From 1eb52fdafdd41c972b404701219b1733325ee7a3 Mon Sep 17 00:00:00 2001 From: LoganSweet Date: Fri, 6 Oct 2017 19:34:04 -0400 Subject: [PATCH 01/28] 1input Mux and and/nand in progress --- alu.v | 42 ++++++++++++++++++++++++++++++++++++++++++ testing.t.v | 26 ++++++++++++++++++++++++++ 2 files changed, 68 insertions(+) create mode 100644 alu.v create mode 100644 testing.t.v diff --git a/alu.v b/alu.v new file mode 100644 index 0000000..8440768 --- /dev/null +++ b/alu.v @@ -0,0 +1,42 @@ +`define AND and #20 // nand with nor is 20 +`define NAND nand #10 // base is 10 +`define NOT not #10 // not base is 10 +`define OR or #20 // nor with not is 20 +`define NOR nor #10 // base is 10 +`define XOR xor #40 // and with or is 40 + +module TwoInMux +( + output out, + input S, + input in0, in1 +); + wire nS; + wire out0; + wire out1; + + `NOT Sinv(nS, S); + `NAND n0(out0, nS, in0); + `NAND n1(out1, S, in1); + `NAND addthem(out, out0, out1); // final output of mux + +endmodule + +module AndNand +( +output AndNandOut, +input A, B, +input[2:0] Command + +); + +wire AnandB; +wire AandB; +//wire[2:0] Command; + + `NAND n0(AnandB, A, B); + `NOT inv0(AandB, AnandB); + TwoInMux potato(AndNandOut, Command[0], A, B); // order to follow out,S,in0, in1 + +endmodule + diff --git a/testing.t.v b/testing.t.v new file mode 100644 index 0000000..ab0013d --- /dev/null +++ b/testing.t.v @@ -0,0 +1,26 @@ +// Intermediate testbench +`timescale 1 ns / 1 ps +`include "alu.v" + +module testMultiplexer (); + +wire AndNandOut; +reg A, B; +reg[2:0] Command; + + AndNand newpotato(AndNandOut, A, B, Command); + +initial begin + + $display("A B| Command |output command?| Expected Output"); + A=1;B=1;Command=3'b000; #1000 + $display("%b %b | %b | %b %b | 1", A, B, Command, Command[0], AndNandOut); + A=1;B=1;Command=3'b000; #1000 + $display("%b %b | %b | %b %b | 0", A, B, Command, Command[1], AndNandOut); + A=1;B=1;Command=3'b000; #1000 + $display("%b %b | %b | %b %b | 0", A, B, Command, Command[2], AndNandOut); + + end + + +endmodule From f48615c9f88e98ff42ad0c7bedcd3a7d161be0ee Mon Sep 17 00:00:00 2001 From: mjakus Date: Sat, 7 Oct 2017 08:07:04 -0400 Subject: [PATCH 02/28] Fixed and/nand, added or/nor/xor --- alu.v | 51 +++++++++++++++++++++++++++++++++++++++++++-------- testing.t.v | 46 +++++++++++++++++++++++++++++++++++++++++----- 2 files changed, 84 insertions(+), 13 deletions(-) diff --git a/alu.v b/alu.v index 8440768..15a0ac3 100644 --- a/alu.v +++ b/alu.v @@ -7,7 +7,7 @@ module TwoInMux ( - output out, + output outfinal, input S, input in0, in1 ); @@ -15,10 +15,16 @@ module TwoInMux wire out0; wire out1; + //`NOT Sinv(nS, S); + //`NAND n0(out0, S, in0); + //`NAND n1(out1, nS, in1); + //`NAND n2(outfinal, out0, out1); // final output of mux + `NOT Sinv(nS, S); - `NAND n0(out0, nS, in0); - `NAND n1(out1, S, in1); - `NAND addthem(out, out0, out1); // final output of mux + `AND andgate1(out0, in0, nS); + `AND andgate3(out1, in1, S); + `OR orgate(outfinal, out0, out1); + endmodule @@ -26,17 +32,46 @@ module AndNand ( output AndNandOut, input A, B, -input[2:0] Command +input[2:0] Command ); wire AnandB; wire AandB; -//wire[2:0] Command; `NAND n0(AnandB, A, B); - `NOT inv0(AandB, AnandB); - TwoInMux potato(AndNandOut, Command[0], A, B); // order to follow out,S,in0, in1 + `NOT Ainv(AandB, AnandB); + TwoInMux potato(AndNandOut, Command[0], AandB, AnandB); // order to follow out,S,in0, in1 endmodule +module OrNorXor +( +output OrNorXorOut, +input A, B, +input[2:0] Command +); +wire AnorB; +wire AorB; +wire AnandB; +wire nXor; +wire AxorB; +wire XorNor; + + `NOR nor0(AnorB, A, B); + `NOT n0(AorB, AnorB); + `NAND and0(AnandB, A, B); + `NAND and1(nXor, AnandB, AorB); + `NOT n1(AxorB, nXor); + + TwoInMux mux0(XorNor, Command[2], AxorB, AnorB); + TwoInMux mux1(OrNorXorOut, Command[0], XorNor, AorB); + + +endmodule + + + + + + diff --git a/testing.t.v b/testing.t.v index ab0013d..14bf3e4 100644 --- a/testing.t.v +++ b/testing.t.v @@ -6,19 +6,55 @@ module testMultiplexer (); wire AndNandOut; reg A, B; -reg[2:0] Command; +reg[2:0] Command; +reg S; AndNand newpotato(AndNandOut, A, B, Command); + OrNorXor ortest(OrNorXorOut, A, B, Command); initial begin - $display("A B| Command |output command?| Expected Output"); +// Exhaustively testing AND/NAND + $display("A B| Command | command0 Output | Expected Output - AND TESTS"); A=1;B=1;Command=3'b000; #1000 $display("%b %b | %b | %b %b | 1", A, B, Command, Command[0], AndNandOut); - A=1;B=1;Command=3'b000; #1000 + A=1;B=1;Command=3'b001; #1000 $display("%b %b | %b | %b %b | 0", A, B, Command, Command[1], AndNandOut); - A=1;B=1;Command=3'b000; #1000 - $display("%b %b | %b | %b %b | 0", A, B, Command, Command[2], AndNandOut); + A=0;B=1;Command=3'b000; #1000 + $display("%b %b | %b | %b %b | 0", A, B, Command, Command[0], AndNandOut); + A=1;B=0;Command=3'b001; #1000 + $display("%b %b | %b | %b %b | 1", A, B, Command, Command[1], AndNandOut); + + +// Exhaustively testing OR/NOR/XOR + $display("A B | Command | Output | Expected Output - OR TESTS"); + A=1; B=1; Command=3'b111; #1000 + $display("%b %b | %b | %b | 1 - OR TEST", A, B, Command, OrNorXorOut); + A=1; B=0; Command=3'b111; #1000 + $display("%b %b | %b | %b | 1 - OR TEST", A, B, Command, OrNorXorOut); + A=0; B=1; Command=3'b111; #1000 + $display("%b %b | %b | %b | 1 - OR TEST", A, B, Command, OrNorXorOut); + A=0; B=0; Command=3'b111; #1000 + $display("%b %b | %b | %b | 0 - OR TEST", A, B, Command, OrNorXorOut); + + + A=1; B=1; Command=3'b110; #1000 + $display("%b %b | %b | %b | 0 - NOR TEST", A, B, Command, OrNorXorOut); + A=1; B=0; Command=3'b110; #1000 + $display("%b %b | %b | %b | 0 - NOR TEST", A, B, Command, OrNorXorOut); + A=0; B=1; Command=3'b110; #1000 + $display("%b %b | %b | %b | 0 - NOR TEST", A, B, Command, OrNorXorOut); + A=0; B=0; Command=3'b110; #1000 + $display("%b %b | %b | %b | 1 - NOR TEST", A, B, Command, OrNorXorOut); + + A=1; B=1; Command=3'b010; #1000 + $display("%b %b | %b | %b | 0 - XOR TEST", A, B, Command, OrNorXorOut); + A=1; B=0; Command=3'b010; #1000 + $display("%b %b | %b | %b | 1 - XOR TEST", A, B, Command, OrNorXorOut); + A=0; B=1; Command=3'b010; #1000 + $display("%b %b | %b | %b | 1 - XOR TEST", A, B, Command, OrNorXorOut); + A=0; B=0; Command=3'b010; #1000 + $display("%b %b | %b | %b | 0 - XOR TEST", A, B, Command, OrNorXorOut); end From 5c95cc15cc8408903b56b7c64ee38a4e21bd121e Mon Sep 17 00:00:00 2001 From: LoganSweet Date: Sat, 7 Oct 2017 17:03:47 -0400 Subject: [PATCH 03/28] AddSubSlt added but incomplete --- alu.v | 78 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 78 insertions(+) diff --git a/alu.v b/alu.v index 15a0ac3..2c5176e 100644 --- a/alu.v +++ b/alu.v @@ -70,7 +70,85 @@ wire XorNor; endmodule +module ZerothAddSubSLT +( +output AddSubSLTSum, carryout, //overflow, +input A, B, +input[2:0] Command, +//input carryin +); + wire nB; + wire BornB; + wire AxorB; + wire AandB; + wire CINandAxorB; + + `NOT Binv(nB, B); + TwoInMux mux0(BornB, Command[0], B, nB); + `XOR XOR1(AxorB, A, BornB); + `XOR XOR2(AddSubSLTSum, AxorB, Command[0]); + `AND AND1(AandB, A, BornB); + `AND AND2(CINandAxorB, AxorB, Command[0]); + `OR OR1(carryout, AandB, CINandAxorB); + +endmodule + +module MiddleAddSubSLT +( +output AddSubSLTSum, carryout, //overflow, +input A, B, +input[2:0] Command, +input carryin +); + wire nB; + wire BornB; + wire AxorB; + wire AandB; + wire CINandAxorB; + + `NOT Binv(nB, B); + TwoInMux mux0(BornB, Command[0], B, nB); + `XOR XOR1(AxorB, A, BornB); + `XOR XOR2(AddSubSLTSum, AxorB, carryin); + `AND AND1(AandB, A, BornB); + `AND AND2(CINandAxorB, AxorB, carryin); + `OR OR1(carryout, AandB, CINandAxorB); + +endmodule + +module LastAddSubSLT +( +output AddSubSLTSum, carryout, overflow, +input A, B, +input[2:0] Command, +input carryin +); + wire nB; + wire BornB; + wire AxorB; + wire AandB; + wire CINandAxorB; + + `NOT Binv(nB, B); + TwoInMux mux0(BornB, Command[0], B, nB); + `XOR XOR1(AxorB, A, BornB); + `XOR XOR2(AddSubSLTSum, AxorB, carryin); + `AND AND1(AandB, A, BornB); + `AND AND2(CINandAxorB, AxorB, carryin); + `OR OR1(carryout, AandB, CINandAxorB); + `XOR xor3(overflow, carryout, carryin); + +endmodule + + +module BitSlice +( + + +); + +endmodule From f260248c94b62247f70a31a003200aa0811e7f95 Mon Sep 17 00:00:00 2001 From: LoganSweet Date: Sat, 7 Oct 2017 19:10:05 -0400 Subject: [PATCH 04/28] full 1 bit attempted; failed --- alu.v | 52 ++++++++++++++++++++++++++++++++++++++++------------ testing.t.v | 24 ++++++++++++++++++++++++ 2 files changed, 64 insertions(+), 12 deletions(-) diff --git a/alu.v b/alu.v index 2c5176e..1fd0b35 100644 --- a/alu.v +++ b/alu.v @@ -24,8 +24,30 @@ module TwoInMux `AND andgate1(out0, in0, nS); `AND andgate3(out1, in1, S); `OR orgate(outfinal, out0, out1); +endmodule + +module FourInMux +( + output out, + input S0, S1, + input in0, in1, in2, in3 +); + wire nS0; + wire nS1; + + wire out0; + wire out1; + wire out2; + wire out3; + `NOT S0inv(nS0, S0); + `NOT S1inv(nS1, S1); + `NAND n0(out0, nS0, nS1, in0); + `NAND n1(out1, S0, nS1, in1); + `NAND n2(out2, nS0, S1, in2); + `NAND n3(out3, S0, S1, in3); + `NAND addthem(out, out0, out1, out2, out3); endmodule module AndNand @@ -41,7 +63,7 @@ wire AandB; `NAND n0(AnandB, A, B); `NOT Ainv(AandB, AnandB); - TwoInMux potato(AndNandOut, Command[0], AandB, AnandB); // order to follow out,S,in0, in1 + TwoInMux potato(AndNandOut, Command[0], AandB, AnandB); // order to follow out,S,in0, in1 endmodule @@ -66,15 +88,13 @@ wire XorNor; TwoInMux mux0(XorNor, Command[2], AxorB, AnorB); TwoInMux mux1(OrNorXorOut, Command[0], XorNor, AorB); - - endmodule module ZerothAddSubSLT ( output AddSubSLTSum, carryout, //overflow, input A, B, -input[2:0] Command, +input[2:0] Command //input carryin ); wire nB; @@ -90,7 +110,6 @@ input[2:0] Command, `AND AND1(AandB, A, BornB); `AND AND2(CINandAxorB, AxorB, Command[0]); `OR OR1(carryout, AandB, CINandAxorB); - endmodule module MiddleAddSubSLT @@ -113,7 +132,6 @@ input carryin `AND AND1(AandB, A, BornB); `AND AND2(CINandAxorB, AxorB, carryin); `OR OR1(carryout, AandB, CINandAxorB); - endmodule module LastAddSubSLT @@ -137,15 +155,25 @@ input carryin `AND AND2(CINandAxorB, AxorB, carryin); `OR OR1(carryout, AandB, CINandAxorB); `XOR xor3(overflow, carryout, carryin); - endmodule - - -module BitSlice + +module Bitslice ( - - +output OneBitFinalOut, +input A, B, +input[2:0] Command, +output AddSubSLTSum, carryout, //overflow, +input carryin, +output OrNorXorOut ); + wire Cmd0Start; + wire Cmd1Start; + + MiddleAddSubSLT rottenpotato(AddSumSLTSum, carryout, A, B, Command, carryin); + OrNorXor idahopotato(OrNorXorOut, A, B, Command); + + FourInMux ZeroMux(Cmd0Start, Command[1], Command[0], AddSumSLTSum, AddSumSLTSum, OrNorXorOut, AddSumSLTSum); + endmodule diff --git a/testing.t.v b/testing.t.v index 14bf3e4..50fdb20 100644 --- a/testing.t.v +++ b/testing.t.v @@ -8,12 +8,36 @@ wire AndNandOut; reg A, B; reg[2:0] Command; reg S; +wire OneBitFinalOut; +wire AddSubSLTSum, carryout; //overflow, +reg carryin; +wire OrNorXorOut; + + +wire muxout; + reg S0, S1; + reg in0, in1, in2, in3; AndNand newpotato(AndNandOut, A, B, Command); OrNorXor ortest(OrNorXorOut, A, B, Command); + + Bitslice yukongoldpotato(OneBitFinalOut, A, B, Command, AddSubSLTSum, carryout, carryin, OrNorXorOut); + + FourInMux arbitrarypotato(muxout, S0, S1, in0, in1, in2, in3); + + initial begin + $display("A B| Command | Output | Expected Output- pure sadness"); + S0 = 1; S1 = 0; in0 = 1; in1 = 1; in2 = 0; in3 = 0; #1000 + $display("%b %b | %b %b %b %b | %b | 1", S0, S1, in0, in1, in2, in3, muxout); + + + $display("A B| Command | Output | Expected Output- pure sadness"); + A=1;B=0;Command=3'b000; #1000 + $display("%b %b | %b | %b | 1", A, B, Command, OneBitFinalOut); + // Exhaustively testing AND/NAND $display("A B| Command | command0 Output | Expected Output - AND TESTS"); A=1;B=1;Command=3'b000; #1000 From d88ff4bec512d789ee00a0b1b61aad5e9eaa7d39 Mon Sep 17 00:00:00 2001 From: mjakus Date: Sat, 7 Oct 2017 20:29:06 -0400 Subject: [PATCH 05/28] Fixed adder/subtractor in bitslice --- alu.v | 23 +++++++++++++---- testing.t.v | 73 +++++++++++++++++++++++++++++++++++++++++++---------- 2 files changed, 78 insertions(+), 18 deletions(-) diff --git a/alu.v b/alu.v index 1fd0b35..8e7014a 100644 --- a/alu.v +++ b/alu.v @@ -160,21 +160,34 @@ endmodule module Bitslice ( output OneBitFinalOut, +output AddSubSLTSum, carryout, //overflow, +output OrNorXorOut, input A, B, input[2:0] Command, -output AddSubSLTSum, carryout, //overflow, -input carryin, -output OrNorXorOut +input carryin + ); wire Cmd0Start; wire Cmd1Start; + wire nB; + wire BornB; + wire AxorB; + wire AandB; + wire CINandAxorB; + + wire AnorB; + wire AorB; + wire AnandB; + wire nXor; + wire XorNor; + MiddleAddSubSLT rottenpotato(AddSumSLTSum, carryout, A, B, Command, carryin); OrNorXor idahopotato(OrNorXorOut, A, B, Command); - FourInMux ZeroMux(Cmd0Start, Command[1], Command[0], AddSumSLTSum, AddSumSLTSum, OrNorXorOut, AddSumSLTSum); - + //FourInMux ZeroMux(Cmd0Start, Command[1], Command[0], AddSumSLTSum, AddSumSLTSum, OrNorXorOut, AddSumSLTSum); + FourInMux ZeroMux(OneBitFinalOut, Command[0], Command[1], AddSumSLTSum, AddSumSLTSum, OrNorXorOut, AddSumSLTSum); endmodule diff --git a/testing.t.v b/testing.t.v index 50fdb20..86e0221 100644 --- a/testing.t.v +++ b/testing.t.v @@ -7,36 +7,83 @@ module testMultiplexer (); wire AndNandOut; reg A, B; reg[2:0] Command; -reg S; +//reg S; wire OneBitFinalOut; wire AddSubSLTSum, carryout; //overflow, reg carryin; wire OrNorXorOut; + //wire muxout; + //reg S0, S1; + //reg in0, in1, in2, in3; -wire muxout; - reg S0, S1; - reg in0, in1, in2, in3; + wire Cmd0Start; + wire Cmd1Start; + + wire nB; + wire BornB; + wire AxorB; + wire AandB; + wire CINandAxorB; + + wire AnorB; + wire AorB; + wire AnandB; + wire nXor; + wire XorNor; + + MiddleAddSubSLT testadd(AddSubSLTSum, carryout, A, B, Command, carryin); AndNand newpotato(AndNandOut, A, B, Command); OrNorXor ortest(OrNorXorOut, A, B, Command); - Bitslice yukongoldpotato(OneBitFinalOut, A, B, Command, AddSubSLTSum, carryout, carryin, OrNorXorOut); + Bitslice yukongoldpotato(OneBitFinalOut, AddSubSLTSum, carryout, OrNorXorOut, A, B, Command, carryin); - FourInMux arbitrarypotato(muxout, S0, S1, in0, in1, in2, in3); + //FourInMux arbitrarypotato(muxout, S0, S1, in0, in1, in2, in3); initial begin - $display("A B| Command | Output | Expected Output- pure sadness"); - S0 = 1; S1 = 0; in0 = 1; in1 = 1; in2 = 0; in3 = 0; #1000 - $display("%b %b | %b %b %b %b | %b | 1", S0, S1, in0, in1, in2, in3, muxout); - +// just the adder - proper behavior + $display("Adder/Subtractor"); + $display("A B| Command | Output | Expected Output"); + A=1;B=1;Command=3'b000; carryin = 0; #1000 + $display("%b %b | %b | %b | 0 | %b", A, B, Command, AddSubSLTSum, carryout); + A=1;B=1;Command=3'b001; carryin = 1; #1000 + $display("%b %b | %b | %b | 0 | %b", A, B, Command, AddSubSLTSum, carryout); + +// testing subtraction + $display("One Bitslice Adder/Subtractor"); + $display("A B| Command |Out|ExOut|Carryout"); + A=1;B=1;Command=3'b000; carryin=0; #1000 + $display("%b %b | %b | %b | 0 | %b", A, B, Command, OneBitFinalOut, carryout); + A=1;B=0;Command=3'b000; carryin=0; #1000 + $display("%b %b | %b | %b | 1 | %b", A, B, Command, OneBitFinalOut, carryout); + A=0;B=0;Command=3'b000; carryin=0; #1000 + $display("%b %b | %b | %b | 0 | %b", A, B, Command, OneBitFinalOut, carryout); + + A=1;B=1;Command=3'b001; carryin=1; #1000 + $display("%b %b | %b | %b | 0 | %b", A, B, Command, OneBitFinalOut, carryout); + A=1;B=0;Command=3'b001; carryin=1; #1000 + $display("%b %b | %b | %b | 1 | %b", A, B, Command, OneBitFinalOut, carryout); + A=0;B=0;Command=3'b001; carryin=1; #1000 + $display("%b %b | %b | %b | 0 | %b", A, B, Command, OneBitFinalOut, carryout); + + + //$display("A B| Command | Output | Expected Output- pure sadness"); + //S0 = 1; S1 = 0; in0 = 1; in1 = 1; in2 = 0; in3 = 0; #1000 + //$display("%b %b | %b %b %b %b | %b | 1", S0, S1, in0, in1, in2, in3, muxout); + +// testing addition + $display("A B| Command | Output | Expected Output-sadness|Carryout"); + A=1;B=1;Command=3'b000; carryin=0; #1000 + $display("%b %b | %b | %b | 0 | %b", A, B, Command, OneBitFinalOut, carryout); + A=1;B=0;Command=3'b000; carryin=0; #1000 + $display("%b %b | %b | %b | 1 | %b", A, B, Command, OneBitFinalOut, carryout); + A=0;B=0;Command=3'b000; carryin=0; #1000 + $display("%b %b | %b | %b | 0 | %b", A, B, Command, OneBitFinalOut, carryout); - $display("A B| Command | Output | Expected Output- pure sadness"); - A=1;B=0;Command=3'b000; #1000 - $display("%b %b | %b | %b | 1", A, B, Command, OneBitFinalOut); // Exhaustively testing AND/NAND $display("A B| Command | command0 Output | Expected Output - AND TESTS"); From e7331432ab81d99827cb0c8b2f88a475a35f1c2e Mon Sep 17 00:00:00 2001 From: mjakus Date: Sun, 8 Oct 2017 16:38:40 -0400 Subject: [PATCH 06/28] Worked on implementing 4 bit adder/subtractor --- OriginalTesting.t.v | 129 ++++++++ alu2.v | 232 +++++++++++++++ test | 698 ++++++++++++++++++++++++++++++++++++++++++++ testing.t.v | 147 ++-------- 4 files changed, 1091 insertions(+), 115 deletions(-) create mode 100644 OriginalTesting.t.v create mode 100644 alu2.v create mode 100755 test diff --git a/OriginalTesting.t.v b/OriginalTesting.t.v new file mode 100644 index 0000000..a48d838 --- /dev/null +++ b/OriginalTesting.t.v @@ -0,0 +1,129 @@ + +module testMultiplexer (); +wire AndNandOut; +reg A, B; +reg[2:0] Command; +//reg S; +wire OneBitFinalOut; +wire AddSubSLTSum, carryout, subtract; //overflow, +reg carryin; +wire OrNorXorOut; + + //wire muxout; + //reg S0, S1; + //reg in0, in1, in2, in3; + + wire Cmd0Start; + wire Cmd1Start; + + wire nB; + wire BornB; + wire AxorB; + wire AandB; + wire CINandAxorB; + + wire AnorB; + wire AorB; + wire AnandB; + wire nXor; + wire XorNor; + + MiddleAddSubSLT testadd(AddSubSLTSum, carryout, subtract, A, B, Command, carryin); + + AndNand newpotato(AndNandOut, A, B, Command); + + OrNorXor ortest(OrNorXorOut, A, B, Command); + + Bitslice yukongoldpotato(OneBitFinalOut, AddSubSLTSum, carryout, OrNorXorOut, AndNandOut, subtract, A, B, Command, carryin); + + +//FourInMux arbitrarypotato(muxout, S0, S1, in0, in1, in2, in3); + +initial begin + +// just the adder - proper behavior + $display("Adder/Subtractor"); + $display("A B| Command | Output | Expected Output"); + A=1;B=1;Command=3'b000; carryin = 0; #1000 + $display("%b %b | %b | %b | 0 | %b", A, B, Command, AddSubSLTSum, carryout); + A=1;B=1;Command=3'b001; carryin = 1; #1000 + $display("%b %b | %b | %b | 0 | %b", A, B, Command, AddSubSLTSum, carryout); + +// testing subtraction + $display("One Bitslice Adder/Subtractor"); + $display("A B| Command |Out|ExOut|Carryout"); + A=1;B=1;Command=3'b000; carryin=0; #1000 + $display("%b %b | %b | %b | 0 | %b", A, B, Command, OneBitFinalOut, carryout); + A=1;B=0;Command=3'b000; carryin=0; #1000 + $display("%b %b | %b | %b | 1 | %b", A, B, Command, OneBitFinalOut, carryout); + A=0;B=0;Command=3'b000; carryin=0; #1000 + $display("%b %b | %b | %b | 0 | %b", A, B, Command, OneBitFinalOut, carryout); + + A=1;B=1;Command=3'b001; carryin=1; #1000 + $display("%b %b | %b | %b | 0 | %b", A, B, Command, OneBitFinalOut, carryout); + A=1;B=0;Command=3'b001; carryin=1; #1000 + $display("%b %b | %b | %b | 1 | %b", A, B, Command, OneBitFinalOut, carryout); + A=0;B=0;Command=3'b001; carryin=1; #1000 + $display("%b %b | %b | %b | 0 | %b", A, B, Command, OneBitFinalOut, carryout); + + + //$display("A B| Command | Output | Expected Output- pure sadness"); + //S0 = 1; S1 = 0; in0 = 1; in1 = 1; in2 = 0; in3 = 0; #1000 + //$display("%b %b | %b %b %b %b | %b | 1", S0, S1, in0, in1, in2, in3, muxout); + +// testing addition + $display("A B| Command | Output | Expected Output-sadness|Carryout"); + A=1;B=1;Command=3'b000; carryin=0; #1000 + $display("%b %b | %b | %b | 0 | %b", A, B, Command, OneBitFinalOut, carryout); + A=1;B=0;Command=3'b000; carryin=0; #1000 + $display("%b %b | %b | %b | 1 | %b", A, B, Command, OneBitFinalOut, carryout); + A=0;B=0;Command=3'b000; carryin=0; #1000 + $display("%b %b | %b | %b | 0 | %b", A, B, Command, OneBitFinalOut, carryout); + + +// Exhaustively testing AND/NAND + $display("A B| Command | command0 Output | Expected Output - AND TESTS"); + A=1;B=1;Command=3'b000; #1000 + $display("%b %b | %b | %b %b | 1", A, B, Command, Command[0], AndNandOut); + A=1;B=1;Command=3'b001; #1000 + $display("%b %b | %b | %b %b | 0", A, B, Command, Command[1], AndNandOut); + A=0;B=1;Command=3'b000; #1000 + $display("%b %b | %b | %b %b | 0", A, B, Command, Command[0], AndNandOut); + A=1;B=0;Command=3'b001; #1000 + $display("%b %b | %b | %b %b | 1", A, B, Command, Command[1], AndNandOut); + + +// Exhaustively testing OR/NOR/XOR + $display("A B | Command | Output | Expected Output - OR TESTS"); + A=1; B=1; Command=3'b111; #1000 + $display("%b %b | %b | %b | 1 - OR TEST", A, B, Command, OrNorXorOut); + A=1; B=0; Command=3'b111; #1000 + $display("%b %b | %b | %b | 1 - OR TEST", A, B, Command, OrNorXorOut); + A=0; B=1; Command=3'b111; #1000 + $display("%b %b | %b | %b | 1 - OR TEST", A, B, Command, OrNorXorOut); + A=0; B=0; Command=3'b111; #1000 + $display("%b %b | %b | %b | 0 - OR TEST", A, B, Command, OrNorXorOut); + + + A=1; B=1; Command=3'b110; #1000 + $display("%b %b | %b | %b | 0 - NOR TEST", A, B, Command, OrNorXorOut); + A=1; B=0; Command=3'b110; #1000 + $display("%b %b | %b | %b | 0 - NOR TEST", A, B, Command, OrNorXorOut); + A=0; B=1; Command=3'b110; #1000 + $display("%b %b | %b | %b | 0 - NOR TEST", A, B, Command, OrNorXorOut); + A=0; B=0; Command=3'b110; #1000 + $display("%b %b | %b | %b | 1 - NOR TEST", A, B, Command, OrNorXorOut); + + A=1; B=1; Command=3'b010; #1000 + $display("%b %b | %b | %b | 0 - XOR TEST", A, B, Command, OrNorXorOut); + A=1; B=0; Command=3'b010; #1000 + $display("%b %b | %b | %b | 1 - XOR TEST", A, B, Command, OrNorXorOut); + A=0; B=1; Command=3'b010; #1000 + $display("%b %b | %b | %b | 1 - XOR TEST", A, B, Command, OrNorXorOut); + A=0; B=0; Command=3'b010; #1000 + $display("%b %b | %b | %b | 0 - XOR TEST", A, B, Command, OrNorXorOut); + + end + + +endmodule diff --git a/alu2.v b/alu2.v new file mode 100644 index 0000000..0140d55 --- /dev/null +++ b/alu2.v @@ -0,0 +1,232 @@ +`define AND and #20 // nand with nor is 20 +`define NAND nand #10 // base is 10 +`define NOT not #10 // not base is 10 +`define OR or #20 // nor with not is 20 +`define NOR nor #10 // base is 10 +`define XOR xor #40 // and with or is 40 + +module TwoInMux +( + output outfinal, + input S, + input in0, in1 +); + wire nS; + wire out0; + wire out1; + + //`NOT Sinv(nS, S); + //`NAND n0(out0, S, in0); + //`NAND n1(out1, nS, in1); + //`NAND n2(outfinal, out0, out1); // final output of mux + + `NOT Sinv(nS, S); + `AND andgate1(out0, in0, nS); + `AND andgate3(out1, in1, S); + `OR orgate(outfinal, out0, out1); +endmodule + +module FourInMux +( + output out, + input S0, S1, + input in0, in1, in2, in3 +); + wire nS0; + wire nS1; + + wire out0; + wire out1; + wire out2; + wire out3; + + `NOT S0inv(nS0, S0); + `NOT S1inv(nS1, S1); + `NAND n0(out0, nS0, nS1, in0); + `NAND n1(out1, S0, nS1, in1); + `NAND n2(out2, nS0, S1, in2); + `NAND n3(out3, S0, S1, in3); + + `NAND addthem(out, out0, out1, out2, out3); +endmodule + +module AndNand +( +output AndNandOut, +input A, B, +input[2:0] Command + +); + +wire AnandB; +wire AandB; + + `NAND n0(AnandB, A, B); + `NOT Ainv(AandB, AnandB); + TwoInMux potato(AndNandOut, Command[0], AandB, AnandB); // order to follow out,S,in0, in1 + +endmodule + +module OrNorXor +( +output OrNorXorOut, +input A, B, +input[2:0] Command +); +wire AnorB; +wire AorB; +wire AnandB; +wire nXor; +wire AxorB; +wire XorNor; + + `NOR nor0(AnorB, A, B); + `NOT n0(AorB, AnorB); + `NAND and0(AnandB, A, B); + `NAND and1(nXor, AnandB, AorB); + `NOT n1(AxorB, nXor); + + TwoInMux mux0(XorNor, Command[2], AxorB, AnorB); + TwoInMux mux1(OrNorXorOut, Command[0], XorNor, AorB); +endmodule + +module ZerothAddSubSLT +( +output AddSubSLTSum, carryout, //overflow, +input A, B, +input[2:0] Command +//input carryin +); + wire nB; + wire BornB; + wire AxorB; + wire AandB; + wire CINandAxorB; + + `NOT Binv(nB, B); + TwoInMux mux0(BornB, Command[0], B, nB); + `XOR XOR1(AxorB, A, BornB); + `XOR XOR2(AddSubSLTSum, AxorB, Command[0]); + `AND AND1(AandB, A, BornB); + `AND AND2(CINandAxorB, AxorB, Command[0]); + `OR OR1(carryout, AandB, CINandAxorB); +endmodule + +module MiddleAddSubSLT +( +output AddSubSLTSum, carryout, //overflow, +output subtract, +input A, B, +input[2:0] Command, +input carryin +); + wire nB; + wire BornB; + wire AxorB; + wire AandB; + wire CINandAxorB; + wire nCmd2; + + `NOT Binv(nB, B); + TwoInMux mux0(BornB, Command[0], B, nB); + `NOT n0(nCmd2, Command[2]); + `AND subtractchoose(subtract, Command[0], nCmd2); + `XOR XOR1(AxorB, A, BornB); + `XOR XOR2(AddSubSLTSum, AxorB, carryin); + `AND AND1(AandB, A, BornB); + `AND AND2(CINandAxorB, AxorB, carryin); + `OR OR1(carryout, AandB, CINandAxorB); +endmodule + +module LastAddSubSLT +( +output AddSubSLTSum, carryout, overflow, +input A, B, +input[2:0] Command, +input carryin +); + wire nB; + wire BornB; + wire AxorB; + wire AandB; + wire CINandAxorB; + + `NOT Binv(nB, B); + TwoInMux mux0(BornB, Command[0], B, nB); + `XOR XOR1(AxorB, A, BornB); + `XOR XOR2(AddSubSLTSum, AxorB, carryin); + `AND AND1(AandB, A, BornB); + `AND AND2(CINandAxorB, AxorB, carryin); + `OR OR1(carryout, AandB, CINandAxorB); + `XOR xor3(overflow, carryout, carryin); +endmodule + +module Bitslice +( +output OneBitFinalOut, +output AddSubSLTSum, carryout, //overflow, +output OrNorXorOut, +output AndNandOut, +output subtract, +input A, B, +input[2:0] Command, +input carryin + +); + wire Cmd0Start; + wire Cmd1Start; + wire nB; + wire BornB; + wire AxorB; + wire AandB; + wire CINandAxorB; + + wire AnorB; + wire AorB; + wire AnandB; + wire nXor; + wire XorNor; + + MiddleAddSubSLT rottenpotato(AddSumSLTSum, carryout, subtract, A, B, Command, carryin); + OrNorXor idahopotato(OrNorXorOut, A, B, Command); + AndNand sweetpotato(AndNandOut, A, B, Command); + + FourInMux ZeroMux(Cmd0Start, Command[0], Command[1], AddSumSLTSum, AddSumSLTSum, OrNorXorOut, AddSumSLTSum); + FourInMux OneMux(Cmd1Start, Command[0], Command[1], AndNandOut, AndNandOut, OrNorXorOut, OrNorXorOut); + TwoInMux TwoMux(OneBitFinalOut, Command[2], Cmd0Start, Cmd1Start); +endmodule + +module AddSubSLT32 +( +output [size-1:0]AddSubSLTSum, +output carryout, +output overflow, +output SLTflag, +output [size-1:0]subtract, +input [size-1:0] A, B, +input [2:0] Command, +input [size-1:0]carryin // we think this doesn't do anything but don't want to break everything +); + wire [size-1:0] CarryoutWire; + wire SLTon; + + MiddleAddSubSLT attempt2(AddSubSLTSum[0], CarryoutWire[0], subtract[0], A[0], B[0], Command, subtract[0]); + + genvar i; + parameter size = 4; + generate + for (i=1; i; 0 drivers +v0x24cf3b0_0 .net "AddSubSLTSum", 0 0, C4; 0 drivers +v0x24cf450_0 .net "AddSumSLTSum", 0 0, L_0x24d7890; 1 drivers +v0x24cf560_0 .net "AndNandOut", 0 0, L_0x24d9560; 1 drivers +v0x24cf670_0 .net "B", 0 0, C4; 0 drivers +v0x24cf780_0 .net "Cmd0Start", 0 0, L_0x24d9df0; 1 drivers +v0x24cf800_0 .net "Cmd1Start", 0 0, L_0x24da880; 1 drivers +v0x24cf880_0 .net "Command", 2 0, C4; 0 drivers +v0x24cf900_0 .net "OneBitFinalOut", 0 0, L_0x24dafe0; 1 drivers +v0x24cf980_0 .net "OrNorXorOut", 0 0, L_0x24d8cb0; 1 drivers +v0x24cfa00_0 .net "carryin", 0 0, C4; 0 drivers +v0x24cfa80_0 .net "carryout", 0 0, L_0x24d7c40; 1 drivers +v0x24cfb00_0 .net "subtract", 0 0, L_0x24d7560; 1 drivers +L_0x24d9fd0 .part C4, 0, 1; +L_0x24da100 .part C4, 1, 1; +L_0x24daa60 .part C4, 0, 1; +L_0x24dab90 .part C4, 1, 1; +L_0x24db110 .part C4, 2, 1; +S_0x24ce2b0 .scope module, "rottenpotato" "MiddleAddSubSLT" 2 190, 2 115, S_0x24a09f0; + .timescale -9 -12; +L_0x24ceec0/d .functor NOT 1, C4, C4<0>, C4<0>, C4<0>; +L_0x24ceec0 .delay (10000,10000,10000) L_0x24ceec0/d; +L_0x24d7420/d .functor NOT 1, L_0x24d74c0, C4<0>, C4<0>, C4<0>; +L_0x24d7420 .delay (10000,10000,10000) L_0x24d7420/d; +L_0x24d7560/d .functor AND 1, L_0x24d76a0, L_0x24d7420, C4<1>, C4<1>; +L_0x24d7560 .delay (20000,20000,20000) L_0x24d7560/d; +L_0x24d7740/d .functor XOR 1, C4, L_0x24d7160, C4<0>, C4<0>; +L_0x24d7740 .delay (40000,40000,40000) L_0x24d7740/d; +L_0x24d7890/d .functor XOR 1, L_0x24d7740, C4, C4<0>, C4<0>; +L_0x24d7890 .delay (40000,40000,40000) L_0x24d7890/d; +L_0x24d79f0/d .functor AND 1, C4, L_0x24d7160, C4<1>, C4<1>; +L_0x24d79f0 .delay (20000,20000,20000) L_0x24d79f0/d; +L_0x24d7b80/d .functor AND 1, L_0x24d7740, C4, C4<1>, C4<1>; +L_0x24d7b80 .delay (20000,20000,20000) L_0x24d7b80/d; +L_0x24d7c40/d .functor OR 1, L_0x24d79f0, L_0x24d7b80, C4<0>, C4<0>; +L_0x24d7c40 .delay (20000,20000,20000) L_0x24d7c40/d; +v0x24ce830_0 .alias "A", 0 0, v0x24cf310_0; +v0x24ce920_0 .net "AandB", 0 0, L_0x24d79f0; 1 drivers +v0x24ce9c0_0 .alias "AddSubSLTSum", 0 0, v0x24cf450_0; +v0x24cea40_0 .net "AxorB", 0 0, L_0x24d7740; 1 drivers +v0x24ceac0_0 .alias "B", 0 0, v0x24cf670_0; +v0x24ceb40_0 .net "BornB", 0 0, L_0x24d7160; 1 drivers +v0x24cec00_0 .net "CINandAxorB", 0 0, L_0x24d7b80; 1 drivers +v0x24cec80_0 .alias "Command", 2 0, v0x24cf880_0; +v0x24ceda0_0 .net *"_s3", 0 0, L_0x24d74c0; 1 drivers +v0x24cee40_0 .net *"_s5", 0 0, L_0x24d76a0; 1 drivers +v0x24cef40_0 .alias "carryin", 0 0, v0x24cfa00_0; +v0x24cefe0_0 .alias "carryout", 0 0, v0x24cfa80_0; +v0x24cf0f0_0 .net "nB", 0 0, L_0x24ceec0; 1 drivers +v0x24cf170_0 .net "nCmd2", 0 0, L_0x24d7420; 1 drivers +v0x24cf270_0 .alias "subtract", 0 0, v0x24cfb00_0; +L_0x24d72f0 .part C4, 0, 1; +L_0x24d74c0 .part C4, 2, 1; +L_0x24d76a0 .part C4, 0, 1; +S_0x24ce3a0 .scope module, "mux0" "TwoInMux" 2 131, 2 8, S_0x24ce2b0; + .timescale -9 -12; +L_0x24d6e80/d .functor NOT 1, L_0x24d72f0, C4<0>, C4<0>, C4<0>; +L_0x24d6e80 .delay (10000,10000,10000) L_0x24d6e80/d; +L_0x24d6f50/d .functor AND 1, C4, L_0x24d6e80, C4<1>, C4<1>; +L_0x24d6f50 .delay (20000,20000,20000) L_0x24d6f50/d; +L_0x24d7070/d .functor AND 1, L_0x24ceec0, L_0x24d72f0, C4<1>, C4<1>; +L_0x24d7070 .delay (20000,20000,20000) L_0x24d7070/d; +L_0x24d7160/d .functor OR 1, L_0x24d6f50, L_0x24d7070, C4<0>, C4<0>; +L_0x24d7160 .delay (20000,20000,20000) L_0x24d7160/d; +v0x24ce490_0 .net "S", 0 0, L_0x24d72f0; 1 drivers +v0x24ce510_0 .alias "in0", 0 0, v0x24cf670_0; +v0x24ce590_0 .alias "in1", 0 0, v0x24cf0f0_0; +v0x24ce610_0 .net "nS", 0 0, L_0x24d6e80; 1 drivers +v0x24ce690_0 .net "out0", 0 0, L_0x24d6f50; 1 drivers +v0x24ce710_0 .net "out1", 0 0, L_0x24d7070; 1 drivers +v0x24ce790_0 .alias "outfinal", 0 0, v0x24ceb40_0; +S_0x24ccfc0 .scope module, "idahopotato" "OrNorXor" 2 191, 2 70, S_0x24a09f0; + .timescale -9 -12; +L_0x24d7dc0/d .functor NOR 1, C4, C4, C4<0>, C4<0>; +L_0x24d7dc0 .delay (10000,10000,10000) L_0x24d7dc0/d; +L_0x24d7f20/d .functor NOT 1, L_0x24d7dc0, C4<0>, C4<0>, C4<0>; +L_0x24d7f20 .delay (10000,10000,10000) L_0x24d7f20/d; +L_0x24d8050/d .functor NAND 1, C4, C4, C4<1>, C4<1>; +L_0x24d8050 .delay (10000,10000,10000) L_0x24d8050/d; +L_0x24d81e0/d .functor NAND 1, L_0x24d8050, L_0x24d7f20, C4<1>, C4<1>; +L_0x24d81e0 .delay (10000,10000,10000) L_0x24d81e0/d; +L_0x24d82d0/d .functor NOT 1, L_0x24d81e0, C4<0>, C4<0>, C4<0>; +L_0x24d82d0 .delay (10000,10000,10000) L_0x24d82d0/d; +v0x24cdb70_0 .alias "A", 0 0, v0x24cf310_0; +v0x24cdc20_0 .net "AnandB", 0 0, L_0x24d8050; 1 drivers +v0x24cdca0_0 .net "AnorB", 0 0, L_0x24d7dc0; 1 drivers +v0x24cdd50_0 .net "AorB", 0 0, L_0x24d7f20; 1 drivers +v0x24cde30_0 .net "AxorB", 0 0, L_0x24d82d0; 1 drivers +v0x24cdee0_0 .alias "B", 0 0, v0x24cf670_0; +v0x24cdfa0_0 .alias "Command", 2 0, v0x24cf880_0; +v0x24ce050_0 .alias "OrNorXorOut", 0 0, v0x24cf980_0; +v0x24ce1b0_0 .net "XorNor", 0 0, L_0x24d8730; 1 drivers +v0x24ce230_0 .net "nXor", 0 0, L_0x24d81e0; 1 drivers +L_0x24d88b0 .part C4, 2, 1; +L_0x24d8e30 .part C4, 0, 1; +S_0x24cd600 .scope module, "mux0" "TwoInMux" 2 89, 2 8, S_0x24ccfc0; + .timescale -9 -12; +L_0x24d8410/d .functor NOT 1, L_0x24d88b0, C4<0>, C4<0>, C4<0>; +L_0x24d8410 .delay (10000,10000,10000) L_0x24d8410/d; +L_0x24d84d0/d .functor AND 1, L_0x24d82d0, L_0x24d8410, C4<1>, C4<1>; +L_0x24d84d0 .delay (20000,20000,20000) L_0x24d84d0/d; +L_0x24d85e0/d .functor AND 1, L_0x24d7dc0, L_0x24d88b0, C4<1>, C4<1>; +L_0x24d85e0 .delay (20000,20000,20000) L_0x24d85e0/d; +L_0x24d8730/d .functor OR 1, L_0x24d84d0, L_0x24d85e0, C4<0>, C4<0>; +L_0x24d8730 .delay (20000,20000,20000) L_0x24d8730/d; +v0x24cd6f0_0 .net "S", 0 0, L_0x24d88b0; 1 drivers +v0x24cd7b0_0 .alias "in0", 0 0, v0x24cde30_0; +v0x24cd850_0 .alias "in1", 0 0, v0x24cdca0_0; +v0x24cd8f0_0 .net "nS", 0 0, L_0x24d8410; 1 drivers +v0x24cd970_0 .net "out0", 0 0, L_0x24d84d0; 1 drivers +v0x24cda10_0 .net "out1", 0 0, L_0x24d85e0; 1 drivers +v0x24cdaf0_0 .alias "outfinal", 0 0, v0x24ce1b0_0; +S_0x24cd0b0 .scope module, "mux1" "TwoInMux" 2 90, 2 8, S_0x24ccfc0; + .timescale -9 -12; +L_0x24d8950/d .functor NOT 1, L_0x24d8e30, C4<0>, C4<0>, C4<0>; +L_0x24d8950 .delay (10000,10000,10000) L_0x24d8950/d; +L_0x24d8a10/d .functor AND 1, L_0x24d8730, L_0x24d8950, C4<1>, C4<1>; +L_0x24d8a10 .delay (20000,20000,20000) L_0x24d8a10/d; +L_0x24d8b60/d .functor AND 1, L_0x24d7f20, L_0x24d8e30, C4<1>, C4<1>; +L_0x24d8b60 .delay (20000,20000,20000) L_0x24d8b60/d; +L_0x24d8cb0/d .functor OR 1, L_0x24d8a10, L_0x24d8b60, C4<0>, C4<0>; +L_0x24d8cb0 .delay (20000,20000,20000) L_0x24d8cb0/d; +v0x24cd1a0_0 .net "S", 0 0, L_0x24d8e30; 1 drivers +v0x24cd240_0 .alias "in0", 0 0, v0x24ce1b0_0; +v0x24cd2e0_0 .alias "in1", 0 0, v0x24cdd50_0; +v0x24cd380_0 .net "nS", 0 0, L_0x24d8950; 1 drivers +v0x24cd400_0 .net "out0", 0 0, L_0x24d8a10; 1 drivers +v0x24cd4a0_0 .net "out1", 0 0, L_0x24d8b60; 1 drivers +v0x24cd580_0 .alias "outfinal", 0 0, v0x24cf980_0; +S_0x24cc620 .scope module, "sweetpotato" "AndNand" 2 192, 2 53, S_0x24a09f0; + .timescale -9 -12; +L_0x24d7390/d .functor NAND 1, C4, C4, C4<1>, C4<1>; +L_0x24d7390 .delay (10000,10000,10000) L_0x24d7390/d; +L_0x24d9110/d .functor NOT 1, L_0x24d7390, C4<0>, C4<0>, C4<0>; +L_0x24d9110 .delay (10000,10000,10000) L_0x24d9110/d; +v0x24ccc40_0 .alias "A", 0 0, v0x24cf310_0; +v0x24ccd00_0 .net "AandB", 0 0, L_0x24d9110; 1 drivers +v0x24ccd80_0 .net "AnandB", 0 0, L_0x24d7390; 1 drivers +v0x24cce00_0 .alias "AndNandOut", 0 0, v0x24cf560_0; +v0x24cce80_0 .alias "B", 0 0, v0x24cf670_0; +v0x24ccf00_0 .alias "Command", 2 0, v0x24cf880_0; +L_0x24d96e0 .part C4, 0, 1; +S_0x24cc710 .scope module, "potato" "TwoInMux" 2 66, 2 8, S_0x24cc620; + .timescale -9 -12; +L_0x24d9240/d .functor NOT 1, L_0x24d96e0, C4<0>, C4<0>, C4<0>; +L_0x24d9240 .delay (10000,10000,10000) L_0x24d9240/d; +L_0x24d9300/d .functor AND 1, L_0x24d9110, L_0x24d9240, C4<1>, C4<1>; +L_0x24d9300 .delay (20000,20000,20000) L_0x24d9300/d; +L_0x24d9410/d .functor AND 1, L_0x24d7390, L_0x24d96e0, C4<1>, C4<1>; +L_0x24d9410 .delay (20000,20000,20000) L_0x24d9410/d; +L_0x24d9560/d .functor OR 1, L_0x24d9300, L_0x24d9410, C4<0>, C4<0>; +L_0x24d9560 .delay (20000,20000,20000) L_0x24d9560/d; +v0x24cc800_0 .net "S", 0 0, L_0x24d96e0; 1 drivers +v0x24cc8c0_0 .alias "in0", 0 0, v0x24ccd00_0; +v0x24cc960_0 .alias "in1", 0 0, v0x24ccd80_0; +v0x24cca00_0 .net "nS", 0 0, L_0x24d9240; 1 drivers +v0x24cca80_0 .net "out0", 0 0, L_0x24d9300; 1 drivers +v0x24ccb20_0 .net "out1", 0 0, L_0x24d9410; 1 drivers +v0x24ccbc0_0 .alias "outfinal", 0 0, v0x24cf560_0; +S_0x24cbc60 .scope module, "ZeroMux" "FourInMux" 2 194, 2 29, S_0x24a09f0; + .timescale -9 -12; +L_0x24d9780/d .functor NOT 1, L_0x24d9fd0, C4<0>, C4<0>, C4<0>; +L_0x24d9780 .delay (10000,10000,10000) L_0x24d9780/d; +L_0x24d9840/d .functor NOT 1, L_0x24da100, C4<0>, C4<0>, C4<0>; +L_0x24d9840 .delay (10000,10000,10000) L_0x24d9840/d; +L_0x24d9900/d .functor NAND 1, L_0x24d9780, L_0x24d9840, L_0x24d7890, C4<1>; +L_0x24d9900 .delay (10000,10000,10000) L_0x24d9900/d; +L_0x24d9a40/d .functor NAND 1, L_0x24d9fd0, L_0x24d9840, L_0x24d7890, C4<1>; +L_0x24d9a40 .delay (10000,10000,10000) L_0x24d9a40/d; +L_0x24d9b30/d .functor NAND 1, L_0x24d9780, L_0x24da100, L_0x24d8cb0, C4<1>; +L_0x24d9b30 .delay (10000,10000,10000) L_0x24d9b30/d; +L_0x24d9c50/d .functor NAND 1, L_0x24d9fd0, L_0x24da100, L_0x24d7890, C4<1>; +L_0x24d9c50 .delay (10000,10000,10000) L_0x24d9c50/d; +L_0x24d9df0/d .functor NAND 1, L_0x24d9900, L_0x24d9a40, L_0x24d9b30, L_0x24d9c50; +L_0x24d9df0 .delay (10000,10000,10000) L_0x24d9df0/d; +v0x24cbd50_0 .net "S0", 0 0, L_0x24d9fd0; 1 drivers +v0x24cbe10_0 .net "S1", 0 0, L_0x24da100; 1 drivers +v0x24cbeb0_0 .alias "in0", 0 0, v0x24cf450_0; +v0x24cbf50_0 .alias "in1", 0 0, v0x24cf450_0; +v0x24cc030_0 .alias "in2", 0 0, v0x24cf980_0; +v0x24cc0b0_0 .alias "in3", 0 0, v0x24cf450_0; +v0x24cc180_0 .net "nS0", 0 0, L_0x24d9780; 1 drivers +v0x24cc200_0 .net "nS1", 0 0, L_0x24d9840; 1 drivers +v0x24cc2d0_0 .alias "out", 0 0, v0x24cf780_0; +v0x24cc350_0 .net "out0", 0 0, L_0x24d9900; 1 drivers +v0x24cc3d0_0 .net "out1", 0 0, L_0x24d9a40; 1 drivers +v0x24cc470_0 .net "out2", 0 0, L_0x24d9b30; 1 drivers +v0x24cc580_0 .net "out3", 0 0, L_0x24d9c50; 1 drivers +S_0x24cb250 .scope module, "OneMux" "FourInMux" 2 195, 2 29, S_0x24a09f0; + .timescale -9 -12; +L_0x24da230/d .functor NOT 1, L_0x24daa60, C4<0>, C4<0>, C4<0>; +L_0x24da230 .delay (10000,10000,10000) L_0x24da230/d; +L_0x24da2f0/d .functor NOT 1, L_0x24dab90, C4<0>, C4<0>, C4<0>; +L_0x24da2f0 .delay (10000,10000,10000) L_0x24da2f0/d; +L_0x24da3b0/d .functor NAND 1, L_0x24da230, L_0x24da2f0, L_0x24d9560, C4<1>; +L_0x24da3b0 .delay (10000,10000,10000) L_0x24da3b0/d; +L_0x24da4b0/d .functor NAND 1, L_0x24daa60, L_0x24da2f0, L_0x24d9560, C4<1>; +L_0x24da4b0 .delay (10000,10000,10000) L_0x24da4b0/d; +L_0x24da5a0/d .functor NAND 1, L_0x24da230, L_0x24dab90, L_0x24d8cb0, C4<1>; +L_0x24da5a0 .delay (10000,10000,10000) L_0x24da5a0/d; +L_0x24da770/d .functor NAND 1, L_0x24daa60, L_0x24dab90, L_0x24d8cb0, C4<1>; +L_0x24da770 .delay (10000,10000,10000) L_0x24da770/d; +L_0x24da880/d .functor NAND 1, L_0x24da3b0, L_0x24da4b0, L_0x24da5a0, L_0x24da770; +L_0x24da880 .delay (10000,10000,10000) L_0x24da880/d; +v0x24cb340_0 .net "S0", 0 0, L_0x24daa60; 1 drivers +v0x24cb400_0 .net "S1", 0 0, L_0x24dab90; 1 drivers +v0x24cb4a0_0 .alias "in0", 0 0, v0x24cf560_0; +v0x24cb540_0 .alias "in1", 0 0, v0x24cf560_0; +v0x24cb5f0_0 .alias "in2", 0 0, v0x24cf980_0; +v0x24cb670_0 .alias "in3", 0 0, v0x24cf980_0; +v0x24cb730_0 .net "nS0", 0 0, L_0x24da230; 1 drivers +v0x24cb7b0_0 .net "nS1", 0 0, L_0x24da2f0; 1 drivers +v0x24cb880_0 .alias "out", 0 0, v0x24cf800_0; +v0x24cb930_0 .net "out0", 0 0, L_0x24da3b0; 1 drivers +v0x24cba10_0 .net "out1", 0 0, L_0x24da4b0; 1 drivers +v0x24cbab0_0 .net "out2", 0 0, L_0x24da5a0; 1 drivers +v0x24cbbc0_0 .net "out3", 0 0, L_0x24da770; 1 drivers +S_0x24a8eb0 .scope module, "TwoMux" "TwoInMux" 2 196, 2 8, S_0x24a09f0; + .timescale -9 -12; +L_0x24dacc0/d .functor NOT 1, L_0x24db110, C4<0>, C4<0>, C4<0>; +L_0x24dacc0 .delay (10000,10000,10000) L_0x24dacc0/d; +L_0x24dad60/d .functor AND 1, L_0x24d9df0, L_0x24dacc0, C4<1>, C4<1>; +L_0x24dad60 .delay (20000,20000,20000) L_0x24dad60/d; +L_0x24dae90/d .functor AND 1, L_0x24da880, L_0x24db110, C4<1>, C4<1>; +L_0x24dae90 .delay (20000,20000,20000) L_0x24dae90/d; +L_0x24dafe0/d .functor OR 1, L_0x24dad60, L_0x24dae90, C4<0>, C4<0>; +L_0x24dafe0 .delay (20000,20000,20000) L_0x24dafe0/d; +v0x247c1d0_0 .net "S", 0 0, L_0x24db110; 1 drivers +v0x24cae40_0 .alias "in0", 0 0, v0x24cf780_0; +v0x24caee0_0 .alias "in1", 0 0, v0x24cf800_0; +v0x24caf80_0 .net "nS", 0 0, L_0x24dacc0; 1 drivers +v0x24cb030_0 .net "out0", 0 0, L_0x24dad60; 1 drivers +v0x24cb0d0_0 .net "out1", 0 0, L_0x24dae90; 1 drivers +v0x24cb1b0_0 .alias "outfinal", 0 0, v0x24cf900_0; +S_0x24a9dd0 .scope module, "LastAddSubSLT" "LastAddSubSLT" 2 141; + .timescale -9 -12; +L_0x24db1b0/d .functor NOT 1, C4, C4<0>, C4<0>, C4<0>; +L_0x24db1b0 .delay (10000,10000,10000) L_0x24db1b0/d; +L_0x24db880/d .functor XOR 1, C4, L_0x24db610, C4<0>, C4<0>; +L_0x24db880 .delay (40000,40000,40000) L_0x24db880/d; +L_0x24db920/d .functor XOR 1, L_0x24db880, C4, C4<0>, C4<0>; +L_0x24db920 .delay (40000,40000,40000) L_0x24db920/d; +L_0x24dba10/d .functor AND 1, C4, L_0x24db610, C4<1>, C4<1>; +L_0x24dba10 .delay (20000,20000,20000) L_0x24dba10/d; +L_0x24dbb40/d .functor AND 1, L_0x24db880, C4, C4<1>, C4<1>; +L_0x24dbb40 .delay (20000,20000,20000) L_0x24dbb40/d; +L_0x24dbc60/d .functor OR 1, L_0x24dba10, L_0x24dbb40, C4<0>, C4<0>; +L_0x24dbc60 .delay (20000,20000,20000) L_0x24dbc60/d; +L_0x24dbe00/d .functor XOR 1, L_0x24dbc60, C4, C4<0>, C4<0>; +L_0x24dbe00 .delay (40000,40000,40000) L_0x24dbe00/d; +v0x24d0060_0 .net "A", 0 0, C4; 0 drivers +v0x24d0120_0 .net "AandB", 0 0, L_0x24dba10; 1 drivers +v0x24d01c0_0 .net "AddSubSLTSum", 0 0, L_0x24db920; 1 drivers +v0x24d0260_0 .net "AxorB", 0 0, L_0x24db880; 1 drivers +v0x24d02e0_0 .net "B", 0 0, C4; 0 drivers +v0x24d0390_0 .net "BornB", 0 0, L_0x24db610; 1 drivers +v0x24d0450_0 .net "CINandAxorB", 0 0, L_0x24dbb40; 1 drivers +v0x24d04d0_0 .net "Command", 2 0, C4; 0 drivers +v0x24d0550_0 .net "carryin", 0 0, C4; 0 drivers +v0x24d05f0_0 .net "carryout", 0 0, L_0x24dbc60; 1 drivers +v0x24d0690_0 .net "nB", 0 0, L_0x24db1b0; 1 drivers +v0x24d0740_0 .net "overflow", 0 0, L_0x24dbe00; 1 drivers +L_0x24db7e0 .part C4, 0, 1; +S_0x24cfb80 .scope module, "mux0" "TwoInMux" 2 155, 2 8, S_0x24a9dd0; + .timescale -9 -12; +L_0x24db330/d .functor NOT 1, L_0x24db7e0, C4<0>, C4<0>, C4<0>; +L_0x24db330 .delay (10000,10000,10000) L_0x24db330/d; +L_0x24db3f0/d .functor AND 1, C4, L_0x24db330, C4<1>, C4<1>; +L_0x24db3f0 .delay (20000,20000,20000) L_0x24db3f0/d; +L_0x24db500/d .functor AND 1, L_0x24db1b0, L_0x24db7e0, C4<1>, C4<1>; +L_0x24db500 .delay (20000,20000,20000) L_0x24db500/d; +L_0x24db610/d .functor OR 1, L_0x24db3f0, L_0x24db500, C4<0>, C4<0>; +L_0x24db610 .delay (20000,20000,20000) L_0x24db610/d; +v0x24cfc70_0 .net "S", 0 0, L_0x24db7e0; 1 drivers +v0x24cfcf0_0 .alias "in0", 0 0, v0x24d02e0_0; +v0x24cfd70_0 .alias "in1", 0 0, v0x24d0690_0; +v0x24cfdf0_0 .net "nS", 0 0, L_0x24db330; 1 drivers +v0x24cfea0_0 .net "out0", 0 0, L_0x24db3f0; 1 drivers +v0x24cff20_0 .net "out1", 0 0, L_0x24db500; 1 drivers +v0x24cffc0_0 .alias "outfinal", 0 0, v0x24d0390_0; +S_0x24a9b60 .scope module, "ZerothAddSubSLT" "ZerothAddSubSLT" 2 93; + .timescale -9 -12; +L_0x24dbf10/d .functor NOT 1, C4, C4<0>, C4<0>, C4<0>; +L_0x24dbf10 .delay (10000,10000,10000) L_0x24dbf10/d; +L_0x24dc600/d .functor XOR 1, C4, L_0x24dc390, C4<0>, C4<0>; +L_0x24dc600 .delay (40000,40000,40000) L_0x24dc600/d; +L_0x24dc6a0/d .functor XOR 1, L_0x24dc600, L_0x24dc790, C4<0>, C4<0>; +L_0x24dc6a0 .delay (40000,40000,40000) L_0x24dc6a0/d; +L_0x24dc880/d .functor AND 1, C4, L_0x24dc390, C4<1>, C4<1>; +L_0x24dc880 .delay (20000,20000,20000) L_0x24dc880/d; +L_0x24dca00/d .functor AND 1, L_0x24dc600, L_0x24dcaa0, C4<1>, C4<1>; +L_0x24dca00 .delay (20000,20000,20000) L_0x24dca00/d; +L_0x24dcb40/d .functor OR 1, L_0x24dc880, L_0x24dca00, C4<0>, C4<0>; +L_0x24dcb40 .delay (20000,20000,20000) L_0x24dcb40/d; +v0x24d0db0_0 .net "A", 0 0, C4; 0 drivers +v0x24d0e70_0 .net "AandB", 0 0, L_0x24dc880; 1 drivers +v0x24d0f10_0 .net "AddSubSLTSum", 0 0, L_0x24dc6a0; 1 drivers +v0x24d0fb0_0 .net "AxorB", 0 0, L_0x24dc600; 1 drivers +v0x24d1030_0 .net "B", 0 0, C4; 0 drivers +v0x24d10e0_0 .net "BornB", 0 0, L_0x24dc390; 1 drivers +v0x24d11a0_0 .net "CINandAxorB", 0 0, L_0x24dca00; 1 drivers +v0x24d1220_0 .net "Command", 2 0, C4; 0 drivers +v0x24d12a0_0 .net *"_s3", 0 0, L_0x24dc790; 1 drivers +v0x24d1340_0 .net *"_s5", 0 0, L_0x24dcaa0; 1 drivers +v0x24d13e0_0 .net "carryout", 0 0, L_0x24dcb40; 1 drivers +v0x24d1480_0 .net "nB", 0 0, L_0x24dbf10; 1 drivers +L_0x24dc560 .part C4, 0, 1; +L_0x24dc790 .part C4, 0, 1; +L_0x24dcaa0 .part C4, 0, 1; +S_0x24d0830 .scope module, "mux0" "TwoInMux" 2 107, 2 8, S_0x24a9b60; + .timescale -9 -12; +L_0x24dc0b0/d .functor NOT 1, L_0x24dc560, C4<0>, C4<0>, C4<0>; +L_0x24dc0b0 .delay (10000,10000,10000) L_0x24dc0b0/d; +L_0x24dc170/d .functor AND 1, C4, L_0x24dc0b0, C4<1>, C4<1>; +L_0x24dc170 .delay (20000,20000,20000) L_0x24dc170/d; +L_0x24dc280/d .functor AND 1, L_0x24dbf10, L_0x24dc560, C4<1>, C4<1>; +L_0x24dc280 .delay (20000,20000,20000) L_0x24dc280/d; +L_0x24dc390/d .functor OR 1, L_0x24dc170, L_0x24dc280, C4<0>, C4<0>; +L_0x24dc390 .delay (20000,20000,20000) L_0x24dc390/d; +v0x24d0920_0 .net "S", 0 0, L_0x24dc560; 1 drivers +v0x24d09e0_0 .alias "in0", 0 0, v0x24d1030_0; +v0x24d0a80_0 .alias "in1", 0 0, v0x24d1480_0; +v0x24d0b20_0 .net "nS", 0 0, L_0x24dc0b0; 1 drivers +v0x24d0bd0_0 .net "out0", 0 0, L_0x24dc170; 1 drivers +v0x24d0c70_0 .net "out1", 0 0, L_0x24dc280; 1 drivers +v0x24d0d10_0 .alias "outfinal", 0 0, v0x24d10e0_0; +S_0x24a9430 .scope module, "test32Adder" "test32Adder" 3 5; + .timescale -9 -12; +P_0x2488d08 .param/l "size" 3 7, +C4<0100>; +v0x24d6840_0 .var "A", 3 0; +RS_0x7f03c2c9b028 .resolv tri, L_0x24ddd90, L_0x24df410, L_0x24e08e0, L_0x24e20e0; +v0x24d68e0_0 .net8 "AddSubSLTSum", 3 0, RS_0x7f03c2c9b028; 4 drivers +v0x24d6990_0 .var "B", 3 0; +v0x24d6a40_0 .var "Command", 2 0; +v0x24d6af0_0 .net "SLTflag", 0 0, L_0x24e2b00; 1 drivers +v0x24d6ba0_0 .var "carryin", 3 0; +v0x24d6c20_0 .net "carryout", 0 0, L_0x24e2460; 1 drivers +v0x24d6cd0_0 .net "overflow", 0 0, L_0x24e2920; 1 drivers +RS_0x7f03c2c9b2c8 .resolv tri, L_0x24ddfe0, L_0x24df640, L_0x24e0b80, L_0x24e10d0; +v0x24d6d80_0 .net8 "subtract", 3 0, RS_0x7f03c2c9b2c8; 4 drivers +S_0x24d15a0 .scope module, "trial" "AddSubSLT32" 3 18, 2 199, S_0x24a9430; + .timescale -9 -12; +P_0x24d1168 .param/l "size" 2 216, +C4<0100>; +L_0x24e2460/d .functor OR 1, L_0x24e2770, C4<0>, C4<0>, C4<0>; +L_0x24e2460 .delay (20000,20000,20000) L_0x24e2460/d; +L_0x24e2920/d .functor XOR 1, L_0x24e2460, L_0x24e2a60, C4<0>, C4<0>; +L_0x24e2920 .delay (40000,40000,40000) L_0x24e2920/d; +L_0x24e2650/d .functor AND 1, L_0x24e2c30, L_0x24e2cd0, C4<1>, C4<1>; +L_0x24e2650 .delay (20000,20000,20000) L_0x24e2650/d; +L_0x24e2b00/d .functor AND 1, L_0x24e2650, L_0x24e2f90, C4<1>, C4<1>; +L_0x24e2b00 .delay (20000,20000,20000) L_0x24e2b00/d; +v0x24d5c70_0 .net "A", 3 0, v0x24d6840_0; 1 drivers +v0x24d5d30_0 .alias "AddSubSLTSum", 3 0, v0x24d68e0_0; +v0x24d5dd0_0 .net "B", 3 0, v0x24d6990_0; 1 drivers +RS_0x7f03c2c9b088 .resolv tri, L_0x24ddef0, L_0x24df500, L_0x24e0a10, L_0x24e21d0; +v0x24d5e70_0 .net8 "CarryoutWire", 3 0, RS_0x7f03c2c9b088; 4 drivers +v0x24d5f20_0 .net "Command", 2 0, v0x24d6a40_0; 1 drivers +v0x24d6030_0 .alias "SLTflag", 0 0, v0x24d6af0_0; +v0x24d60d0_0 .net "SLTon", 0 0, L_0x24e2650; 1 drivers +v0x24d6170_0 .net *"_s40", 0 0, L_0x24e2770; 1 drivers +v0x24d6210_0 .net/s *"_s41", 0 0, C4<0>; 1 drivers +v0x24d62b0_0 .net *"_s44", 0 0, L_0x24e2a60; 1 drivers +v0x24d6350_0 .net *"_s46", 0 0, L_0x24e2c30; 1 drivers +v0x24d63f0_0 .net *"_s48", 0 0, L_0x24e2cd0; 1 drivers +v0x24d6490_0 .net *"_s50", 0 0, L_0x24e2f90; 1 drivers +v0x24d6530_0 .net "carryin", 3 0, v0x24d6ba0_0; 1 drivers +v0x24d6650_0 .alias "carryout", 0 0, v0x24d6c20_0; +v0x24d66f0_0 .alias "overflow", 0 0, v0x24d6cd0_0; +v0x24d65b0_0 .alias "subtract", 3 0, v0x24d6d80_0; +L_0x24ddd90 .part/pv L_0x24dd8e0, 1, 1, 4; +L_0x24ddef0 .part/pv L_0x24ddc30, 1, 1, 4; +L_0x24ddfe0 .part/pv L_0x24dd560, 1, 1, 4; +L_0x24de120 .part v0x24d6840_0, 1, 1; +L_0x24de210 .part v0x24d6990_0, 1, 1; +L_0x24de340 .part RS_0x7f03c2c9b088, 0, 1; +L_0x24df410 .part/pv L_0x24def60, 2, 1, 4; +L_0x24df500 .part/pv L_0x24df2b0, 2, 1, 4; +L_0x24df640 .part/pv L_0x24dec90, 2, 1, 4; +L_0x24df730 .part v0x24d6840_0, 2, 1; +L_0x24df830 .part v0x24d6990_0, 2, 1; +L_0x24df960 .part RS_0x7f03c2c9b088, 1, 1; +L_0x24e08e0 .part/pv L_0x24e0430, 3, 1, 4; +L_0x24e0a10 .part/pv L_0x24e0780, 3, 1, 4; +L_0x24e0b80 .part/pv L_0x24e0160, 3, 1, 4; +L_0x24e0cb0 .part v0x24d6840_0, 3, 1; +L_0x24e0e70 .part v0x24d6990_0, 3, 1; +L_0x24e1030 .part RS_0x7f03c2c9b088, 2, 1; +L_0x24e20e0 .part/pv L_0x24e1c50, 0, 1, 4; +L_0x24e21d0 .part/pv L_0x24e1fa0, 0, 1, 4; +L_0x24e10d0 .part/pv L_0x24dd740, 0, 1, 4; +L_0x24e23c0 .part v0x24d6840_0, 0, 1; +L_0x24e22c0 .part v0x24d6990_0, 0, 1; +L_0x24e25b0 .part RS_0x7f03c2c9b2c8, 0, 1; +L_0x24e2770 .part RS_0x7f03c2c9b088, 3, 1; +L_0x24e2a60 .part RS_0x7f03c2c9b088, 2, 1; +L_0x24e2c30 .part v0x24d6a40_0, 1, 1; +L_0x24e2cd0 .part RS_0x7f03c2c9b2c8, 0, 1; +L_0x24e2f90 .part RS_0x7f03c2c9b028, 3, 1; +S_0x24d4c60 .scope module, "attempt2" "MiddleAddSubSLT" 2 213, 2 115, S_0x24d15a0; + .timescale -9 -12; +L_0x24e0de0/d .functor NOT 1, L_0x24e22c0, C4<0>, C4<0>, C4<0>; +L_0x24e0de0 .delay (10000,10000,10000) L_0x24e0de0/d; +L_0x24e1700/d .functor NOT 1, L_0x24e17c0, C4<0>, C4<0>, C4<0>; +L_0x24e1700 .delay (10000,10000,10000) L_0x24e1700/d; +L_0x24dd740/d .functor AND 1, L_0x24e1ac0, L_0x24e1700, C4<1>, C4<1>; +L_0x24dd740 .delay (20000,20000,20000) L_0x24dd740/d; +L_0x24e1b60/d .functor XOR 1, L_0x24e23c0, L_0x24e1490, C4<0>, C4<0>; +L_0x24e1b60 .delay (40000,40000,40000) L_0x24e1b60/d; +L_0x24e1c50/d .functor XOR 1, L_0x24e1b60, L_0x24e25b0, C4<0>, C4<0>; +L_0x24e1c50 .delay (40000,40000,40000) L_0x24e1c50/d; +L_0x24e1d40/d .functor AND 1, L_0x24e23c0, L_0x24e1490, C4<1>, C4<1>; +L_0x24e1d40 .delay (20000,20000,20000) L_0x24e1d40/d; +L_0x24e1eb0/d .functor AND 1, L_0x24e1b60, L_0x24e25b0, C4<1>, C4<1>; +L_0x24e1eb0 .delay (20000,20000,20000) L_0x24e1eb0/d; +L_0x24e1fa0/d .functor OR 1, L_0x24e1d40, L_0x24e1eb0, C4<0>, C4<0>; +L_0x24e1fa0 .delay (20000,20000,20000) L_0x24e1fa0/d; +v0x24d52d0_0 .net "A", 0 0, L_0x24e23c0; 1 drivers +v0x24d5390_0 .net "AandB", 0 0, L_0x24e1d40; 1 drivers +v0x24d5430_0 .net "AddSubSLTSum", 0 0, L_0x24e1c50; 1 drivers +v0x24d54d0_0 .net "AxorB", 0 0, L_0x24e1b60; 1 drivers +v0x24d5550_0 .net "B", 0 0, L_0x24e22c0; 1 drivers +v0x24d5600_0 .net "BornB", 0 0, L_0x24e1490; 1 drivers +v0x24d56c0_0 .net "CINandAxorB", 0 0, L_0x24e1eb0; 1 drivers +v0x24d5740_0 .alias "Command", 2 0, v0x24d5f20_0; +v0x24d57c0_0 .net *"_s3", 0 0, L_0x24e17c0; 1 drivers +v0x24d5840_0 .net *"_s5", 0 0, L_0x24e1ac0; 1 drivers +v0x24d58e0_0 .net "carryin", 0 0, L_0x24e25b0; 1 drivers +v0x24d5980_0 .net "carryout", 0 0, L_0x24e1fa0; 1 drivers +v0x24d5a20_0 .net "nB", 0 0, L_0x24e0de0; 1 drivers +v0x24d5ad0_0 .net "nCmd2", 0 0, L_0x24e1700; 1 drivers +v0x24d5bd0_0 .net "subtract", 0 0, L_0x24dd740; 1 drivers +L_0x24e1660 .part v0x24d6a40_0, 0, 1; +L_0x24e17c0 .part v0x24d6a40_0, 2, 1; +L_0x24e1ac0 .part v0x24d6a40_0, 0, 1; +S_0x24d4d50 .scope module, "mux0" "TwoInMux" 2 131, 2 8, S_0x24d4c60; + .timescale -9 -12; +L_0x24e11b0/d .functor NOT 1, L_0x24e1660, C4<0>, C4<0>, C4<0>; +L_0x24e11b0 .delay (10000,10000,10000) L_0x24e11b0/d; +L_0x24e1270/d .functor AND 1, L_0x24e22c0, L_0x24e11b0, C4<1>, C4<1>; +L_0x24e1270 .delay (20000,20000,20000) L_0x24e1270/d; +L_0x24e1380/d .functor AND 1, L_0x24e0de0, L_0x24e1660, C4<1>, C4<1>; +L_0x24e1380 .delay (20000,20000,20000) L_0x24e1380/d; +L_0x24e1490/d .functor OR 1, L_0x24e1270, L_0x24e1380, C4<0>, C4<0>; +L_0x24e1490 .delay (20000,20000,20000) L_0x24e1490/d; +v0x24d4e40_0 .net "S", 0 0, L_0x24e1660; 1 drivers +v0x24d4f00_0 .alias "in0", 0 0, v0x24d5550_0; +v0x24d4fa0_0 .alias "in1", 0 0, v0x24d5a20_0; +v0x24d5040_0 .net "nS", 0 0, L_0x24e11b0; 1 drivers +v0x24d50f0_0 .net "out0", 0 0, L_0x24e1270; 1 drivers +v0x24d5190_0 .net "out1", 0 0, L_0x24e1380; 1 drivers +v0x24d5230_0 .alias "outfinal", 0 0, v0x24d5600_0; +S_0x24d3af0 .scope generate, "addbits[1]" "addbits[1]" 2 218, 2 218, S_0x24d15a0; + .timescale -9 -12; +P_0x24d34f8 .param/l "i" 2 218, +C4<01>; +S_0x24d3c60 .scope module, "attempt" "MiddleAddSubSLT" 2 220, 2 115, S_0x24d3af0; + .timescale -9 -12; +L_0x24dcd10/d .functor NOT 1, L_0x24de210, C4<0>, C4<0>, C4<0>; +L_0x24dcd10 .delay (10000,10000,10000) L_0x24dcd10/d; +L_0x24dd400/d .functor NOT 1, L_0x24dd4c0, C4<0>, C4<0>, C4<0>; +L_0x24dd400 .delay (10000,10000,10000) L_0x24dd400/d; +L_0x24dd560/d .functor AND 1, L_0x24dd6a0, L_0x24dd400, C4<1>, C4<1>; +L_0x24dd560 .delay (20000,20000,20000) L_0x24dd560/d; +L_0x24d5fa0/d .functor XOR 1, L_0x24de120, L_0x24dd190, C4<0>, C4<0>; +L_0x24d5fa0 .delay (40000,40000,40000) L_0x24d5fa0/d; +L_0x24dd8e0/d .functor XOR 1, L_0x24d5fa0, L_0x24de340, C4<0>, C4<0>; +L_0x24dd8e0 .delay (40000,40000,40000) L_0x24dd8e0/d; +L_0x24dd9d0/d .functor AND 1, L_0x24de120, L_0x24dd190, C4<1>, C4<1>; +L_0x24dd9d0 .delay (20000,20000,20000) L_0x24dd9d0/d; +L_0x24ddb40/d .functor AND 1, L_0x24d5fa0, L_0x24de340, C4<1>, C4<1>; +L_0x24ddb40 .delay (20000,20000,20000) L_0x24ddb40/d; +L_0x24ddc30/d .functor OR 1, L_0x24dd9d0, L_0x24ddb40, C4<0>, C4<0>; +L_0x24ddc30 .delay (20000,20000,20000) L_0x24ddc30/d; +v0x24d42f0_0 .net "A", 0 0, L_0x24de120; 1 drivers +v0x24d43b0_0 .net "AandB", 0 0, L_0x24dd9d0; 1 drivers +v0x24d4450_0 .net "AddSubSLTSum", 0 0, L_0x24dd8e0; 1 drivers +v0x24d44f0_0 .net "AxorB", 0 0, L_0x24d5fa0; 1 drivers +v0x24d4570_0 .net "B", 0 0, L_0x24de210; 1 drivers +v0x24d4620_0 .net "BornB", 0 0, L_0x24dd190; 1 drivers +v0x24d46e0_0 .net "CINandAxorB", 0 0, L_0x24ddb40; 1 drivers +v0x24d4760_0 .alias "Command", 2 0, v0x24d5f20_0; +v0x24d47e0_0 .net *"_s3", 0 0, L_0x24dd4c0; 1 drivers +v0x24d4860_0 .net *"_s5", 0 0, L_0x24dd6a0; 1 drivers +v0x24d4900_0 .net "carryin", 0 0, L_0x24de340; 1 drivers +v0x24d49a0_0 .net "carryout", 0 0, L_0x24ddc30; 1 drivers +v0x24d4a40_0 .net "nB", 0 0, L_0x24dcd10; 1 drivers +v0x24d4ac0_0 .net "nCmd2", 0 0, L_0x24dd400; 1 drivers +v0x24d4bc0_0 .net "subtract", 0 0, L_0x24dd560; 1 drivers +L_0x24dd360 .part v0x24d6a40_0, 0, 1; +L_0x24dd4c0 .part v0x24d6a40_0, 2, 1; +L_0x24dd6a0 .part v0x24d6a40_0, 0, 1; +S_0x24d3d50 .scope module, "mux0" "TwoInMux" 2 131, 2 8, S_0x24d3c60; + .timescale -9 -12; +L_0x24dceb0/d .functor NOT 1, L_0x24dd360, C4<0>, C4<0>, C4<0>; +L_0x24dceb0 .delay (10000,10000,10000) L_0x24dceb0/d; +L_0x24dcf70/d .functor AND 1, L_0x24de210, L_0x24dceb0, C4<1>, C4<1>; +L_0x24dcf70 .delay (20000,20000,20000) L_0x24dcf70/d; +L_0x24dd080/d .functor AND 1, L_0x24dcd10, L_0x24dd360, C4<1>, C4<1>; +L_0x24dd080 .delay (20000,20000,20000) L_0x24dd080/d; +L_0x24dd190/d .functor OR 1, L_0x24dcf70, L_0x24dd080, C4<0>, C4<0>; +L_0x24dd190 .delay (20000,20000,20000) L_0x24dd190/d; +v0x24d3e40_0 .net "S", 0 0, L_0x24dd360; 1 drivers +v0x24d3ee0_0 .alias "in0", 0 0, v0x24d4570_0; +v0x24d3f80_0 .alias "in1", 0 0, v0x24d4a40_0; +v0x24d4020_0 .net "nS", 0 0, L_0x24dceb0; 1 drivers +v0x24d40d0_0 .net "out0", 0 0, L_0x24dcf70; 1 drivers +v0x24d4170_0 .net "out1", 0 0, L_0x24dd080; 1 drivers +v0x24d4250_0 .alias "outfinal", 0 0, v0x24d4620_0; +S_0x24d2940 .scope generate, "addbits[2]" "addbits[2]" 2 218, 2 218, S_0x24d15a0; + .timescale -9 -12; +P_0x24d22c8 .param/l "i" 2 218, +C4<010>; +S_0x24d2ab0 .scope module, "attempt" "MiddleAddSubSLT" 2 220, 2 115, S_0x24d2940; + .timescale -9 -12; +L_0x24de430/d .functor NOT 1, L_0x24df830, C4<0>, C4<0>, C4<0>; +L_0x24de430 .delay (10000,10000,10000) L_0x24de430/d; +L_0x24deb30/d .functor NOT 1, L_0x24debf0, C4<0>, C4<0>, C4<0>; +L_0x24deb30 .delay (10000,10000,10000) L_0x24deb30/d; +L_0x24dec90/d .functor AND 1, L_0x24dedd0, L_0x24deb30, C4<1>, C4<1>; +L_0x24dec90 .delay (20000,20000,20000) L_0x24dec90/d; +L_0x24dee70/d .functor XOR 1, L_0x24df730, L_0x24de8c0, C4<0>, C4<0>; +L_0x24dee70 .delay (40000,40000,40000) L_0x24dee70/d; +L_0x24def60/d .functor XOR 1, L_0x24dee70, L_0x24df960, C4<0>, C4<0>; +L_0x24def60 .delay (40000,40000,40000) L_0x24def60/d; +L_0x24df050/d .functor AND 1, L_0x24df730, L_0x24de8c0, C4<1>, C4<1>; +L_0x24df050 .delay (20000,20000,20000) L_0x24df050/d; +L_0x24df1c0/d .functor AND 1, L_0x24dee70, L_0x24df960, C4<1>, C4<1>; +L_0x24df1c0 .delay (20000,20000,20000) L_0x24df1c0/d; +L_0x24df2b0/d .functor OR 1, L_0x24df050, L_0x24df1c0, C4<0>, C4<0>; +L_0x24df2b0 .delay (20000,20000,20000) L_0x24df2b0/d; +v0x24d3140_0 .net "A", 0 0, L_0x24df730; 1 drivers +v0x24d3200_0 .net "AandB", 0 0, L_0x24df050; 1 drivers +v0x24d32a0_0 .net "AddSubSLTSum", 0 0, L_0x24def60; 1 drivers +v0x24d3340_0 .net "AxorB", 0 0, L_0x24dee70; 1 drivers +v0x24d33c0_0 .net "B", 0 0, L_0x24df830; 1 drivers +v0x24d3470_0 .net "BornB", 0 0, L_0x24de8c0; 1 drivers +v0x24d3530_0 .net "CINandAxorB", 0 0, L_0x24df1c0; 1 drivers +v0x24d35b0_0 .alias "Command", 2 0, v0x24d5f20_0; +v0x24d3660_0 .net *"_s3", 0 0, L_0x24debf0; 1 drivers +v0x24d36e0_0 .net *"_s5", 0 0, L_0x24dedd0; 1 drivers +v0x24d3760_0 .net "carryin", 0 0, L_0x24df960; 1 drivers +v0x24d3800_0 .net "carryout", 0 0, L_0x24df2b0; 1 drivers +v0x24d38a0_0 .net "nB", 0 0, L_0x24de430; 1 drivers +v0x24d3950_0 .net "nCmd2", 0 0, L_0x24deb30; 1 drivers +v0x24d3a50_0 .net "subtract", 0 0, L_0x24dec90; 1 drivers +L_0x24dea90 .part v0x24d6a40_0, 0, 1; +L_0x24debf0 .part v0x24d6a40_0, 2, 1; +L_0x24dedd0 .part v0x24d6a40_0, 0, 1; +S_0x24d2ba0 .scope module, "mux0" "TwoInMux" 2 131, 2 8, S_0x24d2ab0; + .timescale -9 -12; +L_0x24de5e0/d .functor NOT 1, L_0x24dea90, C4<0>, C4<0>, C4<0>; +L_0x24de5e0 .delay (10000,10000,10000) L_0x24de5e0/d; +L_0x24de6a0/d .functor AND 1, L_0x24df830, L_0x24de5e0, C4<1>, C4<1>; +L_0x24de6a0 .delay (20000,20000,20000) L_0x24de6a0/d; +L_0x24de7b0/d .functor AND 1, L_0x24de430, L_0x24dea90, C4<1>, C4<1>; +L_0x24de7b0 .delay (20000,20000,20000) L_0x24de7b0/d; +L_0x24de8c0/d .functor OR 1, L_0x24de6a0, L_0x24de7b0, C4<0>, C4<0>; +L_0x24de8c0 .delay (20000,20000,20000) L_0x24de8c0/d; +v0x24d2c90_0 .net "S", 0 0, L_0x24dea90; 1 drivers +v0x24d2d30_0 .alias "in0", 0 0, v0x24d33c0_0; +v0x24d2dd0_0 .alias "in1", 0 0, v0x24d38a0_0; +v0x24d2e70_0 .net "nS", 0 0, L_0x24de5e0; 1 drivers +v0x24d2f20_0 .net "out0", 0 0, L_0x24de6a0; 1 drivers +v0x24d2fc0_0 .net "out1", 0 0, L_0x24de7b0; 1 drivers +v0x24d30a0_0 .alias "outfinal", 0 0, v0x24d3470_0; +S_0x24d16f0 .scope generate, "addbits[3]" "addbits[3]" 2 218, 2 218, S_0x24d15a0; + .timescale -9 -12; +P_0x24d17e8 .param/l "i" 2 218, +C4<011>; +S_0x24d1880 .scope module, "attempt" "MiddleAddSubSLT" 2 220, 2 115, S_0x24d16f0; + .timescale -9 -12; +L_0x24df7d0/d .functor NOT 1, L_0x24e0e70, C4<0>, C4<0>, C4<0>; +L_0x24df7d0 .delay (10000,10000,10000) L_0x24df7d0/d; +L_0x24e0000/d .functor NOT 1, L_0x24e00c0, C4<0>, C4<0>, C4<0>; +L_0x24e0000 .delay (10000,10000,10000) L_0x24e0000/d; +L_0x24e0160/d .functor AND 1, L_0x24e02a0, L_0x24e0000, C4<1>, C4<1>; +L_0x24e0160 .delay (20000,20000,20000) L_0x24e0160/d; +L_0x24e0340/d .functor XOR 1, L_0x24e0cb0, L_0x24dfd90, C4<0>, C4<0>; +L_0x24e0340 .delay (40000,40000,40000) L_0x24e0340/d; +L_0x24e0430/d .functor XOR 1, L_0x24e0340, L_0x24e1030, C4<0>, C4<0>; +L_0x24e0430 .delay (40000,40000,40000) L_0x24e0430/d; +L_0x24e0520/d .functor AND 1, L_0x24e0cb0, L_0x24dfd90, C4<1>, C4<1>; +L_0x24e0520 .delay (20000,20000,20000) L_0x24e0520/d; +L_0x24e0690/d .functor AND 1, L_0x24e0340, L_0x24e1030, C4<1>, C4<1>; +L_0x24e0690 .delay (20000,20000,20000) L_0x24e0690/d; +L_0x24e0780/d .functor OR 1, L_0x24e0520, L_0x24e0690, C4<0>, C4<0>; +L_0x24e0780 .delay (20000,20000,20000) L_0x24e0780/d; +v0x24d1f10_0 .net "A", 0 0, L_0x24e0cb0; 1 drivers +v0x24d1fd0_0 .net "AandB", 0 0, L_0x24e0520; 1 drivers +v0x24d2070_0 .net "AddSubSLTSum", 0 0, L_0x24e0430; 1 drivers +v0x24d2110_0 .net "AxorB", 0 0, L_0x24e0340; 1 drivers +v0x24d2190_0 .net "B", 0 0, L_0x24e0e70; 1 drivers +v0x24d2240_0 .net "BornB", 0 0, L_0x24dfd90; 1 drivers +v0x24d2300_0 .net "CINandAxorB", 0 0, L_0x24e0690; 1 drivers +v0x24d2380_0 .alias "Command", 2 0, v0x24d5f20_0; +v0x24d2400_0 .net *"_s3", 0 0, L_0x24e00c0; 1 drivers +v0x24d24a0_0 .net *"_s5", 0 0, L_0x24e02a0; 1 drivers +v0x24d2540_0 .net "carryin", 0 0, L_0x24e1030; 1 drivers +v0x24d25e0_0 .net "carryout", 0 0, L_0x24e0780; 1 drivers +v0x24d26f0_0 .net "nB", 0 0, L_0x24df7d0; 1 drivers +v0x24d27a0_0 .net "nCmd2", 0 0, L_0x24e0000; 1 drivers +v0x24d28a0_0 .net "subtract", 0 0, L_0x24e0160; 1 drivers +L_0x24dff60 .part v0x24d6a40_0, 0, 1; +L_0x24e00c0 .part v0x24d6a40_0, 2, 1; +L_0x24e02a0 .part v0x24d6a40_0, 0, 1; +S_0x24d1970 .scope module, "mux0" "TwoInMux" 2 131, 2 8, S_0x24d1880; + .timescale -9 -12; +L_0x24dfaf0/d .functor NOT 1, L_0x24dff60, C4<0>, C4<0>, C4<0>; +L_0x24dfaf0 .delay (10000,10000,10000) L_0x24dfaf0/d; +L_0x24dfb70/d .functor AND 1, L_0x24e0e70, L_0x24dfaf0, C4<1>, C4<1>; +L_0x24dfb70 .delay (20000,20000,20000) L_0x24dfb70/d; +L_0x24dfc80/d .functor AND 1, L_0x24df7d0, L_0x24dff60, C4<1>, C4<1>; +L_0x24dfc80 .delay (20000,20000,20000) L_0x24dfc80/d; +L_0x24dfd90/d .functor OR 1, L_0x24dfb70, L_0x24dfc80, C4<0>, C4<0>; +L_0x24dfd90 .delay (20000,20000,20000) L_0x24dfd90/d; +v0x24d1a60_0 .net "S", 0 0, L_0x24dff60; 1 drivers +v0x24d1b00_0 .alias "in0", 0 0, v0x24d2190_0; +v0x24d1ba0_0 .alias "in1", 0 0, v0x24d26f0_0; +v0x24d1c40_0 .net "nS", 0 0, L_0x24dfaf0; 1 drivers +v0x24d1cf0_0 .net "out0", 0 0, L_0x24dfb70; 1 drivers +v0x24d1d90_0 .net "out1", 0 0, L_0x24dfc80; 1 drivers +v0x24d1e70_0 .alias "outfinal", 0 0, v0x24d2240_0; + .scope S_0x24a9430; +T_0 ; + %vpi_call 3 21 "$display", " A | B |Command|Output | exOut|Cout|OF|subtract|SLTflag"; + %movi 8, 8, 4; + %set/v v0x24d6840_0, 8, 4; + %movi 8, 1, 4; + %set/v v0x24d6990_0, 8, 4; + %set/v v0x24d6a40_0, 0, 3; + %delay 1000000, 0; + %vpi_call 3 23 "$display", "%b | %b | %b | %b | Expect 1001| %b | %b ", v0x24d6840_0, v0x24d6990_0, v0x24d6a40_0, v0x24d68e0_0, v0x24d6c20_0, v0x24d6cd0_0; + %movi 8, 10, 4; + %set/v v0x24d6840_0, 8, 4; + %movi 8, 1, 4; + %set/v v0x24d6990_0, 8, 4; + %set/v v0x24d6a40_0, 0, 3; + %delay 1000000, 0; + %vpi_call 3 26 "$display", "%b | %b | %b | %b | Expect 1011| %b | %b | %b", v0x24d6840_0, v0x24d6990_0, v0x24d6a40_0, v0x24d68e0_0, v0x24d6c20_0, v0x24d6cd0_0, v0x24d6d80_0; + %movi 8, 10, 4; + %set/v v0x24d6840_0, 8, 4; + %movi 8, 1, 4; + %set/v v0x24d6990_0, 8, 4; + %set/v v0x24d6a40_0, 0, 3; + %delay 1000000, 0; + %vpi_call 3 29 "$display", "%b | %b | %b | %b | Expect 1011| %b | %b ", v0x24d6840_0, v0x24d6990_0, v0x24d6a40_0, v0x24d68e0_0, v0x24d6c20_0, v0x24d6cd0_0; + %movi 8, 10, 4; + %set/v v0x24d6840_0, 8, 4; + %movi 8, 7, 4; + %set/v v0x24d6990_0, 8, 4; + %set/v v0x24d6a40_0, 0, 3; + %delay 1000000, 0; + %vpi_call 3 32 "$display", "%b | %b | %b | %b | Expect 0001| %b | %b ", v0x24d6840_0, v0x24d6990_0, v0x24d6a40_0, v0x24d68e0_0, v0x24d6c20_0, v0x24d6cd0_0; + %movi 8, 10, 4; + %set/v v0x24d6840_0, 8, 4; + %movi 8, 7, 4; + %set/v v0x24d6990_0, 8, 4; + %movi 8, 1, 3; + %set/v v0x24d6a40_0, 8, 3; + %delay 1000000, 0; + %vpi_call 3 35 "$display", "%b | %b | %b | %b | Expect 0011| %b | %b | %b", v0x24d6840_0, v0x24d6990_0, v0x24d6a40_0, v0x24d68e0_0, v0x24d6c20_0, v0x24d6cd0_0, v0x24d6d80_0; + %movi 8, 10, 4; + %set/v v0x24d6840_0, 8, 4; + %movi 8, 7, 4; + %set/v v0x24d6990_0, 8, 4; + %movi 8, 3, 3; + %set/v v0x24d6a40_0, 8, 3; + %delay 1000000, 0; + %vpi_call 3 38 "$display", "%b | %b | %b | %b | Expect 0011| %b | %b | %b | %b", v0x24d6840_0, v0x24d6990_0, v0x24d6a40_0, v0x24d68e0_0, v0x24d6c20_0, v0x24d6cd0_0, v0x24d6d80_0, v0x24d6af0_0; + %movi 8, 7, 4; + %set/v v0x24d6840_0, 8, 4; + %movi 8, 10, 4; + %set/v v0x24d6990_0, 8, 4; + %movi 8, 3, 3; + %set/v v0x24d6a40_0, 8, 3; + %delay 1000000, 0; + %vpi_call 3 41 "$display", "%b | %b | %b | %b | Expect 0011| %b | %b | %b | %b", v0x24d6840_0, v0x24d6990_0, v0x24d6a40_0, v0x24d68e0_0, v0x24d6c20_0, v0x24d6cd0_0, v0x24d6d80_0, v0x24d6af0_0; + %movi 8, 1, 4; + %set/v v0x24d6840_0, 8, 4; + %movi 8, 2, 4; + %set/v v0x24d6990_0, 8, 4; + %movi 8, 3, 3; + %set/v v0x24d6a40_0, 8, 3; + %delay 1000000, 0; + %vpi_call 3 45 "$display", "%b | %b | %b | %b | Expect x| %b | %b | %b | %b", v0x24d6840_0, v0x24d6990_0, v0x24d6a40_0, v0x24d68e0_0, v0x24d6c20_0, v0x24d6cd0_0, v0x24d6d80_0, v0x24d6af0_0; + %end; + .thread T_0; +# The file index is used to find the file name in the following table. +:file_names 4; + "N/A"; + ""; + "./alu2.v"; + "testing.t.v"; diff --git a/testing.t.v b/testing.t.v index 86e0221..7ff5bb0 100644 --- a/testing.t.v +++ b/testing.t.v @@ -1,133 +1,50 @@ // Intermediate testbench `timescale 1 ns / 1 ps -`include "alu.v" +`include "alu2.v" -module testMultiplexer (); +module test32Adder(); -wire AndNandOut; -reg A, B; -reg[2:0] Command; -//reg S; -wire OneBitFinalOut; -wire AddSubSLTSum, carryout; //overflow, -reg carryin; -wire OrNorXorOut; +parameter size = 4; +wire [size-1:0] AddSubSLTSum; +wire carryout; +wire overflow; +wire SLTflag; +wire [size-1:0] subtract; +reg [size-1:0] A, B; +reg [2:0] Command; +reg [size-1:0]carryin; - //wire muxout; - //reg S0, S1; - //reg in0, in1, in2, in3; - - wire Cmd0Start; - wire Cmd1Start; - - wire nB; - wire BornB; - wire AxorB; - wire AandB; - wire CINandAxorB; - - wire AnorB; - wire AorB; - wire AnandB; - wire nXor; - wire XorNor; - - MiddleAddSubSLT testadd(AddSubSLTSum, carryout, A, B, Command, carryin); - - AndNand newpotato(AndNandOut, A, B, Command); - - OrNorXor ortest(OrNorXorOut, A, B, Command); - - Bitslice yukongoldpotato(OneBitFinalOut, AddSubSLTSum, carryout, OrNorXorOut, A, B, Command, carryin); - - - //FourInMux arbitrarypotato(muxout, S0, S1, in0, in1, in2, in3); +wire [size-1:0] CarryoutWire; +AddSubSLT32 trial(AddSubSLTSum, carryout, overflow, SLTflag, subtract, A, B, Command, carryin); initial begin +$display(" A | B |Command|Output | exOut|Cout|OF|subtract|SLTflag"); +A = 4'b1000; B = 4'b0001; Command =3'b000; #1000 +$display("%b | %b | %b | %b | Expect 1001| %b | %b ", A, B, Command, AddSubSLTSum, carryout, overflow); -// just the adder - proper behavior - $display("Adder/Subtractor"); - $display("A B| Command | Output | Expected Output"); - A=1;B=1;Command=3'b000; carryin = 0; #1000 - $display("%b %b | %b | %b | 0 | %b", A, B, Command, AddSubSLTSum, carryout); - A=1;B=1;Command=3'b001; carryin = 1; #1000 - $display("%b %b | %b | %b | 0 | %b", A, B, Command, AddSubSLTSum, carryout); +A = 4'b1010; B = 4'b0001; Command =3'b000; #1000 +$display("%b | %b | %b | %b | Expect 1011| %b | %b | %b", A, B, Command, AddSubSLTSum, carryout, overflow, subtract); -// testing subtraction - $display("One Bitslice Adder/Subtractor"); - $display("A B| Command |Out|ExOut|Carryout"); - A=1;B=1;Command=3'b000; carryin=0; #1000 - $display("%b %b | %b | %b | 0 | %b", A, B, Command, OneBitFinalOut, carryout); - A=1;B=0;Command=3'b000; carryin=0; #1000 - $display("%b %b | %b | %b | 1 | %b", A, B, Command, OneBitFinalOut, carryout); - A=0;B=0;Command=3'b000; carryin=0; #1000 - $display("%b %b | %b | %b | 0 | %b", A, B, Command, OneBitFinalOut, carryout); +A = 4'b1010; B = 4'b0001; Command =3'b000; #1000 +$display("%b | %b | %b | %b | Expect 1011| %b | %b ", A, B, Command, AddSubSLTSum, carryout, overflow); - A=1;B=1;Command=3'b001; carryin=1; #1000 - $display("%b %b | %b | %b | 0 | %b", A, B, Command, OneBitFinalOut, carryout); - A=1;B=0;Command=3'b001; carryin=1; #1000 - $display("%b %b | %b | %b | 1 | %b", A, B, Command, OneBitFinalOut, carryout); - A=0;B=0;Command=3'b001; carryin=1; #1000 - $display("%b %b | %b | %b | 0 | %b", A, B, Command, OneBitFinalOut, carryout); +A = 4'b1010; B = 4'b0111; Command =3'b000; #1000 +$display("%b | %b | %b | %b | Expect 0001| %b | %b ", A, B, Command, AddSubSLTSum, carryout, overflow); +A = 4'b1010; B = 4'b0111; Command =3'b001; #1000 +$display("%b | %b | %b | %b | Expect 0011| %b | %b | %b", A, B, Command, AddSubSLTSum, carryout, overflow, subtract); - //$display("A B| Command | Output | Expected Output- pure sadness"); - //S0 = 1; S1 = 0; in0 = 1; in1 = 1; in2 = 0; in3 = 0; #1000 - //$display("%b %b | %b %b %b %b | %b | 1", S0, S1, in0, in1, in2, in3, muxout); +A = 4'b1010; B = 4'b0111; Command =3'b011; #1000 +$display("%b | %b | %b | %b | Expect 0011| %b | %b | %b | %b", A, B, Command, AddSubSLTSum, carryout, overflow, subtract, SLTflag); -// testing addition - $display("A B| Command | Output | Expected Output-sadness|Carryout"); - A=1;B=1;Command=3'b000; carryin=0; #1000 - $display("%b %b | %b | %b | 0 | %b", A, B, Command, OneBitFinalOut, carryout); - A=1;B=0;Command=3'b000; carryin=0; #1000 - $display("%b %b | %b | %b | 1 | %b", A, B, Command, OneBitFinalOut, carryout); - A=0;B=0;Command=3'b000; carryin=0; #1000 - $display("%b %b | %b | %b | 0 | %b", A, B, Command, OneBitFinalOut, carryout); +A = 4'b0111; B = 4'b1010; Command =3'b011; #1000 +$display("%b | %b | %b | %b | Expect 0011| %b | %b | %b | %b", A, B, Command, AddSubSLTSum, carryout, overflow, subtract, SLTflag); -// Exhaustively testing AND/NAND - $display("A B| Command | command0 Output | Expected Output - AND TESTS"); - A=1;B=1;Command=3'b000; #1000 - $display("%b %b | %b | %b %b | 1", A, B, Command, Command[0], AndNandOut); - A=1;B=1;Command=3'b001; #1000 - $display("%b %b | %b | %b %b | 0", A, B, Command, Command[1], AndNandOut); - A=0;B=1;Command=3'b000; #1000 - $display("%b %b | %b | %b %b | 0", A, B, Command, Command[0], AndNandOut); - A=1;B=0;Command=3'b001; #1000 - $display("%b %b | %b | %b %b | 1", A, B, Command, Command[1], AndNandOut); - - -// Exhaustively testing OR/NOR/XOR - $display("A B | Command | Output | Expected Output - OR TESTS"); - A=1; B=1; Command=3'b111; #1000 - $display("%b %b | %b | %b | 1 - OR TEST", A, B, Command, OrNorXorOut); - A=1; B=0; Command=3'b111; #1000 - $display("%b %b | %b | %b | 1 - OR TEST", A, B, Command, OrNorXorOut); - A=0; B=1; Command=3'b111; #1000 - $display("%b %b | %b | %b | 1 - OR TEST", A, B, Command, OrNorXorOut); - A=0; B=0; Command=3'b111; #1000 - $display("%b %b | %b | %b | 0 - OR TEST", A, B, Command, OrNorXorOut); - - - A=1; B=1; Command=3'b110; #1000 - $display("%b %b | %b | %b | 0 - NOR TEST", A, B, Command, OrNorXorOut); - A=1; B=0; Command=3'b110; #1000 - $display("%b %b | %b | %b | 0 - NOR TEST", A, B, Command, OrNorXorOut); - A=0; B=1; Command=3'b110; #1000 - $display("%b %b | %b | %b | 0 - NOR TEST", A, B, Command, OrNorXorOut); - A=0; B=0; Command=3'b110; #1000 - $display("%b %b | %b | %b | 1 - NOR TEST", A, B, Command, OrNorXorOut); - - A=1; B=1; Command=3'b010; #1000 - $display("%b %b | %b | %b | 0 - XOR TEST", A, B, Command, OrNorXorOut); - A=1; B=0; Command=3'b010; #1000 - $display("%b %b | %b | %b | 1 - XOR TEST", A, B, Command, OrNorXorOut); - A=0; B=1; Command=3'b010; #1000 - $display("%b %b | %b | %b | 1 - XOR TEST", A, B, Command, OrNorXorOut); - A=0; B=0; Command=3'b010; #1000 - $display("%b %b | %b | %b | 0 - XOR TEST", A, B, Command, OrNorXorOut); - - end +A = 4'b0001; B = 4'b0010; Command =3'b011; #1000 +$display("%b | %b | %b | %b | Expect x| %b | %b | %b | %b", A, B, Command, AddSubSLTSum, carryout, overflow, subtract, SLTflag); +end endmodule + From 31c0ddddd48549f80616691a823a7e6fba1d1249 Mon Sep 17 00:00:00 2001 From: mjakus Date: Sun, 8 Oct 2017 18:55:49 -0400 Subject: [PATCH 07/28] Made four bit alu./test! --- alu2.v | 245 ++++- test | 2772 ++++++++++++++++++++++++++++++++++++++------------- testing.t.v | 47 +- 3 files changed, 2339 insertions(+), 725 deletions(-) diff --git a/alu2.v b/alu2.v index 0140d55..75b87f5 100644 --- a/alu2.v +++ b/alu2.v @@ -90,27 +90,7 @@ wire XorNor; TwoInMux mux1(OrNorXorOut, Command[0], XorNor, AorB); endmodule -module ZerothAddSubSLT -( -output AddSubSLTSum, carryout, //overflow, -input A, B, -input[2:0] Command -//input carryin -); - wire nB; - wire BornB; - wire AxorB; - wire AandB; - wire CINandAxorB; - - `NOT Binv(nB, B); - TwoInMux mux0(BornB, Command[0], B, nB); - `XOR XOR1(AxorB, A, BornB); - `XOR XOR2(AddSubSLTSum, AxorB, Command[0]); - `AND AND1(AandB, A, BornB); - `AND AND2(CINandAxorB, AxorB, Command[0]); - `OR OR1(carryout, AandB, CINandAxorB); -endmodule + module MiddleAddSubSLT ( @@ -138,29 +118,6 @@ input carryin `OR OR1(carryout, AandB, CINandAxorB); endmodule -module LastAddSubSLT -( -output AddSubSLTSum, carryout, overflow, -input A, B, -input[2:0] Command, -input carryin -); - wire nB; - wire BornB; - wire AxorB; - wire AandB; - wire CINandAxorB; - - `NOT Binv(nB, B); - TwoInMux mux0(BornB, Command[0], B, nB); - `XOR XOR1(AxorB, A, BornB); - `XOR XOR2(AddSubSLTSum, AxorB, carryin); - `AND AND1(AandB, A, BornB); - `AND AND2(CINandAxorB, AxorB, carryin); - `OR OR1(carryout, AandB, CINandAxorB); - `XOR xor3(overflow, carryout, carryin); -endmodule - module Bitslice ( output OneBitFinalOut, @@ -196,6 +153,59 @@ input carryin TwoInMux TwoMux(OneBitFinalOut, Command[2], Cmd0Start, Cmd1Start); endmodule + +module AndNand32 +( +output [size-1:0] AndNandOut, +input [size-1:0] A, +input [size-1:0] B, +input[2:0] Command + +); +parameter size = 4; +wire AnandB; +wire AandB; + + +AndNand attempt2(AndNandOut[0], A[0], B[0], Command); +genvar i; + generate + for (i=1; i; 0 drivers -v0x24cf3b0_0 .net "AddSubSLTSum", 0 0, C4; 0 drivers -v0x24cf450_0 .net "AddSumSLTSum", 0 0, L_0x24d7890; 1 drivers -v0x24cf560_0 .net "AndNandOut", 0 0, L_0x24d9560; 1 drivers -v0x24cf670_0 .net "B", 0 0, C4; 0 drivers -v0x24cf780_0 .net "Cmd0Start", 0 0, L_0x24d9df0; 1 drivers -v0x24cf800_0 .net "Cmd1Start", 0 0, L_0x24da880; 1 drivers -v0x24cf880_0 .net "Command", 2 0, C4; 0 drivers -v0x24cf900_0 .net "OneBitFinalOut", 0 0, L_0x24dafe0; 1 drivers -v0x24cf980_0 .net "OrNorXorOut", 0 0, L_0x24d8cb0; 1 drivers -v0x24cfa00_0 .net "carryin", 0 0, C4; 0 drivers -v0x24cfa80_0 .net "carryout", 0 0, L_0x24d7c40; 1 drivers -v0x24cfb00_0 .net "subtract", 0 0, L_0x24d7560; 1 drivers -L_0x24d9fd0 .part C4, 0, 1; -L_0x24da100 .part C4, 1, 1; -L_0x24daa60 .part C4, 0, 1; -L_0x24dab90 .part C4, 1, 1; -L_0x24db110 .part C4, 2, 1; -S_0x24ce2b0 .scope module, "rottenpotato" "MiddleAddSubSLT" 2 190, 2 115, S_0x24a09f0; - .timescale -9 -12; -L_0x24ceec0/d .functor NOT 1, C4, C4<0>, C4<0>, C4<0>; -L_0x24ceec0 .delay (10000,10000,10000) L_0x24ceec0/d; -L_0x24d7420/d .functor NOT 1, L_0x24d74c0, C4<0>, C4<0>, C4<0>; -L_0x24d7420 .delay (10000,10000,10000) L_0x24d7420/d; -L_0x24d7560/d .functor AND 1, L_0x24d76a0, L_0x24d7420, C4<1>, C4<1>; -L_0x24d7560 .delay (20000,20000,20000) L_0x24d7560/d; -L_0x24d7740/d .functor XOR 1, C4, L_0x24d7160, C4<0>, C4<0>; -L_0x24d7740 .delay (40000,40000,40000) L_0x24d7740/d; -L_0x24d7890/d .functor XOR 1, L_0x24d7740, C4, C4<0>, C4<0>; -L_0x24d7890 .delay (40000,40000,40000) L_0x24d7890/d; -L_0x24d79f0/d .functor AND 1, C4, L_0x24d7160, C4<1>, C4<1>; -L_0x24d79f0 .delay (20000,20000,20000) L_0x24d79f0/d; -L_0x24d7b80/d .functor AND 1, L_0x24d7740, C4, C4<1>, C4<1>; -L_0x24d7b80 .delay (20000,20000,20000) L_0x24d7b80/d; -L_0x24d7c40/d .functor OR 1, L_0x24d79f0, L_0x24d7b80, C4<0>, C4<0>; -L_0x24d7c40 .delay (20000,20000,20000) L_0x24d7c40/d; -v0x24ce830_0 .alias "A", 0 0, v0x24cf310_0; -v0x24ce920_0 .net "AandB", 0 0, L_0x24d79f0; 1 drivers -v0x24ce9c0_0 .alias "AddSubSLTSum", 0 0, v0x24cf450_0; -v0x24cea40_0 .net "AxorB", 0 0, L_0x24d7740; 1 drivers -v0x24ceac0_0 .alias "B", 0 0, v0x24cf670_0; -v0x24ceb40_0 .net "BornB", 0 0, L_0x24d7160; 1 drivers -v0x24cec00_0 .net "CINandAxorB", 0 0, L_0x24d7b80; 1 drivers -v0x24cec80_0 .alias "Command", 2 0, v0x24cf880_0; -v0x24ceda0_0 .net *"_s3", 0 0, L_0x24d74c0; 1 drivers -v0x24cee40_0 .net *"_s5", 0 0, L_0x24d76a0; 1 drivers -v0x24cef40_0 .alias "carryin", 0 0, v0x24cfa00_0; -v0x24cefe0_0 .alias "carryout", 0 0, v0x24cfa80_0; -v0x24cf0f0_0 .net "nB", 0 0, L_0x24ceec0; 1 drivers -v0x24cf170_0 .net "nCmd2", 0 0, L_0x24d7420; 1 drivers -v0x24cf270_0 .alias "subtract", 0 0, v0x24cfb00_0; -L_0x24d72f0 .part C4, 0, 1; -L_0x24d74c0 .part C4, 2, 1; -L_0x24d76a0 .part C4, 0, 1; -S_0x24ce3a0 .scope module, "mux0" "TwoInMux" 2 131, 2 8, S_0x24ce2b0; - .timescale -9 -12; -L_0x24d6e80/d .functor NOT 1, L_0x24d72f0, C4<0>, C4<0>, C4<0>; -L_0x24d6e80 .delay (10000,10000,10000) L_0x24d6e80/d; -L_0x24d6f50/d .functor AND 1, C4, L_0x24d6e80, C4<1>, C4<1>; -L_0x24d6f50 .delay (20000,20000,20000) L_0x24d6f50/d; -L_0x24d7070/d .functor AND 1, L_0x24ceec0, L_0x24d72f0, C4<1>, C4<1>; -L_0x24d7070 .delay (20000,20000,20000) L_0x24d7070/d; -L_0x24d7160/d .functor OR 1, L_0x24d6f50, L_0x24d7070, C4<0>, C4<0>; -L_0x24d7160 .delay (20000,20000,20000) L_0x24d7160/d; -v0x24ce490_0 .net "S", 0 0, L_0x24d72f0; 1 drivers -v0x24ce510_0 .alias "in0", 0 0, v0x24cf670_0; -v0x24ce590_0 .alias "in1", 0 0, v0x24cf0f0_0; -v0x24ce610_0 .net "nS", 0 0, L_0x24d6e80; 1 drivers -v0x24ce690_0 .net "out0", 0 0, L_0x24d6f50; 1 drivers -v0x24ce710_0 .net "out1", 0 0, L_0x24d7070; 1 drivers -v0x24ce790_0 .alias "outfinal", 0 0, v0x24ceb40_0; -S_0x24ccfc0 .scope module, "idahopotato" "OrNorXor" 2 191, 2 70, S_0x24a09f0; - .timescale -9 -12; -L_0x24d7dc0/d .functor NOR 1, C4, C4, C4<0>, C4<0>; -L_0x24d7dc0 .delay (10000,10000,10000) L_0x24d7dc0/d; -L_0x24d7f20/d .functor NOT 1, L_0x24d7dc0, C4<0>, C4<0>, C4<0>; -L_0x24d7f20 .delay (10000,10000,10000) L_0x24d7f20/d; -L_0x24d8050/d .functor NAND 1, C4, C4, C4<1>, C4<1>; -L_0x24d8050 .delay (10000,10000,10000) L_0x24d8050/d; -L_0x24d81e0/d .functor NAND 1, L_0x24d8050, L_0x24d7f20, C4<1>, C4<1>; -L_0x24d81e0 .delay (10000,10000,10000) L_0x24d81e0/d; -L_0x24d82d0/d .functor NOT 1, L_0x24d81e0, C4<0>, C4<0>, C4<0>; -L_0x24d82d0 .delay (10000,10000,10000) L_0x24d82d0/d; -v0x24cdb70_0 .alias "A", 0 0, v0x24cf310_0; -v0x24cdc20_0 .net "AnandB", 0 0, L_0x24d8050; 1 drivers -v0x24cdca0_0 .net "AnorB", 0 0, L_0x24d7dc0; 1 drivers -v0x24cdd50_0 .net "AorB", 0 0, L_0x24d7f20; 1 drivers -v0x24cde30_0 .net "AxorB", 0 0, L_0x24d82d0; 1 drivers -v0x24cdee0_0 .alias "B", 0 0, v0x24cf670_0; -v0x24cdfa0_0 .alias "Command", 2 0, v0x24cf880_0; -v0x24ce050_0 .alias "OrNorXorOut", 0 0, v0x24cf980_0; -v0x24ce1b0_0 .net "XorNor", 0 0, L_0x24d8730; 1 drivers -v0x24ce230_0 .net "nXor", 0 0, L_0x24d81e0; 1 drivers -L_0x24d88b0 .part C4, 2, 1; -L_0x24d8e30 .part C4, 0, 1; -S_0x24cd600 .scope module, "mux0" "TwoInMux" 2 89, 2 8, S_0x24ccfc0; - .timescale -9 -12; -L_0x24d8410/d .functor NOT 1, L_0x24d88b0, C4<0>, C4<0>, C4<0>; -L_0x24d8410 .delay (10000,10000,10000) L_0x24d8410/d; -L_0x24d84d0/d .functor AND 1, L_0x24d82d0, L_0x24d8410, C4<1>, C4<1>; -L_0x24d84d0 .delay (20000,20000,20000) L_0x24d84d0/d; -L_0x24d85e0/d .functor AND 1, L_0x24d7dc0, L_0x24d88b0, C4<1>, C4<1>; -L_0x24d85e0 .delay (20000,20000,20000) L_0x24d85e0/d; -L_0x24d8730/d .functor OR 1, L_0x24d84d0, L_0x24d85e0, C4<0>, C4<0>; -L_0x24d8730 .delay (20000,20000,20000) L_0x24d8730/d; -v0x24cd6f0_0 .net "S", 0 0, L_0x24d88b0; 1 drivers -v0x24cd7b0_0 .alias "in0", 0 0, v0x24cde30_0; -v0x24cd850_0 .alias "in1", 0 0, v0x24cdca0_0; -v0x24cd8f0_0 .net "nS", 0 0, L_0x24d8410; 1 drivers -v0x24cd970_0 .net "out0", 0 0, L_0x24d84d0; 1 drivers -v0x24cda10_0 .net "out1", 0 0, L_0x24d85e0; 1 drivers -v0x24cdaf0_0 .alias "outfinal", 0 0, v0x24ce1b0_0; -S_0x24cd0b0 .scope module, "mux1" "TwoInMux" 2 90, 2 8, S_0x24ccfc0; - .timescale -9 -12; -L_0x24d8950/d .functor NOT 1, L_0x24d8e30, C4<0>, C4<0>, C4<0>; -L_0x24d8950 .delay (10000,10000,10000) L_0x24d8950/d; -L_0x24d8a10/d .functor AND 1, L_0x24d8730, L_0x24d8950, C4<1>, C4<1>; -L_0x24d8a10 .delay (20000,20000,20000) L_0x24d8a10/d; -L_0x24d8b60/d .functor AND 1, L_0x24d7f20, L_0x24d8e30, C4<1>, C4<1>; -L_0x24d8b60 .delay (20000,20000,20000) L_0x24d8b60/d; -L_0x24d8cb0/d .functor OR 1, L_0x24d8a10, L_0x24d8b60, C4<0>, C4<0>; -L_0x24d8cb0 .delay (20000,20000,20000) L_0x24d8cb0/d; -v0x24cd1a0_0 .net "S", 0 0, L_0x24d8e30; 1 drivers -v0x24cd240_0 .alias "in0", 0 0, v0x24ce1b0_0; -v0x24cd2e0_0 .alias "in1", 0 0, v0x24cdd50_0; -v0x24cd380_0 .net "nS", 0 0, L_0x24d8950; 1 drivers -v0x24cd400_0 .net "out0", 0 0, L_0x24d8a10; 1 drivers -v0x24cd4a0_0 .net "out1", 0 0, L_0x24d8b60; 1 drivers -v0x24cd580_0 .alias "outfinal", 0 0, v0x24cf980_0; -S_0x24cc620 .scope module, "sweetpotato" "AndNand" 2 192, 2 53, S_0x24a09f0; - .timescale -9 -12; -L_0x24d7390/d .functor NAND 1, C4, C4, C4<1>, C4<1>; -L_0x24d7390 .delay (10000,10000,10000) L_0x24d7390/d; -L_0x24d9110/d .functor NOT 1, L_0x24d7390, C4<0>, C4<0>, C4<0>; -L_0x24d9110 .delay (10000,10000,10000) L_0x24d9110/d; -v0x24ccc40_0 .alias "A", 0 0, v0x24cf310_0; -v0x24ccd00_0 .net "AandB", 0 0, L_0x24d9110; 1 drivers -v0x24ccd80_0 .net "AnandB", 0 0, L_0x24d7390; 1 drivers -v0x24cce00_0 .alias "AndNandOut", 0 0, v0x24cf560_0; -v0x24cce80_0 .alias "B", 0 0, v0x24cf670_0; -v0x24ccf00_0 .alias "Command", 2 0, v0x24cf880_0; -L_0x24d96e0 .part C4, 0, 1; -S_0x24cc710 .scope module, "potato" "TwoInMux" 2 66, 2 8, S_0x24cc620; - .timescale -9 -12; -L_0x24d9240/d .functor NOT 1, L_0x24d96e0, C4<0>, C4<0>, C4<0>; -L_0x24d9240 .delay (10000,10000,10000) L_0x24d9240/d; -L_0x24d9300/d .functor AND 1, L_0x24d9110, L_0x24d9240, C4<1>, C4<1>; -L_0x24d9300 .delay (20000,20000,20000) L_0x24d9300/d; -L_0x24d9410/d .functor AND 1, L_0x24d7390, L_0x24d96e0, C4<1>, C4<1>; -L_0x24d9410 .delay (20000,20000,20000) L_0x24d9410/d; -L_0x24d9560/d .functor OR 1, L_0x24d9300, L_0x24d9410, C4<0>, C4<0>; -L_0x24d9560 .delay (20000,20000,20000) L_0x24d9560/d; -v0x24cc800_0 .net "S", 0 0, L_0x24d96e0; 1 drivers -v0x24cc8c0_0 .alias "in0", 0 0, v0x24ccd00_0; -v0x24cc960_0 .alias "in1", 0 0, v0x24ccd80_0; -v0x24cca00_0 .net "nS", 0 0, L_0x24d9240; 1 drivers -v0x24cca80_0 .net "out0", 0 0, L_0x24d9300; 1 drivers -v0x24ccb20_0 .net "out1", 0 0, L_0x24d9410; 1 drivers -v0x24ccbc0_0 .alias "outfinal", 0 0, v0x24cf560_0; -S_0x24cbc60 .scope module, "ZeroMux" "FourInMux" 2 194, 2 29, S_0x24a09f0; - .timescale -9 -12; -L_0x24d9780/d .functor NOT 1, L_0x24d9fd0, C4<0>, C4<0>, C4<0>; -L_0x24d9780 .delay (10000,10000,10000) L_0x24d9780/d; -L_0x24d9840/d .functor NOT 1, L_0x24da100, C4<0>, C4<0>, C4<0>; -L_0x24d9840 .delay (10000,10000,10000) L_0x24d9840/d; -L_0x24d9900/d .functor NAND 1, L_0x24d9780, L_0x24d9840, L_0x24d7890, C4<1>; -L_0x24d9900 .delay (10000,10000,10000) L_0x24d9900/d; -L_0x24d9a40/d .functor NAND 1, L_0x24d9fd0, L_0x24d9840, L_0x24d7890, C4<1>; -L_0x24d9a40 .delay (10000,10000,10000) L_0x24d9a40/d; -L_0x24d9b30/d .functor NAND 1, L_0x24d9780, L_0x24da100, L_0x24d8cb0, C4<1>; -L_0x24d9b30 .delay (10000,10000,10000) L_0x24d9b30/d; -L_0x24d9c50/d .functor NAND 1, L_0x24d9fd0, L_0x24da100, L_0x24d7890, C4<1>; -L_0x24d9c50 .delay (10000,10000,10000) L_0x24d9c50/d; -L_0x24d9df0/d .functor NAND 1, L_0x24d9900, L_0x24d9a40, L_0x24d9b30, L_0x24d9c50; -L_0x24d9df0 .delay (10000,10000,10000) L_0x24d9df0/d; -v0x24cbd50_0 .net "S0", 0 0, L_0x24d9fd0; 1 drivers -v0x24cbe10_0 .net "S1", 0 0, L_0x24da100; 1 drivers -v0x24cbeb0_0 .alias "in0", 0 0, v0x24cf450_0; -v0x24cbf50_0 .alias "in1", 0 0, v0x24cf450_0; -v0x24cc030_0 .alias "in2", 0 0, v0x24cf980_0; -v0x24cc0b0_0 .alias "in3", 0 0, v0x24cf450_0; -v0x24cc180_0 .net "nS0", 0 0, L_0x24d9780; 1 drivers -v0x24cc200_0 .net "nS1", 0 0, L_0x24d9840; 1 drivers -v0x24cc2d0_0 .alias "out", 0 0, v0x24cf780_0; -v0x24cc350_0 .net "out0", 0 0, L_0x24d9900; 1 drivers -v0x24cc3d0_0 .net "out1", 0 0, L_0x24d9a40; 1 drivers -v0x24cc470_0 .net "out2", 0 0, L_0x24d9b30; 1 drivers -v0x24cc580_0 .net "out3", 0 0, L_0x24d9c50; 1 drivers -S_0x24cb250 .scope module, "OneMux" "FourInMux" 2 195, 2 29, S_0x24a09f0; - .timescale -9 -12; -L_0x24da230/d .functor NOT 1, L_0x24daa60, C4<0>, C4<0>, C4<0>; -L_0x24da230 .delay (10000,10000,10000) L_0x24da230/d; -L_0x24da2f0/d .functor NOT 1, L_0x24dab90, C4<0>, C4<0>, C4<0>; -L_0x24da2f0 .delay (10000,10000,10000) L_0x24da2f0/d; -L_0x24da3b0/d .functor NAND 1, L_0x24da230, L_0x24da2f0, L_0x24d9560, C4<1>; -L_0x24da3b0 .delay (10000,10000,10000) L_0x24da3b0/d; -L_0x24da4b0/d .functor NAND 1, L_0x24daa60, L_0x24da2f0, L_0x24d9560, C4<1>; -L_0x24da4b0 .delay (10000,10000,10000) L_0x24da4b0/d; -L_0x24da5a0/d .functor NAND 1, L_0x24da230, L_0x24dab90, L_0x24d8cb0, C4<1>; -L_0x24da5a0 .delay (10000,10000,10000) L_0x24da5a0/d; -L_0x24da770/d .functor NAND 1, L_0x24daa60, L_0x24dab90, L_0x24d8cb0, C4<1>; -L_0x24da770 .delay (10000,10000,10000) L_0x24da770/d; -L_0x24da880/d .functor NAND 1, L_0x24da3b0, L_0x24da4b0, L_0x24da5a0, L_0x24da770; -L_0x24da880 .delay (10000,10000,10000) L_0x24da880/d; -v0x24cb340_0 .net "S0", 0 0, L_0x24daa60; 1 drivers -v0x24cb400_0 .net "S1", 0 0, L_0x24dab90; 1 drivers -v0x24cb4a0_0 .alias "in0", 0 0, v0x24cf560_0; -v0x24cb540_0 .alias "in1", 0 0, v0x24cf560_0; -v0x24cb5f0_0 .alias "in2", 0 0, v0x24cf980_0; -v0x24cb670_0 .alias "in3", 0 0, v0x24cf980_0; -v0x24cb730_0 .net "nS0", 0 0, L_0x24da230; 1 drivers -v0x24cb7b0_0 .net "nS1", 0 0, L_0x24da2f0; 1 drivers -v0x24cb880_0 .alias "out", 0 0, v0x24cf800_0; -v0x24cb930_0 .net "out0", 0 0, L_0x24da3b0; 1 drivers -v0x24cba10_0 .net "out1", 0 0, L_0x24da4b0; 1 drivers -v0x24cbab0_0 .net "out2", 0 0, L_0x24da5a0; 1 drivers -v0x24cbbc0_0 .net "out3", 0 0, L_0x24da770; 1 drivers -S_0x24a8eb0 .scope module, "TwoMux" "TwoInMux" 2 196, 2 8, S_0x24a09f0; - .timescale -9 -12; -L_0x24dacc0/d .functor NOT 1, L_0x24db110, C4<0>, C4<0>, C4<0>; -L_0x24dacc0 .delay (10000,10000,10000) L_0x24dacc0/d; -L_0x24dad60/d .functor AND 1, L_0x24d9df0, L_0x24dacc0, C4<1>, C4<1>; -L_0x24dad60 .delay (20000,20000,20000) L_0x24dad60/d; -L_0x24dae90/d .functor AND 1, L_0x24da880, L_0x24db110, C4<1>, C4<1>; -L_0x24dae90 .delay (20000,20000,20000) L_0x24dae90/d; -L_0x24dafe0/d .functor OR 1, L_0x24dad60, L_0x24dae90, C4<0>, C4<0>; -L_0x24dafe0 .delay (20000,20000,20000) L_0x24dafe0/d; -v0x247c1d0_0 .net "S", 0 0, L_0x24db110; 1 drivers -v0x24cae40_0 .alias "in0", 0 0, v0x24cf780_0; -v0x24caee0_0 .alias "in1", 0 0, v0x24cf800_0; -v0x24caf80_0 .net "nS", 0 0, L_0x24dacc0; 1 drivers -v0x24cb030_0 .net "out0", 0 0, L_0x24dad60; 1 drivers -v0x24cb0d0_0 .net "out1", 0 0, L_0x24dae90; 1 drivers -v0x24cb1b0_0 .alias "outfinal", 0 0, v0x24cf900_0; -S_0x24a9dd0 .scope module, "LastAddSubSLT" "LastAddSubSLT" 2 141; - .timescale -9 -12; -L_0x24db1b0/d .functor NOT 1, C4, C4<0>, C4<0>, C4<0>; -L_0x24db1b0 .delay (10000,10000,10000) L_0x24db1b0/d; -L_0x24db880/d .functor XOR 1, C4, L_0x24db610, C4<0>, C4<0>; -L_0x24db880 .delay (40000,40000,40000) L_0x24db880/d; -L_0x24db920/d .functor XOR 1, L_0x24db880, C4, C4<0>, C4<0>; -L_0x24db920 .delay (40000,40000,40000) L_0x24db920/d; -L_0x24dba10/d .functor AND 1, C4, L_0x24db610, C4<1>, C4<1>; -L_0x24dba10 .delay (20000,20000,20000) L_0x24dba10/d; -L_0x24dbb40/d .functor AND 1, L_0x24db880, C4, C4<1>, C4<1>; -L_0x24dbb40 .delay (20000,20000,20000) L_0x24dbb40/d; -L_0x24dbc60/d .functor OR 1, L_0x24dba10, L_0x24dbb40, C4<0>, C4<0>; -L_0x24dbc60 .delay (20000,20000,20000) L_0x24dbc60/d; -L_0x24dbe00/d .functor XOR 1, L_0x24dbc60, C4, C4<0>, C4<0>; -L_0x24dbe00 .delay (40000,40000,40000) L_0x24dbe00/d; -v0x24d0060_0 .net "A", 0 0, C4; 0 drivers -v0x24d0120_0 .net "AandB", 0 0, L_0x24dba10; 1 drivers -v0x24d01c0_0 .net "AddSubSLTSum", 0 0, L_0x24db920; 1 drivers -v0x24d0260_0 .net "AxorB", 0 0, L_0x24db880; 1 drivers -v0x24d02e0_0 .net "B", 0 0, C4; 0 drivers -v0x24d0390_0 .net "BornB", 0 0, L_0x24db610; 1 drivers -v0x24d0450_0 .net "CINandAxorB", 0 0, L_0x24dbb40; 1 drivers -v0x24d04d0_0 .net "Command", 2 0, C4; 0 drivers -v0x24d0550_0 .net "carryin", 0 0, C4; 0 drivers -v0x24d05f0_0 .net "carryout", 0 0, L_0x24dbc60; 1 drivers -v0x24d0690_0 .net "nB", 0 0, L_0x24db1b0; 1 drivers -v0x24d0740_0 .net "overflow", 0 0, L_0x24dbe00; 1 drivers -L_0x24db7e0 .part C4, 0, 1; -S_0x24cfb80 .scope module, "mux0" "TwoInMux" 2 155, 2 8, S_0x24a9dd0; - .timescale -9 -12; -L_0x24db330/d .functor NOT 1, L_0x24db7e0, C4<0>, C4<0>, C4<0>; -L_0x24db330 .delay (10000,10000,10000) L_0x24db330/d; -L_0x24db3f0/d .functor AND 1, C4, L_0x24db330, C4<1>, C4<1>; -L_0x24db3f0 .delay (20000,20000,20000) L_0x24db3f0/d; -L_0x24db500/d .functor AND 1, L_0x24db1b0, L_0x24db7e0, C4<1>, C4<1>; -L_0x24db500 .delay (20000,20000,20000) L_0x24db500/d; -L_0x24db610/d .functor OR 1, L_0x24db3f0, L_0x24db500, C4<0>, C4<0>; -L_0x24db610 .delay (20000,20000,20000) L_0x24db610/d; -v0x24cfc70_0 .net "S", 0 0, L_0x24db7e0; 1 drivers -v0x24cfcf0_0 .alias "in0", 0 0, v0x24d02e0_0; -v0x24cfd70_0 .alias "in1", 0 0, v0x24d0690_0; -v0x24cfdf0_0 .net "nS", 0 0, L_0x24db330; 1 drivers -v0x24cfea0_0 .net "out0", 0 0, L_0x24db3f0; 1 drivers -v0x24cff20_0 .net "out1", 0 0, L_0x24db500; 1 drivers -v0x24cffc0_0 .alias "outfinal", 0 0, v0x24d0390_0; -S_0x24a9b60 .scope module, "ZerothAddSubSLT" "ZerothAddSubSLT" 2 93; - .timescale -9 -12; -L_0x24dbf10/d .functor NOT 1, C4, C4<0>, C4<0>, C4<0>; -L_0x24dbf10 .delay (10000,10000,10000) L_0x24dbf10/d; -L_0x24dc600/d .functor XOR 1, C4, L_0x24dc390, C4<0>, C4<0>; -L_0x24dc600 .delay (40000,40000,40000) L_0x24dc600/d; -L_0x24dc6a0/d .functor XOR 1, L_0x24dc600, L_0x24dc790, C4<0>, C4<0>; -L_0x24dc6a0 .delay (40000,40000,40000) L_0x24dc6a0/d; -L_0x24dc880/d .functor AND 1, C4, L_0x24dc390, C4<1>, C4<1>; -L_0x24dc880 .delay (20000,20000,20000) L_0x24dc880/d; -L_0x24dca00/d .functor AND 1, L_0x24dc600, L_0x24dcaa0, C4<1>, C4<1>; -L_0x24dca00 .delay (20000,20000,20000) L_0x24dca00/d; -L_0x24dcb40/d .functor OR 1, L_0x24dc880, L_0x24dca00, C4<0>, C4<0>; -L_0x24dcb40 .delay (20000,20000,20000) L_0x24dcb40/d; -v0x24d0db0_0 .net "A", 0 0, C4; 0 drivers -v0x24d0e70_0 .net "AandB", 0 0, L_0x24dc880; 1 drivers -v0x24d0f10_0 .net "AddSubSLTSum", 0 0, L_0x24dc6a0; 1 drivers -v0x24d0fb0_0 .net "AxorB", 0 0, L_0x24dc600; 1 drivers -v0x24d1030_0 .net "B", 0 0, C4; 0 drivers -v0x24d10e0_0 .net "BornB", 0 0, L_0x24dc390; 1 drivers -v0x24d11a0_0 .net "CINandAxorB", 0 0, L_0x24dca00; 1 drivers -v0x24d1220_0 .net "Command", 2 0, C4; 0 drivers -v0x24d12a0_0 .net *"_s3", 0 0, L_0x24dc790; 1 drivers -v0x24d1340_0 .net *"_s5", 0 0, L_0x24dcaa0; 1 drivers -v0x24d13e0_0 .net "carryout", 0 0, L_0x24dcb40; 1 drivers -v0x24d1480_0 .net "nB", 0 0, L_0x24dbf10; 1 drivers -L_0x24dc560 .part C4, 0, 1; -L_0x24dc790 .part C4, 0, 1; -L_0x24dcaa0 .part C4, 0, 1; -S_0x24d0830 .scope module, "mux0" "TwoInMux" 2 107, 2 8, S_0x24a9b60; - .timescale -9 -12; -L_0x24dc0b0/d .functor NOT 1, L_0x24dc560, C4<0>, C4<0>, C4<0>; -L_0x24dc0b0 .delay (10000,10000,10000) L_0x24dc0b0/d; -L_0x24dc170/d .functor AND 1, C4, L_0x24dc0b0, C4<1>, C4<1>; -L_0x24dc170 .delay (20000,20000,20000) L_0x24dc170/d; -L_0x24dc280/d .functor AND 1, L_0x24dbf10, L_0x24dc560, C4<1>, C4<1>; -L_0x24dc280 .delay (20000,20000,20000) L_0x24dc280/d; -L_0x24dc390/d .functor OR 1, L_0x24dc170, L_0x24dc280, C4<0>, C4<0>; -L_0x24dc390 .delay (20000,20000,20000) L_0x24dc390/d; -v0x24d0920_0 .net "S", 0 0, L_0x24dc560; 1 drivers -v0x24d09e0_0 .alias "in0", 0 0, v0x24d1030_0; -v0x24d0a80_0 .alias "in1", 0 0, v0x24d1480_0; -v0x24d0b20_0 .net "nS", 0 0, L_0x24dc0b0; 1 drivers -v0x24d0bd0_0 .net "out0", 0 0, L_0x24dc170; 1 drivers -v0x24d0c70_0 .net "out1", 0 0, L_0x24dc280; 1 drivers -v0x24d0d10_0 .alias "outfinal", 0 0, v0x24d10e0_0; -S_0x24a9430 .scope module, "test32Adder" "test32Adder" 3 5; - .timescale -9 -12; -P_0x2488d08 .param/l "size" 3 7, +C4<0100>; -v0x24d6840_0 .var "A", 3 0; -RS_0x7f03c2c9b028 .resolv tri, L_0x24ddd90, L_0x24df410, L_0x24e08e0, L_0x24e20e0; -v0x24d68e0_0 .net8 "AddSubSLTSum", 3 0, RS_0x7f03c2c9b028; 4 drivers -v0x24d6990_0 .var "B", 3 0; -v0x24d6a40_0 .var "Command", 2 0; -v0x24d6af0_0 .net "SLTflag", 0 0, L_0x24e2b00; 1 drivers -v0x24d6ba0_0 .var "carryin", 3 0; -v0x24d6c20_0 .net "carryout", 0 0, L_0x24e2460; 1 drivers -v0x24d6cd0_0 .net "overflow", 0 0, L_0x24e2920; 1 drivers -RS_0x7f03c2c9b2c8 .resolv tri, L_0x24ddfe0, L_0x24df640, L_0x24e0b80, L_0x24e10d0; -v0x24d6d80_0 .net8 "subtract", 3 0, RS_0x7f03c2c9b2c8; 4 drivers -S_0x24d15a0 .scope module, "trial" "AddSubSLT32" 3 18, 2 199, S_0x24a9430; - .timescale -9 -12; -P_0x24d1168 .param/l "size" 2 216, +C4<0100>; -L_0x24e2460/d .functor OR 1, L_0x24e2770, C4<0>, C4<0>, C4<0>; -L_0x24e2460 .delay (20000,20000,20000) L_0x24e2460/d; -L_0x24e2920/d .functor XOR 1, L_0x24e2460, L_0x24e2a60, C4<0>, C4<0>; -L_0x24e2920 .delay (40000,40000,40000) L_0x24e2920/d; -L_0x24e2650/d .functor AND 1, L_0x24e2c30, L_0x24e2cd0, C4<1>, C4<1>; -L_0x24e2650 .delay (20000,20000,20000) L_0x24e2650/d; -L_0x24e2b00/d .functor AND 1, L_0x24e2650, L_0x24e2f90, C4<1>, C4<1>; -L_0x24e2b00 .delay (20000,20000,20000) L_0x24e2b00/d; -v0x24d5c70_0 .net "A", 3 0, v0x24d6840_0; 1 drivers -v0x24d5d30_0 .alias "AddSubSLTSum", 3 0, v0x24d68e0_0; -v0x24d5dd0_0 .net "B", 3 0, v0x24d6990_0; 1 drivers -RS_0x7f03c2c9b088 .resolv tri, L_0x24ddef0, L_0x24df500, L_0x24e0a10, L_0x24e21d0; -v0x24d5e70_0 .net8 "CarryoutWire", 3 0, RS_0x7f03c2c9b088; 4 drivers -v0x24d5f20_0 .net "Command", 2 0, v0x24d6a40_0; 1 drivers -v0x24d6030_0 .alias "SLTflag", 0 0, v0x24d6af0_0; -v0x24d60d0_0 .net "SLTon", 0 0, L_0x24e2650; 1 drivers -v0x24d6170_0 .net *"_s40", 0 0, L_0x24e2770; 1 drivers -v0x24d6210_0 .net/s *"_s41", 0 0, C4<0>; 1 drivers -v0x24d62b0_0 .net *"_s44", 0 0, L_0x24e2a60; 1 drivers -v0x24d6350_0 .net *"_s46", 0 0, L_0x24e2c30; 1 drivers -v0x24d63f0_0 .net *"_s48", 0 0, L_0x24e2cd0; 1 drivers -v0x24d6490_0 .net *"_s50", 0 0, L_0x24e2f90; 1 drivers -v0x24d6530_0 .net "carryin", 3 0, v0x24d6ba0_0; 1 drivers -v0x24d6650_0 .alias "carryout", 0 0, v0x24d6c20_0; -v0x24d66f0_0 .alias "overflow", 0 0, v0x24d6cd0_0; -v0x24d65b0_0 .alias "subtract", 3 0, v0x24d6d80_0; -L_0x24ddd90 .part/pv L_0x24dd8e0, 1, 1, 4; -L_0x24ddef0 .part/pv L_0x24ddc30, 1, 1, 4; -L_0x24ddfe0 .part/pv L_0x24dd560, 1, 1, 4; -L_0x24de120 .part v0x24d6840_0, 1, 1; -L_0x24de210 .part v0x24d6990_0, 1, 1; -L_0x24de340 .part RS_0x7f03c2c9b088, 0, 1; -L_0x24df410 .part/pv L_0x24def60, 2, 1, 4; -L_0x24df500 .part/pv L_0x24df2b0, 2, 1, 4; -L_0x24df640 .part/pv L_0x24dec90, 2, 1, 4; -L_0x24df730 .part v0x24d6840_0, 2, 1; -L_0x24df830 .part v0x24d6990_0, 2, 1; -L_0x24df960 .part RS_0x7f03c2c9b088, 1, 1; -L_0x24e08e0 .part/pv L_0x24e0430, 3, 1, 4; -L_0x24e0a10 .part/pv L_0x24e0780, 3, 1, 4; -L_0x24e0b80 .part/pv L_0x24e0160, 3, 1, 4; -L_0x24e0cb0 .part v0x24d6840_0, 3, 1; -L_0x24e0e70 .part v0x24d6990_0, 3, 1; -L_0x24e1030 .part RS_0x7f03c2c9b088, 2, 1; -L_0x24e20e0 .part/pv L_0x24e1c50, 0, 1, 4; -L_0x24e21d0 .part/pv L_0x24e1fa0, 0, 1, 4; -L_0x24e10d0 .part/pv L_0x24dd740, 0, 1, 4; -L_0x24e23c0 .part v0x24d6840_0, 0, 1; -L_0x24e22c0 .part v0x24d6990_0, 0, 1; -L_0x24e25b0 .part RS_0x7f03c2c9b2c8, 0, 1; -L_0x24e2770 .part RS_0x7f03c2c9b088, 3, 1; -L_0x24e2a60 .part RS_0x7f03c2c9b088, 2, 1; -L_0x24e2c30 .part v0x24d6a40_0, 1, 1; -L_0x24e2cd0 .part RS_0x7f03c2c9b2c8, 0, 1; -L_0x24e2f90 .part RS_0x7f03c2c9b028, 3, 1; -S_0x24d4c60 .scope module, "attempt2" "MiddleAddSubSLT" 2 213, 2 115, S_0x24d15a0; - .timescale -9 -12; -L_0x24e0de0/d .functor NOT 1, L_0x24e22c0, C4<0>, C4<0>, C4<0>; -L_0x24e0de0 .delay (10000,10000,10000) L_0x24e0de0/d; -L_0x24e1700/d .functor NOT 1, L_0x24e17c0, C4<0>, C4<0>, C4<0>; -L_0x24e1700 .delay (10000,10000,10000) L_0x24e1700/d; -L_0x24dd740/d .functor AND 1, L_0x24e1ac0, L_0x24e1700, C4<1>, C4<1>; -L_0x24dd740 .delay (20000,20000,20000) L_0x24dd740/d; -L_0x24e1b60/d .functor XOR 1, L_0x24e23c0, L_0x24e1490, C4<0>, C4<0>; -L_0x24e1b60 .delay (40000,40000,40000) L_0x24e1b60/d; -L_0x24e1c50/d .functor XOR 1, L_0x24e1b60, L_0x24e25b0, C4<0>, C4<0>; -L_0x24e1c50 .delay (40000,40000,40000) L_0x24e1c50/d; -L_0x24e1d40/d .functor AND 1, L_0x24e23c0, L_0x24e1490, C4<1>, C4<1>; -L_0x24e1d40 .delay (20000,20000,20000) L_0x24e1d40/d; -L_0x24e1eb0/d .functor AND 1, L_0x24e1b60, L_0x24e25b0, C4<1>, C4<1>; -L_0x24e1eb0 .delay (20000,20000,20000) L_0x24e1eb0/d; -L_0x24e1fa0/d .functor OR 1, L_0x24e1d40, L_0x24e1eb0, C4<0>, C4<0>; -L_0x24e1fa0 .delay (20000,20000,20000) L_0x24e1fa0/d; -v0x24d52d0_0 .net "A", 0 0, L_0x24e23c0; 1 drivers -v0x24d5390_0 .net "AandB", 0 0, L_0x24e1d40; 1 drivers -v0x24d5430_0 .net "AddSubSLTSum", 0 0, L_0x24e1c50; 1 drivers -v0x24d54d0_0 .net "AxorB", 0 0, L_0x24e1b60; 1 drivers -v0x24d5550_0 .net "B", 0 0, L_0x24e22c0; 1 drivers -v0x24d5600_0 .net "BornB", 0 0, L_0x24e1490; 1 drivers -v0x24d56c0_0 .net "CINandAxorB", 0 0, L_0x24e1eb0; 1 drivers -v0x24d5740_0 .alias "Command", 2 0, v0x24d5f20_0; -v0x24d57c0_0 .net *"_s3", 0 0, L_0x24e17c0; 1 drivers -v0x24d5840_0 .net *"_s5", 0 0, L_0x24e1ac0; 1 drivers -v0x24d58e0_0 .net "carryin", 0 0, L_0x24e25b0; 1 drivers -v0x24d5980_0 .net "carryout", 0 0, L_0x24e1fa0; 1 drivers -v0x24d5a20_0 .net "nB", 0 0, L_0x24e0de0; 1 drivers -v0x24d5ad0_0 .net "nCmd2", 0 0, L_0x24e1700; 1 drivers -v0x24d5bd0_0 .net "subtract", 0 0, L_0x24dd740; 1 drivers -L_0x24e1660 .part v0x24d6a40_0, 0, 1; -L_0x24e17c0 .part v0x24d6a40_0, 2, 1; -L_0x24e1ac0 .part v0x24d6a40_0, 0, 1; -S_0x24d4d50 .scope module, "mux0" "TwoInMux" 2 131, 2 8, S_0x24d4c60; - .timescale -9 -12; -L_0x24e11b0/d .functor NOT 1, L_0x24e1660, C4<0>, C4<0>, C4<0>; -L_0x24e11b0 .delay (10000,10000,10000) L_0x24e11b0/d; -L_0x24e1270/d .functor AND 1, L_0x24e22c0, L_0x24e11b0, C4<1>, C4<1>; -L_0x24e1270 .delay (20000,20000,20000) L_0x24e1270/d; -L_0x24e1380/d .functor AND 1, L_0x24e0de0, L_0x24e1660, C4<1>, C4<1>; -L_0x24e1380 .delay (20000,20000,20000) L_0x24e1380/d; -L_0x24e1490/d .functor OR 1, L_0x24e1270, L_0x24e1380, C4<0>, C4<0>; -L_0x24e1490 .delay (20000,20000,20000) L_0x24e1490/d; -v0x24d4e40_0 .net "S", 0 0, L_0x24e1660; 1 drivers -v0x24d4f00_0 .alias "in0", 0 0, v0x24d5550_0; -v0x24d4fa0_0 .alias "in1", 0 0, v0x24d5a20_0; -v0x24d5040_0 .net "nS", 0 0, L_0x24e11b0; 1 drivers -v0x24d50f0_0 .net "out0", 0 0, L_0x24e1270; 1 drivers -v0x24d5190_0 .net "out1", 0 0, L_0x24e1380; 1 drivers -v0x24d5230_0 .alias "outfinal", 0 0, v0x24d5600_0; -S_0x24d3af0 .scope generate, "addbits[1]" "addbits[1]" 2 218, 2 218, S_0x24d15a0; - .timescale -9 -12; -P_0x24d34f8 .param/l "i" 2 218, +C4<01>; -S_0x24d3c60 .scope module, "attempt" "MiddleAddSubSLT" 2 220, 2 115, S_0x24d3af0; - .timescale -9 -12; -L_0x24dcd10/d .functor NOT 1, L_0x24de210, C4<0>, C4<0>, C4<0>; -L_0x24dcd10 .delay (10000,10000,10000) L_0x24dcd10/d; -L_0x24dd400/d .functor NOT 1, L_0x24dd4c0, C4<0>, C4<0>, C4<0>; -L_0x24dd400 .delay (10000,10000,10000) L_0x24dd400/d; -L_0x24dd560/d .functor AND 1, L_0x24dd6a0, L_0x24dd400, C4<1>, C4<1>; -L_0x24dd560 .delay (20000,20000,20000) L_0x24dd560/d; -L_0x24d5fa0/d .functor XOR 1, L_0x24de120, L_0x24dd190, C4<0>, C4<0>; -L_0x24d5fa0 .delay (40000,40000,40000) L_0x24d5fa0/d; -L_0x24dd8e0/d .functor XOR 1, L_0x24d5fa0, L_0x24de340, C4<0>, C4<0>; -L_0x24dd8e0 .delay (40000,40000,40000) L_0x24dd8e0/d; -L_0x24dd9d0/d .functor AND 1, L_0x24de120, L_0x24dd190, C4<1>, C4<1>; -L_0x24dd9d0 .delay (20000,20000,20000) L_0x24dd9d0/d; -L_0x24ddb40/d .functor AND 1, L_0x24d5fa0, L_0x24de340, C4<1>, C4<1>; -L_0x24ddb40 .delay (20000,20000,20000) L_0x24ddb40/d; -L_0x24ddc30/d .functor OR 1, L_0x24dd9d0, L_0x24ddb40, C4<0>, C4<0>; -L_0x24ddc30 .delay (20000,20000,20000) L_0x24ddc30/d; -v0x24d42f0_0 .net "A", 0 0, L_0x24de120; 1 drivers -v0x24d43b0_0 .net "AandB", 0 0, L_0x24dd9d0; 1 drivers -v0x24d4450_0 .net "AddSubSLTSum", 0 0, L_0x24dd8e0; 1 drivers -v0x24d44f0_0 .net "AxorB", 0 0, L_0x24d5fa0; 1 drivers -v0x24d4570_0 .net "B", 0 0, L_0x24de210; 1 drivers -v0x24d4620_0 .net "BornB", 0 0, L_0x24dd190; 1 drivers -v0x24d46e0_0 .net "CINandAxorB", 0 0, L_0x24ddb40; 1 drivers -v0x24d4760_0 .alias "Command", 2 0, v0x24d5f20_0; -v0x24d47e0_0 .net *"_s3", 0 0, L_0x24dd4c0; 1 drivers -v0x24d4860_0 .net *"_s5", 0 0, L_0x24dd6a0; 1 drivers -v0x24d4900_0 .net "carryin", 0 0, L_0x24de340; 1 drivers -v0x24d49a0_0 .net "carryout", 0 0, L_0x24ddc30; 1 drivers -v0x24d4a40_0 .net "nB", 0 0, L_0x24dcd10; 1 drivers -v0x24d4ac0_0 .net "nCmd2", 0 0, L_0x24dd400; 1 drivers -v0x24d4bc0_0 .net "subtract", 0 0, L_0x24dd560; 1 drivers -L_0x24dd360 .part v0x24d6a40_0, 0, 1; -L_0x24dd4c0 .part v0x24d6a40_0, 2, 1; -L_0x24dd6a0 .part v0x24d6a40_0, 0, 1; -S_0x24d3d50 .scope module, "mux0" "TwoInMux" 2 131, 2 8, S_0x24d3c60; - .timescale -9 -12; -L_0x24dceb0/d .functor NOT 1, L_0x24dd360, C4<0>, C4<0>, C4<0>; -L_0x24dceb0 .delay (10000,10000,10000) L_0x24dceb0/d; -L_0x24dcf70/d .functor AND 1, L_0x24de210, L_0x24dceb0, C4<1>, C4<1>; -L_0x24dcf70 .delay (20000,20000,20000) L_0x24dcf70/d; -L_0x24dd080/d .functor AND 1, L_0x24dcd10, L_0x24dd360, C4<1>, C4<1>; -L_0x24dd080 .delay (20000,20000,20000) L_0x24dd080/d; -L_0x24dd190/d .functor OR 1, L_0x24dcf70, L_0x24dd080, C4<0>, C4<0>; -L_0x24dd190 .delay (20000,20000,20000) L_0x24dd190/d; -v0x24d3e40_0 .net "S", 0 0, L_0x24dd360; 1 drivers -v0x24d3ee0_0 .alias "in0", 0 0, v0x24d4570_0; -v0x24d3f80_0 .alias "in1", 0 0, v0x24d4a40_0; -v0x24d4020_0 .net "nS", 0 0, L_0x24dceb0; 1 drivers -v0x24d40d0_0 .net "out0", 0 0, L_0x24dcf70; 1 drivers -v0x24d4170_0 .net "out1", 0 0, L_0x24dd080; 1 drivers -v0x24d4250_0 .alias "outfinal", 0 0, v0x24d4620_0; -S_0x24d2940 .scope generate, "addbits[2]" "addbits[2]" 2 218, 2 218, S_0x24d15a0; - .timescale -9 -12; -P_0x24d22c8 .param/l "i" 2 218, +C4<010>; -S_0x24d2ab0 .scope module, "attempt" "MiddleAddSubSLT" 2 220, 2 115, S_0x24d2940; - .timescale -9 -12; -L_0x24de430/d .functor NOT 1, L_0x24df830, C4<0>, C4<0>, C4<0>; -L_0x24de430 .delay (10000,10000,10000) L_0x24de430/d; -L_0x24deb30/d .functor NOT 1, L_0x24debf0, C4<0>, C4<0>, C4<0>; -L_0x24deb30 .delay (10000,10000,10000) L_0x24deb30/d; -L_0x24dec90/d .functor AND 1, L_0x24dedd0, L_0x24deb30, C4<1>, C4<1>; -L_0x24dec90 .delay (20000,20000,20000) L_0x24dec90/d; -L_0x24dee70/d .functor XOR 1, L_0x24df730, L_0x24de8c0, C4<0>, C4<0>; -L_0x24dee70 .delay (40000,40000,40000) L_0x24dee70/d; -L_0x24def60/d .functor XOR 1, L_0x24dee70, L_0x24df960, C4<0>, C4<0>; -L_0x24def60 .delay (40000,40000,40000) L_0x24def60/d; -L_0x24df050/d .functor AND 1, L_0x24df730, L_0x24de8c0, C4<1>, C4<1>; -L_0x24df050 .delay (20000,20000,20000) L_0x24df050/d; -L_0x24df1c0/d .functor AND 1, L_0x24dee70, L_0x24df960, C4<1>, C4<1>; -L_0x24df1c0 .delay (20000,20000,20000) L_0x24df1c0/d; -L_0x24df2b0/d .functor OR 1, L_0x24df050, L_0x24df1c0, C4<0>, C4<0>; -L_0x24df2b0 .delay (20000,20000,20000) L_0x24df2b0/d; -v0x24d3140_0 .net "A", 0 0, L_0x24df730; 1 drivers -v0x24d3200_0 .net "AandB", 0 0, L_0x24df050; 1 drivers -v0x24d32a0_0 .net "AddSubSLTSum", 0 0, L_0x24def60; 1 drivers -v0x24d3340_0 .net "AxorB", 0 0, L_0x24dee70; 1 drivers -v0x24d33c0_0 .net "B", 0 0, L_0x24df830; 1 drivers -v0x24d3470_0 .net "BornB", 0 0, L_0x24de8c0; 1 drivers -v0x24d3530_0 .net "CINandAxorB", 0 0, L_0x24df1c0; 1 drivers -v0x24d35b0_0 .alias "Command", 2 0, v0x24d5f20_0; -v0x24d3660_0 .net *"_s3", 0 0, L_0x24debf0; 1 drivers -v0x24d36e0_0 .net *"_s5", 0 0, L_0x24dedd0; 1 drivers -v0x24d3760_0 .net "carryin", 0 0, L_0x24df960; 1 drivers -v0x24d3800_0 .net "carryout", 0 0, L_0x24df2b0; 1 drivers -v0x24d38a0_0 .net "nB", 0 0, L_0x24de430; 1 drivers -v0x24d3950_0 .net "nCmd2", 0 0, L_0x24deb30; 1 drivers -v0x24d3a50_0 .net "subtract", 0 0, L_0x24dec90; 1 drivers -L_0x24dea90 .part v0x24d6a40_0, 0, 1; -L_0x24debf0 .part v0x24d6a40_0, 2, 1; -L_0x24dedd0 .part v0x24d6a40_0, 0, 1; -S_0x24d2ba0 .scope module, "mux0" "TwoInMux" 2 131, 2 8, S_0x24d2ab0; - .timescale -9 -12; -L_0x24de5e0/d .functor NOT 1, L_0x24dea90, C4<0>, C4<0>, C4<0>; -L_0x24de5e0 .delay (10000,10000,10000) L_0x24de5e0/d; -L_0x24de6a0/d .functor AND 1, L_0x24df830, L_0x24de5e0, C4<1>, C4<1>; -L_0x24de6a0 .delay (20000,20000,20000) L_0x24de6a0/d; -L_0x24de7b0/d .functor AND 1, L_0x24de430, L_0x24dea90, C4<1>, C4<1>; -L_0x24de7b0 .delay (20000,20000,20000) L_0x24de7b0/d; -L_0x24de8c0/d .functor OR 1, L_0x24de6a0, L_0x24de7b0, C4<0>, C4<0>; -L_0x24de8c0 .delay (20000,20000,20000) L_0x24de8c0/d; -v0x24d2c90_0 .net "S", 0 0, L_0x24dea90; 1 drivers -v0x24d2d30_0 .alias "in0", 0 0, v0x24d33c0_0; -v0x24d2dd0_0 .alias "in1", 0 0, v0x24d38a0_0; -v0x24d2e70_0 .net "nS", 0 0, L_0x24de5e0; 1 drivers -v0x24d2f20_0 .net "out0", 0 0, L_0x24de6a0; 1 drivers -v0x24d2fc0_0 .net "out1", 0 0, L_0x24de7b0; 1 drivers -v0x24d30a0_0 .alias "outfinal", 0 0, v0x24d3470_0; -S_0x24d16f0 .scope generate, "addbits[3]" "addbits[3]" 2 218, 2 218, S_0x24d15a0; - .timescale -9 -12; -P_0x24d17e8 .param/l "i" 2 218, +C4<011>; -S_0x24d1880 .scope module, "attempt" "MiddleAddSubSLT" 2 220, 2 115, S_0x24d16f0; - .timescale -9 -12; -L_0x24df7d0/d .functor NOT 1, L_0x24e0e70, C4<0>, C4<0>, C4<0>; -L_0x24df7d0 .delay (10000,10000,10000) L_0x24df7d0/d; -L_0x24e0000/d .functor NOT 1, L_0x24e00c0, C4<0>, C4<0>, C4<0>; -L_0x24e0000 .delay (10000,10000,10000) L_0x24e0000/d; -L_0x24e0160/d .functor AND 1, L_0x24e02a0, L_0x24e0000, C4<1>, C4<1>; -L_0x24e0160 .delay (20000,20000,20000) L_0x24e0160/d; -L_0x24e0340/d .functor XOR 1, L_0x24e0cb0, L_0x24dfd90, C4<0>, C4<0>; -L_0x24e0340 .delay (40000,40000,40000) L_0x24e0340/d; -L_0x24e0430/d .functor XOR 1, L_0x24e0340, L_0x24e1030, C4<0>, C4<0>; -L_0x24e0430 .delay (40000,40000,40000) L_0x24e0430/d; -L_0x24e0520/d .functor AND 1, L_0x24e0cb0, L_0x24dfd90, C4<1>, C4<1>; -L_0x24e0520 .delay (20000,20000,20000) L_0x24e0520/d; -L_0x24e0690/d .functor AND 1, L_0x24e0340, L_0x24e1030, C4<1>, C4<1>; -L_0x24e0690 .delay (20000,20000,20000) L_0x24e0690/d; -L_0x24e0780/d .functor OR 1, L_0x24e0520, L_0x24e0690, C4<0>, C4<0>; -L_0x24e0780 .delay (20000,20000,20000) L_0x24e0780/d; -v0x24d1f10_0 .net "A", 0 0, L_0x24e0cb0; 1 drivers -v0x24d1fd0_0 .net "AandB", 0 0, L_0x24e0520; 1 drivers -v0x24d2070_0 .net "AddSubSLTSum", 0 0, L_0x24e0430; 1 drivers -v0x24d2110_0 .net "AxorB", 0 0, L_0x24e0340; 1 drivers -v0x24d2190_0 .net "B", 0 0, L_0x24e0e70; 1 drivers -v0x24d2240_0 .net "BornB", 0 0, L_0x24dfd90; 1 drivers -v0x24d2300_0 .net "CINandAxorB", 0 0, L_0x24e0690; 1 drivers -v0x24d2380_0 .alias "Command", 2 0, v0x24d5f20_0; -v0x24d2400_0 .net *"_s3", 0 0, L_0x24e00c0; 1 drivers -v0x24d24a0_0 .net *"_s5", 0 0, L_0x24e02a0; 1 drivers -v0x24d2540_0 .net "carryin", 0 0, L_0x24e1030; 1 drivers -v0x24d25e0_0 .net "carryout", 0 0, L_0x24e0780; 1 drivers -v0x24d26f0_0 .net "nB", 0 0, L_0x24df7d0; 1 drivers -v0x24d27a0_0 .net "nCmd2", 0 0, L_0x24e0000; 1 drivers -v0x24d28a0_0 .net "subtract", 0 0, L_0x24e0160; 1 drivers -L_0x24dff60 .part v0x24d6a40_0, 0, 1; -L_0x24e00c0 .part v0x24d6a40_0, 2, 1; -L_0x24e02a0 .part v0x24d6a40_0, 0, 1; -S_0x24d1970 .scope module, "mux0" "TwoInMux" 2 131, 2 8, S_0x24d1880; - .timescale -9 -12; -L_0x24dfaf0/d .functor NOT 1, L_0x24dff60, C4<0>, C4<0>, C4<0>; -L_0x24dfaf0 .delay (10000,10000,10000) L_0x24dfaf0/d; -L_0x24dfb70/d .functor AND 1, L_0x24e0e70, L_0x24dfaf0, C4<1>, C4<1>; -L_0x24dfb70 .delay (20000,20000,20000) L_0x24dfb70/d; -L_0x24dfc80/d .functor AND 1, L_0x24df7d0, L_0x24dff60, C4<1>, C4<1>; -L_0x24dfc80 .delay (20000,20000,20000) L_0x24dfc80/d; -L_0x24dfd90/d .functor OR 1, L_0x24dfb70, L_0x24dfc80, C4<0>, C4<0>; -L_0x24dfd90 .delay (20000,20000,20000) L_0x24dfd90/d; -v0x24d1a60_0 .net "S", 0 0, L_0x24dff60; 1 drivers -v0x24d1b00_0 .alias "in0", 0 0, v0x24d2190_0; -v0x24d1ba0_0 .alias "in1", 0 0, v0x24d26f0_0; -v0x24d1c40_0 .net "nS", 0 0, L_0x24dfaf0; 1 drivers -v0x24d1cf0_0 .net "out0", 0 0, L_0x24dfb70; 1 drivers -v0x24d1d90_0 .net "out1", 0 0, L_0x24dfc80; 1 drivers -v0x24d1e70_0 .alias "outfinal", 0 0, v0x24d2240_0; - .scope S_0x24a9430; +S_0x178b140 .scope module, "Bitslice" "Bitslice" 2 121; + .timescale -9 -12; +v0x17ba940_0 .net "A", 0 0, C4; 0 drivers +v0x17ba9e0_0 .net "AddSubSLTSum", 0 0, C4; 0 drivers +v0x17baa80_0 .net "AddSumSLTSum", 0 0, L_0x17de9e0; 1 drivers +v0x17bab90_0 .net "AndNandOut", 0 0, L_0x17e06b0; 1 drivers +v0x17baca0_0 .net "B", 0 0, C4; 0 drivers +v0x17badb0_0 .net "Cmd0Start", 0 0, L_0x17e0ee0; 1 drivers +v0x17bae30_0 .net "Cmd1Start", 0 0, L_0x17e1910; 1 drivers +v0x17baeb0_0 .net "Command", 2 0, C4; 0 drivers +v0x17baf30_0 .net "OneBitFinalOut", 0 0, L_0x17e2070; 1 drivers +v0x17bafb0_0 .net "OrNorXorOut", 0 0, L_0x17dfe00; 1 drivers +v0x17bb030_0 .net "carryin", 0 0, C4; 0 drivers +v0x17bb0b0_0 .net "carryout", 0 0, L_0x17ded90; 1 drivers +v0x17bb130_0 .net "subtract", 0 0, L_0x17de6b0; 1 drivers +L_0x17e10c0 .part C4, 0, 1; +L_0x17e11f0 .part C4, 1, 1; +L_0x17e1af0 .part C4, 0, 1; +L_0x17e1c20 .part C4, 1, 1; +L_0x17e21a0 .part C4, 2, 1; +S_0x17b98e0 .scope module, "rottenpotato" "MiddleAddSubSLT" 2 147, 2 95, S_0x178b140; + .timescale -9 -12; +L_0x17d9050/d .functor NOT 1, C4, C4<0>, C4<0>, C4<0>; +L_0x17d9050 .delay (10000,10000,10000) L_0x17d9050/d; +L_0x17de550/d .functor NOT 1, L_0x17de610, C4<0>, C4<0>, C4<0>; +L_0x17de550 .delay (10000,10000,10000) L_0x17de550/d; +L_0x17de6b0/d .functor AND 1, L_0x17de7f0, L_0x17de550, C4<1>, C4<1>; +L_0x17de6b0 .delay (20000,20000,20000) L_0x17de6b0/d; +L_0x17de890/d .functor XOR 1, C4, L_0x17de250, C4<0>, C4<0>; +L_0x17de890 .delay (40000,40000,40000) L_0x17de890/d; +L_0x17de9e0/d .functor XOR 1, L_0x17de890, C4, C4<0>, C4<0>; +L_0x17de9e0 .delay (40000,40000,40000) L_0x17de9e0/d; +L_0x17deb40/d .functor AND 1, C4, L_0x17de250, C4<1>, C4<1>; +L_0x17deb40 .delay (20000,20000,20000) L_0x17deb40/d; +L_0x17decd0/d .functor AND 1, L_0x17de890, C4, C4<1>, C4<1>; +L_0x17decd0 .delay (20000,20000,20000) L_0x17decd0/d; +L_0x17ded90/d .functor OR 1, L_0x17deb40, L_0x17decd0, C4<0>, C4<0>; +L_0x17ded90 .delay (20000,20000,20000) L_0x17ded90/d; +v0x17b9e60_0 .alias "A", 0 0, v0x17ba940_0; +v0x17b9f50_0 .net "AandB", 0 0, L_0x17deb40; 1 drivers +v0x17b9ff0_0 .alias "AddSubSLTSum", 0 0, v0x17baa80_0; +v0x17ba070_0 .net "AxorB", 0 0, L_0x17de890; 1 drivers +v0x17ba0f0_0 .alias "B", 0 0, v0x17baca0_0; +v0x17ba170_0 .net "BornB", 0 0, L_0x17de250; 1 drivers +v0x17ba230_0 .net "CINandAxorB", 0 0, L_0x17decd0; 1 drivers +v0x17ba2b0_0 .alias "Command", 2 0, v0x17baeb0_0; +v0x17ba3d0_0 .net *"_s3", 0 0, L_0x17de610; 1 drivers +v0x17ba470_0 .net *"_s5", 0 0, L_0x17de7f0; 1 drivers +v0x17ba570_0 .alias "carryin", 0 0, v0x17bb030_0; +v0x17ba610_0 .alias "carryout", 0 0, v0x17bb0b0_0; +v0x17ba720_0 .net "nB", 0 0, L_0x17d9050; 1 drivers +v0x17ba7a0_0 .net "nCmd2", 0 0, L_0x17de550; 1 drivers +v0x17ba8a0_0 .alias "subtract", 0 0, v0x17bb130_0; +L_0x17de420 .part C4, 0, 1; +L_0x17de610 .part C4, 2, 1; +L_0x17de7f0 .part C4, 0, 1; +S_0x17b99d0 .scope module, "mux0" "TwoInMux" 2 111, 2 8, S_0x17b98e0; + .timescale -9 -12; +L_0x17ddf70/d .functor NOT 1, L_0x17de420, C4<0>, C4<0>, C4<0>; +L_0x17ddf70 .delay (10000,10000,10000) L_0x17ddf70/d; +L_0x17de030/d .functor AND 1, C4, L_0x17ddf70, C4<1>, C4<1>; +L_0x17de030 .delay (20000,20000,20000) L_0x17de030/d; +L_0x17de140/d .functor AND 1, L_0x17d9050, L_0x17de420, C4<1>, C4<1>; +L_0x17de140 .delay (20000,20000,20000) L_0x17de140/d; +L_0x17de250/d .functor OR 1, L_0x17de030, L_0x17de140, C4<0>, C4<0>; +L_0x17de250 .delay (20000,20000,20000) L_0x17de250/d; +v0x17b9ac0_0 .net "S", 0 0, L_0x17de420; 1 drivers +v0x17b9b40_0 .alias "in0", 0 0, v0x17baca0_0; +v0x17b9bc0_0 .alias "in1", 0 0, v0x17ba720_0; +v0x17b9c40_0 .net "nS", 0 0, L_0x17ddf70; 1 drivers +v0x17b9cc0_0 .net "out0", 0 0, L_0x17de030; 1 drivers +v0x17b9d40_0 .net "out1", 0 0, L_0x17de140; 1 drivers +v0x17b9dc0_0 .alias "outfinal", 0 0, v0x17ba170_0; +S_0x17b85f0 .scope module, "idahopotato" "OrNorXor" 2 148, 2 70, S_0x178b140; + .timescale -9 -12; +L_0x17def10/d .functor NOR 1, C4, C4, C4<0>, C4<0>; +L_0x17def10 .delay (10000,10000,10000) L_0x17def10/d; +L_0x17df070/d .functor NOT 1, L_0x17def10, C4<0>, C4<0>, C4<0>; +L_0x17df070 .delay (10000,10000,10000) L_0x17df070/d; +L_0x17df1a0/d .functor NAND 1, C4, C4, C4<1>, C4<1>; +L_0x17df1a0 .delay (10000,10000,10000) L_0x17df1a0/d; +L_0x17df330/d .functor NAND 1, L_0x17df1a0, L_0x17df070, C4<1>, C4<1>; +L_0x17df330 .delay (10000,10000,10000) L_0x17df330/d; +L_0x17df420/d .functor NOT 1, L_0x17df330, C4<0>, C4<0>, C4<0>; +L_0x17df420 .delay (10000,10000,10000) L_0x17df420/d; +v0x17b91a0_0 .alias "A", 0 0, v0x17ba940_0; +v0x17b9250_0 .net "AnandB", 0 0, L_0x17df1a0; 1 drivers +v0x17b92d0_0 .net "AnorB", 0 0, L_0x17def10; 1 drivers +v0x17b9380_0 .net "AorB", 0 0, L_0x17df070; 1 drivers +v0x17b9460_0 .net "AxorB", 0 0, L_0x17df420; 1 drivers +v0x17b9510_0 .alias "B", 0 0, v0x17baca0_0; +v0x17b95d0_0 .alias "Command", 2 0, v0x17baeb0_0; +v0x17b9680_0 .alias "OrNorXorOut", 0 0, v0x17bafb0_0; +v0x17b97e0_0 .net "XorNor", 0 0, L_0x17df880; 1 drivers +v0x17b9860_0 .net "nXor", 0 0, L_0x17df330; 1 drivers +L_0x17dfa00 .part C4, 2, 1; +L_0x17dff80 .part C4, 0, 1; +S_0x17b8c30 .scope module, "mux0" "TwoInMux" 2 89, 2 8, S_0x17b85f0; + .timescale -9 -12; +L_0x17df560/d .functor NOT 1, L_0x17dfa00, C4<0>, C4<0>, C4<0>; +L_0x17df560 .delay (10000,10000,10000) L_0x17df560/d; +L_0x17df620/d .functor AND 1, L_0x17df420, L_0x17df560, C4<1>, C4<1>; +L_0x17df620 .delay (20000,20000,20000) L_0x17df620/d; +L_0x17df730/d .functor AND 1, L_0x17def10, L_0x17dfa00, C4<1>, C4<1>; +L_0x17df730 .delay (20000,20000,20000) L_0x17df730/d; +L_0x17df880/d .functor OR 1, L_0x17df620, L_0x17df730, C4<0>, C4<0>; +L_0x17df880 .delay (20000,20000,20000) L_0x17df880/d; +v0x17b8d20_0 .net "S", 0 0, L_0x17dfa00; 1 drivers +v0x17b8de0_0 .alias "in0", 0 0, v0x17b9460_0; +v0x17b8e80_0 .alias "in1", 0 0, v0x17b92d0_0; +v0x17b8f20_0 .net "nS", 0 0, L_0x17df560; 1 drivers +v0x17b8fa0_0 .net "out0", 0 0, L_0x17df620; 1 drivers +v0x17b9040_0 .net "out1", 0 0, L_0x17df730; 1 drivers +v0x17b9120_0 .alias "outfinal", 0 0, v0x17b97e0_0; +S_0x17b86e0 .scope module, "mux1" "TwoInMux" 2 90, 2 8, S_0x17b85f0; + .timescale -9 -12; +L_0x17dfaa0/d .functor NOT 1, L_0x17dff80, C4<0>, C4<0>, C4<0>; +L_0x17dfaa0 .delay (10000,10000,10000) L_0x17dfaa0/d; +L_0x17dfb60/d .functor AND 1, L_0x17df880, L_0x17dfaa0, C4<1>, C4<1>; +L_0x17dfb60 .delay (20000,20000,20000) L_0x17dfb60/d; +L_0x17dfcb0/d .functor AND 1, L_0x17df070, L_0x17dff80, C4<1>, C4<1>; +L_0x17dfcb0 .delay (20000,20000,20000) L_0x17dfcb0/d; +L_0x17dfe00/d .functor OR 1, L_0x17dfb60, L_0x17dfcb0, C4<0>, C4<0>; +L_0x17dfe00 .delay (20000,20000,20000) L_0x17dfe00/d; +v0x17b87d0_0 .net "S", 0 0, L_0x17dff80; 1 drivers +v0x17b8870_0 .alias "in0", 0 0, v0x17b97e0_0; +v0x17b8910_0 .alias "in1", 0 0, v0x17b9380_0; +v0x17b89b0_0 .net "nS", 0 0, L_0x17dfaa0; 1 drivers +v0x17b8a30_0 .net "out0", 0 0, L_0x17dfb60; 1 drivers +v0x17b8ad0_0 .net "out1", 0 0, L_0x17dfcb0; 1 drivers +v0x17b8bb0_0 .alias "outfinal", 0 0, v0x17bafb0_0; +S_0x17b7c50 .scope module, "sweetpotato" "AndNand" 2 149, 2 53, S_0x178b140; + .timescale -9 -12; +L_0x17de4c0/d .functor NAND 1, C4, C4, C4<1>, C4<1>; +L_0x17de4c0 .delay (10000,10000,10000) L_0x17de4c0/d; +L_0x17e0260/d .functor NOT 1, L_0x17de4c0, C4<0>, C4<0>, C4<0>; +L_0x17e0260 .delay (10000,10000,10000) L_0x17e0260/d; +v0x17b8270_0 .alias "A", 0 0, v0x17ba940_0; +v0x17b8330_0 .net "AandB", 0 0, L_0x17e0260; 1 drivers +v0x17b83b0_0 .net "AnandB", 0 0, L_0x17de4c0; 1 drivers +v0x17b8430_0 .alias "AndNandOut", 0 0, v0x17bab90_0; +v0x17b84b0_0 .alias "B", 0 0, v0x17baca0_0; +v0x17b8530_0 .alias "Command", 2 0, v0x17baeb0_0; +L_0x17e0830 .part C4, 0, 1; +S_0x17b7d40 .scope module, "potato" "TwoInMux" 2 66, 2 8, S_0x17b7c50; + .timescale -9 -12; +L_0x17e0390/d .functor NOT 1, L_0x17e0830, C4<0>, C4<0>, C4<0>; +L_0x17e0390 .delay (10000,10000,10000) L_0x17e0390/d; +L_0x17e0450/d .functor AND 1, L_0x17e0260, L_0x17e0390, C4<1>, C4<1>; +L_0x17e0450 .delay (20000,20000,20000) L_0x17e0450/d; +L_0x17e0560/d .functor AND 1, L_0x17de4c0, L_0x17e0830, C4<1>, C4<1>; +L_0x17e0560 .delay (20000,20000,20000) L_0x17e0560/d; +L_0x17e06b0/d .functor OR 1, L_0x17e0450, L_0x17e0560, C4<0>, C4<0>; +L_0x17e06b0 .delay (20000,20000,20000) L_0x17e06b0/d; +v0x17b7e30_0 .net "S", 0 0, L_0x17e0830; 1 drivers +v0x17b7ef0_0 .alias "in0", 0 0, v0x17b8330_0; +v0x17b7f90_0 .alias "in1", 0 0, v0x17b83b0_0; +v0x17b8030_0 .net "nS", 0 0, L_0x17e0390; 1 drivers +v0x17b80b0_0 .net "out0", 0 0, L_0x17e0450; 1 drivers +v0x17b8150_0 .net "out1", 0 0, L_0x17e0560; 1 drivers +v0x17b81f0_0 .alias "outfinal", 0 0, v0x17bab90_0; +S_0x17b7290 .scope module, "ZeroMux" "FourInMux" 2 151, 2 29, S_0x178b140; + .timescale -9 -12; +L_0x17e08d0/d .functor NOT 1, L_0x17e10c0, C4<0>, C4<0>, C4<0>; +L_0x17e08d0 .delay (10000,10000,10000) L_0x17e08d0/d; +L_0x17e0990/d .functor NOT 1, L_0x17e11f0, C4<0>, C4<0>, C4<0>; +L_0x17e0990 .delay (10000,10000,10000) L_0x17e0990/d; +L_0x17e0a50/d .functor NAND 1, L_0x17e08d0, L_0x17e0990, L_0x17de9e0, C4<1>; +L_0x17e0a50 .delay (10000,10000,10000) L_0x17e0a50/d; +L_0x17e0b90/d .functor NAND 1, L_0x17e10c0, L_0x17e0990, L_0x17de9e0, C4<1>; +L_0x17e0b90 .delay (10000,10000,10000) L_0x17e0b90/d; +L_0x17e0c80/d .functor NAND 1, L_0x17e08d0, L_0x17e11f0, L_0x17dfe00, C4<1>; +L_0x17e0c80 .delay (10000,10000,10000) L_0x17e0c80/d; +L_0x17e0d70/d .functor NAND 1, L_0x17e10c0, L_0x17e11f0, L_0x17de9e0, C4<1>; +L_0x17e0d70 .delay (10000,10000,10000) L_0x17e0d70/d; +L_0x17e0ee0/d .functor NAND 1, L_0x17e0a50, L_0x17e0b90, L_0x17e0c80, L_0x17e0d70; +L_0x17e0ee0 .delay (10000,10000,10000) L_0x17e0ee0/d; +v0x17b7380_0 .net "S0", 0 0, L_0x17e10c0; 1 drivers +v0x17b7440_0 .net "S1", 0 0, L_0x17e11f0; 1 drivers +v0x17b74e0_0 .alias "in0", 0 0, v0x17baa80_0; +v0x17b7580_0 .alias "in1", 0 0, v0x17baa80_0; +v0x17b7660_0 .alias "in2", 0 0, v0x17bafb0_0; +v0x17b76e0_0 .alias "in3", 0 0, v0x17baa80_0; +v0x17b77b0_0 .net "nS0", 0 0, L_0x17e08d0; 1 drivers +v0x17b7830_0 .net "nS1", 0 0, L_0x17e0990; 1 drivers +v0x17b7900_0 .alias "out", 0 0, v0x17badb0_0; +v0x17b7980_0 .net "out0", 0 0, L_0x17e0a50; 1 drivers +v0x17b7a00_0 .net "out1", 0 0, L_0x17e0b90; 1 drivers +v0x17b7aa0_0 .net "out2", 0 0, L_0x17e0c80; 1 drivers +v0x17b7bb0_0 .net "out3", 0 0, L_0x17e0d70; 1 drivers +S_0x17b6880 .scope module, "OneMux" "FourInMux" 2 152, 2 29, S_0x178b140; + .timescale -9 -12; +L_0x17e1320/d .functor NOT 1, L_0x17e1af0, C4<0>, C4<0>, C4<0>; +L_0x17e1320 .delay (10000,10000,10000) L_0x17e1320/d; +L_0x17e13e0/d .functor NOT 1, L_0x17e1c20, C4<0>, C4<0>, C4<0>; +L_0x17e13e0 .delay (10000,10000,10000) L_0x17e13e0/d; +L_0x17e14a0/d .functor NAND 1, L_0x17e1320, L_0x17e13e0, L_0x17e06b0, C4<1>; +L_0x17e14a0 .delay (10000,10000,10000) L_0x17e14a0/d; +L_0x17e1540/d .functor NAND 1, L_0x17e1af0, L_0x17e13e0, L_0x17e06b0, C4<1>; +L_0x17e1540 .delay (10000,10000,10000) L_0x17e1540/d; +L_0x17e1630/d .functor NAND 1, L_0x17e1320, L_0x17e1c20, L_0x17dfe00, C4<1>; +L_0x17e1630 .delay (10000,10000,10000) L_0x17e1630/d; +L_0x17e1800/d .functor NAND 1, L_0x17e1af0, L_0x17e1c20, L_0x17dfe00, C4<1>; +L_0x17e1800 .delay (10000,10000,10000) L_0x17e1800/d; +L_0x17e1910/d .functor NAND 1, L_0x17e14a0, L_0x17e1540, L_0x17e1630, L_0x17e1800; +L_0x17e1910 .delay (10000,10000,10000) L_0x17e1910/d; +v0x17b6970_0 .net "S0", 0 0, L_0x17e1af0; 1 drivers +v0x17b6a30_0 .net "S1", 0 0, L_0x17e1c20; 1 drivers +v0x17b6ad0_0 .alias "in0", 0 0, v0x17bab90_0; +v0x17b6b70_0 .alias "in1", 0 0, v0x17bab90_0; +v0x17b6c20_0 .alias "in2", 0 0, v0x17bafb0_0; +v0x17b6ca0_0 .alias "in3", 0 0, v0x17bafb0_0; +v0x17b6d60_0 .net "nS0", 0 0, L_0x17e1320; 1 drivers +v0x17b6de0_0 .net "nS1", 0 0, L_0x17e13e0; 1 drivers +v0x17b6eb0_0 .alias "out", 0 0, v0x17bae30_0; +v0x17b6f60_0 .net "out0", 0 0, L_0x17e14a0; 1 drivers +v0x17b7040_0 .net "out1", 0 0, L_0x17e1540; 1 drivers +v0x17b70e0_0 .net "out2", 0 0, L_0x17e1630; 1 drivers +v0x17b71f0_0 .net "out3", 0 0, L_0x17e1800; 1 drivers +S_0x1767cd0 .scope module, "TwoMux" "TwoInMux" 2 153, 2 8, S_0x178b140; + .timescale -9 -12; +L_0x17e1d50/d .functor NOT 1, L_0x17e21a0, C4<0>, C4<0>, C4<0>; +L_0x17e1d50 .delay (10000,10000,10000) L_0x17e1d50/d; +L_0x17e1df0/d .functor AND 1, L_0x17e0ee0, L_0x17e1d50, C4<1>, C4<1>; +L_0x17e1df0 .delay (20000,20000,20000) L_0x17e1df0/d; +L_0x17e1f20/d .functor AND 1, L_0x17e1910, L_0x17e21a0, C4<1>, C4<1>; +L_0x17e1f20 .delay (20000,20000,20000) L_0x17e1f20/d; +L_0x17e2070/d .functor OR 1, L_0x17e1df0, L_0x17e1f20, C4<0>, C4<0>; +L_0x17e2070 .delay (20000,20000,20000) L_0x17e2070/d; +v0x16fba40_0 .net "S", 0 0, L_0x17e21a0; 1 drivers +v0x17b6470_0 .alias "in0", 0 0, v0x17badb0_0; +v0x17b6510_0 .alias "in1", 0 0, v0x17bae30_0; +v0x17b65b0_0 .net "nS", 0 0, L_0x17e1d50; 1 drivers +v0x17b6660_0 .net "out0", 0 0, L_0x17e1df0; 1 drivers +v0x17b6700_0 .net "out1", 0 0, L_0x17e1f20; 1 drivers +v0x17b67e0_0 .alias "outfinal", 0 0, v0x17baf30_0; +S_0x1782ed0 .scope module, "test32Adder" "test32Adder" 3 5; + .timescale -9 -12; +P_0x171d108 .param/l "size" 3 7, +C4<0100>; +v0x17dd890_0 .var "A", 3 0; +RS_0x7ff970b2c6f8/0/0 .resolv tri, L_0x17e33e0, L_0x17e4ad0, L_0x17e6010, L_0x17e7610; +RS_0x7ff970b2c6f8/0/4 .resolv tri, L_0x17f8a00, L_0x17f9e20, L_0x17fb220, L_0x17fc800; +RS_0x7ff970b2c6f8 .resolv tri, RS_0x7ff970b2c6f8/0/0, RS_0x7ff970b2c6f8/0/4, C4, C4; +v0x17dd910_0 .net8 "AddSubSLTSum", 3 0, RS_0x7ff970b2c6f8; 8 drivers +RS_0x7ff970b2b948/0/0 .resolv tri, L_0x17e9460, L_0x17e9e50, L_0x17ea8e0, L_0x17eb340; +RS_0x7ff970b2b948/0/4 .resolv tri, L_0x17fe630, L_0x17ff0a0, L_0x17ffb10, L_0x1800670; +RS_0x7ff970b2b948 .resolv tri, RS_0x7ff970b2b948/0/0, RS_0x7ff970b2b948/0/4, C4, C4; +v0x17dd990_0 .net8 "AndNandOut", 3 0, RS_0x7ff970b2b948; 8 drivers +v0x17dda10_0 .var "B", 3 0; +v0x17dda90_0 .var "Command", 2 0; +RS_0x7ff970b2cb48 .resolv tri, L_0x17f25a0, L_0x17f4f80, L_0x17f7790, L_0x1807460; +v0x17ddb10_0 .net8 "OneBitFinalOut", 3 0, RS_0x7ff970b2cb48; 4 drivers +RS_0x7ff970b2b258/0/0 .resolv tri, L_0x17ec700, L_0x17edc60, L_0x17eef60, L_0x17f0250; +RS_0x7ff970b2b258/0/4 .resolv tri, L_0x18019c0, L_0x1802cc0, L_0x1803fc0, L_0x18052b0; +RS_0x7ff970b2b258 .resolv tri, RS_0x7ff970b2b258/0/0, RS_0x7ff970b2b258/0/4, C4, C4; +v0x17ddb90_0 .net8 "OrNorXorOut", 3 0, RS_0x7ff970b2b258; 8 drivers +RS_0x7ff970b2c7b8 .resolv tri, L_0x17e8c40, L_0x17fdcd0, C4, C4; +v0x17ddc10_0 .net8 "SLTflag", 0 0, RS_0x7ff970b2c7b8; 2 drivers +v0x17ddc90_0 .var "carryin", 3 0; +RS_0x7ff970b2c9f8 .resolv tri, L_0x17e36c0, L_0x17fcb80, C4, C4; +v0x17ddd10_0 .net8 "carryout", 0 0, RS_0x7ff970b2c9f8; 2 drivers +RS_0x7ff970b2ca88 .resolv tri, L_0x17e7f10, L_0x17fcff0, C4, C4; +v0x17ddd90_0 .net8 "overflow", 0 0, RS_0x7ff970b2ca88; 2 drivers +RS_0x7ff970b2cab8/0/0 .resolv tri, L_0x17e3620, L_0x17e4d00, L_0x17e6270, L_0x17e6660; +RS_0x7ff970b2cab8/0/4 .resolv tri, L_0x17f8be0, L_0x17fa050, L_0x17fb480, L_0x17fb870; +RS_0x7ff970b2cab8 .resolv tri, RS_0x7ff970b2cab8/0/0, RS_0x7ff970b2cab8/0/4, C4, C4; +v0x17dde10_0 .net8 "subtract", 3 0, RS_0x7ff970b2cab8; 8 drivers +S_0x17d8120 .scope module, "trial" "AddSubSLT32" 3 25, 2 209, S_0x1782ed0; + .timescale -9 -12; +P_0x17d8218 .param/l "size" 2 232, +C4<0100>; +L_0x17e36c0/d .functor OR 1, L_0x17e7d60, C4<0>, C4<0>, C4<0>; +L_0x17e36c0 .delay (20000,20000,20000) L_0x17e36c0/d; +L_0x17e7f10/d .functor XOR 1, RS_0x7ff970b2c9f8, L_0x17e8040, C4<0>, C4<0>; +L_0x17e7f10 .delay (40000,40000,40000) L_0x17e7f10/d; +L_0x17e7c90/d .functor AND 1, L_0x17e8210, L_0x17e82b0, C4<1>, C4<1>; +L_0x17e7c90 .delay (20000,20000,20000) L_0x17e7c90/d; +L_0x17e80e0/d .functor NOT 1, RS_0x7ff970b2ca88, C4<0>, C4<0>, C4<0>; +L_0x17e80e0 .delay (10000,10000,10000) L_0x17e80e0/d; +L_0x17e84e0/d .functor NOT 1, L_0x17e8540, C4<0>, C4<0>, C4<0>; +L_0x17e84e0 .delay (10000,10000,10000) L_0x17e84e0/d; +L_0x17e3480/d .functor AND 1, L_0x17e80e0, L_0x17e8810, C4<1>, C4<1>; +L_0x17e3480 .delay (20000,20000,20000) L_0x17e3480/d; +L_0x17e83a0/d .functor AND 1, RS_0x7ff970b2ca88, L_0x17e84e0, C4<1>, C4<1>; +L_0x17e83a0 .delay (20000,20000,20000) L_0x17e83a0/d; +L_0x17e8a00/d .functor AND 1, L_0x17e3480, L_0x17e7c90, C4<1>, C4<1>; +L_0x17e8a00 .delay (20000,20000,20000) L_0x17e8a00/d; +L_0x17e8b40/d .functor AND 1, L_0x17e83a0, L_0x17e7c90, C4<1>, C4<1>; +L_0x17e8b40 .delay (20000,20000,20000) L_0x17e8b40/d; +L_0x17e8c40/d .functor OR 1, L_0x17e8a00, L_0x17e8b40, C4<0>, C4<0>; +L_0x17e8c40 .delay (20000,20000,20000) L_0x17e8c40/d; +v0x17dc7b0_0 .net "A", 3 0, v0x17dd890_0; 1 drivers +v0x17dc850_0 .alias "AddSubSLTSum", 3 0, v0x17dd910_0; +v0x17dc8d0_0 .net "B", 3 0, v0x17dda10_0; 1 drivers +RS_0x7ff970b2ec78 .resolv tri, L_0x17e3530, L_0x17e4bc0, L_0x17e6100, L_0x17e7700; +v0x17dc950_0 .net8 "CarryoutWire", 3 0, RS_0x7ff970b2ec78; 4 drivers +v0x17dc9d0_0 .net "Command", 2 0, v0x17dda90_0; 1 drivers +v0x17dca50_0 .net "Res0OF1", 0 0, L_0x17e83a0; 1 drivers +v0x17dcaf0_0 .net "Res1OF0", 0 0, L_0x17e3480; 1 drivers +v0x17dcb90_0 .alias "SLTflag", 0 0, v0x17ddc10_0; +v0x17dccb0_0 .net "SLTflag0", 0 0, L_0x17e8a00; 1 drivers +v0x17dcd50_0 .net "SLTflag1", 0 0, L_0x17e8b40; 1 drivers +v0x17dcdf0_0 .net "SLTon", 0 0, L_0x17e7c90; 1 drivers +v0x17dce90_0 .net *"_s40", 0 0, L_0x17e7d60; 1 drivers +v0x17dcf30_0 .net/s *"_s41", 0 0, C4<0>; 1 drivers +v0x17dcfd0_0 .net *"_s44", 0 0, L_0x17e8040; 1 drivers +v0x17dd0f0_0 .net *"_s46", 0 0, L_0x17e8210; 1 drivers +v0x17dd190_0 .net *"_s48", 0 0, L_0x17e82b0; 1 drivers +v0x17dd050_0 .net *"_s50", 0 0, L_0x17e8540; 1 drivers +v0x17dd2e0_0 .net *"_s52", 0 0, L_0x17e8810; 1 drivers +v0x17dd400_0 .net "carryin", 3 0, v0x17ddc90_0; 1 drivers +v0x17dd480_0 .alias "carryout", 0 0, v0x17ddd10_0; +v0x17dd360_0 .net "nAddSubSLTSum", 0 0, L_0x17e84e0; 1 drivers +v0x17dd5b0_0 .net "nOF", 0 0, L_0x17e80e0; 1 drivers +v0x17dd500_0 .alias "overflow", 0 0, v0x17ddd90_0; +v0x17dd740_0 .alias "subtract", 3 0, v0x17dde10_0; +L_0x17e33e0 .part/pv L_0x17e2f00, 1, 1, 4; +L_0x17e3530 .part/pv L_0x17e3280, 1, 1, 4; +L_0x17e3620 .part/pv L_0x17d1170, 1, 1, 4; +L_0x17e3750 .part v0x17dd890_0, 1, 1; +L_0x17e3900 .part v0x17dda10_0, 1, 1; +L_0x17e3ab0 .part RS_0x7ff970b2ec78, 0, 1; +L_0x17e4ad0 .part/pv L_0x17e4600, 2, 1, 4; +L_0x17e4bc0 .part/pv L_0x17e4970, 2, 1, 4; +L_0x17e4d00 .part/pv L_0x17e4330, 2, 1, 4; +L_0x17e4df0 .part v0x17dd890_0, 2, 1; +L_0x17e4ef0 .part v0x17dda10_0, 2, 1; +L_0x17e5020 .part RS_0x7ff970b2ec78, 1, 1; +L_0x17e6010 .part/pv L_0x17e5b60, 3, 1, 4; +L_0x17e6100 .part/pv L_0x17e5eb0, 3, 1, 4; +L_0x17e6270 .part/pv L_0x17e5890, 3, 1, 4; +L_0x17e6360 .part v0x17dd890_0, 3, 1; +L_0x17e6490 .part v0x17dda10_0, 3, 1; +L_0x17e65c0 .part RS_0x7ff970b2ec78, 2, 1; +L_0x17e7610 .part/pv L_0x17e7160, 0, 1, 4; +L_0x17e7700 .part/pv L_0x17e74b0, 0, 1, 4; +L_0x17e6660 .part/pv L_0x17e6e90, 0, 1, 4; +L_0x17e78f0 .part v0x17dd890_0, 0, 1; +L_0x17e77f0 .part v0x17dda10_0, 0, 1; +L_0x17e7ae0 .part RS_0x7ff970b2cab8, 0, 1; +L_0x17e7d60 .part RS_0x7ff970b2ec78, 3, 1; +L_0x17e8040 .part RS_0x7ff970b2ec78, 2, 1; +L_0x17e8210 .part v0x17dda90_0, 1, 1; +L_0x17e82b0 .part RS_0x7ff970b2cab8, 0, 1; +L_0x17e8540 .part RS_0x7ff970b2c6f8, 3, 1; +L_0x17e8810 .part RS_0x7ff970b2c6f8, 3, 1; +S_0x17db7a0 .scope module, "attempt2" "MiddleAddSubSLT" 2 229, 2 95, S_0x17d8120; + .timescale -9 -12; +L_0x17e6400/d .functor NOT 1, L_0x17e77f0, C4<0>, C4<0>, C4<0>; +L_0x17e6400 .delay (10000,10000,10000) L_0x17e6400/d; +L_0x17e6d30/d .functor NOT 1, L_0x17e6df0, C4<0>, C4<0>, C4<0>; +L_0x17e6d30 .delay (10000,10000,10000) L_0x17e6d30/d; +L_0x17e6e90/d .functor AND 1, L_0x17e6fd0, L_0x17e6d30, C4<1>, C4<1>; +L_0x17e6e90 .delay (20000,20000,20000) L_0x17e6e90/d; +L_0x17e7070/d .functor XOR 1, L_0x17e78f0, L_0x17e6ac0, C4<0>, C4<0>; +L_0x17e7070 .delay (40000,40000,40000) L_0x17e7070/d; +L_0x17e7160/d .functor XOR 1, L_0x17e7070, L_0x17e7ae0, C4<0>, C4<0>; +L_0x17e7160 .delay (40000,40000,40000) L_0x17e7160/d; +L_0x17e7250/d .functor AND 1, L_0x17e78f0, L_0x17e6ac0, C4<1>, C4<1>; +L_0x17e7250 .delay (20000,20000,20000) L_0x17e7250/d; +L_0x17e73c0/d .functor AND 1, L_0x17e7070, L_0x17e7ae0, C4<1>, C4<1>; +L_0x17e73c0 .delay (20000,20000,20000) L_0x17e73c0/d; +L_0x17e74b0/d .functor OR 1, L_0x17e7250, L_0x17e73c0, C4<0>, C4<0>; +L_0x17e74b0 .delay (20000,20000,20000) L_0x17e74b0/d; +v0x17dbe10_0 .net "A", 0 0, L_0x17e78f0; 1 drivers +v0x17dbed0_0 .net "AandB", 0 0, L_0x17e7250; 1 drivers +v0x17dbf70_0 .net "AddSubSLTSum", 0 0, L_0x17e7160; 1 drivers +v0x17dc010_0 .net "AxorB", 0 0, L_0x17e7070; 1 drivers +v0x17dc090_0 .net "B", 0 0, L_0x17e77f0; 1 drivers +v0x17dc140_0 .net "BornB", 0 0, L_0x17e6ac0; 1 drivers +v0x17dc200_0 .net "CINandAxorB", 0 0, L_0x17e73c0; 1 drivers +v0x17dc280_0 .alias "Command", 2 0, v0x17dc9d0_0; +v0x17dc300_0 .net *"_s3", 0 0, L_0x17e6df0; 1 drivers +v0x17dc380_0 .net *"_s5", 0 0, L_0x17e6fd0; 1 drivers +v0x17dc420_0 .net "carryin", 0 0, L_0x17e7ae0; 1 drivers +v0x17dc4c0_0 .net "carryout", 0 0, L_0x17e74b0; 1 drivers +v0x17dc560_0 .net "nB", 0 0, L_0x17e6400; 1 drivers +v0x17dc610_0 .net "nCmd2", 0 0, L_0x17e6d30; 1 drivers +v0x17dc710_0 .net "subtract", 0 0, L_0x17e6e90; 1 drivers +L_0x17e6c90 .part v0x17dda90_0, 0, 1; +L_0x17e6df0 .part v0x17dda90_0, 2, 1; +L_0x17e6fd0 .part v0x17dda90_0, 0, 1; +S_0x17db890 .scope module, "mux0" "TwoInMux" 2 111, 2 8, S_0x17db7a0; + .timescale -9 -12; +L_0x17e67e0/d .functor NOT 1, L_0x17e6c90, C4<0>, C4<0>, C4<0>; +L_0x17e67e0 .delay (10000,10000,10000) L_0x17e67e0/d; +L_0x17e68a0/d .functor AND 1, L_0x17e77f0, L_0x17e67e0, C4<1>, C4<1>; +L_0x17e68a0 .delay (20000,20000,20000) L_0x17e68a0/d; +L_0x17e69b0/d .functor AND 1, L_0x17e6400, L_0x17e6c90, C4<1>, C4<1>; +L_0x17e69b0 .delay (20000,20000,20000) L_0x17e69b0/d; +L_0x17e6ac0/d .functor OR 1, L_0x17e68a0, L_0x17e69b0, C4<0>, C4<0>; +L_0x17e6ac0 .delay (20000,20000,20000) L_0x17e6ac0/d; +v0x17db980_0 .net "S", 0 0, L_0x17e6c90; 1 drivers +v0x17dba40_0 .alias "in0", 0 0, v0x17dc090_0; +v0x17dbae0_0 .alias "in1", 0 0, v0x17dc560_0; +v0x17dbb80_0 .net "nS", 0 0, L_0x17e67e0; 1 drivers +v0x17dbc30_0 .net "out0", 0 0, L_0x17e68a0; 1 drivers +v0x17dbcd0_0 .net "out1", 0 0, L_0x17e69b0; 1 drivers +v0x17dbd70_0 .alias "outfinal", 0 0, v0x17dc140_0; +S_0x17da600 .scope generate, "addbits[1]" "addbits[1]" 2 234, 2 234, S_0x17d8120; + .timescale -9 -12; +P_0x17da018 .param/l "i" 2 234, +C4<01>; +S_0x17da770 .scope module, "attempt" "MiddleAddSubSLT" 2 236, 2 95, S_0x17da600; + .timescale -9 -12; +L_0x17e2240/d .functor NOT 1, L_0x17e3900, C4<0>, C4<0>, C4<0>; +L_0x17e2240 .delay (10000,10000,10000) L_0x17e2240/d; +L_0x17cae70/d .functor NOT 1, L_0x17d10d0, C4<0>, C4<0>, C4<0>; +L_0x17cae70 .delay (10000,10000,10000) L_0x17cae70/d; +L_0x17d1170/d .functor AND 1, L_0x17e2d70, L_0x17cae70, C4<1>, C4<1>; +L_0x17d1170 .delay (20000,20000,20000) L_0x17d1170/d; +L_0x17e2e10/d .functor XOR 1, L_0x17e3750, L_0x17e26a0, C4<0>, C4<0>; +L_0x17e2e10 .delay (40000,40000,40000) L_0x17e2e10/d; +L_0x17e2f00/d .functor XOR 1, L_0x17e2e10, L_0x17e3ab0, C4<0>, C4<0>; +L_0x17e2f00 .delay (40000,40000,40000) L_0x17e2f00/d; +L_0x17e2ff0/d .functor AND 1, L_0x17e3750, L_0x17e26a0, C4<1>, C4<1>; +L_0x17e2ff0 .delay (20000,20000,20000) L_0x17e2ff0/d; +L_0x17e3190/d .functor AND 1, L_0x17e2e10, L_0x17e3ab0, C4<1>, C4<1>; +L_0x17e3190 .delay (20000,20000,20000) L_0x17e3190/d; +L_0x17e3280/d .functor OR 1, L_0x17e2ff0, L_0x17e3190, C4<0>, C4<0>; +L_0x17e3280 .delay (20000,20000,20000) L_0x17e3280/d; +v0x17dae00_0 .net "A", 0 0, L_0x17e3750; 1 drivers +v0x17daec0_0 .net "AandB", 0 0, L_0x17e2ff0; 1 drivers +v0x17daf60_0 .net "AddSubSLTSum", 0 0, L_0x17e2f00; 1 drivers +v0x17db000_0 .net "AxorB", 0 0, L_0x17e2e10; 1 drivers +v0x17db080_0 .net "B", 0 0, L_0x17e3900; 1 drivers +v0x17db130_0 .net "BornB", 0 0, L_0x17e26a0; 1 drivers +v0x17db1f0_0 .net "CINandAxorB", 0 0, L_0x17e3190; 1 drivers +v0x17db270_0 .alias "Command", 2 0, v0x17dc9d0_0; +v0x17db2f0_0 .net *"_s3", 0 0, L_0x17d10d0; 1 drivers +v0x17db370_0 .net *"_s5", 0 0, L_0x17e2d70; 1 drivers +v0x17db410_0 .net "carryin", 0 0, L_0x17e3ab0; 1 drivers +v0x17db4b0_0 .net "carryout", 0 0, L_0x17e3280; 1 drivers +v0x17db550_0 .net "nB", 0 0, L_0x17e2240; 1 drivers +v0x17db600_0 .net "nCmd2", 0 0, L_0x17cae70; 1 drivers +v0x17db700_0 .net "subtract", 0 0, L_0x17d1170; 1 drivers +L_0x17e2870 .part v0x17dda90_0, 0, 1; +L_0x17d10d0 .part v0x17dda90_0, 2, 1; +L_0x17e2d70 .part v0x17dda90_0, 0, 1; +S_0x17da860 .scope module, "mux0" "TwoInMux" 2 111, 2 8, S_0x17da770; + .timescale -9 -12; +L_0x17e23c0/d .functor NOT 1, L_0x17e2870, C4<0>, C4<0>, C4<0>; +L_0x17e23c0 .delay (10000,10000,10000) L_0x17e23c0/d; +L_0x17e2480/d .functor AND 1, L_0x17e3900, L_0x17e23c0, C4<1>, C4<1>; +L_0x17e2480 .delay (20000,20000,20000) L_0x17e2480/d; +L_0x17e2590/d .functor AND 1, L_0x17e2240, L_0x17e2870, C4<1>, C4<1>; +L_0x17e2590 .delay (20000,20000,20000) L_0x17e2590/d; +L_0x17e26a0/d .functor OR 1, L_0x17e2480, L_0x17e2590, C4<0>, C4<0>; +L_0x17e26a0 .delay (20000,20000,20000) L_0x17e26a0/d; +v0x17da950_0 .net "S", 0 0, L_0x17e2870; 1 drivers +v0x17da9f0_0 .alias "in0", 0 0, v0x17db080_0; +v0x17daa90_0 .alias "in1", 0 0, v0x17db550_0; +v0x17dab30_0 .net "nS", 0 0, L_0x17e23c0; 1 drivers +v0x17dabe0_0 .net "out0", 0 0, L_0x17e2480; 1 drivers +v0x17dac80_0 .net "out1", 0 0, L_0x17e2590; 1 drivers +v0x17dad60_0 .alias "outfinal", 0 0, v0x17db130_0; +S_0x17d9460 .scope generate, "addbits[2]" "addbits[2]" 2 234, 2 234, S_0x17d8120; + .timescale -9 -12; +P_0x17d8e18 .param/l "i" 2 234, +C4<010>; +S_0x17d95d0 .scope module, "attempt" "MiddleAddSubSLT" 2 236, 2 95, S_0x17d9460; + .timescale -9 -12; +L_0x17d4ed0/d .functor NOT 1, L_0x17e4ef0, C4<0>, C4<0>, C4<0>; +L_0x17d4ed0 .delay (10000,10000,10000) L_0x17d4ed0/d; +L_0x17e41d0/d .functor NOT 1, L_0x17e4290, C4<0>, C4<0>, C4<0>; +L_0x17e41d0 .delay (10000,10000,10000) L_0x17e41d0/d; +L_0x17e4330/d .functor AND 1, L_0x17e4470, L_0x17e41d0, C4<1>, C4<1>; +L_0x17e4330 .delay (20000,20000,20000) L_0x17e4330/d; +L_0x17e4510/d .functor XOR 1, L_0x17e4df0, L_0x17e3f60, C4<0>, C4<0>; +L_0x17e4510 .delay (40000,40000,40000) L_0x17e4510/d; +L_0x17e4600/d .functor XOR 1, L_0x17e4510, L_0x17e5020, C4<0>, C4<0>; +L_0x17e4600 .delay (40000,40000,40000) L_0x17e4600/d; +L_0x17e46f0/d .functor AND 1, L_0x17e4df0, L_0x17e3f60, C4<1>, C4<1>; +L_0x17e46f0 .delay (20000,20000,20000) L_0x17e46f0/d; +L_0x17e4860/d .functor AND 1, L_0x17e4510, L_0x17e5020, C4<1>, C4<1>; +L_0x17e4860 .delay (20000,20000,20000) L_0x17e4860/d; +L_0x17e4970/d .functor OR 1, L_0x17e46f0, L_0x17e4860, C4<0>, C4<0>; +L_0x17e4970 .delay (20000,20000,20000) L_0x17e4970/d; +v0x17d9c60_0 .net "A", 0 0, L_0x17e4df0; 1 drivers +v0x17d9d20_0 .net "AandB", 0 0, L_0x17e46f0; 1 drivers +v0x17d9dc0_0 .net "AddSubSLTSum", 0 0, L_0x17e4600; 1 drivers +v0x17d9e60_0 .net "AxorB", 0 0, L_0x17e4510; 1 drivers +v0x17d9ee0_0 .net "B", 0 0, L_0x17e4ef0; 1 drivers +v0x17d9f90_0 .net "BornB", 0 0, L_0x17e3f60; 1 drivers +v0x17da050_0 .net "CINandAxorB", 0 0, L_0x17e4860; 1 drivers +v0x17da0d0_0 .alias "Command", 2 0, v0x17dc9d0_0; +v0x17da150_0 .net *"_s3", 0 0, L_0x17e4290; 1 drivers +v0x17da1d0_0 .net *"_s5", 0 0, L_0x17e4470; 1 drivers +v0x17da270_0 .net "carryin", 0 0, L_0x17e5020; 1 drivers +v0x17da310_0 .net "carryout", 0 0, L_0x17e4970; 1 drivers +v0x17da3b0_0 .net "nB", 0 0, L_0x17d4ed0; 1 drivers +v0x17da460_0 .net "nCmd2", 0 0, L_0x17e41d0; 1 drivers +v0x17da560_0 .net "subtract", 0 0, L_0x17e4330; 1 drivers +L_0x17e4130 .part v0x17dda90_0, 0, 1; +L_0x17e4290 .part v0x17dda90_0, 2, 1; +L_0x17e4470 .part v0x17dda90_0, 0, 1; +S_0x17d96c0 .scope module, "mux0" "TwoInMux" 2 111, 2 8, S_0x17d95d0; + .timescale -9 -12; +L_0x17e3c80/d .functor NOT 1, L_0x17e4130, C4<0>, C4<0>, C4<0>; +L_0x17e3c80 .delay (10000,10000,10000) L_0x17e3c80/d; +L_0x17e3d40/d .functor AND 1, L_0x17e4ef0, L_0x17e3c80, C4<1>, C4<1>; +L_0x17e3d40 .delay (20000,20000,20000) L_0x17e3d40/d; +L_0x17e3e50/d .functor AND 1, L_0x17d4ed0, L_0x17e4130, C4<1>, C4<1>; +L_0x17e3e50 .delay (20000,20000,20000) L_0x17e3e50/d; +L_0x17e3f60/d .functor OR 1, L_0x17e3d40, L_0x17e3e50, C4<0>, C4<0>; +L_0x17e3f60 .delay (20000,20000,20000) L_0x17e3f60/d; +v0x17d97b0_0 .net "S", 0 0, L_0x17e4130; 1 drivers +v0x17d9850_0 .alias "in0", 0 0, v0x17d9ee0_0; +v0x17d98f0_0 .alias "in1", 0 0, v0x17da3b0_0; +v0x17d9990_0 .net "nS", 0 0, L_0x17e3c80; 1 drivers +v0x17d9a40_0 .net "out0", 0 0, L_0x17e3d40; 1 drivers +v0x17d9ae0_0 .net "out1", 0 0, L_0x17e3e50; 1 drivers +v0x17d9bc0_0 .alias "outfinal", 0 0, v0x17d9f90_0; +S_0x17d8290 .scope generate, "addbits[3]" "addbits[3]" 2 234, 2 234, S_0x17d8120; + .timescale -9 -12; +P_0x17d8388 .param/l "i" 2 234, +C4<011>; +S_0x17d8400 .scope module, "attempt" "MiddleAddSubSLT" 2 236, 2 95, S_0x17d8290; + .timescale -9 -12; +L_0x17e4e90/d .functor NOT 1, L_0x17e6490, C4<0>, C4<0>, C4<0>; +L_0x17e4e90 .delay (10000,10000,10000) L_0x17e4e90/d; +L_0x17e5730/d .functor NOT 1, L_0x17e57f0, C4<0>, C4<0>, C4<0>; +L_0x17e5730 .delay (10000,10000,10000) L_0x17e5730/d; +L_0x17e5890/d .functor AND 1, L_0x17e59d0, L_0x17e5730, C4<1>, C4<1>; +L_0x17e5890 .delay (20000,20000,20000) L_0x17e5890/d; +L_0x17e5a70/d .functor XOR 1, L_0x17e6360, L_0x17e54c0, C4<0>, C4<0>; +L_0x17e5a70 .delay (40000,40000,40000) L_0x17e5a70/d; +L_0x17e5b60/d .functor XOR 1, L_0x17e5a70, L_0x17e65c0, C4<0>, C4<0>; +L_0x17e5b60 .delay (40000,40000,40000) L_0x17e5b60/d; +L_0x17e5c50/d .functor AND 1, L_0x17e6360, L_0x17e54c0, C4<1>, C4<1>; +L_0x17e5c50 .delay (20000,20000,20000) L_0x17e5c50/d; +L_0x17e5dc0/d .functor AND 1, L_0x17e5a70, L_0x17e65c0, C4<1>, C4<1>; +L_0x17e5dc0 .delay (20000,20000,20000) L_0x17e5dc0/d; +L_0x17e5eb0/d .functor OR 1, L_0x17e5c50, L_0x17e5dc0, C4<0>, C4<0>; +L_0x17e5eb0 .delay (20000,20000,20000) L_0x17e5eb0/d; +v0x17d8a60_0 .net "A", 0 0, L_0x17e6360; 1 drivers +v0x17d8b20_0 .net "AandB", 0 0, L_0x17e5c50; 1 drivers +v0x17d8bc0_0 .net "AddSubSLTSum", 0 0, L_0x17e5b60; 1 drivers +v0x17d8c60_0 .net "AxorB", 0 0, L_0x17e5a70; 1 drivers +v0x17d8ce0_0 .net "B", 0 0, L_0x17e6490; 1 drivers +v0x17d8d90_0 .net "BornB", 0 0, L_0x17e54c0; 1 drivers +v0x17d8e50_0 .net "CINandAxorB", 0 0, L_0x17e5dc0; 1 drivers +v0x17d8ed0_0 .alias "Command", 2 0, v0x17dc9d0_0; +v0x17d8f50_0 .net *"_s3", 0 0, L_0x17e57f0; 1 drivers +v0x17d8fd0_0 .net *"_s5", 0 0, L_0x17e59d0; 1 drivers +v0x17d90d0_0 .net "carryin", 0 0, L_0x17e65c0; 1 drivers +v0x17d9170_0 .net "carryout", 0 0, L_0x17e5eb0; 1 drivers +v0x17d9210_0 .net "nB", 0 0, L_0x17e4e90; 1 drivers +v0x17d92c0_0 .net "nCmd2", 0 0, L_0x17e5730; 1 drivers +v0x17d93c0_0 .net "subtract", 0 0, L_0x17e5890; 1 drivers +L_0x17e5690 .part v0x17dda90_0, 0, 1; +L_0x17e57f0 .part v0x17dda90_0, 2, 1; +L_0x17e59d0 .part v0x17dda90_0, 0, 1; +S_0x17d84f0 .scope module, "mux0" "TwoInMux" 2 111, 2 8, S_0x17d8400; + .timescale -9 -12; +L_0x17e5220/d .functor NOT 1, L_0x17e5690, C4<0>, C4<0>, C4<0>; +L_0x17e5220 .delay (10000,10000,10000) L_0x17e5220/d; +L_0x17e52a0/d .functor AND 1, L_0x17e6490, L_0x17e5220, C4<1>, C4<1>; +L_0x17e52a0 .delay (20000,20000,20000) L_0x17e52a0/d; +L_0x17e53b0/d .functor AND 1, L_0x17e4e90, L_0x17e5690, C4<1>, C4<1>; +L_0x17e53b0 .delay (20000,20000,20000) L_0x17e53b0/d; +L_0x17e54c0/d .functor OR 1, L_0x17e52a0, L_0x17e53b0, C4<0>, C4<0>; +L_0x17e54c0 .delay (20000,20000,20000) L_0x17e54c0/d; +v0x17d85e0_0 .net "S", 0 0, L_0x17e5690; 1 drivers +v0x17d8680_0 .alias "in0", 0 0, v0x17d8ce0_0; +v0x17d8720_0 .alias "in1", 0 0, v0x17d9210_0; +v0x17d87c0_0 .net "nS", 0 0, L_0x17e5220; 1 drivers +v0x17d8840_0 .net "out0", 0 0, L_0x17e52a0; 1 drivers +v0x17d88e0_0 .net "out1", 0 0, L_0x17e53b0; 1 drivers +v0x17d89c0_0 .alias "outfinal", 0 0, v0x17d8d90_0; +S_0x17d5060 .scope module, "trial1" "AndNand32" 3 27, 2 157, S_0x1782ed0; + .timescale -9 -12; +P_0x17d4a58 .param/l "size" 2 165, +C4<0100>; +v0x17d7f20_0 .alias "A", 3 0, v0x17dc7b0_0; +v0x17d7fa0_0 .alias "AndNandOut", 3 0, v0x17dd990_0; +v0x17d8020_0 .alias "B", 3 0, v0x17dc8d0_0; +v0x17d80a0_0 .alias "Command", 2 0, v0x17dc9d0_0; +L_0x17e9460 .part/pv L_0x17e9230, 1, 1, 4; +L_0x17e9590 .part v0x17dd890_0, 1, 1; +L_0x17e9630 .part v0x17dda10_0, 1, 1; +L_0x17e9e50 .part/pv L_0x17e9be0, 2, 1, 4; +L_0x17e9ef0 .part v0x17dd890_0, 2, 1; +L_0x17e9f90 .part v0x17dda10_0, 2, 1; +L_0x17ea8e0 .part/pv L_0x17ea670, 3, 1, 4; +L_0x17ea980 .part v0x17dd890_0, 3, 1; +L_0x17eaa70 .part v0x17dda10_0, 3, 1; +L_0x17eb340 .part/pv L_0x17eb0d0, 0, 1, 4; +L_0x17eb440 .part v0x17dd890_0, 0, 1; +L_0x17eb4e0 .part v0x17dda10_0, 0, 1; +S_0x17d74f0 .scope module, "attempt2" "AndNand" 2 170, 2 53, S_0x17d5060; + .timescale -9 -12; +L_0x17eab60/d .functor NAND 1, L_0x17eb440, L_0x17eb4e0, C4<1>, C4<1>; +L_0x17eab60 .delay (10000,10000,10000) L_0x17eab60/d; +L_0x17eac80/d .functor NOT 1, L_0x17eab60, C4<0>, C4<0>, C4<0>; +L_0x17eac80 .delay (10000,10000,10000) L_0x17eac80/d; +v0x17d7b10_0 .net "A", 0 0, L_0x17eb440; 1 drivers +v0x17d7bd0_0 .net "AandB", 0 0, L_0x17eac80; 1 drivers +v0x17d7c50_0 .net "AnandB", 0 0, L_0x17eab60; 1 drivers +v0x17d7d00_0 .net "AndNandOut", 0 0, L_0x17eb0d0; 1 drivers +v0x17d7de0_0 .net "B", 0 0, L_0x17eb4e0; 1 drivers +v0x17d7e60_0 .alias "Command", 2 0, v0x17dc9d0_0; +L_0x17eb2a0 .part v0x17dda90_0, 0, 1; +S_0x17d75e0 .scope module, "potato" "TwoInMux" 2 66, 2 8, S_0x17d74f0; + .timescale -9 -12; +L_0x17eadb0/d .functor NOT 1, L_0x17eb2a0, C4<0>, C4<0>, C4<0>; +L_0x17eadb0 .delay (10000,10000,10000) L_0x17eadb0/d; +L_0x17eae70/d .functor AND 1, L_0x17eac80, L_0x17eadb0, C4<1>, C4<1>; +L_0x17eae70 .delay (20000,20000,20000) L_0x17eae70/d; +L_0x17eaf80/d .functor AND 1, L_0x17eab60, L_0x17eb2a0, C4<1>, C4<1>; +L_0x17eaf80 .delay (20000,20000,20000) L_0x17eaf80/d; +L_0x17eb0d0/d .functor OR 1, L_0x17eae70, L_0x17eaf80, C4<0>, C4<0>; +L_0x17eb0d0 .delay (20000,20000,20000) L_0x17eb0d0/d; +v0x17d76d0_0 .net "S", 0 0, L_0x17eb2a0; 1 drivers +v0x17d7750_0 .alias "in0", 0 0, v0x17d7bd0_0; +v0x17d77d0_0 .alias "in1", 0 0, v0x17d7c50_0; +v0x17d7870_0 .net "nS", 0 0, L_0x17eadb0; 1 drivers +v0x17d78f0_0 .net "out0", 0 0, L_0x17eae70; 1 drivers +v0x17d7990_0 .net "out1", 0 0, L_0x17eaf80; 1 drivers +v0x17d7a70_0 .alias "outfinal", 0 0, v0x17d7d00_0; +S_0x17d6930 .scope generate, "andbits[1]" "andbits[1]" 2 173, 2 173, S_0x17d5060; + .timescale -9 -12; +P_0x17d6a28 .param/l "i" 2 173, +C4<01>; +S_0x17d6aa0 .scope module, "attempt" "AndNand" 2 175, 2 53, S_0x17d6930; + .timescale -9 -12; +L_0x17e8e40/d .functor NAND 1, L_0x17e9590, L_0x17e9630, C4<1>, C4<1>; +L_0x17e8e40 .delay (10000,10000,10000) L_0x17e8e40/d; +L_0x17e8f00/d .functor NOT 1, L_0x17e8e40, C4<0>, C4<0>, C4<0>; +L_0x17e8f00 .delay (10000,10000,10000) L_0x17e8f00/d; +v0x17d70e0_0 .net "A", 0 0, L_0x17e9590; 1 drivers +v0x17d71a0_0 .net "AandB", 0 0, L_0x17e8f00; 1 drivers +v0x17d7220_0 .net "AnandB", 0 0, L_0x17e8e40; 1 drivers +v0x17d72d0_0 .net "AndNandOut", 0 0, L_0x17e9230; 1 drivers +v0x17d73b0_0 .net "B", 0 0, L_0x17e9630; 1 drivers +v0x17d7430_0 .alias "Command", 2 0, v0x17dc9d0_0; +L_0x17e93c0 .part v0x17dda90_0, 0, 1; +S_0x17d6b90 .scope module, "potato" "TwoInMux" 2 66, 2 8, S_0x17d6aa0; + .timescale -9 -12; +L_0x17e61f0/d .functor NOT 1, L_0x17e93c0, C4<0>, C4<0>, C4<0>; +L_0x17e61f0 .delay (10000,10000,10000) L_0x17e61f0/d; +L_0x17e9010/d .functor AND 1, L_0x17e8f00, L_0x17e61f0, C4<1>, C4<1>; +L_0x17e9010 .delay (20000,20000,20000) L_0x17e9010/d; +L_0x17e9100/d .functor AND 1, L_0x17e8e40, L_0x17e93c0, C4<1>, C4<1>; +L_0x17e9100 .delay (20000,20000,20000) L_0x17e9100/d; +L_0x17e9230/d .functor OR 1, L_0x17e9010, L_0x17e9100, C4<0>, C4<0>; +L_0x17e9230 .delay (20000,20000,20000) L_0x17e9230/d; +v0x17d6c80_0 .net "S", 0 0, L_0x17e93c0; 1 drivers +v0x17d6d00_0 .alias "in0", 0 0, v0x17d71a0_0; +v0x17d6da0_0 .alias "in1", 0 0, v0x17d7220_0; +v0x17d6e40_0 .net "nS", 0 0, L_0x17e61f0; 1 drivers +v0x17d6ec0_0 .net "out0", 0 0, L_0x17e9010; 1 drivers +v0x17d6f60_0 .net "out1", 0 0, L_0x17e9100; 1 drivers +v0x17d7040_0 .alias "outfinal", 0 0, v0x17d72d0_0; +S_0x17d5d70 .scope generate, "andbits[2]" "andbits[2]" 2 173, 2 173, S_0x17d5060; + .timescale -9 -12; +P_0x17d5e68 .param/l "i" 2 173, +C4<010>; +S_0x17d5ee0 .scope module, "attempt" "AndNand" 2 175, 2 53, S_0x17d5d70; + .timescale -9 -12; +L_0x17e96d0/d .functor NAND 1, L_0x17e9ef0, L_0x17e9f90, C4<1>, C4<1>; +L_0x17e96d0 .delay (10000,10000,10000) L_0x17e96d0/d; +L_0x17e9810/d .functor NOT 1, L_0x17e96d0, C4<0>, C4<0>, C4<0>; +L_0x17e9810 .delay (10000,10000,10000) L_0x17e9810/d; +v0x17d6520_0 .net "A", 0 0, L_0x17e9ef0; 1 drivers +v0x17d65e0_0 .net "AandB", 0 0, L_0x17e9810; 1 drivers +v0x17d6660_0 .net "AnandB", 0 0, L_0x17e96d0; 1 drivers +v0x17d6710_0 .net "AndNandOut", 0 0, L_0x17e9be0; 1 drivers +v0x17d67f0_0 .net "B", 0 0, L_0x17e9f90; 1 drivers +v0x17d6870_0 .alias "Command", 2 0, v0x17dc9d0_0; +L_0x17e9db0 .part v0x17dda90_0, 0, 1; +S_0x17d5fd0 .scope module, "potato" "TwoInMux" 2 66, 2 8, S_0x17d5ee0; + .timescale -9 -12; +L_0x17e9900/d .functor NOT 1, L_0x17e9db0, C4<0>, C4<0>, C4<0>; +L_0x17e9900 .delay (10000,10000,10000) L_0x17e9900/d; +L_0x17e99a0/d .functor AND 1, L_0x17e9810, L_0x17e9900, C4<1>, C4<1>; +L_0x17e99a0 .delay (20000,20000,20000) L_0x17e99a0/d; +L_0x17e9a90/d .functor AND 1, L_0x17e96d0, L_0x17e9db0, C4<1>, C4<1>; +L_0x17e9a90 .delay (20000,20000,20000) L_0x17e9a90/d; +L_0x17e9be0/d .functor OR 1, L_0x17e99a0, L_0x17e9a90, C4<0>, C4<0>; +L_0x17e9be0 .delay (20000,20000,20000) L_0x17e9be0/d; +v0x17d60c0_0 .net "S", 0 0, L_0x17e9db0; 1 drivers +v0x17d6140_0 .alias "in0", 0 0, v0x17d65e0_0; +v0x17d61e0_0 .alias "in1", 0 0, v0x17d6660_0; +v0x17d6280_0 .net "nS", 0 0, L_0x17e9900; 1 drivers +v0x17d6300_0 .net "out0", 0 0, L_0x17e99a0; 1 drivers +v0x17d63a0_0 .net "out1", 0 0, L_0x17e9a90; 1 drivers +v0x17d6480_0 .alias "outfinal", 0 0, v0x17d6710_0; +S_0x17d5190 .scope generate, "andbits[3]" "andbits[3]" 2 173, 2 173, S_0x17d5060; + .timescale -9 -12; +P_0x17d5288 .param/l "i" 2 173, +C4<011>; +S_0x17d5300 .scope module, "attempt" "AndNand" 2 175, 2 53, S_0x17d5190; + .timescale -9 -12; +L_0x17ea0c0/d .functor NAND 1, L_0x17ea980, L_0x17eaa70, C4<1>, C4<1>; +L_0x17ea0c0 .delay (10000,10000,10000) L_0x17ea0c0/d; +L_0x17ea220/d .functor NOT 1, L_0x17ea0c0, C4<0>, C4<0>, C4<0>; +L_0x17ea220 .delay (10000,10000,10000) L_0x17ea220/d; +v0x17d5960_0 .net "A", 0 0, L_0x17ea980; 1 drivers +v0x17d5a20_0 .net "AandB", 0 0, L_0x17ea220; 1 drivers +v0x17d5aa0_0 .net "AnandB", 0 0, L_0x17ea0c0; 1 drivers +v0x17d5b50_0 .net "AndNandOut", 0 0, L_0x17ea670; 1 drivers +v0x17d5c30_0 .net "B", 0 0, L_0x17eaa70; 1 drivers +v0x17d5cb0_0 .alias "Command", 2 0, v0x17dc9d0_0; +L_0x17ea840 .part v0x17dda90_0, 0, 1; +S_0x17d53f0 .scope module, "potato" "TwoInMux" 2 66, 2 8, S_0x17d5300; + .timescale -9 -12; +L_0x17ea350/d .functor NOT 1, L_0x17ea840, C4<0>, C4<0>, C4<0>; +L_0x17ea350 .delay (10000,10000,10000) L_0x17ea350/d; +L_0x17ea410/d .functor AND 1, L_0x17ea220, L_0x17ea350, C4<1>, C4<1>; +L_0x17ea410 .delay (20000,20000,20000) L_0x17ea410/d; +L_0x17ea520/d .functor AND 1, L_0x17ea0c0, L_0x17ea840, C4<1>, C4<1>; +L_0x17ea520 .delay (20000,20000,20000) L_0x17ea520/d; +L_0x17ea670/d .functor OR 1, L_0x17ea410, L_0x17ea520, C4<0>, C4<0>; +L_0x17ea670 .delay (20000,20000,20000) L_0x17ea670/d; +v0x17d54e0_0 .net "S", 0 0, L_0x17ea840; 1 drivers +v0x17d5580_0 .alias "in0", 0 0, v0x17d5a20_0; +v0x17d5620_0 .alias "in1", 0 0, v0x17d5aa0_0; +v0x17d56c0_0 .net "nS", 0 0, L_0x17ea350; 1 drivers +v0x17d5740_0 .net "out0", 0 0, L_0x17ea410; 1 drivers +v0x17d57e0_0 .net "out1", 0 0, L_0x17ea520; 1 drivers +v0x17d58c0_0 .alias "outfinal", 0 0, v0x17d5b50_0; +S_0x17cfd60 .scope module, "trial2" "OrNorXor32" 3 29, 2 180, S_0x1782ed0; + .timescale -9 -12; +P_0x17cdeb8 .param/l "size" 2 187, +C4<0100>; +v0x17d4d40_0 .alias "A", 3 0, v0x17dc7b0_0; +v0x17d4e50_0 .alias "B", 3 0, v0x17dc8d0_0; +v0x17d4f60_0 .alias "Command", 2 0, v0x17dc9d0_0; +v0x17d4fe0_0 .alias "OrNorXorOut", 3 0, v0x17ddb90_0; +L_0x17ec700 .part/pv L_0x17ec490, 1, 1, 4; +L_0x17ec830 .part v0x17dd890_0, 1, 1; +L_0x17e37f0 .part v0x17dda10_0, 1, 1; +L_0x17edc60 .part/pv L_0x17ed9f0, 2, 1, 4; +L_0x17edd00 .part v0x17dd890_0, 2, 1; +L_0x17edda0 .part v0x17dda10_0, 2, 1; +L_0x17eef60 .part/pv L_0x17eecf0, 3, 1, 4; +L_0x17ef000 .part v0x17dd890_0, 3, 1; +L_0x17ef0a0 .part v0x17dda10_0, 3, 1; +L_0x17f0250 .part/pv L_0x17effe0, 0, 1, 4; +L_0x17f0350 .part v0x17dd890_0, 0, 1; +L_0x17f03f0 .part v0x17dda10_0, 0, 1; +S_0x17d3b00 .scope module, "attempt2" "OrNorXor" 2 195, 2 70, S_0x17cfd60; + .timescale -9 -12; +L_0x17ef140/d .functor NOR 1, L_0x17f0350, L_0x17f03f0, C4<0>, C4<0>; +L_0x17ef140 .delay (10000,10000,10000) L_0x17ef140/d; +L_0x17ef240/d .functor NOT 1, L_0x17ef140, C4<0>, C4<0>, C4<0>; +L_0x17ef240 .delay (10000,10000,10000) L_0x17ef240/d; +L_0x17ef370/d .functor NAND 1, L_0x17f0350, L_0x17f03f0, C4<1>, C4<1>; +L_0x17ef370 .delay (10000,10000,10000) L_0x17ef370/d; +L_0x17ef4d0/d .functor NAND 1, L_0x17ef370, L_0x17ef240, C4<1>, C4<1>; +L_0x17ef4d0 .delay (10000,10000,10000) L_0x17ef4d0/d; +L_0x17ef5e0/d .functor NOT 1, L_0x17ef4d0, C4<0>, C4<0>, C4<0>; +L_0x17ef5e0 .delay (10000,10000,10000) L_0x17ef5e0/d; +v0x17d4650_0 .net "A", 0 0, L_0x17f0350; 1 drivers +v0x17d46f0_0 .net "AnandB", 0 0, L_0x17ef370; 1 drivers +v0x17d4790_0 .net "AnorB", 0 0, L_0x17ef140; 1 drivers +v0x17d4840_0 .net "AorB", 0 0, L_0x17ef240; 1 drivers +v0x17d4920_0 .net "AxorB", 0 0, L_0x17ef5e0; 1 drivers +v0x17d49d0_0 .net "B", 0 0, L_0x17f03f0; 1 drivers +v0x17d4a90_0 .alias "Command", 2 0, v0x17dc9d0_0; +v0x17d4b10_0 .net "OrNorXorOut", 0 0, L_0x17effe0; 1 drivers +v0x17d4b90_0 .net "XorNor", 0 0, L_0x17efa60; 1 drivers +v0x17d4c60_0 .net "nXor", 0 0, L_0x17ef4d0; 1 drivers +L_0x17efbe0 .part v0x17dda90_0, 2, 1; +L_0x17f01b0 .part v0x17dda90_0, 0, 1; +S_0x17d40e0 .scope module, "mux0" "TwoInMux" 2 89, 2 8, S_0x17d3b00; + .timescale -9 -12; +L_0x17ef740/d .functor NOT 1, L_0x17efbe0, C4<0>, C4<0>, C4<0>; +L_0x17ef740 .delay (10000,10000,10000) L_0x17ef740/d; +L_0x17ef800/d .functor AND 1, L_0x17ef5e0, L_0x17ef740, C4<1>, C4<1>; +L_0x17ef800 .delay (20000,20000,20000) L_0x17ef800/d; +L_0x17ef910/d .functor AND 1, L_0x17ef140, L_0x17efbe0, C4<1>, C4<1>; +L_0x17ef910 .delay (20000,20000,20000) L_0x17ef910/d; +L_0x17efa60/d .functor OR 1, L_0x17ef800, L_0x17ef910, C4<0>, C4<0>; +L_0x17efa60 .delay (20000,20000,20000) L_0x17efa60/d; +v0x17d41d0_0 .net "S", 0 0, L_0x17efbe0; 1 drivers +v0x17d4290_0 .alias "in0", 0 0, v0x17d4920_0; +v0x17d4330_0 .alias "in1", 0 0, v0x17d4790_0; +v0x17d43d0_0 .net "nS", 0 0, L_0x17ef740; 1 drivers +v0x17d4450_0 .net "out0", 0 0, L_0x17ef800; 1 drivers +v0x17d44f0_0 .net "out1", 0 0, L_0x17ef910; 1 drivers +v0x17d45d0_0 .alias "outfinal", 0 0, v0x17d4b90_0; +S_0x17d3bf0 .scope module, "mux1" "TwoInMux" 2 90, 2 8, S_0x17d3b00; + .timescale -9 -12; +L_0x17efc80/d .functor NOT 1, L_0x17f01b0, C4<0>, C4<0>, C4<0>; +L_0x17efc80 .delay (10000,10000,10000) L_0x17efc80/d; +L_0x17efd40/d .functor AND 1, L_0x17efa60, L_0x17efc80, C4<1>, C4<1>; +L_0x17efd40 .delay (20000,20000,20000) L_0x17efd40/d; +L_0x17efe90/d .functor AND 1, L_0x17ef240, L_0x17f01b0, C4<1>, C4<1>; +L_0x17efe90 .delay (20000,20000,20000) L_0x17efe90/d; +L_0x17effe0/d .functor OR 1, L_0x17efd40, L_0x17efe90, C4<0>, C4<0>; +L_0x17effe0 .delay (20000,20000,20000) L_0x17effe0/d; +v0x17d3ce0_0 .net "S", 0 0, L_0x17f01b0; 1 drivers +v0x17d3d60_0 .alias "in0", 0 0, v0x17d4b90_0; +v0x17d3de0_0 .alias "in1", 0 0, v0x17d4840_0; +v0x17d3e80_0 .net "nS", 0 0, L_0x17efc80; 1 drivers +v0x17d3f00_0 .net "out0", 0 0, L_0x17efd40; 1 drivers +v0x17d3fa0_0 .net "out1", 0 0, L_0x17efe90; 1 drivers +v0x17d4040_0 .alias "outfinal", 0 0, v0x17d4b10_0; +S_0x17d2730 .scope generate, "orbits[1]" "orbits[1]" 2 199, 2 199, S_0x17cfd60; + .timescale -9 -12; +P_0x17d2448 .param/l "i" 2 199, +C4<01>; +S_0x17d2860 .scope module, "attempt" "OrNorXor" 2 201, 2 70, S_0x17d2730; + .timescale -9 -12; +L_0x17eb3e0/d .functor NOR 1, L_0x17ec830, L_0x17e37f0, C4<0>, C4<0>; +L_0x17eb3e0 .delay (10000,10000,10000) L_0x17eb3e0/d; +L_0x17eb6f0/d .functor NOT 1, L_0x17eb3e0, C4<0>, C4<0>, C4<0>; +L_0x17eb6f0 .delay (10000,10000,10000) L_0x17eb6f0/d; +L_0x17eb820/d .functor NAND 1, L_0x17ec830, L_0x17e37f0, C4<1>, C4<1>; +L_0x17eb820 .delay (10000,10000,10000) L_0x17eb820/d; +L_0x17eb980/d .functor NAND 1, L_0x17eb820, L_0x17eb6f0, C4<1>, C4<1>; +L_0x17eb980 .delay (10000,10000,10000) L_0x17eb980/d; +L_0x17eba90/d .functor NOT 1, L_0x17eb980, C4<0>, C4<0>, C4<0>; +L_0x17eba90 .delay (10000,10000,10000) L_0x17eba90/d; +v0x17d3410_0 .net "A", 0 0, L_0x17ec830; 1 drivers +v0x17d34b0_0 .net "AnandB", 0 0, L_0x17eb820; 1 drivers +v0x17d3550_0 .net "AnorB", 0 0, L_0x17eb3e0; 1 drivers +v0x17d3600_0 .net "AorB", 0 0, L_0x17eb6f0; 1 drivers +v0x17d36e0_0 .net "AxorB", 0 0, L_0x17eba90; 1 drivers +v0x17d3790_0 .net "B", 0 0, L_0x17e37f0; 1 drivers +v0x17d3850_0 .alias "Command", 2 0, v0x17dc9d0_0; +v0x17d38d0_0 .net "OrNorXorOut", 0 0, L_0x17ec490; 1 drivers +v0x17d3950_0 .net "XorNor", 0 0, L_0x17ebf10; 1 drivers +v0x17d3a20_0 .net "nXor", 0 0, L_0x17eb980; 1 drivers +L_0x17ec090 .part v0x17dda90_0, 2, 1; +L_0x17ec660 .part v0x17dda90_0, 0, 1; +S_0x17d2ea0 .scope module, "mux0" "TwoInMux" 2 89, 2 8, S_0x17d2860; + .timescale -9 -12; +L_0x17ebbf0/d .functor NOT 1, L_0x17ec090, C4<0>, C4<0>, C4<0>; +L_0x17ebbf0 .delay (10000,10000,10000) L_0x17ebbf0/d; +L_0x17ebcb0/d .functor AND 1, L_0x17eba90, L_0x17ebbf0, C4<1>, C4<1>; +L_0x17ebcb0 .delay (20000,20000,20000) L_0x17ebcb0/d; +L_0x17ebdc0/d .functor AND 1, L_0x17eb3e0, L_0x17ec090, C4<1>, C4<1>; +L_0x17ebdc0 .delay (20000,20000,20000) L_0x17ebdc0/d; +L_0x17ebf10/d .functor OR 1, L_0x17ebcb0, L_0x17ebdc0, C4<0>, C4<0>; +L_0x17ebf10 .delay (20000,20000,20000) L_0x17ebf10/d; +v0x17d2f90_0 .net "S", 0 0, L_0x17ec090; 1 drivers +v0x17d3050_0 .alias "in0", 0 0, v0x17d36e0_0; +v0x17d30f0_0 .alias "in1", 0 0, v0x17d3550_0; +v0x17d3190_0 .net "nS", 0 0, L_0x17ebbf0; 1 drivers +v0x17d3210_0 .net "out0", 0 0, L_0x17ebcb0; 1 drivers +v0x17d32b0_0 .net "out1", 0 0, L_0x17ebdc0; 1 drivers +v0x17d3390_0 .alias "outfinal", 0 0, v0x17d3950_0; +S_0x17d2950 .scope module, "mux1" "TwoInMux" 2 90, 2 8, S_0x17d2860; + .timescale -9 -12; +L_0x17ec130/d .functor NOT 1, L_0x17ec660, C4<0>, C4<0>, C4<0>; +L_0x17ec130 .delay (10000,10000,10000) L_0x17ec130/d; +L_0x17ec1f0/d .functor AND 1, L_0x17ebf10, L_0x17ec130, C4<1>, C4<1>; +L_0x17ec1f0 .delay (20000,20000,20000) L_0x17ec1f0/d; +L_0x17ec340/d .functor AND 1, L_0x17eb6f0, L_0x17ec660, C4<1>, C4<1>; +L_0x17ec340 .delay (20000,20000,20000) L_0x17ec340/d; +L_0x17ec490/d .functor OR 1, L_0x17ec1f0, L_0x17ec340, C4<0>, C4<0>; +L_0x17ec490 .delay (20000,20000,20000) L_0x17ec490/d; +v0x17d2a40_0 .net "S", 0 0, L_0x17ec660; 1 drivers +v0x17d2ac0_0 .alias "in0", 0 0, v0x17d3950_0; +v0x17d2b60_0 .alias "in1", 0 0, v0x17d3600_0; +v0x17d2c00_0 .net "nS", 0 0, L_0x17ec130; 1 drivers +v0x17d2c80_0 .net "out0", 0 0, L_0x17ec1f0; 1 drivers +v0x17d2d20_0 .net "out1", 0 0, L_0x17ec340; 1 drivers +v0x17d2e00_0 .alias "outfinal", 0 0, v0x17d38d0_0; +S_0x17d1360 .scope generate, "orbits[2]" "orbits[2]" 2 199, 2 199, S_0x17cfd60; + .timescale -9 -12; +P_0x17d0fc8 .param/l "i" 2 199, +C4<010>; +S_0x17d1490 .scope module, "attempt" "OrNorXor" 2 201, 2 70, S_0x17d1360; + .timescale -9 -12; +L_0x17e3890/d .functor NOR 1, L_0x17edd00, L_0x17edda0, C4<0>, C4<0>; +L_0x17e3890 .delay (10000,10000,10000) L_0x17e3890/d; +L_0x17e3a00/d .functor NOT 1, L_0x17e3890, C4<0>, C4<0>, C4<0>; +L_0x17e3a00 .delay (10000,10000,10000) L_0x17e3a00/d; +L_0x17ecd80/d .functor NAND 1, L_0x17edd00, L_0x17edda0, C4<1>, C4<1>; +L_0x17ecd80 .delay (10000,10000,10000) L_0x17ecd80/d; +L_0x17ecee0/d .functor NAND 1, L_0x17ecd80, L_0x17e3a00, C4<1>, C4<1>; +L_0x17ecee0 .delay (10000,10000,10000) L_0x17ecee0/d; +L_0x17ecff0/d .functor NOT 1, L_0x17ecee0, C4<0>, C4<0>, C4<0>; +L_0x17ecff0 .delay (10000,10000,10000) L_0x17ecff0/d; +v0x17d2040_0 .net "A", 0 0, L_0x17edd00; 1 drivers +v0x17d20e0_0 .net "AnandB", 0 0, L_0x17ecd80; 1 drivers +v0x17d2180_0 .net "AnorB", 0 0, L_0x17e3890; 1 drivers +v0x17d2230_0 .net "AorB", 0 0, L_0x17e3a00; 1 drivers +v0x17d2310_0 .net "AxorB", 0 0, L_0x17ecff0; 1 drivers +v0x17d23c0_0 .net "B", 0 0, L_0x17edda0; 1 drivers +v0x17d2480_0 .alias "Command", 2 0, v0x17dc9d0_0; +v0x17d2500_0 .net "OrNorXorOut", 0 0, L_0x17ed9f0; 1 drivers +v0x17d2580_0 .net "XorNor", 0 0, L_0x17ed470; 1 drivers +v0x17d2650_0 .net "nXor", 0 0, L_0x17ecee0; 1 drivers +L_0x17ed5f0 .part v0x17dda90_0, 2, 1; +L_0x17edbc0 .part v0x17dda90_0, 0, 1; +S_0x17d1ad0 .scope module, "mux0" "TwoInMux" 2 89, 2 8, S_0x17d1490; + .timescale -9 -12; +L_0x17ed150/d .functor NOT 1, L_0x17ed5f0, C4<0>, C4<0>, C4<0>; +L_0x17ed150 .delay (10000,10000,10000) L_0x17ed150/d; +L_0x17ed210/d .functor AND 1, L_0x17ecff0, L_0x17ed150, C4<1>, C4<1>; +L_0x17ed210 .delay (20000,20000,20000) L_0x17ed210/d; +L_0x17ed320/d .functor AND 1, L_0x17e3890, L_0x17ed5f0, C4<1>, C4<1>; +L_0x17ed320 .delay (20000,20000,20000) L_0x17ed320/d; +L_0x17ed470/d .functor OR 1, L_0x17ed210, L_0x17ed320, C4<0>, C4<0>; +L_0x17ed470 .delay (20000,20000,20000) L_0x17ed470/d; +v0x17d1bc0_0 .net "S", 0 0, L_0x17ed5f0; 1 drivers +v0x17d1c80_0 .alias "in0", 0 0, v0x17d2310_0; +v0x17d1d20_0 .alias "in1", 0 0, v0x17d2180_0; +v0x17d1dc0_0 .net "nS", 0 0, L_0x17ed150; 1 drivers +v0x17d1e40_0 .net "out0", 0 0, L_0x17ed210; 1 drivers +v0x17d1ee0_0 .net "out1", 0 0, L_0x17ed320; 1 drivers +v0x17d1fc0_0 .alias "outfinal", 0 0, v0x17d2580_0; +S_0x17d1580 .scope module, "mux1" "TwoInMux" 2 90, 2 8, S_0x17d1490; + .timescale -9 -12; +L_0x17ed690/d .functor NOT 1, L_0x17edbc0, C4<0>, C4<0>, C4<0>; +L_0x17ed690 .delay (10000,10000,10000) L_0x17ed690/d; +L_0x17ed750/d .functor AND 1, L_0x17ed470, L_0x17ed690, C4<1>, C4<1>; +L_0x17ed750 .delay (20000,20000,20000) L_0x17ed750/d; +L_0x17ed8a0/d .functor AND 1, L_0x17e3a00, L_0x17edbc0, C4<1>, C4<1>; +L_0x17ed8a0 .delay (20000,20000,20000) L_0x17ed8a0/d; +L_0x17ed9f0/d .functor OR 1, L_0x17ed750, L_0x17ed8a0, C4<0>, C4<0>; +L_0x17ed9f0 .delay (20000,20000,20000) L_0x17ed9f0/d; +v0x17d1670_0 .net "S", 0 0, L_0x17edbc0; 1 drivers +v0x17d16f0_0 .alias "in0", 0 0, v0x17d2580_0; +v0x17d1790_0 .alias "in1", 0 0, v0x17d2230_0; +v0x17d1830_0 .net "nS", 0 0, L_0x17ed690; 1 drivers +v0x17d18b0_0 .net "out0", 0 0, L_0x17ed750; 1 drivers +v0x17d1950_0 .net "out1", 0 0, L_0x17ed8a0; 1 drivers +v0x17d1a30_0 .alias "outfinal", 0 0, v0x17d2500_0; +S_0x17cfe90 .scope generate, "orbits[3]" "orbits[3]" 2 199, 2 199, S_0x17cfd60; + .timescale -9 -12; +P_0x17cff88 .param/l "i" 2 199, +C4<011>; +S_0x17d0000 .scope module, "attempt" "OrNorXor" 2 201, 2 70, S_0x17cfe90; + .timescale -9 -12; +L_0x17ede80/d .functor NOR 1, L_0x17ef000, L_0x17ef0a0, C4<0>, C4<0>; +L_0x17ede80 .delay (10000,10000,10000) L_0x17ede80/d; +L_0x17edf70/d .functor NOT 1, L_0x17ede80, C4<0>, C4<0>, C4<0>; +L_0x17edf70 .delay (10000,10000,10000) L_0x17edf70/d; +L_0x17ee080/d .functor NAND 1, L_0x17ef000, L_0x17ef0a0, C4<1>, C4<1>; +L_0x17ee080 .delay (10000,10000,10000) L_0x17ee080/d; +L_0x17ee1e0/d .functor NAND 1, L_0x17ee080, L_0x17edf70, C4<1>, C4<1>; +L_0x17ee1e0 .delay (10000,10000,10000) L_0x17ee1e0/d; +L_0x17ee2f0/d .functor NOT 1, L_0x17ee1e0, C4<0>, C4<0>, C4<0>; +L_0x17ee2f0 .delay (10000,10000,10000) L_0x17ee2f0/d; +v0x17d0bc0_0 .net "A", 0 0, L_0x17ef000; 1 drivers +v0x17d0c60_0 .net "AnandB", 0 0, L_0x17ee080; 1 drivers +v0x17d0d00_0 .net "AnorB", 0 0, L_0x17ede80; 1 drivers +v0x17d0db0_0 .net "AorB", 0 0, L_0x17edf70; 1 drivers +v0x17d0e90_0 .net "AxorB", 0 0, L_0x17ee2f0; 1 drivers +v0x17d0f40_0 .net "B", 0 0, L_0x17ef0a0; 1 drivers +v0x17d1000_0 .alias "Command", 2 0, v0x17dc9d0_0; +v0x17c9a50_0 .net "OrNorXorOut", 0 0, L_0x17eecf0; 1 drivers +v0x17c9ad0_0 .net "XorNor", 0 0, L_0x17ee770; 1 drivers +v0x17d12e0_0 .net "nXor", 0 0, L_0x17ee1e0; 1 drivers +L_0x17ee8f0 .part v0x17dda90_0, 2, 1; +L_0x17eeec0 .part v0x17dda90_0, 0, 1; +S_0x17d0650 .scope module, "mux0" "TwoInMux" 2 89, 2 8, S_0x17d0000; + .timescale -9 -12; +L_0x17ee450/d .functor NOT 1, L_0x17ee8f0, C4<0>, C4<0>, C4<0>; +L_0x17ee450 .delay (10000,10000,10000) L_0x17ee450/d; +L_0x17ee510/d .functor AND 1, L_0x17ee2f0, L_0x17ee450, C4<1>, C4<1>; +L_0x17ee510 .delay (20000,20000,20000) L_0x17ee510/d; +L_0x17ee620/d .functor AND 1, L_0x17ede80, L_0x17ee8f0, C4<1>, C4<1>; +L_0x17ee620 .delay (20000,20000,20000) L_0x17ee620/d; +L_0x17ee770/d .functor OR 1, L_0x17ee510, L_0x17ee620, C4<0>, C4<0>; +L_0x17ee770 .delay (20000,20000,20000) L_0x17ee770/d; +v0x17d0740_0 .net "S", 0 0, L_0x17ee8f0; 1 drivers +v0x17d0800_0 .alias "in0", 0 0, v0x17d0e90_0; +v0x17d08a0_0 .alias "in1", 0 0, v0x17d0d00_0; +v0x17d0940_0 .net "nS", 0 0, L_0x17ee450; 1 drivers +v0x17d09c0_0 .net "out0", 0 0, L_0x17ee510; 1 drivers +v0x17d0a60_0 .net "out1", 0 0, L_0x17ee620; 1 drivers +v0x17d0b40_0 .alias "outfinal", 0 0, v0x17c9ad0_0; +S_0x17d00f0 .scope module, "mux1" "TwoInMux" 2 90, 2 8, S_0x17d0000; + .timescale -9 -12; +L_0x17ee990/d .functor NOT 1, L_0x17eeec0, C4<0>, C4<0>, C4<0>; +L_0x17ee990 .delay (10000,10000,10000) L_0x17ee990/d; +L_0x17eea50/d .functor AND 1, L_0x17ee770, L_0x17ee990, C4<1>, C4<1>; +L_0x17eea50 .delay (20000,20000,20000) L_0x17eea50/d; +L_0x17eeba0/d .functor AND 1, L_0x17edf70, L_0x17eeec0, C4<1>, C4<1>; +L_0x17eeba0 .delay (20000,20000,20000) L_0x17eeba0/d; +L_0x17eecf0/d .functor OR 1, L_0x17eea50, L_0x17eeba0, C4<0>, C4<0>; +L_0x17eecf0 .delay (20000,20000,20000) L_0x17eecf0/d; +v0x17d01e0_0 .net "S", 0 0, L_0x17eeec0; 1 drivers +v0x17d0260_0 .alias "in0", 0 0, v0x17c9ad0_0; +v0x17d02e0_0 .alias "in1", 0 0, v0x17d0db0_0; +v0x17d0380_0 .net "nS", 0 0, L_0x17ee990; 1 drivers +v0x17d0430_0 .net "out0", 0 0, L_0x17eea50; 1 drivers +v0x17d04d0_0 .net "out1", 0 0, L_0x17eeba0; 1 drivers +v0x17d05b0_0 .alias "outfinal", 0 0, v0x17c9a50_0; +S_0x17bb1b0 .scope module, "superalu" "Bitslice32" 3 31, 2 262, S_0x1782ed0; + .timescale -9 -12; +P_0x17ba1f8 .param/l "size" 2 277, +C4<0100>; +v0x17cf380_0 .alias "A", 3 0, v0x17dc7b0_0; +v0x17cf570_0 .alias "AddSubSLTSum", 3 0, v0x17dd910_0; +v0x17cf5f0_0 .alias "AndNandOut", 3 0, v0x17dd990_0; +v0x17cf670_0 .alias "B", 3 0, v0x17dc8d0_0; +RS_0x7ff970b2cae8 .resolv tri, L_0x17f0b90, L_0x17f31f0, L_0x17f5be0, L_0x1805bf0; +v0x17cf720_0 .net8 "Cmd0Start", 3 0, RS_0x7ff970b2cae8; 4 drivers +RS_0x7ff970b2cb18 .resolv tri, L_0x17f1aa0, L_0x17f40d0, L_0x17f6ba0, L_0x18069b0; +v0x17cf7a0_0 .net8 "Cmd1Start", 3 0, RS_0x7ff970b2cb18; 4 drivers +v0x17cf820_0 .alias "Command", 2 0, v0x17dc9d0_0; +v0x17cf8a0_0 .alias "OneBitFinalOut", 3 0, v0x17ddb10_0; +v0x17cf920_0 .alias "OrNorXorOut", 3 0, v0x17ddb90_0; +v0x17cf9a0_0 .alias "SLTflag", 0 0, v0x17ddc10_0; +v0x17cfa50_0 .alias "carryin", 3 0, v0x17dd400_0; +v0x17cfb00_0 .alias "carryout", 0 0, v0x17ddd10_0; +v0x17cfbb0_0 .alias "overflow", 0 0, v0x17ddd90_0; +v0x17cfc60_0 .alias "subtract", 3 0, v0x17dde10_0; +L_0x17f0b90 .part/pv L_0x17f09b0, 1, 1, 4; +L_0x17f0c30 .part v0x17dda90_0, 0, 1; +L_0x17f0d60 .part v0x17dda90_0, 1, 1; +L_0x17f0e90 .part RS_0x7ff970b2c6f8, 1, 1; +L_0x17f0f30 .part RS_0x7ff970b2c6f8, 1, 1; +L_0x17f0fd0 .part RS_0x7ff970b2b258, 1, 1; +L_0x17f11d0 .part RS_0x7ff970b2c6f8, 1, 1; +L_0x17f1aa0 .part/pv L_0x17f1890, 1, 1, 4; +L_0x17f1b90 .part v0x17dda90_0, 0, 1; +L_0x17f1cc0 .part v0x17dda90_0, 1, 1; +L_0x17f1e50 .part RS_0x7ff970b2b948, 1, 1; +L_0x17f2000 .part RS_0x7ff970b2b948, 1, 1; +L_0x17f20a0 .part RS_0x7ff970b2b258, 1, 1; +L_0x17f2140 .part RS_0x7ff970b2b258, 1, 1; +L_0x17f25a0 .part/pv L_0x17f2460, 1, 1, 4; +L_0x17f2690 .part v0x17dda90_0, 2, 1; +L_0x17f2730 .part RS_0x7ff970b2cae8, 1, 1; +L_0x17f2870 .part RS_0x7ff970b2cb18, 1, 1; +L_0x17f31f0 .part/pv L_0x17f2fe0, 2, 1, 4; +L_0x17f3290 .part v0x17dda90_0, 0, 1; +L_0x17f29b0 .part v0x17dda90_0, 1, 1; +L_0x17f3500 .part RS_0x7ff970b2c6f8, 2, 1; +L_0x17f33c0 .part RS_0x7ff970b2c6f8, 2, 1; +L_0x17f3660 .part RS_0x7ff970b2b258, 2, 1; +L_0x17f35a0 .part RS_0x7ff970b2c6f8, 2, 1; +L_0x17f40d0 .part/pv L_0x17f3ec0, 2, 1, 4; +L_0x17f3750 .part v0x17dda90_0, 0, 1; +L_0x17e2910 .part v0x17dda90_0, 1, 1; +L_0x17f4170 .part RS_0x7ff970b2b948, 2, 1; +L_0x17e2b30 .part RS_0x7ff970b2b948, 2, 1; +L_0x17e2a40 .part RS_0x7ff970b2b258, 2, 1; +L_0x17f4af0 .part RS_0x7ff970b2b258, 2, 1; +L_0x17f4f80 .part/pv L_0x17f4e40, 2, 1, 4; +L_0x17f5020 .part v0x17dda90_0, 2, 1; +L_0x17f4b90 .part RS_0x7ff970b2cae8, 2, 1; +L_0x17f5270 .part RS_0x7ff970b2cb18, 2, 1; +L_0x17f5be0 .part/pv L_0x17f59d0, 3, 1, 4; +L_0x17f5c80 .part v0x17dda90_0, 0, 1; +L_0x17f53a0 .part v0x17dda90_0, 1, 1; +L_0x17f5ef0 .part RS_0x7ff970b2c6f8, 3, 1; +L_0x17e85e0 .part RS_0x7ff970b2c6f8, 3, 1; +L_0x17f5db0 .part RS_0x7ff970b2b258, 3, 1; +L_0x17f6300 .part RS_0x7ff970b2c6f8, 3, 1; +L_0x17f6ba0 .part/pv L_0x17f6990, 3, 1, 4; +L_0x17f61a0 .part v0x17dda90_0, 0, 1; +L_0x17f6db0 .part v0x17dda90_0, 1, 1; +L_0x17f6c40 .part RS_0x7ff970b2b948, 3, 1; +L_0x17f6ce0 .part RS_0x7ff970b2b948, 3, 1; +L_0x17f7070 .part RS_0x7ff970b2b258, 3, 1; +L_0x17f7160 .part RS_0x7ff970b2b258, 3, 1; +L_0x17f7790 .part/pv L_0x17f7650, 3, 1, 4; +L_0x17f78c0 .part v0x17dda90_0, 2, 1; +L_0x17f7460 .part RS_0x7ff970b2cae8, 3, 1; +L_0x17f7500 .part RS_0x7ff970b2cb18, 3, 1; +L_0x1805bf0 .part/pv L_0x1805a10, 0, 1, 4; +L_0x1805c90 .part v0x17dda90_0, 0, 1; +L_0x17f7960 .part v0x17dda90_0, 1, 1; +L_0x1805f90 .part RS_0x7ff970b2c6f8, 0, 1; +L_0x1805dc0 .part RS_0x7ff970b2c6f8, 0, 1; +L_0x1805e60 .part RS_0x7ff970b2b258, 0, 1; +L_0x1806220 .part RS_0x7ff970b2c6f8, 0, 1; +L_0x18069b0 .part/pv L_0x18067d0, 0, 1, 4; +L_0x1806030 .part v0x17dda90_0, 0, 1; +L_0x1806160 .part v0x17dda90_0, 1, 1; +L_0x1806a50 .part RS_0x7ff970b2b948, 0, 1; +L_0x1806af0 .part RS_0x7ff970b2b948, 0, 1; +L_0x1806b90 .part RS_0x7ff970b2b258, 0, 1; +L_0x1806f50 .part RS_0x7ff970b2b258, 0, 1; +L_0x1807460 .part/pv L_0x1807320, 0, 1, 4; +L_0x1807500 .part v0x17dda90_0, 2, 1; +L_0x1807040 .part RS_0x7ff970b2cae8, 0, 1; +L_0x18077e0 .part RS_0x7ff970b2cb18, 0, 1; +S_0x17c9d40 .scope module, "trial" "AddSubSLT32" 2 282, 2 209, S_0x17bb1b0; + .timescale -9 -12; +P_0x17c9e38 .param/l "size" 2 232, +C4<0100>; +L_0x17fcb80/d .functor OR 1, L_0x17fce40, C4<0>, C4<0>, C4<0>; +L_0x17fcb80 .delay (20000,20000,20000) L_0x17fcb80/d; +L_0x17fcff0/d .functor XOR 1, RS_0x7ff970b2c9f8, L_0x17fd0e0, C4<0>, C4<0>; +L_0x17fcff0 .delay (40000,40000,40000) L_0x17fcff0/d; +L_0x17fcd70/d .functor AND 1, L_0x17fd2b0, L_0x17fd350, C4<1>, C4<1>; +L_0x17fcd70 .delay (20000,20000,20000) L_0x17fcd70/d; +L_0x17fd180/d .functor NOT 1, RS_0x7ff970b2ca88, C4<0>, C4<0>, C4<0>; +L_0x17fd180 .delay (10000,10000,10000) L_0x17fd180/d; +L_0x17fd640/d .functor NOT 1, L_0x17fd6a0, C4<0>, C4<0>, C4<0>; +L_0x17fd640 .delay (10000,10000,10000) L_0x17fd640/d; +L_0x17fd740/d .functor AND 1, L_0x17fd180, L_0x17fd880, C4<1>, C4<1>; +L_0x17fd740 .delay (20000,20000,20000) L_0x17fd740/d; +L_0x17fd440/d .functor AND 1, RS_0x7ff970b2ca88, L_0x17fd640, C4<1>, C4<1>; +L_0x17fd440 .delay (20000,20000,20000) L_0x17fd440/d; +L_0x17fda70/d .functor AND 1, L_0x17fd740, L_0x17fcd70, C4<1>, C4<1>; +L_0x17fda70 .delay (20000,20000,20000) L_0x17fda70/d; +L_0x17fdbb0/d .functor AND 1, L_0x17fd440, L_0x17fcd70, C4<1>, C4<1>; +L_0x17fdbb0 .delay (20000,20000,20000) L_0x17fdbb0/d; +L_0x17fdcd0/d .functor OR 1, L_0x17fda70, L_0x17fdbb0, C4<0>, C4<0>; +L_0x17fdcd0 .delay (20000,20000,20000) L_0x17fdcd0/d; +v0x17ce4a0_0 .alias "A", 3 0, v0x17dc7b0_0; +v0x17ce540_0 .alias "AddSubSLTSum", 3 0, v0x17dd910_0; +v0x17ce5e0_0 .alias "B", 3 0, v0x17dc8d0_0; +RS_0x7ff970b2c728 .resolv tri, L_0x17f8af0, L_0x17f9f10, L_0x17fb310, L_0x17fc8f0; +v0x17ce6b0_0 .net8 "CarryoutWire", 3 0, RS_0x7ff970b2c728; 4 drivers +v0x17ce730_0 .alias "Command", 2 0, v0x17dc9d0_0; +v0x17ce7b0_0 .net "Res0OF1", 0 0, L_0x17fd440; 1 drivers +v0x17ce850_0 .net "Res1OF0", 0 0, L_0x17fd740; 1 drivers +v0x17ce8f0_0 .alias "SLTflag", 0 0, v0x17ddc10_0; +v0x17ce9e0_0 .net "SLTflag0", 0 0, L_0x17fda70; 1 drivers +v0x17cea80_0 .net "SLTflag1", 0 0, L_0x17fdbb0; 1 drivers +v0x17ceb20_0 .net "SLTon", 0 0, L_0x17fcd70; 1 drivers +v0x17cebc0_0 .net *"_s40", 0 0, L_0x17fce40; 1 drivers +v0x17cec60_0 .net/s *"_s41", 0 0, C4<0>; 1 drivers +v0x17ced00_0 .net *"_s44", 0 0, L_0x17fd0e0; 1 drivers +v0x17cee20_0 .net *"_s46", 0 0, L_0x17fd2b0; 1 drivers +v0x17ceec0_0 .net *"_s48", 0 0, L_0x17fd350; 1 drivers +v0x17ced80_0 .net *"_s50", 0 0, L_0x17fd6a0; 1 drivers +v0x17cf010_0 .net *"_s52", 0 0, L_0x17fd880; 1 drivers +v0x17cf130_0 .alias "carryin", 3 0, v0x17dd400_0; +v0x17cf1b0_0 .alias "carryout", 0 0, v0x17ddd10_0; +v0x17cf090_0 .net "nAddSubSLTSum", 0 0, L_0x17fd640; 1 drivers +v0x17cf2e0_0 .net "nOF", 0 0, L_0x17fd180; 1 drivers +v0x17cf230_0 .alias "overflow", 0 0, v0x17ddd90_0; +v0x17cf420_0 .alias "subtract", 3 0, v0x17dde10_0; +L_0x17f8a00 .part/pv L_0x17f8570, 1, 1, 4; +L_0x17f8af0 .part/pv L_0x17f88c0, 1, 1, 4; +L_0x17f8be0 .part/pv L_0x17f82a0, 1, 1, 4; +L_0x17f8cd0 .part v0x17dd890_0, 1, 1; +L_0x17f8d70 .part v0x17dda10_0, 1, 1; +L_0x17f8ea0 .part RS_0x7ff970b2c728, 0, 1; +L_0x17f9e20 .part/pv L_0x17f9990, 2, 1, 4; +L_0x17f9f10 .part/pv L_0x17f9ce0, 2, 1, 4; +L_0x17fa050 .part/pv L_0x17f96c0, 2, 1, 4; +L_0x17fa140 .part v0x17dd890_0, 2, 1; +L_0x17fa240 .part v0x17dda10_0, 2, 1; +L_0x17fa370 .part RS_0x7ff970b2c728, 1, 1; +L_0x17fb220 .part/pv L_0x17fad90, 3, 1, 4; +L_0x17fb310 .part/pv L_0x17fb0e0, 3, 1, 4; +L_0x17fb480 .part/pv L_0x17faac0, 3, 1, 4; +L_0x17fb570 .part v0x17dd890_0, 3, 1; +L_0x17fb6a0 .part v0x17dda10_0, 3, 1; +L_0x17fb7d0 .part RS_0x7ff970b2c728, 2, 1; +L_0x17fc800 .part/pv L_0x17fc330, 0, 1, 4; +L_0x17fc8f0 .part/pv L_0x17fc6a0, 0, 1, 4; +L_0x17fb870 .part/pv L_0x17fc060, 0, 1, 4; +L_0x17fcae0 .part v0x17dd890_0, 0, 1; +L_0x17fc9e0 .part v0x17dda10_0, 0, 1; +L_0x17fccd0 .part RS_0x7ff970b2cab8, 0, 1; +L_0x17fce40 .part RS_0x7ff970b2c728, 3, 1; +L_0x17fd0e0 .part RS_0x7ff970b2c728, 2, 1; +L_0x17fd2b0 .part v0x17dda90_0, 1, 1; +L_0x17fd350 .part RS_0x7ff970b2cab8, 0, 1; +L_0x17fd6a0 .part RS_0x7ff970b2c6f8, 3, 1; +L_0x17fd880 .part RS_0x7ff970b2c6f8, 3, 1; +S_0x17cd490 .scope module, "attempt2" "MiddleAddSubSLT" 2 229, 2 95, S_0x17c9d40; + .timescale -9 -12; +L_0x17fb610/d .functor NOT 1, L_0x17fc9e0, C4<0>, C4<0>, C4<0>; +L_0x17fb610 .delay (10000,10000,10000) L_0x17fb610/d; +L_0x17fbf00/d .functor NOT 1, L_0x17fbfc0, C4<0>, C4<0>, C4<0>; +L_0x17fbf00 .delay (10000,10000,10000) L_0x17fbf00/d; +L_0x17fc060/d .functor AND 1, L_0x17fc1a0, L_0x17fbf00, C4<1>, C4<1>; +L_0x17fc060 .delay (20000,20000,20000) L_0x17fc060/d; +L_0x17fc240/d .functor XOR 1, L_0x17fcae0, L_0x17fbc90, C4<0>, C4<0>; +L_0x17fc240 .delay (40000,40000,40000) L_0x17fc240/d; +L_0x17fc330/d .functor XOR 1, L_0x17fc240, L_0x17fccd0, C4<0>, C4<0>; +L_0x17fc330 .delay (40000,40000,40000) L_0x17fc330/d; +L_0x17fc420/d .functor AND 1, L_0x17fcae0, L_0x17fbc90, C4<1>, C4<1>; +L_0x17fc420 .delay (20000,20000,20000) L_0x17fc420/d; +L_0x17fc590/d .functor AND 1, L_0x17fc240, L_0x17fccd0, C4<1>, C4<1>; +L_0x17fc590 .delay (20000,20000,20000) L_0x17fc590/d; +L_0x17fc6a0/d .functor OR 1, L_0x17fc420, L_0x17fc590, C4<0>, C4<0>; +L_0x17fc6a0 .delay (20000,20000,20000) L_0x17fc6a0/d; +v0x17cdb00_0 .net "A", 0 0, L_0x17fcae0; 1 drivers +v0x17cdbc0_0 .net "AandB", 0 0, L_0x17fc420; 1 drivers +v0x17cdc60_0 .net "AddSubSLTSum", 0 0, L_0x17fc330; 1 drivers +v0x17cdd00_0 .net "AxorB", 0 0, L_0x17fc240; 1 drivers +v0x17cdd80_0 .net "B", 0 0, L_0x17fc9e0; 1 drivers +v0x17cde30_0 .net "BornB", 0 0, L_0x17fbc90; 1 drivers +v0x17cdef0_0 .net "CINandAxorB", 0 0, L_0x17fc590; 1 drivers +v0x17cdf70_0 .alias "Command", 2 0, v0x17dc9d0_0; +v0x17cdff0_0 .net *"_s3", 0 0, L_0x17fbfc0; 1 drivers +v0x17ce070_0 .net *"_s5", 0 0, L_0x17fc1a0; 1 drivers +v0x17ce110_0 .net "carryin", 0 0, L_0x17fccd0; 1 drivers +v0x17ce1b0_0 .net "carryout", 0 0, L_0x17fc6a0; 1 drivers +v0x17ce250_0 .net "nB", 0 0, L_0x17fb610; 1 drivers +v0x17ce300_0 .net "nCmd2", 0 0, L_0x17fbf00; 1 drivers +v0x17ce400_0 .net "subtract", 0 0, L_0x17fc060; 1 drivers +L_0x17fbe60 .part v0x17dda90_0, 0, 1; +L_0x17fbfc0 .part v0x17dda90_0, 2, 1; +L_0x17fc1a0 .part v0x17dda90_0, 0, 1; +S_0x17cd580 .scope module, "mux0" "TwoInMux" 2 111, 2 8, S_0x17cd490; + .timescale -9 -12; +L_0x17fb9b0/d .functor NOT 1, L_0x17fbe60, C4<0>, C4<0>, C4<0>; +L_0x17fb9b0 .delay (10000,10000,10000) L_0x17fb9b0/d; +L_0x17fba70/d .functor AND 1, L_0x17fc9e0, L_0x17fb9b0, C4<1>, C4<1>; +L_0x17fba70 .delay (20000,20000,20000) L_0x17fba70/d; +L_0x17fbb80/d .functor AND 1, L_0x17fb610, L_0x17fbe60, C4<1>, C4<1>; +L_0x17fbb80 .delay (20000,20000,20000) L_0x17fbb80/d; +L_0x17fbc90/d .functor OR 1, L_0x17fba70, L_0x17fbb80, C4<0>, C4<0>; +L_0x17fbc90 .delay (20000,20000,20000) L_0x17fbc90/d; +v0x17cd670_0 .net "S", 0 0, L_0x17fbe60; 1 drivers +v0x17cd730_0 .alias "in0", 0 0, v0x17cdd80_0; +v0x17cd7d0_0 .alias "in1", 0 0, v0x17ce250_0; +v0x17cd870_0 .net "nS", 0 0, L_0x17fb9b0; 1 drivers +v0x17cd920_0 .net "out0", 0 0, L_0x17fba70; 1 drivers +v0x17cd9c0_0 .net "out1", 0 0, L_0x17fbb80; 1 drivers +v0x17cda60_0 .alias "outfinal", 0 0, v0x17cde30_0; +S_0x17cc2f0 .scope generate, "addbits[1]" "addbits[1]" 2 234, 2 234, S_0x17c9d40; + .timescale -9 -12; +P_0x17cbd08 .param/l "i" 2 234, +C4<01>; +S_0x17cc460 .scope module, "attempt" "MiddleAddSubSLT" 2 236, 2 95, S_0x17cc2f0; + .timescale -9 -12; +L_0x17f7b20/d .functor NOT 1, L_0x17f8d70, C4<0>, C4<0>, C4<0>; +L_0x17f7b20 .delay (10000,10000,10000) L_0x17f7b20/d; +L_0x17f8160/d .functor NOT 1, L_0x17f8200, C4<0>, C4<0>, C4<0>; +L_0x17f8160 .delay (10000,10000,10000) L_0x17f8160/d; +L_0x17f82a0/d .functor AND 1, L_0x17f83e0, L_0x17f8160, C4<1>, C4<1>; +L_0x17f82a0 .delay (20000,20000,20000) L_0x17f82a0/d; +L_0x17f8480/d .functor XOR 1, L_0x17f8cd0, L_0x17f7f30, C4<0>, C4<0>; +L_0x17f8480 .delay (40000,40000,40000) L_0x17f8480/d; +L_0x17f8570/d .functor XOR 1, L_0x17f8480, L_0x17f8ea0, C4<0>, C4<0>; +L_0x17f8570 .delay (40000,40000,40000) L_0x17f8570/d; +L_0x17f8660/d .functor AND 1, L_0x17f8cd0, L_0x17f7f30, C4<1>, C4<1>; +L_0x17f8660 .delay (20000,20000,20000) L_0x17f8660/d; +L_0x17f87d0/d .functor AND 1, L_0x17f8480, L_0x17f8ea0, C4<1>, C4<1>; +L_0x17f87d0 .delay (20000,20000,20000) L_0x17f87d0/d; +L_0x17f88c0/d .functor OR 1, L_0x17f8660, L_0x17f87d0, C4<0>, C4<0>; +L_0x17f88c0 .delay (20000,20000,20000) L_0x17f88c0/d; +v0x17ccaf0_0 .net "A", 0 0, L_0x17f8cd0; 1 drivers +v0x17ccbb0_0 .net "AandB", 0 0, L_0x17f8660; 1 drivers +v0x17ccc50_0 .net "AddSubSLTSum", 0 0, L_0x17f8570; 1 drivers +v0x17cccf0_0 .net "AxorB", 0 0, L_0x17f8480; 1 drivers +v0x17ccd70_0 .net "B", 0 0, L_0x17f8d70; 1 drivers +v0x17cce20_0 .net "BornB", 0 0, L_0x17f7f30; 1 drivers +v0x17ccee0_0 .net "CINandAxorB", 0 0, L_0x17f87d0; 1 drivers +v0x17ccf60_0 .alias "Command", 2 0, v0x17dc9d0_0; +v0x17ccfe0_0 .net *"_s3", 0 0, L_0x17f8200; 1 drivers +v0x17cd060_0 .net *"_s5", 0 0, L_0x17f83e0; 1 drivers +v0x17cd100_0 .net "carryin", 0 0, L_0x17f8ea0; 1 drivers +v0x17cd1a0_0 .net "carryout", 0 0, L_0x17f88c0; 1 drivers +v0x17cd240_0 .net "nB", 0 0, L_0x17f7b20; 1 drivers +v0x17cd2f0_0 .net "nCmd2", 0 0, L_0x17f8160; 1 drivers +v0x17cd3f0_0 .net "subtract", 0 0, L_0x17f82a0; 1 drivers +L_0x17f80c0 .part v0x17dda90_0, 0, 1; +L_0x17f8200 .part v0x17dda90_0, 2, 1; +L_0x17f83e0 .part v0x17dda90_0, 0, 1; +S_0x17cc550 .scope module, "mux0" "TwoInMux" 2 111, 2 8, S_0x17cc460; + .timescale -9 -12; +L_0x17f7cb0/d .functor NOT 1, L_0x17f80c0, C4<0>, C4<0>, C4<0>; +L_0x17f7cb0 .delay (10000,10000,10000) L_0x17f7cb0/d; +L_0x17f7d50/d .functor AND 1, L_0x17f8d70, L_0x17f7cb0, C4<1>, C4<1>; +L_0x17f7d50 .delay (20000,20000,20000) L_0x17f7d50/d; +L_0x17f7e40/d .functor AND 1, L_0x17f7b20, L_0x17f80c0, C4<1>, C4<1>; +L_0x17f7e40 .delay (20000,20000,20000) L_0x17f7e40/d; +L_0x17f7f30/d .functor OR 1, L_0x17f7d50, L_0x17f7e40, C4<0>, C4<0>; +L_0x17f7f30 .delay (20000,20000,20000) L_0x17f7f30/d; +v0x17cc640_0 .net "S", 0 0, L_0x17f80c0; 1 drivers +v0x17cc6e0_0 .alias "in0", 0 0, v0x17ccd70_0; +v0x17cc780_0 .alias "in1", 0 0, v0x17cd240_0; +v0x17cc820_0 .net "nS", 0 0, L_0x17f7cb0; 1 drivers +v0x17cc8d0_0 .net "out0", 0 0, L_0x17f7d50; 1 drivers +v0x17cc970_0 .net "out1", 0 0, L_0x17f7e40; 1 drivers +v0x17cca50_0 .alias "outfinal", 0 0, v0x17cce20_0; +S_0x17cb150 .scope generate, "addbits[2]" "addbits[2]" 2 234, 2 234, S_0x17c9d40; + .timescale -9 -12; +P_0x17caa48 .param/l "i" 2 234, +C4<010>; +S_0x17cb2c0 .scope module, "attempt" "MiddleAddSubSLT" 2 236, 2 95, S_0x17cb150; + .timescale -9 -12; +L_0x17f8f40/d .functor NOT 1, L_0x17fa240, C4<0>, C4<0>, C4<0>; +L_0x17f8f40 .delay (10000,10000,10000) L_0x17f8f40/d; +L_0x17f9580/d .functor NOT 1, L_0x17f9620, C4<0>, C4<0>, C4<0>; +L_0x17f9580 .delay (10000,10000,10000) L_0x17f9580/d; +L_0x17f96c0/d .functor AND 1, L_0x17f9800, L_0x17f9580, C4<1>, C4<1>; +L_0x17f96c0 .delay (20000,20000,20000) L_0x17f96c0/d; +L_0x17f98a0/d .functor XOR 1, L_0x17fa140, L_0x17f9350, C4<0>, C4<0>; +L_0x17f98a0 .delay (40000,40000,40000) L_0x17f98a0/d; +L_0x17f9990/d .functor XOR 1, L_0x17f98a0, L_0x17fa370, C4<0>, C4<0>; +L_0x17f9990 .delay (40000,40000,40000) L_0x17f9990/d; +L_0x17f9a80/d .functor AND 1, L_0x17fa140, L_0x17f9350, C4<1>, C4<1>; +L_0x17f9a80 .delay (20000,20000,20000) L_0x17f9a80/d; +L_0x17f9bf0/d .functor AND 1, L_0x17f98a0, L_0x17fa370, C4<1>, C4<1>; +L_0x17f9bf0 .delay (20000,20000,20000) L_0x17f9bf0/d; +L_0x17f9ce0/d .functor OR 1, L_0x17f9a80, L_0x17f9bf0, C4<0>, C4<0>; +L_0x17f9ce0 .delay (20000,20000,20000) L_0x17f9ce0/d; +v0x17cb950_0 .net "A", 0 0, L_0x17fa140; 1 drivers +v0x17cba10_0 .net "AandB", 0 0, L_0x17f9a80; 1 drivers +v0x17cbab0_0 .net "AddSubSLTSum", 0 0, L_0x17f9990; 1 drivers +v0x17cbb50_0 .net "AxorB", 0 0, L_0x17f98a0; 1 drivers +v0x17cbbd0_0 .net "B", 0 0, L_0x17fa240; 1 drivers +v0x17cbc80_0 .net "BornB", 0 0, L_0x17f9350; 1 drivers +v0x17cbd40_0 .net "CINandAxorB", 0 0, L_0x17f9bf0; 1 drivers +v0x17cbdc0_0 .alias "Command", 2 0, v0x17dc9d0_0; +v0x17cbe40_0 .net *"_s3", 0 0, L_0x17f9620; 1 drivers +v0x17cbec0_0 .net *"_s5", 0 0, L_0x17f9800; 1 drivers +v0x17cbf60_0 .net "carryin", 0 0, L_0x17fa370; 1 drivers +v0x17cc000_0 .net "carryout", 0 0, L_0x17f9ce0; 1 drivers +v0x17cc0a0_0 .net "nB", 0 0, L_0x17f8f40; 1 drivers +v0x17cc150_0 .net "nCmd2", 0 0, L_0x17f9580; 1 drivers +v0x17cc250_0 .net "subtract", 0 0, L_0x17f96c0; 1 drivers +L_0x17f94e0 .part v0x17dda90_0, 0, 1; +L_0x17f9620 .part v0x17dda90_0, 2, 1; +L_0x17f9800 .part v0x17dda90_0, 0, 1; +S_0x17cb3b0 .scope module, "mux0" "TwoInMux" 2 111, 2 8, S_0x17cb2c0; + .timescale -9 -12; +L_0x17f90d0/d .functor NOT 1, L_0x17f94e0, C4<0>, C4<0>, C4<0>; +L_0x17f90d0 .delay (10000,10000,10000) L_0x17f90d0/d; +L_0x17f9170/d .functor AND 1, L_0x17fa240, L_0x17f90d0, C4<1>, C4<1>; +L_0x17f9170 .delay (20000,20000,20000) L_0x17f9170/d; +L_0x17f9260/d .functor AND 1, L_0x17f8f40, L_0x17f94e0, C4<1>, C4<1>; +L_0x17f9260 .delay (20000,20000,20000) L_0x17f9260/d; +L_0x17f9350/d .functor OR 1, L_0x17f9170, L_0x17f9260, C4<0>, C4<0>; +L_0x17f9350 .delay (20000,20000,20000) L_0x17f9350/d; +v0x17cb4a0_0 .net "S", 0 0, L_0x17f94e0; 1 drivers +v0x17cb540_0 .alias "in0", 0 0, v0x17cbbd0_0; +v0x17cb5e0_0 .alias "in1", 0 0, v0x17cc0a0_0; +v0x17cb680_0 .net "nS", 0 0, L_0x17f90d0; 1 drivers +v0x17cb730_0 .net "out0", 0 0, L_0x17f9170; 1 drivers +v0x17cb7d0_0 .net "out1", 0 0, L_0x17f9260; 1 drivers +v0x17cb8b0_0 .alias "outfinal", 0 0, v0x17cbc80_0; +S_0x17c9eb0 .scope generate, "addbits[3]" "addbits[3]" 2 234, 2 234, S_0x17c9d40; + .timescale -9 -12; +P_0x17c9fa8 .param/l "i" 2 234, +C4<011>; +S_0x17ca020 .scope module, "attempt" "MiddleAddSubSLT" 2 236, 2 95, S_0x17c9eb0; + .timescale -9 -12; +L_0x17fa1e0/d .functor NOT 1, L_0x17fb6a0, C4<0>, C4<0>, C4<0>; +L_0x17fa1e0 .delay (10000,10000,10000) L_0x17fa1e0/d; +L_0x17fa980/d .functor NOT 1, L_0x17faa20, C4<0>, C4<0>, C4<0>; +L_0x17fa980 .delay (10000,10000,10000) L_0x17fa980/d; +L_0x17faac0/d .functor AND 1, L_0x17fac00, L_0x17fa980, C4<1>, C4<1>; +L_0x17faac0 .delay (20000,20000,20000) L_0x17faac0/d; +L_0x17faca0/d .functor XOR 1, L_0x17fb570, L_0x17fa750, C4<0>, C4<0>; +L_0x17faca0 .delay (40000,40000,40000) L_0x17faca0/d; +L_0x17fad90/d .functor XOR 1, L_0x17faca0, L_0x17fb7d0, C4<0>, C4<0>; +L_0x17fad90 .delay (40000,40000,40000) L_0x17fad90/d; +L_0x17fae80/d .functor AND 1, L_0x17fb570, L_0x17fa750, C4<1>, C4<1>; +L_0x17fae80 .delay (20000,20000,20000) L_0x17fae80/d; +L_0x17faff0/d .functor AND 1, L_0x17faca0, L_0x17fb7d0, C4<1>, C4<1>; +L_0x17faff0 .delay (20000,20000,20000) L_0x17faff0/d; +L_0x17fb0e0/d .functor OR 1, L_0x17fae80, L_0x17faff0, C4<0>, C4<0>; +L_0x17fb0e0 .delay (20000,20000,20000) L_0x17fb0e0/d; +v0x17ca690_0 .net "A", 0 0, L_0x17fb570; 1 drivers +v0x17ca750_0 .net "AandB", 0 0, L_0x17fae80; 1 drivers +v0x17ca7f0_0 .net "AddSubSLTSum", 0 0, L_0x17fad90; 1 drivers +v0x17ca890_0 .net "AxorB", 0 0, L_0x17faca0; 1 drivers +v0x17ca910_0 .net "B", 0 0, L_0x17fb6a0; 1 drivers +v0x17ca9c0_0 .net "BornB", 0 0, L_0x17fa750; 1 drivers +v0x17caa80_0 .net "CINandAxorB", 0 0, L_0x17faff0; 1 drivers +v0x17cab00_0 .alias "Command", 2 0, v0x17dc9d0_0; +v0x17cabd0_0 .net *"_s3", 0 0, L_0x17faa20; 1 drivers +v0x17cac50_0 .net *"_s5", 0 0, L_0x17fac00; 1 drivers +v0x17cad50_0 .net "carryin", 0 0, L_0x17fb7d0; 1 drivers +v0x17cadf0_0 .net "carryout", 0 0, L_0x17fb0e0; 1 drivers +v0x17caf00_0 .net "nB", 0 0, L_0x17fa1e0; 1 drivers +v0x17cafb0_0 .net "nCmd2", 0 0, L_0x17fa980; 1 drivers +v0x17cb0b0_0 .net "subtract", 0 0, L_0x17faac0; 1 drivers +L_0x17fa8e0 .part v0x17dda90_0, 0, 1; +L_0x17faa20 .part v0x17dda90_0, 2, 1; +L_0x17fac00 .part v0x17dda90_0, 0, 1; +S_0x17ca110 .scope module, "mux0" "TwoInMux" 2 111, 2 8, S_0x17ca020; + .timescale -9 -12; +L_0x17fa510/d .functor NOT 1, L_0x17fa8e0, C4<0>, C4<0>, C4<0>; +L_0x17fa510 .delay (10000,10000,10000) L_0x17fa510/d; +L_0x17fa570/d .functor AND 1, L_0x17fb6a0, L_0x17fa510, C4<1>, C4<1>; +L_0x17fa570 .delay (20000,20000,20000) L_0x17fa570/d; +L_0x17fa660/d .functor AND 1, L_0x17fa1e0, L_0x17fa8e0, C4<1>, C4<1>; +L_0x17fa660 .delay (20000,20000,20000) L_0x17fa660/d; +L_0x17fa750/d .functor OR 1, L_0x17fa570, L_0x17fa660, C4<0>, C4<0>; +L_0x17fa750 .delay (20000,20000,20000) L_0x17fa750/d; +v0x17ca200_0 .net "S", 0 0, L_0x17fa8e0; 1 drivers +v0x17ca280_0 .alias "in0", 0 0, v0x17ca910_0; +v0x17ca320_0 .alias "in1", 0 0, v0x17caf00_0; +v0x17ca3c0_0 .net "nS", 0 0, L_0x17fa510; 1 drivers +v0x17ca470_0 .net "out0", 0 0, L_0x17fa570; 1 drivers +v0x17ca510_0 .net "out1", 0 0, L_0x17fa660; 1 drivers +v0x17ca5f0_0 .alias "outfinal", 0 0, v0x17ca9c0_0; +S_0x17c6b90 .scope module, "trial1" "AndNand32" 2 283, 2 157, S_0x17bb1b0; + .timescale -9 -12; +P_0x17c6618 .param/l "size" 2 165, +C4<0100>; +v0x17c6a80_0 .alias "A", 3 0, v0x17dc7b0_0; +v0x17c9b60_0 .alias "AndNandOut", 3 0, v0x17dd990_0; +v0x17c9be0_0 .alias "B", 3 0, v0x17dc8d0_0; +v0x17c9c90_0 .alias "Command", 2 0, v0x17dc9d0_0; +L_0x17fe630 .part/pv L_0x17fe3c0, 1, 1, 4; +L_0x17fe6f0 .part v0x17dd890_0, 1, 1; +L_0x17fe790 .part v0x17dda10_0, 1, 1; +L_0x17ff0a0 .part/pv L_0x17fee30, 2, 1, 4; +L_0x17ff140 .part v0x17dd890_0, 2, 1; +L_0x17ff1e0 .part v0x17dda10_0, 2, 1; +L_0x17ffb10 .part/pv L_0x17ff8a0, 3, 1, 4; +L_0x17f1ef0 .part v0x17dd890_0, 3, 1; +L_0x17ffdc0 .part v0x17dda10_0, 3, 1; +L_0x1800670 .part/pv L_0x1800400, 0, 1, 4; +L_0x1800770 .part v0x17dd890_0, 0, 1; +L_0x1800810 .part v0x17dda10_0, 0, 1; +S_0x17c9020 .scope module, "attempt2" "AndNand" 2 170, 2 53, S_0x17c6b90; + .timescale -9 -12; +L_0x17ffeb0/d .functor NAND 1, L_0x1800770, L_0x1800810, C4<1>, C4<1>; +L_0x17ffeb0 .delay (10000,10000,10000) L_0x17ffeb0/d; +L_0x17fffb0/d .functor NOT 1, L_0x17ffeb0, C4<0>, C4<0>, C4<0>; +L_0x17fffb0 .delay (10000,10000,10000) L_0x17fffb0/d; +v0x17c9640_0 .net "A", 0 0, L_0x1800770; 1 drivers +v0x17c9700_0 .net "AandB", 0 0, L_0x17fffb0; 1 drivers +v0x17c9780_0 .net "AnandB", 0 0, L_0x17ffeb0; 1 drivers +v0x17c9830_0 .net "AndNandOut", 0 0, L_0x1800400; 1 drivers +v0x17c9910_0 .net "B", 0 0, L_0x1800810; 1 drivers +v0x17c9990_0 .alias "Command", 2 0, v0x17dc9d0_0; +L_0x18005d0 .part v0x17dda90_0, 0, 1; +S_0x17c9110 .scope module, "potato" "TwoInMux" 2 66, 2 8, S_0x17c9020; + .timescale -9 -12; +L_0x18000e0/d .functor NOT 1, L_0x18005d0, C4<0>, C4<0>, C4<0>; +L_0x18000e0 .delay (10000,10000,10000) L_0x18000e0/d; +L_0x18001a0/d .functor AND 1, L_0x17fffb0, L_0x18000e0, C4<1>, C4<1>; +L_0x18001a0 .delay (20000,20000,20000) L_0x18001a0/d; +L_0x18002b0/d .functor AND 1, L_0x17ffeb0, L_0x18005d0, C4<1>, C4<1>; +L_0x18002b0 .delay (20000,20000,20000) L_0x18002b0/d; +L_0x1800400/d .functor OR 1, L_0x18001a0, L_0x18002b0, C4<0>, C4<0>; +L_0x1800400 .delay (20000,20000,20000) L_0x1800400/d; +v0x17c9200_0 .net "S", 0 0, L_0x18005d0; 1 drivers +v0x17c9280_0 .alias "in0", 0 0, v0x17c9700_0; +v0x17c9300_0 .alias "in1", 0 0, v0x17c9780_0; +v0x17c93a0_0 .net "nS", 0 0, L_0x18000e0; 1 drivers +v0x17c9420_0 .net "out0", 0 0, L_0x18001a0; 1 drivers +v0x17c94c0_0 .net "out1", 0 0, L_0x18002b0; 1 drivers +v0x17c95a0_0 .alias "outfinal", 0 0, v0x17c9830_0; +S_0x17c8450 .scope generate, "andbits[1]" "andbits[1]" 2 173, 2 173, S_0x17c6b90; + .timescale -9 -12; +P_0x17c8548 .param/l "i" 2 173, +C4<01>; +S_0x17c85e0 .scope module, "attempt" "AndNand" 2 175, 2 53, S_0x17c8450; + .timescale -9 -12; +L_0x17fdeb0/d .functor NAND 1, L_0x17fe6f0, L_0x17fe790, C4<1>, C4<1>; +L_0x17fdeb0 .delay (10000,10000,10000) L_0x17fdeb0/d; +L_0x17fdf70/d .functor NOT 1, L_0x17fdeb0, C4<0>, C4<0>, C4<0>; +L_0x17fdf70 .delay (10000,10000,10000) L_0x17fdf70/d; +v0x17c8c40_0 .net "A", 0 0, L_0x17fe6f0; 1 drivers +v0x17c8d00_0 .net "AandB", 0 0, L_0x17fdf70; 1 drivers +v0x17c8d80_0 .net "AnandB", 0 0, L_0x17fdeb0; 1 drivers +v0x17c8e00_0 .net "AndNandOut", 0 0, L_0x17fe3c0; 1 drivers +v0x17c8ee0_0 .net "B", 0 0, L_0x17fe790; 1 drivers +v0x17c8f60_0 .alias "Command", 2 0, v0x17dc9d0_0; +L_0x17fe590 .part v0x17dda90_0, 0, 1; +S_0x17c86d0 .scope module, "potato" "TwoInMux" 2 66, 2 8, S_0x17c85e0; + .timescale -9 -12; +L_0x17fe0a0/d .functor NOT 1, L_0x17fe590, C4<0>, C4<0>, C4<0>; +L_0x17fe0a0 .delay (10000,10000,10000) L_0x17fe0a0/d; +L_0x17fe160/d .functor AND 1, L_0x17fdf70, L_0x17fe0a0, C4<1>, C4<1>; +L_0x17fe160 .delay (20000,20000,20000) L_0x17fe160/d; +L_0x17fe270/d .functor AND 1, L_0x17fdeb0, L_0x17fe590, C4<1>, C4<1>; +L_0x17fe270 .delay (20000,20000,20000) L_0x17fe270/d; +L_0x17fe3c0/d .functor OR 1, L_0x17fe160, L_0x17fe270, C4<0>, C4<0>; +L_0x17fe3c0 .delay (20000,20000,20000) L_0x17fe3c0/d; +v0x17c87c0_0 .net "S", 0 0, L_0x17fe590; 1 drivers +v0x17c8860_0 .alias "in0", 0 0, v0x17c8d00_0; +v0x17c8900_0 .alias "in1", 0 0, v0x17c8d80_0; +v0x17c89a0_0 .net "nS", 0 0, L_0x17fe0a0; 1 drivers +v0x17c8a20_0 .net "out0", 0 0, L_0x17fe160; 1 drivers +v0x17c8ac0_0 .net "out1", 0 0, L_0x17fe270; 1 drivers +v0x17c8ba0_0 .alias "outfinal", 0 0, v0x17c8e00_0; +S_0x17c7930 .scope generate, "andbits[2]" "andbits[2]" 2 173, 2 173, S_0x17c6b90; + .timescale -9 -12; +P_0x17c7a28 .param/l "i" 2 173, +C4<010>; +S_0x17c7aa0 .scope module, "attempt" "AndNand" 2 175, 2 53, S_0x17c7930; + .timescale -9 -12; +L_0x17fe880/d .functor NAND 1, L_0x17ff140, L_0x17ff1e0, C4<1>, C4<1>; +L_0x17fe880 .delay (10000,10000,10000) L_0x17fe880/d; +L_0x17fe9e0/d .functor NOT 1, L_0x17fe880, C4<0>, C4<0>, C4<0>; +L_0x17fe9e0 .delay (10000,10000,10000) L_0x17fe9e0/d; +v0x17c8060_0 .net "A", 0 0, L_0x17ff140; 1 drivers +v0x17c8100_0 .net "AandB", 0 0, L_0x17fe9e0; 1 drivers +v0x17c81b0_0 .net "AnandB", 0 0, L_0x17fe880; 1 drivers +v0x17c8260_0 .net "AndNandOut", 0 0, L_0x17fee30; 1 drivers +v0x17c8310_0 .net "B", 0 0, L_0x17ff1e0; 1 drivers +v0x17c8390_0 .alias "Command", 2 0, v0x17dc9d0_0; +L_0x17ff000 .part v0x17dda90_0, 0, 1; +S_0x17c7b90 .scope module, "potato" "TwoInMux" 2 66, 2 8, S_0x17c7aa0; + .timescale -9 -12; +L_0x17feb10/d .functor NOT 1, L_0x17ff000, C4<0>, C4<0>, C4<0>; +L_0x17feb10 .delay (10000,10000,10000) L_0x17feb10/d; +L_0x17febd0/d .functor AND 1, L_0x17fe9e0, L_0x17feb10, C4<1>, C4<1>; +L_0x17febd0 .delay (20000,20000,20000) L_0x17febd0/d; +L_0x17fece0/d .functor AND 1, L_0x17fe880, L_0x17ff000, C4<1>, C4<1>; +L_0x17fece0 .delay (20000,20000,20000) L_0x17fece0/d; +L_0x17fee30/d .functor OR 1, L_0x17febd0, L_0x17fece0, C4<0>, C4<0>; +L_0x17fee30 .delay (20000,20000,20000) L_0x17fee30/d; +v0x17c7c80_0 .net "S", 0 0, L_0x17ff000; 1 drivers +v0x17c7d00_0 .alias "in0", 0 0, v0x17c8100_0; +v0x17c7da0_0 .alias "in1", 0 0, v0x17c81b0_0; +v0x17c7e40_0 .net "nS", 0 0, L_0x17feb10; 1 drivers +v0x17c7ec0_0 .net "out0", 0 0, L_0x17febd0; 1 drivers +v0x17c7f60_0 .net "out1", 0 0, L_0x17fece0; 1 drivers +v0x17c7fe0_0 .alias "outfinal", 0 0, v0x17c8260_0; +S_0x17c6d00 .scope generate, "andbits[3]" "andbits[3]" 2 173, 2 173, S_0x17c6b90; + .timescale -9 -12; +P_0x17c6df8 .param/l "i" 2 173, +C4<011>; +S_0x17c6e90 .scope module, "attempt" "AndNand" 2 175, 2 53, S_0x17c6d00; + .timescale -9 -12; +L_0x17ff310/d .functor NAND 1, L_0x17f1ef0, L_0x17ffdc0, C4<1>, C4<1>; +L_0x17ff310 .delay (10000,10000,10000) L_0x17ff310/d; +L_0x17ff450/d .functor NOT 1, L_0x17ff310, C4<0>, C4<0>, C4<0>; +L_0x17ff450 .delay (10000,10000,10000) L_0x17ff450/d; +v0x17c7520_0 .net "A", 0 0, L_0x17f1ef0; 1 drivers +v0x17c75e0_0 .net "AandB", 0 0, L_0x17ff450; 1 drivers +v0x17c7660_0 .net "AnandB", 0 0, L_0x17ff310; 1 drivers +v0x17c7710_0 .net "AndNandOut", 0 0, L_0x17ff8a0; 1 drivers +v0x17c77f0_0 .net "B", 0 0, L_0x17ffdc0; 1 drivers +v0x17c7870_0 .alias "Command", 2 0, v0x17dc9d0_0; +L_0x17ffa70 .part v0x17dda90_0, 0, 1; +S_0x17c6f80 .scope module, "potato" "TwoInMux" 2 66, 2 8, S_0x17c6e90; + .timescale -9 -12; +L_0x17ff580/d .functor NOT 1, L_0x17ffa70, C4<0>, C4<0>, C4<0>; +L_0x17ff580 .delay (10000,10000,10000) L_0x17ff580/d; +L_0x17ff640/d .functor AND 1, L_0x17ff450, L_0x17ff580, C4<1>, C4<1>; +L_0x17ff640 .delay (20000,20000,20000) L_0x17ff640/d; +L_0x17ff750/d .functor AND 1, L_0x17ff310, L_0x17ffa70, C4<1>, C4<1>; +L_0x17ff750 .delay (20000,20000,20000) L_0x17ff750/d; +L_0x17ff8a0/d .functor OR 1, L_0x17ff640, L_0x17ff750, C4<0>, C4<0>; +L_0x17ff8a0 .delay (20000,20000,20000) L_0x17ff8a0/d; +v0x17c7070_0 .net "S", 0 0, L_0x17ffa70; 1 drivers +v0x17c7110_0 .alias "in0", 0 0, v0x17c75e0_0; +v0x17c71b0_0 .alias "in1", 0 0, v0x17c7660_0; +v0x17c7250_0 .net "nS", 0 0, L_0x17ff580; 1 drivers +v0x17c7300_0 .net "out0", 0 0, L_0x17ff640; 1 drivers +v0x17c73a0_0 .net "out1", 0 0, L_0x17ff750; 1 drivers +v0x17c7480_0 .alias "outfinal", 0 0, v0x17c7710_0; +S_0x17c19c0 .scope module, "trial2" "OrNorXor32" 2 284, 2 180, S_0x17bb1b0; + .timescale -9 -12; +P_0x17c0b18 .param/l "size" 2 187, +C4<0100>; +v0x17c6900_0 .alias "A", 3 0, v0x17dc7b0_0; +v0x17c6980_0 .alias "B", 3 0, v0x17dc8d0_0; +v0x17c6a00_0 .alias "Command", 2 0, v0x17dc9d0_0; +v0x17c6b10_0 .alias "OrNorXorOut", 3 0, v0x17ddb90_0; +L_0x18019c0 .part/pv L_0x1801750, 1, 1, 4; +L_0x1801a60 .part v0x17dd890_0, 1, 1; +L_0x1801b00 .part v0x17dda10_0, 1, 1; +L_0x1802cc0 .part/pv L_0x1802a50, 2, 1, 4; +L_0x1802d60 .part v0x17dd890_0, 2, 1; +L_0x1802e00 .part v0x17dda10_0, 2, 1; +L_0x1803fc0 .part/pv L_0x1803d50, 3, 1, 4; +L_0x1804060 .part v0x17dd890_0, 3, 1; +L_0x1804100 .part v0x17dda10_0, 3, 1; +L_0x18052b0 .part/pv L_0x1805040, 0, 1, 4; +L_0x18053b0 .part v0x17dd890_0, 0, 1; +L_0x1805450 .part v0x17dda10_0, 0, 1; +S_0x17c56f0 .scope module, "attempt2" "OrNorXor" 2 195, 2 70, S_0x17c19c0; + .timescale -9 -12; +L_0x18041a0/d .functor NOR 1, L_0x18053b0, L_0x1805450, C4<0>, C4<0>; +L_0x18041a0 .delay (10000,10000,10000) L_0x18041a0/d; +L_0x18042a0/d .functor NOT 1, L_0x18041a0, C4<0>, C4<0>, C4<0>; +L_0x18042a0 .delay (10000,10000,10000) L_0x18042a0/d; +L_0x18043d0/d .functor NAND 1, L_0x18053b0, L_0x1805450, C4<1>, C4<1>; +L_0x18043d0 .delay (10000,10000,10000) L_0x18043d0/d; +L_0x1804530/d .functor NAND 1, L_0x18043d0, L_0x18042a0, C4<1>, C4<1>; +L_0x1804530 .delay (10000,10000,10000) L_0x1804530/d; +L_0x1804640/d .functor NOT 1, L_0x1804530, C4<0>, C4<0>, C4<0>; +L_0x1804640 .delay (10000,10000,10000) L_0x1804640/d; +v0x17c6240_0 .net "A", 0 0, L_0x18053b0; 1 drivers +v0x17c62e0_0 .net "AnandB", 0 0, L_0x18043d0; 1 drivers +v0x17c6380_0 .net "AnorB", 0 0, L_0x18041a0; 1 drivers +v0x17c6400_0 .net "AorB", 0 0, L_0x18042a0; 1 drivers +v0x17c64e0_0 .net "AxorB", 0 0, L_0x1804640; 1 drivers +v0x17c6590_0 .net "B", 0 0, L_0x1805450; 1 drivers +v0x17c6650_0 .alias "Command", 2 0, v0x17dc9d0_0; +v0x17c66d0_0 .net "OrNorXorOut", 0 0, L_0x1805040; 1 drivers +v0x17c6750_0 .net "XorNor", 0 0, L_0x1804ac0; 1 drivers +v0x17c6820_0 .net "nXor", 0 0, L_0x1804530; 1 drivers +L_0x1804c40 .part v0x17dda90_0, 2, 1; +L_0x1805210 .part v0x17dda90_0, 0, 1; +S_0x17c5cd0 .scope module, "mux0" "TwoInMux" 2 89, 2 8, S_0x17c56f0; + .timescale -9 -12; +L_0x18047a0/d .functor NOT 1, L_0x1804c40, C4<0>, C4<0>, C4<0>; +L_0x18047a0 .delay (10000,10000,10000) L_0x18047a0/d; +L_0x1804860/d .functor AND 1, L_0x1804640, L_0x18047a0, C4<1>, C4<1>; +L_0x1804860 .delay (20000,20000,20000) L_0x1804860/d; +L_0x1804970/d .functor AND 1, L_0x18041a0, L_0x1804c40, C4<1>, C4<1>; +L_0x1804970 .delay (20000,20000,20000) L_0x1804970/d; +L_0x1804ac0/d .functor OR 1, L_0x1804860, L_0x1804970, C4<0>, C4<0>; +L_0x1804ac0 .delay (20000,20000,20000) L_0x1804ac0/d; +v0x17c5dc0_0 .net "S", 0 0, L_0x1804c40; 1 drivers +v0x17c5e80_0 .alias "in0", 0 0, v0x17c64e0_0; +v0x17c5f20_0 .alias "in1", 0 0, v0x17c6380_0; +v0x17c5fc0_0 .net "nS", 0 0, L_0x18047a0; 1 drivers +v0x17c6040_0 .net "out0", 0 0, L_0x1804860; 1 drivers +v0x17c60e0_0 .net "out1", 0 0, L_0x1804970; 1 drivers +v0x17c61c0_0 .alias "outfinal", 0 0, v0x17c6750_0; +S_0x17c57e0 .scope module, "mux1" "TwoInMux" 2 90, 2 8, S_0x17c56f0; + .timescale -9 -12; +L_0x1804ce0/d .functor NOT 1, L_0x1805210, C4<0>, C4<0>, C4<0>; +L_0x1804ce0 .delay (10000,10000,10000) L_0x1804ce0/d; +L_0x1804da0/d .functor AND 1, L_0x1804ac0, L_0x1804ce0, C4<1>, C4<1>; +L_0x1804da0 .delay (20000,20000,20000) L_0x1804da0/d; +L_0x1804ef0/d .functor AND 1, L_0x18042a0, L_0x1805210, C4<1>, C4<1>; +L_0x1804ef0 .delay (20000,20000,20000) L_0x1804ef0/d; +L_0x1805040/d .functor OR 1, L_0x1804da0, L_0x1804ef0, C4<0>, C4<0>; +L_0x1805040 .delay (20000,20000,20000) L_0x1805040/d; +v0x17c58d0_0 .net "S", 0 0, L_0x1805210; 1 drivers +v0x17c5950_0 .alias "in0", 0 0, v0x17c6750_0; +v0x17c59d0_0 .alias "in1", 0 0, v0x17c6400_0; +v0x17c5a70_0 .net "nS", 0 0, L_0x1804ce0; 1 drivers +v0x17c5af0_0 .net "out0", 0 0, L_0x1804da0; 1 drivers +v0x17c5b90_0 .net "out1", 0 0, L_0x1804ef0; 1 drivers +v0x17c5c30_0 .alias "outfinal", 0 0, v0x17c66d0_0; +S_0x17c42f0 .scope generate, "orbits[1]" "orbits[1]" 2 199, 2 199, S_0x17c19c0; + .timescale -9 -12; +P_0x17c3fd8 .param/l "i" 2 199, +C4<01>; +S_0x17c4420 .scope module, "attempt" "OrNorXor" 2 201, 2 70, S_0x17c42f0; + .timescale -9 -12; +L_0x1800710/d .functor NOR 1, L_0x1801a60, L_0x1801b00, C4<0>, C4<0>; +L_0x1800710 .delay (10000,10000,10000) L_0x1800710/d; +L_0x18009b0/d .functor NOT 1, L_0x1800710, C4<0>, C4<0>, C4<0>; +L_0x18009b0 .delay (10000,10000,10000) L_0x18009b0/d; +L_0x1800ae0/d .functor NAND 1, L_0x1801a60, L_0x1801b00, C4<1>, C4<1>; +L_0x1800ae0 .delay (10000,10000,10000) L_0x1800ae0/d; +L_0x1800c40/d .functor NAND 1, L_0x1800ae0, L_0x18009b0, C4<1>, C4<1>; +L_0x1800c40 .delay (10000,10000,10000) L_0x1800c40/d; +L_0x1800d50/d .functor NOT 1, L_0x1800c40, C4<0>, C4<0>, C4<0>; +L_0x1800d50 .delay (10000,10000,10000) L_0x1800d50/d; +v0x17c4fb0_0 .net "A", 0 0, L_0x1801a60; 1 drivers +v0x17c5050_0 .net "AnandB", 0 0, L_0x1800ae0; 1 drivers +v0x17c50f0_0 .net "AnorB", 0 0, L_0x1800710; 1 drivers +v0x17c51a0_0 .net "AorB", 0 0, L_0x18009b0; 1 drivers +v0x17c5280_0 .net "AxorB", 0 0, L_0x1800d50; 1 drivers +v0x17c5330_0 .net "B", 0 0, L_0x1801b00; 1 drivers +v0x17c53f0_0 .alias "Command", 2 0, v0x17dc9d0_0; +v0x17c5470_0 .net "OrNorXorOut", 0 0, L_0x1801750; 1 drivers +v0x17c5540_0 .net "XorNor", 0 0, L_0x18011d0; 1 drivers +v0x17c5610_0 .net "nXor", 0 0, L_0x1800c40; 1 drivers +L_0x1801350 .part v0x17dda90_0, 2, 1; +L_0x1801920 .part v0x17dda90_0, 0, 1; +S_0x17c4a40 .scope module, "mux0" "TwoInMux" 2 89, 2 8, S_0x17c4420; + .timescale -9 -12; +L_0x1800eb0/d .functor NOT 1, L_0x1801350, C4<0>, C4<0>, C4<0>; +L_0x1800eb0 .delay (10000,10000,10000) L_0x1800eb0/d; +L_0x1800f70/d .functor AND 1, L_0x1800d50, L_0x1800eb0, C4<1>, C4<1>; +L_0x1800f70 .delay (20000,20000,20000) L_0x1800f70/d; +L_0x1801080/d .functor AND 1, L_0x1800710, L_0x1801350, C4<1>, C4<1>; +L_0x1801080 .delay (20000,20000,20000) L_0x1801080/d; +L_0x18011d0/d .functor OR 1, L_0x1800f70, L_0x1801080, C4<0>, C4<0>; +L_0x18011d0 .delay (20000,20000,20000) L_0x18011d0/d; +v0x17c4b30_0 .net "S", 0 0, L_0x1801350; 1 drivers +v0x17c4bf0_0 .alias "in0", 0 0, v0x17c5280_0; +v0x17c4c90_0 .alias "in1", 0 0, v0x17c50f0_0; +v0x17c4d30_0 .net "nS", 0 0, L_0x1800eb0; 1 drivers +v0x17c4db0_0 .net "out0", 0 0, L_0x1800f70; 1 drivers +v0x17c4e50_0 .net "out1", 0 0, L_0x1801080; 1 drivers +v0x17c4f30_0 .alias "outfinal", 0 0, v0x17c5540_0; +S_0x17c4510 .scope module, "mux1" "TwoInMux" 2 90, 2 8, S_0x17c4420; + .timescale -9 -12; +L_0x18013f0/d .functor NOT 1, L_0x1801920, C4<0>, C4<0>, C4<0>; +L_0x18013f0 .delay (10000,10000,10000) L_0x18013f0/d; +L_0x18014b0/d .functor AND 1, L_0x18011d0, L_0x18013f0, C4<1>, C4<1>; +L_0x18014b0 .delay (20000,20000,20000) L_0x18014b0/d; +L_0x1801600/d .functor AND 1, L_0x18009b0, L_0x1801920, C4<1>, C4<1>; +L_0x1801600 .delay (20000,20000,20000) L_0x1801600/d; +L_0x1801750/d .functor OR 1, L_0x18014b0, L_0x1801600, C4<0>, C4<0>; +L_0x1801750 .delay (20000,20000,20000) L_0x1801750/d; +v0x17c4600_0 .net "S", 0 0, L_0x1801920; 1 drivers +v0x17c4680_0 .alias "in0", 0 0, v0x17c5540_0; +v0x17c4700_0 .alias "in1", 0 0, v0x17c51a0_0; +v0x17c47a0_0 .net "nS", 0 0, L_0x18013f0; 1 drivers +v0x17c4820_0 .net "out0", 0 0, L_0x18014b0; 1 drivers +v0x17c48c0_0 .net "out1", 0 0, L_0x1801600; 1 drivers +v0x17c49a0_0 .alias "outfinal", 0 0, v0x17c5470_0; +S_0x17c2ed0 .scope generate, "orbits[2]" "orbits[2]" 2 199, 2 199, S_0x17c19c0; + .timescale -9 -12; +P_0x17c2c98 .param/l "i" 2 199, +C4<010>; +S_0x17c3000 .scope module, "attempt" "OrNorXor" 2 201, 2 70, S_0x17c2ed0; + .timescale -9 -12; +L_0x1801ba0/d .functor NOR 1, L_0x1802d60, L_0x1802e00, C4<0>, C4<0>; +L_0x1801ba0 .delay (10000,10000,10000) L_0x1801ba0/d; +L_0x1801cb0/d .functor NOT 1, L_0x1801ba0, C4<0>, C4<0>, C4<0>; +L_0x1801cb0 .delay (10000,10000,10000) L_0x1801cb0/d; +L_0x1801de0/d .functor NAND 1, L_0x1802d60, L_0x1802e00, C4<1>, C4<1>; +L_0x1801de0 .delay (10000,10000,10000) L_0x1801de0/d; +L_0x1801f40/d .functor NAND 1, L_0x1801de0, L_0x1801cb0, C4<1>, C4<1>; +L_0x1801f40 .delay (10000,10000,10000) L_0x1801f40/d; +L_0x1802050/d .functor NOT 1, L_0x1801f40, C4<0>, C4<0>, C4<0>; +L_0x1802050 .delay (10000,10000,10000) L_0x1802050/d; +v0x17c3bd0_0 .net "A", 0 0, L_0x1802d60; 1 drivers +v0x17c3c70_0 .net "AnandB", 0 0, L_0x1801de0; 1 drivers +v0x17c3d10_0 .net "AnorB", 0 0, L_0x1801ba0; 1 drivers +v0x17c3dc0_0 .net "AorB", 0 0, L_0x1801cb0; 1 drivers +v0x17c3ea0_0 .net "AxorB", 0 0, L_0x1802050; 1 drivers +v0x17c3f50_0 .net "B", 0 0, L_0x1802e00; 1 drivers +v0x17c4010_0 .alias "Command", 2 0, v0x17dc9d0_0; +v0x17c4090_0 .net "OrNorXorOut", 0 0, L_0x1802a50; 1 drivers +v0x17c4140_0 .net "XorNor", 0 0, L_0x18024d0; 1 drivers +v0x17c4210_0 .net "nXor", 0 0, L_0x1801f40; 1 drivers +L_0x1802650 .part v0x17dda90_0, 2, 1; +L_0x1802c20 .part v0x17dda90_0, 0, 1; +S_0x17c3660 .scope module, "mux0" "TwoInMux" 2 89, 2 8, S_0x17c3000; + .timescale -9 -12; +L_0x18021b0/d .functor NOT 1, L_0x1802650, C4<0>, C4<0>, C4<0>; +L_0x18021b0 .delay (10000,10000,10000) L_0x18021b0/d; +L_0x1802270/d .functor AND 1, L_0x1802050, L_0x18021b0, C4<1>, C4<1>; +L_0x1802270 .delay (20000,20000,20000) L_0x1802270/d; +L_0x1802380/d .functor AND 1, L_0x1801ba0, L_0x1802650, C4<1>, C4<1>; +L_0x1802380 .delay (20000,20000,20000) L_0x1802380/d; +L_0x18024d0/d .functor OR 1, L_0x1802270, L_0x1802380, C4<0>, C4<0>; +L_0x18024d0 .delay (20000,20000,20000) L_0x18024d0/d; +v0x17c3750_0 .net "S", 0 0, L_0x1802650; 1 drivers +v0x17c3810_0 .alias "in0", 0 0, v0x17c3ea0_0; +v0x17c38b0_0 .alias "in1", 0 0, v0x17c3d10_0; +v0x17c3950_0 .net "nS", 0 0, L_0x18021b0; 1 drivers +v0x17c39d0_0 .net "out0", 0 0, L_0x1802270; 1 drivers +v0x17c3a70_0 .net "out1", 0 0, L_0x1802380; 1 drivers +v0x17c3b50_0 .alias "outfinal", 0 0, v0x17c4140_0; +S_0x17c30f0 .scope module, "mux1" "TwoInMux" 2 90, 2 8, S_0x17c3000; + .timescale -9 -12; +L_0x18026f0/d .functor NOT 1, L_0x1802c20, C4<0>, C4<0>, C4<0>; +L_0x18026f0 .delay (10000,10000,10000) L_0x18026f0/d; +L_0x18027b0/d .functor AND 1, L_0x18024d0, L_0x18026f0, C4<1>, C4<1>; +L_0x18027b0 .delay (20000,20000,20000) L_0x18027b0/d; +L_0x1802900/d .functor AND 1, L_0x1801cb0, L_0x1802c20, C4<1>, C4<1>; +L_0x1802900 .delay (20000,20000,20000) L_0x1802900/d; +L_0x1802a50/d .functor OR 1, L_0x18027b0, L_0x1802900, C4<0>, C4<0>; +L_0x1802a50 .delay (20000,20000,20000) L_0x1802a50/d; +v0x17c31e0_0 .net "S", 0 0, L_0x1802c20; 1 drivers +v0x17c3280_0 .alias "in0", 0 0, v0x17c4140_0; +v0x17c3320_0 .alias "in1", 0 0, v0x17c3dc0_0; +v0x17c33c0_0 .net "nS", 0 0, L_0x18026f0; 1 drivers +v0x17c3440_0 .net "out0", 0 0, L_0x18027b0; 1 drivers +v0x17c34e0_0 .net "out1", 0 0, L_0x1802900; 1 drivers +v0x17c35c0_0 .alias "outfinal", 0 0, v0x17c4090_0; +S_0x17c1b30 .scope generate, "orbits[3]" "orbits[3]" 2 199, 2 199, S_0x17c19c0; + .timescale -9 -12; +P_0x17c1c28 .param/l "i" 2 199, +C4<011>; +S_0x17c1cc0 .scope module, "attempt" "OrNorXor" 2 201, 2 70, S_0x17c1b30; + .timescale -9 -12; +L_0x1802ee0/d .functor NOR 1, L_0x1804060, L_0x1804100, C4<0>, C4<0>; +L_0x1802ee0 .delay (10000,10000,10000) L_0x1802ee0/d; +L_0x1802fd0/d .functor NOT 1, L_0x1802ee0, C4<0>, C4<0>, C4<0>; +L_0x1802fd0 .delay (10000,10000,10000) L_0x1802fd0/d; +L_0x18030e0/d .functor NAND 1, L_0x1804060, L_0x1804100, C4<1>, C4<1>; +L_0x18030e0 .delay (10000,10000,10000) L_0x18030e0/d; +L_0x1803240/d .functor NAND 1, L_0x18030e0, L_0x1802fd0, C4<1>, C4<1>; +L_0x1803240 .delay (10000,10000,10000) L_0x1803240/d; +L_0x1803350/d .functor NOT 1, L_0x1803240, C4<0>, C4<0>, C4<0>; +L_0x1803350 .delay (10000,10000,10000) L_0x1803350/d; +v0x17c2890_0 .net "A", 0 0, L_0x1804060; 1 drivers +v0x17c2930_0 .net "AnandB", 0 0, L_0x18030e0; 1 drivers +v0x17c29d0_0 .net "AnorB", 0 0, L_0x1802ee0; 1 drivers +v0x17c2a80_0 .net "AorB", 0 0, L_0x1802fd0; 1 drivers +v0x17c2b60_0 .net "AxorB", 0 0, L_0x1803350; 1 drivers +v0x17c2c10_0 .net "B", 0 0, L_0x1804100; 1 drivers +v0x17c2cd0_0 .alias "Command", 2 0, v0x17dc9d0_0; +v0x17c2d50_0 .net "OrNorXorOut", 0 0, L_0x1803d50; 1 drivers +v0x17c2dd0_0 .net "XorNor", 0 0, L_0x18037d0; 1 drivers +v0x17c2e50_0 .net "nXor", 0 0, L_0x1803240; 1 drivers +L_0x1803950 .part v0x17dda90_0, 2, 1; +L_0x1803f20 .part v0x17dda90_0, 0, 1; +S_0x17c2320 .scope module, "mux0" "TwoInMux" 2 89, 2 8, S_0x17c1cc0; + .timescale -9 -12; +L_0x18034b0/d .functor NOT 1, L_0x1803950, C4<0>, C4<0>, C4<0>; +L_0x18034b0 .delay (10000,10000,10000) L_0x18034b0/d; +L_0x1803570/d .functor AND 1, L_0x1803350, L_0x18034b0, C4<1>, C4<1>; +L_0x1803570 .delay (20000,20000,20000) L_0x1803570/d; +L_0x1803680/d .functor AND 1, L_0x1802ee0, L_0x1803950, C4<1>, C4<1>; +L_0x1803680 .delay (20000,20000,20000) L_0x1803680/d; +L_0x18037d0/d .functor OR 1, L_0x1803570, L_0x1803680, C4<0>, C4<0>; +L_0x18037d0 .delay (20000,20000,20000) L_0x18037d0/d; +v0x17c2410_0 .net "S", 0 0, L_0x1803950; 1 drivers +v0x17c24d0_0 .alias "in0", 0 0, v0x17c2b60_0; +v0x17c2570_0 .alias "in1", 0 0, v0x17c29d0_0; +v0x17c2610_0 .net "nS", 0 0, L_0x18034b0; 1 drivers +v0x17c2690_0 .net "out0", 0 0, L_0x1803570; 1 drivers +v0x17c2730_0 .net "out1", 0 0, L_0x1803680; 1 drivers +v0x17c2810_0 .alias "outfinal", 0 0, v0x17c2dd0_0; +S_0x17c1db0 .scope module, "mux1" "TwoInMux" 2 90, 2 8, S_0x17c1cc0; + .timescale -9 -12; +L_0x18039f0/d .functor NOT 1, L_0x1803f20, C4<0>, C4<0>, C4<0>; +L_0x18039f0 .delay (10000,10000,10000) L_0x18039f0/d; +L_0x1803ab0/d .functor AND 1, L_0x18037d0, L_0x18039f0, C4<1>, C4<1>; +L_0x1803ab0 .delay (20000,20000,20000) L_0x1803ab0/d; +L_0x1803c00/d .functor AND 1, L_0x1802fd0, L_0x1803f20, C4<1>, C4<1>; +L_0x1803c00 .delay (20000,20000,20000) L_0x1803c00/d; +L_0x1803d50/d .functor OR 1, L_0x1803ab0, L_0x1803c00, C4<0>, C4<0>; +L_0x1803d50 .delay (20000,20000,20000) L_0x1803d50/d; +v0x17c1ea0_0 .net "S", 0 0, L_0x1803f20; 1 drivers +v0x17c1f40_0 .alias "in0", 0 0, v0x17c2dd0_0; +v0x17c1fe0_0 .alias "in1", 0 0, v0x17c2a80_0; +v0x17c2080_0 .net "nS", 0 0, L_0x18039f0; 1 drivers +v0x17c2100_0 .net "out0", 0 0, L_0x1803ab0; 1 drivers +v0x17c21a0_0 .net "out1", 0 0, L_0x1803c00; 1 drivers +v0x17c2280_0 .alias "outfinal", 0 0, v0x17c2d50_0; +S_0x17c1040 .scope module, "ZeroMux0case" "FourInMux" 2 287, 2 29, S_0x17bb1b0; + .timescale -9 -12; +L_0x1805350/d .functor NOT 1, L_0x1805c90, C4<0>, C4<0>, C4<0>; +L_0x1805350 .delay (10000,10000,10000) L_0x1805350/d; +L_0x18055a0/d .functor NOT 1, L_0x17f7960, C4<0>, C4<0>, C4<0>; +L_0x18055a0 .delay (10000,10000,10000) L_0x18055a0/d; +L_0x1805660/d .functor NAND 1, L_0x1805350, L_0x18055a0, L_0x1805f90, C4<1>; +L_0x1805660 .delay (10000,10000,10000) L_0x1805660/d; +L_0x1805750/d .functor NAND 1, L_0x1805c90, L_0x18055a0, L_0x1805dc0, C4<1>; +L_0x1805750 .delay (10000,10000,10000) L_0x1805750/d; +L_0x1805840/d .functor NAND 1, L_0x1805350, L_0x17f7960, L_0x1805e60, C4<1>; +L_0x1805840 .delay (10000,10000,10000) L_0x1805840/d; +L_0x1805930/d .functor NAND 1, L_0x1805c90, L_0x17f7960, L_0x1806220, C4<1>; +L_0x1805930 .delay (10000,10000,10000) L_0x1805930/d; +L_0x1805a10/d .functor NAND 1, L_0x1805660, L_0x1805750, L_0x1805840, L_0x1805930; +L_0x1805a10 .delay (10000,10000,10000) L_0x1805a10/d; +v0x17c1130_0 .net "S0", 0 0, L_0x1805c90; 1 drivers +v0x17c11f0_0 .net "S1", 0 0, L_0x17f7960; 1 drivers +v0x17c1290_0 .net "in0", 0 0, L_0x1805f90; 1 drivers +v0x17c1330_0 .net "in1", 0 0, L_0x1805dc0; 1 drivers +v0x17c13b0_0 .net "in2", 0 0, L_0x1805e60; 1 drivers +v0x17c1450_0 .net "in3", 0 0, L_0x1806220; 1 drivers +v0x17c14f0_0 .net "nS0", 0 0, L_0x1805350; 1 drivers +v0x17c1590_0 .net "nS1", 0 0, L_0x18055a0; 1 drivers +v0x17c1630_0 .net "out", 0 0, L_0x1805a10; 1 drivers +v0x17c16d0_0 .net "out0", 0 0, L_0x1805660; 1 drivers +v0x17c1770_0 .net "out1", 0 0, L_0x1805750; 1 drivers +v0x17c1810_0 .net "out2", 0 0, L_0x1805840; 1 drivers +v0x17c1920_0 .net "out3", 0 0, L_0x1805930; 1 drivers +S_0x17c0680 .scope module, "OneMux0case" "FourInMux" 2 288, 2 29, S_0x17bb1b0; + .timescale -9 -12; +L_0x18062c0/d .functor NOT 1, L_0x1806030, C4<0>, C4<0>, C4<0>; +L_0x18062c0 .delay (10000,10000,10000) L_0x18062c0/d; +L_0x1806370/d .functor NOT 1, L_0x1806160, C4<0>, C4<0>, C4<0>; +L_0x1806370 .delay (10000,10000,10000) L_0x1806370/d; +L_0x18063d0/d .functor NAND 1, L_0x18062c0, L_0x1806370, L_0x1806a50, C4<1>; +L_0x18063d0 .delay (10000,10000,10000) L_0x18063d0/d; +L_0x1806510/d .functor NAND 1, L_0x1806030, L_0x1806370, L_0x1806af0, C4<1>; +L_0x1806510 .delay (10000,10000,10000) L_0x1806510/d; +L_0x1806600/d .functor NAND 1, L_0x18062c0, L_0x1806160, L_0x1806b90, C4<1>; +L_0x1806600 .delay (10000,10000,10000) L_0x1806600/d; +L_0x18066f0/d .functor NAND 1, L_0x1806030, L_0x1806160, L_0x1806f50, C4<1>; +L_0x18066f0 .delay (10000,10000,10000) L_0x18066f0/d; +L_0x18067d0/d .functor NAND 1, L_0x18063d0, L_0x1806510, L_0x1806600, L_0x18066f0; +L_0x18067d0 .delay (10000,10000,10000) L_0x18067d0/d; +v0x17c0770_0 .net "S0", 0 0, L_0x1806030; 1 drivers +v0x17c0830_0 .net "S1", 0 0, L_0x1806160; 1 drivers +v0x17c08d0_0 .net "in0", 0 0, L_0x1806a50; 1 drivers +v0x17c0970_0 .net "in1", 0 0, L_0x1806af0; 1 drivers +v0x17c09f0_0 .net "in2", 0 0, L_0x1806b90; 1 drivers +v0x17c0a90_0 .net "in3", 0 0, L_0x1806f50; 1 drivers +v0x17c0b70_0 .net "nS0", 0 0, L_0x18062c0; 1 drivers +v0x17c0c10_0 .net "nS1", 0 0, L_0x1806370; 1 drivers +v0x17c0cb0_0 .net "out", 0 0, L_0x18067d0; 1 drivers +v0x17c0d50_0 .net "out0", 0 0, L_0x18063d0; 1 drivers +v0x17c0df0_0 .net "out1", 0 0, L_0x1806510; 1 drivers +v0x17c0e90_0 .net "out2", 0 0, L_0x1806600; 1 drivers +v0x17c0fa0_0 .net "out3", 0 0, L_0x18066f0; 1 drivers +S_0x17c0130 .scope module, "TwoMux0case" "TwoInMux" 2 289, 2 8, S_0x17bb1b0; + .timescale -9 -12; +L_0x1806ce0/d .functor NOT 1, L_0x1807500, C4<0>, C4<0>, C4<0>; +L_0x1806ce0 .delay (10000,10000,10000) L_0x1806ce0/d; +L_0x1806dd0/d .functor AND 1, L_0x1807040, L_0x1806ce0, C4<1>, C4<1>; +L_0x1806dd0 .delay (20000,20000,20000) L_0x1806dd0/d; +L_0x1807270/d .functor AND 1, L_0x18077e0, L_0x1807500, C4<1>, C4<1>; +L_0x1807270 .delay (20000,20000,20000) L_0x1807270/d; +L_0x1807320/d .functor OR 1, L_0x1806dd0, L_0x1807270, C4<0>, C4<0>; +L_0x1807320 .delay (20000,20000,20000) L_0x1807320/d; +v0x17c0220_0 .net "S", 0 0, L_0x1807500; 1 drivers +v0x17c02e0_0 .net "in0", 0 0, L_0x1807040; 1 drivers +v0x17c0380_0 .net "in1", 0 0, L_0x18077e0; 1 drivers +v0x17c0420_0 .net "nS", 0 0, L_0x1806ce0; 1 drivers +v0x17c04a0_0 .net "out0", 0 0, L_0x1806dd0; 1 drivers +v0x17c0540_0 .net "out1", 0 0, L_0x1807270; 1 drivers +v0x17c05e0_0 .net "outfinal", 0 0, L_0x1807320; 1 drivers +S_0x17be710 .scope generate, "muxbits[1]" "muxbits[1]" 2 295, 2 295, S_0x17bb1b0; + .timescale -9 -12; +P_0x17bd868 .param/l "i" 2 295, +C4<01>; +S_0x17bf7b0 .scope module, "ZeroMux" "FourInMux" 2 297, 2 29, S_0x17be710; + .timescale -9 -12; +L_0x17f02f0/d .functor NOT 1, L_0x17f0c30, C4<0>, C4<0>, C4<0>; +L_0x17f02f0 .delay (10000,10000,10000) L_0x17f02f0/d; +L_0x17f0540/d .functor NOT 1, L_0x17f0d60, C4<0>, C4<0>, C4<0>; +L_0x17f0540 .delay (10000,10000,10000) L_0x17f0540/d; +L_0x17f0600/d .functor NAND 1, L_0x17f02f0, L_0x17f0540, L_0x17f0e90, C4<1>; +L_0x17f0600 .delay (10000,10000,10000) L_0x17f0600/d; +L_0x17f06f0/d .functor NAND 1, L_0x17f0c30, L_0x17f0540, L_0x17f0f30, C4<1>; +L_0x17f06f0 .delay (10000,10000,10000) L_0x17f06f0/d; +L_0x17f07e0/d .functor NAND 1, L_0x17f02f0, L_0x17f0d60, L_0x17f0fd0, C4<1>; +L_0x17f07e0 .delay (10000,10000,10000) L_0x17f07e0/d; +L_0x17f08d0/d .functor NAND 1, L_0x17f0c30, L_0x17f0d60, L_0x17f11d0, C4<1>; +L_0x17f08d0 .delay (10000,10000,10000) L_0x17f08d0/d; +L_0x17f09b0/d .functor NAND 1, L_0x17f0600, L_0x17f06f0, L_0x17f07e0, L_0x17f08d0; +L_0x17f09b0 .delay (10000,10000,10000) L_0x17f09b0/d; +v0x17bf8a0_0 .net "S0", 0 0, L_0x17f0c30; 1 drivers +v0x17bf960_0 .net "S1", 0 0, L_0x17f0d60; 1 drivers +v0x17bfa00_0 .net "in0", 0 0, L_0x17f0e90; 1 drivers +v0x17bfaa0_0 .net "in1", 0 0, L_0x17f0f30; 1 drivers +v0x17bfb20_0 .net "in2", 0 0, L_0x17f0fd0; 1 drivers +v0x17bfbc0_0 .net "in3", 0 0, L_0x17f11d0; 1 drivers +v0x17bfc60_0 .net "nS0", 0 0, L_0x17f02f0; 1 drivers +v0x17bfd00_0 .net "nS1", 0 0, L_0x17f0540; 1 drivers +v0x17bfda0_0 .net "out", 0 0, L_0x17f09b0; 1 drivers +v0x17bfe40_0 .net "out0", 0 0, L_0x17f0600; 1 drivers +v0x17bfee0_0 .net "out1", 0 0, L_0x17f06f0; 1 drivers +v0x17bff80_0 .net "out2", 0 0, L_0x17f07e0; 1 drivers +v0x17c0090_0 .net "out3", 0 0, L_0x17f08d0; 1 drivers +S_0x17bedf0 .scope module, "OneMux" "FourInMux" 2 298, 2 29, S_0x17be710; + .timescale -9 -12; +L_0x17f1270/d .functor NOT 1, L_0x17f1b90, C4<0>, C4<0>, C4<0>; +L_0x17f1270 .delay (10000,10000,10000) L_0x17f1270/d; +L_0x17f1360/d .functor NOT 1, L_0x17f1cc0, C4<0>, C4<0>, C4<0>; +L_0x17f1360 .delay (10000,10000,10000) L_0x17f1360/d; +L_0x17f1400/d .functor NAND 1, L_0x17f1270, L_0x17f1360, L_0x17f1e50, C4<1>; +L_0x17f1400 .delay (10000,10000,10000) L_0x17f1400/d; +L_0x17f1540/d .functor NAND 1, L_0x17f1b90, L_0x17f1360, L_0x17f2000, C4<1>; +L_0x17f1540 .delay (10000,10000,10000) L_0x17f1540/d; +L_0x17f1630/d .functor NAND 1, L_0x17f1270, L_0x17f1cc0, L_0x17f20a0, C4<1>; +L_0x17f1630 .delay (10000,10000,10000) L_0x17f1630/d; +L_0x17f1720/d .functor NAND 1, L_0x17f1b90, L_0x17f1cc0, L_0x17f2140, C4<1>; +L_0x17f1720 .delay (10000,10000,10000) L_0x17f1720/d; +L_0x17f1890/d .functor NAND 1, L_0x17f1400, L_0x17f1540, L_0x17f1630, L_0x17f1720; +L_0x17f1890 .delay (10000,10000,10000) L_0x17f1890/d; +v0x17beee0_0 .net "S0", 0 0, L_0x17f1b90; 1 drivers +v0x17befa0_0 .net "S1", 0 0, L_0x17f1cc0; 1 drivers +v0x17bf040_0 .net "in0", 0 0, L_0x17f1e50; 1 drivers +v0x17bf0e0_0 .net "in1", 0 0, L_0x17f2000; 1 drivers +v0x17bf160_0 .net "in2", 0 0, L_0x17f20a0; 1 drivers +v0x17bf200_0 .net "in3", 0 0, L_0x17f2140; 1 drivers +v0x17bf2e0_0 .net "nS0", 0 0, L_0x17f1270; 1 drivers +v0x17bf380_0 .net "nS1", 0 0, L_0x17f1360; 1 drivers +v0x17bf420_0 .net "out", 0 0, L_0x17f1890; 1 drivers +v0x17bf4c0_0 .net "out0", 0 0, L_0x17f1400; 1 drivers +v0x17bf560_0 .net "out1", 0 0, L_0x17f1540; 1 drivers +v0x17bf600_0 .net "out2", 0 0, L_0x17f1630; 1 drivers +v0x17bf710_0 .net "out3", 0 0, L_0x17f1720; 1 drivers +S_0x17be880 .scope module, "TwoMux" "TwoInMux" 2 299, 2 8, S_0x17be710; + .timescale -9 -12; +L_0x17f1df0/d .functor NOT 1, L_0x17f2690, C4<0>, C4<0>, C4<0>; +L_0x17f1df0 .delay (10000,10000,10000) L_0x17f1df0/d; +L_0x17f2280/d .functor AND 1, L_0x17f2730, L_0x17f1df0, C4<1>, C4<1>; +L_0x17f2280 .delay (20000,20000,20000) L_0x17f2280/d; +L_0x17f2370/d .functor AND 1, L_0x17f2870, L_0x17f2690, C4<1>, C4<1>; +L_0x17f2370 .delay (20000,20000,20000) L_0x17f2370/d; +L_0x17f2460/d .functor OR 1, L_0x17f2280, L_0x17f2370, C4<0>, C4<0>; +L_0x17f2460 .delay (20000,20000,20000) L_0x17f2460/d; +v0x17be970_0 .net "S", 0 0, L_0x17f2690; 1 drivers +v0x17bea10_0 .net "in0", 0 0, L_0x17f2730; 1 drivers +v0x17beab0_0 .net "in1", 0 0, L_0x17f2870; 1 drivers +v0x17beb50_0 .net "nS", 0 0, L_0x17f1df0; 1 drivers +v0x17bebd0_0 .net "out0", 0 0, L_0x17f2280; 1 drivers +v0x17bec70_0 .net "out1", 0 0, L_0x17f2370; 1 drivers +v0x17bed50_0 .net "outfinal", 0 0, L_0x17f2460; 1 drivers +S_0x17bccf0 .scope generate, "muxbits[2]" "muxbits[2]" 2 295, 2 295, S_0x17bb1b0; + .timescale -9 -12; +P_0x17bbe48 .param/l "i" 2 295, +C4<010>; +S_0x17bdd90 .scope module, "ZeroMux" "FourInMux" 2 297, 2 29, S_0x17bccf0; + .timescale -9 -12; +L_0x17e9500/d .functor NOT 1, L_0x17f3290, C4<0>, C4<0>, C4<0>; +L_0x17e9500 .delay (10000,10000,10000) L_0x17e9500/d; +L_0x17f2ae0/d .functor NOT 1, L_0x17f29b0, C4<0>, C4<0>, C4<0>; +L_0x17f2ae0 .delay (10000,10000,10000) L_0x17f2ae0/d; +L_0x17f2b80/d .functor NAND 1, L_0x17e9500, L_0x17f2ae0, L_0x17f3500, C4<1>; +L_0x17f2b80 .delay (10000,10000,10000) L_0x17f2b80/d; +L_0x17f2cc0/d .functor NAND 1, L_0x17f3290, L_0x17f2ae0, L_0x17f33c0, C4<1>; +L_0x17f2cc0 .delay (10000,10000,10000) L_0x17f2cc0/d; +L_0x17f2db0/d .functor NAND 1, L_0x17e9500, L_0x17f29b0, L_0x17f3660, C4<1>; +L_0x17f2db0 .delay (10000,10000,10000) L_0x17f2db0/d; +L_0x17f2ea0/d .functor NAND 1, L_0x17f3290, L_0x17f29b0, L_0x17f35a0, C4<1>; +L_0x17f2ea0 .delay (10000,10000,10000) L_0x17f2ea0/d; +L_0x17f2fe0/d .functor NAND 1, L_0x17f2b80, L_0x17f2cc0, L_0x17f2db0, L_0x17f2ea0; +L_0x17f2fe0 .delay (10000,10000,10000) L_0x17f2fe0/d; +v0x17bde80_0 .net "S0", 0 0, L_0x17f3290; 1 drivers +v0x17bdf40_0 .net "S1", 0 0, L_0x17f29b0; 1 drivers +v0x17bdfe0_0 .net "in0", 0 0, L_0x17f3500; 1 drivers +v0x17be080_0 .net "in1", 0 0, L_0x17f33c0; 1 drivers +v0x17be100_0 .net "in2", 0 0, L_0x17f3660; 1 drivers +v0x17be1a0_0 .net "in3", 0 0, L_0x17f35a0; 1 drivers +v0x17be240_0 .net "nS0", 0 0, L_0x17e9500; 1 drivers +v0x17be2e0_0 .net "nS1", 0 0, L_0x17f2ae0; 1 drivers +v0x17be380_0 .net "out", 0 0, L_0x17f2fe0; 1 drivers +v0x17be420_0 .net "out0", 0 0, L_0x17f2b80; 1 drivers +v0x17be4c0_0 .net "out1", 0 0, L_0x17f2cc0; 1 drivers +v0x17be560_0 .net "out2", 0 0, L_0x17f2db0; 1 drivers +v0x17be670_0 .net "out3", 0 0, L_0x17f2ea0; 1 drivers +S_0x17bd3d0 .scope module, "OneMux" "FourInMux" 2 298, 2 29, S_0x17bccf0; + .timescale -9 -12; +L_0x17f3870/d .functor NOT 1, L_0x17f3750, C4<0>, C4<0>, C4<0>; +L_0x17f3870 .delay (10000,10000,10000) L_0x17f3870/d; +L_0x17f3960/d .functor NOT 1, L_0x17e2910, C4<0>, C4<0>, C4<0>; +L_0x17f3960 .delay (10000,10000,10000) L_0x17f3960/d; +L_0x17f3a00/d .functor NAND 1, L_0x17f3870, L_0x17f3960, L_0x17f4170, C4<1>; +L_0x17f3a00 .delay (10000,10000,10000) L_0x17f3a00/d; +L_0x17f3b40/d .functor NAND 1, L_0x17f3750, L_0x17f3960, L_0x17e2b30, C4<1>; +L_0x17f3b40 .delay (10000,10000,10000) L_0x17f3b40/d; +L_0x17f3c30/d .functor NAND 1, L_0x17f3870, L_0x17e2910, L_0x17e2a40, C4<1>; +L_0x17f3c30 .delay (10000,10000,10000) L_0x17f3c30/d; +L_0x17f3d50/d .functor NAND 1, L_0x17f3750, L_0x17e2910, L_0x17f4af0, C4<1>; +L_0x17f3d50 .delay (10000,10000,10000) L_0x17f3d50/d; +L_0x17f3ec0/d .functor NAND 1, L_0x17f3a00, L_0x17f3b40, L_0x17f3c30, L_0x17f3d50; +L_0x17f3ec0 .delay (10000,10000,10000) L_0x17f3ec0/d; +v0x17bd4c0_0 .net "S0", 0 0, L_0x17f3750; 1 drivers +v0x17bd580_0 .net "S1", 0 0, L_0x17e2910; 1 drivers +v0x17bd620_0 .net "in0", 0 0, L_0x17f4170; 1 drivers +v0x17bd6c0_0 .net "in1", 0 0, L_0x17e2b30; 1 drivers +v0x17bd740_0 .net "in2", 0 0, L_0x17e2a40; 1 drivers +v0x17bd7e0_0 .net "in3", 0 0, L_0x17f4af0; 1 drivers +v0x17bd8c0_0 .net "nS0", 0 0, L_0x17f3870; 1 drivers +v0x17bd960_0 .net "nS1", 0 0, L_0x17f3960; 1 drivers +v0x17bda00_0 .net "out", 0 0, L_0x17f3ec0; 1 drivers +v0x17bdaa0_0 .net "out0", 0 0, L_0x17f3a00; 1 drivers +v0x17bdb40_0 .net "out1", 0 0, L_0x17f3b40; 1 drivers +v0x17bdbe0_0 .net "out2", 0 0, L_0x17f3c30; 1 drivers +v0x17bdcf0_0 .net "out3", 0 0, L_0x17f3d50; 1 drivers +S_0x17bce60 .scope module, "TwoMux" "TwoInMux" 2 299, 2 8, S_0x17bccf0; + .timescale -9 -12; +L_0x17e2bd0/d .functor NOT 1, L_0x17f5020, C4<0>, C4<0>, C4<0>; +L_0x17e2bd0 .delay (10000,10000,10000) L_0x17e2bd0/d; +L_0x17f4ca0/d .functor AND 1, L_0x17f4b90, L_0x17e2bd0, C4<1>, C4<1>; +L_0x17f4ca0 .delay (20000,20000,20000) L_0x17f4ca0/d; +L_0x17f4d50/d .functor AND 1, L_0x17f5270, L_0x17f5020, C4<1>, C4<1>; +L_0x17f4d50 .delay (20000,20000,20000) L_0x17f4d50/d; +L_0x17f4e40/d .functor OR 1, L_0x17f4ca0, L_0x17f4d50, C4<0>, C4<0>; +L_0x17f4e40 .delay (20000,20000,20000) L_0x17f4e40/d; +v0x17bcf50_0 .net "S", 0 0, L_0x17f5020; 1 drivers +v0x17bcff0_0 .net "in0", 0 0, L_0x17f4b90; 1 drivers +v0x17bd090_0 .net "in1", 0 0, L_0x17f5270; 1 drivers +v0x17bd130_0 .net "nS", 0 0, L_0x17e2bd0; 1 drivers +v0x17bd1b0_0 .net "out0", 0 0, L_0x17f4ca0; 1 drivers +v0x17bd250_0 .net "out1", 0 0, L_0x17f4d50; 1 drivers +v0x17bd330_0 .net "outfinal", 0 0, L_0x17f4e40; 1 drivers +S_0x17bb2e0 .scope generate, "muxbits[3]" "muxbits[3]" 2 295, 2 295, S_0x17bb1b0; + .timescale -9 -12; +P_0x17bb3d8 .param/l "i" 2 295, +C4<011>; +S_0x17bc370 .scope module, "ZeroMux" "FourInMux" 2 297, 2 29, S_0x17bb2e0; + .timescale -9 -12; +L_0x17f50c0/d .functor NOT 1, L_0x17f5c80, C4<0>, C4<0>, C4<0>; +L_0x17f50c0 .delay (10000,10000,10000) L_0x17f50c0/d; +L_0x17f5160/d .functor NOT 1, L_0x17f53a0, C4<0>, C4<0>, C4<0>; +L_0x17f5160 .delay (10000,10000,10000) L_0x17f5160/d; +L_0x17f5510/d .functor NAND 1, L_0x17f50c0, L_0x17f5160, L_0x17f5ef0, C4<1>; +L_0x17f5510 .delay (10000,10000,10000) L_0x17f5510/d; +L_0x17f5650/d .functor NAND 1, L_0x17f5c80, L_0x17f5160, L_0x17e85e0, C4<1>; +L_0x17f5650 .delay (10000,10000,10000) L_0x17f5650/d; +L_0x17f5740/d .functor NAND 1, L_0x17f50c0, L_0x17f53a0, L_0x17f5db0, C4<1>; +L_0x17f5740 .delay (10000,10000,10000) L_0x17f5740/d; +L_0x17f5860/d .functor NAND 1, L_0x17f5c80, L_0x17f53a0, L_0x17f6300, C4<1>; +L_0x17f5860 .delay (10000,10000,10000) L_0x17f5860/d; +L_0x17f59d0/d .functor NAND 1, L_0x17f5510, L_0x17f5650, L_0x17f5740, L_0x17f5860; +L_0x17f59d0 .delay (10000,10000,10000) L_0x17f59d0/d; +v0x17bc460_0 .net "S0", 0 0, L_0x17f5c80; 1 drivers +v0x17bc520_0 .net "S1", 0 0, L_0x17f53a0; 1 drivers +v0x17bc5c0_0 .net "in0", 0 0, L_0x17f5ef0; 1 drivers +v0x17bc660_0 .net "in1", 0 0, L_0x17e85e0; 1 drivers +v0x17bc6e0_0 .net "in2", 0 0, L_0x17f5db0; 1 drivers +v0x17bc780_0 .net "in3", 0 0, L_0x17f6300; 1 drivers +v0x17bc820_0 .net "nS0", 0 0, L_0x17f50c0; 1 drivers +v0x17bc8c0_0 .net "nS1", 0 0, L_0x17f5160; 1 drivers +v0x17bc960_0 .net "out", 0 0, L_0x17f59d0; 1 drivers +v0x17bca00_0 .net "out0", 0 0, L_0x17f5510; 1 drivers +v0x17bcaa0_0 .net "out1", 0 0, L_0x17f5650; 1 drivers +v0x17bcb40_0 .net "out2", 0 0, L_0x17f5740; 1 drivers +v0x17bcc50_0 .net "out3", 0 0, L_0x17f5860; 1 drivers +S_0x17bb9b0 .scope module, "OneMux" "FourInMux" 2 298, 2 29, S_0x17bb2e0; + .timescale -9 -12; +L_0x17e8680/d .functor NOT 1, L_0x17f61a0, C4<0>, C4<0>, C4<0>; +L_0x17e8680 .delay (10000,10000,10000) L_0x17e8680/d; +L_0x17f6430/d .functor NOT 1, L_0x17f6db0, C4<0>, C4<0>, C4<0>; +L_0x17f6430 .delay (10000,10000,10000) L_0x17f6430/d; +L_0x17f64d0/d .functor NAND 1, L_0x17e8680, L_0x17f6430, L_0x17f6c40, C4<1>; +L_0x17f64d0 .delay (10000,10000,10000) L_0x17f64d0/d; +L_0x17f6610/d .functor NAND 1, L_0x17f61a0, L_0x17f6430, L_0x17f6ce0, C4<1>; +L_0x17f6610 .delay (10000,10000,10000) L_0x17f6610/d; +L_0x17f6700/d .functor NAND 1, L_0x17e8680, L_0x17f6db0, L_0x17f7070, C4<1>; +L_0x17f6700 .delay (10000,10000,10000) L_0x17f6700/d; +L_0x17f6820/d .functor NAND 1, L_0x17f61a0, L_0x17f6db0, L_0x17f7160, C4<1>; +L_0x17f6820 .delay (10000,10000,10000) L_0x17f6820/d; +L_0x17f6990/d .functor NAND 1, L_0x17f64d0, L_0x17f6610, L_0x17f6700, L_0x17f6820; +L_0x17f6990 .delay (10000,10000,10000) L_0x17f6990/d; +v0x17bbaa0_0 .net "S0", 0 0, L_0x17f61a0; 1 drivers +v0x17bbb60_0 .net "S1", 0 0, L_0x17f6db0; 1 drivers +v0x17bbc00_0 .net "in0", 0 0, L_0x17f6c40; 1 drivers +v0x17bbca0_0 .net "in1", 0 0, L_0x17f6ce0; 1 drivers +v0x17bbd20_0 .net "in2", 0 0, L_0x17f7070; 1 drivers +v0x17bbdc0_0 .net "in3", 0 0, L_0x17f7160; 1 drivers +v0x17bbea0_0 .net "nS0", 0 0, L_0x17e8680; 1 drivers +v0x17bbf40_0 .net "nS1", 0 0, L_0x17f6430; 1 drivers +v0x17bbfe0_0 .net "out", 0 0, L_0x17f6990; 1 drivers +v0x17bc080_0 .net "out0", 0 0, L_0x17f64d0; 1 drivers +v0x17bc120_0 .net "out1", 0 0, L_0x17f6610; 1 drivers +v0x17bc1c0_0 .net "out2", 0 0, L_0x17f6700; 1 drivers +v0x17bc2d0_0 .net "out3", 0 0, L_0x17f6820; 1 drivers +S_0x17bb450 .scope module, "TwoMux" "TwoInMux" 2 299, 2 8, S_0x17bb2e0; + .timescale -9 -12; +L_0x17f10c0/d .functor NOT 1, L_0x17f78c0, C4<0>, C4<0>, C4<0>; +L_0x17f10c0 .delay (10000,10000,10000) L_0x17f10c0/d; +L_0x17f6ee0/d .functor AND 1, L_0x17f7460, L_0x17f10c0, C4<1>, C4<1>; +L_0x17f6ee0 .delay (20000,20000,20000) L_0x17f6ee0/d; +L_0x17f6fd0/d .functor AND 1, L_0x17f7500, L_0x17f78c0, C4<1>, C4<1>; +L_0x17f6fd0 .delay (20000,20000,20000) L_0x17f6fd0/d; +L_0x17f7650/d .functor OR 1, L_0x17f6ee0, L_0x17f6fd0, C4<0>, C4<0>; +L_0x17f7650 .delay (20000,20000,20000) L_0x17f7650/d; +v0x17bb540_0 .net "S", 0 0, L_0x17f78c0; 1 drivers +v0x17bb5c0_0 .net "in0", 0 0, L_0x17f7460; 1 drivers +v0x17bb640_0 .net "in1", 0 0, L_0x17f7500; 1 drivers +v0x17bb6e0_0 .net "nS", 0 0, L_0x17f10c0; 1 drivers +v0x17bb790_0 .net "out0", 0 0, L_0x17f6ee0; 1 drivers +v0x17bb830_0 .net "out1", 0 0, L_0x17f6fd0; 1 drivers +v0x17bb910_0 .net "outfinal", 0 0, L_0x17f7650; 1 drivers + .scope S_0x1782ed0; T_0 ; - %vpi_call 3 21 "$display", " A | B |Command|Output | exOut|Cout|OF|subtract|SLTflag"; + %vpi_call 3 35 "$display", "Test ALU - Add"; + %vpi_call 3 36 "$display", " A | B |Command|Output | ExpectOut|Cout|OF|subtract|SLTflag"; %movi 8, 8, 4; - %set/v v0x24d6840_0, 8, 4; - %movi 8, 1, 4; - %set/v v0x24d6990_0, 8, 4; - %set/v v0x24d6a40_0, 0, 3; - %delay 1000000, 0; - %vpi_call 3 23 "$display", "%b | %b | %b | %b | Expect 1001| %b | %b ", v0x24d6840_0, v0x24d6990_0, v0x24d6a40_0, v0x24d68e0_0, v0x24d6c20_0, v0x24d6cd0_0; - %movi 8, 10, 4; - %set/v v0x24d6840_0, 8, 4; + %set/v v0x17dd890_0, 8, 4; %movi 8, 1, 4; - %set/v v0x24d6990_0, 8, 4; - %set/v v0x24d6a40_0, 0, 3; + %set/v v0x17dda10_0, 8, 4; + %set/v v0x17dda90_0, 0, 3; %delay 1000000, 0; - %vpi_call 3 26 "$display", "%b | %b | %b | %b | Expect 1011| %b | %b | %b", v0x24d6840_0, v0x24d6990_0, v0x24d6a40_0, v0x24d68e0_0, v0x24d6c20_0, v0x24d6cd0_0, v0x24d6d80_0; - %movi 8, 10, 4; - %set/v v0x24d6840_0, 8, 4; - %movi 8, 1, 4; - %set/v v0x24d6990_0, 8, 4; - %set/v v0x24d6a40_0, 0, 3; - %delay 1000000, 0; - %vpi_call 3 29 "$display", "%b | %b | %b | %b | Expect 1011| %b | %b ", v0x24d6840_0, v0x24d6990_0, v0x24d6a40_0, v0x24d68e0_0, v0x24d6c20_0, v0x24d6cd0_0; - %movi 8, 10, 4; - %set/v v0x24d6840_0, 8, 4; - %movi 8, 7, 4; - %set/v v0x24d6990_0, 8, 4; - %set/v v0x24d6a40_0, 0, 3; - %delay 1000000, 0; - %vpi_call 3 32 "$display", "%b | %b | %b | %b | Expect 0001| %b | %b ", v0x24d6840_0, v0x24d6990_0, v0x24d6a40_0, v0x24d68e0_0, v0x24d6c20_0, v0x24d6cd0_0; - %movi 8, 10, 4; - %set/v v0x24d6840_0, 8, 4; - %movi 8, 7, 4; - %set/v v0x24d6990_0, 8, 4; - %movi 8, 1, 3; - %set/v v0x24d6a40_0, 8, 3; - %delay 1000000, 0; - %vpi_call 3 35 "$display", "%b | %b | %b | %b | Expect 0011| %b | %b | %b", v0x24d6840_0, v0x24d6990_0, v0x24d6a40_0, v0x24d68e0_0, v0x24d6c20_0, v0x24d6cd0_0, v0x24d6d80_0; - %movi 8, 10, 4; - %set/v v0x24d6840_0, 8, 4; - %movi 8, 7, 4; - %set/v v0x24d6990_0, 8, 4; - %movi 8, 3, 3; - %set/v v0x24d6a40_0, 8, 3; - %delay 1000000, 0; - %vpi_call 3 38 "$display", "%b | %b | %b | %b | Expect 0011| %b | %b | %b | %b", v0x24d6840_0, v0x24d6990_0, v0x24d6a40_0, v0x24d68e0_0, v0x24d6c20_0, v0x24d6cd0_0, v0x24d6d80_0, v0x24d6af0_0; - %movi 8, 7, 4; - %set/v v0x24d6840_0, 8, 4; - %movi 8, 10, 4; - %set/v v0x24d6990_0, 8, 4; - %movi 8, 3, 3; - %set/v v0x24d6a40_0, 8, 3; - %delay 1000000, 0; - %vpi_call 3 41 "$display", "%b | %b | %b | %b | Expect 0011| %b | %b | %b | %b", v0x24d6840_0, v0x24d6990_0, v0x24d6a40_0, v0x24d68e0_0, v0x24d6c20_0, v0x24d6cd0_0, v0x24d6d80_0, v0x24d6af0_0; + %vpi_call 3 38 "$display", "%b | %b | %b | %b | Expect 1001| %b | %b ", v0x17dd890_0, v0x17dda10_0, v0x17dda90_0, v0x17dd910_0, v0x17ddd10_0, v0x17ddd90_0; + %vpi_call 3 40 "$display", " A | B |Command|Output | ExpectOut|Cout|OF|subtract|SLTflag"; + %movi 8, 8, 4; + %set/v v0x17dd890_0, 8, 4; %movi 8, 1, 4; - %set/v v0x24d6840_0, 8, 4; - %movi 8, 2, 4; - %set/v v0x24d6990_0, 8, 4; - %movi 8, 3, 3; - %set/v v0x24d6a40_0, 8, 3; + %set/v v0x17dda10_0, 8, 4; + %set/v v0x17dda90_0, 0, 3; %delay 1000000, 0; - %vpi_call 3 45 "$display", "%b | %b | %b | %b | Expect x| %b | %b | %b | %b", v0x24d6840_0, v0x24d6990_0, v0x24d6a40_0, v0x24d68e0_0, v0x24d6c20_0, v0x24d6cd0_0, v0x24d6d80_0, v0x24d6af0_0; + %vpi_call 3 42 "$display", "%b | %b | %b | %b | Expect 1001| %b | %b ", v0x17dd890_0, v0x17dda10_0, v0x17dda90_0, v0x17ddb10_0, v0x17ddd10_0, v0x17ddd90_0; %end; .thread T_0; # The file index is used to find the file name in the following table. diff --git a/testing.t.v b/testing.t.v index 7ff5bb0..ab5be1b 100644 --- a/testing.t.v +++ b/testing.t.v @@ -5,6 +5,9 @@ module test32Adder(); parameter size = 4; +output [size-1:0] OneBitFinalOut; +output [size-1:0] OrNorXorOut; +output [size-1:0] AndNandOut; wire [size-1:0] AddSubSLTSum; wire carryout; wire overflow; @@ -13,15 +16,31 @@ wire [size-1:0] subtract; reg [size-1:0] A, B; reg [2:0] Command; reg [size-1:0]carryin; +wire Cmd0Start [size-1:0]; +wire Cmd1Start [size-1:0]; wire [size-1:0] CarryoutWire; + + AddSubSLT32 trial(AddSubSLTSum, carryout, overflow, SLTflag, subtract, A, B, Command, carryin); +AndNand32 trial1(AndNandOut, A, B, Command); + +OrNorXor32 trial2(OrNorXorOut, A, B, Command); + +Bitslice32 superalu(OneBitFinalOut, AddSubSLTSum, carryout, overflow, SLTflag, OrNorXorOut, AndNandOut, subtract, A, B, Command, carryin); + + initial begin -$display(" A | B |Command|Output | exOut|Cout|OF|subtract|SLTflag"); +$display("Test ALU - Add"); +$display(" A | B |Command|Output | ExpectOut|Cout|OF|subtract|SLTflag"); A = 4'b1000; B = 4'b0001; Command =3'b000; #1000 $display("%b | %b | %b | %b | Expect 1001| %b | %b ", A, B, Command, AddSubSLTSum, carryout, overflow); +$display(" A | B |Command|Output | ExpectOut|Cout|OF|subtract|SLTflag"); +A = 4'b1000; B = 4'b0001; Command =3'b000; #1000 +$display("%b | %b | %b | %b | Expect 1001| %b | %b ", A, B, Command, OneBitFinalOut, carryout, overflow); +/* A = 4'b1010; B = 4'b0001; Command =3'b000; #1000 $display("%b | %b | %b | %b | Expect 1011| %b | %b | %b", A, B, Command, AddSubSLTSum, carryout, overflow, subtract); @@ -42,7 +61,31 @@ $display("%b | %b | %b | %b | Expect 0011| %b | %b | %b | %b", A, B, Command, Ad A = 4'b0001; B = 4'b0010; Command =3'b011; #1000 -$display("%b | %b | %b | %b | Expect x| %b | %b | %b | %b", A, B, Command, AddSubSLTSum, carryout, overflow, subtract, SLTflag); +$display("%b | %b | %b | %b | Expect xxxx| %b | %b | %b | %b", A, B, Command, AddSubSLTSum, carryout, overflow, subtract, SLTflag); + + +$display("AND/NAND"); +$display("A | B | Command | Output | ExpectedOut"); +A = 4'b0001; B = 4'b0010; Command =3'b100; #1000 +$display("%b | %b | %b | %b | Expect 0000", A, B, Command, AndNandOut); + +$display("A | B | Command | Output | ExpectedOut"); +A = 4'b0001; B = 4'b0010; Command =3'b101; #1000 +$display("%b | %b | %b | %b | Expect 1111", A, B, Command, AndNandOut); + +$display("OR/NOR/XOR"); +$display("A | B | Command | Output | ExpectedOutXOR"); +A = 4'b0001; B = 4'b0010; Command =3'b010; #1000 +$display("%b | %b | %b | %b | Expect 0011", A, B, Command, OrNorXorOut); + +$display("A | B | Command | Output | ExpectedOutNOR"); +A = 4'b0001; B = 4'b0010; Command =3'b110; #1000 +$display("%b | %b | %b | %b | Expect 1100", A, B, Command, OrNorXorOut); + +$display("A | B | Command | Output | ExpectedOutOR"); +A = 4'b0001; B = 4'b0010; Command =3'b111; #1000 +$display("%b | %b | %b | %b | Expect 0011", A, B, Command, OrNorXorOut); +*/ end From c798aebede26e3eedfe3ff814012118f1db0da3e Mon Sep 17 00:00:00 2001 From: Logan Sweet Date: Sun, 8 Oct 2017 18:56:57 -0400 Subject: [PATCH 08/28] delete failed path --- alu.v | 196 ---------------------------------------------------------- 1 file changed, 196 deletions(-) delete mode 100644 alu.v diff --git a/alu.v b/alu.v deleted file mode 100644 index 8e7014a..0000000 --- a/alu.v +++ /dev/null @@ -1,196 +0,0 @@ -`define AND and #20 // nand with nor is 20 -`define NAND nand #10 // base is 10 -`define NOT not #10 // not base is 10 -`define OR or #20 // nor with not is 20 -`define NOR nor #10 // base is 10 -`define XOR xor #40 // and with or is 40 - -module TwoInMux -( - output outfinal, - input S, - input in0, in1 -); - wire nS; - wire out0; - wire out1; - - //`NOT Sinv(nS, S); - //`NAND n0(out0, S, in0); - //`NAND n1(out1, nS, in1); - //`NAND n2(outfinal, out0, out1); // final output of mux - - `NOT Sinv(nS, S); - `AND andgate1(out0, in0, nS); - `AND andgate3(out1, in1, S); - `OR orgate(outfinal, out0, out1); -endmodule - -module FourInMux -( - output out, - input S0, S1, - input in0, in1, in2, in3 -); - wire nS0; - wire nS1; - - wire out0; - wire out1; - wire out2; - wire out3; - - `NOT S0inv(nS0, S0); - `NOT S1inv(nS1, S1); - `NAND n0(out0, nS0, nS1, in0); - `NAND n1(out1, S0, nS1, in1); - `NAND n2(out2, nS0, S1, in2); - `NAND n3(out3, S0, S1, in3); - - `NAND addthem(out, out0, out1, out2, out3); -endmodule - -module AndNand -( -output AndNandOut, -input A, B, -input[2:0] Command - -); - -wire AnandB; -wire AandB; - - `NAND n0(AnandB, A, B); - `NOT Ainv(AandB, AnandB); - TwoInMux potato(AndNandOut, Command[0], AandB, AnandB); // order to follow out,S,in0, in1 - -endmodule - -module OrNorXor -( -output OrNorXorOut, -input A, B, -input[2:0] Command -); -wire AnorB; -wire AorB; -wire AnandB; -wire nXor; -wire AxorB; -wire XorNor; - - `NOR nor0(AnorB, A, B); - `NOT n0(AorB, AnorB); - `NAND and0(AnandB, A, B); - `NAND and1(nXor, AnandB, AorB); - `NOT n1(AxorB, nXor); - - TwoInMux mux0(XorNor, Command[2], AxorB, AnorB); - TwoInMux mux1(OrNorXorOut, Command[0], XorNor, AorB); -endmodule - -module ZerothAddSubSLT -( -output AddSubSLTSum, carryout, //overflow, -input A, B, -input[2:0] Command -//input carryin -); - wire nB; - wire BornB; - wire AxorB; - wire AandB; - wire CINandAxorB; - - `NOT Binv(nB, B); - TwoInMux mux0(BornB, Command[0], B, nB); - `XOR XOR1(AxorB, A, BornB); - `XOR XOR2(AddSubSLTSum, AxorB, Command[0]); - `AND AND1(AandB, A, BornB); - `AND AND2(CINandAxorB, AxorB, Command[0]); - `OR OR1(carryout, AandB, CINandAxorB); -endmodule - -module MiddleAddSubSLT -( -output AddSubSLTSum, carryout, //overflow, -input A, B, -input[2:0] Command, -input carryin -); - wire nB; - wire BornB; - wire AxorB; - wire AandB; - wire CINandAxorB; - - `NOT Binv(nB, B); - TwoInMux mux0(BornB, Command[0], B, nB); - `XOR XOR1(AxorB, A, BornB); - `XOR XOR2(AddSubSLTSum, AxorB, carryin); - `AND AND1(AandB, A, BornB); - `AND AND2(CINandAxorB, AxorB, carryin); - `OR OR1(carryout, AandB, CINandAxorB); -endmodule - -module LastAddSubSLT -( -output AddSubSLTSum, carryout, overflow, -input A, B, -input[2:0] Command, -input carryin -); - wire nB; - wire BornB; - wire AxorB; - wire AandB; - wire CINandAxorB; - - `NOT Binv(nB, B); - TwoInMux mux0(BornB, Command[0], B, nB); - `XOR XOR1(AxorB, A, BornB); - `XOR XOR2(AddSubSLTSum, AxorB, carryin); - `AND AND1(AandB, A, BornB); - `AND AND2(CINandAxorB, AxorB, carryin); - `OR OR1(carryout, AandB, CINandAxorB); - `XOR xor3(overflow, carryout, carryin); -endmodule - -module Bitslice -( -output OneBitFinalOut, -output AddSubSLTSum, carryout, //overflow, -output OrNorXorOut, -input A, B, -input[2:0] Command, -input carryin - -); - wire Cmd0Start; - wire Cmd1Start; - - wire nB; - wire BornB; - wire AxorB; - wire AandB; - wire CINandAxorB; - - wire AnorB; - wire AorB; - wire AnandB; - wire nXor; - wire XorNor; - - MiddleAddSubSLT rottenpotato(AddSumSLTSum, carryout, A, B, Command, carryin); - OrNorXor idahopotato(OrNorXorOut, A, B, Command); - - //FourInMux ZeroMux(Cmd0Start, Command[1], Command[0], AddSumSLTSum, AddSumSLTSum, OrNorXorOut, AddSumSLTSum); - - FourInMux ZeroMux(OneBitFinalOut, Command[0], Command[1], AddSumSLTSum, AddSumSLTSum, OrNorXorOut, AddSumSLTSum); - -endmodule - - - - From ab90137f4df330373fba43762b98ce4e604edaa3 Mon Sep 17 00:00:00 2001 From: mjakus Date: Mon, 9 Oct 2017 08:23:44 -0400 Subject: [PATCH 09/28] Cleaned up code --- alu2.v | 308 ++++++++++++++++++++------------------------------------- 1 file changed, 108 insertions(+), 200 deletions(-) diff --git a/alu2.v b/alu2.v index 75b87f5..f223d96 100644 --- a/alu2.v +++ b/alu2.v @@ -5,7 +5,7 @@ `define NOR nor #10 // base is 10 `define XOR xor #40 // and with or is 40 -module TwoInMux +module TwoInMux // this module is a two input mux that takes in two inputs (in0 and in1) and uses switch S to pick the value for outfinal ( output outfinal, input S, @@ -15,18 +15,13 @@ module TwoInMux wire out0; wire out1; - //`NOT Sinv(nS, S); - //`NAND n0(out0, S, in0); - //`NAND n1(out1, nS, in1); - //`NAND n2(outfinal, out0, out1); // final output of mux - `NOT Sinv(nS, S); - `AND andgate1(out0, in0, nS); + `AND andgate1(out0, in0, nS); `AND andgate3(out1, in1, S); - `OR orgate(outfinal, out0, out1); + `OR orgate(outfinal, out0, out1); endmodule -module FourInMux +module FourInMux // this module is a four input mux that takes in four inputs (in0, in1, in2, and in3) and uses switches S0 and S1 to pick the value for out ( output out, input S0, S1, @@ -50,74 +45,75 @@ module FourInMux `NAND addthem(out, out0, out1, out2, out3); endmodule -module AndNand +module AndNand // Uses Command[0] to determine whether and or nand is chosen ( output AndNandOut, input A, B, input[2:0] Command - ); -wire AnandB; -wire AandB; + wire AnandB; + wire AandB; - `NAND n0(AnandB, A, B); - `NOT Ainv(AandB, AnandB); - TwoInMux potato(AndNandOut, Command[0], AandB, AnandB); // order to follow out,S,in0, in1 + `NAND n0(AnandB, A, B); + `NOT Ainv(AandB, AnandB); + TwoInMux potato(AndNandOut, Command[0], AandB, AnandB); // order to follow out,S,in0, in1 endmodule module OrNorXor ( -output OrNorXorOut, +output OrNorXorOut, // uses both Command[0] and Command[2] to determine whether Or, Nor, or Xor is used input A, B, input[2:0] Command ); -wire AnorB; -wire AorB; -wire AnandB; -wire nXor; -wire AxorB; -wire XorNor; - - `NOR nor0(AnorB, A, B); - `NOT n0(AorB, AnorB); - `NAND and0(AnandB, A, B); - `NAND and1(nXor, AnandB, AorB); - `NOT n1(AxorB, nXor); - - TwoInMux mux0(XorNor, Command[2], AxorB, AnorB); - TwoInMux mux1(OrNorXorOut, Command[0], XorNor, AorB); + wire AnorB; + wire AorB; + wire AnandB; + wire nXor; + wire AxorB; + wire XorNor; + + `NOR nor0(AnorB, A, B); + `NOT n0(AorB, AnorB); + `NAND and0(AnandB, A, B); + `NAND and1(nXor, AnandB, AorB); + `NOT n1(AxorB, nXor); + + TwoInMux mux0(XorNor, Command[2], AxorB, AnorB); + TwoInMux mux1(OrNorXorOut, Command[0], XorNor, AorB); endmodule - -module MiddleAddSubSLT +// this module calculates addition, subtraction, and SLT based on which command is selected. SLT happens when A Date: Mon, 9 Oct 2017 12:52:32 -0400 Subject: [PATCH 10/28] Making ALU test benches --- OriginalTesting.t.v | 6 + alu2.v | 4 + test | 4476 +++++++++++++++++++++++-------------------- testing.t.v | 404 +++- 4 files changed, 2754 insertions(+), 2136 deletions(-) diff --git a/OriginalTesting.t.v b/OriginalTesting.t.v index a48d838..1b76031 100644 --- a/OriginalTesting.t.v +++ b/OriginalTesting.t.v @@ -46,6 +46,12 @@ initial begin $display("A B| Command | Output | Expected Output"); A=1;B=1;Command=3'b000; carryin = 0; #1000 $display("%b %b | %b | %b | 0 | %b", A, B, Command, AddSubSLTSum, carryout); + A=1;B=0;Command=3'b000; carryin = 0; #1000 + $display("%b %b | %b | %b | 1 | %b", A, B, Command, AddSubSLTSum, carryout); + A=0;B=1;Command=3'b000; carryin = 0; #1000 + $display("%b %b | %b | %b | 1 | %b", A, B, Command, AddSubSLTSum, carryout); + A=0;B=0;Command=3'b000; carryin = 0; #1000 + $display("%b %b | %b | %b | 0 | %b", A, B, Command, AddSubSLTSum, carryout); A=1;B=1;Command=3'b001; carryin = 1; #1000 $display("%b %b | %b | %b | 0 | %b", A, B, Command, AddSubSLTSum, carryout); diff --git a/alu2.v b/alu2.v index f223d96..31a7747 100644 --- a/alu2.v +++ b/alu2.v @@ -263,6 +263,7 @@ output SLTflag, output [size-1:0] OrNorXorOut, output [size-1:0] AndNandOut, output [size-1:0] subtract, +output ZeroFlag, input [size-1:0] A, input [size-1:0] B, input[2:0] Command, @@ -291,5 +292,8 @@ input [size-1:0]carryin // don't think this does anything but don't want to brea end endgenerate + // AndNand32 zeroflagtest(ZeroInt0, OneBitFinalOut, OneBitFinalOut, 3'b101); + //`NAND zeroflagtest(ZeroFlag, OneBitFinalOut, OneBitFinalOut); + endmodule diff --git a/test b/test index 6247510..8b195a8 100755 --- a/test +++ b/test @@ -4,2111 +4,2395 @@ :vpi_module "system"; :vpi_module "v2005_math"; :vpi_module "va_math"; -S_0x178b140 .scope module, "Bitslice" "Bitslice" 2 121; - .timescale -9 -12; -v0x17ba940_0 .net "A", 0 0, C4; 0 drivers -v0x17ba9e0_0 .net "AddSubSLTSum", 0 0, C4; 0 drivers -v0x17baa80_0 .net "AddSumSLTSum", 0 0, L_0x17de9e0; 1 drivers -v0x17bab90_0 .net "AndNandOut", 0 0, L_0x17e06b0; 1 drivers -v0x17baca0_0 .net "B", 0 0, C4; 0 drivers -v0x17badb0_0 .net "Cmd0Start", 0 0, L_0x17e0ee0; 1 drivers -v0x17bae30_0 .net "Cmd1Start", 0 0, L_0x17e1910; 1 drivers -v0x17baeb0_0 .net "Command", 2 0, C4; 0 drivers -v0x17baf30_0 .net "OneBitFinalOut", 0 0, L_0x17e2070; 1 drivers -v0x17bafb0_0 .net "OrNorXorOut", 0 0, L_0x17dfe00; 1 drivers -v0x17bb030_0 .net "carryin", 0 0, C4; 0 drivers -v0x17bb0b0_0 .net "carryout", 0 0, L_0x17ded90; 1 drivers -v0x17bb130_0 .net "subtract", 0 0, L_0x17de6b0; 1 drivers -L_0x17e10c0 .part C4, 0, 1; -L_0x17e11f0 .part C4, 1, 1; -L_0x17e1af0 .part C4, 0, 1; -L_0x17e1c20 .part C4, 1, 1; -L_0x17e21a0 .part C4, 2, 1; -S_0x17b98e0 .scope module, "rottenpotato" "MiddleAddSubSLT" 2 147, 2 95, S_0x178b140; - .timescale -9 -12; -L_0x17d9050/d .functor NOT 1, C4, C4<0>, C4<0>, C4<0>; -L_0x17d9050 .delay (10000,10000,10000) L_0x17d9050/d; -L_0x17de550/d .functor NOT 1, L_0x17de610, C4<0>, C4<0>, C4<0>; -L_0x17de550 .delay (10000,10000,10000) L_0x17de550/d; -L_0x17de6b0/d .functor AND 1, L_0x17de7f0, L_0x17de550, C4<1>, C4<1>; -L_0x17de6b0 .delay (20000,20000,20000) L_0x17de6b0/d; -L_0x17de890/d .functor XOR 1, C4, L_0x17de250, C4<0>, C4<0>; -L_0x17de890 .delay (40000,40000,40000) L_0x17de890/d; -L_0x17de9e0/d .functor XOR 1, L_0x17de890, C4, C4<0>, C4<0>; -L_0x17de9e0 .delay (40000,40000,40000) L_0x17de9e0/d; -L_0x17deb40/d .functor AND 1, C4, L_0x17de250, C4<1>, C4<1>; -L_0x17deb40 .delay (20000,20000,20000) L_0x17deb40/d; -L_0x17decd0/d .functor AND 1, L_0x17de890, C4, C4<1>, C4<1>; -L_0x17decd0 .delay (20000,20000,20000) L_0x17decd0/d; -L_0x17ded90/d .functor OR 1, L_0x17deb40, L_0x17decd0, C4<0>, C4<0>; -L_0x17ded90 .delay (20000,20000,20000) L_0x17ded90/d; -v0x17b9e60_0 .alias "A", 0 0, v0x17ba940_0; -v0x17b9f50_0 .net "AandB", 0 0, L_0x17deb40; 1 drivers -v0x17b9ff0_0 .alias "AddSubSLTSum", 0 0, v0x17baa80_0; -v0x17ba070_0 .net "AxorB", 0 0, L_0x17de890; 1 drivers -v0x17ba0f0_0 .alias "B", 0 0, v0x17baca0_0; -v0x17ba170_0 .net "BornB", 0 0, L_0x17de250; 1 drivers -v0x17ba230_0 .net "CINandAxorB", 0 0, L_0x17decd0; 1 drivers -v0x17ba2b0_0 .alias "Command", 2 0, v0x17baeb0_0; -v0x17ba3d0_0 .net *"_s3", 0 0, L_0x17de610; 1 drivers -v0x17ba470_0 .net *"_s5", 0 0, L_0x17de7f0; 1 drivers -v0x17ba570_0 .alias "carryin", 0 0, v0x17bb030_0; -v0x17ba610_0 .alias "carryout", 0 0, v0x17bb0b0_0; -v0x17ba720_0 .net "nB", 0 0, L_0x17d9050; 1 drivers -v0x17ba7a0_0 .net "nCmd2", 0 0, L_0x17de550; 1 drivers -v0x17ba8a0_0 .alias "subtract", 0 0, v0x17bb130_0; -L_0x17de420 .part C4, 0, 1; -L_0x17de610 .part C4, 2, 1; -L_0x17de7f0 .part C4, 0, 1; -S_0x17b99d0 .scope module, "mux0" "TwoInMux" 2 111, 2 8, S_0x17b98e0; - .timescale -9 -12; -L_0x17ddf70/d .functor NOT 1, L_0x17de420, C4<0>, C4<0>, C4<0>; -L_0x17ddf70 .delay (10000,10000,10000) L_0x17ddf70/d; -L_0x17de030/d .functor AND 1, C4, L_0x17ddf70, C4<1>, C4<1>; -L_0x17de030 .delay (20000,20000,20000) L_0x17de030/d; -L_0x17de140/d .functor AND 1, L_0x17d9050, L_0x17de420, C4<1>, C4<1>; -L_0x17de140 .delay (20000,20000,20000) L_0x17de140/d; -L_0x17de250/d .functor OR 1, L_0x17de030, L_0x17de140, C4<0>, C4<0>; -L_0x17de250 .delay (20000,20000,20000) L_0x17de250/d; -v0x17b9ac0_0 .net "S", 0 0, L_0x17de420; 1 drivers -v0x17b9b40_0 .alias "in0", 0 0, v0x17baca0_0; -v0x17b9bc0_0 .alias "in1", 0 0, v0x17ba720_0; -v0x17b9c40_0 .net "nS", 0 0, L_0x17ddf70; 1 drivers -v0x17b9cc0_0 .net "out0", 0 0, L_0x17de030; 1 drivers -v0x17b9d40_0 .net "out1", 0 0, L_0x17de140; 1 drivers -v0x17b9dc0_0 .alias "outfinal", 0 0, v0x17ba170_0; -S_0x17b85f0 .scope module, "idahopotato" "OrNorXor" 2 148, 2 70, S_0x178b140; - .timescale -9 -12; -L_0x17def10/d .functor NOR 1, C4, C4, C4<0>, C4<0>; -L_0x17def10 .delay (10000,10000,10000) L_0x17def10/d; -L_0x17df070/d .functor NOT 1, L_0x17def10, C4<0>, C4<0>, C4<0>; -L_0x17df070 .delay (10000,10000,10000) L_0x17df070/d; -L_0x17df1a0/d .functor NAND 1, C4, C4, C4<1>, C4<1>; -L_0x17df1a0 .delay (10000,10000,10000) L_0x17df1a0/d; -L_0x17df330/d .functor NAND 1, L_0x17df1a0, L_0x17df070, C4<1>, C4<1>; -L_0x17df330 .delay (10000,10000,10000) L_0x17df330/d; -L_0x17df420/d .functor NOT 1, L_0x17df330, C4<0>, C4<0>, C4<0>; -L_0x17df420 .delay (10000,10000,10000) L_0x17df420/d; -v0x17b91a0_0 .alias "A", 0 0, v0x17ba940_0; -v0x17b9250_0 .net "AnandB", 0 0, L_0x17df1a0; 1 drivers -v0x17b92d0_0 .net "AnorB", 0 0, L_0x17def10; 1 drivers -v0x17b9380_0 .net "AorB", 0 0, L_0x17df070; 1 drivers -v0x17b9460_0 .net "AxorB", 0 0, L_0x17df420; 1 drivers -v0x17b9510_0 .alias "B", 0 0, v0x17baca0_0; -v0x17b95d0_0 .alias "Command", 2 0, v0x17baeb0_0; -v0x17b9680_0 .alias "OrNorXorOut", 0 0, v0x17bafb0_0; -v0x17b97e0_0 .net "XorNor", 0 0, L_0x17df880; 1 drivers -v0x17b9860_0 .net "nXor", 0 0, L_0x17df330; 1 drivers -L_0x17dfa00 .part C4, 2, 1; -L_0x17dff80 .part C4, 0, 1; -S_0x17b8c30 .scope module, "mux0" "TwoInMux" 2 89, 2 8, S_0x17b85f0; - .timescale -9 -12; -L_0x17df560/d .functor NOT 1, L_0x17dfa00, C4<0>, C4<0>, C4<0>; -L_0x17df560 .delay (10000,10000,10000) L_0x17df560/d; -L_0x17df620/d .functor AND 1, L_0x17df420, L_0x17df560, C4<1>, C4<1>; -L_0x17df620 .delay (20000,20000,20000) L_0x17df620/d; -L_0x17df730/d .functor AND 1, L_0x17def10, L_0x17dfa00, C4<1>, C4<1>; -L_0x17df730 .delay (20000,20000,20000) L_0x17df730/d; -L_0x17df880/d .functor OR 1, L_0x17df620, L_0x17df730, C4<0>, C4<0>; -L_0x17df880 .delay (20000,20000,20000) L_0x17df880/d; -v0x17b8d20_0 .net "S", 0 0, L_0x17dfa00; 1 drivers -v0x17b8de0_0 .alias "in0", 0 0, v0x17b9460_0; -v0x17b8e80_0 .alias "in1", 0 0, v0x17b92d0_0; -v0x17b8f20_0 .net "nS", 0 0, L_0x17df560; 1 drivers -v0x17b8fa0_0 .net "out0", 0 0, L_0x17df620; 1 drivers -v0x17b9040_0 .net "out1", 0 0, L_0x17df730; 1 drivers -v0x17b9120_0 .alias "outfinal", 0 0, v0x17b97e0_0; -S_0x17b86e0 .scope module, "mux1" "TwoInMux" 2 90, 2 8, S_0x17b85f0; - .timescale -9 -12; -L_0x17dfaa0/d .functor NOT 1, L_0x17dff80, C4<0>, C4<0>, C4<0>; -L_0x17dfaa0 .delay (10000,10000,10000) L_0x17dfaa0/d; -L_0x17dfb60/d .functor AND 1, L_0x17df880, L_0x17dfaa0, C4<1>, C4<1>; -L_0x17dfb60 .delay (20000,20000,20000) L_0x17dfb60/d; -L_0x17dfcb0/d .functor AND 1, L_0x17df070, L_0x17dff80, C4<1>, C4<1>; -L_0x17dfcb0 .delay (20000,20000,20000) L_0x17dfcb0/d; -L_0x17dfe00/d .functor OR 1, L_0x17dfb60, L_0x17dfcb0, C4<0>, C4<0>; -L_0x17dfe00 .delay (20000,20000,20000) L_0x17dfe00/d; -v0x17b87d0_0 .net "S", 0 0, L_0x17dff80; 1 drivers -v0x17b8870_0 .alias "in0", 0 0, v0x17b97e0_0; -v0x17b8910_0 .alias "in1", 0 0, v0x17b9380_0; -v0x17b89b0_0 .net "nS", 0 0, L_0x17dfaa0; 1 drivers -v0x17b8a30_0 .net "out0", 0 0, L_0x17dfb60; 1 drivers -v0x17b8ad0_0 .net "out1", 0 0, L_0x17dfcb0; 1 drivers -v0x17b8bb0_0 .alias "outfinal", 0 0, v0x17bafb0_0; -S_0x17b7c50 .scope module, "sweetpotato" "AndNand" 2 149, 2 53, S_0x178b140; - .timescale -9 -12; -L_0x17de4c0/d .functor NAND 1, C4, C4, C4<1>, C4<1>; -L_0x17de4c0 .delay (10000,10000,10000) L_0x17de4c0/d; -L_0x17e0260/d .functor NOT 1, L_0x17de4c0, C4<0>, C4<0>, C4<0>; -L_0x17e0260 .delay (10000,10000,10000) L_0x17e0260/d; -v0x17b8270_0 .alias "A", 0 0, v0x17ba940_0; -v0x17b8330_0 .net "AandB", 0 0, L_0x17e0260; 1 drivers -v0x17b83b0_0 .net "AnandB", 0 0, L_0x17de4c0; 1 drivers -v0x17b8430_0 .alias "AndNandOut", 0 0, v0x17bab90_0; -v0x17b84b0_0 .alias "B", 0 0, v0x17baca0_0; -v0x17b8530_0 .alias "Command", 2 0, v0x17baeb0_0; -L_0x17e0830 .part C4, 0, 1; -S_0x17b7d40 .scope module, "potato" "TwoInMux" 2 66, 2 8, S_0x17b7c50; - .timescale -9 -12; -L_0x17e0390/d .functor NOT 1, L_0x17e0830, C4<0>, C4<0>, C4<0>; -L_0x17e0390 .delay (10000,10000,10000) L_0x17e0390/d; -L_0x17e0450/d .functor AND 1, L_0x17e0260, L_0x17e0390, C4<1>, C4<1>; -L_0x17e0450 .delay (20000,20000,20000) L_0x17e0450/d; -L_0x17e0560/d .functor AND 1, L_0x17de4c0, L_0x17e0830, C4<1>, C4<1>; -L_0x17e0560 .delay (20000,20000,20000) L_0x17e0560/d; -L_0x17e06b0/d .functor OR 1, L_0x17e0450, L_0x17e0560, C4<0>, C4<0>; -L_0x17e06b0 .delay (20000,20000,20000) L_0x17e06b0/d; -v0x17b7e30_0 .net "S", 0 0, L_0x17e0830; 1 drivers -v0x17b7ef0_0 .alias "in0", 0 0, v0x17b8330_0; -v0x17b7f90_0 .alias "in1", 0 0, v0x17b83b0_0; -v0x17b8030_0 .net "nS", 0 0, L_0x17e0390; 1 drivers -v0x17b80b0_0 .net "out0", 0 0, L_0x17e0450; 1 drivers -v0x17b8150_0 .net "out1", 0 0, L_0x17e0560; 1 drivers -v0x17b81f0_0 .alias "outfinal", 0 0, v0x17bab90_0; -S_0x17b7290 .scope module, "ZeroMux" "FourInMux" 2 151, 2 29, S_0x178b140; - .timescale -9 -12; -L_0x17e08d0/d .functor NOT 1, L_0x17e10c0, C4<0>, C4<0>, C4<0>; -L_0x17e08d0 .delay (10000,10000,10000) L_0x17e08d0/d; -L_0x17e0990/d .functor NOT 1, L_0x17e11f0, C4<0>, C4<0>, C4<0>; -L_0x17e0990 .delay (10000,10000,10000) L_0x17e0990/d; -L_0x17e0a50/d .functor NAND 1, L_0x17e08d0, L_0x17e0990, L_0x17de9e0, C4<1>; -L_0x17e0a50 .delay (10000,10000,10000) L_0x17e0a50/d; -L_0x17e0b90/d .functor NAND 1, L_0x17e10c0, L_0x17e0990, L_0x17de9e0, C4<1>; -L_0x17e0b90 .delay (10000,10000,10000) L_0x17e0b90/d; -L_0x17e0c80/d .functor NAND 1, L_0x17e08d0, L_0x17e11f0, L_0x17dfe00, C4<1>; -L_0x17e0c80 .delay (10000,10000,10000) L_0x17e0c80/d; -L_0x17e0d70/d .functor NAND 1, L_0x17e10c0, L_0x17e11f0, L_0x17de9e0, C4<1>; -L_0x17e0d70 .delay (10000,10000,10000) L_0x17e0d70/d; -L_0x17e0ee0/d .functor NAND 1, L_0x17e0a50, L_0x17e0b90, L_0x17e0c80, L_0x17e0d70; -L_0x17e0ee0 .delay (10000,10000,10000) L_0x17e0ee0/d; -v0x17b7380_0 .net "S0", 0 0, L_0x17e10c0; 1 drivers -v0x17b7440_0 .net "S1", 0 0, L_0x17e11f0; 1 drivers -v0x17b74e0_0 .alias "in0", 0 0, v0x17baa80_0; -v0x17b7580_0 .alias "in1", 0 0, v0x17baa80_0; -v0x17b7660_0 .alias "in2", 0 0, v0x17bafb0_0; -v0x17b76e0_0 .alias "in3", 0 0, v0x17baa80_0; -v0x17b77b0_0 .net "nS0", 0 0, L_0x17e08d0; 1 drivers -v0x17b7830_0 .net "nS1", 0 0, L_0x17e0990; 1 drivers -v0x17b7900_0 .alias "out", 0 0, v0x17badb0_0; -v0x17b7980_0 .net "out0", 0 0, L_0x17e0a50; 1 drivers -v0x17b7a00_0 .net "out1", 0 0, L_0x17e0b90; 1 drivers -v0x17b7aa0_0 .net "out2", 0 0, L_0x17e0c80; 1 drivers -v0x17b7bb0_0 .net "out3", 0 0, L_0x17e0d70; 1 drivers -S_0x17b6880 .scope module, "OneMux" "FourInMux" 2 152, 2 29, S_0x178b140; - .timescale -9 -12; -L_0x17e1320/d .functor NOT 1, L_0x17e1af0, C4<0>, C4<0>, C4<0>; -L_0x17e1320 .delay (10000,10000,10000) L_0x17e1320/d; -L_0x17e13e0/d .functor NOT 1, L_0x17e1c20, C4<0>, C4<0>, C4<0>; -L_0x17e13e0 .delay (10000,10000,10000) L_0x17e13e0/d; -L_0x17e14a0/d .functor NAND 1, L_0x17e1320, L_0x17e13e0, L_0x17e06b0, C4<1>; -L_0x17e14a0 .delay (10000,10000,10000) L_0x17e14a0/d; -L_0x17e1540/d .functor NAND 1, L_0x17e1af0, L_0x17e13e0, L_0x17e06b0, C4<1>; -L_0x17e1540 .delay (10000,10000,10000) L_0x17e1540/d; -L_0x17e1630/d .functor NAND 1, L_0x17e1320, L_0x17e1c20, L_0x17dfe00, C4<1>; -L_0x17e1630 .delay (10000,10000,10000) L_0x17e1630/d; -L_0x17e1800/d .functor NAND 1, L_0x17e1af0, L_0x17e1c20, L_0x17dfe00, C4<1>; -L_0x17e1800 .delay (10000,10000,10000) L_0x17e1800/d; -L_0x17e1910/d .functor NAND 1, L_0x17e14a0, L_0x17e1540, L_0x17e1630, L_0x17e1800; -L_0x17e1910 .delay (10000,10000,10000) L_0x17e1910/d; -v0x17b6970_0 .net "S0", 0 0, L_0x17e1af0; 1 drivers -v0x17b6a30_0 .net "S1", 0 0, L_0x17e1c20; 1 drivers -v0x17b6ad0_0 .alias "in0", 0 0, v0x17bab90_0; -v0x17b6b70_0 .alias "in1", 0 0, v0x17bab90_0; -v0x17b6c20_0 .alias "in2", 0 0, v0x17bafb0_0; -v0x17b6ca0_0 .alias "in3", 0 0, v0x17bafb0_0; -v0x17b6d60_0 .net "nS0", 0 0, L_0x17e1320; 1 drivers -v0x17b6de0_0 .net "nS1", 0 0, L_0x17e13e0; 1 drivers -v0x17b6eb0_0 .alias "out", 0 0, v0x17bae30_0; -v0x17b6f60_0 .net "out0", 0 0, L_0x17e14a0; 1 drivers -v0x17b7040_0 .net "out1", 0 0, L_0x17e1540; 1 drivers -v0x17b70e0_0 .net "out2", 0 0, L_0x17e1630; 1 drivers -v0x17b71f0_0 .net "out3", 0 0, L_0x17e1800; 1 drivers -S_0x1767cd0 .scope module, "TwoMux" "TwoInMux" 2 153, 2 8, S_0x178b140; - .timescale -9 -12; -L_0x17e1d50/d .functor NOT 1, L_0x17e21a0, C4<0>, C4<0>, C4<0>; -L_0x17e1d50 .delay (10000,10000,10000) L_0x17e1d50/d; -L_0x17e1df0/d .functor AND 1, L_0x17e0ee0, L_0x17e1d50, C4<1>, C4<1>; -L_0x17e1df0 .delay (20000,20000,20000) L_0x17e1df0/d; -L_0x17e1f20/d .functor AND 1, L_0x17e1910, L_0x17e21a0, C4<1>, C4<1>; -L_0x17e1f20 .delay (20000,20000,20000) L_0x17e1f20/d; -L_0x17e2070/d .functor OR 1, L_0x17e1df0, L_0x17e1f20, C4<0>, C4<0>; -L_0x17e2070 .delay (20000,20000,20000) L_0x17e2070/d; -v0x16fba40_0 .net "S", 0 0, L_0x17e21a0; 1 drivers -v0x17b6470_0 .alias "in0", 0 0, v0x17badb0_0; -v0x17b6510_0 .alias "in1", 0 0, v0x17bae30_0; -v0x17b65b0_0 .net "nS", 0 0, L_0x17e1d50; 1 drivers -v0x17b6660_0 .net "out0", 0 0, L_0x17e1df0; 1 drivers -v0x17b6700_0 .net "out1", 0 0, L_0x17e1f20; 1 drivers -v0x17b67e0_0 .alias "outfinal", 0 0, v0x17baf30_0; -S_0x1782ed0 .scope module, "test32Adder" "test32Adder" 3 5; - .timescale -9 -12; -P_0x171d108 .param/l "size" 3 7, +C4<0100>; -v0x17dd890_0 .var "A", 3 0; -RS_0x7ff970b2c6f8/0/0 .resolv tri, L_0x17e33e0, L_0x17e4ad0, L_0x17e6010, L_0x17e7610; -RS_0x7ff970b2c6f8/0/4 .resolv tri, L_0x17f8a00, L_0x17f9e20, L_0x17fb220, L_0x17fc800; -RS_0x7ff970b2c6f8 .resolv tri, RS_0x7ff970b2c6f8/0/0, RS_0x7ff970b2c6f8/0/4, C4, C4; -v0x17dd910_0 .net8 "AddSubSLTSum", 3 0, RS_0x7ff970b2c6f8; 8 drivers -RS_0x7ff970b2b948/0/0 .resolv tri, L_0x17e9460, L_0x17e9e50, L_0x17ea8e0, L_0x17eb340; -RS_0x7ff970b2b948/0/4 .resolv tri, L_0x17fe630, L_0x17ff0a0, L_0x17ffb10, L_0x1800670; -RS_0x7ff970b2b948 .resolv tri, RS_0x7ff970b2b948/0/0, RS_0x7ff970b2b948/0/4, C4, C4; -v0x17dd990_0 .net8 "AndNandOut", 3 0, RS_0x7ff970b2b948; 8 drivers -v0x17dda10_0 .var "B", 3 0; -v0x17dda90_0 .var "Command", 2 0; -RS_0x7ff970b2cb48 .resolv tri, L_0x17f25a0, L_0x17f4f80, L_0x17f7790, L_0x1807460; -v0x17ddb10_0 .net8 "OneBitFinalOut", 3 0, RS_0x7ff970b2cb48; 4 drivers -RS_0x7ff970b2b258/0/0 .resolv tri, L_0x17ec700, L_0x17edc60, L_0x17eef60, L_0x17f0250; -RS_0x7ff970b2b258/0/4 .resolv tri, L_0x18019c0, L_0x1802cc0, L_0x1803fc0, L_0x18052b0; -RS_0x7ff970b2b258 .resolv tri, RS_0x7ff970b2b258/0/0, RS_0x7ff970b2b258/0/4, C4, C4; -v0x17ddb90_0 .net8 "OrNorXorOut", 3 0, RS_0x7ff970b2b258; 8 drivers -RS_0x7ff970b2c7b8 .resolv tri, L_0x17e8c40, L_0x17fdcd0, C4, C4; -v0x17ddc10_0 .net8 "SLTflag", 0 0, RS_0x7ff970b2c7b8; 2 drivers -v0x17ddc90_0 .var "carryin", 3 0; -RS_0x7ff970b2c9f8 .resolv tri, L_0x17e36c0, L_0x17fcb80, C4, C4; -v0x17ddd10_0 .net8 "carryout", 0 0, RS_0x7ff970b2c9f8; 2 drivers -RS_0x7ff970b2ca88 .resolv tri, L_0x17e7f10, L_0x17fcff0, C4, C4; -v0x17ddd90_0 .net8 "overflow", 0 0, RS_0x7ff970b2ca88; 2 drivers -RS_0x7ff970b2cab8/0/0 .resolv tri, L_0x17e3620, L_0x17e4d00, L_0x17e6270, L_0x17e6660; -RS_0x7ff970b2cab8/0/4 .resolv tri, L_0x17f8be0, L_0x17fa050, L_0x17fb480, L_0x17fb870; -RS_0x7ff970b2cab8 .resolv tri, RS_0x7ff970b2cab8/0/0, RS_0x7ff970b2cab8/0/4, C4, C4; -v0x17dde10_0 .net8 "subtract", 3 0, RS_0x7ff970b2cab8; 8 drivers -S_0x17d8120 .scope module, "trial" "AddSubSLT32" 3 25, 2 209, S_0x1782ed0; - .timescale -9 -12; -P_0x17d8218 .param/l "size" 2 232, +C4<0100>; -L_0x17e36c0/d .functor OR 1, L_0x17e7d60, C4<0>, C4<0>, C4<0>; -L_0x17e36c0 .delay (20000,20000,20000) L_0x17e36c0/d; -L_0x17e7f10/d .functor XOR 1, RS_0x7ff970b2c9f8, L_0x17e8040, C4<0>, C4<0>; -L_0x17e7f10 .delay (40000,40000,40000) L_0x17e7f10/d; -L_0x17e7c90/d .functor AND 1, L_0x17e8210, L_0x17e82b0, C4<1>, C4<1>; -L_0x17e7c90 .delay (20000,20000,20000) L_0x17e7c90/d; -L_0x17e80e0/d .functor NOT 1, RS_0x7ff970b2ca88, C4<0>, C4<0>, C4<0>; -L_0x17e80e0 .delay (10000,10000,10000) L_0x17e80e0/d; -L_0x17e84e0/d .functor NOT 1, L_0x17e8540, C4<0>, C4<0>, C4<0>; -L_0x17e84e0 .delay (10000,10000,10000) L_0x17e84e0/d; -L_0x17e3480/d .functor AND 1, L_0x17e80e0, L_0x17e8810, C4<1>, C4<1>; -L_0x17e3480 .delay (20000,20000,20000) L_0x17e3480/d; -L_0x17e83a0/d .functor AND 1, RS_0x7ff970b2ca88, L_0x17e84e0, C4<1>, C4<1>; -L_0x17e83a0 .delay (20000,20000,20000) L_0x17e83a0/d; -L_0x17e8a00/d .functor AND 1, L_0x17e3480, L_0x17e7c90, C4<1>, C4<1>; -L_0x17e8a00 .delay (20000,20000,20000) L_0x17e8a00/d; -L_0x17e8b40/d .functor AND 1, L_0x17e83a0, L_0x17e7c90, C4<1>, C4<1>; -L_0x17e8b40 .delay (20000,20000,20000) L_0x17e8b40/d; -L_0x17e8c40/d .functor OR 1, L_0x17e8a00, L_0x17e8b40, C4<0>, C4<0>; -L_0x17e8c40 .delay (20000,20000,20000) L_0x17e8c40/d; -v0x17dc7b0_0 .net "A", 3 0, v0x17dd890_0; 1 drivers -v0x17dc850_0 .alias "AddSubSLTSum", 3 0, v0x17dd910_0; -v0x17dc8d0_0 .net "B", 3 0, v0x17dda10_0; 1 drivers -RS_0x7ff970b2ec78 .resolv tri, L_0x17e3530, L_0x17e4bc0, L_0x17e6100, L_0x17e7700; -v0x17dc950_0 .net8 "CarryoutWire", 3 0, RS_0x7ff970b2ec78; 4 drivers -v0x17dc9d0_0 .net "Command", 2 0, v0x17dda90_0; 1 drivers -v0x17dca50_0 .net "Res0OF1", 0 0, L_0x17e83a0; 1 drivers -v0x17dcaf0_0 .net "Res1OF0", 0 0, L_0x17e3480; 1 drivers -v0x17dcb90_0 .alias "SLTflag", 0 0, v0x17ddc10_0; -v0x17dccb0_0 .net "SLTflag0", 0 0, L_0x17e8a00; 1 drivers -v0x17dcd50_0 .net "SLTflag1", 0 0, L_0x17e8b40; 1 drivers -v0x17dcdf0_0 .net "SLTon", 0 0, L_0x17e7c90; 1 drivers -v0x17dce90_0 .net *"_s40", 0 0, L_0x17e7d60; 1 drivers -v0x17dcf30_0 .net/s *"_s41", 0 0, C4<0>; 1 drivers -v0x17dcfd0_0 .net *"_s44", 0 0, L_0x17e8040; 1 drivers -v0x17dd0f0_0 .net *"_s46", 0 0, L_0x17e8210; 1 drivers -v0x17dd190_0 .net *"_s48", 0 0, L_0x17e82b0; 1 drivers -v0x17dd050_0 .net *"_s50", 0 0, L_0x17e8540; 1 drivers -v0x17dd2e0_0 .net *"_s52", 0 0, L_0x17e8810; 1 drivers -v0x17dd400_0 .net "carryin", 3 0, v0x17ddc90_0; 1 drivers -v0x17dd480_0 .alias "carryout", 0 0, v0x17ddd10_0; -v0x17dd360_0 .net "nAddSubSLTSum", 0 0, L_0x17e84e0; 1 drivers -v0x17dd5b0_0 .net "nOF", 0 0, L_0x17e80e0; 1 drivers -v0x17dd500_0 .alias "overflow", 0 0, v0x17ddd90_0; -v0x17dd740_0 .alias "subtract", 3 0, v0x17dde10_0; -L_0x17e33e0 .part/pv L_0x17e2f00, 1, 1, 4; -L_0x17e3530 .part/pv L_0x17e3280, 1, 1, 4; -L_0x17e3620 .part/pv L_0x17d1170, 1, 1, 4; -L_0x17e3750 .part v0x17dd890_0, 1, 1; -L_0x17e3900 .part v0x17dda10_0, 1, 1; -L_0x17e3ab0 .part RS_0x7ff970b2ec78, 0, 1; -L_0x17e4ad0 .part/pv L_0x17e4600, 2, 1, 4; -L_0x17e4bc0 .part/pv L_0x17e4970, 2, 1, 4; -L_0x17e4d00 .part/pv L_0x17e4330, 2, 1, 4; -L_0x17e4df0 .part v0x17dd890_0, 2, 1; -L_0x17e4ef0 .part v0x17dda10_0, 2, 1; -L_0x17e5020 .part RS_0x7ff970b2ec78, 1, 1; -L_0x17e6010 .part/pv L_0x17e5b60, 3, 1, 4; -L_0x17e6100 .part/pv L_0x17e5eb0, 3, 1, 4; -L_0x17e6270 .part/pv L_0x17e5890, 3, 1, 4; -L_0x17e6360 .part v0x17dd890_0, 3, 1; -L_0x17e6490 .part v0x17dda10_0, 3, 1; -L_0x17e65c0 .part RS_0x7ff970b2ec78, 2, 1; -L_0x17e7610 .part/pv L_0x17e7160, 0, 1, 4; -L_0x17e7700 .part/pv L_0x17e74b0, 0, 1, 4; -L_0x17e6660 .part/pv L_0x17e6e90, 0, 1, 4; -L_0x17e78f0 .part v0x17dd890_0, 0, 1; -L_0x17e77f0 .part v0x17dda10_0, 0, 1; -L_0x17e7ae0 .part RS_0x7ff970b2cab8, 0, 1; -L_0x17e7d60 .part RS_0x7ff970b2ec78, 3, 1; -L_0x17e8040 .part RS_0x7ff970b2ec78, 2, 1; -L_0x17e8210 .part v0x17dda90_0, 1, 1; -L_0x17e82b0 .part RS_0x7ff970b2cab8, 0, 1; -L_0x17e8540 .part RS_0x7ff970b2c6f8, 3, 1; -L_0x17e8810 .part RS_0x7ff970b2c6f8, 3, 1; -S_0x17db7a0 .scope module, "attempt2" "MiddleAddSubSLT" 2 229, 2 95, S_0x17d8120; - .timescale -9 -12; -L_0x17e6400/d .functor NOT 1, L_0x17e77f0, C4<0>, C4<0>, C4<0>; -L_0x17e6400 .delay (10000,10000,10000) L_0x17e6400/d; -L_0x17e6d30/d .functor NOT 1, L_0x17e6df0, C4<0>, C4<0>, C4<0>; -L_0x17e6d30 .delay (10000,10000,10000) L_0x17e6d30/d; -L_0x17e6e90/d .functor AND 1, L_0x17e6fd0, L_0x17e6d30, C4<1>, C4<1>; -L_0x17e6e90 .delay (20000,20000,20000) L_0x17e6e90/d; -L_0x17e7070/d .functor XOR 1, L_0x17e78f0, L_0x17e6ac0, C4<0>, C4<0>; -L_0x17e7070 .delay (40000,40000,40000) L_0x17e7070/d; -L_0x17e7160/d .functor XOR 1, L_0x17e7070, L_0x17e7ae0, C4<0>, C4<0>; -L_0x17e7160 .delay (40000,40000,40000) L_0x17e7160/d; -L_0x17e7250/d .functor AND 1, L_0x17e78f0, L_0x17e6ac0, C4<1>, C4<1>; -L_0x17e7250 .delay (20000,20000,20000) L_0x17e7250/d; -L_0x17e73c0/d .functor AND 1, L_0x17e7070, L_0x17e7ae0, C4<1>, C4<1>; -L_0x17e73c0 .delay (20000,20000,20000) L_0x17e73c0/d; -L_0x17e74b0/d .functor OR 1, L_0x17e7250, L_0x17e73c0, C4<0>, C4<0>; -L_0x17e74b0 .delay (20000,20000,20000) L_0x17e74b0/d; -v0x17dbe10_0 .net "A", 0 0, L_0x17e78f0; 1 drivers -v0x17dbed0_0 .net "AandB", 0 0, L_0x17e7250; 1 drivers -v0x17dbf70_0 .net "AddSubSLTSum", 0 0, L_0x17e7160; 1 drivers -v0x17dc010_0 .net "AxorB", 0 0, L_0x17e7070; 1 drivers -v0x17dc090_0 .net "B", 0 0, L_0x17e77f0; 1 drivers -v0x17dc140_0 .net "BornB", 0 0, L_0x17e6ac0; 1 drivers -v0x17dc200_0 .net "CINandAxorB", 0 0, L_0x17e73c0; 1 drivers -v0x17dc280_0 .alias "Command", 2 0, v0x17dc9d0_0; -v0x17dc300_0 .net *"_s3", 0 0, L_0x17e6df0; 1 drivers -v0x17dc380_0 .net *"_s5", 0 0, L_0x17e6fd0; 1 drivers -v0x17dc420_0 .net "carryin", 0 0, L_0x17e7ae0; 1 drivers -v0x17dc4c0_0 .net "carryout", 0 0, L_0x17e74b0; 1 drivers -v0x17dc560_0 .net "nB", 0 0, L_0x17e6400; 1 drivers -v0x17dc610_0 .net "nCmd2", 0 0, L_0x17e6d30; 1 drivers -v0x17dc710_0 .net "subtract", 0 0, L_0x17e6e90; 1 drivers -L_0x17e6c90 .part v0x17dda90_0, 0, 1; -L_0x17e6df0 .part v0x17dda90_0, 2, 1; -L_0x17e6fd0 .part v0x17dda90_0, 0, 1; -S_0x17db890 .scope module, "mux0" "TwoInMux" 2 111, 2 8, S_0x17db7a0; - .timescale -9 -12; -L_0x17e67e0/d .functor NOT 1, L_0x17e6c90, C4<0>, C4<0>, C4<0>; -L_0x17e67e0 .delay (10000,10000,10000) L_0x17e67e0/d; -L_0x17e68a0/d .functor AND 1, L_0x17e77f0, L_0x17e67e0, C4<1>, C4<1>; -L_0x17e68a0 .delay (20000,20000,20000) L_0x17e68a0/d; -L_0x17e69b0/d .functor AND 1, L_0x17e6400, L_0x17e6c90, C4<1>, C4<1>; -L_0x17e69b0 .delay (20000,20000,20000) L_0x17e69b0/d; -L_0x17e6ac0/d .functor OR 1, L_0x17e68a0, L_0x17e69b0, C4<0>, C4<0>; -L_0x17e6ac0 .delay (20000,20000,20000) L_0x17e6ac0/d; -v0x17db980_0 .net "S", 0 0, L_0x17e6c90; 1 drivers -v0x17dba40_0 .alias "in0", 0 0, v0x17dc090_0; -v0x17dbae0_0 .alias "in1", 0 0, v0x17dc560_0; -v0x17dbb80_0 .net "nS", 0 0, L_0x17e67e0; 1 drivers -v0x17dbc30_0 .net "out0", 0 0, L_0x17e68a0; 1 drivers -v0x17dbcd0_0 .net "out1", 0 0, L_0x17e69b0; 1 drivers -v0x17dbd70_0 .alias "outfinal", 0 0, v0x17dc140_0; -S_0x17da600 .scope generate, "addbits[1]" "addbits[1]" 2 234, 2 234, S_0x17d8120; - .timescale -9 -12; -P_0x17da018 .param/l "i" 2 234, +C4<01>; -S_0x17da770 .scope module, "attempt" "MiddleAddSubSLT" 2 236, 2 95, S_0x17da600; - .timescale -9 -12; -L_0x17e2240/d .functor NOT 1, L_0x17e3900, C4<0>, C4<0>, C4<0>; -L_0x17e2240 .delay (10000,10000,10000) L_0x17e2240/d; -L_0x17cae70/d .functor NOT 1, L_0x17d10d0, C4<0>, C4<0>, C4<0>; -L_0x17cae70 .delay (10000,10000,10000) L_0x17cae70/d; -L_0x17d1170/d .functor AND 1, L_0x17e2d70, L_0x17cae70, C4<1>, C4<1>; -L_0x17d1170 .delay (20000,20000,20000) L_0x17d1170/d; -L_0x17e2e10/d .functor XOR 1, L_0x17e3750, L_0x17e26a0, C4<0>, C4<0>; -L_0x17e2e10 .delay (40000,40000,40000) L_0x17e2e10/d; -L_0x17e2f00/d .functor XOR 1, L_0x17e2e10, L_0x17e3ab0, C4<0>, C4<0>; -L_0x17e2f00 .delay (40000,40000,40000) L_0x17e2f00/d; -L_0x17e2ff0/d .functor AND 1, L_0x17e3750, L_0x17e26a0, C4<1>, C4<1>; -L_0x17e2ff0 .delay (20000,20000,20000) L_0x17e2ff0/d; -L_0x17e3190/d .functor AND 1, L_0x17e2e10, L_0x17e3ab0, C4<1>, C4<1>; -L_0x17e3190 .delay (20000,20000,20000) L_0x17e3190/d; -L_0x17e3280/d .functor OR 1, L_0x17e2ff0, L_0x17e3190, C4<0>, C4<0>; -L_0x17e3280 .delay (20000,20000,20000) L_0x17e3280/d; -v0x17dae00_0 .net "A", 0 0, L_0x17e3750; 1 drivers -v0x17daec0_0 .net "AandB", 0 0, L_0x17e2ff0; 1 drivers -v0x17daf60_0 .net "AddSubSLTSum", 0 0, L_0x17e2f00; 1 drivers -v0x17db000_0 .net "AxorB", 0 0, L_0x17e2e10; 1 drivers -v0x17db080_0 .net "B", 0 0, L_0x17e3900; 1 drivers -v0x17db130_0 .net "BornB", 0 0, L_0x17e26a0; 1 drivers -v0x17db1f0_0 .net "CINandAxorB", 0 0, L_0x17e3190; 1 drivers -v0x17db270_0 .alias "Command", 2 0, v0x17dc9d0_0; -v0x17db2f0_0 .net *"_s3", 0 0, L_0x17d10d0; 1 drivers -v0x17db370_0 .net *"_s5", 0 0, L_0x17e2d70; 1 drivers -v0x17db410_0 .net "carryin", 0 0, L_0x17e3ab0; 1 drivers -v0x17db4b0_0 .net "carryout", 0 0, L_0x17e3280; 1 drivers -v0x17db550_0 .net "nB", 0 0, L_0x17e2240; 1 drivers -v0x17db600_0 .net "nCmd2", 0 0, L_0x17cae70; 1 drivers -v0x17db700_0 .net "subtract", 0 0, L_0x17d1170; 1 drivers -L_0x17e2870 .part v0x17dda90_0, 0, 1; -L_0x17d10d0 .part v0x17dda90_0, 2, 1; -L_0x17e2d70 .part v0x17dda90_0, 0, 1; -S_0x17da860 .scope module, "mux0" "TwoInMux" 2 111, 2 8, S_0x17da770; - .timescale -9 -12; -L_0x17e23c0/d .functor NOT 1, L_0x17e2870, C4<0>, C4<0>, C4<0>; -L_0x17e23c0 .delay (10000,10000,10000) L_0x17e23c0/d; -L_0x17e2480/d .functor AND 1, L_0x17e3900, L_0x17e23c0, C4<1>, C4<1>; -L_0x17e2480 .delay (20000,20000,20000) L_0x17e2480/d; -L_0x17e2590/d .functor AND 1, L_0x17e2240, L_0x17e2870, C4<1>, C4<1>; -L_0x17e2590 .delay (20000,20000,20000) L_0x17e2590/d; -L_0x17e26a0/d .functor OR 1, L_0x17e2480, L_0x17e2590, C4<0>, C4<0>; -L_0x17e26a0 .delay (20000,20000,20000) L_0x17e26a0/d; -v0x17da950_0 .net "S", 0 0, L_0x17e2870; 1 drivers -v0x17da9f0_0 .alias "in0", 0 0, v0x17db080_0; -v0x17daa90_0 .alias "in1", 0 0, v0x17db550_0; -v0x17dab30_0 .net "nS", 0 0, L_0x17e23c0; 1 drivers -v0x17dabe0_0 .net "out0", 0 0, L_0x17e2480; 1 drivers -v0x17dac80_0 .net "out1", 0 0, L_0x17e2590; 1 drivers -v0x17dad60_0 .alias "outfinal", 0 0, v0x17db130_0; -S_0x17d9460 .scope generate, "addbits[2]" "addbits[2]" 2 234, 2 234, S_0x17d8120; - .timescale -9 -12; -P_0x17d8e18 .param/l "i" 2 234, +C4<010>; -S_0x17d95d0 .scope module, "attempt" "MiddleAddSubSLT" 2 236, 2 95, S_0x17d9460; - .timescale -9 -12; -L_0x17d4ed0/d .functor NOT 1, L_0x17e4ef0, C4<0>, C4<0>, C4<0>; -L_0x17d4ed0 .delay (10000,10000,10000) L_0x17d4ed0/d; -L_0x17e41d0/d .functor NOT 1, L_0x17e4290, C4<0>, C4<0>, C4<0>; -L_0x17e41d0 .delay (10000,10000,10000) L_0x17e41d0/d; -L_0x17e4330/d .functor AND 1, L_0x17e4470, L_0x17e41d0, C4<1>, C4<1>; -L_0x17e4330 .delay (20000,20000,20000) L_0x17e4330/d; -L_0x17e4510/d .functor XOR 1, L_0x17e4df0, L_0x17e3f60, C4<0>, C4<0>; -L_0x17e4510 .delay (40000,40000,40000) L_0x17e4510/d; -L_0x17e4600/d .functor XOR 1, L_0x17e4510, L_0x17e5020, C4<0>, C4<0>; -L_0x17e4600 .delay (40000,40000,40000) L_0x17e4600/d; -L_0x17e46f0/d .functor AND 1, L_0x17e4df0, L_0x17e3f60, C4<1>, C4<1>; -L_0x17e46f0 .delay (20000,20000,20000) L_0x17e46f0/d; -L_0x17e4860/d .functor AND 1, L_0x17e4510, L_0x17e5020, C4<1>, C4<1>; -L_0x17e4860 .delay (20000,20000,20000) L_0x17e4860/d; -L_0x17e4970/d .functor OR 1, L_0x17e46f0, L_0x17e4860, C4<0>, C4<0>; -L_0x17e4970 .delay (20000,20000,20000) L_0x17e4970/d; -v0x17d9c60_0 .net "A", 0 0, L_0x17e4df0; 1 drivers -v0x17d9d20_0 .net "AandB", 0 0, L_0x17e46f0; 1 drivers -v0x17d9dc0_0 .net "AddSubSLTSum", 0 0, L_0x17e4600; 1 drivers -v0x17d9e60_0 .net "AxorB", 0 0, L_0x17e4510; 1 drivers -v0x17d9ee0_0 .net "B", 0 0, L_0x17e4ef0; 1 drivers -v0x17d9f90_0 .net "BornB", 0 0, L_0x17e3f60; 1 drivers -v0x17da050_0 .net "CINandAxorB", 0 0, L_0x17e4860; 1 drivers -v0x17da0d0_0 .alias "Command", 2 0, v0x17dc9d0_0; -v0x17da150_0 .net *"_s3", 0 0, L_0x17e4290; 1 drivers -v0x17da1d0_0 .net *"_s5", 0 0, L_0x17e4470; 1 drivers -v0x17da270_0 .net "carryin", 0 0, L_0x17e5020; 1 drivers -v0x17da310_0 .net "carryout", 0 0, L_0x17e4970; 1 drivers -v0x17da3b0_0 .net "nB", 0 0, L_0x17d4ed0; 1 drivers -v0x17da460_0 .net "nCmd2", 0 0, L_0x17e41d0; 1 drivers -v0x17da560_0 .net "subtract", 0 0, L_0x17e4330; 1 drivers -L_0x17e4130 .part v0x17dda90_0, 0, 1; -L_0x17e4290 .part v0x17dda90_0, 2, 1; -L_0x17e4470 .part v0x17dda90_0, 0, 1; -S_0x17d96c0 .scope module, "mux0" "TwoInMux" 2 111, 2 8, S_0x17d95d0; - .timescale -9 -12; -L_0x17e3c80/d .functor NOT 1, L_0x17e4130, C4<0>, C4<0>, C4<0>; -L_0x17e3c80 .delay (10000,10000,10000) L_0x17e3c80/d; -L_0x17e3d40/d .functor AND 1, L_0x17e4ef0, L_0x17e3c80, C4<1>, C4<1>; -L_0x17e3d40 .delay (20000,20000,20000) L_0x17e3d40/d; -L_0x17e3e50/d .functor AND 1, L_0x17d4ed0, L_0x17e4130, C4<1>, C4<1>; -L_0x17e3e50 .delay (20000,20000,20000) L_0x17e3e50/d; -L_0x17e3f60/d .functor OR 1, L_0x17e3d40, L_0x17e3e50, C4<0>, C4<0>; -L_0x17e3f60 .delay (20000,20000,20000) L_0x17e3f60/d; -v0x17d97b0_0 .net "S", 0 0, L_0x17e4130; 1 drivers -v0x17d9850_0 .alias "in0", 0 0, v0x17d9ee0_0; -v0x17d98f0_0 .alias "in1", 0 0, v0x17da3b0_0; -v0x17d9990_0 .net "nS", 0 0, L_0x17e3c80; 1 drivers -v0x17d9a40_0 .net "out0", 0 0, L_0x17e3d40; 1 drivers -v0x17d9ae0_0 .net "out1", 0 0, L_0x17e3e50; 1 drivers -v0x17d9bc0_0 .alias "outfinal", 0 0, v0x17d9f90_0; -S_0x17d8290 .scope generate, "addbits[3]" "addbits[3]" 2 234, 2 234, S_0x17d8120; - .timescale -9 -12; -P_0x17d8388 .param/l "i" 2 234, +C4<011>; -S_0x17d8400 .scope module, "attempt" "MiddleAddSubSLT" 2 236, 2 95, S_0x17d8290; - .timescale -9 -12; -L_0x17e4e90/d .functor NOT 1, L_0x17e6490, C4<0>, C4<0>, C4<0>; -L_0x17e4e90 .delay (10000,10000,10000) L_0x17e4e90/d; -L_0x17e5730/d .functor NOT 1, L_0x17e57f0, C4<0>, C4<0>, C4<0>; -L_0x17e5730 .delay (10000,10000,10000) L_0x17e5730/d; -L_0x17e5890/d .functor AND 1, L_0x17e59d0, L_0x17e5730, C4<1>, C4<1>; -L_0x17e5890 .delay (20000,20000,20000) L_0x17e5890/d; -L_0x17e5a70/d .functor XOR 1, L_0x17e6360, L_0x17e54c0, C4<0>, C4<0>; -L_0x17e5a70 .delay (40000,40000,40000) L_0x17e5a70/d; -L_0x17e5b60/d .functor XOR 1, L_0x17e5a70, L_0x17e65c0, C4<0>, C4<0>; -L_0x17e5b60 .delay (40000,40000,40000) L_0x17e5b60/d; -L_0x17e5c50/d .functor AND 1, L_0x17e6360, L_0x17e54c0, C4<1>, C4<1>; -L_0x17e5c50 .delay (20000,20000,20000) L_0x17e5c50/d; -L_0x17e5dc0/d .functor AND 1, L_0x17e5a70, L_0x17e65c0, C4<1>, C4<1>; -L_0x17e5dc0 .delay (20000,20000,20000) L_0x17e5dc0/d; -L_0x17e5eb0/d .functor OR 1, L_0x17e5c50, L_0x17e5dc0, C4<0>, C4<0>; -L_0x17e5eb0 .delay (20000,20000,20000) L_0x17e5eb0/d; -v0x17d8a60_0 .net "A", 0 0, L_0x17e6360; 1 drivers -v0x17d8b20_0 .net "AandB", 0 0, L_0x17e5c50; 1 drivers -v0x17d8bc0_0 .net "AddSubSLTSum", 0 0, L_0x17e5b60; 1 drivers -v0x17d8c60_0 .net "AxorB", 0 0, L_0x17e5a70; 1 drivers -v0x17d8ce0_0 .net "B", 0 0, L_0x17e6490; 1 drivers -v0x17d8d90_0 .net "BornB", 0 0, L_0x17e54c0; 1 drivers -v0x17d8e50_0 .net "CINandAxorB", 0 0, L_0x17e5dc0; 1 drivers -v0x17d8ed0_0 .alias "Command", 2 0, v0x17dc9d0_0; -v0x17d8f50_0 .net *"_s3", 0 0, L_0x17e57f0; 1 drivers -v0x17d8fd0_0 .net *"_s5", 0 0, L_0x17e59d0; 1 drivers -v0x17d90d0_0 .net "carryin", 0 0, L_0x17e65c0; 1 drivers -v0x17d9170_0 .net "carryout", 0 0, L_0x17e5eb0; 1 drivers -v0x17d9210_0 .net "nB", 0 0, L_0x17e4e90; 1 drivers -v0x17d92c0_0 .net "nCmd2", 0 0, L_0x17e5730; 1 drivers -v0x17d93c0_0 .net "subtract", 0 0, L_0x17e5890; 1 drivers -L_0x17e5690 .part v0x17dda90_0, 0, 1; -L_0x17e57f0 .part v0x17dda90_0, 2, 1; -L_0x17e59d0 .part v0x17dda90_0, 0, 1; -S_0x17d84f0 .scope module, "mux0" "TwoInMux" 2 111, 2 8, S_0x17d8400; - .timescale -9 -12; -L_0x17e5220/d .functor NOT 1, L_0x17e5690, C4<0>, C4<0>, C4<0>; -L_0x17e5220 .delay (10000,10000,10000) L_0x17e5220/d; -L_0x17e52a0/d .functor AND 1, L_0x17e6490, L_0x17e5220, C4<1>, C4<1>; -L_0x17e52a0 .delay (20000,20000,20000) L_0x17e52a0/d; -L_0x17e53b0/d .functor AND 1, L_0x17e4e90, L_0x17e5690, C4<1>, C4<1>; -L_0x17e53b0 .delay (20000,20000,20000) L_0x17e53b0/d; -L_0x17e54c0/d .functor OR 1, L_0x17e52a0, L_0x17e53b0, C4<0>, C4<0>; -L_0x17e54c0 .delay (20000,20000,20000) L_0x17e54c0/d; -v0x17d85e0_0 .net "S", 0 0, L_0x17e5690; 1 drivers -v0x17d8680_0 .alias "in0", 0 0, v0x17d8ce0_0; -v0x17d8720_0 .alias "in1", 0 0, v0x17d9210_0; -v0x17d87c0_0 .net "nS", 0 0, L_0x17e5220; 1 drivers -v0x17d8840_0 .net "out0", 0 0, L_0x17e52a0; 1 drivers -v0x17d88e0_0 .net "out1", 0 0, L_0x17e53b0; 1 drivers -v0x17d89c0_0 .alias "outfinal", 0 0, v0x17d8d90_0; -S_0x17d5060 .scope module, "trial1" "AndNand32" 3 27, 2 157, S_0x1782ed0; - .timescale -9 -12; -P_0x17d4a58 .param/l "size" 2 165, +C4<0100>; -v0x17d7f20_0 .alias "A", 3 0, v0x17dc7b0_0; -v0x17d7fa0_0 .alias "AndNandOut", 3 0, v0x17dd990_0; -v0x17d8020_0 .alias "B", 3 0, v0x17dc8d0_0; -v0x17d80a0_0 .alias "Command", 2 0, v0x17dc9d0_0; -L_0x17e9460 .part/pv L_0x17e9230, 1, 1, 4; -L_0x17e9590 .part v0x17dd890_0, 1, 1; -L_0x17e9630 .part v0x17dda10_0, 1, 1; -L_0x17e9e50 .part/pv L_0x17e9be0, 2, 1, 4; -L_0x17e9ef0 .part v0x17dd890_0, 2, 1; -L_0x17e9f90 .part v0x17dda10_0, 2, 1; -L_0x17ea8e0 .part/pv L_0x17ea670, 3, 1, 4; -L_0x17ea980 .part v0x17dd890_0, 3, 1; -L_0x17eaa70 .part v0x17dda10_0, 3, 1; -L_0x17eb340 .part/pv L_0x17eb0d0, 0, 1, 4; -L_0x17eb440 .part v0x17dd890_0, 0, 1; -L_0x17eb4e0 .part v0x17dda10_0, 0, 1; -S_0x17d74f0 .scope module, "attempt2" "AndNand" 2 170, 2 53, S_0x17d5060; - .timescale -9 -12; -L_0x17eab60/d .functor NAND 1, L_0x17eb440, L_0x17eb4e0, C4<1>, C4<1>; -L_0x17eab60 .delay (10000,10000,10000) L_0x17eab60/d; -L_0x17eac80/d .functor NOT 1, L_0x17eab60, C4<0>, C4<0>, C4<0>; -L_0x17eac80 .delay (10000,10000,10000) L_0x17eac80/d; -v0x17d7b10_0 .net "A", 0 0, L_0x17eb440; 1 drivers -v0x17d7bd0_0 .net "AandB", 0 0, L_0x17eac80; 1 drivers -v0x17d7c50_0 .net "AnandB", 0 0, L_0x17eab60; 1 drivers -v0x17d7d00_0 .net "AndNandOut", 0 0, L_0x17eb0d0; 1 drivers -v0x17d7de0_0 .net "B", 0 0, L_0x17eb4e0; 1 drivers -v0x17d7e60_0 .alias "Command", 2 0, v0x17dc9d0_0; -L_0x17eb2a0 .part v0x17dda90_0, 0, 1; -S_0x17d75e0 .scope module, "potato" "TwoInMux" 2 66, 2 8, S_0x17d74f0; - .timescale -9 -12; -L_0x17eadb0/d .functor NOT 1, L_0x17eb2a0, C4<0>, C4<0>, C4<0>; -L_0x17eadb0 .delay (10000,10000,10000) L_0x17eadb0/d; -L_0x17eae70/d .functor AND 1, L_0x17eac80, L_0x17eadb0, C4<1>, C4<1>; -L_0x17eae70 .delay (20000,20000,20000) L_0x17eae70/d; -L_0x17eaf80/d .functor AND 1, L_0x17eab60, L_0x17eb2a0, C4<1>, C4<1>; -L_0x17eaf80 .delay (20000,20000,20000) L_0x17eaf80/d; -L_0x17eb0d0/d .functor OR 1, L_0x17eae70, L_0x17eaf80, C4<0>, C4<0>; -L_0x17eb0d0 .delay (20000,20000,20000) L_0x17eb0d0/d; -v0x17d76d0_0 .net "S", 0 0, L_0x17eb2a0; 1 drivers -v0x17d7750_0 .alias "in0", 0 0, v0x17d7bd0_0; -v0x17d77d0_0 .alias "in1", 0 0, v0x17d7c50_0; -v0x17d7870_0 .net "nS", 0 0, L_0x17eadb0; 1 drivers -v0x17d78f0_0 .net "out0", 0 0, L_0x17eae70; 1 drivers -v0x17d7990_0 .net "out1", 0 0, L_0x17eaf80; 1 drivers -v0x17d7a70_0 .alias "outfinal", 0 0, v0x17d7d00_0; -S_0x17d6930 .scope generate, "andbits[1]" "andbits[1]" 2 173, 2 173, S_0x17d5060; - .timescale -9 -12; -P_0x17d6a28 .param/l "i" 2 173, +C4<01>; -S_0x17d6aa0 .scope module, "attempt" "AndNand" 2 175, 2 53, S_0x17d6930; - .timescale -9 -12; -L_0x17e8e40/d .functor NAND 1, L_0x17e9590, L_0x17e9630, C4<1>, C4<1>; -L_0x17e8e40 .delay (10000,10000,10000) L_0x17e8e40/d; -L_0x17e8f00/d .functor NOT 1, L_0x17e8e40, C4<0>, C4<0>, C4<0>; -L_0x17e8f00 .delay (10000,10000,10000) L_0x17e8f00/d; -v0x17d70e0_0 .net "A", 0 0, L_0x17e9590; 1 drivers -v0x17d71a0_0 .net "AandB", 0 0, L_0x17e8f00; 1 drivers -v0x17d7220_0 .net "AnandB", 0 0, L_0x17e8e40; 1 drivers -v0x17d72d0_0 .net "AndNandOut", 0 0, L_0x17e9230; 1 drivers -v0x17d73b0_0 .net "B", 0 0, L_0x17e9630; 1 drivers -v0x17d7430_0 .alias "Command", 2 0, v0x17dc9d0_0; -L_0x17e93c0 .part v0x17dda90_0, 0, 1; -S_0x17d6b90 .scope module, "potato" "TwoInMux" 2 66, 2 8, S_0x17d6aa0; - .timescale -9 -12; -L_0x17e61f0/d .functor NOT 1, L_0x17e93c0, C4<0>, C4<0>, C4<0>; -L_0x17e61f0 .delay (10000,10000,10000) L_0x17e61f0/d; -L_0x17e9010/d .functor AND 1, L_0x17e8f00, L_0x17e61f0, C4<1>, C4<1>; -L_0x17e9010 .delay (20000,20000,20000) L_0x17e9010/d; -L_0x17e9100/d .functor AND 1, L_0x17e8e40, L_0x17e93c0, C4<1>, C4<1>; -L_0x17e9100 .delay (20000,20000,20000) L_0x17e9100/d; -L_0x17e9230/d .functor OR 1, L_0x17e9010, L_0x17e9100, C4<0>, C4<0>; -L_0x17e9230 .delay (20000,20000,20000) L_0x17e9230/d; -v0x17d6c80_0 .net "S", 0 0, L_0x17e93c0; 1 drivers -v0x17d6d00_0 .alias "in0", 0 0, v0x17d71a0_0; -v0x17d6da0_0 .alias "in1", 0 0, v0x17d7220_0; -v0x17d6e40_0 .net "nS", 0 0, L_0x17e61f0; 1 drivers -v0x17d6ec0_0 .net "out0", 0 0, L_0x17e9010; 1 drivers -v0x17d6f60_0 .net "out1", 0 0, L_0x17e9100; 1 drivers -v0x17d7040_0 .alias "outfinal", 0 0, v0x17d72d0_0; -S_0x17d5d70 .scope generate, "andbits[2]" "andbits[2]" 2 173, 2 173, S_0x17d5060; - .timescale -9 -12; -P_0x17d5e68 .param/l "i" 2 173, +C4<010>; -S_0x17d5ee0 .scope module, "attempt" "AndNand" 2 175, 2 53, S_0x17d5d70; - .timescale -9 -12; -L_0x17e96d0/d .functor NAND 1, L_0x17e9ef0, L_0x17e9f90, C4<1>, C4<1>; -L_0x17e96d0 .delay (10000,10000,10000) L_0x17e96d0/d; -L_0x17e9810/d .functor NOT 1, L_0x17e96d0, C4<0>, C4<0>, C4<0>; -L_0x17e9810 .delay (10000,10000,10000) L_0x17e9810/d; -v0x17d6520_0 .net "A", 0 0, L_0x17e9ef0; 1 drivers -v0x17d65e0_0 .net "AandB", 0 0, L_0x17e9810; 1 drivers -v0x17d6660_0 .net "AnandB", 0 0, L_0x17e96d0; 1 drivers -v0x17d6710_0 .net "AndNandOut", 0 0, L_0x17e9be0; 1 drivers -v0x17d67f0_0 .net "B", 0 0, L_0x17e9f90; 1 drivers -v0x17d6870_0 .alias "Command", 2 0, v0x17dc9d0_0; -L_0x17e9db0 .part v0x17dda90_0, 0, 1; -S_0x17d5fd0 .scope module, "potato" "TwoInMux" 2 66, 2 8, S_0x17d5ee0; - .timescale -9 -12; -L_0x17e9900/d .functor NOT 1, L_0x17e9db0, C4<0>, C4<0>, C4<0>; -L_0x17e9900 .delay (10000,10000,10000) L_0x17e9900/d; -L_0x17e99a0/d .functor AND 1, L_0x17e9810, L_0x17e9900, C4<1>, C4<1>; -L_0x17e99a0 .delay (20000,20000,20000) L_0x17e99a0/d; -L_0x17e9a90/d .functor AND 1, L_0x17e96d0, L_0x17e9db0, C4<1>, C4<1>; -L_0x17e9a90 .delay (20000,20000,20000) L_0x17e9a90/d; -L_0x17e9be0/d .functor OR 1, L_0x17e99a0, L_0x17e9a90, C4<0>, C4<0>; -L_0x17e9be0 .delay (20000,20000,20000) L_0x17e9be0/d; -v0x17d60c0_0 .net "S", 0 0, L_0x17e9db0; 1 drivers -v0x17d6140_0 .alias "in0", 0 0, v0x17d65e0_0; -v0x17d61e0_0 .alias "in1", 0 0, v0x17d6660_0; -v0x17d6280_0 .net "nS", 0 0, L_0x17e9900; 1 drivers -v0x17d6300_0 .net "out0", 0 0, L_0x17e99a0; 1 drivers -v0x17d63a0_0 .net "out1", 0 0, L_0x17e9a90; 1 drivers -v0x17d6480_0 .alias "outfinal", 0 0, v0x17d6710_0; -S_0x17d5190 .scope generate, "andbits[3]" "andbits[3]" 2 173, 2 173, S_0x17d5060; - .timescale -9 -12; -P_0x17d5288 .param/l "i" 2 173, +C4<011>; -S_0x17d5300 .scope module, "attempt" "AndNand" 2 175, 2 53, S_0x17d5190; - .timescale -9 -12; -L_0x17ea0c0/d .functor NAND 1, L_0x17ea980, L_0x17eaa70, C4<1>, C4<1>; -L_0x17ea0c0 .delay (10000,10000,10000) L_0x17ea0c0/d; -L_0x17ea220/d .functor NOT 1, L_0x17ea0c0, C4<0>, C4<0>, C4<0>; -L_0x17ea220 .delay (10000,10000,10000) L_0x17ea220/d; -v0x17d5960_0 .net "A", 0 0, L_0x17ea980; 1 drivers -v0x17d5a20_0 .net "AandB", 0 0, L_0x17ea220; 1 drivers -v0x17d5aa0_0 .net "AnandB", 0 0, L_0x17ea0c0; 1 drivers -v0x17d5b50_0 .net "AndNandOut", 0 0, L_0x17ea670; 1 drivers -v0x17d5c30_0 .net "B", 0 0, L_0x17eaa70; 1 drivers -v0x17d5cb0_0 .alias "Command", 2 0, v0x17dc9d0_0; -L_0x17ea840 .part v0x17dda90_0, 0, 1; -S_0x17d53f0 .scope module, "potato" "TwoInMux" 2 66, 2 8, S_0x17d5300; - .timescale -9 -12; -L_0x17ea350/d .functor NOT 1, L_0x17ea840, C4<0>, C4<0>, C4<0>; -L_0x17ea350 .delay (10000,10000,10000) L_0x17ea350/d; -L_0x17ea410/d .functor AND 1, L_0x17ea220, L_0x17ea350, C4<1>, C4<1>; -L_0x17ea410 .delay (20000,20000,20000) L_0x17ea410/d; -L_0x17ea520/d .functor AND 1, L_0x17ea0c0, L_0x17ea840, C4<1>, C4<1>; -L_0x17ea520 .delay (20000,20000,20000) L_0x17ea520/d; -L_0x17ea670/d .functor OR 1, L_0x17ea410, L_0x17ea520, C4<0>, C4<0>; -L_0x17ea670 .delay (20000,20000,20000) L_0x17ea670/d; -v0x17d54e0_0 .net "S", 0 0, L_0x17ea840; 1 drivers -v0x17d5580_0 .alias "in0", 0 0, v0x17d5a20_0; -v0x17d5620_0 .alias "in1", 0 0, v0x17d5aa0_0; -v0x17d56c0_0 .net "nS", 0 0, L_0x17ea350; 1 drivers -v0x17d5740_0 .net "out0", 0 0, L_0x17ea410; 1 drivers -v0x17d57e0_0 .net "out1", 0 0, L_0x17ea520; 1 drivers -v0x17d58c0_0 .alias "outfinal", 0 0, v0x17d5b50_0; -S_0x17cfd60 .scope module, "trial2" "OrNorXor32" 3 29, 2 180, S_0x1782ed0; - .timescale -9 -12; -P_0x17cdeb8 .param/l "size" 2 187, +C4<0100>; -v0x17d4d40_0 .alias "A", 3 0, v0x17dc7b0_0; -v0x17d4e50_0 .alias "B", 3 0, v0x17dc8d0_0; -v0x17d4f60_0 .alias "Command", 2 0, v0x17dc9d0_0; -v0x17d4fe0_0 .alias "OrNorXorOut", 3 0, v0x17ddb90_0; -L_0x17ec700 .part/pv L_0x17ec490, 1, 1, 4; -L_0x17ec830 .part v0x17dd890_0, 1, 1; -L_0x17e37f0 .part v0x17dda10_0, 1, 1; -L_0x17edc60 .part/pv L_0x17ed9f0, 2, 1, 4; -L_0x17edd00 .part v0x17dd890_0, 2, 1; -L_0x17edda0 .part v0x17dda10_0, 2, 1; -L_0x17eef60 .part/pv L_0x17eecf0, 3, 1, 4; -L_0x17ef000 .part v0x17dd890_0, 3, 1; -L_0x17ef0a0 .part v0x17dda10_0, 3, 1; -L_0x17f0250 .part/pv L_0x17effe0, 0, 1, 4; -L_0x17f0350 .part v0x17dd890_0, 0, 1; -L_0x17f03f0 .part v0x17dda10_0, 0, 1; -S_0x17d3b00 .scope module, "attempt2" "OrNorXor" 2 195, 2 70, S_0x17cfd60; - .timescale -9 -12; -L_0x17ef140/d .functor NOR 1, L_0x17f0350, L_0x17f03f0, C4<0>, C4<0>; -L_0x17ef140 .delay (10000,10000,10000) L_0x17ef140/d; -L_0x17ef240/d .functor NOT 1, L_0x17ef140, C4<0>, C4<0>, C4<0>; -L_0x17ef240 .delay (10000,10000,10000) L_0x17ef240/d; -L_0x17ef370/d .functor NAND 1, L_0x17f0350, L_0x17f03f0, C4<1>, C4<1>; -L_0x17ef370 .delay (10000,10000,10000) L_0x17ef370/d; -L_0x17ef4d0/d .functor NAND 1, L_0x17ef370, L_0x17ef240, C4<1>, C4<1>; -L_0x17ef4d0 .delay (10000,10000,10000) L_0x17ef4d0/d; -L_0x17ef5e0/d .functor NOT 1, L_0x17ef4d0, C4<0>, C4<0>, C4<0>; -L_0x17ef5e0 .delay (10000,10000,10000) L_0x17ef5e0/d; -v0x17d4650_0 .net "A", 0 0, L_0x17f0350; 1 drivers -v0x17d46f0_0 .net "AnandB", 0 0, L_0x17ef370; 1 drivers -v0x17d4790_0 .net "AnorB", 0 0, L_0x17ef140; 1 drivers -v0x17d4840_0 .net "AorB", 0 0, L_0x17ef240; 1 drivers -v0x17d4920_0 .net "AxorB", 0 0, L_0x17ef5e0; 1 drivers -v0x17d49d0_0 .net "B", 0 0, L_0x17f03f0; 1 drivers -v0x17d4a90_0 .alias "Command", 2 0, v0x17dc9d0_0; -v0x17d4b10_0 .net "OrNorXorOut", 0 0, L_0x17effe0; 1 drivers -v0x17d4b90_0 .net "XorNor", 0 0, L_0x17efa60; 1 drivers -v0x17d4c60_0 .net "nXor", 0 0, L_0x17ef4d0; 1 drivers -L_0x17efbe0 .part v0x17dda90_0, 2, 1; -L_0x17f01b0 .part v0x17dda90_0, 0, 1; -S_0x17d40e0 .scope module, "mux0" "TwoInMux" 2 89, 2 8, S_0x17d3b00; - .timescale -9 -12; -L_0x17ef740/d .functor NOT 1, L_0x17efbe0, C4<0>, C4<0>, C4<0>; -L_0x17ef740 .delay (10000,10000,10000) L_0x17ef740/d; -L_0x17ef800/d .functor AND 1, L_0x17ef5e0, L_0x17ef740, C4<1>, C4<1>; -L_0x17ef800 .delay (20000,20000,20000) L_0x17ef800/d; -L_0x17ef910/d .functor AND 1, L_0x17ef140, L_0x17efbe0, C4<1>, C4<1>; -L_0x17ef910 .delay (20000,20000,20000) L_0x17ef910/d; -L_0x17efa60/d .functor OR 1, L_0x17ef800, L_0x17ef910, C4<0>, C4<0>; -L_0x17efa60 .delay (20000,20000,20000) L_0x17efa60/d; -v0x17d41d0_0 .net "S", 0 0, L_0x17efbe0; 1 drivers -v0x17d4290_0 .alias "in0", 0 0, v0x17d4920_0; -v0x17d4330_0 .alias "in1", 0 0, v0x17d4790_0; -v0x17d43d0_0 .net "nS", 0 0, L_0x17ef740; 1 drivers -v0x17d4450_0 .net "out0", 0 0, L_0x17ef800; 1 drivers -v0x17d44f0_0 .net "out1", 0 0, L_0x17ef910; 1 drivers -v0x17d45d0_0 .alias "outfinal", 0 0, v0x17d4b90_0; -S_0x17d3bf0 .scope module, "mux1" "TwoInMux" 2 90, 2 8, S_0x17d3b00; - .timescale -9 -12; -L_0x17efc80/d .functor NOT 1, L_0x17f01b0, C4<0>, C4<0>, C4<0>; -L_0x17efc80 .delay (10000,10000,10000) L_0x17efc80/d; -L_0x17efd40/d .functor AND 1, L_0x17efa60, L_0x17efc80, C4<1>, C4<1>; -L_0x17efd40 .delay (20000,20000,20000) L_0x17efd40/d; -L_0x17efe90/d .functor AND 1, L_0x17ef240, L_0x17f01b0, C4<1>, C4<1>; -L_0x17efe90 .delay (20000,20000,20000) L_0x17efe90/d; -L_0x17effe0/d .functor OR 1, L_0x17efd40, L_0x17efe90, C4<0>, C4<0>; -L_0x17effe0 .delay (20000,20000,20000) L_0x17effe0/d; -v0x17d3ce0_0 .net "S", 0 0, L_0x17f01b0; 1 drivers -v0x17d3d60_0 .alias "in0", 0 0, v0x17d4b90_0; -v0x17d3de0_0 .alias "in1", 0 0, v0x17d4840_0; -v0x17d3e80_0 .net "nS", 0 0, L_0x17efc80; 1 drivers -v0x17d3f00_0 .net "out0", 0 0, L_0x17efd40; 1 drivers -v0x17d3fa0_0 .net "out1", 0 0, L_0x17efe90; 1 drivers -v0x17d4040_0 .alias "outfinal", 0 0, v0x17d4b10_0; -S_0x17d2730 .scope generate, "orbits[1]" "orbits[1]" 2 199, 2 199, S_0x17cfd60; - .timescale -9 -12; -P_0x17d2448 .param/l "i" 2 199, +C4<01>; -S_0x17d2860 .scope module, "attempt" "OrNorXor" 2 201, 2 70, S_0x17d2730; - .timescale -9 -12; -L_0x17eb3e0/d .functor NOR 1, L_0x17ec830, L_0x17e37f0, C4<0>, C4<0>; -L_0x17eb3e0 .delay (10000,10000,10000) L_0x17eb3e0/d; -L_0x17eb6f0/d .functor NOT 1, L_0x17eb3e0, C4<0>, C4<0>, C4<0>; -L_0x17eb6f0 .delay (10000,10000,10000) L_0x17eb6f0/d; -L_0x17eb820/d .functor NAND 1, L_0x17ec830, L_0x17e37f0, C4<1>, C4<1>; -L_0x17eb820 .delay (10000,10000,10000) L_0x17eb820/d; -L_0x17eb980/d .functor NAND 1, L_0x17eb820, L_0x17eb6f0, C4<1>, C4<1>; -L_0x17eb980 .delay (10000,10000,10000) L_0x17eb980/d; -L_0x17eba90/d .functor NOT 1, L_0x17eb980, C4<0>, C4<0>, C4<0>; -L_0x17eba90 .delay (10000,10000,10000) L_0x17eba90/d; -v0x17d3410_0 .net "A", 0 0, L_0x17ec830; 1 drivers -v0x17d34b0_0 .net "AnandB", 0 0, L_0x17eb820; 1 drivers -v0x17d3550_0 .net "AnorB", 0 0, L_0x17eb3e0; 1 drivers -v0x17d3600_0 .net "AorB", 0 0, L_0x17eb6f0; 1 drivers -v0x17d36e0_0 .net "AxorB", 0 0, L_0x17eba90; 1 drivers -v0x17d3790_0 .net "B", 0 0, L_0x17e37f0; 1 drivers -v0x17d3850_0 .alias "Command", 2 0, v0x17dc9d0_0; -v0x17d38d0_0 .net "OrNorXorOut", 0 0, L_0x17ec490; 1 drivers -v0x17d3950_0 .net "XorNor", 0 0, L_0x17ebf10; 1 drivers -v0x17d3a20_0 .net "nXor", 0 0, L_0x17eb980; 1 drivers -L_0x17ec090 .part v0x17dda90_0, 2, 1; -L_0x17ec660 .part v0x17dda90_0, 0, 1; -S_0x17d2ea0 .scope module, "mux0" "TwoInMux" 2 89, 2 8, S_0x17d2860; - .timescale -9 -12; -L_0x17ebbf0/d .functor NOT 1, L_0x17ec090, C4<0>, C4<0>, C4<0>; -L_0x17ebbf0 .delay (10000,10000,10000) L_0x17ebbf0/d; -L_0x17ebcb0/d .functor AND 1, L_0x17eba90, L_0x17ebbf0, C4<1>, C4<1>; -L_0x17ebcb0 .delay (20000,20000,20000) L_0x17ebcb0/d; -L_0x17ebdc0/d .functor AND 1, L_0x17eb3e0, L_0x17ec090, C4<1>, C4<1>; -L_0x17ebdc0 .delay (20000,20000,20000) L_0x17ebdc0/d; -L_0x17ebf10/d .functor OR 1, L_0x17ebcb0, L_0x17ebdc0, C4<0>, C4<0>; -L_0x17ebf10 .delay (20000,20000,20000) L_0x17ebf10/d; -v0x17d2f90_0 .net "S", 0 0, L_0x17ec090; 1 drivers -v0x17d3050_0 .alias "in0", 0 0, v0x17d36e0_0; -v0x17d30f0_0 .alias "in1", 0 0, v0x17d3550_0; -v0x17d3190_0 .net "nS", 0 0, L_0x17ebbf0; 1 drivers -v0x17d3210_0 .net "out0", 0 0, L_0x17ebcb0; 1 drivers -v0x17d32b0_0 .net "out1", 0 0, L_0x17ebdc0; 1 drivers -v0x17d3390_0 .alias "outfinal", 0 0, v0x17d3950_0; -S_0x17d2950 .scope module, "mux1" "TwoInMux" 2 90, 2 8, S_0x17d2860; - .timescale -9 -12; -L_0x17ec130/d .functor NOT 1, L_0x17ec660, C4<0>, C4<0>, C4<0>; -L_0x17ec130 .delay (10000,10000,10000) L_0x17ec130/d; -L_0x17ec1f0/d .functor AND 1, L_0x17ebf10, L_0x17ec130, C4<1>, C4<1>; -L_0x17ec1f0 .delay (20000,20000,20000) L_0x17ec1f0/d; -L_0x17ec340/d .functor AND 1, L_0x17eb6f0, L_0x17ec660, C4<1>, C4<1>; -L_0x17ec340 .delay (20000,20000,20000) L_0x17ec340/d; -L_0x17ec490/d .functor OR 1, L_0x17ec1f0, L_0x17ec340, C4<0>, C4<0>; -L_0x17ec490 .delay (20000,20000,20000) L_0x17ec490/d; -v0x17d2a40_0 .net "S", 0 0, L_0x17ec660; 1 drivers -v0x17d2ac0_0 .alias "in0", 0 0, v0x17d3950_0; -v0x17d2b60_0 .alias "in1", 0 0, v0x17d3600_0; -v0x17d2c00_0 .net "nS", 0 0, L_0x17ec130; 1 drivers -v0x17d2c80_0 .net "out0", 0 0, L_0x17ec1f0; 1 drivers -v0x17d2d20_0 .net "out1", 0 0, L_0x17ec340; 1 drivers -v0x17d2e00_0 .alias "outfinal", 0 0, v0x17d38d0_0; -S_0x17d1360 .scope generate, "orbits[2]" "orbits[2]" 2 199, 2 199, S_0x17cfd60; - .timescale -9 -12; -P_0x17d0fc8 .param/l "i" 2 199, +C4<010>; -S_0x17d1490 .scope module, "attempt" "OrNorXor" 2 201, 2 70, S_0x17d1360; - .timescale -9 -12; -L_0x17e3890/d .functor NOR 1, L_0x17edd00, L_0x17edda0, C4<0>, C4<0>; -L_0x17e3890 .delay (10000,10000,10000) L_0x17e3890/d; -L_0x17e3a00/d .functor NOT 1, L_0x17e3890, C4<0>, C4<0>, C4<0>; -L_0x17e3a00 .delay (10000,10000,10000) L_0x17e3a00/d; -L_0x17ecd80/d .functor NAND 1, L_0x17edd00, L_0x17edda0, C4<1>, C4<1>; -L_0x17ecd80 .delay (10000,10000,10000) L_0x17ecd80/d; -L_0x17ecee0/d .functor NAND 1, L_0x17ecd80, L_0x17e3a00, C4<1>, C4<1>; -L_0x17ecee0 .delay (10000,10000,10000) L_0x17ecee0/d; -L_0x17ecff0/d .functor NOT 1, L_0x17ecee0, C4<0>, C4<0>, C4<0>; -L_0x17ecff0 .delay (10000,10000,10000) L_0x17ecff0/d; -v0x17d2040_0 .net "A", 0 0, L_0x17edd00; 1 drivers -v0x17d20e0_0 .net "AnandB", 0 0, L_0x17ecd80; 1 drivers -v0x17d2180_0 .net "AnorB", 0 0, L_0x17e3890; 1 drivers -v0x17d2230_0 .net "AorB", 0 0, L_0x17e3a00; 1 drivers -v0x17d2310_0 .net "AxorB", 0 0, L_0x17ecff0; 1 drivers -v0x17d23c0_0 .net "B", 0 0, L_0x17edda0; 1 drivers -v0x17d2480_0 .alias "Command", 2 0, v0x17dc9d0_0; -v0x17d2500_0 .net "OrNorXorOut", 0 0, L_0x17ed9f0; 1 drivers -v0x17d2580_0 .net "XorNor", 0 0, L_0x17ed470; 1 drivers -v0x17d2650_0 .net "nXor", 0 0, L_0x17ecee0; 1 drivers -L_0x17ed5f0 .part v0x17dda90_0, 2, 1; -L_0x17edbc0 .part v0x17dda90_0, 0, 1; -S_0x17d1ad0 .scope module, "mux0" "TwoInMux" 2 89, 2 8, S_0x17d1490; - .timescale -9 -12; -L_0x17ed150/d .functor NOT 1, L_0x17ed5f0, C4<0>, C4<0>, C4<0>; -L_0x17ed150 .delay (10000,10000,10000) L_0x17ed150/d; -L_0x17ed210/d .functor AND 1, L_0x17ecff0, L_0x17ed150, C4<1>, C4<1>; -L_0x17ed210 .delay (20000,20000,20000) L_0x17ed210/d; -L_0x17ed320/d .functor AND 1, L_0x17e3890, L_0x17ed5f0, C4<1>, C4<1>; -L_0x17ed320 .delay (20000,20000,20000) L_0x17ed320/d; -L_0x17ed470/d .functor OR 1, L_0x17ed210, L_0x17ed320, C4<0>, C4<0>; -L_0x17ed470 .delay (20000,20000,20000) L_0x17ed470/d; -v0x17d1bc0_0 .net "S", 0 0, L_0x17ed5f0; 1 drivers -v0x17d1c80_0 .alias "in0", 0 0, v0x17d2310_0; -v0x17d1d20_0 .alias "in1", 0 0, v0x17d2180_0; -v0x17d1dc0_0 .net "nS", 0 0, L_0x17ed150; 1 drivers -v0x17d1e40_0 .net "out0", 0 0, L_0x17ed210; 1 drivers -v0x17d1ee0_0 .net "out1", 0 0, L_0x17ed320; 1 drivers -v0x17d1fc0_0 .alias "outfinal", 0 0, v0x17d2580_0; -S_0x17d1580 .scope module, "mux1" "TwoInMux" 2 90, 2 8, S_0x17d1490; - .timescale -9 -12; -L_0x17ed690/d .functor NOT 1, L_0x17edbc0, C4<0>, C4<0>, C4<0>; -L_0x17ed690 .delay (10000,10000,10000) L_0x17ed690/d; -L_0x17ed750/d .functor AND 1, L_0x17ed470, L_0x17ed690, C4<1>, C4<1>; -L_0x17ed750 .delay (20000,20000,20000) L_0x17ed750/d; -L_0x17ed8a0/d .functor AND 1, L_0x17e3a00, L_0x17edbc0, C4<1>, C4<1>; -L_0x17ed8a0 .delay (20000,20000,20000) L_0x17ed8a0/d; -L_0x17ed9f0/d .functor OR 1, L_0x17ed750, L_0x17ed8a0, C4<0>, C4<0>; -L_0x17ed9f0 .delay (20000,20000,20000) L_0x17ed9f0/d; -v0x17d1670_0 .net "S", 0 0, L_0x17edbc0; 1 drivers -v0x17d16f0_0 .alias "in0", 0 0, v0x17d2580_0; -v0x17d1790_0 .alias "in1", 0 0, v0x17d2230_0; -v0x17d1830_0 .net "nS", 0 0, L_0x17ed690; 1 drivers -v0x17d18b0_0 .net "out0", 0 0, L_0x17ed750; 1 drivers -v0x17d1950_0 .net "out1", 0 0, L_0x17ed8a0; 1 drivers -v0x17d1a30_0 .alias "outfinal", 0 0, v0x17d2500_0; -S_0x17cfe90 .scope generate, "orbits[3]" "orbits[3]" 2 199, 2 199, S_0x17cfd60; - .timescale -9 -12; -P_0x17cff88 .param/l "i" 2 199, +C4<011>; -S_0x17d0000 .scope module, "attempt" "OrNorXor" 2 201, 2 70, S_0x17cfe90; - .timescale -9 -12; -L_0x17ede80/d .functor NOR 1, L_0x17ef000, L_0x17ef0a0, C4<0>, C4<0>; -L_0x17ede80 .delay (10000,10000,10000) L_0x17ede80/d; -L_0x17edf70/d .functor NOT 1, L_0x17ede80, C4<0>, C4<0>, C4<0>; -L_0x17edf70 .delay (10000,10000,10000) L_0x17edf70/d; -L_0x17ee080/d .functor NAND 1, L_0x17ef000, L_0x17ef0a0, C4<1>, C4<1>; -L_0x17ee080 .delay (10000,10000,10000) L_0x17ee080/d; -L_0x17ee1e0/d .functor NAND 1, L_0x17ee080, L_0x17edf70, C4<1>, C4<1>; -L_0x17ee1e0 .delay (10000,10000,10000) L_0x17ee1e0/d; -L_0x17ee2f0/d .functor NOT 1, L_0x17ee1e0, C4<0>, C4<0>, C4<0>; -L_0x17ee2f0 .delay (10000,10000,10000) L_0x17ee2f0/d; -v0x17d0bc0_0 .net "A", 0 0, L_0x17ef000; 1 drivers -v0x17d0c60_0 .net "AnandB", 0 0, L_0x17ee080; 1 drivers -v0x17d0d00_0 .net "AnorB", 0 0, L_0x17ede80; 1 drivers -v0x17d0db0_0 .net "AorB", 0 0, L_0x17edf70; 1 drivers -v0x17d0e90_0 .net "AxorB", 0 0, L_0x17ee2f0; 1 drivers -v0x17d0f40_0 .net "B", 0 0, L_0x17ef0a0; 1 drivers -v0x17d1000_0 .alias "Command", 2 0, v0x17dc9d0_0; -v0x17c9a50_0 .net "OrNorXorOut", 0 0, L_0x17eecf0; 1 drivers -v0x17c9ad0_0 .net "XorNor", 0 0, L_0x17ee770; 1 drivers -v0x17d12e0_0 .net "nXor", 0 0, L_0x17ee1e0; 1 drivers -L_0x17ee8f0 .part v0x17dda90_0, 2, 1; -L_0x17eeec0 .part v0x17dda90_0, 0, 1; -S_0x17d0650 .scope module, "mux0" "TwoInMux" 2 89, 2 8, S_0x17d0000; - .timescale -9 -12; -L_0x17ee450/d .functor NOT 1, L_0x17ee8f0, C4<0>, C4<0>, C4<0>; -L_0x17ee450 .delay (10000,10000,10000) L_0x17ee450/d; -L_0x17ee510/d .functor AND 1, L_0x17ee2f0, L_0x17ee450, C4<1>, C4<1>; -L_0x17ee510 .delay (20000,20000,20000) L_0x17ee510/d; -L_0x17ee620/d .functor AND 1, L_0x17ede80, L_0x17ee8f0, C4<1>, C4<1>; -L_0x17ee620 .delay (20000,20000,20000) L_0x17ee620/d; -L_0x17ee770/d .functor OR 1, L_0x17ee510, L_0x17ee620, C4<0>, C4<0>; -L_0x17ee770 .delay (20000,20000,20000) L_0x17ee770/d; -v0x17d0740_0 .net "S", 0 0, L_0x17ee8f0; 1 drivers -v0x17d0800_0 .alias "in0", 0 0, v0x17d0e90_0; -v0x17d08a0_0 .alias "in1", 0 0, v0x17d0d00_0; -v0x17d0940_0 .net "nS", 0 0, L_0x17ee450; 1 drivers -v0x17d09c0_0 .net "out0", 0 0, L_0x17ee510; 1 drivers -v0x17d0a60_0 .net "out1", 0 0, L_0x17ee620; 1 drivers -v0x17d0b40_0 .alias "outfinal", 0 0, v0x17c9ad0_0; -S_0x17d00f0 .scope module, "mux1" "TwoInMux" 2 90, 2 8, S_0x17d0000; - .timescale -9 -12; -L_0x17ee990/d .functor NOT 1, L_0x17eeec0, C4<0>, C4<0>, C4<0>; -L_0x17ee990 .delay (10000,10000,10000) L_0x17ee990/d; -L_0x17eea50/d .functor AND 1, L_0x17ee770, L_0x17ee990, C4<1>, C4<1>; -L_0x17eea50 .delay (20000,20000,20000) L_0x17eea50/d; -L_0x17eeba0/d .functor AND 1, L_0x17edf70, L_0x17eeec0, C4<1>, C4<1>; -L_0x17eeba0 .delay (20000,20000,20000) L_0x17eeba0/d; -L_0x17eecf0/d .functor OR 1, L_0x17eea50, L_0x17eeba0, C4<0>, C4<0>; -L_0x17eecf0 .delay (20000,20000,20000) L_0x17eecf0/d; -v0x17d01e0_0 .net "S", 0 0, L_0x17eeec0; 1 drivers -v0x17d0260_0 .alias "in0", 0 0, v0x17c9ad0_0; -v0x17d02e0_0 .alias "in1", 0 0, v0x17d0db0_0; -v0x17d0380_0 .net "nS", 0 0, L_0x17ee990; 1 drivers -v0x17d0430_0 .net "out0", 0 0, L_0x17eea50; 1 drivers -v0x17d04d0_0 .net "out1", 0 0, L_0x17eeba0; 1 drivers -v0x17d05b0_0 .alias "outfinal", 0 0, v0x17c9a50_0; -S_0x17bb1b0 .scope module, "superalu" "Bitslice32" 3 31, 2 262, S_0x1782ed0; - .timescale -9 -12; -P_0x17ba1f8 .param/l "size" 2 277, +C4<0100>; -v0x17cf380_0 .alias "A", 3 0, v0x17dc7b0_0; -v0x17cf570_0 .alias "AddSubSLTSum", 3 0, v0x17dd910_0; -v0x17cf5f0_0 .alias "AndNandOut", 3 0, v0x17dd990_0; -v0x17cf670_0 .alias "B", 3 0, v0x17dc8d0_0; -RS_0x7ff970b2cae8 .resolv tri, L_0x17f0b90, L_0x17f31f0, L_0x17f5be0, L_0x1805bf0; -v0x17cf720_0 .net8 "Cmd0Start", 3 0, RS_0x7ff970b2cae8; 4 drivers -RS_0x7ff970b2cb18 .resolv tri, L_0x17f1aa0, L_0x17f40d0, L_0x17f6ba0, L_0x18069b0; -v0x17cf7a0_0 .net8 "Cmd1Start", 3 0, RS_0x7ff970b2cb18; 4 drivers -v0x17cf820_0 .alias "Command", 2 0, v0x17dc9d0_0; -v0x17cf8a0_0 .alias "OneBitFinalOut", 3 0, v0x17ddb10_0; -v0x17cf920_0 .alias "OrNorXorOut", 3 0, v0x17ddb90_0; -v0x17cf9a0_0 .alias "SLTflag", 0 0, v0x17ddc10_0; -v0x17cfa50_0 .alias "carryin", 3 0, v0x17dd400_0; -v0x17cfb00_0 .alias "carryout", 0 0, v0x17ddd10_0; -v0x17cfbb0_0 .alias "overflow", 0 0, v0x17ddd90_0; -v0x17cfc60_0 .alias "subtract", 3 0, v0x17dde10_0; -L_0x17f0b90 .part/pv L_0x17f09b0, 1, 1, 4; -L_0x17f0c30 .part v0x17dda90_0, 0, 1; -L_0x17f0d60 .part v0x17dda90_0, 1, 1; -L_0x17f0e90 .part RS_0x7ff970b2c6f8, 1, 1; -L_0x17f0f30 .part RS_0x7ff970b2c6f8, 1, 1; -L_0x17f0fd0 .part RS_0x7ff970b2b258, 1, 1; -L_0x17f11d0 .part RS_0x7ff970b2c6f8, 1, 1; -L_0x17f1aa0 .part/pv L_0x17f1890, 1, 1, 4; -L_0x17f1b90 .part v0x17dda90_0, 0, 1; -L_0x17f1cc0 .part v0x17dda90_0, 1, 1; -L_0x17f1e50 .part RS_0x7ff970b2b948, 1, 1; -L_0x17f2000 .part RS_0x7ff970b2b948, 1, 1; -L_0x17f20a0 .part RS_0x7ff970b2b258, 1, 1; -L_0x17f2140 .part RS_0x7ff970b2b258, 1, 1; -L_0x17f25a0 .part/pv L_0x17f2460, 1, 1, 4; -L_0x17f2690 .part v0x17dda90_0, 2, 1; -L_0x17f2730 .part RS_0x7ff970b2cae8, 1, 1; -L_0x17f2870 .part RS_0x7ff970b2cb18, 1, 1; -L_0x17f31f0 .part/pv L_0x17f2fe0, 2, 1, 4; -L_0x17f3290 .part v0x17dda90_0, 0, 1; -L_0x17f29b0 .part v0x17dda90_0, 1, 1; -L_0x17f3500 .part RS_0x7ff970b2c6f8, 2, 1; -L_0x17f33c0 .part RS_0x7ff970b2c6f8, 2, 1; -L_0x17f3660 .part RS_0x7ff970b2b258, 2, 1; -L_0x17f35a0 .part RS_0x7ff970b2c6f8, 2, 1; -L_0x17f40d0 .part/pv L_0x17f3ec0, 2, 1, 4; -L_0x17f3750 .part v0x17dda90_0, 0, 1; -L_0x17e2910 .part v0x17dda90_0, 1, 1; -L_0x17f4170 .part RS_0x7ff970b2b948, 2, 1; -L_0x17e2b30 .part RS_0x7ff970b2b948, 2, 1; -L_0x17e2a40 .part RS_0x7ff970b2b258, 2, 1; -L_0x17f4af0 .part RS_0x7ff970b2b258, 2, 1; -L_0x17f4f80 .part/pv L_0x17f4e40, 2, 1, 4; -L_0x17f5020 .part v0x17dda90_0, 2, 1; -L_0x17f4b90 .part RS_0x7ff970b2cae8, 2, 1; -L_0x17f5270 .part RS_0x7ff970b2cb18, 2, 1; -L_0x17f5be0 .part/pv L_0x17f59d0, 3, 1, 4; -L_0x17f5c80 .part v0x17dda90_0, 0, 1; -L_0x17f53a0 .part v0x17dda90_0, 1, 1; -L_0x17f5ef0 .part RS_0x7ff970b2c6f8, 3, 1; -L_0x17e85e0 .part RS_0x7ff970b2c6f8, 3, 1; -L_0x17f5db0 .part RS_0x7ff970b2b258, 3, 1; -L_0x17f6300 .part RS_0x7ff970b2c6f8, 3, 1; -L_0x17f6ba0 .part/pv L_0x17f6990, 3, 1, 4; -L_0x17f61a0 .part v0x17dda90_0, 0, 1; -L_0x17f6db0 .part v0x17dda90_0, 1, 1; -L_0x17f6c40 .part RS_0x7ff970b2b948, 3, 1; -L_0x17f6ce0 .part RS_0x7ff970b2b948, 3, 1; -L_0x17f7070 .part RS_0x7ff970b2b258, 3, 1; -L_0x17f7160 .part RS_0x7ff970b2b258, 3, 1; -L_0x17f7790 .part/pv L_0x17f7650, 3, 1, 4; -L_0x17f78c0 .part v0x17dda90_0, 2, 1; -L_0x17f7460 .part RS_0x7ff970b2cae8, 3, 1; -L_0x17f7500 .part RS_0x7ff970b2cb18, 3, 1; -L_0x1805bf0 .part/pv L_0x1805a10, 0, 1, 4; -L_0x1805c90 .part v0x17dda90_0, 0, 1; -L_0x17f7960 .part v0x17dda90_0, 1, 1; -L_0x1805f90 .part RS_0x7ff970b2c6f8, 0, 1; -L_0x1805dc0 .part RS_0x7ff970b2c6f8, 0, 1; -L_0x1805e60 .part RS_0x7ff970b2b258, 0, 1; -L_0x1806220 .part RS_0x7ff970b2c6f8, 0, 1; -L_0x18069b0 .part/pv L_0x18067d0, 0, 1, 4; -L_0x1806030 .part v0x17dda90_0, 0, 1; -L_0x1806160 .part v0x17dda90_0, 1, 1; -L_0x1806a50 .part RS_0x7ff970b2b948, 0, 1; -L_0x1806af0 .part RS_0x7ff970b2b948, 0, 1; -L_0x1806b90 .part RS_0x7ff970b2b258, 0, 1; -L_0x1806f50 .part RS_0x7ff970b2b258, 0, 1; -L_0x1807460 .part/pv L_0x1807320, 0, 1, 4; -L_0x1807500 .part v0x17dda90_0, 2, 1; -L_0x1807040 .part RS_0x7ff970b2cae8, 0, 1; -L_0x18077e0 .part RS_0x7ff970b2cb18, 0, 1; -S_0x17c9d40 .scope module, "trial" "AddSubSLT32" 2 282, 2 209, S_0x17bb1b0; - .timescale -9 -12; -P_0x17c9e38 .param/l "size" 2 232, +C4<0100>; -L_0x17fcb80/d .functor OR 1, L_0x17fce40, C4<0>, C4<0>, C4<0>; -L_0x17fcb80 .delay (20000,20000,20000) L_0x17fcb80/d; -L_0x17fcff0/d .functor XOR 1, RS_0x7ff970b2c9f8, L_0x17fd0e0, C4<0>, C4<0>; -L_0x17fcff0 .delay (40000,40000,40000) L_0x17fcff0/d; -L_0x17fcd70/d .functor AND 1, L_0x17fd2b0, L_0x17fd350, C4<1>, C4<1>; -L_0x17fcd70 .delay (20000,20000,20000) L_0x17fcd70/d; -L_0x17fd180/d .functor NOT 1, RS_0x7ff970b2ca88, C4<0>, C4<0>, C4<0>; -L_0x17fd180 .delay (10000,10000,10000) L_0x17fd180/d; -L_0x17fd640/d .functor NOT 1, L_0x17fd6a0, C4<0>, C4<0>, C4<0>; -L_0x17fd640 .delay (10000,10000,10000) L_0x17fd640/d; -L_0x17fd740/d .functor AND 1, L_0x17fd180, L_0x17fd880, C4<1>, C4<1>; -L_0x17fd740 .delay (20000,20000,20000) L_0x17fd740/d; -L_0x17fd440/d .functor AND 1, RS_0x7ff970b2ca88, L_0x17fd640, C4<1>, C4<1>; -L_0x17fd440 .delay (20000,20000,20000) L_0x17fd440/d; -L_0x17fda70/d .functor AND 1, L_0x17fd740, L_0x17fcd70, C4<1>, C4<1>; -L_0x17fda70 .delay (20000,20000,20000) L_0x17fda70/d; -L_0x17fdbb0/d .functor AND 1, L_0x17fd440, L_0x17fcd70, C4<1>, C4<1>; -L_0x17fdbb0 .delay (20000,20000,20000) L_0x17fdbb0/d; -L_0x17fdcd0/d .functor OR 1, L_0x17fda70, L_0x17fdbb0, C4<0>, C4<0>; -L_0x17fdcd0 .delay (20000,20000,20000) L_0x17fdcd0/d; -v0x17ce4a0_0 .alias "A", 3 0, v0x17dc7b0_0; -v0x17ce540_0 .alias "AddSubSLTSum", 3 0, v0x17dd910_0; -v0x17ce5e0_0 .alias "B", 3 0, v0x17dc8d0_0; -RS_0x7ff970b2c728 .resolv tri, L_0x17f8af0, L_0x17f9f10, L_0x17fb310, L_0x17fc8f0; -v0x17ce6b0_0 .net8 "CarryoutWire", 3 0, RS_0x7ff970b2c728; 4 drivers -v0x17ce730_0 .alias "Command", 2 0, v0x17dc9d0_0; -v0x17ce7b0_0 .net "Res0OF1", 0 0, L_0x17fd440; 1 drivers -v0x17ce850_0 .net "Res1OF0", 0 0, L_0x17fd740; 1 drivers -v0x17ce8f0_0 .alias "SLTflag", 0 0, v0x17ddc10_0; -v0x17ce9e0_0 .net "SLTflag0", 0 0, L_0x17fda70; 1 drivers -v0x17cea80_0 .net "SLTflag1", 0 0, L_0x17fdbb0; 1 drivers -v0x17ceb20_0 .net "SLTon", 0 0, L_0x17fcd70; 1 drivers -v0x17cebc0_0 .net *"_s40", 0 0, L_0x17fce40; 1 drivers -v0x17cec60_0 .net/s *"_s41", 0 0, C4<0>; 1 drivers -v0x17ced00_0 .net *"_s44", 0 0, L_0x17fd0e0; 1 drivers -v0x17cee20_0 .net *"_s46", 0 0, L_0x17fd2b0; 1 drivers -v0x17ceec0_0 .net *"_s48", 0 0, L_0x17fd350; 1 drivers -v0x17ced80_0 .net *"_s50", 0 0, L_0x17fd6a0; 1 drivers -v0x17cf010_0 .net *"_s52", 0 0, L_0x17fd880; 1 drivers -v0x17cf130_0 .alias "carryin", 3 0, v0x17dd400_0; -v0x17cf1b0_0 .alias "carryout", 0 0, v0x17ddd10_0; -v0x17cf090_0 .net "nAddSubSLTSum", 0 0, L_0x17fd640; 1 drivers -v0x17cf2e0_0 .net "nOF", 0 0, L_0x17fd180; 1 drivers -v0x17cf230_0 .alias "overflow", 0 0, v0x17ddd90_0; -v0x17cf420_0 .alias "subtract", 3 0, v0x17dde10_0; -L_0x17f8a00 .part/pv L_0x17f8570, 1, 1, 4; -L_0x17f8af0 .part/pv L_0x17f88c0, 1, 1, 4; -L_0x17f8be0 .part/pv L_0x17f82a0, 1, 1, 4; -L_0x17f8cd0 .part v0x17dd890_0, 1, 1; -L_0x17f8d70 .part v0x17dda10_0, 1, 1; -L_0x17f8ea0 .part RS_0x7ff970b2c728, 0, 1; -L_0x17f9e20 .part/pv L_0x17f9990, 2, 1, 4; -L_0x17f9f10 .part/pv L_0x17f9ce0, 2, 1, 4; -L_0x17fa050 .part/pv L_0x17f96c0, 2, 1, 4; -L_0x17fa140 .part v0x17dd890_0, 2, 1; -L_0x17fa240 .part v0x17dda10_0, 2, 1; -L_0x17fa370 .part RS_0x7ff970b2c728, 1, 1; -L_0x17fb220 .part/pv L_0x17fad90, 3, 1, 4; -L_0x17fb310 .part/pv L_0x17fb0e0, 3, 1, 4; -L_0x17fb480 .part/pv L_0x17faac0, 3, 1, 4; -L_0x17fb570 .part v0x17dd890_0, 3, 1; -L_0x17fb6a0 .part v0x17dda10_0, 3, 1; -L_0x17fb7d0 .part RS_0x7ff970b2c728, 2, 1; -L_0x17fc800 .part/pv L_0x17fc330, 0, 1, 4; -L_0x17fc8f0 .part/pv L_0x17fc6a0, 0, 1, 4; -L_0x17fb870 .part/pv L_0x17fc060, 0, 1, 4; -L_0x17fcae0 .part v0x17dd890_0, 0, 1; -L_0x17fc9e0 .part v0x17dda10_0, 0, 1; -L_0x17fccd0 .part RS_0x7ff970b2cab8, 0, 1; -L_0x17fce40 .part RS_0x7ff970b2c728, 3, 1; -L_0x17fd0e0 .part RS_0x7ff970b2c728, 2, 1; -L_0x17fd2b0 .part v0x17dda90_0, 1, 1; -L_0x17fd350 .part RS_0x7ff970b2cab8, 0, 1; -L_0x17fd6a0 .part RS_0x7ff970b2c6f8, 3, 1; -L_0x17fd880 .part RS_0x7ff970b2c6f8, 3, 1; -S_0x17cd490 .scope module, "attempt2" "MiddleAddSubSLT" 2 229, 2 95, S_0x17c9d40; - .timescale -9 -12; -L_0x17fb610/d .functor NOT 1, L_0x17fc9e0, C4<0>, C4<0>, C4<0>; -L_0x17fb610 .delay (10000,10000,10000) L_0x17fb610/d; -L_0x17fbf00/d .functor NOT 1, L_0x17fbfc0, C4<0>, C4<0>, C4<0>; -L_0x17fbf00 .delay (10000,10000,10000) L_0x17fbf00/d; -L_0x17fc060/d .functor AND 1, L_0x17fc1a0, L_0x17fbf00, C4<1>, C4<1>; -L_0x17fc060 .delay (20000,20000,20000) L_0x17fc060/d; -L_0x17fc240/d .functor XOR 1, L_0x17fcae0, L_0x17fbc90, C4<0>, C4<0>; -L_0x17fc240 .delay (40000,40000,40000) L_0x17fc240/d; -L_0x17fc330/d .functor XOR 1, L_0x17fc240, L_0x17fccd0, C4<0>, C4<0>; -L_0x17fc330 .delay (40000,40000,40000) L_0x17fc330/d; -L_0x17fc420/d .functor AND 1, L_0x17fcae0, L_0x17fbc90, C4<1>, C4<1>; -L_0x17fc420 .delay (20000,20000,20000) L_0x17fc420/d; -L_0x17fc590/d .functor AND 1, L_0x17fc240, L_0x17fccd0, C4<1>, C4<1>; -L_0x17fc590 .delay (20000,20000,20000) L_0x17fc590/d; -L_0x17fc6a0/d .functor OR 1, L_0x17fc420, L_0x17fc590, C4<0>, C4<0>; -L_0x17fc6a0 .delay (20000,20000,20000) L_0x17fc6a0/d; -v0x17cdb00_0 .net "A", 0 0, L_0x17fcae0; 1 drivers -v0x17cdbc0_0 .net "AandB", 0 0, L_0x17fc420; 1 drivers -v0x17cdc60_0 .net "AddSubSLTSum", 0 0, L_0x17fc330; 1 drivers -v0x17cdd00_0 .net "AxorB", 0 0, L_0x17fc240; 1 drivers -v0x17cdd80_0 .net "B", 0 0, L_0x17fc9e0; 1 drivers -v0x17cde30_0 .net "BornB", 0 0, L_0x17fbc90; 1 drivers -v0x17cdef0_0 .net "CINandAxorB", 0 0, L_0x17fc590; 1 drivers -v0x17cdf70_0 .alias "Command", 2 0, v0x17dc9d0_0; -v0x17cdff0_0 .net *"_s3", 0 0, L_0x17fbfc0; 1 drivers -v0x17ce070_0 .net *"_s5", 0 0, L_0x17fc1a0; 1 drivers -v0x17ce110_0 .net "carryin", 0 0, L_0x17fccd0; 1 drivers -v0x17ce1b0_0 .net "carryout", 0 0, L_0x17fc6a0; 1 drivers -v0x17ce250_0 .net "nB", 0 0, L_0x17fb610; 1 drivers -v0x17ce300_0 .net "nCmd2", 0 0, L_0x17fbf00; 1 drivers -v0x17ce400_0 .net "subtract", 0 0, L_0x17fc060; 1 drivers -L_0x17fbe60 .part v0x17dda90_0, 0, 1; -L_0x17fbfc0 .part v0x17dda90_0, 2, 1; -L_0x17fc1a0 .part v0x17dda90_0, 0, 1; -S_0x17cd580 .scope module, "mux0" "TwoInMux" 2 111, 2 8, S_0x17cd490; - .timescale -9 -12; -L_0x17fb9b0/d .functor NOT 1, L_0x17fbe60, C4<0>, C4<0>, C4<0>; -L_0x17fb9b0 .delay (10000,10000,10000) L_0x17fb9b0/d; -L_0x17fba70/d .functor AND 1, L_0x17fc9e0, L_0x17fb9b0, C4<1>, C4<1>; -L_0x17fba70 .delay (20000,20000,20000) L_0x17fba70/d; -L_0x17fbb80/d .functor AND 1, L_0x17fb610, L_0x17fbe60, C4<1>, C4<1>; -L_0x17fbb80 .delay (20000,20000,20000) L_0x17fbb80/d; -L_0x17fbc90/d .functor OR 1, L_0x17fba70, L_0x17fbb80, C4<0>, C4<0>; -L_0x17fbc90 .delay (20000,20000,20000) L_0x17fbc90/d; -v0x17cd670_0 .net "S", 0 0, L_0x17fbe60; 1 drivers -v0x17cd730_0 .alias "in0", 0 0, v0x17cdd80_0; -v0x17cd7d0_0 .alias "in1", 0 0, v0x17ce250_0; -v0x17cd870_0 .net "nS", 0 0, L_0x17fb9b0; 1 drivers -v0x17cd920_0 .net "out0", 0 0, L_0x17fba70; 1 drivers -v0x17cd9c0_0 .net "out1", 0 0, L_0x17fbb80; 1 drivers -v0x17cda60_0 .alias "outfinal", 0 0, v0x17cde30_0; -S_0x17cc2f0 .scope generate, "addbits[1]" "addbits[1]" 2 234, 2 234, S_0x17c9d40; - .timescale -9 -12; -P_0x17cbd08 .param/l "i" 2 234, +C4<01>; -S_0x17cc460 .scope module, "attempt" "MiddleAddSubSLT" 2 236, 2 95, S_0x17cc2f0; - .timescale -9 -12; -L_0x17f7b20/d .functor NOT 1, L_0x17f8d70, C4<0>, C4<0>, C4<0>; -L_0x17f7b20 .delay (10000,10000,10000) L_0x17f7b20/d; -L_0x17f8160/d .functor NOT 1, L_0x17f8200, C4<0>, C4<0>, C4<0>; -L_0x17f8160 .delay (10000,10000,10000) L_0x17f8160/d; -L_0x17f82a0/d .functor AND 1, L_0x17f83e0, L_0x17f8160, C4<1>, C4<1>; -L_0x17f82a0 .delay (20000,20000,20000) L_0x17f82a0/d; -L_0x17f8480/d .functor XOR 1, L_0x17f8cd0, L_0x17f7f30, C4<0>, C4<0>; -L_0x17f8480 .delay (40000,40000,40000) L_0x17f8480/d; -L_0x17f8570/d .functor XOR 1, L_0x17f8480, L_0x17f8ea0, C4<0>, C4<0>; -L_0x17f8570 .delay (40000,40000,40000) L_0x17f8570/d; -L_0x17f8660/d .functor AND 1, L_0x17f8cd0, L_0x17f7f30, C4<1>, C4<1>; -L_0x17f8660 .delay (20000,20000,20000) L_0x17f8660/d; -L_0x17f87d0/d .functor AND 1, L_0x17f8480, L_0x17f8ea0, C4<1>, C4<1>; -L_0x17f87d0 .delay (20000,20000,20000) L_0x17f87d0/d; -L_0x17f88c0/d .functor OR 1, L_0x17f8660, L_0x17f87d0, C4<0>, C4<0>; -L_0x17f88c0 .delay (20000,20000,20000) L_0x17f88c0/d; -v0x17ccaf0_0 .net "A", 0 0, L_0x17f8cd0; 1 drivers -v0x17ccbb0_0 .net "AandB", 0 0, L_0x17f8660; 1 drivers -v0x17ccc50_0 .net "AddSubSLTSum", 0 0, L_0x17f8570; 1 drivers -v0x17cccf0_0 .net "AxorB", 0 0, L_0x17f8480; 1 drivers -v0x17ccd70_0 .net "B", 0 0, L_0x17f8d70; 1 drivers -v0x17cce20_0 .net "BornB", 0 0, L_0x17f7f30; 1 drivers -v0x17ccee0_0 .net "CINandAxorB", 0 0, L_0x17f87d0; 1 drivers -v0x17ccf60_0 .alias "Command", 2 0, v0x17dc9d0_0; -v0x17ccfe0_0 .net *"_s3", 0 0, L_0x17f8200; 1 drivers -v0x17cd060_0 .net *"_s5", 0 0, L_0x17f83e0; 1 drivers -v0x17cd100_0 .net "carryin", 0 0, L_0x17f8ea0; 1 drivers -v0x17cd1a0_0 .net "carryout", 0 0, L_0x17f88c0; 1 drivers -v0x17cd240_0 .net "nB", 0 0, L_0x17f7b20; 1 drivers -v0x17cd2f0_0 .net "nCmd2", 0 0, L_0x17f8160; 1 drivers -v0x17cd3f0_0 .net "subtract", 0 0, L_0x17f82a0; 1 drivers -L_0x17f80c0 .part v0x17dda90_0, 0, 1; -L_0x17f8200 .part v0x17dda90_0, 2, 1; -L_0x17f83e0 .part v0x17dda90_0, 0, 1; -S_0x17cc550 .scope module, "mux0" "TwoInMux" 2 111, 2 8, S_0x17cc460; - .timescale -9 -12; -L_0x17f7cb0/d .functor NOT 1, L_0x17f80c0, C4<0>, C4<0>, C4<0>; -L_0x17f7cb0 .delay (10000,10000,10000) L_0x17f7cb0/d; -L_0x17f7d50/d .functor AND 1, L_0x17f8d70, L_0x17f7cb0, C4<1>, C4<1>; -L_0x17f7d50 .delay (20000,20000,20000) L_0x17f7d50/d; -L_0x17f7e40/d .functor AND 1, L_0x17f7b20, L_0x17f80c0, C4<1>, C4<1>; -L_0x17f7e40 .delay (20000,20000,20000) L_0x17f7e40/d; -L_0x17f7f30/d .functor OR 1, L_0x17f7d50, L_0x17f7e40, C4<0>, C4<0>; -L_0x17f7f30 .delay (20000,20000,20000) L_0x17f7f30/d; -v0x17cc640_0 .net "S", 0 0, L_0x17f80c0; 1 drivers -v0x17cc6e0_0 .alias "in0", 0 0, v0x17ccd70_0; -v0x17cc780_0 .alias "in1", 0 0, v0x17cd240_0; -v0x17cc820_0 .net "nS", 0 0, L_0x17f7cb0; 1 drivers -v0x17cc8d0_0 .net "out0", 0 0, L_0x17f7d50; 1 drivers -v0x17cc970_0 .net "out1", 0 0, L_0x17f7e40; 1 drivers -v0x17cca50_0 .alias "outfinal", 0 0, v0x17cce20_0; -S_0x17cb150 .scope generate, "addbits[2]" "addbits[2]" 2 234, 2 234, S_0x17c9d40; - .timescale -9 -12; -P_0x17caa48 .param/l "i" 2 234, +C4<010>; -S_0x17cb2c0 .scope module, "attempt" "MiddleAddSubSLT" 2 236, 2 95, S_0x17cb150; - .timescale -9 -12; -L_0x17f8f40/d .functor NOT 1, L_0x17fa240, C4<0>, C4<0>, C4<0>; -L_0x17f8f40 .delay (10000,10000,10000) L_0x17f8f40/d; -L_0x17f9580/d .functor NOT 1, L_0x17f9620, C4<0>, C4<0>, C4<0>; -L_0x17f9580 .delay (10000,10000,10000) L_0x17f9580/d; -L_0x17f96c0/d .functor AND 1, L_0x17f9800, L_0x17f9580, C4<1>, C4<1>; -L_0x17f96c0 .delay (20000,20000,20000) L_0x17f96c0/d; -L_0x17f98a0/d .functor XOR 1, L_0x17fa140, L_0x17f9350, C4<0>, C4<0>; -L_0x17f98a0 .delay (40000,40000,40000) L_0x17f98a0/d; -L_0x17f9990/d .functor XOR 1, L_0x17f98a0, L_0x17fa370, C4<0>, C4<0>; -L_0x17f9990 .delay (40000,40000,40000) L_0x17f9990/d; -L_0x17f9a80/d .functor AND 1, L_0x17fa140, L_0x17f9350, C4<1>, C4<1>; -L_0x17f9a80 .delay (20000,20000,20000) L_0x17f9a80/d; -L_0x17f9bf0/d .functor AND 1, L_0x17f98a0, L_0x17fa370, C4<1>, C4<1>; -L_0x17f9bf0 .delay (20000,20000,20000) L_0x17f9bf0/d; -L_0x17f9ce0/d .functor OR 1, L_0x17f9a80, L_0x17f9bf0, C4<0>, C4<0>; -L_0x17f9ce0 .delay (20000,20000,20000) L_0x17f9ce0/d; -v0x17cb950_0 .net "A", 0 0, L_0x17fa140; 1 drivers -v0x17cba10_0 .net "AandB", 0 0, L_0x17f9a80; 1 drivers -v0x17cbab0_0 .net "AddSubSLTSum", 0 0, L_0x17f9990; 1 drivers -v0x17cbb50_0 .net "AxorB", 0 0, L_0x17f98a0; 1 drivers -v0x17cbbd0_0 .net "B", 0 0, L_0x17fa240; 1 drivers -v0x17cbc80_0 .net "BornB", 0 0, L_0x17f9350; 1 drivers -v0x17cbd40_0 .net "CINandAxorB", 0 0, L_0x17f9bf0; 1 drivers -v0x17cbdc0_0 .alias "Command", 2 0, v0x17dc9d0_0; -v0x17cbe40_0 .net *"_s3", 0 0, L_0x17f9620; 1 drivers -v0x17cbec0_0 .net *"_s5", 0 0, L_0x17f9800; 1 drivers -v0x17cbf60_0 .net "carryin", 0 0, L_0x17fa370; 1 drivers -v0x17cc000_0 .net "carryout", 0 0, L_0x17f9ce0; 1 drivers -v0x17cc0a0_0 .net "nB", 0 0, L_0x17f8f40; 1 drivers -v0x17cc150_0 .net "nCmd2", 0 0, L_0x17f9580; 1 drivers -v0x17cc250_0 .net "subtract", 0 0, L_0x17f96c0; 1 drivers -L_0x17f94e0 .part v0x17dda90_0, 0, 1; -L_0x17f9620 .part v0x17dda90_0, 2, 1; -L_0x17f9800 .part v0x17dda90_0, 0, 1; -S_0x17cb3b0 .scope module, "mux0" "TwoInMux" 2 111, 2 8, S_0x17cb2c0; - .timescale -9 -12; -L_0x17f90d0/d .functor NOT 1, L_0x17f94e0, C4<0>, C4<0>, C4<0>; -L_0x17f90d0 .delay (10000,10000,10000) L_0x17f90d0/d; -L_0x17f9170/d .functor AND 1, L_0x17fa240, L_0x17f90d0, C4<1>, C4<1>; -L_0x17f9170 .delay (20000,20000,20000) L_0x17f9170/d; -L_0x17f9260/d .functor AND 1, L_0x17f8f40, L_0x17f94e0, C4<1>, C4<1>; -L_0x17f9260 .delay (20000,20000,20000) L_0x17f9260/d; -L_0x17f9350/d .functor OR 1, L_0x17f9170, L_0x17f9260, C4<0>, C4<0>; -L_0x17f9350 .delay (20000,20000,20000) L_0x17f9350/d; -v0x17cb4a0_0 .net "S", 0 0, L_0x17f94e0; 1 drivers -v0x17cb540_0 .alias "in0", 0 0, v0x17cbbd0_0; -v0x17cb5e0_0 .alias "in1", 0 0, v0x17cc0a0_0; -v0x17cb680_0 .net "nS", 0 0, L_0x17f90d0; 1 drivers -v0x17cb730_0 .net "out0", 0 0, L_0x17f9170; 1 drivers -v0x17cb7d0_0 .net "out1", 0 0, L_0x17f9260; 1 drivers -v0x17cb8b0_0 .alias "outfinal", 0 0, v0x17cbc80_0; -S_0x17c9eb0 .scope generate, "addbits[3]" "addbits[3]" 2 234, 2 234, S_0x17c9d40; - .timescale -9 -12; -P_0x17c9fa8 .param/l "i" 2 234, +C4<011>; -S_0x17ca020 .scope module, "attempt" "MiddleAddSubSLT" 2 236, 2 95, S_0x17c9eb0; - .timescale -9 -12; -L_0x17fa1e0/d .functor NOT 1, L_0x17fb6a0, C4<0>, C4<0>, C4<0>; -L_0x17fa1e0 .delay (10000,10000,10000) L_0x17fa1e0/d; -L_0x17fa980/d .functor NOT 1, L_0x17faa20, C4<0>, C4<0>, C4<0>; -L_0x17fa980 .delay (10000,10000,10000) L_0x17fa980/d; -L_0x17faac0/d .functor AND 1, L_0x17fac00, L_0x17fa980, C4<1>, C4<1>; -L_0x17faac0 .delay (20000,20000,20000) L_0x17faac0/d; -L_0x17faca0/d .functor XOR 1, L_0x17fb570, L_0x17fa750, C4<0>, C4<0>; -L_0x17faca0 .delay (40000,40000,40000) L_0x17faca0/d; -L_0x17fad90/d .functor XOR 1, L_0x17faca0, L_0x17fb7d0, C4<0>, C4<0>; -L_0x17fad90 .delay (40000,40000,40000) L_0x17fad90/d; -L_0x17fae80/d .functor AND 1, L_0x17fb570, L_0x17fa750, C4<1>, C4<1>; -L_0x17fae80 .delay (20000,20000,20000) L_0x17fae80/d; -L_0x17faff0/d .functor AND 1, L_0x17faca0, L_0x17fb7d0, C4<1>, C4<1>; -L_0x17faff0 .delay (20000,20000,20000) L_0x17faff0/d; -L_0x17fb0e0/d .functor OR 1, L_0x17fae80, L_0x17faff0, C4<0>, C4<0>; -L_0x17fb0e0 .delay (20000,20000,20000) L_0x17fb0e0/d; -v0x17ca690_0 .net "A", 0 0, L_0x17fb570; 1 drivers -v0x17ca750_0 .net "AandB", 0 0, L_0x17fae80; 1 drivers -v0x17ca7f0_0 .net "AddSubSLTSum", 0 0, L_0x17fad90; 1 drivers -v0x17ca890_0 .net "AxorB", 0 0, L_0x17faca0; 1 drivers -v0x17ca910_0 .net "B", 0 0, L_0x17fb6a0; 1 drivers -v0x17ca9c0_0 .net "BornB", 0 0, L_0x17fa750; 1 drivers -v0x17caa80_0 .net "CINandAxorB", 0 0, L_0x17faff0; 1 drivers -v0x17cab00_0 .alias "Command", 2 0, v0x17dc9d0_0; -v0x17cabd0_0 .net *"_s3", 0 0, L_0x17faa20; 1 drivers -v0x17cac50_0 .net *"_s5", 0 0, L_0x17fac00; 1 drivers -v0x17cad50_0 .net "carryin", 0 0, L_0x17fb7d0; 1 drivers -v0x17cadf0_0 .net "carryout", 0 0, L_0x17fb0e0; 1 drivers -v0x17caf00_0 .net "nB", 0 0, L_0x17fa1e0; 1 drivers -v0x17cafb0_0 .net "nCmd2", 0 0, L_0x17fa980; 1 drivers -v0x17cb0b0_0 .net "subtract", 0 0, L_0x17faac0; 1 drivers -L_0x17fa8e0 .part v0x17dda90_0, 0, 1; -L_0x17faa20 .part v0x17dda90_0, 2, 1; -L_0x17fac00 .part v0x17dda90_0, 0, 1; -S_0x17ca110 .scope module, "mux0" "TwoInMux" 2 111, 2 8, S_0x17ca020; - .timescale -9 -12; -L_0x17fa510/d .functor NOT 1, L_0x17fa8e0, C4<0>, C4<0>, C4<0>; -L_0x17fa510 .delay (10000,10000,10000) L_0x17fa510/d; -L_0x17fa570/d .functor AND 1, L_0x17fb6a0, L_0x17fa510, C4<1>, C4<1>; -L_0x17fa570 .delay (20000,20000,20000) L_0x17fa570/d; -L_0x17fa660/d .functor AND 1, L_0x17fa1e0, L_0x17fa8e0, C4<1>, C4<1>; -L_0x17fa660 .delay (20000,20000,20000) L_0x17fa660/d; -L_0x17fa750/d .functor OR 1, L_0x17fa570, L_0x17fa660, C4<0>, C4<0>; -L_0x17fa750 .delay (20000,20000,20000) L_0x17fa750/d; -v0x17ca200_0 .net "S", 0 0, L_0x17fa8e0; 1 drivers -v0x17ca280_0 .alias "in0", 0 0, v0x17ca910_0; -v0x17ca320_0 .alias "in1", 0 0, v0x17caf00_0; -v0x17ca3c0_0 .net "nS", 0 0, L_0x17fa510; 1 drivers -v0x17ca470_0 .net "out0", 0 0, L_0x17fa570; 1 drivers -v0x17ca510_0 .net "out1", 0 0, L_0x17fa660; 1 drivers -v0x17ca5f0_0 .alias "outfinal", 0 0, v0x17ca9c0_0; -S_0x17c6b90 .scope module, "trial1" "AndNand32" 2 283, 2 157, S_0x17bb1b0; - .timescale -9 -12; -P_0x17c6618 .param/l "size" 2 165, +C4<0100>; -v0x17c6a80_0 .alias "A", 3 0, v0x17dc7b0_0; -v0x17c9b60_0 .alias "AndNandOut", 3 0, v0x17dd990_0; -v0x17c9be0_0 .alias "B", 3 0, v0x17dc8d0_0; -v0x17c9c90_0 .alias "Command", 2 0, v0x17dc9d0_0; -L_0x17fe630 .part/pv L_0x17fe3c0, 1, 1, 4; -L_0x17fe6f0 .part v0x17dd890_0, 1, 1; -L_0x17fe790 .part v0x17dda10_0, 1, 1; -L_0x17ff0a0 .part/pv L_0x17fee30, 2, 1, 4; -L_0x17ff140 .part v0x17dd890_0, 2, 1; -L_0x17ff1e0 .part v0x17dda10_0, 2, 1; -L_0x17ffb10 .part/pv L_0x17ff8a0, 3, 1, 4; -L_0x17f1ef0 .part v0x17dd890_0, 3, 1; -L_0x17ffdc0 .part v0x17dda10_0, 3, 1; -L_0x1800670 .part/pv L_0x1800400, 0, 1, 4; -L_0x1800770 .part v0x17dd890_0, 0, 1; -L_0x1800810 .part v0x17dda10_0, 0, 1; -S_0x17c9020 .scope module, "attempt2" "AndNand" 2 170, 2 53, S_0x17c6b90; - .timescale -9 -12; -L_0x17ffeb0/d .functor NAND 1, L_0x1800770, L_0x1800810, C4<1>, C4<1>; -L_0x17ffeb0 .delay (10000,10000,10000) L_0x17ffeb0/d; -L_0x17fffb0/d .functor NOT 1, L_0x17ffeb0, C4<0>, C4<0>, C4<0>; -L_0x17fffb0 .delay (10000,10000,10000) L_0x17fffb0/d; -v0x17c9640_0 .net "A", 0 0, L_0x1800770; 1 drivers -v0x17c9700_0 .net "AandB", 0 0, L_0x17fffb0; 1 drivers -v0x17c9780_0 .net "AnandB", 0 0, L_0x17ffeb0; 1 drivers -v0x17c9830_0 .net "AndNandOut", 0 0, L_0x1800400; 1 drivers -v0x17c9910_0 .net "B", 0 0, L_0x1800810; 1 drivers -v0x17c9990_0 .alias "Command", 2 0, v0x17dc9d0_0; -L_0x18005d0 .part v0x17dda90_0, 0, 1; -S_0x17c9110 .scope module, "potato" "TwoInMux" 2 66, 2 8, S_0x17c9020; - .timescale -9 -12; -L_0x18000e0/d .functor NOT 1, L_0x18005d0, C4<0>, C4<0>, C4<0>; -L_0x18000e0 .delay (10000,10000,10000) L_0x18000e0/d; -L_0x18001a0/d .functor AND 1, L_0x17fffb0, L_0x18000e0, C4<1>, C4<1>; -L_0x18001a0 .delay (20000,20000,20000) L_0x18001a0/d; -L_0x18002b0/d .functor AND 1, L_0x17ffeb0, L_0x18005d0, C4<1>, C4<1>; -L_0x18002b0 .delay (20000,20000,20000) L_0x18002b0/d; -L_0x1800400/d .functor OR 1, L_0x18001a0, L_0x18002b0, C4<0>, C4<0>; -L_0x1800400 .delay (20000,20000,20000) L_0x1800400/d; -v0x17c9200_0 .net "S", 0 0, L_0x18005d0; 1 drivers -v0x17c9280_0 .alias "in0", 0 0, v0x17c9700_0; -v0x17c9300_0 .alias "in1", 0 0, v0x17c9780_0; -v0x17c93a0_0 .net "nS", 0 0, L_0x18000e0; 1 drivers -v0x17c9420_0 .net "out0", 0 0, L_0x18001a0; 1 drivers -v0x17c94c0_0 .net "out1", 0 0, L_0x18002b0; 1 drivers -v0x17c95a0_0 .alias "outfinal", 0 0, v0x17c9830_0; -S_0x17c8450 .scope generate, "andbits[1]" "andbits[1]" 2 173, 2 173, S_0x17c6b90; - .timescale -9 -12; -P_0x17c8548 .param/l "i" 2 173, +C4<01>; -S_0x17c85e0 .scope module, "attempt" "AndNand" 2 175, 2 53, S_0x17c8450; - .timescale -9 -12; -L_0x17fdeb0/d .functor NAND 1, L_0x17fe6f0, L_0x17fe790, C4<1>, C4<1>; -L_0x17fdeb0 .delay (10000,10000,10000) L_0x17fdeb0/d; -L_0x17fdf70/d .functor NOT 1, L_0x17fdeb0, C4<0>, C4<0>, C4<0>; -L_0x17fdf70 .delay (10000,10000,10000) L_0x17fdf70/d; -v0x17c8c40_0 .net "A", 0 0, L_0x17fe6f0; 1 drivers -v0x17c8d00_0 .net "AandB", 0 0, L_0x17fdf70; 1 drivers -v0x17c8d80_0 .net "AnandB", 0 0, L_0x17fdeb0; 1 drivers -v0x17c8e00_0 .net "AndNandOut", 0 0, L_0x17fe3c0; 1 drivers -v0x17c8ee0_0 .net "B", 0 0, L_0x17fe790; 1 drivers -v0x17c8f60_0 .alias "Command", 2 0, v0x17dc9d0_0; -L_0x17fe590 .part v0x17dda90_0, 0, 1; -S_0x17c86d0 .scope module, "potato" "TwoInMux" 2 66, 2 8, S_0x17c85e0; - .timescale -9 -12; -L_0x17fe0a0/d .functor NOT 1, L_0x17fe590, C4<0>, C4<0>, C4<0>; -L_0x17fe0a0 .delay (10000,10000,10000) L_0x17fe0a0/d; -L_0x17fe160/d .functor AND 1, L_0x17fdf70, L_0x17fe0a0, C4<1>, C4<1>; -L_0x17fe160 .delay (20000,20000,20000) L_0x17fe160/d; -L_0x17fe270/d .functor AND 1, L_0x17fdeb0, L_0x17fe590, C4<1>, C4<1>; -L_0x17fe270 .delay (20000,20000,20000) L_0x17fe270/d; -L_0x17fe3c0/d .functor OR 1, L_0x17fe160, L_0x17fe270, C4<0>, C4<0>; -L_0x17fe3c0 .delay (20000,20000,20000) L_0x17fe3c0/d; -v0x17c87c0_0 .net "S", 0 0, L_0x17fe590; 1 drivers -v0x17c8860_0 .alias "in0", 0 0, v0x17c8d00_0; -v0x17c8900_0 .alias "in1", 0 0, v0x17c8d80_0; -v0x17c89a0_0 .net "nS", 0 0, L_0x17fe0a0; 1 drivers -v0x17c8a20_0 .net "out0", 0 0, L_0x17fe160; 1 drivers -v0x17c8ac0_0 .net "out1", 0 0, L_0x17fe270; 1 drivers -v0x17c8ba0_0 .alias "outfinal", 0 0, v0x17c8e00_0; -S_0x17c7930 .scope generate, "andbits[2]" "andbits[2]" 2 173, 2 173, S_0x17c6b90; - .timescale -9 -12; -P_0x17c7a28 .param/l "i" 2 173, +C4<010>; -S_0x17c7aa0 .scope module, "attempt" "AndNand" 2 175, 2 53, S_0x17c7930; - .timescale -9 -12; -L_0x17fe880/d .functor NAND 1, L_0x17ff140, L_0x17ff1e0, C4<1>, C4<1>; -L_0x17fe880 .delay (10000,10000,10000) L_0x17fe880/d; -L_0x17fe9e0/d .functor NOT 1, L_0x17fe880, C4<0>, C4<0>, C4<0>; -L_0x17fe9e0 .delay (10000,10000,10000) L_0x17fe9e0/d; -v0x17c8060_0 .net "A", 0 0, L_0x17ff140; 1 drivers -v0x17c8100_0 .net "AandB", 0 0, L_0x17fe9e0; 1 drivers -v0x17c81b0_0 .net "AnandB", 0 0, L_0x17fe880; 1 drivers -v0x17c8260_0 .net "AndNandOut", 0 0, L_0x17fee30; 1 drivers -v0x17c8310_0 .net "B", 0 0, L_0x17ff1e0; 1 drivers -v0x17c8390_0 .alias "Command", 2 0, v0x17dc9d0_0; -L_0x17ff000 .part v0x17dda90_0, 0, 1; -S_0x17c7b90 .scope module, "potato" "TwoInMux" 2 66, 2 8, S_0x17c7aa0; - .timescale -9 -12; -L_0x17feb10/d .functor NOT 1, L_0x17ff000, C4<0>, C4<0>, C4<0>; -L_0x17feb10 .delay (10000,10000,10000) L_0x17feb10/d; -L_0x17febd0/d .functor AND 1, L_0x17fe9e0, L_0x17feb10, C4<1>, C4<1>; -L_0x17febd0 .delay (20000,20000,20000) L_0x17febd0/d; -L_0x17fece0/d .functor AND 1, L_0x17fe880, L_0x17ff000, C4<1>, C4<1>; -L_0x17fece0 .delay (20000,20000,20000) L_0x17fece0/d; -L_0x17fee30/d .functor OR 1, L_0x17febd0, L_0x17fece0, C4<0>, C4<0>; -L_0x17fee30 .delay (20000,20000,20000) L_0x17fee30/d; -v0x17c7c80_0 .net "S", 0 0, L_0x17ff000; 1 drivers -v0x17c7d00_0 .alias "in0", 0 0, v0x17c8100_0; -v0x17c7da0_0 .alias "in1", 0 0, v0x17c81b0_0; -v0x17c7e40_0 .net "nS", 0 0, L_0x17feb10; 1 drivers -v0x17c7ec0_0 .net "out0", 0 0, L_0x17febd0; 1 drivers -v0x17c7f60_0 .net "out1", 0 0, L_0x17fece0; 1 drivers -v0x17c7fe0_0 .alias "outfinal", 0 0, v0x17c8260_0; -S_0x17c6d00 .scope generate, "andbits[3]" "andbits[3]" 2 173, 2 173, S_0x17c6b90; - .timescale -9 -12; -P_0x17c6df8 .param/l "i" 2 173, +C4<011>; -S_0x17c6e90 .scope module, "attempt" "AndNand" 2 175, 2 53, S_0x17c6d00; - .timescale -9 -12; -L_0x17ff310/d .functor NAND 1, L_0x17f1ef0, L_0x17ffdc0, C4<1>, C4<1>; -L_0x17ff310 .delay (10000,10000,10000) L_0x17ff310/d; -L_0x17ff450/d .functor NOT 1, L_0x17ff310, C4<0>, C4<0>, C4<0>; -L_0x17ff450 .delay (10000,10000,10000) L_0x17ff450/d; -v0x17c7520_0 .net "A", 0 0, L_0x17f1ef0; 1 drivers -v0x17c75e0_0 .net "AandB", 0 0, L_0x17ff450; 1 drivers -v0x17c7660_0 .net "AnandB", 0 0, L_0x17ff310; 1 drivers -v0x17c7710_0 .net "AndNandOut", 0 0, L_0x17ff8a0; 1 drivers -v0x17c77f0_0 .net "B", 0 0, L_0x17ffdc0; 1 drivers -v0x17c7870_0 .alias "Command", 2 0, v0x17dc9d0_0; -L_0x17ffa70 .part v0x17dda90_0, 0, 1; -S_0x17c6f80 .scope module, "potato" "TwoInMux" 2 66, 2 8, S_0x17c6e90; - .timescale -9 -12; -L_0x17ff580/d .functor NOT 1, L_0x17ffa70, C4<0>, C4<0>, C4<0>; -L_0x17ff580 .delay (10000,10000,10000) L_0x17ff580/d; -L_0x17ff640/d .functor AND 1, L_0x17ff450, L_0x17ff580, C4<1>, C4<1>; -L_0x17ff640 .delay (20000,20000,20000) L_0x17ff640/d; -L_0x17ff750/d .functor AND 1, L_0x17ff310, L_0x17ffa70, C4<1>, C4<1>; -L_0x17ff750 .delay (20000,20000,20000) L_0x17ff750/d; -L_0x17ff8a0/d .functor OR 1, L_0x17ff640, L_0x17ff750, C4<0>, C4<0>; -L_0x17ff8a0 .delay (20000,20000,20000) L_0x17ff8a0/d; -v0x17c7070_0 .net "S", 0 0, L_0x17ffa70; 1 drivers -v0x17c7110_0 .alias "in0", 0 0, v0x17c75e0_0; -v0x17c71b0_0 .alias "in1", 0 0, v0x17c7660_0; -v0x17c7250_0 .net "nS", 0 0, L_0x17ff580; 1 drivers -v0x17c7300_0 .net "out0", 0 0, L_0x17ff640; 1 drivers -v0x17c73a0_0 .net "out1", 0 0, L_0x17ff750; 1 drivers -v0x17c7480_0 .alias "outfinal", 0 0, v0x17c7710_0; -S_0x17c19c0 .scope module, "trial2" "OrNorXor32" 2 284, 2 180, S_0x17bb1b0; - .timescale -9 -12; -P_0x17c0b18 .param/l "size" 2 187, +C4<0100>; -v0x17c6900_0 .alias "A", 3 0, v0x17dc7b0_0; -v0x17c6980_0 .alias "B", 3 0, v0x17dc8d0_0; -v0x17c6a00_0 .alias "Command", 2 0, v0x17dc9d0_0; -v0x17c6b10_0 .alias "OrNorXorOut", 3 0, v0x17ddb90_0; -L_0x18019c0 .part/pv L_0x1801750, 1, 1, 4; -L_0x1801a60 .part v0x17dd890_0, 1, 1; -L_0x1801b00 .part v0x17dda10_0, 1, 1; -L_0x1802cc0 .part/pv L_0x1802a50, 2, 1, 4; -L_0x1802d60 .part v0x17dd890_0, 2, 1; -L_0x1802e00 .part v0x17dda10_0, 2, 1; -L_0x1803fc0 .part/pv L_0x1803d50, 3, 1, 4; -L_0x1804060 .part v0x17dd890_0, 3, 1; -L_0x1804100 .part v0x17dda10_0, 3, 1; -L_0x18052b0 .part/pv L_0x1805040, 0, 1, 4; -L_0x18053b0 .part v0x17dd890_0, 0, 1; -L_0x1805450 .part v0x17dda10_0, 0, 1; -S_0x17c56f0 .scope module, "attempt2" "OrNorXor" 2 195, 2 70, S_0x17c19c0; - .timescale -9 -12; -L_0x18041a0/d .functor NOR 1, L_0x18053b0, L_0x1805450, C4<0>, C4<0>; -L_0x18041a0 .delay (10000,10000,10000) L_0x18041a0/d; -L_0x18042a0/d .functor NOT 1, L_0x18041a0, C4<0>, C4<0>, C4<0>; -L_0x18042a0 .delay (10000,10000,10000) L_0x18042a0/d; -L_0x18043d0/d .functor NAND 1, L_0x18053b0, L_0x1805450, C4<1>, C4<1>; -L_0x18043d0 .delay (10000,10000,10000) L_0x18043d0/d; -L_0x1804530/d .functor NAND 1, L_0x18043d0, L_0x18042a0, C4<1>, C4<1>; -L_0x1804530 .delay (10000,10000,10000) L_0x1804530/d; -L_0x1804640/d .functor NOT 1, L_0x1804530, C4<0>, C4<0>, C4<0>; -L_0x1804640 .delay (10000,10000,10000) L_0x1804640/d; -v0x17c6240_0 .net "A", 0 0, L_0x18053b0; 1 drivers -v0x17c62e0_0 .net "AnandB", 0 0, L_0x18043d0; 1 drivers -v0x17c6380_0 .net "AnorB", 0 0, L_0x18041a0; 1 drivers -v0x17c6400_0 .net "AorB", 0 0, L_0x18042a0; 1 drivers -v0x17c64e0_0 .net "AxorB", 0 0, L_0x1804640; 1 drivers -v0x17c6590_0 .net "B", 0 0, L_0x1805450; 1 drivers -v0x17c6650_0 .alias "Command", 2 0, v0x17dc9d0_0; -v0x17c66d0_0 .net "OrNorXorOut", 0 0, L_0x1805040; 1 drivers -v0x17c6750_0 .net "XorNor", 0 0, L_0x1804ac0; 1 drivers -v0x17c6820_0 .net "nXor", 0 0, L_0x1804530; 1 drivers -L_0x1804c40 .part v0x17dda90_0, 2, 1; -L_0x1805210 .part v0x17dda90_0, 0, 1; -S_0x17c5cd0 .scope module, "mux0" "TwoInMux" 2 89, 2 8, S_0x17c56f0; - .timescale -9 -12; -L_0x18047a0/d .functor NOT 1, L_0x1804c40, C4<0>, C4<0>, C4<0>; -L_0x18047a0 .delay (10000,10000,10000) L_0x18047a0/d; -L_0x1804860/d .functor AND 1, L_0x1804640, L_0x18047a0, C4<1>, C4<1>; -L_0x1804860 .delay (20000,20000,20000) L_0x1804860/d; -L_0x1804970/d .functor AND 1, L_0x18041a0, L_0x1804c40, C4<1>, C4<1>; -L_0x1804970 .delay (20000,20000,20000) L_0x1804970/d; -L_0x1804ac0/d .functor OR 1, L_0x1804860, L_0x1804970, C4<0>, C4<0>; -L_0x1804ac0 .delay (20000,20000,20000) L_0x1804ac0/d; -v0x17c5dc0_0 .net "S", 0 0, L_0x1804c40; 1 drivers -v0x17c5e80_0 .alias "in0", 0 0, v0x17c64e0_0; -v0x17c5f20_0 .alias "in1", 0 0, v0x17c6380_0; -v0x17c5fc0_0 .net "nS", 0 0, L_0x18047a0; 1 drivers -v0x17c6040_0 .net "out0", 0 0, L_0x1804860; 1 drivers -v0x17c60e0_0 .net "out1", 0 0, L_0x1804970; 1 drivers -v0x17c61c0_0 .alias "outfinal", 0 0, v0x17c6750_0; -S_0x17c57e0 .scope module, "mux1" "TwoInMux" 2 90, 2 8, S_0x17c56f0; - .timescale -9 -12; -L_0x1804ce0/d .functor NOT 1, L_0x1805210, C4<0>, C4<0>, C4<0>; -L_0x1804ce0 .delay (10000,10000,10000) L_0x1804ce0/d; -L_0x1804da0/d .functor AND 1, L_0x1804ac0, L_0x1804ce0, C4<1>, C4<1>; -L_0x1804da0 .delay (20000,20000,20000) L_0x1804da0/d; -L_0x1804ef0/d .functor AND 1, L_0x18042a0, L_0x1805210, C4<1>, C4<1>; -L_0x1804ef0 .delay (20000,20000,20000) L_0x1804ef0/d; -L_0x1805040/d .functor OR 1, L_0x1804da0, L_0x1804ef0, C4<0>, C4<0>; -L_0x1805040 .delay (20000,20000,20000) L_0x1805040/d; -v0x17c58d0_0 .net "S", 0 0, L_0x1805210; 1 drivers -v0x17c5950_0 .alias "in0", 0 0, v0x17c6750_0; -v0x17c59d0_0 .alias "in1", 0 0, v0x17c6400_0; -v0x17c5a70_0 .net "nS", 0 0, L_0x1804ce0; 1 drivers -v0x17c5af0_0 .net "out0", 0 0, L_0x1804da0; 1 drivers -v0x17c5b90_0 .net "out1", 0 0, L_0x1804ef0; 1 drivers -v0x17c5c30_0 .alias "outfinal", 0 0, v0x17c66d0_0; -S_0x17c42f0 .scope generate, "orbits[1]" "orbits[1]" 2 199, 2 199, S_0x17c19c0; - .timescale -9 -12; -P_0x17c3fd8 .param/l "i" 2 199, +C4<01>; -S_0x17c4420 .scope module, "attempt" "OrNorXor" 2 201, 2 70, S_0x17c42f0; - .timescale -9 -12; -L_0x1800710/d .functor NOR 1, L_0x1801a60, L_0x1801b00, C4<0>, C4<0>; -L_0x1800710 .delay (10000,10000,10000) L_0x1800710/d; -L_0x18009b0/d .functor NOT 1, L_0x1800710, C4<0>, C4<0>, C4<0>; -L_0x18009b0 .delay (10000,10000,10000) L_0x18009b0/d; -L_0x1800ae0/d .functor NAND 1, L_0x1801a60, L_0x1801b00, C4<1>, C4<1>; -L_0x1800ae0 .delay (10000,10000,10000) L_0x1800ae0/d; -L_0x1800c40/d .functor NAND 1, L_0x1800ae0, L_0x18009b0, C4<1>, C4<1>; -L_0x1800c40 .delay (10000,10000,10000) L_0x1800c40/d; -L_0x1800d50/d .functor NOT 1, L_0x1800c40, C4<0>, C4<0>, C4<0>; -L_0x1800d50 .delay (10000,10000,10000) L_0x1800d50/d; -v0x17c4fb0_0 .net "A", 0 0, L_0x1801a60; 1 drivers -v0x17c5050_0 .net "AnandB", 0 0, L_0x1800ae0; 1 drivers -v0x17c50f0_0 .net "AnorB", 0 0, L_0x1800710; 1 drivers -v0x17c51a0_0 .net "AorB", 0 0, L_0x18009b0; 1 drivers -v0x17c5280_0 .net "AxorB", 0 0, L_0x1800d50; 1 drivers -v0x17c5330_0 .net "B", 0 0, L_0x1801b00; 1 drivers -v0x17c53f0_0 .alias "Command", 2 0, v0x17dc9d0_0; -v0x17c5470_0 .net "OrNorXorOut", 0 0, L_0x1801750; 1 drivers -v0x17c5540_0 .net "XorNor", 0 0, L_0x18011d0; 1 drivers -v0x17c5610_0 .net "nXor", 0 0, L_0x1800c40; 1 drivers -L_0x1801350 .part v0x17dda90_0, 2, 1; -L_0x1801920 .part v0x17dda90_0, 0, 1; -S_0x17c4a40 .scope module, "mux0" "TwoInMux" 2 89, 2 8, S_0x17c4420; - .timescale -9 -12; -L_0x1800eb0/d .functor NOT 1, L_0x1801350, C4<0>, C4<0>, C4<0>; -L_0x1800eb0 .delay (10000,10000,10000) L_0x1800eb0/d; -L_0x1800f70/d .functor AND 1, L_0x1800d50, L_0x1800eb0, C4<1>, C4<1>; -L_0x1800f70 .delay (20000,20000,20000) L_0x1800f70/d; -L_0x1801080/d .functor AND 1, L_0x1800710, L_0x1801350, C4<1>, C4<1>; -L_0x1801080 .delay (20000,20000,20000) L_0x1801080/d; -L_0x18011d0/d .functor OR 1, L_0x1800f70, L_0x1801080, C4<0>, C4<0>; -L_0x18011d0 .delay (20000,20000,20000) L_0x18011d0/d; -v0x17c4b30_0 .net "S", 0 0, L_0x1801350; 1 drivers -v0x17c4bf0_0 .alias "in0", 0 0, v0x17c5280_0; -v0x17c4c90_0 .alias "in1", 0 0, v0x17c50f0_0; -v0x17c4d30_0 .net "nS", 0 0, L_0x1800eb0; 1 drivers -v0x17c4db0_0 .net "out0", 0 0, L_0x1800f70; 1 drivers -v0x17c4e50_0 .net "out1", 0 0, L_0x1801080; 1 drivers -v0x17c4f30_0 .alias "outfinal", 0 0, v0x17c5540_0; -S_0x17c4510 .scope module, "mux1" "TwoInMux" 2 90, 2 8, S_0x17c4420; - .timescale -9 -12; -L_0x18013f0/d .functor NOT 1, L_0x1801920, C4<0>, C4<0>, C4<0>; -L_0x18013f0 .delay (10000,10000,10000) L_0x18013f0/d; -L_0x18014b0/d .functor AND 1, L_0x18011d0, L_0x18013f0, C4<1>, C4<1>; -L_0x18014b0 .delay (20000,20000,20000) L_0x18014b0/d; -L_0x1801600/d .functor AND 1, L_0x18009b0, L_0x1801920, C4<1>, C4<1>; -L_0x1801600 .delay (20000,20000,20000) L_0x1801600/d; -L_0x1801750/d .functor OR 1, L_0x18014b0, L_0x1801600, C4<0>, C4<0>; -L_0x1801750 .delay (20000,20000,20000) L_0x1801750/d; -v0x17c4600_0 .net "S", 0 0, L_0x1801920; 1 drivers -v0x17c4680_0 .alias "in0", 0 0, v0x17c5540_0; -v0x17c4700_0 .alias "in1", 0 0, v0x17c51a0_0; -v0x17c47a0_0 .net "nS", 0 0, L_0x18013f0; 1 drivers -v0x17c4820_0 .net "out0", 0 0, L_0x18014b0; 1 drivers -v0x17c48c0_0 .net "out1", 0 0, L_0x1801600; 1 drivers -v0x17c49a0_0 .alias "outfinal", 0 0, v0x17c5470_0; -S_0x17c2ed0 .scope generate, "orbits[2]" "orbits[2]" 2 199, 2 199, S_0x17c19c0; - .timescale -9 -12; -P_0x17c2c98 .param/l "i" 2 199, +C4<010>; -S_0x17c3000 .scope module, "attempt" "OrNorXor" 2 201, 2 70, S_0x17c2ed0; - .timescale -9 -12; -L_0x1801ba0/d .functor NOR 1, L_0x1802d60, L_0x1802e00, C4<0>, C4<0>; -L_0x1801ba0 .delay (10000,10000,10000) L_0x1801ba0/d; -L_0x1801cb0/d .functor NOT 1, L_0x1801ba0, C4<0>, C4<0>, C4<0>; -L_0x1801cb0 .delay (10000,10000,10000) L_0x1801cb0/d; -L_0x1801de0/d .functor NAND 1, L_0x1802d60, L_0x1802e00, C4<1>, C4<1>; -L_0x1801de0 .delay (10000,10000,10000) L_0x1801de0/d; -L_0x1801f40/d .functor NAND 1, L_0x1801de0, L_0x1801cb0, C4<1>, C4<1>; -L_0x1801f40 .delay (10000,10000,10000) L_0x1801f40/d; -L_0x1802050/d .functor NOT 1, L_0x1801f40, C4<0>, C4<0>, C4<0>; -L_0x1802050 .delay (10000,10000,10000) L_0x1802050/d; -v0x17c3bd0_0 .net "A", 0 0, L_0x1802d60; 1 drivers -v0x17c3c70_0 .net "AnandB", 0 0, L_0x1801de0; 1 drivers -v0x17c3d10_0 .net "AnorB", 0 0, L_0x1801ba0; 1 drivers -v0x17c3dc0_0 .net "AorB", 0 0, L_0x1801cb0; 1 drivers -v0x17c3ea0_0 .net "AxorB", 0 0, L_0x1802050; 1 drivers -v0x17c3f50_0 .net "B", 0 0, L_0x1802e00; 1 drivers -v0x17c4010_0 .alias "Command", 2 0, v0x17dc9d0_0; -v0x17c4090_0 .net "OrNorXorOut", 0 0, L_0x1802a50; 1 drivers -v0x17c4140_0 .net "XorNor", 0 0, L_0x18024d0; 1 drivers -v0x17c4210_0 .net "nXor", 0 0, L_0x1801f40; 1 drivers -L_0x1802650 .part v0x17dda90_0, 2, 1; -L_0x1802c20 .part v0x17dda90_0, 0, 1; -S_0x17c3660 .scope module, "mux0" "TwoInMux" 2 89, 2 8, S_0x17c3000; - .timescale -9 -12; -L_0x18021b0/d .functor NOT 1, L_0x1802650, C4<0>, C4<0>, C4<0>; -L_0x18021b0 .delay (10000,10000,10000) L_0x18021b0/d; -L_0x1802270/d .functor AND 1, L_0x1802050, L_0x18021b0, C4<1>, C4<1>; -L_0x1802270 .delay (20000,20000,20000) L_0x1802270/d; -L_0x1802380/d .functor AND 1, L_0x1801ba0, L_0x1802650, C4<1>, C4<1>; -L_0x1802380 .delay (20000,20000,20000) L_0x1802380/d; -L_0x18024d0/d .functor OR 1, L_0x1802270, L_0x1802380, C4<0>, C4<0>; -L_0x18024d0 .delay (20000,20000,20000) L_0x18024d0/d; -v0x17c3750_0 .net "S", 0 0, L_0x1802650; 1 drivers -v0x17c3810_0 .alias "in0", 0 0, v0x17c3ea0_0; -v0x17c38b0_0 .alias "in1", 0 0, v0x17c3d10_0; -v0x17c3950_0 .net "nS", 0 0, L_0x18021b0; 1 drivers -v0x17c39d0_0 .net "out0", 0 0, L_0x1802270; 1 drivers -v0x17c3a70_0 .net "out1", 0 0, L_0x1802380; 1 drivers -v0x17c3b50_0 .alias "outfinal", 0 0, v0x17c4140_0; -S_0x17c30f0 .scope module, "mux1" "TwoInMux" 2 90, 2 8, S_0x17c3000; - .timescale -9 -12; -L_0x18026f0/d .functor NOT 1, L_0x1802c20, C4<0>, C4<0>, C4<0>; -L_0x18026f0 .delay (10000,10000,10000) L_0x18026f0/d; -L_0x18027b0/d .functor AND 1, L_0x18024d0, L_0x18026f0, C4<1>, C4<1>; -L_0x18027b0 .delay (20000,20000,20000) L_0x18027b0/d; -L_0x1802900/d .functor AND 1, L_0x1801cb0, L_0x1802c20, C4<1>, C4<1>; -L_0x1802900 .delay (20000,20000,20000) L_0x1802900/d; -L_0x1802a50/d .functor OR 1, L_0x18027b0, L_0x1802900, C4<0>, C4<0>; -L_0x1802a50 .delay (20000,20000,20000) L_0x1802a50/d; -v0x17c31e0_0 .net "S", 0 0, L_0x1802c20; 1 drivers -v0x17c3280_0 .alias "in0", 0 0, v0x17c4140_0; -v0x17c3320_0 .alias "in1", 0 0, v0x17c3dc0_0; -v0x17c33c0_0 .net "nS", 0 0, L_0x18026f0; 1 drivers -v0x17c3440_0 .net "out0", 0 0, L_0x18027b0; 1 drivers -v0x17c34e0_0 .net "out1", 0 0, L_0x1802900; 1 drivers -v0x17c35c0_0 .alias "outfinal", 0 0, v0x17c4090_0; -S_0x17c1b30 .scope generate, "orbits[3]" "orbits[3]" 2 199, 2 199, S_0x17c19c0; - .timescale -9 -12; -P_0x17c1c28 .param/l "i" 2 199, +C4<011>; -S_0x17c1cc0 .scope module, "attempt" "OrNorXor" 2 201, 2 70, S_0x17c1b30; - .timescale -9 -12; -L_0x1802ee0/d .functor NOR 1, L_0x1804060, L_0x1804100, C4<0>, C4<0>; -L_0x1802ee0 .delay (10000,10000,10000) L_0x1802ee0/d; -L_0x1802fd0/d .functor NOT 1, L_0x1802ee0, C4<0>, C4<0>, C4<0>; -L_0x1802fd0 .delay (10000,10000,10000) L_0x1802fd0/d; -L_0x18030e0/d .functor NAND 1, L_0x1804060, L_0x1804100, C4<1>, C4<1>; -L_0x18030e0 .delay (10000,10000,10000) L_0x18030e0/d; -L_0x1803240/d .functor NAND 1, L_0x18030e0, L_0x1802fd0, C4<1>, C4<1>; -L_0x1803240 .delay (10000,10000,10000) L_0x1803240/d; -L_0x1803350/d .functor NOT 1, L_0x1803240, C4<0>, C4<0>, C4<0>; -L_0x1803350 .delay (10000,10000,10000) L_0x1803350/d; -v0x17c2890_0 .net "A", 0 0, L_0x1804060; 1 drivers -v0x17c2930_0 .net "AnandB", 0 0, L_0x18030e0; 1 drivers -v0x17c29d0_0 .net "AnorB", 0 0, L_0x1802ee0; 1 drivers -v0x17c2a80_0 .net "AorB", 0 0, L_0x1802fd0; 1 drivers -v0x17c2b60_0 .net "AxorB", 0 0, L_0x1803350; 1 drivers -v0x17c2c10_0 .net "B", 0 0, L_0x1804100; 1 drivers -v0x17c2cd0_0 .alias "Command", 2 0, v0x17dc9d0_0; -v0x17c2d50_0 .net "OrNorXorOut", 0 0, L_0x1803d50; 1 drivers -v0x17c2dd0_0 .net "XorNor", 0 0, L_0x18037d0; 1 drivers -v0x17c2e50_0 .net "nXor", 0 0, L_0x1803240; 1 drivers -L_0x1803950 .part v0x17dda90_0, 2, 1; -L_0x1803f20 .part v0x17dda90_0, 0, 1; -S_0x17c2320 .scope module, "mux0" "TwoInMux" 2 89, 2 8, S_0x17c1cc0; - .timescale -9 -12; -L_0x18034b0/d .functor NOT 1, L_0x1803950, C4<0>, C4<0>, C4<0>; -L_0x18034b0 .delay (10000,10000,10000) L_0x18034b0/d; -L_0x1803570/d .functor AND 1, L_0x1803350, L_0x18034b0, C4<1>, C4<1>; -L_0x1803570 .delay (20000,20000,20000) L_0x1803570/d; -L_0x1803680/d .functor AND 1, L_0x1802ee0, L_0x1803950, C4<1>, C4<1>; -L_0x1803680 .delay (20000,20000,20000) L_0x1803680/d; -L_0x18037d0/d .functor OR 1, L_0x1803570, L_0x1803680, C4<0>, C4<0>; -L_0x18037d0 .delay (20000,20000,20000) L_0x18037d0/d; -v0x17c2410_0 .net "S", 0 0, L_0x1803950; 1 drivers -v0x17c24d0_0 .alias "in0", 0 0, v0x17c2b60_0; -v0x17c2570_0 .alias "in1", 0 0, v0x17c29d0_0; -v0x17c2610_0 .net "nS", 0 0, L_0x18034b0; 1 drivers -v0x17c2690_0 .net "out0", 0 0, L_0x1803570; 1 drivers -v0x17c2730_0 .net "out1", 0 0, L_0x1803680; 1 drivers -v0x17c2810_0 .alias "outfinal", 0 0, v0x17c2dd0_0; -S_0x17c1db0 .scope module, "mux1" "TwoInMux" 2 90, 2 8, S_0x17c1cc0; - .timescale -9 -12; -L_0x18039f0/d .functor NOT 1, L_0x1803f20, C4<0>, C4<0>, C4<0>; -L_0x18039f0 .delay (10000,10000,10000) L_0x18039f0/d; -L_0x1803ab0/d .functor AND 1, L_0x18037d0, L_0x18039f0, C4<1>, C4<1>; -L_0x1803ab0 .delay (20000,20000,20000) L_0x1803ab0/d; -L_0x1803c00/d .functor AND 1, L_0x1802fd0, L_0x1803f20, C4<1>, C4<1>; -L_0x1803c00 .delay (20000,20000,20000) L_0x1803c00/d; -L_0x1803d50/d .functor OR 1, L_0x1803ab0, L_0x1803c00, C4<0>, C4<0>; -L_0x1803d50 .delay (20000,20000,20000) L_0x1803d50/d; -v0x17c1ea0_0 .net "S", 0 0, L_0x1803f20; 1 drivers -v0x17c1f40_0 .alias "in0", 0 0, v0x17c2dd0_0; -v0x17c1fe0_0 .alias "in1", 0 0, v0x17c2a80_0; -v0x17c2080_0 .net "nS", 0 0, L_0x18039f0; 1 drivers -v0x17c2100_0 .net "out0", 0 0, L_0x1803ab0; 1 drivers -v0x17c21a0_0 .net "out1", 0 0, L_0x1803c00; 1 drivers -v0x17c2280_0 .alias "outfinal", 0 0, v0x17c2d50_0; -S_0x17c1040 .scope module, "ZeroMux0case" "FourInMux" 2 287, 2 29, S_0x17bb1b0; - .timescale -9 -12; -L_0x1805350/d .functor NOT 1, L_0x1805c90, C4<0>, C4<0>, C4<0>; -L_0x1805350 .delay (10000,10000,10000) L_0x1805350/d; -L_0x18055a0/d .functor NOT 1, L_0x17f7960, C4<0>, C4<0>, C4<0>; -L_0x18055a0 .delay (10000,10000,10000) L_0x18055a0/d; -L_0x1805660/d .functor NAND 1, L_0x1805350, L_0x18055a0, L_0x1805f90, C4<1>; -L_0x1805660 .delay (10000,10000,10000) L_0x1805660/d; -L_0x1805750/d .functor NAND 1, L_0x1805c90, L_0x18055a0, L_0x1805dc0, C4<1>; -L_0x1805750 .delay (10000,10000,10000) L_0x1805750/d; -L_0x1805840/d .functor NAND 1, L_0x1805350, L_0x17f7960, L_0x1805e60, C4<1>; -L_0x1805840 .delay (10000,10000,10000) L_0x1805840/d; -L_0x1805930/d .functor NAND 1, L_0x1805c90, L_0x17f7960, L_0x1806220, C4<1>; -L_0x1805930 .delay (10000,10000,10000) L_0x1805930/d; -L_0x1805a10/d .functor NAND 1, L_0x1805660, L_0x1805750, L_0x1805840, L_0x1805930; -L_0x1805a10 .delay (10000,10000,10000) L_0x1805a10/d; -v0x17c1130_0 .net "S0", 0 0, L_0x1805c90; 1 drivers -v0x17c11f0_0 .net "S1", 0 0, L_0x17f7960; 1 drivers -v0x17c1290_0 .net "in0", 0 0, L_0x1805f90; 1 drivers -v0x17c1330_0 .net "in1", 0 0, L_0x1805dc0; 1 drivers -v0x17c13b0_0 .net "in2", 0 0, L_0x1805e60; 1 drivers -v0x17c1450_0 .net "in3", 0 0, L_0x1806220; 1 drivers -v0x17c14f0_0 .net "nS0", 0 0, L_0x1805350; 1 drivers -v0x17c1590_0 .net "nS1", 0 0, L_0x18055a0; 1 drivers -v0x17c1630_0 .net "out", 0 0, L_0x1805a10; 1 drivers -v0x17c16d0_0 .net "out0", 0 0, L_0x1805660; 1 drivers -v0x17c1770_0 .net "out1", 0 0, L_0x1805750; 1 drivers -v0x17c1810_0 .net "out2", 0 0, L_0x1805840; 1 drivers -v0x17c1920_0 .net "out3", 0 0, L_0x1805930; 1 drivers -S_0x17c0680 .scope module, "OneMux0case" "FourInMux" 2 288, 2 29, S_0x17bb1b0; - .timescale -9 -12; -L_0x18062c0/d .functor NOT 1, L_0x1806030, C4<0>, C4<0>, C4<0>; -L_0x18062c0 .delay (10000,10000,10000) L_0x18062c0/d; -L_0x1806370/d .functor NOT 1, L_0x1806160, C4<0>, C4<0>, C4<0>; -L_0x1806370 .delay (10000,10000,10000) L_0x1806370/d; -L_0x18063d0/d .functor NAND 1, L_0x18062c0, L_0x1806370, L_0x1806a50, C4<1>; -L_0x18063d0 .delay (10000,10000,10000) L_0x18063d0/d; -L_0x1806510/d .functor NAND 1, L_0x1806030, L_0x1806370, L_0x1806af0, C4<1>; -L_0x1806510 .delay (10000,10000,10000) L_0x1806510/d; -L_0x1806600/d .functor NAND 1, L_0x18062c0, L_0x1806160, L_0x1806b90, C4<1>; -L_0x1806600 .delay (10000,10000,10000) L_0x1806600/d; -L_0x18066f0/d .functor NAND 1, L_0x1806030, L_0x1806160, L_0x1806f50, C4<1>; -L_0x18066f0 .delay (10000,10000,10000) L_0x18066f0/d; -L_0x18067d0/d .functor NAND 1, L_0x18063d0, L_0x1806510, L_0x1806600, L_0x18066f0; -L_0x18067d0 .delay (10000,10000,10000) L_0x18067d0/d; -v0x17c0770_0 .net "S0", 0 0, L_0x1806030; 1 drivers -v0x17c0830_0 .net "S1", 0 0, L_0x1806160; 1 drivers -v0x17c08d0_0 .net "in0", 0 0, L_0x1806a50; 1 drivers -v0x17c0970_0 .net "in1", 0 0, L_0x1806af0; 1 drivers -v0x17c09f0_0 .net "in2", 0 0, L_0x1806b90; 1 drivers -v0x17c0a90_0 .net "in3", 0 0, L_0x1806f50; 1 drivers -v0x17c0b70_0 .net "nS0", 0 0, L_0x18062c0; 1 drivers -v0x17c0c10_0 .net "nS1", 0 0, L_0x1806370; 1 drivers -v0x17c0cb0_0 .net "out", 0 0, L_0x18067d0; 1 drivers -v0x17c0d50_0 .net "out0", 0 0, L_0x18063d0; 1 drivers -v0x17c0df0_0 .net "out1", 0 0, L_0x1806510; 1 drivers -v0x17c0e90_0 .net "out2", 0 0, L_0x1806600; 1 drivers -v0x17c0fa0_0 .net "out3", 0 0, L_0x18066f0; 1 drivers -S_0x17c0130 .scope module, "TwoMux0case" "TwoInMux" 2 289, 2 8, S_0x17bb1b0; - .timescale -9 -12; -L_0x1806ce0/d .functor NOT 1, L_0x1807500, C4<0>, C4<0>, C4<0>; -L_0x1806ce0 .delay (10000,10000,10000) L_0x1806ce0/d; -L_0x1806dd0/d .functor AND 1, L_0x1807040, L_0x1806ce0, C4<1>, C4<1>; -L_0x1806dd0 .delay (20000,20000,20000) L_0x1806dd0/d; -L_0x1807270/d .functor AND 1, L_0x18077e0, L_0x1807500, C4<1>, C4<1>; -L_0x1807270 .delay (20000,20000,20000) L_0x1807270/d; -L_0x1807320/d .functor OR 1, L_0x1806dd0, L_0x1807270, C4<0>, C4<0>; -L_0x1807320 .delay (20000,20000,20000) L_0x1807320/d; -v0x17c0220_0 .net "S", 0 0, L_0x1807500; 1 drivers -v0x17c02e0_0 .net "in0", 0 0, L_0x1807040; 1 drivers -v0x17c0380_0 .net "in1", 0 0, L_0x18077e0; 1 drivers -v0x17c0420_0 .net "nS", 0 0, L_0x1806ce0; 1 drivers -v0x17c04a0_0 .net "out0", 0 0, L_0x1806dd0; 1 drivers -v0x17c0540_0 .net "out1", 0 0, L_0x1807270; 1 drivers -v0x17c05e0_0 .net "outfinal", 0 0, L_0x1807320; 1 drivers -S_0x17be710 .scope generate, "muxbits[1]" "muxbits[1]" 2 295, 2 295, S_0x17bb1b0; - .timescale -9 -12; -P_0x17bd868 .param/l "i" 2 295, +C4<01>; -S_0x17bf7b0 .scope module, "ZeroMux" "FourInMux" 2 297, 2 29, S_0x17be710; - .timescale -9 -12; -L_0x17f02f0/d .functor NOT 1, L_0x17f0c30, C4<0>, C4<0>, C4<0>; -L_0x17f02f0 .delay (10000,10000,10000) L_0x17f02f0/d; -L_0x17f0540/d .functor NOT 1, L_0x17f0d60, C4<0>, C4<0>, C4<0>; -L_0x17f0540 .delay (10000,10000,10000) L_0x17f0540/d; -L_0x17f0600/d .functor NAND 1, L_0x17f02f0, L_0x17f0540, L_0x17f0e90, C4<1>; -L_0x17f0600 .delay (10000,10000,10000) L_0x17f0600/d; -L_0x17f06f0/d .functor NAND 1, L_0x17f0c30, L_0x17f0540, L_0x17f0f30, C4<1>; -L_0x17f06f0 .delay (10000,10000,10000) L_0x17f06f0/d; -L_0x17f07e0/d .functor NAND 1, L_0x17f02f0, L_0x17f0d60, L_0x17f0fd0, C4<1>; -L_0x17f07e0 .delay (10000,10000,10000) L_0x17f07e0/d; -L_0x17f08d0/d .functor NAND 1, L_0x17f0c30, L_0x17f0d60, L_0x17f11d0, C4<1>; -L_0x17f08d0 .delay (10000,10000,10000) L_0x17f08d0/d; -L_0x17f09b0/d .functor NAND 1, L_0x17f0600, L_0x17f06f0, L_0x17f07e0, L_0x17f08d0; -L_0x17f09b0 .delay (10000,10000,10000) L_0x17f09b0/d; -v0x17bf8a0_0 .net "S0", 0 0, L_0x17f0c30; 1 drivers -v0x17bf960_0 .net "S1", 0 0, L_0x17f0d60; 1 drivers -v0x17bfa00_0 .net "in0", 0 0, L_0x17f0e90; 1 drivers -v0x17bfaa0_0 .net "in1", 0 0, L_0x17f0f30; 1 drivers -v0x17bfb20_0 .net "in2", 0 0, L_0x17f0fd0; 1 drivers -v0x17bfbc0_0 .net "in3", 0 0, L_0x17f11d0; 1 drivers -v0x17bfc60_0 .net "nS0", 0 0, L_0x17f02f0; 1 drivers -v0x17bfd00_0 .net "nS1", 0 0, L_0x17f0540; 1 drivers -v0x17bfda0_0 .net "out", 0 0, L_0x17f09b0; 1 drivers -v0x17bfe40_0 .net "out0", 0 0, L_0x17f0600; 1 drivers -v0x17bfee0_0 .net "out1", 0 0, L_0x17f06f0; 1 drivers -v0x17bff80_0 .net "out2", 0 0, L_0x17f07e0; 1 drivers -v0x17c0090_0 .net "out3", 0 0, L_0x17f08d0; 1 drivers -S_0x17bedf0 .scope module, "OneMux" "FourInMux" 2 298, 2 29, S_0x17be710; - .timescale -9 -12; -L_0x17f1270/d .functor NOT 1, L_0x17f1b90, C4<0>, C4<0>, C4<0>; -L_0x17f1270 .delay (10000,10000,10000) L_0x17f1270/d; -L_0x17f1360/d .functor NOT 1, L_0x17f1cc0, C4<0>, C4<0>, C4<0>; -L_0x17f1360 .delay (10000,10000,10000) L_0x17f1360/d; -L_0x17f1400/d .functor NAND 1, L_0x17f1270, L_0x17f1360, L_0x17f1e50, C4<1>; -L_0x17f1400 .delay (10000,10000,10000) L_0x17f1400/d; -L_0x17f1540/d .functor NAND 1, L_0x17f1b90, L_0x17f1360, L_0x17f2000, C4<1>; -L_0x17f1540 .delay (10000,10000,10000) L_0x17f1540/d; -L_0x17f1630/d .functor NAND 1, L_0x17f1270, L_0x17f1cc0, L_0x17f20a0, C4<1>; -L_0x17f1630 .delay (10000,10000,10000) L_0x17f1630/d; -L_0x17f1720/d .functor NAND 1, L_0x17f1b90, L_0x17f1cc0, L_0x17f2140, C4<1>; -L_0x17f1720 .delay (10000,10000,10000) L_0x17f1720/d; -L_0x17f1890/d .functor NAND 1, L_0x17f1400, L_0x17f1540, L_0x17f1630, L_0x17f1720; -L_0x17f1890 .delay (10000,10000,10000) L_0x17f1890/d; -v0x17beee0_0 .net "S0", 0 0, L_0x17f1b90; 1 drivers -v0x17befa0_0 .net "S1", 0 0, L_0x17f1cc0; 1 drivers -v0x17bf040_0 .net "in0", 0 0, L_0x17f1e50; 1 drivers -v0x17bf0e0_0 .net "in1", 0 0, L_0x17f2000; 1 drivers -v0x17bf160_0 .net "in2", 0 0, L_0x17f20a0; 1 drivers -v0x17bf200_0 .net "in3", 0 0, L_0x17f2140; 1 drivers -v0x17bf2e0_0 .net "nS0", 0 0, L_0x17f1270; 1 drivers -v0x17bf380_0 .net "nS1", 0 0, L_0x17f1360; 1 drivers -v0x17bf420_0 .net "out", 0 0, L_0x17f1890; 1 drivers -v0x17bf4c0_0 .net "out0", 0 0, L_0x17f1400; 1 drivers -v0x17bf560_0 .net "out1", 0 0, L_0x17f1540; 1 drivers -v0x17bf600_0 .net "out2", 0 0, L_0x17f1630; 1 drivers -v0x17bf710_0 .net "out3", 0 0, L_0x17f1720; 1 drivers -S_0x17be880 .scope module, "TwoMux" "TwoInMux" 2 299, 2 8, S_0x17be710; - .timescale -9 -12; -L_0x17f1df0/d .functor NOT 1, L_0x17f2690, C4<0>, C4<0>, C4<0>; -L_0x17f1df0 .delay (10000,10000,10000) L_0x17f1df0/d; -L_0x17f2280/d .functor AND 1, L_0x17f2730, L_0x17f1df0, C4<1>, C4<1>; -L_0x17f2280 .delay (20000,20000,20000) L_0x17f2280/d; -L_0x17f2370/d .functor AND 1, L_0x17f2870, L_0x17f2690, C4<1>, C4<1>; -L_0x17f2370 .delay (20000,20000,20000) L_0x17f2370/d; -L_0x17f2460/d .functor OR 1, L_0x17f2280, L_0x17f2370, C4<0>, C4<0>; -L_0x17f2460 .delay (20000,20000,20000) L_0x17f2460/d; -v0x17be970_0 .net "S", 0 0, L_0x17f2690; 1 drivers -v0x17bea10_0 .net "in0", 0 0, L_0x17f2730; 1 drivers -v0x17beab0_0 .net "in1", 0 0, L_0x17f2870; 1 drivers -v0x17beb50_0 .net "nS", 0 0, L_0x17f1df0; 1 drivers -v0x17bebd0_0 .net "out0", 0 0, L_0x17f2280; 1 drivers -v0x17bec70_0 .net "out1", 0 0, L_0x17f2370; 1 drivers -v0x17bed50_0 .net "outfinal", 0 0, L_0x17f2460; 1 drivers -S_0x17bccf0 .scope generate, "muxbits[2]" "muxbits[2]" 2 295, 2 295, S_0x17bb1b0; - .timescale -9 -12; -P_0x17bbe48 .param/l "i" 2 295, +C4<010>; -S_0x17bdd90 .scope module, "ZeroMux" "FourInMux" 2 297, 2 29, S_0x17bccf0; - .timescale -9 -12; -L_0x17e9500/d .functor NOT 1, L_0x17f3290, C4<0>, C4<0>, C4<0>; -L_0x17e9500 .delay (10000,10000,10000) L_0x17e9500/d; -L_0x17f2ae0/d .functor NOT 1, L_0x17f29b0, C4<0>, C4<0>, C4<0>; -L_0x17f2ae0 .delay (10000,10000,10000) L_0x17f2ae0/d; -L_0x17f2b80/d .functor NAND 1, L_0x17e9500, L_0x17f2ae0, L_0x17f3500, C4<1>; -L_0x17f2b80 .delay (10000,10000,10000) L_0x17f2b80/d; -L_0x17f2cc0/d .functor NAND 1, L_0x17f3290, L_0x17f2ae0, L_0x17f33c0, C4<1>; -L_0x17f2cc0 .delay (10000,10000,10000) L_0x17f2cc0/d; -L_0x17f2db0/d .functor NAND 1, L_0x17e9500, L_0x17f29b0, L_0x17f3660, C4<1>; -L_0x17f2db0 .delay (10000,10000,10000) L_0x17f2db0/d; -L_0x17f2ea0/d .functor NAND 1, L_0x17f3290, L_0x17f29b0, L_0x17f35a0, C4<1>; -L_0x17f2ea0 .delay (10000,10000,10000) L_0x17f2ea0/d; -L_0x17f2fe0/d .functor NAND 1, L_0x17f2b80, L_0x17f2cc0, L_0x17f2db0, L_0x17f2ea0; -L_0x17f2fe0 .delay (10000,10000,10000) L_0x17f2fe0/d; -v0x17bde80_0 .net "S0", 0 0, L_0x17f3290; 1 drivers -v0x17bdf40_0 .net "S1", 0 0, L_0x17f29b0; 1 drivers -v0x17bdfe0_0 .net "in0", 0 0, L_0x17f3500; 1 drivers -v0x17be080_0 .net "in1", 0 0, L_0x17f33c0; 1 drivers -v0x17be100_0 .net "in2", 0 0, L_0x17f3660; 1 drivers -v0x17be1a0_0 .net "in3", 0 0, L_0x17f35a0; 1 drivers -v0x17be240_0 .net "nS0", 0 0, L_0x17e9500; 1 drivers -v0x17be2e0_0 .net "nS1", 0 0, L_0x17f2ae0; 1 drivers -v0x17be380_0 .net "out", 0 0, L_0x17f2fe0; 1 drivers -v0x17be420_0 .net "out0", 0 0, L_0x17f2b80; 1 drivers -v0x17be4c0_0 .net "out1", 0 0, L_0x17f2cc0; 1 drivers -v0x17be560_0 .net "out2", 0 0, L_0x17f2db0; 1 drivers -v0x17be670_0 .net "out3", 0 0, L_0x17f2ea0; 1 drivers -S_0x17bd3d0 .scope module, "OneMux" "FourInMux" 2 298, 2 29, S_0x17bccf0; - .timescale -9 -12; -L_0x17f3870/d .functor NOT 1, L_0x17f3750, C4<0>, C4<0>, C4<0>; -L_0x17f3870 .delay (10000,10000,10000) L_0x17f3870/d; -L_0x17f3960/d .functor NOT 1, L_0x17e2910, C4<0>, C4<0>, C4<0>; -L_0x17f3960 .delay (10000,10000,10000) L_0x17f3960/d; -L_0x17f3a00/d .functor NAND 1, L_0x17f3870, L_0x17f3960, L_0x17f4170, C4<1>; -L_0x17f3a00 .delay (10000,10000,10000) L_0x17f3a00/d; -L_0x17f3b40/d .functor NAND 1, L_0x17f3750, L_0x17f3960, L_0x17e2b30, C4<1>; -L_0x17f3b40 .delay (10000,10000,10000) L_0x17f3b40/d; -L_0x17f3c30/d .functor NAND 1, L_0x17f3870, L_0x17e2910, L_0x17e2a40, C4<1>; -L_0x17f3c30 .delay (10000,10000,10000) L_0x17f3c30/d; -L_0x17f3d50/d .functor NAND 1, L_0x17f3750, L_0x17e2910, L_0x17f4af0, C4<1>; -L_0x17f3d50 .delay (10000,10000,10000) L_0x17f3d50/d; -L_0x17f3ec0/d .functor NAND 1, L_0x17f3a00, L_0x17f3b40, L_0x17f3c30, L_0x17f3d50; -L_0x17f3ec0 .delay (10000,10000,10000) L_0x17f3ec0/d; -v0x17bd4c0_0 .net "S0", 0 0, L_0x17f3750; 1 drivers -v0x17bd580_0 .net "S1", 0 0, L_0x17e2910; 1 drivers -v0x17bd620_0 .net "in0", 0 0, L_0x17f4170; 1 drivers -v0x17bd6c0_0 .net "in1", 0 0, L_0x17e2b30; 1 drivers -v0x17bd740_0 .net "in2", 0 0, L_0x17e2a40; 1 drivers -v0x17bd7e0_0 .net "in3", 0 0, L_0x17f4af0; 1 drivers -v0x17bd8c0_0 .net "nS0", 0 0, L_0x17f3870; 1 drivers -v0x17bd960_0 .net "nS1", 0 0, L_0x17f3960; 1 drivers -v0x17bda00_0 .net "out", 0 0, L_0x17f3ec0; 1 drivers -v0x17bdaa0_0 .net "out0", 0 0, L_0x17f3a00; 1 drivers -v0x17bdb40_0 .net "out1", 0 0, L_0x17f3b40; 1 drivers -v0x17bdbe0_0 .net "out2", 0 0, L_0x17f3c30; 1 drivers -v0x17bdcf0_0 .net "out3", 0 0, L_0x17f3d50; 1 drivers -S_0x17bce60 .scope module, "TwoMux" "TwoInMux" 2 299, 2 8, S_0x17bccf0; - .timescale -9 -12; -L_0x17e2bd0/d .functor NOT 1, L_0x17f5020, C4<0>, C4<0>, C4<0>; -L_0x17e2bd0 .delay (10000,10000,10000) L_0x17e2bd0/d; -L_0x17f4ca0/d .functor AND 1, L_0x17f4b90, L_0x17e2bd0, C4<1>, C4<1>; -L_0x17f4ca0 .delay (20000,20000,20000) L_0x17f4ca0/d; -L_0x17f4d50/d .functor AND 1, L_0x17f5270, L_0x17f5020, C4<1>, C4<1>; -L_0x17f4d50 .delay (20000,20000,20000) L_0x17f4d50/d; -L_0x17f4e40/d .functor OR 1, L_0x17f4ca0, L_0x17f4d50, C4<0>, C4<0>; -L_0x17f4e40 .delay (20000,20000,20000) L_0x17f4e40/d; -v0x17bcf50_0 .net "S", 0 0, L_0x17f5020; 1 drivers -v0x17bcff0_0 .net "in0", 0 0, L_0x17f4b90; 1 drivers -v0x17bd090_0 .net "in1", 0 0, L_0x17f5270; 1 drivers -v0x17bd130_0 .net "nS", 0 0, L_0x17e2bd0; 1 drivers -v0x17bd1b0_0 .net "out0", 0 0, L_0x17f4ca0; 1 drivers -v0x17bd250_0 .net "out1", 0 0, L_0x17f4d50; 1 drivers -v0x17bd330_0 .net "outfinal", 0 0, L_0x17f4e40; 1 drivers -S_0x17bb2e0 .scope generate, "muxbits[3]" "muxbits[3]" 2 295, 2 295, S_0x17bb1b0; - .timescale -9 -12; -P_0x17bb3d8 .param/l "i" 2 295, +C4<011>; -S_0x17bc370 .scope module, "ZeroMux" "FourInMux" 2 297, 2 29, S_0x17bb2e0; - .timescale -9 -12; -L_0x17f50c0/d .functor NOT 1, L_0x17f5c80, C4<0>, C4<0>, C4<0>; -L_0x17f50c0 .delay (10000,10000,10000) L_0x17f50c0/d; -L_0x17f5160/d .functor NOT 1, L_0x17f53a0, C4<0>, C4<0>, C4<0>; -L_0x17f5160 .delay (10000,10000,10000) L_0x17f5160/d; -L_0x17f5510/d .functor NAND 1, L_0x17f50c0, L_0x17f5160, L_0x17f5ef0, C4<1>; -L_0x17f5510 .delay (10000,10000,10000) L_0x17f5510/d; -L_0x17f5650/d .functor NAND 1, L_0x17f5c80, L_0x17f5160, L_0x17e85e0, C4<1>; -L_0x17f5650 .delay (10000,10000,10000) L_0x17f5650/d; -L_0x17f5740/d .functor NAND 1, L_0x17f50c0, L_0x17f53a0, L_0x17f5db0, C4<1>; -L_0x17f5740 .delay (10000,10000,10000) L_0x17f5740/d; -L_0x17f5860/d .functor NAND 1, L_0x17f5c80, L_0x17f53a0, L_0x17f6300, C4<1>; -L_0x17f5860 .delay (10000,10000,10000) L_0x17f5860/d; -L_0x17f59d0/d .functor NAND 1, L_0x17f5510, L_0x17f5650, L_0x17f5740, L_0x17f5860; -L_0x17f59d0 .delay (10000,10000,10000) L_0x17f59d0/d; -v0x17bc460_0 .net "S0", 0 0, L_0x17f5c80; 1 drivers -v0x17bc520_0 .net "S1", 0 0, L_0x17f53a0; 1 drivers -v0x17bc5c0_0 .net "in0", 0 0, L_0x17f5ef0; 1 drivers -v0x17bc660_0 .net "in1", 0 0, L_0x17e85e0; 1 drivers -v0x17bc6e0_0 .net "in2", 0 0, L_0x17f5db0; 1 drivers -v0x17bc780_0 .net "in3", 0 0, L_0x17f6300; 1 drivers -v0x17bc820_0 .net "nS0", 0 0, L_0x17f50c0; 1 drivers -v0x17bc8c0_0 .net "nS1", 0 0, L_0x17f5160; 1 drivers -v0x17bc960_0 .net "out", 0 0, L_0x17f59d0; 1 drivers -v0x17bca00_0 .net "out0", 0 0, L_0x17f5510; 1 drivers -v0x17bcaa0_0 .net "out1", 0 0, L_0x17f5650; 1 drivers -v0x17bcb40_0 .net "out2", 0 0, L_0x17f5740; 1 drivers -v0x17bcc50_0 .net "out3", 0 0, L_0x17f5860; 1 drivers -S_0x17bb9b0 .scope module, "OneMux" "FourInMux" 2 298, 2 29, S_0x17bb2e0; - .timescale -9 -12; -L_0x17e8680/d .functor NOT 1, L_0x17f61a0, C4<0>, C4<0>, C4<0>; -L_0x17e8680 .delay (10000,10000,10000) L_0x17e8680/d; -L_0x17f6430/d .functor NOT 1, L_0x17f6db0, C4<0>, C4<0>, C4<0>; -L_0x17f6430 .delay (10000,10000,10000) L_0x17f6430/d; -L_0x17f64d0/d .functor NAND 1, L_0x17e8680, L_0x17f6430, L_0x17f6c40, C4<1>; -L_0x17f64d0 .delay (10000,10000,10000) L_0x17f64d0/d; -L_0x17f6610/d .functor NAND 1, L_0x17f61a0, L_0x17f6430, L_0x17f6ce0, C4<1>; -L_0x17f6610 .delay (10000,10000,10000) L_0x17f6610/d; -L_0x17f6700/d .functor NAND 1, L_0x17e8680, L_0x17f6db0, L_0x17f7070, C4<1>; -L_0x17f6700 .delay (10000,10000,10000) L_0x17f6700/d; -L_0x17f6820/d .functor NAND 1, L_0x17f61a0, L_0x17f6db0, L_0x17f7160, C4<1>; -L_0x17f6820 .delay (10000,10000,10000) L_0x17f6820/d; -L_0x17f6990/d .functor NAND 1, L_0x17f64d0, L_0x17f6610, L_0x17f6700, L_0x17f6820; -L_0x17f6990 .delay (10000,10000,10000) L_0x17f6990/d; -v0x17bbaa0_0 .net "S0", 0 0, L_0x17f61a0; 1 drivers -v0x17bbb60_0 .net "S1", 0 0, L_0x17f6db0; 1 drivers -v0x17bbc00_0 .net "in0", 0 0, L_0x17f6c40; 1 drivers -v0x17bbca0_0 .net "in1", 0 0, L_0x17f6ce0; 1 drivers -v0x17bbd20_0 .net "in2", 0 0, L_0x17f7070; 1 drivers -v0x17bbdc0_0 .net "in3", 0 0, L_0x17f7160; 1 drivers -v0x17bbea0_0 .net "nS0", 0 0, L_0x17e8680; 1 drivers -v0x17bbf40_0 .net "nS1", 0 0, L_0x17f6430; 1 drivers -v0x17bbfe0_0 .net "out", 0 0, L_0x17f6990; 1 drivers -v0x17bc080_0 .net "out0", 0 0, L_0x17f64d0; 1 drivers -v0x17bc120_0 .net "out1", 0 0, L_0x17f6610; 1 drivers -v0x17bc1c0_0 .net "out2", 0 0, L_0x17f6700; 1 drivers -v0x17bc2d0_0 .net "out3", 0 0, L_0x17f6820; 1 drivers -S_0x17bb450 .scope module, "TwoMux" "TwoInMux" 2 299, 2 8, S_0x17bb2e0; - .timescale -9 -12; -L_0x17f10c0/d .functor NOT 1, L_0x17f78c0, C4<0>, C4<0>, C4<0>; -L_0x17f10c0 .delay (10000,10000,10000) L_0x17f10c0/d; -L_0x17f6ee0/d .functor AND 1, L_0x17f7460, L_0x17f10c0, C4<1>, C4<1>; -L_0x17f6ee0 .delay (20000,20000,20000) L_0x17f6ee0/d; -L_0x17f6fd0/d .functor AND 1, L_0x17f7500, L_0x17f78c0, C4<1>, C4<1>; -L_0x17f6fd0 .delay (20000,20000,20000) L_0x17f6fd0/d; -L_0x17f7650/d .functor OR 1, L_0x17f6ee0, L_0x17f6fd0, C4<0>, C4<0>; -L_0x17f7650 .delay (20000,20000,20000) L_0x17f7650/d; -v0x17bb540_0 .net "S", 0 0, L_0x17f78c0; 1 drivers -v0x17bb5c0_0 .net "in0", 0 0, L_0x17f7460; 1 drivers -v0x17bb640_0 .net "in1", 0 0, L_0x17f7500; 1 drivers -v0x17bb6e0_0 .net "nS", 0 0, L_0x17f10c0; 1 drivers -v0x17bb790_0 .net "out0", 0 0, L_0x17f6ee0; 1 drivers -v0x17bb830_0 .net "out1", 0 0, L_0x17f6fd0; 1 drivers -v0x17bb910_0 .net "outfinal", 0 0, L_0x17f7650; 1 drivers - .scope S_0x1782ed0; +S_0x1615180 .scope module, "test32Adder" "test32Adder" 2 135; + .timescale -9 -12; +P_0x158cdd8 .param/l "size" 2 137, +C4<0100>; +v0x1675610_0 .var "A", 3 0; +RS_0x7f44879d4218/0/0 .resolv tri, L_0x1676e00, L_0x16784b0, L_0x16799f0, L_0x167aff0; +RS_0x7f44879d4218/0/4 .resolv tri, L_0x168c310, L_0x168d730, L_0x168eb30, L_0x16900b0; +RS_0x7f44879d4218 .resolv tri, RS_0x7f44879d4218/0/0, RS_0x7f44879d4218/0/4, C4, C4; +v0x1675690_0 .net8 "AddSubSLTSum", 3 0, RS_0x7f44879d4218; 8 drivers +RS_0x7f44879d3468/0/0 .resolv tri, L_0x167cfa0, L_0x167da50, L_0x167e4c0, L_0x167ef20; +RS_0x7f44879d3468/0/4 .resolv tri, L_0x1691ee0, L_0x1692950, L_0x16933c0, L_0x1693f20; +RS_0x7f44879d3468 .resolv tri, RS_0x7f44879d3468/0/0, RS_0x7f44879d3468/0/4, C4, C4; +v0x1675710_0 .net8 "AndNandOut", 3 0, RS_0x7f44879d3468; 8 drivers +v0x1675790_0 .var "B", 3 0; +v0x1675810_0 .var "Command", 2 0; +RS_0x7f44879d1998 .resolv tri, L_0x1686050, L_0x16888b0, L_0x168b0c0, L_0x169ad10; +v0x1675890_0 .net8 "OneBitFinalOut", 3 0, RS_0x7f44879d1998; 4 drivers +RS_0x7f44879d2d78/0/0 .resolv tri, L_0x1680270, L_0x16817d0, L_0x1682ad0, L_0x1683dc0; +RS_0x7f44879d2d78/0/4 .resolv tri, L_0x1695270, L_0x1696570, L_0x1697870, L_0x1698b60; +RS_0x7f44879d2d78 .resolv tri, RS_0x7f44879d2d78/0/0, RS_0x7f44879d2d78/0/4, C4, C4; +v0x1675910_0 .net8 "OrNorXorOut", 3 0, RS_0x7f44879d2d78; 8 drivers +RS_0x7f44879d42d8 .resolv tri, L_0x167c620, L_0x1691580, C4, C4; +v0x1675990_0 .net8 "SLTflag", 0 0, RS_0x7f44879d42d8; 2 drivers +RS_0x7f44879d19c8 .resolv tri, L_0x169b8e0, L_0x169c330, L_0x169cde0, L_0x169d950; +v0x1675a10_0 .net8 "ZeroFlag", 3 0, RS_0x7f44879d19c8; 4 drivers +v0x1675ae0_0 .var "carryin", 3 0; +RS_0x7f44879d4518 .resolv tri, L_0x16770c0, L_0x1690430, C4, C4; +v0x1675b60_0 .net8 "carryout", 0 0, RS_0x7f44879d4518; 2 drivers +RS_0x7f44879d45a8 .resolv tri, L_0x167b8f0, L_0x16908a0, C4, C4; +v0x1675be0_0 .net8 "overflow", 0 0, RS_0x7f44879d45a8; 2 drivers +RS_0x7f44879d45d8/0/0 .resolv tri, L_0x1677020, L_0x16786e0, L_0x1679c50, L_0x167a040; +RS_0x7f44879d45d8/0/4 .resolv tri, L_0x168c4f0, L_0x168d960, L_0x168ed90, L_0x168f180; +RS_0x7f44879d45d8 .resolv tri, RS_0x7f44879d45d8/0/0, RS_0x7f44879d45d8/0/4, C4, C4; +v0x1675c60_0 .net8 "subtract", 3 0, RS_0x7f44879d45d8; 8 drivers +S_0x166fea0 .scope module, "trial" "AddSubSLT32" 2 156, 3 205, S_0x1615180; + .timescale -9 -12; +P_0x166ff98 .param/l "size" 3 228, +C4<0100>; +L_0x16770c0/d .functor OR 1, L_0x167b740, C4<0>, C4<0>, C4<0>; +L_0x16770c0 .delay (20000,20000,20000) L_0x16770c0/d; +L_0x167b8f0/d .functor XOR 1, RS_0x7f44879d4518, L_0x167ba20, C4<0>, C4<0>; +L_0x167b8f0 .delay (40000,40000,40000) L_0x167b8f0/d; +L_0x167b670/d .functor AND 1, L_0x167bbf0, L_0x167bc90, C4<1>, C4<1>; +L_0x167b670 .delay (20000,20000,20000) L_0x167b670/d; +L_0x167bac0/d .functor NOT 1, RS_0x7f44879d45a8, C4<0>, C4<0>, C4<0>; +L_0x167bac0 .delay (10000,10000,10000) L_0x167bac0/d; +L_0x167bec0/d .functor NOT 1, L_0x167bf20, C4<0>, C4<0>, C4<0>; +L_0x167bec0 .delay (10000,10000,10000) L_0x167bec0/d; +L_0x1676ea0/d .functor AND 1, L_0x167bac0, L_0x167c1f0, C4<1>, C4<1>; +L_0x1676ea0 .delay (20000,20000,20000) L_0x1676ea0/d; +L_0x167bd80/d .functor AND 1, RS_0x7f44879d45a8, L_0x167bec0, C4<1>, C4<1>; +L_0x167bd80 .delay (20000,20000,20000) L_0x167bd80/d; +L_0x167c3e0/d .functor AND 1, L_0x1676ea0, L_0x167b670, C4<1>, C4<1>; +L_0x167c3e0 .delay (20000,20000,20000) L_0x167c3e0/d; +L_0x167c520/d .functor AND 1, L_0x167bd80, L_0x167b670, C4<1>, C4<1>; +L_0x167c520 .delay (20000,20000,20000) L_0x167c520/d; +L_0x167c620/d .functor OR 1, L_0x167c3e0, L_0x167c520, C4<0>, C4<0>; +L_0x167c620 .delay (20000,20000,20000) L_0x167c620/d; +v0x1674530_0 .net "A", 3 0, v0x1675610_0; 1 drivers +v0x16745d0_0 .alias "AddSubSLTSum", 3 0, v0x1675690_0; +v0x1674650_0 .net "B", 3 0, v0x1675790_0; 1 drivers +RS_0x7f44879d6768 .resolv tri, L_0x1676f30, L_0x16785a0, L_0x1679ae0, L_0x167b0e0; +v0x16746d0_0 .net8 "CarryoutWire", 3 0, RS_0x7f44879d6768; 4 drivers +v0x1674750_0 .net "Command", 2 0, v0x1675810_0; 1 drivers +v0x16747d0_0 .net "Res0OF1", 0 0, L_0x167bd80; 1 drivers +v0x1674870_0 .net "Res1OF0", 0 0, L_0x1676ea0; 1 drivers +v0x1674910_0 .alias "SLTflag", 0 0, v0x1675990_0; +v0x1674a30_0 .net "SLTflag0", 0 0, L_0x167c3e0; 1 drivers +v0x1674ad0_0 .net "SLTflag1", 0 0, L_0x167c520; 1 drivers +v0x1674b70_0 .net "SLTon", 0 0, L_0x167b670; 1 drivers +v0x1674c10_0 .net *"_s40", 0 0, L_0x167b740; 1 drivers +v0x1674cb0_0 .net/s *"_s41", 0 0, C4<0>; 1 drivers +v0x1674d50_0 .net *"_s44", 0 0, L_0x167ba20; 1 drivers +v0x1674e70_0 .net *"_s46", 0 0, L_0x167bbf0; 1 drivers +v0x1674f10_0 .net *"_s48", 0 0, L_0x167bc90; 1 drivers +v0x1674dd0_0 .net *"_s50", 0 0, L_0x167bf20; 1 drivers +v0x1675060_0 .net *"_s52", 0 0, L_0x167c1f0; 1 drivers +v0x1675180_0 .net "carryin", 3 0, v0x1675ae0_0; 1 drivers +v0x1675200_0 .alias "carryout", 0 0, v0x1675b60_0; +v0x16750e0_0 .net "nAddSubSLTSum", 0 0, L_0x167bec0; 1 drivers +v0x1675330_0 .net "nOF", 0 0, L_0x167bac0; 1 drivers +v0x1675280_0 .alias "overflow", 0 0, v0x1675be0_0; +v0x16754c0_0 .alias "subtract", 3 0, v0x1675c60_0; +L_0x1676e00 .part/pv L_0x1676970, 1, 1, 4; +L_0x1676f30 .part/pv L_0x1676cc0, 1, 1, 4; +L_0x1677020 .part/pv L_0x1668ef0, 1, 1, 4; +L_0x1677150 .part v0x1675610_0, 1, 1; +L_0x1677300 .part v0x1675790_0, 1, 1; +L_0x16774b0 .part RS_0x7f44879d6768, 0, 1; +L_0x16784b0 .part/pv L_0x1677fe0, 2, 1, 4; +L_0x16785a0 .part/pv L_0x1678350, 2, 1, 4; +L_0x16786e0 .part/pv L_0x1677d10, 2, 1, 4; +L_0x16787d0 .part v0x1675610_0, 2, 1; +L_0x16788d0 .part v0x1675790_0, 2, 1; +L_0x1678a00 .part RS_0x7f44879d6768, 1, 1; +L_0x16799f0 .part/pv L_0x1679540, 3, 1, 4; +L_0x1679ae0 .part/pv L_0x1679890, 3, 1, 4; +L_0x1679c50 .part/pv L_0x1679270, 3, 1, 4; +L_0x1679d40 .part v0x1675610_0, 3, 1; +L_0x1679e70 .part v0x1675790_0, 3, 1; +L_0x1679fa0 .part RS_0x7f44879d6768, 2, 1; +L_0x167aff0 .part/pv L_0x167ab40, 0, 1, 4; +L_0x167b0e0 .part/pv L_0x167ae90, 0, 1, 4; +L_0x167a040 .part/pv L_0x167a870, 0, 1, 4; +L_0x167b2d0 .part v0x1675610_0, 0, 1; +L_0x167b1d0 .part v0x1675790_0, 0, 1; +L_0x167b4c0 .part RS_0x7f44879d45d8, 0, 1; +L_0x167b740 .part RS_0x7f44879d6768, 3, 1; +L_0x167ba20 .part RS_0x7f44879d6768, 2, 1; +L_0x167bbf0 .part v0x1675810_0, 1, 1; +L_0x167bc90 .part RS_0x7f44879d45d8, 0, 1; +L_0x167bf20 .part RS_0x7f44879d4218, 3, 1; +L_0x167c1f0 .part RS_0x7f44879d4218, 3, 1; +S_0x1673520 .scope module, "attempt2" "MiddleAddSubSLT" 3 225, 3 89, S_0x166fea0; + .timescale -9 -12; +L_0x1679de0/d .functor NOT 1, L_0x167b1d0, C4<0>, C4<0>, C4<0>; +L_0x1679de0 .delay (10000,10000,10000) L_0x1679de0/d; +L_0x167a710/d .functor NOT 1, L_0x167a7d0, C4<0>, C4<0>, C4<0>; +L_0x167a710 .delay (10000,10000,10000) L_0x167a710/d; +L_0x167a870/d .functor AND 1, L_0x167a9b0, L_0x167a710, C4<1>, C4<1>; +L_0x167a870 .delay (20000,20000,20000) L_0x167a870/d; +L_0x167aa50/d .functor XOR 1, L_0x167b2d0, L_0x167a4a0, C4<0>, C4<0>; +L_0x167aa50 .delay (40000,40000,40000) L_0x167aa50/d; +L_0x167ab40/d .functor XOR 1, L_0x167aa50, L_0x167b4c0, C4<0>, C4<0>; +L_0x167ab40 .delay (40000,40000,40000) L_0x167ab40/d; +L_0x167ac30/d .functor AND 1, L_0x167b2d0, L_0x167a4a0, C4<1>, C4<1>; +L_0x167ac30 .delay (20000,20000,20000) L_0x167ac30/d; +L_0x167ada0/d .functor AND 1, L_0x167aa50, L_0x167b4c0, C4<1>, C4<1>; +L_0x167ada0 .delay (20000,20000,20000) L_0x167ada0/d; +L_0x167ae90/d .functor OR 1, L_0x167ac30, L_0x167ada0, C4<0>, C4<0>; +L_0x167ae90 .delay (20000,20000,20000) L_0x167ae90/d; +v0x1673b90_0 .net "A", 0 0, L_0x167b2d0; 1 drivers +v0x1673c50_0 .net "AandB", 0 0, L_0x167ac30; 1 drivers +v0x1673cf0_0 .net "AddSubSLTSum", 0 0, L_0x167ab40; 1 drivers +v0x1673d90_0 .net "AxorB", 0 0, L_0x167aa50; 1 drivers +v0x1673e10_0 .net "B", 0 0, L_0x167b1d0; 1 drivers +v0x1673ec0_0 .net "BornB", 0 0, L_0x167a4a0; 1 drivers +v0x1673f80_0 .net "CINandAxorB", 0 0, L_0x167ada0; 1 drivers +v0x1674000_0 .alias "Command", 2 0, v0x1674750_0; +v0x1674080_0 .net *"_s3", 0 0, L_0x167a7d0; 1 drivers +v0x1674100_0 .net *"_s5", 0 0, L_0x167a9b0; 1 drivers +v0x16741a0_0 .net "carryin", 0 0, L_0x167b4c0; 1 drivers +v0x1674240_0 .net "carryout", 0 0, L_0x167ae90; 1 drivers +v0x16742e0_0 .net "nB", 0 0, L_0x1679de0; 1 drivers +v0x1674390_0 .net "nCmd2", 0 0, L_0x167a710; 1 drivers +v0x1674490_0 .net "subtract", 0 0, L_0x167a870; 1 drivers +L_0x167a670 .part v0x1675810_0, 0, 1; +L_0x167a7d0 .part v0x1675810_0, 2, 1; +L_0x167a9b0 .part v0x1675810_0, 0, 1; +S_0x1673610 .scope module, "mux0" "TwoInMux" 3 105, 3 8, S_0x1673520; + .timescale -9 -12; +L_0x167a1c0/d .functor NOT 1, L_0x167a670, C4<0>, C4<0>, C4<0>; +L_0x167a1c0 .delay (10000,10000,10000) L_0x167a1c0/d; +L_0x167a280/d .functor AND 1, L_0x167b1d0, L_0x167a1c0, C4<1>, C4<1>; +L_0x167a280 .delay (20000,20000,20000) L_0x167a280/d; +L_0x167a390/d .functor AND 1, L_0x1679de0, L_0x167a670, C4<1>, C4<1>; +L_0x167a390 .delay (20000,20000,20000) L_0x167a390/d; +L_0x167a4a0/d .functor OR 1, L_0x167a280, L_0x167a390, C4<0>, C4<0>; +L_0x167a4a0 .delay (20000,20000,20000) L_0x167a4a0/d; +v0x1673700_0 .net "S", 0 0, L_0x167a670; 1 drivers +v0x16737c0_0 .alias "in0", 0 0, v0x1673e10_0; +v0x1673860_0 .alias "in1", 0 0, v0x16742e0_0; +v0x1673900_0 .net "nS", 0 0, L_0x167a1c0; 1 drivers +v0x16739b0_0 .net "out0", 0 0, L_0x167a280; 1 drivers +v0x1673a50_0 .net "out1", 0 0, L_0x167a390; 1 drivers +v0x1673af0_0 .alias "outfinal", 0 0, v0x1673ec0_0; +S_0x1672380 .scope generate, "addbits[1]" "addbits[1]" 3 230, 3 230, S_0x166fea0; + .timescale -9 -12; +P_0x1671d98 .param/l "i" 3 230, +C4<01>; +S_0x16724f0 .scope module, "attempt" "MiddleAddSubSLT" 3 232, 3 89, S_0x1672380; + .timescale -9 -12; +L_0x1670dd0/d .functor NOT 1, L_0x1677300, C4<0>, C4<0>, C4<0>; +L_0x1670dd0 .delay (10000,10000,10000) L_0x1670dd0/d; +L_0x1662ba0/d .functor NOT 1, L_0x1668e50, C4<0>, C4<0>, C4<0>; +L_0x1662ba0 .delay (10000,10000,10000) L_0x1662ba0/d; +L_0x1668ef0/d .functor AND 1, L_0x16767e0, L_0x1662ba0, C4<1>, C4<1>; +L_0x1668ef0 .delay (20000,20000,20000) L_0x1668ef0/d; +L_0x1676880/d .functor XOR 1, L_0x1677150, L_0x1676110, C4<0>, C4<0>; +L_0x1676880 .delay (40000,40000,40000) L_0x1676880/d; +L_0x1676970/d .functor XOR 1, L_0x1676880, L_0x16774b0, C4<0>, C4<0>; +L_0x1676970 .delay (40000,40000,40000) L_0x1676970/d; +L_0x1676a60/d .functor AND 1, L_0x1677150, L_0x1676110, C4<1>, C4<1>; +L_0x1676a60 .delay (20000,20000,20000) L_0x1676a60/d; +L_0x1676bd0/d .functor AND 1, L_0x1676880, L_0x16774b0, C4<1>, C4<1>; +L_0x1676bd0 .delay (20000,20000,20000) L_0x1676bd0/d; +L_0x1676cc0/d .functor OR 1, L_0x1676a60, L_0x1676bd0, C4<0>, C4<0>; +L_0x1676cc0 .delay (20000,20000,20000) L_0x1676cc0/d; +v0x1672b80_0 .net "A", 0 0, L_0x1677150; 1 drivers +v0x1672c40_0 .net "AandB", 0 0, L_0x1676a60; 1 drivers +v0x1672ce0_0 .net "AddSubSLTSum", 0 0, L_0x1676970; 1 drivers +v0x1672d80_0 .net "AxorB", 0 0, L_0x1676880; 1 drivers +v0x1672e00_0 .net "B", 0 0, L_0x1677300; 1 drivers +v0x1672eb0_0 .net "BornB", 0 0, L_0x1676110; 1 drivers +v0x1672f70_0 .net "CINandAxorB", 0 0, L_0x1676bd0; 1 drivers +v0x1672ff0_0 .alias "Command", 2 0, v0x1674750_0; +v0x1673070_0 .net *"_s3", 0 0, L_0x1668e50; 1 drivers +v0x16730f0_0 .net *"_s5", 0 0, L_0x16767e0; 1 drivers +v0x1673190_0 .net "carryin", 0 0, L_0x16774b0; 1 drivers +v0x1673230_0 .net "carryout", 0 0, L_0x1676cc0; 1 drivers +v0x16732d0_0 .net "nB", 0 0, L_0x1670dd0; 1 drivers +v0x1673380_0 .net "nCmd2", 0 0, L_0x1662ba0; 1 drivers +v0x1673480_0 .net "subtract", 0 0, L_0x1668ef0; 1 drivers +L_0x16762e0 .part v0x1675810_0, 0, 1; +L_0x1668e50 .part v0x1675810_0, 2, 1; +L_0x16767e0 .part v0x1675810_0, 0, 1; +S_0x16725e0 .scope module, "mux0" "TwoInMux" 3 105, 3 8, S_0x16724f0; + .timescale -9 -12; +L_0x1675e30/d .functor NOT 1, L_0x16762e0, C4<0>, C4<0>, C4<0>; +L_0x1675e30 .delay (10000,10000,10000) L_0x1675e30/d; +L_0x1675ef0/d .functor AND 1, L_0x1677300, L_0x1675e30, C4<1>, C4<1>; +L_0x1675ef0 .delay (20000,20000,20000) L_0x1675ef0/d; +L_0x1676000/d .functor AND 1, L_0x1670dd0, L_0x16762e0, C4<1>, C4<1>; +L_0x1676000 .delay (20000,20000,20000) L_0x1676000/d; +L_0x1676110/d .functor OR 1, L_0x1675ef0, L_0x1676000, C4<0>, C4<0>; +L_0x1676110 .delay (20000,20000,20000) L_0x1676110/d; +v0x16726d0_0 .net "S", 0 0, L_0x16762e0; 1 drivers +v0x1672770_0 .alias "in0", 0 0, v0x1672e00_0; +v0x1672810_0 .alias "in1", 0 0, v0x16732d0_0; +v0x16728b0_0 .net "nS", 0 0, L_0x1675e30; 1 drivers +v0x1672960_0 .net "out0", 0 0, L_0x1675ef0; 1 drivers +v0x1672a00_0 .net "out1", 0 0, L_0x1676000; 1 drivers +v0x1672ae0_0 .alias "outfinal", 0 0, v0x1672eb0_0; +S_0x16711e0 .scope generate, "addbits[2]" "addbits[2]" 3 230, 3 230, S_0x166fea0; + .timescale -9 -12; +P_0x1670b98 .param/l "i" 3 230, +C4<010>; +S_0x1671350 .scope module, "attempt" "MiddleAddSubSLT" 3 232, 3 89, S_0x16711e0; + .timescale -9 -12; +L_0x166cc50/d .functor NOT 1, L_0x16788d0, C4<0>, C4<0>, C4<0>; +L_0x166cc50 .delay (10000,10000,10000) L_0x166cc50/d; +L_0x1677bb0/d .functor NOT 1, L_0x1677c70, C4<0>, C4<0>, C4<0>; +L_0x1677bb0 .delay (10000,10000,10000) L_0x1677bb0/d; +L_0x1677d10/d .functor AND 1, L_0x1677e50, L_0x1677bb0, C4<1>, C4<1>; +L_0x1677d10 .delay (20000,20000,20000) L_0x1677d10/d; +L_0x1677ef0/d .functor XOR 1, L_0x16787d0, L_0x1677940, C4<0>, C4<0>; +L_0x1677ef0 .delay (40000,40000,40000) L_0x1677ef0/d; +L_0x1677fe0/d .functor XOR 1, L_0x1677ef0, L_0x1678a00, C4<0>, C4<0>; +L_0x1677fe0 .delay (40000,40000,40000) L_0x1677fe0/d; +L_0x16780d0/d .functor AND 1, L_0x16787d0, L_0x1677940, C4<1>, C4<1>; +L_0x16780d0 .delay (20000,20000,20000) L_0x16780d0/d; +L_0x1678240/d .functor AND 1, L_0x1677ef0, L_0x1678a00, C4<1>, C4<1>; +L_0x1678240 .delay (20000,20000,20000) L_0x1678240/d; +L_0x1678350/d .functor OR 1, L_0x16780d0, L_0x1678240, C4<0>, C4<0>; +L_0x1678350 .delay (20000,20000,20000) L_0x1678350/d; +v0x16719e0_0 .net "A", 0 0, L_0x16787d0; 1 drivers +v0x1671aa0_0 .net "AandB", 0 0, L_0x16780d0; 1 drivers +v0x1671b40_0 .net "AddSubSLTSum", 0 0, L_0x1677fe0; 1 drivers +v0x1671be0_0 .net "AxorB", 0 0, L_0x1677ef0; 1 drivers +v0x1671c60_0 .net "B", 0 0, L_0x16788d0; 1 drivers +v0x1671d10_0 .net "BornB", 0 0, L_0x1677940; 1 drivers +v0x1671dd0_0 .net "CINandAxorB", 0 0, L_0x1678240; 1 drivers +v0x1671e50_0 .alias "Command", 2 0, v0x1674750_0; +v0x1671ed0_0 .net *"_s3", 0 0, L_0x1677c70; 1 drivers +v0x1671f50_0 .net *"_s5", 0 0, L_0x1677e50; 1 drivers +v0x1671ff0_0 .net "carryin", 0 0, L_0x1678a00; 1 drivers +v0x1672090_0 .net "carryout", 0 0, L_0x1678350; 1 drivers +v0x1672130_0 .net "nB", 0 0, L_0x166cc50; 1 drivers +v0x16721e0_0 .net "nCmd2", 0 0, L_0x1677bb0; 1 drivers +v0x16722e0_0 .net "subtract", 0 0, L_0x1677d10; 1 drivers +L_0x1677b10 .part v0x1675810_0, 0, 1; +L_0x1677c70 .part v0x1675810_0, 2, 1; +L_0x1677e50 .part v0x1675810_0, 0, 1; +S_0x1671440 .scope module, "mux0" "TwoInMux" 3 105, 3 8, S_0x1671350; + .timescale -9 -12; +L_0x1677680/d .functor NOT 1, L_0x1677b10, C4<0>, C4<0>, C4<0>; +L_0x1677680 .delay (10000,10000,10000) L_0x1677680/d; +L_0x1677720/d .functor AND 1, L_0x16788d0, L_0x1677680, C4<1>, C4<1>; +L_0x1677720 .delay (20000,20000,20000) L_0x1677720/d; +L_0x1677830/d .functor AND 1, L_0x166cc50, L_0x1677b10, C4<1>, C4<1>; +L_0x1677830 .delay (20000,20000,20000) L_0x1677830/d; +L_0x1677940/d .functor OR 1, L_0x1677720, L_0x1677830, C4<0>, C4<0>; +L_0x1677940 .delay (20000,20000,20000) L_0x1677940/d; +v0x1671530_0 .net "S", 0 0, L_0x1677b10; 1 drivers +v0x16715d0_0 .alias "in0", 0 0, v0x1671c60_0; +v0x1671670_0 .alias "in1", 0 0, v0x1672130_0; +v0x1671710_0 .net "nS", 0 0, L_0x1677680; 1 drivers +v0x16717c0_0 .net "out0", 0 0, L_0x1677720; 1 drivers +v0x1671860_0 .net "out1", 0 0, L_0x1677830; 1 drivers +v0x1671940_0 .alias "outfinal", 0 0, v0x1671d10_0; +S_0x1670010 .scope generate, "addbits[3]" "addbits[3]" 3 230, 3 230, S_0x166fea0; + .timescale -9 -12; +P_0x1670108 .param/l "i" 3 230, +C4<011>; +S_0x1670180 .scope module, "attempt" "MiddleAddSubSLT" 3 232, 3 89, S_0x1670010; + .timescale -9 -12; +L_0x1678870/d .functor NOT 1, L_0x1679e70, C4<0>, C4<0>, C4<0>; +L_0x1678870 .delay (10000,10000,10000) L_0x1678870/d; +L_0x1679110/d .functor NOT 1, L_0x16791d0, C4<0>, C4<0>, C4<0>; +L_0x1679110 .delay (10000,10000,10000) L_0x1679110/d; +L_0x1679270/d .functor AND 1, L_0x16793b0, L_0x1679110, C4<1>, C4<1>; +L_0x1679270 .delay (20000,20000,20000) L_0x1679270/d; +L_0x1679450/d .functor XOR 1, L_0x1679d40, L_0x1678ea0, C4<0>, C4<0>; +L_0x1679450 .delay (40000,40000,40000) L_0x1679450/d; +L_0x1679540/d .functor XOR 1, L_0x1679450, L_0x1679fa0, C4<0>, C4<0>; +L_0x1679540 .delay (40000,40000,40000) L_0x1679540/d; +L_0x1679630/d .functor AND 1, L_0x1679d40, L_0x1678ea0, C4<1>, C4<1>; +L_0x1679630 .delay (20000,20000,20000) L_0x1679630/d; +L_0x16797a0/d .functor AND 1, L_0x1679450, L_0x1679fa0, C4<1>, C4<1>; +L_0x16797a0 .delay (20000,20000,20000) L_0x16797a0/d; +L_0x1679890/d .functor OR 1, L_0x1679630, L_0x16797a0, C4<0>, C4<0>; +L_0x1679890 .delay (20000,20000,20000) L_0x1679890/d; +v0x16707e0_0 .net "A", 0 0, L_0x1679d40; 1 drivers +v0x16708a0_0 .net "AandB", 0 0, L_0x1679630; 1 drivers +v0x1670940_0 .net "AddSubSLTSum", 0 0, L_0x1679540; 1 drivers +v0x16709e0_0 .net "AxorB", 0 0, L_0x1679450; 1 drivers +v0x1670a60_0 .net "B", 0 0, L_0x1679e70; 1 drivers +v0x1670b10_0 .net "BornB", 0 0, L_0x1678ea0; 1 drivers +v0x1670bd0_0 .net "CINandAxorB", 0 0, L_0x16797a0; 1 drivers +v0x1670c50_0 .alias "Command", 2 0, v0x1674750_0; +v0x1670cd0_0 .net *"_s3", 0 0, L_0x16791d0; 1 drivers +v0x1670d50_0 .net *"_s5", 0 0, L_0x16793b0; 1 drivers +v0x1670e50_0 .net "carryin", 0 0, L_0x1679fa0; 1 drivers +v0x1670ef0_0 .net "carryout", 0 0, L_0x1679890; 1 drivers +v0x1670f90_0 .net "nB", 0 0, L_0x1678870; 1 drivers +v0x1671040_0 .net "nCmd2", 0 0, L_0x1679110; 1 drivers +v0x1671140_0 .net "subtract", 0 0, L_0x1679270; 1 drivers +L_0x1679070 .part v0x1675810_0, 0, 1; +L_0x16791d0 .part v0x1675810_0, 2, 1; +L_0x16793b0 .part v0x1675810_0, 0, 1; +S_0x1670270 .scope module, "mux0" "TwoInMux" 3 105, 3 8, S_0x1670180; + .timescale -9 -12; +L_0x1678c00/d .functor NOT 1, L_0x1679070, C4<0>, C4<0>, C4<0>; +L_0x1678c00 .delay (10000,10000,10000) L_0x1678c00/d; +L_0x1678c80/d .functor AND 1, L_0x1679e70, L_0x1678c00, C4<1>, C4<1>; +L_0x1678c80 .delay (20000,20000,20000) L_0x1678c80/d; +L_0x1678d90/d .functor AND 1, L_0x1678870, L_0x1679070, C4<1>, C4<1>; +L_0x1678d90 .delay (20000,20000,20000) L_0x1678d90/d; +L_0x1678ea0/d .functor OR 1, L_0x1678c80, L_0x1678d90, C4<0>, C4<0>; +L_0x1678ea0 .delay (20000,20000,20000) L_0x1678ea0/d; +v0x1670360_0 .net "S", 0 0, L_0x1679070; 1 drivers +v0x1670400_0 .alias "in0", 0 0, v0x1670a60_0; +v0x16704a0_0 .alias "in1", 0 0, v0x1670f90_0; +v0x1670540_0 .net "nS", 0 0, L_0x1678c00; 1 drivers +v0x16705c0_0 .net "out0", 0 0, L_0x1678c80; 1 drivers +v0x1670660_0 .net "out1", 0 0, L_0x1678d90; 1 drivers +v0x1670740_0 .alias "outfinal", 0 0, v0x1670b10_0; +S_0x166cde0 .scope module, "trial1" "AndNand32" 2 158, 3 154, S_0x1615180; + .timescale -9 -12; +P_0x166c7d8 .param/l "size" 3 161, +C4<0100>; +v0x166fca0_0 .alias "A", 3 0, v0x1674530_0; +v0x166fd20_0 .alias "AndNandOut", 3 0, v0x1675710_0; +v0x166fda0_0 .alias "B", 3 0, v0x1674650_0; +v0x166fe20_0 .alias "Command", 2 0, v0x1674750_0; +L_0x167cfa0 .part/pv L_0x167cd30, 1, 1, 4; +L_0x167d0f0 .part v0x1675610_0, 1, 1; +L_0x167d190 .part v0x1675790_0, 1, 1; +L_0x167da50 .part/pv L_0x167d7e0, 2, 1, 4; +L_0x167daf0 .part v0x1675610_0, 2, 1; +L_0x167db90 .part v0x1675790_0, 2, 1; +L_0x167e4c0 .part/pv L_0x167e250, 3, 1, 4; +L_0x167e560 .part v0x1675610_0, 3, 1; +L_0x167e650 .part v0x1675790_0, 3, 1; +L_0x167ef20 .part/pv L_0x167ecb0, 0, 1, 4; +L_0x167f020 .part v0x1675610_0, 0, 1; +L_0x167f0c0 .part v0x1675790_0, 0, 1; +S_0x166f270 .scope module, "attempt2" "AndNand" 3 165, 3 48, S_0x166cde0; + .timescale -9 -12; +L_0x167e740/d .functor NAND 1, L_0x167f020, L_0x167f0c0, C4<1>, C4<1>; +L_0x167e740 .delay (10000,10000,10000) L_0x167e740/d; +L_0x167e860/d .functor NOT 1, L_0x167e740, C4<0>, C4<0>, C4<0>; +L_0x167e860 .delay (10000,10000,10000) L_0x167e860/d; +v0x166f890_0 .net "A", 0 0, L_0x167f020; 1 drivers +v0x166f950_0 .net "AandB", 0 0, L_0x167e860; 1 drivers +v0x166f9d0_0 .net "AnandB", 0 0, L_0x167e740; 1 drivers +v0x166fa80_0 .net "AndNandOut", 0 0, L_0x167ecb0; 1 drivers +v0x166fb60_0 .net "B", 0 0, L_0x167f0c0; 1 drivers +v0x166fbe0_0 .alias "Command", 2 0, v0x1674750_0; +L_0x167ee80 .part v0x1675810_0, 0, 1; +S_0x166f360 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0x166f270; + .timescale -9 -12; +L_0x167e990/d .functor NOT 1, L_0x167ee80, C4<0>, C4<0>, C4<0>; +L_0x167e990 .delay (10000,10000,10000) L_0x167e990/d; +L_0x167ea50/d .functor AND 1, L_0x167e860, L_0x167e990, C4<1>, C4<1>; +L_0x167ea50 .delay (20000,20000,20000) L_0x167ea50/d; +L_0x167eb60/d .functor AND 1, L_0x167e740, L_0x167ee80, C4<1>, C4<1>; +L_0x167eb60 .delay (20000,20000,20000) L_0x167eb60/d; +L_0x167ecb0/d .functor OR 1, L_0x167ea50, L_0x167eb60, C4<0>, C4<0>; +L_0x167ecb0 .delay (20000,20000,20000) L_0x167ecb0/d; +v0x166f450_0 .net "S", 0 0, L_0x167ee80; 1 drivers +v0x166f4d0_0 .alias "in0", 0 0, v0x166f950_0; +v0x166f550_0 .alias "in1", 0 0, v0x166f9d0_0; +v0x166f5f0_0 .net "nS", 0 0, L_0x167e990; 1 drivers +v0x166f670_0 .net "out0", 0 0, L_0x167ea50; 1 drivers +v0x166f710_0 .net "out1", 0 0, L_0x167eb60; 1 drivers +v0x166f7f0_0 .alias "outfinal", 0 0, v0x166fa80_0; +S_0x166e6b0 .scope generate, "andbits[1]" "andbits[1]" 3 169, 3 169, S_0x166cde0; + .timescale -9 -12; +P_0x166e7a8 .param/l "i" 3 169, +C4<01>; +S_0x166e820 .scope module, "attempt" "AndNand" 3 171, 3 48, S_0x166e6b0; + .timescale -9 -12; +L_0x167c820/d .functor NAND 1, L_0x167d0f0, L_0x167d190, C4<1>, C4<1>; +L_0x167c820 .delay (10000,10000,10000) L_0x167c820/d; +L_0x167c8e0/d .functor NOT 1, L_0x167c820, C4<0>, C4<0>, C4<0>; +L_0x167c8e0 .delay (10000,10000,10000) L_0x167c8e0/d; +v0x166ee60_0 .net "A", 0 0, L_0x167d0f0; 1 drivers +v0x166ef20_0 .net "AandB", 0 0, L_0x167c8e0; 1 drivers +v0x166efa0_0 .net "AnandB", 0 0, L_0x167c820; 1 drivers +v0x166f050_0 .net "AndNandOut", 0 0, L_0x167cd30; 1 drivers +v0x166f130_0 .net "B", 0 0, L_0x167d190; 1 drivers +v0x166f1b0_0 .alias "Command", 2 0, v0x1674750_0; +L_0x167cf00 .part v0x1675810_0, 0, 1; +S_0x166e910 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0x166e820; + .timescale -9 -12; +L_0x167ca10/d .functor NOT 1, L_0x167cf00, C4<0>, C4<0>, C4<0>; +L_0x167ca10 .delay (10000,10000,10000) L_0x167ca10/d; +L_0x167cad0/d .functor AND 1, L_0x167c8e0, L_0x167ca10, C4<1>, C4<1>; +L_0x167cad0 .delay (20000,20000,20000) L_0x167cad0/d; +L_0x167cbe0/d .functor AND 1, L_0x167c820, L_0x167cf00, C4<1>, C4<1>; +L_0x167cbe0 .delay (20000,20000,20000) L_0x167cbe0/d; +L_0x167cd30/d .functor OR 1, L_0x167cad0, L_0x167cbe0, C4<0>, C4<0>; +L_0x167cd30 .delay (20000,20000,20000) L_0x167cd30/d; +v0x166ea00_0 .net "S", 0 0, L_0x167cf00; 1 drivers +v0x166ea80_0 .alias "in0", 0 0, v0x166ef20_0; +v0x166eb20_0 .alias "in1", 0 0, v0x166efa0_0; +v0x166ebc0_0 .net "nS", 0 0, L_0x167ca10; 1 drivers +v0x166ec40_0 .net "out0", 0 0, L_0x167cad0; 1 drivers +v0x166ece0_0 .net "out1", 0 0, L_0x167cbe0; 1 drivers +v0x166edc0_0 .alias "outfinal", 0 0, v0x166f050_0; +S_0x166daf0 .scope generate, "andbits[2]" "andbits[2]" 3 169, 3 169, S_0x166cde0; + .timescale -9 -12; +P_0x166dbe8 .param/l "i" 3 169, +C4<010>; +S_0x166dc60 .scope module, "attempt" "AndNand" 3 171, 3 48, S_0x166daf0; + .timescale -9 -12; +L_0x167d230/d .functor NAND 1, L_0x167daf0, L_0x167db90, C4<1>, C4<1>; +L_0x167d230 .delay (10000,10000,10000) L_0x167d230/d; +L_0x167d390/d .functor NOT 1, L_0x167d230, C4<0>, C4<0>, C4<0>; +L_0x167d390 .delay (10000,10000,10000) L_0x167d390/d; +v0x166e2a0_0 .net "A", 0 0, L_0x167daf0; 1 drivers +v0x166e360_0 .net "AandB", 0 0, L_0x167d390; 1 drivers +v0x166e3e0_0 .net "AnandB", 0 0, L_0x167d230; 1 drivers +v0x166e490_0 .net "AndNandOut", 0 0, L_0x167d7e0; 1 drivers +v0x166e570_0 .net "B", 0 0, L_0x167db90; 1 drivers +v0x166e5f0_0 .alias "Command", 2 0, v0x1674750_0; +L_0x167d9b0 .part v0x1675810_0, 0, 1; +S_0x166dd50 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0x166dc60; + .timescale -9 -12; +L_0x167d4c0/d .functor NOT 1, L_0x167d9b0, C4<0>, C4<0>, C4<0>; +L_0x167d4c0 .delay (10000,10000,10000) L_0x167d4c0/d; +L_0x167d580/d .functor AND 1, L_0x167d390, L_0x167d4c0, C4<1>, C4<1>; +L_0x167d580 .delay (20000,20000,20000) L_0x167d580/d; +L_0x167d690/d .functor AND 1, L_0x167d230, L_0x167d9b0, C4<1>, C4<1>; +L_0x167d690 .delay (20000,20000,20000) L_0x167d690/d; +L_0x167d7e0/d .functor OR 1, L_0x167d580, L_0x167d690, C4<0>, C4<0>; +L_0x167d7e0 .delay (20000,20000,20000) L_0x167d7e0/d; +v0x166de40_0 .net "S", 0 0, L_0x167d9b0; 1 drivers +v0x166dec0_0 .alias "in0", 0 0, v0x166e360_0; +v0x166df60_0 .alias "in1", 0 0, v0x166e3e0_0; +v0x166e000_0 .net "nS", 0 0, L_0x167d4c0; 1 drivers +v0x166e080_0 .net "out0", 0 0, L_0x167d580; 1 drivers +v0x166e120_0 .net "out1", 0 0, L_0x167d690; 1 drivers +v0x166e200_0 .alias "outfinal", 0 0, v0x166e490_0; +S_0x166cf10 .scope generate, "andbits[3]" "andbits[3]" 3 169, 3 169, S_0x166cde0; + .timescale -9 -12; +P_0x166d008 .param/l "i" 3 169, +C4<011>; +S_0x166d080 .scope module, "attempt" "AndNand" 3 171, 3 48, S_0x166cf10; + .timescale -9 -12; +L_0x167dcc0/d .functor NAND 1, L_0x167e560, L_0x167e650, C4<1>, C4<1>; +L_0x167dcc0 .delay (10000,10000,10000) L_0x167dcc0/d; +L_0x167de00/d .functor NOT 1, L_0x167dcc0, C4<0>, C4<0>, C4<0>; +L_0x167de00 .delay (10000,10000,10000) L_0x167de00/d; +v0x166d6e0_0 .net "A", 0 0, L_0x167e560; 1 drivers +v0x166d7a0_0 .net "AandB", 0 0, L_0x167de00; 1 drivers +v0x166d820_0 .net "AnandB", 0 0, L_0x167dcc0; 1 drivers +v0x166d8d0_0 .net "AndNandOut", 0 0, L_0x167e250; 1 drivers +v0x166d9b0_0 .net "B", 0 0, L_0x167e650; 1 drivers +v0x166da30_0 .alias "Command", 2 0, v0x1674750_0; +L_0x167e420 .part v0x1675810_0, 0, 1; +S_0x166d170 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0x166d080; + .timescale -9 -12; +L_0x167df30/d .functor NOT 1, L_0x167e420, C4<0>, C4<0>, C4<0>; +L_0x167df30 .delay (10000,10000,10000) L_0x167df30/d; +L_0x167dff0/d .functor AND 1, L_0x167de00, L_0x167df30, C4<1>, C4<1>; +L_0x167dff0 .delay (20000,20000,20000) L_0x167dff0/d; +L_0x167e100/d .functor AND 1, L_0x167dcc0, L_0x167e420, C4<1>, C4<1>; +L_0x167e100 .delay (20000,20000,20000) L_0x167e100/d; +L_0x167e250/d .functor OR 1, L_0x167dff0, L_0x167e100, C4<0>, C4<0>; +L_0x167e250 .delay (20000,20000,20000) L_0x167e250/d; +v0x166d260_0 .net "S", 0 0, L_0x167e420; 1 drivers +v0x166d300_0 .alias "in0", 0 0, v0x166d7a0_0; +v0x166d3a0_0 .alias "in1", 0 0, v0x166d820_0; +v0x166d440_0 .net "nS", 0 0, L_0x167df30; 1 drivers +v0x166d4c0_0 .net "out0", 0 0, L_0x167dff0; 1 drivers +v0x166d560_0 .net "out1", 0 0, L_0x167e100; 1 drivers +v0x166d640_0 .alias "outfinal", 0 0, v0x166d8d0_0; +S_0x1667b20 .scope module, "trial2" "OrNorXor32" 2 160, 3 177, S_0x1615180; + .timescale -9 -12; +P_0x16664d8 .param/l "size" 3 184, +C4<0100>; +v0x166cac0_0 .alias "A", 3 0, v0x1674530_0; +v0x166cbd0_0 .alias "B", 3 0, v0x1674650_0; +v0x166cce0_0 .alias "Command", 2 0, v0x1674750_0; +v0x166cd60_0 .alias "OrNorXorOut", 3 0, v0x1675910_0; +L_0x1680270 .part/pv L_0x1680000, 1, 1, 4; +L_0x16803a0 .part v0x1675610_0, 1, 1; +L_0x16771f0 .part v0x1675790_0, 1, 1; +L_0x16817d0 .part/pv L_0x1681560, 2, 1, 4; +L_0x1681870 .part v0x1675610_0, 2, 1; +L_0x1681910 .part v0x1675790_0, 2, 1; +L_0x1682ad0 .part/pv L_0x1682860, 3, 1, 4; +L_0x1682b70 .part v0x1675610_0, 3, 1; +L_0x1682c10 .part v0x1675790_0, 3, 1; +L_0x1683dc0 .part/pv L_0x1683b50, 0, 1, 4; +L_0x1683ec0 .part v0x1675610_0, 0, 1; +L_0x1683f60 .part v0x1675790_0, 0, 1; +S_0x166b880 .scope module, "attempt2" "OrNorXor" 3 192, 3 64, S_0x1667b20; + .timescale -9 -12; +L_0x1682cb0/d .functor NOR 1, L_0x1683ec0, L_0x1683f60, C4<0>, C4<0>; +L_0x1682cb0 .delay (10000,10000,10000) L_0x1682cb0/d; +L_0x1682db0/d .functor NOT 1, L_0x1682cb0, C4<0>, C4<0>, C4<0>; +L_0x1682db0 .delay (10000,10000,10000) L_0x1682db0/d; +L_0x1682ee0/d .functor NAND 1, L_0x1683ec0, L_0x1683f60, C4<1>, C4<1>; +L_0x1682ee0 .delay (10000,10000,10000) L_0x1682ee0/d; +L_0x1683040/d .functor NAND 1, L_0x1682ee0, L_0x1682db0, C4<1>, C4<1>; +L_0x1683040 .delay (10000,10000,10000) L_0x1683040/d; +L_0x1683150/d .functor NOT 1, L_0x1683040, C4<0>, C4<0>, C4<0>; +L_0x1683150 .delay (10000,10000,10000) L_0x1683150/d; +v0x166c3d0_0 .net "A", 0 0, L_0x1683ec0; 1 drivers +v0x166c470_0 .net "AnandB", 0 0, L_0x1682ee0; 1 drivers +v0x166c510_0 .net "AnorB", 0 0, L_0x1682cb0; 1 drivers +v0x166c5c0_0 .net "AorB", 0 0, L_0x1682db0; 1 drivers +v0x166c6a0_0 .net "AxorB", 0 0, L_0x1683150; 1 drivers +v0x166c750_0 .net "B", 0 0, L_0x1683f60; 1 drivers +v0x166c810_0 .alias "Command", 2 0, v0x1674750_0; +v0x166c890_0 .net "OrNorXorOut", 0 0, L_0x1683b50; 1 drivers +v0x166c910_0 .net "XorNor", 0 0, L_0x16835d0; 1 drivers +v0x166c9e0_0 .net "nXor", 0 0, L_0x1683040; 1 drivers +L_0x1683750 .part v0x1675810_0, 2, 1; +L_0x1683d20 .part v0x1675810_0, 0, 1; +S_0x166be60 .scope module, "mux0" "TwoInMux" 3 83, 3 8, S_0x166b880; + .timescale -9 -12; +L_0x16832b0/d .functor NOT 1, L_0x1683750, C4<0>, C4<0>, C4<0>; +L_0x16832b0 .delay (10000,10000,10000) L_0x16832b0/d; +L_0x1683370/d .functor AND 1, L_0x1683150, L_0x16832b0, C4<1>, C4<1>; +L_0x1683370 .delay (20000,20000,20000) L_0x1683370/d; +L_0x1683480/d .functor AND 1, L_0x1682cb0, L_0x1683750, C4<1>, C4<1>; +L_0x1683480 .delay (20000,20000,20000) L_0x1683480/d; +L_0x16835d0/d .functor OR 1, L_0x1683370, L_0x1683480, C4<0>, C4<0>; +L_0x16835d0 .delay (20000,20000,20000) L_0x16835d0/d; +v0x166bf50_0 .net "S", 0 0, L_0x1683750; 1 drivers +v0x166c010_0 .alias "in0", 0 0, v0x166c6a0_0; +v0x166c0b0_0 .alias "in1", 0 0, v0x166c510_0; +v0x166c150_0 .net "nS", 0 0, L_0x16832b0; 1 drivers +v0x166c1d0_0 .net "out0", 0 0, L_0x1683370; 1 drivers +v0x166c270_0 .net "out1", 0 0, L_0x1683480; 1 drivers +v0x166c350_0 .alias "outfinal", 0 0, v0x166c910_0; +S_0x166b970 .scope module, "mux1" "TwoInMux" 3 84, 3 8, S_0x166b880; + .timescale -9 -12; +L_0x16837f0/d .functor NOT 1, L_0x1683d20, C4<0>, C4<0>, C4<0>; +L_0x16837f0 .delay (10000,10000,10000) L_0x16837f0/d; +L_0x16838b0/d .functor AND 1, L_0x16835d0, L_0x16837f0, C4<1>, C4<1>; +L_0x16838b0 .delay (20000,20000,20000) L_0x16838b0/d; +L_0x1683a00/d .functor AND 1, L_0x1682db0, L_0x1683d20, C4<1>, C4<1>; +L_0x1683a00 .delay (20000,20000,20000) L_0x1683a00/d; +L_0x1683b50/d .functor OR 1, L_0x16838b0, L_0x1683a00, C4<0>, C4<0>; +L_0x1683b50 .delay (20000,20000,20000) L_0x1683b50/d; +v0x166ba60_0 .net "S", 0 0, L_0x1683d20; 1 drivers +v0x166bae0_0 .alias "in0", 0 0, v0x166c910_0; +v0x166bb60_0 .alias "in1", 0 0, v0x166c5c0_0; +v0x166bc00_0 .net "nS", 0 0, L_0x16837f0; 1 drivers +v0x166bc80_0 .net "out0", 0 0, L_0x16838b0; 1 drivers +v0x166bd20_0 .net "out1", 0 0, L_0x1683a00; 1 drivers +v0x166bdc0_0 .alias "outfinal", 0 0, v0x166c890_0; +S_0x166a4b0 .scope generate, "orbits[1]" "orbits[1]" 3 196, 3 196, S_0x1667b20; + .timescale -9 -12; +P_0x166a1c8 .param/l "i" 3 196, +C4<01>; +S_0x166a5e0 .scope module, "attempt" "OrNorXor" 3 198, 3 64, S_0x166a4b0; + .timescale -9 -12; +L_0x167efc0/d .functor NOR 1, L_0x16803a0, L_0x16771f0, C4<0>, C4<0>; +L_0x167efc0 .delay (10000,10000,10000) L_0x167efc0/d; +L_0x167f260/d .functor NOT 1, L_0x167efc0, C4<0>, C4<0>, C4<0>; +L_0x167f260 .delay (10000,10000,10000) L_0x167f260/d; +L_0x167f390/d .functor NAND 1, L_0x16803a0, L_0x16771f0, C4<1>, C4<1>; +L_0x167f390 .delay (10000,10000,10000) L_0x167f390/d; +L_0x167f4f0/d .functor NAND 1, L_0x167f390, L_0x167f260, C4<1>, C4<1>; +L_0x167f4f0 .delay (10000,10000,10000) L_0x167f4f0/d; +L_0x167f600/d .functor NOT 1, L_0x167f4f0, C4<0>, C4<0>, C4<0>; +L_0x167f600 .delay (10000,10000,10000) L_0x167f600/d; +v0x166b190_0 .net "A", 0 0, L_0x16803a0; 1 drivers +v0x166b230_0 .net "AnandB", 0 0, L_0x167f390; 1 drivers +v0x166b2d0_0 .net "AnorB", 0 0, L_0x167efc0; 1 drivers +v0x166b380_0 .net "AorB", 0 0, L_0x167f260; 1 drivers +v0x166b460_0 .net "AxorB", 0 0, L_0x167f600; 1 drivers +v0x166b510_0 .net "B", 0 0, L_0x16771f0; 1 drivers +v0x166b5d0_0 .alias "Command", 2 0, v0x1674750_0; +v0x166b650_0 .net "OrNorXorOut", 0 0, L_0x1680000; 1 drivers +v0x166b6d0_0 .net "XorNor", 0 0, L_0x167fa80; 1 drivers +v0x166b7a0_0 .net "nXor", 0 0, L_0x167f4f0; 1 drivers +L_0x167fc00 .part v0x1675810_0, 2, 1; +L_0x16801d0 .part v0x1675810_0, 0, 1; +S_0x166ac20 .scope module, "mux0" "TwoInMux" 3 83, 3 8, S_0x166a5e0; + .timescale -9 -12; +L_0x167f760/d .functor NOT 1, L_0x167fc00, C4<0>, C4<0>, C4<0>; +L_0x167f760 .delay (10000,10000,10000) L_0x167f760/d; +L_0x167f820/d .functor AND 1, L_0x167f600, L_0x167f760, C4<1>, C4<1>; +L_0x167f820 .delay (20000,20000,20000) L_0x167f820/d; +L_0x167f930/d .functor AND 1, L_0x167efc0, L_0x167fc00, C4<1>, C4<1>; +L_0x167f930 .delay (20000,20000,20000) L_0x167f930/d; +L_0x167fa80/d .functor OR 1, L_0x167f820, L_0x167f930, C4<0>, C4<0>; +L_0x167fa80 .delay (20000,20000,20000) L_0x167fa80/d; +v0x166ad10_0 .net "S", 0 0, L_0x167fc00; 1 drivers +v0x166add0_0 .alias "in0", 0 0, v0x166b460_0; +v0x166ae70_0 .alias "in1", 0 0, v0x166b2d0_0; +v0x166af10_0 .net "nS", 0 0, L_0x167f760; 1 drivers +v0x166af90_0 .net "out0", 0 0, L_0x167f820; 1 drivers +v0x166b030_0 .net "out1", 0 0, L_0x167f930; 1 drivers +v0x166b110_0 .alias "outfinal", 0 0, v0x166b6d0_0; +S_0x166a6d0 .scope module, "mux1" "TwoInMux" 3 84, 3 8, S_0x166a5e0; + .timescale -9 -12; +L_0x167fca0/d .functor NOT 1, L_0x16801d0, C4<0>, C4<0>, C4<0>; +L_0x167fca0 .delay (10000,10000,10000) L_0x167fca0/d; +L_0x167fd60/d .functor AND 1, L_0x167fa80, L_0x167fca0, C4<1>, C4<1>; +L_0x167fd60 .delay (20000,20000,20000) L_0x167fd60/d; +L_0x167feb0/d .functor AND 1, L_0x167f260, L_0x16801d0, C4<1>, C4<1>; +L_0x167feb0 .delay (20000,20000,20000) L_0x167feb0/d; +L_0x1680000/d .functor OR 1, L_0x167fd60, L_0x167feb0, C4<0>, C4<0>; +L_0x1680000 .delay (20000,20000,20000) L_0x1680000/d; +v0x166a7c0_0 .net "S", 0 0, L_0x16801d0; 1 drivers +v0x166a840_0 .alias "in0", 0 0, v0x166b6d0_0; +v0x166a8e0_0 .alias "in1", 0 0, v0x166b380_0; +v0x166a980_0 .net "nS", 0 0, L_0x167fca0; 1 drivers +v0x166aa00_0 .net "out0", 0 0, L_0x167fd60; 1 drivers +v0x166aaa0_0 .net "out1", 0 0, L_0x167feb0; 1 drivers +v0x166ab80_0 .alias "outfinal", 0 0, v0x166b650_0; +S_0x16690e0 .scope generate, "orbits[2]" "orbits[2]" 3 196, 3 196, S_0x1667b20; + .timescale -9 -12; +P_0x1668d48 .param/l "i" 3 196, +C4<010>; +S_0x1669210 .scope module, "attempt" "OrNorXor" 3 198, 3 64, S_0x16690e0; + .timescale -9 -12; +L_0x1677290/d .functor NOR 1, L_0x1681870, L_0x1681910, C4<0>, C4<0>; +L_0x1677290 .delay (10000,10000,10000) L_0x1677290/d; +L_0x1677400/d .functor NOT 1, L_0x1677290, C4<0>, C4<0>, C4<0>; +L_0x1677400 .delay (10000,10000,10000) L_0x1677400/d; +L_0x16808f0/d .functor NAND 1, L_0x1681870, L_0x1681910, C4<1>, C4<1>; +L_0x16808f0 .delay (10000,10000,10000) L_0x16808f0/d; +L_0x1680a50/d .functor NAND 1, L_0x16808f0, L_0x1677400, C4<1>, C4<1>; +L_0x1680a50 .delay (10000,10000,10000) L_0x1680a50/d; +L_0x1680b60/d .functor NOT 1, L_0x1680a50, C4<0>, C4<0>, C4<0>; +L_0x1680b60 .delay (10000,10000,10000) L_0x1680b60/d; +v0x1669dc0_0 .net "A", 0 0, L_0x1681870; 1 drivers +v0x1669e60_0 .net "AnandB", 0 0, L_0x16808f0; 1 drivers +v0x1669f00_0 .net "AnorB", 0 0, L_0x1677290; 1 drivers +v0x1669fb0_0 .net "AorB", 0 0, L_0x1677400; 1 drivers +v0x166a090_0 .net "AxorB", 0 0, L_0x1680b60; 1 drivers +v0x166a140_0 .net "B", 0 0, L_0x1681910; 1 drivers +v0x166a200_0 .alias "Command", 2 0, v0x1674750_0; +v0x166a280_0 .net "OrNorXorOut", 0 0, L_0x1681560; 1 drivers +v0x166a300_0 .net "XorNor", 0 0, L_0x1680fe0; 1 drivers +v0x166a3d0_0 .net "nXor", 0 0, L_0x1680a50; 1 drivers +L_0x1681160 .part v0x1675810_0, 2, 1; +L_0x1681730 .part v0x1675810_0, 0, 1; +S_0x1669850 .scope module, "mux0" "TwoInMux" 3 83, 3 8, S_0x1669210; + .timescale -9 -12; +L_0x1680cc0/d .functor NOT 1, L_0x1681160, C4<0>, C4<0>, C4<0>; +L_0x1680cc0 .delay (10000,10000,10000) L_0x1680cc0/d; +L_0x1680d80/d .functor AND 1, L_0x1680b60, L_0x1680cc0, C4<1>, C4<1>; +L_0x1680d80 .delay (20000,20000,20000) L_0x1680d80/d; +L_0x1680e90/d .functor AND 1, L_0x1677290, L_0x1681160, C4<1>, C4<1>; +L_0x1680e90 .delay (20000,20000,20000) L_0x1680e90/d; +L_0x1680fe0/d .functor OR 1, L_0x1680d80, L_0x1680e90, C4<0>, C4<0>; +L_0x1680fe0 .delay (20000,20000,20000) L_0x1680fe0/d; +v0x1669940_0 .net "S", 0 0, L_0x1681160; 1 drivers +v0x1669a00_0 .alias "in0", 0 0, v0x166a090_0; +v0x1669aa0_0 .alias "in1", 0 0, v0x1669f00_0; +v0x1669b40_0 .net "nS", 0 0, L_0x1680cc0; 1 drivers +v0x1669bc0_0 .net "out0", 0 0, L_0x1680d80; 1 drivers +v0x1669c60_0 .net "out1", 0 0, L_0x1680e90; 1 drivers +v0x1669d40_0 .alias "outfinal", 0 0, v0x166a300_0; +S_0x1669300 .scope module, "mux1" "TwoInMux" 3 84, 3 8, S_0x1669210; + .timescale -9 -12; +L_0x1681200/d .functor NOT 1, L_0x1681730, C4<0>, C4<0>, C4<0>; +L_0x1681200 .delay (10000,10000,10000) L_0x1681200/d; +L_0x16812c0/d .functor AND 1, L_0x1680fe0, L_0x1681200, C4<1>, C4<1>; +L_0x16812c0 .delay (20000,20000,20000) L_0x16812c0/d; +L_0x1681410/d .functor AND 1, L_0x1677400, L_0x1681730, C4<1>, C4<1>; +L_0x1681410 .delay (20000,20000,20000) L_0x1681410/d; +L_0x1681560/d .functor OR 1, L_0x16812c0, L_0x1681410, C4<0>, C4<0>; +L_0x1681560 .delay (20000,20000,20000) L_0x1681560/d; +v0x16693f0_0 .net "S", 0 0, L_0x1681730; 1 drivers +v0x1669470_0 .alias "in0", 0 0, v0x166a300_0; +v0x1669510_0 .alias "in1", 0 0, v0x1669fb0_0; +v0x16695b0_0 .net "nS", 0 0, L_0x1681200; 1 drivers +v0x1669630_0 .net "out0", 0 0, L_0x16812c0; 1 drivers +v0x16696d0_0 .net "out1", 0 0, L_0x1681410; 1 drivers +v0x16697b0_0 .alias "outfinal", 0 0, v0x166a280_0; +S_0x1667c50 .scope generate, "orbits[3]" "orbits[3]" 3 196, 3 196, S_0x1667b20; + .timescale -9 -12; +P_0x1667d48 .param/l "i" 3 196, +C4<011>; +S_0x1667dc0 .scope module, "attempt" "OrNorXor" 3 198, 3 64, S_0x1667c50; + .timescale -9 -12; +L_0x16819f0/d .functor NOR 1, L_0x1682b70, L_0x1682c10, C4<0>, C4<0>; +L_0x16819f0 .delay (10000,10000,10000) L_0x16819f0/d; +L_0x1681ae0/d .functor NOT 1, L_0x16819f0, C4<0>, C4<0>, C4<0>; +L_0x1681ae0 .delay (10000,10000,10000) L_0x1681ae0/d; +L_0x1681bf0/d .functor NAND 1, L_0x1682b70, L_0x1682c10, C4<1>, C4<1>; +L_0x1681bf0 .delay (10000,10000,10000) L_0x1681bf0/d; +L_0x1681d50/d .functor NAND 1, L_0x1681bf0, L_0x1681ae0, C4<1>, C4<1>; +L_0x1681d50 .delay (10000,10000,10000) L_0x1681d50/d; +L_0x1681e60/d .functor NOT 1, L_0x1681d50, C4<0>, C4<0>, C4<0>; +L_0x1681e60 .delay (10000,10000,10000) L_0x1681e60/d; +v0x1668940_0 .net "A", 0 0, L_0x1682b70; 1 drivers +v0x16689e0_0 .net "AnandB", 0 0, L_0x1681bf0; 1 drivers +v0x1668a80_0 .net "AnorB", 0 0, L_0x16819f0; 1 drivers +v0x1668b30_0 .net "AorB", 0 0, L_0x1681ae0; 1 drivers +v0x1668c10_0 .net "AxorB", 0 0, L_0x1681e60; 1 drivers +v0x1668cc0_0 .net "B", 0 0, L_0x1682c10; 1 drivers +v0x1668d80_0 .alias "Command", 2 0, v0x1674750_0; +v0x16617d0_0 .net "OrNorXorOut", 0 0, L_0x1682860; 1 drivers +v0x1661850_0 .net "XorNor", 0 0, L_0x16822e0; 1 drivers +v0x1669060_0 .net "nXor", 0 0, L_0x1681d50; 1 drivers +L_0x1682460 .part v0x1675810_0, 2, 1; +L_0x1682a30 .part v0x1675810_0, 0, 1; +S_0x16683d0 .scope module, "mux0" "TwoInMux" 3 83, 3 8, S_0x1667dc0; + .timescale -9 -12; +L_0x1681fc0/d .functor NOT 1, L_0x1682460, C4<0>, C4<0>, C4<0>; +L_0x1681fc0 .delay (10000,10000,10000) L_0x1681fc0/d; +L_0x1682080/d .functor AND 1, L_0x1681e60, L_0x1681fc0, C4<1>, C4<1>; +L_0x1682080 .delay (20000,20000,20000) L_0x1682080/d; +L_0x1682190/d .functor AND 1, L_0x16819f0, L_0x1682460, C4<1>, C4<1>; +L_0x1682190 .delay (20000,20000,20000) L_0x1682190/d; +L_0x16822e0/d .functor OR 1, L_0x1682080, L_0x1682190, C4<0>, C4<0>; +L_0x16822e0 .delay (20000,20000,20000) L_0x16822e0/d; +v0x16684c0_0 .net "S", 0 0, L_0x1682460; 1 drivers +v0x1668580_0 .alias "in0", 0 0, v0x1668c10_0; +v0x1668620_0 .alias "in1", 0 0, v0x1668a80_0; +v0x16686c0_0 .net "nS", 0 0, L_0x1681fc0; 1 drivers +v0x1668740_0 .net "out0", 0 0, L_0x1682080; 1 drivers +v0x16687e0_0 .net "out1", 0 0, L_0x1682190; 1 drivers +v0x16688c0_0 .alias "outfinal", 0 0, v0x1661850_0; +S_0x1667eb0 .scope module, "mux1" "TwoInMux" 3 84, 3 8, S_0x1667dc0; + .timescale -9 -12; +L_0x1682500/d .functor NOT 1, L_0x1682a30, C4<0>, C4<0>, C4<0>; +L_0x1682500 .delay (10000,10000,10000) L_0x1682500/d; +L_0x16825c0/d .functor AND 1, L_0x16822e0, L_0x1682500, C4<1>, C4<1>; +L_0x16825c0 .delay (20000,20000,20000) L_0x16825c0/d; +L_0x1682710/d .functor AND 1, L_0x1681ae0, L_0x1682a30, C4<1>, C4<1>; +L_0x1682710 .delay (20000,20000,20000) L_0x1682710/d; +L_0x1682860/d .functor OR 1, L_0x16825c0, L_0x1682710, C4<0>, C4<0>; +L_0x1682860 .delay (20000,20000,20000) L_0x1682860/d; +v0x1667fa0_0 .net "S", 0 0, L_0x1682a30; 1 drivers +v0x1668020_0 .alias "in0", 0 0, v0x1661850_0; +v0x16680a0_0 .alias "in1", 0 0, v0x1668b30_0; +v0x1668120_0 .net "nS", 0 0, L_0x1682500; 1 drivers +v0x16681d0_0 .net "out0", 0 0, L_0x16825c0; 1 drivers +v0x1668250_0 .net "out1", 0 0, L_0x1682710; 1 drivers +v0x1668330_0 .alias "outfinal", 0 0, v0x16617d0_0; +S_0x15d2f60 .scope module, "superalu" "Bitslice32" 2 162, 3 256, S_0x1615180; + .timescale -9 -12; +P_0x15d2218 .param/l "size" 3 272, +C4<0100>; +v0x16670a0_0 .alias "A", 3 0, v0x1674530_0; +v0x1667290_0 .alias "AddSubSLTSum", 3 0, v0x1675690_0; +v0x1667310_0 .alias "AndNandOut", 3 0, v0x1675710_0; +v0x1667390_0 .alias "B", 3 0, v0x1674650_0; +RS_0x7f44879d4608 .resolv tri, L_0x1684700, L_0x1686c00, L_0x1689510, L_0x16994a0; +v0x1667410_0 .net8 "Cmd0Start", 3 0, RS_0x7f44879d4608; 4 drivers +RS_0x7f44879d4638 .resolv tri, L_0x1685550, L_0x1687a00, L_0x168a4d0, L_0x169a260; +v0x1667490_0 .net8 "Cmd1Start", 3 0, RS_0x7f44879d4638; 4 drivers +v0x1667510_0 .alias "Command", 2 0, v0x1674750_0; +v0x1667590_0 .alias "OneBitFinalOut", 3 0, v0x1675890_0; +v0x1667660_0 .alias "OrNorXorOut", 3 0, v0x1675910_0; +v0x16676e0_0 .alias "SLTflag", 0 0, v0x1675990_0; +v0x1667760_0 .alias "ZeroFlag", 3 0, v0x1675a10_0; +v0x1667810_0 .alias "carryin", 3 0, v0x1675180_0; +v0x16678c0_0 .alias "carryout", 0 0, v0x1675b60_0; +v0x1667970_0 .alias "overflow", 0 0, v0x1675be0_0; +v0x1667aa0_0 .alias "subtract", 3 0, v0x1675c60_0; +L_0x1684700 .part/pv L_0x1684520, 1, 1, 4; +L_0x16847a0 .part v0x1675810_0, 0, 1; +L_0x16848d0 .part v0x1675810_0, 1, 1; +L_0x1684a00 .part RS_0x7f44879d4218, 1, 1; +L_0x1684aa0 .part RS_0x7f44879d4218, 1, 1; +L_0x1684b40 .part RS_0x7f44879d2d78, 1, 1; +L_0x1684d40 .part RS_0x7f44879d4218, 1, 1; +L_0x1685550 .part/pv L_0x1685370, 1, 1, 4; +L_0x1685640 .part v0x1675810_0, 0, 1; +L_0x1685770 .part v0x1675810_0, 1, 1; +L_0x1685900 .part RS_0x7f44879d3468, 1, 1; +L_0x1685ab0 .part RS_0x7f44879d3468, 1, 1; +L_0x1685b50 .part RS_0x7f44879d2d78, 1, 1; +L_0x1685bf0 .part RS_0x7f44879d2d78, 1, 1; +L_0x1686050 .part/pv L_0x1685f10, 1, 1, 4; +L_0x1686180 .part v0x1675810_0, 2, 1; +L_0x1686220 .part RS_0x7f44879d4608, 1, 1; +L_0x1686310 .part RS_0x7f44879d4638, 1, 1; +L_0x1686c00 .part/pv L_0x1686a20, 2, 1, 4; +L_0x1686ca0 .part v0x1675810_0, 0, 1; +L_0x1686450 .part v0x1675810_0, 1, 1; +L_0x1686f10 .part RS_0x7f44879d4218, 2, 1; +L_0x1686dd0 .part RS_0x7f44879d4218, 2, 1; +L_0x1687070 .part RS_0x7f44879d2d78, 2, 1; +L_0x1686fb0 .part RS_0x7f44879d4218, 2, 1; +L_0x1687a00 .part/pv L_0x16877f0, 2, 1, 4; +L_0x1687110 .part v0x1675810_0, 0, 1; +L_0x1676380 .part v0x1675810_0, 1, 1; +L_0x1687aa0 .part RS_0x7f44879d3468, 2, 1; +L_0x16765a0 .part RS_0x7f44879d3468, 2, 1; +L_0x16764b0 .part RS_0x7f44879d2d78, 2, 1; +L_0x1688420 .part RS_0x7f44879d2d78, 2, 1; +L_0x16888b0 .part/pv L_0x1688770, 2, 1, 4; +L_0x1688950 .part v0x1675810_0, 2, 1; +L_0x16884c0 .part RS_0x7f44879d4608, 2, 1; +L_0x1688ba0 .part RS_0x7f44879d4638, 2, 1; +L_0x1689510 .part/pv L_0x1689300, 3, 1, 4; +L_0x16895b0 .part v0x1675810_0, 0, 1; +L_0x1688cd0 .part v0x1675810_0, 1, 1; +L_0x1689820 .part RS_0x7f44879d4218, 3, 1; +L_0x167bfc0 .part RS_0x7f44879d4218, 3, 1; +L_0x16896e0 .part RS_0x7f44879d2d78, 3, 1; +L_0x1689c30 .part RS_0x7f44879d4218, 3, 1; +L_0x168a4d0 .part/pv L_0x168a2c0, 3, 1, 4; +L_0x1689ad0 .part v0x1675810_0, 0, 1; +L_0x168a6e0 .part v0x1675810_0, 1, 1; +L_0x168a570 .part RS_0x7f44879d3468, 3, 1; +L_0x168a610 .part RS_0x7f44879d3468, 3, 1; +L_0x168a9a0 .part RS_0x7f44879d2d78, 3, 1; +L_0x168aa90 .part RS_0x7f44879d2d78, 3, 1; +L_0x168b0c0 .part/pv L_0x168af80, 3, 1, 4; +L_0x168b160 .part v0x1675810_0, 2, 1; +L_0x168ad90 .part RS_0x7f44879d4608, 3, 1; +L_0x168ae80 .part RS_0x7f44879d4638, 3, 1; +L_0x16994a0 .part/pv L_0x16992c0, 0, 1, 4; +L_0x1699540 .part v0x1675810_0, 0, 1; +L_0x168b400 .part v0x1675810_0, 1, 1; +L_0x1699840 .part RS_0x7f44879d4218, 0, 1; +L_0x1699670 .part RS_0x7f44879d4218, 0, 1; +L_0x1699710 .part RS_0x7f44879d2d78, 0, 1; +L_0x1699ad0 .part RS_0x7f44879d4218, 0, 1; +L_0x169a260 .part/pv L_0x169a080, 0, 1, 4; +L_0x16998e0 .part v0x1675810_0, 0, 1; +L_0x1699a10 .part v0x1675810_0, 1, 1; +L_0x169a300 .part RS_0x7f44879d3468, 0, 1; +L_0x169a3a0 .part RS_0x7f44879d3468, 0, 1; +L_0x169a440 .part RS_0x7f44879d2d78, 0, 1; +L_0x169a800 .part RS_0x7f44879d2d78, 0, 1; +L_0x169ad10 .part/pv L_0x169abd0, 0, 1, 4; +L_0x169adb0 .part v0x1675810_0, 2, 1; +L_0x169a8f0 .part RS_0x7f44879d4608, 0, 1; +L_0x169b090 .part RS_0x7f44879d4638, 0, 1; +S_0x1661ac0 .scope module, "trial" "AddSubSLT32" 3 277, 3 205, S_0x15d2f60; + .timescale -9 -12; +P_0x1661bb8 .param/l "size" 3 228, +C4<0100>; +L_0x1690430/d .functor OR 1, L_0x16906f0, C4<0>, C4<0>, C4<0>; +L_0x1690430 .delay (20000,20000,20000) L_0x1690430/d; +L_0x16908a0/d .functor XOR 1, RS_0x7f44879d4518, L_0x1690990, C4<0>, C4<0>; +L_0x16908a0 .delay (40000,40000,40000) L_0x16908a0/d; +L_0x1690620/d .functor AND 1, L_0x1690b60, L_0x1690c00, C4<1>, C4<1>; +L_0x1690620 .delay (20000,20000,20000) L_0x1690620/d; +L_0x1690a30/d .functor NOT 1, RS_0x7f44879d45a8, C4<0>, C4<0>, C4<0>; +L_0x1690a30 .delay (10000,10000,10000) L_0x1690a30/d; +L_0x1690ef0/d .functor NOT 1, L_0x1690f50, C4<0>, C4<0>, C4<0>; +L_0x1690ef0 .delay (10000,10000,10000) L_0x1690ef0/d; +L_0x1690ff0/d .functor AND 1, L_0x1690a30, L_0x1691130, C4<1>, C4<1>; +L_0x1690ff0 .delay (20000,20000,20000) L_0x1690ff0/d; +L_0x1690cf0/d .functor AND 1, RS_0x7f44879d45a8, L_0x1690ef0, C4<1>, C4<1>; +L_0x1690cf0 .delay (20000,20000,20000) L_0x1690cf0/d; +L_0x1691320/d .functor AND 1, L_0x1690ff0, L_0x1690620, C4<1>, C4<1>; +L_0x1691320 .delay (20000,20000,20000) L_0x1691320/d; +L_0x1691460/d .functor AND 1, L_0x1690cf0, L_0x1690620, C4<1>, C4<1>; +L_0x1691460 .delay (20000,20000,20000) L_0x1691460/d; +L_0x1691580/d .functor OR 1, L_0x1691320, L_0x1691460, C4<0>, C4<0>; +L_0x1691580 .delay (20000,20000,20000) L_0x1691580/d; +v0x1666180_0 .alias "A", 3 0, v0x1674530_0; +v0x1666200_0 .alias "AddSubSLTSum", 3 0, v0x1675690_0; +v0x1666280_0 .alias "B", 3 0, v0x1674650_0; +RS_0x7f44879d4248 .resolv tri, L_0x168c400, L_0x168d820, L_0x168ec20, L_0x16901a0; +v0x1666350_0 .net8 "CarryoutWire", 3 0, RS_0x7f44879d4248; 4 drivers +v0x16663d0_0 .alias "Command", 2 0, v0x1674750_0; +v0x1666450_0 .net "Res0OF1", 0 0, L_0x1690cf0; 1 drivers +v0x1666510_0 .net "Res1OF0", 0 0, L_0x1690ff0; 1 drivers +v0x16665b0_0 .alias "SLTflag", 0 0, v0x1675990_0; +v0x16666a0_0 .net "SLTflag0", 0 0, L_0x1691320; 1 drivers +v0x1666740_0 .net "SLTflag1", 0 0, L_0x1691460; 1 drivers +v0x1666840_0 .net "SLTon", 0 0, L_0x1690620; 1 drivers +v0x16668e0_0 .net *"_s40", 0 0, L_0x16906f0; 1 drivers +v0x1666980_0 .net/s *"_s41", 0 0, C4<0>; 1 drivers +v0x1666a20_0 .net *"_s44", 0 0, L_0x1690990; 1 drivers +v0x1666b40_0 .net *"_s46", 0 0, L_0x1690b60; 1 drivers +v0x1666be0_0 .net *"_s48", 0 0, L_0x1690c00; 1 drivers +v0x1666aa0_0 .net *"_s50", 0 0, L_0x1690f50; 1 drivers +v0x1666d30_0 .net *"_s52", 0 0, L_0x1691130; 1 drivers +v0x1666e50_0 .alias "carryin", 3 0, v0x1675180_0; +v0x1666ed0_0 .alias "carryout", 0 0, v0x1675b60_0; +v0x1666db0_0 .net "nAddSubSLTSum", 0 0, L_0x1690ef0; 1 drivers +v0x1667000_0 .net "nOF", 0 0, L_0x1690a30; 1 drivers +v0x1666f50_0 .alias "overflow", 0 0, v0x1675be0_0; +v0x1667140_0 .alias "subtract", 3 0, v0x1675c60_0; +L_0x168c310 .part/pv L_0x168be80, 1, 1, 4; +L_0x168c400 .part/pv L_0x168c1d0, 1, 1, 4; +L_0x168c4f0 .part/pv L_0x168bbb0, 1, 1, 4; +L_0x168c5e0 .part v0x1675610_0, 1, 1; +L_0x168c680 .part v0x1675790_0, 1, 1; +L_0x168c7b0 .part RS_0x7f44879d4248, 0, 1; +L_0x168d730 .part/pv L_0x168d2a0, 2, 1, 4; +L_0x168d820 .part/pv L_0x168d5f0, 2, 1, 4; +L_0x168d960 .part/pv L_0x168cfd0, 2, 1, 4; +L_0x168da50 .part v0x1675610_0, 2, 1; +L_0x168db50 .part v0x1675790_0, 2, 1; +L_0x168dc80 .part RS_0x7f44879d4248, 1, 1; +L_0x168eb30 .part/pv L_0x168e6a0, 3, 1, 4; +L_0x168ec20 .part/pv L_0x168e9f0, 3, 1, 4; +L_0x168ed90 .part/pv L_0x168e3d0, 3, 1, 4; +L_0x168ee80 .part v0x1675610_0, 3, 1; +L_0x168efb0 .part v0x1675790_0, 3, 1; +L_0x168f0e0 .part RS_0x7f44879d4248, 2, 1; +L_0x16900b0 .part/pv L_0x168fbe0, 0, 1, 4; +L_0x16901a0 .part/pv L_0x168ff50, 0, 1, 4; +L_0x168f180 .part/pv L_0x168f910, 0, 1, 4; +L_0x1690390 .part v0x1675610_0, 0, 1; +L_0x1690290 .part v0x1675790_0, 0, 1; +L_0x1690580 .part RS_0x7f44879d45d8, 0, 1; +L_0x16906f0 .part RS_0x7f44879d4248, 3, 1; +L_0x1690990 .part RS_0x7f44879d4248, 2, 1; +L_0x1690b60 .part v0x1675810_0, 1, 1; +L_0x1690c00 .part RS_0x7f44879d45d8, 0, 1; +L_0x1690f50 .part RS_0x7f44879d4218, 3, 1; +L_0x1691130 .part RS_0x7f44879d4218, 3, 1; +S_0x16651c0 .scope module, "attempt2" "MiddleAddSubSLT" 3 225, 3 89, S_0x1661ac0; + .timescale -9 -12; +L_0x168ef20/d .functor NOT 1, L_0x1690290, C4<0>, C4<0>, C4<0>; +L_0x168ef20 .delay (10000,10000,10000) L_0x168ef20/d; +L_0x168f7b0/d .functor NOT 1, L_0x168f870, C4<0>, C4<0>, C4<0>; +L_0x168f7b0 .delay (10000,10000,10000) L_0x168f7b0/d; +L_0x168f910/d .functor AND 1, L_0x168fa50, L_0x168f7b0, C4<1>, C4<1>; +L_0x168f910 .delay (20000,20000,20000) L_0x168f910/d; +L_0x168faf0/d .functor XOR 1, L_0x1690390, L_0x168f540, C4<0>, C4<0>; +L_0x168faf0 .delay (40000,40000,40000) L_0x168faf0/d; +L_0x168fbe0/d .functor XOR 1, L_0x168faf0, L_0x1690580, C4<0>, C4<0>; +L_0x168fbe0 .delay (40000,40000,40000) L_0x168fbe0/d; +L_0x168fcd0/d .functor AND 1, L_0x1690390, L_0x168f540, C4<1>, C4<1>; +L_0x168fcd0 .delay (20000,20000,20000) L_0x168fcd0/d; +L_0x168fe40/d .functor AND 1, L_0x168faf0, L_0x1690580, C4<1>, C4<1>; +L_0x168fe40 .delay (20000,20000,20000) L_0x168fe40/d; +L_0x168ff50/d .functor OR 1, L_0x168fcd0, L_0x168fe40, C4<0>, C4<0>; +L_0x168ff50 .delay (20000,20000,20000) L_0x168ff50/d; +v0x1665830_0 .net "A", 0 0, L_0x1690390; 1 drivers +v0x16658f0_0 .net "AandB", 0 0, L_0x168fcd0; 1 drivers +v0x1665990_0 .net "AddSubSLTSum", 0 0, L_0x168fbe0; 1 drivers +v0x1665a30_0 .net "AxorB", 0 0, L_0x168faf0; 1 drivers +v0x1665ab0_0 .net "B", 0 0, L_0x1690290; 1 drivers +v0x1665b60_0 .net "BornB", 0 0, L_0x168f540; 1 drivers +v0x1665c20_0 .net "CINandAxorB", 0 0, L_0x168fe40; 1 drivers +v0x1665ca0_0 .alias "Command", 2 0, v0x1674750_0; +v0x1665d20_0 .net *"_s3", 0 0, L_0x168f870; 1 drivers +v0x1665da0_0 .net *"_s5", 0 0, L_0x168fa50; 1 drivers +v0x1665e40_0 .net "carryin", 0 0, L_0x1690580; 1 drivers +v0x1665ee0_0 .net "carryout", 0 0, L_0x168ff50; 1 drivers +v0x1665f80_0 .net "nB", 0 0, L_0x168ef20; 1 drivers +v0x1666000_0 .net "nCmd2", 0 0, L_0x168f7b0; 1 drivers +v0x1666100_0 .net "subtract", 0 0, L_0x168f910; 1 drivers +L_0x168f710 .part v0x1675810_0, 0, 1; +L_0x168f870 .part v0x1675810_0, 2, 1; +L_0x168fa50 .part v0x1675810_0, 0, 1; +S_0x16652b0 .scope module, "mux0" "TwoInMux" 3 105, 3 8, S_0x16651c0; + .timescale -9 -12; +L_0x168f2c0/d .functor NOT 1, L_0x168f710, C4<0>, C4<0>, C4<0>; +L_0x168f2c0 .delay (10000,10000,10000) L_0x168f2c0/d; +L_0x168f320/d .functor AND 1, L_0x1690290, L_0x168f2c0, C4<1>, C4<1>; +L_0x168f320 .delay (20000,20000,20000) L_0x168f320/d; +L_0x168f430/d .functor AND 1, L_0x168ef20, L_0x168f710, C4<1>, C4<1>; +L_0x168f430 .delay (20000,20000,20000) L_0x168f430/d; +L_0x168f540/d .functor OR 1, L_0x168f320, L_0x168f430, C4<0>, C4<0>; +L_0x168f540 .delay (20000,20000,20000) L_0x168f540/d; +v0x16653a0_0 .net "S", 0 0, L_0x168f710; 1 drivers +v0x1665460_0 .alias "in0", 0 0, v0x1665ab0_0; +v0x1665500_0 .alias "in1", 0 0, v0x1665f80_0; +v0x16655a0_0 .net "nS", 0 0, L_0x168f2c0; 1 drivers +v0x1665650_0 .net "out0", 0 0, L_0x168f320; 1 drivers +v0x16656f0_0 .net "out1", 0 0, L_0x168f430; 1 drivers +v0x1665790_0 .alias "outfinal", 0 0, v0x1665b60_0; +S_0x1664020 .scope generate, "addbits[1]" "addbits[1]" 3 230, 3 230, S_0x1661ac0; + .timescale -9 -12; +P_0x1663a38 .param/l "i" 3 230, +C4<01>; +S_0x1664190 .scope module, "attempt" "MiddleAddSubSLT" 3 232, 3 89, S_0x1664020; + .timescale -9 -12; +L_0x168b200/d .functor NOT 1, L_0x168c680, C4<0>, C4<0>, C4<0>; +L_0x168b200 .delay (10000,10000,10000) L_0x168b200/d; +L_0x168ba70/d .functor NOT 1, L_0x168bb10, C4<0>, C4<0>, C4<0>; +L_0x168ba70 .delay (10000,10000,10000) L_0x168ba70/d; +L_0x168bbb0/d .functor AND 1, L_0x168bcf0, L_0x168ba70, C4<1>, C4<1>; +L_0x168bbb0 .delay (20000,20000,20000) L_0x168bbb0/d; +L_0x168bd90/d .functor XOR 1, L_0x168c5e0, L_0x168b840, C4<0>, C4<0>; +L_0x168bd90 .delay (40000,40000,40000) L_0x168bd90/d; +L_0x168be80/d .functor XOR 1, L_0x168bd90, L_0x168c7b0, C4<0>, C4<0>; +L_0x168be80 .delay (40000,40000,40000) L_0x168be80/d; +L_0x168bf70/d .functor AND 1, L_0x168c5e0, L_0x168b840, C4<1>, C4<1>; +L_0x168bf70 .delay (20000,20000,20000) L_0x168bf70/d; +L_0x168c0e0/d .functor AND 1, L_0x168bd90, L_0x168c7b0, C4<1>, C4<1>; +L_0x168c0e0 .delay (20000,20000,20000) L_0x168c0e0/d; +L_0x168c1d0/d .functor OR 1, L_0x168bf70, L_0x168c0e0, C4<0>, C4<0>; +L_0x168c1d0 .delay (20000,20000,20000) L_0x168c1d0/d; +v0x1664820_0 .net "A", 0 0, L_0x168c5e0; 1 drivers +v0x16648e0_0 .net "AandB", 0 0, L_0x168bf70; 1 drivers +v0x1664980_0 .net "AddSubSLTSum", 0 0, L_0x168be80; 1 drivers +v0x1664a20_0 .net "AxorB", 0 0, L_0x168bd90; 1 drivers +v0x1664aa0_0 .net "B", 0 0, L_0x168c680; 1 drivers +v0x1664b50_0 .net "BornB", 0 0, L_0x168b840; 1 drivers +v0x1664c10_0 .net "CINandAxorB", 0 0, L_0x168c0e0; 1 drivers +v0x1664c90_0 .alias "Command", 2 0, v0x1674750_0; +v0x1664d10_0 .net *"_s3", 0 0, L_0x168bb10; 1 drivers +v0x1664d90_0 .net *"_s5", 0 0, L_0x168bcf0; 1 drivers +v0x1664e30_0 .net "carryin", 0 0, L_0x168c7b0; 1 drivers +v0x1664ed0_0 .net "carryout", 0 0, L_0x168c1d0; 1 drivers +v0x1664f70_0 .net "nB", 0 0, L_0x168b200; 1 drivers +v0x1665020_0 .net "nCmd2", 0 0, L_0x168ba70; 1 drivers +v0x1665120_0 .net "subtract", 0 0, L_0x168bbb0; 1 drivers +L_0x168b9d0 .part v0x1675810_0, 0, 1; +L_0x168bb10 .part v0x1675810_0, 2, 1; +L_0x168bcf0 .part v0x1675810_0, 0, 1; +S_0x1664280 .scope module, "mux0" "TwoInMux" 3 105, 3 8, S_0x1664190; + .timescale -9 -12; +L_0x168b5c0/d .functor NOT 1, L_0x168b9d0, C4<0>, C4<0>, C4<0>; +L_0x168b5c0 .delay (10000,10000,10000) L_0x168b5c0/d; +L_0x168b660/d .functor AND 1, L_0x168c680, L_0x168b5c0, C4<1>, C4<1>; +L_0x168b660 .delay (20000,20000,20000) L_0x168b660/d; +L_0x168b750/d .functor AND 1, L_0x168b200, L_0x168b9d0, C4<1>, C4<1>; +L_0x168b750 .delay (20000,20000,20000) L_0x168b750/d; +L_0x168b840/d .functor OR 1, L_0x168b660, L_0x168b750, C4<0>, C4<0>; +L_0x168b840 .delay (20000,20000,20000) L_0x168b840/d; +v0x1664370_0 .net "S", 0 0, L_0x168b9d0; 1 drivers +v0x1664410_0 .alias "in0", 0 0, v0x1664aa0_0; +v0x16644b0_0 .alias "in1", 0 0, v0x1664f70_0; +v0x1664550_0 .net "nS", 0 0, L_0x168b5c0; 1 drivers +v0x1664600_0 .net "out0", 0 0, L_0x168b660; 1 drivers +v0x16646a0_0 .net "out1", 0 0, L_0x168b750; 1 drivers +v0x1664780_0 .alias "outfinal", 0 0, v0x1664b50_0; +S_0x1662e80 .scope generate, "addbits[2]" "addbits[2]" 3 230, 3 230, S_0x1661ac0; + .timescale -9 -12; +P_0x16627c8 .param/l "i" 3 230, +C4<010>; +S_0x1662ff0 .scope module, "attempt" "MiddleAddSubSLT" 3 232, 3 89, S_0x1662e80; + .timescale -9 -12; +L_0x168c850/d .functor NOT 1, L_0x168db50, C4<0>, C4<0>, C4<0>; +L_0x168c850 .delay (10000,10000,10000) L_0x168c850/d; +L_0x168ce90/d .functor NOT 1, L_0x168cf30, C4<0>, C4<0>, C4<0>; +L_0x168ce90 .delay (10000,10000,10000) L_0x168ce90/d; +L_0x168cfd0/d .functor AND 1, L_0x168d110, L_0x168ce90, C4<1>, C4<1>; +L_0x168cfd0 .delay (20000,20000,20000) L_0x168cfd0/d; +L_0x168d1b0/d .functor XOR 1, L_0x168da50, L_0x168cc60, C4<0>, C4<0>; +L_0x168d1b0 .delay (40000,40000,40000) L_0x168d1b0/d; +L_0x168d2a0/d .functor XOR 1, L_0x168d1b0, L_0x168dc80, C4<0>, C4<0>; +L_0x168d2a0 .delay (40000,40000,40000) L_0x168d2a0/d; +L_0x168d390/d .functor AND 1, L_0x168da50, L_0x168cc60, C4<1>, C4<1>; +L_0x168d390 .delay (20000,20000,20000) L_0x168d390/d; +L_0x168d500/d .functor AND 1, L_0x168d1b0, L_0x168dc80, C4<1>, C4<1>; +L_0x168d500 .delay (20000,20000,20000) L_0x168d500/d; +L_0x168d5f0/d .functor OR 1, L_0x168d390, L_0x168d500, C4<0>, C4<0>; +L_0x168d5f0 .delay (20000,20000,20000) L_0x168d5f0/d; +v0x1663680_0 .net "A", 0 0, L_0x168da50; 1 drivers +v0x1663740_0 .net "AandB", 0 0, L_0x168d390; 1 drivers +v0x16637e0_0 .net "AddSubSLTSum", 0 0, L_0x168d2a0; 1 drivers +v0x1663880_0 .net "AxorB", 0 0, L_0x168d1b0; 1 drivers +v0x1663900_0 .net "B", 0 0, L_0x168db50; 1 drivers +v0x16639b0_0 .net "BornB", 0 0, L_0x168cc60; 1 drivers +v0x1663a70_0 .net "CINandAxorB", 0 0, L_0x168d500; 1 drivers +v0x1663af0_0 .alias "Command", 2 0, v0x1674750_0; +v0x1663b70_0 .net *"_s3", 0 0, L_0x168cf30; 1 drivers +v0x1663bf0_0 .net *"_s5", 0 0, L_0x168d110; 1 drivers +v0x1663c90_0 .net "carryin", 0 0, L_0x168dc80; 1 drivers +v0x1663d30_0 .net "carryout", 0 0, L_0x168d5f0; 1 drivers +v0x1663dd0_0 .net "nB", 0 0, L_0x168c850; 1 drivers +v0x1663e80_0 .net "nCmd2", 0 0, L_0x168ce90; 1 drivers +v0x1663f80_0 .net "subtract", 0 0, L_0x168cfd0; 1 drivers +L_0x168cdf0 .part v0x1675810_0, 0, 1; +L_0x168cf30 .part v0x1675810_0, 2, 1; +L_0x168d110 .part v0x1675810_0, 0, 1; +S_0x16630e0 .scope module, "mux0" "TwoInMux" 3 105, 3 8, S_0x1662ff0; + .timescale -9 -12; +L_0x168c9e0/d .functor NOT 1, L_0x168cdf0, C4<0>, C4<0>, C4<0>; +L_0x168c9e0 .delay (10000,10000,10000) L_0x168c9e0/d; +L_0x168ca80/d .functor AND 1, L_0x168db50, L_0x168c9e0, C4<1>, C4<1>; +L_0x168ca80 .delay (20000,20000,20000) L_0x168ca80/d; +L_0x168cb70/d .functor AND 1, L_0x168c850, L_0x168cdf0, C4<1>, C4<1>; +L_0x168cb70 .delay (20000,20000,20000) L_0x168cb70/d; +L_0x168cc60/d .functor OR 1, L_0x168ca80, L_0x168cb70, C4<0>, C4<0>; +L_0x168cc60 .delay (20000,20000,20000) L_0x168cc60/d; +v0x16631d0_0 .net "S", 0 0, L_0x168cdf0; 1 drivers +v0x1663270_0 .alias "in0", 0 0, v0x1663900_0; +v0x1663310_0 .alias "in1", 0 0, v0x1663dd0_0; +v0x16633b0_0 .net "nS", 0 0, L_0x168c9e0; 1 drivers +v0x1663460_0 .net "out0", 0 0, L_0x168ca80; 1 drivers +v0x1663500_0 .net "out1", 0 0, L_0x168cb70; 1 drivers +v0x16635e0_0 .alias "outfinal", 0 0, v0x16639b0_0; +S_0x1661c30 .scope generate, "addbits[3]" "addbits[3]" 3 230, 3 230, S_0x1661ac0; + .timescale -9 -12; +P_0x1661d28 .param/l "i" 3 230, +C4<011>; +S_0x1661da0 .scope module, "attempt" "MiddleAddSubSLT" 3 232, 3 89, S_0x1661c30; + .timescale -9 -12; +L_0x168daf0/d .functor NOT 1, L_0x168efb0, C4<0>, C4<0>, C4<0>; +L_0x168daf0 .delay (10000,10000,10000) L_0x168daf0/d; +L_0x168e290/d .functor NOT 1, L_0x168e330, C4<0>, C4<0>, C4<0>; +L_0x168e290 .delay (10000,10000,10000) L_0x168e290/d; +L_0x168e3d0/d .functor AND 1, L_0x168e510, L_0x168e290, C4<1>, C4<1>; +L_0x168e3d0 .delay (20000,20000,20000) L_0x168e3d0/d; +L_0x168e5b0/d .functor XOR 1, L_0x168ee80, L_0x168e060, C4<0>, C4<0>; +L_0x168e5b0 .delay (40000,40000,40000) L_0x168e5b0/d; +L_0x168e6a0/d .functor XOR 1, L_0x168e5b0, L_0x168f0e0, C4<0>, C4<0>; +L_0x168e6a0 .delay (40000,40000,40000) L_0x168e6a0/d; +L_0x168e790/d .functor AND 1, L_0x168ee80, L_0x168e060, C4<1>, C4<1>; +L_0x168e790 .delay (20000,20000,20000) L_0x168e790/d; +L_0x168e900/d .functor AND 1, L_0x168e5b0, L_0x168f0e0, C4<1>, C4<1>; +L_0x168e900 .delay (20000,20000,20000) L_0x168e900/d; +L_0x168e9f0/d .functor OR 1, L_0x168e790, L_0x168e900, C4<0>, C4<0>; +L_0x168e9f0 .delay (20000,20000,20000) L_0x168e9f0/d; +v0x1662410_0 .net "A", 0 0, L_0x168ee80; 1 drivers +v0x16624d0_0 .net "AandB", 0 0, L_0x168e790; 1 drivers +v0x1662570_0 .net "AddSubSLTSum", 0 0, L_0x168e6a0; 1 drivers +v0x1662610_0 .net "AxorB", 0 0, L_0x168e5b0; 1 drivers +v0x1662690_0 .net "B", 0 0, L_0x168efb0; 1 drivers +v0x1662740_0 .net "BornB", 0 0, L_0x168e060; 1 drivers +v0x1662800_0 .net "CINandAxorB", 0 0, L_0x168e900; 1 drivers +v0x1662880_0 .alias "Command", 2 0, v0x1674750_0; +v0x1662900_0 .net *"_s3", 0 0, L_0x168e330; 1 drivers +v0x1662980_0 .net *"_s5", 0 0, L_0x168e510; 1 drivers +v0x1662a80_0 .net "carryin", 0 0, L_0x168f0e0; 1 drivers +v0x1662b20_0 .net "carryout", 0 0, L_0x168e9f0; 1 drivers +v0x1662c30_0 .net "nB", 0 0, L_0x168daf0; 1 drivers +v0x1662ce0_0 .net "nCmd2", 0 0, L_0x168e290; 1 drivers +v0x1662de0_0 .net "subtract", 0 0, L_0x168e3d0; 1 drivers +L_0x168e1f0 .part v0x1675810_0, 0, 1; +L_0x168e330 .part v0x1675810_0, 2, 1; +L_0x168e510 .part v0x1675810_0, 0, 1; +S_0x1661e90 .scope module, "mux0" "TwoInMux" 3 105, 3 8, S_0x1661da0; + .timescale -9 -12; +L_0x168de20/d .functor NOT 1, L_0x168e1f0, C4<0>, C4<0>, C4<0>; +L_0x168de20 .delay (10000,10000,10000) L_0x168de20/d; +L_0x168de80/d .functor AND 1, L_0x168efb0, L_0x168de20, C4<1>, C4<1>; +L_0x168de80 .delay (20000,20000,20000) L_0x168de80/d; +L_0x168df70/d .functor AND 1, L_0x168daf0, L_0x168e1f0, C4<1>, C4<1>; +L_0x168df70 .delay (20000,20000,20000) L_0x168df70/d; +L_0x168e060/d .functor OR 1, L_0x168de80, L_0x168df70, C4<0>, C4<0>; +L_0x168e060 .delay (20000,20000,20000) L_0x168e060/d; +v0x1661f80_0 .net "S", 0 0, L_0x168e1f0; 1 drivers +v0x1662000_0 .alias "in0", 0 0, v0x1662690_0; +v0x16620a0_0 .alias "in1", 0 0, v0x1662c30_0; +v0x1662140_0 .net "nS", 0 0, L_0x168de20; 1 drivers +v0x16621f0_0 .net "out0", 0 0, L_0x168de80; 1 drivers +v0x1662290_0 .net "out1", 0 0, L_0x168df70; 1 drivers +v0x1662370_0 .alias "outfinal", 0 0, v0x1662740_0; +S_0x165e880 .scope module, "trial1" "AndNand32" 3 278, 3 154, S_0x15d2f60; + .timescale -9 -12; +P_0x165e308 .param/l "size" 3 161, +C4<0100>; +v0x165e770_0 .alias "A", 3 0, v0x1674530_0; +v0x16618e0_0 .alias "AndNandOut", 3 0, v0x1675710_0; +v0x1661960_0 .alias "B", 3 0, v0x1674650_0; +v0x1661a10_0 .alias "Command", 2 0, v0x1674750_0; +L_0x1691ee0 .part/pv L_0x1691c70, 1, 1, 4; +L_0x1691fa0 .part v0x1675610_0, 1, 1; +L_0x1692040 .part v0x1675790_0, 1, 1; +L_0x1692950 .part/pv L_0x16926e0, 2, 1, 4; +L_0x16929f0 .part v0x1675610_0, 2, 1; +L_0x1692a90 .part v0x1675790_0, 2, 1; +L_0x16933c0 .part/pv L_0x1693150, 3, 1, 4; +L_0x16859a0 .part v0x1675610_0, 3, 1; +L_0x1693670 .part v0x1675790_0, 3, 1; +L_0x1693f20 .part/pv L_0x1693cb0, 0, 1, 4; +L_0x1694020 .part v0x1675610_0, 0, 1; +L_0x16940c0 .part v0x1675790_0, 0, 1; +S_0x1660da0 .scope module, "attempt2" "AndNand" 3 165, 3 48, S_0x165e880; + .timescale -9 -12; +L_0x1693760/d .functor NAND 1, L_0x1694020, L_0x16940c0, C4<1>, C4<1>; +L_0x1693760 .delay (10000,10000,10000) L_0x1693760/d; +L_0x1693860/d .functor NOT 1, L_0x1693760, C4<0>, C4<0>, C4<0>; +L_0x1693860 .delay (10000,10000,10000) L_0x1693860/d; +v0x16613c0_0 .net "A", 0 0, L_0x1694020; 1 drivers +v0x1661480_0 .net "AandB", 0 0, L_0x1693860; 1 drivers +v0x1661500_0 .net "AnandB", 0 0, L_0x1693760; 1 drivers +v0x16615b0_0 .net "AndNandOut", 0 0, L_0x1693cb0; 1 drivers +v0x1661690_0 .net "B", 0 0, L_0x16940c0; 1 drivers +v0x1661710_0 .alias "Command", 2 0, v0x1674750_0; +L_0x1693e80 .part v0x1675810_0, 0, 1; +S_0x1660e90 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0x1660da0; + .timescale -9 -12; +L_0x1693990/d .functor NOT 1, L_0x1693e80, C4<0>, C4<0>, C4<0>; +L_0x1693990 .delay (10000,10000,10000) L_0x1693990/d; +L_0x1693a50/d .functor AND 1, L_0x1693860, L_0x1693990, C4<1>, C4<1>; +L_0x1693a50 .delay (20000,20000,20000) L_0x1693a50/d; +L_0x1693b60/d .functor AND 1, L_0x1693760, L_0x1693e80, C4<1>, C4<1>; +L_0x1693b60 .delay (20000,20000,20000) L_0x1693b60/d; +L_0x1693cb0/d .functor OR 1, L_0x1693a50, L_0x1693b60, C4<0>, C4<0>; +L_0x1693cb0 .delay (20000,20000,20000) L_0x1693cb0/d; +v0x1660f80_0 .net "S", 0 0, L_0x1693e80; 1 drivers +v0x1661000_0 .alias "in0", 0 0, v0x1661480_0; +v0x1661080_0 .alias "in1", 0 0, v0x1661500_0; +v0x1661120_0 .net "nS", 0 0, L_0x1693990; 1 drivers +v0x16611a0_0 .net "out0", 0 0, L_0x1693a50; 1 drivers +v0x1661240_0 .net "out1", 0 0, L_0x1693b60; 1 drivers +v0x1661320_0 .alias "outfinal", 0 0, v0x16615b0_0; +S_0x16601e0 .scope generate, "andbits[1]" "andbits[1]" 3 169, 3 169, S_0x165e880; + .timescale -9 -12; +P_0x16602d8 .param/l "i" 3 169, +C4<01>; +S_0x1660350 .scope module, "attempt" "AndNand" 3 171, 3 48, S_0x16601e0; + .timescale -9 -12; +L_0x1691760/d .functor NAND 1, L_0x1691fa0, L_0x1692040, C4<1>, C4<1>; +L_0x1691760 .delay (10000,10000,10000) L_0x1691760/d; +L_0x1691820/d .functor NOT 1, L_0x1691760, C4<0>, C4<0>, C4<0>; +L_0x1691820 .delay (10000,10000,10000) L_0x1691820/d; +v0x1660990_0 .net "A", 0 0, L_0x1691fa0; 1 drivers +v0x1660a50_0 .net "AandB", 0 0, L_0x1691820; 1 drivers +v0x1660ad0_0 .net "AnandB", 0 0, L_0x1691760; 1 drivers +v0x1660b80_0 .net "AndNandOut", 0 0, L_0x1691c70; 1 drivers +v0x1660c60_0 .net "B", 0 0, L_0x1692040; 1 drivers +v0x1660ce0_0 .alias "Command", 2 0, v0x1674750_0; +L_0x1691e40 .part v0x1675810_0, 0, 1; +S_0x1660440 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0x1660350; + .timescale -9 -12; +L_0x1691950/d .functor NOT 1, L_0x1691e40, C4<0>, C4<0>, C4<0>; +L_0x1691950 .delay (10000,10000,10000) L_0x1691950/d; +L_0x1691a10/d .functor AND 1, L_0x1691820, L_0x1691950, C4<1>, C4<1>; +L_0x1691a10 .delay (20000,20000,20000) L_0x1691a10/d; +L_0x1691b20/d .functor AND 1, L_0x1691760, L_0x1691e40, C4<1>, C4<1>; +L_0x1691b20 .delay (20000,20000,20000) L_0x1691b20/d; +L_0x1691c70/d .functor OR 1, L_0x1691a10, L_0x1691b20, C4<0>, C4<0>; +L_0x1691c70 .delay (20000,20000,20000) L_0x1691c70/d; +v0x1660530_0 .net "S", 0 0, L_0x1691e40; 1 drivers +v0x16605b0_0 .alias "in0", 0 0, v0x1660a50_0; +v0x1660650_0 .alias "in1", 0 0, v0x1660ad0_0; +v0x16606f0_0 .net "nS", 0 0, L_0x1691950; 1 drivers +v0x1660770_0 .net "out0", 0 0, L_0x1691a10; 1 drivers +v0x1660810_0 .net "out1", 0 0, L_0x1691b20; 1 drivers +v0x16608f0_0 .alias "outfinal", 0 0, v0x1660b80_0; +S_0x165f620 .scope generate, "andbits[2]" "andbits[2]" 3 169, 3 169, S_0x165e880; + .timescale -9 -12; +P_0x165f718 .param/l "i" 3 169, +C4<010>; +S_0x165f790 .scope module, "attempt" "AndNand" 3 171, 3 48, S_0x165f620; + .timescale -9 -12; +L_0x1692130/d .functor NAND 1, L_0x16929f0, L_0x1692a90, C4<1>, C4<1>; +L_0x1692130 .delay (10000,10000,10000) L_0x1692130/d; +L_0x1692290/d .functor NOT 1, L_0x1692130, C4<0>, C4<0>, C4<0>; +L_0x1692290 .delay (10000,10000,10000) L_0x1692290/d; +v0x165fdd0_0 .net "A", 0 0, L_0x16929f0; 1 drivers +v0x165fe90_0 .net "AandB", 0 0, L_0x1692290; 1 drivers +v0x165ff10_0 .net "AnandB", 0 0, L_0x1692130; 1 drivers +v0x165ffc0_0 .net "AndNandOut", 0 0, L_0x16926e0; 1 drivers +v0x16600a0_0 .net "B", 0 0, L_0x1692a90; 1 drivers +v0x1660120_0 .alias "Command", 2 0, v0x1674750_0; +L_0x16928b0 .part v0x1675810_0, 0, 1; +S_0x165f880 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0x165f790; + .timescale -9 -12; +L_0x16923c0/d .functor NOT 1, L_0x16928b0, C4<0>, C4<0>, C4<0>; +L_0x16923c0 .delay (10000,10000,10000) L_0x16923c0/d; +L_0x1692480/d .functor AND 1, L_0x1692290, L_0x16923c0, C4<1>, C4<1>; +L_0x1692480 .delay (20000,20000,20000) L_0x1692480/d; +L_0x1692590/d .functor AND 1, L_0x1692130, L_0x16928b0, C4<1>, C4<1>; +L_0x1692590 .delay (20000,20000,20000) L_0x1692590/d; +L_0x16926e0/d .functor OR 1, L_0x1692480, L_0x1692590, C4<0>, C4<0>; +L_0x16926e0 .delay (20000,20000,20000) L_0x16926e0/d; +v0x165f970_0 .net "S", 0 0, L_0x16928b0; 1 drivers +v0x165f9f0_0 .alias "in0", 0 0, v0x165fe90_0; +v0x165fa90_0 .alias "in1", 0 0, v0x165ff10_0; +v0x165fb30_0 .net "nS", 0 0, L_0x16923c0; 1 drivers +v0x165fbb0_0 .net "out0", 0 0, L_0x1692480; 1 drivers +v0x165fc50_0 .net "out1", 0 0, L_0x1692590; 1 drivers +v0x165fd30_0 .alias "outfinal", 0 0, v0x165ffc0_0; +S_0x165e9f0 .scope generate, "andbits[3]" "andbits[3]" 3 169, 3 169, S_0x165e880; + .timescale -9 -12; +P_0x165eae8 .param/l "i" 3 169, +C4<011>; +S_0x165eb80 .scope module, "attempt" "AndNand" 3 171, 3 48, S_0x165e9f0; + .timescale -9 -12; +L_0x1692bc0/d .functor NAND 1, L_0x16859a0, L_0x1693670, C4<1>, C4<1>; +L_0x1692bc0 .delay (10000,10000,10000) L_0x1692bc0/d; +L_0x1692d00/d .functor NOT 1, L_0x1692bc0, C4<0>, C4<0>, C4<0>; +L_0x1692d00 .delay (10000,10000,10000) L_0x1692d00/d; +v0x165f210_0 .net "A", 0 0, L_0x16859a0; 1 drivers +v0x165f2d0_0 .net "AandB", 0 0, L_0x1692d00; 1 drivers +v0x165f350_0 .net "AnandB", 0 0, L_0x1692bc0; 1 drivers +v0x165f400_0 .net "AndNandOut", 0 0, L_0x1693150; 1 drivers +v0x165f4e0_0 .net "B", 0 0, L_0x1693670; 1 drivers +v0x165f560_0 .alias "Command", 2 0, v0x1674750_0; +L_0x1693320 .part v0x1675810_0, 0, 1; +S_0x165ec70 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0x165eb80; + .timescale -9 -12; +L_0x1692e30/d .functor NOT 1, L_0x1693320, C4<0>, C4<0>, C4<0>; +L_0x1692e30 .delay (10000,10000,10000) L_0x1692e30/d; +L_0x1692ef0/d .functor AND 1, L_0x1692d00, L_0x1692e30, C4<1>, C4<1>; +L_0x1692ef0 .delay (20000,20000,20000) L_0x1692ef0/d; +L_0x1693000/d .functor AND 1, L_0x1692bc0, L_0x1693320, C4<1>, C4<1>; +L_0x1693000 .delay (20000,20000,20000) L_0x1693000/d; +L_0x1693150/d .functor OR 1, L_0x1692ef0, L_0x1693000, C4<0>, C4<0>; +L_0x1693150 .delay (20000,20000,20000) L_0x1693150/d; +v0x165ed60_0 .net "S", 0 0, L_0x1693320; 1 drivers +v0x165ee00_0 .alias "in0", 0 0, v0x165f2d0_0; +v0x165eea0_0 .alias "in1", 0 0, v0x165f350_0; +v0x165ef40_0 .net "nS", 0 0, L_0x1692e30; 1 drivers +v0x165eff0_0 .net "out0", 0 0, L_0x1692ef0; 1 drivers +v0x165f090_0 .net "out1", 0 0, L_0x1693000; 1 drivers +v0x165f170_0 .alias "outfinal", 0 0, v0x165f400_0; +S_0x1659660 .scope module, "trial2" "OrNorXor32" 3 279, 3 177, S_0x15d2f60; + .timescale -9 -12; +P_0x16587b8 .param/l "size" 3 184, +C4<0100>; +v0x165e5f0_0 .alias "A", 3 0, v0x1674530_0; +v0x165e670_0 .alias "B", 3 0, v0x1674650_0; +v0x165e6f0_0 .alias "Command", 2 0, v0x1674750_0; +v0x165e800_0 .alias "OrNorXorOut", 3 0, v0x1675910_0; +L_0x1695270 .part/pv L_0x1695000, 1, 1, 4; +L_0x1695310 .part v0x1675610_0, 1, 1; +L_0x16953b0 .part v0x1675790_0, 1, 1; +L_0x1696570 .part/pv L_0x1696300, 2, 1, 4; +L_0x1696610 .part v0x1675610_0, 2, 1; +L_0x16966b0 .part v0x1675790_0, 2, 1; +L_0x1697870 .part/pv L_0x1697600, 3, 1, 4; +L_0x1697910 .part v0x1675610_0, 3, 1; +L_0x16979b0 .part v0x1675790_0, 3, 1; +L_0x1698b60 .part/pv L_0x16988f0, 0, 1, 4; +L_0x1698c60 .part v0x1675610_0, 0, 1; +L_0x1698d00 .part v0x1675790_0, 0, 1; +S_0x165d3e0 .scope module, "attempt2" "OrNorXor" 3 192, 3 64, S_0x1659660; + .timescale -9 -12; +L_0x1697a50/d .functor NOR 1, L_0x1698c60, L_0x1698d00, C4<0>, C4<0>; +L_0x1697a50 .delay (10000,10000,10000) L_0x1697a50/d; +L_0x1697b50/d .functor NOT 1, L_0x1697a50, C4<0>, C4<0>, C4<0>; +L_0x1697b50 .delay (10000,10000,10000) L_0x1697b50/d; +L_0x1697c80/d .functor NAND 1, L_0x1698c60, L_0x1698d00, C4<1>, C4<1>; +L_0x1697c80 .delay (10000,10000,10000) L_0x1697c80/d; +L_0x1697de0/d .functor NAND 1, L_0x1697c80, L_0x1697b50, C4<1>, C4<1>; +L_0x1697de0 .delay (10000,10000,10000) L_0x1697de0/d; +L_0x1697ef0/d .functor NOT 1, L_0x1697de0, C4<0>, C4<0>, C4<0>; +L_0x1697ef0 .delay (10000,10000,10000) L_0x1697ef0/d; +v0x165df30_0 .net "A", 0 0, L_0x1698c60; 1 drivers +v0x165dfd0_0 .net "AnandB", 0 0, L_0x1697c80; 1 drivers +v0x165e070_0 .net "AnorB", 0 0, L_0x1697a50; 1 drivers +v0x165e0f0_0 .net "AorB", 0 0, L_0x1697b50; 1 drivers +v0x165e1d0_0 .net "AxorB", 0 0, L_0x1697ef0; 1 drivers +v0x165e280_0 .net "B", 0 0, L_0x1698d00; 1 drivers +v0x165e340_0 .alias "Command", 2 0, v0x1674750_0; +v0x165e3c0_0 .net "OrNorXorOut", 0 0, L_0x16988f0; 1 drivers +v0x165e440_0 .net "XorNor", 0 0, L_0x1698370; 1 drivers +v0x165e510_0 .net "nXor", 0 0, L_0x1697de0; 1 drivers +L_0x16984f0 .part v0x1675810_0, 2, 1; +L_0x1698ac0 .part v0x1675810_0, 0, 1; +S_0x165d9c0 .scope module, "mux0" "TwoInMux" 3 83, 3 8, S_0x165d3e0; + .timescale -9 -12; +L_0x1698050/d .functor NOT 1, L_0x16984f0, C4<0>, C4<0>, C4<0>; +L_0x1698050 .delay (10000,10000,10000) L_0x1698050/d; +L_0x1698110/d .functor AND 1, L_0x1697ef0, L_0x1698050, C4<1>, C4<1>; +L_0x1698110 .delay (20000,20000,20000) L_0x1698110/d; +L_0x1698220/d .functor AND 1, L_0x1697a50, L_0x16984f0, C4<1>, C4<1>; +L_0x1698220 .delay (20000,20000,20000) L_0x1698220/d; +L_0x1698370/d .functor OR 1, L_0x1698110, L_0x1698220, C4<0>, C4<0>; +L_0x1698370 .delay (20000,20000,20000) L_0x1698370/d; +v0x165dab0_0 .net "S", 0 0, L_0x16984f0; 1 drivers +v0x165db70_0 .alias "in0", 0 0, v0x165e1d0_0; +v0x165dc10_0 .alias "in1", 0 0, v0x165e070_0; +v0x165dcb0_0 .net "nS", 0 0, L_0x1698050; 1 drivers +v0x165dd30_0 .net "out0", 0 0, L_0x1698110; 1 drivers +v0x165ddd0_0 .net "out1", 0 0, L_0x1698220; 1 drivers +v0x165deb0_0 .alias "outfinal", 0 0, v0x165e440_0; +S_0x165d4d0 .scope module, "mux1" "TwoInMux" 3 84, 3 8, S_0x165d3e0; + .timescale -9 -12; +L_0x1698590/d .functor NOT 1, L_0x1698ac0, C4<0>, C4<0>, C4<0>; +L_0x1698590 .delay (10000,10000,10000) L_0x1698590/d; +L_0x1698650/d .functor AND 1, L_0x1698370, L_0x1698590, C4<1>, C4<1>; +L_0x1698650 .delay (20000,20000,20000) L_0x1698650/d; +L_0x16987a0/d .functor AND 1, L_0x1697b50, L_0x1698ac0, C4<1>, C4<1>; +L_0x16987a0 .delay (20000,20000,20000) L_0x16987a0/d; +L_0x16988f0/d .functor OR 1, L_0x1698650, L_0x16987a0, C4<0>, C4<0>; +L_0x16988f0 .delay (20000,20000,20000) L_0x16988f0/d; +v0x165d5c0_0 .net "S", 0 0, L_0x1698ac0; 1 drivers +v0x165d640_0 .alias "in0", 0 0, v0x165e440_0; +v0x165d6c0_0 .alias "in1", 0 0, v0x165e0f0_0; +v0x165d760_0 .net "nS", 0 0, L_0x1698590; 1 drivers +v0x165d7e0_0 .net "out0", 0 0, L_0x1698650; 1 drivers +v0x165d880_0 .net "out1", 0 0, L_0x16987a0; 1 drivers +v0x165d920_0 .alias "outfinal", 0 0, v0x165e3c0_0; +S_0x165bfe0 .scope generate, "orbits[1]" "orbits[1]" 3 196, 3 196, S_0x1659660; + .timescale -9 -12; +P_0x165bcc8 .param/l "i" 3 196, +C4<01>; +S_0x165c110 .scope module, "attempt" "OrNorXor" 3 198, 3 64, S_0x165bfe0; + .timescale -9 -12; +L_0x1693fc0/d .functor NOR 1, L_0x1695310, L_0x16953b0, C4<0>, C4<0>; +L_0x1693fc0 .delay (10000,10000,10000) L_0x1693fc0/d; +L_0x1694260/d .functor NOT 1, L_0x1693fc0, C4<0>, C4<0>, C4<0>; +L_0x1694260 .delay (10000,10000,10000) L_0x1694260/d; +L_0x1694390/d .functor NAND 1, L_0x1695310, L_0x16953b0, C4<1>, C4<1>; +L_0x1694390 .delay (10000,10000,10000) L_0x1694390/d; +L_0x16944f0/d .functor NAND 1, L_0x1694390, L_0x1694260, C4<1>, C4<1>; +L_0x16944f0 .delay (10000,10000,10000) L_0x16944f0/d; +L_0x1694600/d .functor NOT 1, L_0x16944f0, C4<0>, C4<0>, C4<0>; +L_0x1694600 .delay (10000,10000,10000) L_0x1694600/d; +v0x165cca0_0 .net "A", 0 0, L_0x1695310; 1 drivers +v0x165cd40_0 .net "AnandB", 0 0, L_0x1694390; 1 drivers +v0x165cde0_0 .net "AnorB", 0 0, L_0x1693fc0; 1 drivers +v0x165ce90_0 .net "AorB", 0 0, L_0x1694260; 1 drivers +v0x165cf70_0 .net "AxorB", 0 0, L_0x1694600; 1 drivers +v0x165d020_0 .net "B", 0 0, L_0x16953b0; 1 drivers +v0x165d0e0_0 .alias "Command", 2 0, v0x1674750_0; +v0x165d160_0 .net "OrNorXorOut", 0 0, L_0x1695000; 1 drivers +v0x165d230_0 .net "XorNor", 0 0, L_0x1694a80; 1 drivers +v0x165d300_0 .net "nXor", 0 0, L_0x16944f0; 1 drivers +L_0x1694c00 .part v0x1675810_0, 2, 1; +L_0x16951d0 .part v0x1675810_0, 0, 1; +S_0x165c730 .scope module, "mux0" "TwoInMux" 3 83, 3 8, S_0x165c110; + .timescale -9 -12; +L_0x1694760/d .functor NOT 1, L_0x1694c00, C4<0>, C4<0>, C4<0>; +L_0x1694760 .delay (10000,10000,10000) L_0x1694760/d; +L_0x1694820/d .functor AND 1, L_0x1694600, L_0x1694760, C4<1>, C4<1>; +L_0x1694820 .delay (20000,20000,20000) L_0x1694820/d; +L_0x1694930/d .functor AND 1, L_0x1693fc0, L_0x1694c00, C4<1>, C4<1>; +L_0x1694930 .delay (20000,20000,20000) L_0x1694930/d; +L_0x1694a80/d .functor OR 1, L_0x1694820, L_0x1694930, C4<0>, C4<0>; +L_0x1694a80 .delay (20000,20000,20000) L_0x1694a80/d; +v0x165c820_0 .net "S", 0 0, L_0x1694c00; 1 drivers +v0x165c8e0_0 .alias "in0", 0 0, v0x165cf70_0; +v0x165c980_0 .alias "in1", 0 0, v0x165cde0_0; +v0x165ca20_0 .net "nS", 0 0, L_0x1694760; 1 drivers +v0x165caa0_0 .net "out0", 0 0, L_0x1694820; 1 drivers +v0x165cb40_0 .net "out1", 0 0, L_0x1694930; 1 drivers +v0x165cc20_0 .alias "outfinal", 0 0, v0x165d230_0; +S_0x165c200 .scope module, "mux1" "TwoInMux" 3 84, 3 8, S_0x165c110; + .timescale -9 -12; +L_0x1694ca0/d .functor NOT 1, L_0x16951d0, C4<0>, C4<0>, C4<0>; +L_0x1694ca0 .delay (10000,10000,10000) L_0x1694ca0/d; +L_0x1694d60/d .functor AND 1, L_0x1694a80, L_0x1694ca0, C4<1>, C4<1>; +L_0x1694d60 .delay (20000,20000,20000) L_0x1694d60/d; +L_0x1694eb0/d .functor AND 1, L_0x1694260, L_0x16951d0, C4<1>, C4<1>; +L_0x1694eb0 .delay (20000,20000,20000) L_0x1694eb0/d; +L_0x1695000/d .functor OR 1, L_0x1694d60, L_0x1694eb0, C4<0>, C4<0>; +L_0x1695000 .delay (20000,20000,20000) L_0x1695000/d; +v0x165c2f0_0 .net "S", 0 0, L_0x16951d0; 1 drivers +v0x165c370_0 .alias "in0", 0 0, v0x165d230_0; +v0x165c3f0_0 .alias "in1", 0 0, v0x165ce90_0; +v0x165c490_0 .net "nS", 0 0, L_0x1694ca0; 1 drivers +v0x165c510_0 .net "out0", 0 0, L_0x1694d60; 1 drivers +v0x165c5b0_0 .net "out1", 0 0, L_0x1694eb0; 1 drivers +v0x165c690_0 .alias "outfinal", 0 0, v0x165d160_0; +S_0x165abc0 .scope generate, "orbits[2]" "orbits[2]" 3 196, 3 196, S_0x1659660; + .timescale -9 -12; +P_0x165a938 .param/l "i" 3 196, +C4<010>; +S_0x165acf0 .scope module, "attempt" "OrNorXor" 3 198, 3 64, S_0x165abc0; + .timescale -9 -12; +L_0x1695450/d .functor NOR 1, L_0x1696610, L_0x16966b0, C4<0>, C4<0>; +L_0x1695450 .delay (10000,10000,10000) L_0x1695450/d; +L_0x1695560/d .functor NOT 1, L_0x1695450, C4<0>, C4<0>, C4<0>; +L_0x1695560 .delay (10000,10000,10000) L_0x1695560/d; +L_0x1695690/d .functor NAND 1, L_0x1696610, L_0x16966b0, C4<1>, C4<1>; +L_0x1695690 .delay (10000,10000,10000) L_0x1695690/d; +L_0x16957f0/d .functor NAND 1, L_0x1695690, L_0x1695560, C4<1>, C4<1>; +L_0x16957f0 .delay (10000,10000,10000) L_0x16957f0/d; +L_0x1695900/d .functor NOT 1, L_0x16957f0, C4<0>, C4<0>, C4<0>; +L_0x1695900 .delay (10000,10000,10000) L_0x1695900/d; +v0x165b8c0_0 .net "A", 0 0, L_0x1696610; 1 drivers +v0x165b960_0 .net "AnandB", 0 0, L_0x1695690; 1 drivers +v0x165ba00_0 .net "AnorB", 0 0, L_0x1695450; 1 drivers +v0x165bab0_0 .net "AorB", 0 0, L_0x1695560; 1 drivers +v0x165bb90_0 .net "AxorB", 0 0, L_0x1695900; 1 drivers +v0x165bc40_0 .net "B", 0 0, L_0x16966b0; 1 drivers +v0x165bd00_0 .alias "Command", 2 0, v0x1674750_0; +v0x165bd80_0 .net "OrNorXorOut", 0 0, L_0x1696300; 1 drivers +v0x165be30_0 .net "XorNor", 0 0, L_0x1695d80; 1 drivers +v0x165bf00_0 .net "nXor", 0 0, L_0x16957f0; 1 drivers +L_0x1695f00 .part v0x1675810_0, 2, 1; +L_0x16964d0 .part v0x1675810_0, 0, 1; +S_0x165b350 .scope module, "mux0" "TwoInMux" 3 83, 3 8, S_0x165acf0; + .timescale -9 -12; +L_0x1695a60/d .functor NOT 1, L_0x1695f00, C4<0>, C4<0>, C4<0>; +L_0x1695a60 .delay (10000,10000,10000) L_0x1695a60/d; +L_0x1695b20/d .functor AND 1, L_0x1695900, L_0x1695a60, C4<1>, C4<1>; +L_0x1695b20 .delay (20000,20000,20000) L_0x1695b20/d; +L_0x1695c30/d .functor AND 1, L_0x1695450, L_0x1695f00, C4<1>, C4<1>; +L_0x1695c30 .delay (20000,20000,20000) L_0x1695c30/d; +L_0x1695d80/d .functor OR 1, L_0x1695b20, L_0x1695c30, C4<0>, C4<0>; +L_0x1695d80 .delay (20000,20000,20000) L_0x1695d80/d; +v0x165b440_0 .net "S", 0 0, L_0x1695f00; 1 drivers +v0x165b500_0 .alias "in0", 0 0, v0x165bb90_0; +v0x165b5a0_0 .alias "in1", 0 0, v0x165ba00_0; +v0x165b640_0 .net "nS", 0 0, L_0x1695a60; 1 drivers +v0x165b6c0_0 .net "out0", 0 0, L_0x1695b20; 1 drivers +v0x165b760_0 .net "out1", 0 0, L_0x1695c30; 1 drivers +v0x165b840_0 .alias "outfinal", 0 0, v0x165be30_0; +S_0x165ade0 .scope module, "mux1" "TwoInMux" 3 84, 3 8, S_0x165acf0; + .timescale -9 -12; +L_0x1695fa0/d .functor NOT 1, L_0x16964d0, C4<0>, C4<0>, C4<0>; +L_0x1695fa0 .delay (10000,10000,10000) L_0x1695fa0/d; +L_0x1696060/d .functor AND 1, L_0x1695d80, L_0x1695fa0, C4<1>, C4<1>; +L_0x1696060 .delay (20000,20000,20000) L_0x1696060/d; +L_0x16961b0/d .functor AND 1, L_0x1695560, L_0x16964d0, C4<1>, C4<1>; +L_0x16961b0 .delay (20000,20000,20000) L_0x16961b0/d; +L_0x1696300/d .functor OR 1, L_0x1696060, L_0x16961b0, C4<0>, C4<0>; +L_0x1696300 .delay (20000,20000,20000) L_0x1696300/d; +v0x165aed0_0 .net "S", 0 0, L_0x16964d0; 1 drivers +v0x165af70_0 .alias "in0", 0 0, v0x165be30_0; +v0x165b010_0 .alias "in1", 0 0, v0x165bab0_0; +v0x165b0b0_0 .net "nS", 0 0, L_0x1695fa0; 1 drivers +v0x165b130_0 .net "out0", 0 0, L_0x1696060; 1 drivers +v0x165b1d0_0 .net "out1", 0 0, L_0x16961b0; 1 drivers +v0x165b2b0_0 .alias "outfinal", 0 0, v0x165bd80_0; +S_0x16597d0 .scope generate, "orbits[3]" "orbits[3]" 3 196, 3 196, S_0x1659660; + .timescale -9 -12; +P_0x16598c8 .param/l "i" 3 196, +C4<011>; +S_0x1659960 .scope module, "attempt" "OrNorXor" 3 198, 3 64, S_0x16597d0; + .timescale -9 -12; +L_0x1696790/d .functor NOR 1, L_0x1697910, L_0x16979b0, C4<0>, C4<0>; +L_0x1696790 .delay (10000,10000,10000) L_0x1696790/d; +L_0x1696880/d .functor NOT 1, L_0x1696790, C4<0>, C4<0>, C4<0>; +L_0x1696880 .delay (10000,10000,10000) L_0x1696880/d; +L_0x1696990/d .functor NAND 1, L_0x1697910, L_0x16979b0, C4<1>, C4<1>; +L_0x1696990 .delay (10000,10000,10000) L_0x1696990/d; +L_0x1696af0/d .functor NAND 1, L_0x1696990, L_0x1696880, C4<1>, C4<1>; +L_0x1696af0 .delay (10000,10000,10000) L_0x1696af0/d; +L_0x1696c00/d .functor NOT 1, L_0x1696af0, C4<0>, C4<0>, C4<0>; +L_0x1696c00 .delay (10000,10000,10000) L_0x1696c00/d; +v0x165a530_0 .net "A", 0 0, L_0x1697910; 1 drivers +v0x165a5d0_0 .net "AnandB", 0 0, L_0x1696990; 1 drivers +v0x165a670_0 .net "AnorB", 0 0, L_0x1696790; 1 drivers +v0x165a720_0 .net "AorB", 0 0, L_0x1696880; 1 drivers +v0x165a800_0 .net "AxorB", 0 0, L_0x1696c00; 1 drivers +v0x165a8b0_0 .net "B", 0 0, L_0x16979b0; 1 drivers +v0x165a970_0 .alias "Command", 2 0, v0x1674750_0; +v0x165a9f0_0 .net "OrNorXorOut", 0 0, L_0x1697600; 1 drivers +v0x165aa70_0 .net "XorNor", 0 0, L_0x1697080; 1 drivers +v0x165ab40_0 .net "nXor", 0 0, L_0x1696af0; 1 drivers +L_0x1697200 .part v0x1675810_0, 2, 1; +L_0x16977d0 .part v0x1675810_0, 0, 1; +S_0x1659fc0 .scope module, "mux0" "TwoInMux" 3 83, 3 8, S_0x1659960; + .timescale -9 -12; +L_0x1696d60/d .functor NOT 1, L_0x1697200, C4<0>, C4<0>, C4<0>; +L_0x1696d60 .delay (10000,10000,10000) L_0x1696d60/d; +L_0x1696e20/d .functor AND 1, L_0x1696c00, L_0x1696d60, C4<1>, C4<1>; +L_0x1696e20 .delay (20000,20000,20000) L_0x1696e20/d; +L_0x1696f30/d .functor AND 1, L_0x1696790, L_0x1697200, C4<1>, C4<1>; +L_0x1696f30 .delay (20000,20000,20000) L_0x1696f30/d; +L_0x1697080/d .functor OR 1, L_0x1696e20, L_0x1696f30, C4<0>, C4<0>; +L_0x1697080 .delay (20000,20000,20000) L_0x1697080/d; +v0x165a0b0_0 .net "S", 0 0, L_0x1697200; 1 drivers +v0x165a170_0 .alias "in0", 0 0, v0x165a800_0; +v0x165a210_0 .alias "in1", 0 0, v0x165a670_0; +v0x165a2b0_0 .net "nS", 0 0, L_0x1696d60; 1 drivers +v0x165a330_0 .net "out0", 0 0, L_0x1696e20; 1 drivers +v0x165a3d0_0 .net "out1", 0 0, L_0x1696f30; 1 drivers +v0x165a4b0_0 .alias "outfinal", 0 0, v0x165aa70_0; +S_0x1659a50 .scope module, "mux1" "TwoInMux" 3 84, 3 8, S_0x1659960; + .timescale -9 -12; +L_0x16972a0/d .functor NOT 1, L_0x16977d0, C4<0>, C4<0>, C4<0>; +L_0x16972a0 .delay (10000,10000,10000) L_0x16972a0/d; +L_0x1697360/d .functor AND 1, L_0x1697080, L_0x16972a0, C4<1>, C4<1>; +L_0x1697360 .delay (20000,20000,20000) L_0x1697360/d; +L_0x16974b0/d .functor AND 1, L_0x1696880, L_0x16977d0, C4<1>, C4<1>; +L_0x16974b0 .delay (20000,20000,20000) L_0x16974b0/d; +L_0x1697600/d .functor OR 1, L_0x1697360, L_0x16974b0, C4<0>, C4<0>; +L_0x1697600 .delay (20000,20000,20000) L_0x1697600/d; +v0x1659b40_0 .net "S", 0 0, L_0x16977d0; 1 drivers +v0x1659be0_0 .alias "in0", 0 0, v0x165aa70_0; +v0x1659c80_0 .alias "in1", 0 0, v0x165a720_0; +v0x1659d20_0 .net "nS", 0 0, L_0x16972a0; 1 drivers +v0x1659da0_0 .net "out0", 0 0, L_0x1697360; 1 drivers +v0x1659e40_0 .net "out1", 0 0, L_0x16974b0; 1 drivers +v0x1659f20_0 .alias "outfinal", 0 0, v0x165a9f0_0; +S_0x1658ce0 .scope module, "ZeroMux0case" "FourInMux" 3 281, 3 24, S_0x15d2f60; + .timescale -9 -12; +L_0x1698c00/d .functor NOT 1, L_0x1699540, C4<0>, C4<0>, C4<0>; +L_0x1698c00 .delay (10000,10000,10000) L_0x1698c00/d; +L_0x1698e50/d .functor NOT 1, L_0x168b400, C4<0>, C4<0>, C4<0>; +L_0x1698e50 .delay (10000,10000,10000) L_0x1698e50/d; +L_0x1698f10/d .functor NAND 1, L_0x1698c00, L_0x1698e50, L_0x1699840, C4<1>; +L_0x1698f10 .delay (10000,10000,10000) L_0x1698f10/d; +L_0x1699000/d .functor NAND 1, L_0x1699540, L_0x1698e50, L_0x1699670, C4<1>; +L_0x1699000 .delay (10000,10000,10000) L_0x1699000/d; +L_0x16990f0/d .functor NAND 1, L_0x1698c00, L_0x168b400, L_0x1699710, C4<1>; +L_0x16990f0 .delay (10000,10000,10000) L_0x16990f0/d; +L_0x16991e0/d .functor NAND 1, L_0x1699540, L_0x168b400, L_0x1699ad0, C4<1>; +L_0x16991e0 .delay (10000,10000,10000) L_0x16991e0/d; +L_0x16992c0/d .functor NAND 1, L_0x1698f10, L_0x1699000, L_0x16990f0, L_0x16991e0; +L_0x16992c0 .delay (10000,10000,10000) L_0x16992c0/d; +v0x1658dd0_0 .net "S0", 0 0, L_0x1699540; 1 drivers +v0x1658e90_0 .net "S1", 0 0, L_0x168b400; 1 drivers +v0x1658f30_0 .net "in0", 0 0, L_0x1699840; 1 drivers +v0x1658fd0_0 .net "in1", 0 0, L_0x1699670; 1 drivers +v0x1659050_0 .net "in2", 0 0, L_0x1699710; 1 drivers +v0x16590f0_0 .net "in3", 0 0, L_0x1699ad0; 1 drivers +v0x1659190_0 .net "nS0", 0 0, L_0x1698c00; 1 drivers +v0x1659230_0 .net "nS1", 0 0, L_0x1698e50; 1 drivers +v0x16592d0_0 .net "out", 0 0, L_0x16992c0; 1 drivers +v0x1659370_0 .net "out0", 0 0, L_0x1698f10; 1 drivers +v0x1659410_0 .net "out1", 0 0, L_0x1699000; 1 drivers +v0x16594b0_0 .net "out2", 0 0, L_0x16990f0; 1 drivers +v0x16595c0_0 .net "out3", 0 0, L_0x16991e0; 1 drivers +S_0x1658320 .scope module, "OneMux0case" "FourInMux" 3 282, 3 24, S_0x15d2f60; + .timescale -9 -12; +L_0x1699b70/d .functor NOT 1, L_0x16998e0, C4<0>, C4<0>, C4<0>; +L_0x1699b70 .delay (10000,10000,10000) L_0x1699b70/d; +L_0x1699c20/d .functor NOT 1, L_0x1699a10, C4<0>, C4<0>, C4<0>; +L_0x1699c20 .delay (10000,10000,10000) L_0x1699c20/d; +L_0x1699c80/d .functor NAND 1, L_0x1699b70, L_0x1699c20, L_0x169a300, C4<1>; +L_0x1699c80 .delay (10000,10000,10000) L_0x1699c80/d; +L_0x1699dc0/d .functor NAND 1, L_0x16998e0, L_0x1699c20, L_0x169a3a0, C4<1>; +L_0x1699dc0 .delay (10000,10000,10000) L_0x1699dc0/d; +L_0x1699eb0/d .functor NAND 1, L_0x1699b70, L_0x1699a10, L_0x169a440, C4<1>; +L_0x1699eb0 .delay (10000,10000,10000) L_0x1699eb0/d; +L_0x1699fa0/d .functor NAND 1, L_0x16998e0, L_0x1699a10, L_0x169a800, C4<1>; +L_0x1699fa0 .delay (10000,10000,10000) L_0x1699fa0/d; +L_0x169a080/d .functor NAND 1, L_0x1699c80, L_0x1699dc0, L_0x1699eb0, L_0x1699fa0; +L_0x169a080 .delay (10000,10000,10000) L_0x169a080/d; +v0x1658410_0 .net "S0", 0 0, L_0x16998e0; 1 drivers +v0x16584d0_0 .net "S1", 0 0, L_0x1699a10; 1 drivers +v0x1658570_0 .net "in0", 0 0, L_0x169a300; 1 drivers +v0x1658610_0 .net "in1", 0 0, L_0x169a3a0; 1 drivers +v0x1658690_0 .net "in2", 0 0, L_0x169a440; 1 drivers +v0x1658730_0 .net "in3", 0 0, L_0x169a800; 1 drivers +v0x1658810_0 .net "nS0", 0 0, L_0x1699b70; 1 drivers +v0x16588b0_0 .net "nS1", 0 0, L_0x1699c20; 1 drivers +v0x1658950_0 .net "out", 0 0, L_0x169a080; 1 drivers +v0x16589f0_0 .net "out0", 0 0, L_0x1699c80; 1 drivers +v0x1658a90_0 .net "out1", 0 0, L_0x1699dc0; 1 drivers +v0x1658b30_0 .net "out2", 0 0, L_0x1699eb0; 1 drivers +v0x1658c40_0 .net "out3", 0 0, L_0x1699fa0; 1 drivers +S_0x1657da0 .scope module, "TwoMux0case" "TwoInMux" 3 283, 3 8, S_0x15d2f60; + .timescale -9 -12; +L_0x169a590/d .functor NOT 1, L_0x169adb0, C4<0>, C4<0>, C4<0>; +L_0x169a590 .delay (10000,10000,10000) L_0x169a590/d; +L_0x169a680/d .functor AND 1, L_0x169a8f0, L_0x169a590, C4<1>, C4<1>; +L_0x169a680 .delay (20000,20000,20000) L_0x169a680/d; +L_0x169ab20/d .functor AND 1, L_0x169b090, L_0x169adb0, C4<1>, C4<1>; +L_0x169ab20 .delay (20000,20000,20000) L_0x169ab20/d; +L_0x169abd0/d .functor OR 1, L_0x169a680, L_0x169ab20, C4<0>, C4<0>; +L_0x169abd0 .delay (20000,20000,20000) L_0x169abd0/d; +v0x1657e90_0 .net "S", 0 0, L_0x169adb0; 1 drivers +v0x1657f10_0 .net "in0", 0 0, L_0x169a8f0; 1 drivers +v0x1657fb0_0 .net "in1", 0 0, L_0x169b090; 1 drivers +v0x1658050_0 .net "nS", 0 0, L_0x169a590; 1 drivers +v0x1658100_0 .net "out0", 0 0, L_0x169a680; 1 drivers +v0x16581a0_0 .net "out1", 0 0, L_0x169ab20; 1 drivers +v0x1658280_0 .net "outfinal", 0 0, L_0x169abd0; 1 drivers +S_0x1654bc0 .scope module, "zeroflagtest" "AndNand32" 3 295, 3 154, S_0x15d2f60; + .timescale -9 -12; +P_0x1653d18 .param/l "size" 3 161, +C4<0100>; +v0x1657ae0_0 .alias "A", 3 0, v0x1675890_0; +v0x1657b60_0 .alias "AndNandOut", 3 0, v0x1675a10_0; +v0x1657be0_0 .alias "B", 3 0, v0x1675890_0; +v0x1657c60_0 .net "Command", 2 0, C4<101>; 1 drivers +L_0x169b8e0 .part/pv L_0x169b6b0, 1, 1, 4; +L_0x169b980 .part RS_0x7f44879d1998, 1, 1; +L_0x169bb30 .part RS_0x7f44879d1998, 1, 1; +L_0x169c330 .part/pv L_0x169c0c0, 2, 1, 4; +L_0x169c460 .part RS_0x7f44879d1998, 2, 1; +L_0x169c500 .part RS_0x7f44879d1998, 2, 1; +L_0x169cde0 .part/pv L_0x169cb70, 3, 1, 4; +L_0x169ce80 .part RS_0x7f44879d1998, 3, 1; +L_0x169cf70 .part RS_0x7f44879d1998, 3, 1; +L_0x169d950 .part/pv L_0x169d5d0, 0, 1, 4; +L_0x169d9f0 .part RS_0x7f44879d1998, 0, 1; +L_0x169da90 .part RS_0x7f44879d1998, 0, 1; +S_0x16570e0 .scope module, "attempt2" "AndNand" 3 165, 3 48, S_0x1654bc0; + .timescale -9 -12; +L_0x169d060/d .functor NAND 1, L_0x169d9f0, L_0x169da90, C4<1>, C4<1>; +L_0x169d060 .delay (10000,10000,10000) L_0x169d060/d; +L_0x169d180/d .functor NOT 1, L_0x169d060, C4<0>, C4<0>, C4<0>; +L_0x169d180 .delay (10000,10000,10000) L_0x169d180/d; +v0x1657700_0 .net "A", 0 0, L_0x169d9f0; 1 drivers +v0x16577c0_0 .net "AandB", 0 0, L_0x169d180; 1 drivers +v0x1657840_0 .net "AnandB", 0 0, L_0x169d060; 1 drivers +v0x16578c0_0 .net "AndNandOut", 0 0, L_0x169d5d0; 1 drivers +v0x16579a0_0 .net "B", 0 0, L_0x169da90; 1 drivers +v0x1657a20_0 .alias "Command", 2 0, v0x1657c60_0; +L_0x169d7a0 .part C4<101>, 0, 1; +S_0x16571d0 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0x16570e0; + .timescale -9 -12; +L_0x169d2b0/d .functor NOT 1, L_0x169d7a0, C4<0>, C4<0>, C4<0>; +L_0x169d2b0 .delay (10000,10000,10000) L_0x169d2b0/d; +L_0x169d370/d .functor AND 1, L_0x169d180, L_0x169d2b0, C4<1>, C4<1>; +L_0x169d370 .delay (20000,20000,20000) L_0x169d370/d; +L_0x169d480/d .functor AND 1, L_0x169d060, L_0x169d7a0, C4<1>, C4<1>; +L_0x169d480 .delay (20000,20000,20000) L_0x169d480/d; +L_0x169d5d0/d .functor OR 1, L_0x169d370, L_0x169d480, C4<0>, C4<0>; +L_0x169d5d0 .delay (20000,20000,20000) L_0x169d5d0/d; +v0x16572c0_0 .net "S", 0 0, L_0x169d7a0; 1 drivers +v0x1657340_0 .alias "in0", 0 0, v0x16577c0_0; +v0x16573c0_0 .alias "in1", 0 0, v0x1657840_0; +v0x1657460_0 .net "nS", 0 0, L_0x169d2b0; 1 drivers +v0x16574e0_0 .net "out0", 0 0, L_0x169d370; 1 drivers +v0x1657580_0 .net "out1", 0 0, L_0x169d480; 1 drivers +v0x1657660_0 .alias "outfinal", 0 0, v0x16578c0_0; +S_0x1656510 .scope generate, "andbits[1]" "andbits[1]" 3 169, 3 169, S_0x1654bc0; + .timescale -9 -12; +P_0x1656608 .param/l "i" 3 169, +C4<01>; +S_0x1656680 .scope module, "attempt" "AndNand" 3 171, 3 48, S_0x1656510; + .timescale -9 -12; +L_0x1688c40/d .functor NAND 1, L_0x169b980, L_0x169bb30, C4<1>, C4<1>; +L_0x1688c40 .delay (10000,10000,10000) L_0x1688c40/d; +L_0x169aef0/d .functor NOT 1, L_0x1688c40, C4<0>, C4<0>, C4<0>; +L_0x169aef0 .delay (10000,10000,10000) L_0x169aef0/d; +v0x1656cd0_0 .net "A", 0 0, L_0x169b980; 1 drivers +v0x1656d90_0 .net "AandB", 0 0, L_0x169aef0; 1 drivers +v0x1656e10_0 .net "AnandB", 0 0, L_0x1688c40; 1 drivers +v0x1656ec0_0 .net "AndNandOut", 0 0, L_0x169b6b0; 1 drivers +v0x1656fa0_0 .net "B", 0 0, L_0x169bb30; 1 drivers +v0x1657020_0 .alias "Command", 2 0, v0x1657c60_0; +L_0x169b840 .part C4<101>, 0, 1; +S_0x1656770 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0x1656680; + .timescale -9 -12; +L_0x169afe0/d .functor NOT 1, L_0x169b840, C4<0>, C4<0>, C4<0>; +L_0x169afe0 .delay (10000,10000,10000) L_0x169afe0/d; +L_0x169b490/d .functor AND 1, L_0x169aef0, L_0x169afe0, C4<1>, C4<1>; +L_0x169b490 .delay (20000,20000,20000) L_0x169b490/d; +L_0x169b580/d .functor AND 1, L_0x1688c40, L_0x169b840, C4<1>, C4<1>; +L_0x169b580 .delay (20000,20000,20000) L_0x169b580/d; +L_0x169b6b0/d .functor OR 1, L_0x169b490, L_0x169b580, C4<0>, C4<0>; +L_0x169b6b0 .delay (20000,20000,20000) L_0x169b6b0/d; +v0x1656860_0 .net "S", 0 0, L_0x169b840; 1 drivers +v0x16568e0_0 .alias "in0", 0 0, v0x1656d90_0; +v0x1656960_0 .alias "in1", 0 0, v0x1656e10_0; +v0x1656a00_0 .net "nS", 0 0, L_0x169afe0; 1 drivers +v0x1656ab0_0 .net "out0", 0 0, L_0x169b490; 1 drivers +v0x1656b50_0 .net "out1", 0 0, L_0x169b580; 1 drivers +v0x1656c30_0 .alias "outfinal", 0 0, v0x1656ec0_0; +S_0x1655930 .scope generate, "andbits[2]" "andbits[2]" 3 169, 3 169, S_0x1654bc0; + .timescale -9 -12; +P_0x1655a28 .param/l "i" 3 169, +C4<010>; +S_0x1655aa0 .scope module, "attempt" "AndNand" 3 171, 3 48, S_0x1655930; + .timescale -9 -12; +L_0x169bbd0/d .functor NAND 1, L_0x169c460, L_0x169c500, C4<1>, C4<1>; +L_0x169bbd0 .delay (10000,10000,10000) L_0x169bbd0/d; +L_0x169bcd0/d .functor NOT 1, L_0x169bbd0, C4<0>, C4<0>, C4<0>; +L_0x169bcd0 .delay (10000,10000,10000) L_0x169bcd0/d; +v0x1656100_0 .net "A", 0 0, L_0x169c460; 1 drivers +v0x16561c0_0 .net "AandB", 0 0, L_0x169bcd0; 1 drivers +v0x1656240_0 .net "AnandB", 0 0, L_0x169bbd0; 1 drivers +v0x16562f0_0 .net "AndNandOut", 0 0, L_0x169c0c0; 1 drivers +v0x16563d0_0 .net "B", 0 0, L_0x169c500; 1 drivers +v0x1656450_0 .alias "Command", 2 0, v0x1657c60_0; +L_0x169c290 .part C4<101>, 0, 1; +S_0x1655b90 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0x1655aa0; + .timescale -9 -12; +L_0x169bdc0/d .functor NOT 1, L_0x169c290, C4<0>, C4<0>, C4<0>; +L_0x169bdc0 .delay (10000,10000,10000) L_0x169bdc0/d; +L_0x169be60/d .functor AND 1, L_0x169bcd0, L_0x169bdc0, C4<1>, C4<1>; +L_0x169be60 .delay (20000,20000,20000) L_0x169be60/d; +L_0x169bf70/d .functor AND 1, L_0x169bbd0, L_0x169c290, C4<1>, C4<1>; +L_0x169bf70 .delay (20000,20000,20000) L_0x169bf70/d; +L_0x169c0c0/d .functor OR 1, L_0x169be60, L_0x169bf70, C4<0>, C4<0>; +L_0x169c0c0 .delay (20000,20000,20000) L_0x169c0c0/d; +v0x1655c80_0 .net "S", 0 0, L_0x169c290; 1 drivers +v0x1655d20_0 .alias "in0", 0 0, v0x16561c0_0; +v0x1655dc0_0 .alias "in1", 0 0, v0x1656240_0; +v0x1655e60_0 .net "nS", 0 0, L_0x169bdc0; 1 drivers +v0x1655ee0_0 .net "out0", 0 0, L_0x169be60; 1 drivers +v0x1655f80_0 .net "out1", 0 0, L_0x169bf70; 1 drivers +v0x1656060_0 .alias "outfinal", 0 0, v0x16562f0_0; +S_0x1654d30 .scope generate, "andbits[3]" "andbits[3]" 3 169, 3 169, S_0x1654bc0; + .timescale -9 -12; +P_0x1654e28 .param/l "i" 3 169, +C4<011>; +S_0x1654ec0 .scope module, "attempt" "AndNand" 3 171, 3 48, S_0x1654d30; + .timescale -9 -12; +L_0x169c5e0/d .functor NAND 1, L_0x169ce80, L_0x169cf70, C4<1>, C4<1>; +L_0x169c5e0 .delay (10000,10000,10000) L_0x169c5e0/d; +L_0x169c720/d .functor NOT 1, L_0x169c5e0, C4<0>, C4<0>, C4<0>; +L_0x169c720 .delay (10000,10000,10000) L_0x169c720/d; +v0x1655520_0 .net "A", 0 0, L_0x169ce80; 1 drivers +v0x16555e0_0 .net "AandB", 0 0, L_0x169c720; 1 drivers +v0x1655660_0 .net "AnandB", 0 0, L_0x169c5e0; 1 drivers +v0x1655710_0 .net "AndNandOut", 0 0, L_0x169cb70; 1 drivers +v0x16557f0_0 .net "B", 0 0, L_0x169cf70; 1 drivers +v0x1655870_0 .alias "Command", 2 0, v0x1657c60_0; +L_0x169cd40 .part C4<101>, 0, 1; +S_0x1654fb0 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0x1654ec0; + .timescale -9 -12; +L_0x169c850/d .functor NOT 1, L_0x169cd40, C4<0>, C4<0>, C4<0>; +L_0x169c850 .delay (10000,10000,10000) L_0x169c850/d; +L_0x169c910/d .functor AND 1, L_0x169c720, L_0x169c850, C4<1>, C4<1>; +L_0x169c910 .delay (20000,20000,20000) L_0x169c910/d; +L_0x169ca20/d .functor AND 1, L_0x169c5e0, L_0x169cd40, C4<1>, C4<1>; +L_0x169ca20 .delay (20000,20000,20000) L_0x169ca20/d; +L_0x169cb70/d .functor OR 1, L_0x169c910, L_0x169ca20, C4<0>, C4<0>; +L_0x169cb70 .delay (20000,20000,20000) L_0x169cb70/d; +v0x16550a0_0 .net "S", 0 0, L_0x169cd40; 1 drivers +v0x1655140_0 .alias "in0", 0 0, v0x16555e0_0; +v0x16551e0_0 .alias "in1", 0 0, v0x1655660_0; +v0x1655280_0 .net "nS", 0 0, L_0x169c850; 1 drivers +v0x1655300_0 .net "out0", 0 0, L_0x169c910; 1 drivers +v0x16553a0_0 .net "out1", 0 0, L_0x169ca20; 1 drivers +v0x1655480_0 .alias "outfinal", 0 0, v0x1655710_0; +S_0x16531a0 .scope generate, "muxbits[1]" "muxbits[1]" 3 287, 3 287, S_0x15d2f60; + .timescale -9 -12; +P_0x16522f8 .param/l "i" 3 287, +C4<01>; +S_0x1654240 .scope module, "ZeroMux" "FourInMux" 3 289, 3 24, S_0x16531a0; + .timescale -9 -12; +L_0x1683e60/d .functor NOT 1, L_0x16847a0, C4<0>, C4<0>, C4<0>; +L_0x1683e60 .delay (10000,10000,10000) L_0x1683e60/d; +L_0x16840b0/d .functor NOT 1, L_0x16848d0, C4<0>, C4<0>, C4<0>; +L_0x16840b0 .delay (10000,10000,10000) L_0x16840b0/d; +L_0x1684170/d .functor NAND 1, L_0x1683e60, L_0x16840b0, L_0x1684a00, C4<1>; +L_0x1684170 .delay (10000,10000,10000) L_0x1684170/d; +L_0x1684260/d .functor NAND 1, L_0x16847a0, L_0x16840b0, L_0x1684aa0, C4<1>; +L_0x1684260 .delay (10000,10000,10000) L_0x1684260/d; +L_0x1684350/d .functor NAND 1, L_0x1683e60, L_0x16848d0, L_0x1684b40, C4<1>; +L_0x1684350 .delay (10000,10000,10000) L_0x1684350/d; +L_0x1684440/d .functor NAND 1, L_0x16847a0, L_0x16848d0, L_0x1684d40, C4<1>; +L_0x1684440 .delay (10000,10000,10000) L_0x1684440/d; +L_0x1684520/d .functor NAND 1, L_0x1684170, L_0x1684260, L_0x1684350, L_0x1684440; +L_0x1684520 .delay (10000,10000,10000) L_0x1684520/d; +v0x1654330_0 .net "S0", 0 0, L_0x16847a0; 1 drivers +v0x16543f0_0 .net "S1", 0 0, L_0x16848d0; 1 drivers +v0x1654490_0 .net "in0", 0 0, L_0x1684a00; 1 drivers +v0x1654530_0 .net "in1", 0 0, L_0x1684aa0; 1 drivers +v0x16545b0_0 .net "in2", 0 0, L_0x1684b40; 1 drivers +v0x1654650_0 .net "in3", 0 0, L_0x1684d40; 1 drivers +v0x16546f0_0 .net "nS0", 0 0, L_0x1683e60; 1 drivers +v0x1654790_0 .net "nS1", 0 0, L_0x16840b0; 1 drivers +v0x1654830_0 .net "out", 0 0, L_0x1684520; 1 drivers +v0x16548d0_0 .net "out0", 0 0, L_0x1684170; 1 drivers +v0x1654970_0 .net "out1", 0 0, L_0x1684260; 1 drivers +v0x1654a10_0 .net "out2", 0 0, L_0x1684350; 1 drivers +v0x1654b20_0 .net "out3", 0 0, L_0x1684440; 1 drivers +S_0x1653880 .scope module, "OneMux" "FourInMux" 3 290, 3 24, S_0x16531a0; + .timescale -9 -12; +L_0x1684de0/d .functor NOT 1, L_0x1685640, C4<0>, C4<0>, C4<0>; +L_0x1684de0 .delay (10000,10000,10000) L_0x1684de0/d; +L_0x1684ed0/d .functor NOT 1, L_0x1685770, C4<0>, C4<0>, C4<0>; +L_0x1684ed0 .delay (10000,10000,10000) L_0x1684ed0/d; +L_0x1684f70/d .functor NAND 1, L_0x1684de0, L_0x1684ed0, L_0x1685900, C4<1>; +L_0x1684f70 .delay (10000,10000,10000) L_0x1684f70/d; +L_0x16850b0/d .functor NAND 1, L_0x1685640, L_0x1684ed0, L_0x1685ab0, C4<1>; +L_0x16850b0 .delay (10000,10000,10000) L_0x16850b0/d; +L_0x16851a0/d .functor NAND 1, L_0x1684de0, L_0x1685770, L_0x1685b50, C4<1>; +L_0x16851a0 .delay (10000,10000,10000) L_0x16851a0/d; +L_0x1685290/d .functor NAND 1, L_0x1685640, L_0x1685770, L_0x1685bf0, C4<1>; +L_0x1685290 .delay (10000,10000,10000) L_0x1685290/d; +L_0x1685370/d .functor NAND 1, L_0x1684f70, L_0x16850b0, L_0x16851a0, L_0x1685290; +L_0x1685370 .delay (10000,10000,10000) L_0x1685370/d; +v0x1653970_0 .net "S0", 0 0, L_0x1685640; 1 drivers +v0x1653a30_0 .net "S1", 0 0, L_0x1685770; 1 drivers +v0x1653ad0_0 .net "in0", 0 0, L_0x1685900; 1 drivers +v0x1653b70_0 .net "in1", 0 0, L_0x1685ab0; 1 drivers +v0x1653bf0_0 .net "in2", 0 0, L_0x1685b50; 1 drivers +v0x1653c90_0 .net "in3", 0 0, L_0x1685bf0; 1 drivers +v0x1653d70_0 .net "nS0", 0 0, L_0x1684de0; 1 drivers +v0x1653e10_0 .net "nS1", 0 0, L_0x1684ed0; 1 drivers +v0x1653eb0_0 .net "out", 0 0, L_0x1685370; 1 drivers +v0x1653f50_0 .net "out0", 0 0, L_0x1684f70; 1 drivers +v0x1653ff0_0 .net "out1", 0 0, L_0x16850b0; 1 drivers +v0x1654090_0 .net "out2", 0 0, L_0x16851a0; 1 drivers +v0x16541a0_0 .net "out3", 0 0, L_0x1685290; 1 drivers +S_0x1653310 .scope module, "TwoMux" "TwoInMux" 3 291, 3 8, S_0x16531a0; + .timescale -9 -12; +L_0x16858a0/d .functor NOT 1, L_0x1686180, C4<0>, C4<0>, C4<0>; +L_0x16858a0 .delay (10000,10000,10000) L_0x16858a0/d; +L_0x1685d30/d .functor AND 1, L_0x1686220, L_0x16858a0, C4<1>, C4<1>; +L_0x1685d30 .delay (20000,20000,20000) L_0x1685d30/d; +L_0x1685e20/d .functor AND 1, L_0x1686310, L_0x1686180, C4<1>, C4<1>; +L_0x1685e20 .delay (20000,20000,20000) L_0x1685e20/d; +L_0x1685f10/d .functor OR 1, L_0x1685d30, L_0x1685e20, C4<0>, C4<0>; +L_0x1685f10 .delay (20000,20000,20000) L_0x1685f10/d; +v0x1653400_0 .net "S", 0 0, L_0x1686180; 1 drivers +v0x16534a0_0 .net "in0", 0 0, L_0x1686220; 1 drivers +v0x1653540_0 .net "in1", 0 0, L_0x1686310; 1 drivers +v0x16535e0_0 .net "nS", 0 0, L_0x16858a0; 1 drivers +v0x1653660_0 .net "out0", 0 0, L_0x1685d30; 1 drivers +v0x1653700_0 .net "out1", 0 0, L_0x1685e20; 1 drivers +v0x16537e0_0 .net "outfinal", 0 0, L_0x1685f10; 1 drivers +S_0x1651780 .scope generate, "muxbits[2]" "muxbits[2]" 3 287, 3 287, S_0x15d2f60; + .timescale -9 -12; +P_0x1650828 .param/l "i" 3 287, +C4<010>; +S_0x1652820 .scope module, "ZeroMux" "FourInMux" 3 289, 3 24, S_0x1651780; + .timescale -9 -12; +L_0x167d040/d .functor NOT 1, L_0x1686ca0, C4<0>, C4<0>, C4<0>; +L_0x167d040 .delay (10000,10000,10000) L_0x167d040/d; +L_0x1686580/d .functor NOT 1, L_0x1686450, C4<0>, C4<0>, C4<0>; +L_0x1686580 .delay (10000,10000,10000) L_0x1686580/d; +L_0x1686620/d .functor NAND 1, L_0x167d040, L_0x1686580, L_0x1686f10, C4<1>; +L_0x1686620 .delay (10000,10000,10000) L_0x1686620/d; +L_0x1686760/d .functor NAND 1, L_0x1686ca0, L_0x1686580, L_0x1686dd0, C4<1>; +L_0x1686760 .delay (10000,10000,10000) L_0x1686760/d; +L_0x1686850/d .functor NAND 1, L_0x167d040, L_0x1686450, L_0x1687070, C4<1>; +L_0x1686850 .delay (10000,10000,10000) L_0x1686850/d; +L_0x1686940/d .functor NAND 1, L_0x1686ca0, L_0x1686450, L_0x1686fb0, C4<1>; +L_0x1686940 .delay (10000,10000,10000) L_0x1686940/d; +L_0x1686a20/d .functor NAND 1, L_0x1686620, L_0x1686760, L_0x1686850, L_0x1686940; +L_0x1686a20 .delay (10000,10000,10000) L_0x1686a20/d; +v0x1652910_0 .net "S0", 0 0, L_0x1686ca0; 1 drivers +v0x16529d0_0 .net "S1", 0 0, L_0x1686450; 1 drivers +v0x1652a70_0 .net "in0", 0 0, L_0x1686f10; 1 drivers +v0x1652b10_0 .net "in1", 0 0, L_0x1686dd0; 1 drivers +v0x1652b90_0 .net "in2", 0 0, L_0x1687070; 1 drivers +v0x1652c30_0 .net "in3", 0 0, L_0x1686fb0; 1 drivers +v0x1652cd0_0 .net "nS0", 0 0, L_0x167d040; 1 drivers +v0x1652d70_0 .net "nS1", 0 0, L_0x1686580; 1 drivers +v0x1652e10_0 .net "out", 0 0, L_0x1686a20; 1 drivers +v0x1652eb0_0 .net "out0", 0 0, L_0x1686620; 1 drivers +v0x1652f50_0 .net "out1", 0 0, L_0x1686760; 1 drivers +v0x1652ff0_0 .net "out2", 0 0, L_0x1686850; 1 drivers +v0x1653100_0 .net "out3", 0 0, L_0x1686940; 1 drivers +S_0x1651e60 .scope module, "OneMux" "FourInMux" 3 290, 3 24, S_0x1651780; + .timescale -9 -12; +L_0x1687230/d .functor NOT 1, L_0x1687110, C4<0>, C4<0>, C4<0>; +L_0x1687230 .delay (10000,10000,10000) L_0x1687230/d; +L_0x1687320/d .functor NOT 1, L_0x1676380, C4<0>, C4<0>, C4<0>; +L_0x1687320 .delay (10000,10000,10000) L_0x1687320/d; +L_0x16873c0/d .functor NAND 1, L_0x1687230, L_0x1687320, L_0x1687aa0, C4<1>; +L_0x16873c0 .delay (10000,10000,10000) L_0x16873c0/d; +L_0x1687500/d .functor NAND 1, L_0x1687110, L_0x1687320, L_0x16765a0, C4<1>; +L_0x1687500 .delay (10000,10000,10000) L_0x1687500/d; +L_0x16875f0/d .functor NAND 1, L_0x1687230, L_0x1676380, L_0x16764b0, C4<1>; +L_0x16875f0 .delay (10000,10000,10000) L_0x16875f0/d; +L_0x16876e0/d .functor NAND 1, L_0x1687110, L_0x1676380, L_0x1688420, C4<1>; +L_0x16876e0 .delay (10000,10000,10000) L_0x16876e0/d; +L_0x16877f0/d .functor NAND 1, L_0x16873c0, L_0x1687500, L_0x16875f0, L_0x16876e0; +L_0x16877f0 .delay (10000,10000,10000) L_0x16877f0/d; +v0x1651f50_0 .net "S0", 0 0, L_0x1687110; 1 drivers +v0x1652010_0 .net "S1", 0 0, L_0x1676380; 1 drivers +v0x16520b0_0 .net "in0", 0 0, L_0x1687aa0; 1 drivers +v0x1652150_0 .net "in1", 0 0, L_0x16765a0; 1 drivers +v0x16521d0_0 .net "in2", 0 0, L_0x16764b0; 1 drivers +v0x1652270_0 .net "in3", 0 0, L_0x1688420; 1 drivers +v0x1652350_0 .net "nS0", 0 0, L_0x1687230; 1 drivers +v0x16523f0_0 .net "nS1", 0 0, L_0x1687320; 1 drivers +v0x1652490_0 .net "out", 0 0, L_0x16877f0; 1 drivers +v0x1652530_0 .net "out0", 0 0, L_0x16873c0; 1 drivers +v0x16525d0_0 .net "out1", 0 0, L_0x1687500; 1 drivers +v0x1652670_0 .net "out2", 0 0, L_0x16875f0; 1 drivers +v0x1652780_0 .net "out3", 0 0, L_0x16876e0; 1 drivers +S_0x16518f0 .scope module, "TwoMux" "TwoInMux" 3 291, 3 8, S_0x1651780; + .timescale -9 -12; +L_0x1676640/d .functor NOT 1, L_0x1688950, C4<0>, C4<0>, C4<0>; +L_0x1676640 .delay (10000,10000,10000) L_0x1676640/d; +L_0x16885d0/d .functor AND 1, L_0x16884c0, L_0x1676640, C4<1>, C4<1>; +L_0x16885d0 .delay (20000,20000,20000) L_0x16885d0/d; +L_0x1688680/d .functor AND 1, L_0x1688ba0, L_0x1688950, C4<1>, C4<1>; +L_0x1688680 .delay (20000,20000,20000) L_0x1688680/d; +L_0x1688770/d .functor OR 1, L_0x16885d0, L_0x1688680, C4<0>, C4<0>; +L_0x1688770 .delay (20000,20000,20000) L_0x1688770/d; +v0x16519e0_0 .net "S", 0 0, L_0x1688950; 1 drivers +v0x1651a80_0 .net "in0", 0 0, L_0x16884c0; 1 drivers +v0x1651b20_0 .net "in1", 0 0, L_0x1688ba0; 1 drivers +v0x1651bc0_0 .net "nS", 0 0, L_0x1676640; 1 drivers +v0x1651c40_0 .net "out0", 0 0, L_0x16885d0; 1 drivers +v0x1651ce0_0 .net "out1", 0 0, L_0x1688680; 1 drivers +v0x1651dc0_0 .net "outfinal", 0 0, L_0x1688770; 1 drivers +S_0x15d29e0 .scope generate, "muxbits[3]" "muxbits[3]" 3 287, 3 287, S_0x15d2f60; + .timescale -9 -12; +P_0x15cc7d8 .param/l "i" 3 287, +C4<011>; +S_0x1650e00 .scope module, "ZeroMux" "FourInMux" 3 289, 3 24, S_0x15d29e0; + .timescale -9 -12; +L_0x16889f0/d .functor NOT 1, L_0x16895b0, C4<0>, C4<0>, C4<0>; +L_0x16889f0 .delay (10000,10000,10000) L_0x16889f0/d; +L_0x1688a90/d .functor NOT 1, L_0x1688cd0, C4<0>, C4<0>, C4<0>; +L_0x1688a90 .delay (10000,10000,10000) L_0x1688a90/d; +L_0x1688e40/d .functor NAND 1, L_0x16889f0, L_0x1688a90, L_0x1689820, C4<1>; +L_0x1688e40 .delay (10000,10000,10000) L_0x1688e40/d; +L_0x1688f80/d .functor NAND 1, L_0x16895b0, L_0x1688a90, L_0x167bfc0, C4<1>; +L_0x1688f80 .delay (10000,10000,10000) L_0x1688f80/d; +L_0x1689070/d .functor NAND 1, L_0x16889f0, L_0x1688cd0, L_0x16896e0, C4<1>; +L_0x1689070 .delay (10000,10000,10000) L_0x1689070/d; +L_0x1689190/d .functor NAND 1, L_0x16895b0, L_0x1688cd0, L_0x1689c30, C4<1>; +L_0x1689190 .delay (10000,10000,10000) L_0x1689190/d; +L_0x1689300/d .functor NAND 1, L_0x1688e40, L_0x1688f80, L_0x1689070, L_0x1689190; +L_0x1689300 .delay (10000,10000,10000) L_0x1689300/d; +v0x1650ef0_0 .net "S0", 0 0, L_0x16895b0; 1 drivers +v0x1650fb0_0 .net "S1", 0 0, L_0x1688cd0; 1 drivers +v0x1651050_0 .net "in0", 0 0, L_0x1689820; 1 drivers +v0x16510f0_0 .net "in1", 0 0, L_0x167bfc0; 1 drivers +v0x1651170_0 .net "in2", 0 0, L_0x16896e0; 1 drivers +v0x1651210_0 .net "in3", 0 0, L_0x1689c30; 1 drivers +v0x16512b0_0 .net "nS0", 0 0, L_0x16889f0; 1 drivers +v0x1651350_0 .net "nS1", 0 0, L_0x1688a90; 1 drivers +v0x16513f0_0 .net "out", 0 0, L_0x1689300; 1 drivers +v0x1651490_0 .net "out0", 0 0, L_0x1688e40; 1 drivers +v0x1651530_0 .net "out1", 0 0, L_0x1688f80; 1 drivers +v0x16515d0_0 .net "out2", 0 0, L_0x1689070; 1 drivers +v0x16516e0_0 .net "out3", 0 0, L_0x1689190; 1 drivers +S_0x1650390 .scope module, "OneMux" "FourInMux" 3 290, 3 24, S_0x15d29e0; + .timescale -9 -12; +L_0x167c060/d .functor NOT 1, L_0x1689ad0, C4<0>, C4<0>, C4<0>; +L_0x167c060 .delay (10000,10000,10000) L_0x167c060/d; +L_0x1689d60/d .functor NOT 1, L_0x168a6e0, C4<0>, C4<0>, C4<0>; +L_0x1689d60 .delay (10000,10000,10000) L_0x1689d60/d; +L_0x1689e00/d .functor NAND 1, L_0x167c060, L_0x1689d60, L_0x168a570, C4<1>; +L_0x1689e00 .delay (10000,10000,10000) L_0x1689e00/d; +L_0x1689f40/d .functor NAND 1, L_0x1689ad0, L_0x1689d60, L_0x168a610, C4<1>; +L_0x1689f40 .delay (10000,10000,10000) L_0x1689f40/d; +L_0x168a030/d .functor NAND 1, L_0x167c060, L_0x168a6e0, L_0x168a9a0, C4<1>; +L_0x168a030 .delay (10000,10000,10000) L_0x168a030/d; +L_0x168a150/d .functor NAND 1, L_0x1689ad0, L_0x168a6e0, L_0x168aa90, C4<1>; +L_0x168a150 .delay (10000,10000,10000) L_0x168a150/d; +L_0x168a2c0/d .functor NAND 1, L_0x1689e00, L_0x1689f40, L_0x168a030, L_0x168a150; +L_0x168a2c0 .delay (10000,10000,10000) L_0x168a2c0/d; +v0x1650480_0 .net "S0", 0 0, L_0x1689ad0; 1 drivers +v0x1650540_0 .net "S1", 0 0, L_0x168a6e0; 1 drivers +v0x16505e0_0 .net "in0", 0 0, L_0x168a570; 1 drivers +v0x1650680_0 .net "in1", 0 0, L_0x168a610; 1 drivers +v0x1650700_0 .net "in2", 0 0, L_0x168a9a0; 1 drivers +v0x16507a0_0 .net "in3", 0 0, L_0x168aa90; 1 drivers +v0x1650880_0 .net "nS0", 0 0, L_0x167c060; 1 drivers +v0x1650920_0 .net "nS1", 0 0, L_0x1689d60; 1 drivers +v0x1650a10_0 .net "out", 0 0, L_0x168a2c0; 1 drivers +v0x1650ab0_0 .net "out0", 0 0, L_0x1689e00; 1 drivers +v0x1650bb0_0 .net "out1", 0 0, L_0x1689f40; 1 drivers +v0x1650c50_0 .net "out2", 0 0, L_0x168a030; 1 drivers +v0x1650d60_0 .net "out3", 0 0, L_0x168a150; 1 drivers +S_0x15d2360 .scope module, "TwoMux" "TwoInMux" 3 291, 3 8, S_0x15d29e0; + .timescale -9 -12; +L_0x1684c30/d .functor NOT 1, L_0x168b160, C4<0>, C4<0>, C4<0>; +L_0x1684c30 .delay (10000,10000,10000) L_0x1684c30/d; +L_0x168a810/d .functor AND 1, L_0x168ad90, L_0x1684c30, C4<1>, C4<1>; +L_0x168a810 .delay (20000,20000,20000) L_0x168a810/d; +L_0x168a900/d .functor AND 1, L_0x168ae80, L_0x168b160, C4<1>, C4<1>; +L_0x168a900 .delay (20000,20000,20000) L_0x168a900/d; +L_0x168af80/d .functor OR 1, L_0x168a810, L_0x168a900, C4<0>, C4<0>; +L_0x168af80 .delay (20000,20000,20000) L_0x168af80/d; +v0x15987d0_0 .net "S", 0 0, L_0x168b160; 1 drivers +v0x164ff80_0 .net "in0", 0 0, L_0x168ad90; 1 drivers +v0x1650020_0 .net "in1", 0 0, L_0x168ae80; 1 drivers +v0x16500c0_0 .net "nS", 0 0, L_0x1684c30; 1 drivers +v0x1650170_0 .net "out0", 0 0, L_0x168a810; 1 drivers +v0x1650210_0 .net "out1", 0 0, L_0x168a900; 1 drivers +v0x16502f0_0 .net "outfinal", 0 0, L_0x168af80; 1 drivers + .scope S_0x1615180; T_0 ; - %vpi_call 3 35 "$display", "Test ALU - Add"; - %vpi_call 3 36 "$display", " A | B |Command|Output | ExpectOut|Cout|OF|subtract|SLTflag"; - %movi 8, 8, 4; - %set/v v0x17dd890_0, 8, 4; + %vpi_call 2 166 "$display", "Test 4 Bit Adder Functionality"; + %vpi_call 2 168 "$display", " A | B |Command| Out|ExpectedOut|Cout|OF"; + %movi 8, 2, 4; + %set/v v0x1675610_0, 8, 4; + %movi 8, 4, 4; + %set/v v0x1675790_0, 8, 4; + %set/v v0x1675810_0, 0, 3; + %delay 1000000, 0; + %vpi_call 2 172 "$display", "%b | %b | %b | %b | Expect 0110| %b | %b ", v0x1675610_0, v0x1675790_0, v0x1675810_0, v0x1675690_0, v0x1675b60_0, v0x1675be0_0; %movi 8, 1, 4; - %set/v v0x17dda10_0, 8, 4; - %set/v v0x17dda90_0, 0, 3; + %set/v v0x1675610_0, 8, 4; + %movi 8, 6, 4; + %set/v v0x1675790_0, 8, 4; + %set/v v0x1675810_0, 0, 3; + %delay 1000000, 0; + %vpi_call 2 176 "$display", "%b | %b | %b | %b | Expect 0111| %b | %b ", v0x1675610_0, v0x1675790_0, v0x1675810_0, v0x1675690_0, v0x1675b60_0, v0x1675be0_0; + %movi 8, 5, 4; + %set/v v0x1675610_0, 8, 4; + %movi 8, 13, 4; + %set/v v0x1675790_0, 8, 4; + %set/v v0x1675810_0, 0, 3; + %delay 1000000, 0; + %vpi_call 2 180 "$display", "%b | %b | %b | %b | Expect 0010| %b | %b ", v0x1675610_0, v0x1675790_0, v0x1675810_0, v0x1675690_0, v0x1675b60_0, v0x1675be0_0; + %movi 8, 2, 4; + %set/v v0x1675610_0, 8, 4; + %set/v v0x1675790_0, 1, 4; + %set/v v0x1675810_0, 0, 3; %delay 1000000, 0; - %vpi_call 3 38 "$display", "%b | %b | %b | %b | Expect 1001| %b | %b ", v0x17dd890_0, v0x17dda10_0, v0x17dda90_0, v0x17dd910_0, v0x17ddd10_0, v0x17ddd90_0; - %vpi_call 3 40 "$display", " A | B |Command|Output | ExpectOut|Cout|OF|subtract|SLTflag"; + %vpi_call 2 184 "$display", "%b | %b | %b | %b | Expect 0001| %b | %b ", v0x1675610_0, v0x1675790_0, v0x1675810_0, v0x1675690_0, v0x1675b60_0, v0x1675be0_0; %movi 8, 8, 4; - %set/v v0x17dd890_0, 8, 4; - %movi 8, 1, 4; - %set/v v0x17dda10_0, 8, 4; - %set/v v0x17dda90_0, 0, 3; + %set/v v0x1675610_0, 8, 4; + %movi 8, 3, 4; + %set/v v0x1675790_0, 8, 4; + %set/v v0x1675810_0, 0, 3; + %delay 1000000, 0; + %vpi_call 2 188 "$display", "%b | %b | %b | %b | Expect 1011| %b | %b ", v0x1675610_0, v0x1675790_0, v0x1675810_0, v0x1675690_0, v0x1675b60_0, v0x1675be0_0; + %movi 8, 12, 4; + %set/v v0x1675610_0, 8, 4; + %movi 8, 2, 4; + %set/v v0x1675790_0, 8, 4; + %set/v v0x1675810_0, 0, 3; + %delay 1000000, 0; + %vpi_call 2 192 "$display", "%b | %b | %b | %b | Expect 1110| %b | %b ", v0x1675610_0, v0x1675790_0, v0x1675810_0, v0x1675690_0, v0x1675b60_0, v0x1675be0_0; + %movi 8, 11, 4; + %set/v v0x1675610_0, 8, 4; + %movi 8, 5, 4; + %set/v v0x1675790_0, 8, 4; + %set/v v0x1675810_0, 0, 3; + %delay 1000000, 0; + %vpi_call 2 196 "$display", "%b | %b | %b | %b | Expect 0110| %b | %b ", v0x1675610_0, v0x1675790_0, v0x1675810_0, v0x1675690_0, v0x1675b60_0, v0x1675be0_0; + %movi 8, 7, 4; + %set/v v0x1675610_0, 8, 4; + %movi 8, 9, 4; + %set/v v0x1675790_0, 8, 4; + %set/v v0x1675810_0, 0, 3; + %delay 1000000, 0; + %vpi_call 2 200 "$display", "%b | %b | %b | %b | Expect 0000| %b | %b ", v0x1675610_0, v0x1675790_0, v0x1675810_0, v0x1675690_0, v0x1675b60_0, v0x1675be0_0; + %movi 8, 13, 4; + %set/v v0x1675610_0, 8, 4; + %movi 8, 12, 4; + %set/v v0x1675790_0, 8, 4; + %set/v v0x1675810_0, 0, 3; + %delay 1000000, 0; + %vpi_call 2 204 "$display", "%b | %b | %b | %b | Expect 1001| %b | %b ", v0x1675610_0, v0x1675790_0, v0x1675810_0, v0x1675690_0, v0x1675b60_0, v0x1675be0_0; + %movi 8, 14, 4; + %set/v v0x1675610_0, 8, 4; + %movi 8, 10, 4; + %set/v v0x1675790_0, 8, 4; + %set/v v0x1675810_0, 0, 3; + %delay 1000000, 0; + %vpi_call 2 208 "$display", "%b | %b | %b | %b | Expect 1000| %b | %b ", v0x1675610_0, v0x1675790_0, v0x1675810_0, v0x1675690_0, v0x1675b60_0, v0x1675be0_0; + %movi 8, 5, 4; + %set/v v0x1675610_0, 8, 4; + %movi 8, 6, 4; + %set/v v0x1675790_0, 8, 4; + %set/v v0x1675810_0, 0, 3; + %delay 1000000, 0; + %vpi_call 2 212 "$display", "%b | %b | %b | %b | Expect XXXX| %b | %b ", v0x1675610_0, v0x1675790_0, v0x1675810_0, v0x1675690_0, v0x1675b60_0, v0x1675be0_0; + %movi 8, 2, 4; + %set/v v0x1675610_0, 8, 4; + %movi 8, 7, 4; + %set/v v0x1675790_0, 8, 4; + %set/v v0x1675810_0, 0, 3; + %delay 1000000, 0; + %vpi_call 2 216 "$display", "%b | %b | %b | %b | Expect XXXX| %b | %b ", v0x1675610_0, v0x1675790_0, v0x1675810_0, v0x1675690_0, v0x1675b60_0, v0x1675be0_0; + %movi 8, 7, 4; + %set/v v0x1675610_0, 8, 4; + %movi 8, 7, 4; + %set/v v0x1675790_0, 8, 4; + %set/v v0x1675810_0, 0, 3; + %delay 1000000, 0; + %vpi_call 2 220 "$display", "%b | %b | %b | %b | Expect XXXX| %b | %b ", v0x1675610_0, v0x1675790_0, v0x1675810_0, v0x1675690_0, v0x1675b60_0, v0x1675be0_0; + %movi 8, 8, 4; + %set/v v0x1675610_0, 8, 4; + %set/v v0x1675790_0, 1, 4; + %set/v v0x1675810_0, 0, 3; + %delay 1000000, 0; + %vpi_call 2 224 "$display", "%b | %b | %b | %b | Expect XXXX| %b | %b ", v0x1675610_0, v0x1675790_0, v0x1675810_0, v0x1675690_0, v0x1675b60_0, v0x1675be0_0; + %movi 8, 8, 4; + %set/v v0x1675610_0, 8, 4; + %movi 8, 13, 4; + %set/v v0x1675790_0, 8, 4; + %set/v v0x1675810_0, 0, 3; + %delay 1000000, 0; + %vpi_call 2 228 "$display", "%b | %b | %b | %b | Expect XXXX| %b | %b ", v0x1675610_0, v0x1675790_0, v0x1675810_0, v0x1675690_0, v0x1675b60_0, v0x1675be0_0; + %movi 8, 11, 4; + %set/v v0x1675610_0, 8, 4; + %movi 8, 12, 4; + %set/v v0x1675790_0, 8, 4; + %set/v v0x1675810_0, 0, 3; + %delay 1000000, 0; + %vpi_call 2 232 "$display", "%b | %b | %b | %b | Expect XXXX| %b | %b ", v0x1675610_0, v0x1675790_0, v0x1675810_0, v0x1675690_0, v0x1675b60_0, v0x1675be0_0; + %vpi_call 2 234 "$display", "Test 4 Bit SLT Functionality"; + %vpi_call 2 236 "$display", " A | B |Command| Out|ExpectedOut|Cout|OF |SLTflag"; + %movi 8, 2, 4; + %set/v v0x1675610_0, 8, 4; + %movi 8, 4, 4; + %set/v v0x1675790_0, 8, 4; + %movi 8, 3, 3; + %set/v v0x1675810_0, 8, 3; + %delay 1000000, 0; + %vpi_call 2 240 "$display", "%b | %b | %b | %b | Expect 1110| %b | %b | %b", v0x1675610_0, v0x1675790_0, v0x1675810_0, v0x1675690_0, v0x1675b60_0, v0x1675be0_0, v0x1675990_0; + %movi 8, 4, 4; + %set/v v0x1675610_0, 8, 4; + %movi 8, 2, 4; + %set/v v0x1675790_0, 8, 4; + %movi 8, 3, 3; + %set/v v0x1675810_0, 8, 3; + %delay 1000000, 0; + %vpi_call 2 244 "$display", "%b | %b | %b | %b | Expect 0010| %b | %b | %b", v0x1675610_0, v0x1675790_0, v0x1675810_0, v0x1675690_0, v0x1675b60_0, v0x1675be0_0, v0x1675990_0; + %movi 8, 14, 4; + %set/v v0x1675610_0, 8, 4; + %movi 8, 4, 4; + %set/v v0x1675790_0, 8, 4; + %movi 8, 3, 3; + %set/v v0x1675810_0, 8, 3; + %delay 1000000, 0; + %vpi_call 2 248 "$display", "%b | %b | %b | %b | Expect 1010| %b | %b | %b", v0x1675610_0, v0x1675790_0, v0x1675810_0, v0x1675690_0, v0x1675b60_0, v0x1675be0_0, v0x1675990_0; + %movi 8, 4, 4; + %set/v v0x1675610_0, 8, 4; + %movi 8, 14, 4; + %set/v v0x1675790_0, 8, 4; + %movi 8, 3, 3; + %set/v v0x1675810_0, 8, 3; + %delay 1000000, 0; + %vpi_call 2 252 "$display", "%b | %b | %b | %b | Expect 0110| %b | %b | %b", v0x1675610_0, v0x1675790_0, v0x1675810_0, v0x1675690_0, v0x1675b60_0, v0x1675be0_0, v0x1675990_0; + %movi 8, 14, 4; + %set/v v0x1675610_0, 8, 4; + %set/v v0x1675790_0, 1, 4; + %movi 8, 3, 3; + %set/v v0x1675810_0, 8, 3; + %delay 1000000, 0; + %vpi_call 2 256 "$display", "%b | %b | %b | %b | Expect 1111| %b | %b | %b", v0x1675610_0, v0x1675790_0, v0x1675810_0, v0x1675690_0, v0x1675b60_0, v0x1675be0_0, v0x1675990_0; + %set/v v0x1675610_0, 1, 4; + %movi 8, 14, 4; + %set/v v0x1675790_0, 8, 4; + %movi 8, 3, 3; + %set/v v0x1675810_0, 8, 3; + %delay 1000000, 0; + %vpi_call 2 260 "$display", "%b | %b | %b | %b | Expect 0001| %b | %b | %b", v0x1675610_0, v0x1675790_0, v0x1675810_0, v0x1675690_0, v0x1675b60_0, v0x1675be0_0, v0x1675990_0; + %movi 8, 13, 4; + %set/v v0x1675610_0, 8, 4; + %movi 8, 13, 4; + %set/v v0x1675790_0, 8, 4; + %movi 8, 3, 3; + %set/v v0x1675810_0, 8, 3; + %delay 1000000, 0; + %vpi_call 2 264 "$display", "%b | %b | %b | %b | Expect 0000| %b | %b | %b", v0x1675610_0, v0x1675790_0, v0x1675810_0, v0x1675690_0, v0x1675b60_0, v0x1675be0_0, v0x1675990_0; + %movi 8, 5, 4; + %set/v v0x1675610_0, 8, 4; + %movi 8, 5, 4; + %set/v v0x1675790_0, 8, 4; + %movi 8, 3, 3; + %set/v v0x1675810_0, 8, 3; + %delay 1000000, 0; + %vpi_call 2 268 "$display", "%b | %b | %b | %b | Expect 0000| %b | %b | %b", v0x1675610_0, v0x1675790_0, v0x1675810_0, v0x1675690_0, v0x1675b60_0, v0x1675be0_0, v0x1675990_0; + %movi 8, 9, 4; + %set/v v0x1675610_0, 8, 4; + %movi 8, 5, 4; + %set/v v0x1675790_0, 8, 4; + %movi 8, 3, 3; + %set/v v0x1675810_0, 8, 3; + %delay 1000000, 0; + %vpi_call 2 272 "$display", "%b | %b | %b | %b | Expect XXXX| %b | %b | %b", v0x1675610_0, v0x1675790_0, v0x1675810_0, v0x1675690_0, v0x1675b60_0, v0x1675be0_0, v0x1675990_0; + %vpi_call 2 274 "$display", "Test 4 Bit AND/NAND Functionality"; + %vpi_call 2 276 "$display", " A | B |Command| Out |ExpectedOut-AND"; + %set/v v0x1675610_0, 1, 4; + %set/v v0x1675790_0, 1, 4; + %movi 8, 4, 3; + %set/v v0x1675810_0, 8, 3; + %delay 1000000, 0; + %vpi_call 2 280 "$display", "%b | %b | %b | %b | 1111", v0x1675610_0, v0x1675790_0, v0x1675810_0, v0x1675710_0; + %set/v v0x1675610_0, 1, 4; + %movi 8, 10, 4; + %set/v v0x1675790_0, 8, 4; + %movi 8, 4, 3; + %set/v v0x1675810_0, 8, 3; %delay 1000000, 0; - %vpi_call 3 42 "$display", "%b | %b | %b | %b | Expect 1001| %b | %b ", v0x17dd890_0, v0x17dda10_0, v0x17dda90_0, v0x17ddb10_0, v0x17ddd10_0, v0x17ddd90_0; + %vpi_call 2 284 "$display", "%b | %b | %b | %b | 1010", v0x1675610_0, v0x1675790_0, v0x1675810_0, v0x1675710_0; + %set/v v0x1675610_0, 1, 4; + %movi 8, 5, 4; + %set/v v0x1675790_0, 8, 4; + %movi 8, 4, 3; + %set/v v0x1675810_0, 8, 3; + %delay 1000000, 0; + %vpi_call 2 288 "$display", "%b | %b | %b | %b | 0101", v0x1675610_0, v0x1675790_0, v0x1675810_0, v0x1675710_0; + %set/v v0x1675610_0, 1, 4; + %set/v v0x1675790_0, 0, 4; + %movi 8, 4, 3; + %set/v v0x1675810_0, 8, 3; + %delay 1000000, 0; + %vpi_call 2 292 "$display", "%b | %b | %b | %b | 0000", v0x1675610_0, v0x1675790_0, v0x1675810_0, v0x1675710_0; + %vpi_call 2 295 "$display", " A | B |Command| Out |ExpectedOut-NAND"; + %set/v v0x1675610_0, 1, 4; + %set/v v0x1675790_0, 1, 4; + %movi 8, 5, 3; + %set/v v0x1675810_0, 8, 3; + %delay 1000000, 0; + %vpi_call 2 299 "$display", "%b | %b | %b | %b | 0000", v0x1675610_0, v0x1675790_0, v0x1675810_0, v0x1675710_0; + %set/v v0x1675610_0, 1, 4; + %movi 8, 10, 4; + %set/v v0x1675790_0, 8, 4; + %movi 8, 5, 3; + %set/v v0x1675810_0, 8, 3; + %delay 1000000, 0; + %vpi_call 2 303 "$display", "%b | %b | %b | %b | 0101", v0x1675610_0, v0x1675790_0, v0x1675810_0, v0x1675710_0; + %set/v v0x1675610_0, 1, 4; + %movi 8, 5, 4; + %set/v v0x1675790_0, 8, 4; + %movi 8, 5, 3; + %set/v v0x1675810_0, 8, 3; + %delay 1000000, 0; + %vpi_call 2 307 "$display", "%b | %b | %b | %b | 1010", v0x1675610_0, v0x1675790_0, v0x1675810_0, v0x1675710_0; + %set/v v0x1675610_0, 1, 4; + %set/v v0x1675790_0, 0, 4; + %movi 8, 5, 3; + %set/v v0x1675810_0, 8, 3; + %delay 1000000, 0; + %vpi_call 2 311 "$display", "%b | %b | %b | %b | 1111", v0x1675610_0, v0x1675790_0, v0x1675810_0, v0x1675710_0; + %vpi_call 2 313 "$display", "Test 4 Bit OR/NOR/XOR Functionality"; + %vpi_call 2 315 "$display", " A | B |Command | Out |ExpectedOut-OR"; + %movi 8, 10, 4; + %set/v v0x1675610_0, 8, 4; + %movi 8, 5, 4; + %set/v v0x1675790_0, 8, 4; + %set/v v0x1675810_0, 1, 3; + %delay 1000000, 0; + %vpi_call 2 319 "$display", "%b | %b | %b | %b | 1111", v0x1675610_0, v0x1675790_0, v0x1675810_0, v0x1675910_0; + %set/v v0x1675610_0, 1, 4; + %movi 8, 5, 4; + %set/v v0x1675790_0, 8, 4; + %set/v v0x1675810_0, 1, 3; + %delay 1000000, 0; + %vpi_call 2 323 "$display", "%b | %b | %b | %b | 1111", v0x1675610_0, v0x1675790_0, v0x1675810_0, v0x1675910_0; + %movi 8, 11, 4; + %set/v v0x1675610_0, 8, 4; + %set/v v0x1675790_0, 0, 4; + %set/v v0x1675810_0, 1, 3; + %delay 1000000, 0; + %vpi_call 2 327 "$display", "%b | %b | %b | %b | 1011", v0x1675610_0, v0x1675790_0, v0x1675810_0, v0x1675910_0; + %vpi_call 2 329 "$display", " A | B |Command | Out |ExpectedOut-NOR"; + %movi 8, 10, 4; + %set/v v0x1675610_0, 8, 4; + %movi 8, 5, 4; + %set/v v0x1675790_0, 8, 4; + %movi 8, 6, 3; + %set/v v0x1675810_0, 8, 3; + %delay 1000000, 0; + %vpi_call 2 333 "$display", "%b | %b | %b | %b | 0000", v0x1675610_0, v0x1675790_0, v0x1675810_0, v0x1675910_0; + %set/v v0x1675610_0, 1, 4; + %movi 8, 5, 4; + %set/v v0x1675790_0, 8, 4; + %movi 8, 6, 3; + %set/v v0x1675810_0, 8, 3; + %delay 1000000, 0; + %vpi_call 2 337 "$display", "%b | %b | %b | %b | 0000", v0x1675610_0, v0x1675790_0, v0x1675810_0, v0x1675910_0; + %movi 8, 11, 4; + %set/v v0x1675610_0, 8, 4; + %set/v v0x1675790_0, 0, 4; + %movi 8, 6, 3; + %set/v v0x1675810_0, 8, 3; + %delay 1000000, 0; + %vpi_call 2 341 "$display", "%b | %b | %b | %b | 0100", v0x1675610_0, v0x1675790_0, v0x1675810_0, v0x1675910_0; + %vpi_call 2 343 "$display", " A | B |Command | Out |ExpectedOut-XOR"; + %movi 8, 10, 4; + %set/v v0x1675610_0, 8, 4; + %movi 8, 5, 4; + %set/v v0x1675790_0, 8, 4; + %movi 8, 2, 3; + %set/v v0x1675810_0, 8, 3; + %delay 1000000, 0; + %vpi_call 2 347 "$display", "%b | %b | %b | %b | 1111", v0x1675610_0, v0x1675790_0, v0x1675810_0, v0x1675910_0; + %set/v v0x1675610_0, 1, 4; + %movi 8, 5, 4; + %set/v v0x1675790_0, 8, 4; + %movi 8, 2, 3; + %set/v v0x1675810_0, 8, 3; + %delay 1000000, 0; + %vpi_call 2 351 "$display", "%b | %b | %b | %b | 1010", v0x1675610_0, v0x1675790_0, v0x1675810_0, v0x1675910_0; + %movi 8, 11, 4; + %set/v v0x1675610_0, 8, 4; + %set/v v0x1675790_0, 0, 4; + %movi 8, 2, 3; + %set/v v0x1675810_0, 8, 3; + %delay 1000000, 0; + %vpi_call 2 355 "$display", "%b | %b | %b | %b | 1011", v0x1675610_0, v0x1675790_0, v0x1675810_0, v0x1675910_0; + %vpi_call 2 357 "$display", "Test 4 Bit ALU Functionality"; + %vpi_call 2 359 "$display", " A | B |Command | Out |ExpectedOut | COut | OF |SLT|Zero"; + %set/v v0x1675610_0, 1, 4; + %set/v v0x1675790_0, 1, 4; + %movi 8, 4, 3; + %set/v v0x1675810_0, 8, 3; + %delay 1000000, 0; + %vpi_call 2 364 "$display", "%b | %b | %b - AND | %b | 1111 | %b | %b | %b | %b", v0x1675610_0, v0x1675790_0, v0x1675810_0, v0x1675890_0, v0x1675b60_0, v0x1675be0_0, v0x1675990_0, v0x1675a10_0; + %set/v v0x1675610_0, 1, 4; + %set/v v0x1675790_0, 0, 4; + %movi 8, 5, 3; + %set/v v0x1675810_0, 8, 3; + %delay 1000000, 0; + %vpi_call 2 369 "$display", "%b | %b | %b - NAND | %b | 1111 | %b | %b | %b | %b", v0x1675610_0, v0x1675790_0, v0x1675810_0, v0x1675890_0, v0x1675b60_0, v0x1675be0_0, v0x1675990_0, v0x1675a10_0; + %set/v v0x1675610_0, 1, 4; + %movi 8, 5, 4; + %set/v v0x1675790_0, 8, 4; + %set/v v0x1675810_0, 1, 3; + %delay 1000000, 0; + %vpi_call 2 374 "$display", "%b | %b | %b - OR | %b | 1111 | %b | %b | %b | %b", v0x1675610_0, v0x1675790_0, v0x1675810_0, v0x1675890_0, v0x1675b60_0, v0x1675be0_0, v0x1675990_0, v0x1675a10_0; + %movi 8, 11, 4; + %set/v v0x1675610_0, 8, 4; + %set/v v0x1675790_0, 0, 4; + %movi 8, 6, 3; + %set/v v0x1675810_0, 8, 3; + %delay 1000000, 0; + %vpi_call 2 379 "$display", "%b | %b | %b - NOR | %b | 0100 | %b | %b | %b | %b", v0x1675610_0, v0x1675790_0, v0x1675810_0, v0x1675890_0, v0x1675b60_0, v0x1675be0_0, v0x1675990_0, v0x1675a10_0; + %movi 8, 11, 4; + %set/v v0x1675610_0, 8, 4; + %set/v v0x1675790_0, 0, 4; + %movi 8, 2, 3; + %set/v v0x1675810_0, 8, 3; + %delay 1000000, 0; + %vpi_call 2 384 "$display", "%b | %b | %b - XOR | %b | 1011 | %b | %b | %b | %b", v0x1675610_0, v0x1675790_0, v0x1675810_0, v0x1675890_0, v0x1675b60_0, v0x1675be0_0, v0x1675990_0, v0x1675a10_0; + %movi 8, 2, 4; + %set/v v0x1675610_0, 8, 4; + %movi 8, 4, 4; + %set/v v0x1675790_0, 8, 4; + %set/v v0x1675810_0, 0, 3; + %delay 1000000, 0; + %vpi_call 2 389 "$display", "%b | %b | %b - ADD | %b | 0110 | %b | %b | %b | %b", v0x1675610_0, v0x1675790_0, v0x1675810_0, v0x1675890_0, v0x1675b60_0, v0x1675be0_0, v0x1675990_0, v0x1675a10_0; + %movi 8, 11, 4; + %set/v v0x1675610_0, 8, 4; + %movi 8, 12, 4; + %set/v v0x1675790_0, 8, 4; + %set/v v0x1675810_0, 0, 3; + %delay 1000000, 0; + %vpi_call 2 393 "$display", "%b | %b | %b - ADD | %b | XXXX | %b | %b | %b | %b", v0x1675610_0, v0x1675790_0, v0x1675810_0, v0x1675890_0, v0x1675b60_0, v0x1675be0_0, v0x1675990_0, v0x1675a10_0; + %movi 8, 2, 4; + %set/v v0x1675610_0, 8, 4; + %movi 8, 4, 4; + %set/v v0x1675790_0, 8, 4; + %movi 8, 1, 3; + %set/v v0x1675810_0, 8, 3; + %delay 1000000, 0; + %vpi_call 2 398 "$display", "%b | %b | %b - SUB | %b | 1110 | %b | %b | %b | %b", v0x1675610_0, v0x1675790_0, v0x1675810_0, v0x1675890_0, v0x1675b60_0, v0x1675be0_0, v0x1675990_0, v0x1675a10_0; + %movi 8, 9, 4; + %set/v v0x1675610_0, 8, 4; + %movi 8, 3, 4; + %set/v v0x1675790_0, 8, 4; + %movi 8, 1, 3; + %set/v v0x1675810_0, 8, 3; + %delay 1000000, 0; + %vpi_call 2 402 "$display", "%b | %b | %b - SUB | %b | XXXX | %b | %b | %b | %b", v0x1675610_0, v0x1675790_0, v0x1675810_0, v0x1675890_0, v0x1675b60_0, v0x1675be0_0, v0x1675990_0, v0x1675a10_0; + %movi 8, 4, 4; + %set/v v0x1675610_0, 8, 4; + %movi 8, 2, 4; + %set/v v0x1675790_0, 8, 4; + %movi 8, 3, 3; + %set/v v0x1675810_0, 8, 3; + %delay 1000000, 0; + %vpi_call 2 408 "$display", "%b | %b | %b - SLT | %b | 0010 | %b | %b | %b | %b", v0x1675610_0, v0x1675790_0, v0x1675810_0, v0x1675890_0, v0x1675b60_0, v0x1675be0_0, v0x1675990_0, v0x1675a10_0; + %movi 8, 9, 4; + %set/v v0x1675610_0, 8, 4; + %movi 8, 5, 4; + %set/v v0x1675790_0, 8, 4; + %movi 8, 3, 3; + %set/v v0x1675810_0, 8, 3; + %delay 1000000, 0; + %vpi_call 2 412 "$display", "%b | %b | %b - SLT | %b | XXXX | %b | %b | %b | %b", v0x1675610_0, v0x1675790_0, v0x1675810_0, v0x1675890_0, v0x1675b60_0, v0x1675be0_0, v0x1675990_0, v0x1675a10_0; %end; .thread T_0; # The file index is used to find the file name in the following table. :file_names 4; "N/A"; ""; - "./alu2.v"; "testing.t.v"; + "./alu2.v"; diff --git a/testing.t.v b/testing.t.v index ab5be1b..c1f03e1 100644 --- a/testing.t.v +++ b/testing.t.v @@ -2,6 +2,136 @@ `timescale 1 ns / 1 ps `include "alu2.v" +/* +module testBasicFunctions(); +// we begin by testing the basic AND/NAND, OR/NOR/XOR, and ADD/SUB/SLT modules + +wire AndNandOut; +reg A, B; +reg[2:0] Command; +//reg S; +wire OneBitFinalOut; +wire AddSubSLTSum, carryout, subtract; //overflow - we don't calculate overflow except with the most significant bit, so we don't worry about it here +reg carryin; +wire OrNorXorOut; +reg S0, S1; +reg in0, in1, in2, in3; +wire muxout; + +// test mux functionality: + FourInMux testmux(muxout, S0, S1, in0, in1, in2, in3); +// test ADD/SUB/SLT + MiddleAddSubSLT testadd(AddSubSLTSum, carryout, subtract, A, B, Command, carryin); +// test AND/NAND + AndNand testand(AndNandOut, A, B, Command); +// test OR/NOR/XOR + OrNorXor testor(OrNorXorOut, A, B, Command); + +initial begin +// test mux + $display("Four Input Multiplexer"); + $display("S0 S1 |in0 in1 in2 in3| Output"); + S0 = 0; S1 = 0; in0 = 1'bx; in1 = 0; in2 = 0; in3 = 0; #1000 + $display(" %b %b | %b %b %b %b | %b", S0, S1, in0, in1, in2, in3, muxout); + S0 = 1; S1 = 0; in0 = 0; in1 = 1'bx; in2 = 0; in3 = 0; #1000 + $display(" %b %b | %b %b %b %b | %b", S0, S1, in0, in1, in2, in3, muxout); + S0 = 0; S1 = 1; in0 = 0; in1 = 0; in2 = 1'bx; in3 = 0; #1000 + $display(" %b %b | %b %b %b %b | %b", S0, S1, in0, in1, in2, in3, muxout); + S0 = 1; S1 = 1; in0 = 0; in1 = 0; in2 = 0; in3 = 1'bx; #1000 + $display(" %b %b | %b %b %b %b | %b", S0, S1, in0, in1, in2, in3, muxout); + +// just the adder - proper behavior + $display("Adder/Subtractor"); + $display("A B | Command |Out|ExpectOut|Carryout-Add"); + // adding + A=1;B=1;Command=3'b000; carryin = 0; #1000 + $display("%b %b | %b | %b | 0 | %b", A, B, Command, AddSubSLTSum, carryout); + A=1;B=0;Command=3'b000; carryin = 0; #1000 + $display("%b %b | %b | %b | 1 | %b", A, B, Command, AddSubSLTSum, carryout); + A=0;B=1;Command=3'b000; carryin = 0; #1000 + $display("%b %b | %b | %b | 1 | %b", A, B, Command, AddSubSLTSum, carryout); + A=0;B=0;Command=3'b000; carryin = 0; #1000 + $display("%b %b | %b | %b | 0 | %b", A, B, Command, AddSubSLTSum, carryout); + // subtracting - carrying must be set to 1 for subtraction + $display("A B | Command |Out|ExpectOut|Carryout-Sub"); + A=1;B=1;Command=3'b001; carryin = 1; #1000 + $display("%b %b | %b | %b | 0 | %b", A, B, Command, AddSubSLTSum, carryout); + A=1;B=0;Command=3'b001; carryin = 1; #1000 + $display("%b %b | %b | %b | 1 | %b", A, B, Command, AddSubSLTSum, carryout); + A=0;B=1;Command=3'b001; carryin = 1; #1000 + $display("%b %b | %b | %b | 1 | %b", A, B, Command, AddSubSLTSum, carryout); + A=0;B=0;Command=3'b001; carryin = 1; #1000 + $display("%b %b | %b | %b | 0 | %b", A, B, Command, AddSubSLTSum, carryout); + // SLT - this should look exactly like the subtraction, since nothing has been done to distinguish one from the other + $display("A B | Command |Out|ExpectOut|Carryout-SLT"); + A=1;B=1;Command=3'b011; carryin = 1; #1000 + $display("%b %b | %b | %b | 0 | %b", A, B, Command, AddSubSLTSum, carryout); + A=1;B=0;Command=3'b011; carryin = 1; #1000 + $display("%b %b | %b | %b | 1 | %b", A, B, Command, AddSubSLTSum, carryout); + A=0;B=1;Command=3'b011; carryin = 1; #1000 + $display("%b %b | %b | %b | 1 | %b", A, B, Command, AddSubSLTSum, carryout); + A=0;B=0;Command=3'b011; carryin = 1; #1000 + $display("%b %b | %b | %b | 0 | %b", A, B, Command, AddSubSLTSum, carryout); + +// Exhaustively testing AND/NAND + $display("A B |Command|Out|ExpectOut-AND"); + A=0;B=0;Command=3'b100; #1000 + $display("%b %b | %b | %b | 0", A, B, Command, AndNandOut); + A=0;B=1;Command=3'b100; #1000 + $display("%b %b | %b | %b | 0", A, B, Command, AndNandOut); + A=1;B=0;Command=3'b100; #1000 + $display("%b %b | %b | %b | 0", A, B, Command, AndNandOut); + A=1;B=1;Command=3'b100; #1000 + $display("%b %b | %b | %b | 1", A, B, Command, AndNandOut); + + $display("A B |Command|Out|ExpectOut-NAND"); + A=0;B=0;Command=3'b101; #1000 + $display("%b %b | %b | %b | 1", A, B, Command, AndNandOut); + A=0;B=1;Command=3'b101; #1000 + $display("%b %b | %b | %b | 1", A, B, Command, AndNandOut); + A=1;B=0;Command=3'b101; #1000 + $display("%b %b | %b | %b | 1", A, B, Command, AndNandOut); + A=1;B=1;Command=3'b101; #1000 + $display("%b %b | %b | %b | 0", A, B, Command, AndNandOut); + +// Exhaustively testing OR/NOR/XOR + $display("A B |Command|Out|ExpectOut-OR"); + A=1; B=1; Command=3'b111; #1000 + $display("%b %b | %b | %b | 1", A, B, Command, OrNorXorOut); + A=1; B=0; Command=3'b111; #1000 + $display("%b %b | %b | %b | 1", A, B, Command, OrNorXorOut); + A=0; B=1; Command=3'b111; #1000 + $display("%b %b | %b | %b | 1", A, B, Command, OrNorXorOut); + A=0; B=0; Command=3'b111; #1000 + $display("%b %b | %b | %b | 0", A, B, Command, OrNorXorOut); + + $display("A B |Command|Out|ExpectOut-NOR"); + A=1; B=1; Command=3'b110; #1000 + $display("%b %b | %b | %b | 0", A, B, Command, OrNorXorOut); + A=1; B=0; Command=3'b110; #1000 + $display("%b %b | %b | %b | 0", A, B, Command, OrNorXorOut); + A=0; B=1; Command=3'b110; #1000 + $display("%b %b | %b | %b | 0", A, B, Command, OrNorXorOut); + A=0; B=0; Command=3'b110; #1000 + $display("%b %b | %b | %b | 1", A, B, Command, OrNorXorOut); + + $display("A B |Command|Out|ExpectOut-XOR"); + A=1; B=1; Command=3'b010; #1000 + $display("%b %b | %b | %b | 0", A, B, Command, OrNorXorOut); + A=1; B=0; Command=3'b010; #1000 + $display("%b %b | %b | %b | 1", A, B, Command, OrNorXorOut); + A=0; B=1; Command=3'b010; #1000 + $display("%b %b | %b | %b | 1 ", A, B, Command, OrNorXorOut); + A=0; B=0; Command=3'b010; #1000 + $display("%b %b | %b | %b | 0", A, B, Command, OrNorXorOut); + +end + +endmodule + +*/ + + module test32Adder(); parameter size = 4; @@ -12,6 +142,7 @@ wire [size-1:0] AddSubSLTSum; wire carryout; wire overflow; wire SLTflag; +wire ZeroFlag; wire [size-1:0] subtract; reg [size-1:0] A, B; reg [2:0] Command; @@ -28,66 +159,259 @@ AndNand32 trial1(AndNandOut, A, B, Command); OrNorXor32 trial2(OrNorXorOut, A, B, Command); -Bitslice32 superalu(OneBitFinalOut, AddSubSLTSum, carryout, overflow, SLTflag, OrNorXorOut, AndNandOut, subtract, A, B, Command, carryin); +Bitslice32 superalu(OneBitFinalOut, AddSubSLTSum, carryout, overflow, SLTflag, OrNorXorOut, AndNandOut, subtract, ZeroFlag, A, B, Command, carryin); initial begin -$display("Test ALU - Add"); -$display(" A | B |Command|Output | ExpectOut|Cout|OF|subtract|SLTflag"); -A = 4'b1000; B = 4'b0001; Command =3'b000; #1000 -$display("%b | %b | %b | %b | Expect 1001| %b | %b ", A, B, Command, AddSubSLTSum, carryout, overflow); +$display("Test 4 Bit Adder Functionality"); +// there are too many possibilities even for just a four bit adder/subtractor, which means we need to choose our test cases strategically +$display(" A | B |Command| Out|ExpectedOut|Cout|OF"); -$display(" A | B |Command|Output | ExpectOut|Cout|OF|subtract|SLTflag"); -A = 4'b1000; B = 4'b0001; Command =3'b000; #1000 -$display("%b | %b | %b | %b | Expect 1001| %b | %b ", A, B, Command, OneBitFinalOut, carryout, overflow); -/* -A = 4'b1010; B = 4'b0001; Command =3'b000; #1000 -$display("%b | %b | %b | %b | Expect 1011| %b | %b | %b", A, B, Command, AddSubSLTSum, carryout, overflow, subtract); +//Pos + Pos < 7 | 2 + 4 = 6 | 2 = 0010 | 4 = 0100 | 6 = 0110 | NO OVERFLOW +A = 4'b0010; B = 4'b0100; Command =3'b000; #1000 +$display("%b | %b | %b | %b | Expect 0110| %b | %b ", A, B, Command, AddSubSLTSum, carryout, overflow); -A = 4'b1010; B = 4'b0001; Command =3'b000; #1000 -$display("%b | %b | %b | %b | Expect 1011| %b | %b ", A, B, Command, AddSubSLTSum, carryout, overflow); +//Pos + Pos < 7 | 1 + 6 = 7 | 1 = 0001 | 6 = 0110 | 7 = 0111 | NO OVERFLOW +A = 4'b0001; B = 4'b0110; Command =3'b000; #1000 +$display("%b | %b | %b | %b | Expect 0111| %b | %b ", A, B, Command, AddSubSLTSum, carryout, overflow); + +//Pos + Neg > 0 | 5 + -3 = 2 | 5 = 0101 | -3 = 1101 | 2 = 0010 | NO OVERFLOW +A = 4'b0101; B = 4'b1101; Command =3'b000; #1000 +$display("%b | %b | %b | %b | Expect 0010| %b | %b ", A, B, Command, AddSubSLTSum, carryout, overflow); -A = 4'b1010; B = 4'b0111; Command =3'b000; #1000 +//Pos + Neg > 0 | 2 + -1 = 1 | 2 = 0010 | -1 = 1111 | 1 = 0001 | NO OVERFLOW +A = 4'b0010; B = 4'b1111; Command =3'b000; #1000 $display("%b | %b | %b | %b | Expect 0001| %b | %b ", A, B, Command, AddSubSLTSum, carryout, overflow); -A = 4'b1010; B = 4'b0111; Command =3'b001; #1000 -$display("%b | %b | %b | %b | Expect 0011| %b | %b | %b", A, B, Command, AddSubSLTSum, carryout, overflow, subtract); +//Pos + Neg < 0 | -8 + 3 = -5 | -8 = 1000 | 3 = 0011 | -5 = 1011 | NO OVERFLOW +A = 4'b1000; B = 4'b0011; Command =3'b000; #1000 +$display("%b | %b | %b | %b | Expect 1011| %b | %b ", A, B, Command, AddSubSLTSum, carryout, overflow); + +//Pos + Neg < 0 | -4 + 2 = -2 | -4 = 1100 | 2 = 0010 | -2 = 1110 | NO OVERFLOW +A = 4'b1100; B = 4'b0010; Command =3'b000; #1000 +$display("%b | %b | %b | %b | Expect 1110| %b | %b ", A, B, Command, AddSubSLTSum, carryout, overflow); -A = 4'b1010; B = 4'b0111; Command =3'b011; #1000 -$display("%b | %b | %b | %b | Expect 0011| %b | %b | %b | %b", A, B, Command, AddSubSLTSum, carryout, overflow, subtract, SLTflag); +//Pos + Neg = 0 | -5 + 5 = 0 | -5 = 1101 | 5 = 0101 | 0 = 0000 | NO OVERFLOW +A = 4'b1011; B = 4'b0101; Command =3'b000; #1000 +$display("%b | %b | %b | %b | Expect 0110| %b | %b ", A, B, Command, AddSubSLTSum, carryout, overflow); -A = 4'b0111; B = 4'b1010; Command =3'b011; #1000 -$display("%b | %b | %b | %b | Expect 0011| %b | %b | %b | %b", A, B, Command, AddSubSLTSum, carryout, overflow, subtract, SLTflag); +//Pos + Neg = 0 | -7 + 7 = 0 | -7 = 1001 | 7 = 0111 | 0 = 0000 | NO OVERFLOW +A = 4'b0111; B = 4'b1001; Command =3'b000; #1000 +$display("%b | %b | %b | %b | Expect 0000| %b | %b ", A, B, Command, AddSubSLTSum, carryout, overflow); +//Neg + Neg > -8 | -3 + -4 = -7 | -3 = 1101 | -4 = 1100 | -7 = 1001 | NO OVERFLOW +A = 4'b1101; B = 4'b1100; Command =3'b000; #1000 +$display("%b | %b | %b | %b | Expect 1001| %b | %b ", A, B, Command, AddSubSLTSum, carryout, overflow); -A = 4'b0001; B = 4'b0010; Command =3'b011; #1000 -$display("%b | %b | %b | %b | Expect xxxx| %b | %b | %b | %b", A, B, Command, AddSubSLTSum, carryout, overflow, subtract, SLTflag); +//Neg + Neg > -8 | -2 + -6 = -8 | -2 = 1110 | -6 = 1010 | -8 = 1000 | NO OVERFLOW +A = 4'b1110; B = 4'b1010; Command =3'b000; #1000 +$display("%b | %b | %b | %b | Expect 1000| %b | %b ", A, B, Command, AddSubSLTSum, carryout, overflow); +//Pos + Pos > 7 | 5 + 6 = 11 | 5 = 0101 | 6 = 0110 | | OVERFLOW +A = 4'b0101; B = 4'b0110; Command =3'b000; #1000 +$display("%b | %b | %b | %b | Expect XXXX| %b | %b ", A, B, Command, AddSubSLTSum, carryout, overflow); -$display("AND/NAND"); -$display("A | B | Command | Output | ExpectedOut"); -A = 4'b0001; B = 4'b0010; Command =3'b100; #1000 -$display("%b | %b | %b | %b | Expect 0000", A, B, Command, AndNandOut); +//Pos + Pos > 7 | 2 + 7 = 9 | 2 = 0010 | 7 = 0111 | | OVERFLOW +A = 4'b0010; B = 4'b0111; Command =3'b000; #1000 +$display("%b | %b | %b | %b | Expect XXXX| %b | %b ", A, B, Command, AddSubSLTSum, carryout, overflow); -$display("A | B | Command | Output | ExpectedOut"); -A = 4'b0001; B = 4'b0010; Command =3'b101; #1000 -$display("%b | %b | %b | %b | Expect 1111", A, B, Command, AndNandOut); +//Pos + Pos > 7 | 7 + 7 = 14 | 7 = 0111 | 7 = 0111 | | OVERFLOW +A = 4'b0111; B = 4'b0111; Command =3'b000; #1000 +$display("%b | %b | %b | %b | Expect XXXX| %b | %b ", A, B, Command, AddSubSLTSum, carryout, overflow); -$display("OR/NOR/XOR"); -$display("A | B | Command | Output | ExpectedOutXOR"); -A = 4'b0001; B = 4'b0010; Command =3'b010; #1000 -$display("%b | %b | %b | %b | Expect 0011", A, B, Command, OrNorXorOut); +//Neg + Neg < -8 | -8 + -1 = -9 | -8 = 1000 | -1 = 1111 | | OVERFLOW +A = 4'b1000; B = 4'b1111; Command =3'b000; #1000 +$display("%b | %b | %b | %b | Expect XXXX| %b | %b ", A, B, Command, AddSubSLTSum, carryout, overflow); -$display("A | B | Command | Output | ExpectedOutNOR"); -A = 4'b0001; B = 4'b0010; Command =3'b110; #1000 -$display("%b | %b | %b | %b | Expect 1100", A, B, Command, OrNorXorOut); +//Neg + Neg < -8 | -8 + -3 = -11 | -8 = 1000 | -3 = 1101 | | OVERFLOW +A = 4'b1000; B = 4'b1101; Command =3'b000; #1000 +$display("%b | %b | %b | %b | Expect XXXX| %b | %b ", A, B, Command, AddSubSLTSum, carryout, overflow); -$display("A | B | Command | Output | ExpectedOutOR"); -A = 4'b0001; B = 4'b0010; Command =3'b111; #1000 -$display("%b | %b | %b | %b | Expect 0011", A, B, Command, OrNorXorOut); -*/ +//Neg + Neg < -8 | -5 + -4 = -9 | -5 = 1011 | -4 = 1100 | | OVERFLOW +A = 4'b1011; B = 4'b1100; Command =3'b000; #1000 +$display("%b | %b | %b | %b | Expect XXXX| %b | %b ", A, B, Command, AddSubSLTSum, carryout, overflow); + +$display("Test 4 Bit SLT Functionality"); +// there are too many possibilities even for just a four bit adder/subtractor, which means we need to choose our test cases strategically. We chose to not specifically test the subtractor, since it is part of the SLT, and if the SLT is working, then the subtractor is, too. +$display(" A | B |Command| Out|ExpectedOut|Cout|OF |SLTflag"); + +// A < B, A > 0 | B > 0 | No Overflow | A = 2 = 0010 | B = 4 = 0100 +A = 4'b0010; B = 4'b0100; Command =3'b011; #1000 +$display("%b | %b | %b | %b | Expect 1110| %b | %b | %b", A, B, Command, AddSubSLTSum, carryout, overflow, SLTflag); + +// A > B, A > 0 | B > 0 | No Overflow | A = 4 = 0100 | B = 2 = 0010 +A = 4'b0100; B = 4'b0010; Command =3'b011; #1000 +$display("%b | %b | %b | %b | Expect 0010| %b | %b | %b", A, B, Command, AddSubSLTSum, carryout, overflow, SLTflag); + +// A < B, A < 0 | B > 0 | No Overflow | A = -2 = 1110 | B = 4 = 0100 +A = 4'b1110; B = 4'b0100; Command =3'b011; #1000 +$display("%b | %b | %b | %b | Expect 1010| %b | %b | %b", A, B, Command, AddSubSLTSum, carryout, overflow, SLTflag); + +// A > B, A > 0 | B < 0 | No Overflow | A = 4 = 0100| B = -2 = 1110 +A = 4'b0100; B = 4'b1110; Command =3'b011; #1000 +$display("%b | %b | %b | %b | Expect 0110| %b | %b | %b", A, B, Command, AddSubSLTSum, carryout, overflow, SLTflag); + +// A < B, A < 0 | B < 0 | No Overflow | A = -2 = 1110 | B = -1 = 1111 +A = 4'b1110; B = 4'b1111; Command =3'b011; #1000 +$display("%b | %b | %b | %b | Expect 1111| %b | %b | %b", A, B, Command, AddSubSLTSum, carryout, overflow, SLTflag); + +// A > B, A < 0 | B < 0 | No Overflow | A = -1 = 1111 | B = -2 = 1110 +A = 4'b1111; B = 4'b1110; Command =3'b011; #1000 +$display("%b | %b | %b | %b | Expect 0001| %b | %b | %b", A, B, Command, AddSubSLTSum, carryout, overflow, SLTflag); + +// A = B, A < 0 | B < 0 | No Overflow | A = -3 = 1101 | B = -3 = 1101 +A = 4'b1101; B = 4'b1101; Command =3'b011; #1000 +$display("%b | %b | %b | %b | Expect 0000| %b | %b | %b", A, B, Command, AddSubSLTSum, carryout, overflow, SLTflag); + +// A = B, A > 0 | B > 0 | No Overflow | A = 5 = 0101 | B = 5 = 0101 +A = 4'b0101; B = 4'b0101; Command =3'b011; #1000 +$display("%b | %b | %b | %b | Expect 0000| %b | %b | %b", A, B, Command, AddSubSLTSum, carryout, overflow, SLTflag); + +// A < B, A < 0 | B > 0 | Overflow | A = -7 = 1001 | B = 5 = 0101 +A = 4'b1001; B = 4'b0101; Command =3'b011; #1000 +$display("%b | %b | %b | %b | Expect XXXX| %b | %b | %b", A, B, Command, AddSubSLTSum, carryout, overflow, SLTflag); + +$display("Test 4 Bit AND/NAND Functionality"); +// there are too many possibilities even for just a four bit AND/NAND, which means we need to choose our test cases strategically. +$display(" A | B |Command| Out |ExpectedOut-AND"); + +// A = B | A = 1111 | AND = 1111 + A=4'b1111;B=4'b1111;Command=3'b100; #1000 + $display("%b | %b | %b | %b | 1111", A, B, Command, AndNandOut); + +// A = 1111 | B = 1010 | AND = 1010 + A=4'b1111;B=4'b1010;Command=3'b100; #1000 + $display("%b | %b | %b | %b | 1010", A, B, Command, AndNandOut); + +// A = 1111 | B = 0101 | AND = 0101 + A=4'b1111;B=4'b0101;Command=3'b100; #1000 + $display("%b | %b | %b | %b | 0101", A, B, Command, AndNandOut); + +// A = 1111 | B = 0000 | AND = 0000 + A=4'b1111;B=4'b0000;Command=3'b100; #1000 + $display("%b | %b | %b | %b | 0000", A, B, Command, AndNandOut); + + +$display(" A | B |Command| Out |ExpectedOut-NAND"); + +// A = B | A = 1111 | NAND = 0000 + A=4'b1111;B=4'b1111;Command=3'b101; #1000 + $display("%b | %b | %b | %b | 0000", A, B, Command, AndNandOut); + +// A = 1111 | B = 1010 | NAND = 0101 + A=4'b1111;B=4'b1010;Command=3'b101; #1000 + $display("%b | %b | %b | %b | 0101", A, B, Command, AndNandOut); + +// A = 1111 | B = 0101 | NAND = 1010 + A=4'b1111;B=4'b0101;Command=3'b101; #1000 + $display("%b | %b | %b | %b | 1010", A, B, Command, AndNandOut); + +// A = 1111 | B = 0000 | NAND = 1111 + A=4'b1111;B=4'b0000;Command=3'b101; #1000 + $display("%b | %b | %b | %b | 1111", A, B, Command, AndNandOut); + +$display("Test 4 Bit OR/NOR/XOR Functionality"); +// there are too many possibilities even for just a four bit AND/NAND, which means we need to choose our test cases strategically. +$display(" A | B |Command | Out |ExpectedOut-OR"); + +// A = 1010 | B = 0101 | OR = 1111 + A=4'b1010; B=4'b0101; Command=3'b111; #1000 + $display("%b | %b | %b | %b | 1111", A, B, Command, OrNorXorOut); + +// A = 1111 | B = 0101 | OR = 1111 + A=4'b1111; B=4'b0101; Command=3'b111; #1000 + $display("%b | %b | %b | %b | 1111", A, B, Command, OrNorXorOut); + +// A = 1011 | B = 0000 | OR = 1011 + A=4'b1011; B=4'b0000; Command=3'b111; #1000 + $display("%b | %b | %b | %b | 1011", A, B, Command, OrNorXorOut); + +$display(" A | B |Command | Out |ExpectedOut-NOR"); + +// A = 1010 | B = 0101 | NOR = 0000 + A=4'b1010; B=4'b0101; Command=3'b110; #1000 + $display("%b | %b | %b | %b | 0000", A, B, Command, OrNorXorOut); + +// A = 1111 | B = 0101 | NOR = 0000 + A=4'b1111; B=4'b0101; Command=3'b110; #1000 + $display("%b | %b | %b | %b | 0000", A, B, Command, OrNorXorOut); + +// A = 1011 | B = 0000 | NOR = 0100 + A=4'b1011; B=4'b0000; Command=3'b110; #1000 + $display("%b | %b | %b | %b | 0100", A, B, Command, OrNorXorOut); + +$display(" A | B |Command | Out |ExpectedOut-XOR"); + +// A = 1010 | B = 0101 | XOR = 1111 + A=4'b1010; B=4'b0101; Command=3'b010; #1000 + $display("%b | %b | %b | %b | 1111", A, B, Command, OrNorXorOut); + +// A = 1111 | B = 0101 | XOR = 1010 + A=4'b1111; B=4'b0101; Command=3'b010; #1000 + $display("%b | %b | %b | %b | 1010", A, B, Command, OrNorXorOut); + +// A = 1011 | B = 0000 | XOR = 1011 + A=4'b1011; B=4'b0000; Command=3'b010; #1000 + $display("%b | %b | %b | %b | 1011", A, B, Command, OrNorXorOut); + +$display("Test 4 Bit ALU Functionality"); +// there are too many possibilities even for just a four bit AND/NAND, which means we need to choose our test cases strategically. +$display(" A | B |Command | Out |ExpectedOut | COut | OF |SLT|Zero"); + +// Test AND +// A = B | A = 1111 | AND = 1111 + A=4'b1111;B=4'b1111;Command=3'b100; #1000 + $display("%b | %b | %b - AND | %b | 1111 | %b | %b | %b | %b", A, B, Command, OneBitFinalOut, carryout, overflow, SLTflag, ZeroFlag); + +// Test NAND +// A = 1111 | B = 0000 | NAND = 1111 + A=4'b1111;B=4'b0000;Command=3'b101; #1000 + $display("%b | %b | %b - NAND | %b | 1111 | %b | %b | %b | %b", A, B, Command, OneBitFinalOut, carryout, overflow, SLTflag, ZeroFlag); + +// Test OR +// A = 1111 | B = 0101 | OR = 1111 + A=4'b1111; B=4'b0101; Command=3'b111; #1000 + $display("%b | %b | %b - OR | %b | 1111 | %b | %b | %b | %b", A, B, Command, OneBitFinalOut, carryout, overflow, SLTflag, ZeroFlag); + +// Test NOR +// A = 1011 | B = 0000 | NOR = 0100 + A=4'b1011; B=4'b0000; Command=3'b110; #1000 + $display("%b | %b | %b - NOR | %b | 0100 | %b | %b | %b | %b", A, B, Command, OneBitFinalOut, carryout, overflow, SLTflag, ZeroFlag); + +// Test XOR +// A = 1011 | B = 0000 | XOR = 1011 + A=4'b1011; B=4'b0000; Command=3'b010; #1000 + $display("%b | %b | %b - XOR | %b | 1011 | %b | %b | %b | %b", A, B, Command, OneBitFinalOut, carryout, overflow, SLTflag, ZeroFlag); + +// Test ADD +//Pos + Pos < 7 | 2 + 4 = 6 | 2 = 0010 | 4 = 0100 | 6 = 0110 | NO OVERFLOW +A = 4'b0010; B = 4'b0100; Command =3'b000; #1000 + $display("%b | %b | %b - ADD | %b | 0110 | %b | %b | %b | %b", A, B, Command, OneBitFinalOut, carryout, overflow, SLTflag, ZeroFlag); + +//Neg + Neg < -8 | -5 + -4 = -9 | -5 = 1011 | -4 = 1100 | | OVERFLOW +A = 4'b1011; B = 4'b1100; Command =3'b000; #1000 + $display("%b | %b | %b - ADD | %b | XXXX | %b | %b | %b | %b", A, B, Command, OneBitFinalOut, carryout, overflow, SLTflag, ZeroFlag); + +// Test SUB +// A < B, A > 0 | B > 0 | No Overflow | A = 2 = 0010 | B = 4 = 0100 +A = 4'b0010; B = 4'b0100; Command =3'b001; #1000 + $display("%b | %b | %b - SUB | %b | 1110 | %b | %b | %b | %b", A, B, Command, OneBitFinalOut, carryout, overflow, SLTflag, ZeroFlag); + +// A < B, A < 0 | B > 0 | Overflow | A = -7 = 1001 | B = 3 = 0011 +A = 4'b1001; B = 4'b0011; Command =3'b001; #1000 + $display("%b | %b | %b - SUB | %b | XXXX | %b | %b | %b | %b", A, B, Command, OneBitFinalOut, carryout, overflow, SLTflag, ZeroFlag); + +// Test SLT + +// A > B, A > 0 | B > 0 | No Overflow | A = 4 = 0100 | B = 2 = 0010 +A = 4'b0100; B = 4'b0010; Command =3'b011; #1000 + $display("%b | %b | %b - SLT | %b | 0010 | %b | %b | %b | %b", A, B, Command, OneBitFinalOut, carryout, overflow, SLTflag, ZeroFlag); +// A < B, A < 0 | B > 0 | Overflow | A = -7 = 1001 | B = 5 = 0101 +A = 4'b1001; B = 4'b0101; Command =3'b011; #1000 + $display("%b | %b | %b - SLT | %b | XXXX | %b | %b | %b | %b", A, B, Command, OneBitFinalOut, carryout, overflow, SLTflag, ZeroFlag); end endmodule + From a669e414efe59f502c44e568ad43a5170f9fcfbe Mon Sep 17 00:00:00 2001 From: LoganSweet Date: Mon, 9 Oct 2017 21:51:00 -0400 Subject: [PATCH 11/28] git debacle #1 --- README.md | 165 ---- alu2.v | 310 +++----- test | 2114 --------------------------------------------------- testing.t.v | 404 +++++++++- 4 files changed, 475 insertions(+), 2518 deletions(-) delete mode 100644 README.md delete mode 100755 test diff --git a/README.md b/README.md deleted file mode 100644 index f6202d8..0000000 --- a/README.md +++ /dev/null @@ -1,165 +0,0 @@ -# CompArch Lab 1: Arithmetic Logic Unit - -**Work plan due:** Wed. October 4 - -**Lab due:** Thu. October 12 - - -This lab assignment creates the first component of your processor: the ALU. Additionally, it will help you understand the timing constraints of your designs. - -You will work in groups of 2-3. You may shuffle teams from the first lab if you so choose. - -## Specification ## - -The ALU you will implement is a subset of the standard MIPS ALU. The number of operations supported has been reduced, but otherwise we are emulating that standard. - -ALU diagram - - -| Operation | Result | Sets flags? | ALU Control | -|-----------|---------------|---------------|---------------| -| ADD | `R=A+B` | Yes | `b000` | -| SUB | `R=A-B` | Yes | `b001` | -| XOR | `R=A^B` | No | `b010` | -| SLT | `R=(A; 0 drivers -v0x17ba9e0_0 .net "AddSubSLTSum", 0 0, C4; 0 drivers -v0x17baa80_0 .net "AddSumSLTSum", 0 0, L_0x17de9e0; 1 drivers -v0x17bab90_0 .net "AndNandOut", 0 0, L_0x17e06b0; 1 drivers -v0x17baca0_0 .net "B", 0 0, C4; 0 drivers -v0x17badb0_0 .net "Cmd0Start", 0 0, L_0x17e0ee0; 1 drivers -v0x17bae30_0 .net "Cmd1Start", 0 0, L_0x17e1910; 1 drivers -v0x17baeb0_0 .net "Command", 2 0, C4; 0 drivers -v0x17baf30_0 .net "OneBitFinalOut", 0 0, L_0x17e2070; 1 drivers -v0x17bafb0_0 .net "OrNorXorOut", 0 0, L_0x17dfe00; 1 drivers -v0x17bb030_0 .net "carryin", 0 0, C4; 0 drivers -v0x17bb0b0_0 .net "carryout", 0 0, L_0x17ded90; 1 drivers -v0x17bb130_0 .net "subtract", 0 0, L_0x17de6b0; 1 drivers -L_0x17e10c0 .part C4, 0, 1; -L_0x17e11f0 .part C4, 1, 1; -L_0x17e1af0 .part C4, 0, 1; -L_0x17e1c20 .part C4, 1, 1; -L_0x17e21a0 .part C4, 2, 1; -S_0x17b98e0 .scope module, "rottenpotato" "MiddleAddSubSLT" 2 147, 2 95, S_0x178b140; - .timescale -9 -12; -L_0x17d9050/d .functor NOT 1, C4, C4<0>, C4<0>, C4<0>; -L_0x17d9050 .delay (10000,10000,10000) L_0x17d9050/d; -L_0x17de550/d .functor NOT 1, L_0x17de610, C4<0>, C4<0>, C4<0>; -L_0x17de550 .delay (10000,10000,10000) L_0x17de550/d; -L_0x17de6b0/d .functor AND 1, L_0x17de7f0, L_0x17de550, C4<1>, C4<1>; -L_0x17de6b0 .delay (20000,20000,20000) L_0x17de6b0/d; -L_0x17de890/d .functor XOR 1, C4, L_0x17de250, C4<0>, C4<0>; -L_0x17de890 .delay (40000,40000,40000) L_0x17de890/d; -L_0x17de9e0/d .functor XOR 1, L_0x17de890, C4, C4<0>, C4<0>; -L_0x17de9e0 .delay (40000,40000,40000) L_0x17de9e0/d; -L_0x17deb40/d .functor AND 1, C4, L_0x17de250, C4<1>, C4<1>; -L_0x17deb40 .delay (20000,20000,20000) L_0x17deb40/d; -L_0x17decd0/d .functor AND 1, L_0x17de890, C4, C4<1>, C4<1>; -L_0x17decd0 .delay (20000,20000,20000) L_0x17decd0/d; -L_0x17ded90/d .functor OR 1, L_0x17deb40, L_0x17decd0, C4<0>, C4<0>; -L_0x17ded90 .delay (20000,20000,20000) L_0x17ded90/d; -v0x17b9e60_0 .alias "A", 0 0, v0x17ba940_0; -v0x17b9f50_0 .net "AandB", 0 0, L_0x17deb40; 1 drivers -v0x17b9ff0_0 .alias "AddSubSLTSum", 0 0, v0x17baa80_0; -v0x17ba070_0 .net "AxorB", 0 0, L_0x17de890; 1 drivers -v0x17ba0f0_0 .alias "B", 0 0, v0x17baca0_0; -v0x17ba170_0 .net "BornB", 0 0, L_0x17de250; 1 drivers -v0x17ba230_0 .net "CINandAxorB", 0 0, L_0x17decd0; 1 drivers -v0x17ba2b0_0 .alias "Command", 2 0, v0x17baeb0_0; -v0x17ba3d0_0 .net *"_s3", 0 0, L_0x17de610; 1 drivers -v0x17ba470_0 .net *"_s5", 0 0, L_0x17de7f0; 1 drivers -v0x17ba570_0 .alias "carryin", 0 0, v0x17bb030_0; -v0x17ba610_0 .alias "carryout", 0 0, v0x17bb0b0_0; -v0x17ba720_0 .net "nB", 0 0, L_0x17d9050; 1 drivers -v0x17ba7a0_0 .net "nCmd2", 0 0, L_0x17de550; 1 drivers -v0x17ba8a0_0 .alias "subtract", 0 0, v0x17bb130_0; -L_0x17de420 .part C4, 0, 1; -L_0x17de610 .part C4, 2, 1; -L_0x17de7f0 .part C4, 0, 1; -S_0x17b99d0 .scope module, "mux0" "TwoInMux" 2 111, 2 8, S_0x17b98e0; - .timescale -9 -12; -L_0x17ddf70/d .functor NOT 1, L_0x17de420, C4<0>, C4<0>, C4<0>; -L_0x17ddf70 .delay (10000,10000,10000) L_0x17ddf70/d; -L_0x17de030/d .functor AND 1, C4, L_0x17ddf70, C4<1>, C4<1>; -L_0x17de030 .delay (20000,20000,20000) L_0x17de030/d; -L_0x17de140/d .functor AND 1, L_0x17d9050, L_0x17de420, C4<1>, C4<1>; -L_0x17de140 .delay (20000,20000,20000) L_0x17de140/d; -L_0x17de250/d .functor OR 1, L_0x17de030, L_0x17de140, C4<0>, C4<0>; -L_0x17de250 .delay (20000,20000,20000) L_0x17de250/d; -v0x17b9ac0_0 .net "S", 0 0, L_0x17de420; 1 drivers -v0x17b9b40_0 .alias "in0", 0 0, v0x17baca0_0; -v0x17b9bc0_0 .alias "in1", 0 0, v0x17ba720_0; -v0x17b9c40_0 .net "nS", 0 0, L_0x17ddf70; 1 drivers -v0x17b9cc0_0 .net "out0", 0 0, L_0x17de030; 1 drivers -v0x17b9d40_0 .net "out1", 0 0, L_0x17de140; 1 drivers -v0x17b9dc0_0 .alias "outfinal", 0 0, v0x17ba170_0; -S_0x17b85f0 .scope module, "idahopotato" "OrNorXor" 2 148, 2 70, S_0x178b140; - .timescale -9 -12; -L_0x17def10/d .functor NOR 1, C4, C4, C4<0>, C4<0>; -L_0x17def10 .delay (10000,10000,10000) L_0x17def10/d; -L_0x17df070/d .functor NOT 1, L_0x17def10, C4<0>, C4<0>, C4<0>; -L_0x17df070 .delay (10000,10000,10000) L_0x17df070/d; -L_0x17df1a0/d .functor NAND 1, C4, C4, C4<1>, C4<1>; -L_0x17df1a0 .delay (10000,10000,10000) L_0x17df1a0/d; -L_0x17df330/d .functor NAND 1, L_0x17df1a0, L_0x17df070, C4<1>, C4<1>; -L_0x17df330 .delay (10000,10000,10000) L_0x17df330/d; -L_0x17df420/d .functor NOT 1, L_0x17df330, C4<0>, C4<0>, C4<0>; -L_0x17df420 .delay (10000,10000,10000) L_0x17df420/d; -v0x17b91a0_0 .alias "A", 0 0, v0x17ba940_0; -v0x17b9250_0 .net "AnandB", 0 0, L_0x17df1a0; 1 drivers -v0x17b92d0_0 .net "AnorB", 0 0, L_0x17def10; 1 drivers -v0x17b9380_0 .net "AorB", 0 0, L_0x17df070; 1 drivers -v0x17b9460_0 .net "AxorB", 0 0, L_0x17df420; 1 drivers -v0x17b9510_0 .alias "B", 0 0, v0x17baca0_0; -v0x17b95d0_0 .alias "Command", 2 0, v0x17baeb0_0; -v0x17b9680_0 .alias "OrNorXorOut", 0 0, v0x17bafb0_0; -v0x17b97e0_0 .net "XorNor", 0 0, L_0x17df880; 1 drivers -v0x17b9860_0 .net "nXor", 0 0, L_0x17df330; 1 drivers -L_0x17dfa00 .part C4, 2, 1; -L_0x17dff80 .part C4, 0, 1; -S_0x17b8c30 .scope module, "mux0" "TwoInMux" 2 89, 2 8, S_0x17b85f0; - .timescale -9 -12; -L_0x17df560/d .functor NOT 1, L_0x17dfa00, C4<0>, C4<0>, C4<0>; -L_0x17df560 .delay (10000,10000,10000) L_0x17df560/d; -L_0x17df620/d .functor AND 1, L_0x17df420, L_0x17df560, C4<1>, C4<1>; -L_0x17df620 .delay (20000,20000,20000) L_0x17df620/d; -L_0x17df730/d .functor AND 1, L_0x17def10, L_0x17dfa00, C4<1>, C4<1>; -L_0x17df730 .delay (20000,20000,20000) L_0x17df730/d; -L_0x17df880/d .functor OR 1, L_0x17df620, L_0x17df730, C4<0>, C4<0>; -L_0x17df880 .delay (20000,20000,20000) L_0x17df880/d; -v0x17b8d20_0 .net "S", 0 0, L_0x17dfa00; 1 drivers -v0x17b8de0_0 .alias "in0", 0 0, v0x17b9460_0; -v0x17b8e80_0 .alias "in1", 0 0, v0x17b92d0_0; -v0x17b8f20_0 .net "nS", 0 0, L_0x17df560; 1 drivers -v0x17b8fa0_0 .net "out0", 0 0, L_0x17df620; 1 drivers -v0x17b9040_0 .net "out1", 0 0, L_0x17df730; 1 drivers -v0x17b9120_0 .alias "outfinal", 0 0, v0x17b97e0_0; -S_0x17b86e0 .scope module, "mux1" "TwoInMux" 2 90, 2 8, S_0x17b85f0; - .timescale -9 -12; -L_0x17dfaa0/d .functor NOT 1, L_0x17dff80, C4<0>, C4<0>, C4<0>; -L_0x17dfaa0 .delay (10000,10000,10000) L_0x17dfaa0/d; -L_0x17dfb60/d .functor AND 1, L_0x17df880, L_0x17dfaa0, C4<1>, C4<1>; -L_0x17dfb60 .delay (20000,20000,20000) L_0x17dfb60/d; -L_0x17dfcb0/d .functor AND 1, L_0x17df070, L_0x17dff80, C4<1>, C4<1>; -L_0x17dfcb0 .delay (20000,20000,20000) L_0x17dfcb0/d; -L_0x17dfe00/d .functor OR 1, L_0x17dfb60, L_0x17dfcb0, C4<0>, C4<0>; -L_0x17dfe00 .delay (20000,20000,20000) L_0x17dfe00/d; -v0x17b87d0_0 .net "S", 0 0, L_0x17dff80; 1 drivers -v0x17b8870_0 .alias "in0", 0 0, v0x17b97e0_0; -v0x17b8910_0 .alias "in1", 0 0, v0x17b9380_0; -v0x17b89b0_0 .net "nS", 0 0, L_0x17dfaa0; 1 drivers -v0x17b8a30_0 .net "out0", 0 0, L_0x17dfb60; 1 drivers -v0x17b8ad0_0 .net "out1", 0 0, L_0x17dfcb0; 1 drivers -v0x17b8bb0_0 .alias "outfinal", 0 0, v0x17bafb0_0; -S_0x17b7c50 .scope module, "sweetpotato" "AndNand" 2 149, 2 53, S_0x178b140; - .timescale -9 -12; -L_0x17de4c0/d .functor NAND 1, C4, C4, C4<1>, C4<1>; -L_0x17de4c0 .delay (10000,10000,10000) L_0x17de4c0/d; -L_0x17e0260/d .functor NOT 1, L_0x17de4c0, C4<0>, C4<0>, C4<0>; -L_0x17e0260 .delay (10000,10000,10000) L_0x17e0260/d; -v0x17b8270_0 .alias "A", 0 0, v0x17ba940_0; -v0x17b8330_0 .net "AandB", 0 0, L_0x17e0260; 1 drivers -v0x17b83b0_0 .net "AnandB", 0 0, L_0x17de4c0; 1 drivers -v0x17b8430_0 .alias "AndNandOut", 0 0, v0x17bab90_0; -v0x17b84b0_0 .alias "B", 0 0, v0x17baca0_0; -v0x17b8530_0 .alias "Command", 2 0, v0x17baeb0_0; -L_0x17e0830 .part C4, 0, 1; -S_0x17b7d40 .scope module, "potato" "TwoInMux" 2 66, 2 8, S_0x17b7c50; - .timescale -9 -12; -L_0x17e0390/d .functor NOT 1, L_0x17e0830, C4<0>, C4<0>, C4<0>; -L_0x17e0390 .delay (10000,10000,10000) L_0x17e0390/d; -L_0x17e0450/d .functor AND 1, L_0x17e0260, L_0x17e0390, C4<1>, C4<1>; -L_0x17e0450 .delay (20000,20000,20000) L_0x17e0450/d; -L_0x17e0560/d .functor AND 1, L_0x17de4c0, L_0x17e0830, C4<1>, C4<1>; -L_0x17e0560 .delay (20000,20000,20000) L_0x17e0560/d; -L_0x17e06b0/d .functor OR 1, L_0x17e0450, L_0x17e0560, C4<0>, C4<0>; -L_0x17e06b0 .delay (20000,20000,20000) L_0x17e06b0/d; -v0x17b7e30_0 .net "S", 0 0, L_0x17e0830; 1 drivers -v0x17b7ef0_0 .alias "in0", 0 0, v0x17b8330_0; -v0x17b7f90_0 .alias "in1", 0 0, v0x17b83b0_0; -v0x17b8030_0 .net "nS", 0 0, L_0x17e0390; 1 drivers -v0x17b80b0_0 .net "out0", 0 0, L_0x17e0450; 1 drivers -v0x17b8150_0 .net "out1", 0 0, L_0x17e0560; 1 drivers -v0x17b81f0_0 .alias "outfinal", 0 0, v0x17bab90_0; -S_0x17b7290 .scope module, "ZeroMux" "FourInMux" 2 151, 2 29, S_0x178b140; - .timescale -9 -12; -L_0x17e08d0/d .functor NOT 1, L_0x17e10c0, C4<0>, C4<0>, C4<0>; -L_0x17e08d0 .delay (10000,10000,10000) L_0x17e08d0/d; -L_0x17e0990/d .functor NOT 1, L_0x17e11f0, C4<0>, C4<0>, C4<0>; -L_0x17e0990 .delay (10000,10000,10000) L_0x17e0990/d; -L_0x17e0a50/d .functor NAND 1, L_0x17e08d0, L_0x17e0990, L_0x17de9e0, C4<1>; -L_0x17e0a50 .delay (10000,10000,10000) L_0x17e0a50/d; -L_0x17e0b90/d .functor NAND 1, L_0x17e10c0, L_0x17e0990, L_0x17de9e0, C4<1>; -L_0x17e0b90 .delay (10000,10000,10000) L_0x17e0b90/d; -L_0x17e0c80/d .functor NAND 1, L_0x17e08d0, L_0x17e11f0, L_0x17dfe00, C4<1>; -L_0x17e0c80 .delay (10000,10000,10000) L_0x17e0c80/d; -L_0x17e0d70/d .functor NAND 1, L_0x17e10c0, L_0x17e11f0, L_0x17de9e0, C4<1>; -L_0x17e0d70 .delay (10000,10000,10000) L_0x17e0d70/d; -L_0x17e0ee0/d .functor NAND 1, L_0x17e0a50, L_0x17e0b90, L_0x17e0c80, L_0x17e0d70; -L_0x17e0ee0 .delay (10000,10000,10000) L_0x17e0ee0/d; -v0x17b7380_0 .net "S0", 0 0, L_0x17e10c0; 1 drivers -v0x17b7440_0 .net "S1", 0 0, L_0x17e11f0; 1 drivers -v0x17b74e0_0 .alias "in0", 0 0, v0x17baa80_0; -v0x17b7580_0 .alias "in1", 0 0, v0x17baa80_0; -v0x17b7660_0 .alias "in2", 0 0, v0x17bafb0_0; -v0x17b76e0_0 .alias "in3", 0 0, v0x17baa80_0; -v0x17b77b0_0 .net "nS0", 0 0, L_0x17e08d0; 1 drivers -v0x17b7830_0 .net "nS1", 0 0, L_0x17e0990; 1 drivers -v0x17b7900_0 .alias "out", 0 0, v0x17badb0_0; -v0x17b7980_0 .net "out0", 0 0, L_0x17e0a50; 1 drivers -v0x17b7a00_0 .net "out1", 0 0, L_0x17e0b90; 1 drivers -v0x17b7aa0_0 .net "out2", 0 0, L_0x17e0c80; 1 drivers -v0x17b7bb0_0 .net "out3", 0 0, L_0x17e0d70; 1 drivers -S_0x17b6880 .scope module, "OneMux" "FourInMux" 2 152, 2 29, S_0x178b140; - .timescale -9 -12; -L_0x17e1320/d .functor NOT 1, L_0x17e1af0, C4<0>, C4<0>, C4<0>; -L_0x17e1320 .delay (10000,10000,10000) L_0x17e1320/d; -L_0x17e13e0/d .functor NOT 1, L_0x17e1c20, C4<0>, C4<0>, C4<0>; -L_0x17e13e0 .delay (10000,10000,10000) L_0x17e13e0/d; -L_0x17e14a0/d .functor NAND 1, L_0x17e1320, L_0x17e13e0, L_0x17e06b0, C4<1>; -L_0x17e14a0 .delay (10000,10000,10000) L_0x17e14a0/d; -L_0x17e1540/d .functor NAND 1, L_0x17e1af0, L_0x17e13e0, L_0x17e06b0, C4<1>; -L_0x17e1540 .delay (10000,10000,10000) L_0x17e1540/d; -L_0x17e1630/d .functor NAND 1, L_0x17e1320, L_0x17e1c20, L_0x17dfe00, C4<1>; -L_0x17e1630 .delay (10000,10000,10000) L_0x17e1630/d; -L_0x17e1800/d .functor NAND 1, L_0x17e1af0, L_0x17e1c20, L_0x17dfe00, C4<1>; -L_0x17e1800 .delay (10000,10000,10000) L_0x17e1800/d; -L_0x17e1910/d .functor NAND 1, L_0x17e14a0, L_0x17e1540, L_0x17e1630, L_0x17e1800; -L_0x17e1910 .delay (10000,10000,10000) L_0x17e1910/d; -v0x17b6970_0 .net "S0", 0 0, L_0x17e1af0; 1 drivers -v0x17b6a30_0 .net "S1", 0 0, L_0x17e1c20; 1 drivers -v0x17b6ad0_0 .alias "in0", 0 0, v0x17bab90_0; -v0x17b6b70_0 .alias "in1", 0 0, v0x17bab90_0; -v0x17b6c20_0 .alias "in2", 0 0, v0x17bafb0_0; -v0x17b6ca0_0 .alias "in3", 0 0, v0x17bafb0_0; -v0x17b6d60_0 .net "nS0", 0 0, L_0x17e1320; 1 drivers -v0x17b6de0_0 .net "nS1", 0 0, L_0x17e13e0; 1 drivers -v0x17b6eb0_0 .alias "out", 0 0, v0x17bae30_0; -v0x17b6f60_0 .net "out0", 0 0, L_0x17e14a0; 1 drivers -v0x17b7040_0 .net "out1", 0 0, L_0x17e1540; 1 drivers -v0x17b70e0_0 .net "out2", 0 0, L_0x17e1630; 1 drivers -v0x17b71f0_0 .net "out3", 0 0, L_0x17e1800; 1 drivers -S_0x1767cd0 .scope module, "TwoMux" "TwoInMux" 2 153, 2 8, S_0x178b140; - .timescale -9 -12; -L_0x17e1d50/d .functor NOT 1, L_0x17e21a0, C4<0>, C4<0>, C4<0>; -L_0x17e1d50 .delay (10000,10000,10000) L_0x17e1d50/d; -L_0x17e1df0/d .functor AND 1, L_0x17e0ee0, L_0x17e1d50, C4<1>, C4<1>; -L_0x17e1df0 .delay (20000,20000,20000) L_0x17e1df0/d; -L_0x17e1f20/d .functor AND 1, L_0x17e1910, L_0x17e21a0, C4<1>, C4<1>; -L_0x17e1f20 .delay (20000,20000,20000) L_0x17e1f20/d; -L_0x17e2070/d .functor OR 1, L_0x17e1df0, L_0x17e1f20, C4<0>, C4<0>; -L_0x17e2070 .delay (20000,20000,20000) L_0x17e2070/d; -v0x16fba40_0 .net "S", 0 0, L_0x17e21a0; 1 drivers -v0x17b6470_0 .alias "in0", 0 0, v0x17badb0_0; -v0x17b6510_0 .alias "in1", 0 0, v0x17bae30_0; -v0x17b65b0_0 .net "nS", 0 0, L_0x17e1d50; 1 drivers -v0x17b6660_0 .net "out0", 0 0, L_0x17e1df0; 1 drivers -v0x17b6700_0 .net "out1", 0 0, L_0x17e1f20; 1 drivers -v0x17b67e0_0 .alias "outfinal", 0 0, v0x17baf30_0; -S_0x1782ed0 .scope module, "test32Adder" "test32Adder" 3 5; - .timescale -9 -12; -P_0x171d108 .param/l "size" 3 7, +C4<0100>; -v0x17dd890_0 .var "A", 3 0; -RS_0x7ff970b2c6f8/0/0 .resolv tri, L_0x17e33e0, L_0x17e4ad0, L_0x17e6010, L_0x17e7610; -RS_0x7ff970b2c6f8/0/4 .resolv tri, L_0x17f8a00, L_0x17f9e20, L_0x17fb220, L_0x17fc800; -RS_0x7ff970b2c6f8 .resolv tri, RS_0x7ff970b2c6f8/0/0, RS_0x7ff970b2c6f8/0/4, C4, C4; -v0x17dd910_0 .net8 "AddSubSLTSum", 3 0, RS_0x7ff970b2c6f8; 8 drivers -RS_0x7ff970b2b948/0/0 .resolv tri, L_0x17e9460, L_0x17e9e50, L_0x17ea8e0, L_0x17eb340; -RS_0x7ff970b2b948/0/4 .resolv tri, L_0x17fe630, L_0x17ff0a0, L_0x17ffb10, L_0x1800670; -RS_0x7ff970b2b948 .resolv tri, RS_0x7ff970b2b948/0/0, RS_0x7ff970b2b948/0/4, C4, C4; -v0x17dd990_0 .net8 "AndNandOut", 3 0, RS_0x7ff970b2b948; 8 drivers -v0x17dda10_0 .var "B", 3 0; -v0x17dda90_0 .var "Command", 2 0; -RS_0x7ff970b2cb48 .resolv tri, L_0x17f25a0, L_0x17f4f80, L_0x17f7790, L_0x1807460; -v0x17ddb10_0 .net8 "OneBitFinalOut", 3 0, RS_0x7ff970b2cb48; 4 drivers -RS_0x7ff970b2b258/0/0 .resolv tri, L_0x17ec700, L_0x17edc60, L_0x17eef60, L_0x17f0250; -RS_0x7ff970b2b258/0/4 .resolv tri, L_0x18019c0, L_0x1802cc0, L_0x1803fc0, L_0x18052b0; -RS_0x7ff970b2b258 .resolv tri, RS_0x7ff970b2b258/0/0, RS_0x7ff970b2b258/0/4, C4, C4; -v0x17ddb90_0 .net8 "OrNorXorOut", 3 0, RS_0x7ff970b2b258; 8 drivers -RS_0x7ff970b2c7b8 .resolv tri, L_0x17e8c40, L_0x17fdcd0, C4, C4; -v0x17ddc10_0 .net8 "SLTflag", 0 0, RS_0x7ff970b2c7b8; 2 drivers -v0x17ddc90_0 .var "carryin", 3 0; -RS_0x7ff970b2c9f8 .resolv tri, L_0x17e36c0, L_0x17fcb80, C4, C4; -v0x17ddd10_0 .net8 "carryout", 0 0, RS_0x7ff970b2c9f8; 2 drivers -RS_0x7ff970b2ca88 .resolv tri, L_0x17e7f10, L_0x17fcff0, C4, C4; -v0x17ddd90_0 .net8 "overflow", 0 0, RS_0x7ff970b2ca88; 2 drivers -RS_0x7ff970b2cab8/0/0 .resolv tri, L_0x17e3620, L_0x17e4d00, L_0x17e6270, L_0x17e6660; -RS_0x7ff970b2cab8/0/4 .resolv tri, L_0x17f8be0, L_0x17fa050, L_0x17fb480, L_0x17fb870; -RS_0x7ff970b2cab8 .resolv tri, RS_0x7ff970b2cab8/0/0, RS_0x7ff970b2cab8/0/4, C4, C4; -v0x17dde10_0 .net8 "subtract", 3 0, RS_0x7ff970b2cab8; 8 drivers -S_0x17d8120 .scope module, "trial" "AddSubSLT32" 3 25, 2 209, S_0x1782ed0; - .timescale -9 -12; -P_0x17d8218 .param/l "size" 2 232, +C4<0100>; -L_0x17e36c0/d .functor OR 1, L_0x17e7d60, C4<0>, C4<0>, C4<0>; -L_0x17e36c0 .delay (20000,20000,20000) L_0x17e36c0/d; -L_0x17e7f10/d .functor XOR 1, RS_0x7ff970b2c9f8, L_0x17e8040, C4<0>, C4<0>; -L_0x17e7f10 .delay (40000,40000,40000) L_0x17e7f10/d; -L_0x17e7c90/d .functor AND 1, L_0x17e8210, L_0x17e82b0, C4<1>, C4<1>; -L_0x17e7c90 .delay (20000,20000,20000) L_0x17e7c90/d; -L_0x17e80e0/d .functor NOT 1, RS_0x7ff970b2ca88, C4<0>, C4<0>, C4<0>; -L_0x17e80e0 .delay (10000,10000,10000) L_0x17e80e0/d; -L_0x17e84e0/d .functor NOT 1, L_0x17e8540, C4<0>, C4<0>, C4<0>; -L_0x17e84e0 .delay (10000,10000,10000) L_0x17e84e0/d; -L_0x17e3480/d .functor AND 1, L_0x17e80e0, L_0x17e8810, C4<1>, C4<1>; -L_0x17e3480 .delay (20000,20000,20000) L_0x17e3480/d; -L_0x17e83a0/d .functor AND 1, RS_0x7ff970b2ca88, L_0x17e84e0, C4<1>, C4<1>; -L_0x17e83a0 .delay (20000,20000,20000) L_0x17e83a0/d; -L_0x17e8a00/d .functor AND 1, L_0x17e3480, L_0x17e7c90, C4<1>, C4<1>; -L_0x17e8a00 .delay (20000,20000,20000) L_0x17e8a00/d; -L_0x17e8b40/d .functor AND 1, L_0x17e83a0, L_0x17e7c90, C4<1>, C4<1>; -L_0x17e8b40 .delay (20000,20000,20000) L_0x17e8b40/d; -L_0x17e8c40/d .functor OR 1, L_0x17e8a00, L_0x17e8b40, C4<0>, C4<0>; -L_0x17e8c40 .delay (20000,20000,20000) L_0x17e8c40/d; -v0x17dc7b0_0 .net "A", 3 0, v0x17dd890_0; 1 drivers -v0x17dc850_0 .alias "AddSubSLTSum", 3 0, v0x17dd910_0; -v0x17dc8d0_0 .net "B", 3 0, v0x17dda10_0; 1 drivers -RS_0x7ff970b2ec78 .resolv tri, L_0x17e3530, L_0x17e4bc0, L_0x17e6100, L_0x17e7700; -v0x17dc950_0 .net8 "CarryoutWire", 3 0, RS_0x7ff970b2ec78; 4 drivers -v0x17dc9d0_0 .net "Command", 2 0, v0x17dda90_0; 1 drivers -v0x17dca50_0 .net "Res0OF1", 0 0, L_0x17e83a0; 1 drivers -v0x17dcaf0_0 .net "Res1OF0", 0 0, L_0x17e3480; 1 drivers -v0x17dcb90_0 .alias "SLTflag", 0 0, v0x17ddc10_0; -v0x17dccb0_0 .net "SLTflag0", 0 0, L_0x17e8a00; 1 drivers -v0x17dcd50_0 .net "SLTflag1", 0 0, L_0x17e8b40; 1 drivers -v0x17dcdf0_0 .net "SLTon", 0 0, L_0x17e7c90; 1 drivers -v0x17dce90_0 .net *"_s40", 0 0, L_0x17e7d60; 1 drivers -v0x17dcf30_0 .net/s *"_s41", 0 0, C4<0>; 1 drivers -v0x17dcfd0_0 .net *"_s44", 0 0, L_0x17e8040; 1 drivers -v0x17dd0f0_0 .net *"_s46", 0 0, L_0x17e8210; 1 drivers -v0x17dd190_0 .net *"_s48", 0 0, L_0x17e82b0; 1 drivers -v0x17dd050_0 .net *"_s50", 0 0, L_0x17e8540; 1 drivers -v0x17dd2e0_0 .net *"_s52", 0 0, L_0x17e8810; 1 drivers -v0x17dd400_0 .net "carryin", 3 0, v0x17ddc90_0; 1 drivers -v0x17dd480_0 .alias "carryout", 0 0, v0x17ddd10_0; -v0x17dd360_0 .net "nAddSubSLTSum", 0 0, L_0x17e84e0; 1 drivers -v0x17dd5b0_0 .net "nOF", 0 0, L_0x17e80e0; 1 drivers -v0x17dd500_0 .alias "overflow", 0 0, v0x17ddd90_0; -v0x17dd740_0 .alias "subtract", 3 0, v0x17dde10_0; -L_0x17e33e0 .part/pv L_0x17e2f00, 1, 1, 4; -L_0x17e3530 .part/pv L_0x17e3280, 1, 1, 4; -L_0x17e3620 .part/pv L_0x17d1170, 1, 1, 4; -L_0x17e3750 .part v0x17dd890_0, 1, 1; -L_0x17e3900 .part v0x17dda10_0, 1, 1; -L_0x17e3ab0 .part RS_0x7ff970b2ec78, 0, 1; -L_0x17e4ad0 .part/pv L_0x17e4600, 2, 1, 4; -L_0x17e4bc0 .part/pv L_0x17e4970, 2, 1, 4; -L_0x17e4d00 .part/pv L_0x17e4330, 2, 1, 4; -L_0x17e4df0 .part v0x17dd890_0, 2, 1; -L_0x17e4ef0 .part v0x17dda10_0, 2, 1; -L_0x17e5020 .part RS_0x7ff970b2ec78, 1, 1; -L_0x17e6010 .part/pv L_0x17e5b60, 3, 1, 4; -L_0x17e6100 .part/pv L_0x17e5eb0, 3, 1, 4; -L_0x17e6270 .part/pv L_0x17e5890, 3, 1, 4; -L_0x17e6360 .part v0x17dd890_0, 3, 1; -L_0x17e6490 .part v0x17dda10_0, 3, 1; -L_0x17e65c0 .part RS_0x7ff970b2ec78, 2, 1; -L_0x17e7610 .part/pv L_0x17e7160, 0, 1, 4; -L_0x17e7700 .part/pv L_0x17e74b0, 0, 1, 4; -L_0x17e6660 .part/pv L_0x17e6e90, 0, 1, 4; -L_0x17e78f0 .part v0x17dd890_0, 0, 1; -L_0x17e77f0 .part v0x17dda10_0, 0, 1; -L_0x17e7ae0 .part RS_0x7ff970b2cab8, 0, 1; -L_0x17e7d60 .part RS_0x7ff970b2ec78, 3, 1; -L_0x17e8040 .part RS_0x7ff970b2ec78, 2, 1; -L_0x17e8210 .part v0x17dda90_0, 1, 1; -L_0x17e82b0 .part RS_0x7ff970b2cab8, 0, 1; -L_0x17e8540 .part RS_0x7ff970b2c6f8, 3, 1; -L_0x17e8810 .part RS_0x7ff970b2c6f8, 3, 1; -S_0x17db7a0 .scope module, "attempt2" "MiddleAddSubSLT" 2 229, 2 95, S_0x17d8120; - .timescale -9 -12; -L_0x17e6400/d .functor NOT 1, L_0x17e77f0, C4<0>, C4<0>, C4<0>; -L_0x17e6400 .delay (10000,10000,10000) L_0x17e6400/d; -L_0x17e6d30/d .functor NOT 1, L_0x17e6df0, C4<0>, C4<0>, C4<0>; -L_0x17e6d30 .delay (10000,10000,10000) L_0x17e6d30/d; -L_0x17e6e90/d .functor AND 1, L_0x17e6fd0, L_0x17e6d30, C4<1>, C4<1>; -L_0x17e6e90 .delay (20000,20000,20000) L_0x17e6e90/d; -L_0x17e7070/d .functor XOR 1, L_0x17e78f0, L_0x17e6ac0, C4<0>, C4<0>; -L_0x17e7070 .delay (40000,40000,40000) L_0x17e7070/d; -L_0x17e7160/d .functor XOR 1, L_0x17e7070, L_0x17e7ae0, C4<0>, C4<0>; -L_0x17e7160 .delay (40000,40000,40000) L_0x17e7160/d; -L_0x17e7250/d .functor AND 1, L_0x17e78f0, L_0x17e6ac0, C4<1>, C4<1>; -L_0x17e7250 .delay (20000,20000,20000) L_0x17e7250/d; -L_0x17e73c0/d .functor AND 1, L_0x17e7070, L_0x17e7ae0, C4<1>, C4<1>; -L_0x17e73c0 .delay (20000,20000,20000) L_0x17e73c0/d; -L_0x17e74b0/d .functor OR 1, L_0x17e7250, L_0x17e73c0, C4<0>, C4<0>; -L_0x17e74b0 .delay (20000,20000,20000) L_0x17e74b0/d; -v0x17dbe10_0 .net "A", 0 0, L_0x17e78f0; 1 drivers -v0x17dbed0_0 .net "AandB", 0 0, L_0x17e7250; 1 drivers -v0x17dbf70_0 .net "AddSubSLTSum", 0 0, L_0x17e7160; 1 drivers -v0x17dc010_0 .net "AxorB", 0 0, L_0x17e7070; 1 drivers -v0x17dc090_0 .net "B", 0 0, L_0x17e77f0; 1 drivers -v0x17dc140_0 .net "BornB", 0 0, L_0x17e6ac0; 1 drivers -v0x17dc200_0 .net "CINandAxorB", 0 0, L_0x17e73c0; 1 drivers -v0x17dc280_0 .alias "Command", 2 0, v0x17dc9d0_0; -v0x17dc300_0 .net *"_s3", 0 0, L_0x17e6df0; 1 drivers -v0x17dc380_0 .net *"_s5", 0 0, L_0x17e6fd0; 1 drivers -v0x17dc420_0 .net "carryin", 0 0, L_0x17e7ae0; 1 drivers -v0x17dc4c0_0 .net "carryout", 0 0, L_0x17e74b0; 1 drivers -v0x17dc560_0 .net "nB", 0 0, L_0x17e6400; 1 drivers -v0x17dc610_0 .net "nCmd2", 0 0, L_0x17e6d30; 1 drivers -v0x17dc710_0 .net "subtract", 0 0, L_0x17e6e90; 1 drivers -L_0x17e6c90 .part v0x17dda90_0, 0, 1; -L_0x17e6df0 .part v0x17dda90_0, 2, 1; -L_0x17e6fd0 .part v0x17dda90_0, 0, 1; -S_0x17db890 .scope module, "mux0" "TwoInMux" 2 111, 2 8, S_0x17db7a0; - .timescale -9 -12; -L_0x17e67e0/d .functor NOT 1, L_0x17e6c90, C4<0>, C4<0>, C4<0>; -L_0x17e67e0 .delay (10000,10000,10000) L_0x17e67e0/d; -L_0x17e68a0/d .functor AND 1, L_0x17e77f0, L_0x17e67e0, C4<1>, C4<1>; -L_0x17e68a0 .delay (20000,20000,20000) L_0x17e68a0/d; -L_0x17e69b0/d .functor AND 1, L_0x17e6400, L_0x17e6c90, C4<1>, C4<1>; -L_0x17e69b0 .delay (20000,20000,20000) L_0x17e69b0/d; -L_0x17e6ac0/d .functor OR 1, L_0x17e68a0, L_0x17e69b0, C4<0>, C4<0>; -L_0x17e6ac0 .delay (20000,20000,20000) L_0x17e6ac0/d; -v0x17db980_0 .net "S", 0 0, L_0x17e6c90; 1 drivers -v0x17dba40_0 .alias "in0", 0 0, v0x17dc090_0; -v0x17dbae0_0 .alias "in1", 0 0, v0x17dc560_0; -v0x17dbb80_0 .net "nS", 0 0, L_0x17e67e0; 1 drivers -v0x17dbc30_0 .net "out0", 0 0, L_0x17e68a0; 1 drivers -v0x17dbcd0_0 .net "out1", 0 0, L_0x17e69b0; 1 drivers -v0x17dbd70_0 .alias "outfinal", 0 0, v0x17dc140_0; -S_0x17da600 .scope generate, "addbits[1]" "addbits[1]" 2 234, 2 234, S_0x17d8120; - .timescale -9 -12; -P_0x17da018 .param/l "i" 2 234, +C4<01>; -S_0x17da770 .scope module, "attempt" "MiddleAddSubSLT" 2 236, 2 95, S_0x17da600; - .timescale -9 -12; -L_0x17e2240/d .functor NOT 1, L_0x17e3900, C4<0>, C4<0>, C4<0>; -L_0x17e2240 .delay (10000,10000,10000) L_0x17e2240/d; -L_0x17cae70/d .functor NOT 1, L_0x17d10d0, C4<0>, C4<0>, C4<0>; -L_0x17cae70 .delay (10000,10000,10000) L_0x17cae70/d; -L_0x17d1170/d .functor AND 1, L_0x17e2d70, L_0x17cae70, C4<1>, C4<1>; -L_0x17d1170 .delay (20000,20000,20000) L_0x17d1170/d; -L_0x17e2e10/d .functor XOR 1, L_0x17e3750, L_0x17e26a0, C4<0>, C4<0>; -L_0x17e2e10 .delay (40000,40000,40000) L_0x17e2e10/d; -L_0x17e2f00/d .functor XOR 1, L_0x17e2e10, L_0x17e3ab0, C4<0>, C4<0>; -L_0x17e2f00 .delay (40000,40000,40000) L_0x17e2f00/d; -L_0x17e2ff0/d .functor AND 1, L_0x17e3750, L_0x17e26a0, C4<1>, C4<1>; -L_0x17e2ff0 .delay (20000,20000,20000) L_0x17e2ff0/d; -L_0x17e3190/d .functor AND 1, L_0x17e2e10, L_0x17e3ab0, C4<1>, C4<1>; -L_0x17e3190 .delay (20000,20000,20000) L_0x17e3190/d; -L_0x17e3280/d .functor OR 1, L_0x17e2ff0, L_0x17e3190, C4<0>, C4<0>; -L_0x17e3280 .delay (20000,20000,20000) L_0x17e3280/d; -v0x17dae00_0 .net "A", 0 0, L_0x17e3750; 1 drivers -v0x17daec0_0 .net "AandB", 0 0, L_0x17e2ff0; 1 drivers -v0x17daf60_0 .net "AddSubSLTSum", 0 0, L_0x17e2f00; 1 drivers -v0x17db000_0 .net "AxorB", 0 0, L_0x17e2e10; 1 drivers -v0x17db080_0 .net "B", 0 0, L_0x17e3900; 1 drivers -v0x17db130_0 .net "BornB", 0 0, L_0x17e26a0; 1 drivers -v0x17db1f0_0 .net "CINandAxorB", 0 0, L_0x17e3190; 1 drivers -v0x17db270_0 .alias "Command", 2 0, v0x17dc9d0_0; -v0x17db2f0_0 .net *"_s3", 0 0, L_0x17d10d0; 1 drivers -v0x17db370_0 .net *"_s5", 0 0, L_0x17e2d70; 1 drivers -v0x17db410_0 .net "carryin", 0 0, L_0x17e3ab0; 1 drivers -v0x17db4b0_0 .net "carryout", 0 0, L_0x17e3280; 1 drivers -v0x17db550_0 .net "nB", 0 0, L_0x17e2240; 1 drivers -v0x17db600_0 .net "nCmd2", 0 0, L_0x17cae70; 1 drivers -v0x17db700_0 .net "subtract", 0 0, L_0x17d1170; 1 drivers -L_0x17e2870 .part v0x17dda90_0, 0, 1; -L_0x17d10d0 .part v0x17dda90_0, 2, 1; -L_0x17e2d70 .part v0x17dda90_0, 0, 1; -S_0x17da860 .scope module, "mux0" "TwoInMux" 2 111, 2 8, S_0x17da770; - .timescale -9 -12; -L_0x17e23c0/d .functor NOT 1, L_0x17e2870, C4<0>, C4<0>, C4<0>; -L_0x17e23c0 .delay (10000,10000,10000) L_0x17e23c0/d; -L_0x17e2480/d .functor AND 1, L_0x17e3900, L_0x17e23c0, C4<1>, C4<1>; -L_0x17e2480 .delay (20000,20000,20000) L_0x17e2480/d; -L_0x17e2590/d .functor AND 1, L_0x17e2240, L_0x17e2870, C4<1>, C4<1>; -L_0x17e2590 .delay (20000,20000,20000) L_0x17e2590/d; -L_0x17e26a0/d .functor OR 1, L_0x17e2480, L_0x17e2590, C4<0>, C4<0>; -L_0x17e26a0 .delay (20000,20000,20000) L_0x17e26a0/d; -v0x17da950_0 .net "S", 0 0, L_0x17e2870; 1 drivers -v0x17da9f0_0 .alias "in0", 0 0, v0x17db080_0; -v0x17daa90_0 .alias "in1", 0 0, v0x17db550_0; -v0x17dab30_0 .net "nS", 0 0, L_0x17e23c0; 1 drivers -v0x17dabe0_0 .net "out0", 0 0, L_0x17e2480; 1 drivers -v0x17dac80_0 .net "out1", 0 0, L_0x17e2590; 1 drivers -v0x17dad60_0 .alias "outfinal", 0 0, v0x17db130_0; -S_0x17d9460 .scope generate, "addbits[2]" "addbits[2]" 2 234, 2 234, S_0x17d8120; - .timescale -9 -12; -P_0x17d8e18 .param/l "i" 2 234, +C4<010>; -S_0x17d95d0 .scope module, "attempt" "MiddleAddSubSLT" 2 236, 2 95, S_0x17d9460; - .timescale -9 -12; -L_0x17d4ed0/d .functor NOT 1, L_0x17e4ef0, C4<0>, C4<0>, C4<0>; -L_0x17d4ed0 .delay (10000,10000,10000) L_0x17d4ed0/d; -L_0x17e41d0/d .functor NOT 1, L_0x17e4290, C4<0>, C4<0>, C4<0>; -L_0x17e41d0 .delay (10000,10000,10000) L_0x17e41d0/d; -L_0x17e4330/d .functor AND 1, L_0x17e4470, L_0x17e41d0, C4<1>, C4<1>; -L_0x17e4330 .delay (20000,20000,20000) L_0x17e4330/d; -L_0x17e4510/d .functor XOR 1, L_0x17e4df0, L_0x17e3f60, C4<0>, C4<0>; -L_0x17e4510 .delay (40000,40000,40000) L_0x17e4510/d; -L_0x17e4600/d .functor XOR 1, L_0x17e4510, L_0x17e5020, C4<0>, C4<0>; -L_0x17e4600 .delay (40000,40000,40000) L_0x17e4600/d; -L_0x17e46f0/d .functor AND 1, L_0x17e4df0, L_0x17e3f60, C4<1>, C4<1>; -L_0x17e46f0 .delay (20000,20000,20000) L_0x17e46f0/d; -L_0x17e4860/d .functor AND 1, L_0x17e4510, L_0x17e5020, C4<1>, C4<1>; -L_0x17e4860 .delay (20000,20000,20000) L_0x17e4860/d; -L_0x17e4970/d .functor OR 1, L_0x17e46f0, L_0x17e4860, C4<0>, C4<0>; -L_0x17e4970 .delay (20000,20000,20000) L_0x17e4970/d; -v0x17d9c60_0 .net "A", 0 0, L_0x17e4df0; 1 drivers -v0x17d9d20_0 .net "AandB", 0 0, L_0x17e46f0; 1 drivers -v0x17d9dc0_0 .net "AddSubSLTSum", 0 0, L_0x17e4600; 1 drivers -v0x17d9e60_0 .net "AxorB", 0 0, L_0x17e4510; 1 drivers -v0x17d9ee0_0 .net "B", 0 0, L_0x17e4ef0; 1 drivers -v0x17d9f90_0 .net "BornB", 0 0, L_0x17e3f60; 1 drivers -v0x17da050_0 .net "CINandAxorB", 0 0, L_0x17e4860; 1 drivers -v0x17da0d0_0 .alias "Command", 2 0, v0x17dc9d0_0; -v0x17da150_0 .net *"_s3", 0 0, L_0x17e4290; 1 drivers -v0x17da1d0_0 .net *"_s5", 0 0, L_0x17e4470; 1 drivers -v0x17da270_0 .net "carryin", 0 0, L_0x17e5020; 1 drivers -v0x17da310_0 .net "carryout", 0 0, L_0x17e4970; 1 drivers -v0x17da3b0_0 .net "nB", 0 0, L_0x17d4ed0; 1 drivers -v0x17da460_0 .net "nCmd2", 0 0, L_0x17e41d0; 1 drivers -v0x17da560_0 .net "subtract", 0 0, L_0x17e4330; 1 drivers -L_0x17e4130 .part v0x17dda90_0, 0, 1; -L_0x17e4290 .part v0x17dda90_0, 2, 1; -L_0x17e4470 .part v0x17dda90_0, 0, 1; -S_0x17d96c0 .scope module, "mux0" "TwoInMux" 2 111, 2 8, S_0x17d95d0; - .timescale -9 -12; -L_0x17e3c80/d .functor NOT 1, L_0x17e4130, C4<0>, C4<0>, C4<0>; -L_0x17e3c80 .delay (10000,10000,10000) L_0x17e3c80/d; -L_0x17e3d40/d .functor AND 1, L_0x17e4ef0, L_0x17e3c80, C4<1>, C4<1>; -L_0x17e3d40 .delay (20000,20000,20000) L_0x17e3d40/d; -L_0x17e3e50/d .functor AND 1, L_0x17d4ed0, L_0x17e4130, C4<1>, C4<1>; -L_0x17e3e50 .delay (20000,20000,20000) L_0x17e3e50/d; -L_0x17e3f60/d .functor OR 1, L_0x17e3d40, L_0x17e3e50, C4<0>, C4<0>; -L_0x17e3f60 .delay (20000,20000,20000) L_0x17e3f60/d; -v0x17d97b0_0 .net "S", 0 0, L_0x17e4130; 1 drivers -v0x17d9850_0 .alias "in0", 0 0, v0x17d9ee0_0; -v0x17d98f0_0 .alias "in1", 0 0, v0x17da3b0_0; -v0x17d9990_0 .net "nS", 0 0, L_0x17e3c80; 1 drivers -v0x17d9a40_0 .net "out0", 0 0, L_0x17e3d40; 1 drivers -v0x17d9ae0_0 .net "out1", 0 0, L_0x17e3e50; 1 drivers -v0x17d9bc0_0 .alias "outfinal", 0 0, v0x17d9f90_0; -S_0x17d8290 .scope generate, "addbits[3]" "addbits[3]" 2 234, 2 234, S_0x17d8120; - .timescale -9 -12; -P_0x17d8388 .param/l "i" 2 234, +C4<011>; -S_0x17d8400 .scope module, "attempt" "MiddleAddSubSLT" 2 236, 2 95, S_0x17d8290; - .timescale -9 -12; -L_0x17e4e90/d .functor NOT 1, L_0x17e6490, C4<0>, C4<0>, C4<0>; -L_0x17e4e90 .delay (10000,10000,10000) L_0x17e4e90/d; -L_0x17e5730/d .functor NOT 1, L_0x17e57f0, C4<0>, C4<0>, C4<0>; -L_0x17e5730 .delay (10000,10000,10000) L_0x17e5730/d; -L_0x17e5890/d .functor AND 1, L_0x17e59d0, L_0x17e5730, C4<1>, C4<1>; -L_0x17e5890 .delay (20000,20000,20000) L_0x17e5890/d; -L_0x17e5a70/d .functor XOR 1, L_0x17e6360, L_0x17e54c0, C4<0>, C4<0>; -L_0x17e5a70 .delay (40000,40000,40000) L_0x17e5a70/d; -L_0x17e5b60/d .functor XOR 1, L_0x17e5a70, L_0x17e65c0, C4<0>, C4<0>; -L_0x17e5b60 .delay (40000,40000,40000) L_0x17e5b60/d; -L_0x17e5c50/d .functor AND 1, L_0x17e6360, L_0x17e54c0, C4<1>, C4<1>; -L_0x17e5c50 .delay (20000,20000,20000) L_0x17e5c50/d; -L_0x17e5dc0/d .functor AND 1, L_0x17e5a70, L_0x17e65c0, C4<1>, C4<1>; -L_0x17e5dc0 .delay (20000,20000,20000) L_0x17e5dc0/d; -L_0x17e5eb0/d .functor OR 1, L_0x17e5c50, L_0x17e5dc0, C4<0>, C4<0>; -L_0x17e5eb0 .delay (20000,20000,20000) L_0x17e5eb0/d; -v0x17d8a60_0 .net "A", 0 0, L_0x17e6360; 1 drivers -v0x17d8b20_0 .net "AandB", 0 0, L_0x17e5c50; 1 drivers -v0x17d8bc0_0 .net "AddSubSLTSum", 0 0, L_0x17e5b60; 1 drivers -v0x17d8c60_0 .net "AxorB", 0 0, L_0x17e5a70; 1 drivers -v0x17d8ce0_0 .net "B", 0 0, L_0x17e6490; 1 drivers -v0x17d8d90_0 .net "BornB", 0 0, L_0x17e54c0; 1 drivers -v0x17d8e50_0 .net "CINandAxorB", 0 0, L_0x17e5dc0; 1 drivers -v0x17d8ed0_0 .alias "Command", 2 0, v0x17dc9d0_0; -v0x17d8f50_0 .net *"_s3", 0 0, L_0x17e57f0; 1 drivers -v0x17d8fd0_0 .net *"_s5", 0 0, L_0x17e59d0; 1 drivers -v0x17d90d0_0 .net "carryin", 0 0, L_0x17e65c0; 1 drivers -v0x17d9170_0 .net "carryout", 0 0, L_0x17e5eb0; 1 drivers -v0x17d9210_0 .net "nB", 0 0, L_0x17e4e90; 1 drivers -v0x17d92c0_0 .net "nCmd2", 0 0, L_0x17e5730; 1 drivers -v0x17d93c0_0 .net "subtract", 0 0, L_0x17e5890; 1 drivers -L_0x17e5690 .part v0x17dda90_0, 0, 1; -L_0x17e57f0 .part v0x17dda90_0, 2, 1; -L_0x17e59d0 .part v0x17dda90_0, 0, 1; -S_0x17d84f0 .scope module, "mux0" "TwoInMux" 2 111, 2 8, S_0x17d8400; - .timescale -9 -12; -L_0x17e5220/d .functor NOT 1, L_0x17e5690, C4<0>, C4<0>, C4<0>; -L_0x17e5220 .delay (10000,10000,10000) L_0x17e5220/d; -L_0x17e52a0/d .functor AND 1, L_0x17e6490, L_0x17e5220, C4<1>, C4<1>; -L_0x17e52a0 .delay (20000,20000,20000) L_0x17e52a0/d; -L_0x17e53b0/d .functor AND 1, L_0x17e4e90, L_0x17e5690, C4<1>, C4<1>; -L_0x17e53b0 .delay (20000,20000,20000) L_0x17e53b0/d; -L_0x17e54c0/d .functor OR 1, L_0x17e52a0, L_0x17e53b0, C4<0>, C4<0>; -L_0x17e54c0 .delay (20000,20000,20000) L_0x17e54c0/d; -v0x17d85e0_0 .net "S", 0 0, L_0x17e5690; 1 drivers -v0x17d8680_0 .alias "in0", 0 0, v0x17d8ce0_0; -v0x17d8720_0 .alias "in1", 0 0, v0x17d9210_0; -v0x17d87c0_0 .net "nS", 0 0, L_0x17e5220; 1 drivers -v0x17d8840_0 .net "out0", 0 0, L_0x17e52a0; 1 drivers -v0x17d88e0_0 .net "out1", 0 0, L_0x17e53b0; 1 drivers -v0x17d89c0_0 .alias "outfinal", 0 0, v0x17d8d90_0; -S_0x17d5060 .scope module, "trial1" "AndNand32" 3 27, 2 157, S_0x1782ed0; - .timescale -9 -12; -P_0x17d4a58 .param/l "size" 2 165, +C4<0100>; -v0x17d7f20_0 .alias "A", 3 0, v0x17dc7b0_0; -v0x17d7fa0_0 .alias "AndNandOut", 3 0, v0x17dd990_0; -v0x17d8020_0 .alias "B", 3 0, v0x17dc8d0_0; -v0x17d80a0_0 .alias "Command", 2 0, v0x17dc9d0_0; -L_0x17e9460 .part/pv L_0x17e9230, 1, 1, 4; -L_0x17e9590 .part v0x17dd890_0, 1, 1; -L_0x17e9630 .part v0x17dda10_0, 1, 1; -L_0x17e9e50 .part/pv L_0x17e9be0, 2, 1, 4; -L_0x17e9ef0 .part v0x17dd890_0, 2, 1; -L_0x17e9f90 .part v0x17dda10_0, 2, 1; -L_0x17ea8e0 .part/pv L_0x17ea670, 3, 1, 4; -L_0x17ea980 .part v0x17dd890_0, 3, 1; -L_0x17eaa70 .part v0x17dda10_0, 3, 1; -L_0x17eb340 .part/pv L_0x17eb0d0, 0, 1, 4; -L_0x17eb440 .part v0x17dd890_0, 0, 1; -L_0x17eb4e0 .part v0x17dda10_0, 0, 1; -S_0x17d74f0 .scope module, "attempt2" "AndNand" 2 170, 2 53, S_0x17d5060; - .timescale -9 -12; -L_0x17eab60/d .functor NAND 1, L_0x17eb440, L_0x17eb4e0, C4<1>, C4<1>; -L_0x17eab60 .delay (10000,10000,10000) L_0x17eab60/d; -L_0x17eac80/d .functor NOT 1, L_0x17eab60, C4<0>, C4<0>, C4<0>; -L_0x17eac80 .delay (10000,10000,10000) L_0x17eac80/d; -v0x17d7b10_0 .net "A", 0 0, L_0x17eb440; 1 drivers -v0x17d7bd0_0 .net "AandB", 0 0, L_0x17eac80; 1 drivers -v0x17d7c50_0 .net "AnandB", 0 0, L_0x17eab60; 1 drivers -v0x17d7d00_0 .net "AndNandOut", 0 0, L_0x17eb0d0; 1 drivers -v0x17d7de0_0 .net "B", 0 0, L_0x17eb4e0; 1 drivers -v0x17d7e60_0 .alias "Command", 2 0, v0x17dc9d0_0; -L_0x17eb2a0 .part v0x17dda90_0, 0, 1; -S_0x17d75e0 .scope module, "potato" "TwoInMux" 2 66, 2 8, S_0x17d74f0; - .timescale -9 -12; -L_0x17eadb0/d .functor NOT 1, L_0x17eb2a0, C4<0>, C4<0>, C4<0>; -L_0x17eadb0 .delay (10000,10000,10000) L_0x17eadb0/d; -L_0x17eae70/d .functor AND 1, L_0x17eac80, L_0x17eadb0, C4<1>, C4<1>; -L_0x17eae70 .delay (20000,20000,20000) L_0x17eae70/d; -L_0x17eaf80/d .functor AND 1, L_0x17eab60, L_0x17eb2a0, C4<1>, C4<1>; -L_0x17eaf80 .delay (20000,20000,20000) L_0x17eaf80/d; -L_0x17eb0d0/d .functor OR 1, L_0x17eae70, L_0x17eaf80, C4<0>, C4<0>; -L_0x17eb0d0 .delay (20000,20000,20000) L_0x17eb0d0/d; -v0x17d76d0_0 .net "S", 0 0, L_0x17eb2a0; 1 drivers -v0x17d7750_0 .alias "in0", 0 0, v0x17d7bd0_0; -v0x17d77d0_0 .alias "in1", 0 0, v0x17d7c50_0; -v0x17d7870_0 .net "nS", 0 0, L_0x17eadb0; 1 drivers -v0x17d78f0_0 .net "out0", 0 0, L_0x17eae70; 1 drivers -v0x17d7990_0 .net "out1", 0 0, L_0x17eaf80; 1 drivers -v0x17d7a70_0 .alias "outfinal", 0 0, v0x17d7d00_0; -S_0x17d6930 .scope generate, "andbits[1]" "andbits[1]" 2 173, 2 173, S_0x17d5060; - .timescale -9 -12; -P_0x17d6a28 .param/l "i" 2 173, +C4<01>; -S_0x17d6aa0 .scope module, "attempt" "AndNand" 2 175, 2 53, S_0x17d6930; - .timescale -9 -12; -L_0x17e8e40/d .functor NAND 1, L_0x17e9590, L_0x17e9630, C4<1>, C4<1>; -L_0x17e8e40 .delay (10000,10000,10000) L_0x17e8e40/d; -L_0x17e8f00/d .functor NOT 1, L_0x17e8e40, C4<0>, C4<0>, C4<0>; -L_0x17e8f00 .delay (10000,10000,10000) L_0x17e8f00/d; -v0x17d70e0_0 .net "A", 0 0, L_0x17e9590; 1 drivers -v0x17d71a0_0 .net "AandB", 0 0, L_0x17e8f00; 1 drivers -v0x17d7220_0 .net "AnandB", 0 0, L_0x17e8e40; 1 drivers -v0x17d72d0_0 .net "AndNandOut", 0 0, L_0x17e9230; 1 drivers -v0x17d73b0_0 .net "B", 0 0, L_0x17e9630; 1 drivers -v0x17d7430_0 .alias "Command", 2 0, v0x17dc9d0_0; -L_0x17e93c0 .part v0x17dda90_0, 0, 1; -S_0x17d6b90 .scope module, "potato" "TwoInMux" 2 66, 2 8, S_0x17d6aa0; - .timescale -9 -12; -L_0x17e61f0/d .functor NOT 1, L_0x17e93c0, C4<0>, C4<0>, C4<0>; -L_0x17e61f0 .delay (10000,10000,10000) L_0x17e61f0/d; -L_0x17e9010/d .functor AND 1, L_0x17e8f00, L_0x17e61f0, C4<1>, C4<1>; -L_0x17e9010 .delay (20000,20000,20000) L_0x17e9010/d; -L_0x17e9100/d .functor AND 1, L_0x17e8e40, L_0x17e93c0, C4<1>, C4<1>; -L_0x17e9100 .delay (20000,20000,20000) L_0x17e9100/d; -L_0x17e9230/d .functor OR 1, L_0x17e9010, L_0x17e9100, C4<0>, C4<0>; -L_0x17e9230 .delay (20000,20000,20000) L_0x17e9230/d; -v0x17d6c80_0 .net "S", 0 0, L_0x17e93c0; 1 drivers -v0x17d6d00_0 .alias "in0", 0 0, v0x17d71a0_0; -v0x17d6da0_0 .alias "in1", 0 0, v0x17d7220_0; -v0x17d6e40_0 .net "nS", 0 0, L_0x17e61f0; 1 drivers -v0x17d6ec0_0 .net "out0", 0 0, L_0x17e9010; 1 drivers -v0x17d6f60_0 .net "out1", 0 0, L_0x17e9100; 1 drivers -v0x17d7040_0 .alias "outfinal", 0 0, v0x17d72d0_0; -S_0x17d5d70 .scope generate, "andbits[2]" "andbits[2]" 2 173, 2 173, S_0x17d5060; - .timescale -9 -12; -P_0x17d5e68 .param/l "i" 2 173, +C4<010>; -S_0x17d5ee0 .scope module, "attempt" "AndNand" 2 175, 2 53, S_0x17d5d70; - .timescale -9 -12; -L_0x17e96d0/d .functor NAND 1, L_0x17e9ef0, L_0x17e9f90, C4<1>, C4<1>; -L_0x17e96d0 .delay (10000,10000,10000) L_0x17e96d0/d; -L_0x17e9810/d .functor NOT 1, L_0x17e96d0, C4<0>, C4<0>, C4<0>; -L_0x17e9810 .delay (10000,10000,10000) L_0x17e9810/d; -v0x17d6520_0 .net "A", 0 0, L_0x17e9ef0; 1 drivers -v0x17d65e0_0 .net "AandB", 0 0, L_0x17e9810; 1 drivers -v0x17d6660_0 .net "AnandB", 0 0, L_0x17e96d0; 1 drivers -v0x17d6710_0 .net "AndNandOut", 0 0, L_0x17e9be0; 1 drivers -v0x17d67f0_0 .net "B", 0 0, L_0x17e9f90; 1 drivers -v0x17d6870_0 .alias "Command", 2 0, v0x17dc9d0_0; -L_0x17e9db0 .part v0x17dda90_0, 0, 1; -S_0x17d5fd0 .scope module, "potato" "TwoInMux" 2 66, 2 8, S_0x17d5ee0; - .timescale -9 -12; -L_0x17e9900/d .functor NOT 1, L_0x17e9db0, C4<0>, C4<0>, C4<0>; -L_0x17e9900 .delay (10000,10000,10000) L_0x17e9900/d; -L_0x17e99a0/d .functor AND 1, L_0x17e9810, L_0x17e9900, C4<1>, C4<1>; -L_0x17e99a0 .delay (20000,20000,20000) L_0x17e99a0/d; -L_0x17e9a90/d .functor AND 1, L_0x17e96d0, L_0x17e9db0, C4<1>, C4<1>; -L_0x17e9a90 .delay (20000,20000,20000) L_0x17e9a90/d; -L_0x17e9be0/d .functor OR 1, L_0x17e99a0, L_0x17e9a90, C4<0>, C4<0>; -L_0x17e9be0 .delay (20000,20000,20000) L_0x17e9be0/d; -v0x17d60c0_0 .net "S", 0 0, L_0x17e9db0; 1 drivers -v0x17d6140_0 .alias "in0", 0 0, v0x17d65e0_0; -v0x17d61e0_0 .alias "in1", 0 0, v0x17d6660_0; -v0x17d6280_0 .net "nS", 0 0, L_0x17e9900; 1 drivers -v0x17d6300_0 .net "out0", 0 0, L_0x17e99a0; 1 drivers -v0x17d63a0_0 .net "out1", 0 0, L_0x17e9a90; 1 drivers -v0x17d6480_0 .alias "outfinal", 0 0, v0x17d6710_0; -S_0x17d5190 .scope generate, "andbits[3]" "andbits[3]" 2 173, 2 173, S_0x17d5060; - .timescale -9 -12; -P_0x17d5288 .param/l "i" 2 173, +C4<011>; -S_0x17d5300 .scope module, "attempt" "AndNand" 2 175, 2 53, S_0x17d5190; - .timescale -9 -12; -L_0x17ea0c0/d .functor NAND 1, L_0x17ea980, L_0x17eaa70, C4<1>, C4<1>; -L_0x17ea0c0 .delay (10000,10000,10000) L_0x17ea0c0/d; -L_0x17ea220/d .functor NOT 1, L_0x17ea0c0, C4<0>, C4<0>, C4<0>; -L_0x17ea220 .delay (10000,10000,10000) L_0x17ea220/d; -v0x17d5960_0 .net "A", 0 0, L_0x17ea980; 1 drivers -v0x17d5a20_0 .net "AandB", 0 0, L_0x17ea220; 1 drivers -v0x17d5aa0_0 .net "AnandB", 0 0, L_0x17ea0c0; 1 drivers -v0x17d5b50_0 .net "AndNandOut", 0 0, L_0x17ea670; 1 drivers -v0x17d5c30_0 .net "B", 0 0, L_0x17eaa70; 1 drivers -v0x17d5cb0_0 .alias "Command", 2 0, v0x17dc9d0_0; -L_0x17ea840 .part v0x17dda90_0, 0, 1; -S_0x17d53f0 .scope module, "potato" "TwoInMux" 2 66, 2 8, S_0x17d5300; - .timescale -9 -12; -L_0x17ea350/d .functor NOT 1, L_0x17ea840, C4<0>, C4<0>, C4<0>; -L_0x17ea350 .delay (10000,10000,10000) L_0x17ea350/d; -L_0x17ea410/d .functor AND 1, L_0x17ea220, L_0x17ea350, C4<1>, C4<1>; -L_0x17ea410 .delay (20000,20000,20000) L_0x17ea410/d; -L_0x17ea520/d .functor AND 1, L_0x17ea0c0, L_0x17ea840, C4<1>, C4<1>; -L_0x17ea520 .delay (20000,20000,20000) L_0x17ea520/d; -L_0x17ea670/d .functor OR 1, L_0x17ea410, L_0x17ea520, C4<0>, C4<0>; -L_0x17ea670 .delay (20000,20000,20000) L_0x17ea670/d; -v0x17d54e0_0 .net "S", 0 0, L_0x17ea840; 1 drivers -v0x17d5580_0 .alias "in0", 0 0, v0x17d5a20_0; -v0x17d5620_0 .alias "in1", 0 0, v0x17d5aa0_0; -v0x17d56c0_0 .net "nS", 0 0, L_0x17ea350; 1 drivers -v0x17d5740_0 .net "out0", 0 0, L_0x17ea410; 1 drivers -v0x17d57e0_0 .net "out1", 0 0, L_0x17ea520; 1 drivers -v0x17d58c0_0 .alias "outfinal", 0 0, v0x17d5b50_0; -S_0x17cfd60 .scope module, "trial2" "OrNorXor32" 3 29, 2 180, S_0x1782ed0; - .timescale -9 -12; -P_0x17cdeb8 .param/l "size" 2 187, +C4<0100>; -v0x17d4d40_0 .alias "A", 3 0, v0x17dc7b0_0; -v0x17d4e50_0 .alias "B", 3 0, v0x17dc8d0_0; -v0x17d4f60_0 .alias "Command", 2 0, v0x17dc9d0_0; -v0x17d4fe0_0 .alias "OrNorXorOut", 3 0, v0x17ddb90_0; -L_0x17ec700 .part/pv L_0x17ec490, 1, 1, 4; -L_0x17ec830 .part v0x17dd890_0, 1, 1; -L_0x17e37f0 .part v0x17dda10_0, 1, 1; -L_0x17edc60 .part/pv L_0x17ed9f0, 2, 1, 4; -L_0x17edd00 .part v0x17dd890_0, 2, 1; -L_0x17edda0 .part v0x17dda10_0, 2, 1; -L_0x17eef60 .part/pv L_0x17eecf0, 3, 1, 4; -L_0x17ef000 .part v0x17dd890_0, 3, 1; -L_0x17ef0a0 .part v0x17dda10_0, 3, 1; -L_0x17f0250 .part/pv L_0x17effe0, 0, 1, 4; -L_0x17f0350 .part v0x17dd890_0, 0, 1; -L_0x17f03f0 .part v0x17dda10_0, 0, 1; -S_0x17d3b00 .scope module, "attempt2" "OrNorXor" 2 195, 2 70, S_0x17cfd60; - .timescale -9 -12; -L_0x17ef140/d .functor NOR 1, L_0x17f0350, L_0x17f03f0, C4<0>, C4<0>; -L_0x17ef140 .delay (10000,10000,10000) L_0x17ef140/d; -L_0x17ef240/d .functor NOT 1, L_0x17ef140, C4<0>, C4<0>, C4<0>; -L_0x17ef240 .delay (10000,10000,10000) L_0x17ef240/d; -L_0x17ef370/d .functor NAND 1, L_0x17f0350, L_0x17f03f0, C4<1>, C4<1>; -L_0x17ef370 .delay (10000,10000,10000) L_0x17ef370/d; -L_0x17ef4d0/d .functor NAND 1, L_0x17ef370, L_0x17ef240, C4<1>, C4<1>; -L_0x17ef4d0 .delay (10000,10000,10000) L_0x17ef4d0/d; -L_0x17ef5e0/d .functor NOT 1, L_0x17ef4d0, C4<0>, C4<0>, C4<0>; -L_0x17ef5e0 .delay (10000,10000,10000) L_0x17ef5e0/d; -v0x17d4650_0 .net "A", 0 0, L_0x17f0350; 1 drivers -v0x17d46f0_0 .net "AnandB", 0 0, L_0x17ef370; 1 drivers -v0x17d4790_0 .net "AnorB", 0 0, L_0x17ef140; 1 drivers -v0x17d4840_0 .net "AorB", 0 0, L_0x17ef240; 1 drivers -v0x17d4920_0 .net "AxorB", 0 0, L_0x17ef5e0; 1 drivers -v0x17d49d0_0 .net "B", 0 0, L_0x17f03f0; 1 drivers -v0x17d4a90_0 .alias "Command", 2 0, v0x17dc9d0_0; -v0x17d4b10_0 .net "OrNorXorOut", 0 0, L_0x17effe0; 1 drivers -v0x17d4b90_0 .net "XorNor", 0 0, L_0x17efa60; 1 drivers -v0x17d4c60_0 .net "nXor", 0 0, L_0x17ef4d0; 1 drivers -L_0x17efbe0 .part v0x17dda90_0, 2, 1; -L_0x17f01b0 .part v0x17dda90_0, 0, 1; -S_0x17d40e0 .scope module, "mux0" "TwoInMux" 2 89, 2 8, S_0x17d3b00; - .timescale -9 -12; -L_0x17ef740/d .functor NOT 1, L_0x17efbe0, C4<0>, C4<0>, C4<0>; -L_0x17ef740 .delay (10000,10000,10000) L_0x17ef740/d; -L_0x17ef800/d .functor AND 1, L_0x17ef5e0, L_0x17ef740, C4<1>, C4<1>; -L_0x17ef800 .delay (20000,20000,20000) L_0x17ef800/d; -L_0x17ef910/d .functor AND 1, L_0x17ef140, L_0x17efbe0, C4<1>, C4<1>; -L_0x17ef910 .delay (20000,20000,20000) L_0x17ef910/d; -L_0x17efa60/d .functor OR 1, L_0x17ef800, L_0x17ef910, C4<0>, C4<0>; -L_0x17efa60 .delay (20000,20000,20000) L_0x17efa60/d; -v0x17d41d0_0 .net "S", 0 0, L_0x17efbe0; 1 drivers -v0x17d4290_0 .alias "in0", 0 0, v0x17d4920_0; -v0x17d4330_0 .alias "in1", 0 0, v0x17d4790_0; -v0x17d43d0_0 .net "nS", 0 0, L_0x17ef740; 1 drivers -v0x17d4450_0 .net "out0", 0 0, L_0x17ef800; 1 drivers -v0x17d44f0_0 .net "out1", 0 0, L_0x17ef910; 1 drivers -v0x17d45d0_0 .alias "outfinal", 0 0, v0x17d4b90_0; -S_0x17d3bf0 .scope module, "mux1" "TwoInMux" 2 90, 2 8, S_0x17d3b00; - .timescale -9 -12; -L_0x17efc80/d .functor NOT 1, L_0x17f01b0, C4<0>, C4<0>, C4<0>; -L_0x17efc80 .delay (10000,10000,10000) L_0x17efc80/d; -L_0x17efd40/d .functor AND 1, L_0x17efa60, L_0x17efc80, C4<1>, C4<1>; -L_0x17efd40 .delay (20000,20000,20000) L_0x17efd40/d; -L_0x17efe90/d .functor AND 1, L_0x17ef240, L_0x17f01b0, C4<1>, C4<1>; -L_0x17efe90 .delay (20000,20000,20000) L_0x17efe90/d; -L_0x17effe0/d .functor OR 1, L_0x17efd40, L_0x17efe90, C4<0>, C4<0>; -L_0x17effe0 .delay (20000,20000,20000) L_0x17effe0/d; -v0x17d3ce0_0 .net "S", 0 0, L_0x17f01b0; 1 drivers -v0x17d3d60_0 .alias "in0", 0 0, v0x17d4b90_0; -v0x17d3de0_0 .alias "in1", 0 0, v0x17d4840_0; -v0x17d3e80_0 .net "nS", 0 0, L_0x17efc80; 1 drivers -v0x17d3f00_0 .net "out0", 0 0, L_0x17efd40; 1 drivers -v0x17d3fa0_0 .net "out1", 0 0, L_0x17efe90; 1 drivers -v0x17d4040_0 .alias "outfinal", 0 0, v0x17d4b10_0; -S_0x17d2730 .scope generate, "orbits[1]" "orbits[1]" 2 199, 2 199, S_0x17cfd60; - .timescale -9 -12; -P_0x17d2448 .param/l "i" 2 199, +C4<01>; -S_0x17d2860 .scope module, "attempt" "OrNorXor" 2 201, 2 70, S_0x17d2730; - .timescale -9 -12; -L_0x17eb3e0/d .functor NOR 1, L_0x17ec830, L_0x17e37f0, C4<0>, C4<0>; -L_0x17eb3e0 .delay (10000,10000,10000) L_0x17eb3e0/d; -L_0x17eb6f0/d .functor NOT 1, L_0x17eb3e0, C4<0>, C4<0>, C4<0>; -L_0x17eb6f0 .delay (10000,10000,10000) L_0x17eb6f0/d; -L_0x17eb820/d .functor NAND 1, L_0x17ec830, L_0x17e37f0, C4<1>, C4<1>; -L_0x17eb820 .delay (10000,10000,10000) L_0x17eb820/d; -L_0x17eb980/d .functor NAND 1, L_0x17eb820, L_0x17eb6f0, C4<1>, C4<1>; -L_0x17eb980 .delay (10000,10000,10000) L_0x17eb980/d; -L_0x17eba90/d .functor NOT 1, L_0x17eb980, C4<0>, C4<0>, C4<0>; -L_0x17eba90 .delay (10000,10000,10000) L_0x17eba90/d; -v0x17d3410_0 .net "A", 0 0, L_0x17ec830; 1 drivers -v0x17d34b0_0 .net "AnandB", 0 0, L_0x17eb820; 1 drivers -v0x17d3550_0 .net "AnorB", 0 0, L_0x17eb3e0; 1 drivers -v0x17d3600_0 .net "AorB", 0 0, L_0x17eb6f0; 1 drivers -v0x17d36e0_0 .net "AxorB", 0 0, L_0x17eba90; 1 drivers -v0x17d3790_0 .net "B", 0 0, L_0x17e37f0; 1 drivers -v0x17d3850_0 .alias "Command", 2 0, v0x17dc9d0_0; -v0x17d38d0_0 .net "OrNorXorOut", 0 0, L_0x17ec490; 1 drivers -v0x17d3950_0 .net "XorNor", 0 0, L_0x17ebf10; 1 drivers -v0x17d3a20_0 .net "nXor", 0 0, L_0x17eb980; 1 drivers -L_0x17ec090 .part v0x17dda90_0, 2, 1; -L_0x17ec660 .part v0x17dda90_0, 0, 1; -S_0x17d2ea0 .scope module, "mux0" "TwoInMux" 2 89, 2 8, S_0x17d2860; - .timescale -9 -12; -L_0x17ebbf0/d .functor NOT 1, L_0x17ec090, C4<0>, C4<0>, C4<0>; -L_0x17ebbf0 .delay (10000,10000,10000) L_0x17ebbf0/d; -L_0x17ebcb0/d .functor AND 1, L_0x17eba90, L_0x17ebbf0, C4<1>, C4<1>; -L_0x17ebcb0 .delay (20000,20000,20000) L_0x17ebcb0/d; -L_0x17ebdc0/d .functor AND 1, L_0x17eb3e0, L_0x17ec090, C4<1>, C4<1>; -L_0x17ebdc0 .delay (20000,20000,20000) L_0x17ebdc0/d; -L_0x17ebf10/d .functor OR 1, L_0x17ebcb0, L_0x17ebdc0, C4<0>, C4<0>; -L_0x17ebf10 .delay (20000,20000,20000) L_0x17ebf10/d; -v0x17d2f90_0 .net "S", 0 0, L_0x17ec090; 1 drivers -v0x17d3050_0 .alias "in0", 0 0, v0x17d36e0_0; -v0x17d30f0_0 .alias "in1", 0 0, v0x17d3550_0; -v0x17d3190_0 .net "nS", 0 0, L_0x17ebbf0; 1 drivers -v0x17d3210_0 .net "out0", 0 0, L_0x17ebcb0; 1 drivers -v0x17d32b0_0 .net "out1", 0 0, L_0x17ebdc0; 1 drivers -v0x17d3390_0 .alias "outfinal", 0 0, v0x17d3950_0; -S_0x17d2950 .scope module, "mux1" "TwoInMux" 2 90, 2 8, S_0x17d2860; - .timescale -9 -12; -L_0x17ec130/d .functor NOT 1, L_0x17ec660, C4<0>, C4<0>, C4<0>; -L_0x17ec130 .delay (10000,10000,10000) L_0x17ec130/d; -L_0x17ec1f0/d .functor AND 1, L_0x17ebf10, L_0x17ec130, C4<1>, C4<1>; -L_0x17ec1f0 .delay (20000,20000,20000) L_0x17ec1f0/d; -L_0x17ec340/d .functor AND 1, L_0x17eb6f0, L_0x17ec660, C4<1>, C4<1>; -L_0x17ec340 .delay (20000,20000,20000) L_0x17ec340/d; -L_0x17ec490/d .functor OR 1, L_0x17ec1f0, L_0x17ec340, C4<0>, C4<0>; -L_0x17ec490 .delay (20000,20000,20000) L_0x17ec490/d; -v0x17d2a40_0 .net "S", 0 0, L_0x17ec660; 1 drivers -v0x17d2ac0_0 .alias "in0", 0 0, v0x17d3950_0; -v0x17d2b60_0 .alias "in1", 0 0, v0x17d3600_0; -v0x17d2c00_0 .net "nS", 0 0, L_0x17ec130; 1 drivers -v0x17d2c80_0 .net "out0", 0 0, L_0x17ec1f0; 1 drivers -v0x17d2d20_0 .net "out1", 0 0, L_0x17ec340; 1 drivers -v0x17d2e00_0 .alias "outfinal", 0 0, v0x17d38d0_0; -S_0x17d1360 .scope generate, "orbits[2]" "orbits[2]" 2 199, 2 199, S_0x17cfd60; - .timescale -9 -12; -P_0x17d0fc8 .param/l "i" 2 199, +C4<010>; -S_0x17d1490 .scope module, "attempt" "OrNorXor" 2 201, 2 70, S_0x17d1360; - .timescale -9 -12; -L_0x17e3890/d .functor NOR 1, L_0x17edd00, L_0x17edda0, C4<0>, C4<0>; -L_0x17e3890 .delay (10000,10000,10000) L_0x17e3890/d; -L_0x17e3a00/d .functor NOT 1, L_0x17e3890, C4<0>, C4<0>, C4<0>; -L_0x17e3a00 .delay (10000,10000,10000) L_0x17e3a00/d; -L_0x17ecd80/d .functor NAND 1, L_0x17edd00, L_0x17edda0, C4<1>, C4<1>; -L_0x17ecd80 .delay (10000,10000,10000) L_0x17ecd80/d; -L_0x17ecee0/d .functor NAND 1, L_0x17ecd80, L_0x17e3a00, C4<1>, C4<1>; -L_0x17ecee0 .delay (10000,10000,10000) L_0x17ecee0/d; -L_0x17ecff0/d .functor NOT 1, L_0x17ecee0, C4<0>, C4<0>, C4<0>; -L_0x17ecff0 .delay (10000,10000,10000) L_0x17ecff0/d; -v0x17d2040_0 .net "A", 0 0, L_0x17edd00; 1 drivers -v0x17d20e0_0 .net "AnandB", 0 0, L_0x17ecd80; 1 drivers -v0x17d2180_0 .net "AnorB", 0 0, L_0x17e3890; 1 drivers -v0x17d2230_0 .net "AorB", 0 0, L_0x17e3a00; 1 drivers -v0x17d2310_0 .net "AxorB", 0 0, L_0x17ecff0; 1 drivers -v0x17d23c0_0 .net "B", 0 0, L_0x17edda0; 1 drivers -v0x17d2480_0 .alias "Command", 2 0, v0x17dc9d0_0; -v0x17d2500_0 .net "OrNorXorOut", 0 0, L_0x17ed9f0; 1 drivers -v0x17d2580_0 .net "XorNor", 0 0, L_0x17ed470; 1 drivers -v0x17d2650_0 .net "nXor", 0 0, L_0x17ecee0; 1 drivers -L_0x17ed5f0 .part v0x17dda90_0, 2, 1; -L_0x17edbc0 .part v0x17dda90_0, 0, 1; -S_0x17d1ad0 .scope module, "mux0" "TwoInMux" 2 89, 2 8, S_0x17d1490; - .timescale -9 -12; -L_0x17ed150/d .functor NOT 1, L_0x17ed5f0, C4<0>, C4<0>, C4<0>; -L_0x17ed150 .delay (10000,10000,10000) L_0x17ed150/d; -L_0x17ed210/d .functor AND 1, L_0x17ecff0, L_0x17ed150, C4<1>, C4<1>; -L_0x17ed210 .delay (20000,20000,20000) L_0x17ed210/d; -L_0x17ed320/d .functor AND 1, L_0x17e3890, L_0x17ed5f0, C4<1>, C4<1>; -L_0x17ed320 .delay (20000,20000,20000) L_0x17ed320/d; -L_0x17ed470/d .functor OR 1, L_0x17ed210, L_0x17ed320, C4<0>, C4<0>; -L_0x17ed470 .delay (20000,20000,20000) L_0x17ed470/d; -v0x17d1bc0_0 .net "S", 0 0, L_0x17ed5f0; 1 drivers -v0x17d1c80_0 .alias "in0", 0 0, v0x17d2310_0; -v0x17d1d20_0 .alias "in1", 0 0, v0x17d2180_0; -v0x17d1dc0_0 .net "nS", 0 0, L_0x17ed150; 1 drivers -v0x17d1e40_0 .net "out0", 0 0, L_0x17ed210; 1 drivers -v0x17d1ee0_0 .net "out1", 0 0, L_0x17ed320; 1 drivers -v0x17d1fc0_0 .alias "outfinal", 0 0, v0x17d2580_0; -S_0x17d1580 .scope module, "mux1" "TwoInMux" 2 90, 2 8, S_0x17d1490; - .timescale -9 -12; -L_0x17ed690/d .functor NOT 1, L_0x17edbc0, C4<0>, C4<0>, C4<0>; -L_0x17ed690 .delay (10000,10000,10000) L_0x17ed690/d; -L_0x17ed750/d .functor AND 1, L_0x17ed470, L_0x17ed690, C4<1>, C4<1>; -L_0x17ed750 .delay (20000,20000,20000) L_0x17ed750/d; -L_0x17ed8a0/d .functor AND 1, L_0x17e3a00, L_0x17edbc0, C4<1>, C4<1>; -L_0x17ed8a0 .delay (20000,20000,20000) L_0x17ed8a0/d; -L_0x17ed9f0/d .functor OR 1, L_0x17ed750, L_0x17ed8a0, C4<0>, C4<0>; -L_0x17ed9f0 .delay (20000,20000,20000) L_0x17ed9f0/d; -v0x17d1670_0 .net "S", 0 0, L_0x17edbc0; 1 drivers -v0x17d16f0_0 .alias "in0", 0 0, v0x17d2580_0; -v0x17d1790_0 .alias "in1", 0 0, v0x17d2230_0; -v0x17d1830_0 .net "nS", 0 0, L_0x17ed690; 1 drivers -v0x17d18b0_0 .net "out0", 0 0, L_0x17ed750; 1 drivers -v0x17d1950_0 .net "out1", 0 0, L_0x17ed8a0; 1 drivers -v0x17d1a30_0 .alias "outfinal", 0 0, v0x17d2500_0; -S_0x17cfe90 .scope generate, "orbits[3]" "orbits[3]" 2 199, 2 199, S_0x17cfd60; - .timescale -9 -12; -P_0x17cff88 .param/l "i" 2 199, +C4<011>; -S_0x17d0000 .scope module, "attempt" "OrNorXor" 2 201, 2 70, S_0x17cfe90; - .timescale -9 -12; -L_0x17ede80/d .functor NOR 1, L_0x17ef000, L_0x17ef0a0, C4<0>, C4<0>; -L_0x17ede80 .delay (10000,10000,10000) L_0x17ede80/d; -L_0x17edf70/d .functor NOT 1, L_0x17ede80, C4<0>, C4<0>, C4<0>; -L_0x17edf70 .delay (10000,10000,10000) L_0x17edf70/d; -L_0x17ee080/d .functor NAND 1, L_0x17ef000, L_0x17ef0a0, C4<1>, C4<1>; -L_0x17ee080 .delay (10000,10000,10000) L_0x17ee080/d; -L_0x17ee1e0/d .functor NAND 1, L_0x17ee080, L_0x17edf70, C4<1>, C4<1>; -L_0x17ee1e0 .delay (10000,10000,10000) L_0x17ee1e0/d; -L_0x17ee2f0/d .functor NOT 1, L_0x17ee1e0, C4<0>, C4<0>, C4<0>; -L_0x17ee2f0 .delay (10000,10000,10000) L_0x17ee2f0/d; -v0x17d0bc0_0 .net "A", 0 0, L_0x17ef000; 1 drivers -v0x17d0c60_0 .net "AnandB", 0 0, L_0x17ee080; 1 drivers -v0x17d0d00_0 .net "AnorB", 0 0, L_0x17ede80; 1 drivers -v0x17d0db0_0 .net "AorB", 0 0, L_0x17edf70; 1 drivers -v0x17d0e90_0 .net "AxorB", 0 0, L_0x17ee2f0; 1 drivers -v0x17d0f40_0 .net "B", 0 0, L_0x17ef0a0; 1 drivers -v0x17d1000_0 .alias "Command", 2 0, v0x17dc9d0_0; -v0x17c9a50_0 .net "OrNorXorOut", 0 0, L_0x17eecf0; 1 drivers -v0x17c9ad0_0 .net "XorNor", 0 0, L_0x17ee770; 1 drivers -v0x17d12e0_0 .net "nXor", 0 0, L_0x17ee1e0; 1 drivers -L_0x17ee8f0 .part v0x17dda90_0, 2, 1; -L_0x17eeec0 .part v0x17dda90_0, 0, 1; -S_0x17d0650 .scope module, "mux0" "TwoInMux" 2 89, 2 8, S_0x17d0000; - .timescale -9 -12; -L_0x17ee450/d .functor NOT 1, L_0x17ee8f0, C4<0>, C4<0>, C4<0>; -L_0x17ee450 .delay (10000,10000,10000) L_0x17ee450/d; -L_0x17ee510/d .functor AND 1, L_0x17ee2f0, L_0x17ee450, C4<1>, C4<1>; -L_0x17ee510 .delay (20000,20000,20000) L_0x17ee510/d; -L_0x17ee620/d .functor AND 1, L_0x17ede80, L_0x17ee8f0, C4<1>, C4<1>; -L_0x17ee620 .delay (20000,20000,20000) L_0x17ee620/d; -L_0x17ee770/d .functor OR 1, L_0x17ee510, L_0x17ee620, C4<0>, C4<0>; -L_0x17ee770 .delay (20000,20000,20000) L_0x17ee770/d; -v0x17d0740_0 .net "S", 0 0, L_0x17ee8f0; 1 drivers -v0x17d0800_0 .alias "in0", 0 0, v0x17d0e90_0; -v0x17d08a0_0 .alias "in1", 0 0, v0x17d0d00_0; -v0x17d0940_0 .net "nS", 0 0, L_0x17ee450; 1 drivers -v0x17d09c0_0 .net "out0", 0 0, L_0x17ee510; 1 drivers -v0x17d0a60_0 .net "out1", 0 0, L_0x17ee620; 1 drivers -v0x17d0b40_0 .alias "outfinal", 0 0, v0x17c9ad0_0; -S_0x17d00f0 .scope module, "mux1" "TwoInMux" 2 90, 2 8, S_0x17d0000; - .timescale -9 -12; -L_0x17ee990/d .functor NOT 1, L_0x17eeec0, C4<0>, C4<0>, C4<0>; -L_0x17ee990 .delay (10000,10000,10000) L_0x17ee990/d; -L_0x17eea50/d .functor AND 1, L_0x17ee770, L_0x17ee990, C4<1>, C4<1>; -L_0x17eea50 .delay (20000,20000,20000) L_0x17eea50/d; -L_0x17eeba0/d .functor AND 1, L_0x17edf70, L_0x17eeec0, C4<1>, C4<1>; -L_0x17eeba0 .delay (20000,20000,20000) L_0x17eeba0/d; -L_0x17eecf0/d .functor OR 1, L_0x17eea50, L_0x17eeba0, C4<0>, C4<0>; -L_0x17eecf0 .delay (20000,20000,20000) L_0x17eecf0/d; -v0x17d01e0_0 .net "S", 0 0, L_0x17eeec0; 1 drivers -v0x17d0260_0 .alias "in0", 0 0, v0x17c9ad0_0; -v0x17d02e0_0 .alias "in1", 0 0, v0x17d0db0_0; -v0x17d0380_0 .net "nS", 0 0, L_0x17ee990; 1 drivers -v0x17d0430_0 .net "out0", 0 0, L_0x17eea50; 1 drivers -v0x17d04d0_0 .net "out1", 0 0, L_0x17eeba0; 1 drivers -v0x17d05b0_0 .alias "outfinal", 0 0, v0x17c9a50_0; -S_0x17bb1b0 .scope module, "superalu" "Bitslice32" 3 31, 2 262, S_0x1782ed0; - .timescale -9 -12; -P_0x17ba1f8 .param/l "size" 2 277, +C4<0100>; -v0x17cf380_0 .alias "A", 3 0, v0x17dc7b0_0; -v0x17cf570_0 .alias "AddSubSLTSum", 3 0, v0x17dd910_0; -v0x17cf5f0_0 .alias "AndNandOut", 3 0, v0x17dd990_0; -v0x17cf670_0 .alias "B", 3 0, v0x17dc8d0_0; -RS_0x7ff970b2cae8 .resolv tri, L_0x17f0b90, L_0x17f31f0, L_0x17f5be0, L_0x1805bf0; -v0x17cf720_0 .net8 "Cmd0Start", 3 0, RS_0x7ff970b2cae8; 4 drivers -RS_0x7ff970b2cb18 .resolv tri, L_0x17f1aa0, L_0x17f40d0, L_0x17f6ba0, L_0x18069b0; -v0x17cf7a0_0 .net8 "Cmd1Start", 3 0, RS_0x7ff970b2cb18; 4 drivers -v0x17cf820_0 .alias "Command", 2 0, v0x17dc9d0_0; -v0x17cf8a0_0 .alias "OneBitFinalOut", 3 0, v0x17ddb10_0; -v0x17cf920_0 .alias "OrNorXorOut", 3 0, v0x17ddb90_0; -v0x17cf9a0_0 .alias "SLTflag", 0 0, v0x17ddc10_0; -v0x17cfa50_0 .alias "carryin", 3 0, v0x17dd400_0; -v0x17cfb00_0 .alias "carryout", 0 0, v0x17ddd10_0; -v0x17cfbb0_0 .alias "overflow", 0 0, v0x17ddd90_0; -v0x17cfc60_0 .alias "subtract", 3 0, v0x17dde10_0; -L_0x17f0b90 .part/pv L_0x17f09b0, 1, 1, 4; -L_0x17f0c30 .part v0x17dda90_0, 0, 1; -L_0x17f0d60 .part v0x17dda90_0, 1, 1; -L_0x17f0e90 .part RS_0x7ff970b2c6f8, 1, 1; -L_0x17f0f30 .part RS_0x7ff970b2c6f8, 1, 1; -L_0x17f0fd0 .part RS_0x7ff970b2b258, 1, 1; -L_0x17f11d0 .part RS_0x7ff970b2c6f8, 1, 1; -L_0x17f1aa0 .part/pv L_0x17f1890, 1, 1, 4; -L_0x17f1b90 .part v0x17dda90_0, 0, 1; -L_0x17f1cc0 .part v0x17dda90_0, 1, 1; -L_0x17f1e50 .part RS_0x7ff970b2b948, 1, 1; -L_0x17f2000 .part RS_0x7ff970b2b948, 1, 1; -L_0x17f20a0 .part RS_0x7ff970b2b258, 1, 1; -L_0x17f2140 .part RS_0x7ff970b2b258, 1, 1; -L_0x17f25a0 .part/pv L_0x17f2460, 1, 1, 4; -L_0x17f2690 .part v0x17dda90_0, 2, 1; -L_0x17f2730 .part RS_0x7ff970b2cae8, 1, 1; -L_0x17f2870 .part RS_0x7ff970b2cb18, 1, 1; -L_0x17f31f0 .part/pv L_0x17f2fe0, 2, 1, 4; -L_0x17f3290 .part v0x17dda90_0, 0, 1; -L_0x17f29b0 .part v0x17dda90_0, 1, 1; -L_0x17f3500 .part RS_0x7ff970b2c6f8, 2, 1; -L_0x17f33c0 .part RS_0x7ff970b2c6f8, 2, 1; -L_0x17f3660 .part RS_0x7ff970b2b258, 2, 1; -L_0x17f35a0 .part RS_0x7ff970b2c6f8, 2, 1; -L_0x17f40d0 .part/pv L_0x17f3ec0, 2, 1, 4; -L_0x17f3750 .part v0x17dda90_0, 0, 1; -L_0x17e2910 .part v0x17dda90_0, 1, 1; -L_0x17f4170 .part RS_0x7ff970b2b948, 2, 1; -L_0x17e2b30 .part RS_0x7ff970b2b948, 2, 1; -L_0x17e2a40 .part RS_0x7ff970b2b258, 2, 1; -L_0x17f4af0 .part RS_0x7ff970b2b258, 2, 1; -L_0x17f4f80 .part/pv L_0x17f4e40, 2, 1, 4; -L_0x17f5020 .part v0x17dda90_0, 2, 1; -L_0x17f4b90 .part RS_0x7ff970b2cae8, 2, 1; -L_0x17f5270 .part RS_0x7ff970b2cb18, 2, 1; -L_0x17f5be0 .part/pv L_0x17f59d0, 3, 1, 4; -L_0x17f5c80 .part v0x17dda90_0, 0, 1; -L_0x17f53a0 .part v0x17dda90_0, 1, 1; -L_0x17f5ef0 .part RS_0x7ff970b2c6f8, 3, 1; -L_0x17e85e0 .part RS_0x7ff970b2c6f8, 3, 1; -L_0x17f5db0 .part RS_0x7ff970b2b258, 3, 1; -L_0x17f6300 .part RS_0x7ff970b2c6f8, 3, 1; -L_0x17f6ba0 .part/pv L_0x17f6990, 3, 1, 4; -L_0x17f61a0 .part v0x17dda90_0, 0, 1; -L_0x17f6db0 .part v0x17dda90_0, 1, 1; -L_0x17f6c40 .part RS_0x7ff970b2b948, 3, 1; -L_0x17f6ce0 .part RS_0x7ff970b2b948, 3, 1; -L_0x17f7070 .part RS_0x7ff970b2b258, 3, 1; -L_0x17f7160 .part RS_0x7ff970b2b258, 3, 1; -L_0x17f7790 .part/pv L_0x17f7650, 3, 1, 4; -L_0x17f78c0 .part v0x17dda90_0, 2, 1; -L_0x17f7460 .part RS_0x7ff970b2cae8, 3, 1; -L_0x17f7500 .part RS_0x7ff970b2cb18, 3, 1; -L_0x1805bf0 .part/pv L_0x1805a10, 0, 1, 4; -L_0x1805c90 .part v0x17dda90_0, 0, 1; -L_0x17f7960 .part v0x17dda90_0, 1, 1; -L_0x1805f90 .part RS_0x7ff970b2c6f8, 0, 1; -L_0x1805dc0 .part RS_0x7ff970b2c6f8, 0, 1; -L_0x1805e60 .part RS_0x7ff970b2b258, 0, 1; -L_0x1806220 .part RS_0x7ff970b2c6f8, 0, 1; -L_0x18069b0 .part/pv L_0x18067d0, 0, 1, 4; -L_0x1806030 .part v0x17dda90_0, 0, 1; -L_0x1806160 .part v0x17dda90_0, 1, 1; -L_0x1806a50 .part RS_0x7ff970b2b948, 0, 1; -L_0x1806af0 .part RS_0x7ff970b2b948, 0, 1; -L_0x1806b90 .part RS_0x7ff970b2b258, 0, 1; -L_0x1806f50 .part RS_0x7ff970b2b258, 0, 1; -L_0x1807460 .part/pv L_0x1807320, 0, 1, 4; -L_0x1807500 .part v0x17dda90_0, 2, 1; -L_0x1807040 .part RS_0x7ff970b2cae8, 0, 1; -L_0x18077e0 .part RS_0x7ff970b2cb18, 0, 1; -S_0x17c9d40 .scope module, "trial" "AddSubSLT32" 2 282, 2 209, S_0x17bb1b0; - .timescale -9 -12; -P_0x17c9e38 .param/l "size" 2 232, +C4<0100>; -L_0x17fcb80/d .functor OR 1, L_0x17fce40, C4<0>, C4<0>, C4<0>; -L_0x17fcb80 .delay (20000,20000,20000) L_0x17fcb80/d; -L_0x17fcff0/d .functor XOR 1, RS_0x7ff970b2c9f8, L_0x17fd0e0, C4<0>, C4<0>; -L_0x17fcff0 .delay (40000,40000,40000) L_0x17fcff0/d; -L_0x17fcd70/d .functor AND 1, L_0x17fd2b0, L_0x17fd350, C4<1>, C4<1>; -L_0x17fcd70 .delay (20000,20000,20000) L_0x17fcd70/d; -L_0x17fd180/d .functor NOT 1, RS_0x7ff970b2ca88, C4<0>, C4<0>, C4<0>; -L_0x17fd180 .delay (10000,10000,10000) L_0x17fd180/d; -L_0x17fd640/d .functor NOT 1, L_0x17fd6a0, C4<0>, C4<0>, C4<0>; -L_0x17fd640 .delay (10000,10000,10000) L_0x17fd640/d; -L_0x17fd740/d .functor AND 1, L_0x17fd180, L_0x17fd880, C4<1>, C4<1>; -L_0x17fd740 .delay (20000,20000,20000) L_0x17fd740/d; -L_0x17fd440/d .functor AND 1, RS_0x7ff970b2ca88, L_0x17fd640, C4<1>, C4<1>; -L_0x17fd440 .delay (20000,20000,20000) L_0x17fd440/d; -L_0x17fda70/d .functor AND 1, L_0x17fd740, L_0x17fcd70, C4<1>, C4<1>; -L_0x17fda70 .delay (20000,20000,20000) L_0x17fda70/d; -L_0x17fdbb0/d .functor AND 1, L_0x17fd440, L_0x17fcd70, C4<1>, C4<1>; -L_0x17fdbb0 .delay (20000,20000,20000) L_0x17fdbb0/d; -L_0x17fdcd0/d .functor OR 1, L_0x17fda70, L_0x17fdbb0, C4<0>, C4<0>; -L_0x17fdcd0 .delay (20000,20000,20000) L_0x17fdcd0/d; -v0x17ce4a0_0 .alias "A", 3 0, v0x17dc7b0_0; -v0x17ce540_0 .alias "AddSubSLTSum", 3 0, v0x17dd910_0; -v0x17ce5e0_0 .alias "B", 3 0, v0x17dc8d0_0; -RS_0x7ff970b2c728 .resolv tri, L_0x17f8af0, L_0x17f9f10, L_0x17fb310, L_0x17fc8f0; -v0x17ce6b0_0 .net8 "CarryoutWire", 3 0, RS_0x7ff970b2c728; 4 drivers -v0x17ce730_0 .alias "Command", 2 0, v0x17dc9d0_0; -v0x17ce7b0_0 .net "Res0OF1", 0 0, L_0x17fd440; 1 drivers -v0x17ce850_0 .net "Res1OF0", 0 0, L_0x17fd740; 1 drivers -v0x17ce8f0_0 .alias "SLTflag", 0 0, v0x17ddc10_0; -v0x17ce9e0_0 .net "SLTflag0", 0 0, L_0x17fda70; 1 drivers -v0x17cea80_0 .net "SLTflag1", 0 0, L_0x17fdbb0; 1 drivers -v0x17ceb20_0 .net "SLTon", 0 0, L_0x17fcd70; 1 drivers -v0x17cebc0_0 .net *"_s40", 0 0, L_0x17fce40; 1 drivers -v0x17cec60_0 .net/s *"_s41", 0 0, C4<0>; 1 drivers -v0x17ced00_0 .net *"_s44", 0 0, L_0x17fd0e0; 1 drivers -v0x17cee20_0 .net *"_s46", 0 0, L_0x17fd2b0; 1 drivers -v0x17ceec0_0 .net *"_s48", 0 0, L_0x17fd350; 1 drivers -v0x17ced80_0 .net *"_s50", 0 0, L_0x17fd6a0; 1 drivers -v0x17cf010_0 .net *"_s52", 0 0, L_0x17fd880; 1 drivers -v0x17cf130_0 .alias "carryin", 3 0, v0x17dd400_0; -v0x17cf1b0_0 .alias "carryout", 0 0, v0x17ddd10_0; -v0x17cf090_0 .net "nAddSubSLTSum", 0 0, L_0x17fd640; 1 drivers -v0x17cf2e0_0 .net "nOF", 0 0, L_0x17fd180; 1 drivers -v0x17cf230_0 .alias "overflow", 0 0, v0x17ddd90_0; -v0x17cf420_0 .alias "subtract", 3 0, v0x17dde10_0; -L_0x17f8a00 .part/pv L_0x17f8570, 1, 1, 4; -L_0x17f8af0 .part/pv L_0x17f88c0, 1, 1, 4; -L_0x17f8be0 .part/pv L_0x17f82a0, 1, 1, 4; -L_0x17f8cd0 .part v0x17dd890_0, 1, 1; -L_0x17f8d70 .part v0x17dda10_0, 1, 1; -L_0x17f8ea0 .part RS_0x7ff970b2c728, 0, 1; -L_0x17f9e20 .part/pv L_0x17f9990, 2, 1, 4; -L_0x17f9f10 .part/pv L_0x17f9ce0, 2, 1, 4; -L_0x17fa050 .part/pv L_0x17f96c0, 2, 1, 4; -L_0x17fa140 .part v0x17dd890_0, 2, 1; -L_0x17fa240 .part v0x17dda10_0, 2, 1; -L_0x17fa370 .part RS_0x7ff970b2c728, 1, 1; -L_0x17fb220 .part/pv L_0x17fad90, 3, 1, 4; -L_0x17fb310 .part/pv L_0x17fb0e0, 3, 1, 4; -L_0x17fb480 .part/pv L_0x17faac0, 3, 1, 4; -L_0x17fb570 .part v0x17dd890_0, 3, 1; -L_0x17fb6a0 .part v0x17dda10_0, 3, 1; -L_0x17fb7d0 .part RS_0x7ff970b2c728, 2, 1; -L_0x17fc800 .part/pv L_0x17fc330, 0, 1, 4; -L_0x17fc8f0 .part/pv L_0x17fc6a0, 0, 1, 4; -L_0x17fb870 .part/pv L_0x17fc060, 0, 1, 4; -L_0x17fcae0 .part v0x17dd890_0, 0, 1; -L_0x17fc9e0 .part v0x17dda10_0, 0, 1; -L_0x17fccd0 .part RS_0x7ff970b2cab8, 0, 1; -L_0x17fce40 .part RS_0x7ff970b2c728, 3, 1; -L_0x17fd0e0 .part RS_0x7ff970b2c728, 2, 1; -L_0x17fd2b0 .part v0x17dda90_0, 1, 1; -L_0x17fd350 .part RS_0x7ff970b2cab8, 0, 1; -L_0x17fd6a0 .part RS_0x7ff970b2c6f8, 3, 1; -L_0x17fd880 .part RS_0x7ff970b2c6f8, 3, 1; -S_0x17cd490 .scope module, "attempt2" "MiddleAddSubSLT" 2 229, 2 95, S_0x17c9d40; - .timescale -9 -12; -L_0x17fb610/d .functor NOT 1, L_0x17fc9e0, C4<0>, C4<0>, C4<0>; -L_0x17fb610 .delay (10000,10000,10000) L_0x17fb610/d; -L_0x17fbf00/d .functor NOT 1, L_0x17fbfc0, C4<0>, C4<0>, C4<0>; -L_0x17fbf00 .delay (10000,10000,10000) L_0x17fbf00/d; -L_0x17fc060/d .functor AND 1, L_0x17fc1a0, L_0x17fbf00, C4<1>, C4<1>; -L_0x17fc060 .delay (20000,20000,20000) L_0x17fc060/d; -L_0x17fc240/d .functor XOR 1, L_0x17fcae0, L_0x17fbc90, C4<0>, C4<0>; -L_0x17fc240 .delay (40000,40000,40000) L_0x17fc240/d; -L_0x17fc330/d .functor XOR 1, L_0x17fc240, L_0x17fccd0, C4<0>, C4<0>; -L_0x17fc330 .delay (40000,40000,40000) L_0x17fc330/d; -L_0x17fc420/d .functor AND 1, L_0x17fcae0, L_0x17fbc90, C4<1>, C4<1>; -L_0x17fc420 .delay (20000,20000,20000) L_0x17fc420/d; -L_0x17fc590/d .functor AND 1, L_0x17fc240, L_0x17fccd0, C4<1>, C4<1>; -L_0x17fc590 .delay (20000,20000,20000) L_0x17fc590/d; -L_0x17fc6a0/d .functor OR 1, L_0x17fc420, L_0x17fc590, C4<0>, C4<0>; -L_0x17fc6a0 .delay (20000,20000,20000) L_0x17fc6a0/d; -v0x17cdb00_0 .net "A", 0 0, L_0x17fcae0; 1 drivers -v0x17cdbc0_0 .net "AandB", 0 0, L_0x17fc420; 1 drivers -v0x17cdc60_0 .net "AddSubSLTSum", 0 0, L_0x17fc330; 1 drivers -v0x17cdd00_0 .net "AxorB", 0 0, L_0x17fc240; 1 drivers -v0x17cdd80_0 .net "B", 0 0, L_0x17fc9e0; 1 drivers -v0x17cde30_0 .net "BornB", 0 0, L_0x17fbc90; 1 drivers -v0x17cdef0_0 .net "CINandAxorB", 0 0, L_0x17fc590; 1 drivers -v0x17cdf70_0 .alias "Command", 2 0, v0x17dc9d0_0; -v0x17cdff0_0 .net *"_s3", 0 0, L_0x17fbfc0; 1 drivers -v0x17ce070_0 .net *"_s5", 0 0, L_0x17fc1a0; 1 drivers -v0x17ce110_0 .net "carryin", 0 0, L_0x17fccd0; 1 drivers -v0x17ce1b0_0 .net "carryout", 0 0, L_0x17fc6a0; 1 drivers -v0x17ce250_0 .net "nB", 0 0, L_0x17fb610; 1 drivers -v0x17ce300_0 .net "nCmd2", 0 0, L_0x17fbf00; 1 drivers -v0x17ce400_0 .net "subtract", 0 0, L_0x17fc060; 1 drivers -L_0x17fbe60 .part v0x17dda90_0, 0, 1; -L_0x17fbfc0 .part v0x17dda90_0, 2, 1; -L_0x17fc1a0 .part v0x17dda90_0, 0, 1; -S_0x17cd580 .scope module, "mux0" "TwoInMux" 2 111, 2 8, S_0x17cd490; - .timescale -9 -12; -L_0x17fb9b0/d .functor NOT 1, L_0x17fbe60, C4<0>, C4<0>, C4<0>; -L_0x17fb9b0 .delay (10000,10000,10000) L_0x17fb9b0/d; -L_0x17fba70/d .functor AND 1, L_0x17fc9e0, L_0x17fb9b0, C4<1>, C4<1>; -L_0x17fba70 .delay (20000,20000,20000) L_0x17fba70/d; -L_0x17fbb80/d .functor AND 1, L_0x17fb610, L_0x17fbe60, C4<1>, C4<1>; -L_0x17fbb80 .delay (20000,20000,20000) L_0x17fbb80/d; -L_0x17fbc90/d .functor OR 1, L_0x17fba70, L_0x17fbb80, C4<0>, C4<0>; -L_0x17fbc90 .delay (20000,20000,20000) L_0x17fbc90/d; -v0x17cd670_0 .net "S", 0 0, L_0x17fbe60; 1 drivers -v0x17cd730_0 .alias "in0", 0 0, v0x17cdd80_0; -v0x17cd7d0_0 .alias "in1", 0 0, v0x17ce250_0; -v0x17cd870_0 .net "nS", 0 0, L_0x17fb9b0; 1 drivers -v0x17cd920_0 .net "out0", 0 0, L_0x17fba70; 1 drivers -v0x17cd9c0_0 .net "out1", 0 0, L_0x17fbb80; 1 drivers -v0x17cda60_0 .alias "outfinal", 0 0, v0x17cde30_0; -S_0x17cc2f0 .scope generate, "addbits[1]" "addbits[1]" 2 234, 2 234, S_0x17c9d40; - .timescale -9 -12; -P_0x17cbd08 .param/l "i" 2 234, +C4<01>; -S_0x17cc460 .scope module, "attempt" "MiddleAddSubSLT" 2 236, 2 95, S_0x17cc2f0; - .timescale -9 -12; -L_0x17f7b20/d .functor NOT 1, L_0x17f8d70, C4<0>, C4<0>, C4<0>; -L_0x17f7b20 .delay (10000,10000,10000) L_0x17f7b20/d; -L_0x17f8160/d .functor NOT 1, L_0x17f8200, C4<0>, C4<0>, C4<0>; -L_0x17f8160 .delay (10000,10000,10000) L_0x17f8160/d; -L_0x17f82a0/d .functor AND 1, L_0x17f83e0, L_0x17f8160, C4<1>, C4<1>; -L_0x17f82a0 .delay (20000,20000,20000) L_0x17f82a0/d; -L_0x17f8480/d .functor XOR 1, L_0x17f8cd0, L_0x17f7f30, C4<0>, C4<0>; -L_0x17f8480 .delay (40000,40000,40000) L_0x17f8480/d; -L_0x17f8570/d .functor XOR 1, L_0x17f8480, L_0x17f8ea0, C4<0>, C4<0>; -L_0x17f8570 .delay (40000,40000,40000) L_0x17f8570/d; -L_0x17f8660/d .functor AND 1, L_0x17f8cd0, L_0x17f7f30, C4<1>, C4<1>; -L_0x17f8660 .delay (20000,20000,20000) L_0x17f8660/d; -L_0x17f87d0/d .functor AND 1, L_0x17f8480, L_0x17f8ea0, C4<1>, C4<1>; -L_0x17f87d0 .delay (20000,20000,20000) L_0x17f87d0/d; -L_0x17f88c0/d .functor OR 1, L_0x17f8660, L_0x17f87d0, C4<0>, C4<0>; -L_0x17f88c0 .delay (20000,20000,20000) L_0x17f88c0/d; -v0x17ccaf0_0 .net "A", 0 0, L_0x17f8cd0; 1 drivers -v0x17ccbb0_0 .net "AandB", 0 0, L_0x17f8660; 1 drivers -v0x17ccc50_0 .net "AddSubSLTSum", 0 0, L_0x17f8570; 1 drivers -v0x17cccf0_0 .net "AxorB", 0 0, L_0x17f8480; 1 drivers -v0x17ccd70_0 .net "B", 0 0, L_0x17f8d70; 1 drivers -v0x17cce20_0 .net "BornB", 0 0, L_0x17f7f30; 1 drivers -v0x17ccee0_0 .net "CINandAxorB", 0 0, L_0x17f87d0; 1 drivers -v0x17ccf60_0 .alias "Command", 2 0, v0x17dc9d0_0; -v0x17ccfe0_0 .net *"_s3", 0 0, L_0x17f8200; 1 drivers -v0x17cd060_0 .net *"_s5", 0 0, L_0x17f83e0; 1 drivers -v0x17cd100_0 .net "carryin", 0 0, L_0x17f8ea0; 1 drivers -v0x17cd1a0_0 .net "carryout", 0 0, L_0x17f88c0; 1 drivers -v0x17cd240_0 .net "nB", 0 0, L_0x17f7b20; 1 drivers -v0x17cd2f0_0 .net "nCmd2", 0 0, L_0x17f8160; 1 drivers -v0x17cd3f0_0 .net "subtract", 0 0, L_0x17f82a0; 1 drivers -L_0x17f80c0 .part v0x17dda90_0, 0, 1; -L_0x17f8200 .part v0x17dda90_0, 2, 1; -L_0x17f83e0 .part v0x17dda90_0, 0, 1; -S_0x17cc550 .scope module, "mux0" "TwoInMux" 2 111, 2 8, S_0x17cc460; - .timescale -9 -12; -L_0x17f7cb0/d .functor NOT 1, L_0x17f80c0, C4<0>, C4<0>, C4<0>; -L_0x17f7cb0 .delay (10000,10000,10000) L_0x17f7cb0/d; -L_0x17f7d50/d .functor AND 1, L_0x17f8d70, L_0x17f7cb0, C4<1>, C4<1>; -L_0x17f7d50 .delay (20000,20000,20000) L_0x17f7d50/d; -L_0x17f7e40/d .functor AND 1, L_0x17f7b20, L_0x17f80c0, C4<1>, C4<1>; -L_0x17f7e40 .delay (20000,20000,20000) L_0x17f7e40/d; -L_0x17f7f30/d .functor OR 1, L_0x17f7d50, L_0x17f7e40, C4<0>, C4<0>; -L_0x17f7f30 .delay (20000,20000,20000) L_0x17f7f30/d; -v0x17cc640_0 .net "S", 0 0, L_0x17f80c0; 1 drivers -v0x17cc6e0_0 .alias "in0", 0 0, v0x17ccd70_0; -v0x17cc780_0 .alias "in1", 0 0, v0x17cd240_0; -v0x17cc820_0 .net "nS", 0 0, L_0x17f7cb0; 1 drivers -v0x17cc8d0_0 .net "out0", 0 0, L_0x17f7d50; 1 drivers -v0x17cc970_0 .net "out1", 0 0, L_0x17f7e40; 1 drivers -v0x17cca50_0 .alias "outfinal", 0 0, v0x17cce20_0; -S_0x17cb150 .scope generate, "addbits[2]" "addbits[2]" 2 234, 2 234, S_0x17c9d40; - .timescale -9 -12; -P_0x17caa48 .param/l "i" 2 234, +C4<010>; -S_0x17cb2c0 .scope module, "attempt" "MiddleAddSubSLT" 2 236, 2 95, S_0x17cb150; - .timescale -9 -12; -L_0x17f8f40/d .functor NOT 1, L_0x17fa240, C4<0>, C4<0>, C4<0>; -L_0x17f8f40 .delay (10000,10000,10000) L_0x17f8f40/d; -L_0x17f9580/d .functor NOT 1, L_0x17f9620, C4<0>, C4<0>, C4<0>; -L_0x17f9580 .delay (10000,10000,10000) L_0x17f9580/d; -L_0x17f96c0/d .functor AND 1, L_0x17f9800, L_0x17f9580, C4<1>, C4<1>; -L_0x17f96c0 .delay (20000,20000,20000) L_0x17f96c0/d; -L_0x17f98a0/d .functor XOR 1, L_0x17fa140, L_0x17f9350, C4<0>, C4<0>; -L_0x17f98a0 .delay (40000,40000,40000) L_0x17f98a0/d; -L_0x17f9990/d .functor XOR 1, L_0x17f98a0, L_0x17fa370, C4<0>, C4<0>; -L_0x17f9990 .delay (40000,40000,40000) L_0x17f9990/d; -L_0x17f9a80/d .functor AND 1, L_0x17fa140, L_0x17f9350, C4<1>, C4<1>; -L_0x17f9a80 .delay (20000,20000,20000) L_0x17f9a80/d; -L_0x17f9bf0/d .functor AND 1, L_0x17f98a0, L_0x17fa370, C4<1>, C4<1>; -L_0x17f9bf0 .delay (20000,20000,20000) L_0x17f9bf0/d; -L_0x17f9ce0/d .functor OR 1, L_0x17f9a80, L_0x17f9bf0, C4<0>, C4<0>; -L_0x17f9ce0 .delay (20000,20000,20000) L_0x17f9ce0/d; -v0x17cb950_0 .net "A", 0 0, L_0x17fa140; 1 drivers -v0x17cba10_0 .net "AandB", 0 0, L_0x17f9a80; 1 drivers -v0x17cbab0_0 .net "AddSubSLTSum", 0 0, L_0x17f9990; 1 drivers -v0x17cbb50_0 .net "AxorB", 0 0, L_0x17f98a0; 1 drivers -v0x17cbbd0_0 .net "B", 0 0, L_0x17fa240; 1 drivers -v0x17cbc80_0 .net "BornB", 0 0, L_0x17f9350; 1 drivers -v0x17cbd40_0 .net "CINandAxorB", 0 0, L_0x17f9bf0; 1 drivers -v0x17cbdc0_0 .alias "Command", 2 0, v0x17dc9d0_0; -v0x17cbe40_0 .net *"_s3", 0 0, L_0x17f9620; 1 drivers -v0x17cbec0_0 .net *"_s5", 0 0, L_0x17f9800; 1 drivers -v0x17cbf60_0 .net "carryin", 0 0, L_0x17fa370; 1 drivers -v0x17cc000_0 .net "carryout", 0 0, L_0x17f9ce0; 1 drivers -v0x17cc0a0_0 .net "nB", 0 0, L_0x17f8f40; 1 drivers -v0x17cc150_0 .net "nCmd2", 0 0, L_0x17f9580; 1 drivers -v0x17cc250_0 .net "subtract", 0 0, L_0x17f96c0; 1 drivers -L_0x17f94e0 .part v0x17dda90_0, 0, 1; -L_0x17f9620 .part v0x17dda90_0, 2, 1; -L_0x17f9800 .part v0x17dda90_0, 0, 1; -S_0x17cb3b0 .scope module, "mux0" "TwoInMux" 2 111, 2 8, S_0x17cb2c0; - .timescale -9 -12; -L_0x17f90d0/d .functor NOT 1, L_0x17f94e0, C4<0>, C4<0>, C4<0>; -L_0x17f90d0 .delay (10000,10000,10000) L_0x17f90d0/d; -L_0x17f9170/d .functor AND 1, L_0x17fa240, L_0x17f90d0, C4<1>, C4<1>; -L_0x17f9170 .delay (20000,20000,20000) L_0x17f9170/d; -L_0x17f9260/d .functor AND 1, L_0x17f8f40, L_0x17f94e0, C4<1>, C4<1>; -L_0x17f9260 .delay (20000,20000,20000) L_0x17f9260/d; -L_0x17f9350/d .functor OR 1, L_0x17f9170, L_0x17f9260, C4<0>, C4<0>; -L_0x17f9350 .delay (20000,20000,20000) L_0x17f9350/d; -v0x17cb4a0_0 .net "S", 0 0, L_0x17f94e0; 1 drivers -v0x17cb540_0 .alias "in0", 0 0, v0x17cbbd0_0; -v0x17cb5e0_0 .alias "in1", 0 0, v0x17cc0a0_0; -v0x17cb680_0 .net "nS", 0 0, L_0x17f90d0; 1 drivers -v0x17cb730_0 .net "out0", 0 0, L_0x17f9170; 1 drivers -v0x17cb7d0_0 .net "out1", 0 0, L_0x17f9260; 1 drivers -v0x17cb8b0_0 .alias "outfinal", 0 0, v0x17cbc80_0; -S_0x17c9eb0 .scope generate, "addbits[3]" "addbits[3]" 2 234, 2 234, S_0x17c9d40; - .timescale -9 -12; -P_0x17c9fa8 .param/l "i" 2 234, +C4<011>; -S_0x17ca020 .scope module, "attempt" "MiddleAddSubSLT" 2 236, 2 95, S_0x17c9eb0; - .timescale -9 -12; -L_0x17fa1e0/d .functor NOT 1, L_0x17fb6a0, C4<0>, C4<0>, C4<0>; -L_0x17fa1e0 .delay (10000,10000,10000) L_0x17fa1e0/d; -L_0x17fa980/d .functor NOT 1, L_0x17faa20, C4<0>, C4<0>, C4<0>; -L_0x17fa980 .delay (10000,10000,10000) L_0x17fa980/d; -L_0x17faac0/d .functor AND 1, L_0x17fac00, L_0x17fa980, C4<1>, C4<1>; -L_0x17faac0 .delay (20000,20000,20000) L_0x17faac0/d; -L_0x17faca0/d .functor XOR 1, L_0x17fb570, L_0x17fa750, C4<0>, C4<0>; -L_0x17faca0 .delay (40000,40000,40000) L_0x17faca0/d; -L_0x17fad90/d .functor XOR 1, L_0x17faca0, L_0x17fb7d0, C4<0>, C4<0>; -L_0x17fad90 .delay (40000,40000,40000) L_0x17fad90/d; -L_0x17fae80/d .functor AND 1, L_0x17fb570, L_0x17fa750, C4<1>, C4<1>; -L_0x17fae80 .delay (20000,20000,20000) L_0x17fae80/d; -L_0x17faff0/d .functor AND 1, L_0x17faca0, L_0x17fb7d0, C4<1>, C4<1>; -L_0x17faff0 .delay (20000,20000,20000) L_0x17faff0/d; -L_0x17fb0e0/d .functor OR 1, L_0x17fae80, L_0x17faff0, C4<0>, C4<0>; -L_0x17fb0e0 .delay (20000,20000,20000) L_0x17fb0e0/d; -v0x17ca690_0 .net "A", 0 0, L_0x17fb570; 1 drivers -v0x17ca750_0 .net "AandB", 0 0, L_0x17fae80; 1 drivers -v0x17ca7f0_0 .net "AddSubSLTSum", 0 0, L_0x17fad90; 1 drivers -v0x17ca890_0 .net "AxorB", 0 0, L_0x17faca0; 1 drivers -v0x17ca910_0 .net "B", 0 0, L_0x17fb6a0; 1 drivers -v0x17ca9c0_0 .net "BornB", 0 0, L_0x17fa750; 1 drivers -v0x17caa80_0 .net "CINandAxorB", 0 0, L_0x17faff0; 1 drivers -v0x17cab00_0 .alias "Command", 2 0, v0x17dc9d0_0; -v0x17cabd0_0 .net *"_s3", 0 0, L_0x17faa20; 1 drivers -v0x17cac50_0 .net *"_s5", 0 0, L_0x17fac00; 1 drivers -v0x17cad50_0 .net "carryin", 0 0, L_0x17fb7d0; 1 drivers -v0x17cadf0_0 .net "carryout", 0 0, L_0x17fb0e0; 1 drivers -v0x17caf00_0 .net "nB", 0 0, L_0x17fa1e0; 1 drivers -v0x17cafb0_0 .net "nCmd2", 0 0, L_0x17fa980; 1 drivers -v0x17cb0b0_0 .net "subtract", 0 0, L_0x17faac0; 1 drivers -L_0x17fa8e0 .part v0x17dda90_0, 0, 1; -L_0x17faa20 .part v0x17dda90_0, 2, 1; -L_0x17fac00 .part v0x17dda90_0, 0, 1; -S_0x17ca110 .scope module, "mux0" "TwoInMux" 2 111, 2 8, S_0x17ca020; - .timescale -9 -12; -L_0x17fa510/d .functor NOT 1, L_0x17fa8e0, C4<0>, C4<0>, C4<0>; -L_0x17fa510 .delay (10000,10000,10000) L_0x17fa510/d; -L_0x17fa570/d .functor AND 1, L_0x17fb6a0, L_0x17fa510, C4<1>, C4<1>; -L_0x17fa570 .delay (20000,20000,20000) L_0x17fa570/d; -L_0x17fa660/d .functor AND 1, L_0x17fa1e0, L_0x17fa8e0, C4<1>, C4<1>; -L_0x17fa660 .delay (20000,20000,20000) L_0x17fa660/d; -L_0x17fa750/d .functor OR 1, L_0x17fa570, L_0x17fa660, C4<0>, C4<0>; -L_0x17fa750 .delay (20000,20000,20000) L_0x17fa750/d; -v0x17ca200_0 .net "S", 0 0, L_0x17fa8e0; 1 drivers -v0x17ca280_0 .alias "in0", 0 0, v0x17ca910_0; -v0x17ca320_0 .alias "in1", 0 0, v0x17caf00_0; -v0x17ca3c0_0 .net "nS", 0 0, L_0x17fa510; 1 drivers -v0x17ca470_0 .net "out0", 0 0, L_0x17fa570; 1 drivers -v0x17ca510_0 .net "out1", 0 0, L_0x17fa660; 1 drivers -v0x17ca5f0_0 .alias "outfinal", 0 0, v0x17ca9c0_0; -S_0x17c6b90 .scope module, "trial1" "AndNand32" 2 283, 2 157, S_0x17bb1b0; - .timescale -9 -12; -P_0x17c6618 .param/l "size" 2 165, +C4<0100>; -v0x17c6a80_0 .alias "A", 3 0, v0x17dc7b0_0; -v0x17c9b60_0 .alias "AndNandOut", 3 0, v0x17dd990_0; -v0x17c9be0_0 .alias "B", 3 0, v0x17dc8d0_0; -v0x17c9c90_0 .alias "Command", 2 0, v0x17dc9d0_0; -L_0x17fe630 .part/pv L_0x17fe3c0, 1, 1, 4; -L_0x17fe6f0 .part v0x17dd890_0, 1, 1; -L_0x17fe790 .part v0x17dda10_0, 1, 1; -L_0x17ff0a0 .part/pv L_0x17fee30, 2, 1, 4; -L_0x17ff140 .part v0x17dd890_0, 2, 1; -L_0x17ff1e0 .part v0x17dda10_0, 2, 1; -L_0x17ffb10 .part/pv L_0x17ff8a0, 3, 1, 4; -L_0x17f1ef0 .part v0x17dd890_0, 3, 1; -L_0x17ffdc0 .part v0x17dda10_0, 3, 1; -L_0x1800670 .part/pv L_0x1800400, 0, 1, 4; -L_0x1800770 .part v0x17dd890_0, 0, 1; -L_0x1800810 .part v0x17dda10_0, 0, 1; -S_0x17c9020 .scope module, "attempt2" "AndNand" 2 170, 2 53, S_0x17c6b90; - .timescale -9 -12; -L_0x17ffeb0/d .functor NAND 1, L_0x1800770, L_0x1800810, C4<1>, C4<1>; -L_0x17ffeb0 .delay (10000,10000,10000) L_0x17ffeb0/d; -L_0x17fffb0/d .functor NOT 1, L_0x17ffeb0, C4<0>, C4<0>, C4<0>; -L_0x17fffb0 .delay (10000,10000,10000) L_0x17fffb0/d; -v0x17c9640_0 .net "A", 0 0, L_0x1800770; 1 drivers -v0x17c9700_0 .net "AandB", 0 0, L_0x17fffb0; 1 drivers -v0x17c9780_0 .net "AnandB", 0 0, L_0x17ffeb0; 1 drivers -v0x17c9830_0 .net "AndNandOut", 0 0, L_0x1800400; 1 drivers -v0x17c9910_0 .net "B", 0 0, L_0x1800810; 1 drivers -v0x17c9990_0 .alias "Command", 2 0, v0x17dc9d0_0; -L_0x18005d0 .part v0x17dda90_0, 0, 1; -S_0x17c9110 .scope module, "potato" "TwoInMux" 2 66, 2 8, S_0x17c9020; - .timescale -9 -12; -L_0x18000e0/d .functor NOT 1, L_0x18005d0, C4<0>, C4<0>, C4<0>; -L_0x18000e0 .delay (10000,10000,10000) L_0x18000e0/d; -L_0x18001a0/d .functor AND 1, L_0x17fffb0, L_0x18000e0, C4<1>, C4<1>; -L_0x18001a0 .delay (20000,20000,20000) L_0x18001a0/d; -L_0x18002b0/d .functor AND 1, L_0x17ffeb0, L_0x18005d0, C4<1>, C4<1>; -L_0x18002b0 .delay (20000,20000,20000) L_0x18002b0/d; -L_0x1800400/d .functor OR 1, L_0x18001a0, L_0x18002b0, C4<0>, C4<0>; -L_0x1800400 .delay (20000,20000,20000) L_0x1800400/d; -v0x17c9200_0 .net "S", 0 0, L_0x18005d0; 1 drivers -v0x17c9280_0 .alias "in0", 0 0, v0x17c9700_0; -v0x17c9300_0 .alias "in1", 0 0, v0x17c9780_0; -v0x17c93a0_0 .net "nS", 0 0, L_0x18000e0; 1 drivers -v0x17c9420_0 .net "out0", 0 0, L_0x18001a0; 1 drivers -v0x17c94c0_0 .net "out1", 0 0, L_0x18002b0; 1 drivers -v0x17c95a0_0 .alias "outfinal", 0 0, v0x17c9830_0; -S_0x17c8450 .scope generate, "andbits[1]" "andbits[1]" 2 173, 2 173, S_0x17c6b90; - .timescale -9 -12; -P_0x17c8548 .param/l "i" 2 173, +C4<01>; -S_0x17c85e0 .scope module, "attempt" "AndNand" 2 175, 2 53, S_0x17c8450; - .timescale -9 -12; -L_0x17fdeb0/d .functor NAND 1, L_0x17fe6f0, L_0x17fe790, C4<1>, C4<1>; -L_0x17fdeb0 .delay (10000,10000,10000) L_0x17fdeb0/d; -L_0x17fdf70/d .functor NOT 1, L_0x17fdeb0, C4<0>, C4<0>, C4<0>; -L_0x17fdf70 .delay (10000,10000,10000) L_0x17fdf70/d; -v0x17c8c40_0 .net "A", 0 0, L_0x17fe6f0; 1 drivers -v0x17c8d00_0 .net "AandB", 0 0, L_0x17fdf70; 1 drivers -v0x17c8d80_0 .net "AnandB", 0 0, L_0x17fdeb0; 1 drivers -v0x17c8e00_0 .net "AndNandOut", 0 0, L_0x17fe3c0; 1 drivers -v0x17c8ee0_0 .net "B", 0 0, L_0x17fe790; 1 drivers -v0x17c8f60_0 .alias "Command", 2 0, v0x17dc9d0_0; -L_0x17fe590 .part v0x17dda90_0, 0, 1; -S_0x17c86d0 .scope module, "potato" "TwoInMux" 2 66, 2 8, S_0x17c85e0; - .timescale -9 -12; -L_0x17fe0a0/d .functor NOT 1, L_0x17fe590, C4<0>, C4<0>, C4<0>; -L_0x17fe0a0 .delay (10000,10000,10000) L_0x17fe0a0/d; -L_0x17fe160/d .functor AND 1, L_0x17fdf70, L_0x17fe0a0, C4<1>, C4<1>; -L_0x17fe160 .delay (20000,20000,20000) L_0x17fe160/d; -L_0x17fe270/d .functor AND 1, L_0x17fdeb0, L_0x17fe590, C4<1>, C4<1>; -L_0x17fe270 .delay (20000,20000,20000) L_0x17fe270/d; -L_0x17fe3c0/d .functor OR 1, L_0x17fe160, L_0x17fe270, C4<0>, C4<0>; -L_0x17fe3c0 .delay (20000,20000,20000) L_0x17fe3c0/d; -v0x17c87c0_0 .net "S", 0 0, L_0x17fe590; 1 drivers -v0x17c8860_0 .alias "in0", 0 0, v0x17c8d00_0; -v0x17c8900_0 .alias "in1", 0 0, v0x17c8d80_0; -v0x17c89a0_0 .net "nS", 0 0, L_0x17fe0a0; 1 drivers -v0x17c8a20_0 .net "out0", 0 0, L_0x17fe160; 1 drivers -v0x17c8ac0_0 .net "out1", 0 0, L_0x17fe270; 1 drivers -v0x17c8ba0_0 .alias "outfinal", 0 0, v0x17c8e00_0; -S_0x17c7930 .scope generate, "andbits[2]" "andbits[2]" 2 173, 2 173, S_0x17c6b90; - .timescale -9 -12; -P_0x17c7a28 .param/l "i" 2 173, +C4<010>; -S_0x17c7aa0 .scope module, "attempt" "AndNand" 2 175, 2 53, S_0x17c7930; - .timescale -9 -12; -L_0x17fe880/d .functor NAND 1, L_0x17ff140, L_0x17ff1e0, C4<1>, C4<1>; -L_0x17fe880 .delay (10000,10000,10000) L_0x17fe880/d; -L_0x17fe9e0/d .functor NOT 1, L_0x17fe880, C4<0>, C4<0>, C4<0>; -L_0x17fe9e0 .delay (10000,10000,10000) L_0x17fe9e0/d; -v0x17c8060_0 .net "A", 0 0, L_0x17ff140; 1 drivers -v0x17c8100_0 .net "AandB", 0 0, L_0x17fe9e0; 1 drivers -v0x17c81b0_0 .net "AnandB", 0 0, L_0x17fe880; 1 drivers -v0x17c8260_0 .net "AndNandOut", 0 0, L_0x17fee30; 1 drivers -v0x17c8310_0 .net "B", 0 0, L_0x17ff1e0; 1 drivers -v0x17c8390_0 .alias "Command", 2 0, v0x17dc9d0_0; -L_0x17ff000 .part v0x17dda90_0, 0, 1; -S_0x17c7b90 .scope module, "potato" "TwoInMux" 2 66, 2 8, S_0x17c7aa0; - .timescale -9 -12; -L_0x17feb10/d .functor NOT 1, L_0x17ff000, C4<0>, C4<0>, C4<0>; -L_0x17feb10 .delay (10000,10000,10000) L_0x17feb10/d; -L_0x17febd0/d .functor AND 1, L_0x17fe9e0, L_0x17feb10, C4<1>, C4<1>; -L_0x17febd0 .delay (20000,20000,20000) L_0x17febd0/d; -L_0x17fece0/d .functor AND 1, L_0x17fe880, L_0x17ff000, C4<1>, C4<1>; -L_0x17fece0 .delay (20000,20000,20000) L_0x17fece0/d; -L_0x17fee30/d .functor OR 1, L_0x17febd0, L_0x17fece0, C4<0>, C4<0>; -L_0x17fee30 .delay (20000,20000,20000) L_0x17fee30/d; -v0x17c7c80_0 .net "S", 0 0, L_0x17ff000; 1 drivers -v0x17c7d00_0 .alias "in0", 0 0, v0x17c8100_0; -v0x17c7da0_0 .alias "in1", 0 0, v0x17c81b0_0; -v0x17c7e40_0 .net "nS", 0 0, L_0x17feb10; 1 drivers -v0x17c7ec0_0 .net "out0", 0 0, L_0x17febd0; 1 drivers -v0x17c7f60_0 .net "out1", 0 0, L_0x17fece0; 1 drivers -v0x17c7fe0_0 .alias "outfinal", 0 0, v0x17c8260_0; -S_0x17c6d00 .scope generate, "andbits[3]" "andbits[3]" 2 173, 2 173, S_0x17c6b90; - .timescale -9 -12; -P_0x17c6df8 .param/l "i" 2 173, +C4<011>; -S_0x17c6e90 .scope module, "attempt" "AndNand" 2 175, 2 53, S_0x17c6d00; - .timescale -9 -12; -L_0x17ff310/d .functor NAND 1, L_0x17f1ef0, L_0x17ffdc0, C4<1>, C4<1>; -L_0x17ff310 .delay (10000,10000,10000) L_0x17ff310/d; -L_0x17ff450/d .functor NOT 1, L_0x17ff310, C4<0>, C4<0>, C4<0>; -L_0x17ff450 .delay (10000,10000,10000) L_0x17ff450/d; -v0x17c7520_0 .net "A", 0 0, L_0x17f1ef0; 1 drivers -v0x17c75e0_0 .net "AandB", 0 0, L_0x17ff450; 1 drivers -v0x17c7660_0 .net "AnandB", 0 0, L_0x17ff310; 1 drivers -v0x17c7710_0 .net "AndNandOut", 0 0, L_0x17ff8a0; 1 drivers -v0x17c77f0_0 .net "B", 0 0, L_0x17ffdc0; 1 drivers -v0x17c7870_0 .alias "Command", 2 0, v0x17dc9d0_0; -L_0x17ffa70 .part v0x17dda90_0, 0, 1; -S_0x17c6f80 .scope module, "potato" "TwoInMux" 2 66, 2 8, S_0x17c6e90; - .timescale -9 -12; -L_0x17ff580/d .functor NOT 1, L_0x17ffa70, C4<0>, C4<0>, C4<0>; -L_0x17ff580 .delay (10000,10000,10000) L_0x17ff580/d; -L_0x17ff640/d .functor AND 1, L_0x17ff450, L_0x17ff580, C4<1>, C4<1>; -L_0x17ff640 .delay (20000,20000,20000) L_0x17ff640/d; -L_0x17ff750/d .functor AND 1, L_0x17ff310, L_0x17ffa70, C4<1>, C4<1>; -L_0x17ff750 .delay (20000,20000,20000) L_0x17ff750/d; -L_0x17ff8a0/d .functor OR 1, L_0x17ff640, L_0x17ff750, C4<0>, C4<0>; -L_0x17ff8a0 .delay (20000,20000,20000) L_0x17ff8a0/d; -v0x17c7070_0 .net "S", 0 0, L_0x17ffa70; 1 drivers -v0x17c7110_0 .alias "in0", 0 0, v0x17c75e0_0; -v0x17c71b0_0 .alias "in1", 0 0, v0x17c7660_0; -v0x17c7250_0 .net "nS", 0 0, L_0x17ff580; 1 drivers -v0x17c7300_0 .net "out0", 0 0, L_0x17ff640; 1 drivers -v0x17c73a0_0 .net "out1", 0 0, L_0x17ff750; 1 drivers -v0x17c7480_0 .alias "outfinal", 0 0, v0x17c7710_0; -S_0x17c19c0 .scope module, "trial2" "OrNorXor32" 2 284, 2 180, S_0x17bb1b0; - .timescale -9 -12; -P_0x17c0b18 .param/l "size" 2 187, +C4<0100>; -v0x17c6900_0 .alias "A", 3 0, v0x17dc7b0_0; -v0x17c6980_0 .alias "B", 3 0, v0x17dc8d0_0; -v0x17c6a00_0 .alias "Command", 2 0, v0x17dc9d0_0; -v0x17c6b10_0 .alias "OrNorXorOut", 3 0, v0x17ddb90_0; -L_0x18019c0 .part/pv L_0x1801750, 1, 1, 4; -L_0x1801a60 .part v0x17dd890_0, 1, 1; -L_0x1801b00 .part v0x17dda10_0, 1, 1; -L_0x1802cc0 .part/pv L_0x1802a50, 2, 1, 4; -L_0x1802d60 .part v0x17dd890_0, 2, 1; -L_0x1802e00 .part v0x17dda10_0, 2, 1; -L_0x1803fc0 .part/pv L_0x1803d50, 3, 1, 4; -L_0x1804060 .part v0x17dd890_0, 3, 1; -L_0x1804100 .part v0x17dda10_0, 3, 1; -L_0x18052b0 .part/pv L_0x1805040, 0, 1, 4; -L_0x18053b0 .part v0x17dd890_0, 0, 1; -L_0x1805450 .part v0x17dda10_0, 0, 1; -S_0x17c56f0 .scope module, "attempt2" "OrNorXor" 2 195, 2 70, S_0x17c19c0; - .timescale -9 -12; -L_0x18041a0/d .functor NOR 1, L_0x18053b0, L_0x1805450, C4<0>, C4<0>; -L_0x18041a0 .delay (10000,10000,10000) L_0x18041a0/d; -L_0x18042a0/d .functor NOT 1, L_0x18041a0, C4<0>, C4<0>, C4<0>; -L_0x18042a0 .delay (10000,10000,10000) L_0x18042a0/d; -L_0x18043d0/d .functor NAND 1, L_0x18053b0, L_0x1805450, C4<1>, C4<1>; -L_0x18043d0 .delay (10000,10000,10000) L_0x18043d0/d; -L_0x1804530/d .functor NAND 1, L_0x18043d0, L_0x18042a0, C4<1>, C4<1>; -L_0x1804530 .delay (10000,10000,10000) L_0x1804530/d; -L_0x1804640/d .functor NOT 1, L_0x1804530, C4<0>, C4<0>, C4<0>; -L_0x1804640 .delay (10000,10000,10000) L_0x1804640/d; -v0x17c6240_0 .net "A", 0 0, L_0x18053b0; 1 drivers -v0x17c62e0_0 .net "AnandB", 0 0, L_0x18043d0; 1 drivers -v0x17c6380_0 .net "AnorB", 0 0, L_0x18041a0; 1 drivers -v0x17c6400_0 .net "AorB", 0 0, L_0x18042a0; 1 drivers -v0x17c64e0_0 .net "AxorB", 0 0, L_0x1804640; 1 drivers -v0x17c6590_0 .net "B", 0 0, L_0x1805450; 1 drivers -v0x17c6650_0 .alias "Command", 2 0, v0x17dc9d0_0; -v0x17c66d0_0 .net "OrNorXorOut", 0 0, L_0x1805040; 1 drivers -v0x17c6750_0 .net "XorNor", 0 0, L_0x1804ac0; 1 drivers -v0x17c6820_0 .net "nXor", 0 0, L_0x1804530; 1 drivers -L_0x1804c40 .part v0x17dda90_0, 2, 1; -L_0x1805210 .part v0x17dda90_0, 0, 1; -S_0x17c5cd0 .scope module, "mux0" "TwoInMux" 2 89, 2 8, S_0x17c56f0; - .timescale -9 -12; -L_0x18047a0/d .functor NOT 1, L_0x1804c40, C4<0>, C4<0>, C4<0>; -L_0x18047a0 .delay (10000,10000,10000) L_0x18047a0/d; -L_0x1804860/d .functor AND 1, L_0x1804640, L_0x18047a0, C4<1>, C4<1>; -L_0x1804860 .delay (20000,20000,20000) L_0x1804860/d; -L_0x1804970/d .functor AND 1, L_0x18041a0, L_0x1804c40, C4<1>, C4<1>; -L_0x1804970 .delay (20000,20000,20000) L_0x1804970/d; -L_0x1804ac0/d .functor OR 1, L_0x1804860, L_0x1804970, C4<0>, C4<0>; -L_0x1804ac0 .delay (20000,20000,20000) L_0x1804ac0/d; -v0x17c5dc0_0 .net "S", 0 0, L_0x1804c40; 1 drivers -v0x17c5e80_0 .alias "in0", 0 0, v0x17c64e0_0; -v0x17c5f20_0 .alias "in1", 0 0, v0x17c6380_0; -v0x17c5fc0_0 .net "nS", 0 0, L_0x18047a0; 1 drivers -v0x17c6040_0 .net "out0", 0 0, L_0x1804860; 1 drivers -v0x17c60e0_0 .net "out1", 0 0, L_0x1804970; 1 drivers -v0x17c61c0_0 .alias "outfinal", 0 0, v0x17c6750_0; -S_0x17c57e0 .scope module, "mux1" "TwoInMux" 2 90, 2 8, S_0x17c56f0; - .timescale -9 -12; -L_0x1804ce0/d .functor NOT 1, L_0x1805210, C4<0>, C4<0>, C4<0>; -L_0x1804ce0 .delay (10000,10000,10000) L_0x1804ce0/d; -L_0x1804da0/d .functor AND 1, L_0x1804ac0, L_0x1804ce0, C4<1>, C4<1>; -L_0x1804da0 .delay (20000,20000,20000) L_0x1804da0/d; -L_0x1804ef0/d .functor AND 1, L_0x18042a0, L_0x1805210, C4<1>, C4<1>; -L_0x1804ef0 .delay (20000,20000,20000) L_0x1804ef0/d; -L_0x1805040/d .functor OR 1, L_0x1804da0, L_0x1804ef0, C4<0>, C4<0>; -L_0x1805040 .delay (20000,20000,20000) L_0x1805040/d; -v0x17c58d0_0 .net "S", 0 0, L_0x1805210; 1 drivers -v0x17c5950_0 .alias "in0", 0 0, v0x17c6750_0; -v0x17c59d0_0 .alias "in1", 0 0, v0x17c6400_0; -v0x17c5a70_0 .net "nS", 0 0, L_0x1804ce0; 1 drivers -v0x17c5af0_0 .net "out0", 0 0, L_0x1804da0; 1 drivers -v0x17c5b90_0 .net "out1", 0 0, L_0x1804ef0; 1 drivers -v0x17c5c30_0 .alias "outfinal", 0 0, v0x17c66d0_0; -S_0x17c42f0 .scope generate, "orbits[1]" "orbits[1]" 2 199, 2 199, S_0x17c19c0; - .timescale -9 -12; -P_0x17c3fd8 .param/l "i" 2 199, +C4<01>; -S_0x17c4420 .scope module, "attempt" "OrNorXor" 2 201, 2 70, S_0x17c42f0; - .timescale -9 -12; -L_0x1800710/d .functor NOR 1, L_0x1801a60, L_0x1801b00, C4<0>, C4<0>; -L_0x1800710 .delay (10000,10000,10000) L_0x1800710/d; -L_0x18009b0/d .functor NOT 1, L_0x1800710, C4<0>, C4<0>, C4<0>; -L_0x18009b0 .delay (10000,10000,10000) L_0x18009b0/d; -L_0x1800ae0/d .functor NAND 1, L_0x1801a60, L_0x1801b00, C4<1>, C4<1>; -L_0x1800ae0 .delay (10000,10000,10000) L_0x1800ae0/d; -L_0x1800c40/d .functor NAND 1, L_0x1800ae0, L_0x18009b0, C4<1>, C4<1>; -L_0x1800c40 .delay (10000,10000,10000) L_0x1800c40/d; -L_0x1800d50/d .functor NOT 1, L_0x1800c40, C4<0>, C4<0>, C4<0>; -L_0x1800d50 .delay (10000,10000,10000) L_0x1800d50/d; -v0x17c4fb0_0 .net "A", 0 0, L_0x1801a60; 1 drivers -v0x17c5050_0 .net "AnandB", 0 0, L_0x1800ae0; 1 drivers -v0x17c50f0_0 .net "AnorB", 0 0, L_0x1800710; 1 drivers -v0x17c51a0_0 .net "AorB", 0 0, L_0x18009b0; 1 drivers -v0x17c5280_0 .net "AxorB", 0 0, L_0x1800d50; 1 drivers -v0x17c5330_0 .net "B", 0 0, L_0x1801b00; 1 drivers -v0x17c53f0_0 .alias "Command", 2 0, v0x17dc9d0_0; -v0x17c5470_0 .net "OrNorXorOut", 0 0, L_0x1801750; 1 drivers -v0x17c5540_0 .net "XorNor", 0 0, L_0x18011d0; 1 drivers -v0x17c5610_0 .net "nXor", 0 0, L_0x1800c40; 1 drivers -L_0x1801350 .part v0x17dda90_0, 2, 1; -L_0x1801920 .part v0x17dda90_0, 0, 1; -S_0x17c4a40 .scope module, "mux0" "TwoInMux" 2 89, 2 8, S_0x17c4420; - .timescale -9 -12; -L_0x1800eb0/d .functor NOT 1, L_0x1801350, C4<0>, C4<0>, C4<0>; -L_0x1800eb0 .delay (10000,10000,10000) L_0x1800eb0/d; -L_0x1800f70/d .functor AND 1, L_0x1800d50, L_0x1800eb0, C4<1>, C4<1>; -L_0x1800f70 .delay (20000,20000,20000) L_0x1800f70/d; -L_0x1801080/d .functor AND 1, L_0x1800710, L_0x1801350, C4<1>, C4<1>; -L_0x1801080 .delay (20000,20000,20000) L_0x1801080/d; -L_0x18011d0/d .functor OR 1, L_0x1800f70, L_0x1801080, C4<0>, C4<0>; -L_0x18011d0 .delay (20000,20000,20000) L_0x18011d0/d; -v0x17c4b30_0 .net "S", 0 0, L_0x1801350; 1 drivers -v0x17c4bf0_0 .alias "in0", 0 0, v0x17c5280_0; -v0x17c4c90_0 .alias "in1", 0 0, v0x17c50f0_0; -v0x17c4d30_0 .net "nS", 0 0, L_0x1800eb0; 1 drivers -v0x17c4db0_0 .net "out0", 0 0, L_0x1800f70; 1 drivers -v0x17c4e50_0 .net "out1", 0 0, L_0x1801080; 1 drivers -v0x17c4f30_0 .alias "outfinal", 0 0, v0x17c5540_0; -S_0x17c4510 .scope module, "mux1" "TwoInMux" 2 90, 2 8, S_0x17c4420; - .timescale -9 -12; -L_0x18013f0/d .functor NOT 1, L_0x1801920, C4<0>, C4<0>, C4<0>; -L_0x18013f0 .delay (10000,10000,10000) L_0x18013f0/d; -L_0x18014b0/d .functor AND 1, L_0x18011d0, L_0x18013f0, C4<1>, C4<1>; -L_0x18014b0 .delay (20000,20000,20000) L_0x18014b0/d; -L_0x1801600/d .functor AND 1, L_0x18009b0, L_0x1801920, C4<1>, C4<1>; -L_0x1801600 .delay (20000,20000,20000) L_0x1801600/d; -L_0x1801750/d .functor OR 1, L_0x18014b0, L_0x1801600, C4<0>, C4<0>; -L_0x1801750 .delay (20000,20000,20000) L_0x1801750/d; -v0x17c4600_0 .net "S", 0 0, L_0x1801920; 1 drivers -v0x17c4680_0 .alias "in0", 0 0, v0x17c5540_0; -v0x17c4700_0 .alias "in1", 0 0, v0x17c51a0_0; -v0x17c47a0_0 .net "nS", 0 0, L_0x18013f0; 1 drivers -v0x17c4820_0 .net "out0", 0 0, L_0x18014b0; 1 drivers -v0x17c48c0_0 .net "out1", 0 0, L_0x1801600; 1 drivers -v0x17c49a0_0 .alias "outfinal", 0 0, v0x17c5470_0; -S_0x17c2ed0 .scope generate, "orbits[2]" "orbits[2]" 2 199, 2 199, S_0x17c19c0; - .timescale -9 -12; -P_0x17c2c98 .param/l "i" 2 199, +C4<010>; -S_0x17c3000 .scope module, "attempt" "OrNorXor" 2 201, 2 70, S_0x17c2ed0; - .timescale -9 -12; -L_0x1801ba0/d .functor NOR 1, L_0x1802d60, L_0x1802e00, C4<0>, C4<0>; -L_0x1801ba0 .delay (10000,10000,10000) L_0x1801ba0/d; -L_0x1801cb0/d .functor NOT 1, L_0x1801ba0, C4<0>, C4<0>, C4<0>; -L_0x1801cb0 .delay (10000,10000,10000) L_0x1801cb0/d; -L_0x1801de0/d .functor NAND 1, L_0x1802d60, L_0x1802e00, C4<1>, C4<1>; -L_0x1801de0 .delay (10000,10000,10000) L_0x1801de0/d; -L_0x1801f40/d .functor NAND 1, L_0x1801de0, L_0x1801cb0, C4<1>, C4<1>; -L_0x1801f40 .delay (10000,10000,10000) L_0x1801f40/d; -L_0x1802050/d .functor NOT 1, L_0x1801f40, C4<0>, C4<0>, C4<0>; -L_0x1802050 .delay (10000,10000,10000) L_0x1802050/d; -v0x17c3bd0_0 .net "A", 0 0, L_0x1802d60; 1 drivers -v0x17c3c70_0 .net "AnandB", 0 0, L_0x1801de0; 1 drivers -v0x17c3d10_0 .net "AnorB", 0 0, L_0x1801ba0; 1 drivers -v0x17c3dc0_0 .net "AorB", 0 0, L_0x1801cb0; 1 drivers -v0x17c3ea0_0 .net "AxorB", 0 0, L_0x1802050; 1 drivers -v0x17c3f50_0 .net "B", 0 0, L_0x1802e00; 1 drivers -v0x17c4010_0 .alias "Command", 2 0, v0x17dc9d0_0; -v0x17c4090_0 .net "OrNorXorOut", 0 0, L_0x1802a50; 1 drivers -v0x17c4140_0 .net "XorNor", 0 0, L_0x18024d0; 1 drivers -v0x17c4210_0 .net "nXor", 0 0, L_0x1801f40; 1 drivers -L_0x1802650 .part v0x17dda90_0, 2, 1; -L_0x1802c20 .part v0x17dda90_0, 0, 1; -S_0x17c3660 .scope module, "mux0" "TwoInMux" 2 89, 2 8, S_0x17c3000; - .timescale -9 -12; -L_0x18021b0/d .functor NOT 1, L_0x1802650, C4<0>, C4<0>, C4<0>; -L_0x18021b0 .delay (10000,10000,10000) L_0x18021b0/d; -L_0x1802270/d .functor AND 1, L_0x1802050, L_0x18021b0, C4<1>, C4<1>; -L_0x1802270 .delay (20000,20000,20000) L_0x1802270/d; -L_0x1802380/d .functor AND 1, L_0x1801ba0, L_0x1802650, C4<1>, C4<1>; -L_0x1802380 .delay (20000,20000,20000) L_0x1802380/d; -L_0x18024d0/d .functor OR 1, L_0x1802270, L_0x1802380, C4<0>, C4<0>; -L_0x18024d0 .delay (20000,20000,20000) L_0x18024d0/d; -v0x17c3750_0 .net "S", 0 0, L_0x1802650; 1 drivers -v0x17c3810_0 .alias "in0", 0 0, v0x17c3ea0_0; -v0x17c38b0_0 .alias "in1", 0 0, v0x17c3d10_0; -v0x17c3950_0 .net "nS", 0 0, L_0x18021b0; 1 drivers -v0x17c39d0_0 .net "out0", 0 0, L_0x1802270; 1 drivers -v0x17c3a70_0 .net "out1", 0 0, L_0x1802380; 1 drivers -v0x17c3b50_0 .alias "outfinal", 0 0, v0x17c4140_0; -S_0x17c30f0 .scope module, "mux1" "TwoInMux" 2 90, 2 8, S_0x17c3000; - .timescale -9 -12; -L_0x18026f0/d .functor NOT 1, L_0x1802c20, C4<0>, C4<0>, C4<0>; -L_0x18026f0 .delay (10000,10000,10000) L_0x18026f0/d; -L_0x18027b0/d .functor AND 1, L_0x18024d0, L_0x18026f0, C4<1>, C4<1>; -L_0x18027b0 .delay (20000,20000,20000) L_0x18027b0/d; -L_0x1802900/d .functor AND 1, L_0x1801cb0, L_0x1802c20, C4<1>, C4<1>; -L_0x1802900 .delay (20000,20000,20000) L_0x1802900/d; -L_0x1802a50/d .functor OR 1, L_0x18027b0, L_0x1802900, C4<0>, C4<0>; -L_0x1802a50 .delay (20000,20000,20000) L_0x1802a50/d; -v0x17c31e0_0 .net "S", 0 0, L_0x1802c20; 1 drivers -v0x17c3280_0 .alias "in0", 0 0, v0x17c4140_0; -v0x17c3320_0 .alias "in1", 0 0, v0x17c3dc0_0; -v0x17c33c0_0 .net "nS", 0 0, L_0x18026f0; 1 drivers -v0x17c3440_0 .net "out0", 0 0, L_0x18027b0; 1 drivers -v0x17c34e0_0 .net "out1", 0 0, L_0x1802900; 1 drivers -v0x17c35c0_0 .alias "outfinal", 0 0, v0x17c4090_0; -S_0x17c1b30 .scope generate, "orbits[3]" "orbits[3]" 2 199, 2 199, S_0x17c19c0; - .timescale -9 -12; -P_0x17c1c28 .param/l "i" 2 199, +C4<011>; -S_0x17c1cc0 .scope module, "attempt" "OrNorXor" 2 201, 2 70, S_0x17c1b30; - .timescale -9 -12; -L_0x1802ee0/d .functor NOR 1, L_0x1804060, L_0x1804100, C4<0>, C4<0>; -L_0x1802ee0 .delay (10000,10000,10000) L_0x1802ee0/d; -L_0x1802fd0/d .functor NOT 1, L_0x1802ee0, C4<0>, C4<0>, C4<0>; -L_0x1802fd0 .delay (10000,10000,10000) L_0x1802fd0/d; -L_0x18030e0/d .functor NAND 1, L_0x1804060, L_0x1804100, C4<1>, C4<1>; -L_0x18030e0 .delay (10000,10000,10000) L_0x18030e0/d; -L_0x1803240/d .functor NAND 1, L_0x18030e0, L_0x1802fd0, C4<1>, C4<1>; -L_0x1803240 .delay (10000,10000,10000) L_0x1803240/d; -L_0x1803350/d .functor NOT 1, L_0x1803240, C4<0>, C4<0>, C4<0>; -L_0x1803350 .delay (10000,10000,10000) L_0x1803350/d; -v0x17c2890_0 .net "A", 0 0, L_0x1804060; 1 drivers -v0x17c2930_0 .net "AnandB", 0 0, L_0x18030e0; 1 drivers -v0x17c29d0_0 .net "AnorB", 0 0, L_0x1802ee0; 1 drivers -v0x17c2a80_0 .net "AorB", 0 0, L_0x1802fd0; 1 drivers -v0x17c2b60_0 .net "AxorB", 0 0, L_0x1803350; 1 drivers -v0x17c2c10_0 .net "B", 0 0, L_0x1804100; 1 drivers -v0x17c2cd0_0 .alias "Command", 2 0, v0x17dc9d0_0; -v0x17c2d50_0 .net "OrNorXorOut", 0 0, L_0x1803d50; 1 drivers -v0x17c2dd0_0 .net "XorNor", 0 0, L_0x18037d0; 1 drivers -v0x17c2e50_0 .net "nXor", 0 0, L_0x1803240; 1 drivers -L_0x1803950 .part v0x17dda90_0, 2, 1; -L_0x1803f20 .part v0x17dda90_0, 0, 1; -S_0x17c2320 .scope module, "mux0" "TwoInMux" 2 89, 2 8, S_0x17c1cc0; - .timescale -9 -12; -L_0x18034b0/d .functor NOT 1, L_0x1803950, C4<0>, C4<0>, C4<0>; -L_0x18034b0 .delay (10000,10000,10000) L_0x18034b0/d; -L_0x1803570/d .functor AND 1, L_0x1803350, L_0x18034b0, C4<1>, C4<1>; -L_0x1803570 .delay (20000,20000,20000) L_0x1803570/d; -L_0x1803680/d .functor AND 1, L_0x1802ee0, L_0x1803950, C4<1>, C4<1>; -L_0x1803680 .delay (20000,20000,20000) L_0x1803680/d; -L_0x18037d0/d .functor OR 1, L_0x1803570, L_0x1803680, C4<0>, C4<0>; -L_0x18037d0 .delay (20000,20000,20000) L_0x18037d0/d; -v0x17c2410_0 .net "S", 0 0, L_0x1803950; 1 drivers -v0x17c24d0_0 .alias "in0", 0 0, v0x17c2b60_0; -v0x17c2570_0 .alias "in1", 0 0, v0x17c29d0_0; -v0x17c2610_0 .net "nS", 0 0, L_0x18034b0; 1 drivers -v0x17c2690_0 .net "out0", 0 0, L_0x1803570; 1 drivers -v0x17c2730_0 .net "out1", 0 0, L_0x1803680; 1 drivers -v0x17c2810_0 .alias "outfinal", 0 0, v0x17c2dd0_0; -S_0x17c1db0 .scope module, "mux1" "TwoInMux" 2 90, 2 8, S_0x17c1cc0; - .timescale -9 -12; -L_0x18039f0/d .functor NOT 1, L_0x1803f20, C4<0>, C4<0>, C4<0>; -L_0x18039f0 .delay (10000,10000,10000) L_0x18039f0/d; -L_0x1803ab0/d .functor AND 1, L_0x18037d0, L_0x18039f0, C4<1>, C4<1>; -L_0x1803ab0 .delay (20000,20000,20000) L_0x1803ab0/d; -L_0x1803c00/d .functor AND 1, L_0x1802fd0, L_0x1803f20, C4<1>, C4<1>; -L_0x1803c00 .delay (20000,20000,20000) L_0x1803c00/d; -L_0x1803d50/d .functor OR 1, L_0x1803ab0, L_0x1803c00, C4<0>, C4<0>; -L_0x1803d50 .delay (20000,20000,20000) L_0x1803d50/d; -v0x17c1ea0_0 .net "S", 0 0, L_0x1803f20; 1 drivers -v0x17c1f40_0 .alias "in0", 0 0, v0x17c2dd0_0; -v0x17c1fe0_0 .alias "in1", 0 0, v0x17c2a80_0; -v0x17c2080_0 .net "nS", 0 0, L_0x18039f0; 1 drivers -v0x17c2100_0 .net "out0", 0 0, L_0x1803ab0; 1 drivers -v0x17c21a0_0 .net "out1", 0 0, L_0x1803c00; 1 drivers -v0x17c2280_0 .alias "outfinal", 0 0, v0x17c2d50_0; -S_0x17c1040 .scope module, "ZeroMux0case" "FourInMux" 2 287, 2 29, S_0x17bb1b0; - .timescale -9 -12; -L_0x1805350/d .functor NOT 1, L_0x1805c90, C4<0>, C4<0>, C4<0>; -L_0x1805350 .delay (10000,10000,10000) L_0x1805350/d; -L_0x18055a0/d .functor NOT 1, L_0x17f7960, C4<0>, C4<0>, C4<0>; -L_0x18055a0 .delay (10000,10000,10000) L_0x18055a0/d; -L_0x1805660/d .functor NAND 1, L_0x1805350, L_0x18055a0, L_0x1805f90, C4<1>; -L_0x1805660 .delay (10000,10000,10000) L_0x1805660/d; -L_0x1805750/d .functor NAND 1, L_0x1805c90, L_0x18055a0, L_0x1805dc0, C4<1>; -L_0x1805750 .delay (10000,10000,10000) L_0x1805750/d; -L_0x1805840/d .functor NAND 1, L_0x1805350, L_0x17f7960, L_0x1805e60, C4<1>; -L_0x1805840 .delay (10000,10000,10000) L_0x1805840/d; -L_0x1805930/d .functor NAND 1, L_0x1805c90, L_0x17f7960, L_0x1806220, C4<1>; -L_0x1805930 .delay (10000,10000,10000) L_0x1805930/d; -L_0x1805a10/d .functor NAND 1, L_0x1805660, L_0x1805750, L_0x1805840, L_0x1805930; -L_0x1805a10 .delay (10000,10000,10000) L_0x1805a10/d; -v0x17c1130_0 .net "S0", 0 0, L_0x1805c90; 1 drivers -v0x17c11f0_0 .net "S1", 0 0, L_0x17f7960; 1 drivers -v0x17c1290_0 .net "in0", 0 0, L_0x1805f90; 1 drivers -v0x17c1330_0 .net "in1", 0 0, L_0x1805dc0; 1 drivers -v0x17c13b0_0 .net "in2", 0 0, L_0x1805e60; 1 drivers -v0x17c1450_0 .net "in3", 0 0, L_0x1806220; 1 drivers -v0x17c14f0_0 .net "nS0", 0 0, L_0x1805350; 1 drivers -v0x17c1590_0 .net "nS1", 0 0, L_0x18055a0; 1 drivers -v0x17c1630_0 .net "out", 0 0, L_0x1805a10; 1 drivers -v0x17c16d0_0 .net "out0", 0 0, L_0x1805660; 1 drivers -v0x17c1770_0 .net "out1", 0 0, L_0x1805750; 1 drivers -v0x17c1810_0 .net "out2", 0 0, L_0x1805840; 1 drivers -v0x17c1920_0 .net "out3", 0 0, L_0x1805930; 1 drivers -S_0x17c0680 .scope module, "OneMux0case" "FourInMux" 2 288, 2 29, S_0x17bb1b0; - .timescale -9 -12; -L_0x18062c0/d .functor NOT 1, L_0x1806030, C4<0>, C4<0>, C4<0>; -L_0x18062c0 .delay (10000,10000,10000) L_0x18062c0/d; -L_0x1806370/d .functor NOT 1, L_0x1806160, C4<0>, C4<0>, C4<0>; -L_0x1806370 .delay (10000,10000,10000) L_0x1806370/d; -L_0x18063d0/d .functor NAND 1, L_0x18062c0, L_0x1806370, L_0x1806a50, C4<1>; -L_0x18063d0 .delay (10000,10000,10000) L_0x18063d0/d; -L_0x1806510/d .functor NAND 1, L_0x1806030, L_0x1806370, L_0x1806af0, C4<1>; -L_0x1806510 .delay (10000,10000,10000) L_0x1806510/d; -L_0x1806600/d .functor NAND 1, L_0x18062c0, L_0x1806160, L_0x1806b90, C4<1>; -L_0x1806600 .delay (10000,10000,10000) L_0x1806600/d; -L_0x18066f0/d .functor NAND 1, L_0x1806030, L_0x1806160, L_0x1806f50, C4<1>; -L_0x18066f0 .delay (10000,10000,10000) L_0x18066f0/d; -L_0x18067d0/d .functor NAND 1, L_0x18063d0, L_0x1806510, L_0x1806600, L_0x18066f0; -L_0x18067d0 .delay (10000,10000,10000) L_0x18067d0/d; -v0x17c0770_0 .net "S0", 0 0, L_0x1806030; 1 drivers -v0x17c0830_0 .net "S1", 0 0, L_0x1806160; 1 drivers -v0x17c08d0_0 .net "in0", 0 0, L_0x1806a50; 1 drivers -v0x17c0970_0 .net "in1", 0 0, L_0x1806af0; 1 drivers -v0x17c09f0_0 .net "in2", 0 0, L_0x1806b90; 1 drivers -v0x17c0a90_0 .net "in3", 0 0, L_0x1806f50; 1 drivers -v0x17c0b70_0 .net "nS0", 0 0, L_0x18062c0; 1 drivers -v0x17c0c10_0 .net "nS1", 0 0, L_0x1806370; 1 drivers -v0x17c0cb0_0 .net "out", 0 0, L_0x18067d0; 1 drivers -v0x17c0d50_0 .net "out0", 0 0, L_0x18063d0; 1 drivers -v0x17c0df0_0 .net "out1", 0 0, L_0x1806510; 1 drivers -v0x17c0e90_0 .net "out2", 0 0, L_0x1806600; 1 drivers -v0x17c0fa0_0 .net "out3", 0 0, L_0x18066f0; 1 drivers -S_0x17c0130 .scope module, "TwoMux0case" "TwoInMux" 2 289, 2 8, S_0x17bb1b0; - .timescale -9 -12; -L_0x1806ce0/d .functor NOT 1, L_0x1807500, C4<0>, C4<0>, C4<0>; -L_0x1806ce0 .delay (10000,10000,10000) L_0x1806ce0/d; -L_0x1806dd0/d .functor AND 1, L_0x1807040, L_0x1806ce0, C4<1>, C4<1>; -L_0x1806dd0 .delay (20000,20000,20000) L_0x1806dd0/d; -L_0x1807270/d .functor AND 1, L_0x18077e0, L_0x1807500, C4<1>, C4<1>; -L_0x1807270 .delay (20000,20000,20000) L_0x1807270/d; -L_0x1807320/d .functor OR 1, L_0x1806dd0, L_0x1807270, C4<0>, C4<0>; -L_0x1807320 .delay (20000,20000,20000) L_0x1807320/d; -v0x17c0220_0 .net "S", 0 0, L_0x1807500; 1 drivers -v0x17c02e0_0 .net "in0", 0 0, L_0x1807040; 1 drivers -v0x17c0380_0 .net "in1", 0 0, L_0x18077e0; 1 drivers -v0x17c0420_0 .net "nS", 0 0, L_0x1806ce0; 1 drivers -v0x17c04a0_0 .net "out0", 0 0, L_0x1806dd0; 1 drivers -v0x17c0540_0 .net "out1", 0 0, L_0x1807270; 1 drivers -v0x17c05e0_0 .net "outfinal", 0 0, L_0x1807320; 1 drivers -S_0x17be710 .scope generate, "muxbits[1]" "muxbits[1]" 2 295, 2 295, S_0x17bb1b0; - .timescale -9 -12; -P_0x17bd868 .param/l "i" 2 295, +C4<01>; -S_0x17bf7b0 .scope module, "ZeroMux" "FourInMux" 2 297, 2 29, S_0x17be710; - .timescale -9 -12; -L_0x17f02f0/d .functor NOT 1, L_0x17f0c30, C4<0>, C4<0>, C4<0>; -L_0x17f02f0 .delay (10000,10000,10000) L_0x17f02f0/d; -L_0x17f0540/d .functor NOT 1, L_0x17f0d60, C4<0>, C4<0>, C4<0>; -L_0x17f0540 .delay (10000,10000,10000) L_0x17f0540/d; -L_0x17f0600/d .functor NAND 1, L_0x17f02f0, L_0x17f0540, L_0x17f0e90, C4<1>; -L_0x17f0600 .delay (10000,10000,10000) L_0x17f0600/d; -L_0x17f06f0/d .functor NAND 1, L_0x17f0c30, L_0x17f0540, L_0x17f0f30, C4<1>; -L_0x17f06f0 .delay (10000,10000,10000) L_0x17f06f0/d; -L_0x17f07e0/d .functor NAND 1, L_0x17f02f0, L_0x17f0d60, L_0x17f0fd0, C4<1>; -L_0x17f07e0 .delay (10000,10000,10000) L_0x17f07e0/d; -L_0x17f08d0/d .functor NAND 1, L_0x17f0c30, L_0x17f0d60, L_0x17f11d0, C4<1>; -L_0x17f08d0 .delay (10000,10000,10000) L_0x17f08d0/d; -L_0x17f09b0/d .functor NAND 1, L_0x17f0600, L_0x17f06f0, L_0x17f07e0, L_0x17f08d0; -L_0x17f09b0 .delay (10000,10000,10000) L_0x17f09b0/d; -v0x17bf8a0_0 .net "S0", 0 0, L_0x17f0c30; 1 drivers -v0x17bf960_0 .net "S1", 0 0, L_0x17f0d60; 1 drivers -v0x17bfa00_0 .net "in0", 0 0, L_0x17f0e90; 1 drivers -v0x17bfaa0_0 .net "in1", 0 0, L_0x17f0f30; 1 drivers -v0x17bfb20_0 .net "in2", 0 0, L_0x17f0fd0; 1 drivers -v0x17bfbc0_0 .net "in3", 0 0, L_0x17f11d0; 1 drivers -v0x17bfc60_0 .net "nS0", 0 0, L_0x17f02f0; 1 drivers -v0x17bfd00_0 .net "nS1", 0 0, L_0x17f0540; 1 drivers -v0x17bfda0_0 .net "out", 0 0, L_0x17f09b0; 1 drivers -v0x17bfe40_0 .net "out0", 0 0, L_0x17f0600; 1 drivers -v0x17bfee0_0 .net "out1", 0 0, L_0x17f06f0; 1 drivers -v0x17bff80_0 .net "out2", 0 0, L_0x17f07e0; 1 drivers -v0x17c0090_0 .net "out3", 0 0, L_0x17f08d0; 1 drivers -S_0x17bedf0 .scope module, "OneMux" "FourInMux" 2 298, 2 29, S_0x17be710; - .timescale -9 -12; -L_0x17f1270/d .functor NOT 1, L_0x17f1b90, C4<0>, C4<0>, C4<0>; -L_0x17f1270 .delay (10000,10000,10000) L_0x17f1270/d; -L_0x17f1360/d .functor NOT 1, L_0x17f1cc0, C4<0>, C4<0>, C4<0>; -L_0x17f1360 .delay (10000,10000,10000) L_0x17f1360/d; -L_0x17f1400/d .functor NAND 1, L_0x17f1270, L_0x17f1360, L_0x17f1e50, C4<1>; -L_0x17f1400 .delay (10000,10000,10000) L_0x17f1400/d; -L_0x17f1540/d .functor NAND 1, L_0x17f1b90, L_0x17f1360, L_0x17f2000, C4<1>; -L_0x17f1540 .delay (10000,10000,10000) L_0x17f1540/d; -L_0x17f1630/d .functor NAND 1, L_0x17f1270, L_0x17f1cc0, L_0x17f20a0, C4<1>; -L_0x17f1630 .delay (10000,10000,10000) L_0x17f1630/d; -L_0x17f1720/d .functor NAND 1, L_0x17f1b90, L_0x17f1cc0, L_0x17f2140, C4<1>; -L_0x17f1720 .delay (10000,10000,10000) L_0x17f1720/d; -L_0x17f1890/d .functor NAND 1, L_0x17f1400, L_0x17f1540, L_0x17f1630, L_0x17f1720; -L_0x17f1890 .delay (10000,10000,10000) L_0x17f1890/d; -v0x17beee0_0 .net "S0", 0 0, L_0x17f1b90; 1 drivers -v0x17befa0_0 .net "S1", 0 0, L_0x17f1cc0; 1 drivers -v0x17bf040_0 .net "in0", 0 0, L_0x17f1e50; 1 drivers -v0x17bf0e0_0 .net "in1", 0 0, L_0x17f2000; 1 drivers -v0x17bf160_0 .net "in2", 0 0, L_0x17f20a0; 1 drivers -v0x17bf200_0 .net "in3", 0 0, L_0x17f2140; 1 drivers -v0x17bf2e0_0 .net "nS0", 0 0, L_0x17f1270; 1 drivers -v0x17bf380_0 .net "nS1", 0 0, L_0x17f1360; 1 drivers -v0x17bf420_0 .net "out", 0 0, L_0x17f1890; 1 drivers -v0x17bf4c0_0 .net "out0", 0 0, L_0x17f1400; 1 drivers -v0x17bf560_0 .net "out1", 0 0, L_0x17f1540; 1 drivers -v0x17bf600_0 .net "out2", 0 0, L_0x17f1630; 1 drivers -v0x17bf710_0 .net "out3", 0 0, L_0x17f1720; 1 drivers -S_0x17be880 .scope module, "TwoMux" "TwoInMux" 2 299, 2 8, S_0x17be710; - .timescale -9 -12; -L_0x17f1df0/d .functor NOT 1, L_0x17f2690, C4<0>, C4<0>, C4<0>; -L_0x17f1df0 .delay (10000,10000,10000) L_0x17f1df0/d; -L_0x17f2280/d .functor AND 1, L_0x17f2730, L_0x17f1df0, C4<1>, C4<1>; -L_0x17f2280 .delay (20000,20000,20000) L_0x17f2280/d; -L_0x17f2370/d .functor AND 1, L_0x17f2870, L_0x17f2690, C4<1>, C4<1>; -L_0x17f2370 .delay (20000,20000,20000) L_0x17f2370/d; -L_0x17f2460/d .functor OR 1, L_0x17f2280, L_0x17f2370, C4<0>, C4<0>; -L_0x17f2460 .delay (20000,20000,20000) L_0x17f2460/d; -v0x17be970_0 .net "S", 0 0, L_0x17f2690; 1 drivers -v0x17bea10_0 .net "in0", 0 0, L_0x17f2730; 1 drivers -v0x17beab0_0 .net "in1", 0 0, L_0x17f2870; 1 drivers -v0x17beb50_0 .net "nS", 0 0, L_0x17f1df0; 1 drivers -v0x17bebd0_0 .net "out0", 0 0, L_0x17f2280; 1 drivers -v0x17bec70_0 .net "out1", 0 0, L_0x17f2370; 1 drivers -v0x17bed50_0 .net "outfinal", 0 0, L_0x17f2460; 1 drivers -S_0x17bccf0 .scope generate, "muxbits[2]" "muxbits[2]" 2 295, 2 295, S_0x17bb1b0; - .timescale -9 -12; -P_0x17bbe48 .param/l "i" 2 295, +C4<010>; -S_0x17bdd90 .scope module, "ZeroMux" "FourInMux" 2 297, 2 29, S_0x17bccf0; - .timescale -9 -12; -L_0x17e9500/d .functor NOT 1, L_0x17f3290, C4<0>, C4<0>, C4<0>; -L_0x17e9500 .delay (10000,10000,10000) L_0x17e9500/d; -L_0x17f2ae0/d .functor NOT 1, L_0x17f29b0, C4<0>, C4<0>, C4<0>; -L_0x17f2ae0 .delay (10000,10000,10000) L_0x17f2ae0/d; -L_0x17f2b80/d .functor NAND 1, L_0x17e9500, L_0x17f2ae0, L_0x17f3500, C4<1>; -L_0x17f2b80 .delay (10000,10000,10000) L_0x17f2b80/d; -L_0x17f2cc0/d .functor NAND 1, L_0x17f3290, L_0x17f2ae0, L_0x17f33c0, C4<1>; -L_0x17f2cc0 .delay (10000,10000,10000) L_0x17f2cc0/d; -L_0x17f2db0/d .functor NAND 1, L_0x17e9500, L_0x17f29b0, L_0x17f3660, C4<1>; -L_0x17f2db0 .delay (10000,10000,10000) L_0x17f2db0/d; -L_0x17f2ea0/d .functor NAND 1, L_0x17f3290, L_0x17f29b0, L_0x17f35a0, C4<1>; -L_0x17f2ea0 .delay (10000,10000,10000) L_0x17f2ea0/d; -L_0x17f2fe0/d .functor NAND 1, L_0x17f2b80, L_0x17f2cc0, L_0x17f2db0, L_0x17f2ea0; -L_0x17f2fe0 .delay (10000,10000,10000) L_0x17f2fe0/d; -v0x17bde80_0 .net "S0", 0 0, L_0x17f3290; 1 drivers -v0x17bdf40_0 .net "S1", 0 0, L_0x17f29b0; 1 drivers -v0x17bdfe0_0 .net "in0", 0 0, L_0x17f3500; 1 drivers -v0x17be080_0 .net "in1", 0 0, L_0x17f33c0; 1 drivers -v0x17be100_0 .net "in2", 0 0, L_0x17f3660; 1 drivers -v0x17be1a0_0 .net "in3", 0 0, L_0x17f35a0; 1 drivers -v0x17be240_0 .net "nS0", 0 0, L_0x17e9500; 1 drivers -v0x17be2e0_0 .net "nS1", 0 0, L_0x17f2ae0; 1 drivers -v0x17be380_0 .net "out", 0 0, L_0x17f2fe0; 1 drivers -v0x17be420_0 .net "out0", 0 0, L_0x17f2b80; 1 drivers -v0x17be4c0_0 .net "out1", 0 0, L_0x17f2cc0; 1 drivers -v0x17be560_0 .net "out2", 0 0, L_0x17f2db0; 1 drivers -v0x17be670_0 .net "out3", 0 0, L_0x17f2ea0; 1 drivers -S_0x17bd3d0 .scope module, "OneMux" "FourInMux" 2 298, 2 29, S_0x17bccf0; - .timescale -9 -12; -L_0x17f3870/d .functor NOT 1, L_0x17f3750, C4<0>, C4<0>, C4<0>; -L_0x17f3870 .delay (10000,10000,10000) L_0x17f3870/d; -L_0x17f3960/d .functor NOT 1, L_0x17e2910, C4<0>, C4<0>, C4<0>; -L_0x17f3960 .delay (10000,10000,10000) L_0x17f3960/d; -L_0x17f3a00/d .functor NAND 1, L_0x17f3870, L_0x17f3960, L_0x17f4170, C4<1>; -L_0x17f3a00 .delay (10000,10000,10000) L_0x17f3a00/d; -L_0x17f3b40/d .functor NAND 1, L_0x17f3750, L_0x17f3960, L_0x17e2b30, C4<1>; -L_0x17f3b40 .delay (10000,10000,10000) L_0x17f3b40/d; -L_0x17f3c30/d .functor NAND 1, L_0x17f3870, L_0x17e2910, L_0x17e2a40, C4<1>; -L_0x17f3c30 .delay (10000,10000,10000) L_0x17f3c30/d; -L_0x17f3d50/d .functor NAND 1, L_0x17f3750, L_0x17e2910, L_0x17f4af0, C4<1>; -L_0x17f3d50 .delay (10000,10000,10000) L_0x17f3d50/d; -L_0x17f3ec0/d .functor NAND 1, L_0x17f3a00, L_0x17f3b40, L_0x17f3c30, L_0x17f3d50; -L_0x17f3ec0 .delay (10000,10000,10000) L_0x17f3ec0/d; -v0x17bd4c0_0 .net "S0", 0 0, L_0x17f3750; 1 drivers -v0x17bd580_0 .net "S1", 0 0, L_0x17e2910; 1 drivers -v0x17bd620_0 .net "in0", 0 0, L_0x17f4170; 1 drivers -v0x17bd6c0_0 .net "in1", 0 0, L_0x17e2b30; 1 drivers -v0x17bd740_0 .net "in2", 0 0, L_0x17e2a40; 1 drivers -v0x17bd7e0_0 .net "in3", 0 0, L_0x17f4af0; 1 drivers -v0x17bd8c0_0 .net "nS0", 0 0, L_0x17f3870; 1 drivers -v0x17bd960_0 .net "nS1", 0 0, L_0x17f3960; 1 drivers -v0x17bda00_0 .net "out", 0 0, L_0x17f3ec0; 1 drivers -v0x17bdaa0_0 .net "out0", 0 0, L_0x17f3a00; 1 drivers -v0x17bdb40_0 .net "out1", 0 0, L_0x17f3b40; 1 drivers -v0x17bdbe0_0 .net "out2", 0 0, L_0x17f3c30; 1 drivers -v0x17bdcf0_0 .net "out3", 0 0, L_0x17f3d50; 1 drivers -S_0x17bce60 .scope module, "TwoMux" "TwoInMux" 2 299, 2 8, S_0x17bccf0; - .timescale -9 -12; -L_0x17e2bd0/d .functor NOT 1, L_0x17f5020, C4<0>, C4<0>, C4<0>; -L_0x17e2bd0 .delay (10000,10000,10000) L_0x17e2bd0/d; -L_0x17f4ca0/d .functor AND 1, L_0x17f4b90, L_0x17e2bd0, C4<1>, C4<1>; -L_0x17f4ca0 .delay (20000,20000,20000) L_0x17f4ca0/d; -L_0x17f4d50/d .functor AND 1, L_0x17f5270, L_0x17f5020, C4<1>, C4<1>; -L_0x17f4d50 .delay (20000,20000,20000) L_0x17f4d50/d; -L_0x17f4e40/d .functor OR 1, L_0x17f4ca0, L_0x17f4d50, C4<0>, C4<0>; -L_0x17f4e40 .delay (20000,20000,20000) L_0x17f4e40/d; -v0x17bcf50_0 .net "S", 0 0, L_0x17f5020; 1 drivers -v0x17bcff0_0 .net "in0", 0 0, L_0x17f4b90; 1 drivers -v0x17bd090_0 .net "in1", 0 0, L_0x17f5270; 1 drivers -v0x17bd130_0 .net "nS", 0 0, L_0x17e2bd0; 1 drivers -v0x17bd1b0_0 .net "out0", 0 0, L_0x17f4ca0; 1 drivers -v0x17bd250_0 .net "out1", 0 0, L_0x17f4d50; 1 drivers -v0x17bd330_0 .net "outfinal", 0 0, L_0x17f4e40; 1 drivers -S_0x17bb2e0 .scope generate, "muxbits[3]" "muxbits[3]" 2 295, 2 295, S_0x17bb1b0; - .timescale -9 -12; -P_0x17bb3d8 .param/l "i" 2 295, +C4<011>; -S_0x17bc370 .scope module, "ZeroMux" "FourInMux" 2 297, 2 29, S_0x17bb2e0; - .timescale -9 -12; -L_0x17f50c0/d .functor NOT 1, L_0x17f5c80, C4<0>, C4<0>, C4<0>; -L_0x17f50c0 .delay (10000,10000,10000) L_0x17f50c0/d; -L_0x17f5160/d .functor NOT 1, L_0x17f53a0, C4<0>, C4<0>, C4<0>; -L_0x17f5160 .delay (10000,10000,10000) L_0x17f5160/d; -L_0x17f5510/d .functor NAND 1, L_0x17f50c0, L_0x17f5160, L_0x17f5ef0, C4<1>; -L_0x17f5510 .delay (10000,10000,10000) L_0x17f5510/d; -L_0x17f5650/d .functor NAND 1, L_0x17f5c80, L_0x17f5160, L_0x17e85e0, C4<1>; -L_0x17f5650 .delay (10000,10000,10000) L_0x17f5650/d; -L_0x17f5740/d .functor NAND 1, L_0x17f50c0, L_0x17f53a0, L_0x17f5db0, C4<1>; -L_0x17f5740 .delay (10000,10000,10000) L_0x17f5740/d; -L_0x17f5860/d .functor NAND 1, L_0x17f5c80, L_0x17f53a0, L_0x17f6300, C4<1>; -L_0x17f5860 .delay (10000,10000,10000) L_0x17f5860/d; -L_0x17f59d0/d .functor NAND 1, L_0x17f5510, L_0x17f5650, L_0x17f5740, L_0x17f5860; -L_0x17f59d0 .delay (10000,10000,10000) L_0x17f59d0/d; -v0x17bc460_0 .net "S0", 0 0, L_0x17f5c80; 1 drivers -v0x17bc520_0 .net "S1", 0 0, L_0x17f53a0; 1 drivers -v0x17bc5c0_0 .net "in0", 0 0, L_0x17f5ef0; 1 drivers -v0x17bc660_0 .net "in1", 0 0, L_0x17e85e0; 1 drivers -v0x17bc6e0_0 .net "in2", 0 0, L_0x17f5db0; 1 drivers -v0x17bc780_0 .net "in3", 0 0, L_0x17f6300; 1 drivers -v0x17bc820_0 .net "nS0", 0 0, L_0x17f50c0; 1 drivers -v0x17bc8c0_0 .net "nS1", 0 0, L_0x17f5160; 1 drivers -v0x17bc960_0 .net "out", 0 0, L_0x17f59d0; 1 drivers -v0x17bca00_0 .net "out0", 0 0, L_0x17f5510; 1 drivers -v0x17bcaa0_0 .net "out1", 0 0, L_0x17f5650; 1 drivers -v0x17bcb40_0 .net "out2", 0 0, L_0x17f5740; 1 drivers -v0x17bcc50_0 .net "out3", 0 0, L_0x17f5860; 1 drivers -S_0x17bb9b0 .scope module, "OneMux" "FourInMux" 2 298, 2 29, S_0x17bb2e0; - .timescale -9 -12; -L_0x17e8680/d .functor NOT 1, L_0x17f61a0, C4<0>, C4<0>, C4<0>; -L_0x17e8680 .delay (10000,10000,10000) L_0x17e8680/d; -L_0x17f6430/d .functor NOT 1, L_0x17f6db0, C4<0>, C4<0>, C4<0>; -L_0x17f6430 .delay (10000,10000,10000) L_0x17f6430/d; -L_0x17f64d0/d .functor NAND 1, L_0x17e8680, L_0x17f6430, L_0x17f6c40, C4<1>; -L_0x17f64d0 .delay (10000,10000,10000) L_0x17f64d0/d; -L_0x17f6610/d .functor NAND 1, L_0x17f61a0, L_0x17f6430, L_0x17f6ce0, C4<1>; -L_0x17f6610 .delay (10000,10000,10000) L_0x17f6610/d; -L_0x17f6700/d .functor NAND 1, L_0x17e8680, L_0x17f6db0, L_0x17f7070, C4<1>; -L_0x17f6700 .delay (10000,10000,10000) L_0x17f6700/d; -L_0x17f6820/d .functor NAND 1, L_0x17f61a0, L_0x17f6db0, L_0x17f7160, C4<1>; -L_0x17f6820 .delay (10000,10000,10000) L_0x17f6820/d; -L_0x17f6990/d .functor NAND 1, L_0x17f64d0, L_0x17f6610, L_0x17f6700, L_0x17f6820; -L_0x17f6990 .delay (10000,10000,10000) L_0x17f6990/d; -v0x17bbaa0_0 .net "S0", 0 0, L_0x17f61a0; 1 drivers -v0x17bbb60_0 .net "S1", 0 0, L_0x17f6db0; 1 drivers -v0x17bbc00_0 .net "in0", 0 0, L_0x17f6c40; 1 drivers -v0x17bbca0_0 .net "in1", 0 0, L_0x17f6ce0; 1 drivers -v0x17bbd20_0 .net "in2", 0 0, L_0x17f7070; 1 drivers -v0x17bbdc0_0 .net "in3", 0 0, L_0x17f7160; 1 drivers -v0x17bbea0_0 .net "nS0", 0 0, L_0x17e8680; 1 drivers -v0x17bbf40_0 .net "nS1", 0 0, L_0x17f6430; 1 drivers -v0x17bbfe0_0 .net "out", 0 0, L_0x17f6990; 1 drivers -v0x17bc080_0 .net "out0", 0 0, L_0x17f64d0; 1 drivers -v0x17bc120_0 .net "out1", 0 0, L_0x17f6610; 1 drivers -v0x17bc1c0_0 .net "out2", 0 0, L_0x17f6700; 1 drivers -v0x17bc2d0_0 .net "out3", 0 0, L_0x17f6820; 1 drivers -S_0x17bb450 .scope module, "TwoMux" "TwoInMux" 2 299, 2 8, S_0x17bb2e0; - .timescale -9 -12; -L_0x17f10c0/d .functor NOT 1, L_0x17f78c0, C4<0>, C4<0>, C4<0>; -L_0x17f10c0 .delay (10000,10000,10000) L_0x17f10c0/d; -L_0x17f6ee0/d .functor AND 1, L_0x17f7460, L_0x17f10c0, C4<1>, C4<1>; -L_0x17f6ee0 .delay (20000,20000,20000) L_0x17f6ee0/d; -L_0x17f6fd0/d .functor AND 1, L_0x17f7500, L_0x17f78c0, C4<1>, C4<1>; -L_0x17f6fd0 .delay (20000,20000,20000) L_0x17f6fd0/d; -L_0x17f7650/d .functor OR 1, L_0x17f6ee0, L_0x17f6fd0, C4<0>, C4<0>; -L_0x17f7650 .delay (20000,20000,20000) L_0x17f7650/d; -v0x17bb540_0 .net "S", 0 0, L_0x17f78c0; 1 drivers -v0x17bb5c0_0 .net "in0", 0 0, L_0x17f7460; 1 drivers -v0x17bb640_0 .net "in1", 0 0, L_0x17f7500; 1 drivers -v0x17bb6e0_0 .net "nS", 0 0, L_0x17f10c0; 1 drivers -v0x17bb790_0 .net "out0", 0 0, L_0x17f6ee0; 1 drivers -v0x17bb830_0 .net "out1", 0 0, L_0x17f6fd0; 1 drivers -v0x17bb910_0 .net "outfinal", 0 0, L_0x17f7650; 1 drivers - .scope S_0x1782ed0; -T_0 ; - %vpi_call 3 35 "$display", "Test ALU - Add"; - %vpi_call 3 36 "$display", " A | B |Command|Output | ExpectOut|Cout|OF|subtract|SLTflag"; - %movi 8, 8, 4; - %set/v v0x17dd890_0, 8, 4; - %movi 8, 1, 4; - %set/v v0x17dda10_0, 8, 4; - %set/v v0x17dda90_0, 0, 3; - %delay 1000000, 0; - %vpi_call 3 38 "$display", "%b | %b | %b | %b | Expect 1001| %b | %b ", v0x17dd890_0, v0x17dda10_0, v0x17dda90_0, v0x17dd910_0, v0x17ddd10_0, v0x17ddd90_0; - %vpi_call 3 40 "$display", " A | B |Command|Output | ExpectOut|Cout|OF|subtract|SLTflag"; - %movi 8, 8, 4; - %set/v v0x17dd890_0, 8, 4; - %movi 8, 1, 4; - %set/v v0x17dda10_0, 8, 4; - %set/v v0x17dda90_0, 0, 3; - %delay 1000000, 0; - %vpi_call 3 42 "$display", "%b | %b | %b | %b | Expect 1001| %b | %b ", v0x17dd890_0, v0x17dda10_0, v0x17dda90_0, v0x17ddb10_0, v0x17ddd10_0, v0x17ddd90_0; - %end; - .thread T_0; -# The file index is used to find the file name in the following table. -:file_names 4; - "N/A"; - ""; - "./alu2.v"; - "testing.t.v"; diff --git a/testing.t.v b/testing.t.v index ab5be1b..c1f03e1 100644 --- a/testing.t.v +++ b/testing.t.v @@ -2,6 +2,136 @@ `timescale 1 ns / 1 ps `include "alu2.v" +/* +module testBasicFunctions(); +// we begin by testing the basic AND/NAND, OR/NOR/XOR, and ADD/SUB/SLT modules + +wire AndNandOut; +reg A, B; +reg[2:0] Command; +//reg S; +wire OneBitFinalOut; +wire AddSubSLTSum, carryout, subtract; //overflow - we don't calculate overflow except with the most significant bit, so we don't worry about it here +reg carryin; +wire OrNorXorOut; +reg S0, S1; +reg in0, in1, in2, in3; +wire muxout; + +// test mux functionality: + FourInMux testmux(muxout, S0, S1, in0, in1, in2, in3); +// test ADD/SUB/SLT + MiddleAddSubSLT testadd(AddSubSLTSum, carryout, subtract, A, B, Command, carryin); +// test AND/NAND + AndNand testand(AndNandOut, A, B, Command); +// test OR/NOR/XOR + OrNorXor testor(OrNorXorOut, A, B, Command); + +initial begin +// test mux + $display("Four Input Multiplexer"); + $display("S0 S1 |in0 in1 in2 in3| Output"); + S0 = 0; S1 = 0; in0 = 1'bx; in1 = 0; in2 = 0; in3 = 0; #1000 + $display(" %b %b | %b %b %b %b | %b", S0, S1, in0, in1, in2, in3, muxout); + S0 = 1; S1 = 0; in0 = 0; in1 = 1'bx; in2 = 0; in3 = 0; #1000 + $display(" %b %b | %b %b %b %b | %b", S0, S1, in0, in1, in2, in3, muxout); + S0 = 0; S1 = 1; in0 = 0; in1 = 0; in2 = 1'bx; in3 = 0; #1000 + $display(" %b %b | %b %b %b %b | %b", S0, S1, in0, in1, in2, in3, muxout); + S0 = 1; S1 = 1; in0 = 0; in1 = 0; in2 = 0; in3 = 1'bx; #1000 + $display(" %b %b | %b %b %b %b | %b", S0, S1, in0, in1, in2, in3, muxout); + +// just the adder - proper behavior + $display("Adder/Subtractor"); + $display("A B | Command |Out|ExpectOut|Carryout-Add"); + // adding + A=1;B=1;Command=3'b000; carryin = 0; #1000 + $display("%b %b | %b | %b | 0 | %b", A, B, Command, AddSubSLTSum, carryout); + A=1;B=0;Command=3'b000; carryin = 0; #1000 + $display("%b %b | %b | %b | 1 | %b", A, B, Command, AddSubSLTSum, carryout); + A=0;B=1;Command=3'b000; carryin = 0; #1000 + $display("%b %b | %b | %b | 1 | %b", A, B, Command, AddSubSLTSum, carryout); + A=0;B=0;Command=3'b000; carryin = 0; #1000 + $display("%b %b | %b | %b | 0 | %b", A, B, Command, AddSubSLTSum, carryout); + // subtracting - carrying must be set to 1 for subtraction + $display("A B | Command |Out|ExpectOut|Carryout-Sub"); + A=1;B=1;Command=3'b001; carryin = 1; #1000 + $display("%b %b | %b | %b | 0 | %b", A, B, Command, AddSubSLTSum, carryout); + A=1;B=0;Command=3'b001; carryin = 1; #1000 + $display("%b %b | %b | %b | 1 | %b", A, B, Command, AddSubSLTSum, carryout); + A=0;B=1;Command=3'b001; carryin = 1; #1000 + $display("%b %b | %b | %b | 1 | %b", A, B, Command, AddSubSLTSum, carryout); + A=0;B=0;Command=3'b001; carryin = 1; #1000 + $display("%b %b | %b | %b | 0 | %b", A, B, Command, AddSubSLTSum, carryout); + // SLT - this should look exactly like the subtraction, since nothing has been done to distinguish one from the other + $display("A B | Command |Out|ExpectOut|Carryout-SLT"); + A=1;B=1;Command=3'b011; carryin = 1; #1000 + $display("%b %b | %b | %b | 0 | %b", A, B, Command, AddSubSLTSum, carryout); + A=1;B=0;Command=3'b011; carryin = 1; #1000 + $display("%b %b | %b | %b | 1 | %b", A, B, Command, AddSubSLTSum, carryout); + A=0;B=1;Command=3'b011; carryin = 1; #1000 + $display("%b %b | %b | %b | 1 | %b", A, B, Command, AddSubSLTSum, carryout); + A=0;B=0;Command=3'b011; carryin = 1; #1000 + $display("%b %b | %b | %b | 0 | %b", A, B, Command, AddSubSLTSum, carryout); + +// Exhaustively testing AND/NAND + $display("A B |Command|Out|ExpectOut-AND"); + A=0;B=0;Command=3'b100; #1000 + $display("%b %b | %b | %b | 0", A, B, Command, AndNandOut); + A=0;B=1;Command=3'b100; #1000 + $display("%b %b | %b | %b | 0", A, B, Command, AndNandOut); + A=1;B=0;Command=3'b100; #1000 + $display("%b %b | %b | %b | 0", A, B, Command, AndNandOut); + A=1;B=1;Command=3'b100; #1000 + $display("%b %b | %b | %b | 1", A, B, Command, AndNandOut); + + $display("A B |Command|Out|ExpectOut-NAND"); + A=0;B=0;Command=3'b101; #1000 + $display("%b %b | %b | %b | 1", A, B, Command, AndNandOut); + A=0;B=1;Command=3'b101; #1000 + $display("%b %b | %b | %b | 1", A, B, Command, AndNandOut); + A=1;B=0;Command=3'b101; #1000 + $display("%b %b | %b | %b | 1", A, B, Command, AndNandOut); + A=1;B=1;Command=3'b101; #1000 + $display("%b %b | %b | %b | 0", A, B, Command, AndNandOut); + +// Exhaustively testing OR/NOR/XOR + $display("A B |Command|Out|ExpectOut-OR"); + A=1; B=1; Command=3'b111; #1000 + $display("%b %b | %b | %b | 1", A, B, Command, OrNorXorOut); + A=1; B=0; Command=3'b111; #1000 + $display("%b %b | %b | %b | 1", A, B, Command, OrNorXorOut); + A=0; B=1; Command=3'b111; #1000 + $display("%b %b | %b | %b | 1", A, B, Command, OrNorXorOut); + A=0; B=0; Command=3'b111; #1000 + $display("%b %b | %b | %b | 0", A, B, Command, OrNorXorOut); + + $display("A B |Command|Out|ExpectOut-NOR"); + A=1; B=1; Command=3'b110; #1000 + $display("%b %b | %b | %b | 0", A, B, Command, OrNorXorOut); + A=1; B=0; Command=3'b110; #1000 + $display("%b %b | %b | %b | 0", A, B, Command, OrNorXorOut); + A=0; B=1; Command=3'b110; #1000 + $display("%b %b | %b | %b | 0", A, B, Command, OrNorXorOut); + A=0; B=0; Command=3'b110; #1000 + $display("%b %b | %b | %b | 1", A, B, Command, OrNorXorOut); + + $display("A B |Command|Out|ExpectOut-XOR"); + A=1; B=1; Command=3'b010; #1000 + $display("%b %b | %b | %b | 0", A, B, Command, OrNorXorOut); + A=1; B=0; Command=3'b010; #1000 + $display("%b %b | %b | %b | 1", A, B, Command, OrNorXorOut); + A=0; B=1; Command=3'b010; #1000 + $display("%b %b | %b | %b | 1 ", A, B, Command, OrNorXorOut); + A=0; B=0; Command=3'b010; #1000 + $display("%b %b | %b | %b | 0", A, B, Command, OrNorXorOut); + +end + +endmodule + +*/ + + module test32Adder(); parameter size = 4; @@ -12,6 +142,7 @@ wire [size-1:0] AddSubSLTSum; wire carryout; wire overflow; wire SLTflag; +wire ZeroFlag; wire [size-1:0] subtract; reg [size-1:0] A, B; reg [2:0] Command; @@ -28,66 +159,259 @@ AndNand32 trial1(AndNandOut, A, B, Command); OrNorXor32 trial2(OrNorXorOut, A, B, Command); -Bitslice32 superalu(OneBitFinalOut, AddSubSLTSum, carryout, overflow, SLTflag, OrNorXorOut, AndNandOut, subtract, A, B, Command, carryin); +Bitslice32 superalu(OneBitFinalOut, AddSubSLTSum, carryout, overflow, SLTflag, OrNorXorOut, AndNandOut, subtract, ZeroFlag, A, B, Command, carryin); initial begin -$display("Test ALU - Add"); -$display(" A | B |Command|Output | ExpectOut|Cout|OF|subtract|SLTflag"); -A = 4'b1000; B = 4'b0001; Command =3'b000; #1000 -$display("%b | %b | %b | %b | Expect 1001| %b | %b ", A, B, Command, AddSubSLTSum, carryout, overflow); +$display("Test 4 Bit Adder Functionality"); +// there are too many possibilities even for just a four bit adder/subtractor, which means we need to choose our test cases strategically +$display(" A | B |Command| Out|ExpectedOut|Cout|OF"); -$display(" A | B |Command|Output | ExpectOut|Cout|OF|subtract|SLTflag"); -A = 4'b1000; B = 4'b0001; Command =3'b000; #1000 -$display("%b | %b | %b | %b | Expect 1001| %b | %b ", A, B, Command, OneBitFinalOut, carryout, overflow); -/* -A = 4'b1010; B = 4'b0001; Command =3'b000; #1000 -$display("%b | %b | %b | %b | Expect 1011| %b | %b | %b", A, B, Command, AddSubSLTSum, carryout, overflow, subtract); +//Pos + Pos < 7 | 2 + 4 = 6 | 2 = 0010 | 4 = 0100 | 6 = 0110 | NO OVERFLOW +A = 4'b0010; B = 4'b0100; Command =3'b000; #1000 +$display("%b | %b | %b | %b | Expect 0110| %b | %b ", A, B, Command, AddSubSLTSum, carryout, overflow); -A = 4'b1010; B = 4'b0001; Command =3'b000; #1000 -$display("%b | %b | %b | %b | Expect 1011| %b | %b ", A, B, Command, AddSubSLTSum, carryout, overflow); +//Pos + Pos < 7 | 1 + 6 = 7 | 1 = 0001 | 6 = 0110 | 7 = 0111 | NO OVERFLOW +A = 4'b0001; B = 4'b0110; Command =3'b000; #1000 +$display("%b | %b | %b | %b | Expect 0111| %b | %b ", A, B, Command, AddSubSLTSum, carryout, overflow); + +//Pos + Neg > 0 | 5 + -3 = 2 | 5 = 0101 | -3 = 1101 | 2 = 0010 | NO OVERFLOW +A = 4'b0101; B = 4'b1101; Command =3'b000; #1000 +$display("%b | %b | %b | %b | Expect 0010| %b | %b ", A, B, Command, AddSubSLTSum, carryout, overflow); -A = 4'b1010; B = 4'b0111; Command =3'b000; #1000 +//Pos + Neg > 0 | 2 + -1 = 1 | 2 = 0010 | -1 = 1111 | 1 = 0001 | NO OVERFLOW +A = 4'b0010; B = 4'b1111; Command =3'b000; #1000 $display("%b | %b | %b | %b | Expect 0001| %b | %b ", A, B, Command, AddSubSLTSum, carryout, overflow); -A = 4'b1010; B = 4'b0111; Command =3'b001; #1000 -$display("%b | %b | %b | %b | Expect 0011| %b | %b | %b", A, B, Command, AddSubSLTSum, carryout, overflow, subtract); +//Pos + Neg < 0 | -8 + 3 = -5 | -8 = 1000 | 3 = 0011 | -5 = 1011 | NO OVERFLOW +A = 4'b1000; B = 4'b0011; Command =3'b000; #1000 +$display("%b | %b | %b | %b | Expect 1011| %b | %b ", A, B, Command, AddSubSLTSum, carryout, overflow); + +//Pos + Neg < 0 | -4 + 2 = -2 | -4 = 1100 | 2 = 0010 | -2 = 1110 | NO OVERFLOW +A = 4'b1100; B = 4'b0010; Command =3'b000; #1000 +$display("%b | %b | %b | %b | Expect 1110| %b | %b ", A, B, Command, AddSubSLTSum, carryout, overflow); -A = 4'b1010; B = 4'b0111; Command =3'b011; #1000 -$display("%b | %b | %b | %b | Expect 0011| %b | %b | %b | %b", A, B, Command, AddSubSLTSum, carryout, overflow, subtract, SLTflag); +//Pos + Neg = 0 | -5 + 5 = 0 | -5 = 1101 | 5 = 0101 | 0 = 0000 | NO OVERFLOW +A = 4'b1011; B = 4'b0101; Command =3'b000; #1000 +$display("%b | %b | %b | %b | Expect 0110| %b | %b ", A, B, Command, AddSubSLTSum, carryout, overflow); -A = 4'b0111; B = 4'b1010; Command =3'b011; #1000 -$display("%b | %b | %b | %b | Expect 0011| %b | %b | %b | %b", A, B, Command, AddSubSLTSum, carryout, overflow, subtract, SLTflag); +//Pos + Neg = 0 | -7 + 7 = 0 | -7 = 1001 | 7 = 0111 | 0 = 0000 | NO OVERFLOW +A = 4'b0111; B = 4'b1001; Command =3'b000; #1000 +$display("%b | %b | %b | %b | Expect 0000| %b | %b ", A, B, Command, AddSubSLTSum, carryout, overflow); +//Neg + Neg > -8 | -3 + -4 = -7 | -3 = 1101 | -4 = 1100 | -7 = 1001 | NO OVERFLOW +A = 4'b1101; B = 4'b1100; Command =3'b000; #1000 +$display("%b | %b | %b | %b | Expect 1001| %b | %b ", A, B, Command, AddSubSLTSum, carryout, overflow); -A = 4'b0001; B = 4'b0010; Command =3'b011; #1000 -$display("%b | %b | %b | %b | Expect xxxx| %b | %b | %b | %b", A, B, Command, AddSubSLTSum, carryout, overflow, subtract, SLTflag); +//Neg + Neg > -8 | -2 + -6 = -8 | -2 = 1110 | -6 = 1010 | -8 = 1000 | NO OVERFLOW +A = 4'b1110; B = 4'b1010; Command =3'b000; #1000 +$display("%b | %b | %b | %b | Expect 1000| %b | %b ", A, B, Command, AddSubSLTSum, carryout, overflow); +//Pos + Pos > 7 | 5 + 6 = 11 | 5 = 0101 | 6 = 0110 | | OVERFLOW +A = 4'b0101; B = 4'b0110; Command =3'b000; #1000 +$display("%b | %b | %b | %b | Expect XXXX| %b | %b ", A, B, Command, AddSubSLTSum, carryout, overflow); -$display("AND/NAND"); -$display("A | B | Command | Output | ExpectedOut"); -A = 4'b0001; B = 4'b0010; Command =3'b100; #1000 -$display("%b | %b | %b | %b | Expect 0000", A, B, Command, AndNandOut); +//Pos + Pos > 7 | 2 + 7 = 9 | 2 = 0010 | 7 = 0111 | | OVERFLOW +A = 4'b0010; B = 4'b0111; Command =3'b000; #1000 +$display("%b | %b | %b | %b | Expect XXXX| %b | %b ", A, B, Command, AddSubSLTSum, carryout, overflow); -$display("A | B | Command | Output | ExpectedOut"); -A = 4'b0001; B = 4'b0010; Command =3'b101; #1000 -$display("%b | %b | %b | %b | Expect 1111", A, B, Command, AndNandOut); +//Pos + Pos > 7 | 7 + 7 = 14 | 7 = 0111 | 7 = 0111 | | OVERFLOW +A = 4'b0111; B = 4'b0111; Command =3'b000; #1000 +$display("%b | %b | %b | %b | Expect XXXX| %b | %b ", A, B, Command, AddSubSLTSum, carryout, overflow); -$display("OR/NOR/XOR"); -$display("A | B | Command | Output | ExpectedOutXOR"); -A = 4'b0001; B = 4'b0010; Command =3'b010; #1000 -$display("%b | %b | %b | %b | Expect 0011", A, B, Command, OrNorXorOut); +//Neg + Neg < -8 | -8 + -1 = -9 | -8 = 1000 | -1 = 1111 | | OVERFLOW +A = 4'b1000; B = 4'b1111; Command =3'b000; #1000 +$display("%b | %b | %b | %b | Expect XXXX| %b | %b ", A, B, Command, AddSubSLTSum, carryout, overflow); -$display("A | B | Command | Output | ExpectedOutNOR"); -A = 4'b0001; B = 4'b0010; Command =3'b110; #1000 -$display("%b | %b | %b | %b | Expect 1100", A, B, Command, OrNorXorOut); +//Neg + Neg < -8 | -8 + -3 = -11 | -8 = 1000 | -3 = 1101 | | OVERFLOW +A = 4'b1000; B = 4'b1101; Command =3'b000; #1000 +$display("%b | %b | %b | %b | Expect XXXX| %b | %b ", A, B, Command, AddSubSLTSum, carryout, overflow); -$display("A | B | Command | Output | ExpectedOutOR"); -A = 4'b0001; B = 4'b0010; Command =3'b111; #1000 -$display("%b | %b | %b | %b | Expect 0011", A, B, Command, OrNorXorOut); -*/ +//Neg + Neg < -8 | -5 + -4 = -9 | -5 = 1011 | -4 = 1100 | | OVERFLOW +A = 4'b1011; B = 4'b1100; Command =3'b000; #1000 +$display("%b | %b | %b | %b | Expect XXXX| %b | %b ", A, B, Command, AddSubSLTSum, carryout, overflow); + +$display("Test 4 Bit SLT Functionality"); +// there are too many possibilities even for just a four bit adder/subtractor, which means we need to choose our test cases strategically. We chose to not specifically test the subtractor, since it is part of the SLT, and if the SLT is working, then the subtractor is, too. +$display(" A | B |Command| Out|ExpectedOut|Cout|OF |SLTflag"); + +// A < B, A > 0 | B > 0 | No Overflow | A = 2 = 0010 | B = 4 = 0100 +A = 4'b0010; B = 4'b0100; Command =3'b011; #1000 +$display("%b | %b | %b | %b | Expect 1110| %b | %b | %b", A, B, Command, AddSubSLTSum, carryout, overflow, SLTflag); + +// A > B, A > 0 | B > 0 | No Overflow | A = 4 = 0100 | B = 2 = 0010 +A = 4'b0100; B = 4'b0010; Command =3'b011; #1000 +$display("%b | %b | %b | %b | Expect 0010| %b | %b | %b", A, B, Command, AddSubSLTSum, carryout, overflow, SLTflag); + +// A < B, A < 0 | B > 0 | No Overflow | A = -2 = 1110 | B = 4 = 0100 +A = 4'b1110; B = 4'b0100; Command =3'b011; #1000 +$display("%b | %b | %b | %b | Expect 1010| %b | %b | %b", A, B, Command, AddSubSLTSum, carryout, overflow, SLTflag); + +// A > B, A > 0 | B < 0 | No Overflow | A = 4 = 0100| B = -2 = 1110 +A = 4'b0100; B = 4'b1110; Command =3'b011; #1000 +$display("%b | %b | %b | %b | Expect 0110| %b | %b | %b", A, B, Command, AddSubSLTSum, carryout, overflow, SLTflag); + +// A < B, A < 0 | B < 0 | No Overflow | A = -2 = 1110 | B = -1 = 1111 +A = 4'b1110; B = 4'b1111; Command =3'b011; #1000 +$display("%b | %b | %b | %b | Expect 1111| %b | %b | %b", A, B, Command, AddSubSLTSum, carryout, overflow, SLTflag); + +// A > B, A < 0 | B < 0 | No Overflow | A = -1 = 1111 | B = -2 = 1110 +A = 4'b1111; B = 4'b1110; Command =3'b011; #1000 +$display("%b | %b | %b | %b | Expect 0001| %b | %b | %b", A, B, Command, AddSubSLTSum, carryout, overflow, SLTflag); + +// A = B, A < 0 | B < 0 | No Overflow | A = -3 = 1101 | B = -3 = 1101 +A = 4'b1101; B = 4'b1101; Command =3'b011; #1000 +$display("%b | %b | %b | %b | Expect 0000| %b | %b | %b", A, B, Command, AddSubSLTSum, carryout, overflow, SLTflag); + +// A = B, A > 0 | B > 0 | No Overflow | A = 5 = 0101 | B = 5 = 0101 +A = 4'b0101; B = 4'b0101; Command =3'b011; #1000 +$display("%b | %b | %b | %b | Expect 0000| %b | %b | %b", A, B, Command, AddSubSLTSum, carryout, overflow, SLTflag); + +// A < B, A < 0 | B > 0 | Overflow | A = -7 = 1001 | B = 5 = 0101 +A = 4'b1001; B = 4'b0101; Command =3'b011; #1000 +$display("%b | %b | %b | %b | Expect XXXX| %b | %b | %b", A, B, Command, AddSubSLTSum, carryout, overflow, SLTflag); + +$display("Test 4 Bit AND/NAND Functionality"); +// there are too many possibilities even for just a four bit AND/NAND, which means we need to choose our test cases strategically. +$display(" A | B |Command| Out |ExpectedOut-AND"); + +// A = B | A = 1111 | AND = 1111 + A=4'b1111;B=4'b1111;Command=3'b100; #1000 + $display("%b | %b | %b | %b | 1111", A, B, Command, AndNandOut); + +// A = 1111 | B = 1010 | AND = 1010 + A=4'b1111;B=4'b1010;Command=3'b100; #1000 + $display("%b | %b | %b | %b | 1010", A, B, Command, AndNandOut); + +// A = 1111 | B = 0101 | AND = 0101 + A=4'b1111;B=4'b0101;Command=3'b100; #1000 + $display("%b | %b | %b | %b | 0101", A, B, Command, AndNandOut); + +// A = 1111 | B = 0000 | AND = 0000 + A=4'b1111;B=4'b0000;Command=3'b100; #1000 + $display("%b | %b | %b | %b | 0000", A, B, Command, AndNandOut); + + +$display(" A | B |Command| Out |ExpectedOut-NAND"); + +// A = B | A = 1111 | NAND = 0000 + A=4'b1111;B=4'b1111;Command=3'b101; #1000 + $display("%b | %b | %b | %b | 0000", A, B, Command, AndNandOut); + +// A = 1111 | B = 1010 | NAND = 0101 + A=4'b1111;B=4'b1010;Command=3'b101; #1000 + $display("%b | %b | %b | %b | 0101", A, B, Command, AndNandOut); + +// A = 1111 | B = 0101 | NAND = 1010 + A=4'b1111;B=4'b0101;Command=3'b101; #1000 + $display("%b | %b | %b | %b | 1010", A, B, Command, AndNandOut); + +// A = 1111 | B = 0000 | NAND = 1111 + A=4'b1111;B=4'b0000;Command=3'b101; #1000 + $display("%b | %b | %b | %b | 1111", A, B, Command, AndNandOut); + +$display("Test 4 Bit OR/NOR/XOR Functionality"); +// there are too many possibilities even for just a four bit AND/NAND, which means we need to choose our test cases strategically. +$display(" A | B |Command | Out |ExpectedOut-OR"); + +// A = 1010 | B = 0101 | OR = 1111 + A=4'b1010; B=4'b0101; Command=3'b111; #1000 + $display("%b | %b | %b | %b | 1111", A, B, Command, OrNorXorOut); + +// A = 1111 | B = 0101 | OR = 1111 + A=4'b1111; B=4'b0101; Command=3'b111; #1000 + $display("%b | %b | %b | %b | 1111", A, B, Command, OrNorXorOut); + +// A = 1011 | B = 0000 | OR = 1011 + A=4'b1011; B=4'b0000; Command=3'b111; #1000 + $display("%b | %b | %b | %b | 1011", A, B, Command, OrNorXorOut); + +$display(" A | B |Command | Out |ExpectedOut-NOR"); + +// A = 1010 | B = 0101 | NOR = 0000 + A=4'b1010; B=4'b0101; Command=3'b110; #1000 + $display("%b | %b | %b | %b | 0000", A, B, Command, OrNorXorOut); + +// A = 1111 | B = 0101 | NOR = 0000 + A=4'b1111; B=4'b0101; Command=3'b110; #1000 + $display("%b | %b | %b | %b | 0000", A, B, Command, OrNorXorOut); + +// A = 1011 | B = 0000 | NOR = 0100 + A=4'b1011; B=4'b0000; Command=3'b110; #1000 + $display("%b | %b | %b | %b | 0100", A, B, Command, OrNorXorOut); + +$display(" A | B |Command | Out |ExpectedOut-XOR"); + +// A = 1010 | B = 0101 | XOR = 1111 + A=4'b1010; B=4'b0101; Command=3'b010; #1000 + $display("%b | %b | %b | %b | 1111", A, B, Command, OrNorXorOut); + +// A = 1111 | B = 0101 | XOR = 1010 + A=4'b1111; B=4'b0101; Command=3'b010; #1000 + $display("%b | %b | %b | %b | 1010", A, B, Command, OrNorXorOut); + +// A = 1011 | B = 0000 | XOR = 1011 + A=4'b1011; B=4'b0000; Command=3'b010; #1000 + $display("%b | %b | %b | %b | 1011", A, B, Command, OrNorXorOut); + +$display("Test 4 Bit ALU Functionality"); +// there are too many possibilities even for just a four bit AND/NAND, which means we need to choose our test cases strategically. +$display(" A | B |Command | Out |ExpectedOut | COut | OF |SLT|Zero"); + +// Test AND +// A = B | A = 1111 | AND = 1111 + A=4'b1111;B=4'b1111;Command=3'b100; #1000 + $display("%b | %b | %b - AND | %b | 1111 | %b | %b | %b | %b", A, B, Command, OneBitFinalOut, carryout, overflow, SLTflag, ZeroFlag); + +// Test NAND +// A = 1111 | B = 0000 | NAND = 1111 + A=4'b1111;B=4'b0000;Command=3'b101; #1000 + $display("%b | %b | %b - NAND | %b | 1111 | %b | %b | %b | %b", A, B, Command, OneBitFinalOut, carryout, overflow, SLTflag, ZeroFlag); + +// Test OR +// A = 1111 | B = 0101 | OR = 1111 + A=4'b1111; B=4'b0101; Command=3'b111; #1000 + $display("%b | %b | %b - OR | %b | 1111 | %b | %b | %b | %b", A, B, Command, OneBitFinalOut, carryout, overflow, SLTflag, ZeroFlag); + +// Test NOR +// A = 1011 | B = 0000 | NOR = 0100 + A=4'b1011; B=4'b0000; Command=3'b110; #1000 + $display("%b | %b | %b - NOR | %b | 0100 | %b | %b | %b | %b", A, B, Command, OneBitFinalOut, carryout, overflow, SLTflag, ZeroFlag); + +// Test XOR +// A = 1011 | B = 0000 | XOR = 1011 + A=4'b1011; B=4'b0000; Command=3'b010; #1000 + $display("%b | %b | %b - XOR | %b | 1011 | %b | %b | %b | %b", A, B, Command, OneBitFinalOut, carryout, overflow, SLTflag, ZeroFlag); + +// Test ADD +//Pos + Pos < 7 | 2 + 4 = 6 | 2 = 0010 | 4 = 0100 | 6 = 0110 | NO OVERFLOW +A = 4'b0010; B = 4'b0100; Command =3'b000; #1000 + $display("%b | %b | %b - ADD | %b | 0110 | %b | %b | %b | %b", A, B, Command, OneBitFinalOut, carryout, overflow, SLTflag, ZeroFlag); + +//Neg + Neg < -8 | -5 + -4 = -9 | -5 = 1011 | -4 = 1100 | | OVERFLOW +A = 4'b1011; B = 4'b1100; Command =3'b000; #1000 + $display("%b | %b | %b - ADD | %b | XXXX | %b | %b | %b | %b", A, B, Command, OneBitFinalOut, carryout, overflow, SLTflag, ZeroFlag); + +// Test SUB +// A < B, A > 0 | B > 0 | No Overflow | A = 2 = 0010 | B = 4 = 0100 +A = 4'b0010; B = 4'b0100; Command =3'b001; #1000 + $display("%b | %b | %b - SUB | %b | 1110 | %b | %b | %b | %b", A, B, Command, OneBitFinalOut, carryout, overflow, SLTflag, ZeroFlag); + +// A < B, A < 0 | B > 0 | Overflow | A = -7 = 1001 | B = 3 = 0011 +A = 4'b1001; B = 4'b0011; Command =3'b001; #1000 + $display("%b | %b | %b - SUB | %b | XXXX | %b | %b | %b | %b", A, B, Command, OneBitFinalOut, carryout, overflow, SLTflag, ZeroFlag); + +// Test SLT + +// A > B, A > 0 | B > 0 | No Overflow | A = 4 = 0100 | B = 2 = 0010 +A = 4'b0100; B = 4'b0010; Command =3'b011; #1000 + $display("%b | %b | %b - SLT | %b | 0010 | %b | %b | %b | %b", A, B, Command, OneBitFinalOut, carryout, overflow, SLTflag, ZeroFlag); +// A < B, A < 0 | B > 0 | Overflow | A = -7 = 1001 | B = 5 = 0101 +A = 4'b1001; B = 4'b0101; Command =3'b011; #1000 + $display("%b | %b | %b - SLT | %b | XXXX | %b | %b | %b | %b", A, B, Command, OneBitFinalOut, carryout, overflow, SLTflag, ZeroFlag); end endmodule + From 48a73b3aa4159ba6b407c7828a25655a7dc4381b Mon Sep 17 00:00:00 2001 From: LoganSweet Date: Mon, 9 Oct 2017 21:52:38 -0400 Subject: [PATCH 12/28] git debacle #2 Signed-off-by: LoganSweet --- alu2.v => alu.v | 0 testing.t.v | 2 +- 2 files changed, 1 insertion(+), 1 deletion(-) rename alu2.v => alu.v (100%) diff --git a/alu2.v b/alu.v similarity index 100% rename from alu2.v rename to alu.v diff --git a/testing.t.v b/testing.t.v index c1f03e1..0e54631 100644 --- a/testing.t.v +++ b/testing.t.v @@ -1,6 +1,6 @@ // Intermediate testbench `timescale 1 ns / 1 ps -`include "alu2.v" +`include "alu.v" /* module testBasicFunctions(); From 52f6c1b29c3d716169ceda5471193191c63b0f7c Mon Sep 17 00:00:00 2001 From: LoganSweet Date: Mon, 9 Oct 2017 22:27:29 -0400 Subject: [PATCH 13/28] added alu.v comments and formatting --- OriginalTesting.t.v | 1 - alu.v | 35 ++++++++++++++++------------------- testing.t.v | 8 -------- 3 files changed, 16 insertions(+), 28 deletions(-) diff --git a/OriginalTesting.t.v b/OriginalTesting.t.v index a48d838..d4f68d2 100644 --- a/OriginalTesting.t.v +++ b/OriginalTesting.t.v @@ -125,5 +125,4 @@ initial begin end - endmodule diff --git a/alu.v b/alu.v index 31a7747..838022a 100644 --- a/alu.v +++ b/alu.v @@ -41,30 +41,28 @@ module FourInMux // this module is a four input mux that takes in four inputs (i `NAND n1(out1, S0, nS1, in1); `NAND n2(out2, nS0, S1, in2); `NAND n3(out3, S0, S1, in3); - - `NAND addthem(out, out0, out1, out2, out3); + `NAND finalmuxout(out, out0, out1, out2, out3); endmodule -module AndNand // Uses Command[0] to determine whether and or nand is chosen -( +module AndNand // Uses Command[0] to determine whether and or nand is chosen +( // and is b100 and nang is b101, so we check the 0th digit output AndNandOut, input A, B, input[2:0] Command ); - wire AnandB; wire AandB; `NAND n0(AnandB, A, B); `NOT Ainv(AandB, AnandB); - TwoInMux potato(AndNandOut, Command[0], AandB, AnandB); // order to follow out,S,in0, in1 + TwoInMux potato(AndNandOut, Command[0], AandB, AnandB); // order to follow: out,S,in0, in1 endmodule module OrNorXor ( output OrNorXorOut, // uses both Command[0] and Command[2] to determine whether Or, Nor, or Xor is used -input A, B, +input A, B, // or is b111 - nor is b110 - xor is b010 input[2:0] Command ); wire AnorB; @@ -84,7 +82,6 @@ input[2:0] Command TwoInMux mux1(OrNorXorOut, Command[0], XorNor, AorB); endmodule - // this module calculates addition, subtraction, and SLT based on which command is selected. SLT happens when A Date: Mon, 9 Oct 2017 22:31:13 -0400 Subject: [PATCH 14/28] added top level module requirement scaffolding and note --- alu.v | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/alu.v b/alu.v index 838022a..6d4a7ed 100644 --- a/alu.v +++ b/alu.v @@ -4,6 +4,21 @@ `define OR or #20 // nor with not is 20 `define NOR nor #10 // base is 10 `define XOR xor #40 // and with or is 40 +/* +- - - - - - - - - - - - - - - - - - - - - - - - - - - According to the assignment, we need to have a top-level module with these definitions!!! - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - +module ALU +( +output[31:0] result, +output carryout, +output zero, +output overflow, +input[31:0] operandA, +input[31:0] operandB, +input[2:0] command +); + // Your code here +endmodule +*/ module TwoInMux // this module is a two input mux that takes in two inputs (in0 and in1) and uses switch S to pick the value for outfinal ( From 660ad202ad18ae97d9bd8379d833627872cff544 Mon Sep 17 00:00:00 2001 From: mjakus Date: Tue, 10 Oct 2017 08:20:44 -0400 Subject: [PATCH 15/28] Got zeros working --- alu.v | 19 +- test | 2297 +++++++++++++++++++++++++++++++++++++++++++++++++++ testing.t.v | 32 +- 3 files changed, 2329 insertions(+), 19 deletions(-) create mode 100755 test diff --git a/alu.v b/alu.v index 31a7747..6995192 100644 --- a/alu.v +++ b/alu.v @@ -263,7 +263,8 @@ output SLTflag, output [size-1:0] OrNorXorOut, output [size-1:0] AndNandOut, output [size-1:0] subtract, -output ZeroFlag, +output [size-1:0] ZeroFlag, +output AllZeros, input [size-1:0] A, input [size-1:0] B, input[2:0] Command, @@ -273,6 +274,7 @@ input [size-1:0]carryin // don't think this does anything but don't want to brea wire [size-1:0] Cmd0Start; wire [size-1:0] Cmd1Start; wire [size-1:0] CarryoutWire; + wire yeszero; AddSubSLT32 trial(AddSubSLTSum, carryout, overflow, SLTflag, subtract, A, B, Command, carryin); AndNand32 trial1(AndNandOut, A, B, Command); @@ -280,7 +282,8 @@ input [size-1:0]carryin // don't think this does anything but don't want to brea FourInMux ZeroMux0case(Cmd0Start[0], Command[0], Command[1], AddSubSLTSum[0], AddSubSLTSum[0], OrNorXorOut[0], AddSubSLTSum[0]); FourInMux OneMux0case(Cmd1Start[0], Command[0], Command[1], AndNandOut[0], AndNandOut[0], OrNorXorOut[0], OrNorXorOut[0]); - TwoInMux TwoMux0case(OneBitFinalOut[0], Command[2], Cmd0Start[0], Cmd1Start[0]); + TwoInMux TwoMux0case(OneBitFinalOut[0], Command[2], Cmd0Start[0], Cmd1Start[0]); + `AND setZerothZero(ZeroFlag[0], OneBitFinalOut[0], OneBitFinalOut[0]); genvar i; generate @@ -288,12 +291,16 @@ input [size-1:0]carryin // don't think this does anything but don't want to brea begin: muxbits FourInMux ZeroMux(Cmd0Start[i], Command[0], Command[1], AddSubSLTSum[i], AddSubSLTSum[i], OrNorXorOut[i], AddSubSLTSum[i]); FourInMux OneMux(Cmd1Start[i], Command[0], Command[1], AndNandOut[i], AndNandOut[i], OrNorXorOut[i], OrNorXorOut[i]); - TwoInMux TwoMux(OneBitFinalOut[i], Command[2], Cmd0Start[i], Cmd1Start[i]); + TwoInMux TwoMux(OneBitFinalOut[i], Command[2], Cmd0Start[i], Cmd1Start[i]); + + `OR zeroflagtest(ZeroFlag[i], ZeroFlag[i-1], OneBitFinalOut[i]); end endgenerate - - // AndNand32 zeroflagtest(ZeroInt0, OneBitFinalOut, OneBitFinalOut, 3'b101); - //`NAND zeroflagtest(ZeroFlag, OneBitFinalOut, OneBitFinalOut); + + `NOT invzeroflag(yeszero, ZeroFlag[size-1]); + `AND setzeros(AllZeros, yeszero, yeszero); + + endmodule diff --git a/test b/test new file mode 100755 index 0000000..24c16d3 --- /dev/null +++ b/test @@ -0,0 +1,2297 @@ +#! /usr/bin/vvp +:ivl_version "0.9.7 " "(v0_9_7)"; +:vpi_time_precision - 12; +:vpi_module "system"; +:vpi_module "v2005_math"; +:vpi_module "va_math"; +S_0x1da9580 .scope module, "test32Adder" "test32Adder" 2 122; + .timescale -9 -12; +P_0x1d46268 .param/l "size" 2 123, +C4<0100>; +v0x1e49000_0 .var "A", 3 0; +RS_0x7f060963abe8/0/0 .resolv tri, L_0x1e4a7f0, L_0x1e4bee0, L_0x1e4d420, L_0x1e4ea20; +RS_0x7f060963abe8/0/4 .resolv tri, L_0x1e60860, L_0x1e61c80, L_0x1e63080, L_0x1e645a0; +RS_0x7f060963abe8 .resolv tri, RS_0x7f060963abe8/0/0, RS_0x7f060963abe8/0/4, C4, C4; +v0x1e49080_0 .net8 "AddSubSLTSum", 3 0, RS_0x7f060963abe8; 8 drivers +v0x1e49100_0 .net "AllZeros", 0 0, L_0x1e6fdf0; 1 drivers +RS_0x7f0609639e38/0/0 .resolv tri, L_0x1e509d0, L_0x1e51480, L_0x1e51ef0, L_0x1e52950; +RS_0x7f0609639e38/0/4 .resolv tri, L_0x1e663d0, L_0x1e66e40, L_0x1e678b0, L_0x1e68410; +RS_0x7f0609639e38 .resolv tri, RS_0x7f0609639e38/0/0, RS_0x7f0609639e38/0/4, C4, C4; +v0x1e49180_0 .net8 "AndNandOut", 3 0, RS_0x7f0609639e38; 8 drivers +v0x1e49200_0 .var "B", 3 0; +v0x1e49280_0 .var "Command", 2 0; +RS_0x7f060963b068 .resolv tri, L_0x1e59a40, L_0x1e5c690, L_0x1e5f2c0, L_0x1e6f260; +v0x1e49300_0 .net8 "OneBitFinalOut", 3 0, RS_0x7f060963b068; 4 drivers +RS_0x7f0609639748/0/0 .resolv tri, L_0x1e53ca0, L_0x1e55200, L_0x1e56500, L_0x1e577b0; +RS_0x7f0609639748/0/4 .resolv tri, L_0x1e69760, L_0x1e6aa60, L_0x1e6bd60, L_0x1e6d050; +RS_0x7f0609639748 .resolv tri, RS_0x7f0609639748/0/0, RS_0x7f0609639748/0/4, C4, C4; +v0x1e49380_0 .net8 "OrNorXorOut", 3 0, RS_0x7f0609639748; 8 drivers +RS_0x7f060963aca8 .resolv tri, L_0x1e50050, L_0x1e65a70, C4, C4; +v0x1e49400_0 .net8 "SLTflag", 0 0, RS_0x7f060963aca8; 2 drivers +RS_0x7f060963b098 .resolv tri, L_0x1e59ef0, L_0x1e5cb60, L_0x1e5f400, L_0x1e6f520; +v0x1e49480_0 .net8 "ZeroFlag", 3 0, RS_0x7f060963b098; 4 drivers +v0x1e49500_0 .var "carryin", 3 0; +RS_0x7f060963aee8 .resolv tri, L_0x1e4aad0, L_0x1e64920, C4, C4; +v0x1e49580_0 .net8 "carryout", 0 0, RS_0x7f060963aee8; 2 drivers +RS_0x7f060963af78 .resolv tri, L_0x1e4f320, L_0x1e64d90, C4, C4; +v0x1e49600_0 .net8 "overflow", 0 0, RS_0x7f060963af78; 2 drivers +RS_0x7f060963afa8/0/0 .resolv tri, L_0x1e4aa30, L_0x1e4c110, L_0x1e4d680, L_0x1e4da70; +RS_0x7f060963afa8/0/4 .resolv tri, L_0x1e60a40, L_0x1e61eb0, L_0x1e632e0, L_0x1e636d0; +RS_0x7f060963afa8 .resolv tri, RS_0x7f060963afa8/0/0, RS_0x7f060963afa8/0/4, C4, C4; +v0x1e49680_0 .net8 "subtract", 3 0, RS_0x7f060963afa8; 8 drivers +S_0x1e43820 .scope module, "trial" "AddSubSLT32" 2 141, 3 205, S_0x1da9580; + .timescale -9 -12; +P_0x1e43918 .param/l "size" 3 228, +C4<0100>; +L_0x1e4aad0/d .functor OR 1, L_0x1e4f170, C4<0>, C4<0>, C4<0>; +L_0x1e4aad0 .delay (20000,20000,20000) L_0x1e4aad0/d; +L_0x1e4f320/d .functor XOR 1, RS_0x7f060963aee8, L_0x1e4f450, C4<0>, C4<0>; +L_0x1e4f320 .delay (40000,40000,40000) L_0x1e4f320/d; +L_0x1e4f0a0/d .functor AND 1, L_0x1e4f620, L_0x1e4f6c0, C4<1>, C4<1>; +L_0x1e4f0a0 .delay (20000,20000,20000) L_0x1e4f0a0/d; +L_0x1e4f4f0/d .functor NOT 1, RS_0x7f060963af78, C4<0>, C4<0>, C4<0>; +L_0x1e4f4f0 .delay (10000,10000,10000) L_0x1e4f4f0/d; +L_0x1e4f8f0/d .functor NOT 1, L_0x1e4f950, C4<0>, C4<0>, C4<0>; +L_0x1e4f8f0 .delay (10000,10000,10000) L_0x1e4f8f0/d; +L_0x1e4a890/d .functor AND 1, L_0x1e4f4f0, L_0x1e4fc20, C4<1>, C4<1>; +L_0x1e4a890 .delay (20000,20000,20000) L_0x1e4a890/d; +L_0x1e4f7b0/d .functor AND 1, RS_0x7f060963af78, L_0x1e4f8f0, C4<1>, C4<1>; +L_0x1e4f7b0 .delay (20000,20000,20000) L_0x1e4f7b0/d; +L_0x1e4fe10/d .functor AND 1, L_0x1e4a890, L_0x1e4f0a0, C4<1>, C4<1>; +L_0x1e4fe10 .delay (20000,20000,20000) L_0x1e4fe10/d; +L_0x1e4ff50/d .functor AND 1, L_0x1e4f7b0, L_0x1e4f0a0, C4<1>, C4<1>; +L_0x1e4ff50 .delay (20000,20000,20000) L_0x1e4ff50/d; +L_0x1e50050/d .functor OR 1, L_0x1e4fe10, L_0x1e4ff50, C4<0>, C4<0>; +L_0x1e50050 .delay (20000,20000,20000) L_0x1e50050/d; +v0x1e47f20_0 .net "A", 3 0, v0x1e49000_0; 1 drivers +v0x1e47fc0_0 .alias "AddSubSLTSum", 3 0, v0x1e49080_0; +v0x1e48040_0 .net "B", 3 0, v0x1e49200_0; 1 drivers +RS_0x7f060963d348 .resolv tri, L_0x1e4a940, L_0x1e4bfd0, L_0x1e4d510, L_0x1e4eb10; +v0x1e480c0_0 .net8 "CarryoutWire", 3 0, RS_0x7f060963d348; 4 drivers +v0x1e48140_0 .net "Command", 2 0, v0x1e49280_0; 1 drivers +v0x1e481c0_0 .net "Res0OF1", 0 0, L_0x1e4f7b0; 1 drivers +v0x1e48260_0 .net "Res1OF0", 0 0, L_0x1e4a890; 1 drivers +v0x1e48300_0 .alias "SLTflag", 0 0, v0x1e49400_0; +v0x1e48420_0 .net "SLTflag0", 0 0, L_0x1e4fe10; 1 drivers +v0x1e484c0_0 .net "SLTflag1", 0 0, L_0x1e4ff50; 1 drivers +v0x1e48560_0 .net "SLTon", 0 0, L_0x1e4f0a0; 1 drivers +v0x1e48600_0 .net *"_s40", 0 0, L_0x1e4f170; 1 drivers +v0x1e486a0_0 .net/s *"_s41", 0 0, C4<0>; 1 drivers +v0x1e48740_0 .net *"_s44", 0 0, L_0x1e4f450; 1 drivers +v0x1e48860_0 .net *"_s46", 0 0, L_0x1e4f620; 1 drivers +v0x1e48900_0 .net *"_s48", 0 0, L_0x1e4f6c0; 1 drivers +v0x1e487c0_0 .net *"_s50", 0 0, L_0x1e4f950; 1 drivers +v0x1e48a50_0 .net *"_s52", 0 0, L_0x1e4fc20; 1 drivers +v0x1e48b70_0 .net "carryin", 3 0, v0x1e49500_0; 1 drivers +v0x1e48bf0_0 .alias "carryout", 0 0, v0x1e49580_0; +v0x1e48ad0_0 .net "nAddSubSLTSum", 0 0, L_0x1e4f8f0; 1 drivers +v0x1e48d20_0 .net "nOF", 0 0, L_0x1e4f4f0; 1 drivers +v0x1e48c70_0 .alias "overflow", 0 0, v0x1e49600_0; +v0x1e48eb0_0 .alias "subtract", 3 0, v0x1e49680_0; +L_0x1e4a7f0 .part/pv L_0x1e4a360, 1, 1, 4; +L_0x1e4a940 .part/pv L_0x1e4a6b0, 1, 1, 4; +L_0x1e4aa30 .part/pv L_0x1e3c880, 1, 1, 4; +L_0x1e4ab60 .part v0x1e49000_0, 1, 1; +L_0x1e4ad10 .part v0x1e49200_0, 1, 1; +L_0x1e4aec0 .part RS_0x7f060963d348, 0, 1; +L_0x1e4bee0 .part/pv L_0x1e4ba10, 2, 1, 4; +L_0x1e4bfd0 .part/pv L_0x1e4bd80, 2, 1, 4; +L_0x1e4c110 .part/pv L_0x1e4b740, 2, 1, 4; +L_0x1e4c200 .part v0x1e49000_0, 2, 1; +L_0x1e4c300 .part v0x1e49200_0, 2, 1; +L_0x1e4c430 .part RS_0x7f060963d348, 1, 1; +L_0x1e4d420 .part/pv L_0x1e4cf70, 3, 1, 4; +L_0x1e4d510 .part/pv L_0x1e4d2c0, 3, 1, 4; +L_0x1e4d680 .part/pv L_0x1e4cca0, 3, 1, 4; +L_0x1e4d770 .part v0x1e49000_0, 3, 1; +L_0x1e4d8a0 .part v0x1e49200_0, 3, 1; +L_0x1e4d9d0 .part RS_0x7f060963d348, 2, 1; +L_0x1e4ea20 .part/pv L_0x1e4e570, 0, 1, 4; +L_0x1e4eb10 .part/pv L_0x1e4e8c0, 0, 1, 4; +L_0x1e4da70 .part/pv L_0x1e4e2a0, 0, 1, 4; +L_0x1e4ed00 .part v0x1e49000_0, 0, 1; +L_0x1e4ec00 .part v0x1e49200_0, 0, 1; +L_0x1e4eef0 .part RS_0x7f060963afa8, 0, 1; +L_0x1e4f170 .part RS_0x7f060963d348, 3, 1; +L_0x1e4f450 .part RS_0x7f060963d348, 2, 1; +L_0x1e4f620 .part v0x1e49280_0, 1, 1; +L_0x1e4f6c0 .part RS_0x7f060963afa8, 0, 1; +L_0x1e4f950 .part RS_0x7f060963abe8, 3, 1; +L_0x1e4fc20 .part RS_0x7f060963abe8, 3, 1; +S_0x1e46f10 .scope module, "attempt2" "MiddleAddSubSLT" 3 225, 3 89, S_0x1e43820; + .timescale -9 -12; +L_0x1e4d810/d .functor NOT 1, L_0x1e4ec00, C4<0>, C4<0>, C4<0>; +L_0x1e4d810 .delay (10000,10000,10000) L_0x1e4d810/d; +L_0x1e4e140/d .functor NOT 1, L_0x1e4e200, C4<0>, C4<0>, C4<0>; +L_0x1e4e140 .delay (10000,10000,10000) L_0x1e4e140/d; +L_0x1e4e2a0/d .functor AND 1, L_0x1e4e3e0, L_0x1e4e140, C4<1>, C4<1>; +L_0x1e4e2a0 .delay (20000,20000,20000) L_0x1e4e2a0/d; +L_0x1e4e480/d .functor XOR 1, L_0x1e4ed00, L_0x1e4ded0, C4<0>, C4<0>; +L_0x1e4e480 .delay (40000,40000,40000) L_0x1e4e480/d; +L_0x1e4e570/d .functor XOR 1, L_0x1e4e480, L_0x1e4eef0, C4<0>, C4<0>; +L_0x1e4e570 .delay (40000,40000,40000) L_0x1e4e570/d; +L_0x1e4e660/d .functor AND 1, L_0x1e4ed00, L_0x1e4ded0, C4<1>, C4<1>; +L_0x1e4e660 .delay (20000,20000,20000) L_0x1e4e660/d; +L_0x1e4e7d0/d .functor AND 1, L_0x1e4e480, L_0x1e4eef0, C4<1>, C4<1>; +L_0x1e4e7d0 .delay (20000,20000,20000) L_0x1e4e7d0/d; +L_0x1e4e8c0/d .functor OR 1, L_0x1e4e660, L_0x1e4e7d0, C4<0>, C4<0>; +L_0x1e4e8c0 .delay (20000,20000,20000) L_0x1e4e8c0/d; +v0x1e47580_0 .net "A", 0 0, L_0x1e4ed00; 1 drivers +v0x1e47640_0 .net "AandB", 0 0, L_0x1e4e660; 1 drivers +v0x1e476e0_0 .net "AddSubSLTSum", 0 0, L_0x1e4e570; 1 drivers +v0x1e47780_0 .net "AxorB", 0 0, L_0x1e4e480; 1 drivers +v0x1e47800_0 .net "B", 0 0, L_0x1e4ec00; 1 drivers +v0x1e478b0_0 .net "BornB", 0 0, L_0x1e4ded0; 1 drivers +v0x1e47970_0 .net "CINandAxorB", 0 0, L_0x1e4e7d0; 1 drivers +v0x1e479f0_0 .alias "Command", 2 0, v0x1e48140_0; +v0x1e47a70_0 .net *"_s3", 0 0, L_0x1e4e200; 1 drivers +v0x1e47af0_0 .net *"_s5", 0 0, L_0x1e4e3e0; 1 drivers +v0x1e47b90_0 .net "carryin", 0 0, L_0x1e4eef0; 1 drivers +v0x1e47c30_0 .net "carryout", 0 0, L_0x1e4e8c0; 1 drivers +v0x1e47cd0_0 .net "nB", 0 0, L_0x1e4d810; 1 drivers +v0x1e47d80_0 .net "nCmd2", 0 0, L_0x1e4e140; 1 drivers +v0x1e47e80_0 .net "subtract", 0 0, L_0x1e4e2a0; 1 drivers +L_0x1e4e0a0 .part v0x1e49280_0, 0, 1; +L_0x1e4e200 .part v0x1e49280_0, 2, 1; +L_0x1e4e3e0 .part v0x1e49280_0, 0, 1; +S_0x1e47000 .scope module, "mux0" "TwoInMux" 3 105, 3 8, S_0x1e46f10; + .timescale -9 -12; +L_0x1e4dbf0/d .functor NOT 1, L_0x1e4e0a0, C4<0>, C4<0>, C4<0>; +L_0x1e4dbf0 .delay (10000,10000,10000) L_0x1e4dbf0/d; +L_0x1e4dcb0/d .functor AND 1, L_0x1e4ec00, L_0x1e4dbf0, C4<1>, C4<1>; +L_0x1e4dcb0 .delay (20000,20000,20000) L_0x1e4dcb0/d; +L_0x1e4ddc0/d .functor AND 1, L_0x1e4d810, L_0x1e4e0a0, C4<1>, C4<1>; +L_0x1e4ddc0 .delay (20000,20000,20000) L_0x1e4ddc0/d; +L_0x1e4ded0/d .functor OR 1, L_0x1e4dcb0, L_0x1e4ddc0, C4<0>, C4<0>; +L_0x1e4ded0 .delay (20000,20000,20000) L_0x1e4ded0/d; +v0x1e470f0_0 .net "S", 0 0, L_0x1e4e0a0; 1 drivers +v0x1e471b0_0 .alias "in0", 0 0, v0x1e47800_0; +v0x1e47250_0 .alias "in1", 0 0, v0x1e47cd0_0; +v0x1e472f0_0 .net "nS", 0 0, L_0x1e4dbf0; 1 drivers +v0x1e473a0_0 .net "out0", 0 0, L_0x1e4dcb0; 1 drivers +v0x1e47440_0 .net "out1", 0 0, L_0x1e4ddc0; 1 drivers +v0x1e474e0_0 .alias "outfinal", 0 0, v0x1e478b0_0; +S_0x1e45d70 .scope generate, "addbits[1]" "addbits[1]" 3 230, 3 230, S_0x1e43820; + .timescale -9 -12; +P_0x1e45788 .param/l "i" 3 230, +C4<01>; +S_0x1e45ee0 .scope module, "attempt" "MiddleAddSubSLT" 3 232, 3 89, S_0x1e45d70; + .timescale -9 -12; +L_0x1e44750/d .functor NOT 1, L_0x1e4ad10, C4<0>, C4<0>, C4<0>; +L_0x1e44750 .delay (10000,10000,10000) L_0x1e44750/d; +L_0x1e48df0/d .functor NOT 1, L_0x1e3c7e0, C4<0>, C4<0>, C4<0>; +L_0x1e48df0 .delay (10000,10000,10000) L_0x1e48df0/d; +L_0x1e3c880/d .functor AND 1, L_0x1e4a1d0, L_0x1e48df0, C4<1>, C4<1>; +L_0x1e3c880 .delay (20000,20000,20000) L_0x1e3c880/d; +L_0x1e4a270/d .functor XOR 1, L_0x1e4ab60, L_0x1e49b50, C4<0>, C4<0>; +L_0x1e4a270 .delay (40000,40000,40000) L_0x1e4a270/d; +L_0x1e4a360/d .functor XOR 1, L_0x1e4a270, L_0x1e4aec0, C4<0>, C4<0>; +L_0x1e4a360 .delay (40000,40000,40000) L_0x1e4a360/d; +L_0x1e4a450/d .functor AND 1, L_0x1e4ab60, L_0x1e49b50, C4<1>, C4<1>; +L_0x1e4a450 .delay (20000,20000,20000) L_0x1e4a450/d; +L_0x1e4a5c0/d .functor AND 1, L_0x1e4a270, L_0x1e4aec0, C4<1>, C4<1>; +L_0x1e4a5c0 .delay (20000,20000,20000) L_0x1e4a5c0/d; +L_0x1e4a6b0/d .functor OR 1, L_0x1e4a450, L_0x1e4a5c0, C4<0>, C4<0>; +L_0x1e4a6b0 .delay (20000,20000,20000) L_0x1e4a6b0/d; +v0x1e46570_0 .net "A", 0 0, L_0x1e4ab60; 1 drivers +v0x1e46630_0 .net "AandB", 0 0, L_0x1e4a450; 1 drivers +v0x1e466d0_0 .net "AddSubSLTSum", 0 0, L_0x1e4a360; 1 drivers +v0x1e46770_0 .net "AxorB", 0 0, L_0x1e4a270; 1 drivers +v0x1e467f0_0 .net "B", 0 0, L_0x1e4ad10; 1 drivers +v0x1e468a0_0 .net "BornB", 0 0, L_0x1e49b50; 1 drivers +v0x1e46960_0 .net "CINandAxorB", 0 0, L_0x1e4a5c0; 1 drivers +v0x1e469e0_0 .alias "Command", 2 0, v0x1e48140_0; +v0x1e46a60_0 .net *"_s3", 0 0, L_0x1e3c7e0; 1 drivers +v0x1e46ae0_0 .net *"_s5", 0 0, L_0x1e4a1d0; 1 drivers +v0x1e46b80_0 .net "carryin", 0 0, L_0x1e4aec0; 1 drivers +v0x1e46c20_0 .net "carryout", 0 0, L_0x1e4a6b0; 1 drivers +v0x1e46cc0_0 .net "nB", 0 0, L_0x1e44750; 1 drivers +v0x1e46d70_0 .net "nCmd2", 0 0, L_0x1e48df0; 1 drivers +v0x1e46e70_0 .net "subtract", 0 0, L_0x1e3c880; 1 drivers +L_0x1e49d20 .part v0x1e49280_0, 0, 1; +L_0x1e3c7e0 .part v0x1e49280_0, 2, 1; +L_0x1e4a1d0 .part v0x1e49280_0, 0, 1; +S_0x1e45fd0 .scope module, "mux0" "TwoInMux" 3 105, 3 8, S_0x1e45ee0; + .timescale -9 -12; +L_0x1e49870/d .functor NOT 1, L_0x1e49d20, C4<0>, C4<0>, C4<0>; +L_0x1e49870 .delay (10000,10000,10000) L_0x1e49870/d; +L_0x1e49930/d .functor AND 1, L_0x1e4ad10, L_0x1e49870, C4<1>, C4<1>; +L_0x1e49930 .delay (20000,20000,20000) L_0x1e49930/d; +L_0x1e49a40/d .functor AND 1, L_0x1e44750, L_0x1e49d20, C4<1>, C4<1>; +L_0x1e49a40 .delay (20000,20000,20000) L_0x1e49a40/d; +L_0x1e49b50/d .functor OR 1, L_0x1e49930, L_0x1e49a40, C4<0>, C4<0>; +L_0x1e49b50 .delay (20000,20000,20000) L_0x1e49b50/d; +v0x1e460c0_0 .net "S", 0 0, L_0x1e49d20; 1 drivers +v0x1e46160_0 .alias "in0", 0 0, v0x1e467f0_0; +v0x1e46200_0 .alias "in1", 0 0, v0x1e46cc0_0; +v0x1e462a0_0 .net "nS", 0 0, L_0x1e49870; 1 drivers +v0x1e46350_0 .net "out0", 0 0, L_0x1e49930; 1 drivers +v0x1e463f0_0 .net "out1", 0 0, L_0x1e49a40; 1 drivers +v0x1e464d0_0 .alias "outfinal", 0 0, v0x1e468a0_0; +S_0x1e44bd0 .scope generate, "addbits[2]" "addbits[2]" 3 230, 3 230, S_0x1e43820; + .timescale -9 -12; +P_0x1e44518 .param/l "i" 3 230, +C4<010>; +S_0x1e44d40 .scope module, "attempt" "MiddleAddSubSLT" 3 232, 3 89, S_0x1e44bd0; + .timescale -9 -12; +L_0x1e40590/d .functor NOT 1, L_0x1e4c300, C4<0>, C4<0>, C4<0>; +L_0x1e40590 .delay (10000,10000,10000) L_0x1e40590/d; +L_0x1e4b5e0/d .functor NOT 1, L_0x1e4b6a0, C4<0>, C4<0>, C4<0>; +L_0x1e4b5e0 .delay (10000,10000,10000) L_0x1e4b5e0/d; +L_0x1e4b740/d .functor AND 1, L_0x1e4b880, L_0x1e4b5e0, C4<1>, C4<1>; +L_0x1e4b740 .delay (20000,20000,20000) L_0x1e4b740/d; +L_0x1e4b920/d .functor XOR 1, L_0x1e4c200, L_0x1e4b370, C4<0>, C4<0>; +L_0x1e4b920 .delay (40000,40000,40000) L_0x1e4b920/d; +L_0x1e4ba10/d .functor XOR 1, L_0x1e4b920, L_0x1e4c430, C4<0>, C4<0>; +L_0x1e4ba10 .delay (40000,40000,40000) L_0x1e4ba10/d; +L_0x1e4bb00/d .functor AND 1, L_0x1e4c200, L_0x1e4b370, C4<1>, C4<1>; +L_0x1e4bb00 .delay (20000,20000,20000) L_0x1e4bb00/d; +L_0x1e4bc70/d .functor AND 1, L_0x1e4b920, L_0x1e4c430, C4<1>, C4<1>; +L_0x1e4bc70 .delay (20000,20000,20000) L_0x1e4bc70/d; +L_0x1e4bd80/d .functor OR 1, L_0x1e4bb00, L_0x1e4bc70, C4<0>, C4<0>; +L_0x1e4bd80 .delay (20000,20000,20000) L_0x1e4bd80/d; +v0x1e453d0_0 .net "A", 0 0, L_0x1e4c200; 1 drivers +v0x1e45490_0 .net "AandB", 0 0, L_0x1e4bb00; 1 drivers +v0x1e45530_0 .net "AddSubSLTSum", 0 0, L_0x1e4ba10; 1 drivers +v0x1e455d0_0 .net "AxorB", 0 0, L_0x1e4b920; 1 drivers +v0x1e45650_0 .net "B", 0 0, L_0x1e4c300; 1 drivers +v0x1e45700_0 .net "BornB", 0 0, L_0x1e4b370; 1 drivers +v0x1e457c0_0 .net "CINandAxorB", 0 0, L_0x1e4bc70; 1 drivers +v0x1e45840_0 .alias "Command", 2 0, v0x1e48140_0; +v0x1e458c0_0 .net *"_s3", 0 0, L_0x1e4b6a0; 1 drivers +v0x1e45940_0 .net *"_s5", 0 0, L_0x1e4b880; 1 drivers +v0x1e459e0_0 .net "carryin", 0 0, L_0x1e4c430; 1 drivers +v0x1e45a80_0 .net "carryout", 0 0, L_0x1e4bd80; 1 drivers +v0x1e45b20_0 .net "nB", 0 0, L_0x1e40590; 1 drivers +v0x1e45bd0_0 .net "nCmd2", 0 0, L_0x1e4b5e0; 1 drivers +v0x1e45cd0_0 .net "subtract", 0 0, L_0x1e4b740; 1 drivers +L_0x1e4b540 .part v0x1e49280_0, 0, 1; +L_0x1e4b6a0 .part v0x1e49280_0, 2, 1; +L_0x1e4b880 .part v0x1e49280_0, 0, 1; +S_0x1e44e30 .scope module, "mux0" "TwoInMux" 3 105, 3 8, S_0x1e44d40; + .timescale -9 -12; +L_0x1e4b090/d .functor NOT 1, L_0x1e4b540, C4<0>, C4<0>, C4<0>; +L_0x1e4b090 .delay (10000,10000,10000) L_0x1e4b090/d; +L_0x1e4b150/d .functor AND 1, L_0x1e4c300, L_0x1e4b090, C4<1>, C4<1>; +L_0x1e4b150 .delay (20000,20000,20000) L_0x1e4b150/d; +L_0x1e4b260/d .functor AND 1, L_0x1e40590, L_0x1e4b540, C4<1>, C4<1>; +L_0x1e4b260 .delay (20000,20000,20000) L_0x1e4b260/d; +L_0x1e4b370/d .functor OR 1, L_0x1e4b150, L_0x1e4b260, C4<0>, C4<0>; +L_0x1e4b370 .delay (20000,20000,20000) L_0x1e4b370/d; +v0x1e44f20_0 .net "S", 0 0, L_0x1e4b540; 1 drivers +v0x1e44fc0_0 .alias "in0", 0 0, v0x1e45650_0; +v0x1e45060_0 .alias "in1", 0 0, v0x1e45b20_0; +v0x1e45100_0 .net "nS", 0 0, L_0x1e4b090; 1 drivers +v0x1e451b0_0 .net "out0", 0 0, L_0x1e4b150; 1 drivers +v0x1e45250_0 .net "out1", 0 0, L_0x1e4b260; 1 drivers +v0x1e45330_0 .alias "outfinal", 0 0, v0x1e45700_0; +S_0x1e43990 .scope generate, "addbits[3]" "addbits[3]" 3 230, 3 230, S_0x1e43820; + .timescale -9 -12; +P_0x1e43a88 .param/l "i" 3 230, +C4<011>; +S_0x1e43b00 .scope module, "attempt" "MiddleAddSubSLT" 3 232, 3 89, S_0x1e43990; + .timescale -9 -12; +L_0x1e4c2a0/d .functor NOT 1, L_0x1e4d8a0, C4<0>, C4<0>, C4<0>; +L_0x1e4c2a0 .delay (10000,10000,10000) L_0x1e4c2a0/d; +L_0x1e4cb40/d .functor NOT 1, L_0x1e4cc00, C4<0>, C4<0>, C4<0>; +L_0x1e4cb40 .delay (10000,10000,10000) L_0x1e4cb40/d; +L_0x1e4cca0/d .functor AND 1, L_0x1e4cde0, L_0x1e4cb40, C4<1>, C4<1>; +L_0x1e4cca0 .delay (20000,20000,20000) L_0x1e4cca0/d; +L_0x1e4ce80/d .functor XOR 1, L_0x1e4d770, L_0x1e4c8d0, C4<0>, C4<0>; +L_0x1e4ce80 .delay (40000,40000,40000) L_0x1e4ce80/d; +L_0x1e4cf70/d .functor XOR 1, L_0x1e4ce80, L_0x1e4d9d0, C4<0>, C4<0>; +L_0x1e4cf70 .delay (40000,40000,40000) L_0x1e4cf70/d; +L_0x1e4d060/d .functor AND 1, L_0x1e4d770, L_0x1e4c8d0, C4<1>, C4<1>; +L_0x1e4d060 .delay (20000,20000,20000) L_0x1e4d060/d; +L_0x1e4d1d0/d .functor AND 1, L_0x1e4ce80, L_0x1e4d9d0, C4<1>, C4<1>; +L_0x1e4d1d0 .delay (20000,20000,20000) L_0x1e4d1d0/d; +L_0x1e4d2c0/d .functor OR 1, L_0x1e4d060, L_0x1e4d1d0, C4<0>, C4<0>; +L_0x1e4d2c0 .delay (20000,20000,20000) L_0x1e4d2c0/d; +v0x1e44160_0 .net "A", 0 0, L_0x1e4d770; 1 drivers +v0x1e44220_0 .net "AandB", 0 0, L_0x1e4d060; 1 drivers +v0x1e442c0_0 .net "AddSubSLTSum", 0 0, L_0x1e4cf70; 1 drivers +v0x1e44360_0 .net "AxorB", 0 0, L_0x1e4ce80; 1 drivers +v0x1e443e0_0 .net "B", 0 0, L_0x1e4d8a0; 1 drivers +v0x1e44490_0 .net "BornB", 0 0, L_0x1e4c8d0; 1 drivers +v0x1e44550_0 .net "CINandAxorB", 0 0, L_0x1e4d1d0; 1 drivers +v0x1e445d0_0 .alias "Command", 2 0, v0x1e48140_0; +v0x1e44650_0 .net *"_s3", 0 0, L_0x1e4cc00; 1 drivers +v0x1e446d0_0 .net *"_s5", 0 0, L_0x1e4cde0; 1 drivers +v0x1e447d0_0 .net "carryin", 0 0, L_0x1e4d9d0; 1 drivers +v0x1e44870_0 .net "carryout", 0 0, L_0x1e4d2c0; 1 drivers +v0x1e44980_0 .net "nB", 0 0, L_0x1e4c2a0; 1 drivers +v0x1e44a30_0 .net "nCmd2", 0 0, L_0x1e4cb40; 1 drivers +v0x1e44b30_0 .net "subtract", 0 0, L_0x1e4cca0; 1 drivers +L_0x1e4caa0 .part v0x1e49280_0, 0, 1; +L_0x1e4cc00 .part v0x1e49280_0, 2, 1; +L_0x1e4cde0 .part v0x1e49280_0, 0, 1; +S_0x1e43bf0 .scope module, "mux0" "TwoInMux" 3 105, 3 8, S_0x1e43b00; + .timescale -9 -12; +L_0x1e4c630/d .functor NOT 1, L_0x1e4caa0, C4<0>, C4<0>, C4<0>; +L_0x1e4c630 .delay (10000,10000,10000) L_0x1e4c630/d; +L_0x1e4c6b0/d .functor AND 1, L_0x1e4d8a0, L_0x1e4c630, C4<1>, C4<1>; +L_0x1e4c6b0 .delay (20000,20000,20000) L_0x1e4c6b0/d; +L_0x1e4c7c0/d .functor AND 1, L_0x1e4c2a0, L_0x1e4caa0, C4<1>, C4<1>; +L_0x1e4c7c0 .delay (20000,20000,20000) L_0x1e4c7c0/d; +L_0x1e4c8d0/d .functor OR 1, L_0x1e4c6b0, L_0x1e4c7c0, C4<0>, C4<0>; +L_0x1e4c8d0 .delay (20000,20000,20000) L_0x1e4c8d0/d; +v0x1e43ce0_0 .net "S", 0 0, L_0x1e4caa0; 1 drivers +v0x1e43d80_0 .alias "in0", 0 0, v0x1e443e0_0; +v0x1e43e20_0 .alias "in1", 0 0, v0x1e44980_0; +v0x1e43ec0_0 .net "nS", 0 0, L_0x1e4c630; 1 drivers +v0x1e43f40_0 .net "out0", 0 0, L_0x1e4c6b0; 1 drivers +v0x1e43fe0_0 .net "out1", 0 0, L_0x1e4c7c0; 1 drivers +v0x1e440c0_0 .alias "outfinal", 0 0, v0x1e44490_0; +S_0x1e40720 .scope module, "trial1" "AndNand32" 2 143, 3 154, S_0x1da9580; + .timescale -9 -12; +P_0x1e40818 .param/l "size" 3 161, +C4<0100>; +v0x1e43620_0 .alias "A", 3 0, v0x1e47f20_0; +v0x1e436a0_0 .alias "AndNandOut", 3 0, v0x1e49180_0; +v0x1e43720_0 .alias "B", 3 0, v0x1e48040_0; +v0x1e437a0_0 .alias "Command", 2 0, v0x1e48140_0; +L_0x1e509d0 .part/pv L_0x1e50760, 1, 1, 4; +L_0x1e50b20 .part v0x1e49000_0, 1, 1; +L_0x1e50bc0 .part v0x1e49200_0, 1, 1; +L_0x1e51480 .part/pv L_0x1e51210, 2, 1, 4; +L_0x1e51520 .part v0x1e49000_0, 2, 1; +L_0x1e515c0 .part v0x1e49200_0, 2, 1; +L_0x1e51ef0 .part/pv L_0x1e51c80, 3, 1, 4; +L_0x1e51f90 .part v0x1e49000_0, 3, 1; +L_0x1e52080 .part v0x1e49200_0, 3, 1; +L_0x1e52950 .part/pv L_0x1e526e0, 0, 1, 4; +L_0x1e52a50 .part v0x1e49000_0, 0, 1; +L_0x1e52af0 .part v0x1e49200_0, 0, 1; +S_0x1e42bf0 .scope module, "attempt2" "AndNand" 3 165, 3 48, S_0x1e40720; + .timescale -9 -12; +L_0x1e52170/d .functor NAND 1, L_0x1e52a50, L_0x1e52af0, C4<1>, C4<1>; +L_0x1e52170 .delay (10000,10000,10000) L_0x1e52170/d; +L_0x1e52290/d .functor NOT 1, L_0x1e52170, C4<0>, C4<0>, C4<0>; +L_0x1e52290 .delay (10000,10000,10000) L_0x1e52290/d; +v0x1e43210_0 .net "A", 0 0, L_0x1e52a50; 1 drivers +v0x1e432d0_0 .net "AandB", 0 0, L_0x1e52290; 1 drivers +v0x1e43350_0 .net "AnandB", 0 0, L_0x1e52170; 1 drivers +v0x1e43400_0 .net "AndNandOut", 0 0, L_0x1e526e0; 1 drivers +v0x1e434e0_0 .net "B", 0 0, L_0x1e52af0; 1 drivers +v0x1e43560_0 .alias "Command", 2 0, v0x1e48140_0; +L_0x1e528b0 .part v0x1e49280_0, 0, 1; +S_0x1e42ce0 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0x1e42bf0; + .timescale -9 -12; +L_0x1e523c0/d .functor NOT 1, L_0x1e528b0, C4<0>, C4<0>, C4<0>; +L_0x1e523c0 .delay (10000,10000,10000) L_0x1e523c0/d; +L_0x1e52480/d .functor AND 1, L_0x1e52290, L_0x1e523c0, C4<1>, C4<1>; +L_0x1e52480 .delay (20000,20000,20000) L_0x1e52480/d; +L_0x1e52590/d .functor AND 1, L_0x1e52170, L_0x1e528b0, C4<1>, C4<1>; +L_0x1e52590 .delay (20000,20000,20000) L_0x1e52590/d; +L_0x1e526e0/d .functor OR 1, L_0x1e52480, L_0x1e52590, C4<0>, C4<0>; +L_0x1e526e0 .delay (20000,20000,20000) L_0x1e526e0/d; +v0x1e42dd0_0 .net "S", 0 0, L_0x1e528b0; 1 drivers +v0x1e42e50_0 .alias "in0", 0 0, v0x1e432d0_0; +v0x1e42ed0_0 .alias "in1", 0 0, v0x1e43350_0; +v0x1e42f70_0 .net "nS", 0 0, L_0x1e523c0; 1 drivers +v0x1e42ff0_0 .net "out0", 0 0, L_0x1e52480; 1 drivers +v0x1e43090_0 .net "out1", 0 0, L_0x1e52590; 1 drivers +v0x1e43170_0 .alias "outfinal", 0 0, v0x1e43400_0; +S_0x1e42030 .scope generate, "andbits[1]" "andbits[1]" 3 169, 3 169, S_0x1e40720; + .timescale -9 -12; +P_0x1e42128 .param/l "i" 3 169, +C4<01>; +S_0x1e421a0 .scope module, "attempt" "AndNand" 3 171, 3 48, S_0x1e42030; + .timescale -9 -12; +L_0x1e50250/d .functor NAND 1, L_0x1e50b20, L_0x1e50bc0, C4<1>, C4<1>; +L_0x1e50250 .delay (10000,10000,10000) L_0x1e50250/d; +L_0x1e50310/d .functor NOT 1, L_0x1e50250, C4<0>, C4<0>, C4<0>; +L_0x1e50310 .delay (10000,10000,10000) L_0x1e50310/d; +v0x1e427e0_0 .net "A", 0 0, L_0x1e50b20; 1 drivers +v0x1e428a0_0 .net "AandB", 0 0, L_0x1e50310; 1 drivers +v0x1e42920_0 .net "AnandB", 0 0, L_0x1e50250; 1 drivers +v0x1e429d0_0 .net "AndNandOut", 0 0, L_0x1e50760; 1 drivers +v0x1e42ab0_0 .net "B", 0 0, L_0x1e50bc0; 1 drivers +v0x1e42b30_0 .alias "Command", 2 0, v0x1e48140_0; +L_0x1e50930 .part v0x1e49280_0, 0, 1; +S_0x1e42290 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0x1e421a0; + .timescale -9 -12; +L_0x1e50440/d .functor NOT 1, L_0x1e50930, C4<0>, C4<0>, C4<0>; +L_0x1e50440 .delay (10000,10000,10000) L_0x1e50440/d; +L_0x1e50500/d .functor AND 1, L_0x1e50310, L_0x1e50440, C4<1>, C4<1>; +L_0x1e50500 .delay (20000,20000,20000) L_0x1e50500/d; +L_0x1e50610/d .functor AND 1, L_0x1e50250, L_0x1e50930, C4<1>, C4<1>; +L_0x1e50610 .delay (20000,20000,20000) L_0x1e50610/d; +L_0x1e50760/d .functor OR 1, L_0x1e50500, L_0x1e50610, C4<0>, C4<0>; +L_0x1e50760 .delay (20000,20000,20000) L_0x1e50760/d; +v0x1e42380_0 .net "S", 0 0, L_0x1e50930; 1 drivers +v0x1e42400_0 .alias "in0", 0 0, v0x1e428a0_0; +v0x1e424a0_0 .alias "in1", 0 0, v0x1e42920_0; +v0x1e42540_0 .net "nS", 0 0, L_0x1e50440; 1 drivers +v0x1e425c0_0 .net "out0", 0 0, L_0x1e50500; 1 drivers +v0x1e42660_0 .net "out1", 0 0, L_0x1e50610; 1 drivers +v0x1e42740_0 .alias "outfinal", 0 0, v0x1e429d0_0; +S_0x1e41470 .scope generate, "andbits[2]" "andbits[2]" 3 169, 3 169, S_0x1e40720; + .timescale -9 -12; +P_0x1e41568 .param/l "i" 3 169, +C4<010>; +S_0x1e415e0 .scope module, "attempt" "AndNand" 3 171, 3 48, S_0x1e41470; + .timescale -9 -12; +L_0x1e50c60/d .functor NAND 1, L_0x1e51520, L_0x1e515c0, C4<1>, C4<1>; +L_0x1e50c60 .delay (10000,10000,10000) L_0x1e50c60/d; +L_0x1e50dc0/d .functor NOT 1, L_0x1e50c60, C4<0>, C4<0>, C4<0>; +L_0x1e50dc0 .delay (10000,10000,10000) L_0x1e50dc0/d; +v0x1e41c20_0 .net "A", 0 0, L_0x1e51520; 1 drivers +v0x1e41ce0_0 .net "AandB", 0 0, L_0x1e50dc0; 1 drivers +v0x1e41d60_0 .net "AnandB", 0 0, L_0x1e50c60; 1 drivers +v0x1e41e10_0 .net "AndNandOut", 0 0, L_0x1e51210; 1 drivers +v0x1e41ef0_0 .net "B", 0 0, L_0x1e515c0; 1 drivers +v0x1e41f70_0 .alias "Command", 2 0, v0x1e48140_0; +L_0x1e513e0 .part v0x1e49280_0, 0, 1; +S_0x1e416d0 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0x1e415e0; + .timescale -9 -12; +L_0x1e50ef0/d .functor NOT 1, L_0x1e513e0, C4<0>, C4<0>, C4<0>; +L_0x1e50ef0 .delay (10000,10000,10000) L_0x1e50ef0/d; +L_0x1e50fb0/d .functor AND 1, L_0x1e50dc0, L_0x1e50ef0, C4<1>, C4<1>; +L_0x1e50fb0 .delay (20000,20000,20000) L_0x1e50fb0/d; +L_0x1e510c0/d .functor AND 1, L_0x1e50c60, L_0x1e513e0, C4<1>, C4<1>; +L_0x1e510c0 .delay (20000,20000,20000) L_0x1e510c0/d; +L_0x1e51210/d .functor OR 1, L_0x1e50fb0, L_0x1e510c0, C4<0>, C4<0>; +L_0x1e51210 .delay (20000,20000,20000) L_0x1e51210/d; +v0x1e417c0_0 .net "S", 0 0, L_0x1e513e0; 1 drivers +v0x1e41840_0 .alias "in0", 0 0, v0x1e41ce0_0; +v0x1e418e0_0 .alias "in1", 0 0, v0x1e41d60_0; +v0x1e41980_0 .net "nS", 0 0, L_0x1e50ef0; 1 drivers +v0x1e41a00_0 .net "out0", 0 0, L_0x1e50fb0; 1 drivers +v0x1e41aa0_0 .net "out1", 0 0, L_0x1e510c0; 1 drivers +v0x1e41b80_0 .alias "outfinal", 0 0, v0x1e41e10_0; +S_0x1e40890 .scope generate, "andbits[3]" "andbits[3]" 3 169, 3 169, S_0x1e40720; + .timescale -9 -12; +P_0x1e40988 .param/l "i" 3 169, +C4<011>; +S_0x1e40a00 .scope module, "attempt" "AndNand" 3 171, 3 48, S_0x1e40890; + .timescale -9 -12; +L_0x1e516f0/d .functor NAND 1, L_0x1e51f90, L_0x1e52080, C4<1>, C4<1>; +L_0x1e516f0 .delay (10000,10000,10000) L_0x1e516f0/d; +L_0x1e51830/d .functor NOT 1, L_0x1e516f0, C4<0>, C4<0>, C4<0>; +L_0x1e51830 .delay (10000,10000,10000) L_0x1e51830/d; +v0x1e41060_0 .net "A", 0 0, L_0x1e51f90; 1 drivers +v0x1e41120_0 .net "AandB", 0 0, L_0x1e51830; 1 drivers +v0x1e411a0_0 .net "AnandB", 0 0, L_0x1e516f0; 1 drivers +v0x1e41250_0 .net "AndNandOut", 0 0, L_0x1e51c80; 1 drivers +v0x1e41330_0 .net "B", 0 0, L_0x1e52080; 1 drivers +v0x1e413b0_0 .alias "Command", 2 0, v0x1e48140_0; +L_0x1e51e50 .part v0x1e49280_0, 0, 1; +S_0x1e40af0 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0x1e40a00; + .timescale -9 -12; +L_0x1e51960/d .functor NOT 1, L_0x1e51e50, C4<0>, C4<0>, C4<0>; +L_0x1e51960 .delay (10000,10000,10000) L_0x1e51960/d; +L_0x1e51a20/d .functor AND 1, L_0x1e51830, L_0x1e51960, C4<1>, C4<1>; +L_0x1e51a20 .delay (20000,20000,20000) L_0x1e51a20/d; +L_0x1e51b30/d .functor AND 1, L_0x1e516f0, L_0x1e51e50, C4<1>, C4<1>; +L_0x1e51b30 .delay (20000,20000,20000) L_0x1e51b30/d; +L_0x1e51c80/d .functor OR 1, L_0x1e51a20, L_0x1e51b30, C4<0>, C4<0>; +L_0x1e51c80 .delay (20000,20000,20000) L_0x1e51c80/d; +v0x1e40be0_0 .net "S", 0 0, L_0x1e51e50; 1 drivers +v0x1e40c80_0 .alias "in0", 0 0, v0x1e41120_0; +v0x1e40d20_0 .alias "in1", 0 0, v0x1e411a0_0; +v0x1e40dc0_0 .net "nS", 0 0, L_0x1e51960; 1 drivers +v0x1e40e40_0 .net "out0", 0 0, L_0x1e51a20; 1 drivers +v0x1e40ee0_0 .net "out1", 0 0, L_0x1e51b30; 1 drivers +v0x1e40fc0_0 .alias "outfinal", 0 0, v0x1e41250_0; +S_0x1e3b560 .scope module, "trial2" "OrNorXor32" 2 145, 3 177, S_0x1da9580; + .timescale -9 -12; +P_0x1e38fd8 .param/l "size" 3 184, +C4<0100>; +v0x1e40400_0 .alias "A", 3 0, v0x1e47f20_0; +v0x1e40510_0 .alias "B", 3 0, v0x1e48040_0; +v0x1e40620_0 .alias "Command", 2 0, v0x1e48140_0; +v0x1e406a0_0 .alias "OrNorXorOut", 3 0, v0x1e49380_0; +L_0x1e53ca0 .part/pv L_0x1e53a30, 1, 1, 4; +L_0x1e53dd0 .part v0x1e49000_0, 1, 1; +L_0x1e4ac00 .part v0x1e49200_0, 1, 1; +L_0x1e55200 .part/pv L_0x1e54f90, 2, 1, 4; +L_0x1e552a0 .part v0x1e49000_0, 2, 1; +L_0x1e55340 .part v0x1e49200_0, 2, 1; +L_0x1e56500 .part/pv L_0x1e56290, 3, 1, 4; +L_0x1e565a0 .part v0x1e49000_0, 3, 1; +L_0x1e56640 .part v0x1e49200_0, 3, 1; +L_0x1e577b0 .part/pv L_0x1e57540, 0, 1, 4; +L_0x1e578b0 .part v0x1e49000_0, 0, 1; +L_0x1e57950 .part v0x1e49200_0, 0, 1; +S_0x1e3f260 .scope module, "attempt2" "OrNorXor" 3 192, 3 64, S_0x1e3b560; + .timescale -9 -12; +L_0x1e566e0/d .functor NOR 1, L_0x1e578b0, L_0x1e57950, C4<0>, C4<0>; +L_0x1e566e0 .delay (10000,10000,10000) L_0x1e566e0/d; +L_0x1e567e0/d .functor NOT 1, L_0x1e566e0, C4<0>, C4<0>, C4<0>; +L_0x1e567e0 .delay (10000,10000,10000) L_0x1e567e0/d; +L_0x1e56910/d .functor NAND 1, L_0x1e578b0, L_0x1e57950, C4<1>, C4<1>; +L_0x1e56910 .delay (10000,10000,10000) L_0x1e56910/d; +L_0x1e56a70/d .functor NAND 1, L_0x1e56910, L_0x1e567e0, C4<1>, C4<1>; +L_0x1e56a70 .delay (10000,10000,10000) L_0x1e56a70/d; +L_0x1e56b80/d .functor NOT 1, L_0x1e56a70, C4<0>, C4<0>, C4<0>; +L_0x1e56b80 .delay (10000,10000,10000) L_0x1e56b80/d; +v0x1e3fdb0_0 .net "A", 0 0, L_0x1e578b0; 1 drivers +v0x1e3fe50_0 .net "AnandB", 0 0, L_0x1e56910; 1 drivers +v0x1e3fef0_0 .net "AnorB", 0 0, L_0x1e566e0; 1 drivers +v0x1e3ffa0_0 .net "AorB", 0 0, L_0x1e567e0; 1 drivers +v0x1e40020_0 .net "AxorB", 0 0, L_0x1e56b80; 1 drivers +v0x1e400a0_0 .net "B", 0 0, L_0x1e57950; 1 drivers +v0x1e40120_0 .alias "Command", 2 0, v0x1e48140_0; +v0x1e401a0_0 .net "OrNorXorOut", 0 0, L_0x1e57540; 1 drivers +v0x1e40250_0 .net "XorNor", 0 0, L_0x1e56fc0; 1 drivers +v0x1e40320_0 .net "nXor", 0 0, L_0x1e56a70; 1 drivers +L_0x1e57140 .part v0x1e49280_0, 2, 1; +L_0x1e57710 .part v0x1e49280_0, 0, 1; +S_0x1e3f840 .scope module, "mux0" "TwoInMux" 3 83, 3 8, S_0x1e3f260; + .timescale -9 -12; +L_0x1e56ca0/d .functor NOT 1, L_0x1e57140, C4<0>, C4<0>, C4<0>; +L_0x1e56ca0 .delay (10000,10000,10000) L_0x1e56ca0/d; +L_0x1e56d60/d .functor AND 1, L_0x1e56b80, L_0x1e56ca0, C4<1>, C4<1>; +L_0x1e56d60 .delay (20000,20000,20000) L_0x1e56d60/d; +L_0x1e56e70/d .functor AND 1, L_0x1e566e0, L_0x1e57140, C4<1>, C4<1>; +L_0x1e56e70 .delay (20000,20000,20000) L_0x1e56e70/d; +L_0x1e56fc0/d .functor OR 1, L_0x1e56d60, L_0x1e56e70, C4<0>, C4<0>; +L_0x1e56fc0 .delay (20000,20000,20000) L_0x1e56fc0/d; +v0x1e3f930_0 .net "S", 0 0, L_0x1e57140; 1 drivers +v0x1e3f9f0_0 .alias "in0", 0 0, v0x1e40020_0; +v0x1e3fa90_0 .alias "in1", 0 0, v0x1e3fef0_0; +v0x1e3fb30_0 .net "nS", 0 0, L_0x1e56ca0; 1 drivers +v0x1e3fbb0_0 .net "out0", 0 0, L_0x1e56d60; 1 drivers +v0x1e3fc50_0 .net "out1", 0 0, L_0x1e56e70; 1 drivers +v0x1e3fd30_0 .alias "outfinal", 0 0, v0x1e40250_0; +S_0x1e3f350 .scope module, "mux1" "TwoInMux" 3 84, 3 8, S_0x1e3f260; + .timescale -9 -12; +L_0x1e571e0/d .functor NOT 1, L_0x1e57710, C4<0>, C4<0>, C4<0>; +L_0x1e571e0 .delay (10000,10000,10000) L_0x1e571e0/d; +L_0x1e572a0/d .functor AND 1, L_0x1e56fc0, L_0x1e571e0, C4<1>, C4<1>; +L_0x1e572a0 .delay (20000,20000,20000) L_0x1e572a0/d; +L_0x1e573f0/d .functor AND 1, L_0x1e567e0, L_0x1e57710, C4<1>, C4<1>; +L_0x1e573f0 .delay (20000,20000,20000) L_0x1e573f0/d; +L_0x1e57540/d .functor OR 1, L_0x1e572a0, L_0x1e573f0, C4<0>, C4<0>; +L_0x1e57540 .delay (20000,20000,20000) L_0x1e57540/d; +v0x1e3f440_0 .net "S", 0 0, L_0x1e57710; 1 drivers +v0x1e3f4c0_0 .alias "in0", 0 0, v0x1e40250_0; +v0x1e3f540_0 .alias "in1", 0 0, v0x1e3ffa0_0; +v0x1e3f5e0_0 .net "nS", 0 0, L_0x1e571e0; 1 drivers +v0x1e3f660_0 .net "out0", 0 0, L_0x1e572a0; 1 drivers +v0x1e3f700_0 .net "out1", 0 0, L_0x1e573f0; 1 drivers +v0x1e3f7a0_0 .alias "outfinal", 0 0, v0x1e401a0_0; +S_0x1e3de90 .scope generate, "orbits[1]" "orbits[1]" 3 196, 3 196, S_0x1e3b560; + .timescale -9 -12; +P_0x1e3dba8 .param/l "i" 3 196, +C4<01>; +S_0x1e3dfc0 .scope module, "attempt" "OrNorXor" 3 198, 3 64, S_0x1e3de90; + .timescale -9 -12; +L_0x1e529f0/d .functor NOR 1, L_0x1e53dd0, L_0x1e4ac00, C4<0>, C4<0>; +L_0x1e529f0 .delay (10000,10000,10000) L_0x1e529f0/d; +L_0x1e52c90/d .functor NOT 1, L_0x1e529f0, C4<0>, C4<0>, C4<0>; +L_0x1e52c90 .delay (10000,10000,10000) L_0x1e52c90/d; +L_0x1e52dc0/d .functor NAND 1, L_0x1e53dd0, L_0x1e4ac00, C4<1>, C4<1>; +L_0x1e52dc0 .delay (10000,10000,10000) L_0x1e52dc0/d; +L_0x1e52f20/d .functor NAND 1, L_0x1e52dc0, L_0x1e52c90, C4<1>, C4<1>; +L_0x1e52f20 .delay (10000,10000,10000) L_0x1e52f20/d; +L_0x1e53030/d .functor NOT 1, L_0x1e52f20, C4<0>, C4<0>, C4<0>; +L_0x1e53030 .delay (10000,10000,10000) L_0x1e53030/d; +v0x1e3eb70_0 .net "A", 0 0, L_0x1e53dd0; 1 drivers +v0x1e3ec10_0 .net "AnandB", 0 0, L_0x1e52dc0; 1 drivers +v0x1e3ecb0_0 .net "AnorB", 0 0, L_0x1e529f0; 1 drivers +v0x1e3ed60_0 .net "AorB", 0 0, L_0x1e52c90; 1 drivers +v0x1e3ee40_0 .net "AxorB", 0 0, L_0x1e53030; 1 drivers +v0x1e3eef0_0 .net "B", 0 0, L_0x1e4ac00; 1 drivers +v0x1e3efb0_0 .alias "Command", 2 0, v0x1e48140_0; +v0x1e3f030_0 .net "OrNorXorOut", 0 0, L_0x1e53a30; 1 drivers +v0x1e3f0b0_0 .net "XorNor", 0 0, L_0x1e534b0; 1 drivers +v0x1e3f180_0 .net "nXor", 0 0, L_0x1e52f20; 1 drivers +L_0x1e53630 .part v0x1e49280_0, 2, 1; +L_0x1e53c00 .part v0x1e49280_0, 0, 1; +S_0x1e3e600 .scope module, "mux0" "TwoInMux" 3 83, 3 8, S_0x1e3dfc0; + .timescale -9 -12; +L_0x1e53190/d .functor NOT 1, L_0x1e53630, C4<0>, C4<0>, C4<0>; +L_0x1e53190 .delay (10000,10000,10000) L_0x1e53190/d; +L_0x1e53250/d .functor AND 1, L_0x1e53030, L_0x1e53190, C4<1>, C4<1>; +L_0x1e53250 .delay (20000,20000,20000) L_0x1e53250/d; +L_0x1e53360/d .functor AND 1, L_0x1e529f0, L_0x1e53630, C4<1>, C4<1>; +L_0x1e53360 .delay (20000,20000,20000) L_0x1e53360/d; +L_0x1e534b0/d .functor OR 1, L_0x1e53250, L_0x1e53360, C4<0>, C4<0>; +L_0x1e534b0 .delay (20000,20000,20000) L_0x1e534b0/d; +v0x1e3e6f0_0 .net "S", 0 0, L_0x1e53630; 1 drivers +v0x1e3e7b0_0 .alias "in0", 0 0, v0x1e3ee40_0; +v0x1e3e850_0 .alias "in1", 0 0, v0x1e3ecb0_0; +v0x1e3e8f0_0 .net "nS", 0 0, L_0x1e53190; 1 drivers +v0x1e3e970_0 .net "out0", 0 0, L_0x1e53250; 1 drivers +v0x1e3ea10_0 .net "out1", 0 0, L_0x1e53360; 1 drivers +v0x1e3eaf0_0 .alias "outfinal", 0 0, v0x1e3f0b0_0; +S_0x1e3e0b0 .scope module, "mux1" "TwoInMux" 3 84, 3 8, S_0x1e3dfc0; + .timescale -9 -12; +L_0x1e536d0/d .functor NOT 1, L_0x1e53c00, C4<0>, C4<0>, C4<0>; +L_0x1e536d0 .delay (10000,10000,10000) L_0x1e536d0/d; +L_0x1e53790/d .functor AND 1, L_0x1e534b0, L_0x1e536d0, C4<1>, C4<1>; +L_0x1e53790 .delay (20000,20000,20000) L_0x1e53790/d; +L_0x1e538e0/d .functor AND 1, L_0x1e52c90, L_0x1e53c00, C4<1>, C4<1>; +L_0x1e538e0 .delay (20000,20000,20000) L_0x1e538e0/d; +L_0x1e53a30/d .functor OR 1, L_0x1e53790, L_0x1e538e0, C4<0>, C4<0>; +L_0x1e53a30 .delay (20000,20000,20000) L_0x1e53a30/d; +v0x1e3e1a0_0 .net "S", 0 0, L_0x1e53c00; 1 drivers +v0x1e3e220_0 .alias "in0", 0 0, v0x1e3f0b0_0; +v0x1e3e2c0_0 .alias "in1", 0 0, v0x1e3ed60_0; +v0x1e3e360_0 .net "nS", 0 0, L_0x1e536d0; 1 drivers +v0x1e3e3e0_0 .net "out0", 0 0, L_0x1e53790; 1 drivers +v0x1e3e480_0 .net "out1", 0 0, L_0x1e538e0; 1 drivers +v0x1e3e560_0 .alias "outfinal", 0 0, v0x1e3f030_0; +S_0x1e3cac0 .scope generate, "orbits[2]" "orbits[2]" 3 196, 3 196, S_0x1e3b560; + .timescale -9 -12; +P_0x1e3c728 .param/l "i" 3 196, +C4<010>; +S_0x1e3cbf0 .scope module, "attempt" "OrNorXor" 3 198, 3 64, S_0x1e3cac0; + .timescale -9 -12; +L_0x1e4aca0/d .functor NOR 1, L_0x1e552a0, L_0x1e55340, C4<0>, C4<0>; +L_0x1e4aca0 .delay (10000,10000,10000) L_0x1e4aca0/d; +L_0x1e4ae10/d .functor NOT 1, L_0x1e4aca0, C4<0>, C4<0>, C4<0>; +L_0x1e4ae10 .delay (10000,10000,10000) L_0x1e4ae10/d; +L_0x1e54320/d .functor NAND 1, L_0x1e552a0, L_0x1e55340, C4<1>, C4<1>; +L_0x1e54320 .delay (10000,10000,10000) L_0x1e54320/d; +L_0x1e54480/d .functor NAND 1, L_0x1e54320, L_0x1e4ae10, C4<1>, C4<1>; +L_0x1e54480 .delay (10000,10000,10000) L_0x1e54480/d; +L_0x1e54590/d .functor NOT 1, L_0x1e54480, C4<0>, C4<0>, C4<0>; +L_0x1e54590 .delay (10000,10000,10000) L_0x1e54590/d; +v0x1e3d7a0_0 .net "A", 0 0, L_0x1e552a0; 1 drivers +v0x1e3d840_0 .net "AnandB", 0 0, L_0x1e54320; 1 drivers +v0x1e3d8e0_0 .net "AnorB", 0 0, L_0x1e4aca0; 1 drivers +v0x1e3d990_0 .net "AorB", 0 0, L_0x1e4ae10; 1 drivers +v0x1e3da70_0 .net "AxorB", 0 0, L_0x1e54590; 1 drivers +v0x1e3db20_0 .net "B", 0 0, L_0x1e55340; 1 drivers +v0x1e3dbe0_0 .alias "Command", 2 0, v0x1e48140_0; +v0x1e3dc60_0 .net "OrNorXorOut", 0 0, L_0x1e54f90; 1 drivers +v0x1e3dce0_0 .net "XorNor", 0 0, L_0x1e54a10; 1 drivers +v0x1e3ddb0_0 .net "nXor", 0 0, L_0x1e54480; 1 drivers +L_0x1e54b90 .part v0x1e49280_0, 2, 1; +L_0x1e55160 .part v0x1e49280_0, 0, 1; +S_0x1e3d230 .scope module, "mux0" "TwoInMux" 3 83, 3 8, S_0x1e3cbf0; + .timescale -9 -12; +L_0x1e546f0/d .functor NOT 1, L_0x1e54b90, C4<0>, C4<0>, C4<0>; +L_0x1e546f0 .delay (10000,10000,10000) L_0x1e546f0/d; +L_0x1e547b0/d .functor AND 1, L_0x1e54590, L_0x1e546f0, C4<1>, C4<1>; +L_0x1e547b0 .delay (20000,20000,20000) L_0x1e547b0/d; +L_0x1e548c0/d .functor AND 1, L_0x1e4aca0, L_0x1e54b90, C4<1>, C4<1>; +L_0x1e548c0 .delay (20000,20000,20000) L_0x1e548c0/d; +L_0x1e54a10/d .functor OR 1, L_0x1e547b0, L_0x1e548c0, C4<0>, C4<0>; +L_0x1e54a10 .delay (20000,20000,20000) L_0x1e54a10/d; +v0x1e3d320_0 .net "S", 0 0, L_0x1e54b90; 1 drivers +v0x1e3d3e0_0 .alias "in0", 0 0, v0x1e3da70_0; +v0x1e3d480_0 .alias "in1", 0 0, v0x1e3d8e0_0; +v0x1e3d520_0 .net "nS", 0 0, L_0x1e546f0; 1 drivers +v0x1e3d5a0_0 .net "out0", 0 0, L_0x1e547b0; 1 drivers +v0x1e3d640_0 .net "out1", 0 0, L_0x1e548c0; 1 drivers +v0x1e3d720_0 .alias "outfinal", 0 0, v0x1e3dce0_0; +S_0x1e3cce0 .scope module, "mux1" "TwoInMux" 3 84, 3 8, S_0x1e3cbf0; + .timescale -9 -12; +L_0x1e54c30/d .functor NOT 1, L_0x1e55160, C4<0>, C4<0>, C4<0>; +L_0x1e54c30 .delay (10000,10000,10000) L_0x1e54c30/d; +L_0x1e54cf0/d .functor AND 1, L_0x1e54a10, L_0x1e54c30, C4<1>, C4<1>; +L_0x1e54cf0 .delay (20000,20000,20000) L_0x1e54cf0/d; +L_0x1e54e40/d .functor AND 1, L_0x1e4ae10, L_0x1e55160, C4<1>, C4<1>; +L_0x1e54e40 .delay (20000,20000,20000) L_0x1e54e40/d; +L_0x1e54f90/d .functor OR 1, L_0x1e54cf0, L_0x1e54e40, C4<0>, C4<0>; +L_0x1e54f90 .delay (20000,20000,20000) L_0x1e54f90/d; +v0x1e3cdd0_0 .net "S", 0 0, L_0x1e55160; 1 drivers +v0x1e3ce50_0 .alias "in0", 0 0, v0x1e3dce0_0; +v0x1e3cef0_0 .alias "in1", 0 0, v0x1e3d990_0; +v0x1e3cf90_0 .net "nS", 0 0, L_0x1e54c30; 1 drivers +v0x1e3d010_0 .net "out0", 0 0, L_0x1e54cf0; 1 drivers +v0x1e3d0b0_0 .net "out1", 0 0, L_0x1e54e40; 1 drivers +v0x1e3d190_0 .alias "outfinal", 0 0, v0x1e3dc60_0; +S_0x1e3b650 .scope generate, "orbits[3]" "orbits[3]" 3 196, 3 196, S_0x1e3b560; + .timescale -9 -12; +P_0x1e3b398 .param/l "i" 3 196, +C4<011>; +S_0x1e3b740 .scope module, "attempt" "OrNorXor" 3 198, 3 64, S_0x1e3b650; + .timescale -9 -12; +L_0x1e55420/d .functor NOR 1, L_0x1e565a0, L_0x1e56640, C4<0>, C4<0>; +L_0x1e55420 .delay (10000,10000,10000) L_0x1e55420/d; +L_0x1e55510/d .functor NOT 1, L_0x1e55420, C4<0>, C4<0>, C4<0>; +L_0x1e55510 .delay (10000,10000,10000) L_0x1e55510/d; +L_0x1e55620/d .functor NAND 1, L_0x1e565a0, L_0x1e56640, C4<1>, C4<1>; +L_0x1e55620 .delay (10000,10000,10000) L_0x1e55620/d; +L_0x1e55780/d .functor NAND 1, L_0x1e55620, L_0x1e55510, C4<1>, C4<1>; +L_0x1e55780 .delay (10000,10000,10000) L_0x1e55780/d; +L_0x1e55890/d .functor NOT 1, L_0x1e55780, C4<0>, C4<0>, C4<0>; +L_0x1e55890 .delay (10000,10000,10000) L_0x1e55890/d; +v0x1e3c320_0 .net "A", 0 0, L_0x1e565a0; 1 drivers +v0x1e3c3c0_0 .net "AnandB", 0 0, L_0x1e55620; 1 drivers +v0x1e3c460_0 .net "AnorB", 0 0, L_0x1e55420; 1 drivers +v0x1e3c510_0 .net "AorB", 0 0, L_0x1e55510; 1 drivers +v0x1e3c5f0_0 .net "AxorB", 0 0, L_0x1e55890; 1 drivers +v0x1e3c6a0_0 .net "B", 0 0, L_0x1e56640; 1 drivers +v0x1e3c760_0 .alias "Command", 2 0, v0x1e48140_0; +v0x1e34bc0_0 .net "OrNorXorOut", 0 0, L_0x1e56290; 1 drivers +v0x1e34c40_0 .net "XorNor", 0 0, L_0x1e55d10; 1 drivers +v0x1e3ca40_0 .net "nXor", 0 0, L_0x1e55780; 1 drivers +L_0x1e55e90 .part v0x1e49280_0, 2, 1; +L_0x1e56460 .part v0x1e49280_0, 0, 1; +S_0x1e3bdb0 .scope module, "mux0" "TwoInMux" 3 83, 3 8, S_0x1e3b740; + .timescale -9 -12; +L_0x1e559f0/d .functor NOT 1, L_0x1e55e90, C4<0>, C4<0>, C4<0>; +L_0x1e559f0 .delay (10000,10000,10000) L_0x1e559f0/d; +L_0x1e55ab0/d .functor AND 1, L_0x1e55890, L_0x1e559f0, C4<1>, C4<1>; +L_0x1e55ab0 .delay (20000,20000,20000) L_0x1e55ab0/d; +L_0x1e55bc0/d .functor AND 1, L_0x1e55420, L_0x1e55e90, C4<1>, C4<1>; +L_0x1e55bc0 .delay (20000,20000,20000) L_0x1e55bc0/d; +L_0x1e55d10/d .functor OR 1, L_0x1e55ab0, L_0x1e55bc0, C4<0>, C4<0>; +L_0x1e55d10 .delay (20000,20000,20000) L_0x1e55d10/d; +v0x1e3bea0_0 .net "S", 0 0, L_0x1e55e90; 1 drivers +v0x1e3bf60_0 .alias "in0", 0 0, v0x1e3c5f0_0; +v0x1e3c000_0 .alias "in1", 0 0, v0x1e3c460_0; +v0x1e3c0a0_0 .net "nS", 0 0, L_0x1e559f0; 1 drivers +v0x1e3c120_0 .net "out0", 0 0, L_0x1e55ab0; 1 drivers +v0x1e3c1c0_0 .net "out1", 0 0, L_0x1e55bc0; 1 drivers +v0x1e3c2a0_0 .alias "outfinal", 0 0, v0x1e34c40_0; +S_0x1e3b830 .scope module, "mux1" "TwoInMux" 3 84, 3 8, S_0x1e3b740; + .timescale -9 -12; +L_0x1e55f30/d .functor NOT 1, L_0x1e56460, C4<0>, C4<0>, C4<0>; +L_0x1e55f30 .delay (10000,10000,10000) L_0x1e55f30/d; +L_0x1e55ff0/d .functor AND 1, L_0x1e55d10, L_0x1e55f30, C4<1>, C4<1>; +L_0x1e55ff0 .delay (20000,20000,20000) L_0x1e55ff0/d; +L_0x1e56140/d .functor AND 1, L_0x1e55510, L_0x1e56460, C4<1>, C4<1>; +L_0x1e56140 .delay (20000,20000,20000) L_0x1e56140/d; +L_0x1e56290/d .functor OR 1, L_0x1e55ff0, L_0x1e56140, C4<0>, C4<0>; +L_0x1e56290 .delay (20000,20000,20000) L_0x1e56290/d; +v0x1e3b920_0 .net "S", 0 0, L_0x1e56460; 1 drivers +v0x1e3b9a0_0 .alias "in0", 0 0, v0x1e34c40_0; +v0x1e3ba40_0 .alias "in1", 0 0, v0x1e3c510_0; +v0x1e3bae0_0 .net "nS", 0 0, L_0x1e55f30; 1 drivers +v0x1e3bb90_0 .net "out0", 0 0, L_0x1e55ff0; 1 drivers +v0x1e3bc30_0 .net "out1", 0 0, L_0x1e56140; 1 drivers +v0x1e3bd10_0 .alias "outfinal", 0 0, v0x1e34bc0_0; +S_0x1da9070 .scope module, "superalu" "Bitslice32" 2 147, 3 256, S_0x1da9580; + .timescale -9 -12; +P_0x1da88a8 .param/l "size" 3 273, +C4<0100>; +L_0x1e5c990/d .functor AND 1, L_0x1e6f5c0, L_0x1e6f7a0, C4<1>, C4<1>; +L_0x1e5c990 .delay (20000,20000,20000) L_0x1e5c990/d; +L_0x1e6f890/d .functor NOT 1, L_0x1e6f940, C4<0>, C4<0>, C4<0>; +L_0x1e6f890 .delay (10000,10000,10000) L_0x1e6f890/d; +L_0x1e6fdf0/d .functor AND 1, L_0x1e6f890, L_0x1e6f890, C4<1>, C4<1>; +L_0x1e6fdf0 .delay (20000,20000,20000) L_0x1e6fdf0/d; +v0x1e3a450_0 .alias "A", 3 0, v0x1e47f20_0; +v0x1e3a640_0 .alias "AddSubSLTSum", 3 0, v0x1e49080_0; +v0x1e3a6c0_0 .alias "AllZeros", 0 0, v0x1e49100_0; +v0x1e3a740_0 .alias "AndNandOut", 3 0, v0x1e49180_0; +v0x1e3a7f0_0 .alias "B", 3 0, v0x1e48040_0; +RS_0x7f060963b008 .resolv tri, L_0x1e580f0, L_0x1e5a9a0, L_0x1e5d6f0, L_0x1e6d990; +v0x1e3a870_0 .net8 "Cmd0Start", 3 0, RS_0x7f060963b008; 4 drivers +RS_0x7f060963b038 .resolv tri, L_0x1e58f40, L_0x1e5b860, L_0x1e5e6e0, L_0x1e6e7c0; +v0x1e3a8f0_0 .net8 "Cmd1Start", 3 0, RS_0x7f060963b038; 4 drivers +v0x1e3a970_0 .alias "Command", 2 0, v0x1e48140_0; +v0x1e3a9f0_0 .alias "OneBitFinalOut", 3 0, v0x1e49300_0; +v0x1e3aa90_0 .alias "OrNorXorOut", 3 0, v0x1e49380_0; +v0x1e3ab10_0 .alias "SLTflag", 0 0, v0x1e49400_0; +v0x1e3abc0_0 .alias "ZeroFlag", 3 0, v0x1e49480_0; +v0x1e3ac40_0 .net *"_s111", 0 0, L_0x1e5c990; 1 drivers +v0x1e3acc0_0 .net *"_s114", 0 0, L_0x1e6f5c0; 1 drivers +v0x1e3ade0_0 .net *"_s116", 0 0, L_0x1e6f7a0; 1 drivers +v0x1e3ae80_0 .net *"_s118", 0 0, L_0x1e6f940; 1 drivers +v0x1e3ad40_0 .net *"_s21", 0 0, L_0x1e59f90; 1 drivers +v0x1e3afd0_0 .net *"_s46", 0 0, L_0x1e5c2e0; 1 drivers +v0x1e3b0f0_0 .net *"_s71", 0 0, L_0x1e5f4a0; 1 drivers +v0x1e3b170_0 .alias "carryin", 3 0, v0x1e48b70_0; +v0x1e3b050_0 .alias "carryout", 0 0, v0x1e49580_0; +v0x1e3b2d0_0 .alias "overflow", 0 0, v0x1e49600_0; +v0x1e3b220_0 .alias "subtract", 3 0, v0x1e49680_0; +v0x1e3b410_0 .net "yeszero", 0 0, L_0x1e6f890; 1 drivers +L_0x1e580f0 .part/pv L_0x1e57f10, 1, 1, 4; +L_0x1e58190 .part v0x1e49280_0, 0, 1; +L_0x1e582c0 .part v0x1e49280_0, 1, 1; +L_0x1e583f0 .part RS_0x7f060963abe8, 1, 1; +L_0x1e58490 .part RS_0x7f060963abe8, 1, 1; +L_0x1e58530 .part RS_0x7f0609639748, 1, 1; +L_0x1e58730 .part RS_0x7f060963abe8, 1, 1; +L_0x1e58f40 .part/pv L_0x1e58d60, 1, 1, 4; +L_0x1e59030 .part v0x1e49280_0, 0, 1; +L_0x1e59160 .part v0x1e49280_0, 1, 1; +L_0x1e592f0 .part RS_0x7f0609639e38, 1, 1; +L_0x1e594a0 .part RS_0x7f0609639e38, 1, 1; +L_0x1e59540 .part RS_0x7f0609639748, 1, 1; +L_0x1e595e0 .part RS_0x7f0609639748, 1, 1; +L_0x1e59a40 .part/pv L_0x1e59900, 1, 1, 4; +L_0x1e59b30 .part v0x1e49280_0, 2, 1; +L_0x1e59bd0 .part RS_0x7f060963b008, 1, 1; +L_0x1e59d10 .part RS_0x7f060963b038, 1, 1; +L_0x1e59ef0 .part/pv L_0x1e59f90, 1, 1, 4; +L_0x1e5a090 .part RS_0x7f060963b098, 0, 1; +L_0x1e59e50 .part RS_0x7f060963b068, 1, 1; +L_0x1e5a9a0 .part/pv L_0x1e5a7c0, 2, 1, 4; +L_0x1e5a130 .part v0x1e49280_0, 0, 1; +L_0x1e5ab90 .part v0x1e49280_0, 1, 1; +L_0x1e5aa40 .part RS_0x7f060963abe8, 2, 1; +L_0x1e5ad90 .part RS_0x7f060963abe8, 2, 1; +L_0x1e5acc0 .part RS_0x7f0609639748, 2, 1; +L_0x1e5af60 .part RS_0x7f060963abe8, 2, 1; +L_0x1e5b860 .part/pv L_0x1e5b650, 2, 1, 4; +L_0x1e5b900 .part v0x1e49280_0, 0, 1; +L_0x1e5b050 .part v0x1e49280_0, 1, 1; +L_0x1e49f50 .part RS_0x7f0609639e38, 2, 1; +L_0x1e4a100 .part RS_0x7f0609639e38, 2, 1; +L_0x1e49dc0 .part RS_0x7f0609639748, 2, 1; +L_0x1e49ff0 .part RS_0x7f0609639748, 2, 1; +L_0x1e5c690 .part/pv L_0x1e5c550, 2, 1, 4; +L_0x1e5c240 .part v0x1e49280_0, 2, 1; +L_0x1e5c8f0 .part RS_0x7f060963b008, 2, 1; +L_0x1e5c7c0 .part RS_0x7f060963b038, 2, 1; +L_0x1e5cb60 .part/pv L_0x1e5c2e0, 2, 1, 4; +L_0x1e5ca60 .part RS_0x7f060963b098, 1, 1; +L_0x1e5cde0 .part RS_0x7f060963b068, 2, 1; +L_0x1e5d6f0 .part/pv L_0x1e5d4e0, 3, 1, 4; +L_0x1e5d790 .part v0x1e49280_0, 0, 1; +L_0x1e5ce80 .part v0x1e49280_0, 1, 1; +L_0x1e5da30 .part RS_0x7f060963abe8, 3, 1; +L_0x1e4f9f0 .part RS_0x7f060963abe8, 3, 1; +L_0x1e5d8c0 .part RS_0x7f0609639748, 3, 1; +L_0x1e5de70 .part RS_0x7f060963abe8, 3, 1; +L_0x1e5e6e0 .part/pv L_0x1e5e4d0, 3, 1, 4; +L_0x1e5dce0 .part v0x1e49280_0, 0, 1; +L_0x1e5e920 .part v0x1e49280_0, 1, 1; +L_0x1e5e780 .part RS_0x7f0609639e38, 3, 1; +L_0x1e5e820 .part RS_0x7f0609639e38, 3, 1; +L_0x1e5ec10 .part RS_0x7f0609639748, 3, 1; +L_0x1e5ecb0 .part RS_0x7f0609639748, 3, 1; +L_0x1e5f2c0 .part/pv L_0x1e5f180, 3, 1, 4; +L_0x1e5f360 .part v0x1e49280_0, 2, 1; +L_0x1e5ef60 .part RS_0x7f060963b008, 3, 1; +L_0x1e5f050 .part RS_0x7f060963b038, 3, 1; +L_0x1e5f400 .part/pv L_0x1e5f4a0, 3, 1, 4; +L_0x1e5f820 .part RS_0x7f060963b098, 2, 1; +L_0x1e5f630 .part RS_0x7f060963b068, 3, 1; +L_0x1e6d990 .part/pv L_0x1e6d7b0, 0, 1, 4; +L_0x1e5f8c0 .part v0x1e49280_0, 0, 1; +L_0x1e5f9f0 .part v0x1e49280_0, 1, 1; +L_0x1e6da30 .part RS_0x7f060963abe8, 0, 1; +L_0x1e6dad0 .part RS_0x7f060963abe8, 0, 1; +L_0x1e6db70 .part RS_0x7f0609639748, 0, 1; +L_0x1e6df50 .part RS_0x7f060963abe8, 0, 1; +L_0x1e6e7c0 .part/pv L_0x1e6e5e0, 0, 1, 4; +L_0x1e6e860 .part v0x1e49280_0, 0, 1; +L_0x1e6e040 .part v0x1e49280_0, 1, 1; +L_0x1e6e170 .part RS_0x7f0609639e38, 0, 1; +L_0x1e6ebf0 .part RS_0x7f0609639e38, 0, 1; +L_0x1e6ec90 .part RS_0x7f0609639748, 0, 1; +L_0x1e6e990 .part RS_0x7f0609639748, 0, 1; +L_0x1e6f260 .part/pv L_0x1e6f120, 0, 1, 4; +L_0x1e6ed30 .part v0x1e49280_0, 2, 1; +L_0x1e6edd0 .part RS_0x7f060963b008, 0, 1; +L_0x1e6eec0 .part RS_0x7f060963b038, 0, 1; +L_0x1e6f520 .part/pv L_0x1e5c990, 0, 1, 4; +L_0x1e6f5c0 .part RS_0x7f060963b068, 0, 1; +L_0x1e6f7a0 .part RS_0x7f060963b068, 0, 1; +L_0x1e6f940 .part RS_0x7f060963b098, 3, 1; +S_0x1e34eb0 .scope module, "trial" "AddSubSLT32" 3 279, 3 205, S_0x1da9070; + .timescale -9 -12; +P_0x1e34fa8 .param/l "size" 3 228, +C4<0100>; +L_0x1e64920/d .functor OR 1, L_0x1e64be0, C4<0>, C4<0>, C4<0>; +L_0x1e64920 .delay (20000,20000,20000) L_0x1e64920/d; +L_0x1e64d90/d .functor XOR 1, RS_0x7f060963aee8, L_0x1e64e80, C4<0>, C4<0>; +L_0x1e64d90 .delay (40000,40000,40000) L_0x1e64d90/d; +L_0x1e64b10/d .functor AND 1, L_0x1e65050, L_0x1e650f0, C4<1>, C4<1>; +L_0x1e64b10 .delay (20000,20000,20000) L_0x1e64b10/d; +L_0x1e64f20/d .functor NOT 1, RS_0x7f060963af78, C4<0>, C4<0>, C4<0>; +L_0x1e64f20 .delay (10000,10000,10000) L_0x1e64f20/d; +L_0x1e653e0/d .functor NOT 1, L_0x1e65440, C4<0>, C4<0>, C4<0>; +L_0x1e653e0 .delay (10000,10000,10000) L_0x1e653e0/d; +L_0x1e654e0/d .functor AND 1, L_0x1e64f20, L_0x1e65620, C4<1>, C4<1>; +L_0x1e654e0 .delay (20000,20000,20000) L_0x1e654e0/d; +L_0x1e651e0/d .functor AND 1, RS_0x7f060963af78, L_0x1e653e0, C4<1>, C4<1>; +L_0x1e651e0 .delay (20000,20000,20000) L_0x1e651e0/d; +L_0x1e65810/d .functor AND 1, L_0x1e654e0, L_0x1e64b10, C4<1>, C4<1>; +L_0x1e65810 .delay (20000,20000,20000) L_0x1e65810/d; +L_0x1e65950/d .functor AND 1, L_0x1e651e0, L_0x1e64b10, C4<1>, C4<1>; +L_0x1e65950 .delay (20000,20000,20000) L_0x1e65950/d; +L_0x1e65a70/d .functor OR 1, L_0x1e65810, L_0x1e65950, C4<0>, C4<0>; +L_0x1e65a70 .delay (20000,20000,20000) L_0x1e65a70/d; +v0x1e395c0_0 .alias "A", 3 0, v0x1e47f20_0; +v0x1e39660_0 .alias "AddSubSLTSum", 3 0, v0x1e49080_0; +v0x1e39700_0 .alias "B", 3 0, v0x1e48040_0; +RS_0x7f060963ac18 .resolv tri, L_0x1e60950, L_0x1e61d70, L_0x1e63170, L_0x1e64690; +v0x1e39780_0 .net8 "CarryoutWire", 3 0, RS_0x7f060963ac18; 4 drivers +v0x1e39800_0 .alias "Command", 2 0, v0x1e48140_0; +v0x1e39880_0 .net "Res0OF1", 0 0, L_0x1e651e0; 1 drivers +v0x1e39920_0 .net "Res1OF0", 0 0, L_0x1e654e0; 1 drivers +v0x1e399c0_0 .alias "SLTflag", 0 0, v0x1e49400_0; +v0x1e39ab0_0 .net "SLTflag0", 0 0, L_0x1e65810; 1 drivers +v0x1e39b50_0 .net "SLTflag1", 0 0, L_0x1e65950; 1 drivers +v0x1e39bf0_0 .net "SLTon", 0 0, L_0x1e64b10; 1 drivers +v0x1e39c90_0 .net *"_s40", 0 0, L_0x1e64be0; 1 drivers +v0x1e39d30_0 .net/s *"_s41", 0 0, C4<0>; 1 drivers +v0x1e39dd0_0 .net *"_s44", 0 0, L_0x1e64e80; 1 drivers +v0x1e39ef0_0 .net *"_s46", 0 0, L_0x1e65050; 1 drivers +v0x1e39f90_0 .net *"_s48", 0 0, L_0x1e650f0; 1 drivers +v0x1e39e50_0 .net *"_s50", 0 0, L_0x1e65440; 1 drivers +v0x1e3a0e0_0 .net *"_s52", 0 0, L_0x1e65620; 1 drivers +v0x1e3a200_0 .alias "carryin", 3 0, v0x1e48b70_0; +v0x1e3a280_0 .alias "carryout", 0 0, v0x1e49580_0; +v0x1e3a160_0 .net "nAddSubSLTSum", 0 0, L_0x1e653e0; 1 drivers +v0x1e3a3b0_0 .net "nOF", 0 0, L_0x1e64f20; 1 drivers +v0x1e3a300_0 .alias "overflow", 0 0, v0x1e49600_0; +v0x1e3a4f0_0 .alias "subtract", 3 0, v0x1e49680_0; +L_0x1e60860 .part/pv L_0x1e603d0, 1, 1, 4; +L_0x1e60950 .part/pv L_0x1e60720, 1, 1, 4; +L_0x1e60a40 .part/pv L_0x1e60100, 1, 1, 4; +L_0x1e60b30 .part v0x1e49000_0, 1, 1; +L_0x1e60bd0 .part v0x1e49200_0, 1, 1; +L_0x1e60d00 .part RS_0x7f060963ac18, 0, 1; +L_0x1e61c80 .part/pv L_0x1e617f0, 2, 1, 4; +L_0x1e61d70 .part/pv L_0x1e61b40, 2, 1, 4; +L_0x1e61eb0 .part/pv L_0x1e61520, 2, 1, 4; +L_0x1e61fa0 .part v0x1e49000_0, 2, 1; +L_0x1e620a0 .part v0x1e49200_0, 2, 1; +L_0x1e621d0 .part RS_0x7f060963ac18, 1, 1; +L_0x1e63080 .part/pv L_0x1e62bf0, 3, 1, 4; +L_0x1e63170 .part/pv L_0x1e62f40, 3, 1, 4; +L_0x1e632e0 .part/pv L_0x1e62920, 3, 1, 4; +L_0x1e633d0 .part v0x1e49000_0, 3, 1; +L_0x1e63500 .part v0x1e49200_0, 3, 1; +L_0x1e63630 .part RS_0x7f060963ac18, 2, 1; +L_0x1e645a0 .part/pv L_0x1e640d0, 0, 1, 4; +L_0x1e64690 .part/pv L_0x1e64440, 0, 1, 4; +L_0x1e636d0 .part/pv L_0x1e63e00, 0, 1, 4; +L_0x1e64880 .part v0x1e49000_0, 0, 1; +L_0x1e64780 .part v0x1e49200_0, 0, 1; +L_0x1e64a70 .part RS_0x7f060963afa8, 0, 1; +L_0x1e64be0 .part RS_0x7f060963ac18, 3, 1; +L_0x1e64e80 .part RS_0x7f060963ac18, 2, 1; +L_0x1e65050 .part v0x1e49280_0, 1, 1; +L_0x1e650f0 .part RS_0x7f060963afa8, 0, 1; +L_0x1e65440 .part RS_0x7f060963abe8, 3, 1; +L_0x1e65620 .part RS_0x7f060963abe8, 3, 1; +S_0x1e385b0 .scope module, "attempt2" "MiddleAddSubSLT" 3 225, 3 89, S_0x1e34eb0; + .timescale -9 -12; +L_0x1e63470/d .functor NOT 1, L_0x1e64780, C4<0>, C4<0>, C4<0>; +L_0x1e63470 .delay (10000,10000,10000) L_0x1e63470/d; +L_0x1e63cc0/d .functor NOT 1, L_0x1e63d60, C4<0>, C4<0>, C4<0>; +L_0x1e63cc0 .delay (10000,10000,10000) L_0x1e63cc0/d; +L_0x1e63e00/d .functor AND 1, L_0x1e63f40, L_0x1e63cc0, C4<1>, C4<1>; +L_0x1e63e00 .delay (20000,20000,20000) L_0x1e63e00/d; +L_0x1e63fe0/d .functor XOR 1, L_0x1e64880, L_0x1e63a90, C4<0>, C4<0>; +L_0x1e63fe0 .delay (40000,40000,40000) L_0x1e63fe0/d; +L_0x1e640d0/d .functor XOR 1, L_0x1e63fe0, L_0x1e64a70, C4<0>, C4<0>; +L_0x1e640d0 .delay (40000,40000,40000) L_0x1e640d0/d; +L_0x1e641c0/d .functor AND 1, L_0x1e64880, L_0x1e63a90, C4<1>, C4<1>; +L_0x1e641c0 .delay (20000,20000,20000) L_0x1e641c0/d; +L_0x1e64330/d .functor AND 1, L_0x1e63fe0, L_0x1e64a70, C4<1>, C4<1>; +L_0x1e64330 .delay (20000,20000,20000) L_0x1e64330/d; +L_0x1e64440/d .functor OR 1, L_0x1e641c0, L_0x1e64330, C4<0>, C4<0>; +L_0x1e64440 .delay (20000,20000,20000) L_0x1e64440/d; +v0x1e38c20_0 .net "A", 0 0, L_0x1e64880; 1 drivers +v0x1e38ce0_0 .net "AandB", 0 0, L_0x1e641c0; 1 drivers +v0x1e38d80_0 .net "AddSubSLTSum", 0 0, L_0x1e640d0; 1 drivers +v0x1e38e20_0 .net "AxorB", 0 0, L_0x1e63fe0; 1 drivers +v0x1e38ea0_0 .net "B", 0 0, L_0x1e64780; 1 drivers +v0x1e38f50_0 .net "BornB", 0 0, L_0x1e63a90; 1 drivers +v0x1e39010_0 .net "CINandAxorB", 0 0, L_0x1e64330; 1 drivers +v0x1e39090_0 .alias "Command", 2 0, v0x1e48140_0; +v0x1e39110_0 .net *"_s3", 0 0, L_0x1e63d60; 1 drivers +v0x1e39190_0 .net *"_s5", 0 0, L_0x1e63f40; 1 drivers +v0x1e39230_0 .net "carryin", 0 0, L_0x1e64a70; 1 drivers +v0x1e392d0_0 .net "carryout", 0 0, L_0x1e64440; 1 drivers +v0x1e39370_0 .net "nB", 0 0, L_0x1e63470; 1 drivers +v0x1e39420_0 .net "nCmd2", 0 0, L_0x1e63cc0; 1 drivers +v0x1e39520_0 .net "subtract", 0 0, L_0x1e63e00; 1 drivers +L_0x1e63c20 .part v0x1e49280_0, 0, 1; +L_0x1e63d60 .part v0x1e49280_0, 2, 1; +L_0x1e63f40 .part v0x1e49280_0, 0, 1; +S_0x1e386a0 .scope module, "mux0" "TwoInMux" 3 105, 3 8, S_0x1e385b0; + .timescale -9 -12; +L_0x1e63810/d .functor NOT 1, L_0x1e63c20, C4<0>, C4<0>, C4<0>; +L_0x1e63810 .delay (10000,10000,10000) L_0x1e63810/d; +L_0x1e638b0/d .functor AND 1, L_0x1e64780, L_0x1e63810, C4<1>, C4<1>; +L_0x1e638b0 .delay (20000,20000,20000) L_0x1e638b0/d; +L_0x1e639a0/d .functor AND 1, L_0x1e63470, L_0x1e63c20, C4<1>, C4<1>; +L_0x1e639a0 .delay (20000,20000,20000) L_0x1e639a0/d; +L_0x1e63a90/d .functor OR 1, L_0x1e638b0, L_0x1e639a0, C4<0>, C4<0>; +L_0x1e63a90 .delay (20000,20000,20000) L_0x1e63a90/d; +v0x1e38790_0 .net "S", 0 0, L_0x1e63c20; 1 drivers +v0x1e38850_0 .alias "in0", 0 0, v0x1e38ea0_0; +v0x1e388f0_0 .alias "in1", 0 0, v0x1e39370_0; +v0x1e38990_0 .net "nS", 0 0, L_0x1e63810; 1 drivers +v0x1e38a40_0 .net "out0", 0 0, L_0x1e638b0; 1 drivers +v0x1e38ae0_0 .net "out1", 0 0, L_0x1e639a0; 1 drivers +v0x1e38b80_0 .alias "outfinal", 0 0, v0x1e38f50_0; +S_0x1e37410 .scope generate, "addbits[1]" "addbits[1]" 3 230, 3 230, S_0x1e34eb0; + .timescale -9 -12; +P_0x1e36e28 .param/l "i" 3 230, +C4<01>; +S_0x1e37580 .scope module, "attempt" "MiddleAddSubSLT" 3 232, 3 89, S_0x1e37410; + .timescale -9 -12; +L_0x1e5f720/d .functor NOT 1, L_0x1e60bd0, C4<0>, C4<0>, C4<0>; +L_0x1e5f720 .delay (10000,10000,10000) L_0x1e5f720/d; +L_0x1e5ffc0/d .functor NOT 1, L_0x1e60060, C4<0>, C4<0>, C4<0>; +L_0x1e5ffc0 .delay (10000,10000,10000) L_0x1e5ffc0/d; +L_0x1e60100/d .functor AND 1, L_0x1e60240, L_0x1e5ffc0, C4<1>, C4<1>; +L_0x1e60100 .delay (20000,20000,20000) L_0x1e60100/d; +L_0x1e602e0/d .functor XOR 1, L_0x1e60b30, L_0x1e5fd90, C4<0>, C4<0>; +L_0x1e602e0 .delay (40000,40000,40000) L_0x1e602e0/d; +L_0x1e603d0/d .functor XOR 1, L_0x1e602e0, L_0x1e60d00, C4<0>, C4<0>; +L_0x1e603d0 .delay (40000,40000,40000) L_0x1e603d0/d; +L_0x1e604c0/d .functor AND 1, L_0x1e60b30, L_0x1e5fd90, C4<1>, C4<1>; +L_0x1e604c0 .delay (20000,20000,20000) L_0x1e604c0/d; +L_0x1e60630/d .functor AND 1, L_0x1e602e0, L_0x1e60d00, C4<1>, C4<1>; +L_0x1e60630 .delay (20000,20000,20000) L_0x1e60630/d; +L_0x1e60720/d .functor OR 1, L_0x1e604c0, L_0x1e60630, C4<0>, C4<0>; +L_0x1e60720 .delay (20000,20000,20000) L_0x1e60720/d; +v0x1e37c10_0 .net "A", 0 0, L_0x1e60b30; 1 drivers +v0x1e37cd0_0 .net "AandB", 0 0, L_0x1e604c0; 1 drivers +v0x1e37d70_0 .net "AddSubSLTSum", 0 0, L_0x1e603d0; 1 drivers +v0x1e37e10_0 .net "AxorB", 0 0, L_0x1e602e0; 1 drivers +v0x1e37e90_0 .net "B", 0 0, L_0x1e60bd0; 1 drivers +v0x1e37f40_0 .net "BornB", 0 0, L_0x1e5fd90; 1 drivers +v0x1e38000_0 .net "CINandAxorB", 0 0, L_0x1e60630; 1 drivers +v0x1e38080_0 .alias "Command", 2 0, v0x1e48140_0; +v0x1e38100_0 .net *"_s3", 0 0, L_0x1e60060; 1 drivers +v0x1e38180_0 .net *"_s5", 0 0, L_0x1e60240; 1 drivers +v0x1e38220_0 .net "carryin", 0 0, L_0x1e60d00; 1 drivers +v0x1e382c0_0 .net "carryout", 0 0, L_0x1e60720; 1 drivers +v0x1e38360_0 .net "nB", 0 0, L_0x1e5f720; 1 drivers +v0x1e38410_0 .net "nCmd2", 0 0, L_0x1e5ffc0; 1 drivers +v0x1e38510_0 .net "subtract", 0 0, L_0x1e60100; 1 drivers +L_0x1e5ff20 .part v0x1e49280_0, 0, 1; +L_0x1e60060 .part v0x1e49280_0, 2, 1; +L_0x1e60240 .part v0x1e49280_0, 0, 1; +S_0x1e37670 .scope module, "mux0" "TwoInMux" 3 105, 3 8, S_0x1e37580; + .timescale -9 -12; +L_0x1e5fb10/d .functor NOT 1, L_0x1e5ff20, C4<0>, C4<0>, C4<0>; +L_0x1e5fb10 .delay (10000,10000,10000) L_0x1e5fb10/d; +L_0x1e5fbb0/d .functor AND 1, L_0x1e60bd0, L_0x1e5fb10, C4<1>, C4<1>; +L_0x1e5fbb0 .delay (20000,20000,20000) L_0x1e5fbb0/d; +L_0x1e5fca0/d .functor AND 1, L_0x1e5f720, L_0x1e5ff20, C4<1>, C4<1>; +L_0x1e5fca0 .delay (20000,20000,20000) L_0x1e5fca0/d; +L_0x1e5fd90/d .functor OR 1, L_0x1e5fbb0, L_0x1e5fca0, C4<0>, C4<0>; +L_0x1e5fd90 .delay (20000,20000,20000) L_0x1e5fd90/d; +v0x1e37760_0 .net "S", 0 0, L_0x1e5ff20; 1 drivers +v0x1e37800_0 .alias "in0", 0 0, v0x1e37e90_0; +v0x1e378a0_0 .alias "in1", 0 0, v0x1e38360_0; +v0x1e37940_0 .net "nS", 0 0, L_0x1e5fb10; 1 drivers +v0x1e379f0_0 .net "out0", 0 0, L_0x1e5fbb0; 1 drivers +v0x1e37a90_0 .net "out1", 0 0, L_0x1e5fca0; 1 drivers +v0x1e37b70_0 .alias "outfinal", 0 0, v0x1e37f40_0; +S_0x1e36270 .scope generate, "addbits[2]" "addbits[2]" 3 230, 3 230, S_0x1e34eb0; + .timescale -9 -12; +P_0x1e35bb8 .param/l "i" 3 230, +C4<010>; +S_0x1e363e0 .scope module, "attempt" "MiddleAddSubSLT" 3 232, 3 89, S_0x1e36270; + .timescale -9 -12; +L_0x1e60da0/d .functor NOT 1, L_0x1e620a0, C4<0>, C4<0>, C4<0>; +L_0x1e60da0 .delay (10000,10000,10000) L_0x1e60da0/d; +L_0x1e613e0/d .functor NOT 1, L_0x1e61480, C4<0>, C4<0>, C4<0>; +L_0x1e613e0 .delay (10000,10000,10000) L_0x1e613e0/d; +L_0x1e61520/d .functor AND 1, L_0x1e61660, L_0x1e613e0, C4<1>, C4<1>; +L_0x1e61520 .delay (20000,20000,20000) L_0x1e61520/d; +L_0x1e61700/d .functor XOR 1, L_0x1e61fa0, L_0x1e611b0, C4<0>, C4<0>; +L_0x1e61700 .delay (40000,40000,40000) L_0x1e61700/d; +L_0x1e617f0/d .functor XOR 1, L_0x1e61700, L_0x1e621d0, C4<0>, C4<0>; +L_0x1e617f0 .delay (40000,40000,40000) L_0x1e617f0/d; +L_0x1e618e0/d .functor AND 1, L_0x1e61fa0, L_0x1e611b0, C4<1>, C4<1>; +L_0x1e618e0 .delay (20000,20000,20000) L_0x1e618e0/d; +L_0x1e61a50/d .functor AND 1, L_0x1e61700, L_0x1e621d0, C4<1>, C4<1>; +L_0x1e61a50 .delay (20000,20000,20000) L_0x1e61a50/d; +L_0x1e61b40/d .functor OR 1, L_0x1e618e0, L_0x1e61a50, C4<0>, C4<0>; +L_0x1e61b40 .delay (20000,20000,20000) L_0x1e61b40/d; +v0x1e36a70_0 .net "A", 0 0, L_0x1e61fa0; 1 drivers +v0x1e36b30_0 .net "AandB", 0 0, L_0x1e618e0; 1 drivers +v0x1e36bd0_0 .net "AddSubSLTSum", 0 0, L_0x1e617f0; 1 drivers +v0x1e36c70_0 .net "AxorB", 0 0, L_0x1e61700; 1 drivers +v0x1e36cf0_0 .net "B", 0 0, L_0x1e620a0; 1 drivers +v0x1e36da0_0 .net "BornB", 0 0, L_0x1e611b0; 1 drivers +v0x1e36e60_0 .net "CINandAxorB", 0 0, L_0x1e61a50; 1 drivers +v0x1e36ee0_0 .alias "Command", 2 0, v0x1e48140_0; +v0x1e36f60_0 .net *"_s3", 0 0, L_0x1e61480; 1 drivers +v0x1e36fe0_0 .net *"_s5", 0 0, L_0x1e61660; 1 drivers +v0x1e37080_0 .net "carryin", 0 0, L_0x1e621d0; 1 drivers +v0x1e37120_0 .net "carryout", 0 0, L_0x1e61b40; 1 drivers +v0x1e371c0_0 .net "nB", 0 0, L_0x1e60da0; 1 drivers +v0x1e37270_0 .net "nCmd2", 0 0, L_0x1e613e0; 1 drivers +v0x1e37370_0 .net "subtract", 0 0, L_0x1e61520; 1 drivers +L_0x1e61340 .part v0x1e49280_0, 0, 1; +L_0x1e61480 .part v0x1e49280_0, 2, 1; +L_0x1e61660 .part v0x1e49280_0, 0, 1; +S_0x1e364d0 .scope module, "mux0" "TwoInMux" 3 105, 3 8, S_0x1e363e0; + .timescale -9 -12; +L_0x1e60f30/d .functor NOT 1, L_0x1e61340, C4<0>, C4<0>, C4<0>; +L_0x1e60f30 .delay (10000,10000,10000) L_0x1e60f30/d; +L_0x1e60fd0/d .functor AND 1, L_0x1e620a0, L_0x1e60f30, C4<1>, C4<1>; +L_0x1e60fd0 .delay (20000,20000,20000) L_0x1e60fd0/d; +L_0x1e610c0/d .functor AND 1, L_0x1e60da0, L_0x1e61340, C4<1>, C4<1>; +L_0x1e610c0 .delay (20000,20000,20000) L_0x1e610c0/d; +L_0x1e611b0/d .functor OR 1, L_0x1e60fd0, L_0x1e610c0, C4<0>, C4<0>; +L_0x1e611b0 .delay (20000,20000,20000) L_0x1e611b0/d; +v0x1e365c0_0 .net "S", 0 0, L_0x1e61340; 1 drivers +v0x1e36660_0 .alias "in0", 0 0, v0x1e36cf0_0; +v0x1e36700_0 .alias "in1", 0 0, v0x1e371c0_0; +v0x1e367a0_0 .net "nS", 0 0, L_0x1e60f30; 1 drivers +v0x1e36850_0 .net "out0", 0 0, L_0x1e60fd0; 1 drivers +v0x1e368f0_0 .net "out1", 0 0, L_0x1e610c0; 1 drivers +v0x1e369d0_0 .alias "outfinal", 0 0, v0x1e36da0_0; +S_0x1e35020 .scope generate, "addbits[3]" "addbits[3]" 3 230, 3 230, S_0x1e34eb0; + .timescale -9 -12; +P_0x1e35118 .param/l "i" 3 230, +C4<011>; +S_0x1e35190 .scope module, "attempt" "MiddleAddSubSLT" 3 232, 3 89, S_0x1e35020; + .timescale -9 -12; +L_0x1e62040/d .functor NOT 1, L_0x1e63500, C4<0>, C4<0>, C4<0>; +L_0x1e62040 .delay (10000,10000,10000) L_0x1e62040/d; +L_0x1e627e0/d .functor NOT 1, L_0x1e62880, C4<0>, C4<0>, C4<0>; +L_0x1e627e0 .delay (10000,10000,10000) L_0x1e627e0/d; +L_0x1e62920/d .functor AND 1, L_0x1e62a60, L_0x1e627e0, C4<1>, C4<1>; +L_0x1e62920 .delay (20000,20000,20000) L_0x1e62920/d; +L_0x1e62b00/d .functor XOR 1, L_0x1e633d0, L_0x1e625b0, C4<0>, C4<0>; +L_0x1e62b00 .delay (40000,40000,40000) L_0x1e62b00/d; +L_0x1e62bf0/d .functor XOR 1, L_0x1e62b00, L_0x1e63630, C4<0>, C4<0>; +L_0x1e62bf0 .delay (40000,40000,40000) L_0x1e62bf0/d; +L_0x1e62ce0/d .functor AND 1, L_0x1e633d0, L_0x1e625b0, C4<1>, C4<1>; +L_0x1e62ce0 .delay (20000,20000,20000) L_0x1e62ce0/d; +L_0x1e62e50/d .functor AND 1, L_0x1e62b00, L_0x1e63630, C4<1>, C4<1>; +L_0x1e62e50 .delay (20000,20000,20000) L_0x1e62e50/d; +L_0x1e62f40/d .functor OR 1, L_0x1e62ce0, L_0x1e62e50, C4<0>, C4<0>; +L_0x1e62f40 .delay (20000,20000,20000) L_0x1e62f40/d; +v0x1e35800_0 .net "A", 0 0, L_0x1e633d0; 1 drivers +v0x1e358c0_0 .net "AandB", 0 0, L_0x1e62ce0; 1 drivers +v0x1e35960_0 .net "AddSubSLTSum", 0 0, L_0x1e62bf0; 1 drivers +v0x1e35a00_0 .net "AxorB", 0 0, L_0x1e62b00; 1 drivers +v0x1e35a80_0 .net "B", 0 0, L_0x1e63500; 1 drivers +v0x1e35b30_0 .net "BornB", 0 0, L_0x1e625b0; 1 drivers +v0x1e35bf0_0 .net "CINandAxorB", 0 0, L_0x1e62e50; 1 drivers +v0x1e35c70_0 .alias "Command", 2 0, v0x1e48140_0; +v0x1e35cf0_0 .net *"_s3", 0 0, L_0x1e62880; 1 drivers +v0x1e35d70_0 .net *"_s5", 0 0, L_0x1e62a60; 1 drivers +v0x1e35e70_0 .net "carryin", 0 0, L_0x1e63630; 1 drivers +v0x1e35f10_0 .net "carryout", 0 0, L_0x1e62f40; 1 drivers +v0x1e36020_0 .net "nB", 0 0, L_0x1e62040; 1 drivers +v0x1e360d0_0 .net "nCmd2", 0 0, L_0x1e627e0; 1 drivers +v0x1e361d0_0 .net "subtract", 0 0, L_0x1e62920; 1 drivers +L_0x1e62740 .part v0x1e49280_0, 0, 1; +L_0x1e62880 .part v0x1e49280_0, 2, 1; +L_0x1e62a60 .part v0x1e49280_0, 0, 1; +S_0x1e35280 .scope module, "mux0" "TwoInMux" 3 105, 3 8, S_0x1e35190; + .timescale -9 -12; +L_0x1e62370/d .functor NOT 1, L_0x1e62740, C4<0>, C4<0>, C4<0>; +L_0x1e62370 .delay (10000,10000,10000) L_0x1e62370/d; +L_0x1e623d0/d .functor AND 1, L_0x1e63500, L_0x1e62370, C4<1>, C4<1>; +L_0x1e623d0 .delay (20000,20000,20000) L_0x1e623d0/d; +L_0x1e624c0/d .functor AND 1, L_0x1e62040, L_0x1e62740, C4<1>, C4<1>; +L_0x1e624c0 .delay (20000,20000,20000) L_0x1e624c0/d; +L_0x1e625b0/d .functor OR 1, L_0x1e623d0, L_0x1e624c0, C4<0>, C4<0>; +L_0x1e625b0 .delay (20000,20000,20000) L_0x1e625b0/d; +v0x1e35370_0 .net "S", 0 0, L_0x1e62740; 1 drivers +v0x1e353f0_0 .alias "in0", 0 0, v0x1e35a80_0; +v0x1e35490_0 .alias "in1", 0 0, v0x1e36020_0; +v0x1e35530_0 .net "nS", 0 0, L_0x1e62370; 1 drivers +v0x1e355e0_0 .net "out0", 0 0, L_0x1e623d0; 1 drivers +v0x1e35680_0 .net "out1", 0 0, L_0x1e624c0; 1 drivers +v0x1e35760_0 .alias "outfinal", 0 0, v0x1e35b30_0; +S_0x1e31c70 .scope module, "trial1" "AndNand32" 3 280, 3 154, S_0x1da9070; + .timescale -9 -12; +P_0x1e316f8 .param/l "size" 3 161, +C4<0100>; +v0x1e31b60_0 .alias "A", 3 0, v0x1e47f20_0; +v0x1e34cd0_0 .alias "AndNandOut", 3 0, v0x1e49180_0; +v0x1e34d50_0 .alias "B", 3 0, v0x1e48040_0; +v0x1e34e00_0 .alias "Command", 2 0, v0x1e48140_0; +L_0x1e663d0 .part/pv L_0x1e66160, 1, 1, 4; +L_0x1e66490 .part v0x1e49000_0, 1, 1; +L_0x1e66530 .part v0x1e49200_0, 1, 1; +L_0x1e66e40 .part/pv L_0x1e66bd0, 2, 1, 4; +L_0x1e66ee0 .part v0x1e49000_0, 2, 1; +L_0x1e66f80 .part v0x1e49200_0, 2, 1; +L_0x1e678b0 .part/pv L_0x1e67640, 3, 1, 4; +L_0x1e59390 .part v0x1e49000_0, 3, 1; +L_0x1e67b60 .part v0x1e49200_0, 3, 1; +L_0x1e68410 .part/pv L_0x1e681a0, 0, 1, 4; +L_0x1e68510 .part v0x1e49000_0, 0, 1; +L_0x1e685b0 .part v0x1e49200_0, 0, 1; +S_0x1e34190 .scope module, "attempt2" "AndNand" 3 165, 3 48, S_0x1e31c70; + .timescale -9 -12; +L_0x1e67c50/d .functor NAND 1, L_0x1e68510, L_0x1e685b0, C4<1>, C4<1>; +L_0x1e67c50 .delay (10000,10000,10000) L_0x1e67c50/d; +L_0x1e67d50/d .functor NOT 1, L_0x1e67c50, C4<0>, C4<0>, C4<0>; +L_0x1e67d50 .delay (10000,10000,10000) L_0x1e67d50/d; +v0x1e347b0_0 .net "A", 0 0, L_0x1e68510; 1 drivers +v0x1e34870_0 .net "AandB", 0 0, L_0x1e67d50; 1 drivers +v0x1e348f0_0 .net "AnandB", 0 0, L_0x1e67c50; 1 drivers +v0x1e349a0_0 .net "AndNandOut", 0 0, L_0x1e681a0; 1 drivers +v0x1e34a80_0 .net "B", 0 0, L_0x1e685b0; 1 drivers +v0x1e34b00_0 .alias "Command", 2 0, v0x1e48140_0; +L_0x1e68370 .part v0x1e49280_0, 0, 1; +S_0x1e34280 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0x1e34190; + .timescale -9 -12; +L_0x1e67e80/d .functor NOT 1, L_0x1e68370, C4<0>, C4<0>, C4<0>; +L_0x1e67e80 .delay (10000,10000,10000) L_0x1e67e80/d; +L_0x1e67f40/d .functor AND 1, L_0x1e67d50, L_0x1e67e80, C4<1>, C4<1>; +L_0x1e67f40 .delay (20000,20000,20000) L_0x1e67f40/d; +L_0x1e68050/d .functor AND 1, L_0x1e67c50, L_0x1e68370, C4<1>, C4<1>; +L_0x1e68050 .delay (20000,20000,20000) L_0x1e68050/d; +L_0x1e681a0/d .functor OR 1, L_0x1e67f40, L_0x1e68050, C4<0>, C4<0>; +L_0x1e681a0 .delay (20000,20000,20000) L_0x1e681a0/d; +v0x1e34370_0 .net "S", 0 0, L_0x1e68370; 1 drivers +v0x1e343f0_0 .alias "in0", 0 0, v0x1e34870_0; +v0x1e34470_0 .alias "in1", 0 0, v0x1e348f0_0; +v0x1e34510_0 .net "nS", 0 0, L_0x1e67e80; 1 drivers +v0x1e34590_0 .net "out0", 0 0, L_0x1e67f40; 1 drivers +v0x1e34630_0 .net "out1", 0 0, L_0x1e68050; 1 drivers +v0x1e34710_0 .alias "outfinal", 0 0, v0x1e349a0_0; +S_0x1e335d0 .scope generate, "andbits[1]" "andbits[1]" 3 169, 3 169, S_0x1e31c70; + .timescale -9 -12; +P_0x1e336c8 .param/l "i" 3 169, +C4<01>; +S_0x1e33740 .scope module, "attempt" "AndNand" 3 171, 3 48, S_0x1e335d0; + .timescale -9 -12; +L_0x1e65c50/d .functor NAND 1, L_0x1e66490, L_0x1e66530, C4<1>, C4<1>; +L_0x1e65c50 .delay (10000,10000,10000) L_0x1e65c50/d; +L_0x1e65d10/d .functor NOT 1, L_0x1e65c50, C4<0>, C4<0>, C4<0>; +L_0x1e65d10 .delay (10000,10000,10000) L_0x1e65d10/d; +v0x1e33d80_0 .net "A", 0 0, L_0x1e66490; 1 drivers +v0x1e33e40_0 .net "AandB", 0 0, L_0x1e65d10; 1 drivers +v0x1e33ec0_0 .net "AnandB", 0 0, L_0x1e65c50; 1 drivers +v0x1e33f70_0 .net "AndNandOut", 0 0, L_0x1e66160; 1 drivers +v0x1e34050_0 .net "B", 0 0, L_0x1e66530; 1 drivers +v0x1e340d0_0 .alias "Command", 2 0, v0x1e48140_0; +L_0x1e66330 .part v0x1e49280_0, 0, 1; +S_0x1e33830 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0x1e33740; + .timescale -9 -12; +L_0x1e65e40/d .functor NOT 1, L_0x1e66330, C4<0>, C4<0>, C4<0>; +L_0x1e65e40 .delay (10000,10000,10000) L_0x1e65e40/d; +L_0x1e65f00/d .functor AND 1, L_0x1e65d10, L_0x1e65e40, C4<1>, C4<1>; +L_0x1e65f00 .delay (20000,20000,20000) L_0x1e65f00/d; +L_0x1e66010/d .functor AND 1, L_0x1e65c50, L_0x1e66330, C4<1>, C4<1>; +L_0x1e66010 .delay (20000,20000,20000) L_0x1e66010/d; +L_0x1e66160/d .functor OR 1, L_0x1e65f00, L_0x1e66010, C4<0>, C4<0>; +L_0x1e66160 .delay (20000,20000,20000) L_0x1e66160/d; +v0x1e33920_0 .net "S", 0 0, L_0x1e66330; 1 drivers +v0x1e339a0_0 .alias "in0", 0 0, v0x1e33e40_0; +v0x1e33a40_0 .alias "in1", 0 0, v0x1e33ec0_0; +v0x1e33ae0_0 .net "nS", 0 0, L_0x1e65e40; 1 drivers +v0x1e33b60_0 .net "out0", 0 0, L_0x1e65f00; 1 drivers +v0x1e33c00_0 .net "out1", 0 0, L_0x1e66010; 1 drivers +v0x1e33ce0_0 .alias "outfinal", 0 0, v0x1e33f70_0; +S_0x1e32a10 .scope generate, "andbits[2]" "andbits[2]" 3 169, 3 169, S_0x1e31c70; + .timescale -9 -12; +P_0x1e32b08 .param/l "i" 3 169, +C4<010>; +S_0x1e32b80 .scope module, "attempt" "AndNand" 3 171, 3 48, S_0x1e32a10; + .timescale -9 -12; +L_0x1e66620/d .functor NAND 1, L_0x1e66ee0, L_0x1e66f80, C4<1>, C4<1>; +L_0x1e66620 .delay (10000,10000,10000) L_0x1e66620/d; +L_0x1e66780/d .functor NOT 1, L_0x1e66620, C4<0>, C4<0>, C4<0>; +L_0x1e66780 .delay (10000,10000,10000) L_0x1e66780/d; +v0x1e331c0_0 .net "A", 0 0, L_0x1e66ee0; 1 drivers +v0x1e33280_0 .net "AandB", 0 0, L_0x1e66780; 1 drivers +v0x1e33300_0 .net "AnandB", 0 0, L_0x1e66620; 1 drivers +v0x1e333b0_0 .net "AndNandOut", 0 0, L_0x1e66bd0; 1 drivers +v0x1e33490_0 .net "B", 0 0, L_0x1e66f80; 1 drivers +v0x1e33510_0 .alias "Command", 2 0, v0x1e48140_0; +L_0x1e66da0 .part v0x1e49280_0, 0, 1; +S_0x1e32c70 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0x1e32b80; + .timescale -9 -12; +L_0x1e668b0/d .functor NOT 1, L_0x1e66da0, C4<0>, C4<0>, C4<0>; +L_0x1e668b0 .delay (10000,10000,10000) L_0x1e668b0/d; +L_0x1e66970/d .functor AND 1, L_0x1e66780, L_0x1e668b0, C4<1>, C4<1>; +L_0x1e66970 .delay (20000,20000,20000) L_0x1e66970/d; +L_0x1e66a80/d .functor AND 1, L_0x1e66620, L_0x1e66da0, C4<1>, C4<1>; +L_0x1e66a80 .delay (20000,20000,20000) L_0x1e66a80/d; +L_0x1e66bd0/d .functor OR 1, L_0x1e66970, L_0x1e66a80, C4<0>, C4<0>; +L_0x1e66bd0 .delay (20000,20000,20000) L_0x1e66bd0/d; +v0x1e32d60_0 .net "S", 0 0, L_0x1e66da0; 1 drivers +v0x1e32de0_0 .alias "in0", 0 0, v0x1e33280_0; +v0x1e32e80_0 .alias "in1", 0 0, v0x1e33300_0; +v0x1e32f20_0 .net "nS", 0 0, L_0x1e668b0; 1 drivers +v0x1e32fa0_0 .net "out0", 0 0, L_0x1e66970; 1 drivers +v0x1e33040_0 .net "out1", 0 0, L_0x1e66a80; 1 drivers +v0x1e33120_0 .alias "outfinal", 0 0, v0x1e333b0_0; +S_0x1e31de0 .scope generate, "andbits[3]" "andbits[3]" 3 169, 3 169, S_0x1e31c70; + .timescale -9 -12; +P_0x1e31ed8 .param/l "i" 3 169, +C4<011>; +S_0x1e31f70 .scope module, "attempt" "AndNand" 3 171, 3 48, S_0x1e31de0; + .timescale -9 -12; +L_0x1e670b0/d .functor NAND 1, L_0x1e59390, L_0x1e67b60, C4<1>, C4<1>; +L_0x1e670b0 .delay (10000,10000,10000) L_0x1e670b0/d; +L_0x1e671f0/d .functor NOT 1, L_0x1e670b0, C4<0>, C4<0>, C4<0>; +L_0x1e671f0 .delay (10000,10000,10000) L_0x1e671f0/d; +v0x1e32600_0 .net "A", 0 0, L_0x1e59390; 1 drivers +v0x1e326c0_0 .net "AandB", 0 0, L_0x1e671f0; 1 drivers +v0x1e32740_0 .net "AnandB", 0 0, L_0x1e670b0; 1 drivers +v0x1e327f0_0 .net "AndNandOut", 0 0, L_0x1e67640; 1 drivers +v0x1e328d0_0 .net "B", 0 0, L_0x1e67b60; 1 drivers +v0x1e32950_0 .alias "Command", 2 0, v0x1e48140_0; +L_0x1e67810 .part v0x1e49280_0, 0, 1; +S_0x1e32060 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0x1e31f70; + .timescale -9 -12; +L_0x1e67320/d .functor NOT 1, L_0x1e67810, C4<0>, C4<0>, C4<0>; +L_0x1e67320 .delay (10000,10000,10000) L_0x1e67320/d; +L_0x1e673e0/d .functor AND 1, L_0x1e671f0, L_0x1e67320, C4<1>, C4<1>; +L_0x1e673e0 .delay (20000,20000,20000) L_0x1e673e0/d; +L_0x1e674f0/d .functor AND 1, L_0x1e670b0, L_0x1e67810, C4<1>, C4<1>; +L_0x1e674f0 .delay (20000,20000,20000) L_0x1e674f0/d; +L_0x1e67640/d .functor OR 1, L_0x1e673e0, L_0x1e674f0, C4<0>, C4<0>; +L_0x1e67640 .delay (20000,20000,20000) L_0x1e67640/d; +v0x1e32150_0 .net "S", 0 0, L_0x1e67810; 1 drivers +v0x1e321f0_0 .alias "in0", 0 0, v0x1e326c0_0; +v0x1e32290_0 .alias "in1", 0 0, v0x1e32740_0; +v0x1e32330_0 .net "nS", 0 0, L_0x1e67320; 1 drivers +v0x1e323e0_0 .net "out0", 0 0, L_0x1e673e0; 1 drivers +v0x1e32480_0 .net "out1", 0 0, L_0x1e674f0; 1 drivers +v0x1e32560_0 .alias "outfinal", 0 0, v0x1e327f0_0; +S_0x1e2ca50 .scope module, "trial2" "OrNorXor32" 3 281, 3 177, S_0x1da9070; + .timescale -9 -12; +P_0x1e2bba8 .param/l "size" 3 184, +C4<0100>; +v0x1e319e0_0 .alias "A", 3 0, v0x1e47f20_0; +v0x1e31a60_0 .alias "B", 3 0, v0x1e48040_0; +v0x1e31ae0_0 .alias "Command", 2 0, v0x1e48140_0; +v0x1e31bf0_0 .alias "OrNorXorOut", 3 0, v0x1e49380_0; +L_0x1e69760 .part/pv L_0x1e694f0, 1, 1, 4; +L_0x1e69800 .part v0x1e49000_0, 1, 1; +L_0x1e698a0 .part v0x1e49200_0, 1, 1; +L_0x1e6aa60 .part/pv L_0x1e6a7f0, 2, 1, 4; +L_0x1e6ab00 .part v0x1e49000_0, 2, 1; +L_0x1e6aba0 .part v0x1e49200_0, 2, 1; +L_0x1e6bd60 .part/pv L_0x1e6baf0, 3, 1, 4; +L_0x1e6be00 .part v0x1e49000_0, 3, 1; +L_0x1e6bea0 .part v0x1e49200_0, 3, 1; +L_0x1e6d050 .part/pv L_0x1e6cde0, 0, 1, 4; +L_0x1e6d150 .part v0x1e49000_0, 0, 1; +L_0x1e6d1f0 .part v0x1e49200_0, 0, 1; +S_0x1e307d0 .scope module, "attempt2" "OrNorXor" 3 192, 3 64, S_0x1e2ca50; + .timescale -9 -12; +L_0x1e6bf40/d .functor NOR 1, L_0x1e6d150, L_0x1e6d1f0, C4<0>, C4<0>; +L_0x1e6bf40 .delay (10000,10000,10000) L_0x1e6bf40/d; +L_0x1e6c040/d .functor NOT 1, L_0x1e6bf40, C4<0>, C4<0>, C4<0>; +L_0x1e6c040 .delay (10000,10000,10000) L_0x1e6c040/d; +L_0x1e6c170/d .functor NAND 1, L_0x1e6d150, L_0x1e6d1f0, C4<1>, C4<1>; +L_0x1e6c170 .delay (10000,10000,10000) L_0x1e6c170/d; +L_0x1e6c2d0/d .functor NAND 1, L_0x1e6c170, L_0x1e6c040, C4<1>, C4<1>; +L_0x1e6c2d0 .delay (10000,10000,10000) L_0x1e6c2d0/d; +L_0x1e6c3e0/d .functor NOT 1, L_0x1e6c2d0, C4<0>, C4<0>, C4<0>; +L_0x1e6c3e0 .delay (10000,10000,10000) L_0x1e6c3e0/d; +v0x1e31320_0 .net "A", 0 0, L_0x1e6d150; 1 drivers +v0x1e313c0_0 .net "AnandB", 0 0, L_0x1e6c170; 1 drivers +v0x1e31460_0 .net "AnorB", 0 0, L_0x1e6bf40; 1 drivers +v0x1e314e0_0 .net "AorB", 0 0, L_0x1e6c040; 1 drivers +v0x1e315c0_0 .net "AxorB", 0 0, L_0x1e6c3e0; 1 drivers +v0x1e31670_0 .net "B", 0 0, L_0x1e6d1f0; 1 drivers +v0x1e31730_0 .alias "Command", 2 0, v0x1e48140_0; +v0x1e317b0_0 .net "OrNorXorOut", 0 0, L_0x1e6cde0; 1 drivers +v0x1e31830_0 .net "XorNor", 0 0, L_0x1e6c860; 1 drivers +v0x1e31900_0 .net "nXor", 0 0, L_0x1e6c2d0; 1 drivers +L_0x1e6c9e0 .part v0x1e49280_0, 2, 1; +L_0x1e6cfb0 .part v0x1e49280_0, 0, 1; +S_0x1e30db0 .scope module, "mux0" "TwoInMux" 3 83, 3 8, S_0x1e307d0; + .timescale -9 -12; +L_0x1e6c540/d .functor NOT 1, L_0x1e6c9e0, C4<0>, C4<0>, C4<0>; +L_0x1e6c540 .delay (10000,10000,10000) L_0x1e6c540/d; +L_0x1e6c600/d .functor AND 1, L_0x1e6c3e0, L_0x1e6c540, C4<1>, C4<1>; +L_0x1e6c600 .delay (20000,20000,20000) L_0x1e6c600/d; +L_0x1e6c710/d .functor AND 1, L_0x1e6bf40, L_0x1e6c9e0, C4<1>, C4<1>; +L_0x1e6c710 .delay (20000,20000,20000) L_0x1e6c710/d; +L_0x1e6c860/d .functor OR 1, L_0x1e6c600, L_0x1e6c710, C4<0>, C4<0>; +L_0x1e6c860 .delay (20000,20000,20000) L_0x1e6c860/d; +v0x1e30ea0_0 .net "S", 0 0, L_0x1e6c9e0; 1 drivers +v0x1e30f60_0 .alias "in0", 0 0, v0x1e315c0_0; +v0x1e31000_0 .alias "in1", 0 0, v0x1e31460_0; +v0x1e310a0_0 .net "nS", 0 0, L_0x1e6c540; 1 drivers +v0x1e31120_0 .net "out0", 0 0, L_0x1e6c600; 1 drivers +v0x1e311c0_0 .net "out1", 0 0, L_0x1e6c710; 1 drivers +v0x1e312a0_0 .alias "outfinal", 0 0, v0x1e31830_0; +S_0x1e308c0 .scope module, "mux1" "TwoInMux" 3 84, 3 8, S_0x1e307d0; + .timescale -9 -12; +L_0x1e6ca80/d .functor NOT 1, L_0x1e6cfb0, C4<0>, C4<0>, C4<0>; +L_0x1e6ca80 .delay (10000,10000,10000) L_0x1e6ca80/d; +L_0x1e6cb40/d .functor AND 1, L_0x1e6c860, L_0x1e6ca80, C4<1>, C4<1>; +L_0x1e6cb40 .delay (20000,20000,20000) L_0x1e6cb40/d; +L_0x1e6cc90/d .functor AND 1, L_0x1e6c040, L_0x1e6cfb0, C4<1>, C4<1>; +L_0x1e6cc90 .delay (20000,20000,20000) L_0x1e6cc90/d; +L_0x1e6cde0/d .functor OR 1, L_0x1e6cb40, L_0x1e6cc90, C4<0>, C4<0>; +L_0x1e6cde0 .delay (20000,20000,20000) L_0x1e6cde0/d; +v0x1e309b0_0 .net "S", 0 0, L_0x1e6cfb0; 1 drivers +v0x1e30a30_0 .alias "in0", 0 0, v0x1e31830_0; +v0x1e30ab0_0 .alias "in1", 0 0, v0x1e314e0_0; +v0x1e30b50_0 .net "nS", 0 0, L_0x1e6ca80; 1 drivers +v0x1e30bd0_0 .net "out0", 0 0, L_0x1e6cb40; 1 drivers +v0x1e30c70_0 .net "out1", 0 0, L_0x1e6cc90; 1 drivers +v0x1e30d10_0 .alias "outfinal", 0 0, v0x1e317b0_0; +S_0x1e2f3d0 .scope generate, "orbits[1]" "orbits[1]" 3 196, 3 196, S_0x1e2ca50; + .timescale -9 -12; +P_0x1e2f0b8 .param/l "i" 3 196, +C4<01>; +S_0x1e2f500 .scope module, "attempt" "OrNorXor" 3 198, 3 64, S_0x1e2f3d0; + .timescale -9 -12; +L_0x1e684b0/d .functor NOR 1, L_0x1e69800, L_0x1e698a0, C4<0>, C4<0>; +L_0x1e684b0 .delay (10000,10000,10000) L_0x1e684b0/d; +L_0x1e68750/d .functor NOT 1, L_0x1e684b0, C4<0>, C4<0>, C4<0>; +L_0x1e68750 .delay (10000,10000,10000) L_0x1e68750/d; +L_0x1e68880/d .functor NAND 1, L_0x1e69800, L_0x1e698a0, C4<1>, C4<1>; +L_0x1e68880 .delay (10000,10000,10000) L_0x1e68880/d; +L_0x1e689e0/d .functor NAND 1, L_0x1e68880, L_0x1e68750, C4<1>, C4<1>; +L_0x1e689e0 .delay (10000,10000,10000) L_0x1e689e0/d; +L_0x1e68af0/d .functor NOT 1, L_0x1e689e0, C4<0>, C4<0>, C4<0>; +L_0x1e68af0 .delay (10000,10000,10000) L_0x1e68af0/d; +v0x1e30090_0 .net "A", 0 0, L_0x1e69800; 1 drivers +v0x1e30130_0 .net "AnandB", 0 0, L_0x1e68880; 1 drivers +v0x1e301d0_0 .net "AnorB", 0 0, L_0x1e684b0; 1 drivers +v0x1e30280_0 .net "AorB", 0 0, L_0x1e68750; 1 drivers +v0x1e30360_0 .net "AxorB", 0 0, L_0x1e68af0; 1 drivers +v0x1e30410_0 .net "B", 0 0, L_0x1e698a0; 1 drivers +v0x1e304d0_0 .alias "Command", 2 0, v0x1e48140_0; +v0x1e30550_0 .net "OrNorXorOut", 0 0, L_0x1e694f0; 1 drivers +v0x1e30620_0 .net "XorNor", 0 0, L_0x1e68f70; 1 drivers +v0x1e306f0_0 .net "nXor", 0 0, L_0x1e689e0; 1 drivers +L_0x1e690f0 .part v0x1e49280_0, 2, 1; +L_0x1e696c0 .part v0x1e49280_0, 0, 1; +S_0x1e2fb20 .scope module, "mux0" "TwoInMux" 3 83, 3 8, S_0x1e2f500; + .timescale -9 -12; +L_0x1e68c50/d .functor NOT 1, L_0x1e690f0, C4<0>, C4<0>, C4<0>; +L_0x1e68c50 .delay (10000,10000,10000) L_0x1e68c50/d; +L_0x1e68d10/d .functor AND 1, L_0x1e68af0, L_0x1e68c50, C4<1>, C4<1>; +L_0x1e68d10 .delay (20000,20000,20000) L_0x1e68d10/d; +L_0x1e68e20/d .functor AND 1, L_0x1e684b0, L_0x1e690f0, C4<1>, C4<1>; +L_0x1e68e20 .delay (20000,20000,20000) L_0x1e68e20/d; +L_0x1e68f70/d .functor OR 1, L_0x1e68d10, L_0x1e68e20, C4<0>, C4<0>; +L_0x1e68f70 .delay (20000,20000,20000) L_0x1e68f70/d; +v0x1e2fc10_0 .net "S", 0 0, L_0x1e690f0; 1 drivers +v0x1e2fcd0_0 .alias "in0", 0 0, v0x1e30360_0; +v0x1e2fd70_0 .alias "in1", 0 0, v0x1e301d0_0; +v0x1e2fe10_0 .net "nS", 0 0, L_0x1e68c50; 1 drivers +v0x1e2fe90_0 .net "out0", 0 0, L_0x1e68d10; 1 drivers +v0x1e2ff30_0 .net "out1", 0 0, L_0x1e68e20; 1 drivers +v0x1e30010_0 .alias "outfinal", 0 0, v0x1e30620_0; +S_0x1e2f5f0 .scope module, "mux1" "TwoInMux" 3 84, 3 8, S_0x1e2f500; + .timescale -9 -12; +L_0x1e69190/d .functor NOT 1, L_0x1e696c0, C4<0>, C4<0>, C4<0>; +L_0x1e69190 .delay (10000,10000,10000) L_0x1e69190/d; +L_0x1e69250/d .functor AND 1, L_0x1e68f70, L_0x1e69190, C4<1>, C4<1>; +L_0x1e69250 .delay (20000,20000,20000) L_0x1e69250/d; +L_0x1e693a0/d .functor AND 1, L_0x1e68750, L_0x1e696c0, C4<1>, C4<1>; +L_0x1e693a0 .delay (20000,20000,20000) L_0x1e693a0/d; +L_0x1e694f0/d .functor OR 1, L_0x1e69250, L_0x1e693a0, C4<0>, C4<0>; +L_0x1e694f0 .delay (20000,20000,20000) L_0x1e694f0/d; +v0x1e2f6e0_0 .net "S", 0 0, L_0x1e696c0; 1 drivers +v0x1e2f760_0 .alias "in0", 0 0, v0x1e30620_0; +v0x1e2f7e0_0 .alias "in1", 0 0, v0x1e30280_0; +v0x1e2f880_0 .net "nS", 0 0, L_0x1e69190; 1 drivers +v0x1e2f900_0 .net "out0", 0 0, L_0x1e69250; 1 drivers +v0x1e2f9a0_0 .net "out1", 0 0, L_0x1e693a0; 1 drivers +v0x1e2fa80_0 .alias "outfinal", 0 0, v0x1e30550_0; +S_0x1e2dfb0 .scope generate, "orbits[2]" "orbits[2]" 3 196, 3 196, S_0x1e2ca50; + .timescale -9 -12; +P_0x1e2dd28 .param/l "i" 3 196, +C4<010>; +S_0x1e2e0e0 .scope module, "attempt" "OrNorXor" 3 198, 3 64, S_0x1e2dfb0; + .timescale -9 -12; +L_0x1e69940/d .functor NOR 1, L_0x1e6ab00, L_0x1e6aba0, C4<0>, C4<0>; +L_0x1e69940 .delay (10000,10000,10000) L_0x1e69940/d; +L_0x1e69a50/d .functor NOT 1, L_0x1e69940, C4<0>, C4<0>, C4<0>; +L_0x1e69a50 .delay (10000,10000,10000) L_0x1e69a50/d; +L_0x1e69b80/d .functor NAND 1, L_0x1e6ab00, L_0x1e6aba0, C4<1>, C4<1>; +L_0x1e69b80 .delay (10000,10000,10000) L_0x1e69b80/d; +L_0x1e69ce0/d .functor NAND 1, L_0x1e69b80, L_0x1e69a50, C4<1>, C4<1>; +L_0x1e69ce0 .delay (10000,10000,10000) L_0x1e69ce0/d; +L_0x1e69df0/d .functor NOT 1, L_0x1e69ce0, C4<0>, C4<0>, C4<0>; +L_0x1e69df0 .delay (10000,10000,10000) L_0x1e69df0/d; +v0x1e2ecb0_0 .net "A", 0 0, L_0x1e6ab00; 1 drivers +v0x1e2ed50_0 .net "AnandB", 0 0, L_0x1e69b80; 1 drivers +v0x1e2edf0_0 .net "AnorB", 0 0, L_0x1e69940; 1 drivers +v0x1e2eea0_0 .net "AorB", 0 0, L_0x1e69a50; 1 drivers +v0x1e2ef80_0 .net "AxorB", 0 0, L_0x1e69df0; 1 drivers +v0x1e2f030_0 .net "B", 0 0, L_0x1e6aba0; 1 drivers +v0x1e2f0f0_0 .alias "Command", 2 0, v0x1e48140_0; +v0x1e2f170_0 .net "OrNorXorOut", 0 0, L_0x1e6a7f0; 1 drivers +v0x1e2f220_0 .net "XorNor", 0 0, L_0x1e6a270; 1 drivers +v0x1e2f2f0_0 .net "nXor", 0 0, L_0x1e69ce0; 1 drivers +L_0x1e6a3f0 .part v0x1e49280_0, 2, 1; +L_0x1e6a9c0 .part v0x1e49280_0, 0, 1; +S_0x1e2e740 .scope module, "mux0" "TwoInMux" 3 83, 3 8, S_0x1e2e0e0; + .timescale -9 -12; +L_0x1e69f50/d .functor NOT 1, L_0x1e6a3f0, C4<0>, C4<0>, C4<0>; +L_0x1e69f50 .delay (10000,10000,10000) L_0x1e69f50/d; +L_0x1e6a010/d .functor AND 1, L_0x1e69df0, L_0x1e69f50, C4<1>, C4<1>; +L_0x1e6a010 .delay (20000,20000,20000) L_0x1e6a010/d; +L_0x1e6a120/d .functor AND 1, L_0x1e69940, L_0x1e6a3f0, C4<1>, C4<1>; +L_0x1e6a120 .delay (20000,20000,20000) L_0x1e6a120/d; +L_0x1e6a270/d .functor OR 1, L_0x1e6a010, L_0x1e6a120, C4<0>, C4<0>; +L_0x1e6a270 .delay (20000,20000,20000) L_0x1e6a270/d; +v0x1e2e830_0 .net "S", 0 0, L_0x1e6a3f0; 1 drivers +v0x1e2e8f0_0 .alias "in0", 0 0, v0x1e2ef80_0; +v0x1e2e990_0 .alias "in1", 0 0, v0x1e2edf0_0; +v0x1e2ea30_0 .net "nS", 0 0, L_0x1e69f50; 1 drivers +v0x1e2eab0_0 .net "out0", 0 0, L_0x1e6a010; 1 drivers +v0x1e2eb50_0 .net "out1", 0 0, L_0x1e6a120; 1 drivers +v0x1e2ec30_0 .alias "outfinal", 0 0, v0x1e2f220_0; +S_0x1e2e1d0 .scope module, "mux1" "TwoInMux" 3 84, 3 8, S_0x1e2e0e0; + .timescale -9 -12; +L_0x1e6a490/d .functor NOT 1, L_0x1e6a9c0, C4<0>, C4<0>, C4<0>; +L_0x1e6a490 .delay (10000,10000,10000) L_0x1e6a490/d; +L_0x1e6a550/d .functor AND 1, L_0x1e6a270, L_0x1e6a490, C4<1>, C4<1>; +L_0x1e6a550 .delay (20000,20000,20000) L_0x1e6a550/d; +L_0x1e6a6a0/d .functor AND 1, L_0x1e69a50, L_0x1e6a9c0, C4<1>, C4<1>; +L_0x1e6a6a0 .delay (20000,20000,20000) L_0x1e6a6a0/d; +L_0x1e6a7f0/d .functor OR 1, L_0x1e6a550, L_0x1e6a6a0, C4<0>, C4<0>; +L_0x1e6a7f0 .delay (20000,20000,20000) L_0x1e6a7f0/d; +v0x1e2e2c0_0 .net "S", 0 0, L_0x1e6a9c0; 1 drivers +v0x1e2e360_0 .alias "in0", 0 0, v0x1e2f220_0; +v0x1e2e400_0 .alias "in1", 0 0, v0x1e2eea0_0; +v0x1e2e4a0_0 .net "nS", 0 0, L_0x1e6a490; 1 drivers +v0x1e2e520_0 .net "out0", 0 0, L_0x1e6a550; 1 drivers +v0x1e2e5c0_0 .net "out1", 0 0, L_0x1e6a6a0; 1 drivers +v0x1e2e6a0_0 .alias "outfinal", 0 0, v0x1e2f170_0; +S_0x1e2cbc0 .scope generate, "orbits[3]" "orbits[3]" 3 196, 3 196, S_0x1e2ca50; + .timescale -9 -12; +P_0x1e2ccb8 .param/l "i" 3 196, +C4<011>; +S_0x1e2cd50 .scope module, "attempt" "OrNorXor" 3 198, 3 64, S_0x1e2cbc0; + .timescale -9 -12; +L_0x1e6ac80/d .functor NOR 1, L_0x1e6be00, L_0x1e6bea0, C4<0>, C4<0>; +L_0x1e6ac80 .delay (10000,10000,10000) L_0x1e6ac80/d; +L_0x1e6ad70/d .functor NOT 1, L_0x1e6ac80, C4<0>, C4<0>, C4<0>; +L_0x1e6ad70 .delay (10000,10000,10000) L_0x1e6ad70/d; +L_0x1e6ae80/d .functor NAND 1, L_0x1e6be00, L_0x1e6bea0, C4<1>, C4<1>; +L_0x1e6ae80 .delay (10000,10000,10000) L_0x1e6ae80/d; +L_0x1e6afe0/d .functor NAND 1, L_0x1e6ae80, L_0x1e6ad70, C4<1>, C4<1>; +L_0x1e6afe0 .delay (10000,10000,10000) L_0x1e6afe0/d; +L_0x1e6b0f0/d .functor NOT 1, L_0x1e6afe0, C4<0>, C4<0>, C4<0>; +L_0x1e6b0f0 .delay (10000,10000,10000) L_0x1e6b0f0/d; +v0x1e2d920_0 .net "A", 0 0, L_0x1e6be00; 1 drivers +v0x1e2d9c0_0 .net "AnandB", 0 0, L_0x1e6ae80; 1 drivers +v0x1e2da60_0 .net "AnorB", 0 0, L_0x1e6ac80; 1 drivers +v0x1e2db10_0 .net "AorB", 0 0, L_0x1e6ad70; 1 drivers +v0x1e2dbf0_0 .net "AxorB", 0 0, L_0x1e6b0f0; 1 drivers +v0x1e2dca0_0 .net "B", 0 0, L_0x1e6bea0; 1 drivers +v0x1e2dd60_0 .alias "Command", 2 0, v0x1e48140_0; +v0x1e2dde0_0 .net "OrNorXorOut", 0 0, L_0x1e6baf0; 1 drivers +v0x1e2de60_0 .net "XorNor", 0 0, L_0x1e6b570; 1 drivers +v0x1e2df30_0 .net "nXor", 0 0, L_0x1e6afe0; 1 drivers +L_0x1e6b6f0 .part v0x1e49280_0, 2, 1; +L_0x1e6bcc0 .part v0x1e49280_0, 0, 1; +S_0x1e2d3b0 .scope module, "mux0" "TwoInMux" 3 83, 3 8, S_0x1e2cd50; + .timescale -9 -12; +L_0x1e6b250/d .functor NOT 1, L_0x1e6b6f0, C4<0>, C4<0>, C4<0>; +L_0x1e6b250 .delay (10000,10000,10000) L_0x1e6b250/d; +L_0x1e6b310/d .functor AND 1, L_0x1e6b0f0, L_0x1e6b250, C4<1>, C4<1>; +L_0x1e6b310 .delay (20000,20000,20000) L_0x1e6b310/d; +L_0x1e6b420/d .functor AND 1, L_0x1e6ac80, L_0x1e6b6f0, C4<1>, C4<1>; +L_0x1e6b420 .delay (20000,20000,20000) L_0x1e6b420/d; +L_0x1e6b570/d .functor OR 1, L_0x1e6b310, L_0x1e6b420, C4<0>, C4<0>; +L_0x1e6b570 .delay (20000,20000,20000) L_0x1e6b570/d; +v0x1e2d4a0_0 .net "S", 0 0, L_0x1e6b6f0; 1 drivers +v0x1e2d560_0 .alias "in0", 0 0, v0x1e2dbf0_0; +v0x1e2d600_0 .alias "in1", 0 0, v0x1e2da60_0; +v0x1e2d6a0_0 .net "nS", 0 0, L_0x1e6b250; 1 drivers +v0x1e2d720_0 .net "out0", 0 0, L_0x1e6b310; 1 drivers +v0x1e2d7c0_0 .net "out1", 0 0, L_0x1e6b420; 1 drivers +v0x1e2d8a0_0 .alias "outfinal", 0 0, v0x1e2de60_0; +S_0x1e2ce40 .scope module, "mux1" "TwoInMux" 3 84, 3 8, S_0x1e2cd50; + .timescale -9 -12; +L_0x1e6b790/d .functor NOT 1, L_0x1e6bcc0, C4<0>, C4<0>, C4<0>; +L_0x1e6b790 .delay (10000,10000,10000) L_0x1e6b790/d; +L_0x1e6b850/d .functor AND 1, L_0x1e6b570, L_0x1e6b790, C4<1>, C4<1>; +L_0x1e6b850 .delay (20000,20000,20000) L_0x1e6b850/d; +L_0x1e6b9a0/d .functor AND 1, L_0x1e6ad70, L_0x1e6bcc0, C4<1>, C4<1>; +L_0x1e6b9a0 .delay (20000,20000,20000) L_0x1e6b9a0/d; +L_0x1e6baf0/d .functor OR 1, L_0x1e6b850, L_0x1e6b9a0, C4<0>, C4<0>; +L_0x1e6baf0 .delay (20000,20000,20000) L_0x1e6baf0/d; +v0x1e2cf30_0 .net "S", 0 0, L_0x1e6bcc0; 1 drivers +v0x1e2cfd0_0 .alias "in0", 0 0, v0x1e2de60_0; +v0x1e2d070_0 .alias "in1", 0 0, v0x1e2db10_0; +v0x1e2d110_0 .net "nS", 0 0, L_0x1e6b790; 1 drivers +v0x1e2d190_0 .net "out0", 0 0, L_0x1e6b850; 1 drivers +v0x1e2d230_0 .net "out1", 0 0, L_0x1e6b9a0; 1 drivers +v0x1e2d310_0 .alias "outfinal", 0 0, v0x1e2dde0_0; +S_0x1e2c0d0 .scope module, "ZeroMux0case" "FourInMux" 3 283, 3 24, S_0x1da9070; + .timescale -9 -12; +L_0x1e6d0f0/d .functor NOT 1, L_0x1e5f8c0, C4<0>, C4<0>, C4<0>; +L_0x1e6d0f0 .delay (10000,10000,10000) L_0x1e6d0f0/d; +L_0x1e6d340/d .functor NOT 1, L_0x1e5f9f0, C4<0>, C4<0>, C4<0>; +L_0x1e6d340 .delay (10000,10000,10000) L_0x1e6d340/d; +L_0x1e6d400/d .functor NAND 1, L_0x1e6d0f0, L_0x1e6d340, L_0x1e6da30, C4<1>; +L_0x1e6d400 .delay (10000,10000,10000) L_0x1e6d400/d; +L_0x1e6d4f0/d .functor NAND 1, L_0x1e5f8c0, L_0x1e6d340, L_0x1e6dad0, C4<1>; +L_0x1e6d4f0 .delay (10000,10000,10000) L_0x1e6d4f0/d; +L_0x1e6d5e0/d .functor NAND 1, L_0x1e6d0f0, L_0x1e5f9f0, L_0x1e6db70, C4<1>; +L_0x1e6d5e0 .delay (10000,10000,10000) L_0x1e6d5e0/d; +L_0x1e6d6d0/d .functor NAND 1, L_0x1e5f8c0, L_0x1e5f9f0, L_0x1e6df50, C4<1>; +L_0x1e6d6d0 .delay (10000,10000,10000) L_0x1e6d6d0/d; +L_0x1e6d7b0/d .functor NAND 1, L_0x1e6d400, L_0x1e6d4f0, L_0x1e6d5e0, L_0x1e6d6d0; +L_0x1e6d7b0 .delay (10000,10000,10000) L_0x1e6d7b0/d; +v0x1e2c1c0_0 .net "S0", 0 0, L_0x1e5f8c0; 1 drivers +v0x1e2c280_0 .net "S1", 0 0, L_0x1e5f9f0; 1 drivers +v0x1e2c320_0 .net "in0", 0 0, L_0x1e6da30; 1 drivers +v0x1e2c3c0_0 .net "in1", 0 0, L_0x1e6dad0; 1 drivers +v0x1e2c440_0 .net "in2", 0 0, L_0x1e6db70; 1 drivers +v0x1e2c4e0_0 .net "in3", 0 0, L_0x1e6df50; 1 drivers +v0x1e2c580_0 .net "nS0", 0 0, L_0x1e6d0f0; 1 drivers +v0x1e2c620_0 .net "nS1", 0 0, L_0x1e6d340; 1 drivers +v0x1e2c6c0_0 .net "out", 0 0, L_0x1e6d7b0; 1 drivers +v0x1e2c760_0 .net "out0", 0 0, L_0x1e6d400; 1 drivers +v0x1e2c800_0 .net "out1", 0 0, L_0x1e6d4f0; 1 drivers +v0x1e2c8a0_0 .net "out2", 0 0, L_0x1e6d5e0; 1 drivers +v0x1e2c9b0_0 .net "out3", 0 0, L_0x1e6d6d0; 1 drivers +S_0x1e2b710 .scope module, "OneMux0case" "FourInMux" 3 284, 3 24, S_0x1da9070; + .timescale -9 -12; +L_0x1e6dcd0/d .functor NOT 1, L_0x1e6e860, C4<0>, C4<0>, C4<0>; +L_0x1e6dcd0 .delay (10000,10000,10000) L_0x1e6dcd0/d; +L_0x1e6ddc0/d .functor NOT 1, L_0x1e6e040, C4<0>, C4<0>, C4<0>; +L_0x1e6ddc0 .delay (10000,10000,10000) L_0x1e6ddc0/d; +L_0x1e6de60/d .functor NAND 1, L_0x1e6dcd0, L_0x1e6ddc0, L_0x1e6e170, C4<1>; +L_0x1e6de60 .delay (10000,10000,10000) L_0x1e6de60/d; +L_0x1e6e320/d .functor NAND 1, L_0x1e6e860, L_0x1e6ddc0, L_0x1e6ebf0, C4<1>; +L_0x1e6e320 .delay (10000,10000,10000) L_0x1e6e320/d; +L_0x1e6e410/d .functor NAND 1, L_0x1e6dcd0, L_0x1e6e040, L_0x1e6ec90, C4<1>; +L_0x1e6e410 .delay (10000,10000,10000) L_0x1e6e410/d; +L_0x1e6e500/d .functor NAND 1, L_0x1e6e860, L_0x1e6e040, L_0x1e6e990, C4<1>; +L_0x1e6e500 .delay (10000,10000,10000) L_0x1e6e500/d; +L_0x1e6e5e0/d .functor NAND 1, L_0x1e6de60, L_0x1e6e320, L_0x1e6e410, L_0x1e6e500; +L_0x1e6e5e0 .delay (10000,10000,10000) L_0x1e6e5e0/d; +v0x1e2b800_0 .net "S0", 0 0, L_0x1e6e860; 1 drivers +v0x1e2b8c0_0 .net "S1", 0 0, L_0x1e6e040; 1 drivers +v0x1e2b960_0 .net "in0", 0 0, L_0x1e6e170; 1 drivers +v0x1e2ba00_0 .net "in1", 0 0, L_0x1e6ebf0; 1 drivers +v0x1e2ba80_0 .net "in2", 0 0, L_0x1e6ec90; 1 drivers +v0x1e2bb20_0 .net "in3", 0 0, L_0x1e6e990; 1 drivers +v0x1e2bc00_0 .net "nS0", 0 0, L_0x1e6dcd0; 1 drivers +v0x1e2bca0_0 .net "nS1", 0 0, L_0x1e6ddc0; 1 drivers +v0x1e2bd40_0 .net "out", 0 0, L_0x1e6e5e0; 1 drivers +v0x1e2bde0_0 .net "out0", 0 0, L_0x1e6de60; 1 drivers +v0x1e2be80_0 .net "out1", 0 0, L_0x1e6e320; 1 drivers +v0x1e2bf20_0 .net "out2", 0 0, L_0x1e6e410; 1 drivers +v0x1e2c030_0 .net "out3", 0 0, L_0x1e6e500; 1 drivers +S_0x1e2b1c0 .scope module, "TwoMux0case" "TwoInMux" 3 285, 3 8, S_0x1da9070; + .timescale -9 -12; +L_0x1e6ea80/d .functor NOT 1, L_0x1e6ed30, C4<0>, C4<0>, C4<0>; +L_0x1e6ea80 .delay (10000,10000,10000) L_0x1e6ea80/d; +L_0x1e6eb70/d .functor AND 1, L_0x1e6edd0, L_0x1e6ea80, C4<1>, C4<1>; +L_0x1e6eb70 .delay (20000,20000,20000) L_0x1e6eb70/d; +L_0x1e6f030/d .functor AND 1, L_0x1e6eec0, L_0x1e6ed30, C4<1>, C4<1>; +L_0x1e6f030 .delay (20000,20000,20000) L_0x1e6f030/d; +L_0x1e6f120/d .functor OR 1, L_0x1e6eb70, L_0x1e6f030, C4<0>, C4<0>; +L_0x1e6f120 .delay (20000,20000,20000) L_0x1e6f120/d; +v0x1e2b2b0_0 .net "S", 0 0, L_0x1e6ed30; 1 drivers +v0x1e2b370_0 .net "in0", 0 0, L_0x1e6edd0; 1 drivers +v0x1e2b410_0 .net "in1", 0 0, L_0x1e6eec0; 1 drivers +v0x1e2b4b0_0 .net "nS", 0 0, L_0x1e6ea80; 1 drivers +v0x1e2b530_0 .net "out0", 0 0, L_0x1e6eb70; 1 drivers +v0x1e2b5d0_0 .net "out1", 0 0, L_0x1e6f030; 1 drivers +v0x1e2b670_0 .net "outfinal", 0 0, L_0x1e6f120; 1 drivers +S_0x1e29640 .scope generate, "muxbits[1]" "muxbits[1]" 3 290, 3 290, S_0x1da9070; + .timescale -9 -12; +P_0x1e28638 .param/l "i" 3 290, +C4<01>; +L_0x1e59f90/d .functor OR 1, L_0x1e5a090, L_0x1e59e50, C4<0>, C4<0>; +L_0x1e59f90 .delay (20000,20000,20000) L_0x1e59f90/d; +v0x1e2b060_0 .net *"_s15", 0 0, L_0x1e5a090; 1 drivers +v0x1e2b120_0 .net *"_s16", 0 0, L_0x1e59e50; 1 drivers +S_0x1e2a6e0 .scope module, "ZeroMux" "FourInMux" 3 292, 3 24, S_0x1e29640; + .timescale -9 -12; +L_0x1e57850/d .functor NOT 1, L_0x1e58190, C4<0>, C4<0>, C4<0>; +L_0x1e57850 .delay (10000,10000,10000) L_0x1e57850/d; +L_0x1e57aa0/d .functor NOT 1, L_0x1e582c0, C4<0>, C4<0>, C4<0>; +L_0x1e57aa0 .delay (10000,10000,10000) L_0x1e57aa0/d; +L_0x1e57b60/d .functor NAND 1, L_0x1e57850, L_0x1e57aa0, L_0x1e583f0, C4<1>; +L_0x1e57b60 .delay (10000,10000,10000) L_0x1e57b60/d; +L_0x1e57c50/d .functor NAND 1, L_0x1e58190, L_0x1e57aa0, L_0x1e58490, C4<1>; +L_0x1e57c50 .delay (10000,10000,10000) L_0x1e57c50/d; +L_0x1e57d40/d .functor NAND 1, L_0x1e57850, L_0x1e582c0, L_0x1e58530, C4<1>; +L_0x1e57d40 .delay (10000,10000,10000) L_0x1e57d40/d; +L_0x1e57e30/d .functor NAND 1, L_0x1e58190, L_0x1e582c0, L_0x1e58730, C4<1>; +L_0x1e57e30 .delay (10000,10000,10000) L_0x1e57e30/d; +L_0x1e57f10/d .functor NAND 1, L_0x1e57b60, L_0x1e57c50, L_0x1e57d40, L_0x1e57e30; +L_0x1e57f10 .delay (10000,10000,10000) L_0x1e57f10/d; +v0x1e2a7d0_0 .net "S0", 0 0, L_0x1e58190; 1 drivers +v0x1e2a890_0 .net "S1", 0 0, L_0x1e582c0; 1 drivers +v0x1e2a930_0 .net "in0", 0 0, L_0x1e583f0; 1 drivers +v0x1e2a9d0_0 .net "in1", 0 0, L_0x1e58490; 1 drivers +v0x1e2aa50_0 .net "in2", 0 0, L_0x1e58530; 1 drivers +v0x1e2aaf0_0 .net "in3", 0 0, L_0x1e58730; 1 drivers +v0x1e2ab90_0 .net "nS0", 0 0, L_0x1e57850; 1 drivers +v0x1e2ac30_0 .net "nS1", 0 0, L_0x1e57aa0; 1 drivers +v0x1e2acd0_0 .net "out", 0 0, L_0x1e57f10; 1 drivers +v0x1e2ad70_0 .net "out0", 0 0, L_0x1e57b60; 1 drivers +v0x1e2ae10_0 .net "out1", 0 0, L_0x1e57c50; 1 drivers +v0x1e2aeb0_0 .net "out2", 0 0, L_0x1e57d40; 1 drivers +v0x1e2afc0_0 .net "out3", 0 0, L_0x1e57e30; 1 drivers +S_0x1e29d20 .scope module, "OneMux" "FourInMux" 3 293, 3 24, S_0x1e29640; + .timescale -9 -12; +L_0x1e587d0/d .functor NOT 1, L_0x1e59030, C4<0>, C4<0>, C4<0>; +L_0x1e587d0 .delay (10000,10000,10000) L_0x1e587d0/d; +L_0x1e588c0/d .functor NOT 1, L_0x1e59160, C4<0>, C4<0>, C4<0>; +L_0x1e588c0 .delay (10000,10000,10000) L_0x1e588c0/d; +L_0x1e58960/d .functor NAND 1, L_0x1e587d0, L_0x1e588c0, L_0x1e592f0, C4<1>; +L_0x1e58960 .delay (10000,10000,10000) L_0x1e58960/d; +L_0x1e58aa0/d .functor NAND 1, L_0x1e59030, L_0x1e588c0, L_0x1e594a0, C4<1>; +L_0x1e58aa0 .delay (10000,10000,10000) L_0x1e58aa0/d; +L_0x1e58b90/d .functor NAND 1, L_0x1e587d0, L_0x1e59160, L_0x1e59540, C4<1>; +L_0x1e58b90 .delay (10000,10000,10000) L_0x1e58b90/d; +L_0x1e58c80/d .functor NAND 1, L_0x1e59030, L_0x1e59160, L_0x1e595e0, C4<1>; +L_0x1e58c80 .delay (10000,10000,10000) L_0x1e58c80/d; +L_0x1e58d60/d .functor NAND 1, L_0x1e58960, L_0x1e58aa0, L_0x1e58b90, L_0x1e58c80; +L_0x1e58d60 .delay (10000,10000,10000) L_0x1e58d60/d; +v0x1e29e10_0 .net "S0", 0 0, L_0x1e59030; 1 drivers +v0x1e29ed0_0 .net "S1", 0 0, L_0x1e59160; 1 drivers +v0x1e29f70_0 .net "in0", 0 0, L_0x1e592f0; 1 drivers +v0x1e2a010_0 .net "in1", 0 0, L_0x1e594a0; 1 drivers +v0x1e2a090_0 .net "in2", 0 0, L_0x1e59540; 1 drivers +v0x1e2a130_0 .net "in3", 0 0, L_0x1e595e0; 1 drivers +v0x1e2a210_0 .net "nS0", 0 0, L_0x1e587d0; 1 drivers +v0x1e2a2b0_0 .net "nS1", 0 0, L_0x1e588c0; 1 drivers +v0x1e2a350_0 .net "out", 0 0, L_0x1e58d60; 1 drivers +v0x1e2a3f0_0 .net "out0", 0 0, L_0x1e58960; 1 drivers +v0x1e2a490_0 .net "out1", 0 0, L_0x1e58aa0; 1 drivers +v0x1e2a530_0 .net "out2", 0 0, L_0x1e58b90; 1 drivers +v0x1e2a640_0 .net "out3", 0 0, L_0x1e58c80; 1 drivers +S_0x1e297b0 .scope module, "TwoMux" "TwoInMux" 3 294, 3 8, S_0x1e29640; + .timescale -9 -12; +L_0x1e59290/d .functor NOT 1, L_0x1e59b30, C4<0>, C4<0>, C4<0>; +L_0x1e59290 .delay (10000,10000,10000) L_0x1e59290/d; +L_0x1e59720/d .functor AND 1, L_0x1e59bd0, L_0x1e59290, C4<1>, C4<1>; +L_0x1e59720 .delay (20000,20000,20000) L_0x1e59720/d; +L_0x1e59810/d .functor AND 1, L_0x1e59d10, L_0x1e59b30, C4<1>, C4<1>; +L_0x1e59810 .delay (20000,20000,20000) L_0x1e59810/d; +L_0x1e59900/d .functor OR 1, L_0x1e59720, L_0x1e59810, C4<0>, C4<0>; +L_0x1e59900 .delay (20000,20000,20000) L_0x1e59900/d; +v0x1e298a0_0 .net "S", 0 0, L_0x1e59b30; 1 drivers +v0x1e29940_0 .net "in0", 0 0, L_0x1e59bd0; 1 drivers +v0x1e299e0_0 .net "in1", 0 0, L_0x1e59d10; 1 drivers +v0x1e29a80_0 .net "nS", 0 0, L_0x1e59290; 1 drivers +v0x1e29b00_0 .net "out0", 0 0, L_0x1e59720; 1 drivers +v0x1e29ba0_0 .net "out1", 0 0, L_0x1e59810; 1 drivers +v0x1e29c80_0 .net "outfinal", 0 0, L_0x1e59900; 1 drivers +S_0x1e27ac0 .scope generate, "muxbits[2]" "muxbits[2]" 3 290, 3 290, S_0x1da9070; + .timescale -9 -12; +P_0x1e26a08 .param/l "i" 3 290, +C4<010>; +L_0x1e5c2e0/d .functor OR 1, L_0x1e5ca60, L_0x1e5cde0, C4<0>, C4<0>; +L_0x1e5c2e0 .delay (20000,20000,20000) L_0x1e5c2e0/d; +v0x1e294e0_0 .net *"_s15", 0 0, L_0x1e5ca60; 1 drivers +v0x1e295a0_0 .net *"_s16", 0 0, L_0x1e5cde0; 1 drivers +S_0x1e28b60 .scope module, "ZeroMux" "FourInMux" 3 292, 3 24, S_0x1e27ac0; + .timescale -9 -12; +L_0x1e5a230/d .functor NOT 1, L_0x1e5a130, C4<0>, C4<0>, C4<0>; +L_0x1e5a230 .delay (10000,10000,10000) L_0x1e5a230/d; +L_0x1e5a320/d .functor NOT 1, L_0x1e5ab90, C4<0>, C4<0>, C4<0>; +L_0x1e5a320 .delay (10000,10000,10000) L_0x1e5a320/d; +L_0x1e5a3c0/d .functor NAND 1, L_0x1e5a230, L_0x1e5a320, L_0x1e5aa40, C4<1>; +L_0x1e5a3c0 .delay (10000,10000,10000) L_0x1e5a3c0/d; +L_0x1e5a500/d .functor NAND 1, L_0x1e5a130, L_0x1e5a320, L_0x1e5ad90, C4<1>; +L_0x1e5a500 .delay (10000,10000,10000) L_0x1e5a500/d; +L_0x1e5a5f0/d .functor NAND 1, L_0x1e5a230, L_0x1e5ab90, L_0x1e5acc0, C4<1>; +L_0x1e5a5f0 .delay (10000,10000,10000) L_0x1e5a5f0/d; +L_0x1e5a6e0/d .functor NAND 1, L_0x1e5a130, L_0x1e5ab90, L_0x1e5af60, C4<1>; +L_0x1e5a6e0 .delay (10000,10000,10000) L_0x1e5a6e0/d; +L_0x1e5a7c0/d .functor NAND 1, L_0x1e5a3c0, L_0x1e5a500, L_0x1e5a5f0, L_0x1e5a6e0; +L_0x1e5a7c0 .delay (10000,10000,10000) L_0x1e5a7c0/d; +v0x1e28c50_0 .net "S0", 0 0, L_0x1e5a130; 1 drivers +v0x1e28d10_0 .net "S1", 0 0, L_0x1e5ab90; 1 drivers +v0x1e28db0_0 .net "in0", 0 0, L_0x1e5aa40; 1 drivers +v0x1e28e50_0 .net "in1", 0 0, L_0x1e5ad90; 1 drivers +v0x1e28ed0_0 .net "in2", 0 0, L_0x1e5acc0; 1 drivers +v0x1e28f70_0 .net "in3", 0 0, L_0x1e5af60; 1 drivers +v0x1e29010_0 .net "nS0", 0 0, L_0x1e5a230; 1 drivers +v0x1e290b0_0 .net "nS1", 0 0, L_0x1e5a320; 1 drivers +v0x1e29150_0 .net "out", 0 0, L_0x1e5a7c0; 1 drivers +v0x1e291f0_0 .net "out0", 0 0, L_0x1e5a3c0; 1 drivers +v0x1e29290_0 .net "out1", 0 0, L_0x1e5a500; 1 drivers +v0x1e29330_0 .net "out2", 0 0, L_0x1e5a5f0; 1 drivers +v0x1e29440_0 .net "out3", 0 0, L_0x1e5a6e0; 1 drivers +S_0x1e281a0 .scope module, "OneMux" "FourInMux" 3 293, 3 24, S_0x1e27ac0; + .timescale -9 -12; +L_0x1e5ae30/d .functor NOT 1, L_0x1e5b900, C4<0>, C4<0>, C4<0>; +L_0x1e5ae30 .delay (10000,10000,10000) L_0x1e5ae30/d; +L_0x1e5b190/d .functor NOT 1, L_0x1e5b050, C4<0>, C4<0>, C4<0>; +L_0x1e5b190 .delay (10000,10000,10000) L_0x1e5b190/d; +L_0x1e5b1f0/d .functor NAND 1, L_0x1e5ae30, L_0x1e5b190, L_0x1e49f50, C4<1>; +L_0x1e5b1f0 .delay (10000,10000,10000) L_0x1e5b1f0/d; +L_0x1e5b330/d .functor NAND 1, L_0x1e5b900, L_0x1e5b190, L_0x1e4a100, C4<1>; +L_0x1e5b330 .delay (10000,10000,10000) L_0x1e5b330/d; +L_0x1e5b420/d .functor NAND 1, L_0x1e5ae30, L_0x1e5b050, L_0x1e49dc0, C4<1>; +L_0x1e5b420 .delay (10000,10000,10000) L_0x1e5b420/d; +L_0x1e5b510/d .functor NAND 1, L_0x1e5b900, L_0x1e5b050, L_0x1e49ff0, C4<1>; +L_0x1e5b510 .delay (10000,10000,10000) L_0x1e5b510/d; +L_0x1e5b650/d .functor NAND 1, L_0x1e5b1f0, L_0x1e5b330, L_0x1e5b420, L_0x1e5b510; +L_0x1e5b650 .delay (10000,10000,10000) L_0x1e5b650/d; +v0x1e28290_0 .net "S0", 0 0, L_0x1e5b900; 1 drivers +v0x1e28350_0 .net "S1", 0 0, L_0x1e5b050; 1 drivers +v0x1e283f0_0 .net "in0", 0 0, L_0x1e49f50; 1 drivers +v0x1e28490_0 .net "in1", 0 0, L_0x1e4a100; 1 drivers +v0x1e28510_0 .net "in2", 0 0, L_0x1e49dc0; 1 drivers +v0x1e285b0_0 .net "in3", 0 0, L_0x1e49ff0; 1 drivers +v0x1e28690_0 .net "nS0", 0 0, L_0x1e5ae30; 1 drivers +v0x1e28730_0 .net "nS1", 0 0, L_0x1e5b190; 1 drivers +v0x1e287d0_0 .net "out", 0 0, L_0x1e5b650; 1 drivers +v0x1e28870_0 .net "out0", 0 0, L_0x1e5b1f0; 1 drivers +v0x1e28910_0 .net "out1", 0 0, L_0x1e5b330; 1 drivers +v0x1e289b0_0 .net "out2", 0 0, L_0x1e5b420; 1 drivers +v0x1e28ac0_0 .net "out3", 0 0, L_0x1e5b510; 1 drivers +S_0x1e27c30 .scope module, "TwoMux" "TwoInMux" 3 294, 3 8, S_0x1e27ac0; + .timescale -9 -12; +L_0x1e4a090/d .functor NOT 1, L_0x1e5c240, C4<0>, C4<0>, C4<0>; +L_0x1e4a090 .delay (10000,10000,10000) L_0x1e4a090/d; +L_0x1e5c3b0/d .functor AND 1, L_0x1e5c8f0, L_0x1e4a090, C4<1>, C4<1>; +L_0x1e5c3b0 .delay (20000,20000,20000) L_0x1e5c3b0/d; +L_0x1e5c460/d .functor AND 1, L_0x1e5c7c0, L_0x1e5c240, C4<1>, C4<1>; +L_0x1e5c460 .delay (20000,20000,20000) L_0x1e5c460/d; +L_0x1e5c550/d .functor OR 1, L_0x1e5c3b0, L_0x1e5c460, C4<0>, C4<0>; +L_0x1e5c550 .delay (20000,20000,20000) L_0x1e5c550/d; +v0x1e27d20_0 .net "S", 0 0, L_0x1e5c240; 1 drivers +v0x1e27dc0_0 .net "in0", 0 0, L_0x1e5c8f0; 1 drivers +v0x1e27e60_0 .net "in1", 0 0, L_0x1e5c7c0; 1 drivers +v0x1e27f00_0 .net "nS", 0 0, L_0x1e4a090; 1 drivers +v0x1e27f80_0 .net "out0", 0 0, L_0x1e5c3b0; 1 drivers +v0x1e28020_0 .net "out1", 0 0, L_0x1e5c460; 1 drivers +v0x1e28100_0 .net "outfinal", 0 0, L_0x1e5c550; 1 drivers +S_0x1da89f0 .scope generate, "muxbits[3]" "muxbits[3]" 3 290, 3 290, S_0x1da9070; + .timescale -9 -12; +P_0x1d9fce8 .param/l "i" 3 290, +C4<011>; +L_0x1e5f4a0/d .functor OR 1, L_0x1e5f820, L_0x1e5f630, C4<0>, C4<0>; +L_0x1e5f4a0 .delay (20000,20000,20000) L_0x1e5f4a0/d; +v0x1e27960_0 .net *"_s15", 0 0, L_0x1e5f820; 1 drivers +v0x1e27a20_0 .net *"_s16", 0 0, L_0x1e5f630; 1 drivers +S_0x1e26fe0 .scope module, "ZeroMux" "FourInMux" 3 292, 3 24, S_0x1da89f0; + .timescale -9 -12; +L_0x1e5cc90/d .functor NOT 1, L_0x1e5d790, C4<0>, C4<0>, C4<0>; +L_0x1e5cc90 .delay (10000,10000,10000) L_0x1e5cc90/d; +L_0x1e5cd80/d .functor NOT 1, L_0x1e5ce80, C4<0>, C4<0>, C4<0>; +L_0x1e5cd80 .delay (10000,10000,10000) L_0x1e5cd80/d; +L_0x1e5d020/d .functor NAND 1, L_0x1e5cc90, L_0x1e5cd80, L_0x1e5da30, C4<1>; +L_0x1e5d020 .delay (10000,10000,10000) L_0x1e5d020/d; +L_0x1e5d160/d .functor NAND 1, L_0x1e5d790, L_0x1e5cd80, L_0x1e4f9f0, C4<1>; +L_0x1e5d160 .delay (10000,10000,10000) L_0x1e5d160/d; +L_0x1e5d250/d .functor NAND 1, L_0x1e5cc90, L_0x1e5ce80, L_0x1e5d8c0, C4<1>; +L_0x1e5d250 .delay (10000,10000,10000) L_0x1e5d250/d; +L_0x1e5d370/d .functor NAND 1, L_0x1e5d790, L_0x1e5ce80, L_0x1e5de70, C4<1>; +L_0x1e5d370 .delay (10000,10000,10000) L_0x1e5d370/d; +L_0x1e5d4e0/d .functor NAND 1, L_0x1e5d020, L_0x1e5d160, L_0x1e5d250, L_0x1e5d370; +L_0x1e5d4e0 .delay (10000,10000,10000) L_0x1e5d4e0/d; +v0x1e270d0_0 .net "S0", 0 0, L_0x1e5d790; 1 drivers +v0x1e27190_0 .net "S1", 0 0, L_0x1e5ce80; 1 drivers +v0x1e27230_0 .net "in0", 0 0, L_0x1e5da30; 1 drivers +v0x1e272d0_0 .net "in1", 0 0, L_0x1e4f9f0; 1 drivers +v0x1e27350_0 .net "in2", 0 0, L_0x1e5d8c0; 1 drivers +v0x1e273f0_0 .net "in3", 0 0, L_0x1e5de70; 1 drivers +v0x1e27490_0 .net "nS0", 0 0, L_0x1e5cc90; 1 drivers +v0x1e27530_0 .net "nS1", 0 0, L_0x1e5cd80; 1 drivers +v0x1e275d0_0 .net "out", 0 0, L_0x1e5d4e0; 1 drivers +v0x1e27670_0 .net "out0", 0 0, L_0x1e5d020; 1 drivers +v0x1e27710_0 .net "out1", 0 0, L_0x1e5d160; 1 drivers +v0x1e277b0_0 .net "out2", 0 0, L_0x1e5d250; 1 drivers +v0x1e278c0_0 .net "out3", 0 0, L_0x1e5d370; 1 drivers +S_0x1e26570 .scope module, "OneMux" "FourInMux" 3 293, 3 24, S_0x1da89f0; + .timescale -9 -12; +L_0x1e5d9b0/d .functor NOT 1, L_0x1e5dce0, C4<0>, C4<0>, C4<0>; +L_0x1e5d9b0 .delay (10000,10000,10000) L_0x1e5d9b0/d; +L_0x1e5dfa0/d .functor NOT 1, L_0x1e5e920, C4<0>, C4<0>, C4<0>; +L_0x1e5dfa0 .delay (10000,10000,10000) L_0x1e5dfa0/d; +L_0x1e5e040/d .functor NAND 1, L_0x1e5d9b0, L_0x1e5dfa0, L_0x1e5e780, C4<1>; +L_0x1e5e040 .delay (10000,10000,10000) L_0x1e5e040/d; +L_0x1e5e180/d .functor NAND 1, L_0x1e5dce0, L_0x1e5dfa0, L_0x1e5e820, C4<1>; +L_0x1e5e180 .delay (10000,10000,10000) L_0x1e5e180/d; +L_0x1e5e270/d .functor NAND 1, L_0x1e5d9b0, L_0x1e5e920, L_0x1e5ec10, C4<1>; +L_0x1e5e270 .delay (10000,10000,10000) L_0x1e5e270/d; +L_0x1e5e360/d .functor NAND 1, L_0x1e5dce0, L_0x1e5e920, L_0x1e5ecb0, C4<1>; +L_0x1e5e360 .delay (10000,10000,10000) L_0x1e5e360/d; +L_0x1e5e4d0/d .functor NAND 1, L_0x1e5e040, L_0x1e5e180, L_0x1e5e270, L_0x1e5e360; +L_0x1e5e4d0 .delay (10000,10000,10000) L_0x1e5e4d0/d; +v0x1e26660_0 .net "S0", 0 0, L_0x1e5dce0; 1 drivers +v0x1e26720_0 .net "S1", 0 0, L_0x1e5e920; 1 drivers +v0x1e267c0_0 .net "in0", 0 0, L_0x1e5e780; 1 drivers +v0x1e26860_0 .net "in1", 0 0, L_0x1e5e820; 1 drivers +v0x1e268e0_0 .net "in2", 0 0, L_0x1e5ec10; 1 drivers +v0x1e26980_0 .net "in3", 0 0, L_0x1e5ecb0; 1 drivers +v0x1e26a60_0 .net "nS0", 0 0, L_0x1e5d9b0; 1 drivers +v0x1e26b00_0 .net "nS1", 0 0, L_0x1e5dfa0; 1 drivers +v0x1e26bf0_0 .net "out", 0 0, L_0x1e5e4d0; 1 drivers +v0x1e26c90_0 .net "out0", 0 0, L_0x1e5e040; 1 drivers +v0x1e26d90_0 .net "out1", 0 0, L_0x1e5e180; 1 drivers +v0x1e26e30_0 .net "out2", 0 0, L_0x1e5e270; 1 drivers +v0x1e26f40_0 .net "out3", 0 0, L_0x1e5e360; 1 drivers +S_0x1da5cd0 .scope module, "TwoMux" "TwoInMux" 3 294, 3 8, S_0x1da89f0; + .timescale -9 -12; +L_0x1e58620/d .functor NOT 1, L_0x1e5f360, C4<0>, C4<0>, C4<0>; +L_0x1e58620 .delay (10000,10000,10000) L_0x1e58620/d; +L_0x1e5ea50/d .functor AND 1, L_0x1e5ef60, L_0x1e58620, C4<1>, C4<1>; +L_0x1e5ea50 .delay (20000,20000,20000) L_0x1e5ea50/d; +L_0x1e5eb40/d .functor AND 1, L_0x1e5f050, L_0x1e5f360, C4<1>, C4<1>; +L_0x1e5eb40 .delay (20000,20000,20000) L_0x1e5eb40/d; +L_0x1e5f180/d .functor OR 1, L_0x1e5ea50, L_0x1e5eb40, C4<0>, C4<0>; +L_0x1e5f180 .delay (20000,20000,20000) L_0x1e5f180/d; +v0x1d73ba0_0 .net "S", 0 0, L_0x1e5f360; 1 drivers +v0x1e26160_0 .net "in0", 0 0, L_0x1e5ef60; 1 drivers +v0x1e26200_0 .net "in1", 0 0, L_0x1e5f050; 1 drivers +v0x1e262a0_0 .net "nS", 0 0, L_0x1e58620; 1 drivers +v0x1e26350_0 .net "out0", 0 0, L_0x1e5ea50; 1 drivers +v0x1e263f0_0 .net "out1", 0 0, L_0x1e5eb40; 1 drivers +v0x1e264d0_0 .net "outfinal", 0 0, L_0x1e5f180; 1 drivers + .scope S_0x1da9580; +T_0 ; + %vpi_call 2 150 "$display", "Test 4 Bit Adder Functionality"; + %vpi_call 2 152 "$display", " A | B |Command| Out|ExpectedOut|Cout|OF"; + %movi 8, 2, 4; + %set/v v0x1e49000_0, 8, 4; + %movi 8, 4, 4; + %set/v v0x1e49200_0, 8, 4; + %set/v v0x1e49280_0, 0, 3; + %delay 1000000, 0; + %vpi_call 2 156 "$display", "%b | %b | %b | %b | Expect 0110| %b | %b ", v0x1e49000_0, v0x1e49200_0, v0x1e49280_0, v0x1e49080_0, v0x1e49580_0, v0x1e49600_0; + %movi 8, 1, 4; + %set/v v0x1e49000_0, 8, 4; + %movi 8, 6, 4; + %set/v v0x1e49200_0, 8, 4; + %set/v v0x1e49280_0, 0, 3; + %delay 1000000, 0; + %vpi_call 2 160 "$display", "%b | %b | %b | %b | Expect 0111| %b | %b ", v0x1e49000_0, v0x1e49200_0, v0x1e49280_0, v0x1e49080_0, v0x1e49580_0, v0x1e49600_0; + %movi 8, 5, 4; + %set/v v0x1e49000_0, 8, 4; + %movi 8, 13, 4; + %set/v v0x1e49200_0, 8, 4; + %set/v v0x1e49280_0, 0, 3; + %delay 1000000, 0; + %vpi_call 2 164 "$display", "%b | %b | %b | %b | Expect 0010| %b | %b ", v0x1e49000_0, v0x1e49200_0, v0x1e49280_0, v0x1e49080_0, v0x1e49580_0, v0x1e49600_0; + %movi 8, 2, 4; + %set/v v0x1e49000_0, 8, 4; + %set/v v0x1e49200_0, 1, 4; + %set/v v0x1e49280_0, 0, 3; + %delay 1000000, 0; + %vpi_call 2 168 "$display", "%b | %b | %b | %b | Expect 0001| %b | %b ", v0x1e49000_0, v0x1e49200_0, v0x1e49280_0, v0x1e49080_0, v0x1e49580_0, v0x1e49600_0; + %movi 8, 8, 4; + %set/v v0x1e49000_0, 8, 4; + %movi 8, 3, 4; + %set/v v0x1e49200_0, 8, 4; + %set/v v0x1e49280_0, 0, 3; + %delay 1000000, 0; + %vpi_call 2 172 "$display", "%b | %b | %b | %b | Expect 1011| %b | %b ", v0x1e49000_0, v0x1e49200_0, v0x1e49280_0, v0x1e49080_0, v0x1e49580_0, v0x1e49600_0; + %movi 8, 12, 4; + %set/v v0x1e49000_0, 8, 4; + %movi 8, 2, 4; + %set/v v0x1e49200_0, 8, 4; + %set/v v0x1e49280_0, 0, 3; + %delay 1000000, 0; + %vpi_call 2 176 "$display", "%b | %b | %b | %b | Expect 1110| %b | %b ", v0x1e49000_0, v0x1e49200_0, v0x1e49280_0, v0x1e49080_0, v0x1e49580_0, v0x1e49600_0; + %movi 8, 11, 4; + %set/v v0x1e49000_0, 8, 4; + %movi 8, 5, 4; + %set/v v0x1e49200_0, 8, 4; + %set/v v0x1e49280_0, 0, 3; + %delay 1000000, 0; + %vpi_call 2 180 "$display", "%b | %b | %b | %b | Expect 0110| %b | %b ", v0x1e49000_0, v0x1e49200_0, v0x1e49280_0, v0x1e49080_0, v0x1e49580_0, v0x1e49600_0; + %movi 8, 7, 4; + %set/v v0x1e49000_0, 8, 4; + %movi 8, 9, 4; + %set/v v0x1e49200_0, 8, 4; + %set/v v0x1e49280_0, 0, 3; + %delay 1000000, 0; + %vpi_call 2 184 "$display", "%b | %b | %b | %b | Expect 0000| %b | %b ", v0x1e49000_0, v0x1e49200_0, v0x1e49280_0, v0x1e49080_0, v0x1e49580_0, v0x1e49600_0; + %movi 8, 13, 4; + %set/v v0x1e49000_0, 8, 4; + %movi 8, 12, 4; + %set/v v0x1e49200_0, 8, 4; + %set/v v0x1e49280_0, 0, 3; + %delay 1000000, 0; + %vpi_call 2 188 "$display", "%b | %b | %b | %b | Expect 1001| %b | %b ", v0x1e49000_0, v0x1e49200_0, v0x1e49280_0, v0x1e49080_0, v0x1e49580_0, v0x1e49600_0; + %movi 8, 14, 4; + %set/v v0x1e49000_0, 8, 4; + %movi 8, 10, 4; + %set/v v0x1e49200_0, 8, 4; + %set/v v0x1e49280_0, 0, 3; + %delay 1000000, 0; + %vpi_call 2 192 "$display", "%b | %b | %b | %b | Expect 1000| %b | %b ", v0x1e49000_0, v0x1e49200_0, v0x1e49280_0, v0x1e49080_0, v0x1e49580_0, v0x1e49600_0; + %movi 8, 5, 4; + %set/v v0x1e49000_0, 8, 4; + %movi 8, 6, 4; + %set/v v0x1e49200_0, 8, 4; + %set/v v0x1e49280_0, 0, 3; + %delay 1000000, 0; + %vpi_call 2 196 "$display", "%b | %b | %b | %b | Expect XXXX| %b | %b ", v0x1e49000_0, v0x1e49200_0, v0x1e49280_0, v0x1e49080_0, v0x1e49580_0, v0x1e49600_0; + %movi 8, 2, 4; + %set/v v0x1e49000_0, 8, 4; + %movi 8, 7, 4; + %set/v v0x1e49200_0, 8, 4; + %set/v v0x1e49280_0, 0, 3; + %delay 1000000, 0; + %vpi_call 2 200 "$display", "%b | %b | %b | %b | Expect XXXX| %b | %b ", v0x1e49000_0, v0x1e49200_0, v0x1e49280_0, v0x1e49080_0, v0x1e49580_0, v0x1e49600_0; + %movi 8, 7, 4; + %set/v v0x1e49000_0, 8, 4; + %movi 8, 7, 4; + %set/v v0x1e49200_0, 8, 4; + %set/v v0x1e49280_0, 0, 3; + %delay 1000000, 0; + %vpi_call 2 204 "$display", "%b | %b | %b | %b | Expect XXXX| %b | %b ", v0x1e49000_0, v0x1e49200_0, v0x1e49280_0, v0x1e49080_0, v0x1e49580_0, v0x1e49600_0; + %movi 8, 8, 4; + %set/v v0x1e49000_0, 8, 4; + %set/v v0x1e49200_0, 1, 4; + %set/v v0x1e49280_0, 0, 3; + %delay 1000000, 0; + %vpi_call 2 208 "$display", "%b | %b | %b | %b | Expect XXXX| %b | %b ", v0x1e49000_0, v0x1e49200_0, v0x1e49280_0, v0x1e49080_0, v0x1e49580_0, v0x1e49600_0; + %movi 8, 8, 4; + %set/v v0x1e49000_0, 8, 4; + %movi 8, 13, 4; + %set/v v0x1e49200_0, 8, 4; + %set/v v0x1e49280_0, 0, 3; + %delay 1000000, 0; + %vpi_call 2 212 "$display", "%b | %b | %b | %b | Expect XXXX| %b | %b ", v0x1e49000_0, v0x1e49200_0, v0x1e49280_0, v0x1e49080_0, v0x1e49580_0, v0x1e49600_0; + %movi 8, 11, 4; + %set/v v0x1e49000_0, 8, 4; + %movi 8, 12, 4; + %set/v v0x1e49200_0, 8, 4; + %set/v v0x1e49280_0, 0, 3; + %delay 1000000, 0; + %vpi_call 2 216 "$display", "%b | %b | %b | %b | Expect XXXX| %b | %b ", v0x1e49000_0, v0x1e49200_0, v0x1e49280_0, v0x1e49080_0, v0x1e49580_0, v0x1e49600_0; + %vpi_call 2 218 "$display", "Test 4 Bit SLT Functionality"; + %vpi_call 2 220 "$display", " A | B |Command| Out|ExpectedOut|Cout|OF |SLTflag"; + %movi 8, 2, 4; + %set/v v0x1e49000_0, 8, 4; + %movi 8, 4, 4; + %set/v v0x1e49200_0, 8, 4; + %movi 8, 3, 3; + %set/v v0x1e49280_0, 8, 3; + %delay 1000000, 0; + %vpi_call 2 224 "$display", "%b | %b | %b | %b | Expect 1110| %b | %b | %b", v0x1e49000_0, v0x1e49200_0, v0x1e49280_0, v0x1e49080_0, v0x1e49580_0, v0x1e49600_0, v0x1e49400_0; + %movi 8, 4, 4; + %set/v v0x1e49000_0, 8, 4; + %movi 8, 2, 4; + %set/v v0x1e49200_0, 8, 4; + %movi 8, 3, 3; + %set/v v0x1e49280_0, 8, 3; + %delay 1000000, 0; + %vpi_call 2 228 "$display", "%b | %b | %b | %b | Expect 0010| %b | %b | %b", v0x1e49000_0, v0x1e49200_0, v0x1e49280_0, v0x1e49080_0, v0x1e49580_0, v0x1e49600_0, v0x1e49400_0; + %movi 8, 14, 4; + %set/v v0x1e49000_0, 8, 4; + %movi 8, 4, 4; + %set/v v0x1e49200_0, 8, 4; + %movi 8, 3, 3; + %set/v v0x1e49280_0, 8, 3; + %delay 1000000, 0; + %vpi_call 2 232 "$display", "%b | %b | %b | %b | Expect 1010| %b | %b | %b", v0x1e49000_0, v0x1e49200_0, v0x1e49280_0, v0x1e49080_0, v0x1e49580_0, v0x1e49600_0, v0x1e49400_0; + %movi 8, 4, 4; + %set/v v0x1e49000_0, 8, 4; + %movi 8, 14, 4; + %set/v v0x1e49200_0, 8, 4; + %movi 8, 3, 3; + %set/v v0x1e49280_0, 8, 3; + %delay 1000000, 0; + %vpi_call 2 236 "$display", "%b | %b | %b | %b | Expect 0110| %b | %b | %b", v0x1e49000_0, v0x1e49200_0, v0x1e49280_0, v0x1e49080_0, v0x1e49580_0, v0x1e49600_0, v0x1e49400_0; + %movi 8, 14, 4; + %set/v v0x1e49000_0, 8, 4; + %set/v v0x1e49200_0, 1, 4; + %movi 8, 3, 3; + %set/v v0x1e49280_0, 8, 3; + %delay 1000000, 0; + %vpi_call 2 240 "$display", "%b | %b | %b | %b | Expect 1111| %b | %b | %b", v0x1e49000_0, v0x1e49200_0, v0x1e49280_0, v0x1e49080_0, v0x1e49580_0, v0x1e49600_0, v0x1e49400_0; + %set/v v0x1e49000_0, 1, 4; + %movi 8, 14, 4; + %set/v v0x1e49200_0, 8, 4; + %movi 8, 3, 3; + %set/v v0x1e49280_0, 8, 3; + %delay 1000000, 0; + %vpi_call 2 244 "$display", "%b | %b | %b | %b | Expect 0001| %b | %b | %b", v0x1e49000_0, v0x1e49200_0, v0x1e49280_0, v0x1e49080_0, v0x1e49580_0, v0x1e49600_0, v0x1e49400_0; + %movi 8, 13, 4; + %set/v v0x1e49000_0, 8, 4; + %movi 8, 13, 4; + %set/v v0x1e49200_0, 8, 4; + %movi 8, 3, 3; + %set/v v0x1e49280_0, 8, 3; + %delay 1000000, 0; + %vpi_call 2 248 "$display", "%b | %b | %b | %b | Expect 0000| %b | %b | %b", v0x1e49000_0, v0x1e49200_0, v0x1e49280_0, v0x1e49080_0, v0x1e49580_0, v0x1e49600_0, v0x1e49400_0; + %movi 8, 5, 4; + %set/v v0x1e49000_0, 8, 4; + %movi 8, 5, 4; + %set/v v0x1e49200_0, 8, 4; + %movi 8, 3, 3; + %set/v v0x1e49280_0, 8, 3; + %delay 1000000, 0; + %vpi_call 2 252 "$display", "%b | %b | %b | %b | Expect 0000| %b | %b | %b", v0x1e49000_0, v0x1e49200_0, v0x1e49280_0, v0x1e49080_0, v0x1e49580_0, v0x1e49600_0, v0x1e49400_0; + %movi 8, 9, 4; + %set/v v0x1e49000_0, 8, 4; + %movi 8, 5, 4; + %set/v v0x1e49200_0, 8, 4; + %movi 8, 3, 3; + %set/v v0x1e49280_0, 8, 3; + %delay 1000000, 0; + %vpi_call 2 256 "$display", "%b | %b | %b | %b | Expect XXXX| %b | %b | %b", v0x1e49000_0, v0x1e49200_0, v0x1e49280_0, v0x1e49080_0, v0x1e49580_0, v0x1e49600_0, v0x1e49400_0; + %vpi_call 2 258 "$display", "Test 4 Bit AND/NAND Functionality"; + %vpi_call 2 260 "$display", " A | B |Command| Out |ExpectedOut-AND"; + %set/v v0x1e49000_0, 1, 4; + %set/v v0x1e49200_0, 1, 4; + %movi 8, 4, 3; + %set/v v0x1e49280_0, 8, 3; + %delay 1000000, 0; + %vpi_call 2 264 "$display", "%b | %b | %b | %b | 1111", v0x1e49000_0, v0x1e49200_0, v0x1e49280_0, v0x1e49180_0; + %set/v v0x1e49000_0, 1, 4; + %movi 8, 10, 4; + %set/v v0x1e49200_0, 8, 4; + %movi 8, 4, 3; + %set/v v0x1e49280_0, 8, 3; + %delay 1000000, 0; + %vpi_call 2 268 "$display", "%b | %b | %b | %b | 1010", v0x1e49000_0, v0x1e49200_0, v0x1e49280_0, v0x1e49180_0; + %set/v v0x1e49000_0, 1, 4; + %movi 8, 5, 4; + %set/v v0x1e49200_0, 8, 4; + %movi 8, 4, 3; + %set/v v0x1e49280_0, 8, 3; + %delay 1000000, 0; + %vpi_call 2 272 "$display", "%b | %b | %b | %b | 0101", v0x1e49000_0, v0x1e49200_0, v0x1e49280_0, v0x1e49180_0; + %set/v v0x1e49000_0, 1, 4; + %set/v v0x1e49200_0, 0, 4; + %movi 8, 4, 3; + %set/v v0x1e49280_0, 8, 3; + %delay 1000000, 0; + %vpi_call 2 276 "$display", "%b | %b | %b | %b | 0000", v0x1e49000_0, v0x1e49200_0, v0x1e49280_0, v0x1e49180_0; + %vpi_call 2 279 "$display", " A | B |Command| Out |ExpectedOut-NAND"; + %set/v v0x1e49000_0, 1, 4; + %set/v v0x1e49200_0, 1, 4; + %movi 8, 5, 3; + %set/v v0x1e49280_0, 8, 3; + %delay 1000000, 0; + %vpi_call 2 283 "$display", "%b | %b | %b | %b | 0000", v0x1e49000_0, v0x1e49200_0, v0x1e49280_0, v0x1e49180_0; + %set/v v0x1e49000_0, 1, 4; + %movi 8, 10, 4; + %set/v v0x1e49200_0, 8, 4; + %movi 8, 5, 3; + %set/v v0x1e49280_0, 8, 3; + %delay 1000000, 0; + %vpi_call 2 287 "$display", "%b | %b | %b | %b | 0101", v0x1e49000_0, v0x1e49200_0, v0x1e49280_0, v0x1e49180_0; + %set/v v0x1e49000_0, 1, 4; + %movi 8, 5, 4; + %set/v v0x1e49200_0, 8, 4; + %movi 8, 5, 3; + %set/v v0x1e49280_0, 8, 3; + %delay 1000000, 0; + %vpi_call 2 291 "$display", "%b | %b | %b | %b | 1010", v0x1e49000_0, v0x1e49200_0, v0x1e49280_0, v0x1e49180_0; + %set/v v0x1e49000_0, 1, 4; + %set/v v0x1e49200_0, 0, 4; + %movi 8, 5, 3; + %set/v v0x1e49280_0, 8, 3; + %delay 1000000, 0; + %vpi_call 2 295 "$display", "%b | %b | %b | %b | 1111", v0x1e49000_0, v0x1e49200_0, v0x1e49280_0, v0x1e49180_0; + %vpi_call 2 297 "$display", "Test 4 Bit OR/NOR/XOR Functionality"; + %vpi_call 2 299 "$display", " A | B |Command | Out |ExpectedOut-OR"; + %movi 8, 10, 4; + %set/v v0x1e49000_0, 8, 4; + %movi 8, 5, 4; + %set/v v0x1e49200_0, 8, 4; + %set/v v0x1e49280_0, 1, 3; + %delay 1000000, 0; + %vpi_call 2 303 "$display", "%b | %b | %b | %b | 1111", v0x1e49000_0, v0x1e49200_0, v0x1e49280_0, v0x1e49380_0; + %set/v v0x1e49000_0, 1, 4; + %movi 8, 5, 4; + %set/v v0x1e49200_0, 8, 4; + %set/v v0x1e49280_0, 1, 3; + %delay 1000000, 0; + %vpi_call 2 307 "$display", "%b | %b | %b | %b | 1111", v0x1e49000_0, v0x1e49200_0, v0x1e49280_0, v0x1e49380_0; + %movi 8, 11, 4; + %set/v v0x1e49000_0, 8, 4; + %set/v v0x1e49200_0, 0, 4; + %set/v v0x1e49280_0, 1, 3; + %delay 1000000, 0; + %vpi_call 2 311 "$display", "%b | %b | %b | %b | 1011", v0x1e49000_0, v0x1e49200_0, v0x1e49280_0, v0x1e49380_0; + %vpi_call 2 313 "$display", " A | B |Command | Out |ExpectedOut-NOR"; + %movi 8, 10, 4; + %set/v v0x1e49000_0, 8, 4; + %movi 8, 5, 4; + %set/v v0x1e49200_0, 8, 4; + %movi 8, 6, 3; + %set/v v0x1e49280_0, 8, 3; + %delay 1000000, 0; + %vpi_call 2 317 "$display", "%b | %b | %b | %b | 0000", v0x1e49000_0, v0x1e49200_0, v0x1e49280_0, v0x1e49380_0; + %set/v v0x1e49000_0, 1, 4; + %movi 8, 5, 4; + %set/v v0x1e49200_0, 8, 4; + %movi 8, 6, 3; + %set/v v0x1e49280_0, 8, 3; + %delay 1000000, 0; + %vpi_call 2 321 "$display", "%b | %b | %b | %b | 0000", v0x1e49000_0, v0x1e49200_0, v0x1e49280_0, v0x1e49380_0; + %movi 8, 11, 4; + %set/v v0x1e49000_0, 8, 4; + %set/v v0x1e49200_0, 0, 4; + %movi 8, 6, 3; + %set/v v0x1e49280_0, 8, 3; + %delay 1000000, 0; + %vpi_call 2 325 "$display", "%b | %b | %b | %b | 0100", v0x1e49000_0, v0x1e49200_0, v0x1e49280_0, v0x1e49380_0; + %vpi_call 2 327 "$display", " A | B |Command | Out |ExpectedOut-XOR"; + %movi 8, 10, 4; + %set/v v0x1e49000_0, 8, 4; + %movi 8, 5, 4; + %set/v v0x1e49200_0, 8, 4; + %movi 8, 2, 3; + %set/v v0x1e49280_0, 8, 3; + %delay 1000000, 0; + %vpi_call 2 331 "$display", "%b | %b | %b | %b | 1111", v0x1e49000_0, v0x1e49200_0, v0x1e49280_0, v0x1e49380_0; + %set/v v0x1e49000_0, 1, 4; + %movi 8, 5, 4; + %set/v v0x1e49200_0, 8, 4; + %movi 8, 2, 3; + %set/v v0x1e49280_0, 8, 3; + %delay 1000000, 0; + %vpi_call 2 335 "$display", "%b | %b | %b | %b | 1010", v0x1e49000_0, v0x1e49200_0, v0x1e49280_0, v0x1e49380_0; + %movi 8, 11, 4; + %set/v v0x1e49000_0, 8, 4; + %set/v v0x1e49200_0, 0, 4; + %movi 8, 2, 3; + %set/v v0x1e49280_0, 8, 3; + %delay 1000000, 0; + %vpi_call 2 339 "$display", "%b | %b | %b | %b | 1011", v0x1e49000_0, v0x1e49200_0, v0x1e49280_0, v0x1e49380_0; + %vpi_call 2 341 "$display", "Test 4 Bit ALU Functionality"; + %vpi_call 2 343 "$display", " A | B |Command | Out |ExpectedOut | COut | OF |SLT|Zero"; + %set/v v0x1e49000_0, 1, 4; + %set/v v0x1e49200_0, 1, 4; + %movi 8, 4, 3; + %set/v v0x1e49280_0, 8, 3; + %delay 1000000, 0; + %vpi_call 2 348 "$display", "%b | %b | %b - AND | %b | 1111 | %b | %b | %b | %b", v0x1e49000_0, v0x1e49200_0, v0x1e49280_0, v0x1e49300_0, v0x1e49580_0, v0x1e49600_0, v0x1e49400_0, v0x1e49100_0; + %set/v v0x1e49000_0, 1, 4; + %set/v v0x1e49200_0, 0, 4; + %movi 8, 5, 3; + %set/v v0x1e49280_0, 8, 3; + %delay 1000000, 0; + %vpi_call 2 353 "$display", "%b | %b | %b - NAND | %b | 1111 | %b | %b | %b | %b", v0x1e49000_0, v0x1e49200_0, v0x1e49280_0, v0x1e49300_0, v0x1e49580_0, v0x1e49600_0, v0x1e49400_0, v0x1e49100_0; + %set/v v0x1e49000_0, 1, 4; + %movi 8, 5, 4; + %set/v v0x1e49200_0, 8, 4; + %set/v v0x1e49280_0, 1, 3; + %delay 1000000, 0; + %vpi_call 2 358 "$display", "%b | %b | %b - OR | %b | 1111 | %b | %b | %b | %b", v0x1e49000_0, v0x1e49200_0, v0x1e49280_0, v0x1e49300_0, v0x1e49580_0, v0x1e49600_0, v0x1e49400_0, v0x1e49100_0; + %movi 8, 11, 4; + %set/v v0x1e49000_0, 8, 4; + %set/v v0x1e49200_0, 0, 4; + %movi 8, 6, 3; + %set/v v0x1e49280_0, 8, 3; + %delay 1000000, 0; + %vpi_call 2 363 "$display", "%b | %b | %b - NOR | %b | 0100 | %b | %b | %b | %b", v0x1e49000_0, v0x1e49200_0, v0x1e49280_0, v0x1e49300_0, v0x1e49580_0, v0x1e49600_0, v0x1e49400_0, v0x1e49100_0; + %movi 8, 11, 4; + %set/v v0x1e49000_0, 8, 4; + %set/v v0x1e49200_0, 0, 4; + %movi 8, 2, 3; + %set/v v0x1e49280_0, 8, 3; + %delay 1000000, 0; + %vpi_call 2 368 "$display", "%b | %b | %b - XOR | %b | 1011 | %b | %b | %b | %b", v0x1e49000_0, v0x1e49200_0, v0x1e49280_0, v0x1e49300_0, v0x1e49580_0, v0x1e49600_0, v0x1e49400_0, v0x1e49100_0; + %movi 8, 2, 4; + %set/v v0x1e49000_0, 8, 4; + %movi 8, 4, 4; + %set/v v0x1e49200_0, 8, 4; + %set/v v0x1e49280_0, 0, 3; + %delay 1000000, 0; + %vpi_call 2 373 "$display", "%b | %b | %b - ADD | %b | 0110 | %b | %b | %b | %b", v0x1e49000_0, v0x1e49200_0, v0x1e49280_0, v0x1e49300_0, v0x1e49580_0, v0x1e49600_0, v0x1e49400_0, v0x1e49100_0; + %movi 8, 11, 4; + %set/v v0x1e49000_0, 8, 4; + %movi 8, 12, 4; + %set/v v0x1e49200_0, 8, 4; + %set/v v0x1e49280_0, 0, 3; + %delay 1000000, 0; + %vpi_call 2 377 "$display", "%b | %b | %b - ADD | %b | XXXX | %b | %b | %b | %b", v0x1e49000_0, v0x1e49200_0, v0x1e49280_0, v0x1e49300_0, v0x1e49580_0, v0x1e49600_0, v0x1e49400_0, v0x1e49100_0; + %movi 8, 2, 4; + %set/v v0x1e49000_0, 8, 4; + %movi 8, 4, 4; + %set/v v0x1e49200_0, 8, 4; + %movi 8, 1, 3; + %set/v v0x1e49280_0, 8, 3; + %delay 1000000, 0; + %vpi_call 2 382 "$display", "%b | %b | %b - SUB | %b | 1110 | %b | %b | %b | %b", v0x1e49000_0, v0x1e49200_0, v0x1e49280_0, v0x1e49300_0, v0x1e49580_0, v0x1e49600_0, v0x1e49400_0, v0x1e49100_0; + %movi 8, 9, 4; + %set/v v0x1e49000_0, 8, 4; + %movi 8, 3, 4; + %set/v v0x1e49200_0, 8, 4; + %movi 8, 1, 3; + %set/v v0x1e49280_0, 8, 3; + %delay 1000000, 0; + %vpi_call 2 386 "$display", "%b | %b | %b - SUB | %b | XXXX | %b | %b | %b | %b", v0x1e49000_0, v0x1e49200_0, v0x1e49280_0, v0x1e49300_0, v0x1e49580_0, v0x1e49600_0, v0x1e49400_0, v0x1e49100_0; + %movi 8, 4, 4; + %set/v v0x1e49000_0, 8, 4; + %movi 8, 2, 4; + %set/v v0x1e49200_0, 8, 4; + %movi 8, 3, 3; + %set/v v0x1e49280_0, 8, 3; + %delay 1000000, 0; + %vpi_call 2 392 "$display", "%b | %b | %b - SLT | %b | 0010 | %b | %b | %b | %b", v0x1e49000_0, v0x1e49200_0, v0x1e49280_0, v0x1e49300_0, v0x1e49580_0, v0x1e49600_0, v0x1e49400_0, v0x1e49100_0; + %movi 8, 9, 4; + %set/v v0x1e49000_0, 8, 4; + %movi 8, 5, 4; + %set/v v0x1e49200_0, 8, 4; + %movi 8, 3, 3; + %set/v v0x1e49280_0, 8, 3; + %delay 1000000, 0; + %vpi_call 2 396 "$display", "%b | %b | %b - SLT | %b | XXXX | %b | %b | %b | %b", v0x1e49000_0, v0x1e49200_0, v0x1e49280_0, v0x1e49300_0, v0x1e49580_0, v0x1e49600_0, v0x1e49400_0, v0x1e49100_0; + %set/v v0x1e49000_0, 0, 4; + %set/v v0x1e49200_0, 0, 4; + %movi 8, 3, 3; + %set/v v0x1e49280_0, 8, 3; + %delay 1000000, 0; + %vpi_call 2 401 "$display", "%b | %b | %b - SLT | %b | 0000 | %b | %b | %b | %b", v0x1e49000_0, v0x1e49200_0, v0x1e49280_0, v0x1e49300_0, v0x1e49580_0, v0x1e49600_0, v0x1e49400_0, v0x1e49100_0; + %end; + .thread T_0; +# The file index is used to find the file name in the following table. +:file_names 4; + "N/A"; + ""; + "testing.t.v"; + "./alu.v"; diff --git a/testing.t.v b/testing.t.v index 72ee8be..3cad459 100644 --- a/testing.t.v +++ b/testing.t.v @@ -128,7 +128,8 @@ wire [size-1:0] AddSubSLTSum; wire carryout; wire overflow; wire SLTflag; -wire ZeroFlag; +wire [size-1:0]ZeroFlag; +wire AllZeros; wire [size-1:0] subtract; reg [size-1:0] A, B; reg [2:0] Command; @@ -143,7 +144,7 @@ AndNand32 trial1(AndNandOut, A, B, Command); OrNorXor32 trial2(OrNorXorOut, A, B, Command); -Bitslice32 superalu(OneBitFinalOut, AddSubSLTSum, carryout, overflow, SLTflag, OrNorXorOut, AndNandOut, subtract, ZeroFlag, A, B, Command, carryin); +Bitslice32 superalu(OneBitFinalOut, AddSubSLTSum, carryout, overflow, SLTflag, OrNorXorOut, AndNandOut, subtract, ZeroFlag, AllZeros, A, B, Command, carryin); initial begin $display("Test 4 Bit Adder Functionality"); @@ -344,55 +345,60 @@ $display(" A | B |Command | Out |ExpectedOut | COut | OF |SLT|Zero" // Test AND // A = B | A = 1111 | AND = 1111 A=4'b1111;B=4'b1111;Command=3'b100; #1000 - $display("%b | %b | %b - AND | %b | 1111 | %b | %b | %b | %b", A, B, Command, OneBitFinalOut, carryout, overflow, SLTflag, ZeroFlag); + $display("%b | %b | %b - AND | %b | 1111 | %b | %b | %b | %b", A, B, Command, OneBitFinalOut, carryout, overflow, SLTflag, AllZeros); // Test NAND // A = 1111 | B = 0000 | NAND = 1111 A=4'b1111;B=4'b0000;Command=3'b101; #1000 - $display("%b | %b | %b - NAND | %b | 1111 | %b | %b | %b | %b", A, B, Command, OneBitFinalOut, carryout, overflow, SLTflag, ZeroFlag); + $display("%b | %b | %b - NAND | %b | 1111 | %b | %b | %b | %b", A, B, Command, OneBitFinalOut, carryout, overflow, SLTflag, AllZeros); // Test OR // A = 1111 | B = 0101 | OR = 1111 A=4'b1111; B=4'b0101; Command=3'b111; #1000 - $display("%b | %b | %b - OR | %b | 1111 | %b | %b | %b | %b", A, B, Command, OneBitFinalOut, carryout, overflow, SLTflag, ZeroFlag); + $display("%b | %b | %b - OR | %b | 1111 | %b | %b | %b | %b", A, B, Command, OneBitFinalOut, carryout, overflow, SLTflag, AllZeros); // Test NOR // A = 1011 | B = 0000 | NOR = 0100 A=4'b1011; B=4'b0000; Command=3'b110; #1000 - $display("%b | %b | %b - NOR | %b | 0100 | %b | %b | %b | %b", A, B, Command, OneBitFinalOut, carryout, overflow, SLTflag, ZeroFlag); + $display("%b | %b | %b - NOR | %b | 0100 | %b | %b | %b | %b", A, B, Command, OneBitFinalOut, carryout, overflow, SLTflag, AllZeros); // Test XOR // A = 1011 | B = 0000 | XOR = 1011 A=4'b1011; B=4'b0000; Command=3'b010; #1000 - $display("%b | %b | %b - XOR | %b | 1011 | %b | %b | %b | %b", A, B, Command, OneBitFinalOut, carryout, overflow, SLTflag, ZeroFlag); + $display("%b | %b | %b - XOR | %b | 1011 | %b | %b | %b | %b", A, B, Command, OneBitFinalOut, carryout, overflow, SLTflag, AllZeros); // Test ADD //Pos + Pos < 7 | 2 + 4 = 6 | 2 = 0010 | 4 = 0100 | 6 = 0110 | NO OVERFLOW A = 4'b0010; B = 4'b0100; Command =3'b000; #1000 - $display("%b | %b | %b - ADD | %b | 0110 | %b | %b | %b | %b", A, B, Command, OneBitFinalOut, carryout, overflow, SLTflag, ZeroFlag); + $display("%b | %b | %b - ADD | %b | 0110 | %b | %b | %b | %b", A, B, Command, OneBitFinalOut, carryout, overflow, SLTflag, AllZeros); //Neg + Neg < -8 | -5 + -4 = -9 | -5 = 1011 | -4 = 1100 | | OVERFLOW A = 4'b1011; B = 4'b1100; Command =3'b000; #1000 - $display("%b | %b | %b - ADD | %b | XXXX | %b | %b | %b | %b", A, B, Command, OneBitFinalOut, carryout, overflow, SLTflag, ZeroFlag); + $display("%b | %b | %b - ADD | %b | XXXX | %b | %b | %b | %b", A, B, Command, OneBitFinalOut, carryout, overflow, SLTflag, AllZeros); // Test SUB // A < B, A > 0 | B > 0 | No Overflow | A = 2 = 0010 | B = 4 = 0100 A = 4'b0010; B = 4'b0100; Command =3'b001; #1000 - $display("%b | %b | %b - SUB | %b | 1110 | %b | %b | %b | %b", A, B, Command, OneBitFinalOut, carryout, overflow, SLTflag, ZeroFlag); + $display("%b | %b | %b - SUB | %b | 1110 | %b | %b | %b | %b", A, B, Command, OneBitFinalOut, carryout, overflow, SLTflag, AllZeros); // A < B, A < 0 | B > 0 | Overflow | A = -7 = 1001 | B = 3 = 0011 A = 4'b1001; B = 4'b0011; Command =3'b001; #1000 - $display("%b | %b | %b - SUB | %b | XXXX | %b | %b | %b | %b", A, B, Command, OneBitFinalOut, carryout, overflow, SLTflag, ZeroFlag); + $display("%b | %b | %b - SUB | %b | XXXX | %b | %b | %b | %b", A, B, Command, OneBitFinalOut, carryout, overflow, SLTflag, AllZeros); // Test SLT // A > B, A > 0 | B > 0 | No Overflow | A = 4 = 0100 | B = 2 = 0010 A = 4'b0100; B = 4'b0010; Command =3'b011; #1000 - $display("%b | %b | %b - SLT | %b | 0010 | %b | %b | %b | %b", A, B, Command, OneBitFinalOut, carryout, overflow, SLTflag, ZeroFlag); + $display("%b | %b | %b - SLT | %b | 0010 | %b | %b | %b | %b", A, B, Command, OneBitFinalOut, carryout, overflow, SLTflag, AllZeros); // A < B, A < 0 | B > 0 | Overflow | A = -7 = 1001 | B = 5 = 0101 A = 4'b1001; B = 4'b0101; Command =3'b011; #1000 - $display("%b | %b | %b - SLT | %b | XXXX | %b | %b | %b | %b", A, B, Command, OneBitFinalOut, carryout, overflow, SLTflag, ZeroFlag); + $display("%b | %b | %b - SLT | %b | XXXX | %b | %b | %b | %b", A, B, Command, OneBitFinalOut, carryout, overflow, SLTflag, AllZeros); + +// Test Zero +// A = B, A = 0 | B = 0 | No Overflow +A = 4'b0000; B = 4'b0000; Command =3'b011; #1000 + $display("%b | %b | %b - SLT | %b | 0000 | %b | %b | %b | %b", A, B, Command, OneBitFinalOut, carryout, overflow, SLTflag, AllZeros); end endmodule From d0a7b7a226477450292904bb5a403766a0f70c33 Mon Sep 17 00:00:00 2001 From: mjakus Date: Tue, 10 Oct 2017 08:29:08 -0400 Subject: [PATCH 16/28] Added zeros test cases --- test | 4260 ++++++++++++++++++++++++++------------------------- testing.t.v | 29 +- 2 files changed, 2181 insertions(+), 2108 deletions(-) diff --git a/test b/test index 24c16d3..1fb5990 100755 --- a/test +++ b/test @@ -4,2289 +4,2337 @@ :vpi_module "system"; :vpi_module "v2005_math"; :vpi_module "va_math"; -S_0x1da9580 .scope module, "test32Adder" "test32Adder" 2 122; - .timescale -9 -12; -P_0x1d46268 .param/l "size" 2 123, +C4<0100>; -v0x1e49000_0 .var "A", 3 0; -RS_0x7f060963abe8/0/0 .resolv tri, L_0x1e4a7f0, L_0x1e4bee0, L_0x1e4d420, L_0x1e4ea20; -RS_0x7f060963abe8/0/4 .resolv tri, L_0x1e60860, L_0x1e61c80, L_0x1e63080, L_0x1e645a0; -RS_0x7f060963abe8 .resolv tri, RS_0x7f060963abe8/0/0, RS_0x7f060963abe8/0/4, C4, C4; -v0x1e49080_0 .net8 "AddSubSLTSum", 3 0, RS_0x7f060963abe8; 8 drivers -v0x1e49100_0 .net "AllZeros", 0 0, L_0x1e6fdf0; 1 drivers -RS_0x7f0609639e38/0/0 .resolv tri, L_0x1e509d0, L_0x1e51480, L_0x1e51ef0, L_0x1e52950; -RS_0x7f0609639e38/0/4 .resolv tri, L_0x1e663d0, L_0x1e66e40, L_0x1e678b0, L_0x1e68410; -RS_0x7f0609639e38 .resolv tri, RS_0x7f0609639e38/0/0, RS_0x7f0609639e38/0/4, C4, C4; -v0x1e49180_0 .net8 "AndNandOut", 3 0, RS_0x7f0609639e38; 8 drivers -v0x1e49200_0 .var "B", 3 0; -v0x1e49280_0 .var "Command", 2 0; -RS_0x7f060963b068 .resolv tri, L_0x1e59a40, L_0x1e5c690, L_0x1e5f2c0, L_0x1e6f260; -v0x1e49300_0 .net8 "OneBitFinalOut", 3 0, RS_0x7f060963b068; 4 drivers -RS_0x7f0609639748/0/0 .resolv tri, L_0x1e53ca0, L_0x1e55200, L_0x1e56500, L_0x1e577b0; -RS_0x7f0609639748/0/4 .resolv tri, L_0x1e69760, L_0x1e6aa60, L_0x1e6bd60, L_0x1e6d050; -RS_0x7f0609639748 .resolv tri, RS_0x7f0609639748/0/0, RS_0x7f0609639748/0/4, C4, C4; -v0x1e49380_0 .net8 "OrNorXorOut", 3 0, RS_0x7f0609639748; 8 drivers -RS_0x7f060963aca8 .resolv tri, L_0x1e50050, L_0x1e65a70, C4, C4; -v0x1e49400_0 .net8 "SLTflag", 0 0, RS_0x7f060963aca8; 2 drivers -RS_0x7f060963b098 .resolv tri, L_0x1e59ef0, L_0x1e5cb60, L_0x1e5f400, L_0x1e6f520; -v0x1e49480_0 .net8 "ZeroFlag", 3 0, RS_0x7f060963b098; 4 drivers -v0x1e49500_0 .var "carryin", 3 0; -RS_0x7f060963aee8 .resolv tri, L_0x1e4aad0, L_0x1e64920, C4, C4; -v0x1e49580_0 .net8 "carryout", 0 0, RS_0x7f060963aee8; 2 drivers -RS_0x7f060963af78 .resolv tri, L_0x1e4f320, L_0x1e64d90, C4, C4; -v0x1e49600_0 .net8 "overflow", 0 0, RS_0x7f060963af78; 2 drivers -RS_0x7f060963afa8/0/0 .resolv tri, L_0x1e4aa30, L_0x1e4c110, L_0x1e4d680, L_0x1e4da70; -RS_0x7f060963afa8/0/4 .resolv tri, L_0x1e60a40, L_0x1e61eb0, L_0x1e632e0, L_0x1e636d0; -RS_0x7f060963afa8 .resolv tri, RS_0x7f060963afa8/0/0, RS_0x7f060963afa8/0/4, C4, C4; -v0x1e49680_0 .net8 "subtract", 3 0, RS_0x7f060963afa8; 8 drivers -S_0x1e43820 .scope module, "trial" "AddSubSLT32" 2 141, 3 205, S_0x1da9580; - .timescale -9 -12; -P_0x1e43918 .param/l "size" 3 228, +C4<0100>; -L_0x1e4aad0/d .functor OR 1, L_0x1e4f170, C4<0>, C4<0>, C4<0>; -L_0x1e4aad0 .delay (20000,20000,20000) L_0x1e4aad0/d; -L_0x1e4f320/d .functor XOR 1, RS_0x7f060963aee8, L_0x1e4f450, C4<0>, C4<0>; -L_0x1e4f320 .delay (40000,40000,40000) L_0x1e4f320/d; -L_0x1e4f0a0/d .functor AND 1, L_0x1e4f620, L_0x1e4f6c0, C4<1>, C4<1>; -L_0x1e4f0a0 .delay (20000,20000,20000) L_0x1e4f0a0/d; -L_0x1e4f4f0/d .functor NOT 1, RS_0x7f060963af78, C4<0>, C4<0>, C4<0>; -L_0x1e4f4f0 .delay (10000,10000,10000) L_0x1e4f4f0/d; -L_0x1e4f8f0/d .functor NOT 1, L_0x1e4f950, C4<0>, C4<0>, C4<0>; -L_0x1e4f8f0 .delay (10000,10000,10000) L_0x1e4f8f0/d; -L_0x1e4a890/d .functor AND 1, L_0x1e4f4f0, L_0x1e4fc20, C4<1>, C4<1>; -L_0x1e4a890 .delay (20000,20000,20000) L_0x1e4a890/d; -L_0x1e4f7b0/d .functor AND 1, RS_0x7f060963af78, L_0x1e4f8f0, C4<1>, C4<1>; -L_0x1e4f7b0 .delay (20000,20000,20000) L_0x1e4f7b0/d; -L_0x1e4fe10/d .functor AND 1, L_0x1e4a890, L_0x1e4f0a0, C4<1>, C4<1>; -L_0x1e4fe10 .delay (20000,20000,20000) L_0x1e4fe10/d; -L_0x1e4ff50/d .functor AND 1, L_0x1e4f7b0, L_0x1e4f0a0, C4<1>, C4<1>; -L_0x1e4ff50 .delay (20000,20000,20000) L_0x1e4ff50/d; -L_0x1e50050/d .functor OR 1, L_0x1e4fe10, L_0x1e4ff50, C4<0>, C4<0>; -L_0x1e50050 .delay (20000,20000,20000) L_0x1e50050/d; -v0x1e47f20_0 .net "A", 3 0, v0x1e49000_0; 1 drivers -v0x1e47fc0_0 .alias "AddSubSLTSum", 3 0, v0x1e49080_0; -v0x1e48040_0 .net "B", 3 0, v0x1e49200_0; 1 drivers -RS_0x7f060963d348 .resolv tri, L_0x1e4a940, L_0x1e4bfd0, L_0x1e4d510, L_0x1e4eb10; -v0x1e480c0_0 .net8 "CarryoutWire", 3 0, RS_0x7f060963d348; 4 drivers -v0x1e48140_0 .net "Command", 2 0, v0x1e49280_0; 1 drivers -v0x1e481c0_0 .net "Res0OF1", 0 0, L_0x1e4f7b0; 1 drivers -v0x1e48260_0 .net "Res1OF0", 0 0, L_0x1e4a890; 1 drivers -v0x1e48300_0 .alias "SLTflag", 0 0, v0x1e49400_0; -v0x1e48420_0 .net "SLTflag0", 0 0, L_0x1e4fe10; 1 drivers -v0x1e484c0_0 .net "SLTflag1", 0 0, L_0x1e4ff50; 1 drivers -v0x1e48560_0 .net "SLTon", 0 0, L_0x1e4f0a0; 1 drivers -v0x1e48600_0 .net *"_s40", 0 0, L_0x1e4f170; 1 drivers -v0x1e486a0_0 .net/s *"_s41", 0 0, C4<0>; 1 drivers -v0x1e48740_0 .net *"_s44", 0 0, L_0x1e4f450; 1 drivers -v0x1e48860_0 .net *"_s46", 0 0, L_0x1e4f620; 1 drivers -v0x1e48900_0 .net *"_s48", 0 0, L_0x1e4f6c0; 1 drivers -v0x1e487c0_0 .net *"_s50", 0 0, L_0x1e4f950; 1 drivers -v0x1e48a50_0 .net *"_s52", 0 0, L_0x1e4fc20; 1 drivers -v0x1e48b70_0 .net "carryin", 3 0, v0x1e49500_0; 1 drivers -v0x1e48bf0_0 .alias "carryout", 0 0, v0x1e49580_0; -v0x1e48ad0_0 .net "nAddSubSLTSum", 0 0, L_0x1e4f8f0; 1 drivers -v0x1e48d20_0 .net "nOF", 0 0, L_0x1e4f4f0; 1 drivers -v0x1e48c70_0 .alias "overflow", 0 0, v0x1e49600_0; -v0x1e48eb0_0 .alias "subtract", 3 0, v0x1e49680_0; -L_0x1e4a7f0 .part/pv L_0x1e4a360, 1, 1, 4; -L_0x1e4a940 .part/pv L_0x1e4a6b0, 1, 1, 4; -L_0x1e4aa30 .part/pv L_0x1e3c880, 1, 1, 4; -L_0x1e4ab60 .part v0x1e49000_0, 1, 1; -L_0x1e4ad10 .part v0x1e49200_0, 1, 1; -L_0x1e4aec0 .part RS_0x7f060963d348, 0, 1; -L_0x1e4bee0 .part/pv L_0x1e4ba10, 2, 1, 4; -L_0x1e4bfd0 .part/pv L_0x1e4bd80, 2, 1, 4; -L_0x1e4c110 .part/pv L_0x1e4b740, 2, 1, 4; -L_0x1e4c200 .part v0x1e49000_0, 2, 1; -L_0x1e4c300 .part v0x1e49200_0, 2, 1; -L_0x1e4c430 .part RS_0x7f060963d348, 1, 1; -L_0x1e4d420 .part/pv L_0x1e4cf70, 3, 1, 4; -L_0x1e4d510 .part/pv L_0x1e4d2c0, 3, 1, 4; -L_0x1e4d680 .part/pv L_0x1e4cca0, 3, 1, 4; -L_0x1e4d770 .part v0x1e49000_0, 3, 1; -L_0x1e4d8a0 .part v0x1e49200_0, 3, 1; -L_0x1e4d9d0 .part RS_0x7f060963d348, 2, 1; -L_0x1e4ea20 .part/pv L_0x1e4e570, 0, 1, 4; -L_0x1e4eb10 .part/pv L_0x1e4e8c0, 0, 1, 4; -L_0x1e4da70 .part/pv L_0x1e4e2a0, 0, 1, 4; -L_0x1e4ed00 .part v0x1e49000_0, 0, 1; -L_0x1e4ec00 .part v0x1e49200_0, 0, 1; -L_0x1e4eef0 .part RS_0x7f060963afa8, 0, 1; -L_0x1e4f170 .part RS_0x7f060963d348, 3, 1; -L_0x1e4f450 .part RS_0x7f060963d348, 2, 1; -L_0x1e4f620 .part v0x1e49280_0, 1, 1; -L_0x1e4f6c0 .part RS_0x7f060963afa8, 0, 1; -L_0x1e4f950 .part RS_0x7f060963abe8, 3, 1; -L_0x1e4fc20 .part RS_0x7f060963abe8, 3, 1; -S_0x1e46f10 .scope module, "attempt2" "MiddleAddSubSLT" 3 225, 3 89, S_0x1e43820; - .timescale -9 -12; -L_0x1e4d810/d .functor NOT 1, L_0x1e4ec00, C4<0>, C4<0>, C4<0>; -L_0x1e4d810 .delay (10000,10000,10000) L_0x1e4d810/d; -L_0x1e4e140/d .functor NOT 1, L_0x1e4e200, C4<0>, C4<0>, C4<0>; -L_0x1e4e140 .delay (10000,10000,10000) L_0x1e4e140/d; -L_0x1e4e2a0/d .functor AND 1, L_0x1e4e3e0, L_0x1e4e140, C4<1>, C4<1>; -L_0x1e4e2a0 .delay (20000,20000,20000) L_0x1e4e2a0/d; -L_0x1e4e480/d .functor XOR 1, L_0x1e4ed00, L_0x1e4ded0, C4<0>, C4<0>; -L_0x1e4e480 .delay (40000,40000,40000) L_0x1e4e480/d; -L_0x1e4e570/d .functor XOR 1, L_0x1e4e480, L_0x1e4eef0, C4<0>, C4<0>; -L_0x1e4e570 .delay (40000,40000,40000) L_0x1e4e570/d; -L_0x1e4e660/d .functor AND 1, L_0x1e4ed00, L_0x1e4ded0, C4<1>, C4<1>; -L_0x1e4e660 .delay (20000,20000,20000) L_0x1e4e660/d; -L_0x1e4e7d0/d .functor AND 1, L_0x1e4e480, L_0x1e4eef0, C4<1>, C4<1>; -L_0x1e4e7d0 .delay (20000,20000,20000) L_0x1e4e7d0/d; -L_0x1e4e8c0/d .functor OR 1, L_0x1e4e660, L_0x1e4e7d0, C4<0>, C4<0>; -L_0x1e4e8c0 .delay (20000,20000,20000) L_0x1e4e8c0/d; -v0x1e47580_0 .net "A", 0 0, L_0x1e4ed00; 1 drivers -v0x1e47640_0 .net "AandB", 0 0, L_0x1e4e660; 1 drivers -v0x1e476e0_0 .net "AddSubSLTSum", 0 0, L_0x1e4e570; 1 drivers -v0x1e47780_0 .net "AxorB", 0 0, L_0x1e4e480; 1 drivers -v0x1e47800_0 .net "B", 0 0, L_0x1e4ec00; 1 drivers -v0x1e478b0_0 .net "BornB", 0 0, L_0x1e4ded0; 1 drivers -v0x1e47970_0 .net "CINandAxorB", 0 0, L_0x1e4e7d0; 1 drivers -v0x1e479f0_0 .alias "Command", 2 0, v0x1e48140_0; -v0x1e47a70_0 .net *"_s3", 0 0, L_0x1e4e200; 1 drivers -v0x1e47af0_0 .net *"_s5", 0 0, L_0x1e4e3e0; 1 drivers -v0x1e47b90_0 .net "carryin", 0 0, L_0x1e4eef0; 1 drivers -v0x1e47c30_0 .net "carryout", 0 0, L_0x1e4e8c0; 1 drivers -v0x1e47cd0_0 .net "nB", 0 0, L_0x1e4d810; 1 drivers -v0x1e47d80_0 .net "nCmd2", 0 0, L_0x1e4e140; 1 drivers -v0x1e47e80_0 .net "subtract", 0 0, L_0x1e4e2a0; 1 drivers -L_0x1e4e0a0 .part v0x1e49280_0, 0, 1; -L_0x1e4e200 .part v0x1e49280_0, 2, 1; -L_0x1e4e3e0 .part v0x1e49280_0, 0, 1; -S_0x1e47000 .scope module, "mux0" "TwoInMux" 3 105, 3 8, S_0x1e46f10; - .timescale -9 -12; -L_0x1e4dbf0/d .functor NOT 1, L_0x1e4e0a0, C4<0>, C4<0>, C4<0>; -L_0x1e4dbf0 .delay (10000,10000,10000) L_0x1e4dbf0/d; -L_0x1e4dcb0/d .functor AND 1, L_0x1e4ec00, L_0x1e4dbf0, C4<1>, C4<1>; -L_0x1e4dcb0 .delay (20000,20000,20000) L_0x1e4dcb0/d; -L_0x1e4ddc0/d .functor AND 1, L_0x1e4d810, L_0x1e4e0a0, C4<1>, C4<1>; -L_0x1e4ddc0 .delay (20000,20000,20000) L_0x1e4ddc0/d; -L_0x1e4ded0/d .functor OR 1, L_0x1e4dcb0, L_0x1e4ddc0, C4<0>, C4<0>; -L_0x1e4ded0 .delay (20000,20000,20000) L_0x1e4ded0/d; -v0x1e470f0_0 .net "S", 0 0, L_0x1e4e0a0; 1 drivers -v0x1e471b0_0 .alias "in0", 0 0, v0x1e47800_0; -v0x1e47250_0 .alias "in1", 0 0, v0x1e47cd0_0; -v0x1e472f0_0 .net "nS", 0 0, L_0x1e4dbf0; 1 drivers -v0x1e473a0_0 .net "out0", 0 0, L_0x1e4dcb0; 1 drivers -v0x1e47440_0 .net "out1", 0 0, L_0x1e4ddc0; 1 drivers -v0x1e474e0_0 .alias "outfinal", 0 0, v0x1e478b0_0; -S_0x1e45d70 .scope generate, "addbits[1]" "addbits[1]" 3 230, 3 230, S_0x1e43820; - .timescale -9 -12; -P_0x1e45788 .param/l "i" 3 230, +C4<01>; -S_0x1e45ee0 .scope module, "attempt" "MiddleAddSubSLT" 3 232, 3 89, S_0x1e45d70; - .timescale -9 -12; -L_0x1e44750/d .functor NOT 1, L_0x1e4ad10, C4<0>, C4<0>, C4<0>; -L_0x1e44750 .delay (10000,10000,10000) L_0x1e44750/d; -L_0x1e48df0/d .functor NOT 1, L_0x1e3c7e0, C4<0>, C4<0>, C4<0>; -L_0x1e48df0 .delay (10000,10000,10000) L_0x1e48df0/d; -L_0x1e3c880/d .functor AND 1, L_0x1e4a1d0, L_0x1e48df0, C4<1>, C4<1>; -L_0x1e3c880 .delay (20000,20000,20000) L_0x1e3c880/d; -L_0x1e4a270/d .functor XOR 1, L_0x1e4ab60, L_0x1e49b50, C4<0>, C4<0>; -L_0x1e4a270 .delay (40000,40000,40000) L_0x1e4a270/d; -L_0x1e4a360/d .functor XOR 1, L_0x1e4a270, L_0x1e4aec0, C4<0>, C4<0>; -L_0x1e4a360 .delay (40000,40000,40000) L_0x1e4a360/d; -L_0x1e4a450/d .functor AND 1, L_0x1e4ab60, L_0x1e49b50, C4<1>, C4<1>; -L_0x1e4a450 .delay (20000,20000,20000) L_0x1e4a450/d; -L_0x1e4a5c0/d .functor AND 1, L_0x1e4a270, L_0x1e4aec0, C4<1>, C4<1>; -L_0x1e4a5c0 .delay (20000,20000,20000) L_0x1e4a5c0/d; -L_0x1e4a6b0/d .functor OR 1, L_0x1e4a450, L_0x1e4a5c0, C4<0>, C4<0>; -L_0x1e4a6b0 .delay (20000,20000,20000) L_0x1e4a6b0/d; -v0x1e46570_0 .net "A", 0 0, L_0x1e4ab60; 1 drivers -v0x1e46630_0 .net "AandB", 0 0, L_0x1e4a450; 1 drivers -v0x1e466d0_0 .net "AddSubSLTSum", 0 0, L_0x1e4a360; 1 drivers -v0x1e46770_0 .net "AxorB", 0 0, L_0x1e4a270; 1 drivers -v0x1e467f0_0 .net "B", 0 0, L_0x1e4ad10; 1 drivers -v0x1e468a0_0 .net "BornB", 0 0, L_0x1e49b50; 1 drivers -v0x1e46960_0 .net "CINandAxorB", 0 0, L_0x1e4a5c0; 1 drivers -v0x1e469e0_0 .alias "Command", 2 0, v0x1e48140_0; -v0x1e46a60_0 .net *"_s3", 0 0, L_0x1e3c7e0; 1 drivers -v0x1e46ae0_0 .net *"_s5", 0 0, L_0x1e4a1d0; 1 drivers -v0x1e46b80_0 .net "carryin", 0 0, L_0x1e4aec0; 1 drivers -v0x1e46c20_0 .net "carryout", 0 0, L_0x1e4a6b0; 1 drivers -v0x1e46cc0_0 .net "nB", 0 0, L_0x1e44750; 1 drivers -v0x1e46d70_0 .net "nCmd2", 0 0, L_0x1e48df0; 1 drivers -v0x1e46e70_0 .net "subtract", 0 0, L_0x1e3c880; 1 drivers -L_0x1e49d20 .part v0x1e49280_0, 0, 1; -L_0x1e3c7e0 .part v0x1e49280_0, 2, 1; -L_0x1e4a1d0 .part v0x1e49280_0, 0, 1; -S_0x1e45fd0 .scope module, "mux0" "TwoInMux" 3 105, 3 8, S_0x1e45ee0; - .timescale -9 -12; -L_0x1e49870/d .functor NOT 1, L_0x1e49d20, C4<0>, C4<0>, C4<0>; -L_0x1e49870 .delay (10000,10000,10000) L_0x1e49870/d; -L_0x1e49930/d .functor AND 1, L_0x1e4ad10, L_0x1e49870, C4<1>, C4<1>; -L_0x1e49930 .delay (20000,20000,20000) L_0x1e49930/d; -L_0x1e49a40/d .functor AND 1, L_0x1e44750, L_0x1e49d20, C4<1>, C4<1>; -L_0x1e49a40 .delay (20000,20000,20000) L_0x1e49a40/d; -L_0x1e49b50/d .functor OR 1, L_0x1e49930, L_0x1e49a40, C4<0>, C4<0>; -L_0x1e49b50 .delay (20000,20000,20000) L_0x1e49b50/d; -v0x1e460c0_0 .net "S", 0 0, L_0x1e49d20; 1 drivers -v0x1e46160_0 .alias "in0", 0 0, v0x1e467f0_0; -v0x1e46200_0 .alias "in1", 0 0, v0x1e46cc0_0; -v0x1e462a0_0 .net "nS", 0 0, L_0x1e49870; 1 drivers -v0x1e46350_0 .net "out0", 0 0, L_0x1e49930; 1 drivers -v0x1e463f0_0 .net "out1", 0 0, L_0x1e49a40; 1 drivers -v0x1e464d0_0 .alias "outfinal", 0 0, v0x1e468a0_0; -S_0x1e44bd0 .scope generate, "addbits[2]" "addbits[2]" 3 230, 3 230, S_0x1e43820; - .timescale -9 -12; -P_0x1e44518 .param/l "i" 3 230, +C4<010>; -S_0x1e44d40 .scope module, "attempt" "MiddleAddSubSLT" 3 232, 3 89, S_0x1e44bd0; - .timescale -9 -12; -L_0x1e40590/d .functor NOT 1, L_0x1e4c300, C4<0>, C4<0>, C4<0>; -L_0x1e40590 .delay (10000,10000,10000) L_0x1e40590/d; -L_0x1e4b5e0/d .functor NOT 1, L_0x1e4b6a0, C4<0>, C4<0>, C4<0>; -L_0x1e4b5e0 .delay (10000,10000,10000) L_0x1e4b5e0/d; -L_0x1e4b740/d .functor AND 1, L_0x1e4b880, L_0x1e4b5e0, C4<1>, C4<1>; -L_0x1e4b740 .delay (20000,20000,20000) L_0x1e4b740/d; -L_0x1e4b920/d .functor XOR 1, L_0x1e4c200, L_0x1e4b370, C4<0>, C4<0>; -L_0x1e4b920 .delay (40000,40000,40000) L_0x1e4b920/d; -L_0x1e4ba10/d .functor XOR 1, L_0x1e4b920, L_0x1e4c430, C4<0>, C4<0>; -L_0x1e4ba10 .delay (40000,40000,40000) L_0x1e4ba10/d; -L_0x1e4bb00/d .functor AND 1, L_0x1e4c200, L_0x1e4b370, C4<1>, C4<1>; -L_0x1e4bb00 .delay (20000,20000,20000) L_0x1e4bb00/d; -L_0x1e4bc70/d .functor AND 1, L_0x1e4b920, L_0x1e4c430, C4<1>, C4<1>; -L_0x1e4bc70 .delay (20000,20000,20000) L_0x1e4bc70/d; -L_0x1e4bd80/d .functor OR 1, L_0x1e4bb00, L_0x1e4bc70, C4<0>, C4<0>; -L_0x1e4bd80 .delay (20000,20000,20000) L_0x1e4bd80/d; -v0x1e453d0_0 .net "A", 0 0, L_0x1e4c200; 1 drivers -v0x1e45490_0 .net "AandB", 0 0, L_0x1e4bb00; 1 drivers -v0x1e45530_0 .net "AddSubSLTSum", 0 0, L_0x1e4ba10; 1 drivers -v0x1e455d0_0 .net "AxorB", 0 0, L_0x1e4b920; 1 drivers -v0x1e45650_0 .net "B", 0 0, L_0x1e4c300; 1 drivers -v0x1e45700_0 .net "BornB", 0 0, L_0x1e4b370; 1 drivers -v0x1e457c0_0 .net "CINandAxorB", 0 0, L_0x1e4bc70; 1 drivers -v0x1e45840_0 .alias "Command", 2 0, v0x1e48140_0; -v0x1e458c0_0 .net *"_s3", 0 0, L_0x1e4b6a0; 1 drivers -v0x1e45940_0 .net *"_s5", 0 0, L_0x1e4b880; 1 drivers -v0x1e459e0_0 .net "carryin", 0 0, L_0x1e4c430; 1 drivers -v0x1e45a80_0 .net "carryout", 0 0, L_0x1e4bd80; 1 drivers -v0x1e45b20_0 .net "nB", 0 0, L_0x1e40590; 1 drivers -v0x1e45bd0_0 .net "nCmd2", 0 0, L_0x1e4b5e0; 1 drivers -v0x1e45cd0_0 .net "subtract", 0 0, L_0x1e4b740; 1 drivers -L_0x1e4b540 .part v0x1e49280_0, 0, 1; -L_0x1e4b6a0 .part v0x1e49280_0, 2, 1; -L_0x1e4b880 .part v0x1e49280_0, 0, 1; -S_0x1e44e30 .scope module, "mux0" "TwoInMux" 3 105, 3 8, S_0x1e44d40; - .timescale -9 -12; -L_0x1e4b090/d .functor NOT 1, L_0x1e4b540, C4<0>, C4<0>, C4<0>; -L_0x1e4b090 .delay (10000,10000,10000) L_0x1e4b090/d; -L_0x1e4b150/d .functor AND 1, L_0x1e4c300, L_0x1e4b090, C4<1>, C4<1>; -L_0x1e4b150 .delay (20000,20000,20000) L_0x1e4b150/d; -L_0x1e4b260/d .functor AND 1, L_0x1e40590, L_0x1e4b540, C4<1>, C4<1>; -L_0x1e4b260 .delay (20000,20000,20000) L_0x1e4b260/d; -L_0x1e4b370/d .functor OR 1, L_0x1e4b150, L_0x1e4b260, C4<0>, C4<0>; -L_0x1e4b370 .delay (20000,20000,20000) L_0x1e4b370/d; -v0x1e44f20_0 .net "S", 0 0, L_0x1e4b540; 1 drivers -v0x1e44fc0_0 .alias "in0", 0 0, v0x1e45650_0; -v0x1e45060_0 .alias "in1", 0 0, v0x1e45b20_0; -v0x1e45100_0 .net "nS", 0 0, L_0x1e4b090; 1 drivers -v0x1e451b0_0 .net "out0", 0 0, L_0x1e4b150; 1 drivers -v0x1e45250_0 .net "out1", 0 0, L_0x1e4b260; 1 drivers -v0x1e45330_0 .alias "outfinal", 0 0, v0x1e45700_0; -S_0x1e43990 .scope generate, "addbits[3]" "addbits[3]" 3 230, 3 230, S_0x1e43820; - .timescale -9 -12; -P_0x1e43a88 .param/l "i" 3 230, +C4<011>; -S_0x1e43b00 .scope module, "attempt" "MiddleAddSubSLT" 3 232, 3 89, S_0x1e43990; - .timescale -9 -12; -L_0x1e4c2a0/d .functor NOT 1, L_0x1e4d8a0, C4<0>, C4<0>, C4<0>; -L_0x1e4c2a0 .delay (10000,10000,10000) L_0x1e4c2a0/d; -L_0x1e4cb40/d .functor NOT 1, L_0x1e4cc00, C4<0>, C4<0>, C4<0>; -L_0x1e4cb40 .delay (10000,10000,10000) L_0x1e4cb40/d; -L_0x1e4cca0/d .functor AND 1, L_0x1e4cde0, L_0x1e4cb40, C4<1>, C4<1>; -L_0x1e4cca0 .delay (20000,20000,20000) L_0x1e4cca0/d; -L_0x1e4ce80/d .functor XOR 1, L_0x1e4d770, L_0x1e4c8d0, C4<0>, C4<0>; -L_0x1e4ce80 .delay (40000,40000,40000) L_0x1e4ce80/d; -L_0x1e4cf70/d .functor XOR 1, L_0x1e4ce80, L_0x1e4d9d0, C4<0>, C4<0>; -L_0x1e4cf70 .delay (40000,40000,40000) L_0x1e4cf70/d; -L_0x1e4d060/d .functor AND 1, L_0x1e4d770, L_0x1e4c8d0, C4<1>, C4<1>; -L_0x1e4d060 .delay (20000,20000,20000) L_0x1e4d060/d; -L_0x1e4d1d0/d .functor AND 1, L_0x1e4ce80, L_0x1e4d9d0, C4<1>, C4<1>; -L_0x1e4d1d0 .delay (20000,20000,20000) L_0x1e4d1d0/d; -L_0x1e4d2c0/d .functor OR 1, L_0x1e4d060, L_0x1e4d1d0, C4<0>, C4<0>; -L_0x1e4d2c0 .delay (20000,20000,20000) L_0x1e4d2c0/d; -v0x1e44160_0 .net "A", 0 0, L_0x1e4d770; 1 drivers -v0x1e44220_0 .net "AandB", 0 0, L_0x1e4d060; 1 drivers -v0x1e442c0_0 .net "AddSubSLTSum", 0 0, L_0x1e4cf70; 1 drivers -v0x1e44360_0 .net "AxorB", 0 0, L_0x1e4ce80; 1 drivers -v0x1e443e0_0 .net "B", 0 0, L_0x1e4d8a0; 1 drivers -v0x1e44490_0 .net "BornB", 0 0, L_0x1e4c8d0; 1 drivers -v0x1e44550_0 .net "CINandAxorB", 0 0, L_0x1e4d1d0; 1 drivers -v0x1e445d0_0 .alias "Command", 2 0, v0x1e48140_0; -v0x1e44650_0 .net *"_s3", 0 0, L_0x1e4cc00; 1 drivers -v0x1e446d0_0 .net *"_s5", 0 0, L_0x1e4cde0; 1 drivers -v0x1e447d0_0 .net "carryin", 0 0, L_0x1e4d9d0; 1 drivers -v0x1e44870_0 .net "carryout", 0 0, L_0x1e4d2c0; 1 drivers -v0x1e44980_0 .net "nB", 0 0, L_0x1e4c2a0; 1 drivers -v0x1e44a30_0 .net "nCmd2", 0 0, L_0x1e4cb40; 1 drivers -v0x1e44b30_0 .net "subtract", 0 0, L_0x1e4cca0; 1 drivers -L_0x1e4caa0 .part v0x1e49280_0, 0, 1; -L_0x1e4cc00 .part v0x1e49280_0, 2, 1; -L_0x1e4cde0 .part v0x1e49280_0, 0, 1; -S_0x1e43bf0 .scope module, "mux0" "TwoInMux" 3 105, 3 8, S_0x1e43b00; - .timescale -9 -12; -L_0x1e4c630/d .functor NOT 1, L_0x1e4caa0, C4<0>, C4<0>, C4<0>; -L_0x1e4c630 .delay (10000,10000,10000) L_0x1e4c630/d; -L_0x1e4c6b0/d .functor AND 1, L_0x1e4d8a0, L_0x1e4c630, C4<1>, C4<1>; -L_0x1e4c6b0 .delay (20000,20000,20000) L_0x1e4c6b0/d; -L_0x1e4c7c0/d .functor AND 1, L_0x1e4c2a0, L_0x1e4caa0, C4<1>, C4<1>; -L_0x1e4c7c0 .delay (20000,20000,20000) L_0x1e4c7c0/d; -L_0x1e4c8d0/d .functor OR 1, L_0x1e4c6b0, L_0x1e4c7c0, C4<0>, C4<0>; -L_0x1e4c8d0 .delay (20000,20000,20000) L_0x1e4c8d0/d; -v0x1e43ce0_0 .net "S", 0 0, L_0x1e4caa0; 1 drivers -v0x1e43d80_0 .alias "in0", 0 0, v0x1e443e0_0; -v0x1e43e20_0 .alias "in1", 0 0, v0x1e44980_0; -v0x1e43ec0_0 .net "nS", 0 0, L_0x1e4c630; 1 drivers -v0x1e43f40_0 .net "out0", 0 0, L_0x1e4c6b0; 1 drivers -v0x1e43fe0_0 .net "out1", 0 0, L_0x1e4c7c0; 1 drivers -v0x1e440c0_0 .alias "outfinal", 0 0, v0x1e44490_0; -S_0x1e40720 .scope module, "trial1" "AndNand32" 2 143, 3 154, S_0x1da9580; - .timescale -9 -12; -P_0x1e40818 .param/l "size" 3 161, +C4<0100>; -v0x1e43620_0 .alias "A", 3 0, v0x1e47f20_0; -v0x1e436a0_0 .alias "AndNandOut", 3 0, v0x1e49180_0; -v0x1e43720_0 .alias "B", 3 0, v0x1e48040_0; -v0x1e437a0_0 .alias "Command", 2 0, v0x1e48140_0; -L_0x1e509d0 .part/pv L_0x1e50760, 1, 1, 4; -L_0x1e50b20 .part v0x1e49000_0, 1, 1; -L_0x1e50bc0 .part v0x1e49200_0, 1, 1; -L_0x1e51480 .part/pv L_0x1e51210, 2, 1, 4; -L_0x1e51520 .part v0x1e49000_0, 2, 1; -L_0x1e515c0 .part v0x1e49200_0, 2, 1; -L_0x1e51ef0 .part/pv L_0x1e51c80, 3, 1, 4; -L_0x1e51f90 .part v0x1e49000_0, 3, 1; -L_0x1e52080 .part v0x1e49200_0, 3, 1; -L_0x1e52950 .part/pv L_0x1e526e0, 0, 1, 4; -L_0x1e52a50 .part v0x1e49000_0, 0, 1; -L_0x1e52af0 .part v0x1e49200_0, 0, 1; -S_0x1e42bf0 .scope module, "attempt2" "AndNand" 3 165, 3 48, S_0x1e40720; - .timescale -9 -12; -L_0x1e52170/d .functor NAND 1, L_0x1e52a50, L_0x1e52af0, C4<1>, C4<1>; -L_0x1e52170 .delay (10000,10000,10000) L_0x1e52170/d; -L_0x1e52290/d .functor NOT 1, L_0x1e52170, C4<0>, C4<0>, C4<0>; -L_0x1e52290 .delay (10000,10000,10000) L_0x1e52290/d; -v0x1e43210_0 .net "A", 0 0, L_0x1e52a50; 1 drivers -v0x1e432d0_0 .net "AandB", 0 0, L_0x1e52290; 1 drivers -v0x1e43350_0 .net "AnandB", 0 0, L_0x1e52170; 1 drivers -v0x1e43400_0 .net "AndNandOut", 0 0, L_0x1e526e0; 1 drivers -v0x1e434e0_0 .net "B", 0 0, L_0x1e52af0; 1 drivers -v0x1e43560_0 .alias "Command", 2 0, v0x1e48140_0; -L_0x1e528b0 .part v0x1e49280_0, 0, 1; -S_0x1e42ce0 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0x1e42bf0; - .timescale -9 -12; -L_0x1e523c0/d .functor NOT 1, L_0x1e528b0, C4<0>, C4<0>, C4<0>; -L_0x1e523c0 .delay (10000,10000,10000) L_0x1e523c0/d; -L_0x1e52480/d .functor AND 1, L_0x1e52290, L_0x1e523c0, C4<1>, C4<1>; -L_0x1e52480 .delay (20000,20000,20000) L_0x1e52480/d; -L_0x1e52590/d .functor AND 1, L_0x1e52170, L_0x1e528b0, C4<1>, C4<1>; -L_0x1e52590 .delay (20000,20000,20000) L_0x1e52590/d; -L_0x1e526e0/d .functor OR 1, L_0x1e52480, L_0x1e52590, C4<0>, C4<0>; -L_0x1e526e0 .delay (20000,20000,20000) L_0x1e526e0/d; -v0x1e42dd0_0 .net "S", 0 0, L_0x1e528b0; 1 drivers -v0x1e42e50_0 .alias "in0", 0 0, v0x1e432d0_0; -v0x1e42ed0_0 .alias "in1", 0 0, v0x1e43350_0; -v0x1e42f70_0 .net "nS", 0 0, L_0x1e523c0; 1 drivers -v0x1e42ff0_0 .net "out0", 0 0, L_0x1e52480; 1 drivers -v0x1e43090_0 .net "out1", 0 0, L_0x1e52590; 1 drivers -v0x1e43170_0 .alias "outfinal", 0 0, v0x1e43400_0; -S_0x1e42030 .scope generate, "andbits[1]" "andbits[1]" 3 169, 3 169, S_0x1e40720; - .timescale -9 -12; -P_0x1e42128 .param/l "i" 3 169, +C4<01>; -S_0x1e421a0 .scope module, "attempt" "AndNand" 3 171, 3 48, S_0x1e42030; - .timescale -9 -12; -L_0x1e50250/d .functor NAND 1, L_0x1e50b20, L_0x1e50bc0, C4<1>, C4<1>; -L_0x1e50250 .delay (10000,10000,10000) L_0x1e50250/d; -L_0x1e50310/d .functor NOT 1, L_0x1e50250, C4<0>, C4<0>, C4<0>; -L_0x1e50310 .delay (10000,10000,10000) L_0x1e50310/d; -v0x1e427e0_0 .net "A", 0 0, L_0x1e50b20; 1 drivers -v0x1e428a0_0 .net "AandB", 0 0, L_0x1e50310; 1 drivers -v0x1e42920_0 .net "AnandB", 0 0, L_0x1e50250; 1 drivers -v0x1e429d0_0 .net "AndNandOut", 0 0, L_0x1e50760; 1 drivers -v0x1e42ab0_0 .net "B", 0 0, L_0x1e50bc0; 1 drivers -v0x1e42b30_0 .alias "Command", 2 0, v0x1e48140_0; -L_0x1e50930 .part v0x1e49280_0, 0, 1; -S_0x1e42290 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0x1e421a0; - .timescale -9 -12; -L_0x1e50440/d .functor NOT 1, L_0x1e50930, C4<0>, C4<0>, C4<0>; -L_0x1e50440 .delay (10000,10000,10000) L_0x1e50440/d; -L_0x1e50500/d .functor AND 1, L_0x1e50310, L_0x1e50440, C4<1>, C4<1>; -L_0x1e50500 .delay (20000,20000,20000) L_0x1e50500/d; -L_0x1e50610/d .functor AND 1, L_0x1e50250, L_0x1e50930, C4<1>, C4<1>; -L_0x1e50610 .delay (20000,20000,20000) L_0x1e50610/d; -L_0x1e50760/d .functor OR 1, L_0x1e50500, L_0x1e50610, C4<0>, C4<0>; -L_0x1e50760 .delay (20000,20000,20000) L_0x1e50760/d; -v0x1e42380_0 .net "S", 0 0, L_0x1e50930; 1 drivers -v0x1e42400_0 .alias "in0", 0 0, v0x1e428a0_0; -v0x1e424a0_0 .alias "in1", 0 0, v0x1e42920_0; -v0x1e42540_0 .net "nS", 0 0, L_0x1e50440; 1 drivers -v0x1e425c0_0 .net "out0", 0 0, L_0x1e50500; 1 drivers -v0x1e42660_0 .net "out1", 0 0, L_0x1e50610; 1 drivers -v0x1e42740_0 .alias "outfinal", 0 0, v0x1e429d0_0; -S_0x1e41470 .scope generate, "andbits[2]" "andbits[2]" 3 169, 3 169, S_0x1e40720; - .timescale -9 -12; -P_0x1e41568 .param/l "i" 3 169, +C4<010>; -S_0x1e415e0 .scope module, "attempt" "AndNand" 3 171, 3 48, S_0x1e41470; - .timescale -9 -12; -L_0x1e50c60/d .functor NAND 1, L_0x1e51520, L_0x1e515c0, C4<1>, C4<1>; -L_0x1e50c60 .delay (10000,10000,10000) L_0x1e50c60/d; -L_0x1e50dc0/d .functor NOT 1, L_0x1e50c60, C4<0>, C4<0>, C4<0>; -L_0x1e50dc0 .delay (10000,10000,10000) L_0x1e50dc0/d; -v0x1e41c20_0 .net "A", 0 0, L_0x1e51520; 1 drivers -v0x1e41ce0_0 .net "AandB", 0 0, L_0x1e50dc0; 1 drivers -v0x1e41d60_0 .net "AnandB", 0 0, L_0x1e50c60; 1 drivers -v0x1e41e10_0 .net "AndNandOut", 0 0, L_0x1e51210; 1 drivers -v0x1e41ef0_0 .net "B", 0 0, L_0x1e515c0; 1 drivers -v0x1e41f70_0 .alias "Command", 2 0, v0x1e48140_0; -L_0x1e513e0 .part v0x1e49280_0, 0, 1; -S_0x1e416d0 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0x1e415e0; - .timescale -9 -12; -L_0x1e50ef0/d .functor NOT 1, L_0x1e513e0, C4<0>, C4<0>, C4<0>; -L_0x1e50ef0 .delay (10000,10000,10000) L_0x1e50ef0/d; -L_0x1e50fb0/d .functor AND 1, L_0x1e50dc0, L_0x1e50ef0, C4<1>, C4<1>; -L_0x1e50fb0 .delay (20000,20000,20000) L_0x1e50fb0/d; -L_0x1e510c0/d .functor AND 1, L_0x1e50c60, L_0x1e513e0, C4<1>, C4<1>; -L_0x1e510c0 .delay (20000,20000,20000) L_0x1e510c0/d; -L_0x1e51210/d .functor OR 1, L_0x1e50fb0, L_0x1e510c0, C4<0>, C4<0>; -L_0x1e51210 .delay (20000,20000,20000) L_0x1e51210/d; -v0x1e417c0_0 .net "S", 0 0, L_0x1e513e0; 1 drivers -v0x1e41840_0 .alias "in0", 0 0, v0x1e41ce0_0; -v0x1e418e0_0 .alias "in1", 0 0, v0x1e41d60_0; -v0x1e41980_0 .net "nS", 0 0, L_0x1e50ef0; 1 drivers -v0x1e41a00_0 .net "out0", 0 0, L_0x1e50fb0; 1 drivers -v0x1e41aa0_0 .net "out1", 0 0, L_0x1e510c0; 1 drivers -v0x1e41b80_0 .alias "outfinal", 0 0, v0x1e41e10_0; -S_0x1e40890 .scope generate, "andbits[3]" "andbits[3]" 3 169, 3 169, S_0x1e40720; - .timescale -9 -12; -P_0x1e40988 .param/l "i" 3 169, +C4<011>; -S_0x1e40a00 .scope module, "attempt" "AndNand" 3 171, 3 48, S_0x1e40890; - .timescale -9 -12; -L_0x1e516f0/d .functor NAND 1, L_0x1e51f90, L_0x1e52080, C4<1>, C4<1>; -L_0x1e516f0 .delay (10000,10000,10000) L_0x1e516f0/d; -L_0x1e51830/d .functor NOT 1, L_0x1e516f0, C4<0>, C4<0>, C4<0>; -L_0x1e51830 .delay (10000,10000,10000) L_0x1e51830/d; -v0x1e41060_0 .net "A", 0 0, L_0x1e51f90; 1 drivers -v0x1e41120_0 .net "AandB", 0 0, L_0x1e51830; 1 drivers -v0x1e411a0_0 .net "AnandB", 0 0, L_0x1e516f0; 1 drivers -v0x1e41250_0 .net "AndNandOut", 0 0, L_0x1e51c80; 1 drivers -v0x1e41330_0 .net "B", 0 0, L_0x1e52080; 1 drivers -v0x1e413b0_0 .alias "Command", 2 0, v0x1e48140_0; -L_0x1e51e50 .part v0x1e49280_0, 0, 1; -S_0x1e40af0 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0x1e40a00; - .timescale -9 -12; -L_0x1e51960/d .functor NOT 1, L_0x1e51e50, C4<0>, C4<0>, C4<0>; -L_0x1e51960 .delay (10000,10000,10000) L_0x1e51960/d; -L_0x1e51a20/d .functor AND 1, L_0x1e51830, L_0x1e51960, C4<1>, C4<1>; -L_0x1e51a20 .delay (20000,20000,20000) L_0x1e51a20/d; -L_0x1e51b30/d .functor AND 1, L_0x1e516f0, L_0x1e51e50, C4<1>, C4<1>; -L_0x1e51b30 .delay (20000,20000,20000) L_0x1e51b30/d; -L_0x1e51c80/d .functor OR 1, L_0x1e51a20, L_0x1e51b30, C4<0>, C4<0>; -L_0x1e51c80 .delay (20000,20000,20000) L_0x1e51c80/d; -v0x1e40be0_0 .net "S", 0 0, L_0x1e51e50; 1 drivers -v0x1e40c80_0 .alias "in0", 0 0, v0x1e41120_0; -v0x1e40d20_0 .alias "in1", 0 0, v0x1e411a0_0; -v0x1e40dc0_0 .net "nS", 0 0, L_0x1e51960; 1 drivers -v0x1e40e40_0 .net "out0", 0 0, L_0x1e51a20; 1 drivers -v0x1e40ee0_0 .net "out1", 0 0, L_0x1e51b30; 1 drivers -v0x1e40fc0_0 .alias "outfinal", 0 0, v0x1e41250_0; -S_0x1e3b560 .scope module, "trial2" "OrNorXor32" 2 145, 3 177, S_0x1da9580; - .timescale -9 -12; -P_0x1e38fd8 .param/l "size" 3 184, +C4<0100>; -v0x1e40400_0 .alias "A", 3 0, v0x1e47f20_0; -v0x1e40510_0 .alias "B", 3 0, v0x1e48040_0; -v0x1e40620_0 .alias "Command", 2 0, v0x1e48140_0; -v0x1e406a0_0 .alias "OrNorXorOut", 3 0, v0x1e49380_0; -L_0x1e53ca0 .part/pv L_0x1e53a30, 1, 1, 4; -L_0x1e53dd0 .part v0x1e49000_0, 1, 1; -L_0x1e4ac00 .part v0x1e49200_0, 1, 1; -L_0x1e55200 .part/pv L_0x1e54f90, 2, 1, 4; -L_0x1e552a0 .part v0x1e49000_0, 2, 1; -L_0x1e55340 .part v0x1e49200_0, 2, 1; -L_0x1e56500 .part/pv L_0x1e56290, 3, 1, 4; -L_0x1e565a0 .part v0x1e49000_0, 3, 1; -L_0x1e56640 .part v0x1e49200_0, 3, 1; -L_0x1e577b0 .part/pv L_0x1e57540, 0, 1, 4; -L_0x1e578b0 .part v0x1e49000_0, 0, 1; -L_0x1e57950 .part v0x1e49200_0, 0, 1; -S_0x1e3f260 .scope module, "attempt2" "OrNorXor" 3 192, 3 64, S_0x1e3b560; - .timescale -9 -12; -L_0x1e566e0/d .functor NOR 1, L_0x1e578b0, L_0x1e57950, C4<0>, C4<0>; -L_0x1e566e0 .delay (10000,10000,10000) L_0x1e566e0/d; -L_0x1e567e0/d .functor NOT 1, L_0x1e566e0, C4<0>, C4<0>, C4<0>; -L_0x1e567e0 .delay (10000,10000,10000) L_0x1e567e0/d; -L_0x1e56910/d .functor NAND 1, L_0x1e578b0, L_0x1e57950, C4<1>, C4<1>; -L_0x1e56910 .delay (10000,10000,10000) L_0x1e56910/d; -L_0x1e56a70/d .functor NAND 1, L_0x1e56910, L_0x1e567e0, C4<1>, C4<1>; -L_0x1e56a70 .delay (10000,10000,10000) L_0x1e56a70/d; -L_0x1e56b80/d .functor NOT 1, L_0x1e56a70, C4<0>, C4<0>, C4<0>; -L_0x1e56b80 .delay (10000,10000,10000) L_0x1e56b80/d; -v0x1e3fdb0_0 .net "A", 0 0, L_0x1e578b0; 1 drivers -v0x1e3fe50_0 .net "AnandB", 0 0, L_0x1e56910; 1 drivers -v0x1e3fef0_0 .net "AnorB", 0 0, L_0x1e566e0; 1 drivers -v0x1e3ffa0_0 .net "AorB", 0 0, L_0x1e567e0; 1 drivers -v0x1e40020_0 .net "AxorB", 0 0, L_0x1e56b80; 1 drivers -v0x1e400a0_0 .net "B", 0 0, L_0x1e57950; 1 drivers -v0x1e40120_0 .alias "Command", 2 0, v0x1e48140_0; -v0x1e401a0_0 .net "OrNorXorOut", 0 0, L_0x1e57540; 1 drivers -v0x1e40250_0 .net "XorNor", 0 0, L_0x1e56fc0; 1 drivers -v0x1e40320_0 .net "nXor", 0 0, L_0x1e56a70; 1 drivers -L_0x1e57140 .part v0x1e49280_0, 2, 1; -L_0x1e57710 .part v0x1e49280_0, 0, 1; -S_0x1e3f840 .scope module, "mux0" "TwoInMux" 3 83, 3 8, S_0x1e3f260; - .timescale -9 -12; -L_0x1e56ca0/d .functor NOT 1, L_0x1e57140, C4<0>, C4<0>, C4<0>; -L_0x1e56ca0 .delay (10000,10000,10000) L_0x1e56ca0/d; -L_0x1e56d60/d .functor AND 1, L_0x1e56b80, L_0x1e56ca0, C4<1>, C4<1>; -L_0x1e56d60 .delay (20000,20000,20000) L_0x1e56d60/d; -L_0x1e56e70/d .functor AND 1, L_0x1e566e0, L_0x1e57140, C4<1>, C4<1>; -L_0x1e56e70 .delay (20000,20000,20000) L_0x1e56e70/d; -L_0x1e56fc0/d .functor OR 1, L_0x1e56d60, L_0x1e56e70, C4<0>, C4<0>; -L_0x1e56fc0 .delay (20000,20000,20000) L_0x1e56fc0/d; -v0x1e3f930_0 .net "S", 0 0, L_0x1e57140; 1 drivers -v0x1e3f9f0_0 .alias "in0", 0 0, v0x1e40020_0; -v0x1e3fa90_0 .alias "in1", 0 0, v0x1e3fef0_0; -v0x1e3fb30_0 .net "nS", 0 0, L_0x1e56ca0; 1 drivers -v0x1e3fbb0_0 .net "out0", 0 0, L_0x1e56d60; 1 drivers -v0x1e3fc50_0 .net "out1", 0 0, L_0x1e56e70; 1 drivers -v0x1e3fd30_0 .alias "outfinal", 0 0, v0x1e40250_0; -S_0x1e3f350 .scope module, "mux1" "TwoInMux" 3 84, 3 8, S_0x1e3f260; - .timescale -9 -12; -L_0x1e571e0/d .functor NOT 1, L_0x1e57710, C4<0>, C4<0>, C4<0>; -L_0x1e571e0 .delay (10000,10000,10000) L_0x1e571e0/d; -L_0x1e572a0/d .functor AND 1, L_0x1e56fc0, L_0x1e571e0, C4<1>, C4<1>; -L_0x1e572a0 .delay (20000,20000,20000) L_0x1e572a0/d; -L_0x1e573f0/d .functor AND 1, L_0x1e567e0, L_0x1e57710, C4<1>, C4<1>; -L_0x1e573f0 .delay (20000,20000,20000) L_0x1e573f0/d; -L_0x1e57540/d .functor OR 1, L_0x1e572a0, L_0x1e573f0, C4<0>, C4<0>; -L_0x1e57540 .delay (20000,20000,20000) L_0x1e57540/d; -v0x1e3f440_0 .net "S", 0 0, L_0x1e57710; 1 drivers -v0x1e3f4c0_0 .alias "in0", 0 0, v0x1e40250_0; -v0x1e3f540_0 .alias "in1", 0 0, v0x1e3ffa0_0; -v0x1e3f5e0_0 .net "nS", 0 0, L_0x1e571e0; 1 drivers -v0x1e3f660_0 .net "out0", 0 0, L_0x1e572a0; 1 drivers -v0x1e3f700_0 .net "out1", 0 0, L_0x1e573f0; 1 drivers -v0x1e3f7a0_0 .alias "outfinal", 0 0, v0x1e401a0_0; -S_0x1e3de90 .scope generate, "orbits[1]" "orbits[1]" 3 196, 3 196, S_0x1e3b560; - .timescale -9 -12; -P_0x1e3dba8 .param/l "i" 3 196, +C4<01>; -S_0x1e3dfc0 .scope module, "attempt" "OrNorXor" 3 198, 3 64, S_0x1e3de90; - .timescale -9 -12; -L_0x1e529f0/d .functor NOR 1, L_0x1e53dd0, L_0x1e4ac00, C4<0>, C4<0>; -L_0x1e529f0 .delay (10000,10000,10000) L_0x1e529f0/d; -L_0x1e52c90/d .functor NOT 1, L_0x1e529f0, C4<0>, C4<0>, C4<0>; -L_0x1e52c90 .delay (10000,10000,10000) L_0x1e52c90/d; -L_0x1e52dc0/d .functor NAND 1, L_0x1e53dd0, L_0x1e4ac00, C4<1>, C4<1>; -L_0x1e52dc0 .delay (10000,10000,10000) L_0x1e52dc0/d; -L_0x1e52f20/d .functor NAND 1, L_0x1e52dc0, L_0x1e52c90, C4<1>, C4<1>; -L_0x1e52f20 .delay (10000,10000,10000) L_0x1e52f20/d; -L_0x1e53030/d .functor NOT 1, L_0x1e52f20, C4<0>, C4<0>, C4<0>; -L_0x1e53030 .delay (10000,10000,10000) L_0x1e53030/d; -v0x1e3eb70_0 .net "A", 0 0, L_0x1e53dd0; 1 drivers -v0x1e3ec10_0 .net "AnandB", 0 0, L_0x1e52dc0; 1 drivers -v0x1e3ecb0_0 .net "AnorB", 0 0, L_0x1e529f0; 1 drivers -v0x1e3ed60_0 .net "AorB", 0 0, L_0x1e52c90; 1 drivers -v0x1e3ee40_0 .net "AxorB", 0 0, L_0x1e53030; 1 drivers -v0x1e3eef0_0 .net "B", 0 0, L_0x1e4ac00; 1 drivers -v0x1e3efb0_0 .alias "Command", 2 0, v0x1e48140_0; -v0x1e3f030_0 .net "OrNorXorOut", 0 0, L_0x1e53a30; 1 drivers -v0x1e3f0b0_0 .net "XorNor", 0 0, L_0x1e534b0; 1 drivers -v0x1e3f180_0 .net "nXor", 0 0, L_0x1e52f20; 1 drivers -L_0x1e53630 .part v0x1e49280_0, 2, 1; -L_0x1e53c00 .part v0x1e49280_0, 0, 1; -S_0x1e3e600 .scope module, "mux0" "TwoInMux" 3 83, 3 8, S_0x1e3dfc0; - .timescale -9 -12; -L_0x1e53190/d .functor NOT 1, L_0x1e53630, C4<0>, C4<0>, C4<0>; -L_0x1e53190 .delay (10000,10000,10000) L_0x1e53190/d; -L_0x1e53250/d .functor AND 1, L_0x1e53030, L_0x1e53190, C4<1>, C4<1>; -L_0x1e53250 .delay (20000,20000,20000) L_0x1e53250/d; -L_0x1e53360/d .functor AND 1, L_0x1e529f0, L_0x1e53630, C4<1>, C4<1>; -L_0x1e53360 .delay (20000,20000,20000) L_0x1e53360/d; -L_0x1e534b0/d .functor OR 1, L_0x1e53250, L_0x1e53360, C4<0>, C4<0>; -L_0x1e534b0 .delay (20000,20000,20000) L_0x1e534b0/d; -v0x1e3e6f0_0 .net "S", 0 0, L_0x1e53630; 1 drivers -v0x1e3e7b0_0 .alias "in0", 0 0, v0x1e3ee40_0; -v0x1e3e850_0 .alias "in1", 0 0, v0x1e3ecb0_0; -v0x1e3e8f0_0 .net "nS", 0 0, L_0x1e53190; 1 drivers -v0x1e3e970_0 .net "out0", 0 0, L_0x1e53250; 1 drivers -v0x1e3ea10_0 .net "out1", 0 0, L_0x1e53360; 1 drivers -v0x1e3eaf0_0 .alias "outfinal", 0 0, v0x1e3f0b0_0; -S_0x1e3e0b0 .scope module, "mux1" "TwoInMux" 3 84, 3 8, S_0x1e3dfc0; - .timescale -9 -12; -L_0x1e536d0/d .functor NOT 1, L_0x1e53c00, C4<0>, C4<0>, C4<0>; -L_0x1e536d0 .delay (10000,10000,10000) L_0x1e536d0/d; -L_0x1e53790/d .functor AND 1, L_0x1e534b0, L_0x1e536d0, C4<1>, C4<1>; -L_0x1e53790 .delay (20000,20000,20000) L_0x1e53790/d; -L_0x1e538e0/d .functor AND 1, L_0x1e52c90, L_0x1e53c00, C4<1>, C4<1>; -L_0x1e538e0 .delay (20000,20000,20000) L_0x1e538e0/d; -L_0x1e53a30/d .functor OR 1, L_0x1e53790, L_0x1e538e0, C4<0>, C4<0>; -L_0x1e53a30 .delay (20000,20000,20000) L_0x1e53a30/d; -v0x1e3e1a0_0 .net "S", 0 0, L_0x1e53c00; 1 drivers -v0x1e3e220_0 .alias "in0", 0 0, v0x1e3f0b0_0; -v0x1e3e2c0_0 .alias "in1", 0 0, v0x1e3ed60_0; -v0x1e3e360_0 .net "nS", 0 0, L_0x1e536d0; 1 drivers -v0x1e3e3e0_0 .net "out0", 0 0, L_0x1e53790; 1 drivers -v0x1e3e480_0 .net "out1", 0 0, L_0x1e538e0; 1 drivers -v0x1e3e560_0 .alias "outfinal", 0 0, v0x1e3f030_0; -S_0x1e3cac0 .scope generate, "orbits[2]" "orbits[2]" 3 196, 3 196, S_0x1e3b560; - .timescale -9 -12; -P_0x1e3c728 .param/l "i" 3 196, +C4<010>; -S_0x1e3cbf0 .scope module, "attempt" "OrNorXor" 3 198, 3 64, S_0x1e3cac0; - .timescale -9 -12; -L_0x1e4aca0/d .functor NOR 1, L_0x1e552a0, L_0x1e55340, C4<0>, C4<0>; -L_0x1e4aca0 .delay (10000,10000,10000) L_0x1e4aca0/d; -L_0x1e4ae10/d .functor NOT 1, L_0x1e4aca0, C4<0>, C4<0>, C4<0>; -L_0x1e4ae10 .delay (10000,10000,10000) L_0x1e4ae10/d; -L_0x1e54320/d .functor NAND 1, L_0x1e552a0, L_0x1e55340, C4<1>, C4<1>; -L_0x1e54320 .delay (10000,10000,10000) L_0x1e54320/d; -L_0x1e54480/d .functor NAND 1, L_0x1e54320, L_0x1e4ae10, C4<1>, C4<1>; -L_0x1e54480 .delay (10000,10000,10000) L_0x1e54480/d; -L_0x1e54590/d .functor NOT 1, L_0x1e54480, C4<0>, C4<0>, C4<0>; -L_0x1e54590 .delay (10000,10000,10000) L_0x1e54590/d; -v0x1e3d7a0_0 .net "A", 0 0, L_0x1e552a0; 1 drivers -v0x1e3d840_0 .net "AnandB", 0 0, L_0x1e54320; 1 drivers -v0x1e3d8e0_0 .net "AnorB", 0 0, L_0x1e4aca0; 1 drivers -v0x1e3d990_0 .net "AorB", 0 0, L_0x1e4ae10; 1 drivers -v0x1e3da70_0 .net "AxorB", 0 0, L_0x1e54590; 1 drivers -v0x1e3db20_0 .net "B", 0 0, L_0x1e55340; 1 drivers -v0x1e3dbe0_0 .alias "Command", 2 0, v0x1e48140_0; -v0x1e3dc60_0 .net "OrNorXorOut", 0 0, L_0x1e54f90; 1 drivers -v0x1e3dce0_0 .net "XorNor", 0 0, L_0x1e54a10; 1 drivers -v0x1e3ddb0_0 .net "nXor", 0 0, L_0x1e54480; 1 drivers -L_0x1e54b90 .part v0x1e49280_0, 2, 1; -L_0x1e55160 .part v0x1e49280_0, 0, 1; -S_0x1e3d230 .scope module, "mux0" "TwoInMux" 3 83, 3 8, S_0x1e3cbf0; - .timescale -9 -12; -L_0x1e546f0/d .functor NOT 1, L_0x1e54b90, C4<0>, C4<0>, C4<0>; -L_0x1e546f0 .delay (10000,10000,10000) L_0x1e546f0/d; -L_0x1e547b0/d .functor AND 1, L_0x1e54590, L_0x1e546f0, C4<1>, C4<1>; -L_0x1e547b0 .delay (20000,20000,20000) L_0x1e547b0/d; -L_0x1e548c0/d .functor AND 1, L_0x1e4aca0, L_0x1e54b90, C4<1>, C4<1>; -L_0x1e548c0 .delay (20000,20000,20000) L_0x1e548c0/d; -L_0x1e54a10/d .functor OR 1, L_0x1e547b0, L_0x1e548c0, C4<0>, C4<0>; -L_0x1e54a10 .delay (20000,20000,20000) L_0x1e54a10/d; -v0x1e3d320_0 .net "S", 0 0, L_0x1e54b90; 1 drivers -v0x1e3d3e0_0 .alias "in0", 0 0, v0x1e3da70_0; -v0x1e3d480_0 .alias "in1", 0 0, v0x1e3d8e0_0; -v0x1e3d520_0 .net "nS", 0 0, L_0x1e546f0; 1 drivers -v0x1e3d5a0_0 .net "out0", 0 0, L_0x1e547b0; 1 drivers -v0x1e3d640_0 .net "out1", 0 0, L_0x1e548c0; 1 drivers -v0x1e3d720_0 .alias "outfinal", 0 0, v0x1e3dce0_0; -S_0x1e3cce0 .scope module, "mux1" "TwoInMux" 3 84, 3 8, S_0x1e3cbf0; - .timescale -9 -12; -L_0x1e54c30/d .functor NOT 1, L_0x1e55160, C4<0>, C4<0>, C4<0>; -L_0x1e54c30 .delay (10000,10000,10000) L_0x1e54c30/d; -L_0x1e54cf0/d .functor AND 1, L_0x1e54a10, L_0x1e54c30, C4<1>, C4<1>; -L_0x1e54cf0 .delay (20000,20000,20000) L_0x1e54cf0/d; -L_0x1e54e40/d .functor AND 1, L_0x1e4ae10, L_0x1e55160, C4<1>, C4<1>; -L_0x1e54e40 .delay (20000,20000,20000) L_0x1e54e40/d; -L_0x1e54f90/d .functor OR 1, L_0x1e54cf0, L_0x1e54e40, C4<0>, C4<0>; -L_0x1e54f90 .delay (20000,20000,20000) L_0x1e54f90/d; -v0x1e3cdd0_0 .net "S", 0 0, L_0x1e55160; 1 drivers -v0x1e3ce50_0 .alias "in0", 0 0, v0x1e3dce0_0; -v0x1e3cef0_0 .alias "in1", 0 0, v0x1e3d990_0; -v0x1e3cf90_0 .net "nS", 0 0, L_0x1e54c30; 1 drivers -v0x1e3d010_0 .net "out0", 0 0, L_0x1e54cf0; 1 drivers -v0x1e3d0b0_0 .net "out1", 0 0, L_0x1e54e40; 1 drivers -v0x1e3d190_0 .alias "outfinal", 0 0, v0x1e3dc60_0; -S_0x1e3b650 .scope generate, "orbits[3]" "orbits[3]" 3 196, 3 196, S_0x1e3b560; - .timescale -9 -12; -P_0x1e3b398 .param/l "i" 3 196, +C4<011>; -S_0x1e3b740 .scope module, "attempt" "OrNorXor" 3 198, 3 64, S_0x1e3b650; - .timescale -9 -12; -L_0x1e55420/d .functor NOR 1, L_0x1e565a0, L_0x1e56640, C4<0>, C4<0>; -L_0x1e55420 .delay (10000,10000,10000) L_0x1e55420/d; -L_0x1e55510/d .functor NOT 1, L_0x1e55420, C4<0>, C4<0>, C4<0>; -L_0x1e55510 .delay (10000,10000,10000) L_0x1e55510/d; -L_0x1e55620/d .functor NAND 1, L_0x1e565a0, L_0x1e56640, C4<1>, C4<1>; -L_0x1e55620 .delay (10000,10000,10000) L_0x1e55620/d; -L_0x1e55780/d .functor NAND 1, L_0x1e55620, L_0x1e55510, C4<1>, C4<1>; -L_0x1e55780 .delay (10000,10000,10000) L_0x1e55780/d; -L_0x1e55890/d .functor NOT 1, L_0x1e55780, C4<0>, C4<0>, C4<0>; -L_0x1e55890 .delay (10000,10000,10000) L_0x1e55890/d; -v0x1e3c320_0 .net "A", 0 0, L_0x1e565a0; 1 drivers -v0x1e3c3c0_0 .net "AnandB", 0 0, L_0x1e55620; 1 drivers -v0x1e3c460_0 .net "AnorB", 0 0, L_0x1e55420; 1 drivers -v0x1e3c510_0 .net "AorB", 0 0, L_0x1e55510; 1 drivers -v0x1e3c5f0_0 .net "AxorB", 0 0, L_0x1e55890; 1 drivers -v0x1e3c6a0_0 .net "B", 0 0, L_0x1e56640; 1 drivers -v0x1e3c760_0 .alias "Command", 2 0, v0x1e48140_0; -v0x1e34bc0_0 .net "OrNorXorOut", 0 0, L_0x1e56290; 1 drivers -v0x1e34c40_0 .net "XorNor", 0 0, L_0x1e55d10; 1 drivers -v0x1e3ca40_0 .net "nXor", 0 0, L_0x1e55780; 1 drivers -L_0x1e55e90 .part v0x1e49280_0, 2, 1; -L_0x1e56460 .part v0x1e49280_0, 0, 1; -S_0x1e3bdb0 .scope module, "mux0" "TwoInMux" 3 83, 3 8, S_0x1e3b740; - .timescale -9 -12; -L_0x1e559f0/d .functor NOT 1, L_0x1e55e90, C4<0>, C4<0>, C4<0>; -L_0x1e559f0 .delay (10000,10000,10000) L_0x1e559f0/d; -L_0x1e55ab0/d .functor AND 1, L_0x1e55890, L_0x1e559f0, C4<1>, C4<1>; -L_0x1e55ab0 .delay (20000,20000,20000) L_0x1e55ab0/d; -L_0x1e55bc0/d .functor AND 1, L_0x1e55420, L_0x1e55e90, C4<1>, C4<1>; -L_0x1e55bc0 .delay (20000,20000,20000) L_0x1e55bc0/d; -L_0x1e55d10/d .functor OR 1, L_0x1e55ab0, L_0x1e55bc0, C4<0>, C4<0>; -L_0x1e55d10 .delay (20000,20000,20000) L_0x1e55d10/d; -v0x1e3bea0_0 .net "S", 0 0, L_0x1e55e90; 1 drivers -v0x1e3bf60_0 .alias "in0", 0 0, v0x1e3c5f0_0; -v0x1e3c000_0 .alias "in1", 0 0, v0x1e3c460_0; -v0x1e3c0a0_0 .net "nS", 0 0, L_0x1e559f0; 1 drivers -v0x1e3c120_0 .net "out0", 0 0, L_0x1e55ab0; 1 drivers -v0x1e3c1c0_0 .net "out1", 0 0, L_0x1e55bc0; 1 drivers -v0x1e3c2a0_0 .alias "outfinal", 0 0, v0x1e34c40_0; -S_0x1e3b830 .scope module, "mux1" "TwoInMux" 3 84, 3 8, S_0x1e3b740; - .timescale -9 -12; -L_0x1e55f30/d .functor NOT 1, L_0x1e56460, C4<0>, C4<0>, C4<0>; -L_0x1e55f30 .delay (10000,10000,10000) L_0x1e55f30/d; -L_0x1e55ff0/d .functor AND 1, L_0x1e55d10, L_0x1e55f30, C4<1>, C4<1>; -L_0x1e55ff0 .delay (20000,20000,20000) L_0x1e55ff0/d; -L_0x1e56140/d .functor AND 1, L_0x1e55510, L_0x1e56460, C4<1>, C4<1>; -L_0x1e56140 .delay (20000,20000,20000) L_0x1e56140/d; -L_0x1e56290/d .functor OR 1, L_0x1e55ff0, L_0x1e56140, C4<0>, C4<0>; -L_0x1e56290 .delay (20000,20000,20000) L_0x1e56290/d; -v0x1e3b920_0 .net "S", 0 0, L_0x1e56460; 1 drivers -v0x1e3b9a0_0 .alias "in0", 0 0, v0x1e34c40_0; -v0x1e3ba40_0 .alias "in1", 0 0, v0x1e3c510_0; -v0x1e3bae0_0 .net "nS", 0 0, L_0x1e55f30; 1 drivers -v0x1e3bb90_0 .net "out0", 0 0, L_0x1e55ff0; 1 drivers -v0x1e3bc30_0 .net "out1", 0 0, L_0x1e56140; 1 drivers -v0x1e3bd10_0 .alias "outfinal", 0 0, v0x1e34bc0_0; -S_0x1da9070 .scope module, "superalu" "Bitslice32" 2 147, 3 256, S_0x1da9580; - .timescale -9 -12; -P_0x1da88a8 .param/l "size" 3 273, +C4<0100>; -L_0x1e5c990/d .functor AND 1, L_0x1e6f5c0, L_0x1e6f7a0, C4<1>, C4<1>; -L_0x1e5c990 .delay (20000,20000,20000) L_0x1e5c990/d; -L_0x1e6f890/d .functor NOT 1, L_0x1e6f940, C4<0>, C4<0>, C4<0>; -L_0x1e6f890 .delay (10000,10000,10000) L_0x1e6f890/d; -L_0x1e6fdf0/d .functor AND 1, L_0x1e6f890, L_0x1e6f890, C4<1>, C4<1>; -L_0x1e6fdf0 .delay (20000,20000,20000) L_0x1e6fdf0/d; -v0x1e3a450_0 .alias "A", 3 0, v0x1e47f20_0; -v0x1e3a640_0 .alias "AddSubSLTSum", 3 0, v0x1e49080_0; -v0x1e3a6c0_0 .alias "AllZeros", 0 0, v0x1e49100_0; -v0x1e3a740_0 .alias "AndNandOut", 3 0, v0x1e49180_0; -v0x1e3a7f0_0 .alias "B", 3 0, v0x1e48040_0; -RS_0x7f060963b008 .resolv tri, L_0x1e580f0, L_0x1e5a9a0, L_0x1e5d6f0, L_0x1e6d990; -v0x1e3a870_0 .net8 "Cmd0Start", 3 0, RS_0x7f060963b008; 4 drivers -RS_0x7f060963b038 .resolv tri, L_0x1e58f40, L_0x1e5b860, L_0x1e5e6e0, L_0x1e6e7c0; -v0x1e3a8f0_0 .net8 "Cmd1Start", 3 0, RS_0x7f060963b038; 4 drivers -v0x1e3a970_0 .alias "Command", 2 0, v0x1e48140_0; -v0x1e3a9f0_0 .alias "OneBitFinalOut", 3 0, v0x1e49300_0; -v0x1e3aa90_0 .alias "OrNorXorOut", 3 0, v0x1e49380_0; -v0x1e3ab10_0 .alias "SLTflag", 0 0, v0x1e49400_0; -v0x1e3abc0_0 .alias "ZeroFlag", 3 0, v0x1e49480_0; -v0x1e3ac40_0 .net *"_s111", 0 0, L_0x1e5c990; 1 drivers -v0x1e3acc0_0 .net *"_s114", 0 0, L_0x1e6f5c0; 1 drivers -v0x1e3ade0_0 .net *"_s116", 0 0, L_0x1e6f7a0; 1 drivers -v0x1e3ae80_0 .net *"_s118", 0 0, L_0x1e6f940; 1 drivers -v0x1e3ad40_0 .net *"_s21", 0 0, L_0x1e59f90; 1 drivers -v0x1e3afd0_0 .net *"_s46", 0 0, L_0x1e5c2e0; 1 drivers -v0x1e3b0f0_0 .net *"_s71", 0 0, L_0x1e5f4a0; 1 drivers -v0x1e3b170_0 .alias "carryin", 3 0, v0x1e48b70_0; -v0x1e3b050_0 .alias "carryout", 0 0, v0x1e49580_0; -v0x1e3b2d0_0 .alias "overflow", 0 0, v0x1e49600_0; -v0x1e3b220_0 .alias "subtract", 3 0, v0x1e49680_0; -v0x1e3b410_0 .net "yeszero", 0 0, L_0x1e6f890; 1 drivers -L_0x1e580f0 .part/pv L_0x1e57f10, 1, 1, 4; -L_0x1e58190 .part v0x1e49280_0, 0, 1; -L_0x1e582c0 .part v0x1e49280_0, 1, 1; -L_0x1e583f0 .part RS_0x7f060963abe8, 1, 1; -L_0x1e58490 .part RS_0x7f060963abe8, 1, 1; -L_0x1e58530 .part RS_0x7f0609639748, 1, 1; -L_0x1e58730 .part RS_0x7f060963abe8, 1, 1; -L_0x1e58f40 .part/pv L_0x1e58d60, 1, 1, 4; -L_0x1e59030 .part v0x1e49280_0, 0, 1; -L_0x1e59160 .part v0x1e49280_0, 1, 1; -L_0x1e592f0 .part RS_0x7f0609639e38, 1, 1; -L_0x1e594a0 .part RS_0x7f0609639e38, 1, 1; -L_0x1e59540 .part RS_0x7f0609639748, 1, 1; -L_0x1e595e0 .part RS_0x7f0609639748, 1, 1; -L_0x1e59a40 .part/pv L_0x1e59900, 1, 1, 4; -L_0x1e59b30 .part v0x1e49280_0, 2, 1; -L_0x1e59bd0 .part RS_0x7f060963b008, 1, 1; -L_0x1e59d10 .part RS_0x7f060963b038, 1, 1; -L_0x1e59ef0 .part/pv L_0x1e59f90, 1, 1, 4; -L_0x1e5a090 .part RS_0x7f060963b098, 0, 1; -L_0x1e59e50 .part RS_0x7f060963b068, 1, 1; -L_0x1e5a9a0 .part/pv L_0x1e5a7c0, 2, 1, 4; -L_0x1e5a130 .part v0x1e49280_0, 0, 1; -L_0x1e5ab90 .part v0x1e49280_0, 1, 1; -L_0x1e5aa40 .part RS_0x7f060963abe8, 2, 1; -L_0x1e5ad90 .part RS_0x7f060963abe8, 2, 1; -L_0x1e5acc0 .part RS_0x7f0609639748, 2, 1; -L_0x1e5af60 .part RS_0x7f060963abe8, 2, 1; -L_0x1e5b860 .part/pv L_0x1e5b650, 2, 1, 4; -L_0x1e5b900 .part v0x1e49280_0, 0, 1; -L_0x1e5b050 .part v0x1e49280_0, 1, 1; -L_0x1e49f50 .part RS_0x7f0609639e38, 2, 1; -L_0x1e4a100 .part RS_0x7f0609639e38, 2, 1; -L_0x1e49dc0 .part RS_0x7f0609639748, 2, 1; -L_0x1e49ff0 .part RS_0x7f0609639748, 2, 1; -L_0x1e5c690 .part/pv L_0x1e5c550, 2, 1, 4; -L_0x1e5c240 .part v0x1e49280_0, 2, 1; -L_0x1e5c8f0 .part RS_0x7f060963b008, 2, 1; -L_0x1e5c7c0 .part RS_0x7f060963b038, 2, 1; -L_0x1e5cb60 .part/pv L_0x1e5c2e0, 2, 1, 4; -L_0x1e5ca60 .part RS_0x7f060963b098, 1, 1; -L_0x1e5cde0 .part RS_0x7f060963b068, 2, 1; -L_0x1e5d6f0 .part/pv L_0x1e5d4e0, 3, 1, 4; -L_0x1e5d790 .part v0x1e49280_0, 0, 1; -L_0x1e5ce80 .part v0x1e49280_0, 1, 1; -L_0x1e5da30 .part RS_0x7f060963abe8, 3, 1; -L_0x1e4f9f0 .part RS_0x7f060963abe8, 3, 1; -L_0x1e5d8c0 .part RS_0x7f0609639748, 3, 1; -L_0x1e5de70 .part RS_0x7f060963abe8, 3, 1; -L_0x1e5e6e0 .part/pv L_0x1e5e4d0, 3, 1, 4; -L_0x1e5dce0 .part v0x1e49280_0, 0, 1; -L_0x1e5e920 .part v0x1e49280_0, 1, 1; -L_0x1e5e780 .part RS_0x7f0609639e38, 3, 1; -L_0x1e5e820 .part RS_0x7f0609639e38, 3, 1; -L_0x1e5ec10 .part RS_0x7f0609639748, 3, 1; -L_0x1e5ecb0 .part RS_0x7f0609639748, 3, 1; -L_0x1e5f2c0 .part/pv L_0x1e5f180, 3, 1, 4; -L_0x1e5f360 .part v0x1e49280_0, 2, 1; -L_0x1e5ef60 .part RS_0x7f060963b008, 3, 1; -L_0x1e5f050 .part RS_0x7f060963b038, 3, 1; -L_0x1e5f400 .part/pv L_0x1e5f4a0, 3, 1, 4; -L_0x1e5f820 .part RS_0x7f060963b098, 2, 1; -L_0x1e5f630 .part RS_0x7f060963b068, 3, 1; -L_0x1e6d990 .part/pv L_0x1e6d7b0, 0, 1, 4; -L_0x1e5f8c0 .part v0x1e49280_0, 0, 1; -L_0x1e5f9f0 .part v0x1e49280_0, 1, 1; -L_0x1e6da30 .part RS_0x7f060963abe8, 0, 1; -L_0x1e6dad0 .part RS_0x7f060963abe8, 0, 1; -L_0x1e6db70 .part RS_0x7f0609639748, 0, 1; -L_0x1e6df50 .part RS_0x7f060963abe8, 0, 1; -L_0x1e6e7c0 .part/pv L_0x1e6e5e0, 0, 1, 4; -L_0x1e6e860 .part v0x1e49280_0, 0, 1; -L_0x1e6e040 .part v0x1e49280_0, 1, 1; -L_0x1e6e170 .part RS_0x7f0609639e38, 0, 1; -L_0x1e6ebf0 .part RS_0x7f0609639e38, 0, 1; -L_0x1e6ec90 .part RS_0x7f0609639748, 0, 1; -L_0x1e6e990 .part RS_0x7f0609639748, 0, 1; -L_0x1e6f260 .part/pv L_0x1e6f120, 0, 1, 4; -L_0x1e6ed30 .part v0x1e49280_0, 2, 1; -L_0x1e6edd0 .part RS_0x7f060963b008, 0, 1; -L_0x1e6eec0 .part RS_0x7f060963b038, 0, 1; -L_0x1e6f520 .part/pv L_0x1e5c990, 0, 1, 4; -L_0x1e6f5c0 .part RS_0x7f060963b068, 0, 1; -L_0x1e6f7a0 .part RS_0x7f060963b068, 0, 1; -L_0x1e6f940 .part RS_0x7f060963b098, 3, 1; -S_0x1e34eb0 .scope module, "trial" "AddSubSLT32" 3 279, 3 205, S_0x1da9070; - .timescale -9 -12; -P_0x1e34fa8 .param/l "size" 3 228, +C4<0100>; -L_0x1e64920/d .functor OR 1, L_0x1e64be0, C4<0>, C4<0>, C4<0>; -L_0x1e64920 .delay (20000,20000,20000) L_0x1e64920/d; -L_0x1e64d90/d .functor XOR 1, RS_0x7f060963aee8, L_0x1e64e80, C4<0>, C4<0>; -L_0x1e64d90 .delay (40000,40000,40000) L_0x1e64d90/d; -L_0x1e64b10/d .functor AND 1, L_0x1e65050, L_0x1e650f0, C4<1>, C4<1>; -L_0x1e64b10 .delay (20000,20000,20000) L_0x1e64b10/d; -L_0x1e64f20/d .functor NOT 1, RS_0x7f060963af78, C4<0>, C4<0>, C4<0>; -L_0x1e64f20 .delay (10000,10000,10000) L_0x1e64f20/d; -L_0x1e653e0/d .functor NOT 1, L_0x1e65440, C4<0>, C4<0>, C4<0>; -L_0x1e653e0 .delay (10000,10000,10000) L_0x1e653e0/d; -L_0x1e654e0/d .functor AND 1, L_0x1e64f20, L_0x1e65620, C4<1>, C4<1>; -L_0x1e654e0 .delay (20000,20000,20000) L_0x1e654e0/d; -L_0x1e651e0/d .functor AND 1, RS_0x7f060963af78, L_0x1e653e0, C4<1>, C4<1>; -L_0x1e651e0 .delay (20000,20000,20000) L_0x1e651e0/d; -L_0x1e65810/d .functor AND 1, L_0x1e654e0, L_0x1e64b10, C4<1>, C4<1>; -L_0x1e65810 .delay (20000,20000,20000) L_0x1e65810/d; -L_0x1e65950/d .functor AND 1, L_0x1e651e0, L_0x1e64b10, C4<1>, C4<1>; -L_0x1e65950 .delay (20000,20000,20000) L_0x1e65950/d; -L_0x1e65a70/d .functor OR 1, L_0x1e65810, L_0x1e65950, C4<0>, C4<0>; -L_0x1e65a70 .delay (20000,20000,20000) L_0x1e65a70/d; -v0x1e395c0_0 .alias "A", 3 0, v0x1e47f20_0; -v0x1e39660_0 .alias "AddSubSLTSum", 3 0, v0x1e49080_0; -v0x1e39700_0 .alias "B", 3 0, v0x1e48040_0; -RS_0x7f060963ac18 .resolv tri, L_0x1e60950, L_0x1e61d70, L_0x1e63170, L_0x1e64690; -v0x1e39780_0 .net8 "CarryoutWire", 3 0, RS_0x7f060963ac18; 4 drivers -v0x1e39800_0 .alias "Command", 2 0, v0x1e48140_0; -v0x1e39880_0 .net "Res0OF1", 0 0, L_0x1e651e0; 1 drivers -v0x1e39920_0 .net "Res1OF0", 0 0, L_0x1e654e0; 1 drivers -v0x1e399c0_0 .alias "SLTflag", 0 0, v0x1e49400_0; -v0x1e39ab0_0 .net "SLTflag0", 0 0, L_0x1e65810; 1 drivers -v0x1e39b50_0 .net "SLTflag1", 0 0, L_0x1e65950; 1 drivers -v0x1e39bf0_0 .net "SLTon", 0 0, L_0x1e64b10; 1 drivers -v0x1e39c90_0 .net *"_s40", 0 0, L_0x1e64be0; 1 drivers -v0x1e39d30_0 .net/s *"_s41", 0 0, C4<0>; 1 drivers -v0x1e39dd0_0 .net *"_s44", 0 0, L_0x1e64e80; 1 drivers -v0x1e39ef0_0 .net *"_s46", 0 0, L_0x1e65050; 1 drivers -v0x1e39f90_0 .net *"_s48", 0 0, L_0x1e650f0; 1 drivers -v0x1e39e50_0 .net *"_s50", 0 0, L_0x1e65440; 1 drivers -v0x1e3a0e0_0 .net *"_s52", 0 0, L_0x1e65620; 1 drivers -v0x1e3a200_0 .alias "carryin", 3 0, v0x1e48b70_0; -v0x1e3a280_0 .alias "carryout", 0 0, v0x1e49580_0; -v0x1e3a160_0 .net "nAddSubSLTSum", 0 0, L_0x1e653e0; 1 drivers -v0x1e3a3b0_0 .net "nOF", 0 0, L_0x1e64f20; 1 drivers -v0x1e3a300_0 .alias "overflow", 0 0, v0x1e49600_0; -v0x1e3a4f0_0 .alias "subtract", 3 0, v0x1e49680_0; -L_0x1e60860 .part/pv L_0x1e603d0, 1, 1, 4; -L_0x1e60950 .part/pv L_0x1e60720, 1, 1, 4; -L_0x1e60a40 .part/pv L_0x1e60100, 1, 1, 4; -L_0x1e60b30 .part v0x1e49000_0, 1, 1; -L_0x1e60bd0 .part v0x1e49200_0, 1, 1; -L_0x1e60d00 .part RS_0x7f060963ac18, 0, 1; -L_0x1e61c80 .part/pv L_0x1e617f0, 2, 1, 4; -L_0x1e61d70 .part/pv L_0x1e61b40, 2, 1, 4; -L_0x1e61eb0 .part/pv L_0x1e61520, 2, 1, 4; -L_0x1e61fa0 .part v0x1e49000_0, 2, 1; -L_0x1e620a0 .part v0x1e49200_0, 2, 1; -L_0x1e621d0 .part RS_0x7f060963ac18, 1, 1; -L_0x1e63080 .part/pv L_0x1e62bf0, 3, 1, 4; -L_0x1e63170 .part/pv L_0x1e62f40, 3, 1, 4; -L_0x1e632e0 .part/pv L_0x1e62920, 3, 1, 4; -L_0x1e633d0 .part v0x1e49000_0, 3, 1; -L_0x1e63500 .part v0x1e49200_0, 3, 1; -L_0x1e63630 .part RS_0x7f060963ac18, 2, 1; -L_0x1e645a0 .part/pv L_0x1e640d0, 0, 1, 4; -L_0x1e64690 .part/pv L_0x1e64440, 0, 1, 4; -L_0x1e636d0 .part/pv L_0x1e63e00, 0, 1, 4; -L_0x1e64880 .part v0x1e49000_0, 0, 1; -L_0x1e64780 .part v0x1e49200_0, 0, 1; -L_0x1e64a70 .part RS_0x7f060963afa8, 0, 1; -L_0x1e64be0 .part RS_0x7f060963ac18, 3, 1; -L_0x1e64e80 .part RS_0x7f060963ac18, 2, 1; -L_0x1e65050 .part v0x1e49280_0, 1, 1; -L_0x1e650f0 .part RS_0x7f060963afa8, 0, 1; -L_0x1e65440 .part RS_0x7f060963abe8, 3, 1; -L_0x1e65620 .part RS_0x7f060963abe8, 3, 1; -S_0x1e385b0 .scope module, "attempt2" "MiddleAddSubSLT" 3 225, 3 89, S_0x1e34eb0; - .timescale -9 -12; -L_0x1e63470/d .functor NOT 1, L_0x1e64780, C4<0>, C4<0>, C4<0>; -L_0x1e63470 .delay (10000,10000,10000) L_0x1e63470/d; -L_0x1e63cc0/d .functor NOT 1, L_0x1e63d60, C4<0>, C4<0>, C4<0>; -L_0x1e63cc0 .delay (10000,10000,10000) L_0x1e63cc0/d; -L_0x1e63e00/d .functor AND 1, L_0x1e63f40, L_0x1e63cc0, C4<1>, C4<1>; -L_0x1e63e00 .delay (20000,20000,20000) L_0x1e63e00/d; -L_0x1e63fe0/d .functor XOR 1, L_0x1e64880, L_0x1e63a90, C4<0>, C4<0>; -L_0x1e63fe0 .delay (40000,40000,40000) L_0x1e63fe0/d; -L_0x1e640d0/d .functor XOR 1, L_0x1e63fe0, L_0x1e64a70, C4<0>, C4<0>; -L_0x1e640d0 .delay (40000,40000,40000) L_0x1e640d0/d; -L_0x1e641c0/d .functor AND 1, L_0x1e64880, L_0x1e63a90, C4<1>, C4<1>; -L_0x1e641c0 .delay (20000,20000,20000) L_0x1e641c0/d; -L_0x1e64330/d .functor AND 1, L_0x1e63fe0, L_0x1e64a70, C4<1>, C4<1>; -L_0x1e64330 .delay (20000,20000,20000) L_0x1e64330/d; -L_0x1e64440/d .functor OR 1, L_0x1e641c0, L_0x1e64330, C4<0>, C4<0>; -L_0x1e64440 .delay (20000,20000,20000) L_0x1e64440/d; -v0x1e38c20_0 .net "A", 0 0, L_0x1e64880; 1 drivers -v0x1e38ce0_0 .net "AandB", 0 0, L_0x1e641c0; 1 drivers -v0x1e38d80_0 .net "AddSubSLTSum", 0 0, L_0x1e640d0; 1 drivers -v0x1e38e20_0 .net "AxorB", 0 0, L_0x1e63fe0; 1 drivers -v0x1e38ea0_0 .net "B", 0 0, L_0x1e64780; 1 drivers -v0x1e38f50_0 .net "BornB", 0 0, L_0x1e63a90; 1 drivers -v0x1e39010_0 .net "CINandAxorB", 0 0, L_0x1e64330; 1 drivers -v0x1e39090_0 .alias "Command", 2 0, v0x1e48140_0; -v0x1e39110_0 .net *"_s3", 0 0, L_0x1e63d60; 1 drivers -v0x1e39190_0 .net *"_s5", 0 0, L_0x1e63f40; 1 drivers -v0x1e39230_0 .net "carryin", 0 0, L_0x1e64a70; 1 drivers -v0x1e392d0_0 .net "carryout", 0 0, L_0x1e64440; 1 drivers -v0x1e39370_0 .net "nB", 0 0, L_0x1e63470; 1 drivers -v0x1e39420_0 .net "nCmd2", 0 0, L_0x1e63cc0; 1 drivers -v0x1e39520_0 .net "subtract", 0 0, L_0x1e63e00; 1 drivers -L_0x1e63c20 .part v0x1e49280_0, 0, 1; -L_0x1e63d60 .part v0x1e49280_0, 2, 1; -L_0x1e63f40 .part v0x1e49280_0, 0, 1; -S_0x1e386a0 .scope module, "mux0" "TwoInMux" 3 105, 3 8, S_0x1e385b0; - .timescale -9 -12; -L_0x1e63810/d .functor NOT 1, L_0x1e63c20, C4<0>, C4<0>, C4<0>; -L_0x1e63810 .delay (10000,10000,10000) L_0x1e63810/d; -L_0x1e638b0/d .functor AND 1, L_0x1e64780, L_0x1e63810, C4<1>, C4<1>; -L_0x1e638b0 .delay (20000,20000,20000) L_0x1e638b0/d; -L_0x1e639a0/d .functor AND 1, L_0x1e63470, L_0x1e63c20, C4<1>, C4<1>; -L_0x1e639a0 .delay (20000,20000,20000) L_0x1e639a0/d; -L_0x1e63a90/d .functor OR 1, L_0x1e638b0, L_0x1e639a0, C4<0>, C4<0>; -L_0x1e63a90 .delay (20000,20000,20000) L_0x1e63a90/d; -v0x1e38790_0 .net "S", 0 0, L_0x1e63c20; 1 drivers -v0x1e38850_0 .alias "in0", 0 0, v0x1e38ea0_0; -v0x1e388f0_0 .alias "in1", 0 0, v0x1e39370_0; -v0x1e38990_0 .net "nS", 0 0, L_0x1e63810; 1 drivers -v0x1e38a40_0 .net "out0", 0 0, L_0x1e638b0; 1 drivers -v0x1e38ae0_0 .net "out1", 0 0, L_0x1e639a0; 1 drivers -v0x1e38b80_0 .alias "outfinal", 0 0, v0x1e38f50_0; -S_0x1e37410 .scope generate, "addbits[1]" "addbits[1]" 3 230, 3 230, S_0x1e34eb0; - .timescale -9 -12; -P_0x1e36e28 .param/l "i" 3 230, +C4<01>; -S_0x1e37580 .scope module, "attempt" "MiddleAddSubSLT" 3 232, 3 89, S_0x1e37410; - .timescale -9 -12; -L_0x1e5f720/d .functor NOT 1, L_0x1e60bd0, C4<0>, C4<0>, C4<0>; -L_0x1e5f720 .delay (10000,10000,10000) L_0x1e5f720/d; -L_0x1e5ffc0/d .functor NOT 1, L_0x1e60060, C4<0>, C4<0>, C4<0>; -L_0x1e5ffc0 .delay (10000,10000,10000) L_0x1e5ffc0/d; -L_0x1e60100/d .functor AND 1, L_0x1e60240, L_0x1e5ffc0, C4<1>, C4<1>; -L_0x1e60100 .delay (20000,20000,20000) L_0x1e60100/d; -L_0x1e602e0/d .functor XOR 1, L_0x1e60b30, L_0x1e5fd90, C4<0>, C4<0>; -L_0x1e602e0 .delay (40000,40000,40000) L_0x1e602e0/d; -L_0x1e603d0/d .functor XOR 1, L_0x1e602e0, L_0x1e60d00, C4<0>, C4<0>; -L_0x1e603d0 .delay (40000,40000,40000) L_0x1e603d0/d; -L_0x1e604c0/d .functor AND 1, L_0x1e60b30, L_0x1e5fd90, C4<1>, C4<1>; -L_0x1e604c0 .delay (20000,20000,20000) L_0x1e604c0/d; -L_0x1e60630/d .functor AND 1, L_0x1e602e0, L_0x1e60d00, C4<1>, C4<1>; -L_0x1e60630 .delay (20000,20000,20000) L_0x1e60630/d; -L_0x1e60720/d .functor OR 1, L_0x1e604c0, L_0x1e60630, C4<0>, C4<0>; -L_0x1e60720 .delay (20000,20000,20000) L_0x1e60720/d; -v0x1e37c10_0 .net "A", 0 0, L_0x1e60b30; 1 drivers -v0x1e37cd0_0 .net "AandB", 0 0, L_0x1e604c0; 1 drivers -v0x1e37d70_0 .net "AddSubSLTSum", 0 0, L_0x1e603d0; 1 drivers -v0x1e37e10_0 .net "AxorB", 0 0, L_0x1e602e0; 1 drivers -v0x1e37e90_0 .net "B", 0 0, L_0x1e60bd0; 1 drivers -v0x1e37f40_0 .net "BornB", 0 0, L_0x1e5fd90; 1 drivers -v0x1e38000_0 .net "CINandAxorB", 0 0, L_0x1e60630; 1 drivers -v0x1e38080_0 .alias "Command", 2 0, v0x1e48140_0; -v0x1e38100_0 .net *"_s3", 0 0, L_0x1e60060; 1 drivers -v0x1e38180_0 .net *"_s5", 0 0, L_0x1e60240; 1 drivers -v0x1e38220_0 .net "carryin", 0 0, L_0x1e60d00; 1 drivers -v0x1e382c0_0 .net "carryout", 0 0, L_0x1e60720; 1 drivers -v0x1e38360_0 .net "nB", 0 0, L_0x1e5f720; 1 drivers -v0x1e38410_0 .net "nCmd2", 0 0, L_0x1e5ffc0; 1 drivers -v0x1e38510_0 .net "subtract", 0 0, L_0x1e60100; 1 drivers -L_0x1e5ff20 .part v0x1e49280_0, 0, 1; -L_0x1e60060 .part v0x1e49280_0, 2, 1; -L_0x1e60240 .part v0x1e49280_0, 0, 1; -S_0x1e37670 .scope module, "mux0" "TwoInMux" 3 105, 3 8, S_0x1e37580; - .timescale -9 -12; -L_0x1e5fb10/d .functor NOT 1, L_0x1e5ff20, C4<0>, C4<0>, C4<0>; -L_0x1e5fb10 .delay (10000,10000,10000) L_0x1e5fb10/d; -L_0x1e5fbb0/d .functor AND 1, L_0x1e60bd0, L_0x1e5fb10, C4<1>, C4<1>; -L_0x1e5fbb0 .delay (20000,20000,20000) L_0x1e5fbb0/d; -L_0x1e5fca0/d .functor AND 1, L_0x1e5f720, L_0x1e5ff20, C4<1>, C4<1>; -L_0x1e5fca0 .delay (20000,20000,20000) L_0x1e5fca0/d; -L_0x1e5fd90/d .functor OR 1, L_0x1e5fbb0, L_0x1e5fca0, C4<0>, C4<0>; -L_0x1e5fd90 .delay (20000,20000,20000) L_0x1e5fd90/d; -v0x1e37760_0 .net "S", 0 0, L_0x1e5ff20; 1 drivers -v0x1e37800_0 .alias "in0", 0 0, v0x1e37e90_0; -v0x1e378a0_0 .alias "in1", 0 0, v0x1e38360_0; -v0x1e37940_0 .net "nS", 0 0, L_0x1e5fb10; 1 drivers -v0x1e379f0_0 .net "out0", 0 0, L_0x1e5fbb0; 1 drivers -v0x1e37a90_0 .net "out1", 0 0, L_0x1e5fca0; 1 drivers -v0x1e37b70_0 .alias "outfinal", 0 0, v0x1e37f40_0; -S_0x1e36270 .scope generate, "addbits[2]" "addbits[2]" 3 230, 3 230, S_0x1e34eb0; - .timescale -9 -12; -P_0x1e35bb8 .param/l "i" 3 230, +C4<010>; -S_0x1e363e0 .scope module, "attempt" "MiddleAddSubSLT" 3 232, 3 89, S_0x1e36270; - .timescale -9 -12; -L_0x1e60da0/d .functor NOT 1, L_0x1e620a0, C4<0>, C4<0>, C4<0>; -L_0x1e60da0 .delay (10000,10000,10000) L_0x1e60da0/d; -L_0x1e613e0/d .functor NOT 1, L_0x1e61480, C4<0>, C4<0>, C4<0>; -L_0x1e613e0 .delay (10000,10000,10000) L_0x1e613e0/d; -L_0x1e61520/d .functor AND 1, L_0x1e61660, L_0x1e613e0, C4<1>, C4<1>; -L_0x1e61520 .delay (20000,20000,20000) L_0x1e61520/d; -L_0x1e61700/d .functor XOR 1, L_0x1e61fa0, L_0x1e611b0, C4<0>, C4<0>; -L_0x1e61700 .delay (40000,40000,40000) L_0x1e61700/d; -L_0x1e617f0/d .functor XOR 1, L_0x1e61700, L_0x1e621d0, C4<0>, C4<0>; -L_0x1e617f0 .delay (40000,40000,40000) L_0x1e617f0/d; -L_0x1e618e0/d .functor AND 1, L_0x1e61fa0, L_0x1e611b0, C4<1>, C4<1>; -L_0x1e618e0 .delay (20000,20000,20000) L_0x1e618e0/d; -L_0x1e61a50/d .functor AND 1, L_0x1e61700, L_0x1e621d0, C4<1>, C4<1>; -L_0x1e61a50 .delay (20000,20000,20000) L_0x1e61a50/d; -L_0x1e61b40/d .functor OR 1, L_0x1e618e0, L_0x1e61a50, C4<0>, C4<0>; -L_0x1e61b40 .delay (20000,20000,20000) L_0x1e61b40/d; -v0x1e36a70_0 .net "A", 0 0, L_0x1e61fa0; 1 drivers -v0x1e36b30_0 .net "AandB", 0 0, L_0x1e618e0; 1 drivers -v0x1e36bd0_0 .net "AddSubSLTSum", 0 0, L_0x1e617f0; 1 drivers -v0x1e36c70_0 .net "AxorB", 0 0, L_0x1e61700; 1 drivers -v0x1e36cf0_0 .net "B", 0 0, L_0x1e620a0; 1 drivers -v0x1e36da0_0 .net "BornB", 0 0, L_0x1e611b0; 1 drivers -v0x1e36e60_0 .net "CINandAxorB", 0 0, L_0x1e61a50; 1 drivers -v0x1e36ee0_0 .alias "Command", 2 0, v0x1e48140_0; -v0x1e36f60_0 .net *"_s3", 0 0, L_0x1e61480; 1 drivers -v0x1e36fe0_0 .net *"_s5", 0 0, L_0x1e61660; 1 drivers -v0x1e37080_0 .net "carryin", 0 0, L_0x1e621d0; 1 drivers -v0x1e37120_0 .net "carryout", 0 0, L_0x1e61b40; 1 drivers -v0x1e371c0_0 .net "nB", 0 0, L_0x1e60da0; 1 drivers -v0x1e37270_0 .net "nCmd2", 0 0, L_0x1e613e0; 1 drivers -v0x1e37370_0 .net "subtract", 0 0, L_0x1e61520; 1 drivers -L_0x1e61340 .part v0x1e49280_0, 0, 1; -L_0x1e61480 .part v0x1e49280_0, 2, 1; -L_0x1e61660 .part v0x1e49280_0, 0, 1; -S_0x1e364d0 .scope module, "mux0" "TwoInMux" 3 105, 3 8, S_0x1e363e0; - .timescale -9 -12; -L_0x1e60f30/d .functor NOT 1, L_0x1e61340, C4<0>, C4<0>, C4<0>; -L_0x1e60f30 .delay (10000,10000,10000) L_0x1e60f30/d; -L_0x1e60fd0/d .functor AND 1, L_0x1e620a0, L_0x1e60f30, C4<1>, C4<1>; -L_0x1e60fd0 .delay (20000,20000,20000) L_0x1e60fd0/d; -L_0x1e610c0/d .functor AND 1, L_0x1e60da0, L_0x1e61340, C4<1>, C4<1>; -L_0x1e610c0 .delay (20000,20000,20000) L_0x1e610c0/d; -L_0x1e611b0/d .functor OR 1, L_0x1e60fd0, L_0x1e610c0, C4<0>, C4<0>; -L_0x1e611b0 .delay (20000,20000,20000) L_0x1e611b0/d; -v0x1e365c0_0 .net "S", 0 0, L_0x1e61340; 1 drivers -v0x1e36660_0 .alias "in0", 0 0, v0x1e36cf0_0; -v0x1e36700_0 .alias "in1", 0 0, v0x1e371c0_0; -v0x1e367a0_0 .net "nS", 0 0, L_0x1e60f30; 1 drivers -v0x1e36850_0 .net "out0", 0 0, L_0x1e60fd0; 1 drivers -v0x1e368f0_0 .net "out1", 0 0, L_0x1e610c0; 1 drivers -v0x1e369d0_0 .alias "outfinal", 0 0, v0x1e36da0_0; -S_0x1e35020 .scope generate, "addbits[3]" "addbits[3]" 3 230, 3 230, S_0x1e34eb0; - .timescale -9 -12; -P_0x1e35118 .param/l "i" 3 230, +C4<011>; -S_0x1e35190 .scope module, "attempt" "MiddleAddSubSLT" 3 232, 3 89, S_0x1e35020; - .timescale -9 -12; -L_0x1e62040/d .functor NOT 1, L_0x1e63500, C4<0>, C4<0>, C4<0>; -L_0x1e62040 .delay (10000,10000,10000) L_0x1e62040/d; -L_0x1e627e0/d .functor NOT 1, L_0x1e62880, C4<0>, C4<0>, C4<0>; -L_0x1e627e0 .delay (10000,10000,10000) L_0x1e627e0/d; -L_0x1e62920/d .functor AND 1, L_0x1e62a60, L_0x1e627e0, C4<1>, C4<1>; -L_0x1e62920 .delay (20000,20000,20000) L_0x1e62920/d; -L_0x1e62b00/d .functor XOR 1, L_0x1e633d0, L_0x1e625b0, C4<0>, C4<0>; -L_0x1e62b00 .delay (40000,40000,40000) L_0x1e62b00/d; -L_0x1e62bf0/d .functor XOR 1, L_0x1e62b00, L_0x1e63630, C4<0>, C4<0>; -L_0x1e62bf0 .delay (40000,40000,40000) L_0x1e62bf0/d; -L_0x1e62ce0/d .functor AND 1, L_0x1e633d0, L_0x1e625b0, C4<1>, C4<1>; -L_0x1e62ce0 .delay (20000,20000,20000) L_0x1e62ce0/d; -L_0x1e62e50/d .functor AND 1, L_0x1e62b00, L_0x1e63630, C4<1>, C4<1>; -L_0x1e62e50 .delay (20000,20000,20000) L_0x1e62e50/d; -L_0x1e62f40/d .functor OR 1, L_0x1e62ce0, L_0x1e62e50, C4<0>, C4<0>; -L_0x1e62f40 .delay (20000,20000,20000) L_0x1e62f40/d; -v0x1e35800_0 .net "A", 0 0, L_0x1e633d0; 1 drivers -v0x1e358c0_0 .net "AandB", 0 0, L_0x1e62ce0; 1 drivers -v0x1e35960_0 .net "AddSubSLTSum", 0 0, L_0x1e62bf0; 1 drivers -v0x1e35a00_0 .net "AxorB", 0 0, L_0x1e62b00; 1 drivers -v0x1e35a80_0 .net "B", 0 0, L_0x1e63500; 1 drivers -v0x1e35b30_0 .net "BornB", 0 0, L_0x1e625b0; 1 drivers -v0x1e35bf0_0 .net "CINandAxorB", 0 0, L_0x1e62e50; 1 drivers -v0x1e35c70_0 .alias "Command", 2 0, v0x1e48140_0; -v0x1e35cf0_0 .net *"_s3", 0 0, L_0x1e62880; 1 drivers -v0x1e35d70_0 .net *"_s5", 0 0, L_0x1e62a60; 1 drivers -v0x1e35e70_0 .net "carryin", 0 0, L_0x1e63630; 1 drivers -v0x1e35f10_0 .net "carryout", 0 0, L_0x1e62f40; 1 drivers -v0x1e36020_0 .net "nB", 0 0, L_0x1e62040; 1 drivers -v0x1e360d0_0 .net "nCmd2", 0 0, L_0x1e627e0; 1 drivers -v0x1e361d0_0 .net "subtract", 0 0, L_0x1e62920; 1 drivers -L_0x1e62740 .part v0x1e49280_0, 0, 1; -L_0x1e62880 .part v0x1e49280_0, 2, 1; -L_0x1e62a60 .part v0x1e49280_0, 0, 1; -S_0x1e35280 .scope module, "mux0" "TwoInMux" 3 105, 3 8, S_0x1e35190; - .timescale -9 -12; -L_0x1e62370/d .functor NOT 1, L_0x1e62740, C4<0>, C4<0>, C4<0>; -L_0x1e62370 .delay (10000,10000,10000) L_0x1e62370/d; -L_0x1e623d0/d .functor AND 1, L_0x1e63500, L_0x1e62370, C4<1>, C4<1>; -L_0x1e623d0 .delay (20000,20000,20000) L_0x1e623d0/d; -L_0x1e624c0/d .functor AND 1, L_0x1e62040, L_0x1e62740, C4<1>, C4<1>; -L_0x1e624c0 .delay (20000,20000,20000) L_0x1e624c0/d; -L_0x1e625b0/d .functor OR 1, L_0x1e623d0, L_0x1e624c0, C4<0>, C4<0>; -L_0x1e625b0 .delay (20000,20000,20000) L_0x1e625b0/d; -v0x1e35370_0 .net "S", 0 0, L_0x1e62740; 1 drivers -v0x1e353f0_0 .alias "in0", 0 0, v0x1e35a80_0; -v0x1e35490_0 .alias "in1", 0 0, v0x1e36020_0; -v0x1e35530_0 .net "nS", 0 0, L_0x1e62370; 1 drivers -v0x1e355e0_0 .net "out0", 0 0, L_0x1e623d0; 1 drivers -v0x1e35680_0 .net "out1", 0 0, L_0x1e624c0; 1 drivers -v0x1e35760_0 .alias "outfinal", 0 0, v0x1e35b30_0; -S_0x1e31c70 .scope module, "trial1" "AndNand32" 3 280, 3 154, S_0x1da9070; - .timescale -9 -12; -P_0x1e316f8 .param/l "size" 3 161, +C4<0100>; -v0x1e31b60_0 .alias "A", 3 0, v0x1e47f20_0; -v0x1e34cd0_0 .alias "AndNandOut", 3 0, v0x1e49180_0; -v0x1e34d50_0 .alias "B", 3 0, v0x1e48040_0; -v0x1e34e00_0 .alias "Command", 2 0, v0x1e48140_0; -L_0x1e663d0 .part/pv L_0x1e66160, 1, 1, 4; -L_0x1e66490 .part v0x1e49000_0, 1, 1; -L_0x1e66530 .part v0x1e49200_0, 1, 1; -L_0x1e66e40 .part/pv L_0x1e66bd0, 2, 1, 4; -L_0x1e66ee0 .part v0x1e49000_0, 2, 1; -L_0x1e66f80 .part v0x1e49200_0, 2, 1; -L_0x1e678b0 .part/pv L_0x1e67640, 3, 1, 4; -L_0x1e59390 .part v0x1e49000_0, 3, 1; -L_0x1e67b60 .part v0x1e49200_0, 3, 1; -L_0x1e68410 .part/pv L_0x1e681a0, 0, 1, 4; -L_0x1e68510 .part v0x1e49000_0, 0, 1; -L_0x1e685b0 .part v0x1e49200_0, 0, 1; -S_0x1e34190 .scope module, "attempt2" "AndNand" 3 165, 3 48, S_0x1e31c70; - .timescale -9 -12; -L_0x1e67c50/d .functor NAND 1, L_0x1e68510, L_0x1e685b0, C4<1>, C4<1>; -L_0x1e67c50 .delay (10000,10000,10000) L_0x1e67c50/d; -L_0x1e67d50/d .functor NOT 1, L_0x1e67c50, C4<0>, C4<0>, C4<0>; -L_0x1e67d50 .delay (10000,10000,10000) L_0x1e67d50/d; -v0x1e347b0_0 .net "A", 0 0, L_0x1e68510; 1 drivers -v0x1e34870_0 .net "AandB", 0 0, L_0x1e67d50; 1 drivers -v0x1e348f0_0 .net "AnandB", 0 0, L_0x1e67c50; 1 drivers -v0x1e349a0_0 .net "AndNandOut", 0 0, L_0x1e681a0; 1 drivers -v0x1e34a80_0 .net "B", 0 0, L_0x1e685b0; 1 drivers -v0x1e34b00_0 .alias "Command", 2 0, v0x1e48140_0; -L_0x1e68370 .part v0x1e49280_0, 0, 1; -S_0x1e34280 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0x1e34190; - .timescale -9 -12; -L_0x1e67e80/d .functor NOT 1, L_0x1e68370, C4<0>, C4<0>, C4<0>; -L_0x1e67e80 .delay (10000,10000,10000) L_0x1e67e80/d; -L_0x1e67f40/d .functor AND 1, L_0x1e67d50, L_0x1e67e80, C4<1>, C4<1>; -L_0x1e67f40 .delay (20000,20000,20000) L_0x1e67f40/d; -L_0x1e68050/d .functor AND 1, L_0x1e67c50, L_0x1e68370, C4<1>, C4<1>; -L_0x1e68050 .delay (20000,20000,20000) L_0x1e68050/d; -L_0x1e681a0/d .functor OR 1, L_0x1e67f40, L_0x1e68050, C4<0>, C4<0>; -L_0x1e681a0 .delay (20000,20000,20000) L_0x1e681a0/d; -v0x1e34370_0 .net "S", 0 0, L_0x1e68370; 1 drivers -v0x1e343f0_0 .alias "in0", 0 0, v0x1e34870_0; -v0x1e34470_0 .alias "in1", 0 0, v0x1e348f0_0; -v0x1e34510_0 .net "nS", 0 0, L_0x1e67e80; 1 drivers -v0x1e34590_0 .net "out0", 0 0, L_0x1e67f40; 1 drivers -v0x1e34630_0 .net "out1", 0 0, L_0x1e68050; 1 drivers -v0x1e34710_0 .alias "outfinal", 0 0, v0x1e349a0_0; -S_0x1e335d0 .scope generate, "andbits[1]" "andbits[1]" 3 169, 3 169, S_0x1e31c70; - .timescale -9 -12; -P_0x1e336c8 .param/l "i" 3 169, +C4<01>; -S_0x1e33740 .scope module, "attempt" "AndNand" 3 171, 3 48, S_0x1e335d0; - .timescale -9 -12; -L_0x1e65c50/d .functor NAND 1, L_0x1e66490, L_0x1e66530, C4<1>, C4<1>; -L_0x1e65c50 .delay (10000,10000,10000) L_0x1e65c50/d; -L_0x1e65d10/d .functor NOT 1, L_0x1e65c50, C4<0>, C4<0>, C4<0>; -L_0x1e65d10 .delay (10000,10000,10000) L_0x1e65d10/d; -v0x1e33d80_0 .net "A", 0 0, L_0x1e66490; 1 drivers -v0x1e33e40_0 .net "AandB", 0 0, L_0x1e65d10; 1 drivers -v0x1e33ec0_0 .net "AnandB", 0 0, L_0x1e65c50; 1 drivers -v0x1e33f70_0 .net "AndNandOut", 0 0, L_0x1e66160; 1 drivers -v0x1e34050_0 .net "B", 0 0, L_0x1e66530; 1 drivers -v0x1e340d0_0 .alias "Command", 2 0, v0x1e48140_0; -L_0x1e66330 .part v0x1e49280_0, 0, 1; -S_0x1e33830 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0x1e33740; - .timescale -9 -12; -L_0x1e65e40/d .functor NOT 1, L_0x1e66330, C4<0>, C4<0>, C4<0>; -L_0x1e65e40 .delay (10000,10000,10000) L_0x1e65e40/d; -L_0x1e65f00/d .functor AND 1, L_0x1e65d10, L_0x1e65e40, C4<1>, C4<1>; -L_0x1e65f00 .delay (20000,20000,20000) L_0x1e65f00/d; -L_0x1e66010/d .functor AND 1, L_0x1e65c50, L_0x1e66330, C4<1>, C4<1>; -L_0x1e66010 .delay (20000,20000,20000) L_0x1e66010/d; -L_0x1e66160/d .functor OR 1, L_0x1e65f00, L_0x1e66010, C4<0>, C4<0>; -L_0x1e66160 .delay (20000,20000,20000) L_0x1e66160/d; -v0x1e33920_0 .net "S", 0 0, L_0x1e66330; 1 drivers -v0x1e339a0_0 .alias "in0", 0 0, v0x1e33e40_0; -v0x1e33a40_0 .alias "in1", 0 0, v0x1e33ec0_0; -v0x1e33ae0_0 .net "nS", 0 0, L_0x1e65e40; 1 drivers -v0x1e33b60_0 .net "out0", 0 0, L_0x1e65f00; 1 drivers -v0x1e33c00_0 .net "out1", 0 0, L_0x1e66010; 1 drivers -v0x1e33ce0_0 .alias "outfinal", 0 0, v0x1e33f70_0; -S_0x1e32a10 .scope generate, "andbits[2]" "andbits[2]" 3 169, 3 169, S_0x1e31c70; - .timescale -9 -12; -P_0x1e32b08 .param/l "i" 3 169, +C4<010>; -S_0x1e32b80 .scope module, "attempt" "AndNand" 3 171, 3 48, S_0x1e32a10; - .timescale -9 -12; -L_0x1e66620/d .functor NAND 1, L_0x1e66ee0, L_0x1e66f80, C4<1>, C4<1>; -L_0x1e66620 .delay (10000,10000,10000) L_0x1e66620/d; -L_0x1e66780/d .functor NOT 1, L_0x1e66620, C4<0>, C4<0>, C4<0>; -L_0x1e66780 .delay (10000,10000,10000) L_0x1e66780/d; -v0x1e331c0_0 .net "A", 0 0, L_0x1e66ee0; 1 drivers -v0x1e33280_0 .net "AandB", 0 0, L_0x1e66780; 1 drivers -v0x1e33300_0 .net "AnandB", 0 0, L_0x1e66620; 1 drivers -v0x1e333b0_0 .net "AndNandOut", 0 0, L_0x1e66bd0; 1 drivers -v0x1e33490_0 .net "B", 0 0, L_0x1e66f80; 1 drivers -v0x1e33510_0 .alias "Command", 2 0, v0x1e48140_0; -L_0x1e66da0 .part v0x1e49280_0, 0, 1; -S_0x1e32c70 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0x1e32b80; - .timescale -9 -12; -L_0x1e668b0/d .functor NOT 1, L_0x1e66da0, C4<0>, C4<0>, C4<0>; -L_0x1e668b0 .delay (10000,10000,10000) L_0x1e668b0/d; -L_0x1e66970/d .functor AND 1, L_0x1e66780, L_0x1e668b0, C4<1>, C4<1>; -L_0x1e66970 .delay (20000,20000,20000) L_0x1e66970/d; -L_0x1e66a80/d .functor AND 1, L_0x1e66620, L_0x1e66da0, C4<1>, C4<1>; -L_0x1e66a80 .delay (20000,20000,20000) L_0x1e66a80/d; -L_0x1e66bd0/d .functor OR 1, L_0x1e66970, L_0x1e66a80, C4<0>, C4<0>; -L_0x1e66bd0 .delay (20000,20000,20000) L_0x1e66bd0/d; -v0x1e32d60_0 .net "S", 0 0, L_0x1e66da0; 1 drivers -v0x1e32de0_0 .alias "in0", 0 0, v0x1e33280_0; -v0x1e32e80_0 .alias "in1", 0 0, v0x1e33300_0; -v0x1e32f20_0 .net "nS", 0 0, L_0x1e668b0; 1 drivers -v0x1e32fa0_0 .net "out0", 0 0, L_0x1e66970; 1 drivers -v0x1e33040_0 .net "out1", 0 0, L_0x1e66a80; 1 drivers -v0x1e33120_0 .alias "outfinal", 0 0, v0x1e333b0_0; -S_0x1e31de0 .scope generate, "andbits[3]" "andbits[3]" 3 169, 3 169, S_0x1e31c70; - .timescale -9 -12; -P_0x1e31ed8 .param/l "i" 3 169, +C4<011>; -S_0x1e31f70 .scope module, "attempt" "AndNand" 3 171, 3 48, S_0x1e31de0; - .timescale -9 -12; -L_0x1e670b0/d .functor NAND 1, L_0x1e59390, L_0x1e67b60, C4<1>, C4<1>; -L_0x1e670b0 .delay (10000,10000,10000) L_0x1e670b0/d; -L_0x1e671f0/d .functor NOT 1, L_0x1e670b0, C4<0>, C4<0>, C4<0>; -L_0x1e671f0 .delay (10000,10000,10000) L_0x1e671f0/d; -v0x1e32600_0 .net "A", 0 0, L_0x1e59390; 1 drivers -v0x1e326c0_0 .net "AandB", 0 0, L_0x1e671f0; 1 drivers -v0x1e32740_0 .net "AnandB", 0 0, L_0x1e670b0; 1 drivers -v0x1e327f0_0 .net "AndNandOut", 0 0, L_0x1e67640; 1 drivers -v0x1e328d0_0 .net "B", 0 0, L_0x1e67b60; 1 drivers -v0x1e32950_0 .alias "Command", 2 0, v0x1e48140_0; -L_0x1e67810 .part v0x1e49280_0, 0, 1; -S_0x1e32060 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0x1e31f70; - .timescale -9 -12; -L_0x1e67320/d .functor NOT 1, L_0x1e67810, C4<0>, C4<0>, C4<0>; -L_0x1e67320 .delay (10000,10000,10000) L_0x1e67320/d; -L_0x1e673e0/d .functor AND 1, L_0x1e671f0, L_0x1e67320, C4<1>, C4<1>; -L_0x1e673e0 .delay (20000,20000,20000) L_0x1e673e0/d; -L_0x1e674f0/d .functor AND 1, L_0x1e670b0, L_0x1e67810, C4<1>, C4<1>; -L_0x1e674f0 .delay (20000,20000,20000) L_0x1e674f0/d; -L_0x1e67640/d .functor OR 1, L_0x1e673e0, L_0x1e674f0, C4<0>, C4<0>; -L_0x1e67640 .delay (20000,20000,20000) L_0x1e67640/d; -v0x1e32150_0 .net "S", 0 0, L_0x1e67810; 1 drivers -v0x1e321f0_0 .alias "in0", 0 0, v0x1e326c0_0; -v0x1e32290_0 .alias "in1", 0 0, v0x1e32740_0; -v0x1e32330_0 .net "nS", 0 0, L_0x1e67320; 1 drivers -v0x1e323e0_0 .net "out0", 0 0, L_0x1e673e0; 1 drivers -v0x1e32480_0 .net "out1", 0 0, L_0x1e674f0; 1 drivers -v0x1e32560_0 .alias "outfinal", 0 0, v0x1e327f0_0; -S_0x1e2ca50 .scope module, "trial2" "OrNorXor32" 3 281, 3 177, S_0x1da9070; - .timescale -9 -12; -P_0x1e2bba8 .param/l "size" 3 184, +C4<0100>; -v0x1e319e0_0 .alias "A", 3 0, v0x1e47f20_0; -v0x1e31a60_0 .alias "B", 3 0, v0x1e48040_0; -v0x1e31ae0_0 .alias "Command", 2 0, v0x1e48140_0; -v0x1e31bf0_0 .alias "OrNorXorOut", 3 0, v0x1e49380_0; -L_0x1e69760 .part/pv L_0x1e694f0, 1, 1, 4; -L_0x1e69800 .part v0x1e49000_0, 1, 1; -L_0x1e698a0 .part v0x1e49200_0, 1, 1; -L_0x1e6aa60 .part/pv L_0x1e6a7f0, 2, 1, 4; -L_0x1e6ab00 .part v0x1e49000_0, 2, 1; -L_0x1e6aba0 .part v0x1e49200_0, 2, 1; -L_0x1e6bd60 .part/pv L_0x1e6baf0, 3, 1, 4; -L_0x1e6be00 .part v0x1e49000_0, 3, 1; -L_0x1e6bea0 .part v0x1e49200_0, 3, 1; -L_0x1e6d050 .part/pv L_0x1e6cde0, 0, 1, 4; -L_0x1e6d150 .part v0x1e49000_0, 0, 1; -L_0x1e6d1f0 .part v0x1e49200_0, 0, 1; -S_0x1e307d0 .scope module, "attempt2" "OrNorXor" 3 192, 3 64, S_0x1e2ca50; - .timescale -9 -12; -L_0x1e6bf40/d .functor NOR 1, L_0x1e6d150, L_0x1e6d1f0, C4<0>, C4<0>; -L_0x1e6bf40 .delay (10000,10000,10000) L_0x1e6bf40/d; -L_0x1e6c040/d .functor NOT 1, L_0x1e6bf40, C4<0>, C4<0>, C4<0>; -L_0x1e6c040 .delay (10000,10000,10000) L_0x1e6c040/d; -L_0x1e6c170/d .functor NAND 1, L_0x1e6d150, L_0x1e6d1f0, C4<1>, C4<1>; -L_0x1e6c170 .delay (10000,10000,10000) L_0x1e6c170/d; -L_0x1e6c2d0/d .functor NAND 1, L_0x1e6c170, L_0x1e6c040, C4<1>, C4<1>; -L_0x1e6c2d0 .delay (10000,10000,10000) L_0x1e6c2d0/d; -L_0x1e6c3e0/d .functor NOT 1, L_0x1e6c2d0, C4<0>, C4<0>, C4<0>; -L_0x1e6c3e0 .delay (10000,10000,10000) L_0x1e6c3e0/d; -v0x1e31320_0 .net "A", 0 0, L_0x1e6d150; 1 drivers -v0x1e313c0_0 .net "AnandB", 0 0, L_0x1e6c170; 1 drivers -v0x1e31460_0 .net "AnorB", 0 0, L_0x1e6bf40; 1 drivers -v0x1e314e0_0 .net "AorB", 0 0, L_0x1e6c040; 1 drivers -v0x1e315c0_0 .net "AxorB", 0 0, L_0x1e6c3e0; 1 drivers -v0x1e31670_0 .net "B", 0 0, L_0x1e6d1f0; 1 drivers -v0x1e31730_0 .alias "Command", 2 0, v0x1e48140_0; -v0x1e317b0_0 .net "OrNorXorOut", 0 0, L_0x1e6cde0; 1 drivers -v0x1e31830_0 .net "XorNor", 0 0, L_0x1e6c860; 1 drivers -v0x1e31900_0 .net "nXor", 0 0, L_0x1e6c2d0; 1 drivers -L_0x1e6c9e0 .part v0x1e49280_0, 2, 1; -L_0x1e6cfb0 .part v0x1e49280_0, 0, 1; -S_0x1e30db0 .scope module, "mux0" "TwoInMux" 3 83, 3 8, S_0x1e307d0; - .timescale -9 -12; -L_0x1e6c540/d .functor NOT 1, L_0x1e6c9e0, C4<0>, C4<0>, C4<0>; -L_0x1e6c540 .delay (10000,10000,10000) L_0x1e6c540/d; -L_0x1e6c600/d .functor AND 1, L_0x1e6c3e0, L_0x1e6c540, C4<1>, C4<1>; -L_0x1e6c600 .delay (20000,20000,20000) L_0x1e6c600/d; -L_0x1e6c710/d .functor AND 1, L_0x1e6bf40, L_0x1e6c9e0, C4<1>, C4<1>; -L_0x1e6c710 .delay (20000,20000,20000) L_0x1e6c710/d; -L_0x1e6c860/d .functor OR 1, L_0x1e6c600, L_0x1e6c710, C4<0>, C4<0>; -L_0x1e6c860 .delay (20000,20000,20000) L_0x1e6c860/d; -v0x1e30ea0_0 .net "S", 0 0, L_0x1e6c9e0; 1 drivers -v0x1e30f60_0 .alias "in0", 0 0, v0x1e315c0_0; -v0x1e31000_0 .alias "in1", 0 0, v0x1e31460_0; -v0x1e310a0_0 .net "nS", 0 0, L_0x1e6c540; 1 drivers -v0x1e31120_0 .net "out0", 0 0, L_0x1e6c600; 1 drivers -v0x1e311c0_0 .net "out1", 0 0, L_0x1e6c710; 1 drivers -v0x1e312a0_0 .alias "outfinal", 0 0, v0x1e31830_0; -S_0x1e308c0 .scope module, "mux1" "TwoInMux" 3 84, 3 8, S_0x1e307d0; - .timescale -9 -12; -L_0x1e6ca80/d .functor NOT 1, L_0x1e6cfb0, C4<0>, C4<0>, C4<0>; -L_0x1e6ca80 .delay (10000,10000,10000) L_0x1e6ca80/d; -L_0x1e6cb40/d .functor AND 1, L_0x1e6c860, L_0x1e6ca80, C4<1>, C4<1>; -L_0x1e6cb40 .delay (20000,20000,20000) L_0x1e6cb40/d; -L_0x1e6cc90/d .functor AND 1, L_0x1e6c040, L_0x1e6cfb0, C4<1>, C4<1>; -L_0x1e6cc90 .delay (20000,20000,20000) L_0x1e6cc90/d; -L_0x1e6cde0/d .functor OR 1, L_0x1e6cb40, L_0x1e6cc90, C4<0>, C4<0>; -L_0x1e6cde0 .delay (20000,20000,20000) L_0x1e6cde0/d; -v0x1e309b0_0 .net "S", 0 0, L_0x1e6cfb0; 1 drivers -v0x1e30a30_0 .alias "in0", 0 0, v0x1e31830_0; -v0x1e30ab0_0 .alias "in1", 0 0, v0x1e314e0_0; -v0x1e30b50_0 .net "nS", 0 0, L_0x1e6ca80; 1 drivers -v0x1e30bd0_0 .net "out0", 0 0, L_0x1e6cb40; 1 drivers -v0x1e30c70_0 .net "out1", 0 0, L_0x1e6cc90; 1 drivers -v0x1e30d10_0 .alias "outfinal", 0 0, v0x1e317b0_0; -S_0x1e2f3d0 .scope generate, "orbits[1]" "orbits[1]" 3 196, 3 196, S_0x1e2ca50; - .timescale -9 -12; -P_0x1e2f0b8 .param/l "i" 3 196, +C4<01>; -S_0x1e2f500 .scope module, "attempt" "OrNorXor" 3 198, 3 64, S_0x1e2f3d0; - .timescale -9 -12; -L_0x1e684b0/d .functor NOR 1, L_0x1e69800, L_0x1e698a0, C4<0>, C4<0>; -L_0x1e684b0 .delay (10000,10000,10000) L_0x1e684b0/d; -L_0x1e68750/d .functor NOT 1, L_0x1e684b0, C4<0>, C4<0>, C4<0>; -L_0x1e68750 .delay (10000,10000,10000) L_0x1e68750/d; -L_0x1e68880/d .functor NAND 1, L_0x1e69800, L_0x1e698a0, C4<1>, C4<1>; -L_0x1e68880 .delay (10000,10000,10000) L_0x1e68880/d; -L_0x1e689e0/d .functor NAND 1, L_0x1e68880, L_0x1e68750, C4<1>, C4<1>; -L_0x1e689e0 .delay (10000,10000,10000) L_0x1e689e0/d; -L_0x1e68af0/d .functor NOT 1, L_0x1e689e0, C4<0>, C4<0>, C4<0>; -L_0x1e68af0 .delay (10000,10000,10000) L_0x1e68af0/d; -v0x1e30090_0 .net "A", 0 0, L_0x1e69800; 1 drivers -v0x1e30130_0 .net "AnandB", 0 0, L_0x1e68880; 1 drivers -v0x1e301d0_0 .net "AnorB", 0 0, L_0x1e684b0; 1 drivers -v0x1e30280_0 .net "AorB", 0 0, L_0x1e68750; 1 drivers -v0x1e30360_0 .net "AxorB", 0 0, L_0x1e68af0; 1 drivers -v0x1e30410_0 .net "B", 0 0, L_0x1e698a0; 1 drivers -v0x1e304d0_0 .alias "Command", 2 0, v0x1e48140_0; -v0x1e30550_0 .net "OrNorXorOut", 0 0, L_0x1e694f0; 1 drivers -v0x1e30620_0 .net "XorNor", 0 0, L_0x1e68f70; 1 drivers -v0x1e306f0_0 .net "nXor", 0 0, L_0x1e689e0; 1 drivers -L_0x1e690f0 .part v0x1e49280_0, 2, 1; -L_0x1e696c0 .part v0x1e49280_0, 0, 1; -S_0x1e2fb20 .scope module, "mux0" "TwoInMux" 3 83, 3 8, S_0x1e2f500; - .timescale -9 -12; -L_0x1e68c50/d .functor NOT 1, L_0x1e690f0, C4<0>, C4<0>, C4<0>; -L_0x1e68c50 .delay (10000,10000,10000) L_0x1e68c50/d; -L_0x1e68d10/d .functor AND 1, L_0x1e68af0, L_0x1e68c50, C4<1>, C4<1>; -L_0x1e68d10 .delay (20000,20000,20000) L_0x1e68d10/d; -L_0x1e68e20/d .functor AND 1, L_0x1e684b0, L_0x1e690f0, C4<1>, C4<1>; -L_0x1e68e20 .delay (20000,20000,20000) L_0x1e68e20/d; -L_0x1e68f70/d .functor OR 1, L_0x1e68d10, L_0x1e68e20, C4<0>, C4<0>; -L_0x1e68f70 .delay (20000,20000,20000) L_0x1e68f70/d; -v0x1e2fc10_0 .net "S", 0 0, L_0x1e690f0; 1 drivers -v0x1e2fcd0_0 .alias "in0", 0 0, v0x1e30360_0; -v0x1e2fd70_0 .alias "in1", 0 0, v0x1e301d0_0; -v0x1e2fe10_0 .net "nS", 0 0, L_0x1e68c50; 1 drivers -v0x1e2fe90_0 .net "out0", 0 0, L_0x1e68d10; 1 drivers -v0x1e2ff30_0 .net "out1", 0 0, L_0x1e68e20; 1 drivers -v0x1e30010_0 .alias "outfinal", 0 0, v0x1e30620_0; -S_0x1e2f5f0 .scope module, "mux1" "TwoInMux" 3 84, 3 8, S_0x1e2f500; - .timescale -9 -12; -L_0x1e69190/d .functor NOT 1, L_0x1e696c0, C4<0>, C4<0>, C4<0>; -L_0x1e69190 .delay (10000,10000,10000) L_0x1e69190/d; -L_0x1e69250/d .functor AND 1, L_0x1e68f70, L_0x1e69190, C4<1>, C4<1>; -L_0x1e69250 .delay (20000,20000,20000) L_0x1e69250/d; -L_0x1e693a0/d .functor AND 1, L_0x1e68750, L_0x1e696c0, C4<1>, C4<1>; -L_0x1e693a0 .delay (20000,20000,20000) L_0x1e693a0/d; -L_0x1e694f0/d .functor OR 1, L_0x1e69250, L_0x1e693a0, C4<0>, C4<0>; -L_0x1e694f0 .delay (20000,20000,20000) L_0x1e694f0/d; -v0x1e2f6e0_0 .net "S", 0 0, L_0x1e696c0; 1 drivers -v0x1e2f760_0 .alias "in0", 0 0, v0x1e30620_0; -v0x1e2f7e0_0 .alias "in1", 0 0, v0x1e30280_0; -v0x1e2f880_0 .net "nS", 0 0, L_0x1e69190; 1 drivers -v0x1e2f900_0 .net "out0", 0 0, L_0x1e69250; 1 drivers -v0x1e2f9a0_0 .net "out1", 0 0, L_0x1e693a0; 1 drivers -v0x1e2fa80_0 .alias "outfinal", 0 0, v0x1e30550_0; -S_0x1e2dfb0 .scope generate, "orbits[2]" "orbits[2]" 3 196, 3 196, S_0x1e2ca50; - .timescale -9 -12; -P_0x1e2dd28 .param/l "i" 3 196, +C4<010>; -S_0x1e2e0e0 .scope module, "attempt" "OrNorXor" 3 198, 3 64, S_0x1e2dfb0; - .timescale -9 -12; -L_0x1e69940/d .functor NOR 1, L_0x1e6ab00, L_0x1e6aba0, C4<0>, C4<0>; -L_0x1e69940 .delay (10000,10000,10000) L_0x1e69940/d; -L_0x1e69a50/d .functor NOT 1, L_0x1e69940, C4<0>, C4<0>, C4<0>; -L_0x1e69a50 .delay (10000,10000,10000) L_0x1e69a50/d; -L_0x1e69b80/d .functor NAND 1, L_0x1e6ab00, L_0x1e6aba0, C4<1>, C4<1>; -L_0x1e69b80 .delay (10000,10000,10000) L_0x1e69b80/d; -L_0x1e69ce0/d .functor NAND 1, L_0x1e69b80, L_0x1e69a50, C4<1>, C4<1>; -L_0x1e69ce0 .delay (10000,10000,10000) L_0x1e69ce0/d; -L_0x1e69df0/d .functor NOT 1, L_0x1e69ce0, C4<0>, C4<0>, C4<0>; -L_0x1e69df0 .delay (10000,10000,10000) L_0x1e69df0/d; -v0x1e2ecb0_0 .net "A", 0 0, L_0x1e6ab00; 1 drivers -v0x1e2ed50_0 .net "AnandB", 0 0, L_0x1e69b80; 1 drivers -v0x1e2edf0_0 .net "AnorB", 0 0, L_0x1e69940; 1 drivers -v0x1e2eea0_0 .net "AorB", 0 0, L_0x1e69a50; 1 drivers -v0x1e2ef80_0 .net "AxorB", 0 0, L_0x1e69df0; 1 drivers -v0x1e2f030_0 .net "B", 0 0, L_0x1e6aba0; 1 drivers -v0x1e2f0f0_0 .alias "Command", 2 0, v0x1e48140_0; -v0x1e2f170_0 .net "OrNorXorOut", 0 0, L_0x1e6a7f0; 1 drivers -v0x1e2f220_0 .net "XorNor", 0 0, L_0x1e6a270; 1 drivers -v0x1e2f2f0_0 .net "nXor", 0 0, L_0x1e69ce0; 1 drivers -L_0x1e6a3f0 .part v0x1e49280_0, 2, 1; -L_0x1e6a9c0 .part v0x1e49280_0, 0, 1; -S_0x1e2e740 .scope module, "mux0" "TwoInMux" 3 83, 3 8, S_0x1e2e0e0; - .timescale -9 -12; -L_0x1e69f50/d .functor NOT 1, L_0x1e6a3f0, C4<0>, C4<0>, C4<0>; -L_0x1e69f50 .delay (10000,10000,10000) L_0x1e69f50/d; -L_0x1e6a010/d .functor AND 1, L_0x1e69df0, L_0x1e69f50, C4<1>, C4<1>; -L_0x1e6a010 .delay (20000,20000,20000) L_0x1e6a010/d; -L_0x1e6a120/d .functor AND 1, L_0x1e69940, L_0x1e6a3f0, C4<1>, C4<1>; -L_0x1e6a120 .delay (20000,20000,20000) L_0x1e6a120/d; -L_0x1e6a270/d .functor OR 1, L_0x1e6a010, L_0x1e6a120, C4<0>, C4<0>; -L_0x1e6a270 .delay (20000,20000,20000) L_0x1e6a270/d; -v0x1e2e830_0 .net "S", 0 0, L_0x1e6a3f0; 1 drivers -v0x1e2e8f0_0 .alias "in0", 0 0, v0x1e2ef80_0; -v0x1e2e990_0 .alias "in1", 0 0, v0x1e2edf0_0; -v0x1e2ea30_0 .net "nS", 0 0, L_0x1e69f50; 1 drivers -v0x1e2eab0_0 .net "out0", 0 0, L_0x1e6a010; 1 drivers -v0x1e2eb50_0 .net "out1", 0 0, L_0x1e6a120; 1 drivers -v0x1e2ec30_0 .alias "outfinal", 0 0, v0x1e2f220_0; -S_0x1e2e1d0 .scope module, "mux1" "TwoInMux" 3 84, 3 8, S_0x1e2e0e0; - .timescale -9 -12; -L_0x1e6a490/d .functor NOT 1, L_0x1e6a9c0, C4<0>, C4<0>, C4<0>; -L_0x1e6a490 .delay (10000,10000,10000) L_0x1e6a490/d; -L_0x1e6a550/d .functor AND 1, L_0x1e6a270, L_0x1e6a490, C4<1>, C4<1>; -L_0x1e6a550 .delay (20000,20000,20000) L_0x1e6a550/d; -L_0x1e6a6a0/d .functor AND 1, L_0x1e69a50, L_0x1e6a9c0, C4<1>, C4<1>; -L_0x1e6a6a0 .delay (20000,20000,20000) L_0x1e6a6a0/d; -L_0x1e6a7f0/d .functor OR 1, L_0x1e6a550, L_0x1e6a6a0, C4<0>, C4<0>; -L_0x1e6a7f0 .delay (20000,20000,20000) L_0x1e6a7f0/d; -v0x1e2e2c0_0 .net "S", 0 0, L_0x1e6a9c0; 1 drivers -v0x1e2e360_0 .alias "in0", 0 0, v0x1e2f220_0; -v0x1e2e400_0 .alias "in1", 0 0, v0x1e2eea0_0; -v0x1e2e4a0_0 .net "nS", 0 0, L_0x1e6a490; 1 drivers -v0x1e2e520_0 .net "out0", 0 0, L_0x1e6a550; 1 drivers -v0x1e2e5c0_0 .net "out1", 0 0, L_0x1e6a6a0; 1 drivers -v0x1e2e6a0_0 .alias "outfinal", 0 0, v0x1e2f170_0; -S_0x1e2cbc0 .scope generate, "orbits[3]" "orbits[3]" 3 196, 3 196, S_0x1e2ca50; - .timescale -9 -12; -P_0x1e2ccb8 .param/l "i" 3 196, +C4<011>; -S_0x1e2cd50 .scope module, "attempt" "OrNorXor" 3 198, 3 64, S_0x1e2cbc0; - .timescale -9 -12; -L_0x1e6ac80/d .functor NOR 1, L_0x1e6be00, L_0x1e6bea0, C4<0>, C4<0>; -L_0x1e6ac80 .delay (10000,10000,10000) L_0x1e6ac80/d; -L_0x1e6ad70/d .functor NOT 1, L_0x1e6ac80, C4<0>, C4<0>, C4<0>; -L_0x1e6ad70 .delay (10000,10000,10000) L_0x1e6ad70/d; -L_0x1e6ae80/d .functor NAND 1, L_0x1e6be00, L_0x1e6bea0, C4<1>, C4<1>; -L_0x1e6ae80 .delay (10000,10000,10000) L_0x1e6ae80/d; -L_0x1e6afe0/d .functor NAND 1, L_0x1e6ae80, L_0x1e6ad70, C4<1>, C4<1>; -L_0x1e6afe0 .delay (10000,10000,10000) L_0x1e6afe0/d; -L_0x1e6b0f0/d .functor NOT 1, L_0x1e6afe0, C4<0>, C4<0>, C4<0>; -L_0x1e6b0f0 .delay (10000,10000,10000) L_0x1e6b0f0/d; -v0x1e2d920_0 .net "A", 0 0, L_0x1e6be00; 1 drivers -v0x1e2d9c0_0 .net "AnandB", 0 0, L_0x1e6ae80; 1 drivers -v0x1e2da60_0 .net "AnorB", 0 0, L_0x1e6ac80; 1 drivers -v0x1e2db10_0 .net "AorB", 0 0, L_0x1e6ad70; 1 drivers -v0x1e2dbf0_0 .net "AxorB", 0 0, L_0x1e6b0f0; 1 drivers -v0x1e2dca0_0 .net "B", 0 0, L_0x1e6bea0; 1 drivers -v0x1e2dd60_0 .alias "Command", 2 0, v0x1e48140_0; -v0x1e2dde0_0 .net "OrNorXorOut", 0 0, L_0x1e6baf0; 1 drivers -v0x1e2de60_0 .net "XorNor", 0 0, L_0x1e6b570; 1 drivers -v0x1e2df30_0 .net "nXor", 0 0, L_0x1e6afe0; 1 drivers -L_0x1e6b6f0 .part v0x1e49280_0, 2, 1; -L_0x1e6bcc0 .part v0x1e49280_0, 0, 1; -S_0x1e2d3b0 .scope module, "mux0" "TwoInMux" 3 83, 3 8, S_0x1e2cd50; - .timescale -9 -12; -L_0x1e6b250/d .functor NOT 1, L_0x1e6b6f0, C4<0>, C4<0>, C4<0>; -L_0x1e6b250 .delay (10000,10000,10000) L_0x1e6b250/d; -L_0x1e6b310/d .functor AND 1, L_0x1e6b0f0, L_0x1e6b250, C4<1>, C4<1>; -L_0x1e6b310 .delay (20000,20000,20000) L_0x1e6b310/d; -L_0x1e6b420/d .functor AND 1, L_0x1e6ac80, L_0x1e6b6f0, C4<1>, C4<1>; -L_0x1e6b420 .delay (20000,20000,20000) L_0x1e6b420/d; -L_0x1e6b570/d .functor OR 1, L_0x1e6b310, L_0x1e6b420, C4<0>, C4<0>; -L_0x1e6b570 .delay (20000,20000,20000) L_0x1e6b570/d; -v0x1e2d4a0_0 .net "S", 0 0, L_0x1e6b6f0; 1 drivers -v0x1e2d560_0 .alias "in0", 0 0, v0x1e2dbf0_0; -v0x1e2d600_0 .alias "in1", 0 0, v0x1e2da60_0; -v0x1e2d6a0_0 .net "nS", 0 0, L_0x1e6b250; 1 drivers -v0x1e2d720_0 .net "out0", 0 0, L_0x1e6b310; 1 drivers -v0x1e2d7c0_0 .net "out1", 0 0, L_0x1e6b420; 1 drivers -v0x1e2d8a0_0 .alias "outfinal", 0 0, v0x1e2de60_0; -S_0x1e2ce40 .scope module, "mux1" "TwoInMux" 3 84, 3 8, S_0x1e2cd50; - .timescale -9 -12; -L_0x1e6b790/d .functor NOT 1, L_0x1e6bcc0, C4<0>, C4<0>, C4<0>; -L_0x1e6b790 .delay (10000,10000,10000) L_0x1e6b790/d; -L_0x1e6b850/d .functor AND 1, L_0x1e6b570, L_0x1e6b790, C4<1>, C4<1>; -L_0x1e6b850 .delay (20000,20000,20000) L_0x1e6b850/d; -L_0x1e6b9a0/d .functor AND 1, L_0x1e6ad70, L_0x1e6bcc0, C4<1>, C4<1>; -L_0x1e6b9a0 .delay (20000,20000,20000) L_0x1e6b9a0/d; -L_0x1e6baf0/d .functor OR 1, L_0x1e6b850, L_0x1e6b9a0, C4<0>, C4<0>; -L_0x1e6baf0 .delay (20000,20000,20000) L_0x1e6baf0/d; -v0x1e2cf30_0 .net "S", 0 0, L_0x1e6bcc0; 1 drivers -v0x1e2cfd0_0 .alias "in0", 0 0, v0x1e2de60_0; -v0x1e2d070_0 .alias "in1", 0 0, v0x1e2db10_0; -v0x1e2d110_0 .net "nS", 0 0, L_0x1e6b790; 1 drivers -v0x1e2d190_0 .net "out0", 0 0, L_0x1e6b850; 1 drivers -v0x1e2d230_0 .net "out1", 0 0, L_0x1e6b9a0; 1 drivers -v0x1e2d310_0 .alias "outfinal", 0 0, v0x1e2dde0_0; -S_0x1e2c0d0 .scope module, "ZeroMux0case" "FourInMux" 3 283, 3 24, S_0x1da9070; - .timescale -9 -12; -L_0x1e6d0f0/d .functor NOT 1, L_0x1e5f8c0, C4<0>, C4<0>, C4<0>; -L_0x1e6d0f0 .delay (10000,10000,10000) L_0x1e6d0f0/d; -L_0x1e6d340/d .functor NOT 1, L_0x1e5f9f0, C4<0>, C4<0>, C4<0>; -L_0x1e6d340 .delay (10000,10000,10000) L_0x1e6d340/d; -L_0x1e6d400/d .functor NAND 1, L_0x1e6d0f0, L_0x1e6d340, L_0x1e6da30, C4<1>; -L_0x1e6d400 .delay (10000,10000,10000) L_0x1e6d400/d; -L_0x1e6d4f0/d .functor NAND 1, L_0x1e5f8c0, L_0x1e6d340, L_0x1e6dad0, C4<1>; -L_0x1e6d4f0 .delay (10000,10000,10000) L_0x1e6d4f0/d; -L_0x1e6d5e0/d .functor NAND 1, L_0x1e6d0f0, L_0x1e5f9f0, L_0x1e6db70, C4<1>; -L_0x1e6d5e0 .delay (10000,10000,10000) L_0x1e6d5e0/d; -L_0x1e6d6d0/d .functor NAND 1, L_0x1e5f8c0, L_0x1e5f9f0, L_0x1e6df50, C4<1>; -L_0x1e6d6d0 .delay (10000,10000,10000) L_0x1e6d6d0/d; -L_0x1e6d7b0/d .functor NAND 1, L_0x1e6d400, L_0x1e6d4f0, L_0x1e6d5e0, L_0x1e6d6d0; -L_0x1e6d7b0 .delay (10000,10000,10000) L_0x1e6d7b0/d; -v0x1e2c1c0_0 .net "S0", 0 0, L_0x1e5f8c0; 1 drivers -v0x1e2c280_0 .net "S1", 0 0, L_0x1e5f9f0; 1 drivers -v0x1e2c320_0 .net "in0", 0 0, L_0x1e6da30; 1 drivers -v0x1e2c3c0_0 .net "in1", 0 0, L_0x1e6dad0; 1 drivers -v0x1e2c440_0 .net "in2", 0 0, L_0x1e6db70; 1 drivers -v0x1e2c4e0_0 .net "in3", 0 0, L_0x1e6df50; 1 drivers -v0x1e2c580_0 .net "nS0", 0 0, L_0x1e6d0f0; 1 drivers -v0x1e2c620_0 .net "nS1", 0 0, L_0x1e6d340; 1 drivers -v0x1e2c6c0_0 .net "out", 0 0, L_0x1e6d7b0; 1 drivers -v0x1e2c760_0 .net "out0", 0 0, L_0x1e6d400; 1 drivers -v0x1e2c800_0 .net "out1", 0 0, L_0x1e6d4f0; 1 drivers -v0x1e2c8a0_0 .net "out2", 0 0, L_0x1e6d5e0; 1 drivers -v0x1e2c9b0_0 .net "out3", 0 0, L_0x1e6d6d0; 1 drivers -S_0x1e2b710 .scope module, "OneMux0case" "FourInMux" 3 284, 3 24, S_0x1da9070; - .timescale -9 -12; -L_0x1e6dcd0/d .functor NOT 1, L_0x1e6e860, C4<0>, C4<0>, C4<0>; -L_0x1e6dcd0 .delay (10000,10000,10000) L_0x1e6dcd0/d; -L_0x1e6ddc0/d .functor NOT 1, L_0x1e6e040, C4<0>, C4<0>, C4<0>; -L_0x1e6ddc0 .delay (10000,10000,10000) L_0x1e6ddc0/d; -L_0x1e6de60/d .functor NAND 1, L_0x1e6dcd0, L_0x1e6ddc0, L_0x1e6e170, C4<1>; -L_0x1e6de60 .delay (10000,10000,10000) L_0x1e6de60/d; -L_0x1e6e320/d .functor NAND 1, L_0x1e6e860, L_0x1e6ddc0, L_0x1e6ebf0, C4<1>; -L_0x1e6e320 .delay (10000,10000,10000) L_0x1e6e320/d; -L_0x1e6e410/d .functor NAND 1, L_0x1e6dcd0, L_0x1e6e040, L_0x1e6ec90, C4<1>; -L_0x1e6e410 .delay (10000,10000,10000) L_0x1e6e410/d; -L_0x1e6e500/d .functor NAND 1, L_0x1e6e860, L_0x1e6e040, L_0x1e6e990, C4<1>; -L_0x1e6e500 .delay (10000,10000,10000) L_0x1e6e500/d; -L_0x1e6e5e0/d .functor NAND 1, L_0x1e6de60, L_0x1e6e320, L_0x1e6e410, L_0x1e6e500; -L_0x1e6e5e0 .delay (10000,10000,10000) L_0x1e6e5e0/d; -v0x1e2b800_0 .net "S0", 0 0, L_0x1e6e860; 1 drivers -v0x1e2b8c0_0 .net "S1", 0 0, L_0x1e6e040; 1 drivers -v0x1e2b960_0 .net "in0", 0 0, L_0x1e6e170; 1 drivers -v0x1e2ba00_0 .net "in1", 0 0, L_0x1e6ebf0; 1 drivers -v0x1e2ba80_0 .net "in2", 0 0, L_0x1e6ec90; 1 drivers -v0x1e2bb20_0 .net "in3", 0 0, L_0x1e6e990; 1 drivers -v0x1e2bc00_0 .net "nS0", 0 0, L_0x1e6dcd0; 1 drivers -v0x1e2bca0_0 .net "nS1", 0 0, L_0x1e6ddc0; 1 drivers -v0x1e2bd40_0 .net "out", 0 0, L_0x1e6e5e0; 1 drivers -v0x1e2bde0_0 .net "out0", 0 0, L_0x1e6de60; 1 drivers -v0x1e2be80_0 .net "out1", 0 0, L_0x1e6e320; 1 drivers -v0x1e2bf20_0 .net "out2", 0 0, L_0x1e6e410; 1 drivers -v0x1e2c030_0 .net "out3", 0 0, L_0x1e6e500; 1 drivers -S_0x1e2b1c0 .scope module, "TwoMux0case" "TwoInMux" 3 285, 3 8, S_0x1da9070; - .timescale -9 -12; -L_0x1e6ea80/d .functor NOT 1, L_0x1e6ed30, C4<0>, C4<0>, C4<0>; -L_0x1e6ea80 .delay (10000,10000,10000) L_0x1e6ea80/d; -L_0x1e6eb70/d .functor AND 1, L_0x1e6edd0, L_0x1e6ea80, C4<1>, C4<1>; -L_0x1e6eb70 .delay (20000,20000,20000) L_0x1e6eb70/d; -L_0x1e6f030/d .functor AND 1, L_0x1e6eec0, L_0x1e6ed30, C4<1>, C4<1>; -L_0x1e6f030 .delay (20000,20000,20000) L_0x1e6f030/d; -L_0x1e6f120/d .functor OR 1, L_0x1e6eb70, L_0x1e6f030, C4<0>, C4<0>; -L_0x1e6f120 .delay (20000,20000,20000) L_0x1e6f120/d; -v0x1e2b2b0_0 .net "S", 0 0, L_0x1e6ed30; 1 drivers -v0x1e2b370_0 .net "in0", 0 0, L_0x1e6edd0; 1 drivers -v0x1e2b410_0 .net "in1", 0 0, L_0x1e6eec0; 1 drivers -v0x1e2b4b0_0 .net "nS", 0 0, L_0x1e6ea80; 1 drivers -v0x1e2b530_0 .net "out0", 0 0, L_0x1e6eb70; 1 drivers -v0x1e2b5d0_0 .net "out1", 0 0, L_0x1e6f030; 1 drivers -v0x1e2b670_0 .net "outfinal", 0 0, L_0x1e6f120; 1 drivers -S_0x1e29640 .scope generate, "muxbits[1]" "muxbits[1]" 3 290, 3 290, S_0x1da9070; - .timescale -9 -12; -P_0x1e28638 .param/l "i" 3 290, +C4<01>; -L_0x1e59f90/d .functor OR 1, L_0x1e5a090, L_0x1e59e50, C4<0>, C4<0>; -L_0x1e59f90 .delay (20000,20000,20000) L_0x1e59f90/d; -v0x1e2b060_0 .net *"_s15", 0 0, L_0x1e5a090; 1 drivers -v0x1e2b120_0 .net *"_s16", 0 0, L_0x1e59e50; 1 drivers -S_0x1e2a6e0 .scope module, "ZeroMux" "FourInMux" 3 292, 3 24, S_0x1e29640; - .timescale -9 -12; -L_0x1e57850/d .functor NOT 1, L_0x1e58190, C4<0>, C4<0>, C4<0>; -L_0x1e57850 .delay (10000,10000,10000) L_0x1e57850/d; -L_0x1e57aa0/d .functor NOT 1, L_0x1e582c0, C4<0>, C4<0>, C4<0>; -L_0x1e57aa0 .delay (10000,10000,10000) L_0x1e57aa0/d; -L_0x1e57b60/d .functor NAND 1, L_0x1e57850, L_0x1e57aa0, L_0x1e583f0, C4<1>; -L_0x1e57b60 .delay (10000,10000,10000) L_0x1e57b60/d; -L_0x1e57c50/d .functor NAND 1, L_0x1e58190, L_0x1e57aa0, L_0x1e58490, C4<1>; -L_0x1e57c50 .delay (10000,10000,10000) L_0x1e57c50/d; -L_0x1e57d40/d .functor NAND 1, L_0x1e57850, L_0x1e582c0, L_0x1e58530, C4<1>; -L_0x1e57d40 .delay (10000,10000,10000) L_0x1e57d40/d; -L_0x1e57e30/d .functor NAND 1, L_0x1e58190, L_0x1e582c0, L_0x1e58730, C4<1>; -L_0x1e57e30 .delay (10000,10000,10000) L_0x1e57e30/d; -L_0x1e57f10/d .functor NAND 1, L_0x1e57b60, L_0x1e57c50, L_0x1e57d40, L_0x1e57e30; -L_0x1e57f10 .delay (10000,10000,10000) L_0x1e57f10/d; -v0x1e2a7d0_0 .net "S0", 0 0, L_0x1e58190; 1 drivers -v0x1e2a890_0 .net "S1", 0 0, L_0x1e582c0; 1 drivers -v0x1e2a930_0 .net "in0", 0 0, L_0x1e583f0; 1 drivers -v0x1e2a9d0_0 .net "in1", 0 0, L_0x1e58490; 1 drivers -v0x1e2aa50_0 .net "in2", 0 0, L_0x1e58530; 1 drivers -v0x1e2aaf0_0 .net "in3", 0 0, L_0x1e58730; 1 drivers -v0x1e2ab90_0 .net "nS0", 0 0, L_0x1e57850; 1 drivers -v0x1e2ac30_0 .net "nS1", 0 0, L_0x1e57aa0; 1 drivers -v0x1e2acd0_0 .net "out", 0 0, L_0x1e57f10; 1 drivers -v0x1e2ad70_0 .net "out0", 0 0, L_0x1e57b60; 1 drivers -v0x1e2ae10_0 .net "out1", 0 0, L_0x1e57c50; 1 drivers -v0x1e2aeb0_0 .net "out2", 0 0, L_0x1e57d40; 1 drivers -v0x1e2afc0_0 .net "out3", 0 0, L_0x1e57e30; 1 drivers -S_0x1e29d20 .scope module, "OneMux" "FourInMux" 3 293, 3 24, S_0x1e29640; - .timescale -9 -12; -L_0x1e587d0/d .functor NOT 1, L_0x1e59030, C4<0>, C4<0>, C4<0>; -L_0x1e587d0 .delay (10000,10000,10000) L_0x1e587d0/d; -L_0x1e588c0/d .functor NOT 1, L_0x1e59160, C4<0>, C4<0>, C4<0>; -L_0x1e588c0 .delay (10000,10000,10000) L_0x1e588c0/d; -L_0x1e58960/d .functor NAND 1, L_0x1e587d0, L_0x1e588c0, L_0x1e592f0, C4<1>; -L_0x1e58960 .delay (10000,10000,10000) L_0x1e58960/d; -L_0x1e58aa0/d .functor NAND 1, L_0x1e59030, L_0x1e588c0, L_0x1e594a0, C4<1>; -L_0x1e58aa0 .delay (10000,10000,10000) L_0x1e58aa0/d; -L_0x1e58b90/d .functor NAND 1, L_0x1e587d0, L_0x1e59160, L_0x1e59540, C4<1>; -L_0x1e58b90 .delay (10000,10000,10000) L_0x1e58b90/d; -L_0x1e58c80/d .functor NAND 1, L_0x1e59030, L_0x1e59160, L_0x1e595e0, C4<1>; -L_0x1e58c80 .delay (10000,10000,10000) L_0x1e58c80/d; -L_0x1e58d60/d .functor NAND 1, L_0x1e58960, L_0x1e58aa0, L_0x1e58b90, L_0x1e58c80; -L_0x1e58d60 .delay (10000,10000,10000) L_0x1e58d60/d; -v0x1e29e10_0 .net "S0", 0 0, L_0x1e59030; 1 drivers -v0x1e29ed0_0 .net "S1", 0 0, L_0x1e59160; 1 drivers -v0x1e29f70_0 .net "in0", 0 0, L_0x1e592f0; 1 drivers -v0x1e2a010_0 .net "in1", 0 0, L_0x1e594a0; 1 drivers -v0x1e2a090_0 .net "in2", 0 0, L_0x1e59540; 1 drivers -v0x1e2a130_0 .net "in3", 0 0, L_0x1e595e0; 1 drivers -v0x1e2a210_0 .net "nS0", 0 0, L_0x1e587d0; 1 drivers -v0x1e2a2b0_0 .net "nS1", 0 0, L_0x1e588c0; 1 drivers -v0x1e2a350_0 .net "out", 0 0, L_0x1e58d60; 1 drivers -v0x1e2a3f0_0 .net "out0", 0 0, L_0x1e58960; 1 drivers -v0x1e2a490_0 .net "out1", 0 0, L_0x1e58aa0; 1 drivers -v0x1e2a530_0 .net "out2", 0 0, L_0x1e58b90; 1 drivers -v0x1e2a640_0 .net "out3", 0 0, L_0x1e58c80; 1 drivers -S_0x1e297b0 .scope module, "TwoMux" "TwoInMux" 3 294, 3 8, S_0x1e29640; - .timescale -9 -12; -L_0x1e59290/d .functor NOT 1, L_0x1e59b30, C4<0>, C4<0>, C4<0>; -L_0x1e59290 .delay (10000,10000,10000) L_0x1e59290/d; -L_0x1e59720/d .functor AND 1, L_0x1e59bd0, L_0x1e59290, C4<1>, C4<1>; -L_0x1e59720 .delay (20000,20000,20000) L_0x1e59720/d; -L_0x1e59810/d .functor AND 1, L_0x1e59d10, L_0x1e59b30, C4<1>, C4<1>; -L_0x1e59810 .delay (20000,20000,20000) L_0x1e59810/d; -L_0x1e59900/d .functor OR 1, L_0x1e59720, L_0x1e59810, C4<0>, C4<0>; -L_0x1e59900 .delay (20000,20000,20000) L_0x1e59900/d; -v0x1e298a0_0 .net "S", 0 0, L_0x1e59b30; 1 drivers -v0x1e29940_0 .net "in0", 0 0, L_0x1e59bd0; 1 drivers -v0x1e299e0_0 .net "in1", 0 0, L_0x1e59d10; 1 drivers -v0x1e29a80_0 .net "nS", 0 0, L_0x1e59290; 1 drivers -v0x1e29b00_0 .net "out0", 0 0, L_0x1e59720; 1 drivers -v0x1e29ba0_0 .net "out1", 0 0, L_0x1e59810; 1 drivers -v0x1e29c80_0 .net "outfinal", 0 0, L_0x1e59900; 1 drivers -S_0x1e27ac0 .scope generate, "muxbits[2]" "muxbits[2]" 3 290, 3 290, S_0x1da9070; - .timescale -9 -12; -P_0x1e26a08 .param/l "i" 3 290, +C4<010>; -L_0x1e5c2e0/d .functor OR 1, L_0x1e5ca60, L_0x1e5cde0, C4<0>, C4<0>; -L_0x1e5c2e0 .delay (20000,20000,20000) L_0x1e5c2e0/d; -v0x1e294e0_0 .net *"_s15", 0 0, L_0x1e5ca60; 1 drivers -v0x1e295a0_0 .net *"_s16", 0 0, L_0x1e5cde0; 1 drivers -S_0x1e28b60 .scope module, "ZeroMux" "FourInMux" 3 292, 3 24, S_0x1e27ac0; - .timescale -9 -12; -L_0x1e5a230/d .functor NOT 1, L_0x1e5a130, C4<0>, C4<0>, C4<0>; -L_0x1e5a230 .delay (10000,10000,10000) L_0x1e5a230/d; -L_0x1e5a320/d .functor NOT 1, L_0x1e5ab90, C4<0>, C4<0>, C4<0>; -L_0x1e5a320 .delay (10000,10000,10000) L_0x1e5a320/d; -L_0x1e5a3c0/d .functor NAND 1, L_0x1e5a230, L_0x1e5a320, L_0x1e5aa40, C4<1>; -L_0x1e5a3c0 .delay (10000,10000,10000) L_0x1e5a3c0/d; -L_0x1e5a500/d .functor NAND 1, L_0x1e5a130, L_0x1e5a320, L_0x1e5ad90, C4<1>; -L_0x1e5a500 .delay (10000,10000,10000) L_0x1e5a500/d; -L_0x1e5a5f0/d .functor NAND 1, L_0x1e5a230, L_0x1e5ab90, L_0x1e5acc0, C4<1>; -L_0x1e5a5f0 .delay (10000,10000,10000) L_0x1e5a5f0/d; -L_0x1e5a6e0/d .functor NAND 1, L_0x1e5a130, L_0x1e5ab90, L_0x1e5af60, C4<1>; -L_0x1e5a6e0 .delay (10000,10000,10000) L_0x1e5a6e0/d; -L_0x1e5a7c0/d .functor NAND 1, L_0x1e5a3c0, L_0x1e5a500, L_0x1e5a5f0, L_0x1e5a6e0; -L_0x1e5a7c0 .delay (10000,10000,10000) L_0x1e5a7c0/d; -v0x1e28c50_0 .net "S0", 0 0, L_0x1e5a130; 1 drivers -v0x1e28d10_0 .net "S1", 0 0, L_0x1e5ab90; 1 drivers -v0x1e28db0_0 .net "in0", 0 0, L_0x1e5aa40; 1 drivers -v0x1e28e50_0 .net "in1", 0 0, L_0x1e5ad90; 1 drivers -v0x1e28ed0_0 .net "in2", 0 0, L_0x1e5acc0; 1 drivers -v0x1e28f70_0 .net "in3", 0 0, L_0x1e5af60; 1 drivers -v0x1e29010_0 .net "nS0", 0 0, L_0x1e5a230; 1 drivers -v0x1e290b0_0 .net "nS1", 0 0, L_0x1e5a320; 1 drivers -v0x1e29150_0 .net "out", 0 0, L_0x1e5a7c0; 1 drivers -v0x1e291f0_0 .net "out0", 0 0, L_0x1e5a3c0; 1 drivers -v0x1e29290_0 .net "out1", 0 0, L_0x1e5a500; 1 drivers -v0x1e29330_0 .net "out2", 0 0, L_0x1e5a5f0; 1 drivers -v0x1e29440_0 .net "out3", 0 0, L_0x1e5a6e0; 1 drivers -S_0x1e281a0 .scope module, "OneMux" "FourInMux" 3 293, 3 24, S_0x1e27ac0; - .timescale -9 -12; -L_0x1e5ae30/d .functor NOT 1, L_0x1e5b900, C4<0>, C4<0>, C4<0>; -L_0x1e5ae30 .delay (10000,10000,10000) L_0x1e5ae30/d; -L_0x1e5b190/d .functor NOT 1, L_0x1e5b050, C4<0>, C4<0>, C4<0>; -L_0x1e5b190 .delay (10000,10000,10000) L_0x1e5b190/d; -L_0x1e5b1f0/d .functor NAND 1, L_0x1e5ae30, L_0x1e5b190, L_0x1e49f50, C4<1>; -L_0x1e5b1f0 .delay (10000,10000,10000) L_0x1e5b1f0/d; -L_0x1e5b330/d .functor NAND 1, L_0x1e5b900, L_0x1e5b190, L_0x1e4a100, C4<1>; -L_0x1e5b330 .delay (10000,10000,10000) L_0x1e5b330/d; -L_0x1e5b420/d .functor NAND 1, L_0x1e5ae30, L_0x1e5b050, L_0x1e49dc0, C4<1>; -L_0x1e5b420 .delay (10000,10000,10000) L_0x1e5b420/d; -L_0x1e5b510/d .functor NAND 1, L_0x1e5b900, L_0x1e5b050, L_0x1e49ff0, C4<1>; -L_0x1e5b510 .delay (10000,10000,10000) L_0x1e5b510/d; -L_0x1e5b650/d .functor NAND 1, L_0x1e5b1f0, L_0x1e5b330, L_0x1e5b420, L_0x1e5b510; -L_0x1e5b650 .delay (10000,10000,10000) L_0x1e5b650/d; -v0x1e28290_0 .net "S0", 0 0, L_0x1e5b900; 1 drivers -v0x1e28350_0 .net "S1", 0 0, L_0x1e5b050; 1 drivers -v0x1e283f0_0 .net "in0", 0 0, L_0x1e49f50; 1 drivers -v0x1e28490_0 .net "in1", 0 0, L_0x1e4a100; 1 drivers -v0x1e28510_0 .net "in2", 0 0, L_0x1e49dc0; 1 drivers -v0x1e285b0_0 .net "in3", 0 0, L_0x1e49ff0; 1 drivers -v0x1e28690_0 .net "nS0", 0 0, L_0x1e5ae30; 1 drivers -v0x1e28730_0 .net "nS1", 0 0, L_0x1e5b190; 1 drivers -v0x1e287d0_0 .net "out", 0 0, L_0x1e5b650; 1 drivers -v0x1e28870_0 .net "out0", 0 0, L_0x1e5b1f0; 1 drivers -v0x1e28910_0 .net "out1", 0 0, L_0x1e5b330; 1 drivers -v0x1e289b0_0 .net "out2", 0 0, L_0x1e5b420; 1 drivers -v0x1e28ac0_0 .net "out3", 0 0, L_0x1e5b510; 1 drivers -S_0x1e27c30 .scope module, "TwoMux" "TwoInMux" 3 294, 3 8, S_0x1e27ac0; - .timescale -9 -12; -L_0x1e4a090/d .functor NOT 1, L_0x1e5c240, C4<0>, C4<0>, C4<0>; -L_0x1e4a090 .delay (10000,10000,10000) L_0x1e4a090/d; -L_0x1e5c3b0/d .functor AND 1, L_0x1e5c8f0, L_0x1e4a090, C4<1>, C4<1>; -L_0x1e5c3b0 .delay (20000,20000,20000) L_0x1e5c3b0/d; -L_0x1e5c460/d .functor AND 1, L_0x1e5c7c0, L_0x1e5c240, C4<1>, C4<1>; -L_0x1e5c460 .delay (20000,20000,20000) L_0x1e5c460/d; -L_0x1e5c550/d .functor OR 1, L_0x1e5c3b0, L_0x1e5c460, C4<0>, C4<0>; -L_0x1e5c550 .delay (20000,20000,20000) L_0x1e5c550/d; -v0x1e27d20_0 .net "S", 0 0, L_0x1e5c240; 1 drivers -v0x1e27dc0_0 .net "in0", 0 0, L_0x1e5c8f0; 1 drivers -v0x1e27e60_0 .net "in1", 0 0, L_0x1e5c7c0; 1 drivers -v0x1e27f00_0 .net "nS", 0 0, L_0x1e4a090; 1 drivers -v0x1e27f80_0 .net "out0", 0 0, L_0x1e5c3b0; 1 drivers -v0x1e28020_0 .net "out1", 0 0, L_0x1e5c460; 1 drivers -v0x1e28100_0 .net "outfinal", 0 0, L_0x1e5c550; 1 drivers -S_0x1da89f0 .scope generate, "muxbits[3]" "muxbits[3]" 3 290, 3 290, S_0x1da9070; - .timescale -9 -12; -P_0x1d9fce8 .param/l "i" 3 290, +C4<011>; -L_0x1e5f4a0/d .functor OR 1, L_0x1e5f820, L_0x1e5f630, C4<0>, C4<0>; -L_0x1e5f4a0 .delay (20000,20000,20000) L_0x1e5f4a0/d; -v0x1e27960_0 .net *"_s15", 0 0, L_0x1e5f820; 1 drivers -v0x1e27a20_0 .net *"_s16", 0 0, L_0x1e5f630; 1 drivers -S_0x1e26fe0 .scope module, "ZeroMux" "FourInMux" 3 292, 3 24, S_0x1da89f0; - .timescale -9 -12; -L_0x1e5cc90/d .functor NOT 1, L_0x1e5d790, C4<0>, C4<0>, C4<0>; -L_0x1e5cc90 .delay (10000,10000,10000) L_0x1e5cc90/d; -L_0x1e5cd80/d .functor NOT 1, L_0x1e5ce80, C4<0>, C4<0>, C4<0>; -L_0x1e5cd80 .delay (10000,10000,10000) L_0x1e5cd80/d; -L_0x1e5d020/d .functor NAND 1, L_0x1e5cc90, L_0x1e5cd80, L_0x1e5da30, C4<1>; -L_0x1e5d020 .delay (10000,10000,10000) L_0x1e5d020/d; -L_0x1e5d160/d .functor NAND 1, L_0x1e5d790, L_0x1e5cd80, L_0x1e4f9f0, C4<1>; -L_0x1e5d160 .delay (10000,10000,10000) L_0x1e5d160/d; -L_0x1e5d250/d .functor NAND 1, L_0x1e5cc90, L_0x1e5ce80, L_0x1e5d8c0, C4<1>; -L_0x1e5d250 .delay (10000,10000,10000) L_0x1e5d250/d; -L_0x1e5d370/d .functor NAND 1, L_0x1e5d790, L_0x1e5ce80, L_0x1e5de70, C4<1>; -L_0x1e5d370 .delay (10000,10000,10000) L_0x1e5d370/d; -L_0x1e5d4e0/d .functor NAND 1, L_0x1e5d020, L_0x1e5d160, L_0x1e5d250, L_0x1e5d370; -L_0x1e5d4e0 .delay (10000,10000,10000) L_0x1e5d4e0/d; -v0x1e270d0_0 .net "S0", 0 0, L_0x1e5d790; 1 drivers -v0x1e27190_0 .net "S1", 0 0, L_0x1e5ce80; 1 drivers -v0x1e27230_0 .net "in0", 0 0, L_0x1e5da30; 1 drivers -v0x1e272d0_0 .net "in1", 0 0, L_0x1e4f9f0; 1 drivers -v0x1e27350_0 .net "in2", 0 0, L_0x1e5d8c0; 1 drivers -v0x1e273f0_0 .net "in3", 0 0, L_0x1e5de70; 1 drivers -v0x1e27490_0 .net "nS0", 0 0, L_0x1e5cc90; 1 drivers -v0x1e27530_0 .net "nS1", 0 0, L_0x1e5cd80; 1 drivers -v0x1e275d0_0 .net "out", 0 0, L_0x1e5d4e0; 1 drivers -v0x1e27670_0 .net "out0", 0 0, L_0x1e5d020; 1 drivers -v0x1e27710_0 .net "out1", 0 0, L_0x1e5d160; 1 drivers -v0x1e277b0_0 .net "out2", 0 0, L_0x1e5d250; 1 drivers -v0x1e278c0_0 .net "out3", 0 0, L_0x1e5d370; 1 drivers -S_0x1e26570 .scope module, "OneMux" "FourInMux" 3 293, 3 24, S_0x1da89f0; - .timescale -9 -12; -L_0x1e5d9b0/d .functor NOT 1, L_0x1e5dce0, C4<0>, C4<0>, C4<0>; -L_0x1e5d9b0 .delay (10000,10000,10000) L_0x1e5d9b0/d; -L_0x1e5dfa0/d .functor NOT 1, L_0x1e5e920, C4<0>, C4<0>, C4<0>; -L_0x1e5dfa0 .delay (10000,10000,10000) L_0x1e5dfa0/d; -L_0x1e5e040/d .functor NAND 1, L_0x1e5d9b0, L_0x1e5dfa0, L_0x1e5e780, C4<1>; -L_0x1e5e040 .delay (10000,10000,10000) L_0x1e5e040/d; -L_0x1e5e180/d .functor NAND 1, L_0x1e5dce0, L_0x1e5dfa0, L_0x1e5e820, C4<1>; -L_0x1e5e180 .delay (10000,10000,10000) L_0x1e5e180/d; -L_0x1e5e270/d .functor NAND 1, L_0x1e5d9b0, L_0x1e5e920, L_0x1e5ec10, C4<1>; -L_0x1e5e270 .delay (10000,10000,10000) L_0x1e5e270/d; -L_0x1e5e360/d .functor NAND 1, L_0x1e5dce0, L_0x1e5e920, L_0x1e5ecb0, C4<1>; -L_0x1e5e360 .delay (10000,10000,10000) L_0x1e5e360/d; -L_0x1e5e4d0/d .functor NAND 1, L_0x1e5e040, L_0x1e5e180, L_0x1e5e270, L_0x1e5e360; -L_0x1e5e4d0 .delay (10000,10000,10000) L_0x1e5e4d0/d; -v0x1e26660_0 .net "S0", 0 0, L_0x1e5dce0; 1 drivers -v0x1e26720_0 .net "S1", 0 0, L_0x1e5e920; 1 drivers -v0x1e267c0_0 .net "in0", 0 0, L_0x1e5e780; 1 drivers -v0x1e26860_0 .net "in1", 0 0, L_0x1e5e820; 1 drivers -v0x1e268e0_0 .net "in2", 0 0, L_0x1e5ec10; 1 drivers -v0x1e26980_0 .net "in3", 0 0, L_0x1e5ecb0; 1 drivers -v0x1e26a60_0 .net "nS0", 0 0, L_0x1e5d9b0; 1 drivers -v0x1e26b00_0 .net "nS1", 0 0, L_0x1e5dfa0; 1 drivers -v0x1e26bf0_0 .net "out", 0 0, L_0x1e5e4d0; 1 drivers -v0x1e26c90_0 .net "out0", 0 0, L_0x1e5e040; 1 drivers -v0x1e26d90_0 .net "out1", 0 0, L_0x1e5e180; 1 drivers -v0x1e26e30_0 .net "out2", 0 0, L_0x1e5e270; 1 drivers -v0x1e26f40_0 .net "out3", 0 0, L_0x1e5e360; 1 drivers -S_0x1da5cd0 .scope module, "TwoMux" "TwoInMux" 3 294, 3 8, S_0x1da89f0; - .timescale -9 -12; -L_0x1e58620/d .functor NOT 1, L_0x1e5f360, C4<0>, C4<0>, C4<0>; -L_0x1e58620 .delay (10000,10000,10000) L_0x1e58620/d; -L_0x1e5ea50/d .functor AND 1, L_0x1e5ef60, L_0x1e58620, C4<1>, C4<1>; -L_0x1e5ea50 .delay (20000,20000,20000) L_0x1e5ea50/d; -L_0x1e5eb40/d .functor AND 1, L_0x1e5f050, L_0x1e5f360, C4<1>, C4<1>; -L_0x1e5eb40 .delay (20000,20000,20000) L_0x1e5eb40/d; -L_0x1e5f180/d .functor OR 1, L_0x1e5ea50, L_0x1e5eb40, C4<0>, C4<0>; -L_0x1e5f180 .delay (20000,20000,20000) L_0x1e5f180/d; -v0x1d73ba0_0 .net "S", 0 0, L_0x1e5f360; 1 drivers -v0x1e26160_0 .net "in0", 0 0, L_0x1e5ef60; 1 drivers -v0x1e26200_0 .net "in1", 0 0, L_0x1e5f050; 1 drivers -v0x1e262a0_0 .net "nS", 0 0, L_0x1e58620; 1 drivers -v0x1e26350_0 .net "out0", 0 0, L_0x1e5ea50; 1 drivers -v0x1e263f0_0 .net "out1", 0 0, L_0x1e5eb40; 1 drivers -v0x1e264d0_0 .net "outfinal", 0 0, L_0x1e5f180; 1 drivers - .scope S_0x1da9580; +S_0x18c7e50 .scope module, "test32Adder" "test32Adder" 2 122; + .timescale -9 -12; +P_0x181c268 .param/l "size" 2 123, +C4<0100>; +v0x1929e30_0 .var "A", 3 0; +RS_0x7f644c9d4be8/0/0 .resolv tri, L_0x192b620, L_0x192cd10, L_0x192e250, L_0x192f850; +RS_0x7f644c9d4be8/0/4 .resolv tri, L_0x19417d0, L_0x1942bf0, L_0x1943ff0, L_0x19455d0; +RS_0x7f644c9d4be8 .resolv tri, RS_0x7f644c9d4be8/0/0, RS_0x7f644c9d4be8/0/4, C4, C4; +v0x1929eb0_0 .net8 "AddSubSLTSum", 3 0, RS_0x7f644c9d4be8; 8 drivers +v0x1929f30_0 .net "AllZeros", 0 0, L_0x1950e20; 1 drivers +RS_0x7f644c9d3e38/0/0 .resolv tri, L_0x1931800, L_0x19322b0, L_0x1932d20, L_0x1933780; +RS_0x7f644c9d3e38/0/4 .resolv tri, L_0x1947400, L_0x1947e70, L_0x19488e0, L_0x1949440; +RS_0x7f644c9d3e38 .resolv tri, RS_0x7f644c9d3e38/0/0, RS_0x7f644c9d3e38/0/4, C4, C4; +v0x1929fb0_0 .net8 "AndNandOut", 3 0, RS_0x7f644c9d3e38; 8 drivers +v0x192a030_0 .var "B", 3 0; +v0x192a0b0_0 .var "Command", 2 0; +RS_0x7f644c9d5068 .resolv tri, L_0x193a870, L_0x193d600, L_0x1940230, L_0x1950290; +v0x192a130_0 .net8 "OneBitFinalOut", 3 0, RS_0x7f644c9d5068; 4 drivers +RS_0x7f644c9d3748/0/0 .resolv tri, L_0x1934ad0, L_0x1936030, L_0x1937250, L_0x1938360; +RS_0x7f644c9d3748/0/4 .resolv tri, L_0x194a790, L_0x194ba90, L_0x194cd90, L_0x194e080; +RS_0x7f644c9d3748 .resolv tri, RS_0x7f644c9d3748/0/0, RS_0x7f644c9d3748/0/4, C4, C4; +v0x192a1b0_0 .net8 "OrNorXorOut", 3 0, RS_0x7f644c9d3748; 8 drivers +RS_0x7f644c9d4ca8 .resolv tri, L_0x1930e80, L_0x1946aa0, C4, C4; +v0x192a230_0 .net8 "SLTflag", 0 0, RS_0x7f644c9d4ca8; 2 drivers +RS_0x7f644c9d5098 .resolv tri, L_0x193ad20, L_0x193dad0, L_0x1940370, L_0x1950550; +v0x192a2b0_0 .net8 "ZeroFlag", 3 0, RS_0x7f644c9d5098; 4 drivers +v0x192a330_0 .var "carryin", 3 0; +RS_0x7f644c9d4ee8 .resolv tri, L_0x192b900, L_0x1945950, C4, C4; +v0x192a3b0_0 .net8 "carryout", 0 0, RS_0x7f644c9d4ee8; 2 drivers +RS_0x7f644c9d4f78 .resolv tri, L_0x1930150, L_0x1945dc0, C4, C4; +v0x192a430_0 .net8 "overflow", 0 0, RS_0x7f644c9d4f78; 2 drivers +RS_0x7f644c9d4fa8/0/0 .resolv tri, L_0x192b860, L_0x192cf40, L_0x192e4b0, L_0x192e8a0; +RS_0x7f644c9d4fa8/0/4 .resolv tri, L_0x19419b0, L_0x1942e20, L_0x1944250, L_0x1944640; +RS_0x7f644c9d4fa8 .resolv tri, RS_0x7f644c9d4fa8/0/0, RS_0x7f644c9d4fa8/0/4, C4, C4; +v0x192a4b0_0 .net8 "subtract", 3 0, RS_0x7f644c9d4fa8; 8 drivers +S_0x19246c0 .scope module, "trial" "AddSubSLT32" 2 141, 3 205, S_0x18c7e50; + .timescale -9 -12; +P_0x19247b8 .param/l "size" 3 228, +C4<0100>; +L_0x192b900/d .functor OR 1, L_0x192ffa0, C4<0>, C4<0>, C4<0>; +L_0x192b900 .delay (20000,20000,20000) L_0x192b900/d; +L_0x1930150/d .functor XOR 1, RS_0x7f644c9d4ee8, L_0x1930280, C4<0>, C4<0>; +L_0x1930150 .delay (40000,40000,40000) L_0x1930150/d; +L_0x192fed0/d .functor AND 1, L_0x1930450, L_0x19304f0, C4<1>, C4<1>; +L_0x192fed0 .delay (20000,20000,20000) L_0x192fed0/d; +L_0x1930320/d .functor NOT 1, RS_0x7f644c9d4f78, C4<0>, C4<0>, C4<0>; +L_0x1930320 .delay (10000,10000,10000) L_0x1930320/d; +L_0x1930720/d .functor NOT 1, L_0x1930780, C4<0>, C4<0>, C4<0>; +L_0x1930720 .delay (10000,10000,10000) L_0x1930720/d; +L_0x192b6c0/d .functor AND 1, L_0x1930320, L_0x1930a50, C4<1>, C4<1>; +L_0x192b6c0 .delay (20000,20000,20000) L_0x192b6c0/d; +L_0x19305e0/d .functor AND 1, RS_0x7f644c9d4f78, L_0x1930720, C4<1>, C4<1>; +L_0x19305e0 .delay (20000,20000,20000) L_0x19305e0/d; +L_0x1930c40/d .functor AND 1, L_0x192b6c0, L_0x192fed0, C4<1>, C4<1>; +L_0x1930c40 .delay (20000,20000,20000) L_0x1930c40/d; +L_0x1930d80/d .functor AND 1, L_0x19305e0, L_0x192fed0, C4<1>, C4<1>; +L_0x1930d80 .delay (20000,20000,20000) L_0x1930d80/d; +L_0x1930e80/d .functor OR 1, L_0x1930c40, L_0x1930d80, C4<0>, C4<0>; +L_0x1930e80 .delay (20000,20000,20000) L_0x1930e80/d; +v0x1928d50_0 .net "A", 3 0, v0x1929e30_0; 1 drivers +v0x1928df0_0 .alias "AddSubSLTSum", 3 0, v0x1929eb0_0; +v0x1928e70_0 .net "B", 3 0, v0x192a030_0; 1 drivers +RS_0x7f644c9d7348 .resolv tri, L_0x192b770, L_0x192ce00, L_0x192e340, L_0x192f940; +v0x1928ef0_0 .net8 "CarryoutWire", 3 0, RS_0x7f644c9d7348; 4 drivers +v0x1928f70_0 .net "Command", 2 0, v0x192a0b0_0; 1 drivers +v0x1928ff0_0 .net "Res0OF1", 0 0, L_0x19305e0; 1 drivers +v0x1929090_0 .net "Res1OF0", 0 0, L_0x192b6c0; 1 drivers +v0x1929130_0 .alias "SLTflag", 0 0, v0x192a230_0; +v0x1929250_0 .net "SLTflag0", 0 0, L_0x1930c40; 1 drivers +v0x19292f0_0 .net "SLTflag1", 0 0, L_0x1930d80; 1 drivers +v0x1929390_0 .net "SLTon", 0 0, L_0x192fed0; 1 drivers +v0x1929430_0 .net *"_s40", 0 0, L_0x192ffa0; 1 drivers +v0x19294d0_0 .net/s *"_s41", 0 0, C4<0>; 1 drivers +v0x1929570_0 .net *"_s44", 0 0, L_0x1930280; 1 drivers +v0x1929690_0 .net *"_s46", 0 0, L_0x1930450; 1 drivers +v0x1929730_0 .net *"_s48", 0 0, L_0x19304f0; 1 drivers +v0x19295f0_0 .net *"_s50", 0 0, L_0x1930780; 1 drivers +v0x1929880_0 .net *"_s52", 0 0, L_0x1930a50; 1 drivers +v0x19299a0_0 .net "carryin", 3 0, v0x192a330_0; 1 drivers +v0x1929a20_0 .alias "carryout", 0 0, v0x192a3b0_0; +v0x1929900_0 .net "nAddSubSLTSum", 0 0, L_0x1930720; 1 drivers +v0x1929b50_0 .net "nOF", 0 0, L_0x1930320; 1 drivers +v0x1929aa0_0 .alias "overflow", 0 0, v0x192a430_0; +v0x1929ce0_0 .alias "subtract", 3 0, v0x192a4b0_0; +L_0x192b620 .part/pv L_0x192b190, 1, 1, 4; +L_0x192b770 .part/pv L_0x192b4e0, 1, 1, 4; +L_0x192b860 .part/pv L_0x191d6c0, 1, 1, 4; +L_0x192b990 .part v0x1929e30_0, 1, 1; +L_0x192bb40 .part v0x192a030_0, 1, 1; +L_0x192bcf0 .part RS_0x7f644c9d7348, 0, 1; +L_0x192cd10 .part/pv L_0x192c840, 2, 1, 4; +L_0x192ce00 .part/pv L_0x192cbb0, 2, 1, 4; +L_0x192cf40 .part/pv L_0x192c570, 2, 1, 4; +L_0x192d030 .part v0x1929e30_0, 2, 1; +L_0x192d130 .part v0x192a030_0, 2, 1; +L_0x192d260 .part RS_0x7f644c9d7348, 1, 1; +L_0x192e250 .part/pv L_0x192dda0, 3, 1, 4; +L_0x192e340 .part/pv L_0x192e0f0, 3, 1, 4; +L_0x192e4b0 .part/pv L_0x192dad0, 3, 1, 4; +L_0x192e5a0 .part v0x1929e30_0, 3, 1; +L_0x192e6d0 .part v0x192a030_0, 3, 1; +L_0x192e800 .part RS_0x7f644c9d7348, 2, 1; +L_0x192f850 .part/pv L_0x192f3a0, 0, 1, 4; +L_0x192f940 .part/pv L_0x192f6f0, 0, 1, 4; +L_0x192e8a0 .part/pv L_0x192f0d0, 0, 1, 4; +L_0x192fb30 .part v0x1929e30_0, 0, 1; +L_0x192fa30 .part v0x192a030_0, 0, 1; +L_0x192fd20 .part RS_0x7f644c9d4fa8, 0, 1; +L_0x192ffa0 .part RS_0x7f644c9d7348, 3, 1; +L_0x1930280 .part RS_0x7f644c9d7348, 2, 1; +L_0x1930450 .part v0x192a0b0_0, 1, 1; +L_0x19304f0 .part RS_0x7f644c9d4fa8, 0, 1; +L_0x1930780 .part RS_0x7f644c9d4be8, 3, 1; +L_0x1930a50 .part RS_0x7f644c9d4be8, 3, 1; +S_0x1927d40 .scope module, "attempt2" "MiddleAddSubSLT" 3 225, 3 89, S_0x19246c0; + .timescale -9 -12; +L_0x192e640/d .functor NOT 1, L_0x192fa30, C4<0>, C4<0>, C4<0>; +L_0x192e640 .delay (10000,10000,10000) L_0x192e640/d; +L_0x192ef70/d .functor NOT 1, L_0x192f030, C4<0>, C4<0>, C4<0>; +L_0x192ef70 .delay (10000,10000,10000) L_0x192ef70/d; +L_0x192f0d0/d .functor AND 1, L_0x192f210, L_0x192ef70, C4<1>, C4<1>; +L_0x192f0d0 .delay (20000,20000,20000) L_0x192f0d0/d; +L_0x192f2b0/d .functor XOR 1, L_0x192fb30, L_0x192ed00, C4<0>, C4<0>; +L_0x192f2b0 .delay (40000,40000,40000) L_0x192f2b0/d; +L_0x192f3a0/d .functor XOR 1, L_0x192f2b0, L_0x192fd20, C4<0>, C4<0>; +L_0x192f3a0 .delay (40000,40000,40000) L_0x192f3a0/d; +L_0x192f490/d .functor AND 1, L_0x192fb30, L_0x192ed00, C4<1>, C4<1>; +L_0x192f490 .delay (20000,20000,20000) L_0x192f490/d; +L_0x192f600/d .functor AND 1, L_0x192f2b0, L_0x192fd20, C4<1>, C4<1>; +L_0x192f600 .delay (20000,20000,20000) L_0x192f600/d; +L_0x192f6f0/d .functor OR 1, L_0x192f490, L_0x192f600, C4<0>, C4<0>; +L_0x192f6f0 .delay (20000,20000,20000) L_0x192f6f0/d; +v0x19283b0_0 .net "A", 0 0, L_0x192fb30; 1 drivers +v0x1928470_0 .net "AandB", 0 0, L_0x192f490; 1 drivers +v0x1928510_0 .net "AddSubSLTSum", 0 0, L_0x192f3a0; 1 drivers +v0x19285b0_0 .net "AxorB", 0 0, L_0x192f2b0; 1 drivers +v0x1928630_0 .net "B", 0 0, L_0x192fa30; 1 drivers +v0x19286e0_0 .net "BornB", 0 0, L_0x192ed00; 1 drivers +v0x19287a0_0 .net "CINandAxorB", 0 0, L_0x192f600; 1 drivers +v0x1928820_0 .alias "Command", 2 0, v0x1928f70_0; +v0x19288a0_0 .net *"_s3", 0 0, L_0x192f030; 1 drivers +v0x1928920_0 .net *"_s5", 0 0, L_0x192f210; 1 drivers +v0x19289c0_0 .net "carryin", 0 0, L_0x192fd20; 1 drivers +v0x1928a60_0 .net "carryout", 0 0, L_0x192f6f0; 1 drivers +v0x1928b00_0 .net "nB", 0 0, L_0x192e640; 1 drivers +v0x1928bb0_0 .net "nCmd2", 0 0, L_0x192ef70; 1 drivers +v0x1928cb0_0 .net "subtract", 0 0, L_0x192f0d0; 1 drivers +L_0x192eed0 .part v0x192a0b0_0, 0, 1; +L_0x192f030 .part v0x192a0b0_0, 2, 1; +L_0x192f210 .part v0x192a0b0_0, 0, 1; +S_0x1927e30 .scope module, "mux0" "TwoInMux" 3 105, 3 8, S_0x1927d40; + .timescale -9 -12; +L_0x192ea20/d .functor NOT 1, L_0x192eed0, C4<0>, C4<0>, C4<0>; +L_0x192ea20 .delay (10000,10000,10000) L_0x192ea20/d; +L_0x192eae0/d .functor AND 1, L_0x192fa30, L_0x192ea20, C4<1>, C4<1>; +L_0x192eae0 .delay (20000,20000,20000) L_0x192eae0/d; +L_0x192ebf0/d .functor AND 1, L_0x192e640, L_0x192eed0, C4<1>, C4<1>; +L_0x192ebf0 .delay (20000,20000,20000) L_0x192ebf0/d; +L_0x192ed00/d .functor OR 1, L_0x192eae0, L_0x192ebf0, C4<0>, C4<0>; +L_0x192ed00 .delay (20000,20000,20000) L_0x192ed00/d; +v0x1927f20_0 .net "S", 0 0, L_0x192eed0; 1 drivers +v0x1927fe0_0 .alias "in0", 0 0, v0x1928630_0; +v0x1928080_0 .alias "in1", 0 0, v0x1928b00_0; +v0x1928120_0 .net "nS", 0 0, L_0x192ea20; 1 drivers +v0x19281d0_0 .net "out0", 0 0, L_0x192eae0; 1 drivers +v0x1928270_0 .net "out1", 0 0, L_0x192ebf0; 1 drivers +v0x1928310_0 .alias "outfinal", 0 0, v0x19286e0_0; +S_0x1926ba0 .scope generate, "addbits[1]" "addbits[1]" 3 230, 3 230, S_0x19246c0; + .timescale -9 -12; +P_0x19265b8 .param/l "i" 3 230, +C4<01>; +S_0x1926d10 .scope module, "attempt" "MiddleAddSubSLT" 3 232, 3 89, S_0x1926ba0; + .timescale -9 -12; +L_0x19255f0/d .functor NOT 1, L_0x192bb40, C4<0>, C4<0>, C4<0>; +L_0x19255f0 .delay (10000,10000,10000) L_0x19255f0/d; +L_0x1929c20/d .functor NOT 1, L_0x191d620, C4<0>, C4<0>, C4<0>; +L_0x1929c20 .delay (10000,10000,10000) L_0x1929c20/d; +L_0x191d6c0/d .functor AND 1, L_0x192b000, L_0x1929c20, C4<1>, C4<1>; +L_0x191d6c0 .delay (20000,20000,20000) L_0x191d6c0/d; +L_0x192b0a0/d .functor XOR 1, L_0x192b990, L_0x192a980, C4<0>, C4<0>; +L_0x192b0a0 .delay (40000,40000,40000) L_0x192b0a0/d; +L_0x192b190/d .functor XOR 1, L_0x192b0a0, L_0x192bcf0, C4<0>, C4<0>; +L_0x192b190 .delay (40000,40000,40000) L_0x192b190/d; +L_0x192b280/d .functor AND 1, L_0x192b990, L_0x192a980, C4<1>, C4<1>; +L_0x192b280 .delay (20000,20000,20000) L_0x192b280/d; +L_0x192b3f0/d .functor AND 1, L_0x192b0a0, L_0x192bcf0, C4<1>, C4<1>; +L_0x192b3f0 .delay (20000,20000,20000) L_0x192b3f0/d; +L_0x192b4e0/d .functor OR 1, L_0x192b280, L_0x192b3f0, C4<0>, C4<0>; +L_0x192b4e0 .delay (20000,20000,20000) L_0x192b4e0/d; +v0x19273a0_0 .net "A", 0 0, L_0x192b990; 1 drivers +v0x1927460_0 .net "AandB", 0 0, L_0x192b280; 1 drivers +v0x1927500_0 .net "AddSubSLTSum", 0 0, L_0x192b190; 1 drivers +v0x19275a0_0 .net "AxorB", 0 0, L_0x192b0a0; 1 drivers +v0x1927620_0 .net "B", 0 0, L_0x192bb40; 1 drivers +v0x19276d0_0 .net "BornB", 0 0, L_0x192a980; 1 drivers +v0x1927790_0 .net "CINandAxorB", 0 0, L_0x192b3f0; 1 drivers +v0x1927810_0 .alias "Command", 2 0, v0x1928f70_0; +v0x1927890_0 .net *"_s3", 0 0, L_0x191d620; 1 drivers +v0x1927910_0 .net *"_s5", 0 0, L_0x192b000; 1 drivers +v0x19279b0_0 .net "carryin", 0 0, L_0x192bcf0; 1 drivers +v0x1927a50_0 .net "carryout", 0 0, L_0x192b4e0; 1 drivers +v0x1927af0_0 .net "nB", 0 0, L_0x19255f0; 1 drivers +v0x1927ba0_0 .net "nCmd2", 0 0, L_0x1929c20; 1 drivers +v0x1927ca0_0 .net "subtract", 0 0, L_0x191d6c0; 1 drivers +L_0x192ab50 .part v0x192a0b0_0, 0, 1; +L_0x191d620 .part v0x192a0b0_0, 2, 1; +L_0x192b000 .part v0x192a0b0_0, 0, 1; +S_0x1926e00 .scope module, "mux0" "TwoInMux" 3 105, 3 8, S_0x1926d10; + .timescale -9 -12; +L_0x192a6a0/d .functor NOT 1, L_0x192ab50, C4<0>, C4<0>, C4<0>; +L_0x192a6a0 .delay (10000,10000,10000) L_0x192a6a0/d; +L_0x192a760/d .functor AND 1, L_0x192bb40, L_0x192a6a0, C4<1>, C4<1>; +L_0x192a760 .delay (20000,20000,20000) L_0x192a760/d; +L_0x192a870/d .functor AND 1, L_0x19255f0, L_0x192ab50, C4<1>, C4<1>; +L_0x192a870 .delay (20000,20000,20000) L_0x192a870/d; +L_0x192a980/d .functor OR 1, L_0x192a760, L_0x192a870, C4<0>, C4<0>; +L_0x192a980 .delay (20000,20000,20000) L_0x192a980/d; +v0x1926ef0_0 .net "S", 0 0, L_0x192ab50; 1 drivers +v0x1926f90_0 .alias "in0", 0 0, v0x1927620_0; +v0x1927030_0 .alias "in1", 0 0, v0x1927af0_0; +v0x19270d0_0 .net "nS", 0 0, L_0x192a6a0; 1 drivers +v0x1927180_0 .net "out0", 0 0, L_0x192a760; 1 drivers +v0x1927220_0 .net "out1", 0 0, L_0x192a870; 1 drivers +v0x1927300_0 .alias "outfinal", 0 0, v0x19276d0_0; +S_0x1925a00 .scope generate, "addbits[2]" "addbits[2]" 3 230, 3 230, S_0x19246c0; + .timescale -9 -12; +P_0x19253b8 .param/l "i" 3 230, +C4<010>; +S_0x1925b70 .scope module, "attempt" "MiddleAddSubSLT" 3 232, 3 89, S_0x1925a00; + .timescale -9 -12; +L_0x1921470/d .functor NOT 1, L_0x192d130, C4<0>, C4<0>, C4<0>; +L_0x1921470 .delay (10000,10000,10000) L_0x1921470/d; +L_0x192c410/d .functor NOT 1, L_0x192c4d0, C4<0>, C4<0>, C4<0>; +L_0x192c410 .delay (10000,10000,10000) L_0x192c410/d; +L_0x192c570/d .functor AND 1, L_0x192c6b0, L_0x192c410, C4<1>, C4<1>; +L_0x192c570 .delay (20000,20000,20000) L_0x192c570/d; +L_0x192c750/d .functor XOR 1, L_0x192d030, L_0x192c1a0, C4<0>, C4<0>; +L_0x192c750 .delay (40000,40000,40000) L_0x192c750/d; +L_0x192c840/d .functor XOR 1, L_0x192c750, L_0x192d260, C4<0>, C4<0>; +L_0x192c840 .delay (40000,40000,40000) L_0x192c840/d; +L_0x192c930/d .functor AND 1, L_0x192d030, L_0x192c1a0, C4<1>, C4<1>; +L_0x192c930 .delay (20000,20000,20000) L_0x192c930/d; +L_0x192caa0/d .functor AND 1, L_0x192c750, L_0x192d260, C4<1>, C4<1>; +L_0x192caa0 .delay (20000,20000,20000) L_0x192caa0/d; +L_0x192cbb0/d .functor OR 1, L_0x192c930, L_0x192caa0, C4<0>, C4<0>; +L_0x192cbb0 .delay (20000,20000,20000) L_0x192cbb0/d; +v0x1926200_0 .net "A", 0 0, L_0x192d030; 1 drivers +v0x19262c0_0 .net "AandB", 0 0, L_0x192c930; 1 drivers +v0x1926360_0 .net "AddSubSLTSum", 0 0, L_0x192c840; 1 drivers +v0x1926400_0 .net "AxorB", 0 0, L_0x192c750; 1 drivers +v0x1926480_0 .net "B", 0 0, L_0x192d130; 1 drivers +v0x1926530_0 .net "BornB", 0 0, L_0x192c1a0; 1 drivers +v0x19265f0_0 .net "CINandAxorB", 0 0, L_0x192caa0; 1 drivers +v0x1926670_0 .alias "Command", 2 0, v0x1928f70_0; +v0x19266f0_0 .net *"_s3", 0 0, L_0x192c4d0; 1 drivers +v0x1926770_0 .net *"_s5", 0 0, L_0x192c6b0; 1 drivers +v0x1926810_0 .net "carryin", 0 0, L_0x192d260; 1 drivers +v0x19268b0_0 .net "carryout", 0 0, L_0x192cbb0; 1 drivers +v0x1926950_0 .net "nB", 0 0, L_0x1921470; 1 drivers +v0x1926a00_0 .net "nCmd2", 0 0, L_0x192c410; 1 drivers +v0x1926b00_0 .net "subtract", 0 0, L_0x192c570; 1 drivers +L_0x192c370 .part v0x192a0b0_0, 0, 1; +L_0x192c4d0 .part v0x192a0b0_0, 2, 1; +L_0x192c6b0 .part v0x192a0b0_0, 0, 1; +S_0x1925c60 .scope module, "mux0" "TwoInMux" 3 105, 3 8, S_0x1925b70; + .timescale -9 -12; +L_0x192bec0/d .functor NOT 1, L_0x192c370, C4<0>, C4<0>, C4<0>; +L_0x192bec0 .delay (10000,10000,10000) L_0x192bec0/d; +L_0x192bf80/d .functor AND 1, L_0x192d130, L_0x192bec0, C4<1>, C4<1>; +L_0x192bf80 .delay (20000,20000,20000) L_0x192bf80/d; +L_0x192c090/d .functor AND 1, L_0x1921470, L_0x192c370, C4<1>, C4<1>; +L_0x192c090 .delay (20000,20000,20000) L_0x192c090/d; +L_0x192c1a0/d .functor OR 1, L_0x192bf80, L_0x192c090, C4<0>, C4<0>; +L_0x192c1a0 .delay (20000,20000,20000) L_0x192c1a0/d; +v0x1925d50_0 .net "S", 0 0, L_0x192c370; 1 drivers +v0x1925df0_0 .alias "in0", 0 0, v0x1926480_0; +v0x1925e90_0 .alias "in1", 0 0, v0x1926950_0; +v0x1925f30_0 .net "nS", 0 0, L_0x192bec0; 1 drivers +v0x1925fe0_0 .net "out0", 0 0, L_0x192bf80; 1 drivers +v0x1926080_0 .net "out1", 0 0, L_0x192c090; 1 drivers +v0x1926160_0 .alias "outfinal", 0 0, v0x1926530_0; +S_0x1924830 .scope generate, "addbits[3]" "addbits[3]" 3 230, 3 230, S_0x19246c0; + .timescale -9 -12; +P_0x1924928 .param/l "i" 3 230, +C4<011>; +S_0x19249a0 .scope module, "attempt" "MiddleAddSubSLT" 3 232, 3 89, S_0x1924830; + .timescale -9 -12; +L_0x192d0d0/d .functor NOT 1, L_0x192e6d0, C4<0>, C4<0>, C4<0>; +L_0x192d0d0 .delay (10000,10000,10000) L_0x192d0d0/d; +L_0x192d970/d .functor NOT 1, L_0x192da30, C4<0>, C4<0>, C4<0>; +L_0x192d970 .delay (10000,10000,10000) L_0x192d970/d; +L_0x192dad0/d .functor AND 1, L_0x192dc10, L_0x192d970, C4<1>, C4<1>; +L_0x192dad0 .delay (20000,20000,20000) L_0x192dad0/d; +L_0x192dcb0/d .functor XOR 1, L_0x192e5a0, L_0x192d700, C4<0>, C4<0>; +L_0x192dcb0 .delay (40000,40000,40000) L_0x192dcb0/d; +L_0x192dda0/d .functor XOR 1, L_0x192dcb0, L_0x192e800, C4<0>, C4<0>; +L_0x192dda0 .delay (40000,40000,40000) L_0x192dda0/d; +L_0x192de90/d .functor AND 1, L_0x192e5a0, L_0x192d700, C4<1>, C4<1>; +L_0x192de90 .delay (20000,20000,20000) L_0x192de90/d; +L_0x192e000/d .functor AND 1, L_0x192dcb0, L_0x192e800, C4<1>, C4<1>; +L_0x192e000 .delay (20000,20000,20000) L_0x192e000/d; +L_0x192e0f0/d .functor OR 1, L_0x192de90, L_0x192e000, C4<0>, C4<0>; +L_0x192e0f0 .delay (20000,20000,20000) L_0x192e0f0/d; +v0x1925000_0 .net "A", 0 0, L_0x192e5a0; 1 drivers +v0x19250c0_0 .net "AandB", 0 0, L_0x192de90; 1 drivers +v0x1925160_0 .net "AddSubSLTSum", 0 0, L_0x192dda0; 1 drivers +v0x1925200_0 .net "AxorB", 0 0, L_0x192dcb0; 1 drivers +v0x1925280_0 .net "B", 0 0, L_0x192e6d0; 1 drivers +v0x1925330_0 .net "BornB", 0 0, L_0x192d700; 1 drivers +v0x19253f0_0 .net "CINandAxorB", 0 0, L_0x192e000; 1 drivers +v0x1925470_0 .alias "Command", 2 0, v0x1928f70_0; +v0x19254f0_0 .net *"_s3", 0 0, L_0x192da30; 1 drivers +v0x1925570_0 .net *"_s5", 0 0, L_0x192dc10; 1 drivers +v0x1925670_0 .net "carryin", 0 0, L_0x192e800; 1 drivers +v0x1925710_0 .net "carryout", 0 0, L_0x192e0f0; 1 drivers +v0x19257b0_0 .net "nB", 0 0, L_0x192d0d0; 1 drivers +v0x1925860_0 .net "nCmd2", 0 0, L_0x192d970; 1 drivers +v0x1925960_0 .net "subtract", 0 0, L_0x192dad0; 1 drivers +L_0x192d8d0 .part v0x192a0b0_0, 0, 1; +L_0x192da30 .part v0x192a0b0_0, 2, 1; +L_0x192dc10 .part v0x192a0b0_0, 0, 1; +S_0x1924a90 .scope module, "mux0" "TwoInMux" 3 105, 3 8, S_0x19249a0; + .timescale -9 -12; +L_0x192d460/d .functor NOT 1, L_0x192d8d0, C4<0>, C4<0>, C4<0>; +L_0x192d460 .delay (10000,10000,10000) L_0x192d460/d; +L_0x192d4e0/d .functor AND 1, L_0x192e6d0, L_0x192d460, C4<1>, C4<1>; +L_0x192d4e0 .delay (20000,20000,20000) L_0x192d4e0/d; +L_0x192d5f0/d .functor AND 1, L_0x192d0d0, L_0x192d8d0, C4<1>, C4<1>; +L_0x192d5f0 .delay (20000,20000,20000) L_0x192d5f0/d; +L_0x192d700/d .functor OR 1, L_0x192d4e0, L_0x192d5f0, C4<0>, C4<0>; +L_0x192d700 .delay (20000,20000,20000) L_0x192d700/d; +v0x1924b80_0 .net "S", 0 0, L_0x192d8d0; 1 drivers +v0x1924c20_0 .alias "in0", 0 0, v0x1925280_0; +v0x1924cc0_0 .alias "in1", 0 0, v0x19257b0_0; +v0x1924d60_0 .net "nS", 0 0, L_0x192d460; 1 drivers +v0x1924de0_0 .net "out0", 0 0, L_0x192d4e0; 1 drivers +v0x1924e80_0 .net "out1", 0 0, L_0x192d5f0; 1 drivers +v0x1924f60_0 .alias "outfinal", 0 0, v0x1925330_0; +S_0x1921600 .scope module, "trial1" "AndNand32" 2 143, 3 154, S_0x18c7e50; + .timescale -9 -12; +P_0x1920ff8 .param/l "size" 3 161, +C4<0100>; +v0x19244c0_0 .alias "A", 3 0, v0x1928d50_0; +v0x1924540_0 .alias "AndNandOut", 3 0, v0x1929fb0_0; +v0x19245c0_0 .alias "B", 3 0, v0x1928e70_0; +v0x1924640_0 .alias "Command", 2 0, v0x1928f70_0; +L_0x1931800 .part/pv L_0x1931590, 1, 1, 4; +L_0x1931950 .part v0x1929e30_0, 1, 1; +L_0x19319f0 .part v0x192a030_0, 1, 1; +L_0x19322b0 .part/pv L_0x1932040, 2, 1, 4; +L_0x1932350 .part v0x1929e30_0, 2, 1; +L_0x19323f0 .part v0x192a030_0, 2, 1; +L_0x1932d20 .part/pv L_0x1932ab0, 3, 1, 4; +L_0x1932dc0 .part v0x1929e30_0, 3, 1; +L_0x1932eb0 .part v0x192a030_0, 3, 1; +L_0x1933780 .part/pv L_0x1933510, 0, 1, 4; +L_0x1933880 .part v0x1929e30_0, 0, 1; +L_0x1933920 .part v0x192a030_0, 0, 1; +S_0x1923a90 .scope module, "attempt2" "AndNand" 3 165, 3 48, S_0x1921600; + .timescale -9 -12; +L_0x1932fa0/d .functor NAND 1, L_0x1933880, L_0x1933920, C4<1>, C4<1>; +L_0x1932fa0 .delay (10000,10000,10000) L_0x1932fa0/d; +L_0x19330c0/d .functor NOT 1, L_0x1932fa0, C4<0>, C4<0>, C4<0>; +L_0x19330c0 .delay (10000,10000,10000) L_0x19330c0/d; +v0x19240b0_0 .net "A", 0 0, L_0x1933880; 1 drivers +v0x1924170_0 .net "AandB", 0 0, L_0x19330c0; 1 drivers +v0x19241f0_0 .net "AnandB", 0 0, L_0x1932fa0; 1 drivers +v0x19242a0_0 .net "AndNandOut", 0 0, L_0x1933510; 1 drivers +v0x1924380_0 .net "B", 0 0, L_0x1933920; 1 drivers +v0x1924400_0 .alias "Command", 2 0, v0x1928f70_0; +L_0x19336e0 .part v0x192a0b0_0, 0, 1; +S_0x1923b80 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0x1923a90; + .timescale -9 -12; +L_0x19331f0/d .functor NOT 1, L_0x19336e0, C4<0>, C4<0>, C4<0>; +L_0x19331f0 .delay (10000,10000,10000) L_0x19331f0/d; +L_0x19332b0/d .functor AND 1, L_0x19330c0, L_0x19331f0, C4<1>, C4<1>; +L_0x19332b0 .delay (20000,20000,20000) L_0x19332b0/d; +L_0x19333c0/d .functor AND 1, L_0x1932fa0, L_0x19336e0, C4<1>, C4<1>; +L_0x19333c0 .delay (20000,20000,20000) L_0x19333c0/d; +L_0x1933510/d .functor OR 1, L_0x19332b0, L_0x19333c0, C4<0>, C4<0>; +L_0x1933510 .delay (20000,20000,20000) L_0x1933510/d; +v0x1923c70_0 .net "S", 0 0, L_0x19336e0; 1 drivers +v0x1923cf0_0 .alias "in0", 0 0, v0x1924170_0; +v0x1923d70_0 .alias "in1", 0 0, v0x19241f0_0; +v0x1923e10_0 .net "nS", 0 0, L_0x19331f0; 1 drivers +v0x1923e90_0 .net "out0", 0 0, L_0x19332b0; 1 drivers +v0x1923f30_0 .net "out1", 0 0, L_0x19333c0; 1 drivers +v0x1924010_0 .alias "outfinal", 0 0, v0x19242a0_0; +S_0x1922ed0 .scope generate, "andbits[1]" "andbits[1]" 3 169, 3 169, S_0x1921600; + .timescale -9 -12; +P_0x1922fc8 .param/l "i" 3 169, +C4<01>; +S_0x1923040 .scope module, "attempt" "AndNand" 3 171, 3 48, S_0x1922ed0; + .timescale -9 -12; +L_0x1931080/d .functor NAND 1, L_0x1931950, L_0x19319f0, C4<1>, C4<1>; +L_0x1931080 .delay (10000,10000,10000) L_0x1931080/d; +L_0x1931140/d .functor NOT 1, L_0x1931080, C4<0>, C4<0>, C4<0>; +L_0x1931140 .delay (10000,10000,10000) L_0x1931140/d; +v0x1923680_0 .net "A", 0 0, L_0x1931950; 1 drivers +v0x1923740_0 .net "AandB", 0 0, L_0x1931140; 1 drivers +v0x19237c0_0 .net "AnandB", 0 0, L_0x1931080; 1 drivers +v0x1923870_0 .net "AndNandOut", 0 0, L_0x1931590; 1 drivers +v0x1923950_0 .net "B", 0 0, L_0x19319f0; 1 drivers +v0x19239d0_0 .alias "Command", 2 0, v0x1928f70_0; +L_0x1931760 .part v0x192a0b0_0, 0, 1; +S_0x1923130 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0x1923040; + .timescale -9 -12; +L_0x1931270/d .functor NOT 1, L_0x1931760, C4<0>, C4<0>, C4<0>; +L_0x1931270 .delay (10000,10000,10000) L_0x1931270/d; +L_0x1931330/d .functor AND 1, L_0x1931140, L_0x1931270, C4<1>, C4<1>; +L_0x1931330 .delay (20000,20000,20000) L_0x1931330/d; +L_0x1931440/d .functor AND 1, L_0x1931080, L_0x1931760, C4<1>, C4<1>; +L_0x1931440 .delay (20000,20000,20000) L_0x1931440/d; +L_0x1931590/d .functor OR 1, L_0x1931330, L_0x1931440, C4<0>, C4<0>; +L_0x1931590 .delay (20000,20000,20000) L_0x1931590/d; +v0x1923220_0 .net "S", 0 0, L_0x1931760; 1 drivers +v0x19232a0_0 .alias "in0", 0 0, v0x1923740_0; +v0x1923340_0 .alias "in1", 0 0, v0x19237c0_0; +v0x19233e0_0 .net "nS", 0 0, L_0x1931270; 1 drivers +v0x1923460_0 .net "out0", 0 0, L_0x1931330; 1 drivers +v0x1923500_0 .net "out1", 0 0, L_0x1931440; 1 drivers +v0x19235e0_0 .alias "outfinal", 0 0, v0x1923870_0; +S_0x1922310 .scope generate, "andbits[2]" "andbits[2]" 3 169, 3 169, S_0x1921600; + .timescale -9 -12; +P_0x1922408 .param/l "i" 3 169, +C4<010>; +S_0x1922480 .scope module, "attempt" "AndNand" 3 171, 3 48, S_0x1922310; + .timescale -9 -12; +L_0x1931a90/d .functor NAND 1, L_0x1932350, L_0x19323f0, C4<1>, C4<1>; +L_0x1931a90 .delay (10000,10000,10000) L_0x1931a90/d; +L_0x1931bf0/d .functor NOT 1, L_0x1931a90, C4<0>, C4<0>, C4<0>; +L_0x1931bf0 .delay (10000,10000,10000) L_0x1931bf0/d; +v0x1922ac0_0 .net "A", 0 0, L_0x1932350; 1 drivers +v0x1922b80_0 .net "AandB", 0 0, L_0x1931bf0; 1 drivers +v0x1922c00_0 .net "AnandB", 0 0, L_0x1931a90; 1 drivers +v0x1922cb0_0 .net "AndNandOut", 0 0, L_0x1932040; 1 drivers +v0x1922d90_0 .net "B", 0 0, L_0x19323f0; 1 drivers +v0x1922e10_0 .alias "Command", 2 0, v0x1928f70_0; +L_0x1932210 .part v0x192a0b0_0, 0, 1; +S_0x1922570 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0x1922480; + .timescale -9 -12; +L_0x1931d20/d .functor NOT 1, L_0x1932210, C4<0>, C4<0>, C4<0>; +L_0x1931d20 .delay (10000,10000,10000) L_0x1931d20/d; +L_0x1931de0/d .functor AND 1, L_0x1931bf0, L_0x1931d20, C4<1>, C4<1>; +L_0x1931de0 .delay (20000,20000,20000) L_0x1931de0/d; +L_0x1931ef0/d .functor AND 1, L_0x1931a90, L_0x1932210, C4<1>, C4<1>; +L_0x1931ef0 .delay (20000,20000,20000) L_0x1931ef0/d; +L_0x1932040/d .functor OR 1, L_0x1931de0, L_0x1931ef0, C4<0>, C4<0>; +L_0x1932040 .delay (20000,20000,20000) L_0x1932040/d; +v0x1922660_0 .net "S", 0 0, L_0x1932210; 1 drivers +v0x19226e0_0 .alias "in0", 0 0, v0x1922b80_0; +v0x1922780_0 .alias "in1", 0 0, v0x1922c00_0; +v0x1922820_0 .net "nS", 0 0, L_0x1931d20; 1 drivers +v0x19228a0_0 .net "out0", 0 0, L_0x1931de0; 1 drivers +v0x1922940_0 .net "out1", 0 0, L_0x1931ef0; 1 drivers +v0x1922a20_0 .alias "outfinal", 0 0, v0x1922cb0_0; +S_0x1921730 .scope generate, "andbits[3]" "andbits[3]" 3 169, 3 169, S_0x1921600; + .timescale -9 -12; +P_0x1921828 .param/l "i" 3 169, +C4<011>; +S_0x19218a0 .scope module, "attempt" "AndNand" 3 171, 3 48, S_0x1921730; + .timescale -9 -12; +L_0x1932520/d .functor NAND 1, L_0x1932dc0, L_0x1932eb0, C4<1>, C4<1>; +L_0x1932520 .delay (10000,10000,10000) L_0x1932520/d; +L_0x1932660/d .functor NOT 1, L_0x1932520, C4<0>, C4<0>, C4<0>; +L_0x1932660 .delay (10000,10000,10000) L_0x1932660/d; +v0x1921f00_0 .net "A", 0 0, L_0x1932dc0; 1 drivers +v0x1921fc0_0 .net "AandB", 0 0, L_0x1932660; 1 drivers +v0x1922040_0 .net "AnandB", 0 0, L_0x1932520; 1 drivers +v0x19220f0_0 .net "AndNandOut", 0 0, L_0x1932ab0; 1 drivers +v0x19221d0_0 .net "B", 0 0, L_0x1932eb0; 1 drivers +v0x1922250_0 .alias "Command", 2 0, v0x1928f70_0; +L_0x1932c80 .part v0x192a0b0_0, 0, 1; +S_0x1921990 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0x19218a0; + .timescale -9 -12; +L_0x1932790/d .functor NOT 1, L_0x1932c80, C4<0>, C4<0>, C4<0>; +L_0x1932790 .delay (10000,10000,10000) L_0x1932790/d; +L_0x1932850/d .functor AND 1, L_0x1932660, L_0x1932790, C4<1>, C4<1>; +L_0x1932850 .delay (20000,20000,20000) L_0x1932850/d; +L_0x1932960/d .functor AND 1, L_0x1932520, L_0x1932c80, C4<1>, C4<1>; +L_0x1932960 .delay (20000,20000,20000) L_0x1932960/d; +L_0x1932ab0/d .functor OR 1, L_0x1932850, L_0x1932960, C4<0>, C4<0>; +L_0x1932ab0 .delay (20000,20000,20000) L_0x1932ab0/d; +v0x1921a80_0 .net "S", 0 0, L_0x1932c80; 1 drivers +v0x1921b20_0 .alias "in0", 0 0, v0x1921fc0_0; +v0x1921bc0_0 .alias "in1", 0 0, v0x1922040_0; +v0x1921c60_0 .net "nS", 0 0, L_0x1932790; 1 drivers +v0x1921ce0_0 .net "out0", 0 0, L_0x1932850; 1 drivers +v0x1921d80_0 .net "out1", 0 0, L_0x1932960; 1 drivers +v0x1921e60_0 .alias "outfinal", 0 0, v0x19220f0_0; +S_0x191c3a0 .scope module, "trial2" "OrNorXor32" 2 145, 3 177, S_0x18c7e50; + .timescale -9 -12; +P_0x1919dc8 .param/l "size" 3 184, +C4<0100>; +v0x19212e0_0 .alias "A", 3 0, v0x1928d50_0; +v0x19213f0_0 .alias "B", 3 0, v0x1928e70_0; +v0x1921500_0 .alias "Command", 2 0, v0x1928f70_0; +v0x1921580_0 .alias "OrNorXorOut", 3 0, v0x192a1b0_0; +L_0x1934ad0 .part/pv L_0x1934860, 1, 1, 4; +L_0x1934c00 .part v0x1929e30_0, 1, 1; +L_0x192ba30 .part v0x192a030_0, 1, 1; +L_0x1936030 .part/pv L_0x1935dc0, 2, 1, 4; +L_0x19360d0 .part v0x1929e30_0, 2, 1; +L_0x1936170 .part v0x192a030_0, 2, 1; +L_0x1937250 .part/pv L_0x1924320, 3, 1, 4; +L_0x19372f0 .part v0x1929e30_0, 3, 1; +L_0x1937390 .part v0x192a030_0, 3, 1; +L_0x1938360 .part/pv L_0x1938130, 0, 1, 4; +L_0x1938460 .part v0x1929e30_0, 0, 1; +L_0x1938500 .part v0x192a030_0, 0, 1; +S_0x19200a0 .scope module, "attempt2" "OrNorXor" 3 192, 3 64, S_0x191c3a0; + .timescale -9 -12; +L_0x1937430/d .functor NOR 1, L_0x1938460, L_0x1938500, C4<0>, C4<0>; +L_0x1937430 .delay (10000,10000,10000) L_0x1937430/d; +L_0x1937530/d .functor NOT 1, L_0x1937430, C4<0>, C4<0>, C4<0>; +L_0x1937530 .delay (10000,10000,10000) L_0x1937530/d; +L_0x1937620/d .functor NAND 1, L_0x1938460, L_0x1938500, C4<1>, C4<1>; +L_0x1937620 .delay (10000,10000,10000) L_0x1937620/d; +L_0x1937760/d .functor NAND 1, L_0x1937620, L_0x1937530, C4<1>, C4<1>; +L_0x1937760 .delay (10000,10000,10000) L_0x1937760/d; +L_0x1937850/d .functor NOT 1, L_0x1937760, C4<0>, C4<0>, C4<0>; +L_0x1937850 .delay (10000,10000,10000) L_0x1937850/d; +v0x1920bf0_0 .net "A", 0 0, L_0x1938460; 1 drivers +v0x1920c90_0 .net "AnandB", 0 0, L_0x1937620; 1 drivers +v0x1920d30_0 .net "AnorB", 0 0, L_0x1937430; 1 drivers +v0x1920de0_0 .net "AorB", 0 0, L_0x1937530; 1 drivers +v0x1920ec0_0 .net "AxorB", 0 0, L_0x1937850; 1 drivers +v0x1920f70_0 .net "B", 0 0, L_0x1938500; 1 drivers +v0x1921030_0 .alias "Command", 2 0, v0x1928f70_0; +v0x19210b0_0 .net "OrNorXorOut", 0 0, L_0x1938130; 1 drivers +v0x1921130_0 .net "XorNor", 0 0, L_0x1937c50; 1 drivers +v0x1921200_0 .net "nXor", 0 0, L_0x1937760; 1 drivers +L_0x1937d90 .part v0x192a0b0_0, 2, 1; +L_0x19382c0 .part v0x192a0b0_0, 0, 1; +S_0x1920680 .scope module, "mux0" "TwoInMux" 3 83, 3 8, S_0x19200a0; + .timescale -9 -12; +L_0x1937990/d .functor NOT 1, L_0x1937d90, C4<0>, C4<0>, C4<0>; +L_0x1937990 .delay (10000,10000,10000) L_0x1937990/d; +L_0x1937a30/d .functor AND 1, L_0x1937850, L_0x1937990, C4<1>, C4<1>; +L_0x1937a30 .delay (20000,20000,20000) L_0x1937a30/d; +L_0x1937b20/d .functor AND 1, L_0x1937430, L_0x1937d90, C4<1>, C4<1>; +L_0x1937b20 .delay (20000,20000,20000) L_0x1937b20/d; +L_0x1937c50/d .functor OR 1, L_0x1937a30, L_0x1937b20, C4<0>, C4<0>; +L_0x1937c50 .delay (20000,20000,20000) L_0x1937c50/d; +v0x1920770_0 .net "S", 0 0, L_0x1937d90; 1 drivers +v0x1920830_0 .alias "in0", 0 0, v0x1920ec0_0; +v0x19208d0_0 .alias "in1", 0 0, v0x1920d30_0; +v0x1920970_0 .net "nS", 0 0, L_0x1937990; 1 drivers +v0x19209f0_0 .net "out0", 0 0, L_0x1937a30; 1 drivers +v0x1920a90_0 .net "out1", 0 0, L_0x1937b20; 1 drivers +v0x1920b70_0 .alias "outfinal", 0 0, v0x1921130_0; +S_0x1920190 .scope module, "mux1" "TwoInMux" 3 84, 3 8, S_0x19200a0; + .timescale -9 -12; +L_0x1937e30/d .functor NOT 1, L_0x19382c0, C4<0>, C4<0>, C4<0>; +L_0x1937e30 .delay (10000,10000,10000) L_0x1937e30/d; +L_0x1937ed0/d .functor AND 1, L_0x1937c50, L_0x1937e30, C4<1>, C4<1>; +L_0x1937ed0 .delay (20000,20000,20000) L_0x1937ed0/d; +L_0x1938000/d .functor AND 1, L_0x1937530, L_0x19382c0, C4<1>, C4<1>; +L_0x1938000 .delay (20000,20000,20000) L_0x1938000/d; +L_0x1938130/d .functor OR 1, L_0x1937ed0, L_0x1938000, C4<0>, C4<0>; +L_0x1938130 .delay (20000,20000,20000) L_0x1938130/d; +v0x1920280_0 .net "S", 0 0, L_0x19382c0; 1 drivers +v0x1920300_0 .alias "in0", 0 0, v0x1921130_0; +v0x1920380_0 .alias "in1", 0 0, v0x1920de0_0; +v0x1920420_0 .net "nS", 0 0, L_0x1937e30; 1 drivers +v0x19204a0_0 .net "out0", 0 0, L_0x1937ed0; 1 drivers +v0x1920540_0 .net "out1", 0 0, L_0x1938000; 1 drivers +v0x19205e0_0 .alias "outfinal", 0 0, v0x19210b0_0; +S_0x191ecd0 .scope generate, "orbits[1]" "orbits[1]" 3 196, 3 196, S_0x191c3a0; + .timescale -9 -12; +P_0x191e9e8 .param/l "i" 3 196, +C4<01>; +S_0x191ee00 .scope module, "attempt" "OrNorXor" 3 198, 3 64, S_0x191ecd0; + .timescale -9 -12; +L_0x1933820/d .functor NOR 1, L_0x1934c00, L_0x192ba30, C4<0>, C4<0>; +L_0x1933820 .delay (10000,10000,10000) L_0x1933820/d; +L_0x1933ac0/d .functor NOT 1, L_0x1933820, C4<0>, C4<0>, C4<0>; +L_0x1933ac0 .delay (10000,10000,10000) L_0x1933ac0/d; +L_0x1933bf0/d .functor NAND 1, L_0x1934c00, L_0x192ba30, C4<1>, C4<1>; +L_0x1933bf0 .delay (10000,10000,10000) L_0x1933bf0/d; +L_0x1933d50/d .functor NAND 1, L_0x1933bf0, L_0x1933ac0, C4<1>, C4<1>; +L_0x1933d50 .delay (10000,10000,10000) L_0x1933d50/d; +L_0x1933e60/d .functor NOT 1, L_0x1933d50, C4<0>, C4<0>, C4<0>; +L_0x1933e60 .delay (10000,10000,10000) L_0x1933e60/d; +v0x191f9b0_0 .net "A", 0 0, L_0x1934c00; 1 drivers +v0x191fa50_0 .net "AnandB", 0 0, L_0x1933bf0; 1 drivers +v0x191faf0_0 .net "AnorB", 0 0, L_0x1933820; 1 drivers +v0x191fba0_0 .net "AorB", 0 0, L_0x1933ac0; 1 drivers +v0x191fc80_0 .net "AxorB", 0 0, L_0x1933e60; 1 drivers +v0x191fd30_0 .net "B", 0 0, L_0x192ba30; 1 drivers +v0x191fdf0_0 .alias "Command", 2 0, v0x1928f70_0; +v0x191fe70_0 .net "OrNorXorOut", 0 0, L_0x1934860; 1 drivers +v0x191fef0_0 .net "XorNor", 0 0, L_0x19342e0; 1 drivers +v0x191ffc0_0 .net "nXor", 0 0, L_0x1933d50; 1 drivers +L_0x1934460 .part v0x192a0b0_0, 2, 1; +L_0x1934a30 .part v0x192a0b0_0, 0, 1; +S_0x191f440 .scope module, "mux0" "TwoInMux" 3 83, 3 8, S_0x191ee00; + .timescale -9 -12; +L_0x1933fc0/d .functor NOT 1, L_0x1934460, C4<0>, C4<0>, C4<0>; +L_0x1933fc0 .delay (10000,10000,10000) L_0x1933fc0/d; +L_0x1934080/d .functor AND 1, L_0x1933e60, L_0x1933fc0, C4<1>, C4<1>; +L_0x1934080 .delay (20000,20000,20000) L_0x1934080/d; +L_0x1934190/d .functor AND 1, L_0x1933820, L_0x1934460, C4<1>, C4<1>; +L_0x1934190 .delay (20000,20000,20000) L_0x1934190/d; +L_0x19342e0/d .functor OR 1, L_0x1934080, L_0x1934190, C4<0>, C4<0>; +L_0x19342e0 .delay (20000,20000,20000) L_0x19342e0/d; +v0x191f530_0 .net "S", 0 0, L_0x1934460; 1 drivers +v0x191f5f0_0 .alias "in0", 0 0, v0x191fc80_0; +v0x191f690_0 .alias "in1", 0 0, v0x191faf0_0; +v0x191f730_0 .net "nS", 0 0, L_0x1933fc0; 1 drivers +v0x191f7b0_0 .net "out0", 0 0, L_0x1934080; 1 drivers +v0x191f850_0 .net "out1", 0 0, L_0x1934190; 1 drivers +v0x191f930_0 .alias "outfinal", 0 0, v0x191fef0_0; +S_0x191eef0 .scope module, "mux1" "TwoInMux" 3 84, 3 8, S_0x191ee00; + .timescale -9 -12; +L_0x1934500/d .functor NOT 1, L_0x1934a30, C4<0>, C4<0>, C4<0>; +L_0x1934500 .delay (10000,10000,10000) L_0x1934500/d; +L_0x19345c0/d .functor AND 1, L_0x19342e0, L_0x1934500, C4<1>, C4<1>; +L_0x19345c0 .delay (20000,20000,20000) L_0x19345c0/d; +L_0x1934710/d .functor AND 1, L_0x1933ac0, L_0x1934a30, C4<1>, C4<1>; +L_0x1934710 .delay (20000,20000,20000) L_0x1934710/d; +L_0x1934860/d .functor OR 1, L_0x19345c0, L_0x1934710, C4<0>, C4<0>; +L_0x1934860 .delay (20000,20000,20000) L_0x1934860/d; +v0x191efe0_0 .net "S", 0 0, L_0x1934a30; 1 drivers +v0x191f060_0 .alias "in0", 0 0, v0x191fef0_0; +v0x191f100_0 .alias "in1", 0 0, v0x191fba0_0; +v0x191f1a0_0 .net "nS", 0 0, L_0x1934500; 1 drivers +v0x191f220_0 .net "out0", 0 0, L_0x19345c0; 1 drivers +v0x191f2c0_0 .net "out1", 0 0, L_0x1934710; 1 drivers +v0x191f3a0_0 .alias "outfinal", 0 0, v0x191fe70_0; +S_0x191d900 .scope generate, "orbits[2]" "orbits[2]" 3 196, 3 196, S_0x191c3a0; + .timescale -9 -12; +P_0x191d568 .param/l "i" 3 196, +C4<010>; +S_0x191da30 .scope module, "attempt" "OrNorXor" 3 198, 3 64, S_0x191d900; + .timescale -9 -12; +L_0x192bad0/d .functor NOR 1, L_0x19360d0, L_0x1936170, C4<0>, C4<0>; +L_0x192bad0 .delay (10000,10000,10000) L_0x192bad0/d; +L_0x192bc40/d .functor NOT 1, L_0x192bad0, C4<0>, C4<0>, C4<0>; +L_0x192bc40 .delay (10000,10000,10000) L_0x192bc40/d; +L_0x1935150/d .functor NAND 1, L_0x19360d0, L_0x1936170, C4<1>, C4<1>; +L_0x1935150 .delay (10000,10000,10000) L_0x1935150/d; +L_0x19352b0/d .functor NAND 1, L_0x1935150, L_0x192bc40, C4<1>, C4<1>; +L_0x19352b0 .delay (10000,10000,10000) L_0x19352b0/d; +L_0x19353c0/d .functor NOT 1, L_0x19352b0, C4<0>, C4<0>, C4<0>; +L_0x19353c0 .delay (10000,10000,10000) L_0x19353c0/d; +v0x191e5e0_0 .net "A", 0 0, L_0x19360d0; 1 drivers +v0x191e680_0 .net "AnandB", 0 0, L_0x1935150; 1 drivers +v0x191e720_0 .net "AnorB", 0 0, L_0x192bad0; 1 drivers +v0x191e7d0_0 .net "AorB", 0 0, L_0x192bc40; 1 drivers +v0x191e8b0_0 .net "AxorB", 0 0, L_0x19353c0; 1 drivers +v0x191e960_0 .net "B", 0 0, L_0x1936170; 1 drivers +v0x191ea20_0 .alias "Command", 2 0, v0x1928f70_0; +v0x191eaa0_0 .net "OrNorXorOut", 0 0, L_0x1935dc0; 1 drivers +v0x191eb20_0 .net "XorNor", 0 0, L_0x1935840; 1 drivers +v0x191ebf0_0 .net "nXor", 0 0, L_0x19352b0; 1 drivers +L_0x19359c0 .part v0x192a0b0_0, 2, 1; +L_0x1935f90 .part v0x192a0b0_0, 0, 1; +S_0x191e070 .scope module, "mux0" "TwoInMux" 3 83, 3 8, S_0x191da30; + .timescale -9 -12; +L_0x1935520/d .functor NOT 1, L_0x19359c0, C4<0>, C4<0>, C4<0>; +L_0x1935520 .delay (10000,10000,10000) L_0x1935520/d; +L_0x19355e0/d .functor AND 1, L_0x19353c0, L_0x1935520, C4<1>, C4<1>; +L_0x19355e0 .delay (20000,20000,20000) L_0x19355e0/d; +L_0x19356f0/d .functor AND 1, L_0x192bad0, L_0x19359c0, C4<1>, C4<1>; +L_0x19356f0 .delay (20000,20000,20000) L_0x19356f0/d; +L_0x1935840/d .functor OR 1, L_0x19355e0, L_0x19356f0, C4<0>, C4<0>; +L_0x1935840 .delay (20000,20000,20000) L_0x1935840/d; +v0x191e160_0 .net "S", 0 0, L_0x19359c0; 1 drivers +v0x191e220_0 .alias "in0", 0 0, v0x191e8b0_0; +v0x191e2c0_0 .alias "in1", 0 0, v0x191e720_0; +v0x191e360_0 .net "nS", 0 0, L_0x1935520; 1 drivers +v0x191e3e0_0 .net "out0", 0 0, L_0x19355e0; 1 drivers +v0x191e480_0 .net "out1", 0 0, L_0x19356f0; 1 drivers +v0x191e560_0 .alias "outfinal", 0 0, v0x191eb20_0; +S_0x191db20 .scope module, "mux1" "TwoInMux" 3 84, 3 8, S_0x191da30; + .timescale -9 -12; +L_0x1935a60/d .functor NOT 1, L_0x1935f90, C4<0>, C4<0>, C4<0>; +L_0x1935a60 .delay (10000,10000,10000) L_0x1935a60/d; +L_0x1935b20/d .functor AND 1, L_0x1935840, L_0x1935a60, C4<1>, C4<1>; +L_0x1935b20 .delay (20000,20000,20000) L_0x1935b20/d; +L_0x1935c70/d .functor AND 1, L_0x192bc40, L_0x1935f90, C4<1>, C4<1>; +L_0x1935c70 .delay (20000,20000,20000) L_0x1935c70/d; +L_0x1935dc0/d .functor OR 1, L_0x1935b20, L_0x1935c70, C4<0>, C4<0>; +L_0x1935dc0 .delay (20000,20000,20000) L_0x1935dc0/d; +v0x191dc10_0 .net "S", 0 0, L_0x1935f90; 1 drivers +v0x191dc90_0 .alias "in0", 0 0, v0x191eb20_0; +v0x191dd30_0 .alias "in1", 0 0, v0x191e7d0_0; +v0x191ddd0_0 .net "nS", 0 0, L_0x1935a60; 1 drivers +v0x191de50_0 .net "out0", 0 0, L_0x1935b20; 1 drivers +v0x191def0_0 .net "out1", 0 0, L_0x1935c70; 1 drivers +v0x191dfd0_0 .alias "outfinal", 0 0, v0x191eaa0_0; +S_0x191c490 .scope generate, "orbits[3]" "orbits[3]" 3 196, 3 196, S_0x191c3a0; + .timescale -9 -12; +P_0x191c1d8 .param/l "i" 3 196, +C4<011>; +S_0x191c580 .scope module, "attempt" "OrNorXor" 3 198, 3 64, S_0x191c490; + .timescale -9 -12; +L_0x1936250/d .functor NOR 1, L_0x19372f0, L_0x1937390, C4<0>, C4<0>; +L_0x1936250 .delay (10000,10000,10000) L_0x1936250/d; +L_0x1936340/d .functor NOT 1, L_0x1936250, C4<0>, C4<0>, C4<0>; +L_0x1936340 .delay (10000,10000,10000) L_0x1936340/d; +L_0x1936450/d .functor NAND 1, L_0x19372f0, L_0x1937390, C4<1>, C4<1>; +L_0x1936450 .delay (10000,10000,10000) L_0x1936450/d; +L_0x19365b0/d .functor NAND 1, L_0x1936450, L_0x1936340, C4<1>, C4<1>; +L_0x19365b0 .delay (10000,10000,10000) L_0x19365b0/d; +L_0x19366c0/d .functor NOT 1, L_0x19365b0, C4<0>, C4<0>, C4<0>; +L_0x19366c0 .delay (10000,10000,10000) L_0x19366c0/d; +v0x191d160_0 .net "A", 0 0, L_0x19372f0; 1 drivers +v0x191d200_0 .net "AnandB", 0 0, L_0x1936450; 1 drivers +v0x191d2a0_0 .net "AnorB", 0 0, L_0x1936250; 1 drivers +v0x191d350_0 .net "AorB", 0 0, L_0x1936340; 1 drivers +v0x191d430_0 .net "AxorB", 0 0, L_0x19366c0; 1 drivers +v0x191d4e0_0 .net "B", 0 0, L_0x1937390; 1 drivers +v0x191d5a0_0 .alias "Command", 2 0, v0x1928f70_0; +v0x1915a00_0 .net "OrNorXorOut", 0 0, L_0x1924320; 1 drivers +v0x1915a80_0 .net "XorNor", 0 0, L_0x1936b40; 1 drivers +v0x191d880_0 .net "nXor", 0 0, L_0x19365b0; 1 drivers +L_0x1936cc0 .part v0x192a0b0_0, 2, 1; +L_0x19371b0 .part v0x192a0b0_0, 0, 1; +S_0x191cbf0 .scope module, "mux0" "TwoInMux" 3 83, 3 8, S_0x191c580; + .timescale -9 -12; +L_0x1936820/d .functor NOT 1, L_0x1936cc0, C4<0>, C4<0>, C4<0>; +L_0x1936820 .delay (10000,10000,10000) L_0x1936820/d; +L_0x19368e0/d .functor AND 1, L_0x19366c0, L_0x1936820, C4<1>, C4<1>; +L_0x19368e0 .delay (20000,20000,20000) L_0x19368e0/d; +L_0x19369f0/d .functor AND 1, L_0x1936250, L_0x1936cc0, C4<1>, C4<1>; +L_0x19369f0 .delay (20000,20000,20000) L_0x19369f0/d; +L_0x1936b40/d .functor OR 1, L_0x19368e0, L_0x19369f0, C4<0>, C4<0>; +L_0x1936b40 .delay (20000,20000,20000) L_0x1936b40/d; +v0x191cce0_0 .net "S", 0 0, L_0x1936cc0; 1 drivers +v0x191cda0_0 .alias "in0", 0 0, v0x191d430_0; +v0x191ce40_0 .alias "in1", 0 0, v0x191d2a0_0; +v0x191cee0_0 .net "nS", 0 0, L_0x1936820; 1 drivers +v0x191cf60_0 .net "out0", 0 0, L_0x19368e0; 1 drivers +v0x191d000_0 .net "out1", 0 0, L_0x19369f0; 1 drivers +v0x191d0e0_0 .alias "outfinal", 0 0, v0x1915a80_0; +S_0x191c670 .scope module, "mux1" "TwoInMux" 3 84, 3 8, S_0x191c580; + .timescale -9 -12; +L_0x1936d60/d .functor NOT 1, L_0x19371b0, C4<0>, C4<0>, C4<0>; +L_0x1936d60 .delay (10000,10000,10000) L_0x1936d60/d; +L_0x1936e20/d .functor AND 1, L_0x1936b40, L_0x1936d60, C4<1>, C4<1>; +L_0x1936e20 .delay (20000,20000,20000) L_0x1936e20/d; +L_0x1936f70/d .functor AND 1, L_0x1936340, L_0x19371b0, C4<1>, C4<1>; +L_0x1936f70 .delay (20000,20000,20000) L_0x1936f70/d; +L_0x1924320/d .functor OR 1, L_0x1936e20, L_0x1936f70, C4<0>, C4<0>; +L_0x1924320 .delay (20000,20000,20000) L_0x1924320/d; +v0x191c760_0 .net "S", 0 0, L_0x19371b0; 1 drivers +v0x191c7e0_0 .alias "in0", 0 0, v0x1915a80_0; +v0x191c880_0 .alias "in1", 0 0, v0x191d350_0; +v0x191c920_0 .net "nS", 0 0, L_0x1936d60; 1 drivers +v0x191c9d0_0 .net "out0", 0 0, L_0x1936e20; 1 drivers +v0x191ca70_0 .net "out1", 0 0, L_0x1936f70; 1 drivers +v0x191cb50_0 .alias "outfinal", 0 0, v0x1915a00_0; +S_0x18a5800 .scope module, "superalu" "Bitslice32" 2 147, 3 256, S_0x18c7e50; + .timescale -9 -12; +P_0x1880428 .param/l "size" 3 273, +C4<0100>; +L_0x193d900/d .functor AND 1, L_0x19505f0, L_0x19507d0, C4<1>, C4<1>; +L_0x193d900 .delay (20000,20000,20000) L_0x193d900/d; +L_0x19508c0/d .functor NOT 1, L_0x1950970, C4<0>, C4<0>, C4<0>; +L_0x19508c0 .delay (10000,10000,10000) L_0x19508c0/d; +L_0x1950e20/d .functor AND 1, L_0x19508c0, L_0x19508c0, C4<1>, C4<1>; +L_0x1950e20 .delay (20000,20000,20000) L_0x1950e20/d; +v0x191b290_0 .alias "A", 3 0, v0x1928d50_0; +v0x191b480_0 .alias "AddSubSLTSum", 3 0, v0x1929eb0_0; +v0x191b500_0 .alias "AllZeros", 0 0, v0x1929f30_0; +v0x191b580_0 .alias "AndNandOut", 3 0, v0x1929fb0_0; +v0x191b630_0 .alias "B", 3 0, v0x1928e70_0; +RS_0x7f644c9d5008 .resolv tri, L_0x1938e00, L_0x193b860, L_0x193e660, L_0x194e9c0; +v0x191b6b0_0 .net8 "Cmd0Start", 3 0, RS_0x7f644c9d5008; 4 drivers +RS_0x7f644c9d5038 .resolv tri, L_0x1939d70, L_0x193c750, L_0x193f650, L_0x194f7f0; +v0x191b730_0 .net8 "Cmd1Start", 3 0, RS_0x7f644c9d5038; 4 drivers +v0x191b7b0_0 .alias "Command", 2 0, v0x1928f70_0; +v0x191b830_0 .alias "OneBitFinalOut", 3 0, v0x192a130_0; +v0x191b8d0_0 .alias "OrNorXorOut", 3 0, v0x192a1b0_0; +v0x191b950_0 .alias "SLTflag", 0 0, v0x192a230_0; +v0x191ba00_0 .alias "ZeroFlag", 3 0, v0x192a2b0_0; +v0x191ba80_0 .net *"_s111", 0 0, L_0x193d900; 1 drivers +v0x191bb00_0 .net *"_s114", 0 0, L_0x19505f0; 1 drivers +v0x191bc20_0 .net *"_s116", 0 0, L_0x19507d0; 1 drivers +v0x191bcc0_0 .net *"_s118", 0 0, L_0x1950970; 1 drivers +v0x191bb80_0 .net *"_s21", 0 0, L_0x193adc0; 1 drivers +v0x191be10_0 .net *"_s46", 0 0, L_0x193d1d0; 1 drivers +v0x191bf30_0 .net *"_s71", 0 0, L_0x1940410; 1 drivers +v0x191bfb0_0 .alias "carryin", 3 0, v0x19299a0_0; +v0x191be90_0 .alias "carryout", 0 0, v0x192a3b0_0; +v0x191c110_0 .alias "overflow", 0 0, v0x192a430_0; +v0x191c060_0 .alias "subtract", 3 0, v0x192a4b0_0; +v0x191c250_0 .net "yeszero", 0 0, L_0x19508c0; 1 drivers +L_0x1938e00 .part/pv L_0x1938bf0, 1, 1, 4; +L_0x1938ea0 .part v0x192a0b0_0, 0, 1; +L_0x1938fd0 .part v0x192a0b0_0, 1, 1; +L_0x1939100 .part RS_0x7f644c9d4be8, 1, 1; +L_0x19391a0 .part RS_0x7f644c9d4be8, 1, 1; +L_0x1939240 .part RS_0x7f644c9d3748, 1, 1; +L_0x1939440 .part RS_0x7f644c9d4be8, 1, 1; +L_0x1939d70 .part/pv L_0x1939b60, 1, 1, 4; +L_0x1939e60 .part v0x192a0b0_0, 0, 1; +L_0x1939f90 .part v0x192a0b0_0, 1, 1; +L_0x193a120 .part RS_0x7f644c9d3e38, 1, 1; +L_0x193a2d0 .part RS_0x7f644c9d3e38, 1, 1; +L_0x193a370 .part RS_0x7f644c9d3748, 1, 1; +L_0x193a410 .part RS_0x7f644c9d3748, 1, 1; +L_0x193a870 .part/pv L_0x193a730, 1, 1, 4; +L_0x193a960 .part v0x192a0b0_0, 2, 1; +L_0x193aa00 .part RS_0x7f644c9d5008, 1, 1; +L_0x193ab40 .part RS_0x7f644c9d5038, 1, 1; +L_0x193ad20 .part/pv L_0x193adc0, 1, 1, 4; +L_0x193aec0 .part RS_0x7f644c9d5098, 0, 1; +L_0x193ac80 .part RS_0x7f644c9d5068, 1, 1; +L_0x193b860 .part/pv L_0x193b650, 2, 1, 4; +L_0x193af60 .part v0x192a0b0_0, 0, 1; +L_0x193ba50 .part v0x192a0b0_0, 1, 1; +L_0x193b900 .part RS_0x7f644c9d4be8, 2, 1; +L_0x193bc50 .part RS_0x7f644c9d4be8, 2, 1; +L_0x193bb80 .part RS_0x7f644c9d3748, 2, 1; +L_0x193be20 .part RS_0x7f644c9d4be8, 2, 1; +L_0x193c750 .part/pv L_0x193c540, 2, 1, 4; +L_0x193c7f0 .part v0x192a0b0_0, 0, 1; +L_0x193bf10 .part v0x192a0b0_0, 1, 1; +L_0x192ad80 .part RS_0x7f644c9d3e38, 2, 1; +L_0x192af30 .part RS_0x7f644c9d3e38, 2, 1; +L_0x192abf0 .part RS_0x7f644c9d3748, 2, 1; +L_0x192ae20 .part RS_0x7f644c9d3748, 2, 1; +L_0x193d600 .part/pv L_0x193d4c0, 2, 1, 4; +L_0x193d130 .part v0x192a0b0_0, 2, 1; +L_0x193d860 .part RS_0x7f644c9d5008, 2, 1; +L_0x193d730 .part RS_0x7f644c9d5038, 2, 1; +L_0x193dad0 .part/pv L_0x193d1d0, 2, 1, 4; +L_0x193d9d0 .part RS_0x7f644c9d5098, 1, 1; +L_0x193dd50 .part RS_0x7f644c9d5068, 2, 1; +L_0x193e660 .part/pv L_0x193e450, 3, 1, 4; +L_0x193e700 .part v0x192a0b0_0, 0, 1; +L_0x193ddf0 .part v0x192a0b0_0, 1, 1; +L_0x193e9a0 .part RS_0x7f644c9d4be8, 3, 1; +L_0x1930820 .part RS_0x7f644c9d4be8, 3, 1; +L_0x193e830 .part RS_0x7f644c9d3748, 3, 1; +L_0x193ede0 .part RS_0x7f644c9d4be8, 3, 1; +L_0x193f650 .part/pv L_0x193f440, 3, 1, 4; +L_0x193ec50 .part v0x192a0b0_0, 0, 1; +L_0x193f890 .part v0x192a0b0_0, 1, 1; +L_0x193f6f0 .part RS_0x7f644c9d3e38, 3, 1; +L_0x193f790 .part RS_0x7f644c9d3e38, 3, 1; +L_0x193fb80 .part RS_0x7f644c9d3748, 3, 1; +L_0x193fc20 .part RS_0x7f644c9d3748, 3, 1; +L_0x1940230 .part/pv L_0x19400f0, 3, 1, 4; +L_0x19402d0 .part v0x192a0b0_0, 2, 1; +L_0x193fed0 .part RS_0x7f644c9d5008, 3, 1; +L_0x193ffc0 .part RS_0x7f644c9d5038, 3, 1; +L_0x1940370 .part/pv L_0x1940410, 3, 1, 4; +L_0x1940790 .part RS_0x7f644c9d5098, 2, 1; +L_0x19405a0 .part RS_0x7f644c9d5068, 3, 1; +L_0x194e9c0 .part/pv L_0x194e7e0, 0, 1, 4; +L_0x1940830 .part v0x192a0b0_0, 0, 1; +L_0x1940960 .part v0x192a0b0_0, 1, 1; +L_0x194ea60 .part RS_0x7f644c9d4be8, 0, 1; +L_0x194eb00 .part RS_0x7f644c9d4be8, 0, 1; +L_0x194eba0 .part RS_0x7f644c9d3748, 0, 1; +L_0x194ef80 .part RS_0x7f644c9d4be8, 0, 1; +L_0x194f7f0 .part/pv L_0x194f610, 0, 1, 4; +L_0x194f890 .part v0x192a0b0_0, 0, 1; +L_0x194f070 .part v0x192a0b0_0, 1, 1; +L_0x194f1a0 .part RS_0x7f644c9d3e38, 0, 1; +L_0x194fc20 .part RS_0x7f644c9d3e38, 0, 1; +L_0x194fcc0 .part RS_0x7f644c9d3748, 0, 1; +L_0x194f9c0 .part RS_0x7f644c9d3748, 0, 1; +L_0x1950290 .part/pv L_0x1950150, 0, 1, 4; +L_0x194fd60 .part v0x192a0b0_0, 2, 1; +L_0x194fe00 .part RS_0x7f644c9d5008, 0, 1; +L_0x194fef0 .part RS_0x7f644c9d5038, 0, 1; +L_0x1950550 .part/pv L_0x193d900, 0, 1, 4; +L_0x19505f0 .part RS_0x7f644c9d5068, 0, 1; +L_0x19507d0 .part RS_0x7f644c9d5068, 0, 1; +L_0x1950970 .part RS_0x7f644c9d5098, 3, 1; +S_0x1915cf0 .scope module, "trial" "AddSubSLT32" 3 279, 3 205, S_0x18a5800; + .timescale -9 -12; +P_0x1915de8 .param/l "size" 3 228, +C4<0100>; +L_0x1945950/d .functor OR 1, L_0x1945c10, C4<0>, C4<0>, C4<0>; +L_0x1945950 .delay (20000,20000,20000) L_0x1945950/d; +L_0x1945dc0/d .functor XOR 1, RS_0x7f644c9d4ee8, L_0x1945eb0, C4<0>, C4<0>; +L_0x1945dc0 .delay (40000,40000,40000) L_0x1945dc0/d; +L_0x1945b40/d .functor AND 1, L_0x1946080, L_0x1946120, C4<1>, C4<1>; +L_0x1945b40 .delay (20000,20000,20000) L_0x1945b40/d; +L_0x1945f50/d .functor NOT 1, RS_0x7f644c9d4f78, C4<0>, C4<0>, C4<0>; +L_0x1945f50 .delay (10000,10000,10000) L_0x1945f50/d; +L_0x1946410/d .functor NOT 1, L_0x1946470, C4<0>, C4<0>, C4<0>; +L_0x1946410 .delay (10000,10000,10000) L_0x1946410/d; +L_0x1946510/d .functor AND 1, L_0x1945f50, L_0x1946650, C4<1>, C4<1>; +L_0x1946510 .delay (20000,20000,20000) L_0x1946510/d; +L_0x1946210/d .functor AND 1, RS_0x7f644c9d4f78, L_0x1946410, C4<1>, C4<1>; +L_0x1946210 .delay (20000,20000,20000) L_0x1946210/d; +L_0x1946840/d .functor AND 1, L_0x1946510, L_0x1945b40, C4<1>, C4<1>; +L_0x1946840 .delay (20000,20000,20000) L_0x1946840/d; +L_0x1946980/d .functor AND 1, L_0x1946210, L_0x1945b40, C4<1>, C4<1>; +L_0x1946980 .delay (20000,20000,20000) L_0x1946980/d; +L_0x1946aa0/d .functor OR 1, L_0x1946840, L_0x1946980, C4<0>, C4<0>; +L_0x1946aa0 .delay (20000,20000,20000) L_0x1946aa0/d; +v0x191a3b0_0 .alias "A", 3 0, v0x1928d50_0; +v0x191a450_0 .alias "AddSubSLTSum", 3 0, v0x1929eb0_0; +v0x191a4f0_0 .alias "B", 3 0, v0x1928e70_0; +RS_0x7f644c9d4c18 .resolv tri, L_0x19418c0, L_0x1942ce0, L_0x19440e0, L_0x19456c0; +v0x191a5c0_0 .net8 "CarryoutWire", 3 0, RS_0x7f644c9d4c18; 4 drivers +v0x191a640_0 .alias "Command", 2 0, v0x1928f70_0; +v0x191a6c0_0 .net "Res0OF1", 0 0, L_0x1946210; 1 drivers +v0x191a760_0 .net "Res1OF0", 0 0, L_0x1946510; 1 drivers +v0x191a800_0 .alias "SLTflag", 0 0, v0x192a230_0; +v0x191a8f0_0 .net "SLTflag0", 0 0, L_0x1946840; 1 drivers +v0x191a990_0 .net "SLTflag1", 0 0, L_0x1946980; 1 drivers +v0x191aa30_0 .net "SLTon", 0 0, L_0x1945b40; 1 drivers +v0x191aad0_0 .net *"_s40", 0 0, L_0x1945c10; 1 drivers +v0x191ab70_0 .net/s *"_s41", 0 0, C4<0>; 1 drivers +v0x191ac10_0 .net *"_s44", 0 0, L_0x1945eb0; 1 drivers +v0x191ad30_0 .net *"_s46", 0 0, L_0x1946080; 1 drivers +v0x191add0_0 .net *"_s48", 0 0, L_0x1946120; 1 drivers +v0x191ac90_0 .net *"_s50", 0 0, L_0x1946470; 1 drivers +v0x191af20_0 .net *"_s52", 0 0, L_0x1946650; 1 drivers +v0x191b040_0 .alias "carryin", 3 0, v0x19299a0_0; +v0x191b0c0_0 .alias "carryout", 0 0, v0x192a3b0_0; +v0x191afa0_0 .net "nAddSubSLTSum", 0 0, L_0x1946410; 1 drivers +v0x191b1f0_0 .net "nOF", 0 0, L_0x1945f50; 1 drivers +v0x191b140_0 .alias "overflow", 0 0, v0x192a430_0; +v0x191b330_0 .alias "subtract", 3 0, v0x192a4b0_0; +L_0x19417d0 .part/pv L_0x1941340, 1, 1, 4; +L_0x19418c0 .part/pv L_0x1941690, 1, 1, 4; +L_0x19419b0 .part/pv L_0x1941070, 1, 1, 4; +L_0x1941aa0 .part v0x1929e30_0, 1, 1; +L_0x1941b40 .part v0x192a030_0, 1, 1; +L_0x1941c70 .part RS_0x7f644c9d4c18, 0, 1; +L_0x1942bf0 .part/pv L_0x1942760, 2, 1, 4; +L_0x1942ce0 .part/pv L_0x1942ab0, 2, 1, 4; +L_0x1942e20 .part/pv L_0x1942490, 2, 1, 4; +L_0x1942f10 .part v0x1929e30_0, 2, 1; +L_0x1943010 .part v0x192a030_0, 2, 1; +L_0x1943140 .part RS_0x7f644c9d4c18, 1, 1; +L_0x1943ff0 .part/pv L_0x1943b60, 3, 1, 4; +L_0x19440e0 .part/pv L_0x1943eb0, 3, 1, 4; +L_0x1944250 .part/pv L_0x1943890, 3, 1, 4; +L_0x1944340 .part v0x1929e30_0, 3, 1; +L_0x1944470 .part v0x192a030_0, 3, 1; +L_0x19445a0 .part RS_0x7f644c9d4c18, 2, 1; +L_0x19455d0 .part/pv L_0x1945100, 0, 1, 4; +L_0x19456c0 .part/pv L_0x1945470, 0, 1, 4; +L_0x1944640 .part/pv L_0x1944e30, 0, 1, 4; +L_0x19458b0 .part v0x1929e30_0, 0, 1; +L_0x19457b0 .part v0x192a030_0, 0, 1; +L_0x1945aa0 .part RS_0x7f644c9d4fa8, 0, 1; +L_0x1945c10 .part RS_0x7f644c9d4c18, 3, 1; +L_0x1945eb0 .part RS_0x7f644c9d4c18, 2, 1; +L_0x1946080 .part v0x192a0b0_0, 1, 1; +L_0x1946120 .part RS_0x7f644c9d4fa8, 0, 1; +L_0x1946470 .part RS_0x7f644c9d4be8, 3, 1; +L_0x1946650 .part RS_0x7f644c9d4be8, 3, 1; +S_0x19193a0 .scope module, "attempt2" "MiddleAddSubSLT" 3 225, 3 89, S_0x1915cf0; + .timescale -9 -12; +L_0x19443e0/d .functor NOT 1, L_0x19457b0, C4<0>, C4<0>, C4<0>; +L_0x19443e0 .delay (10000,10000,10000) L_0x19443e0/d; +L_0x1944cd0/d .functor NOT 1, L_0x1944d90, C4<0>, C4<0>, C4<0>; +L_0x1944cd0 .delay (10000,10000,10000) L_0x1944cd0/d; +L_0x1944e30/d .functor AND 1, L_0x1944f70, L_0x1944cd0, C4<1>, C4<1>; +L_0x1944e30 .delay (20000,20000,20000) L_0x1944e30/d; +L_0x1945010/d .functor XOR 1, L_0x19458b0, L_0x1944a60, C4<0>, C4<0>; +L_0x1945010 .delay (40000,40000,40000) L_0x1945010/d; +L_0x1945100/d .functor XOR 1, L_0x1945010, L_0x1945aa0, C4<0>, C4<0>; +L_0x1945100 .delay (40000,40000,40000) L_0x1945100/d; +L_0x19451f0/d .functor AND 1, L_0x19458b0, L_0x1944a60, C4<1>, C4<1>; +L_0x19451f0 .delay (20000,20000,20000) L_0x19451f0/d; +L_0x1945360/d .functor AND 1, L_0x1945010, L_0x1945aa0, C4<1>, C4<1>; +L_0x1945360 .delay (20000,20000,20000) L_0x1945360/d; +L_0x1945470/d .functor OR 1, L_0x19451f0, L_0x1945360, C4<0>, C4<0>; +L_0x1945470 .delay (20000,20000,20000) L_0x1945470/d; +v0x1919a10_0 .net "A", 0 0, L_0x19458b0; 1 drivers +v0x1919ad0_0 .net "AandB", 0 0, L_0x19451f0; 1 drivers +v0x1919b70_0 .net "AddSubSLTSum", 0 0, L_0x1945100; 1 drivers +v0x1919c10_0 .net "AxorB", 0 0, L_0x1945010; 1 drivers +v0x1919c90_0 .net "B", 0 0, L_0x19457b0; 1 drivers +v0x1919d40_0 .net "BornB", 0 0, L_0x1944a60; 1 drivers +v0x1919e00_0 .net "CINandAxorB", 0 0, L_0x1945360; 1 drivers +v0x1919e80_0 .alias "Command", 2 0, v0x1928f70_0; +v0x1919f00_0 .net *"_s3", 0 0, L_0x1944d90; 1 drivers +v0x1919f80_0 .net *"_s5", 0 0, L_0x1944f70; 1 drivers +v0x191a020_0 .net "carryin", 0 0, L_0x1945aa0; 1 drivers +v0x191a0c0_0 .net "carryout", 0 0, L_0x1945470; 1 drivers +v0x191a160_0 .net "nB", 0 0, L_0x19443e0; 1 drivers +v0x191a210_0 .net "nCmd2", 0 0, L_0x1944cd0; 1 drivers +v0x191a310_0 .net "subtract", 0 0, L_0x1944e30; 1 drivers +L_0x1944c30 .part v0x192a0b0_0, 0, 1; +L_0x1944d90 .part v0x192a0b0_0, 2, 1; +L_0x1944f70 .part v0x192a0b0_0, 0, 1; +S_0x1919490 .scope module, "mux0" "TwoInMux" 3 105, 3 8, S_0x19193a0; + .timescale -9 -12; +L_0x1944780/d .functor NOT 1, L_0x1944c30, C4<0>, C4<0>, C4<0>; +L_0x1944780 .delay (10000,10000,10000) L_0x1944780/d; +L_0x1944840/d .functor AND 1, L_0x19457b0, L_0x1944780, C4<1>, C4<1>; +L_0x1944840 .delay (20000,20000,20000) L_0x1944840/d; +L_0x1944950/d .functor AND 1, L_0x19443e0, L_0x1944c30, C4<1>, C4<1>; +L_0x1944950 .delay (20000,20000,20000) L_0x1944950/d; +L_0x1944a60/d .functor OR 1, L_0x1944840, L_0x1944950, C4<0>, C4<0>; +L_0x1944a60 .delay (20000,20000,20000) L_0x1944a60/d; +v0x1919580_0 .net "S", 0 0, L_0x1944c30; 1 drivers +v0x1919640_0 .alias "in0", 0 0, v0x1919c90_0; +v0x19196e0_0 .alias "in1", 0 0, v0x191a160_0; +v0x1919780_0 .net "nS", 0 0, L_0x1944780; 1 drivers +v0x1919830_0 .net "out0", 0 0, L_0x1944840; 1 drivers +v0x19198d0_0 .net "out1", 0 0, L_0x1944950; 1 drivers +v0x1919970_0 .alias "outfinal", 0 0, v0x1919d40_0; +S_0x1918200 .scope generate, "addbits[1]" "addbits[1]" 3 230, 3 230, S_0x1915cf0; + .timescale -9 -12; +P_0x1917c18 .param/l "i" 3 230, +C4<01>; +S_0x1918370 .scope module, "attempt" "MiddleAddSubSLT" 3 232, 3 89, S_0x1918200; + .timescale -9 -12; +L_0x1940690/d .functor NOT 1, L_0x1941b40, C4<0>, C4<0>, C4<0>; +L_0x1940690 .delay (10000,10000,10000) L_0x1940690/d; +L_0x1940f30/d .functor NOT 1, L_0x1940fd0, C4<0>, C4<0>, C4<0>; +L_0x1940f30 .delay (10000,10000,10000) L_0x1940f30/d; +L_0x1941070/d .functor AND 1, L_0x19411b0, L_0x1940f30, C4<1>, C4<1>; +L_0x1941070 .delay (20000,20000,20000) L_0x1941070/d; +L_0x1941250/d .functor XOR 1, L_0x1941aa0, L_0x1940d00, C4<0>, C4<0>; +L_0x1941250 .delay (40000,40000,40000) L_0x1941250/d; +L_0x1941340/d .functor XOR 1, L_0x1941250, L_0x1941c70, C4<0>, C4<0>; +L_0x1941340 .delay (40000,40000,40000) L_0x1941340/d; +L_0x1941430/d .functor AND 1, L_0x1941aa0, L_0x1940d00, C4<1>, C4<1>; +L_0x1941430 .delay (20000,20000,20000) L_0x1941430/d; +L_0x19415a0/d .functor AND 1, L_0x1941250, L_0x1941c70, C4<1>, C4<1>; +L_0x19415a0 .delay (20000,20000,20000) L_0x19415a0/d; +L_0x1941690/d .functor OR 1, L_0x1941430, L_0x19415a0, C4<0>, C4<0>; +L_0x1941690 .delay (20000,20000,20000) L_0x1941690/d; +v0x1918a00_0 .net "A", 0 0, L_0x1941aa0; 1 drivers +v0x1918ac0_0 .net "AandB", 0 0, L_0x1941430; 1 drivers +v0x1918b60_0 .net "AddSubSLTSum", 0 0, L_0x1941340; 1 drivers +v0x1918c00_0 .net "AxorB", 0 0, L_0x1941250; 1 drivers +v0x1918c80_0 .net "B", 0 0, L_0x1941b40; 1 drivers +v0x1918d30_0 .net "BornB", 0 0, L_0x1940d00; 1 drivers +v0x1918df0_0 .net "CINandAxorB", 0 0, L_0x19415a0; 1 drivers +v0x1918e70_0 .alias "Command", 2 0, v0x1928f70_0; +v0x1918ef0_0 .net *"_s3", 0 0, L_0x1940fd0; 1 drivers +v0x1918f70_0 .net *"_s5", 0 0, L_0x19411b0; 1 drivers +v0x1919010_0 .net "carryin", 0 0, L_0x1941c70; 1 drivers +v0x19190b0_0 .net "carryout", 0 0, L_0x1941690; 1 drivers +v0x1919150_0 .net "nB", 0 0, L_0x1940690; 1 drivers +v0x1919200_0 .net "nCmd2", 0 0, L_0x1940f30; 1 drivers +v0x1919300_0 .net "subtract", 0 0, L_0x1941070; 1 drivers +L_0x1940e90 .part v0x192a0b0_0, 0, 1; +L_0x1940fd0 .part v0x192a0b0_0, 2, 1; +L_0x19411b0 .part v0x192a0b0_0, 0, 1; +S_0x1918460 .scope module, "mux0" "TwoInMux" 3 105, 3 8, S_0x1918370; + .timescale -9 -12; +L_0x1940a80/d .functor NOT 1, L_0x1940e90, C4<0>, C4<0>, C4<0>; +L_0x1940a80 .delay (10000,10000,10000) L_0x1940a80/d; +L_0x1940b20/d .functor AND 1, L_0x1941b40, L_0x1940a80, C4<1>, C4<1>; +L_0x1940b20 .delay (20000,20000,20000) L_0x1940b20/d; +L_0x1940c10/d .functor AND 1, L_0x1940690, L_0x1940e90, C4<1>, C4<1>; +L_0x1940c10 .delay (20000,20000,20000) L_0x1940c10/d; +L_0x1940d00/d .functor OR 1, L_0x1940b20, L_0x1940c10, C4<0>, C4<0>; +L_0x1940d00 .delay (20000,20000,20000) L_0x1940d00/d; +v0x1918550_0 .net "S", 0 0, L_0x1940e90; 1 drivers +v0x19185f0_0 .alias "in0", 0 0, v0x1918c80_0; +v0x1918690_0 .alias "in1", 0 0, v0x1919150_0; +v0x1918730_0 .net "nS", 0 0, L_0x1940a80; 1 drivers +v0x19187e0_0 .net "out0", 0 0, L_0x1940b20; 1 drivers +v0x1918880_0 .net "out1", 0 0, L_0x1940c10; 1 drivers +v0x1918960_0 .alias "outfinal", 0 0, v0x1918d30_0; +S_0x1917090 .scope generate, "addbits[2]" "addbits[2]" 3 230, 3 230, S_0x1915cf0; + .timescale -9 -12; +P_0x1916968 .param/l "i" 3 230, +C4<010>; +S_0x1917200 .scope module, "attempt" "MiddleAddSubSLT" 3 232, 3 89, S_0x1917090; + .timescale -9 -12; +L_0x1941d10/d .functor NOT 1, L_0x1943010, C4<0>, C4<0>, C4<0>; +L_0x1941d10 .delay (10000,10000,10000) L_0x1941d10/d; +L_0x1942350/d .functor NOT 1, L_0x19423f0, C4<0>, C4<0>, C4<0>; +L_0x1942350 .delay (10000,10000,10000) L_0x1942350/d; +L_0x1942490/d .functor AND 1, L_0x19425d0, L_0x1942350, C4<1>, C4<1>; +L_0x1942490 .delay (20000,20000,20000) L_0x1942490/d; +L_0x1942670/d .functor XOR 1, L_0x1942f10, L_0x1942120, C4<0>, C4<0>; +L_0x1942670 .delay (40000,40000,40000) L_0x1942670/d; +L_0x1942760/d .functor XOR 1, L_0x1942670, L_0x1943140, C4<0>, C4<0>; +L_0x1942760 .delay (40000,40000,40000) L_0x1942760/d; +L_0x1942850/d .functor AND 1, L_0x1942f10, L_0x1942120, C4<1>, C4<1>; +L_0x1942850 .delay (20000,20000,20000) L_0x1942850/d; +L_0x19429c0/d .functor AND 1, L_0x1942670, L_0x1943140, C4<1>, C4<1>; +L_0x19429c0 .delay (20000,20000,20000) L_0x19429c0/d; +L_0x1942ab0/d .functor OR 1, L_0x1942850, L_0x19429c0, C4<0>, C4<0>; +L_0x1942ab0 .delay (20000,20000,20000) L_0x1942ab0/d; +v0x1917860_0 .net "A", 0 0, L_0x1942f10; 1 drivers +v0x1917920_0 .net "AandB", 0 0, L_0x1942850; 1 drivers +v0x19179c0_0 .net "AddSubSLTSum", 0 0, L_0x1942760; 1 drivers +v0x1917a60_0 .net "AxorB", 0 0, L_0x1942670; 1 drivers +v0x1917ae0_0 .net "B", 0 0, L_0x1943010; 1 drivers +v0x1917b90_0 .net "BornB", 0 0, L_0x1942120; 1 drivers +v0x1917c50_0 .net "CINandAxorB", 0 0, L_0x19429c0; 1 drivers +v0x1917cd0_0 .alias "Command", 2 0, v0x1928f70_0; +v0x1917d50_0 .net *"_s3", 0 0, L_0x19423f0; 1 drivers +v0x1917dd0_0 .net *"_s5", 0 0, L_0x19425d0; 1 drivers +v0x1917e70_0 .net "carryin", 0 0, L_0x1943140; 1 drivers +v0x1917f10_0 .net "carryout", 0 0, L_0x1942ab0; 1 drivers +v0x1917fb0_0 .net "nB", 0 0, L_0x1941d10; 1 drivers +v0x1918060_0 .net "nCmd2", 0 0, L_0x1942350; 1 drivers +v0x1918160_0 .net "subtract", 0 0, L_0x1942490; 1 drivers +L_0x19422b0 .part v0x192a0b0_0, 0, 1; +L_0x19423f0 .part v0x192a0b0_0, 2, 1; +L_0x19425d0 .part v0x192a0b0_0, 0, 1; +S_0x19172f0 .scope module, "mux0" "TwoInMux" 3 105, 3 8, S_0x1917200; + .timescale -9 -12; +L_0x1941ea0/d .functor NOT 1, L_0x19422b0, C4<0>, C4<0>, C4<0>; +L_0x1941ea0 .delay (10000,10000,10000) L_0x1941ea0/d; +L_0x1941f40/d .functor AND 1, L_0x1943010, L_0x1941ea0, C4<1>, C4<1>; +L_0x1941f40 .delay (20000,20000,20000) L_0x1941f40/d; +L_0x1942030/d .functor AND 1, L_0x1941d10, L_0x19422b0, C4<1>, C4<1>; +L_0x1942030 .delay (20000,20000,20000) L_0x1942030/d; +L_0x1942120/d .functor OR 1, L_0x1941f40, L_0x1942030, C4<0>, C4<0>; +L_0x1942120 .delay (20000,20000,20000) L_0x1942120/d; +v0x19173e0_0 .net "S", 0 0, L_0x19422b0; 1 drivers +v0x1917480_0 .alias "in0", 0 0, v0x1917ae0_0; +v0x1917520_0 .alias "in1", 0 0, v0x1917fb0_0; +v0x19175c0_0 .net "nS", 0 0, L_0x1941ea0; 1 drivers +v0x1917640_0 .net "out0", 0 0, L_0x1941f40; 1 drivers +v0x19176e0_0 .net "out1", 0 0, L_0x1942030; 1 drivers +v0x19177c0_0 .alias "outfinal", 0 0, v0x1917b90_0; +S_0x1915e60 .scope generate, "addbits[3]" "addbits[3]" 3 230, 3 230, S_0x1915cf0; + .timescale -9 -12; +P_0x1915f58 .param/l "i" 3 230, +C4<011>; +S_0x1915fd0 .scope module, "attempt" "MiddleAddSubSLT" 3 232, 3 89, S_0x1915e60; + .timescale -9 -12; +L_0x1942fb0/d .functor NOT 1, L_0x1944470, C4<0>, C4<0>, C4<0>; +L_0x1942fb0 .delay (10000,10000,10000) L_0x1942fb0/d; +L_0x1943750/d .functor NOT 1, L_0x19437f0, C4<0>, C4<0>, C4<0>; +L_0x1943750 .delay (10000,10000,10000) L_0x1943750/d; +L_0x1943890/d .functor AND 1, L_0x19439d0, L_0x1943750, C4<1>, C4<1>; +L_0x1943890 .delay (20000,20000,20000) L_0x1943890/d; +L_0x1943a70/d .functor XOR 1, L_0x1944340, L_0x1943520, C4<0>, C4<0>; +L_0x1943a70 .delay (40000,40000,40000) L_0x1943a70/d; +L_0x1943b60/d .functor XOR 1, L_0x1943a70, L_0x19445a0, C4<0>, C4<0>; +L_0x1943b60 .delay (40000,40000,40000) L_0x1943b60/d; +L_0x1943c50/d .functor AND 1, L_0x1944340, L_0x1943520, C4<1>, C4<1>; +L_0x1943c50 .delay (20000,20000,20000) L_0x1943c50/d; +L_0x1943dc0/d .functor AND 1, L_0x1943a70, L_0x19445a0, C4<1>, C4<1>; +L_0x1943dc0 .delay (20000,20000,20000) L_0x1943dc0/d; +L_0x1943eb0/d .functor OR 1, L_0x1943c50, L_0x1943dc0, C4<0>, C4<0>; +L_0x1943eb0 .delay (20000,20000,20000) L_0x1943eb0/d; +v0x19165b0_0 .net "A", 0 0, L_0x1944340; 1 drivers +v0x1916670_0 .net "AandB", 0 0, L_0x1943c50; 1 drivers +v0x1916710_0 .net "AddSubSLTSum", 0 0, L_0x1943b60; 1 drivers +v0x19167b0_0 .net "AxorB", 0 0, L_0x1943a70; 1 drivers +v0x1916830_0 .net "B", 0 0, L_0x1944470; 1 drivers +v0x19168e0_0 .net "BornB", 0 0, L_0x1943520; 1 drivers +v0x19169a0_0 .net "CINandAxorB", 0 0, L_0x1943dc0; 1 drivers +v0x1916a20_0 .alias "Command", 2 0, v0x1928f70_0; +v0x1916af0_0 .net *"_s3", 0 0, L_0x19437f0; 1 drivers +v0x1916b70_0 .net *"_s5", 0 0, L_0x19439d0; 1 drivers +v0x1916c70_0 .net "carryin", 0 0, L_0x19445a0; 1 drivers +v0x1916d10_0 .net "carryout", 0 0, L_0x1943eb0; 1 drivers +v0x1916e20_0 .net "nB", 0 0, L_0x1942fb0; 1 drivers +v0x1916ed0_0 .net "nCmd2", 0 0, L_0x1943750; 1 drivers +v0x1916ff0_0 .net "subtract", 0 0, L_0x1943890; 1 drivers +L_0x19436b0 .part v0x192a0b0_0, 0, 1; +L_0x19437f0 .part v0x192a0b0_0, 2, 1; +L_0x19439d0 .part v0x192a0b0_0, 0, 1; +S_0x19160c0 .scope module, "mux0" "TwoInMux" 3 105, 3 8, S_0x1915fd0; + .timescale -9 -12; +L_0x19432e0/d .functor NOT 1, L_0x19436b0, C4<0>, C4<0>, C4<0>; +L_0x19432e0 .delay (10000,10000,10000) L_0x19432e0/d; +L_0x1943340/d .functor AND 1, L_0x1944470, L_0x19432e0, C4<1>, C4<1>; +L_0x1943340 .delay (20000,20000,20000) L_0x1943340/d; +L_0x1943430/d .functor AND 1, L_0x1942fb0, L_0x19436b0, C4<1>, C4<1>; +L_0x1943430 .delay (20000,20000,20000) L_0x1943430/d; +L_0x1943520/d .functor OR 1, L_0x1943340, L_0x1943430, C4<0>, C4<0>; +L_0x1943520 .delay (20000,20000,20000) L_0x1943520/d; +v0x19161b0_0 .net "S", 0 0, L_0x19436b0; 1 drivers +v0x1916230_0 .alias "in0", 0 0, v0x1916830_0; +v0x19162b0_0 .alias "in1", 0 0, v0x1916e20_0; +v0x1916330_0 .net "nS", 0 0, L_0x19432e0; 1 drivers +v0x19163b0_0 .net "out0", 0 0, L_0x1943340; 1 drivers +v0x1916430_0 .net "out1", 0 0, L_0x1943430; 1 drivers +v0x1916510_0 .alias "outfinal", 0 0, v0x19168e0_0; +S_0x1912ab0 .scope module, "trial1" "AndNand32" 3 280, 3 154, S_0x18a5800; + .timescale -9 -12; +P_0x1912538 .param/l "size" 3 161, +C4<0100>; +v0x19129a0_0 .alias "A", 3 0, v0x1928d50_0; +v0x1915b10_0 .alias "AndNandOut", 3 0, v0x1929fb0_0; +v0x1915b90_0 .alias "B", 3 0, v0x1928e70_0; +v0x1915c40_0 .alias "Command", 2 0, v0x1928f70_0; +L_0x1947400 .part/pv L_0x1947190, 1, 1, 4; +L_0x19474c0 .part v0x1929e30_0, 1, 1; +L_0x1947560 .part v0x192a030_0, 1, 1; +L_0x1947e70 .part/pv L_0x1947c00, 2, 1, 4; +L_0x1947f10 .part v0x1929e30_0, 2, 1; +L_0x1947fb0 .part v0x192a030_0, 2, 1; +L_0x19488e0 .part/pv L_0x1948670, 3, 1, 4; +L_0x193a1c0 .part v0x1929e30_0, 3, 1; +L_0x1948b90 .part v0x192a030_0, 3, 1; +L_0x1949440 .part/pv L_0x19491d0, 0, 1, 4; +L_0x1949540 .part v0x1929e30_0, 0, 1; +L_0x19495e0 .part v0x192a030_0, 0, 1; +S_0x1914fd0 .scope module, "attempt2" "AndNand" 3 165, 3 48, S_0x1912ab0; + .timescale -9 -12; +L_0x1948c80/d .functor NAND 1, L_0x1949540, L_0x19495e0, C4<1>, C4<1>; +L_0x1948c80 .delay (10000,10000,10000) L_0x1948c80/d; +L_0x1948d80/d .functor NOT 1, L_0x1948c80, C4<0>, C4<0>, C4<0>; +L_0x1948d80 .delay (10000,10000,10000) L_0x1948d80/d; +v0x19155f0_0 .net "A", 0 0, L_0x1949540; 1 drivers +v0x19156b0_0 .net "AandB", 0 0, L_0x1948d80; 1 drivers +v0x1915730_0 .net "AnandB", 0 0, L_0x1948c80; 1 drivers +v0x19157e0_0 .net "AndNandOut", 0 0, L_0x19491d0; 1 drivers +v0x19158c0_0 .net "B", 0 0, L_0x19495e0; 1 drivers +v0x1915940_0 .alias "Command", 2 0, v0x1928f70_0; +L_0x19493a0 .part v0x192a0b0_0, 0, 1; +S_0x19150c0 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0x1914fd0; + .timescale -9 -12; +L_0x1948eb0/d .functor NOT 1, L_0x19493a0, C4<0>, C4<0>, C4<0>; +L_0x1948eb0 .delay (10000,10000,10000) L_0x1948eb0/d; +L_0x1948f70/d .functor AND 1, L_0x1948d80, L_0x1948eb0, C4<1>, C4<1>; +L_0x1948f70 .delay (20000,20000,20000) L_0x1948f70/d; +L_0x1949080/d .functor AND 1, L_0x1948c80, L_0x19493a0, C4<1>, C4<1>; +L_0x1949080 .delay (20000,20000,20000) L_0x1949080/d; +L_0x19491d0/d .functor OR 1, L_0x1948f70, L_0x1949080, C4<0>, C4<0>; +L_0x19491d0 .delay (20000,20000,20000) L_0x19491d0/d; +v0x19151b0_0 .net "S", 0 0, L_0x19493a0; 1 drivers +v0x1915230_0 .alias "in0", 0 0, v0x19156b0_0; +v0x19152b0_0 .alias "in1", 0 0, v0x1915730_0; +v0x1915350_0 .net "nS", 0 0, L_0x1948eb0; 1 drivers +v0x19153d0_0 .net "out0", 0 0, L_0x1948f70; 1 drivers +v0x1915470_0 .net "out1", 0 0, L_0x1949080; 1 drivers +v0x1915550_0 .alias "outfinal", 0 0, v0x19157e0_0; +S_0x1914410 .scope generate, "andbits[1]" "andbits[1]" 3 169, 3 169, S_0x1912ab0; + .timescale -9 -12; +P_0x1914508 .param/l "i" 3 169, +C4<01>; +S_0x1914580 .scope module, "attempt" "AndNand" 3 171, 3 48, S_0x1914410; + .timescale -9 -12; +L_0x1946c80/d .functor NAND 1, L_0x19474c0, L_0x1947560, C4<1>, C4<1>; +L_0x1946c80 .delay (10000,10000,10000) L_0x1946c80/d; +L_0x1946d40/d .functor NOT 1, L_0x1946c80, C4<0>, C4<0>, C4<0>; +L_0x1946d40 .delay (10000,10000,10000) L_0x1946d40/d; +v0x1914bc0_0 .net "A", 0 0, L_0x19474c0; 1 drivers +v0x1914c80_0 .net "AandB", 0 0, L_0x1946d40; 1 drivers +v0x1914d00_0 .net "AnandB", 0 0, L_0x1946c80; 1 drivers +v0x1914db0_0 .net "AndNandOut", 0 0, L_0x1947190; 1 drivers +v0x1914e90_0 .net "B", 0 0, L_0x1947560; 1 drivers +v0x1914f10_0 .alias "Command", 2 0, v0x1928f70_0; +L_0x1947360 .part v0x192a0b0_0, 0, 1; +S_0x1914670 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0x1914580; + .timescale -9 -12; +L_0x1946e70/d .functor NOT 1, L_0x1947360, C4<0>, C4<0>, C4<0>; +L_0x1946e70 .delay (10000,10000,10000) L_0x1946e70/d; +L_0x1946f30/d .functor AND 1, L_0x1946d40, L_0x1946e70, C4<1>, C4<1>; +L_0x1946f30 .delay (20000,20000,20000) L_0x1946f30/d; +L_0x1947040/d .functor AND 1, L_0x1946c80, L_0x1947360, C4<1>, C4<1>; +L_0x1947040 .delay (20000,20000,20000) L_0x1947040/d; +L_0x1947190/d .functor OR 1, L_0x1946f30, L_0x1947040, C4<0>, C4<0>; +L_0x1947190 .delay (20000,20000,20000) L_0x1947190/d; +v0x1914760_0 .net "S", 0 0, L_0x1947360; 1 drivers +v0x19147e0_0 .alias "in0", 0 0, v0x1914c80_0; +v0x1914880_0 .alias "in1", 0 0, v0x1914d00_0; +v0x1914920_0 .net "nS", 0 0, L_0x1946e70; 1 drivers +v0x19149a0_0 .net "out0", 0 0, L_0x1946f30; 1 drivers +v0x1914a40_0 .net "out1", 0 0, L_0x1947040; 1 drivers +v0x1914b20_0 .alias "outfinal", 0 0, v0x1914db0_0; +S_0x1913850 .scope generate, "andbits[2]" "andbits[2]" 3 169, 3 169, S_0x1912ab0; + .timescale -9 -12; +P_0x1913948 .param/l "i" 3 169, +C4<010>; +S_0x19139c0 .scope module, "attempt" "AndNand" 3 171, 3 48, S_0x1913850; + .timescale -9 -12; +L_0x1947650/d .functor NAND 1, L_0x1947f10, L_0x1947fb0, C4<1>, C4<1>; +L_0x1947650 .delay (10000,10000,10000) L_0x1947650/d; +L_0x19477b0/d .functor NOT 1, L_0x1947650, C4<0>, C4<0>, C4<0>; +L_0x19477b0 .delay (10000,10000,10000) L_0x19477b0/d; +v0x1914000_0 .net "A", 0 0, L_0x1947f10; 1 drivers +v0x19140c0_0 .net "AandB", 0 0, L_0x19477b0; 1 drivers +v0x1914140_0 .net "AnandB", 0 0, L_0x1947650; 1 drivers +v0x19141f0_0 .net "AndNandOut", 0 0, L_0x1947c00; 1 drivers +v0x19142d0_0 .net "B", 0 0, L_0x1947fb0; 1 drivers +v0x1914350_0 .alias "Command", 2 0, v0x1928f70_0; +L_0x1947dd0 .part v0x192a0b0_0, 0, 1; +S_0x1913ab0 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0x19139c0; + .timescale -9 -12; +L_0x19478e0/d .functor NOT 1, L_0x1947dd0, C4<0>, C4<0>, C4<0>; +L_0x19478e0 .delay (10000,10000,10000) L_0x19478e0/d; +L_0x19479a0/d .functor AND 1, L_0x19477b0, L_0x19478e0, C4<1>, C4<1>; +L_0x19479a0 .delay (20000,20000,20000) L_0x19479a0/d; +L_0x1947ab0/d .functor AND 1, L_0x1947650, L_0x1947dd0, C4<1>, C4<1>; +L_0x1947ab0 .delay (20000,20000,20000) L_0x1947ab0/d; +L_0x1947c00/d .functor OR 1, L_0x19479a0, L_0x1947ab0, C4<0>, C4<0>; +L_0x1947c00 .delay (20000,20000,20000) L_0x1947c00/d; +v0x1913ba0_0 .net "S", 0 0, L_0x1947dd0; 1 drivers +v0x1913c20_0 .alias "in0", 0 0, v0x19140c0_0; +v0x1913cc0_0 .alias "in1", 0 0, v0x1914140_0; +v0x1913d60_0 .net "nS", 0 0, L_0x19478e0; 1 drivers +v0x1913de0_0 .net "out0", 0 0, L_0x19479a0; 1 drivers +v0x1913e80_0 .net "out1", 0 0, L_0x1947ab0; 1 drivers +v0x1913f60_0 .alias "outfinal", 0 0, v0x19141f0_0; +S_0x1912c20 .scope generate, "andbits[3]" "andbits[3]" 3 169, 3 169, S_0x1912ab0; + .timescale -9 -12; +P_0x1912d18 .param/l "i" 3 169, +C4<011>; +S_0x1912db0 .scope module, "attempt" "AndNand" 3 171, 3 48, S_0x1912c20; + .timescale -9 -12; +L_0x19480e0/d .functor NAND 1, L_0x193a1c0, L_0x1948b90, C4<1>, C4<1>; +L_0x19480e0 .delay (10000,10000,10000) L_0x19480e0/d; +L_0x1948220/d .functor NOT 1, L_0x19480e0, C4<0>, C4<0>, C4<0>; +L_0x1948220 .delay (10000,10000,10000) L_0x1948220/d; +v0x1913440_0 .net "A", 0 0, L_0x193a1c0; 1 drivers +v0x1913500_0 .net "AandB", 0 0, L_0x1948220; 1 drivers +v0x1913580_0 .net "AnandB", 0 0, L_0x19480e0; 1 drivers +v0x1913630_0 .net "AndNandOut", 0 0, L_0x1948670; 1 drivers +v0x1913710_0 .net "B", 0 0, L_0x1948b90; 1 drivers +v0x1913790_0 .alias "Command", 2 0, v0x1928f70_0; +L_0x1948840 .part v0x192a0b0_0, 0, 1; +S_0x1912ea0 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0x1912db0; + .timescale -9 -12; +L_0x1948350/d .functor NOT 1, L_0x1948840, C4<0>, C4<0>, C4<0>; +L_0x1948350 .delay (10000,10000,10000) L_0x1948350/d; +L_0x1948410/d .functor AND 1, L_0x1948220, L_0x1948350, C4<1>, C4<1>; +L_0x1948410 .delay (20000,20000,20000) L_0x1948410/d; +L_0x1948520/d .functor AND 1, L_0x19480e0, L_0x1948840, C4<1>, C4<1>; +L_0x1948520 .delay (20000,20000,20000) L_0x1948520/d; +L_0x1948670/d .functor OR 1, L_0x1948410, L_0x1948520, C4<0>, C4<0>; +L_0x1948670 .delay (20000,20000,20000) L_0x1948670/d; +v0x1912f90_0 .net "S", 0 0, L_0x1948840; 1 drivers +v0x1913030_0 .alias "in0", 0 0, v0x1913500_0; +v0x19130d0_0 .alias "in1", 0 0, v0x1913580_0; +v0x1913170_0 .net "nS", 0 0, L_0x1948350; 1 drivers +v0x1913220_0 .net "out0", 0 0, L_0x1948410; 1 drivers +v0x19132c0_0 .net "out1", 0 0, L_0x1948520; 1 drivers +v0x19133a0_0 .alias "outfinal", 0 0, v0x1913630_0; +S_0x190d890 .scope module, "trial2" "OrNorXor32" 3 281, 3 177, S_0x18a5800; + .timescale -9 -12; +P_0x190c9e8 .param/l "size" 3 184, +C4<0100>; +v0x1912820_0 .alias "A", 3 0, v0x1928d50_0; +v0x19128a0_0 .alias "B", 3 0, v0x1928e70_0; +v0x1912920_0 .alias "Command", 2 0, v0x1928f70_0; +v0x1912a30_0 .alias "OrNorXorOut", 3 0, v0x192a1b0_0; +L_0x194a790 .part/pv L_0x194a520, 1, 1, 4; +L_0x194a830 .part v0x1929e30_0, 1, 1; +L_0x194a8d0 .part v0x192a030_0, 1, 1; +L_0x194ba90 .part/pv L_0x194b820, 2, 1, 4; +L_0x194bb30 .part v0x1929e30_0, 2, 1; +L_0x194bbd0 .part v0x192a030_0, 2, 1; +L_0x194cd90 .part/pv L_0x194cb20, 3, 1, 4; +L_0x194ce30 .part v0x1929e30_0, 3, 1; +L_0x194ced0 .part v0x192a030_0, 3, 1; +L_0x194e080 .part/pv L_0x194de10, 0, 1, 4; +L_0x194e180 .part v0x1929e30_0, 0, 1; +L_0x194e220 .part v0x192a030_0, 0, 1; +S_0x1911610 .scope module, "attempt2" "OrNorXor" 3 192, 3 64, S_0x190d890; + .timescale -9 -12; +L_0x194cf70/d .functor NOR 1, L_0x194e180, L_0x194e220, C4<0>, C4<0>; +L_0x194cf70 .delay (10000,10000,10000) L_0x194cf70/d; +L_0x194d070/d .functor NOT 1, L_0x194cf70, C4<0>, C4<0>, C4<0>; +L_0x194d070 .delay (10000,10000,10000) L_0x194d070/d; +L_0x194d1a0/d .functor NAND 1, L_0x194e180, L_0x194e220, C4<1>, C4<1>; +L_0x194d1a0 .delay (10000,10000,10000) L_0x194d1a0/d; +L_0x194d300/d .functor NAND 1, L_0x194d1a0, L_0x194d070, C4<1>, C4<1>; +L_0x194d300 .delay (10000,10000,10000) L_0x194d300/d; +L_0x194d410/d .functor NOT 1, L_0x194d300, C4<0>, C4<0>, C4<0>; +L_0x194d410 .delay (10000,10000,10000) L_0x194d410/d; +v0x1912160_0 .net "A", 0 0, L_0x194e180; 1 drivers +v0x1912200_0 .net "AnandB", 0 0, L_0x194d1a0; 1 drivers +v0x19122a0_0 .net "AnorB", 0 0, L_0x194cf70; 1 drivers +v0x1912320_0 .net "AorB", 0 0, L_0x194d070; 1 drivers +v0x1912400_0 .net "AxorB", 0 0, L_0x194d410; 1 drivers +v0x19124b0_0 .net "B", 0 0, L_0x194e220; 1 drivers +v0x1912570_0 .alias "Command", 2 0, v0x1928f70_0; +v0x19125f0_0 .net "OrNorXorOut", 0 0, L_0x194de10; 1 drivers +v0x1912670_0 .net "XorNor", 0 0, L_0x194d890; 1 drivers +v0x1912740_0 .net "nXor", 0 0, L_0x194d300; 1 drivers +L_0x194da10 .part v0x192a0b0_0, 2, 1; +L_0x194dfe0 .part v0x192a0b0_0, 0, 1; +S_0x1911bf0 .scope module, "mux0" "TwoInMux" 3 83, 3 8, S_0x1911610; + .timescale -9 -12; +L_0x194d570/d .functor NOT 1, L_0x194da10, C4<0>, C4<0>, C4<0>; +L_0x194d570 .delay (10000,10000,10000) L_0x194d570/d; +L_0x194d630/d .functor AND 1, L_0x194d410, L_0x194d570, C4<1>, C4<1>; +L_0x194d630 .delay (20000,20000,20000) L_0x194d630/d; +L_0x194d740/d .functor AND 1, L_0x194cf70, L_0x194da10, C4<1>, C4<1>; +L_0x194d740 .delay (20000,20000,20000) L_0x194d740/d; +L_0x194d890/d .functor OR 1, L_0x194d630, L_0x194d740, C4<0>, C4<0>; +L_0x194d890 .delay (20000,20000,20000) L_0x194d890/d; +v0x1911ce0_0 .net "S", 0 0, L_0x194da10; 1 drivers +v0x1911da0_0 .alias "in0", 0 0, v0x1912400_0; +v0x1911e40_0 .alias "in1", 0 0, v0x19122a0_0; +v0x1911ee0_0 .net "nS", 0 0, L_0x194d570; 1 drivers +v0x1911f60_0 .net "out0", 0 0, L_0x194d630; 1 drivers +v0x1912000_0 .net "out1", 0 0, L_0x194d740; 1 drivers +v0x19120e0_0 .alias "outfinal", 0 0, v0x1912670_0; +S_0x1911700 .scope module, "mux1" "TwoInMux" 3 84, 3 8, S_0x1911610; + .timescale -9 -12; +L_0x194dab0/d .functor NOT 1, L_0x194dfe0, C4<0>, C4<0>, C4<0>; +L_0x194dab0 .delay (10000,10000,10000) L_0x194dab0/d; +L_0x194db70/d .functor AND 1, L_0x194d890, L_0x194dab0, C4<1>, C4<1>; +L_0x194db70 .delay (20000,20000,20000) L_0x194db70/d; +L_0x194dcc0/d .functor AND 1, L_0x194d070, L_0x194dfe0, C4<1>, C4<1>; +L_0x194dcc0 .delay (20000,20000,20000) L_0x194dcc0/d; +L_0x194de10/d .functor OR 1, L_0x194db70, L_0x194dcc0, C4<0>, C4<0>; +L_0x194de10 .delay (20000,20000,20000) L_0x194de10/d; +v0x19117f0_0 .net "S", 0 0, L_0x194dfe0; 1 drivers +v0x1911870_0 .alias "in0", 0 0, v0x1912670_0; +v0x19118f0_0 .alias "in1", 0 0, v0x1912320_0; +v0x1911990_0 .net "nS", 0 0, L_0x194dab0; 1 drivers +v0x1911a10_0 .net "out0", 0 0, L_0x194db70; 1 drivers +v0x1911ab0_0 .net "out1", 0 0, L_0x194dcc0; 1 drivers +v0x1911b50_0 .alias "outfinal", 0 0, v0x19125f0_0; +S_0x1910210 .scope generate, "orbits[1]" "orbits[1]" 3 196, 3 196, S_0x190d890; + .timescale -9 -12; +P_0x190fef8 .param/l "i" 3 196, +C4<01>; +S_0x1910340 .scope module, "attempt" "OrNorXor" 3 198, 3 64, S_0x1910210; + .timescale -9 -12; +L_0x19494e0/d .functor NOR 1, L_0x194a830, L_0x194a8d0, C4<0>, C4<0>; +L_0x19494e0 .delay (10000,10000,10000) L_0x19494e0/d; +L_0x1949780/d .functor NOT 1, L_0x19494e0, C4<0>, C4<0>, C4<0>; +L_0x1949780 .delay (10000,10000,10000) L_0x1949780/d; +L_0x19498b0/d .functor NAND 1, L_0x194a830, L_0x194a8d0, C4<1>, C4<1>; +L_0x19498b0 .delay (10000,10000,10000) L_0x19498b0/d; +L_0x1949a10/d .functor NAND 1, L_0x19498b0, L_0x1949780, C4<1>, C4<1>; +L_0x1949a10 .delay (10000,10000,10000) L_0x1949a10/d; +L_0x1949b20/d .functor NOT 1, L_0x1949a10, C4<0>, C4<0>, C4<0>; +L_0x1949b20 .delay (10000,10000,10000) L_0x1949b20/d; +v0x1910ed0_0 .net "A", 0 0, L_0x194a830; 1 drivers +v0x1910f70_0 .net "AnandB", 0 0, L_0x19498b0; 1 drivers +v0x1911010_0 .net "AnorB", 0 0, L_0x19494e0; 1 drivers +v0x19110c0_0 .net "AorB", 0 0, L_0x1949780; 1 drivers +v0x19111a0_0 .net "AxorB", 0 0, L_0x1949b20; 1 drivers +v0x1911250_0 .net "B", 0 0, L_0x194a8d0; 1 drivers +v0x1911310_0 .alias "Command", 2 0, v0x1928f70_0; +v0x1911390_0 .net "OrNorXorOut", 0 0, L_0x194a520; 1 drivers +v0x1911460_0 .net "XorNor", 0 0, L_0x1949fa0; 1 drivers +v0x1911530_0 .net "nXor", 0 0, L_0x1949a10; 1 drivers +L_0x194a120 .part v0x192a0b0_0, 2, 1; +L_0x194a6f0 .part v0x192a0b0_0, 0, 1; +S_0x1910960 .scope module, "mux0" "TwoInMux" 3 83, 3 8, S_0x1910340; + .timescale -9 -12; +L_0x1949c80/d .functor NOT 1, L_0x194a120, C4<0>, C4<0>, C4<0>; +L_0x1949c80 .delay (10000,10000,10000) L_0x1949c80/d; +L_0x1949d40/d .functor AND 1, L_0x1949b20, L_0x1949c80, C4<1>, C4<1>; +L_0x1949d40 .delay (20000,20000,20000) L_0x1949d40/d; +L_0x1949e50/d .functor AND 1, L_0x19494e0, L_0x194a120, C4<1>, C4<1>; +L_0x1949e50 .delay (20000,20000,20000) L_0x1949e50/d; +L_0x1949fa0/d .functor OR 1, L_0x1949d40, L_0x1949e50, C4<0>, C4<0>; +L_0x1949fa0 .delay (20000,20000,20000) L_0x1949fa0/d; +v0x1910a50_0 .net "S", 0 0, L_0x194a120; 1 drivers +v0x1910b10_0 .alias "in0", 0 0, v0x19111a0_0; +v0x1910bb0_0 .alias "in1", 0 0, v0x1911010_0; +v0x1910c50_0 .net "nS", 0 0, L_0x1949c80; 1 drivers +v0x1910cd0_0 .net "out0", 0 0, L_0x1949d40; 1 drivers +v0x1910d70_0 .net "out1", 0 0, L_0x1949e50; 1 drivers +v0x1910e50_0 .alias "outfinal", 0 0, v0x1911460_0; +S_0x1910430 .scope module, "mux1" "TwoInMux" 3 84, 3 8, S_0x1910340; + .timescale -9 -12; +L_0x194a1c0/d .functor NOT 1, L_0x194a6f0, C4<0>, C4<0>, C4<0>; +L_0x194a1c0 .delay (10000,10000,10000) L_0x194a1c0/d; +L_0x194a280/d .functor AND 1, L_0x1949fa0, L_0x194a1c0, C4<1>, C4<1>; +L_0x194a280 .delay (20000,20000,20000) L_0x194a280/d; +L_0x194a3d0/d .functor AND 1, L_0x1949780, L_0x194a6f0, C4<1>, C4<1>; +L_0x194a3d0 .delay (20000,20000,20000) L_0x194a3d0/d; +L_0x194a520/d .functor OR 1, L_0x194a280, L_0x194a3d0, C4<0>, C4<0>; +L_0x194a520 .delay (20000,20000,20000) L_0x194a520/d; +v0x1910520_0 .net "S", 0 0, L_0x194a6f0; 1 drivers +v0x19105a0_0 .alias "in0", 0 0, v0x1911460_0; +v0x1910620_0 .alias "in1", 0 0, v0x19110c0_0; +v0x19106c0_0 .net "nS", 0 0, L_0x194a1c0; 1 drivers +v0x1910740_0 .net "out0", 0 0, L_0x194a280; 1 drivers +v0x19107e0_0 .net "out1", 0 0, L_0x194a3d0; 1 drivers +v0x19108c0_0 .alias "outfinal", 0 0, v0x1911390_0; +S_0x190edf0 .scope generate, "orbits[2]" "orbits[2]" 3 196, 3 196, S_0x190d890; + .timescale -9 -12; +P_0x190eb68 .param/l "i" 3 196, +C4<010>; +S_0x190ef20 .scope module, "attempt" "OrNorXor" 3 198, 3 64, S_0x190edf0; + .timescale -9 -12; +L_0x194a970/d .functor NOR 1, L_0x194bb30, L_0x194bbd0, C4<0>, C4<0>; +L_0x194a970 .delay (10000,10000,10000) L_0x194a970/d; +L_0x194aa80/d .functor NOT 1, L_0x194a970, C4<0>, C4<0>, C4<0>; +L_0x194aa80 .delay (10000,10000,10000) L_0x194aa80/d; +L_0x194abb0/d .functor NAND 1, L_0x194bb30, L_0x194bbd0, C4<1>, C4<1>; +L_0x194abb0 .delay (10000,10000,10000) L_0x194abb0/d; +L_0x194ad10/d .functor NAND 1, L_0x194abb0, L_0x194aa80, C4<1>, C4<1>; +L_0x194ad10 .delay (10000,10000,10000) L_0x194ad10/d; +L_0x194ae20/d .functor NOT 1, L_0x194ad10, C4<0>, C4<0>, C4<0>; +L_0x194ae20 .delay (10000,10000,10000) L_0x194ae20/d; +v0x190faf0_0 .net "A", 0 0, L_0x194bb30; 1 drivers +v0x190fb90_0 .net "AnandB", 0 0, L_0x194abb0; 1 drivers +v0x190fc30_0 .net "AnorB", 0 0, L_0x194a970; 1 drivers +v0x190fce0_0 .net "AorB", 0 0, L_0x194aa80; 1 drivers +v0x190fdc0_0 .net "AxorB", 0 0, L_0x194ae20; 1 drivers +v0x190fe70_0 .net "B", 0 0, L_0x194bbd0; 1 drivers +v0x190ff30_0 .alias "Command", 2 0, v0x1928f70_0; +v0x190ffb0_0 .net "OrNorXorOut", 0 0, L_0x194b820; 1 drivers +v0x1910060_0 .net "XorNor", 0 0, L_0x194b2a0; 1 drivers +v0x1910130_0 .net "nXor", 0 0, L_0x194ad10; 1 drivers +L_0x194b420 .part v0x192a0b0_0, 2, 1; +L_0x194b9f0 .part v0x192a0b0_0, 0, 1; +S_0x190f580 .scope module, "mux0" "TwoInMux" 3 83, 3 8, S_0x190ef20; + .timescale -9 -12; +L_0x194af80/d .functor NOT 1, L_0x194b420, C4<0>, C4<0>, C4<0>; +L_0x194af80 .delay (10000,10000,10000) L_0x194af80/d; +L_0x194b040/d .functor AND 1, L_0x194ae20, L_0x194af80, C4<1>, C4<1>; +L_0x194b040 .delay (20000,20000,20000) L_0x194b040/d; +L_0x194b150/d .functor AND 1, L_0x194a970, L_0x194b420, C4<1>, C4<1>; +L_0x194b150 .delay (20000,20000,20000) L_0x194b150/d; +L_0x194b2a0/d .functor OR 1, L_0x194b040, L_0x194b150, C4<0>, C4<0>; +L_0x194b2a0 .delay (20000,20000,20000) L_0x194b2a0/d; +v0x190f670_0 .net "S", 0 0, L_0x194b420; 1 drivers +v0x190f730_0 .alias "in0", 0 0, v0x190fdc0_0; +v0x190f7d0_0 .alias "in1", 0 0, v0x190fc30_0; +v0x190f870_0 .net "nS", 0 0, L_0x194af80; 1 drivers +v0x190f8f0_0 .net "out0", 0 0, L_0x194b040; 1 drivers +v0x190f990_0 .net "out1", 0 0, L_0x194b150; 1 drivers +v0x190fa70_0 .alias "outfinal", 0 0, v0x1910060_0; +S_0x190f010 .scope module, "mux1" "TwoInMux" 3 84, 3 8, S_0x190ef20; + .timescale -9 -12; +L_0x194b4c0/d .functor NOT 1, L_0x194b9f0, C4<0>, C4<0>, C4<0>; +L_0x194b4c0 .delay (10000,10000,10000) L_0x194b4c0/d; +L_0x194b580/d .functor AND 1, L_0x194b2a0, L_0x194b4c0, C4<1>, C4<1>; +L_0x194b580 .delay (20000,20000,20000) L_0x194b580/d; +L_0x194b6d0/d .functor AND 1, L_0x194aa80, L_0x194b9f0, C4<1>, C4<1>; +L_0x194b6d0 .delay (20000,20000,20000) L_0x194b6d0/d; +L_0x194b820/d .functor OR 1, L_0x194b580, L_0x194b6d0, C4<0>, C4<0>; +L_0x194b820 .delay (20000,20000,20000) L_0x194b820/d; +v0x190f100_0 .net "S", 0 0, L_0x194b9f0; 1 drivers +v0x190f1a0_0 .alias "in0", 0 0, v0x1910060_0; +v0x190f240_0 .alias "in1", 0 0, v0x190fce0_0; +v0x190f2e0_0 .net "nS", 0 0, L_0x194b4c0; 1 drivers +v0x190f360_0 .net "out0", 0 0, L_0x194b580; 1 drivers +v0x190f400_0 .net "out1", 0 0, L_0x194b6d0; 1 drivers +v0x190f4e0_0 .alias "outfinal", 0 0, v0x190ffb0_0; +S_0x190da00 .scope generate, "orbits[3]" "orbits[3]" 3 196, 3 196, S_0x190d890; + .timescale -9 -12; +P_0x190daf8 .param/l "i" 3 196, +C4<011>; +S_0x190db90 .scope module, "attempt" "OrNorXor" 3 198, 3 64, S_0x190da00; + .timescale -9 -12; +L_0x194bcb0/d .functor NOR 1, L_0x194ce30, L_0x194ced0, C4<0>, C4<0>; +L_0x194bcb0 .delay (10000,10000,10000) L_0x194bcb0/d; +L_0x194bda0/d .functor NOT 1, L_0x194bcb0, C4<0>, C4<0>, C4<0>; +L_0x194bda0 .delay (10000,10000,10000) L_0x194bda0/d; +L_0x194beb0/d .functor NAND 1, L_0x194ce30, L_0x194ced0, C4<1>, C4<1>; +L_0x194beb0 .delay (10000,10000,10000) L_0x194beb0/d; +L_0x194c010/d .functor NAND 1, L_0x194beb0, L_0x194bda0, C4<1>, C4<1>; +L_0x194c010 .delay (10000,10000,10000) L_0x194c010/d; +L_0x194c120/d .functor NOT 1, L_0x194c010, C4<0>, C4<0>, C4<0>; +L_0x194c120 .delay (10000,10000,10000) L_0x194c120/d; +v0x190e760_0 .net "A", 0 0, L_0x194ce30; 1 drivers +v0x190e800_0 .net "AnandB", 0 0, L_0x194beb0; 1 drivers +v0x190e8a0_0 .net "AnorB", 0 0, L_0x194bcb0; 1 drivers +v0x190e950_0 .net "AorB", 0 0, L_0x194bda0; 1 drivers +v0x190ea30_0 .net "AxorB", 0 0, L_0x194c120; 1 drivers +v0x190eae0_0 .net "B", 0 0, L_0x194ced0; 1 drivers +v0x190eba0_0 .alias "Command", 2 0, v0x1928f70_0; +v0x190ec20_0 .net "OrNorXorOut", 0 0, L_0x194cb20; 1 drivers +v0x190eca0_0 .net "XorNor", 0 0, L_0x194c5a0; 1 drivers +v0x190ed70_0 .net "nXor", 0 0, L_0x194c010; 1 drivers +L_0x194c720 .part v0x192a0b0_0, 2, 1; +L_0x194ccf0 .part v0x192a0b0_0, 0, 1; +S_0x190e1f0 .scope module, "mux0" "TwoInMux" 3 83, 3 8, S_0x190db90; + .timescale -9 -12; +L_0x194c280/d .functor NOT 1, L_0x194c720, C4<0>, C4<0>, C4<0>; +L_0x194c280 .delay (10000,10000,10000) L_0x194c280/d; +L_0x194c340/d .functor AND 1, L_0x194c120, L_0x194c280, C4<1>, C4<1>; +L_0x194c340 .delay (20000,20000,20000) L_0x194c340/d; +L_0x194c450/d .functor AND 1, L_0x194bcb0, L_0x194c720, C4<1>, C4<1>; +L_0x194c450 .delay (20000,20000,20000) L_0x194c450/d; +L_0x194c5a0/d .functor OR 1, L_0x194c340, L_0x194c450, C4<0>, C4<0>; +L_0x194c5a0 .delay (20000,20000,20000) L_0x194c5a0/d; +v0x190e2e0_0 .net "S", 0 0, L_0x194c720; 1 drivers +v0x190e3a0_0 .alias "in0", 0 0, v0x190ea30_0; +v0x190e440_0 .alias "in1", 0 0, v0x190e8a0_0; +v0x190e4e0_0 .net "nS", 0 0, L_0x194c280; 1 drivers +v0x190e560_0 .net "out0", 0 0, L_0x194c340; 1 drivers +v0x190e600_0 .net "out1", 0 0, L_0x194c450; 1 drivers +v0x190e6e0_0 .alias "outfinal", 0 0, v0x190eca0_0; +S_0x190dc80 .scope module, "mux1" "TwoInMux" 3 84, 3 8, S_0x190db90; + .timescale -9 -12; +L_0x194c7c0/d .functor NOT 1, L_0x194ccf0, C4<0>, C4<0>, C4<0>; +L_0x194c7c0 .delay (10000,10000,10000) L_0x194c7c0/d; +L_0x194c880/d .functor AND 1, L_0x194c5a0, L_0x194c7c0, C4<1>, C4<1>; +L_0x194c880 .delay (20000,20000,20000) L_0x194c880/d; +L_0x194c9d0/d .functor AND 1, L_0x194bda0, L_0x194ccf0, C4<1>, C4<1>; +L_0x194c9d0 .delay (20000,20000,20000) L_0x194c9d0/d; +L_0x194cb20/d .functor OR 1, L_0x194c880, L_0x194c9d0, C4<0>, C4<0>; +L_0x194cb20 .delay (20000,20000,20000) L_0x194cb20/d; +v0x190dd70_0 .net "S", 0 0, L_0x194ccf0; 1 drivers +v0x190de10_0 .alias "in0", 0 0, v0x190eca0_0; +v0x190deb0_0 .alias "in1", 0 0, v0x190e950_0; +v0x190df50_0 .net "nS", 0 0, L_0x194c7c0; 1 drivers +v0x190dfd0_0 .net "out0", 0 0, L_0x194c880; 1 drivers +v0x190e070_0 .net "out1", 0 0, L_0x194c9d0; 1 drivers +v0x190e150_0 .alias "outfinal", 0 0, v0x190ec20_0; +S_0x190cf10 .scope module, "ZeroMux0case" "FourInMux" 3 283, 3 24, S_0x18a5800; + .timescale -9 -12; +L_0x194e120/d .functor NOT 1, L_0x1940830, C4<0>, C4<0>, C4<0>; +L_0x194e120 .delay (10000,10000,10000) L_0x194e120/d; +L_0x194e370/d .functor NOT 1, L_0x1940960, C4<0>, C4<0>, C4<0>; +L_0x194e370 .delay (10000,10000,10000) L_0x194e370/d; +L_0x194e430/d .functor NAND 1, L_0x194e120, L_0x194e370, L_0x194ea60, C4<1>; +L_0x194e430 .delay (10000,10000,10000) L_0x194e430/d; +L_0x194e520/d .functor NAND 1, L_0x1940830, L_0x194e370, L_0x194eb00, C4<1>; +L_0x194e520 .delay (10000,10000,10000) L_0x194e520/d; +L_0x194e610/d .functor NAND 1, L_0x194e120, L_0x1940960, L_0x194eba0, C4<1>; +L_0x194e610 .delay (10000,10000,10000) L_0x194e610/d; +L_0x194e700/d .functor NAND 1, L_0x1940830, L_0x1940960, L_0x194ef80, C4<1>; +L_0x194e700 .delay (10000,10000,10000) L_0x194e700/d; +L_0x194e7e0/d .functor NAND 1, L_0x194e430, L_0x194e520, L_0x194e610, L_0x194e700; +L_0x194e7e0 .delay (10000,10000,10000) L_0x194e7e0/d; +v0x190d000_0 .net "S0", 0 0, L_0x1940830; 1 drivers +v0x190d0c0_0 .net "S1", 0 0, L_0x1940960; 1 drivers +v0x190d160_0 .net "in0", 0 0, L_0x194ea60; 1 drivers +v0x190d200_0 .net "in1", 0 0, L_0x194eb00; 1 drivers +v0x190d280_0 .net "in2", 0 0, L_0x194eba0; 1 drivers +v0x190d320_0 .net "in3", 0 0, L_0x194ef80; 1 drivers +v0x190d3c0_0 .net "nS0", 0 0, L_0x194e120; 1 drivers +v0x190d460_0 .net "nS1", 0 0, L_0x194e370; 1 drivers +v0x190d500_0 .net "out", 0 0, L_0x194e7e0; 1 drivers +v0x190d5a0_0 .net "out0", 0 0, L_0x194e430; 1 drivers +v0x190d640_0 .net "out1", 0 0, L_0x194e520; 1 drivers +v0x190d6e0_0 .net "out2", 0 0, L_0x194e610; 1 drivers +v0x190d7f0_0 .net "out3", 0 0, L_0x194e700; 1 drivers +S_0x190c550 .scope module, "OneMux0case" "FourInMux" 3 284, 3 24, S_0x18a5800; + .timescale -9 -12; +L_0x194ed00/d .functor NOT 1, L_0x194f890, C4<0>, C4<0>, C4<0>; +L_0x194ed00 .delay (10000,10000,10000) L_0x194ed00/d; +L_0x194edf0/d .functor NOT 1, L_0x194f070, C4<0>, C4<0>, C4<0>; +L_0x194edf0 .delay (10000,10000,10000) L_0x194edf0/d; +L_0x194ee90/d .functor NAND 1, L_0x194ed00, L_0x194edf0, L_0x194f1a0, C4<1>; +L_0x194ee90 .delay (10000,10000,10000) L_0x194ee90/d; +L_0x194f350/d .functor NAND 1, L_0x194f890, L_0x194edf0, L_0x194fc20, C4<1>; +L_0x194f350 .delay (10000,10000,10000) L_0x194f350/d; +L_0x194f440/d .functor NAND 1, L_0x194ed00, L_0x194f070, L_0x194fcc0, C4<1>; +L_0x194f440 .delay (10000,10000,10000) L_0x194f440/d; +L_0x194f530/d .functor NAND 1, L_0x194f890, L_0x194f070, L_0x194f9c0, C4<1>; +L_0x194f530 .delay (10000,10000,10000) L_0x194f530/d; +L_0x194f610/d .functor NAND 1, L_0x194ee90, L_0x194f350, L_0x194f440, L_0x194f530; +L_0x194f610 .delay (10000,10000,10000) L_0x194f610/d; +v0x190c640_0 .net "S0", 0 0, L_0x194f890; 1 drivers +v0x190c700_0 .net "S1", 0 0, L_0x194f070; 1 drivers +v0x190c7a0_0 .net "in0", 0 0, L_0x194f1a0; 1 drivers +v0x190c840_0 .net "in1", 0 0, L_0x194fc20; 1 drivers +v0x190c8c0_0 .net "in2", 0 0, L_0x194fcc0; 1 drivers +v0x190c960_0 .net "in3", 0 0, L_0x194f9c0; 1 drivers +v0x190ca40_0 .net "nS0", 0 0, L_0x194ed00; 1 drivers +v0x190cae0_0 .net "nS1", 0 0, L_0x194edf0; 1 drivers +v0x190cb80_0 .net "out", 0 0, L_0x194f610; 1 drivers +v0x190cc20_0 .net "out0", 0 0, L_0x194ee90; 1 drivers +v0x190ccc0_0 .net "out1", 0 0, L_0x194f350; 1 drivers +v0x190cd60_0 .net "out2", 0 0, L_0x194f440; 1 drivers +v0x190ce70_0 .net "out3", 0 0, L_0x194f530; 1 drivers +S_0x190c000 .scope module, "TwoMux0case" "TwoInMux" 3 285, 3 8, S_0x18a5800; + .timescale -9 -12; +L_0x194fab0/d .functor NOT 1, L_0x194fd60, C4<0>, C4<0>, C4<0>; +L_0x194fab0 .delay (10000,10000,10000) L_0x194fab0/d; +L_0x194fba0/d .functor AND 1, L_0x194fe00, L_0x194fab0, C4<1>, C4<1>; +L_0x194fba0 .delay (20000,20000,20000) L_0x194fba0/d; +L_0x1950060/d .functor AND 1, L_0x194fef0, L_0x194fd60, C4<1>, C4<1>; +L_0x1950060 .delay (20000,20000,20000) L_0x1950060/d; +L_0x1950150/d .functor OR 1, L_0x194fba0, L_0x1950060, C4<0>, C4<0>; +L_0x1950150 .delay (20000,20000,20000) L_0x1950150/d; +v0x190c0f0_0 .net "S", 0 0, L_0x194fd60; 1 drivers +v0x190c1b0_0 .net "in0", 0 0, L_0x194fe00; 1 drivers +v0x190c250_0 .net "in1", 0 0, L_0x194fef0; 1 drivers +v0x190c2f0_0 .net "nS", 0 0, L_0x194fab0; 1 drivers +v0x190c370_0 .net "out0", 0 0, L_0x194fba0; 1 drivers +v0x190c410_0 .net "out1", 0 0, L_0x1950060; 1 drivers +v0x190c4b0_0 .net "outfinal", 0 0, L_0x1950150; 1 drivers +S_0x190a480 .scope generate, "muxbits[1]" "muxbits[1]" 3 290, 3 290, S_0x18a5800; + .timescale -9 -12; +P_0x1909478 .param/l "i" 3 290, +C4<01>; +L_0x193adc0/d .functor OR 1, L_0x193aec0, L_0x193ac80, C4<0>, C4<0>; +L_0x193adc0 .delay (20000,20000,20000) L_0x193adc0/d; +v0x190bea0_0 .net *"_s15", 0 0, L_0x193aec0; 1 drivers +v0x190bf60_0 .net *"_s16", 0 0, L_0x193ac80; 1 drivers +S_0x190b520 .scope module, "ZeroMux" "FourInMux" 3 292, 3 24, S_0x190a480; + .timescale -9 -12; +L_0x1938400/d .functor NOT 1, L_0x1938ea0, C4<0>, C4<0>, C4<0>; +L_0x1938400 .delay (10000,10000,10000) L_0x1938400/d; +L_0x1938650/d .functor NOT 1, L_0x1938fd0, C4<0>, C4<0>, C4<0>; +L_0x1938650 .delay (10000,10000,10000) L_0x1938650/d; +L_0x19386f0/d .functor NAND 1, L_0x1938400, L_0x1938650, L_0x1939100, C4<1>; +L_0x19386f0 .delay (10000,10000,10000) L_0x19386f0/d; +L_0x19387e0/d .functor NAND 1, L_0x1938ea0, L_0x1938650, L_0x19391a0, C4<1>; +L_0x19387e0 .delay (10000,10000,10000) L_0x19387e0/d; +L_0x1938930/d .functor NAND 1, L_0x1938400, L_0x1938fd0, L_0x1939240, C4<1>; +L_0x1938930 .delay (10000,10000,10000) L_0x1938930/d; +L_0x1938a80/d .functor NAND 1, L_0x1938ea0, L_0x1938fd0, L_0x1939440, C4<1>; +L_0x1938a80 .delay (10000,10000,10000) L_0x1938a80/d; +L_0x1938bf0/d .functor NAND 1, L_0x19386f0, L_0x19387e0, L_0x1938930, L_0x1938a80; +L_0x1938bf0 .delay (10000,10000,10000) L_0x1938bf0/d; +v0x190b610_0 .net "S0", 0 0, L_0x1938ea0; 1 drivers +v0x190b6d0_0 .net "S1", 0 0, L_0x1938fd0; 1 drivers +v0x190b770_0 .net "in0", 0 0, L_0x1939100; 1 drivers +v0x190b810_0 .net "in1", 0 0, L_0x19391a0; 1 drivers +v0x190b890_0 .net "in2", 0 0, L_0x1939240; 1 drivers +v0x190b930_0 .net "in3", 0 0, L_0x1939440; 1 drivers +v0x190b9d0_0 .net "nS0", 0 0, L_0x1938400; 1 drivers +v0x190ba70_0 .net "nS1", 0 0, L_0x1938650; 1 drivers +v0x190bb10_0 .net "out", 0 0, L_0x1938bf0; 1 drivers +v0x190bbb0_0 .net "out0", 0 0, L_0x19386f0; 1 drivers +v0x190bc50_0 .net "out1", 0 0, L_0x19387e0; 1 drivers +v0x190bcf0_0 .net "out2", 0 0, L_0x1938930; 1 drivers +v0x190be00_0 .net "out3", 0 0, L_0x1938a80; 1 drivers +S_0x190ab60 .scope module, "OneMux" "FourInMux" 3 293, 3 24, S_0x190a480; + .timescale -9 -12; +L_0x19394e0/d .functor NOT 1, L_0x1939e60, C4<0>, C4<0>, C4<0>; +L_0x19394e0 .delay (10000,10000,10000) L_0x19394e0/d; +L_0x19395d0/d .functor NOT 1, L_0x1939f90, C4<0>, C4<0>, C4<0>; +L_0x19395d0 .delay (10000,10000,10000) L_0x19395d0/d; +L_0x1939670/d .functor NAND 1, L_0x19394e0, L_0x19395d0, L_0x193a120, C4<1>; +L_0x1939670 .delay (10000,10000,10000) L_0x1939670/d; +L_0x19397b0/d .functor NAND 1, L_0x1939e60, L_0x19395d0, L_0x193a2d0, C4<1>; +L_0x19397b0 .delay (10000,10000,10000) L_0x19397b0/d; +L_0x19398a0/d .functor NAND 1, L_0x19394e0, L_0x1939f90, L_0x193a370, C4<1>; +L_0x19398a0 .delay (10000,10000,10000) L_0x19398a0/d; +L_0x19399f0/d .functor NAND 1, L_0x1939e60, L_0x1939f90, L_0x193a410, C4<1>; +L_0x19399f0 .delay (10000,10000,10000) L_0x19399f0/d; +L_0x1939b60/d .functor NAND 1, L_0x1939670, L_0x19397b0, L_0x19398a0, L_0x19399f0; +L_0x1939b60 .delay (10000,10000,10000) L_0x1939b60/d; +v0x190ac50_0 .net "S0", 0 0, L_0x1939e60; 1 drivers +v0x190ad10_0 .net "S1", 0 0, L_0x1939f90; 1 drivers +v0x190adb0_0 .net "in0", 0 0, L_0x193a120; 1 drivers +v0x190ae50_0 .net "in1", 0 0, L_0x193a2d0; 1 drivers +v0x190aed0_0 .net "in2", 0 0, L_0x193a370; 1 drivers +v0x190af70_0 .net "in3", 0 0, L_0x193a410; 1 drivers +v0x190b050_0 .net "nS0", 0 0, L_0x19394e0; 1 drivers +v0x190b0f0_0 .net "nS1", 0 0, L_0x19395d0; 1 drivers +v0x190b190_0 .net "out", 0 0, L_0x1939b60; 1 drivers +v0x190b230_0 .net "out0", 0 0, L_0x1939670; 1 drivers +v0x190b2d0_0 .net "out1", 0 0, L_0x19397b0; 1 drivers +v0x190b370_0 .net "out2", 0 0, L_0x19398a0; 1 drivers +v0x190b480_0 .net "out3", 0 0, L_0x19399f0; 1 drivers +S_0x190a5f0 .scope module, "TwoMux" "TwoInMux" 3 294, 3 8, S_0x190a480; + .timescale -9 -12; +L_0x193a0c0/d .functor NOT 1, L_0x193a960, C4<0>, C4<0>, C4<0>; +L_0x193a0c0 .delay (10000,10000,10000) L_0x193a0c0/d; +L_0x193a550/d .functor AND 1, L_0x193aa00, L_0x193a0c0, C4<1>, C4<1>; +L_0x193a550 .delay (20000,20000,20000) L_0x193a550/d; +L_0x193a640/d .functor AND 1, L_0x193ab40, L_0x193a960, C4<1>, C4<1>; +L_0x193a640 .delay (20000,20000,20000) L_0x193a640/d; +L_0x193a730/d .functor OR 1, L_0x193a550, L_0x193a640, C4<0>, C4<0>; +L_0x193a730 .delay (20000,20000,20000) L_0x193a730/d; +v0x190a6e0_0 .net "S", 0 0, L_0x193a960; 1 drivers +v0x190a780_0 .net "in0", 0 0, L_0x193aa00; 1 drivers +v0x190a820_0 .net "in1", 0 0, L_0x193ab40; 1 drivers +v0x190a8c0_0 .net "nS", 0 0, L_0x193a0c0; 1 drivers +v0x190a940_0 .net "out0", 0 0, L_0x193a550; 1 drivers +v0x190a9e0_0 .net "out1", 0 0, L_0x193a640; 1 drivers +v0x190aac0_0 .net "outfinal", 0 0, L_0x193a730; 1 drivers +S_0x1908900 .scope generate, "muxbits[2]" "muxbits[2]" 3 290, 3 290, S_0x18a5800; + .timescale -9 -12; +P_0x1907848 .param/l "i" 3 290, +C4<010>; +L_0x193d1d0/d .functor OR 1, L_0x193d9d0, L_0x193dd50, C4<0>, C4<0>; +L_0x193d1d0 .delay (20000,20000,20000) L_0x193d1d0/d; +v0x190a320_0 .net *"_s15", 0 0, L_0x193d9d0; 1 drivers +v0x190a3e0_0 .net *"_s16", 0 0, L_0x193dd50; 1 drivers +S_0x19099a0 .scope module, "ZeroMux" "FourInMux" 3 292, 3 24, S_0x1908900; + .timescale -9 -12; +L_0x193b060/d .functor NOT 1, L_0x193af60, C4<0>, C4<0>, C4<0>; +L_0x193b060 .delay (10000,10000,10000) L_0x193b060/d; +L_0x193b150/d .functor NOT 1, L_0x193ba50, C4<0>, C4<0>, C4<0>; +L_0x193b150 .delay (10000,10000,10000) L_0x193b150/d; +L_0x193b1f0/d .functor NAND 1, L_0x193b060, L_0x193b150, L_0x193b900, C4<1>; +L_0x193b1f0 .delay (10000,10000,10000) L_0x193b1f0/d; +L_0x193b330/d .functor NAND 1, L_0x193af60, L_0x193b150, L_0x193bc50, C4<1>; +L_0x193b330 .delay (10000,10000,10000) L_0x193b330/d; +L_0x193b420/d .functor NAND 1, L_0x193b060, L_0x193ba50, L_0x193bb80, C4<1>; +L_0x193b420 .delay (10000,10000,10000) L_0x193b420/d; +L_0x193b510/d .functor NAND 1, L_0x193af60, L_0x193ba50, L_0x193be20, C4<1>; +L_0x193b510 .delay (10000,10000,10000) L_0x193b510/d; +L_0x193b650/d .functor NAND 1, L_0x193b1f0, L_0x193b330, L_0x193b420, L_0x193b510; +L_0x193b650 .delay (10000,10000,10000) L_0x193b650/d; +v0x1909a90_0 .net "S0", 0 0, L_0x193af60; 1 drivers +v0x1909b50_0 .net "S1", 0 0, L_0x193ba50; 1 drivers +v0x1909bf0_0 .net "in0", 0 0, L_0x193b900; 1 drivers +v0x1909c90_0 .net "in1", 0 0, L_0x193bc50; 1 drivers +v0x1909d10_0 .net "in2", 0 0, L_0x193bb80; 1 drivers +v0x1909db0_0 .net "in3", 0 0, L_0x193be20; 1 drivers +v0x1909e50_0 .net "nS0", 0 0, L_0x193b060; 1 drivers +v0x1909ef0_0 .net "nS1", 0 0, L_0x193b150; 1 drivers +v0x1909f90_0 .net "out", 0 0, L_0x193b650; 1 drivers +v0x190a030_0 .net "out0", 0 0, L_0x193b1f0; 1 drivers +v0x190a0d0_0 .net "out1", 0 0, L_0x193b330; 1 drivers +v0x190a170_0 .net "out2", 0 0, L_0x193b420; 1 drivers +v0x190a280_0 .net "out3", 0 0, L_0x193b510; 1 drivers +S_0x1908fe0 .scope module, "OneMux" "FourInMux" 3 293, 3 24, S_0x1908900; + .timescale -9 -12; +L_0x193bcf0/d .functor NOT 1, L_0x193c7f0, C4<0>, C4<0>, C4<0>; +L_0x193bcf0 .delay (10000,10000,10000) L_0x193bcf0/d; +L_0x193c050/d .functor NOT 1, L_0x193bf10, C4<0>, C4<0>, C4<0>; +L_0x193c050 .delay (10000,10000,10000) L_0x193c050/d; +L_0x193c0b0/d .functor NAND 1, L_0x193bcf0, L_0x193c050, L_0x192ad80, C4<1>; +L_0x193c0b0 .delay (10000,10000,10000) L_0x193c0b0/d; +L_0x193c1f0/d .functor NAND 1, L_0x193c7f0, L_0x193c050, L_0x192af30, C4<1>; +L_0x193c1f0 .delay (10000,10000,10000) L_0x193c1f0/d; +L_0x193c2e0/d .functor NAND 1, L_0x193bcf0, L_0x193bf10, L_0x192abf0, C4<1>; +L_0x193c2e0 .delay (10000,10000,10000) L_0x193c2e0/d; +L_0x193c3d0/d .functor NAND 1, L_0x193c7f0, L_0x193bf10, L_0x192ae20, C4<1>; +L_0x193c3d0 .delay (10000,10000,10000) L_0x193c3d0/d; +L_0x193c540/d .functor NAND 1, L_0x193c0b0, L_0x193c1f0, L_0x193c2e0, L_0x193c3d0; +L_0x193c540 .delay (10000,10000,10000) L_0x193c540/d; +v0x19090d0_0 .net "S0", 0 0, L_0x193c7f0; 1 drivers +v0x1909190_0 .net "S1", 0 0, L_0x193bf10; 1 drivers +v0x1909230_0 .net "in0", 0 0, L_0x192ad80; 1 drivers +v0x19092d0_0 .net "in1", 0 0, L_0x192af30; 1 drivers +v0x1909350_0 .net "in2", 0 0, L_0x192abf0; 1 drivers +v0x19093f0_0 .net "in3", 0 0, L_0x192ae20; 1 drivers +v0x19094d0_0 .net "nS0", 0 0, L_0x193bcf0; 1 drivers +v0x1909570_0 .net "nS1", 0 0, L_0x193c050; 1 drivers +v0x1909610_0 .net "out", 0 0, L_0x193c540; 1 drivers +v0x19096b0_0 .net "out0", 0 0, L_0x193c0b0; 1 drivers +v0x1909750_0 .net "out1", 0 0, L_0x193c1f0; 1 drivers +v0x19097f0_0 .net "out2", 0 0, L_0x193c2e0; 1 drivers +v0x1909900_0 .net "out3", 0 0, L_0x193c3d0; 1 drivers +S_0x1908a70 .scope module, "TwoMux" "TwoInMux" 3 294, 3 8, S_0x1908900; + .timescale -9 -12; +L_0x192aec0/d .functor NOT 1, L_0x193d130, C4<0>, C4<0>, C4<0>; +L_0x192aec0 .delay (10000,10000,10000) L_0x192aec0/d; +L_0x193d2e0/d .functor AND 1, L_0x193d860, L_0x192aec0, C4<1>, C4<1>; +L_0x193d2e0 .delay (20000,20000,20000) L_0x193d2e0/d; +L_0x193d3d0/d .functor AND 1, L_0x193d730, L_0x193d130, C4<1>, C4<1>; +L_0x193d3d0 .delay (20000,20000,20000) L_0x193d3d0/d; +L_0x193d4c0/d .functor OR 1, L_0x193d2e0, L_0x193d3d0, C4<0>, C4<0>; +L_0x193d4c0 .delay (20000,20000,20000) L_0x193d4c0/d; +v0x1908b60_0 .net "S", 0 0, L_0x193d130; 1 drivers +v0x1908c00_0 .net "in0", 0 0, L_0x193d860; 1 drivers +v0x1908ca0_0 .net "in1", 0 0, L_0x193d730; 1 drivers +v0x1908d40_0 .net "nS", 0 0, L_0x192aec0; 1 drivers +v0x1908dc0_0 .net "out0", 0 0, L_0x193d2e0; 1 drivers +v0x1908e60_0 .net "out1", 0 0, L_0x193d3d0; 1 drivers +v0x1908f40_0 .net "outfinal", 0 0, L_0x193d4c0; 1 drivers +S_0x1883e50 .scope generate, "muxbits[3]" "muxbits[3]" 3 290, 3 290, S_0x18a5800; + .timescale -9 -12; +P_0x187d708 .param/l "i" 3 290, +C4<011>; +L_0x1940410/d .functor OR 1, L_0x1940790, L_0x19405a0, C4<0>, C4<0>; +L_0x1940410 .delay (20000,20000,20000) L_0x1940410/d; +v0x19087a0_0 .net *"_s15", 0 0, L_0x1940790; 1 drivers +v0x1908860_0 .net *"_s16", 0 0, L_0x19405a0; 1 drivers +S_0x1907e20 .scope module, "ZeroMux" "FourInMux" 3 292, 3 24, S_0x1883e50; + .timescale -9 -12; +L_0x193dc00/d .functor NOT 1, L_0x193e700, C4<0>, C4<0>, C4<0>; +L_0x193dc00 .delay (10000,10000,10000) L_0x193dc00/d; +L_0x193dcf0/d .functor NOT 1, L_0x193ddf0, C4<0>, C4<0>, C4<0>; +L_0x193dcf0 .delay (10000,10000,10000) L_0x193dcf0/d; +L_0x193df90/d .functor NAND 1, L_0x193dc00, L_0x193dcf0, L_0x193e9a0, C4<1>; +L_0x193df90 .delay (10000,10000,10000) L_0x193df90/d; +L_0x193e0d0/d .functor NAND 1, L_0x193e700, L_0x193dcf0, L_0x1930820, C4<1>; +L_0x193e0d0 .delay (10000,10000,10000) L_0x193e0d0/d; +L_0x193e1c0/d .functor NAND 1, L_0x193dc00, L_0x193ddf0, L_0x193e830, C4<1>; +L_0x193e1c0 .delay (10000,10000,10000) L_0x193e1c0/d; +L_0x193e2e0/d .functor NAND 1, L_0x193e700, L_0x193ddf0, L_0x193ede0, C4<1>; +L_0x193e2e0 .delay (10000,10000,10000) L_0x193e2e0/d; +L_0x193e450/d .functor NAND 1, L_0x193df90, L_0x193e0d0, L_0x193e1c0, L_0x193e2e0; +L_0x193e450 .delay (10000,10000,10000) L_0x193e450/d; +v0x1907f10_0 .net "S0", 0 0, L_0x193e700; 1 drivers +v0x1907fd0_0 .net "S1", 0 0, L_0x193ddf0; 1 drivers +v0x1908070_0 .net "in0", 0 0, L_0x193e9a0; 1 drivers +v0x1908110_0 .net "in1", 0 0, L_0x1930820; 1 drivers +v0x1908190_0 .net "in2", 0 0, L_0x193e830; 1 drivers +v0x1908230_0 .net "in3", 0 0, L_0x193ede0; 1 drivers +v0x19082d0_0 .net "nS0", 0 0, L_0x193dc00; 1 drivers +v0x1908370_0 .net "nS1", 0 0, L_0x193dcf0; 1 drivers +v0x1908410_0 .net "out", 0 0, L_0x193e450; 1 drivers +v0x19084b0_0 .net "out0", 0 0, L_0x193df90; 1 drivers +v0x1908550_0 .net "out1", 0 0, L_0x193e0d0; 1 drivers +v0x19085f0_0 .net "out2", 0 0, L_0x193e1c0; 1 drivers +v0x1908700_0 .net "out3", 0 0, L_0x193e2e0; 1 drivers +S_0x19073b0 .scope module, "OneMux" "FourInMux" 3 293, 3 24, S_0x1883e50; + .timescale -9 -12; +L_0x193e920/d .functor NOT 1, L_0x193ec50, C4<0>, C4<0>, C4<0>; +L_0x193e920 .delay (10000,10000,10000) L_0x193e920/d; +L_0x193ef10/d .functor NOT 1, L_0x193f890, C4<0>, C4<0>, C4<0>; +L_0x193ef10 .delay (10000,10000,10000) L_0x193ef10/d; +L_0x193efb0/d .functor NAND 1, L_0x193e920, L_0x193ef10, L_0x193f6f0, C4<1>; +L_0x193efb0 .delay (10000,10000,10000) L_0x193efb0/d; +L_0x193f0f0/d .functor NAND 1, L_0x193ec50, L_0x193ef10, L_0x193f790, C4<1>; +L_0x193f0f0 .delay (10000,10000,10000) L_0x193f0f0/d; +L_0x193f1e0/d .functor NAND 1, L_0x193e920, L_0x193f890, L_0x193fb80, C4<1>; +L_0x193f1e0 .delay (10000,10000,10000) L_0x193f1e0/d; +L_0x193f2d0/d .functor NAND 1, L_0x193ec50, L_0x193f890, L_0x193fc20, C4<1>; +L_0x193f2d0 .delay (10000,10000,10000) L_0x193f2d0/d; +L_0x193f440/d .functor NAND 1, L_0x193efb0, L_0x193f0f0, L_0x193f1e0, L_0x193f2d0; +L_0x193f440 .delay (10000,10000,10000) L_0x193f440/d; +v0x19074a0_0 .net "S0", 0 0, L_0x193ec50; 1 drivers +v0x1907560_0 .net "S1", 0 0, L_0x193f890; 1 drivers +v0x1907600_0 .net "in0", 0 0, L_0x193f6f0; 1 drivers +v0x19076a0_0 .net "in1", 0 0, L_0x193f790; 1 drivers +v0x1907720_0 .net "in2", 0 0, L_0x193fb80; 1 drivers +v0x19077c0_0 .net "in3", 0 0, L_0x193fc20; 1 drivers +v0x19078a0_0 .net "nS0", 0 0, L_0x193e920; 1 drivers +v0x1907940_0 .net "nS1", 0 0, L_0x193ef10; 1 drivers +v0x1907a30_0 .net "out", 0 0, L_0x193f440; 1 drivers +v0x1907ad0_0 .net "out0", 0 0, L_0x193efb0; 1 drivers +v0x1907bd0_0 .net "out1", 0 0, L_0x193f0f0; 1 drivers +v0x1907c70_0 .net "out2", 0 0, L_0x193f1e0; 1 drivers +v0x1907d80_0 .net "out3", 0 0, L_0x193f2d0; 1 drivers +S_0x1883c00 .scope module, "TwoMux" "TwoInMux" 3 294, 3 8, S_0x1883e50; + .timescale -9 -12; +L_0x1939330/d .functor NOT 1, L_0x19402d0, C4<0>, C4<0>, C4<0>; +L_0x1939330 .delay (10000,10000,10000) L_0x1939330/d; +L_0x193f9c0/d .functor AND 1, L_0x193fed0, L_0x1939330, C4<1>, C4<1>; +L_0x193f9c0 .delay (20000,20000,20000) L_0x193f9c0/d; +L_0x193fab0/d .functor AND 1, L_0x193ffc0, L_0x19402d0, C4<1>, C4<1>; +L_0x193fab0 .delay (20000,20000,20000) L_0x193fab0/d; +L_0x19400f0/d .functor OR 1, L_0x193f9c0, L_0x193fab0, C4<0>, C4<0>; +L_0x19400f0 .delay (20000,20000,20000) L_0x19400f0/d; +v0x184e470_0 .net "S", 0 0, L_0x19402d0; 1 drivers +v0x1906fa0_0 .net "in0", 0 0, L_0x193fed0; 1 drivers +v0x1907040_0 .net "in1", 0 0, L_0x193ffc0; 1 drivers +v0x19070e0_0 .net "nS", 0 0, L_0x1939330; 1 drivers +v0x1907190_0 .net "out0", 0 0, L_0x193f9c0; 1 drivers +v0x1907230_0 .net "out1", 0 0, L_0x193fab0; 1 drivers +v0x1907310_0 .net "outfinal", 0 0, L_0x19400f0; 1 drivers + .scope S_0x18c7e50; T_0 ; %vpi_call 2 150 "$display", "Test 4 Bit Adder Functionality"; %vpi_call 2 152 "$display", " A | B |Command| Out|ExpectedOut|Cout|OF"; %movi 8, 2, 4; - %set/v v0x1e49000_0, 8, 4; + %set/v v0x1929e30_0, 8, 4; %movi 8, 4, 4; - %set/v v0x1e49200_0, 8, 4; - %set/v v0x1e49280_0, 0, 3; + %set/v v0x192a030_0, 8, 4; + %set/v v0x192a0b0_0, 0, 3; %delay 1000000, 0; - %vpi_call 2 156 "$display", "%b | %b | %b | %b | Expect 0110| %b | %b ", v0x1e49000_0, v0x1e49200_0, v0x1e49280_0, v0x1e49080_0, v0x1e49580_0, v0x1e49600_0; + %vpi_call 2 156 "$display", "%b | %b | %b | %b | Expect 0110| %b | %b ", v0x1929e30_0, v0x192a030_0, v0x192a0b0_0, v0x1929eb0_0, v0x192a3b0_0, v0x192a430_0; %movi 8, 1, 4; - %set/v v0x1e49000_0, 8, 4; + %set/v v0x1929e30_0, 8, 4; %movi 8, 6, 4; - %set/v v0x1e49200_0, 8, 4; - %set/v v0x1e49280_0, 0, 3; + %set/v v0x192a030_0, 8, 4; + %set/v v0x192a0b0_0, 0, 3; %delay 1000000, 0; - %vpi_call 2 160 "$display", "%b | %b | %b | %b | Expect 0111| %b | %b ", v0x1e49000_0, v0x1e49200_0, v0x1e49280_0, v0x1e49080_0, v0x1e49580_0, v0x1e49600_0; + %vpi_call 2 160 "$display", "%b | %b | %b | %b | Expect 0111| %b | %b ", v0x1929e30_0, v0x192a030_0, v0x192a0b0_0, v0x1929eb0_0, v0x192a3b0_0, v0x192a430_0; %movi 8, 5, 4; - %set/v v0x1e49000_0, 8, 4; + %set/v v0x1929e30_0, 8, 4; %movi 8, 13, 4; - %set/v v0x1e49200_0, 8, 4; - %set/v v0x1e49280_0, 0, 3; + %set/v v0x192a030_0, 8, 4; + %set/v v0x192a0b0_0, 0, 3; %delay 1000000, 0; - %vpi_call 2 164 "$display", "%b | %b | %b | %b | Expect 0010| %b | %b ", v0x1e49000_0, v0x1e49200_0, v0x1e49280_0, v0x1e49080_0, v0x1e49580_0, v0x1e49600_0; + %vpi_call 2 164 "$display", "%b | %b | %b | %b | Expect 0010| %b | %b ", v0x1929e30_0, v0x192a030_0, v0x192a0b0_0, v0x1929eb0_0, v0x192a3b0_0, v0x192a430_0; %movi 8, 2, 4; - %set/v v0x1e49000_0, 8, 4; - %set/v v0x1e49200_0, 1, 4; - %set/v v0x1e49280_0, 0, 3; + %set/v v0x1929e30_0, 8, 4; + %set/v v0x192a030_0, 1, 4; + %set/v v0x192a0b0_0, 0, 3; %delay 1000000, 0; - %vpi_call 2 168 "$display", "%b | %b | %b | %b | Expect 0001| %b | %b ", v0x1e49000_0, v0x1e49200_0, v0x1e49280_0, v0x1e49080_0, v0x1e49580_0, v0x1e49600_0; + %vpi_call 2 168 "$display", "%b | %b | %b | %b | Expect 0001| %b | %b ", v0x1929e30_0, v0x192a030_0, v0x192a0b0_0, v0x1929eb0_0, v0x192a3b0_0, v0x192a430_0; %movi 8, 8, 4; - %set/v v0x1e49000_0, 8, 4; + %set/v v0x1929e30_0, 8, 4; %movi 8, 3, 4; - %set/v v0x1e49200_0, 8, 4; - %set/v v0x1e49280_0, 0, 3; + %set/v v0x192a030_0, 8, 4; + %set/v v0x192a0b0_0, 0, 3; %delay 1000000, 0; - %vpi_call 2 172 "$display", "%b | %b | %b | %b | Expect 1011| %b | %b ", v0x1e49000_0, v0x1e49200_0, v0x1e49280_0, v0x1e49080_0, v0x1e49580_0, v0x1e49600_0; + %vpi_call 2 172 "$display", "%b | %b | %b | %b | Expect 1011| %b | %b ", v0x1929e30_0, v0x192a030_0, v0x192a0b0_0, v0x1929eb0_0, v0x192a3b0_0, v0x192a430_0; %movi 8, 12, 4; - %set/v v0x1e49000_0, 8, 4; + %set/v v0x1929e30_0, 8, 4; %movi 8, 2, 4; - %set/v v0x1e49200_0, 8, 4; - %set/v v0x1e49280_0, 0, 3; + %set/v v0x192a030_0, 8, 4; + %set/v v0x192a0b0_0, 0, 3; %delay 1000000, 0; - %vpi_call 2 176 "$display", "%b | %b | %b | %b | Expect 1110| %b | %b ", v0x1e49000_0, v0x1e49200_0, v0x1e49280_0, v0x1e49080_0, v0x1e49580_0, v0x1e49600_0; + %vpi_call 2 176 "$display", "%b | %b | %b | %b | Expect 1110| %b | %b ", v0x1929e30_0, v0x192a030_0, v0x192a0b0_0, v0x1929eb0_0, v0x192a3b0_0, v0x192a430_0; %movi 8, 11, 4; - %set/v v0x1e49000_0, 8, 4; + %set/v v0x1929e30_0, 8, 4; %movi 8, 5, 4; - %set/v v0x1e49200_0, 8, 4; - %set/v v0x1e49280_0, 0, 3; + %set/v v0x192a030_0, 8, 4; + %set/v v0x192a0b0_0, 0, 3; %delay 1000000, 0; - %vpi_call 2 180 "$display", "%b | %b | %b | %b | Expect 0110| %b | %b ", v0x1e49000_0, v0x1e49200_0, v0x1e49280_0, v0x1e49080_0, v0x1e49580_0, v0x1e49600_0; + %vpi_call 2 180 "$display", "%b | %b | %b | %b | Expect 0110| %b | %b ", v0x1929e30_0, v0x192a030_0, v0x192a0b0_0, v0x1929eb0_0, v0x192a3b0_0, v0x192a430_0; %movi 8, 7, 4; - %set/v v0x1e49000_0, 8, 4; + %set/v v0x1929e30_0, 8, 4; %movi 8, 9, 4; - %set/v v0x1e49200_0, 8, 4; - %set/v v0x1e49280_0, 0, 3; + %set/v v0x192a030_0, 8, 4; + %set/v v0x192a0b0_0, 0, 3; %delay 1000000, 0; - %vpi_call 2 184 "$display", "%b | %b | %b | %b | Expect 0000| %b | %b ", v0x1e49000_0, v0x1e49200_0, v0x1e49280_0, v0x1e49080_0, v0x1e49580_0, v0x1e49600_0; + %vpi_call 2 184 "$display", "%b | %b | %b | %b | Expect 0000| %b | %b ", v0x1929e30_0, v0x192a030_0, v0x192a0b0_0, v0x1929eb0_0, v0x192a3b0_0, v0x192a430_0; %movi 8, 13, 4; - %set/v v0x1e49000_0, 8, 4; + %set/v v0x1929e30_0, 8, 4; %movi 8, 12, 4; - %set/v v0x1e49200_0, 8, 4; - %set/v v0x1e49280_0, 0, 3; + %set/v v0x192a030_0, 8, 4; + %set/v v0x192a0b0_0, 0, 3; %delay 1000000, 0; - %vpi_call 2 188 "$display", "%b | %b | %b | %b | Expect 1001| %b | %b ", v0x1e49000_0, v0x1e49200_0, v0x1e49280_0, v0x1e49080_0, v0x1e49580_0, v0x1e49600_0; + %vpi_call 2 188 "$display", "%b | %b | %b | %b | Expect 1001| %b | %b ", v0x1929e30_0, v0x192a030_0, v0x192a0b0_0, v0x1929eb0_0, v0x192a3b0_0, v0x192a430_0; %movi 8, 14, 4; - %set/v v0x1e49000_0, 8, 4; + %set/v v0x1929e30_0, 8, 4; %movi 8, 10, 4; - %set/v v0x1e49200_0, 8, 4; - %set/v v0x1e49280_0, 0, 3; + %set/v v0x192a030_0, 8, 4; + %set/v v0x192a0b0_0, 0, 3; %delay 1000000, 0; - %vpi_call 2 192 "$display", "%b | %b | %b | %b | Expect 1000| %b | %b ", v0x1e49000_0, v0x1e49200_0, v0x1e49280_0, v0x1e49080_0, v0x1e49580_0, v0x1e49600_0; + %vpi_call 2 192 "$display", "%b | %b | %b | %b | Expect 1000| %b | %b ", v0x1929e30_0, v0x192a030_0, v0x192a0b0_0, v0x1929eb0_0, v0x192a3b0_0, v0x192a430_0; %movi 8, 5, 4; - %set/v v0x1e49000_0, 8, 4; + %set/v v0x1929e30_0, 8, 4; %movi 8, 6, 4; - %set/v v0x1e49200_0, 8, 4; - %set/v v0x1e49280_0, 0, 3; + %set/v v0x192a030_0, 8, 4; + %set/v v0x192a0b0_0, 0, 3; %delay 1000000, 0; - %vpi_call 2 196 "$display", "%b | %b | %b | %b | Expect XXXX| %b | %b ", v0x1e49000_0, v0x1e49200_0, v0x1e49280_0, v0x1e49080_0, v0x1e49580_0, v0x1e49600_0; + %vpi_call 2 196 "$display", "%b | %b | %b | %b | Expect XXXX| %b | %b ", v0x1929e30_0, v0x192a030_0, v0x192a0b0_0, v0x1929eb0_0, v0x192a3b0_0, v0x192a430_0; %movi 8, 2, 4; - %set/v v0x1e49000_0, 8, 4; + %set/v v0x1929e30_0, 8, 4; %movi 8, 7, 4; - %set/v v0x1e49200_0, 8, 4; - %set/v v0x1e49280_0, 0, 3; + %set/v v0x192a030_0, 8, 4; + %set/v v0x192a0b0_0, 0, 3; %delay 1000000, 0; - %vpi_call 2 200 "$display", "%b | %b | %b | %b | Expect XXXX| %b | %b ", v0x1e49000_0, v0x1e49200_0, v0x1e49280_0, v0x1e49080_0, v0x1e49580_0, v0x1e49600_0; + %vpi_call 2 200 "$display", "%b | %b | %b | %b | Expect XXXX| %b | %b ", v0x1929e30_0, v0x192a030_0, v0x192a0b0_0, v0x1929eb0_0, v0x192a3b0_0, v0x192a430_0; %movi 8, 7, 4; - %set/v v0x1e49000_0, 8, 4; + %set/v v0x1929e30_0, 8, 4; %movi 8, 7, 4; - %set/v v0x1e49200_0, 8, 4; - %set/v v0x1e49280_0, 0, 3; + %set/v v0x192a030_0, 8, 4; + %set/v v0x192a0b0_0, 0, 3; %delay 1000000, 0; - %vpi_call 2 204 "$display", "%b | %b | %b | %b | Expect XXXX| %b | %b ", v0x1e49000_0, v0x1e49200_0, v0x1e49280_0, v0x1e49080_0, v0x1e49580_0, v0x1e49600_0; + %vpi_call 2 204 "$display", "%b | %b | %b | %b | Expect XXXX| %b | %b ", v0x1929e30_0, v0x192a030_0, v0x192a0b0_0, v0x1929eb0_0, v0x192a3b0_0, v0x192a430_0; %movi 8, 8, 4; - %set/v v0x1e49000_0, 8, 4; - %set/v v0x1e49200_0, 1, 4; - %set/v v0x1e49280_0, 0, 3; + %set/v v0x1929e30_0, 8, 4; + %set/v v0x192a030_0, 1, 4; + %set/v v0x192a0b0_0, 0, 3; %delay 1000000, 0; - %vpi_call 2 208 "$display", "%b | %b | %b | %b | Expect XXXX| %b | %b ", v0x1e49000_0, v0x1e49200_0, v0x1e49280_0, v0x1e49080_0, v0x1e49580_0, v0x1e49600_0; + %vpi_call 2 208 "$display", "%b | %b | %b | %b | Expect XXXX| %b | %b ", v0x1929e30_0, v0x192a030_0, v0x192a0b0_0, v0x1929eb0_0, v0x192a3b0_0, v0x192a430_0; %movi 8, 8, 4; - %set/v v0x1e49000_0, 8, 4; + %set/v v0x1929e30_0, 8, 4; %movi 8, 13, 4; - %set/v v0x1e49200_0, 8, 4; - %set/v v0x1e49280_0, 0, 3; + %set/v v0x192a030_0, 8, 4; + %set/v v0x192a0b0_0, 0, 3; %delay 1000000, 0; - %vpi_call 2 212 "$display", "%b | %b | %b | %b | Expect XXXX| %b | %b ", v0x1e49000_0, v0x1e49200_0, v0x1e49280_0, v0x1e49080_0, v0x1e49580_0, v0x1e49600_0; + %vpi_call 2 212 "$display", "%b | %b | %b | %b | Expect XXXX| %b | %b ", v0x1929e30_0, v0x192a030_0, v0x192a0b0_0, v0x1929eb0_0, v0x192a3b0_0, v0x192a430_0; %movi 8, 11, 4; - %set/v v0x1e49000_0, 8, 4; + %set/v v0x1929e30_0, 8, 4; %movi 8, 12, 4; - %set/v v0x1e49200_0, 8, 4; - %set/v v0x1e49280_0, 0, 3; + %set/v v0x192a030_0, 8, 4; + %set/v v0x192a0b0_0, 0, 3; %delay 1000000, 0; - %vpi_call 2 216 "$display", "%b | %b | %b | %b | Expect XXXX| %b | %b ", v0x1e49000_0, v0x1e49200_0, v0x1e49280_0, v0x1e49080_0, v0x1e49580_0, v0x1e49600_0; + %vpi_call 2 216 "$display", "%b | %b | %b | %b | Expect XXXX| %b | %b ", v0x1929e30_0, v0x192a030_0, v0x192a0b0_0, v0x1929eb0_0, v0x192a3b0_0, v0x192a430_0; %vpi_call 2 218 "$display", "Test 4 Bit SLT Functionality"; %vpi_call 2 220 "$display", " A | B |Command| Out|ExpectedOut|Cout|OF |SLTflag"; %movi 8, 2, 4; - %set/v v0x1e49000_0, 8, 4; + %set/v v0x1929e30_0, 8, 4; %movi 8, 4, 4; - %set/v v0x1e49200_0, 8, 4; + %set/v v0x192a030_0, 8, 4; %movi 8, 3, 3; - %set/v v0x1e49280_0, 8, 3; + %set/v v0x192a0b0_0, 8, 3; %delay 1000000, 0; - %vpi_call 2 224 "$display", "%b | %b | %b | %b | Expect 1110| %b | %b | %b", v0x1e49000_0, v0x1e49200_0, v0x1e49280_0, v0x1e49080_0, v0x1e49580_0, v0x1e49600_0, v0x1e49400_0; + %vpi_call 2 224 "$display", "%b | %b | %b | %b | Expect 1110| %b | %b | %b", v0x1929e30_0, v0x192a030_0, v0x192a0b0_0, v0x1929eb0_0, v0x192a3b0_0, v0x192a430_0, v0x192a230_0; %movi 8, 4, 4; - %set/v v0x1e49000_0, 8, 4; + %set/v v0x1929e30_0, 8, 4; %movi 8, 2, 4; - %set/v v0x1e49200_0, 8, 4; + %set/v v0x192a030_0, 8, 4; %movi 8, 3, 3; - %set/v v0x1e49280_0, 8, 3; + %set/v v0x192a0b0_0, 8, 3; %delay 1000000, 0; - %vpi_call 2 228 "$display", "%b | %b | %b | %b | Expect 0010| %b | %b | %b", v0x1e49000_0, v0x1e49200_0, v0x1e49280_0, v0x1e49080_0, v0x1e49580_0, v0x1e49600_0, v0x1e49400_0; + %vpi_call 2 228 "$display", "%b | %b | %b | %b | Expect 0010| %b | %b | %b", v0x1929e30_0, v0x192a030_0, v0x192a0b0_0, v0x1929eb0_0, v0x192a3b0_0, v0x192a430_0, v0x192a230_0; %movi 8, 14, 4; - %set/v v0x1e49000_0, 8, 4; + %set/v v0x1929e30_0, 8, 4; %movi 8, 4, 4; - %set/v v0x1e49200_0, 8, 4; + %set/v v0x192a030_0, 8, 4; %movi 8, 3, 3; - %set/v v0x1e49280_0, 8, 3; + %set/v v0x192a0b0_0, 8, 3; %delay 1000000, 0; - %vpi_call 2 232 "$display", "%b | %b | %b | %b | Expect 1010| %b | %b | %b", v0x1e49000_0, v0x1e49200_0, v0x1e49280_0, v0x1e49080_0, v0x1e49580_0, v0x1e49600_0, v0x1e49400_0; + %vpi_call 2 232 "$display", "%b | %b | %b | %b | Expect 1010| %b | %b | %b", v0x1929e30_0, v0x192a030_0, v0x192a0b0_0, v0x1929eb0_0, v0x192a3b0_0, v0x192a430_0, v0x192a230_0; %movi 8, 4, 4; - %set/v v0x1e49000_0, 8, 4; + %set/v v0x1929e30_0, 8, 4; %movi 8, 14, 4; - %set/v v0x1e49200_0, 8, 4; + %set/v v0x192a030_0, 8, 4; %movi 8, 3, 3; - %set/v v0x1e49280_0, 8, 3; + %set/v v0x192a0b0_0, 8, 3; %delay 1000000, 0; - %vpi_call 2 236 "$display", "%b | %b | %b | %b | Expect 0110| %b | %b | %b", v0x1e49000_0, v0x1e49200_0, v0x1e49280_0, v0x1e49080_0, v0x1e49580_0, v0x1e49600_0, v0x1e49400_0; + %vpi_call 2 236 "$display", "%b | %b | %b | %b | Expect 0110| %b | %b | %b", v0x1929e30_0, v0x192a030_0, v0x192a0b0_0, v0x1929eb0_0, v0x192a3b0_0, v0x192a430_0, v0x192a230_0; %movi 8, 14, 4; - %set/v v0x1e49000_0, 8, 4; - %set/v v0x1e49200_0, 1, 4; + %set/v v0x1929e30_0, 8, 4; + %set/v v0x192a030_0, 1, 4; %movi 8, 3, 3; - %set/v v0x1e49280_0, 8, 3; + %set/v v0x192a0b0_0, 8, 3; %delay 1000000, 0; - %vpi_call 2 240 "$display", "%b | %b | %b | %b | Expect 1111| %b | %b | %b", v0x1e49000_0, v0x1e49200_0, v0x1e49280_0, v0x1e49080_0, v0x1e49580_0, v0x1e49600_0, v0x1e49400_0; - %set/v v0x1e49000_0, 1, 4; + %vpi_call 2 240 "$display", "%b | %b | %b | %b | Expect 1111| %b | %b | %b", v0x1929e30_0, v0x192a030_0, v0x192a0b0_0, v0x1929eb0_0, v0x192a3b0_0, v0x192a430_0, v0x192a230_0; + %set/v v0x1929e30_0, 1, 4; %movi 8, 14, 4; - %set/v v0x1e49200_0, 8, 4; + %set/v v0x192a030_0, 8, 4; %movi 8, 3, 3; - %set/v v0x1e49280_0, 8, 3; + %set/v v0x192a0b0_0, 8, 3; %delay 1000000, 0; - %vpi_call 2 244 "$display", "%b | %b | %b | %b | Expect 0001| %b | %b | %b", v0x1e49000_0, v0x1e49200_0, v0x1e49280_0, v0x1e49080_0, v0x1e49580_0, v0x1e49600_0, v0x1e49400_0; + %vpi_call 2 244 "$display", "%b | %b | %b | %b | Expect 0001| %b | %b | %b", v0x1929e30_0, v0x192a030_0, v0x192a0b0_0, v0x1929eb0_0, v0x192a3b0_0, v0x192a430_0, v0x192a230_0; %movi 8, 13, 4; - %set/v v0x1e49000_0, 8, 4; + %set/v v0x1929e30_0, 8, 4; %movi 8, 13, 4; - %set/v v0x1e49200_0, 8, 4; + %set/v v0x192a030_0, 8, 4; %movi 8, 3, 3; - %set/v v0x1e49280_0, 8, 3; + %set/v v0x192a0b0_0, 8, 3; %delay 1000000, 0; - %vpi_call 2 248 "$display", "%b | %b | %b | %b | Expect 0000| %b | %b | %b", v0x1e49000_0, v0x1e49200_0, v0x1e49280_0, v0x1e49080_0, v0x1e49580_0, v0x1e49600_0, v0x1e49400_0; + %vpi_call 2 248 "$display", "%b | %b | %b | %b | Expect 0000| %b | %b | %b", v0x1929e30_0, v0x192a030_0, v0x192a0b0_0, v0x1929eb0_0, v0x192a3b0_0, v0x192a430_0, v0x192a230_0; %movi 8, 5, 4; - %set/v v0x1e49000_0, 8, 4; + %set/v v0x1929e30_0, 8, 4; %movi 8, 5, 4; - %set/v v0x1e49200_0, 8, 4; + %set/v v0x192a030_0, 8, 4; %movi 8, 3, 3; - %set/v v0x1e49280_0, 8, 3; + %set/v v0x192a0b0_0, 8, 3; %delay 1000000, 0; - %vpi_call 2 252 "$display", "%b | %b | %b | %b | Expect 0000| %b | %b | %b", v0x1e49000_0, v0x1e49200_0, v0x1e49280_0, v0x1e49080_0, v0x1e49580_0, v0x1e49600_0, v0x1e49400_0; + %vpi_call 2 252 "$display", "%b | %b | %b | %b | Expect 0000| %b | %b | %b", v0x1929e30_0, v0x192a030_0, v0x192a0b0_0, v0x1929eb0_0, v0x192a3b0_0, v0x192a430_0, v0x192a230_0; %movi 8, 9, 4; - %set/v v0x1e49000_0, 8, 4; + %set/v v0x1929e30_0, 8, 4; %movi 8, 5, 4; - %set/v v0x1e49200_0, 8, 4; + %set/v v0x192a030_0, 8, 4; %movi 8, 3, 3; - %set/v v0x1e49280_0, 8, 3; + %set/v v0x192a0b0_0, 8, 3; %delay 1000000, 0; - %vpi_call 2 256 "$display", "%b | %b | %b | %b | Expect XXXX| %b | %b | %b", v0x1e49000_0, v0x1e49200_0, v0x1e49280_0, v0x1e49080_0, v0x1e49580_0, v0x1e49600_0, v0x1e49400_0; + %vpi_call 2 256 "$display", "%b | %b | %b | %b | Expect XXXX| %b | %b | %b", v0x1929e30_0, v0x192a030_0, v0x192a0b0_0, v0x1929eb0_0, v0x192a3b0_0, v0x192a430_0, v0x192a230_0; %vpi_call 2 258 "$display", "Test 4 Bit AND/NAND Functionality"; %vpi_call 2 260 "$display", " A | B |Command| Out |ExpectedOut-AND"; - %set/v v0x1e49000_0, 1, 4; - %set/v v0x1e49200_0, 1, 4; + %set/v v0x1929e30_0, 1, 4; + %set/v v0x192a030_0, 1, 4; %movi 8, 4, 3; - %set/v v0x1e49280_0, 8, 3; + %set/v v0x192a0b0_0, 8, 3; %delay 1000000, 0; - %vpi_call 2 264 "$display", "%b | %b | %b | %b | 1111", v0x1e49000_0, v0x1e49200_0, v0x1e49280_0, v0x1e49180_0; - %set/v v0x1e49000_0, 1, 4; + %vpi_call 2 264 "$display", "%b | %b | %b | %b | 1111", v0x1929e30_0, v0x192a030_0, v0x192a0b0_0, v0x1929fb0_0; + %set/v v0x1929e30_0, 1, 4; %movi 8, 10, 4; - %set/v v0x1e49200_0, 8, 4; + %set/v v0x192a030_0, 8, 4; %movi 8, 4, 3; - %set/v v0x1e49280_0, 8, 3; + %set/v v0x192a0b0_0, 8, 3; %delay 1000000, 0; - %vpi_call 2 268 "$display", "%b | %b | %b | %b | 1010", v0x1e49000_0, v0x1e49200_0, v0x1e49280_0, v0x1e49180_0; - %set/v v0x1e49000_0, 1, 4; + %vpi_call 2 268 "$display", "%b | %b | %b | %b | 1010", v0x1929e30_0, v0x192a030_0, v0x192a0b0_0, v0x1929fb0_0; + %set/v v0x1929e30_0, 1, 4; %movi 8, 5, 4; - %set/v v0x1e49200_0, 8, 4; + %set/v v0x192a030_0, 8, 4; %movi 8, 4, 3; - %set/v v0x1e49280_0, 8, 3; + %set/v v0x192a0b0_0, 8, 3; %delay 1000000, 0; - %vpi_call 2 272 "$display", "%b | %b | %b | %b | 0101", v0x1e49000_0, v0x1e49200_0, v0x1e49280_0, v0x1e49180_0; - %set/v v0x1e49000_0, 1, 4; - %set/v v0x1e49200_0, 0, 4; + %vpi_call 2 272 "$display", "%b | %b | %b | %b | 0101", v0x1929e30_0, v0x192a030_0, v0x192a0b0_0, v0x1929fb0_0; + %set/v v0x1929e30_0, 1, 4; + %set/v v0x192a030_0, 0, 4; %movi 8, 4, 3; - %set/v v0x1e49280_0, 8, 3; + %set/v v0x192a0b0_0, 8, 3; %delay 1000000, 0; - %vpi_call 2 276 "$display", "%b | %b | %b | %b | 0000", v0x1e49000_0, v0x1e49200_0, v0x1e49280_0, v0x1e49180_0; + %vpi_call 2 276 "$display", "%b | %b | %b | %b | 0000", v0x1929e30_0, v0x192a030_0, v0x192a0b0_0, v0x1929fb0_0; %vpi_call 2 279 "$display", " A | B |Command| Out |ExpectedOut-NAND"; - %set/v v0x1e49000_0, 1, 4; - %set/v v0x1e49200_0, 1, 4; + %set/v v0x1929e30_0, 1, 4; + %set/v v0x192a030_0, 1, 4; %movi 8, 5, 3; - %set/v v0x1e49280_0, 8, 3; + %set/v v0x192a0b0_0, 8, 3; %delay 1000000, 0; - %vpi_call 2 283 "$display", "%b | %b | %b | %b | 0000", v0x1e49000_0, v0x1e49200_0, v0x1e49280_0, v0x1e49180_0; - %set/v v0x1e49000_0, 1, 4; + %vpi_call 2 283 "$display", "%b | %b | %b | %b | 0000", v0x1929e30_0, v0x192a030_0, v0x192a0b0_0, v0x1929fb0_0; + %set/v v0x1929e30_0, 1, 4; %movi 8, 10, 4; - %set/v v0x1e49200_0, 8, 4; + %set/v v0x192a030_0, 8, 4; %movi 8, 5, 3; - %set/v v0x1e49280_0, 8, 3; + %set/v v0x192a0b0_0, 8, 3; %delay 1000000, 0; - %vpi_call 2 287 "$display", "%b | %b | %b | %b | 0101", v0x1e49000_0, v0x1e49200_0, v0x1e49280_0, v0x1e49180_0; - %set/v v0x1e49000_0, 1, 4; + %vpi_call 2 287 "$display", "%b | %b | %b | %b | 0101", v0x1929e30_0, v0x192a030_0, v0x192a0b0_0, v0x1929fb0_0; + %set/v v0x1929e30_0, 1, 4; %movi 8, 5, 4; - %set/v v0x1e49200_0, 8, 4; + %set/v v0x192a030_0, 8, 4; %movi 8, 5, 3; - %set/v v0x1e49280_0, 8, 3; + %set/v v0x192a0b0_0, 8, 3; %delay 1000000, 0; - %vpi_call 2 291 "$display", "%b | %b | %b | %b | 1010", v0x1e49000_0, v0x1e49200_0, v0x1e49280_0, v0x1e49180_0; - %set/v v0x1e49000_0, 1, 4; - %set/v v0x1e49200_0, 0, 4; + %vpi_call 2 291 "$display", "%b | %b | %b | %b | 1010", v0x1929e30_0, v0x192a030_0, v0x192a0b0_0, v0x1929fb0_0; + %set/v v0x1929e30_0, 1, 4; + %set/v v0x192a030_0, 0, 4; %movi 8, 5, 3; - %set/v v0x1e49280_0, 8, 3; + %set/v v0x192a0b0_0, 8, 3; %delay 1000000, 0; - %vpi_call 2 295 "$display", "%b | %b | %b | %b | 1111", v0x1e49000_0, v0x1e49200_0, v0x1e49280_0, v0x1e49180_0; + %vpi_call 2 295 "$display", "%b | %b | %b | %b | 1111", v0x1929e30_0, v0x192a030_0, v0x192a0b0_0, v0x1929fb0_0; %vpi_call 2 297 "$display", "Test 4 Bit OR/NOR/XOR Functionality"; %vpi_call 2 299 "$display", " A | B |Command | Out |ExpectedOut-OR"; %movi 8, 10, 4; - %set/v v0x1e49000_0, 8, 4; + %set/v v0x1929e30_0, 8, 4; %movi 8, 5, 4; - %set/v v0x1e49200_0, 8, 4; - %set/v v0x1e49280_0, 1, 3; + %set/v v0x192a030_0, 8, 4; + %set/v v0x192a0b0_0, 1, 3; %delay 1000000, 0; - %vpi_call 2 303 "$display", "%b | %b | %b | %b | 1111", v0x1e49000_0, v0x1e49200_0, v0x1e49280_0, v0x1e49380_0; - %set/v v0x1e49000_0, 1, 4; + %vpi_call 2 303 "$display", "%b | %b | %b | %b | 1111", v0x1929e30_0, v0x192a030_0, v0x192a0b0_0, v0x192a1b0_0; + %set/v v0x1929e30_0, 1, 4; %movi 8, 5, 4; - %set/v v0x1e49200_0, 8, 4; - %set/v v0x1e49280_0, 1, 3; + %set/v v0x192a030_0, 8, 4; + %set/v v0x192a0b0_0, 1, 3; %delay 1000000, 0; - %vpi_call 2 307 "$display", "%b | %b | %b | %b | 1111", v0x1e49000_0, v0x1e49200_0, v0x1e49280_0, v0x1e49380_0; + %vpi_call 2 307 "$display", "%b | %b | %b | %b | 1111", v0x1929e30_0, v0x192a030_0, v0x192a0b0_0, v0x192a1b0_0; %movi 8, 11, 4; - %set/v v0x1e49000_0, 8, 4; - %set/v v0x1e49200_0, 0, 4; - %set/v v0x1e49280_0, 1, 3; + %set/v v0x1929e30_0, 8, 4; + %set/v v0x192a030_0, 0, 4; + %set/v v0x192a0b0_0, 1, 3; %delay 1000000, 0; - %vpi_call 2 311 "$display", "%b | %b | %b | %b | 1011", v0x1e49000_0, v0x1e49200_0, v0x1e49280_0, v0x1e49380_0; + %vpi_call 2 311 "$display", "%b | %b | %b | %b | 1011", v0x1929e30_0, v0x192a030_0, v0x192a0b0_0, v0x192a1b0_0; %vpi_call 2 313 "$display", " A | B |Command | Out |ExpectedOut-NOR"; %movi 8, 10, 4; - %set/v v0x1e49000_0, 8, 4; + %set/v v0x1929e30_0, 8, 4; %movi 8, 5, 4; - %set/v v0x1e49200_0, 8, 4; + %set/v v0x192a030_0, 8, 4; %movi 8, 6, 3; - %set/v v0x1e49280_0, 8, 3; + %set/v v0x192a0b0_0, 8, 3; %delay 1000000, 0; - %vpi_call 2 317 "$display", "%b | %b | %b | %b | 0000", v0x1e49000_0, v0x1e49200_0, v0x1e49280_0, v0x1e49380_0; - %set/v v0x1e49000_0, 1, 4; + %vpi_call 2 317 "$display", "%b | %b | %b | %b | 0000", v0x1929e30_0, v0x192a030_0, v0x192a0b0_0, v0x192a1b0_0; + %set/v v0x1929e30_0, 1, 4; %movi 8, 5, 4; - %set/v v0x1e49200_0, 8, 4; + %set/v v0x192a030_0, 8, 4; %movi 8, 6, 3; - %set/v v0x1e49280_0, 8, 3; + %set/v v0x192a0b0_0, 8, 3; %delay 1000000, 0; - %vpi_call 2 321 "$display", "%b | %b | %b | %b | 0000", v0x1e49000_0, v0x1e49200_0, v0x1e49280_0, v0x1e49380_0; + %vpi_call 2 321 "$display", "%b | %b | %b | %b | 0000", v0x1929e30_0, v0x192a030_0, v0x192a0b0_0, v0x192a1b0_0; %movi 8, 11, 4; - %set/v v0x1e49000_0, 8, 4; - %set/v v0x1e49200_0, 0, 4; + %set/v v0x1929e30_0, 8, 4; + %set/v v0x192a030_0, 0, 4; %movi 8, 6, 3; - %set/v v0x1e49280_0, 8, 3; + %set/v v0x192a0b0_0, 8, 3; %delay 1000000, 0; - %vpi_call 2 325 "$display", "%b | %b | %b | %b | 0100", v0x1e49000_0, v0x1e49200_0, v0x1e49280_0, v0x1e49380_0; + %vpi_call 2 325 "$display", "%b | %b | %b | %b | 0100", v0x1929e30_0, v0x192a030_0, v0x192a0b0_0, v0x192a1b0_0; %vpi_call 2 327 "$display", " A | B |Command | Out |ExpectedOut-XOR"; %movi 8, 10, 4; - %set/v v0x1e49000_0, 8, 4; + %set/v v0x1929e30_0, 8, 4; %movi 8, 5, 4; - %set/v v0x1e49200_0, 8, 4; + %set/v v0x192a030_0, 8, 4; %movi 8, 2, 3; - %set/v v0x1e49280_0, 8, 3; + %set/v v0x192a0b0_0, 8, 3; %delay 1000000, 0; - %vpi_call 2 331 "$display", "%b | %b | %b | %b | 1111", v0x1e49000_0, v0x1e49200_0, v0x1e49280_0, v0x1e49380_0; - %set/v v0x1e49000_0, 1, 4; + %vpi_call 2 331 "$display", "%b | %b | %b | %b | 1111", v0x1929e30_0, v0x192a030_0, v0x192a0b0_0, v0x192a1b0_0; + %set/v v0x1929e30_0, 1, 4; %movi 8, 5, 4; - %set/v v0x1e49200_0, 8, 4; + %set/v v0x192a030_0, 8, 4; %movi 8, 2, 3; - %set/v v0x1e49280_0, 8, 3; + %set/v v0x192a0b0_0, 8, 3; %delay 1000000, 0; - %vpi_call 2 335 "$display", "%b | %b | %b | %b | 1010", v0x1e49000_0, v0x1e49200_0, v0x1e49280_0, v0x1e49380_0; + %vpi_call 2 335 "$display", "%b | %b | %b | %b | 1010", v0x1929e30_0, v0x192a030_0, v0x192a0b0_0, v0x192a1b0_0; %movi 8, 11, 4; - %set/v v0x1e49000_0, 8, 4; - %set/v v0x1e49200_0, 0, 4; + %set/v v0x1929e30_0, 8, 4; + %set/v v0x192a030_0, 0, 4; %movi 8, 2, 3; - %set/v v0x1e49280_0, 8, 3; + %set/v v0x192a0b0_0, 8, 3; %delay 1000000, 0; - %vpi_call 2 339 "$display", "%b | %b | %b | %b | 1011", v0x1e49000_0, v0x1e49200_0, v0x1e49280_0, v0x1e49380_0; + %vpi_call 2 339 "$display", "%b | %b | %b | %b | 1011", v0x1929e30_0, v0x192a030_0, v0x192a0b0_0, v0x192a1b0_0; %vpi_call 2 341 "$display", "Test 4 Bit ALU Functionality"; %vpi_call 2 343 "$display", " A | B |Command | Out |ExpectedOut | COut | OF |SLT|Zero"; - %set/v v0x1e49000_0, 1, 4; - %set/v v0x1e49200_0, 1, 4; + %set/v v0x1929e30_0, 1, 4; + %set/v v0x192a030_0, 1, 4; %movi 8, 4, 3; - %set/v v0x1e49280_0, 8, 3; + %set/v v0x192a0b0_0, 8, 3; %delay 1000000, 0; - %vpi_call 2 348 "$display", "%b | %b | %b - AND | %b | 1111 | %b | %b | %b | %b", v0x1e49000_0, v0x1e49200_0, v0x1e49280_0, v0x1e49300_0, v0x1e49580_0, v0x1e49600_0, v0x1e49400_0, v0x1e49100_0; - %set/v v0x1e49000_0, 1, 4; - %set/v v0x1e49200_0, 0, 4; + %vpi_call 2 348 "$display", "%b | %b | %b - AND | %b | 1111 | %b | %b | %b | %b", v0x1929e30_0, v0x192a030_0, v0x192a0b0_0, v0x192a130_0, v0x192a3b0_0, v0x192a430_0, v0x192a230_0, v0x1929f30_0; + %set/v v0x1929e30_0, 1, 4; + %set/v v0x192a030_0, 0, 4; %movi 8, 5, 3; - %set/v v0x1e49280_0, 8, 3; + %set/v v0x192a0b0_0, 8, 3; %delay 1000000, 0; - %vpi_call 2 353 "$display", "%b | %b | %b - NAND | %b | 1111 | %b | %b | %b | %b", v0x1e49000_0, v0x1e49200_0, v0x1e49280_0, v0x1e49300_0, v0x1e49580_0, v0x1e49600_0, v0x1e49400_0, v0x1e49100_0; - %set/v v0x1e49000_0, 1, 4; + %vpi_call 2 353 "$display", "%b | %b | %b - NAND | %b | 1111 | %b | %b | %b | %b", v0x1929e30_0, v0x192a030_0, v0x192a0b0_0, v0x192a130_0, v0x192a3b0_0, v0x192a430_0, v0x192a230_0, v0x1929f30_0; + %set/v v0x1929e30_0, 1, 4; %movi 8, 5, 4; - %set/v v0x1e49200_0, 8, 4; - %set/v v0x1e49280_0, 1, 3; + %set/v v0x192a030_0, 8, 4; + %set/v v0x192a0b0_0, 1, 3; %delay 1000000, 0; - %vpi_call 2 358 "$display", "%b | %b | %b - OR | %b | 1111 | %b | %b | %b | %b", v0x1e49000_0, v0x1e49200_0, v0x1e49280_0, v0x1e49300_0, v0x1e49580_0, v0x1e49600_0, v0x1e49400_0, v0x1e49100_0; + %vpi_call 2 358 "$display", "%b | %b | %b - OR | %b | 1111 | %b | %b | %b | %b", v0x1929e30_0, v0x192a030_0, v0x192a0b0_0, v0x192a130_0, v0x192a3b0_0, v0x192a430_0, v0x192a230_0, v0x1929f30_0; %movi 8, 11, 4; - %set/v v0x1e49000_0, 8, 4; - %set/v v0x1e49200_0, 0, 4; + %set/v v0x1929e30_0, 8, 4; + %set/v v0x192a030_0, 0, 4; %movi 8, 6, 3; - %set/v v0x1e49280_0, 8, 3; + %set/v v0x192a0b0_0, 8, 3; %delay 1000000, 0; - %vpi_call 2 363 "$display", "%b | %b | %b - NOR | %b | 0100 | %b | %b | %b | %b", v0x1e49000_0, v0x1e49200_0, v0x1e49280_0, v0x1e49300_0, v0x1e49580_0, v0x1e49600_0, v0x1e49400_0, v0x1e49100_0; + %vpi_call 2 363 "$display", "%b | %b | %b - NOR | %b | 0100 | %b | %b | %b | %b", v0x1929e30_0, v0x192a030_0, v0x192a0b0_0, v0x192a130_0, v0x192a3b0_0, v0x192a430_0, v0x192a230_0, v0x1929f30_0; %movi 8, 11, 4; - %set/v v0x1e49000_0, 8, 4; - %set/v v0x1e49200_0, 0, 4; + %set/v v0x1929e30_0, 8, 4; + %set/v v0x192a030_0, 0, 4; %movi 8, 2, 3; - %set/v v0x1e49280_0, 8, 3; + %set/v v0x192a0b0_0, 8, 3; %delay 1000000, 0; - %vpi_call 2 368 "$display", "%b | %b | %b - XOR | %b | 1011 | %b | %b | %b | %b", v0x1e49000_0, v0x1e49200_0, v0x1e49280_0, v0x1e49300_0, v0x1e49580_0, v0x1e49600_0, v0x1e49400_0, v0x1e49100_0; + %vpi_call 2 368 "$display", "%b | %b | %b - XOR | %b | 1011 | %b | %b | %b | %b", v0x1929e30_0, v0x192a030_0, v0x192a0b0_0, v0x192a130_0, v0x192a3b0_0, v0x192a430_0, v0x192a230_0, v0x1929f30_0; %movi 8, 2, 4; - %set/v v0x1e49000_0, 8, 4; + %set/v v0x1929e30_0, 8, 4; %movi 8, 4, 4; - %set/v v0x1e49200_0, 8, 4; - %set/v v0x1e49280_0, 0, 3; + %set/v v0x192a030_0, 8, 4; + %set/v v0x192a0b0_0, 0, 3; %delay 1000000, 0; - %vpi_call 2 373 "$display", "%b | %b | %b - ADD | %b | 0110 | %b | %b | %b | %b", v0x1e49000_0, v0x1e49200_0, v0x1e49280_0, v0x1e49300_0, v0x1e49580_0, v0x1e49600_0, v0x1e49400_0, v0x1e49100_0; + %vpi_call 2 373 "$display", "%b | %b | %b - ADD | %b | 0110 | %b | %b | %b | %b", v0x1929e30_0, v0x192a030_0, v0x192a0b0_0, v0x192a130_0, v0x192a3b0_0, v0x192a430_0, v0x192a230_0, v0x1929f30_0; %movi 8, 11, 4; - %set/v v0x1e49000_0, 8, 4; + %set/v v0x1929e30_0, 8, 4; %movi 8, 12, 4; - %set/v v0x1e49200_0, 8, 4; - %set/v v0x1e49280_0, 0, 3; + %set/v v0x192a030_0, 8, 4; + %set/v v0x192a0b0_0, 0, 3; %delay 1000000, 0; - %vpi_call 2 377 "$display", "%b | %b | %b - ADD | %b | XXXX | %b | %b | %b | %b", v0x1e49000_0, v0x1e49200_0, v0x1e49280_0, v0x1e49300_0, v0x1e49580_0, v0x1e49600_0, v0x1e49400_0, v0x1e49100_0; + %vpi_call 2 377 "$display", "%b | %b | %b - ADD | %b | XXXX | %b | %b | %b | %b", v0x1929e30_0, v0x192a030_0, v0x192a0b0_0, v0x192a130_0, v0x192a3b0_0, v0x192a430_0, v0x192a230_0, v0x1929f30_0; %movi 8, 2, 4; - %set/v v0x1e49000_0, 8, 4; + %set/v v0x1929e30_0, 8, 4; %movi 8, 4, 4; - %set/v v0x1e49200_0, 8, 4; + %set/v v0x192a030_0, 8, 4; %movi 8, 1, 3; - %set/v v0x1e49280_0, 8, 3; + %set/v v0x192a0b0_0, 8, 3; %delay 1000000, 0; - %vpi_call 2 382 "$display", "%b | %b | %b - SUB | %b | 1110 | %b | %b | %b | %b", v0x1e49000_0, v0x1e49200_0, v0x1e49280_0, v0x1e49300_0, v0x1e49580_0, v0x1e49600_0, v0x1e49400_0, v0x1e49100_0; + %vpi_call 2 382 "$display", "%b | %b | %b - SUB | %b | 1110 | %b | %b | %b | %b", v0x1929e30_0, v0x192a030_0, v0x192a0b0_0, v0x192a130_0, v0x192a3b0_0, v0x192a430_0, v0x192a230_0, v0x1929f30_0; %movi 8, 9, 4; - %set/v v0x1e49000_0, 8, 4; + %set/v v0x1929e30_0, 8, 4; %movi 8, 3, 4; - %set/v v0x1e49200_0, 8, 4; + %set/v v0x192a030_0, 8, 4; %movi 8, 1, 3; - %set/v v0x1e49280_0, 8, 3; + %set/v v0x192a0b0_0, 8, 3; %delay 1000000, 0; - %vpi_call 2 386 "$display", "%b | %b | %b - SUB | %b | XXXX | %b | %b | %b | %b", v0x1e49000_0, v0x1e49200_0, v0x1e49280_0, v0x1e49300_0, v0x1e49580_0, v0x1e49600_0, v0x1e49400_0, v0x1e49100_0; + %vpi_call 2 386 "$display", "%b | %b | %b - SUB | %b | XXXX | %b | %b | %b | %b", v0x1929e30_0, v0x192a030_0, v0x192a0b0_0, v0x192a130_0, v0x192a3b0_0, v0x192a430_0, v0x192a230_0, v0x1929f30_0; %movi 8, 4, 4; - %set/v v0x1e49000_0, 8, 4; + %set/v v0x1929e30_0, 8, 4; %movi 8, 2, 4; - %set/v v0x1e49200_0, 8, 4; + %set/v v0x192a030_0, 8, 4; %movi 8, 3, 3; - %set/v v0x1e49280_0, 8, 3; + %set/v v0x192a0b0_0, 8, 3; %delay 1000000, 0; - %vpi_call 2 392 "$display", "%b | %b | %b - SLT | %b | 0010 | %b | %b | %b | %b", v0x1e49000_0, v0x1e49200_0, v0x1e49280_0, v0x1e49300_0, v0x1e49580_0, v0x1e49600_0, v0x1e49400_0, v0x1e49100_0; + %vpi_call 2 392 "$display", "%b | %b | %b - SLT | %b | 0010 | %b | %b | %b | %b", v0x1929e30_0, v0x192a030_0, v0x192a0b0_0, v0x192a130_0, v0x192a3b0_0, v0x192a430_0, v0x192a230_0, v0x1929f30_0; %movi 8, 9, 4; - %set/v v0x1e49000_0, 8, 4; + %set/v v0x1929e30_0, 8, 4; %movi 8, 5, 4; - %set/v v0x1e49200_0, 8, 4; + %set/v v0x192a030_0, 8, 4; %movi 8, 3, 3; - %set/v v0x1e49280_0, 8, 3; + %set/v v0x192a0b0_0, 8, 3; %delay 1000000, 0; - %vpi_call 2 396 "$display", "%b | %b | %b - SLT | %b | XXXX | %b | %b | %b | %b", v0x1e49000_0, v0x1e49200_0, v0x1e49280_0, v0x1e49300_0, v0x1e49580_0, v0x1e49600_0, v0x1e49400_0, v0x1e49100_0; - %set/v v0x1e49000_0, 0, 4; - %set/v v0x1e49200_0, 0, 4; + %vpi_call 2 396 "$display", "%b | %b | %b - SLT | %b | XXXX | %b | %b | %b | %b", v0x1929e30_0, v0x192a030_0, v0x192a0b0_0, v0x192a130_0, v0x192a3b0_0, v0x192a430_0, v0x192a230_0, v0x1929f30_0; + %set/v v0x1929e30_0, 0, 4; + %set/v v0x192a030_0, 1, 4; + %movi 8, 4, 3; + %set/v v0x192a0b0_0, 8, 3; + %delay 1000000, 0; + %vpi_call 2 402 "$display", "%b | %b | %b - AND | %b | 0000 | %b | %b | %b | %b", v0x1929e30_0, v0x192a030_0, v0x192a0b0_0, v0x192a130_0, v0x192a3b0_0, v0x192a430_0, v0x192a230_0, v0x1929f30_0; + %set/v v0x1929e30_0, 1, 4; + %set/v v0x192a030_0, 1, 4; + %movi 8, 5, 3; + %set/v v0x192a0b0_0, 8, 3; + %delay 1000000, 0; + %vpi_call 2 405 "$display", "%b | %b | %b - NAND | %b | 0000 | %b | %b | %b | %b", v0x1929e30_0, v0x192a030_0, v0x192a0b0_0, v0x192a130_0, v0x192a3b0_0, v0x192a430_0, v0x192a230_0, v0x1929f30_0; + %set/v v0x1929e30_0, 0, 4; + %set/v v0x192a030_0, 0, 4; + %set/v v0x192a0b0_0, 1, 3; + %delay 1000000, 0; + %vpi_call 2 408 "$display", "%b | %b | %b - OR | %b | 0000 | %b | %b | %b | %b", v0x1929e30_0, v0x192a030_0, v0x192a0b0_0, v0x192a130_0, v0x192a3b0_0, v0x192a430_0, v0x192a230_0, v0x1929f30_0; + %movi 8, 11, 4; + %set/v v0x1929e30_0, 8, 4; + %movi 8, 4, 4; + %set/v v0x192a030_0, 8, 4; + %movi 8, 6, 3; + %set/v v0x192a0b0_0, 8, 3; + %delay 1000000, 0; + %vpi_call 2 410 "$display", "%b | %b | %b - NOR | %b | 0000 | %b | %b | %b | %b", v0x1929e30_0, v0x192a030_0, v0x192a0b0_0, v0x192a130_0, v0x192a3b0_0, v0x192a430_0, v0x192a230_0, v0x1929f30_0; + %movi 8, 11, 4; + %set/v v0x1929e30_0, 8, 4; + %movi 8, 11, 4; + %set/v v0x192a030_0, 8, 4; + %movi 8, 2, 3; + %set/v v0x192a0b0_0, 8, 3; + %delay 1000000, 0; + %vpi_call 2 413 "$display", "%b | %b | %b - XOR | %b | 0000 | %b | %b | %b | %b", v0x1929e30_0, v0x192a030_0, v0x192a0b0_0, v0x192a130_0, v0x192a3b0_0, v0x192a430_0, v0x192a230_0, v0x1929f30_0; + %movi 8, 2, 4; + %set/v v0x1929e30_0, 8, 4; + %movi 8, 14, 4; + %set/v v0x192a030_0, 8, 4; + %set/v v0x192a0b0_0, 0, 3; + %delay 1000000, 0; + %vpi_call 2 416 "$display", "%b | %b | %b - ADD | %b | 0000 | %b | %b | %b | %b", v0x1929e30_0, v0x192a030_0, v0x192a0b0_0, v0x192a130_0, v0x192a3b0_0, v0x192a430_0, v0x192a230_0, v0x1929f30_0; + %movi 8, 2, 4; + %set/v v0x1929e30_0, 8, 4; + %movi 8, 2, 4; + %set/v v0x192a030_0, 8, 4; + %movi 8, 1, 3; + %set/v v0x192a0b0_0, 8, 3; + %delay 1000000, 0; + %vpi_call 2 419 "$display", "%b | %b | %b - SUB | %b | 0000 | %b | %b | %b | %b", v0x1929e30_0, v0x192a030_0, v0x192a0b0_0, v0x192a130_0, v0x192a3b0_0, v0x192a430_0, v0x192a230_0, v0x1929f30_0; + %set/v v0x1929e30_0, 0, 4; + %set/v v0x192a030_0, 0, 4; %movi 8, 3, 3; - %set/v v0x1e49280_0, 8, 3; + %set/v v0x192a0b0_0, 8, 3; %delay 1000000, 0; - %vpi_call 2 401 "$display", "%b | %b | %b - SLT | %b | 0000 | %b | %b | %b | %b", v0x1e49000_0, v0x1e49200_0, v0x1e49280_0, v0x1e49300_0, v0x1e49580_0, v0x1e49600_0, v0x1e49400_0, v0x1e49100_0; + %vpi_call 2 423 "$display", "%b | %b | %b - SLT | %b | 0000 | %b | %b | %b | %b", v0x1929e30_0, v0x192a030_0, v0x192a0b0_0, v0x192a130_0, v0x192a3b0_0, v0x192a430_0, v0x192a230_0, v0x1929f30_0; %end; .thread T_0; # The file index is used to find the file name in the following table. diff --git a/testing.t.v b/testing.t.v index 3cad459..33db908 100644 --- a/testing.t.v +++ b/testing.t.v @@ -395,10 +395,35 @@ A = 4'b0100; B = 4'b0010; Command =3'b011; #1000 A = 4'b1001; B = 4'b0101; Command =3'b011; #1000 $display("%b | %b | %b - SLT | %b | XXXX | %b | %b | %b | %b", A, B, Command, OneBitFinalOut, carryout, overflow, SLTflag, AllZeros); -// Test Zero -// A = B, A = 0 | B = 0 | No Overflow +// Test Zero + + + A=4'b0000;B=4'b1111;Command=3'b100; #1000 + $display("%b | %b | %b - AND | %b | 0000 | %b | %b | %b | %b", A, B, Command, OneBitFinalOut, carryout, overflow, SLTflag, AllZeros); + + A=4'b1111;B=4'b1111;Command=3'b101; #1000 + $display("%b | %b | %b - NAND | %b | 0000 | %b | %b | %b | %b", A, B, Command, OneBitFinalOut, carryout, overflow, SLTflag, AllZeros); + + A=4'b0000; B=4'b0000; Command=3'b111; #1000 + $display("%b | %b | %b - OR | %b | 0000 | %b | %b | %b | %b", A, B, Command, OneBitFinalOut, carryout, overflow, SLTflag, AllZeros); + A=4'b1011; B=4'b0100; Command=3'b110; #1000 + $display("%b | %b | %b - NOR | %b | 0000 | %b | %b | %b | %b", A, B, Command, OneBitFinalOut, carryout, overflow, SLTflag, AllZeros); + + A=4'b1011; B=4'b1011; Command=3'b010; #1000 + $display("%b | %b | %b - XOR | %b | 0000 | %b | %b | %b | %b", A, B, Command, OneBitFinalOut, carryout, overflow, SLTflag, AllZeros); + +A = 4'b0010; B = 4'b1110; Command =3'b000; #1000 + $display("%b | %b | %b - ADD | %b | 0000 | %b | %b | %b | %b", A, B, Command, OneBitFinalOut, carryout, overflow, SLTflag, AllZeros); + +A = 4'b0010; B = 4'b0010; Command =3'b001; #1000 + $display("%b | %b | %b - SUB | %b | 0000 | %b | %b | %b | %b", A, B, Command, OneBitFinalOut, carryout, overflow, SLTflag, AllZeros); + + A = 4'b0000; B = 4'b0000; Command =3'b011; #1000 $display("%b | %b | %b - SLT | %b | 0000 | %b | %b | %b | %b", A, B, Command, OneBitFinalOut, carryout, overflow, SLTflag, AllZeros); + + + end endmodule From c26a1fdbc72a80154f2d778d6653007c7c410d89 Mon Sep 17 00:00:00 2001 From: mjakus Date: Tue, 10 Oct 2017 14:24:02 -0400 Subject: [PATCH 17/28] Added for timimg --- testing.t.v | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/testing.t.v b/testing.t.v index 33db908..7c2f30a 100644 --- a/testing.t.v +++ b/testing.t.v @@ -147,6 +147,9 @@ OrNorXor32 trial2(OrNorXorOut, A, B, Command); Bitslice32 superalu(OneBitFinalOut, AddSubSLTSum, carryout, overflow, SLTflag, OrNorXorOut, AndNandOut, subtract, ZeroFlag, AllZeros, A, B, Command, carryin); initial begin + $dumpfile("FullALU.vcd"); + $dumpvars() + $display("Test 4 Bit Adder Functionality"); // there are too many possibilities even for just a four bit adder/subtractor, which means we need to choose our test cases strategically $display(" A | B |Command| Out|ExpectedOut|Cout|OF"); @@ -422,8 +425,6 @@ A = 4'b0010; B = 4'b0010; Command =3'b001; #1000 A = 4'b0000; B = 4'b0000; Command =3'b011; #1000 $display("%b | %b | %b - SLT | %b | 0000 | %b | %b | %b | %b", A, B, Command, OneBitFinalOut, carryout, overflow, SLTflag, AllZeros); - - end endmodule From 7c670ecfe5f1a4af7512e881a3fc6318f890612c Mon Sep 17 00:00:00 2001 From: mjakus Date: Tue, 10 Oct 2017 14:25:20 -0400 Subject: [PATCH 18/28] Added for timimg part 2 --- test | 4296 ++++++++++++++++++++++++++------------------------- testing.t.v | 2 +- 2 files changed, 2150 insertions(+), 2148 deletions(-) diff --git a/test b/test index 1fb5990..702278a 100755 --- a/test +++ b/test @@ -4,2337 +4,2339 @@ :vpi_module "system"; :vpi_module "v2005_math"; :vpi_module "va_math"; -S_0x18c7e50 .scope module, "test32Adder" "test32Adder" 2 122; - .timescale -9 -12; -P_0x181c268 .param/l "size" 2 123, +C4<0100>; -v0x1929e30_0 .var "A", 3 0; -RS_0x7f644c9d4be8/0/0 .resolv tri, L_0x192b620, L_0x192cd10, L_0x192e250, L_0x192f850; -RS_0x7f644c9d4be8/0/4 .resolv tri, L_0x19417d0, L_0x1942bf0, L_0x1943ff0, L_0x19455d0; -RS_0x7f644c9d4be8 .resolv tri, RS_0x7f644c9d4be8/0/0, RS_0x7f644c9d4be8/0/4, C4, C4; -v0x1929eb0_0 .net8 "AddSubSLTSum", 3 0, RS_0x7f644c9d4be8; 8 drivers -v0x1929f30_0 .net "AllZeros", 0 0, L_0x1950e20; 1 drivers -RS_0x7f644c9d3e38/0/0 .resolv tri, L_0x1931800, L_0x19322b0, L_0x1932d20, L_0x1933780; -RS_0x7f644c9d3e38/0/4 .resolv tri, L_0x1947400, L_0x1947e70, L_0x19488e0, L_0x1949440; -RS_0x7f644c9d3e38 .resolv tri, RS_0x7f644c9d3e38/0/0, RS_0x7f644c9d3e38/0/4, C4, C4; -v0x1929fb0_0 .net8 "AndNandOut", 3 0, RS_0x7f644c9d3e38; 8 drivers -v0x192a030_0 .var "B", 3 0; -v0x192a0b0_0 .var "Command", 2 0; -RS_0x7f644c9d5068 .resolv tri, L_0x193a870, L_0x193d600, L_0x1940230, L_0x1950290; -v0x192a130_0 .net8 "OneBitFinalOut", 3 0, RS_0x7f644c9d5068; 4 drivers -RS_0x7f644c9d3748/0/0 .resolv tri, L_0x1934ad0, L_0x1936030, L_0x1937250, L_0x1938360; -RS_0x7f644c9d3748/0/4 .resolv tri, L_0x194a790, L_0x194ba90, L_0x194cd90, L_0x194e080; -RS_0x7f644c9d3748 .resolv tri, RS_0x7f644c9d3748/0/0, RS_0x7f644c9d3748/0/4, C4, C4; -v0x192a1b0_0 .net8 "OrNorXorOut", 3 0, RS_0x7f644c9d3748; 8 drivers -RS_0x7f644c9d4ca8 .resolv tri, L_0x1930e80, L_0x1946aa0, C4, C4; -v0x192a230_0 .net8 "SLTflag", 0 0, RS_0x7f644c9d4ca8; 2 drivers -RS_0x7f644c9d5098 .resolv tri, L_0x193ad20, L_0x193dad0, L_0x1940370, L_0x1950550; -v0x192a2b0_0 .net8 "ZeroFlag", 3 0, RS_0x7f644c9d5098; 4 drivers -v0x192a330_0 .var "carryin", 3 0; -RS_0x7f644c9d4ee8 .resolv tri, L_0x192b900, L_0x1945950, C4, C4; -v0x192a3b0_0 .net8 "carryout", 0 0, RS_0x7f644c9d4ee8; 2 drivers -RS_0x7f644c9d4f78 .resolv tri, L_0x1930150, L_0x1945dc0, C4, C4; -v0x192a430_0 .net8 "overflow", 0 0, RS_0x7f644c9d4f78; 2 drivers -RS_0x7f644c9d4fa8/0/0 .resolv tri, L_0x192b860, L_0x192cf40, L_0x192e4b0, L_0x192e8a0; -RS_0x7f644c9d4fa8/0/4 .resolv tri, L_0x19419b0, L_0x1942e20, L_0x1944250, L_0x1944640; -RS_0x7f644c9d4fa8 .resolv tri, RS_0x7f644c9d4fa8/0/0, RS_0x7f644c9d4fa8/0/4, C4, C4; -v0x192a4b0_0 .net8 "subtract", 3 0, RS_0x7f644c9d4fa8; 8 drivers -S_0x19246c0 .scope module, "trial" "AddSubSLT32" 2 141, 3 205, S_0x18c7e50; - .timescale -9 -12; -P_0x19247b8 .param/l "size" 3 228, +C4<0100>; -L_0x192b900/d .functor OR 1, L_0x192ffa0, C4<0>, C4<0>, C4<0>; -L_0x192b900 .delay (20000,20000,20000) L_0x192b900/d; -L_0x1930150/d .functor XOR 1, RS_0x7f644c9d4ee8, L_0x1930280, C4<0>, C4<0>; -L_0x1930150 .delay (40000,40000,40000) L_0x1930150/d; -L_0x192fed0/d .functor AND 1, L_0x1930450, L_0x19304f0, C4<1>, C4<1>; -L_0x192fed0 .delay (20000,20000,20000) L_0x192fed0/d; -L_0x1930320/d .functor NOT 1, RS_0x7f644c9d4f78, C4<0>, C4<0>, C4<0>; -L_0x1930320 .delay (10000,10000,10000) L_0x1930320/d; -L_0x1930720/d .functor NOT 1, L_0x1930780, C4<0>, C4<0>, C4<0>; -L_0x1930720 .delay (10000,10000,10000) L_0x1930720/d; -L_0x192b6c0/d .functor AND 1, L_0x1930320, L_0x1930a50, C4<1>, C4<1>; -L_0x192b6c0 .delay (20000,20000,20000) L_0x192b6c0/d; -L_0x19305e0/d .functor AND 1, RS_0x7f644c9d4f78, L_0x1930720, C4<1>, C4<1>; -L_0x19305e0 .delay (20000,20000,20000) L_0x19305e0/d; -L_0x1930c40/d .functor AND 1, L_0x192b6c0, L_0x192fed0, C4<1>, C4<1>; -L_0x1930c40 .delay (20000,20000,20000) L_0x1930c40/d; -L_0x1930d80/d .functor AND 1, L_0x19305e0, L_0x192fed0, C4<1>, C4<1>; -L_0x1930d80 .delay (20000,20000,20000) L_0x1930d80/d; -L_0x1930e80/d .functor OR 1, L_0x1930c40, L_0x1930d80, C4<0>, C4<0>; -L_0x1930e80 .delay (20000,20000,20000) L_0x1930e80/d; -v0x1928d50_0 .net "A", 3 0, v0x1929e30_0; 1 drivers -v0x1928df0_0 .alias "AddSubSLTSum", 3 0, v0x1929eb0_0; -v0x1928e70_0 .net "B", 3 0, v0x192a030_0; 1 drivers -RS_0x7f644c9d7348 .resolv tri, L_0x192b770, L_0x192ce00, L_0x192e340, L_0x192f940; -v0x1928ef0_0 .net8 "CarryoutWire", 3 0, RS_0x7f644c9d7348; 4 drivers -v0x1928f70_0 .net "Command", 2 0, v0x192a0b0_0; 1 drivers -v0x1928ff0_0 .net "Res0OF1", 0 0, L_0x19305e0; 1 drivers -v0x1929090_0 .net "Res1OF0", 0 0, L_0x192b6c0; 1 drivers -v0x1929130_0 .alias "SLTflag", 0 0, v0x192a230_0; -v0x1929250_0 .net "SLTflag0", 0 0, L_0x1930c40; 1 drivers -v0x19292f0_0 .net "SLTflag1", 0 0, L_0x1930d80; 1 drivers -v0x1929390_0 .net "SLTon", 0 0, L_0x192fed0; 1 drivers -v0x1929430_0 .net *"_s40", 0 0, L_0x192ffa0; 1 drivers -v0x19294d0_0 .net/s *"_s41", 0 0, C4<0>; 1 drivers -v0x1929570_0 .net *"_s44", 0 0, L_0x1930280; 1 drivers -v0x1929690_0 .net *"_s46", 0 0, L_0x1930450; 1 drivers -v0x1929730_0 .net *"_s48", 0 0, L_0x19304f0; 1 drivers -v0x19295f0_0 .net *"_s50", 0 0, L_0x1930780; 1 drivers -v0x1929880_0 .net *"_s52", 0 0, L_0x1930a50; 1 drivers -v0x19299a0_0 .net "carryin", 3 0, v0x192a330_0; 1 drivers -v0x1929a20_0 .alias "carryout", 0 0, v0x192a3b0_0; -v0x1929900_0 .net "nAddSubSLTSum", 0 0, L_0x1930720; 1 drivers -v0x1929b50_0 .net "nOF", 0 0, L_0x1930320; 1 drivers -v0x1929aa0_0 .alias "overflow", 0 0, v0x192a430_0; -v0x1929ce0_0 .alias "subtract", 3 0, v0x192a4b0_0; -L_0x192b620 .part/pv L_0x192b190, 1, 1, 4; -L_0x192b770 .part/pv L_0x192b4e0, 1, 1, 4; -L_0x192b860 .part/pv L_0x191d6c0, 1, 1, 4; -L_0x192b990 .part v0x1929e30_0, 1, 1; -L_0x192bb40 .part v0x192a030_0, 1, 1; -L_0x192bcf0 .part RS_0x7f644c9d7348, 0, 1; -L_0x192cd10 .part/pv L_0x192c840, 2, 1, 4; -L_0x192ce00 .part/pv L_0x192cbb0, 2, 1, 4; -L_0x192cf40 .part/pv L_0x192c570, 2, 1, 4; -L_0x192d030 .part v0x1929e30_0, 2, 1; -L_0x192d130 .part v0x192a030_0, 2, 1; -L_0x192d260 .part RS_0x7f644c9d7348, 1, 1; -L_0x192e250 .part/pv L_0x192dda0, 3, 1, 4; -L_0x192e340 .part/pv L_0x192e0f0, 3, 1, 4; -L_0x192e4b0 .part/pv L_0x192dad0, 3, 1, 4; -L_0x192e5a0 .part v0x1929e30_0, 3, 1; -L_0x192e6d0 .part v0x192a030_0, 3, 1; -L_0x192e800 .part RS_0x7f644c9d7348, 2, 1; -L_0x192f850 .part/pv L_0x192f3a0, 0, 1, 4; -L_0x192f940 .part/pv L_0x192f6f0, 0, 1, 4; -L_0x192e8a0 .part/pv L_0x192f0d0, 0, 1, 4; -L_0x192fb30 .part v0x1929e30_0, 0, 1; -L_0x192fa30 .part v0x192a030_0, 0, 1; -L_0x192fd20 .part RS_0x7f644c9d4fa8, 0, 1; -L_0x192ffa0 .part RS_0x7f644c9d7348, 3, 1; -L_0x1930280 .part RS_0x7f644c9d7348, 2, 1; -L_0x1930450 .part v0x192a0b0_0, 1, 1; -L_0x19304f0 .part RS_0x7f644c9d4fa8, 0, 1; -L_0x1930780 .part RS_0x7f644c9d4be8, 3, 1; -L_0x1930a50 .part RS_0x7f644c9d4be8, 3, 1; -S_0x1927d40 .scope module, "attempt2" "MiddleAddSubSLT" 3 225, 3 89, S_0x19246c0; - .timescale -9 -12; -L_0x192e640/d .functor NOT 1, L_0x192fa30, C4<0>, C4<0>, C4<0>; -L_0x192e640 .delay (10000,10000,10000) L_0x192e640/d; -L_0x192ef70/d .functor NOT 1, L_0x192f030, C4<0>, C4<0>, C4<0>; -L_0x192ef70 .delay (10000,10000,10000) L_0x192ef70/d; -L_0x192f0d0/d .functor AND 1, L_0x192f210, L_0x192ef70, C4<1>, C4<1>; -L_0x192f0d0 .delay (20000,20000,20000) L_0x192f0d0/d; -L_0x192f2b0/d .functor XOR 1, L_0x192fb30, L_0x192ed00, C4<0>, C4<0>; -L_0x192f2b0 .delay (40000,40000,40000) L_0x192f2b0/d; -L_0x192f3a0/d .functor XOR 1, L_0x192f2b0, L_0x192fd20, C4<0>, C4<0>; -L_0x192f3a0 .delay (40000,40000,40000) L_0x192f3a0/d; -L_0x192f490/d .functor AND 1, L_0x192fb30, L_0x192ed00, C4<1>, C4<1>; -L_0x192f490 .delay (20000,20000,20000) L_0x192f490/d; -L_0x192f600/d .functor AND 1, L_0x192f2b0, L_0x192fd20, C4<1>, C4<1>; -L_0x192f600 .delay (20000,20000,20000) L_0x192f600/d; -L_0x192f6f0/d .functor OR 1, L_0x192f490, L_0x192f600, C4<0>, C4<0>; -L_0x192f6f0 .delay (20000,20000,20000) L_0x192f6f0/d; -v0x19283b0_0 .net "A", 0 0, L_0x192fb30; 1 drivers -v0x1928470_0 .net "AandB", 0 0, L_0x192f490; 1 drivers -v0x1928510_0 .net "AddSubSLTSum", 0 0, L_0x192f3a0; 1 drivers -v0x19285b0_0 .net "AxorB", 0 0, L_0x192f2b0; 1 drivers -v0x1928630_0 .net "B", 0 0, L_0x192fa30; 1 drivers -v0x19286e0_0 .net "BornB", 0 0, L_0x192ed00; 1 drivers -v0x19287a0_0 .net "CINandAxorB", 0 0, L_0x192f600; 1 drivers -v0x1928820_0 .alias "Command", 2 0, v0x1928f70_0; -v0x19288a0_0 .net *"_s3", 0 0, L_0x192f030; 1 drivers -v0x1928920_0 .net *"_s5", 0 0, L_0x192f210; 1 drivers -v0x19289c0_0 .net "carryin", 0 0, L_0x192fd20; 1 drivers -v0x1928a60_0 .net "carryout", 0 0, L_0x192f6f0; 1 drivers -v0x1928b00_0 .net "nB", 0 0, L_0x192e640; 1 drivers -v0x1928bb0_0 .net "nCmd2", 0 0, L_0x192ef70; 1 drivers -v0x1928cb0_0 .net "subtract", 0 0, L_0x192f0d0; 1 drivers -L_0x192eed0 .part v0x192a0b0_0, 0, 1; -L_0x192f030 .part v0x192a0b0_0, 2, 1; -L_0x192f210 .part v0x192a0b0_0, 0, 1; -S_0x1927e30 .scope module, "mux0" "TwoInMux" 3 105, 3 8, S_0x1927d40; - .timescale -9 -12; -L_0x192ea20/d .functor NOT 1, L_0x192eed0, C4<0>, C4<0>, C4<0>; -L_0x192ea20 .delay (10000,10000,10000) L_0x192ea20/d; -L_0x192eae0/d .functor AND 1, L_0x192fa30, L_0x192ea20, C4<1>, C4<1>; -L_0x192eae0 .delay (20000,20000,20000) L_0x192eae0/d; -L_0x192ebf0/d .functor AND 1, L_0x192e640, L_0x192eed0, C4<1>, C4<1>; -L_0x192ebf0 .delay (20000,20000,20000) L_0x192ebf0/d; -L_0x192ed00/d .functor OR 1, L_0x192eae0, L_0x192ebf0, C4<0>, C4<0>; -L_0x192ed00 .delay (20000,20000,20000) L_0x192ed00/d; -v0x1927f20_0 .net "S", 0 0, L_0x192eed0; 1 drivers -v0x1927fe0_0 .alias "in0", 0 0, v0x1928630_0; -v0x1928080_0 .alias "in1", 0 0, v0x1928b00_0; -v0x1928120_0 .net "nS", 0 0, L_0x192ea20; 1 drivers -v0x19281d0_0 .net "out0", 0 0, L_0x192eae0; 1 drivers -v0x1928270_0 .net "out1", 0 0, L_0x192ebf0; 1 drivers -v0x1928310_0 .alias "outfinal", 0 0, v0x19286e0_0; -S_0x1926ba0 .scope generate, "addbits[1]" "addbits[1]" 3 230, 3 230, S_0x19246c0; - .timescale -9 -12; -P_0x19265b8 .param/l "i" 3 230, +C4<01>; -S_0x1926d10 .scope module, "attempt" "MiddleAddSubSLT" 3 232, 3 89, S_0x1926ba0; - .timescale -9 -12; -L_0x19255f0/d .functor NOT 1, L_0x192bb40, C4<0>, C4<0>, C4<0>; -L_0x19255f0 .delay (10000,10000,10000) L_0x19255f0/d; -L_0x1929c20/d .functor NOT 1, L_0x191d620, C4<0>, C4<0>, C4<0>; -L_0x1929c20 .delay (10000,10000,10000) L_0x1929c20/d; -L_0x191d6c0/d .functor AND 1, L_0x192b000, L_0x1929c20, C4<1>, C4<1>; -L_0x191d6c0 .delay (20000,20000,20000) L_0x191d6c0/d; -L_0x192b0a0/d .functor XOR 1, L_0x192b990, L_0x192a980, C4<0>, C4<0>; -L_0x192b0a0 .delay (40000,40000,40000) L_0x192b0a0/d; -L_0x192b190/d .functor XOR 1, L_0x192b0a0, L_0x192bcf0, C4<0>, C4<0>; -L_0x192b190 .delay (40000,40000,40000) L_0x192b190/d; -L_0x192b280/d .functor AND 1, L_0x192b990, L_0x192a980, C4<1>, C4<1>; -L_0x192b280 .delay (20000,20000,20000) L_0x192b280/d; -L_0x192b3f0/d .functor AND 1, L_0x192b0a0, L_0x192bcf0, C4<1>, C4<1>; -L_0x192b3f0 .delay (20000,20000,20000) L_0x192b3f0/d; -L_0x192b4e0/d .functor OR 1, L_0x192b280, L_0x192b3f0, C4<0>, C4<0>; -L_0x192b4e0 .delay (20000,20000,20000) L_0x192b4e0/d; -v0x19273a0_0 .net "A", 0 0, L_0x192b990; 1 drivers -v0x1927460_0 .net "AandB", 0 0, L_0x192b280; 1 drivers -v0x1927500_0 .net "AddSubSLTSum", 0 0, L_0x192b190; 1 drivers -v0x19275a0_0 .net "AxorB", 0 0, L_0x192b0a0; 1 drivers -v0x1927620_0 .net "B", 0 0, L_0x192bb40; 1 drivers -v0x19276d0_0 .net "BornB", 0 0, L_0x192a980; 1 drivers -v0x1927790_0 .net "CINandAxorB", 0 0, L_0x192b3f0; 1 drivers -v0x1927810_0 .alias "Command", 2 0, v0x1928f70_0; -v0x1927890_0 .net *"_s3", 0 0, L_0x191d620; 1 drivers -v0x1927910_0 .net *"_s5", 0 0, L_0x192b000; 1 drivers -v0x19279b0_0 .net "carryin", 0 0, L_0x192bcf0; 1 drivers -v0x1927a50_0 .net "carryout", 0 0, L_0x192b4e0; 1 drivers -v0x1927af0_0 .net "nB", 0 0, L_0x19255f0; 1 drivers -v0x1927ba0_0 .net "nCmd2", 0 0, L_0x1929c20; 1 drivers -v0x1927ca0_0 .net "subtract", 0 0, L_0x191d6c0; 1 drivers -L_0x192ab50 .part v0x192a0b0_0, 0, 1; -L_0x191d620 .part v0x192a0b0_0, 2, 1; -L_0x192b000 .part v0x192a0b0_0, 0, 1; -S_0x1926e00 .scope module, "mux0" "TwoInMux" 3 105, 3 8, S_0x1926d10; - .timescale -9 -12; -L_0x192a6a0/d .functor NOT 1, L_0x192ab50, C4<0>, C4<0>, C4<0>; -L_0x192a6a0 .delay (10000,10000,10000) L_0x192a6a0/d; -L_0x192a760/d .functor AND 1, L_0x192bb40, L_0x192a6a0, C4<1>, C4<1>; -L_0x192a760 .delay (20000,20000,20000) L_0x192a760/d; -L_0x192a870/d .functor AND 1, L_0x19255f0, L_0x192ab50, C4<1>, C4<1>; -L_0x192a870 .delay (20000,20000,20000) L_0x192a870/d; -L_0x192a980/d .functor OR 1, L_0x192a760, L_0x192a870, C4<0>, C4<0>; -L_0x192a980 .delay (20000,20000,20000) L_0x192a980/d; -v0x1926ef0_0 .net "S", 0 0, L_0x192ab50; 1 drivers -v0x1926f90_0 .alias "in0", 0 0, v0x1927620_0; -v0x1927030_0 .alias "in1", 0 0, v0x1927af0_0; -v0x19270d0_0 .net "nS", 0 0, L_0x192a6a0; 1 drivers -v0x1927180_0 .net "out0", 0 0, L_0x192a760; 1 drivers -v0x1927220_0 .net "out1", 0 0, L_0x192a870; 1 drivers -v0x1927300_0 .alias "outfinal", 0 0, v0x19276d0_0; -S_0x1925a00 .scope generate, "addbits[2]" "addbits[2]" 3 230, 3 230, S_0x19246c0; - .timescale -9 -12; -P_0x19253b8 .param/l "i" 3 230, +C4<010>; -S_0x1925b70 .scope module, "attempt" "MiddleAddSubSLT" 3 232, 3 89, S_0x1925a00; - .timescale -9 -12; -L_0x1921470/d .functor NOT 1, L_0x192d130, C4<0>, C4<0>, C4<0>; -L_0x1921470 .delay (10000,10000,10000) L_0x1921470/d; -L_0x192c410/d .functor NOT 1, L_0x192c4d0, C4<0>, C4<0>, C4<0>; -L_0x192c410 .delay (10000,10000,10000) L_0x192c410/d; -L_0x192c570/d .functor AND 1, L_0x192c6b0, L_0x192c410, C4<1>, C4<1>; -L_0x192c570 .delay (20000,20000,20000) L_0x192c570/d; -L_0x192c750/d .functor XOR 1, L_0x192d030, L_0x192c1a0, C4<0>, C4<0>; -L_0x192c750 .delay (40000,40000,40000) L_0x192c750/d; -L_0x192c840/d .functor XOR 1, L_0x192c750, L_0x192d260, C4<0>, C4<0>; -L_0x192c840 .delay (40000,40000,40000) L_0x192c840/d; -L_0x192c930/d .functor AND 1, L_0x192d030, L_0x192c1a0, C4<1>, C4<1>; -L_0x192c930 .delay (20000,20000,20000) L_0x192c930/d; -L_0x192caa0/d .functor AND 1, L_0x192c750, L_0x192d260, C4<1>, C4<1>; -L_0x192caa0 .delay (20000,20000,20000) L_0x192caa0/d; -L_0x192cbb0/d .functor OR 1, L_0x192c930, L_0x192caa0, C4<0>, C4<0>; -L_0x192cbb0 .delay (20000,20000,20000) L_0x192cbb0/d; -v0x1926200_0 .net "A", 0 0, L_0x192d030; 1 drivers -v0x19262c0_0 .net "AandB", 0 0, L_0x192c930; 1 drivers -v0x1926360_0 .net "AddSubSLTSum", 0 0, L_0x192c840; 1 drivers -v0x1926400_0 .net "AxorB", 0 0, L_0x192c750; 1 drivers -v0x1926480_0 .net "B", 0 0, L_0x192d130; 1 drivers -v0x1926530_0 .net "BornB", 0 0, L_0x192c1a0; 1 drivers -v0x19265f0_0 .net "CINandAxorB", 0 0, L_0x192caa0; 1 drivers -v0x1926670_0 .alias "Command", 2 0, v0x1928f70_0; -v0x19266f0_0 .net *"_s3", 0 0, L_0x192c4d0; 1 drivers -v0x1926770_0 .net *"_s5", 0 0, L_0x192c6b0; 1 drivers -v0x1926810_0 .net "carryin", 0 0, L_0x192d260; 1 drivers -v0x19268b0_0 .net "carryout", 0 0, L_0x192cbb0; 1 drivers -v0x1926950_0 .net "nB", 0 0, L_0x1921470; 1 drivers -v0x1926a00_0 .net "nCmd2", 0 0, L_0x192c410; 1 drivers -v0x1926b00_0 .net "subtract", 0 0, L_0x192c570; 1 drivers -L_0x192c370 .part v0x192a0b0_0, 0, 1; -L_0x192c4d0 .part v0x192a0b0_0, 2, 1; -L_0x192c6b0 .part v0x192a0b0_0, 0, 1; -S_0x1925c60 .scope module, "mux0" "TwoInMux" 3 105, 3 8, S_0x1925b70; - .timescale -9 -12; -L_0x192bec0/d .functor NOT 1, L_0x192c370, C4<0>, C4<0>, C4<0>; -L_0x192bec0 .delay (10000,10000,10000) L_0x192bec0/d; -L_0x192bf80/d .functor AND 1, L_0x192d130, L_0x192bec0, C4<1>, C4<1>; -L_0x192bf80 .delay (20000,20000,20000) L_0x192bf80/d; -L_0x192c090/d .functor AND 1, L_0x1921470, L_0x192c370, C4<1>, C4<1>; -L_0x192c090 .delay (20000,20000,20000) L_0x192c090/d; -L_0x192c1a0/d .functor OR 1, L_0x192bf80, L_0x192c090, C4<0>, C4<0>; -L_0x192c1a0 .delay (20000,20000,20000) L_0x192c1a0/d; -v0x1925d50_0 .net "S", 0 0, L_0x192c370; 1 drivers -v0x1925df0_0 .alias "in0", 0 0, v0x1926480_0; -v0x1925e90_0 .alias "in1", 0 0, v0x1926950_0; -v0x1925f30_0 .net "nS", 0 0, L_0x192bec0; 1 drivers -v0x1925fe0_0 .net "out0", 0 0, L_0x192bf80; 1 drivers -v0x1926080_0 .net "out1", 0 0, L_0x192c090; 1 drivers -v0x1926160_0 .alias "outfinal", 0 0, v0x1926530_0; -S_0x1924830 .scope generate, "addbits[3]" "addbits[3]" 3 230, 3 230, S_0x19246c0; - .timescale -9 -12; -P_0x1924928 .param/l "i" 3 230, +C4<011>; -S_0x19249a0 .scope module, "attempt" "MiddleAddSubSLT" 3 232, 3 89, S_0x1924830; - .timescale -9 -12; -L_0x192d0d0/d .functor NOT 1, L_0x192e6d0, C4<0>, C4<0>, C4<0>; -L_0x192d0d0 .delay (10000,10000,10000) L_0x192d0d0/d; -L_0x192d970/d .functor NOT 1, L_0x192da30, C4<0>, C4<0>, C4<0>; -L_0x192d970 .delay (10000,10000,10000) L_0x192d970/d; -L_0x192dad0/d .functor AND 1, L_0x192dc10, L_0x192d970, C4<1>, C4<1>; -L_0x192dad0 .delay (20000,20000,20000) L_0x192dad0/d; -L_0x192dcb0/d .functor XOR 1, L_0x192e5a0, L_0x192d700, C4<0>, C4<0>; -L_0x192dcb0 .delay (40000,40000,40000) L_0x192dcb0/d; -L_0x192dda0/d .functor XOR 1, L_0x192dcb0, L_0x192e800, C4<0>, C4<0>; -L_0x192dda0 .delay (40000,40000,40000) L_0x192dda0/d; -L_0x192de90/d .functor AND 1, L_0x192e5a0, L_0x192d700, C4<1>, C4<1>; -L_0x192de90 .delay (20000,20000,20000) L_0x192de90/d; -L_0x192e000/d .functor AND 1, L_0x192dcb0, L_0x192e800, C4<1>, C4<1>; -L_0x192e000 .delay (20000,20000,20000) L_0x192e000/d; -L_0x192e0f0/d .functor OR 1, L_0x192de90, L_0x192e000, C4<0>, C4<0>; -L_0x192e0f0 .delay (20000,20000,20000) L_0x192e0f0/d; -v0x1925000_0 .net "A", 0 0, L_0x192e5a0; 1 drivers -v0x19250c0_0 .net "AandB", 0 0, L_0x192de90; 1 drivers -v0x1925160_0 .net "AddSubSLTSum", 0 0, L_0x192dda0; 1 drivers -v0x1925200_0 .net "AxorB", 0 0, L_0x192dcb0; 1 drivers -v0x1925280_0 .net "B", 0 0, L_0x192e6d0; 1 drivers -v0x1925330_0 .net "BornB", 0 0, L_0x192d700; 1 drivers -v0x19253f0_0 .net "CINandAxorB", 0 0, L_0x192e000; 1 drivers -v0x1925470_0 .alias "Command", 2 0, v0x1928f70_0; -v0x19254f0_0 .net *"_s3", 0 0, L_0x192da30; 1 drivers -v0x1925570_0 .net *"_s5", 0 0, L_0x192dc10; 1 drivers -v0x1925670_0 .net "carryin", 0 0, L_0x192e800; 1 drivers -v0x1925710_0 .net "carryout", 0 0, L_0x192e0f0; 1 drivers -v0x19257b0_0 .net "nB", 0 0, L_0x192d0d0; 1 drivers -v0x1925860_0 .net "nCmd2", 0 0, L_0x192d970; 1 drivers -v0x1925960_0 .net "subtract", 0 0, L_0x192dad0; 1 drivers -L_0x192d8d0 .part v0x192a0b0_0, 0, 1; -L_0x192da30 .part v0x192a0b0_0, 2, 1; -L_0x192dc10 .part v0x192a0b0_0, 0, 1; -S_0x1924a90 .scope module, "mux0" "TwoInMux" 3 105, 3 8, S_0x19249a0; - .timescale -9 -12; -L_0x192d460/d .functor NOT 1, L_0x192d8d0, C4<0>, C4<0>, C4<0>; -L_0x192d460 .delay (10000,10000,10000) L_0x192d460/d; -L_0x192d4e0/d .functor AND 1, L_0x192e6d0, L_0x192d460, C4<1>, C4<1>; -L_0x192d4e0 .delay (20000,20000,20000) L_0x192d4e0/d; -L_0x192d5f0/d .functor AND 1, L_0x192d0d0, L_0x192d8d0, C4<1>, C4<1>; -L_0x192d5f0 .delay (20000,20000,20000) L_0x192d5f0/d; -L_0x192d700/d .functor OR 1, L_0x192d4e0, L_0x192d5f0, C4<0>, C4<0>; -L_0x192d700 .delay (20000,20000,20000) L_0x192d700/d; -v0x1924b80_0 .net "S", 0 0, L_0x192d8d0; 1 drivers -v0x1924c20_0 .alias "in0", 0 0, v0x1925280_0; -v0x1924cc0_0 .alias "in1", 0 0, v0x19257b0_0; -v0x1924d60_0 .net "nS", 0 0, L_0x192d460; 1 drivers -v0x1924de0_0 .net "out0", 0 0, L_0x192d4e0; 1 drivers -v0x1924e80_0 .net "out1", 0 0, L_0x192d5f0; 1 drivers -v0x1924f60_0 .alias "outfinal", 0 0, v0x1925330_0; -S_0x1921600 .scope module, "trial1" "AndNand32" 2 143, 3 154, S_0x18c7e50; - .timescale -9 -12; -P_0x1920ff8 .param/l "size" 3 161, +C4<0100>; -v0x19244c0_0 .alias "A", 3 0, v0x1928d50_0; -v0x1924540_0 .alias "AndNandOut", 3 0, v0x1929fb0_0; -v0x19245c0_0 .alias "B", 3 0, v0x1928e70_0; -v0x1924640_0 .alias "Command", 2 0, v0x1928f70_0; -L_0x1931800 .part/pv L_0x1931590, 1, 1, 4; -L_0x1931950 .part v0x1929e30_0, 1, 1; -L_0x19319f0 .part v0x192a030_0, 1, 1; -L_0x19322b0 .part/pv L_0x1932040, 2, 1, 4; -L_0x1932350 .part v0x1929e30_0, 2, 1; -L_0x19323f0 .part v0x192a030_0, 2, 1; -L_0x1932d20 .part/pv L_0x1932ab0, 3, 1, 4; -L_0x1932dc0 .part v0x1929e30_0, 3, 1; -L_0x1932eb0 .part v0x192a030_0, 3, 1; -L_0x1933780 .part/pv L_0x1933510, 0, 1, 4; -L_0x1933880 .part v0x1929e30_0, 0, 1; -L_0x1933920 .part v0x192a030_0, 0, 1; -S_0x1923a90 .scope module, "attempt2" "AndNand" 3 165, 3 48, S_0x1921600; - .timescale -9 -12; -L_0x1932fa0/d .functor NAND 1, L_0x1933880, L_0x1933920, C4<1>, C4<1>; -L_0x1932fa0 .delay (10000,10000,10000) L_0x1932fa0/d; -L_0x19330c0/d .functor NOT 1, L_0x1932fa0, C4<0>, C4<0>, C4<0>; -L_0x19330c0 .delay (10000,10000,10000) L_0x19330c0/d; -v0x19240b0_0 .net "A", 0 0, L_0x1933880; 1 drivers -v0x1924170_0 .net "AandB", 0 0, L_0x19330c0; 1 drivers -v0x19241f0_0 .net "AnandB", 0 0, L_0x1932fa0; 1 drivers -v0x19242a0_0 .net "AndNandOut", 0 0, L_0x1933510; 1 drivers -v0x1924380_0 .net "B", 0 0, L_0x1933920; 1 drivers -v0x1924400_0 .alias "Command", 2 0, v0x1928f70_0; -L_0x19336e0 .part v0x192a0b0_0, 0, 1; -S_0x1923b80 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0x1923a90; - .timescale -9 -12; -L_0x19331f0/d .functor NOT 1, L_0x19336e0, C4<0>, C4<0>, C4<0>; -L_0x19331f0 .delay (10000,10000,10000) L_0x19331f0/d; -L_0x19332b0/d .functor AND 1, L_0x19330c0, L_0x19331f0, C4<1>, C4<1>; -L_0x19332b0 .delay (20000,20000,20000) L_0x19332b0/d; -L_0x19333c0/d .functor AND 1, L_0x1932fa0, L_0x19336e0, C4<1>, C4<1>; -L_0x19333c0 .delay (20000,20000,20000) L_0x19333c0/d; -L_0x1933510/d .functor OR 1, L_0x19332b0, L_0x19333c0, C4<0>, C4<0>; -L_0x1933510 .delay (20000,20000,20000) L_0x1933510/d; -v0x1923c70_0 .net "S", 0 0, L_0x19336e0; 1 drivers -v0x1923cf0_0 .alias "in0", 0 0, v0x1924170_0; -v0x1923d70_0 .alias "in1", 0 0, v0x19241f0_0; -v0x1923e10_0 .net "nS", 0 0, L_0x19331f0; 1 drivers -v0x1923e90_0 .net "out0", 0 0, L_0x19332b0; 1 drivers -v0x1923f30_0 .net "out1", 0 0, L_0x19333c0; 1 drivers -v0x1924010_0 .alias "outfinal", 0 0, v0x19242a0_0; -S_0x1922ed0 .scope generate, "andbits[1]" "andbits[1]" 3 169, 3 169, S_0x1921600; - .timescale -9 -12; -P_0x1922fc8 .param/l "i" 3 169, +C4<01>; -S_0x1923040 .scope module, "attempt" "AndNand" 3 171, 3 48, S_0x1922ed0; - .timescale -9 -12; -L_0x1931080/d .functor NAND 1, L_0x1931950, L_0x19319f0, C4<1>, C4<1>; -L_0x1931080 .delay (10000,10000,10000) L_0x1931080/d; -L_0x1931140/d .functor NOT 1, L_0x1931080, C4<0>, C4<0>, C4<0>; -L_0x1931140 .delay (10000,10000,10000) L_0x1931140/d; -v0x1923680_0 .net "A", 0 0, L_0x1931950; 1 drivers -v0x1923740_0 .net "AandB", 0 0, L_0x1931140; 1 drivers -v0x19237c0_0 .net "AnandB", 0 0, L_0x1931080; 1 drivers -v0x1923870_0 .net "AndNandOut", 0 0, L_0x1931590; 1 drivers -v0x1923950_0 .net "B", 0 0, L_0x19319f0; 1 drivers -v0x19239d0_0 .alias "Command", 2 0, v0x1928f70_0; -L_0x1931760 .part v0x192a0b0_0, 0, 1; -S_0x1923130 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0x1923040; - .timescale -9 -12; -L_0x1931270/d .functor NOT 1, L_0x1931760, C4<0>, C4<0>, C4<0>; -L_0x1931270 .delay (10000,10000,10000) L_0x1931270/d; -L_0x1931330/d .functor AND 1, L_0x1931140, L_0x1931270, C4<1>, C4<1>; -L_0x1931330 .delay (20000,20000,20000) L_0x1931330/d; -L_0x1931440/d .functor AND 1, L_0x1931080, L_0x1931760, C4<1>, C4<1>; -L_0x1931440 .delay (20000,20000,20000) L_0x1931440/d; -L_0x1931590/d .functor OR 1, L_0x1931330, L_0x1931440, C4<0>, C4<0>; -L_0x1931590 .delay (20000,20000,20000) L_0x1931590/d; -v0x1923220_0 .net "S", 0 0, L_0x1931760; 1 drivers -v0x19232a0_0 .alias "in0", 0 0, v0x1923740_0; -v0x1923340_0 .alias "in1", 0 0, v0x19237c0_0; -v0x19233e0_0 .net "nS", 0 0, L_0x1931270; 1 drivers -v0x1923460_0 .net "out0", 0 0, L_0x1931330; 1 drivers -v0x1923500_0 .net "out1", 0 0, L_0x1931440; 1 drivers -v0x19235e0_0 .alias "outfinal", 0 0, v0x1923870_0; -S_0x1922310 .scope generate, "andbits[2]" "andbits[2]" 3 169, 3 169, S_0x1921600; - .timescale -9 -12; -P_0x1922408 .param/l "i" 3 169, +C4<010>; -S_0x1922480 .scope module, "attempt" "AndNand" 3 171, 3 48, S_0x1922310; - .timescale -9 -12; -L_0x1931a90/d .functor NAND 1, L_0x1932350, L_0x19323f0, C4<1>, C4<1>; -L_0x1931a90 .delay (10000,10000,10000) L_0x1931a90/d; -L_0x1931bf0/d .functor NOT 1, L_0x1931a90, C4<0>, C4<0>, C4<0>; -L_0x1931bf0 .delay (10000,10000,10000) L_0x1931bf0/d; -v0x1922ac0_0 .net "A", 0 0, L_0x1932350; 1 drivers -v0x1922b80_0 .net "AandB", 0 0, L_0x1931bf0; 1 drivers -v0x1922c00_0 .net "AnandB", 0 0, L_0x1931a90; 1 drivers -v0x1922cb0_0 .net "AndNandOut", 0 0, L_0x1932040; 1 drivers -v0x1922d90_0 .net "B", 0 0, L_0x19323f0; 1 drivers -v0x1922e10_0 .alias "Command", 2 0, v0x1928f70_0; -L_0x1932210 .part v0x192a0b0_0, 0, 1; -S_0x1922570 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0x1922480; - .timescale -9 -12; -L_0x1931d20/d .functor NOT 1, L_0x1932210, C4<0>, C4<0>, C4<0>; -L_0x1931d20 .delay (10000,10000,10000) L_0x1931d20/d; -L_0x1931de0/d .functor AND 1, L_0x1931bf0, L_0x1931d20, C4<1>, C4<1>; -L_0x1931de0 .delay (20000,20000,20000) L_0x1931de0/d; -L_0x1931ef0/d .functor AND 1, L_0x1931a90, L_0x1932210, C4<1>, C4<1>; -L_0x1931ef0 .delay (20000,20000,20000) L_0x1931ef0/d; -L_0x1932040/d .functor OR 1, L_0x1931de0, L_0x1931ef0, C4<0>, C4<0>; -L_0x1932040 .delay (20000,20000,20000) L_0x1932040/d; -v0x1922660_0 .net "S", 0 0, L_0x1932210; 1 drivers -v0x19226e0_0 .alias "in0", 0 0, v0x1922b80_0; -v0x1922780_0 .alias "in1", 0 0, v0x1922c00_0; -v0x1922820_0 .net "nS", 0 0, L_0x1931d20; 1 drivers -v0x19228a0_0 .net "out0", 0 0, L_0x1931de0; 1 drivers -v0x1922940_0 .net "out1", 0 0, L_0x1931ef0; 1 drivers -v0x1922a20_0 .alias "outfinal", 0 0, v0x1922cb0_0; -S_0x1921730 .scope generate, "andbits[3]" "andbits[3]" 3 169, 3 169, S_0x1921600; - .timescale -9 -12; -P_0x1921828 .param/l "i" 3 169, +C4<011>; -S_0x19218a0 .scope module, "attempt" "AndNand" 3 171, 3 48, S_0x1921730; - .timescale -9 -12; -L_0x1932520/d .functor NAND 1, L_0x1932dc0, L_0x1932eb0, C4<1>, C4<1>; -L_0x1932520 .delay (10000,10000,10000) L_0x1932520/d; -L_0x1932660/d .functor NOT 1, L_0x1932520, C4<0>, C4<0>, C4<0>; -L_0x1932660 .delay (10000,10000,10000) L_0x1932660/d; -v0x1921f00_0 .net "A", 0 0, L_0x1932dc0; 1 drivers -v0x1921fc0_0 .net "AandB", 0 0, L_0x1932660; 1 drivers -v0x1922040_0 .net "AnandB", 0 0, L_0x1932520; 1 drivers -v0x19220f0_0 .net "AndNandOut", 0 0, L_0x1932ab0; 1 drivers -v0x19221d0_0 .net "B", 0 0, L_0x1932eb0; 1 drivers -v0x1922250_0 .alias "Command", 2 0, v0x1928f70_0; -L_0x1932c80 .part v0x192a0b0_0, 0, 1; -S_0x1921990 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0x19218a0; - .timescale -9 -12; -L_0x1932790/d .functor NOT 1, L_0x1932c80, C4<0>, C4<0>, C4<0>; -L_0x1932790 .delay (10000,10000,10000) L_0x1932790/d; -L_0x1932850/d .functor AND 1, L_0x1932660, L_0x1932790, C4<1>, C4<1>; -L_0x1932850 .delay (20000,20000,20000) L_0x1932850/d; -L_0x1932960/d .functor AND 1, L_0x1932520, L_0x1932c80, C4<1>, C4<1>; -L_0x1932960 .delay (20000,20000,20000) L_0x1932960/d; -L_0x1932ab0/d .functor OR 1, L_0x1932850, L_0x1932960, C4<0>, C4<0>; -L_0x1932ab0 .delay (20000,20000,20000) L_0x1932ab0/d; -v0x1921a80_0 .net "S", 0 0, L_0x1932c80; 1 drivers -v0x1921b20_0 .alias "in0", 0 0, v0x1921fc0_0; -v0x1921bc0_0 .alias "in1", 0 0, v0x1922040_0; -v0x1921c60_0 .net "nS", 0 0, L_0x1932790; 1 drivers -v0x1921ce0_0 .net "out0", 0 0, L_0x1932850; 1 drivers -v0x1921d80_0 .net "out1", 0 0, L_0x1932960; 1 drivers -v0x1921e60_0 .alias "outfinal", 0 0, v0x19220f0_0; -S_0x191c3a0 .scope module, "trial2" "OrNorXor32" 2 145, 3 177, S_0x18c7e50; - .timescale -9 -12; -P_0x1919dc8 .param/l "size" 3 184, +C4<0100>; -v0x19212e0_0 .alias "A", 3 0, v0x1928d50_0; -v0x19213f0_0 .alias "B", 3 0, v0x1928e70_0; -v0x1921500_0 .alias "Command", 2 0, v0x1928f70_0; -v0x1921580_0 .alias "OrNorXorOut", 3 0, v0x192a1b0_0; -L_0x1934ad0 .part/pv L_0x1934860, 1, 1, 4; -L_0x1934c00 .part v0x1929e30_0, 1, 1; -L_0x192ba30 .part v0x192a030_0, 1, 1; -L_0x1936030 .part/pv L_0x1935dc0, 2, 1, 4; -L_0x19360d0 .part v0x1929e30_0, 2, 1; -L_0x1936170 .part v0x192a030_0, 2, 1; -L_0x1937250 .part/pv L_0x1924320, 3, 1, 4; -L_0x19372f0 .part v0x1929e30_0, 3, 1; -L_0x1937390 .part v0x192a030_0, 3, 1; -L_0x1938360 .part/pv L_0x1938130, 0, 1, 4; -L_0x1938460 .part v0x1929e30_0, 0, 1; -L_0x1938500 .part v0x192a030_0, 0, 1; -S_0x19200a0 .scope module, "attempt2" "OrNorXor" 3 192, 3 64, S_0x191c3a0; - .timescale -9 -12; -L_0x1937430/d .functor NOR 1, L_0x1938460, L_0x1938500, C4<0>, C4<0>; -L_0x1937430 .delay (10000,10000,10000) L_0x1937430/d; -L_0x1937530/d .functor NOT 1, L_0x1937430, C4<0>, C4<0>, C4<0>; -L_0x1937530 .delay (10000,10000,10000) L_0x1937530/d; -L_0x1937620/d .functor NAND 1, L_0x1938460, L_0x1938500, C4<1>, C4<1>; -L_0x1937620 .delay (10000,10000,10000) L_0x1937620/d; -L_0x1937760/d .functor NAND 1, L_0x1937620, L_0x1937530, C4<1>, C4<1>; -L_0x1937760 .delay (10000,10000,10000) L_0x1937760/d; -L_0x1937850/d .functor NOT 1, L_0x1937760, C4<0>, C4<0>, C4<0>; -L_0x1937850 .delay (10000,10000,10000) L_0x1937850/d; -v0x1920bf0_0 .net "A", 0 0, L_0x1938460; 1 drivers -v0x1920c90_0 .net "AnandB", 0 0, L_0x1937620; 1 drivers -v0x1920d30_0 .net "AnorB", 0 0, L_0x1937430; 1 drivers -v0x1920de0_0 .net "AorB", 0 0, L_0x1937530; 1 drivers -v0x1920ec0_0 .net "AxorB", 0 0, L_0x1937850; 1 drivers -v0x1920f70_0 .net "B", 0 0, L_0x1938500; 1 drivers -v0x1921030_0 .alias "Command", 2 0, v0x1928f70_0; -v0x19210b0_0 .net "OrNorXorOut", 0 0, L_0x1938130; 1 drivers -v0x1921130_0 .net "XorNor", 0 0, L_0x1937c50; 1 drivers -v0x1921200_0 .net "nXor", 0 0, L_0x1937760; 1 drivers -L_0x1937d90 .part v0x192a0b0_0, 2, 1; -L_0x19382c0 .part v0x192a0b0_0, 0, 1; -S_0x1920680 .scope module, "mux0" "TwoInMux" 3 83, 3 8, S_0x19200a0; - .timescale -9 -12; -L_0x1937990/d .functor NOT 1, L_0x1937d90, C4<0>, C4<0>, C4<0>; -L_0x1937990 .delay (10000,10000,10000) L_0x1937990/d; -L_0x1937a30/d .functor AND 1, L_0x1937850, L_0x1937990, C4<1>, C4<1>; -L_0x1937a30 .delay (20000,20000,20000) L_0x1937a30/d; -L_0x1937b20/d .functor AND 1, L_0x1937430, L_0x1937d90, C4<1>, C4<1>; -L_0x1937b20 .delay (20000,20000,20000) L_0x1937b20/d; -L_0x1937c50/d .functor OR 1, L_0x1937a30, L_0x1937b20, C4<0>, C4<0>; -L_0x1937c50 .delay (20000,20000,20000) L_0x1937c50/d; -v0x1920770_0 .net "S", 0 0, L_0x1937d90; 1 drivers -v0x1920830_0 .alias "in0", 0 0, v0x1920ec0_0; -v0x19208d0_0 .alias "in1", 0 0, v0x1920d30_0; -v0x1920970_0 .net "nS", 0 0, L_0x1937990; 1 drivers -v0x19209f0_0 .net "out0", 0 0, L_0x1937a30; 1 drivers -v0x1920a90_0 .net "out1", 0 0, L_0x1937b20; 1 drivers -v0x1920b70_0 .alias "outfinal", 0 0, v0x1921130_0; -S_0x1920190 .scope module, "mux1" "TwoInMux" 3 84, 3 8, S_0x19200a0; - .timescale -9 -12; -L_0x1937e30/d .functor NOT 1, L_0x19382c0, C4<0>, C4<0>, C4<0>; -L_0x1937e30 .delay (10000,10000,10000) L_0x1937e30/d; -L_0x1937ed0/d .functor AND 1, L_0x1937c50, L_0x1937e30, C4<1>, C4<1>; -L_0x1937ed0 .delay (20000,20000,20000) L_0x1937ed0/d; -L_0x1938000/d .functor AND 1, L_0x1937530, L_0x19382c0, C4<1>, C4<1>; -L_0x1938000 .delay (20000,20000,20000) L_0x1938000/d; -L_0x1938130/d .functor OR 1, L_0x1937ed0, L_0x1938000, C4<0>, C4<0>; -L_0x1938130 .delay (20000,20000,20000) L_0x1938130/d; -v0x1920280_0 .net "S", 0 0, L_0x19382c0; 1 drivers -v0x1920300_0 .alias "in0", 0 0, v0x1921130_0; -v0x1920380_0 .alias "in1", 0 0, v0x1920de0_0; -v0x1920420_0 .net "nS", 0 0, L_0x1937e30; 1 drivers -v0x19204a0_0 .net "out0", 0 0, L_0x1937ed0; 1 drivers -v0x1920540_0 .net "out1", 0 0, L_0x1938000; 1 drivers -v0x19205e0_0 .alias "outfinal", 0 0, v0x19210b0_0; -S_0x191ecd0 .scope generate, "orbits[1]" "orbits[1]" 3 196, 3 196, S_0x191c3a0; - .timescale -9 -12; -P_0x191e9e8 .param/l "i" 3 196, +C4<01>; -S_0x191ee00 .scope module, "attempt" "OrNorXor" 3 198, 3 64, S_0x191ecd0; - .timescale -9 -12; -L_0x1933820/d .functor NOR 1, L_0x1934c00, L_0x192ba30, C4<0>, C4<0>; -L_0x1933820 .delay (10000,10000,10000) L_0x1933820/d; -L_0x1933ac0/d .functor NOT 1, L_0x1933820, C4<0>, C4<0>, C4<0>; -L_0x1933ac0 .delay (10000,10000,10000) L_0x1933ac0/d; -L_0x1933bf0/d .functor NAND 1, L_0x1934c00, L_0x192ba30, C4<1>, C4<1>; -L_0x1933bf0 .delay (10000,10000,10000) L_0x1933bf0/d; -L_0x1933d50/d .functor NAND 1, L_0x1933bf0, L_0x1933ac0, C4<1>, C4<1>; -L_0x1933d50 .delay (10000,10000,10000) L_0x1933d50/d; -L_0x1933e60/d .functor NOT 1, L_0x1933d50, C4<0>, C4<0>, C4<0>; -L_0x1933e60 .delay (10000,10000,10000) L_0x1933e60/d; -v0x191f9b0_0 .net "A", 0 0, L_0x1934c00; 1 drivers -v0x191fa50_0 .net "AnandB", 0 0, L_0x1933bf0; 1 drivers -v0x191faf0_0 .net "AnorB", 0 0, L_0x1933820; 1 drivers -v0x191fba0_0 .net "AorB", 0 0, L_0x1933ac0; 1 drivers -v0x191fc80_0 .net "AxorB", 0 0, L_0x1933e60; 1 drivers -v0x191fd30_0 .net "B", 0 0, L_0x192ba30; 1 drivers -v0x191fdf0_0 .alias "Command", 2 0, v0x1928f70_0; -v0x191fe70_0 .net "OrNorXorOut", 0 0, L_0x1934860; 1 drivers -v0x191fef0_0 .net "XorNor", 0 0, L_0x19342e0; 1 drivers -v0x191ffc0_0 .net "nXor", 0 0, L_0x1933d50; 1 drivers -L_0x1934460 .part v0x192a0b0_0, 2, 1; -L_0x1934a30 .part v0x192a0b0_0, 0, 1; -S_0x191f440 .scope module, "mux0" "TwoInMux" 3 83, 3 8, S_0x191ee00; - .timescale -9 -12; -L_0x1933fc0/d .functor NOT 1, L_0x1934460, C4<0>, C4<0>, C4<0>; -L_0x1933fc0 .delay (10000,10000,10000) L_0x1933fc0/d; -L_0x1934080/d .functor AND 1, L_0x1933e60, L_0x1933fc0, C4<1>, C4<1>; -L_0x1934080 .delay (20000,20000,20000) L_0x1934080/d; -L_0x1934190/d .functor AND 1, L_0x1933820, L_0x1934460, C4<1>, C4<1>; -L_0x1934190 .delay (20000,20000,20000) L_0x1934190/d; -L_0x19342e0/d .functor OR 1, L_0x1934080, L_0x1934190, C4<0>, C4<0>; -L_0x19342e0 .delay (20000,20000,20000) L_0x19342e0/d; -v0x191f530_0 .net "S", 0 0, L_0x1934460; 1 drivers -v0x191f5f0_0 .alias "in0", 0 0, v0x191fc80_0; -v0x191f690_0 .alias "in1", 0 0, v0x191faf0_0; -v0x191f730_0 .net "nS", 0 0, L_0x1933fc0; 1 drivers -v0x191f7b0_0 .net "out0", 0 0, L_0x1934080; 1 drivers -v0x191f850_0 .net "out1", 0 0, L_0x1934190; 1 drivers -v0x191f930_0 .alias "outfinal", 0 0, v0x191fef0_0; -S_0x191eef0 .scope module, "mux1" "TwoInMux" 3 84, 3 8, S_0x191ee00; - .timescale -9 -12; -L_0x1934500/d .functor NOT 1, L_0x1934a30, C4<0>, C4<0>, C4<0>; -L_0x1934500 .delay (10000,10000,10000) L_0x1934500/d; -L_0x19345c0/d .functor AND 1, L_0x19342e0, L_0x1934500, C4<1>, C4<1>; -L_0x19345c0 .delay (20000,20000,20000) L_0x19345c0/d; -L_0x1934710/d .functor AND 1, L_0x1933ac0, L_0x1934a30, C4<1>, C4<1>; -L_0x1934710 .delay (20000,20000,20000) L_0x1934710/d; -L_0x1934860/d .functor OR 1, L_0x19345c0, L_0x1934710, C4<0>, C4<0>; -L_0x1934860 .delay (20000,20000,20000) L_0x1934860/d; -v0x191efe0_0 .net "S", 0 0, L_0x1934a30; 1 drivers -v0x191f060_0 .alias "in0", 0 0, v0x191fef0_0; -v0x191f100_0 .alias "in1", 0 0, v0x191fba0_0; -v0x191f1a0_0 .net "nS", 0 0, L_0x1934500; 1 drivers -v0x191f220_0 .net "out0", 0 0, L_0x19345c0; 1 drivers -v0x191f2c0_0 .net "out1", 0 0, L_0x1934710; 1 drivers -v0x191f3a0_0 .alias "outfinal", 0 0, v0x191fe70_0; -S_0x191d900 .scope generate, "orbits[2]" "orbits[2]" 3 196, 3 196, S_0x191c3a0; - .timescale -9 -12; -P_0x191d568 .param/l "i" 3 196, +C4<010>; -S_0x191da30 .scope module, "attempt" "OrNorXor" 3 198, 3 64, S_0x191d900; - .timescale -9 -12; -L_0x192bad0/d .functor NOR 1, L_0x19360d0, L_0x1936170, C4<0>, C4<0>; -L_0x192bad0 .delay (10000,10000,10000) L_0x192bad0/d; -L_0x192bc40/d .functor NOT 1, L_0x192bad0, C4<0>, C4<0>, C4<0>; -L_0x192bc40 .delay (10000,10000,10000) L_0x192bc40/d; -L_0x1935150/d .functor NAND 1, L_0x19360d0, L_0x1936170, C4<1>, C4<1>; -L_0x1935150 .delay (10000,10000,10000) L_0x1935150/d; -L_0x19352b0/d .functor NAND 1, L_0x1935150, L_0x192bc40, C4<1>, C4<1>; -L_0x19352b0 .delay (10000,10000,10000) L_0x19352b0/d; -L_0x19353c0/d .functor NOT 1, L_0x19352b0, C4<0>, C4<0>, C4<0>; -L_0x19353c0 .delay (10000,10000,10000) L_0x19353c0/d; -v0x191e5e0_0 .net "A", 0 0, L_0x19360d0; 1 drivers -v0x191e680_0 .net "AnandB", 0 0, L_0x1935150; 1 drivers -v0x191e720_0 .net "AnorB", 0 0, L_0x192bad0; 1 drivers -v0x191e7d0_0 .net "AorB", 0 0, L_0x192bc40; 1 drivers -v0x191e8b0_0 .net "AxorB", 0 0, L_0x19353c0; 1 drivers -v0x191e960_0 .net "B", 0 0, L_0x1936170; 1 drivers -v0x191ea20_0 .alias "Command", 2 0, v0x1928f70_0; -v0x191eaa0_0 .net "OrNorXorOut", 0 0, L_0x1935dc0; 1 drivers -v0x191eb20_0 .net "XorNor", 0 0, L_0x1935840; 1 drivers -v0x191ebf0_0 .net "nXor", 0 0, L_0x19352b0; 1 drivers -L_0x19359c0 .part v0x192a0b0_0, 2, 1; -L_0x1935f90 .part v0x192a0b0_0, 0, 1; -S_0x191e070 .scope module, "mux0" "TwoInMux" 3 83, 3 8, S_0x191da30; - .timescale -9 -12; -L_0x1935520/d .functor NOT 1, L_0x19359c0, C4<0>, C4<0>, C4<0>; -L_0x1935520 .delay (10000,10000,10000) L_0x1935520/d; -L_0x19355e0/d .functor AND 1, L_0x19353c0, L_0x1935520, C4<1>, C4<1>; -L_0x19355e0 .delay (20000,20000,20000) L_0x19355e0/d; -L_0x19356f0/d .functor AND 1, L_0x192bad0, L_0x19359c0, C4<1>, C4<1>; -L_0x19356f0 .delay (20000,20000,20000) L_0x19356f0/d; -L_0x1935840/d .functor OR 1, L_0x19355e0, L_0x19356f0, C4<0>, C4<0>; -L_0x1935840 .delay (20000,20000,20000) L_0x1935840/d; -v0x191e160_0 .net "S", 0 0, L_0x19359c0; 1 drivers -v0x191e220_0 .alias "in0", 0 0, v0x191e8b0_0; -v0x191e2c0_0 .alias "in1", 0 0, v0x191e720_0; -v0x191e360_0 .net "nS", 0 0, L_0x1935520; 1 drivers -v0x191e3e0_0 .net "out0", 0 0, L_0x19355e0; 1 drivers -v0x191e480_0 .net "out1", 0 0, L_0x19356f0; 1 drivers -v0x191e560_0 .alias "outfinal", 0 0, v0x191eb20_0; -S_0x191db20 .scope module, "mux1" "TwoInMux" 3 84, 3 8, S_0x191da30; - .timescale -9 -12; -L_0x1935a60/d .functor NOT 1, L_0x1935f90, C4<0>, C4<0>, C4<0>; -L_0x1935a60 .delay (10000,10000,10000) L_0x1935a60/d; -L_0x1935b20/d .functor AND 1, L_0x1935840, L_0x1935a60, C4<1>, C4<1>; -L_0x1935b20 .delay (20000,20000,20000) L_0x1935b20/d; -L_0x1935c70/d .functor AND 1, L_0x192bc40, L_0x1935f90, C4<1>, C4<1>; -L_0x1935c70 .delay (20000,20000,20000) L_0x1935c70/d; -L_0x1935dc0/d .functor OR 1, L_0x1935b20, L_0x1935c70, C4<0>, C4<0>; -L_0x1935dc0 .delay (20000,20000,20000) L_0x1935dc0/d; -v0x191dc10_0 .net "S", 0 0, L_0x1935f90; 1 drivers -v0x191dc90_0 .alias "in0", 0 0, v0x191eb20_0; -v0x191dd30_0 .alias "in1", 0 0, v0x191e7d0_0; -v0x191ddd0_0 .net "nS", 0 0, L_0x1935a60; 1 drivers -v0x191de50_0 .net "out0", 0 0, L_0x1935b20; 1 drivers -v0x191def0_0 .net "out1", 0 0, L_0x1935c70; 1 drivers -v0x191dfd0_0 .alias "outfinal", 0 0, v0x191eaa0_0; -S_0x191c490 .scope generate, "orbits[3]" "orbits[3]" 3 196, 3 196, S_0x191c3a0; - .timescale -9 -12; -P_0x191c1d8 .param/l "i" 3 196, +C4<011>; -S_0x191c580 .scope module, "attempt" "OrNorXor" 3 198, 3 64, S_0x191c490; - .timescale -9 -12; -L_0x1936250/d .functor NOR 1, L_0x19372f0, L_0x1937390, C4<0>, C4<0>; -L_0x1936250 .delay (10000,10000,10000) L_0x1936250/d; -L_0x1936340/d .functor NOT 1, L_0x1936250, C4<0>, C4<0>, C4<0>; -L_0x1936340 .delay (10000,10000,10000) L_0x1936340/d; -L_0x1936450/d .functor NAND 1, L_0x19372f0, L_0x1937390, C4<1>, C4<1>; -L_0x1936450 .delay (10000,10000,10000) L_0x1936450/d; -L_0x19365b0/d .functor NAND 1, L_0x1936450, L_0x1936340, C4<1>, C4<1>; -L_0x19365b0 .delay (10000,10000,10000) L_0x19365b0/d; -L_0x19366c0/d .functor NOT 1, L_0x19365b0, C4<0>, C4<0>, C4<0>; -L_0x19366c0 .delay (10000,10000,10000) L_0x19366c0/d; -v0x191d160_0 .net "A", 0 0, L_0x19372f0; 1 drivers -v0x191d200_0 .net "AnandB", 0 0, L_0x1936450; 1 drivers -v0x191d2a0_0 .net "AnorB", 0 0, L_0x1936250; 1 drivers -v0x191d350_0 .net "AorB", 0 0, L_0x1936340; 1 drivers -v0x191d430_0 .net "AxorB", 0 0, L_0x19366c0; 1 drivers -v0x191d4e0_0 .net "B", 0 0, L_0x1937390; 1 drivers -v0x191d5a0_0 .alias "Command", 2 0, v0x1928f70_0; -v0x1915a00_0 .net "OrNorXorOut", 0 0, L_0x1924320; 1 drivers -v0x1915a80_0 .net "XorNor", 0 0, L_0x1936b40; 1 drivers -v0x191d880_0 .net "nXor", 0 0, L_0x19365b0; 1 drivers -L_0x1936cc0 .part v0x192a0b0_0, 2, 1; -L_0x19371b0 .part v0x192a0b0_0, 0, 1; -S_0x191cbf0 .scope module, "mux0" "TwoInMux" 3 83, 3 8, S_0x191c580; - .timescale -9 -12; -L_0x1936820/d .functor NOT 1, L_0x1936cc0, C4<0>, C4<0>, C4<0>; -L_0x1936820 .delay (10000,10000,10000) L_0x1936820/d; -L_0x19368e0/d .functor AND 1, L_0x19366c0, L_0x1936820, C4<1>, C4<1>; -L_0x19368e0 .delay (20000,20000,20000) L_0x19368e0/d; -L_0x19369f0/d .functor AND 1, L_0x1936250, L_0x1936cc0, C4<1>, C4<1>; -L_0x19369f0 .delay (20000,20000,20000) L_0x19369f0/d; -L_0x1936b40/d .functor OR 1, L_0x19368e0, L_0x19369f0, C4<0>, C4<0>; -L_0x1936b40 .delay (20000,20000,20000) L_0x1936b40/d; -v0x191cce0_0 .net "S", 0 0, L_0x1936cc0; 1 drivers -v0x191cda0_0 .alias "in0", 0 0, v0x191d430_0; -v0x191ce40_0 .alias "in1", 0 0, v0x191d2a0_0; -v0x191cee0_0 .net "nS", 0 0, L_0x1936820; 1 drivers -v0x191cf60_0 .net "out0", 0 0, L_0x19368e0; 1 drivers -v0x191d000_0 .net "out1", 0 0, L_0x19369f0; 1 drivers -v0x191d0e0_0 .alias "outfinal", 0 0, v0x1915a80_0; -S_0x191c670 .scope module, "mux1" "TwoInMux" 3 84, 3 8, S_0x191c580; - .timescale -9 -12; -L_0x1936d60/d .functor NOT 1, L_0x19371b0, C4<0>, C4<0>, C4<0>; -L_0x1936d60 .delay (10000,10000,10000) L_0x1936d60/d; -L_0x1936e20/d .functor AND 1, L_0x1936b40, L_0x1936d60, C4<1>, C4<1>; -L_0x1936e20 .delay (20000,20000,20000) L_0x1936e20/d; -L_0x1936f70/d .functor AND 1, L_0x1936340, L_0x19371b0, C4<1>, C4<1>; -L_0x1936f70 .delay (20000,20000,20000) L_0x1936f70/d; -L_0x1924320/d .functor OR 1, L_0x1936e20, L_0x1936f70, C4<0>, C4<0>; -L_0x1924320 .delay (20000,20000,20000) L_0x1924320/d; -v0x191c760_0 .net "S", 0 0, L_0x19371b0; 1 drivers -v0x191c7e0_0 .alias "in0", 0 0, v0x1915a80_0; -v0x191c880_0 .alias "in1", 0 0, v0x191d350_0; -v0x191c920_0 .net "nS", 0 0, L_0x1936d60; 1 drivers -v0x191c9d0_0 .net "out0", 0 0, L_0x1936e20; 1 drivers -v0x191ca70_0 .net "out1", 0 0, L_0x1936f70; 1 drivers -v0x191cb50_0 .alias "outfinal", 0 0, v0x1915a00_0; -S_0x18a5800 .scope module, "superalu" "Bitslice32" 2 147, 3 256, S_0x18c7e50; - .timescale -9 -12; -P_0x1880428 .param/l "size" 3 273, +C4<0100>; -L_0x193d900/d .functor AND 1, L_0x19505f0, L_0x19507d0, C4<1>, C4<1>; -L_0x193d900 .delay (20000,20000,20000) L_0x193d900/d; -L_0x19508c0/d .functor NOT 1, L_0x1950970, C4<0>, C4<0>, C4<0>; -L_0x19508c0 .delay (10000,10000,10000) L_0x19508c0/d; -L_0x1950e20/d .functor AND 1, L_0x19508c0, L_0x19508c0, C4<1>, C4<1>; -L_0x1950e20 .delay (20000,20000,20000) L_0x1950e20/d; -v0x191b290_0 .alias "A", 3 0, v0x1928d50_0; -v0x191b480_0 .alias "AddSubSLTSum", 3 0, v0x1929eb0_0; -v0x191b500_0 .alias "AllZeros", 0 0, v0x1929f30_0; -v0x191b580_0 .alias "AndNandOut", 3 0, v0x1929fb0_0; -v0x191b630_0 .alias "B", 3 0, v0x1928e70_0; -RS_0x7f644c9d5008 .resolv tri, L_0x1938e00, L_0x193b860, L_0x193e660, L_0x194e9c0; -v0x191b6b0_0 .net8 "Cmd0Start", 3 0, RS_0x7f644c9d5008; 4 drivers -RS_0x7f644c9d5038 .resolv tri, L_0x1939d70, L_0x193c750, L_0x193f650, L_0x194f7f0; -v0x191b730_0 .net8 "Cmd1Start", 3 0, RS_0x7f644c9d5038; 4 drivers -v0x191b7b0_0 .alias "Command", 2 0, v0x1928f70_0; -v0x191b830_0 .alias "OneBitFinalOut", 3 0, v0x192a130_0; -v0x191b8d0_0 .alias "OrNorXorOut", 3 0, v0x192a1b0_0; -v0x191b950_0 .alias "SLTflag", 0 0, v0x192a230_0; -v0x191ba00_0 .alias "ZeroFlag", 3 0, v0x192a2b0_0; -v0x191ba80_0 .net *"_s111", 0 0, L_0x193d900; 1 drivers -v0x191bb00_0 .net *"_s114", 0 0, L_0x19505f0; 1 drivers -v0x191bc20_0 .net *"_s116", 0 0, L_0x19507d0; 1 drivers -v0x191bcc0_0 .net *"_s118", 0 0, L_0x1950970; 1 drivers -v0x191bb80_0 .net *"_s21", 0 0, L_0x193adc0; 1 drivers -v0x191be10_0 .net *"_s46", 0 0, L_0x193d1d0; 1 drivers -v0x191bf30_0 .net *"_s71", 0 0, L_0x1940410; 1 drivers -v0x191bfb0_0 .alias "carryin", 3 0, v0x19299a0_0; -v0x191be90_0 .alias "carryout", 0 0, v0x192a3b0_0; -v0x191c110_0 .alias "overflow", 0 0, v0x192a430_0; -v0x191c060_0 .alias "subtract", 3 0, v0x192a4b0_0; -v0x191c250_0 .net "yeszero", 0 0, L_0x19508c0; 1 drivers -L_0x1938e00 .part/pv L_0x1938bf0, 1, 1, 4; -L_0x1938ea0 .part v0x192a0b0_0, 0, 1; -L_0x1938fd0 .part v0x192a0b0_0, 1, 1; -L_0x1939100 .part RS_0x7f644c9d4be8, 1, 1; -L_0x19391a0 .part RS_0x7f644c9d4be8, 1, 1; -L_0x1939240 .part RS_0x7f644c9d3748, 1, 1; -L_0x1939440 .part RS_0x7f644c9d4be8, 1, 1; -L_0x1939d70 .part/pv L_0x1939b60, 1, 1, 4; -L_0x1939e60 .part v0x192a0b0_0, 0, 1; -L_0x1939f90 .part v0x192a0b0_0, 1, 1; -L_0x193a120 .part RS_0x7f644c9d3e38, 1, 1; -L_0x193a2d0 .part RS_0x7f644c9d3e38, 1, 1; -L_0x193a370 .part RS_0x7f644c9d3748, 1, 1; -L_0x193a410 .part RS_0x7f644c9d3748, 1, 1; -L_0x193a870 .part/pv L_0x193a730, 1, 1, 4; -L_0x193a960 .part v0x192a0b0_0, 2, 1; -L_0x193aa00 .part RS_0x7f644c9d5008, 1, 1; -L_0x193ab40 .part RS_0x7f644c9d5038, 1, 1; -L_0x193ad20 .part/pv L_0x193adc0, 1, 1, 4; -L_0x193aec0 .part RS_0x7f644c9d5098, 0, 1; -L_0x193ac80 .part RS_0x7f644c9d5068, 1, 1; -L_0x193b860 .part/pv L_0x193b650, 2, 1, 4; -L_0x193af60 .part v0x192a0b0_0, 0, 1; -L_0x193ba50 .part v0x192a0b0_0, 1, 1; -L_0x193b900 .part RS_0x7f644c9d4be8, 2, 1; -L_0x193bc50 .part RS_0x7f644c9d4be8, 2, 1; -L_0x193bb80 .part RS_0x7f644c9d3748, 2, 1; -L_0x193be20 .part RS_0x7f644c9d4be8, 2, 1; -L_0x193c750 .part/pv L_0x193c540, 2, 1, 4; -L_0x193c7f0 .part v0x192a0b0_0, 0, 1; -L_0x193bf10 .part v0x192a0b0_0, 1, 1; -L_0x192ad80 .part RS_0x7f644c9d3e38, 2, 1; -L_0x192af30 .part RS_0x7f644c9d3e38, 2, 1; -L_0x192abf0 .part RS_0x7f644c9d3748, 2, 1; -L_0x192ae20 .part RS_0x7f644c9d3748, 2, 1; -L_0x193d600 .part/pv L_0x193d4c0, 2, 1, 4; -L_0x193d130 .part v0x192a0b0_0, 2, 1; -L_0x193d860 .part RS_0x7f644c9d5008, 2, 1; -L_0x193d730 .part RS_0x7f644c9d5038, 2, 1; -L_0x193dad0 .part/pv L_0x193d1d0, 2, 1, 4; -L_0x193d9d0 .part RS_0x7f644c9d5098, 1, 1; -L_0x193dd50 .part RS_0x7f644c9d5068, 2, 1; -L_0x193e660 .part/pv L_0x193e450, 3, 1, 4; -L_0x193e700 .part v0x192a0b0_0, 0, 1; -L_0x193ddf0 .part v0x192a0b0_0, 1, 1; -L_0x193e9a0 .part RS_0x7f644c9d4be8, 3, 1; -L_0x1930820 .part RS_0x7f644c9d4be8, 3, 1; -L_0x193e830 .part RS_0x7f644c9d3748, 3, 1; -L_0x193ede0 .part RS_0x7f644c9d4be8, 3, 1; -L_0x193f650 .part/pv L_0x193f440, 3, 1, 4; -L_0x193ec50 .part v0x192a0b0_0, 0, 1; -L_0x193f890 .part v0x192a0b0_0, 1, 1; -L_0x193f6f0 .part RS_0x7f644c9d3e38, 3, 1; -L_0x193f790 .part RS_0x7f644c9d3e38, 3, 1; -L_0x193fb80 .part RS_0x7f644c9d3748, 3, 1; -L_0x193fc20 .part RS_0x7f644c9d3748, 3, 1; -L_0x1940230 .part/pv L_0x19400f0, 3, 1, 4; -L_0x19402d0 .part v0x192a0b0_0, 2, 1; -L_0x193fed0 .part RS_0x7f644c9d5008, 3, 1; -L_0x193ffc0 .part RS_0x7f644c9d5038, 3, 1; -L_0x1940370 .part/pv L_0x1940410, 3, 1, 4; -L_0x1940790 .part RS_0x7f644c9d5098, 2, 1; -L_0x19405a0 .part RS_0x7f644c9d5068, 3, 1; -L_0x194e9c0 .part/pv L_0x194e7e0, 0, 1, 4; -L_0x1940830 .part v0x192a0b0_0, 0, 1; -L_0x1940960 .part v0x192a0b0_0, 1, 1; -L_0x194ea60 .part RS_0x7f644c9d4be8, 0, 1; -L_0x194eb00 .part RS_0x7f644c9d4be8, 0, 1; -L_0x194eba0 .part RS_0x7f644c9d3748, 0, 1; -L_0x194ef80 .part RS_0x7f644c9d4be8, 0, 1; -L_0x194f7f0 .part/pv L_0x194f610, 0, 1, 4; -L_0x194f890 .part v0x192a0b0_0, 0, 1; -L_0x194f070 .part v0x192a0b0_0, 1, 1; -L_0x194f1a0 .part RS_0x7f644c9d3e38, 0, 1; -L_0x194fc20 .part RS_0x7f644c9d3e38, 0, 1; -L_0x194fcc0 .part RS_0x7f644c9d3748, 0, 1; -L_0x194f9c0 .part RS_0x7f644c9d3748, 0, 1; -L_0x1950290 .part/pv L_0x1950150, 0, 1, 4; -L_0x194fd60 .part v0x192a0b0_0, 2, 1; -L_0x194fe00 .part RS_0x7f644c9d5008, 0, 1; -L_0x194fef0 .part RS_0x7f644c9d5038, 0, 1; -L_0x1950550 .part/pv L_0x193d900, 0, 1, 4; -L_0x19505f0 .part RS_0x7f644c9d5068, 0, 1; -L_0x19507d0 .part RS_0x7f644c9d5068, 0, 1; -L_0x1950970 .part RS_0x7f644c9d5098, 3, 1; -S_0x1915cf0 .scope module, "trial" "AddSubSLT32" 3 279, 3 205, S_0x18a5800; - .timescale -9 -12; -P_0x1915de8 .param/l "size" 3 228, +C4<0100>; -L_0x1945950/d .functor OR 1, L_0x1945c10, C4<0>, C4<0>, C4<0>; -L_0x1945950 .delay (20000,20000,20000) L_0x1945950/d; -L_0x1945dc0/d .functor XOR 1, RS_0x7f644c9d4ee8, L_0x1945eb0, C4<0>, C4<0>; -L_0x1945dc0 .delay (40000,40000,40000) L_0x1945dc0/d; -L_0x1945b40/d .functor AND 1, L_0x1946080, L_0x1946120, C4<1>, C4<1>; -L_0x1945b40 .delay (20000,20000,20000) L_0x1945b40/d; -L_0x1945f50/d .functor NOT 1, RS_0x7f644c9d4f78, C4<0>, C4<0>, C4<0>; -L_0x1945f50 .delay (10000,10000,10000) L_0x1945f50/d; -L_0x1946410/d .functor NOT 1, L_0x1946470, C4<0>, C4<0>, C4<0>; -L_0x1946410 .delay (10000,10000,10000) L_0x1946410/d; -L_0x1946510/d .functor AND 1, L_0x1945f50, L_0x1946650, C4<1>, C4<1>; -L_0x1946510 .delay (20000,20000,20000) L_0x1946510/d; -L_0x1946210/d .functor AND 1, RS_0x7f644c9d4f78, L_0x1946410, C4<1>, C4<1>; -L_0x1946210 .delay (20000,20000,20000) L_0x1946210/d; -L_0x1946840/d .functor AND 1, L_0x1946510, L_0x1945b40, C4<1>, C4<1>; -L_0x1946840 .delay (20000,20000,20000) L_0x1946840/d; -L_0x1946980/d .functor AND 1, L_0x1946210, L_0x1945b40, C4<1>, C4<1>; -L_0x1946980 .delay (20000,20000,20000) L_0x1946980/d; -L_0x1946aa0/d .functor OR 1, L_0x1946840, L_0x1946980, C4<0>, C4<0>; -L_0x1946aa0 .delay (20000,20000,20000) L_0x1946aa0/d; -v0x191a3b0_0 .alias "A", 3 0, v0x1928d50_0; -v0x191a450_0 .alias "AddSubSLTSum", 3 0, v0x1929eb0_0; -v0x191a4f0_0 .alias "B", 3 0, v0x1928e70_0; -RS_0x7f644c9d4c18 .resolv tri, L_0x19418c0, L_0x1942ce0, L_0x19440e0, L_0x19456c0; -v0x191a5c0_0 .net8 "CarryoutWire", 3 0, RS_0x7f644c9d4c18; 4 drivers -v0x191a640_0 .alias "Command", 2 0, v0x1928f70_0; -v0x191a6c0_0 .net "Res0OF1", 0 0, L_0x1946210; 1 drivers -v0x191a760_0 .net "Res1OF0", 0 0, L_0x1946510; 1 drivers -v0x191a800_0 .alias "SLTflag", 0 0, v0x192a230_0; -v0x191a8f0_0 .net "SLTflag0", 0 0, L_0x1946840; 1 drivers -v0x191a990_0 .net "SLTflag1", 0 0, L_0x1946980; 1 drivers -v0x191aa30_0 .net "SLTon", 0 0, L_0x1945b40; 1 drivers -v0x191aad0_0 .net *"_s40", 0 0, L_0x1945c10; 1 drivers -v0x191ab70_0 .net/s *"_s41", 0 0, C4<0>; 1 drivers -v0x191ac10_0 .net *"_s44", 0 0, L_0x1945eb0; 1 drivers -v0x191ad30_0 .net *"_s46", 0 0, L_0x1946080; 1 drivers -v0x191add0_0 .net *"_s48", 0 0, L_0x1946120; 1 drivers -v0x191ac90_0 .net *"_s50", 0 0, L_0x1946470; 1 drivers -v0x191af20_0 .net *"_s52", 0 0, L_0x1946650; 1 drivers -v0x191b040_0 .alias "carryin", 3 0, v0x19299a0_0; -v0x191b0c0_0 .alias "carryout", 0 0, v0x192a3b0_0; -v0x191afa0_0 .net "nAddSubSLTSum", 0 0, L_0x1946410; 1 drivers -v0x191b1f0_0 .net "nOF", 0 0, L_0x1945f50; 1 drivers -v0x191b140_0 .alias "overflow", 0 0, v0x192a430_0; -v0x191b330_0 .alias "subtract", 3 0, v0x192a4b0_0; -L_0x19417d0 .part/pv L_0x1941340, 1, 1, 4; -L_0x19418c0 .part/pv L_0x1941690, 1, 1, 4; -L_0x19419b0 .part/pv L_0x1941070, 1, 1, 4; -L_0x1941aa0 .part v0x1929e30_0, 1, 1; -L_0x1941b40 .part v0x192a030_0, 1, 1; -L_0x1941c70 .part RS_0x7f644c9d4c18, 0, 1; -L_0x1942bf0 .part/pv L_0x1942760, 2, 1, 4; -L_0x1942ce0 .part/pv L_0x1942ab0, 2, 1, 4; -L_0x1942e20 .part/pv L_0x1942490, 2, 1, 4; -L_0x1942f10 .part v0x1929e30_0, 2, 1; -L_0x1943010 .part v0x192a030_0, 2, 1; -L_0x1943140 .part RS_0x7f644c9d4c18, 1, 1; -L_0x1943ff0 .part/pv L_0x1943b60, 3, 1, 4; -L_0x19440e0 .part/pv L_0x1943eb0, 3, 1, 4; -L_0x1944250 .part/pv L_0x1943890, 3, 1, 4; -L_0x1944340 .part v0x1929e30_0, 3, 1; -L_0x1944470 .part v0x192a030_0, 3, 1; -L_0x19445a0 .part RS_0x7f644c9d4c18, 2, 1; -L_0x19455d0 .part/pv L_0x1945100, 0, 1, 4; -L_0x19456c0 .part/pv L_0x1945470, 0, 1, 4; -L_0x1944640 .part/pv L_0x1944e30, 0, 1, 4; -L_0x19458b0 .part v0x1929e30_0, 0, 1; -L_0x19457b0 .part v0x192a030_0, 0, 1; -L_0x1945aa0 .part RS_0x7f644c9d4fa8, 0, 1; -L_0x1945c10 .part RS_0x7f644c9d4c18, 3, 1; -L_0x1945eb0 .part RS_0x7f644c9d4c18, 2, 1; -L_0x1946080 .part v0x192a0b0_0, 1, 1; -L_0x1946120 .part RS_0x7f644c9d4fa8, 0, 1; -L_0x1946470 .part RS_0x7f644c9d4be8, 3, 1; -L_0x1946650 .part RS_0x7f644c9d4be8, 3, 1; -S_0x19193a0 .scope module, "attempt2" "MiddleAddSubSLT" 3 225, 3 89, S_0x1915cf0; - .timescale -9 -12; -L_0x19443e0/d .functor NOT 1, L_0x19457b0, C4<0>, C4<0>, C4<0>; -L_0x19443e0 .delay (10000,10000,10000) L_0x19443e0/d; -L_0x1944cd0/d .functor NOT 1, L_0x1944d90, C4<0>, C4<0>, C4<0>; -L_0x1944cd0 .delay (10000,10000,10000) L_0x1944cd0/d; -L_0x1944e30/d .functor AND 1, L_0x1944f70, L_0x1944cd0, C4<1>, C4<1>; -L_0x1944e30 .delay (20000,20000,20000) L_0x1944e30/d; -L_0x1945010/d .functor XOR 1, L_0x19458b0, L_0x1944a60, C4<0>, C4<0>; -L_0x1945010 .delay (40000,40000,40000) L_0x1945010/d; -L_0x1945100/d .functor XOR 1, L_0x1945010, L_0x1945aa0, C4<0>, C4<0>; -L_0x1945100 .delay (40000,40000,40000) L_0x1945100/d; -L_0x19451f0/d .functor AND 1, L_0x19458b0, L_0x1944a60, C4<1>, C4<1>; -L_0x19451f0 .delay (20000,20000,20000) L_0x19451f0/d; -L_0x1945360/d .functor AND 1, L_0x1945010, L_0x1945aa0, C4<1>, C4<1>; -L_0x1945360 .delay (20000,20000,20000) L_0x1945360/d; -L_0x1945470/d .functor OR 1, L_0x19451f0, L_0x1945360, C4<0>, C4<0>; -L_0x1945470 .delay (20000,20000,20000) L_0x1945470/d; -v0x1919a10_0 .net "A", 0 0, L_0x19458b0; 1 drivers -v0x1919ad0_0 .net "AandB", 0 0, L_0x19451f0; 1 drivers -v0x1919b70_0 .net "AddSubSLTSum", 0 0, L_0x1945100; 1 drivers -v0x1919c10_0 .net "AxorB", 0 0, L_0x1945010; 1 drivers -v0x1919c90_0 .net "B", 0 0, L_0x19457b0; 1 drivers -v0x1919d40_0 .net "BornB", 0 0, L_0x1944a60; 1 drivers -v0x1919e00_0 .net "CINandAxorB", 0 0, L_0x1945360; 1 drivers -v0x1919e80_0 .alias "Command", 2 0, v0x1928f70_0; -v0x1919f00_0 .net *"_s3", 0 0, L_0x1944d90; 1 drivers -v0x1919f80_0 .net *"_s5", 0 0, L_0x1944f70; 1 drivers -v0x191a020_0 .net "carryin", 0 0, L_0x1945aa0; 1 drivers -v0x191a0c0_0 .net "carryout", 0 0, L_0x1945470; 1 drivers -v0x191a160_0 .net "nB", 0 0, L_0x19443e0; 1 drivers -v0x191a210_0 .net "nCmd2", 0 0, L_0x1944cd0; 1 drivers -v0x191a310_0 .net "subtract", 0 0, L_0x1944e30; 1 drivers -L_0x1944c30 .part v0x192a0b0_0, 0, 1; -L_0x1944d90 .part v0x192a0b0_0, 2, 1; -L_0x1944f70 .part v0x192a0b0_0, 0, 1; -S_0x1919490 .scope module, "mux0" "TwoInMux" 3 105, 3 8, S_0x19193a0; - .timescale -9 -12; -L_0x1944780/d .functor NOT 1, L_0x1944c30, C4<0>, C4<0>, C4<0>; -L_0x1944780 .delay (10000,10000,10000) L_0x1944780/d; -L_0x1944840/d .functor AND 1, L_0x19457b0, L_0x1944780, C4<1>, C4<1>; -L_0x1944840 .delay (20000,20000,20000) L_0x1944840/d; -L_0x1944950/d .functor AND 1, L_0x19443e0, L_0x1944c30, C4<1>, C4<1>; -L_0x1944950 .delay (20000,20000,20000) L_0x1944950/d; -L_0x1944a60/d .functor OR 1, L_0x1944840, L_0x1944950, C4<0>, C4<0>; -L_0x1944a60 .delay (20000,20000,20000) L_0x1944a60/d; -v0x1919580_0 .net "S", 0 0, L_0x1944c30; 1 drivers -v0x1919640_0 .alias "in0", 0 0, v0x1919c90_0; -v0x19196e0_0 .alias "in1", 0 0, v0x191a160_0; -v0x1919780_0 .net "nS", 0 0, L_0x1944780; 1 drivers -v0x1919830_0 .net "out0", 0 0, L_0x1944840; 1 drivers -v0x19198d0_0 .net "out1", 0 0, L_0x1944950; 1 drivers -v0x1919970_0 .alias "outfinal", 0 0, v0x1919d40_0; -S_0x1918200 .scope generate, "addbits[1]" "addbits[1]" 3 230, 3 230, S_0x1915cf0; - .timescale -9 -12; -P_0x1917c18 .param/l "i" 3 230, +C4<01>; -S_0x1918370 .scope module, "attempt" "MiddleAddSubSLT" 3 232, 3 89, S_0x1918200; - .timescale -9 -12; -L_0x1940690/d .functor NOT 1, L_0x1941b40, C4<0>, C4<0>, C4<0>; -L_0x1940690 .delay (10000,10000,10000) L_0x1940690/d; -L_0x1940f30/d .functor NOT 1, L_0x1940fd0, C4<0>, C4<0>, C4<0>; -L_0x1940f30 .delay (10000,10000,10000) L_0x1940f30/d; -L_0x1941070/d .functor AND 1, L_0x19411b0, L_0x1940f30, C4<1>, C4<1>; -L_0x1941070 .delay (20000,20000,20000) L_0x1941070/d; -L_0x1941250/d .functor XOR 1, L_0x1941aa0, L_0x1940d00, C4<0>, C4<0>; -L_0x1941250 .delay (40000,40000,40000) L_0x1941250/d; -L_0x1941340/d .functor XOR 1, L_0x1941250, L_0x1941c70, C4<0>, C4<0>; -L_0x1941340 .delay (40000,40000,40000) L_0x1941340/d; -L_0x1941430/d .functor AND 1, L_0x1941aa0, L_0x1940d00, C4<1>, C4<1>; -L_0x1941430 .delay (20000,20000,20000) L_0x1941430/d; -L_0x19415a0/d .functor AND 1, L_0x1941250, L_0x1941c70, C4<1>, C4<1>; -L_0x19415a0 .delay (20000,20000,20000) L_0x19415a0/d; -L_0x1941690/d .functor OR 1, L_0x1941430, L_0x19415a0, C4<0>, C4<0>; -L_0x1941690 .delay (20000,20000,20000) L_0x1941690/d; -v0x1918a00_0 .net "A", 0 0, L_0x1941aa0; 1 drivers -v0x1918ac0_0 .net "AandB", 0 0, L_0x1941430; 1 drivers -v0x1918b60_0 .net "AddSubSLTSum", 0 0, L_0x1941340; 1 drivers -v0x1918c00_0 .net "AxorB", 0 0, L_0x1941250; 1 drivers -v0x1918c80_0 .net "B", 0 0, L_0x1941b40; 1 drivers -v0x1918d30_0 .net "BornB", 0 0, L_0x1940d00; 1 drivers -v0x1918df0_0 .net "CINandAxorB", 0 0, L_0x19415a0; 1 drivers -v0x1918e70_0 .alias "Command", 2 0, v0x1928f70_0; -v0x1918ef0_0 .net *"_s3", 0 0, L_0x1940fd0; 1 drivers -v0x1918f70_0 .net *"_s5", 0 0, L_0x19411b0; 1 drivers -v0x1919010_0 .net "carryin", 0 0, L_0x1941c70; 1 drivers -v0x19190b0_0 .net "carryout", 0 0, L_0x1941690; 1 drivers -v0x1919150_0 .net "nB", 0 0, L_0x1940690; 1 drivers -v0x1919200_0 .net "nCmd2", 0 0, L_0x1940f30; 1 drivers -v0x1919300_0 .net "subtract", 0 0, L_0x1941070; 1 drivers -L_0x1940e90 .part v0x192a0b0_0, 0, 1; -L_0x1940fd0 .part v0x192a0b0_0, 2, 1; -L_0x19411b0 .part v0x192a0b0_0, 0, 1; -S_0x1918460 .scope module, "mux0" "TwoInMux" 3 105, 3 8, S_0x1918370; - .timescale -9 -12; -L_0x1940a80/d .functor NOT 1, L_0x1940e90, C4<0>, C4<0>, C4<0>; -L_0x1940a80 .delay (10000,10000,10000) L_0x1940a80/d; -L_0x1940b20/d .functor AND 1, L_0x1941b40, L_0x1940a80, C4<1>, C4<1>; -L_0x1940b20 .delay (20000,20000,20000) L_0x1940b20/d; -L_0x1940c10/d .functor AND 1, L_0x1940690, L_0x1940e90, C4<1>, C4<1>; -L_0x1940c10 .delay (20000,20000,20000) L_0x1940c10/d; -L_0x1940d00/d .functor OR 1, L_0x1940b20, L_0x1940c10, C4<0>, C4<0>; -L_0x1940d00 .delay (20000,20000,20000) L_0x1940d00/d; -v0x1918550_0 .net "S", 0 0, L_0x1940e90; 1 drivers -v0x19185f0_0 .alias "in0", 0 0, v0x1918c80_0; -v0x1918690_0 .alias "in1", 0 0, v0x1919150_0; -v0x1918730_0 .net "nS", 0 0, L_0x1940a80; 1 drivers -v0x19187e0_0 .net "out0", 0 0, L_0x1940b20; 1 drivers -v0x1918880_0 .net "out1", 0 0, L_0x1940c10; 1 drivers -v0x1918960_0 .alias "outfinal", 0 0, v0x1918d30_0; -S_0x1917090 .scope generate, "addbits[2]" "addbits[2]" 3 230, 3 230, S_0x1915cf0; - .timescale -9 -12; -P_0x1916968 .param/l "i" 3 230, +C4<010>; -S_0x1917200 .scope module, "attempt" "MiddleAddSubSLT" 3 232, 3 89, S_0x1917090; - .timescale -9 -12; -L_0x1941d10/d .functor NOT 1, L_0x1943010, C4<0>, C4<0>, C4<0>; -L_0x1941d10 .delay (10000,10000,10000) L_0x1941d10/d; -L_0x1942350/d .functor NOT 1, L_0x19423f0, C4<0>, C4<0>, C4<0>; -L_0x1942350 .delay (10000,10000,10000) L_0x1942350/d; -L_0x1942490/d .functor AND 1, L_0x19425d0, L_0x1942350, C4<1>, C4<1>; -L_0x1942490 .delay (20000,20000,20000) L_0x1942490/d; -L_0x1942670/d .functor XOR 1, L_0x1942f10, L_0x1942120, C4<0>, C4<0>; -L_0x1942670 .delay (40000,40000,40000) L_0x1942670/d; -L_0x1942760/d .functor XOR 1, L_0x1942670, L_0x1943140, C4<0>, C4<0>; -L_0x1942760 .delay (40000,40000,40000) L_0x1942760/d; -L_0x1942850/d .functor AND 1, L_0x1942f10, L_0x1942120, C4<1>, C4<1>; -L_0x1942850 .delay (20000,20000,20000) L_0x1942850/d; -L_0x19429c0/d .functor AND 1, L_0x1942670, L_0x1943140, C4<1>, C4<1>; -L_0x19429c0 .delay (20000,20000,20000) L_0x19429c0/d; -L_0x1942ab0/d .functor OR 1, L_0x1942850, L_0x19429c0, C4<0>, C4<0>; -L_0x1942ab0 .delay (20000,20000,20000) L_0x1942ab0/d; -v0x1917860_0 .net "A", 0 0, L_0x1942f10; 1 drivers -v0x1917920_0 .net "AandB", 0 0, L_0x1942850; 1 drivers -v0x19179c0_0 .net "AddSubSLTSum", 0 0, L_0x1942760; 1 drivers -v0x1917a60_0 .net "AxorB", 0 0, L_0x1942670; 1 drivers -v0x1917ae0_0 .net "B", 0 0, L_0x1943010; 1 drivers -v0x1917b90_0 .net "BornB", 0 0, L_0x1942120; 1 drivers -v0x1917c50_0 .net "CINandAxorB", 0 0, L_0x19429c0; 1 drivers -v0x1917cd0_0 .alias "Command", 2 0, v0x1928f70_0; -v0x1917d50_0 .net *"_s3", 0 0, L_0x19423f0; 1 drivers -v0x1917dd0_0 .net *"_s5", 0 0, L_0x19425d0; 1 drivers -v0x1917e70_0 .net "carryin", 0 0, L_0x1943140; 1 drivers -v0x1917f10_0 .net "carryout", 0 0, L_0x1942ab0; 1 drivers -v0x1917fb0_0 .net "nB", 0 0, L_0x1941d10; 1 drivers -v0x1918060_0 .net "nCmd2", 0 0, L_0x1942350; 1 drivers -v0x1918160_0 .net "subtract", 0 0, L_0x1942490; 1 drivers -L_0x19422b0 .part v0x192a0b0_0, 0, 1; -L_0x19423f0 .part v0x192a0b0_0, 2, 1; -L_0x19425d0 .part v0x192a0b0_0, 0, 1; -S_0x19172f0 .scope module, "mux0" "TwoInMux" 3 105, 3 8, S_0x1917200; - .timescale -9 -12; -L_0x1941ea0/d .functor NOT 1, L_0x19422b0, C4<0>, C4<0>, C4<0>; -L_0x1941ea0 .delay (10000,10000,10000) L_0x1941ea0/d; -L_0x1941f40/d .functor AND 1, L_0x1943010, L_0x1941ea0, C4<1>, C4<1>; -L_0x1941f40 .delay (20000,20000,20000) L_0x1941f40/d; -L_0x1942030/d .functor AND 1, L_0x1941d10, L_0x19422b0, C4<1>, C4<1>; -L_0x1942030 .delay (20000,20000,20000) L_0x1942030/d; -L_0x1942120/d .functor OR 1, L_0x1941f40, L_0x1942030, C4<0>, C4<0>; -L_0x1942120 .delay (20000,20000,20000) L_0x1942120/d; -v0x19173e0_0 .net "S", 0 0, L_0x19422b0; 1 drivers -v0x1917480_0 .alias "in0", 0 0, v0x1917ae0_0; -v0x1917520_0 .alias "in1", 0 0, v0x1917fb0_0; -v0x19175c0_0 .net "nS", 0 0, L_0x1941ea0; 1 drivers -v0x1917640_0 .net "out0", 0 0, L_0x1941f40; 1 drivers -v0x19176e0_0 .net "out1", 0 0, L_0x1942030; 1 drivers -v0x19177c0_0 .alias "outfinal", 0 0, v0x1917b90_0; -S_0x1915e60 .scope generate, "addbits[3]" "addbits[3]" 3 230, 3 230, S_0x1915cf0; - .timescale -9 -12; -P_0x1915f58 .param/l "i" 3 230, +C4<011>; -S_0x1915fd0 .scope module, "attempt" "MiddleAddSubSLT" 3 232, 3 89, S_0x1915e60; - .timescale -9 -12; -L_0x1942fb0/d .functor NOT 1, L_0x1944470, C4<0>, C4<0>, C4<0>; -L_0x1942fb0 .delay (10000,10000,10000) L_0x1942fb0/d; -L_0x1943750/d .functor NOT 1, L_0x19437f0, C4<0>, C4<0>, C4<0>; -L_0x1943750 .delay (10000,10000,10000) L_0x1943750/d; -L_0x1943890/d .functor AND 1, L_0x19439d0, L_0x1943750, C4<1>, C4<1>; -L_0x1943890 .delay (20000,20000,20000) L_0x1943890/d; -L_0x1943a70/d .functor XOR 1, L_0x1944340, L_0x1943520, C4<0>, C4<0>; -L_0x1943a70 .delay (40000,40000,40000) L_0x1943a70/d; -L_0x1943b60/d .functor XOR 1, L_0x1943a70, L_0x19445a0, C4<0>, C4<0>; -L_0x1943b60 .delay (40000,40000,40000) L_0x1943b60/d; -L_0x1943c50/d .functor AND 1, L_0x1944340, L_0x1943520, C4<1>, C4<1>; -L_0x1943c50 .delay (20000,20000,20000) L_0x1943c50/d; -L_0x1943dc0/d .functor AND 1, L_0x1943a70, L_0x19445a0, C4<1>, C4<1>; -L_0x1943dc0 .delay (20000,20000,20000) L_0x1943dc0/d; -L_0x1943eb0/d .functor OR 1, L_0x1943c50, L_0x1943dc0, C4<0>, C4<0>; -L_0x1943eb0 .delay (20000,20000,20000) L_0x1943eb0/d; -v0x19165b0_0 .net "A", 0 0, L_0x1944340; 1 drivers -v0x1916670_0 .net "AandB", 0 0, L_0x1943c50; 1 drivers -v0x1916710_0 .net "AddSubSLTSum", 0 0, L_0x1943b60; 1 drivers -v0x19167b0_0 .net "AxorB", 0 0, L_0x1943a70; 1 drivers -v0x1916830_0 .net "B", 0 0, L_0x1944470; 1 drivers -v0x19168e0_0 .net "BornB", 0 0, L_0x1943520; 1 drivers -v0x19169a0_0 .net "CINandAxorB", 0 0, L_0x1943dc0; 1 drivers -v0x1916a20_0 .alias "Command", 2 0, v0x1928f70_0; -v0x1916af0_0 .net *"_s3", 0 0, L_0x19437f0; 1 drivers -v0x1916b70_0 .net *"_s5", 0 0, L_0x19439d0; 1 drivers -v0x1916c70_0 .net "carryin", 0 0, L_0x19445a0; 1 drivers -v0x1916d10_0 .net "carryout", 0 0, L_0x1943eb0; 1 drivers -v0x1916e20_0 .net "nB", 0 0, L_0x1942fb0; 1 drivers -v0x1916ed0_0 .net "nCmd2", 0 0, L_0x1943750; 1 drivers -v0x1916ff0_0 .net "subtract", 0 0, L_0x1943890; 1 drivers -L_0x19436b0 .part v0x192a0b0_0, 0, 1; -L_0x19437f0 .part v0x192a0b0_0, 2, 1; -L_0x19439d0 .part v0x192a0b0_0, 0, 1; -S_0x19160c0 .scope module, "mux0" "TwoInMux" 3 105, 3 8, S_0x1915fd0; - .timescale -9 -12; -L_0x19432e0/d .functor NOT 1, L_0x19436b0, C4<0>, C4<0>, C4<0>; -L_0x19432e0 .delay (10000,10000,10000) L_0x19432e0/d; -L_0x1943340/d .functor AND 1, L_0x1944470, L_0x19432e0, C4<1>, C4<1>; -L_0x1943340 .delay (20000,20000,20000) L_0x1943340/d; -L_0x1943430/d .functor AND 1, L_0x1942fb0, L_0x19436b0, C4<1>, C4<1>; -L_0x1943430 .delay (20000,20000,20000) L_0x1943430/d; -L_0x1943520/d .functor OR 1, L_0x1943340, L_0x1943430, C4<0>, C4<0>; -L_0x1943520 .delay (20000,20000,20000) L_0x1943520/d; -v0x19161b0_0 .net "S", 0 0, L_0x19436b0; 1 drivers -v0x1916230_0 .alias "in0", 0 0, v0x1916830_0; -v0x19162b0_0 .alias "in1", 0 0, v0x1916e20_0; -v0x1916330_0 .net "nS", 0 0, L_0x19432e0; 1 drivers -v0x19163b0_0 .net "out0", 0 0, L_0x1943340; 1 drivers -v0x1916430_0 .net "out1", 0 0, L_0x1943430; 1 drivers -v0x1916510_0 .alias "outfinal", 0 0, v0x19168e0_0; -S_0x1912ab0 .scope module, "trial1" "AndNand32" 3 280, 3 154, S_0x18a5800; - .timescale -9 -12; -P_0x1912538 .param/l "size" 3 161, +C4<0100>; -v0x19129a0_0 .alias "A", 3 0, v0x1928d50_0; -v0x1915b10_0 .alias "AndNandOut", 3 0, v0x1929fb0_0; -v0x1915b90_0 .alias "B", 3 0, v0x1928e70_0; -v0x1915c40_0 .alias "Command", 2 0, v0x1928f70_0; -L_0x1947400 .part/pv L_0x1947190, 1, 1, 4; -L_0x19474c0 .part v0x1929e30_0, 1, 1; -L_0x1947560 .part v0x192a030_0, 1, 1; -L_0x1947e70 .part/pv L_0x1947c00, 2, 1, 4; -L_0x1947f10 .part v0x1929e30_0, 2, 1; -L_0x1947fb0 .part v0x192a030_0, 2, 1; -L_0x19488e0 .part/pv L_0x1948670, 3, 1, 4; -L_0x193a1c0 .part v0x1929e30_0, 3, 1; -L_0x1948b90 .part v0x192a030_0, 3, 1; -L_0x1949440 .part/pv L_0x19491d0, 0, 1, 4; -L_0x1949540 .part v0x1929e30_0, 0, 1; -L_0x19495e0 .part v0x192a030_0, 0, 1; -S_0x1914fd0 .scope module, "attempt2" "AndNand" 3 165, 3 48, S_0x1912ab0; - .timescale -9 -12; -L_0x1948c80/d .functor NAND 1, L_0x1949540, L_0x19495e0, C4<1>, C4<1>; -L_0x1948c80 .delay (10000,10000,10000) L_0x1948c80/d; -L_0x1948d80/d .functor NOT 1, L_0x1948c80, C4<0>, C4<0>, C4<0>; -L_0x1948d80 .delay (10000,10000,10000) L_0x1948d80/d; -v0x19155f0_0 .net "A", 0 0, L_0x1949540; 1 drivers -v0x19156b0_0 .net "AandB", 0 0, L_0x1948d80; 1 drivers -v0x1915730_0 .net "AnandB", 0 0, L_0x1948c80; 1 drivers -v0x19157e0_0 .net "AndNandOut", 0 0, L_0x19491d0; 1 drivers -v0x19158c0_0 .net "B", 0 0, L_0x19495e0; 1 drivers -v0x1915940_0 .alias "Command", 2 0, v0x1928f70_0; -L_0x19493a0 .part v0x192a0b0_0, 0, 1; -S_0x19150c0 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0x1914fd0; - .timescale -9 -12; -L_0x1948eb0/d .functor NOT 1, L_0x19493a0, C4<0>, C4<0>, C4<0>; -L_0x1948eb0 .delay (10000,10000,10000) L_0x1948eb0/d; -L_0x1948f70/d .functor AND 1, L_0x1948d80, L_0x1948eb0, C4<1>, C4<1>; -L_0x1948f70 .delay (20000,20000,20000) L_0x1948f70/d; -L_0x1949080/d .functor AND 1, L_0x1948c80, L_0x19493a0, C4<1>, C4<1>; -L_0x1949080 .delay (20000,20000,20000) L_0x1949080/d; -L_0x19491d0/d .functor OR 1, L_0x1948f70, L_0x1949080, C4<0>, C4<0>; -L_0x19491d0 .delay (20000,20000,20000) L_0x19491d0/d; -v0x19151b0_0 .net "S", 0 0, L_0x19493a0; 1 drivers -v0x1915230_0 .alias "in0", 0 0, v0x19156b0_0; -v0x19152b0_0 .alias "in1", 0 0, v0x1915730_0; -v0x1915350_0 .net "nS", 0 0, L_0x1948eb0; 1 drivers -v0x19153d0_0 .net "out0", 0 0, L_0x1948f70; 1 drivers -v0x1915470_0 .net "out1", 0 0, L_0x1949080; 1 drivers -v0x1915550_0 .alias "outfinal", 0 0, v0x19157e0_0; -S_0x1914410 .scope generate, "andbits[1]" "andbits[1]" 3 169, 3 169, S_0x1912ab0; - .timescale -9 -12; -P_0x1914508 .param/l "i" 3 169, +C4<01>; -S_0x1914580 .scope module, "attempt" "AndNand" 3 171, 3 48, S_0x1914410; - .timescale -9 -12; -L_0x1946c80/d .functor NAND 1, L_0x19474c0, L_0x1947560, C4<1>, C4<1>; -L_0x1946c80 .delay (10000,10000,10000) L_0x1946c80/d; -L_0x1946d40/d .functor NOT 1, L_0x1946c80, C4<0>, C4<0>, C4<0>; -L_0x1946d40 .delay (10000,10000,10000) L_0x1946d40/d; -v0x1914bc0_0 .net "A", 0 0, L_0x19474c0; 1 drivers -v0x1914c80_0 .net "AandB", 0 0, L_0x1946d40; 1 drivers -v0x1914d00_0 .net "AnandB", 0 0, L_0x1946c80; 1 drivers -v0x1914db0_0 .net "AndNandOut", 0 0, L_0x1947190; 1 drivers -v0x1914e90_0 .net "B", 0 0, L_0x1947560; 1 drivers -v0x1914f10_0 .alias "Command", 2 0, v0x1928f70_0; -L_0x1947360 .part v0x192a0b0_0, 0, 1; -S_0x1914670 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0x1914580; - .timescale -9 -12; -L_0x1946e70/d .functor NOT 1, L_0x1947360, C4<0>, C4<0>, C4<0>; -L_0x1946e70 .delay (10000,10000,10000) L_0x1946e70/d; -L_0x1946f30/d .functor AND 1, L_0x1946d40, L_0x1946e70, C4<1>, C4<1>; -L_0x1946f30 .delay (20000,20000,20000) L_0x1946f30/d; -L_0x1947040/d .functor AND 1, L_0x1946c80, L_0x1947360, C4<1>, C4<1>; -L_0x1947040 .delay (20000,20000,20000) L_0x1947040/d; -L_0x1947190/d .functor OR 1, L_0x1946f30, L_0x1947040, C4<0>, C4<0>; -L_0x1947190 .delay (20000,20000,20000) L_0x1947190/d; -v0x1914760_0 .net "S", 0 0, L_0x1947360; 1 drivers -v0x19147e0_0 .alias "in0", 0 0, v0x1914c80_0; -v0x1914880_0 .alias "in1", 0 0, v0x1914d00_0; -v0x1914920_0 .net "nS", 0 0, L_0x1946e70; 1 drivers -v0x19149a0_0 .net "out0", 0 0, L_0x1946f30; 1 drivers -v0x1914a40_0 .net "out1", 0 0, L_0x1947040; 1 drivers -v0x1914b20_0 .alias "outfinal", 0 0, v0x1914db0_0; -S_0x1913850 .scope generate, "andbits[2]" "andbits[2]" 3 169, 3 169, S_0x1912ab0; - .timescale -9 -12; -P_0x1913948 .param/l "i" 3 169, +C4<010>; -S_0x19139c0 .scope module, "attempt" "AndNand" 3 171, 3 48, S_0x1913850; - .timescale -9 -12; -L_0x1947650/d .functor NAND 1, L_0x1947f10, L_0x1947fb0, C4<1>, C4<1>; -L_0x1947650 .delay (10000,10000,10000) L_0x1947650/d; -L_0x19477b0/d .functor NOT 1, L_0x1947650, C4<0>, C4<0>, C4<0>; -L_0x19477b0 .delay (10000,10000,10000) L_0x19477b0/d; -v0x1914000_0 .net "A", 0 0, L_0x1947f10; 1 drivers -v0x19140c0_0 .net "AandB", 0 0, L_0x19477b0; 1 drivers -v0x1914140_0 .net "AnandB", 0 0, L_0x1947650; 1 drivers -v0x19141f0_0 .net "AndNandOut", 0 0, L_0x1947c00; 1 drivers -v0x19142d0_0 .net "B", 0 0, L_0x1947fb0; 1 drivers -v0x1914350_0 .alias "Command", 2 0, v0x1928f70_0; -L_0x1947dd0 .part v0x192a0b0_0, 0, 1; -S_0x1913ab0 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0x19139c0; - .timescale -9 -12; -L_0x19478e0/d .functor NOT 1, L_0x1947dd0, C4<0>, C4<0>, C4<0>; -L_0x19478e0 .delay (10000,10000,10000) L_0x19478e0/d; -L_0x19479a0/d .functor AND 1, L_0x19477b0, L_0x19478e0, C4<1>, C4<1>; -L_0x19479a0 .delay (20000,20000,20000) L_0x19479a0/d; -L_0x1947ab0/d .functor AND 1, L_0x1947650, L_0x1947dd0, C4<1>, C4<1>; -L_0x1947ab0 .delay (20000,20000,20000) L_0x1947ab0/d; -L_0x1947c00/d .functor OR 1, L_0x19479a0, L_0x1947ab0, C4<0>, C4<0>; -L_0x1947c00 .delay (20000,20000,20000) L_0x1947c00/d; -v0x1913ba0_0 .net "S", 0 0, L_0x1947dd0; 1 drivers -v0x1913c20_0 .alias "in0", 0 0, v0x19140c0_0; -v0x1913cc0_0 .alias "in1", 0 0, v0x1914140_0; -v0x1913d60_0 .net "nS", 0 0, L_0x19478e0; 1 drivers -v0x1913de0_0 .net "out0", 0 0, L_0x19479a0; 1 drivers -v0x1913e80_0 .net "out1", 0 0, L_0x1947ab0; 1 drivers -v0x1913f60_0 .alias "outfinal", 0 0, v0x19141f0_0; -S_0x1912c20 .scope generate, "andbits[3]" "andbits[3]" 3 169, 3 169, S_0x1912ab0; - .timescale -9 -12; -P_0x1912d18 .param/l "i" 3 169, +C4<011>; -S_0x1912db0 .scope module, "attempt" "AndNand" 3 171, 3 48, S_0x1912c20; - .timescale -9 -12; -L_0x19480e0/d .functor NAND 1, L_0x193a1c0, L_0x1948b90, C4<1>, C4<1>; -L_0x19480e0 .delay (10000,10000,10000) L_0x19480e0/d; -L_0x1948220/d .functor NOT 1, L_0x19480e0, C4<0>, C4<0>, C4<0>; -L_0x1948220 .delay (10000,10000,10000) L_0x1948220/d; -v0x1913440_0 .net "A", 0 0, L_0x193a1c0; 1 drivers -v0x1913500_0 .net "AandB", 0 0, L_0x1948220; 1 drivers -v0x1913580_0 .net "AnandB", 0 0, L_0x19480e0; 1 drivers -v0x1913630_0 .net "AndNandOut", 0 0, L_0x1948670; 1 drivers -v0x1913710_0 .net "B", 0 0, L_0x1948b90; 1 drivers -v0x1913790_0 .alias "Command", 2 0, v0x1928f70_0; -L_0x1948840 .part v0x192a0b0_0, 0, 1; -S_0x1912ea0 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0x1912db0; - .timescale -9 -12; -L_0x1948350/d .functor NOT 1, L_0x1948840, C4<0>, C4<0>, C4<0>; -L_0x1948350 .delay (10000,10000,10000) L_0x1948350/d; -L_0x1948410/d .functor AND 1, L_0x1948220, L_0x1948350, C4<1>, C4<1>; -L_0x1948410 .delay (20000,20000,20000) L_0x1948410/d; -L_0x1948520/d .functor AND 1, L_0x19480e0, L_0x1948840, C4<1>, C4<1>; -L_0x1948520 .delay (20000,20000,20000) L_0x1948520/d; -L_0x1948670/d .functor OR 1, L_0x1948410, L_0x1948520, C4<0>, C4<0>; -L_0x1948670 .delay (20000,20000,20000) L_0x1948670/d; -v0x1912f90_0 .net "S", 0 0, L_0x1948840; 1 drivers -v0x1913030_0 .alias "in0", 0 0, v0x1913500_0; -v0x19130d0_0 .alias "in1", 0 0, v0x1913580_0; -v0x1913170_0 .net "nS", 0 0, L_0x1948350; 1 drivers -v0x1913220_0 .net "out0", 0 0, L_0x1948410; 1 drivers -v0x19132c0_0 .net "out1", 0 0, L_0x1948520; 1 drivers -v0x19133a0_0 .alias "outfinal", 0 0, v0x1913630_0; -S_0x190d890 .scope module, "trial2" "OrNorXor32" 3 281, 3 177, S_0x18a5800; - .timescale -9 -12; -P_0x190c9e8 .param/l "size" 3 184, +C4<0100>; -v0x1912820_0 .alias "A", 3 0, v0x1928d50_0; -v0x19128a0_0 .alias "B", 3 0, v0x1928e70_0; -v0x1912920_0 .alias "Command", 2 0, v0x1928f70_0; -v0x1912a30_0 .alias "OrNorXorOut", 3 0, v0x192a1b0_0; -L_0x194a790 .part/pv L_0x194a520, 1, 1, 4; -L_0x194a830 .part v0x1929e30_0, 1, 1; -L_0x194a8d0 .part v0x192a030_0, 1, 1; -L_0x194ba90 .part/pv L_0x194b820, 2, 1, 4; -L_0x194bb30 .part v0x1929e30_0, 2, 1; -L_0x194bbd0 .part v0x192a030_0, 2, 1; -L_0x194cd90 .part/pv L_0x194cb20, 3, 1, 4; -L_0x194ce30 .part v0x1929e30_0, 3, 1; -L_0x194ced0 .part v0x192a030_0, 3, 1; -L_0x194e080 .part/pv L_0x194de10, 0, 1, 4; -L_0x194e180 .part v0x1929e30_0, 0, 1; -L_0x194e220 .part v0x192a030_0, 0, 1; -S_0x1911610 .scope module, "attempt2" "OrNorXor" 3 192, 3 64, S_0x190d890; - .timescale -9 -12; -L_0x194cf70/d .functor NOR 1, L_0x194e180, L_0x194e220, C4<0>, C4<0>; -L_0x194cf70 .delay (10000,10000,10000) L_0x194cf70/d; -L_0x194d070/d .functor NOT 1, L_0x194cf70, C4<0>, C4<0>, C4<0>; -L_0x194d070 .delay (10000,10000,10000) L_0x194d070/d; -L_0x194d1a0/d .functor NAND 1, L_0x194e180, L_0x194e220, C4<1>, C4<1>; -L_0x194d1a0 .delay (10000,10000,10000) L_0x194d1a0/d; -L_0x194d300/d .functor NAND 1, L_0x194d1a0, L_0x194d070, C4<1>, C4<1>; -L_0x194d300 .delay (10000,10000,10000) L_0x194d300/d; -L_0x194d410/d .functor NOT 1, L_0x194d300, C4<0>, C4<0>, C4<0>; -L_0x194d410 .delay (10000,10000,10000) L_0x194d410/d; -v0x1912160_0 .net "A", 0 0, L_0x194e180; 1 drivers -v0x1912200_0 .net "AnandB", 0 0, L_0x194d1a0; 1 drivers -v0x19122a0_0 .net "AnorB", 0 0, L_0x194cf70; 1 drivers -v0x1912320_0 .net "AorB", 0 0, L_0x194d070; 1 drivers -v0x1912400_0 .net "AxorB", 0 0, L_0x194d410; 1 drivers -v0x19124b0_0 .net "B", 0 0, L_0x194e220; 1 drivers -v0x1912570_0 .alias "Command", 2 0, v0x1928f70_0; -v0x19125f0_0 .net "OrNorXorOut", 0 0, L_0x194de10; 1 drivers -v0x1912670_0 .net "XorNor", 0 0, L_0x194d890; 1 drivers -v0x1912740_0 .net "nXor", 0 0, L_0x194d300; 1 drivers -L_0x194da10 .part v0x192a0b0_0, 2, 1; -L_0x194dfe0 .part v0x192a0b0_0, 0, 1; -S_0x1911bf0 .scope module, "mux0" "TwoInMux" 3 83, 3 8, S_0x1911610; - .timescale -9 -12; -L_0x194d570/d .functor NOT 1, L_0x194da10, C4<0>, C4<0>, C4<0>; -L_0x194d570 .delay (10000,10000,10000) L_0x194d570/d; -L_0x194d630/d .functor AND 1, L_0x194d410, L_0x194d570, C4<1>, C4<1>; -L_0x194d630 .delay (20000,20000,20000) L_0x194d630/d; -L_0x194d740/d .functor AND 1, L_0x194cf70, L_0x194da10, C4<1>, C4<1>; -L_0x194d740 .delay (20000,20000,20000) L_0x194d740/d; -L_0x194d890/d .functor OR 1, L_0x194d630, L_0x194d740, C4<0>, C4<0>; -L_0x194d890 .delay (20000,20000,20000) L_0x194d890/d; -v0x1911ce0_0 .net "S", 0 0, L_0x194da10; 1 drivers -v0x1911da0_0 .alias "in0", 0 0, v0x1912400_0; -v0x1911e40_0 .alias "in1", 0 0, v0x19122a0_0; -v0x1911ee0_0 .net "nS", 0 0, L_0x194d570; 1 drivers -v0x1911f60_0 .net "out0", 0 0, L_0x194d630; 1 drivers -v0x1912000_0 .net "out1", 0 0, L_0x194d740; 1 drivers -v0x19120e0_0 .alias "outfinal", 0 0, v0x1912670_0; -S_0x1911700 .scope module, "mux1" "TwoInMux" 3 84, 3 8, S_0x1911610; - .timescale -9 -12; -L_0x194dab0/d .functor NOT 1, L_0x194dfe0, C4<0>, C4<0>, C4<0>; -L_0x194dab0 .delay (10000,10000,10000) L_0x194dab0/d; -L_0x194db70/d .functor AND 1, L_0x194d890, L_0x194dab0, C4<1>, C4<1>; -L_0x194db70 .delay (20000,20000,20000) L_0x194db70/d; -L_0x194dcc0/d .functor AND 1, L_0x194d070, L_0x194dfe0, C4<1>, C4<1>; -L_0x194dcc0 .delay (20000,20000,20000) L_0x194dcc0/d; -L_0x194de10/d .functor OR 1, L_0x194db70, L_0x194dcc0, C4<0>, C4<0>; -L_0x194de10 .delay (20000,20000,20000) L_0x194de10/d; -v0x19117f0_0 .net "S", 0 0, L_0x194dfe0; 1 drivers -v0x1911870_0 .alias "in0", 0 0, v0x1912670_0; -v0x19118f0_0 .alias "in1", 0 0, v0x1912320_0; -v0x1911990_0 .net "nS", 0 0, L_0x194dab0; 1 drivers -v0x1911a10_0 .net "out0", 0 0, L_0x194db70; 1 drivers -v0x1911ab0_0 .net "out1", 0 0, L_0x194dcc0; 1 drivers -v0x1911b50_0 .alias "outfinal", 0 0, v0x19125f0_0; -S_0x1910210 .scope generate, "orbits[1]" "orbits[1]" 3 196, 3 196, S_0x190d890; - .timescale -9 -12; -P_0x190fef8 .param/l "i" 3 196, +C4<01>; -S_0x1910340 .scope module, "attempt" "OrNorXor" 3 198, 3 64, S_0x1910210; - .timescale -9 -12; -L_0x19494e0/d .functor NOR 1, L_0x194a830, L_0x194a8d0, C4<0>, C4<0>; -L_0x19494e0 .delay (10000,10000,10000) L_0x19494e0/d; -L_0x1949780/d .functor NOT 1, L_0x19494e0, C4<0>, C4<0>, C4<0>; -L_0x1949780 .delay (10000,10000,10000) L_0x1949780/d; -L_0x19498b0/d .functor NAND 1, L_0x194a830, L_0x194a8d0, C4<1>, C4<1>; -L_0x19498b0 .delay (10000,10000,10000) L_0x19498b0/d; -L_0x1949a10/d .functor NAND 1, L_0x19498b0, L_0x1949780, C4<1>, C4<1>; -L_0x1949a10 .delay (10000,10000,10000) L_0x1949a10/d; -L_0x1949b20/d .functor NOT 1, L_0x1949a10, C4<0>, C4<0>, C4<0>; -L_0x1949b20 .delay (10000,10000,10000) L_0x1949b20/d; -v0x1910ed0_0 .net "A", 0 0, L_0x194a830; 1 drivers -v0x1910f70_0 .net "AnandB", 0 0, L_0x19498b0; 1 drivers -v0x1911010_0 .net "AnorB", 0 0, L_0x19494e0; 1 drivers -v0x19110c0_0 .net "AorB", 0 0, L_0x1949780; 1 drivers -v0x19111a0_0 .net "AxorB", 0 0, L_0x1949b20; 1 drivers -v0x1911250_0 .net "B", 0 0, L_0x194a8d0; 1 drivers -v0x1911310_0 .alias "Command", 2 0, v0x1928f70_0; -v0x1911390_0 .net "OrNorXorOut", 0 0, L_0x194a520; 1 drivers -v0x1911460_0 .net "XorNor", 0 0, L_0x1949fa0; 1 drivers -v0x1911530_0 .net "nXor", 0 0, L_0x1949a10; 1 drivers -L_0x194a120 .part v0x192a0b0_0, 2, 1; -L_0x194a6f0 .part v0x192a0b0_0, 0, 1; -S_0x1910960 .scope module, "mux0" "TwoInMux" 3 83, 3 8, S_0x1910340; - .timescale -9 -12; -L_0x1949c80/d .functor NOT 1, L_0x194a120, C4<0>, C4<0>, C4<0>; -L_0x1949c80 .delay (10000,10000,10000) L_0x1949c80/d; -L_0x1949d40/d .functor AND 1, L_0x1949b20, L_0x1949c80, C4<1>, C4<1>; -L_0x1949d40 .delay (20000,20000,20000) L_0x1949d40/d; -L_0x1949e50/d .functor AND 1, L_0x19494e0, L_0x194a120, C4<1>, C4<1>; -L_0x1949e50 .delay (20000,20000,20000) L_0x1949e50/d; -L_0x1949fa0/d .functor OR 1, L_0x1949d40, L_0x1949e50, C4<0>, C4<0>; -L_0x1949fa0 .delay (20000,20000,20000) L_0x1949fa0/d; -v0x1910a50_0 .net "S", 0 0, L_0x194a120; 1 drivers -v0x1910b10_0 .alias "in0", 0 0, v0x19111a0_0; -v0x1910bb0_0 .alias "in1", 0 0, v0x1911010_0; -v0x1910c50_0 .net "nS", 0 0, L_0x1949c80; 1 drivers -v0x1910cd0_0 .net "out0", 0 0, L_0x1949d40; 1 drivers -v0x1910d70_0 .net "out1", 0 0, L_0x1949e50; 1 drivers -v0x1910e50_0 .alias "outfinal", 0 0, v0x1911460_0; -S_0x1910430 .scope module, "mux1" "TwoInMux" 3 84, 3 8, S_0x1910340; - .timescale -9 -12; -L_0x194a1c0/d .functor NOT 1, L_0x194a6f0, C4<0>, C4<0>, C4<0>; -L_0x194a1c0 .delay (10000,10000,10000) L_0x194a1c0/d; -L_0x194a280/d .functor AND 1, L_0x1949fa0, L_0x194a1c0, C4<1>, C4<1>; -L_0x194a280 .delay (20000,20000,20000) L_0x194a280/d; -L_0x194a3d0/d .functor AND 1, L_0x1949780, L_0x194a6f0, C4<1>, C4<1>; -L_0x194a3d0 .delay (20000,20000,20000) L_0x194a3d0/d; -L_0x194a520/d .functor OR 1, L_0x194a280, L_0x194a3d0, C4<0>, C4<0>; -L_0x194a520 .delay (20000,20000,20000) L_0x194a520/d; -v0x1910520_0 .net "S", 0 0, L_0x194a6f0; 1 drivers -v0x19105a0_0 .alias "in0", 0 0, v0x1911460_0; -v0x1910620_0 .alias "in1", 0 0, v0x19110c0_0; -v0x19106c0_0 .net "nS", 0 0, L_0x194a1c0; 1 drivers -v0x1910740_0 .net "out0", 0 0, L_0x194a280; 1 drivers -v0x19107e0_0 .net "out1", 0 0, L_0x194a3d0; 1 drivers -v0x19108c0_0 .alias "outfinal", 0 0, v0x1911390_0; -S_0x190edf0 .scope generate, "orbits[2]" "orbits[2]" 3 196, 3 196, S_0x190d890; - .timescale -9 -12; -P_0x190eb68 .param/l "i" 3 196, +C4<010>; -S_0x190ef20 .scope module, "attempt" "OrNorXor" 3 198, 3 64, S_0x190edf0; - .timescale -9 -12; -L_0x194a970/d .functor NOR 1, L_0x194bb30, L_0x194bbd0, C4<0>, C4<0>; -L_0x194a970 .delay (10000,10000,10000) L_0x194a970/d; -L_0x194aa80/d .functor NOT 1, L_0x194a970, C4<0>, C4<0>, C4<0>; -L_0x194aa80 .delay (10000,10000,10000) L_0x194aa80/d; -L_0x194abb0/d .functor NAND 1, L_0x194bb30, L_0x194bbd0, C4<1>, C4<1>; -L_0x194abb0 .delay (10000,10000,10000) L_0x194abb0/d; -L_0x194ad10/d .functor NAND 1, L_0x194abb0, L_0x194aa80, C4<1>, C4<1>; -L_0x194ad10 .delay (10000,10000,10000) L_0x194ad10/d; -L_0x194ae20/d .functor NOT 1, L_0x194ad10, C4<0>, C4<0>, C4<0>; -L_0x194ae20 .delay (10000,10000,10000) L_0x194ae20/d; -v0x190faf0_0 .net "A", 0 0, L_0x194bb30; 1 drivers -v0x190fb90_0 .net "AnandB", 0 0, L_0x194abb0; 1 drivers -v0x190fc30_0 .net "AnorB", 0 0, L_0x194a970; 1 drivers -v0x190fce0_0 .net "AorB", 0 0, L_0x194aa80; 1 drivers -v0x190fdc0_0 .net "AxorB", 0 0, L_0x194ae20; 1 drivers -v0x190fe70_0 .net "B", 0 0, L_0x194bbd0; 1 drivers -v0x190ff30_0 .alias "Command", 2 0, v0x1928f70_0; -v0x190ffb0_0 .net "OrNorXorOut", 0 0, L_0x194b820; 1 drivers -v0x1910060_0 .net "XorNor", 0 0, L_0x194b2a0; 1 drivers -v0x1910130_0 .net "nXor", 0 0, L_0x194ad10; 1 drivers -L_0x194b420 .part v0x192a0b0_0, 2, 1; -L_0x194b9f0 .part v0x192a0b0_0, 0, 1; -S_0x190f580 .scope module, "mux0" "TwoInMux" 3 83, 3 8, S_0x190ef20; - .timescale -9 -12; -L_0x194af80/d .functor NOT 1, L_0x194b420, C4<0>, C4<0>, C4<0>; -L_0x194af80 .delay (10000,10000,10000) L_0x194af80/d; -L_0x194b040/d .functor AND 1, L_0x194ae20, L_0x194af80, C4<1>, C4<1>; -L_0x194b040 .delay (20000,20000,20000) L_0x194b040/d; -L_0x194b150/d .functor AND 1, L_0x194a970, L_0x194b420, C4<1>, C4<1>; -L_0x194b150 .delay (20000,20000,20000) L_0x194b150/d; -L_0x194b2a0/d .functor OR 1, L_0x194b040, L_0x194b150, C4<0>, C4<0>; -L_0x194b2a0 .delay (20000,20000,20000) L_0x194b2a0/d; -v0x190f670_0 .net "S", 0 0, L_0x194b420; 1 drivers -v0x190f730_0 .alias "in0", 0 0, v0x190fdc0_0; -v0x190f7d0_0 .alias "in1", 0 0, v0x190fc30_0; -v0x190f870_0 .net "nS", 0 0, L_0x194af80; 1 drivers -v0x190f8f0_0 .net "out0", 0 0, L_0x194b040; 1 drivers -v0x190f990_0 .net "out1", 0 0, L_0x194b150; 1 drivers -v0x190fa70_0 .alias "outfinal", 0 0, v0x1910060_0; -S_0x190f010 .scope module, "mux1" "TwoInMux" 3 84, 3 8, S_0x190ef20; - .timescale -9 -12; -L_0x194b4c0/d .functor NOT 1, L_0x194b9f0, C4<0>, C4<0>, C4<0>; -L_0x194b4c0 .delay (10000,10000,10000) L_0x194b4c0/d; -L_0x194b580/d .functor AND 1, L_0x194b2a0, L_0x194b4c0, C4<1>, C4<1>; -L_0x194b580 .delay (20000,20000,20000) L_0x194b580/d; -L_0x194b6d0/d .functor AND 1, L_0x194aa80, L_0x194b9f0, C4<1>, C4<1>; -L_0x194b6d0 .delay (20000,20000,20000) L_0x194b6d0/d; -L_0x194b820/d .functor OR 1, L_0x194b580, L_0x194b6d0, C4<0>, C4<0>; -L_0x194b820 .delay (20000,20000,20000) L_0x194b820/d; -v0x190f100_0 .net "S", 0 0, L_0x194b9f0; 1 drivers -v0x190f1a0_0 .alias "in0", 0 0, v0x1910060_0; -v0x190f240_0 .alias "in1", 0 0, v0x190fce0_0; -v0x190f2e0_0 .net "nS", 0 0, L_0x194b4c0; 1 drivers -v0x190f360_0 .net "out0", 0 0, L_0x194b580; 1 drivers -v0x190f400_0 .net "out1", 0 0, L_0x194b6d0; 1 drivers -v0x190f4e0_0 .alias "outfinal", 0 0, v0x190ffb0_0; -S_0x190da00 .scope generate, "orbits[3]" "orbits[3]" 3 196, 3 196, S_0x190d890; - .timescale -9 -12; -P_0x190daf8 .param/l "i" 3 196, +C4<011>; -S_0x190db90 .scope module, "attempt" "OrNorXor" 3 198, 3 64, S_0x190da00; - .timescale -9 -12; -L_0x194bcb0/d .functor NOR 1, L_0x194ce30, L_0x194ced0, C4<0>, C4<0>; -L_0x194bcb0 .delay (10000,10000,10000) L_0x194bcb0/d; -L_0x194bda0/d .functor NOT 1, L_0x194bcb0, C4<0>, C4<0>, C4<0>; -L_0x194bda0 .delay (10000,10000,10000) L_0x194bda0/d; -L_0x194beb0/d .functor NAND 1, L_0x194ce30, L_0x194ced0, C4<1>, C4<1>; -L_0x194beb0 .delay (10000,10000,10000) L_0x194beb0/d; -L_0x194c010/d .functor NAND 1, L_0x194beb0, L_0x194bda0, C4<1>, C4<1>; -L_0x194c010 .delay (10000,10000,10000) L_0x194c010/d; -L_0x194c120/d .functor NOT 1, L_0x194c010, C4<0>, C4<0>, C4<0>; -L_0x194c120 .delay (10000,10000,10000) L_0x194c120/d; -v0x190e760_0 .net "A", 0 0, L_0x194ce30; 1 drivers -v0x190e800_0 .net "AnandB", 0 0, L_0x194beb0; 1 drivers -v0x190e8a0_0 .net "AnorB", 0 0, L_0x194bcb0; 1 drivers -v0x190e950_0 .net "AorB", 0 0, L_0x194bda0; 1 drivers -v0x190ea30_0 .net "AxorB", 0 0, L_0x194c120; 1 drivers -v0x190eae0_0 .net "B", 0 0, L_0x194ced0; 1 drivers -v0x190eba0_0 .alias "Command", 2 0, v0x1928f70_0; -v0x190ec20_0 .net "OrNorXorOut", 0 0, L_0x194cb20; 1 drivers -v0x190eca0_0 .net "XorNor", 0 0, L_0x194c5a0; 1 drivers -v0x190ed70_0 .net "nXor", 0 0, L_0x194c010; 1 drivers -L_0x194c720 .part v0x192a0b0_0, 2, 1; -L_0x194ccf0 .part v0x192a0b0_0, 0, 1; -S_0x190e1f0 .scope module, "mux0" "TwoInMux" 3 83, 3 8, S_0x190db90; - .timescale -9 -12; -L_0x194c280/d .functor NOT 1, L_0x194c720, C4<0>, C4<0>, C4<0>; -L_0x194c280 .delay (10000,10000,10000) L_0x194c280/d; -L_0x194c340/d .functor AND 1, L_0x194c120, L_0x194c280, C4<1>, C4<1>; -L_0x194c340 .delay (20000,20000,20000) L_0x194c340/d; -L_0x194c450/d .functor AND 1, L_0x194bcb0, L_0x194c720, C4<1>, C4<1>; -L_0x194c450 .delay (20000,20000,20000) L_0x194c450/d; -L_0x194c5a0/d .functor OR 1, L_0x194c340, L_0x194c450, C4<0>, C4<0>; -L_0x194c5a0 .delay (20000,20000,20000) L_0x194c5a0/d; -v0x190e2e0_0 .net "S", 0 0, L_0x194c720; 1 drivers -v0x190e3a0_0 .alias "in0", 0 0, v0x190ea30_0; -v0x190e440_0 .alias "in1", 0 0, v0x190e8a0_0; -v0x190e4e0_0 .net "nS", 0 0, L_0x194c280; 1 drivers -v0x190e560_0 .net "out0", 0 0, L_0x194c340; 1 drivers -v0x190e600_0 .net "out1", 0 0, L_0x194c450; 1 drivers -v0x190e6e0_0 .alias "outfinal", 0 0, v0x190eca0_0; -S_0x190dc80 .scope module, "mux1" "TwoInMux" 3 84, 3 8, S_0x190db90; - .timescale -9 -12; -L_0x194c7c0/d .functor NOT 1, L_0x194ccf0, C4<0>, C4<0>, C4<0>; -L_0x194c7c0 .delay (10000,10000,10000) L_0x194c7c0/d; -L_0x194c880/d .functor AND 1, L_0x194c5a0, L_0x194c7c0, C4<1>, C4<1>; -L_0x194c880 .delay (20000,20000,20000) L_0x194c880/d; -L_0x194c9d0/d .functor AND 1, L_0x194bda0, L_0x194ccf0, C4<1>, C4<1>; -L_0x194c9d0 .delay (20000,20000,20000) L_0x194c9d0/d; -L_0x194cb20/d .functor OR 1, L_0x194c880, L_0x194c9d0, C4<0>, C4<0>; -L_0x194cb20 .delay (20000,20000,20000) L_0x194cb20/d; -v0x190dd70_0 .net "S", 0 0, L_0x194ccf0; 1 drivers -v0x190de10_0 .alias "in0", 0 0, v0x190eca0_0; -v0x190deb0_0 .alias "in1", 0 0, v0x190e950_0; -v0x190df50_0 .net "nS", 0 0, L_0x194c7c0; 1 drivers -v0x190dfd0_0 .net "out0", 0 0, L_0x194c880; 1 drivers -v0x190e070_0 .net "out1", 0 0, L_0x194c9d0; 1 drivers -v0x190e150_0 .alias "outfinal", 0 0, v0x190ec20_0; -S_0x190cf10 .scope module, "ZeroMux0case" "FourInMux" 3 283, 3 24, S_0x18a5800; - .timescale -9 -12; -L_0x194e120/d .functor NOT 1, L_0x1940830, C4<0>, C4<0>, C4<0>; -L_0x194e120 .delay (10000,10000,10000) L_0x194e120/d; -L_0x194e370/d .functor NOT 1, L_0x1940960, C4<0>, C4<0>, C4<0>; -L_0x194e370 .delay (10000,10000,10000) L_0x194e370/d; -L_0x194e430/d .functor NAND 1, L_0x194e120, L_0x194e370, L_0x194ea60, C4<1>; -L_0x194e430 .delay (10000,10000,10000) L_0x194e430/d; -L_0x194e520/d .functor NAND 1, L_0x1940830, L_0x194e370, L_0x194eb00, C4<1>; -L_0x194e520 .delay (10000,10000,10000) L_0x194e520/d; -L_0x194e610/d .functor NAND 1, L_0x194e120, L_0x1940960, L_0x194eba0, C4<1>; -L_0x194e610 .delay (10000,10000,10000) L_0x194e610/d; -L_0x194e700/d .functor NAND 1, L_0x1940830, L_0x1940960, L_0x194ef80, C4<1>; -L_0x194e700 .delay (10000,10000,10000) L_0x194e700/d; -L_0x194e7e0/d .functor NAND 1, L_0x194e430, L_0x194e520, L_0x194e610, L_0x194e700; -L_0x194e7e0 .delay (10000,10000,10000) L_0x194e7e0/d; -v0x190d000_0 .net "S0", 0 0, L_0x1940830; 1 drivers -v0x190d0c0_0 .net "S1", 0 0, L_0x1940960; 1 drivers -v0x190d160_0 .net "in0", 0 0, L_0x194ea60; 1 drivers -v0x190d200_0 .net "in1", 0 0, L_0x194eb00; 1 drivers -v0x190d280_0 .net "in2", 0 0, L_0x194eba0; 1 drivers -v0x190d320_0 .net "in3", 0 0, L_0x194ef80; 1 drivers -v0x190d3c0_0 .net "nS0", 0 0, L_0x194e120; 1 drivers -v0x190d460_0 .net "nS1", 0 0, L_0x194e370; 1 drivers -v0x190d500_0 .net "out", 0 0, L_0x194e7e0; 1 drivers -v0x190d5a0_0 .net "out0", 0 0, L_0x194e430; 1 drivers -v0x190d640_0 .net "out1", 0 0, L_0x194e520; 1 drivers -v0x190d6e0_0 .net "out2", 0 0, L_0x194e610; 1 drivers -v0x190d7f0_0 .net "out3", 0 0, L_0x194e700; 1 drivers -S_0x190c550 .scope module, "OneMux0case" "FourInMux" 3 284, 3 24, S_0x18a5800; - .timescale -9 -12; -L_0x194ed00/d .functor NOT 1, L_0x194f890, C4<0>, C4<0>, C4<0>; -L_0x194ed00 .delay (10000,10000,10000) L_0x194ed00/d; -L_0x194edf0/d .functor NOT 1, L_0x194f070, C4<0>, C4<0>, C4<0>; -L_0x194edf0 .delay (10000,10000,10000) L_0x194edf0/d; -L_0x194ee90/d .functor NAND 1, L_0x194ed00, L_0x194edf0, L_0x194f1a0, C4<1>; -L_0x194ee90 .delay (10000,10000,10000) L_0x194ee90/d; -L_0x194f350/d .functor NAND 1, L_0x194f890, L_0x194edf0, L_0x194fc20, C4<1>; -L_0x194f350 .delay (10000,10000,10000) L_0x194f350/d; -L_0x194f440/d .functor NAND 1, L_0x194ed00, L_0x194f070, L_0x194fcc0, C4<1>; -L_0x194f440 .delay (10000,10000,10000) L_0x194f440/d; -L_0x194f530/d .functor NAND 1, L_0x194f890, L_0x194f070, L_0x194f9c0, C4<1>; -L_0x194f530 .delay (10000,10000,10000) L_0x194f530/d; -L_0x194f610/d .functor NAND 1, L_0x194ee90, L_0x194f350, L_0x194f440, L_0x194f530; -L_0x194f610 .delay (10000,10000,10000) L_0x194f610/d; -v0x190c640_0 .net "S0", 0 0, L_0x194f890; 1 drivers -v0x190c700_0 .net "S1", 0 0, L_0x194f070; 1 drivers -v0x190c7a0_0 .net "in0", 0 0, L_0x194f1a0; 1 drivers -v0x190c840_0 .net "in1", 0 0, L_0x194fc20; 1 drivers -v0x190c8c0_0 .net "in2", 0 0, L_0x194fcc0; 1 drivers -v0x190c960_0 .net "in3", 0 0, L_0x194f9c0; 1 drivers -v0x190ca40_0 .net "nS0", 0 0, L_0x194ed00; 1 drivers -v0x190cae0_0 .net "nS1", 0 0, L_0x194edf0; 1 drivers -v0x190cb80_0 .net "out", 0 0, L_0x194f610; 1 drivers -v0x190cc20_0 .net "out0", 0 0, L_0x194ee90; 1 drivers -v0x190ccc0_0 .net "out1", 0 0, L_0x194f350; 1 drivers -v0x190cd60_0 .net "out2", 0 0, L_0x194f440; 1 drivers -v0x190ce70_0 .net "out3", 0 0, L_0x194f530; 1 drivers -S_0x190c000 .scope module, "TwoMux0case" "TwoInMux" 3 285, 3 8, S_0x18a5800; - .timescale -9 -12; -L_0x194fab0/d .functor NOT 1, L_0x194fd60, C4<0>, C4<0>, C4<0>; -L_0x194fab0 .delay (10000,10000,10000) L_0x194fab0/d; -L_0x194fba0/d .functor AND 1, L_0x194fe00, L_0x194fab0, C4<1>, C4<1>; -L_0x194fba0 .delay (20000,20000,20000) L_0x194fba0/d; -L_0x1950060/d .functor AND 1, L_0x194fef0, L_0x194fd60, C4<1>, C4<1>; -L_0x1950060 .delay (20000,20000,20000) L_0x1950060/d; -L_0x1950150/d .functor OR 1, L_0x194fba0, L_0x1950060, C4<0>, C4<0>; -L_0x1950150 .delay (20000,20000,20000) L_0x1950150/d; -v0x190c0f0_0 .net "S", 0 0, L_0x194fd60; 1 drivers -v0x190c1b0_0 .net "in0", 0 0, L_0x194fe00; 1 drivers -v0x190c250_0 .net "in1", 0 0, L_0x194fef0; 1 drivers -v0x190c2f0_0 .net "nS", 0 0, L_0x194fab0; 1 drivers -v0x190c370_0 .net "out0", 0 0, L_0x194fba0; 1 drivers -v0x190c410_0 .net "out1", 0 0, L_0x1950060; 1 drivers -v0x190c4b0_0 .net "outfinal", 0 0, L_0x1950150; 1 drivers -S_0x190a480 .scope generate, "muxbits[1]" "muxbits[1]" 3 290, 3 290, S_0x18a5800; - .timescale -9 -12; -P_0x1909478 .param/l "i" 3 290, +C4<01>; -L_0x193adc0/d .functor OR 1, L_0x193aec0, L_0x193ac80, C4<0>, C4<0>; -L_0x193adc0 .delay (20000,20000,20000) L_0x193adc0/d; -v0x190bea0_0 .net *"_s15", 0 0, L_0x193aec0; 1 drivers -v0x190bf60_0 .net *"_s16", 0 0, L_0x193ac80; 1 drivers -S_0x190b520 .scope module, "ZeroMux" "FourInMux" 3 292, 3 24, S_0x190a480; - .timescale -9 -12; -L_0x1938400/d .functor NOT 1, L_0x1938ea0, C4<0>, C4<0>, C4<0>; -L_0x1938400 .delay (10000,10000,10000) L_0x1938400/d; -L_0x1938650/d .functor NOT 1, L_0x1938fd0, C4<0>, C4<0>, C4<0>; -L_0x1938650 .delay (10000,10000,10000) L_0x1938650/d; -L_0x19386f0/d .functor NAND 1, L_0x1938400, L_0x1938650, L_0x1939100, C4<1>; -L_0x19386f0 .delay (10000,10000,10000) L_0x19386f0/d; -L_0x19387e0/d .functor NAND 1, L_0x1938ea0, L_0x1938650, L_0x19391a0, C4<1>; -L_0x19387e0 .delay (10000,10000,10000) L_0x19387e0/d; -L_0x1938930/d .functor NAND 1, L_0x1938400, L_0x1938fd0, L_0x1939240, C4<1>; -L_0x1938930 .delay (10000,10000,10000) L_0x1938930/d; -L_0x1938a80/d .functor NAND 1, L_0x1938ea0, L_0x1938fd0, L_0x1939440, C4<1>; -L_0x1938a80 .delay (10000,10000,10000) L_0x1938a80/d; -L_0x1938bf0/d .functor NAND 1, L_0x19386f0, L_0x19387e0, L_0x1938930, L_0x1938a80; -L_0x1938bf0 .delay (10000,10000,10000) L_0x1938bf0/d; -v0x190b610_0 .net "S0", 0 0, L_0x1938ea0; 1 drivers -v0x190b6d0_0 .net "S1", 0 0, L_0x1938fd0; 1 drivers -v0x190b770_0 .net "in0", 0 0, L_0x1939100; 1 drivers -v0x190b810_0 .net "in1", 0 0, L_0x19391a0; 1 drivers -v0x190b890_0 .net "in2", 0 0, L_0x1939240; 1 drivers -v0x190b930_0 .net "in3", 0 0, L_0x1939440; 1 drivers -v0x190b9d0_0 .net "nS0", 0 0, L_0x1938400; 1 drivers -v0x190ba70_0 .net "nS1", 0 0, L_0x1938650; 1 drivers -v0x190bb10_0 .net "out", 0 0, L_0x1938bf0; 1 drivers -v0x190bbb0_0 .net "out0", 0 0, L_0x19386f0; 1 drivers -v0x190bc50_0 .net "out1", 0 0, L_0x19387e0; 1 drivers -v0x190bcf0_0 .net "out2", 0 0, L_0x1938930; 1 drivers -v0x190be00_0 .net "out3", 0 0, L_0x1938a80; 1 drivers -S_0x190ab60 .scope module, "OneMux" "FourInMux" 3 293, 3 24, S_0x190a480; - .timescale -9 -12; -L_0x19394e0/d .functor NOT 1, L_0x1939e60, C4<0>, C4<0>, C4<0>; -L_0x19394e0 .delay (10000,10000,10000) L_0x19394e0/d; -L_0x19395d0/d .functor NOT 1, L_0x1939f90, C4<0>, C4<0>, C4<0>; -L_0x19395d0 .delay (10000,10000,10000) L_0x19395d0/d; -L_0x1939670/d .functor NAND 1, L_0x19394e0, L_0x19395d0, L_0x193a120, C4<1>; -L_0x1939670 .delay (10000,10000,10000) L_0x1939670/d; -L_0x19397b0/d .functor NAND 1, L_0x1939e60, L_0x19395d0, L_0x193a2d0, C4<1>; -L_0x19397b0 .delay (10000,10000,10000) L_0x19397b0/d; -L_0x19398a0/d .functor NAND 1, L_0x19394e0, L_0x1939f90, L_0x193a370, C4<1>; -L_0x19398a0 .delay (10000,10000,10000) L_0x19398a0/d; -L_0x19399f0/d .functor NAND 1, L_0x1939e60, L_0x1939f90, L_0x193a410, C4<1>; -L_0x19399f0 .delay (10000,10000,10000) L_0x19399f0/d; -L_0x1939b60/d .functor NAND 1, L_0x1939670, L_0x19397b0, L_0x19398a0, L_0x19399f0; -L_0x1939b60 .delay (10000,10000,10000) L_0x1939b60/d; -v0x190ac50_0 .net "S0", 0 0, L_0x1939e60; 1 drivers -v0x190ad10_0 .net "S1", 0 0, L_0x1939f90; 1 drivers -v0x190adb0_0 .net "in0", 0 0, L_0x193a120; 1 drivers -v0x190ae50_0 .net "in1", 0 0, L_0x193a2d0; 1 drivers -v0x190aed0_0 .net "in2", 0 0, L_0x193a370; 1 drivers -v0x190af70_0 .net "in3", 0 0, L_0x193a410; 1 drivers -v0x190b050_0 .net "nS0", 0 0, L_0x19394e0; 1 drivers -v0x190b0f0_0 .net "nS1", 0 0, L_0x19395d0; 1 drivers -v0x190b190_0 .net "out", 0 0, L_0x1939b60; 1 drivers -v0x190b230_0 .net "out0", 0 0, L_0x1939670; 1 drivers -v0x190b2d0_0 .net "out1", 0 0, L_0x19397b0; 1 drivers -v0x190b370_0 .net "out2", 0 0, L_0x19398a0; 1 drivers -v0x190b480_0 .net "out3", 0 0, L_0x19399f0; 1 drivers -S_0x190a5f0 .scope module, "TwoMux" "TwoInMux" 3 294, 3 8, S_0x190a480; - .timescale -9 -12; -L_0x193a0c0/d .functor NOT 1, L_0x193a960, C4<0>, C4<0>, C4<0>; -L_0x193a0c0 .delay (10000,10000,10000) L_0x193a0c0/d; -L_0x193a550/d .functor AND 1, L_0x193aa00, L_0x193a0c0, C4<1>, C4<1>; -L_0x193a550 .delay (20000,20000,20000) L_0x193a550/d; -L_0x193a640/d .functor AND 1, L_0x193ab40, L_0x193a960, C4<1>, C4<1>; -L_0x193a640 .delay (20000,20000,20000) L_0x193a640/d; -L_0x193a730/d .functor OR 1, L_0x193a550, L_0x193a640, C4<0>, C4<0>; -L_0x193a730 .delay (20000,20000,20000) L_0x193a730/d; -v0x190a6e0_0 .net "S", 0 0, L_0x193a960; 1 drivers -v0x190a780_0 .net "in0", 0 0, L_0x193aa00; 1 drivers -v0x190a820_0 .net "in1", 0 0, L_0x193ab40; 1 drivers -v0x190a8c0_0 .net "nS", 0 0, L_0x193a0c0; 1 drivers -v0x190a940_0 .net "out0", 0 0, L_0x193a550; 1 drivers -v0x190a9e0_0 .net "out1", 0 0, L_0x193a640; 1 drivers -v0x190aac0_0 .net "outfinal", 0 0, L_0x193a730; 1 drivers -S_0x1908900 .scope generate, "muxbits[2]" "muxbits[2]" 3 290, 3 290, S_0x18a5800; - .timescale -9 -12; -P_0x1907848 .param/l "i" 3 290, +C4<010>; -L_0x193d1d0/d .functor OR 1, L_0x193d9d0, L_0x193dd50, C4<0>, C4<0>; -L_0x193d1d0 .delay (20000,20000,20000) L_0x193d1d0/d; -v0x190a320_0 .net *"_s15", 0 0, L_0x193d9d0; 1 drivers -v0x190a3e0_0 .net *"_s16", 0 0, L_0x193dd50; 1 drivers -S_0x19099a0 .scope module, "ZeroMux" "FourInMux" 3 292, 3 24, S_0x1908900; - .timescale -9 -12; -L_0x193b060/d .functor NOT 1, L_0x193af60, C4<0>, C4<0>, C4<0>; -L_0x193b060 .delay (10000,10000,10000) L_0x193b060/d; -L_0x193b150/d .functor NOT 1, L_0x193ba50, C4<0>, C4<0>, C4<0>; -L_0x193b150 .delay (10000,10000,10000) L_0x193b150/d; -L_0x193b1f0/d .functor NAND 1, L_0x193b060, L_0x193b150, L_0x193b900, C4<1>; -L_0x193b1f0 .delay (10000,10000,10000) L_0x193b1f0/d; -L_0x193b330/d .functor NAND 1, L_0x193af60, L_0x193b150, L_0x193bc50, C4<1>; -L_0x193b330 .delay (10000,10000,10000) L_0x193b330/d; -L_0x193b420/d .functor NAND 1, L_0x193b060, L_0x193ba50, L_0x193bb80, C4<1>; -L_0x193b420 .delay (10000,10000,10000) L_0x193b420/d; -L_0x193b510/d .functor NAND 1, L_0x193af60, L_0x193ba50, L_0x193be20, C4<1>; -L_0x193b510 .delay (10000,10000,10000) L_0x193b510/d; -L_0x193b650/d .functor NAND 1, L_0x193b1f0, L_0x193b330, L_0x193b420, L_0x193b510; -L_0x193b650 .delay (10000,10000,10000) L_0x193b650/d; -v0x1909a90_0 .net "S0", 0 0, L_0x193af60; 1 drivers -v0x1909b50_0 .net "S1", 0 0, L_0x193ba50; 1 drivers -v0x1909bf0_0 .net "in0", 0 0, L_0x193b900; 1 drivers -v0x1909c90_0 .net "in1", 0 0, L_0x193bc50; 1 drivers -v0x1909d10_0 .net "in2", 0 0, L_0x193bb80; 1 drivers -v0x1909db0_0 .net "in3", 0 0, L_0x193be20; 1 drivers -v0x1909e50_0 .net "nS0", 0 0, L_0x193b060; 1 drivers -v0x1909ef0_0 .net "nS1", 0 0, L_0x193b150; 1 drivers -v0x1909f90_0 .net "out", 0 0, L_0x193b650; 1 drivers -v0x190a030_0 .net "out0", 0 0, L_0x193b1f0; 1 drivers -v0x190a0d0_0 .net "out1", 0 0, L_0x193b330; 1 drivers -v0x190a170_0 .net "out2", 0 0, L_0x193b420; 1 drivers -v0x190a280_0 .net "out3", 0 0, L_0x193b510; 1 drivers -S_0x1908fe0 .scope module, "OneMux" "FourInMux" 3 293, 3 24, S_0x1908900; - .timescale -9 -12; -L_0x193bcf0/d .functor NOT 1, L_0x193c7f0, C4<0>, C4<0>, C4<0>; -L_0x193bcf0 .delay (10000,10000,10000) L_0x193bcf0/d; -L_0x193c050/d .functor NOT 1, L_0x193bf10, C4<0>, C4<0>, C4<0>; -L_0x193c050 .delay (10000,10000,10000) L_0x193c050/d; -L_0x193c0b0/d .functor NAND 1, L_0x193bcf0, L_0x193c050, L_0x192ad80, C4<1>; -L_0x193c0b0 .delay (10000,10000,10000) L_0x193c0b0/d; -L_0x193c1f0/d .functor NAND 1, L_0x193c7f0, L_0x193c050, L_0x192af30, C4<1>; -L_0x193c1f0 .delay (10000,10000,10000) L_0x193c1f0/d; -L_0x193c2e0/d .functor NAND 1, L_0x193bcf0, L_0x193bf10, L_0x192abf0, C4<1>; -L_0x193c2e0 .delay (10000,10000,10000) L_0x193c2e0/d; -L_0x193c3d0/d .functor NAND 1, L_0x193c7f0, L_0x193bf10, L_0x192ae20, C4<1>; -L_0x193c3d0 .delay (10000,10000,10000) L_0x193c3d0/d; -L_0x193c540/d .functor NAND 1, L_0x193c0b0, L_0x193c1f0, L_0x193c2e0, L_0x193c3d0; -L_0x193c540 .delay (10000,10000,10000) L_0x193c540/d; -v0x19090d0_0 .net "S0", 0 0, L_0x193c7f0; 1 drivers -v0x1909190_0 .net "S1", 0 0, L_0x193bf10; 1 drivers -v0x1909230_0 .net "in0", 0 0, L_0x192ad80; 1 drivers -v0x19092d0_0 .net "in1", 0 0, L_0x192af30; 1 drivers -v0x1909350_0 .net "in2", 0 0, L_0x192abf0; 1 drivers -v0x19093f0_0 .net "in3", 0 0, L_0x192ae20; 1 drivers -v0x19094d0_0 .net "nS0", 0 0, L_0x193bcf0; 1 drivers -v0x1909570_0 .net "nS1", 0 0, L_0x193c050; 1 drivers -v0x1909610_0 .net "out", 0 0, L_0x193c540; 1 drivers -v0x19096b0_0 .net "out0", 0 0, L_0x193c0b0; 1 drivers -v0x1909750_0 .net "out1", 0 0, L_0x193c1f0; 1 drivers -v0x19097f0_0 .net "out2", 0 0, L_0x193c2e0; 1 drivers -v0x1909900_0 .net "out3", 0 0, L_0x193c3d0; 1 drivers -S_0x1908a70 .scope module, "TwoMux" "TwoInMux" 3 294, 3 8, S_0x1908900; - .timescale -9 -12; -L_0x192aec0/d .functor NOT 1, L_0x193d130, C4<0>, C4<0>, C4<0>; -L_0x192aec0 .delay (10000,10000,10000) L_0x192aec0/d; -L_0x193d2e0/d .functor AND 1, L_0x193d860, L_0x192aec0, C4<1>, C4<1>; -L_0x193d2e0 .delay (20000,20000,20000) L_0x193d2e0/d; -L_0x193d3d0/d .functor AND 1, L_0x193d730, L_0x193d130, C4<1>, C4<1>; -L_0x193d3d0 .delay (20000,20000,20000) L_0x193d3d0/d; -L_0x193d4c0/d .functor OR 1, L_0x193d2e0, L_0x193d3d0, C4<0>, C4<0>; -L_0x193d4c0 .delay (20000,20000,20000) L_0x193d4c0/d; -v0x1908b60_0 .net "S", 0 0, L_0x193d130; 1 drivers -v0x1908c00_0 .net "in0", 0 0, L_0x193d860; 1 drivers -v0x1908ca0_0 .net "in1", 0 0, L_0x193d730; 1 drivers -v0x1908d40_0 .net "nS", 0 0, L_0x192aec0; 1 drivers -v0x1908dc0_0 .net "out0", 0 0, L_0x193d2e0; 1 drivers -v0x1908e60_0 .net "out1", 0 0, L_0x193d3d0; 1 drivers -v0x1908f40_0 .net "outfinal", 0 0, L_0x193d4c0; 1 drivers -S_0x1883e50 .scope generate, "muxbits[3]" "muxbits[3]" 3 290, 3 290, S_0x18a5800; - .timescale -9 -12; -P_0x187d708 .param/l "i" 3 290, +C4<011>; -L_0x1940410/d .functor OR 1, L_0x1940790, L_0x19405a0, C4<0>, C4<0>; -L_0x1940410 .delay (20000,20000,20000) L_0x1940410/d; -v0x19087a0_0 .net *"_s15", 0 0, L_0x1940790; 1 drivers -v0x1908860_0 .net *"_s16", 0 0, L_0x19405a0; 1 drivers -S_0x1907e20 .scope module, "ZeroMux" "FourInMux" 3 292, 3 24, S_0x1883e50; - .timescale -9 -12; -L_0x193dc00/d .functor NOT 1, L_0x193e700, C4<0>, C4<0>, C4<0>; -L_0x193dc00 .delay (10000,10000,10000) L_0x193dc00/d; -L_0x193dcf0/d .functor NOT 1, L_0x193ddf0, C4<0>, C4<0>, C4<0>; -L_0x193dcf0 .delay (10000,10000,10000) L_0x193dcf0/d; -L_0x193df90/d .functor NAND 1, L_0x193dc00, L_0x193dcf0, L_0x193e9a0, C4<1>; -L_0x193df90 .delay (10000,10000,10000) L_0x193df90/d; -L_0x193e0d0/d .functor NAND 1, L_0x193e700, L_0x193dcf0, L_0x1930820, C4<1>; -L_0x193e0d0 .delay (10000,10000,10000) L_0x193e0d0/d; -L_0x193e1c0/d .functor NAND 1, L_0x193dc00, L_0x193ddf0, L_0x193e830, C4<1>; -L_0x193e1c0 .delay (10000,10000,10000) L_0x193e1c0/d; -L_0x193e2e0/d .functor NAND 1, L_0x193e700, L_0x193ddf0, L_0x193ede0, C4<1>; -L_0x193e2e0 .delay (10000,10000,10000) L_0x193e2e0/d; -L_0x193e450/d .functor NAND 1, L_0x193df90, L_0x193e0d0, L_0x193e1c0, L_0x193e2e0; -L_0x193e450 .delay (10000,10000,10000) L_0x193e450/d; -v0x1907f10_0 .net "S0", 0 0, L_0x193e700; 1 drivers -v0x1907fd0_0 .net "S1", 0 0, L_0x193ddf0; 1 drivers -v0x1908070_0 .net "in0", 0 0, L_0x193e9a0; 1 drivers -v0x1908110_0 .net "in1", 0 0, L_0x1930820; 1 drivers -v0x1908190_0 .net "in2", 0 0, L_0x193e830; 1 drivers -v0x1908230_0 .net "in3", 0 0, L_0x193ede0; 1 drivers -v0x19082d0_0 .net "nS0", 0 0, L_0x193dc00; 1 drivers -v0x1908370_0 .net "nS1", 0 0, L_0x193dcf0; 1 drivers -v0x1908410_0 .net "out", 0 0, L_0x193e450; 1 drivers -v0x19084b0_0 .net "out0", 0 0, L_0x193df90; 1 drivers -v0x1908550_0 .net "out1", 0 0, L_0x193e0d0; 1 drivers -v0x19085f0_0 .net "out2", 0 0, L_0x193e1c0; 1 drivers -v0x1908700_0 .net "out3", 0 0, L_0x193e2e0; 1 drivers -S_0x19073b0 .scope module, "OneMux" "FourInMux" 3 293, 3 24, S_0x1883e50; - .timescale -9 -12; -L_0x193e920/d .functor NOT 1, L_0x193ec50, C4<0>, C4<0>, C4<0>; -L_0x193e920 .delay (10000,10000,10000) L_0x193e920/d; -L_0x193ef10/d .functor NOT 1, L_0x193f890, C4<0>, C4<0>, C4<0>; -L_0x193ef10 .delay (10000,10000,10000) L_0x193ef10/d; -L_0x193efb0/d .functor NAND 1, L_0x193e920, L_0x193ef10, L_0x193f6f0, C4<1>; -L_0x193efb0 .delay (10000,10000,10000) L_0x193efb0/d; -L_0x193f0f0/d .functor NAND 1, L_0x193ec50, L_0x193ef10, L_0x193f790, C4<1>; -L_0x193f0f0 .delay (10000,10000,10000) L_0x193f0f0/d; -L_0x193f1e0/d .functor NAND 1, L_0x193e920, L_0x193f890, L_0x193fb80, C4<1>; -L_0x193f1e0 .delay (10000,10000,10000) L_0x193f1e0/d; -L_0x193f2d0/d .functor NAND 1, L_0x193ec50, L_0x193f890, L_0x193fc20, C4<1>; -L_0x193f2d0 .delay (10000,10000,10000) L_0x193f2d0/d; -L_0x193f440/d .functor NAND 1, L_0x193efb0, L_0x193f0f0, L_0x193f1e0, L_0x193f2d0; -L_0x193f440 .delay (10000,10000,10000) L_0x193f440/d; -v0x19074a0_0 .net "S0", 0 0, L_0x193ec50; 1 drivers -v0x1907560_0 .net "S1", 0 0, L_0x193f890; 1 drivers -v0x1907600_0 .net "in0", 0 0, L_0x193f6f0; 1 drivers -v0x19076a0_0 .net "in1", 0 0, L_0x193f790; 1 drivers -v0x1907720_0 .net "in2", 0 0, L_0x193fb80; 1 drivers -v0x19077c0_0 .net "in3", 0 0, L_0x193fc20; 1 drivers -v0x19078a0_0 .net "nS0", 0 0, L_0x193e920; 1 drivers -v0x1907940_0 .net "nS1", 0 0, L_0x193ef10; 1 drivers -v0x1907a30_0 .net "out", 0 0, L_0x193f440; 1 drivers -v0x1907ad0_0 .net "out0", 0 0, L_0x193efb0; 1 drivers -v0x1907bd0_0 .net "out1", 0 0, L_0x193f0f0; 1 drivers -v0x1907c70_0 .net "out2", 0 0, L_0x193f1e0; 1 drivers -v0x1907d80_0 .net "out3", 0 0, L_0x193f2d0; 1 drivers -S_0x1883c00 .scope module, "TwoMux" "TwoInMux" 3 294, 3 8, S_0x1883e50; - .timescale -9 -12; -L_0x1939330/d .functor NOT 1, L_0x19402d0, C4<0>, C4<0>, C4<0>; -L_0x1939330 .delay (10000,10000,10000) L_0x1939330/d; -L_0x193f9c0/d .functor AND 1, L_0x193fed0, L_0x1939330, C4<1>, C4<1>; -L_0x193f9c0 .delay (20000,20000,20000) L_0x193f9c0/d; -L_0x193fab0/d .functor AND 1, L_0x193ffc0, L_0x19402d0, C4<1>, C4<1>; -L_0x193fab0 .delay (20000,20000,20000) L_0x193fab0/d; -L_0x19400f0/d .functor OR 1, L_0x193f9c0, L_0x193fab0, C4<0>, C4<0>; -L_0x19400f0 .delay (20000,20000,20000) L_0x19400f0/d; -v0x184e470_0 .net "S", 0 0, L_0x19402d0; 1 drivers -v0x1906fa0_0 .net "in0", 0 0, L_0x193fed0; 1 drivers -v0x1907040_0 .net "in1", 0 0, L_0x193ffc0; 1 drivers -v0x19070e0_0 .net "nS", 0 0, L_0x1939330; 1 drivers -v0x1907190_0 .net "out0", 0 0, L_0x193f9c0; 1 drivers -v0x1907230_0 .net "out1", 0 0, L_0x193fab0; 1 drivers -v0x1907310_0 .net "outfinal", 0 0, L_0x19400f0; 1 drivers - .scope S_0x18c7e50; +S_0x1b740f0 .scope module, "test32Adder" "test32Adder" 2 122; + .timescale -9 -12; +P_0x1ac8268 .param/l "size" 2 123, +C4<0100>; +v0x1bd6330_0 .var "A", 3 0; +RS_0x7f6a63aa0be8/0/0 .resolv tri, L_0x1bd7b20, L_0x1bd9210, L_0x1bda750, L_0x1bdbd50; +RS_0x7f6a63aa0be8/0/4 .resolv tri, L_0x1bedc60, L_0x1bef080, L_0x1bf0480, L_0x1bf1a60; +RS_0x7f6a63aa0be8 .resolv tri, RS_0x7f6a63aa0be8/0/0, RS_0x7f6a63aa0be8/0/4, C4, C4; +v0x1bd63b0_0 .net8 "AddSubSLTSum", 3 0, RS_0x7f6a63aa0be8; 8 drivers +v0x1bd6430_0 .net "AllZeros", 0 0, L_0x1bfd2b0; 1 drivers +RS_0x7f6a63a9fe38/0/0 .resolv tri, L_0x1bddd00, L_0x1bde7b0, L_0x1bdf220, L_0x1bdfc80; +RS_0x7f6a63a9fe38/0/4 .resolv tri, L_0x1bf3890, L_0x1bf4300, L_0x1bf4d70, L_0x1bf58d0; +RS_0x7f6a63a9fe38 .resolv tri, RS_0x7f6a63a9fe38/0/0, RS_0x7f6a63a9fe38/0/4, C4, C4; +v0x1bd64b0_0 .net8 "AndNandOut", 3 0, RS_0x7f6a63a9fe38; 8 drivers +v0x1bd6530_0 .var "B", 3 0; +v0x1bd65b0_0 .var "Command", 2 0; +RS_0x7f6a63aa1068 .resolv tri, L_0x1be6d00, L_0x1be9a90, L_0x1bec6c0, L_0x1bfc720; +v0x1bd6630_0 .net8 "OneBitFinalOut", 3 0, RS_0x7f6a63aa1068; 4 drivers +RS_0x7f6a63a9f748/0/0 .resolv tri, L_0x1be0fd0, L_0x1be2530, L_0x1be3830, L_0x1be48e0; +RS_0x7f6a63a9f748/0/4 .resolv tri, L_0x1bf6c20, L_0x1bf7f20, L_0x1bf9220, L_0x1bfa510; +RS_0x7f6a63a9f748 .resolv tri, RS_0x7f6a63a9f748/0/0, RS_0x7f6a63a9f748/0/4, C4, C4; +v0x1bd66b0_0 .net8 "OrNorXorOut", 3 0, RS_0x7f6a63a9f748; 8 drivers +RS_0x7f6a63aa0ca8 .resolv tri, L_0x1bdd380, L_0x1bf2f30, C4, C4; +v0x1bd6730_0 .net8 "SLTflag", 0 0, RS_0x7f6a63aa0ca8; 2 drivers +RS_0x7f6a63aa1098 .resolv tri, L_0x1be71b0, L_0x1be9f60, L_0x1bec800, L_0x1bfc9e0; +v0x1bd67b0_0 .net8 "ZeroFlag", 3 0, RS_0x7f6a63aa1098; 4 drivers +v0x1bd6830_0 .var "carryin", 3 0; +RS_0x7f6a63aa0ee8 .resolv tri, L_0x1bd7e00, L_0x1bf1de0, C4, C4; +v0x1bd68b0_0 .net8 "carryout", 0 0, RS_0x7f6a63aa0ee8; 2 drivers +RS_0x7f6a63aa0f78 .resolv tri, L_0x1bdc650, L_0x1bf2250, C4, C4; +v0x1bd6930_0 .net8 "overflow", 0 0, RS_0x7f6a63aa0f78; 2 drivers +RS_0x7f6a63aa0fa8/0/0 .resolv tri, L_0x1bd7d60, L_0x1bd9440, L_0x1bda9b0, L_0x1bdada0; +RS_0x7f6a63aa0fa8/0/4 .resolv tri, L_0x1bede40, L_0x1bef2b0, L_0x1bf06e0, L_0x1bf0ad0; +RS_0x7f6a63aa0fa8 .resolv tri, RS_0x7f6a63aa0fa8/0/0, RS_0x7f6a63aa0fa8/0/4, C4, C4; +v0x1bd69b0_0 .net8 "subtract", 3 0, RS_0x7f6a63aa0fa8; 8 drivers +S_0x1bd0bc0 .scope module, "trial" "AddSubSLT32" 2 141, 3 205, S_0x1b740f0; + .timescale -9 -12; +P_0x1bd0cb8 .param/l "size" 3 228, +C4<0100>; +L_0x1bd7e00/d .functor OR 1, L_0x1bdc4a0, C4<0>, C4<0>, C4<0>; +L_0x1bd7e00 .delay (20000,20000,20000) L_0x1bd7e00/d; +L_0x1bdc650/d .functor XOR 1, RS_0x7f6a63aa0ee8, L_0x1bdc780, C4<0>, C4<0>; +L_0x1bdc650 .delay (40000,40000,40000) L_0x1bdc650/d; +L_0x1bdc3d0/d .functor AND 1, L_0x1bdc950, L_0x1bdc9f0, C4<1>, C4<1>; +L_0x1bdc3d0 .delay (20000,20000,20000) L_0x1bdc3d0/d; +L_0x1bdc820/d .functor NOT 1, RS_0x7f6a63aa0f78, C4<0>, C4<0>, C4<0>; +L_0x1bdc820 .delay (10000,10000,10000) L_0x1bdc820/d; +L_0x1bdcc20/d .functor NOT 1, L_0x1bdcc80, C4<0>, C4<0>, C4<0>; +L_0x1bdcc20 .delay (10000,10000,10000) L_0x1bdcc20/d; +L_0x1bd7bc0/d .functor AND 1, L_0x1bdc820, L_0x1bdcf50, C4<1>, C4<1>; +L_0x1bd7bc0 .delay (20000,20000,20000) L_0x1bd7bc0/d; +L_0x1bdcae0/d .functor AND 1, RS_0x7f6a63aa0f78, L_0x1bdcc20, C4<1>, C4<1>; +L_0x1bdcae0 .delay (20000,20000,20000) L_0x1bdcae0/d; +L_0x1bdd140/d .functor AND 1, L_0x1bd7bc0, L_0x1bdc3d0, C4<1>, C4<1>; +L_0x1bdd140 .delay (20000,20000,20000) L_0x1bdd140/d; +L_0x1bdd280/d .functor AND 1, L_0x1bdcae0, L_0x1bdc3d0, C4<1>, C4<1>; +L_0x1bdd280 .delay (20000,20000,20000) L_0x1bdd280/d; +L_0x1bdd380/d .functor OR 1, L_0x1bdd140, L_0x1bdd280, C4<0>, C4<0>; +L_0x1bdd380 .delay (20000,20000,20000) L_0x1bdd380/d; +v0x1bd5250_0 .net "A", 3 0, v0x1bd6330_0; 1 drivers +v0x1bd52f0_0 .alias "AddSubSLTSum", 3 0, v0x1bd63b0_0; +v0x1bd5370_0 .net "B", 3 0, v0x1bd6530_0; 1 drivers +RS_0x7f6a63aa3348 .resolv tri, L_0x1bd7c70, L_0x1bd9300, L_0x1bda840, L_0x1bdbe40; +v0x1bd53f0_0 .net8 "CarryoutWire", 3 0, RS_0x7f6a63aa3348; 4 drivers +v0x1bd5470_0 .net "Command", 2 0, v0x1bd65b0_0; 1 drivers +v0x1bd54f0_0 .net "Res0OF1", 0 0, L_0x1bdcae0; 1 drivers +v0x1bd5590_0 .net "Res1OF0", 0 0, L_0x1bd7bc0; 1 drivers +v0x1bd5630_0 .alias "SLTflag", 0 0, v0x1bd6730_0; +v0x1bd5750_0 .net "SLTflag0", 0 0, L_0x1bdd140; 1 drivers +v0x1bd57f0_0 .net "SLTflag1", 0 0, L_0x1bdd280; 1 drivers +v0x1bd5890_0 .net "SLTon", 0 0, L_0x1bdc3d0; 1 drivers +v0x1bd5930_0 .net *"_s40", 0 0, L_0x1bdc4a0; 1 drivers +v0x1bd59d0_0 .net/s *"_s41", 0 0, C4<0>; 1 drivers +v0x1bd5a70_0 .net *"_s44", 0 0, L_0x1bdc780; 1 drivers +v0x1bd5b90_0 .net *"_s46", 0 0, L_0x1bdc950; 1 drivers +v0x1bd5c30_0 .net *"_s48", 0 0, L_0x1bdc9f0; 1 drivers +v0x1bd5af0_0 .net *"_s50", 0 0, L_0x1bdcc80; 1 drivers +v0x1bd5d80_0 .net *"_s52", 0 0, L_0x1bdcf50; 1 drivers +v0x1bd5ea0_0 .net "carryin", 3 0, v0x1bd6830_0; 1 drivers +v0x1bd5f20_0 .alias "carryout", 0 0, v0x1bd68b0_0; +v0x1bd5e00_0 .net "nAddSubSLTSum", 0 0, L_0x1bdcc20; 1 drivers +v0x1bd6050_0 .net "nOF", 0 0, L_0x1bdc820; 1 drivers +v0x1bd5fa0_0 .alias "overflow", 0 0, v0x1bd6930_0; +v0x1bd61e0_0 .alias "subtract", 3 0, v0x1bd69b0_0; +L_0x1bd7b20 .part/pv L_0x1bd7690, 1, 1, 4; +L_0x1bd7c70 .part/pv L_0x1bd79e0, 1, 1, 4; +L_0x1bd7d60 .part/pv L_0x1bc9bc0, 1, 1, 4; +L_0x1bd7e90 .part v0x1bd6330_0, 1, 1; +L_0x1bd8040 .part v0x1bd6530_0, 1, 1; +L_0x1bd81f0 .part RS_0x7f6a63aa3348, 0, 1; +L_0x1bd9210 .part/pv L_0x1bd8d40, 2, 1, 4; +L_0x1bd9300 .part/pv L_0x1bd90b0, 2, 1, 4; +L_0x1bd9440 .part/pv L_0x1bd8a70, 2, 1, 4; +L_0x1bd9530 .part v0x1bd6330_0, 2, 1; +L_0x1bd9630 .part v0x1bd6530_0, 2, 1; +L_0x1bd9760 .part RS_0x7f6a63aa3348, 1, 1; +L_0x1bda750 .part/pv L_0x1bda2a0, 3, 1, 4; +L_0x1bda840 .part/pv L_0x1bda5f0, 3, 1, 4; +L_0x1bda9b0 .part/pv L_0x1bd9fd0, 3, 1, 4; +L_0x1bdaaa0 .part v0x1bd6330_0, 3, 1; +L_0x1bdabd0 .part v0x1bd6530_0, 3, 1; +L_0x1bdad00 .part RS_0x7f6a63aa3348, 2, 1; +L_0x1bdbd50 .part/pv L_0x1bdb8a0, 0, 1, 4; +L_0x1bdbe40 .part/pv L_0x1bdbbf0, 0, 1, 4; +L_0x1bdada0 .part/pv L_0x1bdb5d0, 0, 1, 4; +L_0x1bdc030 .part v0x1bd6330_0, 0, 1; +L_0x1bdbf30 .part v0x1bd6530_0, 0, 1; +L_0x1bdc220 .part RS_0x7f6a63aa0fa8, 0, 1; +L_0x1bdc4a0 .part RS_0x7f6a63aa3348, 3, 1; +L_0x1bdc780 .part RS_0x7f6a63aa3348, 2, 1; +L_0x1bdc950 .part v0x1bd65b0_0, 1, 1; +L_0x1bdc9f0 .part RS_0x7f6a63aa0fa8, 0, 1; +L_0x1bdcc80 .part RS_0x7f6a63aa0be8, 3, 1; +L_0x1bdcf50 .part RS_0x7f6a63aa0be8, 3, 1; +S_0x1bd4240 .scope module, "attempt2" "MiddleAddSubSLT" 3 225, 3 89, S_0x1bd0bc0; + .timescale -9 -12; +L_0x1bdab40/d .functor NOT 1, L_0x1bdbf30, C4<0>, C4<0>, C4<0>; +L_0x1bdab40 .delay (10000,10000,10000) L_0x1bdab40/d; +L_0x1bdb470/d .functor NOT 1, L_0x1bdb530, C4<0>, C4<0>, C4<0>; +L_0x1bdb470 .delay (10000,10000,10000) L_0x1bdb470/d; +L_0x1bdb5d0/d .functor AND 1, L_0x1bdb710, L_0x1bdb470, C4<1>, C4<1>; +L_0x1bdb5d0 .delay (20000,20000,20000) L_0x1bdb5d0/d; +L_0x1bdb7b0/d .functor XOR 1, L_0x1bdc030, L_0x1bdb200, C4<0>, C4<0>; +L_0x1bdb7b0 .delay (40000,40000,40000) L_0x1bdb7b0/d; +L_0x1bdb8a0/d .functor XOR 1, L_0x1bdb7b0, L_0x1bdc220, C4<0>, C4<0>; +L_0x1bdb8a0 .delay (40000,40000,40000) L_0x1bdb8a0/d; +L_0x1bdb990/d .functor AND 1, L_0x1bdc030, L_0x1bdb200, C4<1>, C4<1>; +L_0x1bdb990 .delay (20000,20000,20000) L_0x1bdb990/d; +L_0x1bdbb00/d .functor AND 1, L_0x1bdb7b0, L_0x1bdc220, C4<1>, C4<1>; +L_0x1bdbb00 .delay (20000,20000,20000) L_0x1bdbb00/d; +L_0x1bdbbf0/d .functor OR 1, L_0x1bdb990, L_0x1bdbb00, C4<0>, C4<0>; +L_0x1bdbbf0 .delay (20000,20000,20000) L_0x1bdbbf0/d; +v0x1bd48b0_0 .net "A", 0 0, L_0x1bdc030; 1 drivers +v0x1bd4970_0 .net "AandB", 0 0, L_0x1bdb990; 1 drivers +v0x1bd4a10_0 .net "AddSubSLTSum", 0 0, L_0x1bdb8a0; 1 drivers +v0x1bd4ab0_0 .net "AxorB", 0 0, L_0x1bdb7b0; 1 drivers +v0x1bd4b30_0 .net "B", 0 0, L_0x1bdbf30; 1 drivers +v0x1bd4be0_0 .net "BornB", 0 0, L_0x1bdb200; 1 drivers +v0x1bd4ca0_0 .net "CINandAxorB", 0 0, L_0x1bdbb00; 1 drivers +v0x1bd4d20_0 .alias "Command", 2 0, v0x1bd5470_0; +v0x1bd4da0_0 .net *"_s3", 0 0, L_0x1bdb530; 1 drivers +v0x1bd4e20_0 .net *"_s5", 0 0, L_0x1bdb710; 1 drivers +v0x1bd4ec0_0 .net "carryin", 0 0, L_0x1bdc220; 1 drivers +v0x1bd4f60_0 .net "carryout", 0 0, L_0x1bdbbf0; 1 drivers +v0x1bd5000_0 .net "nB", 0 0, L_0x1bdab40; 1 drivers +v0x1bd50b0_0 .net "nCmd2", 0 0, L_0x1bdb470; 1 drivers +v0x1bd51b0_0 .net "subtract", 0 0, L_0x1bdb5d0; 1 drivers +L_0x1bdb3d0 .part v0x1bd65b0_0, 0, 1; +L_0x1bdb530 .part v0x1bd65b0_0, 2, 1; +L_0x1bdb710 .part v0x1bd65b0_0, 0, 1; +S_0x1bd4330 .scope module, "mux0" "TwoInMux" 3 105, 3 8, S_0x1bd4240; + .timescale -9 -12; +L_0x1bdaf20/d .functor NOT 1, L_0x1bdb3d0, C4<0>, C4<0>, C4<0>; +L_0x1bdaf20 .delay (10000,10000,10000) L_0x1bdaf20/d; +L_0x1bdafe0/d .functor AND 1, L_0x1bdbf30, L_0x1bdaf20, C4<1>, C4<1>; +L_0x1bdafe0 .delay (20000,20000,20000) L_0x1bdafe0/d; +L_0x1bdb0f0/d .functor AND 1, L_0x1bdab40, L_0x1bdb3d0, C4<1>, C4<1>; +L_0x1bdb0f0 .delay (20000,20000,20000) L_0x1bdb0f0/d; +L_0x1bdb200/d .functor OR 1, L_0x1bdafe0, L_0x1bdb0f0, C4<0>, C4<0>; +L_0x1bdb200 .delay (20000,20000,20000) L_0x1bdb200/d; +v0x1bd4420_0 .net "S", 0 0, L_0x1bdb3d0; 1 drivers +v0x1bd44e0_0 .alias "in0", 0 0, v0x1bd4b30_0; +v0x1bd4580_0 .alias "in1", 0 0, v0x1bd5000_0; +v0x1bd4620_0 .net "nS", 0 0, L_0x1bdaf20; 1 drivers +v0x1bd46d0_0 .net "out0", 0 0, L_0x1bdafe0; 1 drivers +v0x1bd4770_0 .net "out1", 0 0, L_0x1bdb0f0; 1 drivers +v0x1bd4810_0 .alias "outfinal", 0 0, v0x1bd4be0_0; +S_0x1bd30a0 .scope generate, "addbits[1]" "addbits[1]" 3 230, 3 230, S_0x1bd0bc0; + .timescale -9 -12; +P_0x1bd2ab8 .param/l "i" 3 230, +C4<01>; +S_0x1bd3210 .scope module, "attempt" "MiddleAddSubSLT" 3 232, 3 89, S_0x1bd30a0; + .timescale -9 -12; +L_0x1bd1af0/d .functor NOT 1, L_0x1bd8040, C4<0>, C4<0>, C4<0>; +L_0x1bd1af0 .delay (10000,10000,10000) L_0x1bd1af0/d; +L_0x1bd6120/d .functor NOT 1, L_0x1bc9b20, C4<0>, C4<0>, C4<0>; +L_0x1bd6120 .delay (10000,10000,10000) L_0x1bd6120/d; +L_0x1bc9bc0/d .functor AND 1, L_0x1bd7500, L_0x1bd6120, C4<1>, C4<1>; +L_0x1bc9bc0 .delay (20000,20000,20000) L_0x1bc9bc0/d; +L_0x1bd75a0/d .functor XOR 1, L_0x1bd7e90, L_0x1bd6e80, C4<0>, C4<0>; +L_0x1bd75a0 .delay (40000,40000,40000) L_0x1bd75a0/d; +L_0x1bd7690/d .functor XOR 1, L_0x1bd75a0, L_0x1bd81f0, C4<0>, C4<0>; +L_0x1bd7690 .delay (40000,40000,40000) L_0x1bd7690/d; +L_0x1bd7780/d .functor AND 1, L_0x1bd7e90, L_0x1bd6e80, C4<1>, C4<1>; +L_0x1bd7780 .delay (20000,20000,20000) L_0x1bd7780/d; +L_0x1bd78f0/d .functor AND 1, L_0x1bd75a0, L_0x1bd81f0, C4<1>, C4<1>; +L_0x1bd78f0 .delay (20000,20000,20000) L_0x1bd78f0/d; +L_0x1bd79e0/d .functor OR 1, L_0x1bd7780, L_0x1bd78f0, C4<0>, C4<0>; +L_0x1bd79e0 .delay (20000,20000,20000) L_0x1bd79e0/d; +v0x1bd38a0_0 .net "A", 0 0, L_0x1bd7e90; 1 drivers +v0x1bd3960_0 .net "AandB", 0 0, L_0x1bd7780; 1 drivers +v0x1bd3a00_0 .net "AddSubSLTSum", 0 0, L_0x1bd7690; 1 drivers +v0x1bd3aa0_0 .net "AxorB", 0 0, L_0x1bd75a0; 1 drivers +v0x1bd3b20_0 .net "B", 0 0, L_0x1bd8040; 1 drivers +v0x1bd3bd0_0 .net "BornB", 0 0, L_0x1bd6e80; 1 drivers +v0x1bd3c90_0 .net "CINandAxorB", 0 0, L_0x1bd78f0; 1 drivers +v0x1bd3d10_0 .alias "Command", 2 0, v0x1bd5470_0; +v0x1bd3d90_0 .net *"_s3", 0 0, L_0x1bc9b20; 1 drivers +v0x1bd3e10_0 .net *"_s5", 0 0, L_0x1bd7500; 1 drivers +v0x1bd3eb0_0 .net "carryin", 0 0, L_0x1bd81f0; 1 drivers +v0x1bd3f50_0 .net "carryout", 0 0, L_0x1bd79e0; 1 drivers +v0x1bd3ff0_0 .net "nB", 0 0, L_0x1bd1af0; 1 drivers +v0x1bd40a0_0 .net "nCmd2", 0 0, L_0x1bd6120; 1 drivers +v0x1bd41a0_0 .net "subtract", 0 0, L_0x1bc9bc0; 1 drivers +L_0x1bd7050 .part v0x1bd65b0_0, 0, 1; +L_0x1bc9b20 .part v0x1bd65b0_0, 2, 1; +L_0x1bd7500 .part v0x1bd65b0_0, 0, 1; +S_0x1bd3300 .scope module, "mux0" "TwoInMux" 3 105, 3 8, S_0x1bd3210; + .timescale -9 -12; +L_0x1bd6ba0/d .functor NOT 1, L_0x1bd7050, C4<0>, C4<0>, C4<0>; +L_0x1bd6ba0 .delay (10000,10000,10000) L_0x1bd6ba0/d; +L_0x1bd6c60/d .functor AND 1, L_0x1bd8040, L_0x1bd6ba0, C4<1>, C4<1>; +L_0x1bd6c60 .delay (20000,20000,20000) L_0x1bd6c60/d; +L_0x1bd6d70/d .functor AND 1, L_0x1bd1af0, L_0x1bd7050, C4<1>, C4<1>; +L_0x1bd6d70 .delay (20000,20000,20000) L_0x1bd6d70/d; +L_0x1bd6e80/d .functor OR 1, L_0x1bd6c60, L_0x1bd6d70, C4<0>, C4<0>; +L_0x1bd6e80 .delay (20000,20000,20000) L_0x1bd6e80/d; +v0x1bd33f0_0 .net "S", 0 0, L_0x1bd7050; 1 drivers +v0x1bd3490_0 .alias "in0", 0 0, v0x1bd3b20_0; +v0x1bd3530_0 .alias "in1", 0 0, v0x1bd3ff0_0; +v0x1bd35d0_0 .net "nS", 0 0, L_0x1bd6ba0; 1 drivers +v0x1bd3680_0 .net "out0", 0 0, L_0x1bd6c60; 1 drivers +v0x1bd3720_0 .net "out1", 0 0, L_0x1bd6d70; 1 drivers +v0x1bd3800_0 .alias "outfinal", 0 0, v0x1bd3bd0_0; +S_0x1bd1f00 .scope generate, "addbits[2]" "addbits[2]" 3 230, 3 230, S_0x1bd0bc0; + .timescale -9 -12; +P_0x1bd18b8 .param/l "i" 3 230, +C4<010>; +S_0x1bd2070 .scope module, "attempt" "MiddleAddSubSLT" 3 232, 3 89, S_0x1bd1f00; + .timescale -9 -12; +L_0x1bcd970/d .functor NOT 1, L_0x1bd9630, C4<0>, C4<0>, C4<0>; +L_0x1bcd970 .delay (10000,10000,10000) L_0x1bcd970/d; +L_0x1bd8910/d .functor NOT 1, L_0x1bd89d0, C4<0>, C4<0>, C4<0>; +L_0x1bd8910 .delay (10000,10000,10000) L_0x1bd8910/d; +L_0x1bd8a70/d .functor AND 1, L_0x1bd8bb0, L_0x1bd8910, C4<1>, C4<1>; +L_0x1bd8a70 .delay (20000,20000,20000) L_0x1bd8a70/d; +L_0x1bd8c50/d .functor XOR 1, L_0x1bd9530, L_0x1bd86a0, C4<0>, C4<0>; +L_0x1bd8c50 .delay (40000,40000,40000) L_0x1bd8c50/d; +L_0x1bd8d40/d .functor XOR 1, L_0x1bd8c50, L_0x1bd9760, C4<0>, C4<0>; +L_0x1bd8d40 .delay (40000,40000,40000) L_0x1bd8d40/d; +L_0x1bd8e30/d .functor AND 1, L_0x1bd9530, L_0x1bd86a0, C4<1>, C4<1>; +L_0x1bd8e30 .delay (20000,20000,20000) L_0x1bd8e30/d; +L_0x1bd8fa0/d .functor AND 1, L_0x1bd8c50, L_0x1bd9760, C4<1>, C4<1>; +L_0x1bd8fa0 .delay (20000,20000,20000) L_0x1bd8fa0/d; +L_0x1bd90b0/d .functor OR 1, L_0x1bd8e30, L_0x1bd8fa0, C4<0>, C4<0>; +L_0x1bd90b0 .delay (20000,20000,20000) L_0x1bd90b0/d; +v0x1bd2700_0 .net "A", 0 0, L_0x1bd9530; 1 drivers +v0x1bd27c0_0 .net "AandB", 0 0, L_0x1bd8e30; 1 drivers +v0x1bd2860_0 .net "AddSubSLTSum", 0 0, L_0x1bd8d40; 1 drivers +v0x1bd2900_0 .net "AxorB", 0 0, L_0x1bd8c50; 1 drivers +v0x1bd2980_0 .net "B", 0 0, L_0x1bd9630; 1 drivers +v0x1bd2a30_0 .net "BornB", 0 0, L_0x1bd86a0; 1 drivers +v0x1bd2af0_0 .net "CINandAxorB", 0 0, L_0x1bd8fa0; 1 drivers +v0x1bd2b70_0 .alias "Command", 2 0, v0x1bd5470_0; +v0x1bd2bf0_0 .net *"_s3", 0 0, L_0x1bd89d0; 1 drivers +v0x1bd2c70_0 .net *"_s5", 0 0, L_0x1bd8bb0; 1 drivers +v0x1bd2d10_0 .net "carryin", 0 0, L_0x1bd9760; 1 drivers +v0x1bd2db0_0 .net "carryout", 0 0, L_0x1bd90b0; 1 drivers +v0x1bd2e50_0 .net "nB", 0 0, L_0x1bcd970; 1 drivers +v0x1bd2f00_0 .net "nCmd2", 0 0, L_0x1bd8910; 1 drivers +v0x1bd3000_0 .net "subtract", 0 0, L_0x1bd8a70; 1 drivers +L_0x1bd8870 .part v0x1bd65b0_0, 0, 1; +L_0x1bd89d0 .part v0x1bd65b0_0, 2, 1; +L_0x1bd8bb0 .part v0x1bd65b0_0, 0, 1; +S_0x1bd2160 .scope module, "mux0" "TwoInMux" 3 105, 3 8, S_0x1bd2070; + .timescale -9 -12; +L_0x1bd83c0/d .functor NOT 1, L_0x1bd8870, C4<0>, C4<0>, C4<0>; +L_0x1bd83c0 .delay (10000,10000,10000) L_0x1bd83c0/d; +L_0x1bd8480/d .functor AND 1, L_0x1bd9630, L_0x1bd83c0, C4<1>, C4<1>; +L_0x1bd8480 .delay (20000,20000,20000) L_0x1bd8480/d; +L_0x1bd8590/d .functor AND 1, L_0x1bcd970, L_0x1bd8870, C4<1>, C4<1>; +L_0x1bd8590 .delay (20000,20000,20000) L_0x1bd8590/d; +L_0x1bd86a0/d .functor OR 1, L_0x1bd8480, L_0x1bd8590, C4<0>, C4<0>; +L_0x1bd86a0 .delay (20000,20000,20000) L_0x1bd86a0/d; +v0x1bd2250_0 .net "S", 0 0, L_0x1bd8870; 1 drivers +v0x1bd22f0_0 .alias "in0", 0 0, v0x1bd2980_0; +v0x1bd2390_0 .alias "in1", 0 0, v0x1bd2e50_0; +v0x1bd2430_0 .net "nS", 0 0, L_0x1bd83c0; 1 drivers +v0x1bd24e0_0 .net "out0", 0 0, L_0x1bd8480; 1 drivers +v0x1bd2580_0 .net "out1", 0 0, L_0x1bd8590; 1 drivers +v0x1bd2660_0 .alias "outfinal", 0 0, v0x1bd2a30_0; +S_0x1bd0d30 .scope generate, "addbits[3]" "addbits[3]" 3 230, 3 230, S_0x1bd0bc0; + .timescale -9 -12; +P_0x1bd0e28 .param/l "i" 3 230, +C4<011>; +S_0x1bd0ea0 .scope module, "attempt" "MiddleAddSubSLT" 3 232, 3 89, S_0x1bd0d30; + .timescale -9 -12; +L_0x1bd95d0/d .functor NOT 1, L_0x1bdabd0, C4<0>, C4<0>, C4<0>; +L_0x1bd95d0 .delay (10000,10000,10000) L_0x1bd95d0/d; +L_0x1bd9e70/d .functor NOT 1, L_0x1bd9f30, C4<0>, C4<0>, C4<0>; +L_0x1bd9e70 .delay (10000,10000,10000) L_0x1bd9e70/d; +L_0x1bd9fd0/d .functor AND 1, L_0x1bda110, L_0x1bd9e70, C4<1>, C4<1>; +L_0x1bd9fd0 .delay (20000,20000,20000) L_0x1bd9fd0/d; +L_0x1bda1b0/d .functor XOR 1, L_0x1bdaaa0, L_0x1bd9c00, C4<0>, C4<0>; +L_0x1bda1b0 .delay (40000,40000,40000) L_0x1bda1b0/d; +L_0x1bda2a0/d .functor XOR 1, L_0x1bda1b0, L_0x1bdad00, C4<0>, C4<0>; +L_0x1bda2a0 .delay (40000,40000,40000) L_0x1bda2a0/d; +L_0x1bda390/d .functor AND 1, L_0x1bdaaa0, L_0x1bd9c00, C4<1>, C4<1>; +L_0x1bda390 .delay (20000,20000,20000) L_0x1bda390/d; +L_0x1bda500/d .functor AND 1, L_0x1bda1b0, L_0x1bdad00, C4<1>, C4<1>; +L_0x1bda500 .delay (20000,20000,20000) L_0x1bda500/d; +L_0x1bda5f0/d .functor OR 1, L_0x1bda390, L_0x1bda500, C4<0>, C4<0>; +L_0x1bda5f0 .delay (20000,20000,20000) L_0x1bda5f0/d; +v0x1bd1500_0 .net "A", 0 0, L_0x1bdaaa0; 1 drivers +v0x1bd15c0_0 .net "AandB", 0 0, L_0x1bda390; 1 drivers +v0x1bd1660_0 .net "AddSubSLTSum", 0 0, L_0x1bda2a0; 1 drivers +v0x1bd1700_0 .net "AxorB", 0 0, L_0x1bda1b0; 1 drivers +v0x1bd1780_0 .net "B", 0 0, L_0x1bdabd0; 1 drivers +v0x1bd1830_0 .net "BornB", 0 0, L_0x1bd9c00; 1 drivers +v0x1bd18f0_0 .net "CINandAxorB", 0 0, L_0x1bda500; 1 drivers +v0x1bd1970_0 .alias "Command", 2 0, v0x1bd5470_0; +v0x1bd19f0_0 .net *"_s3", 0 0, L_0x1bd9f30; 1 drivers +v0x1bd1a70_0 .net *"_s5", 0 0, L_0x1bda110; 1 drivers +v0x1bd1b70_0 .net "carryin", 0 0, L_0x1bdad00; 1 drivers +v0x1bd1c10_0 .net "carryout", 0 0, L_0x1bda5f0; 1 drivers +v0x1bd1cb0_0 .net "nB", 0 0, L_0x1bd95d0; 1 drivers +v0x1bd1d60_0 .net "nCmd2", 0 0, L_0x1bd9e70; 1 drivers +v0x1bd1e60_0 .net "subtract", 0 0, L_0x1bd9fd0; 1 drivers +L_0x1bd9dd0 .part v0x1bd65b0_0, 0, 1; +L_0x1bd9f30 .part v0x1bd65b0_0, 2, 1; +L_0x1bda110 .part v0x1bd65b0_0, 0, 1; +S_0x1bd0f90 .scope module, "mux0" "TwoInMux" 3 105, 3 8, S_0x1bd0ea0; + .timescale -9 -12; +L_0x1bd9960/d .functor NOT 1, L_0x1bd9dd0, C4<0>, C4<0>, C4<0>; +L_0x1bd9960 .delay (10000,10000,10000) L_0x1bd9960/d; +L_0x1bd99e0/d .functor AND 1, L_0x1bdabd0, L_0x1bd9960, C4<1>, C4<1>; +L_0x1bd99e0 .delay (20000,20000,20000) L_0x1bd99e0/d; +L_0x1bd9af0/d .functor AND 1, L_0x1bd95d0, L_0x1bd9dd0, C4<1>, C4<1>; +L_0x1bd9af0 .delay (20000,20000,20000) L_0x1bd9af0/d; +L_0x1bd9c00/d .functor OR 1, L_0x1bd99e0, L_0x1bd9af0, C4<0>, C4<0>; +L_0x1bd9c00 .delay (20000,20000,20000) L_0x1bd9c00/d; +v0x1bd1080_0 .net "S", 0 0, L_0x1bd9dd0; 1 drivers +v0x1bd1120_0 .alias "in0", 0 0, v0x1bd1780_0; +v0x1bd11c0_0 .alias "in1", 0 0, v0x1bd1cb0_0; +v0x1bd1260_0 .net "nS", 0 0, L_0x1bd9960; 1 drivers +v0x1bd12e0_0 .net "out0", 0 0, L_0x1bd99e0; 1 drivers +v0x1bd1380_0 .net "out1", 0 0, L_0x1bd9af0; 1 drivers +v0x1bd1460_0 .alias "outfinal", 0 0, v0x1bd1830_0; +S_0x1bcdb00 .scope module, "trial1" "AndNand32" 2 143, 3 154, S_0x1b740f0; + .timescale -9 -12; +P_0x1bcd4f8 .param/l "size" 3 161, +C4<0100>; +v0x1bd09c0_0 .alias "A", 3 0, v0x1bd5250_0; +v0x1bd0a40_0 .alias "AndNandOut", 3 0, v0x1bd64b0_0; +v0x1bd0ac0_0 .alias "B", 3 0, v0x1bd5370_0; +v0x1bd0b40_0 .alias "Command", 2 0, v0x1bd5470_0; +L_0x1bddd00 .part/pv L_0x1bdda90, 1, 1, 4; +L_0x1bdde50 .part v0x1bd6330_0, 1, 1; +L_0x1bddef0 .part v0x1bd6530_0, 1, 1; +L_0x1bde7b0 .part/pv L_0x1bde540, 2, 1, 4; +L_0x1bde850 .part v0x1bd6330_0, 2, 1; +L_0x1bde8f0 .part v0x1bd6530_0, 2, 1; +L_0x1bdf220 .part/pv L_0x1bdefb0, 3, 1, 4; +L_0x1bdf2c0 .part v0x1bd6330_0, 3, 1; +L_0x1bdf3b0 .part v0x1bd6530_0, 3, 1; +L_0x1bdfc80 .part/pv L_0x1bdfa10, 0, 1, 4; +L_0x1bdfd80 .part v0x1bd6330_0, 0, 1; +L_0x1bdfe20 .part v0x1bd6530_0, 0, 1; +S_0x1bcff90 .scope module, "attempt2" "AndNand" 3 165, 3 48, S_0x1bcdb00; + .timescale -9 -12; +L_0x1bdf4a0/d .functor NAND 1, L_0x1bdfd80, L_0x1bdfe20, C4<1>, C4<1>; +L_0x1bdf4a0 .delay (10000,10000,10000) L_0x1bdf4a0/d; +L_0x1bdf5c0/d .functor NOT 1, L_0x1bdf4a0, C4<0>, C4<0>, C4<0>; +L_0x1bdf5c0 .delay (10000,10000,10000) L_0x1bdf5c0/d; +v0x1bd05b0_0 .net "A", 0 0, L_0x1bdfd80; 1 drivers +v0x1bd0670_0 .net "AandB", 0 0, L_0x1bdf5c0; 1 drivers +v0x1bd06f0_0 .net "AnandB", 0 0, L_0x1bdf4a0; 1 drivers +v0x1bd07a0_0 .net "AndNandOut", 0 0, L_0x1bdfa10; 1 drivers +v0x1bd0880_0 .net "B", 0 0, L_0x1bdfe20; 1 drivers +v0x1bd0900_0 .alias "Command", 2 0, v0x1bd5470_0; +L_0x1bdfbe0 .part v0x1bd65b0_0, 0, 1; +S_0x1bd0080 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0x1bcff90; + .timescale -9 -12; +L_0x1bdf6f0/d .functor NOT 1, L_0x1bdfbe0, C4<0>, C4<0>, C4<0>; +L_0x1bdf6f0 .delay (10000,10000,10000) L_0x1bdf6f0/d; +L_0x1bdf7b0/d .functor AND 1, L_0x1bdf5c0, L_0x1bdf6f0, C4<1>, C4<1>; +L_0x1bdf7b0 .delay (20000,20000,20000) L_0x1bdf7b0/d; +L_0x1bdf8c0/d .functor AND 1, L_0x1bdf4a0, L_0x1bdfbe0, C4<1>, C4<1>; +L_0x1bdf8c0 .delay (20000,20000,20000) L_0x1bdf8c0/d; +L_0x1bdfa10/d .functor OR 1, L_0x1bdf7b0, L_0x1bdf8c0, C4<0>, C4<0>; +L_0x1bdfa10 .delay (20000,20000,20000) L_0x1bdfa10/d; +v0x1bd0170_0 .net "S", 0 0, L_0x1bdfbe0; 1 drivers +v0x1bd01f0_0 .alias "in0", 0 0, v0x1bd0670_0; +v0x1bd0270_0 .alias "in1", 0 0, v0x1bd06f0_0; +v0x1bd0310_0 .net "nS", 0 0, L_0x1bdf6f0; 1 drivers +v0x1bd0390_0 .net "out0", 0 0, L_0x1bdf7b0; 1 drivers +v0x1bd0430_0 .net "out1", 0 0, L_0x1bdf8c0; 1 drivers +v0x1bd0510_0 .alias "outfinal", 0 0, v0x1bd07a0_0; +S_0x1bcf3d0 .scope generate, "andbits[1]" "andbits[1]" 3 169, 3 169, S_0x1bcdb00; + .timescale -9 -12; +P_0x1bcf4c8 .param/l "i" 3 169, +C4<01>; +S_0x1bcf540 .scope module, "attempt" "AndNand" 3 171, 3 48, S_0x1bcf3d0; + .timescale -9 -12; +L_0x1bdd580/d .functor NAND 1, L_0x1bdde50, L_0x1bddef0, C4<1>, C4<1>; +L_0x1bdd580 .delay (10000,10000,10000) L_0x1bdd580/d; +L_0x1bdd640/d .functor NOT 1, L_0x1bdd580, C4<0>, C4<0>, C4<0>; +L_0x1bdd640 .delay (10000,10000,10000) L_0x1bdd640/d; +v0x1bcfb80_0 .net "A", 0 0, L_0x1bdde50; 1 drivers +v0x1bcfc40_0 .net "AandB", 0 0, L_0x1bdd640; 1 drivers +v0x1bcfcc0_0 .net "AnandB", 0 0, L_0x1bdd580; 1 drivers +v0x1bcfd70_0 .net "AndNandOut", 0 0, L_0x1bdda90; 1 drivers +v0x1bcfe50_0 .net "B", 0 0, L_0x1bddef0; 1 drivers +v0x1bcfed0_0 .alias "Command", 2 0, v0x1bd5470_0; +L_0x1bddc60 .part v0x1bd65b0_0, 0, 1; +S_0x1bcf630 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0x1bcf540; + .timescale -9 -12; +L_0x1bdd770/d .functor NOT 1, L_0x1bddc60, C4<0>, C4<0>, C4<0>; +L_0x1bdd770 .delay (10000,10000,10000) L_0x1bdd770/d; +L_0x1bdd830/d .functor AND 1, L_0x1bdd640, L_0x1bdd770, C4<1>, C4<1>; +L_0x1bdd830 .delay (20000,20000,20000) L_0x1bdd830/d; +L_0x1bdd940/d .functor AND 1, L_0x1bdd580, L_0x1bddc60, C4<1>, C4<1>; +L_0x1bdd940 .delay (20000,20000,20000) L_0x1bdd940/d; +L_0x1bdda90/d .functor OR 1, L_0x1bdd830, L_0x1bdd940, C4<0>, C4<0>; +L_0x1bdda90 .delay (20000,20000,20000) L_0x1bdda90/d; +v0x1bcf720_0 .net "S", 0 0, L_0x1bddc60; 1 drivers +v0x1bcf7a0_0 .alias "in0", 0 0, v0x1bcfc40_0; +v0x1bcf840_0 .alias "in1", 0 0, v0x1bcfcc0_0; +v0x1bcf8e0_0 .net "nS", 0 0, L_0x1bdd770; 1 drivers +v0x1bcf960_0 .net "out0", 0 0, L_0x1bdd830; 1 drivers +v0x1bcfa00_0 .net "out1", 0 0, L_0x1bdd940; 1 drivers +v0x1bcfae0_0 .alias "outfinal", 0 0, v0x1bcfd70_0; +S_0x1bce810 .scope generate, "andbits[2]" "andbits[2]" 3 169, 3 169, S_0x1bcdb00; + .timescale -9 -12; +P_0x1bce908 .param/l "i" 3 169, +C4<010>; +S_0x1bce980 .scope module, "attempt" "AndNand" 3 171, 3 48, S_0x1bce810; + .timescale -9 -12; +L_0x1bddf90/d .functor NAND 1, L_0x1bde850, L_0x1bde8f0, C4<1>, C4<1>; +L_0x1bddf90 .delay (10000,10000,10000) L_0x1bddf90/d; +L_0x1bde0f0/d .functor NOT 1, L_0x1bddf90, C4<0>, C4<0>, C4<0>; +L_0x1bde0f0 .delay (10000,10000,10000) L_0x1bde0f0/d; +v0x1bcefc0_0 .net "A", 0 0, L_0x1bde850; 1 drivers +v0x1bcf080_0 .net "AandB", 0 0, L_0x1bde0f0; 1 drivers +v0x1bcf100_0 .net "AnandB", 0 0, L_0x1bddf90; 1 drivers +v0x1bcf1b0_0 .net "AndNandOut", 0 0, L_0x1bde540; 1 drivers +v0x1bcf290_0 .net "B", 0 0, L_0x1bde8f0; 1 drivers +v0x1bcf310_0 .alias "Command", 2 0, v0x1bd5470_0; +L_0x1bde710 .part v0x1bd65b0_0, 0, 1; +S_0x1bcea70 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0x1bce980; + .timescale -9 -12; +L_0x1bde220/d .functor NOT 1, L_0x1bde710, C4<0>, C4<0>, C4<0>; +L_0x1bde220 .delay (10000,10000,10000) L_0x1bde220/d; +L_0x1bde2e0/d .functor AND 1, L_0x1bde0f0, L_0x1bde220, C4<1>, C4<1>; +L_0x1bde2e0 .delay (20000,20000,20000) L_0x1bde2e0/d; +L_0x1bde3f0/d .functor AND 1, L_0x1bddf90, L_0x1bde710, C4<1>, C4<1>; +L_0x1bde3f0 .delay (20000,20000,20000) L_0x1bde3f0/d; +L_0x1bde540/d .functor OR 1, L_0x1bde2e0, L_0x1bde3f0, C4<0>, C4<0>; +L_0x1bde540 .delay (20000,20000,20000) L_0x1bde540/d; +v0x1bceb60_0 .net "S", 0 0, L_0x1bde710; 1 drivers +v0x1bcebe0_0 .alias "in0", 0 0, v0x1bcf080_0; +v0x1bcec80_0 .alias "in1", 0 0, v0x1bcf100_0; +v0x1bced20_0 .net "nS", 0 0, L_0x1bde220; 1 drivers +v0x1bceda0_0 .net "out0", 0 0, L_0x1bde2e0; 1 drivers +v0x1bcee40_0 .net "out1", 0 0, L_0x1bde3f0; 1 drivers +v0x1bcef20_0 .alias "outfinal", 0 0, v0x1bcf1b0_0; +S_0x1bcdc30 .scope generate, "andbits[3]" "andbits[3]" 3 169, 3 169, S_0x1bcdb00; + .timescale -9 -12; +P_0x1bcdd28 .param/l "i" 3 169, +C4<011>; +S_0x1bcdda0 .scope module, "attempt" "AndNand" 3 171, 3 48, S_0x1bcdc30; + .timescale -9 -12; +L_0x1bdea20/d .functor NAND 1, L_0x1bdf2c0, L_0x1bdf3b0, C4<1>, C4<1>; +L_0x1bdea20 .delay (10000,10000,10000) L_0x1bdea20/d; +L_0x1bdeb60/d .functor NOT 1, L_0x1bdea20, C4<0>, C4<0>, C4<0>; +L_0x1bdeb60 .delay (10000,10000,10000) L_0x1bdeb60/d; +v0x1bce400_0 .net "A", 0 0, L_0x1bdf2c0; 1 drivers +v0x1bce4c0_0 .net "AandB", 0 0, L_0x1bdeb60; 1 drivers +v0x1bce540_0 .net "AnandB", 0 0, L_0x1bdea20; 1 drivers +v0x1bce5f0_0 .net "AndNandOut", 0 0, L_0x1bdefb0; 1 drivers +v0x1bce6d0_0 .net "B", 0 0, L_0x1bdf3b0; 1 drivers +v0x1bce750_0 .alias "Command", 2 0, v0x1bd5470_0; +L_0x1bdf180 .part v0x1bd65b0_0, 0, 1; +S_0x1bcde90 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0x1bcdda0; + .timescale -9 -12; +L_0x1bdec90/d .functor NOT 1, L_0x1bdf180, C4<0>, C4<0>, C4<0>; +L_0x1bdec90 .delay (10000,10000,10000) L_0x1bdec90/d; +L_0x1bded50/d .functor AND 1, L_0x1bdeb60, L_0x1bdec90, C4<1>, C4<1>; +L_0x1bded50 .delay (20000,20000,20000) L_0x1bded50/d; +L_0x1bdee60/d .functor AND 1, L_0x1bdea20, L_0x1bdf180, C4<1>, C4<1>; +L_0x1bdee60 .delay (20000,20000,20000) L_0x1bdee60/d; +L_0x1bdefb0/d .functor OR 1, L_0x1bded50, L_0x1bdee60, C4<0>, C4<0>; +L_0x1bdefb0 .delay (20000,20000,20000) L_0x1bdefb0/d; +v0x1bcdf80_0 .net "S", 0 0, L_0x1bdf180; 1 drivers +v0x1bce020_0 .alias "in0", 0 0, v0x1bce4c0_0; +v0x1bce0c0_0 .alias "in1", 0 0, v0x1bce540_0; +v0x1bce160_0 .net "nS", 0 0, L_0x1bdec90; 1 drivers +v0x1bce1e0_0 .net "out0", 0 0, L_0x1bded50; 1 drivers +v0x1bce280_0 .net "out1", 0 0, L_0x1bdee60; 1 drivers +v0x1bce360_0 .alias "outfinal", 0 0, v0x1bce5f0_0; +S_0x1bc88a0 .scope module, "trial2" "OrNorXor32" 2 145, 3 177, S_0x1b740f0; + .timescale -9 -12; +P_0x1bc62c8 .param/l "size" 3 184, +C4<0100>; +v0x1bcd7e0_0 .alias "A", 3 0, v0x1bd5250_0; +v0x1bcd8f0_0 .alias "B", 3 0, v0x1bd5370_0; +v0x1bcda00_0 .alias "Command", 2 0, v0x1bd5470_0; +v0x1bcda80_0 .alias "OrNorXorOut", 3 0, v0x1bd66b0_0; +L_0x1be0fd0 .part/pv L_0x1be0d60, 1, 1, 4; +L_0x1be1100 .part v0x1bd6330_0, 1, 1; +L_0x1bd7f30 .part v0x1bd6530_0, 1, 1; +L_0x1be2530 .part/pv L_0x1be22c0, 2, 1, 4; +L_0x1be25d0 .part v0x1bd6330_0, 2, 1; +L_0x1be2670 .part v0x1bd6530_0, 2, 1; +L_0x1be3830 .part/pv L_0x1be35c0, 3, 1, 4; +L_0x1be38d0 .part v0x1bd6330_0, 3, 1; +L_0x1be3970 .part v0x1bd6530_0, 3, 1; +L_0x1be48e0 .part/pv L_0x1be46b0, 0, 1, 4; +L_0x1be49e0 .part v0x1bd6330_0, 0, 1; +L_0x1be4a80 .part v0x1bd6530_0, 0, 1; +S_0x1bcc5a0 .scope module, "attempt2" "OrNorXor" 3 192, 3 64, S_0x1bc88a0; + .timescale -9 -12; +L_0x1be3a10/d .functor NOR 1, L_0x1be49e0, L_0x1be4a80, C4<0>, C4<0>; +L_0x1be3a10 .delay (10000,10000,10000) L_0x1be3a10/d; +L_0x1be3b10/d .functor NOT 1, L_0x1be3a10, C4<0>, C4<0>, C4<0>; +L_0x1be3b10 .delay (10000,10000,10000) L_0x1be3b10/d; +L_0x1be3c40/d .functor NAND 1, L_0x1be49e0, L_0x1be4a80, C4<1>, C4<1>; +L_0x1be3c40 .delay (10000,10000,10000) L_0x1be3c40/d; +L_0x1be3da0/d .functor NAND 1, L_0x1be3c40, L_0x1be3b10, C4<1>, C4<1>; +L_0x1be3da0 .delay (10000,10000,10000) L_0x1be3da0/d; +L_0x1be3eb0/d .functor NOT 1, L_0x1be3da0, C4<0>, C4<0>, C4<0>; +L_0x1be3eb0 .delay (10000,10000,10000) L_0x1be3eb0/d; +v0x1bcd0f0_0 .net "A", 0 0, L_0x1be49e0; 1 drivers +v0x1bcd190_0 .net "AnandB", 0 0, L_0x1be3c40; 1 drivers +v0x1bcd230_0 .net "AnorB", 0 0, L_0x1be3a10; 1 drivers +v0x1bcd2e0_0 .net "AorB", 0 0, L_0x1be3b10; 1 drivers +v0x1bcd3c0_0 .net "AxorB", 0 0, L_0x1be3eb0; 1 drivers +v0x1bcd470_0 .net "B", 0 0, L_0x1be4a80; 1 drivers +v0x1bcd530_0 .alias "Command", 2 0, v0x1bd5470_0; +v0x1bcd5b0_0 .net "OrNorXorOut", 0 0, L_0x1be46b0; 1 drivers +v0x1bcd630_0 .net "XorNor", 0 0, L_0x1be41d0; 1 drivers +v0x1bcd700_0 .net "nXor", 0 0, L_0x1be3da0; 1 drivers +L_0x1be4310 .part v0x1bd65b0_0, 2, 1; +L_0x1be4840 .part v0x1bd65b0_0, 0, 1; +S_0x1bccb80 .scope module, "mux0" "TwoInMux" 3 83, 3 8, S_0x1bcc5a0; + .timescale -9 -12; +L_0x1bd0820/d .functor NOT 1, L_0x1be4310, C4<0>, C4<0>, C4<0>; +L_0x1bd0820 .delay (10000,10000,10000) L_0x1bd0820/d; +L_0x1be3fa0/d .functor AND 1, L_0x1be3eb0, L_0x1bd0820, C4<1>, C4<1>; +L_0x1be3fa0 .delay (20000,20000,20000) L_0x1be3fa0/d; +L_0x1be40a0/d .functor AND 1, L_0x1be3a10, L_0x1be4310, C4<1>, C4<1>; +L_0x1be40a0 .delay (20000,20000,20000) L_0x1be40a0/d; +L_0x1be41d0/d .functor OR 1, L_0x1be3fa0, L_0x1be40a0, C4<0>, C4<0>; +L_0x1be41d0 .delay (20000,20000,20000) L_0x1be41d0/d; +v0x1bccc70_0 .net "S", 0 0, L_0x1be4310; 1 drivers +v0x1bccd30_0 .alias "in0", 0 0, v0x1bcd3c0_0; +v0x1bccdd0_0 .alias "in1", 0 0, v0x1bcd230_0; +v0x1bcce70_0 .net "nS", 0 0, L_0x1bd0820; 1 drivers +v0x1bccef0_0 .net "out0", 0 0, L_0x1be3fa0; 1 drivers +v0x1bccf90_0 .net "out1", 0 0, L_0x1be40a0; 1 drivers +v0x1bcd070_0 .alias "outfinal", 0 0, v0x1bcd630_0; +S_0x1bcc690 .scope module, "mux1" "TwoInMux" 3 84, 3 8, S_0x1bcc5a0; + .timescale -9 -12; +L_0x1be43b0/d .functor NOT 1, L_0x1be4840, C4<0>, C4<0>, C4<0>; +L_0x1be43b0 .delay (10000,10000,10000) L_0x1be43b0/d; +L_0x1be4450/d .functor AND 1, L_0x1be41d0, L_0x1be43b0, C4<1>, C4<1>; +L_0x1be4450 .delay (20000,20000,20000) L_0x1be4450/d; +L_0x1be4580/d .functor AND 1, L_0x1be3b10, L_0x1be4840, C4<1>, C4<1>; +L_0x1be4580 .delay (20000,20000,20000) L_0x1be4580/d; +L_0x1be46b0/d .functor OR 1, L_0x1be4450, L_0x1be4580, C4<0>, C4<0>; +L_0x1be46b0 .delay (20000,20000,20000) L_0x1be46b0/d; +v0x1bcc780_0 .net "S", 0 0, L_0x1be4840; 1 drivers +v0x1bcc800_0 .alias "in0", 0 0, v0x1bcd630_0; +v0x1bcc880_0 .alias "in1", 0 0, v0x1bcd2e0_0; +v0x1bcc920_0 .net "nS", 0 0, L_0x1be43b0; 1 drivers +v0x1bcc9a0_0 .net "out0", 0 0, L_0x1be4450; 1 drivers +v0x1bcca40_0 .net "out1", 0 0, L_0x1be4580; 1 drivers +v0x1bccae0_0 .alias "outfinal", 0 0, v0x1bcd5b0_0; +S_0x1bcb1d0 .scope generate, "orbits[1]" "orbits[1]" 3 196, 3 196, S_0x1bc88a0; + .timescale -9 -12; +P_0x1bcaee8 .param/l "i" 3 196, +C4<01>; +S_0x1bcb300 .scope module, "attempt" "OrNorXor" 3 198, 3 64, S_0x1bcb1d0; + .timescale -9 -12; +L_0x1bdfd20/d .functor NOR 1, L_0x1be1100, L_0x1bd7f30, C4<0>, C4<0>; +L_0x1bdfd20 .delay (10000,10000,10000) L_0x1bdfd20/d; +L_0x1bdffc0/d .functor NOT 1, L_0x1bdfd20, C4<0>, C4<0>, C4<0>; +L_0x1bdffc0 .delay (10000,10000,10000) L_0x1bdffc0/d; +L_0x1be00f0/d .functor NAND 1, L_0x1be1100, L_0x1bd7f30, C4<1>, C4<1>; +L_0x1be00f0 .delay (10000,10000,10000) L_0x1be00f0/d; +L_0x1be0250/d .functor NAND 1, L_0x1be00f0, L_0x1bdffc0, C4<1>, C4<1>; +L_0x1be0250 .delay (10000,10000,10000) L_0x1be0250/d; +L_0x1be0360/d .functor NOT 1, L_0x1be0250, C4<0>, C4<0>, C4<0>; +L_0x1be0360 .delay (10000,10000,10000) L_0x1be0360/d; +v0x1bcbeb0_0 .net "A", 0 0, L_0x1be1100; 1 drivers +v0x1bcbf50_0 .net "AnandB", 0 0, L_0x1be00f0; 1 drivers +v0x1bcbff0_0 .net "AnorB", 0 0, L_0x1bdfd20; 1 drivers +v0x1bcc0a0_0 .net "AorB", 0 0, L_0x1bdffc0; 1 drivers +v0x1bcc180_0 .net "AxorB", 0 0, L_0x1be0360; 1 drivers +v0x1bcc230_0 .net "B", 0 0, L_0x1bd7f30; 1 drivers +v0x1bcc2f0_0 .alias "Command", 2 0, v0x1bd5470_0; +v0x1bcc370_0 .net "OrNorXorOut", 0 0, L_0x1be0d60; 1 drivers +v0x1bcc3f0_0 .net "XorNor", 0 0, L_0x1be07e0; 1 drivers +v0x1bcc4c0_0 .net "nXor", 0 0, L_0x1be0250; 1 drivers +L_0x1be0960 .part v0x1bd65b0_0, 2, 1; +L_0x1be0f30 .part v0x1bd65b0_0, 0, 1; +S_0x1bcb940 .scope module, "mux0" "TwoInMux" 3 83, 3 8, S_0x1bcb300; + .timescale -9 -12; +L_0x1be04c0/d .functor NOT 1, L_0x1be0960, C4<0>, C4<0>, C4<0>; +L_0x1be04c0 .delay (10000,10000,10000) L_0x1be04c0/d; +L_0x1be0580/d .functor AND 1, L_0x1be0360, L_0x1be04c0, C4<1>, C4<1>; +L_0x1be0580 .delay (20000,20000,20000) L_0x1be0580/d; +L_0x1be0690/d .functor AND 1, L_0x1bdfd20, L_0x1be0960, C4<1>, C4<1>; +L_0x1be0690 .delay (20000,20000,20000) L_0x1be0690/d; +L_0x1be07e0/d .functor OR 1, L_0x1be0580, L_0x1be0690, C4<0>, C4<0>; +L_0x1be07e0 .delay (20000,20000,20000) L_0x1be07e0/d; +v0x1bcba30_0 .net "S", 0 0, L_0x1be0960; 1 drivers +v0x1bcbaf0_0 .alias "in0", 0 0, v0x1bcc180_0; +v0x1bcbb90_0 .alias "in1", 0 0, v0x1bcbff0_0; +v0x1bcbc30_0 .net "nS", 0 0, L_0x1be04c0; 1 drivers +v0x1bcbcb0_0 .net "out0", 0 0, L_0x1be0580; 1 drivers +v0x1bcbd50_0 .net "out1", 0 0, L_0x1be0690; 1 drivers +v0x1bcbe30_0 .alias "outfinal", 0 0, v0x1bcc3f0_0; +S_0x1bcb3f0 .scope module, "mux1" "TwoInMux" 3 84, 3 8, S_0x1bcb300; + .timescale -9 -12; +L_0x1be0a00/d .functor NOT 1, L_0x1be0f30, C4<0>, C4<0>, C4<0>; +L_0x1be0a00 .delay (10000,10000,10000) L_0x1be0a00/d; +L_0x1be0ac0/d .functor AND 1, L_0x1be07e0, L_0x1be0a00, C4<1>, C4<1>; +L_0x1be0ac0 .delay (20000,20000,20000) L_0x1be0ac0/d; +L_0x1be0c10/d .functor AND 1, L_0x1bdffc0, L_0x1be0f30, C4<1>, C4<1>; +L_0x1be0c10 .delay (20000,20000,20000) L_0x1be0c10/d; +L_0x1be0d60/d .functor OR 1, L_0x1be0ac0, L_0x1be0c10, C4<0>, C4<0>; +L_0x1be0d60 .delay (20000,20000,20000) L_0x1be0d60/d; +v0x1bcb4e0_0 .net "S", 0 0, L_0x1be0f30; 1 drivers +v0x1bcb560_0 .alias "in0", 0 0, v0x1bcc3f0_0; +v0x1bcb600_0 .alias "in1", 0 0, v0x1bcc0a0_0; +v0x1bcb6a0_0 .net "nS", 0 0, L_0x1be0a00; 1 drivers +v0x1bcb720_0 .net "out0", 0 0, L_0x1be0ac0; 1 drivers +v0x1bcb7c0_0 .net "out1", 0 0, L_0x1be0c10; 1 drivers +v0x1bcb8a0_0 .alias "outfinal", 0 0, v0x1bcc370_0; +S_0x1bc9e00 .scope generate, "orbits[2]" "orbits[2]" 3 196, 3 196, S_0x1bc88a0; + .timescale -9 -12; +P_0x1bc9a68 .param/l "i" 3 196, +C4<010>; +S_0x1bc9f30 .scope module, "attempt" "OrNorXor" 3 198, 3 64, S_0x1bc9e00; + .timescale -9 -12; +L_0x1bd7fd0/d .functor NOR 1, L_0x1be25d0, L_0x1be2670, C4<0>, C4<0>; +L_0x1bd7fd0 .delay (10000,10000,10000) L_0x1bd7fd0/d; +L_0x1bd8140/d .functor NOT 1, L_0x1bd7fd0, C4<0>, C4<0>, C4<0>; +L_0x1bd8140 .delay (10000,10000,10000) L_0x1bd8140/d; +L_0x1be1650/d .functor NAND 1, L_0x1be25d0, L_0x1be2670, C4<1>, C4<1>; +L_0x1be1650 .delay (10000,10000,10000) L_0x1be1650/d; +L_0x1be17b0/d .functor NAND 1, L_0x1be1650, L_0x1bd8140, C4<1>, C4<1>; +L_0x1be17b0 .delay (10000,10000,10000) L_0x1be17b0/d; +L_0x1be18c0/d .functor NOT 1, L_0x1be17b0, C4<0>, C4<0>, C4<0>; +L_0x1be18c0 .delay (10000,10000,10000) L_0x1be18c0/d; +v0x1bcaae0_0 .net "A", 0 0, L_0x1be25d0; 1 drivers +v0x1bcab80_0 .net "AnandB", 0 0, L_0x1be1650; 1 drivers +v0x1bcac20_0 .net "AnorB", 0 0, L_0x1bd7fd0; 1 drivers +v0x1bcacd0_0 .net "AorB", 0 0, L_0x1bd8140; 1 drivers +v0x1bcadb0_0 .net "AxorB", 0 0, L_0x1be18c0; 1 drivers +v0x1bcae60_0 .net "B", 0 0, L_0x1be2670; 1 drivers +v0x1bcaf20_0 .alias "Command", 2 0, v0x1bd5470_0; +v0x1bcafa0_0 .net "OrNorXorOut", 0 0, L_0x1be22c0; 1 drivers +v0x1bcb020_0 .net "XorNor", 0 0, L_0x1be1d40; 1 drivers +v0x1bcb0f0_0 .net "nXor", 0 0, L_0x1be17b0; 1 drivers +L_0x1be1ec0 .part v0x1bd65b0_0, 2, 1; +L_0x1be2490 .part v0x1bd65b0_0, 0, 1; +S_0x1bca570 .scope module, "mux0" "TwoInMux" 3 83, 3 8, S_0x1bc9f30; + .timescale -9 -12; +L_0x1be1a20/d .functor NOT 1, L_0x1be1ec0, C4<0>, C4<0>, C4<0>; +L_0x1be1a20 .delay (10000,10000,10000) L_0x1be1a20/d; +L_0x1be1ae0/d .functor AND 1, L_0x1be18c0, L_0x1be1a20, C4<1>, C4<1>; +L_0x1be1ae0 .delay (20000,20000,20000) L_0x1be1ae0/d; +L_0x1be1bf0/d .functor AND 1, L_0x1bd7fd0, L_0x1be1ec0, C4<1>, C4<1>; +L_0x1be1bf0 .delay (20000,20000,20000) L_0x1be1bf0/d; +L_0x1be1d40/d .functor OR 1, L_0x1be1ae0, L_0x1be1bf0, C4<0>, C4<0>; +L_0x1be1d40 .delay (20000,20000,20000) L_0x1be1d40/d; +v0x1bca660_0 .net "S", 0 0, L_0x1be1ec0; 1 drivers +v0x1bca720_0 .alias "in0", 0 0, v0x1bcadb0_0; +v0x1bca7c0_0 .alias "in1", 0 0, v0x1bcac20_0; +v0x1bca860_0 .net "nS", 0 0, L_0x1be1a20; 1 drivers +v0x1bca8e0_0 .net "out0", 0 0, L_0x1be1ae0; 1 drivers +v0x1bca980_0 .net "out1", 0 0, L_0x1be1bf0; 1 drivers +v0x1bcaa60_0 .alias "outfinal", 0 0, v0x1bcb020_0; +S_0x1bca020 .scope module, "mux1" "TwoInMux" 3 84, 3 8, S_0x1bc9f30; + .timescale -9 -12; +L_0x1be1f60/d .functor NOT 1, L_0x1be2490, C4<0>, C4<0>, C4<0>; +L_0x1be1f60 .delay (10000,10000,10000) L_0x1be1f60/d; +L_0x1be2020/d .functor AND 1, L_0x1be1d40, L_0x1be1f60, C4<1>, C4<1>; +L_0x1be2020 .delay (20000,20000,20000) L_0x1be2020/d; +L_0x1be2170/d .functor AND 1, L_0x1bd8140, L_0x1be2490, C4<1>, C4<1>; +L_0x1be2170 .delay (20000,20000,20000) L_0x1be2170/d; +L_0x1be22c0/d .functor OR 1, L_0x1be2020, L_0x1be2170, C4<0>, C4<0>; +L_0x1be22c0 .delay (20000,20000,20000) L_0x1be22c0/d; +v0x1bca110_0 .net "S", 0 0, L_0x1be2490; 1 drivers +v0x1bca190_0 .alias "in0", 0 0, v0x1bcb020_0; +v0x1bca230_0 .alias "in1", 0 0, v0x1bcacd0_0; +v0x1bca2d0_0 .net "nS", 0 0, L_0x1be1f60; 1 drivers +v0x1bca350_0 .net "out0", 0 0, L_0x1be2020; 1 drivers +v0x1bca3f0_0 .net "out1", 0 0, L_0x1be2170; 1 drivers +v0x1bca4d0_0 .alias "outfinal", 0 0, v0x1bcafa0_0; +S_0x1bc8990 .scope generate, "orbits[3]" "orbits[3]" 3 196, 3 196, S_0x1bc88a0; + .timescale -9 -12; +P_0x1bc86d8 .param/l "i" 3 196, +C4<011>; +S_0x1bc8a80 .scope module, "attempt" "OrNorXor" 3 198, 3 64, S_0x1bc8990; + .timescale -9 -12; +L_0x1be2750/d .functor NOR 1, L_0x1be38d0, L_0x1be3970, C4<0>, C4<0>; +L_0x1be2750 .delay (10000,10000,10000) L_0x1be2750/d; +L_0x1be2840/d .functor NOT 1, L_0x1be2750, C4<0>, C4<0>, C4<0>; +L_0x1be2840 .delay (10000,10000,10000) L_0x1be2840/d; +L_0x1be2950/d .functor NAND 1, L_0x1be38d0, L_0x1be3970, C4<1>, C4<1>; +L_0x1be2950 .delay (10000,10000,10000) L_0x1be2950/d; +L_0x1be2ab0/d .functor NAND 1, L_0x1be2950, L_0x1be2840, C4<1>, C4<1>; +L_0x1be2ab0 .delay (10000,10000,10000) L_0x1be2ab0/d; +L_0x1be2bc0/d .functor NOT 1, L_0x1be2ab0, C4<0>, C4<0>, C4<0>; +L_0x1be2bc0 .delay (10000,10000,10000) L_0x1be2bc0/d; +v0x1bc9660_0 .net "A", 0 0, L_0x1be38d0; 1 drivers +v0x1bc9700_0 .net "AnandB", 0 0, L_0x1be2950; 1 drivers +v0x1bc97a0_0 .net "AnorB", 0 0, L_0x1be2750; 1 drivers +v0x1bc9850_0 .net "AorB", 0 0, L_0x1be2840; 1 drivers +v0x1bc9930_0 .net "AxorB", 0 0, L_0x1be2bc0; 1 drivers +v0x1bc99e0_0 .net "B", 0 0, L_0x1be3970; 1 drivers +v0x1bc9aa0_0 .alias "Command", 2 0, v0x1bd5470_0; +v0x1bc1ef0_0 .net "OrNorXorOut", 0 0, L_0x1be35c0; 1 drivers +v0x1bc1f70_0 .net "XorNor", 0 0, L_0x1be3040; 1 drivers +v0x1bc9d80_0 .net "nXor", 0 0, L_0x1be2ab0; 1 drivers +L_0x1be31c0 .part v0x1bd65b0_0, 2, 1; +L_0x1be3790 .part v0x1bd65b0_0, 0, 1; +S_0x1bc90f0 .scope module, "mux0" "TwoInMux" 3 83, 3 8, S_0x1bc8a80; + .timescale -9 -12; +L_0x1be2d20/d .functor NOT 1, L_0x1be31c0, C4<0>, C4<0>, C4<0>; +L_0x1be2d20 .delay (10000,10000,10000) L_0x1be2d20/d; +L_0x1be2de0/d .functor AND 1, L_0x1be2bc0, L_0x1be2d20, C4<1>, C4<1>; +L_0x1be2de0 .delay (20000,20000,20000) L_0x1be2de0/d; +L_0x1be2ef0/d .functor AND 1, L_0x1be2750, L_0x1be31c0, C4<1>, C4<1>; +L_0x1be2ef0 .delay (20000,20000,20000) L_0x1be2ef0/d; +L_0x1be3040/d .functor OR 1, L_0x1be2de0, L_0x1be2ef0, C4<0>, C4<0>; +L_0x1be3040 .delay (20000,20000,20000) L_0x1be3040/d; +v0x1bc91e0_0 .net "S", 0 0, L_0x1be31c0; 1 drivers +v0x1bc92a0_0 .alias "in0", 0 0, v0x1bc9930_0; +v0x1bc9340_0 .alias "in1", 0 0, v0x1bc97a0_0; +v0x1bc93e0_0 .net "nS", 0 0, L_0x1be2d20; 1 drivers +v0x1bc9460_0 .net "out0", 0 0, L_0x1be2de0; 1 drivers +v0x1bc9500_0 .net "out1", 0 0, L_0x1be2ef0; 1 drivers +v0x1bc95e0_0 .alias "outfinal", 0 0, v0x1bc1f70_0; +S_0x1bc8b70 .scope module, "mux1" "TwoInMux" 3 84, 3 8, S_0x1bc8a80; + .timescale -9 -12; +L_0x1be3260/d .functor NOT 1, L_0x1be3790, C4<0>, C4<0>, C4<0>; +L_0x1be3260 .delay (10000,10000,10000) L_0x1be3260/d; +L_0x1be3320/d .functor AND 1, L_0x1be3040, L_0x1be3260, C4<1>, C4<1>; +L_0x1be3320 .delay (20000,20000,20000) L_0x1be3320/d; +L_0x1be3470/d .functor AND 1, L_0x1be2840, L_0x1be3790, C4<1>, C4<1>; +L_0x1be3470 .delay (20000,20000,20000) L_0x1be3470/d; +L_0x1be35c0/d .functor OR 1, L_0x1be3320, L_0x1be3470, C4<0>, C4<0>; +L_0x1be35c0 .delay (20000,20000,20000) L_0x1be35c0/d; +v0x1bc8c60_0 .net "S", 0 0, L_0x1be3790; 1 drivers +v0x1bc8ce0_0 .alias "in0", 0 0, v0x1bc1f70_0; +v0x1bc8d80_0 .alias "in1", 0 0, v0x1bc9850_0; +v0x1bc8e20_0 .net "nS", 0 0, L_0x1be3260; 1 drivers +v0x1bc8ed0_0 .net "out0", 0 0, L_0x1be3320; 1 drivers +v0x1bc8f70_0 .net "out1", 0 0, L_0x1be3470; 1 drivers +v0x1bc9050_0 .alias "outfinal", 0 0, v0x1bc1ef0_0; +S_0x1b51ae0 .scope module, "superalu" "Bitslice32" 2 147, 3 256, S_0x1b740f0; + .timescale -9 -12; +P_0x1b298c8 .param/l "size" 3 273, +C4<0100>; +L_0x1be9d90/d .functor AND 1, L_0x1bfca80, L_0x1bfcc60, C4<1>, C4<1>; +L_0x1be9d90 .delay (20000,20000,20000) L_0x1be9d90/d; +L_0x1bfcd50/d .functor NOT 1, L_0x1bfce00, C4<0>, C4<0>, C4<0>; +L_0x1bfcd50 .delay (10000,10000,10000) L_0x1bfcd50/d; +L_0x1bfd2b0/d .functor AND 1, L_0x1bfcd50, L_0x1bfcd50, C4<1>, C4<1>; +L_0x1bfd2b0 .delay (20000,20000,20000) L_0x1bfd2b0/d; +v0x1bc7790_0 .alias "A", 3 0, v0x1bd5250_0; +v0x1bc7980_0 .alias "AddSubSLTSum", 3 0, v0x1bd63b0_0; +v0x1bc7a00_0 .alias "AllZeros", 0 0, v0x1bd6430_0; +v0x1bc7a80_0 .alias "AndNandOut", 3 0, v0x1bd64b0_0; +v0x1bc7b30_0 .alias "B", 3 0, v0x1bd5370_0; +RS_0x7f6a63aa1008 .resolv tri, L_0x1be5290, L_0x1be7cf0, L_0x1beaaf0, L_0x1bfae50; +v0x1bc7bb0_0 .net8 "Cmd0Start", 3 0, RS_0x7f6a63aa1008; 4 drivers +RS_0x7f6a63aa1038 .resolv tri, L_0x1be6200, L_0x1be8be0, L_0x1bebae0, L_0x1bfbc80; +v0x1bc7c30_0 .net8 "Cmd1Start", 3 0, RS_0x7f6a63aa1038; 4 drivers +v0x1bc7cb0_0 .alias "Command", 2 0, v0x1bd5470_0; +v0x1bc7d30_0 .alias "OneBitFinalOut", 3 0, v0x1bd6630_0; +v0x1bc7dd0_0 .alias "OrNorXorOut", 3 0, v0x1bd66b0_0; +v0x1bc7e50_0 .alias "SLTflag", 0 0, v0x1bd6730_0; +v0x1bc7f00_0 .alias "ZeroFlag", 3 0, v0x1bd67b0_0; +v0x1bc7f80_0 .net *"_s111", 0 0, L_0x1be9d90; 1 drivers +v0x1bc8000_0 .net *"_s114", 0 0, L_0x1bfca80; 1 drivers +v0x1bc8120_0 .net *"_s116", 0 0, L_0x1bfcc60; 1 drivers +v0x1bc81c0_0 .net *"_s118", 0 0, L_0x1bfce00; 1 drivers +v0x1bc8080_0 .net *"_s21", 0 0, L_0x1be7250; 1 drivers +v0x1bc8310_0 .net *"_s46", 0 0, L_0x1be9660; 1 drivers +v0x1bc8430_0 .net *"_s71", 0 0, L_0x1bec8a0; 1 drivers +v0x1bc84b0_0 .alias "carryin", 3 0, v0x1bd5ea0_0; +v0x1bc8390_0 .alias "carryout", 0 0, v0x1bd68b0_0; +v0x1bc8610_0 .alias "overflow", 0 0, v0x1bd6930_0; +v0x1bc8560_0 .alias "subtract", 3 0, v0x1bd69b0_0; +v0x1bc8750_0 .net "yeszero", 0 0, L_0x1bfcd50; 1 drivers +L_0x1be5290 .part/pv L_0x1be5080, 1, 1, 4; +L_0x1be5330 .part v0x1bd65b0_0, 0, 1; +L_0x1be5460 .part v0x1bd65b0_0, 1, 1; +L_0x1be5590 .part RS_0x7f6a63aa0be8, 1, 1; +L_0x1be5630 .part RS_0x7f6a63aa0be8, 1, 1; +L_0x1be56d0 .part RS_0x7f6a63a9f748, 1, 1; +L_0x1be58d0 .part RS_0x7f6a63aa0be8, 1, 1; +L_0x1be6200 .part/pv L_0x1be5ff0, 1, 1, 4; +L_0x1be62f0 .part v0x1bd65b0_0, 0, 1; +L_0x1be6420 .part v0x1bd65b0_0, 1, 1; +L_0x1be65b0 .part RS_0x7f6a63a9fe38, 1, 1; +L_0x1be6760 .part RS_0x7f6a63a9fe38, 1, 1; +L_0x1be6800 .part RS_0x7f6a63a9f748, 1, 1; +L_0x1be68a0 .part RS_0x7f6a63a9f748, 1, 1; +L_0x1be6d00 .part/pv L_0x1be6bc0, 1, 1, 4; +L_0x1be6df0 .part v0x1bd65b0_0, 2, 1; +L_0x1be6e90 .part RS_0x7f6a63aa1008, 1, 1; +L_0x1be6fd0 .part RS_0x7f6a63aa1038, 1, 1; +L_0x1be71b0 .part/pv L_0x1be7250, 1, 1, 4; +L_0x1be7350 .part RS_0x7f6a63aa1098, 0, 1; +L_0x1be7110 .part RS_0x7f6a63aa1068, 1, 1; +L_0x1be7cf0 .part/pv L_0x1be7ae0, 2, 1, 4; +L_0x1be73f0 .part v0x1bd65b0_0, 0, 1; +L_0x1be7ee0 .part v0x1bd65b0_0, 1, 1; +L_0x1be7d90 .part RS_0x7f6a63aa0be8, 2, 1; +L_0x1be80e0 .part RS_0x7f6a63aa0be8, 2, 1; +L_0x1be8010 .part RS_0x7f6a63a9f748, 2, 1; +L_0x1be82b0 .part RS_0x7f6a63aa0be8, 2, 1; +L_0x1be8be0 .part/pv L_0x1be89d0, 2, 1, 4; +L_0x1be8c80 .part v0x1bd65b0_0, 0, 1; +L_0x1be83a0 .part v0x1bd65b0_0, 1, 1; +L_0x1bd7280 .part RS_0x7f6a63a9fe38, 2, 1; +L_0x1bd7430 .part RS_0x7f6a63a9fe38, 2, 1; +L_0x1bd70f0 .part RS_0x7f6a63a9f748, 2, 1; +L_0x1bd7320 .part RS_0x7f6a63a9f748, 2, 1; +L_0x1be9a90 .part/pv L_0x1be9950, 2, 1, 4; +L_0x1be95c0 .part v0x1bd65b0_0, 2, 1; +L_0x1be9cf0 .part RS_0x7f6a63aa1008, 2, 1; +L_0x1be9bc0 .part RS_0x7f6a63aa1038, 2, 1; +L_0x1be9f60 .part/pv L_0x1be9660, 2, 1, 4; +L_0x1be9e60 .part RS_0x7f6a63aa1098, 1, 1; +L_0x1bea1e0 .part RS_0x7f6a63aa1068, 2, 1; +L_0x1beaaf0 .part/pv L_0x1bea8e0, 3, 1, 4; +L_0x1beab90 .part v0x1bd65b0_0, 0, 1; +L_0x1bea280 .part v0x1bd65b0_0, 1, 1; +L_0x1beae30 .part RS_0x7f6a63aa0be8, 3, 1; +L_0x1bdcd20 .part RS_0x7f6a63aa0be8, 3, 1; +L_0x1beacc0 .part RS_0x7f6a63a9f748, 3, 1; +L_0x1beb270 .part RS_0x7f6a63aa0be8, 3, 1; +L_0x1bebae0 .part/pv L_0x1beb8d0, 3, 1, 4; +L_0x1beb0e0 .part v0x1bd65b0_0, 0, 1; +L_0x1bebd20 .part v0x1bd65b0_0, 1, 1; +L_0x1bebb80 .part RS_0x7f6a63a9fe38, 3, 1; +L_0x1bebc20 .part RS_0x7f6a63a9fe38, 3, 1; +L_0x1bec010 .part RS_0x7f6a63a9f748, 3, 1; +L_0x1bec0b0 .part RS_0x7f6a63a9f748, 3, 1; +L_0x1bec6c0 .part/pv L_0x1bec580, 3, 1, 4; +L_0x1bec760 .part v0x1bd65b0_0, 2, 1; +L_0x1bec360 .part RS_0x7f6a63aa1008, 3, 1; +L_0x1bec450 .part RS_0x7f6a63aa1038, 3, 1; +L_0x1bec800 .part/pv L_0x1bec8a0, 3, 1, 4; +L_0x1becc20 .part RS_0x7f6a63aa1098, 2, 1; +L_0x1beca30 .part RS_0x7f6a63aa1068, 3, 1; +L_0x1bfae50 .part/pv L_0x1bfac70, 0, 1, 4; +L_0x1beccc0 .part v0x1bd65b0_0, 0, 1; +L_0x1becdf0 .part v0x1bd65b0_0, 1, 1; +L_0x1bfaef0 .part RS_0x7f6a63aa0be8, 0, 1; +L_0x1bfaf90 .part RS_0x7f6a63aa0be8, 0, 1; +L_0x1bfb030 .part RS_0x7f6a63a9f748, 0, 1; +L_0x1bfb410 .part RS_0x7f6a63aa0be8, 0, 1; +L_0x1bfbc80 .part/pv L_0x1bfbaa0, 0, 1, 4; +L_0x1bfbd20 .part v0x1bd65b0_0, 0, 1; +L_0x1bfb500 .part v0x1bd65b0_0, 1, 1; +L_0x1bfb630 .part RS_0x7f6a63a9fe38, 0, 1; +L_0x1bfc0b0 .part RS_0x7f6a63a9fe38, 0, 1; +L_0x1bfc150 .part RS_0x7f6a63a9f748, 0, 1; +L_0x1bfbe50 .part RS_0x7f6a63a9f748, 0, 1; +L_0x1bfc720 .part/pv L_0x1bfc5e0, 0, 1, 4; +L_0x1bfc1f0 .part v0x1bd65b0_0, 2, 1; +L_0x1bfc290 .part RS_0x7f6a63aa1008, 0, 1; +L_0x1bfc380 .part RS_0x7f6a63aa1038, 0, 1; +L_0x1bfc9e0 .part/pv L_0x1be9d90, 0, 1, 4; +L_0x1bfca80 .part RS_0x7f6a63aa1068, 0, 1; +L_0x1bfcc60 .part RS_0x7f6a63aa1068, 0, 1; +L_0x1bfce00 .part RS_0x7f6a63aa1098, 3, 1; +S_0x1bc21e0 .scope module, "trial" "AddSubSLT32" 3 279, 3 205, S_0x1b51ae0; + .timescale -9 -12; +P_0x1bc22d8 .param/l "size" 3 228, +C4<0100>; +L_0x1bf1de0/d .functor OR 1, L_0x1bf20a0, C4<0>, C4<0>, C4<0>; +L_0x1bf1de0 .delay (20000,20000,20000) L_0x1bf1de0/d; +L_0x1bf2250/d .functor XOR 1, RS_0x7f6a63aa0ee8, L_0x1bf2340, C4<0>, C4<0>; +L_0x1bf2250 .delay (40000,40000,40000) L_0x1bf2250/d; +L_0x1bf1fd0/d .functor AND 1, L_0x1bf2510, L_0x1bf25b0, C4<1>, C4<1>; +L_0x1bf1fd0 .delay (20000,20000,20000) L_0x1bf1fd0/d; +L_0x1bf23e0/d .functor NOT 1, RS_0x7f6a63aa0f78, C4<0>, C4<0>, C4<0>; +L_0x1bf23e0 .delay (10000,10000,10000) L_0x1bf23e0/d; +L_0x1bf28a0/d .functor NOT 1, L_0x1bf2900, C4<0>, C4<0>, C4<0>; +L_0x1bf28a0 .delay (10000,10000,10000) L_0x1bf28a0/d; +L_0x1bf29a0/d .functor AND 1, L_0x1bf23e0, L_0x1bf2ae0, C4<1>, C4<1>; +L_0x1bf29a0 .delay (20000,20000,20000) L_0x1bf29a0/d; +L_0x1bf26a0/d .functor AND 1, RS_0x7f6a63aa0f78, L_0x1bf28a0, C4<1>, C4<1>; +L_0x1bf26a0 .delay (20000,20000,20000) L_0x1bf26a0/d; +L_0x1bf2cd0/d .functor AND 1, L_0x1bf29a0, L_0x1bf1fd0, C4<1>, C4<1>; +L_0x1bf2cd0 .delay (20000,20000,20000) L_0x1bf2cd0/d; +L_0x1bf2e10/d .functor AND 1, L_0x1bf26a0, L_0x1bf1fd0, C4<1>, C4<1>; +L_0x1bf2e10 .delay (20000,20000,20000) L_0x1bf2e10/d; +L_0x1bf2f30/d .functor OR 1, L_0x1bf2cd0, L_0x1bf2e10, C4<0>, C4<0>; +L_0x1bf2f30 .delay (20000,20000,20000) L_0x1bf2f30/d; +v0x1bc68b0_0 .alias "A", 3 0, v0x1bd5250_0; +v0x1bc6950_0 .alias "AddSubSLTSum", 3 0, v0x1bd63b0_0; +v0x1bc69f0_0 .alias "B", 3 0, v0x1bd5370_0; +RS_0x7f6a63aa0c18 .resolv tri, L_0x1bedd50, L_0x1bef170, L_0x1bf0570, L_0x1bf1b50; +v0x1bc6ac0_0 .net8 "CarryoutWire", 3 0, RS_0x7f6a63aa0c18; 4 drivers +v0x1bc6b40_0 .alias "Command", 2 0, v0x1bd5470_0; +v0x1bc6bc0_0 .net "Res0OF1", 0 0, L_0x1bf26a0; 1 drivers +v0x1bc6c60_0 .net "Res1OF0", 0 0, L_0x1bf29a0; 1 drivers +v0x1bc6d00_0 .alias "SLTflag", 0 0, v0x1bd6730_0; +v0x1bc6df0_0 .net "SLTflag0", 0 0, L_0x1bf2cd0; 1 drivers +v0x1bc6e90_0 .net "SLTflag1", 0 0, L_0x1bf2e10; 1 drivers +v0x1bc6f30_0 .net "SLTon", 0 0, L_0x1bf1fd0; 1 drivers +v0x1bc6fd0_0 .net *"_s40", 0 0, L_0x1bf20a0; 1 drivers +v0x1bc7070_0 .net/s *"_s41", 0 0, C4<0>; 1 drivers +v0x1bc7110_0 .net *"_s44", 0 0, L_0x1bf2340; 1 drivers +v0x1bc7230_0 .net *"_s46", 0 0, L_0x1bf2510; 1 drivers +v0x1bc72d0_0 .net *"_s48", 0 0, L_0x1bf25b0; 1 drivers +v0x1bc7190_0 .net *"_s50", 0 0, L_0x1bf2900; 1 drivers +v0x1bc7420_0 .net *"_s52", 0 0, L_0x1bf2ae0; 1 drivers +v0x1bc7540_0 .alias "carryin", 3 0, v0x1bd5ea0_0; +v0x1bc75c0_0 .alias "carryout", 0 0, v0x1bd68b0_0; +v0x1bc74a0_0 .net "nAddSubSLTSum", 0 0, L_0x1bf28a0; 1 drivers +v0x1bc76f0_0 .net "nOF", 0 0, L_0x1bf23e0; 1 drivers +v0x1bc7640_0 .alias "overflow", 0 0, v0x1bd6930_0; +v0x1bc7830_0 .alias "subtract", 3 0, v0x1bd69b0_0; +L_0x1bedc60 .part/pv L_0x1bed7d0, 1, 1, 4; +L_0x1bedd50 .part/pv L_0x1bedb20, 1, 1, 4; +L_0x1bede40 .part/pv L_0x1bed500, 1, 1, 4; +L_0x1bedf30 .part v0x1bd6330_0, 1, 1; +L_0x1bedfd0 .part v0x1bd6530_0, 1, 1; +L_0x1bee100 .part RS_0x7f6a63aa0c18, 0, 1; +L_0x1bef080 .part/pv L_0x1beebf0, 2, 1, 4; +L_0x1bef170 .part/pv L_0x1beef40, 2, 1, 4; +L_0x1bef2b0 .part/pv L_0x1bee920, 2, 1, 4; +L_0x1bef3a0 .part v0x1bd6330_0, 2, 1; +L_0x1bef4a0 .part v0x1bd6530_0, 2, 1; +L_0x1bef5d0 .part RS_0x7f6a63aa0c18, 1, 1; +L_0x1bf0480 .part/pv L_0x1befff0, 3, 1, 4; +L_0x1bf0570 .part/pv L_0x1bf0340, 3, 1, 4; +L_0x1bf06e0 .part/pv L_0x1befd20, 3, 1, 4; +L_0x1bf07d0 .part v0x1bd6330_0, 3, 1; +L_0x1bf0900 .part v0x1bd6530_0, 3, 1; +L_0x1bf0a30 .part RS_0x7f6a63aa0c18, 2, 1; +L_0x1bf1a60 .part/pv L_0x1bf15b0, 0, 1, 4; +L_0x1bf1b50 .part/pv L_0x1bf1900, 0, 1, 4; +L_0x1bf0ad0 .part/pv L_0x1bf12e0, 0, 1, 4; +L_0x1bf1d40 .part v0x1bd6330_0, 0, 1; +L_0x1bf1c40 .part v0x1bd6530_0, 0, 1; +L_0x1bf1f30 .part RS_0x7f6a63aa0fa8, 0, 1; +L_0x1bf20a0 .part RS_0x7f6a63aa0c18, 3, 1; +L_0x1bf2340 .part RS_0x7f6a63aa0c18, 2, 1; +L_0x1bf2510 .part v0x1bd65b0_0, 1, 1; +L_0x1bf25b0 .part RS_0x7f6a63aa0fa8, 0, 1; +L_0x1bf2900 .part RS_0x7f6a63aa0be8, 3, 1; +L_0x1bf2ae0 .part RS_0x7f6a63aa0be8, 3, 1; +S_0x1bc58a0 .scope module, "attempt2" "MiddleAddSubSLT" 3 225, 3 89, S_0x1bc21e0; + .timescale -9 -12; +L_0x1bf0870/d .functor NOT 1, L_0x1bf1c40, C4<0>, C4<0>, C4<0>; +L_0x1bf0870 .delay (10000,10000,10000) L_0x1bf0870/d; +L_0x1bf1180/d .functor NOT 1, L_0x1bf1240, C4<0>, C4<0>, C4<0>; +L_0x1bf1180 .delay (10000,10000,10000) L_0x1bf1180/d; +L_0x1bf12e0/d .functor AND 1, L_0x1bf1420, L_0x1bf1180, C4<1>, C4<1>; +L_0x1bf12e0 .delay (20000,20000,20000) L_0x1bf12e0/d; +L_0x1bf14c0/d .functor XOR 1, L_0x1bf1d40, L_0x1bf0f10, C4<0>, C4<0>; +L_0x1bf14c0 .delay (40000,40000,40000) L_0x1bf14c0/d; +L_0x1bf15b0/d .functor XOR 1, L_0x1bf14c0, L_0x1bf1f30, C4<0>, C4<0>; +L_0x1bf15b0 .delay (40000,40000,40000) L_0x1bf15b0/d; +L_0x1bf16a0/d .functor AND 1, L_0x1bf1d40, L_0x1bf0f10, C4<1>, C4<1>; +L_0x1bf16a0 .delay (20000,20000,20000) L_0x1bf16a0/d; +L_0x1bf1810/d .functor AND 1, L_0x1bf14c0, L_0x1bf1f30, C4<1>, C4<1>; +L_0x1bf1810 .delay (20000,20000,20000) L_0x1bf1810/d; +L_0x1bf1900/d .functor OR 1, L_0x1bf16a0, L_0x1bf1810, C4<0>, C4<0>; +L_0x1bf1900 .delay (20000,20000,20000) L_0x1bf1900/d; +v0x1bc5f10_0 .net "A", 0 0, L_0x1bf1d40; 1 drivers +v0x1bc5fd0_0 .net "AandB", 0 0, L_0x1bf16a0; 1 drivers +v0x1bc6070_0 .net "AddSubSLTSum", 0 0, L_0x1bf15b0; 1 drivers +v0x1bc6110_0 .net "AxorB", 0 0, L_0x1bf14c0; 1 drivers +v0x1bc6190_0 .net "B", 0 0, L_0x1bf1c40; 1 drivers +v0x1bc6240_0 .net "BornB", 0 0, L_0x1bf0f10; 1 drivers +v0x1bc6300_0 .net "CINandAxorB", 0 0, L_0x1bf1810; 1 drivers +v0x1bc6380_0 .alias "Command", 2 0, v0x1bd5470_0; +v0x1bc6400_0 .net *"_s3", 0 0, L_0x1bf1240; 1 drivers +v0x1bc6480_0 .net *"_s5", 0 0, L_0x1bf1420; 1 drivers +v0x1bc6520_0 .net "carryin", 0 0, L_0x1bf1f30; 1 drivers +v0x1bc65c0_0 .net "carryout", 0 0, L_0x1bf1900; 1 drivers +v0x1bc6660_0 .net "nB", 0 0, L_0x1bf0870; 1 drivers +v0x1bc6710_0 .net "nCmd2", 0 0, L_0x1bf1180; 1 drivers +v0x1bc6810_0 .net "subtract", 0 0, L_0x1bf12e0; 1 drivers +L_0x1bf10e0 .part v0x1bd65b0_0, 0, 1; +L_0x1bf1240 .part v0x1bd65b0_0, 2, 1; +L_0x1bf1420 .part v0x1bd65b0_0, 0, 1; +S_0x1bc5990 .scope module, "mux0" "TwoInMux" 3 105, 3 8, S_0x1bc58a0; + .timescale -9 -12; +L_0x1bf0c30/d .functor NOT 1, L_0x1bf10e0, C4<0>, C4<0>, C4<0>; +L_0x1bf0c30 .delay (10000,10000,10000) L_0x1bf0c30/d; +L_0x1bf0cf0/d .functor AND 1, L_0x1bf1c40, L_0x1bf0c30, C4<1>, C4<1>; +L_0x1bf0cf0 .delay (20000,20000,20000) L_0x1bf0cf0/d; +L_0x1bf0e00/d .functor AND 1, L_0x1bf0870, L_0x1bf10e0, C4<1>, C4<1>; +L_0x1bf0e00 .delay (20000,20000,20000) L_0x1bf0e00/d; +L_0x1bf0f10/d .functor OR 1, L_0x1bf0cf0, L_0x1bf0e00, C4<0>, C4<0>; +L_0x1bf0f10 .delay (20000,20000,20000) L_0x1bf0f10/d; +v0x1bc5a80_0 .net "S", 0 0, L_0x1bf10e0; 1 drivers +v0x1bc5b40_0 .alias "in0", 0 0, v0x1bc6190_0; +v0x1bc5be0_0 .alias "in1", 0 0, v0x1bc6660_0; +v0x1bc5c80_0 .net "nS", 0 0, L_0x1bf0c30; 1 drivers +v0x1bc5d30_0 .net "out0", 0 0, L_0x1bf0cf0; 1 drivers +v0x1bc5dd0_0 .net "out1", 0 0, L_0x1bf0e00; 1 drivers +v0x1bc5e70_0 .alias "outfinal", 0 0, v0x1bc6240_0; +S_0x1bc4700 .scope generate, "addbits[1]" "addbits[1]" 3 230, 3 230, S_0x1bc21e0; + .timescale -9 -12; +P_0x1bc4118 .param/l "i" 3 230, +C4<01>; +S_0x1bc4870 .scope module, "attempt" "MiddleAddSubSLT" 3 232, 3 89, S_0x1bc4700; + .timescale -9 -12; +L_0x1becb20/d .functor NOT 1, L_0x1bedfd0, C4<0>, C4<0>, C4<0>; +L_0x1becb20 .delay (10000,10000,10000) L_0x1becb20/d; +L_0x1bed3c0/d .functor NOT 1, L_0x1bed460, C4<0>, C4<0>, C4<0>; +L_0x1bed3c0 .delay (10000,10000,10000) L_0x1bed3c0/d; +L_0x1bed500/d .functor AND 1, L_0x1bed640, L_0x1bed3c0, C4<1>, C4<1>; +L_0x1bed500 .delay (20000,20000,20000) L_0x1bed500/d; +L_0x1bed6e0/d .functor XOR 1, L_0x1bedf30, L_0x1bed190, C4<0>, C4<0>; +L_0x1bed6e0 .delay (40000,40000,40000) L_0x1bed6e0/d; +L_0x1bed7d0/d .functor XOR 1, L_0x1bed6e0, L_0x1bee100, C4<0>, C4<0>; +L_0x1bed7d0 .delay (40000,40000,40000) L_0x1bed7d0/d; +L_0x1bed8c0/d .functor AND 1, L_0x1bedf30, L_0x1bed190, C4<1>, C4<1>; +L_0x1bed8c0 .delay (20000,20000,20000) L_0x1bed8c0/d; +L_0x1beda30/d .functor AND 1, L_0x1bed6e0, L_0x1bee100, C4<1>, C4<1>; +L_0x1beda30 .delay (20000,20000,20000) L_0x1beda30/d; +L_0x1bedb20/d .functor OR 1, L_0x1bed8c0, L_0x1beda30, C4<0>, C4<0>; +L_0x1bedb20 .delay (20000,20000,20000) L_0x1bedb20/d; +v0x1bc4f00_0 .net "A", 0 0, L_0x1bedf30; 1 drivers +v0x1bc4fc0_0 .net "AandB", 0 0, L_0x1bed8c0; 1 drivers +v0x1bc5060_0 .net "AddSubSLTSum", 0 0, L_0x1bed7d0; 1 drivers +v0x1bc5100_0 .net "AxorB", 0 0, L_0x1bed6e0; 1 drivers +v0x1bc5180_0 .net "B", 0 0, L_0x1bedfd0; 1 drivers +v0x1bc5230_0 .net "BornB", 0 0, L_0x1bed190; 1 drivers +v0x1bc52f0_0 .net "CINandAxorB", 0 0, L_0x1beda30; 1 drivers +v0x1bc5370_0 .alias "Command", 2 0, v0x1bd5470_0; +v0x1bc53f0_0 .net *"_s3", 0 0, L_0x1bed460; 1 drivers +v0x1bc5470_0 .net *"_s5", 0 0, L_0x1bed640; 1 drivers +v0x1bc5510_0 .net "carryin", 0 0, L_0x1bee100; 1 drivers +v0x1bc55b0_0 .net "carryout", 0 0, L_0x1bedb20; 1 drivers +v0x1bc5650_0 .net "nB", 0 0, L_0x1becb20; 1 drivers +v0x1bc5700_0 .net "nCmd2", 0 0, L_0x1bed3c0; 1 drivers +v0x1bc5800_0 .net "subtract", 0 0, L_0x1bed500; 1 drivers +L_0x1bed320 .part v0x1bd65b0_0, 0, 1; +L_0x1bed460 .part v0x1bd65b0_0, 2, 1; +L_0x1bed640 .part v0x1bd65b0_0, 0, 1; +S_0x1bc4960 .scope module, "mux0" "TwoInMux" 3 105, 3 8, S_0x1bc4870; + .timescale -9 -12; +L_0x1becf10/d .functor NOT 1, L_0x1bed320, C4<0>, C4<0>, C4<0>; +L_0x1becf10 .delay (10000,10000,10000) L_0x1becf10/d; +L_0x1becfb0/d .functor AND 1, L_0x1bedfd0, L_0x1becf10, C4<1>, C4<1>; +L_0x1becfb0 .delay (20000,20000,20000) L_0x1becfb0/d; +L_0x1bed0a0/d .functor AND 1, L_0x1becb20, L_0x1bed320, C4<1>, C4<1>; +L_0x1bed0a0 .delay (20000,20000,20000) L_0x1bed0a0/d; +L_0x1bed190/d .functor OR 1, L_0x1becfb0, L_0x1bed0a0, C4<0>, C4<0>; +L_0x1bed190 .delay (20000,20000,20000) L_0x1bed190/d; +v0x1bc4a50_0 .net "S", 0 0, L_0x1bed320; 1 drivers +v0x1bc4af0_0 .alias "in0", 0 0, v0x1bc5180_0; +v0x1bc4b90_0 .alias "in1", 0 0, v0x1bc5650_0; +v0x1bc4c30_0 .net "nS", 0 0, L_0x1becf10; 1 drivers +v0x1bc4ce0_0 .net "out0", 0 0, L_0x1becfb0; 1 drivers +v0x1bc4d80_0 .net "out1", 0 0, L_0x1bed0a0; 1 drivers +v0x1bc4e60_0 .alias "outfinal", 0 0, v0x1bc5230_0; +S_0x1bc3560 .scope generate, "addbits[2]" "addbits[2]" 3 230, 3 230, S_0x1bc21e0; + .timescale -9 -12; +P_0x1bc2ee8 .param/l "i" 3 230, +C4<010>; +S_0x1bc36d0 .scope module, "attempt" "MiddleAddSubSLT" 3 232, 3 89, S_0x1bc3560; + .timescale -9 -12; +L_0x1bee1a0/d .functor NOT 1, L_0x1bef4a0, C4<0>, C4<0>, C4<0>; +L_0x1bee1a0 .delay (10000,10000,10000) L_0x1bee1a0/d; +L_0x1bee7e0/d .functor NOT 1, L_0x1bee880, C4<0>, C4<0>, C4<0>; +L_0x1bee7e0 .delay (10000,10000,10000) L_0x1bee7e0/d; +L_0x1bee920/d .functor AND 1, L_0x1beea60, L_0x1bee7e0, C4<1>, C4<1>; +L_0x1bee920 .delay (20000,20000,20000) L_0x1bee920/d; +L_0x1beeb00/d .functor XOR 1, L_0x1bef3a0, L_0x1bee5b0, C4<0>, C4<0>; +L_0x1beeb00 .delay (40000,40000,40000) L_0x1beeb00/d; +L_0x1beebf0/d .functor XOR 1, L_0x1beeb00, L_0x1bef5d0, C4<0>, C4<0>; +L_0x1beebf0 .delay (40000,40000,40000) L_0x1beebf0/d; +L_0x1beece0/d .functor AND 1, L_0x1bef3a0, L_0x1bee5b0, C4<1>, C4<1>; +L_0x1beece0 .delay (20000,20000,20000) L_0x1beece0/d; +L_0x1beee50/d .functor AND 1, L_0x1beeb00, L_0x1bef5d0, C4<1>, C4<1>; +L_0x1beee50 .delay (20000,20000,20000) L_0x1beee50/d; +L_0x1beef40/d .functor OR 1, L_0x1beece0, L_0x1beee50, C4<0>, C4<0>; +L_0x1beef40 .delay (20000,20000,20000) L_0x1beef40/d; +v0x1bc3d60_0 .net "A", 0 0, L_0x1bef3a0; 1 drivers +v0x1bc3e20_0 .net "AandB", 0 0, L_0x1beece0; 1 drivers +v0x1bc3ec0_0 .net "AddSubSLTSum", 0 0, L_0x1beebf0; 1 drivers +v0x1bc3f60_0 .net "AxorB", 0 0, L_0x1beeb00; 1 drivers +v0x1bc3fe0_0 .net "B", 0 0, L_0x1bef4a0; 1 drivers +v0x1bc4090_0 .net "BornB", 0 0, L_0x1bee5b0; 1 drivers +v0x1bc4150_0 .net "CINandAxorB", 0 0, L_0x1beee50; 1 drivers +v0x1bc41d0_0 .alias "Command", 2 0, v0x1bd5470_0; +v0x1bc4250_0 .net *"_s3", 0 0, L_0x1bee880; 1 drivers +v0x1bc42d0_0 .net *"_s5", 0 0, L_0x1beea60; 1 drivers +v0x1bc4370_0 .net "carryin", 0 0, L_0x1bef5d0; 1 drivers +v0x1bc4410_0 .net "carryout", 0 0, L_0x1beef40; 1 drivers +v0x1bc44b0_0 .net "nB", 0 0, L_0x1bee1a0; 1 drivers +v0x1bc4560_0 .net "nCmd2", 0 0, L_0x1bee7e0; 1 drivers +v0x1bc4660_0 .net "subtract", 0 0, L_0x1bee920; 1 drivers +L_0x1bee740 .part v0x1bd65b0_0, 0, 1; +L_0x1bee880 .part v0x1bd65b0_0, 2, 1; +L_0x1beea60 .part v0x1bd65b0_0, 0, 1; +S_0x1bc37c0 .scope module, "mux0" "TwoInMux" 3 105, 3 8, S_0x1bc36d0; + .timescale -9 -12; +L_0x1bee330/d .functor NOT 1, L_0x1bee740, C4<0>, C4<0>, C4<0>; +L_0x1bee330 .delay (10000,10000,10000) L_0x1bee330/d; +L_0x1bee3d0/d .functor AND 1, L_0x1bef4a0, L_0x1bee330, C4<1>, C4<1>; +L_0x1bee3d0 .delay (20000,20000,20000) L_0x1bee3d0/d; +L_0x1bee4c0/d .functor AND 1, L_0x1bee1a0, L_0x1bee740, C4<1>, C4<1>; +L_0x1bee4c0 .delay (20000,20000,20000) L_0x1bee4c0/d; +L_0x1bee5b0/d .functor OR 1, L_0x1bee3d0, L_0x1bee4c0, C4<0>, C4<0>; +L_0x1bee5b0 .delay (20000,20000,20000) L_0x1bee5b0/d; +v0x1bc38b0_0 .net "S", 0 0, L_0x1bee740; 1 drivers +v0x1bc3950_0 .alias "in0", 0 0, v0x1bc3fe0_0; +v0x1bc39f0_0 .alias "in1", 0 0, v0x1bc44b0_0; +v0x1bc3a90_0 .net "nS", 0 0, L_0x1bee330; 1 drivers +v0x1bc3b40_0 .net "out0", 0 0, L_0x1bee3d0; 1 drivers +v0x1bc3be0_0 .net "out1", 0 0, L_0x1bee4c0; 1 drivers +v0x1bc3cc0_0 .alias "outfinal", 0 0, v0x1bc4090_0; +S_0x1bc2350 .scope generate, "addbits[3]" "addbits[3]" 3 230, 3 230, S_0x1bc21e0; + .timescale -9 -12; +P_0x1bc2448 .param/l "i" 3 230, +C4<011>; +S_0x1bc24c0 .scope module, "attempt" "MiddleAddSubSLT" 3 232, 3 89, S_0x1bc2350; + .timescale -9 -12; +L_0x1bef440/d .functor NOT 1, L_0x1bf0900, C4<0>, C4<0>, C4<0>; +L_0x1bef440 .delay (10000,10000,10000) L_0x1bef440/d; +L_0x1befbe0/d .functor NOT 1, L_0x1befc80, C4<0>, C4<0>, C4<0>; +L_0x1befbe0 .delay (10000,10000,10000) L_0x1befbe0/d; +L_0x1befd20/d .functor AND 1, L_0x1befe60, L_0x1befbe0, C4<1>, C4<1>; +L_0x1befd20 .delay (20000,20000,20000) L_0x1befd20/d; +L_0x1beff00/d .functor XOR 1, L_0x1bf07d0, L_0x1bef9b0, C4<0>, C4<0>; +L_0x1beff00 .delay (40000,40000,40000) L_0x1beff00/d; +L_0x1befff0/d .functor XOR 1, L_0x1beff00, L_0x1bf0a30, C4<0>, C4<0>; +L_0x1befff0 .delay (40000,40000,40000) L_0x1befff0/d; +L_0x1bf00e0/d .functor AND 1, L_0x1bf07d0, L_0x1bef9b0, C4<1>, C4<1>; +L_0x1bf00e0 .delay (20000,20000,20000) L_0x1bf00e0/d; +L_0x1bf0250/d .functor AND 1, L_0x1beff00, L_0x1bf0a30, C4<1>, C4<1>; +L_0x1bf0250 .delay (20000,20000,20000) L_0x1bf0250/d; +L_0x1bf0340/d .functor OR 1, L_0x1bf00e0, L_0x1bf0250, C4<0>, C4<0>; +L_0x1bf0340 .delay (20000,20000,20000) L_0x1bf0340/d; +v0x1bc2b30_0 .net "A", 0 0, L_0x1bf07d0; 1 drivers +v0x1bc2bf0_0 .net "AandB", 0 0, L_0x1bf00e0; 1 drivers +v0x1bc2c90_0 .net "AddSubSLTSum", 0 0, L_0x1befff0; 1 drivers +v0x1bc2d30_0 .net "AxorB", 0 0, L_0x1beff00; 1 drivers +v0x1bc2db0_0 .net "B", 0 0, L_0x1bf0900; 1 drivers +v0x1bc2e60_0 .net "BornB", 0 0, L_0x1bef9b0; 1 drivers +v0x1bc2f20_0 .net "CINandAxorB", 0 0, L_0x1bf0250; 1 drivers +v0x1bc2fa0_0 .alias "Command", 2 0, v0x1bd5470_0; +v0x1bc3020_0 .net *"_s3", 0 0, L_0x1befc80; 1 drivers +v0x1bc30a0_0 .net *"_s5", 0 0, L_0x1befe60; 1 drivers +v0x1bc3180_0 .net "carryin", 0 0, L_0x1bf0a30; 1 drivers +v0x1bc3200_0 .net "carryout", 0 0, L_0x1bf0340; 1 drivers +v0x1bc3310_0 .net "nB", 0 0, L_0x1bef440; 1 drivers +v0x1bc33c0_0 .net "nCmd2", 0 0, L_0x1befbe0; 1 drivers +v0x1bc34c0_0 .net "subtract", 0 0, L_0x1befd20; 1 drivers +L_0x1befb40 .part v0x1bd65b0_0, 0, 1; +L_0x1befc80 .part v0x1bd65b0_0, 2, 1; +L_0x1befe60 .part v0x1bd65b0_0, 0, 1; +S_0x1bc25b0 .scope module, "mux0" "TwoInMux" 3 105, 3 8, S_0x1bc24c0; + .timescale -9 -12; +L_0x1bef770/d .functor NOT 1, L_0x1befb40, C4<0>, C4<0>, C4<0>; +L_0x1bef770 .delay (10000,10000,10000) L_0x1bef770/d; +L_0x1bef7d0/d .functor AND 1, L_0x1bf0900, L_0x1bef770, C4<1>, C4<1>; +L_0x1bef7d0 .delay (20000,20000,20000) L_0x1bef7d0/d; +L_0x1bef8c0/d .functor AND 1, L_0x1bef440, L_0x1befb40, C4<1>, C4<1>; +L_0x1bef8c0 .delay (20000,20000,20000) L_0x1bef8c0/d; +L_0x1bef9b0/d .functor OR 1, L_0x1bef7d0, L_0x1bef8c0, C4<0>, C4<0>; +L_0x1bef9b0 .delay (20000,20000,20000) L_0x1bef9b0/d; +v0x1bc26a0_0 .net "S", 0 0, L_0x1befb40; 1 drivers +v0x1bc2720_0 .alias "in0", 0 0, v0x1bc2db0_0; +v0x1bc27c0_0 .alias "in1", 0 0, v0x1bc3310_0; +v0x1bc2860_0 .net "nS", 0 0, L_0x1bef770; 1 drivers +v0x1bc2910_0 .net "out0", 0 0, L_0x1bef7d0; 1 drivers +v0x1bc29b0_0 .net "out1", 0 0, L_0x1bef8c0; 1 drivers +v0x1bc2a90_0 .alias "outfinal", 0 0, v0x1bc2e60_0; +S_0x1bbefa0 .scope module, "trial1" "AndNand32" 3 280, 3 154, S_0x1b51ae0; + .timescale -9 -12; +P_0x1bbea28 .param/l "size" 3 161, +C4<0100>; +v0x1bbee90_0 .alias "A", 3 0, v0x1bd5250_0; +v0x1bc2000_0 .alias "AndNandOut", 3 0, v0x1bd64b0_0; +v0x1bc2080_0 .alias "B", 3 0, v0x1bd5370_0; +v0x1bc2130_0 .alias "Command", 2 0, v0x1bd5470_0; +L_0x1bf3890 .part/pv L_0x1bf3620, 1, 1, 4; +L_0x1bf3950 .part v0x1bd6330_0, 1, 1; +L_0x1bf39f0 .part v0x1bd6530_0, 1, 1; +L_0x1bf4300 .part/pv L_0x1bf4090, 2, 1, 4; +L_0x1bf43a0 .part v0x1bd6330_0, 2, 1; +L_0x1bf4440 .part v0x1bd6530_0, 2, 1; +L_0x1bf4d70 .part/pv L_0x1bf4b00, 3, 1, 4; +L_0x1be6650 .part v0x1bd6330_0, 3, 1; +L_0x1bf5020 .part v0x1bd6530_0, 3, 1; +L_0x1bf58d0 .part/pv L_0x1bf5660, 0, 1, 4; +L_0x1bf59d0 .part v0x1bd6330_0, 0, 1; +L_0x1bf5a70 .part v0x1bd6530_0, 0, 1; +S_0x1bc14c0 .scope module, "attempt2" "AndNand" 3 165, 3 48, S_0x1bbefa0; + .timescale -9 -12; +L_0x1bf5110/d .functor NAND 1, L_0x1bf59d0, L_0x1bf5a70, C4<1>, C4<1>; +L_0x1bf5110 .delay (10000,10000,10000) L_0x1bf5110/d; +L_0x1bf5210/d .functor NOT 1, L_0x1bf5110, C4<0>, C4<0>, C4<0>; +L_0x1bf5210 .delay (10000,10000,10000) L_0x1bf5210/d; +v0x1bc1ae0_0 .net "A", 0 0, L_0x1bf59d0; 1 drivers +v0x1bc1ba0_0 .net "AandB", 0 0, L_0x1bf5210; 1 drivers +v0x1bc1c20_0 .net "AnandB", 0 0, L_0x1bf5110; 1 drivers +v0x1bc1cd0_0 .net "AndNandOut", 0 0, L_0x1bf5660; 1 drivers +v0x1bc1db0_0 .net "B", 0 0, L_0x1bf5a70; 1 drivers +v0x1bc1e30_0 .alias "Command", 2 0, v0x1bd5470_0; +L_0x1bf5830 .part v0x1bd65b0_0, 0, 1; +S_0x1bc15b0 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0x1bc14c0; + .timescale -9 -12; +L_0x1bf5340/d .functor NOT 1, L_0x1bf5830, C4<0>, C4<0>, C4<0>; +L_0x1bf5340 .delay (10000,10000,10000) L_0x1bf5340/d; +L_0x1bf5400/d .functor AND 1, L_0x1bf5210, L_0x1bf5340, C4<1>, C4<1>; +L_0x1bf5400 .delay (20000,20000,20000) L_0x1bf5400/d; +L_0x1bf5510/d .functor AND 1, L_0x1bf5110, L_0x1bf5830, C4<1>, C4<1>; +L_0x1bf5510 .delay (20000,20000,20000) L_0x1bf5510/d; +L_0x1bf5660/d .functor OR 1, L_0x1bf5400, L_0x1bf5510, C4<0>, C4<0>; +L_0x1bf5660 .delay (20000,20000,20000) L_0x1bf5660/d; +v0x1bc16a0_0 .net "S", 0 0, L_0x1bf5830; 1 drivers +v0x1bc1720_0 .alias "in0", 0 0, v0x1bc1ba0_0; +v0x1bc17a0_0 .alias "in1", 0 0, v0x1bc1c20_0; +v0x1bc1840_0 .net "nS", 0 0, L_0x1bf5340; 1 drivers +v0x1bc18c0_0 .net "out0", 0 0, L_0x1bf5400; 1 drivers +v0x1bc1960_0 .net "out1", 0 0, L_0x1bf5510; 1 drivers +v0x1bc1a40_0 .alias "outfinal", 0 0, v0x1bc1cd0_0; +S_0x1bc0900 .scope generate, "andbits[1]" "andbits[1]" 3 169, 3 169, S_0x1bbefa0; + .timescale -9 -12; +P_0x1bc09f8 .param/l "i" 3 169, +C4<01>; +S_0x1bc0a70 .scope module, "attempt" "AndNand" 3 171, 3 48, S_0x1bc0900; + .timescale -9 -12; +L_0x1bf3110/d .functor NAND 1, L_0x1bf3950, L_0x1bf39f0, C4<1>, C4<1>; +L_0x1bf3110 .delay (10000,10000,10000) L_0x1bf3110/d; +L_0x1bf31d0/d .functor NOT 1, L_0x1bf3110, C4<0>, C4<0>, C4<0>; +L_0x1bf31d0 .delay (10000,10000,10000) L_0x1bf31d0/d; +v0x1bc10b0_0 .net "A", 0 0, L_0x1bf3950; 1 drivers +v0x1bc1170_0 .net "AandB", 0 0, L_0x1bf31d0; 1 drivers +v0x1bc11f0_0 .net "AnandB", 0 0, L_0x1bf3110; 1 drivers +v0x1bc12a0_0 .net "AndNandOut", 0 0, L_0x1bf3620; 1 drivers +v0x1bc1380_0 .net "B", 0 0, L_0x1bf39f0; 1 drivers +v0x1bc1400_0 .alias "Command", 2 0, v0x1bd5470_0; +L_0x1bf37f0 .part v0x1bd65b0_0, 0, 1; +S_0x1bc0b60 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0x1bc0a70; + .timescale -9 -12; +L_0x1bf3300/d .functor NOT 1, L_0x1bf37f0, C4<0>, C4<0>, C4<0>; +L_0x1bf3300 .delay (10000,10000,10000) L_0x1bf3300/d; +L_0x1bf33c0/d .functor AND 1, L_0x1bf31d0, L_0x1bf3300, C4<1>, C4<1>; +L_0x1bf33c0 .delay (20000,20000,20000) L_0x1bf33c0/d; +L_0x1bf34d0/d .functor AND 1, L_0x1bf3110, L_0x1bf37f0, C4<1>, C4<1>; +L_0x1bf34d0 .delay (20000,20000,20000) L_0x1bf34d0/d; +L_0x1bf3620/d .functor OR 1, L_0x1bf33c0, L_0x1bf34d0, C4<0>, C4<0>; +L_0x1bf3620 .delay (20000,20000,20000) L_0x1bf3620/d; +v0x1bc0c50_0 .net "S", 0 0, L_0x1bf37f0; 1 drivers +v0x1bc0cd0_0 .alias "in0", 0 0, v0x1bc1170_0; +v0x1bc0d70_0 .alias "in1", 0 0, v0x1bc11f0_0; +v0x1bc0e10_0 .net "nS", 0 0, L_0x1bf3300; 1 drivers +v0x1bc0e90_0 .net "out0", 0 0, L_0x1bf33c0; 1 drivers +v0x1bc0f30_0 .net "out1", 0 0, L_0x1bf34d0; 1 drivers +v0x1bc1010_0 .alias "outfinal", 0 0, v0x1bc12a0_0; +S_0x1bbfd40 .scope generate, "andbits[2]" "andbits[2]" 3 169, 3 169, S_0x1bbefa0; + .timescale -9 -12; +P_0x1bbfe38 .param/l "i" 3 169, +C4<010>; +S_0x1bbfeb0 .scope module, "attempt" "AndNand" 3 171, 3 48, S_0x1bbfd40; + .timescale -9 -12; +L_0x1bf3ae0/d .functor NAND 1, L_0x1bf43a0, L_0x1bf4440, C4<1>, C4<1>; +L_0x1bf3ae0 .delay (10000,10000,10000) L_0x1bf3ae0/d; +L_0x1bf3c40/d .functor NOT 1, L_0x1bf3ae0, C4<0>, C4<0>, C4<0>; +L_0x1bf3c40 .delay (10000,10000,10000) L_0x1bf3c40/d; +v0x1bc04f0_0 .net "A", 0 0, L_0x1bf43a0; 1 drivers +v0x1bc05b0_0 .net "AandB", 0 0, L_0x1bf3c40; 1 drivers +v0x1bc0630_0 .net "AnandB", 0 0, L_0x1bf3ae0; 1 drivers +v0x1bc06e0_0 .net "AndNandOut", 0 0, L_0x1bf4090; 1 drivers +v0x1bc07c0_0 .net "B", 0 0, L_0x1bf4440; 1 drivers +v0x1bc0840_0 .alias "Command", 2 0, v0x1bd5470_0; +L_0x1bf4260 .part v0x1bd65b0_0, 0, 1; +S_0x1bbffa0 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0x1bbfeb0; + .timescale -9 -12; +L_0x1bf3d70/d .functor NOT 1, L_0x1bf4260, C4<0>, C4<0>, C4<0>; +L_0x1bf3d70 .delay (10000,10000,10000) L_0x1bf3d70/d; +L_0x1bf3e30/d .functor AND 1, L_0x1bf3c40, L_0x1bf3d70, C4<1>, C4<1>; +L_0x1bf3e30 .delay (20000,20000,20000) L_0x1bf3e30/d; +L_0x1bf3f40/d .functor AND 1, L_0x1bf3ae0, L_0x1bf4260, C4<1>, C4<1>; +L_0x1bf3f40 .delay (20000,20000,20000) L_0x1bf3f40/d; +L_0x1bf4090/d .functor OR 1, L_0x1bf3e30, L_0x1bf3f40, C4<0>, C4<0>; +L_0x1bf4090 .delay (20000,20000,20000) L_0x1bf4090/d; +v0x1bc0090_0 .net "S", 0 0, L_0x1bf4260; 1 drivers +v0x1bc0110_0 .alias "in0", 0 0, v0x1bc05b0_0; +v0x1bc01b0_0 .alias "in1", 0 0, v0x1bc0630_0; +v0x1bc0250_0 .net "nS", 0 0, L_0x1bf3d70; 1 drivers +v0x1bc02d0_0 .net "out0", 0 0, L_0x1bf3e30; 1 drivers +v0x1bc0370_0 .net "out1", 0 0, L_0x1bf3f40; 1 drivers +v0x1bc0450_0 .alias "outfinal", 0 0, v0x1bc06e0_0; +S_0x1bbf110 .scope generate, "andbits[3]" "andbits[3]" 3 169, 3 169, S_0x1bbefa0; + .timescale -9 -12; +P_0x1bbf208 .param/l "i" 3 169, +C4<011>; +S_0x1bbf2a0 .scope module, "attempt" "AndNand" 3 171, 3 48, S_0x1bbf110; + .timescale -9 -12; +L_0x1bf4570/d .functor NAND 1, L_0x1be6650, L_0x1bf5020, C4<1>, C4<1>; +L_0x1bf4570 .delay (10000,10000,10000) L_0x1bf4570/d; +L_0x1bf46b0/d .functor NOT 1, L_0x1bf4570, C4<0>, C4<0>, C4<0>; +L_0x1bf46b0 .delay (10000,10000,10000) L_0x1bf46b0/d; +v0x1bbf930_0 .net "A", 0 0, L_0x1be6650; 1 drivers +v0x1bbf9f0_0 .net "AandB", 0 0, L_0x1bf46b0; 1 drivers +v0x1bbfa70_0 .net "AnandB", 0 0, L_0x1bf4570; 1 drivers +v0x1bbfb20_0 .net "AndNandOut", 0 0, L_0x1bf4b00; 1 drivers +v0x1bbfc00_0 .net "B", 0 0, L_0x1bf5020; 1 drivers +v0x1bbfc80_0 .alias "Command", 2 0, v0x1bd5470_0; +L_0x1bf4cd0 .part v0x1bd65b0_0, 0, 1; +S_0x1bbf390 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0x1bbf2a0; + .timescale -9 -12; +L_0x1bf47e0/d .functor NOT 1, L_0x1bf4cd0, C4<0>, C4<0>, C4<0>; +L_0x1bf47e0 .delay (10000,10000,10000) L_0x1bf47e0/d; +L_0x1bf48a0/d .functor AND 1, L_0x1bf46b0, L_0x1bf47e0, C4<1>, C4<1>; +L_0x1bf48a0 .delay (20000,20000,20000) L_0x1bf48a0/d; +L_0x1bf49b0/d .functor AND 1, L_0x1bf4570, L_0x1bf4cd0, C4<1>, C4<1>; +L_0x1bf49b0 .delay (20000,20000,20000) L_0x1bf49b0/d; +L_0x1bf4b00/d .functor OR 1, L_0x1bf48a0, L_0x1bf49b0, C4<0>, C4<0>; +L_0x1bf4b00 .delay (20000,20000,20000) L_0x1bf4b00/d; +v0x1bbf480_0 .net "S", 0 0, L_0x1bf4cd0; 1 drivers +v0x1bbf520_0 .alias "in0", 0 0, v0x1bbf9f0_0; +v0x1bbf5c0_0 .alias "in1", 0 0, v0x1bbfa70_0; +v0x1bbf660_0 .net "nS", 0 0, L_0x1bf47e0; 1 drivers +v0x1bbf710_0 .net "out0", 0 0, L_0x1bf48a0; 1 drivers +v0x1bbf7b0_0 .net "out1", 0 0, L_0x1bf49b0; 1 drivers +v0x1bbf890_0 .alias "outfinal", 0 0, v0x1bbfb20_0; +S_0x1bb9d80 .scope module, "trial2" "OrNorXor32" 3 281, 3 177, S_0x1b51ae0; + .timescale -9 -12; +P_0x1bb8ed8 .param/l "size" 3 184, +C4<0100>; +v0x1bbed10_0 .alias "A", 3 0, v0x1bd5250_0; +v0x1bbed90_0 .alias "B", 3 0, v0x1bd5370_0; +v0x1bbee10_0 .alias "Command", 2 0, v0x1bd5470_0; +v0x1bbef20_0 .alias "OrNorXorOut", 3 0, v0x1bd66b0_0; +L_0x1bf6c20 .part/pv L_0x1bf69b0, 1, 1, 4; +L_0x1bf6cc0 .part v0x1bd6330_0, 1, 1; +L_0x1bf6d60 .part v0x1bd6530_0, 1, 1; +L_0x1bf7f20 .part/pv L_0x1bf7cb0, 2, 1, 4; +L_0x1bf7fc0 .part v0x1bd6330_0, 2, 1; +L_0x1bf8060 .part v0x1bd6530_0, 2, 1; +L_0x1bf9220 .part/pv L_0x1bf8fb0, 3, 1, 4; +L_0x1bf92c0 .part v0x1bd6330_0, 3, 1; +L_0x1bf9360 .part v0x1bd6530_0, 3, 1; +L_0x1bfa510 .part/pv L_0x1bfa2a0, 0, 1, 4; +L_0x1bfa610 .part v0x1bd6330_0, 0, 1; +L_0x1bfa6b0 .part v0x1bd6530_0, 0, 1; +S_0x1bbdb00 .scope module, "attempt2" "OrNorXor" 3 192, 3 64, S_0x1bb9d80; + .timescale -9 -12; +L_0x1bf9400/d .functor NOR 1, L_0x1bfa610, L_0x1bfa6b0, C4<0>, C4<0>; +L_0x1bf9400 .delay (10000,10000,10000) L_0x1bf9400/d; +L_0x1bf9500/d .functor NOT 1, L_0x1bf9400, C4<0>, C4<0>, C4<0>; +L_0x1bf9500 .delay (10000,10000,10000) L_0x1bf9500/d; +L_0x1bf9630/d .functor NAND 1, L_0x1bfa610, L_0x1bfa6b0, C4<1>, C4<1>; +L_0x1bf9630 .delay (10000,10000,10000) L_0x1bf9630/d; +L_0x1bf9790/d .functor NAND 1, L_0x1bf9630, L_0x1bf9500, C4<1>, C4<1>; +L_0x1bf9790 .delay (10000,10000,10000) L_0x1bf9790/d; +L_0x1bf98a0/d .functor NOT 1, L_0x1bf9790, C4<0>, C4<0>, C4<0>; +L_0x1bf98a0 .delay (10000,10000,10000) L_0x1bf98a0/d; +v0x1bbe650_0 .net "A", 0 0, L_0x1bfa610; 1 drivers +v0x1bbe6f0_0 .net "AnandB", 0 0, L_0x1bf9630; 1 drivers +v0x1bbe790_0 .net "AnorB", 0 0, L_0x1bf9400; 1 drivers +v0x1bbe810_0 .net "AorB", 0 0, L_0x1bf9500; 1 drivers +v0x1bbe8f0_0 .net "AxorB", 0 0, L_0x1bf98a0; 1 drivers +v0x1bbe9a0_0 .net "B", 0 0, L_0x1bfa6b0; 1 drivers +v0x1bbea60_0 .alias "Command", 2 0, v0x1bd5470_0; +v0x1bbeae0_0 .net "OrNorXorOut", 0 0, L_0x1bfa2a0; 1 drivers +v0x1bbeb60_0 .net "XorNor", 0 0, L_0x1bf9d20; 1 drivers +v0x1bbec30_0 .net "nXor", 0 0, L_0x1bf9790; 1 drivers +L_0x1bf9ea0 .part v0x1bd65b0_0, 2, 1; +L_0x1bfa470 .part v0x1bd65b0_0, 0, 1; +S_0x1bbe0e0 .scope module, "mux0" "TwoInMux" 3 83, 3 8, S_0x1bbdb00; + .timescale -9 -12; +L_0x1bf9a00/d .functor NOT 1, L_0x1bf9ea0, C4<0>, C4<0>, C4<0>; +L_0x1bf9a00 .delay (10000,10000,10000) L_0x1bf9a00/d; +L_0x1bf9ac0/d .functor AND 1, L_0x1bf98a0, L_0x1bf9a00, C4<1>, C4<1>; +L_0x1bf9ac0 .delay (20000,20000,20000) L_0x1bf9ac0/d; +L_0x1bf9bd0/d .functor AND 1, L_0x1bf9400, L_0x1bf9ea0, C4<1>, C4<1>; +L_0x1bf9bd0 .delay (20000,20000,20000) L_0x1bf9bd0/d; +L_0x1bf9d20/d .functor OR 1, L_0x1bf9ac0, L_0x1bf9bd0, C4<0>, C4<0>; +L_0x1bf9d20 .delay (20000,20000,20000) L_0x1bf9d20/d; +v0x1bbe1d0_0 .net "S", 0 0, L_0x1bf9ea0; 1 drivers +v0x1bbe290_0 .alias "in0", 0 0, v0x1bbe8f0_0; +v0x1bbe330_0 .alias "in1", 0 0, v0x1bbe790_0; +v0x1bbe3d0_0 .net "nS", 0 0, L_0x1bf9a00; 1 drivers +v0x1bbe450_0 .net "out0", 0 0, L_0x1bf9ac0; 1 drivers +v0x1bbe4f0_0 .net "out1", 0 0, L_0x1bf9bd0; 1 drivers +v0x1bbe5d0_0 .alias "outfinal", 0 0, v0x1bbeb60_0; +S_0x1bbdbf0 .scope module, "mux1" "TwoInMux" 3 84, 3 8, S_0x1bbdb00; + .timescale -9 -12; +L_0x1bf9f40/d .functor NOT 1, L_0x1bfa470, C4<0>, C4<0>, C4<0>; +L_0x1bf9f40 .delay (10000,10000,10000) L_0x1bf9f40/d; +L_0x1bfa000/d .functor AND 1, L_0x1bf9d20, L_0x1bf9f40, C4<1>, C4<1>; +L_0x1bfa000 .delay (20000,20000,20000) L_0x1bfa000/d; +L_0x1bfa150/d .functor AND 1, L_0x1bf9500, L_0x1bfa470, C4<1>, C4<1>; +L_0x1bfa150 .delay (20000,20000,20000) L_0x1bfa150/d; +L_0x1bfa2a0/d .functor OR 1, L_0x1bfa000, L_0x1bfa150, C4<0>, C4<0>; +L_0x1bfa2a0 .delay (20000,20000,20000) L_0x1bfa2a0/d; +v0x1bbdce0_0 .net "S", 0 0, L_0x1bfa470; 1 drivers +v0x1bbdd60_0 .alias "in0", 0 0, v0x1bbeb60_0; +v0x1bbdde0_0 .alias "in1", 0 0, v0x1bbe810_0; +v0x1bbde80_0 .net "nS", 0 0, L_0x1bf9f40; 1 drivers +v0x1bbdf00_0 .net "out0", 0 0, L_0x1bfa000; 1 drivers +v0x1bbdfa0_0 .net "out1", 0 0, L_0x1bfa150; 1 drivers +v0x1bbe040_0 .alias "outfinal", 0 0, v0x1bbeae0_0; +S_0x1bbc700 .scope generate, "orbits[1]" "orbits[1]" 3 196, 3 196, S_0x1bb9d80; + .timescale -9 -12; +P_0x1bbc3e8 .param/l "i" 3 196, +C4<01>; +S_0x1bbc830 .scope module, "attempt" "OrNorXor" 3 198, 3 64, S_0x1bbc700; + .timescale -9 -12; +L_0x1bf5970/d .functor NOR 1, L_0x1bf6cc0, L_0x1bf6d60, C4<0>, C4<0>; +L_0x1bf5970 .delay (10000,10000,10000) L_0x1bf5970/d; +L_0x1bf5c10/d .functor NOT 1, L_0x1bf5970, C4<0>, C4<0>, C4<0>; +L_0x1bf5c10 .delay (10000,10000,10000) L_0x1bf5c10/d; +L_0x1bf5d40/d .functor NAND 1, L_0x1bf6cc0, L_0x1bf6d60, C4<1>, C4<1>; +L_0x1bf5d40 .delay (10000,10000,10000) L_0x1bf5d40/d; +L_0x1bf5ea0/d .functor NAND 1, L_0x1bf5d40, L_0x1bf5c10, C4<1>, C4<1>; +L_0x1bf5ea0 .delay (10000,10000,10000) L_0x1bf5ea0/d; +L_0x1bf5fb0/d .functor NOT 1, L_0x1bf5ea0, C4<0>, C4<0>, C4<0>; +L_0x1bf5fb0 .delay (10000,10000,10000) L_0x1bf5fb0/d; +v0x1bbd3c0_0 .net "A", 0 0, L_0x1bf6cc0; 1 drivers +v0x1bbd460_0 .net "AnandB", 0 0, L_0x1bf5d40; 1 drivers +v0x1bbd500_0 .net "AnorB", 0 0, L_0x1bf5970; 1 drivers +v0x1bbd5b0_0 .net "AorB", 0 0, L_0x1bf5c10; 1 drivers +v0x1bbd690_0 .net "AxorB", 0 0, L_0x1bf5fb0; 1 drivers +v0x1bbd740_0 .net "B", 0 0, L_0x1bf6d60; 1 drivers +v0x1bbd800_0 .alias "Command", 2 0, v0x1bd5470_0; +v0x1bbd880_0 .net "OrNorXorOut", 0 0, L_0x1bf69b0; 1 drivers +v0x1bbd950_0 .net "XorNor", 0 0, L_0x1bf6430; 1 drivers +v0x1bbda20_0 .net "nXor", 0 0, L_0x1bf5ea0; 1 drivers +L_0x1bf65b0 .part v0x1bd65b0_0, 2, 1; +L_0x1bf6b80 .part v0x1bd65b0_0, 0, 1; +S_0x1bbce50 .scope module, "mux0" "TwoInMux" 3 83, 3 8, S_0x1bbc830; + .timescale -9 -12; +L_0x1bf6110/d .functor NOT 1, L_0x1bf65b0, C4<0>, C4<0>, C4<0>; +L_0x1bf6110 .delay (10000,10000,10000) L_0x1bf6110/d; +L_0x1bf61d0/d .functor AND 1, L_0x1bf5fb0, L_0x1bf6110, C4<1>, C4<1>; +L_0x1bf61d0 .delay (20000,20000,20000) L_0x1bf61d0/d; +L_0x1bf62e0/d .functor AND 1, L_0x1bf5970, L_0x1bf65b0, C4<1>, C4<1>; +L_0x1bf62e0 .delay (20000,20000,20000) L_0x1bf62e0/d; +L_0x1bf6430/d .functor OR 1, L_0x1bf61d0, L_0x1bf62e0, C4<0>, C4<0>; +L_0x1bf6430 .delay (20000,20000,20000) L_0x1bf6430/d; +v0x1bbcf40_0 .net "S", 0 0, L_0x1bf65b0; 1 drivers +v0x1bbd000_0 .alias "in0", 0 0, v0x1bbd690_0; +v0x1bbd0a0_0 .alias "in1", 0 0, v0x1bbd500_0; +v0x1bbd140_0 .net "nS", 0 0, L_0x1bf6110; 1 drivers +v0x1bbd1c0_0 .net "out0", 0 0, L_0x1bf61d0; 1 drivers +v0x1bbd260_0 .net "out1", 0 0, L_0x1bf62e0; 1 drivers +v0x1bbd340_0 .alias "outfinal", 0 0, v0x1bbd950_0; +S_0x1bbc920 .scope module, "mux1" "TwoInMux" 3 84, 3 8, S_0x1bbc830; + .timescale -9 -12; +L_0x1bf6650/d .functor NOT 1, L_0x1bf6b80, C4<0>, C4<0>, C4<0>; +L_0x1bf6650 .delay (10000,10000,10000) L_0x1bf6650/d; +L_0x1bf6710/d .functor AND 1, L_0x1bf6430, L_0x1bf6650, C4<1>, C4<1>; +L_0x1bf6710 .delay (20000,20000,20000) L_0x1bf6710/d; +L_0x1bf6860/d .functor AND 1, L_0x1bf5c10, L_0x1bf6b80, C4<1>, C4<1>; +L_0x1bf6860 .delay (20000,20000,20000) L_0x1bf6860/d; +L_0x1bf69b0/d .functor OR 1, L_0x1bf6710, L_0x1bf6860, C4<0>, C4<0>; +L_0x1bf69b0 .delay (20000,20000,20000) L_0x1bf69b0/d; +v0x1bbca10_0 .net "S", 0 0, L_0x1bf6b80; 1 drivers +v0x1bbca90_0 .alias "in0", 0 0, v0x1bbd950_0; +v0x1bbcb10_0 .alias "in1", 0 0, v0x1bbd5b0_0; +v0x1bbcbb0_0 .net "nS", 0 0, L_0x1bf6650; 1 drivers +v0x1bbcc30_0 .net "out0", 0 0, L_0x1bf6710; 1 drivers +v0x1bbccd0_0 .net "out1", 0 0, L_0x1bf6860; 1 drivers +v0x1bbcdb0_0 .alias "outfinal", 0 0, v0x1bbd880_0; +S_0x1bbb2e0 .scope generate, "orbits[2]" "orbits[2]" 3 196, 3 196, S_0x1bb9d80; + .timescale -9 -12; +P_0x1bbb058 .param/l "i" 3 196, +C4<010>; +S_0x1bbb410 .scope module, "attempt" "OrNorXor" 3 198, 3 64, S_0x1bbb2e0; + .timescale -9 -12; +L_0x1bf6e00/d .functor NOR 1, L_0x1bf7fc0, L_0x1bf8060, C4<0>, C4<0>; +L_0x1bf6e00 .delay (10000,10000,10000) L_0x1bf6e00/d; +L_0x1bf6f10/d .functor NOT 1, L_0x1bf6e00, C4<0>, C4<0>, C4<0>; +L_0x1bf6f10 .delay (10000,10000,10000) L_0x1bf6f10/d; +L_0x1bf7040/d .functor NAND 1, L_0x1bf7fc0, L_0x1bf8060, C4<1>, C4<1>; +L_0x1bf7040 .delay (10000,10000,10000) L_0x1bf7040/d; +L_0x1bf71a0/d .functor NAND 1, L_0x1bf7040, L_0x1bf6f10, C4<1>, C4<1>; +L_0x1bf71a0 .delay (10000,10000,10000) L_0x1bf71a0/d; +L_0x1bf72b0/d .functor NOT 1, L_0x1bf71a0, C4<0>, C4<0>, C4<0>; +L_0x1bf72b0 .delay (10000,10000,10000) L_0x1bf72b0/d; +v0x1bbbfe0_0 .net "A", 0 0, L_0x1bf7fc0; 1 drivers +v0x1bbc080_0 .net "AnandB", 0 0, L_0x1bf7040; 1 drivers +v0x1bbc120_0 .net "AnorB", 0 0, L_0x1bf6e00; 1 drivers +v0x1bbc1d0_0 .net "AorB", 0 0, L_0x1bf6f10; 1 drivers +v0x1bbc2b0_0 .net "AxorB", 0 0, L_0x1bf72b0; 1 drivers +v0x1bbc360_0 .net "B", 0 0, L_0x1bf8060; 1 drivers +v0x1bbc420_0 .alias "Command", 2 0, v0x1bd5470_0; +v0x1bbc4a0_0 .net "OrNorXorOut", 0 0, L_0x1bf7cb0; 1 drivers +v0x1bbc550_0 .net "XorNor", 0 0, L_0x1bf7730; 1 drivers +v0x1bbc620_0 .net "nXor", 0 0, L_0x1bf71a0; 1 drivers +L_0x1bf78b0 .part v0x1bd65b0_0, 2, 1; +L_0x1bf7e80 .part v0x1bd65b0_0, 0, 1; +S_0x1bbba70 .scope module, "mux0" "TwoInMux" 3 83, 3 8, S_0x1bbb410; + .timescale -9 -12; +L_0x1bf7410/d .functor NOT 1, L_0x1bf78b0, C4<0>, C4<0>, C4<0>; +L_0x1bf7410 .delay (10000,10000,10000) L_0x1bf7410/d; +L_0x1bf74d0/d .functor AND 1, L_0x1bf72b0, L_0x1bf7410, C4<1>, C4<1>; +L_0x1bf74d0 .delay (20000,20000,20000) L_0x1bf74d0/d; +L_0x1bf75e0/d .functor AND 1, L_0x1bf6e00, L_0x1bf78b0, C4<1>, C4<1>; +L_0x1bf75e0 .delay (20000,20000,20000) L_0x1bf75e0/d; +L_0x1bf7730/d .functor OR 1, L_0x1bf74d0, L_0x1bf75e0, C4<0>, C4<0>; +L_0x1bf7730 .delay (20000,20000,20000) L_0x1bf7730/d; +v0x1bbbb60_0 .net "S", 0 0, L_0x1bf78b0; 1 drivers +v0x1bbbc20_0 .alias "in0", 0 0, v0x1bbc2b0_0; +v0x1bbbcc0_0 .alias "in1", 0 0, v0x1bbc120_0; +v0x1bbbd60_0 .net "nS", 0 0, L_0x1bf7410; 1 drivers +v0x1bbbde0_0 .net "out0", 0 0, L_0x1bf74d0; 1 drivers +v0x1bbbe80_0 .net "out1", 0 0, L_0x1bf75e0; 1 drivers +v0x1bbbf60_0 .alias "outfinal", 0 0, v0x1bbc550_0; +S_0x1bbb500 .scope module, "mux1" "TwoInMux" 3 84, 3 8, S_0x1bbb410; + .timescale -9 -12; +L_0x1bf7950/d .functor NOT 1, L_0x1bf7e80, C4<0>, C4<0>, C4<0>; +L_0x1bf7950 .delay (10000,10000,10000) L_0x1bf7950/d; +L_0x1bf7a10/d .functor AND 1, L_0x1bf7730, L_0x1bf7950, C4<1>, C4<1>; +L_0x1bf7a10 .delay (20000,20000,20000) L_0x1bf7a10/d; +L_0x1bf7b60/d .functor AND 1, L_0x1bf6f10, L_0x1bf7e80, C4<1>, C4<1>; +L_0x1bf7b60 .delay (20000,20000,20000) L_0x1bf7b60/d; +L_0x1bf7cb0/d .functor OR 1, L_0x1bf7a10, L_0x1bf7b60, C4<0>, C4<0>; +L_0x1bf7cb0 .delay (20000,20000,20000) L_0x1bf7cb0/d; +v0x1bbb5f0_0 .net "S", 0 0, L_0x1bf7e80; 1 drivers +v0x1bbb690_0 .alias "in0", 0 0, v0x1bbc550_0; +v0x1bbb730_0 .alias "in1", 0 0, v0x1bbc1d0_0; +v0x1bbb7d0_0 .net "nS", 0 0, L_0x1bf7950; 1 drivers +v0x1bbb850_0 .net "out0", 0 0, L_0x1bf7a10; 1 drivers +v0x1bbb8f0_0 .net "out1", 0 0, L_0x1bf7b60; 1 drivers +v0x1bbb9d0_0 .alias "outfinal", 0 0, v0x1bbc4a0_0; +S_0x1bb9ef0 .scope generate, "orbits[3]" "orbits[3]" 3 196, 3 196, S_0x1bb9d80; + .timescale -9 -12; +P_0x1bb9fe8 .param/l "i" 3 196, +C4<011>; +S_0x1bba080 .scope module, "attempt" "OrNorXor" 3 198, 3 64, S_0x1bb9ef0; + .timescale -9 -12; +L_0x1bf8140/d .functor NOR 1, L_0x1bf92c0, L_0x1bf9360, C4<0>, C4<0>; +L_0x1bf8140 .delay (10000,10000,10000) L_0x1bf8140/d; +L_0x1bf8230/d .functor NOT 1, L_0x1bf8140, C4<0>, C4<0>, C4<0>; +L_0x1bf8230 .delay (10000,10000,10000) L_0x1bf8230/d; +L_0x1bf8340/d .functor NAND 1, L_0x1bf92c0, L_0x1bf9360, C4<1>, C4<1>; +L_0x1bf8340 .delay (10000,10000,10000) L_0x1bf8340/d; +L_0x1bf84a0/d .functor NAND 1, L_0x1bf8340, L_0x1bf8230, C4<1>, C4<1>; +L_0x1bf84a0 .delay (10000,10000,10000) L_0x1bf84a0/d; +L_0x1bf85b0/d .functor NOT 1, L_0x1bf84a0, C4<0>, C4<0>, C4<0>; +L_0x1bf85b0 .delay (10000,10000,10000) L_0x1bf85b0/d; +v0x1bbac50_0 .net "A", 0 0, L_0x1bf92c0; 1 drivers +v0x1bbacf0_0 .net "AnandB", 0 0, L_0x1bf8340; 1 drivers +v0x1bbad90_0 .net "AnorB", 0 0, L_0x1bf8140; 1 drivers +v0x1bbae40_0 .net "AorB", 0 0, L_0x1bf8230; 1 drivers +v0x1bbaf20_0 .net "AxorB", 0 0, L_0x1bf85b0; 1 drivers +v0x1bbafd0_0 .net "B", 0 0, L_0x1bf9360; 1 drivers +v0x1bbb090_0 .alias "Command", 2 0, v0x1bd5470_0; +v0x1bbb110_0 .net "OrNorXorOut", 0 0, L_0x1bf8fb0; 1 drivers +v0x1bbb190_0 .net "XorNor", 0 0, L_0x1bf8a30; 1 drivers +v0x1bbb260_0 .net "nXor", 0 0, L_0x1bf84a0; 1 drivers +L_0x1bf8bb0 .part v0x1bd65b0_0, 2, 1; +L_0x1bf9180 .part v0x1bd65b0_0, 0, 1; +S_0x1bba6e0 .scope module, "mux0" "TwoInMux" 3 83, 3 8, S_0x1bba080; + .timescale -9 -12; +L_0x1bf8710/d .functor NOT 1, L_0x1bf8bb0, C4<0>, C4<0>, C4<0>; +L_0x1bf8710 .delay (10000,10000,10000) L_0x1bf8710/d; +L_0x1bf87d0/d .functor AND 1, L_0x1bf85b0, L_0x1bf8710, C4<1>, C4<1>; +L_0x1bf87d0 .delay (20000,20000,20000) L_0x1bf87d0/d; +L_0x1bf88e0/d .functor AND 1, L_0x1bf8140, L_0x1bf8bb0, C4<1>, C4<1>; +L_0x1bf88e0 .delay (20000,20000,20000) L_0x1bf88e0/d; +L_0x1bf8a30/d .functor OR 1, L_0x1bf87d0, L_0x1bf88e0, C4<0>, C4<0>; +L_0x1bf8a30 .delay (20000,20000,20000) L_0x1bf8a30/d; +v0x1bba7d0_0 .net "S", 0 0, L_0x1bf8bb0; 1 drivers +v0x1bba890_0 .alias "in0", 0 0, v0x1bbaf20_0; +v0x1bba930_0 .alias "in1", 0 0, v0x1bbad90_0; +v0x1bba9d0_0 .net "nS", 0 0, L_0x1bf8710; 1 drivers +v0x1bbaa50_0 .net "out0", 0 0, L_0x1bf87d0; 1 drivers +v0x1bbaaf0_0 .net "out1", 0 0, L_0x1bf88e0; 1 drivers +v0x1bbabd0_0 .alias "outfinal", 0 0, v0x1bbb190_0; +S_0x1bba170 .scope module, "mux1" "TwoInMux" 3 84, 3 8, S_0x1bba080; + .timescale -9 -12; +L_0x1bf8c50/d .functor NOT 1, L_0x1bf9180, C4<0>, C4<0>, C4<0>; +L_0x1bf8c50 .delay (10000,10000,10000) L_0x1bf8c50/d; +L_0x1bf8d10/d .functor AND 1, L_0x1bf8a30, L_0x1bf8c50, C4<1>, C4<1>; +L_0x1bf8d10 .delay (20000,20000,20000) L_0x1bf8d10/d; +L_0x1bf8e60/d .functor AND 1, L_0x1bf8230, L_0x1bf9180, C4<1>, C4<1>; +L_0x1bf8e60 .delay (20000,20000,20000) L_0x1bf8e60/d; +L_0x1bf8fb0/d .functor OR 1, L_0x1bf8d10, L_0x1bf8e60, C4<0>, C4<0>; +L_0x1bf8fb0 .delay (20000,20000,20000) L_0x1bf8fb0/d; +v0x1bba260_0 .net "S", 0 0, L_0x1bf9180; 1 drivers +v0x1bba300_0 .alias "in0", 0 0, v0x1bbb190_0; +v0x1bba3a0_0 .alias "in1", 0 0, v0x1bbae40_0; +v0x1bba440_0 .net "nS", 0 0, L_0x1bf8c50; 1 drivers +v0x1bba4c0_0 .net "out0", 0 0, L_0x1bf8d10; 1 drivers +v0x1bba560_0 .net "out1", 0 0, L_0x1bf8e60; 1 drivers +v0x1bba640_0 .alias "outfinal", 0 0, v0x1bbb110_0; +S_0x1bb9400 .scope module, "ZeroMux0case" "FourInMux" 3 283, 3 24, S_0x1b51ae0; + .timescale -9 -12; +L_0x1bfa5b0/d .functor NOT 1, L_0x1beccc0, C4<0>, C4<0>, C4<0>; +L_0x1bfa5b0 .delay (10000,10000,10000) L_0x1bfa5b0/d; +L_0x1bfa800/d .functor NOT 1, L_0x1becdf0, C4<0>, C4<0>, C4<0>; +L_0x1bfa800 .delay (10000,10000,10000) L_0x1bfa800/d; +L_0x1bfa8c0/d .functor NAND 1, L_0x1bfa5b0, L_0x1bfa800, L_0x1bfaef0, C4<1>; +L_0x1bfa8c0 .delay (10000,10000,10000) L_0x1bfa8c0/d; +L_0x1bfa9b0/d .functor NAND 1, L_0x1beccc0, L_0x1bfa800, L_0x1bfaf90, C4<1>; +L_0x1bfa9b0 .delay (10000,10000,10000) L_0x1bfa9b0/d; +L_0x1bfaaa0/d .functor NAND 1, L_0x1bfa5b0, L_0x1becdf0, L_0x1bfb030, C4<1>; +L_0x1bfaaa0 .delay (10000,10000,10000) L_0x1bfaaa0/d; +L_0x1bfab90/d .functor NAND 1, L_0x1beccc0, L_0x1becdf0, L_0x1bfb410, C4<1>; +L_0x1bfab90 .delay (10000,10000,10000) L_0x1bfab90/d; +L_0x1bfac70/d .functor NAND 1, L_0x1bfa8c0, L_0x1bfa9b0, L_0x1bfaaa0, L_0x1bfab90; +L_0x1bfac70 .delay (10000,10000,10000) L_0x1bfac70/d; +v0x1bb94f0_0 .net "S0", 0 0, L_0x1beccc0; 1 drivers +v0x1bb95b0_0 .net "S1", 0 0, L_0x1becdf0; 1 drivers +v0x1bb9650_0 .net "in0", 0 0, L_0x1bfaef0; 1 drivers +v0x1bb96f0_0 .net "in1", 0 0, L_0x1bfaf90; 1 drivers +v0x1bb9770_0 .net "in2", 0 0, L_0x1bfb030; 1 drivers +v0x1bb9810_0 .net "in3", 0 0, L_0x1bfb410; 1 drivers +v0x1bb98b0_0 .net "nS0", 0 0, L_0x1bfa5b0; 1 drivers +v0x1bb9950_0 .net "nS1", 0 0, L_0x1bfa800; 1 drivers +v0x1bb99f0_0 .net "out", 0 0, L_0x1bfac70; 1 drivers +v0x1bb9a90_0 .net "out0", 0 0, L_0x1bfa8c0; 1 drivers +v0x1bb9b30_0 .net "out1", 0 0, L_0x1bfa9b0; 1 drivers +v0x1bb9bd0_0 .net "out2", 0 0, L_0x1bfaaa0; 1 drivers +v0x1bb9ce0_0 .net "out3", 0 0, L_0x1bfab90; 1 drivers +S_0x1bb8a40 .scope module, "OneMux0case" "FourInMux" 3 284, 3 24, S_0x1b51ae0; + .timescale -9 -12; +L_0x1bfb190/d .functor NOT 1, L_0x1bfbd20, C4<0>, C4<0>, C4<0>; +L_0x1bfb190 .delay (10000,10000,10000) L_0x1bfb190/d; +L_0x1bfb280/d .functor NOT 1, L_0x1bfb500, C4<0>, C4<0>, C4<0>; +L_0x1bfb280 .delay (10000,10000,10000) L_0x1bfb280/d; +L_0x1bfb320/d .functor NAND 1, L_0x1bfb190, L_0x1bfb280, L_0x1bfb630, C4<1>; +L_0x1bfb320 .delay (10000,10000,10000) L_0x1bfb320/d; +L_0x1bfb7e0/d .functor NAND 1, L_0x1bfbd20, L_0x1bfb280, L_0x1bfc0b0, C4<1>; +L_0x1bfb7e0 .delay (10000,10000,10000) L_0x1bfb7e0/d; +L_0x1bfb8d0/d .functor NAND 1, L_0x1bfb190, L_0x1bfb500, L_0x1bfc150, C4<1>; +L_0x1bfb8d0 .delay (10000,10000,10000) L_0x1bfb8d0/d; +L_0x1bfb9c0/d .functor NAND 1, L_0x1bfbd20, L_0x1bfb500, L_0x1bfbe50, C4<1>; +L_0x1bfb9c0 .delay (10000,10000,10000) L_0x1bfb9c0/d; +L_0x1bfbaa0/d .functor NAND 1, L_0x1bfb320, L_0x1bfb7e0, L_0x1bfb8d0, L_0x1bfb9c0; +L_0x1bfbaa0 .delay (10000,10000,10000) L_0x1bfbaa0/d; +v0x1bb8b30_0 .net "S0", 0 0, L_0x1bfbd20; 1 drivers +v0x1bb8bf0_0 .net "S1", 0 0, L_0x1bfb500; 1 drivers +v0x1bb8c90_0 .net "in0", 0 0, L_0x1bfb630; 1 drivers +v0x1bb8d30_0 .net "in1", 0 0, L_0x1bfc0b0; 1 drivers +v0x1bb8db0_0 .net "in2", 0 0, L_0x1bfc150; 1 drivers +v0x1bb8e50_0 .net "in3", 0 0, L_0x1bfbe50; 1 drivers +v0x1bb8f30_0 .net "nS0", 0 0, L_0x1bfb190; 1 drivers +v0x1bb8fd0_0 .net "nS1", 0 0, L_0x1bfb280; 1 drivers +v0x1bb9070_0 .net "out", 0 0, L_0x1bfbaa0; 1 drivers +v0x1bb9110_0 .net "out0", 0 0, L_0x1bfb320; 1 drivers +v0x1bb91b0_0 .net "out1", 0 0, L_0x1bfb7e0; 1 drivers +v0x1bb9250_0 .net "out2", 0 0, L_0x1bfb8d0; 1 drivers +v0x1bb9360_0 .net "out3", 0 0, L_0x1bfb9c0; 1 drivers +S_0x1bb84f0 .scope module, "TwoMux0case" "TwoInMux" 3 285, 3 8, S_0x1b51ae0; + .timescale -9 -12; +L_0x1bfbf40/d .functor NOT 1, L_0x1bfc1f0, C4<0>, C4<0>, C4<0>; +L_0x1bfbf40 .delay (10000,10000,10000) L_0x1bfbf40/d; +L_0x1bfc030/d .functor AND 1, L_0x1bfc290, L_0x1bfbf40, C4<1>, C4<1>; +L_0x1bfc030 .delay (20000,20000,20000) L_0x1bfc030/d; +L_0x1bfc4f0/d .functor AND 1, L_0x1bfc380, L_0x1bfc1f0, C4<1>, C4<1>; +L_0x1bfc4f0 .delay (20000,20000,20000) L_0x1bfc4f0/d; +L_0x1bfc5e0/d .functor OR 1, L_0x1bfc030, L_0x1bfc4f0, C4<0>, C4<0>; +L_0x1bfc5e0 .delay (20000,20000,20000) L_0x1bfc5e0/d; +v0x1bb85e0_0 .net "S", 0 0, L_0x1bfc1f0; 1 drivers +v0x1bb86a0_0 .net "in0", 0 0, L_0x1bfc290; 1 drivers +v0x1bb8740_0 .net "in1", 0 0, L_0x1bfc380; 1 drivers +v0x1bb87e0_0 .net "nS", 0 0, L_0x1bfbf40; 1 drivers +v0x1bb8860_0 .net "out0", 0 0, L_0x1bfc030; 1 drivers +v0x1bb8900_0 .net "out1", 0 0, L_0x1bfc4f0; 1 drivers +v0x1bb89a0_0 .net "outfinal", 0 0, L_0x1bfc5e0; 1 drivers +S_0x1bb6970 .scope generate, "muxbits[1]" "muxbits[1]" 3 290, 3 290, S_0x1b51ae0; + .timescale -9 -12; +P_0x1bb5968 .param/l "i" 3 290, +C4<01>; +L_0x1be7250/d .functor OR 1, L_0x1be7350, L_0x1be7110, C4<0>, C4<0>; +L_0x1be7250 .delay (20000,20000,20000) L_0x1be7250/d; +v0x1bb8390_0 .net *"_s15", 0 0, L_0x1be7350; 1 drivers +v0x1bb8450_0 .net *"_s16", 0 0, L_0x1be7110; 1 drivers +S_0x1bb7a10 .scope module, "ZeroMux" "FourInMux" 3 292, 3 24, S_0x1bb6970; + .timescale -9 -12; +L_0x1be4980/d .functor NOT 1, L_0x1be5330, C4<0>, C4<0>, C4<0>; +L_0x1be4980 .delay (10000,10000,10000) L_0x1be4980/d; +L_0x1be4bd0/d .functor NOT 1, L_0x1be5460, C4<0>, C4<0>, C4<0>; +L_0x1be4bd0 .delay (10000,10000,10000) L_0x1be4bd0/d; +L_0x1be4c70/d .functor NAND 1, L_0x1be4980, L_0x1be4bd0, L_0x1be5590, C4<1>; +L_0x1be4c70 .delay (10000,10000,10000) L_0x1be4c70/d; +L_0x1be4d60/d .functor NAND 1, L_0x1be5330, L_0x1be4bd0, L_0x1be5630, C4<1>; +L_0x1be4d60 .delay (10000,10000,10000) L_0x1be4d60/d; +L_0x1be4e50/d .functor NAND 1, L_0x1be4980, L_0x1be5460, L_0x1be56d0, C4<1>; +L_0x1be4e50 .delay (10000,10000,10000) L_0x1be4e50/d; +L_0x1be4f40/d .functor NAND 1, L_0x1be5330, L_0x1be5460, L_0x1be58d0, C4<1>; +L_0x1be4f40 .delay (10000,10000,10000) L_0x1be4f40/d; +L_0x1be5080/d .functor NAND 1, L_0x1be4c70, L_0x1be4d60, L_0x1be4e50, L_0x1be4f40; +L_0x1be5080 .delay (10000,10000,10000) L_0x1be5080/d; +v0x1bb7b00_0 .net "S0", 0 0, L_0x1be5330; 1 drivers +v0x1bb7bc0_0 .net "S1", 0 0, L_0x1be5460; 1 drivers +v0x1bb7c60_0 .net "in0", 0 0, L_0x1be5590; 1 drivers +v0x1bb7d00_0 .net "in1", 0 0, L_0x1be5630; 1 drivers +v0x1bb7d80_0 .net "in2", 0 0, L_0x1be56d0; 1 drivers +v0x1bb7e20_0 .net "in3", 0 0, L_0x1be58d0; 1 drivers +v0x1bb7ec0_0 .net "nS0", 0 0, L_0x1be4980; 1 drivers +v0x1bb7f60_0 .net "nS1", 0 0, L_0x1be4bd0; 1 drivers +v0x1bb8000_0 .net "out", 0 0, L_0x1be5080; 1 drivers +v0x1bb80a0_0 .net "out0", 0 0, L_0x1be4c70; 1 drivers +v0x1bb8140_0 .net "out1", 0 0, L_0x1be4d60; 1 drivers +v0x1bb81e0_0 .net "out2", 0 0, L_0x1be4e50; 1 drivers +v0x1bb82f0_0 .net "out3", 0 0, L_0x1be4f40; 1 drivers +S_0x1bb7050 .scope module, "OneMux" "FourInMux" 3 293, 3 24, S_0x1bb6970; + .timescale -9 -12; +L_0x1be5970/d .functor NOT 1, L_0x1be62f0, C4<0>, C4<0>, C4<0>; +L_0x1be5970 .delay (10000,10000,10000) L_0x1be5970/d; +L_0x1be5a60/d .functor NOT 1, L_0x1be6420, C4<0>, C4<0>, C4<0>; +L_0x1be5a60 .delay (10000,10000,10000) L_0x1be5a60/d; +L_0x1be5b00/d .functor NAND 1, L_0x1be5970, L_0x1be5a60, L_0x1be65b0, C4<1>; +L_0x1be5b00 .delay (10000,10000,10000) L_0x1be5b00/d; +L_0x1be5c40/d .functor NAND 1, L_0x1be62f0, L_0x1be5a60, L_0x1be6760, C4<1>; +L_0x1be5c40 .delay (10000,10000,10000) L_0x1be5c40/d; +L_0x1be5d30/d .functor NAND 1, L_0x1be5970, L_0x1be6420, L_0x1be6800, C4<1>; +L_0x1be5d30 .delay (10000,10000,10000) L_0x1be5d30/d; +L_0x1be5e80/d .functor NAND 1, L_0x1be62f0, L_0x1be6420, L_0x1be68a0, C4<1>; +L_0x1be5e80 .delay (10000,10000,10000) L_0x1be5e80/d; +L_0x1be5ff0/d .functor NAND 1, L_0x1be5b00, L_0x1be5c40, L_0x1be5d30, L_0x1be5e80; +L_0x1be5ff0 .delay (10000,10000,10000) L_0x1be5ff0/d; +v0x1bb7140_0 .net "S0", 0 0, L_0x1be62f0; 1 drivers +v0x1bb7200_0 .net "S1", 0 0, L_0x1be6420; 1 drivers +v0x1bb72a0_0 .net "in0", 0 0, L_0x1be65b0; 1 drivers +v0x1bb7340_0 .net "in1", 0 0, L_0x1be6760; 1 drivers +v0x1bb73c0_0 .net "in2", 0 0, L_0x1be6800; 1 drivers +v0x1bb7460_0 .net "in3", 0 0, L_0x1be68a0; 1 drivers +v0x1bb7540_0 .net "nS0", 0 0, L_0x1be5970; 1 drivers +v0x1bb75e0_0 .net "nS1", 0 0, L_0x1be5a60; 1 drivers +v0x1bb7680_0 .net "out", 0 0, L_0x1be5ff0; 1 drivers +v0x1bb7720_0 .net "out0", 0 0, L_0x1be5b00; 1 drivers +v0x1bb77c0_0 .net "out1", 0 0, L_0x1be5c40; 1 drivers +v0x1bb7860_0 .net "out2", 0 0, L_0x1be5d30; 1 drivers +v0x1bb7970_0 .net "out3", 0 0, L_0x1be5e80; 1 drivers +S_0x1bb6ae0 .scope module, "TwoMux" "TwoInMux" 3 294, 3 8, S_0x1bb6970; + .timescale -9 -12; +L_0x1be6550/d .functor NOT 1, L_0x1be6df0, C4<0>, C4<0>, C4<0>; +L_0x1be6550 .delay (10000,10000,10000) L_0x1be6550/d; +L_0x1be69e0/d .functor AND 1, L_0x1be6e90, L_0x1be6550, C4<1>, C4<1>; +L_0x1be69e0 .delay (20000,20000,20000) L_0x1be69e0/d; +L_0x1be6ad0/d .functor AND 1, L_0x1be6fd0, L_0x1be6df0, C4<1>, C4<1>; +L_0x1be6ad0 .delay (20000,20000,20000) L_0x1be6ad0/d; +L_0x1be6bc0/d .functor OR 1, L_0x1be69e0, L_0x1be6ad0, C4<0>, C4<0>; +L_0x1be6bc0 .delay (20000,20000,20000) L_0x1be6bc0/d; +v0x1bb6bd0_0 .net "S", 0 0, L_0x1be6df0; 1 drivers +v0x1bb6c70_0 .net "in0", 0 0, L_0x1be6e90; 1 drivers +v0x1bb6d10_0 .net "in1", 0 0, L_0x1be6fd0; 1 drivers +v0x1bb6db0_0 .net "nS", 0 0, L_0x1be6550; 1 drivers +v0x1bb6e30_0 .net "out0", 0 0, L_0x1be69e0; 1 drivers +v0x1bb6ed0_0 .net "out1", 0 0, L_0x1be6ad0; 1 drivers +v0x1bb6fb0_0 .net "outfinal", 0 0, L_0x1be6bc0; 1 drivers +S_0x1bb4df0 .scope generate, "muxbits[2]" "muxbits[2]" 3 290, 3 290, S_0x1b51ae0; + .timescale -9 -12; +P_0x1bb3d38 .param/l "i" 3 290, +C4<010>; +L_0x1be9660/d .functor OR 1, L_0x1be9e60, L_0x1bea1e0, C4<0>, C4<0>; +L_0x1be9660 .delay (20000,20000,20000) L_0x1be9660/d; +v0x1bb6810_0 .net *"_s15", 0 0, L_0x1be9e60; 1 drivers +v0x1bb68d0_0 .net *"_s16", 0 0, L_0x1bea1e0; 1 drivers +S_0x1bb5e90 .scope module, "ZeroMux" "FourInMux" 3 292, 3 24, S_0x1bb4df0; + .timescale -9 -12; +L_0x1be74f0/d .functor NOT 1, L_0x1be73f0, C4<0>, C4<0>, C4<0>; +L_0x1be74f0 .delay (10000,10000,10000) L_0x1be74f0/d; +L_0x1be75e0/d .functor NOT 1, L_0x1be7ee0, C4<0>, C4<0>, C4<0>; +L_0x1be75e0 .delay (10000,10000,10000) L_0x1be75e0/d; +L_0x1be7680/d .functor NAND 1, L_0x1be74f0, L_0x1be75e0, L_0x1be7d90, C4<1>; +L_0x1be7680 .delay (10000,10000,10000) L_0x1be7680/d; +L_0x1be77c0/d .functor NAND 1, L_0x1be73f0, L_0x1be75e0, L_0x1be80e0, C4<1>; +L_0x1be77c0 .delay (10000,10000,10000) L_0x1be77c0/d; +L_0x1be78b0/d .functor NAND 1, L_0x1be74f0, L_0x1be7ee0, L_0x1be8010, C4<1>; +L_0x1be78b0 .delay (10000,10000,10000) L_0x1be78b0/d; +L_0x1be79a0/d .functor NAND 1, L_0x1be73f0, L_0x1be7ee0, L_0x1be82b0, C4<1>; +L_0x1be79a0 .delay (10000,10000,10000) L_0x1be79a0/d; +L_0x1be7ae0/d .functor NAND 1, L_0x1be7680, L_0x1be77c0, L_0x1be78b0, L_0x1be79a0; +L_0x1be7ae0 .delay (10000,10000,10000) L_0x1be7ae0/d; +v0x1bb5f80_0 .net "S0", 0 0, L_0x1be73f0; 1 drivers +v0x1bb6040_0 .net "S1", 0 0, L_0x1be7ee0; 1 drivers +v0x1bb60e0_0 .net "in0", 0 0, L_0x1be7d90; 1 drivers +v0x1bb6180_0 .net "in1", 0 0, L_0x1be80e0; 1 drivers +v0x1bb6200_0 .net "in2", 0 0, L_0x1be8010; 1 drivers +v0x1bb62a0_0 .net "in3", 0 0, L_0x1be82b0; 1 drivers +v0x1bb6340_0 .net "nS0", 0 0, L_0x1be74f0; 1 drivers +v0x1bb63e0_0 .net "nS1", 0 0, L_0x1be75e0; 1 drivers +v0x1bb6480_0 .net "out", 0 0, L_0x1be7ae0; 1 drivers +v0x1bb6520_0 .net "out0", 0 0, L_0x1be7680; 1 drivers +v0x1bb65c0_0 .net "out1", 0 0, L_0x1be77c0; 1 drivers +v0x1bb6660_0 .net "out2", 0 0, L_0x1be78b0; 1 drivers +v0x1bb6770_0 .net "out3", 0 0, L_0x1be79a0; 1 drivers +S_0x1bb54d0 .scope module, "OneMux" "FourInMux" 3 293, 3 24, S_0x1bb4df0; + .timescale -9 -12; +L_0x1be8180/d .functor NOT 1, L_0x1be8c80, C4<0>, C4<0>, C4<0>; +L_0x1be8180 .delay (10000,10000,10000) L_0x1be8180/d; +L_0x1be84e0/d .functor NOT 1, L_0x1be83a0, C4<0>, C4<0>, C4<0>; +L_0x1be84e0 .delay (10000,10000,10000) L_0x1be84e0/d; +L_0x1be8540/d .functor NAND 1, L_0x1be8180, L_0x1be84e0, L_0x1bd7280, C4<1>; +L_0x1be8540 .delay (10000,10000,10000) L_0x1be8540/d; +L_0x1be8680/d .functor NAND 1, L_0x1be8c80, L_0x1be84e0, L_0x1bd7430, C4<1>; +L_0x1be8680 .delay (10000,10000,10000) L_0x1be8680/d; +L_0x1be8770/d .functor NAND 1, L_0x1be8180, L_0x1be83a0, L_0x1bd70f0, C4<1>; +L_0x1be8770 .delay (10000,10000,10000) L_0x1be8770/d; +L_0x1be8860/d .functor NAND 1, L_0x1be8c80, L_0x1be83a0, L_0x1bd7320, C4<1>; +L_0x1be8860 .delay (10000,10000,10000) L_0x1be8860/d; +L_0x1be89d0/d .functor NAND 1, L_0x1be8540, L_0x1be8680, L_0x1be8770, L_0x1be8860; +L_0x1be89d0 .delay (10000,10000,10000) L_0x1be89d0/d; +v0x1bb55c0_0 .net "S0", 0 0, L_0x1be8c80; 1 drivers +v0x1bb5680_0 .net "S1", 0 0, L_0x1be83a0; 1 drivers +v0x1bb5720_0 .net "in0", 0 0, L_0x1bd7280; 1 drivers +v0x1bb57c0_0 .net "in1", 0 0, L_0x1bd7430; 1 drivers +v0x1bb5840_0 .net "in2", 0 0, L_0x1bd70f0; 1 drivers +v0x1bb58e0_0 .net "in3", 0 0, L_0x1bd7320; 1 drivers +v0x1bb59c0_0 .net "nS0", 0 0, L_0x1be8180; 1 drivers +v0x1bb5a60_0 .net "nS1", 0 0, L_0x1be84e0; 1 drivers +v0x1bb5b00_0 .net "out", 0 0, L_0x1be89d0; 1 drivers +v0x1bb5ba0_0 .net "out0", 0 0, L_0x1be8540; 1 drivers +v0x1bb5c40_0 .net "out1", 0 0, L_0x1be8680; 1 drivers +v0x1bb5ce0_0 .net "out2", 0 0, L_0x1be8770; 1 drivers +v0x1bb5df0_0 .net "out3", 0 0, L_0x1be8860; 1 drivers +S_0x1bb4f60 .scope module, "TwoMux" "TwoInMux" 3 294, 3 8, S_0x1bb4df0; + .timescale -9 -12; +L_0x1bd73c0/d .functor NOT 1, L_0x1be95c0, C4<0>, C4<0>, C4<0>; +L_0x1bd73c0 .delay (10000,10000,10000) L_0x1bd73c0/d; +L_0x1be9770/d .functor AND 1, L_0x1be9cf0, L_0x1bd73c0, C4<1>, C4<1>; +L_0x1be9770 .delay (20000,20000,20000) L_0x1be9770/d; +L_0x1be9860/d .functor AND 1, L_0x1be9bc0, L_0x1be95c0, C4<1>, C4<1>; +L_0x1be9860 .delay (20000,20000,20000) L_0x1be9860/d; +L_0x1be9950/d .functor OR 1, L_0x1be9770, L_0x1be9860, C4<0>, C4<0>; +L_0x1be9950 .delay (20000,20000,20000) L_0x1be9950/d; +v0x1bb5050_0 .net "S", 0 0, L_0x1be95c0; 1 drivers +v0x1bb50f0_0 .net "in0", 0 0, L_0x1be9cf0; 1 drivers +v0x1bb5190_0 .net "in1", 0 0, L_0x1be9bc0; 1 drivers +v0x1bb5230_0 .net "nS", 0 0, L_0x1bd73c0; 1 drivers +v0x1bb52b0_0 .net "out0", 0 0, L_0x1be9770; 1 drivers +v0x1bb5350_0 .net "out1", 0 0, L_0x1be9860; 1 drivers +v0x1bb5430_0 .net "outfinal", 0 0, L_0x1be9950; 1 drivers +S_0x1b300c0 .scope generate, "muxbits[3]" "muxbits[3]" 3 290, 3 290, S_0x1b51ae0; + .timescale -9 -12; +P_0x1b2c6c8 .param/l "i" 3 290, +C4<011>; +L_0x1bec8a0/d .functor OR 1, L_0x1becc20, L_0x1beca30, C4<0>, C4<0>; +L_0x1bec8a0 .delay (20000,20000,20000) L_0x1bec8a0/d; +v0x1bb4c90_0 .net *"_s15", 0 0, L_0x1becc20; 1 drivers +v0x1bb4d50_0 .net *"_s16", 0 0, L_0x1beca30; 1 drivers +S_0x1bb4310 .scope module, "ZeroMux" "FourInMux" 3 292, 3 24, S_0x1b300c0; + .timescale -9 -12; +L_0x1bea090/d .functor NOT 1, L_0x1beab90, C4<0>, C4<0>, C4<0>; +L_0x1bea090 .delay (10000,10000,10000) L_0x1bea090/d; +L_0x1bea180/d .functor NOT 1, L_0x1bea280, C4<0>, C4<0>, C4<0>; +L_0x1bea180 .delay (10000,10000,10000) L_0x1bea180/d; +L_0x1bea420/d .functor NAND 1, L_0x1bea090, L_0x1bea180, L_0x1beae30, C4<1>; +L_0x1bea420 .delay (10000,10000,10000) L_0x1bea420/d; +L_0x1bea560/d .functor NAND 1, L_0x1beab90, L_0x1bea180, L_0x1bdcd20, C4<1>; +L_0x1bea560 .delay (10000,10000,10000) L_0x1bea560/d; +L_0x1bea650/d .functor NAND 1, L_0x1bea090, L_0x1bea280, L_0x1beacc0, C4<1>; +L_0x1bea650 .delay (10000,10000,10000) L_0x1bea650/d; +L_0x1bea770/d .functor NAND 1, L_0x1beab90, L_0x1bea280, L_0x1beb270, C4<1>; +L_0x1bea770 .delay (10000,10000,10000) L_0x1bea770/d; +L_0x1bea8e0/d .functor NAND 1, L_0x1bea420, L_0x1bea560, L_0x1bea650, L_0x1bea770; +L_0x1bea8e0 .delay (10000,10000,10000) L_0x1bea8e0/d; +v0x1bb4400_0 .net "S0", 0 0, L_0x1beab90; 1 drivers +v0x1bb44c0_0 .net "S1", 0 0, L_0x1bea280; 1 drivers +v0x1bb4560_0 .net "in0", 0 0, L_0x1beae30; 1 drivers +v0x1bb4600_0 .net "in1", 0 0, L_0x1bdcd20; 1 drivers +v0x1bb4680_0 .net "in2", 0 0, L_0x1beacc0; 1 drivers +v0x1bb4720_0 .net "in3", 0 0, L_0x1beb270; 1 drivers +v0x1bb47c0_0 .net "nS0", 0 0, L_0x1bea090; 1 drivers +v0x1bb4860_0 .net "nS1", 0 0, L_0x1bea180; 1 drivers +v0x1bb4900_0 .net "out", 0 0, L_0x1bea8e0; 1 drivers +v0x1bb49a0_0 .net "out0", 0 0, L_0x1bea420; 1 drivers +v0x1bb4a40_0 .net "out1", 0 0, L_0x1bea560; 1 drivers +v0x1bb4ae0_0 .net "out2", 0 0, L_0x1bea650; 1 drivers +v0x1bb4bf0_0 .net "out3", 0 0, L_0x1bea770; 1 drivers +S_0x1bb38a0 .scope module, "OneMux" "FourInMux" 3 293, 3 24, S_0x1b300c0; + .timescale -9 -12; +L_0x1beadb0/d .functor NOT 1, L_0x1beb0e0, C4<0>, C4<0>, C4<0>; +L_0x1beadb0 .delay (10000,10000,10000) L_0x1beadb0/d; +L_0x1beb3a0/d .functor NOT 1, L_0x1bebd20, C4<0>, C4<0>, C4<0>; +L_0x1beb3a0 .delay (10000,10000,10000) L_0x1beb3a0/d; +L_0x1beb440/d .functor NAND 1, L_0x1beadb0, L_0x1beb3a0, L_0x1bebb80, C4<1>; +L_0x1beb440 .delay (10000,10000,10000) L_0x1beb440/d; +L_0x1beb580/d .functor NAND 1, L_0x1beb0e0, L_0x1beb3a0, L_0x1bebc20, C4<1>; +L_0x1beb580 .delay (10000,10000,10000) L_0x1beb580/d; +L_0x1beb670/d .functor NAND 1, L_0x1beadb0, L_0x1bebd20, L_0x1bec010, C4<1>; +L_0x1beb670 .delay (10000,10000,10000) L_0x1beb670/d; +L_0x1beb760/d .functor NAND 1, L_0x1beb0e0, L_0x1bebd20, L_0x1bec0b0, C4<1>; +L_0x1beb760 .delay (10000,10000,10000) L_0x1beb760/d; +L_0x1beb8d0/d .functor NAND 1, L_0x1beb440, L_0x1beb580, L_0x1beb670, L_0x1beb760; +L_0x1beb8d0 .delay (10000,10000,10000) L_0x1beb8d0/d; +v0x1bb3990_0 .net "S0", 0 0, L_0x1beb0e0; 1 drivers +v0x1bb3a50_0 .net "S1", 0 0, L_0x1bebd20; 1 drivers +v0x1bb3af0_0 .net "in0", 0 0, L_0x1bebb80; 1 drivers +v0x1bb3b90_0 .net "in1", 0 0, L_0x1bebc20; 1 drivers +v0x1bb3c10_0 .net "in2", 0 0, L_0x1bec010; 1 drivers +v0x1bb3cb0_0 .net "in3", 0 0, L_0x1bec0b0; 1 drivers +v0x1bb3d90_0 .net "nS0", 0 0, L_0x1beadb0; 1 drivers +v0x1bb3e30_0 .net "nS1", 0 0, L_0x1beb3a0; 1 drivers +v0x1bb3f20_0 .net "out", 0 0, L_0x1beb8d0; 1 drivers +v0x1bb3fc0_0 .net "out0", 0 0, L_0x1beb440; 1 drivers +v0x1bb40c0_0 .net "out1", 0 0, L_0x1beb580; 1 drivers +v0x1bb4160_0 .net "out2", 0 0, L_0x1beb670; 1 drivers +v0x1bb4270_0 .net "out3", 0 0, L_0x1beb760; 1 drivers +S_0x1b2fe10 .scope module, "TwoMux" "TwoInMux" 3 294, 3 8, S_0x1b300c0; + .timescale -9 -12; +L_0x1be57c0/d .functor NOT 1, L_0x1bec760, C4<0>, C4<0>, C4<0>; +L_0x1be57c0 .delay (10000,10000,10000) L_0x1be57c0/d; +L_0x1bebe50/d .functor AND 1, L_0x1bec360, L_0x1be57c0, C4<1>, C4<1>; +L_0x1bebe50 .delay (20000,20000,20000) L_0x1bebe50/d; +L_0x1bebf40/d .functor AND 1, L_0x1bec450, L_0x1bec760, C4<1>, C4<1>; +L_0x1bebf40 .delay (20000,20000,20000) L_0x1bebf40/d; +L_0x1bec580/d .functor OR 1, L_0x1bebe50, L_0x1bebf40, C4<0>, C4<0>; +L_0x1bec580 .delay (20000,20000,20000) L_0x1bec580/d; +v0x1afa710_0 .net "S", 0 0, L_0x1bec760; 1 drivers +v0x1bb3490_0 .net "in0", 0 0, L_0x1bec360; 1 drivers +v0x1bb3530_0 .net "in1", 0 0, L_0x1bec450; 1 drivers +v0x1bb35d0_0 .net "nS", 0 0, L_0x1be57c0; 1 drivers +v0x1bb3680_0 .net "out0", 0 0, L_0x1bebe50; 1 drivers +v0x1bb3720_0 .net "out1", 0 0, L_0x1bebf40; 1 drivers +v0x1bb3800_0 .net "outfinal", 0 0, L_0x1bec580; 1 drivers + .scope S_0x1b740f0; T_0 ; - %vpi_call 2 150 "$display", "Test 4 Bit Adder Functionality"; - %vpi_call 2 152 "$display", " A | B |Command| Out|ExpectedOut|Cout|OF"; + %vpi_call 2 150 "$dumpfile", "FullALU.vcd"; + %vpi_call 2 151 "$dumpvars"; + %vpi_call 2 153 "$display", "Test 4 Bit Adder Functionality"; + %vpi_call 2 155 "$display", " A | B |Command| Out|ExpectedOut|Cout|OF"; %movi 8, 2, 4; - %set/v v0x1929e30_0, 8, 4; + %set/v v0x1bd6330_0, 8, 4; %movi 8, 4, 4; - %set/v v0x192a030_0, 8, 4; - %set/v v0x192a0b0_0, 0, 3; + %set/v v0x1bd6530_0, 8, 4; + %set/v v0x1bd65b0_0, 0, 3; %delay 1000000, 0; - %vpi_call 2 156 "$display", "%b | %b | %b | %b | Expect 0110| %b | %b ", v0x1929e30_0, v0x192a030_0, v0x192a0b0_0, v0x1929eb0_0, v0x192a3b0_0, v0x192a430_0; + %vpi_call 2 159 "$display", "%b | %b | %b | %b | Expect 0110| %b | %b ", v0x1bd6330_0, v0x1bd6530_0, v0x1bd65b0_0, v0x1bd63b0_0, v0x1bd68b0_0, v0x1bd6930_0; %movi 8, 1, 4; - %set/v v0x1929e30_0, 8, 4; + %set/v v0x1bd6330_0, 8, 4; %movi 8, 6, 4; - %set/v v0x192a030_0, 8, 4; - %set/v v0x192a0b0_0, 0, 3; + %set/v v0x1bd6530_0, 8, 4; + %set/v v0x1bd65b0_0, 0, 3; %delay 1000000, 0; - %vpi_call 2 160 "$display", "%b | %b | %b | %b | Expect 0111| %b | %b ", v0x1929e30_0, v0x192a030_0, v0x192a0b0_0, v0x1929eb0_0, v0x192a3b0_0, v0x192a430_0; + %vpi_call 2 163 "$display", "%b | %b | %b | %b | Expect 0111| %b | %b ", v0x1bd6330_0, v0x1bd6530_0, v0x1bd65b0_0, v0x1bd63b0_0, v0x1bd68b0_0, v0x1bd6930_0; %movi 8, 5, 4; - %set/v v0x1929e30_0, 8, 4; + %set/v v0x1bd6330_0, 8, 4; %movi 8, 13, 4; - %set/v v0x192a030_0, 8, 4; - %set/v v0x192a0b0_0, 0, 3; + %set/v v0x1bd6530_0, 8, 4; + %set/v v0x1bd65b0_0, 0, 3; %delay 1000000, 0; - %vpi_call 2 164 "$display", "%b | %b | %b | %b | Expect 0010| %b | %b ", v0x1929e30_0, v0x192a030_0, v0x192a0b0_0, v0x1929eb0_0, v0x192a3b0_0, v0x192a430_0; + %vpi_call 2 167 "$display", "%b | %b | %b | %b | Expect 0010| %b | %b ", v0x1bd6330_0, v0x1bd6530_0, v0x1bd65b0_0, v0x1bd63b0_0, v0x1bd68b0_0, v0x1bd6930_0; %movi 8, 2, 4; - %set/v v0x1929e30_0, 8, 4; - %set/v v0x192a030_0, 1, 4; - %set/v v0x192a0b0_0, 0, 3; + %set/v v0x1bd6330_0, 8, 4; + %set/v v0x1bd6530_0, 1, 4; + %set/v v0x1bd65b0_0, 0, 3; %delay 1000000, 0; - %vpi_call 2 168 "$display", "%b | %b | %b | %b | Expect 0001| %b | %b ", v0x1929e30_0, v0x192a030_0, v0x192a0b0_0, v0x1929eb0_0, v0x192a3b0_0, v0x192a430_0; + %vpi_call 2 171 "$display", "%b | %b | %b | %b | Expect 0001| %b | %b ", v0x1bd6330_0, v0x1bd6530_0, v0x1bd65b0_0, v0x1bd63b0_0, v0x1bd68b0_0, v0x1bd6930_0; %movi 8, 8, 4; - %set/v v0x1929e30_0, 8, 4; + %set/v v0x1bd6330_0, 8, 4; %movi 8, 3, 4; - %set/v v0x192a030_0, 8, 4; - %set/v v0x192a0b0_0, 0, 3; + %set/v v0x1bd6530_0, 8, 4; + %set/v v0x1bd65b0_0, 0, 3; %delay 1000000, 0; - %vpi_call 2 172 "$display", "%b | %b | %b | %b | Expect 1011| %b | %b ", v0x1929e30_0, v0x192a030_0, v0x192a0b0_0, v0x1929eb0_0, v0x192a3b0_0, v0x192a430_0; + %vpi_call 2 175 "$display", "%b | %b | %b | %b | Expect 1011| %b | %b ", v0x1bd6330_0, v0x1bd6530_0, v0x1bd65b0_0, v0x1bd63b0_0, v0x1bd68b0_0, v0x1bd6930_0; %movi 8, 12, 4; - %set/v v0x1929e30_0, 8, 4; + %set/v v0x1bd6330_0, 8, 4; %movi 8, 2, 4; - %set/v v0x192a030_0, 8, 4; - %set/v v0x192a0b0_0, 0, 3; + %set/v v0x1bd6530_0, 8, 4; + %set/v v0x1bd65b0_0, 0, 3; %delay 1000000, 0; - %vpi_call 2 176 "$display", "%b | %b | %b | %b | Expect 1110| %b | %b ", v0x1929e30_0, v0x192a030_0, v0x192a0b0_0, v0x1929eb0_0, v0x192a3b0_0, v0x192a430_0; + %vpi_call 2 179 "$display", "%b | %b | %b | %b | Expect 1110| %b | %b ", v0x1bd6330_0, v0x1bd6530_0, v0x1bd65b0_0, v0x1bd63b0_0, v0x1bd68b0_0, v0x1bd6930_0; %movi 8, 11, 4; - %set/v v0x1929e30_0, 8, 4; + %set/v v0x1bd6330_0, 8, 4; %movi 8, 5, 4; - %set/v v0x192a030_0, 8, 4; - %set/v v0x192a0b0_0, 0, 3; + %set/v v0x1bd6530_0, 8, 4; + %set/v v0x1bd65b0_0, 0, 3; %delay 1000000, 0; - %vpi_call 2 180 "$display", "%b | %b | %b | %b | Expect 0110| %b | %b ", v0x1929e30_0, v0x192a030_0, v0x192a0b0_0, v0x1929eb0_0, v0x192a3b0_0, v0x192a430_0; + %vpi_call 2 183 "$display", "%b | %b | %b | %b | Expect 0110| %b | %b ", v0x1bd6330_0, v0x1bd6530_0, v0x1bd65b0_0, v0x1bd63b0_0, v0x1bd68b0_0, v0x1bd6930_0; %movi 8, 7, 4; - %set/v v0x1929e30_0, 8, 4; + %set/v v0x1bd6330_0, 8, 4; %movi 8, 9, 4; - %set/v v0x192a030_0, 8, 4; - %set/v v0x192a0b0_0, 0, 3; + %set/v v0x1bd6530_0, 8, 4; + %set/v v0x1bd65b0_0, 0, 3; %delay 1000000, 0; - %vpi_call 2 184 "$display", "%b | %b | %b | %b | Expect 0000| %b | %b ", v0x1929e30_0, v0x192a030_0, v0x192a0b0_0, v0x1929eb0_0, v0x192a3b0_0, v0x192a430_0; + %vpi_call 2 187 "$display", "%b | %b | %b | %b | Expect 0000| %b | %b ", v0x1bd6330_0, v0x1bd6530_0, v0x1bd65b0_0, v0x1bd63b0_0, v0x1bd68b0_0, v0x1bd6930_0; %movi 8, 13, 4; - %set/v v0x1929e30_0, 8, 4; + %set/v v0x1bd6330_0, 8, 4; %movi 8, 12, 4; - %set/v v0x192a030_0, 8, 4; - %set/v v0x192a0b0_0, 0, 3; + %set/v v0x1bd6530_0, 8, 4; + %set/v v0x1bd65b0_0, 0, 3; %delay 1000000, 0; - %vpi_call 2 188 "$display", "%b | %b | %b | %b | Expect 1001| %b | %b ", v0x1929e30_0, v0x192a030_0, v0x192a0b0_0, v0x1929eb0_0, v0x192a3b0_0, v0x192a430_0; + %vpi_call 2 191 "$display", "%b | %b | %b | %b | Expect 1001| %b | %b ", v0x1bd6330_0, v0x1bd6530_0, v0x1bd65b0_0, v0x1bd63b0_0, v0x1bd68b0_0, v0x1bd6930_0; %movi 8, 14, 4; - %set/v v0x1929e30_0, 8, 4; + %set/v v0x1bd6330_0, 8, 4; %movi 8, 10, 4; - %set/v v0x192a030_0, 8, 4; - %set/v v0x192a0b0_0, 0, 3; + %set/v v0x1bd6530_0, 8, 4; + %set/v v0x1bd65b0_0, 0, 3; %delay 1000000, 0; - %vpi_call 2 192 "$display", "%b | %b | %b | %b | Expect 1000| %b | %b ", v0x1929e30_0, v0x192a030_0, v0x192a0b0_0, v0x1929eb0_0, v0x192a3b0_0, v0x192a430_0; + %vpi_call 2 195 "$display", "%b | %b | %b | %b | Expect 1000| %b | %b ", v0x1bd6330_0, v0x1bd6530_0, v0x1bd65b0_0, v0x1bd63b0_0, v0x1bd68b0_0, v0x1bd6930_0; %movi 8, 5, 4; - %set/v v0x1929e30_0, 8, 4; + %set/v v0x1bd6330_0, 8, 4; %movi 8, 6, 4; - %set/v v0x192a030_0, 8, 4; - %set/v v0x192a0b0_0, 0, 3; + %set/v v0x1bd6530_0, 8, 4; + %set/v v0x1bd65b0_0, 0, 3; %delay 1000000, 0; - %vpi_call 2 196 "$display", "%b | %b | %b | %b | Expect XXXX| %b | %b ", v0x1929e30_0, v0x192a030_0, v0x192a0b0_0, v0x1929eb0_0, v0x192a3b0_0, v0x192a430_0; + %vpi_call 2 199 "$display", "%b | %b | %b | %b | Expect XXXX| %b | %b ", v0x1bd6330_0, v0x1bd6530_0, v0x1bd65b0_0, v0x1bd63b0_0, v0x1bd68b0_0, v0x1bd6930_0; %movi 8, 2, 4; - %set/v v0x1929e30_0, 8, 4; + %set/v v0x1bd6330_0, 8, 4; %movi 8, 7, 4; - %set/v v0x192a030_0, 8, 4; - %set/v v0x192a0b0_0, 0, 3; + %set/v v0x1bd6530_0, 8, 4; + %set/v v0x1bd65b0_0, 0, 3; %delay 1000000, 0; - %vpi_call 2 200 "$display", "%b | %b | %b | %b | Expect XXXX| %b | %b ", v0x1929e30_0, v0x192a030_0, v0x192a0b0_0, v0x1929eb0_0, v0x192a3b0_0, v0x192a430_0; + %vpi_call 2 203 "$display", "%b | %b | %b | %b | Expect XXXX| %b | %b ", v0x1bd6330_0, v0x1bd6530_0, v0x1bd65b0_0, v0x1bd63b0_0, v0x1bd68b0_0, v0x1bd6930_0; %movi 8, 7, 4; - %set/v v0x1929e30_0, 8, 4; + %set/v v0x1bd6330_0, 8, 4; %movi 8, 7, 4; - %set/v v0x192a030_0, 8, 4; - %set/v v0x192a0b0_0, 0, 3; + %set/v v0x1bd6530_0, 8, 4; + %set/v v0x1bd65b0_0, 0, 3; %delay 1000000, 0; - %vpi_call 2 204 "$display", "%b | %b | %b | %b | Expect XXXX| %b | %b ", v0x1929e30_0, v0x192a030_0, v0x192a0b0_0, v0x1929eb0_0, v0x192a3b0_0, v0x192a430_0; + %vpi_call 2 207 "$display", "%b | %b | %b | %b | Expect XXXX| %b | %b ", v0x1bd6330_0, v0x1bd6530_0, v0x1bd65b0_0, v0x1bd63b0_0, v0x1bd68b0_0, v0x1bd6930_0; %movi 8, 8, 4; - %set/v v0x1929e30_0, 8, 4; - %set/v v0x192a030_0, 1, 4; - %set/v v0x192a0b0_0, 0, 3; + %set/v v0x1bd6330_0, 8, 4; + %set/v v0x1bd6530_0, 1, 4; + %set/v v0x1bd65b0_0, 0, 3; %delay 1000000, 0; - %vpi_call 2 208 "$display", "%b | %b | %b | %b | Expect XXXX| %b | %b ", v0x1929e30_0, v0x192a030_0, v0x192a0b0_0, v0x1929eb0_0, v0x192a3b0_0, v0x192a430_0; + %vpi_call 2 211 "$display", "%b | %b | %b | %b | Expect XXXX| %b | %b ", v0x1bd6330_0, v0x1bd6530_0, v0x1bd65b0_0, v0x1bd63b0_0, v0x1bd68b0_0, v0x1bd6930_0; %movi 8, 8, 4; - %set/v v0x1929e30_0, 8, 4; + %set/v v0x1bd6330_0, 8, 4; %movi 8, 13, 4; - %set/v v0x192a030_0, 8, 4; - %set/v v0x192a0b0_0, 0, 3; + %set/v v0x1bd6530_0, 8, 4; + %set/v v0x1bd65b0_0, 0, 3; %delay 1000000, 0; - %vpi_call 2 212 "$display", "%b | %b | %b | %b | Expect XXXX| %b | %b ", v0x1929e30_0, v0x192a030_0, v0x192a0b0_0, v0x1929eb0_0, v0x192a3b0_0, v0x192a430_0; + %vpi_call 2 215 "$display", "%b | %b | %b | %b | Expect XXXX| %b | %b ", v0x1bd6330_0, v0x1bd6530_0, v0x1bd65b0_0, v0x1bd63b0_0, v0x1bd68b0_0, v0x1bd6930_0; %movi 8, 11, 4; - %set/v v0x1929e30_0, 8, 4; + %set/v v0x1bd6330_0, 8, 4; %movi 8, 12, 4; - %set/v v0x192a030_0, 8, 4; - %set/v v0x192a0b0_0, 0, 3; + %set/v v0x1bd6530_0, 8, 4; + %set/v v0x1bd65b0_0, 0, 3; %delay 1000000, 0; - %vpi_call 2 216 "$display", "%b | %b | %b | %b | Expect XXXX| %b | %b ", v0x1929e30_0, v0x192a030_0, v0x192a0b0_0, v0x1929eb0_0, v0x192a3b0_0, v0x192a430_0; - %vpi_call 2 218 "$display", "Test 4 Bit SLT Functionality"; - %vpi_call 2 220 "$display", " A | B |Command| Out|ExpectedOut|Cout|OF |SLTflag"; + %vpi_call 2 219 "$display", "%b | %b | %b | %b | Expect XXXX| %b | %b ", v0x1bd6330_0, v0x1bd6530_0, v0x1bd65b0_0, v0x1bd63b0_0, v0x1bd68b0_0, v0x1bd6930_0; + %vpi_call 2 221 "$display", "Test 4 Bit SLT Functionality"; + %vpi_call 2 223 "$display", " A | B |Command| Out|ExpectedOut|Cout|OF |SLTflag"; %movi 8, 2, 4; - %set/v v0x1929e30_0, 8, 4; + %set/v v0x1bd6330_0, 8, 4; %movi 8, 4, 4; - %set/v v0x192a030_0, 8, 4; + %set/v v0x1bd6530_0, 8, 4; %movi 8, 3, 3; - %set/v v0x192a0b0_0, 8, 3; + %set/v v0x1bd65b0_0, 8, 3; %delay 1000000, 0; - %vpi_call 2 224 "$display", "%b | %b | %b | %b | Expect 1110| %b | %b | %b", v0x1929e30_0, v0x192a030_0, v0x192a0b0_0, v0x1929eb0_0, v0x192a3b0_0, v0x192a430_0, v0x192a230_0; + %vpi_call 2 227 "$display", "%b | %b | %b | %b | Expect 1110| %b | %b | %b", v0x1bd6330_0, v0x1bd6530_0, v0x1bd65b0_0, v0x1bd63b0_0, v0x1bd68b0_0, v0x1bd6930_0, v0x1bd6730_0; %movi 8, 4, 4; - %set/v v0x1929e30_0, 8, 4; + %set/v v0x1bd6330_0, 8, 4; %movi 8, 2, 4; - %set/v v0x192a030_0, 8, 4; + %set/v v0x1bd6530_0, 8, 4; %movi 8, 3, 3; - %set/v v0x192a0b0_0, 8, 3; + %set/v v0x1bd65b0_0, 8, 3; %delay 1000000, 0; - %vpi_call 2 228 "$display", "%b | %b | %b | %b | Expect 0010| %b | %b | %b", v0x1929e30_0, v0x192a030_0, v0x192a0b0_0, v0x1929eb0_0, v0x192a3b0_0, v0x192a430_0, v0x192a230_0; + %vpi_call 2 231 "$display", "%b | %b | %b | %b | Expect 0010| %b | %b | %b", v0x1bd6330_0, v0x1bd6530_0, v0x1bd65b0_0, v0x1bd63b0_0, v0x1bd68b0_0, v0x1bd6930_0, v0x1bd6730_0; %movi 8, 14, 4; - %set/v v0x1929e30_0, 8, 4; + %set/v v0x1bd6330_0, 8, 4; %movi 8, 4, 4; - %set/v v0x192a030_0, 8, 4; + %set/v v0x1bd6530_0, 8, 4; %movi 8, 3, 3; - %set/v v0x192a0b0_0, 8, 3; + %set/v v0x1bd65b0_0, 8, 3; %delay 1000000, 0; - %vpi_call 2 232 "$display", "%b | %b | %b | %b | Expect 1010| %b | %b | %b", v0x1929e30_0, v0x192a030_0, v0x192a0b0_0, v0x1929eb0_0, v0x192a3b0_0, v0x192a430_0, v0x192a230_0; + %vpi_call 2 235 "$display", "%b | %b | %b | %b | Expect 1010| %b | %b | %b", v0x1bd6330_0, v0x1bd6530_0, v0x1bd65b0_0, v0x1bd63b0_0, v0x1bd68b0_0, v0x1bd6930_0, v0x1bd6730_0; %movi 8, 4, 4; - %set/v v0x1929e30_0, 8, 4; + %set/v v0x1bd6330_0, 8, 4; %movi 8, 14, 4; - %set/v v0x192a030_0, 8, 4; + %set/v v0x1bd6530_0, 8, 4; %movi 8, 3, 3; - %set/v v0x192a0b0_0, 8, 3; + %set/v v0x1bd65b0_0, 8, 3; %delay 1000000, 0; - %vpi_call 2 236 "$display", "%b | %b | %b | %b | Expect 0110| %b | %b | %b", v0x1929e30_0, v0x192a030_0, v0x192a0b0_0, v0x1929eb0_0, v0x192a3b0_0, v0x192a430_0, v0x192a230_0; + %vpi_call 2 239 "$display", "%b | %b | %b | %b | Expect 0110| %b | %b | %b", v0x1bd6330_0, v0x1bd6530_0, v0x1bd65b0_0, v0x1bd63b0_0, v0x1bd68b0_0, v0x1bd6930_0, v0x1bd6730_0; %movi 8, 14, 4; - %set/v v0x1929e30_0, 8, 4; - %set/v v0x192a030_0, 1, 4; + %set/v v0x1bd6330_0, 8, 4; + %set/v v0x1bd6530_0, 1, 4; %movi 8, 3, 3; - %set/v v0x192a0b0_0, 8, 3; + %set/v v0x1bd65b0_0, 8, 3; %delay 1000000, 0; - %vpi_call 2 240 "$display", "%b | %b | %b | %b | Expect 1111| %b | %b | %b", v0x1929e30_0, v0x192a030_0, v0x192a0b0_0, v0x1929eb0_0, v0x192a3b0_0, v0x192a430_0, v0x192a230_0; - %set/v v0x1929e30_0, 1, 4; + %vpi_call 2 243 "$display", "%b | %b | %b | %b | Expect 1111| %b | %b | %b", v0x1bd6330_0, v0x1bd6530_0, v0x1bd65b0_0, v0x1bd63b0_0, v0x1bd68b0_0, v0x1bd6930_0, v0x1bd6730_0; + %set/v v0x1bd6330_0, 1, 4; %movi 8, 14, 4; - %set/v v0x192a030_0, 8, 4; + %set/v v0x1bd6530_0, 8, 4; %movi 8, 3, 3; - %set/v v0x192a0b0_0, 8, 3; + %set/v v0x1bd65b0_0, 8, 3; %delay 1000000, 0; - %vpi_call 2 244 "$display", "%b | %b | %b | %b | Expect 0001| %b | %b | %b", v0x1929e30_0, v0x192a030_0, v0x192a0b0_0, v0x1929eb0_0, v0x192a3b0_0, v0x192a430_0, v0x192a230_0; + %vpi_call 2 247 "$display", "%b | %b | %b | %b | Expect 0001| %b | %b | %b", v0x1bd6330_0, v0x1bd6530_0, v0x1bd65b0_0, v0x1bd63b0_0, v0x1bd68b0_0, v0x1bd6930_0, v0x1bd6730_0; %movi 8, 13, 4; - %set/v v0x1929e30_0, 8, 4; + %set/v v0x1bd6330_0, 8, 4; %movi 8, 13, 4; - %set/v v0x192a030_0, 8, 4; + %set/v v0x1bd6530_0, 8, 4; %movi 8, 3, 3; - %set/v v0x192a0b0_0, 8, 3; + %set/v v0x1bd65b0_0, 8, 3; %delay 1000000, 0; - %vpi_call 2 248 "$display", "%b | %b | %b | %b | Expect 0000| %b | %b | %b", v0x1929e30_0, v0x192a030_0, v0x192a0b0_0, v0x1929eb0_0, v0x192a3b0_0, v0x192a430_0, v0x192a230_0; + %vpi_call 2 251 "$display", "%b | %b | %b | %b | Expect 0000| %b | %b | %b", v0x1bd6330_0, v0x1bd6530_0, v0x1bd65b0_0, v0x1bd63b0_0, v0x1bd68b0_0, v0x1bd6930_0, v0x1bd6730_0; %movi 8, 5, 4; - %set/v v0x1929e30_0, 8, 4; + %set/v v0x1bd6330_0, 8, 4; %movi 8, 5, 4; - %set/v v0x192a030_0, 8, 4; + %set/v v0x1bd6530_0, 8, 4; %movi 8, 3, 3; - %set/v v0x192a0b0_0, 8, 3; + %set/v v0x1bd65b0_0, 8, 3; %delay 1000000, 0; - %vpi_call 2 252 "$display", "%b | %b | %b | %b | Expect 0000| %b | %b | %b", v0x1929e30_0, v0x192a030_0, v0x192a0b0_0, v0x1929eb0_0, v0x192a3b0_0, v0x192a430_0, v0x192a230_0; + %vpi_call 2 255 "$display", "%b | %b | %b | %b | Expect 0000| %b | %b | %b", v0x1bd6330_0, v0x1bd6530_0, v0x1bd65b0_0, v0x1bd63b0_0, v0x1bd68b0_0, v0x1bd6930_0, v0x1bd6730_0; %movi 8, 9, 4; - %set/v v0x1929e30_0, 8, 4; + %set/v v0x1bd6330_0, 8, 4; %movi 8, 5, 4; - %set/v v0x192a030_0, 8, 4; + %set/v v0x1bd6530_0, 8, 4; %movi 8, 3, 3; - %set/v v0x192a0b0_0, 8, 3; + %set/v v0x1bd65b0_0, 8, 3; %delay 1000000, 0; - %vpi_call 2 256 "$display", "%b | %b | %b | %b | Expect XXXX| %b | %b | %b", v0x1929e30_0, v0x192a030_0, v0x192a0b0_0, v0x1929eb0_0, v0x192a3b0_0, v0x192a430_0, v0x192a230_0; - %vpi_call 2 258 "$display", "Test 4 Bit AND/NAND Functionality"; - %vpi_call 2 260 "$display", " A | B |Command| Out |ExpectedOut-AND"; - %set/v v0x1929e30_0, 1, 4; - %set/v v0x192a030_0, 1, 4; + %vpi_call 2 259 "$display", "%b | %b | %b | %b | Expect XXXX| %b | %b | %b", v0x1bd6330_0, v0x1bd6530_0, v0x1bd65b0_0, v0x1bd63b0_0, v0x1bd68b0_0, v0x1bd6930_0, v0x1bd6730_0; + %vpi_call 2 261 "$display", "Test 4 Bit AND/NAND Functionality"; + %vpi_call 2 263 "$display", " A | B |Command| Out |ExpectedOut-AND"; + %set/v v0x1bd6330_0, 1, 4; + %set/v v0x1bd6530_0, 1, 4; %movi 8, 4, 3; - %set/v v0x192a0b0_0, 8, 3; + %set/v v0x1bd65b0_0, 8, 3; %delay 1000000, 0; - %vpi_call 2 264 "$display", "%b | %b | %b | %b | 1111", v0x1929e30_0, v0x192a030_0, v0x192a0b0_0, v0x1929fb0_0; - %set/v v0x1929e30_0, 1, 4; + %vpi_call 2 267 "$display", "%b | %b | %b | %b | 1111", v0x1bd6330_0, v0x1bd6530_0, v0x1bd65b0_0, v0x1bd64b0_0; + %set/v v0x1bd6330_0, 1, 4; %movi 8, 10, 4; - %set/v v0x192a030_0, 8, 4; + %set/v v0x1bd6530_0, 8, 4; %movi 8, 4, 3; - %set/v v0x192a0b0_0, 8, 3; + %set/v v0x1bd65b0_0, 8, 3; %delay 1000000, 0; - %vpi_call 2 268 "$display", "%b | %b | %b | %b | 1010", v0x1929e30_0, v0x192a030_0, v0x192a0b0_0, v0x1929fb0_0; - %set/v v0x1929e30_0, 1, 4; + %vpi_call 2 271 "$display", "%b | %b | %b | %b | 1010", v0x1bd6330_0, v0x1bd6530_0, v0x1bd65b0_0, v0x1bd64b0_0; + %set/v v0x1bd6330_0, 1, 4; %movi 8, 5, 4; - %set/v v0x192a030_0, 8, 4; + %set/v v0x1bd6530_0, 8, 4; %movi 8, 4, 3; - %set/v v0x192a0b0_0, 8, 3; + %set/v v0x1bd65b0_0, 8, 3; %delay 1000000, 0; - %vpi_call 2 272 "$display", "%b | %b | %b | %b | 0101", v0x1929e30_0, v0x192a030_0, v0x192a0b0_0, v0x1929fb0_0; - %set/v v0x1929e30_0, 1, 4; - %set/v v0x192a030_0, 0, 4; + %vpi_call 2 275 "$display", "%b | %b | %b | %b | 0101", v0x1bd6330_0, v0x1bd6530_0, v0x1bd65b0_0, v0x1bd64b0_0; + %set/v v0x1bd6330_0, 1, 4; + %set/v v0x1bd6530_0, 0, 4; %movi 8, 4, 3; - %set/v v0x192a0b0_0, 8, 3; + %set/v v0x1bd65b0_0, 8, 3; %delay 1000000, 0; - %vpi_call 2 276 "$display", "%b | %b | %b | %b | 0000", v0x1929e30_0, v0x192a030_0, v0x192a0b0_0, v0x1929fb0_0; - %vpi_call 2 279 "$display", " A | B |Command| Out |ExpectedOut-NAND"; - %set/v v0x1929e30_0, 1, 4; - %set/v v0x192a030_0, 1, 4; + %vpi_call 2 279 "$display", "%b | %b | %b | %b | 0000", v0x1bd6330_0, v0x1bd6530_0, v0x1bd65b0_0, v0x1bd64b0_0; + %vpi_call 2 282 "$display", " A | B |Command| Out |ExpectedOut-NAND"; + %set/v v0x1bd6330_0, 1, 4; + %set/v v0x1bd6530_0, 1, 4; %movi 8, 5, 3; - %set/v v0x192a0b0_0, 8, 3; + %set/v v0x1bd65b0_0, 8, 3; %delay 1000000, 0; - %vpi_call 2 283 "$display", "%b | %b | %b | %b | 0000", v0x1929e30_0, v0x192a030_0, v0x192a0b0_0, v0x1929fb0_0; - %set/v v0x1929e30_0, 1, 4; + %vpi_call 2 286 "$display", "%b | %b | %b | %b | 0000", v0x1bd6330_0, v0x1bd6530_0, v0x1bd65b0_0, v0x1bd64b0_0; + %set/v v0x1bd6330_0, 1, 4; %movi 8, 10, 4; - %set/v v0x192a030_0, 8, 4; + %set/v v0x1bd6530_0, 8, 4; %movi 8, 5, 3; - %set/v v0x192a0b0_0, 8, 3; + %set/v v0x1bd65b0_0, 8, 3; %delay 1000000, 0; - %vpi_call 2 287 "$display", "%b | %b | %b | %b | 0101", v0x1929e30_0, v0x192a030_0, v0x192a0b0_0, v0x1929fb0_0; - %set/v v0x1929e30_0, 1, 4; + %vpi_call 2 290 "$display", "%b | %b | %b | %b | 0101", v0x1bd6330_0, v0x1bd6530_0, v0x1bd65b0_0, v0x1bd64b0_0; + %set/v v0x1bd6330_0, 1, 4; %movi 8, 5, 4; - %set/v v0x192a030_0, 8, 4; + %set/v v0x1bd6530_0, 8, 4; %movi 8, 5, 3; - %set/v v0x192a0b0_0, 8, 3; + %set/v v0x1bd65b0_0, 8, 3; %delay 1000000, 0; - %vpi_call 2 291 "$display", "%b | %b | %b | %b | 1010", v0x1929e30_0, v0x192a030_0, v0x192a0b0_0, v0x1929fb0_0; - %set/v v0x1929e30_0, 1, 4; - %set/v v0x192a030_0, 0, 4; + %vpi_call 2 294 "$display", "%b | %b | %b | %b | 1010", v0x1bd6330_0, v0x1bd6530_0, v0x1bd65b0_0, v0x1bd64b0_0; + %set/v v0x1bd6330_0, 1, 4; + %set/v v0x1bd6530_0, 0, 4; %movi 8, 5, 3; - %set/v v0x192a0b0_0, 8, 3; + %set/v v0x1bd65b0_0, 8, 3; %delay 1000000, 0; - %vpi_call 2 295 "$display", "%b | %b | %b | %b | 1111", v0x1929e30_0, v0x192a030_0, v0x192a0b0_0, v0x1929fb0_0; - %vpi_call 2 297 "$display", "Test 4 Bit OR/NOR/XOR Functionality"; - %vpi_call 2 299 "$display", " A | B |Command | Out |ExpectedOut-OR"; + %vpi_call 2 298 "$display", "%b | %b | %b | %b | 1111", v0x1bd6330_0, v0x1bd6530_0, v0x1bd65b0_0, v0x1bd64b0_0; + %vpi_call 2 300 "$display", "Test 4 Bit OR/NOR/XOR Functionality"; + %vpi_call 2 302 "$display", " A | B |Command | Out |ExpectedOut-OR"; %movi 8, 10, 4; - %set/v v0x1929e30_0, 8, 4; + %set/v v0x1bd6330_0, 8, 4; %movi 8, 5, 4; - %set/v v0x192a030_0, 8, 4; - %set/v v0x192a0b0_0, 1, 3; + %set/v v0x1bd6530_0, 8, 4; + %set/v v0x1bd65b0_0, 1, 3; %delay 1000000, 0; - %vpi_call 2 303 "$display", "%b | %b | %b | %b | 1111", v0x1929e30_0, v0x192a030_0, v0x192a0b0_0, v0x192a1b0_0; - %set/v v0x1929e30_0, 1, 4; + %vpi_call 2 306 "$display", "%b | %b | %b | %b | 1111", v0x1bd6330_0, v0x1bd6530_0, v0x1bd65b0_0, v0x1bd66b0_0; + %set/v v0x1bd6330_0, 1, 4; %movi 8, 5, 4; - %set/v v0x192a030_0, 8, 4; - %set/v v0x192a0b0_0, 1, 3; + %set/v v0x1bd6530_0, 8, 4; + %set/v v0x1bd65b0_0, 1, 3; %delay 1000000, 0; - %vpi_call 2 307 "$display", "%b | %b | %b | %b | 1111", v0x1929e30_0, v0x192a030_0, v0x192a0b0_0, v0x192a1b0_0; + %vpi_call 2 310 "$display", "%b | %b | %b | %b | 1111", v0x1bd6330_0, v0x1bd6530_0, v0x1bd65b0_0, v0x1bd66b0_0; %movi 8, 11, 4; - %set/v v0x1929e30_0, 8, 4; - %set/v v0x192a030_0, 0, 4; - %set/v v0x192a0b0_0, 1, 3; + %set/v v0x1bd6330_0, 8, 4; + %set/v v0x1bd6530_0, 0, 4; + %set/v v0x1bd65b0_0, 1, 3; %delay 1000000, 0; - %vpi_call 2 311 "$display", "%b | %b | %b | %b | 1011", v0x1929e30_0, v0x192a030_0, v0x192a0b0_0, v0x192a1b0_0; - %vpi_call 2 313 "$display", " A | B |Command | Out |ExpectedOut-NOR"; + %vpi_call 2 314 "$display", "%b | %b | %b | %b | 1011", v0x1bd6330_0, v0x1bd6530_0, v0x1bd65b0_0, v0x1bd66b0_0; + %vpi_call 2 316 "$display", " A | B |Command | Out |ExpectedOut-NOR"; %movi 8, 10, 4; - %set/v v0x1929e30_0, 8, 4; + %set/v v0x1bd6330_0, 8, 4; %movi 8, 5, 4; - %set/v v0x192a030_0, 8, 4; + %set/v v0x1bd6530_0, 8, 4; %movi 8, 6, 3; - %set/v v0x192a0b0_0, 8, 3; + %set/v v0x1bd65b0_0, 8, 3; %delay 1000000, 0; - %vpi_call 2 317 "$display", "%b | %b | %b | %b | 0000", v0x1929e30_0, v0x192a030_0, v0x192a0b0_0, v0x192a1b0_0; - %set/v v0x1929e30_0, 1, 4; + %vpi_call 2 320 "$display", "%b | %b | %b | %b | 0000", v0x1bd6330_0, v0x1bd6530_0, v0x1bd65b0_0, v0x1bd66b0_0; + %set/v v0x1bd6330_0, 1, 4; %movi 8, 5, 4; - %set/v v0x192a030_0, 8, 4; + %set/v v0x1bd6530_0, 8, 4; %movi 8, 6, 3; - %set/v v0x192a0b0_0, 8, 3; + %set/v v0x1bd65b0_0, 8, 3; %delay 1000000, 0; - %vpi_call 2 321 "$display", "%b | %b | %b | %b | 0000", v0x1929e30_0, v0x192a030_0, v0x192a0b0_0, v0x192a1b0_0; + %vpi_call 2 324 "$display", "%b | %b | %b | %b | 0000", v0x1bd6330_0, v0x1bd6530_0, v0x1bd65b0_0, v0x1bd66b0_0; %movi 8, 11, 4; - %set/v v0x1929e30_0, 8, 4; - %set/v v0x192a030_0, 0, 4; + %set/v v0x1bd6330_0, 8, 4; + %set/v v0x1bd6530_0, 0, 4; %movi 8, 6, 3; - %set/v v0x192a0b0_0, 8, 3; + %set/v v0x1bd65b0_0, 8, 3; %delay 1000000, 0; - %vpi_call 2 325 "$display", "%b | %b | %b | %b | 0100", v0x1929e30_0, v0x192a030_0, v0x192a0b0_0, v0x192a1b0_0; - %vpi_call 2 327 "$display", " A | B |Command | Out |ExpectedOut-XOR"; + %vpi_call 2 328 "$display", "%b | %b | %b | %b | 0100", v0x1bd6330_0, v0x1bd6530_0, v0x1bd65b0_0, v0x1bd66b0_0; + %vpi_call 2 330 "$display", " A | B |Command | Out |ExpectedOut-XOR"; %movi 8, 10, 4; - %set/v v0x1929e30_0, 8, 4; + %set/v v0x1bd6330_0, 8, 4; %movi 8, 5, 4; - %set/v v0x192a030_0, 8, 4; + %set/v v0x1bd6530_0, 8, 4; %movi 8, 2, 3; - %set/v v0x192a0b0_0, 8, 3; + %set/v v0x1bd65b0_0, 8, 3; %delay 1000000, 0; - %vpi_call 2 331 "$display", "%b | %b | %b | %b | 1111", v0x1929e30_0, v0x192a030_0, v0x192a0b0_0, v0x192a1b0_0; - %set/v v0x1929e30_0, 1, 4; + %vpi_call 2 334 "$display", "%b | %b | %b | %b | 1111", v0x1bd6330_0, v0x1bd6530_0, v0x1bd65b0_0, v0x1bd66b0_0; + %set/v v0x1bd6330_0, 1, 4; %movi 8, 5, 4; - %set/v v0x192a030_0, 8, 4; + %set/v v0x1bd6530_0, 8, 4; %movi 8, 2, 3; - %set/v v0x192a0b0_0, 8, 3; + %set/v v0x1bd65b0_0, 8, 3; %delay 1000000, 0; - %vpi_call 2 335 "$display", "%b | %b | %b | %b | 1010", v0x1929e30_0, v0x192a030_0, v0x192a0b0_0, v0x192a1b0_0; + %vpi_call 2 338 "$display", "%b | %b | %b | %b | 1010", v0x1bd6330_0, v0x1bd6530_0, v0x1bd65b0_0, v0x1bd66b0_0; %movi 8, 11, 4; - %set/v v0x1929e30_0, 8, 4; - %set/v v0x192a030_0, 0, 4; + %set/v v0x1bd6330_0, 8, 4; + %set/v v0x1bd6530_0, 0, 4; %movi 8, 2, 3; - %set/v v0x192a0b0_0, 8, 3; + %set/v v0x1bd65b0_0, 8, 3; %delay 1000000, 0; - %vpi_call 2 339 "$display", "%b | %b | %b | %b | 1011", v0x1929e30_0, v0x192a030_0, v0x192a0b0_0, v0x192a1b0_0; - %vpi_call 2 341 "$display", "Test 4 Bit ALU Functionality"; - %vpi_call 2 343 "$display", " A | B |Command | Out |ExpectedOut | COut | OF |SLT|Zero"; - %set/v v0x1929e30_0, 1, 4; - %set/v v0x192a030_0, 1, 4; + %vpi_call 2 342 "$display", "%b | %b | %b | %b | 1011", v0x1bd6330_0, v0x1bd6530_0, v0x1bd65b0_0, v0x1bd66b0_0; + %vpi_call 2 344 "$display", "Test 4 Bit ALU Functionality"; + %vpi_call 2 346 "$display", " A | B |Command | Out |ExpectedOut | COut | OF |SLT|Zero"; + %set/v v0x1bd6330_0, 1, 4; + %set/v v0x1bd6530_0, 1, 4; %movi 8, 4, 3; - %set/v v0x192a0b0_0, 8, 3; + %set/v v0x1bd65b0_0, 8, 3; %delay 1000000, 0; - %vpi_call 2 348 "$display", "%b | %b | %b - AND | %b | 1111 | %b | %b | %b | %b", v0x1929e30_0, v0x192a030_0, v0x192a0b0_0, v0x192a130_0, v0x192a3b0_0, v0x192a430_0, v0x192a230_0, v0x1929f30_0; - %set/v v0x1929e30_0, 1, 4; - %set/v v0x192a030_0, 0, 4; + %vpi_call 2 351 "$display", "%b | %b | %b - AND | %b | 1111 | %b | %b | %b | %b", v0x1bd6330_0, v0x1bd6530_0, v0x1bd65b0_0, v0x1bd6630_0, v0x1bd68b0_0, v0x1bd6930_0, v0x1bd6730_0, v0x1bd6430_0; + %set/v v0x1bd6330_0, 1, 4; + %set/v v0x1bd6530_0, 0, 4; %movi 8, 5, 3; - %set/v v0x192a0b0_0, 8, 3; + %set/v v0x1bd65b0_0, 8, 3; %delay 1000000, 0; - %vpi_call 2 353 "$display", "%b | %b | %b - NAND | %b | 1111 | %b | %b | %b | %b", v0x1929e30_0, v0x192a030_0, v0x192a0b0_0, v0x192a130_0, v0x192a3b0_0, v0x192a430_0, v0x192a230_0, v0x1929f30_0; - %set/v v0x1929e30_0, 1, 4; + %vpi_call 2 356 "$display", "%b | %b | %b - NAND | %b | 1111 | %b | %b | %b | %b", v0x1bd6330_0, v0x1bd6530_0, v0x1bd65b0_0, v0x1bd6630_0, v0x1bd68b0_0, v0x1bd6930_0, v0x1bd6730_0, v0x1bd6430_0; + %set/v v0x1bd6330_0, 1, 4; %movi 8, 5, 4; - %set/v v0x192a030_0, 8, 4; - %set/v v0x192a0b0_0, 1, 3; + %set/v v0x1bd6530_0, 8, 4; + %set/v v0x1bd65b0_0, 1, 3; %delay 1000000, 0; - %vpi_call 2 358 "$display", "%b | %b | %b - OR | %b | 1111 | %b | %b | %b | %b", v0x1929e30_0, v0x192a030_0, v0x192a0b0_0, v0x192a130_0, v0x192a3b0_0, v0x192a430_0, v0x192a230_0, v0x1929f30_0; + %vpi_call 2 361 "$display", "%b | %b | %b - OR | %b | 1111 | %b | %b | %b | %b", v0x1bd6330_0, v0x1bd6530_0, v0x1bd65b0_0, v0x1bd6630_0, v0x1bd68b0_0, v0x1bd6930_0, v0x1bd6730_0, v0x1bd6430_0; %movi 8, 11, 4; - %set/v v0x1929e30_0, 8, 4; - %set/v v0x192a030_0, 0, 4; + %set/v v0x1bd6330_0, 8, 4; + %set/v v0x1bd6530_0, 0, 4; %movi 8, 6, 3; - %set/v v0x192a0b0_0, 8, 3; + %set/v v0x1bd65b0_0, 8, 3; %delay 1000000, 0; - %vpi_call 2 363 "$display", "%b | %b | %b - NOR | %b | 0100 | %b | %b | %b | %b", v0x1929e30_0, v0x192a030_0, v0x192a0b0_0, v0x192a130_0, v0x192a3b0_0, v0x192a430_0, v0x192a230_0, v0x1929f30_0; + %vpi_call 2 366 "$display", "%b | %b | %b - NOR | %b | 0100 | %b | %b | %b | %b", v0x1bd6330_0, v0x1bd6530_0, v0x1bd65b0_0, v0x1bd6630_0, v0x1bd68b0_0, v0x1bd6930_0, v0x1bd6730_0, v0x1bd6430_0; %movi 8, 11, 4; - %set/v v0x1929e30_0, 8, 4; - %set/v v0x192a030_0, 0, 4; + %set/v v0x1bd6330_0, 8, 4; + %set/v v0x1bd6530_0, 0, 4; %movi 8, 2, 3; - %set/v v0x192a0b0_0, 8, 3; + %set/v v0x1bd65b0_0, 8, 3; %delay 1000000, 0; - %vpi_call 2 368 "$display", "%b | %b | %b - XOR | %b | 1011 | %b | %b | %b | %b", v0x1929e30_0, v0x192a030_0, v0x192a0b0_0, v0x192a130_0, v0x192a3b0_0, v0x192a430_0, v0x192a230_0, v0x1929f30_0; + %vpi_call 2 371 "$display", "%b | %b | %b - XOR | %b | 1011 | %b | %b | %b | %b", v0x1bd6330_0, v0x1bd6530_0, v0x1bd65b0_0, v0x1bd6630_0, v0x1bd68b0_0, v0x1bd6930_0, v0x1bd6730_0, v0x1bd6430_0; %movi 8, 2, 4; - %set/v v0x1929e30_0, 8, 4; + %set/v v0x1bd6330_0, 8, 4; %movi 8, 4, 4; - %set/v v0x192a030_0, 8, 4; - %set/v v0x192a0b0_0, 0, 3; + %set/v v0x1bd6530_0, 8, 4; + %set/v v0x1bd65b0_0, 0, 3; %delay 1000000, 0; - %vpi_call 2 373 "$display", "%b | %b | %b - ADD | %b | 0110 | %b | %b | %b | %b", v0x1929e30_0, v0x192a030_0, v0x192a0b0_0, v0x192a130_0, v0x192a3b0_0, v0x192a430_0, v0x192a230_0, v0x1929f30_0; + %vpi_call 2 376 "$display", "%b | %b | %b - ADD | %b | 0110 | %b | %b | %b | %b", v0x1bd6330_0, v0x1bd6530_0, v0x1bd65b0_0, v0x1bd6630_0, v0x1bd68b0_0, v0x1bd6930_0, v0x1bd6730_0, v0x1bd6430_0; %movi 8, 11, 4; - %set/v v0x1929e30_0, 8, 4; + %set/v v0x1bd6330_0, 8, 4; %movi 8, 12, 4; - %set/v v0x192a030_0, 8, 4; - %set/v v0x192a0b0_0, 0, 3; + %set/v v0x1bd6530_0, 8, 4; + %set/v v0x1bd65b0_0, 0, 3; %delay 1000000, 0; - %vpi_call 2 377 "$display", "%b | %b | %b - ADD | %b | XXXX | %b | %b | %b | %b", v0x1929e30_0, v0x192a030_0, v0x192a0b0_0, v0x192a130_0, v0x192a3b0_0, v0x192a430_0, v0x192a230_0, v0x1929f30_0; + %vpi_call 2 380 "$display", "%b | %b | %b - ADD | %b | XXXX | %b | %b | %b | %b", v0x1bd6330_0, v0x1bd6530_0, v0x1bd65b0_0, v0x1bd6630_0, v0x1bd68b0_0, v0x1bd6930_0, v0x1bd6730_0, v0x1bd6430_0; %movi 8, 2, 4; - %set/v v0x1929e30_0, 8, 4; + %set/v v0x1bd6330_0, 8, 4; %movi 8, 4, 4; - %set/v v0x192a030_0, 8, 4; + %set/v v0x1bd6530_0, 8, 4; %movi 8, 1, 3; - %set/v v0x192a0b0_0, 8, 3; + %set/v v0x1bd65b0_0, 8, 3; %delay 1000000, 0; - %vpi_call 2 382 "$display", "%b | %b | %b - SUB | %b | 1110 | %b | %b | %b | %b", v0x1929e30_0, v0x192a030_0, v0x192a0b0_0, v0x192a130_0, v0x192a3b0_0, v0x192a430_0, v0x192a230_0, v0x1929f30_0; + %vpi_call 2 385 "$display", "%b | %b | %b - SUB | %b | 1110 | %b | %b | %b | %b", v0x1bd6330_0, v0x1bd6530_0, v0x1bd65b0_0, v0x1bd6630_0, v0x1bd68b0_0, v0x1bd6930_0, v0x1bd6730_0, v0x1bd6430_0; %movi 8, 9, 4; - %set/v v0x1929e30_0, 8, 4; + %set/v v0x1bd6330_0, 8, 4; %movi 8, 3, 4; - %set/v v0x192a030_0, 8, 4; + %set/v v0x1bd6530_0, 8, 4; %movi 8, 1, 3; - %set/v v0x192a0b0_0, 8, 3; + %set/v v0x1bd65b0_0, 8, 3; %delay 1000000, 0; - %vpi_call 2 386 "$display", "%b | %b | %b - SUB | %b | XXXX | %b | %b | %b | %b", v0x1929e30_0, v0x192a030_0, v0x192a0b0_0, v0x192a130_0, v0x192a3b0_0, v0x192a430_0, v0x192a230_0, v0x1929f30_0; + %vpi_call 2 389 "$display", "%b | %b | %b - SUB | %b | XXXX | %b | %b | %b | %b", v0x1bd6330_0, v0x1bd6530_0, v0x1bd65b0_0, v0x1bd6630_0, v0x1bd68b0_0, v0x1bd6930_0, v0x1bd6730_0, v0x1bd6430_0; %movi 8, 4, 4; - %set/v v0x1929e30_0, 8, 4; + %set/v v0x1bd6330_0, 8, 4; %movi 8, 2, 4; - %set/v v0x192a030_0, 8, 4; + %set/v v0x1bd6530_0, 8, 4; %movi 8, 3, 3; - %set/v v0x192a0b0_0, 8, 3; + %set/v v0x1bd65b0_0, 8, 3; %delay 1000000, 0; - %vpi_call 2 392 "$display", "%b | %b | %b - SLT | %b | 0010 | %b | %b | %b | %b", v0x1929e30_0, v0x192a030_0, v0x192a0b0_0, v0x192a130_0, v0x192a3b0_0, v0x192a430_0, v0x192a230_0, v0x1929f30_0; + %vpi_call 2 395 "$display", "%b | %b | %b - SLT | %b | 0010 | %b | %b | %b | %b", v0x1bd6330_0, v0x1bd6530_0, v0x1bd65b0_0, v0x1bd6630_0, v0x1bd68b0_0, v0x1bd6930_0, v0x1bd6730_0, v0x1bd6430_0; %movi 8, 9, 4; - %set/v v0x1929e30_0, 8, 4; + %set/v v0x1bd6330_0, 8, 4; %movi 8, 5, 4; - %set/v v0x192a030_0, 8, 4; + %set/v v0x1bd6530_0, 8, 4; %movi 8, 3, 3; - %set/v v0x192a0b0_0, 8, 3; + %set/v v0x1bd65b0_0, 8, 3; %delay 1000000, 0; - %vpi_call 2 396 "$display", "%b | %b | %b - SLT | %b | XXXX | %b | %b | %b | %b", v0x1929e30_0, v0x192a030_0, v0x192a0b0_0, v0x192a130_0, v0x192a3b0_0, v0x192a430_0, v0x192a230_0, v0x1929f30_0; - %set/v v0x1929e30_0, 0, 4; - %set/v v0x192a030_0, 1, 4; + %vpi_call 2 399 "$display", "%b | %b | %b - SLT | %b | XXXX | %b | %b | %b | %b", v0x1bd6330_0, v0x1bd6530_0, v0x1bd65b0_0, v0x1bd6630_0, v0x1bd68b0_0, v0x1bd6930_0, v0x1bd6730_0, v0x1bd6430_0; + %set/v v0x1bd6330_0, 0, 4; + %set/v v0x1bd6530_0, 1, 4; %movi 8, 4, 3; - %set/v v0x192a0b0_0, 8, 3; + %set/v v0x1bd65b0_0, 8, 3; %delay 1000000, 0; - %vpi_call 2 402 "$display", "%b | %b | %b - AND | %b | 0000 | %b | %b | %b | %b", v0x1929e30_0, v0x192a030_0, v0x192a0b0_0, v0x192a130_0, v0x192a3b0_0, v0x192a430_0, v0x192a230_0, v0x1929f30_0; - %set/v v0x1929e30_0, 1, 4; - %set/v v0x192a030_0, 1, 4; + %vpi_call 2 405 "$display", "%b | %b | %b - AND | %b | 0000 | %b | %b | %b | %b", v0x1bd6330_0, v0x1bd6530_0, v0x1bd65b0_0, v0x1bd6630_0, v0x1bd68b0_0, v0x1bd6930_0, v0x1bd6730_0, v0x1bd6430_0; + %set/v v0x1bd6330_0, 1, 4; + %set/v v0x1bd6530_0, 1, 4; %movi 8, 5, 3; - %set/v v0x192a0b0_0, 8, 3; + %set/v v0x1bd65b0_0, 8, 3; %delay 1000000, 0; - %vpi_call 2 405 "$display", "%b | %b | %b - NAND | %b | 0000 | %b | %b | %b | %b", v0x1929e30_0, v0x192a030_0, v0x192a0b0_0, v0x192a130_0, v0x192a3b0_0, v0x192a430_0, v0x192a230_0, v0x1929f30_0; - %set/v v0x1929e30_0, 0, 4; - %set/v v0x192a030_0, 0, 4; - %set/v v0x192a0b0_0, 1, 3; + %vpi_call 2 408 "$display", "%b | %b | %b - NAND | %b | 0000 | %b | %b | %b | %b", v0x1bd6330_0, v0x1bd6530_0, v0x1bd65b0_0, v0x1bd6630_0, v0x1bd68b0_0, v0x1bd6930_0, v0x1bd6730_0, v0x1bd6430_0; + %set/v v0x1bd6330_0, 0, 4; + %set/v v0x1bd6530_0, 0, 4; + %set/v v0x1bd65b0_0, 1, 3; %delay 1000000, 0; - %vpi_call 2 408 "$display", "%b | %b | %b - OR | %b | 0000 | %b | %b | %b | %b", v0x1929e30_0, v0x192a030_0, v0x192a0b0_0, v0x192a130_0, v0x192a3b0_0, v0x192a430_0, v0x192a230_0, v0x1929f30_0; + %vpi_call 2 411 "$display", "%b | %b | %b - OR | %b | 0000 | %b | %b | %b | %b", v0x1bd6330_0, v0x1bd6530_0, v0x1bd65b0_0, v0x1bd6630_0, v0x1bd68b0_0, v0x1bd6930_0, v0x1bd6730_0, v0x1bd6430_0; %movi 8, 11, 4; - %set/v v0x1929e30_0, 8, 4; + %set/v v0x1bd6330_0, 8, 4; %movi 8, 4, 4; - %set/v v0x192a030_0, 8, 4; + %set/v v0x1bd6530_0, 8, 4; %movi 8, 6, 3; - %set/v v0x192a0b0_0, 8, 3; + %set/v v0x1bd65b0_0, 8, 3; %delay 1000000, 0; - %vpi_call 2 410 "$display", "%b | %b | %b - NOR | %b | 0000 | %b | %b | %b | %b", v0x1929e30_0, v0x192a030_0, v0x192a0b0_0, v0x192a130_0, v0x192a3b0_0, v0x192a430_0, v0x192a230_0, v0x1929f30_0; + %vpi_call 2 413 "$display", "%b | %b | %b - NOR | %b | 0000 | %b | %b | %b | %b", v0x1bd6330_0, v0x1bd6530_0, v0x1bd65b0_0, v0x1bd6630_0, v0x1bd68b0_0, v0x1bd6930_0, v0x1bd6730_0, v0x1bd6430_0; %movi 8, 11, 4; - %set/v v0x1929e30_0, 8, 4; + %set/v v0x1bd6330_0, 8, 4; %movi 8, 11, 4; - %set/v v0x192a030_0, 8, 4; + %set/v v0x1bd6530_0, 8, 4; %movi 8, 2, 3; - %set/v v0x192a0b0_0, 8, 3; + %set/v v0x1bd65b0_0, 8, 3; %delay 1000000, 0; - %vpi_call 2 413 "$display", "%b | %b | %b - XOR | %b | 0000 | %b | %b | %b | %b", v0x1929e30_0, v0x192a030_0, v0x192a0b0_0, v0x192a130_0, v0x192a3b0_0, v0x192a430_0, v0x192a230_0, v0x1929f30_0; + %vpi_call 2 416 "$display", "%b | %b | %b - XOR | %b | 0000 | %b | %b | %b | %b", v0x1bd6330_0, v0x1bd6530_0, v0x1bd65b0_0, v0x1bd6630_0, v0x1bd68b0_0, v0x1bd6930_0, v0x1bd6730_0, v0x1bd6430_0; %movi 8, 2, 4; - %set/v v0x1929e30_0, 8, 4; + %set/v v0x1bd6330_0, 8, 4; %movi 8, 14, 4; - %set/v v0x192a030_0, 8, 4; - %set/v v0x192a0b0_0, 0, 3; + %set/v v0x1bd6530_0, 8, 4; + %set/v v0x1bd65b0_0, 0, 3; %delay 1000000, 0; - %vpi_call 2 416 "$display", "%b | %b | %b - ADD | %b | 0000 | %b | %b | %b | %b", v0x1929e30_0, v0x192a030_0, v0x192a0b0_0, v0x192a130_0, v0x192a3b0_0, v0x192a430_0, v0x192a230_0, v0x1929f30_0; + %vpi_call 2 419 "$display", "%b | %b | %b - ADD | %b | 0000 | %b | %b | %b | %b", v0x1bd6330_0, v0x1bd6530_0, v0x1bd65b0_0, v0x1bd6630_0, v0x1bd68b0_0, v0x1bd6930_0, v0x1bd6730_0, v0x1bd6430_0; %movi 8, 2, 4; - %set/v v0x1929e30_0, 8, 4; + %set/v v0x1bd6330_0, 8, 4; %movi 8, 2, 4; - %set/v v0x192a030_0, 8, 4; + %set/v v0x1bd6530_0, 8, 4; %movi 8, 1, 3; - %set/v v0x192a0b0_0, 8, 3; + %set/v v0x1bd65b0_0, 8, 3; %delay 1000000, 0; - %vpi_call 2 419 "$display", "%b | %b | %b - SUB | %b | 0000 | %b | %b | %b | %b", v0x1929e30_0, v0x192a030_0, v0x192a0b0_0, v0x192a130_0, v0x192a3b0_0, v0x192a430_0, v0x192a230_0, v0x1929f30_0; - %set/v v0x1929e30_0, 0, 4; - %set/v v0x192a030_0, 0, 4; + %vpi_call 2 422 "$display", "%b | %b | %b - SUB | %b | 0000 | %b | %b | %b | %b", v0x1bd6330_0, v0x1bd6530_0, v0x1bd65b0_0, v0x1bd6630_0, v0x1bd68b0_0, v0x1bd6930_0, v0x1bd6730_0, v0x1bd6430_0; + %set/v v0x1bd6330_0, 0, 4; + %set/v v0x1bd6530_0, 0, 4; %movi 8, 3, 3; - %set/v v0x192a0b0_0, 8, 3; + %set/v v0x1bd65b0_0, 8, 3; %delay 1000000, 0; - %vpi_call 2 423 "$display", "%b | %b | %b - SLT | %b | 0000 | %b | %b | %b | %b", v0x1929e30_0, v0x192a030_0, v0x192a0b0_0, v0x192a130_0, v0x192a3b0_0, v0x192a430_0, v0x192a230_0, v0x1929f30_0; + %vpi_call 2 426 "$display", "%b | %b | %b - SLT | %b | 0000 | %b | %b | %b | %b", v0x1bd6330_0, v0x1bd6530_0, v0x1bd65b0_0, v0x1bd6630_0, v0x1bd68b0_0, v0x1bd6930_0, v0x1bd6730_0, v0x1bd6430_0; %end; .thread T_0; # The file index is used to find the file name in the following table. diff --git a/testing.t.v b/testing.t.v index 7c2f30a..9f0b682 100644 --- a/testing.t.v +++ b/testing.t.v @@ -148,7 +148,7 @@ Bitslice32 superalu(OneBitFinalOut, AddSubSLTSum, carryout, overflow, SLTflag, initial begin $dumpfile("FullALU.vcd"); - $dumpvars() + $dumpvars(); $display("Test 4 Bit Adder Functionality"); // there are too many possibilities even for just a four bit adder/subtractor, which means we need to choose our test cases strategically From 25983a7183f3751b361654a09c96b81f0124507a Mon Sep 17 00:00:00 2001 From: mjakus Date: Tue, 10 Oct 2017 14:42:28 -0400 Subject: [PATCH 19/28] Maybe edits --- alu.v | 8 +- test | 16578 +++++++++++++++++++++++++++++++++++++++++++------- testing.t.v | 12 +- 3 files changed, 14371 insertions(+), 2227 deletions(-) diff --git a/alu.v b/alu.v index 6995192..aa7cf83 100644 --- a/alu.v +++ b/alu.v @@ -158,7 +158,7 @@ input [size-1:0] A, input [size-1:0] B, input[2:0] Command ); - parameter size = 4; // set the parameter size to whatever length you want + parameter size = 32; // set the parameter size to whatever length you want wire AnandB; wire AandB; @@ -181,7 +181,7 @@ input [size-1:0] A, input [size-1:0] B, input[2:0] Command ); - parameter size = 4; // set the parameter size to whatever length you want + parameter size = 32; // set the parameter size to whatever length you want wire AnorB; wire AorB; wire AnandB; @@ -225,7 +225,7 @@ input [size-1:0]carryin // we think this doesn't do anything but don't want to MiddleAddSubSLT attempt2(AddSubSLTSum[0], CarryoutWire[0], subtract[0], A[0], B[0], Command, subtract[0]); genvar i; - parameter size = 4; + parameter size = 32; generate for (i=1; i; -v0x1bd6330_0 .var "A", 3 0; -RS_0x7f6a63aa0be8/0/0 .resolv tri, L_0x1bd7b20, L_0x1bd9210, L_0x1bda750, L_0x1bdbd50; -RS_0x7f6a63aa0be8/0/4 .resolv tri, L_0x1bedc60, L_0x1bef080, L_0x1bf0480, L_0x1bf1a60; -RS_0x7f6a63aa0be8 .resolv tri, RS_0x7f6a63aa0be8/0/0, RS_0x7f6a63aa0be8/0/4, C4, C4; -v0x1bd63b0_0 .net8 "AddSubSLTSum", 3 0, RS_0x7f6a63aa0be8; 8 drivers -v0x1bd6430_0 .net "AllZeros", 0 0, L_0x1bfd2b0; 1 drivers -RS_0x7f6a63a9fe38/0/0 .resolv tri, L_0x1bddd00, L_0x1bde7b0, L_0x1bdf220, L_0x1bdfc80; -RS_0x7f6a63a9fe38/0/4 .resolv tri, L_0x1bf3890, L_0x1bf4300, L_0x1bf4d70, L_0x1bf58d0; -RS_0x7f6a63a9fe38 .resolv tri, RS_0x7f6a63a9fe38/0/0, RS_0x7f6a63a9fe38/0/4, C4, C4; -v0x1bd64b0_0 .net8 "AndNandOut", 3 0, RS_0x7f6a63a9fe38; 8 drivers -v0x1bd6530_0 .var "B", 3 0; -v0x1bd65b0_0 .var "Command", 2 0; -RS_0x7f6a63aa1068 .resolv tri, L_0x1be6d00, L_0x1be9a90, L_0x1bec6c0, L_0x1bfc720; -v0x1bd6630_0 .net8 "OneBitFinalOut", 3 0, RS_0x7f6a63aa1068; 4 drivers -RS_0x7f6a63a9f748/0/0 .resolv tri, L_0x1be0fd0, L_0x1be2530, L_0x1be3830, L_0x1be48e0; -RS_0x7f6a63a9f748/0/4 .resolv tri, L_0x1bf6c20, L_0x1bf7f20, L_0x1bf9220, L_0x1bfa510; -RS_0x7f6a63a9f748 .resolv tri, RS_0x7f6a63a9f748/0/0, RS_0x7f6a63a9f748/0/4, C4, C4; -v0x1bd66b0_0 .net8 "OrNorXorOut", 3 0, RS_0x7f6a63a9f748; 8 drivers -RS_0x7f6a63aa0ca8 .resolv tri, L_0x1bdd380, L_0x1bf2f30, C4, C4; -v0x1bd6730_0 .net8 "SLTflag", 0 0, RS_0x7f6a63aa0ca8; 2 drivers -RS_0x7f6a63aa1098 .resolv tri, L_0x1be71b0, L_0x1be9f60, L_0x1bec800, L_0x1bfc9e0; -v0x1bd67b0_0 .net8 "ZeroFlag", 3 0, RS_0x7f6a63aa1098; 4 drivers -v0x1bd6830_0 .var "carryin", 3 0; -RS_0x7f6a63aa0ee8 .resolv tri, L_0x1bd7e00, L_0x1bf1de0, C4, C4; -v0x1bd68b0_0 .net8 "carryout", 0 0, RS_0x7f6a63aa0ee8; 2 drivers -RS_0x7f6a63aa0f78 .resolv tri, L_0x1bdc650, L_0x1bf2250, C4, C4; -v0x1bd6930_0 .net8 "overflow", 0 0, RS_0x7f6a63aa0f78; 2 drivers -RS_0x7f6a63aa0fa8/0/0 .resolv tri, L_0x1bd7d60, L_0x1bd9440, L_0x1bda9b0, L_0x1bdada0; -RS_0x7f6a63aa0fa8/0/4 .resolv tri, L_0x1bede40, L_0x1bef2b0, L_0x1bf06e0, L_0x1bf0ad0; -RS_0x7f6a63aa0fa8 .resolv tri, RS_0x7f6a63aa0fa8/0/0, RS_0x7f6a63aa0fa8/0/4, C4, C4; -v0x1bd69b0_0 .net8 "subtract", 3 0, RS_0x7f6a63aa0fa8; 8 drivers -S_0x1bd0bc0 .scope module, "trial" "AddSubSLT32" 2 141, 3 205, S_0x1b740f0; - .timescale -9 -12; -P_0x1bd0cb8 .param/l "size" 3 228, +C4<0100>; -L_0x1bd7e00/d .functor OR 1, L_0x1bdc4a0, C4<0>, C4<0>, C4<0>; -L_0x1bd7e00 .delay (20000,20000,20000) L_0x1bd7e00/d; -L_0x1bdc650/d .functor XOR 1, RS_0x7f6a63aa0ee8, L_0x1bdc780, C4<0>, C4<0>; -L_0x1bdc650 .delay (40000,40000,40000) L_0x1bdc650/d; -L_0x1bdc3d0/d .functor AND 1, L_0x1bdc950, L_0x1bdc9f0, C4<1>, C4<1>; -L_0x1bdc3d0 .delay (20000,20000,20000) L_0x1bdc3d0/d; -L_0x1bdc820/d .functor NOT 1, RS_0x7f6a63aa0f78, C4<0>, C4<0>, C4<0>; -L_0x1bdc820 .delay (10000,10000,10000) L_0x1bdc820/d; -L_0x1bdcc20/d .functor NOT 1, L_0x1bdcc80, C4<0>, C4<0>, C4<0>; -L_0x1bdcc20 .delay (10000,10000,10000) L_0x1bdcc20/d; -L_0x1bd7bc0/d .functor AND 1, L_0x1bdc820, L_0x1bdcf50, C4<1>, C4<1>; -L_0x1bd7bc0 .delay (20000,20000,20000) L_0x1bd7bc0/d; -L_0x1bdcae0/d .functor AND 1, RS_0x7f6a63aa0f78, L_0x1bdcc20, C4<1>, C4<1>; -L_0x1bdcae0 .delay (20000,20000,20000) L_0x1bdcae0/d; -L_0x1bdd140/d .functor AND 1, L_0x1bd7bc0, L_0x1bdc3d0, C4<1>, C4<1>; -L_0x1bdd140 .delay (20000,20000,20000) L_0x1bdd140/d; -L_0x1bdd280/d .functor AND 1, L_0x1bdcae0, L_0x1bdc3d0, C4<1>, C4<1>; -L_0x1bdd280 .delay (20000,20000,20000) L_0x1bdd280/d; -L_0x1bdd380/d .functor OR 1, L_0x1bdd140, L_0x1bdd280, C4<0>, C4<0>; -L_0x1bdd380 .delay (20000,20000,20000) L_0x1bdd380/d; -v0x1bd5250_0 .net "A", 3 0, v0x1bd6330_0; 1 drivers -v0x1bd52f0_0 .alias "AddSubSLTSum", 3 0, v0x1bd63b0_0; -v0x1bd5370_0 .net "B", 3 0, v0x1bd6530_0; 1 drivers -RS_0x7f6a63aa3348 .resolv tri, L_0x1bd7c70, L_0x1bd9300, L_0x1bda840, L_0x1bdbe40; -v0x1bd53f0_0 .net8 "CarryoutWire", 3 0, RS_0x7f6a63aa3348; 4 drivers -v0x1bd5470_0 .net "Command", 2 0, v0x1bd65b0_0; 1 drivers -v0x1bd54f0_0 .net "Res0OF1", 0 0, L_0x1bdcae0; 1 drivers -v0x1bd5590_0 .net "Res1OF0", 0 0, L_0x1bd7bc0; 1 drivers -v0x1bd5630_0 .alias "SLTflag", 0 0, v0x1bd6730_0; -v0x1bd5750_0 .net "SLTflag0", 0 0, L_0x1bdd140; 1 drivers -v0x1bd57f0_0 .net "SLTflag1", 0 0, L_0x1bdd280; 1 drivers -v0x1bd5890_0 .net "SLTon", 0 0, L_0x1bdc3d0; 1 drivers -v0x1bd5930_0 .net *"_s40", 0 0, L_0x1bdc4a0; 1 drivers -v0x1bd59d0_0 .net/s *"_s41", 0 0, C4<0>; 1 drivers -v0x1bd5a70_0 .net *"_s44", 0 0, L_0x1bdc780; 1 drivers -v0x1bd5b90_0 .net *"_s46", 0 0, L_0x1bdc950; 1 drivers -v0x1bd5c30_0 .net *"_s48", 0 0, L_0x1bdc9f0; 1 drivers -v0x1bd5af0_0 .net *"_s50", 0 0, L_0x1bdcc80; 1 drivers -v0x1bd5d80_0 .net *"_s52", 0 0, L_0x1bdcf50; 1 drivers -v0x1bd5ea0_0 .net "carryin", 3 0, v0x1bd6830_0; 1 drivers -v0x1bd5f20_0 .alias "carryout", 0 0, v0x1bd68b0_0; -v0x1bd5e00_0 .net "nAddSubSLTSum", 0 0, L_0x1bdcc20; 1 drivers -v0x1bd6050_0 .net "nOF", 0 0, L_0x1bdc820; 1 drivers -v0x1bd5fa0_0 .alias "overflow", 0 0, v0x1bd6930_0; -v0x1bd61e0_0 .alias "subtract", 3 0, v0x1bd69b0_0; -L_0x1bd7b20 .part/pv L_0x1bd7690, 1, 1, 4; -L_0x1bd7c70 .part/pv L_0x1bd79e0, 1, 1, 4; -L_0x1bd7d60 .part/pv L_0x1bc9bc0, 1, 1, 4; -L_0x1bd7e90 .part v0x1bd6330_0, 1, 1; -L_0x1bd8040 .part v0x1bd6530_0, 1, 1; -L_0x1bd81f0 .part RS_0x7f6a63aa3348, 0, 1; -L_0x1bd9210 .part/pv L_0x1bd8d40, 2, 1, 4; -L_0x1bd9300 .part/pv L_0x1bd90b0, 2, 1, 4; -L_0x1bd9440 .part/pv L_0x1bd8a70, 2, 1, 4; -L_0x1bd9530 .part v0x1bd6330_0, 2, 1; -L_0x1bd9630 .part v0x1bd6530_0, 2, 1; -L_0x1bd9760 .part RS_0x7f6a63aa3348, 1, 1; -L_0x1bda750 .part/pv L_0x1bda2a0, 3, 1, 4; -L_0x1bda840 .part/pv L_0x1bda5f0, 3, 1, 4; -L_0x1bda9b0 .part/pv L_0x1bd9fd0, 3, 1, 4; -L_0x1bdaaa0 .part v0x1bd6330_0, 3, 1; -L_0x1bdabd0 .part v0x1bd6530_0, 3, 1; -L_0x1bdad00 .part RS_0x7f6a63aa3348, 2, 1; -L_0x1bdbd50 .part/pv L_0x1bdb8a0, 0, 1, 4; -L_0x1bdbe40 .part/pv L_0x1bdbbf0, 0, 1, 4; -L_0x1bdada0 .part/pv L_0x1bdb5d0, 0, 1, 4; -L_0x1bdc030 .part v0x1bd6330_0, 0, 1; -L_0x1bdbf30 .part v0x1bd6530_0, 0, 1; -L_0x1bdc220 .part RS_0x7f6a63aa0fa8, 0, 1; -L_0x1bdc4a0 .part RS_0x7f6a63aa3348, 3, 1; -L_0x1bdc780 .part RS_0x7f6a63aa3348, 2, 1; -L_0x1bdc950 .part v0x1bd65b0_0, 1, 1; -L_0x1bdc9f0 .part RS_0x7f6a63aa0fa8, 0, 1; -L_0x1bdcc80 .part RS_0x7f6a63aa0be8, 3, 1; -L_0x1bdcf50 .part RS_0x7f6a63aa0be8, 3, 1; -S_0x1bd4240 .scope module, "attempt2" "MiddleAddSubSLT" 3 225, 3 89, S_0x1bd0bc0; - .timescale -9 -12; -L_0x1bdab40/d .functor NOT 1, L_0x1bdbf30, C4<0>, C4<0>, C4<0>; -L_0x1bdab40 .delay (10000,10000,10000) L_0x1bdab40/d; -L_0x1bdb470/d .functor NOT 1, L_0x1bdb530, C4<0>, C4<0>, C4<0>; -L_0x1bdb470 .delay (10000,10000,10000) L_0x1bdb470/d; -L_0x1bdb5d0/d .functor AND 1, L_0x1bdb710, L_0x1bdb470, C4<1>, C4<1>; -L_0x1bdb5d0 .delay (20000,20000,20000) L_0x1bdb5d0/d; -L_0x1bdb7b0/d .functor XOR 1, L_0x1bdc030, L_0x1bdb200, C4<0>, C4<0>; -L_0x1bdb7b0 .delay (40000,40000,40000) L_0x1bdb7b0/d; -L_0x1bdb8a0/d .functor XOR 1, L_0x1bdb7b0, L_0x1bdc220, C4<0>, C4<0>; -L_0x1bdb8a0 .delay (40000,40000,40000) L_0x1bdb8a0/d; -L_0x1bdb990/d .functor AND 1, L_0x1bdc030, L_0x1bdb200, C4<1>, C4<1>; -L_0x1bdb990 .delay (20000,20000,20000) L_0x1bdb990/d; -L_0x1bdbb00/d .functor AND 1, L_0x1bdb7b0, L_0x1bdc220, C4<1>, C4<1>; -L_0x1bdbb00 .delay (20000,20000,20000) L_0x1bdbb00/d; -L_0x1bdbbf0/d .functor OR 1, L_0x1bdb990, L_0x1bdbb00, C4<0>, C4<0>; -L_0x1bdbbf0 .delay (20000,20000,20000) L_0x1bdbbf0/d; -v0x1bd48b0_0 .net "A", 0 0, L_0x1bdc030; 1 drivers -v0x1bd4970_0 .net "AandB", 0 0, L_0x1bdb990; 1 drivers -v0x1bd4a10_0 .net "AddSubSLTSum", 0 0, L_0x1bdb8a0; 1 drivers -v0x1bd4ab0_0 .net "AxorB", 0 0, L_0x1bdb7b0; 1 drivers -v0x1bd4b30_0 .net "B", 0 0, L_0x1bdbf30; 1 drivers -v0x1bd4be0_0 .net "BornB", 0 0, L_0x1bdb200; 1 drivers -v0x1bd4ca0_0 .net "CINandAxorB", 0 0, L_0x1bdbb00; 1 drivers -v0x1bd4d20_0 .alias "Command", 2 0, v0x1bd5470_0; -v0x1bd4da0_0 .net *"_s3", 0 0, L_0x1bdb530; 1 drivers -v0x1bd4e20_0 .net *"_s5", 0 0, L_0x1bdb710; 1 drivers -v0x1bd4ec0_0 .net "carryin", 0 0, L_0x1bdc220; 1 drivers -v0x1bd4f60_0 .net "carryout", 0 0, L_0x1bdbbf0; 1 drivers -v0x1bd5000_0 .net "nB", 0 0, L_0x1bdab40; 1 drivers -v0x1bd50b0_0 .net "nCmd2", 0 0, L_0x1bdb470; 1 drivers -v0x1bd51b0_0 .net "subtract", 0 0, L_0x1bdb5d0; 1 drivers -L_0x1bdb3d0 .part v0x1bd65b0_0, 0, 1; -L_0x1bdb530 .part v0x1bd65b0_0, 2, 1; -L_0x1bdb710 .part v0x1bd65b0_0, 0, 1; -S_0x1bd4330 .scope module, "mux0" "TwoInMux" 3 105, 3 8, S_0x1bd4240; - .timescale -9 -12; -L_0x1bdaf20/d .functor NOT 1, L_0x1bdb3d0, C4<0>, C4<0>, C4<0>; -L_0x1bdaf20 .delay (10000,10000,10000) L_0x1bdaf20/d; -L_0x1bdafe0/d .functor AND 1, L_0x1bdbf30, L_0x1bdaf20, C4<1>, C4<1>; -L_0x1bdafe0 .delay (20000,20000,20000) L_0x1bdafe0/d; -L_0x1bdb0f0/d .functor AND 1, L_0x1bdab40, L_0x1bdb3d0, C4<1>, C4<1>; -L_0x1bdb0f0 .delay (20000,20000,20000) L_0x1bdb0f0/d; -L_0x1bdb200/d .functor OR 1, L_0x1bdafe0, L_0x1bdb0f0, C4<0>, C4<0>; -L_0x1bdb200 .delay (20000,20000,20000) L_0x1bdb200/d; -v0x1bd4420_0 .net "S", 0 0, L_0x1bdb3d0; 1 drivers -v0x1bd44e0_0 .alias "in0", 0 0, v0x1bd4b30_0; -v0x1bd4580_0 .alias "in1", 0 0, v0x1bd5000_0; -v0x1bd4620_0 .net "nS", 0 0, L_0x1bdaf20; 1 drivers -v0x1bd46d0_0 .net "out0", 0 0, L_0x1bdafe0; 1 drivers -v0x1bd4770_0 .net "out1", 0 0, L_0x1bdb0f0; 1 drivers -v0x1bd4810_0 .alias "outfinal", 0 0, v0x1bd4be0_0; -S_0x1bd30a0 .scope generate, "addbits[1]" "addbits[1]" 3 230, 3 230, S_0x1bd0bc0; - .timescale -9 -12; -P_0x1bd2ab8 .param/l "i" 3 230, +C4<01>; -S_0x1bd3210 .scope module, "attempt" "MiddleAddSubSLT" 3 232, 3 89, S_0x1bd30a0; - .timescale -9 -12; -L_0x1bd1af0/d .functor NOT 1, L_0x1bd8040, C4<0>, C4<0>, C4<0>; -L_0x1bd1af0 .delay (10000,10000,10000) L_0x1bd1af0/d; -L_0x1bd6120/d .functor NOT 1, L_0x1bc9b20, C4<0>, C4<0>, C4<0>; -L_0x1bd6120 .delay (10000,10000,10000) L_0x1bd6120/d; -L_0x1bc9bc0/d .functor AND 1, L_0x1bd7500, L_0x1bd6120, C4<1>, C4<1>; -L_0x1bc9bc0 .delay (20000,20000,20000) L_0x1bc9bc0/d; -L_0x1bd75a0/d .functor XOR 1, L_0x1bd7e90, L_0x1bd6e80, C4<0>, C4<0>; -L_0x1bd75a0 .delay (40000,40000,40000) L_0x1bd75a0/d; -L_0x1bd7690/d .functor XOR 1, L_0x1bd75a0, L_0x1bd81f0, C4<0>, C4<0>; -L_0x1bd7690 .delay (40000,40000,40000) L_0x1bd7690/d; -L_0x1bd7780/d .functor AND 1, L_0x1bd7e90, L_0x1bd6e80, C4<1>, C4<1>; -L_0x1bd7780 .delay (20000,20000,20000) L_0x1bd7780/d; -L_0x1bd78f0/d .functor AND 1, L_0x1bd75a0, L_0x1bd81f0, C4<1>, C4<1>; -L_0x1bd78f0 .delay (20000,20000,20000) L_0x1bd78f0/d; -L_0x1bd79e0/d .functor OR 1, L_0x1bd7780, L_0x1bd78f0, C4<0>, C4<0>; -L_0x1bd79e0 .delay (20000,20000,20000) L_0x1bd79e0/d; -v0x1bd38a0_0 .net "A", 0 0, L_0x1bd7e90; 1 drivers -v0x1bd3960_0 .net "AandB", 0 0, L_0x1bd7780; 1 drivers -v0x1bd3a00_0 .net "AddSubSLTSum", 0 0, L_0x1bd7690; 1 drivers -v0x1bd3aa0_0 .net "AxorB", 0 0, L_0x1bd75a0; 1 drivers -v0x1bd3b20_0 .net "B", 0 0, L_0x1bd8040; 1 drivers -v0x1bd3bd0_0 .net "BornB", 0 0, L_0x1bd6e80; 1 drivers -v0x1bd3c90_0 .net "CINandAxorB", 0 0, L_0x1bd78f0; 1 drivers -v0x1bd3d10_0 .alias "Command", 2 0, v0x1bd5470_0; -v0x1bd3d90_0 .net *"_s3", 0 0, L_0x1bc9b20; 1 drivers -v0x1bd3e10_0 .net *"_s5", 0 0, L_0x1bd7500; 1 drivers -v0x1bd3eb0_0 .net "carryin", 0 0, L_0x1bd81f0; 1 drivers -v0x1bd3f50_0 .net "carryout", 0 0, L_0x1bd79e0; 1 drivers -v0x1bd3ff0_0 .net "nB", 0 0, L_0x1bd1af0; 1 drivers -v0x1bd40a0_0 .net "nCmd2", 0 0, L_0x1bd6120; 1 drivers -v0x1bd41a0_0 .net "subtract", 0 0, L_0x1bc9bc0; 1 drivers -L_0x1bd7050 .part v0x1bd65b0_0, 0, 1; -L_0x1bc9b20 .part v0x1bd65b0_0, 2, 1; -L_0x1bd7500 .part v0x1bd65b0_0, 0, 1; -S_0x1bd3300 .scope module, "mux0" "TwoInMux" 3 105, 3 8, S_0x1bd3210; - .timescale -9 -12; -L_0x1bd6ba0/d .functor NOT 1, L_0x1bd7050, C4<0>, C4<0>, C4<0>; -L_0x1bd6ba0 .delay (10000,10000,10000) L_0x1bd6ba0/d; -L_0x1bd6c60/d .functor AND 1, L_0x1bd8040, L_0x1bd6ba0, C4<1>, C4<1>; -L_0x1bd6c60 .delay (20000,20000,20000) L_0x1bd6c60/d; -L_0x1bd6d70/d .functor AND 1, L_0x1bd1af0, L_0x1bd7050, C4<1>, C4<1>; -L_0x1bd6d70 .delay (20000,20000,20000) L_0x1bd6d70/d; -L_0x1bd6e80/d .functor OR 1, L_0x1bd6c60, L_0x1bd6d70, C4<0>, C4<0>; -L_0x1bd6e80 .delay (20000,20000,20000) L_0x1bd6e80/d; -v0x1bd33f0_0 .net "S", 0 0, L_0x1bd7050; 1 drivers -v0x1bd3490_0 .alias "in0", 0 0, v0x1bd3b20_0; -v0x1bd3530_0 .alias "in1", 0 0, v0x1bd3ff0_0; -v0x1bd35d0_0 .net "nS", 0 0, L_0x1bd6ba0; 1 drivers -v0x1bd3680_0 .net "out0", 0 0, L_0x1bd6c60; 1 drivers -v0x1bd3720_0 .net "out1", 0 0, L_0x1bd6d70; 1 drivers -v0x1bd3800_0 .alias "outfinal", 0 0, v0x1bd3bd0_0; -S_0x1bd1f00 .scope generate, "addbits[2]" "addbits[2]" 3 230, 3 230, S_0x1bd0bc0; - .timescale -9 -12; -P_0x1bd18b8 .param/l "i" 3 230, +C4<010>; -S_0x1bd2070 .scope module, "attempt" "MiddleAddSubSLT" 3 232, 3 89, S_0x1bd1f00; - .timescale -9 -12; -L_0x1bcd970/d .functor NOT 1, L_0x1bd9630, C4<0>, C4<0>, C4<0>; -L_0x1bcd970 .delay (10000,10000,10000) L_0x1bcd970/d; -L_0x1bd8910/d .functor NOT 1, L_0x1bd89d0, C4<0>, C4<0>, C4<0>; -L_0x1bd8910 .delay (10000,10000,10000) L_0x1bd8910/d; -L_0x1bd8a70/d .functor AND 1, L_0x1bd8bb0, L_0x1bd8910, C4<1>, C4<1>; -L_0x1bd8a70 .delay (20000,20000,20000) L_0x1bd8a70/d; -L_0x1bd8c50/d .functor XOR 1, L_0x1bd9530, L_0x1bd86a0, C4<0>, C4<0>; -L_0x1bd8c50 .delay (40000,40000,40000) L_0x1bd8c50/d; -L_0x1bd8d40/d .functor XOR 1, L_0x1bd8c50, L_0x1bd9760, C4<0>, C4<0>; -L_0x1bd8d40 .delay (40000,40000,40000) L_0x1bd8d40/d; -L_0x1bd8e30/d .functor AND 1, L_0x1bd9530, L_0x1bd86a0, C4<1>, C4<1>; -L_0x1bd8e30 .delay (20000,20000,20000) L_0x1bd8e30/d; -L_0x1bd8fa0/d .functor AND 1, L_0x1bd8c50, L_0x1bd9760, C4<1>, C4<1>; -L_0x1bd8fa0 .delay (20000,20000,20000) L_0x1bd8fa0/d; -L_0x1bd90b0/d .functor OR 1, L_0x1bd8e30, L_0x1bd8fa0, C4<0>, C4<0>; -L_0x1bd90b0 .delay (20000,20000,20000) L_0x1bd90b0/d; -v0x1bd2700_0 .net "A", 0 0, L_0x1bd9530; 1 drivers -v0x1bd27c0_0 .net "AandB", 0 0, L_0x1bd8e30; 1 drivers -v0x1bd2860_0 .net "AddSubSLTSum", 0 0, L_0x1bd8d40; 1 drivers -v0x1bd2900_0 .net "AxorB", 0 0, L_0x1bd8c50; 1 drivers -v0x1bd2980_0 .net "B", 0 0, L_0x1bd9630; 1 drivers -v0x1bd2a30_0 .net "BornB", 0 0, L_0x1bd86a0; 1 drivers -v0x1bd2af0_0 .net "CINandAxorB", 0 0, L_0x1bd8fa0; 1 drivers -v0x1bd2b70_0 .alias "Command", 2 0, v0x1bd5470_0; -v0x1bd2bf0_0 .net *"_s3", 0 0, L_0x1bd89d0; 1 drivers -v0x1bd2c70_0 .net *"_s5", 0 0, L_0x1bd8bb0; 1 drivers -v0x1bd2d10_0 .net "carryin", 0 0, L_0x1bd9760; 1 drivers -v0x1bd2db0_0 .net "carryout", 0 0, L_0x1bd90b0; 1 drivers -v0x1bd2e50_0 .net "nB", 0 0, L_0x1bcd970; 1 drivers -v0x1bd2f00_0 .net "nCmd2", 0 0, L_0x1bd8910; 1 drivers -v0x1bd3000_0 .net "subtract", 0 0, L_0x1bd8a70; 1 drivers -L_0x1bd8870 .part v0x1bd65b0_0, 0, 1; -L_0x1bd89d0 .part v0x1bd65b0_0, 2, 1; -L_0x1bd8bb0 .part v0x1bd65b0_0, 0, 1; -S_0x1bd2160 .scope module, "mux0" "TwoInMux" 3 105, 3 8, S_0x1bd2070; - .timescale -9 -12; -L_0x1bd83c0/d .functor NOT 1, L_0x1bd8870, C4<0>, C4<0>, C4<0>; -L_0x1bd83c0 .delay (10000,10000,10000) L_0x1bd83c0/d; -L_0x1bd8480/d .functor AND 1, L_0x1bd9630, L_0x1bd83c0, C4<1>, C4<1>; -L_0x1bd8480 .delay (20000,20000,20000) L_0x1bd8480/d; -L_0x1bd8590/d .functor AND 1, L_0x1bcd970, L_0x1bd8870, C4<1>, C4<1>; -L_0x1bd8590 .delay (20000,20000,20000) L_0x1bd8590/d; -L_0x1bd86a0/d .functor OR 1, L_0x1bd8480, L_0x1bd8590, C4<0>, C4<0>; -L_0x1bd86a0 .delay (20000,20000,20000) L_0x1bd86a0/d; -v0x1bd2250_0 .net "S", 0 0, L_0x1bd8870; 1 drivers -v0x1bd22f0_0 .alias "in0", 0 0, v0x1bd2980_0; -v0x1bd2390_0 .alias "in1", 0 0, v0x1bd2e50_0; -v0x1bd2430_0 .net "nS", 0 0, L_0x1bd83c0; 1 drivers -v0x1bd24e0_0 .net "out0", 0 0, L_0x1bd8480; 1 drivers -v0x1bd2580_0 .net "out1", 0 0, L_0x1bd8590; 1 drivers -v0x1bd2660_0 .alias "outfinal", 0 0, v0x1bd2a30_0; -S_0x1bd0d30 .scope generate, "addbits[3]" "addbits[3]" 3 230, 3 230, S_0x1bd0bc0; - .timescale -9 -12; -P_0x1bd0e28 .param/l "i" 3 230, +C4<011>; -S_0x1bd0ea0 .scope module, "attempt" "MiddleAddSubSLT" 3 232, 3 89, S_0x1bd0d30; - .timescale -9 -12; -L_0x1bd95d0/d .functor NOT 1, L_0x1bdabd0, C4<0>, C4<0>, C4<0>; -L_0x1bd95d0 .delay (10000,10000,10000) L_0x1bd95d0/d; -L_0x1bd9e70/d .functor NOT 1, L_0x1bd9f30, C4<0>, C4<0>, C4<0>; -L_0x1bd9e70 .delay (10000,10000,10000) L_0x1bd9e70/d; -L_0x1bd9fd0/d .functor AND 1, L_0x1bda110, L_0x1bd9e70, C4<1>, C4<1>; -L_0x1bd9fd0 .delay (20000,20000,20000) L_0x1bd9fd0/d; -L_0x1bda1b0/d .functor XOR 1, L_0x1bdaaa0, L_0x1bd9c00, C4<0>, C4<0>; -L_0x1bda1b0 .delay (40000,40000,40000) L_0x1bda1b0/d; -L_0x1bda2a0/d .functor XOR 1, L_0x1bda1b0, L_0x1bdad00, C4<0>, C4<0>; -L_0x1bda2a0 .delay (40000,40000,40000) L_0x1bda2a0/d; -L_0x1bda390/d .functor AND 1, L_0x1bdaaa0, L_0x1bd9c00, C4<1>, C4<1>; -L_0x1bda390 .delay (20000,20000,20000) L_0x1bda390/d; -L_0x1bda500/d .functor AND 1, L_0x1bda1b0, L_0x1bdad00, C4<1>, C4<1>; -L_0x1bda500 .delay (20000,20000,20000) L_0x1bda500/d; -L_0x1bda5f0/d .functor OR 1, L_0x1bda390, L_0x1bda500, C4<0>, C4<0>; -L_0x1bda5f0 .delay (20000,20000,20000) L_0x1bda5f0/d; -v0x1bd1500_0 .net "A", 0 0, L_0x1bdaaa0; 1 drivers -v0x1bd15c0_0 .net "AandB", 0 0, L_0x1bda390; 1 drivers -v0x1bd1660_0 .net "AddSubSLTSum", 0 0, L_0x1bda2a0; 1 drivers -v0x1bd1700_0 .net "AxorB", 0 0, L_0x1bda1b0; 1 drivers -v0x1bd1780_0 .net "B", 0 0, L_0x1bdabd0; 1 drivers -v0x1bd1830_0 .net "BornB", 0 0, L_0x1bd9c00; 1 drivers -v0x1bd18f0_0 .net "CINandAxorB", 0 0, L_0x1bda500; 1 drivers -v0x1bd1970_0 .alias "Command", 2 0, v0x1bd5470_0; -v0x1bd19f0_0 .net *"_s3", 0 0, L_0x1bd9f30; 1 drivers -v0x1bd1a70_0 .net *"_s5", 0 0, L_0x1bda110; 1 drivers -v0x1bd1b70_0 .net "carryin", 0 0, L_0x1bdad00; 1 drivers -v0x1bd1c10_0 .net "carryout", 0 0, L_0x1bda5f0; 1 drivers -v0x1bd1cb0_0 .net "nB", 0 0, L_0x1bd95d0; 1 drivers -v0x1bd1d60_0 .net "nCmd2", 0 0, L_0x1bd9e70; 1 drivers -v0x1bd1e60_0 .net "subtract", 0 0, L_0x1bd9fd0; 1 drivers -L_0x1bd9dd0 .part v0x1bd65b0_0, 0, 1; -L_0x1bd9f30 .part v0x1bd65b0_0, 2, 1; -L_0x1bda110 .part v0x1bd65b0_0, 0, 1; -S_0x1bd0f90 .scope module, "mux0" "TwoInMux" 3 105, 3 8, S_0x1bd0ea0; - .timescale -9 -12; -L_0x1bd9960/d .functor NOT 1, L_0x1bd9dd0, C4<0>, C4<0>, C4<0>; -L_0x1bd9960 .delay (10000,10000,10000) L_0x1bd9960/d; -L_0x1bd99e0/d .functor AND 1, L_0x1bdabd0, L_0x1bd9960, C4<1>, C4<1>; -L_0x1bd99e0 .delay (20000,20000,20000) L_0x1bd99e0/d; -L_0x1bd9af0/d .functor AND 1, L_0x1bd95d0, L_0x1bd9dd0, C4<1>, C4<1>; -L_0x1bd9af0 .delay (20000,20000,20000) L_0x1bd9af0/d; -L_0x1bd9c00/d .functor OR 1, L_0x1bd99e0, L_0x1bd9af0, C4<0>, C4<0>; -L_0x1bd9c00 .delay (20000,20000,20000) L_0x1bd9c00/d; -v0x1bd1080_0 .net "S", 0 0, L_0x1bd9dd0; 1 drivers -v0x1bd1120_0 .alias "in0", 0 0, v0x1bd1780_0; -v0x1bd11c0_0 .alias "in1", 0 0, v0x1bd1cb0_0; -v0x1bd1260_0 .net "nS", 0 0, L_0x1bd9960; 1 drivers -v0x1bd12e0_0 .net "out0", 0 0, L_0x1bd99e0; 1 drivers -v0x1bd1380_0 .net "out1", 0 0, L_0x1bd9af0; 1 drivers -v0x1bd1460_0 .alias "outfinal", 0 0, v0x1bd1830_0; -S_0x1bcdb00 .scope module, "trial1" "AndNand32" 2 143, 3 154, S_0x1b740f0; - .timescale -9 -12; -P_0x1bcd4f8 .param/l "size" 3 161, +C4<0100>; -v0x1bd09c0_0 .alias "A", 3 0, v0x1bd5250_0; -v0x1bd0a40_0 .alias "AndNandOut", 3 0, v0x1bd64b0_0; -v0x1bd0ac0_0 .alias "B", 3 0, v0x1bd5370_0; -v0x1bd0b40_0 .alias "Command", 2 0, v0x1bd5470_0; -L_0x1bddd00 .part/pv L_0x1bdda90, 1, 1, 4; -L_0x1bdde50 .part v0x1bd6330_0, 1, 1; -L_0x1bddef0 .part v0x1bd6530_0, 1, 1; -L_0x1bde7b0 .part/pv L_0x1bde540, 2, 1, 4; -L_0x1bde850 .part v0x1bd6330_0, 2, 1; -L_0x1bde8f0 .part v0x1bd6530_0, 2, 1; -L_0x1bdf220 .part/pv L_0x1bdefb0, 3, 1, 4; -L_0x1bdf2c0 .part v0x1bd6330_0, 3, 1; -L_0x1bdf3b0 .part v0x1bd6530_0, 3, 1; -L_0x1bdfc80 .part/pv L_0x1bdfa10, 0, 1, 4; -L_0x1bdfd80 .part v0x1bd6330_0, 0, 1; -L_0x1bdfe20 .part v0x1bd6530_0, 0, 1; -S_0x1bcff90 .scope module, "attempt2" "AndNand" 3 165, 3 48, S_0x1bcdb00; - .timescale -9 -12; -L_0x1bdf4a0/d .functor NAND 1, L_0x1bdfd80, L_0x1bdfe20, C4<1>, C4<1>; -L_0x1bdf4a0 .delay (10000,10000,10000) L_0x1bdf4a0/d; -L_0x1bdf5c0/d .functor NOT 1, L_0x1bdf4a0, C4<0>, C4<0>, C4<0>; -L_0x1bdf5c0 .delay (10000,10000,10000) L_0x1bdf5c0/d; -v0x1bd05b0_0 .net "A", 0 0, L_0x1bdfd80; 1 drivers -v0x1bd0670_0 .net "AandB", 0 0, L_0x1bdf5c0; 1 drivers -v0x1bd06f0_0 .net "AnandB", 0 0, L_0x1bdf4a0; 1 drivers -v0x1bd07a0_0 .net "AndNandOut", 0 0, L_0x1bdfa10; 1 drivers -v0x1bd0880_0 .net "B", 0 0, L_0x1bdfe20; 1 drivers -v0x1bd0900_0 .alias "Command", 2 0, v0x1bd5470_0; -L_0x1bdfbe0 .part v0x1bd65b0_0, 0, 1; -S_0x1bd0080 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0x1bcff90; - .timescale -9 -12; -L_0x1bdf6f0/d .functor NOT 1, L_0x1bdfbe0, C4<0>, C4<0>, C4<0>; -L_0x1bdf6f0 .delay (10000,10000,10000) L_0x1bdf6f0/d; -L_0x1bdf7b0/d .functor AND 1, L_0x1bdf5c0, L_0x1bdf6f0, C4<1>, C4<1>; -L_0x1bdf7b0 .delay (20000,20000,20000) L_0x1bdf7b0/d; -L_0x1bdf8c0/d .functor AND 1, L_0x1bdf4a0, L_0x1bdfbe0, C4<1>, C4<1>; -L_0x1bdf8c0 .delay (20000,20000,20000) L_0x1bdf8c0/d; -L_0x1bdfa10/d .functor OR 1, L_0x1bdf7b0, L_0x1bdf8c0, C4<0>, C4<0>; -L_0x1bdfa10 .delay (20000,20000,20000) L_0x1bdfa10/d; -v0x1bd0170_0 .net "S", 0 0, L_0x1bdfbe0; 1 drivers -v0x1bd01f0_0 .alias "in0", 0 0, v0x1bd0670_0; -v0x1bd0270_0 .alias "in1", 0 0, v0x1bd06f0_0; -v0x1bd0310_0 .net "nS", 0 0, L_0x1bdf6f0; 1 drivers -v0x1bd0390_0 .net "out0", 0 0, L_0x1bdf7b0; 1 drivers -v0x1bd0430_0 .net "out1", 0 0, L_0x1bdf8c0; 1 drivers -v0x1bd0510_0 .alias "outfinal", 0 0, v0x1bd07a0_0; -S_0x1bcf3d0 .scope generate, "andbits[1]" "andbits[1]" 3 169, 3 169, S_0x1bcdb00; - .timescale -9 -12; -P_0x1bcf4c8 .param/l "i" 3 169, +C4<01>; -S_0x1bcf540 .scope module, "attempt" "AndNand" 3 171, 3 48, S_0x1bcf3d0; - .timescale -9 -12; -L_0x1bdd580/d .functor NAND 1, L_0x1bdde50, L_0x1bddef0, C4<1>, C4<1>; -L_0x1bdd580 .delay (10000,10000,10000) L_0x1bdd580/d; -L_0x1bdd640/d .functor NOT 1, L_0x1bdd580, C4<0>, C4<0>, C4<0>; -L_0x1bdd640 .delay (10000,10000,10000) L_0x1bdd640/d; -v0x1bcfb80_0 .net "A", 0 0, L_0x1bdde50; 1 drivers -v0x1bcfc40_0 .net "AandB", 0 0, L_0x1bdd640; 1 drivers -v0x1bcfcc0_0 .net "AnandB", 0 0, L_0x1bdd580; 1 drivers -v0x1bcfd70_0 .net "AndNandOut", 0 0, L_0x1bdda90; 1 drivers -v0x1bcfe50_0 .net "B", 0 0, L_0x1bddef0; 1 drivers -v0x1bcfed0_0 .alias "Command", 2 0, v0x1bd5470_0; -L_0x1bddc60 .part v0x1bd65b0_0, 0, 1; -S_0x1bcf630 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0x1bcf540; - .timescale -9 -12; -L_0x1bdd770/d .functor NOT 1, L_0x1bddc60, C4<0>, C4<0>, C4<0>; -L_0x1bdd770 .delay (10000,10000,10000) L_0x1bdd770/d; -L_0x1bdd830/d .functor AND 1, L_0x1bdd640, L_0x1bdd770, C4<1>, C4<1>; -L_0x1bdd830 .delay (20000,20000,20000) L_0x1bdd830/d; -L_0x1bdd940/d .functor AND 1, L_0x1bdd580, L_0x1bddc60, C4<1>, C4<1>; -L_0x1bdd940 .delay (20000,20000,20000) L_0x1bdd940/d; -L_0x1bdda90/d .functor OR 1, L_0x1bdd830, L_0x1bdd940, C4<0>, C4<0>; -L_0x1bdda90 .delay (20000,20000,20000) L_0x1bdda90/d; -v0x1bcf720_0 .net "S", 0 0, L_0x1bddc60; 1 drivers -v0x1bcf7a0_0 .alias "in0", 0 0, v0x1bcfc40_0; -v0x1bcf840_0 .alias "in1", 0 0, v0x1bcfcc0_0; -v0x1bcf8e0_0 .net "nS", 0 0, L_0x1bdd770; 1 drivers -v0x1bcf960_0 .net "out0", 0 0, L_0x1bdd830; 1 drivers -v0x1bcfa00_0 .net "out1", 0 0, L_0x1bdd940; 1 drivers -v0x1bcfae0_0 .alias "outfinal", 0 0, v0x1bcfd70_0; -S_0x1bce810 .scope generate, "andbits[2]" "andbits[2]" 3 169, 3 169, S_0x1bcdb00; - .timescale -9 -12; -P_0x1bce908 .param/l "i" 3 169, +C4<010>; -S_0x1bce980 .scope module, "attempt" "AndNand" 3 171, 3 48, S_0x1bce810; - .timescale -9 -12; -L_0x1bddf90/d .functor NAND 1, L_0x1bde850, L_0x1bde8f0, C4<1>, C4<1>; -L_0x1bddf90 .delay (10000,10000,10000) L_0x1bddf90/d; -L_0x1bde0f0/d .functor NOT 1, L_0x1bddf90, C4<0>, C4<0>, C4<0>; -L_0x1bde0f0 .delay (10000,10000,10000) L_0x1bde0f0/d; -v0x1bcefc0_0 .net "A", 0 0, L_0x1bde850; 1 drivers -v0x1bcf080_0 .net "AandB", 0 0, L_0x1bde0f0; 1 drivers -v0x1bcf100_0 .net "AnandB", 0 0, L_0x1bddf90; 1 drivers -v0x1bcf1b0_0 .net "AndNandOut", 0 0, L_0x1bde540; 1 drivers -v0x1bcf290_0 .net "B", 0 0, L_0x1bde8f0; 1 drivers -v0x1bcf310_0 .alias "Command", 2 0, v0x1bd5470_0; -L_0x1bde710 .part v0x1bd65b0_0, 0, 1; -S_0x1bcea70 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0x1bce980; - .timescale -9 -12; -L_0x1bde220/d .functor NOT 1, L_0x1bde710, C4<0>, C4<0>, C4<0>; -L_0x1bde220 .delay (10000,10000,10000) L_0x1bde220/d; -L_0x1bde2e0/d .functor AND 1, L_0x1bde0f0, L_0x1bde220, C4<1>, C4<1>; -L_0x1bde2e0 .delay (20000,20000,20000) L_0x1bde2e0/d; -L_0x1bde3f0/d .functor AND 1, L_0x1bddf90, L_0x1bde710, C4<1>, C4<1>; -L_0x1bde3f0 .delay (20000,20000,20000) L_0x1bde3f0/d; -L_0x1bde540/d .functor OR 1, L_0x1bde2e0, L_0x1bde3f0, C4<0>, C4<0>; -L_0x1bde540 .delay (20000,20000,20000) L_0x1bde540/d; -v0x1bceb60_0 .net "S", 0 0, L_0x1bde710; 1 drivers -v0x1bcebe0_0 .alias "in0", 0 0, v0x1bcf080_0; -v0x1bcec80_0 .alias "in1", 0 0, v0x1bcf100_0; -v0x1bced20_0 .net "nS", 0 0, L_0x1bde220; 1 drivers -v0x1bceda0_0 .net "out0", 0 0, L_0x1bde2e0; 1 drivers -v0x1bcee40_0 .net "out1", 0 0, L_0x1bde3f0; 1 drivers -v0x1bcef20_0 .alias "outfinal", 0 0, v0x1bcf1b0_0; -S_0x1bcdc30 .scope generate, "andbits[3]" "andbits[3]" 3 169, 3 169, S_0x1bcdb00; - .timescale -9 -12; -P_0x1bcdd28 .param/l "i" 3 169, +C4<011>; -S_0x1bcdda0 .scope module, "attempt" "AndNand" 3 171, 3 48, S_0x1bcdc30; - .timescale -9 -12; -L_0x1bdea20/d .functor NAND 1, L_0x1bdf2c0, L_0x1bdf3b0, C4<1>, C4<1>; -L_0x1bdea20 .delay (10000,10000,10000) L_0x1bdea20/d; -L_0x1bdeb60/d .functor NOT 1, L_0x1bdea20, C4<0>, C4<0>, C4<0>; -L_0x1bdeb60 .delay (10000,10000,10000) L_0x1bdeb60/d; -v0x1bce400_0 .net "A", 0 0, L_0x1bdf2c0; 1 drivers -v0x1bce4c0_0 .net "AandB", 0 0, L_0x1bdeb60; 1 drivers -v0x1bce540_0 .net "AnandB", 0 0, L_0x1bdea20; 1 drivers -v0x1bce5f0_0 .net "AndNandOut", 0 0, L_0x1bdefb0; 1 drivers -v0x1bce6d0_0 .net "B", 0 0, L_0x1bdf3b0; 1 drivers -v0x1bce750_0 .alias "Command", 2 0, v0x1bd5470_0; -L_0x1bdf180 .part v0x1bd65b0_0, 0, 1; -S_0x1bcde90 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0x1bcdda0; - .timescale -9 -12; -L_0x1bdec90/d .functor NOT 1, L_0x1bdf180, C4<0>, C4<0>, C4<0>; -L_0x1bdec90 .delay (10000,10000,10000) L_0x1bdec90/d; -L_0x1bded50/d .functor AND 1, L_0x1bdeb60, L_0x1bdec90, C4<1>, C4<1>; -L_0x1bded50 .delay (20000,20000,20000) L_0x1bded50/d; -L_0x1bdee60/d .functor AND 1, L_0x1bdea20, L_0x1bdf180, C4<1>, C4<1>; -L_0x1bdee60 .delay (20000,20000,20000) L_0x1bdee60/d; -L_0x1bdefb0/d .functor OR 1, L_0x1bded50, L_0x1bdee60, C4<0>, C4<0>; -L_0x1bdefb0 .delay (20000,20000,20000) L_0x1bdefb0/d; -v0x1bcdf80_0 .net "S", 0 0, L_0x1bdf180; 1 drivers -v0x1bce020_0 .alias "in0", 0 0, v0x1bce4c0_0; -v0x1bce0c0_0 .alias "in1", 0 0, v0x1bce540_0; -v0x1bce160_0 .net "nS", 0 0, L_0x1bdec90; 1 drivers -v0x1bce1e0_0 .net "out0", 0 0, L_0x1bded50; 1 drivers -v0x1bce280_0 .net "out1", 0 0, L_0x1bdee60; 1 drivers -v0x1bce360_0 .alias "outfinal", 0 0, v0x1bce5f0_0; -S_0x1bc88a0 .scope module, "trial2" "OrNorXor32" 2 145, 3 177, S_0x1b740f0; - .timescale -9 -12; -P_0x1bc62c8 .param/l "size" 3 184, +C4<0100>; -v0x1bcd7e0_0 .alias "A", 3 0, v0x1bd5250_0; -v0x1bcd8f0_0 .alias "B", 3 0, v0x1bd5370_0; -v0x1bcda00_0 .alias "Command", 2 0, v0x1bd5470_0; -v0x1bcda80_0 .alias "OrNorXorOut", 3 0, v0x1bd66b0_0; -L_0x1be0fd0 .part/pv L_0x1be0d60, 1, 1, 4; -L_0x1be1100 .part v0x1bd6330_0, 1, 1; -L_0x1bd7f30 .part v0x1bd6530_0, 1, 1; -L_0x1be2530 .part/pv L_0x1be22c0, 2, 1, 4; -L_0x1be25d0 .part v0x1bd6330_0, 2, 1; -L_0x1be2670 .part v0x1bd6530_0, 2, 1; -L_0x1be3830 .part/pv L_0x1be35c0, 3, 1, 4; -L_0x1be38d0 .part v0x1bd6330_0, 3, 1; -L_0x1be3970 .part v0x1bd6530_0, 3, 1; -L_0x1be48e0 .part/pv L_0x1be46b0, 0, 1, 4; -L_0x1be49e0 .part v0x1bd6330_0, 0, 1; -L_0x1be4a80 .part v0x1bd6530_0, 0, 1; -S_0x1bcc5a0 .scope module, "attempt2" "OrNorXor" 3 192, 3 64, S_0x1bc88a0; - .timescale -9 -12; -L_0x1be3a10/d .functor NOR 1, L_0x1be49e0, L_0x1be4a80, C4<0>, C4<0>; -L_0x1be3a10 .delay (10000,10000,10000) L_0x1be3a10/d; -L_0x1be3b10/d .functor NOT 1, L_0x1be3a10, C4<0>, C4<0>, C4<0>; -L_0x1be3b10 .delay (10000,10000,10000) L_0x1be3b10/d; -L_0x1be3c40/d .functor NAND 1, L_0x1be49e0, L_0x1be4a80, C4<1>, C4<1>; -L_0x1be3c40 .delay (10000,10000,10000) L_0x1be3c40/d; -L_0x1be3da0/d .functor NAND 1, L_0x1be3c40, L_0x1be3b10, C4<1>, C4<1>; -L_0x1be3da0 .delay (10000,10000,10000) L_0x1be3da0/d; -L_0x1be3eb0/d .functor NOT 1, L_0x1be3da0, C4<0>, C4<0>, C4<0>; -L_0x1be3eb0 .delay (10000,10000,10000) L_0x1be3eb0/d; -v0x1bcd0f0_0 .net "A", 0 0, L_0x1be49e0; 1 drivers -v0x1bcd190_0 .net "AnandB", 0 0, L_0x1be3c40; 1 drivers -v0x1bcd230_0 .net "AnorB", 0 0, L_0x1be3a10; 1 drivers -v0x1bcd2e0_0 .net "AorB", 0 0, L_0x1be3b10; 1 drivers -v0x1bcd3c0_0 .net "AxorB", 0 0, L_0x1be3eb0; 1 drivers -v0x1bcd470_0 .net "B", 0 0, L_0x1be4a80; 1 drivers -v0x1bcd530_0 .alias "Command", 2 0, v0x1bd5470_0; -v0x1bcd5b0_0 .net "OrNorXorOut", 0 0, L_0x1be46b0; 1 drivers -v0x1bcd630_0 .net "XorNor", 0 0, L_0x1be41d0; 1 drivers -v0x1bcd700_0 .net "nXor", 0 0, L_0x1be3da0; 1 drivers -L_0x1be4310 .part v0x1bd65b0_0, 2, 1; -L_0x1be4840 .part v0x1bd65b0_0, 0, 1; -S_0x1bccb80 .scope module, "mux0" "TwoInMux" 3 83, 3 8, S_0x1bcc5a0; - .timescale -9 -12; -L_0x1bd0820/d .functor NOT 1, L_0x1be4310, C4<0>, C4<0>, C4<0>; -L_0x1bd0820 .delay (10000,10000,10000) L_0x1bd0820/d; -L_0x1be3fa0/d .functor AND 1, L_0x1be3eb0, L_0x1bd0820, C4<1>, C4<1>; -L_0x1be3fa0 .delay (20000,20000,20000) L_0x1be3fa0/d; -L_0x1be40a0/d .functor AND 1, L_0x1be3a10, L_0x1be4310, C4<1>, C4<1>; -L_0x1be40a0 .delay (20000,20000,20000) L_0x1be40a0/d; -L_0x1be41d0/d .functor OR 1, L_0x1be3fa0, L_0x1be40a0, C4<0>, C4<0>; -L_0x1be41d0 .delay (20000,20000,20000) L_0x1be41d0/d; -v0x1bccc70_0 .net "S", 0 0, L_0x1be4310; 1 drivers -v0x1bccd30_0 .alias "in0", 0 0, v0x1bcd3c0_0; -v0x1bccdd0_0 .alias "in1", 0 0, v0x1bcd230_0; -v0x1bcce70_0 .net "nS", 0 0, L_0x1bd0820; 1 drivers -v0x1bccef0_0 .net "out0", 0 0, L_0x1be3fa0; 1 drivers -v0x1bccf90_0 .net "out1", 0 0, L_0x1be40a0; 1 drivers -v0x1bcd070_0 .alias "outfinal", 0 0, v0x1bcd630_0; -S_0x1bcc690 .scope module, "mux1" "TwoInMux" 3 84, 3 8, S_0x1bcc5a0; - .timescale -9 -12; -L_0x1be43b0/d .functor NOT 1, L_0x1be4840, C4<0>, C4<0>, C4<0>; -L_0x1be43b0 .delay (10000,10000,10000) L_0x1be43b0/d; -L_0x1be4450/d .functor AND 1, L_0x1be41d0, L_0x1be43b0, C4<1>, C4<1>; -L_0x1be4450 .delay (20000,20000,20000) L_0x1be4450/d; -L_0x1be4580/d .functor AND 1, L_0x1be3b10, L_0x1be4840, C4<1>, C4<1>; -L_0x1be4580 .delay (20000,20000,20000) L_0x1be4580/d; -L_0x1be46b0/d .functor OR 1, L_0x1be4450, L_0x1be4580, C4<0>, C4<0>; -L_0x1be46b0 .delay (20000,20000,20000) L_0x1be46b0/d; -v0x1bcc780_0 .net "S", 0 0, L_0x1be4840; 1 drivers -v0x1bcc800_0 .alias "in0", 0 0, v0x1bcd630_0; -v0x1bcc880_0 .alias "in1", 0 0, v0x1bcd2e0_0; -v0x1bcc920_0 .net "nS", 0 0, L_0x1be43b0; 1 drivers -v0x1bcc9a0_0 .net "out0", 0 0, L_0x1be4450; 1 drivers -v0x1bcca40_0 .net "out1", 0 0, L_0x1be4580; 1 drivers -v0x1bccae0_0 .alias "outfinal", 0 0, v0x1bcd5b0_0; -S_0x1bcb1d0 .scope generate, "orbits[1]" "orbits[1]" 3 196, 3 196, S_0x1bc88a0; - .timescale -9 -12; -P_0x1bcaee8 .param/l "i" 3 196, +C4<01>; -S_0x1bcb300 .scope module, "attempt" "OrNorXor" 3 198, 3 64, S_0x1bcb1d0; - .timescale -9 -12; -L_0x1bdfd20/d .functor NOR 1, L_0x1be1100, L_0x1bd7f30, C4<0>, C4<0>; -L_0x1bdfd20 .delay (10000,10000,10000) L_0x1bdfd20/d; -L_0x1bdffc0/d .functor NOT 1, L_0x1bdfd20, C4<0>, C4<0>, C4<0>; -L_0x1bdffc0 .delay (10000,10000,10000) L_0x1bdffc0/d; -L_0x1be00f0/d .functor NAND 1, L_0x1be1100, L_0x1bd7f30, C4<1>, C4<1>; -L_0x1be00f0 .delay (10000,10000,10000) L_0x1be00f0/d; -L_0x1be0250/d .functor NAND 1, L_0x1be00f0, L_0x1bdffc0, C4<1>, C4<1>; -L_0x1be0250 .delay (10000,10000,10000) L_0x1be0250/d; -L_0x1be0360/d .functor NOT 1, L_0x1be0250, C4<0>, C4<0>, C4<0>; -L_0x1be0360 .delay (10000,10000,10000) L_0x1be0360/d; -v0x1bcbeb0_0 .net "A", 0 0, L_0x1be1100; 1 drivers -v0x1bcbf50_0 .net "AnandB", 0 0, L_0x1be00f0; 1 drivers -v0x1bcbff0_0 .net "AnorB", 0 0, L_0x1bdfd20; 1 drivers -v0x1bcc0a0_0 .net "AorB", 0 0, L_0x1bdffc0; 1 drivers -v0x1bcc180_0 .net "AxorB", 0 0, L_0x1be0360; 1 drivers -v0x1bcc230_0 .net "B", 0 0, L_0x1bd7f30; 1 drivers -v0x1bcc2f0_0 .alias "Command", 2 0, v0x1bd5470_0; -v0x1bcc370_0 .net "OrNorXorOut", 0 0, L_0x1be0d60; 1 drivers -v0x1bcc3f0_0 .net "XorNor", 0 0, L_0x1be07e0; 1 drivers -v0x1bcc4c0_0 .net "nXor", 0 0, L_0x1be0250; 1 drivers -L_0x1be0960 .part v0x1bd65b0_0, 2, 1; -L_0x1be0f30 .part v0x1bd65b0_0, 0, 1; -S_0x1bcb940 .scope module, "mux0" "TwoInMux" 3 83, 3 8, S_0x1bcb300; - .timescale -9 -12; -L_0x1be04c0/d .functor NOT 1, L_0x1be0960, C4<0>, C4<0>, C4<0>; -L_0x1be04c0 .delay (10000,10000,10000) L_0x1be04c0/d; -L_0x1be0580/d .functor AND 1, L_0x1be0360, L_0x1be04c0, C4<1>, C4<1>; -L_0x1be0580 .delay (20000,20000,20000) L_0x1be0580/d; -L_0x1be0690/d .functor AND 1, L_0x1bdfd20, L_0x1be0960, C4<1>, C4<1>; -L_0x1be0690 .delay (20000,20000,20000) L_0x1be0690/d; -L_0x1be07e0/d .functor OR 1, L_0x1be0580, L_0x1be0690, C4<0>, C4<0>; -L_0x1be07e0 .delay (20000,20000,20000) L_0x1be07e0/d; -v0x1bcba30_0 .net "S", 0 0, L_0x1be0960; 1 drivers -v0x1bcbaf0_0 .alias "in0", 0 0, v0x1bcc180_0; -v0x1bcbb90_0 .alias "in1", 0 0, v0x1bcbff0_0; -v0x1bcbc30_0 .net "nS", 0 0, L_0x1be04c0; 1 drivers -v0x1bcbcb0_0 .net "out0", 0 0, L_0x1be0580; 1 drivers -v0x1bcbd50_0 .net "out1", 0 0, L_0x1be0690; 1 drivers -v0x1bcbe30_0 .alias "outfinal", 0 0, v0x1bcc3f0_0; -S_0x1bcb3f0 .scope module, "mux1" "TwoInMux" 3 84, 3 8, S_0x1bcb300; - .timescale -9 -12; -L_0x1be0a00/d .functor NOT 1, L_0x1be0f30, C4<0>, C4<0>, C4<0>; -L_0x1be0a00 .delay (10000,10000,10000) L_0x1be0a00/d; -L_0x1be0ac0/d .functor AND 1, L_0x1be07e0, L_0x1be0a00, C4<1>, C4<1>; -L_0x1be0ac0 .delay (20000,20000,20000) L_0x1be0ac0/d; -L_0x1be0c10/d .functor AND 1, L_0x1bdffc0, L_0x1be0f30, C4<1>, C4<1>; -L_0x1be0c10 .delay (20000,20000,20000) L_0x1be0c10/d; -L_0x1be0d60/d .functor OR 1, L_0x1be0ac0, L_0x1be0c10, C4<0>, C4<0>; -L_0x1be0d60 .delay (20000,20000,20000) L_0x1be0d60/d; -v0x1bcb4e0_0 .net "S", 0 0, L_0x1be0f30; 1 drivers -v0x1bcb560_0 .alias "in0", 0 0, v0x1bcc3f0_0; -v0x1bcb600_0 .alias "in1", 0 0, v0x1bcc0a0_0; -v0x1bcb6a0_0 .net "nS", 0 0, L_0x1be0a00; 1 drivers -v0x1bcb720_0 .net "out0", 0 0, L_0x1be0ac0; 1 drivers -v0x1bcb7c0_0 .net "out1", 0 0, L_0x1be0c10; 1 drivers -v0x1bcb8a0_0 .alias "outfinal", 0 0, v0x1bcc370_0; -S_0x1bc9e00 .scope generate, "orbits[2]" "orbits[2]" 3 196, 3 196, S_0x1bc88a0; - .timescale -9 -12; -P_0x1bc9a68 .param/l "i" 3 196, +C4<010>; -S_0x1bc9f30 .scope module, "attempt" "OrNorXor" 3 198, 3 64, S_0x1bc9e00; - .timescale -9 -12; -L_0x1bd7fd0/d .functor NOR 1, L_0x1be25d0, L_0x1be2670, C4<0>, C4<0>; -L_0x1bd7fd0 .delay (10000,10000,10000) L_0x1bd7fd0/d; -L_0x1bd8140/d .functor NOT 1, L_0x1bd7fd0, C4<0>, C4<0>, C4<0>; -L_0x1bd8140 .delay (10000,10000,10000) L_0x1bd8140/d; -L_0x1be1650/d .functor NAND 1, L_0x1be25d0, L_0x1be2670, C4<1>, C4<1>; -L_0x1be1650 .delay (10000,10000,10000) L_0x1be1650/d; -L_0x1be17b0/d .functor NAND 1, L_0x1be1650, L_0x1bd8140, C4<1>, C4<1>; -L_0x1be17b0 .delay (10000,10000,10000) L_0x1be17b0/d; -L_0x1be18c0/d .functor NOT 1, L_0x1be17b0, C4<0>, C4<0>, C4<0>; -L_0x1be18c0 .delay (10000,10000,10000) L_0x1be18c0/d; -v0x1bcaae0_0 .net "A", 0 0, L_0x1be25d0; 1 drivers -v0x1bcab80_0 .net "AnandB", 0 0, L_0x1be1650; 1 drivers -v0x1bcac20_0 .net "AnorB", 0 0, L_0x1bd7fd0; 1 drivers -v0x1bcacd0_0 .net "AorB", 0 0, L_0x1bd8140; 1 drivers -v0x1bcadb0_0 .net "AxorB", 0 0, L_0x1be18c0; 1 drivers -v0x1bcae60_0 .net "B", 0 0, L_0x1be2670; 1 drivers -v0x1bcaf20_0 .alias "Command", 2 0, v0x1bd5470_0; -v0x1bcafa0_0 .net "OrNorXorOut", 0 0, L_0x1be22c0; 1 drivers -v0x1bcb020_0 .net "XorNor", 0 0, L_0x1be1d40; 1 drivers -v0x1bcb0f0_0 .net "nXor", 0 0, L_0x1be17b0; 1 drivers -L_0x1be1ec0 .part v0x1bd65b0_0, 2, 1; -L_0x1be2490 .part v0x1bd65b0_0, 0, 1; -S_0x1bca570 .scope module, "mux0" "TwoInMux" 3 83, 3 8, S_0x1bc9f30; - .timescale -9 -12; -L_0x1be1a20/d .functor NOT 1, L_0x1be1ec0, C4<0>, C4<0>, C4<0>; -L_0x1be1a20 .delay (10000,10000,10000) L_0x1be1a20/d; -L_0x1be1ae0/d .functor AND 1, L_0x1be18c0, L_0x1be1a20, C4<1>, C4<1>; -L_0x1be1ae0 .delay (20000,20000,20000) L_0x1be1ae0/d; -L_0x1be1bf0/d .functor AND 1, L_0x1bd7fd0, L_0x1be1ec0, C4<1>, C4<1>; -L_0x1be1bf0 .delay (20000,20000,20000) L_0x1be1bf0/d; -L_0x1be1d40/d .functor OR 1, L_0x1be1ae0, L_0x1be1bf0, C4<0>, C4<0>; -L_0x1be1d40 .delay (20000,20000,20000) L_0x1be1d40/d; -v0x1bca660_0 .net "S", 0 0, L_0x1be1ec0; 1 drivers -v0x1bca720_0 .alias "in0", 0 0, v0x1bcadb0_0; -v0x1bca7c0_0 .alias "in1", 0 0, v0x1bcac20_0; -v0x1bca860_0 .net "nS", 0 0, L_0x1be1a20; 1 drivers -v0x1bca8e0_0 .net "out0", 0 0, L_0x1be1ae0; 1 drivers -v0x1bca980_0 .net "out1", 0 0, L_0x1be1bf0; 1 drivers -v0x1bcaa60_0 .alias "outfinal", 0 0, v0x1bcb020_0; -S_0x1bca020 .scope module, "mux1" "TwoInMux" 3 84, 3 8, S_0x1bc9f30; - .timescale -9 -12; -L_0x1be1f60/d .functor NOT 1, L_0x1be2490, C4<0>, C4<0>, C4<0>; -L_0x1be1f60 .delay (10000,10000,10000) L_0x1be1f60/d; -L_0x1be2020/d .functor AND 1, L_0x1be1d40, L_0x1be1f60, C4<1>, C4<1>; -L_0x1be2020 .delay (20000,20000,20000) L_0x1be2020/d; -L_0x1be2170/d .functor AND 1, L_0x1bd8140, L_0x1be2490, C4<1>, C4<1>; -L_0x1be2170 .delay (20000,20000,20000) L_0x1be2170/d; -L_0x1be22c0/d .functor OR 1, L_0x1be2020, L_0x1be2170, C4<0>, C4<0>; -L_0x1be22c0 .delay (20000,20000,20000) L_0x1be22c0/d; -v0x1bca110_0 .net "S", 0 0, L_0x1be2490; 1 drivers -v0x1bca190_0 .alias "in0", 0 0, v0x1bcb020_0; -v0x1bca230_0 .alias "in1", 0 0, v0x1bcacd0_0; -v0x1bca2d0_0 .net "nS", 0 0, L_0x1be1f60; 1 drivers -v0x1bca350_0 .net "out0", 0 0, L_0x1be2020; 1 drivers -v0x1bca3f0_0 .net "out1", 0 0, L_0x1be2170; 1 drivers -v0x1bca4d0_0 .alias "outfinal", 0 0, v0x1bcafa0_0; -S_0x1bc8990 .scope generate, "orbits[3]" "orbits[3]" 3 196, 3 196, S_0x1bc88a0; - .timescale -9 -12; -P_0x1bc86d8 .param/l "i" 3 196, +C4<011>; -S_0x1bc8a80 .scope module, "attempt" "OrNorXor" 3 198, 3 64, S_0x1bc8990; - .timescale -9 -12; -L_0x1be2750/d .functor NOR 1, L_0x1be38d0, L_0x1be3970, C4<0>, C4<0>; -L_0x1be2750 .delay (10000,10000,10000) L_0x1be2750/d; -L_0x1be2840/d .functor NOT 1, L_0x1be2750, C4<0>, C4<0>, C4<0>; -L_0x1be2840 .delay (10000,10000,10000) L_0x1be2840/d; -L_0x1be2950/d .functor NAND 1, L_0x1be38d0, L_0x1be3970, C4<1>, C4<1>; -L_0x1be2950 .delay (10000,10000,10000) L_0x1be2950/d; -L_0x1be2ab0/d .functor NAND 1, L_0x1be2950, L_0x1be2840, C4<1>, C4<1>; -L_0x1be2ab0 .delay (10000,10000,10000) L_0x1be2ab0/d; -L_0x1be2bc0/d .functor NOT 1, L_0x1be2ab0, C4<0>, C4<0>, C4<0>; -L_0x1be2bc0 .delay (10000,10000,10000) L_0x1be2bc0/d; -v0x1bc9660_0 .net "A", 0 0, L_0x1be38d0; 1 drivers -v0x1bc9700_0 .net "AnandB", 0 0, L_0x1be2950; 1 drivers -v0x1bc97a0_0 .net "AnorB", 0 0, L_0x1be2750; 1 drivers -v0x1bc9850_0 .net "AorB", 0 0, L_0x1be2840; 1 drivers -v0x1bc9930_0 .net "AxorB", 0 0, L_0x1be2bc0; 1 drivers -v0x1bc99e0_0 .net "B", 0 0, L_0x1be3970; 1 drivers -v0x1bc9aa0_0 .alias "Command", 2 0, v0x1bd5470_0; -v0x1bc1ef0_0 .net "OrNorXorOut", 0 0, L_0x1be35c0; 1 drivers -v0x1bc1f70_0 .net "XorNor", 0 0, L_0x1be3040; 1 drivers -v0x1bc9d80_0 .net "nXor", 0 0, L_0x1be2ab0; 1 drivers -L_0x1be31c0 .part v0x1bd65b0_0, 2, 1; -L_0x1be3790 .part v0x1bd65b0_0, 0, 1; -S_0x1bc90f0 .scope module, "mux0" "TwoInMux" 3 83, 3 8, S_0x1bc8a80; - .timescale -9 -12; -L_0x1be2d20/d .functor NOT 1, L_0x1be31c0, C4<0>, C4<0>, C4<0>; -L_0x1be2d20 .delay (10000,10000,10000) L_0x1be2d20/d; -L_0x1be2de0/d .functor AND 1, L_0x1be2bc0, L_0x1be2d20, C4<1>, C4<1>; -L_0x1be2de0 .delay (20000,20000,20000) L_0x1be2de0/d; -L_0x1be2ef0/d .functor AND 1, L_0x1be2750, L_0x1be31c0, C4<1>, C4<1>; -L_0x1be2ef0 .delay (20000,20000,20000) L_0x1be2ef0/d; -L_0x1be3040/d .functor OR 1, L_0x1be2de0, L_0x1be2ef0, C4<0>, C4<0>; -L_0x1be3040 .delay (20000,20000,20000) L_0x1be3040/d; -v0x1bc91e0_0 .net "S", 0 0, L_0x1be31c0; 1 drivers -v0x1bc92a0_0 .alias "in0", 0 0, v0x1bc9930_0; -v0x1bc9340_0 .alias "in1", 0 0, v0x1bc97a0_0; -v0x1bc93e0_0 .net "nS", 0 0, L_0x1be2d20; 1 drivers -v0x1bc9460_0 .net "out0", 0 0, L_0x1be2de0; 1 drivers -v0x1bc9500_0 .net "out1", 0 0, L_0x1be2ef0; 1 drivers -v0x1bc95e0_0 .alias "outfinal", 0 0, v0x1bc1f70_0; -S_0x1bc8b70 .scope module, "mux1" "TwoInMux" 3 84, 3 8, S_0x1bc8a80; - .timescale -9 -12; -L_0x1be3260/d .functor NOT 1, L_0x1be3790, C4<0>, C4<0>, C4<0>; -L_0x1be3260 .delay (10000,10000,10000) L_0x1be3260/d; -L_0x1be3320/d .functor AND 1, L_0x1be3040, L_0x1be3260, C4<1>, C4<1>; -L_0x1be3320 .delay (20000,20000,20000) L_0x1be3320/d; -L_0x1be3470/d .functor AND 1, L_0x1be2840, L_0x1be3790, C4<1>, C4<1>; -L_0x1be3470 .delay (20000,20000,20000) L_0x1be3470/d; -L_0x1be35c0/d .functor OR 1, L_0x1be3320, L_0x1be3470, C4<0>, C4<0>; -L_0x1be35c0 .delay (20000,20000,20000) L_0x1be35c0/d; -v0x1bc8c60_0 .net "S", 0 0, L_0x1be3790; 1 drivers -v0x1bc8ce0_0 .alias "in0", 0 0, v0x1bc1f70_0; -v0x1bc8d80_0 .alias "in1", 0 0, v0x1bc9850_0; -v0x1bc8e20_0 .net "nS", 0 0, L_0x1be3260; 1 drivers -v0x1bc8ed0_0 .net "out0", 0 0, L_0x1be3320; 1 drivers -v0x1bc8f70_0 .net "out1", 0 0, L_0x1be3470; 1 drivers -v0x1bc9050_0 .alias "outfinal", 0 0, v0x1bc1ef0_0; -S_0x1b51ae0 .scope module, "superalu" "Bitslice32" 2 147, 3 256, S_0x1b740f0; - .timescale -9 -12; -P_0x1b298c8 .param/l "size" 3 273, +C4<0100>; -L_0x1be9d90/d .functor AND 1, L_0x1bfca80, L_0x1bfcc60, C4<1>, C4<1>; -L_0x1be9d90 .delay (20000,20000,20000) L_0x1be9d90/d; -L_0x1bfcd50/d .functor NOT 1, L_0x1bfce00, C4<0>, C4<0>, C4<0>; -L_0x1bfcd50 .delay (10000,10000,10000) L_0x1bfcd50/d; -L_0x1bfd2b0/d .functor AND 1, L_0x1bfcd50, L_0x1bfcd50, C4<1>, C4<1>; -L_0x1bfd2b0 .delay (20000,20000,20000) L_0x1bfd2b0/d; -v0x1bc7790_0 .alias "A", 3 0, v0x1bd5250_0; -v0x1bc7980_0 .alias "AddSubSLTSum", 3 0, v0x1bd63b0_0; -v0x1bc7a00_0 .alias "AllZeros", 0 0, v0x1bd6430_0; -v0x1bc7a80_0 .alias "AndNandOut", 3 0, v0x1bd64b0_0; -v0x1bc7b30_0 .alias "B", 3 0, v0x1bd5370_0; -RS_0x7f6a63aa1008 .resolv tri, L_0x1be5290, L_0x1be7cf0, L_0x1beaaf0, L_0x1bfae50; -v0x1bc7bb0_0 .net8 "Cmd0Start", 3 0, RS_0x7f6a63aa1008; 4 drivers -RS_0x7f6a63aa1038 .resolv tri, L_0x1be6200, L_0x1be8be0, L_0x1bebae0, L_0x1bfbc80; -v0x1bc7c30_0 .net8 "Cmd1Start", 3 0, RS_0x7f6a63aa1038; 4 drivers -v0x1bc7cb0_0 .alias "Command", 2 0, v0x1bd5470_0; -v0x1bc7d30_0 .alias "OneBitFinalOut", 3 0, v0x1bd6630_0; -v0x1bc7dd0_0 .alias "OrNorXorOut", 3 0, v0x1bd66b0_0; -v0x1bc7e50_0 .alias "SLTflag", 0 0, v0x1bd6730_0; -v0x1bc7f00_0 .alias "ZeroFlag", 3 0, v0x1bd67b0_0; -v0x1bc7f80_0 .net *"_s111", 0 0, L_0x1be9d90; 1 drivers -v0x1bc8000_0 .net *"_s114", 0 0, L_0x1bfca80; 1 drivers -v0x1bc8120_0 .net *"_s116", 0 0, L_0x1bfcc60; 1 drivers -v0x1bc81c0_0 .net *"_s118", 0 0, L_0x1bfce00; 1 drivers -v0x1bc8080_0 .net *"_s21", 0 0, L_0x1be7250; 1 drivers -v0x1bc8310_0 .net *"_s46", 0 0, L_0x1be9660; 1 drivers -v0x1bc8430_0 .net *"_s71", 0 0, L_0x1bec8a0; 1 drivers -v0x1bc84b0_0 .alias "carryin", 3 0, v0x1bd5ea0_0; -v0x1bc8390_0 .alias "carryout", 0 0, v0x1bd68b0_0; -v0x1bc8610_0 .alias "overflow", 0 0, v0x1bd6930_0; -v0x1bc8560_0 .alias "subtract", 3 0, v0x1bd69b0_0; -v0x1bc8750_0 .net "yeszero", 0 0, L_0x1bfcd50; 1 drivers -L_0x1be5290 .part/pv L_0x1be5080, 1, 1, 4; -L_0x1be5330 .part v0x1bd65b0_0, 0, 1; -L_0x1be5460 .part v0x1bd65b0_0, 1, 1; -L_0x1be5590 .part RS_0x7f6a63aa0be8, 1, 1; -L_0x1be5630 .part RS_0x7f6a63aa0be8, 1, 1; -L_0x1be56d0 .part RS_0x7f6a63a9f748, 1, 1; -L_0x1be58d0 .part RS_0x7f6a63aa0be8, 1, 1; -L_0x1be6200 .part/pv L_0x1be5ff0, 1, 1, 4; -L_0x1be62f0 .part v0x1bd65b0_0, 0, 1; -L_0x1be6420 .part v0x1bd65b0_0, 1, 1; -L_0x1be65b0 .part RS_0x7f6a63a9fe38, 1, 1; -L_0x1be6760 .part RS_0x7f6a63a9fe38, 1, 1; -L_0x1be6800 .part RS_0x7f6a63a9f748, 1, 1; -L_0x1be68a0 .part RS_0x7f6a63a9f748, 1, 1; -L_0x1be6d00 .part/pv L_0x1be6bc0, 1, 1, 4; -L_0x1be6df0 .part v0x1bd65b0_0, 2, 1; -L_0x1be6e90 .part RS_0x7f6a63aa1008, 1, 1; -L_0x1be6fd0 .part RS_0x7f6a63aa1038, 1, 1; -L_0x1be71b0 .part/pv L_0x1be7250, 1, 1, 4; -L_0x1be7350 .part RS_0x7f6a63aa1098, 0, 1; -L_0x1be7110 .part RS_0x7f6a63aa1068, 1, 1; -L_0x1be7cf0 .part/pv L_0x1be7ae0, 2, 1, 4; -L_0x1be73f0 .part v0x1bd65b0_0, 0, 1; -L_0x1be7ee0 .part v0x1bd65b0_0, 1, 1; -L_0x1be7d90 .part RS_0x7f6a63aa0be8, 2, 1; -L_0x1be80e0 .part RS_0x7f6a63aa0be8, 2, 1; -L_0x1be8010 .part RS_0x7f6a63a9f748, 2, 1; -L_0x1be82b0 .part RS_0x7f6a63aa0be8, 2, 1; -L_0x1be8be0 .part/pv L_0x1be89d0, 2, 1, 4; -L_0x1be8c80 .part v0x1bd65b0_0, 0, 1; -L_0x1be83a0 .part v0x1bd65b0_0, 1, 1; -L_0x1bd7280 .part RS_0x7f6a63a9fe38, 2, 1; -L_0x1bd7430 .part RS_0x7f6a63a9fe38, 2, 1; -L_0x1bd70f0 .part RS_0x7f6a63a9f748, 2, 1; -L_0x1bd7320 .part RS_0x7f6a63a9f748, 2, 1; -L_0x1be9a90 .part/pv L_0x1be9950, 2, 1, 4; -L_0x1be95c0 .part v0x1bd65b0_0, 2, 1; -L_0x1be9cf0 .part RS_0x7f6a63aa1008, 2, 1; -L_0x1be9bc0 .part RS_0x7f6a63aa1038, 2, 1; -L_0x1be9f60 .part/pv L_0x1be9660, 2, 1, 4; -L_0x1be9e60 .part RS_0x7f6a63aa1098, 1, 1; -L_0x1bea1e0 .part RS_0x7f6a63aa1068, 2, 1; -L_0x1beaaf0 .part/pv L_0x1bea8e0, 3, 1, 4; -L_0x1beab90 .part v0x1bd65b0_0, 0, 1; -L_0x1bea280 .part v0x1bd65b0_0, 1, 1; -L_0x1beae30 .part RS_0x7f6a63aa0be8, 3, 1; -L_0x1bdcd20 .part RS_0x7f6a63aa0be8, 3, 1; -L_0x1beacc0 .part RS_0x7f6a63a9f748, 3, 1; -L_0x1beb270 .part RS_0x7f6a63aa0be8, 3, 1; -L_0x1bebae0 .part/pv L_0x1beb8d0, 3, 1, 4; -L_0x1beb0e0 .part v0x1bd65b0_0, 0, 1; -L_0x1bebd20 .part v0x1bd65b0_0, 1, 1; -L_0x1bebb80 .part RS_0x7f6a63a9fe38, 3, 1; -L_0x1bebc20 .part RS_0x7f6a63a9fe38, 3, 1; -L_0x1bec010 .part RS_0x7f6a63a9f748, 3, 1; -L_0x1bec0b0 .part RS_0x7f6a63a9f748, 3, 1; -L_0x1bec6c0 .part/pv L_0x1bec580, 3, 1, 4; -L_0x1bec760 .part v0x1bd65b0_0, 2, 1; -L_0x1bec360 .part RS_0x7f6a63aa1008, 3, 1; -L_0x1bec450 .part RS_0x7f6a63aa1038, 3, 1; -L_0x1bec800 .part/pv L_0x1bec8a0, 3, 1, 4; -L_0x1becc20 .part RS_0x7f6a63aa1098, 2, 1; -L_0x1beca30 .part RS_0x7f6a63aa1068, 3, 1; -L_0x1bfae50 .part/pv L_0x1bfac70, 0, 1, 4; -L_0x1beccc0 .part v0x1bd65b0_0, 0, 1; -L_0x1becdf0 .part v0x1bd65b0_0, 1, 1; -L_0x1bfaef0 .part RS_0x7f6a63aa0be8, 0, 1; -L_0x1bfaf90 .part RS_0x7f6a63aa0be8, 0, 1; -L_0x1bfb030 .part RS_0x7f6a63a9f748, 0, 1; -L_0x1bfb410 .part RS_0x7f6a63aa0be8, 0, 1; -L_0x1bfbc80 .part/pv L_0x1bfbaa0, 0, 1, 4; -L_0x1bfbd20 .part v0x1bd65b0_0, 0, 1; -L_0x1bfb500 .part v0x1bd65b0_0, 1, 1; -L_0x1bfb630 .part RS_0x7f6a63a9fe38, 0, 1; -L_0x1bfc0b0 .part RS_0x7f6a63a9fe38, 0, 1; -L_0x1bfc150 .part RS_0x7f6a63a9f748, 0, 1; -L_0x1bfbe50 .part RS_0x7f6a63a9f748, 0, 1; -L_0x1bfc720 .part/pv L_0x1bfc5e0, 0, 1, 4; -L_0x1bfc1f0 .part v0x1bd65b0_0, 2, 1; -L_0x1bfc290 .part RS_0x7f6a63aa1008, 0, 1; -L_0x1bfc380 .part RS_0x7f6a63aa1038, 0, 1; -L_0x1bfc9e0 .part/pv L_0x1be9d90, 0, 1, 4; -L_0x1bfca80 .part RS_0x7f6a63aa1068, 0, 1; -L_0x1bfcc60 .part RS_0x7f6a63aa1068, 0, 1; -L_0x1bfce00 .part RS_0x7f6a63aa1098, 3, 1; -S_0x1bc21e0 .scope module, "trial" "AddSubSLT32" 3 279, 3 205, S_0x1b51ae0; - .timescale -9 -12; -P_0x1bc22d8 .param/l "size" 3 228, +C4<0100>; -L_0x1bf1de0/d .functor OR 1, L_0x1bf20a0, C4<0>, C4<0>, C4<0>; -L_0x1bf1de0 .delay (20000,20000,20000) L_0x1bf1de0/d; -L_0x1bf2250/d .functor XOR 1, RS_0x7f6a63aa0ee8, L_0x1bf2340, C4<0>, C4<0>; -L_0x1bf2250 .delay (40000,40000,40000) L_0x1bf2250/d; -L_0x1bf1fd0/d .functor AND 1, L_0x1bf2510, L_0x1bf25b0, C4<1>, C4<1>; -L_0x1bf1fd0 .delay (20000,20000,20000) L_0x1bf1fd0/d; -L_0x1bf23e0/d .functor NOT 1, RS_0x7f6a63aa0f78, C4<0>, C4<0>, C4<0>; -L_0x1bf23e0 .delay (10000,10000,10000) L_0x1bf23e0/d; -L_0x1bf28a0/d .functor NOT 1, L_0x1bf2900, C4<0>, C4<0>, C4<0>; -L_0x1bf28a0 .delay (10000,10000,10000) L_0x1bf28a0/d; -L_0x1bf29a0/d .functor AND 1, L_0x1bf23e0, L_0x1bf2ae0, C4<1>, C4<1>; -L_0x1bf29a0 .delay (20000,20000,20000) L_0x1bf29a0/d; -L_0x1bf26a0/d .functor AND 1, RS_0x7f6a63aa0f78, L_0x1bf28a0, C4<1>, C4<1>; -L_0x1bf26a0 .delay (20000,20000,20000) L_0x1bf26a0/d; -L_0x1bf2cd0/d .functor AND 1, L_0x1bf29a0, L_0x1bf1fd0, C4<1>, C4<1>; -L_0x1bf2cd0 .delay (20000,20000,20000) L_0x1bf2cd0/d; -L_0x1bf2e10/d .functor AND 1, L_0x1bf26a0, L_0x1bf1fd0, C4<1>, C4<1>; -L_0x1bf2e10 .delay (20000,20000,20000) L_0x1bf2e10/d; -L_0x1bf2f30/d .functor OR 1, L_0x1bf2cd0, L_0x1bf2e10, C4<0>, C4<0>; -L_0x1bf2f30 .delay (20000,20000,20000) L_0x1bf2f30/d; -v0x1bc68b0_0 .alias "A", 3 0, v0x1bd5250_0; -v0x1bc6950_0 .alias "AddSubSLTSum", 3 0, v0x1bd63b0_0; -v0x1bc69f0_0 .alias "B", 3 0, v0x1bd5370_0; -RS_0x7f6a63aa0c18 .resolv tri, L_0x1bedd50, L_0x1bef170, L_0x1bf0570, L_0x1bf1b50; -v0x1bc6ac0_0 .net8 "CarryoutWire", 3 0, RS_0x7f6a63aa0c18; 4 drivers -v0x1bc6b40_0 .alias "Command", 2 0, v0x1bd5470_0; -v0x1bc6bc0_0 .net "Res0OF1", 0 0, L_0x1bf26a0; 1 drivers -v0x1bc6c60_0 .net "Res1OF0", 0 0, L_0x1bf29a0; 1 drivers -v0x1bc6d00_0 .alias "SLTflag", 0 0, v0x1bd6730_0; -v0x1bc6df0_0 .net "SLTflag0", 0 0, L_0x1bf2cd0; 1 drivers -v0x1bc6e90_0 .net "SLTflag1", 0 0, L_0x1bf2e10; 1 drivers -v0x1bc6f30_0 .net "SLTon", 0 0, L_0x1bf1fd0; 1 drivers -v0x1bc6fd0_0 .net *"_s40", 0 0, L_0x1bf20a0; 1 drivers -v0x1bc7070_0 .net/s *"_s41", 0 0, C4<0>; 1 drivers -v0x1bc7110_0 .net *"_s44", 0 0, L_0x1bf2340; 1 drivers -v0x1bc7230_0 .net *"_s46", 0 0, L_0x1bf2510; 1 drivers -v0x1bc72d0_0 .net *"_s48", 0 0, L_0x1bf25b0; 1 drivers -v0x1bc7190_0 .net *"_s50", 0 0, L_0x1bf2900; 1 drivers -v0x1bc7420_0 .net *"_s52", 0 0, L_0x1bf2ae0; 1 drivers -v0x1bc7540_0 .alias "carryin", 3 0, v0x1bd5ea0_0; -v0x1bc75c0_0 .alias "carryout", 0 0, v0x1bd68b0_0; -v0x1bc74a0_0 .net "nAddSubSLTSum", 0 0, L_0x1bf28a0; 1 drivers -v0x1bc76f0_0 .net "nOF", 0 0, L_0x1bf23e0; 1 drivers -v0x1bc7640_0 .alias "overflow", 0 0, v0x1bd6930_0; -v0x1bc7830_0 .alias "subtract", 3 0, v0x1bd69b0_0; -L_0x1bedc60 .part/pv L_0x1bed7d0, 1, 1, 4; -L_0x1bedd50 .part/pv L_0x1bedb20, 1, 1, 4; -L_0x1bede40 .part/pv L_0x1bed500, 1, 1, 4; -L_0x1bedf30 .part v0x1bd6330_0, 1, 1; -L_0x1bedfd0 .part v0x1bd6530_0, 1, 1; -L_0x1bee100 .part RS_0x7f6a63aa0c18, 0, 1; -L_0x1bef080 .part/pv L_0x1beebf0, 2, 1, 4; -L_0x1bef170 .part/pv L_0x1beef40, 2, 1, 4; -L_0x1bef2b0 .part/pv L_0x1bee920, 2, 1, 4; -L_0x1bef3a0 .part v0x1bd6330_0, 2, 1; -L_0x1bef4a0 .part v0x1bd6530_0, 2, 1; -L_0x1bef5d0 .part RS_0x7f6a63aa0c18, 1, 1; -L_0x1bf0480 .part/pv L_0x1befff0, 3, 1, 4; -L_0x1bf0570 .part/pv L_0x1bf0340, 3, 1, 4; -L_0x1bf06e0 .part/pv L_0x1befd20, 3, 1, 4; -L_0x1bf07d0 .part v0x1bd6330_0, 3, 1; -L_0x1bf0900 .part v0x1bd6530_0, 3, 1; -L_0x1bf0a30 .part RS_0x7f6a63aa0c18, 2, 1; -L_0x1bf1a60 .part/pv L_0x1bf15b0, 0, 1, 4; -L_0x1bf1b50 .part/pv L_0x1bf1900, 0, 1, 4; -L_0x1bf0ad0 .part/pv L_0x1bf12e0, 0, 1, 4; -L_0x1bf1d40 .part v0x1bd6330_0, 0, 1; -L_0x1bf1c40 .part v0x1bd6530_0, 0, 1; -L_0x1bf1f30 .part RS_0x7f6a63aa0fa8, 0, 1; -L_0x1bf20a0 .part RS_0x7f6a63aa0c18, 3, 1; -L_0x1bf2340 .part RS_0x7f6a63aa0c18, 2, 1; -L_0x1bf2510 .part v0x1bd65b0_0, 1, 1; -L_0x1bf25b0 .part RS_0x7f6a63aa0fa8, 0, 1; -L_0x1bf2900 .part RS_0x7f6a63aa0be8, 3, 1; -L_0x1bf2ae0 .part RS_0x7f6a63aa0be8, 3, 1; -S_0x1bc58a0 .scope module, "attempt2" "MiddleAddSubSLT" 3 225, 3 89, S_0x1bc21e0; - .timescale -9 -12; -L_0x1bf0870/d .functor NOT 1, L_0x1bf1c40, C4<0>, C4<0>, C4<0>; -L_0x1bf0870 .delay (10000,10000,10000) L_0x1bf0870/d; -L_0x1bf1180/d .functor NOT 1, L_0x1bf1240, C4<0>, C4<0>, C4<0>; -L_0x1bf1180 .delay (10000,10000,10000) L_0x1bf1180/d; -L_0x1bf12e0/d .functor AND 1, L_0x1bf1420, L_0x1bf1180, C4<1>, C4<1>; -L_0x1bf12e0 .delay (20000,20000,20000) L_0x1bf12e0/d; -L_0x1bf14c0/d .functor XOR 1, L_0x1bf1d40, L_0x1bf0f10, C4<0>, C4<0>; -L_0x1bf14c0 .delay (40000,40000,40000) L_0x1bf14c0/d; -L_0x1bf15b0/d .functor XOR 1, L_0x1bf14c0, L_0x1bf1f30, C4<0>, C4<0>; -L_0x1bf15b0 .delay (40000,40000,40000) L_0x1bf15b0/d; -L_0x1bf16a0/d .functor AND 1, L_0x1bf1d40, L_0x1bf0f10, C4<1>, C4<1>; -L_0x1bf16a0 .delay (20000,20000,20000) L_0x1bf16a0/d; -L_0x1bf1810/d .functor AND 1, L_0x1bf14c0, L_0x1bf1f30, C4<1>, C4<1>; -L_0x1bf1810 .delay (20000,20000,20000) L_0x1bf1810/d; -L_0x1bf1900/d .functor OR 1, L_0x1bf16a0, L_0x1bf1810, C4<0>, C4<0>; -L_0x1bf1900 .delay (20000,20000,20000) L_0x1bf1900/d; -v0x1bc5f10_0 .net "A", 0 0, L_0x1bf1d40; 1 drivers -v0x1bc5fd0_0 .net "AandB", 0 0, L_0x1bf16a0; 1 drivers -v0x1bc6070_0 .net "AddSubSLTSum", 0 0, L_0x1bf15b0; 1 drivers -v0x1bc6110_0 .net "AxorB", 0 0, L_0x1bf14c0; 1 drivers -v0x1bc6190_0 .net "B", 0 0, L_0x1bf1c40; 1 drivers -v0x1bc6240_0 .net "BornB", 0 0, L_0x1bf0f10; 1 drivers -v0x1bc6300_0 .net "CINandAxorB", 0 0, L_0x1bf1810; 1 drivers -v0x1bc6380_0 .alias "Command", 2 0, v0x1bd5470_0; -v0x1bc6400_0 .net *"_s3", 0 0, L_0x1bf1240; 1 drivers -v0x1bc6480_0 .net *"_s5", 0 0, L_0x1bf1420; 1 drivers -v0x1bc6520_0 .net "carryin", 0 0, L_0x1bf1f30; 1 drivers -v0x1bc65c0_0 .net "carryout", 0 0, L_0x1bf1900; 1 drivers -v0x1bc6660_0 .net "nB", 0 0, L_0x1bf0870; 1 drivers -v0x1bc6710_0 .net "nCmd2", 0 0, L_0x1bf1180; 1 drivers -v0x1bc6810_0 .net "subtract", 0 0, L_0x1bf12e0; 1 drivers -L_0x1bf10e0 .part v0x1bd65b0_0, 0, 1; -L_0x1bf1240 .part v0x1bd65b0_0, 2, 1; -L_0x1bf1420 .part v0x1bd65b0_0, 0, 1; -S_0x1bc5990 .scope module, "mux0" "TwoInMux" 3 105, 3 8, S_0x1bc58a0; - .timescale -9 -12; -L_0x1bf0c30/d .functor NOT 1, L_0x1bf10e0, C4<0>, C4<0>, C4<0>; -L_0x1bf0c30 .delay (10000,10000,10000) L_0x1bf0c30/d; -L_0x1bf0cf0/d .functor AND 1, L_0x1bf1c40, L_0x1bf0c30, C4<1>, C4<1>; -L_0x1bf0cf0 .delay (20000,20000,20000) L_0x1bf0cf0/d; -L_0x1bf0e00/d .functor AND 1, L_0x1bf0870, L_0x1bf10e0, C4<1>, C4<1>; -L_0x1bf0e00 .delay (20000,20000,20000) L_0x1bf0e00/d; -L_0x1bf0f10/d .functor OR 1, L_0x1bf0cf0, L_0x1bf0e00, C4<0>, C4<0>; -L_0x1bf0f10 .delay (20000,20000,20000) L_0x1bf0f10/d; -v0x1bc5a80_0 .net "S", 0 0, L_0x1bf10e0; 1 drivers -v0x1bc5b40_0 .alias "in0", 0 0, v0x1bc6190_0; -v0x1bc5be0_0 .alias "in1", 0 0, v0x1bc6660_0; -v0x1bc5c80_0 .net "nS", 0 0, L_0x1bf0c30; 1 drivers -v0x1bc5d30_0 .net "out0", 0 0, L_0x1bf0cf0; 1 drivers -v0x1bc5dd0_0 .net "out1", 0 0, L_0x1bf0e00; 1 drivers -v0x1bc5e70_0 .alias "outfinal", 0 0, v0x1bc6240_0; -S_0x1bc4700 .scope generate, "addbits[1]" "addbits[1]" 3 230, 3 230, S_0x1bc21e0; - .timescale -9 -12; -P_0x1bc4118 .param/l "i" 3 230, +C4<01>; -S_0x1bc4870 .scope module, "attempt" "MiddleAddSubSLT" 3 232, 3 89, S_0x1bc4700; - .timescale -9 -12; -L_0x1becb20/d .functor NOT 1, L_0x1bedfd0, C4<0>, C4<0>, C4<0>; -L_0x1becb20 .delay (10000,10000,10000) L_0x1becb20/d; -L_0x1bed3c0/d .functor NOT 1, L_0x1bed460, C4<0>, C4<0>, C4<0>; -L_0x1bed3c0 .delay (10000,10000,10000) L_0x1bed3c0/d; -L_0x1bed500/d .functor AND 1, L_0x1bed640, L_0x1bed3c0, C4<1>, C4<1>; -L_0x1bed500 .delay (20000,20000,20000) L_0x1bed500/d; -L_0x1bed6e0/d .functor XOR 1, L_0x1bedf30, L_0x1bed190, C4<0>, C4<0>; -L_0x1bed6e0 .delay (40000,40000,40000) L_0x1bed6e0/d; -L_0x1bed7d0/d .functor XOR 1, L_0x1bed6e0, L_0x1bee100, C4<0>, C4<0>; -L_0x1bed7d0 .delay (40000,40000,40000) L_0x1bed7d0/d; -L_0x1bed8c0/d .functor AND 1, L_0x1bedf30, L_0x1bed190, C4<1>, C4<1>; -L_0x1bed8c0 .delay (20000,20000,20000) L_0x1bed8c0/d; -L_0x1beda30/d .functor AND 1, L_0x1bed6e0, L_0x1bee100, C4<1>, C4<1>; -L_0x1beda30 .delay (20000,20000,20000) L_0x1beda30/d; -L_0x1bedb20/d .functor OR 1, L_0x1bed8c0, L_0x1beda30, C4<0>, C4<0>; -L_0x1bedb20 .delay (20000,20000,20000) L_0x1bedb20/d; -v0x1bc4f00_0 .net "A", 0 0, L_0x1bedf30; 1 drivers -v0x1bc4fc0_0 .net "AandB", 0 0, L_0x1bed8c0; 1 drivers -v0x1bc5060_0 .net "AddSubSLTSum", 0 0, L_0x1bed7d0; 1 drivers -v0x1bc5100_0 .net "AxorB", 0 0, L_0x1bed6e0; 1 drivers -v0x1bc5180_0 .net "B", 0 0, L_0x1bedfd0; 1 drivers -v0x1bc5230_0 .net "BornB", 0 0, L_0x1bed190; 1 drivers -v0x1bc52f0_0 .net "CINandAxorB", 0 0, L_0x1beda30; 1 drivers -v0x1bc5370_0 .alias "Command", 2 0, v0x1bd5470_0; -v0x1bc53f0_0 .net *"_s3", 0 0, L_0x1bed460; 1 drivers -v0x1bc5470_0 .net *"_s5", 0 0, L_0x1bed640; 1 drivers -v0x1bc5510_0 .net "carryin", 0 0, L_0x1bee100; 1 drivers -v0x1bc55b0_0 .net "carryout", 0 0, L_0x1bedb20; 1 drivers -v0x1bc5650_0 .net "nB", 0 0, L_0x1becb20; 1 drivers -v0x1bc5700_0 .net "nCmd2", 0 0, L_0x1bed3c0; 1 drivers -v0x1bc5800_0 .net "subtract", 0 0, L_0x1bed500; 1 drivers -L_0x1bed320 .part v0x1bd65b0_0, 0, 1; -L_0x1bed460 .part v0x1bd65b0_0, 2, 1; -L_0x1bed640 .part v0x1bd65b0_0, 0, 1; -S_0x1bc4960 .scope module, "mux0" "TwoInMux" 3 105, 3 8, S_0x1bc4870; - .timescale -9 -12; -L_0x1becf10/d .functor NOT 1, L_0x1bed320, C4<0>, C4<0>, C4<0>; -L_0x1becf10 .delay (10000,10000,10000) L_0x1becf10/d; -L_0x1becfb0/d .functor AND 1, L_0x1bedfd0, L_0x1becf10, C4<1>, C4<1>; -L_0x1becfb0 .delay (20000,20000,20000) L_0x1becfb0/d; -L_0x1bed0a0/d .functor AND 1, L_0x1becb20, L_0x1bed320, C4<1>, C4<1>; -L_0x1bed0a0 .delay (20000,20000,20000) L_0x1bed0a0/d; -L_0x1bed190/d .functor OR 1, L_0x1becfb0, L_0x1bed0a0, C4<0>, C4<0>; -L_0x1bed190 .delay (20000,20000,20000) L_0x1bed190/d; -v0x1bc4a50_0 .net "S", 0 0, L_0x1bed320; 1 drivers -v0x1bc4af0_0 .alias "in0", 0 0, v0x1bc5180_0; -v0x1bc4b90_0 .alias "in1", 0 0, v0x1bc5650_0; -v0x1bc4c30_0 .net "nS", 0 0, L_0x1becf10; 1 drivers -v0x1bc4ce0_0 .net "out0", 0 0, L_0x1becfb0; 1 drivers -v0x1bc4d80_0 .net "out1", 0 0, L_0x1bed0a0; 1 drivers -v0x1bc4e60_0 .alias "outfinal", 0 0, v0x1bc5230_0; -S_0x1bc3560 .scope generate, "addbits[2]" "addbits[2]" 3 230, 3 230, S_0x1bc21e0; - .timescale -9 -12; -P_0x1bc2ee8 .param/l "i" 3 230, +C4<010>; -S_0x1bc36d0 .scope module, "attempt" "MiddleAddSubSLT" 3 232, 3 89, S_0x1bc3560; - .timescale -9 -12; -L_0x1bee1a0/d .functor NOT 1, L_0x1bef4a0, C4<0>, C4<0>, C4<0>; -L_0x1bee1a0 .delay (10000,10000,10000) L_0x1bee1a0/d; -L_0x1bee7e0/d .functor NOT 1, L_0x1bee880, C4<0>, C4<0>, C4<0>; -L_0x1bee7e0 .delay (10000,10000,10000) L_0x1bee7e0/d; -L_0x1bee920/d .functor AND 1, L_0x1beea60, L_0x1bee7e0, C4<1>, C4<1>; -L_0x1bee920 .delay (20000,20000,20000) L_0x1bee920/d; -L_0x1beeb00/d .functor XOR 1, L_0x1bef3a0, L_0x1bee5b0, C4<0>, C4<0>; -L_0x1beeb00 .delay (40000,40000,40000) L_0x1beeb00/d; -L_0x1beebf0/d .functor XOR 1, L_0x1beeb00, L_0x1bef5d0, C4<0>, C4<0>; -L_0x1beebf0 .delay (40000,40000,40000) L_0x1beebf0/d; -L_0x1beece0/d .functor AND 1, L_0x1bef3a0, L_0x1bee5b0, C4<1>, C4<1>; -L_0x1beece0 .delay (20000,20000,20000) L_0x1beece0/d; -L_0x1beee50/d .functor AND 1, L_0x1beeb00, L_0x1bef5d0, C4<1>, C4<1>; -L_0x1beee50 .delay (20000,20000,20000) L_0x1beee50/d; -L_0x1beef40/d .functor OR 1, L_0x1beece0, L_0x1beee50, C4<0>, C4<0>; -L_0x1beef40 .delay (20000,20000,20000) L_0x1beef40/d; -v0x1bc3d60_0 .net "A", 0 0, L_0x1bef3a0; 1 drivers -v0x1bc3e20_0 .net "AandB", 0 0, L_0x1beece0; 1 drivers -v0x1bc3ec0_0 .net "AddSubSLTSum", 0 0, L_0x1beebf0; 1 drivers -v0x1bc3f60_0 .net "AxorB", 0 0, L_0x1beeb00; 1 drivers -v0x1bc3fe0_0 .net "B", 0 0, L_0x1bef4a0; 1 drivers -v0x1bc4090_0 .net "BornB", 0 0, L_0x1bee5b0; 1 drivers -v0x1bc4150_0 .net "CINandAxorB", 0 0, L_0x1beee50; 1 drivers -v0x1bc41d0_0 .alias "Command", 2 0, v0x1bd5470_0; -v0x1bc4250_0 .net *"_s3", 0 0, L_0x1bee880; 1 drivers -v0x1bc42d0_0 .net *"_s5", 0 0, L_0x1beea60; 1 drivers -v0x1bc4370_0 .net "carryin", 0 0, L_0x1bef5d0; 1 drivers -v0x1bc4410_0 .net "carryout", 0 0, L_0x1beef40; 1 drivers -v0x1bc44b0_0 .net "nB", 0 0, L_0x1bee1a0; 1 drivers -v0x1bc4560_0 .net "nCmd2", 0 0, L_0x1bee7e0; 1 drivers -v0x1bc4660_0 .net "subtract", 0 0, L_0x1bee920; 1 drivers -L_0x1bee740 .part v0x1bd65b0_0, 0, 1; -L_0x1bee880 .part v0x1bd65b0_0, 2, 1; -L_0x1beea60 .part v0x1bd65b0_0, 0, 1; -S_0x1bc37c0 .scope module, "mux0" "TwoInMux" 3 105, 3 8, S_0x1bc36d0; - .timescale -9 -12; -L_0x1bee330/d .functor NOT 1, L_0x1bee740, C4<0>, C4<0>, C4<0>; -L_0x1bee330 .delay (10000,10000,10000) L_0x1bee330/d; -L_0x1bee3d0/d .functor AND 1, L_0x1bef4a0, L_0x1bee330, C4<1>, C4<1>; -L_0x1bee3d0 .delay (20000,20000,20000) L_0x1bee3d0/d; -L_0x1bee4c0/d .functor AND 1, L_0x1bee1a0, L_0x1bee740, C4<1>, C4<1>; -L_0x1bee4c0 .delay (20000,20000,20000) L_0x1bee4c0/d; -L_0x1bee5b0/d .functor OR 1, L_0x1bee3d0, L_0x1bee4c0, C4<0>, C4<0>; -L_0x1bee5b0 .delay (20000,20000,20000) L_0x1bee5b0/d; -v0x1bc38b0_0 .net "S", 0 0, L_0x1bee740; 1 drivers -v0x1bc3950_0 .alias "in0", 0 0, v0x1bc3fe0_0; -v0x1bc39f0_0 .alias "in1", 0 0, v0x1bc44b0_0; -v0x1bc3a90_0 .net "nS", 0 0, L_0x1bee330; 1 drivers -v0x1bc3b40_0 .net "out0", 0 0, L_0x1bee3d0; 1 drivers -v0x1bc3be0_0 .net "out1", 0 0, L_0x1bee4c0; 1 drivers -v0x1bc3cc0_0 .alias "outfinal", 0 0, v0x1bc4090_0; -S_0x1bc2350 .scope generate, "addbits[3]" "addbits[3]" 3 230, 3 230, S_0x1bc21e0; - .timescale -9 -12; -P_0x1bc2448 .param/l "i" 3 230, +C4<011>; -S_0x1bc24c0 .scope module, "attempt" "MiddleAddSubSLT" 3 232, 3 89, S_0x1bc2350; - .timescale -9 -12; -L_0x1bef440/d .functor NOT 1, L_0x1bf0900, C4<0>, C4<0>, C4<0>; -L_0x1bef440 .delay (10000,10000,10000) L_0x1bef440/d; -L_0x1befbe0/d .functor NOT 1, L_0x1befc80, C4<0>, C4<0>, C4<0>; -L_0x1befbe0 .delay (10000,10000,10000) L_0x1befbe0/d; -L_0x1befd20/d .functor AND 1, L_0x1befe60, L_0x1befbe0, C4<1>, C4<1>; -L_0x1befd20 .delay (20000,20000,20000) L_0x1befd20/d; -L_0x1beff00/d .functor XOR 1, L_0x1bf07d0, L_0x1bef9b0, C4<0>, C4<0>; -L_0x1beff00 .delay (40000,40000,40000) L_0x1beff00/d; -L_0x1befff0/d .functor XOR 1, L_0x1beff00, L_0x1bf0a30, C4<0>, C4<0>; -L_0x1befff0 .delay (40000,40000,40000) L_0x1befff0/d; -L_0x1bf00e0/d .functor AND 1, L_0x1bf07d0, L_0x1bef9b0, C4<1>, C4<1>; -L_0x1bf00e0 .delay (20000,20000,20000) L_0x1bf00e0/d; -L_0x1bf0250/d .functor AND 1, L_0x1beff00, L_0x1bf0a30, C4<1>, C4<1>; -L_0x1bf0250 .delay (20000,20000,20000) L_0x1bf0250/d; -L_0x1bf0340/d .functor OR 1, L_0x1bf00e0, L_0x1bf0250, C4<0>, C4<0>; -L_0x1bf0340 .delay (20000,20000,20000) L_0x1bf0340/d; -v0x1bc2b30_0 .net "A", 0 0, L_0x1bf07d0; 1 drivers -v0x1bc2bf0_0 .net "AandB", 0 0, L_0x1bf00e0; 1 drivers -v0x1bc2c90_0 .net "AddSubSLTSum", 0 0, L_0x1befff0; 1 drivers -v0x1bc2d30_0 .net "AxorB", 0 0, L_0x1beff00; 1 drivers -v0x1bc2db0_0 .net "B", 0 0, L_0x1bf0900; 1 drivers -v0x1bc2e60_0 .net "BornB", 0 0, L_0x1bef9b0; 1 drivers -v0x1bc2f20_0 .net "CINandAxorB", 0 0, L_0x1bf0250; 1 drivers -v0x1bc2fa0_0 .alias "Command", 2 0, v0x1bd5470_0; -v0x1bc3020_0 .net *"_s3", 0 0, L_0x1befc80; 1 drivers -v0x1bc30a0_0 .net *"_s5", 0 0, L_0x1befe60; 1 drivers -v0x1bc3180_0 .net "carryin", 0 0, L_0x1bf0a30; 1 drivers -v0x1bc3200_0 .net "carryout", 0 0, L_0x1bf0340; 1 drivers -v0x1bc3310_0 .net "nB", 0 0, L_0x1bef440; 1 drivers -v0x1bc33c0_0 .net "nCmd2", 0 0, L_0x1befbe0; 1 drivers -v0x1bc34c0_0 .net "subtract", 0 0, L_0x1befd20; 1 drivers -L_0x1befb40 .part v0x1bd65b0_0, 0, 1; -L_0x1befc80 .part v0x1bd65b0_0, 2, 1; -L_0x1befe60 .part v0x1bd65b0_0, 0, 1; -S_0x1bc25b0 .scope module, "mux0" "TwoInMux" 3 105, 3 8, S_0x1bc24c0; - .timescale -9 -12; -L_0x1bef770/d .functor NOT 1, L_0x1befb40, C4<0>, C4<0>, C4<0>; -L_0x1bef770 .delay (10000,10000,10000) L_0x1bef770/d; -L_0x1bef7d0/d .functor AND 1, L_0x1bf0900, L_0x1bef770, C4<1>, C4<1>; -L_0x1bef7d0 .delay (20000,20000,20000) L_0x1bef7d0/d; -L_0x1bef8c0/d .functor AND 1, L_0x1bef440, L_0x1befb40, C4<1>, C4<1>; -L_0x1bef8c0 .delay (20000,20000,20000) L_0x1bef8c0/d; -L_0x1bef9b0/d .functor OR 1, L_0x1bef7d0, L_0x1bef8c0, C4<0>, C4<0>; -L_0x1bef9b0 .delay (20000,20000,20000) L_0x1bef9b0/d; -v0x1bc26a0_0 .net "S", 0 0, L_0x1befb40; 1 drivers -v0x1bc2720_0 .alias "in0", 0 0, v0x1bc2db0_0; -v0x1bc27c0_0 .alias "in1", 0 0, v0x1bc3310_0; -v0x1bc2860_0 .net "nS", 0 0, L_0x1bef770; 1 drivers -v0x1bc2910_0 .net "out0", 0 0, L_0x1bef7d0; 1 drivers -v0x1bc29b0_0 .net "out1", 0 0, L_0x1bef8c0; 1 drivers -v0x1bc2a90_0 .alias "outfinal", 0 0, v0x1bc2e60_0; -S_0x1bbefa0 .scope module, "trial1" "AndNand32" 3 280, 3 154, S_0x1b51ae0; - .timescale -9 -12; -P_0x1bbea28 .param/l "size" 3 161, +C4<0100>; -v0x1bbee90_0 .alias "A", 3 0, v0x1bd5250_0; -v0x1bc2000_0 .alias "AndNandOut", 3 0, v0x1bd64b0_0; -v0x1bc2080_0 .alias "B", 3 0, v0x1bd5370_0; -v0x1bc2130_0 .alias "Command", 2 0, v0x1bd5470_0; -L_0x1bf3890 .part/pv L_0x1bf3620, 1, 1, 4; -L_0x1bf3950 .part v0x1bd6330_0, 1, 1; -L_0x1bf39f0 .part v0x1bd6530_0, 1, 1; -L_0x1bf4300 .part/pv L_0x1bf4090, 2, 1, 4; -L_0x1bf43a0 .part v0x1bd6330_0, 2, 1; -L_0x1bf4440 .part v0x1bd6530_0, 2, 1; -L_0x1bf4d70 .part/pv L_0x1bf4b00, 3, 1, 4; -L_0x1be6650 .part v0x1bd6330_0, 3, 1; -L_0x1bf5020 .part v0x1bd6530_0, 3, 1; -L_0x1bf58d0 .part/pv L_0x1bf5660, 0, 1, 4; -L_0x1bf59d0 .part v0x1bd6330_0, 0, 1; -L_0x1bf5a70 .part v0x1bd6530_0, 0, 1; -S_0x1bc14c0 .scope module, "attempt2" "AndNand" 3 165, 3 48, S_0x1bbefa0; - .timescale -9 -12; -L_0x1bf5110/d .functor NAND 1, L_0x1bf59d0, L_0x1bf5a70, C4<1>, C4<1>; -L_0x1bf5110 .delay (10000,10000,10000) L_0x1bf5110/d; -L_0x1bf5210/d .functor NOT 1, L_0x1bf5110, C4<0>, C4<0>, C4<0>; -L_0x1bf5210 .delay (10000,10000,10000) L_0x1bf5210/d; -v0x1bc1ae0_0 .net "A", 0 0, L_0x1bf59d0; 1 drivers -v0x1bc1ba0_0 .net "AandB", 0 0, L_0x1bf5210; 1 drivers -v0x1bc1c20_0 .net "AnandB", 0 0, L_0x1bf5110; 1 drivers -v0x1bc1cd0_0 .net "AndNandOut", 0 0, L_0x1bf5660; 1 drivers -v0x1bc1db0_0 .net "B", 0 0, L_0x1bf5a70; 1 drivers -v0x1bc1e30_0 .alias "Command", 2 0, v0x1bd5470_0; -L_0x1bf5830 .part v0x1bd65b0_0, 0, 1; -S_0x1bc15b0 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0x1bc14c0; - .timescale -9 -12; -L_0x1bf5340/d .functor NOT 1, L_0x1bf5830, C4<0>, C4<0>, C4<0>; -L_0x1bf5340 .delay (10000,10000,10000) L_0x1bf5340/d; -L_0x1bf5400/d .functor AND 1, L_0x1bf5210, L_0x1bf5340, C4<1>, C4<1>; -L_0x1bf5400 .delay (20000,20000,20000) L_0x1bf5400/d; -L_0x1bf5510/d .functor AND 1, L_0x1bf5110, L_0x1bf5830, C4<1>, C4<1>; -L_0x1bf5510 .delay (20000,20000,20000) L_0x1bf5510/d; -L_0x1bf5660/d .functor OR 1, L_0x1bf5400, L_0x1bf5510, C4<0>, C4<0>; -L_0x1bf5660 .delay (20000,20000,20000) L_0x1bf5660/d; -v0x1bc16a0_0 .net "S", 0 0, L_0x1bf5830; 1 drivers -v0x1bc1720_0 .alias "in0", 0 0, v0x1bc1ba0_0; -v0x1bc17a0_0 .alias "in1", 0 0, v0x1bc1c20_0; -v0x1bc1840_0 .net "nS", 0 0, L_0x1bf5340; 1 drivers -v0x1bc18c0_0 .net "out0", 0 0, L_0x1bf5400; 1 drivers -v0x1bc1960_0 .net "out1", 0 0, L_0x1bf5510; 1 drivers -v0x1bc1a40_0 .alias "outfinal", 0 0, v0x1bc1cd0_0; -S_0x1bc0900 .scope generate, "andbits[1]" "andbits[1]" 3 169, 3 169, S_0x1bbefa0; - .timescale -9 -12; -P_0x1bc09f8 .param/l "i" 3 169, +C4<01>; -S_0x1bc0a70 .scope module, "attempt" "AndNand" 3 171, 3 48, S_0x1bc0900; - .timescale -9 -12; -L_0x1bf3110/d .functor NAND 1, L_0x1bf3950, L_0x1bf39f0, C4<1>, C4<1>; -L_0x1bf3110 .delay (10000,10000,10000) L_0x1bf3110/d; -L_0x1bf31d0/d .functor NOT 1, L_0x1bf3110, C4<0>, C4<0>, C4<0>; -L_0x1bf31d0 .delay (10000,10000,10000) L_0x1bf31d0/d; -v0x1bc10b0_0 .net "A", 0 0, L_0x1bf3950; 1 drivers -v0x1bc1170_0 .net "AandB", 0 0, L_0x1bf31d0; 1 drivers -v0x1bc11f0_0 .net "AnandB", 0 0, L_0x1bf3110; 1 drivers -v0x1bc12a0_0 .net "AndNandOut", 0 0, L_0x1bf3620; 1 drivers -v0x1bc1380_0 .net "B", 0 0, L_0x1bf39f0; 1 drivers -v0x1bc1400_0 .alias "Command", 2 0, v0x1bd5470_0; -L_0x1bf37f0 .part v0x1bd65b0_0, 0, 1; -S_0x1bc0b60 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0x1bc0a70; - .timescale -9 -12; -L_0x1bf3300/d .functor NOT 1, L_0x1bf37f0, C4<0>, C4<0>, C4<0>; -L_0x1bf3300 .delay (10000,10000,10000) L_0x1bf3300/d; -L_0x1bf33c0/d .functor AND 1, L_0x1bf31d0, L_0x1bf3300, C4<1>, C4<1>; -L_0x1bf33c0 .delay (20000,20000,20000) L_0x1bf33c0/d; -L_0x1bf34d0/d .functor AND 1, L_0x1bf3110, L_0x1bf37f0, C4<1>, C4<1>; -L_0x1bf34d0 .delay (20000,20000,20000) L_0x1bf34d0/d; -L_0x1bf3620/d .functor OR 1, L_0x1bf33c0, L_0x1bf34d0, C4<0>, C4<0>; -L_0x1bf3620 .delay (20000,20000,20000) L_0x1bf3620/d; -v0x1bc0c50_0 .net "S", 0 0, L_0x1bf37f0; 1 drivers -v0x1bc0cd0_0 .alias "in0", 0 0, v0x1bc1170_0; -v0x1bc0d70_0 .alias "in1", 0 0, v0x1bc11f0_0; -v0x1bc0e10_0 .net "nS", 0 0, L_0x1bf3300; 1 drivers -v0x1bc0e90_0 .net "out0", 0 0, L_0x1bf33c0; 1 drivers -v0x1bc0f30_0 .net "out1", 0 0, L_0x1bf34d0; 1 drivers -v0x1bc1010_0 .alias "outfinal", 0 0, v0x1bc12a0_0; -S_0x1bbfd40 .scope generate, "andbits[2]" "andbits[2]" 3 169, 3 169, S_0x1bbefa0; - .timescale -9 -12; -P_0x1bbfe38 .param/l "i" 3 169, +C4<010>; -S_0x1bbfeb0 .scope module, "attempt" "AndNand" 3 171, 3 48, S_0x1bbfd40; - .timescale -9 -12; -L_0x1bf3ae0/d .functor NAND 1, L_0x1bf43a0, L_0x1bf4440, C4<1>, C4<1>; -L_0x1bf3ae0 .delay (10000,10000,10000) L_0x1bf3ae0/d; -L_0x1bf3c40/d .functor NOT 1, L_0x1bf3ae0, C4<0>, C4<0>, C4<0>; -L_0x1bf3c40 .delay (10000,10000,10000) L_0x1bf3c40/d; -v0x1bc04f0_0 .net "A", 0 0, L_0x1bf43a0; 1 drivers -v0x1bc05b0_0 .net "AandB", 0 0, L_0x1bf3c40; 1 drivers -v0x1bc0630_0 .net "AnandB", 0 0, L_0x1bf3ae0; 1 drivers -v0x1bc06e0_0 .net "AndNandOut", 0 0, L_0x1bf4090; 1 drivers -v0x1bc07c0_0 .net "B", 0 0, L_0x1bf4440; 1 drivers -v0x1bc0840_0 .alias "Command", 2 0, v0x1bd5470_0; -L_0x1bf4260 .part v0x1bd65b0_0, 0, 1; -S_0x1bbffa0 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0x1bbfeb0; - .timescale -9 -12; -L_0x1bf3d70/d .functor NOT 1, L_0x1bf4260, C4<0>, C4<0>, C4<0>; -L_0x1bf3d70 .delay (10000,10000,10000) L_0x1bf3d70/d; -L_0x1bf3e30/d .functor AND 1, L_0x1bf3c40, L_0x1bf3d70, C4<1>, C4<1>; -L_0x1bf3e30 .delay (20000,20000,20000) L_0x1bf3e30/d; -L_0x1bf3f40/d .functor AND 1, L_0x1bf3ae0, L_0x1bf4260, C4<1>, C4<1>; -L_0x1bf3f40 .delay (20000,20000,20000) L_0x1bf3f40/d; -L_0x1bf4090/d .functor OR 1, L_0x1bf3e30, L_0x1bf3f40, C4<0>, C4<0>; -L_0x1bf4090 .delay (20000,20000,20000) L_0x1bf4090/d; -v0x1bc0090_0 .net "S", 0 0, L_0x1bf4260; 1 drivers -v0x1bc0110_0 .alias "in0", 0 0, v0x1bc05b0_0; -v0x1bc01b0_0 .alias "in1", 0 0, v0x1bc0630_0; -v0x1bc0250_0 .net "nS", 0 0, L_0x1bf3d70; 1 drivers -v0x1bc02d0_0 .net "out0", 0 0, L_0x1bf3e30; 1 drivers -v0x1bc0370_0 .net "out1", 0 0, L_0x1bf3f40; 1 drivers -v0x1bc0450_0 .alias "outfinal", 0 0, v0x1bc06e0_0; -S_0x1bbf110 .scope generate, "andbits[3]" "andbits[3]" 3 169, 3 169, S_0x1bbefa0; - .timescale -9 -12; -P_0x1bbf208 .param/l "i" 3 169, +C4<011>; -S_0x1bbf2a0 .scope module, "attempt" "AndNand" 3 171, 3 48, S_0x1bbf110; - .timescale -9 -12; -L_0x1bf4570/d .functor NAND 1, L_0x1be6650, L_0x1bf5020, C4<1>, C4<1>; -L_0x1bf4570 .delay (10000,10000,10000) L_0x1bf4570/d; -L_0x1bf46b0/d .functor NOT 1, L_0x1bf4570, C4<0>, C4<0>, C4<0>; -L_0x1bf46b0 .delay (10000,10000,10000) L_0x1bf46b0/d; -v0x1bbf930_0 .net "A", 0 0, L_0x1be6650; 1 drivers -v0x1bbf9f0_0 .net "AandB", 0 0, L_0x1bf46b0; 1 drivers -v0x1bbfa70_0 .net "AnandB", 0 0, L_0x1bf4570; 1 drivers -v0x1bbfb20_0 .net "AndNandOut", 0 0, L_0x1bf4b00; 1 drivers -v0x1bbfc00_0 .net "B", 0 0, L_0x1bf5020; 1 drivers -v0x1bbfc80_0 .alias "Command", 2 0, v0x1bd5470_0; -L_0x1bf4cd0 .part v0x1bd65b0_0, 0, 1; -S_0x1bbf390 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0x1bbf2a0; - .timescale -9 -12; -L_0x1bf47e0/d .functor NOT 1, L_0x1bf4cd0, C4<0>, C4<0>, C4<0>; -L_0x1bf47e0 .delay (10000,10000,10000) L_0x1bf47e0/d; -L_0x1bf48a0/d .functor AND 1, L_0x1bf46b0, L_0x1bf47e0, C4<1>, C4<1>; -L_0x1bf48a0 .delay (20000,20000,20000) L_0x1bf48a0/d; -L_0x1bf49b0/d .functor AND 1, L_0x1bf4570, L_0x1bf4cd0, C4<1>, C4<1>; -L_0x1bf49b0 .delay (20000,20000,20000) L_0x1bf49b0/d; -L_0x1bf4b00/d .functor OR 1, L_0x1bf48a0, L_0x1bf49b0, C4<0>, C4<0>; -L_0x1bf4b00 .delay (20000,20000,20000) L_0x1bf4b00/d; -v0x1bbf480_0 .net "S", 0 0, L_0x1bf4cd0; 1 drivers -v0x1bbf520_0 .alias "in0", 0 0, v0x1bbf9f0_0; -v0x1bbf5c0_0 .alias "in1", 0 0, v0x1bbfa70_0; -v0x1bbf660_0 .net "nS", 0 0, L_0x1bf47e0; 1 drivers -v0x1bbf710_0 .net "out0", 0 0, L_0x1bf48a0; 1 drivers -v0x1bbf7b0_0 .net "out1", 0 0, L_0x1bf49b0; 1 drivers -v0x1bbf890_0 .alias "outfinal", 0 0, v0x1bbfb20_0; -S_0x1bb9d80 .scope module, "trial2" "OrNorXor32" 3 281, 3 177, S_0x1b51ae0; - .timescale -9 -12; -P_0x1bb8ed8 .param/l "size" 3 184, +C4<0100>; -v0x1bbed10_0 .alias "A", 3 0, v0x1bd5250_0; -v0x1bbed90_0 .alias "B", 3 0, v0x1bd5370_0; -v0x1bbee10_0 .alias "Command", 2 0, v0x1bd5470_0; -v0x1bbef20_0 .alias "OrNorXorOut", 3 0, v0x1bd66b0_0; -L_0x1bf6c20 .part/pv L_0x1bf69b0, 1, 1, 4; -L_0x1bf6cc0 .part v0x1bd6330_0, 1, 1; -L_0x1bf6d60 .part v0x1bd6530_0, 1, 1; -L_0x1bf7f20 .part/pv L_0x1bf7cb0, 2, 1, 4; -L_0x1bf7fc0 .part v0x1bd6330_0, 2, 1; -L_0x1bf8060 .part v0x1bd6530_0, 2, 1; -L_0x1bf9220 .part/pv L_0x1bf8fb0, 3, 1, 4; -L_0x1bf92c0 .part v0x1bd6330_0, 3, 1; -L_0x1bf9360 .part v0x1bd6530_0, 3, 1; -L_0x1bfa510 .part/pv L_0x1bfa2a0, 0, 1, 4; -L_0x1bfa610 .part v0x1bd6330_0, 0, 1; -L_0x1bfa6b0 .part v0x1bd6530_0, 0, 1; -S_0x1bbdb00 .scope module, "attempt2" "OrNorXor" 3 192, 3 64, S_0x1bb9d80; - .timescale -9 -12; -L_0x1bf9400/d .functor NOR 1, L_0x1bfa610, L_0x1bfa6b0, C4<0>, C4<0>; -L_0x1bf9400 .delay (10000,10000,10000) L_0x1bf9400/d; -L_0x1bf9500/d .functor NOT 1, L_0x1bf9400, C4<0>, C4<0>, C4<0>; -L_0x1bf9500 .delay (10000,10000,10000) L_0x1bf9500/d; -L_0x1bf9630/d .functor NAND 1, L_0x1bfa610, L_0x1bfa6b0, C4<1>, C4<1>; -L_0x1bf9630 .delay (10000,10000,10000) L_0x1bf9630/d; -L_0x1bf9790/d .functor NAND 1, L_0x1bf9630, L_0x1bf9500, C4<1>, C4<1>; -L_0x1bf9790 .delay (10000,10000,10000) L_0x1bf9790/d; -L_0x1bf98a0/d .functor NOT 1, L_0x1bf9790, C4<0>, C4<0>, C4<0>; -L_0x1bf98a0 .delay (10000,10000,10000) L_0x1bf98a0/d; -v0x1bbe650_0 .net "A", 0 0, L_0x1bfa610; 1 drivers -v0x1bbe6f0_0 .net "AnandB", 0 0, L_0x1bf9630; 1 drivers -v0x1bbe790_0 .net "AnorB", 0 0, L_0x1bf9400; 1 drivers -v0x1bbe810_0 .net "AorB", 0 0, L_0x1bf9500; 1 drivers -v0x1bbe8f0_0 .net "AxorB", 0 0, L_0x1bf98a0; 1 drivers -v0x1bbe9a0_0 .net "B", 0 0, L_0x1bfa6b0; 1 drivers -v0x1bbea60_0 .alias "Command", 2 0, v0x1bd5470_0; -v0x1bbeae0_0 .net "OrNorXorOut", 0 0, L_0x1bfa2a0; 1 drivers -v0x1bbeb60_0 .net "XorNor", 0 0, L_0x1bf9d20; 1 drivers -v0x1bbec30_0 .net "nXor", 0 0, L_0x1bf9790; 1 drivers -L_0x1bf9ea0 .part v0x1bd65b0_0, 2, 1; -L_0x1bfa470 .part v0x1bd65b0_0, 0, 1; -S_0x1bbe0e0 .scope module, "mux0" "TwoInMux" 3 83, 3 8, S_0x1bbdb00; - .timescale -9 -12; -L_0x1bf9a00/d .functor NOT 1, L_0x1bf9ea0, C4<0>, C4<0>, C4<0>; -L_0x1bf9a00 .delay (10000,10000,10000) L_0x1bf9a00/d; -L_0x1bf9ac0/d .functor AND 1, L_0x1bf98a0, L_0x1bf9a00, C4<1>, C4<1>; -L_0x1bf9ac0 .delay (20000,20000,20000) L_0x1bf9ac0/d; -L_0x1bf9bd0/d .functor AND 1, L_0x1bf9400, L_0x1bf9ea0, C4<1>, C4<1>; -L_0x1bf9bd0 .delay (20000,20000,20000) L_0x1bf9bd0/d; -L_0x1bf9d20/d .functor OR 1, L_0x1bf9ac0, L_0x1bf9bd0, C4<0>, C4<0>; -L_0x1bf9d20 .delay (20000,20000,20000) L_0x1bf9d20/d; -v0x1bbe1d0_0 .net "S", 0 0, L_0x1bf9ea0; 1 drivers -v0x1bbe290_0 .alias "in0", 0 0, v0x1bbe8f0_0; -v0x1bbe330_0 .alias "in1", 0 0, v0x1bbe790_0; -v0x1bbe3d0_0 .net "nS", 0 0, L_0x1bf9a00; 1 drivers -v0x1bbe450_0 .net "out0", 0 0, L_0x1bf9ac0; 1 drivers -v0x1bbe4f0_0 .net "out1", 0 0, L_0x1bf9bd0; 1 drivers -v0x1bbe5d0_0 .alias "outfinal", 0 0, v0x1bbeb60_0; -S_0x1bbdbf0 .scope module, "mux1" "TwoInMux" 3 84, 3 8, S_0x1bbdb00; - .timescale -9 -12; -L_0x1bf9f40/d .functor NOT 1, L_0x1bfa470, C4<0>, C4<0>, C4<0>; -L_0x1bf9f40 .delay (10000,10000,10000) L_0x1bf9f40/d; -L_0x1bfa000/d .functor AND 1, L_0x1bf9d20, L_0x1bf9f40, C4<1>, C4<1>; -L_0x1bfa000 .delay (20000,20000,20000) L_0x1bfa000/d; -L_0x1bfa150/d .functor AND 1, L_0x1bf9500, L_0x1bfa470, C4<1>, C4<1>; -L_0x1bfa150 .delay (20000,20000,20000) L_0x1bfa150/d; -L_0x1bfa2a0/d .functor OR 1, L_0x1bfa000, L_0x1bfa150, C4<0>, C4<0>; -L_0x1bfa2a0 .delay (20000,20000,20000) L_0x1bfa2a0/d; -v0x1bbdce0_0 .net "S", 0 0, L_0x1bfa470; 1 drivers -v0x1bbdd60_0 .alias "in0", 0 0, v0x1bbeb60_0; -v0x1bbdde0_0 .alias "in1", 0 0, v0x1bbe810_0; -v0x1bbde80_0 .net "nS", 0 0, L_0x1bf9f40; 1 drivers -v0x1bbdf00_0 .net "out0", 0 0, L_0x1bfa000; 1 drivers -v0x1bbdfa0_0 .net "out1", 0 0, L_0x1bfa150; 1 drivers -v0x1bbe040_0 .alias "outfinal", 0 0, v0x1bbeae0_0; -S_0x1bbc700 .scope generate, "orbits[1]" "orbits[1]" 3 196, 3 196, S_0x1bb9d80; - .timescale -9 -12; -P_0x1bbc3e8 .param/l "i" 3 196, +C4<01>; -S_0x1bbc830 .scope module, "attempt" "OrNorXor" 3 198, 3 64, S_0x1bbc700; - .timescale -9 -12; -L_0x1bf5970/d .functor NOR 1, L_0x1bf6cc0, L_0x1bf6d60, C4<0>, C4<0>; -L_0x1bf5970 .delay (10000,10000,10000) L_0x1bf5970/d; -L_0x1bf5c10/d .functor NOT 1, L_0x1bf5970, C4<0>, C4<0>, C4<0>; -L_0x1bf5c10 .delay (10000,10000,10000) L_0x1bf5c10/d; -L_0x1bf5d40/d .functor NAND 1, L_0x1bf6cc0, L_0x1bf6d60, C4<1>, C4<1>; -L_0x1bf5d40 .delay (10000,10000,10000) L_0x1bf5d40/d; -L_0x1bf5ea0/d .functor NAND 1, L_0x1bf5d40, L_0x1bf5c10, C4<1>, C4<1>; -L_0x1bf5ea0 .delay (10000,10000,10000) L_0x1bf5ea0/d; -L_0x1bf5fb0/d .functor NOT 1, L_0x1bf5ea0, C4<0>, C4<0>, C4<0>; -L_0x1bf5fb0 .delay (10000,10000,10000) L_0x1bf5fb0/d; -v0x1bbd3c0_0 .net "A", 0 0, L_0x1bf6cc0; 1 drivers -v0x1bbd460_0 .net "AnandB", 0 0, L_0x1bf5d40; 1 drivers -v0x1bbd500_0 .net "AnorB", 0 0, L_0x1bf5970; 1 drivers -v0x1bbd5b0_0 .net "AorB", 0 0, L_0x1bf5c10; 1 drivers -v0x1bbd690_0 .net "AxorB", 0 0, L_0x1bf5fb0; 1 drivers -v0x1bbd740_0 .net "B", 0 0, L_0x1bf6d60; 1 drivers -v0x1bbd800_0 .alias "Command", 2 0, v0x1bd5470_0; -v0x1bbd880_0 .net "OrNorXorOut", 0 0, L_0x1bf69b0; 1 drivers -v0x1bbd950_0 .net "XorNor", 0 0, L_0x1bf6430; 1 drivers -v0x1bbda20_0 .net "nXor", 0 0, L_0x1bf5ea0; 1 drivers -L_0x1bf65b0 .part v0x1bd65b0_0, 2, 1; -L_0x1bf6b80 .part v0x1bd65b0_0, 0, 1; -S_0x1bbce50 .scope module, "mux0" "TwoInMux" 3 83, 3 8, S_0x1bbc830; - .timescale -9 -12; -L_0x1bf6110/d .functor NOT 1, L_0x1bf65b0, C4<0>, C4<0>, C4<0>; -L_0x1bf6110 .delay (10000,10000,10000) L_0x1bf6110/d; -L_0x1bf61d0/d .functor AND 1, L_0x1bf5fb0, L_0x1bf6110, C4<1>, C4<1>; -L_0x1bf61d0 .delay (20000,20000,20000) L_0x1bf61d0/d; -L_0x1bf62e0/d .functor AND 1, L_0x1bf5970, L_0x1bf65b0, C4<1>, C4<1>; -L_0x1bf62e0 .delay (20000,20000,20000) L_0x1bf62e0/d; -L_0x1bf6430/d .functor OR 1, L_0x1bf61d0, L_0x1bf62e0, C4<0>, C4<0>; -L_0x1bf6430 .delay (20000,20000,20000) L_0x1bf6430/d; -v0x1bbcf40_0 .net "S", 0 0, L_0x1bf65b0; 1 drivers -v0x1bbd000_0 .alias "in0", 0 0, v0x1bbd690_0; -v0x1bbd0a0_0 .alias "in1", 0 0, v0x1bbd500_0; -v0x1bbd140_0 .net "nS", 0 0, L_0x1bf6110; 1 drivers -v0x1bbd1c0_0 .net "out0", 0 0, L_0x1bf61d0; 1 drivers -v0x1bbd260_0 .net "out1", 0 0, L_0x1bf62e0; 1 drivers -v0x1bbd340_0 .alias "outfinal", 0 0, v0x1bbd950_0; -S_0x1bbc920 .scope module, "mux1" "TwoInMux" 3 84, 3 8, S_0x1bbc830; - .timescale -9 -12; -L_0x1bf6650/d .functor NOT 1, L_0x1bf6b80, C4<0>, C4<0>, C4<0>; -L_0x1bf6650 .delay (10000,10000,10000) L_0x1bf6650/d; -L_0x1bf6710/d .functor AND 1, L_0x1bf6430, L_0x1bf6650, C4<1>, C4<1>; -L_0x1bf6710 .delay (20000,20000,20000) L_0x1bf6710/d; -L_0x1bf6860/d .functor AND 1, L_0x1bf5c10, L_0x1bf6b80, C4<1>, C4<1>; -L_0x1bf6860 .delay (20000,20000,20000) L_0x1bf6860/d; -L_0x1bf69b0/d .functor OR 1, L_0x1bf6710, L_0x1bf6860, C4<0>, C4<0>; -L_0x1bf69b0 .delay (20000,20000,20000) L_0x1bf69b0/d; -v0x1bbca10_0 .net "S", 0 0, L_0x1bf6b80; 1 drivers -v0x1bbca90_0 .alias "in0", 0 0, v0x1bbd950_0; -v0x1bbcb10_0 .alias "in1", 0 0, v0x1bbd5b0_0; -v0x1bbcbb0_0 .net "nS", 0 0, L_0x1bf6650; 1 drivers -v0x1bbcc30_0 .net "out0", 0 0, L_0x1bf6710; 1 drivers -v0x1bbccd0_0 .net "out1", 0 0, L_0x1bf6860; 1 drivers -v0x1bbcdb0_0 .alias "outfinal", 0 0, v0x1bbd880_0; -S_0x1bbb2e0 .scope generate, "orbits[2]" "orbits[2]" 3 196, 3 196, S_0x1bb9d80; - .timescale -9 -12; -P_0x1bbb058 .param/l "i" 3 196, +C4<010>; -S_0x1bbb410 .scope module, "attempt" "OrNorXor" 3 198, 3 64, S_0x1bbb2e0; - .timescale -9 -12; -L_0x1bf6e00/d .functor NOR 1, L_0x1bf7fc0, L_0x1bf8060, C4<0>, C4<0>; -L_0x1bf6e00 .delay (10000,10000,10000) L_0x1bf6e00/d; -L_0x1bf6f10/d .functor NOT 1, L_0x1bf6e00, C4<0>, C4<0>, C4<0>; -L_0x1bf6f10 .delay (10000,10000,10000) L_0x1bf6f10/d; -L_0x1bf7040/d .functor NAND 1, L_0x1bf7fc0, L_0x1bf8060, C4<1>, C4<1>; -L_0x1bf7040 .delay (10000,10000,10000) L_0x1bf7040/d; -L_0x1bf71a0/d .functor NAND 1, L_0x1bf7040, L_0x1bf6f10, C4<1>, C4<1>; -L_0x1bf71a0 .delay (10000,10000,10000) L_0x1bf71a0/d; -L_0x1bf72b0/d .functor NOT 1, L_0x1bf71a0, C4<0>, C4<0>, C4<0>; -L_0x1bf72b0 .delay (10000,10000,10000) L_0x1bf72b0/d; -v0x1bbbfe0_0 .net "A", 0 0, L_0x1bf7fc0; 1 drivers -v0x1bbc080_0 .net "AnandB", 0 0, L_0x1bf7040; 1 drivers -v0x1bbc120_0 .net "AnorB", 0 0, L_0x1bf6e00; 1 drivers -v0x1bbc1d0_0 .net "AorB", 0 0, L_0x1bf6f10; 1 drivers -v0x1bbc2b0_0 .net "AxorB", 0 0, L_0x1bf72b0; 1 drivers -v0x1bbc360_0 .net "B", 0 0, L_0x1bf8060; 1 drivers -v0x1bbc420_0 .alias "Command", 2 0, v0x1bd5470_0; -v0x1bbc4a0_0 .net "OrNorXorOut", 0 0, L_0x1bf7cb0; 1 drivers -v0x1bbc550_0 .net "XorNor", 0 0, L_0x1bf7730; 1 drivers -v0x1bbc620_0 .net "nXor", 0 0, L_0x1bf71a0; 1 drivers -L_0x1bf78b0 .part v0x1bd65b0_0, 2, 1; -L_0x1bf7e80 .part v0x1bd65b0_0, 0, 1; -S_0x1bbba70 .scope module, "mux0" "TwoInMux" 3 83, 3 8, S_0x1bbb410; - .timescale -9 -12; -L_0x1bf7410/d .functor NOT 1, L_0x1bf78b0, C4<0>, C4<0>, C4<0>; -L_0x1bf7410 .delay (10000,10000,10000) L_0x1bf7410/d; -L_0x1bf74d0/d .functor AND 1, L_0x1bf72b0, L_0x1bf7410, C4<1>, C4<1>; -L_0x1bf74d0 .delay (20000,20000,20000) L_0x1bf74d0/d; -L_0x1bf75e0/d .functor AND 1, L_0x1bf6e00, L_0x1bf78b0, C4<1>, C4<1>; -L_0x1bf75e0 .delay (20000,20000,20000) L_0x1bf75e0/d; -L_0x1bf7730/d .functor OR 1, L_0x1bf74d0, L_0x1bf75e0, C4<0>, C4<0>; -L_0x1bf7730 .delay (20000,20000,20000) L_0x1bf7730/d; -v0x1bbbb60_0 .net "S", 0 0, L_0x1bf78b0; 1 drivers -v0x1bbbc20_0 .alias "in0", 0 0, v0x1bbc2b0_0; -v0x1bbbcc0_0 .alias "in1", 0 0, v0x1bbc120_0; -v0x1bbbd60_0 .net "nS", 0 0, L_0x1bf7410; 1 drivers -v0x1bbbde0_0 .net "out0", 0 0, L_0x1bf74d0; 1 drivers -v0x1bbbe80_0 .net "out1", 0 0, L_0x1bf75e0; 1 drivers -v0x1bbbf60_0 .alias "outfinal", 0 0, v0x1bbc550_0; -S_0x1bbb500 .scope module, "mux1" "TwoInMux" 3 84, 3 8, S_0x1bbb410; - .timescale -9 -12; -L_0x1bf7950/d .functor NOT 1, L_0x1bf7e80, C4<0>, C4<0>, C4<0>; -L_0x1bf7950 .delay (10000,10000,10000) L_0x1bf7950/d; -L_0x1bf7a10/d .functor AND 1, L_0x1bf7730, L_0x1bf7950, C4<1>, C4<1>; -L_0x1bf7a10 .delay (20000,20000,20000) L_0x1bf7a10/d; -L_0x1bf7b60/d .functor AND 1, L_0x1bf6f10, L_0x1bf7e80, C4<1>, C4<1>; -L_0x1bf7b60 .delay (20000,20000,20000) L_0x1bf7b60/d; -L_0x1bf7cb0/d .functor OR 1, L_0x1bf7a10, L_0x1bf7b60, C4<0>, C4<0>; -L_0x1bf7cb0 .delay (20000,20000,20000) L_0x1bf7cb0/d; -v0x1bbb5f0_0 .net "S", 0 0, L_0x1bf7e80; 1 drivers -v0x1bbb690_0 .alias "in0", 0 0, v0x1bbc550_0; -v0x1bbb730_0 .alias "in1", 0 0, v0x1bbc1d0_0; -v0x1bbb7d0_0 .net "nS", 0 0, L_0x1bf7950; 1 drivers -v0x1bbb850_0 .net "out0", 0 0, L_0x1bf7a10; 1 drivers -v0x1bbb8f0_0 .net "out1", 0 0, L_0x1bf7b60; 1 drivers -v0x1bbb9d0_0 .alias "outfinal", 0 0, v0x1bbc4a0_0; -S_0x1bb9ef0 .scope generate, "orbits[3]" "orbits[3]" 3 196, 3 196, S_0x1bb9d80; - .timescale -9 -12; -P_0x1bb9fe8 .param/l "i" 3 196, +C4<011>; -S_0x1bba080 .scope module, "attempt" "OrNorXor" 3 198, 3 64, S_0x1bb9ef0; - .timescale -9 -12; -L_0x1bf8140/d .functor NOR 1, L_0x1bf92c0, L_0x1bf9360, C4<0>, C4<0>; -L_0x1bf8140 .delay (10000,10000,10000) L_0x1bf8140/d; -L_0x1bf8230/d .functor NOT 1, L_0x1bf8140, C4<0>, C4<0>, C4<0>; -L_0x1bf8230 .delay (10000,10000,10000) L_0x1bf8230/d; -L_0x1bf8340/d .functor NAND 1, L_0x1bf92c0, L_0x1bf9360, C4<1>, C4<1>; -L_0x1bf8340 .delay (10000,10000,10000) L_0x1bf8340/d; -L_0x1bf84a0/d .functor NAND 1, L_0x1bf8340, L_0x1bf8230, C4<1>, C4<1>; -L_0x1bf84a0 .delay (10000,10000,10000) L_0x1bf84a0/d; -L_0x1bf85b0/d .functor NOT 1, L_0x1bf84a0, C4<0>, C4<0>, C4<0>; -L_0x1bf85b0 .delay (10000,10000,10000) L_0x1bf85b0/d; -v0x1bbac50_0 .net "A", 0 0, L_0x1bf92c0; 1 drivers -v0x1bbacf0_0 .net "AnandB", 0 0, L_0x1bf8340; 1 drivers -v0x1bbad90_0 .net "AnorB", 0 0, L_0x1bf8140; 1 drivers -v0x1bbae40_0 .net "AorB", 0 0, L_0x1bf8230; 1 drivers -v0x1bbaf20_0 .net "AxorB", 0 0, L_0x1bf85b0; 1 drivers -v0x1bbafd0_0 .net "B", 0 0, L_0x1bf9360; 1 drivers -v0x1bbb090_0 .alias "Command", 2 0, v0x1bd5470_0; -v0x1bbb110_0 .net "OrNorXorOut", 0 0, L_0x1bf8fb0; 1 drivers -v0x1bbb190_0 .net "XorNor", 0 0, L_0x1bf8a30; 1 drivers -v0x1bbb260_0 .net "nXor", 0 0, L_0x1bf84a0; 1 drivers -L_0x1bf8bb0 .part v0x1bd65b0_0, 2, 1; -L_0x1bf9180 .part v0x1bd65b0_0, 0, 1; -S_0x1bba6e0 .scope module, "mux0" "TwoInMux" 3 83, 3 8, S_0x1bba080; - .timescale -9 -12; -L_0x1bf8710/d .functor NOT 1, L_0x1bf8bb0, C4<0>, C4<0>, C4<0>; -L_0x1bf8710 .delay (10000,10000,10000) L_0x1bf8710/d; -L_0x1bf87d0/d .functor AND 1, L_0x1bf85b0, L_0x1bf8710, C4<1>, C4<1>; -L_0x1bf87d0 .delay (20000,20000,20000) L_0x1bf87d0/d; -L_0x1bf88e0/d .functor AND 1, L_0x1bf8140, L_0x1bf8bb0, C4<1>, C4<1>; -L_0x1bf88e0 .delay (20000,20000,20000) L_0x1bf88e0/d; -L_0x1bf8a30/d .functor OR 1, L_0x1bf87d0, L_0x1bf88e0, C4<0>, C4<0>; -L_0x1bf8a30 .delay (20000,20000,20000) L_0x1bf8a30/d; -v0x1bba7d0_0 .net "S", 0 0, L_0x1bf8bb0; 1 drivers -v0x1bba890_0 .alias "in0", 0 0, v0x1bbaf20_0; -v0x1bba930_0 .alias "in1", 0 0, v0x1bbad90_0; -v0x1bba9d0_0 .net "nS", 0 0, L_0x1bf8710; 1 drivers -v0x1bbaa50_0 .net "out0", 0 0, L_0x1bf87d0; 1 drivers -v0x1bbaaf0_0 .net "out1", 0 0, L_0x1bf88e0; 1 drivers -v0x1bbabd0_0 .alias "outfinal", 0 0, v0x1bbb190_0; -S_0x1bba170 .scope module, "mux1" "TwoInMux" 3 84, 3 8, S_0x1bba080; - .timescale -9 -12; -L_0x1bf8c50/d .functor NOT 1, L_0x1bf9180, C4<0>, C4<0>, C4<0>; -L_0x1bf8c50 .delay (10000,10000,10000) L_0x1bf8c50/d; -L_0x1bf8d10/d .functor AND 1, L_0x1bf8a30, L_0x1bf8c50, C4<1>, C4<1>; -L_0x1bf8d10 .delay (20000,20000,20000) L_0x1bf8d10/d; -L_0x1bf8e60/d .functor AND 1, L_0x1bf8230, L_0x1bf9180, C4<1>, C4<1>; -L_0x1bf8e60 .delay (20000,20000,20000) L_0x1bf8e60/d; -L_0x1bf8fb0/d .functor OR 1, L_0x1bf8d10, L_0x1bf8e60, C4<0>, C4<0>; -L_0x1bf8fb0 .delay (20000,20000,20000) L_0x1bf8fb0/d; -v0x1bba260_0 .net "S", 0 0, L_0x1bf9180; 1 drivers -v0x1bba300_0 .alias "in0", 0 0, v0x1bbb190_0; -v0x1bba3a0_0 .alias "in1", 0 0, v0x1bbae40_0; -v0x1bba440_0 .net "nS", 0 0, L_0x1bf8c50; 1 drivers -v0x1bba4c0_0 .net "out0", 0 0, L_0x1bf8d10; 1 drivers -v0x1bba560_0 .net "out1", 0 0, L_0x1bf8e60; 1 drivers -v0x1bba640_0 .alias "outfinal", 0 0, v0x1bbb110_0; -S_0x1bb9400 .scope module, "ZeroMux0case" "FourInMux" 3 283, 3 24, S_0x1b51ae0; - .timescale -9 -12; -L_0x1bfa5b0/d .functor NOT 1, L_0x1beccc0, C4<0>, C4<0>, C4<0>; -L_0x1bfa5b0 .delay (10000,10000,10000) L_0x1bfa5b0/d; -L_0x1bfa800/d .functor NOT 1, L_0x1becdf0, C4<0>, C4<0>, C4<0>; -L_0x1bfa800 .delay (10000,10000,10000) L_0x1bfa800/d; -L_0x1bfa8c0/d .functor NAND 1, L_0x1bfa5b0, L_0x1bfa800, L_0x1bfaef0, C4<1>; -L_0x1bfa8c0 .delay (10000,10000,10000) L_0x1bfa8c0/d; -L_0x1bfa9b0/d .functor NAND 1, L_0x1beccc0, L_0x1bfa800, L_0x1bfaf90, C4<1>; -L_0x1bfa9b0 .delay (10000,10000,10000) L_0x1bfa9b0/d; -L_0x1bfaaa0/d .functor NAND 1, L_0x1bfa5b0, L_0x1becdf0, L_0x1bfb030, C4<1>; -L_0x1bfaaa0 .delay (10000,10000,10000) L_0x1bfaaa0/d; -L_0x1bfab90/d .functor NAND 1, L_0x1beccc0, L_0x1becdf0, L_0x1bfb410, C4<1>; -L_0x1bfab90 .delay (10000,10000,10000) L_0x1bfab90/d; -L_0x1bfac70/d .functor NAND 1, L_0x1bfa8c0, L_0x1bfa9b0, L_0x1bfaaa0, L_0x1bfab90; -L_0x1bfac70 .delay (10000,10000,10000) L_0x1bfac70/d; -v0x1bb94f0_0 .net "S0", 0 0, L_0x1beccc0; 1 drivers -v0x1bb95b0_0 .net "S1", 0 0, L_0x1becdf0; 1 drivers -v0x1bb9650_0 .net "in0", 0 0, L_0x1bfaef0; 1 drivers -v0x1bb96f0_0 .net "in1", 0 0, L_0x1bfaf90; 1 drivers -v0x1bb9770_0 .net "in2", 0 0, L_0x1bfb030; 1 drivers -v0x1bb9810_0 .net "in3", 0 0, L_0x1bfb410; 1 drivers -v0x1bb98b0_0 .net "nS0", 0 0, L_0x1bfa5b0; 1 drivers -v0x1bb9950_0 .net "nS1", 0 0, L_0x1bfa800; 1 drivers -v0x1bb99f0_0 .net "out", 0 0, L_0x1bfac70; 1 drivers -v0x1bb9a90_0 .net "out0", 0 0, L_0x1bfa8c0; 1 drivers -v0x1bb9b30_0 .net "out1", 0 0, L_0x1bfa9b0; 1 drivers -v0x1bb9bd0_0 .net "out2", 0 0, L_0x1bfaaa0; 1 drivers -v0x1bb9ce0_0 .net "out3", 0 0, L_0x1bfab90; 1 drivers -S_0x1bb8a40 .scope module, "OneMux0case" "FourInMux" 3 284, 3 24, S_0x1b51ae0; - .timescale -9 -12; -L_0x1bfb190/d .functor NOT 1, L_0x1bfbd20, C4<0>, C4<0>, C4<0>; -L_0x1bfb190 .delay (10000,10000,10000) L_0x1bfb190/d; -L_0x1bfb280/d .functor NOT 1, L_0x1bfb500, C4<0>, C4<0>, C4<0>; -L_0x1bfb280 .delay (10000,10000,10000) L_0x1bfb280/d; -L_0x1bfb320/d .functor NAND 1, L_0x1bfb190, L_0x1bfb280, L_0x1bfb630, C4<1>; -L_0x1bfb320 .delay (10000,10000,10000) L_0x1bfb320/d; -L_0x1bfb7e0/d .functor NAND 1, L_0x1bfbd20, L_0x1bfb280, L_0x1bfc0b0, C4<1>; -L_0x1bfb7e0 .delay (10000,10000,10000) L_0x1bfb7e0/d; -L_0x1bfb8d0/d .functor NAND 1, L_0x1bfb190, L_0x1bfb500, L_0x1bfc150, C4<1>; -L_0x1bfb8d0 .delay (10000,10000,10000) L_0x1bfb8d0/d; -L_0x1bfb9c0/d .functor NAND 1, L_0x1bfbd20, L_0x1bfb500, L_0x1bfbe50, C4<1>; -L_0x1bfb9c0 .delay (10000,10000,10000) L_0x1bfb9c0/d; -L_0x1bfbaa0/d .functor NAND 1, L_0x1bfb320, L_0x1bfb7e0, L_0x1bfb8d0, L_0x1bfb9c0; -L_0x1bfbaa0 .delay (10000,10000,10000) L_0x1bfbaa0/d; -v0x1bb8b30_0 .net "S0", 0 0, L_0x1bfbd20; 1 drivers -v0x1bb8bf0_0 .net "S1", 0 0, L_0x1bfb500; 1 drivers -v0x1bb8c90_0 .net "in0", 0 0, L_0x1bfb630; 1 drivers -v0x1bb8d30_0 .net "in1", 0 0, L_0x1bfc0b0; 1 drivers -v0x1bb8db0_0 .net "in2", 0 0, L_0x1bfc150; 1 drivers -v0x1bb8e50_0 .net "in3", 0 0, L_0x1bfbe50; 1 drivers -v0x1bb8f30_0 .net "nS0", 0 0, L_0x1bfb190; 1 drivers -v0x1bb8fd0_0 .net "nS1", 0 0, L_0x1bfb280; 1 drivers -v0x1bb9070_0 .net "out", 0 0, L_0x1bfbaa0; 1 drivers -v0x1bb9110_0 .net "out0", 0 0, L_0x1bfb320; 1 drivers -v0x1bb91b0_0 .net "out1", 0 0, L_0x1bfb7e0; 1 drivers -v0x1bb9250_0 .net "out2", 0 0, L_0x1bfb8d0; 1 drivers -v0x1bb9360_0 .net "out3", 0 0, L_0x1bfb9c0; 1 drivers -S_0x1bb84f0 .scope module, "TwoMux0case" "TwoInMux" 3 285, 3 8, S_0x1b51ae0; - .timescale -9 -12; -L_0x1bfbf40/d .functor NOT 1, L_0x1bfc1f0, C4<0>, C4<0>, C4<0>; -L_0x1bfbf40 .delay (10000,10000,10000) L_0x1bfbf40/d; -L_0x1bfc030/d .functor AND 1, L_0x1bfc290, L_0x1bfbf40, C4<1>, C4<1>; -L_0x1bfc030 .delay (20000,20000,20000) L_0x1bfc030/d; -L_0x1bfc4f0/d .functor AND 1, L_0x1bfc380, L_0x1bfc1f0, C4<1>, C4<1>; -L_0x1bfc4f0 .delay (20000,20000,20000) L_0x1bfc4f0/d; -L_0x1bfc5e0/d .functor OR 1, L_0x1bfc030, L_0x1bfc4f0, C4<0>, C4<0>; -L_0x1bfc5e0 .delay (20000,20000,20000) L_0x1bfc5e0/d; -v0x1bb85e0_0 .net "S", 0 0, L_0x1bfc1f0; 1 drivers -v0x1bb86a0_0 .net "in0", 0 0, L_0x1bfc290; 1 drivers -v0x1bb8740_0 .net "in1", 0 0, L_0x1bfc380; 1 drivers -v0x1bb87e0_0 .net "nS", 0 0, L_0x1bfbf40; 1 drivers -v0x1bb8860_0 .net "out0", 0 0, L_0x1bfc030; 1 drivers -v0x1bb8900_0 .net "out1", 0 0, L_0x1bfc4f0; 1 drivers -v0x1bb89a0_0 .net "outfinal", 0 0, L_0x1bfc5e0; 1 drivers -S_0x1bb6970 .scope generate, "muxbits[1]" "muxbits[1]" 3 290, 3 290, S_0x1b51ae0; - .timescale -9 -12; -P_0x1bb5968 .param/l "i" 3 290, +C4<01>; -L_0x1be7250/d .functor OR 1, L_0x1be7350, L_0x1be7110, C4<0>, C4<0>; -L_0x1be7250 .delay (20000,20000,20000) L_0x1be7250/d; -v0x1bb8390_0 .net *"_s15", 0 0, L_0x1be7350; 1 drivers -v0x1bb8450_0 .net *"_s16", 0 0, L_0x1be7110; 1 drivers -S_0x1bb7a10 .scope module, "ZeroMux" "FourInMux" 3 292, 3 24, S_0x1bb6970; - .timescale -9 -12; -L_0x1be4980/d .functor NOT 1, L_0x1be5330, C4<0>, C4<0>, C4<0>; -L_0x1be4980 .delay (10000,10000,10000) L_0x1be4980/d; -L_0x1be4bd0/d .functor NOT 1, L_0x1be5460, C4<0>, C4<0>, C4<0>; -L_0x1be4bd0 .delay (10000,10000,10000) L_0x1be4bd0/d; -L_0x1be4c70/d .functor NAND 1, L_0x1be4980, L_0x1be4bd0, L_0x1be5590, C4<1>; -L_0x1be4c70 .delay (10000,10000,10000) L_0x1be4c70/d; -L_0x1be4d60/d .functor NAND 1, L_0x1be5330, L_0x1be4bd0, L_0x1be5630, C4<1>; -L_0x1be4d60 .delay (10000,10000,10000) L_0x1be4d60/d; -L_0x1be4e50/d .functor NAND 1, L_0x1be4980, L_0x1be5460, L_0x1be56d0, C4<1>; -L_0x1be4e50 .delay (10000,10000,10000) L_0x1be4e50/d; -L_0x1be4f40/d .functor NAND 1, L_0x1be5330, L_0x1be5460, L_0x1be58d0, C4<1>; -L_0x1be4f40 .delay (10000,10000,10000) L_0x1be4f40/d; -L_0x1be5080/d .functor NAND 1, L_0x1be4c70, L_0x1be4d60, L_0x1be4e50, L_0x1be4f40; -L_0x1be5080 .delay (10000,10000,10000) L_0x1be5080/d; -v0x1bb7b00_0 .net "S0", 0 0, L_0x1be5330; 1 drivers -v0x1bb7bc0_0 .net "S1", 0 0, L_0x1be5460; 1 drivers -v0x1bb7c60_0 .net "in0", 0 0, L_0x1be5590; 1 drivers -v0x1bb7d00_0 .net "in1", 0 0, L_0x1be5630; 1 drivers -v0x1bb7d80_0 .net "in2", 0 0, L_0x1be56d0; 1 drivers -v0x1bb7e20_0 .net "in3", 0 0, L_0x1be58d0; 1 drivers -v0x1bb7ec0_0 .net "nS0", 0 0, L_0x1be4980; 1 drivers -v0x1bb7f60_0 .net "nS1", 0 0, L_0x1be4bd0; 1 drivers -v0x1bb8000_0 .net "out", 0 0, L_0x1be5080; 1 drivers -v0x1bb80a0_0 .net "out0", 0 0, L_0x1be4c70; 1 drivers -v0x1bb8140_0 .net "out1", 0 0, L_0x1be4d60; 1 drivers -v0x1bb81e0_0 .net "out2", 0 0, L_0x1be4e50; 1 drivers -v0x1bb82f0_0 .net "out3", 0 0, L_0x1be4f40; 1 drivers -S_0x1bb7050 .scope module, "OneMux" "FourInMux" 3 293, 3 24, S_0x1bb6970; - .timescale -9 -12; -L_0x1be5970/d .functor NOT 1, L_0x1be62f0, C4<0>, C4<0>, C4<0>; -L_0x1be5970 .delay (10000,10000,10000) L_0x1be5970/d; -L_0x1be5a60/d .functor NOT 1, L_0x1be6420, C4<0>, C4<0>, C4<0>; -L_0x1be5a60 .delay (10000,10000,10000) L_0x1be5a60/d; -L_0x1be5b00/d .functor NAND 1, L_0x1be5970, L_0x1be5a60, L_0x1be65b0, C4<1>; -L_0x1be5b00 .delay (10000,10000,10000) L_0x1be5b00/d; -L_0x1be5c40/d .functor NAND 1, L_0x1be62f0, L_0x1be5a60, L_0x1be6760, C4<1>; -L_0x1be5c40 .delay (10000,10000,10000) L_0x1be5c40/d; -L_0x1be5d30/d .functor NAND 1, L_0x1be5970, L_0x1be6420, L_0x1be6800, C4<1>; -L_0x1be5d30 .delay (10000,10000,10000) L_0x1be5d30/d; -L_0x1be5e80/d .functor NAND 1, L_0x1be62f0, L_0x1be6420, L_0x1be68a0, C4<1>; -L_0x1be5e80 .delay (10000,10000,10000) L_0x1be5e80/d; -L_0x1be5ff0/d .functor NAND 1, L_0x1be5b00, L_0x1be5c40, L_0x1be5d30, L_0x1be5e80; -L_0x1be5ff0 .delay (10000,10000,10000) L_0x1be5ff0/d; -v0x1bb7140_0 .net "S0", 0 0, L_0x1be62f0; 1 drivers -v0x1bb7200_0 .net "S1", 0 0, L_0x1be6420; 1 drivers -v0x1bb72a0_0 .net "in0", 0 0, L_0x1be65b0; 1 drivers -v0x1bb7340_0 .net "in1", 0 0, L_0x1be6760; 1 drivers -v0x1bb73c0_0 .net "in2", 0 0, L_0x1be6800; 1 drivers -v0x1bb7460_0 .net "in3", 0 0, L_0x1be68a0; 1 drivers -v0x1bb7540_0 .net "nS0", 0 0, L_0x1be5970; 1 drivers -v0x1bb75e0_0 .net "nS1", 0 0, L_0x1be5a60; 1 drivers -v0x1bb7680_0 .net "out", 0 0, L_0x1be5ff0; 1 drivers -v0x1bb7720_0 .net "out0", 0 0, L_0x1be5b00; 1 drivers -v0x1bb77c0_0 .net "out1", 0 0, L_0x1be5c40; 1 drivers -v0x1bb7860_0 .net "out2", 0 0, L_0x1be5d30; 1 drivers -v0x1bb7970_0 .net "out3", 0 0, L_0x1be5e80; 1 drivers -S_0x1bb6ae0 .scope module, "TwoMux" "TwoInMux" 3 294, 3 8, S_0x1bb6970; - .timescale -9 -12; -L_0x1be6550/d .functor NOT 1, L_0x1be6df0, C4<0>, C4<0>, C4<0>; -L_0x1be6550 .delay (10000,10000,10000) L_0x1be6550/d; -L_0x1be69e0/d .functor AND 1, L_0x1be6e90, L_0x1be6550, C4<1>, C4<1>; -L_0x1be69e0 .delay (20000,20000,20000) L_0x1be69e0/d; -L_0x1be6ad0/d .functor AND 1, L_0x1be6fd0, L_0x1be6df0, C4<1>, C4<1>; -L_0x1be6ad0 .delay (20000,20000,20000) L_0x1be6ad0/d; -L_0x1be6bc0/d .functor OR 1, L_0x1be69e0, L_0x1be6ad0, C4<0>, C4<0>; -L_0x1be6bc0 .delay (20000,20000,20000) L_0x1be6bc0/d; -v0x1bb6bd0_0 .net "S", 0 0, L_0x1be6df0; 1 drivers -v0x1bb6c70_0 .net "in0", 0 0, L_0x1be6e90; 1 drivers -v0x1bb6d10_0 .net "in1", 0 0, L_0x1be6fd0; 1 drivers -v0x1bb6db0_0 .net "nS", 0 0, L_0x1be6550; 1 drivers -v0x1bb6e30_0 .net "out0", 0 0, L_0x1be69e0; 1 drivers -v0x1bb6ed0_0 .net "out1", 0 0, L_0x1be6ad0; 1 drivers -v0x1bb6fb0_0 .net "outfinal", 0 0, L_0x1be6bc0; 1 drivers -S_0x1bb4df0 .scope generate, "muxbits[2]" "muxbits[2]" 3 290, 3 290, S_0x1b51ae0; - .timescale -9 -12; -P_0x1bb3d38 .param/l "i" 3 290, +C4<010>; -L_0x1be9660/d .functor OR 1, L_0x1be9e60, L_0x1bea1e0, C4<0>, C4<0>; -L_0x1be9660 .delay (20000,20000,20000) L_0x1be9660/d; -v0x1bb6810_0 .net *"_s15", 0 0, L_0x1be9e60; 1 drivers -v0x1bb68d0_0 .net *"_s16", 0 0, L_0x1bea1e0; 1 drivers -S_0x1bb5e90 .scope module, "ZeroMux" "FourInMux" 3 292, 3 24, S_0x1bb4df0; - .timescale -9 -12; -L_0x1be74f0/d .functor NOT 1, L_0x1be73f0, C4<0>, C4<0>, C4<0>; -L_0x1be74f0 .delay (10000,10000,10000) L_0x1be74f0/d; -L_0x1be75e0/d .functor NOT 1, L_0x1be7ee0, C4<0>, C4<0>, C4<0>; -L_0x1be75e0 .delay (10000,10000,10000) L_0x1be75e0/d; -L_0x1be7680/d .functor NAND 1, L_0x1be74f0, L_0x1be75e0, L_0x1be7d90, C4<1>; -L_0x1be7680 .delay (10000,10000,10000) L_0x1be7680/d; -L_0x1be77c0/d .functor NAND 1, L_0x1be73f0, L_0x1be75e0, L_0x1be80e0, C4<1>; -L_0x1be77c0 .delay (10000,10000,10000) L_0x1be77c0/d; -L_0x1be78b0/d .functor NAND 1, L_0x1be74f0, L_0x1be7ee0, L_0x1be8010, C4<1>; -L_0x1be78b0 .delay (10000,10000,10000) L_0x1be78b0/d; -L_0x1be79a0/d .functor NAND 1, L_0x1be73f0, L_0x1be7ee0, L_0x1be82b0, C4<1>; -L_0x1be79a0 .delay (10000,10000,10000) L_0x1be79a0/d; -L_0x1be7ae0/d .functor NAND 1, L_0x1be7680, L_0x1be77c0, L_0x1be78b0, L_0x1be79a0; -L_0x1be7ae0 .delay (10000,10000,10000) L_0x1be7ae0/d; -v0x1bb5f80_0 .net "S0", 0 0, L_0x1be73f0; 1 drivers -v0x1bb6040_0 .net "S1", 0 0, L_0x1be7ee0; 1 drivers -v0x1bb60e0_0 .net "in0", 0 0, L_0x1be7d90; 1 drivers -v0x1bb6180_0 .net "in1", 0 0, L_0x1be80e0; 1 drivers -v0x1bb6200_0 .net "in2", 0 0, L_0x1be8010; 1 drivers -v0x1bb62a0_0 .net "in3", 0 0, L_0x1be82b0; 1 drivers -v0x1bb6340_0 .net "nS0", 0 0, L_0x1be74f0; 1 drivers -v0x1bb63e0_0 .net "nS1", 0 0, L_0x1be75e0; 1 drivers -v0x1bb6480_0 .net "out", 0 0, L_0x1be7ae0; 1 drivers -v0x1bb6520_0 .net "out0", 0 0, L_0x1be7680; 1 drivers -v0x1bb65c0_0 .net "out1", 0 0, L_0x1be77c0; 1 drivers -v0x1bb6660_0 .net "out2", 0 0, L_0x1be78b0; 1 drivers -v0x1bb6770_0 .net "out3", 0 0, L_0x1be79a0; 1 drivers -S_0x1bb54d0 .scope module, "OneMux" "FourInMux" 3 293, 3 24, S_0x1bb4df0; - .timescale -9 -12; -L_0x1be8180/d .functor NOT 1, L_0x1be8c80, C4<0>, C4<0>, C4<0>; -L_0x1be8180 .delay (10000,10000,10000) L_0x1be8180/d; -L_0x1be84e0/d .functor NOT 1, L_0x1be83a0, C4<0>, C4<0>, C4<0>; -L_0x1be84e0 .delay (10000,10000,10000) L_0x1be84e0/d; -L_0x1be8540/d .functor NAND 1, L_0x1be8180, L_0x1be84e0, L_0x1bd7280, C4<1>; -L_0x1be8540 .delay (10000,10000,10000) L_0x1be8540/d; -L_0x1be8680/d .functor NAND 1, L_0x1be8c80, L_0x1be84e0, L_0x1bd7430, C4<1>; -L_0x1be8680 .delay (10000,10000,10000) L_0x1be8680/d; -L_0x1be8770/d .functor NAND 1, L_0x1be8180, L_0x1be83a0, L_0x1bd70f0, C4<1>; -L_0x1be8770 .delay (10000,10000,10000) L_0x1be8770/d; -L_0x1be8860/d .functor NAND 1, L_0x1be8c80, L_0x1be83a0, L_0x1bd7320, C4<1>; -L_0x1be8860 .delay (10000,10000,10000) L_0x1be8860/d; -L_0x1be89d0/d .functor NAND 1, L_0x1be8540, L_0x1be8680, L_0x1be8770, L_0x1be8860; -L_0x1be89d0 .delay (10000,10000,10000) L_0x1be89d0/d; -v0x1bb55c0_0 .net "S0", 0 0, L_0x1be8c80; 1 drivers -v0x1bb5680_0 .net "S1", 0 0, L_0x1be83a0; 1 drivers -v0x1bb5720_0 .net "in0", 0 0, L_0x1bd7280; 1 drivers -v0x1bb57c0_0 .net "in1", 0 0, L_0x1bd7430; 1 drivers -v0x1bb5840_0 .net "in2", 0 0, L_0x1bd70f0; 1 drivers -v0x1bb58e0_0 .net "in3", 0 0, L_0x1bd7320; 1 drivers -v0x1bb59c0_0 .net "nS0", 0 0, L_0x1be8180; 1 drivers -v0x1bb5a60_0 .net "nS1", 0 0, L_0x1be84e0; 1 drivers -v0x1bb5b00_0 .net "out", 0 0, L_0x1be89d0; 1 drivers -v0x1bb5ba0_0 .net "out0", 0 0, L_0x1be8540; 1 drivers -v0x1bb5c40_0 .net "out1", 0 0, L_0x1be8680; 1 drivers -v0x1bb5ce0_0 .net "out2", 0 0, L_0x1be8770; 1 drivers -v0x1bb5df0_0 .net "out3", 0 0, L_0x1be8860; 1 drivers -S_0x1bb4f60 .scope module, "TwoMux" "TwoInMux" 3 294, 3 8, S_0x1bb4df0; - .timescale -9 -12; -L_0x1bd73c0/d .functor NOT 1, L_0x1be95c0, C4<0>, C4<0>, C4<0>; -L_0x1bd73c0 .delay (10000,10000,10000) L_0x1bd73c0/d; -L_0x1be9770/d .functor AND 1, L_0x1be9cf0, L_0x1bd73c0, C4<1>, C4<1>; -L_0x1be9770 .delay (20000,20000,20000) L_0x1be9770/d; -L_0x1be9860/d .functor AND 1, L_0x1be9bc0, L_0x1be95c0, C4<1>, C4<1>; -L_0x1be9860 .delay (20000,20000,20000) L_0x1be9860/d; -L_0x1be9950/d .functor OR 1, L_0x1be9770, L_0x1be9860, C4<0>, C4<0>; -L_0x1be9950 .delay (20000,20000,20000) L_0x1be9950/d; -v0x1bb5050_0 .net "S", 0 0, L_0x1be95c0; 1 drivers -v0x1bb50f0_0 .net "in0", 0 0, L_0x1be9cf0; 1 drivers -v0x1bb5190_0 .net "in1", 0 0, L_0x1be9bc0; 1 drivers -v0x1bb5230_0 .net "nS", 0 0, L_0x1bd73c0; 1 drivers -v0x1bb52b0_0 .net "out0", 0 0, L_0x1be9770; 1 drivers -v0x1bb5350_0 .net "out1", 0 0, L_0x1be9860; 1 drivers -v0x1bb5430_0 .net "outfinal", 0 0, L_0x1be9950; 1 drivers -S_0x1b300c0 .scope generate, "muxbits[3]" "muxbits[3]" 3 290, 3 290, S_0x1b51ae0; - .timescale -9 -12; -P_0x1b2c6c8 .param/l "i" 3 290, +C4<011>; -L_0x1bec8a0/d .functor OR 1, L_0x1becc20, L_0x1beca30, C4<0>, C4<0>; -L_0x1bec8a0 .delay (20000,20000,20000) L_0x1bec8a0/d; -v0x1bb4c90_0 .net *"_s15", 0 0, L_0x1becc20; 1 drivers -v0x1bb4d50_0 .net *"_s16", 0 0, L_0x1beca30; 1 drivers -S_0x1bb4310 .scope module, "ZeroMux" "FourInMux" 3 292, 3 24, S_0x1b300c0; - .timescale -9 -12; -L_0x1bea090/d .functor NOT 1, L_0x1beab90, C4<0>, C4<0>, C4<0>; -L_0x1bea090 .delay (10000,10000,10000) L_0x1bea090/d; -L_0x1bea180/d .functor NOT 1, L_0x1bea280, C4<0>, C4<0>, C4<0>; -L_0x1bea180 .delay (10000,10000,10000) L_0x1bea180/d; -L_0x1bea420/d .functor NAND 1, L_0x1bea090, L_0x1bea180, L_0x1beae30, C4<1>; -L_0x1bea420 .delay (10000,10000,10000) L_0x1bea420/d; -L_0x1bea560/d .functor NAND 1, L_0x1beab90, L_0x1bea180, L_0x1bdcd20, C4<1>; -L_0x1bea560 .delay (10000,10000,10000) L_0x1bea560/d; -L_0x1bea650/d .functor NAND 1, L_0x1bea090, L_0x1bea280, L_0x1beacc0, C4<1>; -L_0x1bea650 .delay (10000,10000,10000) L_0x1bea650/d; -L_0x1bea770/d .functor NAND 1, L_0x1beab90, L_0x1bea280, L_0x1beb270, C4<1>; -L_0x1bea770 .delay (10000,10000,10000) L_0x1bea770/d; -L_0x1bea8e0/d .functor NAND 1, L_0x1bea420, L_0x1bea560, L_0x1bea650, L_0x1bea770; -L_0x1bea8e0 .delay (10000,10000,10000) L_0x1bea8e0/d; -v0x1bb4400_0 .net "S0", 0 0, L_0x1beab90; 1 drivers -v0x1bb44c0_0 .net "S1", 0 0, L_0x1bea280; 1 drivers -v0x1bb4560_0 .net "in0", 0 0, L_0x1beae30; 1 drivers -v0x1bb4600_0 .net "in1", 0 0, L_0x1bdcd20; 1 drivers -v0x1bb4680_0 .net "in2", 0 0, L_0x1beacc0; 1 drivers -v0x1bb4720_0 .net "in3", 0 0, L_0x1beb270; 1 drivers -v0x1bb47c0_0 .net "nS0", 0 0, L_0x1bea090; 1 drivers -v0x1bb4860_0 .net "nS1", 0 0, L_0x1bea180; 1 drivers -v0x1bb4900_0 .net "out", 0 0, L_0x1bea8e0; 1 drivers -v0x1bb49a0_0 .net "out0", 0 0, L_0x1bea420; 1 drivers -v0x1bb4a40_0 .net "out1", 0 0, L_0x1bea560; 1 drivers -v0x1bb4ae0_0 .net "out2", 0 0, L_0x1bea650; 1 drivers -v0x1bb4bf0_0 .net "out3", 0 0, L_0x1bea770; 1 drivers -S_0x1bb38a0 .scope module, "OneMux" "FourInMux" 3 293, 3 24, S_0x1b300c0; - .timescale -9 -12; -L_0x1beadb0/d .functor NOT 1, L_0x1beb0e0, C4<0>, C4<0>, C4<0>; -L_0x1beadb0 .delay (10000,10000,10000) L_0x1beadb0/d; -L_0x1beb3a0/d .functor NOT 1, L_0x1bebd20, C4<0>, C4<0>, C4<0>; -L_0x1beb3a0 .delay (10000,10000,10000) L_0x1beb3a0/d; -L_0x1beb440/d .functor NAND 1, L_0x1beadb0, L_0x1beb3a0, L_0x1bebb80, C4<1>; -L_0x1beb440 .delay (10000,10000,10000) L_0x1beb440/d; -L_0x1beb580/d .functor NAND 1, L_0x1beb0e0, L_0x1beb3a0, L_0x1bebc20, C4<1>; -L_0x1beb580 .delay (10000,10000,10000) L_0x1beb580/d; -L_0x1beb670/d .functor NAND 1, L_0x1beadb0, L_0x1bebd20, L_0x1bec010, C4<1>; -L_0x1beb670 .delay (10000,10000,10000) L_0x1beb670/d; -L_0x1beb760/d .functor NAND 1, L_0x1beb0e0, L_0x1bebd20, L_0x1bec0b0, C4<1>; -L_0x1beb760 .delay (10000,10000,10000) L_0x1beb760/d; -L_0x1beb8d0/d .functor NAND 1, L_0x1beb440, L_0x1beb580, L_0x1beb670, L_0x1beb760; -L_0x1beb8d0 .delay (10000,10000,10000) L_0x1beb8d0/d; -v0x1bb3990_0 .net "S0", 0 0, L_0x1beb0e0; 1 drivers -v0x1bb3a50_0 .net "S1", 0 0, L_0x1bebd20; 1 drivers -v0x1bb3af0_0 .net "in0", 0 0, L_0x1bebb80; 1 drivers -v0x1bb3b90_0 .net "in1", 0 0, L_0x1bebc20; 1 drivers -v0x1bb3c10_0 .net "in2", 0 0, L_0x1bec010; 1 drivers -v0x1bb3cb0_0 .net "in3", 0 0, L_0x1bec0b0; 1 drivers -v0x1bb3d90_0 .net "nS0", 0 0, L_0x1beadb0; 1 drivers -v0x1bb3e30_0 .net "nS1", 0 0, L_0x1beb3a0; 1 drivers -v0x1bb3f20_0 .net "out", 0 0, L_0x1beb8d0; 1 drivers -v0x1bb3fc0_0 .net "out0", 0 0, L_0x1beb440; 1 drivers -v0x1bb40c0_0 .net "out1", 0 0, L_0x1beb580; 1 drivers -v0x1bb4160_0 .net "out2", 0 0, L_0x1beb670; 1 drivers -v0x1bb4270_0 .net "out3", 0 0, L_0x1beb760; 1 drivers -S_0x1b2fe10 .scope module, "TwoMux" "TwoInMux" 3 294, 3 8, S_0x1b300c0; - .timescale -9 -12; -L_0x1be57c0/d .functor NOT 1, L_0x1bec760, C4<0>, C4<0>, C4<0>; -L_0x1be57c0 .delay (10000,10000,10000) L_0x1be57c0/d; -L_0x1bebe50/d .functor AND 1, L_0x1bec360, L_0x1be57c0, C4<1>, C4<1>; -L_0x1bebe50 .delay (20000,20000,20000) L_0x1bebe50/d; -L_0x1bebf40/d .functor AND 1, L_0x1bec450, L_0x1bec760, C4<1>, C4<1>; -L_0x1bebf40 .delay (20000,20000,20000) L_0x1bebf40/d; -L_0x1bec580/d .functor OR 1, L_0x1bebe50, L_0x1bebf40, C4<0>, C4<0>; -L_0x1bec580 .delay (20000,20000,20000) L_0x1bec580/d; -v0x1afa710_0 .net "S", 0 0, L_0x1bec760; 1 drivers -v0x1bb3490_0 .net "in0", 0 0, L_0x1bec360; 1 drivers -v0x1bb3530_0 .net "in1", 0 0, L_0x1bec450; 1 drivers -v0x1bb35d0_0 .net "nS", 0 0, L_0x1be57c0; 1 drivers -v0x1bb3680_0 .net "out0", 0 0, L_0x1bebe50; 1 drivers -v0x1bb3720_0 .net "out1", 0 0, L_0x1bebf40; 1 drivers -v0x1bb3800_0 .net "outfinal", 0 0, L_0x1bec580; 1 drivers - .scope S_0x1b740f0; +S_0x270e6d0 .scope module, "test32Adder" "test32Adder" 2 122; + .timescale -9 -12; +P_0x2665ab8 .param/l "size" 2 123, +C4<0100000>; +v0x2bc7660_0 .var "A", 31 0; +RS_0x7f99c4320aa8/0/0 .resolv tri, L_0x2bc8d00, L_0x2bca3f0, L_0x2bcb830, L_0x2bccdf0; +RS_0x7f99c4320aa8/0/4 .resolv tri, L_0x2bce390, L_0x2bcf9c0, L_0x2bd0ee0, L_0x2bd2400; +RS_0x7f99c4320aa8/0/8 .resolv tri, L_0x2bd3a10, L_0x2bd5120, L_0x2bd6630, L_0x2bd7b40; +RS_0x7f99c4320aa8/0/12 .resolv tri, L_0x2bd9040, L_0x2bda740, L_0x2bdbc50, L_0x2bdd150; +RS_0x7f99c4320aa8/0/16 .resolv tri, L_0x2bde740, L_0x2bdfbb0, L_0x2b875a0, L_0x2be3560; +RS_0x7f99c4320aa8/0/20 .resolv tri, L_0x2be4920, L_0x2be5cf0, L_0x2be70b0, L_0x2be8570; +RS_0x7f99c4320aa8/0/24 .resolv tri, L_0x2be9a60, L_0x2beb340, L_0x2bec820, L_0x2bedd20; +RS_0x7f99c4320aa8/0/28 .resolv tri, L_0x2bef210, L_0x2bf0b00, L_0x2bf1ff0, L_0x2bf34e0; +RS_0x7f99c4320aa8/0/32 .resolv tri, L_0x2c806a0, L_0x2c83eb0, L_0x2c852b0, L_0x2c86790; +RS_0x7f99c4320aa8/0/36 .resolv tri, L_0x2c87c30, L_0x2c89020, L_0x2c8a420, L_0x2c8b880; +RS_0x7f99c4320aa8/0/40 .resolv tri, L_0x2c8ce90, L_0x2c8e3a0, L_0x2c8f8b0, L_0x2c90dc0; +RS_0x7f99c4320aa8/0/44 .resolv tri, L_0x2c921d0, L_0x2c93620, L_0x2c94a90, L_0x2c95f10; +RS_0x7f99c4320aa8/0/48 .resolv tri, L_0x2c975d0, L_0x2c98a40, L_0x2c99ef0, L_0x2c9b360; +RS_0x7f99c4320aa8/0/52 .resolv tri, L_0x2c9c860, L_0x2c9dd70, L_0x2c9f130, L_0x2ca05b0; +RS_0x7f99c4320aa8/0/56 .resolv tri, L_0x2ca1aa0, L_0x2c062e0, L_0x2ca5450, L_0x2ca6d40; +RS_0x7f99c4320aa8/0/60 .resolv tri, L_0x2ca8230, L_0x2ca9730, L_0x2caac20, L_0x2cac110; +RS_0x7f99c4320aa8/1/0 .resolv tri, RS_0x7f99c4320aa8/0/0, RS_0x7f99c4320aa8/0/4, RS_0x7f99c4320aa8/0/8, RS_0x7f99c4320aa8/0/12; +RS_0x7f99c4320aa8/1/4 .resolv tri, RS_0x7f99c4320aa8/0/16, RS_0x7f99c4320aa8/0/20, RS_0x7f99c4320aa8/0/24, RS_0x7f99c4320aa8/0/28; +RS_0x7f99c4320aa8/1/8 .resolv tri, RS_0x7f99c4320aa8/0/32, RS_0x7f99c4320aa8/0/36, RS_0x7f99c4320aa8/0/40, RS_0x7f99c4320aa8/0/44; +RS_0x7f99c4320aa8/1/12 .resolv tri, RS_0x7f99c4320aa8/0/48, RS_0x7f99c4320aa8/0/52, RS_0x7f99c4320aa8/0/56, RS_0x7f99c4320aa8/0/60; +RS_0x7f99c4320aa8 .resolv tri, RS_0x7f99c4320aa8/1/0, RS_0x7f99c4320aa8/1/4, RS_0x7f99c4320aa8/1/8, RS_0x7f99c4320aa8/1/12; +v0x2bc76e0_0 .net8 "AddSubSLTSum", 31 0, RS_0x7f99c4320aa8; 64 drivers +v0x2bc7760_0 .net "AllZeros", 0 0, L_0x2c43980; 1 drivers +RS_0x7f99c4319e78/0/0 .resolv tri, L_0x2bf56a0, L_0x2bf6150, L_0x2bf6bc0, L_0x2bf7620; +RS_0x7f99c4319e78/0/4 .resolv tri, L_0x2bf8090, L_0x2bf8bf0, L_0x2bf9660, L_0x2bfa0c0; +RS_0x7f99c4319e78/0/8 .resolv tri, L_0x2bfab40, L_0x2bfb5b0, L_0x2bfc020, L_0x2bfca90; +RS_0x7f99c4319e78/0/12 .resolv tri, L_0x2bfd510, L_0x2bfe080, L_0x2bfeaf0, L_0x2bff560; +RS_0x7f99c4319e78/0/16 .resolv tri, L_0x2bfffe0, L_0x2c00a40, L_0x2c014c0, L_0x2c01f20; +RS_0x7f99c4319e78/0/20 .resolv tri, L_0x2c02990, L_0x2c03400, L_0x2c03e80, L_0x2c048e0; +RS_0x7f99c4319e78/0/24 .resolv tri, L_0x2c05350, L_0x2c06550, L_0x2c06ee0, L_0x2c07890; +RS_0x7f99c4319e78/0/28 .resolv tri, L_0x2c08250, L_0x2c08e10, L_0x2c097c0, L_0x2c0a170; +RS_0x7f99c4319e78/0/32 .resolv tri, L_0x2cae270, L_0x2caece0, L_0x2caf750, L_0x2cb01b0; +RS_0x7f99c4319e78/0/36 .resolv tri, L_0x2cb0c20, L_0x2cb16f0, L_0x2cb21f0, L_0x2cb2c50; +RS_0x7f99c4319e78/0/40 .resolv tri, L_0x2cb3540, L_0x2cb3ed0, L_0x2cb4880, L_0x2cb52f0; +RS_0x7f99c4319e78/0/44 .resolv tri, L_0x2cb5d70, L_0x2cb6810, L_0x2cb72c0, L_0x2cb7d70; +RS_0x7f99c4319e78/0/48 .resolv tri, L_0x2cb8830, L_0x2cb92d0, L_0x2cb9d90, L_0x2cba7f0; +RS_0x7f99c4319e78/0/52 .resolv tri, L_0x2cbb260, L_0x2cbbcd0, L_0x2cbc750, L_0x2cbd1b0; +RS_0x7f99c4319e78/0/56 .resolv tri, L_0x2cbdc20, L_0x2cbe640, L_0x2cbf110, L_0x2cbfbc0; +RS_0x7f99c4319e78/0/60 .resolv tri, L_0x2cc0640, L_0x2cc10a0, L_0x2cc1b10, L_0x2cc2c60; +RS_0x7f99c4319e78/1/0 .resolv tri, RS_0x7f99c4319e78/0/0, RS_0x7f99c4319e78/0/4, RS_0x7f99c4319e78/0/8, RS_0x7f99c4319e78/0/12; +RS_0x7f99c4319e78/1/4 .resolv tri, RS_0x7f99c4319e78/0/16, RS_0x7f99c4319e78/0/20, RS_0x7f99c4319e78/0/24, RS_0x7f99c4319e78/0/28; +RS_0x7f99c4319e78/1/8 .resolv tri, RS_0x7f99c4319e78/0/32, RS_0x7f99c4319e78/0/36, RS_0x7f99c4319e78/0/40, RS_0x7f99c4319e78/0/44; +RS_0x7f99c4319e78/1/12 .resolv tri, RS_0x7f99c4319e78/0/48, RS_0x7f99c4319e78/0/52, RS_0x7f99c4319e78/0/56, RS_0x7f99c4319e78/0/60; +RS_0x7f99c4319e78 .resolv tri, RS_0x7f99c4319e78/1/0, RS_0x7f99c4319e78/1/4, RS_0x7f99c4319e78/1/8, RS_0x7f99c4319e78/1/12; +v0x2bc77e0_0 .net8 "AndNandOut", 31 0, RS_0x7f99c4319e78; 64 drivers +v0x2bc7860_0 .var "B", 31 0; +v0x2bc78e0_0 .var "Command", 2 0; +RS_0x7f99c4320f28/0/0 .resolv tri, L_0x2c32350, L_0x2c34c80, L_0x2c37620, L_0x2c39df0; +RS_0x7f99c4320f28/0/4 .resolv tri, L_0x2c3c860, L_0x2c3f020, L_0x2c40fb0, L_0x2c43da0; +RS_0x7f99c4320f28/0/8 .resolv tri, L_0x2c46d50, L_0x2c2ca00, L_0x2c4c090, L_0x2c4e800; +RS_0x7f99c4320f28/0/12 .resolv tri, L_0x2c50fd0, L_0x2c526f0, L_0x2c54cb0, L_0x2c57a10; +RS_0x7f99c4320f28/0/16 .resolv tri, L_0x2c5ac10, L_0x2c5d140, L_0x2c5fb10, L_0x2c62240; +RS_0x7f99c4320f28/0/20 .resolv tri, L_0x2c64780, L_0x2c66f10, L_0x2c68f10, L_0x2c6b5a0; +RS_0x7f99c4320f28/0/24 .resolv tri, L_0x2be0b30, L_0x2c73e60, L_0x2c76620, L_0x2c78db0; +RS_0x7f99c4320f28/0/28 .resolv tri, L_0x2c7b5e0, L_0x2c7c950, L_0x2c49690, L_0x2cea940; +RS_0x7f99c4320f28/1/0 .resolv tri, RS_0x7f99c4320f28/0/0, RS_0x7f99c4320f28/0/4, RS_0x7f99c4320f28/0/8, RS_0x7f99c4320f28/0/12; +RS_0x7f99c4320f28/1/4 .resolv tri, RS_0x7f99c4320f28/0/16, RS_0x7f99c4320f28/0/20, RS_0x7f99c4320f28/0/24, RS_0x7f99c4320f28/0/28; +RS_0x7f99c4320f28 .resolv tri, RS_0x7f99c4320f28/1/0, RS_0x7f99c4320f28/1/4, C4, C4; +v0x2bc7960_0 .net8 "OneBitFinalOut", 31 0, RS_0x7f99c4320f28; 32 drivers +RS_0x7f99c4316848/0/0 .resolv tri, L_0x2c0b350, L_0x2c0c590, L_0x2c0d7c0, L_0x2c0ea70; +RS_0x7f99c4316848/0/4 .resolv tri, L_0x2c0fd70, L_0x2c11160, L_0x2c12460, L_0x2c13750; +RS_0x7f99c4316848/0/8 .resolv tri, L_0x2c14a60, L_0x2c15d60, L_0x2c17060, L_0x2c18350; +RS_0x7f99c4316848/0/12 .resolv tri, L_0x2c19670, L_0x2c1aa80, L_0x2c1bd80, L_0x2c1d070; +RS_0x7f99c4316848/0/16 .resolv tri, L_0x2c1e380, L_0x2c1f670, L_0x2c20970, L_0x2c21c70; +RS_0x7f99c4316848/0/20 .resolv tri, L_0x2c22f80, L_0x2c24270, L_0x2c25570, L_0x2c26870; +RS_0x7f99c4316848/0/24 .resolv tri, L_0x2c27b70, L_0x2c28e60, L_0x2c2a170, L_0x2c2b470; +RS_0x7f99c4316848/0/28 .resolv tri, L_0x2c2c770, L_0x2c2daa0, L_0x2c2ebf0, L_0x2c2fe80; +RS_0x7f99c4316848/0/32 .resolv tri, L_0x2cc3e00, L_0x2cc4f00, L_0x2cc6040, L_0x2cc7210; +RS_0x7f99c4316848/0/36 .resolv tri, L_0x2cc8510, L_0x2cc9870, L_0x2ccac00, L_0x2ccbef0; +RS_0x7f99c4316848/0/40 .resolv tri, L_0x2ccd220, L_0x2cce530, L_0x2ccf860, L_0x2cd0b90; +RS_0x7f99c4316848/0/44 .resolv tri, L_0x2cd1ef0, L_0x2cd3290, L_0x2cd4490, L_0x2cd55c0; +RS_0x7f99c4316848/0/48 .resolv tri, L_0x2cd67d0, L_0x2cd7b00, L_0x2cd8e40, L_0x2cda180; +RS_0x7f99c4316848/0/52 .resolv tri, L_0x2cdb4d0, L_0x2cdc840, L_0x2cddb80, L_0x2cdeec0; +RS_0x7f99c4316848/0/56 .resolv tri, L_0x2ce0200, L_0x2ce1570, L_0x2ce28c0, L_0x2ce3c00; +RS_0x7f99c4316848/0/60 .resolv tri, L_0x2ce4f00, L_0x2ce61f0, L_0x2ce7520, L_0x2ce8810; +RS_0x7f99c4316848/1/0 .resolv tri, RS_0x7f99c4316848/0/0, RS_0x7f99c4316848/0/4, RS_0x7f99c4316848/0/8, RS_0x7f99c4316848/0/12; +RS_0x7f99c4316848/1/4 .resolv tri, RS_0x7f99c4316848/0/16, RS_0x7f99c4316848/0/20, RS_0x7f99c4316848/0/24, RS_0x7f99c4316848/0/28; +RS_0x7f99c4316848/1/8 .resolv tri, RS_0x7f99c4316848/0/32, RS_0x7f99c4316848/0/36, RS_0x7f99c4316848/0/40, RS_0x7f99c4316848/0/44; +RS_0x7f99c4316848/1/12 .resolv tri, RS_0x7f99c4316848/0/48, RS_0x7f99c4316848/0/52, RS_0x7f99c4316848/0/56, RS_0x7f99c4316848/0/60; +RS_0x7f99c4316848 .resolv tri, RS_0x7f99c4316848/1/0, RS_0x7f99c4316848/1/4, RS_0x7f99c4316848/1/8, RS_0x7f99c4316848/1/12; +v0x2bc79e0_0 .net8 "OrNorXorOut", 31 0, RS_0x7f99c4316848; 64 drivers +RS_0x7f99c4320b68 .resolv tri, L_0x2bf4d00, L_0x2cad930, C4, C4; +v0x2bc7a60_0 .net8 "SLTflag", 0 0, RS_0x7f99c4320b68; 2 drivers +RS_0x7f99c4320f58/0/0 .resolv tri, L_0x2c32890, L_0x2c35150, L_0x2c37760, L_0x2c3a0b0; +RS_0x7f99c4320f58/0/4 .resolv tri, L_0x2c3c460, L_0x2c3e9e0, L_0x2c41370, L_0x2c39f80; +RS_0x7f99c4320f58/0/8 .resolv tri, L_0x2c465c0, L_0x2c48dd0, L_0x2c4b8e0, L_0x2c4e230; +RS_0x7f99c4320f58/0/12 .resolv tri, L_0x2c50810, L_0x2c52f80, L_0x2c54fd0, L_0x2c43f80; +RS_0x7f99c4320f58/0/16 .resolv tri, L_0x2c5b020, L_0x2c5e470, L_0x2c60b90, L_0x2c62560; +RS_0x7f99c4320f58/0/20 .resolv tri, L_0x2c64aa0, L_0x2c67230, L_0x2c69230, L_0x2c6b8c0; +RS_0x7f99c4320f58/0/24 .resolv tri, L_0x2be0e50, L_0x2c72b50, L_0x2c75340, L_0x2c77db0; +RS_0x7f99c4320f58/0/28 .resolv tri, L_0x2c7a400, L_0x2c7cba0, L_0x2c499b0, L_0x2c58e50; +RS_0x7f99c4320f58/1/0 .resolv tri, RS_0x7f99c4320f58/0/0, RS_0x7f99c4320f58/0/4, RS_0x7f99c4320f58/0/8, RS_0x7f99c4320f58/0/12; +RS_0x7f99c4320f58/1/4 .resolv tri, RS_0x7f99c4320f58/0/16, RS_0x7f99c4320f58/0/20, RS_0x7f99c4320f58/0/24, RS_0x7f99c4320f58/0/28; +RS_0x7f99c4320f58 .resolv tri, RS_0x7f99c4320f58/1/0, RS_0x7f99c4320f58/1/4, C4, C4; +v0x2bc7ae0_0 .net8 "ZeroFlag", 31 0, RS_0x7f99c4320f58; 32 drivers +v0x2bc7b60_0 .var "carryin", 31 0; +RS_0x7f99c4320da8 .resolv tri, L_0x2bf2530, L_0x2cab160, C4, C4; +v0x2bc7be0_0 .net8 "carryout", 0 0, RS_0x7f99c4320da8; 2 drivers +RS_0x7f99c4320e38 .resolv tri, L_0x2bf2750, L_0x2cab310, C4, C4; +v0x2bc7c60_0 .net8 "overflow", 0 0, RS_0x7f99c4320e38; 2 drivers +RS_0x7f99c4320e68/0/0 .resolv tri, L_0x2bc8f40, L_0x2bca620, L_0x2bcba90, L_0x2bcbe80; +RS_0x7f99c4320e68/0/4 .resolv tri, L_0x2bcd470, L_0x2bceae0, L_0x2bcffa0, L_0x2bd1490; +RS_0x7f99c4320e68/0/8 .resolv tri, L_0x2bd2c20, L_0x2bd4360, L_0x2bd56b0, L_0x2bd6bf0; +RS_0x7f99c4320e68/0/12 .resolv tri, L_0x2bd80a0, L_0x2bd97b0, L_0x2bdacf0, L_0x2bdc230; +RS_0x7f99c4320e68/0/16 .resolv tri, L_0x2bddae0, L_0x2bdecf0, L_0x2be0190, L_0x2b87780; +RS_0x7f99c4320e68/0/20 .resolv tri, L_0x2be3740, L_0x2be4b00, L_0x2be5ed0, L_0x2be7290; +RS_0x7f99c4320e68/0/24 .resolv tri, L_0x2be8750, L_0x2bea4f0, L_0x2beb520, L_0x2beca00; +RS_0x7f99c4320e68/0/28 .resolv tri, L_0x2bd9220, L_0x2bef6c0, L_0x2bf0ce0, L_0x2bf21d0; +RS_0x7f99c4320e68/0/32 .resolv tri, L_0x2c80880, L_0x2c840e0, L_0x2c85510, L_0x2c85900; +RS_0x7f99c4320e68/0/36 .resolv tri, L_0x2c86e10, L_0x2c88200, L_0x2c89600, L_0x2c8a9d0; +RS_0x7f99c4320e68/0/40 .resolv tri, L_0x2c8c0a0, L_0x2c8d3f0, L_0x2c8e930, L_0x2c8fe70; +RS_0x7f99c4320e68/0/44 .resolv tri, L_0x2c91320, L_0x2c92750, L_0x2c93bd0, L_0x2c95070; +RS_0x7f99c4320e68/0/48 .resolv tri, L_0x2c968a0, L_0x2c97b80, L_0x2c99020, L_0x2c9a0d0; +RS_0x7f99c4320e68/0/52 .resolv tri, L_0x2c9b540, L_0x2c9ca40, L_0x2c9df50, L_0x2c9f310; +RS_0x7f99c4320e68/0/56 .resolv tri, L_0x2ca0790, L_0x2c05490, L_0x2ca4190, L_0x2ca6340; +RS_0x7f99c4320e68/0/60 .resolv tri, L_0x2ca6f20, L_0x2ca8410, L_0x2ca9910, L_0x2caae00; +RS_0x7f99c4320e68/1/0 .resolv tri, RS_0x7f99c4320e68/0/0, RS_0x7f99c4320e68/0/4, RS_0x7f99c4320e68/0/8, RS_0x7f99c4320e68/0/12; +RS_0x7f99c4320e68/1/4 .resolv tri, RS_0x7f99c4320e68/0/16, RS_0x7f99c4320e68/0/20, RS_0x7f99c4320e68/0/24, RS_0x7f99c4320e68/0/28; +RS_0x7f99c4320e68/1/8 .resolv tri, RS_0x7f99c4320e68/0/32, RS_0x7f99c4320e68/0/36, RS_0x7f99c4320e68/0/40, RS_0x7f99c4320e68/0/44; +RS_0x7f99c4320e68/1/12 .resolv tri, RS_0x7f99c4320e68/0/48, RS_0x7f99c4320e68/0/52, RS_0x7f99c4320e68/0/56, RS_0x7f99c4320e68/0/60; +RS_0x7f99c4320e68 .resolv tri, RS_0x7f99c4320e68/1/0, RS_0x7f99c4320e68/1/4, RS_0x7f99c4320e68/1/8, RS_0x7f99c4320e68/1/12; +v0x2bc7ce0_0 .net8 "subtract", 31 0, RS_0x7f99c4320e68; 64 drivers +S_0x2ba3100 .scope module, "trial" "AddSubSLT32" 2 141, 3 205, S_0x270e6d0; + .timescale -9 -12; +P_0x2ba31f8 .param/l "size" 3 228, +C4<0100000>; +L_0x2bf2530/d .functor OR 1, L_0x2bf2640, C4<0>, C4<0>, C4<0>; +L_0x2bf2530 .delay (20000,20000,20000) L_0x2bf2530/d; +L_0x2bf2750/d .functor XOR 1, RS_0x7f99c4320da8, L_0x2bdd7a0, C4<0>, C4<0>; +L_0x2bf2750 .delay (40000,40000,40000) L_0x2bf2750/d; +L_0x2bdd840/d .functor AND 1, L_0x2bdd950, L_0x2bdd9f0, C4<1>, C4<1>; +L_0x2bdd840 .delay (20000,20000,20000) L_0x2bdd840/d; +L_0x2bf36c0/d .functor NOT 1, RS_0x7f99c4320e38, C4<0>, C4<0>, C4<0>; +L_0x2bf36c0 .delay (10000,10000,10000) L_0x2bf36c0/d; +L_0x2bf37b0/d .functor NOT 1, L_0x2bf3850, C4<0>, C4<0>, C4<0>; +L_0x2bf37b0 .delay (10000,10000,10000) L_0x2bf37b0/d; +L_0x2bf38f0/d .functor AND 1, L_0x2bf36c0, L_0x2bf3a70, C4<1>, C4<1>; +L_0x2bf38f0 .delay (20000,20000,20000) L_0x2bf38f0/d; +L_0x2bf3b10/d .functor AND 1, RS_0x7f99c4320e38, L_0x2bf37b0, C4<1>, C4<1>; +L_0x2bf3b10 .delay (20000,20000,20000) L_0x2bf3b10/d; +L_0x2bf3c50/d .functor AND 1, L_0x2bf38f0, L_0x2bdd840, C4<1>, C4<1>; +L_0x2bf3c50 .delay (20000,20000,20000) L_0x2bf3c50/d; +L_0x2bf4c00/d .functor AND 1, L_0x2bf3b10, L_0x2bdd840, C4<1>, C4<1>; +L_0x2bf4c00 .delay (20000,20000,20000) L_0x2bf4c00/d; +L_0x2bf4d00/d .functor OR 1, L_0x2bf3c50, L_0x2bf4c00, C4<0>, C4<0>; +L_0x2bf4d00 .delay (20000,20000,20000) L_0x2bf4d00/d; +v0x2bc6580_0 .net "A", 31 0, v0x2bc7660_0; 1 drivers +v0x2bc6620_0 .alias "AddSubSLTSum", 31 0, v0x2bc76e0_0; +v0x2bc66a0_0 .net "B", 31 0, v0x2bc7860_0; 1 drivers +RS_0x7f99c4331e48/0/0 .resolv tri, L_0x2bc8e50, L_0x2bca4e0, L_0x2bcb920, L_0x2bccee0; +RS_0x7f99c4331e48/0/4 .resolv tri, L_0x2bce540, L_0x2bcfab0, L_0x2bd0fd0, L_0x2bd24f0; +RS_0x7f99c4331e48/0/8 .resolv tri, L_0x2bd3b00, L_0x2bd5210, L_0x2bd6720, L_0x2bd7c30; +RS_0x7f99c4331e48/0/12 .resolv tri, L_0x2bce480, L_0x2bda830, L_0x2bdbd40, L_0x2bdd240; +RS_0x7f99c4331e48/0/16 .resolv tri, L_0x2bde830, L_0x2bdfca0, L_0x2b87690, L_0x2be3650; +RS_0x7f99c4331e48/0/20 .resolv tri, L_0x2be4a10, L_0x2be5de0, L_0x2be71a0, L_0x2be8660; +RS_0x7f99c4331e48/0/24 .resolv tri, L_0x2be9b50, L_0x2beb430, L_0x2bec910, L_0x2bede10; +RS_0x7f99c4331e48/0/28 .resolv tri, L_0x2bd9130, L_0x2bf0bf0, L_0x2bf20e0, L_0x2bf35d0; +RS_0x7f99c4331e48/1/0 .resolv tri, RS_0x7f99c4331e48/0/0, RS_0x7f99c4331e48/0/4, RS_0x7f99c4331e48/0/8, RS_0x7f99c4331e48/0/12; +RS_0x7f99c4331e48/1/4 .resolv tri, RS_0x7f99c4331e48/0/16, RS_0x7f99c4331e48/0/20, RS_0x7f99c4331e48/0/24, RS_0x7f99c4331e48/0/28; +RS_0x7f99c4331e48 .resolv tri, RS_0x7f99c4331e48/1/0, RS_0x7f99c4331e48/1/4, C4, C4; +v0x2bc6720_0 .net8 "CarryoutWire", 31 0, RS_0x7f99c4331e48; 32 drivers +v0x2bc67a0_0 .net "Command", 2 0, v0x2bc78e0_0; 1 drivers +v0x2bc6820_0 .net "Res0OF1", 0 0, L_0x2bf3b10; 1 drivers +v0x2bc68c0_0 .net "Res1OF0", 0 0, L_0x2bf38f0; 1 drivers +v0x2bc6960_0 .alias "SLTflag", 0 0, v0x2bc7a60_0; +v0x2bc6a80_0 .net "SLTflag0", 0 0, L_0x2bf3c50; 1 drivers +v0x2bc6b20_0 .net "SLTflag1", 0 0, L_0x2bf4c00; 1 drivers +v0x2bc6bc0_0 .net "SLTon", 0 0, L_0x2bdd840; 1 drivers +v0x2bc6c60_0 .net *"_s292", 0 0, L_0x2bf2640; 1 drivers +v0x2bc6d00_0 .net/s *"_s293", 0 0, C4<0>; 1 drivers +v0x2bc6da0_0 .net *"_s296", 0 0, L_0x2bdd7a0; 1 drivers +v0x2bc6ec0_0 .net *"_s298", 0 0, L_0x2bdd950; 1 drivers +v0x2bc6f60_0 .net *"_s300", 0 0, L_0x2bdd9f0; 1 drivers +v0x2bc6e20_0 .net *"_s302", 0 0, L_0x2bf3850; 1 drivers +v0x2bc70b0_0 .net *"_s304", 0 0, L_0x2bf3a70; 1 drivers +v0x2bc71d0_0 .net "carryin", 31 0, v0x2bc7b60_0; 1 drivers +v0x2bc7250_0 .alias "carryout", 0 0, v0x2bc7be0_0; +v0x2bc7130_0 .net "nAddSubSLTSum", 0 0, L_0x2bf37b0; 1 drivers +v0x2bc7380_0 .net "nOF", 0 0, L_0x2bf36c0; 1 drivers +v0x2bc72d0_0 .alias "overflow", 0 0, v0x2bc7c60_0; +v0x2bc7510_0 .alias "subtract", 31 0, v0x2bc7ce0_0; +L_0x2bc8d00 .part/pv L_0x2bc8850, 1, 1, 32; +L_0x2bc8e50 .part/pv L_0x2bc8ba0, 1, 1, 32; +L_0x2bc8f40 .part/pv L_0x2bc8580, 1, 1, 32; +L_0x2bc9070 .part v0x2bc7660_0, 1, 1; +L_0x2bc9220 .part v0x2bc7860_0, 1, 1; +L_0x2bc93d0 .part RS_0x7f99c4331e48, 0, 1; +L_0x2bca3f0 .part/pv L_0x2bc9f20, 2, 1, 32; +L_0x2bca4e0 .part/pv L_0x2bca290, 2, 1, 32; +L_0x2bca620 .part/pv L_0x2bc9c50, 2, 1, 32; +L_0x2bca710 .part v0x2bc7660_0, 2, 1; +L_0x2bca810 .part v0x2bc7860_0, 2, 1; +L_0x2bca940 .part RS_0x7f99c4331e48, 1, 1; +L_0x2bcb830 .part/pv L_0x2bcb3a0, 3, 1, 32; +L_0x2bcb920 .part/pv L_0x2bcb6f0, 3, 1, 32; +L_0x2bcba90 .part/pv L_0x2bcb0d0, 3, 1, 32; +L_0x2bcbb80 .part v0x2bc7660_0, 3, 1; +L_0x2bcbcb0 .part v0x2bc7860_0, 3, 1; +L_0x2bcbde0 .part RS_0x7f99c4331e48, 2, 1; +L_0x2bccdf0 .part/pv L_0x2bcc920, 4, 1, 32; +L_0x2bccee0 .part/pv L_0x2bccc90, 4, 1, 32; +L_0x2bcbe80 .part/pv L_0x2bcc650, 4, 1, 32; +L_0x2bcd0d0 .part v0x2bc7660_0, 4, 1; +L_0x2bccfd0 .part v0x2bc7860_0, 4, 1; +L_0x2bcd2c0 .part RS_0x7f99c4331e48, 3, 1; +L_0x2bce390 .part/pv L_0x2bcdee0, 5, 1, 32; +L_0x2bce540 .part/pv L_0x2bce230, 5, 1, 32; +L_0x2bcd470 .part/pv L_0x2bcdc10, 5, 1, 32; +L_0x2bce820 .part v0x2bc7660_0, 5, 1; +L_0x2bce630 .part v0x2bc7860_0, 5, 1; +L_0x2bcea40 .part RS_0x7f99c4331e48, 4, 1; +L_0x2bcf9c0 .part/pv L_0x2bcf4f0, 6, 1, 32; +L_0x2bcfab0 .part/pv L_0x2bcf860, 6, 1, 32; +L_0x2bceae0 .part/pv L_0x2bcf220, 6, 1, 32; +L_0x2bcfcb0 .part v0x2bc7660_0, 6, 1; +L_0x2bcfba0 .part v0x2bc7860_0, 6, 1; +L_0x2bcff00 .part RS_0x7f99c4331e48, 5, 1; +L_0x2bd0ee0 .part/pv L_0x2bd0a30, 7, 1, 32; +L_0x2bd0fd0 .part/pv L_0x2bd0d80, 7, 1, 32; +L_0x2bcffa0 .part/pv L_0x2bd0760, 7, 1, 32; +L_0x2bd1200 .part v0x2bc7660_0, 7, 1; +L_0x2bd10c0 .part v0x2bc7860_0, 7, 1; +L_0x2bd13f0 .part RS_0x7f99c4331e48, 6, 1; +L_0x2bd2400 .part/pv L_0x2bd1f50, 8, 1, 32; +L_0x2bd24f0 .part/pv L_0x2bd22a0, 8, 1, 32; +L_0x2bd1490 .part/pv L_0x2bd1c80, 8, 1, 32; +L_0x2bd2750 .part v0x2bc7660_0, 8, 1; +L_0x2bd25e0 .part v0x2bc7860_0, 8, 1; +L_0x2bd2970 .part RS_0x7f99c4331e48, 7, 1; +L_0x2bd3a10 .part/pv L_0x2bd3560, 9, 1, 32; +L_0x2bd3b00 .part/pv L_0x2bd38b0, 9, 1, 32; +L_0x2bd2c20 .part/pv L_0x2bd3290, 9, 1, 32; +L_0x2bd2d10 .part v0x2bc7660_0, 9, 1; +L_0x2bc9110 .part v0x2bc7860_0, 9, 1; +L_0x2bd3c80 .part RS_0x7f99c4331e48, 8, 1; +L_0x2bd5120 .part/pv L_0x2bd4c70, 10, 1, 32; +L_0x2bd5210 .part/pv L_0x2bd4fc0, 10, 1, 32; +L_0x2bd4360 .part/pv L_0x2bd49a0, 10, 1, 32; +L_0x2bd4450 .part v0x2bc7660_0, 10, 1; +L_0x2bd54e0 .part v0x2bc7860_0, 10, 1; +L_0x2bd5610 .part RS_0x7f99c4331e48, 9, 1; +L_0x2bd6630 .part/pv L_0x2bd6180, 11, 1, 32; +L_0x2bd6720 .part/pv L_0x2bd64d0, 11, 1, 32; +L_0x2bd56b0 .part/pv L_0x2bd5eb0, 11, 1, 32; +L_0x2bd57a0 .part v0x2bc7660_0, 11, 1; +L_0x2bd6a20 .part v0x2bc7860_0, 11, 1; +L_0x2bd6b50 .part RS_0x7f99c4331e48, 10, 1; +L_0x2bd7b40 .part/pv L_0x2bd7690, 12, 1, 32; +L_0x2bd7c30 .part/pv L_0x2bd79e0, 12, 1, 32; +L_0x2bd6bf0 .part/pv L_0x2bd73c0, 12, 1, 32; +L_0x2bd6ce0 .part v0x2bc7660_0, 12, 1; +L_0x2bd7f60 .part v0x2bc7860_0, 12, 1; +L_0x2bd8000 .part RS_0x7f99c4331e48, 11, 1; +L_0x2bd9040 .part/pv L_0x2bd8b90, 13, 1, 32; +L_0x2bce480 .part/pv L_0x2bd8ee0, 13, 1, 32; +L_0x2bd80a0 .part/pv L_0x2bd88c0, 13, 1, 32; +L_0x2bce760 .part v0x2bc7660_0, 13, 1; +L_0x2bd8140 .part v0x2bc7860_0, 13, 1; +L_0x2bd9340 .part RS_0x7f99c4331e48, 12, 1; +L_0x2bda740 .part/pv L_0x2bda290, 14, 1, 32; +L_0x2bda830 .part/pv L_0x2bda5e0, 14, 1, 32; +L_0x2bd97b0 .part/pv L_0x2bd9fc0, 14, 1, 32; +L_0x2bd98a0 .part v0x2bc7660_0, 14, 1; +L_0x2bd9940 .part v0x2bc7860_0, 14, 1; +L_0x2bdac50 .part RS_0x7f99c4331e48, 13, 1; +L_0x2bdbc50 .part/pv L_0x2bdb7a0, 15, 1, 32; +L_0x2bdbd40 .part/pv L_0x2bdbaf0, 15, 1, 32; +L_0x2bdacf0 .part/pv L_0x2bdb4d0, 15, 1, 32; +L_0x2bdade0 .part v0x2bc7660_0, 15, 1; +L_0x2bdae80 .part v0x2bc7860_0, 15, 1; +L_0x2bdc190 .part RS_0x7f99c4331e48, 14, 1; +L_0x2bdd150 .part/pv L_0x2bdcca0, 16, 1, 32; +L_0x2bdd240 .part/pv L_0x2bdcff0, 16, 1, 32; +L_0x2bdc230 .part/pv L_0x2bdc9d0, 16, 1, 32; +L_0x2bdc320 .part v0x2bc7660_0, 16, 1; +L_0x2bdc3c0 .part v0x2bc7860_0, 16, 1; +L_0x2bdd630 .part RS_0x7f99c4331e48, 15, 1; +L_0x2bde740 .part/pv L_0x2bde2b0, 17, 1, 32; +L_0x2bde830 .part/pv L_0x2bde600, 17, 1, 32; +L_0x2bddae0 .part/pv L_0x2bddfe0, 17, 1, 32; +L_0x2bddbd0 .part v0x2bc7660_0, 17, 1; +L_0x2bddc70 .part v0x2bc7860_0, 17, 1; +L_0x2bdec50 .part RS_0x7f99c4331e48, 16, 1; +L_0x2bdfbb0 .part/pv L_0x2bdf720, 18, 1, 32; +L_0x2bdfca0 .part/pv L_0x2bdfa70, 18, 1, 32; +L_0x2bdecf0 .part/pv L_0x2bdf450, 18, 1, 32; +L_0x2bdede0 .part v0x2bc7660_0, 18, 1; +L_0x2bdee80 .part v0x2bc7860_0, 18, 1; +L_0x2be00f0 .part RS_0x7f99c4331e48, 17, 1; +L_0x2b875a0 .part/pv L_0x2b870f0, 19, 1, 32; +L_0x2b87690 .part/pv L_0x2b87440, 19, 1, 32; +L_0x2be0190 .part/pv L_0x2be0900, 19, 1, 32; +L_0x2be0280 .part v0x2bc7660_0, 19, 1; +L_0x2be0320 .part v0x2bc7860_0, 19, 1; +L_0x2be0450 .part RS_0x7f99c4331e48, 18, 1; +L_0x2be3560 .part/pv L_0x2be30d0, 20, 1, 32; +L_0x2be3650 .part/pv L_0x2be3420, 20, 1, 32; +L_0x2b87780 .part/pv L_0x2be2e00, 20, 1, 32; +L_0x2b87870 .part v0x2bc7660_0, 20, 1; +L_0x2b87910 .part v0x2bc7860_0, 20, 1; +L_0x2b87a40 .part RS_0x7f99c4331e48, 19, 1; +L_0x2be4920 .part/pv L_0x2be4490, 21, 1, 32; +L_0x2be4a10 .part/pv L_0x2be47e0, 21, 1, 32; +L_0x2be3740 .part/pv L_0x2be41c0, 21, 1, 32; +L_0x2be3830 .part v0x2bc7660_0, 21, 1; +L_0x2be38d0 .part v0x2bc7860_0, 21, 1; +L_0x2be3a00 .part RS_0x7f99c4331e48, 20, 1; +L_0x2be5cf0 .part/pv L_0x2be5860, 22, 1, 32; +L_0x2be5de0 .part/pv L_0x2be5bb0, 22, 1, 32; +L_0x2be4b00 .part/pv L_0x2be5590, 22, 1, 32; +L_0x2be4bf0 .part v0x2bc7660_0, 22, 1; +L_0x2be4c90 .part v0x2bc7860_0, 22, 1; +L_0x2be4dc0 .part RS_0x7f99c4331e48, 21, 1; +L_0x2be70b0 .part/pv L_0x2be6c20, 23, 1, 32; +L_0x2be71a0 .part/pv L_0x2be6f70, 23, 1, 32; +L_0x2be5ed0 .part/pv L_0x2be6950, 23, 1, 32; +L_0x2be5fc0 .part v0x2bc7660_0, 23, 1; +L_0x2be6060 .part v0x2bc7860_0, 23, 1; +L_0x2be6190 .part RS_0x7f99c4331e48, 22, 1; +L_0x2be8570 .part/pv L_0x2be8040, 24, 1, 32; +L_0x2be8660 .part/pv L_0x2be8410, 24, 1, 32; +L_0x2be7290 .part/pv L_0x2be7d70, 24, 1, 32; +L_0x2be7380 .part v0x2bc7660_0, 24, 1; +L_0x2be7420 .part v0x2bc7860_0, 24, 1; +L_0x2be7550 .part RS_0x7f99c4331e48, 23, 1; +L_0x2be9a60 .part/pv L_0x2be9530, 25, 1, 32; +L_0x2be9b50 .part/pv L_0x2be9900, 25, 1, 32; +L_0x2be8750 .part/pv L_0x2be9260, 25, 1, 32; +L_0x2be8840 .part v0x2bc7660_0, 25, 1; +L_0x2bd3d90 .part v0x2bc7860_0, 25, 1; +L_0x2bd3ec0 .part RS_0x7f99c4331e48, 24, 1; +L_0x2beb340 .part/pv L_0x2beaeb0, 26, 1, 32; +L_0x2beb430 .part/pv L_0x2beb200, 26, 1, 32; +L_0x2bea4f0 .part/pv L_0x2beabe0, 26, 1, 32; +L_0x2bea5e0 .part v0x2bc7660_0, 26, 1; +L_0x2bea680 .part v0x2bc7860_0, 26, 1; +L_0x2bea7b0 .part RS_0x7f99c4331e48, 25, 1; +L_0x2bec820 .part/pv L_0x2bec2f0, 27, 1, 32; +L_0x2bec910 .part/pv L_0x2bec6c0, 27, 1, 32; +L_0x2beb520 .part/pv L_0x2bec020, 27, 1, 32; +L_0x2beb610 .part v0x2bc7660_0, 27, 1; +L_0x2beb6b0 .part v0x2bc7860_0, 27, 1; +L_0x2beb7e0 .part RS_0x7f99c4331e48, 26, 1; +L_0x2bedd20 .part/pv L_0x2bed810, 28, 1, 32; +L_0x2bede10 .part/pv L_0x2bedbc0, 28, 1, 32; +L_0x2beca00 .part/pv L_0x2bed510, 28, 1, 32; +L_0x2becaf0 .part v0x2bc7660_0, 28, 1; +L_0x2becb90 .part v0x2bc7860_0, 28, 1; +L_0x2beccc0 .part RS_0x7f99c4331e48, 27, 1; +L_0x2bef210 .part/pv L_0x2beed00, 29, 1, 32; +L_0x2bd9130 .part/pv L_0x2bef0b0, 29, 1, 32; +L_0x2bd9220 .part/pv L_0x2beea00, 29, 1, 32; +L_0x2bee360 .part v0x2bc7660_0, 29, 1; +L_0x2bd95a0 .part v0x2bc7860_0, 29, 1; +L_0x2bd96d0 .part RS_0x7f99c4331e48, 28, 1; +L_0x2bf0b00 .part/pv L_0x2bf05d0, 30, 1, 32; +L_0x2bf0bf0 .part/pv L_0x2bf09a0, 30, 1, 32; +L_0x2bef6c0 .part/pv L_0x2bf0300, 30, 1, 32; +L_0x2bef7b0 .part v0x2bc7660_0, 30, 1; +L_0x2bef850 .part v0x2bc7860_0, 30, 1; +L_0x2bef980 .part RS_0x7f99c4331e48, 29, 1; +L_0x2bf1ff0 .part/pv L_0x2bf1ae0, 31, 1, 32; +L_0x2bf20e0 .part/pv L_0x2bf1e90, 31, 1, 32; +L_0x2bf0ce0 .part/pv L_0x2bf17e0, 31, 1, 32; +L_0x2bf0dd0 .part v0x2bc7660_0, 31, 1; +L_0x2bf0e70 .part v0x2bc7860_0, 31, 1; +L_0x2bf0fa0 .part RS_0x7f99c4331e48, 30, 1; +L_0x2bf34e0 .part/pv L_0x2bf2fd0, 0, 1, 32; +L_0x2bf35d0 .part/pv L_0x2bf3380, 0, 1, 32; +L_0x2bf21d0 .part/pv L_0x2bf2d00, 0, 1, 32; +L_0x2bf22c0 .part v0x2bc7660_0, 0, 1; +L_0x2bf2360 .part v0x2bc7860_0, 0, 1; +L_0x2bf2490 .part RS_0x7f99c4320e68, 0, 1; +L_0x2bf2640 .part RS_0x7f99c4331e48, 31, 1; +L_0x2bdd7a0 .part RS_0x7f99c4331e48, 30, 1; +L_0x2bdd950 .part v0x2bc78e0_0, 1, 1; +L_0x2bdd9f0 .part RS_0x7f99c4320e68, 0, 1; +L_0x2bf3850 .part RS_0x7f99c4320aa8, 31, 1; +L_0x2bf3a70 .part RS_0x7f99c4320aa8, 31, 1; +S_0x2bc5570 .scope module, "attempt2" "MiddleAddSubSLT" 3 225, 3 89, S_0x2ba3100; + .timescale -9 -12; +L_0x2bf1040/d .functor NOT 1, L_0x2bf2360, C4<0>, C4<0>, C4<0>; +L_0x2bf1040 .delay (10000,10000,10000) L_0x2bf1040/d; +L_0x2bf2bc0/d .functor NOT 1, L_0x2bf2c60, C4<0>, C4<0>, C4<0>; +L_0x2bf2bc0 .delay (10000,10000,10000) L_0x2bf2bc0/d; +L_0x2bf2d00/d .functor AND 1, L_0x2bf2e40, L_0x2bf2bc0, C4<1>, C4<1>; +L_0x2bf2d00 .delay (20000,20000,20000) L_0x2bf2d00/d; +L_0x2bf2ee0/d .functor XOR 1, L_0x2bf22c0, L_0x2bf2990, C4<0>, C4<0>; +L_0x2bf2ee0 .delay (40000,40000,40000) L_0x2bf2ee0/d; +L_0x2bf2fd0/d .functor XOR 1, L_0x2bf2ee0, L_0x2bf2490, C4<0>, C4<0>; +L_0x2bf2fd0 .delay (40000,40000,40000) L_0x2bf2fd0/d; +L_0x2bf30f0/d .functor AND 1, L_0x2bf22c0, L_0x2bf2990, C4<1>, C4<1>; +L_0x2bf30f0 .delay (20000,20000,20000) L_0x2bf30f0/d; +L_0x2bf3290/d .functor AND 1, L_0x2bf2ee0, L_0x2bf2490, C4<1>, C4<1>; +L_0x2bf3290 .delay (20000,20000,20000) L_0x2bf3290/d; +L_0x2bf3380/d .functor OR 1, L_0x2bf30f0, L_0x2bf3290, C4<0>, C4<0>; +L_0x2bf3380 .delay (20000,20000,20000) L_0x2bf3380/d; +v0x2bc5be0_0 .net "A", 0 0, L_0x2bf22c0; 1 drivers +v0x2bc5ca0_0 .net "AandB", 0 0, L_0x2bf30f0; 1 drivers +v0x2bc5d40_0 .net "AddSubSLTSum", 0 0, L_0x2bf2fd0; 1 drivers +v0x2bc5de0_0 .net "AxorB", 0 0, L_0x2bf2ee0; 1 drivers +v0x2bc5e60_0 .net "B", 0 0, L_0x2bf2360; 1 drivers +v0x2bc5f10_0 .net "BornB", 0 0, L_0x2bf2990; 1 drivers +v0x2bc5fd0_0 .net "CINandAxorB", 0 0, L_0x2bf3290; 1 drivers +v0x2bc6050_0 .alias "Command", 2 0, v0x2bc67a0_0; +v0x2bc60d0_0 .net *"_s3", 0 0, L_0x2bf2c60; 1 drivers +v0x2bc6150_0 .net *"_s5", 0 0, L_0x2bf2e40; 1 drivers +v0x2bc61f0_0 .net "carryin", 0 0, L_0x2bf2490; 1 drivers +v0x2bc6290_0 .net "carryout", 0 0, L_0x2bf3380; 1 drivers +v0x2bc6330_0 .net "nB", 0 0, L_0x2bf1040; 1 drivers +v0x2bc63e0_0 .net "nCmd2", 0 0, L_0x2bf2bc0; 1 drivers +v0x2bc64e0_0 .net "subtract", 0 0, L_0x2bf2d00; 1 drivers +L_0x2bf2b20 .part v0x2bc78e0_0, 0, 1; +L_0x2bf2c60 .part v0x2bc78e0_0, 2, 1; +L_0x2bf2e40 .part v0x2bc78e0_0, 0, 1; +S_0x2bc5660 .scope module, "mux0" "TwoInMux" 3 105, 3 8, S_0x2bc5570; + .timescale -9 -12; +L_0x2bf11a0/d .functor NOT 1, L_0x2bf2b20, C4<0>, C4<0>, C4<0>; +L_0x2bf11a0 .delay (10000,10000,10000) L_0x2bf11a0/d; +L_0x2bf27b0/d .functor AND 1, L_0x2bf2360, L_0x2bf11a0, C4<1>, C4<1>; +L_0x2bf27b0 .delay (20000,20000,20000) L_0x2bf27b0/d; +L_0x2bf28a0/d .functor AND 1, L_0x2bf1040, L_0x2bf2b20, C4<1>, C4<1>; +L_0x2bf28a0 .delay (20000,20000,20000) L_0x2bf28a0/d; +L_0x2bf2990/d .functor OR 1, L_0x2bf27b0, L_0x2bf28a0, C4<0>, C4<0>; +L_0x2bf2990 .delay (20000,20000,20000) L_0x2bf2990/d; +v0x2bc5750_0 .net "S", 0 0, L_0x2bf2b20; 1 drivers +v0x2bc5810_0 .alias "in0", 0 0, v0x2bc5e60_0; +v0x2bc58b0_0 .alias "in1", 0 0, v0x2bc6330_0; +v0x2bc5950_0 .net "nS", 0 0, L_0x2bf11a0; 1 drivers +v0x2bc5a00_0 .net "out0", 0 0, L_0x2bf27b0; 1 drivers +v0x2bc5aa0_0 .net "out1", 0 0, L_0x2bf28a0; 1 drivers +v0x2bc5b40_0 .alias "outfinal", 0 0, v0x2bc5f10_0; +S_0x2bc43d0 .scope generate, "addbits[1]" "addbits[1]" 3 230, 3 230, S_0x2ba3100; + .timescale -9 -12; +P_0x2bc3de8 .param/l "i" 3 230, +C4<01>; +S_0x2bc4540 .scope module, "attempt" "MiddleAddSubSLT" 3 232, 3 89, S_0x2bc43d0; + .timescale -9 -12; +L_0x2baaa50/d .functor NOT 1, L_0x2bc9220, C4<0>, C4<0>, C4<0>; +L_0x2baaa50 .delay (10000,10000,10000) L_0x2baaa50/d; +L_0x2bc8420/d .functor NOT 1, L_0x2bc84e0, C4<0>, C4<0>, C4<0>; +L_0x2bc8420 .delay (10000,10000,10000) L_0x2bc8420/d; +L_0x2bc8580/d .functor AND 1, L_0x2bc86c0, L_0x2bc8420, C4<1>, C4<1>; +L_0x2bc8580 .delay (20000,20000,20000) L_0x2bc8580/d; +L_0x2bc8760/d .functor XOR 1, L_0x2bc9070, L_0x2bc81b0, C4<0>, C4<0>; +L_0x2bc8760 .delay (40000,40000,40000) L_0x2bc8760/d; +L_0x2bc8850/d .functor XOR 1, L_0x2bc8760, L_0x2bc93d0, C4<0>, C4<0>; +L_0x2bc8850 .delay (40000,40000,40000) L_0x2bc8850/d; +L_0x2bc8940/d .functor AND 1, L_0x2bc9070, L_0x2bc81b0, C4<1>, C4<1>; +L_0x2bc8940 .delay (20000,20000,20000) L_0x2bc8940/d; +L_0x2bc8ab0/d .functor AND 1, L_0x2bc8760, L_0x2bc93d0, C4<1>, C4<1>; +L_0x2bc8ab0 .delay (20000,20000,20000) L_0x2bc8ab0/d; +L_0x2bc8ba0/d .functor OR 1, L_0x2bc8940, L_0x2bc8ab0, C4<0>, C4<0>; +L_0x2bc8ba0 .delay (20000,20000,20000) L_0x2bc8ba0/d; +v0x2bc4bd0_0 .net "A", 0 0, L_0x2bc9070; 1 drivers +v0x2bc4c90_0 .net "AandB", 0 0, L_0x2bc8940; 1 drivers +v0x2bc4d30_0 .net "AddSubSLTSum", 0 0, L_0x2bc8850; 1 drivers +v0x2bc4dd0_0 .net "AxorB", 0 0, L_0x2bc8760; 1 drivers +v0x2bc4e50_0 .net "B", 0 0, L_0x2bc9220; 1 drivers +v0x2bc4f00_0 .net "BornB", 0 0, L_0x2bc81b0; 1 drivers +v0x2bc4fc0_0 .net "CINandAxorB", 0 0, L_0x2bc8ab0; 1 drivers +v0x2bc5040_0 .alias "Command", 2 0, v0x2bc67a0_0; +v0x2bc50c0_0 .net *"_s3", 0 0, L_0x2bc84e0; 1 drivers +v0x2bc5140_0 .net *"_s5", 0 0, L_0x2bc86c0; 1 drivers +v0x2bc51e0_0 .net "carryin", 0 0, L_0x2bc93d0; 1 drivers +v0x2bc5280_0 .net "carryout", 0 0, L_0x2bc8ba0; 1 drivers +v0x2bc5320_0 .net "nB", 0 0, L_0x2baaa50; 1 drivers +v0x2bc53d0_0 .net "nCmd2", 0 0, L_0x2bc8420; 1 drivers +v0x2bc54d0_0 .net "subtract", 0 0, L_0x2bc8580; 1 drivers +L_0x2bc8380 .part v0x2bc78e0_0, 0, 1; +L_0x2bc84e0 .part v0x2bc78e0_0, 2, 1; +L_0x2bc86c0 .part v0x2bc78e0_0, 0, 1; +S_0x2bc4630 .scope module, "mux0" "TwoInMux" 3 105, 3 8, S_0x2bc4540; + .timescale -9 -12; +L_0x2bc7ed0/d .functor NOT 1, L_0x2bc8380, C4<0>, C4<0>, C4<0>; +L_0x2bc7ed0 .delay (10000,10000,10000) L_0x2bc7ed0/d; +L_0x2bc7f90/d .functor AND 1, L_0x2bc9220, L_0x2bc7ed0, C4<1>, C4<1>; +L_0x2bc7f90 .delay (20000,20000,20000) L_0x2bc7f90/d; +L_0x2bc80a0/d .functor AND 1, L_0x2baaa50, L_0x2bc8380, C4<1>, C4<1>; +L_0x2bc80a0 .delay (20000,20000,20000) L_0x2bc80a0/d; +L_0x2bc81b0/d .functor OR 1, L_0x2bc7f90, L_0x2bc80a0, C4<0>, C4<0>; +L_0x2bc81b0 .delay (20000,20000,20000) L_0x2bc81b0/d; +v0x2bc4720_0 .net "S", 0 0, L_0x2bc8380; 1 drivers +v0x2bc47c0_0 .alias "in0", 0 0, v0x2bc4e50_0; +v0x2bc4860_0 .alias "in1", 0 0, v0x2bc5320_0; +v0x2bc4900_0 .net "nS", 0 0, L_0x2bc7ed0; 1 drivers +v0x2bc49b0_0 .net "out0", 0 0, L_0x2bc7f90; 1 drivers +v0x2bc4a50_0 .net "out1", 0 0, L_0x2bc80a0; 1 drivers +v0x2bc4b30_0 .alias "outfinal", 0 0, v0x2bc4f00_0; +S_0x2bc3230 .scope generate, "addbits[2]" "addbits[2]" 3 230, 3 230, S_0x2ba3100; + .timescale -9 -12; +P_0x2bc2c48 .param/l "i" 3 230, +C4<010>; +S_0x2bc33a0 .scope module, "attempt" "MiddleAddSubSLT" 3 232, 3 89, S_0x2bc3230; + .timescale -9 -12; +L_0x2b8b5b0/d .functor NOT 1, L_0x2bca810, C4<0>, C4<0>, C4<0>; +L_0x2b8b5b0 .delay (10000,10000,10000) L_0x2b8b5b0/d; +L_0x2bc9af0/d .functor NOT 1, L_0x2bc9bb0, C4<0>, C4<0>, C4<0>; +L_0x2bc9af0 .delay (10000,10000,10000) L_0x2bc9af0/d; +L_0x2bc9c50/d .functor AND 1, L_0x2bc9d90, L_0x2bc9af0, C4<1>, C4<1>; +L_0x2bc9c50 .delay (20000,20000,20000) L_0x2bc9c50/d; +L_0x2bc9e30/d .functor XOR 1, L_0x2bca710, L_0x2bc9880, C4<0>, C4<0>; +L_0x2bc9e30 .delay (40000,40000,40000) L_0x2bc9e30/d; +L_0x2bc9f20/d .functor XOR 1, L_0x2bc9e30, L_0x2bca940, C4<0>, C4<0>; +L_0x2bc9f20 .delay (40000,40000,40000) L_0x2bc9f20/d; +L_0x2bca010/d .functor AND 1, L_0x2bca710, L_0x2bc9880, C4<1>, C4<1>; +L_0x2bca010 .delay (20000,20000,20000) L_0x2bca010/d; +L_0x2bca180/d .functor AND 1, L_0x2bc9e30, L_0x2bca940, C4<1>, C4<1>; +L_0x2bca180 .delay (20000,20000,20000) L_0x2bca180/d; +L_0x2bca290/d .functor OR 1, L_0x2bca010, L_0x2bca180, C4<0>, C4<0>; +L_0x2bca290 .delay (20000,20000,20000) L_0x2bca290/d; +v0x2bc3a30_0 .net "A", 0 0, L_0x2bca710; 1 drivers +v0x2bc3af0_0 .net "AandB", 0 0, L_0x2bca010; 1 drivers +v0x2bc3b90_0 .net "AddSubSLTSum", 0 0, L_0x2bc9f20; 1 drivers +v0x2bc3c30_0 .net "AxorB", 0 0, L_0x2bc9e30; 1 drivers +v0x2bc3cb0_0 .net "B", 0 0, L_0x2bca810; 1 drivers +v0x2bc3d60_0 .net "BornB", 0 0, L_0x2bc9880; 1 drivers +v0x2bc3e20_0 .net "CINandAxorB", 0 0, L_0x2bca180; 1 drivers +v0x2bc3ea0_0 .alias "Command", 2 0, v0x2bc67a0_0; +v0x2bc3f20_0 .net *"_s3", 0 0, L_0x2bc9bb0; 1 drivers +v0x2bc3fa0_0 .net *"_s5", 0 0, L_0x2bc9d90; 1 drivers +v0x2bc4040_0 .net "carryin", 0 0, L_0x2bca940; 1 drivers +v0x2bc40e0_0 .net "carryout", 0 0, L_0x2bca290; 1 drivers +v0x2bc4180_0 .net "nB", 0 0, L_0x2b8b5b0; 1 drivers +v0x2bc4230_0 .net "nCmd2", 0 0, L_0x2bc9af0; 1 drivers +v0x2bc4330_0 .net "subtract", 0 0, L_0x2bc9c50; 1 drivers +L_0x2bc9a50 .part v0x2bc78e0_0, 0, 1; +L_0x2bc9bb0 .part v0x2bc78e0_0, 2, 1; +L_0x2bc9d90 .part v0x2bc78e0_0, 0, 1; +S_0x2bc3490 .scope module, "mux0" "TwoInMux" 3 105, 3 8, S_0x2bc33a0; + .timescale -9 -12; +L_0x2bc95a0/d .functor NOT 1, L_0x2bc9a50, C4<0>, C4<0>, C4<0>; +L_0x2bc95a0 .delay (10000,10000,10000) L_0x2bc95a0/d; +L_0x2bc9660/d .functor AND 1, L_0x2bca810, L_0x2bc95a0, C4<1>, C4<1>; +L_0x2bc9660 .delay (20000,20000,20000) L_0x2bc9660/d; +L_0x2bc9770/d .functor AND 1, L_0x2b8b5b0, L_0x2bc9a50, C4<1>, C4<1>; +L_0x2bc9770 .delay (20000,20000,20000) L_0x2bc9770/d; +L_0x2bc9880/d .functor OR 1, L_0x2bc9660, L_0x2bc9770, C4<0>, C4<0>; +L_0x2bc9880 .delay (20000,20000,20000) L_0x2bc9880/d; +v0x2bc3580_0 .net "S", 0 0, L_0x2bc9a50; 1 drivers +v0x2bc3620_0 .alias "in0", 0 0, v0x2bc3cb0_0; +v0x2bc36c0_0 .alias "in1", 0 0, v0x2bc4180_0; +v0x2bc3760_0 .net "nS", 0 0, L_0x2bc95a0; 1 drivers +v0x2bc3810_0 .net "out0", 0 0, L_0x2bc9660; 1 drivers +v0x2bc38b0_0 .net "out1", 0 0, L_0x2bc9770; 1 drivers +v0x2bc3990_0 .alias "outfinal", 0 0, v0x2bc3d60_0; +S_0x2bc2090 .scope generate, "addbits[3]" "addbits[3]" 3 230, 3 230, S_0x2ba3100; + .timescale -9 -12; +P_0x2bc1aa8 .param/l "i" 3 230, +C4<011>; +S_0x2bc2200 .scope module, "attempt" "MiddleAddSubSLT" 3 232, 3 89, S_0x2bc2090; + .timescale -9 -12; +L_0x2bca7b0/d .functor NOT 1, L_0x2bcbcb0, C4<0>, C4<0>, C4<0>; +L_0x2bca7b0 .delay (10000,10000,10000) L_0x2bca7b0/d; +L_0x2baabf0/d .functor NOT 1, L_0x2bcb030, C4<0>, C4<0>, C4<0>; +L_0x2baabf0 .delay (10000,10000,10000) L_0x2baabf0/d; +L_0x2bcb0d0/d .functor AND 1, L_0x2bcb210, L_0x2baabf0, C4<1>, C4<1>; +L_0x2bcb0d0 .delay (20000,20000,20000) L_0x2bcb0d0/d; +L_0x2bcb2b0/d .functor XOR 1, L_0x2bcbb80, L_0x2bcad70, C4<0>, C4<0>; +L_0x2bcb2b0 .delay (40000,40000,40000) L_0x2bcb2b0/d; +L_0x2bcb3a0/d .functor XOR 1, L_0x2bcb2b0, L_0x2bcbde0, C4<0>, C4<0>; +L_0x2bcb3a0 .delay (40000,40000,40000) L_0x2bcb3a0/d; +L_0x2bcb490/d .functor AND 1, L_0x2bcbb80, L_0x2bcad70, C4<1>, C4<1>; +L_0x2bcb490 .delay (20000,20000,20000) L_0x2bcb490/d; +L_0x2bcb600/d .functor AND 1, L_0x2bcb2b0, L_0x2bcbde0, C4<1>, C4<1>; +L_0x2bcb600 .delay (20000,20000,20000) L_0x2bcb600/d; +L_0x2bcb6f0/d .functor OR 1, L_0x2bcb490, L_0x2bcb600, C4<0>, C4<0>; +L_0x2bcb6f0 .delay (20000,20000,20000) L_0x2bcb6f0/d; +v0x2bc2890_0 .net "A", 0 0, L_0x2bcbb80; 1 drivers +v0x2bc2950_0 .net "AandB", 0 0, L_0x2bcb490; 1 drivers +v0x2bc29f0_0 .net "AddSubSLTSum", 0 0, L_0x2bcb3a0; 1 drivers +v0x2bc2a90_0 .net "AxorB", 0 0, L_0x2bcb2b0; 1 drivers +v0x2bc2b10_0 .net "B", 0 0, L_0x2bcbcb0; 1 drivers +v0x2bc2bc0_0 .net "BornB", 0 0, L_0x2bcad70; 1 drivers +v0x2bc2c80_0 .net "CINandAxorB", 0 0, L_0x2bcb600; 1 drivers +v0x2bc2d00_0 .alias "Command", 2 0, v0x2bc67a0_0; +v0x2bc2d80_0 .net *"_s3", 0 0, L_0x2bcb030; 1 drivers +v0x2bc2e00_0 .net *"_s5", 0 0, L_0x2bcb210; 1 drivers +v0x2bc2ea0_0 .net "carryin", 0 0, L_0x2bcbde0; 1 drivers +v0x2bc2f40_0 .net "carryout", 0 0, L_0x2bcb6f0; 1 drivers +v0x2bc2fe0_0 .net "nB", 0 0, L_0x2bca7b0; 1 drivers +v0x2bc3090_0 .net "nCmd2", 0 0, L_0x2baabf0; 1 drivers +v0x2bc3190_0 .net "subtract", 0 0, L_0x2bcb0d0; 1 drivers +L_0x2bcaf40 .part v0x2bc78e0_0, 0, 1; +L_0x2bcb030 .part v0x2bc78e0_0, 2, 1; +L_0x2bcb210 .part v0x2bc78e0_0, 0, 1; +S_0x2bc22f0 .scope module, "mux0" "TwoInMux" 3 105, 3 8, S_0x2bc2200; + .timescale -9 -12; +L_0x2bcaad0/d .functor NOT 1, L_0x2bcaf40, C4<0>, C4<0>, C4<0>; +L_0x2bcaad0 .delay (10000,10000,10000) L_0x2bcaad0/d; +L_0x2bcab50/d .functor AND 1, L_0x2bcbcb0, L_0x2bcaad0, C4<1>, C4<1>; +L_0x2bcab50 .delay (20000,20000,20000) L_0x2bcab50/d; +L_0x2bcac60/d .functor AND 1, L_0x2bca7b0, L_0x2bcaf40, C4<1>, C4<1>; +L_0x2bcac60 .delay (20000,20000,20000) L_0x2bcac60/d; +L_0x2bcad70/d .functor OR 1, L_0x2bcab50, L_0x2bcac60, C4<0>, C4<0>; +L_0x2bcad70 .delay (20000,20000,20000) L_0x2bcad70/d; +v0x2bc23e0_0 .net "S", 0 0, L_0x2bcaf40; 1 drivers +v0x2bc2480_0 .alias "in0", 0 0, v0x2bc2b10_0; +v0x2bc2520_0 .alias "in1", 0 0, v0x2bc2fe0_0; +v0x2bc25c0_0 .net "nS", 0 0, L_0x2bcaad0; 1 drivers +v0x2bc2670_0 .net "out0", 0 0, L_0x2bcab50; 1 drivers +v0x2bc2710_0 .net "out1", 0 0, L_0x2bcac60; 1 drivers +v0x2bc27f0_0 .alias "outfinal", 0 0, v0x2bc2bc0_0; +S_0x2bc0ef0 .scope generate, "addbits[4]" "addbits[4]" 3 230, 3 230, S_0x2ba3100; + .timescale -9 -12; +P_0x2bc0908 .param/l "i" 3 230, +C4<0100>; +S_0x2bc1060 .scope module, "attempt" "MiddleAddSubSLT" 3 232, 3 89, S_0x2bc0ef0; + .timescale -9 -12; +L_0x2bcbc20/d .functor NOT 1, L_0x2bccfd0, C4<0>, C4<0>, C4<0>; +L_0x2bcbc20 .delay (10000,10000,10000) L_0x2bcbc20/d; +L_0x2bcc4f0/d .functor NOT 1, L_0x2bcc5b0, C4<0>, C4<0>, C4<0>; +L_0x2bcc4f0 .delay (10000,10000,10000) L_0x2bcc4f0/d; +L_0x2bcc650/d .functor AND 1, L_0x2bcc790, L_0x2bcc4f0, C4<1>, C4<1>; +L_0x2bcc650 .delay (20000,20000,20000) L_0x2bcc650/d; +L_0x2bcc830/d .functor XOR 1, L_0x2bcd0d0, L_0x2bcc280, C4<0>, C4<0>; +L_0x2bcc830 .delay (40000,40000,40000) L_0x2bcc830/d; +L_0x2bcc920/d .functor XOR 1, L_0x2bcc830, L_0x2bcd2c0, C4<0>, C4<0>; +L_0x2bcc920 .delay (40000,40000,40000) L_0x2bcc920/d; +L_0x2bcca10/d .functor AND 1, L_0x2bcd0d0, L_0x2bcc280, C4<1>, C4<1>; +L_0x2bcca10 .delay (20000,20000,20000) L_0x2bcca10/d; +L_0x2bccb80/d .functor AND 1, L_0x2bcc830, L_0x2bcd2c0, C4<1>, C4<1>; +L_0x2bccb80 .delay (20000,20000,20000) L_0x2bccb80/d; +L_0x2bccc90/d .functor OR 1, L_0x2bcca10, L_0x2bccb80, C4<0>, C4<0>; +L_0x2bccc90 .delay (20000,20000,20000) L_0x2bccc90/d; +v0x2bc16f0_0 .net "A", 0 0, L_0x2bcd0d0; 1 drivers +v0x2bc17b0_0 .net "AandB", 0 0, L_0x2bcca10; 1 drivers +v0x2bc1850_0 .net "AddSubSLTSum", 0 0, L_0x2bcc920; 1 drivers +v0x2bc18f0_0 .net "AxorB", 0 0, L_0x2bcc830; 1 drivers +v0x2bc1970_0 .net "B", 0 0, L_0x2bccfd0; 1 drivers +v0x2bc1a20_0 .net "BornB", 0 0, L_0x2bcc280; 1 drivers +v0x2bc1ae0_0 .net "CINandAxorB", 0 0, L_0x2bccb80; 1 drivers +v0x2bc1b60_0 .alias "Command", 2 0, v0x2bc67a0_0; +v0x2bc1be0_0 .net *"_s3", 0 0, L_0x2bcc5b0; 1 drivers +v0x2bc1c60_0 .net *"_s5", 0 0, L_0x2bcc790; 1 drivers +v0x2bc1d00_0 .net "carryin", 0 0, L_0x2bcd2c0; 1 drivers +v0x2bc1da0_0 .net "carryout", 0 0, L_0x2bccc90; 1 drivers +v0x2bc1e40_0 .net "nB", 0 0, L_0x2bcbc20; 1 drivers +v0x2bc1ef0_0 .net "nCmd2", 0 0, L_0x2bcc4f0; 1 drivers +v0x2bc1ff0_0 .net "subtract", 0 0, L_0x2bcc650; 1 drivers +L_0x2bcc450 .part v0x2bc78e0_0, 0, 1; +L_0x2bcc5b0 .part v0x2bc78e0_0, 2, 1; +L_0x2bcc790 .part v0x2bc78e0_0, 0, 1; +S_0x2bc1150 .scope module, "mux0" "TwoInMux" 3 105, 3 8, S_0x2bc1060; + .timescale -9 -12; +L_0x2bcbfc0/d .functor NOT 1, L_0x2bcc450, C4<0>, C4<0>, C4<0>; +L_0x2bcbfc0 .delay (10000,10000,10000) L_0x2bcbfc0/d; +L_0x2bcc060/d .functor AND 1, L_0x2bccfd0, L_0x2bcbfc0, C4<1>, C4<1>; +L_0x2bcc060 .delay (20000,20000,20000) L_0x2bcc060/d; +L_0x2bcc170/d .functor AND 1, L_0x2bcbc20, L_0x2bcc450, C4<1>, C4<1>; +L_0x2bcc170 .delay (20000,20000,20000) L_0x2bcc170/d; +L_0x2bcc280/d .functor OR 1, L_0x2bcc060, L_0x2bcc170, C4<0>, C4<0>; +L_0x2bcc280 .delay (20000,20000,20000) L_0x2bcc280/d; +v0x2bc1240_0 .net "S", 0 0, L_0x2bcc450; 1 drivers +v0x2bc12e0_0 .alias "in0", 0 0, v0x2bc1970_0; +v0x2bc1380_0 .alias "in1", 0 0, v0x2bc1e40_0; +v0x2bc1420_0 .net "nS", 0 0, L_0x2bcbfc0; 1 drivers +v0x2bc14d0_0 .net "out0", 0 0, L_0x2bcc060; 1 drivers +v0x2bc1570_0 .net "out1", 0 0, L_0x2bcc170; 1 drivers +v0x2bc1650_0 .alias "outfinal", 0 0, v0x2bc1a20_0; +S_0x2bbfd50 .scope generate, "addbits[5]" "addbits[5]" 3 230, 3 230, S_0x2ba3100; + .timescale -9 -12; +P_0x2bbf768 .param/l "i" 3 230, +C4<0101>; +S_0x2bbfec0 .scope module, "attempt" "MiddleAddSubSLT" 3 232, 3 89, S_0x2bbfd50; + .timescale -9 -12; +L_0x2bca9e0/d .functor NOT 1, L_0x2bce630, C4<0>, C4<0>, C4<0>; +L_0x2bca9e0 .delay (10000,10000,10000) L_0x2bca9e0/d; +L_0x2bcdab0/d .functor NOT 1, L_0x2bcdb70, C4<0>, C4<0>, C4<0>; +L_0x2bcdab0 .delay (10000,10000,10000) L_0x2bcdab0/d; +L_0x2bcdc10/d .functor AND 1, L_0x2bcdd50, L_0x2bcdab0, C4<1>, C4<1>; +L_0x2bcdc10 .delay (20000,20000,20000) L_0x2bcdc10/d; +L_0x2bcddf0/d .functor XOR 1, L_0x2bce820, L_0x2bcd840, C4<0>, C4<0>; +L_0x2bcddf0 .delay (40000,40000,40000) L_0x2bcddf0/d; +L_0x2bcdee0/d .functor XOR 1, L_0x2bcddf0, L_0x2bcea40, C4<0>, C4<0>; +L_0x2bcdee0 .delay (40000,40000,40000) L_0x2bcdee0/d; +L_0x2bcdfd0/d .functor AND 1, L_0x2bce820, L_0x2bcd840, C4<1>, C4<1>; +L_0x2bcdfd0 .delay (20000,20000,20000) L_0x2bcdfd0/d; +L_0x2bce140/d .functor AND 1, L_0x2bcddf0, L_0x2bcea40, C4<1>, C4<1>; +L_0x2bce140 .delay (20000,20000,20000) L_0x2bce140/d; +L_0x2bce230/d .functor OR 1, L_0x2bcdfd0, L_0x2bce140, C4<0>, C4<0>; +L_0x2bce230 .delay (20000,20000,20000) L_0x2bce230/d; +v0x2bc0550_0 .net "A", 0 0, L_0x2bce820; 1 drivers +v0x2bc0610_0 .net "AandB", 0 0, L_0x2bcdfd0; 1 drivers +v0x2bc06b0_0 .net "AddSubSLTSum", 0 0, L_0x2bcdee0; 1 drivers +v0x2bc0750_0 .net "AxorB", 0 0, L_0x2bcddf0; 1 drivers +v0x2bc07d0_0 .net "B", 0 0, L_0x2bce630; 1 drivers +v0x2bc0880_0 .net "BornB", 0 0, L_0x2bcd840; 1 drivers +v0x2bc0940_0 .net "CINandAxorB", 0 0, L_0x2bce140; 1 drivers +v0x2bc09c0_0 .alias "Command", 2 0, v0x2bc67a0_0; +v0x2bc0a40_0 .net *"_s3", 0 0, L_0x2bcdb70; 1 drivers +v0x2bc0ac0_0 .net *"_s5", 0 0, L_0x2bcdd50; 1 drivers +v0x2bc0b60_0 .net "carryin", 0 0, L_0x2bcea40; 1 drivers +v0x2bc0c00_0 .net "carryout", 0 0, L_0x2bce230; 1 drivers +v0x2bc0ca0_0 .net "nB", 0 0, L_0x2bca9e0; 1 drivers +v0x2bc0d50_0 .net "nCmd2", 0 0, L_0x2bcdab0; 1 drivers +v0x2bc0e50_0 .net "subtract", 0 0, L_0x2bcdc10; 1 drivers +L_0x2bcda10 .part v0x2bc78e0_0, 0, 1; +L_0x2bcdb70 .part v0x2bc78e0_0, 2, 1; +L_0x2bcdd50 .part v0x2bc78e0_0, 0, 1; +S_0x2bbffb0 .scope module, "mux0" "TwoInMux" 3 105, 3 8, S_0x2bbfec0; + .timescale -9 -12; +L_0x2bcd560/d .functor NOT 1, L_0x2bcda10, C4<0>, C4<0>, C4<0>; +L_0x2bcd560 .delay (10000,10000,10000) L_0x2bcd560/d; +L_0x2bcd620/d .functor AND 1, L_0x2bce630, L_0x2bcd560, C4<1>, C4<1>; +L_0x2bcd620 .delay (20000,20000,20000) L_0x2bcd620/d; +L_0x2bcd730/d .functor AND 1, L_0x2bca9e0, L_0x2bcda10, C4<1>, C4<1>; +L_0x2bcd730 .delay (20000,20000,20000) L_0x2bcd730/d; +L_0x2bcd840/d .functor OR 1, L_0x2bcd620, L_0x2bcd730, C4<0>, C4<0>; +L_0x2bcd840 .delay (20000,20000,20000) L_0x2bcd840/d; +v0x2bc00a0_0 .net "S", 0 0, L_0x2bcda10; 1 drivers +v0x2bc0140_0 .alias "in0", 0 0, v0x2bc07d0_0; +v0x2bc01e0_0 .alias "in1", 0 0, v0x2bc0ca0_0; +v0x2bc0280_0 .net "nS", 0 0, L_0x2bcd560; 1 drivers +v0x2bc0330_0 .net "out0", 0 0, L_0x2bcd620; 1 drivers +v0x2bc03d0_0 .net "out1", 0 0, L_0x2bcd730; 1 drivers +v0x2bc04b0_0 .alias "outfinal", 0 0, v0x2bc0880_0; +S_0x2bbebb0 .scope generate, "addbits[6]" "addbits[6]" 3 230, 3 230, S_0x2ba3100; + .timescale -9 -12; +P_0x2bbe5c8 .param/l "i" 3 230, +C4<0110>; +S_0x2bbed20 .scope module, "attempt" "MiddleAddSubSLT" 3 232, 3 89, S_0x2bbebb0; + .timescale -9 -12; +L_0x2bce8c0/d .functor NOT 1, L_0x2bcfba0, C4<0>, C4<0>, C4<0>; +L_0x2bce8c0 .delay (10000,10000,10000) L_0x2bce8c0/d; +L_0x2bcf0c0/d .functor NOT 1, L_0x2bcf180, C4<0>, C4<0>, C4<0>; +L_0x2bcf0c0 .delay (10000,10000,10000) L_0x2bcf0c0/d; +L_0x2bcf220/d .functor AND 1, L_0x2bcf360, L_0x2bcf0c0, C4<1>, C4<1>; +L_0x2bcf220 .delay (20000,20000,20000) L_0x2bcf220/d; +L_0x2bcf400/d .functor XOR 1, L_0x2bcfcb0, L_0x2bcee50, C4<0>, C4<0>; +L_0x2bcf400 .delay (40000,40000,40000) L_0x2bcf400/d; +L_0x2bcf4f0/d .functor XOR 1, L_0x2bcf400, L_0x2bcff00, C4<0>, C4<0>; +L_0x2bcf4f0 .delay (40000,40000,40000) L_0x2bcf4f0/d; +L_0x2bcf5e0/d .functor AND 1, L_0x2bcfcb0, L_0x2bcee50, C4<1>, C4<1>; +L_0x2bcf5e0 .delay (20000,20000,20000) L_0x2bcf5e0/d; +L_0x2bcf750/d .functor AND 1, L_0x2bcf400, L_0x2bcff00, C4<1>, C4<1>; +L_0x2bcf750 .delay (20000,20000,20000) L_0x2bcf750/d; +L_0x2bcf860/d .functor OR 1, L_0x2bcf5e0, L_0x2bcf750, C4<0>, C4<0>; +L_0x2bcf860 .delay (20000,20000,20000) L_0x2bcf860/d; +v0x2bbf3b0_0 .net "A", 0 0, L_0x2bcfcb0; 1 drivers +v0x2bbf470_0 .net "AandB", 0 0, L_0x2bcf5e0; 1 drivers +v0x2bbf510_0 .net "AddSubSLTSum", 0 0, L_0x2bcf4f0; 1 drivers +v0x2bbf5b0_0 .net "AxorB", 0 0, L_0x2bcf400; 1 drivers +v0x2bbf630_0 .net "B", 0 0, L_0x2bcfba0; 1 drivers +v0x2bbf6e0_0 .net "BornB", 0 0, L_0x2bcee50; 1 drivers +v0x2bbf7a0_0 .net "CINandAxorB", 0 0, L_0x2bcf750; 1 drivers +v0x2bbf820_0 .alias "Command", 2 0, v0x2bc67a0_0; +v0x2bbf8a0_0 .net *"_s3", 0 0, L_0x2bcf180; 1 drivers +v0x2bbf920_0 .net *"_s5", 0 0, L_0x2bcf360; 1 drivers +v0x2bbf9c0_0 .net "carryin", 0 0, L_0x2bcff00; 1 drivers +v0x2bbfa60_0 .net "carryout", 0 0, L_0x2bcf860; 1 drivers +v0x2bbfb00_0 .net "nB", 0 0, L_0x2bce8c0; 1 drivers +v0x2bbfbb0_0 .net "nCmd2", 0 0, L_0x2bcf0c0; 1 drivers +v0x2bbfcb0_0 .net "subtract", 0 0, L_0x2bcf220; 1 drivers +L_0x2bcf020 .part v0x2bc78e0_0, 0, 1; +L_0x2bcf180 .part v0x2bc78e0_0, 2, 1; +L_0x2bcf360 .part v0x2bc78e0_0, 0, 1; +S_0x2bbee10 .scope module, "mux0" "TwoInMux" 3 105, 3 8, S_0x2bbed20; + .timescale -9 -12; +L_0x2bcec30/d .functor NOT 1, L_0x2bcf020, C4<0>, C4<0>, C4<0>; +L_0x2bcec30 .delay (10000,10000,10000) L_0x2bcec30/d; +L_0x2bcec90/d .functor AND 1, L_0x2bcfba0, L_0x2bcec30, C4<1>, C4<1>; +L_0x2bcec90 .delay (20000,20000,20000) L_0x2bcec90/d; +L_0x2bced40/d .functor AND 1, L_0x2bce8c0, L_0x2bcf020, C4<1>, C4<1>; +L_0x2bced40 .delay (20000,20000,20000) L_0x2bced40/d; +L_0x2bcee50/d .functor OR 1, L_0x2bcec90, L_0x2bced40, C4<0>, C4<0>; +L_0x2bcee50 .delay (20000,20000,20000) L_0x2bcee50/d; +v0x2bbef00_0 .net "S", 0 0, L_0x2bcf020; 1 drivers +v0x2bbefa0_0 .alias "in0", 0 0, v0x2bbf630_0; +v0x2bbf040_0 .alias "in1", 0 0, v0x2bbfb00_0; +v0x2bbf0e0_0 .net "nS", 0 0, L_0x2bcec30; 1 drivers +v0x2bbf190_0 .net "out0", 0 0, L_0x2bcec90; 1 drivers +v0x2bbf230_0 .net "out1", 0 0, L_0x2bced40; 1 drivers +v0x2bbf310_0 .alias "outfinal", 0 0, v0x2bbf6e0_0; +S_0x2bbda10 .scope generate, "addbits[7]" "addbits[7]" 3 230, 3 230, S_0x2ba3100; + .timescale -9 -12; +P_0x2bbd428 .param/l "i" 3 230, +C4<0111>; +S_0x2bbdb80 .scope module, "attempt" "MiddleAddSubSLT" 3 232, 3 89, S_0x2bbda10; + .timescale -9 -12; +L_0x2bcfc40/d .functor NOT 1, L_0x2bd10c0, C4<0>, C4<0>, C4<0>; +L_0x2bcfc40 .delay (10000,10000,10000) L_0x2bcfc40/d; +L_0x2bd0600/d .functor NOT 1, L_0x2bd06c0, C4<0>, C4<0>, C4<0>; +L_0x2bd0600 .delay (10000,10000,10000) L_0x2bd0600/d; +L_0x2bd0760/d .functor AND 1, L_0x2bd08a0, L_0x2bd0600, C4<1>, C4<1>; +L_0x2bd0760 .delay (20000,20000,20000) L_0x2bd0760/d; +L_0x2bd0940/d .functor XOR 1, L_0x2bd1200, L_0x2bd0390, C4<0>, C4<0>; +L_0x2bd0940 .delay (40000,40000,40000) L_0x2bd0940/d; +L_0x2bd0a30/d .functor XOR 1, L_0x2bd0940, L_0x2bd13f0, C4<0>, C4<0>; +L_0x2bd0a30 .delay (40000,40000,40000) L_0x2bd0a30/d; +L_0x2bd0b20/d .functor AND 1, L_0x2bd1200, L_0x2bd0390, C4<1>, C4<1>; +L_0x2bd0b20 .delay (20000,20000,20000) L_0x2bd0b20/d; +L_0x2bd0c90/d .functor AND 1, L_0x2bd0940, L_0x2bd13f0, C4<1>, C4<1>; +L_0x2bd0c90 .delay (20000,20000,20000) L_0x2bd0c90/d; +L_0x2bd0d80/d .functor OR 1, L_0x2bd0b20, L_0x2bd0c90, C4<0>, C4<0>; +L_0x2bd0d80 .delay (20000,20000,20000) L_0x2bd0d80/d; +v0x2bbe210_0 .net "A", 0 0, L_0x2bd1200; 1 drivers +v0x2bbe2d0_0 .net "AandB", 0 0, L_0x2bd0b20; 1 drivers +v0x2bbe370_0 .net "AddSubSLTSum", 0 0, L_0x2bd0a30; 1 drivers +v0x2bbe410_0 .net "AxorB", 0 0, L_0x2bd0940; 1 drivers +v0x2bbe490_0 .net "B", 0 0, L_0x2bd10c0; 1 drivers +v0x2bbe540_0 .net "BornB", 0 0, L_0x2bd0390; 1 drivers +v0x2bbe600_0 .net "CINandAxorB", 0 0, L_0x2bd0c90; 1 drivers +v0x2bbe680_0 .alias "Command", 2 0, v0x2bc67a0_0; +v0x2bbe700_0 .net *"_s3", 0 0, L_0x2bd06c0; 1 drivers +v0x2bbe780_0 .net *"_s5", 0 0, L_0x2bd08a0; 1 drivers +v0x2bbe820_0 .net "carryin", 0 0, L_0x2bd13f0; 1 drivers +v0x2bbe8c0_0 .net "carryout", 0 0, L_0x2bd0d80; 1 drivers +v0x2bbe960_0 .net "nB", 0 0, L_0x2bcfc40; 1 drivers +v0x2bbea10_0 .net "nCmd2", 0 0, L_0x2bd0600; 1 drivers +v0x2bbeb10_0 .net "subtract", 0 0, L_0x2bd0760; 1 drivers +L_0x2bd0560 .part v0x2bc78e0_0, 0, 1; +L_0x2bd06c0 .part v0x2bc78e0_0, 2, 1; +L_0x2bd08a0 .part v0x2bc78e0_0, 0, 1; +S_0x2bbdc70 .scope module, "mux0" "TwoInMux" 3 105, 3 8, S_0x2bbdb80; + .timescale -9 -12; +L_0x2bd00d0/d .functor NOT 1, L_0x2bd0560, C4<0>, C4<0>, C4<0>; +L_0x2bd00d0 .delay (10000,10000,10000) L_0x2bd00d0/d; +L_0x2bd0170/d .functor AND 1, L_0x2bd10c0, L_0x2bd00d0, C4<1>, C4<1>; +L_0x2bd0170 .delay (20000,20000,20000) L_0x2bd0170/d; +L_0x2bd0280/d .functor AND 1, L_0x2bcfc40, L_0x2bd0560, C4<1>, C4<1>; +L_0x2bd0280 .delay (20000,20000,20000) L_0x2bd0280/d; +L_0x2bd0390/d .functor OR 1, L_0x2bd0170, L_0x2bd0280, C4<0>, C4<0>; +L_0x2bd0390 .delay (20000,20000,20000) L_0x2bd0390/d; +v0x2bbdd60_0 .net "S", 0 0, L_0x2bd0560; 1 drivers +v0x2bbde00_0 .alias "in0", 0 0, v0x2bbe490_0; +v0x2bbdea0_0 .alias "in1", 0 0, v0x2bbe960_0; +v0x2bbdf40_0 .net "nS", 0 0, L_0x2bd00d0; 1 drivers +v0x2bbdff0_0 .net "out0", 0 0, L_0x2bd0170; 1 drivers +v0x2bbe090_0 .net "out1", 0 0, L_0x2bd0280; 1 drivers +v0x2bbe170_0 .alias "outfinal", 0 0, v0x2bbe540_0; +S_0x2bbc870 .scope generate, "addbits[8]" "addbits[8]" 3 230, 3 230, S_0x2ba3100; + .timescale -9 -12; +P_0x2bbc288 .param/l "i" 3 230, +C4<01000>; +S_0x2bbc9e0 .scope module, "attempt" "MiddleAddSubSLT" 3 232, 3 89, S_0x2bbc870; + .timescale -9 -12; +L_0x2bd12a0/d .functor NOT 1, L_0x2bd25e0, C4<0>, C4<0>, C4<0>; +L_0x2bd12a0 .delay (10000,10000,10000) L_0x2bd12a0/d; +L_0x2bd1b20/d .functor NOT 1, L_0x2bd1be0, C4<0>, C4<0>, C4<0>; +L_0x2bd1b20 .delay (10000,10000,10000) L_0x2bd1b20/d; +L_0x2bd1c80/d .functor AND 1, L_0x2bd1dc0, L_0x2bd1b20, C4<1>, C4<1>; +L_0x2bd1c80 .delay (20000,20000,20000) L_0x2bd1c80/d; +L_0x2bd1e60/d .functor XOR 1, L_0x2bd2750, L_0x2bd18b0, C4<0>, C4<0>; +L_0x2bd1e60 .delay (40000,40000,40000) L_0x2bd1e60/d; +L_0x2bd1f50/d .functor XOR 1, L_0x2bd1e60, L_0x2bd2970, C4<0>, C4<0>; +L_0x2bd1f50 .delay (40000,40000,40000) L_0x2bd1f50/d; +L_0x2bd2040/d .functor AND 1, L_0x2bd2750, L_0x2bd18b0, C4<1>, C4<1>; +L_0x2bd2040 .delay (20000,20000,20000) L_0x2bd2040/d; +L_0x2bd21b0/d .functor AND 1, L_0x2bd1e60, L_0x2bd2970, C4<1>, C4<1>; +L_0x2bd21b0 .delay (20000,20000,20000) L_0x2bd21b0/d; +L_0x2bd22a0/d .functor OR 1, L_0x2bd2040, L_0x2bd21b0, C4<0>, C4<0>; +L_0x2bd22a0 .delay (20000,20000,20000) L_0x2bd22a0/d; +v0x2bbd070_0 .net "A", 0 0, L_0x2bd2750; 1 drivers +v0x2bbd130_0 .net "AandB", 0 0, L_0x2bd2040; 1 drivers +v0x2bbd1d0_0 .net "AddSubSLTSum", 0 0, L_0x2bd1f50; 1 drivers +v0x2bbd270_0 .net "AxorB", 0 0, L_0x2bd1e60; 1 drivers +v0x2bbd2f0_0 .net "B", 0 0, L_0x2bd25e0; 1 drivers +v0x2bbd3a0_0 .net "BornB", 0 0, L_0x2bd18b0; 1 drivers +v0x2bbd460_0 .net "CINandAxorB", 0 0, L_0x2bd21b0; 1 drivers +v0x2bbd4e0_0 .alias "Command", 2 0, v0x2bc67a0_0; +v0x2bbd560_0 .net *"_s3", 0 0, L_0x2bd1be0; 1 drivers +v0x2bbd5e0_0 .net *"_s5", 0 0, L_0x2bd1dc0; 1 drivers +v0x2bbd680_0 .net "carryin", 0 0, L_0x2bd2970; 1 drivers +v0x2bbd720_0 .net "carryout", 0 0, L_0x2bd22a0; 1 drivers +v0x2bbd7c0_0 .net "nB", 0 0, L_0x2bd12a0; 1 drivers +v0x2bbd870_0 .net "nCmd2", 0 0, L_0x2bd1b20; 1 drivers +v0x2bbd970_0 .net "subtract", 0 0, L_0x2bd1c80; 1 drivers +L_0x2bd1a80 .part v0x2bc78e0_0, 0, 1; +L_0x2bd1be0 .part v0x2bc78e0_0, 2, 1; +L_0x2bd1dc0 .part v0x2bc78e0_0, 0, 1; +S_0x2bbcad0 .scope module, "mux0" "TwoInMux" 3 105, 3 8, S_0x2bbc9e0; + .timescale -9 -12; +L_0x2bd15f0/d .functor NOT 1, L_0x2bd1a80, C4<0>, C4<0>, C4<0>; +L_0x2bd15f0 .delay (10000,10000,10000) L_0x2bd15f0/d; +L_0x2bd1690/d .functor AND 1, L_0x2bd25e0, L_0x2bd15f0, C4<1>, C4<1>; +L_0x2bd1690 .delay (20000,20000,20000) L_0x2bd1690/d; +L_0x2bd17a0/d .functor AND 1, L_0x2bd12a0, L_0x2bd1a80, C4<1>, C4<1>; +L_0x2bd17a0 .delay (20000,20000,20000) L_0x2bd17a0/d; +L_0x2bd18b0/d .functor OR 1, L_0x2bd1690, L_0x2bd17a0, C4<0>, C4<0>; +L_0x2bd18b0 .delay (20000,20000,20000) L_0x2bd18b0/d; +v0x2bbcbc0_0 .net "S", 0 0, L_0x2bd1a80; 1 drivers +v0x2bbcc60_0 .alias "in0", 0 0, v0x2bbd2f0_0; +v0x2bbcd00_0 .alias "in1", 0 0, v0x2bbd7c0_0; +v0x2bbcda0_0 .net "nS", 0 0, L_0x2bd15f0; 1 drivers +v0x2bbce50_0 .net "out0", 0 0, L_0x2bd1690; 1 drivers +v0x2bbcef0_0 .net "out1", 0 0, L_0x2bd17a0; 1 drivers +v0x2bbcfd0_0 .alias "outfinal", 0 0, v0x2bbd3a0_0; +S_0x2bbb6d0 .scope generate, "addbits[9]" "addbits[9]" 3 230, 3 230, S_0x2ba3100; + .timescale -9 -12; +P_0x2bbb0e8 .param/l "i" 3 230, +C4<01001>; +S_0x2bbb840 .scope module, "attempt" "MiddleAddSubSLT" 3 232, 3 89, S_0x2bbb6d0; + .timescale -9 -12; +L_0x2bd1580/d .functor NOT 1, L_0x2bc9110, C4<0>, C4<0>, C4<0>; +L_0x2bd1580 .delay (10000,10000,10000) L_0x2bd1580/d; +L_0x2bd3130/d .functor NOT 1, L_0x2bd31f0, C4<0>, C4<0>, C4<0>; +L_0x2bd3130 .delay (10000,10000,10000) L_0x2bd3130/d; +L_0x2bd3290/d .functor AND 1, L_0x2bd33d0, L_0x2bd3130, C4<1>, C4<1>; +L_0x2bd3290 .delay (20000,20000,20000) L_0x2bd3290/d; +L_0x2bd3470/d .functor XOR 1, L_0x2bd2d10, L_0x2bd2ec0, C4<0>, C4<0>; +L_0x2bd3470 .delay (40000,40000,40000) L_0x2bd3470/d; +L_0x2bd3560/d .functor XOR 1, L_0x2bd3470, L_0x2bd3c80, C4<0>, C4<0>; +L_0x2bd3560 .delay (40000,40000,40000) L_0x2bd3560/d; +L_0x2bd3650/d .functor AND 1, L_0x2bd2d10, L_0x2bd2ec0, C4<1>, C4<1>; +L_0x2bd3650 .delay (20000,20000,20000) L_0x2bd3650/d; +L_0x2bd37c0/d .functor AND 1, L_0x2bd3470, L_0x2bd3c80, C4<1>, C4<1>; +L_0x2bd37c0 .delay (20000,20000,20000) L_0x2bd37c0/d; +L_0x2bd38b0/d .functor OR 1, L_0x2bd3650, L_0x2bd37c0, C4<0>, C4<0>; +L_0x2bd38b0 .delay (20000,20000,20000) L_0x2bd38b0/d; +v0x2bbbed0_0 .net "A", 0 0, L_0x2bd2d10; 1 drivers +v0x2bbbf90_0 .net "AandB", 0 0, L_0x2bd3650; 1 drivers +v0x2bbc030_0 .net "AddSubSLTSum", 0 0, L_0x2bd3560; 1 drivers +v0x2bbc0d0_0 .net "AxorB", 0 0, L_0x2bd3470; 1 drivers +v0x2bbc150_0 .net "B", 0 0, L_0x2bc9110; 1 drivers +v0x2bbc200_0 .net "BornB", 0 0, L_0x2bd2ec0; 1 drivers +v0x2bbc2c0_0 .net "CINandAxorB", 0 0, L_0x2bd37c0; 1 drivers +v0x2bbc340_0 .alias "Command", 2 0, v0x2bc67a0_0; +v0x2bbc3c0_0 .net *"_s3", 0 0, L_0x2bd31f0; 1 drivers +v0x2bbc440_0 .net *"_s5", 0 0, L_0x2bd33d0; 1 drivers +v0x2bbc4e0_0 .net "carryin", 0 0, L_0x2bd3c80; 1 drivers +v0x2bbc580_0 .net "carryout", 0 0, L_0x2bd38b0; 1 drivers +v0x2bbc620_0 .net "nB", 0 0, L_0x2bd1580; 1 drivers +v0x2bbc6d0_0 .net "nCmd2", 0 0, L_0x2bd3130; 1 drivers +v0x2bbc7d0_0 .net "subtract", 0 0, L_0x2bd3290; 1 drivers +L_0x2bd3090 .part v0x2bc78e0_0, 0, 1; +L_0x2bd31f0 .part v0x2bc78e0_0, 2, 1; +L_0x2bd33d0 .part v0x2bc78e0_0, 0, 1; +S_0x2bbb930 .scope module, "mux0" "TwoInMux" 3 105, 3 8, S_0x2bbb840; + .timescale -9 -12; +L_0x2bd27f0/d .functor NOT 1, L_0x2bd3090, C4<0>, C4<0>, C4<0>; +L_0x2bd27f0 .delay (10000,10000,10000) L_0x2bd27f0/d; +L_0x2bd28b0/d .functor AND 1, L_0x2bc9110, L_0x2bd27f0, C4<1>, C4<1>; +L_0x2bd28b0 .delay (20000,20000,20000) L_0x2bd28b0/d; +L_0x2bd2db0/d .functor AND 1, L_0x2bd1580, L_0x2bd3090, C4<1>, C4<1>; +L_0x2bd2db0 .delay (20000,20000,20000) L_0x2bd2db0/d; +L_0x2bd2ec0/d .functor OR 1, L_0x2bd28b0, L_0x2bd2db0, C4<0>, C4<0>; +L_0x2bd2ec0 .delay (20000,20000,20000) L_0x2bd2ec0/d; +v0x2bbba20_0 .net "S", 0 0, L_0x2bd3090; 1 drivers +v0x2bbbac0_0 .alias "in0", 0 0, v0x2bbc150_0; +v0x2bbbb60_0 .alias "in1", 0 0, v0x2bbc620_0; +v0x2bbbc00_0 .net "nS", 0 0, L_0x2bd27f0; 1 drivers +v0x2bbbcb0_0 .net "out0", 0 0, L_0x2bd28b0; 1 drivers +v0x2bbbd50_0 .net "out1", 0 0, L_0x2bd2db0; 1 drivers +v0x2bbbe30_0 .alias "outfinal", 0 0, v0x2bbc200_0; +S_0x2bba530 .scope generate, "addbits[10]" "addbits[10]" 3 230, 3 230, S_0x2ba3100; + .timescale -9 -12; +P_0x2bb9f48 .param/l "i" 3 230, +C4<01010>; +S_0x2bba6a0 .scope module, "attempt" "MiddleAddSubSLT" 3 232, 3 89, S_0x2bba530; + .timescale -9 -12; +L_0x2bc91b0/d .functor NOT 1, L_0x2bd54e0, C4<0>, C4<0>, C4<0>; +L_0x2bc91b0 .delay (10000,10000,10000) L_0x2bc91b0/d; +L_0x2bd4840/d .functor NOT 1, L_0x2bd4900, C4<0>, C4<0>, C4<0>; +L_0x2bd4840 .delay (10000,10000,10000) L_0x2bd4840/d; +L_0x2bd49a0/d .functor AND 1, L_0x2bd4ae0, L_0x2bd4840, C4<1>, C4<1>; +L_0x2bd49a0 .delay (20000,20000,20000) L_0x2bd49a0/d; +L_0x2bd4b80/d .functor XOR 1, L_0x2bd4450, L_0x2bd45d0, C4<0>, C4<0>; +L_0x2bd4b80 .delay (40000,40000,40000) L_0x2bd4b80/d; +L_0x2bd4c70/d .functor XOR 1, L_0x2bd4b80, L_0x2bd5610, C4<0>, C4<0>; +L_0x2bd4c70 .delay (40000,40000,40000) L_0x2bd4c70/d; +L_0x2bd4d60/d .functor AND 1, L_0x2bd4450, L_0x2bd45d0, C4<1>, C4<1>; +L_0x2bd4d60 .delay (20000,20000,20000) L_0x2bd4d60/d; +L_0x2bd4ed0/d .functor AND 1, L_0x2bd4b80, L_0x2bd5610, C4<1>, C4<1>; +L_0x2bd4ed0 .delay (20000,20000,20000) L_0x2bd4ed0/d; +L_0x2bd4fc0/d .functor OR 1, L_0x2bd4d60, L_0x2bd4ed0, C4<0>, C4<0>; +L_0x2bd4fc0 .delay (20000,20000,20000) L_0x2bd4fc0/d; +v0x2bbad30_0 .net "A", 0 0, L_0x2bd4450; 1 drivers +v0x2bbadf0_0 .net "AandB", 0 0, L_0x2bd4d60; 1 drivers +v0x2bbae90_0 .net "AddSubSLTSum", 0 0, L_0x2bd4c70; 1 drivers +v0x2bbaf30_0 .net "AxorB", 0 0, L_0x2bd4b80; 1 drivers +v0x2bbafb0_0 .net "B", 0 0, L_0x2bd54e0; 1 drivers +v0x2bbb060_0 .net "BornB", 0 0, L_0x2bd45d0; 1 drivers +v0x2bbb120_0 .net "CINandAxorB", 0 0, L_0x2bd4ed0; 1 drivers +v0x2bbb1a0_0 .alias "Command", 2 0, v0x2bc67a0_0; +v0x2bbb220_0 .net *"_s3", 0 0, L_0x2bd4900; 1 drivers +v0x2bbb2a0_0 .net *"_s5", 0 0, L_0x2bd4ae0; 1 drivers +v0x2bbb340_0 .net "carryin", 0 0, L_0x2bd5610; 1 drivers +v0x2bbb3e0_0 .net "carryout", 0 0, L_0x2bd4fc0; 1 drivers +v0x2bbb480_0 .net "nB", 0 0, L_0x2bc91b0; 1 drivers +v0x2bbb530_0 .net "nCmd2", 0 0, L_0x2bd4840; 1 drivers +v0x2bbb630_0 .net "subtract", 0 0, L_0x2bd49a0; 1 drivers +L_0x2bd47a0 .part v0x2bc78e0_0, 0, 1; +L_0x2bd4900 .part v0x2bc78e0_0, 2, 1; +L_0x2bd4ae0 .part v0x2bc78e0_0, 0, 1; +S_0x2bba790 .scope module, "mux0" "TwoInMux" 3 105, 3 8, S_0x2bba6a0; + .timescale -9 -12; +L_0x2bc9350/d .functor NOT 1, L_0x2bd47a0, C4<0>, C4<0>, C4<0>; +L_0x2bc9350 .delay (10000,10000,10000) L_0x2bc9350/d; +L_0x2bd3fe0/d .functor AND 1, L_0x2bd54e0, L_0x2bc9350, C4<1>, C4<1>; +L_0x2bd3fe0 .delay (20000,20000,20000) L_0x2bd3fe0/d; +L_0x2bd40f0/d .functor AND 1, L_0x2bc91b0, L_0x2bd47a0, C4<1>, C4<1>; +L_0x2bd40f0 .delay (20000,20000,20000) L_0x2bd40f0/d; +L_0x2bd45d0/d .functor OR 1, L_0x2bd3fe0, L_0x2bd40f0, C4<0>, C4<0>; +L_0x2bd45d0 .delay (20000,20000,20000) L_0x2bd45d0/d; +v0x2bba880_0 .net "S", 0 0, L_0x2bd47a0; 1 drivers +v0x2bba920_0 .alias "in0", 0 0, v0x2bbafb0_0; +v0x2bba9c0_0 .alias "in1", 0 0, v0x2bbb480_0; +v0x2bbaa60_0 .net "nS", 0 0, L_0x2bc9350; 1 drivers +v0x2bbab10_0 .net "out0", 0 0, L_0x2bd3fe0; 1 drivers +v0x2bbabb0_0 .net "out1", 0 0, L_0x2bd40f0; 1 drivers +v0x2bbac90_0 .alias "outfinal", 0 0, v0x2bbb060_0; +S_0x2bb9390 .scope generate, "addbits[11]" "addbits[11]" 3 230, 3 230, S_0x2ba3100; + .timescale -9 -12; +P_0x2bb8da8 .param/l "i" 3 230, +C4<01011>; +S_0x2bb9500 .scope module, "attempt" "MiddleAddSubSLT" 3 232, 3 89, S_0x2bb9390; + .timescale -9 -12; +L_0x2bd5300/d .functor NOT 1, L_0x2bd6a20, C4<0>, C4<0>, C4<0>; +L_0x2bd5300 .delay (10000,10000,10000) L_0x2bd5300/d; +L_0x2bd5d50/d .functor NOT 1, L_0x2bd5e10, C4<0>, C4<0>, C4<0>; +L_0x2bd5d50 .delay (10000,10000,10000) L_0x2bd5d50/d; +L_0x2bd5eb0/d .functor AND 1, L_0x2bd5ff0, L_0x2bd5d50, C4<1>, C4<1>; +L_0x2bd5eb0 .delay (20000,20000,20000) L_0x2bd5eb0/d; +L_0x2bd6090/d .functor XOR 1, L_0x2bd57a0, L_0x2bd5ae0, C4<0>, C4<0>; +L_0x2bd6090 .delay (40000,40000,40000) L_0x2bd6090/d; +L_0x2bd6180/d .functor XOR 1, L_0x2bd6090, L_0x2bd6b50, C4<0>, C4<0>; +L_0x2bd6180 .delay (40000,40000,40000) L_0x2bd6180/d; +L_0x2bd6270/d .functor AND 1, L_0x2bd57a0, L_0x2bd5ae0, C4<1>, C4<1>; +L_0x2bd6270 .delay (20000,20000,20000) L_0x2bd6270/d; +L_0x2bd63e0/d .functor AND 1, L_0x2bd6090, L_0x2bd6b50, C4<1>, C4<1>; +L_0x2bd63e0 .delay (20000,20000,20000) L_0x2bd63e0/d; +L_0x2bd64d0/d .functor OR 1, L_0x2bd6270, L_0x2bd63e0, C4<0>, C4<0>; +L_0x2bd64d0 .delay (20000,20000,20000) L_0x2bd64d0/d; +v0x2bb9b90_0 .net "A", 0 0, L_0x2bd57a0; 1 drivers +v0x2bb9c50_0 .net "AandB", 0 0, L_0x2bd6270; 1 drivers +v0x2bb9cf0_0 .net "AddSubSLTSum", 0 0, L_0x2bd6180; 1 drivers +v0x2bb9d90_0 .net "AxorB", 0 0, L_0x2bd6090; 1 drivers +v0x2bb9e10_0 .net "B", 0 0, L_0x2bd6a20; 1 drivers +v0x2bb9ec0_0 .net "BornB", 0 0, L_0x2bd5ae0; 1 drivers +v0x2bb9f80_0 .net "CINandAxorB", 0 0, L_0x2bd63e0; 1 drivers +v0x2bba000_0 .alias "Command", 2 0, v0x2bc67a0_0; +v0x2bba080_0 .net *"_s3", 0 0, L_0x2bd5e10; 1 drivers +v0x2bba100_0 .net *"_s5", 0 0, L_0x2bd5ff0; 1 drivers +v0x2bba1a0_0 .net "carryin", 0 0, L_0x2bd6b50; 1 drivers +v0x2bba240_0 .net "carryout", 0 0, L_0x2bd64d0; 1 drivers +v0x2bba2e0_0 .net "nB", 0 0, L_0x2bd5300; 1 drivers +v0x2bba390_0 .net "nCmd2", 0 0, L_0x2bd5d50; 1 drivers +v0x2bba490_0 .net "subtract", 0 0, L_0x2bd5eb0; 1 drivers +L_0x2bd5cb0 .part v0x2bc78e0_0, 0, 1; +L_0x2bd5e10 .part v0x2bc78e0_0, 2, 1; +L_0x2bd5ff0 .part v0x2bc78e0_0, 0, 1; +S_0x2bb95f0 .scope module, "mux0" "TwoInMux" 3 105, 3 8, S_0x2bb9500; + .timescale -9 -12; +L_0x2bd5460/d .functor NOT 1, L_0x2bd5cb0, C4<0>, C4<0>, C4<0>; +L_0x2bd5460 .delay (10000,10000,10000) L_0x2bd5460/d; +L_0x2bd58e0/d .functor AND 1, L_0x2bd6a20, L_0x2bd5460, C4<1>, C4<1>; +L_0x2bd58e0 .delay (20000,20000,20000) L_0x2bd58e0/d; +L_0x2bd59d0/d .functor AND 1, L_0x2bd5300, L_0x2bd5cb0, C4<1>, C4<1>; +L_0x2bd59d0 .delay (20000,20000,20000) L_0x2bd59d0/d; +L_0x2bd5ae0/d .functor OR 1, L_0x2bd58e0, L_0x2bd59d0, C4<0>, C4<0>; +L_0x2bd5ae0 .delay (20000,20000,20000) L_0x2bd5ae0/d; +v0x2bb96e0_0 .net "S", 0 0, L_0x2bd5cb0; 1 drivers +v0x2bb9780_0 .alias "in0", 0 0, v0x2bb9e10_0; +v0x2bb9820_0 .alias "in1", 0 0, v0x2bba2e0_0; +v0x2bb98c0_0 .net "nS", 0 0, L_0x2bd5460; 1 drivers +v0x2bb9970_0 .net "out0", 0 0, L_0x2bd58e0; 1 drivers +v0x2bb9a10_0 .net "out1", 0 0, L_0x2bd59d0; 1 drivers +v0x2bb9af0_0 .alias "outfinal", 0 0, v0x2bb9ec0_0; +S_0x2bb81f0 .scope generate, "addbits[12]" "addbits[12]" 3 230, 3 230, S_0x2ba3100; + .timescale -9 -12; +P_0x2bb7c08 .param/l "i" 3 230, +C4<01100>; +S_0x2bb8360 .scope module, "attempt" "MiddleAddSubSLT" 3 232, 3 89, S_0x2bb81f0; + .timescale -9 -12; +L_0x2bd5840/d .functor NOT 1, L_0x2bd7f60, C4<0>, C4<0>, C4<0>; +L_0x2bd5840 .delay (10000,10000,10000) L_0x2bd5840/d; +L_0x2bd7260/d .functor NOT 1, L_0x2bd7320, C4<0>, C4<0>, C4<0>; +L_0x2bd7260 .delay (10000,10000,10000) L_0x2bd7260/d; +L_0x2bd73c0/d .functor AND 1, L_0x2bd7500, L_0x2bd7260, C4<1>, C4<1>; +L_0x2bd73c0 .delay (20000,20000,20000) L_0x2bd73c0/d; +L_0x2bd75a0/d .functor XOR 1, L_0x2bd6ce0, L_0x2bd6ff0, C4<0>, C4<0>; +L_0x2bd75a0 .delay (40000,40000,40000) L_0x2bd75a0/d; +L_0x2bd7690/d .functor XOR 1, L_0x2bd75a0, L_0x2bd8000, C4<0>, C4<0>; +L_0x2bd7690 .delay (40000,40000,40000) L_0x2bd7690/d; +L_0x2bd7780/d .functor AND 1, L_0x2bd6ce0, L_0x2bd6ff0, C4<1>, C4<1>; +L_0x2bd7780 .delay (20000,20000,20000) L_0x2bd7780/d; +L_0x2bd78f0/d .functor AND 1, L_0x2bd75a0, L_0x2bd8000, C4<1>, C4<1>; +L_0x2bd78f0 .delay (20000,20000,20000) L_0x2bd78f0/d; +L_0x2bd79e0/d .functor OR 1, L_0x2bd7780, L_0x2bd78f0, C4<0>, C4<0>; +L_0x2bd79e0 .delay (20000,20000,20000) L_0x2bd79e0/d; +v0x2bb89f0_0 .net "A", 0 0, L_0x2bd6ce0; 1 drivers +v0x2bb8ab0_0 .net "AandB", 0 0, L_0x2bd7780; 1 drivers +v0x2bb8b50_0 .net "AddSubSLTSum", 0 0, L_0x2bd7690; 1 drivers +v0x2bb8bf0_0 .net "AxorB", 0 0, L_0x2bd75a0; 1 drivers +v0x2bb8c70_0 .net "B", 0 0, L_0x2bd7f60; 1 drivers +v0x2bb8d20_0 .net "BornB", 0 0, L_0x2bd6ff0; 1 drivers +v0x2bb8de0_0 .net "CINandAxorB", 0 0, L_0x2bd78f0; 1 drivers +v0x2bb8e60_0 .alias "Command", 2 0, v0x2bc67a0_0; +v0x2bb8ee0_0 .net *"_s3", 0 0, L_0x2bd7320; 1 drivers +v0x2bb8f60_0 .net *"_s5", 0 0, L_0x2bd7500; 1 drivers +v0x2bb9000_0 .net "carryin", 0 0, L_0x2bd8000; 1 drivers +v0x2bb90a0_0 .net "carryout", 0 0, L_0x2bd79e0; 1 drivers +v0x2bb9140_0 .net "nB", 0 0, L_0x2bd5840; 1 drivers +v0x2bb91f0_0 .net "nCmd2", 0 0, L_0x2bd7260; 1 drivers +v0x2bb92f0_0 .net "subtract", 0 0, L_0x2bd73c0; 1 drivers +L_0x2bd71c0 .part v0x2bc78e0_0, 0, 1; +L_0x2bd7320 .part v0x2bc78e0_0, 2, 1; +L_0x2bd7500 .part v0x2bc78e0_0, 0, 1; +S_0x2bb8450 .scope module, "mux0" "TwoInMux" 3 105, 3 8, S_0x2bb8360; + .timescale -9 -12; +L_0x2bd6910/d .functor NOT 1, L_0x2bd71c0, C4<0>, C4<0>, C4<0>; +L_0x2bd6910 .delay (10000,10000,10000) L_0x2bd6910/d; +L_0x2bd6e10/d .functor AND 1, L_0x2bd7f60, L_0x2bd6910, C4<1>, C4<1>; +L_0x2bd6e10 .delay (20000,20000,20000) L_0x2bd6e10/d; +L_0x2bd6f00/d .functor AND 1, L_0x2bd5840, L_0x2bd71c0, C4<1>, C4<1>; +L_0x2bd6f00 .delay (20000,20000,20000) L_0x2bd6f00/d; +L_0x2bd6ff0/d .functor OR 1, L_0x2bd6e10, L_0x2bd6f00, C4<0>, C4<0>; +L_0x2bd6ff0 .delay (20000,20000,20000) L_0x2bd6ff0/d; +v0x2bb8540_0 .net "S", 0 0, L_0x2bd71c0; 1 drivers +v0x2bb85e0_0 .alias "in0", 0 0, v0x2bb8c70_0; +v0x2bb8680_0 .alias "in1", 0 0, v0x2bb9140_0; +v0x2bb8720_0 .net "nS", 0 0, L_0x2bd6910; 1 drivers +v0x2bb87d0_0 .net "out0", 0 0, L_0x2bd6e10; 1 drivers +v0x2bb8870_0 .net "out1", 0 0, L_0x2bd6f00; 1 drivers +v0x2bb8950_0 .alias "outfinal", 0 0, v0x2bb8d20_0; +S_0x2bb7050 .scope generate, "addbits[13]" "addbits[13]" 3 230, 3 230, S_0x2ba3100; + .timescale -9 -12; +P_0x2bb6a68 .param/l "i" 3 230, +C4<01101>; +S_0x2bb71c0 .scope module, "attempt" "MiddleAddSubSLT" 3 232, 3 89, S_0x2bb7050; + .timescale -9 -12; +L_0x2bd7d20/d .functor NOT 1, L_0x2bd8140, C4<0>, C4<0>, C4<0>; +L_0x2bd7d20 .delay (10000,10000,10000) L_0x2bd7d20/d; +L_0x2bd8760/d .functor NOT 1, L_0x2bd8820, C4<0>, C4<0>, C4<0>; +L_0x2bd8760 .delay (10000,10000,10000) L_0x2bd8760/d; +L_0x2bd88c0/d .functor AND 1, L_0x2bd8a00, L_0x2bd8760, C4<1>, C4<1>; +L_0x2bd88c0 .delay (20000,20000,20000) L_0x2bd88c0/d; +L_0x2bd8aa0/d .functor XOR 1, L_0x2bce760, L_0x2bd84f0, C4<0>, C4<0>; +L_0x2bd8aa0 .delay (40000,40000,40000) L_0x2bd8aa0/d; +L_0x2bd8b90/d .functor XOR 1, L_0x2bd8aa0, L_0x2bd9340, C4<0>, C4<0>; +L_0x2bd8b90 .delay (40000,40000,40000) L_0x2bd8b90/d; +L_0x2bd8c80/d .functor AND 1, L_0x2bce760, L_0x2bd84f0, C4<1>, C4<1>; +L_0x2bd8c80 .delay (20000,20000,20000) L_0x2bd8c80/d; +L_0x2bd8df0/d .functor AND 1, L_0x2bd8aa0, L_0x2bd9340, C4<1>, C4<1>; +L_0x2bd8df0 .delay (20000,20000,20000) L_0x2bd8df0/d; +L_0x2bd8ee0/d .functor OR 1, L_0x2bd8c80, L_0x2bd8df0, C4<0>, C4<0>; +L_0x2bd8ee0 .delay (20000,20000,20000) L_0x2bd8ee0/d; +v0x2bb7850_0 .net "A", 0 0, L_0x2bce760; 1 drivers +v0x2bb7910_0 .net "AandB", 0 0, L_0x2bd8c80; 1 drivers +v0x2bb79b0_0 .net "AddSubSLTSum", 0 0, L_0x2bd8b90; 1 drivers +v0x2bb7a50_0 .net "AxorB", 0 0, L_0x2bd8aa0; 1 drivers +v0x2bb7ad0_0 .net "B", 0 0, L_0x2bd8140; 1 drivers +v0x2bb7b80_0 .net "BornB", 0 0, L_0x2bd84f0; 1 drivers +v0x2bb7c40_0 .net "CINandAxorB", 0 0, L_0x2bd8df0; 1 drivers +v0x2bb7cc0_0 .alias "Command", 2 0, v0x2bc67a0_0; +v0x2bb7d40_0 .net *"_s3", 0 0, L_0x2bd8820; 1 drivers +v0x2bb7dc0_0 .net *"_s5", 0 0, L_0x2bd8a00; 1 drivers +v0x2bb7e60_0 .net "carryin", 0 0, L_0x2bd9340; 1 drivers +v0x2bb7f00_0 .net "carryout", 0 0, L_0x2bd8ee0; 1 drivers +v0x2bb7fa0_0 .net "nB", 0 0, L_0x2bd7d20; 1 drivers +v0x2bb8050_0 .net "nCmd2", 0 0, L_0x2bd8760; 1 drivers +v0x2bb8150_0 .net "subtract", 0 0, L_0x2bd88c0; 1 drivers +L_0x2bd86c0 .part v0x2bc78e0_0, 0, 1; +L_0x2bd8820 .part v0x2bc78e0_0, 2, 1; +L_0x2bd8a00 .part v0x2bc78e0_0, 0, 1; +S_0x2bb72b0 .scope module, "mux0" "TwoInMux" 3 105, 3 8, S_0x2bb71c0; + .timescale -9 -12; +L_0x2bd7e80/d .functor NOT 1, L_0x2bd86c0, C4<0>, C4<0>, C4<0>; +L_0x2bd7e80 .delay (10000,10000,10000) L_0x2bd7e80/d; +L_0x2bd82f0/d .functor AND 1, L_0x2bd8140, L_0x2bd7e80, C4<1>, C4<1>; +L_0x2bd82f0 .delay (20000,20000,20000) L_0x2bd82f0/d; +L_0x2bd83e0/d .functor AND 1, L_0x2bd7d20, L_0x2bd86c0, C4<1>, C4<1>; +L_0x2bd83e0 .delay (20000,20000,20000) L_0x2bd83e0/d; +L_0x2bd84f0/d .functor OR 1, L_0x2bd82f0, L_0x2bd83e0, C4<0>, C4<0>; +L_0x2bd84f0 .delay (20000,20000,20000) L_0x2bd84f0/d; +v0x2bb73a0_0 .net "S", 0 0, L_0x2bd86c0; 1 drivers +v0x2bb7440_0 .alias "in0", 0 0, v0x2bb7ad0_0; +v0x2bb74e0_0 .alias "in1", 0 0, v0x2bb7fa0_0; +v0x2bb7580_0 .net "nS", 0 0, L_0x2bd7e80; 1 drivers +v0x2bb7630_0 .net "out0", 0 0, L_0x2bd82f0; 1 drivers +v0x2bb76d0_0 .net "out1", 0 0, L_0x2bd83e0; 1 drivers +v0x2bb77b0_0 .alias "outfinal", 0 0, v0x2bb7b80_0; +S_0x2bb5eb0 .scope generate, "addbits[14]" "addbits[14]" 3 230, 3 230, S_0x2ba3100; + .timescale -9 -12; +P_0x2bb58c8 .param/l "i" 3 230, +C4<01110>; +S_0x2bb6020 .scope module, "attempt" "MiddleAddSubSLT" 3 232, 3 89, S_0x2bb5eb0; + .timescale -9 -12; +L_0x2bd93e0/d .functor NOT 1, L_0x2bd9940, C4<0>, C4<0>, C4<0>; +L_0x2bd93e0 .delay (10000,10000,10000) L_0x2bd93e0/d; +L_0x2bd9e60/d .functor NOT 1, L_0x2bd9f20, C4<0>, C4<0>, C4<0>; +L_0x2bd9e60 .delay (10000,10000,10000) L_0x2bd9e60/d; +L_0x2bd9fc0/d .functor AND 1, L_0x2bda100, L_0x2bd9e60, C4<1>, C4<1>; +L_0x2bd9fc0 .delay (20000,20000,20000) L_0x2bd9fc0/d; +L_0x2bda1a0/d .functor XOR 1, L_0x2bd98a0, L_0x2bd9bf0, C4<0>, C4<0>; +L_0x2bda1a0 .delay (40000,40000,40000) L_0x2bda1a0/d; +L_0x2bda290/d .functor XOR 1, L_0x2bda1a0, L_0x2bdac50, C4<0>, C4<0>; +L_0x2bda290 .delay (40000,40000,40000) L_0x2bda290/d; +L_0x2bda380/d .functor AND 1, L_0x2bd98a0, L_0x2bd9bf0, C4<1>, C4<1>; +L_0x2bda380 .delay (20000,20000,20000) L_0x2bda380/d; +L_0x2bda4f0/d .functor AND 1, L_0x2bda1a0, L_0x2bdac50, C4<1>, C4<1>; +L_0x2bda4f0 .delay (20000,20000,20000) L_0x2bda4f0/d; +L_0x2bda5e0/d .functor OR 1, L_0x2bda380, L_0x2bda4f0, C4<0>, C4<0>; +L_0x2bda5e0 .delay (20000,20000,20000) L_0x2bda5e0/d; +v0x2bb66b0_0 .net "A", 0 0, L_0x2bd98a0; 1 drivers +v0x2bb6770_0 .net "AandB", 0 0, L_0x2bda380; 1 drivers +v0x2bb6810_0 .net "AddSubSLTSum", 0 0, L_0x2bda290; 1 drivers +v0x2bb68b0_0 .net "AxorB", 0 0, L_0x2bda1a0; 1 drivers +v0x2bb6930_0 .net "B", 0 0, L_0x2bd9940; 1 drivers +v0x2bb69e0_0 .net "BornB", 0 0, L_0x2bd9bf0; 1 drivers +v0x2bb6aa0_0 .net "CINandAxorB", 0 0, L_0x2bda4f0; 1 drivers +v0x2bb6b20_0 .alias "Command", 2 0, v0x2bc67a0_0; +v0x2bb6ba0_0 .net *"_s3", 0 0, L_0x2bd9f20; 1 drivers +v0x2bb6c20_0 .net *"_s5", 0 0, L_0x2bda100; 1 drivers +v0x2bb6cc0_0 .net "carryin", 0 0, L_0x2bdac50; 1 drivers +v0x2bb6d60_0 .net "carryout", 0 0, L_0x2bda5e0; 1 drivers +v0x2bb6e00_0 .net "nB", 0 0, L_0x2bd93e0; 1 drivers +v0x2bb6eb0_0 .net "nCmd2", 0 0, L_0x2bd9e60; 1 drivers +v0x2bb6fb0_0 .net "subtract", 0 0, L_0x2bd9fc0; 1 drivers +L_0x2bd9dc0 .part v0x2bc78e0_0, 0, 1; +L_0x2bd9f20 .part v0x2bc78e0_0, 2, 1; +L_0x2bda100 .part v0x2bc78e0_0, 0, 1; +S_0x2bb6110 .scope module, "mux0" "TwoInMux" 3 105, 3 8, S_0x2bb6020; + .timescale -9 -12; +L_0x2bd9500/d .functor NOT 1, L_0x2bd9dc0, C4<0>, C4<0>, C4<0>; +L_0x2bd9500 .delay (10000,10000,10000) L_0x2bd9500/d; +L_0x2bd9a30/d .functor AND 1, L_0x2bd9940, L_0x2bd9500, C4<1>, C4<1>; +L_0x2bd9a30 .delay (20000,20000,20000) L_0x2bd9a30/d; +L_0x2bd9ae0/d .functor AND 1, L_0x2bd93e0, L_0x2bd9dc0, C4<1>, C4<1>; +L_0x2bd9ae0 .delay (20000,20000,20000) L_0x2bd9ae0/d; +L_0x2bd9bf0/d .functor OR 1, L_0x2bd9a30, L_0x2bd9ae0, C4<0>, C4<0>; +L_0x2bd9bf0 .delay (20000,20000,20000) L_0x2bd9bf0/d; +v0x2bb6200_0 .net "S", 0 0, L_0x2bd9dc0; 1 drivers +v0x2bb62a0_0 .alias "in0", 0 0, v0x2bb6930_0; +v0x2bb6340_0 .alias "in1", 0 0, v0x2bb6e00_0; +v0x2bb63e0_0 .net "nS", 0 0, L_0x2bd9500; 1 drivers +v0x2bb6490_0 .net "out0", 0 0, L_0x2bd9a30; 1 drivers +v0x2bb6530_0 .net "out1", 0 0, L_0x2bd9ae0; 1 drivers +v0x2bb6610_0 .alias "outfinal", 0 0, v0x2bb69e0_0; +S_0x2bb4d10 .scope generate, "addbits[15]" "addbits[15]" 3 230, 3 230, S_0x2ba3100; + .timescale -9 -12; +P_0x2bb4728 .param/l "i" 3 230, +C4<01111>; +S_0x2bb4e80 .scope module, "attempt" "MiddleAddSubSLT" 3 232, 3 89, S_0x2bb4d10; + .timescale -9 -12; +L_0x2bda920/d .functor NOT 1, L_0x2bdae80, C4<0>, C4<0>, C4<0>; +L_0x2bda920 .delay (10000,10000,10000) L_0x2bda920/d; +L_0x2bdb370/d .functor NOT 1, L_0x2bdb430, C4<0>, C4<0>, C4<0>; +L_0x2bdb370 .delay (10000,10000,10000) L_0x2bdb370/d; +L_0x2bdb4d0/d .functor AND 1, L_0x2bdb610, L_0x2bdb370, C4<1>, C4<1>; +L_0x2bdb4d0 .delay (20000,20000,20000) L_0x2bdb4d0/d; +L_0x2bdb6b0/d .functor XOR 1, L_0x2bdade0, L_0x2bdb100, C4<0>, C4<0>; +L_0x2bdb6b0 .delay (40000,40000,40000) L_0x2bdb6b0/d; +L_0x2bdb7a0/d .functor XOR 1, L_0x2bdb6b0, L_0x2bdc190, C4<0>, C4<0>; +L_0x2bdb7a0 .delay (40000,40000,40000) L_0x2bdb7a0/d; +L_0x2bdb890/d .functor AND 1, L_0x2bdade0, L_0x2bdb100, C4<1>, C4<1>; +L_0x2bdb890 .delay (20000,20000,20000) L_0x2bdb890/d; +L_0x2bdba00/d .functor AND 1, L_0x2bdb6b0, L_0x2bdc190, C4<1>, C4<1>; +L_0x2bdba00 .delay (20000,20000,20000) L_0x2bdba00/d; +L_0x2bdbaf0/d .functor OR 1, L_0x2bdb890, L_0x2bdba00, C4<0>, C4<0>; +L_0x2bdbaf0 .delay (20000,20000,20000) L_0x2bdbaf0/d; +v0x2bb5510_0 .net "A", 0 0, L_0x2bdade0; 1 drivers +v0x2bb55d0_0 .net "AandB", 0 0, L_0x2bdb890; 1 drivers +v0x2bb5670_0 .net "AddSubSLTSum", 0 0, L_0x2bdb7a0; 1 drivers +v0x2bb5710_0 .net "AxorB", 0 0, L_0x2bdb6b0; 1 drivers +v0x2bb5790_0 .net "B", 0 0, L_0x2bdae80; 1 drivers +v0x2bb5840_0 .net "BornB", 0 0, L_0x2bdb100; 1 drivers +v0x2bb5900_0 .net "CINandAxorB", 0 0, L_0x2bdba00; 1 drivers +v0x2bb5980_0 .alias "Command", 2 0, v0x2bc67a0_0; +v0x2bb5a00_0 .net *"_s3", 0 0, L_0x2bdb430; 1 drivers +v0x2bb5a80_0 .net *"_s5", 0 0, L_0x2bdb610; 1 drivers +v0x2bb5b20_0 .net "carryin", 0 0, L_0x2bdc190; 1 drivers +v0x2bb5bc0_0 .net "carryout", 0 0, L_0x2bdbaf0; 1 drivers +v0x2bb5c60_0 .net "nB", 0 0, L_0x2bda920; 1 drivers +v0x2bb5d10_0 .net "nCmd2", 0 0, L_0x2bdb370; 1 drivers +v0x2bb5e10_0 .net "subtract", 0 0, L_0x2bdb4d0; 1 drivers +L_0x2bdb2d0 .part v0x2bc78e0_0, 0, 1; +L_0x2bdb430 .part v0x2bc78e0_0, 2, 1; +L_0x2bdb610 .part v0x2bc78e0_0, 0, 1; +S_0x2bb4f70 .scope module, "mux0" "TwoInMux" 3 105, 3 8, S_0x2bb4e80; + .timescale -9 -12; +L_0x2bdaa30/d .functor NOT 1, L_0x2bdb2d0, C4<0>, C4<0>, C4<0>; +L_0x2bdaa30 .delay (10000,10000,10000) L_0x2bdaa30/d; +L_0x2bdaaf0/d .functor AND 1, L_0x2bdae80, L_0x2bdaa30, C4<1>, C4<1>; +L_0x2bdaaf0 .delay (20000,20000,20000) L_0x2bdaaf0/d; +L_0x2bdaff0/d .functor AND 1, L_0x2bda920, L_0x2bdb2d0, C4<1>, C4<1>; +L_0x2bdaff0 .delay (20000,20000,20000) L_0x2bdaff0/d; +L_0x2bdb100/d .functor OR 1, L_0x2bdaaf0, L_0x2bdaff0, C4<0>, C4<0>; +L_0x2bdb100 .delay (20000,20000,20000) L_0x2bdb100/d; +v0x2bb5060_0 .net "S", 0 0, L_0x2bdb2d0; 1 drivers +v0x2bb5100_0 .alias "in0", 0 0, v0x2bb5790_0; +v0x2bb51a0_0 .alias "in1", 0 0, v0x2bb5c60_0; +v0x2bb5240_0 .net "nS", 0 0, L_0x2bdaa30; 1 drivers +v0x2bb52f0_0 .net "out0", 0 0, L_0x2bdaaf0; 1 drivers +v0x2bb5390_0 .net "out1", 0 0, L_0x2bdaff0; 1 drivers +v0x2bb5470_0 .alias "outfinal", 0 0, v0x2bb5840_0; +S_0x2bb3b70 .scope generate, "addbits[16]" "addbits[16]" 3 230, 3 230, S_0x2ba3100; + .timescale -9 -12; +P_0x2bb3588 .param/l "i" 3 230, +C4<010000>; +S_0x2bb3ce0 .scope module, "attempt" "MiddleAddSubSLT" 3 232, 3 89, S_0x2bb3b70; + .timescale -9 -12; +L_0x2bdaf20/d .functor NOT 1, L_0x2bdc3c0, C4<0>, C4<0>, C4<0>; +L_0x2bdaf20 .delay (10000,10000,10000) L_0x2bdaf20/d; +L_0x2bdc870/d .functor NOT 1, L_0x2bdc930, C4<0>, C4<0>, C4<0>; +L_0x2bdc870 .delay (10000,10000,10000) L_0x2bdc870/d; +L_0x2bdc9d0/d .functor AND 1, L_0x2bdcb10, L_0x2bdc870, C4<1>, C4<1>; +L_0x2bdc9d0 .delay (20000,20000,20000) L_0x2bdc9d0/d; +L_0x2bdcbb0/d .functor XOR 1, L_0x2bdc320, L_0x2bdc600, C4<0>, C4<0>; +L_0x2bdcbb0 .delay (40000,40000,40000) L_0x2bdcbb0/d; +L_0x2bdcca0/d .functor XOR 1, L_0x2bdcbb0, L_0x2bdd630, C4<0>, C4<0>; +L_0x2bdcca0 .delay (40000,40000,40000) L_0x2bdcca0/d; +L_0x2bdcd90/d .functor AND 1, L_0x2bdc320, L_0x2bdc600, C4<1>, C4<1>; +L_0x2bdcd90 .delay (20000,20000,20000) L_0x2bdcd90/d; +L_0x2bdcf00/d .functor AND 1, L_0x2bdcbb0, L_0x2bdd630, C4<1>, C4<1>; +L_0x2bdcf00 .delay (20000,20000,20000) L_0x2bdcf00/d; +L_0x2bdcff0/d .functor OR 1, L_0x2bdcd90, L_0x2bdcf00, C4<0>, C4<0>; +L_0x2bdcff0 .delay (20000,20000,20000) L_0x2bdcff0/d; +v0x2bb4370_0 .net "A", 0 0, L_0x2bdc320; 1 drivers +v0x2bb4430_0 .net "AandB", 0 0, L_0x2bdcd90; 1 drivers +v0x2bb44d0_0 .net "AddSubSLTSum", 0 0, L_0x2bdcca0; 1 drivers +v0x2bb4570_0 .net "AxorB", 0 0, L_0x2bdcbb0; 1 drivers +v0x2bb45f0_0 .net "B", 0 0, L_0x2bdc3c0; 1 drivers +v0x2bb46a0_0 .net "BornB", 0 0, L_0x2bdc600; 1 drivers +v0x2bb4760_0 .net "CINandAxorB", 0 0, L_0x2bdcf00; 1 drivers +v0x2bb47e0_0 .alias "Command", 2 0, v0x2bc67a0_0; +v0x2bb4860_0 .net *"_s3", 0 0, L_0x2bdc930; 1 drivers +v0x2bb48e0_0 .net *"_s5", 0 0, L_0x2bdcb10; 1 drivers +v0x2bb4980_0 .net "carryin", 0 0, L_0x2bdd630; 1 drivers +v0x2bb4a20_0 .net "carryout", 0 0, L_0x2bdcff0; 1 drivers +v0x2bb4ac0_0 .net "nB", 0 0, L_0x2bdaf20; 1 drivers +v0x2bb4b70_0 .net "nCmd2", 0 0, L_0x2bdc870; 1 drivers +v0x2bb4c70_0 .net "subtract", 0 0, L_0x2bdc9d0; 1 drivers +L_0x2bdc7d0 .part v0x2bc78e0_0, 0, 1; +L_0x2bdc930 .part v0x2bc78e0_0, 2, 1; +L_0x2bdcb10 .part v0x2bc78e0_0, 0, 1; +S_0x2bb3dd0 .scope module, "mux0" "TwoInMux" 3 105, 3 8, S_0x2bb3ce0; + .timescale -9 -12; +L_0x2bdbf10/d .functor NOT 1, L_0x2bdc7d0, C4<0>, C4<0>, C4<0>; +L_0x2bdbf10 .delay (10000,10000,10000) L_0x2bdbf10/d; +L_0x2bdbfd0/d .functor AND 1, L_0x2bdc3c0, L_0x2bdbf10, C4<1>, C4<1>; +L_0x2bdbfd0 .delay (20000,20000,20000) L_0x2bdbfd0/d; +L_0x2bdc510/d .functor AND 1, L_0x2bdaf20, L_0x2bdc7d0, C4<1>, C4<1>; +L_0x2bdc510 .delay (20000,20000,20000) L_0x2bdc510/d; +L_0x2bdc600/d .functor OR 1, L_0x2bdbfd0, L_0x2bdc510, C4<0>, C4<0>; +L_0x2bdc600 .delay (20000,20000,20000) L_0x2bdc600/d; +v0x2bb3ec0_0 .net "S", 0 0, L_0x2bdc7d0; 1 drivers +v0x2bb3f60_0 .alias "in0", 0 0, v0x2bb45f0_0; +v0x2bb4000_0 .alias "in1", 0 0, v0x2bb4ac0_0; +v0x2bb40a0_0 .net "nS", 0 0, L_0x2bdbf10; 1 drivers +v0x2bb4150_0 .net "out0", 0 0, L_0x2bdbfd0; 1 drivers +v0x2bb41f0_0 .net "out1", 0 0, L_0x2bdc510; 1 drivers +v0x2bb42d0_0 .alias "outfinal", 0 0, v0x2bb46a0_0; +S_0x2bb29d0 .scope generate, "addbits[17]" "addbits[17]" 3 230, 3 230, S_0x2ba3100; + .timescale -9 -12; +P_0x2bb23e8 .param/l "i" 3 230, +C4<010001>; +S_0x2bb2b40 .scope module, "attempt" "MiddleAddSubSLT" 3 232, 3 89, S_0x2bb29d0; + .timescale -9 -12; +L_0x2bc7450/d .functor NOT 1, L_0x2bddc70, C4<0>, C4<0>, C4<0>; +L_0x2bc7450 .delay (10000,10000,10000) L_0x2bc7450/d; +L_0x2bddee0/d .functor NOT 1, L_0x2bddf40, C4<0>, C4<0>, C4<0>; +L_0x2bddee0 .delay (10000,10000,10000) L_0x2bddee0/d; +L_0x2bddfe0/d .functor AND 1, L_0x2bde120, L_0x2bddee0, C4<1>, C4<1>; +L_0x2bddfe0 .delay (20000,20000,20000) L_0x2bddfe0/d; +L_0x2bde1c0/d .functor XOR 1, L_0x2bddbd0, L_0x2bdd490, C4<0>, C4<0>; +L_0x2bde1c0 .delay (40000,40000,40000) L_0x2bde1c0/d; +L_0x2bde2b0/d .functor XOR 1, L_0x2bde1c0, L_0x2bdec50, C4<0>, C4<0>; +L_0x2bde2b0 .delay (40000,40000,40000) L_0x2bde2b0/d; +L_0x2bde3a0/d .functor AND 1, L_0x2bddbd0, L_0x2bdd490, C4<1>, C4<1>; +L_0x2bde3a0 .delay (20000,20000,20000) L_0x2bde3a0/d; +L_0x2bde510/d .functor AND 1, L_0x2bde1c0, L_0x2bdec50, C4<1>, C4<1>; +L_0x2bde510 .delay (20000,20000,20000) L_0x2bde510/d; +L_0x2bde600/d .functor OR 1, L_0x2bde3a0, L_0x2bde510, C4<0>, C4<0>; +L_0x2bde600 .delay (20000,20000,20000) L_0x2bde600/d; +v0x2bb31d0_0 .net "A", 0 0, L_0x2bddbd0; 1 drivers +v0x2bb3290_0 .net "AandB", 0 0, L_0x2bde3a0; 1 drivers +v0x2bb3330_0 .net "AddSubSLTSum", 0 0, L_0x2bde2b0; 1 drivers +v0x2bb33d0_0 .net "AxorB", 0 0, L_0x2bde1c0; 1 drivers +v0x2bb3450_0 .net "B", 0 0, L_0x2bddc70; 1 drivers +v0x2bb3500_0 .net "BornB", 0 0, L_0x2bdd490; 1 drivers +v0x2bb35c0_0 .net "CINandAxorB", 0 0, L_0x2bde510; 1 drivers +v0x2bb3640_0 .alias "Command", 2 0, v0x2bc67a0_0; +v0x2bb36c0_0 .net *"_s3", 0 0, L_0x2bddf40; 1 drivers +v0x2bb3740_0 .net *"_s5", 0 0, L_0x2bde120; 1 drivers +v0x2bb37e0_0 .net "carryin", 0 0, L_0x2bdec50; 1 drivers +v0x2bb3880_0 .net "carryout", 0 0, L_0x2bde600; 1 drivers +v0x2bb3920_0 .net "nB", 0 0, L_0x2bc7450; 1 drivers +v0x2bb39d0_0 .net "nCmd2", 0 0, L_0x2bddee0; 1 drivers +v0x2bb3ad0_0 .net "subtract", 0 0, L_0x2bddfe0; 1 drivers +L_0x2bdde40 .part v0x2bc78e0_0, 0, 1; +L_0x2bddf40 .part v0x2bc78e0_0, 2, 1; +L_0x2bde120 .part v0x2bc78e0_0, 0, 1; +S_0x2bb2c30 .scope module, "mux0" "TwoInMux" 3 105, 3 8, S_0x2bb2b40; + .timescale -9 -12; +L_0x2bd2aa0/d .functor NOT 1, L_0x2bdde40, C4<0>, C4<0>, C4<0>; +L_0x2bd2aa0 .delay (10000,10000,10000) L_0x2bd2aa0/d; +L_0x2bd2b60/d .functor AND 1, L_0x2bddc70, L_0x2bd2aa0, C4<1>, C4<1>; +L_0x2bd2b60 .delay (20000,20000,20000) L_0x2bd2b60/d; +L_0x2bdd380/d .functor AND 1, L_0x2bc7450, L_0x2bdde40, C4<1>, C4<1>; +L_0x2bdd380 .delay (20000,20000,20000) L_0x2bdd380/d; +L_0x2bdd490/d .functor OR 1, L_0x2bd2b60, L_0x2bdd380, C4<0>, C4<0>; +L_0x2bdd490 .delay (20000,20000,20000) L_0x2bdd490/d; +v0x2bb2d20_0 .net "S", 0 0, L_0x2bdde40; 1 drivers +v0x2bb2dc0_0 .alias "in0", 0 0, v0x2bb3450_0; +v0x2bb2e60_0 .alias "in1", 0 0, v0x2bb3920_0; +v0x2bb2f00_0 .net "nS", 0 0, L_0x2bd2aa0; 1 drivers +v0x2bb2fb0_0 .net "out0", 0 0, L_0x2bd2b60; 1 drivers +v0x2bb3050_0 .net "out1", 0 0, L_0x2bdd380; 1 drivers +v0x2bb3130_0 .alias "outfinal", 0 0, v0x2bb3500_0; +S_0x2bb1830 .scope generate, "addbits[18]" "addbits[18]" 3 230, 3 230, S_0x2ba3100; + .timescale -9 -12; +P_0x2bb1248 .param/l "i" 3 230, +C4<010010>; +S_0x2bb19a0 .scope module, "attempt" "MiddleAddSubSLT" 3 232, 3 89, S_0x2bb1830; + .timescale -9 -12; +L_0x2bde920/d .functor NOT 1, L_0x2bdee80, C4<0>, C4<0>, C4<0>; +L_0x2bde920 .delay (10000,10000,10000) L_0x2bde920/d; +L_0x2bdf310/d .functor NOT 1, L_0x2bdf3b0, C4<0>, C4<0>, C4<0>; +L_0x2bdf310 .delay (10000,10000,10000) L_0x2bdf310/d; +L_0x2bdf450/d .functor AND 1, L_0x2bdf590, L_0x2bdf310, C4<1>, C4<1>; +L_0x2bdf450 .delay (20000,20000,20000) L_0x2bdf450/d; +L_0x2bdf630/d .functor XOR 1, L_0x2bdede0, L_0x2bdf0e0, C4<0>, C4<0>; +L_0x2bdf630 .delay (40000,40000,40000) L_0x2bdf630/d; +L_0x2bdf720/d .functor XOR 1, L_0x2bdf630, L_0x2be00f0, C4<0>, C4<0>; +L_0x2bdf720 .delay (40000,40000,40000) L_0x2bdf720/d; +L_0x2bdf810/d .functor AND 1, L_0x2bdede0, L_0x2bdf0e0, C4<1>, C4<1>; +L_0x2bdf810 .delay (20000,20000,20000) L_0x2bdf810/d; +L_0x2bdf980/d .functor AND 1, L_0x2bdf630, L_0x2be00f0, C4<1>, C4<1>; +L_0x2bdf980 .delay (20000,20000,20000) L_0x2bdf980/d; +L_0x2bdfa70/d .functor OR 1, L_0x2bdf810, L_0x2bdf980, C4<0>, C4<0>; +L_0x2bdfa70 .delay (20000,20000,20000) L_0x2bdfa70/d; +v0x2bb2030_0 .net "A", 0 0, L_0x2bdede0; 1 drivers +v0x2bb20f0_0 .net "AandB", 0 0, L_0x2bdf810; 1 drivers +v0x2bb2190_0 .net "AddSubSLTSum", 0 0, L_0x2bdf720; 1 drivers +v0x2bb2230_0 .net "AxorB", 0 0, L_0x2bdf630; 1 drivers +v0x2bb22b0_0 .net "B", 0 0, L_0x2bdee80; 1 drivers +v0x2bb2360_0 .net "BornB", 0 0, L_0x2bdf0e0; 1 drivers +v0x2bb2420_0 .net "CINandAxorB", 0 0, L_0x2bdf980; 1 drivers +v0x2bb24a0_0 .alias "Command", 2 0, v0x2bc67a0_0; +v0x2bb2520_0 .net *"_s3", 0 0, L_0x2bdf3b0; 1 drivers +v0x2bb25a0_0 .net *"_s5", 0 0, L_0x2bdf590; 1 drivers +v0x2bb2640_0 .net "carryin", 0 0, L_0x2be00f0; 1 drivers +v0x2bb26e0_0 .net "carryout", 0 0, L_0x2bdfa70; 1 drivers +v0x2bb2780_0 .net "nB", 0 0, L_0x2bde920; 1 drivers +v0x2bb2830_0 .net "nCmd2", 0 0, L_0x2bdf310; 1 drivers +v0x2bb2930_0 .net "subtract", 0 0, L_0x2bdf450; 1 drivers +L_0x2bdf270 .part v0x2bc78e0_0, 0, 1; +L_0x2bdf3b0 .part v0x2bc78e0_0, 2, 1; +L_0x2bdf590 .part v0x2bc78e0_0, 0, 1; +S_0x2bb1a90 .scope module, "mux0" "TwoInMux" 3 105, 3 8, S_0x2bb19a0; + .timescale -9 -12; +L_0x2bdea30/d .functor NOT 1, L_0x2bdf270, C4<0>, C4<0>, C4<0>; +L_0x2bdea30 .delay (10000,10000,10000) L_0x2bdea30/d; +L_0x2bdeaf0/d .functor AND 1, L_0x2bdee80, L_0x2bdea30, C4<1>, C4<1>; +L_0x2bdeaf0 .delay (20000,20000,20000) L_0x2bdeaf0/d; +L_0x2bdf030/d .functor AND 1, L_0x2bde920, L_0x2bdf270, C4<1>, C4<1>; +L_0x2bdf030 .delay (20000,20000,20000) L_0x2bdf030/d; +L_0x2bdf0e0/d .functor OR 1, L_0x2bdeaf0, L_0x2bdf030, C4<0>, C4<0>; +L_0x2bdf0e0 .delay (20000,20000,20000) L_0x2bdf0e0/d; +v0x2bb1b80_0 .net "S", 0 0, L_0x2bdf270; 1 drivers +v0x2bb1c20_0 .alias "in0", 0 0, v0x2bb22b0_0; +v0x2bb1cc0_0 .alias "in1", 0 0, v0x2bb2780_0; +v0x2bb1d60_0 .net "nS", 0 0, L_0x2bdea30; 1 drivers +v0x2bb1e10_0 .net "out0", 0 0, L_0x2bdeaf0; 1 drivers +v0x2bb1eb0_0 .net "out1", 0 0, L_0x2bdf030; 1 drivers +v0x2bb1f90_0 .alias "outfinal", 0 0, v0x2bb2360_0; +S_0x2bb0690 .scope generate, "addbits[19]" "addbits[19]" 3 230, 3 230, S_0x2ba3100; + .timescale -9 -12; +P_0x2bb00a8 .param/l "i" 3 230, +C4<010011>; +S_0x2bb0800 .scope module, "attempt" "MiddleAddSubSLT" 3 232, 3 89, S_0x2bb0690; + .timescale -9 -12; +L_0x2bdefb0/d .functor NOT 1, L_0x2be0320, C4<0>, C4<0>, C4<0>; +L_0x2bdefb0 .delay (10000,10000,10000) L_0x2bdefb0/d; +L_0x2be07c0/d .functor NOT 1, L_0x2be0860, C4<0>, C4<0>, C4<0>; +L_0x2be07c0 .delay (10000,10000,10000) L_0x2be07c0/d; +L_0x2be0900/d .functor AND 1, L_0x2be0a40, L_0x2be07c0, C4<1>, C4<1>; +L_0x2be0900 .delay (20000,20000,20000) L_0x2be0900/d; +L_0x2b87000/d .functor XOR 1, L_0x2be0280, L_0x2be0590, C4<0>, C4<0>; +L_0x2b87000 .delay (40000,40000,40000) L_0x2b87000/d; +L_0x2b870f0/d .functor XOR 1, L_0x2b87000, L_0x2be0450, C4<0>, C4<0>; +L_0x2b870f0 .delay (40000,40000,40000) L_0x2b870f0/d; +L_0x2b871e0/d .functor AND 1, L_0x2be0280, L_0x2be0590, C4<1>, C4<1>; +L_0x2b871e0 .delay (20000,20000,20000) L_0x2b871e0/d; +L_0x2b87350/d .functor AND 1, L_0x2b87000, L_0x2be0450, C4<1>, C4<1>; +L_0x2b87350 .delay (20000,20000,20000) L_0x2b87350/d; +L_0x2b87440/d .functor OR 1, L_0x2b871e0, L_0x2b87350, C4<0>, C4<0>; +L_0x2b87440 .delay (20000,20000,20000) L_0x2b87440/d; +v0x2bb0e90_0 .net "A", 0 0, L_0x2be0280; 1 drivers +v0x2bb0f50_0 .net "AandB", 0 0, L_0x2b871e0; 1 drivers +v0x2bb0ff0_0 .net "AddSubSLTSum", 0 0, L_0x2b870f0; 1 drivers +v0x2bb1090_0 .net "AxorB", 0 0, L_0x2b87000; 1 drivers +v0x2bb1110_0 .net "B", 0 0, L_0x2be0320; 1 drivers +v0x2bb11c0_0 .net "BornB", 0 0, L_0x2be0590; 1 drivers +v0x2bb1280_0 .net "CINandAxorB", 0 0, L_0x2b87350; 1 drivers +v0x2bb1300_0 .alias "Command", 2 0, v0x2bc67a0_0; +v0x2bb1380_0 .net *"_s3", 0 0, L_0x2be0860; 1 drivers +v0x2bb1400_0 .net *"_s5", 0 0, L_0x2be0a40; 1 drivers +v0x2bb14a0_0 .net "carryin", 0 0, L_0x2be0450; 1 drivers +v0x2bb1540_0 .net "carryout", 0 0, L_0x2b87440; 1 drivers +v0x2bb15e0_0 .net "nB", 0 0, L_0x2bdefb0; 1 drivers +v0x2bb1690_0 .net "nCmd2", 0 0, L_0x2be07c0; 1 drivers +v0x2bb1790_0 .net "subtract", 0 0, L_0x2be0900; 1 drivers +L_0x2be0720 .part v0x2bc78e0_0, 0, 1; +L_0x2be0860 .part v0x2bc78e0_0, 2, 1; +L_0x2be0a40 .part v0x2bc78e0_0, 0, 1; +S_0x2bb08f0 .scope module, "mux0" "TwoInMux" 3 105, 3 8, S_0x2bb0800; + .timescale -9 -12; +L_0x2bdfe70/d .functor NOT 1, L_0x2be0720, C4<0>, C4<0>, C4<0>; +L_0x2bdfe70 .delay (10000,10000,10000) L_0x2bdfe70/d; +L_0x2bdff30/d .functor AND 1, L_0x2be0320, L_0x2bdfe70, C4<1>, C4<1>; +L_0x2bdff30 .delay (20000,20000,20000) L_0x2bdff30/d; +L_0x2be0040/d .functor AND 1, L_0x2bdefb0, L_0x2be0720, C4<1>, C4<1>; +L_0x2be0040 .delay (20000,20000,20000) L_0x2be0040/d; +L_0x2be0590/d .functor OR 1, L_0x2bdff30, L_0x2be0040, C4<0>, C4<0>; +L_0x2be0590 .delay (20000,20000,20000) L_0x2be0590/d; +v0x2bb09e0_0 .net "S", 0 0, L_0x2be0720; 1 drivers +v0x2bb0a80_0 .alias "in0", 0 0, v0x2bb1110_0; +v0x2bb0b20_0 .alias "in1", 0 0, v0x2bb15e0_0; +v0x2bb0bc0_0 .net "nS", 0 0, L_0x2bdfe70; 1 drivers +v0x2bb0c70_0 .net "out0", 0 0, L_0x2bdff30; 1 drivers +v0x2bb0d10_0 .net "out1", 0 0, L_0x2be0040; 1 drivers +v0x2bb0df0_0 .alias "outfinal", 0 0, v0x2bb11c0_0; +S_0x2baf4f0 .scope generate, "addbits[20]" "addbits[20]" 3 230, 3 230, S_0x2ba3100; + .timescale -9 -12; +P_0x2baef08 .param/l "i" 3 230, +C4<010100>; +S_0x2baf660 .scope module, "attempt" "MiddleAddSubSLT" 3 232, 3 89, S_0x2baf4f0; + .timescale -9 -12; +L_0x2b87b20/d .functor NOT 1, L_0x2b87910, C4<0>, C4<0>, C4<0>; +L_0x2b87b20 .delay (10000,10000,10000) L_0x2b87b20/d; +L_0x2be2cc0/d .functor NOT 1, L_0x2be2d60, C4<0>, C4<0>, C4<0>; +L_0x2be2cc0 .delay (10000,10000,10000) L_0x2be2cc0/d; +L_0x2be2e00/d .functor AND 1, L_0x2be2f40, L_0x2be2cc0, C4<1>, C4<1>; +L_0x2be2e00 .delay (20000,20000,20000) L_0x2be2e00/d; +L_0x2be2fe0/d .functor XOR 1, L_0x2b87870, L_0x2b87f60, C4<0>, C4<0>; +L_0x2be2fe0 .delay (40000,40000,40000) L_0x2be2fe0/d; +L_0x2be30d0/d .functor XOR 1, L_0x2be2fe0, L_0x2b87a40, C4<0>, C4<0>; +L_0x2be30d0 .delay (40000,40000,40000) L_0x2be30d0/d; +L_0x2be31c0/d .functor AND 1, L_0x2b87870, L_0x2b87f60, C4<1>, C4<1>; +L_0x2be31c0 .delay (20000,20000,20000) L_0x2be31c0/d; +L_0x2be3330/d .functor AND 1, L_0x2be2fe0, L_0x2b87a40, C4<1>, C4<1>; +L_0x2be3330 .delay (20000,20000,20000) L_0x2be3330/d; +L_0x2be3420/d .functor OR 1, L_0x2be31c0, L_0x2be3330, C4<0>, C4<0>; +L_0x2be3420 .delay (20000,20000,20000) L_0x2be3420/d; +v0x2bafcf0_0 .net "A", 0 0, L_0x2b87870; 1 drivers +v0x2bafdb0_0 .net "AandB", 0 0, L_0x2be31c0; 1 drivers +v0x2bafe50_0 .net "AddSubSLTSum", 0 0, L_0x2be30d0; 1 drivers +v0x2bafef0_0 .net "AxorB", 0 0, L_0x2be2fe0; 1 drivers +v0x2baff70_0 .net "B", 0 0, L_0x2b87910; 1 drivers +v0x2bb0020_0 .net "BornB", 0 0, L_0x2b87f60; 1 drivers +v0x2bb00e0_0 .net "CINandAxorB", 0 0, L_0x2be3330; 1 drivers +v0x2bb0160_0 .alias "Command", 2 0, v0x2bc67a0_0; +v0x2bb01e0_0 .net *"_s3", 0 0, L_0x2be2d60; 1 drivers +v0x2bb0260_0 .net *"_s5", 0 0, L_0x2be2f40; 1 drivers +v0x2bb0300_0 .net "carryin", 0 0, L_0x2b87a40; 1 drivers +v0x2bb03a0_0 .net "carryout", 0 0, L_0x2be3420; 1 drivers +v0x2bb0440_0 .net "nB", 0 0, L_0x2b87b20; 1 drivers +v0x2bb04f0_0 .net "nCmd2", 0 0, L_0x2be2cc0; 1 drivers +v0x2bb05f0_0 .net "subtract", 0 0, L_0x2be2e00; 1 drivers +L_0x2be2c20 .part v0x2bc78e0_0, 0, 1; +L_0x2be2d60 .part v0x2bc78e0_0, 2, 1; +L_0x2be2f40 .part v0x2bc78e0_0, 0, 1; +S_0x2baf750 .scope module, "mux0" "TwoInMux" 3 105, 3 8, S_0x2baf660; + .timescale -9 -12; +L_0x2b87c80/d .functor NOT 1, L_0x2be2c20, C4<0>, C4<0>, C4<0>; +L_0x2b87c80 .delay (10000,10000,10000) L_0x2b87c80/d; +L_0x2b87d40/d .functor AND 1, L_0x2b87910, L_0x2b87c80, C4<1>, C4<1>; +L_0x2b87d40 .delay (20000,20000,20000) L_0x2b87d40/d; +L_0x2b87e50/d .functor AND 1, L_0x2b87b20, L_0x2be2c20, C4<1>, C4<1>; +L_0x2b87e50 .delay (20000,20000,20000) L_0x2b87e50/d; +L_0x2b87f60/d .functor OR 1, L_0x2b87d40, L_0x2b87e50, C4<0>, C4<0>; +L_0x2b87f60 .delay (20000,20000,20000) L_0x2b87f60/d; +v0x2baf840_0 .net "S", 0 0, L_0x2be2c20; 1 drivers +v0x2baf8e0_0 .alias "in0", 0 0, v0x2baff70_0; +v0x2baf980_0 .alias "in1", 0 0, v0x2bb0440_0; +v0x2bafa20_0 .net "nS", 0 0, L_0x2b87c80; 1 drivers +v0x2bafad0_0 .net "out0", 0 0, L_0x2b87d40; 1 drivers +v0x2bafb70_0 .net "out1", 0 0, L_0x2b87e50; 1 drivers +v0x2bafc50_0 .alias "outfinal", 0 0, v0x2bb0020_0; +S_0x2bae350 .scope generate, "addbits[21]" "addbits[21]" 3 230, 3 230, S_0x2ba3100; + .timescale -9 -12; +P_0x2badd68 .param/l "i" 3 230, +C4<010101>; +S_0x2bae4c0 .scope module, "attempt" "MiddleAddSubSLT" 3 232, 3 89, S_0x2bae350; + .timescale -9 -12; +L_0x2be3b10/d .functor NOT 1, L_0x2be38d0, C4<0>, C4<0>, C4<0>; +L_0x2be3b10 .delay (10000,10000,10000) L_0x2be3b10/d; +L_0x2be4080/d .functor NOT 1, L_0x2be4120, C4<0>, C4<0>, C4<0>; +L_0x2be4080 .delay (10000,10000,10000) L_0x2be4080/d; +L_0x2be41c0/d .functor AND 1, L_0x2be4300, L_0x2be4080, C4<1>, C4<1>; +L_0x2be41c0 .delay (20000,20000,20000) L_0x2be41c0/d; +L_0x2be43a0/d .functor XOR 1, L_0x2be3830, L_0x2be3e50, C4<0>, C4<0>; +L_0x2be43a0 .delay (40000,40000,40000) L_0x2be43a0/d; +L_0x2be4490/d .functor XOR 1, L_0x2be43a0, L_0x2be3a00, C4<0>, C4<0>; +L_0x2be4490 .delay (40000,40000,40000) L_0x2be4490/d; +L_0x2be4580/d .functor AND 1, L_0x2be3830, L_0x2be3e50, C4<1>, C4<1>; +L_0x2be4580 .delay (20000,20000,20000) L_0x2be4580/d; +L_0x2be46f0/d .functor AND 1, L_0x2be43a0, L_0x2be3a00, C4<1>, C4<1>; +L_0x2be46f0 .delay (20000,20000,20000) L_0x2be46f0/d; +L_0x2be47e0/d .functor OR 1, L_0x2be4580, L_0x2be46f0, C4<0>, C4<0>; +L_0x2be47e0 .delay (20000,20000,20000) L_0x2be47e0/d; +v0x2baeb50_0 .net "A", 0 0, L_0x2be3830; 1 drivers +v0x2baec10_0 .net "AandB", 0 0, L_0x2be4580; 1 drivers +v0x2baecb0_0 .net "AddSubSLTSum", 0 0, L_0x2be4490; 1 drivers +v0x2baed50_0 .net "AxorB", 0 0, L_0x2be43a0; 1 drivers +v0x2baedd0_0 .net "B", 0 0, L_0x2be38d0; 1 drivers +v0x2baee80_0 .net "BornB", 0 0, L_0x2be3e50; 1 drivers +v0x2baef40_0 .net "CINandAxorB", 0 0, L_0x2be46f0; 1 drivers +v0x2baefc0_0 .alias "Command", 2 0, v0x2bc67a0_0; +v0x2baf040_0 .net *"_s3", 0 0, L_0x2be4120; 1 drivers +v0x2baf0c0_0 .net *"_s5", 0 0, L_0x2be4300; 1 drivers +v0x2baf160_0 .net "carryin", 0 0, L_0x2be3a00; 1 drivers +v0x2baf200_0 .net "carryout", 0 0, L_0x2be47e0; 1 drivers +v0x2baf2a0_0 .net "nB", 0 0, L_0x2be3b10; 1 drivers +v0x2baf350_0 .net "nCmd2", 0 0, L_0x2be4080; 1 drivers +v0x2baf450_0 .net "subtract", 0 0, L_0x2be41c0; 1 drivers +L_0x2be3fe0 .part v0x2bc78e0_0, 0, 1; +L_0x2be4120 .part v0x2bc78e0_0, 2, 1; +L_0x2be4300 .part v0x2bc78e0_0, 0, 1; +S_0x2bae5b0 .scope module, "mux0" "TwoInMux" 3 105, 3 8, S_0x2bae4c0; + .timescale -9 -12; +L_0x2be3c10/d .functor NOT 1, L_0x2be3fe0, C4<0>, C4<0>, C4<0>; +L_0x2be3c10 .delay (10000,10000,10000) L_0x2be3c10/d; +L_0x2be3c70/d .functor AND 1, L_0x2be38d0, L_0x2be3c10, C4<1>, C4<1>; +L_0x2be3c70 .delay (20000,20000,20000) L_0x2be3c70/d; +L_0x2be3d60/d .functor AND 1, L_0x2be3b10, L_0x2be3fe0, C4<1>, C4<1>; +L_0x2be3d60 .delay (20000,20000,20000) L_0x2be3d60/d; +L_0x2be3e50/d .functor OR 1, L_0x2be3c70, L_0x2be3d60, C4<0>, C4<0>; +L_0x2be3e50 .delay (20000,20000,20000) L_0x2be3e50/d; +v0x2bae6a0_0 .net "S", 0 0, L_0x2be3fe0; 1 drivers +v0x2bae740_0 .alias "in0", 0 0, v0x2baedd0_0; +v0x2bae7e0_0 .alias "in1", 0 0, v0x2baf2a0_0; +v0x2bae880_0 .net "nS", 0 0, L_0x2be3c10; 1 drivers +v0x2bae930_0 .net "out0", 0 0, L_0x2be3c70; 1 drivers +v0x2bae9d0_0 .net "out1", 0 0, L_0x2be3d60; 1 drivers +v0x2baeab0_0 .alias "outfinal", 0 0, v0x2baee80_0; +S_0x2bad1b0 .scope generate, "addbits[22]" "addbits[22]" 3 230, 3 230, S_0x2ba3100; + .timescale -9 -12; +P_0x2bacbc8 .param/l "i" 3 230, +C4<010110>; +S_0x2bad320 .scope module, "attempt" "MiddleAddSubSLT" 3 232, 3 89, S_0x2bad1b0; + .timescale -9 -12; +L_0x2be3aa0/d .functor NOT 1, L_0x2be4c90, C4<0>, C4<0>, C4<0>; +L_0x2be3aa0 .delay (10000,10000,10000) L_0x2be3aa0/d; +L_0x2be5450/d .functor NOT 1, L_0x2be54f0, C4<0>, C4<0>, C4<0>; +L_0x2be5450 .delay (10000,10000,10000) L_0x2be5450/d; +L_0x2be5590/d .functor AND 1, L_0x2be56d0, L_0x2be5450, C4<1>, C4<1>; +L_0x2be5590 .delay (20000,20000,20000) L_0x2be5590/d; +L_0x2be5770/d .functor XOR 1, L_0x2be4bf0, L_0x2be5220, C4<0>, C4<0>; +L_0x2be5770 .delay (40000,40000,40000) L_0x2be5770/d; +L_0x2be5860/d .functor XOR 1, L_0x2be5770, L_0x2be4dc0, C4<0>, C4<0>; +L_0x2be5860 .delay (40000,40000,40000) L_0x2be5860/d; +L_0x2be5950/d .functor AND 1, L_0x2be4bf0, L_0x2be5220, C4<1>, C4<1>; +L_0x2be5950 .delay (20000,20000,20000) L_0x2be5950/d; +L_0x2be5ac0/d .functor AND 1, L_0x2be5770, L_0x2be4dc0, C4<1>, C4<1>; +L_0x2be5ac0 .delay (20000,20000,20000) L_0x2be5ac0/d; +L_0x2be5bb0/d .functor OR 1, L_0x2be5950, L_0x2be5ac0, C4<0>, C4<0>; +L_0x2be5bb0 .delay (20000,20000,20000) L_0x2be5bb0/d; +v0x2bad9b0_0 .net "A", 0 0, L_0x2be4bf0; 1 drivers +v0x2bada70_0 .net "AandB", 0 0, L_0x2be5950; 1 drivers +v0x2badb10_0 .net "AddSubSLTSum", 0 0, L_0x2be5860; 1 drivers +v0x2badbb0_0 .net "AxorB", 0 0, L_0x2be5770; 1 drivers +v0x2badc30_0 .net "B", 0 0, L_0x2be4c90; 1 drivers +v0x2badce0_0 .net "BornB", 0 0, L_0x2be5220; 1 drivers +v0x2badda0_0 .net "CINandAxorB", 0 0, L_0x2be5ac0; 1 drivers +v0x2bade20_0 .alias "Command", 2 0, v0x2bc67a0_0; +v0x2badea0_0 .net *"_s3", 0 0, L_0x2be54f0; 1 drivers +v0x2badf20_0 .net *"_s5", 0 0, L_0x2be56d0; 1 drivers +v0x2badfc0_0 .net "carryin", 0 0, L_0x2be4dc0; 1 drivers +v0x2bae060_0 .net "carryout", 0 0, L_0x2be5bb0; 1 drivers +v0x2bae100_0 .net "nB", 0 0, L_0x2be3aa0; 1 drivers +v0x2bae1b0_0 .net "nCmd2", 0 0, L_0x2be5450; 1 drivers +v0x2bae2b0_0 .net "subtract", 0 0, L_0x2be5590; 1 drivers +L_0x2be53b0 .part v0x2bc78e0_0, 0, 1; +L_0x2be54f0 .part v0x2bc78e0_0, 2, 1; +L_0x2be56d0 .part v0x2bc78e0_0, 0, 1; +S_0x2bad410 .scope module, "mux0" "TwoInMux" 3 105, 3 8, S_0x2bad320; + .timescale -9 -12; +L_0x2be4fa0/d .functor NOT 1, L_0x2be53b0, C4<0>, C4<0>, C4<0>; +L_0x2be4fa0 .delay (10000,10000,10000) L_0x2be4fa0/d; +L_0x2be5040/d .functor AND 1, L_0x2be4c90, L_0x2be4fa0, C4<1>, C4<1>; +L_0x2be5040 .delay (20000,20000,20000) L_0x2be5040/d; +L_0x2be5130/d .functor AND 1, L_0x2be3aa0, L_0x2be53b0, C4<1>, C4<1>; +L_0x2be5130 .delay (20000,20000,20000) L_0x2be5130/d; +L_0x2be5220/d .functor OR 1, L_0x2be5040, L_0x2be5130, C4<0>, C4<0>; +L_0x2be5220 .delay (20000,20000,20000) L_0x2be5220/d; +v0x2bad500_0 .net "S", 0 0, L_0x2be53b0; 1 drivers +v0x2bad5a0_0 .alias "in0", 0 0, v0x2badc30_0; +v0x2bad640_0 .alias "in1", 0 0, v0x2bae100_0; +v0x2bad6e0_0 .net "nS", 0 0, L_0x2be4fa0; 1 drivers +v0x2bad790_0 .net "out0", 0 0, L_0x2be5040; 1 drivers +v0x2bad830_0 .net "out1", 0 0, L_0x2be5130; 1 drivers +v0x2bad910_0 .alias "outfinal", 0 0, v0x2badce0_0; +S_0x2bac010 .scope generate, "addbits[23]" "addbits[23]" 3 230, 3 230, S_0x2ba3100; + .timescale -9 -12; +P_0x2baba28 .param/l "i" 3 230, +C4<010111>; +S_0x2bac180 .scope module, "attempt" "MiddleAddSubSLT" 3 232, 3 89, S_0x2bac010; + .timescale -9 -12; +L_0x2be4e60/d .functor NOT 1, L_0x2be6060, C4<0>, C4<0>, C4<0>; +L_0x2be4e60 .delay (10000,10000,10000) L_0x2be4e60/d; +L_0x2be6810/d .functor NOT 1, L_0x2be68b0, C4<0>, C4<0>, C4<0>; +L_0x2be6810 .delay (10000,10000,10000) L_0x2be6810/d; +L_0x2be6950/d .functor AND 1, L_0x2be6a90, L_0x2be6810, C4<1>, C4<1>; +L_0x2be6950 .delay (20000,20000,20000) L_0x2be6950/d; +L_0x2be6b30/d .functor XOR 1, L_0x2be5fc0, L_0x2be65e0, C4<0>, C4<0>; +L_0x2be6b30 .delay (40000,40000,40000) L_0x2be6b30/d; +L_0x2be6c20/d .functor XOR 1, L_0x2be6b30, L_0x2be6190, C4<0>, C4<0>; +L_0x2be6c20 .delay (40000,40000,40000) L_0x2be6c20/d; +L_0x2be6d10/d .functor AND 1, L_0x2be5fc0, L_0x2be65e0, C4<1>, C4<1>; +L_0x2be6d10 .delay (20000,20000,20000) L_0x2be6d10/d; +L_0x2be6e80/d .functor AND 1, L_0x2be6b30, L_0x2be6190, C4<1>, C4<1>; +L_0x2be6e80 .delay (20000,20000,20000) L_0x2be6e80/d; +L_0x2be6f70/d .functor OR 1, L_0x2be6d10, L_0x2be6e80, C4<0>, C4<0>; +L_0x2be6f70 .delay (20000,20000,20000) L_0x2be6f70/d; +v0x2bac810_0 .net "A", 0 0, L_0x2be5fc0; 1 drivers +v0x2bac8d0_0 .net "AandB", 0 0, L_0x2be6d10; 1 drivers +v0x2bac970_0 .net "AddSubSLTSum", 0 0, L_0x2be6c20; 1 drivers +v0x2baca10_0 .net "AxorB", 0 0, L_0x2be6b30; 1 drivers +v0x2baca90_0 .net "B", 0 0, L_0x2be6060; 1 drivers +v0x2bacb40_0 .net "BornB", 0 0, L_0x2be65e0; 1 drivers +v0x2bacc00_0 .net "CINandAxorB", 0 0, L_0x2be6e80; 1 drivers +v0x2bacc80_0 .alias "Command", 2 0, v0x2bc67a0_0; +v0x2bacd00_0 .net *"_s3", 0 0, L_0x2be68b0; 1 drivers +v0x2bacd80_0 .net *"_s5", 0 0, L_0x2be6a90; 1 drivers +v0x2bace20_0 .net "carryin", 0 0, L_0x2be6190; 1 drivers +v0x2bacec0_0 .net "carryout", 0 0, L_0x2be6f70; 1 drivers +v0x2bacf60_0 .net "nB", 0 0, L_0x2be4e60; 1 drivers +v0x2bad010_0 .net "nCmd2", 0 0, L_0x2be6810; 1 drivers +v0x2bad110_0 .net "subtract", 0 0, L_0x2be6950; 1 drivers +L_0x2be6770 .part v0x2bc78e0_0, 0, 1; +L_0x2be68b0 .part v0x2bc78e0_0, 2, 1; +L_0x2be6a90 .part v0x2bc78e0_0, 0, 1; +S_0x2bac270 .scope module, "mux0" "TwoInMux" 3 105, 3 8, S_0x2bac180; + .timescale -9 -12; +L_0x2be63a0/d .functor NOT 1, L_0x2be6770, C4<0>, C4<0>, C4<0>; +L_0x2be63a0 .delay (10000,10000,10000) L_0x2be63a0/d; +L_0x2be6400/d .functor AND 1, L_0x2be6060, L_0x2be63a0, C4<1>, C4<1>; +L_0x2be6400 .delay (20000,20000,20000) L_0x2be6400/d; +L_0x2be64f0/d .functor AND 1, L_0x2be4e60, L_0x2be6770, C4<1>, C4<1>; +L_0x2be64f0 .delay (20000,20000,20000) L_0x2be64f0/d; +L_0x2be65e0/d .functor OR 1, L_0x2be6400, L_0x2be64f0, C4<0>, C4<0>; +L_0x2be65e0 .delay (20000,20000,20000) L_0x2be65e0/d; +v0x2bac360_0 .net "S", 0 0, L_0x2be6770; 1 drivers +v0x2bac400_0 .alias "in0", 0 0, v0x2baca90_0; +v0x2bac4a0_0 .alias "in1", 0 0, v0x2bacf60_0; +v0x2bac540_0 .net "nS", 0 0, L_0x2be63a0; 1 drivers +v0x2bac5f0_0 .net "out0", 0 0, L_0x2be6400; 1 drivers +v0x2bac690_0 .net "out1", 0 0, L_0x2be64f0; 1 drivers +v0x2bac770_0 .alias "outfinal", 0 0, v0x2bacb40_0; +S_0x2baaea0 .scope generate, "addbits[24]" "addbits[24]" 3 230, 3 230, S_0x2ba3100; + .timescale -9 -12; +P_0x2baa788 .param/l "i" 3 230, +C4<011000>; +S_0x2bab010 .scope module, "attempt" "MiddleAddSubSLT" 3 232, 3 89, S_0x2baaea0; + .timescale -9 -12; +L_0x2be6230/d .functor NOT 1, L_0x2be7420, C4<0>, C4<0>, C4<0>; +L_0x2be6230 .delay (10000,10000,10000) L_0x2be6230/d; +L_0x2be7c10/d .functor NOT 1, L_0x2be7cd0, C4<0>, C4<0>, C4<0>; +L_0x2be7c10 .delay (10000,10000,10000) L_0x2be7c10/d; +L_0x2be7d70/d .functor AND 1, L_0x2be7eb0, L_0x2be7c10, C4<1>, C4<1>; +L_0x2be7d70 .delay (20000,20000,20000) L_0x2be7d70/d; +L_0x2be7f50/d .functor XOR 1, L_0x2be7380, L_0x2be79c0, C4<0>, C4<0>; +L_0x2be7f50 .delay (40000,40000,40000) L_0x2be7f50/d; +L_0x2be8040/d .functor XOR 1, L_0x2be7f50, L_0x2be7550, C4<0>, C4<0>; +L_0x2be8040 .delay (40000,40000,40000) L_0x2be8040/d; +L_0x2be8160/d .functor AND 1, L_0x2be7380, L_0x2be79c0, C4<1>, C4<1>; +L_0x2be8160 .delay (20000,20000,20000) L_0x2be8160/d; +L_0x2be8300/d .functor AND 1, L_0x2be7f50, L_0x2be7550, C4<1>, C4<1>; +L_0x2be8300 .delay (20000,20000,20000) L_0x2be8300/d; +L_0x2be8410/d .functor OR 1, L_0x2be8160, L_0x2be8300, C4<0>, C4<0>; +L_0x2be8410 .delay (20000,20000,20000) L_0x2be8410/d; +v0x2bab670_0 .net "A", 0 0, L_0x2be7380; 1 drivers +v0x2bab730_0 .net "AandB", 0 0, L_0x2be8160; 1 drivers +v0x2bab7d0_0 .net "AddSubSLTSum", 0 0, L_0x2be8040; 1 drivers +v0x2bab870_0 .net "AxorB", 0 0, L_0x2be7f50; 1 drivers +v0x2bab8f0_0 .net "B", 0 0, L_0x2be7420; 1 drivers +v0x2bab9a0_0 .net "BornB", 0 0, L_0x2be79c0; 1 drivers +v0x2baba60_0 .net "CINandAxorB", 0 0, L_0x2be8300; 1 drivers +v0x2babae0_0 .alias "Command", 2 0, v0x2bc67a0_0; +v0x2babb60_0 .net *"_s3", 0 0, L_0x2be7cd0; 1 drivers +v0x2babbe0_0 .net *"_s5", 0 0, L_0x2be7eb0; 1 drivers +v0x2babc80_0 .net "carryin", 0 0, L_0x2be7550; 1 drivers +v0x2babd20_0 .net "carryout", 0 0, L_0x2be8410; 1 drivers +v0x2babdc0_0 .net "nB", 0 0, L_0x2be6230; 1 drivers +v0x2babe70_0 .net "nCmd2", 0 0, L_0x2be7c10; 1 drivers +v0x2babf70_0 .net "subtract", 0 0, L_0x2be7d70; 1 drivers +L_0x2be7b70 .part v0x2bc78e0_0, 0, 1; +L_0x2be7cd0 .part v0x2bc78e0_0, 2, 1; +L_0x2be7eb0 .part v0x2bc78e0_0, 0, 1; +S_0x2bab100 .scope module, "mux0" "TwoInMux" 3 105, 3 8, S_0x2bab010; + .timescale -9 -12; +L_0x2be7740/d .functor NOT 1, L_0x2be7b70, C4<0>, C4<0>, C4<0>; +L_0x2be7740 .delay (10000,10000,10000) L_0x2be7740/d; +L_0x2be77e0/d .functor AND 1, L_0x2be7420, L_0x2be7740, C4<1>, C4<1>; +L_0x2be77e0 .delay (20000,20000,20000) L_0x2be77e0/d; +L_0x2be78d0/d .functor AND 1, L_0x2be6230, L_0x2be7b70, C4<1>, C4<1>; +L_0x2be78d0 .delay (20000,20000,20000) L_0x2be78d0/d; +L_0x2be79c0/d .functor OR 1, L_0x2be77e0, L_0x2be78d0, C4<0>, C4<0>; +L_0x2be79c0 .delay (20000,20000,20000) L_0x2be79c0/d; +v0x2bab1f0_0 .net "S", 0 0, L_0x2be7b70; 1 drivers +v0x2bab290_0 .alias "in0", 0 0, v0x2bab8f0_0; +v0x2bab330_0 .alias "in1", 0 0, v0x2babdc0_0; +v0x2bab3d0_0 .net "nS", 0 0, L_0x2be7740; 1 drivers +v0x2bab450_0 .net "out0", 0 0, L_0x2be77e0; 1 drivers +v0x2bab4f0_0 .net "out1", 0 0, L_0x2be78d0; 1 drivers +v0x2bab5d0_0 .alias "outfinal", 0 0, v0x2bab9a0_0; +S_0x2ba9cd0 .scope generate, "addbits[25]" "addbits[25]" 3 230, 3 230, S_0x2ba3100; + .timescale -9 -12; +P_0x2ba96e8 .param/l "i" 3 230, +C4<011001>; +S_0x2ba9e40 .scope module, "attempt" "MiddleAddSubSLT" 3 232, 3 89, S_0x2ba9cd0; + .timescale -9 -12; +L_0x2be75f0/d .functor NOT 1, L_0x2bd3d90, C4<0>, C4<0>, C4<0>; +L_0x2be75f0 .delay (10000,10000,10000) L_0x2be75f0/d; +L_0x2be9100/d .functor NOT 1, L_0x2be91c0, C4<0>, C4<0>, C4<0>; +L_0x2be9100 .delay (10000,10000,10000) L_0x2be9100/d; +L_0x2be9260/d .functor AND 1, L_0x2be93a0, L_0x2be9100, C4<1>, C4<1>; +L_0x2be9260 .delay (20000,20000,20000) L_0x2be9260/d; +L_0x2be9440/d .functor XOR 1, L_0x2be8840, L_0x2be8eb0, C4<0>, C4<0>; +L_0x2be9440 .delay (40000,40000,40000) L_0x2be9440/d; +L_0x2be9530/d .functor XOR 1, L_0x2be9440, L_0x2bd3ec0, C4<0>, C4<0>; +L_0x2be9530 .delay (40000,40000,40000) L_0x2be9530/d; +L_0x2be9650/d .functor AND 1, L_0x2be8840, L_0x2be8eb0, C4<1>, C4<1>; +L_0x2be9650 .delay (20000,20000,20000) L_0x2be9650/d; +L_0x2be97f0/d .functor AND 1, L_0x2be9440, L_0x2bd3ec0, C4<1>, C4<1>; +L_0x2be97f0 .delay (20000,20000,20000) L_0x2be97f0/d; +L_0x2be9900/d .functor OR 1, L_0x2be9650, L_0x2be97f0, C4<0>, C4<0>; +L_0x2be9900 .delay (20000,20000,20000) L_0x2be9900/d; +v0x2baa3a0_0 .net "A", 0 0, L_0x2be8840; 1 drivers +v0x2baa460_0 .net "AandB", 0 0, L_0x2be9650; 1 drivers +v0x2baa500_0 .net "AddSubSLTSum", 0 0, L_0x2be9530; 1 drivers +v0x2baa5a0_0 .net "AxorB", 0 0, L_0x2be9440; 1 drivers +v0x2baa650_0 .net "B", 0 0, L_0x2bd3d90; 1 drivers +v0x2baa700_0 .net "BornB", 0 0, L_0x2be8eb0; 1 drivers +v0x2baa7c0_0 .net "CINandAxorB", 0 0, L_0x2be97f0; 1 drivers +v0x2baa860_0 .alias "Command", 2 0, v0x2bc67a0_0; +v0x2baa930_0 .net *"_s3", 0 0, L_0x2be91c0; 1 drivers +v0x2baa9d0_0 .net *"_s5", 0 0, L_0x2be93a0; 1 drivers +v0x2baaad0_0 .net "carryin", 0 0, L_0x2bd3ec0; 1 drivers +v0x2baab70_0 .net "carryout", 0 0, L_0x2be9900; 1 drivers +v0x2baac80_0 .net "nB", 0 0, L_0x2be75f0; 1 drivers +v0x2baad00_0 .net "nCmd2", 0 0, L_0x2be9100; 1 drivers +v0x2baae00_0 .net "subtract", 0 0, L_0x2be9260; 1 drivers +L_0x2be9060 .part v0x2bc78e0_0, 0, 1; +L_0x2be91c0 .part v0x2bc78e0_0, 2, 1; +L_0x2be93a0 .part v0x2bc78e0_0, 0, 1; +S_0x2ba9f30 .scope module, "mux0" "TwoInMux" 3 105, 3 8, S_0x2ba9e40; + .timescale -9 -12; +L_0x2be8c30/d .functor NOT 1, L_0x2be9060, C4<0>, C4<0>, C4<0>; +L_0x2be8c30 .delay (10000,10000,10000) L_0x2be8c30/d; +L_0x2be8cd0/d .functor AND 1, L_0x2bd3d90, L_0x2be8c30, C4<1>, C4<1>; +L_0x2be8cd0 .delay (20000,20000,20000) L_0x2be8cd0/d; +L_0x2be8dc0/d .functor AND 1, L_0x2be75f0, L_0x2be9060, C4<1>, C4<1>; +L_0x2be8dc0 .delay (20000,20000,20000) L_0x2be8dc0/d; +L_0x2be8eb0/d .functor OR 1, L_0x2be8cd0, L_0x2be8dc0, C4<0>, C4<0>; +L_0x2be8eb0 .delay (20000,20000,20000) L_0x2be8eb0/d; +v0x2baa020_0 .net "S", 0 0, L_0x2be9060; 1 drivers +v0x2baa0a0_0 .alias "in0", 0 0, v0x2baa650_0; +v0x2baa120_0 .alias "in1", 0 0, v0x2baac80_0; +v0x2baa1a0_0 .net "nS", 0 0, L_0x2be8c30; 1 drivers +v0x2baa220_0 .net "out0", 0 0, L_0x2be8cd0; 1 drivers +v0x2baa2a0_0 .net "out1", 0 0, L_0x2be8dc0; 1 drivers +v0x2baa320_0 .alias "outfinal", 0 0, v0x2baa700_0; +S_0x2ba8b30 .scope generate, "addbits[26]" "addbits[26]" 3 230, 3 230, S_0x2ba3100; + .timescale -9 -12; +P_0x2ba8548 .param/l "i" 3 230, +C4<011010>; +S_0x2ba8ca0 .scope module, "attempt" "MiddleAddSubSLT" 3 232, 3 89, S_0x2ba8b30; + .timescale -9 -12; +L_0x2bea050/d .functor NOT 1, L_0x2bea680, C4<0>, C4<0>, C4<0>; +L_0x2bea050 .delay (10000,10000,10000) L_0x2bea050/d; +L_0x2beaaa0/d .functor NOT 1, L_0x2beab40, C4<0>, C4<0>, C4<0>; +L_0x2beaaa0 .delay (10000,10000,10000) L_0x2beaaa0/d; +L_0x2beabe0/d .functor AND 1, L_0x2bead20, L_0x2beaaa0, C4<1>, C4<1>; +L_0x2beabe0 .delay (20000,20000,20000) L_0x2beabe0/d; +L_0x2beadc0/d .functor XOR 1, L_0x2bea5e0, L_0x2be8a80, C4<0>, C4<0>; +L_0x2beadc0 .delay (40000,40000,40000) L_0x2beadc0/d; +L_0x2beaeb0/d .functor XOR 1, L_0x2beadc0, L_0x2bea7b0, C4<0>, C4<0>; +L_0x2beaeb0 .delay (40000,40000,40000) L_0x2beaeb0/d; +L_0x2beafa0/d .functor AND 1, L_0x2bea5e0, L_0x2be8a80, C4<1>, C4<1>; +L_0x2beafa0 .delay (20000,20000,20000) L_0x2beafa0/d; +L_0x2beb110/d .functor AND 1, L_0x2beadc0, L_0x2bea7b0, C4<1>, C4<1>; +L_0x2beb110 .delay (20000,20000,20000) L_0x2beb110/d; +L_0x2beb200/d .functor OR 1, L_0x2beafa0, L_0x2beb110, C4<0>, C4<0>; +L_0x2beb200 .delay (20000,20000,20000) L_0x2beb200/d; +v0x2ba9330_0 .net "A", 0 0, L_0x2bea5e0; 1 drivers +v0x2ba93f0_0 .net "AandB", 0 0, L_0x2beafa0; 1 drivers +v0x2ba9490_0 .net "AddSubSLTSum", 0 0, L_0x2beaeb0; 1 drivers +v0x2ba9530_0 .net "AxorB", 0 0, L_0x2beadc0; 1 drivers +v0x2ba95b0_0 .net "B", 0 0, L_0x2bea680; 1 drivers +v0x2ba9660_0 .net "BornB", 0 0, L_0x2be8a80; 1 drivers +v0x2ba9720_0 .net "CINandAxorB", 0 0, L_0x2beb110; 1 drivers +v0x2ba97a0_0 .alias "Command", 2 0, v0x2bc67a0_0; +v0x2ba9820_0 .net *"_s3", 0 0, L_0x2beab40; 1 drivers +v0x2ba98a0_0 .net *"_s5", 0 0, L_0x2bead20; 1 drivers +v0x2ba9940_0 .net "carryin", 0 0, L_0x2bea7b0; 1 drivers +v0x2ba99e0_0 .net "carryout", 0 0, L_0x2beb200; 1 drivers +v0x2ba9a80_0 .net "nB", 0 0, L_0x2bea050; 1 drivers +v0x2ba9b30_0 .net "nCmd2", 0 0, L_0x2beaaa0; 1 drivers +v0x2ba9c30_0 .net "subtract", 0 0, L_0x2beabe0; 1 drivers +L_0x2beaa00 .part v0x2bc78e0_0, 0, 1; +L_0x2beab40 .part v0x2bc78e0_0, 2, 1; +L_0x2bead20 .part v0x2bc78e0_0, 0, 1; +S_0x2ba8d90 .scope module, "mux0" "TwoInMux" 3 105, 3 8, S_0x2ba8ca0; + .timescale -9 -12; +L_0x2bd4230/d .functor NOT 1, L_0x2beaa00, C4<0>, C4<0>, C4<0>; +L_0x2bd4230 .delay (10000,10000,10000) L_0x2bd4230/d; +L_0x2bd42b0/d .functor AND 1, L_0x2bea680, L_0x2bd4230, C4<1>, C4<1>; +L_0x2bd42b0 .delay (20000,20000,20000) L_0x2bd42b0/d; +L_0x2be8970/d .functor AND 1, L_0x2bea050, L_0x2beaa00, C4<1>, C4<1>; +L_0x2be8970 .delay (20000,20000,20000) L_0x2be8970/d; +L_0x2be8a80/d .functor OR 1, L_0x2bd42b0, L_0x2be8970, C4<0>, C4<0>; +L_0x2be8a80 .delay (20000,20000,20000) L_0x2be8a80/d; +v0x2ba8e80_0 .net "S", 0 0, L_0x2beaa00; 1 drivers +v0x2ba8f20_0 .alias "in0", 0 0, v0x2ba95b0_0; +v0x2ba8fc0_0 .alias "in1", 0 0, v0x2ba9a80_0; +v0x2ba9060_0 .net "nS", 0 0, L_0x2bd4230; 1 drivers +v0x2ba9110_0 .net "out0", 0 0, L_0x2bd42b0; 1 drivers +v0x2ba91b0_0 .net "out1", 0 0, L_0x2be8970; 1 drivers +v0x2ba9290_0 .alias "outfinal", 0 0, v0x2ba9660_0; +S_0x2ba7990 .scope generate, "addbits[27]" "addbits[27]" 3 230, 3 230, S_0x2ba3100; + .timescale -9 -12; +P_0x2ba73a8 .param/l "i" 3 230, +C4<011011>; +S_0x2ba7b00 .scope module, "attempt" "MiddleAddSubSLT" 3 232, 3 89, S_0x2ba7990; + .timescale -9 -12; +L_0x2bea850/d .functor NOT 1, L_0x2beb6b0, C4<0>, C4<0>, C4<0>; +L_0x2bea850 .delay (10000,10000,10000) L_0x2bea850/d; +L_0x2bebec0/d .functor NOT 1, L_0x2bebf80, C4<0>, C4<0>, C4<0>; +L_0x2bebec0 .delay (10000,10000,10000) L_0x2bebec0/d; +L_0x2bec020/d .functor AND 1, L_0x2bec160, L_0x2bebec0, C4<1>, C4<1>; +L_0x2bec020 .delay (20000,20000,20000) L_0x2bec020/d; +L_0x2bec200/d .functor XOR 1, L_0x2beb610, L_0x2bebc50, C4<0>, C4<0>; +L_0x2bec200 .delay (40000,40000,40000) L_0x2bec200/d; +L_0x2bec2f0/d .functor XOR 1, L_0x2bec200, L_0x2beb7e0, C4<0>, C4<0>; +L_0x2bec2f0 .delay (40000,40000,40000) L_0x2bec2f0/d; +L_0x2bec410/d .functor AND 1, L_0x2beb610, L_0x2bebc50, C4<1>, C4<1>; +L_0x2bec410 .delay (20000,20000,20000) L_0x2bec410/d; +L_0x2bec5b0/d .functor AND 1, L_0x2bec200, L_0x2beb7e0, C4<1>, C4<1>; +L_0x2bec5b0 .delay (20000,20000,20000) L_0x2bec5b0/d; +L_0x2bec6c0/d .functor OR 1, L_0x2bec410, L_0x2bec5b0, C4<0>, C4<0>; +L_0x2bec6c0 .delay (20000,20000,20000) L_0x2bec6c0/d; +v0x2ba8190_0 .net "A", 0 0, L_0x2beb610; 1 drivers +v0x2ba8250_0 .net "AandB", 0 0, L_0x2bec410; 1 drivers +v0x2ba82f0_0 .net "AddSubSLTSum", 0 0, L_0x2bec2f0; 1 drivers +v0x2ba8390_0 .net "AxorB", 0 0, L_0x2bec200; 1 drivers +v0x2ba8410_0 .net "B", 0 0, L_0x2beb6b0; 1 drivers +v0x2ba84c0_0 .net "BornB", 0 0, L_0x2bebc50; 1 drivers +v0x2ba8580_0 .net "CINandAxorB", 0 0, L_0x2bec5b0; 1 drivers +v0x2ba8600_0 .alias "Command", 2 0, v0x2bc67a0_0; +v0x2ba8680_0 .net *"_s3", 0 0, L_0x2bebf80; 1 drivers +v0x2ba8700_0 .net *"_s5", 0 0, L_0x2bec160; 1 drivers +v0x2ba87a0_0 .net "carryin", 0 0, L_0x2beb7e0; 1 drivers +v0x2ba8840_0 .net "carryout", 0 0, L_0x2bec6c0; 1 drivers +v0x2ba88e0_0 .net "nB", 0 0, L_0x2bea850; 1 drivers +v0x2ba8990_0 .net "nCmd2", 0 0, L_0x2bebec0; 1 drivers +v0x2ba8a90_0 .net "subtract", 0 0, L_0x2bec020; 1 drivers +L_0x2bebe20 .part v0x2bc78e0_0, 0, 1; +L_0x2bebf80 .part v0x2bc78e0_0, 2, 1; +L_0x2bec160 .part v0x2bc78e0_0, 0, 1; +S_0x2ba7bf0 .scope module, "mux0" "TwoInMux" 3 105, 3 8, S_0x2ba7b00; + .timescale -9 -12; +L_0x2beba10/d .functor NOT 1, L_0x2bebe20, C4<0>, C4<0>, C4<0>; +L_0x2beba10 .delay (10000,10000,10000) L_0x2beba10/d; +L_0x2beba70/d .functor AND 1, L_0x2beb6b0, L_0x2beba10, C4<1>, C4<1>; +L_0x2beba70 .delay (20000,20000,20000) L_0x2beba70/d; +L_0x2bebb60/d .functor AND 1, L_0x2bea850, L_0x2bebe20, C4<1>, C4<1>; +L_0x2bebb60 .delay (20000,20000,20000) L_0x2bebb60/d; +L_0x2bebc50/d .functor OR 1, L_0x2beba70, L_0x2bebb60, C4<0>, C4<0>; +L_0x2bebc50 .delay (20000,20000,20000) L_0x2bebc50/d; +v0x2ba7ce0_0 .net "S", 0 0, L_0x2bebe20; 1 drivers +v0x2ba7d80_0 .alias "in0", 0 0, v0x2ba8410_0; +v0x2ba7e20_0 .alias "in1", 0 0, v0x2ba88e0_0; +v0x2ba7ec0_0 .net "nS", 0 0, L_0x2beba10; 1 drivers +v0x2ba7f70_0 .net "out0", 0 0, L_0x2beba70; 1 drivers +v0x2ba8010_0 .net "out1", 0 0, L_0x2bebb60; 1 drivers +v0x2ba80f0_0 .alias "outfinal", 0 0, v0x2ba84c0_0; +S_0x2ba67f0 .scope generate, "addbits[28]" "addbits[28]" 3 230, 3 230, S_0x2ba3100; + .timescale -9 -12; +P_0x2ba6208 .param/l "i" 3 230, +C4<011100>; +S_0x2ba6960 .scope module, "attempt" "MiddleAddSubSLT" 3 232, 3 89, S_0x2ba67f0; + .timescale -9 -12; +L_0x2beb880/d .functor NOT 1, L_0x2becb90, C4<0>, C4<0>, C4<0>; +L_0x2beb880 .delay (10000,10000,10000) L_0x2beb880/d; +L_0x2bed3d0/d .functor NOT 1, L_0x2bed470, C4<0>, C4<0>, C4<0>; +L_0x2bed3d0 .delay (10000,10000,10000) L_0x2bed3d0/d; +L_0x2bed510/d .functor AND 1, L_0x2bed650, L_0x2bed3d0, C4<1>, C4<1>; +L_0x2bed510 .delay (20000,20000,20000) L_0x2bed510/d; +L_0x2bed6f0/d .functor XOR 1, L_0x2becaf0, L_0x2bed1a0, C4<0>, C4<0>; +L_0x2bed6f0 .delay (40000,40000,40000) L_0x2bed6f0/d; +L_0x2bed810/d .functor XOR 1, L_0x2bed6f0, L_0x2beccc0, C4<0>, C4<0>; +L_0x2bed810 .delay (40000,40000,40000) L_0x2bed810/d; +L_0x2bed930/d .functor AND 1, L_0x2becaf0, L_0x2bed1a0, C4<1>, C4<1>; +L_0x2bed930 .delay (20000,20000,20000) L_0x2bed930/d; +L_0x2bedad0/d .functor AND 1, L_0x2bed6f0, L_0x2beccc0, C4<1>, C4<1>; +L_0x2bedad0 .delay (20000,20000,20000) L_0x2bedad0/d; +L_0x2bedbc0/d .functor OR 1, L_0x2bed930, L_0x2bedad0, C4<0>, C4<0>; +L_0x2bedbc0 .delay (20000,20000,20000) L_0x2bedbc0/d; +v0x2ba6ff0_0 .net "A", 0 0, L_0x2becaf0; 1 drivers +v0x2ba70b0_0 .net "AandB", 0 0, L_0x2bed930; 1 drivers +v0x2ba7150_0 .net "AddSubSLTSum", 0 0, L_0x2bed810; 1 drivers +v0x2ba71f0_0 .net "AxorB", 0 0, L_0x2bed6f0; 1 drivers +v0x2ba7270_0 .net "B", 0 0, L_0x2becb90; 1 drivers +v0x2ba7320_0 .net "BornB", 0 0, L_0x2bed1a0; 1 drivers +v0x2ba73e0_0 .net "CINandAxorB", 0 0, L_0x2bedad0; 1 drivers +v0x2ba7460_0 .alias "Command", 2 0, v0x2bc67a0_0; +v0x2ba74e0_0 .net *"_s3", 0 0, L_0x2bed470; 1 drivers +v0x2ba7560_0 .net *"_s5", 0 0, L_0x2bed650; 1 drivers +v0x2ba7600_0 .net "carryin", 0 0, L_0x2beccc0; 1 drivers +v0x2ba76a0_0 .net "carryout", 0 0, L_0x2bedbc0; 1 drivers +v0x2ba7740_0 .net "nB", 0 0, L_0x2beb880; 1 drivers +v0x2ba77f0_0 .net "nCmd2", 0 0, L_0x2bed3d0; 1 drivers +v0x2ba78f0_0 .net "subtract", 0 0, L_0x2bed510; 1 drivers +L_0x2bed330 .part v0x2bc78e0_0, 0, 1; +L_0x2bed470 .part v0x2bc78e0_0, 2, 1; +L_0x2bed650 .part v0x2bc78e0_0, 0, 1; +S_0x2ba6a50 .scope module, "mux0" "TwoInMux" 3 105, 3 8, S_0x2ba6960; + .timescale -9 -12; +L_0x2becf20/d .functor NOT 1, L_0x2bed330, C4<0>, C4<0>, C4<0>; +L_0x2becf20 .delay (10000,10000,10000) L_0x2becf20/d; +L_0x2becfc0/d .functor AND 1, L_0x2becb90, L_0x2becf20, C4<1>, C4<1>; +L_0x2becfc0 .delay (20000,20000,20000) L_0x2becfc0/d; +L_0x2bed0b0/d .functor AND 1, L_0x2beb880, L_0x2bed330, C4<1>, C4<1>; +L_0x2bed0b0 .delay (20000,20000,20000) L_0x2bed0b0/d; +L_0x2bed1a0/d .functor OR 1, L_0x2becfc0, L_0x2bed0b0, C4<0>, C4<0>; +L_0x2bed1a0 .delay (20000,20000,20000) L_0x2bed1a0/d; +v0x2ba6b40_0 .net "S", 0 0, L_0x2bed330; 1 drivers +v0x2ba6be0_0 .alias "in0", 0 0, v0x2ba7270_0; +v0x2ba6c80_0 .alias "in1", 0 0, v0x2ba7740_0; +v0x2ba6d20_0 .net "nS", 0 0, L_0x2becf20; 1 drivers +v0x2ba6dd0_0 .net "out0", 0 0, L_0x2becfc0; 1 drivers +v0x2ba6e70_0 .net "out1", 0 0, L_0x2bed0b0; 1 drivers +v0x2ba6f50_0 .alias "outfinal", 0 0, v0x2ba7320_0; +S_0x2ba5650 .scope generate, "addbits[29]" "addbits[29]" 3 230, 3 230, S_0x2ba3100; + .timescale -9 -12; +P_0x2ba5068 .param/l "i" 3 230, +C4<011101>; +S_0x2ba57c0 .scope module, "attempt" "MiddleAddSubSLT" 3 232, 3 89, S_0x2ba5650; + .timescale -9 -12; +L_0x2becd60/d .functor NOT 1, L_0x2bd95a0, C4<0>, C4<0>, C4<0>; +L_0x2becd60 .delay (10000,10000,10000) L_0x2becd60/d; +L_0x2bee8a0/d .functor NOT 1, L_0x2bee960, C4<0>, C4<0>, C4<0>; +L_0x2bee8a0 .delay (10000,10000,10000) L_0x2bee8a0/d; +L_0x2beea00/d .functor AND 1, L_0x2beeb40, L_0x2bee8a0, C4<1>, C4<1>; +L_0x2beea00 .delay (20000,20000,20000) L_0x2beea00/d; +L_0x2beebe0/d .functor XOR 1, L_0x2bee360, L_0x2bee670, C4<0>, C4<0>; +L_0x2beebe0 .delay (40000,40000,40000) L_0x2beebe0/d; +L_0x2beed00/d .functor XOR 1, L_0x2beebe0, L_0x2bd96d0, C4<0>, C4<0>; +L_0x2beed00 .delay (40000,40000,40000) L_0x2beed00/d; +L_0x2beee20/d .functor AND 1, L_0x2bee360, L_0x2bee670, C4<1>, C4<1>; +L_0x2beee20 .delay (20000,20000,20000) L_0x2beee20/d; +L_0x2beefc0/d .functor AND 1, L_0x2beebe0, L_0x2bd96d0, C4<1>, C4<1>; +L_0x2beefc0 .delay (20000,20000,20000) L_0x2beefc0/d; +L_0x2bef0b0/d .functor OR 1, L_0x2beee20, L_0x2beefc0, C4<0>, C4<0>; +L_0x2bef0b0 .delay (20000,20000,20000) L_0x2bef0b0/d; +v0x2ba5e50_0 .net "A", 0 0, L_0x2bee360; 1 drivers +v0x2ba5f10_0 .net "AandB", 0 0, L_0x2beee20; 1 drivers +v0x2ba5fb0_0 .net "AddSubSLTSum", 0 0, L_0x2beed00; 1 drivers +v0x2ba6050_0 .net "AxorB", 0 0, L_0x2beebe0; 1 drivers +v0x2ba60d0_0 .net "B", 0 0, L_0x2bd95a0; 1 drivers +v0x2ba6180_0 .net "BornB", 0 0, L_0x2bee670; 1 drivers +v0x2ba6240_0 .net "CINandAxorB", 0 0, L_0x2beefc0; 1 drivers +v0x2ba62c0_0 .alias "Command", 2 0, v0x2bc67a0_0; +v0x2ba6340_0 .net *"_s3", 0 0, L_0x2bee960; 1 drivers +v0x2ba63c0_0 .net *"_s5", 0 0, L_0x2beeb40; 1 drivers +v0x2ba6460_0 .net "carryin", 0 0, L_0x2bd96d0; 1 drivers +v0x2ba6500_0 .net "carryout", 0 0, L_0x2bef0b0; 1 drivers +v0x2ba65a0_0 .net "nB", 0 0, L_0x2becd60; 1 drivers +v0x2ba6650_0 .net "nCmd2", 0 0, L_0x2bee8a0; 1 drivers +v0x2ba6750_0 .net "subtract", 0 0, L_0x2beea00; 1 drivers +L_0x2bee800 .part v0x2bc78e0_0, 0, 1; +L_0x2bee960 .part v0x2bc78e0_0, 2, 1; +L_0x2beeb40 .part v0x2bc78e0_0, 0, 1; +S_0x2ba58b0 .scope module, "mux0" "TwoInMux" 3 105, 3 8, S_0x2ba57c0; + .timescale -9 -12; +L_0x2becec0/d .functor NOT 1, L_0x2bee800, C4<0>, C4<0>, C4<0>; +L_0x2becec0 .delay (10000,10000,10000) L_0x2becec0/d; +L_0x2bee490/d .functor AND 1, L_0x2bd95a0, L_0x2becec0, C4<1>, C4<1>; +L_0x2bee490 .delay (20000,20000,20000) L_0x2bee490/d; +L_0x2bee580/d .functor AND 1, L_0x2becd60, L_0x2bee800, C4<1>, C4<1>; +L_0x2bee580 .delay (20000,20000,20000) L_0x2bee580/d; +L_0x2bee670/d .functor OR 1, L_0x2bee490, L_0x2bee580, C4<0>, C4<0>; +L_0x2bee670 .delay (20000,20000,20000) L_0x2bee670/d; +v0x2ba59a0_0 .net "S", 0 0, L_0x2bee800; 1 drivers +v0x2ba5a40_0 .alias "in0", 0 0, v0x2ba60d0_0; +v0x2ba5ae0_0 .alias "in1", 0 0, v0x2ba65a0_0; +v0x2ba5b80_0 .net "nS", 0 0, L_0x2becec0; 1 drivers +v0x2ba5c30_0 .net "out0", 0 0, L_0x2bee490; 1 drivers +v0x2ba5cd0_0 .net "out1", 0 0, L_0x2bee580; 1 drivers +v0x2ba5db0_0 .alias "outfinal", 0 0, v0x2ba6180_0; +S_0x2ba44b0 .scope generate, "addbits[30]" "addbits[30]" 3 230, 3 230, S_0x2ba3100; + .timescale -9 -12; +P_0x2ba3df8 .param/l "i" 3 230, +C4<011110>; +S_0x2ba4620 .scope module, "attempt" "MiddleAddSubSLT" 3 232, 3 89, S_0x2ba44b0; + .timescale -9 -12; +L_0x2befc40/d .functor NOT 1, L_0x2bef850, C4<0>, C4<0>, C4<0>; +L_0x2befc40 .delay (10000,10000,10000) L_0x2befc40/d; +L_0x2bf01a0/d .functor NOT 1, L_0x2bf0260, C4<0>, C4<0>, C4<0>; +L_0x2bf01a0 .delay (10000,10000,10000) L_0x2bf01a0/d; +L_0x2bf0300/d .functor AND 1, L_0x2bf0440, L_0x2bf01a0, C4<1>, C4<1>; +L_0x2bf0300 .delay (20000,20000,20000) L_0x2bf0300/d; +L_0x2bf04e0/d .functor XOR 1, L_0x2bef7b0, L_0x2beff30, C4<0>, C4<0>; +L_0x2bf04e0 .delay (40000,40000,40000) L_0x2bf04e0/d; +L_0x2bf05d0/d .functor XOR 1, L_0x2bf04e0, L_0x2bef980, C4<0>, C4<0>; +L_0x2bf05d0 .delay (40000,40000,40000) L_0x2bf05d0/d; +L_0x2bf06f0/d .functor AND 1, L_0x2bef7b0, L_0x2beff30, C4<1>, C4<1>; +L_0x2bf06f0 .delay (20000,20000,20000) L_0x2bf06f0/d; +L_0x2bf0890/d .functor AND 1, L_0x2bf04e0, L_0x2bef980, C4<1>, C4<1>; +L_0x2bf0890 .delay (20000,20000,20000) L_0x2bf0890/d; +L_0x2bf09a0/d .functor OR 1, L_0x2bf06f0, L_0x2bf0890, C4<0>, C4<0>; +L_0x2bf09a0 .delay (20000,20000,20000) L_0x2bf09a0/d; +v0x2ba4cb0_0 .net "A", 0 0, L_0x2bef7b0; 1 drivers +v0x2ba4d70_0 .net "AandB", 0 0, L_0x2bf06f0; 1 drivers +v0x2ba4e10_0 .net "AddSubSLTSum", 0 0, L_0x2bf05d0; 1 drivers +v0x2ba4eb0_0 .net "AxorB", 0 0, L_0x2bf04e0; 1 drivers +v0x2ba4f30_0 .net "B", 0 0, L_0x2bef850; 1 drivers +v0x2ba4fe0_0 .net "BornB", 0 0, L_0x2beff30; 1 drivers +v0x2ba50a0_0 .net "CINandAxorB", 0 0, L_0x2bf0890; 1 drivers +v0x2ba5120_0 .alias "Command", 2 0, v0x2bc67a0_0; +v0x2ba51a0_0 .net *"_s3", 0 0, L_0x2bf0260; 1 drivers +v0x2ba5220_0 .net *"_s5", 0 0, L_0x2bf0440; 1 drivers +v0x2ba52c0_0 .net "carryin", 0 0, L_0x2bef980; 1 drivers +v0x2ba5360_0 .net "carryout", 0 0, L_0x2bf09a0; 1 drivers +v0x2ba5400_0 .net "nB", 0 0, L_0x2befc40; 1 drivers +v0x2ba54b0_0 .net "nCmd2", 0 0, L_0x2bf01a0; 1 drivers +v0x2ba55b0_0 .net "subtract", 0 0, L_0x2bf0300; 1 drivers +L_0x2bf0100 .part v0x2bc78e0_0, 0, 1; +L_0x2bf0260 .part v0x2bc78e0_0, 2, 1; +L_0x2bf0440 .part v0x2bc78e0_0, 0, 1; +S_0x2ba4710 .scope module, "mux0" "TwoInMux" 3 105, 3 8, S_0x2ba4620; + .timescale -9 -12; +L_0x2befcf0/d .functor NOT 1, L_0x2bf0100, C4<0>, C4<0>, C4<0>; +L_0x2befcf0 .delay (10000,10000,10000) L_0x2befcf0/d; +L_0x2befd50/d .functor AND 1, L_0x2bef850, L_0x2befcf0, C4<1>, C4<1>; +L_0x2befd50 .delay (20000,20000,20000) L_0x2befd50/d; +L_0x2befe40/d .functor AND 1, L_0x2befc40, L_0x2bf0100, C4<1>, C4<1>; +L_0x2befe40 .delay (20000,20000,20000) L_0x2befe40/d; +L_0x2beff30/d .functor OR 1, L_0x2befd50, L_0x2befe40, C4<0>, C4<0>; +L_0x2beff30 .delay (20000,20000,20000) L_0x2beff30/d; +v0x2ba4800_0 .net "S", 0 0, L_0x2bf0100; 1 drivers +v0x2ba48a0_0 .alias "in0", 0 0, v0x2ba4f30_0; +v0x2ba4940_0 .alias "in1", 0 0, v0x2ba5400_0; +v0x2ba49e0_0 .net "nS", 0 0, L_0x2befcf0; 1 drivers +v0x2ba4a90_0 .net "out0", 0 0, L_0x2befd50; 1 drivers +v0x2ba4b30_0 .net "out1", 0 0, L_0x2befe40; 1 drivers +v0x2ba4c10_0 .alias "outfinal", 0 0, v0x2ba4fe0_0; +S_0x2ba3270 .scope generate, "addbits[31]" "addbits[31]" 3 230, 3 230, S_0x2ba3100; + .timescale -9 -12; +P_0x2ba3368 .param/l "i" 3 230, +C4<011111>; +S_0x2ba33e0 .scope module, "attempt" "MiddleAddSubSLT" 3 232, 3 89, S_0x2ba3270; + .timescale -9 -12; +L_0x2befa20/d .functor NOT 1, L_0x2bf0e70, C4<0>, C4<0>, C4<0>; +L_0x2befa20 .delay (10000,10000,10000) L_0x2befa20/d; +L_0x2bf16a0/d .functor NOT 1, L_0x2bf1740, C4<0>, C4<0>, C4<0>; +L_0x2bf16a0 .delay (10000,10000,10000) L_0x2bf16a0/d; +L_0x2bf17e0/d .functor AND 1, L_0x2bf1920, L_0x2bf16a0, C4<1>, C4<1>; +L_0x2bf17e0 .delay (20000,20000,20000) L_0x2bf17e0/d; +L_0x2bf19c0/d .functor XOR 1, L_0x2bf0dd0, L_0x2bf1470, C4<0>, C4<0>; +L_0x2bf19c0 .delay (40000,40000,40000) L_0x2bf19c0/d; +L_0x2bf1ae0/d .functor XOR 1, L_0x2bf19c0, L_0x2bf0fa0, C4<0>, C4<0>; +L_0x2bf1ae0 .delay (40000,40000,40000) L_0x2bf1ae0/d; +L_0x2bf1c00/d .functor AND 1, L_0x2bf0dd0, L_0x2bf1470, C4<1>, C4<1>; +L_0x2bf1c00 .delay (20000,20000,20000) L_0x2bf1c00/d; +L_0x2bf1da0/d .functor AND 1, L_0x2bf19c0, L_0x2bf0fa0, C4<1>, C4<1>; +L_0x2bf1da0 .delay (20000,20000,20000) L_0x2bf1da0/d; +L_0x2bf1e90/d .functor OR 1, L_0x2bf1c00, L_0x2bf1da0, C4<0>, C4<0>; +L_0x2bf1e90 .delay (20000,20000,20000) L_0x2bf1e90/d; +v0x2ba3a40_0 .net "A", 0 0, L_0x2bf0dd0; 1 drivers +v0x2ba3b00_0 .net "AandB", 0 0, L_0x2bf1c00; 1 drivers +v0x2ba3ba0_0 .net "AddSubSLTSum", 0 0, L_0x2bf1ae0; 1 drivers +v0x2ba3c40_0 .net "AxorB", 0 0, L_0x2bf19c0; 1 drivers +v0x2ba3cc0_0 .net "B", 0 0, L_0x2bf0e70; 1 drivers +v0x2ba3d70_0 .net "BornB", 0 0, L_0x2bf1470; 1 drivers +v0x2ba3e30_0 .net "CINandAxorB", 0 0, L_0x2bf1da0; 1 drivers +v0x2ba3eb0_0 .alias "Command", 2 0, v0x2bc67a0_0; +v0x2ba3f30_0 .net *"_s3", 0 0, L_0x2bf1740; 1 drivers +v0x2ba3fb0_0 .net *"_s5", 0 0, L_0x2bf1920; 1 drivers +v0x2ba40b0_0 .net "carryin", 0 0, L_0x2bf0fa0; 1 drivers +v0x2ba4150_0 .net "carryout", 0 0, L_0x2bf1e90; 1 drivers +v0x2ba4260_0 .net "nB", 0 0, L_0x2befa20; 1 drivers +v0x2ba4310_0 .net "nCmd2", 0 0, L_0x2bf16a0; 1 drivers +v0x2ba4410_0 .net "subtract", 0 0, L_0x2bf17e0; 1 drivers +L_0x2bf1600 .part v0x2bc78e0_0, 0, 1; +L_0x2bf1740 .part v0x2bc78e0_0, 2, 1; +L_0x2bf1920 .part v0x2bc78e0_0, 0, 1; +S_0x2ba34d0 .scope module, "mux0" "TwoInMux" 3 105, 3 8, S_0x2ba33e0; + .timescale -9 -12; +L_0x2befb80/d .functor NOT 1, L_0x2bf1600, C4<0>, C4<0>, C4<0>; +L_0x2befb80 .delay (10000,10000,10000) L_0x2befb80/d; +L_0x2bf1290/d .functor AND 1, L_0x2bf0e70, L_0x2befb80, C4<1>, C4<1>; +L_0x2bf1290 .delay (20000,20000,20000) L_0x2bf1290/d; +L_0x2bf1380/d .functor AND 1, L_0x2befa20, L_0x2bf1600, C4<1>, C4<1>; +L_0x2bf1380 .delay (20000,20000,20000) L_0x2bf1380/d; +L_0x2bf1470/d .functor OR 1, L_0x2bf1290, L_0x2bf1380, C4<0>, C4<0>; +L_0x2bf1470 .delay (20000,20000,20000) L_0x2bf1470/d; +v0x2ba35c0_0 .net "S", 0 0, L_0x2bf1600; 1 drivers +v0x2ba3660_0 .alias "in0", 0 0, v0x2ba3cc0_0; +v0x2ba3700_0 .alias "in1", 0 0, v0x2ba4260_0; +v0x2ba37a0_0 .net "nS", 0 0, L_0x2befb80; 1 drivers +v0x2ba3820_0 .net "out0", 0 0, L_0x2bf1290; 1 drivers +v0x2ba38c0_0 .net "out1", 0 0, L_0x2bf1380; 1 drivers +v0x2ba39a0_0 .alias "outfinal", 0 0, v0x2ba3d70_0; +S_0x2b8b740 .scope module, "trial1" "AndNand32" 2 143, 3 154, S_0x270e6d0; + .timescale -9 -12; +P_0x2b8b138 .param/l "size" 3 161, +C4<0100000>; +v0x2ba2f00_0 .alias "A", 31 0, v0x2bc6580_0; +v0x2ba2f80_0 .alias "AndNandOut", 31 0, v0x2bc77e0_0; +v0x2ba3000_0 .alias "B", 31 0, v0x2bc66a0_0; +v0x2ba3080_0 .alias "Command", 2 0, v0x2bc67a0_0; +L_0x2bf56a0 .part/pv L_0x2bf5430, 1, 1, 32; +L_0x2bf57f0 .part v0x2bc7660_0, 1, 1; +L_0x2bf5890 .part v0x2bc7860_0, 1, 1; +L_0x2bf6150 .part/pv L_0x2bf5ee0, 2, 1, 32; +L_0x2bf61f0 .part v0x2bc7660_0, 2, 1; +L_0x2bf6290 .part v0x2bc7860_0, 2, 1; +L_0x2bf6bc0 .part/pv L_0x2bf6950, 3, 1, 32; +L_0x2bf6c60 .part v0x2bc7660_0, 3, 1; +L_0x2bf6d50 .part v0x2bc7860_0, 3, 1; +L_0x2bf7620 .part/pv L_0x2bf73b0, 4, 1, 32; +L_0x2bf7720 .part v0x2bc7660_0, 4, 1; +L_0x2bf77c0 .part v0x2bc7860_0, 4, 1; +L_0x2bf8090 .part/pv L_0x2bf7e20, 5, 1, 32; +L_0x2bf8240 .part v0x2bc7660_0, 5, 1; +L_0x2bf82e0 .part v0x2bc7860_0, 5, 1; +L_0x2bf8bf0 .part/pv L_0x2bf8980, 6, 1, 32; +L_0x2bf8c90 .part v0x2bc7660_0, 6, 1; +L_0x2bf8d30 .part v0x2bc7860_0, 6, 1; +L_0x2bf9660 .part/pv L_0x2bf93f0, 7, 1, 32; +L_0x2bf9700 .part v0x2bc7660_0, 7, 1; +L_0x2bf8e20 .part v0x2bc7860_0, 7, 1; +L_0x2bfa0c0 .part/pv L_0x2bf9e50, 8, 1, 32; +L_0x2bf97a0 .part v0x2bc7660_0, 8, 1; +L_0x2bfa220 .part v0x2bc7860_0, 8, 1; +L_0x2bfab40 .part/pv L_0x2bfa8d0, 9, 1, 32; +L_0x2bfabe0 .part v0x2bc7660_0, 9, 1; +L_0x2bfa310 .part v0x2bc7860_0, 9, 1; +L_0x2bfb5b0 .part/pv L_0x2bfb340, 10, 1, 32; +L_0x2bfac80 .part v0x2bc7660_0, 10, 1; +L_0x2bfb740 .part v0x2bc7860_0, 10, 1; +L_0x2bfc020 .part/pv L_0x2bfbdb0, 11, 1, 32; +L_0x2bfc0c0 .part v0x2bc7660_0, 11, 1; +L_0x2bfb830 .part v0x2bc7860_0, 11, 1; +L_0x2bfca90 .part/pv L_0x2bfc820, 12, 1, 32; +L_0x2bfc160 .part v0x2bc7660_0, 12, 1; +L_0x2bfcc50 .part v0x2bc7860_0, 12, 1; +L_0x2bfd510 .part/pv L_0x2bfd2a0, 13, 1, 32; +L_0x2bf8130 .part v0x2bc7660_0, 13, 1; +L_0x2bfccf0 .part v0x2bc7860_0, 13, 1; +L_0x2bfe080 .part/pv L_0x2bfde10, 14, 1, 32; +L_0x2bfd7c0 .part v0x2bc7660_0, 14, 1; +L_0x2bfd860 .part v0x2bc7860_0, 14, 1; +L_0x2bfeaf0 .part/pv L_0x2bfe880, 15, 1, 32; +L_0x2bfeb90 .part v0x2bc7660_0, 15, 1; +L_0x2bfe2c0 .part v0x2bc7860_0, 15, 1; +L_0x2bff560 .part/pv L_0x2bff2f0, 16, 1, 32; +L_0x2bfec30 .part v0x2bc7660_0, 16, 1; +L_0x2bfecd0 .part v0x2bc7860_0, 16, 1; +L_0x2bfffe0 .part/pv L_0x2bffd70, 17, 1, 32; +L_0x2c00080 .part v0x2bc7660_0, 17, 1; +L_0x2bff7d0 .part v0x2bc7860_0, 17, 1; +L_0x2c00a40 .part/pv L_0x2c007d0, 18, 1, 32; +L_0x2c00120 .part v0x2bc7660_0, 18, 1; +L_0x2c001c0 .part v0x2bc7860_0, 18, 1; +L_0x2c014c0 .part/pv L_0x2c01250, 19, 1, 32; +L_0x2c01560 .part v0x2bc7660_0, 19, 1; +L_0x2c00ae0 .part v0x2bc7860_0, 19, 1; +L_0x2c01f20 .part/pv L_0x2c01cb0, 20, 1, 32; +L_0x2c01600 .part v0x2bc7660_0, 20, 1; +L_0x2c016a0 .part v0x2bc7860_0, 20, 1; +L_0x2c02990 .part/pv L_0x2c02720, 21, 1, 32; +L_0x2c02a30 .part v0x2bc7660_0, 21, 1; +L_0x2c01fc0 .part v0x2bc7860_0, 21, 1; +L_0x2c03400 .part/pv L_0x2c03190, 22, 1, 32; +L_0x2c02ad0 .part v0x2bc7660_0, 22, 1; +L_0x2c02b70 .part v0x2bc7860_0, 22, 1; +L_0x2c03e80 .part/pv L_0x2c03c10, 23, 1, 32; +L_0x2c03f20 .part v0x2bc7660_0, 23, 1; +L_0x2c034a0 .part v0x2bc7860_0, 23, 1; +L_0x2c048e0 .part/pv L_0x2c04670, 24, 1, 32; +L_0x2c03fc0 .part v0x2bc7660_0, 24, 1; +L_0x2c04060 .part v0x2bc7860_0, 24, 1; +L_0x2c05350 .part/pv L_0x2c050e0, 25, 1, 32; +L_0x2c053f0 .part v0x2bc7660_0, 25, 1; +L_0x2bea340 .part v0x2bc7860_0, 25, 1; +L_0x2c06550 .part/pv L_0x2be9ea0, 26, 1, 32; +L_0x2bea0e0 .part v0x2bc7660_0, 26, 1; +L_0x2bea180 .part v0x2bc7860_0, 26, 1; +L_0x2c06ee0 .part/pv L_0x2c06cb0, 27, 1, 32; +L_0x2c06f80 .part v0x2bc7660_0, 27, 1; +L_0x2c065f0 .part v0x2bc7860_0, 27, 1; +L_0x2c07890 .part/pv L_0x2c07660, 28, 1, 32; +L_0x2c07020 .part v0x2bc7660_0, 28, 1; +L_0x2c070c0 .part v0x2bc7860_0, 28, 1; +L_0x2c08250 .part/pv L_0x2c08020, 29, 1, 32; +L_0x2bfd5b0 .part v0x2bc7660_0, 29, 1; +L_0x2bfd650 .part v0x2bc7860_0, 29, 1; +L_0x2c08e10 .part/pv L_0x2c08be0, 30, 1, 32; +L_0x2c08700 .part v0x2bc7660_0, 30, 1; +L_0x2c087a0 .part v0x2bc7860_0, 30, 1; +L_0x2c097c0 .part/pv L_0x2c09590, 31, 1, 32; +L_0x2c09860 .part v0x2bc7660_0, 31, 1; +L_0x2c08eb0 .part v0x2bc7860_0, 31, 1; +L_0x2c0a170 .part/pv L_0x2c09f40, 0, 1, 32; +L_0x2c09900 .part v0x2bc7660_0, 0, 1; +L_0x2c099a0 .part v0x2bc7860_0, 0, 1; +S_0x2ba24d0 .scope module, "attempt2" "AndNand" 3 165, 3 48, S_0x2b8b740; + .timescale -9 -12; +L_0x2c08fa0/d .functor NAND 1, L_0x2c09900, L_0x2c099a0, C4<1>, C4<1>; +L_0x2c08fa0 .delay (10000,10000,10000) L_0x2c08fa0/d; +L_0x2c09100/d .functor NOT 1, L_0x2c08fa0, C4<0>, C4<0>, C4<0>; +L_0x2c09100 .delay (10000,10000,10000) L_0x2c09100/d; +v0x2ba2af0_0 .net "A", 0 0, L_0x2c09900; 1 drivers +v0x2ba2bb0_0 .net "AandB", 0 0, L_0x2c09100; 1 drivers +v0x2ba2c30_0 .net "AnandB", 0 0, L_0x2c08fa0; 1 drivers +v0x2ba2ce0_0 .net "AndNandOut", 0 0, L_0x2c09f40; 1 drivers +v0x2ba2dc0_0 .net "B", 0 0, L_0x2c099a0; 1 drivers +v0x2ba2e40_0 .alias "Command", 2 0, v0x2bc67a0_0; +L_0x2c0a0d0 .part v0x2bc78e0_0, 0, 1; +S_0x2ba25c0 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0x2ba24d0; + .timescale -9 -12; +L_0x2c09c80/d .functor NOT 1, L_0x2c0a0d0, C4<0>, C4<0>, C4<0>; +L_0x2c09c80 .delay (10000,10000,10000) L_0x2c09c80/d; +L_0x2c09d20/d .functor AND 1, L_0x2c09100, L_0x2c09c80, C4<1>, C4<1>; +L_0x2c09d20 .delay (20000,20000,20000) L_0x2c09d20/d; +L_0x2c09e10/d .functor AND 1, L_0x2c08fa0, L_0x2c0a0d0, C4<1>, C4<1>; +L_0x2c09e10 .delay (20000,20000,20000) L_0x2c09e10/d; +L_0x2c09f40/d .functor OR 1, L_0x2c09d20, L_0x2c09e10, C4<0>, C4<0>; +L_0x2c09f40 .delay (20000,20000,20000) L_0x2c09f40/d; +v0x2ba26b0_0 .net "S", 0 0, L_0x2c0a0d0; 1 drivers +v0x2ba2730_0 .alias "in0", 0 0, v0x2ba2bb0_0; +v0x2ba27b0_0 .alias "in1", 0 0, v0x2ba2c30_0; +v0x2ba2850_0 .net "nS", 0 0, L_0x2c09c80; 1 drivers +v0x2ba28d0_0 .net "out0", 0 0, L_0x2c09d20; 1 drivers +v0x2ba2970_0 .net "out1", 0 0, L_0x2c09e10; 1 drivers +v0x2ba2a50_0 .alias "outfinal", 0 0, v0x2ba2ce0_0; +S_0x2ba1910 .scope generate, "andbits[1]" "andbits[1]" 3 169, 3 169, S_0x2b8b740; + .timescale -9 -12; +P_0x2ba1a08 .param/l "i" 3 169, +C4<01>; +S_0x2ba1a80 .scope module, "attempt" "AndNand" 3 171, 3 48, S_0x2ba1910; + .timescale -9 -12; +L_0x2bf4f20/d .functor NAND 1, L_0x2bf57f0, L_0x2bf5890, C4<1>, C4<1>; +L_0x2bf4f20 .delay (10000,10000,10000) L_0x2bf4f20/d; +L_0x2bf4fe0/d .functor NOT 1, L_0x2bf4f20, C4<0>, C4<0>, C4<0>; +L_0x2bf4fe0 .delay (10000,10000,10000) L_0x2bf4fe0/d; +v0x2ba20c0_0 .net "A", 0 0, L_0x2bf57f0; 1 drivers +v0x2ba2180_0 .net "AandB", 0 0, L_0x2bf4fe0; 1 drivers +v0x2ba2200_0 .net "AnandB", 0 0, L_0x2bf4f20; 1 drivers +v0x2ba22b0_0 .net "AndNandOut", 0 0, L_0x2bf5430; 1 drivers +v0x2ba2390_0 .net "B", 0 0, L_0x2bf5890; 1 drivers +v0x2ba2410_0 .alias "Command", 2 0, v0x2bc67a0_0; +L_0x2bf5600 .part v0x2bc78e0_0, 0, 1; +S_0x2ba1b70 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0x2ba1a80; + .timescale -9 -12; +L_0x2bf5110/d .functor NOT 1, L_0x2bf5600, C4<0>, C4<0>, C4<0>; +L_0x2bf5110 .delay (10000,10000,10000) L_0x2bf5110/d; +L_0x2bf51d0/d .functor AND 1, L_0x2bf4fe0, L_0x2bf5110, C4<1>, C4<1>; +L_0x2bf51d0 .delay (20000,20000,20000) L_0x2bf51d0/d; +L_0x2bf52e0/d .functor AND 1, L_0x2bf4f20, L_0x2bf5600, C4<1>, C4<1>; +L_0x2bf52e0 .delay (20000,20000,20000) L_0x2bf52e0/d; +L_0x2bf5430/d .functor OR 1, L_0x2bf51d0, L_0x2bf52e0, C4<0>, C4<0>; +L_0x2bf5430 .delay (20000,20000,20000) L_0x2bf5430/d; +v0x2ba1c60_0 .net "S", 0 0, L_0x2bf5600; 1 drivers +v0x2ba1ce0_0 .alias "in0", 0 0, v0x2ba2180_0; +v0x2ba1d80_0 .alias "in1", 0 0, v0x2ba2200_0; +v0x2ba1e20_0 .net "nS", 0 0, L_0x2bf5110; 1 drivers +v0x2ba1ea0_0 .net "out0", 0 0, L_0x2bf51d0; 1 drivers +v0x2ba1f40_0 .net "out1", 0 0, L_0x2bf52e0; 1 drivers +v0x2ba2020_0 .alias "outfinal", 0 0, v0x2ba22b0_0; +S_0x2ba0d50 .scope generate, "andbits[2]" "andbits[2]" 3 169, 3 169, S_0x2b8b740; + .timescale -9 -12; +P_0x2ba0e48 .param/l "i" 3 169, +C4<010>; +S_0x2ba0ec0 .scope module, "attempt" "AndNand" 3 171, 3 48, S_0x2ba0d50; + .timescale -9 -12; +L_0x2bf5930/d .functor NAND 1, L_0x2bf61f0, L_0x2bf6290, C4<1>, C4<1>; +L_0x2bf5930 .delay (10000,10000,10000) L_0x2bf5930/d; +L_0x2bf5a90/d .functor NOT 1, L_0x2bf5930, C4<0>, C4<0>, C4<0>; +L_0x2bf5a90 .delay (10000,10000,10000) L_0x2bf5a90/d; +v0x2ba1500_0 .net "A", 0 0, L_0x2bf61f0; 1 drivers +v0x2ba15c0_0 .net "AandB", 0 0, L_0x2bf5a90; 1 drivers +v0x2ba1640_0 .net "AnandB", 0 0, L_0x2bf5930; 1 drivers +v0x2ba16f0_0 .net "AndNandOut", 0 0, L_0x2bf5ee0; 1 drivers +v0x2ba17d0_0 .net "B", 0 0, L_0x2bf6290; 1 drivers +v0x2ba1850_0 .alias "Command", 2 0, v0x2bc67a0_0; +L_0x2bf60b0 .part v0x2bc78e0_0, 0, 1; +S_0x2ba0fb0 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0x2ba0ec0; + .timescale -9 -12; +L_0x2bf5bc0/d .functor NOT 1, L_0x2bf60b0, C4<0>, C4<0>, C4<0>; +L_0x2bf5bc0 .delay (10000,10000,10000) L_0x2bf5bc0/d; +L_0x2bf5c80/d .functor AND 1, L_0x2bf5a90, L_0x2bf5bc0, C4<1>, C4<1>; +L_0x2bf5c80 .delay (20000,20000,20000) L_0x2bf5c80/d; +L_0x2bf5d90/d .functor AND 1, L_0x2bf5930, L_0x2bf60b0, C4<1>, C4<1>; +L_0x2bf5d90 .delay (20000,20000,20000) L_0x2bf5d90/d; +L_0x2bf5ee0/d .functor OR 1, L_0x2bf5c80, L_0x2bf5d90, C4<0>, C4<0>; +L_0x2bf5ee0 .delay (20000,20000,20000) L_0x2bf5ee0/d; +v0x2ba10a0_0 .net "S", 0 0, L_0x2bf60b0; 1 drivers +v0x2ba1120_0 .alias "in0", 0 0, v0x2ba15c0_0; +v0x2ba11c0_0 .alias "in1", 0 0, v0x2ba1640_0; +v0x2ba1260_0 .net "nS", 0 0, L_0x2bf5bc0; 1 drivers +v0x2ba12e0_0 .net "out0", 0 0, L_0x2bf5c80; 1 drivers +v0x2ba1380_0 .net "out1", 0 0, L_0x2bf5d90; 1 drivers +v0x2ba1460_0 .alias "outfinal", 0 0, v0x2ba16f0_0; +S_0x2ba0190 .scope generate, "andbits[3]" "andbits[3]" 3 169, 3 169, S_0x2b8b740; + .timescale -9 -12; +P_0x2ba0288 .param/l "i" 3 169, +C4<011>; +S_0x2ba0300 .scope module, "attempt" "AndNand" 3 171, 3 48, S_0x2ba0190; + .timescale -9 -12; +L_0x2bf63c0/d .functor NAND 1, L_0x2bf6c60, L_0x2bf6d50, C4<1>, C4<1>; +L_0x2bf63c0 .delay (10000,10000,10000) L_0x2bf63c0/d; +L_0x2bf6500/d .functor NOT 1, L_0x2bf63c0, C4<0>, C4<0>, C4<0>; +L_0x2bf6500 .delay (10000,10000,10000) L_0x2bf6500/d; +v0x2ba0940_0 .net "A", 0 0, L_0x2bf6c60; 1 drivers +v0x2ba0a00_0 .net "AandB", 0 0, L_0x2bf6500; 1 drivers +v0x2ba0a80_0 .net "AnandB", 0 0, L_0x2bf63c0; 1 drivers +v0x2ba0b30_0 .net "AndNandOut", 0 0, L_0x2bf6950; 1 drivers +v0x2ba0c10_0 .net "B", 0 0, L_0x2bf6d50; 1 drivers +v0x2ba0c90_0 .alias "Command", 2 0, v0x2bc67a0_0; +L_0x2bf6b20 .part v0x2bc78e0_0, 0, 1; +S_0x2ba03f0 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0x2ba0300; + .timescale -9 -12; +L_0x2bf6630/d .functor NOT 1, L_0x2bf6b20, C4<0>, C4<0>, C4<0>; +L_0x2bf6630 .delay (10000,10000,10000) L_0x2bf6630/d; +L_0x2bf66f0/d .functor AND 1, L_0x2bf6500, L_0x2bf6630, C4<1>, C4<1>; +L_0x2bf66f0 .delay (20000,20000,20000) L_0x2bf66f0/d; +L_0x2bf6800/d .functor AND 1, L_0x2bf63c0, L_0x2bf6b20, C4<1>, C4<1>; +L_0x2bf6800 .delay (20000,20000,20000) L_0x2bf6800/d; +L_0x2bf6950/d .functor OR 1, L_0x2bf66f0, L_0x2bf6800, C4<0>, C4<0>; +L_0x2bf6950 .delay (20000,20000,20000) L_0x2bf6950/d; +v0x2ba04e0_0 .net "S", 0 0, L_0x2bf6b20; 1 drivers +v0x2ba0560_0 .alias "in0", 0 0, v0x2ba0a00_0; +v0x2ba0600_0 .alias "in1", 0 0, v0x2ba0a80_0; +v0x2ba06a0_0 .net "nS", 0 0, L_0x2bf6630; 1 drivers +v0x2ba0720_0 .net "out0", 0 0, L_0x2bf66f0; 1 drivers +v0x2ba07c0_0 .net "out1", 0 0, L_0x2bf6800; 1 drivers +v0x2ba08a0_0 .alias "outfinal", 0 0, v0x2ba0b30_0; +S_0x2b9f5d0 .scope generate, "andbits[4]" "andbits[4]" 3 169, 3 169, S_0x2b8b740; + .timescale -9 -12; +P_0x2b9f6c8 .param/l "i" 3 169, +C4<0100>; +S_0x2b9f740 .scope module, "attempt" "AndNand" 3 171, 3 48, S_0x2b9f5d0; + .timescale -9 -12; +L_0x2bf6e40/d .functor NAND 1, L_0x2bf7720, L_0x2bf77c0, C4<1>, C4<1>; +L_0x2bf6e40 .delay (10000,10000,10000) L_0x2bf6e40/d; +L_0x2bf6f60/d .functor NOT 1, L_0x2bf6e40, C4<0>, C4<0>, C4<0>; +L_0x2bf6f60 .delay (10000,10000,10000) L_0x2bf6f60/d; +v0x2b9fd80_0 .net "A", 0 0, L_0x2bf7720; 1 drivers +v0x2b9fe40_0 .net "AandB", 0 0, L_0x2bf6f60; 1 drivers +v0x2b9fec0_0 .net "AnandB", 0 0, L_0x2bf6e40; 1 drivers +v0x2b9ff70_0 .net "AndNandOut", 0 0, L_0x2bf73b0; 1 drivers +v0x2ba0050_0 .net "B", 0 0, L_0x2bf77c0; 1 drivers +v0x2ba00d0_0 .alias "Command", 2 0, v0x2bc67a0_0; +L_0x2bf7580 .part v0x2bc78e0_0, 0, 1; +S_0x2b9f830 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0x2b9f740; + .timescale -9 -12; +L_0x2bf7090/d .functor NOT 1, L_0x2bf7580, C4<0>, C4<0>, C4<0>; +L_0x2bf7090 .delay (10000,10000,10000) L_0x2bf7090/d; +L_0x2bf7150/d .functor AND 1, L_0x2bf6f60, L_0x2bf7090, C4<1>, C4<1>; +L_0x2bf7150 .delay (20000,20000,20000) L_0x2bf7150/d; +L_0x2bf7260/d .functor AND 1, L_0x2bf6e40, L_0x2bf7580, C4<1>, C4<1>; +L_0x2bf7260 .delay (20000,20000,20000) L_0x2bf7260/d; +L_0x2bf73b0/d .functor OR 1, L_0x2bf7150, L_0x2bf7260, C4<0>, C4<0>; +L_0x2bf73b0 .delay (20000,20000,20000) L_0x2bf73b0/d; +v0x2b9f920_0 .net "S", 0 0, L_0x2bf7580; 1 drivers +v0x2b9f9a0_0 .alias "in0", 0 0, v0x2b9fe40_0; +v0x2b9fa40_0 .alias "in1", 0 0, v0x2b9fec0_0; +v0x2b9fae0_0 .net "nS", 0 0, L_0x2bf7090; 1 drivers +v0x2b9fb60_0 .net "out0", 0 0, L_0x2bf7150; 1 drivers +v0x2b9fc00_0 .net "out1", 0 0, L_0x2bf7260; 1 drivers +v0x2b9fce0_0 .alias "outfinal", 0 0, v0x2b9ff70_0; +S_0x2b9ea10 .scope generate, "andbits[5]" "andbits[5]" 3 169, 3 169, S_0x2b8b740; + .timescale -9 -12; +P_0x2b9eb08 .param/l "i" 3 169, +C4<0101>; +S_0x2b9eb80 .scope module, "attempt" "AndNand" 3 171, 3 48, S_0x2b9ea10; + .timescale -9 -12; +L_0x2bf76c0/d .functor NAND 1, L_0x2bf8240, L_0x2bf82e0, C4<1>, C4<1>; +L_0x2bf76c0 .delay (10000,10000,10000) L_0x2bf76c0/d; +L_0x2bf79d0/d .functor NOT 1, L_0x2bf76c0, C4<0>, C4<0>, C4<0>; +L_0x2bf79d0 .delay (10000,10000,10000) L_0x2bf79d0/d; +v0x2b9f1c0_0 .net "A", 0 0, L_0x2bf8240; 1 drivers +v0x2b9f280_0 .net "AandB", 0 0, L_0x2bf79d0; 1 drivers +v0x2b9f300_0 .net "AnandB", 0 0, L_0x2bf76c0; 1 drivers +v0x2b9f3b0_0 .net "AndNandOut", 0 0, L_0x2bf7e20; 1 drivers +v0x2b9f490_0 .net "B", 0 0, L_0x2bf82e0; 1 drivers +v0x2b9f510_0 .alias "Command", 2 0, v0x2bc67a0_0; +L_0x2bf7ff0 .part v0x2bc78e0_0, 0, 1; +S_0x2b9ec70 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0x2b9eb80; + .timescale -9 -12; +L_0x2bf7b00/d .functor NOT 1, L_0x2bf7ff0, C4<0>, C4<0>, C4<0>; +L_0x2bf7b00 .delay (10000,10000,10000) L_0x2bf7b00/d; +L_0x2bf7bc0/d .functor AND 1, L_0x2bf79d0, L_0x2bf7b00, C4<1>, C4<1>; +L_0x2bf7bc0 .delay (20000,20000,20000) L_0x2bf7bc0/d; +L_0x2bf7cd0/d .functor AND 1, L_0x2bf76c0, L_0x2bf7ff0, C4<1>, C4<1>; +L_0x2bf7cd0 .delay (20000,20000,20000) L_0x2bf7cd0/d; +L_0x2bf7e20/d .functor OR 1, L_0x2bf7bc0, L_0x2bf7cd0, C4<0>, C4<0>; +L_0x2bf7e20 .delay (20000,20000,20000) L_0x2bf7e20/d; +v0x2b9ed60_0 .net "S", 0 0, L_0x2bf7ff0; 1 drivers +v0x2b9ede0_0 .alias "in0", 0 0, v0x2b9f280_0; +v0x2b9ee80_0 .alias "in1", 0 0, v0x2b9f300_0; +v0x2b9ef20_0 .net "nS", 0 0, L_0x2bf7b00; 1 drivers +v0x2b9efa0_0 .net "out0", 0 0, L_0x2bf7bc0; 1 drivers +v0x2b9f040_0 .net "out1", 0 0, L_0x2bf7cd0; 1 drivers +v0x2b9f120_0 .alias "outfinal", 0 0, v0x2b9f3b0_0; +S_0x2b9de50 .scope generate, "andbits[6]" "andbits[6]" 3 169, 3 169, S_0x2b8b740; + .timescale -9 -12; +P_0x2b9df48 .param/l "i" 3 169, +C4<0110>; +S_0x2b9dfc0 .scope module, "attempt" "AndNand" 3 171, 3 48, S_0x2b9de50; + .timescale -9 -12; +L_0x2bf83d0/d .functor NAND 1, L_0x2bf8c90, L_0x2bf8d30, C4<1>, C4<1>; +L_0x2bf83d0 .delay (10000,10000,10000) L_0x2bf83d0/d; +L_0x2bf8530/d .functor NOT 1, L_0x2bf83d0, C4<0>, C4<0>, C4<0>; +L_0x2bf8530 .delay (10000,10000,10000) L_0x2bf8530/d; +v0x2b9e600_0 .net "A", 0 0, L_0x2bf8c90; 1 drivers +v0x2b9e6c0_0 .net "AandB", 0 0, L_0x2bf8530; 1 drivers +v0x2b9e740_0 .net "AnandB", 0 0, L_0x2bf83d0; 1 drivers +v0x2b9e7f0_0 .net "AndNandOut", 0 0, L_0x2bf8980; 1 drivers +v0x2b9e8d0_0 .net "B", 0 0, L_0x2bf8d30; 1 drivers +v0x2b9e950_0 .alias "Command", 2 0, v0x2bc67a0_0; +L_0x2bf8b50 .part v0x2bc78e0_0, 0, 1; +S_0x2b9e0b0 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0x2b9dfc0; + .timescale -9 -12; +L_0x2bf8660/d .functor NOT 1, L_0x2bf8b50, C4<0>, C4<0>, C4<0>; +L_0x2bf8660 .delay (10000,10000,10000) L_0x2bf8660/d; +L_0x2bf8720/d .functor AND 1, L_0x2bf8530, L_0x2bf8660, C4<1>, C4<1>; +L_0x2bf8720 .delay (20000,20000,20000) L_0x2bf8720/d; +L_0x2bf8830/d .functor AND 1, L_0x2bf83d0, L_0x2bf8b50, C4<1>, C4<1>; +L_0x2bf8830 .delay (20000,20000,20000) L_0x2bf8830/d; +L_0x2bf8980/d .functor OR 1, L_0x2bf8720, L_0x2bf8830, C4<0>, C4<0>; +L_0x2bf8980 .delay (20000,20000,20000) L_0x2bf8980/d; +v0x2b9e1a0_0 .net "S", 0 0, L_0x2bf8b50; 1 drivers +v0x2b9e220_0 .alias "in0", 0 0, v0x2b9e6c0_0; +v0x2b9e2c0_0 .alias "in1", 0 0, v0x2b9e740_0; +v0x2b9e360_0 .net "nS", 0 0, L_0x2bf8660; 1 drivers +v0x2b9e3e0_0 .net "out0", 0 0, L_0x2bf8720; 1 drivers +v0x2b9e480_0 .net "out1", 0 0, L_0x2bf8830; 1 drivers +v0x2b9e560_0 .alias "outfinal", 0 0, v0x2b9e7f0_0; +S_0x2b9d290 .scope generate, "andbits[7]" "andbits[7]" 3 169, 3 169, S_0x2b8b740; + .timescale -9 -12; +P_0x2b9d388 .param/l "i" 3 169, +C4<0111>; +S_0x2b9d400 .scope module, "attempt" "AndNand" 3 171, 3 48, S_0x2b9d290; + .timescale -9 -12; +L_0x2bf5740/d .functor NAND 1, L_0x2bf9700, L_0x2bf8e20, C4<1>, C4<1>; +L_0x2bf5740 .delay (10000,10000,10000) L_0x2bf5740/d; +L_0x2bf8fa0/d .functor NOT 1, L_0x2bf5740, C4<0>, C4<0>, C4<0>; +L_0x2bf8fa0 .delay (10000,10000,10000) L_0x2bf8fa0/d; +v0x2b9da40_0 .net "A", 0 0, L_0x2bf9700; 1 drivers +v0x2b9db00_0 .net "AandB", 0 0, L_0x2bf8fa0; 1 drivers +v0x2b9db80_0 .net "AnandB", 0 0, L_0x2bf5740; 1 drivers +v0x2b9dc30_0 .net "AndNandOut", 0 0, L_0x2bf93f0; 1 drivers +v0x2b9dd10_0 .net "B", 0 0, L_0x2bf8e20; 1 drivers +v0x2b9dd90_0 .alias "Command", 2 0, v0x2bc67a0_0; +L_0x2bf95c0 .part v0x2bc78e0_0, 0, 1; +S_0x2b9d4f0 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0x2b9d400; + .timescale -9 -12; +L_0x2bf90d0/d .functor NOT 1, L_0x2bf95c0, C4<0>, C4<0>, C4<0>; +L_0x2bf90d0 .delay (10000,10000,10000) L_0x2bf90d0/d; +L_0x2bf9190/d .functor AND 1, L_0x2bf8fa0, L_0x2bf90d0, C4<1>, C4<1>; +L_0x2bf9190 .delay (20000,20000,20000) L_0x2bf9190/d; +L_0x2bf92a0/d .functor AND 1, L_0x2bf5740, L_0x2bf95c0, C4<1>, C4<1>; +L_0x2bf92a0 .delay (20000,20000,20000) L_0x2bf92a0/d; +L_0x2bf93f0/d .functor OR 1, L_0x2bf9190, L_0x2bf92a0, C4<0>, C4<0>; +L_0x2bf93f0 .delay (20000,20000,20000) L_0x2bf93f0/d; +v0x2b9d5e0_0 .net "S", 0 0, L_0x2bf95c0; 1 drivers +v0x2b9d660_0 .alias "in0", 0 0, v0x2b9db00_0; +v0x2b9d700_0 .alias "in1", 0 0, v0x2b9db80_0; +v0x2b9d7a0_0 .net "nS", 0 0, L_0x2bf90d0; 1 drivers +v0x2b9d820_0 .net "out0", 0 0, L_0x2bf9190; 1 drivers +v0x2b9d8c0_0 .net "out1", 0 0, L_0x2bf92a0; 1 drivers +v0x2b9d9a0_0 .alias "outfinal", 0 0, v0x2b9dc30_0; +S_0x2b9c6d0 .scope generate, "andbits[8]" "andbits[8]" 3 169, 3 169, S_0x2b8b740; + .timescale -9 -12; +P_0x2b9c7c8 .param/l "i" 3 169, +C4<01000>; +S_0x2b9c840 .scope module, "attempt" "AndNand" 3 171, 3 48, S_0x2b9c6d0; + .timescale -9 -12; +L_0x2bf98a0/d .functor NAND 1, L_0x2bf97a0, L_0x2bfa220, C4<1>, C4<1>; +L_0x2bf98a0 .delay (10000,10000,10000) L_0x2bf98a0/d; +L_0x2bf9a00/d .functor NOT 1, L_0x2bf98a0, C4<0>, C4<0>, C4<0>; +L_0x2bf9a00 .delay (10000,10000,10000) L_0x2bf9a00/d; +v0x2b9ce80_0 .net "A", 0 0, L_0x2bf97a0; 1 drivers +v0x2b9cf40_0 .net "AandB", 0 0, L_0x2bf9a00; 1 drivers +v0x2b9cfc0_0 .net "AnandB", 0 0, L_0x2bf98a0; 1 drivers +v0x2b9d070_0 .net "AndNandOut", 0 0, L_0x2bf9e50; 1 drivers +v0x2b9d150_0 .net "B", 0 0, L_0x2bfa220; 1 drivers +v0x2b9d1d0_0 .alias "Command", 2 0, v0x2bc67a0_0; +L_0x2bfa020 .part v0x2bc78e0_0, 0, 1; +S_0x2b9c930 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0x2b9c840; + .timescale -9 -12; +L_0x2bf9b30/d .functor NOT 1, L_0x2bfa020, C4<0>, C4<0>, C4<0>; +L_0x2bf9b30 .delay (10000,10000,10000) L_0x2bf9b30/d; +L_0x2bf9bf0/d .functor AND 1, L_0x2bf9a00, L_0x2bf9b30, C4<1>, C4<1>; +L_0x2bf9bf0 .delay (20000,20000,20000) L_0x2bf9bf0/d; +L_0x2bf9d00/d .functor AND 1, L_0x2bf98a0, L_0x2bfa020, C4<1>, C4<1>; +L_0x2bf9d00 .delay (20000,20000,20000) L_0x2bf9d00/d; +L_0x2bf9e50/d .functor OR 1, L_0x2bf9bf0, L_0x2bf9d00, C4<0>, C4<0>; +L_0x2bf9e50 .delay (20000,20000,20000) L_0x2bf9e50/d; +v0x2b9ca20_0 .net "S", 0 0, L_0x2bfa020; 1 drivers +v0x2b9caa0_0 .alias "in0", 0 0, v0x2b9cf40_0; +v0x2b9cb40_0 .alias "in1", 0 0, v0x2b9cfc0_0; +v0x2b9cbe0_0 .net "nS", 0 0, L_0x2bf9b30; 1 drivers +v0x2b9cc60_0 .net "out0", 0 0, L_0x2bf9bf0; 1 drivers +v0x2b9cd00_0 .net "out1", 0 0, L_0x2bf9d00; 1 drivers +v0x2b9cde0_0 .alias "outfinal", 0 0, v0x2b9d070_0; +S_0x2b9bb10 .scope generate, "andbits[9]" "andbits[9]" 3 169, 3 169, S_0x2b8b740; + .timescale -9 -12; +P_0x2b9bc08 .param/l "i" 3 169, +C4<01001>; +S_0x2b9bc80 .scope module, "attempt" "AndNand" 3 171, 3 48, S_0x2b9bb10; + .timescale -9 -12; +L_0x2bfa160/d .functor NAND 1, L_0x2bfabe0, L_0x2bfa310, C4<1>, C4<1>; +L_0x2bfa160 .delay (10000,10000,10000) L_0x2bfa160/d; +L_0x2bfa480/d .functor NOT 1, L_0x2bfa160, C4<0>, C4<0>, C4<0>; +L_0x2bfa480 .delay (10000,10000,10000) L_0x2bfa480/d; +v0x2b9c2c0_0 .net "A", 0 0, L_0x2bfabe0; 1 drivers +v0x2b9c380_0 .net "AandB", 0 0, L_0x2bfa480; 1 drivers +v0x2b9c400_0 .net "AnandB", 0 0, L_0x2bfa160; 1 drivers +v0x2b9c4b0_0 .net "AndNandOut", 0 0, L_0x2bfa8d0; 1 drivers +v0x2b9c590_0 .net "B", 0 0, L_0x2bfa310; 1 drivers +v0x2b9c610_0 .alias "Command", 2 0, v0x2bc67a0_0; +L_0x2bfaaa0 .part v0x2bc78e0_0, 0, 1; +S_0x2b9bd70 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0x2b9bc80; + .timescale -9 -12; +L_0x2bfa5b0/d .functor NOT 1, L_0x2bfaaa0, C4<0>, C4<0>, C4<0>; +L_0x2bfa5b0 .delay (10000,10000,10000) L_0x2bfa5b0/d; +L_0x2bfa670/d .functor AND 1, L_0x2bfa480, L_0x2bfa5b0, C4<1>, C4<1>; +L_0x2bfa670 .delay (20000,20000,20000) L_0x2bfa670/d; +L_0x2bfa780/d .functor AND 1, L_0x2bfa160, L_0x2bfaaa0, C4<1>, C4<1>; +L_0x2bfa780 .delay (20000,20000,20000) L_0x2bfa780/d; +L_0x2bfa8d0/d .functor OR 1, L_0x2bfa670, L_0x2bfa780, C4<0>, C4<0>; +L_0x2bfa8d0 .delay (20000,20000,20000) L_0x2bfa8d0/d; +v0x2b9be60_0 .net "S", 0 0, L_0x2bfaaa0; 1 drivers +v0x2b9bee0_0 .alias "in0", 0 0, v0x2b9c380_0; +v0x2b9bf80_0 .alias "in1", 0 0, v0x2b9c400_0; +v0x2b9c020_0 .net "nS", 0 0, L_0x2bfa5b0; 1 drivers +v0x2b9c0a0_0 .net "out0", 0 0, L_0x2bfa670; 1 drivers +v0x2b9c140_0 .net "out1", 0 0, L_0x2bfa780; 1 drivers +v0x2b9c220_0 .alias "outfinal", 0 0, v0x2b9c4b0_0; +S_0x2b9af50 .scope generate, "andbits[10]" "andbits[10]" 3 169, 3 169, S_0x2b8b740; + .timescale -9 -12; +P_0x2b9b048 .param/l "i" 3 169, +C4<01010>; +S_0x2b9b0c0 .scope module, "attempt" "AndNand" 3 171, 3 48, S_0x2b9af50; + .timescale -9 -12; +L_0x2bfadb0/d .functor NAND 1, L_0x2bfac80, L_0x2bfb740, C4<1>, C4<1>; +L_0x2bfadb0 .delay (10000,10000,10000) L_0x2bfadb0/d; +L_0x2bfaef0/d .functor NOT 1, L_0x2bfadb0, C4<0>, C4<0>, C4<0>; +L_0x2bfaef0 .delay (10000,10000,10000) L_0x2bfaef0/d; +v0x2b9b700_0 .net "A", 0 0, L_0x2bfac80; 1 drivers +v0x2b9b7c0_0 .net "AandB", 0 0, L_0x2bfaef0; 1 drivers +v0x2b9b840_0 .net "AnandB", 0 0, L_0x2bfadb0; 1 drivers +v0x2b9b8f0_0 .net "AndNandOut", 0 0, L_0x2bfb340; 1 drivers +v0x2b9b9d0_0 .net "B", 0 0, L_0x2bfb740; 1 drivers +v0x2b9ba50_0 .alias "Command", 2 0, v0x2bc67a0_0; +L_0x2bfb510 .part v0x2bc78e0_0, 0, 1; +S_0x2b9b1b0 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0x2b9b0c0; + .timescale -9 -12; +L_0x2bfb020/d .functor NOT 1, L_0x2bfb510, C4<0>, C4<0>, C4<0>; +L_0x2bfb020 .delay (10000,10000,10000) L_0x2bfb020/d; +L_0x2bfb0e0/d .functor AND 1, L_0x2bfaef0, L_0x2bfb020, C4<1>, C4<1>; +L_0x2bfb0e0 .delay (20000,20000,20000) L_0x2bfb0e0/d; +L_0x2bfb1f0/d .functor AND 1, L_0x2bfadb0, L_0x2bfb510, C4<1>, C4<1>; +L_0x2bfb1f0 .delay (20000,20000,20000) L_0x2bfb1f0/d; +L_0x2bfb340/d .functor OR 1, L_0x2bfb0e0, L_0x2bfb1f0, C4<0>, C4<0>; +L_0x2bfb340 .delay (20000,20000,20000) L_0x2bfb340/d; +v0x2b9b2a0_0 .net "S", 0 0, L_0x2bfb510; 1 drivers +v0x2b9b320_0 .alias "in0", 0 0, v0x2b9b7c0_0; +v0x2b9b3c0_0 .alias "in1", 0 0, v0x2b9b840_0; +v0x2b9b460_0 .net "nS", 0 0, L_0x2bfb020; 1 drivers +v0x2b9b4e0_0 .net "out0", 0 0, L_0x2bfb0e0; 1 drivers +v0x2b9b580_0 .net "out1", 0 0, L_0x2bfb1f0; 1 drivers +v0x2b9b660_0 .alias "outfinal", 0 0, v0x2b9b8f0_0; +S_0x2b9a390 .scope generate, "andbits[11]" "andbits[11]" 3 169, 3 169, S_0x2b8b740; + .timescale -9 -12; +P_0x2b9a488 .param/l "i" 3 169, +C4<01011>; +S_0x2b9a500 .scope module, "attempt" "AndNand" 3 171, 3 48, S_0x2b9a390; + .timescale -9 -12; +L_0x2bfb650/d .functor NAND 1, L_0x2bfc0c0, L_0x2bfb830, C4<1>, C4<1>; +L_0x2bfb650 .delay (10000,10000,10000) L_0x2bfb650/d; +L_0x2bfb980/d .functor NOT 1, L_0x2bfb650, C4<0>, C4<0>, C4<0>; +L_0x2bfb980 .delay (10000,10000,10000) L_0x2bfb980/d; +v0x2b9ab40_0 .net "A", 0 0, L_0x2bfc0c0; 1 drivers +v0x2b9ac00_0 .net "AandB", 0 0, L_0x2bfb980; 1 drivers +v0x2b9ac80_0 .net "AnandB", 0 0, L_0x2bfb650; 1 drivers +v0x2b9ad30_0 .net "AndNandOut", 0 0, L_0x2bfbdb0; 1 drivers +v0x2b9ae10_0 .net "B", 0 0, L_0x2bfb830; 1 drivers +v0x2b9ae90_0 .alias "Command", 2 0, v0x2bc67a0_0; +L_0x2bfbf80 .part v0x2bc78e0_0, 0, 1; +S_0x2b9a5f0 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0x2b9a500; + .timescale -9 -12; +L_0x2bfba90/d .functor NOT 1, L_0x2bfbf80, C4<0>, C4<0>, C4<0>; +L_0x2bfba90 .delay (10000,10000,10000) L_0x2bfba90/d; +L_0x2bfbb50/d .functor AND 1, L_0x2bfb980, L_0x2bfba90, C4<1>, C4<1>; +L_0x2bfbb50 .delay (20000,20000,20000) L_0x2bfbb50/d; +L_0x2bfbc60/d .functor AND 1, L_0x2bfb650, L_0x2bfbf80, C4<1>, C4<1>; +L_0x2bfbc60 .delay (20000,20000,20000) L_0x2bfbc60/d; +L_0x2bfbdb0/d .functor OR 1, L_0x2bfbb50, L_0x2bfbc60, C4<0>, C4<0>; +L_0x2bfbdb0 .delay (20000,20000,20000) L_0x2bfbdb0/d; +v0x2b9a6e0_0 .net "S", 0 0, L_0x2bfbf80; 1 drivers +v0x2b9a760_0 .alias "in0", 0 0, v0x2b9ac00_0; +v0x2b9a800_0 .alias "in1", 0 0, v0x2b9ac80_0; +v0x2b9a8a0_0 .net "nS", 0 0, L_0x2bfba90; 1 drivers +v0x2b9a920_0 .net "out0", 0 0, L_0x2bfbb50; 1 drivers +v0x2b9a9c0_0 .net "out1", 0 0, L_0x2bfbc60; 1 drivers +v0x2b9aaa0_0 .alias "outfinal", 0 0, v0x2b9ad30_0; +S_0x2b997d0 .scope generate, "andbits[12]" "andbits[12]" 3 169, 3 169, S_0x2b8b740; + .timescale -9 -12; +P_0x2b998c8 .param/l "i" 3 169, +C4<01100>; +S_0x2b99940 .scope module, "attempt" "AndNand" 3 171, 3 48, S_0x2b997d0; + .timescale -9 -12; +L_0x2bfc270/d .functor NAND 1, L_0x2bfc160, L_0x2bfcc50, C4<1>, C4<1>; +L_0x2bfc270 .delay (10000,10000,10000) L_0x2bfc270/d; +L_0x2bfc3d0/d .functor NOT 1, L_0x2bfc270, C4<0>, C4<0>, C4<0>; +L_0x2bfc3d0 .delay (10000,10000,10000) L_0x2bfc3d0/d; +v0x2b99f80_0 .net "A", 0 0, L_0x2bfc160; 1 drivers +v0x2b9a040_0 .net "AandB", 0 0, L_0x2bfc3d0; 1 drivers +v0x2b9a0c0_0 .net "AnandB", 0 0, L_0x2bfc270; 1 drivers +v0x2b9a170_0 .net "AndNandOut", 0 0, L_0x2bfc820; 1 drivers +v0x2b9a250_0 .net "B", 0 0, L_0x2bfcc50; 1 drivers +v0x2b9a2d0_0 .alias "Command", 2 0, v0x2bc67a0_0; +L_0x2bfc9f0 .part v0x2bc78e0_0, 0, 1; +S_0x2b99a30 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0x2b99940; + .timescale -9 -12; +L_0x2bfc500/d .functor NOT 1, L_0x2bfc9f0, C4<0>, C4<0>, C4<0>; +L_0x2bfc500 .delay (10000,10000,10000) L_0x2bfc500/d; +L_0x2bfc5c0/d .functor AND 1, L_0x2bfc3d0, L_0x2bfc500, C4<1>, C4<1>; +L_0x2bfc5c0 .delay (20000,20000,20000) L_0x2bfc5c0/d; +L_0x2bfc6d0/d .functor AND 1, L_0x2bfc270, L_0x2bfc9f0, C4<1>, C4<1>; +L_0x2bfc6d0 .delay (20000,20000,20000) L_0x2bfc6d0/d; +L_0x2bfc820/d .functor OR 1, L_0x2bfc5c0, L_0x2bfc6d0, C4<0>, C4<0>; +L_0x2bfc820 .delay (20000,20000,20000) L_0x2bfc820/d; +v0x2b99b20_0 .net "S", 0 0, L_0x2bfc9f0; 1 drivers +v0x2b99ba0_0 .alias "in0", 0 0, v0x2b9a040_0; +v0x2b99c40_0 .alias "in1", 0 0, v0x2b9a0c0_0; +v0x2b99ce0_0 .net "nS", 0 0, L_0x2bfc500; 1 drivers +v0x2b99d60_0 .net "out0", 0 0, L_0x2bfc5c0; 1 drivers +v0x2b99e00_0 .net "out1", 0 0, L_0x2bfc6d0; 1 drivers +v0x2b99ee0_0 .alias "outfinal", 0 0, v0x2b9a170_0; +S_0x2b98c10 .scope generate, "andbits[13]" "andbits[13]" 3 169, 3 169, S_0x2b8b740; + .timescale -9 -12; +P_0x2b98d08 .param/l "i" 3 169, +C4<01101>; +S_0x2b98d80 .scope module, "attempt" "AndNand" 3 171, 3 48, S_0x2b98c10; + .timescale -9 -12; +L_0x2bfcb30/d .functor NAND 1, L_0x2bf8130, L_0x2bfccf0, C4<1>, C4<1>; +L_0x2bfcb30 .delay (10000,10000,10000) L_0x2bfcb30/d; +L_0x2bfce70/d .functor NOT 1, L_0x2bfcb30, C4<0>, C4<0>, C4<0>; +L_0x2bfce70 .delay (10000,10000,10000) L_0x2bfce70/d; +v0x2b993c0_0 .net "A", 0 0, L_0x2bf8130; 1 drivers +v0x2b99480_0 .net "AandB", 0 0, L_0x2bfce70; 1 drivers +v0x2b99500_0 .net "AnandB", 0 0, L_0x2bfcb30; 1 drivers +v0x2b995b0_0 .net "AndNandOut", 0 0, L_0x2bfd2a0; 1 drivers +v0x2b99690_0 .net "B", 0 0, L_0x2bfccf0; 1 drivers +v0x2b99710_0 .alias "Command", 2 0, v0x2bc67a0_0; +L_0x2bfd470 .part v0x2bc78e0_0, 0, 1; +S_0x2b98e70 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0x2b98d80; + .timescale -9 -12; +L_0x2bfcf80/d .functor NOT 1, L_0x2bfd470, C4<0>, C4<0>, C4<0>; +L_0x2bfcf80 .delay (10000,10000,10000) L_0x2bfcf80/d; +L_0x2bfd040/d .functor AND 1, L_0x2bfce70, L_0x2bfcf80, C4<1>, C4<1>; +L_0x2bfd040 .delay (20000,20000,20000) L_0x2bfd040/d; +L_0x2bfd150/d .functor AND 1, L_0x2bfcb30, L_0x2bfd470, C4<1>, C4<1>; +L_0x2bfd150 .delay (20000,20000,20000) L_0x2bfd150/d; +L_0x2bfd2a0/d .functor OR 1, L_0x2bfd040, L_0x2bfd150, C4<0>, C4<0>; +L_0x2bfd2a0 .delay (20000,20000,20000) L_0x2bfd2a0/d; +v0x2b98f60_0 .net "S", 0 0, L_0x2bfd470; 1 drivers +v0x2b98fe0_0 .alias "in0", 0 0, v0x2b99480_0; +v0x2b99080_0 .alias "in1", 0 0, v0x2b99500_0; +v0x2b99120_0 .net "nS", 0 0, L_0x2bfcf80; 1 drivers +v0x2b991a0_0 .net "out0", 0 0, L_0x2bfd040; 1 drivers +v0x2b99240_0 .net "out1", 0 0, L_0x2bfd150; 1 drivers +v0x2b99320_0 .alias "outfinal", 0 0, v0x2b995b0_0; +S_0x2b98050 .scope generate, "andbits[14]" "andbits[14]" 3 169, 3 169, S_0x2b8b740; + .timescale -9 -12; +P_0x2b98148 .param/l "i" 3 169, +C4<01110>; +S_0x2b981c0 .scope module, "attempt" "AndNand" 3 171, 3 48, S_0x2b98050; + .timescale -9 -12; +L_0x2bf81d0/d .functor NAND 1, L_0x2bfd7c0, L_0x2bfd860, C4<1>, C4<1>; +L_0x2bf81d0 .delay (10000,10000,10000) L_0x2bf81d0/d; +L_0x2bfd9e0/d .functor NOT 1, L_0x2bf81d0, C4<0>, C4<0>, C4<0>; +L_0x2bfd9e0 .delay (10000,10000,10000) L_0x2bfd9e0/d; +v0x2b98800_0 .net "A", 0 0, L_0x2bfd7c0; 1 drivers +v0x2b988c0_0 .net "AandB", 0 0, L_0x2bfd9e0; 1 drivers +v0x2b98940_0 .net "AnandB", 0 0, L_0x2bf81d0; 1 drivers +v0x2b989f0_0 .net "AndNandOut", 0 0, L_0x2bfde10; 1 drivers +v0x2b98ad0_0 .net "B", 0 0, L_0x2bfd860; 1 drivers +v0x2b98b50_0 .alias "Command", 2 0, v0x2bc67a0_0; +L_0x2bfdfe0 .part v0x2bc78e0_0, 0, 1; +S_0x2b982b0 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0x2b981c0; + .timescale -9 -12; +L_0x2bfdaf0/d .functor NOT 1, L_0x2bfdfe0, C4<0>, C4<0>, C4<0>; +L_0x2bfdaf0 .delay (10000,10000,10000) L_0x2bfdaf0/d; +L_0x2bfdbb0/d .functor AND 1, L_0x2bfd9e0, L_0x2bfdaf0, C4<1>, C4<1>; +L_0x2bfdbb0 .delay (20000,20000,20000) L_0x2bfdbb0/d; +L_0x2bfdcc0/d .functor AND 1, L_0x2bf81d0, L_0x2bfdfe0, C4<1>, C4<1>; +L_0x2bfdcc0 .delay (20000,20000,20000) L_0x2bfdcc0/d; +L_0x2bfde10/d .functor OR 1, L_0x2bfdbb0, L_0x2bfdcc0, C4<0>, C4<0>; +L_0x2bfde10 .delay (20000,20000,20000) L_0x2bfde10/d; +v0x2b983a0_0 .net "S", 0 0, L_0x2bfdfe0; 1 drivers +v0x2b98420_0 .alias "in0", 0 0, v0x2b988c0_0; +v0x2b984c0_0 .alias "in1", 0 0, v0x2b98940_0; +v0x2b98560_0 .net "nS", 0 0, L_0x2bfdaf0; 1 drivers +v0x2b985e0_0 .net "out0", 0 0, L_0x2bfdbb0; 1 drivers +v0x2b98680_0 .net "out1", 0 0, L_0x2bfdcc0; 1 drivers +v0x2b98760_0 .alias "outfinal", 0 0, v0x2b989f0_0; +S_0x2b97490 .scope generate, "andbits[15]" "andbits[15]" 3 169, 3 169, S_0x2b8b740; + .timescale -9 -12; +P_0x2b97588 .param/l "i" 3 169, +C4<01111>; +S_0x2b97600 .scope module, "attempt" "AndNand" 3 171, 3 48, S_0x2b97490; + .timescale -9 -12; +L_0x2bfe120/d .functor NAND 1, L_0x2bfeb90, L_0x2bfe2c0, C4<1>, C4<1>; +L_0x2bfe120 .delay (10000,10000,10000) L_0x2bfe120/d; +L_0x2bfe470/d .functor NOT 1, L_0x2bfe120, C4<0>, C4<0>, C4<0>; +L_0x2bfe470 .delay (10000,10000,10000) L_0x2bfe470/d; +v0x2b97c40_0 .net "A", 0 0, L_0x2bfeb90; 1 drivers +v0x2b97d00_0 .net "AandB", 0 0, L_0x2bfe470; 1 drivers +v0x2b97d80_0 .net "AnandB", 0 0, L_0x2bfe120; 1 drivers +v0x2b97e30_0 .net "AndNandOut", 0 0, L_0x2bfe880; 1 drivers +v0x2b97f10_0 .net "B", 0 0, L_0x2bfe2c0; 1 drivers +v0x2b97f90_0 .alias "Command", 2 0, v0x2bc67a0_0; +L_0x2bfea50 .part v0x2bc78e0_0, 0, 1; +S_0x2b976f0 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0x2b97600; + .timescale -9 -12; +L_0x2bfe560/d .functor NOT 1, L_0x2bfea50, C4<0>, C4<0>, C4<0>; +L_0x2bfe560 .delay (10000,10000,10000) L_0x2bfe560/d; +L_0x2bfe620/d .functor AND 1, L_0x2bfe470, L_0x2bfe560, C4<1>, C4<1>; +L_0x2bfe620 .delay (20000,20000,20000) L_0x2bfe620/d; +L_0x2bfe730/d .functor AND 1, L_0x2bfe120, L_0x2bfea50, C4<1>, C4<1>; +L_0x2bfe730 .delay (20000,20000,20000) L_0x2bfe730/d; +L_0x2bfe880/d .functor OR 1, L_0x2bfe620, L_0x2bfe730, C4<0>, C4<0>; +L_0x2bfe880 .delay (20000,20000,20000) L_0x2bfe880/d; +v0x2b977e0_0 .net "S", 0 0, L_0x2bfea50; 1 drivers +v0x2b97860_0 .alias "in0", 0 0, v0x2b97d00_0; +v0x2b97900_0 .alias "in1", 0 0, v0x2b97d80_0; +v0x2b979a0_0 .net "nS", 0 0, L_0x2bfe560; 1 drivers +v0x2b97a20_0 .net "out0", 0 0, L_0x2bfe620; 1 drivers +v0x2b97ac0_0 .net "out1", 0 0, L_0x2bfe730; 1 drivers +v0x2b97ba0_0 .alias "outfinal", 0 0, v0x2b97e30_0; +S_0x2b968d0 .scope generate, "andbits[16]" "andbits[16]" 3 169, 3 169, S_0x2b8b740; + .timescale -9 -12; +P_0x2b969c8 .param/l "i" 3 169, +C4<010000>; +S_0x2b96a40 .scope module, "attempt" "AndNand" 3 171, 3 48, S_0x2b968d0; + .timescale -9 -12; +L_0x2bfe3b0/d .functor NAND 1, L_0x2bfec30, L_0x2bfecd0, C4<1>, C4<1>; +L_0x2bfe3b0 .delay (10000,10000,10000) L_0x2bfe3b0/d; +L_0x2bfeea0/d .functor NOT 1, L_0x2bfe3b0, C4<0>, C4<0>, C4<0>; +L_0x2bfeea0 .delay (10000,10000,10000) L_0x2bfeea0/d; +v0x2b97080_0 .net "A", 0 0, L_0x2bfec30; 1 drivers +v0x2b97140_0 .net "AandB", 0 0, L_0x2bfeea0; 1 drivers +v0x2b971c0_0 .net "AnandB", 0 0, L_0x2bfe3b0; 1 drivers +v0x2b97270_0 .net "AndNandOut", 0 0, L_0x2bff2f0; 1 drivers +v0x2b97350_0 .net "B", 0 0, L_0x2bfecd0; 1 drivers +v0x2b973d0_0 .alias "Command", 2 0, v0x2bc67a0_0; +L_0x2bff4c0 .part v0x2bc78e0_0, 0, 1; +S_0x2b96b30 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0x2b96a40; + .timescale -9 -12; +L_0x2bfefd0/d .functor NOT 1, L_0x2bff4c0, C4<0>, C4<0>, C4<0>; +L_0x2bfefd0 .delay (10000,10000,10000) L_0x2bfefd0/d; +L_0x2bff090/d .functor AND 1, L_0x2bfeea0, L_0x2bfefd0, C4<1>, C4<1>; +L_0x2bff090 .delay (20000,20000,20000) L_0x2bff090/d; +L_0x2bff1a0/d .functor AND 1, L_0x2bfe3b0, L_0x2bff4c0, C4<1>, C4<1>; +L_0x2bff1a0 .delay (20000,20000,20000) L_0x2bff1a0/d; +L_0x2bff2f0/d .functor OR 1, L_0x2bff090, L_0x2bff1a0, C4<0>, C4<0>; +L_0x2bff2f0 .delay (20000,20000,20000) L_0x2bff2f0/d; +v0x2b96c20_0 .net "S", 0 0, L_0x2bff4c0; 1 drivers +v0x2b96ca0_0 .alias "in0", 0 0, v0x2b97140_0; +v0x2b96d40_0 .alias "in1", 0 0, v0x2b971c0_0; +v0x2b96de0_0 .net "nS", 0 0, L_0x2bfefd0; 1 drivers +v0x2b96e60_0 .net "out0", 0 0, L_0x2bff090; 1 drivers +v0x2b96f00_0 .net "out1", 0 0, L_0x2bff1a0; 1 drivers +v0x2b96fe0_0 .alias "outfinal", 0 0, v0x2b97270_0; +S_0x2b95d10 .scope generate, "andbits[17]" "andbits[17]" 3 169, 3 169, S_0x2b8b740; + .timescale -9 -12; +P_0x2b95e08 .param/l "i" 3 169, +C4<010001>; +S_0x2b95e80 .scope module, "attempt" "AndNand" 3 171, 3 48, S_0x2b95d10; + .timescale -9 -12; +L_0x2bff600/d .functor NAND 1, L_0x2c00080, L_0x2bff7d0, C4<1>, C4<1>; +L_0x2bff600 .delay (10000,10000,10000) L_0x2bff600/d; +L_0x2bff960/d .functor NOT 1, L_0x2bff600, C4<0>, C4<0>, C4<0>; +L_0x2bff960 .delay (10000,10000,10000) L_0x2bff960/d; +v0x2b964c0_0 .net "A", 0 0, L_0x2c00080; 1 drivers +v0x2b96580_0 .net "AandB", 0 0, L_0x2bff960; 1 drivers +v0x2b96600_0 .net "AnandB", 0 0, L_0x2bff600; 1 drivers +v0x2b966b0_0 .net "AndNandOut", 0 0, L_0x2bffd70; 1 drivers +v0x2b96790_0 .net "B", 0 0, L_0x2bff7d0; 1 drivers +v0x2b96810_0 .alias "Command", 2 0, v0x2bc67a0_0; +L_0x2bfff40 .part v0x2bc78e0_0, 0, 1; +S_0x2b95f70 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0x2b95e80; + .timescale -9 -12; +L_0x2bffa50/d .functor NOT 1, L_0x2bfff40, C4<0>, C4<0>, C4<0>; +L_0x2bffa50 .delay (10000,10000,10000) L_0x2bffa50/d; +L_0x2bffb10/d .functor AND 1, L_0x2bff960, L_0x2bffa50, C4<1>, C4<1>; +L_0x2bffb10 .delay (20000,20000,20000) L_0x2bffb10/d; +L_0x2bffc20/d .functor AND 1, L_0x2bff600, L_0x2bfff40, C4<1>, C4<1>; +L_0x2bffc20 .delay (20000,20000,20000) L_0x2bffc20/d; +L_0x2bffd70/d .functor OR 1, L_0x2bffb10, L_0x2bffc20, C4<0>, C4<0>; +L_0x2bffd70 .delay (20000,20000,20000) L_0x2bffd70/d; +v0x2b96060_0 .net "S", 0 0, L_0x2bfff40; 1 drivers +v0x2b960e0_0 .alias "in0", 0 0, v0x2b96580_0; +v0x2b96180_0 .alias "in1", 0 0, v0x2b96600_0; +v0x2b96220_0 .net "nS", 0 0, L_0x2bffa50; 1 drivers +v0x2b962a0_0 .net "out0", 0 0, L_0x2bffb10; 1 drivers +v0x2b96340_0 .net "out1", 0 0, L_0x2bffc20; 1 drivers +v0x2b96420_0 .alias "outfinal", 0 0, v0x2b966b0_0; +S_0x2b95150 .scope generate, "andbits[18]" "andbits[18]" 3 169, 3 169, S_0x2b8b740; + .timescale -9 -12; +P_0x2b95248 .param/l "i" 3 169, +C4<010010>; +S_0x2b952c0 .scope module, "attempt" "AndNand" 3 171, 3 48, S_0x2b95150; + .timescale -9 -12; +L_0x2bff8c0/d .functor NAND 1, L_0x2c00120, L_0x2c001c0, C4<1>, C4<1>; +L_0x2bff8c0 .delay (10000,10000,10000) L_0x2bff8c0/d; +L_0x2c003a0/d .functor NOT 1, L_0x2bff8c0, C4<0>, C4<0>, C4<0>; +L_0x2c003a0 .delay (10000,10000,10000) L_0x2c003a0/d; +v0x2b95900_0 .net "A", 0 0, L_0x2c00120; 1 drivers +v0x2b959c0_0 .net "AandB", 0 0, L_0x2c003a0; 1 drivers +v0x2b95a40_0 .net "AnandB", 0 0, L_0x2bff8c0; 1 drivers +v0x2b95af0_0 .net "AndNandOut", 0 0, L_0x2c007d0; 1 drivers +v0x2b95bd0_0 .net "B", 0 0, L_0x2c001c0; 1 drivers +v0x2b95c50_0 .alias "Command", 2 0, v0x2bc67a0_0; +L_0x2c009a0 .part v0x2bc78e0_0, 0, 1; +S_0x2b953b0 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0x2b952c0; + .timescale -9 -12; +L_0x2c004b0/d .functor NOT 1, L_0x2c009a0, C4<0>, C4<0>, C4<0>; +L_0x2c004b0 .delay (10000,10000,10000) L_0x2c004b0/d; +L_0x2c00570/d .functor AND 1, L_0x2c003a0, L_0x2c004b0, C4<1>, C4<1>; +L_0x2c00570 .delay (20000,20000,20000) L_0x2c00570/d; +L_0x2c00680/d .functor AND 1, L_0x2bff8c0, L_0x2c009a0, C4<1>, C4<1>; +L_0x2c00680 .delay (20000,20000,20000) L_0x2c00680/d; +L_0x2c007d0/d .functor OR 1, L_0x2c00570, L_0x2c00680, C4<0>, C4<0>; +L_0x2c007d0 .delay (20000,20000,20000) L_0x2c007d0/d; +v0x2b954a0_0 .net "S", 0 0, L_0x2c009a0; 1 drivers +v0x2b95520_0 .alias "in0", 0 0, v0x2b959c0_0; +v0x2b955c0_0 .alias "in1", 0 0, v0x2b95a40_0; +v0x2b95660_0 .net "nS", 0 0, L_0x2c004b0; 1 drivers +v0x2b956e0_0 .net "out0", 0 0, L_0x2c00570; 1 drivers +v0x2b95780_0 .net "out1", 0 0, L_0x2c00680; 1 drivers +v0x2b95860_0 .alias "outfinal", 0 0, v0x2b95af0_0; +S_0x2b94590 .scope generate, "andbits[19]" "andbits[19]" 3 169, 3 169, S_0x2b8b740; + .timescale -9 -12; +P_0x2b94688 .param/l "i" 3 169, +C4<010011>; +S_0x2b94700 .scope module, "attempt" "AndNand" 3 171, 3 48, S_0x2b94590; + .timescale -9 -12; +L_0x2c00ca0/d .functor NAND 1, L_0x2c01560, L_0x2c00ae0, C4<1>, C4<1>; +L_0x2c00ca0 .delay (10000,10000,10000) L_0x2c00ca0/d; +L_0x2c00e00/d .functor NOT 1, L_0x2c00ca0, C4<0>, C4<0>, C4<0>; +L_0x2c00e00 .delay (10000,10000,10000) L_0x2c00e00/d; +v0x2b94d40_0 .net "A", 0 0, L_0x2c01560; 1 drivers +v0x2b94e00_0 .net "AandB", 0 0, L_0x2c00e00; 1 drivers +v0x2b94e80_0 .net "AnandB", 0 0, L_0x2c00ca0; 1 drivers +v0x2b94f30_0 .net "AndNandOut", 0 0, L_0x2c01250; 1 drivers +v0x2b95010_0 .net "B", 0 0, L_0x2c00ae0; 1 drivers +v0x2b95090_0 .alias "Command", 2 0, v0x2bc67a0_0; +L_0x2c01420 .part v0x2bc78e0_0, 0, 1; +S_0x2b947f0 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0x2b94700; + .timescale -9 -12; +L_0x2c00f30/d .functor NOT 1, L_0x2c01420, C4<0>, C4<0>, C4<0>; +L_0x2c00f30 .delay (10000,10000,10000) L_0x2c00f30/d; +L_0x2c00ff0/d .functor AND 1, L_0x2c00e00, L_0x2c00f30, C4<1>, C4<1>; +L_0x2c00ff0 .delay (20000,20000,20000) L_0x2c00ff0/d; +L_0x2c01100/d .functor AND 1, L_0x2c00ca0, L_0x2c01420, C4<1>, C4<1>; +L_0x2c01100 .delay (20000,20000,20000) L_0x2c01100/d; +L_0x2c01250/d .functor OR 1, L_0x2c00ff0, L_0x2c01100, C4<0>, C4<0>; +L_0x2c01250 .delay (20000,20000,20000) L_0x2c01250/d; +v0x2b948e0_0 .net "S", 0 0, L_0x2c01420; 1 drivers +v0x2b94960_0 .alias "in0", 0 0, v0x2b94e00_0; +v0x2b94a00_0 .alias "in1", 0 0, v0x2b94e80_0; +v0x2b94aa0_0 .net "nS", 0 0, L_0x2c00f30; 1 drivers +v0x2b94b20_0 .net "out0", 0 0, L_0x2c00ff0; 1 drivers +v0x2b94bc0_0 .net "out1", 0 0, L_0x2c01100; 1 drivers +v0x2b94ca0_0 .alias "outfinal", 0 0, v0x2b94f30_0; +S_0x2b939d0 .scope generate, "andbits[20]" "andbits[20]" 3 169, 3 169, S_0x2b8b740; + .timescale -9 -12; +P_0x2b93ac8 .param/l "i" 3 169, +C4<010100>; +S_0x2b93b40 .scope module, "attempt" "AndNand" 3 171, 3 48, S_0x2b939d0; + .timescale -9 -12; +L_0x2c00bd0/d .functor NAND 1, L_0x2c01600, L_0x2c016a0, C4<1>, C4<1>; +L_0x2c00bd0 .delay (10000,10000,10000) L_0x2c00bd0/d; +L_0x2c01860/d .functor NOT 1, L_0x2c00bd0, C4<0>, C4<0>, C4<0>; +L_0x2c01860 .delay (10000,10000,10000) L_0x2c01860/d; +v0x2b94180_0 .net "A", 0 0, L_0x2c01600; 1 drivers +v0x2b94240_0 .net "AandB", 0 0, L_0x2c01860; 1 drivers +v0x2b942c0_0 .net "AnandB", 0 0, L_0x2c00bd0; 1 drivers +v0x2b94370_0 .net "AndNandOut", 0 0, L_0x2c01cb0; 1 drivers +v0x2b94450_0 .net "B", 0 0, L_0x2c016a0; 1 drivers +v0x2b944d0_0 .alias "Command", 2 0, v0x2bc67a0_0; +L_0x2c01e80 .part v0x2bc78e0_0, 0, 1; +S_0x2b93c30 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0x2b93b40; + .timescale -9 -12; +L_0x2c01990/d .functor NOT 1, L_0x2c01e80, C4<0>, C4<0>, C4<0>; +L_0x2c01990 .delay (10000,10000,10000) L_0x2c01990/d; +L_0x2c01a50/d .functor AND 1, L_0x2c01860, L_0x2c01990, C4<1>, C4<1>; +L_0x2c01a50 .delay (20000,20000,20000) L_0x2c01a50/d; +L_0x2c01b60/d .functor AND 1, L_0x2c00bd0, L_0x2c01e80, C4<1>, C4<1>; +L_0x2c01b60 .delay (20000,20000,20000) L_0x2c01b60/d; +L_0x2c01cb0/d .functor OR 1, L_0x2c01a50, L_0x2c01b60, C4<0>, C4<0>; +L_0x2c01cb0 .delay (20000,20000,20000) L_0x2c01cb0/d; +v0x2b93d20_0 .net "S", 0 0, L_0x2c01e80; 1 drivers +v0x2b93da0_0 .alias "in0", 0 0, v0x2b94240_0; +v0x2b93e40_0 .alias "in1", 0 0, v0x2b942c0_0; +v0x2b93ee0_0 .net "nS", 0 0, L_0x2c01990; 1 drivers +v0x2b93f60_0 .net "out0", 0 0, L_0x2c01a50; 1 drivers +v0x2b94000_0 .net "out1", 0 0, L_0x2c01b60; 1 drivers +v0x2b940e0_0 .alias "outfinal", 0 0, v0x2b94370_0; +S_0x2b92e10 .scope generate, "andbits[21]" "andbits[21]" 3 169, 3 169, S_0x2b8b740; + .timescale -9 -12; +P_0x2b92f08 .param/l "i" 3 169, +C4<010101>; +S_0x2b92f80 .scope module, "attempt" "AndNand" 3 171, 3 48, S_0x2b92e10; + .timescale -9 -12; +L_0x2c021b0/d .functor NAND 1, L_0x2c02a30, L_0x2c01fc0, C4<1>, C4<1>; +L_0x2c021b0 .delay (10000,10000,10000) L_0x2c021b0/d; +L_0x2c022f0/d .functor NOT 1, L_0x2c021b0, C4<0>, C4<0>, C4<0>; +L_0x2c022f0 .delay (10000,10000,10000) L_0x2c022f0/d; +v0x2b935c0_0 .net "A", 0 0, L_0x2c02a30; 1 drivers +v0x2b93680_0 .net "AandB", 0 0, L_0x2c022f0; 1 drivers +v0x2b93700_0 .net "AnandB", 0 0, L_0x2c021b0; 1 drivers +v0x2b937b0_0 .net "AndNandOut", 0 0, L_0x2c02720; 1 drivers +v0x2b93890_0 .net "B", 0 0, L_0x2c01fc0; 1 drivers +v0x2b93910_0 .alias "Command", 2 0, v0x2bc67a0_0; +L_0x2c028f0 .part v0x2bc78e0_0, 0, 1; +S_0x2b93070 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0x2b92f80; + .timescale -9 -12; +L_0x2c02400/d .functor NOT 1, L_0x2c028f0, C4<0>, C4<0>, C4<0>; +L_0x2c02400 .delay (10000,10000,10000) L_0x2c02400/d; +L_0x2c024c0/d .functor AND 1, L_0x2c022f0, L_0x2c02400, C4<1>, C4<1>; +L_0x2c024c0 .delay (20000,20000,20000) L_0x2c024c0/d; +L_0x2c025d0/d .functor AND 1, L_0x2c021b0, L_0x2c028f0, C4<1>, C4<1>; +L_0x2c025d0 .delay (20000,20000,20000) L_0x2c025d0/d; +L_0x2c02720/d .functor OR 1, L_0x2c024c0, L_0x2c025d0, C4<0>, C4<0>; +L_0x2c02720 .delay (20000,20000,20000) L_0x2c02720/d; +v0x2b93160_0 .net "S", 0 0, L_0x2c028f0; 1 drivers +v0x2b931e0_0 .alias "in0", 0 0, v0x2b93680_0; +v0x2b93280_0 .alias "in1", 0 0, v0x2b93700_0; +v0x2b93320_0 .net "nS", 0 0, L_0x2c02400; 1 drivers +v0x2b933a0_0 .net "out0", 0 0, L_0x2c024c0; 1 drivers +v0x2b93440_0 .net "out1", 0 0, L_0x2c025d0; 1 drivers +v0x2b93520_0 .alias "outfinal", 0 0, v0x2b937b0_0; +S_0x2b92250 .scope generate, "andbits[22]" "andbits[22]" 3 169, 3 169, S_0x2b8b740; + .timescale -9 -12; +P_0x2b92348 .param/l "i" 3 169, +C4<010110>; +S_0x2b923c0 .scope module, "attempt" "AndNand" 3 171, 3 48, S_0x2b92250; + .timescale -9 -12; +L_0x2c020b0/d .functor NAND 1, L_0x2c02ad0, L_0x2c02b70, C4<1>, C4<1>; +L_0x2c020b0 .delay (10000,10000,10000) L_0x2c020b0/d; +L_0x2c02d60/d .functor NOT 1, L_0x2c020b0, C4<0>, C4<0>, C4<0>; +L_0x2c02d60 .delay (10000,10000,10000) L_0x2c02d60/d; +v0x2b92a00_0 .net "A", 0 0, L_0x2c02ad0; 1 drivers +v0x2b92ac0_0 .net "AandB", 0 0, L_0x2c02d60; 1 drivers +v0x2b92b40_0 .net "AnandB", 0 0, L_0x2c020b0; 1 drivers +v0x2b92bf0_0 .net "AndNandOut", 0 0, L_0x2c03190; 1 drivers +v0x2b92cd0_0 .net "B", 0 0, L_0x2c02b70; 1 drivers +v0x2b92d50_0 .alias "Command", 2 0, v0x2bc67a0_0; +L_0x2c03360 .part v0x2bc78e0_0, 0, 1; +S_0x2b924b0 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0x2b923c0; + .timescale -9 -12; +L_0x2c02e70/d .functor NOT 1, L_0x2c03360, C4<0>, C4<0>, C4<0>; +L_0x2c02e70 .delay (10000,10000,10000) L_0x2c02e70/d; +L_0x2c02f30/d .functor AND 1, L_0x2c02d60, L_0x2c02e70, C4<1>, C4<1>; +L_0x2c02f30 .delay (20000,20000,20000) L_0x2c02f30/d; +L_0x2c03040/d .functor AND 1, L_0x2c020b0, L_0x2c03360, C4<1>, C4<1>; +L_0x2c03040 .delay (20000,20000,20000) L_0x2c03040/d; +L_0x2c03190/d .functor OR 1, L_0x2c02f30, L_0x2c03040, C4<0>, C4<0>; +L_0x2c03190 .delay (20000,20000,20000) L_0x2c03190/d; +v0x2b925a0_0 .net "S", 0 0, L_0x2c03360; 1 drivers +v0x2b92620_0 .alias "in0", 0 0, v0x2b92ac0_0; +v0x2b926c0_0 .alias "in1", 0 0, v0x2b92b40_0; +v0x2b92760_0 .net "nS", 0 0, L_0x2c02e70; 1 drivers +v0x2b927e0_0 .net "out0", 0 0, L_0x2c02f30; 1 drivers +v0x2b92880_0 .net "out1", 0 0, L_0x2c03040; 1 drivers +v0x2b92960_0 .alias "outfinal", 0 0, v0x2b92bf0_0; +S_0x2b91690 .scope generate, "andbits[23]" "andbits[23]" 3 169, 3 169, S_0x2b8b740; + .timescale -9 -12; +P_0x2b91788 .param/l "i" 3 169, +C4<010111>; +S_0x2b91800 .scope module, "attempt" "AndNand" 3 171, 3 48, S_0x2b91690; + .timescale -9 -12; +L_0x2c02c60/d .functor NAND 1, L_0x2c03f20, L_0x2c034a0, C4<1>, C4<1>; +L_0x2c02c60 .delay (10000,10000,10000) L_0x2c02c60/d; +L_0x2c037c0/d .functor NOT 1, L_0x2c02c60, C4<0>, C4<0>, C4<0>; +L_0x2c037c0 .delay (10000,10000,10000) L_0x2c037c0/d; +v0x2b91e40_0 .net "A", 0 0, L_0x2c03f20; 1 drivers +v0x2b91f00_0 .net "AandB", 0 0, L_0x2c037c0; 1 drivers +v0x2b91f80_0 .net "AnandB", 0 0, L_0x2c02c60; 1 drivers +v0x2b92030_0 .net "AndNandOut", 0 0, L_0x2c03c10; 1 drivers +v0x2b92110_0 .net "B", 0 0, L_0x2c034a0; 1 drivers +v0x2b92190_0 .alias "Command", 2 0, v0x2bc67a0_0; +L_0x2c03de0 .part v0x2bc78e0_0, 0, 1; +S_0x2b918f0 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0x2b91800; + .timescale -9 -12; +L_0x2c038f0/d .functor NOT 1, L_0x2c03de0, C4<0>, C4<0>, C4<0>; +L_0x2c038f0 .delay (10000,10000,10000) L_0x2c038f0/d; +L_0x2c039b0/d .functor AND 1, L_0x2c037c0, L_0x2c038f0, C4<1>, C4<1>; +L_0x2c039b0 .delay (20000,20000,20000) L_0x2c039b0/d; +L_0x2c03ac0/d .functor AND 1, L_0x2c02c60, L_0x2c03de0, C4<1>, C4<1>; +L_0x2c03ac0 .delay (20000,20000,20000) L_0x2c03ac0/d; +L_0x2c03c10/d .functor OR 1, L_0x2c039b0, L_0x2c03ac0, C4<0>, C4<0>; +L_0x2c03c10 .delay (20000,20000,20000) L_0x2c03c10/d; +v0x2b919e0_0 .net "S", 0 0, L_0x2c03de0; 1 drivers +v0x2b91a60_0 .alias "in0", 0 0, v0x2b91f00_0; +v0x2b91b00_0 .alias "in1", 0 0, v0x2b91f80_0; +v0x2b91ba0_0 .net "nS", 0 0, L_0x2c038f0; 1 drivers +v0x2b91c20_0 .net "out0", 0 0, L_0x2c039b0; 1 drivers +v0x2b91cc0_0 .net "out1", 0 0, L_0x2c03ac0; 1 drivers +v0x2b91da0_0 .alias "outfinal", 0 0, v0x2b92030_0; +S_0x2b90ad0 .scope generate, "andbits[24]" "andbits[24]" 3 169, 3 169, S_0x2b8b740; + .timescale -9 -12; +P_0x2b90bc8 .param/l "i" 3 169, +C4<011000>; +S_0x2b90c40 .scope module, "attempt" "AndNand" 3 171, 3 48, S_0x2b90ad0; + .timescale -9 -12; +L_0x2c03590/d .functor NAND 1, L_0x2c03fc0, L_0x2c04060, C4<1>, C4<1>; +L_0x2c03590 .delay (10000,10000,10000) L_0x2c03590/d; +L_0x2c04240/d .functor NOT 1, L_0x2c03590, C4<0>, C4<0>, C4<0>; +L_0x2c04240 .delay (10000,10000,10000) L_0x2c04240/d; +v0x2b91280_0 .net "A", 0 0, L_0x2c03fc0; 1 drivers +v0x2b91340_0 .net "AandB", 0 0, L_0x2c04240; 1 drivers +v0x2b913c0_0 .net "AnandB", 0 0, L_0x2c03590; 1 drivers +v0x2b91470_0 .net "AndNandOut", 0 0, L_0x2c04670; 1 drivers +v0x2b91550_0 .net "B", 0 0, L_0x2c04060; 1 drivers +v0x2b915d0_0 .alias "Command", 2 0, v0x2bc67a0_0; +L_0x2c04840 .part v0x2bc78e0_0, 0, 1; +S_0x2b90d30 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0x2b90c40; + .timescale -9 -12; +L_0x2c04350/d .functor NOT 1, L_0x2c04840, C4<0>, C4<0>, C4<0>; +L_0x2c04350 .delay (10000,10000,10000) L_0x2c04350/d; +L_0x2c04410/d .functor AND 1, L_0x2c04240, L_0x2c04350, C4<1>, C4<1>; +L_0x2c04410 .delay (20000,20000,20000) L_0x2c04410/d; +L_0x2c04520/d .functor AND 1, L_0x2c03590, L_0x2c04840, C4<1>, C4<1>; +L_0x2c04520 .delay (20000,20000,20000) L_0x2c04520/d; +L_0x2c04670/d .functor OR 1, L_0x2c04410, L_0x2c04520, C4<0>, C4<0>; +L_0x2c04670 .delay (20000,20000,20000) L_0x2c04670/d; +v0x2b90e20_0 .net "S", 0 0, L_0x2c04840; 1 drivers +v0x2b90ea0_0 .alias "in0", 0 0, v0x2b91340_0; +v0x2b90f40_0 .alias "in1", 0 0, v0x2b913c0_0; +v0x2b90fe0_0 .net "nS", 0 0, L_0x2c04350; 1 drivers +v0x2b91060_0 .net "out0", 0 0, L_0x2c04410; 1 drivers +v0x2b91100_0 .net "out1", 0 0, L_0x2c04520; 1 drivers +v0x2b911e0_0 .alias "outfinal", 0 0, v0x2b91470_0; +S_0x2b8ff10 .scope generate, "andbits[25]" "andbits[25]" 3 169, 3 169, S_0x2b8b740; + .timescale -9 -12; +P_0x2b90008 .param/l "i" 3 169, +C4<011001>; +S_0x2b90080 .scope module, "attempt" "AndNand" 3 171, 3 48, S_0x2b8ff10; + .timescale -9 -12; +L_0x2c04150/d .functor NAND 1, L_0x2c053f0, L_0x2bea340, C4<1>, C4<1>; +L_0x2c04150 .delay (10000,10000,10000) L_0x2c04150/d; +L_0x2c04cb0/d .functor NOT 1, L_0x2c04150, C4<0>, C4<0>, C4<0>; +L_0x2c04cb0 .delay (10000,10000,10000) L_0x2c04cb0/d; +v0x2b906c0_0 .net "A", 0 0, L_0x2c053f0; 1 drivers +v0x2b90780_0 .net "AandB", 0 0, L_0x2c04cb0; 1 drivers +v0x2b90800_0 .net "AnandB", 0 0, L_0x2c04150; 1 drivers +v0x2b908b0_0 .net "AndNandOut", 0 0, L_0x2c050e0; 1 drivers +v0x2b90990_0 .net "B", 0 0, L_0x2bea340; 1 drivers +v0x2b90a10_0 .alias "Command", 2 0, v0x2bc67a0_0; +L_0x2c052b0 .part v0x2bc78e0_0, 0, 1; +S_0x2b90170 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0x2b90080; + .timescale -9 -12; +L_0x2c04dc0/d .functor NOT 1, L_0x2c052b0, C4<0>, C4<0>, C4<0>; +L_0x2c04dc0 .delay (10000,10000,10000) L_0x2c04dc0/d; +L_0x2c04e80/d .functor AND 1, L_0x2c04cb0, L_0x2c04dc0, C4<1>, C4<1>; +L_0x2c04e80 .delay (20000,20000,20000) L_0x2c04e80/d; +L_0x2c04f90/d .functor AND 1, L_0x2c04150, L_0x2c052b0, C4<1>, C4<1>; +L_0x2c04f90 .delay (20000,20000,20000) L_0x2c04f90/d; +L_0x2c050e0/d .functor OR 1, L_0x2c04e80, L_0x2c04f90, C4<0>, C4<0>; +L_0x2c050e0 .delay (20000,20000,20000) L_0x2c050e0/d; +v0x2b90260_0 .net "S", 0 0, L_0x2c052b0; 1 drivers +v0x2b902e0_0 .alias "in0", 0 0, v0x2b90780_0; +v0x2b90380_0 .alias "in1", 0 0, v0x2b90800_0; +v0x2b90420_0 .net "nS", 0 0, L_0x2c04dc0; 1 drivers +v0x2b904a0_0 .net "out0", 0 0, L_0x2c04e80; 1 drivers +v0x2b90540_0 .net "out1", 0 0, L_0x2c04f90; 1 drivers +v0x2b90620_0 .alias "outfinal", 0 0, v0x2b908b0_0; +S_0x2b8f350 .scope generate, "andbits[26]" "andbits[26]" 3 169, 3 169, S_0x2b8b740; + .timescale -9 -12; +P_0x2b8f448 .param/l "i" 3 169, +C4<011010>; +S_0x2b8f4c0 .scope module, "attempt" "AndNand" 3 171, 3 48, S_0x2b8f350; + .timescale -9 -12; +L_0x2bf7860/d .functor NAND 1, L_0x2bea0e0, L_0x2bea180, C4<1>, C4<1>; +L_0x2bf7860 .delay (10000,10000,10000) L_0x2bf7860/d; +L_0x2c049d0/d .functor NOT 1, L_0x2bf7860, C4<0>, C4<0>, C4<0>; +L_0x2c049d0 .delay (10000,10000,10000) L_0x2c049d0/d; +v0x2b8fb00_0 .net "A", 0 0, L_0x2bea0e0; 1 drivers +v0x2b8fbc0_0 .net "AandB", 0 0, L_0x2c049d0; 1 drivers +v0x2b8fc40_0 .net "AnandB", 0 0, L_0x2bf7860; 1 drivers +v0x2b8fcf0_0 .net "AndNandOut", 0 0, L_0x2be9ea0; 1 drivers +v0x2b8fdd0_0 .net "B", 0 0, L_0x2bea180; 1 drivers +v0x2b8fe50_0 .alias "Command", 2 0, v0x2bc67a0_0; +L_0x2c064b0 .part v0x2bc78e0_0, 0, 1; +S_0x2b8f5b0 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0x2b8f4c0; + .timescale -9 -12; +L_0x2c04b00/d .functor NOT 1, L_0x2c064b0, C4<0>, C4<0>, C4<0>; +L_0x2c04b00 .delay (10000,10000,10000) L_0x2c04b00/d; +L_0x2be9c40/d .functor AND 1, L_0x2c049d0, L_0x2c04b00, C4<1>, C4<1>; +L_0x2be9c40 .delay (20000,20000,20000) L_0x2be9c40/d; +L_0x2be9d50/d .functor AND 1, L_0x2bf7860, L_0x2c064b0, C4<1>, C4<1>; +L_0x2be9d50 .delay (20000,20000,20000) L_0x2be9d50/d; +L_0x2be9ea0/d .functor OR 1, L_0x2be9c40, L_0x2be9d50, C4<0>, C4<0>; +L_0x2be9ea0 .delay (20000,20000,20000) L_0x2be9ea0/d; +v0x2b8f6a0_0 .net "S", 0 0, L_0x2c064b0; 1 drivers +v0x2b8f720_0 .alias "in0", 0 0, v0x2b8fbc0_0; +v0x2b8f7c0_0 .alias "in1", 0 0, v0x2b8fc40_0; +v0x2b8f860_0 .net "nS", 0 0, L_0x2c04b00; 1 drivers +v0x2b8f8e0_0 .net "out0", 0 0, L_0x2be9c40; 1 drivers +v0x2b8f980_0 .net "out1", 0 0, L_0x2be9d50; 1 drivers +v0x2b8fa60_0 .alias "outfinal", 0 0, v0x2b8fcf0_0; +S_0x2b8e790 .scope generate, "andbits[27]" "andbits[27]" 3 169, 3 169, S_0x2b8b740; + .timescale -9 -12; +P_0x2b8e888 .param/l "i" 3 169, +C4<011011>; +S_0x2b8e900 .scope module, "attempt" "AndNand" 3 171, 3 48, S_0x2b8e790; + .timescale -9 -12; +L_0x2bea270/d .functor NAND 1, L_0x2c06f80, L_0x2c065f0, C4<1>, C4<1>; +L_0x2bea270 .delay (10000,10000,10000) L_0x2bea270/d; +L_0x2c06900/d .functor NOT 1, L_0x2bea270, C4<0>, C4<0>, C4<0>; +L_0x2c06900 .delay (10000,10000,10000) L_0x2c06900/d; +v0x2b8ef40_0 .net "A", 0 0, L_0x2c06f80; 1 drivers +v0x2b8f000_0 .net "AandB", 0 0, L_0x2c06900; 1 drivers +v0x2b8f080_0 .net "AnandB", 0 0, L_0x2bea270; 1 drivers +v0x2b8f130_0 .net "AndNandOut", 0 0, L_0x2c06cb0; 1 drivers +v0x2b8f210_0 .net "B", 0 0, L_0x2c065f0; 1 drivers +v0x2b8f290_0 .alias "Command", 2 0, v0x2bc67a0_0; +L_0x2c06e40 .part v0x2bc78e0_0, 0, 1; +S_0x2b8e9f0 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0x2b8e900; + .timescale -9 -12; +L_0x2c069f0/d .functor NOT 1, L_0x2c06e40, C4<0>, C4<0>, C4<0>; +L_0x2c069f0 .delay (10000,10000,10000) L_0x2c069f0/d; +L_0x2c06a90/d .functor AND 1, L_0x2c06900, L_0x2c069f0, C4<1>, C4<1>; +L_0x2c06a90 .delay (20000,20000,20000) L_0x2c06a90/d; +L_0x2c06b80/d .functor AND 1, L_0x2bea270, L_0x2c06e40, C4<1>, C4<1>; +L_0x2c06b80 .delay (20000,20000,20000) L_0x2c06b80/d; +L_0x2c06cb0/d .functor OR 1, L_0x2c06a90, L_0x2c06b80, C4<0>, C4<0>; +L_0x2c06cb0 .delay (20000,20000,20000) L_0x2c06cb0/d; +v0x2b8eae0_0 .net "S", 0 0, L_0x2c06e40; 1 drivers +v0x2b8eb60_0 .alias "in0", 0 0, v0x2b8f000_0; +v0x2b8ec00_0 .alias "in1", 0 0, v0x2b8f080_0; +v0x2b8eca0_0 .net "nS", 0 0, L_0x2c069f0; 1 drivers +v0x2b8ed20_0 .net "out0", 0 0, L_0x2c06a90; 1 drivers +v0x2b8edc0_0 .net "out1", 0 0, L_0x2c06b80; 1 drivers +v0x2b8eea0_0 .alias "outfinal", 0 0, v0x2b8f130_0; +S_0x2b8dbd0 .scope generate, "andbits[28]" "andbits[28]" 3 169, 3 169, S_0x2b8b740; + .timescale -9 -12; +P_0x2b8dcc8 .param/l "i" 3 169, +C4<011100>; +S_0x2b8dd40 .scope module, "attempt" "AndNand" 3 171, 3 48, S_0x2b8dbd0; + .timescale -9 -12; +L_0x2c066e0/d .functor NAND 1, L_0x2c07020, L_0x2c070c0, C4<1>, C4<1>; +L_0x2c066e0 .delay (10000,10000,10000) L_0x2c066e0/d; +L_0x2c072b0/d .functor NOT 1, L_0x2c066e0, C4<0>, C4<0>, C4<0>; +L_0x2c072b0 .delay (10000,10000,10000) L_0x2c072b0/d; +v0x2b8e380_0 .net "A", 0 0, L_0x2c07020; 1 drivers +v0x2b8e440_0 .net "AandB", 0 0, L_0x2c072b0; 1 drivers +v0x2b8e4c0_0 .net "AnandB", 0 0, L_0x2c066e0; 1 drivers +v0x2b8e570_0 .net "AndNandOut", 0 0, L_0x2c07660; 1 drivers +v0x2b8e650_0 .net "B", 0 0, L_0x2c070c0; 1 drivers +v0x2b8e6d0_0 .alias "Command", 2 0, v0x2bc67a0_0; +L_0x2c077f0 .part v0x2bc78e0_0, 0, 1; +S_0x2b8de30 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0x2b8dd40; + .timescale -9 -12; +L_0x2c073a0/d .functor NOT 1, L_0x2c077f0, C4<0>, C4<0>, C4<0>; +L_0x2c073a0 .delay (10000,10000,10000) L_0x2c073a0/d; +L_0x2c07440/d .functor AND 1, L_0x2c072b0, L_0x2c073a0, C4<1>, C4<1>; +L_0x2c07440 .delay (20000,20000,20000) L_0x2c07440/d; +L_0x2c07530/d .functor AND 1, L_0x2c066e0, L_0x2c077f0, C4<1>, C4<1>; +L_0x2c07530 .delay (20000,20000,20000) L_0x2c07530/d; +L_0x2c07660/d .functor OR 1, L_0x2c07440, L_0x2c07530, C4<0>, C4<0>; +L_0x2c07660 .delay (20000,20000,20000) L_0x2c07660/d; +v0x2b8df20_0 .net "S", 0 0, L_0x2c077f0; 1 drivers +v0x2b8dfa0_0 .alias "in0", 0 0, v0x2b8e440_0; +v0x2b8e040_0 .alias "in1", 0 0, v0x2b8e4c0_0; +v0x2b8e0e0_0 .net "nS", 0 0, L_0x2c073a0; 1 drivers +v0x2b8e160_0 .net "out0", 0 0, L_0x2c07440; 1 drivers +v0x2b8e200_0 .net "out1", 0 0, L_0x2c07530; 1 drivers +v0x2b8e2e0_0 .alias "outfinal", 0 0, v0x2b8e570_0; +S_0x2b8d010 .scope generate, "andbits[29]" "andbits[29]" 3 169, 3 169, S_0x2b8b740; + .timescale -9 -12; +P_0x2b8d108 .param/l "i" 3 169, +C4<011101>; +S_0x2b8d180 .scope module, "attempt" "AndNand" 3 171, 3 48, S_0x2b8d010; + .timescale -9 -12; +L_0x2c071b0/d .functor NAND 1, L_0x2bfd5b0, L_0x2bfd650, C4<1>, C4<1>; +L_0x2c071b0 .delay (10000,10000,10000) L_0x2c071b0/d; +L_0x2c07c70/d .functor NOT 1, L_0x2c071b0, C4<0>, C4<0>, C4<0>; +L_0x2c07c70 .delay (10000,10000,10000) L_0x2c07c70/d; +v0x2b8d7c0_0 .net "A", 0 0, L_0x2bfd5b0; 1 drivers +v0x2b8d880_0 .net "AandB", 0 0, L_0x2c07c70; 1 drivers +v0x2b8d900_0 .net "AnandB", 0 0, L_0x2c071b0; 1 drivers +v0x2b8d9b0_0 .net "AndNandOut", 0 0, L_0x2c08020; 1 drivers +v0x2b8da90_0 .net "B", 0 0, L_0x2bfd650; 1 drivers +v0x2b8db10_0 .alias "Command", 2 0, v0x2bc67a0_0; +L_0x2c081b0 .part v0x2bc78e0_0, 0, 1; +S_0x2b8d270 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0x2b8d180; + .timescale -9 -12; +L_0x2c07d60/d .functor NOT 1, L_0x2c081b0, C4<0>, C4<0>, C4<0>; +L_0x2c07d60 .delay (10000,10000,10000) L_0x2c07d60/d; +L_0x2c07e00/d .functor AND 1, L_0x2c07c70, L_0x2c07d60, C4<1>, C4<1>; +L_0x2c07e00 .delay (20000,20000,20000) L_0x2c07e00/d; +L_0x2c07ef0/d .functor AND 1, L_0x2c071b0, L_0x2c081b0, C4<1>, C4<1>; +L_0x2c07ef0 .delay (20000,20000,20000) L_0x2c07ef0/d; +L_0x2c08020/d .functor OR 1, L_0x2c07e00, L_0x2c07ef0, C4<0>, C4<0>; +L_0x2c08020 .delay (20000,20000,20000) L_0x2c08020/d; +v0x2b8d360_0 .net "S", 0 0, L_0x2c081b0; 1 drivers +v0x2b8d3e0_0 .alias "in0", 0 0, v0x2b8d880_0; +v0x2b8d480_0 .alias "in1", 0 0, v0x2b8d900_0; +v0x2b8d520_0 .net "nS", 0 0, L_0x2c07d60; 1 drivers +v0x2b8d5a0_0 .net "out0", 0 0, L_0x2c07e00; 1 drivers +v0x2b8d640_0 .net "out1", 0 0, L_0x2c07ef0; 1 drivers +v0x2b8d720_0 .alias "outfinal", 0 0, v0x2b8d9b0_0; +S_0x2b8c450 .scope generate, "andbits[30]" "andbits[30]" 3 169, 3 169, S_0x2b8b740; + .timescale -9 -12; +P_0x2b8c548 .param/l "i" 3 169, +C4<011110>; +S_0x2b8c5c0 .scope module, "attempt" "AndNand" 3 171, 3 48, S_0x2b8c450; + .timescale -9 -12; +L_0x2bfd740/d .functor NAND 1, L_0x2c08700, L_0x2c087a0, C4<1>, C4<1>; +L_0x2bfd740 .delay (10000,10000,10000) L_0x2bfd740/d; +L_0x2c07a10/d .functor NOT 1, L_0x2bfd740, C4<0>, C4<0>, C4<0>; +L_0x2c07a10 .delay (10000,10000,10000) L_0x2c07a10/d; +v0x2b8cc00_0 .net "A", 0 0, L_0x2c08700; 1 drivers +v0x2b8ccc0_0 .net "AandB", 0 0, L_0x2c07a10; 1 drivers +v0x2b8cd40_0 .net "AnandB", 0 0, L_0x2bfd740; 1 drivers +v0x2b8cdf0_0 .net "AndNandOut", 0 0, L_0x2c08be0; 1 drivers +v0x2b8ced0_0 .net "B", 0 0, L_0x2c087a0; 1 drivers +v0x2b8cf50_0 .alias "Command", 2 0, v0x2bc67a0_0; +L_0x2c08d70 .part v0x2bc78e0_0, 0, 1; +S_0x2b8c6b0 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0x2b8c5c0; + .timescale -9 -12; +L_0x2c07b40/d .functor NOT 1, L_0x2c08d70, C4<0>, C4<0>, C4<0>; +L_0x2c07b40 .delay (10000,10000,10000) L_0x2c07b40/d; +L_0x2c089c0/d .functor AND 1, L_0x2c07a10, L_0x2c07b40, C4<1>, C4<1>; +L_0x2c089c0 .delay (20000,20000,20000) L_0x2c089c0/d; +L_0x2c08ab0/d .functor AND 1, L_0x2bfd740, L_0x2c08d70, C4<1>, C4<1>; +L_0x2c08ab0 .delay (20000,20000,20000) L_0x2c08ab0/d; +L_0x2c08be0/d .functor OR 1, L_0x2c089c0, L_0x2c08ab0, C4<0>, C4<0>; +L_0x2c08be0 .delay (20000,20000,20000) L_0x2c08be0/d; +v0x2b8c7a0_0 .net "S", 0 0, L_0x2c08d70; 1 drivers +v0x2b8c820_0 .alias "in0", 0 0, v0x2b8ccc0_0; +v0x2b8c8c0_0 .alias "in1", 0 0, v0x2b8cd40_0; +v0x2b8c960_0 .net "nS", 0 0, L_0x2c07b40; 1 drivers +v0x2b8c9e0_0 .net "out0", 0 0, L_0x2c089c0; 1 drivers +v0x2b8ca80_0 .net "out1", 0 0, L_0x2c08ab0; 1 drivers +v0x2b8cb60_0 .alias "outfinal", 0 0, v0x2b8cdf0_0; +S_0x2b8b870 .scope generate, "andbits[31]" "andbits[31]" 3 169, 3 169, S_0x2b8b740; + .timescale -9 -12; +P_0x2b8b968 .param/l "i" 3 169, +C4<011111>; +S_0x2b8b9e0 .scope module, "attempt" "AndNand" 3 171, 3 48, S_0x2b8b870; + .timescale -9 -12; +L_0x2c08890/d .functor NAND 1, L_0x2c09860, L_0x2c08eb0, C4<1>, C4<1>; +L_0x2c08890 .delay (10000,10000,10000) L_0x2c08890/d; +L_0x2c091e0/d .functor NOT 1, L_0x2c08890, C4<0>, C4<0>, C4<0>; +L_0x2c091e0 .delay (10000,10000,10000) L_0x2c091e0/d; +v0x2b8c040_0 .net "A", 0 0, L_0x2c09860; 1 drivers +v0x2b8c100_0 .net "AandB", 0 0, L_0x2c091e0; 1 drivers +v0x2b8c180_0 .net "AnandB", 0 0, L_0x2c08890; 1 drivers +v0x2b8c230_0 .net "AndNandOut", 0 0, L_0x2c09590; 1 drivers +v0x2b8c310_0 .net "B", 0 0, L_0x2c08eb0; 1 drivers +v0x2b8c390_0 .alias "Command", 2 0, v0x2bc67a0_0; +L_0x2c09720 .part v0x2bc78e0_0, 0, 1; +S_0x2b8bad0 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0x2b8b9e0; + .timescale -9 -12; +L_0x2c092d0/d .functor NOT 1, L_0x2c09720, C4<0>, C4<0>, C4<0>; +L_0x2c092d0 .delay (10000,10000,10000) L_0x2c092d0/d; +L_0x2c09370/d .functor AND 1, L_0x2c091e0, L_0x2c092d0, C4<1>, C4<1>; +L_0x2c09370 .delay (20000,20000,20000) L_0x2c09370/d; +L_0x2c09460/d .functor AND 1, L_0x2c08890, L_0x2c09720, C4<1>, C4<1>; +L_0x2c09460 .delay (20000,20000,20000) L_0x2c09460/d; +L_0x2c09590/d .functor OR 1, L_0x2c09370, L_0x2c09460, C4<0>, C4<0>; +L_0x2c09590 .delay (20000,20000,20000) L_0x2c09590/d; +v0x2b8bbc0_0 .net "S", 0 0, L_0x2c09720; 1 drivers +v0x2b8bc60_0 .alias "in0", 0 0, v0x2b8c100_0; +v0x2b8bd00_0 .alias "in1", 0 0, v0x2b8c180_0; +v0x2b8bda0_0 .net "nS", 0 0, L_0x2c092d0; 1 drivers +v0x2b8be20_0 .net "out0", 0 0, L_0x2c09370; 1 drivers +v0x2b8bec0_0 .net "out1", 0 0, L_0x2c09460; 1 drivers +v0x2b8bfa0_0 .alias "outfinal", 0 0, v0x2b8c230_0; +S_0x2b62fd0 .scope module, "trial2" "OrNorXor32" 2 145, 3 177, S_0x270e6d0; + .timescale -9 -12; +P_0x2b5fb08 .param/l "size" 3 184, +C4<0100000>; +v0x2b8b420_0 .alias "A", 31 0, v0x2bc6580_0; +v0x2b8b530_0 .alias "B", 31 0, v0x2bc66a0_0; +v0x2b8b640_0 .alias "Command", 2 0, v0x2bc67a0_0; +v0x2b8b6c0_0 .alias "OrNorXorOut", 31 0, v0x2bc79e0_0; +L_0x2c0b350 .part/pv L_0x2c0b120, 1, 1, 32; +L_0x2c0b480 .part v0x2bc7660_0, 1, 1; +L_0x2c0b520 .part v0x2bc7860_0, 1, 1; +L_0x2c0c590 .part/pv L_0x2c0c320, 2, 1, 32; +L_0x2c0c630 .part v0x2bc7660_0, 2, 1; +L_0x2c0c6d0 .part v0x2bc7860_0, 2, 1; +L_0x2c0d7c0 .part/pv L_0x2c0d590, 3, 1, 32; +L_0x2c0d860 .part v0x2bc7660_0, 3, 1; +L_0x2c0d900 .part v0x2bc7860_0, 3, 1; +L_0x2c0ea70 .part/pv L_0x2c0e800, 4, 1, 32; +L_0x2c0eb70 .part v0x2bc7660_0, 4, 1; +L_0x2c0ec10 .part v0x2bc7860_0, 4, 1; +L_0x2c0fd70 .part/pv L_0x2c0fb00, 5, 1, 32; +L_0x2c0ff20 .part v0x2bc7660_0, 5, 1; +L_0x2c0ffc0 .part v0x2bc7860_0, 5, 1; +L_0x2c11160 .part/pv L_0x2c10ef0, 6, 1, 32; +L_0x2c11200 .part v0x2bc7660_0, 6, 1; +L_0x2c112a0 .part v0x2bc7860_0, 6, 1; +L_0x2c12460 .part/pv L_0x2c121f0, 7, 1, 32; +L_0x2c12500 .part v0x2bc7660_0, 7, 1; +L_0x2c11340 .part v0x2bc7860_0, 7, 1; +L_0x2c13750 .part/pv L_0x2c134e0, 8, 1, 32; +L_0x2c125a0 .part v0x2bc7660_0, 8, 1; +L_0x2c138b0 .part v0x2bc7860_0, 8, 1; +L_0x2c14a60 .part/pv L_0x2c147f0, 9, 1, 32; +L_0x2c14b00 .part v0x2bc7660_0, 9, 1; +L_0x2c13950 .part v0x2bc7860_0, 9, 1; +L_0x2c15d60 .part/pv L_0x2c15af0, 10, 1, 32; +L_0x2c14ba0 .part v0x2bc7660_0, 10, 1; +L_0x2c15ef0 .part v0x2bc7860_0, 10, 1; +L_0x2c17060 .part/pv L_0x2c16df0, 11, 1, 32; +L_0x2c17100 .part v0x2bc7660_0, 11, 1; +L_0x2c15f90 .part v0x2bc7860_0, 11, 1; +L_0x2c18350 .part/pv L_0x2c180e0, 12, 1, 32; +L_0x2c171a0 .part v0x2bc7660_0, 12, 1; +L_0x2c18510 .part v0x2bc7860_0, 12, 1; +L_0x2c19670 .part/pv L_0x2c19400, 13, 1, 32; +L_0x2c0fe10 .part v0x2bc7660_0, 13, 1; +L_0x2c185b0 .part v0x2bc7860_0, 13, 1; +L_0x2c1aa80 .part/pv L_0x2c1a810, 14, 1, 32; +L_0x2c19920 .part v0x2bc7660_0, 14, 1; +L_0x2c199c0 .part v0x2bc7860_0, 14, 1; +L_0x2c1bd80 .part/pv L_0x2c1bb10, 15, 1, 32; +L_0x2c1be20 .part v0x2bc7660_0, 15, 1; +L_0x2c1ab20 .part v0x2bc7860_0, 15, 1; +L_0x2c1d070 .part/pv L_0x2c1ce00, 16, 1, 32; +L_0x2c1bec0 .part v0x2bc7660_0, 16, 1; +L_0x2c1bf60 .part v0x2bc7860_0, 16, 1; +L_0x2c1e380 .part/pv L_0x2c1e110, 17, 1, 32; +L_0x2c1e420 .part v0x2bc7660_0, 17, 1; +L_0x2c1d110 .part v0x2bc7860_0, 17, 1; +L_0x2c1f670 .part/pv L_0x2c1f400, 18, 1, 32; +L_0x2c1e4c0 .part v0x2bc7660_0, 18, 1; +L_0x2c1e560 .part v0x2bc7860_0, 18, 1; +L_0x2c20970 .part/pv L_0x2c20700, 19, 1, 32; +L_0x2c20a10 .part v0x2bc7660_0, 19, 1; +L_0x2c1f710 .part v0x2bc7860_0, 19, 1; +L_0x2c21c70 .part/pv L_0x2c21a00, 20, 1, 32; +L_0x2c20ab0 .part v0x2bc7660_0, 20, 1; +L_0x2c20b50 .part v0x2bc7860_0, 20, 1; +L_0x2c22f80 .part/pv L_0x2c22d10, 21, 1, 32; +L_0x2c23020 .part v0x2bc7660_0, 21, 1; +L_0x2c21d10 .part v0x2bc7860_0, 21, 1; +L_0x2c24270 .part/pv L_0x2c24000, 22, 1, 32; +L_0x2c230c0 .part v0x2bc7660_0, 22, 1; +L_0x2c23160 .part v0x2bc7860_0, 22, 1; +L_0x2c25570 .part/pv L_0x2c25300, 23, 1, 32; +L_0x2c25610 .part v0x2bc7660_0, 23, 1; +L_0x2c24310 .part v0x2bc7860_0, 23, 1; +L_0x2c26870 .part/pv L_0x2c26600, 24, 1, 32; +L_0x2c256b0 .part v0x2bc7660_0, 24, 1; +L_0x2c25750 .part v0x2bc7860_0, 24, 1; +L_0x2c27b70 .part/pv L_0x2c27900, 25, 1, 32; +L_0x2c27c10 .part v0x2bc7660_0, 25, 1; +L_0x2c26910 .part v0x2bc7860_0, 25, 1; +L_0x2c28e60 .part/pv L_0x2c28bf0, 26, 1, 32; +L_0x2c27cb0 .part v0x2bc7660_0, 26, 1; +L_0x2c27d50 .part v0x2bc7860_0, 26, 1; +L_0x2c2a170 .part/pv L_0x2c29f00, 27, 1, 32; +L_0x2c2a210 .part v0x2bc7660_0, 27, 1; +L_0x2c28f00 .part v0x2bc7860_0, 27, 1; +L_0x2c2b470 .part/pv L_0x2c2b200, 28, 1, 32; +L_0x2c2a2b0 .part v0x2bc7660_0, 28, 1; +L_0x2c2a350 .part v0x2bc7860_0, 28, 1; +L_0x2c2c770 .part/pv L_0x2c2c500, 29, 1, 32; +L_0x2c19710 .part v0x2bc7660_0, 29, 1; +L_0x2c197b0 .part v0x2bc7860_0, 29, 1; +L_0x2c2daa0 .part/pv L_0x2c2d870, 30, 1, 32; +L_0x2c2cc20 .part v0x2bc7660_0, 30, 1; +L_0x2c2ccc0 .part v0x2bc7860_0, 30, 1; +L_0x2c2ebf0 .part/pv L_0x2c2e9c0, 31, 1, 32; +L_0x2c2ec90 .part v0x2bc7660_0, 31, 1; +L_0x2c2db40 .part v0x2bc7860_0, 31, 1; +L_0x2c2fe80 .part/pv L_0x2c2fc10, 0, 1, 32; +L_0x2c2ed30 .part v0x2bc7660_0, 0, 1; +L_0x2c2edd0 .part v0x2bc7860_0, 0, 1; +S_0x2b8a1e0 .scope module, "attempt2" "OrNorXor" 3 192, 3 64, S_0x2b62fd0; + .timescale -9 -12; +L_0x2c2dbe0/d .functor NOR 1, L_0x2c2ed30, L_0x2c2edd0, C4<0>, C4<0>; +L_0x2c2dbe0 .delay (10000,10000,10000) L_0x2c2dbe0/d; +L_0x2c2dcd0/d .functor NOT 1, L_0x2c2dbe0, C4<0>, C4<0>, C4<0>; +L_0x2c2dcd0 .delay (10000,10000,10000) L_0x2c2dcd0/d; +L_0x2c2f020/d .functor NAND 1, L_0x2c2ed30, L_0x2c2edd0, C4<1>, C4<1>; +L_0x2c2f020 .delay (10000,10000,10000) L_0x2c2f020/d; +L_0x2c2f120/d .functor NAND 1, L_0x2c2f020, L_0x2c2dcd0, C4<1>, C4<1>; +L_0x2c2f120 .delay (10000,10000,10000) L_0x2c2f120/d; +L_0x2c2f210/d .functor NOT 1, L_0x2c2f120, C4<0>, C4<0>, C4<0>; +L_0x2c2f210 .delay (10000,10000,10000) L_0x2c2f210/d; +v0x2b8ad30_0 .net "A", 0 0, L_0x2c2ed30; 1 drivers +v0x2b8add0_0 .net "AnandB", 0 0, L_0x2c2f020; 1 drivers +v0x2b8ae70_0 .net "AnorB", 0 0, L_0x2c2dbe0; 1 drivers +v0x2b8af20_0 .net "AorB", 0 0, L_0x2c2dcd0; 1 drivers +v0x2b8b000_0 .net "AxorB", 0 0, L_0x2c2f210; 1 drivers +v0x2b8b0b0_0 .net "B", 0 0, L_0x2c2edd0; 1 drivers +v0x2b8b170_0 .alias "Command", 2 0, v0x2bc67a0_0; +v0x2b8b1f0_0 .net "OrNorXorOut", 0 0, L_0x2c2fc10; 1 drivers +v0x2b8b270_0 .net "XorNor", 0 0, L_0x2c2f690; 1 drivers +v0x2b8b340_0 .net "nXor", 0 0, L_0x2c2f120; 1 drivers +L_0x2c2f810 .part v0x2bc78e0_0, 2, 1; +L_0x2c2fde0 .part v0x2bc78e0_0, 0, 1; +S_0x2b8a7c0 .scope module, "mux0" "TwoInMux" 3 83, 3 8, S_0x2b8a1e0; + .timescale -9 -12; +L_0x2c2f370/d .functor NOT 1, L_0x2c2f810, C4<0>, C4<0>, C4<0>; +L_0x2c2f370 .delay (10000,10000,10000) L_0x2c2f370/d; +L_0x2c2f430/d .functor AND 1, L_0x2c2f210, L_0x2c2f370, C4<1>, C4<1>; +L_0x2c2f430 .delay (20000,20000,20000) L_0x2c2f430/d; +L_0x2c2f540/d .functor AND 1, L_0x2c2dbe0, L_0x2c2f810, C4<1>, C4<1>; +L_0x2c2f540 .delay (20000,20000,20000) L_0x2c2f540/d; +L_0x2c2f690/d .functor OR 1, L_0x2c2f430, L_0x2c2f540, C4<0>, C4<0>; +L_0x2c2f690 .delay (20000,20000,20000) L_0x2c2f690/d; +v0x2b8a8b0_0 .net "S", 0 0, L_0x2c2f810; 1 drivers +v0x2b8a970_0 .alias "in0", 0 0, v0x2b8b000_0; +v0x2b8aa10_0 .alias "in1", 0 0, v0x2b8ae70_0; +v0x2b8aab0_0 .net "nS", 0 0, L_0x2c2f370; 1 drivers +v0x2b8ab30_0 .net "out0", 0 0, L_0x2c2f430; 1 drivers +v0x2b8abd0_0 .net "out1", 0 0, L_0x2c2f540; 1 drivers +v0x2b8acb0_0 .alias "outfinal", 0 0, v0x2b8b270_0; +S_0x2b8a2d0 .scope module, "mux1" "TwoInMux" 3 84, 3 8, S_0x2b8a1e0; + .timescale -9 -12; +L_0x2c2f8b0/d .functor NOT 1, L_0x2c2fde0, C4<0>, C4<0>, C4<0>; +L_0x2c2f8b0 .delay (10000,10000,10000) L_0x2c2f8b0/d; +L_0x2c2f970/d .functor AND 1, L_0x2c2f690, L_0x2c2f8b0, C4<1>, C4<1>; +L_0x2c2f970 .delay (20000,20000,20000) L_0x2c2f970/d; +L_0x2c2fac0/d .functor AND 1, L_0x2c2dcd0, L_0x2c2fde0, C4<1>, C4<1>; +L_0x2c2fac0 .delay (20000,20000,20000) L_0x2c2fac0/d; +L_0x2c2fc10/d .functor OR 1, L_0x2c2f970, L_0x2c2fac0, C4<0>, C4<0>; +L_0x2c2fc10 .delay (20000,20000,20000) L_0x2c2fc10/d; +v0x2b8a3c0_0 .net "S", 0 0, L_0x2c2fde0; 1 drivers +v0x2b8a440_0 .alias "in0", 0 0, v0x2b8b270_0; +v0x2b8a4c0_0 .alias "in1", 0 0, v0x2b8af20_0; +v0x2b8a560_0 .net "nS", 0 0, L_0x2c2f8b0; 1 drivers +v0x2b8a5e0_0 .net "out0", 0 0, L_0x2c2f970; 1 drivers +v0x2b8a680_0 .net "out1", 0 0, L_0x2c2fac0; 1 drivers +v0x2b8a720_0 .alias "outfinal", 0 0, v0x2b8b1f0_0; +S_0x2b88e10 .scope generate, "orbits[1]" "orbits[1]" 3 196, 3 196, S_0x2b62fd0; + .timescale -9 -12; +P_0x2b88b28 .param/l "i" 3 196, +C4<01>; +S_0x2b88f40 .scope module, "attempt" "OrNorXor" 3 198, 3 64, S_0x2b88e10; + .timescale -9 -12; +L_0x2c09a90/d .functor NOR 1, L_0x2c0b480, L_0x2c0b520, C4<0>, C4<0>; +L_0x2c09a90 .delay (10000,10000,10000) L_0x2c09a90/d; +L_0x2c0a520/d .functor NOT 1, L_0x2c09a90, C4<0>, C4<0>, C4<0>; +L_0x2c0a520 .delay (10000,10000,10000) L_0x2c0a520/d; +L_0x2c0a610/d .functor NAND 1, L_0x2c0b480, L_0x2c0b520, C4<1>, C4<1>; +L_0x2c0a610 .delay (10000,10000,10000) L_0x2c0a610/d; +L_0x2c0a750/d .functor NAND 1, L_0x2c0a610, L_0x2c0a520, C4<1>, C4<1>; +L_0x2c0a750 .delay (10000,10000,10000) L_0x2c0a750/d; +L_0x2c0a840/d .functor NOT 1, L_0x2c0a750, C4<0>, C4<0>, C4<0>; +L_0x2c0a840 .delay (10000,10000,10000) L_0x2c0a840/d; +v0x2b89ab0_0 .net "A", 0 0, L_0x2c0b480; 1 drivers +v0x2b89b70_0 .net "AnandB", 0 0, L_0x2c0a610; 1 drivers +v0x2b89c10_0 .net "AnorB", 0 0, L_0x2c09a90; 1 drivers +v0x2b89c90_0 .net "AorB", 0 0, L_0x2c0a520; 1 drivers +v0x2b89d70_0 .net "AxorB", 0 0, L_0x2c0a840; 1 drivers +v0x2b89e20_0 .net "B", 0 0, L_0x2c0b520; 1 drivers +v0x2b89ee0_0 .alias "Command", 2 0, v0x2bc67a0_0; +v0x2b89f60_0 .net "OrNorXorOut", 0 0, L_0x2c0b120; 1 drivers +v0x2b8a030_0 .net "XorNor", 0 0, L_0x2c0ac40; 1 drivers +v0x2b8a100_0 .net "nXor", 0 0, L_0x2c0a750; 1 drivers +L_0x2c0ad80 .part v0x2bc78e0_0, 2, 1; +L_0x2c0b2b0 .part v0x2bc78e0_0, 0, 1; +S_0x2b89540 .scope module, "mux0" "TwoInMux" 3 83, 3 8, S_0x2b88f40; + .timescale -9 -12; +L_0x2c0a980/d .functor NOT 1, L_0x2c0ad80, C4<0>, C4<0>, C4<0>; +L_0x2c0a980 .delay (10000,10000,10000) L_0x2c0a980/d; +L_0x2c0aa20/d .functor AND 1, L_0x2c0a840, L_0x2c0a980, C4<1>, C4<1>; +L_0x2c0aa20 .delay (20000,20000,20000) L_0x2c0aa20/d; +L_0x2c0ab10/d .functor AND 1, L_0x2c09a90, L_0x2c0ad80, C4<1>, C4<1>; +L_0x2c0ab10 .delay (20000,20000,20000) L_0x2c0ab10/d; +L_0x2c0ac40/d .functor OR 1, L_0x2c0aa20, L_0x2c0ab10, C4<0>, C4<0>; +L_0x2c0ac40 .delay (20000,20000,20000) L_0x2c0ac40/d; +v0x2b89630_0 .net "S", 0 0, L_0x2c0ad80; 1 drivers +v0x2b896f0_0 .alias "in0", 0 0, v0x2b89d70_0; +v0x2b89790_0 .alias "in1", 0 0, v0x2b89c10_0; +v0x2b89830_0 .net "nS", 0 0, L_0x2c0a980; 1 drivers +v0x2b898b0_0 .net "out0", 0 0, L_0x2c0aa20; 1 drivers +v0x2b89950_0 .net "out1", 0 0, L_0x2c0ab10; 1 drivers +v0x2b89a30_0 .alias "outfinal", 0 0, v0x2b8a030_0; +S_0x2b89030 .scope module, "mux1" "TwoInMux" 3 84, 3 8, S_0x2b88f40; + .timescale -9 -12; +L_0x2c0ae20/d .functor NOT 1, L_0x2c0b2b0, C4<0>, C4<0>, C4<0>; +L_0x2c0ae20 .delay (10000,10000,10000) L_0x2c0ae20/d; +L_0x2c0aec0/d .functor AND 1, L_0x2c0ac40, L_0x2c0ae20, C4<1>, C4<1>; +L_0x2c0aec0 .delay (20000,20000,20000) L_0x2c0aec0/d; +L_0x2c0aff0/d .functor AND 1, L_0x2c0a520, L_0x2c0b2b0, C4<1>, C4<1>; +L_0x2c0aff0 .delay (20000,20000,20000) L_0x2c0aff0/d; +L_0x2c0b120/d .functor OR 1, L_0x2c0aec0, L_0x2c0aff0, C4<0>, C4<0>; +L_0x2c0b120 .delay (20000,20000,20000) L_0x2c0b120/d; +v0x2b89120_0 .net "S", 0 0, L_0x2c0b2b0; 1 drivers +v0x2b891a0_0 .alias "in0", 0 0, v0x2b8a030_0; +v0x2b89220_0 .alias "in1", 0 0, v0x2b89c90_0; +v0x2b892a0_0 .net "nS", 0 0, L_0x2c0ae20; 1 drivers +v0x2b89320_0 .net "out0", 0 0, L_0x2c0aec0; 1 drivers +v0x2b893c0_0 .net "out1", 0 0, L_0x2c0aff0; 1 drivers +v0x2b894a0_0 .alias "outfinal", 0 0, v0x2b89f60_0; +S_0x2b3c7e0 .scope generate, "orbits[2]" "orbits[2]" 3 196, 3 196, S_0x2b62fd0; + .timescale -9 -12; +P_0x2b86f48 .param/l "i" 3 196, +C4<010>; +S_0x2b3c910 .scope module, "attempt" "OrNorXor" 3 198, 3 64, S_0x2b3c7e0; + .timescale -9 -12; +L_0x2c0b5c0/d .functor NOR 1, L_0x2c0c630, L_0x2c0c6d0, C4<0>, C4<0>; +L_0x2c0b5c0 .delay (10000,10000,10000) L_0x2c0b5c0/d; +L_0x2c0b660/d .functor NOT 1, L_0x2c0b5c0, C4<0>, C4<0>, C4<0>; +L_0x2c0b660 .delay (10000,10000,10000) L_0x2c0b660/d; +L_0x2c0b750/d .functor NAND 1, L_0x2c0c630, L_0x2c0c6d0, C4<1>, C4<1>; +L_0x2c0b750 .delay (10000,10000,10000) L_0x2c0b750/d; +L_0x2c0b890/d .functor NAND 1, L_0x2c0b750, L_0x2c0b660, C4<1>, C4<1>; +L_0x2c0b890 .delay (10000,10000,10000) L_0x2c0b890/d; +L_0x2c0b980/d .functor NOT 1, L_0x2c0b890, C4<0>, C4<0>, C4<0>; +L_0x2c0b980 .delay (10000,10000,10000) L_0x2c0b980/d; +v0x2b88720_0 .net "A", 0 0, L_0x2c0c630; 1 drivers +v0x2b887c0_0 .net "AnandB", 0 0, L_0x2c0b750; 1 drivers +v0x2b88860_0 .net "AnorB", 0 0, L_0x2c0b5c0; 1 drivers +v0x2b88910_0 .net "AorB", 0 0, L_0x2c0b660; 1 drivers +v0x2b889f0_0 .net "AxorB", 0 0, L_0x2c0b980; 1 drivers +v0x2b88aa0_0 .net "B", 0 0, L_0x2c0c6d0; 1 drivers +v0x2b88b60_0 .alias "Command", 2 0, v0x2bc67a0_0; +v0x2b88be0_0 .net "OrNorXorOut", 0 0, L_0x2c0c320; 1 drivers +v0x2b88c60_0 .net "XorNor", 0 0, L_0x2c0bda0; 1 drivers +v0x2b88d30_0 .net "nXor", 0 0, L_0x2c0b890; 1 drivers +L_0x2c0bf20 .part v0x2bc78e0_0, 2, 1; +L_0x2c0c4f0 .part v0x2bc78e0_0, 0, 1; +S_0x2b881b0 .scope module, "mux0" "TwoInMux" 3 83, 3 8, S_0x2b3c910; + .timescale -9 -12; +L_0x2c0bac0/d .functor NOT 1, L_0x2c0bf20, C4<0>, C4<0>, C4<0>; +L_0x2c0bac0 .delay (10000,10000,10000) L_0x2c0bac0/d; +L_0x2c0bb60/d .functor AND 1, L_0x2c0b980, L_0x2c0bac0, C4<1>, C4<1>; +L_0x2c0bb60 .delay (20000,20000,20000) L_0x2c0bb60/d; +L_0x2c0bc50/d .functor AND 1, L_0x2c0b5c0, L_0x2c0bf20, C4<1>, C4<1>; +L_0x2c0bc50 .delay (20000,20000,20000) L_0x2c0bc50/d; +L_0x2c0bda0/d .functor OR 1, L_0x2c0bb60, L_0x2c0bc50, C4<0>, C4<0>; +L_0x2c0bda0 .delay (20000,20000,20000) L_0x2c0bda0/d; +v0x2b882a0_0 .net "S", 0 0, L_0x2c0bf20; 1 drivers +v0x2b88360_0 .alias "in0", 0 0, v0x2b889f0_0; +v0x2b88400_0 .alias "in1", 0 0, v0x2b88860_0; +v0x2b884a0_0 .net "nS", 0 0, L_0x2c0bac0; 1 drivers +v0x2b88520_0 .net "out0", 0 0, L_0x2c0bb60; 1 drivers +v0x2b885c0_0 .net "out1", 0 0, L_0x2c0bc50; 1 drivers +v0x2b886a0_0 .alias "outfinal", 0 0, v0x2b88c60_0; +S_0x2b3ca00 .scope module, "mux1" "TwoInMux" 3 84, 3 8, S_0x2b3c910; + .timescale -9 -12; +L_0x2c0bfc0/d .functor NOT 1, L_0x2c0c4f0, C4<0>, C4<0>, C4<0>; +L_0x2c0bfc0 .delay (10000,10000,10000) L_0x2c0bfc0/d; +L_0x2c0c080/d .functor AND 1, L_0x2c0bda0, L_0x2c0bfc0, C4<1>, C4<1>; +L_0x2c0c080 .delay (20000,20000,20000) L_0x2c0c080/d; +L_0x2c0c1d0/d .functor AND 1, L_0x2c0b660, L_0x2c0c4f0, C4<1>, C4<1>; +L_0x2c0c1d0 .delay (20000,20000,20000) L_0x2c0c1d0/d; +L_0x2c0c320/d .functor OR 1, L_0x2c0c080, L_0x2c0c1d0, C4<0>, C4<0>; +L_0x2c0c320 .delay (20000,20000,20000) L_0x2c0c320/d; +v0x2b3caf0_0 .net "S", 0 0, L_0x2c0c4f0; 1 drivers +v0x2b3cb70_0 .alias "in0", 0 0, v0x2b88c60_0; +v0x2b3cc10_0 .alias "in1", 0 0, v0x2b88910_0; +v0x2b3ccb0_0 .net "nS", 0 0, L_0x2c0bfc0; 1 drivers +v0x2b3cd30_0 .net "out0", 0 0, L_0x2c0c080; 1 drivers +v0x2b88030_0 .net "out1", 0 0, L_0x2c0c1d0; 1 drivers +v0x2b88110_0 .alias "outfinal", 0 0, v0x2b88be0_0; +S_0x2b85e60 .scope generate, "orbits[3]" "orbits[3]" 3 196, 3 196, S_0x2b62fd0; + .timescale -9 -12; +P_0x2b85b78 .param/l "i" 3 196, +C4<011>; +S_0x2b85f90 .scope module, "attempt" "OrNorXor" 3 198, 3 64, S_0x2b85e60; + .timescale -9 -12; +L_0x2c0c7b0/d .functor NOR 1, L_0x2c0d860, L_0x2c0d900, C4<0>, C4<0>; +L_0x2c0c7b0 .delay (10000,10000,10000) L_0x2c0c7b0/d; +L_0x2c0c8a0/d .functor NOT 1, L_0x2c0c7b0, C4<0>, C4<0>, C4<0>; +L_0x2c0c8a0 .delay (10000,10000,10000) L_0x2c0c8a0/d; +L_0x2c0c9b0/d .functor NAND 1, L_0x2c0d860, L_0x2c0d900, C4<1>, C4<1>; +L_0x2c0c9b0 .delay (10000,10000,10000) L_0x2c0c9b0/d; +L_0x2c0cb10/d .functor NAND 1, L_0x2c0c9b0, L_0x2c0c8a0, C4<1>, C4<1>; +L_0x2c0cb10 .delay (10000,10000,10000) L_0x2c0cb10/d; +L_0x2c0cc20/d .functor NOT 1, L_0x2c0cb10, C4<0>, C4<0>, C4<0>; +L_0x2c0cc20 .delay (10000,10000,10000) L_0x2c0cc20/d; +v0x2b86b40_0 .net "A", 0 0, L_0x2c0d860; 1 drivers +v0x2b86be0_0 .net "AnandB", 0 0, L_0x2c0c9b0; 1 drivers +v0x2b86c80_0 .net "AnorB", 0 0, L_0x2c0c7b0; 1 drivers +v0x2b86d30_0 .net "AorB", 0 0, L_0x2c0c8a0; 1 drivers +v0x2b86e10_0 .net "AxorB", 0 0, L_0x2c0cc20; 1 drivers +v0x2b86ec0_0 .net "B", 0 0, L_0x2c0d900; 1 drivers +v0x2b86f80_0 .alias "Command", 2 0, v0x2bc67a0_0; +v0x2b3c5b0_0 .net "OrNorXorOut", 0 0, L_0x2c0d590; 1 drivers +v0x2b3c630_0 .net "XorNor", 0 0, L_0x2c0d0b0; 1 drivers +v0x2b3c700_0 .net "nXor", 0 0, L_0x2c0cb10; 1 drivers +L_0x2c0d1f0 .part v0x2bc78e0_0, 2, 1; +L_0x2c0d720 .part v0x2bc78e0_0, 0, 1; +S_0x2b865d0 .scope module, "mux0" "TwoInMux" 3 83, 3 8, S_0x2b85f90; + .timescale -9 -12; +L_0x2c0cd80/d .functor NOT 1, L_0x2c0d1f0, C4<0>, C4<0>, C4<0>; +L_0x2c0cd80 .delay (10000,10000,10000) L_0x2c0cd80/d; +L_0x2c0ce40/d .functor AND 1, L_0x2c0cc20, L_0x2c0cd80, C4<1>, C4<1>; +L_0x2c0ce40 .delay (20000,20000,20000) L_0x2c0ce40/d; +L_0x2c0cf50/d .functor AND 1, L_0x2c0c7b0, L_0x2c0d1f0, C4<1>, C4<1>; +L_0x2c0cf50 .delay (20000,20000,20000) L_0x2c0cf50/d; +L_0x2c0d0b0/d .functor OR 1, L_0x2c0ce40, L_0x2c0cf50, C4<0>, C4<0>; +L_0x2c0d0b0 .delay (20000,20000,20000) L_0x2c0d0b0/d; +v0x2b866c0_0 .net "S", 0 0, L_0x2c0d1f0; 1 drivers +v0x2b86780_0 .alias "in0", 0 0, v0x2b86e10_0; +v0x2b86820_0 .alias "in1", 0 0, v0x2b86c80_0; +v0x2b868c0_0 .net "nS", 0 0, L_0x2c0cd80; 1 drivers +v0x2b86940_0 .net "out0", 0 0, L_0x2c0ce40; 1 drivers +v0x2b869e0_0 .net "out1", 0 0, L_0x2c0cf50; 1 drivers +v0x2b86ac0_0 .alias "outfinal", 0 0, v0x2b3c630_0; +S_0x2b86080 .scope module, "mux1" "TwoInMux" 3 84, 3 8, S_0x2b85f90; + .timescale -9 -12; +L_0x2c0d290/d .functor NOT 1, L_0x2c0d720, C4<0>, C4<0>, C4<0>; +L_0x2c0d290 .delay (10000,10000,10000) L_0x2c0d290/d; +L_0x2c0d330/d .functor AND 1, L_0x2c0d0b0, L_0x2c0d290, C4<1>, C4<1>; +L_0x2c0d330 .delay (20000,20000,20000) L_0x2c0d330/d; +L_0x2c0d460/d .functor AND 1, L_0x2c0c8a0, L_0x2c0d720, C4<1>, C4<1>; +L_0x2c0d460 .delay (20000,20000,20000) L_0x2c0d460/d; +L_0x2c0d590/d .functor OR 1, L_0x2c0d330, L_0x2c0d460, C4<0>, C4<0>; +L_0x2c0d590 .delay (20000,20000,20000) L_0x2c0d590/d; +v0x2b86170_0 .net "S", 0 0, L_0x2c0d720; 1 drivers +v0x2b861f0_0 .alias "in0", 0 0, v0x2b3c630_0; +v0x2b86290_0 .alias "in1", 0 0, v0x2b86d30_0; +v0x2b86330_0 .net "nS", 0 0, L_0x2c0d290; 1 drivers +v0x2b863b0_0 .net "out0", 0 0, L_0x2c0d330; 1 drivers +v0x2b86450_0 .net "out1", 0 0, L_0x2c0d460; 1 drivers +v0x2b86530_0 .alias "outfinal", 0 0, v0x2b3c5b0_0; +S_0x2b84a90 .scope generate, "orbits[4]" "orbits[4]" 3 196, 3 196, S_0x2b62fd0; + .timescale -9 -12; +P_0x2b847a8 .param/l "i" 3 196, +C4<0100>; +S_0x2b84bc0 .scope module, "attempt" "OrNorXor" 3 198, 3 64, S_0x2b84a90; + .timescale -9 -12; +L_0x2c0d9a0/d .functor NOR 1, L_0x2c0eb70, L_0x2c0ec10, C4<0>, C4<0>; +L_0x2c0d9a0 .delay (10000,10000,10000) L_0x2c0d9a0/d; +L_0x2c0daa0/d .functor NOT 1, L_0x2c0d9a0, C4<0>, C4<0>, C4<0>; +L_0x2c0daa0 .delay (10000,10000,10000) L_0x2c0daa0/d; +L_0x2c0db90/d .functor NAND 1, L_0x2c0eb70, L_0x2c0ec10, C4<1>, C4<1>; +L_0x2c0db90 .delay (10000,10000,10000) L_0x2c0db90/d; +L_0x2c0dcf0/d .functor NAND 1, L_0x2c0db90, L_0x2c0daa0, C4<1>, C4<1>; +L_0x2c0dcf0 .delay (10000,10000,10000) L_0x2c0dcf0/d; +L_0x2c0de00/d .functor NOT 1, L_0x2c0dcf0, C4<0>, C4<0>, C4<0>; +L_0x2c0de00 .delay (10000,10000,10000) L_0x2c0de00/d; +v0x2b85770_0 .net "A", 0 0, L_0x2c0eb70; 1 drivers +v0x2b85810_0 .net "AnandB", 0 0, L_0x2c0db90; 1 drivers +v0x2b858b0_0 .net "AnorB", 0 0, L_0x2c0d9a0; 1 drivers +v0x2b85960_0 .net "AorB", 0 0, L_0x2c0daa0; 1 drivers +v0x2b85a40_0 .net "AxorB", 0 0, L_0x2c0de00; 1 drivers +v0x2b85af0_0 .net "B", 0 0, L_0x2c0ec10; 1 drivers +v0x2b85bb0_0 .alias "Command", 2 0, v0x2bc67a0_0; +v0x2b85c30_0 .net "OrNorXorOut", 0 0, L_0x2c0e800; 1 drivers +v0x2b85cb0_0 .net "XorNor", 0 0, L_0x2c0e280; 1 drivers +v0x2b85d80_0 .net "nXor", 0 0, L_0x2c0dcf0; 1 drivers +L_0x2c0e400 .part v0x2bc78e0_0, 2, 1; +L_0x2c0e9d0 .part v0x2bc78e0_0, 0, 1; +S_0x2b85200 .scope module, "mux0" "TwoInMux" 3 83, 3 8, S_0x2b84bc0; + .timescale -9 -12; +L_0x2c0df60/d .functor NOT 1, L_0x2c0e400, C4<0>, C4<0>, C4<0>; +L_0x2c0df60 .delay (10000,10000,10000) L_0x2c0df60/d; +L_0x2c0e020/d .functor AND 1, L_0x2c0de00, L_0x2c0df60, C4<1>, C4<1>; +L_0x2c0e020 .delay (20000,20000,20000) L_0x2c0e020/d; +L_0x2c0e130/d .functor AND 1, L_0x2c0d9a0, L_0x2c0e400, C4<1>, C4<1>; +L_0x2c0e130 .delay (20000,20000,20000) L_0x2c0e130/d; +L_0x2c0e280/d .functor OR 1, L_0x2c0e020, L_0x2c0e130, C4<0>, C4<0>; +L_0x2c0e280 .delay (20000,20000,20000) L_0x2c0e280/d; +v0x2b852f0_0 .net "S", 0 0, L_0x2c0e400; 1 drivers +v0x2b853b0_0 .alias "in0", 0 0, v0x2b85a40_0; +v0x2b85450_0 .alias "in1", 0 0, v0x2b858b0_0; +v0x2b854f0_0 .net "nS", 0 0, L_0x2c0df60; 1 drivers +v0x2b85570_0 .net "out0", 0 0, L_0x2c0e020; 1 drivers +v0x2b85610_0 .net "out1", 0 0, L_0x2c0e130; 1 drivers +v0x2b856f0_0 .alias "outfinal", 0 0, v0x2b85cb0_0; +S_0x2b84cb0 .scope module, "mux1" "TwoInMux" 3 84, 3 8, S_0x2b84bc0; + .timescale -9 -12; +L_0x2c0e4a0/d .functor NOT 1, L_0x2c0e9d0, C4<0>, C4<0>, C4<0>; +L_0x2c0e4a0 .delay (10000,10000,10000) L_0x2c0e4a0/d; +L_0x2c0e560/d .functor AND 1, L_0x2c0e280, L_0x2c0e4a0, C4<1>, C4<1>; +L_0x2c0e560 .delay (20000,20000,20000) L_0x2c0e560/d; +L_0x2c0e6b0/d .functor AND 1, L_0x2c0daa0, L_0x2c0e9d0, C4<1>, C4<1>; +L_0x2c0e6b0 .delay (20000,20000,20000) L_0x2c0e6b0/d; +L_0x2c0e800/d .functor OR 1, L_0x2c0e560, L_0x2c0e6b0, C4<0>, C4<0>; +L_0x2c0e800 .delay (20000,20000,20000) L_0x2c0e800/d; +v0x2b84da0_0 .net "S", 0 0, L_0x2c0e9d0; 1 drivers +v0x2b84e20_0 .alias "in0", 0 0, v0x2b85cb0_0; +v0x2b84ec0_0 .alias "in1", 0 0, v0x2b85960_0; +v0x2b84f60_0 .net "nS", 0 0, L_0x2c0e4a0; 1 drivers +v0x2b84fe0_0 .net "out0", 0 0, L_0x2c0e560; 1 drivers +v0x2b85080_0 .net "out1", 0 0, L_0x2c0e6b0; 1 drivers +v0x2b85160_0 .alias "outfinal", 0 0, v0x2b85c30_0; +S_0x2b836c0 .scope generate, "orbits[5]" "orbits[5]" 3 196, 3 196, S_0x2b62fd0; + .timescale -9 -12; +P_0x2b833d8 .param/l "i" 3 196, +C4<0101>; +S_0x2b837f0 .scope module, "attempt" "OrNorXor" 3 198, 3 64, S_0x2b836c0; + .timescale -9 -12; +L_0x2c0eb10/d .functor NOR 1, L_0x2c0ff20, L_0x2c0ffc0, C4<0>, C4<0>; +L_0x2c0eb10 .delay (10000,10000,10000) L_0x2c0eb10/d; +L_0x2c0ed60/d .functor NOT 1, L_0x2c0eb10, C4<0>, C4<0>, C4<0>; +L_0x2c0ed60 .delay (10000,10000,10000) L_0x2c0ed60/d; +L_0x2c0ee90/d .functor NAND 1, L_0x2c0ff20, L_0x2c0ffc0, C4<1>, C4<1>; +L_0x2c0ee90 .delay (10000,10000,10000) L_0x2c0ee90/d; +L_0x2c0eff0/d .functor NAND 1, L_0x2c0ee90, L_0x2c0ed60, C4<1>, C4<1>; +L_0x2c0eff0 .delay (10000,10000,10000) L_0x2c0eff0/d; +L_0x2c0f100/d .functor NOT 1, L_0x2c0eff0, C4<0>, C4<0>, C4<0>; +L_0x2c0f100 .delay (10000,10000,10000) L_0x2c0f100/d; +v0x2b843a0_0 .net "A", 0 0, L_0x2c0ff20; 1 drivers +v0x2b84440_0 .net "AnandB", 0 0, L_0x2c0ee90; 1 drivers +v0x2b844e0_0 .net "AnorB", 0 0, L_0x2c0eb10; 1 drivers +v0x2b84590_0 .net "AorB", 0 0, L_0x2c0ed60; 1 drivers +v0x2b84670_0 .net "AxorB", 0 0, L_0x2c0f100; 1 drivers +v0x2b84720_0 .net "B", 0 0, L_0x2c0ffc0; 1 drivers +v0x2b847e0_0 .alias "Command", 2 0, v0x2bc67a0_0; +v0x2b84860_0 .net "OrNorXorOut", 0 0, L_0x2c0fb00; 1 drivers +v0x2b848e0_0 .net "XorNor", 0 0, L_0x2c0f580; 1 drivers +v0x2b849b0_0 .net "nXor", 0 0, L_0x2c0eff0; 1 drivers +L_0x2c0f700 .part v0x2bc78e0_0, 2, 1; +L_0x2c0fcd0 .part v0x2bc78e0_0, 0, 1; +S_0x2b83e30 .scope module, "mux0" "TwoInMux" 3 83, 3 8, S_0x2b837f0; + .timescale -9 -12; +L_0x2c0f260/d .functor NOT 1, L_0x2c0f700, C4<0>, C4<0>, C4<0>; +L_0x2c0f260 .delay (10000,10000,10000) L_0x2c0f260/d; +L_0x2c0f320/d .functor AND 1, L_0x2c0f100, L_0x2c0f260, C4<1>, C4<1>; +L_0x2c0f320 .delay (20000,20000,20000) L_0x2c0f320/d; +L_0x2c0f430/d .functor AND 1, L_0x2c0eb10, L_0x2c0f700, C4<1>, C4<1>; +L_0x2c0f430 .delay (20000,20000,20000) L_0x2c0f430/d; +L_0x2c0f580/d .functor OR 1, L_0x2c0f320, L_0x2c0f430, C4<0>, C4<0>; +L_0x2c0f580 .delay (20000,20000,20000) L_0x2c0f580/d; +v0x2b83f20_0 .net "S", 0 0, L_0x2c0f700; 1 drivers +v0x2b83fe0_0 .alias "in0", 0 0, v0x2b84670_0; +v0x2b84080_0 .alias "in1", 0 0, v0x2b844e0_0; +v0x2b84120_0 .net "nS", 0 0, L_0x2c0f260; 1 drivers +v0x2b841a0_0 .net "out0", 0 0, L_0x2c0f320; 1 drivers +v0x2b84240_0 .net "out1", 0 0, L_0x2c0f430; 1 drivers +v0x2b84320_0 .alias "outfinal", 0 0, v0x2b848e0_0; +S_0x2b838e0 .scope module, "mux1" "TwoInMux" 3 84, 3 8, S_0x2b837f0; + .timescale -9 -12; +L_0x2c0f7a0/d .functor NOT 1, L_0x2c0fcd0, C4<0>, C4<0>, C4<0>; +L_0x2c0f7a0 .delay (10000,10000,10000) L_0x2c0f7a0/d; +L_0x2c0f860/d .functor AND 1, L_0x2c0f580, L_0x2c0f7a0, C4<1>, C4<1>; +L_0x2c0f860 .delay (20000,20000,20000) L_0x2c0f860/d; +L_0x2c0f9b0/d .functor AND 1, L_0x2c0ed60, L_0x2c0fcd0, C4<1>, C4<1>; +L_0x2c0f9b0 .delay (20000,20000,20000) L_0x2c0f9b0/d; +L_0x2c0fb00/d .functor OR 1, L_0x2c0f860, L_0x2c0f9b0, C4<0>, C4<0>; +L_0x2c0fb00 .delay (20000,20000,20000) L_0x2c0fb00/d; +v0x2b839d0_0 .net "S", 0 0, L_0x2c0fcd0; 1 drivers +v0x2b83a50_0 .alias "in0", 0 0, v0x2b848e0_0; +v0x2b83af0_0 .alias "in1", 0 0, v0x2b84590_0; +v0x2b83b90_0 .net "nS", 0 0, L_0x2c0f7a0; 1 drivers +v0x2b83c10_0 .net "out0", 0 0, L_0x2c0f860; 1 drivers +v0x2b83cb0_0 .net "out1", 0 0, L_0x2c0f9b0; 1 drivers +v0x2b83d90_0 .alias "outfinal", 0 0, v0x2b84860_0; +S_0x2b822f0 .scope generate, "orbits[6]" "orbits[6]" 3 196, 3 196, S_0x2b62fd0; + .timescale -9 -12; +P_0x2b82008 .param/l "i" 3 196, +C4<0110>; +S_0x2b82420 .scope module, "attempt" "OrNorXor" 3 198, 3 64, S_0x2b822f0; + .timescale -9 -12; +L_0x2c10060/d .functor NOR 1, L_0x2c11200, L_0x2c112a0, C4<0>, C4<0>; +L_0x2c10060 .delay (10000,10000,10000) L_0x2c10060/d; +L_0x2c10150/d .functor NOT 1, L_0x2c10060, C4<0>, C4<0>, C4<0>; +L_0x2c10150 .delay (10000,10000,10000) L_0x2c10150/d; +L_0x2c10280/d .functor NAND 1, L_0x2c11200, L_0x2c112a0, C4<1>, C4<1>; +L_0x2c10280 .delay (10000,10000,10000) L_0x2c10280/d; +L_0x2c103e0/d .functor NAND 1, L_0x2c10280, L_0x2c10150, C4<1>, C4<1>; +L_0x2c103e0 .delay (10000,10000,10000) L_0x2c103e0/d; +L_0x2c104f0/d .functor NOT 1, L_0x2c103e0, C4<0>, C4<0>, C4<0>; +L_0x2c104f0 .delay (10000,10000,10000) L_0x2c104f0/d; +v0x2b82fd0_0 .net "A", 0 0, L_0x2c11200; 1 drivers +v0x2b83070_0 .net "AnandB", 0 0, L_0x2c10280; 1 drivers +v0x2b83110_0 .net "AnorB", 0 0, L_0x2c10060; 1 drivers +v0x2b831c0_0 .net "AorB", 0 0, L_0x2c10150; 1 drivers +v0x2b832a0_0 .net "AxorB", 0 0, L_0x2c104f0; 1 drivers +v0x2b83350_0 .net "B", 0 0, L_0x2c112a0; 1 drivers +v0x2b83410_0 .alias "Command", 2 0, v0x2bc67a0_0; +v0x2b83490_0 .net "OrNorXorOut", 0 0, L_0x2c10ef0; 1 drivers +v0x2b83510_0 .net "XorNor", 0 0, L_0x2c10970; 1 drivers +v0x2b835e0_0 .net "nXor", 0 0, L_0x2c103e0; 1 drivers +L_0x2c10af0 .part v0x2bc78e0_0, 2, 1; +L_0x2c110c0 .part v0x2bc78e0_0, 0, 1; +S_0x2b82a60 .scope module, "mux0" "TwoInMux" 3 83, 3 8, S_0x2b82420; + .timescale -9 -12; +L_0x2c10650/d .functor NOT 1, L_0x2c10af0, C4<0>, C4<0>, C4<0>; +L_0x2c10650 .delay (10000,10000,10000) L_0x2c10650/d; +L_0x2c10710/d .functor AND 1, L_0x2c104f0, L_0x2c10650, C4<1>, C4<1>; +L_0x2c10710 .delay (20000,20000,20000) L_0x2c10710/d; +L_0x2c10820/d .functor AND 1, L_0x2c10060, L_0x2c10af0, C4<1>, C4<1>; +L_0x2c10820 .delay (20000,20000,20000) L_0x2c10820/d; +L_0x2c10970/d .functor OR 1, L_0x2c10710, L_0x2c10820, C4<0>, C4<0>; +L_0x2c10970 .delay (20000,20000,20000) L_0x2c10970/d; +v0x2b82b50_0 .net "S", 0 0, L_0x2c10af0; 1 drivers +v0x2b82c10_0 .alias "in0", 0 0, v0x2b832a0_0; +v0x2b82cb0_0 .alias "in1", 0 0, v0x2b83110_0; +v0x2b82d50_0 .net "nS", 0 0, L_0x2c10650; 1 drivers +v0x2b82dd0_0 .net "out0", 0 0, L_0x2c10710; 1 drivers +v0x2b82e70_0 .net "out1", 0 0, L_0x2c10820; 1 drivers +v0x2b82f50_0 .alias "outfinal", 0 0, v0x2b83510_0; +S_0x2b82510 .scope module, "mux1" "TwoInMux" 3 84, 3 8, S_0x2b82420; + .timescale -9 -12; +L_0x2c10b90/d .functor NOT 1, L_0x2c110c0, C4<0>, C4<0>, C4<0>; +L_0x2c10b90 .delay (10000,10000,10000) L_0x2c10b90/d; +L_0x2c10c50/d .functor AND 1, L_0x2c10970, L_0x2c10b90, C4<1>, C4<1>; +L_0x2c10c50 .delay (20000,20000,20000) L_0x2c10c50/d; +L_0x2c10da0/d .functor AND 1, L_0x2c10150, L_0x2c110c0, C4<1>, C4<1>; +L_0x2c10da0 .delay (20000,20000,20000) L_0x2c10da0/d; +L_0x2c10ef0/d .functor OR 1, L_0x2c10c50, L_0x2c10da0, C4<0>, C4<0>; +L_0x2c10ef0 .delay (20000,20000,20000) L_0x2c10ef0/d; +v0x2b82600_0 .net "S", 0 0, L_0x2c110c0; 1 drivers +v0x2b82680_0 .alias "in0", 0 0, v0x2b83510_0; +v0x2b82720_0 .alias "in1", 0 0, v0x2b831c0_0; +v0x2b827c0_0 .net "nS", 0 0, L_0x2c10b90; 1 drivers +v0x2b82840_0 .net "out0", 0 0, L_0x2c10c50; 1 drivers +v0x2b828e0_0 .net "out1", 0 0, L_0x2c10da0; 1 drivers +v0x2b829c0_0 .alias "outfinal", 0 0, v0x2b83490_0; +S_0x2b80f20 .scope generate, "orbits[7]" "orbits[7]" 3 196, 3 196, S_0x2b62fd0; + .timescale -9 -12; +P_0x2b80c38 .param/l "i" 3 196, +C4<0111>; +S_0x2b81050 .scope module, "attempt" "OrNorXor" 3 198, 3 64, S_0x2b80f20; + .timescale -9 -12; +L_0x2c0b3f0/d .functor NOR 1, L_0x2c12500, L_0x2c11340, C4<0>, C4<0>; +L_0x2c0b3f0 .delay (10000,10000,10000) L_0x2c0b3f0/d; +L_0x2c11470/d .functor NOT 1, L_0x2c0b3f0, C4<0>, C4<0>, C4<0>; +L_0x2c11470 .delay (10000,10000,10000) L_0x2c11470/d; +L_0x2c11580/d .functor NAND 1, L_0x2c12500, L_0x2c11340, C4<1>, C4<1>; +L_0x2c11580 .delay (10000,10000,10000) L_0x2c11580/d; +L_0x2c116e0/d .functor NAND 1, L_0x2c11580, L_0x2c11470, C4<1>, C4<1>; +L_0x2c116e0 .delay (10000,10000,10000) L_0x2c116e0/d; +L_0x2c117f0/d .functor NOT 1, L_0x2c116e0, C4<0>, C4<0>, C4<0>; +L_0x2c117f0 .delay (10000,10000,10000) L_0x2c117f0/d; +v0x2b81c00_0 .net "A", 0 0, L_0x2c12500; 1 drivers +v0x2b81ca0_0 .net "AnandB", 0 0, L_0x2c11580; 1 drivers +v0x2b81d40_0 .net "AnorB", 0 0, L_0x2c0b3f0; 1 drivers +v0x2b81df0_0 .net "AorB", 0 0, L_0x2c11470; 1 drivers +v0x2b81ed0_0 .net "AxorB", 0 0, L_0x2c117f0; 1 drivers +v0x2b81f80_0 .net "B", 0 0, L_0x2c11340; 1 drivers +v0x2b82040_0 .alias "Command", 2 0, v0x2bc67a0_0; +v0x2b820c0_0 .net "OrNorXorOut", 0 0, L_0x2c121f0; 1 drivers +v0x2b82140_0 .net "XorNor", 0 0, L_0x2c11c70; 1 drivers +v0x2b82210_0 .net "nXor", 0 0, L_0x2c116e0; 1 drivers +L_0x2c11df0 .part v0x2bc78e0_0, 2, 1; +L_0x2c123c0 .part v0x2bc78e0_0, 0, 1; +S_0x2b81690 .scope module, "mux0" "TwoInMux" 3 83, 3 8, S_0x2b81050; + .timescale -9 -12; +L_0x2c11950/d .functor NOT 1, L_0x2c11df0, C4<0>, C4<0>, C4<0>; +L_0x2c11950 .delay (10000,10000,10000) L_0x2c11950/d; +L_0x2c11a10/d .functor AND 1, L_0x2c117f0, L_0x2c11950, C4<1>, C4<1>; +L_0x2c11a10 .delay (20000,20000,20000) L_0x2c11a10/d; +L_0x2c11b20/d .functor AND 1, L_0x2c0b3f0, L_0x2c11df0, C4<1>, C4<1>; +L_0x2c11b20 .delay (20000,20000,20000) L_0x2c11b20/d; +L_0x2c11c70/d .functor OR 1, L_0x2c11a10, L_0x2c11b20, C4<0>, C4<0>; +L_0x2c11c70 .delay (20000,20000,20000) L_0x2c11c70/d; +v0x2b81780_0 .net "S", 0 0, L_0x2c11df0; 1 drivers +v0x2b81840_0 .alias "in0", 0 0, v0x2b81ed0_0; +v0x2b818e0_0 .alias "in1", 0 0, v0x2b81d40_0; +v0x2b81980_0 .net "nS", 0 0, L_0x2c11950; 1 drivers +v0x2b81a00_0 .net "out0", 0 0, L_0x2c11a10; 1 drivers +v0x2b81aa0_0 .net "out1", 0 0, L_0x2c11b20; 1 drivers +v0x2b81b80_0 .alias "outfinal", 0 0, v0x2b82140_0; +S_0x2b81140 .scope module, "mux1" "TwoInMux" 3 84, 3 8, S_0x2b81050; + .timescale -9 -12; +L_0x2c11e90/d .functor NOT 1, L_0x2c123c0, C4<0>, C4<0>, C4<0>; +L_0x2c11e90 .delay (10000,10000,10000) L_0x2c11e90/d; +L_0x2c11f50/d .functor AND 1, L_0x2c11c70, L_0x2c11e90, C4<1>, C4<1>; +L_0x2c11f50 .delay (20000,20000,20000) L_0x2c11f50/d; +L_0x2c120a0/d .functor AND 1, L_0x2c11470, L_0x2c123c0, C4<1>, C4<1>; +L_0x2c120a0 .delay (20000,20000,20000) L_0x2c120a0/d; +L_0x2c121f0/d .functor OR 1, L_0x2c11f50, L_0x2c120a0, C4<0>, C4<0>; +L_0x2c121f0 .delay (20000,20000,20000) L_0x2c121f0/d; +v0x2b81230_0 .net "S", 0 0, L_0x2c123c0; 1 drivers +v0x2b812b0_0 .alias "in0", 0 0, v0x2b82140_0; +v0x2b81350_0 .alias "in1", 0 0, v0x2b81df0_0; +v0x2b813f0_0 .net "nS", 0 0, L_0x2c11e90; 1 drivers +v0x2b81470_0 .net "out0", 0 0, L_0x2c11f50; 1 drivers +v0x2b81510_0 .net "out1", 0 0, L_0x2c120a0; 1 drivers +v0x2b815f0_0 .alias "outfinal", 0 0, v0x2b820c0_0; +S_0x2b7fb50 .scope generate, "orbits[8]" "orbits[8]" 3 196, 3 196, S_0x2b62fd0; + .timescale -9 -12; +P_0x2b7f868 .param/l "i" 3 196, +C4<01000>; +S_0x2b7fc80 .scope module, "attempt" "OrNorXor" 3 198, 3 64, S_0x2b7fb50; + .timescale -9 -12; +L_0x2c12650/d .functor NOR 1, L_0x2c125a0, L_0x2c138b0, C4<0>, C4<0>; +L_0x2c12650 .delay (10000,10000,10000) L_0x2c12650/d; +L_0x2c12740/d .functor NOT 1, L_0x2c12650, C4<0>, C4<0>, C4<0>; +L_0x2c12740 .delay (10000,10000,10000) L_0x2c12740/d; +L_0x2c12870/d .functor NAND 1, L_0x2c125a0, L_0x2c138b0, C4<1>, C4<1>; +L_0x2c12870 .delay (10000,10000,10000) L_0x2c12870/d; +L_0x2c129d0/d .functor NAND 1, L_0x2c12870, L_0x2c12740, C4<1>, C4<1>; +L_0x2c129d0 .delay (10000,10000,10000) L_0x2c129d0/d; +L_0x2c12ae0/d .functor NOT 1, L_0x2c129d0, C4<0>, C4<0>, C4<0>; +L_0x2c12ae0 .delay (10000,10000,10000) L_0x2c12ae0/d; +v0x2b80830_0 .net "A", 0 0, L_0x2c125a0; 1 drivers +v0x2b808d0_0 .net "AnandB", 0 0, L_0x2c12870; 1 drivers +v0x2b80970_0 .net "AnorB", 0 0, L_0x2c12650; 1 drivers +v0x2b80a20_0 .net "AorB", 0 0, L_0x2c12740; 1 drivers +v0x2b80b00_0 .net "AxorB", 0 0, L_0x2c12ae0; 1 drivers +v0x2b80bb0_0 .net "B", 0 0, L_0x2c138b0; 1 drivers +v0x2b80c70_0 .alias "Command", 2 0, v0x2bc67a0_0; +v0x2b80cf0_0 .net "OrNorXorOut", 0 0, L_0x2c134e0; 1 drivers +v0x2b80d70_0 .net "XorNor", 0 0, L_0x2c12f60; 1 drivers +v0x2b80e40_0 .net "nXor", 0 0, L_0x2c129d0; 1 drivers +L_0x2c130e0 .part v0x2bc78e0_0, 2, 1; +L_0x2c136b0 .part v0x2bc78e0_0, 0, 1; +S_0x2b802c0 .scope module, "mux0" "TwoInMux" 3 83, 3 8, S_0x2b7fc80; + .timescale -9 -12; +L_0x2c12c40/d .functor NOT 1, L_0x2c130e0, C4<0>, C4<0>, C4<0>; +L_0x2c12c40 .delay (10000,10000,10000) L_0x2c12c40/d; +L_0x2c12d00/d .functor AND 1, L_0x2c12ae0, L_0x2c12c40, C4<1>, C4<1>; +L_0x2c12d00 .delay (20000,20000,20000) L_0x2c12d00/d; +L_0x2c12e10/d .functor AND 1, L_0x2c12650, L_0x2c130e0, C4<1>, C4<1>; +L_0x2c12e10 .delay (20000,20000,20000) L_0x2c12e10/d; +L_0x2c12f60/d .functor OR 1, L_0x2c12d00, L_0x2c12e10, C4<0>, C4<0>; +L_0x2c12f60 .delay (20000,20000,20000) L_0x2c12f60/d; +v0x2b803b0_0 .net "S", 0 0, L_0x2c130e0; 1 drivers +v0x2b80470_0 .alias "in0", 0 0, v0x2b80b00_0; +v0x2b80510_0 .alias "in1", 0 0, v0x2b80970_0; +v0x2b805b0_0 .net "nS", 0 0, L_0x2c12c40; 1 drivers +v0x2b80630_0 .net "out0", 0 0, L_0x2c12d00; 1 drivers +v0x2b806d0_0 .net "out1", 0 0, L_0x2c12e10; 1 drivers +v0x2b807b0_0 .alias "outfinal", 0 0, v0x2b80d70_0; +S_0x2b7fd70 .scope module, "mux1" "TwoInMux" 3 84, 3 8, S_0x2b7fc80; + .timescale -9 -12; +L_0x2c13180/d .functor NOT 1, L_0x2c136b0, C4<0>, C4<0>, C4<0>; +L_0x2c13180 .delay (10000,10000,10000) L_0x2c13180/d; +L_0x2c13240/d .functor AND 1, L_0x2c12f60, L_0x2c13180, C4<1>, C4<1>; +L_0x2c13240 .delay (20000,20000,20000) L_0x2c13240/d; +L_0x2c13390/d .functor AND 1, L_0x2c12740, L_0x2c136b0, C4<1>, C4<1>; +L_0x2c13390 .delay (20000,20000,20000) L_0x2c13390/d; +L_0x2c134e0/d .functor OR 1, L_0x2c13240, L_0x2c13390, C4<0>, C4<0>; +L_0x2c134e0 .delay (20000,20000,20000) L_0x2c134e0/d; +v0x2b7fe60_0 .net "S", 0 0, L_0x2c136b0; 1 drivers +v0x2b7fee0_0 .alias "in0", 0 0, v0x2b80d70_0; +v0x2b7ff80_0 .alias "in1", 0 0, v0x2b80a20_0; +v0x2b80020_0 .net "nS", 0 0, L_0x2c13180; 1 drivers +v0x2b800a0_0 .net "out0", 0 0, L_0x2c13240; 1 drivers +v0x2b80140_0 .net "out1", 0 0, L_0x2c13390; 1 drivers +v0x2b80220_0 .alias "outfinal", 0 0, v0x2b80cf0_0; +S_0x2b7e780 .scope generate, "orbits[9]" "orbits[9]" 3 196, 3 196, S_0x2b62fd0; + .timescale -9 -12; +P_0x2b7e498 .param/l "i" 3 196, +C4<01001>; +S_0x2b7e8b0 .scope module, "attempt" "OrNorXor" 3 198, 3 64, S_0x2b7e780; + .timescale -9 -12; +L_0x2c137f0/d .functor NOR 1, L_0x2c14b00, L_0x2c13950, C4<0>, C4<0>; +L_0x2c137f0 .delay (10000,10000,10000) L_0x2c137f0/d; +L_0x2c13a70/d .functor NOT 1, L_0x2c137f0, C4<0>, C4<0>, C4<0>; +L_0x2c13a70 .delay (10000,10000,10000) L_0x2c13a70/d; +L_0x2c13b80/d .functor NAND 1, L_0x2c14b00, L_0x2c13950, C4<1>, C4<1>; +L_0x2c13b80 .delay (10000,10000,10000) L_0x2c13b80/d; +L_0x2c13ce0/d .functor NAND 1, L_0x2c13b80, L_0x2c13a70, C4<1>, C4<1>; +L_0x2c13ce0 .delay (10000,10000,10000) L_0x2c13ce0/d; +L_0x2c13df0/d .functor NOT 1, L_0x2c13ce0, C4<0>, C4<0>, C4<0>; +L_0x2c13df0 .delay (10000,10000,10000) L_0x2c13df0/d; +v0x2b7f460_0 .net "A", 0 0, L_0x2c14b00; 1 drivers +v0x2b7f500_0 .net "AnandB", 0 0, L_0x2c13b80; 1 drivers +v0x2b7f5a0_0 .net "AnorB", 0 0, L_0x2c137f0; 1 drivers +v0x2b7f650_0 .net "AorB", 0 0, L_0x2c13a70; 1 drivers +v0x2b7f730_0 .net "AxorB", 0 0, L_0x2c13df0; 1 drivers +v0x2b7f7e0_0 .net "B", 0 0, L_0x2c13950; 1 drivers +v0x2b7f8a0_0 .alias "Command", 2 0, v0x2bc67a0_0; +v0x2b7f920_0 .net "OrNorXorOut", 0 0, L_0x2c147f0; 1 drivers +v0x2b7f9a0_0 .net "XorNor", 0 0, L_0x2c14270; 1 drivers +v0x2b7fa70_0 .net "nXor", 0 0, L_0x2c13ce0; 1 drivers +L_0x2c143f0 .part v0x2bc78e0_0, 2, 1; +L_0x2c149c0 .part v0x2bc78e0_0, 0, 1; +S_0x2b7eef0 .scope module, "mux0" "TwoInMux" 3 83, 3 8, S_0x2b7e8b0; + .timescale -9 -12; +L_0x2c13f50/d .functor NOT 1, L_0x2c143f0, C4<0>, C4<0>, C4<0>; +L_0x2c13f50 .delay (10000,10000,10000) L_0x2c13f50/d; +L_0x2c14010/d .functor AND 1, L_0x2c13df0, L_0x2c13f50, C4<1>, C4<1>; +L_0x2c14010 .delay (20000,20000,20000) L_0x2c14010/d; +L_0x2c14120/d .functor AND 1, L_0x2c137f0, L_0x2c143f0, C4<1>, C4<1>; +L_0x2c14120 .delay (20000,20000,20000) L_0x2c14120/d; +L_0x2c14270/d .functor OR 1, L_0x2c14010, L_0x2c14120, C4<0>, C4<0>; +L_0x2c14270 .delay (20000,20000,20000) L_0x2c14270/d; +v0x2b7efe0_0 .net "S", 0 0, L_0x2c143f0; 1 drivers +v0x2b7f0a0_0 .alias "in0", 0 0, v0x2b7f730_0; +v0x2b7f140_0 .alias "in1", 0 0, v0x2b7f5a0_0; +v0x2b7f1e0_0 .net "nS", 0 0, L_0x2c13f50; 1 drivers +v0x2b7f260_0 .net "out0", 0 0, L_0x2c14010; 1 drivers +v0x2b7f300_0 .net "out1", 0 0, L_0x2c14120; 1 drivers +v0x2b7f3e0_0 .alias "outfinal", 0 0, v0x2b7f9a0_0; +S_0x2b7e9a0 .scope module, "mux1" "TwoInMux" 3 84, 3 8, S_0x2b7e8b0; + .timescale -9 -12; +L_0x2c14490/d .functor NOT 1, L_0x2c149c0, C4<0>, C4<0>, C4<0>; +L_0x2c14490 .delay (10000,10000,10000) L_0x2c14490/d; +L_0x2c14550/d .functor AND 1, L_0x2c14270, L_0x2c14490, C4<1>, C4<1>; +L_0x2c14550 .delay (20000,20000,20000) L_0x2c14550/d; +L_0x2c146a0/d .functor AND 1, L_0x2c13a70, L_0x2c149c0, C4<1>, C4<1>; +L_0x2c146a0 .delay (20000,20000,20000) L_0x2c146a0/d; +L_0x2c147f0/d .functor OR 1, L_0x2c14550, L_0x2c146a0, C4<0>, C4<0>; +L_0x2c147f0 .delay (20000,20000,20000) L_0x2c147f0/d; +v0x2b7ea90_0 .net "S", 0 0, L_0x2c149c0; 1 drivers +v0x2b7eb10_0 .alias "in0", 0 0, v0x2b7f9a0_0; +v0x2b7ebb0_0 .alias "in1", 0 0, v0x2b7f650_0; +v0x2b7ec50_0 .net "nS", 0 0, L_0x2c14490; 1 drivers +v0x2b7ecd0_0 .net "out0", 0 0, L_0x2c14550; 1 drivers +v0x2b7ed70_0 .net "out1", 0 0, L_0x2c146a0; 1 drivers +v0x2b7ee50_0 .alias "outfinal", 0 0, v0x2b7f920_0; +S_0x2b7d3b0 .scope generate, "orbits[10]" "orbits[10]" 3 196, 3 196, S_0x2b62fd0; + .timescale -9 -12; +P_0x2b7d0c8 .param/l "i" 3 196, +C4<01010>; +S_0x2b7d4e0 .scope module, "attempt" "OrNorXor" 3 198, 3 64, S_0x2b7d3b0; + .timescale -9 -12; +L_0x2c14c80/d .functor NOR 1, L_0x2c14ba0, L_0x2c15ef0, C4<0>, C4<0>; +L_0x2c14c80 .delay (10000,10000,10000) L_0x2c14c80/d; +L_0x2c14d70/d .functor NOT 1, L_0x2c14c80, C4<0>, C4<0>, C4<0>; +L_0x2c14d70 .delay (10000,10000,10000) L_0x2c14d70/d; +L_0x2c14e80/d .functor NAND 1, L_0x2c14ba0, L_0x2c15ef0, C4<1>, C4<1>; +L_0x2c14e80 .delay (10000,10000,10000) L_0x2c14e80/d; +L_0x2c14fe0/d .functor NAND 1, L_0x2c14e80, L_0x2c14d70, C4<1>, C4<1>; +L_0x2c14fe0 .delay (10000,10000,10000) L_0x2c14fe0/d; +L_0x2c150f0/d .functor NOT 1, L_0x2c14fe0, C4<0>, C4<0>, C4<0>; +L_0x2c150f0 .delay (10000,10000,10000) L_0x2c150f0/d; +v0x2b7e090_0 .net "A", 0 0, L_0x2c14ba0; 1 drivers +v0x2b7e130_0 .net "AnandB", 0 0, L_0x2c14e80; 1 drivers +v0x2b7e1d0_0 .net "AnorB", 0 0, L_0x2c14c80; 1 drivers +v0x2b7e280_0 .net "AorB", 0 0, L_0x2c14d70; 1 drivers +v0x2b7e360_0 .net "AxorB", 0 0, L_0x2c150f0; 1 drivers +v0x2b7e410_0 .net "B", 0 0, L_0x2c15ef0; 1 drivers +v0x2b7e4d0_0 .alias "Command", 2 0, v0x2bc67a0_0; +v0x2b7e550_0 .net "OrNorXorOut", 0 0, L_0x2c15af0; 1 drivers +v0x2b7e5d0_0 .net "XorNor", 0 0, L_0x2c15570; 1 drivers +v0x2b7e6a0_0 .net "nXor", 0 0, L_0x2c14fe0; 1 drivers +L_0x2c156f0 .part v0x2bc78e0_0, 2, 1; +L_0x2c15cc0 .part v0x2bc78e0_0, 0, 1; +S_0x2b7db20 .scope module, "mux0" "TwoInMux" 3 83, 3 8, S_0x2b7d4e0; + .timescale -9 -12; +L_0x2c15250/d .functor NOT 1, L_0x2c156f0, C4<0>, C4<0>, C4<0>; +L_0x2c15250 .delay (10000,10000,10000) L_0x2c15250/d; +L_0x2c15310/d .functor AND 1, L_0x2c150f0, L_0x2c15250, C4<1>, C4<1>; +L_0x2c15310 .delay (20000,20000,20000) L_0x2c15310/d; +L_0x2c15420/d .functor AND 1, L_0x2c14c80, L_0x2c156f0, C4<1>, C4<1>; +L_0x2c15420 .delay (20000,20000,20000) L_0x2c15420/d; +L_0x2c15570/d .functor OR 1, L_0x2c15310, L_0x2c15420, C4<0>, C4<0>; +L_0x2c15570 .delay (20000,20000,20000) L_0x2c15570/d; +v0x2b7dc10_0 .net "S", 0 0, L_0x2c156f0; 1 drivers +v0x2b7dcd0_0 .alias "in0", 0 0, v0x2b7e360_0; +v0x2b7dd70_0 .alias "in1", 0 0, v0x2b7e1d0_0; +v0x2b7de10_0 .net "nS", 0 0, L_0x2c15250; 1 drivers +v0x2b7de90_0 .net "out0", 0 0, L_0x2c15310; 1 drivers +v0x2b7df30_0 .net "out1", 0 0, L_0x2c15420; 1 drivers +v0x2b7e010_0 .alias "outfinal", 0 0, v0x2b7e5d0_0; +S_0x2b7d5d0 .scope module, "mux1" "TwoInMux" 3 84, 3 8, S_0x2b7d4e0; + .timescale -9 -12; +L_0x2c15790/d .functor NOT 1, L_0x2c15cc0, C4<0>, C4<0>, C4<0>; +L_0x2c15790 .delay (10000,10000,10000) L_0x2c15790/d; +L_0x2c15850/d .functor AND 1, L_0x2c15570, L_0x2c15790, C4<1>, C4<1>; +L_0x2c15850 .delay (20000,20000,20000) L_0x2c15850/d; +L_0x2c159a0/d .functor AND 1, L_0x2c14d70, L_0x2c15cc0, C4<1>, C4<1>; +L_0x2c159a0 .delay (20000,20000,20000) L_0x2c159a0/d; +L_0x2c15af0/d .functor OR 1, L_0x2c15850, L_0x2c159a0, C4<0>, C4<0>; +L_0x2c15af0 .delay (20000,20000,20000) L_0x2c15af0/d; +v0x2b7d6c0_0 .net "S", 0 0, L_0x2c15cc0; 1 drivers +v0x2b7d740_0 .alias "in0", 0 0, v0x2b7e5d0_0; +v0x2b7d7e0_0 .alias "in1", 0 0, v0x2b7e280_0; +v0x2b7d880_0 .net "nS", 0 0, L_0x2c15790; 1 drivers +v0x2b7d900_0 .net "out0", 0 0, L_0x2c15850; 1 drivers +v0x2b7d9a0_0 .net "out1", 0 0, L_0x2c159a0; 1 drivers +v0x2b7da80_0 .alias "outfinal", 0 0, v0x2b7e550_0; +S_0x2b7bfe0 .scope generate, "orbits[11]" "orbits[11]" 3 196, 3 196, S_0x2b62fd0; + .timescale -9 -12; +P_0x2b7bcf8 .param/l "i" 3 196, +C4<01011>; +S_0x2b7c110 .scope module, "attempt" "OrNorXor" 3 198, 3 64, S_0x2b7bfe0; + .timescale -9 -12; +L_0x2c15e00/d .functor NOR 1, L_0x2c17100, L_0x2c15f90, C4<0>, C4<0>; +L_0x2c15e00 .delay (10000,10000,10000) L_0x2c15e00/d; +L_0x2c16090/d .functor NOT 1, L_0x2c15e00, C4<0>, C4<0>, C4<0>; +L_0x2c16090 .delay (10000,10000,10000) L_0x2c16090/d; +L_0x2c16180/d .functor NAND 1, L_0x2c17100, L_0x2c15f90, C4<1>, C4<1>; +L_0x2c16180 .delay (10000,10000,10000) L_0x2c16180/d; +L_0x2c162e0/d .functor NAND 1, L_0x2c16180, L_0x2c16090, C4<1>, C4<1>; +L_0x2c162e0 .delay (10000,10000,10000) L_0x2c162e0/d; +L_0x2c163f0/d .functor NOT 1, L_0x2c162e0, C4<0>, C4<0>, C4<0>; +L_0x2c163f0 .delay (10000,10000,10000) L_0x2c163f0/d; +v0x2b7ccc0_0 .net "A", 0 0, L_0x2c17100; 1 drivers +v0x2b7cd60_0 .net "AnandB", 0 0, L_0x2c16180; 1 drivers +v0x2b7ce00_0 .net "AnorB", 0 0, L_0x2c15e00; 1 drivers +v0x2b7ceb0_0 .net "AorB", 0 0, L_0x2c16090; 1 drivers +v0x2b7cf90_0 .net "AxorB", 0 0, L_0x2c163f0; 1 drivers +v0x2b7d040_0 .net "B", 0 0, L_0x2c15f90; 1 drivers +v0x2b7d100_0 .alias "Command", 2 0, v0x2bc67a0_0; +v0x2b7d180_0 .net "OrNorXorOut", 0 0, L_0x2c16df0; 1 drivers +v0x2b7d200_0 .net "XorNor", 0 0, L_0x2c16870; 1 drivers +v0x2b7d2d0_0 .net "nXor", 0 0, L_0x2c162e0; 1 drivers +L_0x2c169f0 .part v0x2bc78e0_0, 2, 1; +L_0x2c16fc0 .part v0x2bc78e0_0, 0, 1; +S_0x2b7c750 .scope module, "mux0" "TwoInMux" 3 83, 3 8, S_0x2b7c110; + .timescale -9 -12; +L_0x2c16550/d .functor NOT 1, L_0x2c169f0, C4<0>, C4<0>, C4<0>; +L_0x2c16550 .delay (10000,10000,10000) L_0x2c16550/d; +L_0x2c16610/d .functor AND 1, L_0x2c163f0, L_0x2c16550, C4<1>, C4<1>; +L_0x2c16610 .delay (20000,20000,20000) L_0x2c16610/d; +L_0x2c16720/d .functor AND 1, L_0x2c15e00, L_0x2c169f0, C4<1>, C4<1>; +L_0x2c16720 .delay (20000,20000,20000) L_0x2c16720/d; +L_0x2c16870/d .functor OR 1, L_0x2c16610, L_0x2c16720, C4<0>, C4<0>; +L_0x2c16870 .delay (20000,20000,20000) L_0x2c16870/d; +v0x2b7c840_0 .net "S", 0 0, L_0x2c169f0; 1 drivers +v0x2b7c900_0 .alias "in0", 0 0, v0x2b7cf90_0; +v0x2b7c9a0_0 .alias "in1", 0 0, v0x2b7ce00_0; +v0x2b7ca40_0 .net "nS", 0 0, L_0x2c16550; 1 drivers +v0x2b7cac0_0 .net "out0", 0 0, L_0x2c16610; 1 drivers +v0x2b7cb60_0 .net "out1", 0 0, L_0x2c16720; 1 drivers +v0x2b7cc40_0 .alias "outfinal", 0 0, v0x2b7d200_0; +S_0x2b7c200 .scope module, "mux1" "TwoInMux" 3 84, 3 8, S_0x2b7c110; + .timescale -9 -12; +L_0x2c16a90/d .functor NOT 1, L_0x2c16fc0, C4<0>, C4<0>, C4<0>; +L_0x2c16a90 .delay (10000,10000,10000) L_0x2c16a90/d; +L_0x2c16b50/d .functor AND 1, L_0x2c16870, L_0x2c16a90, C4<1>, C4<1>; +L_0x2c16b50 .delay (20000,20000,20000) L_0x2c16b50/d; +L_0x2c16ca0/d .functor AND 1, L_0x2c16090, L_0x2c16fc0, C4<1>, C4<1>; +L_0x2c16ca0 .delay (20000,20000,20000) L_0x2c16ca0/d; +L_0x2c16df0/d .functor OR 1, L_0x2c16b50, L_0x2c16ca0, C4<0>, C4<0>; +L_0x2c16df0 .delay (20000,20000,20000) L_0x2c16df0/d; +v0x2b7c2f0_0 .net "S", 0 0, L_0x2c16fc0; 1 drivers +v0x2b7c370_0 .alias "in0", 0 0, v0x2b7d200_0; +v0x2b7c410_0 .alias "in1", 0 0, v0x2b7ceb0_0; +v0x2b7c4b0_0 .net "nS", 0 0, L_0x2c16a90; 1 drivers +v0x2b7c530_0 .net "out0", 0 0, L_0x2c16b50; 1 drivers +v0x2b7c5d0_0 .net "out1", 0 0, L_0x2c16ca0; 1 drivers +v0x2b7c6b0_0 .alias "outfinal", 0 0, v0x2b7d180_0; +S_0x2b7ac10 .scope generate, "orbits[12]" "orbits[12]" 3 196, 3 196, S_0x2b62fd0; + .timescale -9 -12; +P_0x2b7a928 .param/l "i" 3 196, +C4<01100>; +S_0x2b7ad40 .scope module, "attempt" "OrNorXor" 3 198, 3 64, S_0x2b7ac10; + .timescale -9 -12; +L_0x2c16030/d .functor NOR 1, L_0x2c171a0, L_0x2c18510, C4<0>, C4<0>; +L_0x2c16030 .delay (10000,10000,10000) L_0x2c16030/d; +L_0x2c17340/d .functor NOT 1, L_0x2c16030, C4<0>, C4<0>, C4<0>; +L_0x2c17340 .delay (10000,10000,10000) L_0x2c17340/d; +L_0x2c17470/d .functor NAND 1, L_0x2c171a0, L_0x2c18510, C4<1>, C4<1>; +L_0x2c17470 .delay (10000,10000,10000) L_0x2c17470/d; +L_0x2c175d0/d .functor NAND 1, L_0x2c17470, L_0x2c17340, C4<1>, C4<1>; +L_0x2c175d0 .delay (10000,10000,10000) L_0x2c175d0/d; +L_0x2c176e0/d .functor NOT 1, L_0x2c175d0, C4<0>, C4<0>, C4<0>; +L_0x2c176e0 .delay (10000,10000,10000) L_0x2c176e0/d; +v0x2b7b8f0_0 .net "A", 0 0, L_0x2c171a0; 1 drivers +v0x2b7b990_0 .net "AnandB", 0 0, L_0x2c17470; 1 drivers +v0x2b7ba30_0 .net "AnorB", 0 0, L_0x2c16030; 1 drivers +v0x2b7bae0_0 .net "AorB", 0 0, L_0x2c17340; 1 drivers +v0x2b7bbc0_0 .net "AxorB", 0 0, L_0x2c176e0; 1 drivers +v0x2b7bc70_0 .net "B", 0 0, L_0x2c18510; 1 drivers +v0x2b7bd30_0 .alias "Command", 2 0, v0x2bc67a0_0; +v0x2b7bdb0_0 .net "OrNorXorOut", 0 0, L_0x2c180e0; 1 drivers +v0x2b7be30_0 .net "XorNor", 0 0, L_0x2c17b60; 1 drivers +v0x2b7bf00_0 .net "nXor", 0 0, L_0x2c175d0; 1 drivers +L_0x2c17ce0 .part v0x2bc78e0_0, 2, 1; +L_0x2c182b0 .part v0x2bc78e0_0, 0, 1; +S_0x2b7b380 .scope module, "mux0" "TwoInMux" 3 83, 3 8, S_0x2b7ad40; + .timescale -9 -12; +L_0x2c17840/d .functor NOT 1, L_0x2c17ce0, C4<0>, C4<0>, C4<0>; +L_0x2c17840 .delay (10000,10000,10000) L_0x2c17840/d; +L_0x2c17900/d .functor AND 1, L_0x2c176e0, L_0x2c17840, C4<1>, C4<1>; +L_0x2c17900 .delay (20000,20000,20000) L_0x2c17900/d; +L_0x2c17a10/d .functor AND 1, L_0x2c16030, L_0x2c17ce0, C4<1>, C4<1>; +L_0x2c17a10 .delay (20000,20000,20000) L_0x2c17a10/d; +L_0x2c17b60/d .functor OR 1, L_0x2c17900, L_0x2c17a10, C4<0>, C4<0>; +L_0x2c17b60 .delay (20000,20000,20000) L_0x2c17b60/d; +v0x2b7b470_0 .net "S", 0 0, L_0x2c17ce0; 1 drivers +v0x2b7b530_0 .alias "in0", 0 0, v0x2b7bbc0_0; +v0x2b7b5d0_0 .alias "in1", 0 0, v0x2b7ba30_0; +v0x2b7b670_0 .net "nS", 0 0, L_0x2c17840; 1 drivers +v0x2b7b6f0_0 .net "out0", 0 0, L_0x2c17900; 1 drivers +v0x2b7b790_0 .net "out1", 0 0, L_0x2c17a10; 1 drivers +v0x2b7b870_0 .alias "outfinal", 0 0, v0x2b7be30_0; +S_0x2b7ae30 .scope module, "mux1" "TwoInMux" 3 84, 3 8, S_0x2b7ad40; + .timescale -9 -12; +L_0x2c17d80/d .functor NOT 1, L_0x2c182b0, C4<0>, C4<0>, C4<0>; +L_0x2c17d80 .delay (10000,10000,10000) L_0x2c17d80/d; +L_0x2c17e40/d .functor AND 1, L_0x2c17b60, L_0x2c17d80, C4<1>, C4<1>; +L_0x2c17e40 .delay (20000,20000,20000) L_0x2c17e40/d; +L_0x2c17f90/d .functor AND 1, L_0x2c17340, L_0x2c182b0, C4<1>, C4<1>; +L_0x2c17f90 .delay (20000,20000,20000) L_0x2c17f90/d; +L_0x2c180e0/d .functor OR 1, L_0x2c17e40, L_0x2c17f90, C4<0>, C4<0>; +L_0x2c180e0 .delay (20000,20000,20000) L_0x2c180e0/d; +v0x2b7af20_0 .net "S", 0 0, L_0x2c182b0; 1 drivers +v0x2b7afa0_0 .alias "in0", 0 0, v0x2b7be30_0; +v0x2b7b040_0 .alias "in1", 0 0, v0x2b7bae0_0; +v0x2b7b0e0_0 .net "nS", 0 0, L_0x2c17d80; 1 drivers +v0x2b7b160_0 .net "out0", 0 0, L_0x2c17e40; 1 drivers +v0x2b7b200_0 .net "out1", 0 0, L_0x2c17f90; 1 drivers +v0x2b7b2e0_0 .alias "outfinal", 0 0, v0x2b7bdb0_0; +S_0x2b79840 .scope generate, "orbits[13]" "orbits[13]" 3 196, 3 196, S_0x2b62fd0; + .timescale -9 -12; +P_0x2b79558 .param/l "i" 3 196, +C4<01101>; +S_0x2b79970 .scope module, "attempt" "OrNorXor" 3 198, 3 64, S_0x2b79840; + .timescale -9 -12; +L_0x2c17240/d .functor NOR 1, L_0x2c0fe10, L_0x2c185b0, C4<0>, C4<0>; +L_0x2c17240 .delay (10000,10000,10000) L_0x2c17240/d; +L_0x2c18480/d .functor NOT 1, L_0x2c17240, C4<0>, C4<0>, C4<0>; +L_0x2c18480 .delay (10000,10000,10000) L_0x2c18480/d; +L_0x2c18790/d .functor NAND 1, L_0x2c0fe10, L_0x2c185b0, C4<1>, C4<1>; +L_0x2c18790 .delay (10000,10000,10000) L_0x2c18790/d; +L_0x2c188f0/d .functor NAND 1, L_0x2c18790, L_0x2c18480, C4<1>, C4<1>; +L_0x2c188f0 .delay (10000,10000,10000) L_0x2c188f0/d; +L_0x2c18a00/d .functor NOT 1, L_0x2c188f0, C4<0>, C4<0>, C4<0>; +L_0x2c18a00 .delay (10000,10000,10000) L_0x2c18a00/d; +v0x2b7a520_0 .net "A", 0 0, L_0x2c0fe10; 1 drivers +v0x2b7a5c0_0 .net "AnandB", 0 0, L_0x2c18790; 1 drivers +v0x2b7a660_0 .net "AnorB", 0 0, L_0x2c17240; 1 drivers +v0x2b7a710_0 .net "AorB", 0 0, L_0x2c18480; 1 drivers +v0x2b7a7f0_0 .net "AxorB", 0 0, L_0x2c18a00; 1 drivers +v0x2b7a8a0_0 .net "B", 0 0, L_0x2c185b0; 1 drivers +v0x2b7a960_0 .alias "Command", 2 0, v0x2bc67a0_0; +v0x2b7a9e0_0 .net "OrNorXorOut", 0 0, L_0x2c19400; 1 drivers +v0x2b7aa60_0 .net "XorNor", 0 0, L_0x2c18e80; 1 drivers +v0x2b7ab30_0 .net "nXor", 0 0, L_0x2c188f0; 1 drivers +L_0x2c19000 .part v0x2bc78e0_0, 2, 1; +L_0x2c195d0 .part v0x2bc78e0_0, 0, 1; +S_0x2b79fb0 .scope module, "mux0" "TwoInMux" 3 83, 3 8, S_0x2b79970; + .timescale -9 -12; +L_0x2c18b60/d .functor NOT 1, L_0x2c19000, C4<0>, C4<0>, C4<0>; +L_0x2c18b60 .delay (10000,10000,10000) L_0x2c18b60/d; +L_0x2c18c20/d .functor AND 1, L_0x2c18a00, L_0x2c18b60, C4<1>, C4<1>; +L_0x2c18c20 .delay (20000,20000,20000) L_0x2c18c20/d; +L_0x2c18d30/d .functor AND 1, L_0x2c17240, L_0x2c19000, C4<1>, C4<1>; +L_0x2c18d30 .delay (20000,20000,20000) L_0x2c18d30/d; +L_0x2c18e80/d .functor OR 1, L_0x2c18c20, L_0x2c18d30, C4<0>, C4<0>; +L_0x2c18e80 .delay (20000,20000,20000) L_0x2c18e80/d; +v0x2b7a0a0_0 .net "S", 0 0, L_0x2c19000; 1 drivers +v0x2b7a160_0 .alias "in0", 0 0, v0x2b7a7f0_0; +v0x2b7a200_0 .alias "in1", 0 0, v0x2b7a660_0; +v0x2b7a2a0_0 .net "nS", 0 0, L_0x2c18b60; 1 drivers +v0x2b7a320_0 .net "out0", 0 0, L_0x2c18c20; 1 drivers +v0x2b7a3c0_0 .net "out1", 0 0, L_0x2c18d30; 1 drivers +v0x2b7a4a0_0 .alias "outfinal", 0 0, v0x2b7aa60_0; +S_0x2b79a60 .scope module, "mux1" "TwoInMux" 3 84, 3 8, S_0x2b79970; + .timescale -9 -12; +L_0x2c190a0/d .functor NOT 1, L_0x2c195d0, C4<0>, C4<0>, C4<0>; +L_0x2c190a0 .delay (10000,10000,10000) L_0x2c190a0/d; +L_0x2c19160/d .functor AND 1, L_0x2c18e80, L_0x2c190a0, C4<1>, C4<1>; +L_0x2c19160 .delay (20000,20000,20000) L_0x2c19160/d; +L_0x2c192b0/d .functor AND 1, L_0x2c18480, L_0x2c195d0, C4<1>, C4<1>; +L_0x2c192b0 .delay (20000,20000,20000) L_0x2c192b0/d; +L_0x2c19400/d .functor OR 1, L_0x2c19160, L_0x2c192b0, C4<0>, C4<0>; +L_0x2c19400 .delay (20000,20000,20000) L_0x2c19400/d; +v0x2b79b50_0 .net "S", 0 0, L_0x2c195d0; 1 drivers +v0x2b79bd0_0 .alias "in0", 0 0, v0x2b7aa60_0; +v0x2b79c70_0 .alias "in1", 0 0, v0x2b7a710_0; +v0x2b79d10_0 .net "nS", 0 0, L_0x2c190a0; 1 drivers +v0x2b79d90_0 .net "out0", 0 0, L_0x2c19160; 1 drivers +v0x2b79e30_0 .net "out1", 0 0, L_0x2c192b0; 1 drivers +v0x2b79f10_0 .alias "outfinal", 0 0, v0x2b7a9e0_0; +S_0x2b78470 .scope generate, "orbits[14]" "orbits[14]" 3 196, 3 196, S_0x2b62fd0; + .timescale -9 -12; +P_0x2b78188 .param/l "i" 3 196, +C4<01110>; +S_0x2b785a0 .scope module, "attempt" "OrNorXor" 3 198, 3 64, S_0x2b78470; + .timescale -9 -12; +L_0x2c18650/d .functor NOR 1, L_0x2c19920, L_0x2c199c0, C4<0>, C4<0>; +L_0x2c18650 .delay (10000,10000,10000) L_0x2c18650/d; +L_0x2c19ab0/d .functor NOT 1, L_0x2c18650, C4<0>, C4<0>, C4<0>; +L_0x2c19ab0 .delay (10000,10000,10000) L_0x2c19ab0/d; +L_0x2c19ba0/d .functor NAND 1, L_0x2c19920, L_0x2c199c0, C4<1>, C4<1>; +L_0x2c19ba0 .delay (10000,10000,10000) L_0x2c19ba0/d; +L_0x2c19d00/d .functor NAND 1, L_0x2c19ba0, L_0x2c19ab0, C4<1>, C4<1>; +L_0x2c19d00 .delay (10000,10000,10000) L_0x2c19d00/d; +L_0x2c19e10/d .functor NOT 1, L_0x2c19d00, C4<0>, C4<0>, C4<0>; +L_0x2c19e10 .delay (10000,10000,10000) L_0x2c19e10/d; +v0x2b79150_0 .net "A", 0 0, L_0x2c19920; 1 drivers +v0x2b791f0_0 .net "AnandB", 0 0, L_0x2c19ba0; 1 drivers +v0x2b79290_0 .net "AnorB", 0 0, L_0x2c18650; 1 drivers +v0x2b79340_0 .net "AorB", 0 0, L_0x2c19ab0; 1 drivers +v0x2b79420_0 .net "AxorB", 0 0, L_0x2c19e10; 1 drivers +v0x2b794d0_0 .net "B", 0 0, L_0x2c199c0; 1 drivers +v0x2b79590_0 .alias "Command", 2 0, v0x2bc67a0_0; +v0x2b79610_0 .net "OrNorXorOut", 0 0, L_0x2c1a810; 1 drivers +v0x2b79690_0 .net "XorNor", 0 0, L_0x2c1a290; 1 drivers +v0x2b79760_0 .net "nXor", 0 0, L_0x2c19d00; 1 drivers +L_0x2c1a410 .part v0x2bc78e0_0, 2, 1; +L_0x2c1a9e0 .part v0x2bc78e0_0, 0, 1; +S_0x2b78be0 .scope module, "mux0" "TwoInMux" 3 83, 3 8, S_0x2b785a0; + .timescale -9 -12; +L_0x2c19f70/d .functor NOT 1, L_0x2c1a410, C4<0>, C4<0>, C4<0>; +L_0x2c19f70 .delay (10000,10000,10000) L_0x2c19f70/d; +L_0x2c1a030/d .functor AND 1, L_0x2c19e10, L_0x2c19f70, C4<1>, C4<1>; +L_0x2c1a030 .delay (20000,20000,20000) L_0x2c1a030/d; +L_0x2c1a140/d .functor AND 1, L_0x2c18650, L_0x2c1a410, C4<1>, C4<1>; +L_0x2c1a140 .delay (20000,20000,20000) L_0x2c1a140/d; +L_0x2c1a290/d .functor OR 1, L_0x2c1a030, L_0x2c1a140, C4<0>, C4<0>; +L_0x2c1a290 .delay (20000,20000,20000) L_0x2c1a290/d; +v0x2b78cd0_0 .net "S", 0 0, L_0x2c1a410; 1 drivers +v0x2b78d90_0 .alias "in0", 0 0, v0x2b79420_0; +v0x2b78e30_0 .alias "in1", 0 0, v0x2b79290_0; +v0x2b78ed0_0 .net "nS", 0 0, L_0x2c19f70; 1 drivers +v0x2b78f50_0 .net "out0", 0 0, L_0x2c1a030; 1 drivers +v0x2b78ff0_0 .net "out1", 0 0, L_0x2c1a140; 1 drivers +v0x2b790d0_0 .alias "outfinal", 0 0, v0x2b79690_0; +S_0x2b78690 .scope module, "mux1" "TwoInMux" 3 84, 3 8, S_0x2b785a0; + .timescale -9 -12; +L_0x2c1a4b0/d .functor NOT 1, L_0x2c1a9e0, C4<0>, C4<0>, C4<0>; +L_0x2c1a4b0 .delay (10000,10000,10000) L_0x2c1a4b0/d; +L_0x2c1a570/d .functor AND 1, L_0x2c1a290, L_0x2c1a4b0, C4<1>, C4<1>; +L_0x2c1a570 .delay (20000,20000,20000) L_0x2c1a570/d; +L_0x2c1a6c0/d .functor AND 1, L_0x2c19ab0, L_0x2c1a9e0, C4<1>, C4<1>; +L_0x2c1a6c0 .delay (20000,20000,20000) L_0x2c1a6c0/d; +L_0x2c1a810/d .functor OR 1, L_0x2c1a570, L_0x2c1a6c0, C4<0>, C4<0>; +L_0x2c1a810 .delay (20000,20000,20000) L_0x2c1a810/d; +v0x2b78780_0 .net "S", 0 0, L_0x2c1a9e0; 1 drivers +v0x2b78800_0 .alias "in0", 0 0, v0x2b79690_0; +v0x2b788a0_0 .alias "in1", 0 0, v0x2b79340_0; +v0x2b78940_0 .net "nS", 0 0, L_0x2c1a4b0; 1 drivers +v0x2b789c0_0 .net "out0", 0 0, L_0x2c1a570; 1 drivers +v0x2b78a60_0 .net "out1", 0 0, L_0x2c1a6c0; 1 drivers +v0x2b78b40_0 .alias "outfinal", 0 0, v0x2b79610_0; +S_0x2b770a0 .scope generate, "orbits[15]" "orbits[15]" 3 196, 3 196, S_0x2b62fd0; + .timescale -9 -12; +P_0x2b76db8 .param/l "i" 3 196, +C4<01111>; +S_0x2b771d0 .scope module, "attempt" "OrNorXor" 3 198, 3 64, S_0x2b770a0; + .timescale -9 -12; +L_0x2c1ac80/d .functor NOR 1, L_0x2c1be20, L_0x2c1ab20, C4<0>, C4<0>; +L_0x2c1ac80 .delay (10000,10000,10000) L_0x2c1ac80/d; +L_0x2c1ad70/d .functor NOT 1, L_0x2c1ac80, C4<0>, C4<0>, C4<0>; +L_0x2c1ad70 .delay (10000,10000,10000) L_0x2c1ad70/d; +L_0x2c1aea0/d .functor NAND 1, L_0x2c1be20, L_0x2c1ab20, C4<1>, C4<1>; +L_0x2c1aea0 .delay (10000,10000,10000) L_0x2c1aea0/d; +L_0x2c1b000/d .functor NAND 1, L_0x2c1aea0, L_0x2c1ad70, C4<1>, C4<1>; +L_0x2c1b000 .delay (10000,10000,10000) L_0x2c1b000/d; +L_0x2c1b110/d .functor NOT 1, L_0x2c1b000, C4<0>, C4<0>, C4<0>; +L_0x2c1b110 .delay (10000,10000,10000) L_0x2c1b110/d; +v0x2b77d80_0 .net "A", 0 0, L_0x2c1be20; 1 drivers +v0x2b77e20_0 .net "AnandB", 0 0, L_0x2c1aea0; 1 drivers +v0x2b77ec0_0 .net "AnorB", 0 0, L_0x2c1ac80; 1 drivers +v0x2b77f70_0 .net "AorB", 0 0, L_0x2c1ad70; 1 drivers +v0x2b78050_0 .net "AxorB", 0 0, L_0x2c1b110; 1 drivers +v0x2b78100_0 .net "B", 0 0, L_0x2c1ab20; 1 drivers +v0x2b781c0_0 .alias "Command", 2 0, v0x2bc67a0_0; +v0x2b78240_0 .net "OrNorXorOut", 0 0, L_0x2c1bb10; 1 drivers +v0x2b782c0_0 .net "XorNor", 0 0, L_0x2c1b590; 1 drivers +v0x2b78390_0 .net "nXor", 0 0, L_0x2c1b000; 1 drivers +L_0x2c1b710 .part v0x2bc78e0_0, 2, 1; +L_0x2c1bce0 .part v0x2bc78e0_0, 0, 1; +S_0x2b77810 .scope module, "mux0" "TwoInMux" 3 83, 3 8, S_0x2b771d0; + .timescale -9 -12; +L_0x2c1b270/d .functor NOT 1, L_0x2c1b710, C4<0>, C4<0>, C4<0>; +L_0x2c1b270 .delay (10000,10000,10000) L_0x2c1b270/d; +L_0x2c1b330/d .functor AND 1, L_0x2c1b110, L_0x2c1b270, C4<1>, C4<1>; +L_0x2c1b330 .delay (20000,20000,20000) L_0x2c1b330/d; +L_0x2c1b440/d .functor AND 1, L_0x2c1ac80, L_0x2c1b710, C4<1>, C4<1>; +L_0x2c1b440 .delay (20000,20000,20000) L_0x2c1b440/d; +L_0x2c1b590/d .functor OR 1, L_0x2c1b330, L_0x2c1b440, C4<0>, C4<0>; +L_0x2c1b590 .delay (20000,20000,20000) L_0x2c1b590/d; +v0x2b77900_0 .net "S", 0 0, L_0x2c1b710; 1 drivers +v0x2b779c0_0 .alias "in0", 0 0, v0x2b78050_0; +v0x2b77a60_0 .alias "in1", 0 0, v0x2b77ec0_0; +v0x2b77b00_0 .net "nS", 0 0, L_0x2c1b270; 1 drivers +v0x2b77b80_0 .net "out0", 0 0, L_0x2c1b330; 1 drivers +v0x2b77c20_0 .net "out1", 0 0, L_0x2c1b440; 1 drivers +v0x2b77d00_0 .alias "outfinal", 0 0, v0x2b782c0_0; +S_0x2b772c0 .scope module, "mux1" "TwoInMux" 3 84, 3 8, S_0x2b771d0; + .timescale -9 -12; +L_0x2c1b7b0/d .functor NOT 1, L_0x2c1bce0, C4<0>, C4<0>, C4<0>; +L_0x2c1b7b0 .delay (10000,10000,10000) L_0x2c1b7b0/d; +L_0x2c1b870/d .functor AND 1, L_0x2c1b590, L_0x2c1b7b0, C4<1>, C4<1>; +L_0x2c1b870 .delay (20000,20000,20000) L_0x2c1b870/d; +L_0x2c1b9c0/d .functor AND 1, L_0x2c1ad70, L_0x2c1bce0, C4<1>, C4<1>; +L_0x2c1b9c0 .delay (20000,20000,20000) L_0x2c1b9c0/d; +L_0x2c1bb10/d .functor OR 1, L_0x2c1b870, L_0x2c1b9c0, C4<0>, C4<0>; +L_0x2c1bb10 .delay (20000,20000,20000) L_0x2c1bb10/d; +v0x2b773b0_0 .net "S", 0 0, L_0x2c1bce0; 1 drivers +v0x2b77430_0 .alias "in0", 0 0, v0x2b782c0_0; +v0x2b774d0_0 .alias "in1", 0 0, v0x2b77f70_0; +v0x2b77570_0 .net "nS", 0 0, L_0x2c1b7b0; 1 drivers +v0x2b775f0_0 .net "out0", 0 0, L_0x2c1b870; 1 drivers +v0x2b77690_0 .net "out1", 0 0, L_0x2c1b9c0; 1 drivers +v0x2b77770_0 .alias "outfinal", 0 0, v0x2b78240_0; +S_0x2b75cd0 .scope generate, "orbits[16]" "orbits[16]" 3 196, 3 196, S_0x2b62fd0; + .timescale -9 -12; +P_0x2b759e8 .param/l "i" 3 196, +C4<010000>; +S_0x2b75e00 .scope module, "attempt" "OrNorXor" 3 198, 3 64, S_0x2b75cd0; + .timescale -9 -12; +L_0x2c1abc0/d .functor NOR 1, L_0x2c1bec0, L_0x2c1bf60, C4<0>, C4<0>; +L_0x2c1abc0 .delay (10000,10000,10000) L_0x2c1abc0/d; +L_0x2c1c080/d .functor NOT 1, L_0x2c1abc0, C4<0>, C4<0>, C4<0>; +L_0x2c1c080 .delay (10000,10000,10000) L_0x2c1c080/d; +L_0x2c1c190/d .functor NAND 1, L_0x2c1bec0, L_0x2c1bf60, C4<1>, C4<1>; +L_0x2c1c190 .delay (10000,10000,10000) L_0x2c1c190/d; +L_0x2c1c2f0/d .functor NAND 1, L_0x2c1c190, L_0x2c1c080, C4<1>, C4<1>; +L_0x2c1c2f0 .delay (10000,10000,10000) L_0x2c1c2f0/d; +L_0x2c1c400/d .functor NOT 1, L_0x2c1c2f0, C4<0>, C4<0>, C4<0>; +L_0x2c1c400 .delay (10000,10000,10000) L_0x2c1c400/d; +v0x2b769b0_0 .net "A", 0 0, L_0x2c1bec0; 1 drivers +v0x2b76a50_0 .net "AnandB", 0 0, L_0x2c1c190; 1 drivers +v0x2b76af0_0 .net "AnorB", 0 0, L_0x2c1abc0; 1 drivers +v0x2b76ba0_0 .net "AorB", 0 0, L_0x2c1c080; 1 drivers +v0x2b76c80_0 .net "AxorB", 0 0, L_0x2c1c400; 1 drivers +v0x2b76d30_0 .net "B", 0 0, L_0x2c1bf60; 1 drivers +v0x2b76df0_0 .alias "Command", 2 0, v0x2bc67a0_0; +v0x2b76e70_0 .net "OrNorXorOut", 0 0, L_0x2c1ce00; 1 drivers +v0x2b76ef0_0 .net "XorNor", 0 0, L_0x2c1c880; 1 drivers +v0x2b76fc0_0 .net "nXor", 0 0, L_0x2c1c2f0; 1 drivers +L_0x2c1ca00 .part v0x2bc78e0_0, 2, 1; +L_0x2c1cfd0 .part v0x2bc78e0_0, 0, 1; +S_0x2b76440 .scope module, "mux0" "TwoInMux" 3 83, 3 8, S_0x2b75e00; + .timescale -9 -12; +L_0x2c1c560/d .functor NOT 1, L_0x2c1ca00, C4<0>, C4<0>, C4<0>; +L_0x2c1c560 .delay (10000,10000,10000) L_0x2c1c560/d; +L_0x2c1c620/d .functor AND 1, L_0x2c1c400, L_0x2c1c560, C4<1>, C4<1>; +L_0x2c1c620 .delay (20000,20000,20000) L_0x2c1c620/d; +L_0x2c1c730/d .functor AND 1, L_0x2c1abc0, L_0x2c1ca00, C4<1>, C4<1>; +L_0x2c1c730 .delay (20000,20000,20000) L_0x2c1c730/d; +L_0x2c1c880/d .functor OR 1, L_0x2c1c620, L_0x2c1c730, C4<0>, C4<0>; +L_0x2c1c880 .delay (20000,20000,20000) L_0x2c1c880/d; +v0x2b76530_0 .net "S", 0 0, L_0x2c1ca00; 1 drivers +v0x2b765f0_0 .alias "in0", 0 0, v0x2b76c80_0; +v0x2b76690_0 .alias "in1", 0 0, v0x2b76af0_0; +v0x2b76730_0 .net "nS", 0 0, L_0x2c1c560; 1 drivers +v0x2b767b0_0 .net "out0", 0 0, L_0x2c1c620; 1 drivers +v0x2b76850_0 .net "out1", 0 0, L_0x2c1c730; 1 drivers +v0x2b76930_0 .alias "outfinal", 0 0, v0x2b76ef0_0; +S_0x2b75ef0 .scope module, "mux1" "TwoInMux" 3 84, 3 8, S_0x2b75e00; + .timescale -9 -12; +L_0x2c1caa0/d .functor NOT 1, L_0x2c1cfd0, C4<0>, C4<0>, C4<0>; +L_0x2c1caa0 .delay (10000,10000,10000) L_0x2c1caa0/d; +L_0x2c1cb60/d .functor AND 1, L_0x2c1c880, L_0x2c1caa0, C4<1>, C4<1>; +L_0x2c1cb60 .delay (20000,20000,20000) L_0x2c1cb60/d; +L_0x2c1ccb0/d .functor AND 1, L_0x2c1c080, L_0x2c1cfd0, C4<1>, C4<1>; +L_0x2c1ccb0 .delay (20000,20000,20000) L_0x2c1ccb0/d; +L_0x2c1ce00/d .functor OR 1, L_0x2c1cb60, L_0x2c1ccb0, C4<0>, C4<0>; +L_0x2c1ce00 .delay (20000,20000,20000) L_0x2c1ce00/d; +v0x2b75fe0_0 .net "S", 0 0, L_0x2c1cfd0; 1 drivers +v0x2b76060_0 .alias "in0", 0 0, v0x2b76ef0_0; +v0x2b76100_0 .alias "in1", 0 0, v0x2b76ba0_0; +v0x2b761a0_0 .net "nS", 0 0, L_0x2c1caa0; 1 drivers +v0x2b76220_0 .net "out0", 0 0, L_0x2c1cb60; 1 drivers +v0x2b762c0_0 .net "out1", 0 0, L_0x2c1ccb0; 1 drivers +v0x2b763a0_0 .alias "outfinal", 0 0, v0x2b76e70_0; +S_0x2b74900 .scope generate, "orbits[17]" "orbits[17]" 3 196, 3 196, S_0x2b62fd0; + .timescale -9 -12; +P_0x2b74618 .param/l "i" 3 196, +C4<010001>; +S_0x2b74a30 .scope module, "attempt" "OrNorXor" 3 198, 3 64, S_0x2b74900; + .timescale -9 -12; +L_0x2c1d2a0/d .functor NOR 1, L_0x2c1e420, L_0x2c1d110, C4<0>, C4<0>; +L_0x2c1d2a0 .delay (10000,10000,10000) L_0x2c1d2a0/d; +L_0x2c1d390/d .functor NOT 1, L_0x2c1d2a0, C4<0>, C4<0>, C4<0>; +L_0x2c1d390 .delay (10000,10000,10000) L_0x2c1d390/d; +L_0x2c1d4a0/d .functor NAND 1, L_0x2c1e420, L_0x2c1d110, C4<1>, C4<1>; +L_0x2c1d4a0 .delay (10000,10000,10000) L_0x2c1d4a0/d; +L_0x2c1d600/d .functor NAND 1, L_0x2c1d4a0, L_0x2c1d390, C4<1>, C4<1>; +L_0x2c1d600 .delay (10000,10000,10000) L_0x2c1d600/d; +L_0x2c1d710/d .functor NOT 1, L_0x2c1d600, C4<0>, C4<0>, C4<0>; +L_0x2c1d710 .delay (10000,10000,10000) L_0x2c1d710/d; +v0x2b755e0_0 .net "A", 0 0, L_0x2c1e420; 1 drivers +v0x2b75680_0 .net "AnandB", 0 0, L_0x2c1d4a0; 1 drivers +v0x2b75720_0 .net "AnorB", 0 0, L_0x2c1d2a0; 1 drivers +v0x2b757d0_0 .net "AorB", 0 0, L_0x2c1d390; 1 drivers +v0x2b758b0_0 .net "AxorB", 0 0, L_0x2c1d710; 1 drivers +v0x2b75960_0 .net "B", 0 0, L_0x2c1d110; 1 drivers +v0x2b75a20_0 .alias "Command", 2 0, v0x2bc67a0_0; +v0x2b75aa0_0 .net "OrNorXorOut", 0 0, L_0x2c1e110; 1 drivers +v0x2b75b20_0 .net "XorNor", 0 0, L_0x2c1db90; 1 drivers +v0x2b75bf0_0 .net "nXor", 0 0, L_0x2c1d600; 1 drivers +L_0x2c1dd10 .part v0x2bc78e0_0, 2, 1; +L_0x2c1e2e0 .part v0x2bc78e0_0, 0, 1; +S_0x2b75070 .scope module, "mux0" "TwoInMux" 3 83, 3 8, S_0x2b74a30; + .timescale -9 -12; +L_0x2c1d870/d .functor NOT 1, L_0x2c1dd10, C4<0>, C4<0>, C4<0>; +L_0x2c1d870 .delay (10000,10000,10000) L_0x2c1d870/d; +L_0x2c1d930/d .functor AND 1, L_0x2c1d710, L_0x2c1d870, C4<1>, C4<1>; +L_0x2c1d930 .delay (20000,20000,20000) L_0x2c1d930/d; +L_0x2c1da40/d .functor AND 1, L_0x2c1d2a0, L_0x2c1dd10, C4<1>, C4<1>; +L_0x2c1da40 .delay (20000,20000,20000) L_0x2c1da40/d; +L_0x2c1db90/d .functor OR 1, L_0x2c1d930, L_0x2c1da40, C4<0>, C4<0>; +L_0x2c1db90 .delay (20000,20000,20000) L_0x2c1db90/d; +v0x2b75160_0 .net "S", 0 0, L_0x2c1dd10; 1 drivers +v0x2b75220_0 .alias "in0", 0 0, v0x2b758b0_0; +v0x2b752c0_0 .alias "in1", 0 0, v0x2b75720_0; +v0x2b75360_0 .net "nS", 0 0, L_0x2c1d870; 1 drivers +v0x2b753e0_0 .net "out0", 0 0, L_0x2c1d930; 1 drivers +v0x2b75480_0 .net "out1", 0 0, L_0x2c1da40; 1 drivers +v0x2b75560_0 .alias "outfinal", 0 0, v0x2b75b20_0; +S_0x2b74b20 .scope module, "mux1" "TwoInMux" 3 84, 3 8, S_0x2b74a30; + .timescale -9 -12; +L_0x2c1ddb0/d .functor NOT 1, L_0x2c1e2e0, C4<0>, C4<0>, C4<0>; +L_0x2c1ddb0 .delay (10000,10000,10000) L_0x2c1ddb0/d; +L_0x2c1de70/d .functor AND 1, L_0x2c1db90, L_0x2c1ddb0, C4<1>, C4<1>; +L_0x2c1de70 .delay (20000,20000,20000) L_0x2c1de70/d; +L_0x2c1dfc0/d .functor AND 1, L_0x2c1d390, L_0x2c1e2e0, C4<1>, C4<1>; +L_0x2c1dfc0 .delay (20000,20000,20000) L_0x2c1dfc0/d; +L_0x2c1e110/d .functor OR 1, L_0x2c1de70, L_0x2c1dfc0, C4<0>, C4<0>; +L_0x2c1e110 .delay (20000,20000,20000) L_0x2c1e110/d; +v0x2b74c10_0 .net "S", 0 0, L_0x2c1e2e0; 1 drivers +v0x2b74c90_0 .alias "in0", 0 0, v0x2b75b20_0; +v0x2b74d30_0 .alias "in1", 0 0, v0x2b757d0_0; +v0x2b74dd0_0 .net "nS", 0 0, L_0x2c1ddb0; 1 drivers +v0x2b74e50_0 .net "out0", 0 0, L_0x2c1de70; 1 drivers +v0x2b74ef0_0 .net "out1", 0 0, L_0x2c1dfc0; 1 drivers +v0x2b74fd0_0 .alias "outfinal", 0 0, v0x2b75aa0_0; +S_0x2b73530 .scope generate, "orbits[18]" "orbits[18]" 3 196, 3 196, S_0x2b62fd0; + .timescale -9 -12; +P_0x2b73248 .param/l "i" 3 196, +C4<010010>; +S_0x2b73660 .scope module, "attempt" "OrNorXor" 3 198, 3 64, S_0x2b73530; + .timescale -9 -12; +L_0x2c1d1b0/d .functor NOR 1, L_0x2c1e4c0, L_0x2c1e560, C4<0>, C4<0>; +L_0x2c1d1b0 .delay (10000,10000,10000) L_0x2c1d1b0/d; +L_0x2c1e660/d .functor NOT 1, L_0x2c1d1b0, C4<0>, C4<0>, C4<0>; +L_0x2c1e660 .delay (10000,10000,10000) L_0x2c1e660/d; +L_0x2c1e790/d .functor NAND 1, L_0x2c1e4c0, L_0x2c1e560, C4<1>, C4<1>; +L_0x2c1e790 .delay (10000,10000,10000) L_0x2c1e790/d; +L_0x2c1e8f0/d .functor NAND 1, L_0x2c1e790, L_0x2c1e660, C4<1>, C4<1>; +L_0x2c1e8f0 .delay (10000,10000,10000) L_0x2c1e8f0/d; +L_0x2c1ea00/d .functor NOT 1, L_0x2c1e8f0, C4<0>, C4<0>, C4<0>; +L_0x2c1ea00 .delay (10000,10000,10000) L_0x2c1ea00/d; +v0x2b74210_0 .net "A", 0 0, L_0x2c1e4c0; 1 drivers +v0x2b742b0_0 .net "AnandB", 0 0, L_0x2c1e790; 1 drivers +v0x2b74350_0 .net "AnorB", 0 0, L_0x2c1d1b0; 1 drivers +v0x2b74400_0 .net "AorB", 0 0, L_0x2c1e660; 1 drivers +v0x2b744e0_0 .net "AxorB", 0 0, L_0x2c1ea00; 1 drivers +v0x2b74590_0 .net "B", 0 0, L_0x2c1e560; 1 drivers +v0x2b74650_0 .alias "Command", 2 0, v0x2bc67a0_0; +v0x2b746d0_0 .net "OrNorXorOut", 0 0, L_0x2c1f400; 1 drivers +v0x2b74750_0 .net "XorNor", 0 0, L_0x2c1ee80; 1 drivers +v0x2b74820_0 .net "nXor", 0 0, L_0x2c1e8f0; 1 drivers +L_0x2c1f000 .part v0x2bc78e0_0, 2, 1; +L_0x2c1f5d0 .part v0x2bc78e0_0, 0, 1; +S_0x2b73ca0 .scope module, "mux0" "TwoInMux" 3 83, 3 8, S_0x2b73660; + .timescale -9 -12; +L_0x2c1eb60/d .functor NOT 1, L_0x2c1f000, C4<0>, C4<0>, C4<0>; +L_0x2c1eb60 .delay (10000,10000,10000) L_0x2c1eb60/d; +L_0x2c1ec20/d .functor AND 1, L_0x2c1ea00, L_0x2c1eb60, C4<1>, C4<1>; +L_0x2c1ec20 .delay (20000,20000,20000) L_0x2c1ec20/d; +L_0x2c1ed30/d .functor AND 1, L_0x2c1d1b0, L_0x2c1f000, C4<1>, C4<1>; +L_0x2c1ed30 .delay (20000,20000,20000) L_0x2c1ed30/d; +L_0x2c1ee80/d .functor OR 1, L_0x2c1ec20, L_0x2c1ed30, C4<0>, C4<0>; +L_0x2c1ee80 .delay (20000,20000,20000) L_0x2c1ee80/d; +v0x2b73d90_0 .net "S", 0 0, L_0x2c1f000; 1 drivers +v0x2b73e50_0 .alias "in0", 0 0, v0x2b744e0_0; +v0x2b73ef0_0 .alias "in1", 0 0, v0x2b74350_0; +v0x2b73f90_0 .net "nS", 0 0, L_0x2c1eb60; 1 drivers +v0x2b74010_0 .net "out0", 0 0, L_0x2c1ec20; 1 drivers +v0x2b740b0_0 .net "out1", 0 0, L_0x2c1ed30; 1 drivers +v0x2b74190_0 .alias "outfinal", 0 0, v0x2b74750_0; +S_0x2b73750 .scope module, "mux1" "TwoInMux" 3 84, 3 8, S_0x2b73660; + .timescale -9 -12; +L_0x2c1f0a0/d .functor NOT 1, L_0x2c1f5d0, C4<0>, C4<0>, C4<0>; +L_0x2c1f0a0 .delay (10000,10000,10000) L_0x2c1f0a0/d; +L_0x2c1f160/d .functor AND 1, L_0x2c1ee80, L_0x2c1f0a0, C4<1>, C4<1>; +L_0x2c1f160 .delay (20000,20000,20000) L_0x2c1f160/d; +L_0x2c1f2b0/d .functor AND 1, L_0x2c1e660, L_0x2c1f5d0, C4<1>, C4<1>; +L_0x2c1f2b0 .delay (20000,20000,20000) L_0x2c1f2b0/d; +L_0x2c1f400/d .functor OR 1, L_0x2c1f160, L_0x2c1f2b0, C4<0>, C4<0>; +L_0x2c1f400 .delay (20000,20000,20000) L_0x2c1f400/d; +v0x2b73840_0 .net "S", 0 0, L_0x2c1f5d0; 1 drivers +v0x2b738c0_0 .alias "in0", 0 0, v0x2b74750_0; +v0x2b73960_0 .alias "in1", 0 0, v0x2b74400_0; +v0x2b73a00_0 .net "nS", 0 0, L_0x2c1f0a0; 1 drivers +v0x2b73a80_0 .net "out0", 0 0, L_0x2c1f160; 1 drivers +v0x2b73b20_0 .net "out1", 0 0, L_0x2c1f2b0; 1 drivers +v0x2b73c00_0 .alias "outfinal", 0 0, v0x2b746d0_0; +S_0x2b72160 .scope generate, "orbits[19]" "orbits[19]" 3 196, 3 196, S_0x2b62fd0; + .timescale -9 -12; +P_0x2b71e78 .param/l "i" 3 196, +C4<010011>; +S_0x2b72290 .scope module, "attempt" "OrNorXor" 3 198, 3 64, S_0x2b72160; + .timescale -9 -12; +L_0x2c1e600/d .functor NOR 1, L_0x2c20a10, L_0x2c1f710, C4<0>, C4<0>; +L_0x2c1e600 .delay (10000,10000,10000) L_0x2c1e600/d; +L_0x2c1f960/d .functor NOT 1, L_0x2c1e600, C4<0>, C4<0>, C4<0>; +L_0x2c1f960 .delay (10000,10000,10000) L_0x2c1f960/d; +L_0x2c1fa90/d .functor NAND 1, L_0x2c20a10, L_0x2c1f710, C4<1>, C4<1>; +L_0x2c1fa90 .delay (10000,10000,10000) L_0x2c1fa90/d; +L_0x2c1fbf0/d .functor NAND 1, L_0x2c1fa90, L_0x2c1f960, C4<1>, C4<1>; +L_0x2c1fbf0 .delay (10000,10000,10000) L_0x2c1fbf0/d; +L_0x2c1fd00/d .functor NOT 1, L_0x2c1fbf0, C4<0>, C4<0>, C4<0>; +L_0x2c1fd00 .delay (10000,10000,10000) L_0x2c1fd00/d; +v0x2b72e40_0 .net "A", 0 0, L_0x2c20a10; 1 drivers +v0x2b72ee0_0 .net "AnandB", 0 0, L_0x2c1fa90; 1 drivers +v0x2b72f80_0 .net "AnorB", 0 0, L_0x2c1e600; 1 drivers +v0x2b73030_0 .net "AorB", 0 0, L_0x2c1f960; 1 drivers +v0x2b73110_0 .net "AxorB", 0 0, L_0x2c1fd00; 1 drivers +v0x2b731c0_0 .net "B", 0 0, L_0x2c1f710; 1 drivers +v0x2b73280_0 .alias "Command", 2 0, v0x2bc67a0_0; +v0x2b73300_0 .net "OrNorXorOut", 0 0, L_0x2c20700; 1 drivers +v0x2b73380_0 .net "XorNor", 0 0, L_0x2c20180; 1 drivers +v0x2b73450_0 .net "nXor", 0 0, L_0x2c1fbf0; 1 drivers +L_0x2c20300 .part v0x2bc78e0_0, 2, 1; +L_0x2c208d0 .part v0x2bc78e0_0, 0, 1; +S_0x2b728d0 .scope module, "mux0" "TwoInMux" 3 83, 3 8, S_0x2b72290; + .timescale -9 -12; +L_0x2c1fe60/d .functor NOT 1, L_0x2c20300, C4<0>, C4<0>, C4<0>; +L_0x2c1fe60 .delay (10000,10000,10000) L_0x2c1fe60/d; +L_0x2c1ff20/d .functor AND 1, L_0x2c1fd00, L_0x2c1fe60, C4<1>, C4<1>; +L_0x2c1ff20 .delay (20000,20000,20000) L_0x2c1ff20/d; +L_0x2c20030/d .functor AND 1, L_0x2c1e600, L_0x2c20300, C4<1>, C4<1>; +L_0x2c20030 .delay (20000,20000,20000) L_0x2c20030/d; +L_0x2c20180/d .functor OR 1, L_0x2c1ff20, L_0x2c20030, C4<0>, C4<0>; +L_0x2c20180 .delay (20000,20000,20000) L_0x2c20180/d; +v0x2b729c0_0 .net "S", 0 0, L_0x2c20300; 1 drivers +v0x2b72a80_0 .alias "in0", 0 0, v0x2b73110_0; +v0x2b72b20_0 .alias "in1", 0 0, v0x2b72f80_0; +v0x2b72bc0_0 .net "nS", 0 0, L_0x2c1fe60; 1 drivers +v0x2b72c40_0 .net "out0", 0 0, L_0x2c1ff20; 1 drivers +v0x2b72ce0_0 .net "out1", 0 0, L_0x2c20030; 1 drivers +v0x2b72dc0_0 .alias "outfinal", 0 0, v0x2b73380_0; +S_0x2b72380 .scope module, "mux1" "TwoInMux" 3 84, 3 8, S_0x2b72290; + .timescale -9 -12; +L_0x2c203a0/d .functor NOT 1, L_0x2c208d0, C4<0>, C4<0>, C4<0>; +L_0x2c203a0 .delay (10000,10000,10000) L_0x2c203a0/d; +L_0x2c20460/d .functor AND 1, L_0x2c20180, L_0x2c203a0, C4<1>, C4<1>; +L_0x2c20460 .delay (20000,20000,20000) L_0x2c20460/d; +L_0x2c205b0/d .functor AND 1, L_0x2c1f960, L_0x2c208d0, C4<1>, C4<1>; +L_0x2c205b0 .delay (20000,20000,20000) L_0x2c205b0/d; +L_0x2c20700/d .functor OR 1, L_0x2c20460, L_0x2c205b0, C4<0>, C4<0>; +L_0x2c20700 .delay (20000,20000,20000) L_0x2c20700/d; +v0x2b72470_0 .net "S", 0 0, L_0x2c208d0; 1 drivers +v0x2b724f0_0 .alias "in0", 0 0, v0x2b73380_0; +v0x2b72590_0 .alias "in1", 0 0, v0x2b73030_0; +v0x2b72630_0 .net "nS", 0 0, L_0x2c203a0; 1 drivers +v0x2b726b0_0 .net "out0", 0 0, L_0x2c20460; 1 drivers +v0x2b72750_0 .net "out1", 0 0, L_0x2c205b0; 1 drivers +v0x2b72830_0 .alias "outfinal", 0 0, v0x2b73300_0; +S_0x2b70d90 .scope generate, "orbits[20]" "orbits[20]" 3 196, 3 196, S_0x2b62fd0; + .timescale -9 -12; +P_0x2b70aa8 .param/l "i" 3 196, +C4<010100>; +S_0x2b70ec0 .scope module, "attempt" "OrNorXor" 3 198, 3 64, S_0x2b70d90; + .timescale -9 -12; +L_0x2c1f7b0/d .functor NOR 1, L_0x2c20ab0, L_0x2c20b50, C4<0>, C4<0>; +L_0x2c1f7b0 .delay (10000,10000,10000) L_0x2c1f7b0/d; +L_0x2c20c80/d .functor NOT 1, L_0x2c1f7b0, C4<0>, C4<0>, C4<0>; +L_0x2c20c80 .delay (10000,10000,10000) L_0x2c20c80/d; +L_0x2c20d90/d .functor NAND 1, L_0x2c20ab0, L_0x2c20b50, C4<1>, C4<1>; +L_0x2c20d90 .delay (10000,10000,10000) L_0x2c20d90/d; +L_0x2c20ef0/d .functor NAND 1, L_0x2c20d90, L_0x2c20c80, C4<1>, C4<1>; +L_0x2c20ef0 .delay (10000,10000,10000) L_0x2c20ef0/d; +L_0x2c21000/d .functor NOT 1, L_0x2c20ef0, C4<0>, C4<0>, C4<0>; +L_0x2c21000 .delay (10000,10000,10000) L_0x2c21000/d; +v0x2b71a70_0 .net "A", 0 0, L_0x2c20ab0; 1 drivers +v0x2b71b10_0 .net "AnandB", 0 0, L_0x2c20d90; 1 drivers +v0x2b71bb0_0 .net "AnorB", 0 0, L_0x2c1f7b0; 1 drivers +v0x2b71c60_0 .net "AorB", 0 0, L_0x2c20c80; 1 drivers +v0x2b71d40_0 .net "AxorB", 0 0, L_0x2c21000; 1 drivers +v0x2b71df0_0 .net "B", 0 0, L_0x2c20b50; 1 drivers +v0x2b71eb0_0 .alias "Command", 2 0, v0x2bc67a0_0; +v0x2b71f30_0 .net "OrNorXorOut", 0 0, L_0x2c21a00; 1 drivers +v0x2b71fb0_0 .net "XorNor", 0 0, L_0x2c21480; 1 drivers +v0x2b72080_0 .net "nXor", 0 0, L_0x2c20ef0; 1 drivers +L_0x2c21600 .part v0x2bc78e0_0, 2, 1; +L_0x2c21bd0 .part v0x2bc78e0_0, 0, 1; +S_0x2b71500 .scope module, "mux0" "TwoInMux" 3 83, 3 8, S_0x2b70ec0; + .timescale -9 -12; +L_0x2c21160/d .functor NOT 1, L_0x2c21600, C4<0>, C4<0>, C4<0>; +L_0x2c21160 .delay (10000,10000,10000) L_0x2c21160/d; +L_0x2c21220/d .functor AND 1, L_0x2c21000, L_0x2c21160, C4<1>, C4<1>; +L_0x2c21220 .delay (20000,20000,20000) L_0x2c21220/d; +L_0x2c21330/d .functor AND 1, L_0x2c1f7b0, L_0x2c21600, C4<1>, C4<1>; +L_0x2c21330 .delay (20000,20000,20000) L_0x2c21330/d; +L_0x2c21480/d .functor OR 1, L_0x2c21220, L_0x2c21330, C4<0>, C4<0>; +L_0x2c21480 .delay (20000,20000,20000) L_0x2c21480/d; +v0x2b715f0_0 .net "S", 0 0, L_0x2c21600; 1 drivers +v0x2b716b0_0 .alias "in0", 0 0, v0x2b71d40_0; +v0x2b71750_0 .alias "in1", 0 0, v0x2b71bb0_0; +v0x2b717f0_0 .net "nS", 0 0, L_0x2c21160; 1 drivers +v0x2b71870_0 .net "out0", 0 0, L_0x2c21220; 1 drivers +v0x2b71910_0 .net "out1", 0 0, L_0x2c21330; 1 drivers +v0x2b719f0_0 .alias "outfinal", 0 0, v0x2b71fb0_0; +S_0x2b70fb0 .scope module, "mux1" "TwoInMux" 3 84, 3 8, S_0x2b70ec0; + .timescale -9 -12; +L_0x2c216a0/d .functor NOT 1, L_0x2c21bd0, C4<0>, C4<0>, C4<0>; +L_0x2c216a0 .delay (10000,10000,10000) L_0x2c216a0/d; +L_0x2c21760/d .functor AND 1, L_0x2c21480, L_0x2c216a0, C4<1>, C4<1>; +L_0x2c21760 .delay (20000,20000,20000) L_0x2c21760/d; +L_0x2c218b0/d .functor AND 1, L_0x2c20c80, L_0x2c21bd0, C4<1>, C4<1>; +L_0x2c218b0 .delay (20000,20000,20000) L_0x2c218b0/d; +L_0x2c21a00/d .functor OR 1, L_0x2c21760, L_0x2c218b0, C4<0>, C4<0>; +L_0x2c21a00 .delay (20000,20000,20000) L_0x2c21a00/d; +v0x2b710a0_0 .net "S", 0 0, L_0x2c21bd0; 1 drivers +v0x2b71120_0 .alias "in0", 0 0, v0x2b71fb0_0; +v0x2b711c0_0 .alias "in1", 0 0, v0x2b71c60_0; +v0x2b71260_0 .net "nS", 0 0, L_0x2c216a0; 1 drivers +v0x2b712e0_0 .net "out0", 0 0, L_0x2c21760; 1 drivers +v0x2b71380_0 .net "out1", 0 0, L_0x2c218b0; 1 drivers +v0x2b71460_0 .alias "outfinal", 0 0, v0x2b71f30_0; +S_0x2b6f9c0 .scope generate, "orbits[21]" "orbits[21]" 3 196, 3 196, S_0x2b62fd0; + .timescale -9 -12; +P_0x2b6f6d8 .param/l "i" 3 196, +C4<010101>; +S_0x2b6faf0 .scope module, "attempt" "OrNorXor" 3 198, 3 64, S_0x2b6f9c0; + .timescale -9 -12; +L_0x2c20bf0/d .functor NOR 1, L_0x2c23020, L_0x2c21d10, C4<0>, C4<0>; +L_0x2c20bf0 .delay (10000,10000,10000) L_0x2c20bf0/d; +L_0x2c21f90/d .functor NOT 1, L_0x2c20bf0, C4<0>, C4<0>, C4<0>; +L_0x2c21f90 .delay (10000,10000,10000) L_0x2c21f90/d; +L_0x2c220a0/d .functor NAND 1, L_0x2c23020, L_0x2c21d10, C4<1>, C4<1>; +L_0x2c220a0 .delay (10000,10000,10000) L_0x2c220a0/d; +L_0x2c22200/d .functor NAND 1, L_0x2c220a0, L_0x2c21f90, C4<1>, C4<1>; +L_0x2c22200 .delay (10000,10000,10000) L_0x2c22200/d; +L_0x2c22310/d .functor NOT 1, L_0x2c22200, C4<0>, C4<0>, C4<0>; +L_0x2c22310 .delay (10000,10000,10000) L_0x2c22310/d; +v0x2b706a0_0 .net "A", 0 0, L_0x2c23020; 1 drivers +v0x2b70740_0 .net "AnandB", 0 0, L_0x2c220a0; 1 drivers +v0x2b707e0_0 .net "AnorB", 0 0, L_0x2c20bf0; 1 drivers +v0x2b70890_0 .net "AorB", 0 0, L_0x2c21f90; 1 drivers +v0x2b70970_0 .net "AxorB", 0 0, L_0x2c22310; 1 drivers +v0x2b70a20_0 .net "B", 0 0, L_0x2c21d10; 1 drivers +v0x2b70ae0_0 .alias "Command", 2 0, v0x2bc67a0_0; +v0x2b70b60_0 .net "OrNorXorOut", 0 0, L_0x2c22d10; 1 drivers +v0x2b70be0_0 .net "XorNor", 0 0, L_0x2c22790; 1 drivers +v0x2b70cb0_0 .net "nXor", 0 0, L_0x2c22200; 1 drivers +L_0x2c22910 .part v0x2bc78e0_0, 2, 1; +L_0x2c22ee0 .part v0x2bc78e0_0, 0, 1; +S_0x2b70130 .scope module, "mux0" "TwoInMux" 3 83, 3 8, S_0x2b6faf0; + .timescale -9 -12; +L_0x2c22470/d .functor NOT 1, L_0x2c22910, C4<0>, C4<0>, C4<0>; +L_0x2c22470 .delay (10000,10000,10000) L_0x2c22470/d; +L_0x2c22530/d .functor AND 1, L_0x2c22310, L_0x2c22470, C4<1>, C4<1>; +L_0x2c22530 .delay (20000,20000,20000) L_0x2c22530/d; +L_0x2c22640/d .functor AND 1, L_0x2c20bf0, L_0x2c22910, C4<1>, C4<1>; +L_0x2c22640 .delay (20000,20000,20000) L_0x2c22640/d; +L_0x2c22790/d .functor OR 1, L_0x2c22530, L_0x2c22640, C4<0>, C4<0>; +L_0x2c22790 .delay (20000,20000,20000) L_0x2c22790/d; +v0x2b70220_0 .net "S", 0 0, L_0x2c22910; 1 drivers +v0x2b702e0_0 .alias "in0", 0 0, v0x2b70970_0; +v0x2b70380_0 .alias "in1", 0 0, v0x2b707e0_0; +v0x2b70420_0 .net "nS", 0 0, L_0x2c22470; 1 drivers +v0x2b704a0_0 .net "out0", 0 0, L_0x2c22530; 1 drivers +v0x2b70540_0 .net "out1", 0 0, L_0x2c22640; 1 drivers +v0x2b70620_0 .alias "outfinal", 0 0, v0x2b70be0_0; +S_0x2b6fbe0 .scope module, "mux1" "TwoInMux" 3 84, 3 8, S_0x2b6faf0; + .timescale -9 -12; +L_0x2c229b0/d .functor NOT 1, L_0x2c22ee0, C4<0>, C4<0>, C4<0>; +L_0x2c229b0 .delay (10000,10000,10000) L_0x2c229b0/d; +L_0x2c22a70/d .functor AND 1, L_0x2c22790, L_0x2c229b0, C4<1>, C4<1>; +L_0x2c22a70 .delay (20000,20000,20000) L_0x2c22a70/d; +L_0x2c22bc0/d .functor AND 1, L_0x2c21f90, L_0x2c22ee0, C4<1>, C4<1>; +L_0x2c22bc0 .delay (20000,20000,20000) L_0x2c22bc0/d; +L_0x2c22d10/d .functor OR 1, L_0x2c22a70, L_0x2c22bc0, C4<0>, C4<0>; +L_0x2c22d10 .delay (20000,20000,20000) L_0x2c22d10/d; +v0x2b6fcd0_0 .net "S", 0 0, L_0x2c22ee0; 1 drivers +v0x2b6fd50_0 .alias "in0", 0 0, v0x2b70be0_0; +v0x2b6fdf0_0 .alias "in1", 0 0, v0x2b70890_0; +v0x2b6fe90_0 .net "nS", 0 0, L_0x2c229b0; 1 drivers +v0x2b6ff10_0 .net "out0", 0 0, L_0x2c22a70; 1 drivers +v0x2b6ffb0_0 .net "out1", 0 0, L_0x2c22bc0; 1 drivers +v0x2b70090_0 .alias "outfinal", 0 0, v0x2b70b60_0; +S_0x2b6e5f0 .scope generate, "orbits[22]" "orbits[22]" 3 196, 3 196, S_0x2b62fd0; + .timescale -9 -12; +P_0x2b6e308 .param/l "i" 3 196, +C4<010110>; +S_0x2b6e720 .scope module, "attempt" "OrNorXor" 3 198, 3 64, S_0x2b6e5f0; + .timescale -9 -12; +L_0x2c21db0/d .functor NOR 1, L_0x2c230c0, L_0x2c23160, C4<0>, C4<0>; +L_0x2c21db0 .delay (10000,10000,10000) L_0x2c21db0/d; +L_0x2c21ea0/d .functor NOT 1, L_0x2c21db0, C4<0>, C4<0>, C4<0>; +L_0x2c21ea0 .delay (10000,10000,10000) L_0x2c21ea0/d; +L_0x2c23390/d .functor NAND 1, L_0x2c230c0, L_0x2c23160, C4<1>, C4<1>; +L_0x2c23390 .delay (10000,10000,10000) L_0x2c23390/d; +L_0x2c234f0/d .functor NAND 1, L_0x2c23390, L_0x2c21ea0, C4<1>, C4<1>; +L_0x2c234f0 .delay (10000,10000,10000) L_0x2c234f0/d; +L_0x2c23600/d .functor NOT 1, L_0x2c234f0, C4<0>, C4<0>, C4<0>; +L_0x2c23600 .delay (10000,10000,10000) L_0x2c23600/d; +v0x2b6f2d0_0 .net "A", 0 0, L_0x2c230c0; 1 drivers +v0x2b6f370_0 .net "AnandB", 0 0, L_0x2c23390; 1 drivers +v0x2b6f410_0 .net "AnorB", 0 0, L_0x2c21db0; 1 drivers +v0x2b6f4c0_0 .net "AorB", 0 0, L_0x2c21ea0; 1 drivers +v0x2b6f5a0_0 .net "AxorB", 0 0, L_0x2c23600; 1 drivers +v0x2b6f650_0 .net "B", 0 0, L_0x2c23160; 1 drivers +v0x2b6f710_0 .alias "Command", 2 0, v0x2bc67a0_0; +v0x2b6f790_0 .net "OrNorXorOut", 0 0, L_0x2c24000; 1 drivers +v0x2b6f810_0 .net "XorNor", 0 0, L_0x2c23a80; 1 drivers +v0x2b6f8e0_0 .net "nXor", 0 0, L_0x2c234f0; 1 drivers +L_0x2c23c00 .part v0x2bc78e0_0, 2, 1; +L_0x2c241d0 .part v0x2bc78e0_0, 0, 1; +S_0x2b6ed60 .scope module, "mux0" "TwoInMux" 3 83, 3 8, S_0x2b6e720; + .timescale -9 -12; +L_0x2c23760/d .functor NOT 1, L_0x2c23c00, C4<0>, C4<0>, C4<0>; +L_0x2c23760 .delay (10000,10000,10000) L_0x2c23760/d; +L_0x2c23820/d .functor AND 1, L_0x2c23600, L_0x2c23760, C4<1>, C4<1>; +L_0x2c23820 .delay (20000,20000,20000) L_0x2c23820/d; +L_0x2c23930/d .functor AND 1, L_0x2c21db0, L_0x2c23c00, C4<1>, C4<1>; +L_0x2c23930 .delay (20000,20000,20000) L_0x2c23930/d; +L_0x2c23a80/d .functor OR 1, L_0x2c23820, L_0x2c23930, C4<0>, C4<0>; +L_0x2c23a80 .delay (20000,20000,20000) L_0x2c23a80/d; +v0x2b6ee50_0 .net "S", 0 0, L_0x2c23c00; 1 drivers +v0x2b6ef10_0 .alias "in0", 0 0, v0x2b6f5a0_0; +v0x2b6efb0_0 .alias "in1", 0 0, v0x2b6f410_0; +v0x2b6f050_0 .net "nS", 0 0, L_0x2c23760; 1 drivers +v0x2b6f0d0_0 .net "out0", 0 0, L_0x2c23820; 1 drivers +v0x2b6f170_0 .net "out1", 0 0, L_0x2c23930; 1 drivers +v0x2b6f250_0 .alias "outfinal", 0 0, v0x2b6f810_0; +S_0x2b6e810 .scope module, "mux1" "TwoInMux" 3 84, 3 8, S_0x2b6e720; + .timescale -9 -12; +L_0x2c23ca0/d .functor NOT 1, L_0x2c241d0, C4<0>, C4<0>, C4<0>; +L_0x2c23ca0 .delay (10000,10000,10000) L_0x2c23ca0/d; +L_0x2c23d60/d .functor AND 1, L_0x2c23a80, L_0x2c23ca0, C4<1>, C4<1>; +L_0x2c23d60 .delay (20000,20000,20000) L_0x2c23d60/d; +L_0x2c23eb0/d .functor AND 1, L_0x2c21ea0, L_0x2c241d0, C4<1>, C4<1>; +L_0x2c23eb0 .delay (20000,20000,20000) L_0x2c23eb0/d; +L_0x2c24000/d .functor OR 1, L_0x2c23d60, L_0x2c23eb0, C4<0>, C4<0>; +L_0x2c24000 .delay (20000,20000,20000) L_0x2c24000/d; +v0x2b6e900_0 .net "S", 0 0, L_0x2c241d0; 1 drivers +v0x2b6e980_0 .alias "in0", 0 0, v0x2b6f810_0; +v0x2b6ea20_0 .alias "in1", 0 0, v0x2b6f4c0_0; +v0x2b6eac0_0 .net "nS", 0 0, L_0x2c23ca0; 1 drivers +v0x2b6eb40_0 .net "out0", 0 0, L_0x2c23d60; 1 drivers +v0x2b6ebe0_0 .net "out1", 0 0, L_0x2c23eb0; 1 drivers +v0x2b6ecc0_0 .alias "outfinal", 0 0, v0x2b6f790_0; +S_0x2b6d220 .scope generate, "orbits[23]" "orbits[23]" 3 196, 3 196, S_0x2b62fd0; + .timescale -9 -12; +P_0x2b6cf38 .param/l "i" 3 196, +C4<010111>; +S_0x2b6d350 .scope module, "attempt" "OrNorXor" 3 198, 3 64, S_0x2b6d220; + .timescale -9 -12; +L_0x2c23200/d .functor NOR 1, L_0x2c25610, L_0x2c24310, C4<0>, C4<0>; +L_0x2c23200 .delay (10000,10000,10000) L_0x2c23200/d; +L_0x2c24580/d .functor NOT 1, L_0x2c23200, C4<0>, C4<0>, C4<0>; +L_0x2c24580 .delay (10000,10000,10000) L_0x2c24580/d; +L_0x2c24690/d .functor NAND 1, L_0x2c25610, L_0x2c24310, C4<1>, C4<1>; +L_0x2c24690 .delay (10000,10000,10000) L_0x2c24690/d; +L_0x2c247f0/d .functor NAND 1, L_0x2c24690, L_0x2c24580, C4<1>, C4<1>; +L_0x2c247f0 .delay (10000,10000,10000) L_0x2c247f0/d; +L_0x2c24900/d .functor NOT 1, L_0x2c247f0, C4<0>, C4<0>, C4<0>; +L_0x2c24900 .delay (10000,10000,10000) L_0x2c24900/d; +v0x2b6df00_0 .net "A", 0 0, L_0x2c25610; 1 drivers +v0x2b6dfa0_0 .net "AnandB", 0 0, L_0x2c24690; 1 drivers +v0x2b6e040_0 .net "AnorB", 0 0, L_0x2c23200; 1 drivers +v0x2b6e0f0_0 .net "AorB", 0 0, L_0x2c24580; 1 drivers +v0x2b6e1d0_0 .net "AxorB", 0 0, L_0x2c24900; 1 drivers +v0x2b6e280_0 .net "B", 0 0, L_0x2c24310; 1 drivers +v0x2b6e340_0 .alias "Command", 2 0, v0x2bc67a0_0; +v0x2b6e3c0_0 .net "OrNorXorOut", 0 0, L_0x2c25300; 1 drivers +v0x2b6e440_0 .net "XorNor", 0 0, L_0x2c24d80; 1 drivers +v0x2b6e510_0 .net "nXor", 0 0, L_0x2c247f0; 1 drivers +L_0x2c24f00 .part v0x2bc78e0_0, 2, 1; +L_0x2c254d0 .part v0x2bc78e0_0, 0, 1; +S_0x2b6d990 .scope module, "mux0" "TwoInMux" 3 83, 3 8, S_0x2b6d350; + .timescale -9 -12; +L_0x2c24a60/d .functor NOT 1, L_0x2c24f00, C4<0>, C4<0>, C4<0>; +L_0x2c24a60 .delay (10000,10000,10000) L_0x2c24a60/d; +L_0x2c24b20/d .functor AND 1, L_0x2c24900, L_0x2c24a60, C4<1>, C4<1>; +L_0x2c24b20 .delay (20000,20000,20000) L_0x2c24b20/d; +L_0x2c24c30/d .functor AND 1, L_0x2c23200, L_0x2c24f00, C4<1>, C4<1>; +L_0x2c24c30 .delay (20000,20000,20000) L_0x2c24c30/d; +L_0x2c24d80/d .functor OR 1, L_0x2c24b20, L_0x2c24c30, C4<0>, C4<0>; +L_0x2c24d80 .delay (20000,20000,20000) L_0x2c24d80/d; +v0x2b6da80_0 .net "S", 0 0, L_0x2c24f00; 1 drivers +v0x2b6db40_0 .alias "in0", 0 0, v0x2b6e1d0_0; +v0x2b6dbe0_0 .alias "in1", 0 0, v0x2b6e040_0; +v0x2b6dc80_0 .net "nS", 0 0, L_0x2c24a60; 1 drivers +v0x2b6dd00_0 .net "out0", 0 0, L_0x2c24b20; 1 drivers +v0x2b6dda0_0 .net "out1", 0 0, L_0x2c24c30; 1 drivers +v0x2b6de80_0 .alias "outfinal", 0 0, v0x2b6e440_0; +S_0x2b6d440 .scope module, "mux1" "TwoInMux" 3 84, 3 8, S_0x2b6d350; + .timescale -9 -12; +L_0x2c24fa0/d .functor NOT 1, L_0x2c254d0, C4<0>, C4<0>, C4<0>; +L_0x2c24fa0 .delay (10000,10000,10000) L_0x2c24fa0/d; +L_0x2c25060/d .functor AND 1, L_0x2c24d80, L_0x2c24fa0, C4<1>, C4<1>; +L_0x2c25060 .delay (20000,20000,20000) L_0x2c25060/d; +L_0x2c251b0/d .functor AND 1, L_0x2c24580, L_0x2c254d0, C4<1>, C4<1>; +L_0x2c251b0 .delay (20000,20000,20000) L_0x2c251b0/d; +L_0x2c25300/d .functor OR 1, L_0x2c25060, L_0x2c251b0, C4<0>, C4<0>; +L_0x2c25300 .delay (20000,20000,20000) L_0x2c25300/d; +v0x2b6d530_0 .net "S", 0 0, L_0x2c254d0; 1 drivers +v0x2b6d5b0_0 .alias "in0", 0 0, v0x2b6e440_0; +v0x2b6d650_0 .alias "in1", 0 0, v0x2b6e0f0_0; +v0x2b6d6f0_0 .net "nS", 0 0, L_0x2c24fa0; 1 drivers +v0x2b6d770_0 .net "out0", 0 0, L_0x2c25060; 1 drivers +v0x2b6d810_0 .net "out1", 0 0, L_0x2c251b0; 1 drivers +v0x2b6d8f0_0 .alias "outfinal", 0 0, v0x2b6e3c0_0; +S_0x2b6be50 .scope generate, "orbits[24]" "orbits[24]" 3 196, 3 196, S_0x2b62fd0; + .timescale -9 -12; +P_0x2b6bb68 .param/l "i" 3 196, +C4<011000>; +S_0x2b6bf80 .scope module, "attempt" "OrNorXor" 3 198, 3 64, S_0x2b6be50; + .timescale -9 -12; +L_0x2c243b0/d .functor NOR 1, L_0x2c256b0, L_0x2c25750, C4<0>, C4<0>; +L_0x2c243b0 .delay (10000,10000,10000) L_0x2c243b0/d; +L_0x2c244a0/d .functor NOT 1, L_0x2c243b0, C4<0>, C4<0>, C4<0>; +L_0x2c244a0 .delay (10000,10000,10000) L_0x2c244a0/d; +L_0x2c25990/d .functor NAND 1, L_0x2c256b0, L_0x2c25750, C4<1>, C4<1>; +L_0x2c25990 .delay (10000,10000,10000) L_0x2c25990/d; +L_0x2c25af0/d .functor NAND 1, L_0x2c25990, L_0x2c244a0, C4<1>, C4<1>; +L_0x2c25af0 .delay (10000,10000,10000) L_0x2c25af0/d; +L_0x2c25c00/d .functor NOT 1, L_0x2c25af0, C4<0>, C4<0>, C4<0>; +L_0x2c25c00 .delay (10000,10000,10000) L_0x2c25c00/d; +v0x2b6cb30_0 .net "A", 0 0, L_0x2c256b0; 1 drivers +v0x2b6cbd0_0 .net "AnandB", 0 0, L_0x2c25990; 1 drivers +v0x2b6cc70_0 .net "AnorB", 0 0, L_0x2c243b0; 1 drivers +v0x2b6cd20_0 .net "AorB", 0 0, L_0x2c244a0; 1 drivers +v0x2b6ce00_0 .net "AxorB", 0 0, L_0x2c25c00; 1 drivers +v0x2b6ceb0_0 .net "B", 0 0, L_0x2c25750; 1 drivers +v0x2b6cf70_0 .alias "Command", 2 0, v0x2bc67a0_0; +v0x2b6cff0_0 .net "OrNorXorOut", 0 0, L_0x2c26600; 1 drivers +v0x2b6d070_0 .net "XorNor", 0 0, L_0x2c26080; 1 drivers +v0x2b6d140_0 .net "nXor", 0 0, L_0x2c25af0; 1 drivers +L_0x2c26200 .part v0x2bc78e0_0, 2, 1; +L_0x2c267d0 .part v0x2bc78e0_0, 0, 1; +S_0x2b6c5c0 .scope module, "mux0" "TwoInMux" 3 83, 3 8, S_0x2b6bf80; + .timescale -9 -12; +L_0x2c25d60/d .functor NOT 1, L_0x2c26200, C4<0>, C4<0>, C4<0>; +L_0x2c25d60 .delay (10000,10000,10000) L_0x2c25d60/d; +L_0x2c25e20/d .functor AND 1, L_0x2c25c00, L_0x2c25d60, C4<1>, C4<1>; +L_0x2c25e20 .delay (20000,20000,20000) L_0x2c25e20/d; +L_0x2c25f30/d .functor AND 1, L_0x2c243b0, L_0x2c26200, C4<1>, C4<1>; +L_0x2c25f30 .delay (20000,20000,20000) L_0x2c25f30/d; +L_0x2c26080/d .functor OR 1, L_0x2c25e20, L_0x2c25f30, C4<0>, C4<0>; +L_0x2c26080 .delay (20000,20000,20000) L_0x2c26080/d; +v0x2b6c6b0_0 .net "S", 0 0, L_0x2c26200; 1 drivers +v0x2b6c770_0 .alias "in0", 0 0, v0x2b6ce00_0; +v0x2b6c810_0 .alias "in1", 0 0, v0x2b6cc70_0; +v0x2b6c8b0_0 .net "nS", 0 0, L_0x2c25d60; 1 drivers +v0x2b6c930_0 .net "out0", 0 0, L_0x2c25e20; 1 drivers +v0x2b6c9d0_0 .net "out1", 0 0, L_0x2c25f30; 1 drivers +v0x2b6cab0_0 .alias "outfinal", 0 0, v0x2b6d070_0; +S_0x2b6c070 .scope module, "mux1" "TwoInMux" 3 84, 3 8, S_0x2b6bf80; + .timescale -9 -12; +L_0x2c262a0/d .functor NOT 1, L_0x2c267d0, C4<0>, C4<0>, C4<0>; +L_0x2c262a0 .delay (10000,10000,10000) L_0x2c262a0/d; +L_0x2c26360/d .functor AND 1, L_0x2c26080, L_0x2c262a0, C4<1>, C4<1>; +L_0x2c26360 .delay (20000,20000,20000) L_0x2c26360/d; +L_0x2c264b0/d .functor AND 1, L_0x2c244a0, L_0x2c267d0, C4<1>, C4<1>; +L_0x2c264b0 .delay (20000,20000,20000) L_0x2c264b0/d; +L_0x2c26600/d .functor OR 1, L_0x2c26360, L_0x2c264b0, C4<0>, C4<0>; +L_0x2c26600 .delay (20000,20000,20000) L_0x2c26600/d; +v0x2b6c160_0 .net "S", 0 0, L_0x2c267d0; 1 drivers +v0x2b6c1e0_0 .alias "in0", 0 0, v0x2b6d070_0; +v0x2b6c280_0 .alias "in1", 0 0, v0x2b6cd20_0; +v0x2b6c320_0 .net "nS", 0 0, L_0x2c262a0; 1 drivers +v0x2b6c3a0_0 .net "out0", 0 0, L_0x2c26360; 1 drivers +v0x2b6c440_0 .net "out1", 0 0, L_0x2c264b0; 1 drivers +v0x2b6c520_0 .alias "outfinal", 0 0, v0x2b6cff0_0; +S_0x2b6aa80 .scope generate, "orbits[25]" "orbits[25]" 3 196, 3 196, S_0x2b62fd0; + .timescale -9 -12; +P_0x2b6a798 .param/l "i" 3 196, +C4<011001>; +S_0x2b6abb0 .scope module, "attempt" "OrNorXor" 3 198, 3 64, S_0x2b6aa80; + .timescale -9 -12; +L_0x2c257f0/d .functor NOR 1, L_0x2c27c10, L_0x2c26910, C4<0>, C4<0>; +L_0x2c257f0 .delay (10000,10000,10000) L_0x2c257f0/d; +L_0x2c26b60/d .functor NOT 1, L_0x2c257f0, C4<0>, C4<0>, C4<0>; +L_0x2c26b60 .delay (10000,10000,10000) L_0x2c26b60/d; +L_0x2c26c90/d .functor NAND 1, L_0x2c27c10, L_0x2c26910, C4<1>, C4<1>; +L_0x2c26c90 .delay (10000,10000,10000) L_0x2c26c90/d; +L_0x2c26df0/d .functor NAND 1, L_0x2c26c90, L_0x2c26b60, C4<1>, C4<1>; +L_0x2c26df0 .delay (10000,10000,10000) L_0x2c26df0/d; +L_0x2c26f00/d .functor NOT 1, L_0x2c26df0, C4<0>, C4<0>, C4<0>; +L_0x2c26f00 .delay (10000,10000,10000) L_0x2c26f00/d; +v0x2b6b760_0 .net "A", 0 0, L_0x2c27c10; 1 drivers +v0x2b6b800_0 .net "AnandB", 0 0, L_0x2c26c90; 1 drivers +v0x2b6b8a0_0 .net "AnorB", 0 0, L_0x2c257f0; 1 drivers +v0x2b6b950_0 .net "AorB", 0 0, L_0x2c26b60; 1 drivers +v0x2b6ba30_0 .net "AxorB", 0 0, L_0x2c26f00; 1 drivers +v0x2b6bae0_0 .net "B", 0 0, L_0x2c26910; 1 drivers +v0x2b6bba0_0 .alias "Command", 2 0, v0x2bc67a0_0; +v0x2b6bc20_0 .net "OrNorXorOut", 0 0, L_0x2c27900; 1 drivers +v0x2b6bca0_0 .net "XorNor", 0 0, L_0x2c27380; 1 drivers +v0x2b6bd70_0 .net "nXor", 0 0, L_0x2c26df0; 1 drivers +L_0x2c27500 .part v0x2bc78e0_0, 2, 1; +L_0x2c27ad0 .part v0x2bc78e0_0, 0, 1; +S_0x2b6b1f0 .scope module, "mux0" "TwoInMux" 3 83, 3 8, S_0x2b6abb0; + .timescale -9 -12; +L_0x2c27060/d .functor NOT 1, L_0x2c27500, C4<0>, C4<0>, C4<0>; +L_0x2c27060 .delay (10000,10000,10000) L_0x2c27060/d; +L_0x2c27120/d .functor AND 1, L_0x2c26f00, L_0x2c27060, C4<1>, C4<1>; +L_0x2c27120 .delay (20000,20000,20000) L_0x2c27120/d; +L_0x2c27230/d .functor AND 1, L_0x2c257f0, L_0x2c27500, C4<1>, C4<1>; +L_0x2c27230 .delay (20000,20000,20000) L_0x2c27230/d; +L_0x2c27380/d .functor OR 1, L_0x2c27120, L_0x2c27230, C4<0>, C4<0>; +L_0x2c27380 .delay (20000,20000,20000) L_0x2c27380/d; +v0x2b6b2e0_0 .net "S", 0 0, L_0x2c27500; 1 drivers +v0x2b6b3a0_0 .alias "in0", 0 0, v0x2b6ba30_0; +v0x2b6b440_0 .alias "in1", 0 0, v0x2b6b8a0_0; +v0x2b6b4e0_0 .net "nS", 0 0, L_0x2c27060; 1 drivers +v0x2b6b560_0 .net "out0", 0 0, L_0x2c27120; 1 drivers +v0x2b6b600_0 .net "out1", 0 0, L_0x2c27230; 1 drivers +v0x2b6b6e0_0 .alias "outfinal", 0 0, v0x2b6bca0_0; +S_0x2b6aca0 .scope module, "mux1" "TwoInMux" 3 84, 3 8, S_0x2b6abb0; + .timescale -9 -12; +L_0x2c275a0/d .functor NOT 1, L_0x2c27ad0, C4<0>, C4<0>, C4<0>; +L_0x2c275a0 .delay (10000,10000,10000) L_0x2c275a0/d; +L_0x2c27660/d .functor AND 1, L_0x2c27380, L_0x2c275a0, C4<1>, C4<1>; +L_0x2c27660 .delay (20000,20000,20000) L_0x2c27660/d; +L_0x2c277b0/d .functor AND 1, L_0x2c26b60, L_0x2c27ad0, C4<1>, C4<1>; +L_0x2c277b0 .delay (20000,20000,20000) L_0x2c277b0/d; +L_0x2c27900/d .functor OR 1, L_0x2c27660, L_0x2c277b0, C4<0>, C4<0>; +L_0x2c27900 .delay (20000,20000,20000) L_0x2c27900/d; +v0x2b6ad90_0 .net "S", 0 0, L_0x2c27ad0; 1 drivers +v0x2b6ae10_0 .alias "in0", 0 0, v0x2b6bca0_0; +v0x2b6aeb0_0 .alias "in1", 0 0, v0x2b6b950_0; +v0x2b6af50_0 .net "nS", 0 0, L_0x2c275a0; 1 drivers +v0x2b6afd0_0 .net "out0", 0 0, L_0x2c27660; 1 drivers +v0x2b6b070_0 .net "out1", 0 0, L_0x2c277b0; 1 drivers +v0x2b6b150_0 .alias "outfinal", 0 0, v0x2b6bc20_0; +S_0x2b696b0 .scope generate, "orbits[26]" "orbits[26]" 3 196, 3 196, S_0x2b62fd0; + .timescale -9 -12; +P_0x2b693c8 .param/l "i" 3 196, +C4<011010>; +S_0x2b697e0 .scope module, "attempt" "OrNorXor" 3 198, 3 64, S_0x2b696b0; + .timescale -9 -12; +L_0x2c269b0/d .functor NOR 1, L_0x2c27cb0, L_0x2c27d50, C4<0>, C4<0>; +L_0x2c269b0 .delay (10000,10000,10000) L_0x2c269b0/d; +L_0x2c26aa0/d .functor NOT 1, L_0x2c269b0, C4<0>, C4<0>, C4<0>; +L_0x2c26aa0 .delay (10000,10000,10000) L_0x2c26aa0/d; +L_0x2c27f80/d .functor NAND 1, L_0x2c27cb0, L_0x2c27d50, C4<1>, C4<1>; +L_0x2c27f80 .delay (10000,10000,10000) L_0x2c27f80/d; +L_0x2c280e0/d .functor NAND 1, L_0x2c27f80, L_0x2c26aa0, C4<1>, C4<1>; +L_0x2c280e0 .delay (10000,10000,10000) L_0x2c280e0/d; +L_0x2c281f0/d .functor NOT 1, L_0x2c280e0, C4<0>, C4<0>, C4<0>; +L_0x2c281f0 .delay (10000,10000,10000) L_0x2c281f0/d; +v0x2b6a390_0 .net "A", 0 0, L_0x2c27cb0; 1 drivers +v0x2b6a430_0 .net "AnandB", 0 0, L_0x2c27f80; 1 drivers +v0x2b6a4d0_0 .net "AnorB", 0 0, L_0x2c269b0; 1 drivers +v0x2b6a580_0 .net "AorB", 0 0, L_0x2c26aa0; 1 drivers +v0x2b6a660_0 .net "AxorB", 0 0, L_0x2c281f0; 1 drivers +v0x2b6a710_0 .net "B", 0 0, L_0x2c27d50; 1 drivers +v0x2b6a7d0_0 .alias "Command", 2 0, v0x2bc67a0_0; +v0x2b6a850_0 .net "OrNorXorOut", 0 0, L_0x2c28bf0; 1 drivers +v0x2b6a8d0_0 .net "XorNor", 0 0, L_0x2c28670; 1 drivers +v0x2b6a9a0_0 .net "nXor", 0 0, L_0x2c280e0; 1 drivers +L_0x2c287f0 .part v0x2bc78e0_0, 2, 1; +L_0x2c28dc0 .part v0x2bc78e0_0, 0, 1; +S_0x2b69e20 .scope module, "mux0" "TwoInMux" 3 83, 3 8, S_0x2b697e0; + .timescale -9 -12; +L_0x2c28350/d .functor NOT 1, L_0x2c287f0, C4<0>, C4<0>, C4<0>; +L_0x2c28350 .delay (10000,10000,10000) L_0x2c28350/d; +L_0x2c28410/d .functor AND 1, L_0x2c281f0, L_0x2c28350, C4<1>, C4<1>; +L_0x2c28410 .delay (20000,20000,20000) L_0x2c28410/d; +L_0x2c28520/d .functor AND 1, L_0x2c269b0, L_0x2c287f0, C4<1>, C4<1>; +L_0x2c28520 .delay (20000,20000,20000) L_0x2c28520/d; +L_0x2c28670/d .functor OR 1, L_0x2c28410, L_0x2c28520, C4<0>, C4<0>; +L_0x2c28670 .delay (20000,20000,20000) L_0x2c28670/d; +v0x2b69f10_0 .net "S", 0 0, L_0x2c287f0; 1 drivers +v0x2b69fd0_0 .alias "in0", 0 0, v0x2b6a660_0; +v0x2b6a070_0 .alias "in1", 0 0, v0x2b6a4d0_0; +v0x2b6a110_0 .net "nS", 0 0, L_0x2c28350; 1 drivers +v0x2b6a190_0 .net "out0", 0 0, L_0x2c28410; 1 drivers +v0x2b6a230_0 .net "out1", 0 0, L_0x2c28520; 1 drivers +v0x2b6a310_0 .alias "outfinal", 0 0, v0x2b6a8d0_0; +S_0x2b698d0 .scope module, "mux1" "TwoInMux" 3 84, 3 8, S_0x2b697e0; + .timescale -9 -12; +L_0x2c28890/d .functor NOT 1, L_0x2c28dc0, C4<0>, C4<0>, C4<0>; +L_0x2c28890 .delay (10000,10000,10000) L_0x2c28890/d; +L_0x2c28950/d .functor AND 1, L_0x2c28670, L_0x2c28890, C4<1>, C4<1>; +L_0x2c28950 .delay (20000,20000,20000) L_0x2c28950/d; +L_0x2c28aa0/d .functor AND 1, L_0x2c26aa0, L_0x2c28dc0, C4<1>, C4<1>; +L_0x2c28aa0 .delay (20000,20000,20000) L_0x2c28aa0/d; +L_0x2c28bf0/d .functor OR 1, L_0x2c28950, L_0x2c28aa0, C4<0>, C4<0>; +L_0x2c28bf0 .delay (20000,20000,20000) L_0x2c28bf0/d; +v0x2b699c0_0 .net "S", 0 0, L_0x2c28dc0; 1 drivers +v0x2b69a40_0 .alias "in0", 0 0, v0x2b6a8d0_0; +v0x2b69ae0_0 .alias "in1", 0 0, v0x2b6a580_0; +v0x2b69b80_0 .net "nS", 0 0, L_0x2c28890; 1 drivers +v0x2b69c00_0 .net "out0", 0 0, L_0x2c28950; 1 drivers +v0x2b69ca0_0 .net "out1", 0 0, L_0x2c28aa0; 1 drivers +v0x2b69d80_0 .alias "outfinal", 0 0, v0x2b6a850_0; +S_0x2b682c0 .scope generate, "orbits[27]" "orbits[27]" 3 196, 3 196, S_0x2b62fd0; + .timescale -9 -12; +P_0x2b683b8 .param/l "i" 3 196, +C4<011011>; +S_0x2b68430 .scope module, "attempt" "OrNorXor" 3 198, 3 64, S_0x2b682c0; + .timescale -9 -12; +L_0x2c27df0/d .functor NOR 1, L_0x2c2a210, L_0x2c28f00, C4<0>, C4<0>; +L_0x2c27df0 .delay (10000,10000,10000) L_0x2c27df0/d; +L_0x2c29180/d .functor NOT 1, L_0x2c27df0, C4<0>, C4<0>, C4<0>; +L_0x2c29180 .delay (10000,10000,10000) L_0x2c29180/d; +L_0x2c29290/d .functor NAND 1, L_0x2c2a210, L_0x2c28f00, C4<1>, C4<1>; +L_0x2c29290 .delay (10000,10000,10000) L_0x2c29290/d; +L_0x2c293f0/d .functor NAND 1, L_0x2c29290, L_0x2c29180, C4<1>, C4<1>; +L_0x2c293f0 .delay (10000,10000,10000) L_0x2c293f0/d; +L_0x2c29500/d .functor NOT 1, L_0x2c293f0, C4<0>, C4<0>, C4<0>; +L_0x2c29500 .delay (10000,10000,10000) L_0x2c29500/d; +v0x2b68fc0_0 .net "A", 0 0, L_0x2c2a210; 1 drivers +v0x2b69060_0 .net "AnandB", 0 0, L_0x2c29290; 1 drivers +v0x2b69100_0 .net "AnorB", 0 0, L_0x2c27df0; 1 drivers +v0x2b691b0_0 .net "AorB", 0 0, L_0x2c29180; 1 drivers +v0x2b69290_0 .net "AxorB", 0 0, L_0x2c29500; 1 drivers +v0x2b69340_0 .net "B", 0 0, L_0x2c28f00; 1 drivers +v0x2b69400_0 .alias "Command", 2 0, v0x2bc67a0_0; +v0x2b69480_0 .net "OrNorXorOut", 0 0, L_0x2c29f00; 1 drivers +v0x2b69500_0 .net "XorNor", 0 0, L_0x2c29980; 1 drivers +v0x2b695d0_0 .net "nXor", 0 0, L_0x2c293f0; 1 drivers +L_0x2c29b00 .part v0x2bc78e0_0, 2, 1; +L_0x2c2a0d0 .part v0x2bc78e0_0, 0, 1; +S_0x2b68a50 .scope module, "mux0" "TwoInMux" 3 83, 3 8, S_0x2b68430; + .timescale -9 -12; +L_0x2c29660/d .functor NOT 1, L_0x2c29b00, C4<0>, C4<0>, C4<0>; +L_0x2c29660 .delay (10000,10000,10000) L_0x2c29660/d; +L_0x2c29720/d .functor AND 1, L_0x2c29500, L_0x2c29660, C4<1>, C4<1>; +L_0x2c29720 .delay (20000,20000,20000) L_0x2c29720/d; +L_0x2c29830/d .functor AND 1, L_0x2c27df0, L_0x2c29b00, C4<1>, C4<1>; +L_0x2c29830 .delay (20000,20000,20000) L_0x2c29830/d; +L_0x2c29980/d .functor OR 1, L_0x2c29720, L_0x2c29830, C4<0>, C4<0>; +L_0x2c29980 .delay (20000,20000,20000) L_0x2c29980/d; +v0x2b68b40_0 .net "S", 0 0, L_0x2c29b00; 1 drivers +v0x2b68c00_0 .alias "in0", 0 0, v0x2b69290_0; +v0x2b68ca0_0 .alias "in1", 0 0, v0x2b69100_0; +v0x2b68d40_0 .net "nS", 0 0, L_0x2c29660; 1 drivers +v0x2b68dc0_0 .net "out0", 0 0, L_0x2c29720; 1 drivers +v0x2b68e60_0 .net "out1", 0 0, L_0x2c29830; 1 drivers +v0x2b68f40_0 .alias "outfinal", 0 0, v0x2b69500_0; +S_0x2b68520 .scope module, "mux1" "TwoInMux" 3 84, 3 8, S_0x2b68430; + .timescale -9 -12; +L_0x2c29ba0/d .functor NOT 1, L_0x2c2a0d0, C4<0>, C4<0>, C4<0>; +L_0x2c29ba0 .delay (10000,10000,10000) L_0x2c29ba0/d; +L_0x2c29c60/d .functor AND 1, L_0x2c29980, L_0x2c29ba0, C4<1>, C4<1>; +L_0x2c29c60 .delay (20000,20000,20000) L_0x2c29c60/d; +L_0x2c29db0/d .functor AND 1, L_0x2c29180, L_0x2c2a0d0, C4<1>, C4<1>; +L_0x2c29db0 .delay (20000,20000,20000) L_0x2c29db0/d; +L_0x2c29f00/d .functor OR 1, L_0x2c29c60, L_0x2c29db0, C4<0>, C4<0>; +L_0x2c29f00 .delay (20000,20000,20000) L_0x2c29f00/d; +v0x2b68610_0 .net "S", 0 0, L_0x2c2a0d0; 1 drivers +v0x2b68690_0 .alias "in0", 0 0, v0x2b69500_0; +v0x2b68710_0 .alias "in1", 0 0, v0x2b691b0_0; +v0x2b687b0_0 .net "nS", 0 0, L_0x2c29ba0; 1 drivers +v0x2b68830_0 .net "out0", 0 0, L_0x2c29c60; 1 drivers +v0x2b688d0_0 .net "out1", 0 0, L_0x2c29db0; 1 drivers +v0x2b689b0_0 .alias "outfinal", 0 0, v0x2b69480_0; +S_0x2b66f80 .scope generate, "orbits[28]" "orbits[28]" 3 196, 3 196, S_0x2b62fd0; + .timescale -9 -12; +P_0x2b66c98 .param/l "i" 3 196, +C4<011100>; +S_0x2b670b0 .scope module, "attempt" "OrNorXor" 3 198, 3 64, S_0x2b66f80; + .timescale -9 -12; +L_0x2c28fa0/d .functor NOR 1, L_0x2c2a2b0, L_0x2c2a350, C4<0>, C4<0>; +L_0x2c28fa0 .delay (10000,10000,10000) L_0x2c28fa0/d; +L_0x2c29090/d .functor NOT 1, L_0x2c28fa0, C4<0>, C4<0>, C4<0>; +L_0x2c29090 .delay (10000,10000,10000) L_0x2c29090/d; +L_0x2c2a590/d .functor NAND 1, L_0x2c2a2b0, L_0x2c2a350, C4<1>, C4<1>; +L_0x2c2a590 .delay (10000,10000,10000) L_0x2c2a590/d; +L_0x2c2a6f0/d .functor NAND 1, L_0x2c2a590, L_0x2c29090, C4<1>, C4<1>; +L_0x2c2a6f0 .delay (10000,10000,10000) L_0x2c2a6f0/d; +L_0x2c2a800/d .functor NOT 1, L_0x2c2a6f0, C4<0>, C4<0>, C4<0>; +L_0x2c2a800 .delay (10000,10000,10000) L_0x2c2a800/d; +v0x2b67c60_0 .net "A", 0 0, L_0x2c2a2b0; 1 drivers +v0x2b67d00_0 .net "AnandB", 0 0, L_0x2c2a590; 1 drivers +v0x2b67da0_0 .net "AnorB", 0 0, L_0x2c28fa0; 1 drivers +v0x2b67e50_0 .net "AorB", 0 0, L_0x2c29090; 1 drivers +v0x2b67f30_0 .net "AxorB", 0 0, L_0x2c2a800; 1 drivers +v0x2b67fe0_0 .net "B", 0 0, L_0x2c2a350; 1 drivers +v0x2b68060_0 .alias "Command", 2 0, v0x2bc67a0_0; +v0x2b680e0_0 .net "OrNorXorOut", 0 0, L_0x2c2b200; 1 drivers +v0x2b68160_0 .net "XorNor", 0 0, L_0x2c2ac80; 1 drivers +v0x2b681e0_0 .net "nXor", 0 0, L_0x2c2a6f0; 1 drivers +L_0x2c2ae00 .part v0x2bc78e0_0, 2, 1; +L_0x2c2b3d0 .part v0x2bc78e0_0, 0, 1; +S_0x2b676f0 .scope module, "mux0" "TwoInMux" 3 83, 3 8, S_0x2b670b0; + .timescale -9 -12; +L_0x2c2a960/d .functor NOT 1, L_0x2c2ae00, C4<0>, C4<0>, C4<0>; +L_0x2c2a960 .delay (10000,10000,10000) L_0x2c2a960/d; +L_0x2c2aa20/d .functor AND 1, L_0x2c2a800, L_0x2c2a960, C4<1>, C4<1>; +L_0x2c2aa20 .delay (20000,20000,20000) L_0x2c2aa20/d; +L_0x2c2ab30/d .functor AND 1, L_0x2c28fa0, L_0x2c2ae00, C4<1>, C4<1>; +L_0x2c2ab30 .delay (20000,20000,20000) L_0x2c2ab30/d; +L_0x2c2ac80/d .functor OR 1, L_0x2c2aa20, L_0x2c2ab30, C4<0>, C4<0>; +L_0x2c2ac80 .delay (20000,20000,20000) L_0x2c2ac80/d; +v0x2b677e0_0 .net "S", 0 0, L_0x2c2ae00; 1 drivers +v0x2b678a0_0 .alias "in0", 0 0, v0x2b67f30_0; +v0x2b67940_0 .alias "in1", 0 0, v0x2b67da0_0; +v0x2b679e0_0 .net "nS", 0 0, L_0x2c2a960; 1 drivers +v0x2b67a60_0 .net "out0", 0 0, L_0x2c2aa20; 1 drivers +v0x2b67b00_0 .net "out1", 0 0, L_0x2c2ab30; 1 drivers +v0x2b67be0_0 .alias "outfinal", 0 0, v0x2b68160_0; +S_0x2b671a0 .scope module, "mux1" "TwoInMux" 3 84, 3 8, S_0x2b670b0; + .timescale -9 -12; +L_0x2c2aea0/d .functor NOT 1, L_0x2c2b3d0, C4<0>, C4<0>, C4<0>; +L_0x2c2aea0 .delay (10000,10000,10000) L_0x2c2aea0/d; +L_0x2c2af60/d .functor AND 1, L_0x2c2ac80, L_0x2c2aea0, C4<1>, C4<1>; +L_0x2c2af60 .delay (20000,20000,20000) L_0x2c2af60/d; +L_0x2c2b0b0/d .functor AND 1, L_0x2c29090, L_0x2c2b3d0, C4<1>, C4<1>; +L_0x2c2b0b0 .delay (20000,20000,20000) L_0x2c2b0b0/d; +L_0x2c2b200/d .functor OR 1, L_0x2c2af60, L_0x2c2b0b0, C4<0>, C4<0>; +L_0x2c2b200 .delay (20000,20000,20000) L_0x2c2b200/d; +v0x2b67290_0 .net "S", 0 0, L_0x2c2b3d0; 1 drivers +v0x2b67310_0 .alias "in0", 0 0, v0x2b68160_0; +v0x2b673b0_0 .alias "in1", 0 0, v0x2b67e50_0; +v0x2b67450_0 .net "nS", 0 0, L_0x2c2aea0; 1 drivers +v0x2b674d0_0 .net "out0", 0 0, L_0x2c2af60; 1 drivers +v0x2b67570_0 .net "out1", 0 0, L_0x2c2b0b0; 1 drivers +v0x2b67650_0 .alias "outfinal", 0 0, v0x2b680e0_0; +S_0x2b65bb0 .scope generate, "orbits[29]" "orbits[29]" 3 196, 3 196, S_0x2b62fd0; + .timescale -9 -12; +P_0x2b658c8 .param/l "i" 3 196, +C4<011101>; +S_0x2b65ce0 .scope module, "attempt" "OrNorXor" 3 198, 3 64, S_0x2b65bb0; + .timescale -9 -12; +L_0x2c2a3f0/d .functor NOR 1, L_0x2c19710, L_0x2c197b0, C4<0>, C4<0>; +L_0x2c2a3f0 .delay (10000,10000,10000) L_0x2c2a3f0/d; +L_0x2c2a4e0/d .functor NOT 1, L_0x2c2a3f0, C4<0>, C4<0>, C4<0>; +L_0x2c2a4e0 .delay (10000,10000,10000) L_0x2c2a4e0/d; +L_0x2c2b890/d .functor NAND 1, L_0x2c19710, L_0x2c197b0, C4<1>, C4<1>; +L_0x2c2b890 .delay (10000,10000,10000) L_0x2c2b890/d; +L_0x2c2b9f0/d .functor NAND 1, L_0x2c2b890, L_0x2c2a4e0, C4<1>, C4<1>; +L_0x2c2b9f0 .delay (10000,10000,10000) L_0x2c2b9f0/d; +L_0x2c2bb00/d .functor NOT 1, L_0x2c2b9f0, C4<0>, C4<0>, C4<0>; +L_0x2c2bb00 .delay (10000,10000,10000) L_0x2c2bb00/d; +v0x2b66890_0 .net "A", 0 0, L_0x2c19710; 1 drivers +v0x2b66930_0 .net "AnandB", 0 0, L_0x2c2b890; 1 drivers +v0x2b669d0_0 .net "AnorB", 0 0, L_0x2c2a3f0; 1 drivers +v0x2b66a80_0 .net "AorB", 0 0, L_0x2c2a4e0; 1 drivers +v0x2b66b60_0 .net "AxorB", 0 0, L_0x2c2bb00; 1 drivers +v0x2b66c10_0 .net "B", 0 0, L_0x2c197b0; 1 drivers +v0x2b66cd0_0 .alias "Command", 2 0, v0x2bc67a0_0; +v0x2b66d50_0 .net "OrNorXorOut", 0 0, L_0x2c2c500; 1 drivers +v0x2b66dd0_0 .net "XorNor", 0 0, L_0x2c2bf80; 1 drivers +v0x2b66ea0_0 .net "nXor", 0 0, L_0x2c2b9f0; 1 drivers +L_0x2c2c100 .part v0x2bc78e0_0, 2, 1; +L_0x2c2c6d0 .part v0x2bc78e0_0, 0, 1; +S_0x2b66320 .scope module, "mux0" "TwoInMux" 3 83, 3 8, S_0x2b65ce0; + .timescale -9 -12; +L_0x2c2bc60/d .functor NOT 1, L_0x2c2c100, C4<0>, C4<0>, C4<0>; +L_0x2c2bc60 .delay (10000,10000,10000) L_0x2c2bc60/d; +L_0x2c2bd20/d .functor AND 1, L_0x2c2bb00, L_0x2c2bc60, C4<1>, C4<1>; +L_0x2c2bd20 .delay (20000,20000,20000) L_0x2c2bd20/d; +L_0x2c2be30/d .functor AND 1, L_0x2c2a3f0, L_0x2c2c100, C4<1>, C4<1>; +L_0x2c2be30 .delay (20000,20000,20000) L_0x2c2be30/d; +L_0x2c2bf80/d .functor OR 1, L_0x2c2bd20, L_0x2c2be30, C4<0>, C4<0>; +L_0x2c2bf80 .delay (20000,20000,20000) L_0x2c2bf80/d; +v0x2b66410_0 .net "S", 0 0, L_0x2c2c100; 1 drivers +v0x2b664d0_0 .alias "in0", 0 0, v0x2b66b60_0; +v0x2b66570_0 .alias "in1", 0 0, v0x2b669d0_0; +v0x2b66610_0 .net "nS", 0 0, L_0x2c2bc60; 1 drivers +v0x2b66690_0 .net "out0", 0 0, L_0x2c2bd20; 1 drivers +v0x2b66730_0 .net "out1", 0 0, L_0x2c2be30; 1 drivers +v0x2b66810_0 .alias "outfinal", 0 0, v0x2b66dd0_0; +S_0x2b65dd0 .scope module, "mux1" "TwoInMux" 3 84, 3 8, S_0x2b65ce0; + .timescale -9 -12; +L_0x2c2c1a0/d .functor NOT 1, L_0x2c2c6d0, C4<0>, C4<0>, C4<0>; +L_0x2c2c1a0 .delay (10000,10000,10000) L_0x2c2c1a0/d; +L_0x2c2c260/d .functor AND 1, L_0x2c2bf80, L_0x2c2c1a0, C4<1>, C4<1>; +L_0x2c2c260 .delay (20000,20000,20000) L_0x2c2c260/d; +L_0x2c2c3b0/d .functor AND 1, L_0x2c2a4e0, L_0x2c2c6d0, C4<1>, C4<1>; +L_0x2c2c3b0 .delay (20000,20000,20000) L_0x2c2c3b0/d; +L_0x2c2c500/d .functor OR 1, L_0x2c2c260, L_0x2c2c3b0, C4<0>, C4<0>; +L_0x2c2c500 .delay (20000,20000,20000) L_0x2c2c500/d; +v0x2b65ec0_0 .net "S", 0 0, L_0x2c2c6d0; 1 drivers +v0x2b65f40_0 .alias "in0", 0 0, v0x2b66dd0_0; +v0x2b65fe0_0 .alias "in1", 0 0, v0x2b66a80_0; +v0x2b66080_0 .net "nS", 0 0, L_0x2c2c1a0; 1 drivers +v0x2b66100_0 .net "out0", 0 0, L_0x2c2c260; 1 drivers +v0x2b661a0_0 .net "out1", 0 0, L_0x2c2c3b0; 1 drivers +v0x2b66280_0 .alias "outfinal", 0 0, v0x2b66d50_0; +S_0x2b647e0 .scope generate, "orbits[30]" "orbits[30]" 3 196, 3 196, S_0x2b62fd0; + .timescale -9 -12; +P_0x2b64558 .param/l "i" 3 196, +C4<011110>; +S_0x2b64910 .scope module, "attempt" "OrNorXor" 3 198, 3 64, S_0x2b647e0; + .timescale -9 -12; +L_0x2c19850/d .functor NOR 1, L_0x2c2cc20, L_0x2c2ccc0, C4<0>, C4<0>; +L_0x2c19850 .delay (10000,10000,10000) L_0x2c19850/d; +L_0x2c2b510/d .functor NOT 1, L_0x2c19850, C4<0>, C4<0>, C4<0>; +L_0x2c2b510 .delay (10000,10000,10000) L_0x2c2b510/d; +L_0x2c2b620/d .functor NAND 1, L_0x2c2cc20, L_0x2c2ccc0, C4<1>, C4<1>; +L_0x2c2b620 .delay (10000,10000,10000) L_0x2c2b620/d; +L_0x2c2cee0/d .functor NAND 1, L_0x2c2b620, L_0x2c2b510, C4<1>, C4<1>; +L_0x2c2cee0 .delay (10000,10000,10000) L_0x2c2cee0/d; +L_0x2c2cf90/d .functor NOT 1, L_0x2c2cee0, C4<0>, C4<0>, C4<0>; +L_0x2c2cf90 .delay (10000,10000,10000) L_0x2c2cf90/d; +v0x2b654c0_0 .net "A", 0 0, L_0x2c2cc20; 1 drivers +v0x2b65560_0 .net "AnandB", 0 0, L_0x2c2b620; 1 drivers +v0x2b65600_0 .net "AnorB", 0 0, L_0x2c19850; 1 drivers +v0x2b656b0_0 .net "AorB", 0 0, L_0x2c2b510; 1 drivers +v0x2b65790_0 .net "AxorB", 0 0, L_0x2c2cf90; 1 drivers +v0x2b65840_0 .net "B", 0 0, L_0x2c2ccc0; 1 drivers +v0x2b65900_0 .alias "Command", 2 0, v0x2bc67a0_0; +v0x2b65980_0 .net "OrNorXorOut", 0 0, L_0x2c2d870; 1 drivers +v0x2b65a00_0 .net "XorNor", 0 0, L_0x2c2d390; 1 drivers +v0x2b65ad0_0 .net "nXor", 0 0, L_0x2c2cee0; 1 drivers +L_0x2c2d4d0 .part v0x2bc78e0_0, 2, 1; +L_0x2c2da00 .part v0x2bc78e0_0, 0, 1; +S_0x2b64f50 .scope module, "mux0" "TwoInMux" 3 83, 3 8, S_0x2b64910; + .timescale -9 -12; +L_0x2c2d0d0/d .functor NOT 1, L_0x2c2d4d0, C4<0>, C4<0>, C4<0>; +L_0x2c2d0d0 .delay (10000,10000,10000) L_0x2c2d0d0/d; +L_0x2c2d170/d .functor AND 1, L_0x2c2cf90, L_0x2c2d0d0, C4<1>, C4<1>; +L_0x2c2d170 .delay (20000,20000,20000) L_0x2c2d170/d; +L_0x2c2d260/d .functor AND 1, L_0x2c19850, L_0x2c2d4d0, C4<1>, C4<1>; +L_0x2c2d260 .delay (20000,20000,20000) L_0x2c2d260/d; +L_0x2c2d390/d .functor OR 1, L_0x2c2d170, L_0x2c2d260, C4<0>, C4<0>; +L_0x2c2d390 .delay (20000,20000,20000) L_0x2c2d390/d; +v0x2b65040_0 .net "S", 0 0, L_0x2c2d4d0; 1 drivers +v0x2b65100_0 .alias "in0", 0 0, v0x2b65790_0; +v0x2b651a0_0 .alias "in1", 0 0, v0x2b65600_0; +v0x2b65240_0 .net "nS", 0 0, L_0x2c2d0d0; 1 drivers +v0x2b652c0_0 .net "out0", 0 0, L_0x2c2d170; 1 drivers +v0x2b65360_0 .net "out1", 0 0, L_0x2c2d260; 1 drivers +v0x2b65440_0 .alias "outfinal", 0 0, v0x2b65a00_0; +S_0x2b64a00 .scope module, "mux1" "TwoInMux" 3 84, 3 8, S_0x2b64910; + .timescale -9 -12; +L_0x2c2d570/d .functor NOT 1, L_0x2c2da00, C4<0>, C4<0>, C4<0>; +L_0x2c2d570 .delay (10000,10000,10000) L_0x2c2d570/d; +L_0x2c2d610/d .functor AND 1, L_0x2c2d390, L_0x2c2d570, C4<1>, C4<1>; +L_0x2c2d610 .delay (20000,20000,20000) L_0x2c2d610/d; +L_0x2c2d740/d .functor AND 1, L_0x2c2b510, L_0x2c2da00, C4<1>, C4<1>; +L_0x2c2d740 .delay (20000,20000,20000) L_0x2c2d740/d; +L_0x2c2d870/d .functor OR 1, L_0x2c2d610, L_0x2c2d740, C4<0>, C4<0>; +L_0x2c2d870 .delay (20000,20000,20000) L_0x2c2d870/d; +v0x2b64af0_0 .net "S", 0 0, L_0x2c2da00; 1 drivers +v0x2b64b70_0 .alias "in0", 0 0, v0x2b65a00_0; +v0x2b64c10_0 .alias "in1", 0 0, v0x2b656b0_0; +v0x2b64cb0_0 .net "nS", 0 0, L_0x2c2d570; 1 drivers +v0x2b64d30_0 .net "out0", 0 0, L_0x2c2d610; 1 drivers +v0x2b64dd0_0 .net "out1", 0 0, L_0x2c2d740; 1 drivers +v0x2b64eb0_0 .alias "outfinal", 0 0, v0x2b65980_0; +S_0x2b63450 .scope generate, "orbits[31]" "orbits[31]" 3 196, 3 196, S_0x2b62fd0; + .timescale -9 -12; +P_0x2b63138 .param/l "i" 3 196, +C4<011111>; +S_0x2b63580 .scope module, "attempt" "OrNorXor" 3 198, 3 64, S_0x2b63450; + .timescale -9 -12; +L_0x2c2cd60/d .functor NOR 1, L_0x2c2ec90, L_0x2c2db40, C4<0>, C4<0>; +L_0x2c2cd60 .delay (10000,10000,10000) L_0x2c2cd60/d; +L_0x2c2ce50/d .functor NOT 1, L_0x2c2cd60, C4<0>, C4<0>, C4<0>; +L_0x2c2ce50 .delay (10000,10000,10000) L_0x2c2ce50/d; +L_0x2c2deb0/d .functor NAND 1, L_0x2c2ec90, L_0x2c2db40, C4<1>, C4<1>; +L_0x2c2deb0 .delay (10000,10000,10000) L_0x2c2deb0/d; +L_0x2c2dfa0/d .functor NAND 1, L_0x2c2deb0, L_0x2c2ce50, C4<1>, C4<1>; +L_0x2c2dfa0 .delay (10000,10000,10000) L_0x2c2dfa0/d; +L_0x2c2e0e0/d .functor NOT 1, L_0x2c2dfa0, C4<0>, C4<0>, C4<0>; +L_0x2c2e0e0 .delay (10000,10000,10000) L_0x2c2e0e0/d; +v0x2b64150_0 .net "A", 0 0, L_0x2c2ec90; 1 drivers +v0x2b641f0_0 .net "AnandB", 0 0, L_0x2c2deb0; 1 drivers +v0x2b64290_0 .net "AnorB", 0 0, L_0x2c2cd60; 1 drivers +v0x2b64340_0 .net "AorB", 0 0, L_0x2c2ce50; 1 drivers +v0x2b64420_0 .net "AxorB", 0 0, L_0x2c2e0e0; 1 drivers +v0x2b644d0_0 .net "B", 0 0, L_0x2c2db40; 1 drivers +v0x2b64590_0 .alias "Command", 2 0, v0x2bc67a0_0; +v0x2b64610_0 .net "OrNorXorOut", 0 0, L_0x2c2e9c0; 1 drivers +v0x2b64690_0 .net "XorNor", 0 0, L_0x2c2e4e0; 1 drivers +v0x2b64760_0 .net "nXor", 0 0, L_0x2c2dfa0; 1 drivers +L_0x2c2e620 .part v0x2bc78e0_0, 2, 1; +L_0x2c2eb50 .part v0x2bc78e0_0, 0, 1; +S_0x2b63be0 .scope module, "mux0" "TwoInMux" 3 83, 3 8, S_0x2b63580; + .timescale -9 -12; +L_0x2c2e220/d .functor NOT 1, L_0x2c2e620, C4<0>, C4<0>, C4<0>; +L_0x2c2e220 .delay (10000,10000,10000) L_0x2c2e220/d; +L_0x2c2e2c0/d .functor AND 1, L_0x2c2e0e0, L_0x2c2e220, C4<1>, C4<1>; +L_0x2c2e2c0 .delay (20000,20000,20000) L_0x2c2e2c0/d; +L_0x2c2e3b0/d .functor AND 1, L_0x2c2cd60, L_0x2c2e620, C4<1>, C4<1>; +L_0x2c2e3b0 .delay (20000,20000,20000) L_0x2c2e3b0/d; +L_0x2c2e4e0/d .functor OR 1, L_0x2c2e2c0, L_0x2c2e3b0, C4<0>, C4<0>; +L_0x2c2e4e0 .delay (20000,20000,20000) L_0x2c2e4e0/d; +v0x2b63cd0_0 .net "S", 0 0, L_0x2c2e620; 1 drivers +v0x2b63d90_0 .alias "in0", 0 0, v0x2b64420_0; +v0x2b63e30_0 .alias "in1", 0 0, v0x2b64290_0; +v0x2b63ed0_0 .net "nS", 0 0, L_0x2c2e220; 1 drivers +v0x2b63f50_0 .net "out0", 0 0, L_0x2c2e2c0; 1 drivers +v0x2b63ff0_0 .net "out1", 0 0, L_0x2c2e3b0; 1 drivers +v0x2b640d0_0 .alias "outfinal", 0 0, v0x2b64690_0; +S_0x2b63670 .scope module, "mux1" "TwoInMux" 3 84, 3 8, S_0x2b63580; + .timescale -9 -12; +L_0x2c2e6c0/d .functor NOT 1, L_0x2c2eb50, C4<0>, C4<0>, C4<0>; +L_0x2c2e6c0 .delay (10000,10000,10000) L_0x2c2e6c0/d; +L_0x2c2e760/d .functor AND 1, L_0x2c2e4e0, L_0x2c2e6c0, C4<1>, C4<1>; +L_0x2c2e760 .delay (20000,20000,20000) L_0x2c2e760/d; +L_0x2c2e890/d .functor AND 1, L_0x2c2ce50, L_0x2c2eb50, C4<1>, C4<1>; +L_0x2c2e890 .delay (20000,20000,20000) L_0x2c2e890/d; +L_0x2c2e9c0/d .functor OR 1, L_0x2c2e760, L_0x2c2e890, C4<0>, C4<0>; +L_0x2c2e9c0 .delay (20000,20000,20000) L_0x2c2e9c0/d; +v0x2b63760_0 .net "S", 0 0, L_0x2c2eb50; 1 drivers +v0x2b63800_0 .alias "in0", 0 0, v0x2b64690_0; +v0x2b638a0_0 .alias "in1", 0 0, v0x2b64340_0; +v0x2b63940_0 .net "nS", 0 0, L_0x2c2e6c0; 1 drivers +v0x2b639c0_0 .net "out0", 0 0, L_0x2c2e760; 1 drivers +v0x2b63a60_0 .net "out1", 0 0, L_0x2c2e890; 1 drivers +v0x2b63b40_0 .alias "outfinal", 0 0, v0x2b64610_0; +S_0x29738d0 .scope module, "superalu" "Bitslice32" 2 147, 3 256, S_0x270e6d0; + .timescale -9 -12; +P_0x26c6208 .param/l "size" 3 273, +C4<0100000>; +L_0x2c58ef0/d .functor AND 1, L_0x2c43660, L_0x2c43700, C4<1>, C4<1>; +L_0x2c58ef0 .delay (20000,20000,20000) L_0x2c58ef0/d; +L_0x2c437f0/d .functor NOT 1, L_0x2c438e0, C4<0>, C4<0>, C4<0>; +L_0x2c437f0 .delay (10000,10000,10000) L_0x2c437f0/d; +L_0x2c43980/d .functor AND 1, L_0x2c437f0, L_0x2c437f0, C4<1>, C4<1>; +L_0x2c43980 .delay (20000,20000,20000) L_0x2c43980/d; +v0x2b60fd0_0 .alias "A", 31 0, v0x2bc6580_0; +v0x2b611c0_0 .alias "AddSubSLTSum", 31 0, v0x2bc76e0_0; +v0x2b61240_0 .alias "AllZeros", 0 0, v0x2bc7760_0; +v0x2b612c0_0 .alias "AndNandOut", 31 0, v0x2bc77e0_0; +v0x2b61370_0 .alias "B", 31 0, v0x2bc66a0_0; +RS_0x7f99c4320ec8/0/0 .resolv tri, L_0x2c30990, L_0x2c33340, L_0x2c35cb0, L_0x2c384c0; +RS_0x7f99c4320ec8/0/4 .resolv tri, L_0x2c3aef0, L_0x2c3d700, L_0x2c3fd30, L_0x2c42490; +RS_0x7f99c4320ec8/0/8 .resolv tri, L_0x2c450c0, L_0x2c47c20, L_0x2c4a7e0, L_0x2c4cf50; +RS_0x7f99c4320ec8/0/12 .resolv tri, L_0x2c4f700, L_0x2c51e30, L_0x2c545c0, L_0x2c57150; +RS_0x7f99c4320ec8/0/16 .resolv tri, L_0x2c5a110, L_0x2c5c880, L_0x2c5e350, L_0x2c60810; +RS_0x7f99c4320ec8/0/20 .resolv tri, L_0x2c63ee0, L_0x2c66650, L_0x2c67f00, L_0x2c6a680; +RS_0x7f99c4320ec8/0/24 .resolv tri, L_0x2c6cde0, L_0x2be19c0, L_0x2c736c0, L_0x2c75e70; +RS_0x7f99c4320ec8/0/28 .resolv tri, L_0x2c78950, L_0x2c7af00, L_0x2c7d710, L_0x2ce9150; +RS_0x7f99c4320ec8/1/0 .resolv tri, RS_0x7f99c4320ec8/0/0, RS_0x7f99c4320ec8/0/4, RS_0x7f99c4320ec8/0/8, RS_0x7f99c4320ec8/0/12; +RS_0x7f99c4320ec8/1/4 .resolv tri, RS_0x7f99c4320ec8/0/16, RS_0x7f99c4320ec8/0/20, RS_0x7f99c4320ec8/0/24, RS_0x7f99c4320ec8/0/28; +RS_0x7f99c4320ec8 .resolv tri, RS_0x7f99c4320ec8/1/0, RS_0x7f99c4320ec8/1/4, C4, C4; +v0x2b613f0_0 .net8 "Cmd0Start", 31 0, RS_0x7f99c4320ec8; 32 drivers +RS_0x7f99c4320ef8/0/0 .resolv tri, L_0x2c31870, L_0x2c34200, L_0x2c36b60, L_0x2c39350; +RS_0x7f99c4320ef8/0/4 .resolv tri, L_0x2c3bda0, L_0x2c3e590, L_0x2c40ba0, L_0x2c43350; +RS_0x7f99c4320ef8/0/8 .resolv tri, L_0x2c46340, L_0x2c48ac0, L_0x2c4b660, L_0x2c4dde0; +RS_0x7f99c4320ef8/0/12 .resolv tri, L_0x2c50590, L_0x2c52cc0, L_0x2c55450, L_0x2c57fb0; +RS_0x7f99c4320ef8/0/16 .resolv tri, L_0x2c5af80, L_0x2c5d6e0, L_0x2c5fe80, L_0x2c61820; +RS_0x7f99c4320ef8/0/20 .resolv tri, L_0x2c63660, L_0x2c67500, L_0x2c69cf0, L_0x2c6c470; +RS_0x7f99c4320ef8/0/24 .resolv tri, L_0x2be2160, L_0x2c72140, L_0x2c749a0, L_0x2c76f50; +RS_0x7f99c4320ef8/0/28 .resolv tri, L_0x2c79760, L_0x2c7bf20, L_0x2c45f50, L_0x2c83420; +RS_0x7f99c4320ef8/1/0 .resolv tri, RS_0x7f99c4320ef8/0/0, RS_0x7f99c4320ef8/0/4, RS_0x7f99c4320ef8/0/8, RS_0x7f99c4320ef8/0/12; +RS_0x7f99c4320ef8/1/4 .resolv tri, RS_0x7f99c4320ef8/0/16, RS_0x7f99c4320ef8/0/20, RS_0x7f99c4320ef8/0/24, RS_0x7f99c4320ef8/0/28; +RS_0x7f99c4320ef8 .resolv tri, RS_0x7f99c4320ef8/1/0, RS_0x7f99c4320ef8/1/4, C4, C4; +v0x2b61470_0 .net8 "Cmd1Start", 31 0, RS_0x7f99c4320ef8; 32 drivers +v0x2b614f0_0 .alias "Command", 2 0, v0x2bc67a0_0; +v0x2b61570_0 .alias "OneBitFinalOut", 31 0, v0x2bc7960_0; +v0x2b61610_0 .alias "OrNorXorOut", 31 0, v0x2bc79e0_0; +v0x2b61690_0 .alias "SLTflag", 0 0, v0x2bc7a60_0; +v0x2b61740_0 .alias "ZeroFlag", 31 0, v0x2bc7ae0_0; +v0x2b617c0_0 .net *"_s121", 0 0, L_0x2c3c500; 1 drivers +v0x2b61840_0 .net *"_s146", 0 0, L_0x2c3ea80; 1 drivers +v0x2b61960_0 .net *"_s171", 0 0, L_0x2c41410; 1 drivers +v0x2b61a00_0 .net *"_s196", 0 0, L_0x2c3a2c0; 1 drivers +v0x2b618c0_0 .net *"_s21", 0 0, L_0x2c32930; 1 drivers +v0x2b61b50_0 .net *"_s221", 0 0, L_0x2c46660; 1 drivers +v0x2b61c70_0 .net *"_s246", 0 0, L_0x2c48e70; 1 drivers +v0x2b61cf0_0 .net *"_s271", 0 0, L_0x2c4b980; 1 drivers +v0x2b61bd0_0 .net *"_s296", 0 0, L_0x2c4e2d0; 1 drivers +v0x2b61e20_0 .net *"_s321", 0 0, L_0x2c508b0; 1 drivers +v0x2b61d70_0 .net *"_s346", 0 0, L_0x2c53020; 1 drivers +v0x2b61f60_0 .net *"_s371", 0 0, L_0x2c55070; 1 drivers +v0x2b61ec0_0 .net *"_s396", 0 0, L_0x2c44580; 1 drivers +v0x2b620b0_0 .net *"_s421", 0 0, L_0x2c5b0c0; 1 drivers +v0x2b62000_0 .net *"_s446", 0 0, L_0x2c5d8b0; 1 drivers +v0x2b62210_0 .net *"_s46", 0 0, L_0x2c34850; 1 drivers +v0x2b62150_0 .net *"_s471", 0 0, L_0x2c60c30; 1 drivers +v0x2b62380_0 .net *"_s496", 0 0, L_0x2c62600; 1 drivers +v0x2b62290_0 .net *"_s521", 0 0, L_0x2c64b40; 1 drivers +v0x2b62500_0 .net *"_s546", 0 0, L_0x2c672d0; 1 drivers +v0x2b62400_0 .net *"_s571", 0 0, L_0x2c692d0; 1 drivers +v0x2b62690_0 .net *"_s596", 0 0, L_0x2c6b960; 1 drivers +v0x2b62580_0 .net *"_s621", 0 0, L_0x2be0ef0; 1 drivers +v0x2b62830_0 .net *"_s646", 0 0, L_0x2c72bf0; 1 drivers +v0x2b62710_0 .net *"_s671", 0 0, L_0x2c753e0; 1 drivers +v0x2b627b0_0 .net *"_s696", 0 0, L_0x2c77e50; 1 drivers +v0x2b629f0_0 .net *"_s71", 0 0, L_0x2c37800; 1 drivers +v0x2b62a70_0 .net *"_s721", 0 0, L_0x2c7a4a0; 1 drivers +v0x2b628b0_0 .net *"_s746", 0 0, L_0x2c7cc40; 1 drivers +v0x2b62950_0 .net *"_s771", 0 0, L_0x2c49a50; 1 drivers +v0x2b62c50_0 .net *"_s811", 0 0, L_0x2c58ef0; 1 drivers +v0x2b62cd0_0 .net *"_s814", 0 0, L_0x2c43660; 1 drivers +v0x2b62af0_0 .net *"_s816", 0 0, L_0x2c43700; 1 drivers +v0x2b62b90_0 .net *"_s818", 0 0, L_0x2c438e0; 1 drivers +v0x2b62ed0_0 .net *"_s96", 0 0, L_0x2c34f80; 1 drivers +v0x2b62f50_0 .alias "carryin", 31 0, v0x2bc71d0_0; +v0x2b62d80_0 .alias "carryout", 0 0, v0x2bc7be0_0; +v0x2b62e30_0 .alias "overflow", 0 0, v0x2bc7c60_0; +v0x2b631a0_0 .alias "subtract", 31 0, v0x2bc7ce0_0; +v0x2b63220_0 .net "yeszero", 0 0, L_0x2c437f0; 1 drivers +L_0x2c30990 .part/pv L_0x2c30780, 1, 1, 32; +L_0x2c30a30 .part v0x2bc78e0_0, 0, 1; +L_0x2c30b60 .part v0x2bc78e0_0, 1, 1; +L_0x2c30c90 .part RS_0x7f99c4320aa8, 1, 1; +L_0x2c30d30 .part RS_0x7f99c4320aa8, 1, 1; +L_0x2c30dd0 .part RS_0x7f99c4316848, 1, 1; +L_0x2c30f00 .part RS_0x7f99c4320aa8, 1, 1; +L_0x2c31870 .part/pv L_0x2c31630, 1, 1, 32; +L_0x2c31960 .part v0x2bc78e0_0, 0, 1; +L_0x2c31a90 .part v0x2bc78e0_0, 1, 1; +L_0x2c31c20 .part RS_0x7f99c4319e78, 1, 1; +L_0x2c31cc0 .part RS_0x7f99c4319e78, 1, 1; +L_0x2c31dd0 .part RS_0x7f99c4316848, 1, 1; +L_0x2c31e70 .part RS_0x7f99c4316848, 1, 1; +L_0x2c32350 .part/pv L_0x2c32210, 1, 1, 32; +L_0x2c32440 .part v0x2bc78e0_0, 2, 1; +L_0x2c32570 .part RS_0x7f99c4320ec8, 1, 1; +L_0x2c326b0 .part RS_0x7f99c4320ef8, 1, 1; +L_0x2c32890 .part/pv L_0x2c32930, 1, 1, 32; +L_0x2c32a30 .part RS_0x7f99c4320f58, 0, 1; +L_0x2c327f0 .part RS_0x7f99c4320f28, 1, 1; +L_0x2c33340 .part/pv L_0x2c33160, 2, 1, 32; +L_0x2c32ad0 .part v0x2bc78e0_0, 0, 1; +L_0x2c33530 .part v0x2bc78e0_0, 1, 1; +L_0x2c333e0 .part RS_0x7f99c4320aa8, 2, 1; +L_0x2c33730 .part RS_0x7f99c4320aa8, 2, 1; +L_0x2c33660 .part RS_0x7f99c4316848, 2, 1; +L_0x2c33900 .part RS_0x7f99c4320aa8, 2, 1; +L_0x2c34200 .part/pv L_0x2c33ff0, 2, 1, 32; +L_0x2c342a0 .part v0x2bc78e0_0, 0, 1; +L_0x2c339f0 .part v0x2bc78e0_0, 1, 1; +L_0x2c34560 .part RS_0x7f99c4319e78, 2, 1; +L_0x2c343d0 .part RS_0x7f99c4319e78, 2, 1; +L_0x2c34710 .part RS_0x7f99c4316848, 2, 1; +L_0x2c34600 .part RS_0x7f99c4316848, 2, 1; +L_0x2c34c80 .part/pv L_0x2c34b40, 2, 1, 32; +L_0x2c347b0 .part v0x2bc78e0_0, 2, 1; +L_0x2c34ee0 .part RS_0x7f99c4320ec8, 2, 1; +L_0x2c34db0 .part RS_0x7f99c4320ef8, 2, 1; +L_0x2c35150 .part/pv L_0x2c34850, 2, 1, 32; +L_0x2c35050 .part RS_0x7f99c4320f58, 1, 1; +L_0x2c353d0 .part RS_0x7f99c4320f28, 2, 1; +L_0x2c35cb0 .part/pv L_0x2c35aa0, 3, 1, 32; +L_0x2c35d50 .part v0x2bc78e0_0, 0, 1; +L_0x2c35470 .part v0x2bc78e0_0, 1, 1; +L_0x2c35ff0 .part RS_0x7f99c4320aa8, 3, 1; +L_0x2c35e80 .part RS_0x7f99c4320aa8, 3, 1; +L_0x2c35f20 .part RS_0x7f99c4316848, 3, 1; +L_0x2c36090 .part RS_0x7f99c4320aa8, 3, 1; +L_0x2c36b60 .part/pv L_0x2c36950, 3, 1, 32; +L_0x2c36260 .part v0x2bc78e0_0, 0, 1; +L_0x2c36da0 .part v0x2bc78e0_0, 1, 1; +L_0x2c36c00 .part RS_0x7f99c4319e78, 3, 1; +L_0x2c36ca0 .part RS_0x7f99c4319e78, 3, 1; +L_0x2c37090 .part RS_0x7f99c4316848, 3, 1; +L_0x2c37130 .part RS_0x7f99c4316848, 3, 1; +L_0x2c37620 .part/pv L_0x2c374e0, 3, 1, 32; +L_0x2c376c0 .part v0x2bc78e0_0, 2, 1; +L_0x2c371d0 .part RS_0x7f99c4320ec8, 3, 1; +L_0x2c372c0 .part RS_0x7f99c4320ef8, 3, 1; +L_0x2c37760 .part/pv L_0x2c37800, 3, 1, 32; +L_0x2c37b80 .part RS_0x7f99c4320f58, 2, 1; +L_0x2c37990 .part RS_0x7f99c4320f28, 3, 1; +L_0x2c384c0 .part/pv L_0x2c382b0, 4, 1, 32; +L_0x2c37c20 .part v0x2bc78e0_0, 0, 1; +L_0x2c37d50 .part v0x2bc78e0_0, 1, 1; +L_0x2c38560 .part RS_0x7f99c4320aa8, 4, 1; +L_0x2c38600 .part RS_0x7f99c4320aa8, 4, 1; +L_0x2c386a0 .part RS_0x7f99c4316848, 4, 1; +L_0x2c38a80 .part RS_0x7f99c4320aa8, 4, 1; +L_0x2c39350 .part/pv L_0x2c39140, 4, 1, 32; +L_0x2c393f0 .part v0x2bc78e0_0, 0, 1; +L_0x2c38b70 .part v0x2bc78e0_0, 1, 1; +L_0x2c38ca0 .part RS_0x7f99c4319e78, 4, 1; +L_0x2c39780 .part RS_0x7f99c4319e78, 4, 1; +L_0x2c39820 .part RS_0x7f99c4316848, 4, 1; +L_0x2c39520 .part RS_0x7f99c4316848, 4, 1; +L_0x2c39df0 .part/pv L_0x2c39cb0, 4, 1, 32; +L_0x2c398c0 .part v0x2bc78e0_0, 2, 1; +L_0x2c39960 .part RS_0x7f99c4320ec8, 4, 1; +L_0x2c39a50 .part RS_0x7f99c4320ef8, 4, 1; +L_0x2c3a0b0 .part/pv L_0x2c34f80, 4, 1, 32; +L_0x2c3a150 .part RS_0x7f99c4320f58, 3, 1; +L_0x2c3a330 .part RS_0x7f99c4320f28, 4, 1; +L_0x2c3aef0 .part/pv L_0x2c3ace0, 5, 1, 32; +L_0x2c3af90 .part v0x2bc78e0_0, 0, 1; +L_0x2c3a6d0 .part v0x2bc78e0_0, 1, 1; +L_0x2c3a800 .part RS_0x7f99c4320aa8, 5, 1; +L_0x2c3a8a0 .part RS_0x7f99c4320aa8, 5, 1; +L_0x2c3b390 .part RS_0x7f99c4316848, 5, 1; +L_0x2c3b0c0 .part RS_0x7f99c4320aa8, 5, 1; +L_0x2c3bda0 .part/pv L_0x2c3bb90, 5, 1, 32; +L_0x2c3b480 .part v0x2bc78e0_0, 0, 1; +L_0x2c3b5b0 .part v0x2bc78e0_0, 1, 1; +L_0x2c3c140 .part RS_0x7f99c4319e78, 5, 1; +L_0x2c3c1e0 .part RS_0x7f99c4319e78, 5, 1; +L_0x2c3be40 .part RS_0x7f99c4316848, 5, 1; +L_0x2c3bf30 .part RS_0x7f99c4316848, 5, 1; +L_0x2c3c860 .part/pv L_0x2c3c720, 5, 1, 32; +L_0x2c3c900 .part v0x2bc78e0_0, 2, 1; +L_0x2c3c280 .part RS_0x7f99c4320ec8, 5, 1; +L_0x2c3c370 .part RS_0x7f99c4320ef8, 5, 1; +L_0x2c3c460 .part/pv L_0x2c3c500, 5, 1, 32; +L_0x2c3cd80 .part RS_0x7f99c4320f58, 4, 1; +L_0x2c3c9a0 .part RS_0x7f99c4320f28, 5, 1; +L_0x2c3d700 .part/pv L_0x2c3d4f0, 6, 1, 32; +L_0x2c3ce20 .part v0x2bc78e0_0, 0, 1; +L_0x2c3cf50 .part v0x2bc78e0_0, 1, 1; +L_0x2c3d080 .part RS_0x7f99c4320aa8, 6, 1; +L_0x2c3db10 .part RS_0x7f99c4320aa8, 6, 1; +L_0x2c3d7a0 .part RS_0x7f99c4316848, 6, 1; +L_0x2c3d840 .part RS_0x7f99c4320aa8, 6, 1; +L_0x2c3e590 .part/pv L_0x2c3e380, 6, 1, 32; +L_0x2c3e630 .part v0x2bc78e0_0, 0, 1; +L_0x2c3dbb0 .part v0x2bc78e0_0, 1, 1; +L_0x2c3dce0 .part RS_0x7f99c4319e78, 6, 1; +L_0x2c3dd80 .part RS_0x7f99c4319e78, 6, 1; +L_0x2c3de20 .part RS_0x7f99c4316848, 6, 1; +L_0x2c3eb20 .part RS_0x7f99c4316848, 6, 1; +L_0x2c3f020 .part/pv L_0x2c3eee0, 6, 1, 32; +L_0x2c3e760 .part v0x2bc78e0_0, 2, 1; +L_0x2c3e800 .part RS_0x7f99c4320ec8, 6, 1; +L_0x2c3e8f0 .part RS_0x7f99c4320ef8, 6, 1; +L_0x2c3e9e0 .part/pv L_0x2c3ea80, 6, 1, 32; +L_0x2c3f550 .part RS_0x7f99c4320f58, 5, 1; +L_0x2c3f5f0 .part RS_0x7f99c4320f28, 6, 1; +L_0x2c3fd30 .part/pv L_0x2c3fb20, 7, 1, 32; +L_0x2c3fdd0 .part v0x2bc78e0_0, 0, 1; +L_0x2c3f6e0 .part v0x2bc78e0_0, 1, 1; +L_0x2c3f810 .part RS_0x7f99c4320aa8, 7, 1; +L_0x2c3f8b0 .part RS_0x7f99c4320aa8, 7, 1; +L_0x2c3f950 .part RS_0x7f99c4316848, 7, 1; +L_0x2c3fa40 .part RS_0x7f99c4320aa8, 7, 1; +L_0x2c40ba0 .part/pv L_0x2c40990, 7, 1, 32; +L_0x2c3ff00 .part v0x2bc78e0_0, 0, 1; +L_0x2c40030 .part v0x2bc78e0_0, 1, 1; +L_0x2c40160 .part RS_0x7f99c4319e78, 7, 1; +L_0x2c40200 .part RS_0x7f99c4319e78, 7, 1; +L_0x2c410a0 .part RS_0x7f99c4316848, 7, 1; +L_0x2c41140 .part RS_0x7f99c4316848, 7, 1; +L_0x2c40fb0 .part/pv L_0x2c40e70, 7, 1, 32; +L_0x2c41650 .part v0x2bc78e0_0, 2, 1; +L_0x2c411e0 .part RS_0x7f99c4320ec8, 7, 1; +L_0x2c41280 .part RS_0x7f99c4320ef8, 7, 1; +L_0x2c41370 .part/pv L_0x2c41410, 7, 1, 32; +L_0x2c41550 .part RS_0x7f99c4320f58, 6, 1; +L_0x2c41b90 .part RS_0x7f99c4320f28, 7, 1; +L_0x2c42490 .part/pv L_0x2c42280, 8, 1, 32; +L_0x2c416f0 .part v0x2bc78e0_0, 0, 1; +L_0x2c41820 .part v0x2bc78e0_0, 1, 1; +L_0x2c41950 .part RS_0x7f99c4320aa8, 8, 1; +L_0x2c419f0 .part RS_0x7f99c4320aa8, 8, 1; +L_0x2c41a90 .part RS_0x7f99c4316848, 8, 1; +L_0x2c42a00 .part RS_0x7f99c4320aa8, 8, 1; +L_0x2c43350 .part/pv L_0x2c43140, 8, 1, 32; +L_0x2c433f0 .part v0x2bc78e0_0, 0, 1; +L_0x2c42af0 .part v0x2bc78e0_0, 1, 1; +L_0x2c42c20 .part RS_0x7f99c4319e78, 8, 1; +L_0x2c42cc0 .part RS_0x7f99c4319e78, 8, 1; +L_0x2c42d60 .part RS_0x7f99c4316848, 8, 1; +L_0x2c42e50 .part RS_0x7f99c4316848, 8, 1; +L_0x2c43da0 .part/pv L_0x2c43c60, 8, 1, 32; +L_0x2c39e90 .part v0x2bc78e0_0, 2, 1; +L_0x2c43520 .part RS_0x7f99c4320ec8, 8, 1; +L_0x2c3a220 .part RS_0x7f99c4320ef8, 8, 1; +L_0x2c39f80 .part/pv L_0x2c3a2c0, 8, 1, 32; +L_0x2c3a610 .part RS_0x7f99c4320f58, 7, 1; +L_0x2c44050 .part RS_0x7f99c4320f28, 8, 1; +L_0x2c450c0 .part/pv L_0x2c44eb0, 9, 1, 32; +L_0x2c45160 .part v0x2bc78e0_0, 0, 1; +L_0x2c44790 .part v0x2bc78e0_0, 1, 1; +L_0x2c448c0 .part RS_0x7f99c4320aa8, 9, 1; +L_0x2c44960 .part RS_0x7f99c4320aa8, 9, 1; +L_0x2c44a00 .part RS_0x7f99c4316848, 9, 1; +L_0x2c44af0 .part RS_0x7f99c4320aa8, 9, 1; +L_0x2c46340 .part/pv L_0x2c46130, 9, 1, 32; +L_0x2c45290 .part v0x2bc78e0_0, 0, 1; +L_0x2c453c0 .part v0x2bc78e0_0, 1, 1; +L_0x2c454f0 .part RS_0x7f99c4319e78, 9, 1; +L_0x2c45590 .part RS_0x7f99c4319e78, 9, 1; +L_0x2c45630 .part RS_0x7f99c4316848, 9, 1; +L_0x2c45720 .part RS_0x7f99c4316848, 9, 1; +L_0x2c46d50 .part/pv L_0x2c46c10, 9, 1, 32; +L_0x2c46df0 .part v0x2bc78e0_0, 2, 1; +L_0x2c463e0 .part RS_0x7f99c4320ec8, 9, 1; +L_0x2c464d0 .part RS_0x7f99c4320ef8, 9, 1; +L_0x2c465c0 .part/pv L_0x2c46660, 9, 1, 32; +L_0x2c467a0 .part RS_0x7f99c4320f58, 8, 1; +L_0x2c46840 .part RS_0x7f99c4320f28, 9, 1; +L_0x2c47c20 .part/pv L_0x2c47a10, 10, 1, 32; +L_0x2c46e90 .part v0x2bc78e0_0, 0, 1; +L_0x2c46fc0 .part v0x2bc78e0_0, 1, 1; +L_0x2c470f0 .part RS_0x7f99c4320aa8, 10, 1; +L_0x2c47190 .part RS_0x7f99c4320aa8, 10, 1; +L_0x2c47230 .part RS_0x7f99c4316848, 10, 1; +L_0x2c47320 .part RS_0x7f99c4320aa8, 10, 1; +L_0x2c48ac0 .part/pv L_0x2c488b0, 10, 1, 32; +L_0x2c48b60 .part v0x2bc78e0_0, 0, 1; +L_0x2c47cc0 .part v0x2bc78e0_0, 1, 1; +L_0x2c47df0 .part RS_0x7f99c4319e78, 10, 1; +L_0x2c47e90 .part RS_0x7f99c4319e78, 10, 1; +L_0x2c47f30 .part RS_0x7f99c4316848, 10, 1; +L_0x2c48020 .part RS_0x7f99c4316848, 10, 1; +L_0x2c2ca00 .part/pv L_0x2c2c8c0, 10, 1, 32; +L_0x2c2caa0 .part v0x2bc78e0_0, 2, 1; +L_0x2c2cb40 .part RS_0x7f99c4320ec8, 10, 1; +L_0x2c48ce0 .part RS_0x7f99c4320ef8, 10, 1; +L_0x2c48dd0 .part/pv L_0x2c48e70, 10, 1, 32; +L_0x2c48f70 .part RS_0x7f99c4320f58, 9, 1; +L_0x2c49010 .part RS_0x7f99c4320f28, 10, 1; +L_0x2c4a7e0 .part/pv L_0x2c4a5d0, 11, 1, 32; +L_0x2c4a880 .part v0x2bc78e0_0, 0, 1; +L_0x2c49af0 .part v0x2bc78e0_0, 1, 1; +L_0x2c49c20 .part RS_0x7f99c4320aa8, 11, 1; +L_0x2c49cc0 .part RS_0x7f99c4320aa8, 11, 1; +L_0x2c49d60 .part RS_0x7f99c4316848, 11, 1; +L_0x2c49e50 .part RS_0x7f99c4320aa8, 11, 1; +L_0x2c4b660 .part/pv L_0x2c4b450, 11, 1, 32; +L_0x2c4a9b0 .part v0x2bc78e0_0, 0, 1; +L_0x2c4aae0 .part v0x2bc78e0_0, 1, 1; +L_0x2c4ac10 .part RS_0x7f99c4319e78, 11, 1; +L_0x2c4acb0 .part RS_0x7f99c4319e78, 11, 1; +L_0x2c4ad50 .part RS_0x7f99c4316848, 11, 1; +L_0x2c4ae40 .part RS_0x7f99c4316848, 11, 1; +L_0x2c4c090 .part/pv L_0x2c4bf50, 11, 1, 32; +L_0x2c4c130 .part v0x2bc78e0_0, 2, 1; +L_0x2c4b700 .part RS_0x7f99c4320ec8, 11, 1; +L_0x2c4b7f0 .part RS_0x7f99c4320ef8, 11, 1; +L_0x2c4b8e0 .part/pv L_0x2c4b980, 11, 1, 32; +L_0x2c4bac0 .part RS_0x7f99c4320f58, 10, 1; +L_0x2c4bb60 .part RS_0x7f99c4320f28, 11, 1; +L_0x2c4cf50 .part/pv L_0x2c4cd40, 12, 1, 32; +L_0x2c4c1d0 .part v0x2bc78e0_0, 0, 1; +L_0x2c4c300 .part v0x2bc78e0_0, 1, 1; +L_0x2c4c430 .part RS_0x7f99c4320aa8, 12, 1; +L_0x2c4c4d0 .part RS_0x7f99c4320aa8, 12, 1; +L_0x2c4c570 .part RS_0x7f99c4316848, 12, 1; +L_0x2c4c660 .part RS_0x7f99c4320aa8, 12, 1; +L_0x2c4dde0 .part/pv L_0x2c4dbd0, 12, 1, 32; +L_0x2c4de80 .part v0x2bc78e0_0, 0, 1; +L_0x2c4cff0 .part v0x2bc78e0_0, 1, 1; +L_0x2c4d120 .part RS_0x7f99c4319e78, 12, 1; +L_0x2c4d1c0 .part RS_0x7f99c4319e78, 12, 1; +L_0x2c4d260 .part RS_0x7f99c4316848, 12, 1; +L_0x2c4d350 .part RS_0x7f99c4316848, 12, 1; +L_0x2c4e800 .part/pv L_0x2c4d6d0, 12, 1, 32; +L_0x2c4dfb0 .part v0x2bc78e0_0, 2, 1; +L_0x2c4e050 .part RS_0x7f99c4320ec8, 12, 1; +L_0x2c4e140 .part RS_0x7f99c4320ef8, 12, 1; +L_0x2c4e230 .part/pv L_0x2c4e2d0, 12, 1, 32; +L_0x2c4e410 .part RS_0x7f99c4320f58, 11, 1; +L_0x2c4e4b0 .part RS_0x7f99c4320f28, 12, 1; +L_0x2c4f700 .part/pv L_0x2c4f4f0, 13, 1, 32; +L_0x2c4f7a0 .part v0x2bc78e0_0, 0, 1; +L_0x2c4e8a0 .part v0x2bc78e0_0, 1, 1; +L_0x2c4e9d0 .part RS_0x7f99c4320aa8, 13, 1; +L_0x2c4ea70 .part RS_0x7f99c4320aa8, 13, 1; +L_0x2c4eb10 .part RS_0x7f99c4316848, 13, 1; +L_0x2c4ec00 .part RS_0x7f99c4320aa8, 13, 1; +L_0x2c50590 .part/pv L_0x2c50380, 13, 1, 32; +L_0x2c4f8d0 .part v0x2bc78e0_0, 0, 1; +L_0x2c4fa00 .part v0x2bc78e0_0, 1, 1; +L_0x2c4fb30 .part RS_0x7f99c4319e78, 13, 1; +L_0x2c4fbd0 .part RS_0x7f99c4319e78, 13, 1; +L_0x2c4fc70 .part RS_0x7f99c4316848, 13, 1; +L_0x2c4fd60 .part RS_0x7f99c4316848, 13, 1; +L_0x2c50fd0 .part/pv L_0x2c50e90, 13, 1, 32; +L_0x2c51070 .part v0x2bc78e0_0, 2, 1; +L_0x2c50630 .part RS_0x7f99c4320ec8, 13, 1; +L_0x2c50720 .part RS_0x7f99c4320ef8, 13, 1; +L_0x2c50810 .part/pv L_0x2c508b0, 13, 1, 32; +L_0x2c509f0 .part RS_0x7f99c4320f58, 12, 1; +L_0x2c50a90 .part RS_0x7f99c4320f28, 13, 1; +L_0x2c51e30 .part/pv L_0x2c51c20, 14, 1, 32; +L_0x2c51110 .part v0x2bc78e0_0, 0, 1; +L_0x2c51240 .part v0x2bc78e0_0, 1, 1; +L_0x2c51370 .part RS_0x7f99c4320aa8, 14, 1; +L_0x2c51410 .part RS_0x7f99c4320aa8, 14, 1; +L_0x2c514b0 .part RS_0x7f99c4316848, 14, 1; +L_0x2c515a0 .part RS_0x7f99c4320aa8, 14, 1; +L_0x2c52cc0 .part/pv L_0x2c52ab0, 14, 1, 32; +L_0x2c52d60 .part v0x2bc78e0_0, 0, 1; +L_0x2c51ed0 .part v0x2bc78e0_0, 1, 1; +L_0x2c52000 .part RS_0x7f99c4319e78, 14, 1; +L_0x2c520a0 .part RS_0x7f99c4319e78, 14, 1; +L_0x2c52140 .part RS_0x7f99c4316848, 14, 1; +L_0x2c52230 .part RS_0x7f99c4316848, 14, 1; +L_0x2c526f0 .part/pv L_0x2c525b0, 14, 1, 32; +L_0x2c537a0 .part v0x2bc78e0_0, 2, 1; +L_0x2c53840 .part RS_0x7f99c4320ec8, 14, 1; +L_0x2c52e90 .part RS_0x7f99c4320ef8, 14, 1; +L_0x2c52f80 .part/pv L_0x2c53020, 14, 1, 32; +L_0x2c53160 .part RS_0x7f99c4320f58, 13, 1; +L_0x2c53200 .part RS_0x7f99c4320f28, 14, 1; +L_0x2c545c0 .part/pv L_0x2c543b0, 15, 1, 32; +L_0x2c54660 .part v0x2bc78e0_0, 0, 1; +L_0x2c53930 .part v0x2bc78e0_0, 1, 1; +L_0x2c53a60 .part RS_0x7f99c4320aa8, 15, 1; +L_0x2c53b00 .part RS_0x7f99c4320aa8, 15, 1; +L_0x2c53ba0 .part RS_0x7f99c4316848, 15, 1; +L_0x2c53c90 .part RS_0x7f99c4320aa8, 15, 1; +L_0x2c55450 .part/pv L_0x2c55240, 15, 1, 32; +L_0x2c54790 .part v0x2bc78e0_0, 0, 1; +L_0x2c548c0 .part v0x2bc78e0_0, 1, 1; +L_0x2c549f0 .part RS_0x7f99c4319e78, 15, 1; +L_0x2c082f0 .part RS_0x7f99c4319e78, 15, 1; +L_0x2c08390 .part RS_0x7f99c4316848, 15, 1; +L_0x2c08480 .part RS_0x7f99c4316848, 15, 1; +L_0x2c54cb0 .part/pv L_0x2c54b70, 15, 1, 32; +L_0x2c54d50 .part v0x2bc78e0_0, 2, 1; +L_0x2c54df0 .part RS_0x7f99c4320ec8, 15, 1; +L_0x2c54ee0 .part RS_0x7f99c4320ef8, 15, 1; +L_0x2c54fd0 .part/pv L_0x2c55070, 15, 1, 32; +L_0x2c555d0 .part RS_0x7f99c4320f58, 14, 1; +L_0x2c55670 .part RS_0x7f99c4320f28, 15, 1; +L_0x2c57150 .part/pv L_0x2c55d20, 16, 1, 32; +L_0x2c56690 .part v0x2bc78e0_0, 0, 1; +L_0x2c567c0 .part v0x2bc78e0_0, 1, 1; +L_0x2c568f0 .part RS_0x7f99c4320aa8, 16, 1; +L_0x2c56990 .part RS_0x7f99c4320aa8, 16, 1; +L_0x2c56a30 .part RS_0x7f99c4316848, 16, 1; +L_0x2c56b20 .part RS_0x7f99c4320aa8, 16, 1; +L_0x2c57fb0 .part/pv L_0x2c57da0, 16, 1, 32; +L_0x2c58050 .part v0x2bc78e0_0, 0, 1; +L_0x2c571f0 .part v0x2bc78e0_0, 1, 1; +L_0x2c57320 .part RS_0x7f99c4319e78, 16, 1; +L_0x2c573c0 .part RS_0x7f99c4319e78, 16, 1; +L_0x2c57460 .part RS_0x7f99c4316848, 16, 1; +L_0x2c57550 .part RS_0x7f99c4316848, 16, 1; +L_0x2c57a10 .part/pv L_0x2c578d0, 16, 1, 32; +L_0x2c57ab0 .part v0x2bc78e0_0, 2, 1; +L_0x2c57b50 .part RS_0x7f99c4320ec8, 16, 1; +L_0x2c43e90 .part RS_0x7f99c4320ef8, 16, 1; +L_0x2c43f80 .part/pv L_0x2c44580, 16, 1, 32; +L_0x2c446c0 .part RS_0x7f99c4320f58, 15, 1; +L_0x2c589a0 .part RS_0x7f99c4320f28, 16, 1; +L_0x2c5a110 .part/pv L_0x2c59f00, 17, 1, 32; +L_0x2c5a1b0 .part v0x2bc78e0_0, 0, 1; +L_0x2c58fe0 .part v0x2bc78e0_0, 1, 1; +L_0x2c59110 .part RS_0x7f99c4320aa8, 17, 1; +L_0x2c591b0 .part RS_0x7f99c4320aa8, 17, 1; +L_0x2c59250 .part RS_0x7f99c4316848, 17, 1; +L_0x2c59340 .part RS_0x7f99c4320aa8, 17, 1; +L_0x2c5af80 .part/pv L_0x2c5ada0, 17, 1, 32; +L_0x2c5a2e0 .part v0x2bc78e0_0, 0, 1; +L_0x2c5a410 .part v0x2bc78e0_0, 1, 1; +L_0x2c5a540 .part RS_0x7f99c4319e78, 17, 1; +L_0x2c5a5e0 .part RS_0x7f99c4319e78, 17, 1; +L_0x2c5a680 .part RS_0x7f99c4316848, 17, 1; +L_0x2c5a770 .part RS_0x7f99c4316848, 17, 1; +L_0x2c5ac10 .part/pv L_0x2c5aad0, 17, 1, 32; +L_0x2c5acb0 .part v0x2bc78e0_0, 2, 1; +L_0x2c5bb30 .part RS_0x7f99c4320ec8, 17, 1; +L_0x2c5bbd0 .part RS_0x7f99c4320ef8, 17, 1; +L_0x2c5b020 .part/pv L_0x2c5b0c0, 17, 1, 32; +L_0x2c5b200 .part RS_0x7f99c4320f58, 16, 1; +L_0x2c5b2a0 .part RS_0x7f99c4320f28, 17, 1; +L_0x2c5c880 .part/pv L_0x2c5b980, 18, 1, 32; +L_0x2c5bcc0 .part v0x2bc78e0_0, 0, 1; +L_0x2c5bdf0 .part v0x2bc78e0_0, 1, 1; +L_0x2c5bf20 .part RS_0x7f99c4320aa8, 18, 1; +L_0x2c5bfc0 .part RS_0x7f99c4320aa8, 18, 1; +L_0x2c5c060 .part RS_0x7f99c4316848, 18, 1; +L_0x2c5c150 .part RS_0x7f99c4320aa8, 18, 1; +L_0x2c5d6e0 .part/pv L_0x2c5d4d0, 18, 1, 32; +L_0x2c5d780 .part v0x2bc78e0_0, 0, 1; +L_0x2c5c920 .part v0x2bc78e0_0, 1, 1; +L_0x2c5ca50 .part RS_0x7f99c4319e78, 18, 1; +L_0x2c5caf0 .part RS_0x7f99c4319e78, 18, 1; +L_0x2c5cb90 .part RS_0x7f99c4316848, 18, 1; +L_0x2c5cc80 .part RS_0x7f99c4316848, 18, 1; +L_0x2c5d140 .part/pv L_0x2c5d000, 18, 1, 32; +L_0x2c5d1e0 .part v0x2bc78e0_0, 2, 1; +L_0x2c5d280 .part RS_0x7f99c4320ec8, 18, 1; +L_0x2c5d370 .part RS_0x7f99c4320ef8, 18, 1; +L_0x2c5e470 .part/pv L_0x2c5d8b0, 18, 1, 32; +L_0x2c5d9f0 .part RS_0x7f99c4320f58, 17, 1; +L_0x2c5da90 .part RS_0x7f99c4320f28, 18, 1; +L_0x2c5e350 .part/pv L_0x2c5e140, 19, 1, 32; +L_0x2c5f0f0 .part v0x2bc78e0_0, 0, 1; +L_0x2c5e510 .part v0x2bc78e0_0, 1, 1; +L_0x2c5e640 .part RS_0x7f99c4320aa8, 19, 1; +L_0x2c5e6e0 .part RS_0x7f99c4320aa8, 19, 1; +L_0x2c5e780 .part RS_0x7f99c4316848, 19, 1; +L_0x2c5e870 .part RS_0x7f99c4320aa8, 19, 1; +L_0x2c5fe80 .part/pv L_0x2c5ef70, 19, 1, 32; +L_0x2c5f220 .part v0x2bc78e0_0, 0, 1; +L_0x2c5f350 .part v0x2bc78e0_0, 1, 1; +L_0x2c5f480 .part RS_0x7f99c4319e78, 19, 1; +L_0x2c5f520 .part RS_0x7f99c4319e78, 19, 1; +L_0x2c5f5c0 .part RS_0x7f99c4316848, 19, 1; +L_0x2c5f6b0 .part RS_0x7f99c4316848, 19, 1; +L_0x2c5fb10 .part/pv L_0x2c5f9d0, 19, 1, 32; +L_0x2c5fbb0 .part v0x2bc78e0_0, 2, 1; +L_0x2c5fc50 .part RS_0x7f99c4320ec8, 19, 1; +L_0x2c5fd40 .part RS_0x7f99c4320ef8, 19, 1; +L_0x2c60b90 .part/pv L_0x2c60c30, 19, 1, 32; +L_0x2c60d70 .part RS_0x7f99c4320f58, 18, 1; +L_0x2c5ff20 .part RS_0x7f99c4320f28, 19, 1; +L_0x2c60810 .part/pv L_0x2c60600, 20, 1, 32; +L_0x2c608b0 .part v0x2bc78e0_0, 0, 1; +L_0x2c609e0 .part v0x2bc78e0_0, 1, 1; +L_0x2c61ab0 .part RS_0x7f99c4320aa8, 20, 1; +L_0x2c61b50 .part RS_0x7f99c4320aa8, 20, 1; +L_0x2c60e10 .part RS_0x7f99c4316848, 20, 1; +L_0x2c60f00 .part RS_0x7f99c4320aa8, 20, 1; +L_0x2c61820 .part/pv L_0x2c61610, 20, 1, 32; +L_0x2c618c0 .part v0x2bc78e0_0, 0, 1; +L_0x2c619f0 .part v0x2bc78e0_0, 1, 1; +L_0x2c62950 .part RS_0x7f99c4319e78, 20, 1; +L_0x2c61bf0 .part RS_0x7f99c4319e78, 20, 1; +L_0x2c61c90 .part RS_0x7f99c4316848, 20, 1; +L_0x2c61d80 .part RS_0x7f99c4316848, 20, 1; +L_0x2c62240 .part/pv L_0x2c62100, 20, 1, 32; +L_0x2c622e0 .part v0x2bc78e0_0, 2, 1; +L_0x2c62380 .part RS_0x7f99c4320ec8, 20, 1; +L_0x2c62470 .part RS_0x7f99c4320ef8, 20, 1; +L_0x2c62560 .part/pv L_0x2c62600, 20, 1, 32; +L_0x2c62740 .part RS_0x7f99c4320f58, 19, 1; +L_0x2c627e0 .part RS_0x7f99c4320f28, 20, 1; +L_0x2c63ee0 .part/pv L_0x2c63cd0, 21, 1, 32; +L_0x2c63f80 .part v0x2bc78e0_0, 0, 1; +L_0x2c629f0 .part v0x2bc78e0_0, 1, 1; +L_0x2c62b20 .part RS_0x7f99c4320aa8, 21, 1; +L_0x2c62bc0 .part RS_0x7f99c4320aa8, 21, 1; +L_0x2c62c60 .part RS_0x7f99c4316848, 21, 1; +L_0x2c62d50 .part RS_0x7f99c4320aa8, 21, 1; +L_0x2c63660 .part/pv L_0x2c63450, 21, 1, 32; +L_0x2c64e20 .part v0x2bc78e0_0, 0, 1; +L_0x2c64f50 .part v0x2bc78e0_0, 1, 1; +L_0x2c640b0 .part RS_0x7f99c4319e78, 21, 1; +L_0x2c64150 .part RS_0x7f99c4319e78, 21, 1; +L_0x2c641f0 .part RS_0x7f99c4316848, 21, 1; +L_0x2c642e0 .part RS_0x7f99c4316848, 21, 1; +L_0x2c64780 .part/pv L_0x2c64640, 21, 1, 32; +L_0x2c64820 .part v0x2bc78e0_0, 2, 1; +L_0x2c648c0 .part RS_0x7f99c4320ec8, 21, 1; +L_0x2c649b0 .part RS_0x7f99c4320ef8, 21, 1; +L_0x2c64aa0 .part/pv L_0x2c64b40, 21, 1, 32; +L_0x2c64c80 .part RS_0x7f99c4320f58, 20, 1; +L_0x2c64d20 .part RS_0x7f99c4320f28, 21, 1; +L_0x2c66650 .part/pv L_0x2c66440, 22, 1, 32; +L_0x2c65080 .part v0x2bc78e0_0, 0, 1; +L_0x2c651b0 .part v0x2bc78e0_0, 1, 1; +L_0x2c652e0 .part RS_0x7f99c4320aa8, 22, 1; +L_0x2c65380 .part RS_0x7f99c4320aa8, 22, 1; +L_0x2c65420 .part RS_0x7f99c4316848, 22, 1; +L_0x2c65510 .part RS_0x7f99c4320aa8, 22, 1; +L_0x2c67500 .part/pv L_0x2c65c20, 22, 1, 32; +L_0x2c675a0 .part v0x2bc78e0_0, 0, 1; +L_0x2c666f0 .part v0x2bc78e0_0, 1, 1; +L_0x2c66820 .part RS_0x7f99c4319e78, 22, 1; +L_0x2c668c0 .part RS_0x7f99c4319e78, 22, 1; +L_0x2c66960 .part RS_0x7f99c4316848, 22, 1; +L_0x2c66a50 .part RS_0x7f99c4316848, 22, 1; +L_0x2c66f10 .part/pv L_0x2c66dd0, 22, 1, 32; +L_0x2c66fb0 .part v0x2bc78e0_0, 2, 1; +L_0x2c67050 .part RS_0x7f99c4320ec8, 22, 1; +L_0x2c67140 .part RS_0x7f99c4320ef8, 22, 1; +L_0x2c67230 .part/pv L_0x2c672d0, 22, 1, 32; +L_0x2c67410 .part RS_0x7f99c4320f58, 21, 1; +L_0x2c68540 .part RS_0x7f99c4320f28, 22, 1; +L_0x2c67f00 .part/pv L_0x2c67cf0, 23, 1, 32; +L_0x2c67fa0 .part v0x2bc78e0_0, 0, 1; +L_0x2c680d0 .part v0x2bc78e0_0, 1, 1; +L_0x2c68200 .part RS_0x7f99c4320aa8, 23, 1; +L_0x2c682a0 .part RS_0x7f99c4320aa8, 23, 1; +L_0x2c68340 .part RS_0x7f99c4316848, 23, 1; +L_0x2c68430 .part RS_0x7f99c4320aa8, 23, 1; +L_0x2c69cf0 .part/pv L_0x2c69ae0, 23, 1, 32; +L_0x2c685e0 .part v0x2bc78e0_0, 0, 1; +L_0x2c68710 .part v0x2bc78e0_0, 1, 1; +L_0x2c68840 .part RS_0x7f99c4319e78, 23, 1; +L_0x2c688e0 .part RS_0x7f99c4319e78, 23, 1; +L_0x2c68980 .part RS_0x7f99c4316848, 23, 1; +L_0x2c68a70 .part RS_0x7f99c4316848, 23, 1; +L_0x2c68f10 .part/pv L_0x2c68dd0, 23, 1, 32; +L_0x2c68fb0 .part v0x2bc78e0_0, 2, 1; +L_0x2c69050 .part RS_0x7f99c4320ec8, 23, 1; +L_0x2c69140 .part RS_0x7f99c4320ef8, 23, 1; +L_0x2c69230 .part/pv L_0x2c692d0, 23, 1, 32; +L_0x2c6aca0 .part RS_0x7f99c4320f58, 22, 1; +L_0x2c69d90 .part RS_0x7f99c4320f28, 23, 1; +L_0x2c6a680 .part/pv L_0x2c6a470, 24, 1, 32; +L_0x2c6a720 .part v0x2bc78e0_0, 0, 1; +L_0x2c6a850 .part v0x2bc78e0_0, 1, 1; +L_0x2c6a980 .part RS_0x7f99c4320aa8, 24, 1; +L_0x2c6aa20 .part RS_0x7f99c4320aa8, 24, 1; +L_0x2c6aac0 .part RS_0x7f99c4316848, 24, 1; +L_0x2c6abb0 .part RS_0x7f99c4320aa8, 24, 1; +L_0x2c6c470 .part/pv L_0x2c6c260, 24, 1, 32; +L_0x2c6c510 .part v0x2bc78e0_0, 0, 1; +L_0x2c6ad40 .part v0x2bc78e0_0, 1, 1; +L_0x2c6ae70 .part RS_0x7f99c4319e78, 24, 1; +L_0x2c6af10 .part RS_0x7f99c4319e78, 24, 1; +L_0x2c6afb0 .part RS_0x7f99c4316848, 24, 1; +L_0x2c6b0a0 .part RS_0x7f99c4316848, 24, 1; +L_0x2c6b5a0 .part/pv L_0x2c6b460, 24, 1, 32; +L_0x2c6b640 .part v0x2bc78e0_0, 2, 1; +L_0x2c6b6e0 .part RS_0x7f99c4320ec8, 24, 1; +L_0x2c6b7d0 .part RS_0x7f99c4320ef8, 24, 1; +L_0x2c6b8c0 .part/pv L_0x2c6b960, 24, 1, 32; +L_0x2c6baa0 .part RS_0x7f99c4320f58, 23, 1; +L_0x2c6bb40 .part RS_0x7f99c4320f28, 24, 1; +L_0x2c6cde0 .part/pv L_0x2c6cbd0, 25, 1, 32; +L_0x2c6ce80 .part v0x2bc78e0_0, 0, 1; +L_0x2c6cfb0 .part v0x2bc78e0_0, 1, 1; +L_0x2c6d0e0 .part RS_0x7f99c4320aa8, 25, 1; +L_0x2c6d180 .part RS_0x7f99c4320aa8, 25, 1; +L_0x2c6d220 .part RS_0x7f99c4316848, 25, 1; +L_0x2c6d310 .part RS_0x7f99c4320aa8, 25, 1; +L_0x2be2160 .part/pv L_0x2be1f50, 25, 1, 32; +L_0x2be2200 .part v0x2bc78e0_0, 0, 1; +L_0x2be2330 .part v0x2bc78e0_0, 1, 1; +L_0x2be2460 .part RS_0x7f99c4319e78, 25, 1; +L_0x2be2500 .part RS_0x7f99c4319e78, 25, 1; +L_0x2be25a0 .part RS_0x7f99c4316848, 25, 1; +L_0x2be2690 .part RS_0x7f99c4316848, 25, 1; +L_0x2be0b30 .part/pv L_0x2be29f0, 25, 1, 32; +L_0x2be0bd0 .part v0x2bc78e0_0, 2, 1; +L_0x2be0c70 .part RS_0x7f99c4320ec8, 25, 1; +L_0x2be0d60 .part RS_0x7f99c4320ef8, 25, 1; +L_0x2be0e50 .part/pv L_0x2be0ef0, 25, 1, 32; +L_0x2be1030 .part RS_0x7f99c4320f58, 24, 1; +L_0x2be10d0 .part RS_0x7f99c4320f28, 25, 1; +L_0x2be19c0 .part/pv L_0x2be17b0, 26, 1, 32; +L_0x2c72670 .part v0x2bc78e0_0, 0, 1; +L_0x2c727a0 .part v0x2bc78e0_0, 1, 1; +L_0x2c715f0 .part RS_0x7f99c4320aa8, 26, 1; +L_0x2c71690 .part RS_0x7f99c4320aa8, 26, 1; +L_0x2c71730 .part RS_0x7f99c4316848, 26, 1; +L_0x2c71820 .part RS_0x7f99c4320aa8, 26, 1; +L_0x2c72140 .part/pv L_0x2c71f30, 26, 1, 32; +L_0x2c721e0 .part v0x2bc78e0_0, 0, 1; +L_0x2c72310 .part v0x2bc78e0_0, 1, 1; +L_0x2c72440 .part RS_0x7f99c4319e78, 26, 1; +L_0x2c724e0 .part RS_0x7f99c4319e78, 26, 1; +L_0x2c72580 .part RS_0x7f99c4316848, 26, 1; +L_0x2c739b0 .part RS_0x7f99c4316848, 26, 1; +L_0x2c73e60 .part/pv L_0x2c73d20, 26, 1, 32; +L_0x2c728d0 .part v0x2bc78e0_0, 2, 1; +L_0x2c72970 .part RS_0x7f99c4320ec8, 26, 1; +L_0x2c72a60 .part RS_0x7f99c4320ef8, 26, 1; +L_0x2c72b50 .part/pv L_0x2c72bf0, 26, 1, 32; +L_0x2c72d30 .part RS_0x7f99c4320f58, 25, 1; +L_0x2c72dd0 .part RS_0x7f99c4320f28, 26, 1; +L_0x2c736c0 .part/pv L_0x2c734b0, 27, 1, 32; +L_0x2c73760 .part v0x2bc78e0_0, 0, 1; +L_0x2c73890 .part v0x2bc78e0_0, 1, 1; +L_0x2c750c0 .part RS_0x7f99c4320aa8, 27, 1; +L_0x2c73f00 .part RS_0x7f99c4320aa8, 27, 1; +L_0x2c73fa0 .part RS_0x7f99c4316848, 27, 1; +L_0x2c74090 .part RS_0x7f99c4320aa8, 27, 1; +L_0x2c749a0 .part/pv L_0x2c74790, 27, 1, 32; +L_0x2c74a40 .part v0x2bc78e0_0, 0, 1; +L_0x2c74b70 .part v0x2bc78e0_0, 1, 1; +L_0x2c74ca0 .part RS_0x7f99c4319e78, 27, 1; +L_0x2c74d40 .part RS_0x7f99c4319e78, 27, 1; +L_0x2c74de0 .part RS_0x7f99c4316848, 27, 1; +L_0x2c74ed0 .part RS_0x7f99c4316848, 27, 1; +L_0x2c76620 .part/pv L_0x2c764e0, 27, 1, 32; +L_0x2c766c0 .part v0x2bc78e0_0, 2, 1; +L_0x2c75160 .part RS_0x7f99c4320ec8, 27, 1; +L_0x2c75250 .part RS_0x7f99c4320ef8, 27, 1; +L_0x2c75340 .part/pv L_0x2c753e0, 27, 1, 32; +L_0x2c754e0 .part RS_0x7f99c4320f58, 26, 1; +L_0x2c75580 .part RS_0x7f99c4320f28, 27, 1; +L_0x2c75e70 .part/pv L_0x2c75c60, 28, 1, 32; +L_0x2c75f10 .part v0x2bc78e0_0, 0, 1; +L_0x2c76040 .part v0x2bc78e0_0, 1, 1; +L_0x2c76170 .part RS_0x7f99c4320aa8, 28, 1; +L_0x2c76210 .part RS_0x7f99c4320aa8, 28, 1; +L_0x2c77950 .part RS_0x7f99c4316848, 28, 1; +L_0x2c77a40 .part RS_0x7f99c4320aa8, 28, 1; +L_0x2c76f50 .part/pv L_0x2c76d40, 28, 1, 32; +L_0x2c76ff0 .part v0x2bc78e0_0, 0, 1; +L_0x2c77120 .part v0x2bc78e0_0, 1, 1; +L_0x2c77250 .part RS_0x7f99c4319e78, 28, 1; +L_0x2c772f0 .part RS_0x7f99c4319e78, 28, 1; +L_0x2c77390 .part RS_0x7f99c4316848, 28, 1; +L_0x2c77480 .part RS_0x7f99c4316848, 28, 1; +L_0x2c78db0 .part/pv L_0x2c77840, 28, 1, 32; +L_0x2c77b30 .part v0x2bc78e0_0, 2, 1; +L_0x2c77bd0 .part RS_0x7f99c4320ec8, 28, 1; +L_0x2c77cc0 .part RS_0x7f99c4320ef8, 28, 1; +L_0x2c77db0 .part/pv L_0x2c77e50, 28, 1, 32; +L_0x2c77f90 .part RS_0x7f99c4320f58, 27, 1; +L_0x2c78030 .part RS_0x7f99c4320f28, 28, 1; +L_0x2c78950 .part/pv L_0x2c78740, 29, 1, 32; +L_0x2c789f0 .part v0x2bc78e0_0, 0, 1; +L_0x2c78b20 .part v0x2bc78e0_0, 1, 1; +L_0x2c78c50 .part RS_0x7f99c4320aa8, 29, 1; +L_0x2c7a0e0 .part RS_0x7f99c4320aa8, 29, 1; +L_0x2c7a180 .part RS_0x7f99c4316848, 29, 1; +L_0x2c78e50 .part RS_0x7f99c4320aa8, 29, 1; +L_0x2c79760 .part/pv L_0x2c79550, 29, 1, 32; +L_0x2c79800 .part v0x2bc78e0_0, 0, 1; +L_0x2c79930 .part v0x2bc78e0_0, 1, 1; +L_0x2c79a60 .part RS_0x7f99c4319e78, 29, 1; +L_0x2c79b00 .part RS_0x7f99c4319e78, 29, 1; +L_0x2c79ba0 .part RS_0x7f99c4316848, 29, 1; +L_0x2c79c90 .part RS_0x7f99c4316848, 29, 1; +L_0x2c7b5e0 .part/pv L_0x2c7a050, 29, 1, 32; +L_0x2c7b680 .part v0x2bc78e0_0, 2, 1; +L_0x2c7a220 .part RS_0x7f99c4320ec8, 29, 1; +L_0x2c7a310 .part RS_0x7f99c4320ef8, 29, 1; +L_0x2c7a400 .part/pv L_0x2c7a4a0, 29, 1, 32; +L_0x2c7a5a0 .part RS_0x7f99c4320f58, 28, 1; +L_0x2c7a640 .part RS_0x7f99c4320f28, 29, 1; +L_0x2c7af00 .part/pv L_0x2c7acf0, 30, 1, 32; +L_0x2c7afa0 .part v0x2bc78e0_0, 0, 1; +L_0x2c7b0d0 .part v0x2bc78e0_0, 1, 1; +L_0x2c7b200 .part RS_0x7f99c4320aa8, 30, 1; +L_0x2c7b2a0 .part RS_0x7f99c4320aa8, 30, 1; +L_0x2c7b340 .part RS_0x7f99c4316848, 30, 1; +L_0x2c7b430 .part RS_0x7f99c4320aa8, 30, 1; +L_0x2c7bf20 .part/pv L_0x2c7bd10, 30, 1, 32; +L_0x2c7bfc0 .part v0x2bc78e0_0, 0, 1; +L_0x2c7c0f0 .part v0x2bc78e0_0, 1, 1; +L_0x2c7c220 .part RS_0x7f99c4319e78, 30, 1; +L_0x2c7c2c0 .part RS_0x7f99c4319e78, 30, 1; +L_0x2c7c360 .part RS_0x7f99c4316848, 30, 1; +L_0x2c7c450 .part RS_0x7f99c4316848, 30, 1; +L_0x2c7c950 .part/pv L_0x2c7c810, 30, 1, 32; +L_0x2c7de40 .part v0x2bc78e0_0, 2, 1; +L_0x2c7dee0 .part RS_0x7f99c4320ec8, 30, 1; +L_0x2c7cab0 .part RS_0x7f99c4320ef8, 30, 1; +L_0x2c7cba0 .part/pv L_0x2c7cc40, 30, 1, 32; +L_0x2c7cd80 .part RS_0x7f99c4320f58, 29, 1; +L_0x2c7ce20 .part RS_0x7f99c4320f28, 30, 1; +L_0x2c7d710 .part/pv L_0x2c7d500, 31, 1, 32; +L_0x2c7d7b0 .part v0x2bc78e0_0, 0, 1; +L_0x2c7d8e0 .part v0x2bc78e0_0, 1, 1; +L_0x2c7da10 .part RS_0x7f99c4320aa8, 31, 1; +L_0x2c7dab0 .part RS_0x7f99c4320aa8, 31, 1; +L_0x2c7db50 .part RS_0x7f99c4316848, 31, 1; +L_0x2c7dc40 .part RS_0x7f99c4320aa8, 31, 1; +L_0x2c45f50 .part/pv L_0x2c45d40, 31, 1, 32; +L_0x2c7df80 .part v0x2bc78e0_0, 0, 1; +L_0x2c7e0b0 .part v0x2bc78e0_0, 1, 1; +L_0x2c7e1e0 .part RS_0x7f99c4319e78, 31, 1; +L_0x2c7e280 .part RS_0x7f99c4319e78, 31, 1; +L_0x2c7e320 .part RS_0x7f99c4316848, 31, 1; +L_0x2c7e410 .part RS_0x7f99c4316848, 31, 1; +L_0x2c49690 .part/pv L_0x2c49550, 31, 1, 32; +L_0x2c49730 .part v0x2bc78e0_0, 2, 1; +L_0x2c497d0 .part RS_0x7f99c4320ec8, 31, 1; +L_0x2c498c0 .part RS_0x7f99c4320ef8, 31, 1; +L_0x2c499b0 .part/pv L_0x2c49a50, 31, 1, 32; +L_0x2c7e5a0 .part RS_0x7f99c4320f58, 30, 1; +L_0x2c7e640 .part RS_0x7f99c4320f28, 31, 1; +L_0x2ce9150 .part/pv L_0x2ce8f70, 0, 1, 32; +L_0x2c82790 .part v0x2bc78e0_0, 0, 1; +L_0x2c828c0 .part v0x2bc78e0_0, 1, 1; +L_0x2c829f0 .part RS_0x7f99c4320aa8, 0, 1; +L_0x2c82a90 .part RS_0x7f99c4320aa8, 0, 1; +L_0x2c82b30 .part RS_0x7f99c4316848, 0, 1; +L_0x2c82c20 .part RS_0x7f99c4320aa8, 0, 1; +L_0x2c83420 .part/pv L_0x2c83240, 0, 1, 32; +L_0x2c834c0 .part v0x2bc78e0_0, 0, 1; +L_0x2c835f0 .part v0x2bc78e0_0, 1, 1; +L_0x2c83720 .part RS_0x7f99c4319e78, 0, 1; +L_0x2c837c0 .part RS_0x7f99c4319e78, 0, 1; +L_0x2c83860 .part RS_0x7f99c4316848, 0, 1; +L_0x2c83950 .part RS_0x7f99c4316848, 0, 1; +L_0x2cea940 .part/pv L_0x2cea800, 0, 1, 32; +L_0x2c58bd0 .part v0x2bc78e0_0, 2, 1; +L_0x2c58c70 .part RS_0x7f99c4320ec8, 0, 1; +L_0x2c58d60 .part RS_0x7f99c4320ef8, 0, 1; +L_0x2c58e50 .part/pv L_0x2c58ef0, 0, 1, 32; +L_0x2c43660 .part RS_0x7f99c4320f28, 0, 1; +L_0x2c43700 .part RS_0x7f99c4320f28, 0, 1; +L_0x2c438e0 .part RS_0x7f99c4320f58, 31, 1; +S_0x2851a90 .scope module, "trial" "AddSubSLT32" 3 279, 3 205, S_0x29738d0; + .timescale -9 -12; +P_0x2851b88 .param/l "size" 3 228, +C4<0100000>; +L_0x2cab160/d .functor OR 1, L_0x2cab1e0, C4<0>, C4<0>, C4<0>; +L_0x2cab160 .delay (20000,20000,20000) L_0x2cab160/d; +L_0x2cab310/d .functor XOR 1, RS_0x7f99c4320da8, L_0x2c964e0, C4<0>, C4<0>; +L_0x2cab310 .delay (40000,40000,40000) L_0x2cab310/d; +L_0x2c96580/d .functor AND 1, L_0x2c96690, L_0x2c96730, C4<1>, C4<1>; +L_0x2c96580 .delay (20000,20000,20000) L_0x2c96580/d; +L_0x2c96820/d .functor NOT 1, RS_0x7f99c4320e38, C4<0>, C4<0>, C4<0>; +L_0x2c96820 .delay (10000,10000,10000) L_0x2c96820/d; +L_0x2cac400/d .functor NOT 1, L_0x2cac4a0, C4<0>, C4<0>, C4<0>; +L_0x2cac400 .delay (10000,10000,10000) L_0x2cac400/d; +L_0x2cac540/d .functor AND 1, L_0x2c96820, L_0x2cac6c0, C4<1>, C4<1>; +L_0x2cac540 .delay (20000,20000,20000) L_0x2cac540/d; +L_0x2cac760/d .functor AND 1, RS_0x7f99c4320e38, L_0x2cac400, C4<1>, C4<1>; +L_0x2cac760 .delay (20000,20000,20000) L_0x2cac760/d; +L_0x2cac8a0/d .functor AND 1, L_0x2cac540, L_0x2c96580, C4<1>, C4<1>; +L_0x2cac8a0 .delay (20000,20000,20000) L_0x2cac8a0/d; +L_0x2cad830/d .functor AND 1, L_0x2cac760, L_0x2c96580, C4<1>, C4<1>; +L_0x2cad830 .delay (20000,20000,20000) L_0x2cad830/d; +L_0x2cad930/d .functor OR 1, L_0x2cac8a0, L_0x2cad830, C4<0>, C4<0>; +L_0x2cad930 .delay (20000,20000,20000) L_0x2cad930/d; +v0x2b600f0_0 .alias "A", 31 0, v0x2bc6580_0; +v0x2b60190_0 .alias "AddSubSLTSum", 31 0, v0x2bc76e0_0; +v0x2b60230_0 .alias "B", 31 0, v0x2bc66a0_0; +RS_0x7f99c4320ad8/0/0 .resolv tri, L_0x2c80790, L_0x2c83fa0, L_0x2c853a0, L_0x2c86880; +RS_0x7f99c4320ad8/0/4 .resolv tri, L_0x2c87d20, L_0x2c89110, L_0x2c8a510, L_0x2c8b970; +RS_0x7f99c4320ad8/0/8 .resolv tri, L_0x2c8cf80, L_0x2c8e490, L_0x2c8f9a0, L_0x2c90eb0; +RS_0x7f99c4320ad8/0/12 .resolv tri, L_0x2c922c0, L_0x2c93710, L_0x2c94b80, L_0x2c96000; +RS_0x7f99c4320ad8/0/16 .resolv tri, L_0x2c976c0, L_0x2c98b30, L_0x2c99fe0, L_0x2c9b450; +RS_0x7f99c4320ad8/0/20 .resolv tri, L_0x2c9c950, L_0x2c9de60, L_0x2c9f220, L_0x2ca06a0; +RS_0x7f99c4320ad8/0/24 .resolv tri, L_0x2ca1b90, L_0x2c063d0, L_0x2ca5540, L_0x2ca6e30; +RS_0x7f99c4320ad8/0/28 .resolv tri, L_0x2ca8320, L_0x2ca9820, L_0x2caad10, L_0x2cac200; +RS_0x7f99c4320ad8/1/0 .resolv tri, RS_0x7f99c4320ad8/0/0, RS_0x7f99c4320ad8/0/4, RS_0x7f99c4320ad8/0/8, RS_0x7f99c4320ad8/0/12; +RS_0x7f99c4320ad8/1/4 .resolv tri, RS_0x7f99c4320ad8/0/16, RS_0x7f99c4320ad8/0/20, RS_0x7f99c4320ad8/0/24, RS_0x7f99c4320ad8/0/28; +RS_0x7f99c4320ad8 .resolv tri, RS_0x7f99c4320ad8/1/0, RS_0x7f99c4320ad8/1/4, C4, C4; +v0x2b60300_0 .net8 "CarryoutWire", 31 0, RS_0x7f99c4320ad8; 32 drivers +v0x2b60380_0 .alias "Command", 2 0, v0x2bc67a0_0; +v0x2b60400_0 .net "Res0OF1", 0 0, L_0x2cac760; 1 drivers +v0x2b604a0_0 .net "Res1OF0", 0 0, L_0x2cac540; 1 drivers +v0x2b60540_0 .alias "SLTflag", 0 0, v0x2bc7a60_0; +v0x2b60630_0 .net "SLTflag0", 0 0, L_0x2cac8a0; 1 drivers +v0x2b606d0_0 .net "SLTflag1", 0 0, L_0x2cad830; 1 drivers +v0x2b60770_0 .net "SLTon", 0 0, L_0x2c96580; 1 drivers +v0x2b60810_0 .net *"_s292", 0 0, L_0x2cab1e0; 1 drivers +v0x2b608b0_0 .net/s *"_s293", 0 0, C4<0>; 1 drivers +v0x2b60950_0 .net *"_s296", 0 0, L_0x2c964e0; 1 drivers +v0x2b60a70_0 .net *"_s298", 0 0, L_0x2c96690; 1 drivers +v0x2b60b10_0 .net *"_s300", 0 0, L_0x2c96730; 1 drivers +v0x2b609d0_0 .net *"_s302", 0 0, L_0x2cac4a0; 1 drivers +v0x2b60c60_0 .net *"_s304", 0 0, L_0x2cac6c0; 1 drivers +v0x2b60d80_0 .alias "carryin", 31 0, v0x2bc71d0_0; +v0x2b60e00_0 .alias "carryout", 0 0, v0x2bc7be0_0; +v0x2b60ce0_0 .net "nAddSubSLTSum", 0 0, L_0x2cac400; 1 drivers +v0x2b60f30_0 .net "nOF", 0 0, L_0x2c96820; 1 drivers +v0x2b60e80_0 .alias "overflow", 0 0, v0x2bc7c60_0; +v0x2b61070_0 .alias "subtract", 31 0, v0x2bc7ce0_0; +L_0x2c806a0 .part/pv L_0x2c7f180, 1, 1, 32; +L_0x2c80790 .part/pv L_0x2c80560, 1, 1, 32; +L_0x2c80880 .part/pv L_0x2c7eeb0, 1, 1, 32; +L_0x2c80970 .part v0x2bc7660_0, 1, 1; +L_0x2c80a10 .part v0x2bc7860_0, 1, 1; +L_0x2c80b40 .part RS_0x7f99c4320ad8, 0, 1; +L_0x2c83eb0 .part/pv L_0x2c81630, 2, 1, 32; +L_0x2c83fa0 .part/pv L_0x2c83d70, 2, 1, 32; +L_0x2c840e0 .part/pv L_0x2c81360, 2, 1, 32; +L_0x2c841d0 .part v0x2bc7660_0, 2, 1; +L_0x2c842d0 .part v0x2bc7860_0, 2, 1; +L_0x2c84400 .part RS_0x7f99c4320ad8, 1, 1; +L_0x2c852b0 .part/pv L_0x2c84e20, 3, 1, 32; +L_0x2c853a0 .part/pv L_0x2c85170, 3, 1, 32; +L_0x2c85510 .part/pv L_0x2c84b50, 3, 1, 32; +L_0x2c85600 .part v0x2bc7660_0, 3, 1; +L_0x2c85730 .part v0x2bc7860_0, 3, 1; +L_0x2c85860 .part RS_0x7f99c4320ad8, 2, 1; +L_0x2c86790 .part/pv L_0x2c86300, 4, 1, 32; +L_0x2c86880 .part/pv L_0x2c86650, 4, 1, 32; +L_0x2c85900 .part/pv L_0x2c86030, 4, 1, 32; +L_0x2c86a70 .part v0x2bc7660_0, 4, 1; +L_0x2c86970 .part v0x2bc7860_0, 4, 1; +L_0x2c86c60 .part RS_0x7f99c4320ad8, 3, 1; +L_0x2c87c30 .part/pv L_0x2c877a0, 5, 1, 32; +L_0x2c87d20 .part/pv L_0x2c87af0, 5, 1, 32; +L_0x2c86e10 .part/pv L_0x2c874d0, 5, 1, 32; +L_0x2c87f40 .part v0x2bc7660_0, 5, 1; +L_0x2c87e10 .part v0x2bc7860_0, 5, 1; +L_0x2c88160 .part RS_0x7f99c4320ad8, 4, 1; +L_0x2c89020 .part/pv L_0x2c88b90, 6, 1, 32; +L_0x2c89110 .part/pv L_0x2c88ee0, 6, 1, 32; +L_0x2c88200 .part/pv L_0x2c888c0, 6, 1, 32; +L_0x2c89310 .part v0x2bc7660_0, 6, 1; +L_0x2c89200 .part v0x2bc7860_0, 6, 1; +L_0x2c89560 .part RS_0x7f99c4320ad8, 5, 1; +L_0x2c8a420 .part/pv L_0x2c89f90, 7, 1, 32; +L_0x2c8a510 .part/pv L_0x2c8a2e0, 7, 1, 32; +L_0x2c89600 .part/pv L_0x2c89cc0, 7, 1, 32; +L_0x2c8a740 .part v0x2bc7660_0, 7, 1; +L_0x2c8a600 .part v0x2bc7860_0, 7, 1; +L_0x2c8a930 .part RS_0x7f99c4320ad8, 6, 1; +L_0x2c8b880 .part/pv L_0x2c8b3b0, 8, 1, 32; +L_0x2c8b970 .part/pv L_0x2c8b720, 8, 1, 32; +L_0x2c8a9d0 .part/pv L_0x2c8b0e0, 8, 1, 32; +L_0x2c8bbd0 .part v0x2bc7660_0, 8, 1; +L_0x2c8ba60 .part v0x2bc7860_0, 8, 1; +L_0x2c8bdf0 .part RS_0x7f99c4320ad8, 7, 1; +L_0x2c8ce90 .part/pv L_0x2c8c9e0, 9, 1, 32; +L_0x2c8cf80 .part/pv L_0x2c8cd30, 9, 1, 32; +L_0x2c8c0a0 .part/pv L_0x2c8c710, 9, 1, 32; +L_0x2c8c190 .part v0x2bc7660_0, 9, 1; +L_0x2c8d220 .part v0x2bc7860_0, 9, 1; +L_0x2c8d350 .part RS_0x7f99c4320ad8, 8, 1; +L_0x2c8e3a0 .part/pv L_0x2c8def0, 10, 1, 32; +L_0x2c8e490 .part/pv L_0x2c8e240, 10, 1, 32; +L_0x2c8d3f0 .part/pv L_0x2c8dc20, 10, 1, 32; +L_0x2c8d4e0 .part v0x2bc7660_0, 10, 1; +L_0x2c8e760 .part v0x2bc7860_0, 10, 1; +L_0x2c8e890 .part RS_0x7f99c4320ad8, 9, 1; +L_0x2c8f8b0 .part/pv L_0x2c8f400, 11, 1, 32; +L_0x2c8f9a0 .part/pv L_0x2c8f750, 11, 1, 32; +L_0x2c8e930 .part/pv L_0x2c8f130, 11, 1, 32; +L_0x2c8ea20 .part v0x2bc7660_0, 11, 1; +L_0x2c8fca0 .part v0x2bc7860_0, 11, 1; +L_0x2c8fdd0 .part RS_0x7f99c4320ad8, 10, 1; +L_0x2c90dc0 .part/pv L_0x2c90910, 12, 1, 32; +L_0x2c90eb0 .part/pv L_0x2c90c60, 12, 1, 32; +L_0x2c8fe70 .part/pv L_0x2c90640, 12, 1, 32; +L_0x2c8ff60 .part v0x2bc7660_0, 12, 1; +L_0x2c911e0 .part v0x2bc7860_0, 12, 1; +L_0x2c91280 .part RS_0x7f99c4320ad8, 11, 1; +L_0x2c921d0 .part/pv L_0x2c91e10, 13, 1, 32; +L_0x2c922c0 .part/pv L_0x2c92090, 13, 1, 32; +L_0x2c91320 .part/pv L_0x2c91b40, 13, 1, 32; +L_0x2c91410 .part v0x2bc7660_0, 13, 1; +L_0x2c914b0 .part v0x2bc7860_0, 13, 1; +L_0x2c926b0 .part RS_0x7f99c4320ad8, 12, 1; +L_0x2c93620 .part/pv L_0x2c93190, 14, 1, 32; +L_0x2c93710 .part/pv L_0x2c934e0, 14, 1, 32; +L_0x2c92750 .part/pv L_0x2c92ec0, 14, 1, 32; +L_0x2c92840 .part v0x2bc7660_0, 14, 1; +L_0x2c928e0 .part v0x2bc7860_0, 14, 1; +L_0x2c93b30 .part RS_0x7f99c4320ad8, 13, 1; +L_0x2c94a90 .part/pv L_0x2c94600, 15, 1, 32; +L_0x2c94b80 .part/pv L_0x2c94950, 15, 1, 32; +L_0x2c93bd0 .part/pv L_0x2c94330, 15, 1, 32; +L_0x2c93cc0 .part v0x2bc7660_0, 15, 1; +L_0x2c93d60 .part v0x2bc7860_0, 15, 1; +L_0x2c94fd0 .part RS_0x7f99c4320ad8, 14, 1; +L_0x2c95f10 .part/pv L_0x2c95a80, 16, 1, 32; +L_0x2c96000 .part/pv L_0x2c95dd0, 16, 1, 32; +L_0x2c95070 .part/pv L_0x2c957b0, 16, 1, 32; +L_0x2c95160 .part v0x2bc7660_0, 16, 1; +L_0x2c95200 .part v0x2bc7860_0, 16, 1; +L_0x2c963f0 .part RS_0x7f99c4320ad8, 15, 1; +L_0x2c975d0 .part/pv L_0x2c97140, 17, 1, 32; +L_0x2c976c0 .part/pv L_0x2c97490, 17, 1, 32; +L_0x2c968a0 .part/pv L_0x2c96e70, 17, 1, 32; +L_0x2c96990 .part v0x2bc7660_0, 17, 1; +L_0x2c96a30 .part v0x2bc7860_0, 17, 1; +L_0x2c97ae0 .part RS_0x7f99c4320ad8, 16, 1; +L_0x2c98a40 .part/pv L_0x2c985b0, 18, 1, 32; +L_0x2c98b30 .part/pv L_0x2c98900, 18, 1, 32; +L_0x2c97b80 .part/pv L_0x2c982e0, 18, 1, 32; +L_0x2c97c70 .part v0x2bc7660_0, 18, 1; +L_0x2c97d10 .part v0x2bc7860_0, 18, 1; +L_0x2c98f80 .part RS_0x7f99c4320ad8, 17, 1; +L_0x2c99ef0 .part/pv L_0x2c99a60, 19, 1, 32; +L_0x2c99fe0 .part/pv L_0x2c99db0, 19, 1, 32; +L_0x2c99020 .part/pv L_0x2c99790, 19, 1, 32; +L_0x2c99110 .part v0x2bc7660_0, 19, 1; +L_0x2c991b0 .part v0x2bc7860_0, 19, 1; +L_0x2c992e0 .part RS_0x7f99c4320ad8, 18, 1; +L_0x2c9b360 .part/pv L_0x2c9ae90, 20, 1, 32; +L_0x2c9b450 .part/pv L_0x2c9b200, 20, 1, 32; +L_0x2c9a0d0 .part/pv L_0x2c9abc0, 20, 1, 32; +L_0x2c9a1c0 .part v0x2bc7660_0, 20, 1; +L_0x2c9a260 .part v0x2bc7860_0, 20, 1; +L_0x2c9a390 .part RS_0x7f99c4320ad8, 19, 1; +L_0x2c9c860 .part/pv L_0x2c9c3b0, 21, 1, 32; +L_0x2c9c950 .part/pv L_0x2c9c700, 21, 1, 32; +L_0x2c9b540 .part/pv L_0x2c9c0e0, 21, 1, 32; +L_0x2c9b630 .part v0x2bc7660_0, 21, 1; +L_0x2c9b6d0 .part v0x2bc7860_0, 21, 1; +L_0x2c9b800 .part RS_0x7f99c4320ad8, 20, 1; +L_0x2c9dd70 .part/pv L_0x2c9d8c0, 22, 1, 32; +L_0x2c9de60 .part/pv L_0x2c9dc10, 22, 1, 32; +L_0x2c9ca40 .part/pv L_0x2c9d5f0, 22, 1, 32; +L_0x2c9cb30 .part v0x2bc7660_0, 22, 1; +L_0x2c9cbd0 .part v0x2bc7860_0, 22, 1; +L_0x2c9cd00 .part RS_0x7f99c4320ad8, 21, 1; +L_0x2c9f130 .part/pv L_0x2c9eca0, 23, 1, 32; +L_0x2c9f220 .part/pv L_0x2c9eff0, 23, 1, 32; +L_0x2c9df50 .part/pv L_0x2c9e9d0, 23, 1, 32; +L_0x2c9e040 .part v0x2bc7660_0, 23, 1; +L_0x2c9e0e0 .part v0x2bc7860_0, 23, 1; +L_0x2c9e210 .part RS_0x7f99c4320ad8, 22, 1; +L_0x2ca05b0 .part/pv L_0x2ca0080, 24, 1, 32; +L_0x2ca06a0 .part/pv L_0x2ca0450, 24, 1, 32; +L_0x2c9f310 .part/pv L_0x2c9fdb0, 24, 1, 32; +L_0x2c9f400 .part v0x2bc7660_0, 24, 1; +L_0x2c9f4a0 .part v0x2bc7860_0, 24, 1; +L_0x2c9f5d0 .part RS_0x7f99c4320ad8, 23, 1; +L_0x2ca1aa0 .part/pv L_0x2ca1570, 25, 1, 32; +L_0x2ca1b90 .part/pv L_0x2ca1940, 25, 1, 32; +L_0x2ca0790 .part/pv L_0x2ca12a0, 25, 1, 32; +L_0x2ca0880 .part v0x2bc7660_0, 25, 1; +L_0x2ca0920 .part v0x2bc7860_0, 25, 1; +L_0x2ca0a50 .part RS_0x7f99c4320ad8, 24, 1; +L_0x2c062e0 .part/pv L_0x2c05de0, 26, 1, 32; +L_0x2c063d0 .part/pv L_0x2c06180, 26, 1, 32; +L_0x2c05490 .part/pv L_0x2c05b10, 26, 1, 32; +L_0x2c05580 .part v0x2bc7660_0, 26, 1; +L_0x2c05620 .part v0x2bc7860_0, 26, 1; +L_0x2c05750 .part RS_0x7f99c4320ad8, 25, 1; +L_0x2ca5450 .part/pv L_0x2ca4f20, 27, 1, 32; +L_0x2ca5540 .part/pv L_0x2ca52f0, 27, 1, 32; +L_0x2ca4190 .part/pv L_0x2ca4c50, 27, 1, 32; +L_0x2bedf50 .part v0x2bc7660_0, 27, 1; +L_0x2bedff0 .part v0x2bc7860_0, 27, 1; +L_0x2bee120 .part RS_0x7f99c4320ad8, 26, 1; +L_0x2ca6d40 .part/pv L_0x2ca68b0, 28, 1, 32; +L_0x2ca6e30 .part/pv L_0x2ca6c00, 28, 1, 32; +L_0x2ca6340 .part/pv L_0x2ca58a0, 28, 1, 32; +L_0x2ca6430 .part v0x2bc7660_0, 28, 1; +L_0x2ca64d0 .part v0x2bc7860_0, 28, 1; +L_0x2ca6600 .part RS_0x7f99c4320ad8, 27, 1; +L_0x2ca8230 .part/pv L_0x2ca7d20, 29, 1, 32; +L_0x2ca8320 .part/pv L_0x2ca80d0, 29, 1, 32; +L_0x2ca6f20 .part/pv L_0x2ca7a20, 29, 1, 32; +L_0x2ca7010 .part v0x2bc7660_0, 29, 1; +L_0x2ca70b0 .part v0x2bc7860_0, 29, 1; +L_0x2ca71e0 .part RS_0x7f99c4320ad8, 28, 1; +L_0x2ca9730 .part/pv L_0x2ca9220, 30, 1, 32; +L_0x2ca9820 .part/pv L_0x2ca95d0, 30, 1, 32; +L_0x2ca8410 .part/pv L_0x2ca8f20, 30, 1, 32; +L_0x2ca8500 .part v0x2bc7660_0, 30, 1; +L_0x2ca85a0 .part v0x2bc7860_0, 30, 1; +L_0x2ca86d0 .part RS_0x7f99c4320ad8, 29, 1; +L_0x2caac20 .part/pv L_0x2caa710, 31, 1, 32; +L_0x2caad10 .part/pv L_0x2caaac0, 31, 1, 32; +L_0x2ca9910 .part/pv L_0x2caa410, 31, 1, 32; +L_0x2ca9a00 .part v0x2bc7660_0, 31, 1; +L_0x2ca9aa0 .part v0x2bc7860_0, 31, 1; +L_0x2ca9bd0 .part RS_0x7f99c4320ad8, 30, 1; +L_0x2cac110 .part/pv L_0x2cabc00, 0, 1, 32; +L_0x2cac200 .part/pv L_0x2cabfb0, 0, 1, 32; +L_0x2caae00 .part/pv L_0x2cab930, 0, 1, 32; +L_0x2caaef0 .part v0x2bc7660_0, 0, 1; +L_0x2caaf90 .part v0x2bc7860_0, 0, 1; +L_0x2cab0c0 .part RS_0x7f99c4320e68, 0, 1; +L_0x2cab1e0 .part RS_0x7f99c4320ad8, 31, 1; +L_0x2c964e0 .part RS_0x7f99c4320ad8, 30, 1; +L_0x2c96690 .part v0x2bc78e0_0, 1, 1; +L_0x2c96730 .part RS_0x7f99c4320e68, 0, 1; +L_0x2cac4a0 .part RS_0x7f99c4320aa8, 31, 1; +L_0x2cac6c0 .part RS_0x7f99c4320aa8, 31, 1; +S_0x2b5f0e0 .scope module, "attempt2" "MiddleAddSubSLT" 3 225, 3 89, S_0x2851a90; + .timescale -9 -12; +L_0x2ca9c70/d .functor NOT 1, L_0x2caaf90, C4<0>, C4<0>, C4<0>; +L_0x2ca9c70 .delay (10000,10000,10000) L_0x2ca9c70/d; +L_0x2cab7f0/d .functor NOT 1, L_0x2cab890, C4<0>, C4<0>, C4<0>; +L_0x2cab7f0 .delay (10000,10000,10000) L_0x2cab7f0/d; +L_0x2cab930/d .functor AND 1, L_0x2caba70, L_0x2cab7f0, C4<1>, C4<1>; +L_0x2cab930 .delay (20000,20000,20000) L_0x2cab930/d; +L_0x2cabb10/d .functor XOR 1, L_0x2caaef0, L_0x2cab5c0, C4<0>, C4<0>; +L_0x2cabb10 .delay (40000,40000,40000) L_0x2cabb10/d; +L_0x2cabc00/d .functor XOR 1, L_0x2cabb10, L_0x2cab0c0, C4<0>, C4<0>; +L_0x2cabc00 .delay (40000,40000,40000) L_0x2cabc00/d; +L_0x2cabd20/d .functor AND 1, L_0x2caaef0, L_0x2cab5c0, C4<1>, C4<1>; +L_0x2cabd20 .delay (20000,20000,20000) L_0x2cabd20/d; +L_0x2cabec0/d .functor AND 1, L_0x2cabb10, L_0x2cab0c0, C4<1>, C4<1>; +L_0x2cabec0 .delay (20000,20000,20000) L_0x2cabec0/d; +L_0x2cabfb0/d .functor OR 1, L_0x2cabd20, L_0x2cabec0, C4<0>, C4<0>; +L_0x2cabfb0 .delay (20000,20000,20000) L_0x2cabfb0/d; +v0x2b5f750_0 .net "A", 0 0, L_0x2caaef0; 1 drivers +v0x2b5f810_0 .net "AandB", 0 0, L_0x2cabd20; 1 drivers +v0x2b5f8b0_0 .net "AddSubSLTSum", 0 0, L_0x2cabc00; 1 drivers +v0x2b5f950_0 .net "AxorB", 0 0, L_0x2cabb10; 1 drivers +v0x2b5f9d0_0 .net "B", 0 0, L_0x2caaf90; 1 drivers +v0x2b5fa80_0 .net "BornB", 0 0, L_0x2cab5c0; 1 drivers +v0x2b5fb40_0 .net "CINandAxorB", 0 0, L_0x2cabec0; 1 drivers +v0x2b5fbc0_0 .alias "Command", 2 0, v0x2bc67a0_0; +v0x2b5fc40_0 .net *"_s3", 0 0, L_0x2cab890; 1 drivers +v0x2b5fcc0_0 .net *"_s5", 0 0, L_0x2caba70; 1 drivers +v0x2b5fd60_0 .net "carryin", 0 0, L_0x2cab0c0; 1 drivers +v0x2b5fe00_0 .net "carryout", 0 0, L_0x2cabfb0; 1 drivers +v0x2b5fea0_0 .net "nB", 0 0, L_0x2ca9c70; 1 drivers +v0x2b5ff50_0 .net "nCmd2", 0 0, L_0x2cab7f0; 1 drivers +v0x2b60050_0 .net "subtract", 0 0, L_0x2cab930; 1 drivers +L_0x2cab750 .part v0x2bc78e0_0, 0, 1; +L_0x2cab890 .part v0x2bc78e0_0, 2, 1; +L_0x2caba70 .part v0x2bc78e0_0, 0, 1; +S_0x2b5f1d0 .scope module, "mux0" "TwoInMux" 3 105, 3 8, S_0x2b5f0e0; + .timescale -9 -12; +L_0x2ca9dd0/d .functor NOT 1, L_0x2cab750, C4<0>, C4<0>, C4<0>; +L_0x2ca9dd0 .delay (10000,10000,10000) L_0x2ca9dd0/d; +L_0x2cab3e0/d .functor AND 1, L_0x2caaf90, L_0x2ca9dd0, C4<1>, C4<1>; +L_0x2cab3e0 .delay (20000,20000,20000) L_0x2cab3e0/d; +L_0x2cab4d0/d .functor AND 1, L_0x2ca9c70, L_0x2cab750, C4<1>, C4<1>; +L_0x2cab4d0 .delay (20000,20000,20000) L_0x2cab4d0/d; +L_0x2cab5c0/d .functor OR 1, L_0x2cab3e0, L_0x2cab4d0, C4<0>, C4<0>; +L_0x2cab5c0 .delay (20000,20000,20000) L_0x2cab5c0/d; +v0x2b5f2c0_0 .net "S", 0 0, L_0x2cab750; 1 drivers +v0x2b5f380_0 .alias "in0", 0 0, v0x2b5f9d0_0; +v0x2b5f420_0 .alias "in1", 0 0, v0x2b5fea0_0; +v0x2b5f4c0_0 .net "nS", 0 0, L_0x2ca9dd0; 1 drivers +v0x2b5f570_0 .net "out0", 0 0, L_0x2cab3e0; 1 drivers +v0x2b5f610_0 .net "out1", 0 0, L_0x2cab4d0; 1 drivers +v0x2b5f6b0_0 .alias "outfinal", 0 0, v0x2b5fa80_0; +S_0x2b5df40 .scope generate, "addbits[1]" "addbits[1]" 3 230, 3 230, S_0x2851a90; + .timescale -9 -12; +P_0x2b5d958 .param/l "i" 3 230, +C4<01>; +S_0x2b5e0b0 .scope module, "attempt" "MiddleAddSubSLT" 3 232, 3 89, S_0x2b5df40; + .timescale -9 -12; +L_0x2c7e730/d .functor NOT 1, L_0x2c80a10, C4<0>, C4<0>, C4<0>; +L_0x2c7e730 .delay (10000,10000,10000) L_0x2c7e730/d; +L_0x2c7ed70/d .functor NOT 1, L_0x2c7ee10, C4<0>, C4<0>, C4<0>; +L_0x2c7ed70 .delay (10000,10000,10000) L_0x2c7ed70/d; +L_0x2c7eeb0/d .functor AND 1, L_0x2c7eff0, L_0x2c7ed70, C4<1>, C4<1>; +L_0x2c7eeb0 .delay (20000,20000,20000) L_0x2c7eeb0/d; +L_0x2c7f090/d .functor XOR 1, L_0x2c80970, L_0x2c7eb40, C4<0>, C4<0>; +L_0x2c7f090 .delay (40000,40000,40000) L_0x2c7f090/d; +L_0x2c7f180/d .functor XOR 1, L_0x2c7f090, L_0x2c80b40, C4<0>, C4<0>; +L_0x2c7f180 .delay (40000,40000,40000) L_0x2c7f180/d; +L_0x2c7f270/d .functor AND 1, L_0x2c80970, L_0x2c7eb40, C4<1>, C4<1>; +L_0x2c7f270 .delay (20000,20000,20000) L_0x2c7f270/d; +L_0x2c80470/d .functor AND 1, L_0x2c7f090, L_0x2c80b40, C4<1>, C4<1>; +L_0x2c80470 .delay (20000,20000,20000) L_0x2c80470/d; +L_0x2c80560/d .functor OR 1, L_0x2c7f270, L_0x2c80470, C4<0>, C4<0>; +L_0x2c80560 .delay (20000,20000,20000) L_0x2c80560/d; +v0x2b5e740_0 .net "A", 0 0, L_0x2c80970; 1 drivers +v0x2b5e800_0 .net "AandB", 0 0, L_0x2c7f270; 1 drivers +v0x2b5e8a0_0 .net "AddSubSLTSum", 0 0, L_0x2c7f180; 1 drivers +v0x2b5e940_0 .net "AxorB", 0 0, L_0x2c7f090; 1 drivers +v0x2b5e9c0_0 .net "B", 0 0, L_0x2c80a10; 1 drivers +v0x2b5ea70_0 .net "BornB", 0 0, L_0x2c7eb40; 1 drivers +v0x2b5eb30_0 .net "CINandAxorB", 0 0, L_0x2c80470; 1 drivers +v0x2b5ebb0_0 .alias "Command", 2 0, v0x2bc67a0_0; +v0x2b5ec30_0 .net *"_s3", 0 0, L_0x2c7ee10; 1 drivers +v0x2b5ecb0_0 .net *"_s5", 0 0, L_0x2c7eff0; 1 drivers +v0x2b5ed50_0 .net "carryin", 0 0, L_0x2c80b40; 1 drivers +v0x2b5edf0_0 .net "carryout", 0 0, L_0x2c80560; 1 drivers +v0x2b5ee90_0 .net "nB", 0 0, L_0x2c7e730; 1 drivers +v0x2b5ef40_0 .net "nCmd2", 0 0, L_0x2c7ed70; 1 drivers +v0x2b5f040_0 .net "subtract", 0 0, L_0x2c7eeb0; 1 drivers +L_0x2c7ecd0 .part v0x2bc78e0_0, 0, 1; +L_0x2c7ee10 .part v0x2bc78e0_0, 2, 1; +L_0x2c7eff0 .part v0x2bc78e0_0, 0, 1; +S_0x2b5e1a0 .scope module, "mux0" "TwoInMux" 3 105, 3 8, S_0x2b5e0b0; + .timescale -9 -12; +L_0x2c7e8c0/d .functor NOT 1, L_0x2c7ecd0, C4<0>, C4<0>, C4<0>; +L_0x2c7e8c0 .delay (10000,10000,10000) L_0x2c7e8c0/d; +L_0x2c7e960/d .functor AND 1, L_0x2c80a10, L_0x2c7e8c0, C4<1>, C4<1>; +L_0x2c7e960 .delay (20000,20000,20000) L_0x2c7e960/d; +L_0x2c7ea50/d .functor AND 1, L_0x2c7e730, L_0x2c7ecd0, C4<1>, C4<1>; +L_0x2c7ea50 .delay (20000,20000,20000) L_0x2c7ea50/d; +L_0x2c7eb40/d .functor OR 1, L_0x2c7e960, L_0x2c7ea50, C4<0>, C4<0>; +L_0x2c7eb40 .delay (20000,20000,20000) L_0x2c7eb40/d; +v0x2b5e290_0 .net "S", 0 0, L_0x2c7ecd0; 1 drivers +v0x2b5e330_0 .alias "in0", 0 0, v0x2b5e9c0_0; +v0x2b5e3d0_0 .alias "in1", 0 0, v0x2b5ee90_0; +v0x2b5e470_0 .net "nS", 0 0, L_0x2c7e8c0; 1 drivers +v0x2b5e520_0 .net "out0", 0 0, L_0x2c7e960; 1 drivers +v0x2b5e5c0_0 .net "out1", 0 0, L_0x2c7ea50; 1 drivers +v0x2b5e6a0_0 .alias "outfinal", 0 0, v0x2b5ea70_0; +S_0x2b5cda0 .scope generate, "addbits[2]" "addbits[2]" 3 230, 3 230, S_0x2851a90; + .timescale -9 -12; +P_0x2b5c7b8 .param/l "i" 3 230, +C4<010>; +S_0x2b5cf10 .scope module, "attempt" "MiddleAddSubSLT" 3 232, 3 89, S_0x2b5cda0; + .timescale -9 -12; +L_0x2c80be0/d .functor NOT 1, L_0x2c842d0, C4<0>, C4<0>, C4<0>; +L_0x2c80be0 .delay (10000,10000,10000) L_0x2c80be0/d; +L_0x2c81220/d .functor NOT 1, L_0x2c812c0, C4<0>, C4<0>, C4<0>; +L_0x2c81220 .delay (10000,10000,10000) L_0x2c81220/d; +L_0x2c81360/d .functor AND 1, L_0x2c814a0, L_0x2c81220, C4<1>, C4<1>; +L_0x2c81360 .delay (20000,20000,20000) L_0x2c81360/d; +L_0x2c81540/d .functor XOR 1, L_0x2c841d0, L_0x2c80ff0, C4<0>, C4<0>; +L_0x2c81540 .delay (40000,40000,40000) L_0x2c81540/d; +L_0x2c81630/d .functor XOR 1, L_0x2c81540, L_0x2c84400, C4<0>, C4<0>; +L_0x2c81630 .delay (40000,40000,40000) L_0x2c81630/d; +L_0x2c81720/d .functor AND 1, L_0x2c841d0, L_0x2c80ff0, C4<1>, C4<1>; +L_0x2c81720 .delay (20000,20000,20000) L_0x2c81720/d; +L_0x2c83c80/d .functor AND 1, L_0x2c81540, L_0x2c84400, C4<1>, C4<1>; +L_0x2c83c80 .delay (20000,20000,20000) L_0x2c83c80/d; +L_0x2c83d70/d .functor OR 1, L_0x2c81720, L_0x2c83c80, C4<0>, C4<0>; +L_0x2c83d70 .delay (20000,20000,20000) L_0x2c83d70/d; +v0x2b5d5a0_0 .net "A", 0 0, L_0x2c841d0; 1 drivers +v0x2b5d660_0 .net "AandB", 0 0, L_0x2c81720; 1 drivers +v0x2b5d700_0 .net "AddSubSLTSum", 0 0, L_0x2c81630; 1 drivers +v0x2b5d7a0_0 .net "AxorB", 0 0, L_0x2c81540; 1 drivers +v0x2b5d820_0 .net "B", 0 0, L_0x2c842d0; 1 drivers +v0x2b5d8d0_0 .net "BornB", 0 0, L_0x2c80ff0; 1 drivers +v0x2b5d990_0 .net "CINandAxorB", 0 0, L_0x2c83c80; 1 drivers +v0x2b5da10_0 .alias "Command", 2 0, v0x2bc67a0_0; +v0x2b5da90_0 .net *"_s3", 0 0, L_0x2c812c0; 1 drivers +v0x2b5db10_0 .net *"_s5", 0 0, L_0x2c814a0; 1 drivers +v0x2b5dbb0_0 .net "carryin", 0 0, L_0x2c84400; 1 drivers +v0x2b5dc50_0 .net "carryout", 0 0, L_0x2c83d70; 1 drivers +v0x2b5dcf0_0 .net "nB", 0 0, L_0x2c80be0; 1 drivers +v0x2b5dda0_0 .net "nCmd2", 0 0, L_0x2c81220; 1 drivers +v0x2b5dea0_0 .net "subtract", 0 0, L_0x2c81360; 1 drivers +L_0x2c81180 .part v0x2bc78e0_0, 0, 1; +L_0x2c812c0 .part v0x2bc78e0_0, 2, 1; +L_0x2c814a0 .part v0x2bc78e0_0, 0, 1; +S_0x2b5d000 .scope module, "mux0" "TwoInMux" 3 105, 3 8, S_0x2b5cf10; + .timescale -9 -12; +L_0x2c80d70/d .functor NOT 1, L_0x2c81180, C4<0>, C4<0>, C4<0>; +L_0x2c80d70 .delay (10000,10000,10000) L_0x2c80d70/d; +L_0x2c80e10/d .functor AND 1, L_0x2c842d0, L_0x2c80d70, C4<1>, C4<1>; +L_0x2c80e10 .delay (20000,20000,20000) L_0x2c80e10/d; +L_0x2c80f00/d .functor AND 1, L_0x2c80be0, L_0x2c81180, C4<1>, C4<1>; +L_0x2c80f00 .delay (20000,20000,20000) L_0x2c80f00/d; +L_0x2c80ff0/d .functor OR 1, L_0x2c80e10, L_0x2c80f00, C4<0>, C4<0>; +L_0x2c80ff0 .delay (20000,20000,20000) L_0x2c80ff0/d; +v0x2b5d0f0_0 .net "S", 0 0, L_0x2c81180; 1 drivers +v0x2b5d190_0 .alias "in0", 0 0, v0x2b5d820_0; +v0x2b5d230_0 .alias "in1", 0 0, v0x2b5dcf0_0; +v0x2b5d2d0_0 .net "nS", 0 0, L_0x2c80d70; 1 drivers +v0x2b5d380_0 .net "out0", 0 0, L_0x2c80e10; 1 drivers +v0x2b5d420_0 .net "out1", 0 0, L_0x2c80f00; 1 drivers +v0x2b5d500_0 .alias "outfinal", 0 0, v0x2b5d8d0_0; +S_0x2b5bc00 .scope generate, "addbits[3]" "addbits[3]" 3 230, 3 230, S_0x2851a90; + .timescale -9 -12; +P_0x2b5b618 .param/l "i" 3 230, +C4<011>; +S_0x2b5bd70 .scope module, "attempt" "MiddleAddSubSLT" 3 232, 3 89, S_0x2b5bc00; + .timescale -9 -12; +L_0x2c84270/d .functor NOT 1, L_0x2c85730, C4<0>, C4<0>, C4<0>; +L_0x2c84270 .delay (10000,10000,10000) L_0x2c84270/d; +L_0x2c84a10/d .functor NOT 1, L_0x2c84ab0, C4<0>, C4<0>, C4<0>; +L_0x2c84a10 .delay (10000,10000,10000) L_0x2c84a10/d; +L_0x2c84b50/d .functor AND 1, L_0x2c84c90, L_0x2c84a10, C4<1>, C4<1>; +L_0x2c84b50 .delay (20000,20000,20000) L_0x2c84b50/d; +L_0x2c84d30/d .functor XOR 1, L_0x2c85600, L_0x2c847e0, C4<0>, C4<0>; +L_0x2c84d30 .delay (40000,40000,40000) L_0x2c84d30/d; +L_0x2c84e20/d .functor XOR 1, L_0x2c84d30, L_0x2c85860, C4<0>, C4<0>; +L_0x2c84e20 .delay (40000,40000,40000) L_0x2c84e20/d; +L_0x2c84f10/d .functor AND 1, L_0x2c85600, L_0x2c847e0, C4<1>, C4<1>; +L_0x2c84f10 .delay (20000,20000,20000) L_0x2c84f10/d; +L_0x2c85080/d .functor AND 1, L_0x2c84d30, L_0x2c85860, C4<1>, C4<1>; +L_0x2c85080 .delay (20000,20000,20000) L_0x2c85080/d; +L_0x2c85170/d .functor OR 1, L_0x2c84f10, L_0x2c85080, C4<0>, C4<0>; +L_0x2c85170 .delay (20000,20000,20000) L_0x2c85170/d; +v0x2b5c400_0 .net "A", 0 0, L_0x2c85600; 1 drivers +v0x2b5c4c0_0 .net "AandB", 0 0, L_0x2c84f10; 1 drivers +v0x2b5c560_0 .net "AddSubSLTSum", 0 0, L_0x2c84e20; 1 drivers +v0x2b5c600_0 .net "AxorB", 0 0, L_0x2c84d30; 1 drivers +v0x2b5c680_0 .net "B", 0 0, L_0x2c85730; 1 drivers +v0x2b5c730_0 .net "BornB", 0 0, L_0x2c847e0; 1 drivers +v0x2b5c7f0_0 .net "CINandAxorB", 0 0, L_0x2c85080; 1 drivers +v0x2b5c870_0 .alias "Command", 2 0, v0x2bc67a0_0; +v0x2b5c8f0_0 .net *"_s3", 0 0, L_0x2c84ab0; 1 drivers +v0x2b5c970_0 .net *"_s5", 0 0, L_0x2c84c90; 1 drivers +v0x2b5ca10_0 .net "carryin", 0 0, L_0x2c85860; 1 drivers +v0x2b5cab0_0 .net "carryout", 0 0, L_0x2c85170; 1 drivers +v0x2b5cb50_0 .net "nB", 0 0, L_0x2c84270; 1 drivers +v0x2b5cc00_0 .net "nCmd2", 0 0, L_0x2c84a10; 1 drivers +v0x2b5cd00_0 .net "subtract", 0 0, L_0x2c84b50; 1 drivers +L_0x2c84970 .part v0x2bc78e0_0, 0, 1; +L_0x2c84ab0 .part v0x2bc78e0_0, 2, 1; +L_0x2c84c90 .part v0x2bc78e0_0, 0, 1; +S_0x2b5be60 .scope module, "mux0" "TwoInMux" 3 105, 3 8, S_0x2b5bd70; + .timescale -9 -12; +L_0x2c845a0/d .functor NOT 1, L_0x2c84970, C4<0>, C4<0>, C4<0>; +L_0x2c845a0 .delay (10000,10000,10000) L_0x2c845a0/d; +L_0x2c84600/d .functor AND 1, L_0x2c85730, L_0x2c845a0, C4<1>, C4<1>; +L_0x2c84600 .delay (20000,20000,20000) L_0x2c84600/d; +L_0x2c846f0/d .functor AND 1, L_0x2c84270, L_0x2c84970, C4<1>, C4<1>; +L_0x2c846f0 .delay (20000,20000,20000) L_0x2c846f0/d; +L_0x2c847e0/d .functor OR 1, L_0x2c84600, L_0x2c846f0, C4<0>, C4<0>; +L_0x2c847e0 .delay (20000,20000,20000) L_0x2c847e0/d; +v0x2b5bf50_0 .net "S", 0 0, L_0x2c84970; 1 drivers +v0x2b5bff0_0 .alias "in0", 0 0, v0x2b5c680_0; +v0x2b5c090_0 .alias "in1", 0 0, v0x2b5cb50_0; +v0x2b5c130_0 .net "nS", 0 0, L_0x2c845a0; 1 drivers +v0x2b5c1e0_0 .net "out0", 0 0, L_0x2c84600; 1 drivers +v0x2b5c280_0 .net "out1", 0 0, L_0x2c846f0; 1 drivers +v0x2b5c360_0 .alias "outfinal", 0 0, v0x2b5c730_0; +S_0x2b5aa60 .scope generate, "addbits[4]" "addbits[4]" 3 230, 3 230, S_0x2851a90; + .timescale -9 -12; +P_0x2b5a478 .param/l "i" 3 230, +C4<0100>; +S_0x2b5abd0 .scope module, "attempt" "MiddleAddSubSLT" 3 232, 3 89, S_0x2b5aa60; + .timescale -9 -12; +L_0x2c856a0/d .functor NOT 1, L_0x2c86970, C4<0>, C4<0>, C4<0>; +L_0x2c856a0 .delay (10000,10000,10000) L_0x2c856a0/d; +L_0x2c85ef0/d .functor NOT 1, L_0x2c85f90, C4<0>, C4<0>, C4<0>; +L_0x2c85ef0 .delay (10000,10000,10000) L_0x2c85ef0/d; +L_0x2c86030/d .functor AND 1, L_0x2c86170, L_0x2c85ef0, C4<1>, C4<1>; +L_0x2c86030 .delay (20000,20000,20000) L_0x2c86030/d; +L_0x2c86210/d .functor XOR 1, L_0x2c86a70, L_0x2c85cc0, C4<0>, C4<0>; +L_0x2c86210 .delay (40000,40000,40000) L_0x2c86210/d; +L_0x2c86300/d .functor XOR 1, L_0x2c86210, L_0x2c86c60, C4<0>, C4<0>; +L_0x2c86300 .delay (40000,40000,40000) L_0x2c86300/d; +L_0x2c863f0/d .functor AND 1, L_0x2c86a70, L_0x2c85cc0, C4<1>, C4<1>; +L_0x2c863f0 .delay (20000,20000,20000) L_0x2c863f0/d; +L_0x2c86560/d .functor AND 1, L_0x2c86210, L_0x2c86c60, C4<1>, C4<1>; +L_0x2c86560 .delay (20000,20000,20000) L_0x2c86560/d; +L_0x2c86650/d .functor OR 1, L_0x2c863f0, L_0x2c86560, C4<0>, C4<0>; +L_0x2c86650 .delay (20000,20000,20000) L_0x2c86650/d; +v0x2b5b260_0 .net "A", 0 0, L_0x2c86a70; 1 drivers +v0x2b5b320_0 .net "AandB", 0 0, L_0x2c863f0; 1 drivers +v0x2b5b3c0_0 .net "AddSubSLTSum", 0 0, L_0x2c86300; 1 drivers +v0x2b5b460_0 .net "AxorB", 0 0, L_0x2c86210; 1 drivers +v0x2b5b4e0_0 .net "B", 0 0, L_0x2c86970; 1 drivers +v0x2b5b590_0 .net "BornB", 0 0, L_0x2c85cc0; 1 drivers +v0x2b5b650_0 .net "CINandAxorB", 0 0, L_0x2c86560; 1 drivers +v0x2b5b6d0_0 .alias "Command", 2 0, v0x2bc67a0_0; +v0x2b5b750_0 .net *"_s3", 0 0, L_0x2c85f90; 1 drivers +v0x2b5b7d0_0 .net *"_s5", 0 0, L_0x2c86170; 1 drivers +v0x2b5b870_0 .net "carryin", 0 0, L_0x2c86c60; 1 drivers +v0x2b5b910_0 .net "carryout", 0 0, L_0x2c86650; 1 drivers +v0x2b5b9b0_0 .net "nB", 0 0, L_0x2c856a0; 1 drivers +v0x2b5ba60_0 .net "nCmd2", 0 0, L_0x2c85ef0; 1 drivers +v0x2b5bb60_0 .net "subtract", 0 0, L_0x2c86030; 1 drivers +L_0x2c85e50 .part v0x2bc78e0_0, 0, 1; +L_0x2c85f90 .part v0x2bc78e0_0, 2, 1; +L_0x2c86170 .part v0x2bc78e0_0, 0, 1; +S_0x2b5acc0 .scope module, "mux0" "TwoInMux" 3 105, 3 8, S_0x2b5abd0; + .timescale -9 -12; +L_0x2c85a40/d .functor NOT 1, L_0x2c85e50, C4<0>, C4<0>, C4<0>; +L_0x2c85a40 .delay (10000,10000,10000) L_0x2c85a40/d; +L_0x2c85ae0/d .functor AND 1, L_0x2c86970, L_0x2c85a40, C4<1>, C4<1>; +L_0x2c85ae0 .delay (20000,20000,20000) L_0x2c85ae0/d; +L_0x2c85bd0/d .functor AND 1, L_0x2c856a0, L_0x2c85e50, C4<1>, C4<1>; +L_0x2c85bd0 .delay (20000,20000,20000) L_0x2c85bd0/d; +L_0x2c85cc0/d .functor OR 1, L_0x2c85ae0, L_0x2c85bd0, C4<0>, C4<0>; +L_0x2c85cc0 .delay (20000,20000,20000) L_0x2c85cc0/d; +v0x2b5adb0_0 .net "S", 0 0, L_0x2c85e50; 1 drivers +v0x2b5ae50_0 .alias "in0", 0 0, v0x2b5b4e0_0; +v0x2b5aef0_0 .alias "in1", 0 0, v0x2b5b9b0_0; +v0x2b5af90_0 .net "nS", 0 0, L_0x2c85a40; 1 drivers +v0x2b5b040_0 .net "out0", 0 0, L_0x2c85ae0; 1 drivers +v0x2b5b0e0_0 .net "out1", 0 0, L_0x2c85bd0; 1 drivers +v0x2b5b1c0_0 .alias "outfinal", 0 0, v0x2b5b590_0; +S_0x2b598c0 .scope generate, "addbits[5]" "addbits[5]" 3 230, 3 230, S_0x2851a90; + .timescale -9 -12; +P_0x2b592d8 .param/l "i" 3 230, +C4<0101>; +S_0x2b59a30 .scope module, "attempt" "MiddleAddSubSLT" 3 232, 3 89, S_0x2b598c0; + .timescale -9 -12; +L_0x2c844a0/d .functor NOT 1, L_0x2c87e10, C4<0>, C4<0>, C4<0>; +L_0x2c844a0 .delay (10000,10000,10000) L_0x2c844a0/d; +L_0x2c87390/d .functor NOT 1, L_0x2c87430, C4<0>, C4<0>, C4<0>; +L_0x2c87390 .delay (10000,10000,10000) L_0x2c87390/d; +L_0x2c874d0/d .functor AND 1, L_0x2c87610, L_0x2c87390, C4<1>, C4<1>; +L_0x2c874d0 .delay (20000,20000,20000) L_0x2c874d0/d; +L_0x2c876b0/d .functor XOR 1, L_0x2c87f40, L_0x2c87160, C4<0>, C4<0>; +L_0x2c876b0 .delay (40000,40000,40000) L_0x2c876b0/d; +L_0x2c877a0/d .functor XOR 1, L_0x2c876b0, L_0x2c88160, C4<0>, C4<0>; +L_0x2c877a0 .delay (40000,40000,40000) L_0x2c877a0/d; +L_0x2c87890/d .functor AND 1, L_0x2c87f40, L_0x2c87160, C4<1>, C4<1>; +L_0x2c87890 .delay (20000,20000,20000) L_0x2c87890/d; +L_0x2c87a00/d .functor AND 1, L_0x2c876b0, L_0x2c88160, C4<1>, C4<1>; +L_0x2c87a00 .delay (20000,20000,20000) L_0x2c87a00/d; +L_0x2c87af0/d .functor OR 1, L_0x2c87890, L_0x2c87a00, C4<0>, C4<0>; +L_0x2c87af0 .delay (20000,20000,20000) L_0x2c87af0/d; +v0x2b5a0c0_0 .net "A", 0 0, L_0x2c87f40; 1 drivers +v0x2b5a180_0 .net "AandB", 0 0, L_0x2c87890; 1 drivers +v0x2b5a220_0 .net "AddSubSLTSum", 0 0, L_0x2c877a0; 1 drivers +v0x2b5a2c0_0 .net "AxorB", 0 0, L_0x2c876b0; 1 drivers +v0x2b5a340_0 .net "B", 0 0, L_0x2c87e10; 1 drivers +v0x2b5a3f0_0 .net "BornB", 0 0, L_0x2c87160; 1 drivers +v0x2b5a4b0_0 .net "CINandAxorB", 0 0, L_0x2c87a00; 1 drivers +v0x2b5a530_0 .alias "Command", 2 0, v0x2bc67a0_0; +v0x2b5a5b0_0 .net *"_s3", 0 0, L_0x2c87430; 1 drivers +v0x2b5a630_0 .net *"_s5", 0 0, L_0x2c87610; 1 drivers +v0x2b5a6d0_0 .net "carryin", 0 0, L_0x2c88160; 1 drivers +v0x2b5a770_0 .net "carryout", 0 0, L_0x2c87af0; 1 drivers +v0x2b5a810_0 .net "nB", 0 0, L_0x2c844a0; 1 drivers +v0x2b5a8c0_0 .net "nCmd2", 0 0, L_0x2c87390; 1 drivers +v0x2b5a9c0_0 .net "subtract", 0 0, L_0x2c874d0; 1 drivers +L_0x2c872f0 .part v0x2bc78e0_0, 0, 1; +L_0x2c87430 .part v0x2bc78e0_0, 2, 1; +L_0x2c87610 .part v0x2bc78e0_0, 0, 1; +S_0x2b59b20 .scope module, "mux0" "TwoInMux" 3 105, 3 8, S_0x2b59a30; + .timescale -9 -12; +L_0x2c86ee0/d .functor NOT 1, L_0x2c872f0, C4<0>, C4<0>, C4<0>; +L_0x2c86ee0 .delay (10000,10000,10000) L_0x2c86ee0/d; +L_0x2c86f80/d .functor AND 1, L_0x2c87e10, L_0x2c86ee0, C4<1>, C4<1>; +L_0x2c86f80 .delay (20000,20000,20000) L_0x2c86f80/d; +L_0x2c87070/d .functor AND 1, L_0x2c844a0, L_0x2c872f0, C4<1>, C4<1>; +L_0x2c87070 .delay (20000,20000,20000) L_0x2c87070/d; +L_0x2c87160/d .functor OR 1, L_0x2c86f80, L_0x2c87070, C4<0>, C4<0>; +L_0x2c87160 .delay (20000,20000,20000) L_0x2c87160/d; +v0x2b59c10_0 .net "S", 0 0, L_0x2c872f0; 1 drivers +v0x2b59cb0_0 .alias "in0", 0 0, v0x2b5a340_0; +v0x2b59d50_0 .alias "in1", 0 0, v0x2b5a810_0; +v0x2b59df0_0 .net "nS", 0 0, L_0x2c86ee0; 1 drivers +v0x2b59ea0_0 .net "out0", 0 0, L_0x2c86f80; 1 drivers +v0x2b59f40_0 .net "out1", 0 0, L_0x2c87070; 1 drivers +v0x2b5a020_0 .alias "outfinal", 0 0, v0x2b5a3f0_0; +S_0x2b58720 .scope generate, "addbits[6]" "addbits[6]" 3 230, 3 230, S_0x2851a90; + .timescale -9 -12; +P_0x2b58138 .param/l "i" 3 230, +C4<0110>; +S_0x2b58890 .scope module, "attempt" "MiddleAddSubSLT" 3 232, 3 89, S_0x2b58720; + .timescale -9 -12; +L_0x2c87fe0/d .functor NOT 1, L_0x2c89200, C4<0>, C4<0>, C4<0>; +L_0x2c87fe0 .delay (10000,10000,10000) L_0x2c87fe0/d; +L_0x2c88780/d .functor NOT 1, L_0x2c88820, C4<0>, C4<0>, C4<0>; +L_0x2c88780 .delay (10000,10000,10000) L_0x2c88780/d; +L_0x2c888c0/d .functor AND 1, L_0x2c88a00, L_0x2c88780, C4<1>, C4<1>; +L_0x2c888c0 .delay (20000,20000,20000) L_0x2c888c0/d; +L_0x2c88aa0/d .functor XOR 1, L_0x2c89310, L_0x2c88550, C4<0>, C4<0>; +L_0x2c88aa0 .delay (40000,40000,40000) L_0x2c88aa0/d; +L_0x2c88b90/d .functor XOR 1, L_0x2c88aa0, L_0x2c89560, C4<0>, C4<0>; +L_0x2c88b90 .delay (40000,40000,40000) L_0x2c88b90/d; +L_0x2c88c80/d .functor AND 1, L_0x2c89310, L_0x2c88550, C4<1>, C4<1>; +L_0x2c88c80 .delay (20000,20000,20000) L_0x2c88c80/d; +L_0x2c88df0/d .functor AND 1, L_0x2c88aa0, L_0x2c89560, C4<1>, C4<1>; +L_0x2c88df0 .delay (20000,20000,20000) L_0x2c88df0/d; +L_0x2c88ee0/d .functor OR 1, L_0x2c88c80, L_0x2c88df0, C4<0>, C4<0>; +L_0x2c88ee0 .delay (20000,20000,20000) L_0x2c88ee0/d; +v0x2b58f20_0 .net "A", 0 0, L_0x2c89310; 1 drivers +v0x2b58fe0_0 .net "AandB", 0 0, L_0x2c88c80; 1 drivers +v0x2b59080_0 .net "AddSubSLTSum", 0 0, L_0x2c88b90; 1 drivers +v0x2b59120_0 .net "AxorB", 0 0, L_0x2c88aa0; 1 drivers +v0x2b591a0_0 .net "B", 0 0, L_0x2c89200; 1 drivers +v0x2b59250_0 .net "BornB", 0 0, L_0x2c88550; 1 drivers +v0x2b59310_0 .net "CINandAxorB", 0 0, L_0x2c88df0; 1 drivers +v0x2b59390_0 .alias "Command", 2 0, v0x2bc67a0_0; +v0x2b59410_0 .net *"_s3", 0 0, L_0x2c88820; 1 drivers +v0x2b59490_0 .net *"_s5", 0 0, L_0x2c88a00; 1 drivers +v0x2b59530_0 .net "carryin", 0 0, L_0x2c89560; 1 drivers +v0x2b595d0_0 .net "carryout", 0 0, L_0x2c88ee0; 1 drivers +v0x2b59670_0 .net "nB", 0 0, L_0x2c87fe0; 1 drivers +v0x2b59720_0 .net "nCmd2", 0 0, L_0x2c88780; 1 drivers +v0x2b59820_0 .net "subtract", 0 0, L_0x2c888c0; 1 drivers +L_0x2c886e0 .part v0x2bc78e0_0, 0, 1; +L_0x2c88820 .part v0x2bc78e0_0, 2, 1; +L_0x2c88a00 .part v0x2bc78e0_0, 0, 1; +S_0x2b58980 .scope module, "mux0" "TwoInMux" 3 105, 3 8, S_0x2b58890; + .timescale -9 -12; +L_0x2c88350/d .functor NOT 1, L_0x2c886e0, C4<0>, C4<0>, C4<0>; +L_0x2c88350 .delay (10000,10000,10000) L_0x2c88350/d; +L_0x2c883b0/d .functor AND 1, L_0x2c89200, L_0x2c88350, C4<1>, C4<1>; +L_0x2c883b0 .delay (20000,20000,20000) L_0x2c883b0/d; +L_0x2c88460/d .functor AND 1, L_0x2c87fe0, L_0x2c886e0, C4<1>, C4<1>; +L_0x2c88460 .delay (20000,20000,20000) L_0x2c88460/d; +L_0x2c88550/d .functor OR 1, L_0x2c883b0, L_0x2c88460, C4<0>, C4<0>; +L_0x2c88550 .delay (20000,20000,20000) L_0x2c88550/d; +v0x2b58a70_0 .net "S", 0 0, L_0x2c886e0; 1 drivers +v0x2b58b10_0 .alias "in0", 0 0, v0x2b591a0_0; +v0x2b58bb0_0 .alias "in1", 0 0, v0x2b59670_0; +v0x2b58c50_0 .net "nS", 0 0, L_0x2c88350; 1 drivers +v0x2b58d00_0 .net "out0", 0 0, L_0x2c883b0; 1 drivers +v0x2b58da0_0 .net "out1", 0 0, L_0x2c88460; 1 drivers +v0x2b58e80_0 .alias "outfinal", 0 0, v0x2b59250_0; +S_0x2b57580 .scope generate, "addbits[7]" "addbits[7]" 3 230, 3 230, S_0x2851a90; + .timescale -9 -12; +P_0x2b56f98 .param/l "i" 3 230, +C4<0111>; +S_0x2b576f0 .scope module, "attempt" "MiddleAddSubSLT" 3 232, 3 89, S_0x2b57580; + .timescale -9 -12; +L_0x2c892a0/d .functor NOT 1, L_0x2c8a600, C4<0>, C4<0>, C4<0>; +L_0x2c892a0 .delay (10000,10000,10000) L_0x2c892a0/d; +L_0x2c89b80/d .functor NOT 1, L_0x2c89c20, C4<0>, C4<0>, C4<0>; +L_0x2c89b80 .delay (10000,10000,10000) L_0x2c89b80/d; +L_0x2c89cc0/d .functor AND 1, L_0x2c89e00, L_0x2c89b80, C4<1>, C4<1>; +L_0x2c89cc0 .delay (20000,20000,20000) L_0x2c89cc0/d; +L_0x2c89ea0/d .functor XOR 1, L_0x2c8a740, L_0x2c89950, C4<0>, C4<0>; +L_0x2c89ea0 .delay (40000,40000,40000) L_0x2c89ea0/d; +L_0x2c89f90/d .functor XOR 1, L_0x2c89ea0, L_0x2c8a930, C4<0>, C4<0>; +L_0x2c89f90 .delay (40000,40000,40000) L_0x2c89f90/d; +L_0x2c8a080/d .functor AND 1, L_0x2c8a740, L_0x2c89950, C4<1>, C4<1>; +L_0x2c8a080 .delay (20000,20000,20000) L_0x2c8a080/d; +L_0x2c8a1f0/d .functor AND 1, L_0x2c89ea0, L_0x2c8a930, C4<1>, C4<1>; +L_0x2c8a1f0 .delay (20000,20000,20000) L_0x2c8a1f0/d; +L_0x2c8a2e0/d .functor OR 1, L_0x2c8a080, L_0x2c8a1f0, C4<0>, C4<0>; +L_0x2c8a2e0 .delay (20000,20000,20000) L_0x2c8a2e0/d; +v0x2b57d80_0 .net "A", 0 0, L_0x2c8a740; 1 drivers +v0x2b57e40_0 .net "AandB", 0 0, L_0x2c8a080; 1 drivers +v0x2b57ee0_0 .net "AddSubSLTSum", 0 0, L_0x2c89f90; 1 drivers +v0x2b57f80_0 .net "AxorB", 0 0, L_0x2c89ea0; 1 drivers +v0x2b58000_0 .net "B", 0 0, L_0x2c8a600; 1 drivers +v0x2b580b0_0 .net "BornB", 0 0, L_0x2c89950; 1 drivers +v0x2b58170_0 .net "CINandAxorB", 0 0, L_0x2c8a1f0; 1 drivers +v0x2b581f0_0 .alias "Command", 2 0, v0x2bc67a0_0; +v0x2b58270_0 .net *"_s3", 0 0, L_0x2c89c20; 1 drivers +v0x2b582f0_0 .net *"_s5", 0 0, L_0x2c89e00; 1 drivers +v0x2b58390_0 .net "carryin", 0 0, L_0x2c8a930; 1 drivers +v0x2b58430_0 .net "carryout", 0 0, L_0x2c8a2e0; 1 drivers +v0x2b584d0_0 .net "nB", 0 0, L_0x2c892a0; 1 drivers +v0x2b58580_0 .net "nCmd2", 0 0, L_0x2c89b80; 1 drivers +v0x2b58680_0 .net "subtract", 0 0, L_0x2c89cc0; 1 drivers +L_0x2c89ae0 .part v0x2bc78e0_0, 0, 1; +L_0x2c89c20 .part v0x2bc78e0_0, 2, 1; +L_0x2c89e00 .part v0x2bc78e0_0, 0, 1; +S_0x2b577e0 .scope module, "mux0" "TwoInMux" 3 105, 3 8, S_0x2b576f0; + .timescale -9 -12; +L_0x2c89450/d .functor NOT 1, L_0x2c89ae0, C4<0>, C4<0>, C4<0>; +L_0x2c89450 .delay (10000,10000,10000) L_0x2c89450/d; +L_0x2c89770/d .functor AND 1, L_0x2c8a600, L_0x2c89450, C4<1>, C4<1>; +L_0x2c89770 .delay (20000,20000,20000) L_0x2c89770/d; +L_0x2c89860/d .functor AND 1, L_0x2c892a0, L_0x2c89ae0, C4<1>, C4<1>; +L_0x2c89860 .delay (20000,20000,20000) L_0x2c89860/d; +L_0x2c89950/d .functor OR 1, L_0x2c89770, L_0x2c89860, C4<0>, C4<0>; +L_0x2c89950 .delay (20000,20000,20000) L_0x2c89950/d; +v0x2b578d0_0 .net "S", 0 0, L_0x2c89ae0; 1 drivers +v0x2b57970_0 .alias "in0", 0 0, v0x2b58000_0; +v0x2b57a10_0 .alias "in1", 0 0, v0x2b584d0_0; +v0x2b57ab0_0 .net "nS", 0 0, L_0x2c89450; 1 drivers +v0x2b57b60_0 .net "out0", 0 0, L_0x2c89770; 1 drivers +v0x2b57c00_0 .net "out1", 0 0, L_0x2c89860; 1 drivers +v0x2b57ce0_0 .alias "outfinal", 0 0, v0x2b580b0_0; +S_0x2b563e0 .scope generate, "addbits[8]" "addbits[8]" 3 230, 3 230, S_0x2851a90; + .timescale -9 -12; +P_0x2b55df8 .param/l "i" 3 230, +C4<01000>; +S_0x2b56550 .scope module, "attempt" "MiddleAddSubSLT" 3 232, 3 89, S_0x2b563e0; + .timescale -9 -12; +L_0x2c8a7e0/d .functor NOT 1, L_0x2c8ba60, C4<0>, C4<0>, C4<0>; +L_0x2c8a7e0 .delay (10000,10000,10000) L_0x2c8a7e0/d; +L_0x2c8afa0/d .functor NOT 1, L_0x2c8b040, C4<0>, C4<0>, C4<0>; +L_0x2c8afa0 .delay (10000,10000,10000) L_0x2c8afa0/d; +L_0x2c8b0e0/d .functor AND 1, L_0x2c8b220, L_0x2c8afa0, C4<1>, C4<1>; +L_0x2c8b0e0 .delay (20000,20000,20000) L_0x2c8b0e0/d; +L_0x2c8b2c0/d .functor XOR 1, L_0x2c8bbd0, L_0x2c8ad70, C4<0>, C4<0>; +L_0x2c8b2c0 .delay (40000,40000,40000) L_0x2c8b2c0/d; +L_0x2c8b3b0/d .functor XOR 1, L_0x2c8b2c0, L_0x2c8bdf0, C4<0>, C4<0>; +L_0x2c8b3b0 .delay (40000,40000,40000) L_0x2c8b3b0/d; +L_0x2c8b4a0/d .functor AND 1, L_0x2c8bbd0, L_0x2c8ad70, C4<1>, C4<1>; +L_0x2c8b4a0 .delay (20000,20000,20000) L_0x2c8b4a0/d; +L_0x2c8b610/d .functor AND 1, L_0x2c8b2c0, L_0x2c8bdf0, C4<1>, C4<1>; +L_0x2c8b610 .delay (20000,20000,20000) L_0x2c8b610/d; +L_0x2c8b720/d .functor OR 1, L_0x2c8b4a0, L_0x2c8b610, C4<0>, C4<0>; +L_0x2c8b720 .delay (20000,20000,20000) L_0x2c8b720/d; +v0x2b56be0_0 .net "A", 0 0, L_0x2c8bbd0; 1 drivers +v0x2b56ca0_0 .net "AandB", 0 0, L_0x2c8b4a0; 1 drivers +v0x2b56d40_0 .net "AddSubSLTSum", 0 0, L_0x2c8b3b0; 1 drivers +v0x2b56de0_0 .net "AxorB", 0 0, L_0x2c8b2c0; 1 drivers +v0x2b56e60_0 .net "B", 0 0, L_0x2c8ba60; 1 drivers +v0x2b56f10_0 .net "BornB", 0 0, L_0x2c8ad70; 1 drivers +v0x2b56fd0_0 .net "CINandAxorB", 0 0, L_0x2c8b610; 1 drivers +v0x2b57050_0 .alias "Command", 2 0, v0x2bc67a0_0; +v0x2b570d0_0 .net *"_s3", 0 0, L_0x2c8b040; 1 drivers +v0x2b57150_0 .net *"_s5", 0 0, L_0x2c8b220; 1 drivers +v0x2b571f0_0 .net "carryin", 0 0, L_0x2c8bdf0; 1 drivers +v0x2b57290_0 .net "carryout", 0 0, L_0x2c8b720; 1 drivers +v0x2b57330_0 .net "nB", 0 0, L_0x2c8a7e0; 1 drivers +v0x2b573e0_0 .net "nCmd2", 0 0, L_0x2c8afa0; 1 drivers +v0x2b574e0_0 .net "subtract", 0 0, L_0x2c8b0e0; 1 drivers +L_0x2c8af00 .part v0x2bc78e0_0, 0, 1; +L_0x2c8b040 .part v0x2bc78e0_0, 2, 1; +L_0x2c8b220 .part v0x2bc78e0_0, 0, 1; +S_0x2b56640 .scope module, "mux0" "TwoInMux" 3 105, 3 8, S_0x2b56550; + .timescale -9 -12; +L_0x2c8ab30/d .functor NOT 1, L_0x2c8af00, C4<0>, C4<0>, C4<0>; +L_0x2c8ab30 .delay (10000,10000,10000) L_0x2c8ab30/d; +L_0x2c8ab90/d .functor AND 1, L_0x2c8ba60, L_0x2c8ab30, C4<1>, C4<1>; +L_0x2c8ab90 .delay (20000,20000,20000) L_0x2c8ab90/d; +L_0x2c8ac80/d .functor AND 1, L_0x2c8a7e0, L_0x2c8af00, C4<1>, C4<1>; +L_0x2c8ac80 .delay (20000,20000,20000) L_0x2c8ac80/d; +L_0x2c8ad70/d .functor OR 1, L_0x2c8ab90, L_0x2c8ac80, C4<0>, C4<0>; +L_0x2c8ad70 .delay (20000,20000,20000) L_0x2c8ad70/d; +v0x2b56730_0 .net "S", 0 0, L_0x2c8af00; 1 drivers +v0x2b567d0_0 .alias "in0", 0 0, v0x2b56e60_0; +v0x2b56870_0 .alias "in1", 0 0, v0x2b57330_0; +v0x2b56910_0 .net "nS", 0 0, L_0x2c8ab30; 1 drivers +v0x2b569c0_0 .net "out0", 0 0, L_0x2c8ab90; 1 drivers +v0x2b56a60_0 .net "out1", 0 0, L_0x2c8ac80; 1 drivers +v0x2b56b40_0 .alias "outfinal", 0 0, v0x2b56f10_0; +S_0x2b55240 .scope generate, "addbits[9]" "addbits[9]" 3 230, 3 230, S_0x2851a90; + .timescale -9 -12; +P_0x2b54c58 .param/l "i" 3 230, +C4<01001>; +S_0x2b553b0 .scope module, "attempt" "MiddleAddSubSLT" 3 232, 3 89, S_0x2b55240; + .timescale -9 -12; +L_0x2c8aac0/d .functor NOT 1, L_0x2c8d220, C4<0>, C4<0>, C4<0>; +L_0x2c8aac0 .delay (10000,10000,10000) L_0x2c8aac0/d; +L_0x2c8c5b0/d .functor NOT 1, L_0x2c8c670, C4<0>, C4<0>, C4<0>; +L_0x2c8c5b0 .delay (10000,10000,10000) L_0x2c8c5b0/d; +L_0x2c8c710/d .functor AND 1, L_0x2c8c850, L_0x2c8c5b0, C4<1>, C4<1>; +L_0x2c8c710 .delay (20000,20000,20000) L_0x2c8c710/d; +L_0x2c8c8f0/d .functor XOR 1, L_0x2c8c190, L_0x2c8c340, C4<0>, C4<0>; +L_0x2c8c8f0 .delay (40000,40000,40000) L_0x2c8c8f0/d; +L_0x2c8c9e0/d .functor XOR 1, L_0x2c8c8f0, L_0x2c8d350, C4<0>, C4<0>; +L_0x2c8c9e0 .delay (40000,40000,40000) L_0x2c8c9e0/d; +L_0x2c8cad0/d .functor AND 1, L_0x2c8c190, L_0x2c8c340, C4<1>, C4<1>; +L_0x2c8cad0 .delay (20000,20000,20000) L_0x2c8cad0/d; +L_0x2c8cc40/d .functor AND 1, L_0x2c8c8f0, L_0x2c8d350, C4<1>, C4<1>; +L_0x2c8cc40 .delay (20000,20000,20000) L_0x2c8cc40/d; +L_0x2c8cd30/d .functor OR 1, L_0x2c8cad0, L_0x2c8cc40, C4<0>, C4<0>; +L_0x2c8cd30 .delay (20000,20000,20000) L_0x2c8cd30/d; +v0x2b55a40_0 .net "A", 0 0, L_0x2c8c190; 1 drivers +v0x2b55b00_0 .net "AandB", 0 0, L_0x2c8cad0; 1 drivers +v0x2b55ba0_0 .net "AddSubSLTSum", 0 0, L_0x2c8c9e0; 1 drivers +v0x2b55c40_0 .net "AxorB", 0 0, L_0x2c8c8f0; 1 drivers +v0x2b55cc0_0 .net "B", 0 0, L_0x2c8d220; 1 drivers +v0x2b55d70_0 .net "BornB", 0 0, L_0x2c8c340; 1 drivers +v0x2b55e30_0 .net "CINandAxorB", 0 0, L_0x2c8cc40; 1 drivers +v0x2b55eb0_0 .alias "Command", 2 0, v0x2bc67a0_0; +v0x2b55f30_0 .net *"_s3", 0 0, L_0x2c8c670; 1 drivers +v0x2b55fb0_0 .net *"_s5", 0 0, L_0x2c8c850; 1 drivers +v0x2b56050_0 .net "carryin", 0 0, L_0x2c8d350; 1 drivers +v0x2b560f0_0 .net "carryout", 0 0, L_0x2c8cd30; 1 drivers +v0x2b56190_0 .net "nB", 0 0, L_0x2c8aac0; 1 drivers +v0x2b56240_0 .net "nCmd2", 0 0, L_0x2c8c5b0; 1 drivers +v0x2b56340_0 .net "subtract", 0 0, L_0x2c8c710; 1 drivers +L_0x2c8c510 .part v0x2bc78e0_0, 0, 1; +L_0x2c8c670 .part v0x2bc78e0_0, 2, 1; +L_0x2c8c850 .part v0x2bc78e0_0, 0, 1; +S_0x2b554a0 .scope module, "mux0" "TwoInMux" 3 105, 3 8, S_0x2b553b0; + .timescale -9 -12; +L_0x2c8bc70/d .functor NOT 1, L_0x2c8c510, C4<0>, C4<0>, C4<0>; +L_0x2c8bc70 .delay (10000,10000,10000) L_0x2c8bc70/d; +L_0x2c8bd30/d .functor AND 1, L_0x2c8d220, L_0x2c8bc70, C4<1>, C4<1>; +L_0x2c8bd30 .delay (20000,20000,20000) L_0x2c8bd30/d; +L_0x2c8c230/d .functor AND 1, L_0x2c8aac0, L_0x2c8c510, C4<1>, C4<1>; +L_0x2c8c230 .delay (20000,20000,20000) L_0x2c8c230/d; +L_0x2c8c340/d .functor OR 1, L_0x2c8bd30, L_0x2c8c230, C4<0>, C4<0>; +L_0x2c8c340 .delay (20000,20000,20000) L_0x2c8c340/d; +v0x2b55590_0 .net "S", 0 0, L_0x2c8c510; 1 drivers +v0x2b55630_0 .alias "in0", 0 0, v0x2b55cc0_0; +v0x2b556d0_0 .alias "in1", 0 0, v0x2b56190_0; +v0x2b55770_0 .net "nS", 0 0, L_0x2c8bc70; 1 drivers +v0x2b55820_0 .net "out0", 0 0, L_0x2c8bd30; 1 drivers +v0x2b558c0_0 .net "out1", 0 0, L_0x2c8c230; 1 drivers +v0x2b559a0_0 .alias "outfinal", 0 0, v0x2b55d70_0; +S_0x2b540a0 .scope generate, "addbits[10]" "addbits[10]" 3 230, 3 230, S_0x2851a90; + .timescale -9 -12; +P_0x2b53ab8 .param/l "i" 3 230, +C4<01010>; +S_0x2b54210 .scope module, "attempt" "MiddleAddSubSLT" 3 232, 3 89, S_0x2b540a0; + .timescale -9 -12; +L_0x2c8d070/d .functor NOT 1, L_0x2c8e760, C4<0>, C4<0>, C4<0>; +L_0x2c8d070 .delay (10000,10000,10000) L_0x2c8d070/d; +L_0x2c8dac0/d .functor NOT 1, L_0x2c8db80, C4<0>, C4<0>, C4<0>; +L_0x2c8dac0 .delay (10000,10000,10000) L_0x2c8dac0/d; +L_0x2c8dc20/d .functor AND 1, L_0x2c8dd60, L_0x2c8dac0, C4<1>, C4<1>; +L_0x2c8dc20 .delay (20000,20000,20000) L_0x2c8dc20/d; +L_0x2c8de00/d .functor XOR 1, L_0x2c8d4e0, L_0x2c8d850, C4<0>, C4<0>; +L_0x2c8de00 .delay (40000,40000,40000) L_0x2c8de00/d; +L_0x2c8def0/d .functor XOR 1, L_0x2c8de00, L_0x2c8e890, C4<0>, C4<0>; +L_0x2c8def0 .delay (40000,40000,40000) L_0x2c8def0/d; +L_0x2c8dfe0/d .functor AND 1, L_0x2c8d4e0, L_0x2c8d850, C4<1>, C4<1>; +L_0x2c8dfe0 .delay (20000,20000,20000) L_0x2c8dfe0/d; +L_0x2c8e150/d .functor AND 1, L_0x2c8de00, L_0x2c8e890, C4<1>, C4<1>; +L_0x2c8e150 .delay (20000,20000,20000) L_0x2c8e150/d; +L_0x2c8e240/d .functor OR 1, L_0x2c8dfe0, L_0x2c8e150, C4<0>, C4<0>; +L_0x2c8e240 .delay (20000,20000,20000) L_0x2c8e240/d; +v0x2b548a0_0 .net "A", 0 0, L_0x2c8d4e0; 1 drivers +v0x2b54960_0 .net "AandB", 0 0, L_0x2c8dfe0; 1 drivers +v0x2b54a00_0 .net "AddSubSLTSum", 0 0, L_0x2c8def0; 1 drivers +v0x2b54aa0_0 .net "AxorB", 0 0, L_0x2c8de00; 1 drivers +v0x2b54b20_0 .net "B", 0 0, L_0x2c8e760; 1 drivers +v0x2b54bd0_0 .net "BornB", 0 0, L_0x2c8d850; 1 drivers +v0x2b54c90_0 .net "CINandAxorB", 0 0, L_0x2c8e150; 1 drivers +v0x2b54d10_0 .alias "Command", 2 0, v0x2bc67a0_0; +v0x2b54d90_0 .net *"_s3", 0 0, L_0x2c8db80; 1 drivers +v0x2b54e10_0 .net *"_s5", 0 0, L_0x2c8dd60; 1 drivers +v0x2b54eb0_0 .net "carryin", 0 0, L_0x2c8e890; 1 drivers +v0x2b54f50_0 .net "carryout", 0 0, L_0x2c8e240; 1 drivers +v0x2b54ff0_0 .net "nB", 0 0, L_0x2c8d070; 1 drivers +v0x2b550a0_0 .net "nCmd2", 0 0, L_0x2c8dac0; 1 drivers +v0x2b551a0_0 .net "subtract", 0 0, L_0x2c8dc20; 1 drivers +L_0x2c8da20 .part v0x2bc78e0_0, 0, 1; +L_0x2c8db80 .part v0x2bc78e0_0, 2, 1; +L_0x2c8dd60 .part v0x2bc78e0_0, 0, 1; +S_0x2b54300 .scope module, "mux0" "TwoInMux" 3 105, 3 8, S_0x2b54210; + .timescale -9 -12; +L_0x2c8d5b0/d .functor NOT 1, L_0x2c8da20, C4<0>, C4<0>, C4<0>; +L_0x2c8d5b0 .delay (10000,10000,10000) L_0x2c8d5b0/d; +L_0x2c8d650/d .functor AND 1, L_0x2c8e760, L_0x2c8d5b0, C4<1>, C4<1>; +L_0x2c8d650 .delay (20000,20000,20000) L_0x2c8d650/d; +L_0x2c8d740/d .functor AND 1, L_0x2c8d070, L_0x2c8da20, C4<1>, C4<1>; +L_0x2c8d740 .delay (20000,20000,20000) L_0x2c8d740/d; +L_0x2c8d850/d .functor OR 1, L_0x2c8d650, L_0x2c8d740, C4<0>, C4<0>; +L_0x2c8d850 .delay (20000,20000,20000) L_0x2c8d850/d; +v0x2b543f0_0 .net "S", 0 0, L_0x2c8da20; 1 drivers +v0x2b54490_0 .alias "in0", 0 0, v0x2b54b20_0; +v0x2b54530_0 .alias "in1", 0 0, v0x2b54ff0_0; +v0x2b545d0_0 .net "nS", 0 0, L_0x2c8d5b0; 1 drivers +v0x2b54680_0 .net "out0", 0 0, L_0x2c8d650; 1 drivers +v0x2b54720_0 .net "out1", 0 0, L_0x2c8d740; 1 drivers +v0x2b54800_0 .alias "outfinal", 0 0, v0x2b54bd0_0; +S_0x2b52f00 .scope generate, "addbits[11]" "addbits[11]" 3 230, 3 230, S_0x2851a90; + .timescale -9 -12; +P_0x2b52918 .param/l "i" 3 230, +C4<01011>; +S_0x2b53070 .scope module, "attempt" "MiddleAddSubSLT" 3 232, 3 89, S_0x2b52f00; + .timescale -9 -12; +L_0x2c8e580/d .functor NOT 1, L_0x2c8fca0, C4<0>, C4<0>, C4<0>; +L_0x2c8e580 .delay (10000,10000,10000) L_0x2c8e580/d; +L_0x2c8efd0/d .functor NOT 1, L_0x2c8f090, C4<0>, C4<0>, C4<0>; +L_0x2c8efd0 .delay (10000,10000,10000) L_0x2c8efd0/d; +L_0x2c8f130/d .functor AND 1, L_0x2c8f270, L_0x2c8efd0, C4<1>, C4<1>; +L_0x2c8f130 .delay (20000,20000,20000) L_0x2c8f130/d; +L_0x2c8f310/d .functor XOR 1, L_0x2c8ea20, L_0x2c8ed60, C4<0>, C4<0>; +L_0x2c8f310 .delay (40000,40000,40000) L_0x2c8f310/d; +L_0x2c8f400/d .functor XOR 1, L_0x2c8f310, L_0x2c8fdd0, C4<0>, C4<0>; +L_0x2c8f400 .delay (40000,40000,40000) L_0x2c8f400/d; +L_0x2c8f4f0/d .functor AND 1, L_0x2c8ea20, L_0x2c8ed60, C4<1>, C4<1>; +L_0x2c8f4f0 .delay (20000,20000,20000) L_0x2c8f4f0/d; +L_0x2c8f660/d .functor AND 1, L_0x2c8f310, L_0x2c8fdd0, C4<1>, C4<1>; +L_0x2c8f660 .delay (20000,20000,20000) L_0x2c8f660/d; +L_0x2c8f750/d .functor OR 1, L_0x2c8f4f0, L_0x2c8f660, C4<0>, C4<0>; +L_0x2c8f750 .delay (20000,20000,20000) L_0x2c8f750/d; +v0x2b53700_0 .net "A", 0 0, L_0x2c8ea20; 1 drivers +v0x2b537c0_0 .net "AandB", 0 0, L_0x2c8f4f0; 1 drivers +v0x2b53860_0 .net "AddSubSLTSum", 0 0, L_0x2c8f400; 1 drivers +v0x2b53900_0 .net "AxorB", 0 0, L_0x2c8f310; 1 drivers +v0x2b53980_0 .net "B", 0 0, L_0x2c8fca0; 1 drivers +v0x2b53a30_0 .net "BornB", 0 0, L_0x2c8ed60; 1 drivers +v0x2b53af0_0 .net "CINandAxorB", 0 0, L_0x2c8f660; 1 drivers +v0x2b53b70_0 .alias "Command", 2 0, v0x2bc67a0_0; +v0x2b53bf0_0 .net *"_s3", 0 0, L_0x2c8f090; 1 drivers +v0x2b53c70_0 .net *"_s5", 0 0, L_0x2c8f270; 1 drivers +v0x2b53d10_0 .net "carryin", 0 0, L_0x2c8fdd0; 1 drivers +v0x2b53db0_0 .net "carryout", 0 0, L_0x2c8f750; 1 drivers +v0x2b53e50_0 .net "nB", 0 0, L_0x2c8e580; 1 drivers +v0x2b53f00_0 .net "nCmd2", 0 0, L_0x2c8efd0; 1 drivers +v0x2b54000_0 .net "subtract", 0 0, L_0x2c8f130; 1 drivers +L_0x2c8ef30 .part v0x2bc78e0_0, 0, 1; +L_0x2c8f090 .part v0x2bc78e0_0, 2, 1; +L_0x2c8f270 .part v0x2bc78e0_0, 0, 1; +S_0x2b53160 .scope module, "mux0" "TwoInMux" 3 105, 3 8, S_0x2b53070; + .timescale -9 -12; +L_0x2c8e6e0/d .functor NOT 1, L_0x2c8ef30, C4<0>, C4<0>, C4<0>; +L_0x2c8e6e0 .delay (10000,10000,10000) L_0x2c8e6e0/d; +L_0x2c8eb60/d .functor AND 1, L_0x2c8fca0, L_0x2c8e6e0, C4<1>, C4<1>; +L_0x2c8eb60 .delay (20000,20000,20000) L_0x2c8eb60/d; +L_0x2c8ec50/d .functor AND 1, L_0x2c8e580, L_0x2c8ef30, C4<1>, C4<1>; +L_0x2c8ec50 .delay (20000,20000,20000) L_0x2c8ec50/d; +L_0x2c8ed60/d .functor OR 1, L_0x2c8eb60, L_0x2c8ec50, C4<0>, C4<0>; +L_0x2c8ed60 .delay (20000,20000,20000) L_0x2c8ed60/d; +v0x2b53250_0 .net "S", 0 0, L_0x2c8ef30; 1 drivers +v0x2b532f0_0 .alias "in0", 0 0, v0x2b53980_0; +v0x2b53390_0 .alias "in1", 0 0, v0x2b53e50_0; +v0x2b53430_0 .net "nS", 0 0, L_0x2c8e6e0; 1 drivers +v0x2b534e0_0 .net "out0", 0 0, L_0x2c8eb60; 1 drivers +v0x2b53580_0 .net "out1", 0 0, L_0x2c8ec50; 1 drivers +v0x2b53660_0 .alias "outfinal", 0 0, v0x2b53a30_0; +S_0x2b51d60 .scope generate, "addbits[12]" "addbits[12]" 3 230, 3 230, S_0x2851a90; + .timescale -9 -12; +P_0x2b51778 .param/l "i" 3 230, +C4<01100>; +S_0x2b51ed0 .scope module, "attempt" "MiddleAddSubSLT" 3 232, 3 89, S_0x2b51d60; + .timescale -9 -12; +L_0x2c8eac0/d .functor NOT 1, L_0x2c911e0, C4<0>, C4<0>, C4<0>; +L_0x2c8eac0 .delay (10000,10000,10000) L_0x2c8eac0/d; +L_0x2c904e0/d .functor NOT 1, L_0x2c905a0, C4<0>, C4<0>, C4<0>; +L_0x2c904e0 .delay (10000,10000,10000) L_0x2c904e0/d; +L_0x2c90640/d .functor AND 1, L_0x2c90780, L_0x2c904e0, C4<1>, C4<1>; +L_0x2c90640 .delay (20000,20000,20000) L_0x2c90640/d; +L_0x2c90820/d .functor XOR 1, L_0x2c8ff60, L_0x2c90270, C4<0>, C4<0>; +L_0x2c90820 .delay (40000,40000,40000) L_0x2c90820/d; +L_0x2c90910/d .functor XOR 1, L_0x2c90820, L_0x2c91280, C4<0>, C4<0>; +L_0x2c90910 .delay (40000,40000,40000) L_0x2c90910/d; +L_0x2c90a00/d .functor AND 1, L_0x2c8ff60, L_0x2c90270, C4<1>, C4<1>; +L_0x2c90a00 .delay (20000,20000,20000) L_0x2c90a00/d; +L_0x2c90b70/d .functor AND 1, L_0x2c90820, L_0x2c91280, C4<1>, C4<1>; +L_0x2c90b70 .delay (20000,20000,20000) L_0x2c90b70/d; +L_0x2c90c60/d .functor OR 1, L_0x2c90a00, L_0x2c90b70, C4<0>, C4<0>; +L_0x2c90c60 .delay (20000,20000,20000) L_0x2c90c60/d; +v0x2b52560_0 .net "A", 0 0, L_0x2c8ff60; 1 drivers +v0x2b52620_0 .net "AandB", 0 0, L_0x2c90a00; 1 drivers +v0x2b526c0_0 .net "AddSubSLTSum", 0 0, L_0x2c90910; 1 drivers +v0x2b52760_0 .net "AxorB", 0 0, L_0x2c90820; 1 drivers +v0x2b527e0_0 .net "B", 0 0, L_0x2c911e0; 1 drivers +v0x2b52890_0 .net "BornB", 0 0, L_0x2c90270; 1 drivers +v0x2b52950_0 .net "CINandAxorB", 0 0, L_0x2c90b70; 1 drivers +v0x2b529d0_0 .alias "Command", 2 0, v0x2bc67a0_0; +v0x2b52a50_0 .net *"_s3", 0 0, L_0x2c905a0; 1 drivers +v0x2b52ad0_0 .net *"_s5", 0 0, L_0x2c90780; 1 drivers +v0x2b52b70_0 .net "carryin", 0 0, L_0x2c91280; 1 drivers +v0x2b52c10_0 .net "carryout", 0 0, L_0x2c90c60; 1 drivers +v0x2b52cb0_0 .net "nB", 0 0, L_0x2c8eac0; 1 drivers +v0x2b52d60_0 .net "nCmd2", 0 0, L_0x2c904e0; 1 drivers +v0x2b52e60_0 .net "subtract", 0 0, L_0x2c90640; 1 drivers +L_0x2c90440 .part v0x2bc78e0_0, 0, 1; +L_0x2c905a0 .part v0x2bc78e0_0, 2, 1; +L_0x2c90780 .part v0x2bc78e0_0, 0, 1; +S_0x2b51fc0 .scope module, "mux0" "TwoInMux" 3 105, 3 8, S_0x2b51ed0; + .timescale -9 -12; +L_0x2c8fb90/d .functor NOT 1, L_0x2c90440, C4<0>, C4<0>, C4<0>; +L_0x2c8fb90 .delay (10000,10000,10000) L_0x2c8fb90/d; +L_0x2c90090/d .functor AND 1, L_0x2c911e0, L_0x2c8fb90, C4<1>, C4<1>; +L_0x2c90090 .delay (20000,20000,20000) L_0x2c90090/d; +L_0x2c90180/d .functor AND 1, L_0x2c8eac0, L_0x2c90440, C4<1>, C4<1>; +L_0x2c90180 .delay (20000,20000,20000) L_0x2c90180/d; +L_0x2c90270/d .functor OR 1, L_0x2c90090, L_0x2c90180, C4<0>, C4<0>; +L_0x2c90270 .delay (20000,20000,20000) L_0x2c90270/d; +v0x2b520b0_0 .net "S", 0 0, L_0x2c90440; 1 drivers +v0x2b52150_0 .alias "in0", 0 0, v0x2b527e0_0; +v0x2b521f0_0 .alias "in1", 0 0, v0x2b52cb0_0; +v0x2b52290_0 .net "nS", 0 0, L_0x2c8fb90; 1 drivers +v0x2b52340_0 .net "out0", 0 0, L_0x2c90090; 1 drivers +v0x2b523e0_0 .net "out1", 0 0, L_0x2c90180; 1 drivers +v0x2b524c0_0 .alias "outfinal", 0 0, v0x2b52890_0; +S_0x2b50bc0 .scope generate, "addbits[13]" "addbits[13]" 3 230, 3 230, S_0x2851a90; + .timescale -9 -12; +P_0x2b505d8 .param/l "i" 3 230, +C4<01101>; +S_0x2b50d30 .scope module, "attempt" "MiddleAddSubSLT" 3 232, 3 89, S_0x2b50bc0; + .timescale -9 -12; +L_0x2c90fa0/d .functor NOT 1, L_0x2c914b0, C4<0>, C4<0>, C4<0>; +L_0x2c90fa0 .delay (10000,10000,10000) L_0x2c90fa0/d; +L_0x2c919e0/d .functor NOT 1, L_0x2c91aa0, C4<0>, C4<0>, C4<0>; +L_0x2c919e0 .delay (10000,10000,10000) L_0x2c919e0/d; +L_0x2c91b40/d .functor AND 1, L_0x2c91c80, L_0x2c919e0, C4<1>, C4<1>; +L_0x2c91b40 .delay (20000,20000,20000) L_0x2c91b40/d; +L_0x2c91d20/d .functor XOR 1, L_0x2c91410, L_0x2c91770, C4<0>, C4<0>; +L_0x2c91d20 .delay (40000,40000,40000) L_0x2c91d20/d; +L_0x2c91e10/d .functor XOR 1, L_0x2c91d20, L_0x2c926b0, C4<0>, C4<0>; +L_0x2c91e10 .delay (40000,40000,40000) L_0x2c91e10/d; +L_0x2c91f00/d .functor AND 1, L_0x2c91410, L_0x2c91770, C4<1>, C4<1>; +L_0x2c91f00 .delay (20000,20000,20000) L_0x2c91f00/d; +L_0x2c84530/d .functor AND 1, L_0x2c91d20, L_0x2c926b0, C4<1>, C4<1>; +L_0x2c84530 .delay (20000,20000,20000) L_0x2c84530/d; +L_0x2c92090/d .functor OR 1, L_0x2c91f00, L_0x2c84530, C4<0>, C4<0>; +L_0x2c92090 .delay (20000,20000,20000) L_0x2c92090/d; +v0x2b513c0_0 .net "A", 0 0, L_0x2c91410; 1 drivers +v0x2b51480_0 .net "AandB", 0 0, L_0x2c91f00; 1 drivers +v0x2b51520_0 .net "AddSubSLTSum", 0 0, L_0x2c91e10; 1 drivers +v0x2b515c0_0 .net "AxorB", 0 0, L_0x2c91d20; 1 drivers +v0x2b51640_0 .net "B", 0 0, L_0x2c914b0; 1 drivers +v0x2b516f0_0 .net "BornB", 0 0, L_0x2c91770; 1 drivers +v0x2b517b0_0 .net "CINandAxorB", 0 0, L_0x2c84530; 1 drivers +v0x2b51830_0 .alias "Command", 2 0, v0x2bc67a0_0; +v0x2b518b0_0 .net *"_s3", 0 0, L_0x2c91aa0; 1 drivers +v0x2b51930_0 .net *"_s5", 0 0, L_0x2c91c80; 1 drivers +v0x2b519d0_0 .net "carryin", 0 0, L_0x2c926b0; 1 drivers +v0x2b51a70_0 .net "carryout", 0 0, L_0x2c92090; 1 drivers +v0x2b51b10_0 .net "nB", 0 0, L_0x2c90fa0; 1 drivers +v0x2b51bc0_0 .net "nCmd2", 0 0, L_0x2c919e0; 1 drivers +v0x2b51cc0_0 .net "subtract", 0 0, L_0x2c91b40; 1 drivers +L_0x2c91940 .part v0x2bc78e0_0, 0, 1; +L_0x2c91aa0 .part v0x2bc78e0_0, 2, 1; +L_0x2c91c80 .part v0x2bc78e0_0, 0, 1; +S_0x2b50e20 .scope module, "mux0" "TwoInMux" 3 105, 3 8, S_0x2b50d30; + .timescale -9 -12; +L_0x2c91100/d .functor NOT 1, L_0x2c91940, C4<0>, C4<0>, C4<0>; +L_0x2c91100 .delay (10000,10000,10000) L_0x2c91100/d; +L_0x2c91570/d .functor AND 1, L_0x2c914b0, L_0x2c91100, C4<1>, C4<1>; +L_0x2c91570 .delay (20000,20000,20000) L_0x2c91570/d; +L_0x2c91660/d .functor AND 1, L_0x2c90fa0, L_0x2c91940, C4<1>, C4<1>; +L_0x2c91660 .delay (20000,20000,20000) L_0x2c91660/d; +L_0x2c91770/d .functor OR 1, L_0x2c91570, L_0x2c91660, C4<0>, C4<0>; +L_0x2c91770 .delay (20000,20000,20000) L_0x2c91770/d; +v0x2b50f10_0 .net "S", 0 0, L_0x2c91940; 1 drivers +v0x2b50fb0_0 .alias "in0", 0 0, v0x2b51640_0; +v0x2b51050_0 .alias "in1", 0 0, v0x2b51b10_0; +v0x2b510f0_0 .net "nS", 0 0, L_0x2c91100; 1 drivers +v0x2b511a0_0 .net "out0", 0 0, L_0x2c91570; 1 drivers +v0x2b51240_0 .net "out1", 0 0, L_0x2c91660; 1 drivers +v0x2b51320_0 .alias "outfinal", 0 0, v0x2b516f0_0; +S_0x2b4fa20 .scope generate, "addbits[14]" "addbits[14]" 3 230, 3 230, S_0x2851a90; + .timescale -9 -12; +P_0x2b4f438 .param/l "i" 3 230, +C4<01110>; +S_0x2b4fb90 .scope module, "attempt" "MiddleAddSubSLT" 3 232, 3 89, S_0x2b4fa20; + .timescale -9 -12; +L_0x2c923b0/d .functor NOT 1, L_0x2c928e0, C4<0>, C4<0>, C4<0>; +L_0x2c923b0 .delay (10000,10000,10000) L_0x2c923b0/d; +L_0x2c92d80/d .functor NOT 1, L_0x2c92e20, C4<0>, C4<0>, C4<0>; +L_0x2c92d80 .delay (10000,10000,10000) L_0x2c92d80/d; +L_0x2c92ec0/d .functor AND 1, L_0x2c93000, L_0x2c92d80, C4<1>, C4<1>; +L_0x2c92ec0 .delay (20000,20000,20000) L_0x2c92ec0/d; +L_0x2c930a0/d .functor XOR 1, L_0x2c92840, L_0x2c92b50, C4<0>, C4<0>; +L_0x2c930a0 .delay (40000,40000,40000) L_0x2c930a0/d; +L_0x2c93190/d .functor XOR 1, L_0x2c930a0, L_0x2c93b30, C4<0>, C4<0>; +L_0x2c93190 .delay (40000,40000,40000) L_0x2c93190/d; +L_0x2c93280/d .functor AND 1, L_0x2c92840, L_0x2c92b50, C4<1>, C4<1>; +L_0x2c93280 .delay (20000,20000,20000) L_0x2c93280/d; +L_0x2c933f0/d .functor AND 1, L_0x2c930a0, L_0x2c93b30, C4<1>, C4<1>; +L_0x2c933f0 .delay (20000,20000,20000) L_0x2c933f0/d; +L_0x2c934e0/d .functor OR 1, L_0x2c93280, L_0x2c933f0, C4<0>, C4<0>; +L_0x2c934e0 .delay (20000,20000,20000) L_0x2c934e0/d; +v0x2b50220_0 .net "A", 0 0, L_0x2c92840; 1 drivers +v0x2b502e0_0 .net "AandB", 0 0, L_0x2c93280; 1 drivers +v0x2b50380_0 .net "AddSubSLTSum", 0 0, L_0x2c93190; 1 drivers +v0x2b50420_0 .net "AxorB", 0 0, L_0x2c930a0; 1 drivers +v0x2b504a0_0 .net "B", 0 0, L_0x2c928e0; 1 drivers +v0x2b50550_0 .net "BornB", 0 0, L_0x2c92b50; 1 drivers +v0x2b50610_0 .net "CINandAxorB", 0 0, L_0x2c933f0; 1 drivers +v0x2b50690_0 .alias "Command", 2 0, v0x2bc67a0_0; +v0x2b50710_0 .net *"_s3", 0 0, L_0x2c92e20; 1 drivers +v0x2b50790_0 .net *"_s5", 0 0, L_0x2c93000; 1 drivers +v0x2b50830_0 .net "carryin", 0 0, L_0x2c93b30; 1 drivers +v0x2b508d0_0 .net "carryout", 0 0, L_0x2c934e0; 1 drivers +v0x2b50970_0 .net "nB", 0 0, L_0x2c923b0; 1 drivers +v0x2b50a20_0 .net "nCmd2", 0 0, L_0x2c92d80; 1 drivers +v0x2b50b20_0 .net "subtract", 0 0, L_0x2c92ec0; 1 drivers +L_0x2c92ce0 .part v0x2bc78e0_0, 0, 1; +L_0x2c92e20 .part v0x2bc78e0_0, 2, 1; +L_0x2c93000 .part v0x2bc78e0_0, 0, 1; +S_0x2b4fc80 .scope module, "mux0" "TwoInMux" 3 105, 3 8, S_0x2b4fb90; + .timescale -9 -12; +L_0x2c924f0/d .functor NOT 1, L_0x2c92ce0, C4<0>, C4<0>, C4<0>; +L_0x2c924f0 .delay (10000,10000,10000) L_0x2c924f0/d; +L_0x2c925b0/d .functor AND 1, L_0x2c928e0, L_0x2c924f0, C4<1>, C4<1>; +L_0x2c925b0 .delay (20000,20000,20000) L_0x2c925b0/d; +L_0x2c92a60/d .functor AND 1, L_0x2c923b0, L_0x2c92ce0, C4<1>, C4<1>; +L_0x2c92a60 .delay (20000,20000,20000) L_0x2c92a60/d; +L_0x2c92b50/d .functor OR 1, L_0x2c925b0, L_0x2c92a60, C4<0>, C4<0>; +L_0x2c92b50 .delay (20000,20000,20000) L_0x2c92b50/d; +v0x2b4fd70_0 .net "S", 0 0, L_0x2c92ce0; 1 drivers +v0x2b4fe10_0 .alias "in0", 0 0, v0x2b504a0_0; +v0x2b4feb0_0 .alias "in1", 0 0, v0x2b50970_0; +v0x2b4ff50_0 .net "nS", 0 0, L_0x2c924f0; 1 drivers +v0x2b50000_0 .net "out0", 0 0, L_0x2c925b0; 1 drivers +v0x2b500a0_0 .net "out1", 0 0, L_0x2c92a60; 1 drivers +v0x2b50180_0 .alias "outfinal", 0 0, v0x2b50550_0; +S_0x2b4e880 .scope generate, "addbits[15]" "addbits[15]" 3 230, 3 230, S_0x2851a90; + .timescale -9 -12; +P_0x2b4e298 .param/l "i" 3 230, +C4<01111>; +S_0x2b4e9f0 .scope module, "attempt" "MiddleAddSubSLT" 3 232, 3 89, S_0x2b4e880; + .timescale -9 -12; +L_0x2c93800/d .functor NOT 1, L_0x2c93d60, C4<0>, C4<0>, C4<0>; +L_0x2c93800 .delay (10000,10000,10000) L_0x2c93800/d; +L_0x2c941f0/d .functor NOT 1, L_0x2c94290, C4<0>, C4<0>, C4<0>; +L_0x2c941f0 .delay (10000,10000,10000) L_0x2c941f0/d; +L_0x2c94330/d .functor AND 1, L_0x2c94470, L_0x2c941f0, C4<1>, C4<1>; +L_0x2c94330 .delay (20000,20000,20000) L_0x2c94330/d; +L_0x2c94510/d .functor XOR 1, L_0x2c93cc0, L_0x2c93fc0, C4<0>, C4<0>; +L_0x2c94510 .delay (40000,40000,40000) L_0x2c94510/d; +L_0x2c94600/d .functor XOR 1, L_0x2c94510, L_0x2c94fd0, C4<0>, C4<0>; +L_0x2c94600 .delay (40000,40000,40000) L_0x2c94600/d; +L_0x2c946f0/d .functor AND 1, L_0x2c93cc0, L_0x2c93fc0, C4<1>, C4<1>; +L_0x2c946f0 .delay (20000,20000,20000) L_0x2c946f0/d; +L_0x2c94860/d .functor AND 1, L_0x2c94510, L_0x2c94fd0, C4<1>, C4<1>; +L_0x2c94860 .delay (20000,20000,20000) L_0x2c94860/d; +L_0x2c94950/d .functor OR 1, L_0x2c946f0, L_0x2c94860, C4<0>, C4<0>; +L_0x2c94950 .delay (20000,20000,20000) L_0x2c94950/d; +v0x2b4f080_0 .net "A", 0 0, L_0x2c93cc0; 1 drivers +v0x2b4f140_0 .net "AandB", 0 0, L_0x2c946f0; 1 drivers +v0x2b4f1e0_0 .net "AddSubSLTSum", 0 0, L_0x2c94600; 1 drivers +v0x2b4f280_0 .net "AxorB", 0 0, L_0x2c94510; 1 drivers +v0x2b4f300_0 .net "B", 0 0, L_0x2c93d60; 1 drivers +v0x2b4f3b0_0 .net "BornB", 0 0, L_0x2c93fc0; 1 drivers +v0x2b4f470_0 .net "CINandAxorB", 0 0, L_0x2c94860; 1 drivers +v0x2b4f4f0_0 .alias "Command", 2 0, v0x2bc67a0_0; +v0x2b4f570_0 .net *"_s3", 0 0, L_0x2c94290; 1 drivers +v0x2b4f5f0_0 .net *"_s5", 0 0, L_0x2c94470; 1 drivers +v0x2b4f690_0 .net "carryin", 0 0, L_0x2c94fd0; 1 drivers +v0x2b4f730_0 .net "carryout", 0 0, L_0x2c94950; 1 drivers +v0x2b4f7d0_0 .net "nB", 0 0, L_0x2c93800; 1 drivers +v0x2b4f880_0 .net "nCmd2", 0 0, L_0x2c941f0; 1 drivers +v0x2b4f980_0 .net "subtract", 0 0, L_0x2c94330; 1 drivers +L_0x2c94150 .part v0x2bc78e0_0, 0, 1; +L_0x2c94290 .part v0x2bc78e0_0, 2, 1; +L_0x2c94470 .part v0x2bc78e0_0, 0, 1; +S_0x2b4eae0 .scope module, "mux0" "TwoInMux" 3 105, 3 8, S_0x2b4e9f0; + .timescale -9 -12; +L_0x2c93910/d .functor NOT 1, L_0x2c94150, C4<0>, C4<0>, C4<0>; +L_0x2c93910 .delay (10000,10000,10000) L_0x2c93910/d; +L_0x2c939d0/d .functor AND 1, L_0x2c93d60, L_0x2c93910, C4<1>, C4<1>; +L_0x2c939d0 .delay (20000,20000,20000) L_0x2c939d0/d; +L_0x2c93ed0/d .functor AND 1, L_0x2c93800, L_0x2c94150, C4<1>, C4<1>; +L_0x2c93ed0 .delay (20000,20000,20000) L_0x2c93ed0/d; +L_0x2c93fc0/d .functor OR 1, L_0x2c939d0, L_0x2c93ed0, C4<0>, C4<0>; +L_0x2c93fc0 .delay (20000,20000,20000) L_0x2c93fc0/d; +v0x2b4ebd0_0 .net "S", 0 0, L_0x2c94150; 1 drivers +v0x2b4ec70_0 .alias "in0", 0 0, v0x2b4f300_0; +v0x2b4ed10_0 .alias "in1", 0 0, v0x2b4f7d0_0; +v0x2b4edb0_0 .net "nS", 0 0, L_0x2c93910; 1 drivers +v0x2b4ee60_0 .net "out0", 0 0, L_0x2c939d0; 1 drivers +v0x2b4ef00_0 .net "out1", 0 0, L_0x2c93ed0; 1 drivers +v0x2b4efe0_0 .alias "outfinal", 0 0, v0x2b4f3b0_0; +S_0x2b4d6e0 .scope generate, "addbits[16]" "addbits[16]" 3 230, 3 230, S_0x2851a90; + .timescale -9 -12; +P_0x2b4d0f8 .param/l "i" 3 230, +C4<010000>; +S_0x2b4d850 .scope module, "attempt" "MiddleAddSubSLT" 3 232, 3 89, S_0x2b4d6e0; + .timescale -9 -12; +L_0x2c93e00/d .functor NOT 1, L_0x2c95200, C4<0>, C4<0>, C4<0>; +L_0x2c93e00 .delay (10000,10000,10000) L_0x2c93e00/d; +L_0x2c95670/d .functor NOT 1, L_0x2c95710, C4<0>, C4<0>, C4<0>; +L_0x2c95670 .delay (10000,10000,10000) L_0x2c95670/d; +L_0x2c957b0/d .functor AND 1, L_0x2c958f0, L_0x2c95670, C4<1>, C4<1>; +L_0x2c957b0 .delay (20000,20000,20000) L_0x2c957b0/d; +L_0x2c95990/d .functor XOR 1, L_0x2c95160, L_0x2c95440, C4<0>, C4<0>; +L_0x2c95990 .delay (40000,40000,40000) L_0x2c95990/d; +L_0x2c95a80/d .functor XOR 1, L_0x2c95990, L_0x2c963f0, C4<0>, C4<0>; +L_0x2c95a80 .delay (40000,40000,40000) L_0x2c95a80/d; +L_0x2c95b70/d .functor AND 1, L_0x2c95160, L_0x2c95440, C4<1>, C4<1>; +L_0x2c95b70 .delay (20000,20000,20000) L_0x2c95b70/d; +L_0x2c95ce0/d .functor AND 1, L_0x2c95990, L_0x2c963f0, C4<1>, C4<1>; +L_0x2c95ce0 .delay (20000,20000,20000) L_0x2c95ce0/d; +L_0x2c95dd0/d .functor OR 1, L_0x2c95b70, L_0x2c95ce0, C4<0>, C4<0>; +L_0x2c95dd0 .delay (20000,20000,20000) L_0x2c95dd0/d; +v0x2b4dee0_0 .net "A", 0 0, L_0x2c95160; 1 drivers +v0x2b4dfa0_0 .net "AandB", 0 0, L_0x2c95b70; 1 drivers +v0x2b4e040_0 .net "AddSubSLTSum", 0 0, L_0x2c95a80; 1 drivers +v0x2b4e0e0_0 .net "AxorB", 0 0, L_0x2c95990; 1 drivers +v0x2b4e160_0 .net "B", 0 0, L_0x2c95200; 1 drivers +v0x2b4e210_0 .net "BornB", 0 0, L_0x2c95440; 1 drivers +v0x2b4e2d0_0 .net "CINandAxorB", 0 0, L_0x2c95ce0; 1 drivers +v0x2b4e350_0 .alias "Command", 2 0, v0x2bc67a0_0; +v0x2b4e3d0_0 .net *"_s3", 0 0, L_0x2c95710; 1 drivers +v0x2b4e450_0 .net *"_s5", 0 0, L_0x2c958f0; 1 drivers +v0x2b4e4f0_0 .net "carryin", 0 0, L_0x2c963f0; 1 drivers +v0x2b4e590_0 .net "carryout", 0 0, L_0x2c95dd0; 1 drivers +v0x2b4e630_0 .net "nB", 0 0, L_0x2c93e00; 1 drivers +v0x2b4e6e0_0 .net "nCmd2", 0 0, L_0x2c95670; 1 drivers +v0x2b4e7e0_0 .net "subtract", 0 0, L_0x2c957b0; 1 drivers +L_0x2c955d0 .part v0x2bc78e0_0, 0, 1; +L_0x2c95710 .part v0x2bc78e0_0, 2, 1; +L_0x2c958f0 .part v0x2bc78e0_0, 0, 1; +S_0x2b4d940 .scope module, "mux0" "TwoInMux" 3 105, 3 8, S_0x2b4d850; + .timescale -9 -12; +L_0x2c94d50/d .functor NOT 1, L_0x2c955d0, C4<0>, C4<0>, C4<0>; +L_0x2c94d50 .delay (10000,10000,10000) L_0x2c94d50/d; +L_0x2c94e10/d .functor AND 1, L_0x2c95200, L_0x2c94d50, C4<1>, C4<1>; +L_0x2c94e10 .delay (20000,20000,20000) L_0x2c94e10/d; +L_0x2c95350/d .functor AND 1, L_0x2c93e00, L_0x2c955d0, C4<1>, C4<1>; +L_0x2c95350 .delay (20000,20000,20000) L_0x2c95350/d; +L_0x2c95440/d .functor OR 1, L_0x2c94e10, L_0x2c95350, C4<0>, C4<0>; +L_0x2c95440 .delay (20000,20000,20000) L_0x2c95440/d; +v0x2b4da30_0 .net "S", 0 0, L_0x2c955d0; 1 drivers +v0x2b4dad0_0 .alias "in0", 0 0, v0x2b4e160_0; +v0x2b4db70_0 .alias "in1", 0 0, v0x2b4e630_0; +v0x2b4dc10_0 .net "nS", 0 0, L_0x2c94d50; 1 drivers +v0x2b4dcc0_0 .net "out0", 0 0, L_0x2c94e10; 1 drivers +v0x2b4dd60_0 .net "out1", 0 0, L_0x2c95350; 1 drivers +v0x2b4de40_0 .alias "outfinal", 0 0, v0x2b4e210_0; +S_0x2b4c540 .scope generate, "addbits[17]" "addbits[17]" 3 230, 3 230, S_0x2851a90; + .timescale -9 -12; +P_0x2b4bf58 .param/l "i" 3 230, +C4<010001>; +S_0x2b4c6b0 .scope module, "attempt" "MiddleAddSubSLT" 3 232, 3 89, S_0x2b4c540; + .timescale -9 -12; +L_0x2c8be90/d .functor NOT 1, L_0x2c96a30, C4<0>, C4<0>, C4<0>; +L_0x2c8be90 .delay (10000,10000,10000) L_0x2c8be90/d; +L_0x2c96d30/d .functor NOT 1, L_0x2c96dd0, C4<0>, C4<0>, C4<0>; +L_0x2c96d30 .delay (10000,10000,10000) L_0x2c96d30/d; +L_0x2c96e70/d .functor AND 1, L_0x2c96fb0, L_0x2c96d30, C4<1>, C4<1>; +L_0x2c96e70 .delay (20000,20000,20000) L_0x2c96e70/d; +L_0x2c97050/d .functor XOR 1, L_0x2c96990, L_0x2c96310, C4<0>, C4<0>; +L_0x2c97050 .delay (40000,40000,40000) L_0x2c97050/d; +L_0x2c97140/d .functor XOR 1, L_0x2c97050, L_0x2c97ae0, C4<0>, C4<0>; +L_0x2c97140 .delay (40000,40000,40000) L_0x2c97140/d; +L_0x2c97230/d .functor AND 1, L_0x2c96990, L_0x2c96310, C4<1>, C4<1>; +L_0x2c97230 .delay (20000,20000,20000) L_0x2c97230/d; +L_0x2c973a0/d .functor AND 1, L_0x2c97050, L_0x2c97ae0, C4<1>, C4<1>; +L_0x2c973a0 .delay (20000,20000,20000) L_0x2c973a0/d; +L_0x2c97490/d .functor OR 1, L_0x2c97230, L_0x2c973a0, C4<0>, C4<0>; +L_0x2c97490 .delay (20000,20000,20000) L_0x2c97490/d; +v0x2b4cd40_0 .net "A", 0 0, L_0x2c96990; 1 drivers +v0x2b4ce00_0 .net "AandB", 0 0, L_0x2c97230; 1 drivers +v0x2b4cea0_0 .net "AddSubSLTSum", 0 0, L_0x2c97140; 1 drivers +v0x2b4cf40_0 .net "AxorB", 0 0, L_0x2c97050; 1 drivers +v0x2b4cfc0_0 .net "B", 0 0, L_0x2c96a30; 1 drivers +v0x2b4d070_0 .net "BornB", 0 0, L_0x2c96310; 1 drivers +v0x2b4d130_0 .net "CINandAxorB", 0 0, L_0x2c973a0; 1 drivers +v0x2b4d1b0_0 .alias "Command", 2 0, v0x2bc67a0_0; +v0x2b4d230_0 .net *"_s3", 0 0, L_0x2c96dd0; 1 drivers +v0x2b4d2b0_0 .net *"_s5", 0 0, L_0x2c96fb0; 1 drivers +v0x2b4d350_0 .net "carryin", 0 0, L_0x2c97ae0; 1 drivers +v0x2b4d3f0_0 .net "carryout", 0 0, L_0x2c97490; 1 drivers +v0x2b4d490_0 .net "nB", 0 0, L_0x2c8be90; 1 drivers +v0x2b4d540_0 .net "nCmd2", 0 0, L_0x2c96d30; 1 drivers +v0x2b4d640_0 .net "subtract", 0 0, L_0x2c96e70; 1 drivers +L_0x2c96c90 .part v0x2bc78e0_0, 0, 1; +L_0x2c96dd0 .part v0x2bc78e0_0, 2, 1; +L_0x2c96fb0 .part v0x2bc78e0_0, 0, 1; +S_0x2b4c7a0 .scope module, "mux0" "TwoInMux" 3 105, 3 8, S_0x2b4c6b0; + .timescale -9 -12; +L_0x2c8bfd0/d .functor NOT 1, L_0x2c96c90, C4<0>, C4<0>, C4<0>; +L_0x2c8bfd0 .delay (10000,10000,10000) L_0x2c8bfd0/d; +L_0x2c960f0/d .functor AND 1, L_0x2c96a30, L_0x2c8bfd0, C4<1>, C4<1>; +L_0x2c960f0 .delay (20000,20000,20000) L_0x2c960f0/d; +L_0x2c96200/d .functor AND 1, L_0x2c8be90, L_0x2c96c90, C4<1>, C4<1>; +L_0x2c96200 .delay (20000,20000,20000) L_0x2c96200/d; +L_0x2c96310/d .functor OR 1, L_0x2c960f0, L_0x2c96200, C4<0>, C4<0>; +L_0x2c96310 .delay (20000,20000,20000) L_0x2c96310/d; +v0x2b4c890_0 .net "S", 0 0, L_0x2c96c90; 1 drivers +v0x2b4c930_0 .alias "in0", 0 0, v0x2b4cfc0_0; +v0x2b4c9d0_0 .alias "in1", 0 0, v0x2b4d490_0; +v0x2b4ca70_0 .net "nS", 0 0, L_0x2c8bfd0; 1 drivers +v0x2b4cb20_0 .net "out0", 0 0, L_0x2c960f0; 1 drivers +v0x2b4cbc0_0 .net "out1", 0 0, L_0x2c96200; 1 drivers +v0x2b4cca0_0 .alias "outfinal", 0 0, v0x2b4d070_0; +S_0x2b4b3a0 .scope generate, "addbits[18]" "addbits[18]" 3 230, 3 230, S_0x2851a90; + .timescale -9 -12; +P_0x2b4adb8 .param/l "i" 3 230, +C4<010010>; +S_0x2b4b510 .scope module, "attempt" "MiddleAddSubSLT" 3 232, 3 89, S_0x2b4b3a0; + .timescale -9 -12; +L_0x2c977b0/d .functor NOT 1, L_0x2c97d10, C4<0>, C4<0>, C4<0>; +L_0x2c977b0 .delay (10000,10000,10000) L_0x2c977b0/d; +L_0x2c981a0/d .functor NOT 1, L_0x2c98240, C4<0>, C4<0>, C4<0>; +L_0x2c981a0 .delay (10000,10000,10000) L_0x2c981a0/d; +L_0x2c982e0/d .functor AND 1, L_0x2c98420, L_0x2c981a0, C4<1>, C4<1>; +L_0x2c982e0 .delay (20000,20000,20000) L_0x2c982e0/d; +L_0x2c984c0/d .functor XOR 1, L_0x2c97c70, L_0x2c97f70, C4<0>, C4<0>; +L_0x2c984c0 .delay (40000,40000,40000) L_0x2c984c0/d; +L_0x2c985b0/d .functor XOR 1, L_0x2c984c0, L_0x2c98f80, C4<0>, C4<0>; +L_0x2c985b0 .delay (40000,40000,40000) L_0x2c985b0/d; +L_0x2c986a0/d .functor AND 1, L_0x2c97c70, L_0x2c97f70, C4<1>, C4<1>; +L_0x2c986a0 .delay (20000,20000,20000) L_0x2c986a0/d; +L_0x2c98810/d .functor AND 1, L_0x2c984c0, L_0x2c98f80, C4<1>, C4<1>; +L_0x2c98810 .delay (20000,20000,20000) L_0x2c98810/d; +L_0x2c98900/d .functor OR 1, L_0x2c986a0, L_0x2c98810, C4<0>, C4<0>; +L_0x2c98900 .delay (20000,20000,20000) L_0x2c98900/d; +v0x2b4bba0_0 .net "A", 0 0, L_0x2c97c70; 1 drivers +v0x2b4bc60_0 .net "AandB", 0 0, L_0x2c986a0; 1 drivers +v0x2b4bd00_0 .net "AddSubSLTSum", 0 0, L_0x2c985b0; 1 drivers +v0x2b4bda0_0 .net "AxorB", 0 0, L_0x2c984c0; 1 drivers +v0x2b4be20_0 .net "B", 0 0, L_0x2c97d10; 1 drivers +v0x2b4bed0_0 .net "BornB", 0 0, L_0x2c97f70; 1 drivers +v0x2b4bf90_0 .net "CINandAxorB", 0 0, L_0x2c98810; 1 drivers +v0x2b4c010_0 .alias "Command", 2 0, v0x2bc67a0_0; +v0x2b4c090_0 .net *"_s3", 0 0, L_0x2c98240; 1 drivers +v0x2b4c110_0 .net *"_s5", 0 0, L_0x2c98420; 1 drivers +v0x2b4c1b0_0 .net "carryin", 0 0, L_0x2c98f80; 1 drivers +v0x2b4c250_0 .net "carryout", 0 0, L_0x2c98900; 1 drivers +v0x2b4c2f0_0 .net "nB", 0 0, L_0x2c977b0; 1 drivers +v0x2b4c3a0_0 .net "nCmd2", 0 0, L_0x2c981a0; 1 drivers +v0x2b4c4a0_0 .net "subtract", 0 0, L_0x2c982e0; 1 drivers +L_0x2c98100 .part v0x2bc78e0_0, 0, 1; +L_0x2c98240 .part v0x2bc78e0_0, 2, 1; +L_0x2c98420 .part v0x2bc78e0_0, 0, 1; +S_0x2b4b600 .scope module, "mux0" "TwoInMux" 3 105, 3 8, S_0x2b4b510; + .timescale -9 -12; +L_0x2c978c0/d .functor NOT 1, L_0x2c98100, C4<0>, C4<0>, C4<0>; +L_0x2c978c0 .delay (10000,10000,10000) L_0x2c978c0/d; +L_0x2c97980/d .functor AND 1, L_0x2c97d10, L_0x2c978c0, C4<1>, C4<1>; +L_0x2c97980 .delay (20000,20000,20000) L_0x2c97980/d; +L_0x2c97ec0/d .functor AND 1, L_0x2c977b0, L_0x2c98100, C4<1>, C4<1>; +L_0x2c97ec0 .delay (20000,20000,20000) L_0x2c97ec0/d; +L_0x2c97f70/d .functor OR 1, L_0x2c97980, L_0x2c97ec0, C4<0>, C4<0>; +L_0x2c97f70 .delay (20000,20000,20000) L_0x2c97f70/d; +v0x2b4b6f0_0 .net "S", 0 0, L_0x2c98100; 1 drivers +v0x2b4b790_0 .alias "in0", 0 0, v0x2b4be20_0; +v0x2b4b830_0 .alias "in1", 0 0, v0x2b4c2f0_0; +v0x2b4b8d0_0 .net "nS", 0 0, L_0x2c978c0; 1 drivers +v0x2b4b980_0 .net "out0", 0 0, L_0x2c97980; 1 drivers +v0x2b4ba20_0 .net "out1", 0 0, L_0x2c97ec0; 1 drivers +v0x2b4bb00_0 .alias "outfinal", 0 0, v0x2b4bed0_0; +S_0x2b4a200 .scope generate, "addbits[19]" "addbits[19]" 3 230, 3 230, S_0x2851a90; + .timescale -9 -12; +P_0x2b49c18 .param/l "i" 3 230, +C4<010011>; +S_0x2b4a370 .scope module, "attempt" "MiddleAddSubSLT" 3 232, 3 89, S_0x2b4a200; + .timescale -9 -12; +L_0x2c97e40/d .functor NOT 1, L_0x2c991b0, C4<0>, C4<0>, C4<0>; +L_0x2c97e40 .delay (10000,10000,10000) L_0x2c97e40/d; +L_0x2c99650/d .functor NOT 1, L_0x2c996f0, C4<0>, C4<0>, C4<0>; +L_0x2c99650 .delay (10000,10000,10000) L_0x2c99650/d; +L_0x2c99790/d .functor AND 1, L_0x2c998d0, L_0x2c99650, C4<1>, C4<1>; +L_0x2c99790 .delay (20000,20000,20000) L_0x2c99790/d; +L_0x2c99970/d .functor XOR 1, L_0x2c99110, L_0x2c99420, C4<0>, C4<0>; +L_0x2c99970 .delay (40000,40000,40000) L_0x2c99970/d; +L_0x2c99a60/d .functor XOR 1, L_0x2c99970, L_0x2c992e0, C4<0>, C4<0>; +L_0x2c99a60 .delay (40000,40000,40000) L_0x2c99a60/d; +L_0x2c99b50/d .functor AND 1, L_0x2c99110, L_0x2c99420, C4<1>, C4<1>; +L_0x2c99b50 .delay (20000,20000,20000) L_0x2c99b50/d; +L_0x2c99cc0/d .functor AND 1, L_0x2c99970, L_0x2c992e0, C4<1>, C4<1>; +L_0x2c99cc0 .delay (20000,20000,20000) L_0x2c99cc0/d; +L_0x2c99db0/d .functor OR 1, L_0x2c99b50, L_0x2c99cc0, C4<0>, C4<0>; +L_0x2c99db0 .delay (20000,20000,20000) L_0x2c99db0/d; +v0x2b4aa00_0 .net "A", 0 0, L_0x2c99110; 1 drivers +v0x2b4aac0_0 .net "AandB", 0 0, L_0x2c99b50; 1 drivers +v0x2b4ab60_0 .net "AddSubSLTSum", 0 0, L_0x2c99a60; 1 drivers +v0x2b4ac00_0 .net "AxorB", 0 0, L_0x2c99970; 1 drivers +v0x2b4ac80_0 .net "B", 0 0, L_0x2c991b0; 1 drivers +v0x2b4ad30_0 .net "BornB", 0 0, L_0x2c99420; 1 drivers +v0x2b4adf0_0 .net "CINandAxorB", 0 0, L_0x2c99cc0; 1 drivers +v0x2b4ae70_0 .alias "Command", 2 0, v0x2bc67a0_0; +v0x2b4aef0_0 .net *"_s3", 0 0, L_0x2c996f0; 1 drivers +v0x2b4af70_0 .net *"_s5", 0 0, L_0x2c998d0; 1 drivers +v0x2b4b010_0 .net "carryin", 0 0, L_0x2c992e0; 1 drivers +v0x2b4b0b0_0 .net "carryout", 0 0, L_0x2c99db0; 1 drivers +v0x2b4b150_0 .net "nB", 0 0, L_0x2c97e40; 1 drivers +v0x2b4b200_0 .net "nCmd2", 0 0, L_0x2c99650; 1 drivers +v0x2b4b300_0 .net "subtract", 0 0, L_0x2c99790; 1 drivers +L_0x2c995b0 .part v0x2bc78e0_0, 0, 1; +L_0x2c996f0 .part v0x2bc78e0_0, 2, 1; +L_0x2c998d0 .part v0x2bc78e0_0, 0, 1; +S_0x2b4a460 .scope module, "mux0" "TwoInMux" 3 105, 3 8, S_0x2b4a370; + .timescale -9 -12; +L_0x2c98d00/d .functor NOT 1, L_0x2c995b0, C4<0>, C4<0>, C4<0>; +L_0x2c98d00 .delay (10000,10000,10000) L_0x2c98d00/d; +L_0x2c98dc0/d .functor AND 1, L_0x2c991b0, L_0x2c98d00, C4<1>, C4<1>; +L_0x2c98dc0 .delay (20000,20000,20000) L_0x2c98dc0/d; +L_0x2c98ed0/d .functor AND 1, L_0x2c97e40, L_0x2c995b0, C4<1>, C4<1>; +L_0x2c98ed0 .delay (20000,20000,20000) L_0x2c98ed0/d; +L_0x2c99420/d .functor OR 1, L_0x2c98dc0, L_0x2c98ed0, C4<0>, C4<0>; +L_0x2c99420 .delay (20000,20000,20000) L_0x2c99420/d; +v0x2b4a550_0 .net "S", 0 0, L_0x2c995b0; 1 drivers +v0x2b4a5f0_0 .alias "in0", 0 0, v0x2b4ac80_0; +v0x2b4a690_0 .alias "in1", 0 0, v0x2b4b150_0; +v0x2b4a730_0 .net "nS", 0 0, L_0x2c98d00; 1 drivers +v0x2b4a7e0_0 .net "out0", 0 0, L_0x2c98dc0; 1 drivers +v0x2b4a880_0 .net "out1", 0 0, L_0x2c98ed0; 1 drivers +v0x2b4a960_0 .alias "outfinal", 0 0, v0x2b4ad30_0; +S_0x2b49060 .scope generate, "addbits[20]" "addbits[20]" 3 230, 3 230, S_0x2851a90; + .timescale -9 -12; +P_0x2b48a78 .param/l "i" 3 230, +C4<010100>; +S_0x2b491d0 .scope module, "attempt" "MiddleAddSubSLT" 3 232, 3 89, S_0x2b49060; + .timescale -9 -12; +L_0x2c9a470/d .functor NOT 1, L_0x2c9a260, C4<0>, C4<0>, C4<0>; +L_0x2c9a470 .delay (10000,10000,10000) L_0x2c9a470/d; +L_0x2c9aa60/d .functor NOT 1, L_0x2c9ab20, C4<0>, C4<0>, C4<0>; +L_0x2c9aa60 .delay (10000,10000,10000) L_0x2c9aa60/d; +L_0x2c9abc0/d .functor AND 1, L_0x2c9ad00, L_0x2c9aa60, C4<1>, C4<1>; +L_0x2c9abc0 .delay (20000,20000,20000) L_0x2c9abc0/d; +L_0x2c9ada0/d .functor XOR 1, L_0x2c9a1c0, L_0x2c9a7f0, C4<0>, C4<0>; +L_0x2c9ada0 .delay (40000,40000,40000) L_0x2c9ada0/d; +L_0x2c9ae90/d .functor XOR 1, L_0x2c9ada0, L_0x2c9a390, C4<0>, C4<0>; +L_0x2c9ae90 .delay (40000,40000,40000) L_0x2c9ae90/d; +L_0x2c9af80/d .functor AND 1, L_0x2c9a1c0, L_0x2c9a7f0, C4<1>, C4<1>; +L_0x2c9af80 .delay (20000,20000,20000) L_0x2c9af80/d; +L_0x2c9b0f0/d .functor AND 1, L_0x2c9ada0, L_0x2c9a390, C4<1>, C4<1>; +L_0x2c9b0f0 .delay (20000,20000,20000) L_0x2c9b0f0/d; +L_0x2c9b200/d .functor OR 1, L_0x2c9af80, L_0x2c9b0f0, C4<0>, C4<0>; +L_0x2c9b200 .delay (20000,20000,20000) L_0x2c9b200/d; +v0x2b49860_0 .net "A", 0 0, L_0x2c9a1c0; 1 drivers +v0x2b49920_0 .net "AandB", 0 0, L_0x2c9af80; 1 drivers +v0x2b499c0_0 .net "AddSubSLTSum", 0 0, L_0x2c9ae90; 1 drivers +v0x2b49a60_0 .net "AxorB", 0 0, L_0x2c9ada0; 1 drivers +v0x2b49ae0_0 .net "B", 0 0, L_0x2c9a260; 1 drivers +v0x2b49b90_0 .net "BornB", 0 0, L_0x2c9a7f0; 1 drivers +v0x2b49c50_0 .net "CINandAxorB", 0 0, L_0x2c9b0f0; 1 drivers +v0x2b49cd0_0 .alias "Command", 2 0, v0x2bc67a0_0; +v0x2b49d50_0 .net *"_s3", 0 0, L_0x2c9ab20; 1 drivers +v0x2b49dd0_0 .net *"_s5", 0 0, L_0x2c9ad00; 1 drivers +v0x2b49e70_0 .net "carryin", 0 0, L_0x2c9a390; 1 drivers +v0x2b49f10_0 .net "carryout", 0 0, L_0x2c9b200; 1 drivers +v0x2b49fb0_0 .net "nB", 0 0, L_0x2c9a470; 1 drivers +v0x2b4a060_0 .net "nCmd2", 0 0, L_0x2c9aa60; 1 drivers +v0x2b4a160_0 .net "subtract", 0 0, L_0x2c9abc0; 1 drivers +L_0x2c9a9c0 .part v0x2bc78e0_0, 0, 1; +L_0x2c9ab20 .part v0x2bc78e0_0, 2, 1; +L_0x2c9ad00 .part v0x2bc78e0_0, 0, 1; +S_0x2b492c0 .scope module, "mux0" "TwoInMux" 3 105, 3 8, S_0x2b491d0; + .timescale -9 -12; +L_0x2c9a570/d .functor NOT 1, L_0x2c9a9c0, C4<0>, C4<0>, C4<0>; +L_0x2c9a570 .delay (10000,10000,10000) L_0x2c9a570/d; +L_0x2c9a610/d .functor AND 1, L_0x2c9a260, L_0x2c9a570, C4<1>, C4<1>; +L_0x2c9a610 .delay (20000,20000,20000) L_0x2c9a610/d; +L_0x2c9a700/d .functor AND 1, L_0x2c9a470, L_0x2c9a9c0, C4<1>, C4<1>; +L_0x2c9a700 .delay (20000,20000,20000) L_0x2c9a700/d; +L_0x2c9a7f0/d .functor OR 1, L_0x2c9a610, L_0x2c9a700, C4<0>, C4<0>; +L_0x2c9a7f0 .delay (20000,20000,20000) L_0x2c9a7f0/d; +v0x2b493b0_0 .net "S", 0 0, L_0x2c9a9c0; 1 drivers +v0x2b49450_0 .alias "in0", 0 0, v0x2b49ae0_0; +v0x2b494f0_0 .alias "in1", 0 0, v0x2b49fb0_0; +v0x2b49590_0 .net "nS", 0 0, L_0x2c9a570; 1 drivers +v0x2b49640_0 .net "out0", 0 0, L_0x2c9a610; 1 drivers +v0x2b496e0_0 .net "out1", 0 0, L_0x2c9a700; 1 drivers +v0x2b497c0_0 .alias "outfinal", 0 0, v0x2b49b90_0; +S_0x2b47ef0 .scope generate, "addbits[21]" "addbits[21]" 3 230, 3 230, S_0x2851a90; + .timescale -9 -12; +P_0x2b477d8 .param/l "i" 3 230, +C4<010101>; +S_0x2b48060 .scope module, "attempt" "MiddleAddSubSLT" 3 232, 3 89, S_0x2b47ef0; + .timescale -9 -12; +L_0x2c9b910/d .functor NOT 1, L_0x2c9b6d0, C4<0>, C4<0>, C4<0>; +L_0x2c9b910 .delay (10000,10000,10000) L_0x2c9b910/d; +L_0x2c9bf80/d .functor NOT 1, L_0x2c9c040, C4<0>, C4<0>, C4<0>; +L_0x2c9bf80 .delay (10000,10000,10000) L_0x2c9bf80/d; +L_0x2c9c0e0/d .functor AND 1, L_0x2c9c220, L_0x2c9bf80, C4<1>, C4<1>; +L_0x2c9c0e0 .delay (20000,20000,20000) L_0x2c9c0e0/d; +L_0x2c9c2c0/d .functor XOR 1, L_0x2c9b630, L_0x2c9bd10, C4<0>, C4<0>; +L_0x2c9c2c0 .delay (40000,40000,40000) L_0x2c9c2c0/d; +L_0x2c9c3b0/d .functor XOR 1, L_0x2c9c2c0, L_0x2c9b800, C4<0>, C4<0>; +L_0x2c9c3b0 .delay (40000,40000,40000) L_0x2c9c3b0/d; +L_0x2c9c4a0/d .functor AND 1, L_0x2c9b630, L_0x2c9bd10, C4<1>, C4<1>; +L_0x2c9c4a0 .delay (20000,20000,20000) L_0x2c9c4a0/d; +L_0x2c9c610/d .functor AND 1, L_0x2c9c2c0, L_0x2c9b800, C4<1>, C4<1>; +L_0x2c9c610 .delay (20000,20000,20000) L_0x2c9c610/d; +L_0x2c9c700/d .functor OR 1, L_0x2c9c4a0, L_0x2c9c610, C4<0>, C4<0>; +L_0x2c9c700 .delay (20000,20000,20000) L_0x2c9c700/d; +v0x2b486c0_0 .net "A", 0 0, L_0x2c9b630; 1 drivers +v0x2b48780_0 .net "AandB", 0 0, L_0x2c9c4a0; 1 drivers +v0x2b48820_0 .net "AddSubSLTSum", 0 0, L_0x2c9c3b0; 1 drivers +v0x2b488c0_0 .net "AxorB", 0 0, L_0x2c9c2c0; 1 drivers +v0x2b48940_0 .net "B", 0 0, L_0x2c9b6d0; 1 drivers +v0x2b489f0_0 .net "BornB", 0 0, L_0x2c9bd10; 1 drivers +v0x2b48ab0_0 .net "CINandAxorB", 0 0, L_0x2c9c610; 1 drivers +v0x2b48b30_0 .alias "Command", 2 0, v0x2bc67a0_0; +v0x2b48bb0_0 .net *"_s3", 0 0, L_0x2c9c040; 1 drivers +v0x2b48c30_0 .net *"_s5", 0 0, L_0x2c9c220; 1 drivers +v0x2b48cd0_0 .net "carryin", 0 0, L_0x2c9b800; 1 drivers +v0x2b48d70_0 .net "carryout", 0 0, L_0x2c9c700; 1 drivers +v0x2b48e10_0 .net "nB", 0 0, L_0x2c9b910; 1 drivers +v0x2b48ec0_0 .net "nCmd2", 0 0, L_0x2c9bf80; 1 drivers +v0x2b48fc0_0 .net "subtract", 0 0, L_0x2c9c0e0; 1 drivers +L_0x2c9bee0 .part v0x2bc78e0_0, 0, 1; +L_0x2c9c040 .part v0x2bc78e0_0, 2, 1; +L_0x2c9c220 .part v0x2bc78e0_0, 0, 1; +S_0x2b48150 .scope module, "mux0" "TwoInMux" 3 105, 3 8, S_0x2b48060; + .timescale -9 -12; +L_0x2c9ba30/d .functor NOT 1, L_0x2c9bee0, C4<0>, C4<0>, C4<0>; +L_0x2c9ba30 .delay (10000,10000,10000) L_0x2c9ba30/d; +L_0x2c9baf0/d .functor AND 1, L_0x2c9b6d0, L_0x2c9ba30, C4<1>, C4<1>; +L_0x2c9baf0 .delay (20000,20000,20000) L_0x2c9baf0/d; +L_0x2c9bc00/d .functor AND 1, L_0x2c9b910, L_0x2c9bee0, C4<1>, C4<1>; +L_0x2c9bc00 .delay (20000,20000,20000) L_0x2c9bc00/d; +L_0x2c9bd10/d .functor OR 1, L_0x2c9baf0, L_0x2c9bc00, C4<0>, C4<0>; +L_0x2c9bd10 .delay (20000,20000,20000) L_0x2c9bd10/d; +v0x2b48240_0 .net "S", 0 0, L_0x2c9bee0; 1 drivers +v0x2b482e0_0 .alias "in0", 0 0, v0x2b48940_0; +v0x2b48380_0 .alias "in1", 0 0, v0x2b48e10_0; +v0x2b48420_0 .net "nS", 0 0, L_0x2c9ba30; 1 drivers +v0x2b484a0_0 .net "out0", 0 0, L_0x2c9baf0; 1 drivers +v0x2b48540_0 .net "out1", 0 0, L_0x2c9bc00; 1 drivers +v0x2b48620_0 .alias "outfinal", 0 0, v0x2b489f0_0; +S_0x2b46d20 .scope generate, "addbits[22]" "addbits[22]" 3 230, 3 230, S_0x2851a90; + .timescale -9 -12; +P_0x2b46738 .param/l "i" 3 230, +C4<010110>; +S_0x2b46e90 .scope module, "attempt" "MiddleAddSubSLT" 3 232, 3 89, S_0x2b46d20; + .timescale -9 -12; +L_0x2c9b8a0/d .functor NOT 1, L_0x2c9cbd0, C4<0>, C4<0>, C4<0>; +L_0x2c9b8a0 .delay (10000,10000,10000) L_0x2c9b8a0/d; +L_0x2c9d490/d .functor NOT 1, L_0x2c9d550, C4<0>, C4<0>, C4<0>; +L_0x2c9d490 .delay (10000,10000,10000) L_0x2c9d490/d; +L_0x2c9d5f0/d .functor AND 1, L_0x2c9d730, L_0x2c9d490, C4<1>, C4<1>; +L_0x2c9d5f0 .delay (20000,20000,20000) L_0x2c9d5f0/d; +L_0x2c9d7d0/d .functor XOR 1, L_0x2c9cb30, L_0x2c9d220, C4<0>, C4<0>; +L_0x2c9d7d0 .delay (40000,40000,40000) L_0x2c9d7d0/d; +L_0x2c9d8c0/d .functor XOR 1, L_0x2c9d7d0, L_0x2c9cd00, C4<0>, C4<0>; +L_0x2c9d8c0 .delay (40000,40000,40000) L_0x2c9d8c0/d; +L_0x2c9d9b0/d .functor AND 1, L_0x2c9cb30, L_0x2c9d220, C4<1>, C4<1>; +L_0x2c9d9b0 .delay (20000,20000,20000) L_0x2c9d9b0/d; +L_0x2c9db20/d .functor AND 1, L_0x2c9d7d0, L_0x2c9cd00, C4<1>, C4<1>; +L_0x2c9db20 .delay (20000,20000,20000) L_0x2c9db20/d; +L_0x2c9dc10/d .functor OR 1, L_0x2c9d9b0, L_0x2c9db20, C4<0>, C4<0>; +L_0x2c9dc10 .delay (20000,20000,20000) L_0x2c9dc10/d; +v0x2b473f0_0 .net "A", 0 0, L_0x2c9cb30; 1 drivers +v0x2b474b0_0 .net "AandB", 0 0, L_0x2c9d9b0; 1 drivers +v0x2b47550_0 .net "AddSubSLTSum", 0 0, L_0x2c9d8c0; 1 drivers +v0x2b475f0_0 .net "AxorB", 0 0, L_0x2c9d7d0; 1 drivers +v0x2b476a0_0 .net "B", 0 0, L_0x2c9cbd0; 1 drivers +v0x2b47750_0 .net "BornB", 0 0, L_0x2c9d220; 1 drivers +v0x2b47810_0 .net "CINandAxorB", 0 0, L_0x2c9db20; 1 drivers +v0x2b478b0_0 .alias "Command", 2 0, v0x2bc67a0_0; +v0x2b47980_0 .net *"_s3", 0 0, L_0x2c9d550; 1 drivers +v0x2b47a20_0 .net *"_s5", 0 0, L_0x2c9d730; 1 drivers +v0x2b47b20_0 .net "carryin", 0 0, L_0x2c9cd00; 1 drivers +v0x2b47bc0_0 .net "carryout", 0 0, L_0x2c9dc10; 1 drivers +v0x2b47cd0_0 .net "nB", 0 0, L_0x2c9b8a0; 1 drivers +v0x2b47d50_0 .net "nCmd2", 0 0, L_0x2c9d490; 1 drivers +v0x2b47e50_0 .net "subtract", 0 0, L_0x2c9d5f0; 1 drivers +L_0x2c9d3f0 .part v0x2bc78e0_0, 0, 1; +L_0x2c9d550 .part v0x2bc78e0_0, 2, 1; +L_0x2c9d730 .part v0x2bc78e0_0, 0, 1; +S_0x2b46f80 .scope module, "mux0" "TwoInMux" 3 105, 3 8, S_0x2b46e90; + .timescale -9 -12; +L_0x2c9cf40/d .functor NOT 1, L_0x2c9d3f0, C4<0>, C4<0>, C4<0>; +L_0x2c9cf40 .delay (10000,10000,10000) L_0x2c9cf40/d; +L_0x2c9d000/d .functor AND 1, L_0x2c9cbd0, L_0x2c9cf40, C4<1>, C4<1>; +L_0x2c9d000 .delay (20000,20000,20000) L_0x2c9d000/d; +L_0x2c9d110/d .functor AND 1, L_0x2c9b8a0, L_0x2c9d3f0, C4<1>, C4<1>; +L_0x2c9d110 .delay (20000,20000,20000) L_0x2c9d110/d; +L_0x2c9d220/d .functor OR 1, L_0x2c9d000, L_0x2c9d110, C4<0>, C4<0>; +L_0x2c9d220 .delay (20000,20000,20000) L_0x2c9d220/d; +v0x2b47070_0 .net "S", 0 0, L_0x2c9d3f0; 1 drivers +v0x2b470f0_0 .alias "in0", 0 0, v0x2b476a0_0; +v0x2b47170_0 .alias "in1", 0 0, v0x2b47cd0_0; +v0x2b471f0_0 .net "nS", 0 0, L_0x2c9cf40; 1 drivers +v0x2b47270_0 .net "out0", 0 0, L_0x2c9d000; 1 drivers +v0x2b472f0_0 .net "out1", 0 0, L_0x2c9d110; 1 drivers +v0x2b47370_0 .alias "outfinal", 0 0, v0x2b47750_0; +S_0x2b45b80 .scope generate, "addbits[23]" "addbits[23]" 3 230, 3 230, S_0x2851a90; + .timescale -9 -12; +P_0x2b45598 .param/l "i" 3 230, +C4<010111>; +S_0x2b45cf0 .scope module, "attempt" "MiddleAddSubSLT" 3 232, 3 89, S_0x2b45b80; + .timescale -9 -12; +L_0x2c9cda0/d .functor NOT 1, L_0x2c9e0e0, C4<0>, C4<0>, C4<0>; +L_0x2c9cda0 .delay (10000,10000,10000) L_0x2c9cda0/d; +L_0x2c9e890/d .functor NOT 1, L_0x2c9e930, C4<0>, C4<0>, C4<0>; +L_0x2c9e890 .delay (10000,10000,10000) L_0x2c9e890/d; +L_0x2c9e9d0/d .functor AND 1, L_0x2c9eb10, L_0x2c9e890, C4<1>, C4<1>; +L_0x2c9e9d0 .delay (20000,20000,20000) L_0x2c9e9d0/d; +L_0x2c9ebb0/d .functor XOR 1, L_0x2c9e040, L_0x2c9e660, C4<0>, C4<0>; +L_0x2c9ebb0 .delay (40000,40000,40000) L_0x2c9ebb0/d; +L_0x2c9eca0/d .functor XOR 1, L_0x2c9ebb0, L_0x2c9e210, C4<0>, C4<0>; +L_0x2c9eca0 .delay (40000,40000,40000) L_0x2c9eca0/d; +L_0x2c9ed90/d .functor AND 1, L_0x2c9e040, L_0x2c9e660, C4<1>, C4<1>; +L_0x2c9ed90 .delay (20000,20000,20000) L_0x2c9ed90/d; +L_0x2c9ef00/d .functor AND 1, L_0x2c9ebb0, L_0x2c9e210, C4<1>, C4<1>; +L_0x2c9ef00 .delay (20000,20000,20000) L_0x2c9ef00/d; +L_0x2c9eff0/d .functor OR 1, L_0x2c9ed90, L_0x2c9ef00, C4<0>, C4<0>; +L_0x2c9eff0 .delay (20000,20000,20000) L_0x2c9eff0/d; +v0x2b46380_0 .net "A", 0 0, L_0x2c9e040; 1 drivers +v0x2b46440_0 .net "AandB", 0 0, L_0x2c9ed90; 1 drivers +v0x2b464e0_0 .net "AddSubSLTSum", 0 0, L_0x2c9eca0; 1 drivers +v0x2b46580_0 .net "AxorB", 0 0, L_0x2c9ebb0; 1 drivers +v0x2b46600_0 .net "B", 0 0, L_0x2c9e0e0; 1 drivers +v0x2b466b0_0 .net "BornB", 0 0, L_0x2c9e660; 1 drivers +v0x2b46770_0 .net "CINandAxorB", 0 0, L_0x2c9ef00; 1 drivers +v0x2b467f0_0 .alias "Command", 2 0, v0x2bc67a0_0; +v0x2b46870_0 .net *"_s3", 0 0, L_0x2c9e930; 1 drivers +v0x2b468f0_0 .net *"_s5", 0 0, L_0x2c9eb10; 1 drivers +v0x2b46990_0 .net "carryin", 0 0, L_0x2c9e210; 1 drivers +v0x2b46a30_0 .net "carryout", 0 0, L_0x2c9eff0; 1 drivers +v0x2b46ad0_0 .net "nB", 0 0, L_0x2c9cda0; 1 drivers +v0x2b46b80_0 .net "nCmd2", 0 0, L_0x2c9e890; 1 drivers +v0x2b46c80_0 .net "subtract", 0 0, L_0x2c9e9d0; 1 drivers +L_0x2c9e7f0 .part v0x2bc78e0_0, 0, 1; +L_0x2c9e930 .part v0x2bc78e0_0, 2, 1; +L_0x2c9eb10 .part v0x2bc78e0_0, 0, 1; +S_0x2b45de0 .scope module, "mux0" "TwoInMux" 3 105, 3 8, S_0x2b45cf0; + .timescale -9 -12; +L_0x2c9e420/d .functor NOT 1, L_0x2c9e7f0, C4<0>, C4<0>, C4<0>; +L_0x2c9e420 .delay (10000,10000,10000) L_0x2c9e420/d; +L_0x2c9e480/d .functor AND 1, L_0x2c9e0e0, L_0x2c9e420, C4<1>, C4<1>; +L_0x2c9e480 .delay (20000,20000,20000) L_0x2c9e480/d; +L_0x2c9e570/d .functor AND 1, L_0x2c9cda0, L_0x2c9e7f0, C4<1>, C4<1>; +L_0x2c9e570 .delay (20000,20000,20000) L_0x2c9e570/d; +L_0x2c9e660/d .functor OR 1, L_0x2c9e480, L_0x2c9e570, C4<0>, C4<0>; +L_0x2c9e660 .delay (20000,20000,20000) L_0x2c9e660/d; +v0x2b45ed0_0 .net "S", 0 0, L_0x2c9e7f0; 1 drivers +v0x2b45f70_0 .alias "in0", 0 0, v0x2b46600_0; +v0x2b46010_0 .alias "in1", 0 0, v0x2b46ad0_0; +v0x2b460b0_0 .net "nS", 0 0, L_0x2c9e420; 1 drivers +v0x2b46160_0 .net "out0", 0 0, L_0x2c9e480; 1 drivers +v0x2b46200_0 .net "out1", 0 0, L_0x2c9e570; 1 drivers +v0x2b462e0_0 .alias "outfinal", 0 0, v0x2b466b0_0; +S_0x2b449e0 .scope generate, "addbits[24]" "addbits[24]" 3 230, 3 230, S_0x2851a90; + .timescale -9 -12; +P_0x2b443f8 .param/l "i" 3 230, +C4<011000>; +S_0x2b44b50 .scope module, "attempt" "MiddleAddSubSLT" 3 232, 3 89, S_0x2b449e0; + .timescale -9 -12; +L_0x2c9e2b0/d .functor NOT 1, L_0x2c9f4a0, C4<0>, C4<0>, C4<0>; +L_0x2c9e2b0 .delay (10000,10000,10000) L_0x2c9e2b0/d; +L_0x2c9fc70/d .functor NOT 1, L_0x2c9fd10, C4<0>, C4<0>, C4<0>; +L_0x2c9fc70 .delay (10000,10000,10000) L_0x2c9fc70/d; +L_0x2c9fdb0/d .functor AND 1, L_0x2c9fef0, L_0x2c9fc70, C4<1>, C4<1>; +L_0x2c9fdb0 .delay (20000,20000,20000) L_0x2c9fdb0/d; +L_0x2c9ff90/d .functor XOR 1, L_0x2c9f400, L_0x2c9fa40, C4<0>, C4<0>; +L_0x2c9ff90 .delay (40000,40000,40000) L_0x2c9ff90/d; +L_0x2ca0080/d .functor XOR 1, L_0x2c9ff90, L_0x2c9f5d0, C4<0>, C4<0>; +L_0x2ca0080 .delay (40000,40000,40000) L_0x2ca0080/d; +L_0x2ca01a0/d .functor AND 1, L_0x2c9f400, L_0x2c9fa40, C4<1>, C4<1>; +L_0x2ca01a0 .delay (20000,20000,20000) L_0x2ca01a0/d; +L_0x2ca0340/d .functor AND 1, L_0x2c9ff90, L_0x2c9f5d0, C4<1>, C4<1>; +L_0x2ca0340 .delay (20000,20000,20000) L_0x2ca0340/d; +L_0x2ca0450/d .functor OR 1, L_0x2ca01a0, L_0x2ca0340, C4<0>, C4<0>; +L_0x2ca0450 .delay (20000,20000,20000) L_0x2ca0450/d; +v0x2b451e0_0 .net "A", 0 0, L_0x2c9f400; 1 drivers +v0x2b452a0_0 .net "AandB", 0 0, L_0x2ca01a0; 1 drivers +v0x2b45340_0 .net "AddSubSLTSum", 0 0, L_0x2ca0080; 1 drivers +v0x2b453e0_0 .net "AxorB", 0 0, L_0x2c9ff90; 1 drivers +v0x2b45460_0 .net "B", 0 0, L_0x2c9f4a0; 1 drivers +v0x2b45510_0 .net "BornB", 0 0, L_0x2c9fa40; 1 drivers +v0x2b455d0_0 .net "CINandAxorB", 0 0, L_0x2ca0340; 1 drivers +v0x2b45650_0 .alias "Command", 2 0, v0x2bc67a0_0; +v0x2b456d0_0 .net *"_s3", 0 0, L_0x2c9fd10; 1 drivers +v0x2b45750_0 .net *"_s5", 0 0, L_0x2c9fef0; 1 drivers +v0x2b457f0_0 .net "carryin", 0 0, L_0x2c9f5d0; 1 drivers +v0x2b45890_0 .net "carryout", 0 0, L_0x2ca0450; 1 drivers +v0x2b45930_0 .net "nB", 0 0, L_0x2c9e2b0; 1 drivers +v0x2b459e0_0 .net "nCmd2", 0 0, L_0x2c9fc70; 1 drivers +v0x2b45ae0_0 .net "subtract", 0 0, L_0x2c9fdb0; 1 drivers +L_0x2c9fbd0 .part v0x2bc78e0_0, 0, 1; +L_0x2c9fd10 .part v0x2bc78e0_0, 2, 1; +L_0x2c9fef0 .part v0x2bc78e0_0, 0, 1; +S_0x2b44c40 .scope module, "mux0" "TwoInMux" 3 105, 3 8, S_0x2b44b50; + .timescale -9 -12; +L_0x2c9f7c0/d .functor NOT 1, L_0x2c9fbd0, C4<0>, C4<0>, C4<0>; +L_0x2c9f7c0 .delay (10000,10000,10000) L_0x2c9f7c0/d; +L_0x2c9f860/d .functor AND 1, L_0x2c9f4a0, L_0x2c9f7c0, C4<1>, C4<1>; +L_0x2c9f860 .delay (20000,20000,20000) L_0x2c9f860/d; +L_0x2c9f950/d .functor AND 1, L_0x2c9e2b0, L_0x2c9fbd0, C4<1>, C4<1>; +L_0x2c9f950 .delay (20000,20000,20000) L_0x2c9f950/d; +L_0x2c9fa40/d .functor OR 1, L_0x2c9f860, L_0x2c9f950, C4<0>, C4<0>; +L_0x2c9fa40 .delay (20000,20000,20000) L_0x2c9fa40/d; +v0x2b44d30_0 .net "S", 0 0, L_0x2c9fbd0; 1 drivers +v0x2b44dd0_0 .alias "in0", 0 0, v0x2b45460_0; +v0x2b44e70_0 .alias "in1", 0 0, v0x2b45930_0; +v0x2b44f10_0 .net "nS", 0 0, L_0x2c9f7c0; 1 drivers +v0x2b44fc0_0 .net "out0", 0 0, L_0x2c9f860; 1 drivers +v0x2b45060_0 .net "out1", 0 0, L_0x2c9f950; 1 drivers +v0x2b45140_0 .alias "outfinal", 0 0, v0x2b45510_0; +S_0x2b43840 .scope generate, "addbits[25]" "addbits[25]" 3 230, 3 230, S_0x2851a90; + .timescale -9 -12; +P_0x2b43258 .param/l "i" 3 230, +C4<011001>; +S_0x2b439b0 .scope module, "attempt" "MiddleAddSubSLT" 3 232, 3 89, S_0x2b43840; + .timescale -9 -12; +L_0x2c9f670/d .functor NOT 1, L_0x2ca0920, C4<0>, C4<0>, C4<0>; +L_0x2c9f670 .delay (10000,10000,10000) L_0x2c9f670/d; +L_0x2ca1140/d .functor NOT 1, L_0x2ca1200, C4<0>, C4<0>, C4<0>; +L_0x2ca1140 .delay (10000,10000,10000) L_0x2ca1140/d; +L_0x2ca12a0/d .functor AND 1, L_0x2ca13e0, L_0x2ca1140, C4<1>, C4<1>; +L_0x2ca12a0 .delay (20000,20000,20000) L_0x2ca12a0/d; +L_0x2ca1480/d .functor XOR 1, L_0x2ca0880, L_0x2ca0ef0, C4<0>, C4<0>; +L_0x2ca1480 .delay (40000,40000,40000) L_0x2ca1480/d; +L_0x2ca1570/d .functor XOR 1, L_0x2ca1480, L_0x2ca0a50, C4<0>, C4<0>; +L_0x2ca1570 .delay (40000,40000,40000) L_0x2ca1570/d; +L_0x2ca1690/d .functor AND 1, L_0x2ca0880, L_0x2ca0ef0, C4<1>, C4<1>; +L_0x2ca1690 .delay (20000,20000,20000) L_0x2ca1690/d; +L_0x2ca1830/d .functor AND 1, L_0x2ca1480, L_0x2ca0a50, C4<1>, C4<1>; +L_0x2ca1830 .delay (20000,20000,20000) L_0x2ca1830/d; +L_0x2ca1940/d .functor OR 1, L_0x2ca1690, L_0x2ca1830, C4<0>, C4<0>; +L_0x2ca1940 .delay (20000,20000,20000) L_0x2ca1940/d; +v0x2b44040_0 .net "A", 0 0, L_0x2ca0880; 1 drivers +v0x2b44100_0 .net "AandB", 0 0, L_0x2ca1690; 1 drivers +v0x2b441a0_0 .net "AddSubSLTSum", 0 0, L_0x2ca1570; 1 drivers +v0x2b44240_0 .net "AxorB", 0 0, L_0x2ca1480; 1 drivers +v0x2b442c0_0 .net "B", 0 0, L_0x2ca0920; 1 drivers +v0x2b44370_0 .net "BornB", 0 0, L_0x2ca0ef0; 1 drivers +v0x2b44430_0 .net "CINandAxorB", 0 0, L_0x2ca1830; 1 drivers +v0x2b444b0_0 .alias "Command", 2 0, v0x2bc67a0_0; +v0x2b44530_0 .net *"_s3", 0 0, L_0x2ca1200; 1 drivers +v0x2b445b0_0 .net *"_s5", 0 0, L_0x2ca13e0; 1 drivers +v0x2b44650_0 .net "carryin", 0 0, L_0x2ca0a50; 1 drivers +v0x2b446f0_0 .net "carryout", 0 0, L_0x2ca1940; 1 drivers +v0x2b44790_0 .net "nB", 0 0, L_0x2c9f670; 1 drivers +v0x2b44840_0 .net "nCmd2", 0 0, L_0x2ca1140; 1 drivers +v0x2b44940_0 .net "subtract", 0 0, L_0x2ca12a0; 1 drivers +L_0x2ca10a0 .part v0x2bc78e0_0, 0, 1; +L_0x2ca1200 .part v0x2bc78e0_0, 2, 1; +L_0x2ca13e0 .part v0x2bc78e0_0, 0, 1; +S_0x2b43aa0 .scope module, "mux0" "TwoInMux" 3 105, 3 8, S_0x2b439b0; + .timescale -9 -12; +L_0x2ca0c70/d .functor NOT 1, L_0x2ca10a0, C4<0>, C4<0>, C4<0>; +L_0x2ca0c70 .delay (10000,10000,10000) L_0x2ca0c70/d; +L_0x2ca0d10/d .functor AND 1, L_0x2ca0920, L_0x2ca0c70, C4<1>, C4<1>; +L_0x2ca0d10 .delay (20000,20000,20000) L_0x2ca0d10/d; +L_0x2ca0e00/d .functor AND 1, L_0x2c9f670, L_0x2ca10a0, C4<1>, C4<1>; +L_0x2ca0e00 .delay (20000,20000,20000) L_0x2ca0e00/d; +L_0x2ca0ef0/d .functor OR 1, L_0x2ca0d10, L_0x2ca0e00, C4<0>, C4<0>; +L_0x2ca0ef0 .delay (20000,20000,20000) L_0x2ca0ef0/d; +v0x2b43b90_0 .net "S", 0 0, L_0x2ca10a0; 1 drivers +v0x2b43c30_0 .alias "in0", 0 0, v0x2b442c0_0; +v0x2b43cd0_0 .alias "in1", 0 0, v0x2b44790_0; +v0x2b43d70_0 .net "nS", 0 0, L_0x2ca0c70; 1 drivers +v0x2b43e20_0 .net "out0", 0 0, L_0x2ca0d10; 1 drivers +v0x2b43ec0_0 .net "out1", 0 0, L_0x2ca0e00; 1 drivers +v0x2b43fa0_0 .alias "outfinal", 0 0, v0x2b44370_0; +S_0x2b426a0 .scope generate, "addbits[26]" "addbits[26]" 3 230, 3 230, S_0x2851a90; + .timescale -9 -12; +P_0x2b420b8 .param/l "i" 3 230, +C4<011010>; +S_0x2b42810 .scope module, "attempt" "MiddleAddSubSLT" 3 232, 3 89, S_0x2b426a0; + .timescale -9 -12; +L_0x2ca0af0/d .functor NOT 1, L_0x2c05620, C4<0>, C4<0>, C4<0>; +L_0x2ca0af0 .delay (10000,10000,10000) L_0x2ca0af0/d; +L_0x2c059f0/d .functor NOT 1, L_0x2c05a70, C4<0>, C4<0>, C4<0>; +L_0x2c059f0 .delay (10000,10000,10000) L_0x2c059f0/d; +L_0x2c05b10/d .functor AND 1, L_0x2c05c50, L_0x2c059f0, C4<1>, C4<1>; +L_0x2c05b10 .delay (20000,20000,20000) L_0x2c05b10/d; +L_0x2c05cf0/d .functor XOR 1, L_0x2c05580, L_0x2ca1f30, C4<0>, C4<0>; +L_0x2c05cf0 .delay (40000,40000,40000) L_0x2c05cf0/d; +L_0x2c05de0/d .functor XOR 1, L_0x2c05cf0, L_0x2c05750, C4<0>, C4<0>; +L_0x2c05de0 .delay (40000,40000,40000) L_0x2c05de0/d; +L_0x2c05ed0/d .functor AND 1, L_0x2c05580, L_0x2ca1f30, C4<1>, C4<1>; +L_0x2c05ed0 .delay (20000,20000,20000) L_0x2c05ed0/d; +L_0x2c06070/d .functor AND 1, L_0x2c05cf0, L_0x2c05750, C4<1>, C4<1>; +L_0x2c06070 .delay (20000,20000,20000) L_0x2c06070/d; +L_0x2c06180/d .functor OR 1, L_0x2c05ed0, L_0x2c06070, C4<0>, C4<0>; +L_0x2c06180 .delay (20000,20000,20000) L_0x2c06180/d; +v0x2b42ea0_0 .net "A", 0 0, L_0x2c05580; 1 drivers +v0x2b42f60_0 .net "AandB", 0 0, L_0x2c05ed0; 1 drivers +v0x2b43000_0 .net "AddSubSLTSum", 0 0, L_0x2c05de0; 1 drivers +v0x2b430a0_0 .net "AxorB", 0 0, L_0x2c05cf0; 1 drivers +v0x2b43120_0 .net "B", 0 0, L_0x2c05620; 1 drivers +v0x2b431d0_0 .net "BornB", 0 0, L_0x2ca1f30; 1 drivers +v0x2b43290_0 .net "CINandAxorB", 0 0, L_0x2c06070; 1 drivers +v0x2b43310_0 .alias "Command", 2 0, v0x2bc67a0_0; +v0x2b43390_0 .net *"_s3", 0 0, L_0x2c05a70; 1 drivers +v0x2b43410_0 .net *"_s5", 0 0, L_0x2c05c50; 1 drivers +v0x2b434b0_0 .net "carryin", 0 0, L_0x2c05750; 1 drivers +v0x2b43550_0 .net "carryout", 0 0, L_0x2c06180; 1 drivers +v0x2b435f0_0 .net "nB", 0 0, L_0x2ca0af0; 1 drivers +v0x2b436a0_0 .net "nCmd2", 0 0, L_0x2c059f0; 1 drivers +v0x2b437a0_0 .net "subtract", 0 0, L_0x2c05b10; 1 drivers +L_0x2c05950 .part v0x2bc78e0_0, 0, 1; +L_0x2c05a70 .part v0x2bc78e0_0, 2, 1; +L_0x2c05c50 .part v0x2bc78e0_0, 0, 1; +S_0x2b42900 .scope module, "mux0" "TwoInMux" 3 105, 3 8, S_0x2b42810; + .timescale -9 -12; +L_0x2ca0bc0/d .functor NOT 1, L_0x2c05950, C4<0>, C4<0>, C4<0>; +L_0x2ca0bc0 .delay (10000,10000,10000) L_0x2ca0bc0/d; +L_0x2ca1d10/d .functor AND 1, L_0x2c05620, L_0x2ca0bc0, C4<1>, C4<1>; +L_0x2ca1d10 .delay (20000,20000,20000) L_0x2ca1d10/d; +L_0x2ca1e20/d .functor AND 1, L_0x2ca0af0, L_0x2c05950, C4<1>, C4<1>; +L_0x2ca1e20 .delay (20000,20000,20000) L_0x2ca1e20/d; +L_0x2ca1f30/d .functor OR 1, L_0x2ca1d10, L_0x2ca1e20, C4<0>, C4<0>; +L_0x2ca1f30 .delay (20000,20000,20000) L_0x2ca1f30/d; +v0x2b429f0_0 .net "S", 0 0, L_0x2c05950; 1 drivers +v0x2b42a90_0 .alias "in0", 0 0, v0x2b43120_0; +v0x2b42b30_0 .alias "in1", 0 0, v0x2b435f0_0; +v0x2b42bd0_0 .net "nS", 0 0, L_0x2ca0bc0; 1 drivers +v0x2b42c80_0 .net "out0", 0 0, L_0x2ca1d10; 1 drivers +v0x2b42d20_0 .net "out1", 0 0, L_0x2ca1e20; 1 drivers +v0x2b42e00_0 .alias "outfinal", 0 0, v0x2b431d0_0; +S_0x2b41500 .scope generate, "addbits[27]" "addbits[27]" 3 230, 3 230, S_0x2851a90; + .timescale -9 -12; +P_0x2b40f18 .param/l "i" 3 230, +C4<011011>; +S_0x2b41670 .scope module, "attempt" "MiddleAddSubSLT" 3 232, 3 89, S_0x2b41500; + .timescale -9 -12; +L_0x2c057f0/d .functor NOT 1, L_0x2bedff0, C4<0>, C4<0>, C4<0>; +L_0x2c057f0 .delay (10000,10000,10000) L_0x2c057f0/d; +L_0x2ca4af0/d .functor NOT 1, L_0x2ca4bb0, C4<0>, C4<0>, C4<0>; +L_0x2ca4af0 .delay (10000,10000,10000) L_0x2ca4af0/d; +L_0x2ca4c50/d .functor AND 1, L_0x2ca4d90, L_0x2ca4af0, C4<1>, C4<1>; +L_0x2ca4c50 .delay (20000,20000,20000) L_0x2ca4c50/d; +L_0x2ca4e30/d .functor XOR 1, L_0x2bedf50, L_0x2ca4880, C4<0>, C4<0>; +L_0x2ca4e30 .delay (40000,40000,40000) L_0x2ca4e30/d; +L_0x2ca4f20/d .functor XOR 1, L_0x2ca4e30, L_0x2bee120, C4<0>, C4<0>; +L_0x2ca4f20 .delay (40000,40000,40000) L_0x2ca4f20/d; +L_0x2ca5040/d .functor AND 1, L_0x2bedf50, L_0x2ca4880, C4<1>, C4<1>; +L_0x2ca5040 .delay (20000,20000,20000) L_0x2ca5040/d; +L_0x2ca51e0/d .functor AND 1, L_0x2ca4e30, L_0x2bee120, C4<1>, C4<1>; +L_0x2ca51e0 .delay (20000,20000,20000) L_0x2ca51e0/d; +L_0x2ca52f0/d .functor OR 1, L_0x2ca5040, L_0x2ca51e0, C4<0>, C4<0>; +L_0x2ca52f0 .delay (20000,20000,20000) L_0x2ca52f0/d; +v0x2b41d00_0 .net "A", 0 0, L_0x2bedf50; 1 drivers +v0x2b41dc0_0 .net "AandB", 0 0, L_0x2ca5040; 1 drivers +v0x2b41e60_0 .net "AddSubSLTSum", 0 0, L_0x2ca4f20; 1 drivers +v0x2b41f00_0 .net "AxorB", 0 0, L_0x2ca4e30; 1 drivers +v0x2b41f80_0 .net "B", 0 0, L_0x2bedff0; 1 drivers +v0x2b42030_0 .net "BornB", 0 0, L_0x2ca4880; 1 drivers +v0x2b420f0_0 .net "CINandAxorB", 0 0, L_0x2ca51e0; 1 drivers +v0x2b42170_0 .alias "Command", 2 0, v0x2bc67a0_0; +v0x2b421f0_0 .net *"_s3", 0 0, L_0x2ca4bb0; 1 drivers +v0x2b42270_0 .net *"_s5", 0 0, L_0x2ca4d90; 1 drivers +v0x2b42310_0 .net "carryin", 0 0, L_0x2bee120; 1 drivers +v0x2b423b0_0 .net "carryout", 0 0, L_0x2ca52f0; 1 drivers +v0x2b42450_0 .net "nB", 0 0, L_0x2c057f0; 1 drivers +v0x2b42500_0 .net "nCmd2", 0 0, L_0x2ca4af0; 1 drivers +v0x2b42600_0 .net "subtract", 0 0, L_0x2ca4c50; 1 drivers +L_0x2ca4a50 .part v0x2bc78e0_0, 0, 1; +L_0x2ca4bb0 .part v0x2bc78e0_0, 2, 1; +L_0x2ca4d90 .part v0x2bc78e0_0, 0, 1; +S_0x2b41760 .scope module, "mux0" "TwoInMux" 3 105, 3 8, S_0x2b41670; + .timescale -9 -12; +L_0x2ca4680/d .functor NOT 1, L_0x2ca4a50, C4<0>, C4<0>, C4<0>; +L_0x2ca4680 .delay (10000,10000,10000) L_0x2ca4680/d; +L_0x2ca46e0/d .functor AND 1, L_0x2bedff0, L_0x2ca4680, C4<1>, C4<1>; +L_0x2ca46e0 .delay (20000,20000,20000) L_0x2ca46e0/d; +L_0x2ca4790/d .functor AND 1, L_0x2c057f0, L_0x2ca4a50, C4<1>, C4<1>; +L_0x2ca4790 .delay (20000,20000,20000) L_0x2ca4790/d; +L_0x2ca4880/d .functor OR 1, L_0x2ca46e0, L_0x2ca4790, C4<0>, C4<0>; +L_0x2ca4880 .delay (20000,20000,20000) L_0x2ca4880/d; +v0x2b41850_0 .net "S", 0 0, L_0x2ca4a50; 1 drivers +v0x2b418f0_0 .alias "in0", 0 0, v0x2b41f80_0; +v0x2b41990_0 .alias "in1", 0 0, v0x2b42450_0; +v0x2b41a30_0 .net "nS", 0 0, L_0x2ca4680; 1 drivers +v0x2b41ae0_0 .net "out0", 0 0, L_0x2ca46e0; 1 drivers +v0x2b41b80_0 .net "out1", 0 0, L_0x2ca4790; 1 drivers +v0x2b41c60_0 .alias "outfinal", 0 0, v0x2b42030_0; +S_0x2b40360 .scope generate, "addbits[28]" "addbits[28]" 3 230, 3 230, S_0x2851a90; + .timescale -9 -12; +P_0x2b3fd78 .param/l "i" 3 230, +C4<011100>; +S_0x2b404d0 .scope module, "attempt" "MiddleAddSubSLT" 3 232, 3 89, S_0x2b40360; + .timescale -9 -12; +L_0x2bee1c0/d .functor NOT 1, L_0x2ca64d0, C4<0>, C4<0>, C4<0>; +L_0x2bee1c0 .delay (10000,10000,10000) L_0x2bee1c0/d; +L_0x2ca5740/d .functor NOT 1, L_0x2ca5800, C4<0>, C4<0>, C4<0>; +L_0x2ca5740 .delay (10000,10000,10000) L_0x2ca5740/d; +L_0x2ca58a0/d .functor AND 1, L_0x2ca59e0, L_0x2ca5740, C4<1>, C4<1>; +L_0x2ca58a0 .delay (20000,20000,20000) L_0x2ca58a0/d; +L_0x2ca5a80/d .functor XOR 1, L_0x2ca6430, L_0x2ca4510, C4<0>, C4<0>; +L_0x2ca5a80 .delay (40000,40000,40000) L_0x2ca5a80/d; +L_0x2ca68b0/d .functor XOR 1, L_0x2ca5a80, L_0x2ca6600, C4<0>, C4<0>; +L_0x2ca68b0 .delay (40000,40000,40000) L_0x2ca68b0/d; +L_0x2ca69a0/d .functor AND 1, L_0x2ca6430, L_0x2ca4510, C4<1>, C4<1>; +L_0x2ca69a0 .delay (20000,20000,20000) L_0x2ca69a0/d; +L_0x2ca6b10/d .functor AND 1, L_0x2ca5a80, L_0x2ca6600, C4<1>, C4<1>; +L_0x2ca6b10 .delay (20000,20000,20000) L_0x2ca6b10/d; +L_0x2ca6c00/d .functor OR 1, L_0x2ca69a0, L_0x2ca6b10, C4<0>, C4<0>; +L_0x2ca6c00 .delay (20000,20000,20000) L_0x2ca6c00/d; +v0x2b40b60_0 .net "A", 0 0, L_0x2ca6430; 1 drivers +v0x2b40c20_0 .net "AandB", 0 0, L_0x2ca69a0; 1 drivers +v0x2b40cc0_0 .net "AddSubSLTSum", 0 0, L_0x2ca68b0; 1 drivers +v0x2b40d60_0 .net "AxorB", 0 0, L_0x2ca5a80; 1 drivers +v0x2b40de0_0 .net "B", 0 0, L_0x2ca64d0; 1 drivers +v0x2b40e90_0 .net "BornB", 0 0, L_0x2ca4510; 1 drivers +v0x2b40f50_0 .net "CINandAxorB", 0 0, L_0x2ca6b10; 1 drivers +v0x2b40fd0_0 .alias "Command", 2 0, v0x2bc67a0_0; +v0x2b41050_0 .net *"_s3", 0 0, L_0x2ca5800; 1 drivers +v0x2b410d0_0 .net *"_s5", 0 0, L_0x2ca59e0; 1 drivers +v0x2b41170_0 .net "carryin", 0 0, L_0x2ca6600; 1 drivers +v0x2b41210_0 .net "carryout", 0 0, L_0x2ca6c00; 1 drivers +v0x2b412b0_0 .net "nB", 0 0, L_0x2bee1c0; 1 drivers +v0x2b41360_0 .net "nCmd2", 0 0, L_0x2ca5740; 1 drivers +v0x2b41460_0 .net "subtract", 0 0, L_0x2ca58a0; 1 drivers +L_0x2ca56a0 .part v0x2bc78e0_0, 0, 1; +L_0x2ca5800 .part v0x2bc78e0_0, 2, 1; +L_0x2ca59e0 .part v0x2bc78e0_0, 0, 1; +S_0x2b405c0 .scope module, "mux0" "TwoInMux" 3 105, 3 8, S_0x2b404d0; + .timescale -9 -12; +L_0x2ca4230/d .functor NOT 1, L_0x2ca56a0, C4<0>, C4<0>, C4<0>; +L_0x2ca4230 .delay (10000,10000,10000) L_0x2ca4230/d; +L_0x2ca42f0/d .functor AND 1, L_0x2ca64d0, L_0x2ca4230, C4<1>, C4<1>; +L_0x2ca42f0 .delay (20000,20000,20000) L_0x2ca42f0/d; +L_0x2ca4400/d .functor AND 1, L_0x2bee1c0, L_0x2ca56a0, C4<1>, C4<1>; +L_0x2ca4400 .delay (20000,20000,20000) L_0x2ca4400/d; +L_0x2ca4510/d .functor OR 1, L_0x2ca42f0, L_0x2ca4400, C4<0>, C4<0>; +L_0x2ca4510 .delay (20000,20000,20000) L_0x2ca4510/d; +v0x2b406b0_0 .net "S", 0 0, L_0x2ca56a0; 1 drivers +v0x2b40750_0 .alias "in0", 0 0, v0x2b40de0_0; +v0x2b407f0_0 .alias "in1", 0 0, v0x2b412b0_0; +v0x2b40890_0 .net "nS", 0 0, L_0x2ca4230; 1 drivers +v0x2b40940_0 .net "out0", 0 0, L_0x2ca42f0; 1 drivers +v0x2b409e0_0 .net "out1", 0 0, L_0x2ca4400; 1 drivers +v0x2b40ac0_0 .alias "outfinal", 0 0, v0x2b40e90_0; +S_0x2b3f1c0 .scope generate, "addbits[29]" "addbits[29]" 3 230, 3 230, S_0x2851a90; + .timescale -9 -12; +P_0x2b3ebd8 .param/l "i" 3 230, +C4<011101>; +S_0x2b3f330 .scope module, "attempt" "MiddleAddSubSLT" 3 232, 3 89, S_0x2b3f1c0; + .timescale -9 -12; +L_0x2ca66a0/d .functor NOT 1, L_0x2ca70b0, C4<0>, C4<0>, C4<0>; +L_0x2ca66a0 .delay (10000,10000,10000) L_0x2ca66a0/d; +L_0x2ca78c0/d .functor NOT 1, L_0x2ca7980, C4<0>, C4<0>, C4<0>; +L_0x2ca78c0 .delay (10000,10000,10000) L_0x2ca78c0/d; +L_0x2ca7a20/d .functor AND 1, L_0x2ca7b60, L_0x2ca78c0, C4<1>, C4<1>; +L_0x2ca7a20 .delay (20000,20000,20000) L_0x2ca7a20/d; +L_0x2ca7c00/d .functor XOR 1, L_0x2ca7010, L_0x2ca7690, C4<0>, C4<0>; +L_0x2ca7c00 .delay (40000,40000,40000) L_0x2ca7c00/d; +L_0x2ca7d20/d .functor XOR 1, L_0x2ca7c00, L_0x2ca71e0, C4<0>, C4<0>; +L_0x2ca7d20 .delay (40000,40000,40000) L_0x2ca7d20/d; +L_0x2ca7e40/d .functor AND 1, L_0x2ca7010, L_0x2ca7690, C4<1>, C4<1>; +L_0x2ca7e40 .delay (20000,20000,20000) L_0x2ca7e40/d; +L_0x2ca7fe0/d .functor AND 1, L_0x2ca7c00, L_0x2ca71e0, C4<1>, C4<1>; +L_0x2ca7fe0 .delay (20000,20000,20000) L_0x2ca7fe0/d; +L_0x2ca80d0/d .functor OR 1, L_0x2ca7e40, L_0x2ca7fe0, C4<0>, C4<0>; +L_0x2ca80d0 .delay (20000,20000,20000) L_0x2ca80d0/d; +v0x2b3f9c0_0 .net "A", 0 0, L_0x2ca7010; 1 drivers +v0x2b3fa80_0 .net "AandB", 0 0, L_0x2ca7e40; 1 drivers +v0x2b3fb20_0 .net "AddSubSLTSum", 0 0, L_0x2ca7d20; 1 drivers +v0x2b3fbc0_0 .net "AxorB", 0 0, L_0x2ca7c00; 1 drivers +v0x2b3fc40_0 .net "B", 0 0, L_0x2ca70b0; 1 drivers +v0x2b3fcf0_0 .net "BornB", 0 0, L_0x2ca7690; 1 drivers +v0x2b3fdb0_0 .net "CINandAxorB", 0 0, L_0x2ca7fe0; 1 drivers +v0x2b3fe30_0 .alias "Command", 2 0, v0x2bc67a0_0; +v0x2b3feb0_0 .net *"_s3", 0 0, L_0x2ca7980; 1 drivers +v0x2b3ff30_0 .net *"_s5", 0 0, L_0x2ca7b60; 1 drivers +v0x2b3ffd0_0 .net "carryin", 0 0, L_0x2ca71e0; 1 drivers +v0x2b40070_0 .net "carryout", 0 0, L_0x2ca80d0; 1 drivers +v0x2b40110_0 .net "nB", 0 0, L_0x2ca66a0; 1 drivers +v0x2b401c0_0 .net "nCmd2", 0 0, L_0x2ca78c0; 1 drivers +v0x2b402c0_0 .net "subtract", 0 0, L_0x2ca7a20; 1 drivers +L_0x2ca7820 .part v0x2bc78e0_0, 0, 1; +L_0x2ca7980 .part v0x2bc78e0_0, 2, 1; +L_0x2ca7b60 .part v0x2bc78e0_0, 0, 1; +S_0x2b3f420 .scope module, "mux0" "TwoInMux" 3 105, 3 8, S_0x2b3f330; + .timescale -9 -12; +L_0x2ca6800/d .functor NOT 1, L_0x2ca7820, C4<0>, C4<0>, C4<0>; +L_0x2ca6800 .delay (10000,10000,10000) L_0x2ca6800/d; +L_0x2ca74b0/d .functor AND 1, L_0x2ca70b0, L_0x2ca6800, C4<1>, C4<1>; +L_0x2ca74b0 .delay (20000,20000,20000) L_0x2ca74b0/d; +L_0x2ca75a0/d .functor AND 1, L_0x2ca66a0, L_0x2ca7820, C4<1>, C4<1>; +L_0x2ca75a0 .delay (20000,20000,20000) L_0x2ca75a0/d; +L_0x2ca7690/d .functor OR 1, L_0x2ca74b0, L_0x2ca75a0, C4<0>, C4<0>; +L_0x2ca7690 .delay (20000,20000,20000) L_0x2ca7690/d; +v0x2b3f510_0 .net "S", 0 0, L_0x2ca7820; 1 drivers +v0x2b3f5b0_0 .alias "in0", 0 0, v0x2b3fc40_0; +v0x2b3f650_0 .alias "in1", 0 0, v0x2b40110_0; +v0x2b3f6f0_0 .net "nS", 0 0, L_0x2ca6800; 1 drivers +v0x2b3f7a0_0 .net "out0", 0 0, L_0x2ca74b0; 1 drivers +v0x2b3f840_0 .net "out1", 0 0, L_0x2ca75a0; 1 drivers +v0x2b3f920_0 .alias "outfinal", 0 0, v0x2b3fcf0_0; +S_0x2b3e020 .scope generate, "addbits[30]" "addbits[30]" 3 230, 3 230, S_0x2851a90; + .timescale -9 -12; +P_0x2b3d918 .param/l "i" 3 230, +C4<011110>; +S_0x2b3e190 .scope module, "attempt" "MiddleAddSubSLT" 3 232, 3 89, S_0x2b3e020; + .timescale -9 -12; +L_0x2ca7280/d .functor NOT 1, L_0x2ca85a0, C4<0>, C4<0>, C4<0>; +L_0x2ca7280 .delay (10000,10000,10000) L_0x2ca7280/d; +L_0x2ca8de0/d .functor NOT 1, L_0x2ca8e80, C4<0>, C4<0>, C4<0>; +L_0x2ca8de0 .delay (10000,10000,10000) L_0x2ca8de0/d; +L_0x2ca8f20/d .functor AND 1, L_0x2ca9060, L_0x2ca8de0, C4<1>, C4<1>; +L_0x2ca8f20 .delay (20000,20000,20000) L_0x2ca8f20/d; +L_0x2ca9100/d .functor XOR 1, L_0x2ca8500, L_0x2ca8bb0, C4<0>, C4<0>; +L_0x2ca9100 .delay (40000,40000,40000) L_0x2ca9100/d; +L_0x2ca9220/d .functor XOR 1, L_0x2ca9100, L_0x2ca86d0, C4<0>, C4<0>; +L_0x2ca9220 .delay (40000,40000,40000) L_0x2ca9220/d; +L_0x2ca9340/d .functor AND 1, L_0x2ca8500, L_0x2ca8bb0, C4<1>, C4<1>; +L_0x2ca9340 .delay (20000,20000,20000) L_0x2ca9340/d; +L_0x2ca94e0/d .functor AND 1, L_0x2ca9100, L_0x2ca86d0, C4<1>, C4<1>; +L_0x2ca94e0 .delay (20000,20000,20000) L_0x2ca94e0/d; +L_0x2ca95d0/d .functor OR 1, L_0x2ca9340, L_0x2ca94e0, C4<0>, C4<0>; +L_0x2ca95d0 .delay (20000,20000,20000) L_0x2ca95d0/d; +v0x2b3e820_0 .net "A", 0 0, L_0x2ca8500; 1 drivers +v0x2b3e8e0_0 .net "AandB", 0 0, L_0x2ca9340; 1 drivers +v0x2b3e980_0 .net "AddSubSLTSum", 0 0, L_0x2ca9220; 1 drivers +v0x2b3ea20_0 .net "AxorB", 0 0, L_0x2ca9100; 1 drivers +v0x2b3eaa0_0 .net "B", 0 0, L_0x2ca85a0; 1 drivers +v0x2b3eb50_0 .net "BornB", 0 0, L_0x2ca8bb0; 1 drivers +v0x2b3ec10_0 .net "CINandAxorB", 0 0, L_0x2ca94e0; 1 drivers +v0x2b3ec90_0 .alias "Command", 2 0, v0x2bc67a0_0; +v0x2b3ed10_0 .net *"_s3", 0 0, L_0x2ca8e80; 1 drivers +v0x2b3ed90_0 .net *"_s5", 0 0, L_0x2ca9060; 1 drivers +v0x2b3ee30_0 .net "carryin", 0 0, L_0x2ca86d0; 1 drivers +v0x2b3eed0_0 .net "carryout", 0 0, L_0x2ca95d0; 1 drivers +v0x2b3ef70_0 .net "nB", 0 0, L_0x2ca7280; 1 drivers +v0x2b3f020_0 .net "nCmd2", 0 0, L_0x2ca8de0; 1 drivers +v0x2b3f120_0 .net "subtract", 0 0, L_0x2ca8f20; 1 drivers +L_0x2ca8d40 .part v0x2bc78e0_0, 0, 1; +L_0x2ca8e80 .part v0x2bc78e0_0, 2, 1; +L_0x2ca9060 .part v0x2bc78e0_0, 0, 1; +S_0x2b3e280 .scope module, "mux0" "TwoInMux" 3 105, 3 8, S_0x2b3e190; + .timescale -9 -12; +L_0x2ca73e0/d .functor NOT 1, L_0x2ca8d40, C4<0>, C4<0>, C4<0>; +L_0x2ca73e0 .delay (10000,10000,10000) L_0x2ca73e0/d; +L_0x2ca89d0/d .functor AND 1, L_0x2ca85a0, L_0x2ca73e0, C4<1>, C4<1>; +L_0x2ca89d0 .delay (20000,20000,20000) L_0x2ca89d0/d; +L_0x2ca8ac0/d .functor AND 1, L_0x2ca7280, L_0x2ca8d40, C4<1>, C4<1>; +L_0x2ca8ac0 .delay (20000,20000,20000) L_0x2ca8ac0/d; +L_0x2ca8bb0/d .functor OR 1, L_0x2ca89d0, L_0x2ca8ac0, C4<0>, C4<0>; +L_0x2ca8bb0 .delay (20000,20000,20000) L_0x2ca8bb0/d; +v0x2b3e370_0 .net "S", 0 0, L_0x2ca8d40; 1 drivers +v0x2b3e410_0 .alias "in0", 0 0, v0x2b3eaa0_0; +v0x2b3e4b0_0 .alias "in1", 0 0, v0x2b3ef70_0; +v0x2b3e550_0 .net "nS", 0 0, L_0x2ca73e0; 1 drivers +v0x2b3e600_0 .net "out0", 0 0, L_0x2ca89d0; 1 drivers +v0x2b3e6a0_0 .net "out1", 0 0, L_0x2ca8ac0; 1 drivers +v0x2b3e780_0 .alias "outfinal", 0 0, v0x2b3eb50_0; +S_0x2b3cdc0 .scope generate, "addbits[31]" "addbits[31]" 3 230, 3 230, S_0x2851a90; + .timescale -9 -12; +P_0x2851c08 .param/l "i" 3 230, +C4<011111>; +S_0x2b3cef0 .scope module, "attempt" "MiddleAddSubSLT" 3 232, 3 89, S_0x2b3cdc0; + .timescale -9 -12; +L_0x2ca8770/d .functor NOT 1, L_0x2ca9aa0, C4<0>, C4<0>, C4<0>; +L_0x2ca8770 .delay (10000,10000,10000) L_0x2ca8770/d; +L_0x2caa2d0/d .functor NOT 1, L_0x2caa370, C4<0>, C4<0>, C4<0>; +L_0x2caa2d0 .delay (10000,10000,10000) L_0x2caa2d0/d; +L_0x2caa410/d .functor AND 1, L_0x2caa550, L_0x2caa2d0, C4<1>, C4<1>; +L_0x2caa410 .delay (20000,20000,20000) L_0x2caa410/d; +L_0x2caa5f0/d .functor XOR 1, L_0x2ca9a00, L_0x2caa0a0, C4<0>, C4<0>; +L_0x2caa5f0 .delay (40000,40000,40000) L_0x2caa5f0/d; +L_0x2caa710/d .functor XOR 1, L_0x2caa5f0, L_0x2ca9bd0, C4<0>, C4<0>; +L_0x2caa710 .delay (40000,40000,40000) L_0x2caa710/d; +L_0x2caa830/d .functor AND 1, L_0x2ca9a00, L_0x2caa0a0, C4<1>, C4<1>; +L_0x2caa830 .delay (20000,20000,20000) L_0x2caa830/d; +L_0x2caa9d0/d .functor AND 1, L_0x2caa5f0, L_0x2ca9bd0, C4<1>, C4<1>; +L_0x2caa9d0 .delay (20000,20000,20000) L_0x2caa9d0/d; +L_0x2caaac0/d .functor OR 1, L_0x2caa830, L_0x2caa9d0, C4<0>, C4<0>; +L_0x2caaac0 .delay (20000,20000,20000) L_0x2caaac0/d; +v0x2b3d560_0 .net "A", 0 0, L_0x2ca9a00; 1 drivers +v0x2b3d620_0 .net "AandB", 0 0, L_0x2caa830; 1 drivers +v0x2b3d6c0_0 .net "AddSubSLTSum", 0 0, L_0x2caa710; 1 drivers +v0x2b3d760_0 .net "AxorB", 0 0, L_0x2caa5f0; 1 drivers +v0x2b3d7e0_0 .net "B", 0 0, L_0x2ca9aa0; 1 drivers +v0x2b3d890_0 .net "BornB", 0 0, L_0x2caa0a0; 1 drivers +v0x2b3d950_0 .net "CINandAxorB", 0 0, L_0x2caa9d0; 1 drivers +v0x2b3d9d0_0 .alias "Command", 2 0, v0x2bc67a0_0; +v0x2b3daa0_0 .net *"_s3", 0 0, L_0x2caa370; 1 drivers +v0x2b3db20_0 .net *"_s5", 0 0, L_0x2caa550; 1 drivers +v0x2b3dc20_0 .net "carryin", 0 0, L_0x2ca9bd0; 1 drivers +v0x2b3dcc0_0 .net "carryout", 0 0, L_0x2caaac0; 1 drivers +v0x2b3ddd0_0 .net "nB", 0 0, L_0x2ca8770; 1 drivers +v0x2b3de80_0 .net "nCmd2", 0 0, L_0x2caa2d0; 1 drivers +v0x2b3df80_0 .net "subtract", 0 0, L_0x2caa410; 1 drivers +L_0x2caa230 .part v0x2bc78e0_0, 0, 1; +L_0x2caa370 .part v0x2bc78e0_0, 2, 1; +L_0x2caa550 .part v0x2bc78e0_0, 0, 1; +S_0x2b3cfe0 .scope module, "mux0" "TwoInMux" 3 105, 3 8, S_0x2b3cef0; + .timescale -9 -12; +L_0x2ca88d0/d .functor NOT 1, L_0x2caa230, C4<0>, C4<0>, C4<0>; +L_0x2ca88d0 .delay (10000,10000,10000) L_0x2ca88d0/d; +L_0x2ca9ec0/d .functor AND 1, L_0x2ca9aa0, L_0x2ca88d0, C4<1>, C4<1>; +L_0x2ca9ec0 .delay (20000,20000,20000) L_0x2ca9ec0/d; +L_0x2ca9fb0/d .functor AND 1, L_0x2ca8770, L_0x2caa230, C4<1>, C4<1>; +L_0x2ca9fb0 .delay (20000,20000,20000) L_0x2ca9fb0/d; +L_0x2caa0a0/d .functor OR 1, L_0x2ca9ec0, L_0x2ca9fb0, C4<0>, C4<0>; +L_0x2caa0a0 .delay (20000,20000,20000) L_0x2caa0a0/d; +v0x2b3d0d0_0 .net "S", 0 0, L_0x2caa230; 1 drivers +v0x2b3d150_0 .alias "in0", 0 0, v0x2b3d7e0_0; +v0x2b3d1f0_0 .alias "in1", 0 0, v0x2b3ddd0_0; +v0x2b3d290_0 .net "nS", 0 0, L_0x2ca88d0; 1 drivers +v0x2b3d340_0 .net "out0", 0 0, L_0x2ca9ec0; 1 drivers +v0x2b3d3e0_0 .net "out1", 0 0, L_0x2ca9fb0; 1 drivers +v0x2b3d4c0_0 .alias "outfinal", 0 0, v0x2b3d890_0; +S_0x2ae82e0 .scope module, "trial1" "AndNand32" 3 280, 3 154, S_0x29738d0; + .timescale -9 -12; +P_0x2ad3738 .param/l "size" 3 161, +C4<0100000>; +v0x2851830_0 .alias "A", 31 0, v0x2bc6580_0; +v0x28518b0_0 .alias "AndNandOut", 31 0, v0x2bc77e0_0; +v0x2851930_0 .alias "B", 31 0, v0x2bc66a0_0; +v0x28519e0_0 .alias "Command", 2 0, v0x2bc67a0_0; +L_0x2cae270 .part/pv L_0x2cae000, 1, 1, 32; +L_0x2cae330 .part v0x2bc7660_0, 1, 1; +L_0x2cae3d0 .part v0x2bc7860_0, 1, 1; +L_0x2caece0 .part/pv L_0x2caea70, 2, 1, 32; +L_0x2caed80 .part v0x2bc7660_0, 2, 1; +L_0x2caee20 .part v0x2bc7860_0, 2, 1; +L_0x2caf750 .part/pv L_0x2caf4e0, 3, 1, 32; +L_0x2caf7f0 .part v0x2bc7660_0, 3, 1; +L_0x2caf8e0 .part v0x2bc7860_0, 3, 1; +L_0x2cb01b0 .part/pv L_0x2caff40, 4, 1, 32; +L_0x2cb02b0 .part v0x2bc7660_0, 4, 1; +L_0x2cb0350 .part v0x2bc7860_0, 4, 1; +L_0x2cb0c20 .part/pv L_0x2cb09b0, 5, 1, 32; +L_0x2cb0cc0 .part v0x2bc7660_0, 5, 1; +L_0x2cb0de0 .part v0x2bc7860_0, 5, 1; +L_0x2cb16f0 .part/pv L_0x2cb1480, 6, 1, 32; +L_0x2cb1820 .part v0x2bc7660_0, 6, 1; +L_0x2cb18c0 .part v0x2bc7860_0, 6, 1; +L_0x2cb21f0 .part/pv L_0x2cb1f80, 7, 1, 32; +L_0x2cb2290 .part v0x2bc7660_0, 7, 1; +L_0x2cb19b0 .part v0x2bc7860_0, 7, 1; +L_0x2cb2c50 .part/pv L_0x2cb29e0, 8, 1, 32; +L_0x2cb2330 .part v0x2bc7660_0, 8, 1; +L_0x2cb2db0 .part v0x2bc7860_0, 8, 1; +L_0x2cb3540 .part/pv L_0x2cb3310, 9, 1, 32; +L_0x2cb35e0 .part v0x2bc7660_0, 9, 1; +L_0x2cb2ea0 .part v0x2bc7860_0, 9, 1; +L_0x2cb3ed0 .part/pv L_0x2cb3ca0, 10, 1, 32; +L_0x2cb3680 .part v0x2bc7660_0, 10, 1; +L_0x2cb4060 .part v0x2bc7860_0, 10, 1; +L_0x2cb4880 .part/pv L_0x2cb4650, 11, 1, 32; +L_0x2cb4920 .part v0x2bc7660_0, 11, 1; +L_0x2cb4150 .part v0x2bc7860_0, 11, 1; +L_0x2cb52f0 .part/pv L_0x2cb5080, 12, 1, 32; +L_0x2cb49c0 .part v0x2bc7660_0, 12, 1; +L_0x2cb54b0 .part v0x2bc7860_0, 12, 1; +L_0x2cb5d70 .part/pv L_0x2cb5b00, 13, 1, 32; +L_0x2cb5e10 .part v0x2bc7660_0, 13, 1; +L_0x2cb5550 .part v0x2bc7860_0, 13, 1; +L_0x2cb6810 .part/pv L_0x2cb65a0, 14, 1, 32; +L_0x2cb5eb0 .part v0x2bc7660_0, 14, 1; +L_0x2cb5f50 .part v0x2bc7860_0, 14, 1; +L_0x2cb72c0 .part/pv L_0x2cb7050, 15, 1, 32; +L_0x2cb7360 .part v0x2bc7660_0, 15, 1; +L_0x2cb6a50 .part v0x2bc7860_0, 15, 1; +L_0x2cb7d70 .part/pv L_0x2cb7b00, 16, 1, 32; +L_0x2cb7400 .part v0x2bc7660_0, 16, 1; +L_0x2cb74a0 .part v0x2bc7860_0, 16, 1; +L_0x2cb8830 .part/pv L_0x2cb85c0, 17, 1, 32; +L_0x2cb88d0 .part v0x2bc7660_0, 17, 1; +L_0x2cb7fe0 .part v0x2bc7860_0, 17, 1; +L_0x2cb92d0 .part/pv L_0x2cb9060, 18, 1, 32; +L_0x2cb8970 .part v0x2bc7660_0, 18, 1; +L_0x2cb8a10 .part v0x2bc7860_0, 18, 1; +L_0x2cb9d90 .part/pv L_0x2cb9b20, 19, 1, 32; +L_0x2cb9e30 .part v0x2bc7660_0, 19, 1; +L_0x2cb9370 .part v0x2bc7860_0, 19, 1; +L_0x2cba7f0 .part/pv L_0x2cba580, 20, 1, 32; +L_0x2cb9ed0 .part v0x2bc7660_0, 20, 1; +L_0x2cb9f70 .part v0x2bc7860_0, 20, 1; +L_0x2cbb260 .part/pv L_0x2cbaff0, 21, 1, 32; +L_0x2cbb300 .part v0x2bc7660_0, 21, 1; +L_0x2cba890 .part v0x2bc7860_0, 21, 1; +L_0x2cbbcd0 .part/pv L_0x2cbba60, 22, 1, 32; +L_0x2cbb3a0 .part v0x2bc7660_0, 22, 1; +L_0x2cbb440 .part v0x2bc7860_0, 22, 1; +L_0x2cbc750 .part/pv L_0x2cbc4e0, 23, 1, 32; +L_0x2cbc7f0 .part v0x2bc7660_0, 23, 1; +L_0x2cbbd70 .part v0x2bc7860_0, 23, 1; +L_0x2cbd1b0 .part/pv L_0x2cbcf40, 24, 1, 32; +L_0x2cbc890 .part v0x2bc7660_0, 24, 1; +L_0x2cbc930 .part v0x2bc7860_0, 24, 1; +L_0x2cbdc20 .part/pv L_0x2cbd9b0, 25, 1, 32; +L_0x2cbdcc0 .part v0x2bc7660_0, 25, 1; +L_0x2cbd250 .part v0x2bc7860_0, 25, 1; +L_0x2cbe640 .part/pv L_0x2cbe410, 26, 1, 32; +L_0x2cbdd60 .part v0x2bc7660_0, 26, 1; +L_0x2cbde00 .part v0x2bc7860_0, 26, 1; +L_0x2cbf110 .part/pv L_0x2cbeea0, 27, 1, 32; +L_0x2cbf1b0 .part v0x2bc7660_0, 27, 1; +L_0x2cbe6e0 .part v0x2bc7860_0, 27, 1; +L_0x2cbfbc0 .part/pv L_0x2cbf950, 28, 1, 32; +L_0x2cbf250 .part v0x2bc7660_0, 28, 1; +L_0x2cbf2f0 .part v0x2bc7860_0, 28, 1; +L_0x2cc0640 .part/pv L_0x2cc03d0, 29, 1, 32; +L_0x2cc06e0 .part v0x2bc7660_0, 29, 1; +L_0x2cbfc60 .part v0x2bc7860_0, 29, 1; +L_0x2cc10a0 .part/pv L_0x2cc0e30, 30, 1, 32; +L_0x2cc0780 .part v0x2bc7660_0, 30, 1; +L_0x2cc0820 .part v0x2bc7860_0, 30, 1; +L_0x2cc1b10 .part/pv L_0x2cc18a0, 31, 1, 32; +L_0x2c55e80 .part v0x2bc7660_0, 31, 1; +L_0x2cc1140 .part v0x2bc7860_0, 31, 1; +L_0x2cc2c60 .part/pv L_0x2c56470, 0, 1, 32; +L_0x2c55f20 .part v0x2bc7660_0, 0, 1; +L_0x2c55fc0 .part v0x2bc7860_0, 0, 1; +S_0x2b3bb80 .scope module, "attempt2" "AndNand" 3 165, 3 48, S_0x2ae82e0; + .timescale -9 -12; +L_0x29b6d20/d .functor NAND 1, L_0x2c55f20, L_0x2c55fc0, C4<1>, C4<1>; +L_0x29b6d20 .delay (10000,10000,10000) L_0x29b6d20/d; +L_0x29d41b0/d .functor NOT 1, L_0x29b6d20, C4<0>, C4<0>, C4<0>; +L_0x29d41b0 .delay (10000,10000,10000) L_0x29d41b0/d; +v0x2b3c1a0_0 .net "A", 0 0, L_0x2c55f20; 1 drivers +v0x2b3c260_0 .net "AandB", 0 0, L_0x29d41b0; 1 drivers +v0x2b3c2e0_0 .net "AnandB", 0 0, L_0x29b6d20; 1 drivers +v0x2b3c390_0 .net "AndNandOut", 0 0, L_0x2c56470; 1 drivers +v0x2b3c470_0 .net "B", 0 0, L_0x2c55fc0; 1 drivers +v0x2b3c4f0_0 .alias "Command", 2 0, v0x2bc67a0_0; +L_0x2cc2bc0 .part v0x2bc78e0_0, 0, 1; +S_0x2b3bc70 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0x2b3bb80; + .timescale -9 -12; +L_0x2994d70/d .functor NOT 1, L_0x2cc2bc0, C4<0>, C4<0>, C4<0>; +L_0x2994d70 .delay (10000,10000,10000) L_0x2994d70/d; +L_0x2c56210/d .functor AND 1, L_0x29d41b0, L_0x2994d70, C4<1>, C4<1>; +L_0x2c56210 .delay (20000,20000,20000) L_0x2c56210/d; +L_0x2c56320/d .functor AND 1, L_0x29b6d20, L_0x2cc2bc0, C4<1>, C4<1>; +L_0x2c56320 .delay (20000,20000,20000) L_0x2c56320/d; +L_0x2c56470/d .functor OR 1, L_0x2c56210, L_0x2c56320, C4<0>, C4<0>; +L_0x2c56470 .delay (20000,20000,20000) L_0x2c56470/d; +v0x2b3bd60_0 .net "S", 0 0, L_0x2cc2bc0; 1 drivers +v0x2b3bde0_0 .alias "in0", 0 0, v0x2b3c260_0; +v0x2b3be60_0 .alias "in1", 0 0, v0x2b3c2e0_0; +v0x2b3bf00_0 .net "nS", 0 0, L_0x2994d70; 1 drivers +v0x2b3bf80_0 .net "out0", 0 0, L_0x2c56210; 1 drivers +v0x2b3c020_0 .net "out1", 0 0, L_0x2c56320; 1 drivers +v0x2b3c100_0 .alias "outfinal", 0 0, v0x2b3c390_0; +S_0x2b3afc0 .scope generate, "andbits[1]" "andbits[1]" 3 169, 3 169, S_0x2ae82e0; + .timescale -9 -12; +P_0x2b3b0b8 .param/l "i" 3 169, +C4<01>; +S_0x2b3b130 .scope module, "attempt" "AndNand" 3 171, 3 48, S_0x2b3afc0; + .timescale -9 -12; +L_0x2cadaf0/d .functor NAND 1, L_0x2cae330, L_0x2cae3d0, C4<1>, C4<1>; +L_0x2cadaf0 .delay (10000,10000,10000) L_0x2cadaf0/d; +L_0x2cadbb0/d .functor NOT 1, L_0x2cadaf0, C4<0>, C4<0>, C4<0>; +L_0x2cadbb0 .delay (10000,10000,10000) L_0x2cadbb0/d; +v0x2b3b770_0 .net "A", 0 0, L_0x2cae330; 1 drivers +v0x2b3b830_0 .net "AandB", 0 0, L_0x2cadbb0; 1 drivers +v0x2b3b8b0_0 .net "AnandB", 0 0, L_0x2cadaf0; 1 drivers +v0x2b3b960_0 .net "AndNandOut", 0 0, L_0x2cae000; 1 drivers +v0x2b3ba40_0 .net "B", 0 0, L_0x2cae3d0; 1 drivers +v0x2b3bac0_0 .alias "Command", 2 0, v0x2bc67a0_0; +L_0x2cae1d0 .part v0x2bc78e0_0, 0, 1; +S_0x2b3b220 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0x2b3b130; + .timescale -9 -12; +L_0x2cadce0/d .functor NOT 1, L_0x2cae1d0, C4<0>, C4<0>, C4<0>; +L_0x2cadce0 .delay (10000,10000,10000) L_0x2cadce0/d; +L_0x2cadda0/d .functor AND 1, L_0x2cadbb0, L_0x2cadce0, C4<1>, C4<1>; +L_0x2cadda0 .delay (20000,20000,20000) L_0x2cadda0/d; +L_0x2cadeb0/d .functor AND 1, L_0x2cadaf0, L_0x2cae1d0, C4<1>, C4<1>; +L_0x2cadeb0 .delay (20000,20000,20000) L_0x2cadeb0/d; +L_0x2cae000/d .functor OR 1, L_0x2cadda0, L_0x2cadeb0, C4<0>, C4<0>; +L_0x2cae000 .delay (20000,20000,20000) L_0x2cae000/d; +v0x2b3b310_0 .net "S", 0 0, L_0x2cae1d0; 1 drivers +v0x2b3b390_0 .alias "in0", 0 0, v0x2b3b830_0; +v0x2b3b430_0 .alias "in1", 0 0, v0x2b3b8b0_0; +v0x2b3b4d0_0 .net "nS", 0 0, L_0x2cadce0; 1 drivers +v0x2b3b550_0 .net "out0", 0 0, L_0x2cadda0; 1 drivers +v0x2b3b5f0_0 .net "out1", 0 0, L_0x2cadeb0; 1 drivers +v0x2b3b6d0_0 .alias "outfinal", 0 0, v0x2b3b960_0; +S_0x2b3a400 .scope generate, "andbits[2]" "andbits[2]" 3 169, 3 169, S_0x2ae82e0; + .timescale -9 -12; +P_0x2b3a4f8 .param/l "i" 3 169, +C4<010>; +S_0x2b3a570 .scope module, "attempt" "AndNand" 3 171, 3 48, S_0x2b3a400; + .timescale -9 -12; +L_0x2cae4c0/d .functor NAND 1, L_0x2caed80, L_0x2caee20, C4<1>, C4<1>; +L_0x2cae4c0 .delay (10000,10000,10000) L_0x2cae4c0/d; +L_0x2cae620/d .functor NOT 1, L_0x2cae4c0, C4<0>, C4<0>, C4<0>; +L_0x2cae620 .delay (10000,10000,10000) L_0x2cae620/d; +v0x2b3abb0_0 .net "A", 0 0, L_0x2caed80; 1 drivers +v0x2b3ac70_0 .net "AandB", 0 0, L_0x2cae620; 1 drivers +v0x2b3acf0_0 .net "AnandB", 0 0, L_0x2cae4c0; 1 drivers +v0x2b3ada0_0 .net "AndNandOut", 0 0, L_0x2caea70; 1 drivers +v0x2b3ae80_0 .net "B", 0 0, L_0x2caee20; 1 drivers +v0x2b3af00_0 .alias "Command", 2 0, v0x2bc67a0_0; +L_0x2caec40 .part v0x2bc78e0_0, 0, 1; +S_0x2b3a660 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0x2b3a570; + .timescale -9 -12; +L_0x2cae750/d .functor NOT 1, L_0x2caec40, C4<0>, C4<0>, C4<0>; +L_0x2cae750 .delay (10000,10000,10000) L_0x2cae750/d; +L_0x2cae810/d .functor AND 1, L_0x2cae620, L_0x2cae750, C4<1>, C4<1>; +L_0x2cae810 .delay (20000,20000,20000) L_0x2cae810/d; +L_0x2cae920/d .functor AND 1, L_0x2cae4c0, L_0x2caec40, C4<1>, C4<1>; +L_0x2cae920 .delay (20000,20000,20000) L_0x2cae920/d; +L_0x2caea70/d .functor OR 1, L_0x2cae810, L_0x2cae920, C4<0>, C4<0>; +L_0x2caea70 .delay (20000,20000,20000) L_0x2caea70/d; +v0x2b3a750_0 .net "S", 0 0, L_0x2caec40; 1 drivers +v0x2b3a7d0_0 .alias "in0", 0 0, v0x2b3ac70_0; +v0x2b3a870_0 .alias "in1", 0 0, v0x2b3acf0_0; +v0x2b3a910_0 .net "nS", 0 0, L_0x2cae750; 1 drivers +v0x2b3a990_0 .net "out0", 0 0, L_0x2cae810; 1 drivers +v0x2b3aa30_0 .net "out1", 0 0, L_0x2cae920; 1 drivers +v0x2b3ab10_0 .alias "outfinal", 0 0, v0x2b3ada0_0; +S_0x2b39840 .scope generate, "andbits[3]" "andbits[3]" 3 169, 3 169, S_0x2ae82e0; + .timescale -9 -12; +P_0x2b39938 .param/l "i" 3 169, +C4<011>; +S_0x2b399b0 .scope module, "attempt" "AndNand" 3 171, 3 48, S_0x2b39840; + .timescale -9 -12; +L_0x2caef50/d .functor NAND 1, L_0x2caf7f0, L_0x2caf8e0, C4<1>, C4<1>; +L_0x2caef50 .delay (10000,10000,10000) L_0x2caef50/d; +L_0x2caf090/d .functor NOT 1, L_0x2caef50, C4<0>, C4<0>, C4<0>; +L_0x2caf090 .delay (10000,10000,10000) L_0x2caf090/d; +v0x2b39ff0_0 .net "A", 0 0, L_0x2caf7f0; 1 drivers +v0x2b3a0b0_0 .net "AandB", 0 0, L_0x2caf090; 1 drivers +v0x2b3a130_0 .net "AnandB", 0 0, L_0x2caef50; 1 drivers +v0x2b3a1e0_0 .net "AndNandOut", 0 0, L_0x2caf4e0; 1 drivers +v0x2b3a2c0_0 .net "B", 0 0, L_0x2caf8e0; 1 drivers +v0x2b3a340_0 .alias "Command", 2 0, v0x2bc67a0_0; +L_0x2caf6b0 .part v0x2bc78e0_0, 0, 1; +S_0x2b39aa0 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0x2b399b0; + .timescale -9 -12; +L_0x2caf1c0/d .functor NOT 1, L_0x2caf6b0, C4<0>, C4<0>, C4<0>; +L_0x2caf1c0 .delay (10000,10000,10000) L_0x2caf1c0/d; +L_0x2caf280/d .functor AND 1, L_0x2caf090, L_0x2caf1c0, C4<1>, C4<1>; +L_0x2caf280 .delay (20000,20000,20000) L_0x2caf280/d; +L_0x2caf390/d .functor AND 1, L_0x2caef50, L_0x2caf6b0, C4<1>, C4<1>; +L_0x2caf390 .delay (20000,20000,20000) L_0x2caf390/d; +L_0x2caf4e0/d .functor OR 1, L_0x2caf280, L_0x2caf390, C4<0>, C4<0>; +L_0x2caf4e0 .delay (20000,20000,20000) L_0x2caf4e0/d; +v0x2b39b90_0 .net "S", 0 0, L_0x2caf6b0; 1 drivers +v0x2b39c10_0 .alias "in0", 0 0, v0x2b3a0b0_0; +v0x2b39cb0_0 .alias "in1", 0 0, v0x2b3a130_0; +v0x2b39d50_0 .net "nS", 0 0, L_0x2caf1c0; 1 drivers +v0x2b39dd0_0 .net "out0", 0 0, L_0x2caf280; 1 drivers +v0x2b39e70_0 .net "out1", 0 0, L_0x2caf390; 1 drivers +v0x2b39f50_0 .alias "outfinal", 0 0, v0x2b3a1e0_0; +S_0x2b38c80 .scope generate, "andbits[4]" "andbits[4]" 3 169, 3 169, S_0x2ae82e0; + .timescale -9 -12; +P_0x2b38d78 .param/l "i" 3 169, +C4<0100>; +S_0x2b38df0 .scope module, "attempt" "AndNand" 3 171, 3 48, S_0x2b38c80; + .timescale -9 -12; +L_0x2caf9d0/d .functor NAND 1, L_0x2cb02b0, L_0x2cb0350, C4<1>, C4<1>; +L_0x2caf9d0 .delay (10000,10000,10000) L_0x2caf9d0/d; +L_0x2cafaf0/d .functor NOT 1, L_0x2caf9d0, C4<0>, C4<0>, C4<0>; +L_0x2cafaf0 .delay (10000,10000,10000) L_0x2cafaf0/d; +v0x2b39430_0 .net "A", 0 0, L_0x2cb02b0; 1 drivers +v0x2b394f0_0 .net "AandB", 0 0, L_0x2cafaf0; 1 drivers +v0x2b39570_0 .net "AnandB", 0 0, L_0x2caf9d0; 1 drivers +v0x2b39620_0 .net "AndNandOut", 0 0, L_0x2caff40; 1 drivers +v0x2b39700_0 .net "B", 0 0, L_0x2cb0350; 1 drivers +v0x2b39780_0 .alias "Command", 2 0, v0x2bc67a0_0; +L_0x2cb0110 .part v0x2bc78e0_0, 0, 1; +S_0x2b38ee0 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0x2b38df0; + .timescale -9 -12; +L_0x2cafc20/d .functor NOT 1, L_0x2cb0110, C4<0>, C4<0>, C4<0>; +L_0x2cafc20 .delay (10000,10000,10000) L_0x2cafc20/d; +L_0x2cafce0/d .functor AND 1, L_0x2cafaf0, L_0x2cafc20, C4<1>, C4<1>; +L_0x2cafce0 .delay (20000,20000,20000) L_0x2cafce0/d; +L_0x2cafdf0/d .functor AND 1, L_0x2caf9d0, L_0x2cb0110, C4<1>, C4<1>; +L_0x2cafdf0 .delay (20000,20000,20000) L_0x2cafdf0/d; +L_0x2caff40/d .functor OR 1, L_0x2cafce0, L_0x2cafdf0, C4<0>, C4<0>; +L_0x2caff40 .delay (20000,20000,20000) L_0x2caff40/d; +v0x2b38fd0_0 .net "S", 0 0, L_0x2cb0110; 1 drivers +v0x2b39050_0 .alias "in0", 0 0, v0x2b394f0_0; +v0x2b390f0_0 .alias "in1", 0 0, v0x2b39570_0; +v0x2b39190_0 .net "nS", 0 0, L_0x2cafc20; 1 drivers +v0x2b39210_0 .net "out0", 0 0, L_0x2cafce0; 1 drivers +v0x2b392b0_0 .net "out1", 0 0, L_0x2cafdf0; 1 drivers +v0x2b39390_0 .alias "outfinal", 0 0, v0x2b39620_0; +S_0x2b380c0 .scope generate, "andbits[5]" "andbits[5]" 3 169, 3 169, S_0x2ae82e0; + .timescale -9 -12; +P_0x2b381b8 .param/l "i" 3 169, +C4<0101>; +S_0x2b38230 .scope module, "attempt" "AndNand" 3 171, 3 48, S_0x2b380c0; + .timescale -9 -12; +L_0x2cb0250/d .functor NAND 1, L_0x2cb0cc0, L_0x2cb0de0, C4<1>, C4<1>; +L_0x2cb0250 .delay (10000,10000,10000) L_0x2cb0250/d; +L_0x2cb0560/d .functor NOT 1, L_0x2cb0250, C4<0>, C4<0>, C4<0>; +L_0x2cb0560 .delay (10000,10000,10000) L_0x2cb0560/d; +v0x2b38870_0 .net "A", 0 0, L_0x2cb0cc0; 1 drivers +v0x2b38930_0 .net "AandB", 0 0, L_0x2cb0560; 1 drivers +v0x2b389b0_0 .net "AnandB", 0 0, L_0x2cb0250; 1 drivers +v0x2b38a60_0 .net "AndNandOut", 0 0, L_0x2cb09b0; 1 drivers +v0x2b38b40_0 .net "B", 0 0, L_0x2cb0de0; 1 drivers +v0x2b38bc0_0 .alias "Command", 2 0, v0x2bc67a0_0; +L_0x2cb0b80 .part v0x2bc78e0_0, 0, 1; +S_0x2b38320 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0x2b38230; + .timescale -9 -12; +L_0x2cb0690/d .functor NOT 1, L_0x2cb0b80, C4<0>, C4<0>, C4<0>; +L_0x2cb0690 .delay (10000,10000,10000) L_0x2cb0690/d; +L_0x2cb0750/d .functor AND 1, L_0x2cb0560, L_0x2cb0690, C4<1>, C4<1>; +L_0x2cb0750 .delay (20000,20000,20000) L_0x2cb0750/d; +L_0x2cb0860/d .functor AND 1, L_0x2cb0250, L_0x2cb0b80, C4<1>, C4<1>; +L_0x2cb0860 .delay (20000,20000,20000) L_0x2cb0860/d; +L_0x2cb09b0/d .functor OR 1, L_0x2cb0750, L_0x2cb0860, C4<0>, C4<0>; +L_0x2cb09b0 .delay (20000,20000,20000) L_0x2cb09b0/d; +v0x2b38410_0 .net "S", 0 0, L_0x2cb0b80; 1 drivers +v0x2b38490_0 .alias "in0", 0 0, v0x2b38930_0; +v0x2b38530_0 .alias "in1", 0 0, v0x2b389b0_0; +v0x2b385d0_0 .net "nS", 0 0, L_0x2cb0690; 1 drivers +v0x2b38650_0 .net "out0", 0 0, L_0x2cb0750; 1 drivers +v0x2b386f0_0 .net "out1", 0 0, L_0x2cb0860; 1 drivers +v0x2b387d0_0 .alias "outfinal", 0 0, v0x2b38a60_0; +S_0x2b37500 .scope generate, "andbits[6]" "andbits[6]" 3 169, 3 169, S_0x2ae82e0; + .timescale -9 -12; +P_0x2b375f8 .param/l "i" 3 169, +C4<0110>; +S_0x2b37670 .scope module, "attempt" "AndNand" 3 171, 3 48, S_0x2b37500; + .timescale -9 -12; +L_0x2cb0ed0/d .functor NAND 1, L_0x2cb1820, L_0x2cb18c0, C4<1>, C4<1>; +L_0x2cb0ed0 .delay (10000,10000,10000) L_0x2cb0ed0/d; +L_0x2cb1030/d .functor NOT 1, L_0x2cb0ed0, C4<0>, C4<0>, C4<0>; +L_0x2cb1030 .delay (10000,10000,10000) L_0x2cb1030/d; +v0x2b37cb0_0 .net "A", 0 0, L_0x2cb1820; 1 drivers +v0x2b37d70_0 .net "AandB", 0 0, L_0x2cb1030; 1 drivers +v0x2b37df0_0 .net "AnandB", 0 0, L_0x2cb0ed0; 1 drivers +v0x2b37ea0_0 .net "AndNandOut", 0 0, L_0x2cb1480; 1 drivers +v0x2b37f80_0 .net "B", 0 0, L_0x2cb18c0; 1 drivers +v0x2b38000_0 .alias "Command", 2 0, v0x2bc67a0_0; +L_0x2cb1650 .part v0x2bc78e0_0, 0, 1; +S_0x2b37760 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0x2b37670; + .timescale -9 -12; +L_0x2cb1160/d .functor NOT 1, L_0x2cb1650, C4<0>, C4<0>, C4<0>; +L_0x2cb1160 .delay (10000,10000,10000) L_0x2cb1160/d; +L_0x2cb1220/d .functor AND 1, L_0x2cb1030, L_0x2cb1160, C4<1>, C4<1>; +L_0x2cb1220 .delay (20000,20000,20000) L_0x2cb1220/d; +L_0x2cb1330/d .functor AND 1, L_0x2cb0ed0, L_0x2cb1650, C4<1>, C4<1>; +L_0x2cb1330 .delay (20000,20000,20000) L_0x2cb1330/d; +L_0x2cb1480/d .functor OR 1, L_0x2cb1220, L_0x2cb1330, C4<0>, C4<0>; +L_0x2cb1480 .delay (20000,20000,20000) L_0x2cb1480/d; +v0x2b37850_0 .net "S", 0 0, L_0x2cb1650; 1 drivers +v0x2b378d0_0 .alias "in0", 0 0, v0x2b37d70_0; +v0x2b37970_0 .alias "in1", 0 0, v0x2b37df0_0; +v0x2b37a10_0 .net "nS", 0 0, L_0x2cb1160; 1 drivers +v0x2b37a90_0 .net "out0", 0 0, L_0x2cb1220; 1 drivers +v0x2b37b30_0 .net "out1", 0 0, L_0x2cb1330; 1 drivers +v0x2b37c10_0 .alias "outfinal", 0 0, v0x2b37ea0_0; +S_0x2b36940 .scope generate, "andbits[7]" "andbits[7]" 3 169, 3 169, S_0x2ae82e0; + .timescale -9 -12; +P_0x2b36a38 .param/l "i" 3 169, +C4<0111>; +S_0x2b36ab0 .scope module, "attempt" "AndNand" 3 171, 3 48, S_0x2b36940; + .timescale -9 -12; +L_0x2cb1790/d .functor NAND 1, L_0x2cb2290, L_0x2cb19b0, C4<1>, C4<1>; +L_0x2cb1790 .delay (10000,10000,10000) L_0x2cb1790/d; +L_0x2cb1b30/d .functor NOT 1, L_0x2cb1790, C4<0>, C4<0>, C4<0>; +L_0x2cb1b30 .delay (10000,10000,10000) L_0x2cb1b30/d; +v0x2b370f0_0 .net "A", 0 0, L_0x2cb2290; 1 drivers +v0x2b371b0_0 .net "AandB", 0 0, L_0x2cb1b30; 1 drivers +v0x2b37230_0 .net "AnandB", 0 0, L_0x2cb1790; 1 drivers +v0x2b372e0_0 .net "AndNandOut", 0 0, L_0x2cb1f80; 1 drivers +v0x2b373c0_0 .net "B", 0 0, L_0x2cb19b0; 1 drivers +v0x2b37440_0 .alias "Command", 2 0, v0x2bc67a0_0; +L_0x2cb2150 .part v0x2bc78e0_0, 0, 1; +S_0x2b36ba0 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0x2b36ab0; + .timescale -9 -12; +L_0x2cb1c60/d .functor NOT 1, L_0x2cb2150, C4<0>, C4<0>, C4<0>; +L_0x2cb1c60 .delay (10000,10000,10000) L_0x2cb1c60/d; +L_0x2cb1d20/d .functor AND 1, L_0x2cb1b30, L_0x2cb1c60, C4<1>, C4<1>; +L_0x2cb1d20 .delay (20000,20000,20000) L_0x2cb1d20/d; +L_0x2cb1e30/d .functor AND 1, L_0x2cb1790, L_0x2cb2150, C4<1>, C4<1>; +L_0x2cb1e30 .delay (20000,20000,20000) L_0x2cb1e30/d; +L_0x2cb1f80/d .functor OR 1, L_0x2cb1d20, L_0x2cb1e30, C4<0>, C4<0>; +L_0x2cb1f80 .delay (20000,20000,20000) L_0x2cb1f80/d; +v0x2b36c90_0 .net "S", 0 0, L_0x2cb2150; 1 drivers +v0x2b36d10_0 .alias "in0", 0 0, v0x2b371b0_0; +v0x2b36db0_0 .alias "in1", 0 0, v0x2b37230_0; +v0x2b36e50_0 .net "nS", 0 0, L_0x2cb1c60; 1 drivers +v0x2b36ed0_0 .net "out0", 0 0, L_0x2cb1d20; 1 drivers +v0x2b36f70_0 .net "out1", 0 0, L_0x2cb1e30; 1 drivers +v0x2b37050_0 .alias "outfinal", 0 0, v0x2b372e0_0; +S_0x2b35d80 .scope generate, "andbits[8]" "andbits[8]" 3 169, 3 169, S_0x2ae82e0; + .timescale -9 -12; +P_0x2b35e78 .param/l "i" 3 169, +C4<01000>; +S_0x2b35ef0 .scope module, "attempt" "AndNand" 3 171, 3 48, S_0x2b35d80; + .timescale -9 -12; +L_0x2cb2430/d .functor NAND 1, L_0x2cb2330, L_0x2cb2db0, C4<1>, C4<1>; +L_0x2cb2430 .delay (10000,10000,10000) L_0x2cb2430/d; +L_0x2cb2590/d .functor NOT 1, L_0x2cb2430, C4<0>, C4<0>, C4<0>; +L_0x2cb2590 .delay (10000,10000,10000) L_0x2cb2590/d; +v0x2b36530_0 .net "A", 0 0, L_0x2cb2330; 1 drivers +v0x2b365f0_0 .net "AandB", 0 0, L_0x2cb2590; 1 drivers +v0x2b36670_0 .net "AnandB", 0 0, L_0x2cb2430; 1 drivers +v0x2b36720_0 .net "AndNandOut", 0 0, L_0x2cb29e0; 1 drivers +v0x2b36800_0 .net "B", 0 0, L_0x2cb2db0; 1 drivers +v0x2b36880_0 .alias "Command", 2 0, v0x2bc67a0_0; +L_0x2cb2bb0 .part v0x2bc78e0_0, 0, 1; +S_0x2b35fe0 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0x2b35ef0; + .timescale -9 -12; +L_0x2cb26c0/d .functor NOT 1, L_0x2cb2bb0, C4<0>, C4<0>, C4<0>; +L_0x2cb26c0 .delay (10000,10000,10000) L_0x2cb26c0/d; +L_0x2cb2780/d .functor AND 1, L_0x2cb2590, L_0x2cb26c0, C4<1>, C4<1>; +L_0x2cb2780 .delay (20000,20000,20000) L_0x2cb2780/d; +L_0x2cb2890/d .functor AND 1, L_0x2cb2430, L_0x2cb2bb0, C4<1>, C4<1>; +L_0x2cb2890 .delay (20000,20000,20000) L_0x2cb2890/d; +L_0x2cb29e0/d .functor OR 1, L_0x2cb2780, L_0x2cb2890, C4<0>, C4<0>; +L_0x2cb29e0 .delay (20000,20000,20000) L_0x2cb29e0/d; +v0x2b360d0_0 .net "S", 0 0, L_0x2cb2bb0; 1 drivers +v0x2b36150_0 .alias "in0", 0 0, v0x2b365f0_0; +v0x2b361f0_0 .alias "in1", 0 0, v0x2b36670_0; +v0x2b36290_0 .net "nS", 0 0, L_0x2cb26c0; 1 drivers +v0x2b36310_0 .net "out0", 0 0, L_0x2cb2780; 1 drivers +v0x2b363b0_0 .net "out1", 0 0, L_0x2cb2890; 1 drivers +v0x2b36490_0 .alias "outfinal", 0 0, v0x2b36720_0; +S_0x2b351c0 .scope generate, "andbits[9]" "andbits[9]" 3 169, 3 169, S_0x2ae82e0; + .timescale -9 -12; +P_0x2b352b8 .param/l "i" 3 169, +C4<01001>; +S_0x2b35330 .scope module, "attempt" "AndNand" 3 171, 3 48, S_0x2b351c0; + .timescale -9 -12; +L_0x2cb2cf0/d .functor NAND 1, L_0x2cb35e0, L_0x2cb2ea0, C4<1>, C4<1>; +L_0x2cb2cf0 .delay (10000,10000,10000) L_0x2cb2cf0/d; +L_0x2cb0d60/d .functor NOT 1, L_0x2cb2cf0, C4<0>, C4<0>, C4<0>; +L_0x2cb0d60 .delay (10000,10000,10000) L_0x2cb0d60/d; +v0x2b35970_0 .net "A", 0 0, L_0x2cb35e0; 1 drivers +v0x2b35a30_0 .net "AandB", 0 0, L_0x2cb0d60; 1 drivers +v0x2b35ab0_0 .net "AnandB", 0 0, L_0x2cb2cf0; 1 drivers +v0x2b35b60_0 .net "AndNandOut", 0 0, L_0x2cb3310; 1 drivers +v0x2b35c40_0 .net "B", 0 0, L_0x2cb2ea0; 1 drivers +v0x2b35cc0_0 .alias "Command", 2 0, v0x2bc67a0_0; +L_0x2cb34a0 .part v0x2bc78e0_0, 0, 1; +S_0x2b35420 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0x2b35330; + .timescale -9 -12; +L_0x2cb3050/d .functor NOT 1, L_0x2cb34a0, C4<0>, C4<0>, C4<0>; +L_0x2cb3050 .delay (10000,10000,10000) L_0x2cb3050/d; +L_0x2cb30f0/d .functor AND 1, L_0x2cb0d60, L_0x2cb3050, C4<1>, C4<1>; +L_0x2cb30f0 .delay (20000,20000,20000) L_0x2cb30f0/d; +L_0x2cb31e0/d .functor AND 1, L_0x2cb2cf0, L_0x2cb34a0, C4<1>, C4<1>; +L_0x2cb31e0 .delay (20000,20000,20000) L_0x2cb31e0/d; +L_0x2cb3310/d .functor OR 1, L_0x2cb30f0, L_0x2cb31e0, C4<0>, C4<0>; +L_0x2cb3310 .delay (20000,20000,20000) L_0x2cb3310/d; +v0x2b35510_0 .net "S", 0 0, L_0x2cb34a0; 1 drivers +v0x2b35590_0 .alias "in0", 0 0, v0x2b35a30_0; +v0x2b35630_0 .alias "in1", 0 0, v0x2b35ab0_0; +v0x2b356d0_0 .net "nS", 0 0, L_0x2cb3050; 1 drivers +v0x2b35750_0 .net "out0", 0 0, L_0x2cb30f0; 1 drivers +v0x2b357f0_0 .net "out1", 0 0, L_0x2cb31e0; 1 drivers +v0x2b358d0_0 .alias "outfinal", 0 0, v0x2b35b60_0; +S_0x2b34600 .scope generate, "andbits[10]" "andbits[10]" 3 169, 3 169, S_0x2ae82e0; + .timescale -9 -12; +P_0x2b346f8 .param/l "i" 3 169, +C4<01010>; +S_0x2b34770 .scope module, "attempt" "AndNand" 3 171, 3 48, S_0x2b34600; + .timescale -9 -12; +L_0x2cb37b0/d .functor NAND 1, L_0x2cb3680, L_0x2cb4060, C4<1>, C4<1>; +L_0x2cb37b0 .delay (10000,10000,10000) L_0x2cb37b0/d; +L_0x2cb38f0/d .functor NOT 1, L_0x2cb37b0, C4<0>, C4<0>, C4<0>; +L_0x2cb38f0 .delay (10000,10000,10000) L_0x2cb38f0/d; +v0x2b34db0_0 .net "A", 0 0, L_0x2cb3680; 1 drivers +v0x2b34e70_0 .net "AandB", 0 0, L_0x2cb38f0; 1 drivers +v0x2b34ef0_0 .net "AnandB", 0 0, L_0x2cb37b0; 1 drivers +v0x2b34fa0_0 .net "AndNandOut", 0 0, L_0x2cb3ca0; 1 drivers +v0x2b35080_0 .net "B", 0 0, L_0x2cb4060; 1 drivers +v0x2b35100_0 .alias "Command", 2 0, v0x2bc67a0_0; +L_0x2cb3e30 .part v0x2bc78e0_0, 0, 1; +S_0x2b34860 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0x2b34770; + .timescale -9 -12; +L_0x2cb39e0/d .functor NOT 1, L_0x2cb3e30, C4<0>, C4<0>, C4<0>; +L_0x2cb39e0 .delay (10000,10000,10000) L_0x2cb39e0/d; +L_0x2cb3a80/d .functor AND 1, L_0x2cb38f0, L_0x2cb39e0, C4<1>, C4<1>; +L_0x2cb3a80 .delay (20000,20000,20000) L_0x2cb3a80/d; +L_0x2cb3b70/d .functor AND 1, L_0x2cb37b0, L_0x2cb3e30, C4<1>, C4<1>; +L_0x2cb3b70 .delay (20000,20000,20000) L_0x2cb3b70/d; +L_0x2cb3ca0/d .functor OR 1, L_0x2cb3a80, L_0x2cb3b70, C4<0>, C4<0>; +L_0x2cb3ca0 .delay (20000,20000,20000) L_0x2cb3ca0/d; +v0x2b34950_0 .net "S", 0 0, L_0x2cb3e30; 1 drivers +v0x2b349d0_0 .alias "in0", 0 0, v0x2b34e70_0; +v0x2b34a70_0 .alias "in1", 0 0, v0x2b34ef0_0; +v0x2b34b10_0 .net "nS", 0 0, L_0x2cb39e0; 1 drivers +v0x2b34b90_0 .net "out0", 0 0, L_0x2cb3a80; 1 drivers +v0x2b34c30_0 .net "out1", 0 0, L_0x2cb3b70; 1 drivers +v0x2b34d10_0 .alias "outfinal", 0 0, v0x2b34fa0_0; +S_0x2b33a40 .scope generate, "andbits[11]" "andbits[11]" 3 169, 3 169, S_0x2ae82e0; + .timescale -9 -12; +P_0x2b33b38 .param/l "i" 3 169, +C4<01011>; +S_0x2b33bb0 .scope module, "attempt" "AndNand" 3 171, 3 48, S_0x2b33a40; + .timescale -9 -12; +L_0x2cb3f70/d .functor NAND 1, L_0x2cb4920, L_0x2cb4150, C4<1>, C4<1>; +L_0x2cb3f70 .delay (10000,10000,10000) L_0x2cb3f70/d; +L_0x2cb42a0/d .functor NOT 1, L_0x2cb3f70, C4<0>, C4<0>, C4<0>; +L_0x2cb42a0 .delay (10000,10000,10000) L_0x2cb42a0/d; +v0x2b341f0_0 .net "A", 0 0, L_0x2cb4920; 1 drivers +v0x2b342b0_0 .net "AandB", 0 0, L_0x2cb42a0; 1 drivers +v0x2b34330_0 .net "AnandB", 0 0, L_0x2cb3f70; 1 drivers +v0x2b343e0_0 .net "AndNandOut", 0 0, L_0x2cb4650; 1 drivers +v0x2b344c0_0 .net "B", 0 0, L_0x2cb4150; 1 drivers +v0x2b34540_0 .alias "Command", 2 0, v0x2bc67a0_0; +L_0x2cb47e0 .part v0x2bc78e0_0, 0, 1; +S_0x2b33ca0 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0x2b33bb0; + .timescale -9 -12; +L_0x2cb4390/d .functor NOT 1, L_0x2cb47e0, C4<0>, C4<0>, C4<0>; +L_0x2cb4390 .delay (10000,10000,10000) L_0x2cb4390/d; +L_0x2cb4430/d .functor AND 1, L_0x2cb42a0, L_0x2cb4390, C4<1>, C4<1>; +L_0x2cb4430 .delay (20000,20000,20000) L_0x2cb4430/d; +L_0x2cb4520/d .functor AND 1, L_0x2cb3f70, L_0x2cb47e0, C4<1>, C4<1>; +L_0x2cb4520 .delay (20000,20000,20000) L_0x2cb4520/d; +L_0x2cb4650/d .functor OR 1, L_0x2cb4430, L_0x2cb4520, C4<0>, C4<0>; +L_0x2cb4650 .delay (20000,20000,20000) L_0x2cb4650/d; +v0x2b33d90_0 .net "S", 0 0, L_0x2cb47e0; 1 drivers +v0x2b33e10_0 .alias "in0", 0 0, v0x2b342b0_0; +v0x2b33eb0_0 .alias "in1", 0 0, v0x2b34330_0; +v0x2b33f50_0 .net "nS", 0 0, L_0x2cb4390; 1 drivers +v0x2b33fd0_0 .net "out0", 0 0, L_0x2cb4430; 1 drivers +v0x2b34070_0 .net "out1", 0 0, L_0x2cb4520; 1 drivers +v0x2b34150_0 .alias "outfinal", 0 0, v0x2b343e0_0; +S_0x2b32e80 .scope generate, "andbits[12]" "andbits[12]" 3 169, 3 169, S_0x2ae82e0; + .timescale -9 -12; +P_0x2b32f78 .param/l "i" 3 169, +C4<01100>; +S_0x2b32ff0 .scope module, "attempt" "AndNand" 3 171, 3 48, S_0x2b32e80; + .timescale -9 -12; +L_0x2cb4ad0/d .functor NAND 1, L_0x2cb49c0, L_0x2cb54b0, C4<1>, C4<1>; +L_0x2cb4ad0 .delay (10000,10000,10000) L_0x2cb4ad0/d; +L_0x2cb4c30/d .functor NOT 1, L_0x2cb4ad0, C4<0>, C4<0>, C4<0>; +L_0x2cb4c30 .delay (10000,10000,10000) L_0x2cb4c30/d; +v0x2b33630_0 .net "A", 0 0, L_0x2cb49c0; 1 drivers +v0x2b336f0_0 .net "AandB", 0 0, L_0x2cb4c30; 1 drivers +v0x2b33770_0 .net "AnandB", 0 0, L_0x2cb4ad0; 1 drivers +v0x2b33820_0 .net "AndNandOut", 0 0, L_0x2cb5080; 1 drivers +v0x2b33900_0 .net "B", 0 0, L_0x2cb54b0; 1 drivers +v0x2b33980_0 .alias "Command", 2 0, v0x2bc67a0_0; +L_0x2cb5250 .part v0x2bc78e0_0, 0, 1; +S_0x2b330e0 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0x2b32ff0; + .timescale -9 -12; +L_0x2cb4d60/d .functor NOT 1, L_0x2cb5250, C4<0>, C4<0>, C4<0>; +L_0x2cb4d60 .delay (10000,10000,10000) L_0x2cb4d60/d; +L_0x2cb4e20/d .functor AND 1, L_0x2cb4c30, L_0x2cb4d60, C4<1>, C4<1>; +L_0x2cb4e20 .delay (20000,20000,20000) L_0x2cb4e20/d; +L_0x2cb4f30/d .functor AND 1, L_0x2cb4ad0, L_0x2cb5250, C4<1>, C4<1>; +L_0x2cb4f30 .delay (20000,20000,20000) L_0x2cb4f30/d; +L_0x2cb5080/d .functor OR 1, L_0x2cb4e20, L_0x2cb4f30, C4<0>, C4<0>; +L_0x2cb5080 .delay (20000,20000,20000) L_0x2cb5080/d; +v0x2b331d0_0 .net "S", 0 0, L_0x2cb5250; 1 drivers +v0x2b33250_0 .alias "in0", 0 0, v0x2b336f0_0; +v0x2b332f0_0 .alias "in1", 0 0, v0x2b33770_0; +v0x2b33390_0 .net "nS", 0 0, L_0x2cb4d60; 1 drivers +v0x2b33410_0 .net "out0", 0 0, L_0x2cb4e20; 1 drivers +v0x2b334b0_0 .net "out1", 0 0, L_0x2cb4f30; 1 drivers +v0x2b33590_0 .alias "outfinal", 0 0, v0x2b33820_0; +S_0x2b322d0 .scope generate, "andbits[13]" "andbits[13]" 3 169, 3 169, S_0x2ae82e0; + .timescale -9 -12; +P_0x2b323c8 .param/l "i" 3 169, +C4<01101>; +S_0x2b32440 .scope module, "attempt" "AndNand" 3 171, 3 48, S_0x2b322d0; + .timescale -9 -12; +L_0x2cb5390/d .functor NAND 1, L_0x2cb5e10, L_0x2cb5550, C4<1>, C4<1>; +L_0x2cb5390 .delay (10000,10000,10000) L_0x2cb5390/d; +L_0x2cb56d0/d .functor NOT 1, L_0x2cb5390, C4<0>, C4<0>, C4<0>; +L_0x2cb56d0 .delay (10000,10000,10000) L_0x2cb56d0/d; +v0x2b32aa0_0 .net "A", 0 0, L_0x2cb5e10; 1 drivers +v0x2b32b60_0 .net "AandB", 0 0, L_0x2cb56d0; 1 drivers +v0x2b32be0_0 .net "AnandB", 0 0, L_0x2cb5390; 1 drivers +v0x2b32c60_0 .net "AndNandOut", 0 0, L_0x2cb5b00; 1 drivers +v0x2b32d40_0 .net "B", 0 0, L_0x2cb5550; 1 drivers +v0x2b32dc0_0 .alias "Command", 2 0, v0x2bc67a0_0; +L_0x2cb5cd0 .part v0x2bc78e0_0, 0, 1; +S_0x2b32530 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0x2b32440; + .timescale -9 -12; +L_0x2cb57e0/d .functor NOT 1, L_0x2cb5cd0, C4<0>, C4<0>, C4<0>; +L_0x2cb57e0 .delay (10000,10000,10000) L_0x2cb57e0/d; +L_0x2cb58a0/d .functor AND 1, L_0x2cb56d0, L_0x2cb57e0, C4<1>, C4<1>; +L_0x2cb58a0 .delay (20000,20000,20000) L_0x2cb58a0/d; +L_0x2cb59b0/d .functor AND 1, L_0x2cb5390, L_0x2cb5cd0, C4<1>, C4<1>; +L_0x2cb59b0 .delay (20000,20000,20000) L_0x2cb59b0/d; +L_0x2cb5b00/d .functor OR 1, L_0x2cb58a0, L_0x2cb59b0, C4<0>, C4<0>; +L_0x2cb5b00 .delay (20000,20000,20000) L_0x2cb5b00/d; +v0x2b32620_0 .net "S", 0 0, L_0x2cb5cd0; 1 drivers +v0x2b326c0_0 .alias "in0", 0 0, v0x2b32b60_0; +v0x2b32760_0 .alias "in1", 0 0, v0x2b32be0_0; +v0x2b32800_0 .net "nS", 0 0, L_0x2cb57e0; 1 drivers +v0x2b32880_0 .net "out0", 0 0, L_0x2cb58a0; 1 drivers +v0x2b32920_0 .net "out1", 0 0, L_0x2cb59b0; 1 drivers +v0x2b32a00_0 .alias "outfinal", 0 0, v0x2b32c60_0; +S_0x2b31980 .scope generate, "andbits[14]" "andbits[14]" 3 169, 3 169, S_0x2ae82e0; + .timescale -9 -12; +P_0x2a16f78 .param/l "i" 3 169, +C4<01110>; +S_0x2b31a70 .scope module, "attempt" "AndNand" 3 171, 3 48, S_0x2b31980; + .timescale -9 -12; +L_0x2cb5ff0/d .functor NAND 1, L_0x2cb5eb0, L_0x2cb5f50, C4<1>, C4<1>; +L_0x2cb5ff0 .delay (10000,10000,10000) L_0x2cb5ff0/d; +L_0x2cb6130/d .functor NOT 1, L_0x2cb5ff0, C4<0>, C4<0>, C4<0>; +L_0x2cb6130 .delay (10000,10000,10000) L_0x2cb6130/d; +v0x2b31fd0_0 .net "A", 0 0, L_0x2cb5eb0; 1 drivers +v0x2b32050_0 .net "AandB", 0 0, L_0x2cb6130; 1 drivers +v0x2b320d0_0 .net "AnandB", 0 0, L_0x2cb5ff0; 1 drivers +v0x2b32150_0 .net "AndNandOut", 0 0, L_0x2cb65a0; 1 drivers +v0x2b321d0_0 .net "B", 0 0, L_0x2cb5f50; 1 drivers +v0x2b32250_0 .alias "Command", 2 0, v0x2bc67a0_0; +L_0x2cb6770 .part v0x2bc78e0_0, 0, 1; +S_0x2b31b60 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0x2b31a70; + .timescale -9 -12; +L_0x2cb6240/d .functor NOT 1, L_0x2cb6770, C4<0>, C4<0>, C4<0>; +L_0x2cb6240 .delay (10000,10000,10000) L_0x2cb6240/d; +L_0x2cb6320/d .functor AND 1, L_0x2cb6130, L_0x2cb6240, C4<1>, C4<1>; +L_0x2cb6320 .delay (20000,20000,20000) L_0x2cb6320/d; +L_0x2cb6430/d .functor AND 1, L_0x2cb5ff0, L_0x2cb6770, C4<1>, C4<1>; +L_0x2cb6430 .delay (20000,20000,20000) L_0x2cb6430/d; +L_0x2cb65a0/d .functor OR 1, L_0x2cb6320, L_0x2cb6430, C4<0>, C4<0>; +L_0x2cb65a0 .delay (20000,20000,20000) L_0x2cb65a0/d; +v0x2b31c50_0 .net "S", 0 0, L_0x2cb6770; 1 drivers +v0x2b31cd0_0 .alias "in0", 0 0, v0x2b32050_0; +v0x2b31d50_0 .alias "in1", 0 0, v0x2b320d0_0; +v0x2b31dd0_0 .net "nS", 0 0, L_0x2cb6240; 1 drivers +v0x2b31e50_0 .net "out0", 0 0, L_0x2cb6320; 1 drivers +v0x2b31ed0_0 .net "out1", 0 0, L_0x2cb6430; 1 drivers +v0x2b31f50_0 .alias "outfinal", 0 0, v0x2b32150_0; +S_0x2b31030 .scope generate, "andbits[15]" "andbits[15]" 3 169, 3 169, S_0x2ae82e0; + .timescale -9 -12; +P_0x29d1bf8 .param/l "i" 3 169, +C4<01111>; +S_0x2b31120 .scope module, "attempt" "AndNand" 3 171, 3 48, S_0x2b31030; + .timescale -9 -12; +L_0x2cb68b0/d .functor NAND 1, L_0x2cb7360, L_0x2cb6a50, C4<1>, C4<1>; +L_0x2cb68b0 .delay (10000,10000,10000) L_0x2cb68b0/d; +L_0x2cb6c00/d .functor NOT 1, L_0x2cb68b0, C4<0>, C4<0>, C4<0>; +L_0x2cb6c00 .delay (10000,10000,10000) L_0x2cb6c00/d; +v0x2b31680_0 .net "A", 0 0, L_0x2cb7360; 1 drivers +v0x2b31700_0 .net "AandB", 0 0, L_0x2cb6c00; 1 drivers +v0x2b31780_0 .net "AnandB", 0 0, L_0x2cb68b0; 1 drivers +v0x2b31800_0 .net "AndNandOut", 0 0, L_0x2cb7050; 1 drivers +v0x2b31880_0 .net "B", 0 0, L_0x2cb6a50; 1 drivers +v0x2b31900_0 .alias "Command", 2 0, v0x2bc67a0_0; +L_0x2cb7220 .part v0x2bc78e0_0, 0, 1; +S_0x2b31210 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0x2b31120; + .timescale -9 -12; +L_0x2cb6cf0/d .functor NOT 1, L_0x2cb7220, C4<0>, C4<0>, C4<0>; +L_0x2cb6cf0 .delay (10000,10000,10000) L_0x2cb6cf0/d; +L_0x2cb6dd0/d .functor AND 1, L_0x2cb6c00, L_0x2cb6cf0, C4<1>, C4<1>; +L_0x2cb6dd0 .delay (20000,20000,20000) L_0x2cb6dd0/d; +L_0x2cb6ee0/d .functor AND 1, L_0x2cb68b0, L_0x2cb7220, C4<1>, C4<1>; +L_0x2cb6ee0 .delay (20000,20000,20000) L_0x2cb6ee0/d; +L_0x2cb7050/d .functor OR 1, L_0x2cb6dd0, L_0x2cb6ee0, C4<0>, C4<0>; +L_0x2cb7050 .delay (20000,20000,20000) L_0x2cb7050/d; +v0x2b31300_0 .net "S", 0 0, L_0x2cb7220; 1 drivers +v0x2b31380_0 .alias "in0", 0 0, v0x2b31700_0; +v0x2b31400_0 .alias "in1", 0 0, v0x2b31780_0; +v0x2b31480_0 .net "nS", 0 0, L_0x2cb6cf0; 1 drivers +v0x2b31500_0 .net "out0", 0 0, L_0x2cb6dd0; 1 drivers +v0x2b31580_0 .net "out1", 0 0, L_0x2cb6ee0; 1 drivers +v0x2b31600_0 .alias "outfinal", 0 0, v0x2b31800_0; +S_0x2b306e0 .scope generate, "andbits[16]" "andbits[16]" 3 169, 3 169, S_0x2ae82e0; + .timescale -9 -12; +P_0x2996d58 .param/l "i" 3 169, +C4<010000>; +S_0x2b307d0 .scope module, "attempt" "AndNand" 3 171, 3 48, S_0x2b306e0; + .timescale -9 -12; +L_0x2cb6b40/d .functor NAND 1, L_0x2cb7400, L_0x2cb74a0, C4<1>, C4<1>; +L_0x2cb6b40 .delay (10000,10000,10000) L_0x2cb6b40/d; +L_0x2cb7670/d .functor NOT 1, L_0x2cb6b40, C4<0>, C4<0>, C4<0>; +L_0x2cb7670 .delay (10000,10000,10000) L_0x2cb7670/d; +v0x2b30d30_0 .net "A", 0 0, L_0x2cb7400; 1 drivers +v0x2b30db0_0 .net "AandB", 0 0, L_0x2cb7670; 1 drivers +v0x2b30e30_0 .net "AnandB", 0 0, L_0x2cb6b40; 1 drivers +v0x2b30eb0_0 .net "AndNandOut", 0 0, L_0x2cb7b00; 1 drivers +v0x2b30f30_0 .net "B", 0 0, L_0x2cb74a0; 1 drivers +v0x2b30fb0_0 .alias "Command", 2 0, v0x2bc67a0_0; +L_0x2cb7cd0 .part v0x2bc78e0_0, 0, 1; +S_0x2b308c0 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0x2b307d0; + .timescale -9 -12; +L_0x2cb77a0/d .functor NOT 1, L_0x2cb7cd0, C4<0>, C4<0>, C4<0>; +L_0x2cb77a0 .delay (10000,10000,10000) L_0x2cb77a0/d; +L_0x2cb7880/d .functor AND 1, L_0x2cb7670, L_0x2cb77a0, C4<1>, C4<1>; +L_0x2cb7880 .delay (20000,20000,20000) L_0x2cb7880/d; +L_0x2cb7990/d .functor AND 1, L_0x2cb6b40, L_0x2cb7cd0, C4<1>, C4<1>; +L_0x2cb7990 .delay (20000,20000,20000) L_0x2cb7990/d; +L_0x2cb7b00/d .functor OR 1, L_0x2cb7880, L_0x2cb7990, C4<0>, C4<0>; +L_0x2cb7b00 .delay (20000,20000,20000) L_0x2cb7b00/d; +v0x2b309b0_0 .net "S", 0 0, L_0x2cb7cd0; 1 drivers +v0x2b30a30_0 .alias "in0", 0 0, v0x2b30db0_0; +v0x2b30ab0_0 .alias "in1", 0 0, v0x2b30e30_0; +v0x2b30b30_0 .net "nS", 0 0, L_0x2cb77a0; 1 drivers +v0x2b30bb0_0 .net "out0", 0 0, L_0x2cb7880; 1 drivers +v0x2b30c30_0 .net "out1", 0 0, L_0x2cb7990; 1 drivers +v0x2b30cb0_0 .alias "outfinal", 0 0, v0x2b30eb0_0; +S_0x2b2fd90 .scope generate, "andbits[17]" "andbits[17]" 3 169, 3 169, S_0x2ae82e0; + .timescale -9 -12; +P_0x2a606b8 .param/l "i" 3 169, +C4<010001>; +S_0x2b2fe80 .scope module, "attempt" "AndNand" 3 171, 3 48, S_0x2b2fd90; + .timescale -9 -12; +L_0x2cb7e10/d .functor NAND 1, L_0x2cb88d0, L_0x2cb7fe0, C4<1>, C4<1>; +L_0x2cb7e10 .delay (10000,10000,10000) L_0x2cb7e10/d; +L_0x2cb8170/d .functor NOT 1, L_0x2cb7e10, C4<0>, C4<0>, C4<0>; +L_0x2cb8170 .delay (10000,10000,10000) L_0x2cb8170/d; +v0x2b303e0_0 .net "A", 0 0, L_0x2cb88d0; 1 drivers +v0x2b30460_0 .net "AandB", 0 0, L_0x2cb8170; 1 drivers +v0x2b304e0_0 .net "AnandB", 0 0, L_0x2cb7e10; 1 drivers +v0x2b30560_0 .net "AndNandOut", 0 0, L_0x2cb85c0; 1 drivers +v0x2b305e0_0 .net "B", 0 0, L_0x2cb7fe0; 1 drivers +v0x2b30660_0 .alias "Command", 2 0, v0x2bc67a0_0; +L_0x2cb8790 .part v0x2bc78e0_0, 0, 1; +S_0x2b2ff70 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0x2b2fe80; + .timescale -9 -12; +L_0x2cb8260/d .functor NOT 1, L_0x2cb8790, C4<0>, C4<0>, C4<0>; +L_0x2cb8260 .delay (10000,10000,10000) L_0x2cb8260/d; +L_0x2cb8340/d .functor AND 1, L_0x2cb8170, L_0x2cb8260, C4<1>, C4<1>; +L_0x2cb8340 .delay (20000,20000,20000) L_0x2cb8340/d; +L_0x2cb8450/d .functor AND 1, L_0x2cb7e10, L_0x2cb8790, C4<1>, C4<1>; +L_0x2cb8450 .delay (20000,20000,20000) L_0x2cb8450/d; +L_0x2cb85c0/d .functor OR 1, L_0x2cb8340, L_0x2cb8450, C4<0>, C4<0>; +L_0x2cb85c0 .delay (20000,20000,20000) L_0x2cb85c0/d; +v0x2b30060_0 .net "S", 0 0, L_0x2cb8790; 1 drivers +v0x2b300e0_0 .alias "in0", 0 0, v0x2b30460_0; +v0x2b30160_0 .alias "in1", 0 0, v0x2b304e0_0; +v0x2b301e0_0 .net "nS", 0 0, L_0x2cb8260; 1 drivers +v0x2b30260_0 .net "out0", 0 0, L_0x2cb8340; 1 drivers +v0x2b302e0_0 .net "out1", 0 0, L_0x2cb8450; 1 drivers +v0x2b30360_0 .alias "outfinal", 0 0, v0x2b30560_0; +S_0x2b2f440 .scope generate, "andbits[18]" "andbits[18]" 3 169, 3 169, S_0x2ae82e0; + .timescale -9 -12; +P_0x28b4f98 .param/l "i" 3 169, +C4<010010>; +S_0x2b2f530 .scope module, "attempt" "AndNand" 3 171, 3 48, S_0x2b2f440; + .timescale -9 -12; +L_0x2cb80d0/d .functor NAND 1, L_0x2cb8970, L_0x2cb8a10, C4<1>, C4<1>; +L_0x2cb80d0 .delay (10000,10000,10000) L_0x2cb80d0/d; +L_0x2cb8bf0/d .functor NOT 1, L_0x2cb80d0, C4<0>, C4<0>, C4<0>; +L_0x2cb8bf0 .delay (10000,10000,10000) L_0x2cb8bf0/d; +v0x2b2fa90_0 .net "A", 0 0, L_0x2cb8970; 1 drivers +v0x2b2fb10_0 .net "AandB", 0 0, L_0x2cb8bf0; 1 drivers +v0x2b2fb90_0 .net "AnandB", 0 0, L_0x2cb80d0; 1 drivers +v0x2b2fc10_0 .net "AndNandOut", 0 0, L_0x2cb9060; 1 drivers +v0x2b2fc90_0 .net "B", 0 0, L_0x2cb8a10; 1 drivers +v0x2b2fd10_0 .alias "Command", 2 0, v0x2bc67a0_0; +L_0x2cb9230 .part v0x2bc78e0_0, 0, 1; +S_0x2b2f620 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0x2b2f530; + .timescale -9 -12; +L_0x2cb8d00/d .functor NOT 1, L_0x2cb9230, C4<0>, C4<0>, C4<0>; +L_0x2cb8d00 .delay (10000,10000,10000) L_0x2cb8d00/d; +L_0x2cb8de0/d .functor AND 1, L_0x2cb8bf0, L_0x2cb8d00, C4<1>, C4<1>; +L_0x2cb8de0 .delay (20000,20000,20000) L_0x2cb8de0/d; +L_0x2cb8ef0/d .functor AND 1, L_0x2cb80d0, L_0x2cb9230, C4<1>, C4<1>; +L_0x2cb8ef0 .delay (20000,20000,20000) L_0x2cb8ef0/d; +L_0x2cb9060/d .functor OR 1, L_0x2cb8de0, L_0x2cb8ef0, C4<0>, C4<0>; +L_0x2cb9060 .delay (20000,20000,20000) L_0x2cb9060/d; +v0x2b2f710_0 .net "S", 0 0, L_0x2cb9230; 1 drivers +v0x2b2f790_0 .alias "in0", 0 0, v0x2b2fb10_0; +v0x2b2f810_0 .alias "in1", 0 0, v0x2b2fb90_0; +v0x2b2f890_0 .net "nS", 0 0, L_0x2cb8d00; 1 drivers +v0x2b2f910_0 .net "out0", 0 0, L_0x2cb8de0; 1 drivers +v0x2b2f990_0 .net "out1", 0 0, L_0x2cb8ef0; 1 drivers +v0x2b2fa10_0 .alias "outfinal", 0 0, v0x2b2fc10_0; +S_0x2b2eaf0 .scope generate, "andbits[19]" "andbits[19]" 3 169, 3 169, S_0x2ae82e0; + .timescale -9 -12; +P_0x28a9898 .param/l "i" 3 169, +C4<010011>; +S_0x2b2ebe0 .scope module, "attempt" "AndNand" 3 171, 3 48, S_0x2b2eaf0; + .timescale -9 -12; +L_0x2cb9530/d .functor NAND 1, L_0x2cb9e30, L_0x2cb9370, C4<1>, C4<1>; +L_0x2cb9530 .delay (10000,10000,10000) L_0x2cb9530/d; +L_0x2cb9690/d .functor NOT 1, L_0x2cb9530, C4<0>, C4<0>, C4<0>; +L_0x2cb9690 .delay (10000,10000,10000) L_0x2cb9690/d; +v0x2b2f140_0 .net "A", 0 0, L_0x2cb9e30; 1 drivers +v0x2b2f1c0_0 .net "AandB", 0 0, L_0x2cb9690; 1 drivers +v0x2b2f240_0 .net "AnandB", 0 0, L_0x2cb9530; 1 drivers +v0x2b2f2c0_0 .net "AndNandOut", 0 0, L_0x2cb9b20; 1 drivers +v0x2b2f340_0 .net "B", 0 0, L_0x2cb9370; 1 drivers +v0x2b2f3c0_0 .alias "Command", 2 0, v0x2bc67a0_0; +L_0x2cb9cf0 .part v0x2bc78e0_0, 0, 1; +S_0x2b2ecd0 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0x2b2ebe0; + .timescale -9 -12; +L_0x2cb97c0/d .functor NOT 1, L_0x2cb9cf0, C4<0>, C4<0>, C4<0>; +L_0x2cb97c0 .delay (10000,10000,10000) L_0x2cb97c0/d; +L_0x2cb9880/d .functor AND 1, L_0x2cb9690, L_0x2cb97c0, C4<1>, C4<1>; +L_0x2cb9880 .delay (20000,20000,20000) L_0x2cb9880/d; +L_0x2cb99b0/d .functor AND 1, L_0x2cb9530, L_0x2cb9cf0, C4<1>, C4<1>; +L_0x2cb99b0 .delay (20000,20000,20000) L_0x2cb99b0/d; +L_0x2cb9b20/d .functor OR 1, L_0x2cb9880, L_0x2cb99b0, C4<0>, C4<0>; +L_0x2cb9b20 .delay (20000,20000,20000) L_0x2cb9b20/d; +v0x2b2edc0_0 .net "S", 0 0, L_0x2cb9cf0; 1 drivers +v0x2b2ee40_0 .alias "in0", 0 0, v0x2b2f1c0_0; +v0x2b2eec0_0 .alias "in1", 0 0, v0x2b2f240_0; +v0x2b2ef40_0 .net "nS", 0 0, L_0x2cb97c0; 1 drivers +v0x2b2efc0_0 .net "out0", 0 0, L_0x2cb9880; 1 drivers +v0x2b2f040_0 .net "out1", 0 0, L_0x2cb99b0; 1 drivers +v0x2b2f0c0_0 .alias "outfinal", 0 0, v0x2b2f2c0_0; +S_0x2b2e1a0 .scope generate, "andbits[20]" "andbits[20]" 3 169, 3 169, S_0x2ae82e0; + .timescale -9 -12; +P_0x2927b78 .param/l "i" 3 169, +C4<010100>; +S_0x2b2e290 .scope module, "attempt" "AndNand" 3 171, 3 48, S_0x2b2e1a0; + .timescale -9 -12; +L_0x2cb9460/d .functor NAND 1, L_0x2cb9ed0, L_0x2cb9f70, C4<1>, C4<1>; +L_0x2cb9460 .delay (10000,10000,10000) L_0x2cb9460/d; +L_0x2cba130/d .functor NOT 1, L_0x2cb9460, C4<0>, C4<0>, C4<0>; +L_0x2cba130 .delay (10000,10000,10000) L_0x2cba130/d; +v0x2b2e7f0_0 .net "A", 0 0, L_0x2cb9ed0; 1 drivers +v0x2b2e870_0 .net "AandB", 0 0, L_0x2cba130; 1 drivers +v0x2b2e8f0_0 .net "AnandB", 0 0, L_0x2cb9460; 1 drivers +v0x2b2e970_0 .net "AndNandOut", 0 0, L_0x2cba580; 1 drivers +v0x2b2e9f0_0 .net "B", 0 0, L_0x2cb9f70; 1 drivers +v0x2b2ea70_0 .alias "Command", 2 0, v0x2bc67a0_0; +L_0x2cba750 .part v0x2bc78e0_0, 0, 1; +S_0x2b2e380 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0x2b2e290; + .timescale -9 -12; +L_0x2cba260/d .functor NOT 1, L_0x2cba750, C4<0>, C4<0>, C4<0>; +L_0x2cba260 .delay (10000,10000,10000) L_0x2cba260/d; +L_0x2cba320/d .functor AND 1, L_0x2cba130, L_0x2cba260, C4<1>, C4<1>; +L_0x2cba320 .delay (20000,20000,20000) L_0x2cba320/d; +L_0x2cba430/d .functor AND 1, L_0x2cb9460, L_0x2cba750, C4<1>, C4<1>; +L_0x2cba430 .delay (20000,20000,20000) L_0x2cba430/d; +L_0x2cba580/d .functor OR 1, L_0x2cba320, L_0x2cba430, C4<0>, C4<0>; +L_0x2cba580 .delay (20000,20000,20000) L_0x2cba580/d; +v0x2b2e470_0 .net "S", 0 0, L_0x2cba750; 1 drivers +v0x2b2e4f0_0 .alias "in0", 0 0, v0x2b2e870_0; +v0x2b2e570_0 .alias "in1", 0 0, v0x2b2e8f0_0; +v0x2b2e5f0_0 .net "nS", 0 0, L_0x2cba260; 1 drivers +v0x2b2e670_0 .net "out0", 0 0, L_0x2cba320; 1 drivers +v0x2b2e6f0_0 .net "out1", 0 0, L_0x2cba430; 1 drivers +v0x2b2e770_0 .alias "outfinal", 0 0, v0x2b2e970_0; +S_0x2b2d850 .scope generate, "andbits[21]" "andbits[21]" 3 169, 3 169, S_0x2ae82e0; + .timescale -9 -12; +P_0x2977a48 .param/l "i" 3 169, +C4<010101>; +S_0x2b2d940 .scope module, "attempt" "AndNand" 3 171, 3 48, S_0x2b2d850; + .timescale -9 -12; +L_0x2cbaa80/d .functor NAND 1, L_0x2cbb300, L_0x2cba890, C4<1>, C4<1>; +L_0x2cbaa80 .delay (10000,10000,10000) L_0x2cbaa80/d; +L_0x2cbabc0/d .functor NOT 1, L_0x2cbaa80, C4<0>, C4<0>, C4<0>; +L_0x2cbabc0 .delay (10000,10000,10000) L_0x2cbabc0/d; +v0x2b2dea0_0 .net "A", 0 0, L_0x2cbb300; 1 drivers +v0x2b2df20_0 .net "AandB", 0 0, L_0x2cbabc0; 1 drivers +v0x2b2dfa0_0 .net "AnandB", 0 0, L_0x2cbaa80; 1 drivers +v0x2b2e020_0 .net "AndNandOut", 0 0, L_0x2cbaff0; 1 drivers +v0x2b2e0a0_0 .net "B", 0 0, L_0x2cba890; 1 drivers +v0x2b2e120_0 .alias "Command", 2 0, v0x2bc67a0_0; +L_0x2cbb1c0 .part v0x2bc78e0_0, 0, 1; +S_0x2b2da30 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0x2b2d940; + .timescale -9 -12; +L_0x2cbacd0/d .functor NOT 1, L_0x2cbb1c0, C4<0>, C4<0>, C4<0>; +L_0x2cbacd0 .delay (10000,10000,10000) L_0x2cbacd0/d; +L_0x2cbad90/d .functor AND 1, L_0x2cbabc0, L_0x2cbacd0, C4<1>, C4<1>; +L_0x2cbad90 .delay (20000,20000,20000) L_0x2cbad90/d; +L_0x2cbaea0/d .functor AND 1, L_0x2cbaa80, L_0x2cbb1c0, C4<1>, C4<1>; +L_0x2cbaea0 .delay (20000,20000,20000) L_0x2cbaea0/d; +L_0x2cbaff0/d .functor OR 1, L_0x2cbad90, L_0x2cbaea0, C4<0>, C4<0>; +L_0x2cbaff0 .delay (20000,20000,20000) L_0x2cbaff0/d; +v0x2b2db20_0 .net "S", 0 0, L_0x2cbb1c0; 1 drivers +v0x2b2dba0_0 .alias "in0", 0 0, v0x2b2df20_0; +v0x2b2dc20_0 .alias "in1", 0 0, v0x2b2dfa0_0; +v0x2b2dca0_0 .net "nS", 0 0, L_0x2cbacd0; 1 drivers +v0x2b2dd20_0 .net "out0", 0 0, L_0x2cbad90; 1 drivers +v0x2b2dda0_0 .net "out1", 0 0, L_0x2cbaea0; 1 drivers +v0x2b2de20_0 .alias "outfinal", 0 0, v0x2b2e020_0; +S_0x2b2cf00 .scope generate, "andbits[22]" "andbits[22]" 3 169, 3 169, S_0x2ae82e0; + .timescale -9 -12; +P_0x29f7738 .param/l "i" 3 169, +C4<010110>; +S_0x2b2cff0 .scope module, "attempt" "AndNand" 3 171, 3 48, S_0x2b2cf00; + .timescale -9 -12; +L_0x2cba980/d .functor NAND 1, L_0x2cbb3a0, L_0x2cbb440, C4<1>, C4<1>; +L_0x2cba980 .delay (10000,10000,10000) L_0x2cba980/d; +L_0x2cbb630/d .functor NOT 1, L_0x2cba980, C4<0>, C4<0>, C4<0>; +L_0x2cbb630 .delay (10000,10000,10000) L_0x2cbb630/d; +v0x2b2d550_0 .net "A", 0 0, L_0x2cbb3a0; 1 drivers +v0x2b2d5d0_0 .net "AandB", 0 0, L_0x2cbb630; 1 drivers +v0x2b2d650_0 .net "AnandB", 0 0, L_0x2cba980; 1 drivers +v0x2b2d6d0_0 .net "AndNandOut", 0 0, L_0x2cbba60; 1 drivers +v0x2b2d750_0 .net "B", 0 0, L_0x2cbb440; 1 drivers +v0x2b2d7d0_0 .alias "Command", 2 0, v0x2bc67a0_0; +L_0x2cbbc30 .part v0x2bc78e0_0, 0, 1; +S_0x2b2d0e0 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0x2b2cff0; + .timescale -9 -12; +L_0x2cbb740/d .functor NOT 1, L_0x2cbbc30, C4<0>, C4<0>, C4<0>; +L_0x2cbb740 .delay (10000,10000,10000) L_0x2cbb740/d; +L_0x2cbb800/d .functor AND 1, L_0x2cbb630, L_0x2cbb740, C4<1>, C4<1>; +L_0x2cbb800 .delay (20000,20000,20000) L_0x2cbb800/d; +L_0x2cbb910/d .functor AND 1, L_0x2cba980, L_0x2cbbc30, C4<1>, C4<1>; +L_0x2cbb910 .delay (20000,20000,20000) L_0x2cbb910/d; +L_0x2cbba60/d .functor OR 1, L_0x2cbb800, L_0x2cbb910, C4<0>, C4<0>; +L_0x2cbba60 .delay (20000,20000,20000) L_0x2cbba60/d; +v0x2b2d1d0_0 .net "S", 0 0, L_0x2cbbc30; 1 drivers +v0x2b2d250_0 .alias "in0", 0 0, v0x2b2d5d0_0; +v0x2b2d2d0_0 .alias "in1", 0 0, v0x2b2d650_0; +v0x2b2d350_0 .net "nS", 0 0, L_0x2cbb740; 1 drivers +v0x2b2d3d0_0 .net "out0", 0 0, L_0x2cbb800; 1 drivers +v0x2b2d450_0 .net "out1", 0 0, L_0x2cbb910; 1 drivers +v0x2b2d4d0_0 .alias "outfinal", 0 0, v0x2b2d6d0_0; +S_0x2b2c5b0 .scope generate, "andbits[23]" "andbits[23]" 3 169, 3 169, S_0x2ae82e0; + .timescale -9 -12; +P_0x29e5958 .param/l "i" 3 169, +C4<010111>; +S_0x2b2c6a0 .scope module, "attempt" "AndNand" 3 171, 3 48, S_0x2b2c5b0; + .timescale -9 -12; +L_0x2cbb530/d .functor NAND 1, L_0x2cbc7f0, L_0x2cbbd70, C4<1>, C4<1>; +L_0x2cbb530 .delay (10000,10000,10000) L_0x2cbb530/d; +L_0x2cbc090/d .functor NOT 1, L_0x2cbb530, C4<0>, C4<0>, C4<0>; +L_0x2cbc090 .delay (10000,10000,10000) L_0x2cbc090/d; +v0x2b2cc00_0 .net "A", 0 0, L_0x2cbc7f0; 1 drivers +v0x2b2cc80_0 .net "AandB", 0 0, L_0x2cbc090; 1 drivers +v0x2b2cd00_0 .net "AnandB", 0 0, L_0x2cbb530; 1 drivers +v0x2b2cd80_0 .net "AndNandOut", 0 0, L_0x2cbc4e0; 1 drivers +v0x2b2ce00_0 .net "B", 0 0, L_0x2cbbd70; 1 drivers +v0x2b2ce80_0 .alias "Command", 2 0, v0x2bc67a0_0; +L_0x2cbc6b0 .part v0x2bc78e0_0, 0, 1; +S_0x2b2c790 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0x2b2c6a0; + .timescale -9 -12; +L_0x2cbc1c0/d .functor NOT 1, L_0x2cbc6b0, C4<0>, C4<0>, C4<0>; +L_0x2cbc1c0 .delay (10000,10000,10000) L_0x2cbc1c0/d; +L_0x2cbc280/d .functor AND 1, L_0x2cbc090, L_0x2cbc1c0, C4<1>, C4<1>; +L_0x2cbc280 .delay (20000,20000,20000) L_0x2cbc280/d; +L_0x2cbc390/d .functor AND 1, L_0x2cbb530, L_0x2cbc6b0, C4<1>, C4<1>; +L_0x2cbc390 .delay (20000,20000,20000) L_0x2cbc390/d; +L_0x2cbc4e0/d .functor OR 1, L_0x2cbc280, L_0x2cbc390, C4<0>, C4<0>; +L_0x2cbc4e0 .delay (20000,20000,20000) L_0x2cbc4e0/d; +v0x2b2c880_0 .net "S", 0 0, L_0x2cbc6b0; 1 drivers +v0x2b2c900_0 .alias "in0", 0 0, v0x2b2cc80_0; +v0x2b2c980_0 .alias "in1", 0 0, v0x2b2cd00_0; +v0x2b2ca00_0 .net "nS", 0 0, L_0x2cbc1c0; 1 drivers +v0x2b2ca80_0 .net "out0", 0 0, L_0x2cbc280; 1 drivers +v0x2b2cb00_0 .net "out1", 0 0, L_0x2cbc390; 1 drivers +v0x2b2cb80_0 .alias "outfinal", 0 0, v0x2b2cd80_0; +S_0x2b2bc60 .scope generate, "andbits[24]" "andbits[24]" 3 169, 3 169, S_0x2ae82e0; + .timescale -9 -12; +P_0x29bc5f8 .param/l "i" 3 169, +C4<011000>; +S_0x2b2bd50 .scope module, "attempt" "AndNand" 3 171, 3 48, S_0x2b2bc60; + .timescale -9 -12; +L_0x2cbbe60/d .functor NAND 1, L_0x2cbc890, L_0x2cbc930, C4<1>, C4<1>; +L_0x2cbbe60 .delay (10000,10000,10000) L_0x2cbbe60/d; +L_0x2cbcb10/d .functor NOT 1, L_0x2cbbe60, C4<0>, C4<0>, C4<0>; +L_0x2cbcb10 .delay (10000,10000,10000) L_0x2cbcb10/d; +v0x2b2c2b0_0 .net "A", 0 0, L_0x2cbc890; 1 drivers +v0x2b2c330_0 .net "AandB", 0 0, L_0x2cbcb10; 1 drivers +v0x2b2c3b0_0 .net "AnandB", 0 0, L_0x2cbbe60; 1 drivers +v0x2b2c430_0 .net "AndNandOut", 0 0, L_0x2cbcf40; 1 drivers +v0x2b2c4b0_0 .net "B", 0 0, L_0x2cbc930; 1 drivers +v0x2b2c530_0 .alias "Command", 2 0, v0x2bc67a0_0; +L_0x2cbd110 .part v0x2bc78e0_0, 0, 1; +S_0x2b2be40 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0x2b2bd50; + .timescale -9 -12; +L_0x2cbcc20/d .functor NOT 1, L_0x2cbd110, C4<0>, C4<0>, C4<0>; +L_0x2cbcc20 .delay (10000,10000,10000) L_0x2cbcc20/d; +L_0x2cbcce0/d .functor AND 1, L_0x2cbcb10, L_0x2cbcc20, C4<1>, C4<1>; +L_0x2cbcce0 .delay (20000,20000,20000) L_0x2cbcce0/d; +L_0x2cbcdf0/d .functor AND 1, L_0x2cbbe60, L_0x2cbd110, C4<1>, C4<1>; +L_0x2cbcdf0 .delay (20000,20000,20000) L_0x2cbcdf0/d; +L_0x2cbcf40/d .functor OR 1, L_0x2cbcce0, L_0x2cbcdf0, C4<0>, C4<0>; +L_0x2cbcf40 .delay (20000,20000,20000) L_0x2cbcf40/d; +v0x2b2bf30_0 .net "S", 0 0, L_0x2cbd110; 1 drivers +v0x2b2bfb0_0 .alias "in0", 0 0, v0x2b2c330_0; +v0x2b2c030_0 .alias "in1", 0 0, v0x2b2c3b0_0; +v0x2b2c0b0_0 .net "nS", 0 0, L_0x2cbcc20; 1 drivers +v0x2b2c130_0 .net "out0", 0 0, L_0x2cbcce0; 1 drivers +v0x2b2c1b0_0 .net "out1", 0 0, L_0x2cbcdf0; 1 drivers +v0x2b2c230_0 .alias "outfinal", 0 0, v0x2b2c430_0; +S_0x2b2b310 .scope generate, "andbits[25]" "andbits[25]" 3 169, 3 169, S_0x2ae82e0; + .timescale -9 -12; +P_0x299cb88 .param/l "i" 3 169, +C4<011001>; +S_0x2b2b400 .scope module, "attempt" "AndNand" 3 171, 3 48, S_0x2b2b310; + .timescale -9 -12; +L_0x2cbca20/d .functor NAND 1, L_0x2cbdcc0, L_0x2cbd250, C4<1>, C4<1>; +L_0x2cbca20 .delay (10000,10000,10000) L_0x2cbca20/d; +L_0x2cbd580/d .functor NOT 1, L_0x2cbca20, C4<0>, C4<0>, C4<0>; +L_0x2cbd580 .delay (10000,10000,10000) L_0x2cbd580/d; +v0x2b2b960_0 .net "A", 0 0, L_0x2cbdcc0; 1 drivers +v0x2b2b9e0_0 .net "AandB", 0 0, L_0x2cbd580; 1 drivers +v0x2b2ba60_0 .net "AnandB", 0 0, L_0x2cbca20; 1 drivers +v0x2b2bae0_0 .net "AndNandOut", 0 0, L_0x2cbd9b0; 1 drivers +v0x2b2bb60_0 .net "B", 0 0, L_0x2cbd250; 1 drivers +v0x2b2bbe0_0 .alias "Command", 2 0, v0x2bc67a0_0; +L_0x2cbdb80 .part v0x2bc78e0_0, 0, 1; +S_0x2b2b4f0 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0x2b2b400; + .timescale -9 -12; +L_0x2cbd690/d .functor NOT 1, L_0x2cbdb80, C4<0>, C4<0>, C4<0>; +L_0x2cbd690 .delay (10000,10000,10000) L_0x2cbd690/d; +L_0x2cbd750/d .functor AND 1, L_0x2cbd580, L_0x2cbd690, C4<1>, C4<1>; +L_0x2cbd750 .delay (20000,20000,20000) L_0x2cbd750/d; +L_0x2cbd860/d .functor AND 1, L_0x2cbca20, L_0x2cbdb80, C4<1>, C4<1>; +L_0x2cbd860 .delay (20000,20000,20000) L_0x2cbd860/d; +L_0x2cbd9b0/d .functor OR 1, L_0x2cbd750, L_0x2cbd860, C4<0>, C4<0>; +L_0x2cbd9b0 .delay (20000,20000,20000) L_0x2cbd9b0/d; +v0x2b2b5e0_0 .net "S", 0 0, L_0x2cbdb80; 1 drivers +v0x2b2b660_0 .alias "in0", 0 0, v0x2b2b9e0_0; +v0x2b2b6e0_0 .alias "in1", 0 0, v0x2b2ba60_0; +v0x2b2b760_0 .net "nS", 0 0, L_0x2cbd690; 1 drivers +v0x2b2b7e0_0 .net "out0", 0 0, L_0x2cbd750; 1 drivers +v0x2b2b860_0 .net "out1", 0 0, L_0x2cbd860; 1 drivers +v0x2b2b8e0_0 .alias "outfinal", 0 0, v0x2b2bae0_0; +S_0x2b2a9c0 .scope generate, "andbits[26]" "andbits[26]" 3 169, 3 169, S_0x2ae82e0; + .timescale -9 -12; +P_0x297c2c8 .param/l "i" 3 169, +C4<011010>; +S_0x2b2aab0 .scope module, "attempt" "AndNand" 3 171, 3 48, S_0x2b2a9c0; + .timescale -9 -12; +L_0x2cbd340/d .functor NAND 1, L_0x2cbdd60, L_0x2cbde00, C4<1>, C4<1>; +L_0x2cbd340 .delay (10000,10000,10000) L_0x2cbd340/d; +L_0x2cbdfc0/d .functor NOT 1, L_0x2cbd340, C4<0>, C4<0>, C4<0>; +L_0x2cbdfc0 .delay (10000,10000,10000) L_0x2cbdfc0/d; +v0x2b2b010_0 .net "A", 0 0, L_0x2cbdd60; 1 drivers +v0x2b2b090_0 .net "AandB", 0 0, L_0x2cbdfc0; 1 drivers +v0x2b2b110_0 .net "AnandB", 0 0, L_0x2cbd340; 1 drivers +v0x2b2b190_0 .net "AndNandOut", 0 0, L_0x2cbe410; 1 drivers +v0x2b2b210_0 .net "B", 0 0, L_0x2cbde00; 1 drivers +v0x2b2b290_0 .alias "Command", 2 0, v0x2bc67a0_0; +L_0x2cbe5a0 .part v0x2bc78e0_0, 0, 1; +S_0x2b2aba0 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0x2b2aab0; + .timescale -9 -12; +L_0x2cbe0f0/d .functor NOT 1, L_0x2cbe5a0, C4<0>, C4<0>, C4<0>; +L_0x2cbe0f0 .delay (10000,10000,10000) L_0x2cbe0f0/d; +L_0x2cbe1b0/d .functor AND 1, L_0x2cbdfc0, L_0x2cbe0f0, C4<1>, C4<1>; +L_0x2cbe1b0 .delay (20000,20000,20000) L_0x2cbe1b0/d; +L_0x2cbe2c0/d .functor AND 1, L_0x2cbd340, L_0x2cbe5a0, C4<1>, C4<1>; +L_0x2cbe2c0 .delay (20000,20000,20000) L_0x2cbe2c0/d; +L_0x2cbe410/d .functor OR 1, L_0x2cbe1b0, L_0x2cbe2c0, C4<0>, C4<0>; +L_0x2cbe410 .delay (20000,20000,20000) L_0x2cbe410/d; +v0x2b2ac90_0 .net "S", 0 0, L_0x2cbe5a0; 1 drivers +v0x2b2ad10_0 .alias "in0", 0 0, v0x2b2b090_0; +v0x2b2ad90_0 .alias "in1", 0 0, v0x2b2b110_0; +v0x2b2ae10_0 .net "nS", 0 0, L_0x2cbe0f0; 1 drivers +v0x2b2ae90_0 .net "out0", 0 0, L_0x2cbe1b0; 1 drivers +v0x2b2af10_0 .net "out1", 0 0, L_0x2cbe2c0; 1 drivers +v0x2b2af90_0 .alias "outfinal", 0 0, v0x2b2b190_0; +S_0x2b2a070 .scope generate, "andbits[27]" "andbits[27]" 3 169, 3 169, S_0x2ae82e0; + .timescale -9 -12; +P_0x270f708 .param/l "i" 3 169, +C4<011011>; +S_0x2b2a160 .scope module, "attempt" "AndNand" 3 171, 3 48, S_0x2b2a070; + .timescale -9 -12; +L_0x2cbdef0/d .functor NAND 1, L_0x2cbf1b0, L_0x2cbe6e0, C4<1>, C4<1>; +L_0x2cbdef0 .delay (10000,10000,10000) L_0x2cbdef0/d; +L_0x2cbea10/d .functor NOT 1, L_0x2cbdef0, C4<0>, C4<0>, C4<0>; +L_0x2cbea10 .delay (10000,10000,10000) L_0x2cbea10/d; +v0x2b2a6c0_0 .net "A", 0 0, L_0x2cbf1b0; 1 drivers +v0x2b2a740_0 .net "AandB", 0 0, L_0x2cbea10; 1 drivers +v0x2b2a7c0_0 .net "AnandB", 0 0, L_0x2cbdef0; 1 drivers +v0x2b2a840_0 .net "AndNandOut", 0 0, L_0x2cbeea0; 1 drivers +v0x2b2a8c0_0 .net "B", 0 0, L_0x2cbe6e0; 1 drivers +v0x2b2a940_0 .alias "Command", 2 0, v0x2bc67a0_0; +L_0x2cbf070 .part v0x2bc78e0_0, 0, 1; +S_0x2b2a250 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0x2b2a160; + .timescale -9 -12; +L_0x2cbeb40/d .functor NOT 1, L_0x2cbf070, C4<0>, C4<0>, C4<0>; +L_0x2cbeb40 .delay (10000,10000,10000) L_0x2cbeb40/d; +L_0x2cbec20/d .functor AND 1, L_0x2cbea10, L_0x2cbeb40, C4<1>, C4<1>; +L_0x2cbec20 .delay (20000,20000,20000) L_0x2cbec20/d; +L_0x2cbed50/d .functor AND 1, L_0x2cbdef0, L_0x2cbf070, C4<1>, C4<1>; +L_0x2cbed50 .delay (20000,20000,20000) L_0x2cbed50/d; +L_0x2cbeea0/d .functor OR 1, L_0x2cbec20, L_0x2cbed50, C4<0>, C4<0>; +L_0x2cbeea0 .delay (20000,20000,20000) L_0x2cbeea0/d; +v0x2b2a340_0 .net "S", 0 0, L_0x2cbf070; 1 drivers +v0x2b2a3c0_0 .alias "in0", 0 0, v0x2b2a740_0; +v0x2b2a440_0 .alias "in1", 0 0, v0x2b2a7c0_0; +v0x2b2a4c0_0 .net "nS", 0 0, L_0x2cbeb40; 1 drivers +v0x2b2a540_0 .net "out0", 0 0, L_0x2cbec20; 1 drivers +v0x2b2a5c0_0 .net "out1", 0 0, L_0x2cbed50; 1 drivers +v0x2b2a640_0 .alias "outfinal", 0 0, v0x2b2a840_0; +S_0x270f0b0 .scope generate, "andbits[28]" "andbits[28]" 3 169, 3 169, S_0x2ae82e0; + .timescale -9 -12; +P_0x270f1a8 .param/l "i" 3 169, +C4<011100>; +S_0x270f220 .scope module, "attempt" "AndNand" 3 171, 3 48, S_0x270f0b0; + .timescale -9 -12; +L_0x2cbe7d0/d .functor NAND 1, L_0x2cbf250, L_0x2cbf2f0, C4<1>, C4<1>; +L_0x2cbe7d0 .delay (10000,10000,10000) L_0x2cbe7d0/d; +L_0x2cbf4e0/d .functor NOT 1, L_0x2cbe7d0, C4<0>, C4<0>, C4<0>; +L_0x2cbf4e0 .delay (10000,10000,10000) L_0x2cbf4e0/d; +v0x2b29d70_0 .net "A", 0 0, L_0x2cbf250; 1 drivers +v0x2b29df0_0 .net "AandB", 0 0, L_0x2cbf4e0; 1 drivers +v0x2b29e70_0 .net "AnandB", 0 0, L_0x2cbe7d0; 1 drivers +v0x2b29ef0_0 .net "AndNandOut", 0 0, L_0x2cbf950; 1 drivers +v0x2b29f70_0 .net "B", 0 0, L_0x2cbf2f0; 1 drivers +v0x2b29ff0_0 .alias "Command", 2 0, v0x2bc67a0_0; +L_0x2cbfb20 .part v0x2bc78e0_0, 0, 1; +S_0x270f310 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0x270f220; + .timescale -9 -12; +L_0x2cbf610/d .functor NOT 1, L_0x2cbfb20, C4<0>, C4<0>, C4<0>; +L_0x2cbf610 .delay (10000,10000,10000) L_0x2cbf610/d; +L_0x2cbf6d0/d .functor AND 1, L_0x2cbf4e0, L_0x2cbf610, C4<1>, C4<1>; +L_0x2cbf6d0 .delay (20000,20000,20000) L_0x2cbf6d0/d; +L_0x2cbf7e0/d .functor AND 1, L_0x2cbe7d0, L_0x2cbfb20, C4<1>, C4<1>; +L_0x2cbf7e0 .delay (20000,20000,20000) L_0x2cbf7e0/d; +L_0x2cbf950/d .functor OR 1, L_0x2cbf6d0, L_0x2cbf7e0, C4<0>, C4<0>; +L_0x2cbf950 .delay (20000,20000,20000) L_0x2cbf950/d; +v0x270f400_0 .net "S", 0 0, L_0x2cbfb20; 1 drivers +v0x270f4a0_0 .alias "in0", 0 0, v0x2b29df0_0; +v0x270f540_0 .alias "in1", 0 0, v0x2b29e70_0; +v0x270f5e0_0 .net "nS", 0 0, L_0x2cbf610; 1 drivers +v0x270f660_0 .net "out0", 0 0, L_0x2cbf6d0; 1 drivers +v0x2b29c70_0 .net "out1", 0 0, L_0x2cbf7e0; 1 drivers +v0x2b29cf0_0 .alias "outfinal", 0 0, v0x2b29ef0_0; +S_0x2626690 .scope generate, "andbits[29]" "andbits[29]" 3 169, 3 169, S_0x2ae82e0; + .timescale -9 -12; +P_0x2626788 .param/l "i" 3 169, +C4<011101>; +S_0x2626800 .scope module, "attempt" "AndNand" 3 171, 3 48, S_0x2626690; + .timescale -9 -12; +L_0x2cbf3e0/d .functor NAND 1, L_0x2cc06e0, L_0x2cbfc60, C4<1>, C4<1>; +L_0x2cbf3e0 .delay (10000,10000,10000) L_0x2cbf3e0/d; +L_0x2cbffa0/d .functor NOT 1, L_0x2cbf3e0, C4<0>, C4<0>, C4<0>; +L_0x2cbffa0 .delay (10000,10000,10000) L_0x2cbffa0/d; +v0x2763de0_0 .net "A", 0 0, L_0x2cc06e0; 1 drivers +v0x2763ea0_0 .net "AandB", 0 0, L_0x2cbffa0; 1 drivers +v0x2763f20_0 .net "AnandB", 0 0, L_0x2cbf3e0; 1 drivers +v0x270eef0_0 .net "AndNandOut", 0 0, L_0x2cc03d0; 1 drivers +v0x270ef70_0 .net "B", 0 0, L_0x2cbfc60; 1 drivers +v0x270eff0_0 .alias "Command", 2 0, v0x2bc67a0_0; +L_0x2cc05a0 .part v0x2bc78e0_0, 0, 1; +S_0x26784a0 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0x2626800; + .timescale -9 -12; +L_0x2cc00b0/d .functor NOT 1, L_0x2cc05a0, C4<0>, C4<0>, C4<0>; +L_0x2cc00b0 .delay (10000,10000,10000) L_0x2cc00b0/d; +L_0x2cc0170/d .functor AND 1, L_0x2cbffa0, L_0x2cc00b0, C4<1>, C4<1>; +L_0x2cc0170 .delay (20000,20000,20000) L_0x2cc0170/d; +L_0x2cc0280/d .functor AND 1, L_0x2cbf3e0, L_0x2cc05a0, C4<1>, C4<1>; +L_0x2cc0280 .delay (20000,20000,20000) L_0x2cc0280/d; +L_0x2cc03d0/d .functor OR 1, L_0x2cc0170, L_0x2cc0280, C4<0>, C4<0>; +L_0x2cc03d0 .delay (20000,20000,20000) L_0x2cc03d0/d; +v0x2678590_0 .net "S", 0 0, L_0x2cc05a0; 1 drivers +v0x2678610_0 .alias "in0", 0 0, v0x2763ea0_0; +v0x26786b0_0 .alias "in1", 0 0, v0x2763f20_0; +v0x2763b40_0 .net "nS", 0 0, L_0x2cc00b0; 1 drivers +v0x2763bc0_0 .net "out0", 0 0, L_0x2cc0170; 1 drivers +v0x2763c60_0 .net "out1", 0 0, L_0x2cc0280; 1 drivers +v0x2763d40_0 .alias "outfinal", 0 0, v0x270eef0_0; +S_0x2670230 .scope generate, "andbits[30]" "andbits[30]" 3 169, 3 169, S_0x2ae82e0; + .timescale -9 -12; +P_0x2670328 .param/l "i" 3 169, +C4<011110>; +S_0x265c450 .scope module, "attempt" "AndNand" 3 171, 3 48, S_0x2670230; + .timescale -9 -12; +L_0x2cbfd50/d .functor NAND 1, L_0x2cc0780, L_0x2cc0820, C4<1>, C4<1>; +L_0x2cbfd50 .delay (10000,10000,10000) L_0x2cbfd50/d; +L_0x2cbfeb0/d .functor NOT 1, L_0x2cbfd50, C4<0>, C4<0>, C4<0>; +L_0x2cbfeb0 .delay (10000,10000,10000) L_0x2cbfeb0/d; +v0x2660790_0 .net "A", 0 0, L_0x2cc0780; 1 drivers +v0x2667ec0_0 .net "AandB", 0 0, L_0x2cbfeb0; 1 drivers +v0x2667f40_0 .net "AnandB", 0 0, L_0x2cbfd50; 1 drivers +v0x2667fc0_0 .net "AndNandOut", 0 0, L_0x2cc0e30; 1 drivers +v0x2668040_0 .net "B", 0 0, L_0x2cc0820; 1 drivers +v0x26680c0_0 .alias "Command", 2 0, v0x2bc67a0_0; +L_0x2cc1000 .part v0x2bc78e0_0, 0, 1; +S_0x265c540 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0x265c450; + .timescale -9 -12; +L_0x2cc0b10/d .functor NOT 1, L_0x2cc1000, C4<0>, C4<0>, C4<0>; +L_0x2cc0b10 .delay (10000,10000,10000) L_0x2cc0b10/d; +L_0x2cc0bd0/d .functor AND 1, L_0x2cbfeb0, L_0x2cc0b10, C4<1>, C4<1>; +L_0x2cc0bd0 .delay (20000,20000,20000) L_0x2cc0bd0/d; +L_0x2cc0ce0/d .functor AND 1, L_0x2cbfd50, L_0x2cc1000, C4<1>, C4<1>; +L_0x2cc0ce0 .delay (20000,20000,20000) L_0x2cc0ce0/d; +L_0x2cc0e30/d .functor OR 1, L_0x2cc0bd0, L_0x2cc0ce0, C4<0>, C4<0>; +L_0x2cc0e30 .delay (20000,20000,20000) L_0x2cc0e30/d; +v0x265c630_0 .net "S", 0 0, L_0x2cc1000; 1 drivers +v0x2662bb0_0 .alias "in0", 0 0, v0x2667ec0_0; +v0x2662c50_0 .alias "in1", 0 0, v0x2667f40_0; +v0x2662cf0_0 .net "nS", 0 0, L_0x2cc0b10; 1 drivers +v0x2662d70_0 .net "out0", 0 0, L_0x2cc0bd0; 1 drivers +v0x2660610_0 .net "out1", 0 0, L_0x2cc0ce0; 1 drivers +v0x26606f0_0 .alias "outfinal", 0 0, v0x2667fc0_0; +S_0x2ae83f0 .scope generate, "andbits[31]" "andbits[31]" 3 169, 3 169, S_0x2ae82e0; + .timescale -9 -12; +P_0x2ada678 .param/l "i" 3 169, +C4<011111>; +S_0x2aea7e0 .scope module, "attempt" "AndNand" 3 171, 3 48, S_0x2ae83f0; + .timescale -9 -12; +L_0x2cc0910/d .functor NAND 1, L_0x2c55e80, L_0x2cc1140, C4<1>, C4<1>; +L_0x2cc0910 .delay (10000,10000,10000) L_0x2cc0910/d; +L_0x2cc1470/d .functor NOT 1, L_0x2cc0910, C4<0>, C4<0>, C4<0>; +L_0x2cc1470 .delay (10000,10000,10000) L_0x2cc1470/d; +v0x2665cb0_0 .net "A", 0 0, L_0x2c55e80; 1 drivers +v0x2665d70_0 .net "AandB", 0 0, L_0x2cc1470; 1 drivers +v0x2665df0_0 .net "AnandB", 0 0, L_0x2cc0910; 1 drivers +v0x2665e70_0 .net "AndNandOut", 0 0, L_0x2cc18a0; 1 drivers +v0x2670130_0 .net "B", 0 0, L_0x2cc1140; 1 drivers +v0x26701b0_0 .alias "Command", 2 0, v0x2bc67a0_0; +L_0x2cc1a70 .part v0x2bc78e0_0, 0, 1; +S_0x2aea8d0 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0x2aea7e0; + .timescale -9 -12; +L_0x2cc1580/d .functor NOT 1, L_0x2cc1a70, C4<0>, C4<0>, C4<0>; +L_0x2cc1580 .delay (10000,10000,10000) L_0x2cc1580/d; +L_0x2cc1640/d .functor AND 1, L_0x2cc1470, L_0x2cc1580, C4<1>, C4<1>; +L_0x2cc1640 .delay (20000,20000,20000) L_0x2cc1640/d; +L_0x2cc1750/d .functor AND 1, L_0x2cc0910, L_0x2cc1a70, C4<1>, C4<1>; +L_0x2cc1750 .delay (20000,20000,20000) L_0x2cc1750/d; +L_0x2cc18a0/d .functor OR 1, L_0x2cc1640, L_0x2cc1750, C4<0>, C4<0>; +L_0x2cc18a0 .delay (20000,20000,20000) L_0x2cc18a0/d; +v0x266a3f0_0 .net "S", 0 0, L_0x2cc1a70; 1 drivers +v0x266a490_0 .alias "in0", 0 0, v0x2665d70_0; +v0x266a530_0 .alias "in1", 0 0, v0x2665df0_0; +v0x265f000_0 .net "nS", 0 0, L_0x2cc1580; 1 drivers +v0x265f080_0 .net "out0", 0 0, L_0x2cc1640; 1 drivers +v0x265f120_0 .net "out1", 0 0, L_0x2cc1750; 1 drivers +v0x265f1c0_0 .alias "outfinal", 0 0, v0x2665e70_0; +S_0x29fb160 .scope module, "trial2" "OrNorXor32" 3 281, 3 177, S_0x29738d0; + .timescale -9 -12; +P_0x29e8548 .param/l "size" 3 184, +C4<0100000>; +v0x2ae3a70_0 .alias "A", 31 0, v0x2bc6580_0; +v0x2ae5de0_0 .alias "B", 31 0, v0x2bc66a0_0; +v0x2ae5e80_0 .alias "Command", 2 0, v0x2bc67a0_0; +v0x2ae5f00_0 .alias "OrNorXorOut", 31 0, v0x2bc79e0_0; +L_0x2cc3e00 .part/pv L_0x2cc3bd0, 1, 1, 32; +L_0x2cc3ea0 .part v0x2bc7660_0, 1, 1; +L_0x2cc3f40 .part v0x2bc7860_0, 1, 1; +L_0x2cc4f00 .part/pv L_0x2cc4cd0, 2, 1, 32; +L_0x2cc4fa0 .part v0x2bc7660_0, 2, 1; +L_0x2cc5040 .part v0x2bc7860_0, 2, 1; +L_0x2cc6040 .part/pv L_0x2cc5e10, 3, 1, 32; +L_0x2cc60e0 .part v0x2bc7660_0, 3, 1; +L_0x2cc6180 .part v0x2bc7860_0, 3, 1; +L_0x2cc7210 .part/pv L_0x2cc6fa0, 4, 1, 32; +L_0x2cc7310 .part v0x2bc7660_0, 4, 1; +L_0x2cc73b0 .part v0x2bc7860_0, 4, 1; +L_0x2cc8510 .part/pv L_0x2cc82a0, 5, 1, 32; +L_0x2cc85b0 .part v0x2bc7660_0, 5, 1; +L_0x2cc86d0 .part v0x2bc7860_0, 5, 1; +L_0x2cc9870 .part/pv L_0x2cc9600, 6, 1, 32; +L_0x2cc99a0 .part v0x2bc7660_0, 6, 1; +L_0x2cc9a40 .part v0x2bc7860_0, 6, 1; +L_0x2ccac00 .part/pv L_0x2cca990, 7, 1, 32; +L_0x2ccaca0 .part v0x2bc7660_0, 7, 1; +L_0x2cc9ae0 .part v0x2bc7860_0, 7, 1; +L_0x2ccbef0 .part/pv L_0x2ccbc80, 8, 1, 32; +L_0x2ccad40 .part v0x2bc7660_0, 8, 1; +L_0x2ccc050 .part v0x2bc7860_0, 8, 1; +L_0x2ccd220 .part/pv L_0x2cccfb0, 9, 1, 32; +L_0x2ccd2c0 .part v0x2bc7660_0, 9, 1; +L_0x2ccc0f0 .part v0x2bc7860_0, 9, 1; +L_0x2cce530 .part/pv L_0x2cce2c0, 10, 1, 32; +L_0x2ccd360 .part v0x2bc7660_0, 10, 1; +L_0x2cce6c0 .part v0x2bc7860_0, 10, 1; +L_0x2ccf860 .part/pv L_0x2ccf5f0, 11, 1, 32; +L_0x2ccf900 .part v0x2bc7660_0, 11, 1; +L_0x2cce760 .part v0x2bc7860_0, 11, 1; +L_0x2cd0b90 .part/pv L_0x2cd0920, 12, 1, 32; +L_0x2ccf9a0 .part v0x2bc7660_0, 12, 1; +L_0x2cd0d50 .part v0x2bc7860_0, 12, 1; +L_0x2cd1ef0 .part/pv L_0x2cd1c80, 13, 1, 32; +L_0x2cd1f90 .part v0x2bc7660_0, 13, 1; +L_0x2cd0df0 .part v0x2bc7860_0, 13, 1; +L_0x2cd3290 .part/pv L_0x2cd3020, 14, 1, 32; +L_0x2cd2030 .part v0x2bc7660_0, 14, 1; +L_0x2cd20d0 .part v0x2bc7860_0, 14, 1; +L_0x2cd4490 .part/pv L_0x2cd4260, 15, 1, 32; +L_0x2cd4530 .part v0x2bc7660_0, 15, 1; +L_0x2cd3330 .part v0x2bc7860_0, 15, 1; +L_0x2cd55c0 .part/pv L_0x2cd5390, 16, 1, 32; +L_0x2cd45d0 .part v0x2bc7660_0, 16, 1; +L_0x2cd4670 .part v0x2bc7860_0, 16, 1; +L_0x2cd67d0 .part/pv L_0x2cd6560, 17, 1, 32; +L_0x2cd6870 .part v0x2bc7660_0, 17, 1; +L_0x2cd5660 .part v0x2bc7860_0, 17, 1; +L_0x2cd7b00 .part/pv L_0x2cd7890, 18, 1, 32; +L_0x2cd6910 .part v0x2bc7660_0, 18, 1; +L_0x2cd69b0 .part v0x2bc7860_0, 18, 1; +L_0x2cd8e40 .part/pv L_0x2cd8bd0, 19, 1, 32; +L_0x2cd8ee0 .part v0x2bc7660_0, 19, 1; +L_0x2cd7ba0 .part v0x2bc7860_0, 19, 1; +L_0x2cda180 .part/pv L_0x2cd9f10, 20, 1, 32; +L_0x2cd8f80 .part v0x2bc7660_0, 20, 1; +L_0x2cd9020 .part v0x2bc7860_0, 20, 1; +L_0x2cdb4d0 .part/pv L_0x2cdb260, 21, 1, 32; +L_0x2cdb570 .part v0x2bc7660_0, 21, 1; +L_0x2cda220 .part v0x2bc7860_0, 21, 1; +L_0x2cdc840 .part/pv L_0x2cdc5d0, 22, 1, 32; +L_0x2cdb610 .part v0x2bc7660_0, 22, 1; +L_0x2cdb6b0 .part v0x2bc7860_0, 22, 1; +L_0x2cddb80 .part/pv L_0x2cdd910, 23, 1, 32; +L_0x2cddc20 .part v0x2bc7660_0, 23, 1; +L_0x2cdc8e0 .part v0x2bc7860_0, 23, 1; +L_0x2cdeec0 .part/pv L_0x2cdec50, 24, 1, 32; +L_0x2cddcc0 .part v0x2bc7660_0, 24, 1; +L_0x2cddd60 .part v0x2bc7860_0, 24, 1; +L_0x2ce0200 .part/pv L_0x2cdff90, 25, 1, 32; +L_0x2ce02a0 .part v0x2bc7660_0, 25, 1; +L_0x2cdef60 .part v0x2bc7860_0, 25, 1; +L_0x2ce1570 .part/pv L_0x2ce1300, 26, 1, 32; +L_0x2ce0340 .part v0x2bc7660_0, 26, 1; +L_0x2ce03e0 .part v0x2bc7860_0, 26, 1; +L_0x2ce28c0 .part/pv L_0x2ce2650, 27, 1, 32; +L_0x2ce2960 .part v0x2bc7660_0, 27, 1; +L_0x2ce1610 .part v0x2bc7860_0, 27, 1; +L_0x2ce3c00 .part/pv L_0x2ce3990, 28, 1, 32; +L_0x2ce2a00 .part v0x2bc7660_0, 28, 1; +L_0x2ce2aa0 .part v0x2bc7860_0, 28, 1; +L_0x2ce4f00 .part/pv L_0x2ce4c90, 29, 1, 32; +L_0x2ce4fa0 .part v0x2bc7660_0, 29, 1; +L_0x2ce3ca0 .part v0x2bc7860_0, 29, 1; +L_0x2ce61f0 .part/pv L_0x2ce5f80, 30, 1, 32; +L_0x2ce5040 .part v0x2bc7660_0, 30, 1; +L_0x2ce50e0 .part v0x2bc7860_0, 30, 1; +L_0x2ce7520 .part/pv L_0x2ce72b0, 31, 1, 32; +L_0x2ce75c0 .part v0x2bc7660_0, 31, 1; +L_0x2ce6290 .part v0x2bc7860_0, 31, 1; +L_0x2ce8810 .part/pv L_0x2ce85a0, 0, 1, 32; +L_0x2ce7660 .part v0x2bc7660_0, 0, 1; +L_0x2ce7700 .part v0x2bc7860_0, 0, 1; +S_0x2acec70 .scope module, "attempt2" "OrNorXor" 3 192, 3 64, S_0x29fb160; + .timescale -9 -12; +L_0x2ce6330/d .functor NOR 1, L_0x2ce7660, L_0x2ce7700, C4<0>, C4<0>; +L_0x2ce6330 .delay (10000,10000,10000) L_0x2ce6330/d; +L_0x2ce6420/d .functor NOT 1, L_0x2ce6330, C4<0>, C4<0>, C4<0>; +L_0x2ce6420 .delay (10000,10000,10000) L_0x2ce6420/d; +L_0x2ce7950/d .functor NAND 1, L_0x2ce7660, L_0x2ce7700, C4<1>, C4<1>; +L_0x2ce7950 .delay (10000,10000,10000) L_0x2ce7950/d; +L_0x2ce7a90/d .functor NAND 1, L_0x2ce7950, L_0x2ce6420, C4<1>, C4<1>; +L_0x2ce7a90 .delay (10000,10000,10000) L_0x2ce7a90/d; +L_0x2ce7ba0/d .functor NOT 1, L_0x2ce7a90, C4<0>, C4<0>, C4<0>; +L_0x2ce7ba0 .delay (10000,10000,10000) L_0x2ce7ba0/d; +v0x2adeed0_0 .net "A", 0 0, L_0x2ce7660; 1 drivers +v0x2adef70_0 .net "AnandB", 0 0, L_0x2ce7950; 1 drivers +v0x2adf010_0 .net "AnorB", 0 0, L_0x2ce6330; 1 drivers +v0x2ae13e0_0 .net "AorB", 0 0, L_0x2ce6420; 1 drivers +v0x2ae1460_0 .net "AxorB", 0 0, L_0x2ce7ba0; 1 drivers +v0x2ae14e0_0 .net "B", 0 0, L_0x2ce7700; 1 drivers +v0x2ae1560_0 .alias "Command", 2 0, v0x2bc67a0_0; +v0x2ae38f0_0 .net "OrNorXorOut", 0 0, L_0x2ce85a0; 1 drivers +v0x2ae3970_0 .net "XorNor", 0 0, L_0x2ce8020; 1 drivers +v0x2ae39f0_0 .net "nXor", 0 0, L_0x2ce7a90; 1 drivers +L_0x2ce81a0 .part v0x2bc78e0_0, 2, 1; +L_0x2ce8770 .part v0x2bc78e0_0, 0, 1; +S_0x2ad7fa0 .scope module, "mux0" "TwoInMux" 3 83, 3 8, S_0x2acec70; + .timescale -9 -12; +L_0x2ce7d00/d .functor NOT 1, L_0x2ce81a0, C4<0>, C4<0>, C4<0>; +L_0x2ce7d00 .delay (10000,10000,10000) L_0x2ce7d00/d; +L_0x2ce7dc0/d .functor AND 1, L_0x2ce7ba0, L_0x2ce7d00, C4<1>, C4<1>; +L_0x2ce7dc0 .delay (20000,20000,20000) L_0x2ce7dc0/d; +L_0x2ce7ed0/d .functor AND 1, L_0x2ce6330, L_0x2ce81a0, C4<1>, C4<1>; +L_0x2ce7ed0 .delay (20000,20000,20000) L_0x2ce7ed0/d; +L_0x2ce8020/d .functor OR 1, L_0x2ce7dc0, L_0x2ce7ed0, C4<0>, C4<0>; +L_0x2ce8020 .delay (20000,20000,20000) L_0x2ce8020/d; +v0x2ad8090_0 .net "S", 0 0, L_0x2ce81a0; 1 drivers +v0x2ada4b0_0 .alias "in0", 0 0, v0x2ae1460_0; +v0x2ada550_0 .alias "in1", 0 0, v0x2adf010_0; +v0x2ada5f0_0 .net "nS", 0 0, L_0x2ce7d00; 1 drivers +v0x2adc9c0_0 .net "out0", 0 0, L_0x2ce7dc0; 1 drivers +v0x2adca60_0 .net "out1", 0 0, L_0x2ce7ed0; 1 drivers +v0x2adcb00_0 .alias "outfinal", 0 0, v0x2ae3970_0; +S_0x2ad1070 .scope module, "mux1" "TwoInMux" 3 84, 3 8, S_0x2acec70; + .timescale -9 -12; +L_0x2ce8240/d .functor NOT 1, L_0x2ce8770, C4<0>, C4<0>, C4<0>; +L_0x2ce8240 .delay (10000,10000,10000) L_0x2ce8240/d; +L_0x2ce8300/d .functor AND 1, L_0x2ce8020, L_0x2ce8240, C4<1>, C4<1>; +L_0x2ce8300 .delay (20000,20000,20000) L_0x2ce8300/d; +L_0x2ce8450/d .functor AND 1, L_0x2ce6420, L_0x2ce8770, C4<1>, C4<1>; +L_0x2ce8450 .delay (20000,20000,20000) L_0x2ce8450/d; +L_0x2ce85a0/d .functor OR 1, L_0x2ce8300, L_0x2ce8450, C4<0>, C4<0>; +L_0x2ce85a0 .delay (20000,20000,20000) L_0x2ce85a0/d; +v0x2ad1160_0 .net "S", 0 0, L_0x2ce8770; 1 drivers +v0x2ad3570_0 .alias "in0", 0 0, v0x2ae3970_0; +v0x2ad3610_0 .alias "in1", 0 0, v0x2ae13e0_0; +v0x2ad36b0_0 .net "nS", 0 0, L_0x2ce8240; 1 drivers +v0x2ad5a90_0 .net "out0", 0 0, L_0x2ce8300; 1 drivers +v0x2ad5b30_0 .net "out1", 0 0, L_0x2ce8450; 1 drivers +v0x2ad5bd0_0 .alias "outfinal", 0 0, v0x2ae38f0_0; +S_0x2ab9e20 .scope generate, "orbits[1]" "orbits[1]" 3 196, 3 196, S_0x29fb160; + .timescale -9 -12; +P_0x2aae6a8 .param/l "i" 3 196, +C4<01>; +S_0x2ab9f10 .scope module, "attempt" "OrNorXor" 3 198, 3 64, S_0x2ab9e20; + .timescale -9 -12; +L_0x2c56060/d .functor NOR 1, L_0x2cc3ea0, L_0x2cc3f40, C4<0>, C4<0>; +L_0x2c56060 .delay (10000,10000,10000) L_0x2c56060/d; +L_0x2cc3010/d .functor NOT 1, L_0x2c56060, C4<0>, C4<0>, C4<0>; +L_0x2cc3010 .delay (10000,10000,10000) L_0x2cc3010/d; +L_0x2cc30c0/d .functor NAND 1, L_0x2cc3ea0, L_0x2cc3f40, C4<1>, C4<1>; +L_0x2cc30c0 .delay (10000,10000,10000) L_0x2cc30c0/d; +L_0x2cc3200/d .functor NAND 1, L_0x2cc30c0, L_0x2cc3010, C4<1>, C4<1>; +L_0x2cc3200 .delay (10000,10000,10000) L_0x2cc3200/d; +L_0x2cc32f0/d .functor NOT 1, L_0x2cc3200, C4<0>, C4<0>, C4<0>; +L_0x2cc32f0 .delay (10000,10000,10000) L_0x2cc32f0/d; +v0x2ac7d90_0 .net "A", 0 0, L_0x2cc3ea0; 1 drivers +v0x2aca170_0 .net "AnandB", 0 0, L_0x2cc30c0; 1 drivers +v0x2aca210_0 .net "AnorB", 0 0, L_0x2c56060; 1 drivers +v0x2aca290_0 .net "AorB", 0 0, L_0x2cc3010; 1 drivers +v0x2acc670_0 .net "AxorB", 0 0, L_0x2cc32f0; 1 drivers +v0x2acc6f0_0 .net "B", 0 0, L_0x2cc3f40; 1 drivers +v0x2acc770_0 .alias "Command", 2 0, v0x2bc67a0_0; +v0x2acc7f0_0 .net "OrNorXorOut", 0 0, L_0x2cc3bd0; 1 drivers +v0x2aceb70_0 .net "XorNor", 0 0, L_0x2cc36f0; 1 drivers +v0x2acebf0_0 .net "nXor", 0 0, L_0x2cc3200; 1 drivers +L_0x2cc3830 .part v0x2bc78e0_0, 2, 1; +L_0x2cc3d60 .part v0x2bc78e0_0, 0, 1; +S_0x2ac3260 .scope module, "mux0" "TwoInMux" 3 83, 3 8, S_0x2ab9f10; + .timescale -9 -12; +L_0x2cc3430/d .functor NOT 1, L_0x2cc3830, C4<0>, C4<0>, C4<0>; +L_0x2cc3430 .delay (10000,10000,10000) L_0x2cc3430/d; +L_0x2cc34d0/d .functor AND 1, L_0x2cc32f0, L_0x2cc3430, C4<1>, C4<1>; +L_0x2cc34d0 .delay (20000,20000,20000) L_0x2cc34d0/d; +L_0x2cc35c0/d .functor AND 1, L_0x2c56060, L_0x2cc3830, C4<1>, C4<1>; +L_0x2cc35c0 .delay (20000,20000,20000) L_0x2cc35c0/d; +L_0x2cc36f0/d .functor OR 1, L_0x2cc34d0, L_0x2cc35c0, C4<0>, C4<0>; +L_0x2cc36f0 .delay (20000,20000,20000) L_0x2cc36f0/d; +v0x2ac3350_0 .net "S", 0 0, L_0x2cc3830; 1 drivers +v0x2ac0e90_0 .alias "in0", 0 0, v0x2acc670_0; +v0x2ac5770_0 .alias "in1", 0 0, v0x2aca210_0; +v0x2ac5810_0 .net "nS", 0 0, L_0x2cc3430; 1 drivers +v0x2ac5890_0 .net "out0", 0 0, L_0x2cc34d0; 1 drivers +v0x2ac7c70_0 .net "out1", 0 0, L_0x2cc35c0; 1 drivers +v0x2ac7d10_0 .alias "outfinal", 0 0, v0x2aceb70_0; +S_0x2abc330 .scope module, "mux1" "TwoInMux" 3 84, 3 8, S_0x2ab9f10; + .timescale -9 -12; +L_0x2cc38d0/d .functor NOT 1, L_0x2cc3d60, C4<0>, C4<0>, C4<0>; +L_0x2cc38d0 .delay (10000,10000,10000) L_0x2cc38d0/d; +L_0x2cc3970/d .functor AND 1, L_0x2cc36f0, L_0x2cc38d0, C4<1>, C4<1>; +L_0x2cc3970 .delay (20000,20000,20000) L_0x2cc3970/d; +L_0x2cc3aa0/d .functor AND 1, L_0x2cc3010, L_0x2cc3d60, C4<1>, C4<1>; +L_0x2cc3aa0 .delay (20000,20000,20000) L_0x2cc3aa0/d; +L_0x2cc3bd0/d .functor OR 1, L_0x2cc3970, L_0x2cc3aa0, C4<0>, C4<0>; +L_0x2cc3bd0 .delay (20000,20000,20000) L_0x2cc3bd0/d; +v0x2ab7a90_0 .net "S", 0 0, L_0x2cc3d60; 1 drivers +v0x2abc420_0 .alias "in0", 0 0, v0x2aceb70_0; +v0x2abe840_0 .alias "in1", 0 0, v0x2aca290_0; +v0x2abe8e0_0 .net "nS", 0 0, L_0x2cc38d0; 1 drivers +v0x2abe960_0 .net "out0", 0 0, L_0x2cc3970; 1 drivers +v0x2ac0d50_0 .net "out1", 0 0, L_0x2cc3aa0; 1 drivers +v0x2ac0df0_0 .alias "outfinal", 0 0, v0x2acc7f0_0; +S_0x2aecd60 .scope generate, "orbits[2]" "orbits[2]" 3 196, 3 196, S_0x29fb160; + .timescale -9 -12; +P_0x2a8a658 .param/l "i" 3 196, +C4<010>; +S_0x2aa5030 .scope module, "attempt" "OrNorXor" 3 198, 3 64, S_0x2aecd60; + .timescale -9 -12; +L_0x2cc3fe0/d .functor NOR 1, L_0x2cc4fa0, L_0x2cc5040, C4<0>, C4<0>; +L_0x2cc3fe0 .delay (10000,10000,10000) L_0x2cc3fe0/d; +L_0x2cc40d0/d .functor NOT 1, L_0x2cc3fe0, C4<0>, C4<0>, C4<0>; +L_0x2cc40d0 .delay (10000,10000,10000) L_0x2cc40d0/d; +L_0x2cc41c0/d .functor NAND 1, L_0x2cc4fa0, L_0x2cc5040, C4<1>, C4<1>; +L_0x2cc41c0 .delay (10000,10000,10000) L_0x2cc41c0/d; +L_0x2cc4300/d .functor NAND 1, L_0x2cc41c0, L_0x2cc40d0, C4<1>, C4<1>; +L_0x2cc4300 .delay (10000,10000,10000) L_0x2cc4300/d; +L_0x2cc43f0/d .functor NOT 1, L_0x2cc4300, C4<0>, C4<0>, C4<0>; +L_0x2cc43f0 .delay (10000,10000,10000) L_0x2cc43f0/d; +v0x2ab2ee0_0 .net "A", 0 0, L_0x2cc4fa0; 1 drivers +v0x2ab2f80_0 .net "AnandB", 0 0, L_0x2cc41c0; 1 drivers +v0x2ab3020_0 .net "AnorB", 0 0, L_0x2cc3fe0; 1 drivers +v0x2ab5400_0 .net "AorB", 0 0, L_0x2cc40d0; 1 drivers +v0x2ab5480_0 .net "AxorB", 0 0, L_0x2cc43f0; 1 drivers +v0x2ab5500_0 .net "B", 0 0, L_0x2cc5040; 1 drivers +v0x2ab5580_0 .alias "Command", 2 0, v0x2bc67a0_0; +v0x2ab7910_0 .net "OrNorXorOut", 0 0, L_0x2cc4cd0; 1 drivers +v0x2ab7990_0 .net "XorNor", 0 0, L_0x2cc47f0; 1 drivers +v0x2ab7a10_0 .net "nXor", 0 0, L_0x2cc4300; 1 drivers +L_0x2cc4930 .part v0x2bc78e0_0, 2, 1; +L_0x2cc4e60 .part v0x2bc78e0_0, 0, 1; +S_0x2aabfe0 .scope module, "mux0" "TwoInMux" 3 83, 3 8, S_0x2aa5030; + .timescale -9 -12; +L_0x2cc4530/d .functor NOT 1, L_0x2cc4930, C4<0>, C4<0>, C4<0>; +L_0x2cc4530 .delay (10000,10000,10000) L_0x2cc4530/d; +L_0x2cc45d0/d .functor AND 1, L_0x2cc43f0, L_0x2cc4530, C4<1>, C4<1>; +L_0x2cc45d0 .delay (20000,20000,20000) L_0x2cc45d0/d; +L_0x2cc46c0/d .functor AND 1, L_0x2cc3fe0, L_0x2cc4930, C4<1>, C4<1>; +L_0x2cc46c0 .delay (20000,20000,20000) L_0x2cc46c0/d; +L_0x2cc47f0/d .functor OR 1, L_0x2cc45d0, L_0x2cc46c0, C4<0>, C4<0>; +L_0x2cc47f0 .delay (20000,20000,20000) L_0x2cc47f0/d; +v0x2aac0d0_0 .net "S", 0 0, L_0x2cc4930; 1 drivers +v0x2aae4e0_0 .alias "in0", 0 0, v0x2ab5480_0; +v0x2aae580_0 .alias "in1", 0 0, v0x2ab3020_0; +v0x2aae620_0 .net "nS", 0 0, L_0x2cc4530; 1 drivers +v0x2ab09e0_0 .net "out0", 0 0, L_0x2cc45d0; 1 drivers +v0x2ab0a80_0 .net "out1", 0 0, L_0x2cc46c0; 1 drivers +v0x2ab0b20_0 .alias "outfinal", 0 0, v0x2ab7990_0; +S_0x2aa5120 .scope module, "mux1" "TwoInMux" 3 84, 3 8, S_0x2aa5030; + .timescale -9 -12; +L_0x2cc49d0/d .functor NOT 1, L_0x2cc4e60, C4<0>, C4<0>, C4<0>; +L_0x2cc49d0 .delay (10000,10000,10000) L_0x2cc49d0/d; +L_0x2cc4a70/d .functor AND 1, L_0x2cc47f0, L_0x2cc49d0, C4<1>, C4<1>; +L_0x2cc4a70 .delay (20000,20000,20000) L_0x2cc4a70/d; +L_0x2cc4ba0/d .functor AND 1, L_0x2cc40d0, L_0x2cc4e60, C4<1>, C4<1>; +L_0x2cc4ba0 .delay (20000,20000,20000) L_0x2cc4ba0/d; +L_0x2cc4cd0/d .functor OR 1, L_0x2cc4a70, L_0x2cc4ba0, C4<0>, C4<0>; +L_0x2cc4cd0 .delay (20000,20000,20000) L_0x2cc4cd0/d; +v0x2aece50_0 .net "S", 0 0, L_0x2cc4e60; 1 drivers +v0x2aa75e0_0 .alias "in0", 0 0, v0x2ab7990_0; +v0x2aa7660_0 .alias "in1", 0 0, v0x2ab5400_0; +v0x2aa7700_0 .net "nS", 0 0, L_0x2cc49d0; 1 drivers +v0x2aa9ae0_0 .net "out0", 0 0, L_0x2cc4a70; 1 drivers +v0x2aa9b80_0 .net "out1", 0 0, L_0x2cc4ba0; 1 drivers +v0x2aa9c20_0 .alias "outfinal", 0 0, v0x2ab7910_0; +S_0x2a86410 .scope generate, "orbits[3]" "orbits[3]" 3 196, 3 196, S_0x29fb160; + .timescale -9 -12; +P_0x2960cb8 .param/l "i" 3 196, +C4<011>; +S_0x2a87910 .scope module, "attempt" "OrNorXor" 3 198, 3 64, S_0x2a86410; + .timescale -9 -12; +L_0x2cc5120/d .functor NOR 1, L_0x2cc60e0, L_0x2cc6180, C4<0>, C4<0>; +L_0x2cc5120 .delay (10000,10000,10000) L_0x2cc5120/d; +L_0x2cc5210/d .functor NOT 1, L_0x2cc5120, C4<0>, C4<0>, C4<0>; +L_0x2cc5210 .delay (10000,10000,10000) L_0x2cc5210/d; +L_0x2cc5300/d .functor NAND 1, L_0x2cc60e0, L_0x2cc6180, C4<1>, C4<1>; +L_0x2cc5300 .delay (10000,10000,10000) L_0x2cc5300/d; +L_0x2cc5440/d .functor NAND 1, L_0x2cc5300, L_0x2cc5210, C4<1>, C4<1>; +L_0x2cc5440 .delay (10000,10000,10000) L_0x2cc5440/d; +L_0x2cc5530/d .functor NOT 1, L_0x2cc5440, C4<0>, C4<0>, C4<0>; +L_0x2cc5530 .delay (10000,10000,10000) L_0x2cc5530/d; +v0x2a8fc10_0 .net "A", 0 0, L_0x2cc60e0; 1 drivers +v0x2a8fcb0_0 .net "AnandB", 0 0, L_0x2cc5300; 1 drivers +v0x2a91110_0 .net "AnorB", 0 0, L_0x2cc5120; 1 drivers +v0x2a91190_0 .net "AorB", 0 0, L_0x2cc5210; 1 drivers +v0x2a91210_0 .net "AxorB", 0 0, L_0x2cc5530; 1 drivers +v0x2a91290_0 .net "B", 0 0, L_0x2cc6180; 1 drivers +v0x2a92710_0 .alias "Command", 2 0, v0x2bc67a0_0; +v0x2a92790_0 .net "OrNorXorOut", 0 0, L_0x2cc5e10; 1 drivers +v0x2a92810_0 .net "XorNor", 0 0, L_0x2cc5930; 1 drivers +v0x2aecce0_0 .net "nXor", 0 0, L_0x2cc5440; 1 drivers +L_0x2cc5a70 .part v0x2bc78e0_0, 2, 1; +L_0x2cc5fa0 .part v0x2bc78e0_0, 0, 1; +S_0x2a8bab0 .scope module, "mux0" "TwoInMux" 3 83, 3 8, S_0x2a87910; + .timescale -9 -12; +L_0x2cc5670/d .functor NOT 1, L_0x2cc5a70, C4<0>, C4<0>, C4<0>; +L_0x2cc5670 .delay (10000,10000,10000) L_0x2cc5670/d; +L_0x2cc5710/d .functor AND 1, L_0x2cc5530, L_0x2cc5670, C4<1>, C4<1>; +L_0x2cc5710 .delay (20000,20000,20000) L_0x2cc5710/d; +L_0x2cc5800/d .functor AND 1, L_0x2cc5120, L_0x2cc5a70, C4<1>, C4<1>; +L_0x2cc5800 .delay (20000,20000,20000) L_0x2cc5800/d; +L_0x2cc5930/d .functor OR 1, L_0x2cc5710, L_0x2cc5800, C4<0>, C4<0>; +L_0x2cc5930 .delay (20000,20000,20000) L_0x2cc5930/d; +v0x2a8d010_0 .net "S", 0 0, L_0x2cc5a70; 1 drivers +v0x2a8d0d0_0 .alias "in0", 0 0, v0x2a91210_0; +v0x2a8d170_0 .alias "in1", 0 0, v0x2a91110_0; +v0x2a8e590_0 .net "nS", 0 0, L_0x2cc5670; 1 drivers +v0x2a8e610_0 .net "out0", 0 0, L_0x2cc5710; 1 drivers +v0x2a8e6b0_0 .net "out1", 0 0, L_0x2cc5800; 1 drivers +v0x2a8fb90_0 .alias "outfinal", 0 0, v0x2a92810_0; +S_0x2a87a00 .scope module, "mux1" "TwoInMux" 3 84, 3 8, S_0x2a87910; + .timescale -9 -12; +L_0x2cc5b10/d .functor NOT 1, L_0x2cc5fa0, C4<0>, C4<0>, C4<0>; +L_0x2cc5b10 .delay (10000,10000,10000) L_0x2cc5b10/d; +L_0x2cc5bb0/d .functor AND 1, L_0x2cc5930, L_0x2cc5b10, C4<1>, C4<1>; +L_0x2cc5bb0 .delay (20000,20000,20000) L_0x2cc5bb0/d; +L_0x2cc5ce0/d .functor AND 1, L_0x2cc5210, L_0x2cc5fa0, C4<1>, C4<1>; +L_0x2cc5ce0 .delay (20000,20000,20000) L_0x2cc5ce0/d; +L_0x2cc5e10/d .functor OR 1, L_0x2cc5bb0, L_0x2cc5ce0, C4<0>, C4<0>; +L_0x2cc5e10 .delay (20000,20000,20000) L_0x2cc5e10/d; +v0x2a88e90_0 .net "S", 0 0, L_0x2cc5fa0; 1 drivers +v0x2a88f10_0 .alias "in0", 0 0, v0x2a92810_0; +v0x2a88fb0_0 .alias "in1", 0 0, v0x2a91190_0; +v0x2a8a490_0 .net "nS", 0 0, L_0x2cc5b10; 1 drivers +v0x2a8a510_0 .net "out0", 0 0, L_0x2cc5bb0; 1 drivers +v0x2a8a5b0_0 .net "out1", 0 0, L_0x2cc5ce0; 1 drivers +v0x2a8ba10_0 .alias "outfinal", 0 0, v0x2a92790_0; +S_0x2959d80 .scope generate, "orbits[4]" "orbits[4]" 3 196, 3 196, S_0x29fb160; + .timescale -9 -12; +P_0x294e968 .param/l "i" 3 196, +C4<0100>; +S_0x2959e70 .scope module, "attempt" "OrNorXor" 3 198, 3 64, S_0x2959d80; + .timescale -9 -12; +L_0x2cc6220/d .functor NOR 1, L_0x2cc7310, L_0x2cc73b0, C4<0>, C4<0>; +L_0x2cc6220 .delay (10000,10000,10000) L_0x2cc6220/d; +L_0x2cc6320/d .functor NOT 1, L_0x2cc6220, C4<0>, C4<0>, C4<0>; +L_0x2cc6320 .delay (10000,10000,10000) L_0x2cc6320/d; +L_0x2cc6410/d .functor NAND 1, L_0x2cc7310, L_0x2cc73b0, C4<1>, C4<1>; +L_0x2cc6410 .delay (10000,10000,10000) L_0x2cc6410/d; +L_0x2cc6550/d .functor NAND 1, L_0x2cc6410, L_0x2cc6320, C4<1>, C4<1>; +L_0x2cc6550 .delay (10000,10000,10000) L_0x2cc6550/d; +L_0x2cc6640/d .functor NOT 1, L_0x2cc6550, C4<0>, C4<0>, C4<0>; +L_0x2cc6640 .delay (10000,10000,10000) L_0x2cc6640/d; +v0x2a822f0_0 .net "A", 0 0, L_0x2cc7310; 1 drivers +v0x2a83790_0 .net "AnandB", 0 0, L_0x2cc6410; 1 drivers +v0x2a83830_0 .net "AnorB", 0 0, L_0x2cc6220; 1 drivers +v0x2a838b0_0 .net "AorB", 0 0, L_0x2cc6320; 1 drivers +v0x2a84d90_0 .net "AxorB", 0 0, L_0x2cc6640; 1 drivers +v0x2a84e10_0 .net "B", 0 0, L_0x2cc73b0; 1 drivers +v0x2a84e90_0 .alias "Command", 2 0, v0x2bc67a0_0; +v0x2a84f10_0 .net "OrNorXorOut", 0 0, L_0x2cc6fa0; 1 drivers +v0x2a86310_0 .net "XorNor", 0 0, L_0x2cc6a40; 1 drivers +v0x2a86390_0 .net "nXor", 0 0, L_0x2cc6550; 1 drivers +L_0x2cc6ba0 .part v0x2bc78e0_0, 2, 1; +L_0x2cc7170 .part v0x2bc78e0_0, 0, 1; +S_0x2a789d0 .scope module, "mux0" "TwoInMux" 3 83, 3 8, S_0x2959e70; + .timescale -9 -12; +L_0x2cc6780/d .functor NOT 1, L_0x2cc6ba0, C4<0>, C4<0>, C4<0>; +L_0x2cc6780 .delay (10000,10000,10000) L_0x2cc6780/d; +L_0x2cc6820/d .functor AND 1, L_0x2cc6640, L_0x2cc6780, C4<1>, C4<1>; +L_0x2cc6820 .delay (20000,20000,20000) L_0x2cc6820/d; +L_0x2cc6910/d .functor AND 1, L_0x2cc6220, L_0x2cc6ba0, C4<1>, C4<1>; +L_0x2cc6910 .delay (20000,20000,20000) L_0x2cc6910/d; +L_0x2cc6a40/d .functor OR 1, L_0x2cc6820, L_0x2cc6910, C4<0>, C4<0>; +L_0x2cc6a40 .delay (20000,20000,20000) L_0x2cc6a40/d; +v0x2a78ac0_0 .net "S", 0 0, L_0x2cc6ba0; 1 drivers +v0x2960c30_0 .alias "in0", 0 0, v0x2a84d90_0; +v0x2a7a020_0 .alias "in1", 0 0, v0x2a83830_0; +v0x2a7a0c0_0 .net "nS", 0 0, L_0x2cc6780; 1 drivers +v0x2a7a140_0 .net "out0", 0 0, L_0x2cc6820; 1 drivers +v0x2a821d0_0 .net "out1", 0 0, L_0x2cc6910; 1 drivers +v0x2a82270_0 .alias "outfinal", 0 0, v0x2a86310_0; +S_0x295c1e0 .scope module, "mux1" "TwoInMux" 3 84, 3 8, S_0x2959e70; + .timescale -9 -12; +L_0x2cc6c40/d .functor NOT 1, L_0x2cc7170, C4<0>, C4<0>, C4<0>; +L_0x2cc6c40 .delay (10000,10000,10000) L_0x2cc6c40/d; +L_0x2cc6d00/d .functor AND 1, L_0x2cc6a40, L_0x2cc6c40, C4<1>, C4<1>; +L_0x2cc6d00 .delay (20000,20000,20000) L_0x2cc6d00/d; +L_0x2cc6e50/d .functor AND 1, L_0x2cc6320, L_0x2cc7170, C4<1>, C4<1>; +L_0x2cc6e50 .delay (20000,20000,20000) L_0x2cc6e50/d; +L_0x2cc6fa0/d .functor OR 1, L_0x2cc6d00, L_0x2cc6e50, C4<0>, C4<0>; +L_0x2cc6fa0 .delay (20000,20000,20000) L_0x2cc6fa0/d; +v0x2957aa0_0 .net "S", 0 0, L_0x2cc7170; 1 drivers +v0x295c2d0_0 .alias "in0", 0 0, v0x2a86310_0; +v0x295e640_0 .alias "in1", 0 0, v0x2a838b0_0; +v0x295e6e0_0 .net "nS", 0 0, L_0x2cc6c40; 1 drivers +v0x295e760_0 .net "out0", 0 0, L_0x2cc6d00; 1 drivers +v0x2960af0_0 .net "out1", 0 0, L_0x2cc6e50; 1 drivers +v0x2960b90_0 .alias "outfinal", 0 0, v0x2a84f10_0; +S_0x29430b0 .scope generate, "orbits[5]" "orbits[5]" 3 196, 3 196, S_0x29fb160; + .timescale -9 -12; +P_0x2933208 .param/l "i" 3 196, +C4<0101>; +S_0x29454e0 .scope module, "attempt" "OrNorXor" 3 198, 3 64, S_0x29430b0; + .timescale -9 -12; +L_0x2cc72b0/d .functor NOR 1, L_0x2cc85b0, L_0x2cc86d0, C4<0>, C4<0>; +L_0x2cc72b0 .delay (10000,10000,10000) L_0x2cc72b0/d; +L_0x2cc7500/d .functor NOT 1, L_0x2cc72b0, C4<0>, C4<0>, C4<0>; +L_0x2cc7500 .delay (10000,10000,10000) L_0x2cc7500/d; +L_0x2cc7630/d .functor NAND 1, L_0x2cc85b0, L_0x2cc86d0, C4<1>, C4<1>; +L_0x2cc7630 .delay (10000,10000,10000) L_0x2cc7630/d; +L_0x2cc7790/d .functor NAND 1, L_0x2cc7630, L_0x2cc7500, C4<1>, C4<1>; +L_0x2cc7790 .delay (10000,10000,10000) L_0x2cc7790/d; +L_0x2cc78a0/d .functor NOT 1, L_0x2cc7790, C4<0>, C4<0>, C4<0>; +L_0x2cc78a0 .delay (10000,10000,10000) L_0x2cc78a0/d; +v0x2953060_0 .net "A", 0 0, L_0x2cc85b0; 1 drivers +v0x2953100_0 .net "AnandB", 0 0, L_0x2cc7630; 1 drivers +v0x29531a0_0 .net "AnorB", 0 0, L_0x2cc72b0; 1 drivers +v0x29554c0_0 .net "AorB", 0 0, L_0x2cc7500; 1 drivers +v0x2955540_0 .net "AxorB", 0 0, L_0x2cc78a0; 1 drivers +v0x29555c0_0 .net "B", 0 0, L_0x2cc86d0; 1 drivers +v0x2955640_0 .alias "Command", 2 0, v0x2bc67a0_0; +v0x2957920_0 .net "OrNorXorOut", 0 0, L_0x2cc82a0; 1 drivers +v0x29579a0_0 .net "XorNor", 0 0, L_0x2cc7d20; 1 drivers +v0x2957a20_0 .net "nXor", 0 0, L_0x2cc7790; 1 drivers +L_0x2cc7ea0 .part v0x2bc78e0_0, 2, 1; +L_0x2cc8470 .part v0x2bc78e0_0, 0, 1; +S_0x294c2f0 .scope module, "mux0" "TwoInMux" 3 83, 3 8, S_0x29454e0; + .timescale -9 -12; +L_0x2cc7a00/d .functor NOT 1, L_0x2cc7ea0, C4<0>, C4<0>, C4<0>; +L_0x2cc7a00 .delay (10000,10000,10000) L_0x2cc7a00/d; +L_0x2cc7ac0/d .functor AND 1, L_0x2cc78a0, L_0x2cc7a00, C4<1>, C4<1>; +L_0x2cc7ac0 .delay (20000,20000,20000) L_0x2cc7ac0/d; +L_0x2cc7bd0/d .functor AND 1, L_0x2cc72b0, L_0x2cc7ea0, C4<1>, C4<1>; +L_0x2cc7bd0 .delay (20000,20000,20000) L_0x2cc7bd0/d; +L_0x2cc7d20/d .functor OR 1, L_0x2cc7ac0, L_0x2cc7bd0, C4<0>, C4<0>; +L_0x2cc7d20 .delay (20000,20000,20000) L_0x2cc7d20/d; +v0x294c3e0_0 .net "S", 0 0, L_0x2cc7ea0; 1 drivers +v0x294e7a0_0 .alias "in0", 0 0, v0x2955540_0; +v0x294e840_0 .alias "in1", 0 0, v0x29531a0_0; +v0x294e8e0_0 .net "nS", 0 0, L_0x2cc7a00; 1 drivers +v0x2950c00_0 .net "out0", 0 0, L_0x2cc7ac0; 1 drivers +v0x2950ca0_0 .net "out1", 0 0, L_0x2cc7bd0; 1 drivers +v0x2950d40_0 .alias "outfinal", 0 0, v0x29579a0_0; +S_0x29455d0 .scope module, "mux1" "TwoInMux" 3 84, 3 8, S_0x29454e0; + .timescale -9 -12; +L_0x2cc7f40/d .functor NOT 1, L_0x2cc8470, C4<0>, C4<0>, C4<0>; +L_0x2cc7f40 .delay (10000,10000,10000) L_0x2cc7f40/d; +L_0x2cc8000/d .functor AND 1, L_0x2cc7d20, L_0x2cc7f40, C4<1>, C4<1>; +L_0x2cc8000 .delay (20000,20000,20000) L_0x2cc8000/d; +L_0x2cc8150/d .functor AND 1, L_0x2cc7500, L_0x2cc8470, C4<1>, C4<1>; +L_0x2cc8150 .delay (20000,20000,20000) L_0x2cc8150/d; +L_0x2cc82a0/d .functor OR 1, L_0x2cc8000, L_0x2cc8150, C4<0>, C4<0>; +L_0x2cc82a0 .delay (20000,20000,20000) L_0x2cc82a0/d; +v0x29431a0_0 .net "S", 0 0, L_0x2cc8470; 1 drivers +v0x2947990_0 .alias "in0", 0 0, v0x29579a0_0; +v0x2947a10_0 .alias "in1", 0 0, v0x29554c0_0; +v0x2947ab0_0 .net "nS", 0 0, L_0x2cc7f40; 1 drivers +v0x2949e40_0 .net "out0", 0 0, L_0x2cc8000; 1 drivers +v0x2949ee0_0 .net "out1", 0 0, L_0x2cc8150; 1 drivers +v0x2949f80_0 .alias "outfinal", 0 0, v0x2957920_0; +S_0x292c430 .scope generate, "orbits[6]" "orbits[6]" 3 196, 3 196, S_0x29fb160; + .timescale -9 -12; +P_0x291e8d8 .param/l "i" 3 196, +C4<0110>; +S_0x292e780 .scope module, "attempt" "OrNorXor" 3 198, 3 64, S_0x292c430; + .timescale -9 -12; +L_0x2cc8770/d .functor NOR 1, L_0x2cc99a0, L_0x2cc9a40, C4<0>, C4<0>; +L_0x2cc8770 .delay (10000,10000,10000) L_0x2cc8770/d; +L_0x2cc8860/d .functor NOT 1, L_0x2cc8770, C4<0>, C4<0>, C4<0>; +L_0x2cc8860 .delay (10000,10000,10000) L_0x2cc8860/d; +L_0x2cc8990/d .functor NAND 1, L_0x2cc99a0, L_0x2cc9a40, C4<1>, C4<1>; +L_0x2cc8990 .delay (10000,10000,10000) L_0x2cc8990/d; +L_0x2cc8af0/d .functor NAND 1, L_0x2cc8990, L_0x2cc8860, C4<1>, C4<1>; +L_0x2cc8af0 .delay (10000,10000,10000) L_0x2cc8af0/d; +L_0x2cc8c00/d .functor NOT 1, L_0x2cc8af0, C4<0>, C4<0>, C4<0>; +L_0x2cc8c00 .delay (10000,10000,10000) L_0x2cc8c00/d; +v0x293c240_0 .net "A", 0 0, L_0x2cc99a0; 1 drivers +v0x293c2e0_0 .net "AnandB", 0 0, L_0x2cc8990; 1 drivers +v0x293e6d0_0 .net "AnorB", 0 0, L_0x2cc8770; 1 drivers +v0x293e750_0 .net "AorB", 0 0, L_0x2cc8860; 1 drivers +v0x293e7d0_0 .net "AxorB", 0 0, L_0x2cc8c00; 1 drivers +v0x293e850_0 .net "B", 0 0, L_0x2cc9a40; 1 drivers +v0x2940b80_0 .alias "Command", 2 0, v0x2bc67a0_0; +v0x2940c00_0 .net "OrNorXorOut", 0 0, L_0x2cc9600; 1 drivers +v0x2940c80_0 .net "XorNor", 0 0, L_0x2cc9080; 1 drivers +v0x2943030_0 .net "nXor", 0 0, L_0x2cc8af0; 1 drivers +L_0x2cc9200 .part v0x2bc78e0_0, 2, 1; +L_0x2cc97d0 .part v0x2bc78e0_0, 0, 1; +S_0x2935540 .scope module, "mux0" "TwoInMux" 3 83, 3 8, S_0x292e780; + .timescale -9 -12; +L_0x2cc8d60/d .functor NOT 1, L_0x2cc9200, C4<0>, C4<0>, C4<0>; +L_0x2cc8d60 .delay (10000,10000,10000) L_0x2cc8d60/d; +L_0x2cc8e20/d .functor AND 1, L_0x2cc8c00, L_0x2cc8d60, C4<1>, C4<1>; +L_0x2cc8e20 .delay (20000,20000,20000) L_0x2cc8e20/d; +L_0x2cc8f30/d .functor AND 1, L_0x2cc8770, L_0x2cc9200, C4<1>, C4<1>; +L_0x2cc8f30 .delay (20000,20000,20000) L_0x2cc8f30/d; +L_0x2cc9080/d .functor OR 1, L_0x2cc8e20, L_0x2cc8f30, C4<0>, C4<0>; +L_0x2cc9080 .delay (20000,20000,20000) L_0x2cc9080/d; +v0x2937900_0 .net "S", 0 0, L_0x2cc9200; 1 drivers +v0x29379c0_0 .alias "in0", 0 0, v0x293e7d0_0; +v0x2937a60_0 .alias "in1", 0 0, v0x293e6d0_0; +v0x2939d60_0 .net "nS", 0 0, L_0x2cc8d60; 1 drivers +v0x2939de0_0 .net "out0", 0 0, L_0x2cc8e20; 1 drivers +v0x2939e80_0 .net "out1", 0 0, L_0x2cc8f30; 1 drivers +v0x293c1c0_0 .alias "outfinal", 0 0, v0x2940c80_0; +S_0x292e870 .scope module, "mux1" "TwoInMux" 3 84, 3 8, S_0x292e780; + .timescale -9 -12; +L_0x2cc92a0/d .functor NOT 1, L_0x2cc97d0, C4<0>, C4<0>, C4<0>; +L_0x2cc92a0 .delay (10000,10000,10000) L_0x2cc92a0/d; +L_0x2cc9360/d .functor AND 1, L_0x2cc9080, L_0x2cc92a0, C4<1>, C4<1>; +L_0x2cc9360 .delay (20000,20000,20000) L_0x2cc9360/d; +L_0x2cc94b0/d .functor AND 1, L_0x2cc8860, L_0x2cc97d0, C4<1>, C4<1>; +L_0x2cc94b0 .delay (20000,20000,20000) L_0x2cc94b0/d; +L_0x2cc9600/d .functor OR 1, L_0x2cc9360, L_0x2cc94b0, C4<0>, C4<0>; +L_0x2cc9600 .delay (20000,20000,20000) L_0x2cc9600/d; +v0x2930be0_0 .net "S", 0 0, L_0x2cc97d0; 1 drivers +v0x2930c60_0 .alias "in0", 0 0, v0x2940c80_0; +v0x2930d00_0 .alias "in1", 0 0, v0x293e750_0; +v0x2933040_0 .net "nS", 0 0, L_0x2cc92a0; 1 drivers +v0x29330c0_0 .net "out0", 0 0, L_0x2cc9360; 1 drivers +v0x2933160_0 .net "out1", 0 0, L_0x2cc94b0; 1 drivers +v0x29354a0_0 .alias "outfinal", 0 0, v0x2940c00_0; +S_0x290cab0 .scope generate, "orbits[7]" "orbits[7]" 3 196, 3 196, S_0x29fb160; + .timescale -9 -12; +P_0x2906238 .param/l "i" 3 196, +C4<0111>; +S_0x290cba0 .scope module, "attempt" "OrNorXor" 3 198, 3 64, S_0x290cab0; + .timescale -9 -12; +L_0x2cc9910/d .functor NOR 1, L_0x2ccaca0, L_0x2cc9ae0, C4<0>, C4<0>; +L_0x2cc9910 .delay (10000,10000,10000) L_0x2cc9910/d; +L_0x2cc9c10/d .functor NOT 1, L_0x2cc9910, C4<0>, C4<0>, C4<0>; +L_0x2cc9c10 .delay (10000,10000,10000) L_0x2cc9c10/d; +L_0x2cc9d20/d .functor NAND 1, L_0x2ccaca0, L_0x2cc9ae0, C4<1>, C4<1>; +L_0x2cc9d20 .delay (10000,10000,10000) L_0x2cc9d20/d; +L_0x2cc9e80/d .functor NAND 1, L_0x2cc9d20, L_0x2cc9c10, C4<1>, C4<1>; +L_0x2cc9e80 .delay (10000,10000,10000) L_0x2cc9e80/d; +L_0x2cc9f90/d .functor NOT 1, L_0x2cc9e80, C4<0>, C4<0>, C4<0>; +L_0x2cc9f90 .delay (10000,10000,10000) L_0x2cc9f90/d; +v0x2925640_0 .net "A", 0 0, L_0x2ccaca0; 1 drivers +v0x29279d0_0 .net "AnandB", 0 0, L_0x2cc9d20; 1 drivers +v0x2927a70_0 .net "AnorB", 0 0, L_0x2cc9910; 1 drivers +v0x2927af0_0 .net "AorB", 0 0, L_0x2cc9c10; 1 drivers +v0x2929e80_0 .net "AxorB", 0 0, L_0x2cc9f90; 1 drivers +v0x2929f00_0 .net "B", 0 0, L_0x2cc9ae0; 1 drivers +v0x2929f80_0 .alias "Command", 2 0, v0x2bc67a0_0; +v0x292a000_0 .net "OrNorXorOut", 0 0, L_0x2cca990; 1 drivers +v0x292c330_0 .net "XorNor", 0 0, L_0x2cca410; 1 drivers +v0x292c3b0_0 .net "nXor", 0 0, L_0x2cc9e80; 1 drivers +L_0x2cca590 .part v0x2bc78e0_0, 2, 1; +L_0x2ccab60 .part v0x2bc78e0_0, 0, 1; +S_0x2920bc0 .scope module, "mux0" "TwoInMux" 3 83, 3 8, S_0x290cba0; + .timescale -9 -12; +L_0x2cca0f0/d .functor NOT 1, L_0x2cca590, C4<0>, C4<0>, C4<0>; +L_0x2cca0f0 .delay (10000,10000,10000) L_0x2cca0f0/d; +L_0x2cca1b0/d .functor AND 1, L_0x2cc9f90, L_0x2cca0f0, C4<1>, C4<1>; +L_0x2cca1b0 .delay (20000,20000,20000) L_0x2cca1b0/d; +L_0x2cca2c0/d .functor AND 1, L_0x2cc9910, L_0x2cca590, C4<1>, C4<1>; +L_0x2cca2c0 .delay (20000,20000,20000) L_0x2cca2c0/d; +L_0x2cca410/d .functor OR 1, L_0x2cca1b0, L_0x2cca2c0, C4<0>, C4<0>; +L_0x2cca410 .delay (20000,20000,20000) L_0x2cca410/d; +v0x2920cb0_0 .net "S", 0 0, L_0x2cca590; 1 drivers +v0x291e850_0 .alias "in0", 0 0, v0x2929e80_0; +v0x2923070_0 .alias "in1", 0 0, v0x2927a70_0; +v0x2923110_0 .net "nS", 0 0, L_0x2cca0f0; 1 drivers +v0x2923190_0 .net "out0", 0 0, L_0x2cca1b0; 1 drivers +v0x2925520_0 .net "out1", 0 0, L_0x2cca2c0; 1 drivers +v0x29255c0_0 .alias "outfinal", 0 0, v0x292c330_0; +S_0x2962fa0 .scope module, "mux1" "TwoInMux" 3 84, 3 8, S_0x290cba0; + .timescale -9 -12; +L_0x2cca630/d .functor NOT 1, L_0x2ccab60, C4<0>, C4<0>, C4<0>; +L_0x2cca630 .delay (10000,10000,10000) L_0x2cca630/d; +L_0x2cca6f0/d .functor AND 1, L_0x2cca410, L_0x2cca630, C4<1>, C4<1>; +L_0x2cca6f0 .delay (20000,20000,20000) L_0x2cca6f0/d; +L_0x2cca840/d .functor AND 1, L_0x2cc9c10, L_0x2ccab60, C4<1>, C4<1>; +L_0x2cca840 .delay (20000,20000,20000) L_0x2cca840/d; +L_0x2cca990/d .functor OR 1, L_0x2cca6f0, L_0x2cca840, C4<0>, C4<0>; +L_0x2cca990 .delay (20000,20000,20000) L_0x2cca990/d; +v0x290b6f0_0 .net "S", 0 0, L_0x2ccab60; 1 drivers +v0x2963090_0 .alias "in0", 0 0, v0x292c330_0; +v0x291c1c0_0 .alias "in1", 0 0, v0x2927af0_0; +v0x291c260_0 .net "nS", 0 0, L_0x2cca630; 1 drivers +v0x291c2e0_0 .net "out0", 0 0, L_0x2cca6f0; 1 drivers +v0x291e710_0 .net "out1", 0 0, L_0x2cca840; 1 drivers +v0x291e7b0_0 .alias "outfinal", 0 0, v0x292a000_0; +S_0x28ff630 .scope generate, "orbits[8]" "orbits[8]" 3 196, 3 196, S_0x29fb160; + .timescale -9 -12; +P_0x28f23e8 .param/l "i" 3 196, +C4<01000>; +S_0x28ff740 .scope module, "attempt" "OrNorXor" 3 198, 3 64, S_0x28ff630; + .timescale -9 -12; +L_0x2ccadf0/d .functor NOR 1, L_0x2ccad40, L_0x2ccc050, C4<0>, C4<0>; +L_0x2ccadf0 .delay (10000,10000,10000) L_0x2ccadf0/d; +L_0x2ccaee0/d .functor NOT 1, L_0x2ccadf0, C4<0>, C4<0>, C4<0>; +L_0x2ccaee0 .delay (10000,10000,10000) L_0x2ccaee0/d; +L_0x2ccb010/d .functor NAND 1, L_0x2ccad40, L_0x2ccc050, C4<1>, C4<1>; +L_0x2ccb010 .delay (10000,10000,10000) L_0x2ccb010/d; +L_0x2ccb170/d .functor NAND 1, L_0x2ccb010, L_0x2ccaee0, C4<1>, C4<1>; +L_0x2ccb170 .delay (10000,10000,10000) L_0x2ccb170/d; +L_0x2ccb280/d .functor NOT 1, L_0x2ccb170, C4<0>, C4<0>, C4<0>; +L_0x2ccb280 .delay (10000,10000,10000) L_0x2ccb280/d; +v0x2908af0_0 .net "A", 0 0, L_0x2ccad40; 1 drivers +v0x2908b90_0 .net "AnandB", 0 0, L_0x2ccb010; 1 drivers +v0x2908c30_0 .net "AnorB", 0 0, L_0x2ccadf0; 1 drivers +v0x290a030_0 .net "AorB", 0 0, L_0x2ccaee0; 1 drivers +v0x290a0b0_0 .net "AxorB", 0 0, L_0x2ccb280; 1 drivers +v0x290a130_0 .net "B", 0 0, L_0x2ccc050; 1 drivers +v0x290a1b0_0 .alias "Command", 2 0, v0x2bc67a0_0; +v0x290b570_0 .net "OrNorXorOut", 0 0, L_0x2ccbc80; 1 drivers +v0x290b5f0_0 .net "XorNor", 0 0, L_0x2ccb700; 1 drivers +v0x290b670_0 .net "nXor", 0 0, L_0x2ccb170; 1 drivers +L_0x2ccb880 .part v0x2bc78e0_0, 2, 1; +L_0x2ccbe50 .part v0x2bc78e0_0, 0, 1; +S_0x2904b30 .scope module, "mux0" "TwoInMux" 3 83, 3 8, S_0x28ff740; + .timescale -9 -12; +L_0x2ccb3e0/d .functor NOT 1, L_0x2ccb880, C4<0>, C4<0>, C4<0>; +L_0x2ccb3e0 .delay (10000,10000,10000) L_0x2ccb3e0/d; +L_0x2ccb4a0/d .functor AND 1, L_0x2ccb280, L_0x2ccb3e0, C4<1>, C4<1>; +L_0x2ccb4a0 .delay (20000,20000,20000) L_0x2ccb4a0/d; +L_0x2ccb5b0/d .functor AND 1, L_0x2ccadf0, L_0x2ccb880, C4<1>, C4<1>; +L_0x2ccb5b0 .delay (20000,20000,20000) L_0x2ccb5b0/d; +L_0x2ccb700/d .functor OR 1, L_0x2ccb4a0, L_0x2ccb5b0, C4<0>, C4<0>; +L_0x2ccb700 .delay (20000,20000,20000) L_0x2ccb700/d; +v0x2904c20_0 .net "S", 0 0, L_0x2ccb880; 1 drivers +v0x2906070_0 .alias "in0", 0 0, v0x290a0b0_0; +v0x2906110_0 .alias "in1", 0 0, v0x2908c30_0; +v0x29061b0_0 .net "nS", 0 0, L_0x2ccb3e0; 1 drivers +v0x29075b0_0 .net "out0", 0 0, L_0x2ccb4a0; 1 drivers +v0x2907650_0 .net "out1", 0 0, L_0x2ccb5b0; 1 drivers +v0x29076f0_0 .alias "outfinal", 0 0, v0x290b5f0_0; +S_0x2900b70 .scope module, "mux1" "TwoInMux" 3 84, 3 8, S_0x28ff740; + .timescale -9 -12; +L_0x2ccb920/d .functor NOT 1, L_0x2ccbe50, C4<0>, C4<0>, C4<0>; +L_0x2ccb920 .delay (10000,10000,10000) L_0x2ccb920/d; +L_0x2ccb9e0/d .functor AND 1, L_0x2ccb700, L_0x2ccb920, C4<1>, C4<1>; +L_0x2ccb9e0 .delay (20000,20000,20000) L_0x2ccb9e0/d; +L_0x2ccbb30/d .functor AND 1, L_0x2ccaee0, L_0x2ccbe50, C4<1>, C4<1>; +L_0x2ccbb30 .delay (20000,20000,20000) L_0x2ccbb30/d; +L_0x2ccbc80/d .functor OR 1, L_0x2ccb9e0, L_0x2ccbb30, C4<0>, C4<0>; +L_0x2ccbc80 .delay (20000,20000,20000) L_0x2ccbc80/d; +v0x2900c60_0 .net "S", 0 0, L_0x2ccbe50; 1 drivers +v0x29020b0_0 .alias "in0", 0 0, v0x290b5f0_0; +v0x2902150_0 .alias "in1", 0 0, v0x290a030_0; +v0x29021f0_0 .net "nS", 0 0, L_0x2ccb920; 1 drivers +v0x29035f0_0 .net "out0", 0 0, L_0x2ccb9e0; 1 drivers +v0x2903690_0 .net "out1", 0 0, L_0x2ccbb30; 1 drivers +v0x2903730_0 .alias "outfinal", 0 0, v0x290b570_0; +S_0x297d500 .scope generate, "orbits[9]" "orbits[9]" 3 196, 3 196, S_0x29fb160; + .timescale -9 -12; +P_0x29b24f8 .param/l "i" 3 196, +C4<01001>; +S_0x297b490 .scope module, "attempt" "OrNorXor" 3 198, 3 64, S_0x297d500; + .timescale -9 -12; +L_0x2ccbf90/d .functor NOR 1, L_0x2ccd2c0, L_0x2ccc0f0, C4<0>, C4<0>; +L_0x2ccbf90 .delay (10000,10000,10000) L_0x2ccbf90/d; +L_0x2ccc210/d .functor NOT 1, L_0x2ccbf90, C4<0>, C4<0>, C4<0>; +L_0x2ccc210 .delay (10000,10000,10000) L_0x2ccc210/d; +L_0x2ccc340/d .functor NAND 1, L_0x2ccd2c0, L_0x2ccc0f0, C4<1>, C4<1>; +L_0x2ccc340 .delay (10000,10000,10000) L_0x2ccc340/d; +L_0x2ccc4a0/d .functor NAND 1, L_0x2ccc340, L_0x2ccc210, C4<1>, C4<1>; +L_0x2ccc4a0 .delay (10000,10000,10000) L_0x2ccc4a0/d; +L_0x2ccc5b0/d .functor NOT 1, L_0x2ccc4a0, C4<0>, C4<0>, C4<0>; +L_0x2ccc5b0 .delay (10000,10000,10000) L_0x2ccc5b0/d; +v0x2741210_0 .net "A", 0 0, L_0x2ccd2c0; 1 drivers +v0x28f0cf0_0 .net "AnandB", 0 0, L_0x2ccc340; 1 drivers +v0x28f0d90_0 .net "AnorB", 0 0, L_0x2ccbf90; 1 drivers +v0x28f0e10_0 .net "AorB", 0 0, L_0x2ccc210; 1 drivers +v0x28f22e0_0 .net "AxorB", 0 0, L_0x2ccc5b0; 1 drivers +v0x28f2360_0 .net "B", 0 0, L_0x2ccc0f0; 1 drivers +v0x28f2420_0 .alias "Command", 2 0, v0x2bc67a0_0; +v0x28fe0f0_0 .net "OrNorXorOut", 0 0, L_0x2cccfb0; 1 drivers +v0x28fe170_0 .net "XorNor", 0 0, L_0x2ccca30; 1 drivers +v0x28fe240_0 .net "nXor", 0 0, L_0x2ccc4a0; 1 drivers +L_0x2cccbb0 .part v0x2bc78e0_0, 2, 1; +L_0x2ccd180 .part v0x2bc78e0_0, 0, 1; +S_0x2764480 .scope module, "mux0" "TwoInMux" 3 83, 3 8, S_0x297b490; + .timescale -9 -12; +L_0x2ccc710/d .functor NOT 1, L_0x2cccbb0, C4<0>, C4<0>, C4<0>; +L_0x2ccc710 .delay (10000,10000,10000) L_0x2ccc710/d; +L_0x2ccc7d0/d .functor AND 1, L_0x2ccc5b0, L_0x2ccc710, C4<1>, C4<1>; +L_0x2ccc7d0 .delay (20000,20000,20000) L_0x2ccc7d0/d; +L_0x2ccc8e0/d .functor AND 1, L_0x2ccbf90, L_0x2cccbb0, C4<1>, C4<1>; +L_0x2ccc8e0 .delay (20000,20000,20000) L_0x2ccc8e0/d; +L_0x2ccca30/d .functor OR 1, L_0x2ccc7d0, L_0x2ccc8e0, C4<0>, C4<0>; +L_0x2ccca30 .delay (20000,20000,20000) L_0x2ccca30/d; +v0x282ef60_0 .net "S", 0 0, L_0x2cccbb0; 1 drivers +v0x27645b0_0 .alias "in0", 0 0, v0x28f22e0_0; +v0x270ecf0_0 .alias "in1", 0 0, v0x28f0d90_0; +v0x270ed90_0 .net "nS", 0 0, L_0x2ccc710; 1 drivers +v0x270ee10_0 .net "out0", 0 0, L_0x2ccc7d0; 1 drivers +v0x27410f0_0 .net "out1", 0 0, L_0x2ccc8e0; 1 drivers +v0x2741190_0 .alias "outfinal", 0 0, v0x28fe170_0; +S_0x2a10d70 .scope module, "mux1" "TwoInMux" 3 84, 3 8, S_0x297b490; + .timescale -9 -12; +L_0x2cccc50/d .functor NOT 1, L_0x2ccd180, C4<0>, C4<0>, C4<0>; +L_0x2cccc50 .delay (10000,10000,10000) L_0x2cccc50/d; +L_0x2cccd10/d .functor AND 1, L_0x2ccca30, L_0x2cccc50, C4<1>, C4<1>; +L_0x2cccd10 .delay (20000,20000,20000) L_0x2cccd10/d; +L_0x2ccce60/d .functor AND 1, L_0x2ccc210, L_0x2ccd180, C4<1>, C4<1>; +L_0x2ccce60 .delay (20000,20000,20000) L_0x2ccce60/d; +L_0x2cccfb0/d .functor OR 1, L_0x2cccd10, L_0x2ccce60, C4<0>, C4<0>; +L_0x2cccfb0 .delay (20000,20000,20000) L_0x2cccfb0/d; +v0x297b580_0 .net "S", 0 0, L_0x2ccd180; 1 drivers +v0x2a10e60_0 .alias "in0", 0 0, v0x28fe170_0; +v0x2852170_0 .alias "in1", 0 0, v0x28f0e10_0; +v0x2852210_0 .net "nS", 0 0, L_0x2cccc50; 1 drivers +v0x2852290_0 .net "out0", 0 0, L_0x2cccd10; 1 drivers +v0x282ee20_0 .net "out1", 0 0, L_0x2ccce60; 1 drivers +v0x282eec0_0 .alias "outfinal", 0 0, v0x28fe0f0_0; +S_0x29d38e0 .scope generate, "orbits[10]" "orbits[10]" 3 196, 3 196, S_0x29fb160; + .timescale -9 -12; +P_0x2971f08 .param/l "i" 3 196, +C4<01010>; +S_0x29bdff0 .scope module, "attempt" "OrNorXor" 3 198, 3 64, S_0x29d38e0; + .timescale -9 -12; +L_0x2ccd440/d .functor NOR 1, L_0x2ccd360, L_0x2cce6c0, C4<0>, C4<0>; +L_0x2ccd440 .delay (10000,10000,10000) L_0x2ccd440/d; +L_0x2ccd530/d .functor NOT 1, L_0x2ccd440, C4<0>, C4<0>, C4<0>; +L_0x2ccd530 .delay (10000,10000,10000) L_0x2ccd530/d; +L_0x2ccd640/d .functor NAND 1, L_0x2ccd360, L_0x2cce6c0, C4<1>, C4<1>; +L_0x2ccd640 .delay (10000,10000,10000) L_0x2ccd640/d; +L_0x2ccd7a0/d .functor NAND 1, L_0x2ccd640, L_0x2ccd530, C4<1>, C4<1>; +L_0x2ccd7a0 .delay (10000,10000,10000) L_0x2ccd7a0/d; +L_0x2ccd8b0/d .functor NOT 1, L_0x2ccd7a0, C4<0>, C4<0>, C4<0>; +L_0x2ccd8b0 .delay (10000,10000,10000) L_0x2ccd8b0/d; +v0x2998a40_0 .net "A", 0 0, L_0x2ccd360; 1 drivers +v0x2994c50_0 .net "AnandB", 0 0, L_0x2ccd640; 1 drivers +v0x2994cf0_0 .net "AnorB", 0 0, L_0x2ccd440; 1 drivers +v0x2992ba0_0 .net "AorB", 0 0, L_0x2ccd530; 1 drivers +v0x2992c20_0 .net "AxorB", 0 0, L_0x2ccd8b0; 1 drivers +v0x2992ca0_0 .net "B", 0 0, L_0x2cce6c0; 1 drivers +v0x298ee70_0 .alias "Command", 2 0, v0x2bc67a0_0; +v0x298eef0_0 .net "OrNorXorOut", 0 0, L_0x2cce2c0; 1 drivers +v0x298ef70_0 .net "XorNor", 0 0, L_0x2ccdd50; 1 drivers +v0x297d480_0 .net "nXor", 0 0, L_0x2ccd7a0; 1 drivers +L_0x2ccded0 .part v0x2bc78e0_0, 2, 1; +L_0x2cce490 .part v0x2bc78e0_0, 0, 1; +S_0x29b0300 .scope module, "mux0" "TwoInMux" 3 83, 3 8, S_0x29bdff0; + .timescale -9 -12; +L_0x2ccda10/d .functor NOT 1, L_0x2ccded0, C4<0>, C4<0>, C4<0>; +L_0x2ccda10 .delay (10000,10000,10000) L_0x2ccda10/d; +L_0x2ccdaf0/d .functor AND 1, L_0x2ccd8b0, L_0x2ccda10, C4<1>, C4<1>; +L_0x2ccdaf0 .delay (20000,20000,20000) L_0x2ccdaf0/d; +L_0x2ccdc00/d .functor AND 1, L_0x2ccd440, L_0x2ccded0, C4<1>, C4<1>; +L_0x2ccdc00 .delay (20000,20000,20000) L_0x2ccdc00/d; +L_0x2ccdd50/d .functor OR 1, L_0x2ccdaf0, L_0x2ccdc00, C4<0>, C4<0>; +L_0x2ccdd50 .delay (20000,20000,20000) L_0x2ccdd50/d; +v0x29b03f0_0 .net "S", 0 0, L_0x2ccded0; 1 drivers +v0x29b2450_0 .alias "in0", 0 0, v0x2992c20_0; +v0x299e7e0_0 .alias "in1", 0 0, v0x2994cf0_0; +v0x299e880_0 .net "nS", 0 0, L_0x2ccda10; 1 drivers +v0x299aa70_0 .net "out0", 0 0, L_0x2ccdaf0; 1 drivers +v0x299ab10_0 .net "out1", 0 0, L_0x2ccdc00; 1 drivers +v0x29989c0_0 .alias "outfinal", 0 0, v0x298ef70_0; +S_0x29bbf40 .scope module, "mux1" "TwoInMux" 3 84, 3 8, S_0x29bdff0; + .timescale -9 -12; +L_0x2ccdf70/d .functor NOT 1, L_0x2cce490, C4<0>, C4<0>, C4<0>; +L_0x2ccdf70 .delay (10000,10000,10000) L_0x2ccdf70/d; +L_0x2cce030/d .functor AND 1, L_0x2ccdd50, L_0x2ccdf70, C4<1>, C4<1>; +L_0x2cce030 .delay (20000,20000,20000) L_0x2cce030/d; +L_0x29c9dd0/d .functor AND 1, L_0x2ccd530, L_0x2cce490, C4<1>, C4<1>; +L_0x29c9dd0 .delay (20000,20000,20000) L_0x29c9dd0/d; +L_0x2cce2c0/d .functor OR 1, L_0x2cce030, L_0x29c9dd0, C4<0>, C4<0>; +L_0x2cce2c0 .delay (20000,20000,20000) L_0x2cce2c0/d; +v0x29be0e0_0 .net "S", 0 0, L_0x2cce490; 1 drivers +v0x29bc030_0 .alias "in0", 0 0, v0x298ef70_0; +v0x29b81d0_0 .alias "in1", 0 0, v0x2992ba0_0; +v0x29b8270_0 .net "nS", 0 0, L_0x2ccdf70; 1 drivers +v0x29b6120_0 .net "out0", 0 0, L_0x2cce030; 1 drivers +v0x29b61c0_0 .net "out1", 0 0, L_0x29c9dd0; 1 drivers +v0x29b23b0_0 .alias "outfinal", 0 0, v0x298eef0_0; +S_0x29759b0 .scope generate, "orbits[11]" "orbits[11]" 3 196, 3 196, S_0x29fb160; + .timescale -9 -12; +P_0x2a116d8 .param/l "i" 3 196, +C4<01011>; +S_0x29fecb0 .scope module, "attempt" "OrNorXor" 3 198, 3 64, S_0x29759b0; + .timescale -9 -12; +L_0x2cce5d0/d .functor NOR 1, L_0x2ccf900, L_0x2cce760, C4<0>, C4<0>; +L_0x2cce5d0 .delay (10000,10000,10000) L_0x2cce5d0/d; +L_0x2cce860/d .functor NOT 1, L_0x2cce5d0, C4<0>, C4<0>, C4<0>; +L_0x2cce860 .delay (10000,10000,10000) L_0x2cce860/d; +L_0x2cce950/d .functor NAND 1, L_0x2ccf900, L_0x2cce760, C4<1>, C4<1>; +L_0x2cce950 .delay (10000,10000,10000) L_0x2cce950/d; +L_0x2cceab0/d .functor NAND 1, L_0x2cce950, L_0x2cce860, C4<1>, C4<1>; +L_0x2cceab0 .delay (10000,10000,10000) L_0x2cceab0/d; +L_0x2ccebc0/d .functor NOT 1, L_0x2cceab0, C4<0>, C4<0>, C4<0>; +L_0x2ccebc0 .delay (10000,10000,10000) L_0x2ccebc0/d; +v0x29db7b0_0 .net "A", 0 0, L_0x2ccf900; 1 drivers +v0x29d9680_0 .net "AnandB", 0 0, L_0x2cce950; 1 drivers +v0x29d9720_0 .net "AnorB", 0 0, L_0x2cce5d0; 1 drivers +v0x296fdd0_0 .net "AorB", 0 0, L_0x2cce860; 1 drivers +v0x296fe50_0 .net "AxorB", 0 0, L_0x2ccebc0; 1 drivers +v0x296fed0_0 .net "B", 0 0, L_0x2cce760; 1 drivers +v0x29d5910_0 .alias "Command", 2 0, v0x2bc67a0_0; +v0x29d5990_0 .net "OrNorXorOut", 0 0, L_0x2ccf5f0; 1 drivers +v0x29d5a10_0 .net "XorNor", 0 0, L_0x2ccf060; 1 drivers +v0x29d3860_0 .net "nXor", 0 0, L_0x2cceab0; 1 drivers +L_0x2ccf1e0 .part v0x2bc78e0_0, 2, 1; +L_0x2ccf7c0 .part v0x2bc78e0_0, 0, 1; +S_0x29f0fa0 .scope module, "mux0" "TwoInMux" 3 83, 3 8, S_0x29fecb0; + .timescale -9 -12; +L_0x2cced20/d .functor NOT 1, L_0x2ccf1e0, C4<0>, C4<0>, C4<0>; +L_0x2cced20 .delay (10000,10000,10000) L_0x2cced20/d; +L_0x2ccee00/d .functor AND 1, L_0x2ccebc0, L_0x2cced20, C4<1>, C4<1>; +L_0x2ccee00 .delay (20000,20000,20000) L_0x2ccee00/d; +L_0x2ccef10/d .functor AND 1, L_0x2cce5d0, L_0x2ccf1e0, C4<1>, C4<1>; +L_0x2ccef10 .delay (20000,20000,20000) L_0x2ccef10/d; +L_0x2ccf060/d .functor OR 1, L_0x2ccee00, L_0x2ccef10, C4<0>, C4<0>; +L_0x2ccf060 .delay (20000,20000,20000) L_0x2ccf060/d; +v0x29f1090_0 .net "S", 0 0, L_0x2ccf1e0; 1 drivers +v0x29f3110_0 .alias "in0", 0 0, v0x296fe50_0; +v0x2971dc0_0 .alias "in1", 0 0, v0x29d9720_0; +v0x2971e60_0 .net "nS", 0 0, L_0x2cced20; 1 drivers +v0x29df4a0_0 .net "out0", 0 0, L_0x2ccee00; 1 drivers +v0x29df540_0 .net "out1", 0 0, L_0x2ccef10; 1 drivers +v0x29db730_0 .alias "outfinal", 0 0, v0x29d5a10_0; +S_0x29fcc00 .scope module, "mux1" "TwoInMux" 3 84, 3 8, S_0x29fecb0; + .timescale -9 -12; +L_0x2ccf280/d .functor NOT 1, L_0x2ccf7c0, C4<0>, C4<0>, C4<0>; +L_0x2ccf280 .delay (10000,10000,10000) L_0x2ccf280/d; +L_0x2ccf360/d .functor AND 1, L_0x2ccf060, L_0x2ccf280, C4<1>, C4<1>; +L_0x2ccf360 .delay (20000,20000,20000) L_0x2ccf360/d; +L_0x29cfc30/d .functor AND 1, L_0x2cce860, L_0x2ccf7c0, C4<1>, C4<1>; +L_0x29cfc30 .delay (20000,20000,20000) L_0x29cfc30/d; +L_0x2ccf5f0/d .functor OR 1, L_0x2ccf360, L_0x29cfc30, C4<0>, C4<0>; +L_0x2ccf5f0 .delay (20000,20000,20000) L_0x2ccf5f0/d; +v0x29feda0_0 .net "S", 0 0, L_0x2ccf7c0; 1 drivers +v0x29fccf0_0 .alias "in0", 0 0, v0x29d5a10_0; +v0x29f8e90_0 .alias "in1", 0 0, v0x296fdd0_0; +v0x29f8f30_0 .net "nS", 0 0, L_0x2ccf280; 1 drivers +v0x29f6de0_0 .net "out0", 0 0, L_0x2ccf360; 1 drivers +v0x29f6e80_0 .net "out1", 0 0, L_0x29cfc30; 1 drivers +v0x29f3070_0 .alias "outfinal", 0 0, v0x29d5990_0; +S_0x2a11070 .scope generate, "orbits[12]" "orbits[12]" 3 196, 3 196, S_0x29fb160; + .timescale -9 -12; +P_0x2a08ea8 .param/l "i" 3 196, +C4<01100>; +S_0x2a127f0 .scope module, "attempt" "OrNorXor" 3 198, 3 64, S_0x2a11070; + .timescale -9 -12; +L_0x2cce800/d .functor NOR 1, L_0x2ccf9a0, L_0x2cd0d50, C4<0>, C4<0>; +L_0x2cce800 .delay (10000,10000,10000) L_0x2cce800/d; +L_0x2ccfb40/d .functor NOT 1, L_0x2cce800, C4<0>, C4<0>, C4<0>; +L_0x2ccfb40 .delay (10000,10000,10000) L_0x2ccfb40/d; +L_0x2ccfc70/d .functor NAND 1, L_0x2ccf9a0, L_0x2cd0d50, C4<1>, C4<1>; +L_0x2ccfc70 .delay (10000,10000,10000) L_0x2ccfc70/d; +L_0x2ccfdd0/d .functor NAND 1, L_0x2ccfc70, L_0x2ccfb40, C4<1>, C4<1>; +L_0x2ccfdd0 .delay (10000,10000,10000) L_0x2ccfdd0/d; +L_0x2ccfee0/d .functor NOT 1, L_0x2ccfdd0, C4<0>, C4<0>, C4<0>; +L_0x2ccfee0 .delay (10000,10000,10000) L_0x2ccfee0/d; +v0x2a14b80_0 .net "A", 0 0, L_0x2ccf9a0; 1 drivers +v0x2977920_0 .net "AnandB", 0 0, L_0x2ccfc70; 1 drivers +v0x29779c0_0 .net "AnorB", 0 0, L_0x2cce800; 1 drivers +v0x2a165f0_0 .net "AorB", 0 0, L_0x2ccfb40; 1 drivers +v0x2a16670_0 .net "AxorB", 0 0, L_0x2ccfee0; 1 drivers +v0x2a166f0_0 .net "B", 0 0, L_0x2cd0d50; 1 drivers +v0x2a14540_0 .alias "Command", 2 0, v0x2bc67a0_0; +v0x2a145c0_0 .net "OrNorXorOut", 0 0, L_0x2cd0920; 1 drivers +v0x2a14640_0 .net "XorNor", 0 0, L_0x2cd03a0; 1 drivers +v0x2975930_0 .net "nXor", 0 0, L_0x2ccfdd0; 1 drivers +L_0x2cd0520 .part v0x2bc78e0_0, 2, 1; +L_0x2cd0af0 .part v0x2bc78e0_0, 0, 1; +S_0x2a15300 .scope module, "mux0" "TwoInMux" 3 83, 3 8, S_0x2a127f0; + .timescale -9 -12; +L_0x2cd0040/d .functor NOT 1, L_0x2cd0520, C4<0>, C4<0>, C4<0>; +L_0x2cd0040 .delay (10000,10000,10000) L_0x2cd0040/d; +L_0x2cd0120/d .functor AND 1, L_0x2ccfee0, L_0x2cd0040, C4<1>, C4<1>; +L_0x2cd0120 .delay (20000,20000,20000) L_0x2cd0120/d; +L_0x2cd0250/d .functor AND 1, L_0x2cce800, L_0x2cd0520, C4<1>, C4<1>; +L_0x2cd0250 .delay (20000,20000,20000) L_0x2cd0250/d; +L_0x2cd03a0/d .functor OR 1, L_0x2cd0120, L_0x2cd0250, C4<0>, C4<0>; +L_0x2cd03a0 .delay (20000,20000,20000) L_0x2cd03a0/d; +v0x2a16c90_0 .net "S", 0 0, L_0x2cd0520; 1 drivers +v0x2a15050_0 .alias "in0", 0 0, v0x2a16670_0; +v0x2a150f0_0 .alias "in1", 0 0, v0x29779c0_0; +v0x2a18610_0 .net "nS", 0 0, L_0x2cd0040; 1 drivers +v0x2a186b0_0 .net "out0", 0 0, L_0x2cd0120; 1 drivers +v0x2a14da0_0 .net "out1", 0 0, L_0x2cd0250; 1 drivers +v0x2a14b00_0 .alias "outfinal", 0 0, v0x2a14640_0; +S_0x2a0ec80 .scope module, "mux1" "TwoInMux" 3 84, 3 8, S_0x2a127f0; + .timescale -9 -12; +L_0x2cd05c0/d .functor NOT 1, L_0x2cd0af0, C4<0>, C4<0>, C4<0>; +L_0x2cd05c0 .delay (10000,10000,10000) L_0x2cd05c0/d; +L_0x2cd0680/d .functor AND 1, L_0x2cd03a0, L_0x2cd05c0, C4<1>, C4<1>; +L_0x2cd0680 .delay (20000,20000,20000) L_0x2cd0680/d; +L_0x2cd07d0/d .functor AND 1, L_0x2ccfb40, L_0x2cd0af0, C4<1>, C4<1>; +L_0x2cd07d0 .delay (20000,20000,20000) L_0x2cd07d0/d; +L_0x2cd0920/d .functor OR 1, L_0x2cd0680, L_0x2cd07d0, C4<0>, C4<0>; +L_0x2cd0920 .delay (20000,20000,20000) L_0x2cd0920/d; +v0x2a113a0_0 .net "S", 0 0, L_0x2cd0af0; 1 drivers +v0x2a173f0_0 .alias "in0", 0 0, v0x2a14640_0; +v0x2a17490_0 .alias "in1", 0 0, v0x2a165f0_0; +v0x2a17140_0 .net "nS", 0 0, L_0x2cd05c0; 1 drivers +v0x2a171c0_0 .net "out0", 0 0, L_0x2cd0680; 1 drivers +v0x2a16e90_0 .net "out1", 0 0, L_0x2cd07d0; 1 drivers +v0x2a16bf0_0 .alias "outfinal", 0 0, v0x2a145c0_0; +S_0x29f78f0 .scope generate, "orbits[13]" "orbits[13]" 3 196, 3 196, S_0x29fb160; + .timescale -9 -12; +P_0x29f97b8 .param/l "i" 3 196, +C4<01101>; +S_0x29faeb0 .scope module, "attempt" "OrNorXor" 3 198, 3 64, S_0x29f78f0; + .timescale -9 -12; +L_0x2ccfa40/d .functor NOR 1, L_0x2cd1f90, L_0x2cd0df0, C4<0>, C4<0>; +L_0x2ccfa40 .delay (10000,10000,10000) L_0x2ccfa40/d; +L_0x2cd0cc0/d .functor NOT 1, L_0x2ccfa40, C4<0>, C4<0>, C4<0>; +L_0x2cd0cc0 .delay (10000,10000,10000) L_0x2cd0cc0/d; +L_0x2cd0fd0/d .functor NAND 1, L_0x2cd1f90, L_0x2cd0df0, C4<1>, C4<1>; +L_0x2cd0fd0 .delay (10000,10000,10000) L_0x2cd0fd0/d; +L_0x2cd1130/d .functor NAND 1, L_0x2cd0fd0, L_0x2cd0cc0, C4<1>, C4<1>; +L_0x2cd1130 .delay (10000,10000,10000) L_0x2cd1130/d; +L_0x2cd1240/d .functor NOT 1, L_0x2cd1130, C4<0>, C4<0>, C4<0>; +L_0x2cd1240 .delay (10000,10000,10000) L_0x2cd1240/d; +v0x2a05130_0 .net "A", 0 0, L_0x2cd1f90; 1 drivers +v0x2a02fc0_0 .net "AnandB", 0 0, L_0x2cd0fd0; 1 drivers +v0x2a03060_0 .net "AnorB", 0 0, L_0x2ccfa40; 1 drivers +v0x2a0af10_0 .net "AorB", 0 0, L_0x2cd0cc0; 1 drivers +v0x2a0af90_0 .net "AxorB", 0 0, L_0x2cd1240; 1 drivers +v0x2a08e20_0 .net "B", 0 0, L_0x2cd0df0; 1 drivers +v0x2a08ee0_0 .alias "Command", 2 0, v0x2bc67a0_0; +v0x2a115d0_0 .net "OrNorXorOut", 0 0, L_0x2cd1c80; 1 drivers +v0x2a11650_0 .net "XorNor", 0 0, L_0x2cd1700; 1 drivers +v0x2a11320_0 .net "nXor", 0 0, L_0x2cd1130; 1 drivers +L_0x2cd1880 .part v0x2bc78e0_0, 2, 1; +L_0x2cd1e50 .part v0x2bc78e0_0, 0, 1; +S_0x29fd9c0 .scope module, "mux0" "TwoInMux" 3 83, 3 8, S_0x29faeb0; + .timescale -9 -12; +L_0x2cd13a0/d .functor NOT 1, L_0x2cd1880, C4<0>, C4<0>, C4<0>; +L_0x2cd13a0 .delay (10000,10000,10000) L_0x2cd13a0/d; +L_0x2cd1480/d .functor AND 1, L_0x2cd1240, L_0x2cd13a0, C4<1>, C4<1>; +L_0x2cd1480 .delay (20000,20000,20000) L_0x2cd1480/d; +L_0x2cd15b0/d .functor AND 1, L_0x2ccfa40, L_0x2cd1880, C4<1>, C4<1>; +L_0x2cd15b0 .delay (20000,20000,20000) L_0x2cd15b0/d; +L_0x2cd1700/d .functor OR 1, L_0x2cd1480, L_0x2cd15b0, C4<0>, C4<0>; +L_0x2cd1700 .delay (20000,20000,20000) L_0x2cd1700/d; +v0x29ff350_0 .net "S", 0 0, L_0x2cd1880; 1 drivers +v0x29fd710_0 .alias "in0", 0 0, v0x2a0af90_0; +v0x29fd7b0_0 .alias "in1", 0 0, v0x2a03060_0; +v0x29fd460_0 .net "nS", 0 0, L_0x2cd13a0; 1 drivers +v0x29fd500_0 .net "out0", 0 0, L_0x2cd1480; 1 drivers +v0x29fd1c0_0 .net "out1", 0 0, L_0x2cd15b0; 1 drivers +v0x2a050b0_0 .alias "outfinal", 0 0, v0x2a11650_0; +S_0x29f7640 .scope module, "mux1" "TwoInMux" 3 84, 3 8, S_0x29faeb0; + .timescale -9 -12; +L_0x2cd1920/d .functor NOT 1, L_0x2cd1e50, C4<0>, C4<0>, C4<0>; +L_0x2cd1920 .delay (10000,10000,10000) L_0x2cd1920/d; +L_0x2cd19e0/d .functor AND 1, L_0x2cd1700, L_0x2cd1920, C4<1>, C4<1>; +L_0x2cd19e0 .delay (20000,20000,20000) L_0x2cd19e0/d; +L_0x2cd1b30/d .functor AND 1, L_0x2cd0cc0, L_0x2cd1e50, C4<1>, C4<1>; +L_0x2cd1b30 .delay (20000,20000,20000) L_0x2cd1b30/d; +L_0x2cd1c80/d .functor OR 1, L_0x2cd19e0, L_0x2cd1b30, C4<0>, C4<0>; +L_0x2cd1c80 .delay (20000,20000,20000) L_0x2cd1c80/d; +v0x29f7c20_0 .net "S", 0 0, L_0x2cd1e50; 1 drivers +v0x29f73a0_0 .alias "in0", 0 0, v0x2a11650_0; +v0x29f7440_0 .alias "in1", 0 0, v0x2a0af10_0; +v0x29ff800_0 .net "nS", 0 0, L_0x2cd1920; 1 drivers +v0x29ff880_0 .net "out0", 0 0, L_0x2cd19e0; 1 drivers +v0x29ff550_0 .net "out1", 0 0, L_0x2cd1b30; 1 drivers +v0x29ff2b0_0 .alias "outfinal", 0 0, v0x2a115d0_0; +S_0x29e5860 .scope generate, "orbits[14]" "orbits[14]" 3 196, 3 196, S_0x29fb160; + .timescale -9 -12; +P_0x29e79d8 .param/l "i" 3 196, +C4<01110>; +S_0x29ed7b0 .scope module, "attempt" "OrNorXor" 3 198, 3 64, S_0x29e5860; + .timescale -9 -12; +L_0x2cd0e90/d .functor NOR 1, L_0x2cd2030, L_0x2cd20d0, C4<0>, C4<0>; +L_0x2cd0e90 .delay (10000,10000,10000) L_0x2cd0e90/d; +L_0x2cd2200/d .functor NOT 1, L_0x2cd0e90, C4<0>, C4<0>, C4<0>; +L_0x2cd2200 .delay (10000,10000,10000) L_0x2cd2200/d; +L_0x2cd2330/d .functor NAND 1, L_0x2cd2030, L_0x2cd20d0, C4<1>, C4<1>; +L_0x2cd2330 .delay (10000,10000,10000) L_0x2cd2330/d; +L_0x2cd2490/d .functor NAND 1, L_0x2cd2330, L_0x2cd2200, C4<1>, C4<1>; +L_0x2cd2490 .delay (10000,10000,10000) L_0x2cd2490/d; +L_0x2cd25a0/d .functor NOT 1, L_0x2cd2490, C4<0>, C4<0>, C4<0>; +L_0x2cd25a0 .delay (10000,10000,10000) L_0x2cd25a0/d; +v0x29f1600_0 .net "A", 0 0, L_0x2cd2030; 1 drivers +v0x29f9c90_0 .net "AnandB", 0 0, L_0x2cd2330; 1 drivers +v0x29f9d30_0 .net "AnorB", 0 0, L_0x2cd0e90; 1 drivers +v0x29f99e0_0 .net "AorB", 0 0, L_0x2cd2200; 1 drivers +v0x29f9a60_0 .net "AxorB", 0 0, L_0x2cd25a0; 1 drivers +v0x29f9730_0 .net "B", 0 0, L_0x2cd20d0; 1 drivers +v0x29f97f0_0 .alias "Command", 2 0, v0x2bc67a0_0; +v0x29f9490_0 .net "OrNorXorOut", 0 0, L_0x2cd3020; 1 drivers +v0x29f9510_0 .net "XorNor", 0 0, L_0x2cd2a80; 1 drivers +v0x29f7ba0_0 .net "nXor", 0 0, L_0x2cd2490; 1 drivers +L_0x2cd2c00 .part v0x2bc78e0_0, 2, 1; +L_0x2cd31f0 .part v0x2bc78e0_0, 0, 1; +S_0x29f1d80 .scope module, "mux0" "TwoInMux" 3 83, 3 8, S_0x29ed7b0; + .timescale -9 -12; +L_0x2cd2720/d .functor NOT 1, L_0x2cd2c00, C4<0>, C4<0>, C4<0>; +L_0x2cd2720 .delay (10000,10000,10000) L_0x2cd2720/d; +L_0x2cd2800/d .functor AND 1, L_0x2cd25a0, L_0x2cd2720, C4<1>, C4<1>; +L_0x2cd2800 .delay (20000,20000,20000) L_0x2cd2800/d; +L_0x2cd2930/d .functor AND 1, L_0x2cd0e90, L_0x2cd2c00, C4<1>, C4<1>; +L_0x2cd2930 .delay (20000,20000,20000) L_0x2cd2930/d; +L_0x2cd2a80/d .functor OR 1, L_0x2cd2800, L_0x2cd2930, C4<0>, C4<0>; +L_0x2cd2a80 .delay (20000,20000,20000) L_0x2cd2a80/d; +v0x29f3710_0 .net "S", 0 0, L_0x2cd2c00; 1 drivers +v0x29f1ad0_0 .alias "in0", 0 0, v0x29f9a60_0; +v0x29f1b70_0 .alias "in1", 0 0, v0x29f9d30_0; +v0x29f5090_0 .net "nS", 0 0, L_0x2cd2720; 1 drivers +v0x29f5130_0 .net "out0", 0 0, L_0x2cd2800; 1 drivers +v0x29f1820_0 .net "out1", 0 0, L_0x2cd2930; 1 drivers +v0x29f1580_0 .alias "outfinal", 0 0, v0x29f9510_0; +S_0x29eb6c0 .scope module, "mux1" "TwoInMux" 3 84, 3 8, S_0x29ed7b0; + .timescale -9 -12; +L_0x2cd2ca0/d .functor NOT 1, L_0x2cd31f0, C4<0>, C4<0>, C4<0>; +L_0x2cd2ca0 .delay (10000,10000,10000) L_0x2cd2ca0/d; +L_0x2cd2d60/d .functor AND 1, L_0x2cd2a80, L_0x2cd2ca0, C4<1>, C4<1>; +L_0x2cd2d60 .delay (20000,20000,20000) L_0x2cd2d60/d; +L_0x2cd2eb0/d .functor AND 1, L_0x2cd2200, L_0x2cd31f0, C4<1>, C4<1>; +L_0x2cd2eb0 .delay (20000,20000,20000) L_0x2cd2eb0/d; +L_0x2cd3020/d .functor OR 1, L_0x2cd2d60, L_0x2cd2eb0, C4<0>, C4<0>; +L_0x2cd3020 .delay (20000,20000,20000) L_0x2cd3020/d; +v0x29f3e70_0 .net "S", 0 0, L_0x2cd31f0; 1 drivers +v0x29f3f10_0 .alias "in0", 0 0, v0x29f9510_0; +v0x29f3bc0_0 .alias "in1", 0 0, v0x29f99e0_0; +v0x29f3c60_0 .net "nS", 0 0, L_0x2cd2ca0; 1 drivers +v0x29f3910_0 .net "out0", 0 0, L_0x2cd2d60; 1 drivers +v0x29f39b0_0 .net "out1", 0 0, L_0x2cd2eb0; 1 drivers +v0x29f3670_0 .alias "outfinal", 0 0, v0x29f9490_0; +S_0x29d4370 .scope generate, "orbits[15]" "orbits[15]" 3 196, 3 196, S_0x29fb160; + .timescale -9 -12; +P_0x29d6238 .param/l "i" 3 196, +C4<01111>; +S_0x29d7930 .scope module, "attempt" "OrNorXor" 3 198, 3 64, S_0x29d4370; + .timescale -9 -12; +L_0x2cd3490/d .functor NOR 1, L_0x2cd4530, L_0x2cd3330, C4<0>, C4<0>; +L_0x2cd3490 .delay (10000,10000,10000) L_0x2cd3490/d; +L_0x2cd3580/d .functor NOT 1, L_0x2cd3490, C4<0>, C4<0>, C4<0>; +L_0x2cd3580 .delay (10000,10000,10000) L_0x2cd3580/d; +L_0x2cd36b0/d .functor NAND 1, L_0x2cd4530, L_0x2cd3330, C4<1>, C4<1>; +L_0x2cd36b0 .delay (10000,10000,10000) L_0x2cd36b0/d; +L_0x2cd3810/d .functor NAND 1, L_0x2cd36b0, L_0x2cd3580, C4<1>, C4<1>; +L_0x2cd3810 .delay (10000,10000,10000) L_0x2cd3810/d; +L_0x2cd3920/d .functor NOT 1, L_0x2cd3810, C4<0>, C4<0>, C4<0>; +L_0x2cd3920 .delay (10000,10000,10000) L_0x2cd3920/d; +v0x29d9f60_0 .net "A", 0 0, L_0x2cd4530; 1 drivers +v0x29d9c40_0 .net "AnandB", 0 0, L_0x2cd36b0; 1 drivers +v0x29d9ce0_0 .net "AnorB", 0 0, L_0x2cd3490; 1 drivers +v0x29e1af0_0 .net "AorB", 0 0, L_0x2cd3580; 1 drivers +v0x29e1b70_0 .net "AxorB", 0 0, L_0x2cd3920; 1 drivers +v0x29e7950_0 .net "B", 0 0, L_0x2cd3330; 1 drivers +v0x29e7a10_0 .alias "Command", 2 0, v0x2bc67a0_0; +v0x266a600_0 .net "OrNorXorOut", 0 0, L_0x2cd4260; 1 drivers +v0x2986f40_0 .net "XorNor", 0 0, L_0x2cd3de0; 1 drivers +v0x2986fc0_0 .net "nXor", 0 0, L_0x2cd3810; 1 drivers +L_0x2cd3f60 .part v0x2bc78e0_0, 2, 1; +L_0x2cd43f0 .part v0x2bc78e0_0, 0, 1; +S_0x29dbd30 .scope module, "mux0" "TwoInMux" 3 83, 3 8, S_0x29d7930; + .timescale -9 -12; +L_0x2cd3a80/d .functor NOT 1, L_0x2cd3f60, C4<0>, C4<0>, C4<0>; +L_0x2cd3a80 .delay (10000,10000,10000) L_0x2cd3a80/d; +L_0x2cd3b60/d .functor AND 1, L_0x2cd3920, L_0x2cd3a80, C4<1>, C4<1>; +L_0x2cd3b60 .delay (20000,20000,20000) L_0x2cd3b60/d; +L_0x2cd3c90/d .functor AND 1, L_0x2cd3490, L_0x2cd3f60, C4<1>, C4<1>; +L_0x2cd3c90 .delay (20000,20000,20000) L_0x2cd3c90/d; +L_0x2cd3de0/d .functor OR 1, L_0x2cd3b60, L_0x2cd3c90, C4<0>, C4<0>; +L_0x2cd3de0 .delay (20000,20000,20000) L_0x2cd3de0/d; +v0x29dc070_0 .net "S", 0 0, L_0x2cd3f60; 1 drivers +v0x29da440_0 .alias "in0", 0 0, v0x29e1b70_0; +v0x29da4e0_0 .alias "in1", 0 0, v0x29d9ce0_0; +v0x29da190_0 .net "nS", 0 0, L_0x2cd3a80; 1 drivers +v0x29da230_0 .net "out0", 0 0, L_0x2cd3b60; 1 drivers +v0x29dd750_0 .net "out1", 0 0, L_0x2cd3c90; 1 drivers +v0x29d9ee0_0 .alias "outfinal", 0 0, v0x2986f40_0; +S_0x29d40c0 .scope module, "mux1" "TwoInMux" 3 84, 3 8, S_0x29d7930; + .timescale -9 -12; +L_0x2cc7450/d .functor NOT 1, L_0x2cd43f0, C4<0>, C4<0>, C4<0>; +L_0x2cc7450 .delay (10000,10000,10000) L_0x2cc7450/d; +L_0x2cd4000/d .functor AND 1, L_0x2cd3de0, L_0x2cc7450, C4<1>, C4<1>; +L_0x2cd4000 .delay (20000,20000,20000) L_0x2cd4000/d; +L_0x2cd4130/d .functor AND 1, L_0x2cd3580, L_0x2cd43f0, C4<1>, C4<1>; +L_0x2cd4130 .delay (20000,20000,20000) L_0x2cd4130/d; +L_0x2cd4260/d .functor OR 1, L_0x2cd4000, L_0x2cd4130, C4<0>, C4<0>; +L_0x2cd4260 .delay (20000,20000,20000) L_0x2cd4260/d; +v0x29d46a0_0 .net "S", 0 0, L_0x2cd43f0; 1 drivers +v0x29d3e20_0 .alias "in0", 0 0, v0x2986f40_0; +v0x29d3ec0_0 .alias "in1", 0 0, v0x29e1af0_0; +v0x29dc530_0 .net "nS", 0 0, L_0x2cc7450; 1 drivers +v0x29dc5b0_0 .net "out0", 0 0, L_0x2cd4000; 1 drivers +v0x29dc280_0 .net "out1", 0 0, L_0x2cd4130; 1 drivers +v0x29dbfd0_0 .alias "outfinal", 0 0, v0x266a600_0; +S_0x29bc7a0 .scope generate, "orbits[16]" "orbits[16]" 3 196, 3 196, S_0x29fb160; + .timescale -9 -12; +P_0x29be678 .param/l "i" 3 196, +C4<010000>; +S_0x29bc500 .scope module, "attempt" "OrNorXor" 3 198, 3 64, S_0x29bc7a0; + .timescale -9 -12; +L_0x2cd33d0/d .functor NOR 1, L_0x2cd45d0, L_0x2cd4670, C4<0>, C4<0>; +L_0x2cd33d0 .delay (10000,10000,10000) L_0x2cd33d0/d; +L_0x2cd4790/d .functor NOT 1, L_0x2cd33d0, C4<0>, C4<0>, C4<0>; +L_0x2cd4790 .delay (10000,10000,10000) L_0x2cd4790/d; +L_0x2cd4880/d .functor NAND 1, L_0x2cd45d0, L_0x2cd4670, C4<1>, C4<1>; +L_0x2cd4880 .delay (10000,10000,10000) L_0x2cd4880/d; +L_0x2cd49c0/d .functor NAND 1, L_0x2cd4880, L_0x2cd4790, C4<1>, C4<1>; +L_0x2cd49c0 .delay (10000,10000,10000) L_0x2cd49c0/d; +L_0x2cd4ab0/d .functor NOT 1, L_0x2cd49c0, C4<0>, C4<0>, C4<0>; +L_0x2cd4ab0 .delay (10000,10000,10000) L_0x2cd4ab0/d; +v0x29ce030_0 .net "A", 0 0, L_0x2cd45d0; 1 drivers +v0x29d6710_0 .net "AnandB", 0 0, L_0x2cd4880; 1 drivers +v0x29d67b0_0 .net "AnorB", 0 0, L_0x2cd33d0; 1 drivers +v0x29d6460_0 .net "AorB", 0 0, L_0x2cd4790; 1 drivers +v0x29d64e0_0 .net "AxorB", 0 0, L_0x2cd4ab0; 1 drivers +v0x29d61b0_0 .net "B", 0 0, L_0x2cd4670; 1 drivers +v0x29d6270_0 .alias "Command", 2 0, v0x2bc67a0_0; +v0x29d5f10_0 .net "OrNorXorOut", 0 0, L_0x2cd5390; 1 drivers +v0x29d5f90_0 .net "XorNor", 0 0, L_0x2cd4eb0; 1 drivers +v0x29d4620_0 .net "nXor", 0 0, L_0x2cd49c0; 1 drivers +L_0x2cd4ff0 .part v0x2bc78e0_0, 2, 1; +L_0x2cd5520 .part v0x2bc78e0_0, 0, 1; +S_0x29d0640 .scope module, "mux0" "TwoInMux" 3 83, 3 8, S_0x29bc500; + .timescale -9 -12; +L_0x2cd4bf0/d .functor NOT 1, L_0x2cd4ff0, C4<0>, C4<0>, C4<0>; +L_0x2cd4bf0 .delay (10000,10000,10000) L_0x2cd4bf0/d; +L_0x2cd4c90/d .functor AND 1, L_0x2cd4ab0, L_0x2cd4bf0, C4<1>, C4<1>; +L_0x2cd4c90 .delay (20000,20000,20000) L_0x2cd4c90/d; +L_0x2cd4d80/d .functor AND 1, L_0x2cd33d0, L_0x2cd4ff0, C4<1>, C4<1>; +L_0x2cd4d80 .delay (20000,20000,20000) L_0x2cd4d80/d; +L_0x2cd4eb0/d .functor OR 1, L_0x2cd4c90, L_0x2cd4d80, C4<0>, C4<0>; +L_0x2cd4eb0 .delay (20000,20000,20000) L_0x2cd4eb0/d; +v0x29d0990_0 .net "S", 0 0, L_0x2cd4ff0; 1 drivers +v0x29d0390_0 .alias "in0", 0 0, v0x29d64e0_0; +v0x29d0430_0 .alias "in1", 0 0, v0x29d67b0_0; +v0x29d00f0_0 .net "nS", 0 0, L_0x2cd4bf0; 1 drivers +v0x29d0190_0 .net "out0", 0 0, L_0x2cd4c90; 1 drivers +v0x29d1b10_0 .net "out1", 0 0, L_0x2cd4d80; 1 drivers +v0x29cdfb0_0 .alias "outfinal", 0 0, v0x29d5f90_0; +S_0x29c43e0 .scope module, "mux1" "TwoInMux" 3 84, 3 8, S_0x29bc500; + .timescale -9 -12; +L_0x2cd5090/d .functor NOT 1, L_0x2cd5520, C4<0>, C4<0>, C4<0>; +L_0x2cd5090 .delay (10000,10000,10000) L_0x2cd5090/d; +L_0x2cd5130/d .functor AND 1, L_0x2cd4eb0, L_0x2cd5090, C4<1>, C4<1>; +L_0x2cd5130 .delay (20000,20000,20000) L_0x2cd5130/d; +L_0x2cd5260/d .functor AND 1, L_0x2cd4790, L_0x2cd5520, C4<1>, C4<1>; +L_0x2cd5260 .delay (20000,20000,20000) L_0x2cd5260/d; +L_0x2cd5390/d .functor OR 1, L_0x2cd5130, L_0x2cd5260, C4<0>, C4<0>; +L_0x2cd5390 .delay (20000,20000,20000) L_0x2cd5390/d; +v0x29bcad0_0 .net "S", 0 0, L_0x2cd5520; 1 drivers +v0x29c22f0_0 .alias "in0", 0 0, v0x29d5f90_0; +v0x29c2390_0 .alias "in1", 0 0, v0x29d6460_0; +v0x29ca240_0 .net "nS", 0 0, L_0x2cd5090; 1 drivers +v0x29ca2c0_0 .net "out0", 0 0, L_0x2cd5130; 1 drivers +v0x29c8150_0 .net "out1", 0 0, L_0x2cd5260; 1 drivers +v0x29d08f0_0 .alias "outfinal", 0 0, v0x29d5f10_0; +S_0x29b0b60 .scope generate, "orbits[17]" "orbits[17]" 3 196, 3 196, S_0x29fb160; + .timescale -9 -12; +P_0x29b1148 .param/l "i" 3 196, +C4<010001>; +S_0x29b08c0 .scope module, "attempt" "OrNorXor" 3 198, 3 64, S_0x29b0b60; + .timescale -9 -12; +L_0x2cd57f0/d .functor NOR 1, L_0x2cd6870, L_0x2cd5660, C4<0>, C4<0>; +L_0x2cd57f0 .delay (10000,10000,10000) L_0x2cd57f0/d; +L_0x2cd58e0/d .functor NOT 1, L_0x2cd57f0, C4<0>, C4<0>, C4<0>; +L_0x2cd58e0 .delay (10000,10000,10000) L_0x2cd58e0/d; +L_0x2cd59d0/d .functor NAND 1, L_0x2cd6870, L_0x2cd5660, C4<1>, C4<1>; +L_0x2cd59d0 .delay (10000,10000,10000) L_0x2cd59d0/d; +L_0x2cd5b10/d .functor NAND 1, L_0x2cd59d0, L_0x2cd58e0, C4<1>, C4<1>; +L_0x2cd5b10 .delay (10000,10000,10000) L_0x2cd5b10/d; +L_0x2cd5c00/d .functor NOT 1, L_0x2cd5b10, C4<0>, C4<0>, C4<0>; +L_0x2cd5c00 .delay (10000,10000,10000) L_0x2cd5c00/d; +v0x29bee70_0 .net "A", 0 0, L_0x2cd6870; 1 drivers +v0x29beb40_0 .net "AnandB", 0 0, L_0x2cd59d0; 1 drivers +v0x29bebe0_0 .net "AnorB", 0 0, L_0x2cd57f0; 1 drivers +v0x29be890_0 .net "AorB", 0 0, L_0x2cd58e0; 1 drivers +v0x29be910_0 .net "AxorB", 0 0, L_0x2cd5c00; 1 drivers +v0x29be5f0_0 .net "B", 0 0, L_0x2cd5660; 1 drivers +v0x29be6b0_0 .alias "Command", 2 0, v0x2bc67a0_0; +v0x29bcd00_0 .net "OrNorXorOut", 0 0, L_0x2cd6560; 1 drivers +v0x29bcd80_0 .net "XorNor", 0 0, L_0x2cd6000; 1 drivers +v0x29bca50_0 .net "nXor", 0 0, L_0x2cd5b10; 1 drivers +L_0x2cd6140 .part v0x2bc78e0_0, 2, 1; +L_0x2cd6730 .part v0x2bc78e0_0, 0, 1; +S_0x29b6c30 .scope module, "mux0" "TwoInMux" 3 83, 3 8, S_0x29b08c0; + .timescale -9 -12; +L_0x2cd5d40/d .functor NOT 1, L_0x2cd6140, C4<0>, C4<0>, C4<0>; +L_0x2cd5d40 .delay (10000,10000,10000) L_0x2cd5d40/d; +L_0x2cd5de0/d .functor AND 1, L_0x2cd5c00, L_0x2cd5d40, C4<1>, C4<1>; +L_0x2cd5de0 .delay (20000,20000,20000) L_0x2cd5de0/d; +L_0x2cd5ed0/d .functor AND 1, L_0x2cd57f0, L_0x2cd6140, C4<1>, C4<1>; +L_0x2cd5ed0 .delay (20000,20000,20000) L_0x2cd5ed0/d; +L_0x2cd6000/d .functor OR 1, L_0x2cd5de0, L_0x2cd5ed0, C4<0>, C4<0>; +L_0x2cd6000 .delay (20000,20000,20000) L_0x2cd6000/d; +v0x29b6f80_0 .net "S", 0 0, L_0x2cd6140; 1 drivers +v0x29ba1f0_0 .alias "in0", 0 0, v0x29be910_0; +v0x29ba290_0 .alias "in1", 0 0, v0x29bebe0_0; +v0x29b6980_0 .net "nS", 0 0, L_0x2cd5d40; 1 drivers +v0x29b6a20_0 .net "out0", 0 0, L_0x2cd5de0; 1 drivers +v0x29b66e0_0 .net "out1", 0 0, L_0x2cd5ed0; 1 drivers +v0x29bedf0_0 .alias "outfinal", 0 0, v0x29bcd80_0; +S_0x29b8fd0 .scope module, "mux1" "TwoInMux" 3 84, 3 8, S_0x29b08c0; + .timescale -9 -12; +L_0x2cd6200/d .functor NOT 1, L_0x2cd6730, C4<0>, C4<0>, C4<0>; +L_0x2cd6200 .delay (10000,10000,10000) L_0x2cd6200/d; +L_0x2cd62c0/d .functor AND 1, L_0x2cd6000, L_0x2cd6200, C4<1>, C4<1>; +L_0x2cd62c0 .delay (20000,20000,20000) L_0x2cd62c0/d; +L_0x2cd6410/d .functor AND 1, L_0x2cd58e0, L_0x2cd6730, C4<1>, C4<1>; +L_0x2cd6410 .delay (20000,20000,20000) L_0x2cd6410/d; +L_0x2cd6560/d .functor OR 1, L_0x2cd62c0, L_0x2cd6410, C4<0>, C4<0>; +L_0x2cd6560 .delay (20000,20000,20000) L_0x2cd6560/d; +v0x29b4450_0 .net "S", 0 0, L_0x2cd6730; 1 drivers +v0x29b8d20_0 .alias "in0", 0 0, v0x29bcd80_0; +v0x29b8dc0_0 .alias "in1", 0 0, v0x29be890_0; +v0x29b8a70_0 .net "nS", 0 0, L_0x2cd6200; 1 drivers +v0x29b8af0_0 .net "out0", 0 0, L_0x2cd62c0; 1 drivers +v0x29b87d0_0 .net "out1", 0 0, L_0x2cd6410; 1 drivers +v0x29b6ee0_0 .alias "outfinal", 0 0, v0x29bcd00_0; +S_0x2999780 .scope generate, "orbits[18]" "orbits[18]" 3 196, 3 196, S_0x29fb160; + .timescale -9 -12; +P_0x299b648 .param/l "i" 3 196, +C4<010010>; +S_0x29994d0 .scope module, "attempt" "OrNorXor" 3 198, 3 64, S_0x2999780; + .timescale -9 -12; +L_0x2cd5700/d .functor NOR 1, L_0x2cd6910, L_0x2cd69b0, C4<0>, C4<0>; +L_0x2cd5700 .delay (10000,10000,10000) L_0x2cd5700/d; +L_0x2cd6ab0/d .functor NOT 1, L_0x2cd5700, C4<0>, C4<0>, C4<0>; +L_0x2cd6ab0 .delay (10000,10000,10000) L_0x2cd6ab0/d; +L_0x2cd6be0/d .functor NAND 1, L_0x2cd6910, L_0x2cd69b0, C4<1>, C4<1>; +L_0x2cd6be0 .delay (10000,10000,10000) L_0x2cd6be0/d; +L_0x2cd6d40/d .functor NAND 1, L_0x2cd6be0, L_0x2cd6ab0, C4<1>, C4<1>; +L_0x2cd6d40 .delay (10000,10000,10000) L_0x2cd6d40/d; +L_0x2cd6e50/d .functor NOT 1, L_0x2cd6d40, C4<0>, C4<0>, C4<0>; +L_0x2cd6e50 .delay (10000,10000,10000) L_0x2cd6e50/d; +v0x29b2f80_0 .net "A", 0 0, L_0x2cd6910; 1 drivers +v0x29b2c50_0 .net "AnandB", 0 0, L_0x2cd6be0; 1 drivers +v0x29b2cf0_0 .net "AnorB", 0 0, L_0x2cd5700; 1 drivers +v0x29b29b0_0 .net "AorB", 0 0, L_0x2cd6ab0; 1 drivers +v0x29b2a30_0 .net "AxorB", 0 0, L_0x2cd6e50; 1 drivers +v0x29b10c0_0 .net "B", 0 0, L_0x2cd69b0; 1 drivers +v0x29b1180_0 .alias "Command", 2 0, v0x2bc67a0_0; +v0x29b0e10_0 .net "OrNorXorOut", 0 0, L_0x2cd7890; 1 drivers +v0x29b0e90_0 .net "XorNor", 0 0, L_0x2cd7310; 1 drivers +v0x29b43d0_0 .net "nXor", 0 0, L_0x2cd6d40; 1 drivers +L_0x2cd7490 .part v0x2bc78e0_0, 2, 1; +L_0x2cd7a60 .part v0x2bc78e0_0, 0, 1; +S_0x29a4ba0 .scope module, "mux0" "TwoInMux" 3 83, 3 8, S_0x29994d0; + .timescale -9 -12; +L_0x2cd6fb0/d .functor NOT 1, L_0x2cd7490, C4<0>, C4<0>, C4<0>; +L_0x2cd6fb0 .delay (10000,10000,10000) L_0x2cd6fb0/d; +L_0x2cd7090/d .functor AND 1, L_0x2cd6e50, L_0x2cd6fb0, C4<1>, C4<1>; +L_0x2cd7090 .delay (20000,20000,20000) L_0x2cd7090/d; +L_0x2cd71c0/d .functor AND 1, L_0x2cd5700, L_0x2cd7490, C4<1>, C4<1>; +L_0x2cd71c0 .delay (20000,20000,20000) L_0x2cd71c0/d; +L_0x2cd7310/d .functor OR 1, L_0x2cd7090, L_0x2cd71c0, C4<0>, C4<0>; +L_0x2cd7310 .delay (20000,20000,20000) L_0x2cd7310/d; +v0x29a6d30_0 .net "S", 0 0, L_0x2cd7490; 1 drivers +v0x29acaf0_0 .alias "in0", 0 0, v0x29b2a30_0; +v0x29acb90_0 .alias "in1", 0 0, v0x29b2cf0_0; +v0x29aaa00_0 .net "nS", 0 0, L_0x2cd6fb0; 1 drivers +v0x29aaaa0_0 .net "out0", 0 0, L_0x2cd7090; 1 drivers +v0x29b31b0_0 .net "out1", 0 0, L_0x2cd71c0; 1 drivers +v0x29b2f00_0 .alias "outfinal", 0 0, v0x29b0e90_0; +S_0x299ca90 .scope module, "mux1" "TwoInMux" 3 84, 3 8, S_0x29994d0; + .timescale -9 -12; +L_0x2cd7530/d .functor NOT 1, L_0x2cd7a60, C4<0>, C4<0>, C4<0>; +L_0x2cd7530 .delay (10000,10000,10000) L_0x2cd7530/d; +L_0x2cd75f0/d .functor AND 1, L_0x2cd7310, L_0x2cd7530, C4<1>, C4<1>; +L_0x2cd75f0 .delay (20000,20000,20000) L_0x2cd75f0/d; +L_0x2cd7740/d .functor AND 1, L_0x2cd6ab0, L_0x2cd7a60, C4<1>, C4<1>; +L_0x2cd7740 .delay (20000,20000,20000) L_0x2cd7740/d; +L_0x2cd7890/d .functor OR 1, L_0x2cd75f0, L_0x2cd7740, C4<0>, C4<0>; +L_0x2cd7890 .delay (20000,20000,20000) L_0x2cd7890/d; +v0x299b0f0_0 .net "S", 0 0, L_0x2cd7a60; 1 drivers +v0x2999220_0 .alias "in0", 0 0, v0x29b0e90_0; +v0x29992c0_0 .alias "in1", 0 0, v0x29b29b0_0; +v0x2998f80_0 .net "nS", 0 0, L_0x2cd7530; 1 drivers +v0x2999000_0 .net "out0", 0 0, L_0x2cd75f0; 1 drivers +v0x29a0e30_0 .net "out1", 0 0, L_0x2cd7740; 1 drivers +v0x29a6c90_0 .alias "outfinal", 0 0, v0x29b0e10_0; +S_0x298f6d0 .scope generate, "orbits[19]" "orbits[19]" 3 196, 3 196, S_0x29fb160; + .timescale -9 -12; +P_0x2987508 .param/l "i" 3 196, +C4<010011>; +S_0x298f430 .scope module, "attempt" "OrNorXor" 3 198, 3 64, S_0x298f6d0; + .timescale -9 -12; +L_0x2cd6a50/d .functor NOR 1, L_0x2cd8ee0, L_0x2cd7ba0, C4<0>, C4<0>; +L_0x2cd6a50 .delay (10000,10000,10000) L_0x2cd6a50/d; +L_0x2cd7df0/d .functor NOT 1, L_0x2cd6a50, C4<0>, C4<0>, C4<0>; +L_0x2cd7df0 .delay (10000,10000,10000) L_0x2cd7df0/d; +L_0x2cd7f20/d .functor NAND 1, L_0x2cd8ee0, L_0x2cd7ba0, C4<1>, C4<1>; +L_0x2cd7f20 .delay (10000,10000,10000) L_0x2cd7f20/d; +L_0x2cd8080/d .functor NAND 1, L_0x2cd7f20, L_0x2cd7df0, C4<1>, C4<1>; +L_0x2cd8080 .delay (10000,10000,10000) L_0x2cd8080/d; +L_0x2cd8190/d .functor NOT 1, L_0x2cd8080, C4<0>, C4<0>, C4<0>; +L_0x2cd8190 .delay (10000,10000,10000) L_0x2cd8190/d; +v0x2993480_0 .net "A", 0 0, L_0x2cd8ee0; 1 drivers +v0x2993160_0 .net "AnandB", 0 0, L_0x2cd7f20; 1 drivers +v0x2993200_0 .net "AnorB", 0 0, L_0x2cd6a50; 1 drivers +v0x299b870_0 .net "AorB", 0 0, L_0x2cd7df0; 1 drivers +v0x299b8f0_0 .net "AxorB", 0 0, L_0x2cd8190; 1 drivers +v0x299b5c0_0 .net "B", 0 0, L_0x2cd7ba0; 1 drivers +v0x299b680_0 .alias "Command", 2 0, v0x2bc67a0_0; +v0x299b310_0 .net "OrNorXorOut", 0 0, L_0x2cd8bd0; 1 drivers +v0x299b390_0 .net "XorNor", 0 0, L_0x2cd8650; 1 drivers +v0x299b070_0 .net "nXor", 0 0, L_0x2cd8080; 1 drivers +L_0x2cd87d0 .part v0x2bc78e0_0, 2, 1; +L_0x2cd8da0 .part v0x2bc78e0_0, 0, 1; +S_0x2995250 .scope module, "mux0" "TwoInMux" 3 83, 3 8, S_0x298f430; + .timescale -9 -12; +L_0x2cd82f0/d .functor NOT 1, L_0x2cd87d0, C4<0>, C4<0>, C4<0>; +L_0x2cd82f0 .delay (10000,10000,10000) L_0x2cd82f0/d; +L_0x2cd83d0/d .functor AND 1, L_0x2cd8190, L_0x2cd82f0, C4<1>, C4<1>; +L_0x2cd83d0 .delay (20000,20000,20000) L_0x2cd83d0/d; +L_0x2cd8500/d .functor AND 1, L_0x2cd6a50, L_0x2cd87d0, C4<1>, C4<1>; +L_0x2cd8500 .delay (20000,20000,20000) L_0x2cd8500/d; +L_0x2cd8650/d .functor OR 1, L_0x2cd83d0, L_0x2cd8500, C4<0>, C4<0>; +L_0x2cd8650 .delay (20000,20000,20000) L_0x2cd8650/d; +v0x2995590_0 .net "S", 0 0, L_0x2cd87d0; 1 drivers +v0x2993960_0 .alias "in0", 0 0, v0x299b8f0_0; +v0x2993a00_0 .alias "in1", 0 0, v0x2993200_0; +v0x29936b0_0 .net "nS", 0 0, L_0x2cd82f0; 1 drivers +v0x2993750_0 .net "out0", 0 0, L_0x2cd83d0; 1 drivers +v0x2996c70_0 .net "out1", 0 0, L_0x2cd8500; 1 drivers +v0x2993400_0 .alias "outfinal", 0 0, v0x299b390_0; +S_0x2990e50 .scope module, "mux1" "TwoInMux" 3 84, 3 8, S_0x298f430; + .timescale -9 -12; +L_0x2cd8870/d .functor NOT 1, L_0x2cd8da0, C4<0>, C4<0>, C4<0>; +L_0x2cd8870 .delay (10000,10000,10000) L_0x2cd8870/d; +L_0x2cd8930/d .functor AND 1, L_0x2cd8650, L_0x2cd8870, C4<1>, C4<1>; +L_0x2cd8930 .delay (20000,20000,20000) L_0x2cd8930/d; +L_0x2cd8a80/d .functor AND 1, L_0x2cd7df0, L_0x2cd8da0, C4<1>, C4<1>; +L_0x2cd8a80 .delay (20000,20000,20000) L_0x2cd8a80/d; +L_0x2cd8bd0/d .functor OR 1, L_0x2cd8930, L_0x2cd8a80, C4<0>, C4<0>; +L_0x2cd8bd0 .delay (20000,20000,20000) L_0x2cd8bd0/d; +v0x298fa00_0 .net "S", 0 0, L_0x2cd8da0; 1 drivers +v0x298d2e0_0 .alias "in0", 0 0, v0x299b390_0; +v0x298d380_0 .alias "in1", 0 0, v0x299b870_0; +v0x2995a50_0 .net "nS", 0 0, L_0x2cd8870; 1 drivers +v0x2995ad0_0 .net "out0", 0 0, L_0x2cd8930; 1 drivers +v0x29957a0_0 .net "out1", 0 0, L_0x2cd8a80; 1 drivers +v0x29954f0_0 .alias "outfinal", 0 0, v0x299b310_0; +S_0x2979800 .scope generate, "orbits[20]" "orbits[20]" 3 196, 3 196, S_0x29fb160; + .timescale -9 -12; +P_0x2977f48 .param/l "i" 3 196, +C4<010100>; +S_0x2976150 .scope module, "attempt" "OrNorXor" 3 198, 3 64, S_0x2979800; + .timescale -9 -12; +L_0x2cd7c40/d .functor NOR 1, L_0x2cd8f80, L_0x2cd9020, C4<0>, C4<0>; +L_0x2cd7c40 .delay (10000,10000,10000) L_0x2cd7c40/d; +L_0x2cd9150/d .functor NOT 1, L_0x2cd7c40, C4<0>, C4<0>, C4<0>; +L_0x2cd9150 .delay (10000,10000,10000) L_0x2cd9150/d; +L_0x2cd9260/d .functor NAND 1, L_0x2cd8f80, L_0x2cd9020, C4<1>, C4<1>; +L_0x2cd9260 .delay (10000,10000,10000) L_0x2cd9260/d; +L_0x2cd93c0/d .functor NAND 1, L_0x2cd9260, L_0x2cd9150, C4<1>, C4<1>; +L_0x2cd93c0 .delay (10000,10000,10000) L_0x2cd93c0/d; +L_0x2cd94d0/d .functor NOT 1, L_0x2cd93c0, C4<0>, C4<0>, C4<0>; +L_0x2cd94d0 .delay (10000,10000,10000) L_0x2cd94d0/d; +v0x2983790_0 .net "A", 0 0, L_0x2cd8f80; 1 drivers +v0x2981620_0 .net "AnandB", 0 0, L_0x2cd9260; 1 drivers +v0x29816c0_0 .net "AnorB", 0 0, L_0x2cd7c40; 1 drivers +v0x2989570_0 .net "AorB", 0 0, L_0x2cd9150; 1 drivers +v0x29895f0_0 .net "AxorB", 0 0, L_0x2cd94d0; 1 drivers +v0x2987480_0 .net "B", 0 0, L_0x2cd9020; 1 drivers +v0x2987540_0 .alias "Command", 2 0, v0x2bc67a0_0; +v0x298fc30_0 .net "OrNorXorOut", 0 0, L_0x2cd9f10; 1 drivers +v0x298fcb0_0 .net "XorNor", 0 0, L_0x2cd9990; 1 drivers +v0x298f980_0 .net "nXor", 0 0, L_0x2cd93c0; 1 drivers +L_0x2cd9b10 .part v0x2bc78e0_0, 2, 1; +L_0x2cda0e0 .part v0x2bc78e0_0, 0, 1; +S_0x297c1d0 .scope module, "mux0" "TwoInMux" 3 83, 3 8, S_0x2976150; + .timescale -9 -12; +L_0x2cd9630/d .functor NOT 1, L_0x2cd9b10, C4<0>, C4<0>, C4<0>; +L_0x2cd9630 .delay (10000,10000,10000) L_0x2cd9630/d; +L_0x2cd9710/d .functor AND 1, L_0x2cd94d0, L_0x2cd9630, C4<1>, C4<1>; +L_0x2cd9710 .delay (20000,20000,20000) L_0x2cd9710/d; +L_0x2cd9840/d .functor AND 1, L_0x2cd7c40, L_0x2cd9b10, C4<1>, C4<1>; +L_0x2cd9840 .delay (20000,20000,20000) L_0x2cd9840/d; +L_0x2cd9990/d .functor OR 1, L_0x2cd9710, L_0x2cd9840, C4<0>, C4<0>; +L_0x2cd9990 .delay (20000,20000,20000) L_0x2cd9990/d; +v0x297dac0_0 .net "S", 0 0, L_0x2cd9b10; 1 drivers +v0x297bf40_0 .alias "in0", 0 0, v0x29895f0_0; +v0x297bfe0_0 .alias "in1", 0 0, v0x29816c0_0; +v0x297bcb0_0 .net "nS", 0 0, L_0x2cd9630; 1 drivers +v0x297bd50_0 .net "out0", 0 0, L_0x2cd9710; 1 drivers +v0x297ba30_0 .net "out1", 0 0, L_0x2cd9840; 1 drivers +v0x2983710_0 .alias "outfinal", 0 0, v0x298fcb0_0; +S_0x2975ed0 .scope module, "mux1" "TwoInMux" 3 84, 3 8, S_0x2976150; + .timescale -9 -12; +L_0x2cd9bb0/d .functor NOT 1, L_0x2cda0e0, C4<0>, C4<0>, C4<0>; +L_0x2cd9bb0 .delay (10000,10000,10000) L_0x2cd9bb0/d; +L_0x2cd9c70/d .functor AND 1, L_0x2cd9990, L_0x2cd9bb0, C4<1>, C4<1>; +L_0x2cd9c70 .delay (20000,20000,20000) L_0x2cd9c70/d; +L_0x2cd9dc0/d .functor AND 1, L_0x2cd9150, L_0x2cda0e0, C4<1>, C4<1>; +L_0x2cd9dc0 .delay (20000,20000,20000) L_0x2cd9dc0/d; +L_0x2cd9f10/d .functor OR 1, L_0x2cd9c70, L_0x2cd9dc0, C4<0>, C4<0>; +L_0x2cd9f10 .delay (20000,20000,20000) L_0x2cd9f10/d; +v0x2976460_0 .net "S", 0 0, L_0x2cda0e0; 1 drivers +v0x297e1c0_0 .alias "in0", 0 0, v0x298fcb0_0; +v0x297e260_0 .alias "in1", 0 0, v0x2989570_0; +v0x297df30_0 .net "nS", 0 0, L_0x2cd9bb0; 1 drivers +v0x297dfb0_0 .net "out0", 0 0, L_0x2cd9c70; 1 drivers +v0x297dca0_0 .net "out1", 0 0, L_0x2cd9dc0; 1 drivers +v0x297da20_0 .alias "outfinal", 0 0, v0x298fc30_0; +S_0x2a1c260 .scope generate, "orbits[21]" "orbits[21]" 3 196, 3 196, S_0x29fb160; + .timescale -9 -12; +P_0x2a54d58 .param/l "i" 3 196, +C4<010101>; +S_0x2a79160 .scope module, "attempt" "OrNorXor" 3 198, 3 64, S_0x2a1c260; + .timescale -9 -12; +L_0x2cd90c0/d .functor NOR 1, L_0x2cdb570, L_0x2cda220, C4<0>, C4<0>; +L_0x2cd90c0 .delay (10000,10000,10000) L_0x2cd90c0/d; +L_0x2cda4a0/d .functor NOT 1, L_0x2cd90c0, C4<0>, C4<0>, C4<0>; +L_0x2cda4a0 .delay (10000,10000,10000) L_0x2cda4a0/d; +L_0x2cda5b0/d .functor NAND 1, L_0x2cdb570, L_0x2cda220, C4<1>, C4<1>; +L_0x2cda5b0 .delay (10000,10000,10000) L_0x2cda5b0/d; +L_0x2cda710/d .functor NAND 1, L_0x2cda5b0, L_0x2cda4a0, C4<1>, C4<1>; +L_0x2cda710 .delay (10000,10000,10000) L_0x2cda710/d; +L_0x2cda820/d .functor NOT 1, L_0x2cda710, C4<0>, C4<0>, C4<0>; +L_0x2cda820 .delay (10000,10000,10000) L_0x2cda820/d; +v0x29786e0_0 .net "A", 0 0, L_0x2cdb570; 1 drivers +v0x29783d0_0 .net "AnandB", 0 0, L_0x2cda5b0; 1 drivers +v0x2978470_0 .net "AnorB", 0 0, L_0x2cd90c0; 1 drivers +v0x2978140_0 .net "AorB", 0 0, L_0x2cda4a0; 1 drivers +v0x29781c0_0 .net "AxorB", 0 0, L_0x2cda820; 1 drivers +v0x2977ec0_0 .net "B", 0 0, L_0x2cda220; 1 drivers +v0x2977f80_0 .alias "Command", 2 0, v0x2bc67a0_0; +v0x2976670_0 .net "OrNorXorOut", 0 0, L_0x2cdb260; 1 drivers +v0x29766f0_0 .net "XorNor", 0 0, L_0x2cdace0; 1 drivers +v0x29763e0_0 .net "nXor", 0 0, L_0x2cda710; 1 drivers +L_0x2cdae60 .part v0x2bc78e0_0, 2, 1; +L_0x2cdb430 .part v0x2bc78e0_0, 0, 1; +S_0x2970880 .scope module, "mux0" "TwoInMux" 3 83, 3 8, S_0x2a79160; + .timescale -9 -12; +L_0x2cda980/d .functor NOT 1, L_0x2cdae60, C4<0>, C4<0>, C4<0>; +L_0x2cda980 .delay (10000,10000,10000) L_0x2cda980/d; +L_0x2cdaa60/d .functor AND 1, L_0x2cda820, L_0x2cda980, C4<1>, C4<1>; +L_0x2cdaa60 .delay (20000,20000,20000) L_0x2cdaa60/d; +L_0x2cdab90/d .functor AND 1, L_0x2cd90c0, L_0x2cdae60, C4<1>, C4<1>; +L_0x2cdab90 .delay (20000,20000,20000) L_0x2cdab90/d; +L_0x2cdace0/d .functor OR 1, L_0x2cdaa60, L_0x2cdab90, C4<0>, C4<0>; +L_0x2cdace0 .delay (20000,20000,20000) L_0x2cdace0/d; +v0x2970bb0_0 .net "S", 0 0, L_0x2cdae60; 1 drivers +v0x2973ca0_0 .alias "in0", 0 0, v0x29781c0_0; +v0x2973d40_0 .alias "in1", 0 0, v0x2978470_0; +v0x29705f0_0 .net "nS", 0 0, L_0x2cda980; 1 drivers +v0x2970690_0 .net "out0", 0 0, L_0x2cdaa60; 1 drivers +v0x2970370_0 .net "out1", 0 0, L_0x2cdab90; 1 drivers +v0x2978660_0 .alias "outfinal", 0 0, v0x29766f0_0; +S_0x2972b00 .scope module, "mux1" "TwoInMux" 3 84, 3 8, S_0x2a79160; + .timescale -9 -12; +L_0x2cdaf00/d .functor NOT 1, L_0x2cdb430, C4<0>, C4<0>, C4<0>; +L_0x2cdaf00 .delay (10000,10000,10000) L_0x2cdaf00/d; +L_0x2cdafc0/d .functor AND 1, L_0x2cdace0, L_0x2cdaf00, C4<1>, C4<1>; +L_0x2cdafc0 .delay (20000,20000,20000) L_0x2cdafc0/d; +L_0x2cdb110/d .functor AND 1, L_0x2cda4a0, L_0x2cdb430, C4<1>, C4<1>; +L_0x2cdb110 .delay (20000,20000,20000) L_0x2cdb110/d; +L_0x2cdb260/d .functor OR 1, L_0x2cdafc0, L_0x2cdb110, C4<0>, C4<0>; +L_0x2cdb260 .delay (20000,20000,20000) L_0x2cdb260/d; +v0x2a3def0_0 .net "S", 0 0, L_0x2cdb430; 1 drivers +v0x2972870_0 .alias "in0", 0 0, v0x29766f0_0; +v0x2972910_0 .alias "in1", 0 0, v0x2978140_0; +v0x29725e0_0 .net "nS", 0 0, L_0x2cdaf00; 1 drivers +v0x2972660_0 .net "out0", 0 0, L_0x2cdafc0; 1 drivers +v0x2972360_0 .net "out1", 0 0, L_0x2cdb110; 1 drivers +v0x2970b10_0 .alias "outfinal", 0 0, v0x2976670_0; +S_0x29810e0 .scope generate, "orbits[22]" "orbits[22]" 3 196, 3 196, S_0x29fb160; + .timescale -9 -12; +P_0x2989098 .param/l "i" 3 196, +C4<010110>; +S_0x29643b0 .scope module, "attempt" "OrNorXor" 3 198, 3 64, S_0x29810e0; + .timescale -9 -12; +L_0x2cda2c0/d .functor NOR 1, L_0x2cdb610, L_0x2cdb6b0, C4<0>, C4<0>; +L_0x2cda2c0 .delay (10000,10000,10000) L_0x2cda2c0/d; +L_0x2cdb810/d .functor NOT 1, L_0x2cda2c0, C4<0>, C4<0>, C4<0>; +L_0x2cdb810 .delay (10000,10000,10000) L_0x2cdb810/d; +L_0x2cdb900/d .functor NAND 1, L_0x2cdb610, L_0x2cdb6b0, C4<1>, C4<1>; +L_0x2cdb900 .delay (10000,10000,10000) L_0x2cdb900/d; +L_0x2cdba60/d .functor NAND 1, L_0x2cdb900, L_0x2cdb810, C4<1>, C4<1>; +L_0x2cdba60 .delay (10000,10000,10000) L_0x2cdba60/d; +L_0x2cdbb70/d .functor NOT 1, L_0x2cdba60, C4<0>, C4<0>, C4<0>; +L_0x2cdbb70 .delay (10000,10000,10000) L_0x2cdbb70/d; +v0x2a5d810_0 .net "A", 0 0, L_0x2cdb610; 1 drivers +v0x2a5a950_0 .net "AnandB", 0 0, L_0x2cdb900; 1 drivers +v0x2a5a9f0_0 .net "AnorB", 0 0, L_0x2cda2c0; 1 drivers +v0x2a57b10_0 .net "AorB", 0 0, L_0x2cdb810; 1 drivers +v0x2a57b90_0 .net "AxorB", 0 0, L_0x2cdbb70; 1 drivers +v0x2a54cd0_0 .net "B", 0 0, L_0x2cdb6b0; 1 drivers +v0x2a54d90_0 .alias "Command", 2 0, v0x2bc67a0_0; +v0x2a21140_0 .net "OrNorXorOut", 0 0, L_0x2cdc5d0; 1 drivers +v0x2a211c0_0 .net "XorNor", 0 0, L_0x2cdc030; 1 drivers +v0x2a3de70_0 .net "nXor", 0 0, L_0x2cdba60; 1 drivers +L_0x2cdc1b0 .part v0x2bc78e0_0, 2, 1; +L_0x2cdc7a0 .part v0x2bc78e0_0, 0, 1; +S_0x2a74660 .scope module, "mux0" "TwoInMux" 3 83, 3 8, S_0x29643b0; + .timescale -9 -12; +L_0x2cdbcd0/d .functor NOT 1, L_0x2cdc1b0, C4<0>, C4<0>, C4<0>; +L_0x2cdbcd0 .delay (10000,10000,10000) L_0x2cdbcd0/d; +L_0x2cdbdb0/d .functor AND 1, L_0x2cdbb70, L_0x2cdbcd0, C4<1>, C4<1>; +L_0x2cdbdb0 .delay (20000,20000,20000) L_0x2cdbdb0/d; +L_0x2cdbee0/d .functor AND 1, L_0x2cda2c0, L_0x2cdc1b0, C4<1>, C4<1>; +L_0x2cdbee0 .delay (20000,20000,20000) L_0x2cdbee0/d; +L_0x2cdc030/d .functor OR 1, L_0x2cdbdb0, L_0x2cdbee0, C4<0>, C4<0>; +L_0x2cdc030 .delay (20000,20000,20000) L_0x2cdc030/d; +v0x2a32610_0 .net "S", 0 0, L_0x2cdc1b0; 1 drivers +v0x2a637b0_0 .alias "in0", 0 0, v0x2a57b90_0; +v0x2a63850_0 .alias "in1", 0 0, v0x2a5a9f0_0; +v0x2a63260_0 .net "nS", 0 0, L_0x2cdbcd0; 1 drivers +v0x2a63300_0 .net "out0", 0 0, L_0x2cdbdb0; 1 drivers +v0x2a605d0_0 .net "out1", 0 0, L_0x2cdbee0; 1 drivers +v0x2a5d790_0 .alias "outfinal", 0 0, v0x2a211c0_0; +S_0x2a3b030 .scope module, "mux1" "TwoInMux" 3 84, 3 8, S_0x29643b0; + .timescale -9 -12; +L_0x2cdc250/d .functor NOT 1, L_0x2cdc7a0, C4<0>, C4<0>, C4<0>; +L_0x2cdc250 .delay (10000,10000,10000) L_0x2cdc250/d; +L_0x2cdc310/d .functor AND 1, L_0x2cdc030, L_0x2cdc250, C4<1>, C4<1>; +L_0x2cdc310 .delay (20000,20000,20000) L_0x2cdc310/d; +L_0x2cdc460/d .functor AND 1, L_0x2cdb810, L_0x2cdc7a0, C4<1>, C4<1>; +L_0x2cdc460 .delay (20000,20000,20000) L_0x2cdc460/d; +L_0x2cdc5d0/d .functor OR 1, L_0x2cdc310, L_0x2cdc460, C4<0>, C4<0>; +L_0x2cdc5d0 .delay (20000,20000,20000) L_0x2cdc5d0/d; +v0x2a381f0_0 .net "S", 0 0, L_0x2cdc7a0; 1 drivers +v0x2a38290_0 .alias "in0", 0 0, v0x2a211c0_0; +v0x2a1e3c0_0 .alias "in1", 0 0, v0x2a57b10_0; +v0x2a1e460_0 .net "nS", 0 0, L_0x2cdc250; 1 drivers +v0x2a353b0_0 .net "out0", 0 0, L_0x2cdc310; 1 drivers +v0x2a35450_0 .net "out1", 0 0, L_0x2cdc460; 1 drivers +v0x2a32570_0 .alias "outfinal", 0 0, v0x2a21140_0; +S_0x29cfb40 .scope generate, "orbits[23]" "orbits[23]" 3 196, 3 196, S_0x29fb160; + .timescale -9 -12; +P_0x29e7478 .param/l "i" 3 196, +C4<010111>; +S_0x29cda70 .scope module, "attempt" "OrNorXor" 3 198, 3 64, S_0x29cfb40; + .timescale -9 -12; +L_0x2cdb750/d .functor NOR 1, L_0x2cddc20, L_0x2cdc8e0, C4<0>, C4<0>; +L_0x2cdb750 .delay (10000,10000,10000) L_0x2cdb750/d; +L_0x2cdcb50/d .functor NOT 1, L_0x2cdb750, C4<0>, C4<0>, C4<0>; +L_0x2cdcb50 .delay (10000,10000,10000) L_0x2cdcb50/d; +L_0x2cdcc60/d .functor NAND 1, L_0x2cddc20, L_0x2cdc8e0, C4<1>, C4<1>; +L_0x2cdcc60 .delay (10000,10000,10000) L_0x2cdcc60/d; +L_0x2cdcdc0/d .functor NAND 1, L_0x2cdcc60, L_0x2cdcb50, C4<1>, C4<1>; +L_0x2cdcdc0 .delay (10000,10000,10000) L_0x2cdcdc0/d; +L_0x2cdced0/d .functor NOT 1, L_0x2cdcdc0, C4<0>, C4<0>, C4<0>; +L_0x2cdced0 .delay (10000,10000,10000) L_0x2cdced0/d; +v0x29a0950_0 .net "A", 0 0, L_0x2cddc20; 1 drivers +v0x296a1c0_0 .net "AnandB", 0 0, L_0x2cdcc60; 1 drivers +v0x296a260_0 .net "AnorB", 0 0, L_0x2cdb750; 1 drivers +v0x298cda0_0 .net "AorB", 0 0, L_0x2cdcb50; 1 drivers +v0x298ce20_0 .net "AxorB", 0 0, L_0x2cdced0; 1 drivers +v0x2989010_0 .net "B", 0 0, L_0x2cdc8e0; 1 drivers +v0x29890d0_0 .alias "Command", 2 0, v0x2bc67a0_0; +v0x28d3b50_0 .net "OrNorXorOut", 0 0, L_0x2cdd910; 1 drivers +v0x29831b0_0 .net "XorNor", 0 0, L_0x2cdd390; 1 drivers +v0x2983230_0 .net "nXor", 0 0, L_0x2cdcdc0; 1 drivers +L_0x2cdd510 .part v0x2bc78e0_0, 2, 1; +L_0x2cddae0 .part v0x2bc78e0_0, 0, 1; +S_0x29ac590 .scope module, "mux0" "TwoInMux" 3 83, 3 8, S_0x29cda70; + .timescale -9 -12; +L_0x2cdd030/d .functor NOT 1, L_0x2cdd510, C4<0>, C4<0>, C4<0>; +L_0x2cdd030 .delay (10000,10000,10000) L_0x2cdd030/d; +L_0x2cdd110/d .functor AND 1, L_0x2cdced0, L_0x2cdd030, C4<1>, C4<1>; +L_0x2cdd110 .delay (20000,20000,20000) L_0x2cdd110/d; +L_0x2cdd240/d .functor AND 1, L_0x2cdb750, L_0x2cdd510, C4<1>, C4<1>; +L_0x2cdd240 .delay (20000,20000,20000) L_0x2cdd240/d; +L_0x2cdd390/d .functor OR 1, L_0x2cdd110, L_0x2cdd240, C4<0>, C4<0>; +L_0x2cdd390 .delay (20000,20000,20000) L_0x2cdd390/d; +v0x296c2a0_0 .net "S", 0 0, L_0x2cdd510; 1 drivers +v0x29aa4c0_0 .alias "in0", 0 0, v0x298ce20_0; +v0x29aa560_0 .alias "in1", 0 0, v0x296a260_0; +v0x29a6730_0 .net "nS", 0 0, L_0x2cdd030; 1 drivers +v0x29a67d0_0 .net "out0", 0 0, L_0x2cdd110; 1 drivers +v0x29a4660_0 .net "out1", 0 0, L_0x2cdd240; 1 drivers +v0x29a08d0_0 .alias "outfinal", 0 0, v0x29831b0_0; +S_0x29c9ce0 .scope module, "mux1" "TwoInMux" 3 84, 3 8, S_0x29cda70; + .timescale -9 -12; +L_0x2cdd5b0/d .functor NOT 1, L_0x2cddae0, C4<0>, C4<0>, C4<0>; +L_0x2cdd5b0 .delay (10000,10000,10000) L_0x2cdd5b0/d; +L_0x2cdd670/d .functor AND 1, L_0x2cdd390, L_0x2cdd5b0, C4<1>, C4<1>; +L_0x2cdd670 .delay (20000,20000,20000) L_0x2cdd670/d; +L_0x2cdd7c0/d .functor AND 1, L_0x2cdcb50, L_0x2cddae0, C4<1>, C4<1>; +L_0x2cdd7c0 .delay (20000,20000,20000) L_0x2cdd7c0/d; +L_0x2cdd910/d .functor OR 1, L_0x2cdd670, L_0x2cdd7c0, C4<0>, C4<0>; +L_0x2cdd910 .delay (20000,20000,20000) L_0x2cdd910/d; +v0x29e1610_0 .net "S", 0 0, L_0x2cddae0; 1 drivers +v0x29c7c10_0 .alias "in0", 0 0, v0x29831b0_0; +v0x29c7cb0_0 .alias "in1", 0 0, v0x298cda0_0; +v0x29c3e80_0 .net "nS", 0 0, L_0x2cdd5b0; 1 drivers +v0x29c3f00_0 .net "out0", 0 0, L_0x2cdd670; 1 drivers +v0x29c1db0_0 .net "out1", 0 0, L_0x2cdd7c0; 1 drivers +v0x296c200_0 .alias "outfinal", 0 0, v0x28d3b50_0; +S_0x2aef130 .scope generate, "orbits[24]" "orbits[24]" 3 196, 3 196, S_0x29fb160; + .timescale -9 -12; +P_0x2af0a98 .param/l "i" 3 196, +C4<011000>; +S_0x2aeee90 .scope module, "attempt" "OrNorXor" 3 198, 3 64, S_0x2aef130; + .timescale -9 -12; +L_0x2cdc980/d .functor NOR 1, L_0x2cddcc0, L_0x2cddd60, C4<0>, C4<0>; +L_0x2cdc980 .delay (10000,10000,10000) L_0x2cdc980/d; +L_0x2cdca70/d .functor NOT 1, L_0x2cdc980, C4<0>, C4<0>, C4<0>; +L_0x2cdca70 .delay (10000,10000,10000) L_0x2cdca70/d; +L_0x2cddfa0/d .functor NAND 1, L_0x2cddcc0, L_0x2cddd60, C4<1>, C4<1>; +L_0x2cddfa0 .delay (10000,10000,10000) L_0x2cddfa0/d; +L_0x2cde100/d .functor NAND 1, L_0x2cddfa0, L_0x2cdca70, C4<1>, C4<1>; +L_0x2cde100 .delay (10000,10000,10000) L_0x2cde100/d; +L_0x2cde210/d .functor NOT 1, L_0x2cde100, C4<0>, C4<0>, C4<0>; +L_0x2cde210 .delay (10000,10000,10000) L_0x2cde210/d; +v0x2a02b00_0 .net "A", 0 0, L_0x2cddcc0; 1 drivers +v0x29ed250_0 .net "AnandB", 0 0, L_0x2cddfa0; 1 drivers +v0x29ed2f0_0 .net "AnorB", 0 0, L_0x2cdc980; 1 drivers +v0x29eb180_0 .net "AorB", 0 0, L_0x2cdca70; 1 drivers +v0x29eb200_0 .net "AxorB", 0 0, L_0x2cde210; 1 drivers +v0x29e73f0_0 .net "B", 0 0, L_0x2cddd60; 1 drivers +v0x29e74b0_0 .alias "Command", 2 0, v0x2bc67a0_0; +v0x29e5320_0 .net "OrNorXorOut", 0 0, L_0x2cdec50; 1 drivers +v0x29e53a0_0 .net "XorNor", 0 0, L_0x2cde6d0; 1 drivers +v0x29e1590_0 .net "nXor", 0 0, L_0x2cde100; 1 drivers +L_0x2cde850 .part v0x2bc78e0_0, 2, 1; +L_0x2cdee20 .part v0x2bc78e0_0, 0, 1; +S_0x2a0e740 .scope module, "mux0" "TwoInMux" 3 83, 3 8, S_0x2aeee90; + .timescale -9 -12; +L_0x2cde370/d .functor NOT 1, L_0x2cde850, C4<0>, C4<0>, C4<0>; +L_0x2cde370 .delay (10000,10000,10000) L_0x2cde370/d; +L_0x2cde450/d .functor AND 1, L_0x2cde210, L_0x2cde370, C4<1>, C4<1>; +L_0x2cde450 .delay (20000,20000,20000) L_0x2cde450/d; +L_0x2cde580/d .functor AND 1, L_0x2cdc980, L_0x2cde850, C4<1>, C4<1>; +L_0x2cde580 .delay (20000,20000,20000) L_0x2cde580/d; +L_0x2cde6d0/d .functor OR 1, L_0x2cde450, L_0x2cde580, C4<0>, C4<0>; +L_0x2cde6d0 .delay (20000,20000,20000) L_0x2cde6d0/d; +v0x2a108b0_0 .net "S", 0 0, L_0x2cde850; 1 drivers +v0x2a0a9b0_0 .alias "in0", 0 0, v0x29eb200_0; +v0x2a0aa50_0 .alias "in1", 0 0, v0x29ed2f0_0; +v0x2a088e0_0 .net "nS", 0 0, L_0x2cde370; 1 drivers +v0x2a08980_0 .net "out0", 0 0, L_0x2cde450; 1 drivers +v0x2a04b50_0 .net "out1", 0 0, L_0x2cde580; 1 drivers +v0x2a02a80_0 .alias "outfinal", 0 0, v0x29e53a0_0; +S_0x2aeebf0 .scope module, "mux1" "TwoInMux" 3 84, 3 8, S_0x2aeee90; + .timescale -9 -12; +L_0x2cde8f0/d .functor NOT 1, L_0x2cdee20, C4<0>, C4<0>, C4<0>; +L_0x2cde8f0 .delay (10000,10000,10000) L_0x2cde8f0/d; +L_0x2cde9b0/d .functor AND 1, L_0x2cde6d0, L_0x2cde8f0, C4<1>, C4<1>; +L_0x2cde9b0 .delay (20000,20000,20000) L_0x2cde9b0/d; +L_0x2cdeb00/d .functor AND 1, L_0x2cdca70, L_0x2cdee20, C4<1>, C4<1>; +L_0x2cdeb00 .delay (20000,20000,20000) L_0x2cdeb00/d; +L_0x2cdec50/d .functor OR 1, L_0x2cde9b0, L_0x2cdeb00, C4<0>, C4<0>; +L_0x2cdec50 .delay (20000,20000,20000) L_0x2cdec50/d; +v0x2af0210_0 .net "S", 0 0, L_0x2cdee20; 1 drivers +v0x2aee950_0 .alias "in0", 0 0, v0x29e53a0_0; +v0x2aee9f0_0 .alias "in1", 0 0, v0x29eb180_0; +v0x2aee650_0 .net "nS", 0 0, L_0x2cde8f0; 1 drivers +v0x2aee6d0_0 .net "out0", 0 0, L_0x2cde9b0; 1 drivers +v0x2aee0d0_0 .net "out1", 0 0, L_0x2cdeb00; 1 drivers +v0x2a10810_0 .alias "outfinal", 0 0, v0x29e5320_0; +S_0x28bcf10 .scope generate, "orbits[25]" "orbits[25]" 3 196, 3 196, S_0x29fb160; + .timescale -9 -12; +P_0x28bfcb8 .param/l "i" 3 196, +C4<011001>; +S_0x28ba770 .scope module, "attempt" "OrNorXor" 3 198, 3 64, S_0x28bcf10; + .timescale -9 -12; +L_0x2cdde00/d .functor NOR 1, L_0x2ce02a0, L_0x2cdef60, C4<0>, C4<0>; +L_0x2cdde00 .delay (10000,10000,10000) L_0x2cdde00/d; +L_0x2cdf1b0/d .functor NOT 1, L_0x2cdde00, C4<0>, C4<0>, C4<0>; +L_0x2cdf1b0 .delay (10000,10000,10000) L_0x2cdf1b0/d; +L_0x2cdf2e0/d .functor NAND 1, L_0x2ce02a0, L_0x2cdef60, C4<1>, C4<1>; +L_0x2cdf2e0 .delay (10000,10000,10000) L_0x2cdf2e0/d; +L_0x2cdf440/d .functor NAND 1, L_0x2cdf2e0, L_0x2cdf1b0, C4<1>, C4<1>; +L_0x2cdf440 .delay (10000,10000,10000) L_0x2cdf440/d; +L_0x2cdf550/d .functor NOT 1, L_0x2cdf440, C4<0>, C4<0>, C4<0>; +L_0x2cdf550 .delay (10000,10000,10000) L_0x2cdf550/d; +v0x2966540_0 .net "A", 0 0, L_0x2ce02a0; 1 drivers +v0x2af0f50_0 .net "AnandB", 0 0, L_0x2cdf2e0; 1 drivers +v0x2af0ff0_0 .net "AnorB", 0 0, L_0x2cdde00; 1 drivers +v0x2af0cb0_0 .net "AorB", 0 0, L_0x2cdf1b0; 1 drivers +v0x2af0d30_0 .net "AxorB", 0 0, L_0x2cdf550; 1 drivers +v0x2af0a10_0 .net "B", 0 0, L_0x2cdef60; 1 drivers +v0x2af0ad0_0 .alias "Command", 2 0, v0x2bc67a0_0; +v0x2af0710_0 .net "OrNorXorOut", 0 0, L_0x2cdff90; 1 drivers +v0x2af0790_0 .net "XorNor", 0 0, L_0x2cdfa10; 1 drivers +v0x2af0190_0 .net "nXor", 0 0, L_0x2cdf440; 1 drivers +L_0x2cdfb90 .part v0x2bc78e0_0, 2, 1; +L_0x2ce0160 .part v0x2bc78e0_0, 0, 1; +S_0x28f1420 .scope module, "mux0" "TwoInMux" 3 83, 3 8, S_0x28ba770; + .timescale -9 -12; +L_0x2cdf6b0/d .functor NOT 1, L_0x2cdfb90, C4<0>, C4<0>, C4<0>; +L_0x2cdf6b0 .delay (10000,10000,10000) L_0x2cdf6b0/d; +L_0x2cdf790/d .functor AND 1, L_0x2cdf550, L_0x2cdf6b0, C4<1>, C4<1>; +L_0x2cdf790 .delay (20000,20000,20000) L_0x2cdf790/d; +L_0x2cdf8c0/d .functor AND 1, L_0x2cdde00, L_0x2cdfb90, C4<1>, C4<1>; +L_0x2cdf8c0 .delay (20000,20000,20000) L_0x2cdf8c0/d; +L_0x2cdfa10/d .functor OR 1, L_0x2cdf790, L_0x2cdf8c0, C4<0>, C4<0>; +L_0x2cdfa10 .delay (20000,20000,20000) L_0x2cdfa10/d; +v0x2896a30_0 .net "S", 0 0, L_0x2cdfb90; 1 drivers +v0x2af2400_0 .alias "in0", 0 0, v0x2af0d30_0; +v0x2af24a0_0 .alias "in1", 0 0, v0x2af0ff0_0; +v0x2af2160_0 .net "nS", 0 0, L_0x2cdf6b0; 1 drivers +v0x2af2200_0 .net "out0", 0 0, L_0x2cdf790; 1 drivers +v0x2af11f0_0 .net "out1", 0 0, L_0x2cdf8c0; 1 drivers +v0x29664c0_0 .alias "outfinal", 0 0, v0x2af0790_0; +S_0x28ba260 .scope module, "mux1" "TwoInMux" 3 84, 3 8, S_0x28ba770; + .timescale -9 -12; +L_0x2cdfc30/d .functor NOT 1, L_0x2ce0160, C4<0>, C4<0>, C4<0>; +L_0x2cdfc30 .delay (10000,10000,10000) L_0x2cdfc30/d; +L_0x2cdfcf0/d .functor AND 1, L_0x2cdfa10, L_0x2cdfc30, C4<1>, C4<1>; +L_0x2cdfcf0 .delay (20000,20000,20000) L_0x2cdfcf0/d; +L_0x2cdfe40/d .functor AND 1, L_0x2cdf1b0, L_0x2ce0160, C4<1>, C4<1>; +L_0x2cdfe40 .delay (20000,20000,20000) L_0x2cdfe40/d; +L_0x2cdff90/d .functor OR 1, L_0x2cdfcf0, L_0x2cdfe40, C4<0>, C4<0>; +L_0x2cdff90 .delay (20000,20000,20000) L_0x2cdff90/d; +v0x2898fa0_0 .net "S", 0 0, L_0x2ce0160; 1 drivers +v0x28b7b10_0 .alias "in0", 0 0, v0x2af0790_0; +v0x28b7bb0_0 .alias "in1", 0 0, v0x2af0cb0_0; +v0x28b7600_0 .net "nS", 0 0, L_0x2cdfc30; 1 drivers +v0x28b7680_0 .net "out0", 0 0, L_0x2cdfcf0; 1 drivers +v0x28b4eb0_0 .net "out1", 0 0, L_0x2cdfe40; 1 drivers +v0x2896990_0 .alias "outfinal", 0 0, v0x2af0710_0; +S_0x28d0ef0 .scope generate, "orbits[26]" "orbits[26]" 3 196, 3 196, S_0x29fb160; + .timescale -9 -12; +P_0x28d6328 .param/l "i" 3 196, +C4<011010>; +S_0x28d09e0 .scope module, "attempt" "OrNorXor" 3 198, 3 64, S_0x28d0ef0; + .timescale -9 -12; +L_0x2cdf000/d .functor NOR 1, L_0x2ce0340, L_0x2ce03e0, C4<0>, C4<0>; +L_0x2cdf000 .delay (10000,10000,10000) L_0x2cdf000/d; +L_0x2cdf110/d .functor NOT 1, L_0x2cdf000, C4<0>, C4<0>, C4<0>; +L_0x2cdf110 .delay (10000,10000,10000) L_0x2cdf110/d; +L_0x2ce0630/d .functor NAND 1, L_0x2ce0340, L_0x2ce03e0, C4<1>, C4<1>; +L_0x2ce0630 .delay (10000,10000,10000) L_0x2ce0630/d; +L_0x2ce0790/d .functor NAND 1, L_0x2ce0630, L_0x2cdf110, C4<1>, C4<1>; +L_0x2ce0790 .delay (10000,10000,10000) L_0x2ce0790/d; +L_0x2ce08a0/d .functor NOT 1, L_0x2ce0790, C4<0>, C4<0>, C4<0>; +L_0x2ce08a0 .delay (10000,10000,10000) L_0x2ce08a0/d; +v0x28c2f20_0 .net "A", 0 0, L_0x2ce0340; 1 drivers +v0x28c2950_0 .net "AnandB", 0 0, L_0x2ce0630; 1 drivers +v0x28c29f0_0 .net "AnorB", 0 0, L_0x2cdf000; 1 drivers +v0x28c0180_0 .net "AorB", 0 0, L_0x2cdf110; 1 drivers +v0x28c0200_0 .net "AxorB", 0 0, L_0x2ce08a0; 1 drivers +v0x28bfc30_0 .net "B", 0 0, L_0x2ce03e0; 1 drivers +v0x28bfcf0_0 .alias "Command", 2 0, v0x2bc67a0_0; +v0x28bd460_0 .net "OrNorXorOut", 0 0, L_0x2ce1300; 1 drivers +v0x28bd4e0_0 .net "XorNor", 0 0, L_0x2ce0d60; 1 drivers +v0x2898f20_0 .net "nXor", 0 0, L_0x2ce0790; 1 drivers +L_0x2ce0ee0 .part v0x2bc78e0_0, 2, 1; +L_0x2ce14d0 .part v0x2bc78e0_0, 0, 1; +S_0x28c88e0 .scope module, "mux0" "TwoInMux" 3 83, 3 8, S_0x28d09e0; + .timescale -9 -12; +L_0x2ce0a00/d .functor NOT 1, L_0x2ce0ee0, C4<0>, C4<0>, C4<0>; +L_0x2ce0a00 .delay (10000,10000,10000) L_0x2ce0a00/d; +L_0x2ce0ae0/d .functor AND 1, L_0x2ce08a0, L_0x2ce0a00, C4<1>, C4<1>; +L_0x2ce0ae0 .delay (20000,20000,20000) L_0x2ce0ae0/d; +L_0x2ce0c10/d .functor AND 1, L_0x2cdf000, L_0x2ce0ee0, C4<1>, C4<1>; +L_0x2ce0c10 .delay (20000,20000,20000) L_0x2ce0c10/d; +L_0x2ce0d60/d .functor OR 1, L_0x2ce0ae0, L_0x2ce0c10, C4<0>, C4<0>; +L_0x2ce0d60 .delay (20000,20000,20000) L_0x2ce0d60/d; +v0x28cb150_0 .net "S", 0 0, L_0x2ce0ee0; 1 drivers +v0x28c8390_0 .alias "in0", 0 0, v0x28c0200_0; +v0x28c8430_0 .alias "in1", 0 0, v0x28c29f0_0; +v0x28c5bc0_0 .net "nS", 0 0, L_0x2ce0a00; 1 drivers +v0x28c5c60_0 .net "out0", 0 0, L_0x2ce0ae0; 1 drivers +v0x28c5670_0 .net "out1", 0 0, L_0x2ce0c10; 1 drivers +v0x28c2ea0_0 .alias "outfinal", 0 0, v0x28bd4e0_0; +S_0x28ce290 .scope module, "mux1" "TwoInMux" 3 84, 3 8, S_0x28d09e0; + .timescale -9 -12; +L_0x2ce0f80/d .functor NOT 1, L_0x2ce14d0, C4<0>, C4<0>, C4<0>; +L_0x2ce0f80 .delay (10000,10000,10000) L_0x2ce0f80/d; +L_0x2ce1040/d .functor AND 1, L_0x2ce0d60, L_0x2ce0f80, C4<1>, C4<1>; +L_0x2ce1040 .delay (20000,20000,20000) L_0x2ce1040/d; +L_0x2ce1190/d .functor AND 1, L_0x2cdf110, L_0x2ce14d0, C4<1>, C4<1>; +L_0x2ce1190 .delay (20000,20000,20000) L_0x2ce1190/d; +L_0x2ce1300/d .functor OR 1, L_0x2ce1040, L_0x2ce1190, C4<0>, C4<0>; +L_0x2ce1300 .delay (20000,20000,20000) L_0x2ce1300/d; +v0x28cdd80_0 .net "S", 0 0, L_0x2ce14d0; 1 drivers +v0x28cde20_0 .alias "in0", 0 0, v0x28bd4e0_0; +v0x289b670_0 .alias "in1", 0 0, v0x28c0180_0; +v0x289b710_0 .net "nS", 0 0, L_0x2ce0f80; 1 drivers +v0x28cb600_0 .net "out0", 0 0, L_0x2ce1040; 1 drivers +v0x28cb6a0_0 .net "out1", 0 0, L_0x2ce1190; 1 drivers +v0x28cb0b0_0 .alias "outfinal", 0 0, v0x28bd460_0; +S_0x289e330 .scope generate, "orbits[27]" "orbits[27]" 3 196, 3 196, S_0x29fb160; + .timescale -9 -12; +P_0x28eca78 .param/l "i" 3 196, +C4<011011>; +S_0x28e7500 .scope module, "attempt" "OrNorXor" 3 198, 3 64, S_0x289e330; + .timescale -9 -12; +L_0x2ce0480/d .functor NOR 1, L_0x2ce2960, L_0x2ce1610, C4<0>, C4<0>; +L_0x2ce0480 .delay (10000,10000,10000) L_0x2ce0480/d; +L_0x2ce1890/d .functor NOT 1, L_0x2ce0480, C4<0>, C4<0>, C4<0>; +L_0x2ce1890 .delay (10000,10000,10000) L_0x2ce1890/d; +L_0x2ce19a0/d .functor NAND 1, L_0x2ce2960, L_0x2ce1610, C4<1>, C4<1>; +L_0x2ce19a0 .delay (10000,10000,10000) L_0x2ce19a0/d; +L_0x2ce1b00/d .functor NAND 1, L_0x2ce19a0, L_0x2ce1890, C4<1>, C4<1>; +L_0x2ce1b00 .delay (10000,10000,10000) L_0x2ce1b00/d; +L_0x2ce1c10/d .functor NOT 1, L_0x2ce1b00, C4<0>, C4<0>, C4<0>; +L_0x2ce1c10 .delay (10000,10000,10000) L_0x2ce1c10/d; +v0x28d9490_0 .net "A", 0 0, L_0x2ce2960; 1 drivers +v0x28d8f00_0 .net "AnandB", 0 0, L_0x2ce19a0; 1 drivers +v0x28d8fa0_0 .net "AnorB", 0 0, L_0x2ce0480; 1 drivers +v0x28d67b0_0 .net "AorB", 0 0, L_0x2ce1890; 1 drivers +v0x28d6830_0 .net "AxorB", 0 0, L_0x2ce1c10; 1 drivers +v0x28d62a0_0 .net "B", 0 0, L_0x2ce1610; 1 drivers +v0x28d6360_0 .alias "Command", 2 0, v0x2bc67a0_0; +v0x28d3be0_0 .net "OrNorXorOut", 0 0, L_0x2ce2650; 1 drivers +v0x28d3640_0 .net "XorNor", 0 0, L_0x2ce20d0; 1 drivers +v0x28d36c0_0 .net "nXor", 0 0, L_0x2ce1b00; 1 drivers +L_0x2ce2250 .part v0x2bc78e0_0, 2, 1; +L_0x2ce2820 .part v0x2bc78e0_0, 0, 1; +S_0x28deda0 .scope module, "mux0" "TwoInMux" 3 83, 3 8, S_0x28e7500; + .timescale -9 -12; +L_0x2ce1d70/d .functor NOT 1, L_0x2ce2250, C4<0>, C4<0>, C4<0>; +L_0x2ce1d70 .delay (10000,10000,10000) L_0x2ce1d70/d; +L_0x2ce1e50/d .functor AND 1, L_0x2ce1c10, L_0x2ce1d70, C4<1>, C4<1>; +L_0x2ce1e50 .delay (20000,20000,20000) L_0x2ce1e50/d; +L_0x2ce1f80/d .functor AND 1, L_0x2ce0480, L_0x2ce2250, C4<1>, C4<1>; +L_0x2ce1f80 .delay (20000,20000,20000) L_0x2ce1f80/d; +L_0x2ce20d0/d .functor OR 1, L_0x2ce1e50, L_0x2ce1f80, C4<0>, C4<0>; +L_0x2ce20d0 .delay (20000,20000,20000) L_0x2ce20d0/d; +v0x28e1610_0 .net "S", 0 0, L_0x2ce2250; 1 drivers +v0x28de850_0 .alias "in0", 0 0, v0x28d6830_0; +v0x28de8f0_0 .alias "in1", 0 0, v0x28d8fa0_0; +v0x28dc070_0 .net "nS", 0 0, L_0x2ce1d70; 1 drivers +v0x28dc110_0 .net "out0", 0 0, L_0x2ce1e50; 1 drivers +v0x28dbb60_0 .net "out1", 0 0, L_0x2ce1f80; 1 drivers +v0x28d9410_0 .alias "outfinal", 0 0, v0x28d3640_0; +S_0x28e6fb0 .scope module, "mux1" "TwoInMux" 3 84, 3 8, S_0x28e7500; + .timescale -9 -12; +L_0x2ce22f0/d .functor NOT 1, L_0x2ce2820, C4<0>, C4<0>, C4<0>; +L_0x2ce22f0 .delay (10000,10000,10000) L_0x2ce22f0/d; +L_0x2ce23b0/d .functor AND 1, L_0x2ce20d0, L_0x2ce22f0, C4<1>, C4<1>; +L_0x2ce23b0 .delay (20000,20000,20000) L_0x2ce23b0/d; +L_0x2ce2500/d .functor AND 1, L_0x2ce1890, L_0x2ce2820, C4<1>, C4<1>; +L_0x2ce2500 .delay (20000,20000,20000) L_0x2ce2500/d; +L_0x2ce2650/d .functor OR 1, L_0x2ce23b0, L_0x2ce2500, C4<0>, C4<0>; +L_0x2ce2650 .delay (20000,20000,20000) L_0x2ce2650/d; +v0x28e9d50_0 .net "S", 0 0, L_0x2ce2820; 1 drivers +v0x28e47e0_0 .alias "in0", 0 0, v0x28d3640_0; +v0x28e4880_0 .alias "in1", 0 0, v0x28d67b0_0; +v0x28e4290_0 .net "nS", 0 0, L_0x2ce22f0; 1 drivers +v0x28e4310_0 .net "out0", 0 0, L_0x2ce23b0; 1 drivers +v0x28e1ac0_0 .net "out1", 0 0, L_0x2ce2500; 1 drivers +v0x28e1570_0 .alias "outfinal", 0 0, v0x28d3be0_0; +S_0x28af5f0 .scope generate, "orbits[28]" "orbits[28]" 3 196, 3 196, S_0x29fb160; + .timescale -9 -12; +P_0x2a17788 .param/l "i" 3 196, +C4<011100>; +S_0x28af0e0 .scope module, "attempt" "OrNorXor" 3 198, 3 64, S_0x28af5f0; + .timescale -9 -12; +L_0x2ce16b0/d .functor NOR 1, L_0x2ce2a00, L_0x2ce2aa0, C4<0>, C4<0>; +L_0x2ce16b0 .delay (10000,10000,10000) L_0x2ce16b0/d; +L_0x2ce17a0/d .functor NOT 1, L_0x2ce16b0, C4<0>, C4<0>, C4<0>; +L_0x2ce17a0 .delay (10000,10000,10000) L_0x2ce17a0/d; +L_0x2ce2ce0/d .functor NAND 1, L_0x2ce2a00, L_0x2ce2aa0, C4<1>, C4<1>; +L_0x2ce2ce0 .delay (10000,10000,10000) L_0x2ce2ce0/d; +L_0x2ce2e40/d .functor NAND 1, L_0x2ce2ce0, L_0x2ce17a0, C4<1>, C4<1>; +L_0x2ce2e40 .delay (10000,10000,10000) L_0x2ce2e40/d; +L_0x2ce2f50/d .functor NOT 1, L_0x2ce2e40, C4<0>, C4<0>, C4<0>; +L_0x2ce2f50 .delay (10000,10000,10000) L_0x2ce2f50/d; +v0x28a10d0_0 .net "A", 0 0, L_0x2ce2a00; 1 drivers +v0x289e880_0 .net "AnandB", 0 0, L_0x2ce2ce0; 1 drivers +v0x289e920_0 .net "AnorB", 0 0, L_0x2ce16b0; 1 drivers +v0x28ecf40_0 .net "AorB", 0 0, L_0x2ce17a0; 1 drivers +v0x28ecfc0_0 .net "AxorB", 0 0, L_0x2ce2f50; 1 drivers +v0x28ec9f0_0 .net "B", 0 0, L_0x2ce2aa0; 1 drivers +v0x28ecab0_0 .alias "Command", 2 0, v0x2bc67a0_0; +v0x28ea220_0 .net "OrNorXorOut", 0 0, L_0x2ce3990; 1 drivers +v0x28ea2a0_0 .net "XorNor", 0 0, L_0x2ce3410; 1 drivers +v0x28e9cd0_0 .net "nXor", 0 0, L_0x2ce2e40; 1 drivers +L_0x2ce3590 .part v0x2bc78e0_0, 2, 1; +L_0x2ce3b60 .part v0x2bc78e0_0, 0, 1; +S_0x28a6a90 .scope module, "mux0" "TwoInMux" 3 83, 3 8, S_0x28af0e0; + .timescale -9 -12; +L_0x2ce30b0/d .functor NOT 1, L_0x2ce3590, C4<0>, C4<0>, C4<0>; +L_0x2ce30b0 .delay (10000,10000,10000) L_0x2ce30b0/d; +L_0x2ce3190/d .functor AND 1, L_0x2ce2f50, L_0x2ce30b0, C4<1>, C4<1>; +L_0x2ce3190 .delay (20000,20000,20000) L_0x2ce3190/d; +L_0x2ce32c0/d .functor AND 1, L_0x2ce16b0, L_0x2ce3590, C4<1>, C4<1>; +L_0x2ce32c0 .delay (20000,20000,20000) L_0x2ce32c0/d; +L_0x2ce3410/d .functor OR 1, L_0x2ce3190, L_0x2ce32c0, C4<0>, C4<0>; +L_0x2ce3410 .delay (20000,20000,20000) L_0x2ce3410/d; +v0x28a7080_0 .net "S", 0 0, L_0x2ce3590; 1 drivers +v0x28a42c0_0 .alias "in0", 0 0, v0x28ecfc0_0; +v0x28a4360_0 .alias "in1", 0 0, v0x289e920_0; +v0x28a3d70_0 .net "nS", 0 0, L_0x2ce30b0; 1 drivers +v0x28a3e10_0 .net "out0", 0 0, L_0x2ce3190; 1 drivers +v0x28a15a0_0 .net "out1", 0 0, L_0x2ce32c0; 1 drivers +v0x28a1050_0 .alias "outfinal", 0 0, v0x28ea2a0_0; +S_0x28ac990 .scope module, "mux1" "TwoInMux" 3 84, 3 8, S_0x28af0e0; + .timescale -9 -12; +L_0x2ce3630/d .functor NOT 1, L_0x2ce3b60, C4<0>, C4<0>, C4<0>; +L_0x2ce3630 .delay (10000,10000,10000) L_0x2ce3630/d; +L_0x2ce36f0/d .functor AND 1, L_0x2ce3410, L_0x2ce3630, C4<1>, C4<1>; +L_0x2ce36f0 .delay (20000,20000,20000) L_0x2ce36f0/d; +L_0x2ce3840/d .functor AND 1, L_0x2ce17a0, L_0x2ce3b60, C4<1>, C4<1>; +L_0x2ce3840 .delay (20000,20000,20000) L_0x2ce3840/d; +L_0x2ce3990/d .functor OR 1, L_0x2ce36f0, L_0x2ce3840, C4<0>, C4<0>; +L_0x2ce3990 .delay (20000,20000,20000) L_0x2ce3990/d; +v0x2898a90_0 .net "S", 0 0, L_0x2ce3b60; 1 drivers +v0x28ac480_0 .alias "in0", 0 0, v0x28ea2a0_0; +v0x28ac520_0 .alias "in1", 0 0, v0x28ecf40_0; +v0x28a9d00_0 .net "nS", 0 0, L_0x2ce3630; 1 drivers +v0x28a9d80_0 .net "out0", 0 0, L_0x2ce36f0; 1 drivers +v0x28a97b0_0 .net "out1", 0 0, L_0x2ce3840; 1 drivers +v0x28a6fe0_0 .alias "outfinal", 0 0, v0x28ea220_0; +S_0x2a12d50 .scope generate, "orbits[29]" "orbits[29]" 3 196, 3 196, S_0x29fb160; + .timescale -9 -12; +P_0x2a0bdb8 .param/l "i" 3 196, +C4<011101>; +S_0x2a12aa0 .scope module, "attempt" "OrNorXor" 3 198, 3 64, S_0x2a12d50; + .timescale -9 -12; +L_0x2ce2b40/d .functor NOR 1, L_0x2ce4fa0, L_0x2ce3ca0, C4<0>, C4<0>; +L_0x2ce2b40 .delay (10000,10000,10000) L_0x2ce2b40/d; +L_0x2ce2c30/d .functor NOT 1, L_0x2ce2b40, C4<0>, C4<0>, C4<0>; +L_0x2ce2c30 .delay (10000,10000,10000) L_0x2ce2c30/d; +L_0x2ce4020/d .functor NAND 1, L_0x2ce4fa0, L_0x2ce3ca0, C4<1>, C4<1>; +L_0x2ce4020 .delay (10000,10000,10000) L_0x2ce4020/d; +L_0x2ce4180/d .functor NAND 1, L_0x2ce4020, L_0x2ce2c30, C4<1>, C4<1>; +L_0x2ce4180 .delay (10000,10000,10000) L_0x2ce4180/d; +L_0x2ce4290/d .functor NOT 1, L_0x2ce4180, C4<0>, C4<0>, C4<0>; +L_0x2ce4290 .delay (10000,10000,10000) L_0x2ce4290/d; +v0x2b293c0_0 .net "A", 0 0, L_0x2ce4fa0; 1 drivers +v0x2672ab0_0 .net "AnandB", 0 0, L_0x2ce4020; 1 drivers +v0x2672b50_0 .net "AnorB", 0 0, L_0x2ce2b40; 1 drivers +v0x28b49a0_0 .net "AorB", 0 0, L_0x2ce2c30; 1 drivers +v0x28b4a20_0 .net "AxorB", 0 0, L_0x2ce4290; 1 drivers +v0x28b2250_0 .net "B", 0 0, L_0x2ce3ca0; 1 drivers +v0x28b22d0_0 .alias "Command", 2 0, v0x2bc67a0_0; +v0x28b1d40_0 .net "OrNorXorOut", 0 0, L_0x2ce4c90; 1 drivers +v0x28b1dc0_0 .net "XorNor", 0 0, L_0x2ce4710; 1 drivers +v0x2898a10_0 .net "nXor", 0 0, L_0x2ce4180; 1 drivers +L_0x2ce4890 .part v0x2bc78e0_0, 2, 1; +L_0x2ce4e60 .part v0x2bc78e0_0, 0, 1; +S_0x2a18b70 .scope module, "mux0" "TwoInMux" 3 83, 3 8, S_0x2a12aa0; + .timescale -9 -12; +L_0x2ce43f0/d .functor NOT 1, L_0x2ce4890, C4<0>, C4<0>, C4<0>; +L_0x2ce43f0 .delay (10000,10000,10000) L_0x2ce43f0/d; +L_0x2ce44b0/d .functor AND 1, L_0x2ce4290, L_0x2ce43f0, C4<1>, C4<1>; +L_0x2ce44b0 .delay (20000,20000,20000) L_0x2ce44b0/d; +L_0x2ce45c0/d .functor AND 1, L_0x2ce2b40, L_0x2ce4890, C4<1>, C4<1>; +L_0x2ce45c0 .delay (20000,20000,20000) L_0x2ce45c0/d; +L_0x2ce4710/d .functor OR 1, L_0x2ce44b0, L_0x2ce45c0, C4<0>, C4<0>; +L_0x2ce4710 .delay (20000,20000,20000) L_0x2ce4710/d; +v0x2a15630_0 .net "S", 0 0, L_0x2ce4890; 1 drivers +v0x2a188c0_0 .alias "in0", 0 0, v0x28b4a20_0; +v0x2a18940_0 .alias "in1", 0 0, v0x2672b50_0; +v0x2a17950_0 .net "nS", 0 0, L_0x2ce43f0; 1 drivers +v0x2a179d0_0 .net "out0", 0 0, L_0x2ce44b0; 1 drivers +v0x2a176a0_0 .net "out1", 0 0, L_0x2ce45c0; 1 drivers +v0x2b29340_0 .alias "outfinal", 0 0, v0x28b1dc0_0; +S_0x2a11b30 .scope module, "mux1" "TwoInMux" 3 84, 3 8, S_0x2a12aa0; + .timescale -9 -12; +L_0x2ce4930/d .functor NOT 1, L_0x2ce4e60, C4<0>, C4<0>, C4<0>; +L_0x2ce4930 .delay (10000,10000,10000) L_0x2ce4930/d; +L_0x2ce49f0/d .functor AND 1, L_0x2ce4710, L_0x2ce4930, C4<1>, C4<1>; +L_0x2ce49f0 .delay (20000,20000,20000) L_0x2ce49f0/d; +L_0x2ce4b40/d .functor AND 1, L_0x2ce2c30, L_0x2ce4e60, C4<1>, C4<1>; +L_0x2ce4b40 .delay (20000,20000,20000) L_0x2ce4b40/d; +L_0x2ce4c90/d .functor OR 1, L_0x2ce49f0, L_0x2ce4b40, C4<0>, C4<0>; +L_0x2ce4c90 .delay (20000,20000,20000) L_0x2ce4c90/d; +v0x2a0f2b0_0 .net "S", 0 0, L_0x2ce4e60; 1 drivers +v0x2a11880_0 .alias "in0", 0 0, v0x28b1dc0_0; +v0x2a11900_0 .alias "in1", 0 0, v0x28b49a0_0; +v0x2a0ef80_0 .net "nS", 0 0, L_0x2ce4930; 1 drivers +v0x2a0f000_0 .net "out0", 0 0, L_0x2ce49f0; 1 drivers +v0x2a15860_0 .net "out1", 0 0, L_0x2ce4b40; 1 drivers +v0x2a155b0_0 .alias "outfinal", 0 0, v0x28b1d40_0; +S_0x2a05bc0 .scope generate, "orbits[30]" "orbits[30]" 3 196, 3 196, S_0x29fb160; + .timescale -9 -12; +P_0x2a059d8 .param/l "i" 3 196, +C4<011110>; +S_0x2a032c0 .scope module, "attempt" "OrNorXor" 3 198, 3 64, S_0x2a05bc0; + .timescale -9 -12; +L_0x2ce3d40/d .functor NOR 1, L_0x2ce5040, L_0x2ce50e0, C4<0>, C4<0>; +L_0x2ce3d40 .delay (10000,10000,10000) L_0x2ce3d40/d; +L_0x2ce3e30/d .functor NOT 1, L_0x2ce3d40, C4<0>, C4<0>, C4<0>; +L_0x2ce3e30 .delay (10000,10000,10000) L_0x2ce3e30/d; +L_0x2ce3ef0/d .functor NAND 1, L_0x2ce5040, L_0x2ce50e0, C4<1>, C4<1>; +L_0x2ce3ef0 .delay (10000,10000,10000) L_0x2ce3ef0/d; +L_0x2ce5470/d .functor NAND 1, L_0x2ce3ef0, L_0x2ce3e30, C4<1>, C4<1>; +L_0x2ce5470 .delay (10000,10000,10000) L_0x2ce5470/d; +L_0x2ce5580/d .functor NOT 1, L_0x2ce5470, C4<0>, C4<0>, C4<0>; +L_0x2ce5580 .delay (10000,10000,10000) L_0x2ce5580/d; +v0x2a0baa0_0 .net "A", 0 0, L_0x2ce5040; 1 drivers +v0x2a09120_0 .net "AnandB", 0 0, L_0x2ce3ef0; 1 drivers +v0x2a091c0_0 .net "AnorB", 0 0, L_0x2ce3d40; 1 drivers +v0x2a0fa40_0 .net "AorB", 0 0, L_0x2ce3e30; 1 drivers +v0x2a0fac0_0 .net "AxorB", 0 0, L_0x2ce5580; 1 drivers +v0x2a0f790_0 .net "B", 0 0, L_0x2ce50e0; 1 drivers +v0x2a0f810_0 .alias "Command", 2 0, v0x2bc67a0_0; +v0x2a0f4e0_0 .net "OrNorXorOut", 0 0, L_0x2ce5f80; 1 drivers +v0x2a0f560_0 .net "XorNor", 0 0, L_0x2ce5a00; 1 drivers +v0x2a0f230_0 .net "nXor", 0 0, L_0x2ce5470; 1 drivers +L_0x2ce5b80 .part v0x2bc78e0_0, 2, 1; +L_0x2ce6150 .part v0x2bc78e0_0, 0, 1; +S_0x2a09680 .scope module, "mux0" "TwoInMux" 3 83, 3 8, S_0x2a032c0; + .timescale -9 -12; +L_0x2ce56e0/d .functor NOT 1, L_0x2ce5b80, C4<0>, C4<0>, C4<0>; +L_0x2ce56e0 .delay (10000,10000,10000) L_0x2ce56e0/d; +L_0x2ce57a0/d .functor AND 1, L_0x2ce5580, L_0x2ce56e0, C4<1>, C4<1>; +L_0x2ce57a0 .delay (20000,20000,20000) L_0x2ce57a0/d; +L_0x2ce58b0/d .functor AND 1, L_0x2ce3d40, L_0x2ce5b80, C4<1>, C4<1>; +L_0x2ce58b0 .delay (20000,20000,20000) L_0x2ce58b0/d; +L_0x2ce5a00/d .functor OR 1, L_0x2ce57a0, L_0x2ce58b0, C4<0>, C4<0>; +L_0x2ce5a00 .delay (20000,20000,20000) L_0x2ce5a00/d; +v0x2a093d0_0 .net "S", 0 0, L_0x2ce5b80; 1 drivers +v0x2a0cf10_0 .alias "in0", 0 0, v0x2a0fac0_0; +v0x2a0cfb0_0 .alias "in1", 0 0, v0x2a091c0_0; +v0x2a0cc60_0 .net "nS", 0 0, L_0x2ce56e0; 1 drivers +v0x2a0cce0_0 .net "out0", 0 0, L_0x2ce57a0; 1 drivers +v0x2a0bcd0_0 .net "out1", 0 0, L_0x2ce58b0; 1 drivers +v0x2a0ba20_0 .alias "outfinal", 0 0, v0x2a0f560_0; +S_0x2a0b770 .scope module, "mux1" "TwoInMux" 3 84, 3 8, S_0x2a032c0; + .timescale -9 -12; +L_0x2ce5c20/d .functor NOT 1, L_0x2ce6150, C4<0>, C4<0>, C4<0>; +L_0x2ce5c20 .delay (10000,10000,10000) L_0x2ce5c20/d; +L_0x2ce5ce0/d .functor AND 1, L_0x2ce5a00, L_0x2ce5c20, C4<1>, C4<1>; +L_0x2ce5ce0 .delay (20000,20000,20000) L_0x2ce5ce0/d; +L_0x2ce5e30/d .functor AND 1, L_0x2ce3e30, L_0x2ce6150, C4<1>, C4<1>; +L_0x2ce5e30 .delay (20000,20000,20000) L_0x2ce5e30/d; +L_0x2ce5f80/d .functor OR 1, L_0x2ce5ce0, L_0x2ce5e30, C4<0>, C4<0>; +L_0x2ce5f80 .delay (20000,20000,20000) L_0x2ce5f80/d; +v0x2a0b4c0_0 .net "S", 0 0, L_0x2ce6150; 1 drivers +v0x2a0b540_0 .alias "in0", 0 0, v0x2a0f560_0; +v0x2a0b210_0 .alias "in1", 0 0, v0x2a0fa40_0; +v0x2a0b290_0 .net "nS", 0 0, L_0x2ce5c20; 1 drivers +v0x2a09be0_0 .net "out0", 0 0, L_0x2ce5ce0; 1 drivers +v0x2a09c60_0 .net "out1", 0 0, L_0x2ce5e30; 1 drivers +v0x2a09970_0 .alias "outfinal", 0 0, v0x2a0f4e0_0; +S_0x29f9f40 .scope generate, "orbits[31]" "orbits[31]" 3 196, 3 196, S_0x29fb160; + .timescale -9 -12; +P_0x29fa238 .param/l "i" 3 196, +C4<011111>; +S_0x29ffab0 .scope module, "attempt" "OrNorXor" 3 198, 3 64, S_0x29f9f40; + .timescale -9 -12; +L_0x2ce5180/d .functor NOR 1, L_0x2ce75c0, L_0x2ce6290, C4<0>, C4<0>; +L_0x2ce5180 .delay (10000,10000,10000) L_0x2ce5180/d; +L_0x2ce5270/d .functor NOT 1, L_0x2ce5180, C4<0>, C4<0>, C4<0>; +L_0x2ce5270 .delay (10000,10000,10000) L_0x2ce5270/d; +L_0x2ce6620/d .functor NAND 1, L_0x2ce75c0, L_0x2ce6290, C4<1>, C4<1>; +L_0x2ce6620 .delay (10000,10000,10000) L_0x2ce6620/d; +L_0x2ce6780/d .functor NAND 1, L_0x2ce6620, L_0x2ce5270, C4<1>, C4<1>; +L_0x2ce6780 .delay (10000,10000,10000) L_0x2ce6780/d; +L_0x2ce6890/d .functor NOT 1, L_0x2ce6780, C4<0>, C4<0>, C4<0>; +L_0x2ce6890 .delay (10000,10000,10000) L_0x2ce6890/d; +v0x2a03ad0_0 .net "A", 0 0, L_0x2ce75c0; 1 drivers +v0x2a03820_0 .net "AnandB", 0 0, L_0x2ce6620; 1 drivers +v0x2a038c0_0 .net "AnorB", 0 0, L_0x2ce5180; 1 drivers +v0x2a03570_0 .net "AorB", 0 0, L_0x2ce5270; 1 drivers +v0x2a035f0_0 .net "AxorB", 0 0, L_0x2ce6890; 1 drivers +v0x2a070b0_0 .net "B", 0 0, L_0x2ce6290; 1 drivers +v0x2a06e00_0 .alias "Command", 2 0, v0x2bc67a0_0; +v0x2a06e80_0 .net "OrNorXorOut", 0 0, L_0x2ce72b0; 1 drivers +v0x2a05e70_0 .net "XorNor", 0 0, L_0x2ce6d10; 1 drivers +v0x2a05ef0_0 .net "nXor", 0 0, L_0x2ce6780; 1 drivers +L_0x2ce6e90 .part v0x2bc78e0_0, 2, 1; +L_0x2ce7480 .part v0x2bc78e0_0, 0, 1; +S_0x29ffd60 .scope module, "mux0" "TwoInMux" 3 83, 3 8, S_0x29ffab0; + .timescale -9 -12; +L_0x2ce69f0/d .functor NOT 1, L_0x2ce6e90, C4<0>, C4<0>, C4<0>; +L_0x2ce69f0 .delay (10000,10000,10000) L_0x2ce69f0/d; +L_0x2ce6ab0/d .functor AND 1, L_0x2ce6890, L_0x2ce69f0, C4<1>, C4<1>; +L_0x2ce6ab0 .delay (20000,20000,20000) L_0x2ce6ab0/d; +L_0x2ce6bc0/d .functor AND 1, L_0x2ce5180, L_0x2ce6e90, C4<1>, C4<1>; +L_0x2ce6bc0 .delay (20000,20000,20000) L_0x2ce6bc0/d; +L_0x2ce6d10/d .functor OR 1, L_0x2ce6ab0, L_0x2ce6bc0, C4<0>, C4<0>; +L_0x2ce6d10 .delay (20000,20000,20000) L_0x2ce6d10/d; +v0x2a05910_0 .net "S", 0 0, L_0x2ce6e90; 1 drivers +v0x2a05660_0 .alias "in0", 0 0, v0x2a035f0_0; +v0x2a05700_0 .alias "in1", 0 0, v0x2a038c0_0; +v0x2a053b0_0 .net "nS", 0 0, L_0x2ce69f0; 1 drivers +v0x2a05430_0 .net "out0", 0 0, L_0x2ce6ab0; 1 drivers +v0x2a03d80_0 .net "out1", 0 0, L_0x2ce6bc0; 1 drivers +v0x2a03e20_0 .alias "outfinal", 0 0, v0x2a05e70_0; +S_0x29fdf20 .scope module, "mux1" "TwoInMux" 3 84, 3 8, S_0x29ffab0; + .timescale -9 -12; +L_0x2ce6f30/d .functor NOT 1, L_0x2ce7480, C4<0>, C4<0>, C4<0>; +L_0x2ce6f30 .delay (10000,10000,10000) L_0x2ce6f30/d; +L_0x2ce7010/d .functor AND 1, L_0x2ce6d10, L_0x2ce6f30, C4<1>, C4<1>; +L_0x2ce7010 .delay (20000,20000,20000) L_0x2ce7010/d; +L_0x2ce7160/d .functor AND 1, L_0x2ce5270, L_0x2ce7480, C4<1>, C4<1>; +L_0x2ce7160 .delay (20000,20000,20000) L_0x2ce7160/d; +L_0x2ce72b0/d .functor OR 1, L_0x2ce7010, L_0x2ce7160, C4<0>, C4<0>; +L_0x2ce72b0 .delay (20000,20000,20000) L_0x2ce72b0/d; +v0x29fdc70_0 .net "S", 0 0, L_0x2ce7480; 1 drivers +v0x29fdd10_0 .alias "in0", 0 0, v0x2a05e70_0; +v0x2a01250_0 .alias "in1", 0 0, v0x2a03570_0; +v0x2a012f0_0 .net "nS", 0 0, L_0x2ce6f30; 1 drivers +v0x2a00fa0_0 .net "out0", 0 0, L_0x2ce7010; 1 drivers +v0x2a01040_0 .net "out1", 0 0, L_0x2ce7160; 1 drivers +v0x2a00070_0 .alias "outfinal", 0 0, v0x2a06e80_0; +S_0x29f2030 .scope module, "ZeroMux0case" "FourInMux" 3 283, 3 24, S_0x29738d0; + .timescale -9 -12; +L_0x2ce77a0/d .functor NOT 1, L_0x2c82790, C4<0>, C4<0>, C4<0>; +L_0x2ce77a0 .delay (10000,10000,10000) L_0x2ce77a0/d; +L_0x2ce7840/d .functor NOT 1, L_0x2c828c0, C4<0>, C4<0>, C4<0>; +L_0x2ce7840 .delay (10000,10000,10000) L_0x2ce7840/d; +L_0x2ce8bc0/d .functor NAND 1, L_0x2ce77a0, L_0x2ce7840, L_0x2c829f0, C4<1>; +L_0x2ce8bc0 .delay (10000,10000,10000) L_0x2ce8bc0/d; +L_0x2ce8cb0/d .functor NAND 1, L_0x2c82790, L_0x2ce7840, L_0x2c82a90, C4<1>; +L_0x2ce8cb0 .delay (10000,10000,10000) L_0x2ce8cb0/d; +L_0x2ce8da0/d .functor NAND 1, L_0x2ce77a0, L_0x2c828c0, L_0x2c82b30, C4<1>; +L_0x2ce8da0 .delay (10000,10000,10000) L_0x2ce8da0/d; +L_0x2ce8e90/d .functor NAND 1, L_0x2c82790, L_0x2c828c0, L_0x2c82c20, C4<1>; +L_0x2ce8e90 .delay (10000,10000,10000) L_0x2ce8e90/d; +L_0x2ce8f70/d .functor NAND 1, L_0x2ce8bc0, L_0x2ce8cb0, L_0x2ce8da0, L_0x2ce8e90; +L_0x2ce8f70 .delay (10000,10000,10000) L_0x2ce8f70/d; +v0x29f2380_0 .net "S0", 0 0, L_0x2c82790; 1 drivers +v0x29f55f0_0 .net "S1", 0 0, L_0x2c828c0; 1 drivers +v0x29f5690_0 .net "in0", 0 0, L_0x2c829f0; 1 drivers +v0x29f5340_0 .net "in1", 0 0, L_0x2c82a90; 1 drivers +v0x29f53c0_0 .net "in2", 0 0, L_0x2c82b30; 1 drivers +v0x29f43d0_0 .net "in3", 0 0, L_0x2c82c20; 1 drivers +v0x29f4470_0 .net "nS0", 0 0, L_0x2ce77a0; 1 drivers +v0x29f4140_0 .net "nS1", 0 0, L_0x2ce7840; 1 drivers +v0x29f8100_0 .net "out", 0 0, L_0x2ce8f70; 1 drivers +v0x29f81a0_0 .net "out0", 0 0, L_0x2ce8bc0; 1 drivers +v0x29f7e50_0 .net "out1", 0 0, L_0x2ce8cb0; 1 drivers +v0x29f7ef0_0 .net "out2", 0 0, L_0x2ce8da0; 1 drivers +v0x29fb4a0_0 .net "out3", 0 0, L_0x2ce8e90; 1 drivers +S_0x29ec1d0 .scope module, "OneMux0case" "FourInMux" 3 284, 3 24, S_0x29738d0; + .timescale -9 -12; +L_0x29f41c0/d .functor NOT 1, L_0x2c834c0, C4<0>, C4<0>, C4<0>; +L_0x29f41c0 .delay (10000,10000,10000) L_0x29f41c0/d; +L_0x2c82da0/d .functor NOT 1, L_0x2c835f0, C4<0>, C4<0>, C4<0>; +L_0x2c82da0 .delay (10000,10000,10000) L_0x2c82da0/d; +L_0x2c82e40/d .functor NAND 1, L_0x29f41c0, L_0x2c82da0, L_0x2c83720, C4<1>; +L_0x2c82e40 .delay (10000,10000,10000) L_0x2c82e40/d; +L_0x2c82f80/d .functor NAND 1, L_0x2c834c0, L_0x2c82da0, L_0x2c837c0, C4<1>; +L_0x2c82f80 .delay (10000,10000,10000) L_0x2c82f80/d; +L_0x2c83070/d .functor NAND 1, L_0x29f41c0, L_0x2c835f0, L_0x2c83860, C4<1>; +L_0x2c83070 .delay (10000,10000,10000) L_0x2c83070/d; +L_0x2c83160/d .functor NAND 1, L_0x2c834c0, L_0x2c835f0, L_0x2c83950, C4<1>; +L_0x2c83160 .delay (10000,10000,10000) L_0x2c83160/d; +L_0x2c83240/d .functor NAND 1, L_0x2c82e40, L_0x2c82f80, L_0x2c83070, L_0x2c83160; +L_0x2c83240 .delay (10000,10000,10000) L_0x2c83240/d; +v0x29ebf20_0 .net "S0", 0 0, L_0x2c834c0; 1 drivers +v0x29ebc70_0 .net "S1", 0 0, L_0x2c835f0; 1 drivers +v0x29ebd10_0 .net "in0", 0 0, L_0x2c83720; 1 drivers +v0x29ef7b0_0 .net "in1", 0 0, L_0x2c837c0; 1 drivers +v0x29ef830_0 .net "in2", 0 0, L_0x2c83860; 1 drivers +v0x29ef500_0 .net "in3", 0 0, L_0x2c83950; 1 drivers +v0x29ef5a0_0 .net "nS0", 0 0, L_0x29f41c0; 1 drivers +v0x29ee570_0 .net "nS1", 0 0, L_0x2c82da0; 1 drivers +v0x29ee610_0 .net "out", 0 0, L_0x2c83240; 1 drivers +v0x29ee2c0_0 .net "out0", 0 0, L_0x2c82e40; 1 drivers +v0x29ee340_0 .net "out1", 0 0, L_0x2c82f80; 1 drivers +v0x29eb9c0_0 .net "out2", 0 0, L_0x2c83070; 1 drivers +v0x29f22e0_0 .net "out3", 0 0, L_0x2c83160; 1 drivers +S_0x29e5b60 .scope module, "TwoMux0case" "TwoInMux" 3 285, 3 8, S_0x29738d0; + .timescale -9 -12; +L_0x2c83a40/d .functor NOT 1, L_0x2c58bd0, C4<0>, C4<0>, C4<0>; +L_0x2c83a40 .delay (10000,10000,10000) L_0x2c83a40/d; +L_0x2c83b30/d .functor AND 1, L_0x2c58c70, L_0x2c83a40, C4<1>, C4<1>; +L_0x2c83b30 .delay (20000,20000,20000) L_0x2c83b30/d; +L_0x2cea710/d .functor AND 1, L_0x2c58d60, L_0x2c58bd0, C4<1>, C4<1>; +L_0x2cea710 .delay (20000,20000,20000) L_0x2cea710/d; +L_0x2cea800/d .functor OR 1, L_0x2c83b30, L_0x2cea710, C4<0>, C4<0>; +L_0x2cea800 .delay (20000,20000,20000) L_0x2cea800/d; +v0x29ee010_0 .net "S", 0 0, L_0x2c58bd0; 1 drivers +v0x29edd60_0 .net "in0", 0 0, L_0x2c58c70; 1 drivers +v0x29ede00_0 .net "in1", 0 0, L_0x2c58d60; 1 drivers +v0x29edab0_0 .net "nS", 0 0, L_0x2c83a40; 1 drivers +v0x29edb30_0 .net "out0", 0 0, L_0x2c83b30; 1 drivers +v0x29ec480_0 .net "out1", 0 0, L_0x2cea710; 1 drivers +v0x29ec520_0 .net "outfinal", 0 0, L_0x2cea800; 1 drivers +S_0x29dc7e0 .scope generate, "muxbits[1]" "muxbits[1]" 3 290, 3 290, S_0x29738d0; + .timescale -9 -12; +P_0x29d1dc8 .param/l "i" 3 290, +C4<01>; +L_0x2c32930/d .functor OR 1, L_0x2c32a30, L_0x2c327f0, C4<0>, C4<0>; +L_0x2c32930 .delay (20000,20000,20000) L_0x2c32930/d; +v0x29e87b0_0 .net *"_s15", 0 0, L_0x2c32a30; 1 drivers +v0x29e8480_0 .net *"_s16", 0 0, L_0x2c327f0; 1 drivers +S_0x29e7f00 .scope module, "ZeroMux" "FourInMux" 3 292, 3 24, S_0x29dc7e0; + .timescale -9 -12; +L_0x2c2ee70/d .functor NOT 1, L_0x2c30a30, C4<0>, C4<0>, C4<0>; +L_0x2c2ee70 .delay (10000,10000,10000) L_0x2c2ee70/d; +L_0x2c2ef10/d .functor NOT 1, L_0x2c30b60, C4<0>, C4<0>, C4<0>; +L_0x2c2ef10 .delay (10000,10000,10000) L_0x2c2ef10/d; +L_0x2c30230/d .functor NAND 1, L_0x2c2ee70, L_0x2c2ef10, L_0x2c30c90, C4<1>; +L_0x2c30230 .delay (10000,10000,10000) L_0x2c30230/d; +L_0x2c30370/d .functor NAND 1, L_0x2c30a30, L_0x2c2ef10, L_0x2c30d30, C4<1>; +L_0x2c30370 .delay (10000,10000,10000) L_0x2c30370/d; +L_0x2c304c0/d .functor NAND 1, L_0x2c2ee70, L_0x2c30b60, L_0x2c30dd0, C4<1>; +L_0x2c304c0 .delay (10000,10000,10000) L_0x2c304c0/d; +L_0x2c30610/d .functor NAND 1, L_0x2c30a30, L_0x2c30b60, L_0x2c30f00, C4<1>; +L_0x2c30610 .delay (10000,10000,10000) L_0x2c30610/d; +L_0x2c30780/d .functor NAND 1, L_0x2c30230, L_0x2c30370, L_0x2c304c0, L_0x2c30610; +L_0x2c30780 .delay (10000,10000,10000) L_0x2c30780/d; +v0x29e7c50_0 .net "S0", 0 0, L_0x2c30a30; 1 drivers +v0x29e7cf0_0 .net "S1", 0 0, L_0x2c30b60; 1 drivers +v0x29e6620_0 .net "in0", 0 0, L_0x2c30c90; 1 drivers +v0x29e66c0_0 .net "in1", 0 0, L_0x2c30d30; 1 drivers +v0x29e6370_0 .net "in2", 0 0, L_0x2c30dd0; 1 drivers +v0x29e6410_0 .net "in3", 0 0, L_0x2c30f00; 1 drivers +v0x29e60e0_0 .net "nS0", 0 0, L_0x2c2ee70; 1 drivers +v0x29e5e10_0 .net "nS1", 0 0, L_0x2c2ef10; 1 drivers +v0x29e5eb0_0 .net "out", 0 0, L_0x2c30780; 1 drivers +v0x29e9950_0 .net "out0", 0 0, L_0x2c30230; 1 drivers +v0x29e99f0_0 .net "out1", 0 0, L_0x2c30370; 1 drivers +v0x29e96a0_0 .net "out2", 0 0, L_0x2c304c0; 1 drivers +v0x29e8710_0 .net "out3", 0 0, L_0x2c30610; 1 drivers +S_0x29dffb0 .scope module, "OneMux" "FourInMux" 3 293, 3 24, S_0x29dc7e0; + .timescale -9 -12; +L_0x2c30ff0/d .functor NOT 1, L_0x2c31960, C4<0>, C4<0>, C4<0>; +L_0x2c30ff0 .delay (10000,10000,10000) L_0x2c30ff0/d; +L_0x2c310e0/d .functor NOT 1, L_0x2c31a90, C4<0>, C4<0>, C4<0>; +L_0x2c310e0 .delay (10000,10000,10000) L_0x2c310e0/d; +L_0x2c31180/d .functor NAND 1, L_0x2c30ff0, L_0x2c310e0, L_0x2c31c20, C4<1>; +L_0x2c31180 .delay (10000,10000,10000) L_0x2c31180/d; +L_0x2c312c0/d .functor NAND 1, L_0x2c31960, L_0x2c310e0, L_0x2c31cc0, C4<1>; +L_0x2c312c0 .delay (10000,10000,10000) L_0x2c312c0/d; +L_0x2c313b0/d .functor NAND 1, L_0x2c30ff0, L_0x2c31a90, L_0x2c31dd0, C4<1>; +L_0x2c313b0 .delay (10000,10000,10000) L_0x2c313b0/d; +L_0x2c31500/d .functor NAND 1, L_0x2c31960, L_0x2c31a90, L_0x2c31e70, C4<1>; +L_0x2c31500 .delay (10000,10000,10000) L_0x2c31500/d; +L_0x2c31630/d .functor NAND 1, L_0x2c31180, L_0x2c312c0, L_0x2c313b0, L_0x2c31500; +L_0x2c31630 .delay (10000,10000,10000) L_0x2c31630/d; +v0x29e0300_0 .net "S0", 0 0, L_0x2c31960; 1 drivers +v0x29e3af0_0 .net "S1", 0 0, L_0x2c31a90; 1 drivers +v0x29e3b70_0 .net "in0", 0 0, L_0x2c31c20; 1 drivers +v0x29e3840_0 .net "in1", 0 0, L_0x2c31cc0; 1 drivers +v0x29e38e0_0 .net "in2", 0 0, L_0x2c31dd0; 1 drivers +v0x29e28b0_0 .net "in3", 0 0, L_0x2c31e70; 1 drivers +v0x29e2950_0 .net "nS0", 0 0, L_0x2c30ff0; 1 drivers +v0x29e2620_0 .net "nS1", 0 0, L_0x2c310e0; 1 drivers +v0x29dfd00_0 .net "out", 0 0, L_0x2c31630; 1 drivers +v0x29dfda0_0 .net "out0", 0 0, L_0x2c31180; 1 drivers +v0x29dfa60_0 .net "out1", 0 0, L_0x2c312c0; 1 drivers +v0x29dfb00_0 .net "out2", 0 0, L_0x2c313b0; 1 drivers +v0x29e8240_0 .net "out3", 0 0, L_0x2c31500; 1 drivers +S_0x29e2350 .scope module, "TwoMux" "TwoInMux" 3 294, 3 8, S_0x29dc7e0; + .timescale -9 -12; +L_0x2c31bc0/d .functor NOT 1, L_0x2c32440, C4<0>, C4<0>, C4<0>; +L_0x2c31bc0 .delay (10000,10000,10000) L_0x2c31bc0/d; +L_0x2c32030/d .functor AND 1, L_0x2c32570, L_0x2c31bc0, C4<1>, C4<1>; +L_0x2c32030 .delay (20000,20000,20000) L_0x2c32030/d; +L_0x2c32120/d .functor AND 1, L_0x2c326b0, L_0x2c32440, C4<1>, C4<1>; +L_0x2c32120 .delay (20000,20000,20000) L_0x2c32120/d; +L_0x2c32210/d .functor OR 1, L_0x2c32030, L_0x2c32120, C4<0>, C4<0>; +L_0x2c32210 .delay (20000,20000,20000) L_0x2c32210/d; +v0x29e20a0_0 .net "S", 0 0, L_0x2c32440; 1 drivers +v0x29e2140_0 .net "in0", 0 0, L_0x2c32570; 1 drivers +v0x29e1df0_0 .net "in1", 0 0, L_0x2c326b0; 1 drivers +v0x29e1e90_0 .net "nS", 0 0, L_0x2c31bc0; 1 drivers +v0x29e07e0_0 .net "out0", 0 0, L_0x2c32030; 1 drivers +v0x29e0510_0 .net "out1", 0 0, L_0x2c32120; 1 drivers +v0x29e0260_0 .net "outfinal", 0 0, L_0x2c32210; 1 drivers +S_0x29cc240 .scope generate, "muxbits[2]" "muxbits[2]" 3 290, 3 290, S_0x29738d0; + .timescale -9 -12; +P_0x29bf438 .param/l "i" 3 290, +C4<010>; +L_0x2c34850/d .functor OR 1, L_0x2c35050, L_0x2c353d0, C4<0>, C4<0>; +L_0x2c34850 .delay (20000,20000,20000) L_0x2c34850/d; +v0x29ddaa0_0 .net *"_s15", 0 0, L_0x2c35050; 1 drivers +v0x29dca90_0 .net *"_s16", 0 0, L_0x2c353d0; 1 drivers +S_0x29d48d0 .scope module, "ZeroMux" "FourInMux" 3 292, 3 24, S_0x29cc240; + .timescale -9 -12; +L_0x2c32bd0/d .functor NOT 1, L_0x2c32ad0, C4<0>, C4<0>, C4<0>; +L_0x2c32bd0 .delay (10000,10000,10000) L_0x2c32bd0/d; +L_0x2c32cc0/d .functor NOT 1, L_0x2c33530, C4<0>, C4<0>, C4<0>; +L_0x2c32cc0 .delay (10000,10000,10000) L_0x2c32cc0/d; +L_0x2c32d60/d .functor NAND 1, L_0x2c32bd0, L_0x2c32cc0, L_0x2c333e0, C4<1>; +L_0x2c32d60 .delay (10000,10000,10000) L_0x2c32d60/d; +L_0x2c32ea0/d .functor NAND 1, L_0x2c32ad0, L_0x2c32cc0, L_0x2c33730, C4<1>; +L_0x2c32ea0 .delay (10000,10000,10000) L_0x2c32ea0/d; +L_0x2c32f90/d .functor NAND 1, L_0x2c32bd0, L_0x2c33530, L_0x2c33660, C4<1>; +L_0x2c32f90 .delay (10000,10000,10000) L_0x2c32f90/d; +L_0x2c33080/d .functor NAND 1, L_0x2c32ad0, L_0x2c33530, L_0x2c33900, C4<1>; +L_0x2c33080 .delay (10000,10000,10000) L_0x2c33080/d; +L_0x2c33160/d .functor NAND 1, L_0x2c32d60, L_0x2c32ea0, L_0x2c32f90, L_0x2c33080; +L_0x2c33160 .delay (10000,10000,10000) L_0x2c33160/d; +v0x29d7e90_0 .net "S0", 0 0, L_0x2c32ad0; 1 drivers +v0x29d7be0_0 .net "S1", 0 0, L_0x2c33530; 1 drivers +v0x29d7c80_0 .net "in0", 0 0, L_0x2c333e0; 1 drivers +v0x29d6c70_0 .net "in1", 0 0, L_0x2c33730; 1 drivers +v0x29d6cf0_0 .net "in2", 0 0, L_0x2c33660; 1 drivers +v0x29d69c0_0 .net "in3", 0 0, L_0x2c33900; 1 drivers +v0x29d6a60_0 .net "nS0", 0 0, L_0x2c32bd0; 1 drivers +v0x29da9a0_0 .net "nS1", 0 0, L_0x2c32cc0; 1 drivers +v0x29daa40_0 .net "out", 0 0, L_0x2c33160; 1 drivers +v0x29da6f0_0 .net "out0", 0 0, L_0x2c32d60; 1 drivers +v0x29da770_0 .net "out1", 0 0, L_0x2c32ea0; 1 drivers +v0x29ddcb0_0 .net "out2", 0 0, L_0x2c32f90; 1 drivers +v0x29dda00_0 .net "out3", 0 0, L_0x2c33080; 1 drivers +S_0x29ceac0 .scope module, "OneMux" "FourInMux" 3 293, 3 24, S_0x29cc240; + .timescale -9 -12; +L_0x2c337d0/d .functor NOT 1, L_0x2c342a0, C4<0>, C4<0>, C4<0>; +L_0x2c337d0 .delay (10000,10000,10000) L_0x2c337d0/d; +L_0x2c33b30/d .functor NOT 1, L_0x2c339f0, C4<0>, C4<0>, C4<0>; +L_0x2c33b30 .delay (10000,10000,10000) L_0x2c33b30/d; +L_0x2c33b90/d .functor NAND 1, L_0x2c337d0, L_0x2c33b30, L_0x2c34560, C4<1>; +L_0x2c33b90 .delay (10000,10000,10000) L_0x2c33b90/d; +L_0x2c33cd0/d .functor NAND 1, L_0x2c342a0, L_0x2c33b30, L_0x2c343d0, C4<1>; +L_0x2c33cd0 .delay (10000,10000,10000) L_0x2c33cd0/d; +L_0x2c33dc0/d .functor NAND 1, L_0x2c337d0, L_0x2c339f0, L_0x2c34710, C4<1>; +L_0x2c33dc0 .delay (10000,10000,10000) L_0x2c33dc0/d; +L_0x2c33eb0/d .functor NAND 1, L_0x2c342a0, L_0x2c339f0, L_0x2c34600, C4<1>; +L_0x2c33eb0 .delay (10000,10000,10000) L_0x2c33eb0/d; +L_0x2c33ff0/d .functor NAND 1, L_0x2c33b90, L_0x2c33cd0, L_0x2c33dc0, L_0x2c33eb0; +L_0x2c33ff0 .delay (10000,10000,10000) L_0x2c33ff0/d; +v0x29ce810_0 .net "S0", 0 0, L_0x2c342a0; 1 drivers +v0x29ce8b0_0 .net "S1", 0 0, L_0x2c339f0; 1 drivers +v0x29ce560_0 .net "in0", 0 0, L_0x2c34560; 1 drivers +v0x29ce600_0 .net "in1", 0 0, L_0x2c343d0; 1 drivers +v0x29d2070_0 .net "in2", 0 0, L_0x2c34710; 1 drivers +v0x29d2110_0 .net "in3", 0 0, L_0x2c34600; 1 drivers +v0x29d1e20_0 .net "nS0", 0 0, L_0x2c337d0; 1 drivers +v0x29d0e50_0 .net "nS1", 0 0, L_0x2c33b30; 1 drivers +v0x29d0ed0_0 .net "out", 0 0, L_0x2c33ff0; 1 drivers +v0x29d0ba0_0 .net "out0", 0 0, L_0x2c33b90; 1 drivers +v0x29d0c40_0 .net "out1", 0 0, L_0x2c33cd0; 1 drivers +v0x29ce2d0_0 .net "out2", 0 0, L_0x2c33dc0; 1 drivers +v0x29d4ba0_0 .net "out3", 0 0, L_0x2c33eb0; 1 drivers +S_0x29cbf90 .scope module, "TwoMux" "TwoInMux" 3 294, 3 8, S_0x29cc240; + .timescale -9 -12; +L_0x2c346a0/d .functor NOT 1, L_0x2c347b0, C4<0>, C4<0>, C4<0>; +L_0x2c346a0 .delay (10000,10000,10000) L_0x2c346a0/d; +L_0x2c34960/d .functor AND 1, L_0x2c34ee0, L_0x2c346a0, C4<1>, C4<1>; +L_0x2c34960 .delay (20000,20000,20000) L_0x2c34960/d; +L_0x2c34a50/d .functor AND 1, L_0x2c34db0, L_0x2c347b0, C4<1>, C4<1>; +L_0x2c34a50 .delay (20000,20000,20000) L_0x2c34a50/d; +L_0x2c34b40/d .functor OR 1, L_0x2c34960, L_0x2c34a50, C4<0>, C4<0>; +L_0x2c34b40 .delay (20000,20000,20000) L_0x2c34b40/d; +v0x29cb000_0 .net "S", 0 0, L_0x2c347b0; 1 drivers +v0x29cb0a0_0 .net "in0", 0 0, L_0x2c34ee0; 1 drivers +v0x29cad50_0 .net "in1", 0 0, L_0x2c34db0; 1 drivers +v0x29cadf0_0 .net "nS", 0 0, L_0x2c346a0; 1 drivers +v0x29c8450_0 .net "out0", 0 0, L_0x2c34960; 1 drivers +v0x29c84f0_0 .net "out1", 0 0, L_0x2c34a50; 1 drivers +v0x29cedd0_0 .net "outfinal", 0 0, L_0x2c34b40; 1 drivers +S_0x29bcfb0 .scope generate, "muxbits[3]" "muxbits[3]" 3 290, 3 290, S_0x29738d0; + .timescale -9 -12; +P_0x29ad608 .param/l "i" 3 290, +C4<011>; +L_0x2c37800/d .functor OR 1, L_0x2c37b80, L_0x2c37990, C4<0>, C4<0>; +L_0x2c37800 .delay (20000,20000,20000) L_0x2c37800/d; +v0x29c8a50_0 .net *"_s15", 0 0, L_0x2c37b80; 1 drivers +v0x29c8720_0 .net *"_s16", 0 0, L_0x2c37990; 1 drivers +S_0x29c51a0 .scope module, "ZeroMux" "FourInMux" 3 292, 3 24, S_0x29bcfb0; + .timescale -9 -12; +L_0x2c35280/d .functor NOT 1, L_0x2c35d50, C4<0>, C4<0>, C4<0>; +L_0x2c35280 .delay (10000,10000,10000) L_0x2c35280/d; +L_0x2c35370/d .functor NOT 1, L_0x2c35470, C4<0>, C4<0>, C4<0>; +L_0x2c35370 .delay (10000,10000,10000) L_0x2c35370/d; +L_0x2c35610/d .functor NAND 1, L_0x2c35280, L_0x2c35370, L_0x2c35ff0, C4<1>; +L_0x2c35610 .delay (10000,10000,10000) L_0x2c35610/d; +L_0x2c35750/d .functor NAND 1, L_0x2c35d50, L_0x2c35370, L_0x2c35e80, C4<1>; +L_0x2c35750 .delay (10000,10000,10000) L_0x2c35750/d; +L_0x2c35840/d .functor NAND 1, L_0x2c35280, L_0x2c35470, L_0x2c35f20, C4<1>; +L_0x2c35840 .delay (10000,10000,10000) L_0x2c35840/d; +L_0x2c35930/d .functor NAND 1, L_0x2c35d50, L_0x2c35470, L_0x2c36090, C4<1>; +L_0x2c35930 .delay (10000,10000,10000) L_0x2c35930/d; +L_0x2c35aa0/d .functor NAND 1, L_0x2c35610, L_0x2c35750, L_0x2c35840, L_0x2c35930; +L_0x2c35aa0 .delay (10000,10000,10000) L_0x2c35aa0/d; +v0x29c4ef0_0 .net "S0", 0 0, L_0x2c35d50; 1 drivers +v0x29c4f90_0 .net "S1", 0 0, L_0x2c35470; 1 drivers +v0x29c25f0_0 .net "in0", 0 0, L_0x2c35ff0; 1 drivers +v0x29c2690_0 .net "in1", 0 0, L_0x2c35e80; 1 drivers +v0x29caaa0_0 .net "in2", 0 0, L_0x2c35f20; 1 drivers +v0x29cab40_0 .net "in3", 0 0, L_0x2c36090; 1 drivers +v0x29ca810_0 .net "nS0", 0 0, L_0x2c35280; 1 drivers +v0x29ca540_0 .net "nS1", 0 0, L_0x2c35370; 1 drivers +v0x29ca5e0_0 .net "out", 0 0, L_0x2c35aa0; 1 drivers +v0x29c8f10_0 .net "out0", 0 0, L_0x2c35610; 1 drivers +v0x29c8fb0_0 .net "out1", 0 0, L_0x2c35750; 1 drivers +v0x29c8c60_0 .net "out2", 0 0, L_0x2c35840; 1 drivers +v0x29c89b0_0 .net "out3", 0 0, L_0x2c35930; 1 drivers +S_0x29c4990 .scope module, "OneMux" "FourInMux" 3 293, 3 24, S_0x29bcfb0; + .timescale -9 -12; +L_0x2c36180/d .functor NOT 1, L_0x2c36260, C4<0>, C4<0>, C4<0>; +L_0x2c36180 .delay (10000,10000,10000) L_0x2c36180/d; +L_0x2c36480/d .functor NOT 1, L_0x2c36da0, C4<0>, C4<0>, C4<0>; +L_0x2c36480 .delay (10000,10000,10000) L_0x2c36480/d; +L_0x2c36520/d .functor NAND 1, L_0x2c36180, L_0x2c36480, L_0x2c36c00, C4<1>; +L_0x2c36520 .delay (10000,10000,10000) L_0x2c36520/d; +L_0x2c36660/d .functor NAND 1, L_0x2c36260, L_0x2c36480, L_0x2c36ca0, C4<1>; +L_0x2c36660 .delay (10000,10000,10000) L_0x2c36660/d; +L_0x2c36750/d .functor NAND 1, L_0x2c36180, L_0x2c36da0, L_0x2c37090, C4<1>; +L_0x2c36750 .delay (10000,10000,10000) L_0x2c36750/d; +L_0x2c36840/d .functor NAND 1, L_0x2c36260, L_0x2c36da0, L_0x2c37130, C4<1>; +L_0x2c36840 .delay (10000,10000,10000) L_0x2c36840/d; +L_0x2c36950/d .functor NAND 1, L_0x2c36520, L_0x2c36660, L_0x2c36750, L_0x2c36840; +L_0x2c36950 .delay (10000,10000,10000) L_0x2c36950/d; +v0x29c4ce0_0 .net "S0", 0 0, L_0x2c36260; 1 drivers +v0x29c46e0_0 .net "S1", 0 0, L_0x2c36da0; 1 drivers +v0x29c4760_0 .net "in0", 0 0, L_0x2c36c00; 1 drivers +v0x29c30b0_0 .net "in1", 0 0, L_0x2c36ca0; 1 drivers +v0x29c3150_0 .net "in2", 0 0, L_0x2c37090; 1 drivers +v0x29c2e00_0 .net "in3", 0 0, L_0x2c37130; 1 drivers +v0x29c2ea0_0 .net "nS0", 0 0, L_0x2c36180; 1 drivers +v0x29c2b70_0 .net "nS1", 0 0, L_0x2c36480; 1 drivers +v0x29c28a0_0 .net "out", 0 0, L_0x2c36950; 1 drivers +v0x29c2940_0 .net "out0", 0 0, L_0x2c36520; 1 drivers +v0x29c63e0_0 .net "out1", 0 0, L_0x2c36660; 1 drivers +v0x29c6480_0 .net "out2", 0 0, L_0x2c36750; 1 drivers +v0x29c61c0_0 .net "out3", 0 0, L_0x2c36840; 1 drivers +S_0x29c0570 .scope module, "TwoMux" "TwoInMux" 3 294, 3 8, S_0x29bcfb0; + .timescale -9 -12; +L_0x2c36ed0/d .functor NOT 1, L_0x2c376c0, C4<0>, C4<0>, C4<0>; +L_0x2c36ed0 .delay (10000,10000,10000) L_0x2c36ed0/d; +L_0x2c36fc0/d .functor AND 1, L_0x2c371d0, L_0x2c36ed0, C4<1>, C4<1>; +L_0x2c36fc0 .delay (20000,20000,20000) L_0x2c36fc0/d; +L_0x2c373f0/d .functor AND 1, L_0x2c372c0, L_0x2c376c0, C4<1>, C4<1>; +L_0x2c373f0 .delay (20000,20000,20000) L_0x2c373f0/d; +L_0x2c374e0/d .functor OR 1, L_0x2c36fc0, L_0x2c373f0, C4<0>, C4<0>; +L_0x2c374e0 .delay (20000,20000,20000) L_0x2c374e0/d; +v0x29c02c0_0 .net "S", 0 0, L_0x2c376c0; 1 drivers +v0x29c0360_0 .net "in0", 0 0, L_0x2c371d0; 1 drivers +v0x29c0010_0 .net "in1", 0 0, L_0x2c372c0; 1 drivers +v0x29c00b0_0 .net "nS", 0 0, L_0x2c36ed0; 1 drivers +v0x29bf370_0 .net "out0", 0 0, L_0x2c36fc0; 1 drivers +v0x29bf0a0_0 .net "out1", 0 0, L_0x2c373f0; 1 drivers +v0x29c4c40_0 .net "outfinal", 0 0, L_0x2c374e0; 1 drivers +S_0x29ad350 .scope generate, "muxbits[4]" "muxbits[4]" 3 290, 3 290, S_0x29738d0; + .timescale -9 -12; +P_0x299f938 .param/l "i" 3 290, +C4<0100>; +L_0x2c34f80/d .functor OR 1, L_0x2c3a150, L_0x2c3a330, C4<0>, C4<0>; +L_0x2c34f80 .delay (20000,20000,20000) L_0x2c34f80/d; +v0x29b9320_0 .net *"_s15", 0 0, L_0x2c3a150; 1 drivers +v0x29bd260_0 .net *"_s16", 0 0, L_0x2c3a330; 1 drivers +S_0x29b4680 .scope module, "ZeroMux" "FourInMux" 3 292, 3 24, S_0x29ad350; + .timescale -9 -12; +L_0x2c37a80/d .functor NOT 1, L_0x2c37c20, C4<0>, C4<0>, C4<0>; +L_0x2c37a80 .delay (10000,10000,10000) L_0x2c37a80/d; +L_0x2c37e20/d .functor NOT 1, L_0x2c37d50, C4<0>, C4<0>, C4<0>; +L_0x2c37e20 .delay (10000,10000,10000) L_0x2c37e20/d; +L_0x2c37e80/d .functor NAND 1, L_0x2c37a80, L_0x2c37e20, L_0x2c38560, C4<1>; +L_0x2c37e80 .delay (10000,10000,10000) L_0x2c37e80/d; +L_0x2c37fc0/d .functor NAND 1, L_0x2c37c20, L_0x2c37e20, L_0x2c38600, C4<1>; +L_0x2c37fc0 .delay (10000,10000,10000) L_0x2c37fc0/d; +L_0x2c380b0/d .functor NAND 1, L_0x2c37a80, L_0x2c37d50, L_0x2c386a0, C4<1>; +L_0x2c380b0 .delay (10000,10000,10000) L_0x2c380b0/d; +L_0x2c381a0/d .functor NAND 1, L_0x2c37c20, L_0x2c37d50, L_0x2c38a80, C4<1>; +L_0x2c381a0 .delay (10000,10000,10000) L_0x2c381a0/d; +L_0x2c382b0/d .functor NAND 1, L_0x2c37e80, L_0x2c37fc0, L_0x2c380b0, L_0x2c381a0; +L_0x2c382b0 .delay (10000,10000,10000) L_0x2c382b0/d; +v0x29b3710_0 .net "S0", 0 0, L_0x2c37c20; 1 drivers +v0x29b3460_0 .net "S1", 0 0, L_0x2c37d50; 1 drivers +v0x29b3500_0 .net "in0", 0 0, L_0x2c38560; 1 drivers +v0x29b7440_0 .net "in1", 0 0, L_0x2c38600; 1 drivers +v0x29b74c0_0 .net "in2", 0 0, L_0x2c386a0; 1 drivers +v0x29b7190_0 .net "in3", 0 0, L_0x2c38a80; 1 drivers +v0x29b7230_0 .net "nS0", 0 0, L_0x2c37a80; 1 drivers +v0x29ba750_0 .net "nS1", 0 0, L_0x2c37e20; 1 drivers +v0x29ba7f0_0 .net "out", 0 0, L_0x2c382b0; 1 drivers +v0x29ba4a0_0 .net "out0", 0 0, L_0x2c37e80; 1 drivers +v0x29ba520_0 .net "out1", 0 0, L_0x2c37fc0; 1 drivers +v0x29b9530_0 .net "out2", 0 0, L_0x2c380b0; 1 drivers +v0x29b9280_0 .net "out3", 0 0, L_0x2c381a0; 1 drivers +S_0x29aafb0 .scope module, "OneMux" "FourInMux" 3 293, 3 24, S_0x29ad350; + .timescale -9 -12; +L_0x2c38800/d .functor NOT 1, L_0x2c393f0, C4<0>, C4<0>, C4<0>; +L_0x2c38800 .delay (10000,10000,10000) L_0x2c38800/d; +L_0x2c388f0/d .functor NOT 1, L_0x2c38b70, C4<0>, C4<0>, C4<0>; +L_0x2c388f0 .delay (10000,10000,10000) L_0x2c388f0/d; +L_0x2c38990/d .functor NAND 1, L_0x2c38800, L_0x2c388f0, L_0x2c38ca0, C4<1>; +L_0x2c38990 .delay (10000,10000,10000) L_0x2c38990/d; +L_0x2c38e50/d .functor NAND 1, L_0x2c393f0, L_0x2c388f0, L_0x2c39780, C4<1>; +L_0x2c38e50 .delay (10000,10000,10000) L_0x2c38e50/d; +L_0x2c38f40/d .functor NAND 1, L_0x2c38800, L_0x2c38b70, L_0x2c39820, C4<1>; +L_0x2c38f40 .delay (10000,10000,10000) L_0x2c38f40/d; +L_0x2c39030/d .functor NAND 1, L_0x2c393f0, L_0x2c38b70, L_0x2c39520, C4<1>; +L_0x2c39030 .delay (10000,10000,10000) L_0x2c39030/d; +L_0x2c39140/d .functor NAND 1, L_0x2c38990, L_0x2c38e50, L_0x2c38f40, L_0x2c39030; +L_0x2c39140 .delay (10000,10000,10000) L_0x2c39140/d; +v0x29aeaf0_0 .net "S0", 0 0, L_0x2c393f0; 1 drivers +v0x29aeb90_0 .net "S1", 0 0, L_0x2c38b70; 1 drivers +v0x29ae840_0 .net "in0", 0 0, L_0x2c38ca0; 1 drivers +v0x29ae8e0_0 .net "in1", 0 0, L_0x2c39780; 1 drivers +v0x29ad8b0_0 .net "in2", 0 0, L_0x2c39820; 1 drivers +v0x29ad950_0 .net "in3", 0 0, L_0x2c39520; 1 drivers +v0x29ad660_0 .net "nS0", 0 0, L_0x2c38800; 1 drivers +v0x29aad00_0 .net "nS1", 0 0, L_0x2c388f0; 1 drivers +v0x29aad80_0 .net "out", 0 0, L_0x2c39140; 1 drivers +v0x29b1620_0 .net "out0", 0 0, L_0x2c38990; 1 drivers +v0x29b16c0_0 .net "out1", 0 0, L_0x2c38e50; 1 drivers +v0x29b1390_0 .net "out2", 0 0, L_0x2c38f40; 1 drivers +v0x29b4950_0 .net "out3", 0 0, L_0x2c39030; 1 drivers +S_0x29ad0a0 .scope module, "TwoMux" "TwoInMux" 3 294, 3 8, S_0x29ad350; + .timescale -9 -12; +L_0x2c39610/d .functor NOT 1, L_0x2c398c0, C4<0>, C4<0>, C4<0>; +L_0x2c39610 .delay (10000,10000,10000) L_0x2c39610/d; +L_0x2c39700/d .functor AND 1, L_0x2c39960, L_0x2c39610, C4<1>, C4<1>; +L_0x2c39700 .delay (20000,20000,20000) L_0x2c39700/d; +L_0x2c39bc0/d .functor AND 1, L_0x2c39a50, L_0x2c398c0, C4<1>, C4<1>; +L_0x2c39bc0 .delay (20000,20000,20000) L_0x2c39bc0/d; +L_0x2c39cb0/d .functor OR 1, L_0x2c39700, L_0x2c39bc0, C4<0>, C4<0>; +L_0x2c39cb0 .delay (20000,20000,20000) L_0x2c39cb0/d; +v0x29acdf0_0 .net "S", 0 0, L_0x2c398c0; 1 drivers +v0x29ace90_0 .net "in0", 0 0, L_0x2c39960; 1 drivers +v0x29ab7c0_0 .net "in1", 0 0, L_0x2c39a50; 1 drivers +v0x29ab860_0 .net "nS", 0 0, L_0x2c39610; 1 drivers +v0x29ab510_0 .net "out0", 0 0, L_0x2c39700; 1 drivers +v0x29ab5b0_0 .net "out1", 0 0, L_0x2c39bc0; 1 drivers +v0x29ab2c0_0 .net "outfinal", 0 0, L_0x2c39cb0; 1 drivers +S_0x29a1690 .scope generate, "muxbits[5]" "muxbits[5]" 3 290, 3 290, S_0x29738d0; + .timescale -9 -12; +P_0x2990198 .param/l "i" 3 290, +C4<0101>; +L_0x2c3c500/d .functor OR 1, L_0x2c3cd80, L_0x2c3c9a0, C4<0>, C4<0>; +L_0x2c3c500 .delay (20000,20000,20000) L_0x2c3c500/d; +v0x29a7840_0 .net *"_s15", 0 0, L_0x2c3cd80; 1 drivers +v0x29a4ec0_0 .net *"_s16", 0 0, L_0x2c3c9a0; 1 drivers +S_0x29a6f90 .scope module, "ZeroMux" "FourInMux" 3 292, 3 24, S_0x29a1690; + .timescale -9 -12; +L_0x2c3a420/d .functor NOT 1, L_0x2c3af90, C4<0>, C4<0>, C4<0>; +L_0x2c3a420 .delay (10000,10000,10000) L_0x2c3a420/d; +L_0x2c3a4d0/d .functor NOT 1, L_0x2c3a6d0, C4<0>, C4<0>, C4<0>; +L_0x2c3a4d0 .delay (10000,10000,10000) L_0x2c3a4d0/d; +L_0x2c3a530/d .functor NAND 1, L_0x2c3a420, L_0x2c3a4d0, L_0x2c3a800, C4<1>; +L_0x2c3a530 .delay (10000,10000,10000) L_0x2c3a530/d; +L_0x2c3aa20/d .functor NAND 1, L_0x2c3af90, L_0x2c3a4d0, L_0x2c3a8a0, C4<1>; +L_0x2c3aa20 .delay (10000,10000,10000) L_0x2c3aa20/d; +L_0x2c3ab10/d .functor NAND 1, L_0x2c3a420, L_0x2c3a6d0, L_0x2c3b390, C4<1>; +L_0x2c3ab10 .delay (10000,10000,10000) L_0x2c3ab10/d; +L_0x2c3ac00/d .functor NAND 1, L_0x2c3af90, L_0x2c3a6d0, L_0x2c3b0c0, C4<1>; +L_0x2c3ac00 .delay (10000,10000,10000) L_0x2c3ac00/d; +L_0x2c3ace0/d .functor NAND 1, L_0x2c3a530, L_0x2c3aa20, L_0x2c3ab10, L_0x2c3ac00; +L_0x2c3ace0 .delay (10000,10000,10000) L_0x2c3ace0/d; +v0x29a5960_0 .net "S0", 0 0, L_0x2c3af90; 1 drivers +v0x29a5a00_0 .net "S1", 0 0, L_0x2c3a6d0; 1 drivers +v0x29a56b0_0 .net "in0", 0 0, L_0x2c3a800; 1 drivers +v0x29a5750_0 .net "in1", 0 0, L_0x2c3a8a0; 1 drivers +v0x29a5400_0 .net "in2", 0 0, L_0x2c3b390; 1 drivers +v0x29a54a0_0 .net "in3", 0 0, L_0x2c3b0c0; 1 drivers +v0x29a5170_0 .net "nS0", 0 0, L_0x2c3a420; 1 drivers +v0x29a8c90_0 .net "nS1", 0 0, L_0x2c3a4d0; 1 drivers +v0x29a8d30_0 .net "out", 0 0, L_0x2c3ace0; 1 drivers +v0x29a89e0_0 .net "out0", 0 0, L_0x2c3a530; 1 drivers +v0x29a8a80_0 .net "out1", 0 0, L_0x2c3aa20; 1 drivers +v0x29a7a50_0 .net "out2", 0 0, L_0x2c3ab10; 1 drivers +v0x29a77a0_0 .net "out3", 0 0, L_0x2c3ac00; 1 drivers +S_0x29a2e30 .scope module, "OneMux" "FourInMux" 3 293, 3 24, S_0x29a1690; + .timescale -9 -12; +L_0x2c3b1b0/d .functor NOT 1, L_0x2c3b480, C4<0>, C4<0>, C4<0>; +L_0x2c3b1b0 .delay (10000,10000,10000) L_0x2c3b1b0/d; +L_0x2c3b260/d .functor NOT 1, L_0x2c3b5b0, C4<0>, C4<0>, C4<0>; +L_0x2c3b260 .delay (10000,10000,10000) L_0x2c3b260/d; +L_0x2c3b300/d .functor NAND 1, L_0x2c3b1b0, L_0x2c3b260, L_0x2c3c140, C4<1>; +L_0x2c3b300 .delay (10000,10000,10000) L_0x2c3b300/d; +L_0x2c3b840/d .functor NAND 1, L_0x2c3b480, L_0x2c3b260, L_0x2c3c1e0, C4<1>; +L_0x2c3b840 .delay (10000,10000,10000) L_0x2c3b840/d; +L_0x2c3b930/d .functor NAND 1, L_0x2c3b1b0, L_0x2c3b5b0, L_0x2c3be40, C4<1>; +L_0x2c3b930 .delay (10000,10000,10000) L_0x2c3b930/d; +L_0x2c3ba20/d .functor NAND 1, L_0x2c3b480, L_0x2c3b5b0, L_0x2c3bf30, C4<1>; +L_0x2c3ba20 .delay (10000,10000,10000) L_0x2c3ba20/d; +L_0x2c3bb90/d .functor NAND 1, L_0x2c3b300, L_0x2c3b840, L_0x2c3b930, L_0x2c3ba20; +L_0x2c3bb90 .delay (10000,10000,10000) L_0x2c3bb90/d; +v0x299f390_0 .net "S0", 0 0, L_0x2c3b480; 1 drivers +v0x29a2b80_0 .net "S1", 0 0, L_0x2c3b5b0; 1 drivers +v0x29a2c00_0 .net "in0", 0 0, L_0x2c3c140; 1 drivers +v0x29a1bf0_0 .net "in1", 0 0, L_0x2c3c1e0; 1 drivers +v0x29a1c90_0 .net "in2", 0 0, L_0x2c3be40; 1 drivers +v0x29a1940_0 .net "in3", 0 0, L_0x2c3bf30; 1 drivers +v0x29a19e0_0 .net "nS0", 0 0, L_0x2c3b1b0; 1 drivers +v0x299f060_0 .net "nS1", 0 0, L_0x2c3b260; 1 drivers +v0x299eda0_0 .net "out", 0 0, L_0x2c3bb90; 1 drivers +v0x299ee40_0 .net "out0", 0 0, L_0x2c3b300; 1 drivers +v0x29a74f0_0 .net "out1", 0 0, L_0x2c3b840; 1 drivers +v0x29a7590_0 .net "out2", 0 0, L_0x2c3b930; 1 drivers +v0x29a72d0_0 .net "out3", 0 0, L_0x2c3ba20; 1 drivers +S_0x29a13e0 .scope module, "TwoMux" "TwoInMux" 3 294, 3 8, S_0x29a1690; + .timescale -9 -12; +L_0x2c3c020/d .functor NOT 1, L_0x2c3c900, C4<0>, C4<0>, C4<0>; +L_0x2c3c020 .delay (10000,10000,10000) L_0x2c3c020/d; +L_0x2c3b6e0/d .functor AND 1, L_0x2c3c280, L_0x2c3c020, C4<1>, C4<1>; +L_0x2c3b6e0 .delay (20000,20000,20000) L_0x2c3b6e0/d; +L_0x2c3c630/d .functor AND 1, L_0x2c3c370, L_0x2c3c900, C4<1>, C4<1>; +L_0x2c3c630 .delay (20000,20000,20000) L_0x2c3c630/d; +L_0x2c3c720/d .functor OR 1, L_0x2c3b6e0, L_0x2c3c630, C4<0>, C4<0>; +L_0x2c3c720 .delay (20000,20000,20000) L_0x2c3c720/d; +v0x29a1130_0 .net "S", 0 0, L_0x2c3c900; 1 drivers +v0x29a11d0_0 .net "in0", 0 0, L_0x2c3c280; 1 drivers +v0x299fb00_0 .net "in1", 0 0, L_0x2c3c370; 1 drivers +v0x299fba0_0 .net "nS", 0 0, L_0x2c3c020; 1 drivers +v0x299f870_0 .net "out0", 0 0, L_0x2c3b6e0; 1 drivers +v0x299f5a0_0 .net "out1", 0 0, L_0x2c3c630; 1 drivers +v0x299f2f0_0 .net "outfinal", 0 0, L_0x2c3c720; 1 drivers +S_0x298b2c0 .scope generate, "muxbits[6]" "muxbits[6]" 3 290, 3 290, S_0x29738d0; + .timescale -9 -12; +P_0x297e538 .param/l "i" 3 290, +C4<0110>; +L_0x2c3ea80/d .functor OR 1, L_0x2c3f550, L_0x2c3f5f0, C4<0>, C4<0>; +L_0x2c3ea80 .delay (20000,20000,20000) L_0x2c3ea80/d; +v0x299be70_0 .net *"_s15", 0 0, L_0x2c3f550; 1 drivers +v0x299bb20_0 .net *"_s16", 0 0, L_0x2c3f5f0; 1 drivers +S_0x29971d0 .scope module, "ZeroMux" "FourInMux" 3 292, 3 24, S_0x298b2c0; + .timescale -9 -12; +L_0x2c3ca90/d .functor NOT 1, L_0x2c3ce20, C4<0>, C4<0>, C4<0>; +L_0x2c3ca90 .delay (10000,10000,10000) L_0x2c3ca90/d; +L_0x2c3cb80/d .functor NOT 1, L_0x2c3cf50, C4<0>, C4<0>, C4<0>; +L_0x2c3cb80 .delay (10000,10000,10000) L_0x2c3cb80/d; +L_0x2c3cc20/d .functor NAND 1, L_0x2c3ca90, L_0x2c3cb80, L_0x2c3d080, C4<1>; +L_0x2c3cc20 .delay (10000,10000,10000) L_0x2c3cc20/d; +L_0x2c3d200/d .functor NAND 1, L_0x2c3ce20, L_0x2c3cb80, L_0x2c3db10, C4<1>; +L_0x2c3d200 .delay (10000,10000,10000) L_0x2c3d200/d; +L_0x2c3d2f0/d .functor NAND 1, L_0x2c3ca90, L_0x2c3cf50, L_0x2c3d7a0, C4<1>; +L_0x2c3d2f0 .delay (10000,10000,10000) L_0x2c3d2f0/d; +L_0x2c3d3e0/d .functor NAND 1, L_0x2c3ce20, L_0x2c3cf50, L_0x2c3d840, C4<1>; +L_0x2c3d3e0 .delay (10000,10000,10000) L_0x2c3d3e0/d; +L_0x2c3d4f0/d .functor NAND 1, L_0x2c3cc20, L_0x2c3d200, L_0x2c3d2f0, L_0x2c3d3e0; +L_0x2c3d4f0 .delay (10000,10000,10000) L_0x2c3d4f0/d; +v0x2996f20_0 .net "S0", 0 0, L_0x2c3ce20; 1 drivers +v0x2995fb0_0 .net "S1", 0 0, L_0x2c3cf50; 1 drivers +v0x2996050_0 .net "in0", 0 0, L_0x2c3d080; 1 drivers +v0x2995d00_0 .net "in1", 0 0, L_0x2c3db10; 1 drivers +v0x2995d80_0 .net "in2", 0 0, L_0x2c3d7a0; 1 drivers +v0x2999ce0_0 .net "in3", 0 0, L_0x2c3d840; 1 drivers +v0x2999d80_0 .net "nS0", 0 0, L_0x2c3ca90; 1 drivers +v0x2999a30_0 .net "nS1", 0 0, L_0x2c3cb80; 1 drivers +v0x2999ad0_0 .net "out", 0 0, L_0x2c3d4f0; 1 drivers +v0x299cff0_0 .net "out0", 0 0, L_0x2c3cc20; 1 drivers +v0x299d070_0 .net "out1", 0 0, L_0x2c3d200; 1 drivers +v0x299cd40_0 .net "out2", 0 0, L_0x2c3d2f0; 1 drivers +v0x299bdd0_0 .net "out3", 0 0, L_0x2c3d3e0; 1 drivers +S_0x298db40 .scope module, "OneMux" "FourInMux" 3 293, 3 24, S_0x298b2c0; + .timescale -9 -12; +L_0x2c3d930/d .functor NOT 1, L_0x2c3e630, C4<0>, C4<0>, C4<0>; +L_0x2c3d930 .delay (10000,10000,10000) L_0x2c3d930/d; +L_0x2c3da20/d .functor NOT 1, L_0x2c3dbb0, C4<0>, C4<0>, C4<0>; +L_0x2c3da20 .delay (10000,10000,10000) L_0x2c3da20/d; +L_0x2c3df40/d .functor NAND 1, L_0x2c3d930, L_0x2c3da20, L_0x2c3dce0, C4<1>; +L_0x2c3df40 .delay (10000,10000,10000) L_0x2c3df40/d; +L_0x2c3e030/d .functor NAND 1, L_0x2c3e630, L_0x2c3da20, L_0x2c3dd80, C4<1>; +L_0x2c3e030 .delay (10000,10000,10000) L_0x2c3e030/d; +L_0x2c3e120/d .functor NAND 1, L_0x2c3d930, L_0x2c3dbb0, L_0x2c3de20, C4<1>; +L_0x2c3e120 .delay (10000,10000,10000) L_0x2c3e120/d; +L_0x2c3e210/d .functor NAND 1, L_0x2c3e630, L_0x2c3dbb0, L_0x2c3eb20, C4<1>; +L_0x2c3e210 .delay (10000,10000,10000) L_0x2c3e210/d; +L_0x2c3e380/d .functor NAND 1, L_0x2c3df40, L_0x2c3e030, L_0x2c3e120, L_0x2c3e210; +L_0x2c3e380 .delay (10000,10000,10000) L_0x2c3e380/d; +v0x298d890_0 .net "S0", 0 0, L_0x2c3e630; 1 drivers +v0x298d930_0 .net "S1", 0 0, L_0x2c3dbb0; 1 drivers +v0x29913b0_0 .net "in0", 0 0, L_0x2c3dce0; 1 drivers +v0x2991450_0 .net "in1", 0 0, L_0x2c3dd80; 1 drivers +v0x2991100_0 .net "in2", 0 0, L_0x2c3de20; 1 drivers +v0x29911a0_0 .net "in3", 0 0, L_0x2c3eb20; 1 drivers +v0x29901f0_0 .net "nS0", 0 0, L_0x2c3d930; 1 drivers +v0x298fee0_0 .net "nS1", 0 0, L_0x2c3da20; 1 drivers +v0x298ff60_0 .net "out", 0 0, L_0x2c3e380; 1 drivers +v0x298d5e0_0 .net "out0", 0 0, L_0x2c3df40; 1 drivers +v0x298d680_0 .net "out1", 0 0, L_0x2c3e030; 1 drivers +v0x2993ee0_0 .net "out2", 0 0, L_0x2c3e120; 1 drivers +v0x2993c30_0 .net "out3", 0 0, L_0x2c3e210; 1 drivers +S_0x298a330 .scope module, "TwoMux" "TwoInMux" 3 294, 3 8, S_0x298b2c0; + .timescale -9 -12; +L_0x2c3ec10/d .functor NOT 1, L_0x2c3e760, C4<0>, C4<0>, C4<0>; +L_0x2c3ec10 .delay (10000,10000,10000) L_0x2c3ec10/d; +L_0x2c3ed00/d .functor AND 1, L_0x2c3e800, L_0x2c3ec10, C4<1>, C4<1>; +L_0x2c3ed00 .delay (20000,20000,20000) L_0x2c3ed00/d; +L_0x2c3edf0/d .functor AND 1, L_0x2c3e8f0, L_0x2c3e760, C4<1>, C4<1>; +L_0x2c3edf0 .delay (20000,20000,20000) L_0x2c3edf0/d; +L_0x2c3eee0/d .functor OR 1, L_0x2c3ed00, L_0x2c3edf0, C4<0>, C4<0>; +L_0x2c3eee0 .delay (20000,20000,20000) L_0x2c3eee0/d; +v0x298a080_0 .net "S", 0 0, L_0x2c3e760; 1 drivers +v0x298a120_0 .net "in0", 0 0, L_0x2c3e800; 1 drivers +v0x2987780_0 .net "in1", 0 0, L_0x2c3e8f0; 1 drivers +v0x2987820_0 .net "nS", 0 0, L_0x2c3ec10; 1 drivers +v0x298e0a0_0 .net "out0", 0 0, L_0x2c3ed00; 1 drivers +v0x298e140_0 .net "out1", 0 0, L_0x2c3edf0; 1 drivers +v0x298de50_0 .net "outfinal", 0 0, L_0x2c3eee0; 1 drivers +S_0x297f8c0 .scope generate, "muxbits[7]" "muxbits[7]" 3 290, 3 290, S_0x29738d0; + .timescale -9 -12; +P_0x296a708 .param/l "i" 3 290, +C4<0111>; +L_0x2c41410/d .functor OR 1, L_0x2c41550, L_0x2c41b90, C4<0>, C4<0>; +L_0x2c41410 .delay (20000,20000,20000) L_0x2c41410/d; +v0x2987ad0_0 .net *"_s15", 0 0, L_0x2c41550; 1 drivers +v0x298b590_0 .net *"_s16", 0 0, L_0x2c41b90; 1 drivers +S_0x2984220 .scope module, "ZeroMux" "FourInMux" 3 292, 3 24, S_0x297f8c0; + .timescale -9 -12; +L_0x2c31d60/d .functor NOT 1, L_0x2c3fdd0, C4<0>, C4<0>, C4<0>; +L_0x2c31d60 .delay (10000,10000,10000) L_0x2c31d60/d; +L_0x2c3f0c0/d .functor NOT 1, L_0x2c3f6e0, C4<0>, C4<0>, C4<0>; +L_0x2c3f0c0 .delay (10000,10000,10000) L_0x2c3f0c0/d; +L_0x2c3f120/d .functor NAND 1, L_0x2c31d60, L_0x2c3f0c0, L_0x2c3f810, C4<1>; +L_0x2c3f120 .delay (10000,10000,10000) L_0x2c3f120/d; +L_0x2c3f220/d .functor NAND 1, L_0x2c3fdd0, L_0x2c3f0c0, L_0x2c3f8b0, C4<1>; +L_0x2c3f220 .delay (10000,10000,10000) L_0x2c3f220/d; +L_0x2c3f2d0/d .functor NAND 1, L_0x2c31d60, L_0x2c3f6e0, L_0x2c3f950, C4<1>; +L_0x2c3f2d0 .delay (10000,10000,10000) L_0x2c3f2d0/d; +L_0x2c3f3c0/d .functor NAND 1, L_0x2c3fdd0, L_0x2c3f6e0, L_0x2c3fa40, C4<1>; +L_0x2c3f3c0 .delay (10000,10000,10000) L_0x2c3f3c0/d; +L_0x2c3fb20/d .functor NAND 1, L_0x2c3f120, L_0x2c3f220, L_0x2c3f2d0, L_0x2c3f3c0; +L_0x2c3fb20 .delay (10000,10000,10000) L_0x2c3fb20/d; +v0x2981920_0 .net "S0", 0 0, L_0x2c3fdd0; 1 drivers +v0x29819c0_0 .net "S1", 0 0, L_0x2c3f6e0; 1 drivers +v0x2989dd0_0 .net "in0", 0 0, L_0x2c3f810; 1 drivers +v0x2989e70_0 .net "in1", 0 0, L_0x2c3f8b0; 1 drivers +v0x2989b20_0 .net "in2", 0 0, L_0x2c3f950; 1 drivers +v0x2989bc0_0 .net "in3", 0 0, L_0x2c3fa40; 1 drivers +v0x2989890_0 .net "nS0", 0 0, L_0x2c31d60; 1 drivers +v0x2988240_0 .net "nS1", 0 0, L_0x2c3f0c0; 1 drivers +v0x29882e0_0 .net "out", 0 0, L_0x2c3fb20; 1 drivers +v0x2987f90_0 .net "out0", 0 0, L_0x2c3f120; 1 drivers +v0x2988030_0 .net "out1", 0 0, L_0x2c3f220; 1 drivers +v0x2987ce0_0 .net "out2", 0 0, L_0x2c3f2d0; 1 drivers +v0x2987a30_0 .net "out3", 0 0, L_0x2c3f3c0; 1 drivers +S_0x2983a10 .scope module, "OneMux" "FourInMux" 3 293, 3 24, S_0x297f8c0; + .timescale -9 -12; +L_0x2c40380/d .functor NOT 1, L_0x2c3ff00, C4<0>, C4<0>, C4<0>; +L_0x2c40380 .delay (10000,10000,10000) L_0x2c40380/d; +L_0x2c40430/d .functor NOT 1, L_0x2c40030, C4<0>, C4<0>, C4<0>; +L_0x2c40430 .delay (10000,10000,10000) L_0x2c40430/d; +L_0x2c404d0/d .functor NAND 1, L_0x2c40380, L_0x2c40430, L_0x2c40160, C4<1>; +L_0x2c404d0 .delay (10000,10000,10000) L_0x2c404d0/d; +L_0x2c40610/d .functor NAND 1, L_0x2c3ff00, L_0x2c40430, L_0x2c40200, C4<1>; +L_0x2c40610 .delay (10000,10000,10000) L_0x2c40610/d; +L_0x2c40700/d .functor NAND 1, L_0x2c40380, L_0x2c40030, L_0x2c410a0, C4<1>; +L_0x2c40700 .delay (10000,10000,10000) L_0x2c40700/d; +L_0x2c40820/d .functor NAND 1, L_0x2c3ff00, L_0x2c40030, L_0x2c41140, C4<1>; +L_0x2c40820 .delay (10000,10000,10000) L_0x2c40820/d; +L_0x2c40990/d .functor NAND 1, L_0x2c404d0, L_0x2c40610, L_0x2c40700, L_0x2c40820; +L_0x2c40990 .delay (10000,10000,10000) L_0x2c40990/d; +v0x2983d60_0 .net "S0", 0 0, L_0x2c3ff00; 1 drivers +v0x29823e0_0 .net "S1", 0 0, L_0x2c40030; 1 drivers +v0x2982460_0 .net "in0", 0 0, L_0x2c40160; 1 drivers +v0x2982130_0 .net "in1", 0 0, L_0x2c40200; 1 drivers +v0x29821d0_0 .net "in2", 0 0, L_0x2c410a0; 1 drivers +v0x2981e80_0 .net "in3", 0 0, L_0x2c41140; 1 drivers +v0x2981f20_0 .net "nS0", 0 0, L_0x2c40380; 1 drivers +v0x2981bf0_0 .net "nS1", 0 0, L_0x2c40430; 1 drivers +v0x2985710_0 .net "out", 0 0, L_0x2c40990; 1 drivers +v0x29857b0_0 .net "out0", 0 0, L_0x2c404d0; 1 drivers +v0x2985460_0 .net "out1", 0 0, L_0x2c40610; 1 drivers +v0x2985500_0 .net "out2", 0 0, L_0x2c40700; 1 drivers +v0x2984560_0 .net "out3", 0 0, L_0x2c40820; 1 drivers +S_0x297f610 .scope module, "TwoMux" "TwoInMux" 3 294, 3 8, S_0x297f8c0; + .timescale -9 -12; +L_0x2c408b0/d .functor NOT 1, L_0x2c41650, C4<0>, C4<0>, C4<0>; +L_0x2c408b0 .delay (10000,10000,10000) L_0x2c408b0/d; +L_0x2c40c90/d .functor AND 1, L_0x2c411e0, L_0x2c408b0, C4<1>, C4<1>; +L_0x2c40c90 .delay (20000,20000,20000) L_0x2c40c90/d; +L_0x2c40d80/d .functor AND 1, L_0x2c41280, L_0x2c41650, C4<1>, C4<1>; +L_0x2c40d80 .delay (20000,20000,20000) L_0x2c40d80/d; +L_0x2c40e70/d .functor OR 1, L_0x2c40c90, L_0x2c40d80, C4<0>, C4<0>; +L_0x2c40e70 .delay (20000,20000,20000) L_0x2c40e70/d; +v0x297f380_0 .net "S", 0 0, L_0x2c41650; 1 drivers +v0x297f420_0 .net "in0", 0 0, L_0x2c411e0; 1 drivers +v0x297e6e0_0 .net "in1", 0 0, L_0x2c41280; 1 drivers +v0x297e780_0 .net "nS", 0 0, L_0x2c408b0; 1 drivers +v0x297e470_0 .net "out0", 0 0, L_0x2c40c90; 1 drivers +v0x2983f70_0 .net "out1", 0 0, L_0x2c40d80; 1 drivers +v0x2983cc0_0 .net "outfinal", 0 0, L_0x2c40e70; 1 drivers +S_0x296c740 .scope generate, "muxbits[8]" "muxbits[8]" 3 290, 3 290, S_0x29738d0; + .timescale -9 -12; +P_0x2ae54d8 .param/l "i" 3 290, +C4<01000>; +L_0x2c3a2c0/d .functor OR 1, L_0x2c3a610, L_0x2c44050, C4<0>, C4<0>; +L_0x2c3a2c0 .delay (20000,20000,20000) L_0x2c3a2c0/d; +v0x297c790_0 .net *"_s15", 0 0, L_0x2c3a610; 1 drivers +v0x297c460_0 .net *"_s16", 0 0, L_0x2c44050; 1 drivers +S_0x2973020 .scope module, "ZeroMux" "FourInMux" 3 292, 3 24, S_0x296c740; + .timescale -9 -12; +L_0x2c41c30/d .functor NOT 1, L_0x2c416f0, C4<0>, C4<0>, C4<0>; +L_0x2c41c30 .delay (10000,10000,10000) L_0x2c41c30/d; +L_0x2c41d20/d .functor NOT 1, L_0x2c41820, C4<0>, C4<0>, C4<0>; +L_0x2c41d20 .delay (10000,10000,10000) L_0x2c41d20/d; +L_0x2c41dc0/d .functor NAND 1, L_0x2c41c30, L_0x2c41d20, L_0x2c41950, C4<1>; +L_0x2c41dc0 .delay (10000,10000,10000) L_0x2c41dc0/d; +L_0x2c41f00/d .functor NAND 1, L_0x2c416f0, L_0x2c41d20, L_0x2c419f0, C4<1>; +L_0x2c41f00 .delay (10000,10000,10000) L_0x2c41f00/d; +L_0x2c41ff0/d .functor NAND 1, L_0x2c41c30, L_0x2c41820, L_0x2c41a90, C4<1>; +L_0x2c41ff0 .delay (10000,10000,10000) L_0x2c41ff0/d; +L_0x2c42140/d .functor NAND 1, L_0x2c416f0, L_0x2c41820, L_0x2c42a00, C4<1>; +L_0x2c42140 .delay (10000,10000,10000) L_0x2c42140/d; +L_0x2c42280/d .functor NAND 1, L_0x2c41dc0, L_0x2c41f00, L_0x2c41ff0, L_0x2c42140; +L_0x2c42280 .delay (10000,10000,10000) L_0x2c42280/d; +v0x2972d90_0 .net "S0", 0 0, L_0x2c416f0; 1 drivers +v0x2976b90_0 .net "S1", 0 0, L_0x2c41820; 1 drivers +v0x2976c30_0 .net "in0", 0 0, L_0x2c41950; 1 drivers +v0x2976900_0 .net "in1", 0 0, L_0x2c419f0; 1 drivers +v0x2976980_0 .net "in2", 0 0, L_0x2c41a90; 1 drivers +v0x2979d20_0 .net "in3", 0 0, L_0x2c42a00; 1 drivers +v0x2979dc0_0 .net "nS0", 0 0, L_0x2c41c30; 1 drivers +v0x2979a90_0 .net "nS1", 0 0, L_0x2c41d20; 1 drivers +v0x2979b30_0 .net "out", 0 0, L_0x2c42280; 1 drivers +v0x2978b80_0 .net "out0", 0 0, L_0x2c41dc0; 1 drivers +v0x2978c00_0 .net "out1", 0 0, L_0x2c41f00; 1 drivers +v0x29788f0_0 .net "out2", 0 0, L_0x2c41ff0; 1 drivers +v0x297c6f0_0 .net "out3", 0 0, L_0x2c42140; 1 drivers +S_0x296e3d0 .scope module, "OneMux" "FourInMux" 3 293, 3 24, S_0x296c740; + .timescale -9 -12; +L_0x2c421a0/d .functor NOT 1, L_0x2c433f0, C4<0>, C4<0>, C4<0>; +L_0x2c421a0 .delay (10000,10000,10000) L_0x2c421a0/d; +L_0x2c425c0/d .functor NOT 1, L_0x2c42af0, C4<0>, C4<0>, C4<0>; +L_0x2c425c0 .delay (10000,10000,10000) L_0x2c425c0/d; +L_0x2c42660/d .functor NAND 1, L_0x2c421a0, L_0x2c425c0, L_0x2c42c20, C4<1>; +L_0x2c42660 .delay (10000,10000,10000) L_0x2c42660/d; +L_0x2c427a0/d .functor NAND 1, L_0x2c433f0, L_0x2c425c0, L_0x2c42cc0, C4<1>; +L_0x2c427a0 .delay (10000,10000,10000) L_0x2c427a0/d; +L_0x2c42890/d .functor NAND 1, L_0x2c421a0, L_0x2c42af0, L_0x2c42d60, C4<1>; +L_0x2c42890 .delay (10000,10000,10000) L_0x2c42890/d; +L_0x2c42fd0/d .functor NAND 1, L_0x2c433f0, L_0x2c42af0, L_0x2c42e50, C4<1>; +L_0x2c42fd0 .delay (10000,10000,10000) L_0x2c42fd0/d; +L_0x2c43140/d .functor NAND 1, L_0x2c42660, L_0x2c427a0, L_0x2c42890, L_0x2c42fd0; +L_0x2c43140 .delay (10000,10000,10000) L_0x2c43140/d; +v0x296e110_0 .net "S0", 0 0, L_0x2c433f0; 1 drivers +v0x296e1b0_0 .net "S1", 0 0, L_0x2c42af0; 1 drivers +v0x296d470_0 .net "in0", 0 0, L_0x2c42c20; 1 drivers +v0x296d510_0 .net "in1", 0 0, L_0x2c42cc0; 1 drivers +v0x296d1e0_0 .net "in2", 0 0, L_0x2c42d60; 1 drivers +v0x296d280_0 .net "in3", 0 0, L_0x2c42e50; 1 drivers +v0x296a760_0 .net "nS0", 0 0, L_0x2c421a0; 1 drivers +v0x2971030_0 .net "nS1", 0 0, L_0x2c425c0; 1 drivers +v0x29710b0_0 .net "out", 0 0, L_0x2c43140; 1 drivers +v0x2970da0_0 .net "out0", 0 0, L_0x2c42660; 1 drivers +v0x2970e40_0 .net "out1", 0 0, L_0x2c427a0; 1 drivers +v0x29741e0_0 .net "out2", 0 0, L_0x2c42890; 1 drivers +v0x2973f50_0 .net "out3", 0 0, L_0x2c42fd0; 1 drivers +S_0x296b430 .scope module, "TwoMux" "TwoInMux" 3 294, 3 8, S_0x296c740; + .timescale -9 -12; +L_0x2c42f40/d .functor NOT 1, L_0x2c39e90, C4<0>, C4<0>, C4<0>; +L_0x2c42f40 .delay (10000,10000,10000) L_0x2c42f40/d; +L_0x2c43a80/d .functor AND 1, L_0x2c43520, L_0x2c42f40, C4<1>, C4<1>; +L_0x2c43a80 .delay (20000,20000,20000) L_0x2c43a80/d; +L_0x2c43b70/d .functor AND 1, L_0x2c3a220, L_0x2c39e90, C4<1>, C4<1>; +L_0x2c43b70 .delay (20000,20000,20000) L_0x2c43b70/d; +L_0x2c43c60/d .functor OR 1, L_0x2c43a80, L_0x2c43b70, C4<0>, C4<0>; +L_0x2c43c60 .delay (20000,20000,20000) L_0x2c43c60/d; +v0x296b1a0_0 .net "S", 0 0, L_0x2c39e90; 1 drivers +v0x296b240_0 .net "in0", 0 0, L_0x2c43520; 1 drivers +v0x296af10_0 .net "in1", 0 0, L_0x2c3a220; 1 drivers +v0x296afb0_0 .net "nS", 0 0, L_0x2c42f40; 1 drivers +v0x296ac80_0 .net "out0", 0 0, L_0x2c43a80; 1 drivers +v0x296ad20_0 .net "out1", 0 0, L_0x2c43b70; 1 drivers +v0x296e6c0_0 .net "outfinal", 0 0, L_0x2c43c60; 1 drivers +S_0x2ae3dc0 .scope generate, "muxbits[9]" "muxbits[9]" 3 290, 3 290, S_0x29738d0; + .timescale -9 -12; +P_0x2ad8478 .param/l "i" 3 290, +C4<01001>; +L_0x2c46660/d .functor OR 1, L_0x2c467a0, L_0x2c46840, C4<0>, C4<0>; +L_0x2c46660 .delay (20000,20000,20000) L_0x2c46660/d; +v0x296cff0_0 .net *"_s15", 0 0, L_0x2c467a0; 1 drivers +v0x296cce0_0 .net *"_s16", 0 0, L_0x2c46840; 1 drivers +S_0x2965430 .scope module, "ZeroMux" "FourInMux" 3 292, 3 24, S_0x2ae3dc0; + .timescale -9 -12; +L_0x2c44140/d .functor NOT 1, L_0x2c45160, C4<0>, C4<0>, C4<0>; +L_0x2c44140 .delay (10000,10000,10000) L_0x2c44140/d; +L_0x2c44230/d .functor NOT 1, L_0x2c44790, C4<0>, C4<0>, C4<0>; +L_0x2c44230 .delay (10000,10000,10000) L_0x2c44230/d; +L_0x2c442d0/d .functor NAND 1, L_0x2c44140, L_0x2c44230, L_0x2c448c0, C4<1>; +L_0x2c442d0 .delay (10000,10000,10000) L_0x2c442d0/d; +L_0x2c44410/d .functor NAND 1, L_0x2c45160, L_0x2c44230, L_0x2c44960, C4<1>; +L_0x2c44410 .delay (10000,10000,10000) L_0x2c44410/d; +L_0x2c44500/d .functor NAND 1, L_0x2c44140, L_0x2c44790, L_0x2c44a00, C4<1>; +L_0x2c44500 .delay (10000,10000,10000) L_0x2c44500/d; +L_0x2c44d70/d .functor NAND 1, L_0x2c45160, L_0x2c44790, L_0x2c44af0, C4<1>; +L_0x2c44d70 .delay (10000,10000,10000) L_0x2c44d70/d; +L_0x2c44eb0/d .functor NAND 1, L_0x2c442d0, L_0x2c44410, L_0x2c44500, L_0x2c44d70; +L_0x2c44eb0 .delay (10000,10000,10000) L_0x2c44eb0/d; +v0x29651a0_0 .net "S0", 0 0, L_0x2c45160; 1 drivers +v0x2965240_0 .net "S1", 0 0, L_0x2c44790; 1 drivers +v0x2964ee0_0 .net "in0", 0 0, L_0x2c448c0; 1 drivers +v0x2964f80_0 .net "in1", 0 0, L_0x2c44960; 1 drivers +v0x29689d0_0 .net "in2", 0 0, L_0x2c44a00; 1 drivers +v0x2968a70_0 .net "in3", 0 0, L_0x2c44af0; 1 drivers +v0x2968760_0 .net "nS0", 0 0, L_0x2c44140; 1 drivers +v0x29677a0_0 .net "nS1", 0 0, L_0x2c44230; 1 drivers +v0x2967840_0 .net "out", 0 0, L_0x2c44eb0; 1 drivers +v0x2967510_0 .net "out0", 0 0, L_0x2c442d0; 1 drivers +v0x29675b0_0 .net "out1", 0 0, L_0x2c44410; 1 drivers +v0x2964960_0 .net "out2", 0 0, L_0x2c44500; 1 drivers +v0x296cf50_0 .net "out3", 0 0, L_0x2c44d70; 1 drivers +S_0x2ae78f0 .scope module, "OneMux" "FourInMux" 3 293, 3 24, S_0x2ae3dc0; + .timescale -9 -12; +L_0x2c44dd0/d .functor NOT 1, L_0x2c45290, C4<0>, C4<0>, C4<0>; +L_0x2c44dd0 .delay (10000,10000,10000) L_0x2c44dd0/d; +L_0x2c44c30/d .functor NOT 1, L_0x2c453c0, C4<0>, C4<0>, C4<0>; +L_0x2c44c30 .delay (10000,10000,10000) L_0x2c44c30/d; +L_0x2bef2b0/d .functor NAND 1, L_0x2c44dd0, L_0x2c44c30, L_0x2c454f0, C4<1>; +L_0x2bef2b0 .delay (10000,10000,10000) L_0x2bef2b0/d; +L_0x2bef3f0/d .functor NAND 1, L_0x2c45290, L_0x2c44c30, L_0x2c45590, C4<1>; +L_0x2bef3f0 .delay (10000,10000,10000) L_0x2bef3f0/d; +L_0x2bef510/d .functor NAND 1, L_0x2c44dd0, L_0x2c453c0, L_0x2c45630, C4<1>; +L_0x2bef510 .delay (10000,10000,10000) L_0x2bef510/d; +L_0x2bef660/d .functor NAND 1, L_0x2c45290, L_0x2c453c0, L_0x2c45720, C4<1>; +L_0x2bef660 .delay (10000,10000,10000) L_0x2bef660/d; +L_0x2c46130/d .functor NAND 1, L_0x2bef2b0, L_0x2bef3f0, L_0x2bef510, L_0x2bef660; +L_0x2c46130 .delay (10000,10000,10000) L_0x2c46130/d; +v0x2ae8860_0 .net "S0", 0 0, L_0x2c45290; 1 drivers +v0x2aeaf40_0 .net "S1", 0 0, L_0x2c453c0; 1 drivers +v0x2aeafc0_0 .net "in0", 0 0, L_0x2c454f0; 1 drivers +v0x2aeacc0_0 .net "in1", 0 0, L_0x2c45590; 1 drivers +v0x2aead60_0 .net "in2", 0 0, L_0x2c45630; 1 drivers +v0x2ae9df0_0 .net "in3", 0 0, L_0x2c45720; 1 drivers +v0x2ae9e90_0 .net "nS0", 0 0, L_0x2c44dd0; 1 drivers +v0x29672a0_0 .net "nS1", 0 0, L_0x2c44c30; 1 drivers +v0x2966fc0_0 .net "out", 0 0, L_0x2c46130; 1 drivers +v0x2967060_0 .net "out0", 0 0, L_0x2bef2b0; 1 drivers +v0x2966a40_0 .net "out1", 0 0, L_0x2bef3f0; 1 drivers +v0x2966ae0_0 .net "out2", 0 0, L_0x2bef510; 1 drivers +v0x2965780_0 .net "out3", 0 0, L_0x2bef660; 1 drivers +S_0x2ae2ed0 .scope module, "TwoMux" "TwoInMux" 3 294, 3 8, S_0x2ae3dc0; + .timescale -9 -12; +L_0x2967320/d .functor NOT 1, L_0x2c46df0, C4<0>, C4<0>, C4<0>; +L_0x2967320 .delay (10000,10000,10000) L_0x2967320/d; +L_0x2c46a30/d .functor AND 1, L_0x2c463e0, L_0x2967320, C4<1>, C4<1>; +L_0x2c46a30 .delay (20000,20000,20000) L_0x2c46a30/d; +L_0x2c46b20/d .functor AND 1, L_0x2c464d0, L_0x2c46df0, C4<1>, C4<1>; +L_0x2c46b20 .delay (20000,20000,20000) L_0x2c46b20/d; +L_0x2c46c10/d .functor OR 1, L_0x2c46a30, L_0x2c46b20, C4<0>, C4<0>; +L_0x2c46c10 .delay (20000,20000,20000) L_0x2c46c10/d; +v0x2ae6540_0 .net "S", 0 0, L_0x2c46df0; 1 drivers +v0x2ae65e0_0 .net "in0", 0 0, L_0x2c463e0; 1 drivers +v0x2ae62c0_0 .net "in1", 0 0, L_0x2c464d0; 1 drivers +v0x2ae6360_0 .net "nS", 0 0, L_0x2967320; 1 drivers +v0x2ae5410_0 .net "out0", 0 0, L_0x2c46a30; 1 drivers +v0x2ae8a40_0 .net "out1", 0 0, L_0x2c46b20; 1 drivers +v0x2ae87c0_0 .net "outfinal", 0 0, L_0x2c46c10; 1 drivers +S_0x2ad17d0 .scope generate, "muxbits[10]" "muxbits[10]" 3 290, 3 290, S_0x29738d0; + .timescale -9 -12; +P_0x2ac1588 .param/l "i" 3 290, +C4<01010>; +L_0x2c48e70/d .functor OR 1, L_0x2c48f70, L_0x2c49010, C4<0>, C4<0>; +L_0x2c48e70 .delay (20000,20000,20000) L_0x2c48e70/d; +v0x2ae0a60_0 .net *"_s15", 0 0, L_0x2c48f70; 1 drivers +v0x2ae4040_0 .net *"_s16", 0 0, L_0x2c49010; 1 drivers +S_0x2add110 .scope module, "ZeroMux" "FourInMux" 3 292, 3 24, S_0x2ad17d0; + .timescale -9 -12; +L_0x2c46930/d .functor NOT 1, L_0x2c46e90, C4<0>, C4<0>, C4<0>; +L_0x2c46930 .delay (10000,10000,10000) L_0x2c46930/d; +L_0x2c47510/d .functor NOT 1, L_0x2c46fc0, C4<0>, C4<0>, C4<0>; +L_0x2c47510 .delay (10000,10000,10000) L_0x2c47510/d; +L_0x2c475b0/d .functor NAND 1, L_0x2c46930, L_0x2c47510, L_0x2c470f0, C4<1>; +L_0x2c475b0 .delay (10000,10000,10000) L_0x2c475b0/d; +L_0x2c476f0/d .functor NAND 1, L_0x2c46e90, L_0x2c47510, L_0x2c47190, C4<1>; +L_0x2c476f0 .delay (10000,10000,10000) L_0x2c476f0/d; +L_0x2c477e0/d .functor NAND 1, L_0x2c46930, L_0x2c46fc0, L_0x2c47230, C4<1>; +L_0x2c477e0 .delay (10000,10000,10000) L_0x2c477e0/d; +L_0x2c478d0/d .functor NAND 1, L_0x2c46e90, L_0x2c46fc0, L_0x2c47320, C4<1>; +L_0x2c478d0 .delay (10000,10000,10000) L_0x2c478d0/d; +L_0x2c47a10/d .functor NAND 1, L_0x2c475b0, L_0x2c476f0, L_0x2c477e0, L_0x2c478d0; +L_0x2c47a10 .delay (10000,10000,10000) L_0x2c47a10/d; +v0x2adce90_0 .net "S0", 0 0, L_0x2c46e90; 1 drivers +v0x2adbfa0_0 .net "S1", 0 0, L_0x2c46fc0; 1 drivers +v0x2adc040_0 .net "in0", 0 0, L_0x2c470f0; 1 drivers +v0x2adf620_0 .net "in1", 0 0, L_0x2c47190; 1 drivers +v0x2adf6a0_0 .net "in2", 0 0, L_0x2c47230; 1 drivers +v0x2adf3a0_0 .net "in3", 0 0, L_0x2c47320; 1 drivers +v0x2adf440_0 .net "nS0", 0 0, L_0x2c46930; 1 drivers +v0x2ade4b0_0 .net "nS1", 0 0, L_0x2c47510; 1 drivers +v0x2ade550_0 .net "out", 0 0, L_0x2c47a10; 1 drivers +v0x2ae1b30_0 .net "out0", 0 0, L_0x2c475b0; 1 drivers +v0x2ae1bb0_0 .net "out1", 0 0, L_0x2c476f0; 1 drivers +v0x2ae18b0_0 .net "out2", 0 0, L_0x2c477e0; 1 drivers +v0x2ae09c0_0 .net "out3", 0 0, L_0x2c478d0; 1 drivers +S_0x2ad61e0 .scope module, "OneMux" "FourInMux" 3 293, 3 24, S_0x2ad17d0; + .timescale -9 -12; +L_0x2c47410/d .functor NOT 1, L_0x2c48b60, C4<0>, C4<0>, C4<0>; +L_0x2c47410 .delay (10000,10000,10000) L_0x2c47410/d; +L_0x2c48380/d .functor NOT 1, L_0x2c47cc0, C4<0>, C4<0>, C4<0>; +L_0x2c48380 .delay (10000,10000,10000) L_0x2c48380/d; +L_0x2c48420/d .functor NAND 1, L_0x2c47410, L_0x2c48380, L_0x2c47df0, C4<1>; +L_0x2c48420 .delay (10000,10000,10000) L_0x2c48420/d; +L_0x2c48560/d .functor NAND 1, L_0x2c48b60, L_0x2c48380, L_0x2c47e90, C4<1>; +L_0x2c48560 .delay (10000,10000,10000) L_0x2c48560/d; +L_0x2c48650/d .functor NAND 1, L_0x2c47410, L_0x2c47cc0, L_0x2c47f30, C4<1>; +L_0x2c48650 .delay (10000,10000,10000) L_0x2c48650/d; +L_0x2c48740/d .functor NAND 1, L_0x2c48b60, L_0x2c47cc0, L_0x2c48020, C4<1>; +L_0x2c48740 .delay (10000,10000,10000) L_0x2c48740/d; +L_0x2c488b0/d .functor NAND 1, L_0x2c48420, L_0x2c48560, L_0x2c48650, L_0x2c48740; +L_0x2c488b0 .delay (10000,10000,10000) L_0x2c488b0/d; +v0x2ad5f60_0 .net "S0", 0 0, L_0x2c48b60; 1 drivers +v0x2ad6000_0 .net "S1", 0 0, L_0x2c47cc0; 1 drivers +v0x2ad5070_0 .net "in0", 0 0, L_0x2c47df0; 1 drivers +v0x2ad5110_0 .net "in1", 0 0, L_0x2c47e90; 1 drivers +v0x2ad86f0_0 .net "in2", 0 0, L_0x2c47f30; 1 drivers +v0x2ad8790_0 .net "in3", 0 0, L_0x2c48020; 1 drivers +v0x2ad84d0_0 .net "nS0", 0 0, L_0x2c47410; 1 drivers +v0x2ad7580_0 .net "nS1", 0 0, L_0x2c48380; 1 drivers +v0x2ad7600_0 .net "out", 0 0, L_0x2c488b0; 1 drivers +v0x2adac00_0 .net "out0", 0 0, L_0x2c48420; 1 drivers +v0x2adaca0_0 .net "out1", 0 0, L_0x2c48560; 1 drivers +v0x2ada9a0_0 .net "out2", 0 0, L_0x2c48650; 1 drivers +v0x2ad9ab0_0 .net "out3", 0 0, L_0x2c48740; 1 drivers +S_0x2ad1550 .scope module, "TwoMux" "TwoInMux" 3 294, 3 8, S_0x2ad17d0; + .timescale -9 -12; +L_0x2c48110/d .functor NOT 1, L_0x2c2caa0, C4<0>, C4<0>, C4<0>; +L_0x2c48110 .delay (10000,10000,10000) L_0x2c48110/d; +L_0x2c481c0/d .functor AND 1, L_0x2c2cb40, L_0x2c48110, C4<1>, C4<1>; +L_0x2c481c0 .delay (20000,20000,20000) L_0x2c481c0/d; +L_0x2c2c810/d .functor AND 1, L_0x2c48ce0, L_0x2c2caa0, C4<1>, C4<1>; +L_0x2c2c810 .delay (20000,20000,20000) L_0x2c2c810/d; +L_0x2c2c8c0/d .functor OR 1, L_0x2c481c0, L_0x2c2c810, C4<0>, C4<0>; +L_0x2c2c8c0 .delay (20000,20000,20000) L_0x2c2c8c0/d; +v0x2ad0680_0 .net "S", 0 0, L_0x2c2caa0; 1 drivers +v0x2ad0720_0 .net "in0", 0 0, L_0x2c2cb40; 1 drivers +v0x2ad3cd0_0 .net "in1", 0 0, L_0x2c48ce0; 1 drivers +v0x2ad3d70_0 .net "nS", 0 0, L_0x2c48110; 1 drivers +v0x2ad3a50_0 .net "out0", 0 0, L_0x2c481c0; 1 drivers +v0x2ad3af0_0 .net "out1", 0 0, L_0x2c2c810; 1 drivers +v0x2ad2be0_0 .net "outfinal", 0 0, L_0x2c2c8c0; 1 drivers +S_0x2abb910 .scope generate, "muxbits[11]" "muxbits[11]" 3 290, 3 290, S_0x29738d0; + .timescale -9 -12; +P_0x2aafff8 .param/l "i" 3 290, +C4<01011>; +L_0x2c4b980/d .functor OR 1, L_0x2c4bac0, L_0x2c4bb60, C4<0>, C4<0>; +L_0x2c4b980 .delay (20000,20000,20000) L_0x2c4b980/d; +v0x2acf0f0_0 .net *"_s15", 0 0, L_0x2c4bac0; 1 drivers +v0x2ace1a0_0 .net *"_s16", 0 0, L_0x2c4bb60; 1 drivers +S_0x2ac7280 .scope module, "ZeroMux" "FourInMux" 3 292, 3 24, S_0x2abb910; + .timescale -9 -12; +L_0x2c49100/d .functor NOT 1, L_0x2c4a880, C4<0>, C4<0>, C4<0>; +L_0x2c49100 .delay (10000,10000,10000) L_0x2c49100/d; +L_0x2c491f0/d .functor NOT 1, L_0x2c49af0, C4<0>, C4<0>, C4<0>; +L_0x2c491f0 .delay (10000,10000,10000) L_0x2c491f0/d; +L_0x2c4a190/d .functor NAND 1, L_0x2c49100, L_0x2c491f0, L_0x2c49c20, C4<1>; +L_0x2c4a190 .delay (10000,10000,10000) L_0x2c4a190/d; +L_0x2c4a280/d .functor NAND 1, L_0x2c4a880, L_0x2c491f0, L_0x2c49cc0, C4<1>; +L_0x2c4a280 .delay (10000,10000,10000) L_0x2c4a280/d; +L_0x2c4a370/d .functor NAND 1, L_0x2c49100, L_0x2c49af0, L_0x2c49d60, C4<1>; +L_0x2c4a370 .delay (10000,10000,10000) L_0x2c4a370/d; +L_0x2c4a460/d .functor NAND 1, L_0x2c4a880, L_0x2c49af0, L_0x2c49e50, C4<1>; +L_0x2c4a460 .delay (10000,10000,10000) L_0x2c4a460/d; +L_0x2c4a5d0/d .functor NAND 1, L_0x2c4a190, L_0x2c4a280, L_0x2c4a370, L_0x2c4a460; +L_0x2c4a5d0 .delay (10000,10000,10000) L_0x2c4a5d0/d; +v0x2aca8d0_0 .net "S0", 0 0, L_0x2c4a880; 1 drivers +v0x2aca970_0 .net "S1", 0 0, L_0x2c49af0; 1 drivers +v0x2aca650_0 .net "in0", 0 0, L_0x2c49c20; 1 drivers +v0x2aca6f0_0 .net "in1", 0 0, L_0x2c49cc0; 1 drivers +v0x2ac9780_0 .net "in2", 0 0, L_0x2c49d60; 1 drivers +v0x2ac9820_0 .net "in3", 0 0, L_0x2c49e50; 1 drivers +v0x2accdf0_0 .net "nS0", 0 0, L_0x2c49100; 1 drivers +v0x2accb50_0 .net "nS1", 0 0, L_0x2c491f0; 1 drivers +v0x2accbf0_0 .net "out", 0 0, L_0x2c4a5d0; 1 drivers +v0x2acbc80_0 .net "out0", 0 0, L_0x2c4a190; 1 drivers +v0x2acbd20_0 .net "out1", 0 0, L_0x2c4a280; 1 drivers +v0x2acf2d0_0 .net "out2", 0 0, L_0x2c4a370; 1 drivers +v0x2acf050_0 .net "out3", 0 0, L_0x2c4a460; 1 drivers +S_0x2ac39d0 .scope module, "OneMux" "FourInMux" 3 293, 3 24, S_0x2abb910; + .timescale -9 -12; +L_0x2c49f40/d .functor NOT 1, L_0x2c4a9b0, C4<0>, C4<0>, C4<0>; +L_0x2c49f40 .delay (10000,10000,10000) L_0x2c49f40/d; +L_0x2c49ff0/d .functor NOT 1, L_0x2c4aae0, C4<0>, C4<0>, C4<0>; +L_0x2c49ff0 .delay (10000,10000,10000) L_0x2c49ff0/d; +L_0x2c4a090/d .functor NAND 1, L_0x2c49f40, L_0x2c49ff0, L_0x2c4ac10, C4<1>; +L_0x2c4a090 .delay (10000,10000,10000) L_0x2c4a090/d; +L_0x2c4b0d0/d .functor NAND 1, L_0x2c4a9b0, L_0x2c49ff0, L_0x2c4acb0, C4<1>; +L_0x2c4b0d0 .delay (10000,10000,10000) L_0x2c4b0d0/d; +L_0x2c4b1c0/d .functor NAND 1, L_0x2c49f40, L_0x2c4aae0, L_0x2c4ad50, C4<1>; +L_0x2c4b1c0 .delay (10000,10000,10000) L_0x2c4b1c0/d; +L_0x2c4b2e0/d .functor NAND 1, L_0x2c4a9b0, L_0x2c4aae0, L_0x2c4ae40, C4<1>; +L_0x2c4b2e0 .delay (10000,10000,10000) L_0x2c4b2e0/d; +L_0x2c4b450/d .functor NAND 1, L_0x2c4a090, L_0x2c4b0d0, L_0x2c4b1c0, L_0x2c4b2e0; +L_0x2c4b450 .delay (10000,10000,10000) L_0x2c4b450/d; +v0x2ac03d0_0 .net "S0", 0 0, L_0x2c4a9b0; 1 drivers +v0x2ac3720_0 .net "S1", 0 0, L_0x2c4aae0; 1 drivers +v0x2ac37a0_0 .net "in0", 0 0, L_0x2c4ac10; 1 drivers +v0x2ac2840_0 .net "in1", 0 0, L_0x2c4acb0; 1 drivers +v0x2ac28e0_0 .net "in2", 0 0, L_0x2c4ad50; 1 drivers +v0x2ac5ed0_0 .net "in3", 0 0, L_0x2c4ae40; 1 drivers +v0x2ac5f70_0 .net "nS0", 0 0, L_0x2c49f40; 1 drivers +v0x2ac5c70_0 .net "nS1", 0 0, L_0x2c49ff0; 1 drivers +v0x2ac4d80_0 .net "out", 0 0, L_0x2c4b450; 1 drivers +v0x2ac4e20_0 .net "out0", 0 0, L_0x2c4a090; 1 drivers +v0x2ac83d0_0 .net "out1", 0 0, L_0x2c4b0d0; 1 drivers +v0x2ac8470_0 .net "out2", 0 0, L_0x2c4b1c0; 1 drivers +v0x2ac81e0_0 .net "out3", 0 0, L_0x2c4b2e0; 1 drivers +S_0x2abef90 .scope module, "TwoMux" "TwoInMux" 3 294, 3 8, S_0x2abb910; + .timescale -9 -12; +L_0x2ac5cf0/d .functor NOT 1, L_0x2c4c130, C4<0>, C4<0>, C4<0>; +L_0x2ac5cf0 .delay (10000,10000,10000) L_0x2ac5cf0/d; +L_0x2c4afc0/d .functor AND 1, L_0x2c4b700, L_0x2ac5cf0, C4<1>, C4<1>; +L_0x2c4afc0 .delay (20000,20000,20000) L_0x2c4afc0/d; +L_0x2c4be60/d .functor AND 1, L_0x2c4b7f0, L_0x2c4c130, C4<1>, C4<1>; +L_0x2c4be60 .delay (20000,20000,20000) L_0x2c4be60/d; +L_0x2c4bf50/d .functor OR 1, L_0x2c4afc0, L_0x2c4be60, C4<0>, C4<0>; +L_0x2c4bf50 .delay (20000,20000,20000) L_0x2c4bf50/d; +v0x2abed10_0 .net "S", 0 0, L_0x2c4c130; 1 drivers +v0x2abedb0_0 .net "in0", 0 0, L_0x2c4b700; 1 drivers +v0x2abde20_0 .net "in1", 0 0, L_0x2c4b7f0; 1 drivers +v0x2abdec0_0 .net "nS", 0 0, L_0x2ac5cf0; 1 drivers +v0x2ac14c0_0 .net "out0", 0 0, L_0x2c4afc0; 1 drivers +v0x2ac1220_0 .net "out1", 0 0, L_0x2c4be60; 1 drivers +v0x2ac0330_0 .net "outfinal", 0 0, L_0x2c4bf50; 1 drivers +S_0x2aa9fc0 .scope generate, "muxbits[12]" "muxbits[12]" 3 290, 3 290, S_0x29738d0; + .timescale -9 -12; +P_0x2a9dab8 .param/l "i" 3 290, +C4<01100>; +L_0x2c4e2d0/d .functor OR 1, L_0x2c4e410, L_0x2c4e4b0, C4<0>, C4<0>; +L_0x2c4e2d0 .delay (20000,20000,20000) L_0x2c4e2d0/d; +v0x2abcb20_0 .net *"_s15", 0 0, L_0x2c4e410; 1 drivers +v0x2abc800_0 .net *"_s16", 0 0, L_0x2c4e4b0; 1 drivers +S_0x2ab58d0 .scope module, "ZeroMux" "FourInMux" 3 292, 3 24, S_0x2aa9fc0; + .timescale -9 -12; +L_0x2c4bc50/d .functor NOT 1, L_0x2c4c1d0, C4<0>, C4<0>, C4<0>; +L_0x2c4bc50 .delay (10000,10000,10000) L_0x2c4bc50/d; +L_0x2c4bd40/d .functor NOT 1, L_0x2c4c300, C4<0>, C4<0>, C4<0>; +L_0x2c4bd40 .delay (10000,10000,10000) L_0x2c4bd40/d; +L_0x2c4c910/d .functor NAND 1, L_0x2c4bc50, L_0x2c4bd40, L_0x2c4c430, C4<1>; +L_0x2c4c910 .delay (10000,10000,10000) L_0x2c4c910/d; +L_0x2c4ca50/d .functor NAND 1, L_0x2c4c1d0, L_0x2c4bd40, L_0x2c4c4d0, C4<1>; +L_0x2c4ca50 .delay (10000,10000,10000) L_0x2c4ca50/d; +L_0x2c4cb40/d .functor NAND 1, L_0x2c4bc50, L_0x2c4c300, L_0x2c4c570, C4<1>; +L_0x2c4cb40 .delay (10000,10000,10000) L_0x2c4cb40/d; +L_0x2c4cc30/d .functor NAND 1, L_0x2c4c1d0, L_0x2c4c300, L_0x2c4c660, C4<1>; +L_0x2c4cc30 .delay (10000,10000,10000) L_0x2c4cc30/d; +L_0x2c4cd40/d .functor NAND 1, L_0x2c4c910, L_0x2c4ca50, L_0x2c4cb40, L_0x2c4cc30; +L_0x2c4cd40 .delay (10000,10000,10000) L_0x2c4cd40/d; +v0x2ab49e0_0 .net "S0", 0 0, L_0x2c4c1d0; 1 drivers +v0x2ab8060_0 .net "S1", 0 0, L_0x2c4c300; 1 drivers +v0x2ab8100_0 .net "in0", 0 0, L_0x2c4c430; 1 drivers +v0x2ab7de0_0 .net "in1", 0 0, L_0x2c4c4d0; 1 drivers +v0x2ab7e60_0 .net "in2", 0 0, L_0x2c4c570; 1 drivers +v0x2ab6ef0_0 .net "in3", 0 0, L_0x2c4c660; 1 drivers +v0x2ab6f90_0 .net "nS0", 0 0, L_0x2c4bc50; 1 drivers +v0x2aba570_0 .net "nS1", 0 0, L_0x2c4bd40; 1 drivers +v0x2aba610_0 .net "out", 0 0, L_0x2c4cd40; 1 drivers +v0x2aba2f0_0 .net "out0", 0 0, L_0x2c4c910; 1 drivers +v0x2aba370_0 .net "out1", 0 0, L_0x2c4ca50; 1 drivers +v0x2ab9400_0 .net "out2", 0 0, L_0x2c4cb40; 1 drivers +v0x2abca80_0 .net "out3", 0 0, L_0x2c4cc30; 1 drivers +S_0x2aae9c0 .scope module, "OneMux" "FourInMux" 3 293, 3 24, S_0x2aa9fc0; + .timescale -9 -12; +L_0x2c4c750/d .functor NOT 1, L_0x2c4de80, C4<0>, C4<0>, C4<0>; +L_0x2c4c750 .delay (10000,10000,10000) L_0x2c4c750/d; +L_0x2c4c840/d .functor NOT 1, L_0x2c4cff0, C4<0>, C4<0>, C4<0>; +L_0x2c4c840 .delay (10000,10000,10000) L_0x2c4c840/d; +L_0x2c4d770/d .functor NAND 1, L_0x2c4c750, L_0x2c4c840, L_0x2c4d120, C4<1>; +L_0x2c4d770 .delay (10000,10000,10000) L_0x2c4d770/d; +L_0x2c4d8b0/d .functor NAND 1, L_0x2c4de80, L_0x2c4c840, L_0x2c4d1c0, C4<1>; +L_0x2c4d8b0 .delay (10000,10000,10000) L_0x2c4d8b0/d; +L_0x2c4d9a0/d .functor NAND 1, L_0x2c4c750, L_0x2c4cff0, L_0x2c4d260, C4<1>; +L_0x2c4d9a0 .delay (10000,10000,10000) L_0x2c4d9a0/d; +L_0x2c4da90/d .functor NAND 1, L_0x2c4de80, L_0x2c4cff0, L_0x2c4d350, C4<1>; +L_0x2c4da90 .delay (10000,10000,10000) L_0x2c4da90/d; +L_0x2c4dbd0/d .functor NAND 1, L_0x2c4d770, L_0x2c4d8b0, L_0x2c4d9a0, L_0x2c4da90; +L_0x2c4dbd0 .delay (10000,10000,10000) L_0x2c4dbd0/d; +v0x2aadaf0_0 .net "S0", 0 0, L_0x2c4de80; 1 drivers +v0x2aadb90_0 .net "S1", 0 0, L_0x2c4cff0; 1 drivers +v0x2ab1140_0 .net "in0", 0 0, L_0x2c4d120; 1 drivers +v0x2ab11e0_0 .net "in1", 0 0, L_0x2c4d1c0; 1 drivers +v0x2ab0ec0_0 .net "in2", 0 0, L_0x2c4d260; 1 drivers +v0x2ab0f60_0 .net "in3", 0 0, L_0x2c4d350; 1 drivers +v0x2ab0050_0 .net "nS0", 0 0, L_0x2c4c750; 1 drivers +v0x2ab3640_0 .net "nS1", 0 0, L_0x2c4c840; 1 drivers +v0x2ab36c0_0 .net "out", 0 0, L_0x2c4dbd0; 1 drivers +v0x2ab33c0_0 .net "out0", 0 0, L_0x2c4d770; 1 drivers +v0x2ab3460_0 .net "out1", 0 0, L_0x2c4d8b0; 1 drivers +v0x2ab2510_0 .net "out2", 0 0, L_0x2c4d9a0; 1 drivers +v0x2ab5b70_0 .net "out3", 0 0, L_0x2c4da90; 1 drivers +S_0x2aa90f0 .scope module, "TwoMux" "TwoInMux" 3 294, 3 8, S_0x2aa9fc0; + .timescale -9 -12; +L_0x2c4d440/d .functor NOT 1, L_0x2c4dfb0, C4<0>, C4<0>, C4<0>; +L_0x2c4d440 .delay (10000,10000,10000) L_0x2c4d440/d; +L_0x2c4d4f0/d .functor AND 1, L_0x2c4e050, L_0x2c4d440, C4<1>, C4<1>; +L_0x2c4d4f0 .delay (20000,20000,20000) L_0x2c4d4f0/d; +L_0x2c4d5e0/d .functor AND 1, L_0x2c4e140, L_0x2c4dfb0, C4<1>, C4<1>; +L_0x2c4d5e0 .delay (20000,20000,20000) L_0x2c4d5e0/d; +L_0x2c4d6d0/d .functor OR 1, L_0x2c4d4f0, L_0x2c4d5e0, C4<0>, C4<0>; +L_0x2c4d6d0 .delay (20000,20000,20000) L_0x2c4d6d0/d; +v0x2aac740_0 .net "S", 0 0, L_0x2c4dfb0; 1 drivers +v0x2aac7e0_0 .net "in0", 0 0, L_0x2c4e050; 1 drivers +v0x2aac4c0_0 .net "in1", 0 0, L_0x2c4e140; 1 drivers +v0x2aac560_0 .net "nS", 0 0, L_0x2c4d440; 1 drivers +v0x2aab5f0_0 .net "out0", 0 0, L_0x2c4d4f0; 1 drivers +v0x2aab690_0 .net "out1", 0 0, L_0x2c4d5e0; 1 drivers +v0x2aaeca0_0 .net "outfinal", 0 0, L_0x2c4d6d0; 1 drivers +S_0x2a9c690 .scope generate, "muxbits[13]" "muxbits[13]" 3 290, 3 290, S_0x29738d0; + .timescale -9 -12; +P_0x2a959d8 .param/l "i" 3 290, +C4<01101>; +L_0x2c508b0/d .functor OR 1, L_0x2c509f0, L_0x2c50a90, C4<0>, C4<0>; +L_0x2c508b0 .delay (20000,20000,20000) L_0x2c508b0/d; +v0x2aa6c60_0 .net *"_s15", 0 0, L_0x2c509f0; 1 drivers +v0x2aaa260_0 .net *"_s16", 0 0, L_0x2c50a90; 1 drivers +S_0x2aed420 .scope module, "ZeroMux" "FourInMux" 3 292, 3 24, S_0x2a9c690; + .timescale -9 -12; +L_0x2c4e5a0/d .functor NOT 1, L_0x2c4f7a0, C4<0>, C4<0>, C4<0>; +L_0x2c4e5a0 .delay (10000,10000,10000) L_0x2c4e5a0/d; +L_0x2c4e690/d .functor NOT 1, L_0x2c4e8a0, C4<0>, C4<0>, C4<0>; +L_0x2c4e690 .delay (10000,10000,10000) L_0x2c4e690/d; +L_0x2c4f090/d .functor NAND 1, L_0x2c4e5a0, L_0x2c4e690, L_0x2c4e9d0, C4<1>; +L_0x2c4f090 .delay (10000,10000,10000) L_0x2c4f090/d; +L_0x2c4f1d0/d .functor NAND 1, L_0x2c4f7a0, L_0x2c4e690, L_0x2c4ea70, C4<1>; +L_0x2c4f1d0 .delay (10000,10000,10000) L_0x2c4f1d0/d; +L_0x2c4f2c0/d .functor NAND 1, L_0x2c4e5a0, L_0x2c4e8a0, L_0x2c4eb10, C4<1>; +L_0x2c4f2c0 .delay (10000,10000,10000) L_0x2c4f2c0/d; +L_0x2c4f3b0/d .functor NAND 1, L_0x2c4f7a0, L_0x2c4e8a0, L_0x2c4ec00, C4<1>; +L_0x2c4f3b0 .delay (10000,10000,10000) L_0x2c4f3b0/d; +L_0x2c4f4f0/d .functor NAND 1, L_0x2c4f090, L_0x2c4f1d0, L_0x2c4f2c0, L_0x2c4f3b0; +L_0x2c4f4f0 .delay (10000,10000,10000) L_0x2c4f4f0/d; +v0x2aed1b0_0 .net "S0", 0 0, L_0x2c4f7a0; 1 drivers +v0x2aed250_0 .net "S1", 0 0, L_0x2c4e8a0; 1 drivers +v0x2aec2f0_0 .net "in0", 0 0, L_0x2c4e9d0; 1 drivers +v0x2aec390_0 .net "in1", 0 0, L_0x2c4ea70; 1 drivers +v0x2aa57d0_0 .net "in2", 0 0, L_0x2c4eb10; 1 drivers +v0x2aa5870_0 .net "in3", 0 0, L_0x2c4ec00; 1 drivers +v0x2aa5510_0 .net "nS0", 0 0, L_0x2c4e5a0; 1 drivers +v0x2aa4640_0 .net "nS1", 0 0, L_0x2c4e690; 1 drivers +v0x2aa46e0_0 .net "out", 0 0, L_0x2c4f4f0; 1 drivers +v0x2aa7d40_0 .net "out0", 0 0, L_0x2c4f090; 1 drivers +v0x2aa7de0_0 .net "out1", 0 0, L_0x2c4f1d0; 1 drivers +v0x2aa7ac0_0 .net "out2", 0 0, L_0x2c4f2c0; 1 drivers +v0x2aa6bc0_0 .net "out3", 0 0, L_0x2c4f3b0; 1 drivers +S_0x2a9ef90 .scope module, "OneMux" "FourInMux" 3 293, 3 24, S_0x2a9c690; + .timescale -9 -12; +L_0x2c4ecf0/d .functor NOT 1, L_0x2c4f8d0, C4<0>, C4<0>, C4<0>; +L_0x2c4ecf0 .delay (10000,10000,10000) L_0x2c4ecf0/d; +L_0x2c4eda0/d .functor NOT 1, L_0x2c4fa00, C4<0>, C4<0>, C4<0>; +L_0x2c4eda0 .delay (10000,10000,10000) L_0x2c4eda0/d; +L_0x2c4ee40/d .functor NAND 1, L_0x2c4ecf0, L_0x2c4eda0, L_0x2c4fb30, C4<1>; +L_0x2c4ee40 .delay (10000,10000,10000) L_0x2c4ee40/d; +L_0x2c4ef80/d .functor NAND 1, L_0x2c4f8d0, L_0x2c4eda0, L_0x2c4fbd0, C4<1>; +L_0x2c4ef80 .delay (10000,10000,10000) L_0x2c4ef80/d; +L_0x2c500f0/d .functor NAND 1, L_0x2c4ecf0, L_0x2c4fa00, L_0x2c4fc70, C4<1>; +L_0x2c500f0 .delay (10000,10000,10000) L_0x2c500f0/d; +L_0x2c50210/d .functor NAND 1, L_0x2c4f8d0, L_0x2c4fa00, L_0x2c4fd60, C4<1>; +L_0x2c50210 .delay (10000,10000,10000) L_0x2c50210/d; +L_0x2c50380/d .functor NAND 1, L_0x2c4ee40, L_0x2c4ef80, L_0x2c500f0, L_0x2c50210; +L_0x2c50380 .delay (10000,10000,10000) L_0x2c50380/d; +v0x2a9f2b0_0 .net "S0", 0 0, L_0x2c4f8d0; 1 drivers +v0x2a9ea90_0 .net "S1", 0 0, L_0x2c4fa00; 1 drivers +v0x2a9eb10_0 .net "in0", 0 0, L_0x2c4fb30; 1 drivers +v0x2aa07d0_0 .net "in1", 0 0, L_0x2c4fbd0; 1 drivers +v0x2aa0870_0 .net "in2", 0 0, L_0x2c4fc70; 1 drivers +v0x2aa0550_0 .net "in3", 0 0, L_0x2c4fd60; 1 drivers +v0x2aa05f0_0 .net "nS0", 0 0, L_0x2c4ecf0; 1 drivers +v0x2aa0070_0 .net "nS1", 0 0, L_0x2c4eda0; 1 drivers +v0x2aa1d90_0 .net "out", 0 0, L_0x2c50380; 1 drivers +v0x2aa1e30_0 .net "out0", 0 0, L_0x2c4ee40; 1 drivers +v0x2aa1b10_0 .net "out1", 0 0, L_0x2c4ef80; 1 drivers +v0x2aa1bb0_0 .net "out2", 0 0, L_0x2c500f0; 1 drivers +v0x2aa16a0_0 .net "out3", 0 0, L_0x2c50210; 1 drivers +S_0x2a9c410 .scope module, "TwoMux" "TwoInMux" 3 294, 3 8, S_0x2a9c690; + .timescale -9 -12; +L_0x2aa00f0/d .functor NOT 1, L_0x2c51070, C4<0>, C4<0>, C4<0>; +L_0x2aa00f0 .delay (10000,10000,10000) L_0x2aa00f0/d; +L_0x2c4fee0/d .functor AND 1, L_0x2c50630, L_0x2aa00f0, C4<1>, C4<1>; +L_0x2c4fee0 .delay (20000,20000,20000) L_0x2c4fee0/d; +L_0x2c4ffd0/d .functor AND 1, L_0x2c50720, L_0x2c51070, C4<1>, C4<1>; +L_0x2c4ffd0 .delay (20000,20000,20000) L_0x2c4ffd0/d; +L_0x2c50e90/d .functor OR 1, L_0x2c4fee0, L_0x2c4ffd0, C4<0>, C4<0>; +L_0x2c50e90 .delay (20000,20000,20000) L_0x2c50e90/d; +v0x2a9bf10_0 .net "S", 0 0, L_0x2c51070; 1 drivers +v0x2a9bfb0_0 .net "in0", 0 0, L_0x2c50630; 1 drivers +v0x2a9dc50_0 .net "in1", 0 0, L_0x2c50720; 1 drivers +v0x2a9dcf0_0 .net "nS", 0 0, L_0x2aa00f0; 1 drivers +v0x2a9d9f0_0 .net "out0", 0 0, L_0x2c4fee0; 1 drivers +v0x2a9d4d0_0 .net "out1", 0 0, L_0x2c4ffd0; 1 drivers +v0x2a9f210_0 .net "outfinal", 0 0, L_0x2c50e90; 1 drivers +S_0x2a8ea90 .scope generate, "muxbits[14]" "muxbits[14]" 3 290, 3 290, S_0x29738d0; + .timescale -9 -12; +P_0x2a81298 .param/l "i" 3 290, +C4<01110>; +L_0x2c53020/d .functor OR 1, L_0x2c53160, L_0x2c53200, C4<0>, C4<0>; +L_0x2c53020 .delay (20000,20000,20000) L_0x2c53020/d; +v0x2a9aef0_0 .net *"_s15", 0 0, L_0x2c53160; 1 drivers +v0x2a9a950_0 .net *"_s16", 0 0, L_0x2c53200; 1 drivers +S_0x2a96810 .scope module, "ZeroMux" "FourInMux" 3 292, 3 24, S_0x2a8ea90; + .timescale -9 -12; +L_0x2c50b80/d .functor NOT 1, L_0x2c51110, C4<0>, C4<0>, C4<0>; +L_0x2c50b80 .delay (10000,10000,10000) L_0x2c50b80/d; +L_0x2c50c70/d .functor NOT 1, L_0x2c51240, C4<0>, C4<0>, C4<0>; +L_0x2c50c70 .delay (10000,10000,10000) L_0x2c50c70/d; +L_0x2c50d10/d .functor NAND 1, L_0x2c50b80, L_0x2c50c70, L_0x2c51370, C4<1>; +L_0x2c50d10 .delay (10000,10000,10000) L_0x2c50d10/d; +L_0x2c519a0/d .functor NAND 1, L_0x2c51110, L_0x2c50c70, L_0x2c51410, C4<1>; +L_0x2c519a0 .delay (10000,10000,10000) L_0x2c519a0/d; +L_0x2c51a50/d .functor NAND 1, L_0x2c50b80, L_0x2c51240, L_0x2c514b0, C4<1>; +L_0x2c51a50 .delay (10000,10000,10000) L_0x2c51a50/d; +L_0x2c51b40/d .functor NAND 1, L_0x2c51110, L_0x2c51240, L_0x2c515a0, C4<1>; +L_0x2c51b40 .delay (10000,10000,10000) L_0x2c51b40/d; +L_0x2c51c20/d .functor NAND 1, L_0x2c50d10, L_0x2c519a0, L_0x2c51a50, L_0x2c51b40; +L_0x2c51c20 .delay (10000,10000,10000) L_0x2c51c20/d; +v0x2a98550_0 .net "S0", 0 0, L_0x2c51110; 1 drivers +v0x2a982d0_0 .net "S1", 0 0, L_0x2c51240; 1 drivers +v0x2a98370_0 .net "in0", 0 0, L_0x2c51370; 1 drivers +v0x2a97dd0_0 .net "in1", 0 0, L_0x2c51410; 1 drivers +v0x2a97e50_0 .net "in2", 0 0, L_0x2c514b0; 1 drivers +v0x2a99b10_0 .net "in3", 0 0, L_0x2c515a0; 1 drivers +v0x2a99bb0_0 .net "nS0", 0 0, L_0x2c50b80; 1 drivers +v0x2a99890_0 .net "nS1", 0 0, L_0x2c50c70; 1 drivers +v0x2a99930_0 .net "out", 0 0, L_0x2c51c20; 1 drivers +v0x2a99390_0 .net "out0", 0 0, L_0x2c50d10; 1 drivers +v0x2a99410_0 .net "out1", 0 0, L_0x2c519a0; 1 drivers +v0x2a9b0d0_0 .net "out2", 0 0, L_0x2c51a50; 1 drivers +v0x2a9ae50_0 .net "out3", 0 0, L_0x2c51b40; 1 drivers +S_0x2a92bb0 .scope module, "OneMux" "FourInMux" 3 293, 3 24, S_0x2a8ea90; + .timescale -9 -12; +L_0x2c51690/d .functor NOT 1, L_0x2c52d60, C4<0>, C4<0>, C4<0>; +L_0x2c51690 .delay (10000,10000,10000) L_0x2c51690/d; +L_0x2c51780/d .functor NOT 1, L_0x2c51ed0, C4<0>, C4<0>, C4<0>; +L_0x2c51780 .delay (10000,10000,10000) L_0x2c51780/d; +L_0x2c51820/d .functor NAND 1, L_0x2c51690, L_0x2c51780, L_0x2c52000, C4<1>; +L_0x2c51820 .delay (10000,10000,10000) L_0x2c51820/d; +L_0x2c527a0/d .functor NAND 1, L_0x2c52d60, L_0x2c51780, L_0x2c520a0, C4<1>; +L_0x2c527a0 .delay (10000,10000,10000) L_0x2c527a0/d; +L_0x2c52850/d .functor NAND 1, L_0x2c51690, L_0x2c51ed0, L_0x2c52140, C4<1>; +L_0x2c52850 .delay (10000,10000,10000) L_0x2c52850/d; +L_0x2c52940/d .functor NAND 1, L_0x2c52d60, L_0x2c51ed0, L_0x2c52230, C4<1>; +L_0x2c52940 .delay (10000,10000,10000) L_0x2c52940/d; +L_0x2c52ab0/d .functor NAND 1, L_0x2c51820, L_0x2c527a0, L_0x2c52850, L_0x2c52940; +L_0x2c52ab0 .delay (10000,10000,10000) L_0x2c52ab0/d; +v0x2a94410_0 .net "S0", 0 0, L_0x2c52d60; 1 drivers +v0x2a944b0_0 .net "S1", 0 0, L_0x2c51ed0; 1 drivers +v0x2a94190_0 .net "in0", 0 0, L_0x2c52000; 1 drivers +v0x2a94230_0 .net "in1", 0 0, L_0x2c520a0; 1 drivers +v0x2a93c90_0 .net "in2", 0 0, L_0x2c52140; 1 drivers +v0x2a93d30_0 .net "in3", 0 0, L_0x2c52230; 1 drivers +v0x2a95a30_0 .net "nS0", 0 0, L_0x2c51690; 1 drivers +v0x2a95750_0 .net "nS1", 0 0, L_0x2c51780; 1 drivers +v0x2a957d0_0 .net "out", 0 0, L_0x2c52ab0; 1 drivers +v0x2a95250_0 .net "out0", 0 0, L_0x2c51820; 1 drivers +v0x2a952f0_0 .net "out1", 0 0, L_0x2c527a0; 1 drivers +v0x2a96fb0_0 .net "out2", 0 0, L_0x2c52850; 1 drivers +v0x2a96d30_0 .net "out3", 0 0, L_0x2c52940; 1 drivers +S_0x2a902d0 .scope module, "TwoMux" "TwoInMux" 3 294, 3 8, S_0x2a8ea90; + .timescale -9 -12; +L_0x2c52320/d .functor NOT 1, L_0x2c537a0, C4<0>, C4<0>, C4<0>; +L_0x2c52320 .delay (10000,10000,10000) L_0x2c52320/d; +L_0x2c523d0/d .functor AND 1, L_0x2c53840, L_0x2c52320, C4<1>, C4<1>; +L_0x2c523d0 .delay (20000,20000,20000) L_0x2c523d0/d; +L_0x2c524c0/d .functor AND 1, L_0x2c52e90, L_0x2c537a0, C4<1>, C4<1>; +L_0x2c524c0 .delay (20000,20000,20000) L_0x2c524c0/d; +L_0x2c525b0/d .functor OR 1, L_0x2c523d0, L_0x2c524c0, C4<0>, C4<0>; +L_0x2c525b0 .delay (20000,20000,20000) L_0x2c525b0/d; +v0x2a90030_0 .net "S", 0 0, L_0x2c537a0; 1 drivers +v0x2a900d0_0 .net "in0", 0 0, L_0x2c53840; 1 drivers +v0x2a91890_0 .net "in1", 0 0, L_0x2c52e90; 1 drivers +v0x2a91930_0 .net "nS", 0 0, L_0x2c52320; 1 drivers +v0x2a91610_0 .net "out0", 0 0, L_0x2c523d0; 1 drivers +v0x2a916b0_0 .net "out1", 0 0, L_0x2c524c0; 1 drivers +v0x2a92eb0_0 .net "outfinal", 0 0, L_0x2c525b0; 1 drivers +S_0x2a7fe70 .scope generate, "muxbits[15]" "muxbits[15]" 3 290, 3 290, S_0x29738d0; + .timescale -9 -12; +P_0x2aa3338 .param/l "i" 3 290, +C4<01111>; +L_0x2c55070/d .functor OR 1, L_0x2c555d0, L_0x2c55670, C4<0>, C4<0>; +L_0x2c55070 .delay (20000,20000,20000) L_0x2c55070/d; +v0x2a8d550_0 .net *"_s15", 0 0, L_0x2c555d0; 1 drivers +v0x2a8ed30_0 .net *"_s16", 0 0, L_0x2c55670; 1 drivers +S_0x2a87db0 .scope module, "ZeroMux" "FourInMux" 3 292, 3 24, S_0x2a7fe70; + .timescale -9 -12; +L_0x2c532f0/d .functor NOT 1, L_0x2c54660, C4<0>, C4<0>, C4<0>; +L_0x2c532f0 .delay (10000,10000,10000) L_0x2c532f0/d; +L_0x2c533e0/d .functor NOT 1, L_0x2c53930, C4<0>, C4<0>, C4<0>; +L_0x2c533e0 .delay (10000,10000,10000) L_0x2c533e0/d; +L_0x2c53480/d .functor NAND 1, L_0x2c532f0, L_0x2c533e0, L_0x2c53a60, C4<1>; +L_0x2c53480 .delay (10000,10000,10000) L_0x2c53480/d; +L_0x2c535c0/d .functor NAND 1, L_0x2c54660, L_0x2c533e0, L_0x2c53b00, C4<1>; +L_0x2c535c0 .delay (10000,10000,10000) L_0x2c535c0/d; +L_0x2c536b0/d .functor NAND 1, L_0x2c532f0, L_0x2c53930, L_0x2c53ba0, C4<1>; +L_0x2c536b0 .delay (10000,10000,10000) L_0x2c536b0/d; +L_0x2c54270/d .functor NAND 1, L_0x2c54660, L_0x2c53930, L_0x2c53c90, C4<1>; +L_0x2c54270 .delay (10000,10000,10000) L_0x2c54270/d; +L_0x2c543b0/d .functor NAND 1, L_0x2c53480, L_0x2c535c0, L_0x2c536b0, L_0x2c54270; +L_0x2c543b0 .delay (10000,10000,10000) L_0x2c543b0/d; +v0x2a89610_0 .net "S0", 0 0, L_0x2c54660; 1 drivers +v0x2a896b0_0 .net "S1", 0 0, L_0x2c53930; 1 drivers +v0x2a89390_0 .net "in0", 0 0, L_0x2c53a60; 1 drivers +v0x2a89430_0 .net "in1", 0 0, L_0x2c53b00; 1 drivers +v0x2a8abd0_0 .net "in2", 0 0, L_0x2c53ba0; 1 drivers +v0x2a8ac70_0 .net "in3", 0 0, L_0x2c53c90; 1 drivers +v0x2a8a950_0 .net "nS0", 0 0, L_0x2c532f0; 1 drivers +v0x2a8c190_0 .net "nS1", 0 0, L_0x2c533e0; 1 drivers +v0x2a8c230_0 .net "out", 0 0, L_0x2c543b0; 1 drivers +v0x2a8bf10_0 .net "out0", 0 0, L_0x2c53480; 1 drivers +v0x2a8bfb0_0 .net "out1", 0 0, L_0x2c535c0; 1 drivers +v0x2a8d750_0 .net "out2", 0 0, L_0x2c536b0; 1 drivers +v0x2a8d4b0_0 .net "out3", 0 0, L_0x2c54270; 1 drivers +S_0x2a826d0 .scope module, "OneMux" "FourInMux" 3 293, 3 24, S_0x2a7fe70; + .timescale -9 -12; +L_0x2c53d80/d .functor NOT 1, L_0x2c54790, C4<0>, C4<0>, C4<0>; +L_0x2c53d80 .delay (10000,10000,10000) L_0x2c53d80/d; +L_0x2c53e30/d .functor NOT 1, L_0x2c548c0, C4<0>, C4<0>, C4<0>; +L_0x2c53e30 .delay (10000,10000,10000) L_0x2c53e30/d; +L_0x2c53ed0/d .functor NAND 1, L_0x2c53d80, L_0x2c53e30, L_0x2c549f0, C4<1>; +L_0x2c53ed0 .delay (10000,10000,10000) L_0x2c53ed0/d; +L_0x2c54010/d .functor NAND 1, L_0x2c54790, L_0x2c53e30, L_0x2c082f0, C4<1>; +L_0x2c54010 .delay (10000,10000,10000) L_0x2c54010/d; +L_0x2c54100/d .functor NAND 1, L_0x2c53d80, L_0x2c548c0, L_0x2c08390, C4<1>; +L_0x2c54100 .delay (10000,10000,10000) L_0x2c54100/d; +L_0x2c55100/d .functor NAND 1, L_0x2c54790, L_0x2c548c0, L_0x2c08480, C4<1>; +L_0x2c55100 .delay (10000,10000,10000) L_0x2c55100/d; +L_0x2c55240/d .functor NAND 1, L_0x2c53ed0, L_0x2c54010, L_0x2c54100, L_0x2c55100; +L_0x2c55240 .delay (10000,10000,10000) L_0x2c55240/d; +v0x2a829f0_0 .net "S0", 0 0, L_0x2c54790; 1 drivers +v0x2a83f10_0 .net "S1", 0 0, L_0x2c548c0; 1 drivers +v0x2a83f90_0 .net "in0", 0 0, L_0x2c549f0; 1 drivers +v0x2a83c90_0 .net "in1", 0 0, L_0x2c082f0; 1 drivers +v0x2a83d30_0 .net "in2", 0 0, L_0x2c08390; 1 drivers +v0x2a854d0_0 .net "in3", 0 0, L_0x2c08480; 1 drivers +v0x2a85570_0 .net "nS0", 0 0, L_0x2c53d80; 1 drivers +v0x2a85250_0 .net "nS1", 0 0, L_0x2c53e30; 1 drivers +v0x2a86a90_0 .net "out", 0 0, L_0x2c55240; 1 drivers +v0x2a86b30_0 .net "out0", 0 0, L_0x2c53ed0; 1 drivers +v0x2a86810_0 .net "out1", 0 0, L_0x2c54010; 1 drivers +v0x2a868b0_0 .net "out2", 0 0, L_0x2c54100; 1 drivers +v0x2a880e0_0 .net "out3", 0 0, L_0x2c55100; 1 drivers +S_0x2a7fbf0 .scope module, "TwoMux" "TwoInMux" 3 294, 3 8, S_0x2a7fe70; + .timescale -9 -12; +L_0x2a852d0/d .functor NOT 1, L_0x2c54d50, C4<0>, C4<0>, C4<0>; +L_0x2a852d0 .delay (10000,10000,10000) L_0x2a852d0/d; +L_0x2c08600/d .functor AND 1, L_0x2c54df0, L_0x2a852d0, C4<1>, C4<1>; +L_0x2c08600 .delay (20000,20000,20000) L_0x2c08600/d; +L_0x2c086a0/d .functor AND 1, L_0x2c54ee0, L_0x2c54d50, C4<1>, C4<1>; +L_0x2c086a0 .delay (20000,20000,20000) L_0x2c086a0/d; +L_0x2c54b70/d .functor OR 1, L_0x2c08600, L_0x2c086a0, C4<0>, C4<0>; +L_0x2c54b70 .delay (20000,20000,20000) L_0x2c54b70/d; +v0x2a7f6f0_0 .net "S", 0 0, L_0x2c54d50; 1 drivers +v0x2a7f790_0 .net "in0", 0 0, L_0x2c54df0; 1 drivers +v0x2a81430_0 .net "in1", 0 0, L_0x2c54ee0; 1 drivers +v0x2a814d0_0 .net "nS", 0 0, L_0x2a852d0; 1 drivers +v0x2a811d0_0 .net "out0", 0 0, L_0x2c08600; 1 drivers +v0x2a80cb0_0 .net "out1", 0 0, L_0x2c086a0; 1 drivers +v0x2a82950_0 .net "outfinal", 0 0, L_0x2c54b70; 1 drivers +S_0x2a6c960 .scope generate, "muxbits[16]" "muxbits[16]" 3 290, 3 290, S_0x29738d0; + .timescale -9 -12; +P_0x2a569f8 .param/l "i" 3 290, +C4<010000>; +L_0x2c44580/d .functor OR 1, L_0x2c446c0, L_0x2c589a0, C4<0>, C4<0>; +L_0x2c44580 .delay (20000,20000,20000) L_0x2c44580/d; +v0x2a7e6d0_0 .net *"_s15", 0 0, L_0x2c446c0; 1 drivers +v0x2a7e130_0 .net *"_s16", 0 0, L_0x2c589a0; 1 drivers +S_0x2a7a4f0 .scope module, "ZeroMux" "FourInMux" 3 292, 3 24, S_0x2a6c960; + .timescale -9 -12; +L_0x2c55760/d .functor NOT 1, L_0x2c56690, C4<0>, C4<0>, C4<0>; +L_0x2c55760 .delay (10000,10000,10000) L_0x2c55760/d; +L_0x2c55850/d .functor NOT 1, L_0x2c567c0, C4<0>, C4<0>, C4<0>; +L_0x2c55850 .delay (10000,10000,10000) L_0x2c55850/d; +L_0x2c558f0/d .functor NAND 1, L_0x2c55760, L_0x2c55850, L_0x2c568f0, C4<1>; +L_0x2c558f0 .delay (10000,10000,10000) L_0x2c558f0/d; +L_0x2c55a30/d .functor NAND 1, L_0x2c56690, L_0x2c55850, L_0x2c56990, C4<1>; +L_0x2c55a30 .delay (10000,10000,10000) L_0x2c55a30/d; +L_0x2c55b20/d .functor NAND 1, L_0x2c55760, L_0x2c567c0, L_0x2c56a30, C4<1>; +L_0x2c55b20 .delay (10000,10000,10000) L_0x2c55b20/d; +L_0x2c55c10/d .functor NAND 1, L_0x2c56690, L_0x2c567c0, L_0x2c56b20, C4<1>; +L_0x2c55c10 .delay (10000,10000,10000) L_0x2c55c10/d; +L_0x2c55d20/d .functor NAND 1, L_0x2c558f0, L_0x2c55a30, L_0x2c55b20, L_0x2c55c10; +L_0x2c55d20 .delay (10000,10000,10000) L_0x2c55d20/d; +v0x2a7bd30_0 .net "S0", 0 0, L_0x2c56690; 1 drivers +v0x2a7bab0_0 .net "S1", 0 0, L_0x2c567c0; 1 drivers +v0x2a7bb50_0 .net "in0", 0 0, L_0x2c568f0; 1 drivers +v0x2a7b5b0_0 .net "in1", 0 0, L_0x2c56990; 1 drivers +v0x2a7b630_0 .net "in2", 0 0, L_0x2c56a30; 1 drivers +v0x2a7d2f0_0 .net "in3", 0 0, L_0x2c56b20; 1 drivers +v0x2a7d390_0 .net "nS0", 0 0, L_0x2c55760; 1 drivers +v0x2a7d070_0 .net "nS1", 0 0, L_0x2c55850; 1 drivers +v0x2a7d110_0 .net "out", 0 0, L_0x2c55d20; 1 drivers +v0x2a7cb70_0 .net "out0", 0 0, L_0x2c558f0; 1 drivers +v0x2a7cbf0_0 .net "out1", 0 0, L_0x2c55a30; 1 drivers +v0x2a7e8b0_0 .net "out2", 0 0, L_0x2c55b20; 1 drivers +v0x2a7e630_0 .net "out3", 0 0, L_0x2c55c10; 1 drivers +S_0x2a6d870 .scope module, "OneMux" "FourInMux" 3 293, 3 24, S_0x2a6c960; + .timescale -9 -12; +L_0x2c56c10/d .functor NOT 1, L_0x2c58050, C4<0>, C4<0>, C4<0>; +L_0x2c56c10 .delay (10000,10000,10000) L_0x2c56c10/d; +L_0x2c56d00/d .functor NOT 1, L_0x2c571f0, C4<0>, C4<0>, C4<0>; +L_0x2c56d00 .delay (10000,10000,10000) L_0x2c56d00/d; +L_0x2c56da0/d .functor NAND 1, L_0x2c56c10, L_0x2c56d00, L_0x2c57320, C4<1>; +L_0x2c56da0 .delay (10000,10000,10000) L_0x2c56da0/d; +L_0x2c56ee0/d .functor NAND 1, L_0x2c58050, L_0x2c56d00, L_0x2c573c0, C4<1>; +L_0x2c56ee0 .delay (10000,10000,10000) L_0x2c56ee0/d; +L_0x2c56fd0/d .functor NAND 1, L_0x2c56c10, L_0x2c571f0, L_0x2c57460, C4<1>; +L_0x2c56fd0 .delay (10000,10000,10000) L_0x2c56fd0/d; +L_0x2c57c60/d .functor NAND 1, L_0x2c58050, L_0x2c571f0, L_0x2c57550, C4<1>; +L_0x2c57c60 .delay (10000,10000,10000) L_0x2c57c60/d; +L_0x2c57da0/d .functor NAND 1, L_0x2c56da0, L_0x2c56ee0, L_0x2c56fd0, L_0x2c57c60; +L_0x2c57da0 .delay (10000,10000,10000) L_0x2c57da0/d; +v0x2a72560_0 .net "S0", 0 0, L_0x2c58050; 1 drivers +v0x2a72600_0 .net "S1", 0 0, L_0x2c571f0; 1 drivers +v0x2a722b0_0 .net "in0", 0 0, L_0x2c57320; 1 drivers +v0x2a72350_0 .net "in1", 0 0, L_0x2c573c0; 1 drivers +v0x2a70670_0 .net "in2", 0 0, L_0x2c57460; 1 drivers +v0x2a70710_0 .net "in3", 0 0, L_0x2c57550; 1 drivers +v0x2aa3390_0 .net "nS0", 0 0, L_0x2c56c10; 1 drivers +v0x2aa30c0_0 .net "nS1", 0 0, L_0x2c56d00; 1 drivers +v0x2aa3140_0 .net "out", 0 0, L_0x2c57da0; 1 drivers +v0x2aa2bd0_0 .net "out0", 0 0, L_0x2c56da0; 1 drivers +v0x2aa2c70_0 .net "out1", 0 0, L_0x2c56ee0; 1 drivers +v0x2a78ea0_0 .net "out2", 0 0, L_0x2c56fd0; 1 drivers +v0x2a7a790_0 .net "out3", 0 0, L_0x2c57c60; 1 drivers +S_0x2a6c6b0 .scope module, "TwoMux" "TwoInMux" 3 294, 3 8, S_0x2a6c960; + .timescale -9 -12; +L_0x2c57640/d .functor NOT 1, L_0x2c57ab0, C4<0>, C4<0>, C4<0>; +L_0x2c57640 .delay (10000,10000,10000) L_0x2c57640/d; +L_0x2c576f0/d .functor AND 1, L_0x2c57b50, L_0x2c57640, C4<1>, C4<1>; +L_0x2c576f0 .delay (20000,20000,20000) L_0x2c576f0/d; +L_0x2c577e0/d .functor AND 1, L_0x2c43e90, L_0x2c57ab0, C4<1>, C4<1>; +L_0x2c577e0 .delay (20000,20000,20000) L_0x2c577e0/d; +L_0x2c578d0/d .functor OR 1, L_0x2c576f0, L_0x2c577e0, C4<0>, C4<0>; +L_0x2c578d0 .delay (20000,20000,20000) L_0x2c578d0/d; +v0x2a6aa70_0 .net "S", 0 0, L_0x2c57ab0; 1 drivers +v0x2a6ab10_0 .net "in0", 0 0, L_0x2c57b50; 1 drivers +v0x2a6f9c0_0 .net "in1", 0 0, L_0x2c43e90; 1 drivers +v0x2a6fa60_0 .net "nS", 0 0, L_0x2c57640; 1 drivers +v0x2a6f760_0 .net "out0", 0 0, L_0x2c576f0; 1 drivers +v0x2a6f800_0 .net "out1", 0 0, L_0x2c577e0; 1 drivers +v0x2a6f510_0 .net "outfinal", 0 0, L_0x2c578d0; 1 drivers +S_0x2a55760 .scope generate, "muxbits[17]" "muxbits[17]" 3 290, 3 290, S_0x29738d0; + .timescale -9 -12; +P_0x2a4a1d8 .param/l "i" 3 290, +C4<010001>; +L_0x2c5b0c0/d .functor OR 1, L_0x2c5b200, L_0x2c5b2a0, C4<0>, C4<0>; +L_0x2c5b0c0 .delay (20000,20000,20000) L_0x2c5b0c0/d; +v0x2a67d10_0 .net *"_s15", 0 0, L_0x2c5b200; 1 drivers +v0x2a6cbe0_0 .net *"_s16", 0 0, L_0x2c5b2a0; 1 drivers +S_0x2a63f60 .scope module, "ZeroMux" "FourInMux" 3 292, 3 24, S_0x2a55760; + .timescale -9 -12; +L_0x2c58a90/d .functor NOT 1, L_0x2c5a1b0, C4<0>, C4<0>, C4<0>; +L_0x2c58a90 .delay (10000,10000,10000) L_0x2c58a90/d; +L_0x2c59a70/d .functor NOT 1, L_0x2c58fe0, C4<0>, C4<0>, C4<0>; +L_0x2c59a70 .delay (10000,10000,10000) L_0x2c59a70/d; +L_0x2c59ad0/d .functor NAND 1, L_0x2c58a90, L_0x2c59a70, L_0x2c59110, C4<1>; +L_0x2c59ad0 .delay (10000,10000,10000) L_0x2c59ad0/d; +L_0x2c59c10/d .functor NAND 1, L_0x2c5a1b0, L_0x2c59a70, L_0x2c591b0, C4<1>; +L_0x2c59c10 .delay (10000,10000,10000) L_0x2c59c10/d; +L_0x2c59d00/d .functor NAND 1, L_0x2c58a90, L_0x2c58fe0, L_0x2c59250, C4<1>; +L_0x2c59d00 .delay (10000,10000,10000) L_0x2c59d00/d; +L_0x2c59df0/d .functor NAND 1, L_0x2c5a1b0, L_0x2c58fe0, L_0x2c59340, C4<1>; +L_0x2c59df0 .delay (10000,10000,10000) L_0x2c59df0/d; +L_0x2c59f00/d .functor NAND 1, L_0x2c59ad0, L_0x2c59c10, L_0x2c59d00, L_0x2c59df0; +L_0x2c59f00 .delay (10000,10000,10000) L_0x2c59f00/d; +v0x2a66fc0_0 .net "S0", 0 0, L_0x2c5a1b0; 1 drivers +v0x2a67060_0 .net "S1", 0 0, L_0x2c58fe0; 1 drivers +v0x2a66d60_0 .net "in0", 0 0, L_0x2c59110; 1 drivers +v0x2a66e00_0 .net "in1", 0 0, L_0x2c591b0; 1 drivers +v0x2a66ab0_0 .net "in2", 0 0, L_0x2c59250; 1 drivers +v0x2a66b50_0 .net "in3", 0 0, L_0x2c59340; 1 drivers +v0x2a64e90_0 .net "nS0", 0 0, L_0x2c58a90; 1 drivers +v0x2a69dc0_0 .net "nS1", 0 0, L_0x2c59a70; 1 drivers +v0x2a69e60_0 .net "out", 0 0, L_0x2c59f00; 1 drivers +v0x2a69b60_0 .net "out0", 0 0, L_0x2c59ad0; 1 drivers +v0x2a69c00_0 .net "out1", 0 0, L_0x2c59c10; 1 drivers +v0x2a698b0_0 .net "out2", 0 0, L_0x2c59d00; 1 drivers +v0x2a67c70_0 .net "out3", 0 0, L_0x2c59df0; 1 drivers +S_0x2a59750 .scope module, "OneMux" "FourInMux" 3 293, 3 24, S_0x2a55760; + .timescale -9 -12; +L_0x2c59430/d .functor NOT 1, L_0x2c5a2e0, C4<0>, C4<0>, C4<0>; +L_0x2c59430 .delay (10000,10000,10000) L_0x2c59430/d; +L_0x2c594e0/d .functor NOT 1, L_0x2c5a410, C4<0>, C4<0>, C4<0>; +L_0x2c594e0 .delay (10000,10000,10000) L_0x2c594e0/d; +L_0x2c59580/d .functor NAND 1, L_0x2c59430, L_0x2c594e0, L_0x2c5a540, C4<1>; +L_0x2c59580 .delay (10000,10000,10000) L_0x2c59580/d; +L_0x2c596c0/d .functor NAND 1, L_0x2c5a2e0, L_0x2c594e0, L_0x2c5a5e0, C4<1>; +L_0x2c596c0 .delay (10000,10000,10000) L_0x2c596c0/d; +L_0x2c597b0/d .functor NAND 1, L_0x2c59430, L_0x2c5a410, L_0x2c5a680, C4<1>; +L_0x2c597b0 .delay (10000,10000,10000) L_0x2c597b0/d; +L_0x2c598d0/d .functor NAND 1, L_0x2c5a2e0, L_0x2c5a410, L_0x2c5a770, C4<1>; +L_0x2c598d0 .delay (10000,10000,10000) L_0x2c598d0/d; +L_0x2c5ada0/d .functor NAND 1, L_0x2c59580, L_0x2c596c0, L_0x2c597b0, L_0x2c598d0; +L_0x2c5ada0 .delay (10000,10000,10000) L_0x2c5ada0/d; +v0x2a5b480_0 .net "S0", 0 0, L_0x2c5a2e0; 1 drivers +v0x2a5e4d0_0 .net "S1", 0 0, L_0x2c5a410; 1 drivers +v0x2a5e550_0 .net "in0", 0 0, L_0x2c5a540; 1 drivers +v0x2a5e220_0 .net "in1", 0 0, L_0x2c5a5e0; 1 drivers +v0x2a5e2c0_0 .net "in2", 0 0, L_0x2c5a680; 1 drivers +v0x2a5c590_0 .net "in3", 0 0, L_0x2c5a770; 1 drivers +v0x2a5c630_0 .net "nS0", 0 0, L_0x2c59430; 1 drivers +v0x2a61330_0 .net "nS1", 0 0, L_0x2c594e0; 1 drivers +v0x2a61060_0 .net "out", 0 0, L_0x2c5ada0; 1 drivers +v0x2a61100_0 .net "out0", 0 0, L_0x2c59580; 1 drivers +v0x2a5f3d0_0 .net "out1", 0 0, L_0x2c596c0; 1 drivers +v0x2a5f470_0 .net "out2", 0 0, L_0x2c597b0; 1 drivers +v0x2a64250_0 .net "out3", 0 0, L_0x2c598d0; 1 drivers +S_0x2a53ad0 .scope module, "TwoMux" "TwoInMux" 3 294, 3 8, S_0x2a55760; + .timescale -9 -12; +L_0x2a613b0/d .functor NOT 1, L_0x2c5acb0, C4<0>, C4<0>, C4<0>; +L_0x2a613b0 .delay (10000,10000,10000) L_0x2a613b0/d; +L_0x2c5a8f0/d .functor AND 1, L_0x2c5bb30, L_0x2a613b0, C4<1>, C4<1>; +L_0x2c5a8f0 .delay (20000,20000,20000) L_0x2c5a8f0/d; +L_0x2c5a9e0/d .functor AND 1, L_0x2c5bbd0, L_0x2c5acb0, C4<1>, C4<1>; +L_0x2c5a9e0 .delay (20000,20000,20000) L_0x2c5a9e0/d; +L_0x2c5aad0/d .functor OR 1, L_0x2c5a8f0, L_0x2c5a9e0, C4<0>, C4<0>; +L_0x2c5aad0 .delay (20000,20000,20000) L_0x2c5aad0/d; +v0x2a58850_0 .net "S", 0 0, L_0x2c5acb0; 1 drivers +v0x2a588f0_0 .net "in0", 0 0, L_0x2c5bb30; 1 drivers +v0x2a585a0_0 .net "in1", 0 0, L_0x2c5bbd0; 1 drivers +v0x2a58640_0 .net "nS", 0 0, L_0x2a613b0; 1 drivers +v0x2a56930_0 .net "out0", 0 0, L_0x2c5a8f0; 1 drivers +v0x2a5b690_0 .net "out1", 0 0, L_0x2c5a9e0; 1 drivers +v0x2a5b3e0_0 .net "outfinal", 0 0, L_0x2c5aad0; 1 drivers +S_0x2a3fab0 .scope generate, "muxbits[18]" "muxbits[18]" 3 290, 3 290, S_0x29738d0; + .timescale -9 -12; +P_0x2a30548 .param/l "i" 3 290, +C4<010010>; +L_0x2c5d8b0/d .functor OR 1, L_0x2c5d9f0, L_0x2c5da90, C4<0>, C4<0>; +L_0x2c5d8b0 .delay (20000,20000,20000) L_0x2c5d8b0/d; +v0x2a50d80_0 .net *"_s15", 0 0, L_0x2c5d9f0; 1 drivers +v0x2a55a10_0 .net *"_s16", 0 0, L_0x2c5da90; 1 drivers +S_0x2a4cd20 .scope module, "ZeroMux" "FourInMux" 3 292, 3 24, S_0x2a3fab0; + .timescale -9 -12; +L_0x2c5b390/d .functor NOT 1, L_0x2c5bcc0, C4<0>, C4<0>, C4<0>; +L_0x2c5b390 .delay (10000,10000,10000) L_0x2c5b390/d; +L_0x2c5b480/d .functor NOT 1, L_0x2c5bdf0, C4<0>, C4<0>, C4<0>; +L_0x2c5b480 .delay (10000,10000,10000) L_0x2c5b480/d; +L_0x2c5b520/d .functor NAND 1, L_0x2c5b390, L_0x2c5b480, L_0x2c5bf20, C4<1>; +L_0x2c5b520 .delay (10000,10000,10000) L_0x2c5b520/d; +L_0x2c5b660/d .functor NAND 1, L_0x2c5bcc0, L_0x2c5b480, L_0x2c5bfc0, C4<1>; +L_0x2c5b660 .delay (10000,10000,10000) L_0x2c5b660/d; +L_0x2c5b750/d .functor NAND 1, L_0x2c5b390, L_0x2c5bdf0, L_0x2c5c060, C4<1>; +L_0x2c5b750 .delay (10000,10000,10000) L_0x2c5b750/d; +L_0x2c5b840/d .functor NAND 1, L_0x2c5bcc0, L_0x2c5bdf0, L_0x2c5c150, C4<1>; +L_0x2c5b840 .delay (10000,10000,10000) L_0x2c5b840/d; +L_0x2c5b980/d .functor NAND 1, L_0x2c5b520, L_0x2c5b660, L_0x2c5b750, L_0x2c5b840; +L_0x2c5b980 .delay (10000,10000,10000) L_0x2c5b980/d; +v0x2a4b0e0_0 .net "S0", 0 0, L_0x2c5bcc0; 1 drivers +v0x2a50030_0 .net "S1", 0 0, L_0x2c5bdf0; 1 drivers +v0x2a500d0_0 .net "in0", 0 0, L_0x2c5bf20; 1 drivers +v0x2a4fdd0_0 .net "in1", 0 0, L_0x2c5bfc0; 1 drivers +v0x2a4fe50_0 .net "in2", 0 0, L_0x2c5c060; 1 drivers +v0x2a4fb20_0 .net "in3", 0 0, L_0x2c5c150; 1 drivers +v0x2a4fbc0_0 .net "nS0", 0 0, L_0x2c5b390; 1 drivers +v0x2a4dee0_0 .net "nS1", 0 0, L_0x2c5b480; 1 drivers +v0x2a4df80_0 .net "out", 0 0, L_0x2c5b980; 1 drivers +v0x2a52bd0_0 .net "out0", 0 0, L_0x2c5b520; 1 drivers +v0x2a52c50_0 .net "out1", 0 0, L_0x2c5b660; 1 drivers +v0x2a52920_0 .net "out2", 0 0, L_0x2c5b750; 1 drivers +v0x2a50ce0_0 .net "out3", 0 0, L_0x2c5b840; 1 drivers +S_0x2a473d0 .scope module, "OneMux" "FourInMux" 3 293, 3 24, S_0x2a3fab0; + .timescale -9 -12; +L_0x2c5c240/d .functor NOT 1, L_0x2c5d780, C4<0>, C4<0>, C4<0>; +L_0x2c5c240 .delay (10000,10000,10000) L_0x2c5c240/d; +L_0x2c5c330/d .functor NOT 1, L_0x2c5c920, C4<0>, C4<0>, C4<0>; +L_0x2c5c330 .delay (10000,10000,10000) L_0x2c5c330/d; +L_0x2c5c3d0/d .functor NAND 1, L_0x2c5c240, L_0x2c5c330, L_0x2c5ca50, C4<1>; +L_0x2c5c3d0 .delay (10000,10000,10000) L_0x2c5c3d0/d; +L_0x2c5c510/d .functor NAND 1, L_0x2c5d780, L_0x2c5c330, L_0x2c5caf0, C4<1>; +L_0x2c5c510 .delay (10000,10000,10000) L_0x2c5c510/d; +L_0x2c5c600/d .functor NAND 1, L_0x2c5c240, L_0x2c5c920, L_0x2c5cb90, C4<1>; +L_0x2c5c600 .delay (10000,10000,10000) L_0x2c5c600/d; +L_0x2c5c6f0/d .functor NAND 1, L_0x2c5d780, L_0x2c5c920, L_0x2c5cc80, C4<1>; +L_0x2c5c6f0 .delay (10000,10000,10000) L_0x2c5c6f0/d; +L_0x2c5d4d0/d .functor NAND 1, L_0x2c5c3d0, L_0x2c5c510, L_0x2c5c600, L_0x2c5c6f0; +L_0x2c5d4d0 .delay (10000,10000,10000) L_0x2c5d4d0/d; +v0x2a47120_0 .net "S0", 0 0, L_0x2c5d780; 1 drivers +v0x2a471c0_0 .net "S1", 0 0, L_0x2c5c920; 1 drivers +v0x2a454e0_0 .net "in0", 0 0, L_0x2c5ca50; 1 drivers +v0x2a45580_0 .net "in1", 0 0, L_0x2c5caf0; 1 drivers +v0x2a4a430_0 .net "in2", 0 0, L_0x2c5cb90; 1 drivers +v0x2a4a4d0_0 .net "in3", 0 0, L_0x2c5cc80; 1 drivers +v0x2a4a230_0 .net "nS0", 0 0, L_0x2c5c240; 1 drivers +v0x2a49f20_0 .net "nS1", 0 0, L_0x2c5c330; 1 drivers +v0x2a49fa0_0 .net "out", 0 0, L_0x2c5d4d0; 1 drivers +v0x2a482e0_0 .net "out0", 0 0, L_0x2c5c3d0; 1 drivers +v0x2a48380_0 .net "out1", 0 0, L_0x2c5c510; 1 drivers +v0x2a4d250_0 .net "out2", 0 0, L_0x2c5c600; 1 drivers +v0x2a4cff0_0 .net "out3", 0 0, L_0x2c5c6f0; 1 drivers +S_0x2a44830 .scope module, "TwoMux" "TwoInMux" 3 294, 3 8, S_0x2a3fab0; + .timescale -9 -12; +L_0x2c5cd70/d .functor NOT 1, L_0x2c5d1e0, C4<0>, C4<0>, C4<0>; +L_0x2c5cd70 .delay (10000,10000,10000) L_0x2c5cd70/d; +L_0x2c5ce20/d .functor AND 1, L_0x2c5d280, L_0x2c5cd70, C4<1>, C4<1>; +L_0x2c5ce20 .delay (20000,20000,20000) L_0x2c5ce20/d; +L_0x2c5cf10/d .functor AND 1, L_0x2c5d370, L_0x2c5d1e0, C4<1>, C4<1>; +L_0x2c5cf10 .delay (20000,20000,20000) L_0x2c5cf10/d; +L_0x2c5d000/d .functor OR 1, L_0x2c5ce20, L_0x2c5cf10, C4<0>, C4<0>; +L_0x2c5d000 .delay (20000,20000,20000) L_0x2c5d000/d; +v0x2a445d0_0 .net "S", 0 0, L_0x2c5d1e0; 1 drivers +v0x2a44670_0 .net "in0", 0 0, L_0x2c5d280; 1 drivers +v0x2a44320_0 .net "in1", 0 0, L_0x2c5d370; 1 drivers +v0x2a443c0_0 .net "nS", 0 0, L_0x2c5cd70; 1 drivers +v0x2a426e0_0 .net "out0", 0 0, L_0x2c5ce20; 1 drivers +v0x2a42780_0 .net "out1", 0 0, L_0x2c5cf10; 1 drivers +v0x2a47690_0 .net "outfinal", 0 0, L_0x2c5d000; 1 drivers +S_0x2a2d660 .scope generate, "muxbits[19]" "muxbits[19]" 3 290, 3 290, S_0x29738d0; + .timescale -9 -12; +P_0x2a21e68 .param/l "i" 3 290, +C4<010011>; +L_0x2c60c30/d .functor OR 1, L_0x2c60d70, L_0x2c5ff20, C4<0>, C4<0>; +L_0x2c60c30 .delay (20000,20000,20000) L_0x2c60c30/d; +v0x2a41870_0 .net *"_s15", 0 0, L_0x2c60d70; 1 drivers +v0x2a41540_0 .net *"_s16", 0 0, L_0x2c5ff20; 1 drivers +S_0x2a36ff0 .scope module, "ZeroMux" "FourInMux" 3 292, 3 24, S_0x2a2d660; + .timescale -9 -12; +L_0x2c5db80/d .functor NOT 1, L_0x2c5f0f0, C4<0>, C4<0>, C4<0>; +L_0x2c5db80 .delay (10000,10000,10000) L_0x2c5db80/d; +L_0x2c5dc70/d .functor NOT 1, L_0x2c5e510, C4<0>, C4<0>, C4<0>; +L_0x2c5dc70 .delay (10000,10000,10000) L_0x2c5dc70/d; +L_0x2c5dd10/d .functor NAND 1, L_0x2c5db80, L_0x2c5dc70, L_0x2c5e640, C4<1>; +L_0x2c5dd10 .delay (10000,10000,10000) L_0x2c5dd10/d; +L_0x2c5de50/d .functor NAND 1, L_0x2c5f0f0, L_0x2c5dc70, L_0x2c5e6e0, C4<1>; +L_0x2c5de50 .delay (10000,10000,10000) L_0x2c5de50/d; +L_0x2c5df40/d .functor NAND 1, L_0x2c5db80, L_0x2c5e510, L_0x2c5e780, C4<1>; +L_0x2c5df40 .delay (10000,10000,10000) L_0x2c5df40/d; +L_0x2c5e030/d .functor NAND 1, L_0x2c5f0f0, L_0x2c5e510, L_0x2c5e870, C4<1>; +L_0x2c5e030 .delay (10000,10000,10000) L_0x2c5e030/d; +L_0x2c5e140/d .functor NAND 1, L_0x2c5dd10, L_0x2c5de50, L_0x2c5df40, L_0x2c5e030; +L_0x2c5e140 .delay (10000,10000,10000) L_0x2c5e140/d; +v0x2a3bd70_0 .net "S0", 0 0, L_0x2c5f0f0; 1 drivers +v0x2a3be10_0 .net "S1", 0 0, L_0x2c5e510; 1 drivers +v0x2a3bac0_0 .net "in0", 0 0, L_0x2c5e640; 1 drivers +v0x2a3bb60_0 .net "in1", 0 0, L_0x2c5e6e0; 1 drivers +v0x2a39e30_0 .net "in2", 0 0, L_0x2c5e780; 1 drivers +v0x2a39ed0_0 .net "in3", 0 0, L_0x2c5e870; 1 drivers +v0x2a3ebd0_0 .net "nS0", 0 0, L_0x2c5db80; 1 drivers +v0x2a3e900_0 .net "nS1", 0 0, L_0x2c5dc70; 1 drivers +v0x2a3e9a0_0 .net "out", 0 0, L_0x2c5e140; 1 drivers +v0x2a3cc70_0 .net "out0", 0 0, L_0x2c5dd10; 1 drivers +v0x2a3cd10_0 .net "out1", 0 0, L_0x2c5de50; 1 drivers +v0x2a41a30_0 .net "out2", 0 0, L_0x2c5df40; 1 drivers +v0x2a417d0_0 .net "out3", 0 0, L_0x2c5e030; 1 drivers +S_0x2a332b0 .scope module, "OneMux" "FourInMux" 3 293, 3 24, S_0x2a2d660; + .timescale -9 -12; +L_0x2c5e960/d .functor NOT 1, L_0x2c5f220, C4<0>, C4<0>, C4<0>; +L_0x2c5e960 .delay (10000,10000,10000) L_0x2c5e960/d; +L_0x2c5ea10/d .functor NOT 1, L_0x2c5f350, C4<0>, C4<0>, C4<0>; +L_0x2c5ea10 .delay (10000,10000,10000) L_0x2c5ea10/d; +L_0x2c5eab0/d .functor NAND 1, L_0x2c5e960, L_0x2c5ea10, L_0x2c5f480, C4<1>; +L_0x2c5eab0 .delay (10000,10000,10000) L_0x2c5eab0/d; +L_0x2c5ebf0/d .functor NAND 1, L_0x2c5f220, L_0x2c5ea10, L_0x2c5f520, C4<1>; +L_0x2c5ebf0 .delay (10000,10000,10000) L_0x2c5ebf0/d; +L_0x2c5ece0/d .functor NAND 1, L_0x2c5e960, L_0x2c5f350, L_0x2c5f5c0, C4<1>; +L_0x2c5ece0 .delay (10000,10000,10000) L_0x2c5ece0/d; +L_0x2c5ee00/d .functor NAND 1, L_0x2c5f220, L_0x2c5f350, L_0x2c5f6b0, C4<1>; +L_0x2c5ee00 .delay (10000,10000,10000) L_0x2c5ee00/d; +L_0x2c5ef70/d .functor NAND 1, L_0x2c5eab0, L_0x2c5ebf0, L_0x2c5ece0, L_0x2c5ee00; +L_0x2c5ef70 .delay (10000,10000,10000) L_0x2c5ef70/d; +v0x2a2e610_0 .net "S0", 0 0, L_0x2c5f220; 1 drivers +v0x2a33000_0 .net "S1", 0 0, L_0x2c5f350; 1 drivers +v0x2a33080_0 .net "in0", 0 0, L_0x2c5f480; 1 drivers +v0x2a31370_0 .net "in1", 0 0, L_0x2c5f520; 1 drivers +v0x2a31410_0 .net "in2", 0 0, L_0x2c5f5c0; 1 drivers +v0x2a360f0_0 .net "in3", 0 0, L_0x2c5f6b0; 1 drivers +v0x2a36190_0 .net "nS0", 0 0, L_0x2c5e960; 1 drivers +v0x2a35e60_0 .net "nS1", 0 0, L_0x2c5ea10; 1 drivers +v0x2a341b0_0 .net "out", 0 0, L_0x2c5ef70; 1 drivers +v0x2a34250_0 .net "out0", 0 0, L_0x2c5eab0; 1 drivers +v0x2a38f30_0 .net "out1", 0 0, L_0x2c5ebf0; 1 drivers +v0x2a38fd0_0 .net "out2", 0 0, L_0x2c5ece0; 1 drivers +v0x2a38d10_0 .net "out3", 0 0, L_0x2c5ee00; 1 drivers +S_0x2a2d3b0 .scope module, "TwoMux" "TwoInMux" 3 294, 3 8, S_0x2a2d660; + .timescale -9 -12; +L_0x2a35ee0/d .functor NOT 1, L_0x2c5fbb0, C4<0>, C4<0>, C4<0>; +L_0x2a35ee0 .delay (10000,10000,10000) L_0x2a35ee0/d; +L_0x2c5f7f0/d .functor AND 1, L_0x2c5fc50, L_0x2a35ee0, C4<1>, C4<1>; +L_0x2c5f7f0 .delay (20000,20000,20000) L_0x2c5f7f0/d; +L_0x2c5f8e0/d .functor AND 1, L_0x2c5fd40, L_0x2c5fbb0, C4<1>, C4<1>; +L_0x2c5f8e0 .delay (20000,20000,20000) L_0x2c5f8e0/d; +L_0x2c5f9d0/d .functor OR 1, L_0x2c5f7f0, L_0x2c5f8e0, C4<0>, C4<0>; +L_0x2c5f9d0 .delay (20000,20000,20000) L_0x2c5f9d0/d; +v0x2a2b770_0 .net "S", 0 0, L_0x2c5fbb0; 1 drivers +v0x2a2b810_0 .net "in0", 0 0, L_0x2c5fc50; 1 drivers +v0x2a306c0_0 .net "in1", 0 0, L_0x2c5fd40; 1 drivers +v0x2a30760_0 .net "nS", 0 0, L_0x2a35ee0; 1 drivers +v0x2a30480_0 .net "out0", 0 0, L_0x2c5f7f0; 1 drivers +v0x2a301b0_0 .net "out1", 0 0, L_0x2c5f8e0; 1 drivers +v0x2a2e570_0 .net "outfinal", 0 0, L_0x2c5f9d0; 1 drivers +S_0x2a40cb0 .scope generate, "muxbits[20]" "muxbits[20]" 3 290, 3 290, S_0x29738d0; + .timescale -9 -12; +P_0x2a63688 .param/l "i" 3 290, +C4<010100>; +L_0x2c62600/d .functor OR 1, L_0x2c62740, L_0x2c627e0, C4<0>, C4<0>; +L_0x2c62600 .delay (20000,20000,20000) L_0x2c62600/d; +v0x2a28a10_0 .net *"_s15", 0 0, L_0x2c62740; 1 drivers +v0x2a2d8c0_0 .net *"_s16", 0 0, L_0x2c627e0; 1 drivers +S_0x2a22d70 .scope module, "ZeroMux" "FourInMux" 3 292, 3 24, S_0x2a40cb0; + .timescale -9 -12; +L_0x2c60010/d .functor NOT 1, L_0x2c608b0, C4<0>, C4<0>, C4<0>; +L_0x2c60010 .delay (10000,10000,10000) L_0x2c60010/d; +L_0x2c60100/d .functor NOT 1, L_0x2c609e0, C4<0>, C4<0>, C4<0>; +L_0x2c60100 .delay (10000,10000,10000) L_0x2c60100/d; +L_0x2c601a0/d .functor NAND 1, L_0x2c60010, L_0x2c60100, L_0x2c61ab0, C4<1>; +L_0x2c601a0 .delay (10000,10000,10000) L_0x2c601a0/d; +L_0x2c602e0/d .functor NAND 1, L_0x2c608b0, L_0x2c60100, L_0x2c61b50, C4<1>; +L_0x2c602e0 .delay (10000,10000,10000) L_0x2c602e0/d; +L_0x2c603d0/d .functor NAND 1, L_0x2c60010, L_0x2c609e0, L_0x2c60e10, C4<1>; +L_0x2c603d0 .delay (10000,10000,10000) L_0x2c603d0/d; +L_0x2c604c0/d .functor NAND 1, L_0x2c608b0, L_0x2c609e0, L_0x2c60f00, C4<1>; +L_0x2c604c0 .delay (10000,10000,10000) L_0x2c604c0/d; +L_0x2c60600/d .functor NAND 1, L_0x2c601a0, L_0x2c602e0, L_0x2c603d0, L_0x2c604c0; +L_0x2c60600 .delay (10000,10000,10000) L_0x2c60600/d; +v0x2a27cc0_0 .net "S0", 0 0, L_0x2c608b0; 1 drivers +v0x2a27a60_0 .net "S1", 0 0, L_0x2c609e0; 1 drivers +v0x2a27b00_0 .net "in0", 0 0, L_0x2c61ab0; 1 drivers +v0x2a277b0_0 .net "in1", 0 0, L_0x2c61b50; 1 drivers +v0x2a27830_0 .net "in2", 0 0, L_0x2c60e10; 1 drivers +v0x2a25b70_0 .net "in3", 0 0, L_0x2c60f00; 1 drivers +v0x2a25c10_0 .net "nS0", 0 0, L_0x2c60010; 1 drivers +v0x2a2aac0_0 .net "nS1", 0 0, L_0x2c60100; 1 drivers +v0x2a2ab60_0 .net "out", 0 0, L_0x2c60600; 1 drivers +v0x2a2a860_0 .net "out0", 0 0, L_0x2c601a0; 1 drivers +v0x2a2a8e0_0 .net "out1", 0 0, L_0x2c602e0; 1 drivers +v0x2a2a5b0_0 .net "out2", 0 0, L_0x2c603d0; 1 drivers +v0x2a28970_0 .net "out3", 0 0, L_0x2c604c0; 1 drivers +S_0x2a1f100 .scope module, "OneMux" "FourInMux" 3 293, 3 24, S_0x2a40cb0; + .timescale -9 -12; +L_0x2c60ff0/d .functor NOT 1, L_0x2c618c0, C4<0>, C4<0>, C4<0>; +L_0x2c60ff0 .delay (10000,10000,10000) L_0x2c60ff0/d; +L_0x2c610e0/d .functor NOT 1, L_0x2c619f0, C4<0>, C4<0>, C4<0>; +L_0x2c610e0 .delay (10000,10000,10000) L_0x2c610e0/d; +L_0x2c61180/d .functor NAND 1, L_0x2c60ff0, L_0x2c610e0, L_0x2c62950, C4<1>; +L_0x2c61180 .delay (10000,10000,10000) L_0x2c61180/d; +L_0x2c612c0/d .functor NAND 1, L_0x2c618c0, L_0x2c610e0, L_0x2c61bf0, C4<1>; +L_0x2c612c0 .delay (10000,10000,10000) L_0x2c612c0/d; +L_0x2c613b0/d .functor NAND 1, L_0x2c60ff0, L_0x2c619f0, L_0x2c61c90, C4<1>; +L_0x2c613b0 .delay (10000,10000,10000) L_0x2c613b0/d; +L_0x2c614a0/d .functor NAND 1, L_0x2c618c0, L_0x2c619f0, L_0x2c61d80, C4<1>; +L_0x2c614a0 .delay (10000,10000,10000) L_0x2c614a0/d; +L_0x2c61610/d .functor NAND 1, L_0x2c61180, L_0x2c612c0, L_0x2c613b0, L_0x2c614a0; +L_0x2c61610 .delay (10000,10000,10000) L_0x2c61610/d; +v0x2a1ee50_0 .net "S0", 0 0, L_0x2c618c0; 1 drivers +v0x2a1eef0_0 .net "S1", 0 0, L_0x2c619f0; 1 drivers +v0x2a1d1c0_0 .net "in0", 0 0, L_0x2c62950; 1 drivers +v0x2a1d260_0 .net "in1", 0 0, L_0x2c61bf0; 1 drivers +v0x2a220c0_0 .net "in2", 0 0, L_0x2c61c90; 1 drivers +v0x2a22160_0 .net "in3", 0 0, L_0x2c61d80; 1 drivers +v0x2a21ec0_0 .net "nS0", 0 0, L_0x2c60ff0; 1 drivers +v0x2a20000_0 .net "nS1", 0 0, L_0x2c610e0; 1 drivers +v0x2a20080_0 .net "out", 0 0, L_0x2c61610; 1 drivers +v0x2a24ec0_0 .net "out0", 0 0, L_0x2c61180; 1 drivers +v0x2a24f60_0 .net "out1", 0 0, L_0x2c612c0; 1 drivers +v0x2a24c80_0 .net "out2", 0 0, L_0x2c613b0; 1 drivers +v0x2a249d0_0 .net "out3", 0 0, L_0x2c614a0; 1 drivers +S_0x2a3e430 .scope module, "TwoMux" "TwoInMux" 3 294, 3 8, S_0x2a40cb0; + .timescale -9 -12; +L_0x2c61e70/d .functor NOT 1, L_0x2c622e0, C4<0>, C4<0>, C4<0>; +L_0x2c61e70 .delay (10000,10000,10000) L_0x2c61e70/d; +L_0x2c61f20/d .functor AND 1, L_0x2c62380, L_0x2c61e70, C4<1>, C4<1>; +L_0x2c61f20 .delay (20000,20000,20000) L_0x2c61f20/d; +L_0x2c62010/d .functor AND 1, L_0x2c62470, L_0x2c622e0, C4<1>, C4<1>; +L_0x2c62010 .delay (20000,20000,20000) L_0x2c62010/d; +L_0x2c62100/d .functor OR 1, L_0x2c61f20, L_0x2c62010, C4<0>, C4<0>; +L_0x2c62100 .delay (20000,20000,20000) L_0x2c62100/d; +v0x2a3b5f0_0 .net "S", 0 0, L_0x2c622e0; 1 drivers +v0x2a3b690_0 .net "in0", 0 0, L_0x2c62380; 1 drivers +v0x2a73460_0 .net "in1", 0 0, L_0x2c62470; 1 drivers +v0x2a73500_0 .net "nS", 0 0, L_0x2c61e70; 1 drivers +v0x2a1bf80_0 .net "out0", 0 0, L_0x2c61f20; 1 drivers +v0x2a1c020_0 .net "out1", 0 0, L_0x2c62010; 1 drivers +v0x2a1a2c0_0 .net "outfinal", 0 0, L_0x2c62100; 1 drivers +S_0x2a69410 .scope generate, "muxbits[21]" "muxbits[21]" 3 290, 3 290, S_0x29738d0; + .timescale -9 -12; +P_0x2a27318 .param/l "i" 3 290, +C4<010101>; +L_0x2c64b40/d .functor OR 1, L_0x2c64c80, L_0x2c64d20, C4<0>, C4<0>; +L_0x2c64b40 .delay (20000,20000,20000) L_0x2c64b40/d; +v0x2a1ea20_0 .net *"_s15", 0 0, L_0x2c64c80; 1 drivers +v0x2a43920_0 .net *"_s16", 0 0, L_0x2c64d20; 1 drivers +S_0x2a4f100 .scope module, "ZeroMux" "FourInMux" 3 292, 3 24, S_0x2a69410; + .timescale -9 -12; +L_0x2c63720/d .functor NOT 1, L_0x2c63f80, C4<0>, C4<0>, C4<0>; +L_0x2c63720 .delay (10000,10000,10000) L_0x2c63720/d; +L_0x2c637d0/d .functor NOT 1, L_0x2c629f0, C4<0>, C4<0>, C4<0>; +L_0x2c637d0 .delay (10000,10000,10000) L_0x2c637d0/d; +L_0x2c63870/d .functor NAND 1, L_0x2c63720, L_0x2c637d0, L_0x2c62b20, C4<1>; +L_0x2c63870 .delay (10000,10000,10000) L_0x2c63870/d; +L_0x2c639b0/d .functor NAND 1, L_0x2c63f80, L_0x2c637d0, L_0x2c62bc0, C4<1>; +L_0x2c639b0 .delay (10000,10000,10000) L_0x2c639b0/d; +L_0x2c63aa0/d .functor NAND 1, L_0x2c63720, L_0x2c629f0, L_0x2c62c60, C4<1>; +L_0x2c63aa0 .delay (10000,10000,10000) L_0x2c63aa0/d; +L_0x2c63b90/d .functor NAND 1, L_0x2c63f80, L_0x2c629f0, L_0x2c62d50, C4<1>; +L_0x2c63b90 .delay (10000,10000,10000) L_0x2c63b90/d; +L_0x2c63cd0/d .functor NAND 1, L_0x2c63870, L_0x2c639b0, L_0x2c63aa0, L_0x2c63b90; +L_0x2c63cd0 .delay (10000,10000,10000) L_0x2c63cd0/d; +v0x2a4c880_0 .net "S0", 0 0, L_0x2c63f80; 1 drivers +v0x2a4c920_0 .net "S1", 0 0, L_0x2c629f0; 1 drivers +v0x2a4c300_0 .net "in0", 0 0, L_0x2c62b20; 1 drivers +v0x2a4c3a0_0 .net "in1", 0 0, L_0x2c62bc0; 1 drivers +v0x2a49a80_0 .net "in2", 0 0, L_0x2c62c60; 1 drivers +v0x2a49b20_0 .net "in3", 0 0, L_0x2c62d50; 1 drivers +v0x2a49520_0 .net "nS0", 0 0, L_0x2c63720; 1 drivers +v0x2a46c80_0 .net "nS1", 0 0, L_0x2c637d0; 1 drivers +v0x2a46d20_0 .net "out", 0 0, L_0x2c63cd0; 1 drivers +v0x2a46700_0 .net "out0", 0 0, L_0x2c63870; 1 drivers +v0x2a467a0_0 .net "out1", 0 0, L_0x2c639b0; 1 drivers +v0x2a43e80_0 .net "out2", 0 0, L_0x2c63aa0; 1 drivers +v0x2a1e980_0 .net "out3", 0 0, L_0x2c63b90; 1 drivers +S_0x2a5dd50 .scope module, "OneMux" "FourInMux" 3 293, 3 24, S_0x2a69410; + .timescale -9 -12; +L_0x2c62e40/d .functor NOT 1, L_0x2c64e20, C4<0>, C4<0>, C4<0>; +L_0x2c62e40 .delay (10000,10000,10000) L_0x2c62e40/d; +L_0x2c62ef0/d .functor NOT 1, L_0x2c64f50, C4<0>, C4<0>, C4<0>; +L_0x2c62ef0 .delay (10000,10000,10000) L_0x2c62ef0/d; +L_0x2c62f90/d .functor NAND 1, L_0x2c62e40, L_0x2c62ef0, L_0x2c640b0, C4<1>; +L_0x2c62f90 .delay (10000,10000,10000) L_0x2c62f90/d; +L_0x2c630d0/d .functor NAND 1, L_0x2c64e20, L_0x2c62ef0, L_0x2c64150, C4<1>; +L_0x2c630d0 .delay (10000,10000,10000) L_0x2c630d0/d; +L_0x2c631c0/d .functor NAND 1, L_0x2c62e40, L_0x2c64f50, L_0x2c641f0, C4<1>; +L_0x2c631c0 .delay (10000,10000,10000) L_0x2c631c0/d; +L_0x2c632e0/d .functor NAND 1, L_0x2c64e20, L_0x2c64f50, L_0x2c642e0, C4<1>; +L_0x2c632e0 .delay (10000,10000,10000) L_0x2c632e0/d; +L_0x2c63450/d .functor NAND 1, L_0x2c62f90, L_0x2c630d0, L_0x2c631c0, L_0x2c632e0; +L_0x2c63450 .delay (10000,10000,10000) L_0x2c63450/d; +v0x2a21780_0 .net "S0", 0 0, L_0x2c64e20; 1 drivers +v0x2a5af10_0 .net "S1", 0 0, L_0x2c64f50; 1 drivers +v0x2a5af90_0 .net "in0", 0 0, L_0x2c640b0; 1 drivers +v0x2a21480_0 .net "in1", 0 0, L_0x2c64150; 1 drivers +v0x2a21520_0 .net "in2", 0 0, L_0x2c641f0; 1 drivers +v0x2a580d0_0 .net "in3", 0 0, L_0x2c642e0; 1 drivers +v0x2a58170_0 .net "nS0", 0 0, L_0x2c62e40; 1 drivers +v0x2a552b0_0 .net "nS1", 0 0, L_0x2c62ef0; 1 drivers +v0x2a52480_0 .net "out", 0 0, L_0x2c63450; 1 drivers +v0x2a52520_0 .net "out0", 0 0, L_0x2c62f90; 1 drivers +v0x2a51f00_0 .net "out1", 0 0, L_0x2c630d0; 1 drivers +v0x2a51fa0_0 .net "out2", 0 0, L_0x2c631c0; 1 drivers +v0x2a4f710_0 .net "out3", 0 0, L_0x2c632e0; 1 drivers +S_0x2a68e90 .scope module, "TwoMux" "TwoInMux" 3 294, 3 8, S_0x2a69410; + .timescale -9 -12; +L_0x2a55330/d .functor NOT 1, L_0x2c64820, C4<0>, C4<0>, C4<0>; +L_0x2a55330 .delay (10000,10000,10000) L_0x2a55330/d; +L_0x2c64460/d .functor AND 1, L_0x2c648c0, L_0x2a55330, C4<1>, C4<1>; +L_0x2c64460 .delay (20000,20000,20000) L_0x2c64460/d; +L_0x2c64550/d .functor AND 1, L_0x2c649b0, L_0x2c64820, C4<1>, C4<1>; +L_0x2c64550 .delay (20000,20000,20000) L_0x2c64550/d; +L_0x2c64640/d .functor OR 1, L_0x2c64460, L_0x2c64550, C4<0>, C4<0>; +L_0x2c64640 .delay (20000,20000,20000) L_0x2c64640/d; +v0x2a66610_0 .net "S", 0 0, L_0x2c64820; 1 drivers +v0x2a666b0_0 .net "in0", 0 0, L_0x2c648c0; 1 drivers +v0x2a66090_0 .net "in1", 0 0, L_0x2c649b0; 1 drivers +v0x2a66130_0 .net "nS", 0 0, L_0x2a55330; 1 drivers +v0x2a635c0_0 .net "out0", 0 0, L_0x2c64460; 1 drivers +v0x2a60b90_0 .net "out1", 0 0, L_0x2c64550; 1 drivers +v0x2a216e0_0 .net "outfinal", 0 0, L_0x2c64640; 1 drivers +S_0x2aef3d0 .scope generate, "muxbits[22]" "muxbits[22]" 3 290, 3 290, S_0x29738d0; + .timescale -9 -12; +P_0x2952758 .param/l "i" 3 290, +C4<010110>; +L_0x2c672d0/d .functor OR 1, L_0x2c67410, L_0x2c68540, C4<0>, C4<0>; +L_0x2c672d0 .delay (20000,20000,20000) L_0x2c672d0/d; +v0x2a6c2b0_0 .net *"_s15", 0 0, L_0x2c67410; 1 drivers +v0x2a6bc90_0 .net *"_s16", 0 0, L_0x2c68540; 1 drivers +S_0x2a75380 .scope module, "ZeroMux" "FourInMux" 3 292, 3 24, S_0x2aef3d0; + .timescale -9 -12; +L_0x2c65e50/d .functor NOT 1, L_0x2c65080, C4<0>, C4<0>, C4<0>; +L_0x2c65e50 .delay (10000,10000,10000) L_0x2c65e50/d; +L_0x2c65f40/d .functor NOT 1, L_0x2c651b0, C4<0>, C4<0>, C4<0>; +L_0x2c65f40 .delay (10000,10000,10000) L_0x2c65f40/d; +L_0x2c65fe0/d .functor NAND 1, L_0x2c65e50, L_0x2c65f40, L_0x2c652e0, C4<1>; +L_0x2c65fe0 .delay (10000,10000,10000) L_0x2c65fe0/d; +L_0x2c66120/d .functor NAND 1, L_0x2c65080, L_0x2c65f40, L_0x2c65380, C4<1>; +L_0x2c66120 .delay (10000,10000,10000) L_0x2c66120/d; +L_0x2c66210/d .functor NAND 1, L_0x2c65e50, L_0x2c651b0, L_0x2c65420, C4<1>; +L_0x2c66210 .delay (10000,10000,10000) L_0x2c66210/d; +L_0x2c66300/d .functor NAND 1, L_0x2c65080, L_0x2c651b0, L_0x2c65510, C4<1>; +L_0x2c66300 .delay (10000,10000,10000) L_0x2c66300/d; +L_0x2c66440/d .functor NAND 1, L_0x2c65fe0, L_0x2c66120, L_0x2c66210, L_0x2c66300; +L_0x2c66440 .delay (10000,10000,10000) L_0x2c66440/d; +v0x2a750e0_0 .net "S0", 0 0, L_0x2c65080; 1 drivers +v0x2a74c20_0 .net "S1", 0 0, L_0x2c651b0; 1 drivers +v0x2a74cc0_0 .net "in0", 0 0, L_0x2c652e0; 1 drivers +v0x2a71e10_0 .net "in1", 0 0, L_0x2c65380; 1 drivers +v0x2a71e90_0 .net "in2", 0 0, L_0x2c65420; 1 drivers +v0x2a71890_0 .net "in3", 0 0, L_0x2c65510; 1 drivers +v0x2a71930_0 .net "nS0", 0 0, L_0x2c65e50; 1 drivers +v0x2a23f90_0 .net "nS1", 0 0, L_0x2c65f40; 1 drivers +v0x2a24030_0 .net "out", 0 0, L_0x2c66440; 1 drivers +v0x2a6f010_0 .net "out0", 0 0, L_0x2c65fe0; 1 drivers +v0x2a6f090_0 .net "out1", 0 0, L_0x2c66120; 1 drivers +v0x2a6ea90_0 .net "out2", 0 0, L_0x2c66210; 1 drivers +v0x2a6c210_0 .net "out3", 0 0, L_0x2c66300; 1 drivers +S_0x2a2cf10 .scope module, "OneMux" "FourInMux" 3 293, 3 24, S_0x2aef3d0; + .timescale -9 -12; +L_0x2c65600/d .functor NOT 1, L_0x2c675a0, C4<0>, C4<0>, C4<0>; +L_0x2c65600 .delay (10000,10000,10000) L_0x2c65600/d; +L_0x2c656f0/d .functor NOT 1, L_0x2c666f0, C4<0>, C4<0>, C4<0>; +L_0x2c656f0 .delay (10000,10000,10000) L_0x2c656f0/d; +L_0x2c65790/d .functor NAND 1, L_0x2c65600, L_0x2c656f0, L_0x2c66820, C4<1>; +L_0x2c65790 .delay (10000,10000,10000) L_0x2c65790/d; +L_0x2c658d0/d .functor NAND 1, L_0x2c675a0, L_0x2c656f0, L_0x2c668c0, C4<1>; +L_0x2c658d0 .delay (10000,10000,10000) L_0x2c658d0/d; +L_0x2c659c0/d .functor NAND 1, L_0x2c65600, L_0x2c666f0, L_0x2c66960, C4<1>; +L_0x2c659c0 .delay (10000,10000,10000) L_0x2c659c0/d; +L_0x2c65ab0/d .functor NAND 1, L_0x2c675a0, L_0x2c666f0, L_0x2c66a50, C4<1>; +L_0x2c65ab0 .delay (10000,10000,10000) L_0x2c65ab0/d; +L_0x2c65c20/d .functor NAND 1, L_0x2c65790, L_0x2c658d0, L_0x2c659c0, L_0x2c65ab0; +L_0x2c65c20 .delay (10000,10000,10000) L_0x2c65c20/d; +v0x2a2c990_0 .net "S0", 0 0, L_0x2c675a0; 1 drivers +v0x2a2ca30_0 .net "S1", 0 0, L_0x2c666f0; 1 drivers +v0x2a2a110_0 .net "in0", 0 0, L_0x2c66820; 1 drivers +v0x2a2a1b0_0 .net "in1", 0 0, L_0x2c668c0; 1 drivers +v0x2a29b90_0 .net "in2", 0 0, L_0x2c66960; 1 drivers +v0x2a29c30_0 .net "in3", 0 0, L_0x2c66a50; 1 drivers +v0x2a27370_0 .net "nS0", 0 0, L_0x2c65600; 1 drivers +v0x2a1bab0_0 .net "nS1", 0 0, L_0x2c656f0; 1 drivers +v0x2a1bb30_0 .net "out", 0 0, L_0x2c65c20; 1 drivers +v0x2a26d90_0 .net "out0", 0 0, L_0x2c65790; 1 drivers +v0x2a26e30_0 .net "out1", 0 0, L_0x2c658d0; 1 drivers +v0x2a24530_0 .net "out2", 0 0, L_0x2c659c0; 1 drivers +v0x2a75610_0 .net "out3", 0 0, L_0x2c65ab0; 1 drivers +S_0x2a387b0 .scope module, "TwoMux" "TwoInMux" 3 294, 3 8, S_0x2aef3d0; + .timescale -9 -12; +L_0x2c66b40/d .functor NOT 1, L_0x2c66fb0, C4<0>, C4<0>, C4<0>; +L_0x2c66b40 .delay (10000,10000,10000) L_0x2c66b40/d; +L_0x2c66bf0/d .functor AND 1, L_0x2c67050, L_0x2c66b40, C4<1>, C4<1>; +L_0x2c66bf0 .delay (20000,20000,20000) L_0x2c66bf0/d; +L_0x2c66ce0/d .functor AND 1, L_0x2c67140, L_0x2c66fb0, C4<1>, C4<1>; +L_0x2c66ce0 .delay (20000,20000,20000) L_0x2c66ce0/d; +L_0x2c66dd0/d .functor OR 1, L_0x2c66bf0, L_0x2c66ce0, C4<0>, C4<0>; +L_0x2c66dd0 .delay (20000,20000,20000) L_0x2c66dd0/d; +v0x2a35970_0 .net "S", 0 0, L_0x2c66fb0; 1 drivers +v0x2a35a10_0 .net "in0", 0 0, L_0x2c67050; 1 drivers +v0x2a32b30_0 .net "in1", 0 0, L_0x2c67140; 1 drivers +v0x2a32bd0_0 .net "nS", 0 0, L_0x2c66b40; 1 drivers +v0x2a2fd10_0 .net "out0", 0 0, L_0x2c66bf0; 1 drivers +v0x2a2fdb0_0 .net "out1", 0 0, L_0x2c66ce0; 1 drivers +v0x2a2f7f0_0 .net "outfinal", 0 0, L_0x2c66dd0; 1 drivers +S_0x2951070 .scope generate, "muxbits[23]" "muxbits[23]" 3 290, 3 290, S_0x29738d0; + .timescale -9 -12; +P_0x2945988 .param/l "i" 3 290, +C4<010111>; +L_0x2c692d0/d .functor OR 1, L_0x2c6aca0, L_0x2c69d90, C4<0>, C4<0>; +L_0x2c692d0 .delay (20000,20000,20000) L_0x2c692d0/d; +v0x2af2740_0 .net *"_s15", 0 0, L_0x2c6aca0; 1 drivers +v0x2af14b0_0 .net *"_s16", 0 0, L_0x2c69d90; 1 drivers +S_0x295c650 .scope module, "ZeroMux" "FourInMux" 3 292, 3 24, S_0x2951070; + .timescale -9 -12; +L_0x2c676d0/d .functor NOT 1, L_0x2c67fa0, C4<0>, C4<0>, C4<0>; +L_0x2c676d0 .delay (10000,10000,10000) L_0x2c676d0/d; +L_0x2c677c0/d .functor NOT 1, L_0x2c680d0, C4<0>, C4<0>, C4<0>; +L_0x2c677c0 .delay (10000,10000,10000) L_0x2c677c0/d; +L_0x2c67860/d .functor NAND 1, L_0x2c676d0, L_0x2c677c0, L_0x2c68200, C4<1>; +L_0x2c67860 .delay (10000,10000,10000) L_0x2c67860/d; +L_0x2c679a0/d .functor NAND 1, L_0x2c67fa0, L_0x2c677c0, L_0x2c682a0, C4<1>; +L_0x2c679a0 .delay (10000,10000,10000) L_0x2c679a0/d; +L_0x2c67a90/d .functor NAND 1, L_0x2c676d0, L_0x2c680d0, L_0x2c68340, C4<1>; +L_0x2c67a90 .delay (10000,10000,10000) L_0x2c67a90/d; +L_0x2c67b80/d .functor NAND 1, L_0x2c67fa0, L_0x2c680d0, L_0x2c68430, C4<1>; +L_0x2c67b80 .delay (10000,10000,10000) L_0x2c67b80/d; +L_0x2c67cf0/d .functor NAND 1, L_0x2c67860, L_0x2c679a0, L_0x2c67a90, L_0x2c67b80; +L_0x2c67cf0 .delay (10000,10000,10000) L_0x2c67cf0/d; +v0x295b7f0_0 .net "S0", 0 0, L_0x2c67fa0; 1 drivers +v0x295b890_0 .net "S1", 0 0, L_0x2c680d0; 1 drivers +v0x295ed40_0 .net "in0", 0 0, L_0x2c68200; 1 drivers +v0x295ede0_0 .net "in1", 0 0, L_0x2c682a0; 1 drivers +v0x295eae0_0 .net "in2", 0 0, L_0x2c68340; 1 drivers +v0x295eb80_0 .net "in3", 0 0, L_0x2c68430; 1 drivers +v0x295dc70_0 .net "nS0", 0 0, L_0x2c676d0; 1 drivers +v0x29611f0_0 .net "nS1", 0 0, L_0x2c677c0; 1 drivers +v0x2961290_0 .net "out", 0 0, L_0x2c67cf0; 1 drivers +v0x2960f90_0 .net "out0", 0 0, L_0x2c67860; 1 drivers +v0x2961030_0 .net "out1", 0 0, L_0x2c679a0; 1 drivers +v0x2960100_0 .net "out2", 0 0, L_0x2c67a90; 1 drivers +v0x2af26a0_0 .net "out3", 0 0, L_0x2c67b80; 1 drivers +S_0x2954ad0 .scope module, "OneMux" "FourInMux" 3 293, 3 24, S_0x2951070; + .timescale -9 -12; +L_0x2c69490/d .functor NOT 1, L_0x2c685e0, C4<0>, C4<0>, C4<0>; +L_0x2c69490 .delay (10000,10000,10000) L_0x2c69490/d; +L_0x2c69580/d .functor NOT 1, L_0x2c68710, C4<0>, C4<0>, C4<0>; +L_0x2c69580 .delay (10000,10000,10000) L_0x2c69580/d; +L_0x2c69620/d .functor NAND 1, L_0x2c69490, L_0x2c69580, L_0x2c68840, C4<1>; +L_0x2c69620 .delay (10000,10000,10000) L_0x2c69620/d; +L_0x2c69760/d .functor NAND 1, L_0x2c685e0, L_0x2c69580, L_0x2c688e0, C4<1>; +L_0x2c69760 .delay (10000,10000,10000) L_0x2c69760/d; +L_0x2c69850/d .functor NAND 1, L_0x2c69490, L_0x2c68710, L_0x2c68980, C4<1>; +L_0x2c69850 .delay (10000,10000,10000) L_0x2c69850/d; +L_0x2c69970/d .functor NAND 1, L_0x2c685e0, L_0x2c68710, L_0x2c68a70, C4<1>; +L_0x2c69970 .delay (10000,10000,10000) L_0x2c69970/d; +L_0x2c69ae0/d .functor NAND 1, L_0x2c69620, L_0x2c69760, L_0x2c69850, L_0x2c69970; +L_0x2c69ae0 .delay (10000,10000,10000) L_0x2c69ae0/d; +v0x29559d0_0 .net "S0", 0 0, L_0x2c685e0; 1 drivers +v0x2957ff0_0 .net "S1", 0 0, L_0x2c68710; 1 drivers +v0x2958070_0 .net "in0", 0 0, L_0x2c68840; 1 drivers +v0x2957d90_0 .net "in1", 0 0, L_0x2c688e0; 1 drivers +v0x2957e30_0 .net "in2", 0 0, L_0x2c68980; 1 drivers +v0x2956f30_0 .net "in3", 0 0, L_0x2c68a70; 1 drivers +v0x2956fd0_0 .net "nS0", 0 0, L_0x2c69490; 1 drivers +v0x295a470_0 .net "nS1", 0 0, L_0x2c69580; 1 drivers +v0x295a1f0_0 .net "out", 0 0, L_0x2c69ae0; 1 drivers +v0x295a290_0 .net "out0", 0 0, L_0x2c69620; 1 drivers +v0x2959390_0 .net "out1", 0 0, L_0x2c69760; 1 drivers +v0x2959430_0 .net "out2", 0 0, L_0x2c69850; 1 drivers +v0x295c940_0 .net "out3", 0 0, L_0x2c69970; 1 drivers +S_0x2950210 .scope module, "TwoMux" "TwoInMux" 3 294, 3 8, S_0x2951070; + .timescale -9 -12; +L_0x295a4f0/d .functor NOT 1, L_0x2c68fb0, C4<0>, C4<0>, C4<0>; +L_0x295a4f0 .delay (10000,10000,10000) L_0x295a4f0/d; +L_0x2c68bf0/d .functor AND 1, L_0x2c69050, L_0x295a4f0, C4<1>, C4<1>; +L_0x2c68bf0 .delay (20000,20000,20000) L_0x2c68bf0/d; +L_0x2c68ce0/d .functor AND 1, L_0x2c69140, L_0x2c68fb0, C4<1>, C4<1>; +L_0x2c68ce0 .delay (20000,20000,20000) L_0x2c68ce0/d; +L_0x2c68dd0/d .functor OR 1, L_0x2c68bf0, L_0x2c68ce0, C4<0>, C4<0>; +L_0x2c68dd0 .delay (20000,20000,20000) L_0x2c68dd0/d; +v0x2953730_0 .net "S", 0 0, L_0x2c68fb0; 1 drivers +v0x29537d0_0 .net "in0", 0 0, L_0x2c69050; 1 drivers +v0x29534d0_0 .net "in1", 0 0, L_0x2c69140; 1 drivers +v0x2953570_0 .net "nS", 0 0, L_0x295a4f0; 1 drivers +v0x2952690_0 .net "out0", 0 0, L_0x2c68bf0; 1 drivers +v0x2955b90_0 .net "out1", 0 0, L_0x2c68ce0; 1 drivers +v0x2955930_0 .net "outfinal", 0 0, L_0x2c68dd0; 1 drivers +S_0x293b7d0 .scope generate, "muxbits[24]" "muxbits[24]" 3 290, 3 290, S_0x29738d0; + .timescale -9 -12; +P_0x292ba28 .param/l "i" 3 290, +C4<011000>; +L_0x2c6b960/d .functor OR 1, L_0x2c6baa0, L_0x2c6bb40, C4<0>, C4<0>; +L_0x2c6b960 .delay (20000,20000,20000) L_0x2c6b960/d; +v0x294de50_0 .net *"_s15", 0 0, L_0x2c6baa0; 1 drivers +v0x29512d0_0 .net *"_s16", 0 0, L_0x2c6bb40; 1 drivers +S_0x294a540 .scope module, "ZeroMux" "FourInMux" 3 292, 3 24, S_0x293b7d0; + .timescale -9 -12; +L_0x2c69e80/d .functor NOT 1, L_0x2c6a720, C4<0>, C4<0>, C4<0>; +L_0x2c69e80 .delay (10000,10000,10000) L_0x2c69e80/d; +L_0x2c69f70/d .functor NOT 1, L_0x2c6a850, C4<0>, C4<0>, C4<0>; +L_0x2c69f70 .delay (10000,10000,10000) L_0x2c69f70/d; +L_0x2c6a010/d .functor NAND 1, L_0x2c69e80, L_0x2c69f70, L_0x2c6a980, C4<1>; +L_0x2c6a010 .delay (10000,10000,10000) L_0x2c6a010/d; +L_0x2c6a150/d .functor NAND 1, L_0x2c6a720, L_0x2c69f70, L_0x2c6aa20, C4<1>; +L_0x2c6a150 .delay (10000,10000,10000) L_0x2c6a150/d; +L_0x2c6a240/d .functor NAND 1, L_0x2c69e80, L_0x2c6a850, L_0x2c6aac0, C4<1>; +L_0x2c6a240 .delay (10000,10000,10000) L_0x2c6a240/d; +L_0x2c6a330/d .functor NAND 1, L_0x2c6a720, L_0x2c6a850, L_0x2c6abb0, C4<1>; +L_0x2c6a330 .delay (10000,10000,10000) L_0x2c6a330/d; +L_0x2c6a470/d .functor NAND 1, L_0x2c6a010, L_0x2c6a150, L_0x2c6a240, L_0x2c6a330; +L_0x2c6a470 .delay (10000,10000,10000) L_0x2c6a470/d; +v0x294a2e0_0 .net "S0", 0 0, L_0x2c6a720; 1 drivers +v0x2949450_0 .net "S1", 0 0, L_0x2c6a850; 1 drivers +v0x29494f0_0 .net "in0", 0 0, L_0x2c6a980; 1 drivers +v0x294c9f0_0 .net "in1", 0 0, L_0x2c6aa20; 1 drivers +v0x294ca70_0 .net "in2", 0 0, L_0x2c6aac0; 1 drivers +v0x294c790_0 .net "in3", 0 0, L_0x2c6abb0; 1 drivers +v0x294c830_0 .net "nS0", 0 0, L_0x2c69e80; 1 drivers +v0x294b900_0 .net "nS1", 0 0, L_0x2c69f70; 1 drivers +v0x294b9a0_0 .net "out", 0 0, L_0x2c6a470; 1 drivers +v0x294ee70_0 .net "out0", 0 0, L_0x2c6a010; 1 drivers +v0x294eef0_0 .net "out1", 0 0, L_0x2c6a150; 1 drivers +v0x294ec10_0 .net "out2", 0 0, L_0x2c6a240; 1 drivers +v0x294ddb0_0 .net "out3", 0 0, L_0x2c6a330; 1 drivers +S_0x2943730 .scope module, "OneMux" "FourInMux" 3 293, 3 24, S_0x293b7d0; + .timescale -9 -12; +L_0x2c69410/d .functor NOT 1, L_0x2c6c510, C4<0>, C4<0>, C4<0>; +L_0x2c69410 .delay (10000,10000,10000) L_0x2c69410/d; +L_0x2c6bd30/d .functor NOT 1, L_0x2c6ad40, C4<0>, C4<0>, C4<0>; +L_0x2c6bd30 .delay (10000,10000,10000) L_0x2c6bd30/d; +L_0x2c6bdd0/d .functor NAND 1, L_0x2c69410, L_0x2c6bd30, L_0x2c6ae70, C4<1>; +L_0x2c6bdd0 .delay (10000,10000,10000) L_0x2c6bdd0/d; +L_0x2c6bf10/d .functor NAND 1, L_0x2c6c510, L_0x2c6bd30, L_0x2c6af10, C4<1>; +L_0x2c6bf10 .delay (10000,10000,10000) L_0x2c6bf10/d; +L_0x2c6c000/d .functor NAND 1, L_0x2c69410, L_0x2c6ad40, L_0x2c6afb0, C4<1>; +L_0x2c6c000 .delay (10000,10000,10000) L_0x2c6c000/d; +L_0x2c6c0f0/d .functor NAND 1, L_0x2c6c510, L_0x2c6ad40, L_0x2c6b0a0, C4<1>; +L_0x2c6c0f0 .delay (10000,10000,10000) L_0x2c6c0f0/d; +L_0x2c6c260/d .functor NAND 1, L_0x2c6bdd0, L_0x2c6bf10, L_0x2c6c000, L_0x2c6c0f0; +L_0x2c6c260 .delay (10000,10000,10000) L_0x2c6c260/d; +v0x29434d0_0 .net "S0", 0 0, L_0x2c6c510; 1 drivers +v0x2943570_0 .net "S1", 0 0, L_0x2c6ad40; 1 drivers +v0x2942640_0 .net "in0", 0 0, L_0x2c6ae70; 1 drivers +v0x29426e0_0 .net "in1", 0 0, L_0x2c6af10; 1 drivers +v0x2945be0_0 .net "in2", 0 0, L_0x2c6afb0; 1 drivers +v0x2945c80_0 .net "in3", 0 0, L_0x2c6b0a0; 1 drivers +v0x29459e0_0 .net "nS0", 0 0, L_0x2c69410; 1 drivers +v0x2944af0_0 .net "nS1", 0 0, L_0x2c6bd30; 1 drivers +v0x2944b70_0 .net "out", 0 0, L_0x2c6c260; 1 drivers +v0x2948090_0 .net "out0", 0 0, L_0x2c6bdd0; 1 drivers +v0x2948130_0 .net "out1", 0 0, L_0x2c6bf10; 1 drivers +v0x2947e50_0 .net "out2", 0 0, L_0x2c6c000; 1 drivers +v0x2946fc0_0 .net "out3", 0 0, L_0x2c6c0f0; 1 drivers +S_0x293edd0 .scope module, "TwoMux" "TwoInMux" 3 294, 3 8, S_0x293b7d0; + .timescale -9 -12; +L_0x2c6b190/d .functor NOT 1, L_0x2c6b640, C4<0>, C4<0>, C4<0>; +L_0x2c6b190 .delay (10000,10000,10000) L_0x2c6b190/d; +L_0x2c6b280/d .functor AND 1, L_0x2c6b6e0, L_0x2c6b190, C4<1>, C4<1>; +L_0x2c6b280 .delay (20000,20000,20000) L_0x2c6b280/d; +L_0x2c6b370/d .functor AND 1, L_0x2c6b7d0, L_0x2c6b640, C4<1>, C4<1>; +L_0x2c6b370 .delay (20000,20000,20000) L_0x2c6b370/d; +L_0x2c6b460/d .functor OR 1, L_0x2c6b280, L_0x2c6b370, C4<0>, C4<0>; +L_0x2c6b460 .delay (20000,20000,20000) L_0x2c6b460/d; +v0x293eb70_0 .net "S", 0 0, L_0x2c6b640; 1 drivers +v0x293ec10_0 .net "in0", 0 0, L_0x2c6b6e0; 1 drivers +v0x2941280_0 .net "in1", 0 0, L_0x2c6b7d0; 1 drivers +v0x2941320_0 .net "nS", 0 0, L_0x2c6b190; 1 drivers +v0x2941020_0 .net "out0", 0 0, L_0x2c6b280; 1 drivers +v0x29410c0_0 .net "out1", 0 0, L_0x2c6b370; 1 drivers +v0x29401f0_0 .net "outfinal", 0 0, L_0x2c6b460; 1 drivers +S_0x292a320 .scope generate, "muxbits[25]" "muxbits[25]" 3 290, 3 290, S_0x29738d0; + .timescale -9 -12; +P_0x291ebb8 .param/l "i" 3 290, +C4<011001>; +L_0x2be0ef0/d .functor OR 1, L_0x2be1030, L_0x2be10d0, C4<0>, C4<0>; +L_0x2be0ef0 .delay (20000,20000,20000) L_0x2be0ef0/d; +v0x293c930_0 .net *"_s15", 0 0, L_0x2be1030; 1 drivers +v0x293c650_0 .net *"_s16", 0 0, L_0x2be10d0; 1 drivers +S_0x2935910 .scope module, "ZeroMux" "FourInMux" 3 292, 3 24, S_0x292a320; + .timescale -9 -12; +L_0x2c6bc30/d .functor NOT 1, L_0x2c6ce80, C4<0>, C4<0>, C4<0>; +L_0x2c6bc30 .delay (10000,10000,10000) L_0x2c6bc30/d; +L_0x2c6c6d0/d .functor NOT 1, L_0x2c6cfb0, C4<0>, C4<0>, C4<0>; +L_0x2c6c6d0 .delay (10000,10000,10000) L_0x2c6c6d0/d; +L_0x2c6c770/d .functor NAND 1, L_0x2c6bc30, L_0x2c6c6d0, L_0x2c6d0e0, C4<1>; +L_0x2c6c770 .delay (10000,10000,10000) L_0x2c6c770/d; +L_0x2c6c8b0/d .functor NAND 1, L_0x2c6ce80, L_0x2c6c6d0, L_0x2c6d180, C4<1>; +L_0x2c6c8b0 .delay (10000,10000,10000) L_0x2c6c8b0/d; +L_0x2c6c9a0/d .functor NAND 1, L_0x2c6bc30, L_0x2c6cfb0, L_0x2c6d220, C4<1>; +L_0x2c6c9a0 .delay (10000,10000,10000) L_0x2c6c9a0/d; +L_0x2c6ca90/d .functor NAND 1, L_0x2c6ce80, L_0x2c6cfb0, L_0x2c6d310, C4<1>; +L_0x2c6ca90 .delay (10000,10000,10000) L_0x2c6ca90/d; +L_0x2c6cbd0/d .functor NAND 1, L_0x2c6c770, L_0x2c6c8b0, L_0x2c6c9a0, L_0x2c6ca90; +L_0x2c6cbd0 .delay (10000,10000,10000) L_0x2c6cbd0/d; +v0x2934ab0_0 .net "S0", 0 0, L_0x2c6ce80; 1 drivers +v0x2934b50_0 .net "S1", 0 0, L_0x2c6cfb0; 1 drivers +v0x2937fd0_0 .net "in0", 0 0, L_0x2c6d0e0; 1 drivers +v0x2938070_0 .net "in1", 0 0, L_0x2c6d180; 1 drivers +v0x2937d70_0 .net "in2", 0 0, L_0x2c6d220; 1 drivers +v0x2937e10_0 .net "in3", 0 0, L_0x2c6d310; 1 drivers +v0x2936f30_0 .net "nS0", 0 0, L_0x2c6bc30; 1 drivers +v0x293a430_0 .net "nS1", 0 0, L_0x2c6c6d0; 1 drivers +v0x293a4d0_0 .net "out", 0 0, L_0x2c6cbd0; 1 drivers +v0x293a1d0_0 .net "out0", 0 0, L_0x2c6c770; 1 drivers +v0x293a270_0 .net "out1", 0 0, L_0x2c6c8b0; 1 drivers +v0x2939370_0 .net "out2", 0 0, L_0x2c6c9a0; 1 drivers +v0x293c890_0 .net "out3", 0 0, L_0x2c6ca90; 1 drivers +S_0x292dd90 .scope module, "OneMux" "FourInMux" 3 293, 3 24, S_0x292a320; + .timescale -9 -12; +L_0x2c6d400/d .functor NOT 1, L_0x2be2200, C4<0>, C4<0>, C4<0>; +L_0x2c6d400 .delay (10000,10000,10000) L_0x2c6d400/d; +L_0x2c6d4f0/d .functor NOT 1, L_0x2be2330, C4<0>, C4<0>, C4<0>; +L_0x2c6d4f0 .delay (10000,10000,10000) L_0x2c6d4f0/d; +L_0x2be1ae0/d .functor NAND 1, L_0x2c6d400, L_0x2c6d4f0, L_0x2be2460, C4<1>; +L_0x2be1ae0 .delay (10000,10000,10000) L_0x2be1ae0/d; +L_0x2be1bd0/d .functor NAND 1, L_0x2be2200, L_0x2c6d4f0, L_0x2be2500, C4<1>; +L_0x2be1bd0 .delay (10000,10000,10000) L_0x2be1bd0/d; +L_0x2be1cc0/d .functor NAND 1, L_0x2c6d400, L_0x2be2330, L_0x2be25a0, C4<1>; +L_0x2be1cc0 .delay (10000,10000,10000) L_0x2be1cc0/d; +L_0x2be1de0/d .functor NAND 1, L_0x2be2200, L_0x2be2330, L_0x2be2690, C4<1>; +L_0x2be1de0 .delay (10000,10000,10000) L_0x2be1de0/d; +L_0x2be1f50/d .functor NAND 1, L_0x2be1ae0, L_0x2be1bd0, L_0x2be1cc0, L_0x2be1de0; +L_0x2be1f50 .delay (10000,10000,10000) L_0x2be1f50/d; +v0x292ec90_0 .net "S0", 0 0, L_0x2be2200; 1 drivers +v0x29312b0_0 .net "S1", 0 0, L_0x2be2330; 1 drivers +v0x2931330_0 .net "in0", 0 0, L_0x2be2460; 1 drivers +v0x2931050_0 .net "in1", 0 0, L_0x2be2500; 1 drivers +v0x29310f0_0 .net "in2", 0 0, L_0x2be25a0; 1 drivers +v0x29301f0_0 .net "in3", 0 0, L_0x2be2690; 1 drivers +v0x2930290_0 .net "nS0", 0 0, L_0x2c6d400; 1 drivers +v0x2933730_0 .net "nS1", 0 0, L_0x2c6d4f0; 1 drivers +v0x29334b0_0 .net "out", 0 0, L_0x2be1f50; 1 drivers +v0x2933550_0 .net "out0", 0 0, L_0x2be1ae0; 1 drivers +v0x2932650_0 .net "out1", 0 0, L_0x2be1bd0; 1 drivers +v0x29326f0_0 .net "out2", 0 0, L_0x2be1cc0; 1 drivers +v0x2935c00_0 .net "out3", 0 0, L_0x2be1de0; 1 drivers +S_0x2929490 .scope module, "TwoMux" "TwoInMux" 3 294, 3 8, S_0x292a320; + .timescale -9 -12; +L_0x29337b0/d .functor NOT 1, L_0x2be0bd0, C4<0>, C4<0>, C4<0>; +L_0x29337b0 .delay (10000,10000,10000) L_0x29337b0/d; +L_0x2be2810/d .functor AND 1, L_0x2be0c70, L_0x29337b0, C4<1>, C4<1>; +L_0x2be2810 .delay (20000,20000,20000) L_0x2be2810/d; +L_0x2be2900/d .functor AND 1, L_0x2be0d60, L_0x2be0bd0, C4<1>, C4<1>; +L_0x2be2900 .delay (20000,20000,20000) L_0x2be2900/d; +L_0x2be29f0/d .functor OR 1, L_0x2be2810, L_0x2be2900, C4<0>, C4<0>; +L_0x2be29f0 .delay (20000,20000,20000) L_0x2be29f0/d; +v0x292ca30_0 .net "S", 0 0, L_0x2be0bd0; 1 drivers +v0x292cad0_0 .net "in0", 0 0, L_0x2be0c70; 1 drivers +v0x292c7d0_0 .net "in1", 0 0, L_0x2be0d60; 1 drivers +v0x292c870_0 .net "nS", 0 0, L_0x29337b0; 1 drivers +v0x292b960_0 .net "out0", 0 0, L_0x2be2810; 1 drivers +v0x292ee50_0 .net "out1", 0 0, L_0x2be2900; 1 drivers +v0x292ebf0_0 .net "outfinal", 0 0, L_0x2be29f0; 1 drivers +S_0x2918fd0 .scope generate, "muxbits[26]" "muxbits[26]" 3 290, 3 290, S_0x29738d0; + .timescale -9 -12; +P_0x290fcd8 .param/l "i" 3 290, +C4<011010>; +L_0x2c72bf0/d .functor OR 1, L_0x2c72d30, L_0x2c72dd0, C4<0>, C4<0>; +L_0x2c72bf0 .delay (20000,20000,20000) L_0x2c72bf0/d; +v0x2927080_0 .net *"_s15", 0 0, L_0x2c72d30; 1 drivers +v0x292a580_0 .net *"_s16", 0 0, L_0x2c72dd0; 1 drivers +S_0x2923770 .scope module, "ZeroMux" "FourInMux" 3 292, 3 24, S_0x2918fd0; + .timescale -9 -12; +L_0x2be11c0/d .functor NOT 1, L_0x2c72670, C4<0>, C4<0>, C4<0>; +L_0x2be11c0 .delay (10000,10000,10000) L_0x2be11c0/d; +L_0x2be12b0/d .functor NOT 1, L_0x2c727a0, C4<0>, C4<0>, C4<0>; +L_0x2be12b0 .delay (10000,10000,10000) L_0x2be12b0/d; +L_0x2be1350/d .functor NAND 1, L_0x2be11c0, L_0x2be12b0, L_0x2c715f0, C4<1>; +L_0x2be1350 .delay (10000,10000,10000) L_0x2be1350/d; +L_0x2be1490/d .functor NAND 1, L_0x2c72670, L_0x2be12b0, L_0x2c71690, C4<1>; +L_0x2be1490 .delay (10000,10000,10000) L_0x2be1490/d; +L_0x2be1580/d .functor NAND 1, L_0x2be11c0, L_0x2c727a0, L_0x2c71730, C4<1>; +L_0x2be1580 .delay (10000,10000,10000) L_0x2be1580/d; +L_0x2be1670/d .functor NAND 1, L_0x2c72670, L_0x2c727a0, L_0x2c71820, C4<1>; +L_0x2be1670 .delay (10000,10000,10000) L_0x2be1670/d; +L_0x2be17b0/d .functor NAND 1, L_0x2be1350, L_0x2be1490, L_0x2be1580, L_0x2be1670; +L_0x2be17b0 .delay (10000,10000,10000) L_0x2be17b0/d; +v0x2923510_0 .net "S0", 0 0, L_0x2c72670; 1 drivers +v0x2922680_0 .net "S1", 0 0, L_0x2c727a0; 1 drivers +v0x2922720_0 .net "in0", 0 0, L_0x2c715f0; 1 drivers +v0x2925c20_0 .net "in1", 0 0, L_0x2c71690; 1 drivers +v0x2925ca0_0 .net "in2", 0 0, L_0x2c71730; 1 drivers +v0x29259c0_0 .net "in3", 0 0, L_0x2c71820; 1 drivers +v0x2925a60_0 .net "nS0", 0 0, L_0x2be11c0; 1 drivers +v0x2924b30_0 .net "nS1", 0 0, L_0x2be12b0; 1 drivers +v0x2924bd0_0 .net "out", 0 0, L_0x2be17b0; 1 drivers +v0x29280d0_0 .net "out0", 0 0, L_0x2be1350; 1 drivers +v0x2928150_0 .net "out1", 0 0, L_0x2be1490; 1 drivers +v0x2927e70_0 .net "out2", 0 0, L_0x2be1580; 1 drivers +v0x2926fe0_0 .net "out3", 0 0, L_0x2be1670; 1 drivers +S_0x291c8f0 .scope module, "OneMux" "FourInMux" 3 293, 3 24, S_0x2918fd0; + .timescale -9 -12; +L_0x2c71910/d .functor NOT 1, L_0x2c721e0, C4<0>, C4<0>, C4<0>; +L_0x2c71910 .delay (10000,10000,10000) L_0x2c71910/d; +L_0x2c71a00/d .functor NOT 1, L_0x2c72310, C4<0>, C4<0>, C4<0>; +L_0x2c71a00 .delay (10000,10000,10000) L_0x2c71a00/d; +L_0x2c71aa0/d .functor NAND 1, L_0x2c71910, L_0x2c71a00, L_0x2c72440, C4<1>; +L_0x2c71aa0 .delay (10000,10000,10000) L_0x2c71aa0/d; +L_0x2c71be0/d .functor NAND 1, L_0x2c721e0, L_0x2c71a00, L_0x2c724e0, C4<1>; +L_0x2c71be0 .delay (10000,10000,10000) L_0x2c71be0/d; +L_0x2c71cd0/d .functor NAND 1, L_0x2c71910, L_0x2c72310, L_0x2c72580, C4<1>; +L_0x2c71cd0 .delay (10000,10000,10000) L_0x2c71cd0/d; +L_0x2c71dc0/d .functor NAND 1, L_0x2c721e0, L_0x2c72310, L_0x2c739b0, C4<1>; +L_0x2c71dc0 .delay (10000,10000,10000) L_0x2c71dc0/d; +L_0x2c71f30/d .functor NAND 1, L_0x2c71aa0, L_0x2c71be0, L_0x2c71cd0, L_0x2c71dc0; +L_0x2c71f30 .delay (10000,10000,10000) L_0x2c71f30/d; +v0x291c630_0 .net "S0", 0 0, L_0x2c721e0; 1 drivers +v0x291c6d0_0 .net "S1", 0 0, L_0x2c72310; 1 drivers +v0x291b7d0_0 .net "in0", 0 0, L_0x2c72440; 1 drivers +v0x291b870_0 .net "in1", 0 0, L_0x2c724e0; 1 drivers +v0x291ee10_0 .net "in2", 0 0, L_0x2c72580; 1 drivers +v0x291eeb0_0 .net "in3", 0 0, L_0x2c739b0; 1 drivers +v0x291ec10_0 .net "nS0", 0 0, L_0x2c71910; 1 drivers +v0x291dd20_0 .net "nS1", 0 0, L_0x2c71a00; 1 drivers +v0x291dda0_0 .net "out", 0 0, L_0x2c71f30; 1 drivers +v0x29212c0_0 .net "out0", 0 0, L_0x2c71aa0; 1 drivers +v0x2921360_0 .net "out1", 0 0, L_0x2c71be0; 1 drivers +v0x2921080_0 .net "out2", 0 0, L_0x2c71cd0; 1 drivers +v0x29201f0_0 .net "out3", 0 0, L_0x2c71dc0; 1 drivers +S_0x2918d70 .scope module, "TwoMux" "TwoInMux" 3 294, 3 8, S_0x2918fd0; + .timescale -9 -12; +L_0x2c73a50/d .functor NOT 1, L_0x2c728d0, C4<0>, C4<0>, C4<0>; +L_0x2c73a50 .delay (10000,10000,10000) L_0x2c73a50/d; +L_0x2c73b40/d .functor AND 1, L_0x2c72970, L_0x2c73a50, C4<1>, C4<1>; +L_0x2c73b40 .delay (20000,20000,20000) L_0x2c73b40/d; +L_0x2c73c30/d .functor AND 1, L_0x2c72a60, L_0x2c728d0, C4<1>, C4<1>; +L_0x2c73c30 .delay (20000,20000,20000) L_0x2c73c30/d; +L_0x2c73d20/d .functor OR 1, L_0x2c73b40, L_0x2c73c30, C4<0>, C4<0>; +L_0x2c73d20 .delay (20000,20000,20000) L_0x2c73d20/d; +v0x29188d0_0 .net "S", 0 0, L_0x2c728d0; 1 drivers +v0x2918970_0 .net "in0", 0 0, L_0x2c72970; 1 drivers +v0x2963680_0 .net "in1", 0 0, L_0x2c72a60; 1 drivers +v0x2963720_0 .net "nS", 0 0, L_0x2c73a50; 1 drivers +v0x2963430_0 .net "out0", 0 0, L_0x2c73b40; 1 drivers +v0x29634d0_0 .net "out1", 0 0, L_0x2c73c30; 1 drivers +v0x2962610_0 .net "outfinal", 0 0, L_0x2c73d20; 1 drivers +S_0x290cf50 .scope generate, "muxbits[27]" "muxbits[27]" 3 290, 3 290, S_0x29738d0; + .timescale -9 -12; +P_0x2903cf8 .param/l "i" 3 290, +C4<011011>; +L_0x2c753e0/d .functor OR 1, L_0x2c754e0, L_0x2c75580, C4<0>, C4<0>; +L_0x2c753e0 .delay (20000,20000,20000) L_0x2c753e0/d; +v0x29178f0_0 .net *"_s15", 0 0, L_0x2c754e0; 1 drivers +v0x29173d0_0 .net *"_s16", 0 0, L_0x2c75580; 1 drivers +S_0x2913450 .scope module, "ZeroMux" "FourInMux" 3 292, 3 24, S_0x290cf50; + .timescale -9 -12; +L_0x2c72ec0/d .functor NOT 1, L_0x2c73760, C4<0>, C4<0>, C4<0>; +L_0x2c72ec0 .delay (10000,10000,10000) L_0x2c72ec0/d; +L_0x2c72fb0/d .functor NOT 1, L_0x2c73890, C4<0>, C4<0>, C4<0>; +L_0x2c72fb0 .delay (10000,10000,10000) L_0x2c72fb0/d; +L_0x2c73050/d .functor NAND 1, L_0x2c72ec0, L_0x2c72fb0, L_0x2c750c0, C4<1>; +L_0x2c73050 .delay (10000,10000,10000) L_0x2c73050/d; +L_0x2c73190/d .functor NAND 1, L_0x2c73760, L_0x2c72fb0, L_0x2c73f00, C4<1>; +L_0x2c73190 .delay (10000,10000,10000) L_0x2c73190/d; +L_0x2c73280/d .functor NAND 1, L_0x2c72ec0, L_0x2c73890, L_0x2c73fa0, C4<1>; +L_0x2c73280 .delay (10000,10000,10000) L_0x2c73280/d; +L_0x2c73370/d .functor NAND 1, L_0x2c73760, L_0x2c73890, L_0x2c74090, C4<1>; +L_0x2c73370 .delay (10000,10000,10000) L_0x2c73370/d; +L_0x2c734b0/d .functor NAND 1, L_0x2c73050, L_0x2c73190, L_0x2c73280, L_0x2c73370; +L_0x2c734b0 .delay (10000,10000,10000) L_0x2c734b0/d; +v0x2915070_0 .net "S0", 0 0, L_0x2c73760; 1 drivers +v0x2915110_0 .net "S1", 0 0, L_0x2c73890; 1 drivers +v0x2914e10_0 .net "in0", 0 0, L_0x2c750c0; 1 drivers +v0x2914eb0_0 .net "in1", 0 0, L_0x2c73f00; 1 drivers +v0x2914970_0 .net "in2", 0 0, L_0x2c73fa0; 1 drivers +v0x2914a10_0 .net "in3", 0 0, L_0x2c74090; 1 drivers +v0x29165b0_0 .net "nS0", 0 0, L_0x2c72ec0; 1 drivers +v0x2916330_0 .net "nS1", 0 0, L_0x2c72fb0; 1 drivers +v0x29163d0_0 .net "out", 0 0, L_0x2c734b0; 1 drivers +v0x2915e90_0 .net "out0", 0 0, L_0x2c73050; 1 drivers +v0x2915f30_0 .net "out1", 0 0, L_0x2c73190; 1 drivers +v0x2917ab0_0 .net "out2", 0 0, L_0x2c73280; 1 drivers +v0x2917850_0 .net "out3", 0 0, L_0x2c73370; 1 drivers +S_0x2911110 .scope module, "OneMux" "FourInMux" 3 293, 3 24, S_0x290cf50; + .timescale -9 -12; +L_0x2c74180/d .functor NOT 1, L_0x2c74a40, C4<0>, C4<0>, C4<0>; +L_0x2c74180 .delay (10000,10000,10000) L_0x2c74180/d; +L_0x2c74230/d .functor NOT 1, L_0x2c74b70, C4<0>, C4<0>, C4<0>; +L_0x2c74230 .delay (10000,10000,10000) L_0x2c74230/d; +L_0x2c742d0/d .functor NAND 1, L_0x2c74180, L_0x2c74230, L_0x2c74ca0, C4<1>; +L_0x2c742d0 .delay (10000,10000,10000) L_0x2c742d0/d; +L_0x2c74410/d .functor NAND 1, L_0x2c74a40, L_0x2c74230, L_0x2c74d40, C4<1>; +L_0x2c74410 .delay (10000,10000,10000) L_0x2c74410/d; +L_0x2c74500/d .functor NAND 1, L_0x2c74180, L_0x2c74b70, L_0x2c74de0, C4<1>; +L_0x2c74500 .delay (10000,10000,10000) L_0x2c74500/d; +L_0x2c74620/d .functor NAND 1, L_0x2c74a40, L_0x2c74b70, L_0x2c74ed0, C4<1>; +L_0x2c74620 .delay (10000,10000,10000) L_0x2c74620/d; +L_0x2c74790/d .functor NAND 1, L_0x2c742d0, L_0x2c74410, L_0x2c74500, L_0x2c74620; +L_0x2c74790 .delay (10000,10000,10000) L_0x2c74790/d; +v0x290f590_0 .net "S0", 0 0, L_0x2c74a40; 1 drivers +v0x2910eb0_0 .net "S1", 0 0, L_0x2c74b70; 1 drivers +v0x2910f30_0 .net "in0", 0 0, L_0x2c74ca0; 1 drivers +v0x2910a10_0 .net "in1", 0 0, L_0x2c74d40; 1 drivers +v0x2910ab0_0 .net "in2", 0 0, L_0x2c74de0; 1 drivers +v0x2912630_0 .net "in3", 0 0, L_0x2c74ed0; 1 drivers +v0x29126d0_0 .net "nS0", 0 0, L_0x2c74180; 1 drivers +v0x29123f0_0 .net "nS1", 0 0, L_0x2c74230; 1 drivers +v0x2911f30_0 .net "out", 0 0, L_0x2c74790; 1 drivers +v0x2911fd0_0 .net "out0", 0 0, L_0x2c742d0; 1 drivers +v0x2913b50_0 .net "out1", 0 0, L_0x2c74410; 1 drivers +v0x2913bf0_0 .net "out2", 0 0, L_0x2c74500; 1 drivers +v0x2913980_0 .net "out3", 0 0, L_0x2c74620; 1 drivers +S_0x290e6d0 .scope module, "TwoMux" "TwoInMux" 3 294, 3 8, S_0x290cf50; + .timescale -9 -12; +L_0x2c74fc0/d .functor NOT 1, L_0x2c766c0, C4<0>, C4<0>, C4<0>; +L_0x2c74fc0 .delay (10000,10000,10000) L_0x2c74fc0/d; +L_0x2c76340/d .functor AND 1, L_0x2c75160, L_0x2c74fc0, C4<1>, C4<1>; +L_0x2c76340 .delay (20000,20000,20000) L_0x2c76340/d; +L_0x2c763f0/d .functor AND 1, L_0x2c75250, L_0x2c766c0, C4<1>, C4<1>; +L_0x2c763f0 .delay (20000,20000,20000) L_0x2c763f0/d; +L_0x2c764e0/d .functor OR 1, L_0x2c76340, L_0x2c763f0, C4<0>, C4<0>; +L_0x2c764e0 .delay (20000,20000,20000) L_0x2c764e0/d; +v0x290e470_0 .net "S", 0 0, L_0x2c766c0; 1 drivers +v0x290e510_0 .net "in0", 0 0, L_0x2c75160; 1 drivers +v0x290dfd0_0 .net "in1", 0 0, L_0x2c75250; 1 drivers +v0x290e070_0 .net "nS", 0 0, L_0x2c74fc0; 1 drivers +v0x290fc10_0 .net "out0", 0 0, L_0x2c76340; 1 drivers +v0x290f990_0 .net "out1", 0 0, L_0x2c763f0; 1 drivers +v0x290f4f0_0 .net "outfinal", 0 0, L_0x2c764e0; 1 drivers +S_0x28fd050 .scope generate, "muxbits[28]" "muxbits[28]" 3 290, 3 290, S_0x29738d0; + .timescale -9 -12; +P_0x28f3d58 .param/l "i" 3 290, +C4<011100>; +L_0x2c77e50/d .functor OR 1, L_0x2c77f90, L_0x2c78030, C4<0>, C4<0>; +L_0x2c77e50 .delay (20000,20000,20000) L_0x2c77e50/d; +v0x290bab0_0 .net *"_s15", 0 0, L_0x2c77f90; 1 drivers +v0x290d1b0_0 .net *"_s16", 0 0, L_0x2c78030; 1 drivers +S_0x2906510 .scope module, "ZeroMux" "FourInMux" 3 292, 3 24, S_0x28fd050; + .timescale -9 -12; +L_0x2c75670/d .functor NOT 1, L_0x2c75f10, C4<0>, C4<0>, C4<0>; +L_0x2c75670 .delay (10000,10000,10000) L_0x2c75670/d; +L_0x2c75760/d .functor NOT 1, L_0x2c76040, C4<0>, C4<0>, C4<0>; +L_0x2c75760 .delay (10000,10000,10000) L_0x2c75760/d; +L_0x2c75800/d .functor NAND 1, L_0x2c75670, L_0x2c75760, L_0x2c76170, C4<1>; +L_0x2c75800 .delay (10000,10000,10000) L_0x2c75800/d; +L_0x2c75940/d .functor NAND 1, L_0x2c75f10, L_0x2c75760, L_0x2c76210, C4<1>; +L_0x2c75940 .delay (10000,10000,10000) L_0x2c75940/d; +L_0x2c75a30/d .functor NAND 1, L_0x2c75670, L_0x2c76040, L_0x2c77950, C4<1>; +L_0x2c75a30 .delay (10000,10000,10000) L_0x2c75a30/d; +L_0x2c75b20/d .functor NAND 1, L_0x2c75f10, L_0x2c76040, L_0x2c77a40, C4<1>; +L_0x2c75b20 .delay (10000,10000,10000) L_0x2c75b20/d; +L_0x2c75c60/d .functor NAND 1, L_0x2c75800, L_0x2c75940, L_0x2c75a30, L_0x2c75b20; +L_0x2c75c60 .delay (10000,10000,10000) L_0x2c75c60/d; +v0x2907cb0_0 .net "S0", 0 0, L_0x2c75f10; 1 drivers +v0x2907a50_0 .net "S1", 0 0, L_0x2c76040; 1 drivers +v0x2907af0_0 .net "in0", 0 0, L_0x2c76170; 1 drivers +v0x29091f0_0 .net "in1", 0 0, L_0x2c76210; 1 drivers +v0x2909270_0 .net "in2", 0 0, L_0x2c77950; 1 drivers +v0x2908f90_0 .net "in3", 0 0, L_0x2c77a40; 1 drivers +v0x2909030_0 .net "nS0", 0 0, L_0x2c75670; 1 drivers +v0x290a730_0 .net "nS1", 0 0, L_0x2c75760; 1 drivers +v0x290a7d0_0 .net "out", 0 0, L_0x2c75c60; 1 drivers +v0x290a4d0_0 .net "out0", 0 0, L_0x2c75800; 1 drivers +v0x290a550_0 .net "out1", 0 0, L_0x2c75940; 1 drivers +v0x290bc70_0 .net "out2", 0 0, L_0x2c75a30; 1 drivers +v0x290ba10_0 .net "out3", 0 0, L_0x2c75b20; 1 drivers +S_0x2901270 .scope module, "OneMux" "FourInMux" 3 293, 3 24, S_0x28fd050; + .timescale -9 -12; +L_0x2c75b80/d .functor NOT 1, L_0x2c76ff0, C4<0>, C4<0>, C4<0>; +L_0x2c75b80 .delay (10000,10000,10000) L_0x2c75b80/d; +L_0x2c767b0/d .functor NOT 1, L_0x2c77120, C4<0>, C4<0>, C4<0>; +L_0x2c767b0 .delay (10000,10000,10000) L_0x2c767b0/d; +L_0x2c76850/d .functor NAND 1, L_0x2c75b80, L_0x2c767b0, L_0x2c77250, C4<1>; +L_0x2c76850 .delay (10000,10000,10000) L_0x2c76850/d; +L_0x2c76990/d .functor NAND 1, L_0x2c76ff0, L_0x2c767b0, L_0x2c772f0, C4<1>; +L_0x2c76990 .delay (10000,10000,10000) L_0x2c76990/d; +L_0x2c76a80/d .functor NAND 1, L_0x2c75b80, L_0x2c77120, L_0x2c77390, C4<1>; +L_0x2c76a80 .delay (10000,10000,10000) L_0x2c76a80/d; +L_0x2c76bd0/d .functor NAND 1, L_0x2c76ff0, L_0x2c77120, L_0x2c77480, C4<1>; +L_0x2c76bd0 .delay (10000,10000,10000) L_0x2c76bd0/d; +L_0x2c76d40/d .functor NAND 1, L_0x2c76850, L_0x2c76990, L_0x2c76a80, L_0x2c76bd0; +L_0x2c76d40 .delay (10000,10000,10000) L_0x2c76d40/d; +v0x2901010_0 .net "S0", 0 0, L_0x2c76ff0; 1 drivers +v0x29010b0_0 .net "S1", 0 0, L_0x2c77120; 1 drivers +v0x29027b0_0 .net "in0", 0 0, L_0x2c77250; 1 drivers +v0x2902850_0 .net "in1", 0 0, L_0x2c772f0; 1 drivers +v0x2902550_0 .net "in2", 0 0, L_0x2c77390; 1 drivers +v0x29025f0_0 .net "in3", 0 0, L_0x2c77480; 1 drivers +v0x2903d50_0 .net "nS0", 0 0, L_0x2c75b80; 1 drivers +v0x2903a90_0 .net "nS1", 0 0, L_0x2c767b0; 1 drivers +v0x2903b10_0 .net "out", 0 0, L_0x2c76d40; 1 drivers +v0x2905230_0 .net "out0", 0 0, L_0x2c76850; 1 drivers +v0x29052d0_0 .net "out1", 0 0, L_0x2c76990; 1 drivers +v0x2904ff0_0 .net "out2", 0 0, L_0x2c76a80; 1 drivers +v0x2906790_0 .net "out3", 0 0, L_0x2c76bd0; 1 drivers +S_0x28fcbb0 .scope module, "TwoMux" "TwoInMux" 3 294, 3 8, S_0x28fd050; + .timescale -9 -12; +L_0x2c77570/d .functor NOT 1, L_0x2c77b30, C4<0>, C4<0>, C4<0>; +L_0x2c77570 .delay (10000,10000,10000) L_0x2c77570/d; +L_0x2c77660/d .functor AND 1, L_0x2c77bd0, L_0x2c77570, C4<1>, C4<1>; +L_0x2c77660 .delay (20000,20000,20000) L_0x2c77660/d; +L_0x2c77750/d .functor AND 1, L_0x2c77cc0, L_0x2c77b30, C4<1>, C4<1>; +L_0x2c77750 .delay (20000,20000,20000) L_0x2c77750/d; +L_0x2c77840/d .functor OR 1, L_0x2c77660, L_0x2c77750, C4<0>, C4<0>; +L_0x2c77840 .delay (20000,20000,20000) L_0x2c77840/d; +v0x28fe7f0_0 .net "S", 0 0, L_0x2c77b30; 1 drivers +v0x28fe890_0 .net "in0", 0 0, L_0x2c77bd0; 1 drivers +v0x28fe590_0 .net "in1", 0 0, L_0x2c77cc0; 1 drivers +v0x28fe630_0 .net "nS", 0 0, L_0x2c77570; 1 drivers +v0x28ffd30_0 .net "out0", 0 0, L_0x2c77660; 1 drivers +v0x28ffdd0_0 .net "out1", 0 0, L_0x2c77750; 1 drivers +v0x28ffb30_0 .net "outfinal", 0 0, L_0x2c77840; 1 drivers +S_0x28f1160 .scope generate, "muxbits[29]" "muxbits[29]" 3 290, 3 290, S_0x29738d0; + .timescale -9 -12; +P_0x28dc518 .param/l "i" 3 290, +C4<011101>; +L_0x2c7a4a0/d .functor OR 1, L_0x2c7a5a0, L_0x2c7a640, C4<0>, C4<0>; +L_0x2c7a4a0 .delay (20000,20000,20000) L_0x2c7a4a0/d; +v0x28fb730_0 .net *"_s15", 0 0, L_0x2c7a5a0; 1 drivers +v0x28fd2d0_0 .net *"_s16", 0 0, L_0x2c7a640; 1 drivers +S_0x28f9350 .scope module, "ZeroMux" "FourInMux" 3 292, 3 24, S_0x28f1160; + .timescale -9 -12; +L_0x2c78120/d .functor NOT 1, L_0x2c789f0, C4<0>, C4<0>, C4<0>; +L_0x2c78120 .delay (10000,10000,10000) L_0x2c78120/d; +L_0x2c78210/d .functor NOT 1, L_0x2c78b20, C4<0>, C4<0>, C4<0>; +L_0x2c78210 .delay (10000,10000,10000) L_0x2c78210/d; +L_0x2c782b0/d .functor NAND 1, L_0x2c78120, L_0x2c78210, L_0x2c78c50, C4<1>; +L_0x2c782b0 .delay (10000,10000,10000) L_0x2c782b0/d; +L_0x2c783f0/d .functor NAND 1, L_0x2c789f0, L_0x2c78210, L_0x2c7a0e0, C4<1>; +L_0x2c783f0 .delay (10000,10000,10000) L_0x2c783f0/d; +L_0x2c784e0/d .functor NAND 1, L_0x2c78120, L_0x2c78b20, L_0x2c7a180, C4<1>; +L_0x2c784e0 .delay (10000,10000,10000) L_0x2c784e0/d; +L_0x2c785d0/d .functor NAND 1, L_0x2c789f0, L_0x2c78b20, L_0x2c78e50, C4<1>; +L_0x2c785d0 .delay (10000,10000,10000) L_0x2c785d0/d; +L_0x2c78740/d .functor NAND 1, L_0x2c782b0, L_0x2c783f0, L_0x2c784e0, L_0x2c785d0; +L_0x2c78740 .delay (10000,10000,10000) L_0x2c78740/d; +v0x28f90f0_0 .net "S0", 0 0, L_0x2c789f0; 1 drivers +v0x28f9190_0 .net "S1", 0 0, L_0x2c78b20; 1 drivers +v0x28f8c50_0 .net "in0", 0 0, L_0x2c78c50; 1 drivers +v0x28f8cf0_0 .net "in1", 0 0, L_0x2c7a0e0; 1 drivers +v0x28fa870_0 .net "in2", 0 0, L_0x2c7a180; 1 drivers +v0x28fa910_0 .net "in3", 0 0, L_0x2c78e50; 1 drivers +v0x28fa630_0 .net "nS0", 0 0, L_0x2c78120; 1 drivers +v0x28fa170_0 .net "nS1", 0 0, L_0x2c78210; 1 drivers +v0x28fa210_0 .net "out", 0 0, L_0x2c78740; 1 drivers +v0x28fbd90_0 .net "out0", 0 0, L_0x2c782b0; 1 drivers +v0x28fbe30_0 .net "out1", 0 0, L_0x2c783f0; 1 drivers +v0x28fbb30_0 .net "out2", 0 0, L_0x2c784e0; 1 drivers +v0x28fb690_0 .net "out3", 0 0, L_0x2c785d0; 1 drivers +S_0x28f5190 .scope module, "OneMux" "FourInMux" 3 293, 3 24, S_0x28f1160; + .timescale -9 -12; +L_0x2c78f40/d .functor NOT 1, L_0x2c79800, C4<0>, C4<0>, C4<0>; +L_0x2c78f40 .delay (10000,10000,10000) L_0x2c78f40/d; +L_0x2c78ff0/d .functor NOT 1, L_0x2c79930, C4<0>, C4<0>, C4<0>; +L_0x2c78ff0 .delay (10000,10000,10000) L_0x2c78ff0/d; +L_0x2c79090/d .functor NAND 1, L_0x2c78f40, L_0x2c78ff0, L_0x2c79a60, C4<1>; +L_0x2c79090 .delay (10000,10000,10000) L_0x2c79090/d; +L_0x2c791d0/d .functor NAND 1, L_0x2c79800, L_0x2c78ff0, L_0x2c79b00, C4<1>; +L_0x2c791d0 .delay (10000,10000,10000) L_0x2c791d0/d; +L_0x2c792c0/d .functor NAND 1, L_0x2c78f40, L_0x2c79930, L_0x2c79ba0, C4<1>; +L_0x2c792c0 .delay (10000,10000,10000) L_0x2c792c0/d; +L_0x2c793e0/d .functor NAND 1, L_0x2c79800, L_0x2c79930, L_0x2c79c90, C4<1>; +L_0x2c793e0 .delay (10000,10000,10000) L_0x2c793e0/d; +L_0x2c79550/d .functor NAND 1, L_0x2c79090, L_0x2c791d0, L_0x2c792c0, L_0x2c793e0; +L_0x2c79550 .delay (10000,10000,10000) L_0x2c79550/d; +v0x28f5490_0 .net "S0", 0 0, L_0x2c79800; 1 drivers +v0x28f4cf0_0 .net "S1", 0 0, L_0x2c79930; 1 drivers +v0x28f4d70_0 .net "in0", 0 0, L_0x2c79a60; 1 drivers +v0x28f6910_0 .net "in1", 0 0, L_0x2c79b00; 1 drivers +v0x28f69b0_0 .net "in2", 0 0, L_0x2c79ba0; 1 drivers +v0x28f66b0_0 .net "in3", 0 0, L_0x2c79c90; 1 drivers +v0x28f6750_0 .net "nS0", 0 0, L_0x2c78f40; 1 drivers +v0x28f6230_0 .net "nS1", 0 0, L_0x2c78ff0; 1 drivers +v0x28f7e30_0 .net "out", 0 0, L_0x2c79550; 1 drivers +v0x28f7ed0_0 .net "out0", 0 0, L_0x2c79090; 1 drivers +v0x28f7bd0_0 .net "out1", 0 0, L_0x2c791d0; 1 drivers +v0x28f7c70_0 .net "out2", 0 0, L_0x2c792c0; 1 drivers +v0x28f77c0_0 .net "out3", 0 0, L_0x2c793e0; 1 drivers +S_0x28f29b0 .scope module, "TwoMux" "TwoInMux" 3 294, 3 8, S_0x28f1160; + .timescale -9 -12; +L_0x2c79d80/d .functor NOT 1, L_0x2c7b680, C4<0>, C4<0>, C4<0>; +L_0x2c79d80 .delay (10000,10000,10000) L_0x2c79d80/d; +L_0x2c79e70/d .functor AND 1, L_0x2c7a220, L_0x2c79d80, C4<1>, C4<1>; +L_0x2c79e70 .delay (20000,20000,20000) L_0x2c79e70/d; +L_0x2c79f60/d .functor AND 1, L_0x2c7a310, L_0x2c7b680, C4<1>, C4<1>; +L_0x2c79f60 .delay (20000,20000,20000) L_0x2c79f60/d; +L_0x2c7a050/d .functor OR 1, L_0x2c79e70, L_0x2c79f60, C4<0>, C4<0>; +L_0x2c7a050 .delay (20000,20000,20000) L_0x2c7a050/d; +v0x28f2750_0 .net "S", 0 0, L_0x2c7b680; 1 drivers +v0x28f27f0_0 .net "in0", 0 0, L_0x2c7a220; 1 drivers +v0x28f3ed0_0 .net "in1", 0 0, L_0x2c7a310; 1 drivers +v0x28f3f70_0 .net "nS", 0 0, L_0x2c79d80; 1 drivers +v0x28f3c90_0 .net "out0", 0 0, L_0x2c79e70; 1 drivers +v0x28f37d0_0 .net "out1", 0 0, L_0x2c79f60; 1 drivers +v0x28f53f0_0 .net "outfinal", 0 0, L_0x2c7a050; 1 drivers +S_0x28d4280 .scope generate, "muxbits[30]" "muxbits[30]" 3 290, 3 290, S_0x29738d0; + .timescale -9 -12; +P_0x28c0b88 .param/l "i" 3 290, +C4<011110>; +L_0x2c7cc40/d .functor OR 1, L_0x2c7cd80, L_0x2c7ce20, C4<0>, C4<0>; +L_0x2c7cc40 .delay (20000,20000,20000) L_0x2c7cc40/d; +v0x291a320_0 .net *"_s15", 0 0, L_0x2c7cd80; 1 drivers +v0x2919df0_0 .net *"_s16", 0 0, L_0x2c7ce20; 1 drivers +S_0x28e03c0 .scope module, "ZeroMux" "FourInMux" 3 292, 3 24, S_0x28d4280; + .timescale -9 -12; +L_0x2c7a730/d .functor NOT 1, L_0x2c7afa0, C4<0>, C4<0>, C4<0>; +L_0x2c7a730 .delay (10000,10000,10000) L_0x2c7a730/d; +L_0x2c7a820/d .functor NOT 1, L_0x2c7b0d0, C4<0>, C4<0>, C4<0>; +L_0x2c7a820 .delay (10000,10000,10000) L_0x2c7a820/d; +L_0x2c7a8c0/d .functor NAND 1, L_0x2c7a730, L_0x2c7a820, L_0x2c7b200, C4<1>; +L_0x2c7a8c0 .delay (10000,10000,10000) L_0x2c7a8c0/d; +L_0x2c7aa00/d .functor NAND 1, L_0x2c7afa0, L_0x2c7a820, L_0x2c7b2a0, C4<1>; +L_0x2c7aa00 .delay (10000,10000,10000) L_0x2c7aa00/d; +L_0x2c7aaf0/d .functor NAND 1, L_0x2c7a730, L_0x2c7b0d0, L_0x2c7b340, C4<1>; +L_0x2c7aaf0 .delay (10000,10000,10000) L_0x2c7aaf0/d; +L_0x2c7abe0/d .functor NAND 1, L_0x2c7afa0, L_0x2c7b0d0, L_0x2c7b430, C4<1>; +L_0x2c7abe0 .delay (10000,10000,10000) L_0x2c7abe0/d; +L_0x2c7acf0/d .functor NAND 1, L_0x2c7a8c0, L_0x2c7aa00, L_0x2c7aaf0, L_0x2c7abe0; +L_0x2c7acf0 .delay (10000,10000,10000) L_0x2c7acf0/d; +v0x28e5160_0 .net "S0", 0 0, L_0x2c7afa0; 1 drivers +v0x28e30e0_0 .net "S1", 0 0, L_0x2c7b0d0; 1 drivers +v0x28e3180_0 .net "in0", 0 0, L_0x2c7b200; 1 drivers +v0x28e7e80_0 .net "in1", 0 0, L_0x2c7b2a0; 1 drivers +v0x28e7f00_0 .net "in2", 0 0, L_0x2c7b340; 1 drivers +v0x28e5e00_0 .net "in3", 0 0, L_0x2c7b430; 1 drivers +v0x28e5ea0_0 .net "nS0", 0 0, L_0x2c7a730; 1 drivers +v0x28eaba0_0 .net "nS1", 0 0, L_0x2c7a820; 1 drivers +v0x28eac40_0 .net "out", 0 0, L_0x2c7acf0; 1 drivers +v0x28e8b20_0 .net "out0", 0 0, L_0x2c7a8c0; 1 drivers +v0x28e8ba0_0 .net "out1", 0 0, L_0x2c7aa00; 1 drivers +v0x291a4d0_0 .net "out2", 0 0, L_0x2c7aaf0; 1 drivers +v0x291a280_0 .net "out3", 0 0, L_0x2c7abe0; 1 drivers +S_0x28d9b40 .scope module, "OneMux" "FourInMux" 3 293, 3 24, S_0x28d4280; + .timescale -9 -12; +L_0x2c7b720/d .functor NOT 1, L_0x2c7bfc0, C4<0>, C4<0>, C4<0>; +L_0x2c7b720 .delay (10000,10000,10000) L_0x2c7b720/d; +L_0x2c7b810/d .functor NOT 1, L_0x2c7c0f0, C4<0>, C4<0>, C4<0>; +L_0x2c7b810 .delay (10000,10000,10000) L_0x2c7b810/d; +L_0x2c7b8b0/d .functor NAND 1, L_0x2c7b720, L_0x2c7b810, L_0x2c7c220, C4<1>; +L_0x2c7b8b0 .delay (10000,10000,10000) L_0x2c7b8b0/d; +L_0x2c7b9f0/d .functor NAND 1, L_0x2c7bfc0, L_0x2c7b810, L_0x2c7c2c0, C4<1>; +L_0x2c7b9f0 .delay (10000,10000,10000) L_0x2c7b9f0/d; +L_0x2c7bae0/d .functor NAND 1, L_0x2c7b720, L_0x2c7c0f0, L_0x2c7c360, C4<1>; +L_0x2c7bae0 .delay (10000,10000,10000) L_0x2c7bae0/d; +L_0x2c7bbd0/d .functor NAND 1, L_0x2c7bfc0, L_0x2c7c0f0, L_0x2c7c450, C4<1>; +L_0x2c7bbd0 .delay (10000,10000,10000) L_0x2c7bbd0/d; +L_0x2c7bd10/d .functor NAND 1, L_0x2c7b8b0, L_0x2c7b9f0, L_0x2c7bae0, L_0x2c7bbd0; +L_0x2c7bd10 .delay (10000,10000,10000) L_0x2c7bd10/d; +v0x28d98b0_0 .net "S0", 0 0, L_0x2c7bfc0; 1 drivers +v0x28d9950_0 .net "S1", 0 0, L_0x2c7c0f0; 1 drivers +v0x28d7da0_0 .net "in0", 0 0, L_0x2c7c220; 1 drivers +v0x28d7e40_0 .net "in1", 0 0, L_0x2c7c2c0; 1 drivers +v0x28dc7a0_0 .net "in2", 0 0, L_0x2c7c360; 1 drivers +v0x28dc840_0 .net "in3", 0 0, L_0x2c7c450; 1 drivers +v0x28dc570_0 .net "nS0", 0 0, L_0x2c7b720; 1 drivers +v0x28daa00_0 .net "nS1", 0 0, L_0x2c7b810; 1 drivers +v0x28daa80_0 .net "out", 0 0, L_0x2c7bd10; 1 drivers +v0x28df720_0 .net "out0", 0 0, L_0x2c7b8b0; 1 drivers +v0x28df7c0_0 .net "out1", 0 0, L_0x2c7b9f0; 1 drivers +v0x28dd6c0_0 .net "out2", 0 0, L_0x2c7bae0; 1 drivers +v0x28e2460_0 .net "out3", 0 0, L_0x2c7bbd0; 1 drivers +S_0x28d3ff0 .scope module, "TwoMux" "TwoInMux" 3 294, 3 8, S_0x28d4280; + .timescale -9 -12; +L_0x2c7c540/d .functor NOT 1, L_0x2c7de40, C4<0>, C4<0>, C4<0>; +L_0x2c7c540 .delay (10000,10000,10000) L_0x2c7c540/d; +L_0x2c7c630/d .functor AND 1, L_0x2c7dee0, L_0x2c7c540, C4<1>, C4<1>; +L_0x2c7c630 .delay (20000,20000,20000) L_0x2c7c630/d; +L_0x2c7c720/d .functor AND 1, L_0x2c7cab0, L_0x2c7de40, C4<1>, C4<1>; +L_0x2c7c720 .delay (20000,20000,20000) L_0x2c7c720/d; +L_0x2c7c810/d .functor OR 1, L_0x2c7c630, L_0x2c7c720, C4<0>, C4<0>; +L_0x2c7c810 .delay (20000,20000,20000) L_0x2c7c810/d; +v0x28d24e0_0 .net "S", 0 0, L_0x2c7de40; 1 drivers +v0x28d2580_0 .net "in0", 0 0, L_0x2c7dee0; 1 drivers +v0x28d6ee0_0 .net "in1", 0 0, L_0x2c7cab0; 1 drivers +v0x28d6f80_0 .net "nS", 0 0, L_0x2c7c540; 1 drivers +v0x28d6c50_0 .net "out0", 0 0, L_0x2c7c630; 1 drivers +v0x28d6cf0_0 .net "out1", 0 0, L_0x2c7c720; 1 drivers +v0x28d51a0_0 .net "outfinal", 0 0, L_0x2c7c810; 1 drivers +S_0x2979430 .scope generate, "muxbits[31]" "muxbits[31]" 3 290, 3 290, S_0x29738d0; + .timescale -9 -12; +P_0x28b1f38 .param/l "i" 3 290, +C4<011111>; +L_0x2c49a50/d .functor OR 1, L_0x2c7e5a0, L_0x2c7e640, C4<0>, C4<0>; +L_0x2c49a50 .delay (20000,20000,20000) L_0x2c49a50/d; +v0x28d1430_0 .net *"_s15", 0 0, L_0x2c7e5a0; 1 drivers +v0x28cf880_0 .net *"_s16", 0 0, L_0x2c7e640; 1 drivers +S_0x28c9260 .scope module, "ZeroMux" "FourInMux" 3 292, 3 24, S_0x2979430; + .timescale -9 -12; +L_0x2c7cf10/d .functor NOT 1, L_0x2c7d7b0, C4<0>, C4<0>, C4<0>; +L_0x2c7cf10 .delay (10000,10000,10000) L_0x2c7cf10/d; +L_0x2c7d000/d .functor NOT 1, L_0x2c7d8e0, C4<0>, C4<0>, C4<0>; +L_0x2c7d000 .delay (10000,10000,10000) L_0x2c7d000/d; +L_0x2c7d0a0/d .functor NAND 1, L_0x2c7cf10, L_0x2c7d000, L_0x2c7da10, C4<1>; +L_0x2c7d0a0 .delay (10000,10000,10000) L_0x2c7d0a0/d; +L_0x2c7d1e0/d .functor NAND 1, L_0x2c7d7b0, L_0x2c7d000, L_0x2c7dab0, C4<1>; +L_0x2c7d1e0 .delay (10000,10000,10000) L_0x2c7d1e0/d; +L_0x2c7d2d0/d .functor NAND 1, L_0x2c7cf10, L_0x2c7d8e0, L_0x2c7db50, C4<1>; +L_0x2c7d2d0 .delay (10000,10000,10000) L_0x2c7d2d0/d; +L_0x2c7d3c0/d .functor NAND 1, L_0x2c7d7b0, L_0x2c7d8e0, L_0x2c7dc40, C4<1>; +L_0x2c7d3c0 .delay (10000,10000,10000) L_0x2c7d3c0/d; +L_0x2c7d500/d .functor NAND 1, L_0x2c7d0a0, L_0x2c7d1e0, L_0x2c7d2d0, L_0x2c7d3c0; +L_0x2c7d500 .delay (10000,10000,10000) L_0x2c7d500/d; +v0x28c4540_0 .net "S0", 0 0, L_0x2c7d7b0; 1 drivers +v0x28c71e0_0 .net "S1", 0 0, L_0x2c7d8e0; 1 drivers +v0x28c7280_0 .net "in0", 0 0, L_0x2c7da10; 1 drivers +v0x28cbfa0_0 .net "in1", 0 0, L_0x2c7dab0; 1 drivers +v0x28cc020_0 .net "in2", 0 0, L_0x2c7db50; 1 drivers +v0x28c9f20_0 .net "in3", 0 0, L_0x2c7dc40; 1 drivers +v0x28ce9c0_0 .net "nS0", 0 0, L_0x2c7cf10; 1 drivers +v0x28cea60_0 .net "nS1", 0 0, L_0x2c7d000; 1 drivers +v0x28ce730_0 .net "out", 0 0, L_0x2c7d500; 1 drivers +v0x28ce7d0_0 .net "out0", 0 0, L_0x2c7d0a0; 1 drivers +v0x28ccca0_0 .net "out1", 0 0, L_0x2c7d1e0; 1 drivers +v0x28d1620_0 .net "out2", 0 0, L_0x2c7d2d0; 1 drivers +v0x28d1390_0 .net "out3", 0 0, L_0x2c7d3c0; 1 drivers +S_0x28b9100 .scope module, "OneMux" "FourInMux" 3 293, 3 24, S_0x2979430; + .timescale -9 -12; +L_0x2c7dd30/d .functor NOT 1, L_0x2c7df80, C4<0>, C4<0>, C4<0>; +L_0x2c7dd30 .delay (10000,10000,10000) L_0x2c7dd30/d; +L_0x2c45810/d .functor NOT 1, L_0x2c7e0b0, C4<0>, C4<0>, C4<0>; +L_0x2c45810 .delay (10000,10000,10000) L_0x2c45810/d; +L_0x2c458b0/d .functor NAND 1, L_0x2c7dd30, L_0x2c45810, L_0x2c7e1e0, C4<1>; +L_0x2c458b0 .delay (10000,10000,10000) L_0x2c458b0/d; +L_0x2c459f0/d .functor NAND 1, L_0x2c7df80, L_0x2c45810, L_0x2c7e280, C4<1>; +L_0x2c459f0 .delay (10000,10000,10000) L_0x2c459f0/d; +L_0x2c45ae0/d .functor NAND 1, L_0x2c7dd30, L_0x2c7e0b0, L_0x2c7e320, C4<1>; +L_0x2c45ae0 .delay (10000,10000,10000) L_0x2c45ae0/d; +L_0x2c45bd0/d .functor NAND 1, L_0x2c7df80, L_0x2c7e0b0, L_0x2c7e410, C4<1>; +L_0x2c45bd0 .delay (10000,10000,10000) L_0x2c45bd0/d; +L_0x2c45d40/d .functor NAND 1, L_0x2c458b0, L_0x2c459f0, L_0x2c45ae0, L_0x2c45bd0; +L_0x2c45d40 .delay (10000,10000,10000) L_0x2c45d40/d; +v0x28bacb0_0 .net "S0", 0 0, L_0x2c7df80; 1 drivers +v0x28bdde0_0 .net "S1", 0 0, L_0x2c7e0b0; 1 drivers +v0x28bde60_0 .net "in0", 0 0, L_0x2c7e1e0; 1 drivers +v0x28bbd60_0 .net "in1", 0 0, L_0x2c7e280; 1 drivers +v0x28bbe00_0 .net "in2", 0 0, L_0x2c7e320; 1 drivers +v0x28c0b00_0 .net "in3", 0 0, L_0x2c7e410; 1 drivers +v0x28bea80_0 .net "nS0", 0 0, L_0x2c7dd30; 1 drivers +v0x28beb20_0 .net "nS1", 0 0, L_0x2c45810; 1 drivers +v0x28c3890_0 .net "out", 0 0, L_0x2c45d40; 1 drivers +v0x28c17a0_0 .net "out0", 0 0, L_0x2c458b0; 1 drivers +v0x28c6540_0 .net "out1", 0 0, L_0x2c459f0; 1 drivers +v0x28c65e0_0 .net "out2", 0 0, L_0x2c45ae0; 1 drivers +v0x28c44c0_0 .net "out3", 0 0, L_0x2c45bd0; 1 drivers +S_0x2990a40 .scope module, "TwoMux" "TwoInMux" 3 294, 3 8, S_0x2979430; + .timescale -9 -12; +L_0x2c45c60/d .functor NOT 1, L_0x2c49730, C4<0>, C4<0>, C4<0>; +L_0x2c45c60 .delay (10000,10000,10000) L_0x2c45c60/d; +L_0x2c49370/d .functor AND 1, L_0x2c497d0, L_0x2c45c60, C4<1>, C4<1>; +L_0x2c49370 .delay (20000,20000,20000) L_0x2c49370/d; +L_0x2c49460/d .functor AND 1, L_0x2c498c0, L_0x2c49730, C4<1>, C4<1>; +L_0x2c49460 .delay (20000,20000,20000) L_0x2c49460/d; +L_0x2c49550/d .functor OR 1, L_0x2c49370, L_0x2c49460, C4<0>, C4<0>; +L_0x2c49550 .delay (20000,20000,20000) L_0x2c49550/d; +v0x2663a40_0 .net "S", 0 0, L_0x2c49730; 1 drivers +v0x28b82c0_0 .net "in0", 0 0, L_0x2c497d0; 1 drivers +v0x28b7fb0_0 .net "in1", 0 0, L_0x2c498c0; 1 drivers +v0x28b8050_0 .net "nS", 0 0, L_0x2c45c60; 1 drivers +v0x28b64d0_0 .net "out0", 0 0, L_0x2c49370; 1 drivers +v0x28baea0_0 .net "out1", 0 0, L_0x2c49460; 1 drivers +v0x28bac10_0 .net "outfinal", 0 0, L_0x2c49550; 1 drivers + .scope S_0x270e6d0; T_0 ; %vpi_call 2 150 "$dumpfile", "FullALU.vcd"; %vpi_call 2 151 "$dumpvars"; %vpi_call 2 153 "$display", "Test 4 Bit Adder Functionality"; %vpi_call 2 155 "$display", " A | B |Command| Out|ExpectedOut|Cout|OF"; - %movi 8, 2, 4; - %set/v v0x1bd6330_0, 8, 4; - %movi 8, 4, 4; - %set/v v0x1bd6530_0, 8, 4; - %set/v v0x1bd65b0_0, 0, 3; + %movi 8, 2, 32; + %set/v v0x2bc7660_0, 8, 32; + %movi 8, 4, 32; + %set/v v0x2bc7860_0, 8, 32; + %set/v v0x2bc78e0_0, 0, 3; %delay 1000000, 0; - %vpi_call 2 159 "$display", "%b | %b | %b | %b | Expect 0110| %b | %b ", v0x1bd6330_0, v0x1bd6530_0, v0x1bd65b0_0, v0x1bd63b0_0, v0x1bd68b0_0, v0x1bd6930_0; - %movi 8, 1, 4; - %set/v v0x1bd6330_0, 8, 4; - %movi 8, 6, 4; - %set/v v0x1bd6530_0, 8, 4; - %set/v v0x1bd65b0_0, 0, 3; + %vpi_call 2 159 "$display", "%b | %b | %b | %b | Expect 0110| %b | %b ", v0x2bc7660_0, v0x2bc7860_0, v0x2bc78e0_0, v0x2bc76e0_0, v0x2bc7be0_0, v0x2bc7c60_0; + %movi 8, 1, 32; + %set/v v0x2bc7660_0, 8, 32; + %movi 8, 6, 32; + %set/v v0x2bc7860_0, 8, 32; + %set/v v0x2bc78e0_0, 0, 3; %delay 1000000, 0; - %vpi_call 2 163 "$display", "%b | %b | %b | %b | Expect 0111| %b | %b ", v0x1bd6330_0, v0x1bd6530_0, v0x1bd65b0_0, v0x1bd63b0_0, v0x1bd68b0_0, v0x1bd6930_0; - %movi 8, 5, 4; - %set/v v0x1bd6330_0, 8, 4; - %movi 8, 13, 4; - %set/v v0x1bd6530_0, 8, 4; - %set/v v0x1bd65b0_0, 0, 3; + %vpi_call 2 163 "$display", "%b | %b | %b | %b | Expect 0111| %b | %b ", v0x2bc7660_0, v0x2bc7860_0, v0x2bc78e0_0, v0x2bc76e0_0, v0x2bc7be0_0, v0x2bc7c60_0; + %movi 8, 5, 32; + %set/v v0x2bc7660_0, 8, 32; + %movi 8, 13, 32; + %set/v v0x2bc7860_0, 8, 32; + %set/v v0x2bc78e0_0, 0, 3; %delay 1000000, 0; - %vpi_call 2 167 "$display", "%b | %b | %b | %b | Expect 0010| %b | %b ", v0x1bd6330_0, v0x1bd6530_0, v0x1bd65b0_0, v0x1bd63b0_0, v0x1bd68b0_0, v0x1bd6930_0; - %movi 8, 2, 4; - %set/v v0x1bd6330_0, 8, 4; - %set/v v0x1bd6530_0, 1, 4; - %set/v v0x1bd65b0_0, 0, 3; + %vpi_call 2 167 "$display", "%b | %b | %b | %b | Expect 0010| %b | %b ", v0x2bc7660_0, v0x2bc7860_0, v0x2bc78e0_0, v0x2bc76e0_0, v0x2bc7be0_0, v0x2bc7c60_0; + %movi 8, 2, 32; + %set/v v0x2bc7660_0, 8, 32; + %movi 8, 15, 32; + %set/v v0x2bc7860_0, 8, 32; + %set/v v0x2bc78e0_0, 0, 3; %delay 1000000, 0; - %vpi_call 2 171 "$display", "%b | %b | %b | %b | Expect 0001| %b | %b ", v0x1bd6330_0, v0x1bd6530_0, v0x1bd65b0_0, v0x1bd63b0_0, v0x1bd68b0_0, v0x1bd6930_0; - %movi 8, 8, 4; - %set/v v0x1bd6330_0, 8, 4; - %movi 8, 3, 4; - %set/v v0x1bd6530_0, 8, 4; - %set/v v0x1bd65b0_0, 0, 3; + %vpi_call 2 171 "$display", "%b | %b | %b | %b | Expect 0001| %b | %b ", v0x2bc7660_0, v0x2bc7860_0, v0x2bc78e0_0, v0x2bc76e0_0, v0x2bc7be0_0, v0x2bc7c60_0; + %movi 8, 8, 32; + %set/v v0x2bc7660_0, 8, 32; + %movi 8, 3, 32; + %set/v v0x2bc7860_0, 8, 32; + %set/v v0x2bc78e0_0, 0, 3; %delay 1000000, 0; - %vpi_call 2 175 "$display", "%b | %b | %b | %b | Expect 1011| %b | %b ", v0x1bd6330_0, v0x1bd6530_0, v0x1bd65b0_0, v0x1bd63b0_0, v0x1bd68b0_0, v0x1bd6930_0; - %movi 8, 12, 4; - %set/v v0x1bd6330_0, 8, 4; - %movi 8, 2, 4; - %set/v v0x1bd6530_0, 8, 4; - %set/v v0x1bd65b0_0, 0, 3; + %vpi_call 2 175 "$display", "%b | %b | %b | %b | Expect 1011| %b | %b ", v0x2bc7660_0, v0x2bc7860_0, v0x2bc78e0_0, v0x2bc76e0_0, v0x2bc7be0_0, v0x2bc7c60_0; + %movi 8, 12, 32; + %set/v v0x2bc7660_0, 8, 32; + %movi 8, 2, 32; + %set/v v0x2bc7860_0, 8, 32; + %set/v v0x2bc78e0_0, 0, 3; %delay 1000000, 0; - %vpi_call 2 179 "$display", "%b | %b | %b | %b | Expect 1110| %b | %b ", v0x1bd6330_0, v0x1bd6530_0, v0x1bd65b0_0, v0x1bd63b0_0, v0x1bd68b0_0, v0x1bd6930_0; - %movi 8, 11, 4; - %set/v v0x1bd6330_0, 8, 4; - %movi 8, 5, 4; - %set/v v0x1bd6530_0, 8, 4; - %set/v v0x1bd65b0_0, 0, 3; + %vpi_call 2 179 "$display", "%b | %b | %b | %b | Expect 1110| %b | %b ", v0x2bc7660_0, v0x2bc7860_0, v0x2bc78e0_0, v0x2bc76e0_0, v0x2bc7be0_0, v0x2bc7c60_0; + %movi 8, 11, 32; + %set/v v0x2bc7660_0, 8, 32; + %movi 8, 5, 32; + %set/v v0x2bc7860_0, 8, 32; + %set/v v0x2bc78e0_0, 0, 3; %delay 1000000, 0; - %vpi_call 2 183 "$display", "%b | %b | %b | %b | Expect 0110| %b | %b ", v0x1bd6330_0, v0x1bd6530_0, v0x1bd65b0_0, v0x1bd63b0_0, v0x1bd68b0_0, v0x1bd6930_0; - %movi 8, 7, 4; - %set/v v0x1bd6330_0, 8, 4; - %movi 8, 9, 4; - %set/v v0x1bd6530_0, 8, 4; - %set/v v0x1bd65b0_0, 0, 3; + %vpi_call 2 183 "$display", "%b | %b | %b | %b | Expect 0110| %b | %b ", v0x2bc7660_0, v0x2bc7860_0, v0x2bc78e0_0, v0x2bc76e0_0, v0x2bc7be0_0, v0x2bc7c60_0; + %movi 8, 7, 32; + %set/v v0x2bc7660_0, 8, 32; + %movi 8, 9, 32; + %set/v v0x2bc7860_0, 8, 32; + %set/v v0x2bc78e0_0, 0, 3; %delay 1000000, 0; - %vpi_call 2 187 "$display", "%b | %b | %b | %b | Expect 0000| %b | %b ", v0x1bd6330_0, v0x1bd6530_0, v0x1bd65b0_0, v0x1bd63b0_0, v0x1bd68b0_0, v0x1bd6930_0; - %movi 8, 13, 4; - %set/v v0x1bd6330_0, 8, 4; - %movi 8, 12, 4; - %set/v v0x1bd6530_0, 8, 4; - %set/v v0x1bd65b0_0, 0, 3; + %vpi_call 2 187 "$display", "%b | %b | %b | %b | Expect 0000| %b | %b ", v0x2bc7660_0, v0x2bc7860_0, v0x2bc78e0_0, v0x2bc76e0_0, v0x2bc7be0_0, v0x2bc7c60_0; + %movi 8, 13, 32; + %set/v v0x2bc7660_0, 8, 32; + %movi 8, 12, 32; + %set/v v0x2bc7860_0, 8, 32; + %set/v v0x2bc78e0_0, 0, 3; %delay 1000000, 0; - %vpi_call 2 191 "$display", "%b | %b | %b | %b | Expect 1001| %b | %b ", v0x1bd6330_0, v0x1bd6530_0, v0x1bd65b0_0, v0x1bd63b0_0, v0x1bd68b0_0, v0x1bd6930_0; - %movi 8, 14, 4; - %set/v v0x1bd6330_0, 8, 4; - %movi 8, 10, 4; - %set/v v0x1bd6530_0, 8, 4; - %set/v v0x1bd65b0_0, 0, 3; + %vpi_call 2 191 "$display", "%b | %b | %b | %b | Expect 1001| %b | %b ", v0x2bc7660_0, v0x2bc7860_0, v0x2bc78e0_0, v0x2bc76e0_0, v0x2bc7be0_0, v0x2bc7c60_0; + %movi 8, 14, 32; + %set/v v0x2bc7660_0, 8, 32; + %movi 8, 10, 32; + %set/v v0x2bc7860_0, 8, 32; + %set/v v0x2bc78e0_0, 0, 3; %delay 1000000, 0; - %vpi_call 2 195 "$display", "%b | %b | %b | %b | Expect 1000| %b | %b ", v0x1bd6330_0, v0x1bd6530_0, v0x1bd65b0_0, v0x1bd63b0_0, v0x1bd68b0_0, v0x1bd6930_0; - %movi 8, 5, 4; - %set/v v0x1bd6330_0, 8, 4; - %movi 8, 6, 4; - %set/v v0x1bd6530_0, 8, 4; - %set/v v0x1bd65b0_0, 0, 3; + %vpi_call 2 195 "$display", "%b | %b | %b | %b | Expect 1000| %b | %b ", v0x2bc7660_0, v0x2bc7860_0, v0x2bc78e0_0, v0x2bc76e0_0, v0x2bc7be0_0, v0x2bc7c60_0; + %movi 8, 5, 32; + %set/v v0x2bc7660_0, 8, 32; + %movi 8, 6, 32; + %set/v v0x2bc7860_0, 8, 32; + %set/v v0x2bc78e0_0, 0, 3; %delay 1000000, 0; - %vpi_call 2 199 "$display", "%b | %b | %b | %b | Expect XXXX| %b | %b ", v0x1bd6330_0, v0x1bd6530_0, v0x1bd65b0_0, v0x1bd63b0_0, v0x1bd68b0_0, v0x1bd6930_0; - %movi 8, 2, 4; - %set/v v0x1bd6330_0, 8, 4; - %movi 8, 7, 4; - %set/v v0x1bd6530_0, 8, 4; - %set/v v0x1bd65b0_0, 0, 3; + %vpi_call 2 199 "$display", "%b | %b | %b | %b | Expect XXXX| %b | %b ", v0x2bc7660_0, v0x2bc7860_0, v0x2bc78e0_0, v0x2bc76e0_0, v0x2bc7be0_0, v0x2bc7c60_0; + %movi 8, 2, 32; + %set/v v0x2bc7660_0, 8, 32; + %movi 8, 7, 32; + %set/v v0x2bc7860_0, 8, 32; + %set/v v0x2bc78e0_0, 0, 3; %delay 1000000, 0; - %vpi_call 2 203 "$display", "%b | %b | %b | %b | Expect XXXX| %b | %b ", v0x1bd6330_0, v0x1bd6530_0, v0x1bd65b0_0, v0x1bd63b0_0, v0x1bd68b0_0, v0x1bd6930_0; - %movi 8, 7, 4; - %set/v v0x1bd6330_0, 8, 4; - %movi 8, 7, 4; - %set/v v0x1bd6530_0, 8, 4; - %set/v v0x1bd65b0_0, 0, 3; + %vpi_call 2 203 "$display", "%b | %b | %b | %b | Expect XXXX| %b | %b ", v0x2bc7660_0, v0x2bc7860_0, v0x2bc78e0_0, v0x2bc76e0_0, v0x2bc7be0_0, v0x2bc7c60_0; + %movi 8, 7, 32; + %set/v v0x2bc7660_0, 8, 32; + %movi 8, 7, 32; + %set/v v0x2bc7860_0, 8, 32; + %set/v v0x2bc78e0_0, 0, 3; %delay 1000000, 0; - %vpi_call 2 207 "$display", "%b | %b | %b | %b | Expect XXXX| %b | %b ", v0x1bd6330_0, v0x1bd6530_0, v0x1bd65b0_0, v0x1bd63b0_0, v0x1bd68b0_0, v0x1bd6930_0; - %movi 8, 8, 4; - %set/v v0x1bd6330_0, 8, 4; - %set/v v0x1bd6530_0, 1, 4; - %set/v v0x1bd65b0_0, 0, 3; + %vpi_call 2 207 "$display", "%b | %b | %b | %b | Expect XXXX| %b | %b ", v0x2bc7660_0, v0x2bc7860_0, v0x2bc78e0_0, v0x2bc76e0_0, v0x2bc7be0_0, v0x2bc7c60_0; + %movi 8, 8, 32; + %set/v v0x2bc7660_0, 8, 32; + %movi 8, 15, 32; + %set/v v0x2bc7860_0, 8, 32; + %set/v v0x2bc78e0_0, 0, 3; %delay 1000000, 0; - %vpi_call 2 211 "$display", "%b | %b | %b | %b | Expect XXXX| %b | %b ", v0x1bd6330_0, v0x1bd6530_0, v0x1bd65b0_0, v0x1bd63b0_0, v0x1bd68b0_0, v0x1bd6930_0; - %movi 8, 8, 4; - %set/v v0x1bd6330_0, 8, 4; - %movi 8, 13, 4; - %set/v v0x1bd6530_0, 8, 4; - %set/v v0x1bd65b0_0, 0, 3; + %vpi_call 2 211 "$display", "%b | %b | %b | %b | Expect XXXX| %b | %b ", v0x2bc7660_0, v0x2bc7860_0, v0x2bc78e0_0, v0x2bc76e0_0, v0x2bc7be0_0, v0x2bc7c60_0; + %movi 8, 8, 32; + %set/v v0x2bc7660_0, 8, 32; + %movi 8, 13, 32; + %set/v v0x2bc7860_0, 8, 32; + %set/v v0x2bc78e0_0, 0, 3; %delay 1000000, 0; - %vpi_call 2 215 "$display", "%b | %b | %b | %b | Expect XXXX| %b | %b ", v0x1bd6330_0, v0x1bd6530_0, v0x1bd65b0_0, v0x1bd63b0_0, v0x1bd68b0_0, v0x1bd6930_0; - %movi 8, 11, 4; - %set/v v0x1bd6330_0, 8, 4; - %movi 8, 12, 4; - %set/v v0x1bd6530_0, 8, 4; - %set/v v0x1bd65b0_0, 0, 3; + %vpi_call 2 215 "$display", "%b | %b | %b | %b | Expect XXXX| %b | %b ", v0x2bc7660_0, v0x2bc7860_0, v0x2bc78e0_0, v0x2bc76e0_0, v0x2bc7be0_0, v0x2bc7c60_0; + %movi 8, 11, 32; + %set/v v0x2bc7660_0, 8, 32; + %movi 8, 12, 32; + %set/v v0x2bc7860_0, 8, 32; + %set/v v0x2bc78e0_0, 0, 3; %delay 1000000, 0; - %vpi_call 2 219 "$display", "%b | %b | %b | %b | Expect XXXX| %b | %b ", v0x1bd6330_0, v0x1bd6530_0, v0x1bd65b0_0, v0x1bd63b0_0, v0x1bd68b0_0, v0x1bd6930_0; + %vpi_call 2 219 "$display", "%b | %b | %b | %b | Expect XXXX| %b | %b ", v0x2bc7660_0, v0x2bc7860_0, v0x2bc78e0_0, v0x2bc76e0_0, v0x2bc7be0_0, v0x2bc7c60_0; %vpi_call 2 221 "$display", "Test 4 Bit SLT Functionality"; %vpi_call 2 223 "$display", " A | B |Command| Out|ExpectedOut|Cout|OF |SLTflag"; - %movi 8, 2, 4; - %set/v v0x1bd6330_0, 8, 4; - %movi 8, 4, 4; - %set/v v0x1bd6530_0, 8, 4; + %movi 8, 2, 32; + %set/v v0x2bc7660_0, 8, 32; + %movi 8, 4, 32; + %set/v v0x2bc7860_0, 8, 32; %movi 8, 3, 3; - %set/v v0x1bd65b0_0, 8, 3; + %set/v v0x2bc78e0_0, 8, 3; %delay 1000000, 0; - %vpi_call 2 227 "$display", "%b | %b | %b | %b | Expect 1110| %b | %b | %b", v0x1bd6330_0, v0x1bd6530_0, v0x1bd65b0_0, v0x1bd63b0_0, v0x1bd68b0_0, v0x1bd6930_0, v0x1bd6730_0; - %movi 8, 4, 4; - %set/v v0x1bd6330_0, 8, 4; - %movi 8, 2, 4; - %set/v v0x1bd6530_0, 8, 4; + %vpi_call 2 227 "$display", "%b | %b | %b | %b | Expect 1110| %b | %b | %b", v0x2bc7660_0, v0x2bc7860_0, v0x2bc78e0_0, v0x2bc76e0_0, v0x2bc7be0_0, v0x2bc7c60_0, v0x2bc7a60_0; + %movi 8, 4, 32; + %set/v v0x2bc7660_0, 8, 32; + %movi 8, 2, 32; + %set/v v0x2bc7860_0, 8, 32; %movi 8, 3, 3; - %set/v v0x1bd65b0_0, 8, 3; + %set/v v0x2bc78e0_0, 8, 3; %delay 1000000, 0; - %vpi_call 2 231 "$display", "%b | %b | %b | %b | Expect 0010| %b | %b | %b", v0x1bd6330_0, v0x1bd6530_0, v0x1bd65b0_0, v0x1bd63b0_0, v0x1bd68b0_0, v0x1bd6930_0, v0x1bd6730_0; - %movi 8, 14, 4; - %set/v v0x1bd6330_0, 8, 4; - %movi 8, 4, 4; - %set/v v0x1bd6530_0, 8, 4; + %vpi_call 2 231 "$display", "%b | %b | %b | %b | Expect 0010| %b | %b | %b", v0x2bc7660_0, v0x2bc7860_0, v0x2bc78e0_0, v0x2bc76e0_0, v0x2bc7be0_0, v0x2bc7c60_0, v0x2bc7a60_0; + %movi 8, 14, 32; + %set/v v0x2bc7660_0, 8, 32; + %movi 8, 4, 32; + %set/v v0x2bc7860_0, 8, 32; %movi 8, 3, 3; - %set/v v0x1bd65b0_0, 8, 3; + %set/v v0x2bc78e0_0, 8, 3; %delay 1000000, 0; - %vpi_call 2 235 "$display", "%b | %b | %b | %b | Expect 1010| %b | %b | %b", v0x1bd6330_0, v0x1bd6530_0, v0x1bd65b0_0, v0x1bd63b0_0, v0x1bd68b0_0, v0x1bd6930_0, v0x1bd6730_0; - %movi 8, 4, 4; - %set/v v0x1bd6330_0, 8, 4; - %movi 8, 14, 4; - %set/v v0x1bd6530_0, 8, 4; + %vpi_call 2 235 "$display", "%b | %b | %b | %b | Expect 1010| %b | %b | %b", v0x2bc7660_0, v0x2bc7860_0, v0x2bc78e0_0, v0x2bc76e0_0, v0x2bc7be0_0, v0x2bc7c60_0, v0x2bc7a60_0; + %movi 8, 4, 32; + %set/v v0x2bc7660_0, 8, 32; + %movi 8, 14, 32; + %set/v v0x2bc7860_0, 8, 32; %movi 8, 3, 3; - %set/v v0x1bd65b0_0, 8, 3; + %set/v v0x2bc78e0_0, 8, 3; %delay 1000000, 0; - %vpi_call 2 239 "$display", "%b | %b | %b | %b | Expect 0110| %b | %b | %b", v0x1bd6330_0, v0x1bd6530_0, v0x1bd65b0_0, v0x1bd63b0_0, v0x1bd68b0_0, v0x1bd6930_0, v0x1bd6730_0; - %movi 8, 14, 4; - %set/v v0x1bd6330_0, 8, 4; - %set/v v0x1bd6530_0, 1, 4; + %vpi_call 2 239 "$display", "%b | %b | %b | %b | Expect 0110| %b | %b | %b", v0x2bc7660_0, v0x2bc7860_0, v0x2bc78e0_0, v0x2bc76e0_0, v0x2bc7be0_0, v0x2bc7c60_0, v0x2bc7a60_0; + %movi 8, 14, 32; + %set/v v0x2bc7660_0, 8, 32; + %movi 8, 15, 32; + %set/v v0x2bc7860_0, 8, 32; %movi 8, 3, 3; - %set/v v0x1bd65b0_0, 8, 3; + %set/v v0x2bc78e0_0, 8, 3; %delay 1000000, 0; - %vpi_call 2 243 "$display", "%b | %b | %b | %b | Expect 1111| %b | %b | %b", v0x1bd6330_0, v0x1bd6530_0, v0x1bd65b0_0, v0x1bd63b0_0, v0x1bd68b0_0, v0x1bd6930_0, v0x1bd6730_0; - %set/v v0x1bd6330_0, 1, 4; - %movi 8, 14, 4; - %set/v v0x1bd6530_0, 8, 4; + %vpi_call 2 243 "$display", "%b | %b | %b | %b | Expect 1111| %b | %b | %b", v0x2bc7660_0, v0x2bc7860_0, v0x2bc78e0_0, v0x2bc76e0_0, v0x2bc7be0_0, v0x2bc7c60_0, v0x2bc7a60_0; + %movi 8, 15, 32; + %set/v v0x2bc7660_0, 8, 32; + %movi 8, 14, 32; + %set/v v0x2bc7860_0, 8, 32; %movi 8, 3, 3; - %set/v v0x1bd65b0_0, 8, 3; + %set/v v0x2bc78e0_0, 8, 3; %delay 1000000, 0; - %vpi_call 2 247 "$display", "%b | %b | %b | %b | Expect 0001| %b | %b | %b", v0x1bd6330_0, v0x1bd6530_0, v0x1bd65b0_0, v0x1bd63b0_0, v0x1bd68b0_0, v0x1bd6930_0, v0x1bd6730_0; - %movi 8, 13, 4; - %set/v v0x1bd6330_0, 8, 4; - %movi 8, 13, 4; - %set/v v0x1bd6530_0, 8, 4; + %vpi_call 2 247 "$display", "%b | %b | %b | %b | Expect 0001| %b | %b | %b", v0x2bc7660_0, v0x2bc7860_0, v0x2bc78e0_0, v0x2bc76e0_0, v0x2bc7be0_0, v0x2bc7c60_0, v0x2bc7a60_0; + %movi 8, 13, 32; + %set/v v0x2bc7660_0, 8, 32; + %movi 8, 13, 32; + %set/v v0x2bc7860_0, 8, 32; %movi 8, 3, 3; - %set/v v0x1bd65b0_0, 8, 3; + %set/v v0x2bc78e0_0, 8, 3; %delay 1000000, 0; - %vpi_call 2 251 "$display", "%b | %b | %b | %b | Expect 0000| %b | %b | %b", v0x1bd6330_0, v0x1bd6530_0, v0x1bd65b0_0, v0x1bd63b0_0, v0x1bd68b0_0, v0x1bd6930_0, v0x1bd6730_0; - %movi 8, 5, 4; - %set/v v0x1bd6330_0, 8, 4; - %movi 8, 5, 4; - %set/v v0x1bd6530_0, 8, 4; + %vpi_call 2 251 "$display", "%b | %b | %b | %b | Expect 0000| %b | %b | %b", v0x2bc7660_0, v0x2bc7860_0, v0x2bc78e0_0, v0x2bc76e0_0, v0x2bc7be0_0, v0x2bc7c60_0, v0x2bc7a60_0; + %movi 8, 5, 32; + %set/v v0x2bc7660_0, 8, 32; + %movi 8, 5, 32; + %set/v v0x2bc7860_0, 8, 32; %movi 8, 3, 3; - %set/v v0x1bd65b0_0, 8, 3; + %set/v v0x2bc78e0_0, 8, 3; %delay 1000000, 0; - %vpi_call 2 255 "$display", "%b | %b | %b | %b | Expect 0000| %b | %b | %b", v0x1bd6330_0, v0x1bd6530_0, v0x1bd65b0_0, v0x1bd63b0_0, v0x1bd68b0_0, v0x1bd6930_0, v0x1bd6730_0; - %movi 8, 9, 4; - %set/v v0x1bd6330_0, 8, 4; - %movi 8, 5, 4; - %set/v v0x1bd6530_0, 8, 4; + %vpi_call 2 255 "$display", "%b | %b | %b | %b | Expect 0000| %b | %b | %b", v0x2bc7660_0, v0x2bc7860_0, v0x2bc78e0_0, v0x2bc76e0_0, v0x2bc7be0_0, v0x2bc7c60_0, v0x2bc7a60_0; + %movi 8, 9, 32; + %set/v v0x2bc7660_0, 8, 32; + %movi 8, 5, 32; + %set/v v0x2bc7860_0, 8, 32; %movi 8, 3, 3; - %set/v v0x1bd65b0_0, 8, 3; + %set/v v0x2bc78e0_0, 8, 3; %delay 1000000, 0; - %vpi_call 2 259 "$display", "%b | %b | %b | %b | Expect XXXX| %b | %b | %b", v0x1bd6330_0, v0x1bd6530_0, v0x1bd65b0_0, v0x1bd63b0_0, v0x1bd68b0_0, v0x1bd6930_0, v0x1bd6730_0; + %vpi_call 2 259 "$display", "%b | %b | %b | %b | Expect XXXX| %b | %b | %b", v0x2bc7660_0, v0x2bc7860_0, v0x2bc78e0_0, v0x2bc76e0_0, v0x2bc7be0_0, v0x2bc7c60_0, v0x2bc7a60_0; %vpi_call 2 261 "$display", "Test 4 Bit AND/NAND Functionality"; %vpi_call 2 263 "$display", " A | B |Command| Out |ExpectedOut-AND"; - %set/v v0x1bd6330_0, 1, 4; - %set/v v0x1bd6530_0, 1, 4; + %movi 8, 15, 32; + %set/v v0x2bc7660_0, 8, 32; + %movi 8, 15, 32; + %set/v v0x2bc7860_0, 8, 32; %movi 8, 4, 3; - %set/v v0x1bd65b0_0, 8, 3; + %set/v v0x2bc78e0_0, 8, 3; %delay 1000000, 0; - %vpi_call 2 267 "$display", "%b | %b | %b | %b | 1111", v0x1bd6330_0, v0x1bd6530_0, v0x1bd65b0_0, v0x1bd64b0_0; - %set/v v0x1bd6330_0, 1, 4; - %movi 8, 10, 4; - %set/v v0x1bd6530_0, 8, 4; + %vpi_call 2 267 "$display", "%b | %b | %b | %b | 1111", v0x2bc7660_0, v0x2bc7860_0, v0x2bc78e0_0, v0x2bc77e0_0; + %movi 8, 15, 32; + %set/v v0x2bc7660_0, 8, 32; + %movi 8, 10, 32; + %set/v v0x2bc7860_0, 8, 32; %movi 8, 4, 3; - %set/v v0x1bd65b0_0, 8, 3; + %set/v v0x2bc78e0_0, 8, 3; %delay 1000000, 0; - %vpi_call 2 271 "$display", "%b | %b | %b | %b | 1010", v0x1bd6330_0, v0x1bd6530_0, v0x1bd65b0_0, v0x1bd64b0_0; - %set/v v0x1bd6330_0, 1, 4; - %movi 8, 5, 4; - %set/v v0x1bd6530_0, 8, 4; + %vpi_call 2 271 "$display", "%b | %b | %b | %b | 1010", v0x2bc7660_0, v0x2bc7860_0, v0x2bc78e0_0, v0x2bc77e0_0; + %movi 8, 15, 32; + %set/v v0x2bc7660_0, 8, 32; + %movi 8, 5, 32; + %set/v v0x2bc7860_0, 8, 32; %movi 8, 4, 3; - %set/v v0x1bd65b0_0, 8, 3; + %set/v v0x2bc78e0_0, 8, 3; %delay 1000000, 0; - %vpi_call 2 275 "$display", "%b | %b | %b | %b | 0101", v0x1bd6330_0, v0x1bd6530_0, v0x1bd65b0_0, v0x1bd64b0_0; - %set/v v0x1bd6330_0, 1, 4; - %set/v v0x1bd6530_0, 0, 4; + %vpi_call 2 275 "$display", "%b | %b | %b | %b | 0101", v0x2bc7660_0, v0x2bc7860_0, v0x2bc78e0_0, v0x2bc77e0_0; + %movi 8, 15, 32; + %set/v v0x2bc7660_0, 8, 32; + %set/v v0x2bc7860_0, 0, 32; %movi 8, 4, 3; - %set/v v0x1bd65b0_0, 8, 3; + %set/v v0x2bc78e0_0, 8, 3; %delay 1000000, 0; - %vpi_call 2 279 "$display", "%b | %b | %b | %b | 0000", v0x1bd6330_0, v0x1bd6530_0, v0x1bd65b0_0, v0x1bd64b0_0; + %vpi_call 2 279 "$display", "%b | %b | %b | %b | 0000", v0x2bc7660_0, v0x2bc7860_0, v0x2bc78e0_0, v0x2bc77e0_0; %vpi_call 2 282 "$display", " A | B |Command| Out |ExpectedOut-NAND"; - %set/v v0x1bd6330_0, 1, 4; - %set/v v0x1bd6530_0, 1, 4; + %movi 8, 15, 32; + %set/v v0x2bc7660_0, 8, 32; + %movi 8, 15, 32; + %set/v v0x2bc7860_0, 8, 32; %movi 8, 5, 3; - %set/v v0x1bd65b0_0, 8, 3; + %set/v v0x2bc78e0_0, 8, 3; %delay 1000000, 0; - %vpi_call 2 286 "$display", "%b | %b | %b | %b | 0000", v0x1bd6330_0, v0x1bd6530_0, v0x1bd65b0_0, v0x1bd64b0_0; - %set/v v0x1bd6330_0, 1, 4; - %movi 8, 10, 4; - %set/v v0x1bd6530_0, 8, 4; + %vpi_call 2 286 "$display", "%b | %b | %b | %b | 0000", v0x2bc7660_0, v0x2bc7860_0, v0x2bc78e0_0, v0x2bc77e0_0; + %movi 8, 15, 32; + %set/v v0x2bc7660_0, 8, 32; + %movi 8, 10, 32; + %set/v v0x2bc7860_0, 8, 32; %movi 8, 5, 3; - %set/v v0x1bd65b0_0, 8, 3; + %set/v v0x2bc78e0_0, 8, 3; %delay 1000000, 0; - %vpi_call 2 290 "$display", "%b | %b | %b | %b | 0101", v0x1bd6330_0, v0x1bd6530_0, v0x1bd65b0_0, v0x1bd64b0_0; - %set/v v0x1bd6330_0, 1, 4; - %movi 8, 5, 4; - %set/v v0x1bd6530_0, 8, 4; + %vpi_call 2 290 "$display", "%b | %b | %b | %b | 0101", v0x2bc7660_0, v0x2bc7860_0, v0x2bc78e0_0, v0x2bc77e0_0; + %movi 8, 15, 32; + %set/v v0x2bc7660_0, 8, 32; + %movi 8, 5, 32; + %set/v v0x2bc7860_0, 8, 32; %movi 8, 5, 3; - %set/v v0x1bd65b0_0, 8, 3; + %set/v v0x2bc78e0_0, 8, 3; %delay 1000000, 0; - %vpi_call 2 294 "$display", "%b | %b | %b | %b | 1010", v0x1bd6330_0, v0x1bd6530_0, v0x1bd65b0_0, v0x1bd64b0_0; - %set/v v0x1bd6330_0, 1, 4; - %set/v v0x1bd6530_0, 0, 4; + %vpi_call 2 294 "$display", "%b | %b | %b | %b | 1010", v0x2bc7660_0, v0x2bc7860_0, v0x2bc78e0_0, v0x2bc77e0_0; + %movi 8, 15, 32; + %set/v v0x2bc7660_0, 8, 32; + %set/v v0x2bc7860_0, 0, 32; %movi 8, 5, 3; - %set/v v0x1bd65b0_0, 8, 3; + %set/v v0x2bc78e0_0, 8, 3; %delay 1000000, 0; - %vpi_call 2 298 "$display", "%b | %b | %b | %b | 1111", v0x1bd6330_0, v0x1bd6530_0, v0x1bd65b0_0, v0x1bd64b0_0; + %vpi_call 2 298 "$display", "%b | %b | %b | %b | 1111", v0x2bc7660_0, v0x2bc7860_0, v0x2bc78e0_0, v0x2bc77e0_0; %vpi_call 2 300 "$display", "Test 4 Bit OR/NOR/XOR Functionality"; %vpi_call 2 302 "$display", " A | B |Command | Out |ExpectedOut-OR"; - %movi 8, 10, 4; - %set/v v0x1bd6330_0, 8, 4; - %movi 8, 5, 4; - %set/v v0x1bd6530_0, 8, 4; - %set/v v0x1bd65b0_0, 1, 3; + %movi 8, 10, 32; + %set/v v0x2bc7660_0, 8, 32; + %movi 8, 5, 32; + %set/v v0x2bc7860_0, 8, 32; + %set/v v0x2bc78e0_0, 1, 3; %delay 1000000, 0; - %vpi_call 2 306 "$display", "%b | %b | %b | %b | 1111", v0x1bd6330_0, v0x1bd6530_0, v0x1bd65b0_0, v0x1bd66b0_0; - %set/v v0x1bd6330_0, 1, 4; - %movi 8, 5, 4; - %set/v v0x1bd6530_0, 8, 4; - %set/v v0x1bd65b0_0, 1, 3; + %vpi_call 2 306 "$display", "%b | %b | %b | %b | 1111", v0x2bc7660_0, v0x2bc7860_0, v0x2bc78e0_0, v0x2bc79e0_0; + %movi 8, 15, 32; + %set/v v0x2bc7660_0, 8, 32; + %movi 8, 5, 32; + %set/v v0x2bc7860_0, 8, 32; + %set/v v0x2bc78e0_0, 1, 3; %delay 1000000, 0; - %vpi_call 2 310 "$display", "%b | %b | %b | %b | 1111", v0x1bd6330_0, v0x1bd6530_0, v0x1bd65b0_0, v0x1bd66b0_0; - %movi 8, 11, 4; - %set/v v0x1bd6330_0, 8, 4; - %set/v v0x1bd6530_0, 0, 4; - %set/v v0x1bd65b0_0, 1, 3; + %vpi_call 2 310 "$display", "%b | %b | %b | %b | 1111", v0x2bc7660_0, v0x2bc7860_0, v0x2bc78e0_0, v0x2bc79e0_0; + %movi 8, 11, 32; + %set/v v0x2bc7660_0, 8, 32; + %set/v v0x2bc7860_0, 0, 32; + %set/v v0x2bc78e0_0, 1, 3; %delay 1000000, 0; - %vpi_call 2 314 "$display", "%b | %b | %b | %b | 1011", v0x1bd6330_0, v0x1bd6530_0, v0x1bd65b0_0, v0x1bd66b0_0; + %vpi_call 2 314 "$display", "%b | %b | %b | %b | 1011", v0x2bc7660_0, v0x2bc7860_0, v0x2bc78e0_0, v0x2bc79e0_0; %vpi_call 2 316 "$display", " A | B |Command | Out |ExpectedOut-NOR"; - %movi 8, 10, 4; - %set/v v0x1bd6330_0, 8, 4; - %movi 8, 5, 4; - %set/v v0x1bd6530_0, 8, 4; + %movi 8, 10, 32; + %set/v v0x2bc7660_0, 8, 32; + %movi 8, 5, 32; + %set/v v0x2bc7860_0, 8, 32; %movi 8, 6, 3; - %set/v v0x1bd65b0_0, 8, 3; + %set/v v0x2bc78e0_0, 8, 3; %delay 1000000, 0; - %vpi_call 2 320 "$display", "%b | %b | %b | %b | 0000", v0x1bd6330_0, v0x1bd6530_0, v0x1bd65b0_0, v0x1bd66b0_0; - %set/v v0x1bd6330_0, 1, 4; - %movi 8, 5, 4; - %set/v v0x1bd6530_0, 8, 4; + %vpi_call 2 320 "$display", "%b | %b | %b | %b | 0000", v0x2bc7660_0, v0x2bc7860_0, v0x2bc78e0_0, v0x2bc79e0_0; + %movi 8, 15, 32; + %set/v v0x2bc7660_0, 8, 32; + %movi 8, 5, 32; + %set/v v0x2bc7860_0, 8, 32; %movi 8, 6, 3; - %set/v v0x1bd65b0_0, 8, 3; + %set/v v0x2bc78e0_0, 8, 3; %delay 1000000, 0; - %vpi_call 2 324 "$display", "%b | %b | %b | %b | 0000", v0x1bd6330_0, v0x1bd6530_0, v0x1bd65b0_0, v0x1bd66b0_0; - %movi 8, 11, 4; - %set/v v0x1bd6330_0, 8, 4; - %set/v v0x1bd6530_0, 0, 4; + %vpi_call 2 324 "$display", "%b | %b | %b | %b | 0000", v0x2bc7660_0, v0x2bc7860_0, v0x2bc78e0_0, v0x2bc79e0_0; + %movi 8, 11, 32; + %set/v v0x2bc7660_0, 8, 32; + %set/v v0x2bc7860_0, 0, 32; %movi 8, 6, 3; - %set/v v0x1bd65b0_0, 8, 3; + %set/v v0x2bc78e0_0, 8, 3; %delay 1000000, 0; - %vpi_call 2 328 "$display", "%b | %b | %b | %b | 0100", v0x1bd6330_0, v0x1bd6530_0, v0x1bd65b0_0, v0x1bd66b0_0; + %vpi_call 2 328 "$display", "%b | %b | %b | %b | 0100", v0x2bc7660_0, v0x2bc7860_0, v0x2bc78e0_0, v0x2bc79e0_0; %vpi_call 2 330 "$display", " A | B |Command | Out |ExpectedOut-XOR"; - %movi 8, 10, 4; - %set/v v0x1bd6330_0, 8, 4; - %movi 8, 5, 4; - %set/v v0x1bd6530_0, 8, 4; + %movi 8, 10, 32; + %set/v v0x2bc7660_0, 8, 32; + %movi 8, 5, 32; + %set/v v0x2bc7860_0, 8, 32; %movi 8, 2, 3; - %set/v v0x1bd65b0_0, 8, 3; + %set/v v0x2bc78e0_0, 8, 3; %delay 1000000, 0; - %vpi_call 2 334 "$display", "%b | %b | %b | %b | 1111", v0x1bd6330_0, v0x1bd6530_0, v0x1bd65b0_0, v0x1bd66b0_0; - %set/v v0x1bd6330_0, 1, 4; - %movi 8, 5, 4; - %set/v v0x1bd6530_0, 8, 4; + %vpi_call 2 334 "$display", "%b | %b | %b | %b | 1111", v0x2bc7660_0, v0x2bc7860_0, v0x2bc78e0_0, v0x2bc79e0_0; + %movi 8, 15, 32; + %set/v v0x2bc7660_0, 8, 32; + %movi 8, 5, 32; + %set/v v0x2bc7860_0, 8, 32; %movi 8, 2, 3; - %set/v v0x1bd65b0_0, 8, 3; + %set/v v0x2bc78e0_0, 8, 3; %delay 1000000, 0; - %vpi_call 2 338 "$display", "%b | %b | %b | %b | 1010", v0x1bd6330_0, v0x1bd6530_0, v0x1bd65b0_0, v0x1bd66b0_0; - %movi 8, 11, 4; - %set/v v0x1bd6330_0, 8, 4; - %set/v v0x1bd6530_0, 0, 4; + %vpi_call 2 338 "$display", "%b | %b | %b | %b | 1010", v0x2bc7660_0, v0x2bc7860_0, v0x2bc78e0_0, v0x2bc79e0_0; + %movi 8, 11, 32; + %set/v v0x2bc7660_0, 8, 32; + %set/v v0x2bc7860_0, 0, 32; %movi 8, 2, 3; - %set/v v0x1bd65b0_0, 8, 3; + %set/v v0x2bc78e0_0, 8, 3; %delay 1000000, 0; - %vpi_call 2 342 "$display", "%b | %b | %b | %b | 1011", v0x1bd6330_0, v0x1bd6530_0, v0x1bd65b0_0, v0x1bd66b0_0; + %vpi_call 2 342 "$display", "%b | %b | %b | %b | 1011", v0x2bc7660_0, v0x2bc7860_0, v0x2bc78e0_0, v0x2bc79e0_0; %vpi_call 2 344 "$display", "Test 4 Bit ALU Functionality"; %vpi_call 2 346 "$display", " A | B |Command | Out |ExpectedOut | COut | OF |SLT|Zero"; - %set/v v0x1bd6330_0, 1, 4; - %set/v v0x1bd6530_0, 1, 4; + %movi 8, 15, 32; + %set/v v0x2bc7660_0, 8, 32; + %movi 8, 15, 32; + %set/v v0x2bc7860_0, 8, 32; %movi 8, 4, 3; - %set/v v0x1bd65b0_0, 8, 3; + %set/v v0x2bc78e0_0, 8, 3; %delay 1000000, 0; - %vpi_call 2 351 "$display", "%b | %b | %b - AND | %b | 1111 | %b | %b | %b | %b", v0x1bd6330_0, v0x1bd6530_0, v0x1bd65b0_0, v0x1bd6630_0, v0x1bd68b0_0, v0x1bd6930_0, v0x1bd6730_0, v0x1bd6430_0; - %set/v v0x1bd6330_0, 1, 4; - %set/v v0x1bd6530_0, 0, 4; + %vpi_call 2 351 "$display", "%b | %b | %b - AND | %b | 1111 | %b | %b | %b | %b", v0x2bc7660_0, v0x2bc7860_0, v0x2bc78e0_0, v0x2bc7960_0, v0x2bc7be0_0, v0x2bc7c60_0, v0x2bc7a60_0, v0x2bc7760_0; + %movi 8, 15, 32; + %set/v v0x2bc7660_0, 8, 32; + %set/v v0x2bc7860_0, 0, 32; %movi 8, 5, 3; - %set/v v0x1bd65b0_0, 8, 3; + %set/v v0x2bc78e0_0, 8, 3; %delay 1000000, 0; - %vpi_call 2 356 "$display", "%b | %b | %b - NAND | %b | 1111 | %b | %b | %b | %b", v0x1bd6330_0, v0x1bd6530_0, v0x1bd65b0_0, v0x1bd6630_0, v0x1bd68b0_0, v0x1bd6930_0, v0x1bd6730_0, v0x1bd6430_0; - %set/v v0x1bd6330_0, 1, 4; - %movi 8, 5, 4; - %set/v v0x1bd6530_0, 8, 4; - %set/v v0x1bd65b0_0, 1, 3; + %vpi_call 2 356 "$display", "%b | %b | %b - NAND | %b | 1111 | %b | %b | %b | %b", v0x2bc7660_0, v0x2bc7860_0, v0x2bc78e0_0, v0x2bc7960_0, v0x2bc7be0_0, v0x2bc7c60_0, v0x2bc7a60_0, v0x2bc7760_0; + %movi 8, 15, 32; + %set/v v0x2bc7660_0, 8, 32; + %movi 8, 5, 32; + %set/v v0x2bc7860_0, 8, 32; + %set/v v0x2bc78e0_0, 1, 3; %delay 1000000, 0; - %vpi_call 2 361 "$display", "%b | %b | %b - OR | %b | 1111 | %b | %b | %b | %b", v0x1bd6330_0, v0x1bd6530_0, v0x1bd65b0_0, v0x1bd6630_0, v0x1bd68b0_0, v0x1bd6930_0, v0x1bd6730_0, v0x1bd6430_0; - %movi 8, 11, 4; - %set/v v0x1bd6330_0, 8, 4; - %set/v v0x1bd6530_0, 0, 4; + %vpi_call 2 361 "$display", "%b | %b | %b - OR | %b | 1111 | %b | %b | %b | %b", v0x2bc7660_0, v0x2bc7860_0, v0x2bc78e0_0, v0x2bc7960_0, v0x2bc7be0_0, v0x2bc7c60_0, v0x2bc7a60_0, v0x2bc7760_0; + %movi 8, 11, 32; + %set/v v0x2bc7660_0, 8, 32; + %set/v v0x2bc7860_0, 0, 32; %movi 8, 6, 3; - %set/v v0x1bd65b0_0, 8, 3; + %set/v v0x2bc78e0_0, 8, 3; %delay 1000000, 0; - %vpi_call 2 366 "$display", "%b | %b | %b - NOR | %b | 0100 | %b | %b | %b | %b", v0x1bd6330_0, v0x1bd6530_0, v0x1bd65b0_0, v0x1bd6630_0, v0x1bd68b0_0, v0x1bd6930_0, v0x1bd6730_0, v0x1bd6430_0; - %movi 8, 11, 4; - %set/v v0x1bd6330_0, 8, 4; - %set/v v0x1bd6530_0, 0, 4; + %vpi_call 2 366 "$display", "%b | %b | %b - NOR | %b | 0100 | %b | %b | %b | %b", v0x2bc7660_0, v0x2bc7860_0, v0x2bc78e0_0, v0x2bc7960_0, v0x2bc7be0_0, v0x2bc7c60_0, v0x2bc7a60_0, v0x2bc7760_0; + %movi 8, 11, 32; + %set/v v0x2bc7660_0, 8, 32; + %set/v v0x2bc7860_0, 0, 32; %movi 8, 2, 3; - %set/v v0x1bd65b0_0, 8, 3; + %set/v v0x2bc78e0_0, 8, 3; %delay 1000000, 0; - %vpi_call 2 371 "$display", "%b | %b | %b - XOR | %b | 1011 | %b | %b | %b | %b", v0x1bd6330_0, v0x1bd6530_0, v0x1bd65b0_0, v0x1bd6630_0, v0x1bd68b0_0, v0x1bd6930_0, v0x1bd6730_0, v0x1bd6430_0; - %movi 8, 2, 4; - %set/v v0x1bd6330_0, 8, 4; - %movi 8, 4, 4; - %set/v v0x1bd6530_0, 8, 4; - %set/v v0x1bd65b0_0, 0, 3; + %vpi_call 2 371 "$display", "%b | %b | %b - XOR | %b | 1011 | %b | %b | %b | %b", v0x2bc7660_0, v0x2bc7860_0, v0x2bc78e0_0, v0x2bc7960_0, v0x2bc7be0_0, v0x2bc7c60_0, v0x2bc7a60_0, v0x2bc7760_0; + %movi 8, 2, 32; + %set/v v0x2bc7660_0, 8, 32; + %movi 8, 4, 32; + %set/v v0x2bc7860_0, 8, 32; + %set/v v0x2bc78e0_0, 0, 3; %delay 1000000, 0; - %vpi_call 2 376 "$display", "%b | %b | %b - ADD | %b | 0110 | %b | %b | %b | %b", v0x1bd6330_0, v0x1bd6530_0, v0x1bd65b0_0, v0x1bd6630_0, v0x1bd68b0_0, v0x1bd6930_0, v0x1bd6730_0, v0x1bd6430_0; - %movi 8, 11, 4; - %set/v v0x1bd6330_0, 8, 4; - %movi 8, 12, 4; - %set/v v0x1bd6530_0, 8, 4; - %set/v v0x1bd65b0_0, 0, 3; + %vpi_call 2 376 "$display", "%b | %b | %b - ADD | %b | 0110 | %b | %b | %b | %b", v0x2bc7660_0, v0x2bc7860_0, v0x2bc78e0_0, v0x2bc7960_0, v0x2bc7be0_0, v0x2bc7c60_0, v0x2bc7a60_0, v0x2bc7760_0; + %movi 8, 11, 32; + %set/v v0x2bc7660_0, 8, 32; + %movi 8, 12, 32; + %set/v v0x2bc7860_0, 8, 32; + %set/v v0x2bc78e0_0, 0, 3; %delay 1000000, 0; - %vpi_call 2 380 "$display", "%b | %b | %b - ADD | %b | XXXX | %b | %b | %b | %b", v0x1bd6330_0, v0x1bd6530_0, v0x1bd65b0_0, v0x1bd6630_0, v0x1bd68b0_0, v0x1bd6930_0, v0x1bd6730_0, v0x1bd6430_0; - %movi 8, 2, 4; - %set/v v0x1bd6330_0, 8, 4; - %movi 8, 4, 4; - %set/v v0x1bd6530_0, 8, 4; + %vpi_call 2 380 "$display", "%b | %b | %b - ADD | %b | XXXX | %b | %b | %b | %b", v0x2bc7660_0, v0x2bc7860_0, v0x2bc78e0_0, v0x2bc7960_0, v0x2bc7be0_0, v0x2bc7c60_0, v0x2bc7a60_0, v0x2bc7760_0; + %movi 8, 2, 32; + %set/v v0x2bc7660_0, 8, 32; + %movi 8, 4, 32; + %set/v v0x2bc7860_0, 8, 32; %movi 8, 1, 3; - %set/v v0x1bd65b0_0, 8, 3; + %set/v v0x2bc78e0_0, 8, 3; %delay 1000000, 0; - %vpi_call 2 385 "$display", "%b | %b | %b - SUB | %b | 1110 | %b | %b | %b | %b", v0x1bd6330_0, v0x1bd6530_0, v0x1bd65b0_0, v0x1bd6630_0, v0x1bd68b0_0, v0x1bd6930_0, v0x1bd6730_0, v0x1bd6430_0; - %movi 8, 9, 4; - %set/v v0x1bd6330_0, 8, 4; - %movi 8, 3, 4; - %set/v v0x1bd6530_0, 8, 4; + %vpi_call 2 385 "$display", "%b | %b | %b - SUB | %b | 1110 | %b | %b | %b | %b", v0x2bc7660_0, v0x2bc7860_0, v0x2bc78e0_0, v0x2bc7960_0, v0x2bc7be0_0, v0x2bc7c60_0, v0x2bc7a60_0, v0x2bc7760_0; + %movi 8, 9, 32; + %set/v v0x2bc7660_0, 8, 32; + %movi 8, 3, 32; + %set/v v0x2bc7860_0, 8, 32; %movi 8, 1, 3; - %set/v v0x1bd65b0_0, 8, 3; + %set/v v0x2bc78e0_0, 8, 3; %delay 1000000, 0; - %vpi_call 2 389 "$display", "%b | %b | %b - SUB | %b | XXXX | %b | %b | %b | %b", v0x1bd6330_0, v0x1bd6530_0, v0x1bd65b0_0, v0x1bd6630_0, v0x1bd68b0_0, v0x1bd6930_0, v0x1bd6730_0, v0x1bd6430_0; - %movi 8, 4, 4; - %set/v v0x1bd6330_0, 8, 4; - %movi 8, 2, 4; - %set/v v0x1bd6530_0, 8, 4; + %vpi_call 2 389 "$display", "%b | %b | %b - SUB | %b | XXXX | %b | %b | %b | %b", v0x2bc7660_0, v0x2bc7860_0, v0x2bc78e0_0, v0x2bc7960_0, v0x2bc7be0_0, v0x2bc7c60_0, v0x2bc7a60_0, v0x2bc7760_0; + %movi 8, 4, 32; + %set/v v0x2bc7660_0, 8, 32; + %movi 8, 2, 32; + %set/v v0x2bc7860_0, 8, 32; %movi 8, 3, 3; - %set/v v0x1bd65b0_0, 8, 3; + %set/v v0x2bc78e0_0, 8, 3; %delay 1000000, 0; - %vpi_call 2 395 "$display", "%b | %b | %b - SLT | %b | 0010 | %b | %b | %b | %b", v0x1bd6330_0, v0x1bd6530_0, v0x1bd65b0_0, v0x1bd6630_0, v0x1bd68b0_0, v0x1bd6930_0, v0x1bd6730_0, v0x1bd6430_0; - %movi 8, 9, 4; - %set/v v0x1bd6330_0, 8, 4; - %movi 8, 5, 4; - %set/v v0x1bd6530_0, 8, 4; + %vpi_call 2 395 "$display", "%b | %b | %b - SLT | %b | 0010 | %b | %b | %b | %b", v0x2bc7660_0, v0x2bc7860_0, v0x2bc78e0_0, v0x2bc7960_0, v0x2bc7be0_0, v0x2bc7c60_0, v0x2bc7a60_0, v0x2bc7760_0; + %movi 8, 9, 32; + %set/v v0x2bc7660_0, 8, 32; + %movi 8, 5, 32; + %set/v v0x2bc7860_0, 8, 32; %movi 8, 3, 3; - %set/v v0x1bd65b0_0, 8, 3; + %set/v v0x2bc78e0_0, 8, 3; %delay 1000000, 0; - %vpi_call 2 399 "$display", "%b | %b | %b - SLT | %b | XXXX | %b | %b | %b | %b", v0x1bd6330_0, v0x1bd6530_0, v0x1bd65b0_0, v0x1bd6630_0, v0x1bd68b0_0, v0x1bd6930_0, v0x1bd6730_0, v0x1bd6430_0; - %set/v v0x1bd6330_0, 0, 4; - %set/v v0x1bd6530_0, 1, 4; + %vpi_call 2 399 "$display", "%b | %b | %b - SLT | %b | XXXX | %b | %b | %b | %b", v0x2bc7660_0, v0x2bc7860_0, v0x2bc78e0_0, v0x2bc7960_0, v0x2bc7be0_0, v0x2bc7c60_0, v0x2bc7a60_0, v0x2bc7760_0; + %set/v v0x2bc7660_0, 0, 32; + %movi 8, 15, 32; + %set/v v0x2bc7860_0, 8, 32; %movi 8, 4, 3; - %set/v v0x1bd65b0_0, 8, 3; + %set/v v0x2bc78e0_0, 8, 3; %delay 1000000, 0; - %vpi_call 2 405 "$display", "%b | %b | %b - AND | %b | 0000 | %b | %b | %b | %b", v0x1bd6330_0, v0x1bd6530_0, v0x1bd65b0_0, v0x1bd6630_0, v0x1bd68b0_0, v0x1bd6930_0, v0x1bd6730_0, v0x1bd6430_0; - %set/v v0x1bd6330_0, 1, 4; - %set/v v0x1bd6530_0, 1, 4; + %vpi_call 2 405 "$display", "%b | %b | %b - AND | %b | 0000 | %b | %b | %b | %b", v0x2bc7660_0, v0x2bc7860_0, v0x2bc78e0_0, v0x2bc7960_0, v0x2bc7be0_0, v0x2bc7c60_0, v0x2bc7a60_0, v0x2bc7760_0; + %movi 8, 15, 32; + %set/v v0x2bc7660_0, 8, 32; + %movi 8, 15, 32; + %set/v v0x2bc7860_0, 8, 32; %movi 8, 5, 3; - %set/v v0x1bd65b0_0, 8, 3; + %set/v v0x2bc78e0_0, 8, 3; %delay 1000000, 0; - %vpi_call 2 408 "$display", "%b | %b | %b - NAND | %b | 0000 | %b | %b | %b | %b", v0x1bd6330_0, v0x1bd6530_0, v0x1bd65b0_0, v0x1bd6630_0, v0x1bd68b0_0, v0x1bd6930_0, v0x1bd6730_0, v0x1bd6430_0; - %set/v v0x1bd6330_0, 0, 4; - %set/v v0x1bd6530_0, 0, 4; - %set/v v0x1bd65b0_0, 1, 3; + %vpi_call 2 408 "$display", "%b | %b | %b - NAND | %b | 0000 | %b | %b | %b | %b", v0x2bc7660_0, v0x2bc7860_0, v0x2bc78e0_0, v0x2bc7960_0, v0x2bc7be0_0, v0x2bc7c60_0, v0x2bc7a60_0, v0x2bc7760_0; + %set/v v0x2bc7660_0, 0, 32; + %set/v v0x2bc7860_0, 0, 32; + %set/v v0x2bc78e0_0, 1, 3; %delay 1000000, 0; - %vpi_call 2 411 "$display", "%b | %b | %b - OR | %b | 0000 | %b | %b | %b | %b", v0x1bd6330_0, v0x1bd6530_0, v0x1bd65b0_0, v0x1bd6630_0, v0x1bd68b0_0, v0x1bd6930_0, v0x1bd6730_0, v0x1bd6430_0; - %movi 8, 11, 4; - %set/v v0x1bd6330_0, 8, 4; - %movi 8, 4, 4; - %set/v v0x1bd6530_0, 8, 4; + %vpi_call 2 411 "$display", "%b | %b | %b - OR | %b | 0000 | %b | %b | %b | %b", v0x2bc7660_0, v0x2bc7860_0, v0x2bc78e0_0, v0x2bc7960_0, v0x2bc7be0_0, v0x2bc7c60_0, v0x2bc7a60_0, v0x2bc7760_0; + %movi 8, 11, 32; + %set/v v0x2bc7660_0, 8, 32; + %movi 8, 4, 32; + %set/v v0x2bc7860_0, 8, 32; %movi 8, 6, 3; - %set/v v0x1bd65b0_0, 8, 3; + %set/v v0x2bc78e0_0, 8, 3; %delay 1000000, 0; - %vpi_call 2 413 "$display", "%b | %b | %b - NOR | %b | 0000 | %b | %b | %b | %b", v0x1bd6330_0, v0x1bd6530_0, v0x1bd65b0_0, v0x1bd6630_0, v0x1bd68b0_0, v0x1bd6930_0, v0x1bd6730_0, v0x1bd6430_0; - %movi 8, 11, 4; - %set/v v0x1bd6330_0, 8, 4; - %movi 8, 11, 4; - %set/v v0x1bd6530_0, 8, 4; + %vpi_call 2 413 "$display", "%b | %b | %b - NOR | %b | 0000 | %b | %b | %b | %b", v0x2bc7660_0, v0x2bc7860_0, v0x2bc78e0_0, v0x2bc7960_0, v0x2bc7be0_0, v0x2bc7c60_0, v0x2bc7a60_0, v0x2bc7760_0; + %movi 8, 11, 32; + %set/v v0x2bc7660_0, 8, 32; + %movi 8, 11, 32; + %set/v v0x2bc7860_0, 8, 32; %movi 8, 2, 3; - %set/v v0x1bd65b0_0, 8, 3; + %set/v v0x2bc78e0_0, 8, 3; %delay 1000000, 0; - %vpi_call 2 416 "$display", "%b | %b | %b - XOR | %b | 0000 | %b | %b | %b | %b", v0x1bd6330_0, v0x1bd6530_0, v0x1bd65b0_0, v0x1bd6630_0, v0x1bd68b0_0, v0x1bd6930_0, v0x1bd6730_0, v0x1bd6430_0; - %movi 8, 2, 4; - %set/v v0x1bd6330_0, 8, 4; - %movi 8, 14, 4; - %set/v v0x1bd6530_0, 8, 4; - %set/v v0x1bd65b0_0, 0, 3; + %vpi_call 2 416 "$display", "%b | %b | %b - XOR | %b | 0000 | %b | %b | %b | %b", v0x2bc7660_0, v0x2bc7860_0, v0x2bc78e0_0, v0x2bc7960_0, v0x2bc7be0_0, v0x2bc7c60_0, v0x2bc7a60_0, v0x2bc7760_0; + %movi 8, 2, 32; + %set/v v0x2bc7660_0, 8, 32; + %movi 8, 14, 32; + %set/v v0x2bc7860_0, 8, 32; + %set/v v0x2bc78e0_0, 0, 3; %delay 1000000, 0; - %vpi_call 2 419 "$display", "%b | %b | %b - ADD | %b | 0000 | %b | %b | %b | %b", v0x1bd6330_0, v0x1bd6530_0, v0x1bd65b0_0, v0x1bd6630_0, v0x1bd68b0_0, v0x1bd6930_0, v0x1bd6730_0, v0x1bd6430_0; - %movi 8, 2, 4; - %set/v v0x1bd6330_0, 8, 4; - %movi 8, 2, 4; - %set/v v0x1bd6530_0, 8, 4; + %vpi_call 2 419 "$display", "%b | %b | %b - ADD | %b | 0000 | %b | %b | %b | %b", v0x2bc7660_0, v0x2bc7860_0, v0x2bc78e0_0, v0x2bc7960_0, v0x2bc7be0_0, v0x2bc7c60_0, v0x2bc7a60_0, v0x2bc7760_0; + %movi 8, 2, 32; + %set/v v0x2bc7660_0, 8, 32; + %movi 8, 2, 32; + %set/v v0x2bc7860_0, 8, 32; %movi 8, 1, 3; - %set/v v0x1bd65b0_0, 8, 3; + %set/v v0x2bc78e0_0, 8, 3; %delay 1000000, 0; - %vpi_call 2 422 "$display", "%b | %b | %b - SUB | %b | 0000 | %b | %b | %b | %b", v0x1bd6330_0, v0x1bd6530_0, v0x1bd65b0_0, v0x1bd6630_0, v0x1bd68b0_0, v0x1bd6930_0, v0x1bd6730_0, v0x1bd6430_0; - %set/v v0x1bd6330_0, 0, 4; - %set/v v0x1bd6530_0, 0, 4; + %vpi_call 2 422 "$display", "%b | %b | %b - SUB | %b | 0000 | %b | %b | %b | %b", v0x2bc7660_0, v0x2bc7860_0, v0x2bc78e0_0, v0x2bc7960_0, v0x2bc7be0_0, v0x2bc7c60_0, v0x2bc7a60_0, v0x2bc7760_0; + %set/v v0x2bc7660_0, 0, 32; + %set/v v0x2bc7860_0, 0, 32; %movi 8, 3, 3; - %set/v v0x1bd65b0_0, 8, 3; + %set/v v0x2bc78e0_0, 8, 3; %delay 1000000, 0; - %vpi_call 2 426 "$display", "%b | %b | %b - SLT | %b | 0000 | %b | %b | %b | %b", v0x1bd6330_0, v0x1bd6530_0, v0x1bd65b0_0, v0x1bd6630_0, v0x1bd68b0_0, v0x1bd6930_0, v0x1bd6730_0, v0x1bd6430_0; + %vpi_call 2 426 "$display", "%b | %b | %b - SLT | %b | 0000 | %b | %b | %b | %b", v0x2bc7660_0, v0x2bc7860_0, v0x2bc78e0_0, v0x2bc7960_0, v0x2bc7be0_0, v0x2bc7c60_0, v0x2bc7a60_0, v0x2bc7760_0; %end; .thread T_0; # The file index is used to find the file name in the following table. diff --git a/testing.t.v b/testing.t.v index 9f0b682..922f06b 100644 --- a/testing.t.v +++ b/testing.t.v @@ -2,7 +2,7 @@ `timescale 1 ns / 1 ps `include "alu.v" -/* + module testBasicFunctions(); // we begin by testing the basic AND/NAND, OR/NOR/XOR, and ADD/SUB/SLT modules wire AndNandOut; @@ -117,10 +117,11 @@ initial begin $display("%b %b | %b | %b | 0", A, B, Command, OrNorXorOut); end endmodule -*/ + +/* module test32Adder(); -parameter size = 4; +parameter size = 32; output [size-1:0] OneBitFinalOut; output [size-1:0] OrNorXorOut; output [size-1:0] AndNandOut; @@ -424,8 +425,11 @@ A = 4'b0010; B = 4'b0010; Command =3'b001; #1000 A = 4'b0000; B = 4'b0000; Command =3'b011; #1000 $display("%b | %b | %b - SLT | %b | 0000 | %b | %b | %b | %b", A, B, Command, OneBitFinalOut, carryout, overflow, SLTflag, AllZeros); - + end endmodule +*/ + + From 9b0db367bfcbd57f5848e43c4664c35f7bb8516d Mon Sep 17 00:00:00 2001 From: mjakus Date: Tue, 10 Oct 2017 14:43:10 -0400 Subject: [PATCH 20/28] Add VCD file --- FullALU.vcd | 71565 ++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 71565 insertions(+) create mode 100644 FullALU.vcd diff --git a/FullALU.vcd b/FullALU.vcd new file mode 100644 index 0000000..043d1dd --- /dev/null +++ b/FullALU.vcd @@ -0,0 +1,71565 @@ +$date + Tue Oct 10 14:34:59 2017 +$end +$version + Icarus Verilog +$end +$timescale + 1ps +$end +$scope module test32Adder $end +$var wire 32 ! AddSubSLTSum [31:0] $end +$var wire 1 " AllZeros $end +$var wire 32 # AndNandOut [31:0] $end +$var wire 32 $ OneBitFinalOut [31:0] $end +$var wire 32 % OrNorXorOut [31:0] $end +$var wire 1 & SLTflag $end +$var wire 32 ' ZeroFlag [31:0] $end +$var wire 1 ( carryout $end +$var wire 1 ) overflow $end +$var wire 32 * subtract [31:0] $end +$var reg 32 + A [31:0] $end +$var reg 32 , B [31:0] $end +$var reg 3 - Command [2:0] $end +$var reg 32 . carryin [31:0] $end +$scope module trial $end +$var wire 32 / A [31:0] $end +$var wire 32 0 AddSubSLTSum [31:0] $end +$var wire 32 1 B [31:0] $end +$var wire 32 2 CarryoutWire [31:0] $end +$var wire 3 3 Command [2:0] $end +$var wire 1 4 Res0OF1 $end +$var wire 1 5 Res1OF0 $end +$var wire 1 & SLTflag $end +$var wire 1 6 SLTflag0 $end +$var wire 1 7 SLTflag1 $end +$var wire 1 8 SLTon $end +$var wire 32 9 carryin [31:0] $end +$var wire 1 ( carryout $end +$var wire 1 : nAddSubSLTSum $end +$var wire 1 ; nOF $end +$var wire 1 ) overflow $end +$var wire 32 < subtract [31:0] $end +$scope module attempt2 $end +$var wire 1 = A $end +$var wire 1 > AandB $end +$var wire 1 ? AddSubSLTSum $end +$var wire 1 @ AxorB $end +$var wire 1 A B $end +$var wire 1 B BornB $end +$var wire 1 C CINandAxorB $end +$var wire 3 D Command [2:0] $end +$var wire 1 E carryin $end +$var wire 1 F carryout $end +$var wire 1 G nB $end +$var wire 1 H nCmd2 $end +$var wire 1 I subtract $end +$scope module mux0 $end +$var wire 1 J S $end +$var wire 1 A in0 $end +$var wire 1 G in1 $end +$var wire 1 K nS $end +$var wire 1 L out0 $end +$var wire 1 M out1 $end +$var wire 1 B outfinal $end +$upscope $end +$upscope $end +$scope begin addbits[1] $end +$scope module attempt $end +$var wire 1 N A $end +$var wire 1 O AandB $end +$var wire 1 P AddSubSLTSum $end +$var wire 1 Q AxorB $end +$var wire 1 R B $end +$var wire 1 S BornB $end +$var wire 1 T CINandAxorB $end +$var wire 3 U Command [2:0] $end +$var wire 1 V carryin $end +$var wire 1 W carryout $end +$var wire 1 X nB $end +$var wire 1 Y nCmd2 $end +$var wire 1 Z subtract $end +$scope module mux0 $end +$var wire 1 [ S $end +$var wire 1 R in0 $end +$var wire 1 X in1 $end +$var wire 1 \ nS $end +$var wire 1 ] out0 $end +$var wire 1 ^ out1 $end +$var wire 1 S outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin addbits[2] $end +$scope module attempt $end +$var wire 1 _ A $end +$var wire 1 ` AandB $end +$var wire 1 a AddSubSLTSum $end +$var wire 1 b AxorB $end +$var wire 1 c B $end +$var wire 1 d BornB $end +$var wire 1 e CINandAxorB $end +$var wire 3 f Command [2:0] $end +$var wire 1 g carryin $end +$var wire 1 h carryout $end +$var wire 1 i nB $end +$var wire 1 j nCmd2 $end +$var wire 1 k subtract $end +$scope module mux0 $end +$var wire 1 l S $end +$var wire 1 c in0 $end +$var wire 1 i in1 $end +$var wire 1 m nS $end +$var wire 1 n out0 $end +$var wire 1 o out1 $end +$var wire 1 d outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin addbits[3] $end +$scope module attempt $end +$var wire 1 p A $end +$var wire 1 q AandB $end +$var wire 1 r AddSubSLTSum $end +$var wire 1 s AxorB $end +$var wire 1 t B $end +$var wire 1 u BornB $end +$var wire 1 v CINandAxorB $end +$var wire 3 w Command [2:0] $end +$var wire 1 x carryin $end +$var wire 1 y carryout $end +$var wire 1 z nB $end +$var wire 1 { nCmd2 $end +$var wire 1 | subtract $end +$scope module mux0 $end +$var wire 1 } S $end +$var wire 1 t in0 $end +$var wire 1 z in1 $end +$var wire 1 ~ nS $end +$var wire 1 !" out0 $end +$var wire 1 "" out1 $end +$var wire 1 u outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin addbits[4] $end +$scope module attempt $end +$var wire 1 #" A $end +$var wire 1 $" AandB $end +$var wire 1 %" AddSubSLTSum $end +$var wire 1 &" AxorB $end +$var wire 1 '" B $end +$var wire 1 (" BornB $end +$var wire 1 )" CINandAxorB $end +$var wire 3 *" Command [2:0] $end +$var wire 1 +" carryin $end +$var wire 1 ," carryout $end +$var wire 1 -" nB $end +$var wire 1 ." nCmd2 $end +$var wire 1 /" subtract $end +$scope module mux0 $end +$var wire 1 0" S $end +$var wire 1 '" in0 $end +$var wire 1 -" in1 $end +$var wire 1 1" nS $end +$var wire 1 2" out0 $end +$var wire 1 3" out1 $end +$var wire 1 (" outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin addbits[5] $end +$scope module attempt $end +$var wire 1 4" A $end +$var wire 1 5" AandB $end +$var wire 1 6" AddSubSLTSum $end +$var wire 1 7" AxorB $end +$var wire 1 8" B $end +$var wire 1 9" BornB $end +$var wire 1 :" CINandAxorB $end +$var wire 3 ;" Command [2:0] $end +$var wire 1 <" carryin $end +$var wire 1 =" carryout $end +$var wire 1 >" nB $end +$var wire 1 ?" nCmd2 $end +$var wire 1 @" subtract $end +$scope module mux0 $end +$var wire 1 A" S $end +$var wire 1 8" in0 $end +$var wire 1 >" in1 $end +$var wire 1 B" nS $end +$var wire 1 C" out0 $end +$var wire 1 D" out1 $end +$var wire 1 9" outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin addbits[6] $end +$scope module attempt $end +$var wire 1 E" A $end +$var wire 1 F" AandB $end +$var wire 1 G" AddSubSLTSum $end +$var wire 1 H" AxorB $end +$var wire 1 I" B $end +$var wire 1 J" BornB $end +$var wire 1 K" CINandAxorB $end +$var wire 3 L" Command [2:0] $end +$var wire 1 M" carryin $end +$var wire 1 N" carryout $end +$var wire 1 O" nB $end +$var wire 1 P" nCmd2 $end +$var wire 1 Q" subtract $end +$scope module mux0 $end +$var wire 1 R" S $end +$var wire 1 I" in0 $end +$var wire 1 O" in1 $end +$var wire 1 S" nS $end +$var wire 1 T" out0 $end +$var wire 1 U" out1 $end +$var wire 1 J" outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin addbits[7] $end +$scope module attempt $end +$var wire 1 V" A $end +$var wire 1 W" AandB $end +$var wire 1 X" AddSubSLTSum $end +$var wire 1 Y" AxorB $end +$var wire 1 Z" B $end +$var wire 1 [" BornB $end +$var wire 1 \" CINandAxorB $end +$var wire 3 ]" Command [2:0] $end +$var wire 1 ^" carryin $end +$var wire 1 _" carryout $end +$var wire 1 `" nB $end +$var wire 1 a" nCmd2 $end +$var wire 1 b" subtract $end +$scope module mux0 $end +$var wire 1 c" S $end +$var wire 1 Z" in0 $end +$var wire 1 `" in1 $end +$var wire 1 d" nS $end +$var wire 1 e" out0 $end +$var wire 1 f" out1 $end +$var wire 1 [" outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin addbits[8] $end +$scope module attempt $end +$var wire 1 g" A $end +$var wire 1 h" AandB $end +$var wire 1 i" AddSubSLTSum $end +$var wire 1 j" AxorB $end +$var wire 1 k" B $end +$var wire 1 l" BornB $end +$var wire 1 m" CINandAxorB $end +$var wire 3 n" Command [2:0] $end +$var wire 1 o" carryin $end +$var wire 1 p" carryout $end +$var wire 1 q" nB $end +$var wire 1 r" nCmd2 $end +$var wire 1 s" subtract $end +$scope module mux0 $end +$var wire 1 t" S $end +$var wire 1 k" in0 $end +$var wire 1 q" in1 $end +$var wire 1 u" nS $end +$var wire 1 v" out0 $end +$var wire 1 w" out1 $end +$var wire 1 l" outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin addbits[9] $end +$scope module attempt $end +$var wire 1 x" A $end +$var wire 1 y" AandB $end +$var wire 1 z" AddSubSLTSum $end +$var wire 1 {" AxorB $end +$var wire 1 |" B $end +$var wire 1 }" BornB $end +$var wire 1 ~" CINandAxorB $end +$var wire 3 !# Command [2:0] $end +$var wire 1 "# carryin $end +$var wire 1 ## carryout $end +$var wire 1 $# nB $end +$var wire 1 %# nCmd2 $end +$var wire 1 &# subtract $end +$scope module mux0 $end +$var wire 1 '# S $end +$var wire 1 |" in0 $end +$var wire 1 $# in1 $end +$var wire 1 (# nS $end +$var wire 1 )# out0 $end +$var wire 1 *# out1 $end +$var wire 1 }" outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin addbits[10] $end +$scope module attempt $end +$var wire 1 +# A $end +$var wire 1 ,# AandB $end +$var wire 1 -# AddSubSLTSum $end +$var wire 1 .# AxorB $end +$var wire 1 /# B $end +$var wire 1 0# BornB $end +$var wire 1 1# CINandAxorB $end +$var wire 3 2# Command [2:0] $end +$var wire 1 3# carryin $end +$var wire 1 4# carryout $end +$var wire 1 5# nB $end +$var wire 1 6# nCmd2 $end +$var wire 1 7# subtract $end +$scope module mux0 $end +$var wire 1 8# S $end +$var wire 1 /# in0 $end +$var wire 1 5# in1 $end +$var wire 1 9# nS $end +$var wire 1 :# out0 $end +$var wire 1 ;# out1 $end +$var wire 1 0# outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin addbits[11] $end +$scope module attempt $end +$var wire 1 <# A $end +$var wire 1 =# AandB $end +$var wire 1 ># AddSubSLTSum $end +$var wire 1 ?# AxorB $end +$var wire 1 @# B $end +$var wire 1 A# BornB $end +$var wire 1 B# CINandAxorB $end +$var wire 3 C# Command [2:0] $end +$var wire 1 D# carryin $end +$var wire 1 E# carryout $end +$var wire 1 F# nB $end +$var wire 1 G# nCmd2 $end +$var wire 1 H# subtract $end +$scope module mux0 $end +$var wire 1 I# S $end +$var wire 1 @# in0 $end +$var wire 1 F# in1 $end +$var wire 1 J# nS $end +$var wire 1 K# out0 $end +$var wire 1 L# out1 $end +$var wire 1 A# outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin addbits[12] $end +$scope module attempt $end +$var wire 1 M# A $end +$var wire 1 N# AandB $end +$var wire 1 O# AddSubSLTSum $end +$var wire 1 P# AxorB $end +$var wire 1 Q# B $end +$var wire 1 R# BornB $end +$var wire 1 S# CINandAxorB $end +$var wire 3 T# Command [2:0] $end +$var wire 1 U# carryin $end +$var wire 1 V# carryout $end +$var wire 1 W# nB $end +$var wire 1 X# nCmd2 $end +$var wire 1 Y# subtract $end +$scope module mux0 $end +$var wire 1 Z# S $end +$var wire 1 Q# in0 $end +$var wire 1 W# in1 $end +$var wire 1 [# nS $end +$var wire 1 \# out0 $end +$var wire 1 ]# out1 $end +$var wire 1 R# outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin addbits[13] $end +$scope module attempt $end +$var wire 1 ^# A $end +$var wire 1 _# AandB $end +$var wire 1 `# AddSubSLTSum $end +$var wire 1 a# AxorB $end +$var wire 1 b# B $end +$var wire 1 c# BornB $end +$var wire 1 d# CINandAxorB $end +$var wire 3 e# Command [2:0] $end +$var wire 1 f# carryin $end +$var wire 1 g# carryout $end +$var wire 1 h# nB $end +$var wire 1 i# nCmd2 $end +$var wire 1 j# subtract $end +$scope module mux0 $end +$var wire 1 k# S $end +$var wire 1 b# in0 $end +$var wire 1 h# in1 $end +$var wire 1 l# nS $end +$var wire 1 m# out0 $end +$var wire 1 n# out1 $end +$var wire 1 c# outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin addbits[14] $end +$scope module attempt $end +$var wire 1 o# A $end +$var wire 1 p# AandB $end +$var wire 1 q# AddSubSLTSum $end +$var wire 1 r# AxorB $end +$var wire 1 s# B $end +$var wire 1 t# BornB $end +$var wire 1 u# CINandAxorB $end +$var wire 3 v# Command [2:0] $end +$var wire 1 w# carryin $end +$var wire 1 x# carryout $end +$var wire 1 y# nB $end +$var wire 1 z# nCmd2 $end +$var wire 1 {# subtract $end +$scope module mux0 $end +$var wire 1 |# S $end +$var wire 1 s# in0 $end +$var wire 1 y# in1 $end +$var wire 1 }# nS $end +$var wire 1 ~# out0 $end +$var wire 1 !$ out1 $end +$var wire 1 t# outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin addbits[15] $end +$scope module attempt $end +$var wire 1 "$ A $end +$var wire 1 #$ AandB $end +$var wire 1 $$ AddSubSLTSum $end +$var wire 1 %$ AxorB $end +$var wire 1 &$ B $end +$var wire 1 '$ BornB $end +$var wire 1 ($ CINandAxorB $end +$var wire 3 )$ Command [2:0] $end +$var wire 1 *$ carryin $end +$var wire 1 +$ carryout $end +$var wire 1 ,$ nB $end +$var wire 1 -$ nCmd2 $end +$var wire 1 .$ subtract $end +$scope module mux0 $end +$var wire 1 /$ S $end +$var wire 1 &$ in0 $end +$var wire 1 ,$ in1 $end +$var wire 1 0$ nS $end +$var wire 1 1$ out0 $end +$var wire 1 2$ out1 $end +$var wire 1 '$ outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin addbits[16] $end +$scope module attempt $end +$var wire 1 3$ A $end +$var wire 1 4$ AandB $end +$var wire 1 5$ AddSubSLTSum $end +$var wire 1 6$ AxorB $end +$var wire 1 7$ B $end +$var wire 1 8$ BornB $end +$var wire 1 9$ CINandAxorB $end +$var wire 3 :$ Command [2:0] $end +$var wire 1 ;$ carryin $end +$var wire 1 <$ carryout $end +$var wire 1 =$ nB $end +$var wire 1 >$ nCmd2 $end +$var wire 1 ?$ subtract $end +$scope module mux0 $end +$var wire 1 @$ S $end +$var wire 1 7$ in0 $end +$var wire 1 =$ in1 $end +$var wire 1 A$ nS $end +$var wire 1 B$ out0 $end +$var wire 1 C$ out1 $end +$var wire 1 8$ outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin addbits[17] $end +$scope module attempt $end +$var wire 1 D$ A $end +$var wire 1 E$ AandB $end +$var wire 1 F$ AddSubSLTSum $end +$var wire 1 G$ AxorB $end +$var wire 1 H$ B $end +$var wire 1 I$ BornB $end +$var wire 1 J$ CINandAxorB $end +$var wire 3 K$ Command [2:0] $end +$var wire 1 L$ carryin $end +$var wire 1 M$ carryout $end +$var wire 1 N$ nB $end +$var wire 1 O$ nCmd2 $end +$var wire 1 P$ subtract $end +$scope module mux0 $end +$var wire 1 Q$ S $end +$var wire 1 H$ in0 $end +$var wire 1 N$ in1 $end +$var wire 1 R$ nS $end +$var wire 1 S$ out0 $end +$var wire 1 T$ out1 $end +$var wire 1 I$ outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin addbits[18] $end +$scope module attempt $end +$var wire 1 U$ A $end +$var wire 1 V$ AandB $end +$var wire 1 W$ AddSubSLTSum $end +$var wire 1 X$ AxorB $end +$var wire 1 Y$ B $end +$var wire 1 Z$ BornB $end +$var wire 1 [$ CINandAxorB $end +$var wire 3 \$ Command [2:0] $end +$var wire 1 ]$ carryin $end +$var wire 1 ^$ carryout $end +$var wire 1 _$ nB $end +$var wire 1 `$ nCmd2 $end +$var wire 1 a$ subtract $end +$scope module mux0 $end +$var wire 1 b$ S $end +$var wire 1 Y$ in0 $end +$var wire 1 _$ in1 $end +$var wire 1 c$ nS $end +$var wire 1 d$ out0 $end +$var wire 1 e$ out1 $end +$var wire 1 Z$ outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin addbits[19] $end +$scope module attempt $end +$var wire 1 f$ A $end +$var wire 1 g$ AandB $end +$var wire 1 h$ AddSubSLTSum $end +$var wire 1 i$ AxorB $end +$var wire 1 j$ B $end +$var wire 1 k$ BornB $end +$var wire 1 l$ CINandAxorB $end +$var wire 3 m$ Command [2:0] $end +$var wire 1 n$ carryin $end +$var wire 1 o$ carryout $end +$var wire 1 p$ nB $end +$var wire 1 q$ nCmd2 $end +$var wire 1 r$ subtract $end +$scope module mux0 $end +$var wire 1 s$ S $end +$var wire 1 j$ in0 $end +$var wire 1 p$ in1 $end +$var wire 1 t$ nS $end +$var wire 1 u$ out0 $end +$var wire 1 v$ out1 $end +$var wire 1 k$ outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin addbits[20] $end +$scope module attempt $end +$var wire 1 w$ A $end +$var wire 1 x$ AandB $end +$var wire 1 y$ AddSubSLTSum $end +$var wire 1 z$ AxorB $end +$var wire 1 {$ B $end +$var wire 1 |$ BornB $end +$var wire 1 }$ CINandAxorB $end +$var wire 3 ~$ Command [2:0] $end +$var wire 1 !% carryin $end +$var wire 1 "% carryout $end +$var wire 1 #% nB $end +$var wire 1 $% nCmd2 $end +$var wire 1 %% subtract $end +$scope module mux0 $end +$var wire 1 &% S $end +$var wire 1 {$ in0 $end +$var wire 1 #% in1 $end +$var wire 1 '% nS $end +$var wire 1 (% out0 $end +$var wire 1 )% out1 $end +$var wire 1 |$ outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin addbits[21] $end +$scope module attempt $end +$var wire 1 *% A $end +$var wire 1 +% AandB $end +$var wire 1 ,% AddSubSLTSum $end +$var wire 1 -% AxorB $end +$var wire 1 .% B $end +$var wire 1 /% BornB $end +$var wire 1 0% CINandAxorB $end +$var wire 3 1% Command [2:0] $end +$var wire 1 2% carryin $end +$var wire 1 3% carryout $end +$var wire 1 4% nB $end +$var wire 1 5% nCmd2 $end +$var wire 1 6% subtract $end +$scope module mux0 $end +$var wire 1 7% S $end +$var wire 1 .% in0 $end +$var wire 1 4% in1 $end +$var wire 1 8% nS $end +$var wire 1 9% out0 $end +$var wire 1 :% out1 $end +$var wire 1 /% outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin addbits[22] $end +$scope module attempt $end +$var wire 1 ;% A $end +$var wire 1 <% AandB $end +$var wire 1 =% AddSubSLTSum $end +$var wire 1 >% AxorB $end +$var wire 1 ?% B $end +$var wire 1 @% BornB $end +$var wire 1 A% CINandAxorB $end +$var wire 3 B% Command [2:0] $end +$var wire 1 C% carryin $end +$var wire 1 D% carryout $end +$var wire 1 E% nB $end +$var wire 1 F% nCmd2 $end +$var wire 1 G% subtract $end +$scope module mux0 $end +$var wire 1 H% S $end +$var wire 1 ?% in0 $end +$var wire 1 E% in1 $end +$var wire 1 I% nS $end +$var wire 1 J% out0 $end +$var wire 1 K% out1 $end +$var wire 1 @% outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin addbits[23] $end +$scope module attempt $end +$var wire 1 L% A $end +$var wire 1 M% AandB $end +$var wire 1 N% AddSubSLTSum $end +$var wire 1 O% AxorB $end +$var wire 1 P% B $end +$var wire 1 Q% BornB $end +$var wire 1 R% CINandAxorB $end +$var wire 3 S% Command [2:0] $end +$var wire 1 T% carryin $end +$var wire 1 U% carryout $end +$var wire 1 V% nB $end +$var wire 1 W% nCmd2 $end +$var wire 1 X% subtract $end +$scope module mux0 $end +$var wire 1 Y% S $end +$var wire 1 P% in0 $end +$var wire 1 V% in1 $end +$var wire 1 Z% nS $end +$var wire 1 [% out0 $end +$var wire 1 \% out1 $end +$var wire 1 Q% outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin addbits[24] $end +$scope module attempt $end +$var wire 1 ]% A $end +$var wire 1 ^% AandB $end +$var wire 1 _% AddSubSLTSum $end +$var wire 1 `% AxorB $end +$var wire 1 a% B $end +$var wire 1 b% BornB $end +$var wire 1 c% CINandAxorB $end +$var wire 3 d% Command [2:0] $end +$var wire 1 e% carryin $end +$var wire 1 f% carryout $end +$var wire 1 g% nB $end +$var wire 1 h% nCmd2 $end +$var wire 1 i% subtract $end +$scope module mux0 $end +$var wire 1 j% S $end +$var wire 1 a% in0 $end +$var wire 1 g% in1 $end +$var wire 1 k% nS $end +$var wire 1 l% out0 $end +$var wire 1 m% out1 $end +$var wire 1 b% outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin addbits[25] $end +$scope module attempt $end +$var wire 1 n% A $end +$var wire 1 o% AandB $end +$var wire 1 p% AddSubSLTSum $end +$var wire 1 q% AxorB $end +$var wire 1 r% B $end +$var wire 1 s% BornB $end +$var wire 1 t% CINandAxorB $end +$var wire 3 u% Command [2:0] $end +$var wire 1 v% carryin $end +$var wire 1 w% carryout $end +$var wire 1 x% nB $end +$var wire 1 y% nCmd2 $end +$var wire 1 z% subtract $end +$scope module mux0 $end +$var wire 1 {% S $end +$var wire 1 r% in0 $end +$var wire 1 x% in1 $end +$var wire 1 |% nS $end +$var wire 1 }% out0 $end +$var wire 1 ~% out1 $end +$var wire 1 s% outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin addbits[26] $end +$scope module attempt $end +$var wire 1 !& A $end +$var wire 1 "& AandB $end +$var wire 1 #& AddSubSLTSum $end +$var wire 1 $& AxorB $end +$var wire 1 %& B $end +$var wire 1 && BornB $end +$var wire 1 '& CINandAxorB $end +$var wire 3 (& Command [2:0] $end +$var wire 1 )& carryin $end +$var wire 1 *& carryout $end +$var wire 1 +& nB $end +$var wire 1 ,& nCmd2 $end +$var wire 1 -& subtract $end +$scope module mux0 $end +$var wire 1 .& S $end +$var wire 1 %& in0 $end +$var wire 1 +& in1 $end +$var wire 1 /& nS $end +$var wire 1 0& out0 $end +$var wire 1 1& out1 $end +$var wire 1 && outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin addbits[27] $end +$scope module attempt $end +$var wire 1 2& A $end +$var wire 1 3& AandB $end +$var wire 1 4& AddSubSLTSum $end +$var wire 1 5& AxorB $end +$var wire 1 6& B $end +$var wire 1 7& BornB $end +$var wire 1 8& CINandAxorB $end +$var wire 3 9& Command [2:0] $end +$var wire 1 :& carryin $end +$var wire 1 ;& carryout $end +$var wire 1 <& nB $end +$var wire 1 =& nCmd2 $end +$var wire 1 >& subtract $end +$scope module mux0 $end +$var wire 1 ?& S $end +$var wire 1 6& in0 $end +$var wire 1 <& in1 $end +$var wire 1 @& nS $end +$var wire 1 A& out0 $end +$var wire 1 B& out1 $end +$var wire 1 7& outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin addbits[28] $end +$scope module attempt $end +$var wire 1 C& A $end +$var wire 1 D& AandB $end +$var wire 1 E& AddSubSLTSum $end +$var wire 1 F& AxorB $end +$var wire 1 G& B $end +$var wire 1 H& BornB $end +$var wire 1 I& CINandAxorB $end +$var wire 3 J& Command [2:0] $end +$var wire 1 K& carryin $end +$var wire 1 L& carryout $end +$var wire 1 M& nB $end +$var wire 1 N& nCmd2 $end +$var wire 1 O& subtract $end +$scope module mux0 $end +$var wire 1 P& S $end +$var wire 1 G& in0 $end +$var wire 1 M& in1 $end +$var wire 1 Q& nS $end +$var wire 1 R& out0 $end +$var wire 1 S& out1 $end +$var wire 1 H& outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin addbits[29] $end +$scope module attempt $end +$var wire 1 T& A $end +$var wire 1 U& AandB $end +$var wire 1 V& AddSubSLTSum $end +$var wire 1 W& AxorB $end +$var wire 1 X& B $end +$var wire 1 Y& BornB $end +$var wire 1 Z& CINandAxorB $end +$var wire 3 [& Command [2:0] $end +$var wire 1 \& carryin $end +$var wire 1 ]& carryout $end +$var wire 1 ^& nB $end +$var wire 1 _& nCmd2 $end +$var wire 1 `& subtract $end +$scope module mux0 $end +$var wire 1 a& S $end +$var wire 1 X& in0 $end +$var wire 1 ^& in1 $end +$var wire 1 b& nS $end +$var wire 1 c& out0 $end +$var wire 1 d& out1 $end +$var wire 1 Y& outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin addbits[30] $end +$scope module attempt $end +$var wire 1 e& A $end +$var wire 1 f& AandB $end +$var wire 1 g& AddSubSLTSum $end +$var wire 1 h& AxorB $end +$var wire 1 i& B $end +$var wire 1 j& BornB $end +$var wire 1 k& CINandAxorB $end +$var wire 3 l& Command [2:0] $end +$var wire 1 m& carryin $end +$var wire 1 n& carryout $end +$var wire 1 o& nB $end +$var wire 1 p& nCmd2 $end +$var wire 1 q& subtract $end +$scope module mux0 $end +$var wire 1 r& S $end +$var wire 1 i& in0 $end +$var wire 1 o& in1 $end +$var wire 1 s& nS $end +$var wire 1 t& out0 $end +$var wire 1 u& out1 $end +$var wire 1 j& outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin addbits[31] $end +$scope module attempt $end +$var wire 1 v& A $end +$var wire 1 w& AandB $end +$var wire 1 x& AddSubSLTSum $end +$var wire 1 y& AxorB $end +$var wire 1 z& B $end +$var wire 1 {& BornB $end +$var wire 1 |& CINandAxorB $end +$var wire 3 }& Command [2:0] $end +$var wire 1 ~& carryin $end +$var wire 1 !' carryout $end +$var wire 1 "' nB $end +$var wire 1 #' nCmd2 $end +$var wire 1 $' subtract $end +$scope module mux0 $end +$var wire 1 %' S $end +$var wire 1 z& in0 $end +$var wire 1 "' in1 $end +$var wire 1 &' nS $end +$var wire 1 '' out0 $end +$var wire 1 (' out1 $end +$var wire 1 {& outfinal $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope module trial1 $end +$var wire 32 )' A [31:0] $end +$var wire 32 *' AndNandOut [31:0] $end +$var wire 32 +' B [31:0] $end +$var wire 3 ,' Command [2:0] $end +$scope module attempt2 $end +$var wire 1 -' A $end +$var wire 1 .' AandB $end +$var wire 1 /' AnandB $end +$var wire 1 0' AndNandOut $end +$var wire 1 1' B $end +$var wire 3 2' Command [2:0] $end +$scope module potato $end +$var wire 1 3' S $end +$var wire 1 .' in0 $end +$var wire 1 /' in1 $end +$var wire 1 4' nS $end +$var wire 1 5' out0 $end +$var wire 1 6' out1 $end +$var wire 1 0' outfinal $end +$upscope $end +$upscope $end +$scope begin andbits[1] $end +$scope module attempt $end +$var wire 1 7' A $end +$var wire 1 8' AandB $end +$var wire 1 9' AnandB $end +$var wire 1 :' AndNandOut $end +$var wire 1 ;' B $end +$var wire 3 <' Command [2:0] $end +$scope module potato $end +$var wire 1 =' S $end +$var wire 1 8' in0 $end +$var wire 1 9' in1 $end +$var wire 1 >' nS $end +$var wire 1 ?' out0 $end +$var wire 1 @' out1 $end +$var wire 1 :' outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin andbits[2] $end +$scope module attempt $end +$var wire 1 A' A $end +$var wire 1 B' AandB $end +$var wire 1 C' AnandB $end +$var wire 1 D' AndNandOut $end +$var wire 1 E' B $end +$var wire 3 F' Command [2:0] $end +$scope module potato $end +$var wire 1 G' S $end +$var wire 1 B' in0 $end +$var wire 1 C' in1 $end +$var wire 1 H' nS $end +$var wire 1 I' out0 $end +$var wire 1 J' out1 $end +$var wire 1 D' outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin andbits[3] $end +$scope module attempt $end +$var wire 1 K' A $end +$var wire 1 L' AandB $end +$var wire 1 M' AnandB $end +$var wire 1 N' AndNandOut $end +$var wire 1 O' B $end +$var wire 3 P' Command [2:0] $end +$scope module potato $end +$var wire 1 Q' S $end +$var wire 1 L' in0 $end +$var wire 1 M' in1 $end +$var wire 1 R' nS $end +$var wire 1 S' out0 $end +$var wire 1 T' out1 $end +$var wire 1 N' outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin andbits[4] $end +$scope module attempt $end +$var wire 1 U' A $end +$var wire 1 V' AandB $end +$var wire 1 W' AnandB $end +$var wire 1 X' AndNandOut $end +$var wire 1 Y' B $end +$var wire 3 Z' Command [2:0] $end +$scope module potato $end +$var wire 1 [' S $end +$var wire 1 V' in0 $end +$var wire 1 W' in1 $end +$var wire 1 \' nS $end +$var wire 1 ]' out0 $end +$var wire 1 ^' out1 $end +$var wire 1 X' outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin andbits[5] $end +$scope module attempt $end +$var wire 1 _' A $end +$var wire 1 `' AandB $end +$var wire 1 a' AnandB $end +$var wire 1 b' AndNandOut $end +$var wire 1 c' B $end +$var wire 3 d' Command [2:0] $end +$scope module potato $end +$var wire 1 e' S $end +$var wire 1 `' in0 $end +$var wire 1 a' in1 $end +$var wire 1 f' nS $end +$var wire 1 g' out0 $end +$var wire 1 h' out1 $end +$var wire 1 b' outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin andbits[6] $end +$scope module attempt $end +$var wire 1 i' A $end +$var wire 1 j' AandB $end +$var wire 1 k' AnandB $end +$var wire 1 l' AndNandOut $end +$var wire 1 m' B $end +$var wire 3 n' Command [2:0] $end +$scope module potato $end +$var wire 1 o' S $end +$var wire 1 j' in0 $end +$var wire 1 k' in1 $end +$var wire 1 p' nS $end +$var wire 1 q' out0 $end +$var wire 1 r' out1 $end +$var wire 1 l' outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin andbits[7] $end +$scope module attempt $end +$var wire 1 s' A $end +$var wire 1 t' AandB $end +$var wire 1 u' AnandB $end +$var wire 1 v' AndNandOut $end +$var wire 1 w' B $end +$var wire 3 x' Command [2:0] $end +$scope module potato $end +$var wire 1 y' S $end +$var wire 1 t' in0 $end +$var wire 1 u' in1 $end +$var wire 1 z' nS $end +$var wire 1 {' out0 $end +$var wire 1 |' out1 $end +$var wire 1 v' outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin andbits[8] $end +$scope module attempt $end +$var wire 1 }' A $end +$var wire 1 ~' AandB $end +$var wire 1 !( AnandB $end +$var wire 1 "( AndNandOut $end +$var wire 1 #( B $end +$var wire 3 $( Command [2:0] $end +$scope module potato $end +$var wire 1 %( S $end +$var wire 1 ~' in0 $end +$var wire 1 !( in1 $end +$var wire 1 &( nS $end +$var wire 1 '( out0 $end +$var wire 1 (( out1 $end +$var wire 1 "( outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin andbits[9] $end +$scope module attempt $end +$var wire 1 )( A $end +$var wire 1 *( AandB $end +$var wire 1 +( AnandB $end +$var wire 1 ,( AndNandOut $end +$var wire 1 -( B $end +$var wire 3 .( Command [2:0] $end +$scope module potato $end +$var wire 1 /( S $end +$var wire 1 *( in0 $end +$var wire 1 +( in1 $end +$var wire 1 0( nS $end +$var wire 1 1( out0 $end +$var wire 1 2( out1 $end +$var wire 1 ,( outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin andbits[10] $end +$scope module attempt $end +$var wire 1 3( A $end +$var wire 1 4( AandB $end +$var wire 1 5( AnandB $end +$var wire 1 6( AndNandOut $end +$var wire 1 7( B $end +$var wire 3 8( Command [2:0] $end +$scope module potato $end +$var wire 1 9( S $end +$var wire 1 4( in0 $end +$var wire 1 5( in1 $end +$var wire 1 :( nS $end +$var wire 1 ;( out0 $end +$var wire 1 <( out1 $end +$var wire 1 6( outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin andbits[11] $end +$scope module attempt $end +$var wire 1 =( A $end +$var wire 1 >( AandB $end +$var wire 1 ?( AnandB $end +$var wire 1 @( AndNandOut $end +$var wire 1 A( B $end +$var wire 3 B( Command [2:0] $end +$scope module potato $end +$var wire 1 C( S $end +$var wire 1 >( in0 $end +$var wire 1 ?( in1 $end +$var wire 1 D( nS $end +$var wire 1 E( out0 $end +$var wire 1 F( out1 $end +$var wire 1 @( outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin andbits[12] $end +$scope module attempt $end +$var wire 1 G( A $end +$var wire 1 H( AandB $end +$var wire 1 I( AnandB $end +$var wire 1 J( AndNandOut $end +$var wire 1 K( B $end +$var wire 3 L( Command [2:0] $end +$scope module potato $end +$var wire 1 M( S $end +$var wire 1 H( in0 $end +$var wire 1 I( in1 $end +$var wire 1 N( nS $end +$var wire 1 O( out0 $end +$var wire 1 P( out1 $end +$var wire 1 J( outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin andbits[13] $end +$scope module attempt $end +$var wire 1 Q( A $end +$var wire 1 R( AandB $end +$var wire 1 S( AnandB $end +$var wire 1 T( AndNandOut $end +$var wire 1 U( B $end +$var wire 3 V( Command [2:0] $end +$scope module potato $end +$var wire 1 W( S $end +$var wire 1 R( in0 $end +$var wire 1 S( in1 $end +$var wire 1 X( nS $end +$var wire 1 Y( out0 $end +$var wire 1 Z( out1 $end +$var wire 1 T( outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin andbits[14] $end +$scope module attempt $end +$var wire 1 [( A $end +$var wire 1 \( AandB $end +$var wire 1 ]( AnandB $end +$var wire 1 ^( AndNandOut $end +$var wire 1 _( B $end +$var wire 3 `( Command [2:0] $end +$scope module potato $end +$var wire 1 a( S $end +$var wire 1 \( in0 $end +$var wire 1 ]( in1 $end +$var wire 1 b( nS $end +$var wire 1 c( out0 $end +$var wire 1 d( out1 $end +$var wire 1 ^( outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin andbits[15] $end +$scope module attempt $end +$var wire 1 e( A $end +$var wire 1 f( AandB $end +$var wire 1 g( AnandB $end +$var wire 1 h( AndNandOut $end +$var wire 1 i( B $end +$var wire 3 j( Command [2:0] $end +$scope module potato $end +$var wire 1 k( S $end +$var wire 1 f( in0 $end +$var wire 1 g( in1 $end +$var wire 1 l( nS $end +$var wire 1 m( out0 $end +$var wire 1 n( out1 $end +$var wire 1 h( outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin andbits[16] $end +$scope module attempt $end +$var wire 1 o( A $end +$var wire 1 p( AandB $end +$var wire 1 q( AnandB $end +$var wire 1 r( AndNandOut $end +$var wire 1 s( B $end +$var wire 3 t( Command [2:0] $end +$scope module potato $end +$var wire 1 u( S $end +$var wire 1 p( in0 $end +$var wire 1 q( in1 $end +$var wire 1 v( nS $end +$var wire 1 w( out0 $end +$var wire 1 x( out1 $end +$var wire 1 r( outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin andbits[17] $end +$scope module attempt $end +$var wire 1 y( A $end +$var wire 1 z( AandB $end +$var wire 1 {( AnandB $end +$var wire 1 |( AndNandOut $end +$var wire 1 }( B $end +$var wire 3 ~( Command [2:0] $end +$scope module potato $end +$var wire 1 !) S $end +$var wire 1 z( in0 $end +$var wire 1 {( in1 $end +$var wire 1 ") nS $end +$var wire 1 #) out0 $end +$var wire 1 $) out1 $end +$var wire 1 |( outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin andbits[18] $end +$scope module attempt $end +$var wire 1 %) A $end +$var wire 1 &) AandB $end +$var wire 1 ') AnandB $end +$var wire 1 () AndNandOut $end +$var wire 1 )) B $end +$var wire 3 *) Command [2:0] $end +$scope module potato $end +$var wire 1 +) S $end +$var wire 1 &) in0 $end +$var wire 1 ') in1 $end +$var wire 1 ,) nS $end +$var wire 1 -) out0 $end +$var wire 1 .) out1 $end +$var wire 1 () outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin andbits[19] $end +$scope module attempt $end +$var wire 1 /) A $end +$var wire 1 0) AandB $end +$var wire 1 1) AnandB $end +$var wire 1 2) AndNandOut $end +$var wire 1 3) B $end +$var wire 3 4) Command [2:0] $end +$scope module potato $end +$var wire 1 5) S $end +$var wire 1 0) in0 $end +$var wire 1 1) in1 $end +$var wire 1 6) nS $end +$var wire 1 7) out0 $end +$var wire 1 8) out1 $end +$var wire 1 2) outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin andbits[20] $end +$scope module attempt $end +$var wire 1 9) A $end +$var wire 1 :) AandB $end +$var wire 1 ;) AnandB $end +$var wire 1 <) AndNandOut $end +$var wire 1 =) B $end +$var wire 3 >) Command [2:0] $end +$scope module potato $end +$var wire 1 ?) S $end +$var wire 1 :) in0 $end +$var wire 1 ;) in1 $end +$var wire 1 @) nS $end +$var wire 1 A) out0 $end +$var wire 1 B) out1 $end +$var wire 1 <) outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin andbits[21] $end +$scope module attempt $end +$var wire 1 C) A $end +$var wire 1 D) AandB $end +$var wire 1 E) AnandB $end +$var wire 1 F) AndNandOut $end +$var wire 1 G) B $end +$var wire 3 H) Command [2:0] $end +$scope module potato $end +$var wire 1 I) S $end +$var wire 1 D) in0 $end +$var wire 1 E) in1 $end +$var wire 1 J) nS $end +$var wire 1 K) out0 $end +$var wire 1 L) out1 $end +$var wire 1 F) outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin andbits[22] $end +$scope module attempt $end +$var wire 1 M) A $end +$var wire 1 N) AandB $end +$var wire 1 O) AnandB $end +$var wire 1 P) AndNandOut $end +$var wire 1 Q) B $end +$var wire 3 R) Command [2:0] $end +$scope module potato $end +$var wire 1 S) S $end +$var wire 1 N) in0 $end +$var wire 1 O) in1 $end +$var wire 1 T) nS $end +$var wire 1 U) out0 $end +$var wire 1 V) out1 $end +$var wire 1 P) outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin andbits[23] $end +$scope module attempt $end +$var wire 1 W) A $end +$var wire 1 X) AandB $end +$var wire 1 Y) AnandB $end +$var wire 1 Z) AndNandOut $end +$var wire 1 [) B $end +$var wire 3 \) Command [2:0] $end +$scope module potato $end +$var wire 1 ]) S $end +$var wire 1 X) in0 $end +$var wire 1 Y) in1 $end +$var wire 1 ^) nS $end +$var wire 1 _) out0 $end +$var wire 1 `) out1 $end +$var wire 1 Z) outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin andbits[24] $end +$scope module attempt $end +$var wire 1 a) A $end +$var wire 1 b) AandB $end +$var wire 1 c) AnandB $end +$var wire 1 d) AndNandOut $end +$var wire 1 e) B $end +$var wire 3 f) Command [2:0] $end +$scope module potato $end +$var wire 1 g) S $end +$var wire 1 b) in0 $end +$var wire 1 c) in1 $end +$var wire 1 h) nS $end +$var wire 1 i) out0 $end +$var wire 1 j) out1 $end +$var wire 1 d) outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin andbits[25] $end +$scope module attempt $end +$var wire 1 k) A $end +$var wire 1 l) AandB $end +$var wire 1 m) AnandB $end +$var wire 1 n) AndNandOut $end +$var wire 1 o) B $end +$var wire 3 p) Command [2:0] $end +$scope module potato $end +$var wire 1 q) S $end +$var wire 1 l) in0 $end +$var wire 1 m) in1 $end +$var wire 1 r) nS $end +$var wire 1 s) out0 $end +$var wire 1 t) out1 $end +$var wire 1 n) outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin andbits[26] $end +$scope module attempt $end +$var wire 1 u) A $end +$var wire 1 v) AandB $end +$var wire 1 w) AnandB $end +$var wire 1 x) AndNandOut $end +$var wire 1 y) B $end +$var wire 3 z) Command [2:0] $end +$scope module potato $end +$var wire 1 {) S $end +$var wire 1 v) in0 $end +$var wire 1 w) in1 $end +$var wire 1 |) nS $end +$var wire 1 }) out0 $end +$var wire 1 ~) out1 $end +$var wire 1 x) outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin andbits[27] $end +$scope module attempt $end +$var wire 1 !* A $end +$var wire 1 "* AandB $end +$var wire 1 #* AnandB $end +$var wire 1 $* AndNandOut $end +$var wire 1 %* B $end +$var wire 3 &* Command [2:0] $end +$scope module potato $end +$var wire 1 '* S $end +$var wire 1 "* in0 $end +$var wire 1 #* in1 $end +$var wire 1 (* nS $end +$var wire 1 )* out0 $end +$var wire 1 ** out1 $end +$var wire 1 $* outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin andbits[28] $end +$scope module attempt $end +$var wire 1 +* A $end +$var wire 1 ,* AandB $end +$var wire 1 -* AnandB $end +$var wire 1 .* AndNandOut $end +$var wire 1 /* B $end +$var wire 3 0* Command [2:0] $end +$scope module potato $end +$var wire 1 1* S $end +$var wire 1 ,* in0 $end +$var wire 1 -* in1 $end +$var wire 1 2* nS $end +$var wire 1 3* out0 $end +$var wire 1 4* out1 $end +$var wire 1 .* outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin andbits[29] $end +$scope module attempt $end +$var wire 1 5* A $end +$var wire 1 6* AandB $end +$var wire 1 7* AnandB $end +$var wire 1 8* AndNandOut $end +$var wire 1 9* B $end +$var wire 3 :* Command [2:0] $end +$scope module potato $end +$var wire 1 ;* S $end +$var wire 1 6* in0 $end +$var wire 1 7* in1 $end +$var wire 1 <* nS $end +$var wire 1 =* out0 $end +$var wire 1 >* out1 $end +$var wire 1 8* outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin andbits[30] $end +$scope module attempt $end +$var wire 1 ?* A $end +$var wire 1 @* AandB $end +$var wire 1 A* AnandB $end +$var wire 1 B* AndNandOut $end +$var wire 1 C* B $end +$var wire 3 D* Command [2:0] $end +$scope module potato $end +$var wire 1 E* S $end +$var wire 1 @* in0 $end +$var wire 1 A* in1 $end +$var wire 1 F* nS $end +$var wire 1 G* out0 $end +$var wire 1 H* out1 $end +$var wire 1 B* outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin andbits[31] $end +$scope module attempt $end +$var wire 1 I* A $end +$var wire 1 J* AandB $end +$var wire 1 K* AnandB $end +$var wire 1 L* AndNandOut $end +$var wire 1 M* B $end +$var wire 3 N* Command [2:0] $end +$scope module potato $end +$var wire 1 O* S $end +$var wire 1 J* in0 $end +$var wire 1 K* in1 $end +$var wire 1 P* nS $end +$var wire 1 Q* out0 $end +$var wire 1 R* out1 $end +$var wire 1 L* outfinal $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope module trial2 $end +$var wire 32 S* A [31:0] $end +$var wire 32 T* B [31:0] $end +$var wire 3 U* Command [2:0] $end +$var wire 32 V* OrNorXorOut [31:0] $end +$scope module attempt2 $end +$var wire 1 W* A $end +$var wire 1 X* AnandB $end +$var wire 1 Y* AnorB $end +$var wire 1 Z* AorB $end +$var wire 1 [* AxorB $end +$var wire 1 \* B $end +$var wire 3 ]* Command [2:0] $end +$var wire 1 ^* OrNorXorOut $end +$var wire 1 _* XorNor $end +$var wire 1 `* nXor $end +$scope module mux0 $end +$var wire 1 a* S $end +$var wire 1 [* in0 $end +$var wire 1 Y* in1 $end +$var wire 1 b* nS $end +$var wire 1 c* out0 $end +$var wire 1 d* out1 $end +$var wire 1 _* outfinal $end +$upscope $end +$scope module mux1 $end +$var wire 1 e* S $end +$var wire 1 _* in0 $end +$var wire 1 Z* in1 $end +$var wire 1 f* nS $end +$var wire 1 g* out0 $end +$var wire 1 h* out1 $end +$var wire 1 ^* outfinal $end +$upscope $end +$upscope $end +$scope begin orbits[1] $end +$scope module attempt $end +$var wire 1 i* A $end +$var wire 1 j* AnandB $end +$var wire 1 k* AnorB $end +$var wire 1 l* AorB $end +$var wire 1 m* AxorB $end +$var wire 1 n* B $end +$var wire 3 o* Command [2:0] $end +$var wire 1 p* OrNorXorOut $end +$var wire 1 q* XorNor $end +$var wire 1 r* nXor $end +$scope module mux0 $end +$var wire 1 s* S $end +$var wire 1 m* in0 $end +$var wire 1 k* in1 $end +$var wire 1 t* nS $end +$var wire 1 u* out0 $end +$var wire 1 v* out1 $end +$var wire 1 q* outfinal $end +$upscope $end +$scope module mux1 $end +$var wire 1 w* S $end +$var wire 1 q* in0 $end +$var wire 1 l* in1 $end +$var wire 1 x* nS $end +$var wire 1 y* out0 $end +$var wire 1 z* out1 $end +$var wire 1 p* outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin orbits[2] $end +$scope module attempt $end +$var wire 1 {* A $end +$var wire 1 |* AnandB $end +$var wire 1 }* AnorB $end +$var wire 1 ~* AorB $end +$var wire 1 !+ AxorB $end +$var wire 1 "+ B $end +$var wire 3 #+ Command [2:0] $end +$var wire 1 $+ OrNorXorOut $end +$var wire 1 %+ XorNor $end +$var wire 1 &+ nXor $end +$scope module mux0 $end +$var wire 1 '+ S $end +$var wire 1 !+ in0 $end +$var wire 1 }* in1 $end +$var wire 1 (+ nS $end +$var wire 1 )+ out0 $end +$var wire 1 *+ out1 $end +$var wire 1 %+ outfinal $end +$upscope $end +$scope module mux1 $end +$var wire 1 ++ S $end +$var wire 1 %+ in0 $end +$var wire 1 ~* in1 $end +$var wire 1 ,+ nS $end +$var wire 1 -+ out0 $end +$var wire 1 .+ out1 $end +$var wire 1 $+ outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin orbits[3] $end +$scope module attempt $end +$var wire 1 /+ A $end +$var wire 1 0+ AnandB $end +$var wire 1 1+ AnorB $end +$var wire 1 2+ AorB $end +$var wire 1 3+ AxorB $end +$var wire 1 4+ B $end +$var wire 3 5+ Command [2:0] $end +$var wire 1 6+ OrNorXorOut $end +$var wire 1 7+ XorNor $end +$var wire 1 8+ nXor $end +$scope module mux0 $end +$var wire 1 9+ S $end +$var wire 1 3+ in0 $end +$var wire 1 1+ in1 $end +$var wire 1 :+ nS $end +$var wire 1 ;+ out0 $end +$var wire 1 <+ out1 $end +$var wire 1 7+ outfinal $end +$upscope $end +$scope module mux1 $end +$var wire 1 =+ S $end +$var wire 1 7+ in0 $end +$var wire 1 2+ in1 $end +$var wire 1 >+ nS $end +$var wire 1 ?+ out0 $end +$var wire 1 @+ out1 $end +$var wire 1 6+ outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin orbits[4] $end +$scope module attempt $end +$var wire 1 A+ A $end +$var wire 1 B+ AnandB $end +$var wire 1 C+ AnorB $end +$var wire 1 D+ AorB $end +$var wire 1 E+ AxorB $end +$var wire 1 F+ B $end +$var wire 3 G+ Command [2:0] $end +$var wire 1 H+ OrNorXorOut $end +$var wire 1 I+ XorNor $end +$var wire 1 J+ nXor $end +$scope module mux0 $end +$var wire 1 K+ S $end +$var wire 1 E+ in0 $end +$var wire 1 C+ in1 $end +$var wire 1 L+ nS $end +$var wire 1 M+ out0 $end +$var wire 1 N+ out1 $end +$var wire 1 I+ outfinal $end +$upscope $end +$scope module mux1 $end +$var wire 1 O+ S $end +$var wire 1 I+ in0 $end +$var wire 1 D+ in1 $end +$var wire 1 P+ nS $end +$var wire 1 Q+ out0 $end +$var wire 1 R+ out1 $end +$var wire 1 H+ outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin orbits[5] $end +$scope module attempt $end +$var wire 1 S+ A $end +$var wire 1 T+ AnandB $end +$var wire 1 U+ AnorB $end +$var wire 1 V+ AorB $end +$var wire 1 W+ AxorB $end +$var wire 1 X+ B $end +$var wire 3 Y+ Command [2:0] $end +$var wire 1 Z+ OrNorXorOut $end +$var wire 1 [+ XorNor $end +$var wire 1 \+ nXor $end +$scope module mux0 $end +$var wire 1 ]+ S $end +$var wire 1 W+ in0 $end +$var wire 1 U+ in1 $end +$var wire 1 ^+ nS $end +$var wire 1 _+ out0 $end +$var wire 1 `+ out1 $end +$var wire 1 [+ outfinal $end +$upscope $end +$scope module mux1 $end +$var wire 1 a+ S $end +$var wire 1 [+ in0 $end +$var wire 1 V+ in1 $end +$var wire 1 b+ nS $end +$var wire 1 c+ out0 $end +$var wire 1 d+ out1 $end +$var wire 1 Z+ outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin orbits[6] $end +$scope module attempt $end +$var wire 1 e+ A $end +$var wire 1 f+ AnandB $end +$var wire 1 g+ AnorB $end +$var wire 1 h+ AorB $end +$var wire 1 i+ AxorB $end +$var wire 1 j+ B $end +$var wire 3 k+ Command [2:0] $end +$var wire 1 l+ OrNorXorOut $end +$var wire 1 m+ XorNor $end +$var wire 1 n+ nXor $end +$scope module mux0 $end +$var wire 1 o+ S $end +$var wire 1 i+ in0 $end +$var wire 1 g+ in1 $end +$var wire 1 p+ nS $end +$var wire 1 q+ out0 $end +$var wire 1 r+ out1 $end +$var wire 1 m+ outfinal $end +$upscope $end +$scope module mux1 $end +$var wire 1 s+ S $end +$var wire 1 m+ in0 $end +$var wire 1 h+ in1 $end +$var wire 1 t+ nS $end +$var wire 1 u+ out0 $end +$var wire 1 v+ out1 $end +$var wire 1 l+ outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin orbits[7] $end +$scope module attempt $end +$var wire 1 w+ A $end +$var wire 1 x+ AnandB $end +$var wire 1 y+ AnorB $end +$var wire 1 z+ AorB $end +$var wire 1 {+ AxorB $end +$var wire 1 |+ B $end +$var wire 3 }+ Command [2:0] $end +$var wire 1 ~+ OrNorXorOut $end +$var wire 1 !, XorNor $end +$var wire 1 ", nXor $end +$scope module mux0 $end +$var wire 1 #, S $end +$var wire 1 {+ in0 $end +$var wire 1 y+ in1 $end +$var wire 1 $, nS $end +$var wire 1 %, out0 $end +$var wire 1 &, out1 $end +$var wire 1 !, outfinal $end +$upscope $end +$scope module mux1 $end +$var wire 1 ', S $end +$var wire 1 !, in0 $end +$var wire 1 z+ in1 $end +$var wire 1 (, nS $end +$var wire 1 ), out0 $end +$var wire 1 *, out1 $end +$var wire 1 ~+ outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin orbits[8] $end +$scope module attempt $end +$var wire 1 +, A $end +$var wire 1 ,, AnandB $end +$var wire 1 -, AnorB $end +$var wire 1 ., AorB $end +$var wire 1 /, AxorB $end +$var wire 1 0, B $end +$var wire 3 1, Command [2:0] $end +$var wire 1 2, OrNorXorOut $end +$var wire 1 3, XorNor $end +$var wire 1 4, nXor $end +$scope module mux0 $end +$var wire 1 5, S $end +$var wire 1 /, in0 $end +$var wire 1 -, in1 $end +$var wire 1 6, nS $end +$var wire 1 7, out0 $end +$var wire 1 8, out1 $end +$var wire 1 3, outfinal $end +$upscope $end +$scope module mux1 $end +$var wire 1 9, S $end +$var wire 1 3, in0 $end +$var wire 1 ., in1 $end +$var wire 1 :, nS $end +$var wire 1 ;, out0 $end +$var wire 1 <, out1 $end +$var wire 1 2, outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin orbits[9] $end +$scope module attempt $end +$var wire 1 =, A $end +$var wire 1 >, AnandB $end +$var wire 1 ?, AnorB $end +$var wire 1 @, AorB $end +$var wire 1 A, AxorB $end +$var wire 1 B, B $end +$var wire 3 C, Command [2:0] $end +$var wire 1 D, OrNorXorOut $end +$var wire 1 E, XorNor $end +$var wire 1 F, nXor $end +$scope module mux0 $end +$var wire 1 G, S $end +$var wire 1 A, in0 $end +$var wire 1 ?, in1 $end +$var wire 1 H, nS $end +$var wire 1 I, out0 $end +$var wire 1 J, out1 $end +$var wire 1 E, outfinal $end +$upscope $end +$scope module mux1 $end +$var wire 1 K, S $end +$var wire 1 E, in0 $end +$var wire 1 @, in1 $end +$var wire 1 L, nS $end +$var wire 1 M, out0 $end +$var wire 1 N, out1 $end +$var wire 1 D, outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin orbits[10] $end +$scope module attempt $end +$var wire 1 O, A $end +$var wire 1 P, AnandB $end +$var wire 1 Q, AnorB $end +$var wire 1 R, AorB $end +$var wire 1 S, AxorB $end +$var wire 1 T, B $end +$var wire 3 U, Command [2:0] $end +$var wire 1 V, OrNorXorOut $end +$var wire 1 W, XorNor $end +$var wire 1 X, nXor $end +$scope module mux0 $end +$var wire 1 Y, S $end +$var wire 1 S, in0 $end +$var wire 1 Q, in1 $end +$var wire 1 Z, nS $end +$var wire 1 [, out0 $end +$var wire 1 \, out1 $end +$var wire 1 W, outfinal $end +$upscope $end +$scope module mux1 $end +$var wire 1 ], S $end +$var wire 1 W, in0 $end +$var wire 1 R, in1 $end +$var wire 1 ^, nS $end +$var wire 1 _, out0 $end +$var wire 1 `, out1 $end +$var wire 1 V, outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin orbits[11] $end +$scope module attempt $end +$var wire 1 a, A $end +$var wire 1 b, AnandB $end +$var wire 1 c, AnorB $end +$var wire 1 d, AorB $end +$var wire 1 e, AxorB $end +$var wire 1 f, B $end +$var wire 3 g, Command [2:0] $end +$var wire 1 h, OrNorXorOut $end +$var wire 1 i, XorNor $end +$var wire 1 j, nXor $end +$scope module mux0 $end +$var wire 1 k, S $end +$var wire 1 e, in0 $end +$var wire 1 c, in1 $end +$var wire 1 l, nS $end +$var wire 1 m, out0 $end +$var wire 1 n, out1 $end +$var wire 1 i, outfinal $end +$upscope $end +$scope module mux1 $end +$var wire 1 o, S $end +$var wire 1 i, in0 $end +$var wire 1 d, in1 $end +$var wire 1 p, nS $end +$var wire 1 q, out0 $end +$var wire 1 r, out1 $end +$var wire 1 h, outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin orbits[12] $end +$scope module attempt $end +$var wire 1 s, A $end +$var wire 1 t, AnandB $end +$var wire 1 u, AnorB $end +$var wire 1 v, AorB $end +$var wire 1 w, AxorB $end +$var wire 1 x, B $end +$var wire 3 y, Command [2:0] $end +$var wire 1 z, OrNorXorOut $end +$var wire 1 {, XorNor $end +$var wire 1 |, nXor $end +$scope module mux0 $end +$var wire 1 }, S $end +$var wire 1 w, in0 $end +$var wire 1 u, in1 $end +$var wire 1 ~, nS $end +$var wire 1 !- out0 $end +$var wire 1 "- out1 $end +$var wire 1 {, outfinal $end +$upscope $end +$scope module mux1 $end +$var wire 1 #- S $end +$var wire 1 {, in0 $end +$var wire 1 v, in1 $end +$var wire 1 $- nS $end +$var wire 1 %- out0 $end +$var wire 1 &- out1 $end +$var wire 1 z, outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin orbits[13] $end +$scope module attempt $end +$var wire 1 '- A $end +$var wire 1 (- AnandB $end +$var wire 1 )- AnorB $end +$var wire 1 *- AorB $end +$var wire 1 +- AxorB $end +$var wire 1 ,- B $end +$var wire 3 -- Command [2:0] $end +$var wire 1 .- OrNorXorOut $end +$var wire 1 /- XorNor $end +$var wire 1 0- nXor $end +$scope module mux0 $end +$var wire 1 1- S $end +$var wire 1 +- in0 $end +$var wire 1 )- in1 $end +$var wire 1 2- nS $end +$var wire 1 3- out0 $end +$var wire 1 4- out1 $end +$var wire 1 /- outfinal $end +$upscope $end +$scope module mux1 $end +$var wire 1 5- S $end +$var wire 1 /- in0 $end +$var wire 1 *- in1 $end +$var wire 1 6- nS $end +$var wire 1 7- out0 $end +$var wire 1 8- out1 $end +$var wire 1 .- outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin orbits[14] $end +$scope module attempt $end +$var wire 1 9- A $end +$var wire 1 :- AnandB $end +$var wire 1 ;- AnorB $end +$var wire 1 <- AorB $end +$var wire 1 =- AxorB $end +$var wire 1 >- B $end +$var wire 3 ?- Command [2:0] $end +$var wire 1 @- OrNorXorOut $end +$var wire 1 A- XorNor $end +$var wire 1 B- nXor $end +$scope module mux0 $end +$var wire 1 C- S $end +$var wire 1 =- in0 $end +$var wire 1 ;- in1 $end +$var wire 1 D- nS $end +$var wire 1 E- out0 $end +$var wire 1 F- out1 $end +$var wire 1 A- outfinal $end +$upscope $end +$scope module mux1 $end +$var wire 1 G- S $end +$var wire 1 A- in0 $end +$var wire 1 <- in1 $end +$var wire 1 H- nS $end +$var wire 1 I- out0 $end +$var wire 1 J- out1 $end +$var wire 1 @- outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin orbits[15] $end +$scope module attempt $end +$var wire 1 K- A $end +$var wire 1 L- AnandB $end +$var wire 1 M- AnorB $end +$var wire 1 N- AorB $end +$var wire 1 O- AxorB $end +$var wire 1 P- B $end +$var wire 3 Q- Command [2:0] $end +$var wire 1 R- OrNorXorOut $end +$var wire 1 S- XorNor $end +$var wire 1 T- nXor $end +$scope module mux0 $end +$var wire 1 U- S $end +$var wire 1 O- in0 $end +$var wire 1 M- in1 $end +$var wire 1 V- nS $end +$var wire 1 W- out0 $end +$var wire 1 X- out1 $end +$var wire 1 S- outfinal $end +$upscope $end +$scope module mux1 $end +$var wire 1 Y- S $end +$var wire 1 S- in0 $end +$var wire 1 N- in1 $end +$var wire 1 Z- nS $end +$var wire 1 [- out0 $end +$var wire 1 \- out1 $end +$var wire 1 R- outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin orbits[16] $end +$scope module attempt $end +$var wire 1 ]- A $end +$var wire 1 ^- AnandB $end +$var wire 1 _- AnorB $end +$var wire 1 `- AorB $end +$var wire 1 a- AxorB $end +$var wire 1 b- B $end +$var wire 3 c- Command [2:0] $end +$var wire 1 d- OrNorXorOut $end +$var wire 1 e- XorNor $end +$var wire 1 f- nXor $end +$scope module mux0 $end +$var wire 1 g- S $end +$var wire 1 a- in0 $end +$var wire 1 _- in1 $end +$var wire 1 h- nS $end +$var wire 1 i- out0 $end +$var wire 1 j- out1 $end +$var wire 1 e- outfinal $end +$upscope $end +$scope module mux1 $end +$var wire 1 k- S $end +$var wire 1 e- in0 $end +$var wire 1 `- in1 $end +$var wire 1 l- nS $end +$var wire 1 m- out0 $end +$var wire 1 n- out1 $end +$var wire 1 d- outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin orbits[17] $end +$scope module attempt $end +$var wire 1 o- A $end +$var wire 1 p- AnandB $end +$var wire 1 q- AnorB $end +$var wire 1 r- AorB $end +$var wire 1 s- AxorB $end +$var wire 1 t- B $end +$var wire 3 u- Command [2:0] $end +$var wire 1 v- OrNorXorOut $end +$var wire 1 w- XorNor $end +$var wire 1 x- nXor $end +$scope module mux0 $end +$var wire 1 y- S $end +$var wire 1 s- in0 $end +$var wire 1 q- in1 $end +$var wire 1 z- nS $end +$var wire 1 {- out0 $end +$var wire 1 |- out1 $end +$var wire 1 w- outfinal $end +$upscope $end +$scope module mux1 $end +$var wire 1 }- S $end +$var wire 1 w- in0 $end +$var wire 1 r- in1 $end +$var wire 1 ~- nS $end +$var wire 1 !. out0 $end +$var wire 1 ". out1 $end +$var wire 1 v- outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin orbits[18] $end +$scope module attempt $end +$var wire 1 #. A $end +$var wire 1 $. AnandB $end +$var wire 1 %. AnorB $end +$var wire 1 &. AorB $end +$var wire 1 '. AxorB $end +$var wire 1 (. B $end +$var wire 3 ). Command [2:0] $end +$var wire 1 *. OrNorXorOut $end +$var wire 1 +. XorNor $end +$var wire 1 ,. nXor $end +$scope module mux0 $end +$var wire 1 -. S $end +$var wire 1 '. in0 $end +$var wire 1 %. in1 $end +$var wire 1 .. nS $end +$var wire 1 /. out0 $end +$var wire 1 0. out1 $end +$var wire 1 +. outfinal $end +$upscope $end +$scope module mux1 $end +$var wire 1 1. S $end +$var wire 1 +. in0 $end +$var wire 1 &. in1 $end +$var wire 1 2. nS $end +$var wire 1 3. out0 $end +$var wire 1 4. out1 $end +$var wire 1 *. outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin orbits[19] $end +$scope module attempt $end +$var wire 1 5. A $end +$var wire 1 6. AnandB $end +$var wire 1 7. AnorB $end +$var wire 1 8. AorB $end +$var wire 1 9. AxorB $end +$var wire 1 :. B $end +$var wire 3 ;. Command [2:0] $end +$var wire 1 <. OrNorXorOut $end +$var wire 1 =. XorNor $end +$var wire 1 >. nXor $end +$scope module mux0 $end +$var wire 1 ?. S $end +$var wire 1 9. in0 $end +$var wire 1 7. in1 $end +$var wire 1 @. nS $end +$var wire 1 A. out0 $end +$var wire 1 B. out1 $end +$var wire 1 =. outfinal $end +$upscope $end +$scope module mux1 $end +$var wire 1 C. S $end +$var wire 1 =. in0 $end +$var wire 1 8. in1 $end +$var wire 1 D. nS $end +$var wire 1 E. out0 $end +$var wire 1 F. out1 $end +$var wire 1 <. outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin orbits[20] $end +$scope module attempt $end +$var wire 1 G. A $end +$var wire 1 H. AnandB $end +$var wire 1 I. AnorB $end +$var wire 1 J. AorB $end +$var wire 1 K. AxorB $end +$var wire 1 L. B $end +$var wire 3 M. Command [2:0] $end +$var wire 1 N. OrNorXorOut $end +$var wire 1 O. XorNor $end +$var wire 1 P. nXor $end +$scope module mux0 $end +$var wire 1 Q. S $end +$var wire 1 K. in0 $end +$var wire 1 I. in1 $end +$var wire 1 R. nS $end +$var wire 1 S. out0 $end +$var wire 1 T. out1 $end +$var wire 1 O. outfinal $end +$upscope $end +$scope module mux1 $end +$var wire 1 U. S $end +$var wire 1 O. in0 $end +$var wire 1 J. in1 $end +$var wire 1 V. nS $end +$var wire 1 W. out0 $end +$var wire 1 X. out1 $end +$var wire 1 N. outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin orbits[21] $end +$scope module attempt $end +$var wire 1 Y. A $end +$var wire 1 Z. AnandB $end +$var wire 1 [. AnorB $end +$var wire 1 \. AorB $end +$var wire 1 ]. AxorB $end +$var wire 1 ^. B $end +$var wire 3 _. Command [2:0] $end +$var wire 1 `. OrNorXorOut $end +$var wire 1 a. XorNor $end +$var wire 1 b. nXor $end +$scope module mux0 $end +$var wire 1 c. S $end +$var wire 1 ]. in0 $end +$var wire 1 [. in1 $end +$var wire 1 d. nS $end +$var wire 1 e. out0 $end +$var wire 1 f. out1 $end +$var wire 1 a. outfinal $end +$upscope $end +$scope module mux1 $end +$var wire 1 g. S $end +$var wire 1 a. in0 $end +$var wire 1 \. in1 $end +$var wire 1 h. nS $end +$var wire 1 i. out0 $end +$var wire 1 j. out1 $end +$var wire 1 `. outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin orbits[22] $end +$scope module attempt $end +$var wire 1 k. A $end +$var wire 1 l. AnandB $end +$var wire 1 m. AnorB $end +$var wire 1 n. AorB $end +$var wire 1 o. AxorB $end +$var wire 1 p. B $end +$var wire 3 q. Command [2:0] $end +$var wire 1 r. OrNorXorOut $end +$var wire 1 s. XorNor $end +$var wire 1 t. nXor $end +$scope module mux0 $end +$var wire 1 u. S $end +$var wire 1 o. in0 $end +$var wire 1 m. in1 $end +$var wire 1 v. nS $end +$var wire 1 w. out0 $end +$var wire 1 x. out1 $end +$var wire 1 s. outfinal $end +$upscope $end +$scope module mux1 $end +$var wire 1 y. S $end +$var wire 1 s. in0 $end +$var wire 1 n. in1 $end +$var wire 1 z. nS $end +$var wire 1 {. out0 $end +$var wire 1 |. out1 $end +$var wire 1 r. outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin orbits[23] $end +$scope module attempt $end +$var wire 1 }. A $end +$var wire 1 ~. AnandB $end +$var wire 1 !/ AnorB $end +$var wire 1 "/ AorB $end +$var wire 1 #/ AxorB $end +$var wire 1 $/ B $end +$var wire 3 %/ Command [2:0] $end +$var wire 1 &/ OrNorXorOut $end +$var wire 1 '/ XorNor $end +$var wire 1 (/ nXor $end +$scope module mux0 $end +$var wire 1 )/ S $end +$var wire 1 #/ in0 $end +$var wire 1 !/ in1 $end +$var wire 1 */ nS $end +$var wire 1 +/ out0 $end +$var wire 1 ,/ out1 $end +$var wire 1 '/ outfinal $end +$upscope $end +$scope module mux1 $end +$var wire 1 -/ S $end +$var wire 1 '/ in0 $end +$var wire 1 "/ in1 $end +$var wire 1 ./ nS $end +$var wire 1 // out0 $end +$var wire 1 0/ out1 $end +$var wire 1 &/ outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin orbits[24] $end +$scope module attempt $end +$var wire 1 1/ A $end +$var wire 1 2/ AnandB $end +$var wire 1 3/ AnorB $end +$var wire 1 4/ AorB $end +$var wire 1 5/ AxorB $end +$var wire 1 6/ B $end +$var wire 3 7/ Command [2:0] $end +$var wire 1 8/ OrNorXorOut $end +$var wire 1 9/ XorNor $end +$var wire 1 :/ nXor $end +$scope module mux0 $end +$var wire 1 ;/ S $end +$var wire 1 5/ in0 $end +$var wire 1 3/ in1 $end +$var wire 1 / out1 $end +$var wire 1 9/ outfinal $end +$upscope $end +$scope module mux1 $end +$var wire 1 ?/ S $end +$var wire 1 9/ in0 $end +$var wire 1 4/ in1 $end +$var wire 1 @/ nS $end +$var wire 1 A/ out0 $end +$var wire 1 B/ out1 $end +$var wire 1 8/ outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin orbits[25] $end +$scope module attempt $end +$var wire 1 C/ A $end +$var wire 1 D/ AnandB $end +$var wire 1 E/ AnorB $end +$var wire 1 F/ AorB $end +$var wire 1 G/ AxorB $end +$var wire 1 H/ B $end +$var wire 3 I/ Command [2:0] $end +$var wire 1 J/ OrNorXorOut $end +$var wire 1 K/ XorNor $end +$var wire 1 L/ nXor $end +$scope module mux0 $end +$var wire 1 M/ S $end +$var wire 1 G/ in0 $end +$var wire 1 E/ in1 $end +$var wire 1 N/ nS $end +$var wire 1 O/ out0 $end +$var wire 1 P/ out1 $end +$var wire 1 K/ outfinal $end +$upscope $end +$scope module mux1 $end +$var wire 1 Q/ S $end +$var wire 1 K/ in0 $end +$var wire 1 F/ in1 $end +$var wire 1 R/ nS $end +$var wire 1 S/ out0 $end +$var wire 1 T/ out1 $end +$var wire 1 J/ outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin orbits[26] $end +$scope module attempt $end +$var wire 1 U/ A $end +$var wire 1 V/ AnandB $end +$var wire 1 W/ AnorB $end +$var wire 1 X/ AorB $end +$var wire 1 Y/ AxorB $end +$var wire 1 Z/ B $end +$var wire 3 [/ Command [2:0] $end +$var wire 1 \/ OrNorXorOut $end +$var wire 1 ]/ XorNor $end +$var wire 1 ^/ nXor $end +$scope module mux0 $end +$var wire 1 _/ S $end +$var wire 1 Y/ in0 $end +$var wire 1 W/ in1 $end +$var wire 1 `/ nS $end +$var wire 1 a/ out0 $end +$var wire 1 b/ out1 $end +$var wire 1 ]/ outfinal $end +$upscope $end +$scope module mux1 $end +$var wire 1 c/ S $end +$var wire 1 ]/ in0 $end +$var wire 1 X/ in1 $end +$var wire 1 d/ nS $end +$var wire 1 e/ out0 $end +$var wire 1 f/ out1 $end +$var wire 1 \/ outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin orbits[27] $end +$scope module attempt $end +$var wire 1 g/ A $end +$var wire 1 h/ AnandB $end +$var wire 1 i/ AnorB $end +$var wire 1 j/ AorB $end +$var wire 1 k/ AxorB $end +$var wire 1 l/ B $end +$var wire 3 m/ Command [2:0] $end +$var wire 1 n/ OrNorXorOut $end +$var wire 1 o/ XorNor $end +$var wire 1 p/ nXor $end +$scope module mux0 $end +$var wire 1 q/ S $end +$var wire 1 k/ in0 $end +$var wire 1 i/ in1 $end +$var wire 1 r/ nS $end +$var wire 1 s/ out0 $end +$var wire 1 t/ out1 $end +$var wire 1 o/ outfinal $end +$upscope $end +$scope module mux1 $end +$var wire 1 u/ S $end +$var wire 1 o/ in0 $end +$var wire 1 j/ in1 $end +$var wire 1 v/ nS $end +$var wire 1 w/ out0 $end +$var wire 1 x/ out1 $end +$var wire 1 n/ outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin orbits[28] $end +$scope module attempt $end +$var wire 1 y/ A $end +$var wire 1 z/ AnandB $end +$var wire 1 {/ AnorB $end +$var wire 1 |/ AorB $end +$var wire 1 }/ AxorB $end +$var wire 1 ~/ B $end +$var wire 3 !0 Command [2:0] $end +$var wire 1 "0 OrNorXorOut $end +$var wire 1 #0 XorNor $end +$var wire 1 $0 nXor $end +$scope module mux0 $end +$var wire 1 %0 S $end +$var wire 1 }/ in0 $end +$var wire 1 {/ in1 $end +$var wire 1 &0 nS $end +$var wire 1 '0 out0 $end +$var wire 1 (0 out1 $end +$var wire 1 #0 outfinal $end +$upscope $end +$scope module mux1 $end +$var wire 1 )0 S $end +$var wire 1 #0 in0 $end +$var wire 1 |/ in1 $end +$var wire 1 *0 nS $end +$var wire 1 +0 out0 $end +$var wire 1 ,0 out1 $end +$var wire 1 "0 outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin orbits[29] $end +$scope module attempt $end +$var wire 1 -0 A $end +$var wire 1 .0 AnandB $end +$var wire 1 /0 AnorB $end +$var wire 1 00 AorB $end +$var wire 1 10 AxorB $end +$var wire 1 20 B $end +$var wire 3 30 Command [2:0] $end +$var wire 1 40 OrNorXorOut $end +$var wire 1 50 XorNor $end +$var wire 1 60 nXor $end +$scope module mux0 $end +$var wire 1 70 S $end +$var wire 1 10 in0 $end +$var wire 1 /0 in1 $end +$var wire 1 80 nS $end +$var wire 1 90 out0 $end +$var wire 1 :0 out1 $end +$var wire 1 50 outfinal $end +$upscope $end +$scope module mux1 $end +$var wire 1 ;0 S $end +$var wire 1 50 in0 $end +$var wire 1 00 in1 $end +$var wire 1 <0 nS $end +$var wire 1 =0 out0 $end +$var wire 1 >0 out1 $end +$var wire 1 40 outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin orbits[30] $end +$scope module attempt $end +$var wire 1 ?0 A $end +$var wire 1 @0 AnandB $end +$var wire 1 A0 AnorB $end +$var wire 1 B0 AorB $end +$var wire 1 C0 AxorB $end +$var wire 1 D0 B $end +$var wire 3 E0 Command [2:0] $end +$var wire 1 F0 OrNorXorOut $end +$var wire 1 G0 XorNor $end +$var wire 1 H0 nXor $end +$scope module mux0 $end +$var wire 1 I0 S $end +$var wire 1 C0 in0 $end +$var wire 1 A0 in1 $end +$var wire 1 J0 nS $end +$var wire 1 K0 out0 $end +$var wire 1 L0 out1 $end +$var wire 1 G0 outfinal $end +$upscope $end +$scope module mux1 $end +$var wire 1 M0 S $end +$var wire 1 G0 in0 $end +$var wire 1 B0 in1 $end +$var wire 1 N0 nS $end +$var wire 1 O0 out0 $end +$var wire 1 P0 out1 $end +$var wire 1 F0 outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin orbits[31] $end +$scope module attempt $end +$var wire 1 Q0 A $end +$var wire 1 R0 AnandB $end +$var wire 1 S0 AnorB $end +$var wire 1 T0 AorB $end +$var wire 1 U0 AxorB $end +$var wire 1 V0 B $end +$var wire 3 W0 Command [2:0] $end +$var wire 1 X0 OrNorXorOut $end +$var wire 1 Y0 XorNor $end +$var wire 1 Z0 nXor $end +$scope module mux0 $end +$var wire 1 [0 S $end +$var wire 1 U0 in0 $end +$var wire 1 S0 in1 $end +$var wire 1 \0 nS $end +$var wire 1 ]0 out0 $end +$var wire 1 ^0 out1 $end +$var wire 1 Y0 outfinal $end +$upscope $end +$scope module mux1 $end +$var wire 1 _0 S $end +$var wire 1 Y0 in0 $end +$var wire 1 T0 in1 $end +$var wire 1 `0 nS $end +$var wire 1 a0 out0 $end +$var wire 1 b0 out1 $end +$var wire 1 X0 outfinal $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope module superalu $end +$var wire 32 c0 A [31:0] $end +$var wire 32 d0 AddSubSLTSum [31:0] $end +$var wire 1 " AllZeros $end +$var wire 32 e0 AndNandOut [31:0] $end +$var wire 32 f0 B [31:0] $end +$var wire 32 g0 Cmd0Start [31:0] $end +$var wire 32 h0 Cmd1Start [31:0] $end +$var wire 3 i0 Command [2:0] $end +$var wire 32 j0 OneBitFinalOut [31:0] $end +$var wire 32 k0 OrNorXorOut [31:0] $end +$var wire 1 & SLTflag $end +$var wire 32 l0 ZeroFlag [31:0] $end +$var wire 32 m0 carryin [31:0] $end +$var wire 1 ( carryout $end +$var wire 1 ) overflow $end +$var wire 32 n0 subtract [31:0] $end +$var wire 1 o0 yeszero $end +$scope module trial $end +$var wire 32 p0 A [31:0] $end +$var wire 32 q0 AddSubSLTSum [31:0] $end +$var wire 32 r0 B [31:0] $end +$var wire 32 s0 CarryoutWire [31:0] $end +$var wire 3 t0 Command [2:0] $end +$var wire 1 u0 Res0OF1 $end +$var wire 1 v0 Res1OF0 $end +$var wire 1 & SLTflag $end +$var wire 1 w0 SLTflag0 $end +$var wire 1 x0 SLTflag1 $end +$var wire 1 y0 SLTon $end +$var wire 32 z0 carryin [31:0] $end +$var wire 1 ( carryout $end +$var wire 1 {0 nAddSubSLTSum $end +$var wire 1 |0 nOF $end +$var wire 1 ) overflow $end +$var wire 32 }0 subtract [31:0] $end +$scope module attempt2 $end +$var wire 1 ~0 A $end +$var wire 1 !1 AandB $end +$var wire 1 "1 AddSubSLTSum $end +$var wire 1 #1 AxorB $end +$var wire 1 $1 B $end +$var wire 1 %1 BornB $end +$var wire 1 &1 CINandAxorB $end +$var wire 3 '1 Command [2:0] $end +$var wire 1 (1 carryin $end +$var wire 1 )1 carryout $end +$var wire 1 *1 nB $end +$var wire 1 +1 nCmd2 $end +$var wire 1 ,1 subtract $end +$scope module mux0 $end +$var wire 1 -1 S $end +$var wire 1 $1 in0 $end +$var wire 1 *1 in1 $end +$var wire 1 .1 nS $end +$var wire 1 /1 out0 $end +$var wire 1 01 out1 $end +$var wire 1 %1 outfinal $end +$upscope $end +$upscope $end +$scope begin addbits[1] $end +$scope module attempt $end +$var wire 1 11 A $end +$var wire 1 21 AandB $end +$var wire 1 31 AddSubSLTSum $end +$var wire 1 41 AxorB $end +$var wire 1 51 B $end +$var wire 1 61 BornB $end +$var wire 1 71 CINandAxorB $end +$var wire 3 81 Command [2:0] $end +$var wire 1 91 carryin $end +$var wire 1 :1 carryout $end +$var wire 1 ;1 nB $end +$var wire 1 <1 nCmd2 $end +$var wire 1 =1 subtract $end +$scope module mux0 $end +$var wire 1 >1 S $end +$var wire 1 51 in0 $end +$var wire 1 ;1 in1 $end +$var wire 1 ?1 nS $end +$var wire 1 @1 out0 $end +$var wire 1 A1 out1 $end +$var wire 1 61 outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin addbits[2] $end +$scope module attempt $end +$var wire 1 B1 A $end +$var wire 1 C1 AandB $end +$var wire 1 D1 AddSubSLTSum $end +$var wire 1 E1 AxorB $end +$var wire 1 F1 B $end +$var wire 1 G1 BornB $end +$var wire 1 H1 CINandAxorB $end +$var wire 3 I1 Command [2:0] $end +$var wire 1 J1 carryin $end +$var wire 1 K1 carryout $end +$var wire 1 L1 nB $end +$var wire 1 M1 nCmd2 $end +$var wire 1 N1 subtract $end +$scope module mux0 $end +$var wire 1 O1 S $end +$var wire 1 F1 in0 $end +$var wire 1 L1 in1 $end +$var wire 1 P1 nS $end +$var wire 1 Q1 out0 $end +$var wire 1 R1 out1 $end +$var wire 1 G1 outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin addbits[3] $end +$scope module attempt $end +$var wire 1 S1 A $end +$var wire 1 T1 AandB $end +$var wire 1 U1 AddSubSLTSum $end +$var wire 1 V1 AxorB $end +$var wire 1 W1 B $end +$var wire 1 X1 BornB $end +$var wire 1 Y1 CINandAxorB $end +$var wire 3 Z1 Command [2:0] $end +$var wire 1 [1 carryin $end +$var wire 1 \1 carryout $end +$var wire 1 ]1 nB $end +$var wire 1 ^1 nCmd2 $end +$var wire 1 _1 subtract $end +$scope module mux0 $end +$var wire 1 `1 S $end +$var wire 1 W1 in0 $end +$var wire 1 ]1 in1 $end +$var wire 1 a1 nS $end +$var wire 1 b1 out0 $end +$var wire 1 c1 out1 $end +$var wire 1 X1 outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin addbits[4] $end +$scope module attempt $end +$var wire 1 d1 A $end +$var wire 1 e1 AandB $end +$var wire 1 f1 AddSubSLTSum $end +$var wire 1 g1 AxorB $end +$var wire 1 h1 B $end +$var wire 1 i1 BornB $end +$var wire 1 j1 CINandAxorB $end +$var wire 3 k1 Command [2:0] $end +$var wire 1 l1 carryin $end +$var wire 1 m1 carryout $end +$var wire 1 n1 nB $end +$var wire 1 o1 nCmd2 $end +$var wire 1 p1 subtract $end +$scope module mux0 $end +$var wire 1 q1 S $end +$var wire 1 h1 in0 $end +$var wire 1 n1 in1 $end +$var wire 1 r1 nS $end +$var wire 1 s1 out0 $end +$var wire 1 t1 out1 $end +$var wire 1 i1 outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin addbits[5] $end +$scope module attempt $end +$var wire 1 u1 A $end +$var wire 1 v1 AandB $end +$var wire 1 w1 AddSubSLTSum $end +$var wire 1 x1 AxorB $end +$var wire 1 y1 B $end +$var wire 1 z1 BornB $end +$var wire 1 {1 CINandAxorB $end +$var wire 3 |1 Command [2:0] $end +$var wire 1 }1 carryin $end +$var wire 1 ~1 carryout $end +$var wire 1 !2 nB $end +$var wire 1 "2 nCmd2 $end +$var wire 1 #2 subtract $end +$scope module mux0 $end +$var wire 1 $2 S $end +$var wire 1 y1 in0 $end +$var wire 1 !2 in1 $end +$var wire 1 %2 nS $end +$var wire 1 &2 out0 $end +$var wire 1 '2 out1 $end +$var wire 1 z1 outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin addbits[6] $end +$scope module attempt $end +$var wire 1 (2 A $end +$var wire 1 )2 AandB $end +$var wire 1 *2 AddSubSLTSum $end +$var wire 1 +2 AxorB $end +$var wire 1 ,2 B $end +$var wire 1 -2 BornB $end +$var wire 1 .2 CINandAxorB $end +$var wire 3 /2 Command [2:0] $end +$var wire 1 02 carryin $end +$var wire 1 12 carryout $end +$var wire 1 22 nB $end +$var wire 1 32 nCmd2 $end +$var wire 1 42 subtract $end +$scope module mux0 $end +$var wire 1 52 S $end +$var wire 1 ,2 in0 $end +$var wire 1 22 in1 $end +$var wire 1 62 nS $end +$var wire 1 72 out0 $end +$var wire 1 82 out1 $end +$var wire 1 -2 outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin addbits[7] $end +$scope module attempt $end +$var wire 1 92 A $end +$var wire 1 :2 AandB $end +$var wire 1 ;2 AddSubSLTSum $end +$var wire 1 <2 AxorB $end +$var wire 1 =2 B $end +$var wire 1 >2 BornB $end +$var wire 1 ?2 CINandAxorB $end +$var wire 3 @2 Command [2:0] $end +$var wire 1 A2 carryin $end +$var wire 1 B2 carryout $end +$var wire 1 C2 nB $end +$var wire 1 D2 nCmd2 $end +$var wire 1 E2 subtract $end +$scope module mux0 $end +$var wire 1 F2 S $end +$var wire 1 =2 in0 $end +$var wire 1 C2 in1 $end +$var wire 1 G2 nS $end +$var wire 1 H2 out0 $end +$var wire 1 I2 out1 $end +$var wire 1 >2 outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin addbits[8] $end +$scope module attempt $end +$var wire 1 J2 A $end +$var wire 1 K2 AandB $end +$var wire 1 L2 AddSubSLTSum $end +$var wire 1 M2 AxorB $end +$var wire 1 N2 B $end +$var wire 1 O2 BornB $end +$var wire 1 P2 CINandAxorB $end +$var wire 3 Q2 Command [2:0] $end +$var wire 1 R2 carryin $end +$var wire 1 S2 carryout $end +$var wire 1 T2 nB $end +$var wire 1 U2 nCmd2 $end +$var wire 1 V2 subtract $end +$scope module mux0 $end +$var wire 1 W2 S $end +$var wire 1 N2 in0 $end +$var wire 1 T2 in1 $end +$var wire 1 X2 nS $end +$var wire 1 Y2 out0 $end +$var wire 1 Z2 out1 $end +$var wire 1 O2 outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin addbits[9] $end +$scope module attempt $end +$var wire 1 [2 A $end +$var wire 1 \2 AandB $end +$var wire 1 ]2 AddSubSLTSum $end +$var wire 1 ^2 AxorB $end +$var wire 1 _2 B $end +$var wire 1 `2 BornB $end +$var wire 1 a2 CINandAxorB $end +$var wire 3 b2 Command [2:0] $end +$var wire 1 c2 carryin $end +$var wire 1 d2 carryout $end +$var wire 1 e2 nB $end +$var wire 1 f2 nCmd2 $end +$var wire 1 g2 subtract $end +$scope module mux0 $end +$var wire 1 h2 S $end +$var wire 1 _2 in0 $end +$var wire 1 e2 in1 $end +$var wire 1 i2 nS $end +$var wire 1 j2 out0 $end +$var wire 1 k2 out1 $end +$var wire 1 `2 outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin addbits[10] $end +$scope module attempt $end +$var wire 1 l2 A $end +$var wire 1 m2 AandB $end +$var wire 1 n2 AddSubSLTSum $end +$var wire 1 o2 AxorB $end +$var wire 1 p2 B $end +$var wire 1 q2 BornB $end +$var wire 1 r2 CINandAxorB $end +$var wire 3 s2 Command [2:0] $end +$var wire 1 t2 carryin $end +$var wire 1 u2 carryout $end +$var wire 1 v2 nB $end +$var wire 1 w2 nCmd2 $end +$var wire 1 x2 subtract $end +$scope module mux0 $end +$var wire 1 y2 S $end +$var wire 1 p2 in0 $end +$var wire 1 v2 in1 $end +$var wire 1 z2 nS $end +$var wire 1 {2 out0 $end +$var wire 1 |2 out1 $end +$var wire 1 q2 outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin addbits[11] $end +$scope module attempt $end +$var wire 1 }2 A $end +$var wire 1 ~2 AandB $end +$var wire 1 !3 AddSubSLTSum $end +$var wire 1 "3 AxorB $end +$var wire 1 #3 B $end +$var wire 1 $3 BornB $end +$var wire 1 %3 CINandAxorB $end +$var wire 3 &3 Command [2:0] $end +$var wire 1 '3 carryin $end +$var wire 1 (3 carryout $end +$var wire 1 )3 nB $end +$var wire 1 *3 nCmd2 $end +$var wire 1 +3 subtract $end +$scope module mux0 $end +$var wire 1 ,3 S $end +$var wire 1 #3 in0 $end +$var wire 1 )3 in1 $end +$var wire 1 -3 nS $end +$var wire 1 .3 out0 $end +$var wire 1 /3 out1 $end +$var wire 1 $3 outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin addbits[12] $end +$scope module attempt $end +$var wire 1 03 A $end +$var wire 1 13 AandB $end +$var wire 1 23 AddSubSLTSum $end +$var wire 1 33 AxorB $end +$var wire 1 43 B $end +$var wire 1 53 BornB $end +$var wire 1 63 CINandAxorB $end +$var wire 3 73 Command [2:0] $end +$var wire 1 83 carryin $end +$var wire 1 93 carryout $end +$var wire 1 :3 nB $end +$var wire 1 ;3 nCmd2 $end +$var wire 1 <3 subtract $end +$scope module mux0 $end +$var wire 1 =3 S $end +$var wire 1 43 in0 $end +$var wire 1 :3 in1 $end +$var wire 1 >3 nS $end +$var wire 1 ?3 out0 $end +$var wire 1 @3 out1 $end +$var wire 1 53 outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin addbits[13] $end +$scope module attempt $end +$var wire 1 A3 A $end +$var wire 1 B3 AandB $end +$var wire 1 C3 AddSubSLTSum $end +$var wire 1 D3 AxorB $end +$var wire 1 E3 B $end +$var wire 1 F3 BornB $end +$var wire 1 G3 CINandAxorB $end +$var wire 3 H3 Command [2:0] $end +$var wire 1 I3 carryin $end +$var wire 1 J3 carryout $end +$var wire 1 K3 nB $end +$var wire 1 L3 nCmd2 $end +$var wire 1 M3 subtract $end +$scope module mux0 $end +$var wire 1 N3 S $end +$var wire 1 E3 in0 $end +$var wire 1 K3 in1 $end +$var wire 1 O3 nS $end +$var wire 1 P3 out0 $end +$var wire 1 Q3 out1 $end +$var wire 1 F3 outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin addbits[14] $end +$scope module attempt $end +$var wire 1 R3 A $end +$var wire 1 S3 AandB $end +$var wire 1 T3 AddSubSLTSum $end +$var wire 1 U3 AxorB $end +$var wire 1 V3 B $end +$var wire 1 W3 BornB $end +$var wire 1 X3 CINandAxorB $end +$var wire 3 Y3 Command [2:0] $end +$var wire 1 Z3 carryin $end +$var wire 1 [3 carryout $end +$var wire 1 \3 nB $end +$var wire 1 ]3 nCmd2 $end +$var wire 1 ^3 subtract $end +$scope module mux0 $end +$var wire 1 _3 S $end +$var wire 1 V3 in0 $end +$var wire 1 \3 in1 $end +$var wire 1 `3 nS $end +$var wire 1 a3 out0 $end +$var wire 1 b3 out1 $end +$var wire 1 W3 outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin addbits[15] $end +$scope module attempt $end +$var wire 1 c3 A $end +$var wire 1 d3 AandB $end +$var wire 1 e3 AddSubSLTSum $end +$var wire 1 f3 AxorB $end +$var wire 1 g3 B $end +$var wire 1 h3 BornB $end +$var wire 1 i3 CINandAxorB $end +$var wire 3 j3 Command [2:0] $end +$var wire 1 k3 carryin $end +$var wire 1 l3 carryout $end +$var wire 1 m3 nB $end +$var wire 1 n3 nCmd2 $end +$var wire 1 o3 subtract $end +$scope module mux0 $end +$var wire 1 p3 S $end +$var wire 1 g3 in0 $end +$var wire 1 m3 in1 $end +$var wire 1 q3 nS $end +$var wire 1 r3 out0 $end +$var wire 1 s3 out1 $end +$var wire 1 h3 outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin addbits[16] $end +$scope module attempt $end +$var wire 1 t3 A $end +$var wire 1 u3 AandB $end +$var wire 1 v3 AddSubSLTSum $end +$var wire 1 w3 AxorB $end +$var wire 1 x3 B $end +$var wire 1 y3 BornB $end +$var wire 1 z3 CINandAxorB $end +$var wire 3 {3 Command [2:0] $end +$var wire 1 |3 carryin $end +$var wire 1 }3 carryout $end +$var wire 1 ~3 nB $end +$var wire 1 !4 nCmd2 $end +$var wire 1 "4 subtract $end +$scope module mux0 $end +$var wire 1 #4 S $end +$var wire 1 x3 in0 $end +$var wire 1 ~3 in1 $end +$var wire 1 $4 nS $end +$var wire 1 %4 out0 $end +$var wire 1 &4 out1 $end +$var wire 1 y3 outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin addbits[17] $end +$scope module attempt $end +$var wire 1 '4 A $end +$var wire 1 (4 AandB $end +$var wire 1 )4 AddSubSLTSum $end +$var wire 1 *4 AxorB $end +$var wire 1 +4 B $end +$var wire 1 ,4 BornB $end +$var wire 1 -4 CINandAxorB $end +$var wire 3 .4 Command [2:0] $end +$var wire 1 /4 carryin $end +$var wire 1 04 carryout $end +$var wire 1 14 nB $end +$var wire 1 24 nCmd2 $end +$var wire 1 34 subtract $end +$scope module mux0 $end +$var wire 1 44 S $end +$var wire 1 +4 in0 $end +$var wire 1 14 in1 $end +$var wire 1 54 nS $end +$var wire 1 64 out0 $end +$var wire 1 74 out1 $end +$var wire 1 ,4 outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin addbits[18] $end +$scope module attempt $end +$var wire 1 84 A $end +$var wire 1 94 AandB $end +$var wire 1 :4 AddSubSLTSum $end +$var wire 1 ;4 AxorB $end +$var wire 1 <4 B $end +$var wire 1 =4 BornB $end +$var wire 1 >4 CINandAxorB $end +$var wire 3 ?4 Command [2:0] $end +$var wire 1 @4 carryin $end +$var wire 1 A4 carryout $end +$var wire 1 B4 nB $end +$var wire 1 C4 nCmd2 $end +$var wire 1 D4 subtract $end +$scope module mux0 $end +$var wire 1 E4 S $end +$var wire 1 <4 in0 $end +$var wire 1 B4 in1 $end +$var wire 1 F4 nS $end +$var wire 1 G4 out0 $end +$var wire 1 H4 out1 $end +$var wire 1 =4 outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin addbits[19] $end +$scope module attempt $end +$var wire 1 I4 A $end +$var wire 1 J4 AandB $end +$var wire 1 K4 AddSubSLTSum $end +$var wire 1 L4 AxorB $end +$var wire 1 M4 B $end +$var wire 1 N4 BornB $end +$var wire 1 O4 CINandAxorB $end +$var wire 3 P4 Command [2:0] $end +$var wire 1 Q4 carryin $end +$var wire 1 R4 carryout $end +$var wire 1 S4 nB $end +$var wire 1 T4 nCmd2 $end +$var wire 1 U4 subtract $end +$scope module mux0 $end +$var wire 1 V4 S $end +$var wire 1 M4 in0 $end +$var wire 1 S4 in1 $end +$var wire 1 W4 nS $end +$var wire 1 X4 out0 $end +$var wire 1 Y4 out1 $end +$var wire 1 N4 outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin addbits[20] $end +$scope module attempt $end +$var wire 1 Z4 A $end +$var wire 1 [4 AandB $end +$var wire 1 \4 AddSubSLTSum $end +$var wire 1 ]4 AxorB $end +$var wire 1 ^4 B $end +$var wire 1 _4 BornB $end +$var wire 1 `4 CINandAxorB $end +$var wire 3 a4 Command [2:0] $end +$var wire 1 b4 carryin $end +$var wire 1 c4 carryout $end +$var wire 1 d4 nB $end +$var wire 1 e4 nCmd2 $end +$var wire 1 f4 subtract $end +$scope module mux0 $end +$var wire 1 g4 S $end +$var wire 1 ^4 in0 $end +$var wire 1 d4 in1 $end +$var wire 1 h4 nS $end +$var wire 1 i4 out0 $end +$var wire 1 j4 out1 $end +$var wire 1 _4 outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin addbits[21] $end +$scope module attempt $end +$var wire 1 k4 A $end +$var wire 1 l4 AandB $end +$var wire 1 m4 AddSubSLTSum $end +$var wire 1 n4 AxorB $end +$var wire 1 o4 B $end +$var wire 1 p4 BornB $end +$var wire 1 q4 CINandAxorB $end +$var wire 3 r4 Command [2:0] $end +$var wire 1 s4 carryin $end +$var wire 1 t4 carryout $end +$var wire 1 u4 nB $end +$var wire 1 v4 nCmd2 $end +$var wire 1 w4 subtract $end +$scope module mux0 $end +$var wire 1 x4 S $end +$var wire 1 o4 in0 $end +$var wire 1 u4 in1 $end +$var wire 1 y4 nS $end +$var wire 1 z4 out0 $end +$var wire 1 {4 out1 $end +$var wire 1 p4 outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin addbits[22] $end +$scope module attempt $end +$var wire 1 |4 A $end +$var wire 1 }4 AandB $end +$var wire 1 ~4 AddSubSLTSum $end +$var wire 1 !5 AxorB $end +$var wire 1 "5 B $end +$var wire 1 #5 BornB $end +$var wire 1 $5 CINandAxorB $end +$var wire 3 %5 Command [2:0] $end +$var wire 1 &5 carryin $end +$var wire 1 '5 carryout $end +$var wire 1 (5 nB $end +$var wire 1 )5 nCmd2 $end +$var wire 1 *5 subtract $end +$scope module mux0 $end +$var wire 1 +5 S $end +$var wire 1 "5 in0 $end +$var wire 1 (5 in1 $end +$var wire 1 ,5 nS $end +$var wire 1 -5 out0 $end +$var wire 1 .5 out1 $end +$var wire 1 #5 outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin addbits[23] $end +$scope module attempt $end +$var wire 1 /5 A $end +$var wire 1 05 AandB $end +$var wire 1 15 AddSubSLTSum $end +$var wire 1 25 AxorB $end +$var wire 1 35 B $end +$var wire 1 45 BornB $end +$var wire 1 55 CINandAxorB $end +$var wire 3 65 Command [2:0] $end +$var wire 1 75 carryin $end +$var wire 1 85 carryout $end +$var wire 1 95 nB $end +$var wire 1 :5 nCmd2 $end +$var wire 1 ;5 subtract $end +$scope module mux0 $end +$var wire 1 <5 S $end +$var wire 1 35 in0 $end +$var wire 1 95 in1 $end +$var wire 1 =5 nS $end +$var wire 1 >5 out0 $end +$var wire 1 ?5 out1 $end +$var wire 1 45 outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin addbits[24] $end +$scope module attempt $end +$var wire 1 @5 A $end +$var wire 1 A5 AandB $end +$var wire 1 B5 AddSubSLTSum $end +$var wire 1 C5 AxorB $end +$var wire 1 D5 B $end +$var wire 1 E5 BornB $end +$var wire 1 F5 CINandAxorB $end +$var wire 3 G5 Command [2:0] $end +$var wire 1 H5 carryin $end +$var wire 1 I5 carryout $end +$var wire 1 J5 nB $end +$var wire 1 K5 nCmd2 $end +$var wire 1 L5 subtract $end +$scope module mux0 $end +$var wire 1 M5 S $end +$var wire 1 D5 in0 $end +$var wire 1 J5 in1 $end +$var wire 1 N5 nS $end +$var wire 1 O5 out0 $end +$var wire 1 P5 out1 $end +$var wire 1 E5 outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin addbits[25] $end +$scope module attempt $end +$var wire 1 Q5 A $end +$var wire 1 R5 AandB $end +$var wire 1 S5 AddSubSLTSum $end +$var wire 1 T5 AxorB $end +$var wire 1 U5 B $end +$var wire 1 V5 BornB $end +$var wire 1 W5 CINandAxorB $end +$var wire 3 X5 Command [2:0] $end +$var wire 1 Y5 carryin $end +$var wire 1 Z5 carryout $end +$var wire 1 [5 nB $end +$var wire 1 \5 nCmd2 $end +$var wire 1 ]5 subtract $end +$scope module mux0 $end +$var wire 1 ^5 S $end +$var wire 1 U5 in0 $end +$var wire 1 [5 in1 $end +$var wire 1 _5 nS $end +$var wire 1 `5 out0 $end +$var wire 1 a5 out1 $end +$var wire 1 V5 outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin addbits[26] $end +$scope module attempt $end +$var wire 1 b5 A $end +$var wire 1 c5 AandB $end +$var wire 1 d5 AddSubSLTSum $end +$var wire 1 e5 AxorB $end +$var wire 1 f5 B $end +$var wire 1 g5 BornB $end +$var wire 1 h5 CINandAxorB $end +$var wire 3 i5 Command [2:0] $end +$var wire 1 j5 carryin $end +$var wire 1 k5 carryout $end +$var wire 1 l5 nB $end +$var wire 1 m5 nCmd2 $end +$var wire 1 n5 subtract $end +$scope module mux0 $end +$var wire 1 o5 S $end +$var wire 1 f5 in0 $end +$var wire 1 l5 in1 $end +$var wire 1 p5 nS $end +$var wire 1 q5 out0 $end +$var wire 1 r5 out1 $end +$var wire 1 g5 outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin addbits[27] $end +$scope module attempt $end +$var wire 1 s5 A $end +$var wire 1 t5 AandB $end +$var wire 1 u5 AddSubSLTSum $end +$var wire 1 v5 AxorB $end +$var wire 1 w5 B $end +$var wire 1 x5 BornB $end +$var wire 1 y5 CINandAxorB $end +$var wire 3 z5 Command [2:0] $end +$var wire 1 {5 carryin $end +$var wire 1 |5 carryout $end +$var wire 1 }5 nB $end +$var wire 1 ~5 nCmd2 $end +$var wire 1 !6 subtract $end +$scope module mux0 $end +$var wire 1 "6 S $end +$var wire 1 w5 in0 $end +$var wire 1 }5 in1 $end +$var wire 1 #6 nS $end +$var wire 1 $6 out0 $end +$var wire 1 %6 out1 $end +$var wire 1 x5 outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin addbits[28] $end +$scope module attempt $end +$var wire 1 &6 A $end +$var wire 1 '6 AandB $end +$var wire 1 (6 AddSubSLTSum $end +$var wire 1 )6 AxorB $end +$var wire 1 *6 B $end +$var wire 1 +6 BornB $end +$var wire 1 ,6 CINandAxorB $end +$var wire 3 -6 Command [2:0] $end +$var wire 1 .6 carryin $end +$var wire 1 /6 carryout $end +$var wire 1 06 nB $end +$var wire 1 16 nCmd2 $end +$var wire 1 26 subtract $end +$scope module mux0 $end +$var wire 1 36 S $end +$var wire 1 *6 in0 $end +$var wire 1 06 in1 $end +$var wire 1 46 nS $end +$var wire 1 56 out0 $end +$var wire 1 66 out1 $end +$var wire 1 +6 outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin addbits[29] $end +$scope module attempt $end +$var wire 1 76 A $end +$var wire 1 86 AandB $end +$var wire 1 96 AddSubSLTSum $end +$var wire 1 :6 AxorB $end +$var wire 1 ;6 B $end +$var wire 1 <6 BornB $end +$var wire 1 =6 CINandAxorB $end +$var wire 3 >6 Command [2:0] $end +$var wire 1 ?6 carryin $end +$var wire 1 @6 carryout $end +$var wire 1 A6 nB $end +$var wire 1 B6 nCmd2 $end +$var wire 1 C6 subtract $end +$scope module mux0 $end +$var wire 1 D6 S $end +$var wire 1 ;6 in0 $end +$var wire 1 A6 in1 $end +$var wire 1 E6 nS $end +$var wire 1 F6 out0 $end +$var wire 1 G6 out1 $end +$var wire 1 <6 outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin addbits[30] $end +$scope module attempt $end +$var wire 1 H6 A $end +$var wire 1 I6 AandB $end +$var wire 1 J6 AddSubSLTSum $end +$var wire 1 K6 AxorB $end +$var wire 1 L6 B $end +$var wire 1 M6 BornB $end +$var wire 1 N6 CINandAxorB $end +$var wire 3 O6 Command [2:0] $end +$var wire 1 P6 carryin $end +$var wire 1 Q6 carryout $end +$var wire 1 R6 nB $end +$var wire 1 S6 nCmd2 $end +$var wire 1 T6 subtract $end +$scope module mux0 $end +$var wire 1 U6 S $end +$var wire 1 L6 in0 $end +$var wire 1 R6 in1 $end +$var wire 1 V6 nS $end +$var wire 1 W6 out0 $end +$var wire 1 X6 out1 $end +$var wire 1 M6 outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin addbits[31] $end +$scope module attempt $end +$var wire 1 Y6 A $end +$var wire 1 Z6 AandB $end +$var wire 1 [6 AddSubSLTSum $end +$var wire 1 \6 AxorB $end +$var wire 1 ]6 B $end +$var wire 1 ^6 BornB $end +$var wire 1 _6 CINandAxorB $end +$var wire 3 `6 Command [2:0] $end +$var wire 1 a6 carryin $end +$var wire 1 b6 carryout $end +$var wire 1 c6 nB $end +$var wire 1 d6 nCmd2 $end +$var wire 1 e6 subtract $end +$scope module mux0 $end +$var wire 1 f6 S $end +$var wire 1 ]6 in0 $end +$var wire 1 c6 in1 $end +$var wire 1 g6 nS $end +$var wire 1 h6 out0 $end +$var wire 1 i6 out1 $end +$var wire 1 ^6 outfinal $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope module trial1 $end +$var wire 32 j6 A [31:0] $end +$var wire 32 k6 AndNandOut [31:0] $end +$var wire 32 l6 B [31:0] $end +$var wire 3 m6 Command [2:0] $end +$scope module attempt2 $end +$var wire 1 n6 A $end +$var wire 1 o6 AandB $end +$var wire 1 p6 AnandB $end +$var wire 1 q6 AndNandOut $end +$var wire 1 r6 B $end +$var wire 3 s6 Command [2:0] $end +$scope module potato $end +$var wire 1 t6 S $end +$var wire 1 o6 in0 $end +$var wire 1 p6 in1 $end +$var wire 1 u6 nS $end +$var wire 1 v6 out0 $end +$var wire 1 w6 out1 $end +$var wire 1 q6 outfinal $end +$upscope $end +$upscope $end +$scope begin andbits[1] $end +$scope module attempt $end +$var wire 1 x6 A $end +$var wire 1 y6 AandB $end +$var wire 1 z6 AnandB $end +$var wire 1 {6 AndNandOut $end +$var wire 1 |6 B $end +$var wire 3 }6 Command [2:0] $end +$scope module potato $end +$var wire 1 ~6 S $end +$var wire 1 y6 in0 $end +$var wire 1 z6 in1 $end +$var wire 1 !7 nS $end +$var wire 1 "7 out0 $end +$var wire 1 #7 out1 $end +$var wire 1 {6 outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin andbits[2] $end +$scope module attempt $end +$var wire 1 $7 A $end +$var wire 1 %7 AandB $end +$var wire 1 &7 AnandB $end +$var wire 1 '7 AndNandOut $end +$var wire 1 (7 B $end +$var wire 3 )7 Command [2:0] $end +$scope module potato $end +$var wire 1 *7 S $end +$var wire 1 %7 in0 $end +$var wire 1 &7 in1 $end +$var wire 1 +7 nS $end +$var wire 1 ,7 out0 $end +$var wire 1 -7 out1 $end +$var wire 1 '7 outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin andbits[3] $end +$scope module attempt $end +$var wire 1 .7 A $end +$var wire 1 /7 AandB $end +$var wire 1 07 AnandB $end +$var wire 1 17 AndNandOut $end +$var wire 1 27 B $end +$var wire 3 37 Command [2:0] $end +$scope module potato $end +$var wire 1 47 S $end +$var wire 1 /7 in0 $end +$var wire 1 07 in1 $end +$var wire 1 57 nS $end +$var wire 1 67 out0 $end +$var wire 1 77 out1 $end +$var wire 1 17 outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin andbits[4] $end +$scope module attempt $end +$var wire 1 87 A $end +$var wire 1 97 AandB $end +$var wire 1 :7 AnandB $end +$var wire 1 ;7 AndNandOut $end +$var wire 1 <7 B $end +$var wire 3 =7 Command [2:0] $end +$scope module potato $end +$var wire 1 >7 S $end +$var wire 1 97 in0 $end +$var wire 1 :7 in1 $end +$var wire 1 ?7 nS $end +$var wire 1 @7 out0 $end +$var wire 1 A7 out1 $end +$var wire 1 ;7 outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin andbits[5] $end +$scope module attempt $end +$var wire 1 B7 A $end +$var wire 1 C7 AandB $end +$var wire 1 D7 AnandB $end +$var wire 1 E7 AndNandOut $end +$var wire 1 F7 B $end +$var wire 3 G7 Command [2:0] $end +$scope module potato $end +$var wire 1 H7 S $end +$var wire 1 C7 in0 $end +$var wire 1 D7 in1 $end +$var wire 1 I7 nS $end +$var wire 1 J7 out0 $end +$var wire 1 K7 out1 $end +$var wire 1 E7 outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin andbits[6] $end +$scope module attempt $end +$var wire 1 L7 A $end +$var wire 1 M7 AandB $end +$var wire 1 N7 AnandB $end +$var wire 1 O7 AndNandOut $end +$var wire 1 P7 B $end +$var wire 3 Q7 Command [2:0] $end +$scope module potato $end +$var wire 1 R7 S $end +$var wire 1 M7 in0 $end +$var wire 1 N7 in1 $end +$var wire 1 S7 nS $end +$var wire 1 T7 out0 $end +$var wire 1 U7 out1 $end +$var wire 1 O7 outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin andbits[7] $end +$scope module attempt $end +$var wire 1 V7 A $end +$var wire 1 W7 AandB $end +$var wire 1 X7 AnandB $end +$var wire 1 Y7 AndNandOut $end +$var wire 1 Z7 B $end +$var wire 3 [7 Command [2:0] $end +$scope module potato $end +$var wire 1 \7 S $end +$var wire 1 W7 in0 $end +$var wire 1 X7 in1 $end +$var wire 1 ]7 nS $end +$var wire 1 ^7 out0 $end +$var wire 1 _7 out1 $end +$var wire 1 Y7 outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin andbits[8] $end +$scope module attempt $end +$var wire 1 `7 A $end +$var wire 1 a7 AandB $end +$var wire 1 b7 AnandB $end +$var wire 1 c7 AndNandOut $end +$var wire 1 d7 B $end +$var wire 3 e7 Command [2:0] $end +$scope module potato $end +$var wire 1 f7 S $end +$var wire 1 a7 in0 $end +$var wire 1 b7 in1 $end +$var wire 1 g7 nS $end +$var wire 1 h7 out0 $end +$var wire 1 i7 out1 $end +$var wire 1 c7 outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin andbits[9] $end +$scope module attempt $end +$var wire 1 j7 A $end +$var wire 1 k7 AandB $end +$var wire 1 l7 AnandB $end +$var wire 1 m7 AndNandOut $end +$var wire 1 n7 B $end +$var wire 3 o7 Command [2:0] $end +$scope module potato $end +$var wire 1 p7 S $end +$var wire 1 k7 in0 $end +$var wire 1 l7 in1 $end +$var wire 1 q7 nS $end +$var wire 1 r7 out0 $end +$var wire 1 s7 out1 $end +$var wire 1 m7 outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin andbits[10] $end +$scope module attempt $end +$var wire 1 t7 A $end +$var wire 1 u7 AandB $end +$var wire 1 v7 AnandB $end +$var wire 1 w7 AndNandOut $end +$var wire 1 x7 B $end +$var wire 3 y7 Command [2:0] $end +$scope module potato $end +$var wire 1 z7 S $end +$var wire 1 u7 in0 $end +$var wire 1 v7 in1 $end +$var wire 1 {7 nS $end +$var wire 1 |7 out0 $end +$var wire 1 }7 out1 $end +$var wire 1 w7 outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin andbits[11] $end +$scope module attempt $end +$var wire 1 ~7 A $end +$var wire 1 !8 AandB $end +$var wire 1 "8 AnandB $end +$var wire 1 #8 AndNandOut $end +$var wire 1 $8 B $end +$var wire 3 %8 Command [2:0] $end +$scope module potato $end +$var wire 1 &8 S $end +$var wire 1 !8 in0 $end +$var wire 1 "8 in1 $end +$var wire 1 '8 nS $end +$var wire 1 (8 out0 $end +$var wire 1 )8 out1 $end +$var wire 1 #8 outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin andbits[12] $end +$scope module attempt $end +$var wire 1 *8 A $end +$var wire 1 +8 AandB $end +$var wire 1 ,8 AnandB $end +$var wire 1 -8 AndNandOut $end +$var wire 1 .8 B $end +$var wire 3 /8 Command [2:0] $end +$scope module potato $end +$var wire 1 08 S $end +$var wire 1 +8 in0 $end +$var wire 1 ,8 in1 $end +$var wire 1 18 nS $end +$var wire 1 28 out0 $end +$var wire 1 38 out1 $end +$var wire 1 -8 outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin andbits[13] $end +$scope module attempt $end +$var wire 1 48 A $end +$var wire 1 58 AandB $end +$var wire 1 68 AnandB $end +$var wire 1 78 AndNandOut $end +$var wire 1 88 B $end +$var wire 3 98 Command [2:0] $end +$scope module potato $end +$var wire 1 :8 S $end +$var wire 1 58 in0 $end +$var wire 1 68 in1 $end +$var wire 1 ;8 nS $end +$var wire 1 <8 out0 $end +$var wire 1 =8 out1 $end +$var wire 1 78 outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin andbits[14] $end +$scope module attempt $end +$var wire 1 >8 A $end +$var wire 1 ?8 AandB $end +$var wire 1 @8 AnandB $end +$var wire 1 A8 AndNandOut $end +$var wire 1 B8 B $end +$var wire 3 C8 Command [2:0] $end +$scope module potato $end +$var wire 1 D8 S $end +$var wire 1 ?8 in0 $end +$var wire 1 @8 in1 $end +$var wire 1 E8 nS $end +$var wire 1 F8 out0 $end +$var wire 1 G8 out1 $end +$var wire 1 A8 outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin andbits[15] $end +$scope module attempt $end +$var wire 1 H8 A $end +$var wire 1 I8 AandB $end +$var wire 1 J8 AnandB $end +$var wire 1 K8 AndNandOut $end +$var wire 1 L8 B $end +$var wire 3 M8 Command [2:0] $end +$scope module potato $end +$var wire 1 N8 S $end +$var wire 1 I8 in0 $end +$var wire 1 J8 in1 $end +$var wire 1 O8 nS $end +$var wire 1 P8 out0 $end +$var wire 1 Q8 out1 $end +$var wire 1 K8 outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin andbits[16] $end +$scope module attempt $end +$var wire 1 R8 A $end +$var wire 1 S8 AandB $end +$var wire 1 T8 AnandB $end +$var wire 1 U8 AndNandOut $end +$var wire 1 V8 B $end +$var wire 3 W8 Command [2:0] $end +$scope module potato $end +$var wire 1 X8 S $end +$var wire 1 S8 in0 $end +$var wire 1 T8 in1 $end +$var wire 1 Y8 nS $end +$var wire 1 Z8 out0 $end +$var wire 1 [8 out1 $end +$var wire 1 U8 outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin andbits[17] $end +$scope module attempt $end +$var wire 1 \8 A $end +$var wire 1 ]8 AandB $end +$var wire 1 ^8 AnandB $end +$var wire 1 _8 AndNandOut $end +$var wire 1 `8 B $end +$var wire 3 a8 Command [2:0] $end +$scope module potato $end +$var wire 1 b8 S $end +$var wire 1 ]8 in0 $end +$var wire 1 ^8 in1 $end +$var wire 1 c8 nS $end +$var wire 1 d8 out0 $end +$var wire 1 e8 out1 $end +$var wire 1 _8 outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin andbits[18] $end +$scope module attempt $end +$var wire 1 f8 A $end +$var wire 1 g8 AandB $end +$var wire 1 h8 AnandB $end +$var wire 1 i8 AndNandOut $end +$var wire 1 j8 B $end +$var wire 3 k8 Command [2:0] $end +$scope module potato $end +$var wire 1 l8 S $end +$var wire 1 g8 in0 $end +$var wire 1 h8 in1 $end +$var wire 1 m8 nS $end +$var wire 1 n8 out0 $end +$var wire 1 o8 out1 $end +$var wire 1 i8 outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin andbits[19] $end +$scope module attempt $end +$var wire 1 p8 A $end +$var wire 1 q8 AandB $end +$var wire 1 r8 AnandB $end +$var wire 1 s8 AndNandOut $end +$var wire 1 t8 B $end +$var wire 3 u8 Command [2:0] $end +$scope module potato $end +$var wire 1 v8 S $end +$var wire 1 q8 in0 $end +$var wire 1 r8 in1 $end +$var wire 1 w8 nS $end +$var wire 1 x8 out0 $end +$var wire 1 y8 out1 $end +$var wire 1 s8 outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin andbits[20] $end +$scope module attempt $end +$var wire 1 z8 A $end +$var wire 1 {8 AandB $end +$var wire 1 |8 AnandB $end +$var wire 1 }8 AndNandOut $end +$var wire 1 ~8 B $end +$var wire 3 !9 Command [2:0] $end +$scope module potato $end +$var wire 1 "9 S $end +$var wire 1 {8 in0 $end +$var wire 1 |8 in1 $end +$var wire 1 #9 nS $end +$var wire 1 $9 out0 $end +$var wire 1 %9 out1 $end +$var wire 1 }8 outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin andbits[21] $end +$scope module attempt $end +$var wire 1 &9 A $end +$var wire 1 '9 AandB $end +$var wire 1 (9 AnandB $end +$var wire 1 )9 AndNandOut $end +$var wire 1 *9 B $end +$var wire 3 +9 Command [2:0] $end +$scope module potato $end +$var wire 1 ,9 S $end +$var wire 1 '9 in0 $end +$var wire 1 (9 in1 $end +$var wire 1 -9 nS $end +$var wire 1 .9 out0 $end +$var wire 1 /9 out1 $end +$var wire 1 )9 outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin andbits[22] $end +$scope module attempt $end +$var wire 1 09 A $end +$var wire 1 19 AandB $end +$var wire 1 29 AnandB $end +$var wire 1 39 AndNandOut $end +$var wire 1 49 B $end +$var wire 3 59 Command [2:0] $end +$scope module potato $end +$var wire 1 69 S $end +$var wire 1 19 in0 $end +$var wire 1 29 in1 $end +$var wire 1 79 nS $end +$var wire 1 89 out0 $end +$var wire 1 99 out1 $end +$var wire 1 39 outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin andbits[23] $end +$scope module attempt $end +$var wire 1 :9 A $end +$var wire 1 ;9 AandB $end +$var wire 1 <9 AnandB $end +$var wire 1 =9 AndNandOut $end +$var wire 1 >9 B $end +$var wire 3 ?9 Command [2:0] $end +$scope module potato $end +$var wire 1 @9 S $end +$var wire 1 ;9 in0 $end +$var wire 1 <9 in1 $end +$var wire 1 A9 nS $end +$var wire 1 B9 out0 $end +$var wire 1 C9 out1 $end +$var wire 1 =9 outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin andbits[24] $end +$scope module attempt $end +$var wire 1 D9 A $end +$var wire 1 E9 AandB $end +$var wire 1 F9 AnandB $end +$var wire 1 G9 AndNandOut $end +$var wire 1 H9 B $end +$var wire 3 I9 Command [2:0] $end +$scope module potato $end +$var wire 1 J9 S $end +$var wire 1 E9 in0 $end +$var wire 1 F9 in1 $end +$var wire 1 K9 nS $end +$var wire 1 L9 out0 $end +$var wire 1 M9 out1 $end +$var wire 1 G9 outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin andbits[25] $end +$scope module attempt $end +$var wire 1 N9 A $end +$var wire 1 O9 AandB $end +$var wire 1 P9 AnandB $end +$var wire 1 Q9 AndNandOut $end +$var wire 1 R9 B $end +$var wire 3 S9 Command [2:0] $end +$scope module potato $end +$var wire 1 T9 S $end +$var wire 1 O9 in0 $end +$var wire 1 P9 in1 $end +$var wire 1 U9 nS $end +$var wire 1 V9 out0 $end +$var wire 1 W9 out1 $end +$var wire 1 Q9 outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin andbits[26] $end +$scope module attempt $end +$var wire 1 X9 A $end +$var wire 1 Y9 AandB $end +$var wire 1 Z9 AnandB $end +$var wire 1 [9 AndNandOut $end +$var wire 1 \9 B $end +$var wire 3 ]9 Command [2:0] $end +$scope module potato $end +$var wire 1 ^9 S $end +$var wire 1 Y9 in0 $end +$var wire 1 Z9 in1 $end +$var wire 1 _9 nS $end +$var wire 1 `9 out0 $end +$var wire 1 a9 out1 $end +$var wire 1 [9 outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin andbits[27] $end +$scope module attempt $end +$var wire 1 b9 A $end +$var wire 1 c9 AandB $end +$var wire 1 d9 AnandB $end +$var wire 1 e9 AndNandOut $end +$var wire 1 f9 B $end +$var wire 3 g9 Command [2:0] $end +$scope module potato $end +$var wire 1 h9 S $end +$var wire 1 c9 in0 $end +$var wire 1 d9 in1 $end +$var wire 1 i9 nS $end +$var wire 1 j9 out0 $end +$var wire 1 k9 out1 $end +$var wire 1 e9 outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin andbits[28] $end +$scope module attempt $end +$var wire 1 l9 A $end +$var wire 1 m9 AandB $end +$var wire 1 n9 AnandB $end +$var wire 1 o9 AndNandOut $end +$var wire 1 p9 B $end +$var wire 3 q9 Command [2:0] $end +$scope module potato $end +$var wire 1 r9 S $end +$var wire 1 m9 in0 $end +$var wire 1 n9 in1 $end +$var wire 1 s9 nS $end +$var wire 1 t9 out0 $end +$var wire 1 u9 out1 $end +$var wire 1 o9 outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin andbits[29] $end +$scope module attempt $end +$var wire 1 v9 A $end +$var wire 1 w9 AandB $end +$var wire 1 x9 AnandB $end +$var wire 1 y9 AndNandOut $end +$var wire 1 z9 B $end +$var wire 3 {9 Command [2:0] $end +$scope module potato $end +$var wire 1 |9 S $end +$var wire 1 w9 in0 $end +$var wire 1 x9 in1 $end +$var wire 1 }9 nS $end +$var wire 1 ~9 out0 $end +$var wire 1 !: out1 $end +$var wire 1 y9 outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin andbits[30] $end +$scope module attempt $end +$var wire 1 ": A $end +$var wire 1 #: AandB $end +$var wire 1 $: AnandB $end +$var wire 1 %: AndNandOut $end +$var wire 1 &: B $end +$var wire 3 ': Command [2:0] $end +$scope module potato $end +$var wire 1 (: S $end +$var wire 1 #: in0 $end +$var wire 1 $: in1 $end +$var wire 1 ): nS $end +$var wire 1 *: out0 $end +$var wire 1 +: out1 $end +$var wire 1 %: outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin andbits[31] $end +$scope module attempt $end +$var wire 1 ,: A $end +$var wire 1 -: AandB $end +$var wire 1 .: AnandB $end +$var wire 1 /: AndNandOut $end +$var wire 1 0: B $end +$var wire 3 1: Command [2:0] $end +$scope module potato $end +$var wire 1 2: S $end +$var wire 1 -: in0 $end +$var wire 1 .: in1 $end +$var wire 1 3: nS $end +$var wire 1 4: out0 $end +$var wire 1 5: out1 $end +$var wire 1 /: outfinal $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope module trial2 $end +$var wire 32 6: A [31:0] $end +$var wire 32 7: B [31:0] $end +$var wire 3 8: Command [2:0] $end +$var wire 32 9: OrNorXorOut [31:0] $end +$scope module attempt2 $end +$var wire 1 :: A $end +$var wire 1 ;: AnandB $end +$var wire 1 <: AnorB $end +$var wire 1 =: AorB $end +$var wire 1 >: AxorB $end +$var wire 1 ?: B $end +$var wire 3 @: Command [2:0] $end +$var wire 1 A: OrNorXorOut $end +$var wire 1 B: XorNor $end +$var wire 1 C: nXor $end +$scope module mux0 $end +$var wire 1 D: S $end +$var wire 1 >: in0 $end +$var wire 1 <: in1 $end +$var wire 1 E: nS $end +$var wire 1 F: out0 $end +$var wire 1 G: out1 $end +$var wire 1 B: outfinal $end +$upscope $end +$scope module mux1 $end +$var wire 1 H: S $end +$var wire 1 B: in0 $end +$var wire 1 =: in1 $end +$var wire 1 I: nS $end +$var wire 1 J: out0 $end +$var wire 1 K: out1 $end +$var wire 1 A: outfinal $end +$upscope $end +$upscope $end +$scope begin orbits[1] $end +$scope module attempt $end +$var wire 1 L: A $end +$var wire 1 M: AnandB $end +$var wire 1 N: AnorB $end +$var wire 1 O: AorB $end +$var wire 1 P: AxorB $end +$var wire 1 Q: B $end +$var wire 3 R: Command [2:0] $end +$var wire 1 S: OrNorXorOut $end +$var wire 1 T: XorNor $end +$var wire 1 U: nXor $end +$scope module mux0 $end +$var wire 1 V: S $end +$var wire 1 P: in0 $end +$var wire 1 N: in1 $end +$var wire 1 W: nS $end +$var wire 1 X: out0 $end +$var wire 1 Y: out1 $end +$var wire 1 T: outfinal $end +$upscope $end +$scope module mux1 $end +$var wire 1 Z: S $end +$var wire 1 T: in0 $end +$var wire 1 O: in1 $end +$var wire 1 [: nS $end +$var wire 1 \: out0 $end +$var wire 1 ]: out1 $end +$var wire 1 S: outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin orbits[2] $end +$scope module attempt $end +$var wire 1 ^: A $end +$var wire 1 _: AnandB $end +$var wire 1 `: AnorB $end +$var wire 1 a: AorB $end +$var wire 1 b: AxorB $end +$var wire 1 c: B $end +$var wire 3 d: Command [2:0] $end +$var wire 1 e: OrNorXorOut $end +$var wire 1 f: XorNor $end +$var wire 1 g: nXor $end +$scope module mux0 $end +$var wire 1 h: S $end +$var wire 1 b: in0 $end +$var wire 1 `: in1 $end +$var wire 1 i: nS $end +$var wire 1 j: out0 $end +$var wire 1 k: out1 $end +$var wire 1 f: outfinal $end +$upscope $end +$scope module mux1 $end +$var wire 1 l: S $end +$var wire 1 f: in0 $end +$var wire 1 a: in1 $end +$var wire 1 m: nS $end +$var wire 1 n: out0 $end +$var wire 1 o: out1 $end +$var wire 1 e: outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin orbits[3] $end +$scope module attempt $end +$var wire 1 p: A $end +$var wire 1 q: AnandB $end +$var wire 1 r: AnorB $end +$var wire 1 s: AorB $end +$var wire 1 t: AxorB $end +$var wire 1 u: B $end +$var wire 3 v: Command [2:0] $end +$var wire 1 w: OrNorXorOut $end +$var wire 1 x: XorNor $end +$var wire 1 y: nXor $end +$scope module mux0 $end +$var wire 1 z: S $end +$var wire 1 t: in0 $end +$var wire 1 r: in1 $end +$var wire 1 {: nS $end +$var wire 1 |: out0 $end +$var wire 1 }: out1 $end +$var wire 1 x: outfinal $end +$upscope $end +$scope module mux1 $end +$var wire 1 ~: S $end +$var wire 1 x: in0 $end +$var wire 1 s: in1 $end +$var wire 1 !; nS $end +$var wire 1 "; out0 $end +$var wire 1 #; out1 $end +$var wire 1 w: outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin orbits[4] $end +$scope module attempt $end +$var wire 1 $; A $end +$var wire 1 %; AnandB $end +$var wire 1 &; AnorB $end +$var wire 1 '; AorB $end +$var wire 1 (; AxorB $end +$var wire 1 ); B $end +$var wire 3 *; Command [2:0] $end +$var wire 1 +; OrNorXorOut $end +$var wire 1 ,; XorNor $end +$var wire 1 -; nXor $end +$scope module mux0 $end +$var wire 1 .; S $end +$var wire 1 (; in0 $end +$var wire 1 &; in1 $end +$var wire 1 /; nS $end +$var wire 1 0; out0 $end +$var wire 1 1; out1 $end +$var wire 1 ,; outfinal $end +$upscope $end +$scope module mux1 $end +$var wire 1 2; S $end +$var wire 1 ,; in0 $end +$var wire 1 '; in1 $end +$var wire 1 3; nS $end +$var wire 1 4; out0 $end +$var wire 1 5; out1 $end +$var wire 1 +; outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin orbits[5] $end +$scope module attempt $end +$var wire 1 6; A $end +$var wire 1 7; AnandB $end +$var wire 1 8; AnorB $end +$var wire 1 9; AorB $end +$var wire 1 :; AxorB $end +$var wire 1 ;; B $end +$var wire 3 <; Command [2:0] $end +$var wire 1 =; OrNorXorOut $end +$var wire 1 >; XorNor $end +$var wire 1 ?; nXor $end +$scope module mux0 $end +$var wire 1 @; S $end +$var wire 1 :; in0 $end +$var wire 1 8; in1 $end +$var wire 1 A; nS $end +$var wire 1 B; out0 $end +$var wire 1 C; out1 $end +$var wire 1 >; outfinal $end +$upscope $end +$scope module mux1 $end +$var wire 1 D; S $end +$var wire 1 >; in0 $end +$var wire 1 9; in1 $end +$var wire 1 E; nS $end +$var wire 1 F; out0 $end +$var wire 1 G; out1 $end +$var wire 1 =; outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin orbits[6] $end +$scope module attempt $end +$var wire 1 H; A $end +$var wire 1 I; AnandB $end +$var wire 1 J; AnorB $end +$var wire 1 K; AorB $end +$var wire 1 L; AxorB $end +$var wire 1 M; B $end +$var wire 3 N; Command [2:0] $end +$var wire 1 O; OrNorXorOut $end +$var wire 1 P; XorNor $end +$var wire 1 Q; nXor $end +$scope module mux0 $end +$var wire 1 R; S $end +$var wire 1 L; in0 $end +$var wire 1 J; in1 $end +$var wire 1 S; nS $end +$var wire 1 T; out0 $end +$var wire 1 U; out1 $end +$var wire 1 P; outfinal $end +$upscope $end +$scope module mux1 $end +$var wire 1 V; S $end +$var wire 1 P; in0 $end +$var wire 1 K; in1 $end +$var wire 1 W; nS $end +$var wire 1 X; out0 $end +$var wire 1 Y; out1 $end +$var wire 1 O; outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin orbits[7] $end +$scope module attempt $end +$var wire 1 Z; A $end +$var wire 1 [; AnandB $end +$var wire 1 \; AnorB $end +$var wire 1 ]; AorB $end +$var wire 1 ^; AxorB $end +$var wire 1 _; B $end +$var wire 3 `; Command [2:0] $end +$var wire 1 a; OrNorXorOut $end +$var wire 1 b; XorNor $end +$var wire 1 c; nXor $end +$scope module mux0 $end +$var wire 1 d; S $end +$var wire 1 ^; in0 $end +$var wire 1 \; in1 $end +$var wire 1 e; nS $end +$var wire 1 f; out0 $end +$var wire 1 g; out1 $end +$var wire 1 b; outfinal $end +$upscope $end +$scope module mux1 $end +$var wire 1 h; S $end +$var wire 1 b; in0 $end +$var wire 1 ]; in1 $end +$var wire 1 i; nS $end +$var wire 1 j; out0 $end +$var wire 1 k; out1 $end +$var wire 1 a; outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin orbits[8] $end +$scope module attempt $end +$var wire 1 l; A $end +$var wire 1 m; AnandB $end +$var wire 1 n; AnorB $end +$var wire 1 o; AorB $end +$var wire 1 p; AxorB $end +$var wire 1 q; B $end +$var wire 3 r; Command [2:0] $end +$var wire 1 s; OrNorXorOut $end +$var wire 1 t; XorNor $end +$var wire 1 u; nXor $end +$scope module mux0 $end +$var wire 1 v; S $end +$var wire 1 p; in0 $end +$var wire 1 n; in1 $end +$var wire 1 w; nS $end +$var wire 1 x; out0 $end +$var wire 1 y; out1 $end +$var wire 1 t; outfinal $end +$upscope $end +$scope module mux1 $end +$var wire 1 z; S $end +$var wire 1 t; in0 $end +$var wire 1 o; in1 $end +$var wire 1 {; nS $end +$var wire 1 |; out0 $end +$var wire 1 }; out1 $end +$var wire 1 s; outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin orbits[9] $end +$scope module attempt $end +$var wire 1 ~; A $end +$var wire 1 !< AnandB $end +$var wire 1 "< AnorB $end +$var wire 1 #< AorB $end +$var wire 1 $< AxorB $end +$var wire 1 %< B $end +$var wire 3 &< Command [2:0] $end +$var wire 1 '< OrNorXorOut $end +$var wire 1 (< XorNor $end +$var wire 1 )< nXor $end +$scope module mux0 $end +$var wire 1 *< S $end +$var wire 1 $< in0 $end +$var wire 1 "< in1 $end +$var wire 1 +< nS $end +$var wire 1 ,< out0 $end +$var wire 1 -< out1 $end +$var wire 1 (< outfinal $end +$upscope $end +$scope module mux1 $end +$var wire 1 .< S $end +$var wire 1 (< in0 $end +$var wire 1 #< in1 $end +$var wire 1 /< nS $end +$var wire 1 0< out0 $end +$var wire 1 1< out1 $end +$var wire 1 '< outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin orbits[10] $end +$scope module attempt $end +$var wire 1 2< A $end +$var wire 1 3< AnandB $end +$var wire 1 4< AnorB $end +$var wire 1 5< AorB $end +$var wire 1 6< AxorB $end +$var wire 1 7< B $end +$var wire 3 8< Command [2:0] $end +$var wire 1 9< OrNorXorOut $end +$var wire 1 :< XorNor $end +$var wire 1 ;< nXor $end +$scope module mux0 $end +$var wire 1 << S $end +$var wire 1 6< in0 $end +$var wire 1 4< in1 $end +$var wire 1 =< nS $end +$var wire 1 >< out0 $end +$var wire 1 ?< out1 $end +$var wire 1 :< outfinal $end +$upscope $end +$scope module mux1 $end +$var wire 1 @< S $end +$var wire 1 :< in0 $end +$var wire 1 5< in1 $end +$var wire 1 A< nS $end +$var wire 1 B< out0 $end +$var wire 1 C< out1 $end +$var wire 1 9< outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin orbits[11] $end +$scope module attempt $end +$var wire 1 D< A $end +$var wire 1 E< AnandB $end +$var wire 1 F< AnorB $end +$var wire 1 G< AorB $end +$var wire 1 H< AxorB $end +$var wire 1 I< B $end +$var wire 3 J< Command [2:0] $end +$var wire 1 K< OrNorXorOut $end +$var wire 1 L< XorNor $end +$var wire 1 M< nXor $end +$scope module mux0 $end +$var wire 1 N< S $end +$var wire 1 H< in0 $end +$var wire 1 F< in1 $end +$var wire 1 O< nS $end +$var wire 1 P< out0 $end +$var wire 1 Q< out1 $end +$var wire 1 L< outfinal $end +$upscope $end +$scope module mux1 $end +$var wire 1 R< S $end +$var wire 1 L< in0 $end +$var wire 1 G< in1 $end +$var wire 1 S< nS $end +$var wire 1 T< out0 $end +$var wire 1 U< out1 $end +$var wire 1 K< outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin orbits[12] $end +$scope module attempt $end +$var wire 1 V< A $end +$var wire 1 W< AnandB $end +$var wire 1 X< AnorB $end +$var wire 1 Y< AorB $end +$var wire 1 Z< AxorB $end +$var wire 1 [< B $end +$var wire 3 \< Command [2:0] $end +$var wire 1 ]< OrNorXorOut $end +$var wire 1 ^< XorNor $end +$var wire 1 _< nXor $end +$scope module mux0 $end +$var wire 1 `< S $end +$var wire 1 Z< in0 $end +$var wire 1 X< in1 $end +$var wire 1 a< nS $end +$var wire 1 b< out0 $end +$var wire 1 c< out1 $end +$var wire 1 ^< outfinal $end +$upscope $end +$scope module mux1 $end +$var wire 1 d< S $end +$var wire 1 ^< in0 $end +$var wire 1 Y< in1 $end +$var wire 1 e< nS $end +$var wire 1 f< out0 $end +$var wire 1 g< out1 $end +$var wire 1 ]< outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin orbits[13] $end +$scope module attempt $end +$var wire 1 h< A $end +$var wire 1 i< AnandB $end +$var wire 1 j< AnorB $end +$var wire 1 k< AorB $end +$var wire 1 l< AxorB $end +$var wire 1 m< B $end +$var wire 3 n< Command [2:0] $end +$var wire 1 o< OrNorXorOut $end +$var wire 1 p< XorNor $end +$var wire 1 q< nXor $end +$scope module mux0 $end +$var wire 1 r< S $end +$var wire 1 l< in0 $end +$var wire 1 j< in1 $end +$var wire 1 s< nS $end +$var wire 1 t< out0 $end +$var wire 1 u< out1 $end +$var wire 1 p< outfinal $end +$upscope $end +$scope module mux1 $end +$var wire 1 v< S $end +$var wire 1 p< in0 $end +$var wire 1 k< in1 $end +$var wire 1 w< nS $end +$var wire 1 x< out0 $end +$var wire 1 y< out1 $end +$var wire 1 o< outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin orbits[14] $end +$scope module attempt $end +$var wire 1 z< A $end +$var wire 1 {< AnandB $end +$var wire 1 |< AnorB $end +$var wire 1 }< AorB $end +$var wire 1 ~< AxorB $end +$var wire 1 != B $end +$var wire 3 "= Command [2:0] $end +$var wire 1 #= OrNorXorOut $end +$var wire 1 $= XorNor $end +$var wire 1 %= nXor $end +$scope module mux0 $end +$var wire 1 &= S $end +$var wire 1 ~< in0 $end +$var wire 1 |< in1 $end +$var wire 1 '= nS $end +$var wire 1 (= out0 $end +$var wire 1 )= out1 $end +$var wire 1 $= outfinal $end +$upscope $end +$scope module mux1 $end +$var wire 1 *= S $end +$var wire 1 $= in0 $end +$var wire 1 }< in1 $end +$var wire 1 += nS $end +$var wire 1 ,= out0 $end +$var wire 1 -= out1 $end +$var wire 1 #= outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin orbits[15] $end +$scope module attempt $end +$var wire 1 .= A $end +$var wire 1 /= AnandB $end +$var wire 1 0= AnorB $end +$var wire 1 1= AorB $end +$var wire 1 2= AxorB $end +$var wire 1 3= B $end +$var wire 3 4= Command [2:0] $end +$var wire 1 5= OrNorXorOut $end +$var wire 1 6= XorNor $end +$var wire 1 7= nXor $end +$scope module mux0 $end +$var wire 1 8= S $end +$var wire 1 2= in0 $end +$var wire 1 0= in1 $end +$var wire 1 9= nS $end +$var wire 1 := out0 $end +$var wire 1 ;= out1 $end +$var wire 1 6= outfinal $end +$upscope $end +$scope module mux1 $end +$var wire 1 <= S $end +$var wire 1 6= in0 $end +$var wire 1 1= in1 $end +$var wire 1 == nS $end +$var wire 1 >= out0 $end +$var wire 1 ?= out1 $end +$var wire 1 5= outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin orbits[16] $end +$scope module attempt $end +$var wire 1 @= A $end +$var wire 1 A= AnandB $end +$var wire 1 B= AnorB $end +$var wire 1 C= AorB $end +$var wire 1 D= AxorB $end +$var wire 1 E= B $end +$var wire 3 F= Command [2:0] $end +$var wire 1 G= OrNorXorOut $end +$var wire 1 H= XorNor $end +$var wire 1 I= nXor $end +$scope module mux0 $end +$var wire 1 J= S $end +$var wire 1 D= in0 $end +$var wire 1 B= in1 $end +$var wire 1 K= nS $end +$var wire 1 L= out0 $end +$var wire 1 M= out1 $end +$var wire 1 H= outfinal $end +$upscope $end +$scope module mux1 $end +$var wire 1 N= S $end +$var wire 1 H= in0 $end +$var wire 1 C= in1 $end +$var wire 1 O= nS $end +$var wire 1 P= out0 $end +$var wire 1 Q= out1 $end +$var wire 1 G= outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin orbits[17] $end +$scope module attempt $end +$var wire 1 R= A $end +$var wire 1 S= AnandB $end +$var wire 1 T= AnorB $end +$var wire 1 U= AorB $end +$var wire 1 V= AxorB $end +$var wire 1 W= B $end +$var wire 3 X= Command [2:0] $end +$var wire 1 Y= OrNorXorOut $end +$var wire 1 Z= XorNor $end +$var wire 1 [= nXor $end +$scope module mux0 $end +$var wire 1 \= S $end +$var wire 1 V= in0 $end +$var wire 1 T= in1 $end +$var wire 1 ]= nS $end +$var wire 1 ^= out0 $end +$var wire 1 _= out1 $end +$var wire 1 Z= outfinal $end +$upscope $end +$scope module mux1 $end +$var wire 1 `= S $end +$var wire 1 Z= in0 $end +$var wire 1 U= in1 $end +$var wire 1 a= nS $end +$var wire 1 b= out0 $end +$var wire 1 c= out1 $end +$var wire 1 Y= outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin orbits[18] $end +$scope module attempt $end +$var wire 1 d= A $end +$var wire 1 e= AnandB $end +$var wire 1 f= AnorB $end +$var wire 1 g= AorB $end +$var wire 1 h= AxorB $end +$var wire 1 i= B $end +$var wire 3 j= Command [2:0] $end +$var wire 1 k= OrNorXorOut $end +$var wire 1 l= XorNor $end +$var wire 1 m= nXor $end +$scope module mux0 $end +$var wire 1 n= S $end +$var wire 1 h= in0 $end +$var wire 1 f= in1 $end +$var wire 1 o= nS $end +$var wire 1 p= out0 $end +$var wire 1 q= out1 $end +$var wire 1 l= outfinal $end +$upscope $end +$scope module mux1 $end +$var wire 1 r= S $end +$var wire 1 l= in0 $end +$var wire 1 g= in1 $end +$var wire 1 s= nS $end +$var wire 1 t= out0 $end +$var wire 1 u= out1 $end +$var wire 1 k= outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin orbits[19] $end +$scope module attempt $end +$var wire 1 v= A $end +$var wire 1 w= AnandB $end +$var wire 1 x= AnorB $end +$var wire 1 y= AorB $end +$var wire 1 z= AxorB $end +$var wire 1 {= B $end +$var wire 3 |= Command [2:0] $end +$var wire 1 }= OrNorXorOut $end +$var wire 1 ~= XorNor $end +$var wire 1 !> nXor $end +$scope module mux0 $end +$var wire 1 "> S $end +$var wire 1 z= in0 $end +$var wire 1 x= in1 $end +$var wire 1 #> nS $end +$var wire 1 $> out0 $end +$var wire 1 %> out1 $end +$var wire 1 ~= outfinal $end +$upscope $end +$scope module mux1 $end +$var wire 1 &> S $end +$var wire 1 ~= in0 $end +$var wire 1 y= in1 $end +$var wire 1 '> nS $end +$var wire 1 (> out0 $end +$var wire 1 )> out1 $end +$var wire 1 }= outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin orbits[20] $end +$scope module attempt $end +$var wire 1 *> A $end +$var wire 1 +> AnandB $end +$var wire 1 ,> AnorB $end +$var wire 1 -> AorB $end +$var wire 1 .> AxorB $end +$var wire 1 /> B $end +$var wire 3 0> Command [2:0] $end +$var wire 1 1> OrNorXorOut $end +$var wire 1 2> XorNor $end +$var wire 1 3> nXor $end +$scope module mux0 $end +$var wire 1 4> S $end +$var wire 1 .> in0 $end +$var wire 1 ,> in1 $end +$var wire 1 5> nS $end +$var wire 1 6> out0 $end +$var wire 1 7> out1 $end +$var wire 1 2> outfinal $end +$upscope $end +$scope module mux1 $end +$var wire 1 8> S $end +$var wire 1 2> in0 $end +$var wire 1 -> in1 $end +$var wire 1 9> nS $end +$var wire 1 :> out0 $end +$var wire 1 ;> out1 $end +$var wire 1 1> outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin orbits[21] $end +$scope module attempt $end +$var wire 1 <> A $end +$var wire 1 => AnandB $end +$var wire 1 >> AnorB $end +$var wire 1 ?> AorB $end +$var wire 1 @> AxorB $end +$var wire 1 A> B $end +$var wire 3 B> Command [2:0] $end +$var wire 1 C> OrNorXorOut $end +$var wire 1 D> XorNor $end +$var wire 1 E> nXor $end +$scope module mux0 $end +$var wire 1 F> S $end +$var wire 1 @> in0 $end +$var wire 1 >> in1 $end +$var wire 1 G> nS $end +$var wire 1 H> out0 $end +$var wire 1 I> out1 $end +$var wire 1 D> outfinal $end +$upscope $end +$scope module mux1 $end +$var wire 1 J> S $end +$var wire 1 D> in0 $end +$var wire 1 ?> in1 $end +$var wire 1 K> nS $end +$var wire 1 L> out0 $end +$var wire 1 M> out1 $end +$var wire 1 C> outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin orbits[22] $end +$scope module attempt $end +$var wire 1 N> A $end +$var wire 1 O> AnandB $end +$var wire 1 P> AnorB $end +$var wire 1 Q> AorB $end +$var wire 1 R> AxorB $end +$var wire 1 S> B $end +$var wire 3 T> Command [2:0] $end +$var wire 1 U> OrNorXorOut $end +$var wire 1 V> XorNor $end +$var wire 1 W> nXor $end +$scope module mux0 $end +$var wire 1 X> S $end +$var wire 1 R> in0 $end +$var wire 1 P> in1 $end +$var wire 1 Y> nS $end +$var wire 1 Z> out0 $end +$var wire 1 [> out1 $end +$var wire 1 V> outfinal $end +$upscope $end +$scope module mux1 $end +$var wire 1 \> S $end +$var wire 1 V> in0 $end +$var wire 1 Q> in1 $end +$var wire 1 ]> nS $end +$var wire 1 ^> out0 $end +$var wire 1 _> out1 $end +$var wire 1 U> outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin orbits[23] $end +$scope module attempt $end +$var wire 1 `> A $end +$var wire 1 a> AnandB $end +$var wire 1 b> AnorB $end +$var wire 1 c> AorB $end +$var wire 1 d> AxorB $end +$var wire 1 e> B $end +$var wire 3 f> Command [2:0] $end +$var wire 1 g> OrNorXorOut $end +$var wire 1 h> XorNor $end +$var wire 1 i> nXor $end +$scope module mux0 $end +$var wire 1 j> S $end +$var wire 1 d> in0 $end +$var wire 1 b> in1 $end +$var wire 1 k> nS $end +$var wire 1 l> out0 $end +$var wire 1 m> out1 $end +$var wire 1 h> outfinal $end +$upscope $end +$scope module mux1 $end +$var wire 1 n> S $end +$var wire 1 h> in0 $end +$var wire 1 c> in1 $end +$var wire 1 o> nS $end +$var wire 1 p> out0 $end +$var wire 1 q> out1 $end +$var wire 1 g> outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin orbits[24] $end +$scope module attempt $end +$var wire 1 r> A $end +$var wire 1 s> AnandB $end +$var wire 1 t> AnorB $end +$var wire 1 u> AorB $end +$var wire 1 v> AxorB $end +$var wire 1 w> B $end +$var wire 3 x> Command [2:0] $end +$var wire 1 y> OrNorXorOut $end +$var wire 1 z> XorNor $end +$var wire 1 {> nXor $end +$scope module mux0 $end +$var wire 1 |> S $end +$var wire 1 v> in0 $end +$var wire 1 t> in1 $end +$var wire 1 }> nS $end +$var wire 1 ~> out0 $end +$var wire 1 !? out1 $end +$var wire 1 z> outfinal $end +$upscope $end +$scope module mux1 $end +$var wire 1 "? S $end +$var wire 1 z> in0 $end +$var wire 1 u> in1 $end +$var wire 1 #? nS $end +$var wire 1 $? out0 $end +$var wire 1 %? out1 $end +$var wire 1 y> outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin orbits[25] $end +$scope module attempt $end +$var wire 1 &? A $end +$var wire 1 '? AnandB $end +$var wire 1 (? AnorB $end +$var wire 1 )? AorB $end +$var wire 1 *? AxorB $end +$var wire 1 +? B $end +$var wire 3 ,? Command [2:0] $end +$var wire 1 -? OrNorXorOut $end +$var wire 1 .? XorNor $end +$var wire 1 /? nXor $end +$scope module mux0 $end +$var wire 1 0? S $end +$var wire 1 *? in0 $end +$var wire 1 (? in1 $end +$var wire 1 1? nS $end +$var wire 1 2? out0 $end +$var wire 1 3? out1 $end +$var wire 1 .? outfinal $end +$upscope $end +$scope module mux1 $end +$var wire 1 4? S $end +$var wire 1 .? in0 $end +$var wire 1 )? in1 $end +$var wire 1 5? nS $end +$var wire 1 6? out0 $end +$var wire 1 7? out1 $end +$var wire 1 -? outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin orbits[26] $end +$scope module attempt $end +$var wire 1 8? A $end +$var wire 1 9? AnandB $end +$var wire 1 :? AnorB $end +$var wire 1 ;? AorB $end +$var wire 1 ? Command [2:0] $end +$var wire 1 ?? OrNorXorOut $end +$var wire 1 @? XorNor $end +$var wire 1 A? nXor $end +$scope module mux0 $end +$var wire 1 B? S $end +$var wire 1 @ S $end +$var wire 1 8@ in0 $end +$var wire 1 6@ in1 $end +$var wire 1 ?@ nS $end +$var wire 1 @@ out0 $end +$var wire 1 A@ out1 $end +$var wire 1 <@ outfinal $end +$upscope $end +$scope module mux1 $end +$var wire 1 B@ S $end +$var wire 1 <@ in0 $end +$var wire 1 7@ in1 $end +$var wire 1 C@ nS $end +$var wire 1 D@ out0 $end +$var wire 1 E@ out1 $end +$var wire 1 ;@ outfinal $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope module ZeroMux0case $end +$var wire 1 F@ S0 $end +$var wire 1 G@ S1 $end +$var wire 1 H@ in0 $end +$var wire 1 I@ in1 $end +$var wire 1 J@ in2 $end +$var wire 1 K@ in3 $end +$var wire 1 L@ nS0 $end +$var wire 1 M@ nS1 $end +$var wire 1 N@ out $end +$var wire 1 O@ out0 $end +$var wire 1 P@ out1 $end +$var wire 1 Q@ out2 $end +$var wire 1 R@ out3 $end +$upscope $end +$scope module OneMux0case $end +$var wire 1 S@ S0 $end +$var wire 1 T@ S1 $end +$var wire 1 U@ in0 $end +$var wire 1 V@ in1 $end +$var wire 1 W@ in2 $end +$var wire 1 X@ in3 $end +$var wire 1 Y@ nS0 $end +$var wire 1 Z@ nS1 $end +$var wire 1 [@ out $end +$var wire 1 \@ out0 $end +$var wire 1 ]@ out1 $end +$var wire 1 ^@ out2 $end +$var wire 1 _@ out3 $end +$upscope $end +$scope module TwoMux0case $end +$var wire 1 `@ S $end +$var wire 1 a@ in0 $end +$var wire 1 b@ in1 $end +$var wire 1 c@ nS $end +$var wire 1 d@ out0 $end +$var wire 1 e@ out1 $end +$var wire 1 f@ outfinal $end +$upscope $end +$scope begin muxbits[1] $end +$scope module ZeroMux $end +$var wire 1 g@ S0 $end +$var wire 1 h@ S1 $end +$var wire 1 i@ in0 $end +$var wire 1 j@ in1 $end +$var wire 1 k@ in2 $end +$var wire 1 l@ in3 $end +$var wire 1 m@ nS0 $end +$var wire 1 n@ nS1 $end +$var wire 1 o@ out $end +$var wire 1 p@ out0 $end +$var wire 1 q@ out1 $end +$var wire 1 r@ out2 $end +$var wire 1 s@ out3 $end +$upscope $end +$scope module OneMux $end +$var wire 1 t@ S0 $end +$var wire 1 u@ S1 $end +$var wire 1 v@ in0 $end +$var wire 1 w@ in1 $end +$var wire 1 x@ in2 $end +$var wire 1 y@ in3 $end +$var wire 1 z@ nS0 $end +$var wire 1 {@ nS1 $end +$var wire 1 |@ out $end +$var wire 1 }@ out0 $end +$var wire 1 ~@ out1 $end +$var wire 1 !A out2 $end +$var wire 1 "A out3 $end +$upscope $end +$scope module TwoMux $end +$var wire 1 #A S $end +$var wire 1 $A in0 $end +$var wire 1 %A in1 $end +$var wire 1 &A nS $end +$var wire 1 'A out0 $end +$var wire 1 (A out1 $end +$var wire 1 )A outfinal $end +$upscope $end +$upscope $end +$scope begin muxbits[2] $end +$scope module ZeroMux $end +$var wire 1 *A S0 $end +$var wire 1 +A S1 $end +$var wire 1 ,A in0 $end +$var wire 1 -A in1 $end +$var wire 1 .A in2 $end +$var wire 1 /A in3 $end +$var wire 1 0A nS0 $end +$var wire 1 1A nS1 $end +$var wire 1 2A out $end +$var wire 1 3A out0 $end +$var wire 1 4A out1 $end +$var wire 1 5A out2 $end +$var wire 1 6A out3 $end +$upscope $end +$scope module OneMux $end +$var wire 1 7A S0 $end +$var wire 1 8A S1 $end +$var wire 1 9A in0 $end +$var wire 1 :A in1 $end +$var wire 1 ;A in2 $end +$var wire 1 A nS1 $end +$var wire 1 ?A out $end +$var wire 1 @A out0 $end +$var wire 1 AA out1 $end +$var wire 1 BA out2 $end +$var wire 1 CA out3 $end +$upscope $end +$scope module TwoMux $end +$var wire 1 DA S $end +$var wire 1 EA in0 $end +$var wire 1 FA in1 $end +$var wire 1 GA nS $end +$var wire 1 HA out0 $end +$var wire 1 IA out1 $end +$var wire 1 JA outfinal $end +$upscope $end +$upscope $end +$scope begin muxbits[3] $end +$scope module ZeroMux $end +$var wire 1 KA S0 $end +$var wire 1 LA S1 $end +$var wire 1 MA in0 $end +$var wire 1 NA in1 $end +$var wire 1 OA in2 $end +$var wire 1 PA in3 $end +$var wire 1 QA nS0 $end +$var wire 1 RA nS1 $end +$var wire 1 SA out $end +$var wire 1 TA out0 $end +$var wire 1 UA out1 $end +$var wire 1 VA out2 $end +$var wire 1 WA out3 $end +$upscope $end +$scope module OneMux $end +$var wire 1 XA S0 $end +$var wire 1 YA S1 $end +$var wire 1 ZA in0 $end +$var wire 1 [A in1 $end +$var wire 1 \A in2 $end +$var wire 1 ]A in3 $end +$var wire 1 ^A nS0 $end +$var wire 1 _A nS1 $end +$var wire 1 `A out $end +$var wire 1 aA out0 $end +$var wire 1 bA out1 $end +$var wire 1 cA out2 $end +$var wire 1 dA out3 $end +$upscope $end +$scope module TwoMux $end +$var wire 1 eA S $end +$var wire 1 fA in0 $end +$var wire 1 gA in1 $end +$var wire 1 hA nS $end +$var wire 1 iA out0 $end +$var wire 1 jA out1 $end +$var wire 1 kA outfinal $end +$upscope $end +$upscope $end +$scope begin muxbits[4] $end +$scope module ZeroMux $end +$var wire 1 lA S0 $end +$var wire 1 mA S1 $end +$var wire 1 nA in0 $end +$var wire 1 oA in1 $end +$var wire 1 pA in2 $end +$var wire 1 qA in3 $end +$var wire 1 rA nS0 $end +$var wire 1 sA nS1 $end +$var wire 1 tA out $end +$var wire 1 uA out0 $end +$var wire 1 vA out1 $end +$var wire 1 wA out2 $end +$var wire 1 xA out3 $end +$upscope $end +$scope module OneMux $end +$var wire 1 yA S0 $end +$var wire 1 zA S1 $end +$var wire 1 {A in0 $end +$var wire 1 |A in1 $end +$var wire 1 }A in2 $end +$var wire 1 ~A in3 $end +$var wire 1 !B nS0 $end +$var wire 1 "B nS1 $end +$var wire 1 #B out $end +$var wire 1 $B out0 $end +$var wire 1 %B out1 $end +$var wire 1 &B out2 $end +$var wire 1 'B out3 $end +$upscope $end +$scope module TwoMux $end +$var wire 1 (B S $end +$var wire 1 )B in0 $end +$var wire 1 *B in1 $end +$var wire 1 +B nS $end +$var wire 1 ,B out0 $end +$var wire 1 -B out1 $end +$var wire 1 .B outfinal $end +$upscope $end +$upscope $end +$scope begin muxbits[5] $end +$scope module ZeroMux $end +$var wire 1 /B S0 $end +$var wire 1 0B S1 $end +$var wire 1 1B in0 $end +$var wire 1 2B in1 $end +$var wire 1 3B in2 $end +$var wire 1 4B in3 $end +$var wire 1 5B nS0 $end +$var wire 1 6B nS1 $end +$var wire 1 7B out $end +$var wire 1 8B out0 $end +$var wire 1 9B out1 $end +$var wire 1 :B out2 $end +$var wire 1 ;B out3 $end +$upscope $end +$scope module OneMux $end +$var wire 1 B in0 $end +$var wire 1 ?B in1 $end +$var wire 1 @B in2 $end +$var wire 1 AB in3 $end +$var wire 1 BB nS0 $end +$var wire 1 CB nS1 $end +$var wire 1 DB out $end +$var wire 1 EB out0 $end +$var wire 1 FB out1 $end +$var wire 1 GB out2 $end +$var wire 1 HB out3 $end +$upscope $end +$scope module TwoMux $end +$var wire 1 IB S $end +$var wire 1 JB in0 $end +$var wire 1 KB in1 $end +$var wire 1 LB nS $end +$var wire 1 MB out0 $end +$var wire 1 NB out1 $end +$var wire 1 OB outfinal $end +$upscope $end +$upscope $end +$scope begin muxbits[6] $end +$scope module ZeroMux $end +$var wire 1 PB S0 $end +$var wire 1 QB S1 $end +$var wire 1 RB in0 $end +$var wire 1 SB in1 $end +$var wire 1 TB in2 $end +$var wire 1 UB in3 $end +$var wire 1 VB nS0 $end +$var wire 1 WB nS1 $end +$var wire 1 XB out $end +$var wire 1 YB out0 $end +$var wire 1 ZB out1 $end +$var wire 1 [B out2 $end +$var wire 1 \B out3 $end +$upscope $end +$scope module OneMux $end +$var wire 1 ]B S0 $end +$var wire 1 ^B S1 $end +$var wire 1 _B in0 $end +$var wire 1 `B in1 $end +$var wire 1 aB in2 $end +$var wire 1 bB in3 $end +$var wire 1 cB nS0 $end +$var wire 1 dB nS1 $end +$var wire 1 eB out $end +$var wire 1 fB out0 $end +$var wire 1 gB out1 $end +$var wire 1 hB out2 $end +$var wire 1 iB out3 $end +$upscope $end +$scope module TwoMux $end +$var wire 1 jB S $end +$var wire 1 kB in0 $end +$var wire 1 lB in1 $end +$var wire 1 mB nS $end +$var wire 1 nB out0 $end +$var wire 1 oB out1 $end +$var wire 1 pB outfinal $end +$upscope $end +$upscope $end +$scope begin muxbits[7] $end +$scope module ZeroMux $end +$var wire 1 qB S0 $end +$var wire 1 rB S1 $end +$var wire 1 sB in0 $end +$var wire 1 tB in1 $end +$var wire 1 uB in2 $end +$var wire 1 vB in3 $end +$var wire 1 wB nS0 $end +$var wire 1 xB nS1 $end +$var wire 1 yB out $end +$var wire 1 zB out0 $end +$var wire 1 {B out1 $end +$var wire 1 |B out2 $end +$var wire 1 }B out3 $end +$upscope $end +$scope module OneMux $end +$var wire 1 ~B S0 $end +$var wire 1 !C S1 $end +$var wire 1 "C in0 $end +$var wire 1 #C in1 $end +$var wire 1 $C in2 $end +$var wire 1 %C in3 $end +$var wire 1 &C nS0 $end +$var wire 1 'C nS1 $end +$var wire 1 (C out $end +$var wire 1 )C out0 $end +$var wire 1 *C out1 $end +$var wire 1 +C out2 $end +$var wire 1 ,C out3 $end +$upscope $end +$scope module TwoMux $end +$var wire 1 -C S $end +$var wire 1 .C in0 $end +$var wire 1 /C in1 $end +$var wire 1 0C nS $end +$var wire 1 1C out0 $end +$var wire 1 2C out1 $end +$var wire 1 3C outfinal $end +$upscope $end +$upscope $end +$scope begin muxbits[8] $end +$scope module ZeroMux $end +$var wire 1 4C S0 $end +$var wire 1 5C S1 $end +$var wire 1 6C in0 $end +$var wire 1 7C in1 $end +$var wire 1 8C in2 $end +$var wire 1 9C in3 $end +$var wire 1 :C nS0 $end +$var wire 1 ;C nS1 $end +$var wire 1 C out1 $end +$var wire 1 ?C out2 $end +$var wire 1 @C out3 $end +$upscope $end +$scope module OneMux $end +$var wire 1 AC S0 $end +$var wire 1 BC S1 $end +$var wire 1 CC in0 $end +$var wire 1 DC in1 $end +$var wire 1 EC in2 $end +$var wire 1 FC in3 $end +$var wire 1 GC nS0 $end +$var wire 1 HC nS1 $end +$var wire 1 IC out $end +$var wire 1 JC out0 $end +$var wire 1 KC out1 $end +$var wire 1 LC out2 $end +$var wire 1 MC out3 $end +$upscope $end +$scope module TwoMux $end +$var wire 1 NC S $end +$var wire 1 OC in0 $end +$var wire 1 PC in1 $end +$var wire 1 QC nS $end +$var wire 1 RC out0 $end +$var wire 1 SC out1 $end +$var wire 1 TC outfinal $end +$upscope $end +$upscope $end +$scope begin muxbits[9] $end +$scope module ZeroMux $end +$var wire 1 UC S0 $end +$var wire 1 VC S1 $end +$var wire 1 WC in0 $end +$var wire 1 XC in1 $end +$var wire 1 YC in2 $end +$var wire 1 ZC in3 $end +$var wire 1 [C nS0 $end +$var wire 1 \C nS1 $end +$var wire 1 ]C out $end +$var wire 1 ^C out0 $end +$var wire 1 _C out1 $end +$var wire 1 `C out2 $end +$var wire 1 aC out3 $end +$upscope $end +$scope module OneMux $end +$var wire 1 bC S0 $end +$var wire 1 cC S1 $end +$var wire 1 dC in0 $end +$var wire 1 eC in1 $end +$var wire 1 fC in2 $end +$var wire 1 gC in3 $end +$var wire 1 hC nS0 $end +$var wire 1 iC nS1 $end +$var wire 1 jC out $end +$var wire 1 kC out0 $end +$var wire 1 lC out1 $end +$var wire 1 mC out2 $end +$var wire 1 nC out3 $end +$upscope $end +$scope module TwoMux $end +$var wire 1 oC S $end +$var wire 1 pC in0 $end +$var wire 1 qC in1 $end +$var wire 1 rC nS $end +$var wire 1 sC out0 $end +$var wire 1 tC out1 $end +$var wire 1 uC outfinal $end +$upscope $end +$upscope $end +$scope begin muxbits[10] $end +$scope module ZeroMux $end +$var wire 1 vC S0 $end +$var wire 1 wC S1 $end +$var wire 1 xC in0 $end +$var wire 1 yC in1 $end +$var wire 1 zC in2 $end +$var wire 1 {C in3 $end +$var wire 1 |C nS0 $end +$var wire 1 }C nS1 $end +$var wire 1 ~C out $end +$var wire 1 !D out0 $end +$var wire 1 "D out1 $end +$var wire 1 #D out2 $end +$var wire 1 $D out3 $end +$upscope $end +$scope module OneMux $end +$var wire 1 %D S0 $end +$var wire 1 &D S1 $end +$var wire 1 'D in0 $end +$var wire 1 (D in1 $end +$var wire 1 )D in2 $end +$var wire 1 *D in3 $end +$var wire 1 +D nS0 $end +$var wire 1 ,D nS1 $end +$var wire 1 -D out $end +$var wire 1 .D out0 $end +$var wire 1 /D out1 $end +$var wire 1 0D out2 $end +$var wire 1 1D out3 $end +$upscope $end +$scope module TwoMux $end +$var wire 1 2D S $end +$var wire 1 3D in0 $end +$var wire 1 4D in1 $end +$var wire 1 5D nS $end +$var wire 1 6D out0 $end +$var wire 1 7D out1 $end +$var wire 1 8D outfinal $end +$upscope $end +$upscope $end +$scope begin muxbits[11] $end +$scope module ZeroMux $end +$var wire 1 9D S0 $end +$var wire 1 :D S1 $end +$var wire 1 ;D in0 $end +$var wire 1 D in3 $end +$var wire 1 ?D nS0 $end +$var wire 1 @D nS1 $end +$var wire 1 AD out $end +$var wire 1 BD out0 $end +$var wire 1 CD out1 $end +$var wire 1 DD out2 $end +$var wire 1 ED out3 $end +$upscope $end +$scope module OneMux $end +$var wire 1 FD S0 $end +$var wire 1 GD S1 $end +$var wire 1 HD in0 $end +$var wire 1 ID in1 $end +$var wire 1 JD in2 $end +$var wire 1 KD in3 $end +$var wire 1 LD nS0 $end +$var wire 1 MD nS1 $end +$var wire 1 ND out $end +$var wire 1 OD out0 $end +$var wire 1 PD out1 $end +$var wire 1 QD out2 $end +$var wire 1 RD out3 $end +$upscope $end +$scope module TwoMux $end +$var wire 1 SD S $end +$var wire 1 TD in0 $end +$var wire 1 UD in1 $end +$var wire 1 VD nS $end +$var wire 1 WD out0 $end +$var wire 1 XD out1 $end +$var wire 1 YD outfinal $end +$upscope $end +$upscope $end +$scope begin muxbits[12] $end +$scope module ZeroMux $end +$var wire 1 ZD S0 $end +$var wire 1 [D S1 $end +$var wire 1 \D in0 $end +$var wire 1 ]D in1 $end +$var wire 1 ^D in2 $end +$var wire 1 _D in3 $end +$var wire 1 `D nS0 $end +$var wire 1 aD nS1 $end +$var wire 1 bD out $end +$var wire 1 cD out0 $end +$var wire 1 dD out1 $end +$var wire 1 eD out2 $end +$var wire 1 fD out3 $end +$upscope $end +$scope module OneMux $end +$var wire 1 gD S0 $end +$var wire 1 hD S1 $end +$var wire 1 iD in0 $end +$var wire 1 jD in1 $end +$var wire 1 kD in2 $end +$var wire 1 lD in3 $end +$var wire 1 mD nS0 $end +$var wire 1 nD nS1 $end +$var wire 1 oD out $end +$var wire 1 pD out0 $end +$var wire 1 qD out1 $end +$var wire 1 rD out2 $end +$var wire 1 sD out3 $end +$upscope $end +$scope module TwoMux $end +$var wire 1 tD S $end +$var wire 1 uD in0 $end +$var wire 1 vD in1 $end +$var wire 1 wD nS $end +$var wire 1 xD out0 $end +$var wire 1 yD out1 $end +$var wire 1 zD outfinal $end +$upscope $end +$upscope $end +$scope begin muxbits[13] $end +$scope module ZeroMux $end +$var wire 1 {D S0 $end +$var wire 1 |D S1 $end +$var wire 1 }D in0 $end +$var wire 1 ~D in1 $end +$var wire 1 !E in2 $end +$var wire 1 "E in3 $end +$var wire 1 #E nS0 $end +$var wire 1 $E nS1 $end +$var wire 1 %E out $end +$var wire 1 &E out0 $end +$var wire 1 'E out1 $end +$var wire 1 (E out2 $end +$var wire 1 )E out3 $end +$upscope $end +$scope module OneMux $end +$var wire 1 *E S0 $end +$var wire 1 +E S1 $end +$var wire 1 ,E in0 $end +$var wire 1 -E in1 $end +$var wire 1 .E in2 $end +$var wire 1 /E in3 $end +$var wire 1 0E nS0 $end +$var wire 1 1E nS1 $end +$var wire 1 2E out $end +$var wire 1 3E out0 $end +$var wire 1 4E out1 $end +$var wire 1 5E out2 $end +$var wire 1 6E out3 $end +$upscope $end +$scope module TwoMux $end +$var wire 1 7E S $end +$var wire 1 8E in0 $end +$var wire 1 9E in1 $end +$var wire 1 :E nS $end +$var wire 1 ;E out0 $end +$var wire 1 E S0 $end +$var wire 1 ?E S1 $end +$var wire 1 @E in0 $end +$var wire 1 AE in1 $end +$var wire 1 BE in2 $end +$var wire 1 CE in3 $end +$var wire 1 DE nS0 $end +$var wire 1 EE nS1 $end +$var wire 1 FE out $end +$var wire 1 GE out0 $end +$var wire 1 HE out1 $end +$var wire 1 IE out2 $end +$var wire 1 JE out3 $end +$upscope $end +$scope module OneMux $end +$var wire 1 KE S0 $end +$var wire 1 LE S1 $end +$var wire 1 ME in0 $end +$var wire 1 NE in1 $end +$var wire 1 OE in2 $end +$var wire 1 PE in3 $end +$var wire 1 QE nS0 $end +$var wire 1 RE nS1 $end +$var wire 1 SE out $end +$var wire 1 TE out0 $end +$var wire 1 UE out1 $end +$var wire 1 VE out2 $end +$var wire 1 WE out3 $end +$upscope $end +$scope module TwoMux $end +$var wire 1 XE S $end +$var wire 1 YE in0 $end +$var wire 1 ZE in1 $end +$var wire 1 [E nS $end +$var wire 1 \E out0 $end +$var wire 1 ]E out1 $end +$var wire 1 ^E outfinal $end +$upscope $end +$upscope $end +$scope begin muxbits[15] $end +$scope module ZeroMux $end +$var wire 1 _E S0 $end +$var wire 1 `E S1 $end +$var wire 1 aE in0 $end +$var wire 1 bE in1 $end +$var wire 1 cE in2 $end +$var wire 1 dE in3 $end +$var wire 1 eE nS0 $end +$var wire 1 fE nS1 $end +$var wire 1 gE out $end +$var wire 1 hE out0 $end +$var wire 1 iE out1 $end +$var wire 1 jE out2 $end +$var wire 1 kE out3 $end +$upscope $end +$scope module OneMux $end +$var wire 1 lE S0 $end +$var wire 1 mE S1 $end +$var wire 1 nE in0 $end +$var wire 1 oE in1 $end +$var wire 1 pE in2 $end +$var wire 1 qE in3 $end +$var wire 1 rE nS0 $end +$var wire 1 sE nS1 $end +$var wire 1 tE out $end +$var wire 1 uE out0 $end +$var wire 1 vE out1 $end +$var wire 1 wE out2 $end +$var wire 1 xE out3 $end +$upscope $end +$scope module TwoMux $end +$var wire 1 yE S $end +$var wire 1 zE in0 $end +$var wire 1 {E in1 $end +$var wire 1 |E nS $end +$var wire 1 }E out0 $end +$var wire 1 ~E out1 $end +$var wire 1 !F outfinal $end +$upscope $end +$upscope $end +$scope begin muxbits[16] $end +$scope module ZeroMux $end +$var wire 1 "F S0 $end +$var wire 1 #F S1 $end +$var wire 1 $F in0 $end +$var wire 1 %F in1 $end +$var wire 1 &F in2 $end +$var wire 1 'F in3 $end +$var wire 1 (F nS0 $end +$var wire 1 )F nS1 $end +$var wire 1 *F out $end +$var wire 1 +F out0 $end +$var wire 1 ,F out1 $end +$var wire 1 -F out2 $end +$var wire 1 .F out3 $end +$upscope $end +$scope module OneMux $end +$var wire 1 /F S0 $end +$var wire 1 0F S1 $end +$var wire 1 1F in0 $end +$var wire 1 2F in1 $end +$var wire 1 3F in2 $end +$var wire 1 4F in3 $end +$var wire 1 5F nS0 $end +$var wire 1 6F nS1 $end +$var wire 1 7F out $end +$var wire 1 8F out0 $end +$var wire 1 9F out1 $end +$var wire 1 :F out2 $end +$var wire 1 ;F out3 $end +$upscope $end +$scope module TwoMux $end +$var wire 1 F in1 $end +$var wire 1 ?F nS $end +$var wire 1 @F out0 $end +$var wire 1 AF out1 $end +$var wire 1 BF outfinal $end +$upscope $end +$upscope $end +$scope begin muxbits[17] $end +$scope module ZeroMux $end +$var wire 1 CF S0 $end +$var wire 1 DF S1 $end +$var wire 1 EF in0 $end +$var wire 1 FF in1 $end +$var wire 1 GF in2 $end +$var wire 1 HF in3 $end +$var wire 1 IF nS0 $end +$var wire 1 JF nS1 $end +$var wire 1 KF out $end +$var wire 1 LF out0 $end +$var wire 1 MF out1 $end +$var wire 1 NF out2 $end +$var wire 1 OF out3 $end +$upscope $end +$scope module OneMux $end +$var wire 1 PF S0 $end +$var wire 1 QF S1 $end +$var wire 1 RF in0 $end +$var wire 1 SF in1 $end +$var wire 1 TF in2 $end +$var wire 1 UF in3 $end +$var wire 1 VF nS0 $end +$var wire 1 WF nS1 $end +$var wire 1 XF out $end +$var wire 1 YF out0 $end +$var wire 1 ZF out1 $end +$var wire 1 [F out2 $end +$var wire 1 \F out3 $end +$upscope $end +$scope module TwoMux $end +$var wire 1 ]F S $end +$var wire 1 ^F in0 $end +$var wire 1 _F in1 $end +$var wire 1 `F nS $end +$var wire 1 aF out0 $end +$var wire 1 bF out1 $end +$var wire 1 cF outfinal $end +$upscope $end +$upscope $end +$scope begin muxbits[18] $end +$scope module ZeroMux $end +$var wire 1 dF S0 $end +$var wire 1 eF S1 $end +$var wire 1 fF in0 $end +$var wire 1 gF in1 $end +$var wire 1 hF in2 $end +$var wire 1 iF in3 $end +$var wire 1 jF nS0 $end +$var wire 1 kF nS1 $end +$var wire 1 lF out $end +$var wire 1 mF out0 $end +$var wire 1 nF out1 $end +$var wire 1 oF out2 $end +$var wire 1 pF out3 $end +$upscope $end +$scope module OneMux $end +$var wire 1 qF S0 $end +$var wire 1 rF S1 $end +$var wire 1 sF in0 $end +$var wire 1 tF in1 $end +$var wire 1 uF in2 $end +$var wire 1 vF in3 $end +$var wire 1 wF nS0 $end +$var wire 1 xF nS1 $end +$var wire 1 yF out $end +$var wire 1 zF out0 $end +$var wire 1 {F out1 $end +$var wire 1 |F out2 $end +$var wire 1 }F out3 $end +$upscope $end +$scope module TwoMux $end +$var wire 1 ~F S $end +$var wire 1 !G in0 $end +$var wire 1 "G in1 $end +$var wire 1 #G nS $end +$var wire 1 $G out0 $end +$var wire 1 %G out1 $end +$var wire 1 &G outfinal $end +$upscope $end +$upscope $end +$scope begin muxbits[19] $end +$scope module ZeroMux $end +$var wire 1 'G S0 $end +$var wire 1 (G S1 $end +$var wire 1 )G in0 $end +$var wire 1 *G in1 $end +$var wire 1 +G in2 $end +$var wire 1 ,G in3 $end +$var wire 1 -G nS0 $end +$var wire 1 .G nS1 $end +$var wire 1 /G out $end +$var wire 1 0G out0 $end +$var wire 1 1G out1 $end +$var wire 1 2G out2 $end +$var wire 1 3G out3 $end +$upscope $end +$scope module OneMux $end +$var wire 1 4G S0 $end +$var wire 1 5G S1 $end +$var wire 1 6G in0 $end +$var wire 1 7G in1 $end +$var wire 1 8G in2 $end +$var wire 1 9G in3 $end +$var wire 1 :G nS0 $end +$var wire 1 ;G nS1 $end +$var wire 1 G out1 $end +$var wire 1 ?G out2 $end +$var wire 1 @G out3 $end +$upscope $end +$scope module TwoMux $end +$var wire 1 AG S $end +$var wire 1 BG in0 $end +$var wire 1 CG in1 $end +$var wire 1 DG nS $end +$var wire 1 EG out0 $end +$var wire 1 FG out1 $end +$var wire 1 GG outfinal $end +$upscope $end +$upscope $end +$scope begin muxbits[20] $end +$scope module ZeroMux $end +$var wire 1 HG S0 $end +$var wire 1 IG S1 $end +$var wire 1 JG in0 $end +$var wire 1 KG in1 $end +$var wire 1 LG in2 $end +$var wire 1 MG in3 $end +$var wire 1 NG nS0 $end +$var wire 1 OG nS1 $end +$var wire 1 PG out $end +$var wire 1 QG out0 $end +$var wire 1 RG out1 $end +$var wire 1 SG out2 $end +$var wire 1 TG out3 $end +$upscope $end +$scope module OneMux $end +$var wire 1 UG S0 $end +$var wire 1 VG S1 $end +$var wire 1 WG in0 $end +$var wire 1 XG in1 $end +$var wire 1 YG in2 $end +$var wire 1 ZG in3 $end +$var wire 1 [G nS0 $end +$var wire 1 \G nS1 $end +$var wire 1 ]G out $end +$var wire 1 ^G out0 $end +$var wire 1 _G out1 $end +$var wire 1 `G out2 $end +$var wire 1 aG out3 $end +$upscope $end +$scope module TwoMux $end +$var wire 1 bG S $end +$var wire 1 cG in0 $end +$var wire 1 dG in1 $end +$var wire 1 eG nS $end +$var wire 1 fG out0 $end +$var wire 1 gG out1 $end +$var wire 1 hG outfinal $end +$upscope $end +$upscope $end +$scope begin muxbits[21] $end +$scope module ZeroMux $end +$var wire 1 iG S0 $end +$var wire 1 jG S1 $end +$var wire 1 kG in0 $end +$var wire 1 lG in1 $end +$var wire 1 mG in2 $end +$var wire 1 nG in3 $end +$var wire 1 oG nS0 $end +$var wire 1 pG nS1 $end +$var wire 1 qG out $end +$var wire 1 rG out0 $end +$var wire 1 sG out1 $end +$var wire 1 tG out2 $end +$var wire 1 uG out3 $end +$upscope $end +$scope module OneMux $end +$var wire 1 vG S0 $end +$var wire 1 wG S1 $end +$var wire 1 xG in0 $end +$var wire 1 yG in1 $end +$var wire 1 zG in2 $end +$var wire 1 {G in3 $end +$var wire 1 |G nS0 $end +$var wire 1 }G nS1 $end +$var wire 1 ~G out $end +$var wire 1 !H out0 $end +$var wire 1 "H out1 $end +$var wire 1 #H out2 $end +$var wire 1 $H out3 $end +$upscope $end +$scope module TwoMux $end +$var wire 1 %H S $end +$var wire 1 &H in0 $end +$var wire 1 'H in1 $end +$var wire 1 (H nS $end +$var wire 1 )H out0 $end +$var wire 1 *H out1 $end +$var wire 1 +H outfinal $end +$upscope $end +$upscope $end +$scope begin muxbits[22] $end +$scope module ZeroMux $end +$var wire 1 ,H S0 $end +$var wire 1 -H S1 $end +$var wire 1 .H in0 $end +$var wire 1 /H in1 $end +$var wire 1 0H in2 $end +$var wire 1 1H in3 $end +$var wire 1 2H nS0 $end +$var wire 1 3H nS1 $end +$var wire 1 4H out $end +$var wire 1 5H out0 $end +$var wire 1 6H out1 $end +$var wire 1 7H out2 $end +$var wire 1 8H out3 $end +$upscope $end +$scope module OneMux $end +$var wire 1 9H S0 $end +$var wire 1 :H S1 $end +$var wire 1 ;H in0 $end +$var wire 1 H in3 $end +$var wire 1 ?H nS0 $end +$var wire 1 @H nS1 $end +$var wire 1 AH out $end +$var wire 1 BH out0 $end +$var wire 1 CH out1 $end +$var wire 1 DH out2 $end +$var wire 1 EH out3 $end +$upscope $end +$scope module TwoMux $end +$var wire 1 FH S $end +$var wire 1 GH in0 $end +$var wire 1 HH in1 $end +$var wire 1 IH nS $end +$var wire 1 JH out0 $end +$var wire 1 KH out1 $end +$var wire 1 LH outfinal $end +$upscope $end +$upscope $end +$scope begin muxbits[23] $end +$scope module ZeroMux $end +$var wire 1 MH S0 $end +$var wire 1 NH S1 $end +$var wire 1 OH in0 $end +$var wire 1 PH in1 $end +$var wire 1 QH in2 $end +$var wire 1 RH in3 $end +$var wire 1 SH nS0 $end +$var wire 1 TH nS1 $end +$var wire 1 UH out $end +$var wire 1 VH out0 $end +$var wire 1 WH out1 $end +$var wire 1 XH out2 $end +$var wire 1 YH out3 $end +$upscope $end +$scope module OneMux $end +$var wire 1 ZH S0 $end +$var wire 1 [H S1 $end +$var wire 1 \H in0 $end +$var wire 1 ]H in1 $end +$var wire 1 ^H in2 $end +$var wire 1 _H in3 $end +$var wire 1 `H nS0 $end +$var wire 1 aH nS1 $end +$var wire 1 bH out $end +$var wire 1 cH out0 $end +$var wire 1 dH out1 $end +$var wire 1 eH out2 $end +$var wire 1 fH out3 $end +$upscope $end +$scope module TwoMux $end +$var wire 1 gH S $end +$var wire 1 hH in0 $end +$var wire 1 iH in1 $end +$var wire 1 jH nS $end +$var wire 1 kH out0 $end +$var wire 1 lH out1 $end +$var wire 1 mH outfinal $end +$upscope $end +$upscope $end +$scope begin muxbits[24] $end +$scope module ZeroMux $end +$var wire 1 nH S0 $end +$var wire 1 oH S1 $end +$var wire 1 pH in0 $end +$var wire 1 qH in1 $end +$var wire 1 rH in2 $end +$var wire 1 sH in3 $end +$var wire 1 tH nS0 $end +$var wire 1 uH nS1 $end +$var wire 1 vH out $end +$var wire 1 wH out0 $end +$var wire 1 xH out1 $end +$var wire 1 yH out2 $end +$var wire 1 zH out3 $end +$upscope $end +$scope module OneMux $end +$var wire 1 {H S0 $end +$var wire 1 |H S1 $end +$var wire 1 }H in0 $end +$var wire 1 ~H in1 $end +$var wire 1 !I in2 $end +$var wire 1 "I in3 $end +$var wire 1 #I nS0 $end +$var wire 1 $I nS1 $end +$var wire 1 %I out $end +$var wire 1 &I out0 $end +$var wire 1 'I out1 $end +$var wire 1 (I out2 $end +$var wire 1 )I out3 $end +$upscope $end +$scope module TwoMux $end +$var wire 1 *I S $end +$var wire 1 +I in0 $end +$var wire 1 ,I in1 $end +$var wire 1 -I nS $end +$var wire 1 .I out0 $end +$var wire 1 /I out1 $end +$var wire 1 0I outfinal $end +$upscope $end +$upscope $end +$scope begin muxbits[25] $end +$scope module ZeroMux $end +$var wire 1 1I S0 $end +$var wire 1 2I S1 $end +$var wire 1 3I in0 $end +$var wire 1 4I in1 $end +$var wire 1 5I in2 $end +$var wire 1 6I in3 $end +$var wire 1 7I nS0 $end +$var wire 1 8I nS1 $end +$var wire 1 9I out $end +$var wire 1 :I out0 $end +$var wire 1 ;I out1 $end +$var wire 1 I S0 $end +$var wire 1 ?I S1 $end +$var wire 1 @I in0 $end +$var wire 1 AI in1 $end +$var wire 1 BI in2 $end +$var wire 1 CI in3 $end +$var wire 1 DI nS0 $end +$var wire 1 EI nS1 $end +$var wire 1 FI out $end +$var wire 1 GI out0 $end +$var wire 1 HI out1 $end +$var wire 1 II out2 $end +$var wire 1 JI out3 $end +$upscope $end +$scope module TwoMux $end +$var wire 1 KI S $end +$var wire 1 LI in0 $end +$var wire 1 MI in1 $end +$var wire 1 NI nS $end +$var wire 1 OI out0 $end +$var wire 1 PI out1 $end +$var wire 1 QI outfinal $end +$upscope $end +$upscope $end +$scope begin muxbits[26] $end +$scope module ZeroMux $end +$var wire 1 RI S0 $end +$var wire 1 SI S1 $end +$var wire 1 TI in0 $end +$var wire 1 UI in1 $end +$var wire 1 VI in2 $end +$var wire 1 WI in3 $end +$var wire 1 XI nS0 $end +$var wire 1 YI nS1 $end +$var wire 1 ZI out $end +$var wire 1 [I out0 $end +$var wire 1 \I out1 $end +$var wire 1 ]I out2 $end +$var wire 1 ^I out3 $end +$upscope $end +$scope module OneMux $end +$var wire 1 _I S0 $end +$var wire 1 `I S1 $end +$var wire 1 aI in0 $end +$var wire 1 bI in1 $end +$var wire 1 cI in2 $end +$var wire 1 dI in3 $end +$var wire 1 eI nS0 $end +$var wire 1 fI nS1 $end +$var wire 1 gI out $end +$var wire 1 hI out0 $end +$var wire 1 iI out1 $end +$var wire 1 jI out2 $end +$var wire 1 kI out3 $end +$upscope $end +$scope module TwoMux $end +$var wire 1 lI S $end +$var wire 1 mI in0 $end +$var wire 1 nI in1 $end +$var wire 1 oI nS $end +$var wire 1 pI out0 $end +$var wire 1 qI out1 $end +$var wire 1 rI outfinal $end +$upscope $end +$upscope $end +$scope begin muxbits[27] $end +$scope module ZeroMux $end +$var wire 1 sI S0 $end +$var wire 1 tI S1 $end +$var wire 1 uI in0 $end +$var wire 1 vI in1 $end +$var wire 1 wI in2 $end +$var wire 1 xI in3 $end +$var wire 1 yI nS0 $end +$var wire 1 zI nS1 $end +$var wire 1 {I out $end +$var wire 1 |I out0 $end +$var wire 1 }I out1 $end +$var wire 1 ~I out2 $end +$var wire 1 !J out3 $end +$upscope $end +$scope module OneMux $end +$var wire 1 "J S0 $end +$var wire 1 #J S1 $end +$var wire 1 $J in0 $end +$var wire 1 %J in1 $end +$var wire 1 &J in2 $end +$var wire 1 'J in3 $end +$var wire 1 (J nS0 $end +$var wire 1 )J nS1 $end +$var wire 1 *J out $end +$var wire 1 +J out0 $end +$var wire 1 ,J out1 $end +$var wire 1 -J out2 $end +$var wire 1 .J out3 $end +$upscope $end +$scope module TwoMux $end +$var wire 1 /J S $end +$var wire 1 0J in0 $end +$var wire 1 1J in1 $end +$var wire 1 2J nS $end +$var wire 1 3J out0 $end +$var wire 1 4J out1 $end +$var wire 1 5J outfinal $end +$upscope $end +$upscope $end +$scope begin muxbits[28] $end +$scope module ZeroMux $end +$var wire 1 6J S0 $end +$var wire 1 7J S1 $end +$var wire 1 8J in0 $end +$var wire 1 9J in1 $end +$var wire 1 :J in2 $end +$var wire 1 ;J in3 $end +$var wire 1 J out $end +$var wire 1 ?J out0 $end +$var wire 1 @J out1 $end +$var wire 1 AJ out2 $end +$var wire 1 BJ out3 $end +$upscope $end +$scope module OneMux $end +$var wire 1 CJ S0 $end +$var wire 1 DJ S1 $end +$var wire 1 EJ in0 $end +$var wire 1 FJ in1 $end +$var wire 1 GJ in2 $end +$var wire 1 HJ in3 $end +$var wire 1 IJ nS0 $end +$var wire 1 JJ nS1 $end +$var wire 1 KJ out $end +$var wire 1 LJ out0 $end +$var wire 1 MJ out1 $end +$var wire 1 NJ out2 $end +$var wire 1 OJ out3 $end +$upscope $end +$scope module TwoMux $end +$var wire 1 PJ S $end +$var wire 1 QJ in0 $end +$var wire 1 RJ in1 $end +$var wire 1 SJ nS $end +$var wire 1 TJ out0 $end +$var wire 1 UJ out1 $end +$var wire 1 VJ outfinal $end +$upscope $end +$upscope $end +$scope begin muxbits[29] $end +$scope module ZeroMux $end +$var wire 1 WJ S0 $end +$var wire 1 XJ S1 $end +$var wire 1 YJ in0 $end +$var wire 1 ZJ in1 $end +$var wire 1 [J in2 $end +$var wire 1 \J in3 $end +$var wire 1 ]J nS0 $end +$var wire 1 ^J nS1 $end +$var wire 1 _J out $end +$var wire 1 `J out0 $end +$var wire 1 aJ out1 $end +$var wire 1 bJ out2 $end +$var wire 1 cJ out3 $end +$upscope $end +$scope module OneMux $end +$var wire 1 dJ S0 $end +$var wire 1 eJ S1 $end +$var wire 1 fJ in0 $end +$var wire 1 gJ in1 $end +$var wire 1 hJ in2 $end +$var wire 1 iJ in3 $end +$var wire 1 jJ nS0 $end +$var wire 1 kJ nS1 $end +$var wire 1 lJ out $end +$var wire 1 mJ out0 $end +$var wire 1 nJ out1 $end +$var wire 1 oJ out2 $end +$var wire 1 pJ out3 $end +$upscope $end +$scope module TwoMux $end +$var wire 1 qJ S $end +$var wire 1 rJ in0 $end +$var wire 1 sJ in1 $end +$var wire 1 tJ nS $end +$var wire 1 uJ out0 $end +$var wire 1 vJ out1 $end +$var wire 1 wJ outfinal $end +$upscope $end +$upscope $end +$scope begin muxbits[30] $end +$scope module ZeroMux $end +$var wire 1 xJ S0 $end +$var wire 1 yJ S1 $end +$var wire 1 zJ in0 $end +$var wire 1 {J in1 $end +$var wire 1 |J in2 $end +$var wire 1 }J in3 $end +$var wire 1 ~J nS0 $end +$var wire 1 !K nS1 $end +$var wire 1 "K out $end +$var wire 1 #K out0 $end +$var wire 1 $K out1 $end +$var wire 1 %K out2 $end +$var wire 1 &K out3 $end +$upscope $end +$scope module OneMux $end +$var wire 1 'K S0 $end +$var wire 1 (K S1 $end +$var wire 1 )K in0 $end +$var wire 1 *K in1 $end +$var wire 1 +K in2 $end +$var wire 1 ,K in3 $end +$var wire 1 -K nS0 $end +$var wire 1 .K nS1 $end +$var wire 1 /K out $end +$var wire 1 0K out0 $end +$var wire 1 1K out1 $end +$var wire 1 2K out2 $end +$var wire 1 3K out3 $end +$upscope $end +$scope module TwoMux $end +$var wire 1 4K S $end +$var wire 1 5K in0 $end +$var wire 1 6K in1 $end +$var wire 1 7K nS $end +$var wire 1 8K out0 $end +$var wire 1 9K out1 $end +$var wire 1 :K outfinal $end +$upscope $end +$upscope $end +$scope begin muxbits[31] $end +$scope module ZeroMux $end +$var wire 1 ;K S0 $end +$var wire 1 K in1 $end +$var wire 1 ?K in2 $end +$var wire 1 @K in3 $end +$var wire 1 AK nS0 $end +$var wire 1 BK nS1 $end +$var wire 1 CK out $end +$var wire 1 DK out0 $end +$var wire 1 EK out1 $end +$var wire 1 FK out2 $end +$var wire 1 GK out3 $end +$upscope $end +$scope module OneMux $end +$var wire 1 HK S0 $end +$var wire 1 IK S1 $end +$var wire 1 JK in0 $end +$var wire 1 KK in1 $end +$var wire 1 LK in2 $end +$var wire 1 MK in3 $end +$var wire 1 NK nS0 $end +$var wire 1 OK nS1 $end +$var wire 1 PK out $end +$var wire 1 QK out0 $end +$var wire 1 RK out1 $end +$var wire 1 SK out2 $end +$var wire 1 TK out3 $end +$upscope $end +$scope module TwoMux $end +$var wire 1 UK S $end +$var wire 1 VK in0 $end +$var wire 1 WK in1 $end +$var wire 1 XK nS $end +$var wire 1 YK out0 $end +$var wire 1 ZK out1 $end +$var wire 1 [K outfinal $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$enddefinitions $end +#0 +$dumpvars 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+b10000000000000000000000000000000 ' +b10000000000000000000000000000000 l0 +#61380000 +17 +1x0 +#61390000 +0[K +b0 $ +b0 j0 +0) +#61400000 +1; +1|0 +1& +#61410000 +b0 ' +b0 l0 +04 +0u0 +#61420000 +1o0 +#61430000 +07 +0x0 +#61440000 +1" +#61450000 +0& From 05282f1960a406d4391373e352a0d0651afed1e5 Mon Sep 17 00:00:00 2001 From: mjakus Date: Tue, 10 Oct 2017 14:52:01 -0400 Subject: [PATCH 21/28] Testing time --- test | 23462 +++++++++++++++++++------------------------------- testing.t.v | 8 +- 2 files changed, 9045 insertions(+), 14425 deletions(-) diff --git a/test b/test index a94d207..7da9118 100755 --- a/test +++ b/test @@ -4,14484 +4,9100 @@ :vpi_module "system"; :vpi_module "v2005_math"; :vpi_module "va_math"; -S_0x270e6d0 .scope module, "test32Adder" "test32Adder" 2 122; - .timescale -9 -12; -P_0x2665ab8 .param/l "size" 2 123, +C4<0100000>; -v0x2bc7660_0 .var "A", 31 0; -RS_0x7f99c4320aa8/0/0 .resolv tri, L_0x2bc8d00, L_0x2bca3f0, L_0x2bcb830, L_0x2bccdf0; -RS_0x7f99c4320aa8/0/4 .resolv tri, L_0x2bce390, L_0x2bcf9c0, L_0x2bd0ee0, L_0x2bd2400; -RS_0x7f99c4320aa8/0/8 .resolv tri, L_0x2bd3a10, L_0x2bd5120, L_0x2bd6630, L_0x2bd7b40; -RS_0x7f99c4320aa8/0/12 .resolv tri, L_0x2bd9040, L_0x2bda740, L_0x2bdbc50, L_0x2bdd150; -RS_0x7f99c4320aa8/0/16 .resolv tri, L_0x2bde740, L_0x2bdfbb0, L_0x2b875a0, L_0x2be3560; -RS_0x7f99c4320aa8/0/20 .resolv tri, L_0x2be4920, L_0x2be5cf0, L_0x2be70b0, L_0x2be8570; -RS_0x7f99c4320aa8/0/24 .resolv tri, L_0x2be9a60, L_0x2beb340, L_0x2bec820, L_0x2bedd20; -RS_0x7f99c4320aa8/0/28 .resolv tri, L_0x2bef210, L_0x2bf0b00, L_0x2bf1ff0, L_0x2bf34e0; -RS_0x7f99c4320aa8/0/32 .resolv tri, L_0x2c806a0, L_0x2c83eb0, L_0x2c852b0, L_0x2c86790; -RS_0x7f99c4320aa8/0/36 .resolv tri, L_0x2c87c30, L_0x2c89020, L_0x2c8a420, L_0x2c8b880; -RS_0x7f99c4320aa8/0/40 .resolv tri, L_0x2c8ce90, L_0x2c8e3a0, L_0x2c8f8b0, L_0x2c90dc0; -RS_0x7f99c4320aa8/0/44 .resolv tri, L_0x2c921d0, L_0x2c93620, L_0x2c94a90, L_0x2c95f10; -RS_0x7f99c4320aa8/0/48 .resolv tri, L_0x2c975d0, L_0x2c98a40, L_0x2c99ef0, L_0x2c9b360; -RS_0x7f99c4320aa8/0/52 .resolv tri, L_0x2c9c860, L_0x2c9dd70, L_0x2c9f130, L_0x2ca05b0; -RS_0x7f99c4320aa8/0/56 .resolv tri, L_0x2ca1aa0, L_0x2c062e0, L_0x2ca5450, L_0x2ca6d40; -RS_0x7f99c4320aa8/0/60 .resolv tri, L_0x2ca8230, L_0x2ca9730, L_0x2caac20, L_0x2cac110; -RS_0x7f99c4320aa8/1/0 .resolv tri, RS_0x7f99c4320aa8/0/0, RS_0x7f99c4320aa8/0/4, RS_0x7f99c4320aa8/0/8, RS_0x7f99c4320aa8/0/12; -RS_0x7f99c4320aa8/1/4 .resolv tri, RS_0x7f99c4320aa8/0/16, RS_0x7f99c4320aa8/0/20, RS_0x7f99c4320aa8/0/24, RS_0x7f99c4320aa8/0/28; -RS_0x7f99c4320aa8/1/8 .resolv tri, RS_0x7f99c4320aa8/0/32, RS_0x7f99c4320aa8/0/36, RS_0x7f99c4320aa8/0/40, RS_0x7f99c4320aa8/0/44; -RS_0x7f99c4320aa8/1/12 .resolv tri, RS_0x7f99c4320aa8/0/48, RS_0x7f99c4320aa8/0/52, RS_0x7f99c4320aa8/0/56, RS_0x7f99c4320aa8/0/60; -RS_0x7f99c4320aa8 .resolv tri, RS_0x7f99c4320aa8/1/0, RS_0x7f99c4320aa8/1/4, RS_0x7f99c4320aa8/1/8, RS_0x7f99c4320aa8/1/12; -v0x2bc76e0_0 .net8 "AddSubSLTSum", 31 0, RS_0x7f99c4320aa8; 64 drivers -v0x2bc7760_0 .net "AllZeros", 0 0, L_0x2c43980; 1 drivers -RS_0x7f99c4319e78/0/0 .resolv tri, L_0x2bf56a0, L_0x2bf6150, L_0x2bf6bc0, L_0x2bf7620; -RS_0x7f99c4319e78/0/4 .resolv tri, L_0x2bf8090, L_0x2bf8bf0, L_0x2bf9660, L_0x2bfa0c0; -RS_0x7f99c4319e78/0/8 .resolv tri, L_0x2bfab40, L_0x2bfb5b0, L_0x2bfc020, L_0x2bfca90; -RS_0x7f99c4319e78/0/12 .resolv tri, L_0x2bfd510, L_0x2bfe080, L_0x2bfeaf0, L_0x2bff560; -RS_0x7f99c4319e78/0/16 .resolv tri, L_0x2bfffe0, L_0x2c00a40, L_0x2c014c0, L_0x2c01f20; -RS_0x7f99c4319e78/0/20 .resolv tri, L_0x2c02990, L_0x2c03400, L_0x2c03e80, L_0x2c048e0; -RS_0x7f99c4319e78/0/24 .resolv tri, L_0x2c05350, L_0x2c06550, L_0x2c06ee0, L_0x2c07890; -RS_0x7f99c4319e78/0/28 .resolv tri, L_0x2c08250, L_0x2c08e10, L_0x2c097c0, L_0x2c0a170; -RS_0x7f99c4319e78/0/32 .resolv tri, L_0x2cae270, L_0x2caece0, L_0x2caf750, L_0x2cb01b0; -RS_0x7f99c4319e78/0/36 .resolv tri, L_0x2cb0c20, L_0x2cb16f0, L_0x2cb21f0, L_0x2cb2c50; -RS_0x7f99c4319e78/0/40 .resolv tri, L_0x2cb3540, L_0x2cb3ed0, L_0x2cb4880, L_0x2cb52f0; -RS_0x7f99c4319e78/0/44 .resolv tri, L_0x2cb5d70, L_0x2cb6810, L_0x2cb72c0, L_0x2cb7d70; -RS_0x7f99c4319e78/0/48 .resolv tri, L_0x2cb8830, L_0x2cb92d0, L_0x2cb9d90, L_0x2cba7f0; -RS_0x7f99c4319e78/0/52 .resolv tri, L_0x2cbb260, L_0x2cbbcd0, L_0x2cbc750, L_0x2cbd1b0; -RS_0x7f99c4319e78/0/56 .resolv tri, L_0x2cbdc20, L_0x2cbe640, L_0x2cbf110, L_0x2cbfbc0; -RS_0x7f99c4319e78/0/60 .resolv tri, L_0x2cc0640, L_0x2cc10a0, L_0x2cc1b10, L_0x2cc2c60; -RS_0x7f99c4319e78/1/0 .resolv tri, RS_0x7f99c4319e78/0/0, RS_0x7f99c4319e78/0/4, RS_0x7f99c4319e78/0/8, RS_0x7f99c4319e78/0/12; -RS_0x7f99c4319e78/1/4 .resolv tri, RS_0x7f99c4319e78/0/16, RS_0x7f99c4319e78/0/20, RS_0x7f99c4319e78/0/24, RS_0x7f99c4319e78/0/28; -RS_0x7f99c4319e78/1/8 .resolv tri, RS_0x7f99c4319e78/0/32, RS_0x7f99c4319e78/0/36, RS_0x7f99c4319e78/0/40, RS_0x7f99c4319e78/0/44; -RS_0x7f99c4319e78/1/12 .resolv tri, RS_0x7f99c4319e78/0/48, RS_0x7f99c4319e78/0/52, RS_0x7f99c4319e78/0/56, RS_0x7f99c4319e78/0/60; -RS_0x7f99c4319e78 .resolv tri, RS_0x7f99c4319e78/1/0, RS_0x7f99c4319e78/1/4, RS_0x7f99c4319e78/1/8, RS_0x7f99c4319e78/1/12; -v0x2bc77e0_0 .net8 "AndNandOut", 31 0, RS_0x7f99c4319e78; 64 drivers -v0x2bc7860_0 .var "B", 31 0; -v0x2bc78e0_0 .var "Command", 2 0; -RS_0x7f99c4320f28/0/0 .resolv tri, L_0x2c32350, L_0x2c34c80, L_0x2c37620, L_0x2c39df0; -RS_0x7f99c4320f28/0/4 .resolv tri, L_0x2c3c860, L_0x2c3f020, L_0x2c40fb0, L_0x2c43da0; -RS_0x7f99c4320f28/0/8 .resolv tri, L_0x2c46d50, L_0x2c2ca00, L_0x2c4c090, L_0x2c4e800; -RS_0x7f99c4320f28/0/12 .resolv tri, L_0x2c50fd0, L_0x2c526f0, L_0x2c54cb0, L_0x2c57a10; -RS_0x7f99c4320f28/0/16 .resolv tri, L_0x2c5ac10, L_0x2c5d140, L_0x2c5fb10, L_0x2c62240; -RS_0x7f99c4320f28/0/20 .resolv tri, L_0x2c64780, L_0x2c66f10, L_0x2c68f10, L_0x2c6b5a0; -RS_0x7f99c4320f28/0/24 .resolv tri, L_0x2be0b30, L_0x2c73e60, L_0x2c76620, L_0x2c78db0; -RS_0x7f99c4320f28/0/28 .resolv tri, L_0x2c7b5e0, L_0x2c7c950, L_0x2c49690, L_0x2cea940; -RS_0x7f99c4320f28/1/0 .resolv tri, RS_0x7f99c4320f28/0/0, RS_0x7f99c4320f28/0/4, RS_0x7f99c4320f28/0/8, RS_0x7f99c4320f28/0/12; -RS_0x7f99c4320f28/1/4 .resolv tri, RS_0x7f99c4320f28/0/16, RS_0x7f99c4320f28/0/20, RS_0x7f99c4320f28/0/24, RS_0x7f99c4320f28/0/28; -RS_0x7f99c4320f28 .resolv tri, RS_0x7f99c4320f28/1/0, RS_0x7f99c4320f28/1/4, C4, C4; -v0x2bc7960_0 .net8 "OneBitFinalOut", 31 0, RS_0x7f99c4320f28; 32 drivers -RS_0x7f99c4316848/0/0 .resolv tri, L_0x2c0b350, L_0x2c0c590, L_0x2c0d7c0, L_0x2c0ea70; -RS_0x7f99c4316848/0/4 .resolv tri, L_0x2c0fd70, L_0x2c11160, L_0x2c12460, L_0x2c13750; -RS_0x7f99c4316848/0/8 .resolv tri, L_0x2c14a60, L_0x2c15d60, L_0x2c17060, L_0x2c18350; -RS_0x7f99c4316848/0/12 .resolv tri, L_0x2c19670, L_0x2c1aa80, L_0x2c1bd80, L_0x2c1d070; -RS_0x7f99c4316848/0/16 .resolv tri, L_0x2c1e380, L_0x2c1f670, L_0x2c20970, L_0x2c21c70; -RS_0x7f99c4316848/0/20 .resolv tri, L_0x2c22f80, L_0x2c24270, L_0x2c25570, L_0x2c26870; -RS_0x7f99c4316848/0/24 .resolv tri, L_0x2c27b70, L_0x2c28e60, L_0x2c2a170, L_0x2c2b470; -RS_0x7f99c4316848/0/28 .resolv tri, L_0x2c2c770, L_0x2c2daa0, L_0x2c2ebf0, L_0x2c2fe80; -RS_0x7f99c4316848/0/32 .resolv tri, L_0x2cc3e00, L_0x2cc4f00, L_0x2cc6040, L_0x2cc7210; -RS_0x7f99c4316848/0/36 .resolv tri, L_0x2cc8510, L_0x2cc9870, L_0x2ccac00, L_0x2ccbef0; -RS_0x7f99c4316848/0/40 .resolv tri, L_0x2ccd220, L_0x2cce530, L_0x2ccf860, L_0x2cd0b90; -RS_0x7f99c4316848/0/44 .resolv tri, L_0x2cd1ef0, L_0x2cd3290, L_0x2cd4490, L_0x2cd55c0; -RS_0x7f99c4316848/0/48 .resolv tri, L_0x2cd67d0, L_0x2cd7b00, L_0x2cd8e40, L_0x2cda180; -RS_0x7f99c4316848/0/52 .resolv tri, L_0x2cdb4d0, L_0x2cdc840, L_0x2cddb80, L_0x2cdeec0; -RS_0x7f99c4316848/0/56 .resolv tri, L_0x2ce0200, L_0x2ce1570, L_0x2ce28c0, L_0x2ce3c00; -RS_0x7f99c4316848/0/60 .resolv tri, L_0x2ce4f00, L_0x2ce61f0, L_0x2ce7520, L_0x2ce8810; -RS_0x7f99c4316848/1/0 .resolv tri, RS_0x7f99c4316848/0/0, RS_0x7f99c4316848/0/4, RS_0x7f99c4316848/0/8, RS_0x7f99c4316848/0/12; -RS_0x7f99c4316848/1/4 .resolv tri, RS_0x7f99c4316848/0/16, RS_0x7f99c4316848/0/20, RS_0x7f99c4316848/0/24, RS_0x7f99c4316848/0/28; -RS_0x7f99c4316848/1/8 .resolv tri, RS_0x7f99c4316848/0/32, RS_0x7f99c4316848/0/36, RS_0x7f99c4316848/0/40, RS_0x7f99c4316848/0/44; -RS_0x7f99c4316848/1/12 .resolv tri, RS_0x7f99c4316848/0/48, RS_0x7f99c4316848/0/52, RS_0x7f99c4316848/0/56, RS_0x7f99c4316848/0/60; -RS_0x7f99c4316848 .resolv tri, RS_0x7f99c4316848/1/0, RS_0x7f99c4316848/1/4, RS_0x7f99c4316848/1/8, RS_0x7f99c4316848/1/12; -v0x2bc79e0_0 .net8 "OrNorXorOut", 31 0, RS_0x7f99c4316848; 64 drivers -RS_0x7f99c4320b68 .resolv tri, L_0x2bf4d00, L_0x2cad930, C4, C4; -v0x2bc7a60_0 .net8 "SLTflag", 0 0, RS_0x7f99c4320b68; 2 drivers -RS_0x7f99c4320f58/0/0 .resolv tri, L_0x2c32890, L_0x2c35150, L_0x2c37760, L_0x2c3a0b0; -RS_0x7f99c4320f58/0/4 .resolv tri, L_0x2c3c460, L_0x2c3e9e0, L_0x2c41370, L_0x2c39f80; -RS_0x7f99c4320f58/0/8 .resolv tri, L_0x2c465c0, L_0x2c48dd0, L_0x2c4b8e0, L_0x2c4e230; -RS_0x7f99c4320f58/0/12 .resolv tri, L_0x2c50810, L_0x2c52f80, L_0x2c54fd0, L_0x2c43f80; -RS_0x7f99c4320f58/0/16 .resolv tri, L_0x2c5b020, L_0x2c5e470, L_0x2c60b90, L_0x2c62560; -RS_0x7f99c4320f58/0/20 .resolv tri, L_0x2c64aa0, L_0x2c67230, L_0x2c69230, L_0x2c6b8c0; -RS_0x7f99c4320f58/0/24 .resolv tri, L_0x2be0e50, L_0x2c72b50, L_0x2c75340, L_0x2c77db0; -RS_0x7f99c4320f58/0/28 .resolv tri, L_0x2c7a400, L_0x2c7cba0, L_0x2c499b0, L_0x2c58e50; -RS_0x7f99c4320f58/1/0 .resolv tri, RS_0x7f99c4320f58/0/0, RS_0x7f99c4320f58/0/4, RS_0x7f99c4320f58/0/8, RS_0x7f99c4320f58/0/12; -RS_0x7f99c4320f58/1/4 .resolv tri, RS_0x7f99c4320f58/0/16, RS_0x7f99c4320f58/0/20, RS_0x7f99c4320f58/0/24, RS_0x7f99c4320f58/0/28; -RS_0x7f99c4320f58 .resolv tri, RS_0x7f99c4320f58/1/0, RS_0x7f99c4320f58/1/4, C4, C4; -v0x2bc7ae0_0 .net8 "ZeroFlag", 31 0, RS_0x7f99c4320f58; 32 drivers -v0x2bc7b60_0 .var "carryin", 31 0; -RS_0x7f99c4320da8 .resolv tri, L_0x2bf2530, L_0x2cab160, C4, C4; -v0x2bc7be0_0 .net8 "carryout", 0 0, RS_0x7f99c4320da8; 2 drivers -RS_0x7f99c4320e38 .resolv tri, L_0x2bf2750, L_0x2cab310, C4, C4; -v0x2bc7c60_0 .net8 "overflow", 0 0, RS_0x7f99c4320e38; 2 drivers -RS_0x7f99c4320e68/0/0 .resolv tri, L_0x2bc8f40, L_0x2bca620, L_0x2bcba90, L_0x2bcbe80; -RS_0x7f99c4320e68/0/4 .resolv tri, L_0x2bcd470, L_0x2bceae0, L_0x2bcffa0, L_0x2bd1490; -RS_0x7f99c4320e68/0/8 .resolv tri, L_0x2bd2c20, L_0x2bd4360, L_0x2bd56b0, L_0x2bd6bf0; -RS_0x7f99c4320e68/0/12 .resolv tri, L_0x2bd80a0, L_0x2bd97b0, L_0x2bdacf0, L_0x2bdc230; -RS_0x7f99c4320e68/0/16 .resolv tri, L_0x2bddae0, L_0x2bdecf0, L_0x2be0190, L_0x2b87780; -RS_0x7f99c4320e68/0/20 .resolv tri, L_0x2be3740, L_0x2be4b00, L_0x2be5ed0, L_0x2be7290; -RS_0x7f99c4320e68/0/24 .resolv tri, L_0x2be8750, L_0x2bea4f0, L_0x2beb520, L_0x2beca00; -RS_0x7f99c4320e68/0/28 .resolv tri, L_0x2bd9220, L_0x2bef6c0, L_0x2bf0ce0, L_0x2bf21d0; -RS_0x7f99c4320e68/0/32 .resolv tri, L_0x2c80880, L_0x2c840e0, L_0x2c85510, L_0x2c85900; -RS_0x7f99c4320e68/0/36 .resolv tri, L_0x2c86e10, L_0x2c88200, L_0x2c89600, L_0x2c8a9d0; -RS_0x7f99c4320e68/0/40 .resolv tri, L_0x2c8c0a0, L_0x2c8d3f0, L_0x2c8e930, L_0x2c8fe70; -RS_0x7f99c4320e68/0/44 .resolv tri, L_0x2c91320, L_0x2c92750, L_0x2c93bd0, L_0x2c95070; -RS_0x7f99c4320e68/0/48 .resolv tri, L_0x2c968a0, L_0x2c97b80, L_0x2c99020, L_0x2c9a0d0; -RS_0x7f99c4320e68/0/52 .resolv tri, L_0x2c9b540, L_0x2c9ca40, L_0x2c9df50, L_0x2c9f310; -RS_0x7f99c4320e68/0/56 .resolv tri, L_0x2ca0790, L_0x2c05490, L_0x2ca4190, L_0x2ca6340; -RS_0x7f99c4320e68/0/60 .resolv tri, L_0x2ca6f20, L_0x2ca8410, L_0x2ca9910, L_0x2caae00; -RS_0x7f99c4320e68/1/0 .resolv tri, RS_0x7f99c4320e68/0/0, RS_0x7f99c4320e68/0/4, RS_0x7f99c4320e68/0/8, RS_0x7f99c4320e68/0/12; -RS_0x7f99c4320e68/1/4 .resolv tri, RS_0x7f99c4320e68/0/16, RS_0x7f99c4320e68/0/20, RS_0x7f99c4320e68/0/24, RS_0x7f99c4320e68/0/28; -RS_0x7f99c4320e68/1/8 .resolv tri, RS_0x7f99c4320e68/0/32, RS_0x7f99c4320e68/0/36, RS_0x7f99c4320e68/0/40, RS_0x7f99c4320e68/0/44; -RS_0x7f99c4320e68/1/12 .resolv tri, RS_0x7f99c4320e68/0/48, RS_0x7f99c4320e68/0/52, RS_0x7f99c4320e68/0/56, RS_0x7f99c4320e68/0/60; -RS_0x7f99c4320e68 .resolv tri, RS_0x7f99c4320e68/1/0, RS_0x7f99c4320e68/1/4, RS_0x7f99c4320e68/1/8, RS_0x7f99c4320e68/1/12; -v0x2bc7ce0_0 .net8 "subtract", 31 0, RS_0x7f99c4320e68; 64 drivers -S_0x2ba3100 .scope module, "trial" "AddSubSLT32" 2 141, 3 205, S_0x270e6d0; - .timescale -9 -12; -P_0x2ba31f8 .param/l "size" 3 228, +C4<0100000>; -L_0x2bf2530/d .functor OR 1, L_0x2bf2640, C4<0>, C4<0>, C4<0>; -L_0x2bf2530 .delay (20000,20000,20000) L_0x2bf2530/d; -L_0x2bf2750/d .functor XOR 1, RS_0x7f99c4320da8, L_0x2bdd7a0, C4<0>, C4<0>; -L_0x2bf2750 .delay (40000,40000,40000) L_0x2bf2750/d; -L_0x2bdd840/d .functor AND 1, L_0x2bdd950, L_0x2bdd9f0, C4<1>, C4<1>; -L_0x2bdd840 .delay (20000,20000,20000) L_0x2bdd840/d; -L_0x2bf36c0/d .functor NOT 1, RS_0x7f99c4320e38, C4<0>, C4<0>, C4<0>; -L_0x2bf36c0 .delay (10000,10000,10000) L_0x2bf36c0/d; -L_0x2bf37b0/d .functor NOT 1, L_0x2bf3850, C4<0>, C4<0>, C4<0>; -L_0x2bf37b0 .delay (10000,10000,10000) L_0x2bf37b0/d; -L_0x2bf38f0/d .functor AND 1, L_0x2bf36c0, L_0x2bf3a70, C4<1>, C4<1>; -L_0x2bf38f0 .delay (20000,20000,20000) L_0x2bf38f0/d; -L_0x2bf3b10/d .functor AND 1, RS_0x7f99c4320e38, L_0x2bf37b0, C4<1>, C4<1>; -L_0x2bf3b10 .delay (20000,20000,20000) L_0x2bf3b10/d; -L_0x2bf3c50/d .functor AND 1, L_0x2bf38f0, L_0x2bdd840, C4<1>, C4<1>; -L_0x2bf3c50 .delay (20000,20000,20000) L_0x2bf3c50/d; -L_0x2bf4c00/d .functor AND 1, L_0x2bf3b10, L_0x2bdd840, C4<1>, C4<1>; -L_0x2bf4c00 .delay (20000,20000,20000) L_0x2bf4c00/d; -L_0x2bf4d00/d .functor OR 1, L_0x2bf3c50, L_0x2bf4c00, C4<0>, C4<0>; -L_0x2bf4d00 .delay (20000,20000,20000) L_0x2bf4d00/d; -v0x2bc6580_0 .net "A", 31 0, v0x2bc7660_0; 1 drivers -v0x2bc6620_0 .alias "AddSubSLTSum", 31 0, v0x2bc76e0_0; -v0x2bc66a0_0 .net "B", 31 0, v0x2bc7860_0; 1 drivers -RS_0x7f99c4331e48/0/0 .resolv tri, L_0x2bc8e50, L_0x2bca4e0, L_0x2bcb920, L_0x2bccee0; -RS_0x7f99c4331e48/0/4 .resolv tri, L_0x2bce540, L_0x2bcfab0, L_0x2bd0fd0, L_0x2bd24f0; -RS_0x7f99c4331e48/0/8 .resolv tri, L_0x2bd3b00, L_0x2bd5210, L_0x2bd6720, L_0x2bd7c30; -RS_0x7f99c4331e48/0/12 .resolv tri, L_0x2bce480, L_0x2bda830, L_0x2bdbd40, L_0x2bdd240; -RS_0x7f99c4331e48/0/16 .resolv tri, L_0x2bde830, L_0x2bdfca0, L_0x2b87690, L_0x2be3650; -RS_0x7f99c4331e48/0/20 .resolv tri, L_0x2be4a10, L_0x2be5de0, L_0x2be71a0, L_0x2be8660; -RS_0x7f99c4331e48/0/24 .resolv tri, L_0x2be9b50, L_0x2beb430, L_0x2bec910, L_0x2bede10; -RS_0x7f99c4331e48/0/28 .resolv tri, L_0x2bd9130, L_0x2bf0bf0, L_0x2bf20e0, L_0x2bf35d0; -RS_0x7f99c4331e48/1/0 .resolv tri, RS_0x7f99c4331e48/0/0, RS_0x7f99c4331e48/0/4, RS_0x7f99c4331e48/0/8, RS_0x7f99c4331e48/0/12; -RS_0x7f99c4331e48/1/4 .resolv tri, RS_0x7f99c4331e48/0/16, RS_0x7f99c4331e48/0/20, RS_0x7f99c4331e48/0/24, RS_0x7f99c4331e48/0/28; -RS_0x7f99c4331e48 .resolv tri, RS_0x7f99c4331e48/1/0, RS_0x7f99c4331e48/1/4, C4, C4; -v0x2bc6720_0 .net8 "CarryoutWire", 31 0, RS_0x7f99c4331e48; 32 drivers -v0x2bc67a0_0 .net "Command", 2 0, v0x2bc78e0_0; 1 drivers -v0x2bc6820_0 .net "Res0OF1", 0 0, L_0x2bf3b10; 1 drivers -v0x2bc68c0_0 .net "Res1OF0", 0 0, L_0x2bf38f0; 1 drivers -v0x2bc6960_0 .alias "SLTflag", 0 0, v0x2bc7a60_0; -v0x2bc6a80_0 .net "SLTflag0", 0 0, L_0x2bf3c50; 1 drivers -v0x2bc6b20_0 .net "SLTflag1", 0 0, L_0x2bf4c00; 1 drivers -v0x2bc6bc0_0 .net "SLTon", 0 0, L_0x2bdd840; 1 drivers -v0x2bc6c60_0 .net *"_s292", 0 0, L_0x2bf2640; 1 drivers -v0x2bc6d00_0 .net/s *"_s293", 0 0, C4<0>; 1 drivers -v0x2bc6da0_0 .net *"_s296", 0 0, L_0x2bdd7a0; 1 drivers -v0x2bc6ec0_0 .net *"_s298", 0 0, L_0x2bdd950; 1 drivers -v0x2bc6f60_0 .net *"_s300", 0 0, L_0x2bdd9f0; 1 drivers -v0x2bc6e20_0 .net *"_s302", 0 0, L_0x2bf3850; 1 drivers -v0x2bc70b0_0 .net *"_s304", 0 0, L_0x2bf3a70; 1 drivers -v0x2bc71d0_0 .net "carryin", 31 0, v0x2bc7b60_0; 1 drivers -v0x2bc7250_0 .alias "carryout", 0 0, v0x2bc7be0_0; -v0x2bc7130_0 .net "nAddSubSLTSum", 0 0, L_0x2bf37b0; 1 drivers -v0x2bc7380_0 .net "nOF", 0 0, L_0x2bf36c0; 1 drivers -v0x2bc72d0_0 .alias "overflow", 0 0, v0x2bc7c60_0; -v0x2bc7510_0 .alias "subtract", 31 0, v0x2bc7ce0_0; -L_0x2bc8d00 .part/pv L_0x2bc8850, 1, 1, 32; -L_0x2bc8e50 .part/pv L_0x2bc8ba0, 1, 1, 32; -L_0x2bc8f40 .part/pv L_0x2bc8580, 1, 1, 32; -L_0x2bc9070 .part v0x2bc7660_0, 1, 1; -L_0x2bc9220 .part v0x2bc7860_0, 1, 1; -L_0x2bc93d0 .part RS_0x7f99c4331e48, 0, 1; -L_0x2bca3f0 .part/pv L_0x2bc9f20, 2, 1, 32; -L_0x2bca4e0 .part/pv L_0x2bca290, 2, 1, 32; -L_0x2bca620 .part/pv L_0x2bc9c50, 2, 1, 32; -L_0x2bca710 .part v0x2bc7660_0, 2, 1; -L_0x2bca810 .part v0x2bc7860_0, 2, 1; -L_0x2bca940 .part RS_0x7f99c4331e48, 1, 1; -L_0x2bcb830 .part/pv L_0x2bcb3a0, 3, 1, 32; -L_0x2bcb920 .part/pv L_0x2bcb6f0, 3, 1, 32; -L_0x2bcba90 .part/pv L_0x2bcb0d0, 3, 1, 32; -L_0x2bcbb80 .part v0x2bc7660_0, 3, 1; -L_0x2bcbcb0 .part v0x2bc7860_0, 3, 1; -L_0x2bcbde0 .part RS_0x7f99c4331e48, 2, 1; -L_0x2bccdf0 .part/pv L_0x2bcc920, 4, 1, 32; -L_0x2bccee0 .part/pv L_0x2bccc90, 4, 1, 32; -L_0x2bcbe80 .part/pv L_0x2bcc650, 4, 1, 32; -L_0x2bcd0d0 .part v0x2bc7660_0, 4, 1; -L_0x2bccfd0 .part v0x2bc7860_0, 4, 1; -L_0x2bcd2c0 .part RS_0x7f99c4331e48, 3, 1; -L_0x2bce390 .part/pv L_0x2bcdee0, 5, 1, 32; -L_0x2bce540 .part/pv L_0x2bce230, 5, 1, 32; -L_0x2bcd470 .part/pv L_0x2bcdc10, 5, 1, 32; -L_0x2bce820 .part v0x2bc7660_0, 5, 1; -L_0x2bce630 .part v0x2bc7860_0, 5, 1; -L_0x2bcea40 .part RS_0x7f99c4331e48, 4, 1; -L_0x2bcf9c0 .part/pv L_0x2bcf4f0, 6, 1, 32; -L_0x2bcfab0 .part/pv L_0x2bcf860, 6, 1, 32; -L_0x2bceae0 .part/pv L_0x2bcf220, 6, 1, 32; -L_0x2bcfcb0 .part v0x2bc7660_0, 6, 1; -L_0x2bcfba0 .part v0x2bc7860_0, 6, 1; -L_0x2bcff00 .part RS_0x7f99c4331e48, 5, 1; -L_0x2bd0ee0 .part/pv L_0x2bd0a30, 7, 1, 32; -L_0x2bd0fd0 .part/pv L_0x2bd0d80, 7, 1, 32; -L_0x2bcffa0 .part/pv L_0x2bd0760, 7, 1, 32; -L_0x2bd1200 .part v0x2bc7660_0, 7, 1; -L_0x2bd10c0 .part v0x2bc7860_0, 7, 1; -L_0x2bd13f0 .part RS_0x7f99c4331e48, 6, 1; -L_0x2bd2400 .part/pv L_0x2bd1f50, 8, 1, 32; -L_0x2bd24f0 .part/pv L_0x2bd22a0, 8, 1, 32; -L_0x2bd1490 .part/pv L_0x2bd1c80, 8, 1, 32; -L_0x2bd2750 .part v0x2bc7660_0, 8, 1; -L_0x2bd25e0 .part v0x2bc7860_0, 8, 1; -L_0x2bd2970 .part RS_0x7f99c4331e48, 7, 1; -L_0x2bd3a10 .part/pv L_0x2bd3560, 9, 1, 32; -L_0x2bd3b00 .part/pv L_0x2bd38b0, 9, 1, 32; -L_0x2bd2c20 .part/pv L_0x2bd3290, 9, 1, 32; -L_0x2bd2d10 .part v0x2bc7660_0, 9, 1; -L_0x2bc9110 .part v0x2bc7860_0, 9, 1; -L_0x2bd3c80 .part RS_0x7f99c4331e48, 8, 1; -L_0x2bd5120 .part/pv L_0x2bd4c70, 10, 1, 32; -L_0x2bd5210 .part/pv L_0x2bd4fc0, 10, 1, 32; -L_0x2bd4360 .part/pv L_0x2bd49a0, 10, 1, 32; -L_0x2bd4450 .part v0x2bc7660_0, 10, 1; -L_0x2bd54e0 .part v0x2bc7860_0, 10, 1; -L_0x2bd5610 .part RS_0x7f99c4331e48, 9, 1; -L_0x2bd6630 .part/pv L_0x2bd6180, 11, 1, 32; -L_0x2bd6720 .part/pv L_0x2bd64d0, 11, 1, 32; -L_0x2bd56b0 .part/pv L_0x2bd5eb0, 11, 1, 32; -L_0x2bd57a0 .part v0x2bc7660_0, 11, 1; -L_0x2bd6a20 .part v0x2bc7860_0, 11, 1; -L_0x2bd6b50 .part RS_0x7f99c4331e48, 10, 1; -L_0x2bd7b40 .part/pv L_0x2bd7690, 12, 1, 32; -L_0x2bd7c30 .part/pv L_0x2bd79e0, 12, 1, 32; -L_0x2bd6bf0 .part/pv L_0x2bd73c0, 12, 1, 32; -L_0x2bd6ce0 .part v0x2bc7660_0, 12, 1; -L_0x2bd7f60 .part v0x2bc7860_0, 12, 1; -L_0x2bd8000 .part RS_0x7f99c4331e48, 11, 1; -L_0x2bd9040 .part/pv L_0x2bd8b90, 13, 1, 32; -L_0x2bce480 .part/pv L_0x2bd8ee0, 13, 1, 32; -L_0x2bd80a0 .part/pv L_0x2bd88c0, 13, 1, 32; -L_0x2bce760 .part v0x2bc7660_0, 13, 1; -L_0x2bd8140 .part v0x2bc7860_0, 13, 1; -L_0x2bd9340 .part RS_0x7f99c4331e48, 12, 1; -L_0x2bda740 .part/pv L_0x2bda290, 14, 1, 32; -L_0x2bda830 .part/pv L_0x2bda5e0, 14, 1, 32; -L_0x2bd97b0 .part/pv L_0x2bd9fc0, 14, 1, 32; -L_0x2bd98a0 .part v0x2bc7660_0, 14, 1; -L_0x2bd9940 .part v0x2bc7860_0, 14, 1; -L_0x2bdac50 .part RS_0x7f99c4331e48, 13, 1; -L_0x2bdbc50 .part/pv L_0x2bdb7a0, 15, 1, 32; -L_0x2bdbd40 .part/pv L_0x2bdbaf0, 15, 1, 32; -L_0x2bdacf0 .part/pv L_0x2bdb4d0, 15, 1, 32; -L_0x2bdade0 .part v0x2bc7660_0, 15, 1; -L_0x2bdae80 .part v0x2bc7860_0, 15, 1; -L_0x2bdc190 .part RS_0x7f99c4331e48, 14, 1; -L_0x2bdd150 .part/pv L_0x2bdcca0, 16, 1, 32; -L_0x2bdd240 .part/pv L_0x2bdcff0, 16, 1, 32; -L_0x2bdc230 .part/pv L_0x2bdc9d0, 16, 1, 32; -L_0x2bdc320 .part v0x2bc7660_0, 16, 1; -L_0x2bdc3c0 .part v0x2bc7860_0, 16, 1; -L_0x2bdd630 .part RS_0x7f99c4331e48, 15, 1; -L_0x2bde740 .part/pv L_0x2bde2b0, 17, 1, 32; -L_0x2bde830 .part/pv L_0x2bde600, 17, 1, 32; -L_0x2bddae0 .part/pv L_0x2bddfe0, 17, 1, 32; -L_0x2bddbd0 .part v0x2bc7660_0, 17, 1; -L_0x2bddc70 .part v0x2bc7860_0, 17, 1; -L_0x2bdec50 .part RS_0x7f99c4331e48, 16, 1; -L_0x2bdfbb0 .part/pv L_0x2bdf720, 18, 1, 32; -L_0x2bdfca0 .part/pv L_0x2bdfa70, 18, 1, 32; -L_0x2bdecf0 .part/pv L_0x2bdf450, 18, 1, 32; -L_0x2bdede0 .part v0x2bc7660_0, 18, 1; -L_0x2bdee80 .part v0x2bc7860_0, 18, 1; -L_0x2be00f0 .part RS_0x7f99c4331e48, 17, 1; -L_0x2b875a0 .part/pv L_0x2b870f0, 19, 1, 32; -L_0x2b87690 .part/pv L_0x2b87440, 19, 1, 32; -L_0x2be0190 .part/pv L_0x2be0900, 19, 1, 32; -L_0x2be0280 .part v0x2bc7660_0, 19, 1; -L_0x2be0320 .part v0x2bc7860_0, 19, 1; -L_0x2be0450 .part RS_0x7f99c4331e48, 18, 1; -L_0x2be3560 .part/pv L_0x2be30d0, 20, 1, 32; -L_0x2be3650 .part/pv L_0x2be3420, 20, 1, 32; -L_0x2b87780 .part/pv L_0x2be2e00, 20, 1, 32; -L_0x2b87870 .part v0x2bc7660_0, 20, 1; -L_0x2b87910 .part v0x2bc7860_0, 20, 1; -L_0x2b87a40 .part RS_0x7f99c4331e48, 19, 1; -L_0x2be4920 .part/pv L_0x2be4490, 21, 1, 32; -L_0x2be4a10 .part/pv L_0x2be47e0, 21, 1, 32; -L_0x2be3740 .part/pv L_0x2be41c0, 21, 1, 32; -L_0x2be3830 .part v0x2bc7660_0, 21, 1; -L_0x2be38d0 .part v0x2bc7860_0, 21, 1; -L_0x2be3a00 .part RS_0x7f99c4331e48, 20, 1; -L_0x2be5cf0 .part/pv L_0x2be5860, 22, 1, 32; -L_0x2be5de0 .part/pv L_0x2be5bb0, 22, 1, 32; -L_0x2be4b00 .part/pv L_0x2be5590, 22, 1, 32; -L_0x2be4bf0 .part v0x2bc7660_0, 22, 1; -L_0x2be4c90 .part v0x2bc7860_0, 22, 1; -L_0x2be4dc0 .part RS_0x7f99c4331e48, 21, 1; -L_0x2be70b0 .part/pv L_0x2be6c20, 23, 1, 32; -L_0x2be71a0 .part/pv L_0x2be6f70, 23, 1, 32; -L_0x2be5ed0 .part/pv L_0x2be6950, 23, 1, 32; -L_0x2be5fc0 .part v0x2bc7660_0, 23, 1; -L_0x2be6060 .part v0x2bc7860_0, 23, 1; -L_0x2be6190 .part RS_0x7f99c4331e48, 22, 1; -L_0x2be8570 .part/pv L_0x2be8040, 24, 1, 32; -L_0x2be8660 .part/pv L_0x2be8410, 24, 1, 32; -L_0x2be7290 .part/pv L_0x2be7d70, 24, 1, 32; -L_0x2be7380 .part v0x2bc7660_0, 24, 1; -L_0x2be7420 .part v0x2bc7860_0, 24, 1; -L_0x2be7550 .part RS_0x7f99c4331e48, 23, 1; -L_0x2be9a60 .part/pv L_0x2be9530, 25, 1, 32; -L_0x2be9b50 .part/pv L_0x2be9900, 25, 1, 32; -L_0x2be8750 .part/pv L_0x2be9260, 25, 1, 32; -L_0x2be8840 .part v0x2bc7660_0, 25, 1; -L_0x2bd3d90 .part v0x2bc7860_0, 25, 1; -L_0x2bd3ec0 .part RS_0x7f99c4331e48, 24, 1; -L_0x2beb340 .part/pv L_0x2beaeb0, 26, 1, 32; -L_0x2beb430 .part/pv L_0x2beb200, 26, 1, 32; -L_0x2bea4f0 .part/pv L_0x2beabe0, 26, 1, 32; -L_0x2bea5e0 .part v0x2bc7660_0, 26, 1; -L_0x2bea680 .part v0x2bc7860_0, 26, 1; -L_0x2bea7b0 .part RS_0x7f99c4331e48, 25, 1; -L_0x2bec820 .part/pv L_0x2bec2f0, 27, 1, 32; -L_0x2bec910 .part/pv L_0x2bec6c0, 27, 1, 32; -L_0x2beb520 .part/pv L_0x2bec020, 27, 1, 32; -L_0x2beb610 .part v0x2bc7660_0, 27, 1; -L_0x2beb6b0 .part v0x2bc7860_0, 27, 1; -L_0x2beb7e0 .part RS_0x7f99c4331e48, 26, 1; -L_0x2bedd20 .part/pv L_0x2bed810, 28, 1, 32; -L_0x2bede10 .part/pv L_0x2bedbc0, 28, 1, 32; -L_0x2beca00 .part/pv L_0x2bed510, 28, 1, 32; -L_0x2becaf0 .part v0x2bc7660_0, 28, 1; -L_0x2becb90 .part v0x2bc7860_0, 28, 1; -L_0x2beccc0 .part RS_0x7f99c4331e48, 27, 1; -L_0x2bef210 .part/pv L_0x2beed00, 29, 1, 32; -L_0x2bd9130 .part/pv L_0x2bef0b0, 29, 1, 32; -L_0x2bd9220 .part/pv L_0x2beea00, 29, 1, 32; -L_0x2bee360 .part v0x2bc7660_0, 29, 1; -L_0x2bd95a0 .part v0x2bc7860_0, 29, 1; -L_0x2bd96d0 .part RS_0x7f99c4331e48, 28, 1; -L_0x2bf0b00 .part/pv L_0x2bf05d0, 30, 1, 32; -L_0x2bf0bf0 .part/pv L_0x2bf09a0, 30, 1, 32; -L_0x2bef6c0 .part/pv L_0x2bf0300, 30, 1, 32; -L_0x2bef7b0 .part v0x2bc7660_0, 30, 1; -L_0x2bef850 .part v0x2bc7860_0, 30, 1; -L_0x2bef980 .part RS_0x7f99c4331e48, 29, 1; -L_0x2bf1ff0 .part/pv L_0x2bf1ae0, 31, 1, 32; -L_0x2bf20e0 .part/pv L_0x2bf1e90, 31, 1, 32; -L_0x2bf0ce0 .part/pv L_0x2bf17e0, 31, 1, 32; -L_0x2bf0dd0 .part v0x2bc7660_0, 31, 1; -L_0x2bf0e70 .part v0x2bc7860_0, 31, 1; -L_0x2bf0fa0 .part RS_0x7f99c4331e48, 30, 1; -L_0x2bf34e0 .part/pv L_0x2bf2fd0, 0, 1, 32; -L_0x2bf35d0 .part/pv L_0x2bf3380, 0, 1, 32; -L_0x2bf21d0 .part/pv L_0x2bf2d00, 0, 1, 32; -L_0x2bf22c0 .part v0x2bc7660_0, 0, 1; -L_0x2bf2360 .part v0x2bc7860_0, 0, 1; -L_0x2bf2490 .part RS_0x7f99c4320e68, 0, 1; -L_0x2bf2640 .part RS_0x7f99c4331e48, 31, 1; -L_0x2bdd7a0 .part RS_0x7f99c4331e48, 30, 1; -L_0x2bdd950 .part v0x2bc78e0_0, 1, 1; -L_0x2bdd9f0 .part RS_0x7f99c4320e68, 0, 1; -L_0x2bf3850 .part RS_0x7f99c4320aa8, 31, 1; -L_0x2bf3a70 .part RS_0x7f99c4320aa8, 31, 1; -S_0x2bc5570 .scope module, "attempt2" "MiddleAddSubSLT" 3 225, 3 89, S_0x2ba3100; - .timescale -9 -12; -L_0x2bf1040/d .functor NOT 1, L_0x2bf2360, C4<0>, C4<0>, C4<0>; -L_0x2bf1040 .delay (10000,10000,10000) L_0x2bf1040/d; -L_0x2bf2bc0/d .functor NOT 1, L_0x2bf2c60, C4<0>, C4<0>, C4<0>; -L_0x2bf2bc0 .delay (10000,10000,10000) L_0x2bf2bc0/d; -L_0x2bf2d00/d .functor AND 1, L_0x2bf2e40, L_0x2bf2bc0, C4<1>, C4<1>; -L_0x2bf2d00 .delay (20000,20000,20000) L_0x2bf2d00/d; -L_0x2bf2ee0/d .functor XOR 1, L_0x2bf22c0, L_0x2bf2990, C4<0>, C4<0>; -L_0x2bf2ee0 .delay (40000,40000,40000) L_0x2bf2ee0/d; -L_0x2bf2fd0/d .functor XOR 1, L_0x2bf2ee0, L_0x2bf2490, C4<0>, C4<0>; -L_0x2bf2fd0 .delay (40000,40000,40000) L_0x2bf2fd0/d; -L_0x2bf30f0/d .functor AND 1, L_0x2bf22c0, L_0x2bf2990, C4<1>, C4<1>; -L_0x2bf30f0 .delay (20000,20000,20000) L_0x2bf30f0/d; -L_0x2bf3290/d .functor AND 1, L_0x2bf2ee0, L_0x2bf2490, C4<1>, C4<1>; -L_0x2bf3290 .delay (20000,20000,20000) L_0x2bf3290/d; -L_0x2bf3380/d .functor OR 1, L_0x2bf30f0, L_0x2bf3290, C4<0>, C4<0>; -L_0x2bf3380 .delay (20000,20000,20000) L_0x2bf3380/d; -v0x2bc5be0_0 .net "A", 0 0, L_0x2bf22c0; 1 drivers -v0x2bc5ca0_0 .net "AandB", 0 0, L_0x2bf30f0; 1 drivers -v0x2bc5d40_0 .net "AddSubSLTSum", 0 0, L_0x2bf2fd0; 1 drivers -v0x2bc5de0_0 .net "AxorB", 0 0, L_0x2bf2ee0; 1 drivers -v0x2bc5e60_0 .net "B", 0 0, L_0x2bf2360; 1 drivers -v0x2bc5f10_0 .net "BornB", 0 0, L_0x2bf2990; 1 drivers -v0x2bc5fd0_0 .net "CINandAxorB", 0 0, L_0x2bf3290; 1 drivers -v0x2bc6050_0 .alias "Command", 2 0, v0x2bc67a0_0; -v0x2bc60d0_0 .net *"_s3", 0 0, L_0x2bf2c60; 1 drivers -v0x2bc6150_0 .net *"_s5", 0 0, L_0x2bf2e40; 1 drivers -v0x2bc61f0_0 .net "carryin", 0 0, L_0x2bf2490; 1 drivers -v0x2bc6290_0 .net "carryout", 0 0, L_0x2bf3380; 1 drivers -v0x2bc6330_0 .net "nB", 0 0, L_0x2bf1040; 1 drivers -v0x2bc63e0_0 .net "nCmd2", 0 0, L_0x2bf2bc0; 1 drivers -v0x2bc64e0_0 .net "subtract", 0 0, L_0x2bf2d00; 1 drivers -L_0x2bf2b20 .part v0x2bc78e0_0, 0, 1; -L_0x2bf2c60 .part v0x2bc78e0_0, 2, 1; -L_0x2bf2e40 .part v0x2bc78e0_0, 0, 1; -S_0x2bc5660 .scope module, "mux0" "TwoInMux" 3 105, 3 8, S_0x2bc5570; - .timescale -9 -12; -L_0x2bf11a0/d .functor NOT 1, L_0x2bf2b20, C4<0>, C4<0>, C4<0>; -L_0x2bf11a0 .delay (10000,10000,10000) L_0x2bf11a0/d; -L_0x2bf27b0/d .functor AND 1, L_0x2bf2360, L_0x2bf11a0, C4<1>, C4<1>; -L_0x2bf27b0 .delay (20000,20000,20000) L_0x2bf27b0/d; -L_0x2bf28a0/d .functor AND 1, L_0x2bf1040, L_0x2bf2b20, C4<1>, C4<1>; -L_0x2bf28a0 .delay (20000,20000,20000) L_0x2bf28a0/d; -L_0x2bf2990/d .functor OR 1, L_0x2bf27b0, L_0x2bf28a0, C4<0>, C4<0>; -L_0x2bf2990 .delay (20000,20000,20000) L_0x2bf2990/d; -v0x2bc5750_0 .net "S", 0 0, L_0x2bf2b20; 1 drivers -v0x2bc5810_0 .alias "in0", 0 0, v0x2bc5e60_0; -v0x2bc58b0_0 .alias "in1", 0 0, v0x2bc6330_0; -v0x2bc5950_0 .net "nS", 0 0, L_0x2bf11a0; 1 drivers -v0x2bc5a00_0 .net "out0", 0 0, L_0x2bf27b0; 1 drivers -v0x2bc5aa0_0 .net "out1", 0 0, L_0x2bf28a0; 1 drivers -v0x2bc5b40_0 .alias "outfinal", 0 0, v0x2bc5f10_0; -S_0x2bc43d0 .scope generate, "addbits[1]" "addbits[1]" 3 230, 3 230, S_0x2ba3100; - .timescale -9 -12; -P_0x2bc3de8 .param/l "i" 3 230, +C4<01>; -S_0x2bc4540 .scope module, "attempt" "MiddleAddSubSLT" 3 232, 3 89, S_0x2bc43d0; - .timescale -9 -12; -L_0x2baaa50/d .functor NOT 1, L_0x2bc9220, C4<0>, C4<0>, C4<0>; -L_0x2baaa50 .delay (10000,10000,10000) L_0x2baaa50/d; -L_0x2bc8420/d .functor NOT 1, L_0x2bc84e0, C4<0>, C4<0>, C4<0>; -L_0x2bc8420 .delay (10000,10000,10000) L_0x2bc8420/d; -L_0x2bc8580/d .functor AND 1, L_0x2bc86c0, L_0x2bc8420, C4<1>, C4<1>; -L_0x2bc8580 .delay (20000,20000,20000) L_0x2bc8580/d; -L_0x2bc8760/d .functor XOR 1, L_0x2bc9070, L_0x2bc81b0, C4<0>, C4<0>; -L_0x2bc8760 .delay (40000,40000,40000) L_0x2bc8760/d; -L_0x2bc8850/d .functor XOR 1, L_0x2bc8760, L_0x2bc93d0, C4<0>, C4<0>; -L_0x2bc8850 .delay (40000,40000,40000) L_0x2bc8850/d; -L_0x2bc8940/d .functor AND 1, L_0x2bc9070, L_0x2bc81b0, C4<1>, C4<1>; -L_0x2bc8940 .delay (20000,20000,20000) L_0x2bc8940/d; -L_0x2bc8ab0/d .functor AND 1, L_0x2bc8760, L_0x2bc93d0, C4<1>, C4<1>; -L_0x2bc8ab0 .delay (20000,20000,20000) L_0x2bc8ab0/d; -L_0x2bc8ba0/d .functor OR 1, L_0x2bc8940, L_0x2bc8ab0, C4<0>, C4<0>; -L_0x2bc8ba0 .delay (20000,20000,20000) L_0x2bc8ba0/d; -v0x2bc4bd0_0 .net "A", 0 0, L_0x2bc9070; 1 drivers -v0x2bc4c90_0 .net "AandB", 0 0, L_0x2bc8940; 1 drivers -v0x2bc4d30_0 .net "AddSubSLTSum", 0 0, L_0x2bc8850; 1 drivers -v0x2bc4dd0_0 .net "AxorB", 0 0, L_0x2bc8760; 1 drivers -v0x2bc4e50_0 .net "B", 0 0, L_0x2bc9220; 1 drivers -v0x2bc4f00_0 .net "BornB", 0 0, L_0x2bc81b0; 1 drivers -v0x2bc4fc0_0 .net "CINandAxorB", 0 0, L_0x2bc8ab0; 1 drivers -v0x2bc5040_0 .alias "Command", 2 0, v0x2bc67a0_0; -v0x2bc50c0_0 .net *"_s3", 0 0, L_0x2bc84e0; 1 drivers -v0x2bc5140_0 .net *"_s5", 0 0, L_0x2bc86c0; 1 drivers -v0x2bc51e0_0 .net "carryin", 0 0, L_0x2bc93d0; 1 drivers -v0x2bc5280_0 .net "carryout", 0 0, L_0x2bc8ba0; 1 drivers -v0x2bc5320_0 .net "nB", 0 0, L_0x2baaa50; 1 drivers -v0x2bc53d0_0 .net "nCmd2", 0 0, L_0x2bc8420; 1 drivers -v0x2bc54d0_0 .net "subtract", 0 0, L_0x2bc8580; 1 drivers -L_0x2bc8380 .part v0x2bc78e0_0, 0, 1; -L_0x2bc84e0 .part v0x2bc78e0_0, 2, 1; -L_0x2bc86c0 .part v0x2bc78e0_0, 0, 1; -S_0x2bc4630 .scope module, "mux0" "TwoInMux" 3 105, 3 8, S_0x2bc4540; - .timescale -9 -12; -L_0x2bc7ed0/d .functor NOT 1, L_0x2bc8380, C4<0>, C4<0>, C4<0>; -L_0x2bc7ed0 .delay (10000,10000,10000) L_0x2bc7ed0/d; -L_0x2bc7f90/d .functor AND 1, L_0x2bc9220, L_0x2bc7ed0, C4<1>, C4<1>; -L_0x2bc7f90 .delay (20000,20000,20000) L_0x2bc7f90/d; -L_0x2bc80a0/d .functor AND 1, L_0x2baaa50, L_0x2bc8380, C4<1>, C4<1>; -L_0x2bc80a0 .delay (20000,20000,20000) L_0x2bc80a0/d; -L_0x2bc81b0/d .functor OR 1, L_0x2bc7f90, L_0x2bc80a0, C4<0>, C4<0>; -L_0x2bc81b0 .delay (20000,20000,20000) L_0x2bc81b0/d; -v0x2bc4720_0 .net "S", 0 0, L_0x2bc8380; 1 drivers -v0x2bc47c0_0 .alias "in0", 0 0, v0x2bc4e50_0; -v0x2bc4860_0 .alias "in1", 0 0, v0x2bc5320_0; -v0x2bc4900_0 .net "nS", 0 0, L_0x2bc7ed0; 1 drivers -v0x2bc49b0_0 .net "out0", 0 0, L_0x2bc7f90; 1 drivers -v0x2bc4a50_0 .net "out1", 0 0, L_0x2bc80a0; 1 drivers -v0x2bc4b30_0 .alias "outfinal", 0 0, v0x2bc4f00_0; -S_0x2bc3230 .scope generate, "addbits[2]" "addbits[2]" 3 230, 3 230, S_0x2ba3100; - .timescale -9 -12; -P_0x2bc2c48 .param/l "i" 3 230, +C4<010>; -S_0x2bc33a0 .scope module, "attempt" "MiddleAddSubSLT" 3 232, 3 89, S_0x2bc3230; - .timescale -9 -12; -L_0x2b8b5b0/d .functor NOT 1, L_0x2bca810, C4<0>, C4<0>, C4<0>; -L_0x2b8b5b0 .delay (10000,10000,10000) L_0x2b8b5b0/d; -L_0x2bc9af0/d .functor NOT 1, L_0x2bc9bb0, C4<0>, C4<0>, C4<0>; -L_0x2bc9af0 .delay (10000,10000,10000) L_0x2bc9af0/d; -L_0x2bc9c50/d .functor AND 1, L_0x2bc9d90, L_0x2bc9af0, C4<1>, C4<1>; -L_0x2bc9c50 .delay (20000,20000,20000) L_0x2bc9c50/d; -L_0x2bc9e30/d .functor XOR 1, L_0x2bca710, L_0x2bc9880, C4<0>, C4<0>; -L_0x2bc9e30 .delay (40000,40000,40000) L_0x2bc9e30/d; -L_0x2bc9f20/d .functor XOR 1, L_0x2bc9e30, L_0x2bca940, C4<0>, C4<0>; -L_0x2bc9f20 .delay (40000,40000,40000) L_0x2bc9f20/d; -L_0x2bca010/d .functor AND 1, L_0x2bca710, L_0x2bc9880, C4<1>, C4<1>; -L_0x2bca010 .delay (20000,20000,20000) L_0x2bca010/d; -L_0x2bca180/d .functor AND 1, L_0x2bc9e30, L_0x2bca940, C4<1>, C4<1>; -L_0x2bca180 .delay (20000,20000,20000) L_0x2bca180/d; -L_0x2bca290/d .functor OR 1, L_0x2bca010, L_0x2bca180, C4<0>, C4<0>; -L_0x2bca290 .delay (20000,20000,20000) L_0x2bca290/d; -v0x2bc3a30_0 .net "A", 0 0, L_0x2bca710; 1 drivers -v0x2bc3af0_0 .net "AandB", 0 0, L_0x2bca010; 1 drivers -v0x2bc3b90_0 .net "AddSubSLTSum", 0 0, L_0x2bc9f20; 1 drivers -v0x2bc3c30_0 .net "AxorB", 0 0, L_0x2bc9e30; 1 drivers -v0x2bc3cb0_0 .net "B", 0 0, L_0x2bca810; 1 drivers -v0x2bc3d60_0 .net "BornB", 0 0, L_0x2bc9880; 1 drivers -v0x2bc3e20_0 .net "CINandAxorB", 0 0, L_0x2bca180; 1 drivers -v0x2bc3ea0_0 .alias "Command", 2 0, v0x2bc67a0_0; -v0x2bc3f20_0 .net *"_s3", 0 0, L_0x2bc9bb0; 1 drivers -v0x2bc3fa0_0 .net *"_s5", 0 0, L_0x2bc9d90; 1 drivers -v0x2bc4040_0 .net "carryin", 0 0, L_0x2bca940; 1 drivers -v0x2bc40e0_0 .net "carryout", 0 0, L_0x2bca290; 1 drivers -v0x2bc4180_0 .net "nB", 0 0, L_0x2b8b5b0; 1 drivers -v0x2bc4230_0 .net "nCmd2", 0 0, L_0x2bc9af0; 1 drivers -v0x2bc4330_0 .net "subtract", 0 0, L_0x2bc9c50; 1 drivers -L_0x2bc9a50 .part v0x2bc78e0_0, 0, 1; -L_0x2bc9bb0 .part v0x2bc78e0_0, 2, 1; -L_0x2bc9d90 .part v0x2bc78e0_0, 0, 1; -S_0x2bc3490 .scope module, "mux0" "TwoInMux" 3 105, 3 8, S_0x2bc33a0; - .timescale -9 -12; -L_0x2bc95a0/d .functor NOT 1, L_0x2bc9a50, C4<0>, C4<0>, C4<0>; -L_0x2bc95a0 .delay (10000,10000,10000) L_0x2bc95a0/d; -L_0x2bc9660/d .functor AND 1, L_0x2bca810, L_0x2bc95a0, C4<1>, C4<1>; -L_0x2bc9660 .delay (20000,20000,20000) L_0x2bc9660/d; -L_0x2bc9770/d .functor AND 1, L_0x2b8b5b0, L_0x2bc9a50, C4<1>, C4<1>; -L_0x2bc9770 .delay (20000,20000,20000) L_0x2bc9770/d; -L_0x2bc9880/d .functor OR 1, L_0x2bc9660, L_0x2bc9770, C4<0>, C4<0>; -L_0x2bc9880 .delay (20000,20000,20000) L_0x2bc9880/d; -v0x2bc3580_0 .net "S", 0 0, L_0x2bc9a50; 1 drivers -v0x2bc3620_0 .alias "in0", 0 0, v0x2bc3cb0_0; -v0x2bc36c0_0 .alias "in1", 0 0, v0x2bc4180_0; -v0x2bc3760_0 .net "nS", 0 0, L_0x2bc95a0; 1 drivers -v0x2bc3810_0 .net "out0", 0 0, L_0x2bc9660; 1 drivers -v0x2bc38b0_0 .net "out1", 0 0, L_0x2bc9770; 1 drivers -v0x2bc3990_0 .alias "outfinal", 0 0, v0x2bc3d60_0; -S_0x2bc2090 .scope generate, "addbits[3]" "addbits[3]" 3 230, 3 230, S_0x2ba3100; - .timescale -9 -12; -P_0x2bc1aa8 .param/l "i" 3 230, +C4<011>; -S_0x2bc2200 .scope module, "attempt" "MiddleAddSubSLT" 3 232, 3 89, S_0x2bc2090; - .timescale -9 -12; -L_0x2bca7b0/d .functor NOT 1, L_0x2bcbcb0, C4<0>, C4<0>, C4<0>; -L_0x2bca7b0 .delay (10000,10000,10000) L_0x2bca7b0/d; -L_0x2baabf0/d .functor NOT 1, L_0x2bcb030, C4<0>, C4<0>, C4<0>; -L_0x2baabf0 .delay (10000,10000,10000) L_0x2baabf0/d; -L_0x2bcb0d0/d .functor AND 1, L_0x2bcb210, L_0x2baabf0, C4<1>, C4<1>; -L_0x2bcb0d0 .delay (20000,20000,20000) L_0x2bcb0d0/d; -L_0x2bcb2b0/d .functor XOR 1, L_0x2bcbb80, L_0x2bcad70, C4<0>, C4<0>; -L_0x2bcb2b0 .delay (40000,40000,40000) L_0x2bcb2b0/d; -L_0x2bcb3a0/d .functor XOR 1, L_0x2bcb2b0, L_0x2bcbde0, C4<0>, C4<0>; -L_0x2bcb3a0 .delay (40000,40000,40000) L_0x2bcb3a0/d; -L_0x2bcb490/d .functor AND 1, L_0x2bcbb80, L_0x2bcad70, C4<1>, C4<1>; -L_0x2bcb490 .delay (20000,20000,20000) L_0x2bcb490/d; -L_0x2bcb600/d .functor AND 1, L_0x2bcb2b0, L_0x2bcbde0, C4<1>, C4<1>; -L_0x2bcb600 .delay (20000,20000,20000) L_0x2bcb600/d; -L_0x2bcb6f0/d .functor OR 1, L_0x2bcb490, L_0x2bcb600, C4<0>, C4<0>; -L_0x2bcb6f0 .delay (20000,20000,20000) L_0x2bcb6f0/d; -v0x2bc2890_0 .net "A", 0 0, L_0x2bcbb80; 1 drivers -v0x2bc2950_0 .net "AandB", 0 0, L_0x2bcb490; 1 drivers -v0x2bc29f0_0 .net "AddSubSLTSum", 0 0, L_0x2bcb3a0; 1 drivers -v0x2bc2a90_0 .net "AxorB", 0 0, L_0x2bcb2b0; 1 drivers -v0x2bc2b10_0 .net "B", 0 0, L_0x2bcbcb0; 1 drivers -v0x2bc2bc0_0 .net "BornB", 0 0, L_0x2bcad70; 1 drivers -v0x2bc2c80_0 .net "CINandAxorB", 0 0, L_0x2bcb600; 1 drivers -v0x2bc2d00_0 .alias "Command", 2 0, v0x2bc67a0_0; -v0x2bc2d80_0 .net *"_s3", 0 0, L_0x2bcb030; 1 drivers -v0x2bc2e00_0 .net *"_s5", 0 0, L_0x2bcb210; 1 drivers -v0x2bc2ea0_0 .net "carryin", 0 0, L_0x2bcbde0; 1 drivers -v0x2bc2f40_0 .net "carryout", 0 0, L_0x2bcb6f0; 1 drivers -v0x2bc2fe0_0 .net "nB", 0 0, L_0x2bca7b0; 1 drivers -v0x2bc3090_0 .net "nCmd2", 0 0, L_0x2baabf0; 1 drivers -v0x2bc3190_0 .net "subtract", 0 0, L_0x2bcb0d0; 1 drivers -L_0x2bcaf40 .part v0x2bc78e0_0, 0, 1; -L_0x2bcb030 .part v0x2bc78e0_0, 2, 1; -L_0x2bcb210 .part v0x2bc78e0_0, 0, 1; -S_0x2bc22f0 .scope module, "mux0" "TwoInMux" 3 105, 3 8, S_0x2bc2200; - .timescale -9 -12; -L_0x2bcaad0/d .functor NOT 1, L_0x2bcaf40, C4<0>, C4<0>, C4<0>; -L_0x2bcaad0 .delay (10000,10000,10000) L_0x2bcaad0/d; -L_0x2bcab50/d .functor AND 1, L_0x2bcbcb0, L_0x2bcaad0, C4<1>, C4<1>; -L_0x2bcab50 .delay (20000,20000,20000) L_0x2bcab50/d; -L_0x2bcac60/d .functor AND 1, L_0x2bca7b0, L_0x2bcaf40, C4<1>, C4<1>; -L_0x2bcac60 .delay (20000,20000,20000) L_0x2bcac60/d; -L_0x2bcad70/d .functor OR 1, L_0x2bcab50, L_0x2bcac60, C4<0>, C4<0>; -L_0x2bcad70 .delay (20000,20000,20000) L_0x2bcad70/d; -v0x2bc23e0_0 .net "S", 0 0, L_0x2bcaf40; 1 drivers -v0x2bc2480_0 .alias "in0", 0 0, v0x2bc2b10_0; -v0x2bc2520_0 .alias "in1", 0 0, v0x2bc2fe0_0; -v0x2bc25c0_0 .net "nS", 0 0, L_0x2bcaad0; 1 drivers -v0x2bc2670_0 .net "out0", 0 0, L_0x2bcab50; 1 drivers -v0x2bc2710_0 .net "out1", 0 0, L_0x2bcac60; 1 drivers -v0x2bc27f0_0 .alias "outfinal", 0 0, v0x2bc2bc0_0; -S_0x2bc0ef0 .scope generate, "addbits[4]" "addbits[4]" 3 230, 3 230, S_0x2ba3100; - .timescale -9 -12; -P_0x2bc0908 .param/l "i" 3 230, +C4<0100>; -S_0x2bc1060 .scope module, "attempt" "MiddleAddSubSLT" 3 232, 3 89, S_0x2bc0ef0; - .timescale -9 -12; -L_0x2bcbc20/d .functor NOT 1, L_0x2bccfd0, C4<0>, C4<0>, C4<0>; -L_0x2bcbc20 .delay (10000,10000,10000) L_0x2bcbc20/d; -L_0x2bcc4f0/d .functor NOT 1, L_0x2bcc5b0, C4<0>, C4<0>, C4<0>; -L_0x2bcc4f0 .delay (10000,10000,10000) L_0x2bcc4f0/d; -L_0x2bcc650/d .functor AND 1, L_0x2bcc790, L_0x2bcc4f0, C4<1>, C4<1>; -L_0x2bcc650 .delay (20000,20000,20000) L_0x2bcc650/d; -L_0x2bcc830/d .functor XOR 1, L_0x2bcd0d0, L_0x2bcc280, C4<0>, C4<0>; -L_0x2bcc830 .delay (40000,40000,40000) L_0x2bcc830/d; -L_0x2bcc920/d .functor XOR 1, L_0x2bcc830, L_0x2bcd2c0, C4<0>, C4<0>; -L_0x2bcc920 .delay (40000,40000,40000) L_0x2bcc920/d; -L_0x2bcca10/d .functor AND 1, L_0x2bcd0d0, L_0x2bcc280, C4<1>, C4<1>; -L_0x2bcca10 .delay (20000,20000,20000) L_0x2bcca10/d; -L_0x2bccb80/d .functor AND 1, L_0x2bcc830, L_0x2bcd2c0, C4<1>, C4<1>; -L_0x2bccb80 .delay (20000,20000,20000) L_0x2bccb80/d; -L_0x2bccc90/d .functor OR 1, L_0x2bcca10, L_0x2bccb80, C4<0>, C4<0>; -L_0x2bccc90 .delay (20000,20000,20000) L_0x2bccc90/d; -v0x2bc16f0_0 .net "A", 0 0, L_0x2bcd0d0; 1 drivers -v0x2bc17b0_0 .net "AandB", 0 0, L_0x2bcca10; 1 drivers -v0x2bc1850_0 .net "AddSubSLTSum", 0 0, L_0x2bcc920; 1 drivers -v0x2bc18f0_0 .net "AxorB", 0 0, L_0x2bcc830; 1 drivers -v0x2bc1970_0 .net "B", 0 0, L_0x2bccfd0; 1 drivers -v0x2bc1a20_0 .net "BornB", 0 0, L_0x2bcc280; 1 drivers -v0x2bc1ae0_0 .net "CINandAxorB", 0 0, L_0x2bccb80; 1 drivers -v0x2bc1b60_0 .alias "Command", 2 0, v0x2bc67a0_0; -v0x2bc1be0_0 .net *"_s3", 0 0, L_0x2bcc5b0; 1 drivers -v0x2bc1c60_0 .net *"_s5", 0 0, L_0x2bcc790; 1 drivers -v0x2bc1d00_0 .net "carryin", 0 0, L_0x2bcd2c0; 1 drivers -v0x2bc1da0_0 .net "carryout", 0 0, L_0x2bccc90; 1 drivers -v0x2bc1e40_0 .net "nB", 0 0, L_0x2bcbc20; 1 drivers -v0x2bc1ef0_0 .net "nCmd2", 0 0, L_0x2bcc4f0; 1 drivers -v0x2bc1ff0_0 .net "subtract", 0 0, L_0x2bcc650; 1 drivers -L_0x2bcc450 .part v0x2bc78e0_0, 0, 1; -L_0x2bcc5b0 .part v0x2bc78e0_0, 2, 1; -L_0x2bcc790 .part v0x2bc78e0_0, 0, 1; -S_0x2bc1150 .scope module, "mux0" "TwoInMux" 3 105, 3 8, S_0x2bc1060; - .timescale -9 -12; -L_0x2bcbfc0/d .functor NOT 1, L_0x2bcc450, C4<0>, C4<0>, C4<0>; -L_0x2bcbfc0 .delay (10000,10000,10000) L_0x2bcbfc0/d; -L_0x2bcc060/d .functor AND 1, L_0x2bccfd0, L_0x2bcbfc0, C4<1>, C4<1>; -L_0x2bcc060 .delay (20000,20000,20000) L_0x2bcc060/d; -L_0x2bcc170/d .functor AND 1, L_0x2bcbc20, L_0x2bcc450, C4<1>, C4<1>; -L_0x2bcc170 .delay (20000,20000,20000) L_0x2bcc170/d; -L_0x2bcc280/d .functor OR 1, L_0x2bcc060, L_0x2bcc170, C4<0>, C4<0>; -L_0x2bcc280 .delay (20000,20000,20000) L_0x2bcc280/d; -v0x2bc1240_0 .net "S", 0 0, L_0x2bcc450; 1 drivers -v0x2bc12e0_0 .alias "in0", 0 0, v0x2bc1970_0; -v0x2bc1380_0 .alias "in1", 0 0, v0x2bc1e40_0; -v0x2bc1420_0 .net "nS", 0 0, L_0x2bcbfc0; 1 drivers -v0x2bc14d0_0 .net "out0", 0 0, L_0x2bcc060; 1 drivers -v0x2bc1570_0 .net "out1", 0 0, L_0x2bcc170; 1 drivers -v0x2bc1650_0 .alias "outfinal", 0 0, v0x2bc1a20_0; -S_0x2bbfd50 .scope generate, "addbits[5]" "addbits[5]" 3 230, 3 230, S_0x2ba3100; - .timescale -9 -12; -P_0x2bbf768 .param/l "i" 3 230, +C4<0101>; -S_0x2bbfec0 .scope module, "attempt" "MiddleAddSubSLT" 3 232, 3 89, S_0x2bbfd50; - .timescale -9 -12; -L_0x2bca9e0/d .functor NOT 1, L_0x2bce630, C4<0>, C4<0>, C4<0>; -L_0x2bca9e0 .delay (10000,10000,10000) L_0x2bca9e0/d; -L_0x2bcdab0/d .functor NOT 1, L_0x2bcdb70, C4<0>, C4<0>, C4<0>; -L_0x2bcdab0 .delay (10000,10000,10000) L_0x2bcdab0/d; -L_0x2bcdc10/d .functor AND 1, L_0x2bcdd50, L_0x2bcdab0, C4<1>, C4<1>; -L_0x2bcdc10 .delay (20000,20000,20000) L_0x2bcdc10/d; -L_0x2bcddf0/d .functor XOR 1, L_0x2bce820, L_0x2bcd840, C4<0>, C4<0>; -L_0x2bcddf0 .delay (40000,40000,40000) L_0x2bcddf0/d; -L_0x2bcdee0/d .functor XOR 1, L_0x2bcddf0, L_0x2bcea40, C4<0>, C4<0>; -L_0x2bcdee0 .delay (40000,40000,40000) L_0x2bcdee0/d; -L_0x2bcdfd0/d .functor AND 1, L_0x2bce820, L_0x2bcd840, C4<1>, C4<1>; -L_0x2bcdfd0 .delay (20000,20000,20000) L_0x2bcdfd0/d; -L_0x2bce140/d .functor AND 1, L_0x2bcddf0, L_0x2bcea40, C4<1>, C4<1>; -L_0x2bce140 .delay (20000,20000,20000) L_0x2bce140/d; -L_0x2bce230/d .functor OR 1, L_0x2bcdfd0, L_0x2bce140, C4<0>, C4<0>; -L_0x2bce230 .delay (20000,20000,20000) L_0x2bce230/d; -v0x2bc0550_0 .net "A", 0 0, L_0x2bce820; 1 drivers -v0x2bc0610_0 .net "AandB", 0 0, L_0x2bcdfd0; 1 drivers -v0x2bc06b0_0 .net "AddSubSLTSum", 0 0, L_0x2bcdee0; 1 drivers -v0x2bc0750_0 .net "AxorB", 0 0, L_0x2bcddf0; 1 drivers -v0x2bc07d0_0 .net "B", 0 0, L_0x2bce630; 1 drivers -v0x2bc0880_0 .net "BornB", 0 0, L_0x2bcd840; 1 drivers -v0x2bc0940_0 .net "CINandAxorB", 0 0, L_0x2bce140; 1 drivers -v0x2bc09c0_0 .alias "Command", 2 0, v0x2bc67a0_0; -v0x2bc0a40_0 .net *"_s3", 0 0, L_0x2bcdb70; 1 drivers -v0x2bc0ac0_0 .net *"_s5", 0 0, L_0x2bcdd50; 1 drivers -v0x2bc0b60_0 .net "carryin", 0 0, L_0x2bcea40; 1 drivers -v0x2bc0c00_0 .net "carryout", 0 0, L_0x2bce230; 1 drivers -v0x2bc0ca0_0 .net "nB", 0 0, L_0x2bca9e0; 1 drivers -v0x2bc0d50_0 .net "nCmd2", 0 0, L_0x2bcdab0; 1 drivers -v0x2bc0e50_0 .net "subtract", 0 0, L_0x2bcdc10; 1 drivers -L_0x2bcda10 .part v0x2bc78e0_0, 0, 1; -L_0x2bcdb70 .part v0x2bc78e0_0, 2, 1; -L_0x2bcdd50 .part v0x2bc78e0_0, 0, 1; -S_0x2bbffb0 .scope module, "mux0" "TwoInMux" 3 105, 3 8, S_0x2bbfec0; - .timescale -9 -12; -L_0x2bcd560/d .functor NOT 1, L_0x2bcda10, C4<0>, C4<0>, C4<0>; -L_0x2bcd560 .delay (10000,10000,10000) L_0x2bcd560/d; -L_0x2bcd620/d .functor AND 1, L_0x2bce630, L_0x2bcd560, C4<1>, C4<1>; -L_0x2bcd620 .delay (20000,20000,20000) L_0x2bcd620/d; -L_0x2bcd730/d .functor AND 1, L_0x2bca9e0, L_0x2bcda10, C4<1>, C4<1>; -L_0x2bcd730 .delay (20000,20000,20000) L_0x2bcd730/d; -L_0x2bcd840/d .functor OR 1, L_0x2bcd620, L_0x2bcd730, C4<0>, C4<0>; -L_0x2bcd840 .delay (20000,20000,20000) L_0x2bcd840/d; -v0x2bc00a0_0 .net "S", 0 0, L_0x2bcda10; 1 drivers -v0x2bc0140_0 .alias "in0", 0 0, v0x2bc07d0_0; -v0x2bc01e0_0 .alias "in1", 0 0, v0x2bc0ca0_0; -v0x2bc0280_0 .net "nS", 0 0, L_0x2bcd560; 1 drivers -v0x2bc0330_0 .net "out0", 0 0, L_0x2bcd620; 1 drivers -v0x2bc03d0_0 .net "out1", 0 0, L_0x2bcd730; 1 drivers -v0x2bc04b0_0 .alias "outfinal", 0 0, v0x2bc0880_0; -S_0x2bbebb0 .scope generate, "addbits[6]" "addbits[6]" 3 230, 3 230, S_0x2ba3100; - .timescale -9 -12; -P_0x2bbe5c8 .param/l "i" 3 230, +C4<0110>; -S_0x2bbed20 .scope module, "attempt" "MiddleAddSubSLT" 3 232, 3 89, S_0x2bbebb0; - .timescale -9 -12; -L_0x2bce8c0/d .functor NOT 1, L_0x2bcfba0, C4<0>, C4<0>, C4<0>; -L_0x2bce8c0 .delay (10000,10000,10000) L_0x2bce8c0/d; -L_0x2bcf0c0/d .functor NOT 1, L_0x2bcf180, C4<0>, C4<0>, C4<0>; -L_0x2bcf0c0 .delay (10000,10000,10000) L_0x2bcf0c0/d; -L_0x2bcf220/d .functor AND 1, L_0x2bcf360, L_0x2bcf0c0, C4<1>, C4<1>; -L_0x2bcf220 .delay (20000,20000,20000) L_0x2bcf220/d; -L_0x2bcf400/d .functor XOR 1, L_0x2bcfcb0, L_0x2bcee50, C4<0>, C4<0>; -L_0x2bcf400 .delay (40000,40000,40000) L_0x2bcf400/d; -L_0x2bcf4f0/d .functor XOR 1, L_0x2bcf400, L_0x2bcff00, C4<0>, C4<0>; -L_0x2bcf4f0 .delay (40000,40000,40000) L_0x2bcf4f0/d; -L_0x2bcf5e0/d .functor AND 1, L_0x2bcfcb0, L_0x2bcee50, C4<1>, C4<1>; -L_0x2bcf5e0 .delay (20000,20000,20000) L_0x2bcf5e0/d; -L_0x2bcf750/d .functor AND 1, L_0x2bcf400, L_0x2bcff00, C4<1>, C4<1>; -L_0x2bcf750 .delay (20000,20000,20000) L_0x2bcf750/d; -L_0x2bcf860/d .functor OR 1, L_0x2bcf5e0, L_0x2bcf750, C4<0>, C4<0>; -L_0x2bcf860 .delay (20000,20000,20000) L_0x2bcf860/d; -v0x2bbf3b0_0 .net "A", 0 0, L_0x2bcfcb0; 1 drivers -v0x2bbf470_0 .net "AandB", 0 0, L_0x2bcf5e0; 1 drivers -v0x2bbf510_0 .net "AddSubSLTSum", 0 0, L_0x2bcf4f0; 1 drivers -v0x2bbf5b0_0 .net "AxorB", 0 0, L_0x2bcf400; 1 drivers -v0x2bbf630_0 .net "B", 0 0, L_0x2bcfba0; 1 drivers -v0x2bbf6e0_0 .net "BornB", 0 0, L_0x2bcee50; 1 drivers -v0x2bbf7a0_0 .net "CINandAxorB", 0 0, L_0x2bcf750; 1 drivers -v0x2bbf820_0 .alias "Command", 2 0, v0x2bc67a0_0; -v0x2bbf8a0_0 .net *"_s3", 0 0, L_0x2bcf180; 1 drivers -v0x2bbf920_0 .net *"_s5", 0 0, L_0x2bcf360; 1 drivers -v0x2bbf9c0_0 .net "carryin", 0 0, L_0x2bcff00; 1 drivers -v0x2bbfa60_0 .net "carryout", 0 0, L_0x2bcf860; 1 drivers -v0x2bbfb00_0 .net "nB", 0 0, L_0x2bce8c0; 1 drivers -v0x2bbfbb0_0 .net "nCmd2", 0 0, L_0x2bcf0c0; 1 drivers -v0x2bbfcb0_0 .net "subtract", 0 0, L_0x2bcf220; 1 drivers -L_0x2bcf020 .part v0x2bc78e0_0, 0, 1; -L_0x2bcf180 .part v0x2bc78e0_0, 2, 1; -L_0x2bcf360 .part v0x2bc78e0_0, 0, 1; -S_0x2bbee10 .scope module, "mux0" "TwoInMux" 3 105, 3 8, S_0x2bbed20; - .timescale -9 -12; -L_0x2bcec30/d .functor NOT 1, L_0x2bcf020, C4<0>, C4<0>, C4<0>; -L_0x2bcec30 .delay (10000,10000,10000) L_0x2bcec30/d; -L_0x2bcec90/d .functor AND 1, L_0x2bcfba0, L_0x2bcec30, C4<1>, C4<1>; -L_0x2bcec90 .delay (20000,20000,20000) L_0x2bcec90/d; -L_0x2bced40/d .functor AND 1, L_0x2bce8c0, L_0x2bcf020, C4<1>, C4<1>; -L_0x2bced40 .delay (20000,20000,20000) L_0x2bced40/d; -L_0x2bcee50/d .functor OR 1, L_0x2bcec90, L_0x2bced40, C4<0>, C4<0>; -L_0x2bcee50 .delay (20000,20000,20000) L_0x2bcee50/d; -v0x2bbef00_0 .net "S", 0 0, L_0x2bcf020; 1 drivers -v0x2bbefa0_0 .alias "in0", 0 0, v0x2bbf630_0; -v0x2bbf040_0 .alias "in1", 0 0, v0x2bbfb00_0; -v0x2bbf0e0_0 .net "nS", 0 0, L_0x2bcec30; 1 drivers -v0x2bbf190_0 .net "out0", 0 0, L_0x2bcec90; 1 drivers -v0x2bbf230_0 .net "out1", 0 0, L_0x2bced40; 1 drivers -v0x2bbf310_0 .alias "outfinal", 0 0, v0x2bbf6e0_0; -S_0x2bbda10 .scope generate, "addbits[7]" "addbits[7]" 3 230, 3 230, S_0x2ba3100; - .timescale -9 -12; -P_0x2bbd428 .param/l "i" 3 230, +C4<0111>; -S_0x2bbdb80 .scope module, "attempt" "MiddleAddSubSLT" 3 232, 3 89, S_0x2bbda10; - .timescale -9 -12; -L_0x2bcfc40/d .functor NOT 1, L_0x2bd10c0, C4<0>, C4<0>, C4<0>; -L_0x2bcfc40 .delay (10000,10000,10000) L_0x2bcfc40/d; -L_0x2bd0600/d .functor NOT 1, L_0x2bd06c0, C4<0>, C4<0>, C4<0>; -L_0x2bd0600 .delay (10000,10000,10000) L_0x2bd0600/d; -L_0x2bd0760/d .functor AND 1, L_0x2bd08a0, L_0x2bd0600, C4<1>, C4<1>; -L_0x2bd0760 .delay (20000,20000,20000) L_0x2bd0760/d; -L_0x2bd0940/d .functor XOR 1, L_0x2bd1200, L_0x2bd0390, C4<0>, C4<0>; -L_0x2bd0940 .delay (40000,40000,40000) L_0x2bd0940/d; -L_0x2bd0a30/d .functor XOR 1, L_0x2bd0940, L_0x2bd13f0, C4<0>, C4<0>; -L_0x2bd0a30 .delay (40000,40000,40000) L_0x2bd0a30/d; -L_0x2bd0b20/d .functor AND 1, L_0x2bd1200, L_0x2bd0390, C4<1>, C4<1>; -L_0x2bd0b20 .delay (20000,20000,20000) L_0x2bd0b20/d; -L_0x2bd0c90/d .functor AND 1, L_0x2bd0940, L_0x2bd13f0, C4<1>, C4<1>; -L_0x2bd0c90 .delay (20000,20000,20000) L_0x2bd0c90/d; -L_0x2bd0d80/d .functor OR 1, L_0x2bd0b20, L_0x2bd0c90, C4<0>, C4<0>; -L_0x2bd0d80 .delay (20000,20000,20000) L_0x2bd0d80/d; -v0x2bbe210_0 .net "A", 0 0, L_0x2bd1200; 1 drivers -v0x2bbe2d0_0 .net "AandB", 0 0, L_0x2bd0b20; 1 drivers -v0x2bbe370_0 .net "AddSubSLTSum", 0 0, L_0x2bd0a30; 1 drivers -v0x2bbe410_0 .net "AxorB", 0 0, L_0x2bd0940; 1 drivers -v0x2bbe490_0 .net "B", 0 0, L_0x2bd10c0; 1 drivers -v0x2bbe540_0 .net "BornB", 0 0, L_0x2bd0390; 1 drivers -v0x2bbe600_0 .net "CINandAxorB", 0 0, L_0x2bd0c90; 1 drivers -v0x2bbe680_0 .alias "Command", 2 0, v0x2bc67a0_0; -v0x2bbe700_0 .net *"_s3", 0 0, L_0x2bd06c0; 1 drivers -v0x2bbe780_0 .net *"_s5", 0 0, L_0x2bd08a0; 1 drivers -v0x2bbe820_0 .net "carryin", 0 0, L_0x2bd13f0; 1 drivers -v0x2bbe8c0_0 .net "carryout", 0 0, L_0x2bd0d80; 1 drivers -v0x2bbe960_0 .net "nB", 0 0, L_0x2bcfc40; 1 drivers -v0x2bbea10_0 .net "nCmd2", 0 0, L_0x2bd0600; 1 drivers -v0x2bbeb10_0 .net "subtract", 0 0, L_0x2bd0760; 1 drivers -L_0x2bd0560 .part v0x2bc78e0_0, 0, 1; -L_0x2bd06c0 .part v0x2bc78e0_0, 2, 1; -L_0x2bd08a0 .part v0x2bc78e0_0, 0, 1; -S_0x2bbdc70 .scope module, "mux0" "TwoInMux" 3 105, 3 8, S_0x2bbdb80; - .timescale -9 -12; -L_0x2bd00d0/d .functor NOT 1, L_0x2bd0560, C4<0>, C4<0>, C4<0>; -L_0x2bd00d0 .delay (10000,10000,10000) L_0x2bd00d0/d; -L_0x2bd0170/d .functor AND 1, L_0x2bd10c0, L_0x2bd00d0, C4<1>, C4<1>; -L_0x2bd0170 .delay (20000,20000,20000) L_0x2bd0170/d; -L_0x2bd0280/d .functor AND 1, L_0x2bcfc40, L_0x2bd0560, C4<1>, C4<1>; -L_0x2bd0280 .delay (20000,20000,20000) L_0x2bd0280/d; -L_0x2bd0390/d .functor OR 1, L_0x2bd0170, L_0x2bd0280, C4<0>, C4<0>; -L_0x2bd0390 .delay (20000,20000,20000) L_0x2bd0390/d; -v0x2bbdd60_0 .net "S", 0 0, L_0x2bd0560; 1 drivers -v0x2bbde00_0 .alias "in0", 0 0, v0x2bbe490_0; -v0x2bbdea0_0 .alias "in1", 0 0, v0x2bbe960_0; -v0x2bbdf40_0 .net "nS", 0 0, L_0x2bd00d0; 1 drivers -v0x2bbdff0_0 .net "out0", 0 0, L_0x2bd0170; 1 drivers -v0x2bbe090_0 .net "out1", 0 0, L_0x2bd0280; 1 drivers -v0x2bbe170_0 .alias "outfinal", 0 0, v0x2bbe540_0; -S_0x2bbc870 .scope generate, "addbits[8]" "addbits[8]" 3 230, 3 230, S_0x2ba3100; - .timescale -9 -12; -P_0x2bbc288 .param/l "i" 3 230, +C4<01000>; -S_0x2bbc9e0 .scope module, "attempt" "MiddleAddSubSLT" 3 232, 3 89, S_0x2bbc870; - .timescale -9 -12; -L_0x2bd12a0/d .functor NOT 1, L_0x2bd25e0, C4<0>, C4<0>, C4<0>; -L_0x2bd12a0 .delay (10000,10000,10000) L_0x2bd12a0/d; -L_0x2bd1b20/d .functor NOT 1, L_0x2bd1be0, C4<0>, C4<0>, C4<0>; -L_0x2bd1b20 .delay (10000,10000,10000) L_0x2bd1b20/d; -L_0x2bd1c80/d .functor AND 1, L_0x2bd1dc0, L_0x2bd1b20, C4<1>, C4<1>; -L_0x2bd1c80 .delay (20000,20000,20000) L_0x2bd1c80/d; -L_0x2bd1e60/d .functor XOR 1, L_0x2bd2750, L_0x2bd18b0, C4<0>, C4<0>; -L_0x2bd1e60 .delay (40000,40000,40000) L_0x2bd1e60/d; -L_0x2bd1f50/d .functor XOR 1, L_0x2bd1e60, L_0x2bd2970, C4<0>, C4<0>; -L_0x2bd1f50 .delay (40000,40000,40000) L_0x2bd1f50/d; -L_0x2bd2040/d .functor AND 1, L_0x2bd2750, L_0x2bd18b0, C4<1>, C4<1>; -L_0x2bd2040 .delay (20000,20000,20000) L_0x2bd2040/d; -L_0x2bd21b0/d .functor AND 1, L_0x2bd1e60, L_0x2bd2970, C4<1>, C4<1>; -L_0x2bd21b0 .delay (20000,20000,20000) L_0x2bd21b0/d; -L_0x2bd22a0/d .functor OR 1, L_0x2bd2040, L_0x2bd21b0, C4<0>, C4<0>; -L_0x2bd22a0 .delay (20000,20000,20000) L_0x2bd22a0/d; -v0x2bbd070_0 .net "A", 0 0, L_0x2bd2750; 1 drivers -v0x2bbd130_0 .net "AandB", 0 0, L_0x2bd2040; 1 drivers -v0x2bbd1d0_0 .net "AddSubSLTSum", 0 0, L_0x2bd1f50; 1 drivers -v0x2bbd270_0 .net "AxorB", 0 0, L_0x2bd1e60; 1 drivers -v0x2bbd2f0_0 .net "B", 0 0, L_0x2bd25e0; 1 drivers -v0x2bbd3a0_0 .net "BornB", 0 0, L_0x2bd18b0; 1 drivers -v0x2bbd460_0 .net "CINandAxorB", 0 0, L_0x2bd21b0; 1 drivers -v0x2bbd4e0_0 .alias "Command", 2 0, v0x2bc67a0_0; -v0x2bbd560_0 .net *"_s3", 0 0, L_0x2bd1be0; 1 drivers -v0x2bbd5e0_0 .net *"_s5", 0 0, L_0x2bd1dc0; 1 drivers -v0x2bbd680_0 .net "carryin", 0 0, L_0x2bd2970; 1 drivers -v0x2bbd720_0 .net "carryout", 0 0, L_0x2bd22a0; 1 drivers -v0x2bbd7c0_0 .net "nB", 0 0, L_0x2bd12a0; 1 drivers -v0x2bbd870_0 .net "nCmd2", 0 0, L_0x2bd1b20; 1 drivers -v0x2bbd970_0 .net "subtract", 0 0, L_0x2bd1c80; 1 drivers -L_0x2bd1a80 .part v0x2bc78e0_0, 0, 1; -L_0x2bd1be0 .part v0x2bc78e0_0, 2, 1; -L_0x2bd1dc0 .part v0x2bc78e0_0, 0, 1; -S_0x2bbcad0 .scope module, "mux0" "TwoInMux" 3 105, 3 8, S_0x2bbc9e0; - .timescale -9 -12; -L_0x2bd15f0/d .functor NOT 1, L_0x2bd1a80, C4<0>, C4<0>, C4<0>; -L_0x2bd15f0 .delay (10000,10000,10000) L_0x2bd15f0/d; -L_0x2bd1690/d .functor AND 1, L_0x2bd25e0, L_0x2bd15f0, C4<1>, C4<1>; -L_0x2bd1690 .delay (20000,20000,20000) L_0x2bd1690/d; -L_0x2bd17a0/d .functor AND 1, L_0x2bd12a0, L_0x2bd1a80, C4<1>, C4<1>; -L_0x2bd17a0 .delay (20000,20000,20000) L_0x2bd17a0/d; -L_0x2bd18b0/d .functor OR 1, L_0x2bd1690, L_0x2bd17a0, C4<0>, C4<0>; -L_0x2bd18b0 .delay (20000,20000,20000) L_0x2bd18b0/d; -v0x2bbcbc0_0 .net "S", 0 0, L_0x2bd1a80; 1 drivers -v0x2bbcc60_0 .alias "in0", 0 0, v0x2bbd2f0_0; -v0x2bbcd00_0 .alias "in1", 0 0, v0x2bbd7c0_0; -v0x2bbcda0_0 .net "nS", 0 0, L_0x2bd15f0; 1 drivers -v0x2bbce50_0 .net "out0", 0 0, L_0x2bd1690; 1 drivers -v0x2bbcef0_0 .net "out1", 0 0, L_0x2bd17a0; 1 drivers -v0x2bbcfd0_0 .alias "outfinal", 0 0, v0x2bbd3a0_0; -S_0x2bbb6d0 .scope generate, "addbits[9]" "addbits[9]" 3 230, 3 230, S_0x2ba3100; - .timescale -9 -12; -P_0x2bbb0e8 .param/l "i" 3 230, +C4<01001>; -S_0x2bbb840 .scope module, "attempt" "MiddleAddSubSLT" 3 232, 3 89, S_0x2bbb6d0; - .timescale -9 -12; -L_0x2bd1580/d .functor NOT 1, L_0x2bc9110, C4<0>, C4<0>, C4<0>; -L_0x2bd1580 .delay (10000,10000,10000) L_0x2bd1580/d; -L_0x2bd3130/d .functor NOT 1, L_0x2bd31f0, C4<0>, C4<0>, C4<0>; -L_0x2bd3130 .delay (10000,10000,10000) L_0x2bd3130/d; -L_0x2bd3290/d .functor AND 1, L_0x2bd33d0, L_0x2bd3130, C4<1>, C4<1>; -L_0x2bd3290 .delay (20000,20000,20000) L_0x2bd3290/d; -L_0x2bd3470/d .functor XOR 1, L_0x2bd2d10, L_0x2bd2ec0, C4<0>, C4<0>; -L_0x2bd3470 .delay (40000,40000,40000) L_0x2bd3470/d; -L_0x2bd3560/d .functor XOR 1, L_0x2bd3470, L_0x2bd3c80, C4<0>, C4<0>; -L_0x2bd3560 .delay (40000,40000,40000) L_0x2bd3560/d; -L_0x2bd3650/d .functor AND 1, L_0x2bd2d10, L_0x2bd2ec0, C4<1>, C4<1>; -L_0x2bd3650 .delay (20000,20000,20000) L_0x2bd3650/d; -L_0x2bd37c0/d .functor AND 1, L_0x2bd3470, L_0x2bd3c80, C4<1>, C4<1>; -L_0x2bd37c0 .delay (20000,20000,20000) L_0x2bd37c0/d; -L_0x2bd38b0/d .functor OR 1, L_0x2bd3650, L_0x2bd37c0, C4<0>, C4<0>; -L_0x2bd38b0 .delay (20000,20000,20000) L_0x2bd38b0/d; -v0x2bbbed0_0 .net "A", 0 0, L_0x2bd2d10; 1 drivers -v0x2bbbf90_0 .net "AandB", 0 0, L_0x2bd3650; 1 drivers -v0x2bbc030_0 .net "AddSubSLTSum", 0 0, L_0x2bd3560; 1 drivers -v0x2bbc0d0_0 .net "AxorB", 0 0, L_0x2bd3470; 1 drivers -v0x2bbc150_0 .net "B", 0 0, L_0x2bc9110; 1 drivers -v0x2bbc200_0 .net "BornB", 0 0, L_0x2bd2ec0; 1 drivers -v0x2bbc2c0_0 .net "CINandAxorB", 0 0, L_0x2bd37c0; 1 drivers -v0x2bbc340_0 .alias "Command", 2 0, v0x2bc67a0_0; -v0x2bbc3c0_0 .net *"_s3", 0 0, L_0x2bd31f0; 1 drivers -v0x2bbc440_0 .net *"_s5", 0 0, L_0x2bd33d0; 1 drivers -v0x2bbc4e0_0 .net "carryin", 0 0, L_0x2bd3c80; 1 drivers -v0x2bbc580_0 .net "carryout", 0 0, L_0x2bd38b0; 1 drivers -v0x2bbc620_0 .net "nB", 0 0, L_0x2bd1580; 1 drivers -v0x2bbc6d0_0 .net "nCmd2", 0 0, L_0x2bd3130; 1 drivers -v0x2bbc7d0_0 .net "subtract", 0 0, L_0x2bd3290; 1 drivers -L_0x2bd3090 .part v0x2bc78e0_0, 0, 1; -L_0x2bd31f0 .part v0x2bc78e0_0, 2, 1; -L_0x2bd33d0 .part v0x2bc78e0_0, 0, 1; -S_0x2bbb930 .scope module, "mux0" "TwoInMux" 3 105, 3 8, S_0x2bbb840; - .timescale -9 -12; -L_0x2bd27f0/d .functor NOT 1, L_0x2bd3090, C4<0>, C4<0>, C4<0>; -L_0x2bd27f0 .delay (10000,10000,10000) L_0x2bd27f0/d; -L_0x2bd28b0/d .functor AND 1, L_0x2bc9110, L_0x2bd27f0, C4<1>, C4<1>; -L_0x2bd28b0 .delay (20000,20000,20000) L_0x2bd28b0/d; -L_0x2bd2db0/d .functor AND 1, L_0x2bd1580, L_0x2bd3090, C4<1>, C4<1>; -L_0x2bd2db0 .delay (20000,20000,20000) L_0x2bd2db0/d; -L_0x2bd2ec0/d .functor OR 1, L_0x2bd28b0, L_0x2bd2db0, C4<0>, C4<0>; -L_0x2bd2ec0 .delay (20000,20000,20000) L_0x2bd2ec0/d; -v0x2bbba20_0 .net "S", 0 0, L_0x2bd3090; 1 drivers -v0x2bbbac0_0 .alias "in0", 0 0, v0x2bbc150_0; -v0x2bbbb60_0 .alias "in1", 0 0, v0x2bbc620_0; -v0x2bbbc00_0 .net "nS", 0 0, L_0x2bd27f0; 1 drivers -v0x2bbbcb0_0 .net "out0", 0 0, L_0x2bd28b0; 1 drivers -v0x2bbbd50_0 .net "out1", 0 0, L_0x2bd2db0; 1 drivers -v0x2bbbe30_0 .alias "outfinal", 0 0, v0x2bbc200_0; -S_0x2bba530 .scope generate, "addbits[10]" "addbits[10]" 3 230, 3 230, S_0x2ba3100; - .timescale -9 -12; -P_0x2bb9f48 .param/l "i" 3 230, +C4<01010>; -S_0x2bba6a0 .scope module, "attempt" "MiddleAddSubSLT" 3 232, 3 89, S_0x2bba530; - .timescale -9 -12; -L_0x2bc91b0/d .functor NOT 1, L_0x2bd54e0, C4<0>, C4<0>, C4<0>; -L_0x2bc91b0 .delay (10000,10000,10000) L_0x2bc91b0/d; -L_0x2bd4840/d .functor NOT 1, L_0x2bd4900, C4<0>, C4<0>, C4<0>; -L_0x2bd4840 .delay (10000,10000,10000) L_0x2bd4840/d; -L_0x2bd49a0/d .functor AND 1, L_0x2bd4ae0, L_0x2bd4840, C4<1>, C4<1>; -L_0x2bd49a0 .delay (20000,20000,20000) L_0x2bd49a0/d; -L_0x2bd4b80/d .functor XOR 1, L_0x2bd4450, L_0x2bd45d0, C4<0>, C4<0>; -L_0x2bd4b80 .delay (40000,40000,40000) L_0x2bd4b80/d; -L_0x2bd4c70/d .functor XOR 1, L_0x2bd4b80, L_0x2bd5610, C4<0>, C4<0>; -L_0x2bd4c70 .delay (40000,40000,40000) L_0x2bd4c70/d; -L_0x2bd4d60/d .functor AND 1, L_0x2bd4450, L_0x2bd45d0, C4<1>, C4<1>; -L_0x2bd4d60 .delay (20000,20000,20000) L_0x2bd4d60/d; -L_0x2bd4ed0/d .functor AND 1, L_0x2bd4b80, L_0x2bd5610, C4<1>, C4<1>; -L_0x2bd4ed0 .delay (20000,20000,20000) L_0x2bd4ed0/d; -L_0x2bd4fc0/d .functor OR 1, L_0x2bd4d60, L_0x2bd4ed0, C4<0>, C4<0>; -L_0x2bd4fc0 .delay (20000,20000,20000) L_0x2bd4fc0/d; -v0x2bbad30_0 .net "A", 0 0, L_0x2bd4450; 1 drivers -v0x2bbadf0_0 .net "AandB", 0 0, L_0x2bd4d60; 1 drivers -v0x2bbae90_0 .net "AddSubSLTSum", 0 0, L_0x2bd4c70; 1 drivers -v0x2bbaf30_0 .net "AxorB", 0 0, L_0x2bd4b80; 1 drivers -v0x2bbafb0_0 .net "B", 0 0, L_0x2bd54e0; 1 drivers -v0x2bbb060_0 .net "BornB", 0 0, L_0x2bd45d0; 1 drivers -v0x2bbb120_0 .net "CINandAxorB", 0 0, L_0x2bd4ed0; 1 drivers -v0x2bbb1a0_0 .alias "Command", 2 0, v0x2bc67a0_0; -v0x2bbb220_0 .net *"_s3", 0 0, L_0x2bd4900; 1 drivers -v0x2bbb2a0_0 .net *"_s5", 0 0, L_0x2bd4ae0; 1 drivers -v0x2bbb340_0 .net "carryin", 0 0, L_0x2bd5610; 1 drivers -v0x2bbb3e0_0 .net "carryout", 0 0, L_0x2bd4fc0; 1 drivers -v0x2bbb480_0 .net "nB", 0 0, L_0x2bc91b0; 1 drivers -v0x2bbb530_0 .net "nCmd2", 0 0, L_0x2bd4840; 1 drivers -v0x2bbb630_0 .net "subtract", 0 0, L_0x2bd49a0; 1 drivers -L_0x2bd47a0 .part v0x2bc78e0_0, 0, 1; -L_0x2bd4900 .part v0x2bc78e0_0, 2, 1; -L_0x2bd4ae0 .part v0x2bc78e0_0, 0, 1; -S_0x2bba790 .scope module, "mux0" "TwoInMux" 3 105, 3 8, S_0x2bba6a0; - .timescale -9 -12; -L_0x2bc9350/d .functor NOT 1, L_0x2bd47a0, C4<0>, C4<0>, C4<0>; -L_0x2bc9350 .delay (10000,10000,10000) L_0x2bc9350/d; -L_0x2bd3fe0/d .functor AND 1, L_0x2bd54e0, L_0x2bc9350, C4<1>, C4<1>; -L_0x2bd3fe0 .delay (20000,20000,20000) L_0x2bd3fe0/d; -L_0x2bd40f0/d .functor AND 1, L_0x2bc91b0, L_0x2bd47a0, C4<1>, C4<1>; -L_0x2bd40f0 .delay (20000,20000,20000) L_0x2bd40f0/d; -L_0x2bd45d0/d .functor OR 1, L_0x2bd3fe0, L_0x2bd40f0, C4<0>, C4<0>; -L_0x2bd45d0 .delay (20000,20000,20000) L_0x2bd45d0/d; -v0x2bba880_0 .net "S", 0 0, L_0x2bd47a0; 1 drivers -v0x2bba920_0 .alias "in0", 0 0, v0x2bbafb0_0; -v0x2bba9c0_0 .alias "in1", 0 0, v0x2bbb480_0; -v0x2bbaa60_0 .net "nS", 0 0, L_0x2bc9350; 1 drivers -v0x2bbab10_0 .net "out0", 0 0, L_0x2bd3fe0; 1 drivers -v0x2bbabb0_0 .net "out1", 0 0, L_0x2bd40f0; 1 drivers -v0x2bbac90_0 .alias "outfinal", 0 0, v0x2bbb060_0; -S_0x2bb9390 .scope generate, "addbits[11]" "addbits[11]" 3 230, 3 230, S_0x2ba3100; - .timescale -9 -12; -P_0x2bb8da8 .param/l "i" 3 230, +C4<01011>; -S_0x2bb9500 .scope module, "attempt" "MiddleAddSubSLT" 3 232, 3 89, S_0x2bb9390; - .timescale -9 -12; -L_0x2bd5300/d .functor NOT 1, L_0x2bd6a20, C4<0>, C4<0>, C4<0>; -L_0x2bd5300 .delay (10000,10000,10000) L_0x2bd5300/d; -L_0x2bd5d50/d .functor NOT 1, L_0x2bd5e10, C4<0>, C4<0>, C4<0>; -L_0x2bd5d50 .delay (10000,10000,10000) L_0x2bd5d50/d; -L_0x2bd5eb0/d .functor AND 1, L_0x2bd5ff0, L_0x2bd5d50, C4<1>, C4<1>; -L_0x2bd5eb0 .delay (20000,20000,20000) L_0x2bd5eb0/d; -L_0x2bd6090/d .functor XOR 1, L_0x2bd57a0, L_0x2bd5ae0, C4<0>, C4<0>; -L_0x2bd6090 .delay (40000,40000,40000) L_0x2bd6090/d; -L_0x2bd6180/d .functor XOR 1, L_0x2bd6090, L_0x2bd6b50, C4<0>, C4<0>; -L_0x2bd6180 .delay (40000,40000,40000) L_0x2bd6180/d; -L_0x2bd6270/d .functor AND 1, L_0x2bd57a0, L_0x2bd5ae0, C4<1>, C4<1>; -L_0x2bd6270 .delay (20000,20000,20000) L_0x2bd6270/d; -L_0x2bd63e0/d .functor AND 1, L_0x2bd6090, L_0x2bd6b50, C4<1>, C4<1>; -L_0x2bd63e0 .delay (20000,20000,20000) L_0x2bd63e0/d; -L_0x2bd64d0/d .functor OR 1, L_0x2bd6270, L_0x2bd63e0, C4<0>, C4<0>; -L_0x2bd64d0 .delay (20000,20000,20000) L_0x2bd64d0/d; -v0x2bb9b90_0 .net "A", 0 0, L_0x2bd57a0; 1 drivers -v0x2bb9c50_0 .net "AandB", 0 0, L_0x2bd6270; 1 drivers -v0x2bb9cf0_0 .net "AddSubSLTSum", 0 0, L_0x2bd6180; 1 drivers -v0x2bb9d90_0 .net "AxorB", 0 0, L_0x2bd6090; 1 drivers -v0x2bb9e10_0 .net "B", 0 0, L_0x2bd6a20; 1 drivers -v0x2bb9ec0_0 .net "BornB", 0 0, L_0x2bd5ae0; 1 drivers -v0x2bb9f80_0 .net "CINandAxorB", 0 0, L_0x2bd63e0; 1 drivers -v0x2bba000_0 .alias "Command", 2 0, v0x2bc67a0_0; -v0x2bba080_0 .net *"_s3", 0 0, L_0x2bd5e10; 1 drivers -v0x2bba100_0 .net *"_s5", 0 0, L_0x2bd5ff0; 1 drivers -v0x2bba1a0_0 .net "carryin", 0 0, L_0x2bd6b50; 1 drivers -v0x2bba240_0 .net "carryout", 0 0, L_0x2bd64d0; 1 drivers -v0x2bba2e0_0 .net "nB", 0 0, L_0x2bd5300; 1 drivers -v0x2bba390_0 .net "nCmd2", 0 0, L_0x2bd5d50; 1 drivers -v0x2bba490_0 .net "subtract", 0 0, L_0x2bd5eb0; 1 drivers -L_0x2bd5cb0 .part v0x2bc78e0_0, 0, 1; -L_0x2bd5e10 .part v0x2bc78e0_0, 2, 1; -L_0x2bd5ff0 .part v0x2bc78e0_0, 0, 1; -S_0x2bb95f0 .scope module, "mux0" "TwoInMux" 3 105, 3 8, S_0x2bb9500; - .timescale -9 -12; -L_0x2bd5460/d .functor NOT 1, L_0x2bd5cb0, C4<0>, C4<0>, C4<0>; -L_0x2bd5460 .delay (10000,10000,10000) L_0x2bd5460/d; -L_0x2bd58e0/d .functor AND 1, L_0x2bd6a20, L_0x2bd5460, C4<1>, C4<1>; -L_0x2bd58e0 .delay (20000,20000,20000) L_0x2bd58e0/d; -L_0x2bd59d0/d .functor AND 1, L_0x2bd5300, L_0x2bd5cb0, C4<1>, C4<1>; -L_0x2bd59d0 .delay (20000,20000,20000) L_0x2bd59d0/d; -L_0x2bd5ae0/d .functor OR 1, L_0x2bd58e0, L_0x2bd59d0, C4<0>, C4<0>; -L_0x2bd5ae0 .delay (20000,20000,20000) L_0x2bd5ae0/d; -v0x2bb96e0_0 .net "S", 0 0, L_0x2bd5cb0; 1 drivers -v0x2bb9780_0 .alias "in0", 0 0, v0x2bb9e10_0; -v0x2bb9820_0 .alias "in1", 0 0, v0x2bba2e0_0; -v0x2bb98c0_0 .net "nS", 0 0, L_0x2bd5460; 1 drivers -v0x2bb9970_0 .net "out0", 0 0, L_0x2bd58e0; 1 drivers -v0x2bb9a10_0 .net "out1", 0 0, L_0x2bd59d0; 1 drivers -v0x2bb9af0_0 .alias "outfinal", 0 0, v0x2bb9ec0_0; -S_0x2bb81f0 .scope generate, "addbits[12]" "addbits[12]" 3 230, 3 230, S_0x2ba3100; - .timescale -9 -12; -P_0x2bb7c08 .param/l "i" 3 230, +C4<01100>; -S_0x2bb8360 .scope module, "attempt" "MiddleAddSubSLT" 3 232, 3 89, S_0x2bb81f0; - .timescale -9 -12; -L_0x2bd5840/d .functor NOT 1, L_0x2bd7f60, C4<0>, C4<0>, C4<0>; -L_0x2bd5840 .delay (10000,10000,10000) L_0x2bd5840/d; -L_0x2bd7260/d .functor NOT 1, L_0x2bd7320, C4<0>, C4<0>, C4<0>; -L_0x2bd7260 .delay (10000,10000,10000) L_0x2bd7260/d; -L_0x2bd73c0/d .functor AND 1, L_0x2bd7500, L_0x2bd7260, C4<1>, C4<1>; -L_0x2bd73c0 .delay (20000,20000,20000) L_0x2bd73c0/d; -L_0x2bd75a0/d .functor XOR 1, L_0x2bd6ce0, L_0x2bd6ff0, C4<0>, C4<0>; -L_0x2bd75a0 .delay (40000,40000,40000) L_0x2bd75a0/d; -L_0x2bd7690/d .functor XOR 1, L_0x2bd75a0, L_0x2bd8000, C4<0>, C4<0>; -L_0x2bd7690 .delay (40000,40000,40000) L_0x2bd7690/d; -L_0x2bd7780/d .functor AND 1, L_0x2bd6ce0, L_0x2bd6ff0, C4<1>, C4<1>; -L_0x2bd7780 .delay (20000,20000,20000) L_0x2bd7780/d; -L_0x2bd78f0/d .functor AND 1, L_0x2bd75a0, L_0x2bd8000, C4<1>, C4<1>; -L_0x2bd78f0 .delay (20000,20000,20000) L_0x2bd78f0/d; -L_0x2bd79e0/d .functor OR 1, L_0x2bd7780, L_0x2bd78f0, C4<0>, C4<0>; -L_0x2bd79e0 .delay (20000,20000,20000) L_0x2bd79e0/d; -v0x2bb89f0_0 .net "A", 0 0, L_0x2bd6ce0; 1 drivers -v0x2bb8ab0_0 .net "AandB", 0 0, L_0x2bd7780; 1 drivers -v0x2bb8b50_0 .net "AddSubSLTSum", 0 0, L_0x2bd7690; 1 drivers -v0x2bb8bf0_0 .net "AxorB", 0 0, L_0x2bd75a0; 1 drivers -v0x2bb8c70_0 .net "B", 0 0, L_0x2bd7f60; 1 drivers -v0x2bb8d20_0 .net "BornB", 0 0, L_0x2bd6ff0; 1 drivers -v0x2bb8de0_0 .net "CINandAxorB", 0 0, L_0x2bd78f0; 1 drivers -v0x2bb8e60_0 .alias "Command", 2 0, v0x2bc67a0_0; -v0x2bb8ee0_0 .net *"_s3", 0 0, L_0x2bd7320; 1 drivers -v0x2bb8f60_0 .net *"_s5", 0 0, L_0x2bd7500; 1 drivers -v0x2bb9000_0 .net "carryin", 0 0, L_0x2bd8000; 1 drivers -v0x2bb90a0_0 .net "carryout", 0 0, L_0x2bd79e0; 1 drivers -v0x2bb9140_0 .net "nB", 0 0, L_0x2bd5840; 1 drivers -v0x2bb91f0_0 .net "nCmd2", 0 0, L_0x2bd7260; 1 drivers -v0x2bb92f0_0 .net "subtract", 0 0, L_0x2bd73c0; 1 drivers -L_0x2bd71c0 .part v0x2bc78e0_0, 0, 1; -L_0x2bd7320 .part v0x2bc78e0_0, 2, 1; -L_0x2bd7500 .part v0x2bc78e0_0, 0, 1; -S_0x2bb8450 .scope module, "mux0" "TwoInMux" 3 105, 3 8, S_0x2bb8360; - .timescale -9 -12; -L_0x2bd6910/d .functor NOT 1, L_0x2bd71c0, C4<0>, C4<0>, C4<0>; -L_0x2bd6910 .delay (10000,10000,10000) L_0x2bd6910/d; -L_0x2bd6e10/d .functor AND 1, L_0x2bd7f60, L_0x2bd6910, C4<1>, C4<1>; -L_0x2bd6e10 .delay (20000,20000,20000) L_0x2bd6e10/d; -L_0x2bd6f00/d .functor AND 1, L_0x2bd5840, L_0x2bd71c0, C4<1>, C4<1>; -L_0x2bd6f00 .delay (20000,20000,20000) L_0x2bd6f00/d; -L_0x2bd6ff0/d .functor OR 1, L_0x2bd6e10, L_0x2bd6f00, C4<0>, C4<0>; -L_0x2bd6ff0 .delay (20000,20000,20000) L_0x2bd6ff0/d; -v0x2bb8540_0 .net "S", 0 0, L_0x2bd71c0; 1 drivers -v0x2bb85e0_0 .alias "in0", 0 0, v0x2bb8c70_0; -v0x2bb8680_0 .alias "in1", 0 0, v0x2bb9140_0; -v0x2bb8720_0 .net "nS", 0 0, L_0x2bd6910; 1 drivers -v0x2bb87d0_0 .net "out0", 0 0, L_0x2bd6e10; 1 drivers -v0x2bb8870_0 .net "out1", 0 0, L_0x2bd6f00; 1 drivers -v0x2bb8950_0 .alias "outfinal", 0 0, v0x2bb8d20_0; -S_0x2bb7050 .scope generate, "addbits[13]" "addbits[13]" 3 230, 3 230, S_0x2ba3100; - .timescale -9 -12; -P_0x2bb6a68 .param/l "i" 3 230, +C4<01101>; -S_0x2bb71c0 .scope module, "attempt" "MiddleAddSubSLT" 3 232, 3 89, S_0x2bb7050; - .timescale -9 -12; -L_0x2bd7d20/d .functor NOT 1, L_0x2bd8140, C4<0>, C4<0>, C4<0>; -L_0x2bd7d20 .delay (10000,10000,10000) L_0x2bd7d20/d; -L_0x2bd8760/d .functor NOT 1, L_0x2bd8820, C4<0>, C4<0>, C4<0>; -L_0x2bd8760 .delay (10000,10000,10000) L_0x2bd8760/d; -L_0x2bd88c0/d .functor AND 1, L_0x2bd8a00, L_0x2bd8760, C4<1>, C4<1>; -L_0x2bd88c0 .delay (20000,20000,20000) L_0x2bd88c0/d; -L_0x2bd8aa0/d .functor XOR 1, L_0x2bce760, L_0x2bd84f0, C4<0>, C4<0>; -L_0x2bd8aa0 .delay (40000,40000,40000) L_0x2bd8aa0/d; -L_0x2bd8b90/d .functor XOR 1, L_0x2bd8aa0, L_0x2bd9340, C4<0>, C4<0>; -L_0x2bd8b90 .delay (40000,40000,40000) L_0x2bd8b90/d; -L_0x2bd8c80/d .functor AND 1, L_0x2bce760, L_0x2bd84f0, C4<1>, C4<1>; -L_0x2bd8c80 .delay (20000,20000,20000) L_0x2bd8c80/d; -L_0x2bd8df0/d .functor AND 1, L_0x2bd8aa0, L_0x2bd9340, C4<1>, C4<1>; -L_0x2bd8df0 .delay (20000,20000,20000) L_0x2bd8df0/d; -L_0x2bd8ee0/d .functor OR 1, L_0x2bd8c80, L_0x2bd8df0, C4<0>, C4<0>; -L_0x2bd8ee0 .delay (20000,20000,20000) L_0x2bd8ee0/d; -v0x2bb7850_0 .net "A", 0 0, L_0x2bce760; 1 drivers -v0x2bb7910_0 .net "AandB", 0 0, L_0x2bd8c80; 1 drivers -v0x2bb79b0_0 .net "AddSubSLTSum", 0 0, L_0x2bd8b90; 1 drivers -v0x2bb7a50_0 .net "AxorB", 0 0, L_0x2bd8aa0; 1 drivers -v0x2bb7ad0_0 .net "B", 0 0, L_0x2bd8140; 1 drivers -v0x2bb7b80_0 .net "BornB", 0 0, L_0x2bd84f0; 1 drivers -v0x2bb7c40_0 .net "CINandAxorB", 0 0, L_0x2bd8df0; 1 drivers -v0x2bb7cc0_0 .alias "Command", 2 0, v0x2bc67a0_0; -v0x2bb7d40_0 .net *"_s3", 0 0, L_0x2bd8820; 1 drivers -v0x2bb7dc0_0 .net *"_s5", 0 0, L_0x2bd8a00; 1 drivers -v0x2bb7e60_0 .net "carryin", 0 0, L_0x2bd9340; 1 drivers -v0x2bb7f00_0 .net "carryout", 0 0, L_0x2bd8ee0; 1 drivers -v0x2bb7fa0_0 .net "nB", 0 0, L_0x2bd7d20; 1 drivers -v0x2bb8050_0 .net "nCmd2", 0 0, L_0x2bd8760; 1 drivers -v0x2bb8150_0 .net "subtract", 0 0, L_0x2bd88c0; 1 drivers -L_0x2bd86c0 .part v0x2bc78e0_0, 0, 1; -L_0x2bd8820 .part v0x2bc78e0_0, 2, 1; -L_0x2bd8a00 .part v0x2bc78e0_0, 0, 1; -S_0x2bb72b0 .scope module, "mux0" "TwoInMux" 3 105, 3 8, S_0x2bb71c0; - .timescale -9 -12; -L_0x2bd7e80/d .functor NOT 1, L_0x2bd86c0, C4<0>, C4<0>, C4<0>; -L_0x2bd7e80 .delay (10000,10000,10000) L_0x2bd7e80/d; -L_0x2bd82f0/d .functor AND 1, L_0x2bd8140, L_0x2bd7e80, C4<1>, C4<1>; -L_0x2bd82f0 .delay (20000,20000,20000) L_0x2bd82f0/d; -L_0x2bd83e0/d .functor AND 1, L_0x2bd7d20, L_0x2bd86c0, C4<1>, C4<1>; -L_0x2bd83e0 .delay (20000,20000,20000) L_0x2bd83e0/d; -L_0x2bd84f0/d .functor OR 1, L_0x2bd82f0, L_0x2bd83e0, C4<0>, C4<0>; -L_0x2bd84f0 .delay (20000,20000,20000) L_0x2bd84f0/d; -v0x2bb73a0_0 .net "S", 0 0, L_0x2bd86c0; 1 drivers -v0x2bb7440_0 .alias "in0", 0 0, v0x2bb7ad0_0; -v0x2bb74e0_0 .alias "in1", 0 0, v0x2bb7fa0_0; -v0x2bb7580_0 .net "nS", 0 0, L_0x2bd7e80; 1 drivers -v0x2bb7630_0 .net "out0", 0 0, L_0x2bd82f0; 1 drivers -v0x2bb76d0_0 .net "out1", 0 0, L_0x2bd83e0; 1 drivers -v0x2bb77b0_0 .alias "outfinal", 0 0, v0x2bb7b80_0; -S_0x2bb5eb0 .scope generate, "addbits[14]" "addbits[14]" 3 230, 3 230, S_0x2ba3100; - .timescale -9 -12; -P_0x2bb58c8 .param/l "i" 3 230, +C4<01110>; -S_0x2bb6020 .scope module, "attempt" "MiddleAddSubSLT" 3 232, 3 89, S_0x2bb5eb0; - .timescale -9 -12; -L_0x2bd93e0/d .functor NOT 1, L_0x2bd9940, C4<0>, C4<0>, C4<0>; -L_0x2bd93e0 .delay (10000,10000,10000) L_0x2bd93e0/d; -L_0x2bd9e60/d .functor NOT 1, L_0x2bd9f20, C4<0>, C4<0>, C4<0>; -L_0x2bd9e60 .delay (10000,10000,10000) L_0x2bd9e60/d; -L_0x2bd9fc0/d .functor AND 1, L_0x2bda100, L_0x2bd9e60, C4<1>, C4<1>; -L_0x2bd9fc0 .delay (20000,20000,20000) L_0x2bd9fc0/d; -L_0x2bda1a0/d .functor XOR 1, L_0x2bd98a0, L_0x2bd9bf0, C4<0>, C4<0>; -L_0x2bda1a0 .delay (40000,40000,40000) L_0x2bda1a0/d; -L_0x2bda290/d .functor XOR 1, L_0x2bda1a0, L_0x2bdac50, C4<0>, C4<0>; -L_0x2bda290 .delay (40000,40000,40000) L_0x2bda290/d; -L_0x2bda380/d .functor AND 1, L_0x2bd98a0, L_0x2bd9bf0, C4<1>, C4<1>; -L_0x2bda380 .delay (20000,20000,20000) L_0x2bda380/d; -L_0x2bda4f0/d .functor AND 1, L_0x2bda1a0, L_0x2bdac50, C4<1>, C4<1>; -L_0x2bda4f0 .delay (20000,20000,20000) L_0x2bda4f0/d; -L_0x2bda5e0/d .functor OR 1, L_0x2bda380, L_0x2bda4f0, C4<0>, C4<0>; -L_0x2bda5e0 .delay (20000,20000,20000) L_0x2bda5e0/d; -v0x2bb66b0_0 .net "A", 0 0, L_0x2bd98a0; 1 drivers -v0x2bb6770_0 .net "AandB", 0 0, L_0x2bda380; 1 drivers -v0x2bb6810_0 .net "AddSubSLTSum", 0 0, L_0x2bda290; 1 drivers -v0x2bb68b0_0 .net "AxorB", 0 0, L_0x2bda1a0; 1 drivers -v0x2bb6930_0 .net "B", 0 0, L_0x2bd9940; 1 drivers -v0x2bb69e0_0 .net "BornB", 0 0, L_0x2bd9bf0; 1 drivers -v0x2bb6aa0_0 .net "CINandAxorB", 0 0, L_0x2bda4f0; 1 drivers -v0x2bb6b20_0 .alias "Command", 2 0, v0x2bc67a0_0; -v0x2bb6ba0_0 .net *"_s3", 0 0, L_0x2bd9f20; 1 drivers -v0x2bb6c20_0 .net *"_s5", 0 0, L_0x2bda100; 1 drivers -v0x2bb6cc0_0 .net "carryin", 0 0, L_0x2bdac50; 1 drivers -v0x2bb6d60_0 .net "carryout", 0 0, L_0x2bda5e0; 1 drivers -v0x2bb6e00_0 .net "nB", 0 0, L_0x2bd93e0; 1 drivers -v0x2bb6eb0_0 .net "nCmd2", 0 0, L_0x2bd9e60; 1 drivers -v0x2bb6fb0_0 .net "subtract", 0 0, L_0x2bd9fc0; 1 drivers -L_0x2bd9dc0 .part v0x2bc78e0_0, 0, 1; -L_0x2bd9f20 .part v0x2bc78e0_0, 2, 1; -L_0x2bda100 .part v0x2bc78e0_0, 0, 1; -S_0x2bb6110 .scope module, "mux0" "TwoInMux" 3 105, 3 8, S_0x2bb6020; - .timescale -9 -12; -L_0x2bd9500/d .functor NOT 1, L_0x2bd9dc0, C4<0>, C4<0>, C4<0>; -L_0x2bd9500 .delay (10000,10000,10000) L_0x2bd9500/d; -L_0x2bd9a30/d .functor AND 1, L_0x2bd9940, L_0x2bd9500, C4<1>, C4<1>; -L_0x2bd9a30 .delay (20000,20000,20000) L_0x2bd9a30/d; -L_0x2bd9ae0/d .functor AND 1, L_0x2bd93e0, L_0x2bd9dc0, C4<1>, C4<1>; -L_0x2bd9ae0 .delay (20000,20000,20000) L_0x2bd9ae0/d; -L_0x2bd9bf0/d .functor OR 1, L_0x2bd9a30, L_0x2bd9ae0, C4<0>, C4<0>; -L_0x2bd9bf0 .delay (20000,20000,20000) L_0x2bd9bf0/d; -v0x2bb6200_0 .net "S", 0 0, L_0x2bd9dc0; 1 drivers -v0x2bb62a0_0 .alias "in0", 0 0, v0x2bb6930_0; -v0x2bb6340_0 .alias "in1", 0 0, v0x2bb6e00_0; -v0x2bb63e0_0 .net "nS", 0 0, L_0x2bd9500; 1 drivers -v0x2bb6490_0 .net "out0", 0 0, L_0x2bd9a30; 1 drivers -v0x2bb6530_0 .net "out1", 0 0, L_0x2bd9ae0; 1 drivers -v0x2bb6610_0 .alias "outfinal", 0 0, v0x2bb69e0_0; -S_0x2bb4d10 .scope generate, "addbits[15]" "addbits[15]" 3 230, 3 230, S_0x2ba3100; - .timescale -9 -12; -P_0x2bb4728 .param/l "i" 3 230, +C4<01111>; -S_0x2bb4e80 .scope module, "attempt" "MiddleAddSubSLT" 3 232, 3 89, S_0x2bb4d10; - .timescale -9 -12; -L_0x2bda920/d .functor NOT 1, L_0x2bdae80, C4<0>, C4<0>, C4<0>; -L_0x2bda920 .delay (10000,10000,10000) L_0x2bda920/d; -L_0x2bdb370/d .functor NOT 1, L_0x2bdb430, C4<0>, C4<0>, C4<0>; -L_0x2bdb370 .delay (10000,10000,10000) L_0x2bdb370/d; -L_0x2bdb4d0/d .functor AND 1, L_0x2bdb610, L_0x2bdb370, C4<1>, C4<1>; -L_0x2bdb4d0 .delay (20000,20000,20000) L_0x2bdb4d0/d; -L_0x2bdb6b0/d .functor XOR 1, L_0x2bdade0, L_0x2bdb100, C4<0>, C4<0>; -L_0x2bdb6b0 .delay (40000,40000,40000) L_0x2bdb6b0/d; -L_0x2bdb7a0/d .functor XOR 1, L_0x2bdb6b0, L_0x2bdc190, C4<0>, C4<0>; -L_0x2bdb7a0 .delay (40000,40000,40000) L_0x2bdb7a0/d; -L_0x2bdb890/d .functor AND 1, L_0x2bdade0, L_0x2bdb100, C4<1>, C4<1>; -L_0x2bdb890 .delay (20000,20000,20000) L_0x2bdb890/d; -L_0x2bdba00/d .functor AND 1, L_0x2bdb6b0, L_0x2bdc190, C4<1>, C4<1>; -L_0x2bdba00 .delay (20000,20000,20000) L_0x2bdba00/d; -L_0x2bdbaf0/d .functor OR 1, L_0x2bdb890, L_0x2bdba00, C4<0>, C4<0>; -L_0x2bdbaf0 .delay (20000,20000,20000) L_0x2bdbaf0/d; -v0x2bb5510_0 .net "A", 0 0, L_0x2bdade0; 1 drivers -v0x2bb55d0_0 .net "AandB", 0 0, L_0x2bdb890; 1 drivers -v0x2bb5670_0 .net "AddSubSLTSum", 0 0, L_0x2bdb7a0; 1 drivers -v0x2bb5710_0 .net "AxorB", 0 0, L_0x2bdb6b0; 1 drivers -v0x2bb5790_0 .net "B", 0 0, L_0x2bdae80; 1 drivers -v0x2bb5840_0 .net "BornB", 0 0, L_0x2bdb100; 1 drivers -v0x2bb5900_0 .net "CINandAxorB", 0 0, L_0x2bdba00; 1 drivers -v0x2bb5980_0 .alias "Command", 2 0, v0x2bc67a0_0; -v0x2bb5a00_0 .net *"_s3", 0 0, L_0x2bdb430; 1 drivers -v0x2bb5a80_0 .net *"_s5", 0 0, L_0x2bdb610; 1 drivers -v0x2bb5b20_0 .net "carryin", 0 0, L_0x2bdc190; 1 drivers -v0x2bb5bc0_0 .net "carryout", 0 0, L_0x2bdbaf0; 1 drivers -v0x2bb5c60_0 .net "nB", 0 0, L_0x2bda920; 1 drivers -v0x2bb5d10_0 .net "nCmd2", 0 0, L_0x2bdb370; 1 drivers -v0x2bb5e10_0 .net "subtract", 0 0, L_0x2bdb4d0; 1 drivers -L_0x2bdb2d0 .part v0x2bc78e0_0, 0, 1; -L_0x2bdb430 .part v0x2bc78e0_0, 2, 1; -L_0x2bdb610 .part v0x2bc78e0_0, 0, 1; -S_0x2bb4f70 .scope module, "mux0" "TwoInMux" 3 105, 3 8, S_0x2bb4e80; - .timescale -9 -12; -L_0x2bdaa30/d .functor NOT 1, L_0x2bdb2d0, C4<0>, C4<0>, C4<0>; -L_0x2bdaa30 .delay (10000,10000,10000) L_0x2bdaa30/d; -L_0x2bdaaf0/d .functor AND 1, L_0x2bdae80, L_0x2bdaa30, C4<1>, C4<1>; -L_0x2bdaaf0 .delay (20000,20000,20000) L_0x2bdaaf0/d; -L_0x2bdaff0/d .functor AND 1, L_0x2bda920, L_0x2bdb2d0, C4<1>, C4<1>; -L_0x2bdaff0 .delay (20000,20000,20000) L_0x2bdaff0/d; -L_0x2bdb100/d .functor OR 1, L_0x2bdaaf0, L_0x2bdaff0, C4<0>, C4<0>; -L_0x2bdb100 .delay (20000,20000,20000) L_0x2bdb100/d; -v0x2bb5060_0 .net "S", 0 0, L_0x2bdb2d0; 1 drivers -v0x2bb5100_0 .alias "in0", 0 0, v0x2bb5790_0; -v0x2bb51a0_0 .alias "in1", 0 0, v0x2bb5c60_0; -v0x2bb5240_0 .net "nS", 0 0, L_0x2bdaa30; 1 drivers -v0x2bb52f0_0 .net "out0", 0 0, L_0x2bdaaf0; 1 drivers -v0x2bb5390_0 .net "out1", 0 0, L_0x2bdaff0; 1 drivers -v0x2bb5470_0 .alias "outfinal", 0 0, v0x2bb5840_0; -S_0x2bb3b70 .scope generate, "addbits[16]" "addbits[16]" 3 230, 3 230, S_0x2ba3100; - .timescale -9 -12; -P_0x2bb3588 .param/l "i" 3 230, +C4<010000>; -S_0x2bb3ce0 .scope module, "attempt" "MiddleAddSubSLT" 3 232, 3 89, S_0x2bb3b70; - .timescale -9 -12; -L_0x2bdaf20/d .functor NOT 1, L_0x2bdc3c0, C4<0>, C4<0>, C4<0>; -L_0x2bdaf20 .delay (10000,10000,10000) L_0x2bdaf20/d; -L_0x2bdc870/d .functor NOT 1, L_0x2bdc930, C4<0>, C4<0>, C4<0>; -L_0x2bdc870 .delay (10000,10000,10000) L_0x2bdc870/d; -L_0x2bdc9d0/d .functor AND 1, L_0x2bdcb10, L_0x2bdc870, C4<1>, C4<1>; -L_0x2bdc9d0 .delay (20000,20000,20000) L_0x2bdc9d0/d; -L_0x2bdcbb0/d .functor XOR 1, L_0x2bdc320, L_0x2bdc600, C4<0>, C4<0>; -L_0x2bdcbb0 .delay (40000,40000,40000) L_0x2bdcbb0/d; -L_0x2bdcca0/d .functor XOR 1, L_0x2bdcbb0, L_0x2bdd630, C4<0>, C4<0>; -L_0x2bdcca0 .delay (40000,40000,40000) L_0x2bdcca0/d; -L_0x2bdcd90/d .functor AND 1, L_0x2bdc320, L_0x2bdc600, C4<1>, C4<1>; -L_0x2bdcd90 .delay (20000,20000,20000) L_0x2bdcd90/d; -L_0x2bdcf00/d .functor AND 1, L_0x2bdcbb0, L_0x2bdd630, C4<1>, C4<1>; -L_0x2bdcf00 .delay (20000,20000,20000) L_0x2bdcf00/d; -L_0x2bdcff0/d .functor OR 1, L_0x2bdcd90, L_0x2bdcf00, C4<0>, C4<0>; -L_0x2bdcff0 .delay (20000,20000,20000) L_0x2bdcff0/d; -v0x2bb4370_0 .net "A", 0 0, L_0x2bdc320; 1 drivers -v0x2bb4430_0 .net "AandB", 0 0, L_0x2bdcd90; 1 drivers -v0x2bb44d0_0 .net "AddSubSLTSum", 0 0, L_0x2bdcca0; 1 drivers -v0x2bb4570_0 .net "AxorB", 0 0, L_0x2bdcbb0; 1 drivers -v0x2bb45f0_0 .net "B", 0 0, L_0x2bdc3c0; 1 drivers -v0x2bb46a0_0 .net "BornB", 0 0, L_0x2bdc600; 1 drivers -v0x2bb4760_0 .net "CINandAxorB", 0 0, L_0x2bdcf00; 1 drivers -v0x2bb47e0_0 .alias "Command", 2 0, v0x2bc67a0_0; -v0x2bb4860_0 .net *"_s3", 0 0, L_0x2bdc930; 1 drivers -v0x2bb48e0_0 .net *"_s5", 0 0, L_0x2bdcb10; 1 drivers -v0x2bb4980_0 .net "carryin", 0 0, L_0x2bdd630; 1 drivers -v0x2bb4a20_0 .net "carryout", 0 0, L_0x2bdcff0; 1 drivers -v0x2bb4ac0_0 .net "nB", 0 0, L_0x2bdaf20; 1 drivers -v0x2bb4b70_0 .net "nCmd2", 0 0, L_0x2bdc870; 1 drivers -v0x2bb4c70_0 .net "subtract", 0 0, L_0x2bdc9d0; 1 drivers -L_0x2bdc7d0 .part v0x2bc78e0_0, 0, 1; -L_0x2bdc930 .part v0x2bc78e0_0, 2, 1; -L_0x2bdcb10 .part v0x2bc78e0_0, 0, 1; -S_0x2bb3dd0 .scope module, "mux0" "TwoInMux" 3 105, 3 8, S_0x2bb3ce0; - .timescale -9 -12; -L_0x2bdbf10/d .functor NOT 1, L_0x2bdc7d0, C4<0>, C4<0>, C4<0>; -L_0x2bdbf10 .delay (10000,10000,10000) L_0x2bdbf10/d; -L_0x2bdbfd0/d .functor AND 1, L_0x2bdc3c0, L_0x2bdbf10, C4<1>, C4<1>; -L_0x2bdbfd0 .delay (20000,20000,20000) L_0x2bdbfd0/d; -L_0x2bdc510/d .functor AND 1, L_0x2bdaf20, L_0x2bdc7d0, C4<1>, C4<1>; -L_0x2bdc510 .delay (20000,20000,20000) L_0x2bdc510/d; -L_0x2bdc600/d .functor OR 1, L_0x2bdbfd0, L_0x2bdc510, C4<0>, C4<0>; -L_0x2bdc600 .delay (20000,20000,20000) L_0x2bdc600/d; -v0x2bb3ec0_0 .net "S", 0 0, L_0x2bdc7d0; 1 drivers -v0x2bb3f60_0 .alias "in0", 0 0, v0x2bb45f0_0; -v0x2bb4000_0 .alias "in1", 0 0, v0x2bb4ac0_0; -v0x2bb40a0_0 .net "nS", 0 0, L_0x2bdbf10; 1 drivers -v0x2bb4150_0 .net "out0", 0 0, L_0x2bdbfd0; 1 drivers -v0x2bb41f0_0 .net "out1", 0 0, L_0x2bdc510; 1 drivers -v0x2bb42d0_0 .alias "outfinal", 0 0, v0x2bb46a0_0; -S_0x2bb29d0 .scope generate, "addbits[17]" "addbits[17]" 3 230, 3 230, S_0x2ba3100; - .timescale -9 -12; -P_0x2bb23e8 .param/l "i" 3 230, +C4<010001>; -S_0x2bb2b40 .scope module, "attempt" "MiddleAddSubSLT" 3 232, 3 89, S_0x2bb29d0; - .timescale -9 -12; -L_0x2bc7450/d .functor NOT 1, L_0x2bddc70, C4<0>, C4<0>, C4<0>; -L_0x2bc7450 .delay (10000,10000,10000) L_0x2bc7450/d; -L_0x2bddee0/d .functor NOT 1, L_0x2bddf40, C4<0>, C4<0>, C4<0>; -L_0x2bddee0 .delay (10000,10000,10000) L_0x2bddee0/d; -L_0x2bddfe0/d .functor AND 1, L_0x2bde120, L_0x2bddee0, C4<1>, C4<1>; -L_0x2bddfe0 .delay (20000,20000,20000) L_0x2bddfe0/d; -L_0x2bde1c0/d .functor XOR 1, L_0x2bddbd0, L_0x2bdd490, C4<0>, C4<0>; -L_0x2bde1c0 .delay (40000,40000,40000) L_0x2bde1c0/d; -L_0x2bde2b0/d .functor XOR 1, L_0x2bde1c0, L_0x2bdec50, C4<0>, C4<0>; -L_0x2bde2b0 .delay (40000,40000,40000) L_0x2bde2b0/d; -L_0x2bde3a0/d .functor AND 1, L_0x2bddbd0, L_0x2bdd490, C4<1>, C4<1>; -L_0x2bde3a0 .delay (20000,20000,20000) L_0x2bde3a0/d; -L_0x2bde510/d .functor AND 1, L_0x2bde1c0, L_0x2bdec50, C4<1>, C4<1>; -L_0x2bde510 .delay (20000,20000,20000) L_0x2bde510/d; -L_0x2bde600/d .functor OR 1, L_0x2bde3a0, L_0x2bde510, C4<0>, C4<0>; -L_0x2bde600 .delay (20000,20000,20000) L_0x2bde600/d; -v0x2bb31d0_0 .net "A", 0 0, L_0x2bddbd0; 1 drivers -v0x2bb3290_0 .net "AandB", 0 0, L_0x2bde3a0; 1 drivers -v0x2bb3330_0 .net "AddSubSLTSum", 0 0, L_0x2bde2b0; 1 drivers -v0x2bb33d0_0 .net "AxorB", 0 0, L_0x2bde1c0; 1 drivers -v0x2bb3450_0 .net "B", 0 0, L_0x2bddc70; 1 drivers -v0x2bb3500_0 .net "BornB", 0 0, L_0x2bdd490; 1 drivers -v0x2bb35c0_0 .net "CINandAxorB", 0 0, L_0x2bde510; 1 drivers -v0x2bb3640_0 .alias "Command", 2 0, v0x2bc67a0_0; -v0x2bb36c0_0 .net *"_s3", 0 0, L_0x2bddf40; 1 drivers -v0x2bb3740_0 .net *"_s5", 0 0, L_0x2bde120; 1 drivers -v0x2bb37e0_0 .net "carryin", 0 0, L_0x2bdec50; 1 drivers -v0x2bb3880_0 .net "carryout", 0 0, L_0x2bde600; 1 drivers -v0x2bb3920_0 .net "nB", 0 0, L_0x2bc7450; 1 drivers -v0x2bb39d0_0 .net "nCmd2", 0 0, L_0x2bddee0; 1 drivers -v0x2bb3ad0_0 .net "subtract", 0 0, L_0x2bddfe0; 1 drivers -L_0x2bdde40 .part v0x2bc78e0_0, 0, 1; -L_0x2bddf40 .part v0x2bc78e0_0, 2, 1; -L_0x2bde120 .part v0x2bc78e0_0, 0, 1; -S_0x2bb2c30 .scope module, "mux0" "TwoInMux" 3 105, 3 8, S_0x2bb2b40; - .timescale -9 -12; -L_0x2bd2aa0/d .functor NOT 1, L_0x2bdde40, C4<0>, C4<0>, C4<0>; -L_0x2bd2aa0 .delay (10000,10000,10000) L_0x2bd2aa0/d; -L_0x2bd2b60/d .functor AND 1, L_0x2bddc70, L_0x2bd2aa0, C4<1>, C4<1>; -L_0x2bd2b60 .delay (20000,20000,20000) L_0x2bd2b60/d; -L_0x2bdd380/d .functor AND 1, L_0x2bc7450, L_0x2bdde40, C4<1>, C4<1>; -L_0x2bdd380 .delay (20000,20000,20000) L_0x2bdd380/d; -L_0x2bdd490/d .functor OR 1, L_0x2bd2b60, L_0x2bdd380, C4<0>, C4<0>; -L_0x2bdd490 .delay (20000,20000,20000) L_0x2bdd490/d; -v0x2bb2d20_0 .net "S", 0 0, L_0x2bdde40; 1 drivers -v0x2bb2dc0_0 .alias "in0", 0 0, v0x2bb3450_0; -v0x2bb2e60_0 .alias "in1", 0 0, v0x2bb3920_0; -v0x2bb2f00_0 .net "nS", 0 0, L_0x2bd2aa0; 1 drivers -v0x2bb2fb0_0 .net "out0", 0 0, L_0x2bd2b60; 1 drivers -v0x2bb3050_0 .net "out1", 0 0, L_0x2bdd380; 1 drivers -v0x2bb3130_0 .alias "outfinal", 0 0, v0x2bb3500_0; -S_0x2bb1830 .scope generate, "addbits[18]" "addbits[18]" 3 230, 3 230, S_0x2ba3100; - .timescale -9 -12; -P_0x2bb1248 .param/l "i" 3 230, +C4<010010>; -S_0x2bb19a0 .scope module, "attempt" "MiddleAddSubSLT" 3 232, 3 89, S_0x2bb1830; - .timescale -9 -12; -L_0x2bde920/d .functor NOT 1, L_0x2bdee80, C4<0>, C4<0>, C4<0>; -L_0x2bde920 .delay (10000,10000,10000) L_0x2bde920/d; -L_0x2bdf310/d .functor NOT 1, L_0x2bdf3b0, C4<0>, C4<0>, C4<0>; -L_0x2bdf310 .delay (10000,10000,10000) L_0x2bdf310/d; -L_0x2bdf450/d .functor AND 1, L_0x2bdf590, L_0x2bdf310, C4<1>, C4<1>; -L_0x2bdf450 .delay (20000,20000,20000) L_0x2bdf450/d; -L_0x2bdf630/d .functor XOR 1, L_0x2bdede0, L_0x2bdf0e0, C4<0>, C4<0>; -L_0x2bdf630 .delay (40000,40000,40000) L_0x2bdf630/d; -L_0x2bdf720/d .functor XOR 1, L_0x2bdf630, L_0x2be00f0, C4<0>, C4<0>; -L_0x2bdf720 .delay (40000,40000,40000) L_0x2bdf720/d; -L_0x2bdf810/d .functor AND 1, L_0x2bdede0, L_0x2bdf0e0, C4<1>, C4<1>; -L_0x2bdf810 .delay (20000,20000,20000) L_0x2bdf810/d; -L_0x2bdf980/d .functor AND 1, L_0x2bdf630, L_0x2be00f0, C4<1>, C4<1>; -L_0x2bdf980 .delay (20000,20000,20000) L_0x2bdf980/d; -L_0x2bdfa70/d .functor OR 1, L_0x2bdf810, L_0x2bdf980, C4<0>, C4<0>; -L_0x2bdfa70 .delay (20000,20000,20000) L_0x2bdfa70/d; -v0x2bb2030_0 .net "A", 0 0, L_0x2bdede0; 1 drivers -v0x2bb20f0_0 .net "AandB", 0 0, L_0x2bdf810; 1 drivers -v0x2bb2190_0 .net "AddSubSLTSum", 0 0, L_0x2bdf720; 1 drivers -v0x2bb2230_0 .net "AxorB", 0 0, L_0x2bdf630; 1 drivers -v0x2bb22b0_0 .net "B", 0 0, L_0x2bdee80; 1 drivers -v0x2bb2360_0 .net "BornB", 0 0, L_0x2bdf0e0; 1 drivers -v0x2bb2420_0 .net "CINandAxorB", 0 0, L_0x2bdf980; 1 drivers -v0x2bb24a0_0 .alias "Command", 2 0, v0x2bc67a0_0; -v0x2bb2520_0 .net *"_s3", 0 0, L_0x2bdf3b0; 1 drivers -v0x2bb25a0_0 .net *"_s5", 0 0, L_0x2bdf590; 1 drivers -v0x2bb2640_0 .net "carryin", 0 0, L_0x2be00f0; 1 drivers -v0x2bb26e0_0 .net "carryout", 0 0, L_0x2bdfa70; 1 drivers -v0x2bb2780_0 .net "nB", 0 0, L_0x2bde920; 1 drivers -v0x2bb2830_0 .net "nCmd2", 0 0, L_0x2bdf310; 1 drivers -v0x2bb2930_0 .net "subtract", 0 0, L_0x2bdf450; 1 drivers -L_0x2bdf270 .part v0x2bc78e0_0, 0, 1; -L_0x2bdf3b0 .part v0x2bc78e0_0, 2, 1; -L_0x2bdf590 .part v0x2bc78e0_0, 0, 1; -S_0x2bb1a90 .scope module, "mux0" "TwoInMux" 3 105, 3 8, S_0x2bb19a0; - .timescale -9 -12; -L_0x2bdea30/d .functor NOT 1, L_0x2bdf270, C4<0>, C4<0>, C4<0>; -L_0x2bdea30 .delay (10000,10000,10000) L_0x2bdea30/d; -L_0x2bdeaf0/d .functor AND 1, L_0x2bdee80, L_0x2bdea30, C4<1>, C4<1>; -L_0x2bdeaf0 .delay (20000,20000,20000) L_0x2bdeaf0/d; -L_0x2bdf030/d .functor AND 1, L_0x2bde920, L_0x2bdf270, C4<1>, C4<1>; -L_0x2bdf030 .delay (20000,20000,20000) L_0x2bdf030/d; -L_0x2bdf0e0/d .functor OR 1, L_0x2bdeaf0, L_0x2bdf030, C4<0>, C4<0>; -L_0x2bdf0e0 .delay (20000,20000,20000) L_0x2bdf0e0/d; -v0x2bb1b80_0 .net "S", 0 0, L_0x2bdf270; 1 drivers -v0x2bb1c20_0 .alias "in0", 0 0, v0x2bb22b0_0; -v0x2bb1cc0_0 .alias "in1", 0 0, v0x2bb2780_0; -v0x2bb1d60_0 .net "nS", 0 0, L_0x2bdea30; 1 drivers -v0x2bb1e10_0 .net "out0", 0 0, L_0x2bdeaf0; 1 drivers -v0x2bb1eb0_0 .net "out1", 0 0, L_0x2bdf030; 1 drivers -v0x2bb1f90_0 .alias "outfinal", 0 0, v0x2bb2360_0; -S_0x2bb0690 .scope generate, "addbits[19]" "addbits[19]" 3 230, 3 230, S_0x2ba3100; - .timescale -9 -12; -P_0x2bb00a8 .param/l "i" 3 230, +C4<010011>; -S_0x2bb0800 .scope module, "attempt" "MiddleAddSubSLT" 3 232, 3 89, S_0x2bb0690; - .timescale -9 -12; -L_0x2bdefb0/d .functor NOT 1, L_0x2be0320, C4<0>, C4<0>, C4<0>; -L_0x2bdefb0 .delay (10000,10000,10000) L_0x2bdefb0/d; -L_0x2be07c0/d .functor NOT 1, L_0x2be0860, C4<0>, C4<0>, C4<0>; -L_0x2be07c0 .delay (10000,10000,10000) L_0x2be07c0/d; -L_0x2be0900/d .functor AND 1, L_0x2be0a40, L_0x2be07c0, C4<1>, C4<1>; -L_0x2be0900 .delay (20000,20000,20000) L_0x2be0900/d; -L_0x2b87000/d .functor XOR 1, L_0x2be0280, L_0x2be0590, C4<0>, C4<0>; -L_0x2b87000 .delay (40000,40000,40000) L_0x2b87000/d; -L_0x2b870f0/d .functor XOR 1, L_0x2b87000, L_0x2be0450, C4<0>, C4<0>; -L_0x2b870f0 .delay (40000,40000,40000) L_0x2b870f0/d; -L_0x2b871e0/d .functor AND 1, L_0x2be0280, L_0x2be0590, C4<1>, C4<1>; -L_0x2b871e0 .delay (20000,20000,20000) L_0x2b871e0/d; -L_0x2b87350/d .functor AND 1, L_0x2b87000, L_0x2be0450, C4<1>, C4<1>; -L_0x2b87350 .delay (20000,20000,20000) L_0x2b87350/d; -L_0x2b87440/d .functor OR 1, L_0x2b871e0, L_0x2b87350, C4<0>, C4<0>; -L_0x2b87440 .delay (20000,20000,20000) L_0x2b87440/d; -v0x2bb0e90_0 .net "A", 0 0, L_0x2be0280; 1 drivers -v0x2bb0f50_0 .net "AandB", 0 0, L_0x2b871e0; 1 drivers -v0x2bb0ff0_0 .net "AddSubSLTSum", 0 0, L_0x2b870f0; 1 drivers -v0x2bb1090_0 .net "AxorB", 0 0, L_0x2b87000; 1 drivers -v0x2bb1110_0 .net "B", 0 0, L_0x2be0320; 1 drivers -v0x2bb11c0_0 .net "BornB", 0 0, L_0x2be0590; 1 drivers -v0x2bb1280_0 .net "CINandAxorB", 0 0, L_0x2b87350; 1 drivers -v0x2bb1300_0 .alias "Command", 2 0, v0x2bc67a0_0; -v0x2bb1380_0 .net *"_s3", 0 0, L_0x2be0860; 1 drivers -v0x2bb1400_0 .net *"_s5", 0 0, L_0x2be0a40; 1 drivers -v0x2bb14a0_0 .net "carryin", 0 0, L_0x2be0450; 1 drivers -v0x2bb1540_0 .net "carryout", 0 0, L_0x2b87440; 1 drivers -v0x2bb15e0_0 .net "nB", 0 0, L_0x2bdefb0; 1 drivers -v0x2bb1690_0 .net "nCmd2", 0 0, L_0x2be07c0; 1 drivers -v0x2bb1790_0 .net "subtract", 0 0, L_0x2be0900; 1 drivers -L_0x2be0720 .part v0x2bc78e0_0, 0, 1; -L_0x2be0860 .part v0x2bc78e0_0, 2, 1; -L_0x2be0a40 .part v0x2bc78e0_0, 0, 1; -S_0x2bb08f0 .scope module, "mux0" "TwoInMux" 3 105, 3 8, S_0x2bb0800; - .timescale -9 -12; -L_0x2bdfe70/d .functor NOT 1, L_0x2be0720, C4<0>, C4<0>, C4<0>; -L_0x2bdfe70 .delay (10000,10000,10000) L_0x2bdfe70/d; -L_0x2bdff30/d .functor AND 1, L_0x2be0320, L_0x2bdfe70, C4<1>, C4<1>; -L_0x2bdff30 .delay (20000,20000,20000) L_0x2bdff30/d; -L_0x2be0040/d .functor AND 1, L_0x2bdefb0, L_0x2be0720, C4<1>, C4<1>; -L_0x2be0040 .delay (20000,20000,20000) L_0x2be0040/d; -L_0x2be0590/d .functor OR 1, L_0x2bdff30, L_0x2be0040, C4<0>, C4<0>; -L_0x2be0590 .delay (20000,20000,20000) L_0x2be0590/d; -v0x2bb09e0_0 .net "S", 0 0, L_0x2be0720; 1 drivers -v0x2bb0a80_0 .alias "in0", 0 0, v0x2bb1110_0; -v0x2bb0b20_0 .alias "in1", 0 0, v0x2bb15e0_0; -v0x2bb0bc0_0 .net "nS", 0 0, L_0x2bdfe70; 1 drivers -v0x2bb0c70_0 .net "out0", 0 0, L_0x2bdff30; 1 drivers -v0x2bb0d10_0 .net "out1", 0 0, L_0x2be0040; 1 drivers -v0x2bb0df0_0 .alias "outfinal", 0 0, v0x2bb11c0_0; -S_0x2baf4f0 .scope generate, "addbits[20]" "addbits[20]" 3 230, 3 230, S_0x2ba3100; - .timescale -9 -12; -P_0x2baef08 .param/l "i" 3 230, +C4<010100>; -S_0x2baf660 .scope module, "attempt" "MiddleAddSubSLT" 3 232, 3 89, S_0x2baf4f0; - .timescale -9 -12; -L_0x2b87b20/d .functor NOT 1, L_0x2b87910, C4<0>, C4<0>, C4<0>; -L_0x2b87b20 .delay (10000,10000,10000) L_0x2b87b20/d; -L_0x2be2cc0/d .functor NOT 1, L_0x2be2d60, C4<0>, C4<0>, C4<0>; -L_0x2be2cc0 .delay (10000,10000,10000) L_0x2be2cc0/d; -L_0x2be2e00/d .functor AND 1, L_0x2be2f40, L_0x2be2cc0, C4<1>, C4<1>; -L_0x2be2e00 .delay (20000,20000,20000) L_0x2be2e00/d; -L_0x2be2fe0/d .functor XOR 1, L_0x2b87870, L_0x2b87f60, C4<0>, C4<0>; -L_0x2be2fe0 .delay (40000,40000,40000) L_0x2be2fe0/d; -L_0x2be30d0/d .functor XOR 1, L_0x2be2fe0, L_0x2b87a40, C4<0>, C4<0>; -L_0x2be30d0 .delay (40000,40000,40000) L_0x2be30d0/d; -L_0x2be31c0/d .functor AND 1, L_0x2b87870, L_0x2b87f60, C4<1>, C4<1>; -L_0x2be31c0 .delay (20000,20000,20000) L_0x2be31c0/d; -L_0x2be3330/d .functor AND 1, L_0x2be2fe0, L_0x2b87a40, C4<1>, C4<1>; -L_0x2be3330 .delay (20000,20000,20000) L_0x2be3330/d; -L_0x2be3420/d .functor OR 1, L_0x2be31c0, L_0x2be3330, C4<0>, C4<0>; -L_0x2be3420 .delay (20000,20000,20000) L_0x2be3420/d; -v0x2bafcf0_0 .net "A", 0 0, L_0x2b87870; 1 drivers -v0x2bafdb0_0 .net "AandB", 0 0, L_0x2be31c0; 1 drivers -v0x2bafe50_0 .net "AddSubSLTSum", 0 0, L_0x2be30d0; 1 drivers -v0x2bafef0_0 .net "AxorB", 0 0, L_0x2be2fe0; 1 drivers -v0x2baff70_0 .net "B", 0 0, L_0x2b87910; 1 drivers -v0x2bb0020_0 .net "BornB", 0 0, L_0x2b87f60; 1 drivers -v0x2bb00e0_0 .net "CINandAxorB", 0 0, L_0x2be3330; 1 drivers -v0x2bb0160_0 .alias "Command", 2 0, v0x2bc67a0_0; -v0x2bb01e0_0 .net *"_s3", 0 0, L_0x2be2d60; 1 drivers -v0x2bb0260_0 .net *"_s5", 0 0, L_0x2be2f40; 1 drivers -v0x2bb0300_0 .net "carryin", 0 0, L_0x2b87a40; 1 drivers -v0x2bb03a0_0 .net "carryout", 0 0, L_0x2be3420; 1 drivers -v0x2bb0440_0 .net "nB", 0 0, L_0x2b87b20; 1 drivers -v0x2bb04f0_0 .net "nCmd2", 0 0, L_0x2be2cc0; 1 drivers -v0x2bb05f0_0 .net "subtract", 0 0, L_0x2be2e00; 1 drivers -L_0x2be2c20 .part v0x2bc78e0_0, 0, 1; -L_0x2be2d60 .part v0x2bc78e0_0, 2, 1; -L_0x2be2f40 .part v0x2bc78e0_0, 0, 1; -S_0x2baf750 .scope module, "mux0" "TwoInMux" 3 105, 3 8, S_0x2baf660; - .timescale -9 -12; -L_0x2b87c80/d .functor NOT 1, L_0x2be2c20, C4<0>, C4<0>, C4<0>; -L_0x2b87c80 .delay (10000,10000,10000) L_0x2b87c80/d; -L_0x2b87d40/d .functor AND 1, L_0x2b87910, L_0x2b87c80, C4<1>, C4<1>; -L_0x2b87d40 .delay (20000,20000,20000) L_0x2b87d40/d; -L_0x2b87e50/d .functor AND 1, L_0x2b87b20, L_0x2be2c20, C4<1>, C4<1>; -L_0x2b87e50 .delay (20000,20000,20000) L_0x2b87e50/d; -L_0x2b87f60/d .functor OR 1, L_0x2b87d40, L_0x2b87e50, C4<0>, C4<0>; -L_0x2b87f60 .delay (20000,20000,20000) L_0x2b87f60/d; -v0x2baf840_0 .net "S", 0 0, L_0x2be2c20; 1 drivers -v0x2baf8e0_0 .alias "in0", 0 0, v0x2baff70_0; -v0x2baf980_0 .alias "in1", 0 0, v0x2bb0440_0; -v0x2bafa20_0 .net "nS", 0 0, L_0x2b87c80; 1 drivers -v0x2bafad0_0 .net "out0", 0 0, L_0x2b87d40; 1 drivers -v0x2bafb70_0 .net "out1", 0 0, L_0x2b87e50; 1 drivers -v0x2bafc50_0 .alias "outfinal", 0 0, v0x2bb0020_0; -S_0x2bae350 .scope generate, "addbits[21]" "addbits[21]" 3 230, 3 230, S_0x2ba3100; - .timescale -9 -12; -P_0x2badd68 .param/l "i" 3 230, +C4<010101>; -S_0x2bae4c0 .scope module, "attempt" "MiddleAddSubSLT" 3 232, 3 89, S_0x2bae350; - .timescale -9 -12; -L_0x2be3b10/d .functor NOT 1, L_0x2be38d0, C4<0>, C4<0>, C4<0>; -L_0x2be3b10 .delay (10000,10000,10000) L_0x2be3b10/d; -L_0x2be4080/d .functor NOT 1, L_0x2be4120, C4<0>, C4<0>, C4<0>; -L_0x2be4080 .delay (10000,10000,10000) L_0x2be4080/d; -L_0x2be41c0/d .functor AND 1, L_0x2be4300, L_0x2be4080, C4<1>, C4<1>; -L_0x2be41c0 .delay (20000,20000,20000) L_0x2be41c0/d; -L_0x2be43a0/d .functor XOR 1, L_0x2be3830, L_0x2be3e50, C4<0>, C4<0>; -L_0x2be43a0 .delay (40000,40000,40000) L_0x2be43a0/d; -L_0x2be4490/d .functor XOR 1, L_0x2be43a0, L_0x2be3a00, C4<0>, C4<0>; -L_0x2be4490 .delay (40000,40000,40000) L_0x2be4490/d; -L_0x2be4580/d .functor AND 1, L_0x2be3830, L_0x2be3e50, C4<1>, C4<1>; -L_0x2be4580 .delay (20000,20000,20000) L_0x2be4580/d; -L_0x2be46f0/d .functor AND 1, L_0x2be43a0, L_0x2be3a00, C4<1>, C4<1>; -L_0x2be46f0 .delay (20000,20000,20000) L_0x2be46f0/d; -L_0x2be47e0/d .functor OR 1, L_0x2be4580, L_0x2be46f0, C4<0>, C4<0>; -L_0x2be47e0 .delay (20000,20000,20000) L_0x2be47e0/d; -v0x2baeb50_0 .net "A", 0 0, L_0x2be3830; 1 drivers -v0x2baec10_0 .net "AandB", 0 0, L_0x2be4580; 1 drivers -v0x2baecb0_0 .net "AddSubSLTSum", 0 0, L_0x2be4490; 1 drivers -v0x2baed50_0 .net "AxorB", 0 0, L_0x2be43a0; 1 drivers -v0x2baedd0_0 .net "B", 0 0, L_0x2be38d0; 1 drivers -v0x2baee80_0 .net "BornB", 0 0, L_0x2be3e50; 1 drivers -v0x2baef40_0 .net "CINandAxorB", 0 0, L_0x2be46f0; 1 drivers -v0x2baefc0_0 .alias "Command", 2 0, v0x2bc67a0_0; -v0x2baf040_0 .net *"_s3", 0 0, L_0x2be4120; 1 drivers -v0x2baf0c0_0 .net *"_s5", 0 0, L_0x2be4300; 1 drivers -v0x2baf160_0 .net "carryin", 0 0, L_0x2be3a00; 1 drivers -v0x2baf200_0 .net "carryout", 0 0, L_0x2be47e0; 1 drivers -v0x2baf2a0_0 .net "nB", 0 0, L_0x2be3b10; 1 drivers -v0x2baf350_0 .net "nCmd2", 0 0, L_0x2be4080; 1 drivers -v0x2baf450_0 .net "subtract", 0 0, L_0x2be41c0; 1 drivers -L_0x2be3fe0 .part v0x2bc78e0_0, 0, 1; -L_0x2be4120 .part v0x2bc78e0_0, 2, 1; -L_0x2be4300 .part v0x2bc78e0_0, 0, 1; -S_0x2bae5b0 .scope module, "mux0" "TwoInMux" 3 105, 3 8, S_0x2bae4c0; - .timescale -9 -12; -L_0x2be3c10/d .functor NOT 1, L_0x2be3fe0, C4<0>, C4<0>, C4<0>; -L_0x2be3c10 .delay (10000,10000,10000) L_0x2be3c10/d; -L_0x2be3c70/d .functor AND 1, L_0x2be38d0, L_0x2be3c10, C4<1>, C4<1>; -L_0x2be3c70 .delay (20000,20000,20000) L_0x2be3c70/d; -L_0x2be3d60/d .functor AND 1, L_0x2be3b10, L_0x2be3fe0, C4<1>, C4<1>; -L_0x2be3d60 .delay (20000,20000,20000) L_0x2be3d60/d; -L_0x2be3e50/d .functor OR 1, L_0x2be3c70, L_0x2be3d60, C4<0>, C4<0>; -L_0x2be3e50 .delay (20000,20000,20000) L_0x2be3e50/d; -v0x2bae6a0_0 .net "S", 0 0, L_0x2be3fe0; 1 drivers -v0x2bae740_0 .alias "in0", 0 0, v0x2baedd0_0; -v0x2bae7e0_0 .alias "in1", 0 0, v0x2baf2a0_0; -v0x2bae880_0 .net "nS", 0 0, L_0x2be3c10; 1 drivers -v0x2bae930_0 .net "out0", 0 0, L_0x2be3c70; 1 drivers -v0x2bae9d0_0 .net "out1", 0 0, L_0x2be3d60; 1 drivers -v0x2baeab0_0 .alias "outfinal", 0 0, v0x2baee80_0; -S_0x2bad1b0 .scope generate, "addbits[22]" "addbits[22]" 3 230, 3 230, S_0x2ba3100; - .timescale -9 -12; -P_0x2bacbc8 .param/l "i" 3 230, +C4<010110>; -S_0x2bad320 .scope module, "attempt" "MiddleAddSubSLT" 3 232, 3 89, S_0x2bad1b0; - .timescale -9 -12; -L_0x2be3aa0/d .functor NOT 1, L_0x2be4c90, C4<0>, C4<0>, C4<0>; -L_0x2be3aa0 .delay (10000,10000,10000) L_0x2be3aa0/d; -L_0x2be5450/d .functor NOT 1, L_0x2be54f0, C4<0>, C4<0>, C4<0>; -L_0x2be5450 .delay (10000,10000,10000) L_0x2be5450/d; -L_0x2be5590/d .functor AND 1, L_0x2be56d0, L_0x2be5450, C4<1>, C4<1>; -L_0x2be5590 .delay (20000,20000,20000) L_0x2be5590/d; -L_0x2be5770/d .functor XOR 1, L_0x2be4bf0, L_0x2be5220, C4<0>, C4<0>; -L_0x2be5770 .delay (40000,40000,40000) L_0x2be5770/d; -L_0x2be5860/d .functor XOR 1, L_0x2be5770, L_0x2be4dc0, C4<0>, C4<0>; -L_0x2be5860 .delay (40000,40000,40000) L_0x2be5860/d; -L_0x2be5950/d .functor AND 1, L_0x2be4bf0, L_0x2be5220, C4<1>, C4<1>; -L_0x2be5950 .delay (20000,20000,20000) L_0x2be5950/d; -L_0x2be5ac0/d .functor AND 1, L_0x2be5770, L_0x2be4dc0, C4<1>, C4<1>; -L_0x2be5ac0 .delay (20000,20000,20000) L_0x2be5ac0/d; -L_0x2be5bb0/d .functor OR 1, L_0x2be5950, L_0x2be5ac0, C4<0>, C4<0>; -L_0x2be5bb0 .delay (20000,20000,20000) L_0x2be5bb0/d; -v0x2bad9b0_0 .net "A", 0 0, L_0x2be4bf0; 1 drivers -v0x2bada70_0 .net "AandB", 0 0, L_0x2be5950; 1 drivers -v0x2badb10_0 .net "AddSubSLTSum", 0 0, L_0x2be5860; 1 drivers -v0x2badbb0_0 .net "AxorB", 0 0, L_0x2be5770; 1 drivers -v0x2badc30_0 .net "B", 0 0, L_0x2be4c90; 1 drivers -v0x2badce0_0 .net "BornB", 0 0, L_0x2be5220; 1 drivers -v0x2badda0_0 .net "CINandAxorB", 0 0, L_0x2be5ac0; 1 drivers -v0x2bade20_0 .alias "Command", 2 0, v0x2bc67a0_0; -v0x2badea0_0 .net *"_s3", 0 0, L_0x2be54f0; 1 drivers -v0x2badf20_0 .net *"_s5", 0 0, L_0x2be56d0; 1 drivers -v0x2badfc0_0 .net "carryin", 0 0, L_0x2be4dc0; 1 drivers -v0x2bae060_0 .net "carryout", 0 0, L_0x2be5bb0; 1 drivers -v0x2bae100_0 .net "nB", 0 0, L_0x2be3aa0; 1 drivers -v0x2bae1b0_0 .net "nCmd2", 0 0, L_0x2be5450; 1 drivers -v0x2bae2b0_0 .net "subtract", 0 0, L_0x2be5590; 1 drivers -L_0x2be53b0 .part v0x2bc78e0_0, 0, 1; -L_0x2be54f0 .part v0x2bc78e0_0, 2, 1; -L_0x2be56d0 .part v0x2bc78e0_0, 0, 1; -S_0x2bad410 .scope module, "mux0" "TwoInMux" 3 105, 3 8, S_0x2bad320; - .timescale -9 -12; -L_0x2be4fa0/d .functor NOT 1, L_0x2be53b0, C4<0>, C4<0>, C4<0>; -L_0x2be4fa0 .delay (10000,10000,10000) L_0x2be4fa0/d; -L_0x2be5040/d .functor AND 1, L_0x2be4c90, L_0x2be4fa0, C4<1>, C4<1>; -L_0x2be5040 .delay (20000,20000,20000) L_0x2be5040/d; -L_0x2be5130/d .functor AND 1, L_0x2be3aa0, L_0x2be53b0, C4<1>, C4<1>; -L_0x2be5130 .delay (20000,20000,20000) L_0x2be5130/d; -L_0x2be5220/d .functor OR 1, L_0x2be5040, L_0x2be5130, C4<0>, C4<0>; -L_0x2be5220 .delay (20000,20000,20000) L_0x2be5220/d; -v0x2bad500_0 .net "S", 0 0, L_0x2be53b0; 1 drivers -v0x2bad5a0_0 .alias "in0", 0 0, v0x2badc30_0; -v0x2bad640_0 .alias "in1", 0 0, v0x2bae100_0; -v0x2bad6e0_0 .net "nS", 0 0, L_0x2be4fa0; 1 drivers -v0x2bad790_0 .net "out0", 0 0, L_0x2be5040; 1 drivers -v0x2bad830_0 .net "out1", 0 0, L_0x2be5130; 1 drivers -v0x2bad910_0 .alias "outfinal", 0 0, v0x2badce0_0; -S_0x2bac010 .scope generate, "addbits[23]" "addbits[23]" 3 230, 3 230, S_0x2ba3100; - .timescale -9 -12; -P_0x2baba28 .param/l "i" 3 230, +C4<010111>; -S_0x2bac180 .scope module, "attempt" "MiddleAddSubSLT" 3 232, 3 89, S_0x2bac010; - .timescale -9 -12; -L_0x2be4e60/d .functor NOT 1, L_0x2be6060, C4<0>, C4<0>, C4<0>; -L_0x2be4e60 .delay (10000,10000,10000) L_0x2be4e60/d; -L_0x2be6810/d .functor NOT 1, L_0x2be68b0, C4<0>, C4<0>, C4<0>; -L_0x2be6810 .delay (10000,10000,10000) L_0x2be6810/d; -L_0x2be6950/d .functor AND 1, L_0x2be6a90, L_0x2be6810, C4<1>, C4<1>; -L_0x2be6950 .delay (20000,20000,20000) L_0x2be6950/d; -L_0x2be6b30/d .functor XOR 1, L_0x2be5fc0, L_0x2be65e0, C4<0>, C4<0>; -L_0x2be6b30 .delay (40000,40000,40000) L_0x2be6b30/d; -L_0x2be6c20/d .functor XOR 1, L_0x2be6b30, L_0x2be6190, C4<0>, C4<0>; -L_0x2be6c20 .delay (40000,40000,40000) L_0x2be6c20/d; -L_0x2be6d10/d .functor AND 1, L_0x2be5fc0, L_0x2be65e0, C4<1>, C4<1>; -L_0x2be6d10 .delay (20000,20000,20000) L_0x2be6d10/d; -L_0x2be6e80/d .functor AND 1, L_0x2be6b30, L_0x2be6190, C4<1>, C4<1>; -L_0x2be6e80 .delay (20000,20000,20000) L_0x2be6e80/d; -L_0x2be6f70/d .functor OR 1, L_0x2be6d10, L_0x2be6e80, C4<0>, C4<0>; -L_0x2be6f70 .delay (20000,20000,20000) L_0x2be6f70/d; -v0x2bac810_0 .net "A", 0 0, L_0x2be5fc0; 1 drivers -v0x2bac8d0_0 .net "AandB", 0 0, L_0x2be6d10; 1 drivers -v0x2bac970_0 .net "AddSubSLTSum", 0 0, L_0x2be6c20; 1 drivers -v0x2baca10_0 .net "AxorB", 0 0, L_0x2be6b30; 1 drivers -v0x2baca90_0 .net "B", 0 0, L_0x2be6060; 1 drivers -v0x2bacb40_0 .net "BornB", 0 0, L_0x2be65e0; 1 drivers -v0x2bacc00_0 .net "CINandAxorB", 0 0, L_0x2be6e80; 1 drivers -v0x2bacc80_0 .alias "Command", 2 0, v0x2bc67a0_0; -v0x2bacd00_0 .net *"_s3", 0 0, L_0x2be68b0; 1 drivers -v0x2bacd80_0 .net *"_s5", 0 0, L_0x2be6a90; 1 drivers -v0x2bace20_0 .net "carryin", 0 0, L_0x2be6190; 1 drivers -v0x2bacec0_0 .net "carryout", 0 0, L_0x2be6f70; 1 drivers -v0x2bacf60_0 .net "nB", 0 0, L_0x2be4e60; 1 drivers -v0x2bad010_0 .net "nCmd2", 0 0, L_0x2be6810; 1 drivers -v0x2bad110_0 .net "subtract", 0 0, L_0x2be6950; 1 drivers -L_0x2be6770 .part v0x2bc78e0_0, 0, 1; -L_0x2be68b0 .part v0x2bc78e0_0, 2, 1; -L_0x2be6a90 .part v0x2bc78e0_0, 0, 1; -S_0x2bac270 .scope module, "mux0" "TwoInMux" 3 105, 3 8, S_0x2bac180; - .timescale -9 -12; -L_0x2be63a0/d .functor NOT 1, L_0x2be6770, C4<0>, C4<0>, C4<0>; -L_0x2be63a0 .delay (10000,10000,10000) L_0x2be63a0/d; -L_0x2be6400/d .functor AND 1, L_0x2be6060, L_0x2be63a0, C4<1>, C4<1>; -L_0x2be6400 .delay (20000,20000,20000) L_0x2be6400/d; -L_0x2be64f0/d .functor AND 1, L_0x2be4e60, L_0x2be6770, C4<1>, C4<1>; -L_0x2be64f0 .delay (20000,20000,20000) L_0x2be64f0/d; -L_0x2be65e0/d .functor OR 1, L_0x2be6400, L_0x2be64f0, C4<0>, C4<0>; -L_0x2be65e0 .delay (20000,20000,20000) L_0x2be65e0/d; -v0x2bac360_0 .net "S", 0 0, L_0x2be6770; 1 drivers -v0x2bac400_0 .alias "in0", 0 0, v0x2baca90_0; -v0x2bac4a0_0 .alias "in1", 0 0, v0x2bacf60_0; -v0x2bac540_0 .net "nS", 0 0, L_0x2be63a0; 1 drivers -v0x2bac5f0_0 .net "out0", 0 0, L_0x2be6400; 1 drivers -v0x2bac690_0 .net "out1", 0 0, L_0x2be64f0; 1 drivers -v0x2bac770_0 .alias "outfinal", 0 0, v0x2bacb40_0; -S_0x2baaea0 .scope generate, "addbits[24]" "addbits[24]" 3 230, 3 230, S_0x2ba3100; - .timescale -9 -12; -P_0x2baa788 .param/l "i" 3 230, +C4<011000>; -S_0x2bab010 .scope module, "attempt" "MiddleAddSubSLT" 3 232, 3 89, S_0x2baaea0; - .timescale -9 -12; -L_0x2be6230/d .functor NOT 1, L_0x2be7420, C4<0>, C4<0>, C4<0>; -L_0x2be6230 .delay (10000,10000,10000) L_0x2be6230/d; -L_0x2be7c10/d .functor NOT 1, L_0x2be7cd0, C4<0>, C4<0>, C4<0>; -L_0x2be7c10 .delay (10000,10000,10000) L_0x2be7c10/d; -L_0x2be7d70/d .functor AND 1, L_0x2be7eb0, L_0x2be7c10, C4<1>, C4<1>; -L_0x2be7d70 .delay (20000,20000,20000) L_0x2be7d70/d; -L_0x2be7f50/d .functor XOR 1, L_0x2be7380, L_0x2be79c0, C4<0>, C4<0>; -L_0x2be7f50 .delay (40000,40000,40000) L_0x2be7f50/d; -L_0x2be8040/d .functor XOR 1, L_0x2be7f50, L_0x2be7550, C4<0>, C4<0>; -L_0x2be8040 .delay (40000,40000,40000) L_0x2be8040/d; -L_0x2be8160/d .functor AND 1, L_0x2be7380, L_0x2be79c0, C4<1>, C4<1>; -L_0x2be8160 .delay (20000,20000,20000) L_0x2be8160/d; -L_0x2be8300/d .functor AND 1, L_0x2be7f50, L_0x2be7550, C4<1>, C4<1>; -L_0x2be8300 .delay (20000,20000,20000) L_0x2be8300/d; -L_0x2be8410/d .functor OR 1, L_0x2be8160, L_0x2be8300, C4<0>, C4<0>; -L_0x2be8410 .delay (20000,20000,20000) L_0x2be8410/d; -v0x2bab670_0 .net "A", 0 0, L_0x2be7380; 1 drivers -v0x2bab730_0 .net "AandB", 0 0, L_0x2be8160; 1 drivers -v0x2bab7d0_0 .net "AddSubSLTSum", 0 0, L_0x2be8040; 1 drivers -v0x2bab870_0 .net "AxorB", 0 0, L_0x2be7f50; 1 drivers -v0x2bab8f0_0 .net "B", 0 0, L_0x2be7420; 1 drivers -v0x2bab9a0_0 .net "BornB", 0 0, L_0x2be79c0; 1 drivers -v0x2baba60_0 .net "CINandAxorB", 0 0, L_0x2be8300; 1 drivers -v0x2babae0_0 .alias "Command", 2 0, v0x2bc67a0_0; -v0x2babb60_0 .net *"_s3", 0 0, L_0x2be7cd0; 1 drivers -v0x2babbe0_0 .net *"_s5", 0 0, L_0x2be7eb0; 1 drivers -v0x2babc80_0 .net "carryin", 0 0, L_0x2be7550; 1 drivers -v0x2babd20_0 .net "carryout", 0 0, L_0x2be8410; 1 drivers -v0x2babdc0_0 .net "nB", 0 0, L_0x2be6230; 1 drivers -v0x2babe70_0 .net "nCmd2", 0 0, L_0x2be7c10; 1 drivers -v0x2babf70_0 .net "subtract", 0 0, L_0x2be7d70; 1 drivers -L_0x2be7b70 .part v0x2bc78e0_0, 0, 1; -L_0x2be7cd0 .part v0x2bc78e0_0, 2, 1; -L_0x2be7eb0 .part v0x2bc78e0_0, 0, 1; -S_0x2bab100 .scope module, "mux0" "TwoInMux" 3 105, 3 8, S_0x2bab010; - .timescale -9 -12; -L_0x2be7740/d .functor NOT 1, L_0x2be7b70, C4<0>, C4<0>, C4<0>; -L_0x2be7740 .delay (10000,10000,10000) L_0x2be7740/d; -L_0x2be77e0/d .functor AND 1, L_0x2be7420, L_0x2be7740, C4<1>, C4<1>; -L_0x2be77e0 .delay (20000,20000,20000) L_0x2be77e0/d; -L_0x2be78d0/d .functor AND 1, L_0x2be6230, L_0x2be7b70, C4<1>, C4<1>; -L_0x2be78d0 .delay (20000,20000,20000) L_0x2be78d0/d; -L_0x2be79c0/d .functor OR 1, L_0x2be77e0, L_0x2be78d0, C4<0>, C4<0>; -L_0x2be79c0 .delay (20000,20000,20000) L_0x2be79c0/d; -v0x2bab1f0_0 .net "S", 0 0, L_0x2be7b70; 1 drivers -v0x2bab290_0 .alias "in0", 0 0, v0x2bab8f0_0; -v0x2bab330_0 .alias "in1", 0 0, v0x2babdc0_0; -v0x2bab3d0_0 .net "nS", 0 0, L_0x2be7740; 1 drivers -v0x2bab450_0 .net "out0", 0 0, L_0x2be77e0; 1 drivers -v0x2bab4f0_0 .net "out1", 0 0, L_0x2be78d0; 1 drivers -v0x2bab5d0_0 .alias "outfinal", 0 0, v0x2bab9a0_0; -S_0x2ba9cd0 .scope generate, "addbits[25]" "addbits[25]" 3 230, 3 230, S_0x2ba3100; - .timescale -9 -12; -P_0x2ba96e8 .param/l "i" 3 230, +C4<011001>; -S_0x2ba9e40 .scope module, "attempt" "MiddleAddSubSLT" 3 232, 3 89, S_0x2ba9cd0; - .timescale -9 -12; -L_0x2be75f0/d .functor NOT 1, L_0x2bd3d90, C4<0>, C4<0>, C4<0>; -L_0x2be75f0 .delay (10000,10000,10000) L_0x2be75f0/d; -L_0x2be9100/d .functor NOT 1, L_0x2be91c0, C4<0>, C4<0>, C4<0>; -L_0x2be9100 .delay (10000,10000,10000) L_0x2be9100/d; -L_0x2be9260/d .functor AND 1, L_0x2be93a0, L_0x2be9100, C4<1>, C4<1>; -L_0x2be9260 .delay (20000,20000,20000) L_0x2be9260/d; -L_0x2be9440/d .functor XOR 1, L_0x2be8840, L_0x2be8eb0, C4<0>, C4<0>; -L_0x2be9440 .delay (40000,40000,40000) L_0x2be9440/d; -L_0x2be9530/d .functor XOR 1, L_0x2be9440, L_0x2bd3ec0, C4<0>, C4<0>; -L_0x2be9530 .delay (40000,40000,40000) L_0x2be9530/d; -L_0x2be9650/d .functor AND 1, L_0x2be8840, L_0x2be8eb0, C4<1>, C4<1>; -L_0x2be9650 .delay (20000,20000,20000) L_0x2be9650/d; -L_0x2be97f0/d .functor AND 1, L_0x2be9440, L_0x2bd3ec0, C4<1>, C4<1>; -L_0x2be97f0 .delay (20000,20000,20000) L_0x2be97f0/d; -L_0x2be9900/d .functor OR 1, L_0x2be9650, L_0x2be97f0, C4<0>, C4<0>; -L_0x2be9900 .delay (20000,20000,20000) L_0x2be9900/d; -v0x2baa3a0_0 .net "A", 0 0, L_0x2be8840; 1 drivers -v0x2baa460_0 .net "AandB", 0 0, L_0x2be9650; 1 drivers -v0x2baa500_0 .net "AddSubSLTSum", 0 0, L_0x2be9530; 1 drivers -v0x2baa5a0_0 .net "AxorB", 0 0, L_0x2be9440; 1 drivers -v0x2baa650_0 .net "B", 0 0, L_0x2bd3d90; 1 drivers -v0x2baa700_0 .net "BornB", 0 0, L_0x2be8eb0; 1 drivers -v0x2baa7c0_0 .net "CINandAxorB", 0 0, L_0x2be97f0; 1 drivers -v0x2baa860_0 .alias "Command", 2 0, v0x2bc67a0_0; -v0x2baa930_0 .net *"_s3", 0 0, L_0x2be91c0; 1 drivers -v0x2baa9d0_0 .net *"_s5", 0 0, L_0x2be93a0; 1 drivers -v0x2baaad0_0 .net "carryin", 0 0, L_0x2bd3ec0; 1 drivers -v0x2baab70_0 .net "carryout", 0 0, L_0x2be9900; 1 drivers -v0x2baac80_0 .net "nB", 0 0, L_0x2be75f0; 1 drivers -v0x2baad00_0 .net "nCmd2", 0 0, L_0x2be9100; 1 drivers -v0x2baae00_0 .net "subtract", 0 0, L_0x2be9260; 1 drivers -L_0x2be9060 .part v0x2bc78e0_0, 0, 1; -L_0x2be91c0 .part v0x2bc78e0_0, 2, 1; -L_0x2be93a0 .part v0x2bc78e0_0, 0, 1; -S_0x2ba9f30 .scope module, "mux0" "TwoInMux" 3 105, 3 8, S_0x2ba9e40; - .timescale -9 -12; -L_0x2be8c30/d .functor NOT 1, L_0x2be9060, C4<0>, C4<0>, C4<0>; -L_0x2be8c30 .delay (10000,10000,10000) L_0x2be8c30/d; -L_0x2be8cd0/d .functor AND 1, L_0x2bd3d90, L_0x2be8c30, C4<1>, C4<1>; -L_0x2be8cd0 .delay (20000,20000,20000) L_0x2be8cd0/d; -L_0x2be8dc0/d .functor AND 1, L_0x2be75f0, L_0x2be9060, C4<1>, C4<1>; -L_0x2be8dc0 .delay (20000,20000,20000) L_0x2be8dc0/d; -L_0x2be8eb0/d .functor OR 1, L_0x2be8cd0, L_0x2be8dc0, C4<0>, C4<0>; -L_0x2be8eb0 .delay (20000,20000,20000) L_0x2be8eb0/d; -v0x2baa020_0 .net "S", 0 0, L_0x2be9060; 1 drivers -v0x2baa0a0_0 .alias "in0", 0 0, v0x2baa650_0; -v0x2baa120_0 .alias "in1", 0 0, v0x2baac80_0; -v0x2baa1a0_0 .net "nS", 0 0, L_0x2be8c30; 1 drivers -v0x2baa220_0 .net "out0", 0 0, L_0x2be8cd0; 1 drivers -v0x2baa2a0_0 .net "out1", 0 0, L_0x2be8dc0; 1 drivers -v0x2baa320_0 .alias "outfinal", 0 0, v0x2baa700_0; -S_0x2ba8b30 .scope generate, "addbits[26]" "addbits[26]" 3 230, 3 230, S_0x2ba3100; - .timescale -9 -12; -P_0x2ba8548 .param/l "i" 3 230, +C4<011010>; -S_0x2ba8ca0 .scope module, "attempt" "MiddleAddSubSLT" 3 232, 3 89, S_0x2ba8b30; - .timescale -9 -12; -L_0x2bea050/d .functor NOT 1, L_0x2bea680, C4<0>, C4<0>, C4<0>; -L_0x2bea050 .delay (10000,10000,10000) L_0x2bea050/d; -L_0x2beaaa0/d .functor NOT 1, L_0x2beab40, C4<0>, C4<0>, C4<0>; -L_0x2beaaa0 .delay (10000,10000,10000) L_0x2beaaa0/d; -L_0x2beabe0/d .functor AND 1, L_0x2bead20, L_0x2beaaa0, C4<1>, C4<1>; -L_0x2beabe0 .delay (20000,20000,20000) L_0x2beabe0/d; -L_0x2beadc0/d .functor XOR 1, L_0x2bea5e0, L_0x2be8a80, C4<0>, C4<0>; -L_0x2beadc0 .delay (40000,40000,40000) L_0x2beadc0/d; -L_0x2beaeb0/d .functor XOR 1, L_0x2beadc0, L_0x2bea7b0, C4<0>, C4<0>; -L_0x2beaeb0 .delay (40000,40000,40000) L_0x2beaeb0/d; -L_0x2beafa0/d .functor AND 1, L_0x2bea5e0, L_0x2be8a80, C4<1>, C4<1>; -L_0x2beafa0 .delay (20000,20000,20000) L_0x2beafa0/d; -L_0x2beb110/d .functor AND 1, L_0x2beadc0, L_0x2bea7b0, C4<1>, C4<1>; -L_0x2beb110 .delay (20000,20000,20000) L_0x2beb110/d; -L_0x2beb200/d .functor OR 1, L_0x2beafa0, L_0x2beb110, C4<0>, C4<0>; -L_0x2beb200 .delay (20000,20000,20000) L_0x2beb200/d; -v0x2ba9330_0 .net "A", 0 0, L_0x2bea5e0; 1 drivers -v0x2ba93f0_0 .net "AandB", 0 0, L_0x2beafa0; 1 drivers -v0x2ba9490_0 .net "AddSubSLTSum", 0 0, L_0x2beaeb0; 1 drivers -v0x2ba9530_0 .net "AxorB", 0 0, L_0x2beadc0; 1 drivers -v0x2ba95b0_0 .net "B", 0 0, L_0x2bea680; 1 drivers -v0x2ba9660_0 .net "BornB", 0 0, L_0x2be8a80; 1 drivers -v0x2ba9720_0 .net "CINandAxorB", 0 0, L_0x2beb110; 1 drivers -v0x2ba97a0_0 .alias "Command", 2 0, v0x2bc67a0_0; -v0x2ba9820_0 .net *"_s3", 0 0, L_0x2beab40; 1 drivers -v0x2ba98a0_0 .net *"_s5", 0 0, L_0x2bead20; 1 drivers -v0x2ba9940_0 .net "carryin", 0 0, L_0x2bea7b0; 1 drivers -v0x2ba99e0_0 .net "carryout", 0 0, L_0x2beb200; 1 drivers -v0x2ba9a80_0 .net "nB", 0 0, L_0x2bea050; 1 drivers -v0x2ba9b30_0 .net "nCmd2", 0 0, L_0x2beaaa0; 1 drivers -v0x2ba9c30_0 .net "subtract", 0 0, L_0x2beabe0; 1 drivers -L_0x2beaa00 .part v0x2bc78e0_0, 0, 1; -L_0x2beab40 .part v0x2bc78e0_0, 2, 1; -L_0x2bead20 .part v0x2bc78e0_0, 0, 1; -S_0x2ba8d90 .scope module, "mux0" "TwoInMux" 3 105, 3 8, S_0x2ba8ca0; - .timescale -9 -12; -L_0x2bd4230/d .functor NOT 1, L_0x2beaa00, C4<0>, C4<0>, C4<0>; -L_0x2bd4230 .delay (10000,10000,10000) L_0x2bd4230/d; -L_0x2bd42b0/d .functor AND 1, L_0x2bea680, L_0x2bd4230, C4<1>, C4<1>; -L_0x2bd42b0 .delay (20000,20000,20000) L_0x2bd42b0/d; -L_0x2be8970/d .functor AND 1, L_0x2bea050, L_0x2beaa00, C4<1>, C4<1>; -L_0x2be8970 .delay (20000,20000,20000) L_0x2be8970/d; -L_0x2be8a80/d .functor OR 1, L_0x2bd42b0, L_0x2be8970, C4<0>, C4<0>; -L_0x2be8a80 .delay (20000,20000,20000) L_0x2be8a80/d; -v0x2ba8e80_0 .net "S", 0 0, L_0x2beaa00; 1 drivers -v0x2ba8f20_0 .alias "in0", 0 0, v0x2ba95b0_0; -v0x2ba8fc0_0 .alias "in1", 0 0, v0x2ba9a80_0; -v0x2ba9060_0 .net "nS", 0 0, L_0x2bd4230; 1 drivers -v0x2ba9110_0 .net "out0", 0 0, L_0x2bd42b0; 1 drivers -v0x2ba91b0_0 .net "out1", 0 0, L_0x2be8970; 1 drivers -v0x2ba9290_0 .alias "outfinal", 0 0, v0x2ba9660_0; -S_0x2ba7990 .scope generate, "addbits[27]" "addbits[27]" 3 230, 3 230, S_0x2ba3100; - .timescale -9 -12; -P_0x2ba73a8 .param/l "i" 3 230, +C4<011011>; -S_0x2ba7b00 .scope module, "attempt" "MiddleAddSubSLT" 3 232, 3 89, S_0x2ba7990; - .timescale -9 -12; -L_0x2bea850/d .functor NOT 1, L_0x2beb6b0, C4<0>, C4<0>, C4<0>; -L_0x2bea850 .delay (10000,10000,10000) L_0x2bea850/d; -L_0x2bebec0/d .functor NOT 1, L_0x2bebf80, C4<0>, C4<0>, C4<0>; -L_0x2bebec0 .delay (10000,10000,10000) L_0x2bebec0/d; -L_0x2bec020/d .functor AND 1, L_0x2bec160, L_0x2bebec0, C4<1>, C4<1>; -L_0x2bec020 .delay (20000,20000,20000) L_0x2bec020/d; -L_0x2bec200/d .functor XOR 1, L_0x2beb610, L_0x2bebc50, C4<0>, C4<0>; -L_0x2bec200 .delay (40000,40000,40000) L_0x2bec200/d; -L_0x2bec2f0/d .functor XOR 1, L_0x2bec200, L_0x2beb7e0, C4<0>, C4<0>; -L_0x2bec2f0 .delay (40000,40000,40000) L_0x2bec2f0/d; -L_0x2bec410/d .functor AND 1, L_0x2beb610, L_0x2bebc50, C4<1>, C4<1>; -L_0x2bec410 .delay (20000,20000,20000) L_0x2bec410/d; -L_0x2bec5b0/d .functor AND 1, L_0x2bec200, L_0x2beb7e0, C4<1>, C4<1>; -L_0x2bec5b0 .delay (20000,20000,20000) L_0x2bec5b0/d; -L_0x2bec6c0/d .functor OR 1, L_0x2bec410, L_0x2bec5b0, C4<0>, C4<0>; -L_0x2bec6c0 .delay (20000,20000,20000) L_0x2bec6c0/d; -v0x2ba8190_0 .net "A", 0 0, L_0x2beb610; 1 drivers -v0x2ba8250_0 .net "AandB", 0 0, L_0x2bec410; 1 drivers -v0x2ba82f0_0 .net "AddSubSLTSum", 0 0, L_0x2bec2f0; 1 drivers -v0x2ba8390_0 .net "AxorB", 0 0, L_0x2bec200; 1 drivers -v0x2ba8410_0 .net "B", 0 0, L_0x2beb6b0; 1 drivers -v0x2ba84c0_0 .net "BornB", 0 0, L_0x2bebc50; 1 drivers -v0x2ba8580_0 .net "CINandAxorB", 0 0, L_0x2bec5b0; 1 drivers -v0x2ba8600_0 .alias "Command", 2 0, v0x2bc67a0_0; -v0x2ba8680_0 .net *"_s3", 0 0, L_0x2bebf80; 1 drivers -v0x2ba8700_0 .net *"_s5", 0 0, L_0x2bec160; 1 drivers -v0x2ba87a0_0 .net "carryin", 0 0, L_0x2beb7e0; 1 drivers -v0x2ba8840_0 .net "carryout", 0 0, L_0x2bec6c0; 1 drivers -v0x2ba88e0_0 .net "nB", 0 0, L_0x2bea850; 1 drivers -v0x2ba8990_0 .net "nCmd2", 0 0, L_0x2bebec0; 1 drivers -v0x2ba8a90_0 .net "subtract", 0 0, L_0x2bec020; 1 drivers -L_0x2bebe20 .part v0x2bc78e0_0, 0, 1; -L_0x2bebf80 .part v0x2bc78e0_0, 2, 1; -L_0x2bec160 .part v0x2bc78e0_0, 0, 1; -S_0x2ba7bf0 .scope module, "mux0" "TwoInMux" 3 105, 3 8, S_0x2ba7b00; - .timescale -9 -12; -L_0x2beba10/d .functor NOT 1, L_0x2bebe20, C4<0>, C4<0>, C4<0>; -L_0x2beba10 .delay (10000,10000,10000) L_0x2beba10/d; -L_0x2beba70/d .functor AND 1, L_0x2beb6b0, L_0x2beba10, C4<1>, C4<1>; -L_0x2beba70 .delay (20000,20000,20000) L_0x2beba70/d; -L_0x2bebb60/d .functor AND 1, L_0x2bea850, L_0x2bebe20, C4<1>, C4<1>; -L_0x2bebb60 .delay (20000,20000,20000) L_0x2bebb60/d; -L_0x2bebc50/d .functor OR 1, L_0x2beba70, L_0x2bebb60, C4<0>, C4<0>; -L_0x2bebc50 .delay (20000,20000,20000) L_0x2bebc50/d; -v0x2ba7ce0_0 .net "S", 0 0, L_0x2bebe20; 1 drivers -v0x2ba7d80_0 .alias "in0", 0 0, v0x2ba8410_0; -v0x2ba7e20_0 .alias "in1", 0 0, v0x2ba88e0_0; -v0x2ba7ec0_0 .net "nS", 0 0, L_0x2beba10; 1 drivers -v0x2ba7f70_0 .net "out0", 0 0, L_0x2beba70; 1 drivers -v0x2ba8010_0 .net "out1", 0 0, L_0x2bebb60; 1 drivers -v0x2ba80f0_0 .alias "outfinal", 0 0, v0x2ba84c0_0; -S_0x2ba67f0 .scope generate, "addbits[28]" "addbits[28]" 3 230, 3 230, S_0x2ba3100; - .timescale -9 -12; -P_0x2ba6208 .param/l "i" 3 230, +C4<011100>; -S_0x2ba6960 .scope module, "attempt" "MiddleAddSubSLT" 3 232, 3 89, S_0x2ba67f0; - .timescale -9 -12; -L_0x2beb880/d .functor NOT 1, L_0x2becb90, C4<0>, C4<0>, C4<0>; -L_0x2beb880 .delay (10000,10000,10000) L_0x2beb880/d; -L_0x2bed3d0/d .functor NOT 1, L_0x2bed470, C4<0>, C4<0>, C4<0>; -L_0x2bed3d0 .delay (10000,10000,10000) L_0x2bed3d0/d; -L_0x2bed510/d .functor AND 1, L_0x2bed650, L_0x2bed3d0, C4<1>, C4<1>; -L_0x2bed510 .delay (20000,20000,20000) L_0x2bed510/d; -L_0x2bed6f0/d .functor XOR 1, L_0x2becaf0, L_0x2bed1a0, C4<0>, C4<0>; -L_0x2bed6f0 .delay (40000,40000,40000) L_0x2bed6f0/d; -L_0x2bed810/d .functor XOR 1, L_0x2bed6f0, L_0x2beccc0, C4<0>, C4<0>; -L_0x2bed810 .delay (40000,40000,40000) L_0x2bed810/d; -L_0x2bed930/d .functor AND 1, L_0x2becaf0, L_0x2bed1a0, C4<1>, C4<1>; -L_0x2bed930 .delay (20000,20000,20000) L_0x2bed930/d; -L_0x2bedad0/d .functor AND 1, L_0x2bed6f0, L_0x2beccc0, C4<1>, C4<1>; -L_0x2bedad0 .delay (20000,20000,20000) L_0x2bedad0/d; -L_0x2bedbc0/d .functor OR 1, L_0x2bed930, L_0x2bedad0, C4<0>, C4<0>; -L_0x2bedbc0 .delay (20000,20000,20000) L_0x2bedbc0/d; -v0x2ba6ff0_0 .net "A", 0 0, L_0x2becaf0; 1 drivers -v0x2ba70b0_0 .net "AandB", 0 0, L_0x2bed930; 1 drivers -v0x2ba7150_0 .net "AddSubSLTSum", 0 0, L_0x2bed810; 1 drivers -v0x2ba71f0_0 .net "AxorB", 0 0, L_0x2bed6f0; 1 drivers -v0x2ba7270_0 .net "B", 0 0, L_0x2becb90; 1 drivers -v0x2ba7320_0 .net "BornB", 0 0, L_0x2bed1a0; 1 drivers -v0x2ba73e0_0 .net "CINandAxorB", 0 0, L_0x2bedad0; 1 drivers -v0x2ba7460_0 .alias "Command", 2 0, v0x2bc67a0_0; -v0x2ba74e0_0 .net *"_s3", 0 0, L_0x2bed470; 1 drivers -v0x2ba7560_0 .net *"_s5", 0 0, L_0x2bed650; 1 drivers -v0x2ba7600_0 .net "carryin", 0 0, L_0x2beccc0; 1 drivers -v0x2ba76a0_0 .net "carryout", 0 0, L_0x2bedbc0; 1 drivers -v0x2ba7740_0 .net "nB", 0 0, L_0x2beb880; 1 drivers -v0x2ba77f0_0 .net "nCmd2", 0 0, L_0x2bed3d0; 1 drivers -v0x2ba78f0_0 .net "subtract", 0 0, L_0x2bed510; 1 drivers -L_0x2bed330 .part v0x2bc78e0_0, 0, 1; -L_0x2bed470 .part v0x2bc78e0_0, 2, 1; -L_0x2bed650 .part v0x2bc78e0_0, 0, 1; -S_0x2ba6a50 .scope module, "mux0" "TwoInMux" 3 105, 3 8, S_0x2ba6960; - .timescale -9 -12; -L_0x2becf20/d .functor NOT 1, L_0x2bed330, C4<0>, C4<0>, C4<0>; -L_0x2becf20 .delay (10000,10000,10000) L_0x2becf20/d; -L_0x2becfc0/d .functor AND 1, L_0x2becb90, L_0x2becf20, C4<1>, C4<1>; -L_0x2becfc0 .delay (20000,20000,20000) L_0x2becfc0/d; -L_0x2bed0b0/d .functor AND 1, L_0x2beb880, L_0x2bed330, C4<1>, C4<1>; -L_0x2bed0b0 .delay (20000,20000,20000) L_0x2bed0b0/d; -L_0x2bed1a0/d .functor OR 1, L_0x2becfc0, L_0x2bed0b0, C4<0>, C4<0>; -L_0x2bed1a0 .delay (20000,20000,20000) L_0x2bed1a0/d; -v0x2ba6b40_0 .net "S", 0 0, L_0x2bed330; 1 drivers -v0x2ba6be0_0 .alias "in0", 0 0, v0x2ba7270_0; -v0x2ba6c80_0 .alias "in1", 0 0, v0x2ba7740_0; -v0x2ba6d20_0 .net "nS", 0 0, L_0x2becf20; 1 drivers -v0x2ba6dd0_0 .net "out0", 0 0, L_0x2becfc0; 1 drivers -v0x2ba6e70_0 .net "out1", 0 0, L_0x2bed0b0; 1 drivers -v0x2ba6f50_0 .alias "outfinal", 0 0, v0x2ba7320_0; -S_0x2ba5650 .scope generate, "addbits[29]" "addbits[29]" 3 230, 3 230, S_0x2ba3100; - .timescale -9 -12; -P_0x2ba5068 .param/l "i" 3 230, +C4<011101>; -S_0x2ba57c0 .scope module, "attempt" "MiddleAddSubSLT" 3 232, 3 89, S_0x2ba5650; - .timescale -9 -12; -L_0x2becd60/d .functor NOT 1, L_0x2bd95a0, C4<0>, C4<0>, C4<0>; -L_0x2becd60 .delay (10000,10000,10000) L_0x2becd60/d; -L_0x2bee8a0/d .functor NOT 1, L_0x2bee960, C4<0>, C4<0>, C4<0>; -L_0x2bee8a0 .delay (10000,10000,10000) L_0x2bee8a0/d; -L_0x2beea00/d .functor AND 1, L_0x2beeb40, L_0x2bee8a0, C4<1>, C4<1>; -L_0x2beea00 .delay (20000,20000,20000) L_0x2beea00/d; -L_0x2beebe0/d .functor XOR 1, L_0x2bee360, L_0x2bee670, C4<0>, C4<0>; -L_0x2beebe0 .delay (40000,40000,40000) L_0x2beebe0/d; -L_0x2beed00/d .functor XOR 1, L_0x2beebe0, L_0x2bd96d0, C4<0>, C4<0>; -L_0x2beed00 .delay (40000,40000,40000) L_0x2beed00/d; -L_0x2beee20/d .functor AND 1, L_0x2bee360, L_0x2bee670, C4<1>, C4<1>; -L_0x2beee20 .delay (20000,20000,20000) L_0x2beee20/d; -L_0x2beefc0/d .functor AND 1, L_0x2beebe0, L_0x2bd96d0, C4<1>, C4<1>; -L_0x2beefc0 .delay (20000,20000,20000) L_0x2beefc0/d; -L_0x2bef0b0/d .functor OR 1, L_0x2beee20, L_0x2beefc0, C4<0>, C4<0>; -L_0x2bef0b0 .delay (20000,20000,20000) L_0x2bef0b0/d; -v0x2ba5e50_0 .net "A", 0 0, L_0x2bee360; 1 drivers -v0x2ba5f10_0 .net "AandB", 0 0, L_0x2beee20; 1 drivers -v0x2ba5fb0_0 .net "AddSubSLTSum", 0 0, L_0x2beed00; 1 drivers -v0x2ba6050_0 .net "AxorB", 0 0, L_0x2beebe0; 1 drivers -v0x2ba60d0_0 .net "B", 0 0, L_0x2bd95a0; 1 drivers -v0x2ba6180_0 .net "BornB", 0 0, L_0x2bee670; 1 drivers -v0x2ba6240_0 .net "CINandAxorB", 0 0, L_0x2beefc0; 1 drivers -v0x2ba62c0_0 .alias "Command", 2 0, v0x2bc67a0_0; -v0x2ba6340_0 .net *"_s3", 0 0, L_0x2bee960; 1 drivers -v0x2ba63c0_0 .net *"_s5", 0 0, L_0x2beeb40; 1 drivers -v0x2ba6460_0 .net "carryin", 0 0, L_0x2bd96d0; 1 drivers -v0x2ba6500_0 .net "carryout", 0 0, L_0x2bef0b0; 1 drivers -v0x2ba65a0_0 .net "nB", 0 0, L_0x2becd60; 1 drivers -v0x2ba6650_0 .net "nCmd2", 0 0, L_0x2bee8a0; 1 drivers -v0x2ba6750_0 .net "subtract", 0 0, L_0x2beea00; 1 drivers -L_0x2bee800 .part v0x2bc78e0_0, 0, 1; -L_0x2bee960 .part v0x2bc78e0_0, 2, 1; -L_0x2beeb40 .part v0x2bc78e0_0, 0, 1; -S_0x2ba58b0 .scope module, "mux0" "TwoInMux" 3 105, 3 8, S_0x2ba57c0; - .timescale -9 -12; -L_0x2becec0/d .functor NOT 1, L_0x2bee800, C4<0>, C4<0>, C4<0>; -L_0x2becec0 .delay (10000,10000,10000) L_0x2becec0/d; -L_0x2bee490/d .functor AND 1, L_0x2bd95a0, L_0x2becec0, C4<1>, C4<1>; -L_0x2bee490 .delay (20000,20000,20000) L_0x2bee490/d; -L_0x2bee580/d .functor AND 1, L_0x2becd60, L_0x2bee800, C4<1>, C4<1>; -L_0x2bee580 .delay (20000,20000,20000) L_0x2bee580/d; -L_0x2bee670/d .functor OR 1, L_0x2bee490, L_0x2bee580, C4<0>, C4<0>; -L_0x2bee670 .delay (20000,20000,20000) L_0x2bee670/d; -v0x2ba59a0_0 .net "S", 0 0, L_0x2bee800; 1 drivers -v0x2ba5a40_0 .alias "in0", 0 0, v0x2ba60d0_0; -v0x2ba5ae0_0 .alias "in1", 0 0, v0x2ba65a0_0; -v0x2ba5b80_0 .net "nS", 0 0, L_0x2becec0; 1 drivers -v0x2ba5c30_0 .net "out0", 0 0, L_0x2bee490; 1 drivers -v0x2ba5cd0_0 .net "out1", 0 0, L_0x2bee580; 1 drivers -v0x2ba5db0_0 .alias "outfinal", 0 0, v0x2ba6180_0; -S_0x2ba44b0 .scope generate, "addbits[30]" "addbits[30]" 3 230, 3 230, S_0x2ba3100; - .timescale -9 -12; -P_0x2ba3df8 .param/l "i" 3 230, +C4<011110>; -S_0x2ba4620 .scope module, "attempt" "MiddleAddSubSLT" 3 232, 3 89, S_0x2ba44b0; - .timescale -9 -12; -L_0x2befc40/d .functor NOT 1, L_0x2bef850, C4<0>, C4<0>, C4<0>; -L_0x2befc40 .delay (10000,10000,10000) L_0x2befc40/d; -L_0x2bf01a0/d .functor NOT 1, L_0x2bf0260, C4<0>, C4<0>, C4<0>; -L_0x2bf01a0 .delay (10000,10000,10000) L_0x2bf01a0/d; -L_0x2bf0300/d .functor AND 1, L_0x2bf0440, L_0x2bf01a0, C4<1>, C4<1>; -L_0x2bf0300 .delay (20000,20000,20000) L_0x2bf0300/d; -L_0x2bf04e0/d .functor XOR 1, L_0x2bef7b0, L_0x2beff30, C4<0>, C4<0>; -L_0x2bf04e0 .delay (40000,40000,40000) L_0x2bf04e0/d; -L_0x2bf05d0/d .functor XOR 1, L_0x2bf04e0, L_0x2bef980, C4<0>, C4<0>; -L_0x2bf05d0 .delay (40000,40000,40000) L_0x2bf05d0/d; -L_0x2bf06f0/d .functor AND 1, L_0x2bef7b0, L_0x2beff30, C4<1>, C4<1>; -L_0x2bf06f0 .delay (20000,20000,20000) L_0x2bf06f0/d; -L_0x2bf0890/d .functor AND 1, L_0x2bf04e0, L_0x2bef980, C4<1>, C4<1>; -L_0x2bf0890 .delay (20000,20000,20000) L_0x2bf0890/d; -L_0x2bf09a0/d .functor OR 1, L_0x2bf06f0, L_0x2bf0890, C4<0>, C4<0>; -L_0x2bf09a0 .delay (20000,20000,20000) L_0x2bf09a0/d; -v0x2ba4cb0_0 .net "A", 0 0, L_0x2bef7b0; 1 drivers -v0x2ba4d70_0 .net "AandB", 0 0, L_0x2bf06f0; 1 drivers -v0x2ba4e10_0 .net "AddSubSLTSum", 0 0, L_0x2bf05d0; 1 drivers -v0x2ba4eb0_0 .net "AxorB", 0 0, L_0x2bf04e0; 1 drivers -v0x2ba4f30_0 .net "B", 0 0, L_0x2bef850; 1 drivers -v0x2ba4fe0_0 .net "BornB", 0 0, L_0x2beff30; 1 drivers -v0x2ba50a0_0 .net "CINandAxorB", 0 0, L_0x2bf0890; 1 drivers -v0x2ba5120_0 .alias "Command", 2 0, v0x2bc67a0_0; -v0x2ba51a0_0 .net *"_s3", 0 0, L_0x2bf0260; 1 drivers -v0x2ba5220_0 .net *"_s5", 0 0, L_0x2bf0440; 1 drivers -v0x2ba52c0_0 .net "carryin", 0 0, L_0x2bef980; 1 drivers -v0x2ba5360_0 .net "carryout", 0 0, L_0x2bf09a0; 1 drivers -v0x2ba5400_0 .net "nB", 0 0, L_0x2befc40; 1 drivers -v0x2ba54b0_0 .net "nCmd2", 0 0, L_0x2bf01a0; 1 drivers -v0x2ba55b0_0 .net "subtract", 0 0, L_0x2bf0300; 1 drivers -L_0x2bf0100 .part v0x2bc78e0_0, 0, 1; -L_0x2bf0260 .part v0x2bc78e0_0, 2, 1; -L_0x2bf0440 .part v0x2bc78e0_0, 0, 1; -S_0x2ba4710 .scope module, "mux0" "TwoInMux" 3 105, 3 8, S_0x2ba4620; - .timescale -9 -12; -L_0x2befcf0/d .functor NOT 1, L_0x2bf0100, C4<0>, C4<0>, C4<0>; -L_0x2befcf0 .delay (10000,10000,10000) L_0x2befcf0/d; -L_0x2befd50/d .functor AND 1, L_0x2bef850, L_0x2befcf0, C4<1>, C4<1>; -L_0x2befd50 .delay (20000,20000,20000) L_0x2befd50/d; -L_0x2befe40/d .functor AND 1, L_0x2befc40, L_0x2bf0100, C4<1>, C4<1>; -L_0x2befe40 .delay (20000,20000,20000) L_0x2befe40/d; -L_0x2beff30/d .functor OR 1, L_0x2befd50, L_0x2befe40, C4<0>, C4<0>; -L_0x2beff30 .delay (20000,20000,20000) L_0x2beff30/d; -v0x2ba4800_0 .net "S", 0 0, L_0x2bf0100; 1 drivers -v0x2ba48a0_0 .alias "in0", 0 0, v0x2ba4f30_0; -v0x2ba4940_0 .alias "in1", 0 0, v0x2ba5400_0; -v0x2ba49e0_0 .net "nS", 0 0, L_0x2befcf0; 1 drivers -v0x2ba4a90_0 .net "out0", 0 0, L_0x2befd50; 1 drivers -v0x2ba4b30_0 .net "out1", 0 0, L_0x2befe40; 1 drivers -v0x2ba4c10_0 .alias "outfinal", 0 0, v0x2ba4fe0_0; -S_0x2ba3270 .scope generate, "addbits[31]" "addbits[31]" 3 230, 3 230, S_0x2ba3100; - .timescale -9 -12; -P_0x2ba3368 .param/l "i" 3 230, +C4<011111>; -S_0x2ba33e0 .scope module, "attempt" "MiddleAddSubSLT" 3 232, 3 89, S_0x2ba3270; - .timescale -9 -12; -L_0x2befa20/d .functor NOT 1, L_0x2bf0e70, C4<0>, C4<0>, C4<0>; -L_0x2befa20 .delay (10000,10000,10000) L_0x2befa20/d; -L_0x2bf16a0/d .functor NOT 1, L_0x2bf1740, C4<0>, C4<0>, C4<0>; -L_0x2bf16a0 .delay (10000,10000,10000) L_0x2bf16a0/d; -L_0x2bf17e0/d .functor AND 1, L_0x2bf1920, L_0x2bf16a0, C4<1>, C4<1>; -L_0x2bf17e0 .delay (20000,20000,20000) L_0x2bf17e0/d; -L_0x2bf19c0/d .functor XOR 1, L_0x2bf0dd0, L_0x2bf1470, C4<0>, C4<0>; -L_0x2bf19c0 .delay (40000,40000,40000) L_0x2bf19c0/d; -L_0x2bf1ae0/d .functor XOR 1, L_0x2bf19c0, L_0x2bf0fa0, C4<0>, C4<0>; -L_0x2bf1ae0 .delay (40000,40000,40000) L_0x2bf1ae0/d; -L_0x2bf1c00/d .functor AND 1, L_0x2bf0dd0, L_0x2bf1470, C4<1>, C4<1>; -L_0x2bf1c00 .delay (20000,20000,20000) L_0x2bf1c00/d; -L_0x2bf1da0/d .functor AND 1, L_0x2bf19c0, L_0x2bf0fa0, C4<1>, C4<1>; -L_0x2bf1da0 .delay (20000,20000,20000) L_0x2bf1da0/d; -L_0x2bf1e90/d .functor OR 1, L_0x2bf1c00, L_0x2bf1da0, C4<0>, C4<0>; -L_0x2bf1e90 .delay (20000,20000,20000) L_0x2bf1e90/d; -v0x2ba3a40_0 .net "A", 0 0, L_0x2bf0dd0; 1 drivers -v0x2ba3b00_0 .net "AandB", 0 0, L_0x2bf1c00; 1 drivers -v0x2ba3ba0_0 .net "AddSubSLTSum", 0 0, L_0x2bf1ae0; 1 drivers -v0x2ba3c40_0 .net "AxorB", 0 0, L_0x2bf19c0; 1 drivers -v0x2ba3cc0_0 .net "B", 0 0, L_0x2bf0e70; 1 drivers -v0x2ba3d70_0 .net "BornB", 0 0, L_0x2bf1470; 1 drivers -v0x2ba3e30_0 .net "CINandAxorB", 0 0, L_0x2bf1da0; 1 drivers -v0x2ba3eb0_0 .alias "Command", 2 0, v0x2bc67a0_0; -v0x2ba3f30_0 .net *"_s3", 0 0, L_0x2bf1740; 1 drivers -v0x2ba3fb0_0 .net *"_s5", 0 0, L_0x2bf1920; 1 drivers -v0x2ba40b0_0 .net "carryin", 0 0, L_0x2bf0fa0; 1 drivers -v0x2ba4150_0 .net "carryout", 0 0, L_0x2bf1e90; 1 drivers -v0x2ba4260_0 .net "nB", 0 0, L_0x2befa20; 1 drivers -v0x2ba4310_0 .net "nCmd2", 0 0, L_0x2bf16a0; 1 drivers -v0x2ba4410_0 .net "subtract", 0 0, L_0x2bf17e0; 1 drivers -L_0x2bf1600 .part v0x2bc78e0_0, 0, 1; -L_0x2bf1740 .part v0x2bc78e0_0, 2, 1; -L_0x2bf1920 .part v0x2bc78e0_0, 0, 1; -S_0x2ba34d0 .scope module, "mux0" "TwoInMux" 3 105, 3 8, S_0x2ba33e0; - .timescale -9 -12; -L_0x2befb80/d .functor NOT 1, L_0x2bf1600, C4<0>, C4<0>, C4<0>; -L_0x2befb80 .delay (10000,10000,10000) L_0x2befb80/d; -L_0x2bf1290/d .functor AND 1, L_0x2bf0e70, L_0x2befb80, C4<1>, C4<1>; -L_0x2bf1290 .delay (20000,20000,20000) L_0x2bf1290/d; -L_0x2bf1380/d .functor AND 1, L_0x2befa20, L_0x2bf1600, C4<1>, C4<1>; -L_0x2bf1380 .delay (20000,20000,20000) L_0x2bf1380/d; -L_0x2bf1470/d .functor OR 1, L_0x2bf1290, L_0x2bf1380, C4<0>, C4<0>; -L_0x2bf1470 .delay (20000,20000,20000) L_0x2bf1470/d; -v0x2ba35c0_0 .net "S", 0 0, L_0x2bf1600; 1 drivers -v0x2ba3660_0 .alias "in0", 0 0, v0x2ba3cc0_0; -v0x2ba3700_0 .alias "in1", 0 0, v0x2ba4260_0; -v0x2ba37a0_0 .net "nS", 0 0, L_0x2befb80; 1 drivers -v0x2ba3820_0 .net "out0", 0 0, L_0x2bf1290; 1 drivers -v0x2ba38c0_0 .net "out1", 0 0, L_0x2bf1380; 1 drivers -v0x2ba39a0_0 .alias "outfinal", 0 0, v0x2ba3d70_0; -S_0x2b8b740 .scope module, "trial1" "AndNand32" 2 143, 3 154, S_0x270e6d0; - .timescale -9 -12; -P_0x2b8b138 .param/l "size" 3 161, +C4<0100000>; -v0x2ba2f00_0 .alias "A", 31 0, v0x2bc6580_0; -v0x2ba2f80_0 .alias "AndNandOut", 31 0, v0x2bc77e0_0; -v0x2ba3000_0 .alias "B", 31 0, v0x2bc66a0_0; -v0x2ba3080_0 .alias "Command", 2 0, v0x2bc67a0_0; -L_0x2bf56a0 .part/pv L_0x2bf5430, 1, 1, 32; -L_0x2bf57f0 .part v0x2bc7660_0, 1, 1; -L_0x2bf5890 .part v0x2bc7860_0, 1, 1; -L_0x2bf6150 .part/pv L_0x2bf5ee0, 2, 1, 32; -L_0x2bf61f0 .part v0x2bc7660_0, 2, 1; -L_0x2bf6290 .part v0x2bc7860_0, 2, 1; -L_0x2bf6bc0 .part/pv L_0x2bf6950, 3, 1, 32; -L_0x2bf6c60 .part v0x2bc7660_0, 3, 1; -L_0x2bf6d50 .part v0x2bc7860_0, 3, 1; -L_0x2bf7620 .part/pv L_0x2bf73b0, 4, 1, 32; -L_0x2bf7720 .part v0x2bc7660_0, 4, 1; -L_0x2bf77c0 .part v0x2bc7860_0, 4, 1; -L_0x2bf8090 .part/pv L_0x2bf7e20, 5, 1, 32; -L_0x2bf8240 .part v0x2bc7660_0, 5, 1; -L_0x2bf82e0 .part v0x2bc7860_0, 5, 1; -L_0x2bf8bf0 .part/pv L_0x2bf8980, 6, 1, 32; -L_0x2bf8c90 .part v0x2bc7660_0, 6, 1; -L_0x2bf8d30 .part v0x2bc7860_0, 6, 1; -L_0x2bf9660 .part/pv L_0x2bf93f0, 7, 1, 32; -L_0x2bf9700 .part v0x2bc7660_0, 7, 1; -L_0x2bf8e20 .part v0x2bc7860_0, 7, 1; -L_0x2bfa0c0 .part/pv L_0x2bf9e50, 8, 1, 32; -L_0x2bf97a0 .part v0x2bc7660_0, 8, 1; -L_0x2bfa220 .part v0x2bc7860_0, 8, 1; -L_0x2bfab40 .part/pv L_0x2bfa8d0, 9, 1, 32; -L_0x2bfabe0 .part v0x2bc7660_0, 9, 1; -L_0x2bfa310 .part v0x2bc7860_0, 9, 1; -L_0x2bfb5b0 .part/pv L_0x2bfb340, 10, 1, 32; -L_0x2bfac80 .part v0x2bc7660_0, 10, 1; -L_0x2bfb740 .part v0x2bc7860_0, 10, 1; -L_0x2bfc020 .part/pv L_0x2bfbdb0, 11, 1, 32; -L_0x2bfc0c0 .part v0x2bc7660_0, 11, 1; -L_0x2bfb830 .part v0x2bc7860_0, 11, 1; -L_0x2bfca90 .part/pv L_0x2bfc820, 12, 1, 32; -L_0x2bfc160 .part v0x2bc7660_0, 12, 1; -L_0x2bfcc50 .part v0x2bc7860_0, 12, 1; -L_0x2bfd510 .part/pv L_0x2bfd2a0, 13, 1, 32; -L_0x2bf8130 .part v0x2bc7660_0, 13, 1; -L_0x2bfccf0 .part v0x2bc7860_0, 13, 1; -L_0x2bfe080 .part/pv L_0x2bfde10, 14, 1, 32; -L_0x2bfd7c0 .part v0x2bc7660_0, 14, 1; -L_0x2bfd860 .part v0x2bc7860_0, 14, 1; -L_0x2bfeaf0 .part/pv L_0x2bfe880, 15, 1, 32; -L_0x2bfeb90 .part v0x2bc7660_0, 15, 1; -L_0x2bfe2c0 .part v0x2bc7860_0, 15, 1; -L_0x2bff560 .part/pv L_0x2bff2f0, 16, 1, 32; -L_0x2bfec30 .part v0x2bc7660_0, 16, 1; -L_0x2bfecd0 .part v0x2bc7860_0, 16, 1; -L_0x2bfffe0 .part/pv L_0x2bffd70, 17, 1, 32; -L_0x2c00080 .part v0x2bc7660_0, 17, 1; -L_0x2bff7d0 .part v0x2bc7860_0, 17, 1; -L_0x2c00a40 .part/pv L_0x2c007d0, 18, 1, 32; -L_0x2c00120 .part v0x2bc7660_0, 18, 1; -L_0x2c001c0 .part v0x2bc7860_0, 18, 1; -L_0x2c014c0 .part/pv L_0x2c01250, 19, 1, 32; -L_0x2c01560 .part v0x2bc7660_0, 19, 1; -L_0x2c00ae0 .part v0x2bc7860_0, 19, 1; -L_0x2c01f20 .part/pv L_0x2c01cb0, 20, 1, 32; -L_0x2c01600 .part v0x2bc7660_0, 20, 1; -L_0x2c016a0 .part v0x2bc7860_0, 20, 1; -L_0x2c02990 .part/pv L_0x2c02720, 21, 1, 32; -L_0x2c02a30 .part v0x2bc7660_0, 21, 1; -L_0x2c01fc0 .part v0x2bc7860_0, 21, 1; -L_0x2c03400 .part/pv L_0x2c03190, 22, 1, 32; -L_0x2c02ad0 .part v0x2bc7660_0, 22, 1; -L_0x2c02b70 .part v0x2bc7860_0, 22, 1; -L_0x2c03e80 .part/pv L_0x2c03c10, 23, 1, 32; -L_0x2c03f20 .part v0x2bc7660_0, 23, 1; -L_0x2c034a0 .part v0x2bc7860_0, 23, 1; -L_0x2c048e0 .part/pv L_0x2c04670, 24, 1, 32; -L_0x2c03fc0 .part v0x2bc7660_0, 24, 1; -L_0x2c04060 .part v0x2bc7860_0, 24, 1; -L_0x2c05350 .part/pv L_0x2c050e0, 25, 1, 32; -L_0x2c053f0 .part v0x2bc7660_0, 25, 1; -L_0x2bea340 .part v0x2bc7860_0, 25, 1; -L_0x2c06550 .part/pv L_0x2be9ea0, 26, 1, 32; -L_0x2bea0e0 .part v0x2bc7660_0, 26, 1; -L_0x2bea180 .part v0x2bc7860_0, 26, 1; -L_0x2c06ee0 .part/pv L_0x2c06cb0, 27, 1, 32; -L_0x2c06f80 .part v0x2bc7660_0, 27, 1; -L_0x2c065f0 .part v0x2bc7860_0, 27, 1; -L_0x2c07890 .part/pv L_0x2c07660, 28, 1, 32; -L_0x2c07020 .part v0x2bc7660_0, 28, 1; -L_0x2c070c0 .part v0x2bc7860_0, 28, 1; -L_0x2c08250 .part/pv L_0x2c08020, 29, 1, 32; -L_0x2bfd5b0 .part v0x2bc7660_0, 29, 1; -L_0x2bfd650 .part v0x2bc7860_0, 29, 1; -L_0x2c08e10 .part/pv L_0x2c08be0, 30, 1, 32; -L_0x2c08700 .part v0x2bc7660_0, 30, 1; -L_0x2c087a0 .part v0x2bc7860_0, 30, 1; -L_0x2c097c0 .part/pv L_0x2c09590, 31, 1, 32; -L_0x2c09860 .part v0x2bc7660_0, 31, 1; -L_0x2c08eb0 .part v0x2bc7860_0, 31, 1; -L_0x2c0a170 .part/pv L_0x2c09f40, 0, 1, 32; -L_0x2c09900 .part v0x2bc7660_0, 0, 1; -L_0x2c099a0 .part v0x2bc7860_0, 0, 1; -S_0x2ba24d0 .scope module, "attempt2" "AndNand" 3 165, 3 48, S_0x2b8b740; - .timescale -9 -12; -L_0x2c08fa0/d .functor NAND 1, L_0x2c09900, L_0x2c099a0, C4<1>, C4<1>; -L_0x2c08fa0 .delay (10000,10000,10000) L_0x2c08fa0/d; -L_0x2c09100/d .functor NOT 1, L_0x2c08fa0, C4<0>, C4<0>, C4<0>; -L_0x2c09100 .delay (10000,10000,10000) L_0x2c09100/d; -v0x2ba2af0_0 .net "A", 0 0, L_0x2c09900; 1 drivers -v0x2ba2bb0_0 .net "AandB", 0 0, L_0x2c09100; 1 drivers -v0x2ba2c30_0 .net "AnandB", 0 0, L_0x2c08fa0; 1 drivers -v0x2ba2ce0_0 .net "AndNandOut", 0 0, L_0x2c09f40; 1 drivers -v0x2ba2dc0_0 .net "B", 0 0, L_0x2c099a0; 1 drivers -v0x2ba2e40_0 .alias "Command", 2 0, v0x2bc67a0_0; -L_0x2c0a0d0 .part v0x2bc78e0_0, 0, 1; -S_0x2ba25c0 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0x2ba24d0; - .timescale -9 -12; -L_0x2c09c80/d .functor NOT 1, L_0x2c0a0d0, C4<0>, C4<0>, C4<0>; -L_0x2c09c80 .delay (10000,10000,10000) L_0x2c09c80/d; -L_0x2c09d20/d .functor AND 1, L_0x2c09100, L_0x2c09c80, C4<1>, C4<1>; -L_0x2c09d20 .delay (20000,20000,20000) L_0x2c09d20/d; -L_0x2c09e10/d .functor AND 1, L_0x2c08fa0, L_0x2c0a0d0, C4<1>, C4<1>; -L_0x2c09e10 .delay (20000,20000,20000) L_0x2c09e10/d; -L_0x2c09f40/d .functor OR 1, L_0x2c09d20, L_0x2c09e10, C4<0>, C4<0>; -L_0x2c09f40 .delay (20000,20000,20000) L_0x2c09f40/d; -v0x2ba26b0_0 .net "S", 0 0, L_0x2c0a0d0; 1 drivers -v0x2ba2730_0 .alias "in0", 0 0, v0x2ba2bb0_0; -v0x2ba27b0_0 .alias "in1", 0 0, v0x2ba2c30_0; -v0x2ba2850_0 .net "nS", 0 0, L_0x2c09c80; 1 drivers -v0x2ba28d0_0 .net "out0", 0 0, L_0x2c09d20; 1 drivers -v0x2ba2970_0 .net "out1", 0 0, L_0x2c09e10; 1 drivers -v0x2ba2a50_0 .alias "outfinal", 0 0, v0x2ba2ce0_0; -S_0x2ba1910 .scope generate, "andbits[1]" "andbits[1]" 3 169, 3 169, S_0x2b8b740; - .timescale -9 -12; -P_0x2ba1a08 .param/l "i" 3 169, +C4<01>; -S_0x2ba1a80 .scope module, "attempt" "AndNand" 3 171, 3 48, S_0x2ba1910; - .timescale -9 -12; -L_0x2bf4f20/d .functor NAND 1, L_0x2bf57f0, L_0x2bf5890, C4<1>, C4<1>; -L_0x2bf4f20 .delay (10000,10000,10000) L_0x2bf4f20/d; -L_0x2bf4fe0/d .functor NOT 1, L_0x2bf4f20, C4<0>, C4<0>, C4<0>; -L_0x2bf4fe0 .delay (10000,10000,10000) L_0x2bf4fe0/d; -v0x2ba20c0_0 .net "A", 0 0, L_0x2bf57f0; 1 drivers -v0x2ba2180_0 .net "AandB", 0 0, L_0x2bf4fe0; 1 drivers -v0x2ba2200_0 .net "AnandB", 0 0, L_0x2bf4f20; 1 drivers -v0x2ba22b0_0 .net "AndNandOut", 0 0, L_0x2bf5430; 1 drivers -v0x2ba2390_0 .net "B", 0 0, L_0x2bf5890; 1 drivers -v0x2ba2410_0 .alias "Command", 2 0, v0x2bc67a0_0; -L_0x2bf5600 .part v0x2bc78e0_0, 0, 1; -S_0x2ba1b70 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0x2ba1a80; - .timescale -9 -12; -L_0x2bf5110/d .functor NOT 1, L_0x2bf5600, C4<0>, C4<0>, C4<0>; -L_0x2bf5110 .delay (10000,10000,10000) L_0x2bf5110/d; -L_0x2bf51d0/d .functor AND 1, L_0x2bf4fe0, L_0x2bf5110, C4<1>, C4<1>; -L_0x2bf51d0 .delay (20000,20000,20000) L_0x2bf51d0/d; -L_0x2bf52e0/d .functor AND 1, L_0x2bf4f20, L_0x2bf5600, C4<1>, C4<1>; -L_0x2bf52e0 .delay (20000,20000,20000) L_0x2bf52e0/d; -L_0x2bf5430/d .functor OR 1, L_0x2bf51d0, L_0x2bf52e0, C4<0>, C4<0>; -L_0x2bf5430 .delay (20000,20000,20000) L_0x2bf5430/d; -v0x2ba1c60_0 .net "S", 0 0, L_0x2bf5600; 1 drivers -v0x2ba1ce0_0 .alias "in0", 0 0, v0x2ba2180_0; -v0x2ba1d80_0 .alias "in1", 0 0, v0x2ba2200_0; -v0x2ba1e20_0 .net "nS", 0 0, L_0x2bf5110; 1 drivers -v0x2ba1ea0_0 .net "out0", 0 0, L_0x2bf51d0; 1 drivers -v0x2ba1f40_0 .net "out1", 0 0, L_0x2bf52e0; 1 drivers -v0x2ba2020_0 .alias "outfinal", 0 0, v0x2ba22b0_0; -S_0x2ba0d50 .scope generate, "andbits[2]" "andbits[2]" 3 169, 3 169, S_0x2b8b740; - .timescale -9 -12; -P_0x2ba0e48 .param/l "i" 3 169, +C4<010>; -S_0x2ba0ec0 .scope module, "attempt" "AndNand" 3 171, 3 48, S_0x2ba0d50; - .timescale -9 -12; -L_0x2bf5930/d .functor NAND 1, L_0x2bf61f0, L_0x2bf6290, C4<1>, C4<1>; -L_0x2bf5930 .delay (10000,10000,10000) L_0x2bf5930/d; -L_0x2bf5a90/d .functor NOT 1, L_0x2bf5930, C4<0>, C4<0>, C4<0>; -L_0x2bf5a90 .delay (10000,10000,10000) L_0x2bf5a90/d; -v0x2ba1500_0 .net "A", 0 0, L_0x2bf61f0; 1 drivers -v0x2ba15c0_0 .net "AandB", 0 0, L_0x2bf5a90; 1 drivers -v0x2ba1640_0 .net "AnandB", 0 0, L_0x2bf5930; 1 drivers -v0x2ba16f0_0 .net "AndNandOut", 0 0, L_0x2bf5ee0; 1 drivers -v0x2ba17d0_0 .net "B", 0 0, L_0x2bf6290; 1 drivers -v0x2ba1850_0 .alias "Command", 2 0, v0x2bc67a0_0; -L_0x2bf60b0 .part v0x2bc78e0_0, 0, 1; -S_0x2ba0fb0 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0x2ba0ec0; - .timescale -9 -12; -L_0x2bf5bc0/d .functor NOT 1, L_0x2bf60b0, C4<0>, C4<0>, C4<0>; -L_0x2bf5bc0 .delay (10000,10000,10000) L_0x2bf5bc0/d; -L_0x2bf5c80/d .functor AND 1, L_0x2bf5a90, L_0x2bf5bc0, C4<1>, C4<1>; -L_0x2bf5c80 .delay (20000,20000,20000) L_0x2bf5c80/d; -L_0x2bf5d90/d .functor AND 1, L_0x2bf5930, L_0x2bf60b0, C4<1>, C4<1>; -L_0x2bf5d90 .delay (20000,20000,20000) L_0x2bf5d90/d; -L_0x2bf5ee0/d .functor OR 1, L_0x2bf5c80, L_0x2bf5d90, C4<0>, C4<0>; -L_0x2bf5ee0 .delay (20000,20000,20000) L_0x2bf5ee0/d; -v0x2ba10a0_0 .net "S", 0 0, L_0x2bf60b0; 1 drivers -v0x2ba1120_0 .alias "in0", 0 0, v0x2ba15c0_0; -v0x2ba11c0_0 .alias "in1", 0 0, v0x2ba1640_0; -v0x2ba1260_0 .net "nS", 0 0, L_0x2bf5bc0; 1 drivers -v0x2ba12e0_0 .net "out0", 0 0, L_0x2bf5c80; 1 drivers -v0x2ba1380_0 .net "out1", 0 0, L_0x2bf5d90; 1 drivers -v0x2ba1460_0 .alias "outfinal", 0 0, v0x2ba16f0_0; -S_0x2ba0190 .scope generate, "andbits[3]" "andbits[3]" 3 169, 3 169, S_0x2b8b740; - .timescale -9 -12; -P_0x2ba0288 .param/l "i" 3 169, +C4<011>; -S_0x2ba0300 .scope module, "attempt" "AndNand" 3 171, 3 48, S_0x2ba0190; - .timescale -9 -12; -L_0x2bf63c0/d .functor NAND 1, L_0x2bf6c60, L_0x2bf6d50, C4<1>, C4<1>; -L_0x2bf63c0 .delay (10000,10000,10000) L_0x2bf63c0/d; -L_0x2bf6500/d .functor NOT 1, L_0x2bf63c0, C4<0>, C4<0>, C4<0>; -L_0x2bf6500 .delay (10000,10000,10000) L_0x2bf6500/d; -v0x2ba0940_0 .net "A", 0 0, L_0x2bf6c60; 1 drivers -v0x2ba0a00_0 .net "AandB", 0 0, L_0x2bf6500; 1 drivers -v0x2ba0a80_0 .net "AnandB", 0 0, L_0x2bf63c0; 1 drivers -v0x2ba0b30_0 .net "AndNandOut", 0 0, L_0x2bf6950; 1 drivers -v0x2ba0c10_0 .net "B", 0 0, L_0x2bf6d50; 1 drivers -v0x2ba0c90_0 .alias "Command", 2 0, v0x2bc67a0_0; -L_0x2bf6b20 .part v0x2bc78e0_0, 0, 1; -S_0x2ba03f0 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0x2ba0300; - .timescale -9 -12; -L_0x2bf6630/d .functor NOT 1, L_0x2bf6b20, C4<0>, C4<0>, C4<0>; -L_0x2bf6630 .delay (10000,10000,10000) L_0x2bf6630/d; -L_0x2bf66f0/d .functor AND 1, L_0x2bf6500, L_0x2bf6630, C4<1>, C4<1>; -L_0x2bf66f0 .delay (20000,20000,20000) L_0x2bf66f0/d; -L_0x2bf6800/d .functor AND 1, L_0x2bf63c0, L_0x2bf6b20, C4<1>, C4<1>; -L_0x2bf6800 .delay (20000,20000,20000) L_0x2bf6800/d; -L_0x2bf6950/d .functor OR 1, L_0x2bf66f0, L_0x2bf6800, C4<0>, C4<0>; -L_0x2bf6950 .delay (20000,20000,20000) L_0x2bf6950/d; -v0x2ba04e0_0 .net "S", 0 0, L_0x2bf6b20; 1 drivers -v0x2ba0560_0 .alias "in0", 0 0, v0x2ba0a00_0; -v0x2ba0600_0 .alias "in1", 0 0, v0x2ba0a80_0; -v0x2ba06a0_0 .net "nS", 0 0, L_0x2bf6630; 1 drivers -v0x2ba0720_0 .net "out0", 0 0, L_0x2bf66f0; 1 drivers -v0x2ba07c0_0 .net "out1", 0 0, L_0x2bf6800; 1 drivers -v0x2ba08a0_0 .alias "outfinal", 0 0, v0x2ba0b30_0; -S_0x2b9f5d0 .scope generate, "andbits[4]" "andbits[4]" 3 169, 3 169, S_0x2b8b740; - .timescale -9 -12; -P_0x2b9f6c8 .param/l "i" 3 169, +C4<0100>; -S_0x2b9f740 .scope module, "attempt" "AndNand" 3 171, 3 48, S_0x2b9f5d0; - .timescale -9 -12; -L_0x2bf6e40/d .functor NAND 1, L_0x2bf7720, L_0x2bf77c0, C4<1>, C4<1>; -L_0x2bf6e40 .delay (10000,10000,10000) L_0x2bf6e40/d; -L_0x2bf6f60/d .functor NOT 1, L_0x2bf6e40, C4<0>, C4<0>, C4<0>; -L_0x2bf6f60 .delay (10000,10000,10000) L_0x2bf6f60/d; -v0x2b9fd80_0 .net "A", 0 0, L_0x2bf7720; 1 drivers -v0x2b9fe40_0 .net "AandB", 0 0, L_0x2bf6f60; 1 drivers -v0x2b9fec0_0 .net "AnandB", 0 0, L_0x2bf6e40; 1 drivers -v0x2b9ff70_0 .net "AndNandOut", 0 0, L_0x2bf73b0; 1 drivers -v0x2ba0050_0 .net "B", 0 0, L_0x2bf77c0; 1 drivers -v0x2ba00d0_0 .alias "Command", 2 0, v0x2bc67a0_0; -L_0x2bf7580 .part v0x2bc78e0_0, 0, 1; -S_0x2b9f830 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0x2b9f740; - .timescale -9 -12; -L_0x2bf7090/d .functor NOT 1, L_0x2bf7580, C4<0>, C4<0>, C4<0>; -L_0x2bf7090 .delay (10000,10000,10000) L_0x2bf7090/d; -L_0x2bf7150/d .functor AND 1, L_0x2bf6f60, L_0x2bf7090, C4<1>, C4<1>; -L_0x2bf7150 .delay (20000,20000,20000) L_0x2bf7150/d; -L_0x2bf7260/d .functor AND 1, L_0x2bf6e40, L_0x2bf7580, C4<1>, C4<1>; -L_0x2bf7260 .delay (20000,20000,20000) L_0x2bf7260/d; -L_0x2bf73b0/d .functor OR 1, L_0x2bf7150, L_0x2bf7260, C4<0>, C4<0>; -L_0x2bf73b0 .delay (20000,20000,20000) L_0x2bf73b0/d; -v0x2b9f920_0 .net "S", 0 0, L_0x2bf7580; 1 drivers -v0x2b9f9a0_0 .alias "in0", 0 0, v0x2b9fe40_0; -v0x2b9fa40_0 .alias "in1", 0 0, v0x2b9fec0_0; -v0x2b9fae0_0 .net "nS", 0 0, L_0x2bf7090; 1 drivers -v0x2b9fb60_0 .net "out0", 0 0, L_0x2bf7150; 1 drivers -v0x2b9fc00_0 .net "out1", 0 0, L_0x2bf7260; 1 drivers -v0x2b9fce0_0 .alias "outfinal", 0 0, v0x2b9ff70_0; -S_0x2b9ea10 .scope generate, "andbits[5]" "andbits[5]" 3 169, 3 169, S_0x2b8b740; - .timescale -9 -12; -P_0x2b9eb08 .param/l "i" 3 169, +C4<0101>; -S_0x2b9eb80 .scope module, "attempt" "AndNand" 3 171, 3 48, S_0x2b9ea10; - .timescale -9 -12; -L_0x2bf76c0/d .functor NAND 1, L_0x2bf8240, L_0x2bf82e0, C4<1>, C4<1>; -L_0x2bf76c0 .delay (10000,10000,10000) L_0x2bf76c0/d; -L_0x2bf79d0/d .functor NOT 1, L_0x2bf76c0, C4<0>, C4<0>, C4<0>; -L_0x2bf79d0 .delay (10000,10000,10000) L_0x2bf79d0/d; -v0x2b9f1c0_0 .net "A", 0 0, L_0x2bf8240; 1 drivers -v0x2b9f280_0 .net "AandB", 0 0, L_0x2bf79d0; 1 drivers -v0x2b9f300_0 .net "AnandB", 0 0, L_0x2bf76c0; 1 drivers -v0x2b9f3b0_0 .net "AndNandOut", 0 0, L_0x2bf7e20; 1 drivers -v0x2b9f490_0 .net "B", 0 0, L_0x2bf82e0; 1 drivers -v0x2b9f510_0 .alias "Command", 2 0, v0x2bc67a0_0; -L_0x2bf7ff0 .part v0x2bc78e0_0, 0, 1; -S_0x2b9ec70 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0x2b9eb80; - .timescale -9 -12; -L_0x2bf7b00/d .functor NOT 1, L_0x2bf7ff0, C4<0>, C4<0>, C4<0>; -L_0x2bf7b00 .delay (10000,10000,10000) L_0x2bf7b00/d; -L_0x2bf7bc0/d .functor AND 1, L_0x2bf79d0, L_0x2bf7b00, C4<1>, C4<1>; -L_0x2bf7bc0 .delay (20000,20000,20000) L_0x2bf7bc0/d; -L_0x2bf7cd0/d .functor AND 1, L_0x2bf76c0, L_0x2bf7ff0, C4<1>, C4<1>; -L_0x2bf7cd0 .delay (20000,20000,20000) L_0x2bf7cd0/d; -L_0x2bf7e20/d .functor OR 1, L_0x2bf7bc0, L_0x2bf7cd0, C4<0>, C4<0>; -L_0x2bf7e20 .delay (20000,20000,20000) L_0x2bf7e20/d; -v0x2b9ed60_0 .net "S", 0 0, L_0x2bf7ff0; 1 drivers -v0x2b9ede0_0 .alias "in0", 0 0, v0x2b9f280_0; -v0x2b9ee80_0 .alias "in1", 0 0, v0x2b9f300_0; -v0x2b9ef20_0 .net "nS", 0 0, L_0x2bf7b00; 1 drivers -v0x2b9efa0_0 .net "out0", 0 0, L_0x2bf7bc0; 1 drivers -v0x2b9f040_0 .net "out1", 0 0, L_0x2bf7cd0; 1 drivers -v0x2b9f120_0 .alias "outfinal", 0 0, v0x2b9f3b0_0; -S_0x2b9de50 .scope generate, "andbits[6]" "andbits[6]" 3 169, 3 169, S_0x2b8b740; - .timescale -9 -12; -P_0x2b9df48 .param/l "i" 3 169, +C4<0110>; -S_0x2b9dfc0 .scope module, "attempt" "AndNand" 3 171, 3 48, S_0x2b9de50; - .timescale -9 -12; -L_0x2bf83d0/d .functor NAND 1, L_0x2bf8c90, L_0x2bf8d30, C4<1>, C4<1>; -L_0x2bf83d0 .delay (10000,10000,10000) L_0x2bf83d0/d; -L_0x2bf8530/d .functor NOT 1, L_0x2bf83d0, C4<0>, C4<0>, C4<0>; -L_0x2bf8530 .delay (10000,10000,10000) L_0x2bf8530/d; -v0x2b9e600_0 .net "A", 0 0, L_0x2bf8c90; 1 drivers -v0x2b9e6c0_0 .net "AandB", 0 0, L_0x2bf8530; 1 drivers -v0x2b9e740_0 .net "AnandB", 0 0, L_0x2bf83d0; 1 drivers -v0x2b9e7f0_0 .net "AndNandOut", 0 0, L_0x2bf8980; 1 drivers -v0x2b9e8d0_0 .net "B", 0 0, L_0x2bf8d30; 1 drivers -v0x2b9e950_0 .alias "Command", 2 0, v0x2bc67a0_0; -L_0x2bf8b50 .part v0x2bc78e0_0, 0, 1; -S_0x2b9e0b0 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0x2b9dfc0; - .timescale -9 -12; -L_0x2bf8660/d .functor NOT 1, L_0x2bf8b50, C4<0>, C4<0>, C4<0>; -L_0x2bf8660 .delay (10000,10000,10000) L_0x2bf8660/d; -L_0x2bf8720/d .functor AND 1, L_0x2bf8530, L_0x2bf8660, C4<1>, C4<1>; -L_0x2bf8720 .delay (20000,20000,20000) L_0x2bf8720/d; -L_0x2bf8830/d .functor AND 1, L_0x2bf83d0, L_0x2bf8b50, C4<1>, C4<1>; -L_0x2bf8830 .delay (20000,20000,20000) L_0x2bf8830/d; -L_0x2bf8980/d .functor OR 1, L_0x2bf8720, L_0x2bf8830, C4<0>, C4<0>; -L_0x2bf8980 .delay (20000,20000,20000) L_0x2bf8980/d; -v0x2b9e1a0_0 .net "S", 0 0, L_0x2bf8b50; 1 drivers -v0x2b9e220_0 .alias "in0", 0 0, v0x2b9e6c0_0; -v0x2b9e2c0_0 .alias "in1", 0 0, v0x2b9e740_0; -v0x2b9e360_0 .net "nS", 0 0, L_0x2bf8660; 1 drivers -v0x2b9e3e0_0 .net "out0", 0 0, L_0x2bf8720; 1 drivers -v0x2b9e480_0 .net "out1", 0 0, L_0x2bf8830; 1 drivers -v0x2b9e560_0 .alias "outfinal", 0 0, v0x2b9e7f0_0; -S_0x2b9d290 .scope generate, "andbits[7]" "andbits[7]" 3 169, 3 169, S_0x2b8b740; - .timescale -9 -12; -P_0x2b9d388 .param/l "i" 3 169, +C4<0111>; -S_0x2b9d400 .scope module, "attempt" "AndNand" 3 171, 3 48, S_0x2b9d290; - .timescale -9 -12; -L_0x2bf5740/d .functor NAND 1, L_0x2bf9700, L_0x2bf8e20, C4<1>, C4<1>; -L_0x2bf5740 .delay (10000,10000,10000) L_0x2bf5740/d; -L_0x2bf8fa0/d .functor NOT 1, L_0x2bf5740, C4<0>, C4<0>, C4<0>; -L_0x2bf8fa0 .delay (10000,10000,10000) L_0x2bf8fa0/d; -v0x2b9da40_0 .net "A", 0 0, L_0x2bf9700; 1 drivers -v0x2b9db00_0 .net "AandB", 0 0, L_0x2bf8fa0; 1 drivers -v0x2b9db80_0 .net "AnandB", 0 0, L_0x2bf5740; 1 drivers -v0x2b9dc30_0 .net "AndNandOut", 0 0, L_0x2bf93f0; 1 drivers -v0x2b9dd10_0 .net "B", 0 0, L_0x2bf8e20; 1 drivers -v0x2b9dd90_0 .alias "Command", 2 0, v0x2bc67a0_0; -L_0x2bf95c0 .part v0x2bc78e0_0, 0, 1; -S_0x2b9d4f0 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0x2b9d400; - .timescale -9 -12; -L_0x2bf90d0/d .functor NOT 1, L_0x2bf95c0, C4<0>, C4<0>, C4<0>; -L_0x2bf90d0 .delay (10000,10000,10000) L_0x2bf90d0/d; -L_0x2bf9190/d .functor AND 1, L_0x2bf8fa0, L_0x2bf90d0, C4<1>, C4<1>; -L_0x2bf9190 .delay (20000,20000,20000) L_0x2bf9190/d; -L_0x2bf92a0/d .functor AND 1, L_0x2bf5740, L_0x2bf95c0, C4<1>, C4<1>; -L_0x2bf92a0 .delay (20000,20000,20000) L_0x2bf92a0/d; -L_0x2bf93f0/d .functor OR 1, L_0x2bf9190, L_0x2bf92a0, C4<0>, C4<0>; -L_0x2bf93f0 .delay (20000,20000,20000) L_0x2bf93f0/d; -v0x2b9d5e0_0 .net "S", 0 0, L_0x2bf95c0; 1 drivers -v0x2b9d660_0 .alias "in0", 0 0, v0x2b9db00_0; -v0x2b9d700_0 .alias "in1", 0 0, v0x2b9db80_0; -v0x2b9d7a0_0 .net "nS", 0 0, L_0x2bf90d0; 1 drivers -v0x2b9d820_0 .net "out0", 0 0, L_0x2bf9190; 1 drivers -v0x2b9d8c0_0 .net "out1", 0 0, L_0x2bf92a0; 1 drivers -v0x2b9d9a0_0 .alias "outfinal", 0 0, v0x2b9dc30_0; -S_0x2b9c6d0 .scope generate, "andbits[8]" "andbits[8]" 3 169, 3 169, S_0x2b8b740; - .timescale -9 -12; -P_0x2b9c7c8 .param/l "i" 3 169, +C4<01000>; -S_0x2b9c840 .scope module, "attempt" "AndNand" 3 171, 3 48, S_0x2b9c6d0; - .timescale -9 -12; -L_0x2bf98a0/d .functor NAND 1, L_0x2bf97a0, L_0x2bfa220, C4<1>, C4<1>; -L_0x2bf98a0 .delay (10000,10000,10000) L_0x2bf98a0/d; -L_0x2bf9a00/d .functor NOT 1, L_0x2bf98a0, C4<0>, C4<0>, C4<0>; -L_0x2bf9a00 .delay (10000,10000,10000) L_0x2bf9a00/d; -v0x2b9ce80_0 .net "A", 0 0, L_0x2bf97a0; 1 drivers -v0x2b9cf40_0 .net "AandB", 0 0, L_0x2bf9a00; 1 drivers -v0x2b9cfc0_0 .net "AnandB", 0 0, L_0x2bf98a0; 1 drivers -v0x2b9d070_0 .net "AndNandOut", 0 0, L_0x2bf9e50; 1 drivers -v0x2b9d150_0 .net "B", 0 0, L_0x2bfa220; 1 drivers -v0x2b9d1d0_0 .alias "Command", 2 0, v0x2bc67a0_0; -L_0x2bfa020 .part v0x2bc78e0_0, 0, 1; -S_0x2b9c930 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0x2b9c840; - .timescale -9 -12; -L_0x2bf9b30/d .functor NOT 1, L_0x2bfa020, C4<0>, C4<0>, C4<0>; -L_0x2bf9b30 .delay (10000,10000,10000) L_0x2bf9b30/d; -L_0x2bf9bf0/d .functor AND 1, L_0x2bf9a00, L_0x2bf9b30, C4<1>, C4<1>; -L_0x2bf9bf0 .delay (20000,20000,20000) L_0x2bf9bf0/d; -L_0x2bf9d00/d .functor AND 1, L_0x2bf98a0, L_0x2bfa020, C4<1>, C4<1>; -L_0x2bf9d00 .delay (20000,20000,20000) L_0x2bf9d00/d; -L_0x2bf9e50/d .functor OR 1, L_0x2bf9bf0, L_0x2bf9d00, C4<0>, C4<0>; -L_0x2bf9e50 .delay (20000,20000,20000) L_0x2bf9e50/d; -v0x2b9ca20_0 .net "S", 0 0, L_0x2bfa020; 1 drivers -v0x2b9caa0_0 .alias "in0", 0 0, v0x2b9cf40_0; -v0x2b9cb40_0 .alias "in1", 0 0, v0x2b9cfc0_0; -v0x2b9cbe0_0 .net "nS", 0 0, L_0x2bf9b30; 1 drivers -v0x2b9cc60_0 .net "out0", 0 0, L_0x2bf9bf0; 1 drivers -v0x2b9cd00_0 .net "out1", 0 0, L_0x2bf9d00; 1 drivers -v0x2b9cde0_0 .alias "outfinal", 0 0, v0x2b9d070_0; -S_0x2b9bb10 .scope generate, "andbits[9]" "andbits[9]" 3 169, 3 169, S_0x2b8b740; - .timescale -9 -12; -P_0x2b9bc08 .param/l "i" 3 169, +C4<01001>; -S_0x2b9bc80 .scope module, "attempt" "AndNand" 3 171, 3 48, S_0x2b9bb10; - .timescale -9 -12; -L_0x2bfa160/d .functor NAND 1, L_0x2bfabe0, L_0x2bfa310, C4<1>, C4<1>; -L_0x2bfa160 .delay (10000,10000,10000) L_0x2bfa160/d; -L_0x2bfa480/d .functor NOT 1, L_0x2bfa160, C4<0>, C4<0>, C4<0>; -L_0x2bfa480 .delay (10000,10000,10000) L_0x2bfa480/d; -v0x2b9c2c0_0 .net "A", 0 0, L_0x2bfabe0; 1 drivers -v0x2b9c380_0 .net "AandB", 0 0, L_0x2bfa480; 1 drivers -v0x2b9c400_0 .net "AnandB", 0 0, L_0x2bfa160; 1 drivers -v0x2b9c4b0_0 .net "AndNandOut", 0 0, L_0x2bfa8d0; 1 drivers -v0x2b9c590_0 .net "B", 0 0, L_0x2bfa310; 1 drivers -v0x2b9c610_0 .alias "Command", 2 0, v0x2bc67a0_0; -L_0x2bfaaa0 .part v0x2bc78e0_0, 0, 1; -S_0x2b9bd70 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0x2b9bc80; - .timescale -9 -12; -L_0x2bfa5b0/d .functor NOT 1, L_0x2bfaaa0, C4<0>, C4<0>, C4<0>; -L_0x2bfa5b0 .delay (10000,10000,10000) L_0x2bfa5b0/d; -L_0x2bfa670/d .functor AND 1, L_0x2bfa480, L_0x2bfa5b0, C4<1>, C4<1>; -L_0x2bfa670 .delay (20000,20000,20000) L_0x2bfa670/d; -L_0x2bfa780/d .functor AND 1, L_0x2bfa160, L_0x2bfaaa0, C4<1>, C4<1>; -L_0x2bfa780 .delay (20000,20000,20000) L_0x2bfa780/d; -L_0x2bfa8d0/d .functor OR 1, L_0x2bfa670, L_0x2bfa780, C4<0>, C4<0>; -L_0x2bfa8d0 .delay (20000,20000,20000) L_0x2bfa8d0/d; -v0x2b9be60_0 .net "S", 0 0, L_0x2bfaaa0; 1 drivers -v0x2b9bee0_0 .alias "in0", 0 0, v0x2b9c380_0; -v0x2b9bf80_0 .alias "in1", 0 0, v0x2b9c400_0; -v0x2b9c020_0 .net "nS", 0 0, L_0x2bfa5b0; 1 drivers -v0x2b9c0a0_0 .net "out0", 0 0, L_0x2bfa670; 1 drivers -v0x2b9c140_0 .net "out1", 0 0, L_0x2bfa780; 1 drivers -v0x2b9c220_0 .alias "outfinal", 0 0, v0x2b9c4b0_0; -S_0x2b9af50 .scope generate, "andbits[10]" "andbits[10]" 3 169, 3 169, S_0x2b8b740; - .timescale -9 -12; -P_0x2b9b048 .param/l "i" 3 169, +C4<01010>; -S_0x2b9b0c0 .scope module, "attempt" "AndNand" 3 171, 3 48, S_0x2b9af50; - .timescale -9 -12; -L_0x2bfadb0/d .functor NAND 1, L_0x2bfac80, L_0x2bfb740, C4<1>, C4<1>; -L_0x2bfadb0 .delay (10000,10000,10000) L_0x2bfadb0/d; -L_0x2bfaef0/d .functor NOT 1, L_0x2bfadb0, C4<0>, C4<0>, C4<0>; -L_0x2bfaef0 .delay (10000,10000,10000) L_0x2bfaef0/d; -v0x2b9b700_0 .net "A", 0 0, L_0x2bfac80; 1 drivers -v0x2b9b7c0_0 .net "AandB", 0 0, L_0x2bfaef0; 1 drivers -v0x2b9b840_0 .net "AnandB", 0 0, L_0x2bfadb0; 1 drivers -v0x2b9b8f0_0 .net "AndNandOut", 0 0, L_0x2bfb340; 1 drivers -v0x2b9b9d0_0 .net "B", 0 0, L_0x2bfb740; 1 drivers -v0x2b9ba50_0 .alias "Command", 2 0, v0x2bc67a0_0; -L_0x2bfb510 .part v0x2bc78e0_0, 0, 1; -S_0x2b9b1b0 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0x2b9b0c0; - .timescale -9 -12; -L_0x2bfb020/d .functor NOT 1, L_0x2bfb510, C4<0>, C4<0>, C4<0>; -L_0x2bfb020 .delay (10000,10000,10000) L_0x2bfb020/d; -L_0x2bfb0e0/d .functor AND 1, L_0x2bfaef0, L_0x2bfb020, C4<1>, C4<1>; -L_0x2bfb0e0 .delay (20000,20000,20000) L_0x2bfb0e0/d; -L_0x2bfb1f0/d .functor AND 1, L_0x2bfadb0, L_0x2bfb510, C4<1>, C4<1>; -L_0x2bfb1f0 .delay (20000,20000,20000) L_0x2bfb1f0/d; -L_0x2bfb340/d .functor OR 1, L_0x2bfb0e0, L_0x2bfb1f0, C4<0>, C4<0>; -L_0x2bfb340 .delay (20000,20000,20000) L_0x2bfb340/d; -v0x2b9b2a0_0 .net "S", 0 0, L_0x2bfb510; 1 drivers -v0x2b9b320_0 .alias "in0", 0 0, v0x2b9b7c0_0; -v0x2b9b3c0_0 .alias "in1", 0 0, v0x2b9b840_0; -v0x2b9b460_0 .net "nS", 0 0, L_0x2bfb020; 1 drivers -v0x2b9b4e0_0 .net "out0", 0 0, L_0x2bfb0e0; 1 drivers -v0x2b9b580_0 .net "out1", 0 0, L_0x2bfb1f0; 1 drivers -v0x2b9b660_0 .alias "outfinal", 0 0, v0x2b9b8f0_0; -S_0x2b9a390 .scope generate, "andbits[11]" "andbits[11]" 3 169, 3 169, S_0x2b8b740; - .timescale -9 -12; -P_0x2b9a488 .param/l "i" 3 169, +C4<01011>; -S_0x2b9a500 .scope module, "attempt" "AndNand" 3 171, 3 48, S_0x2b9a390; - .timescale -9 -12; -L_0x2bfb650/d .functor NAND 1, L_0x2bfc0c0, L_0x2bfb830, C4<1>, C4<1>; -L_0x2bfb650 .delay (10000,10000,10000) L_0x2bfb650/d; -L_0x2bfb980/d .functor NOT 1, L_0x2bfb650, C4<0>, C4<0>, C4<0>; -L_0x2bfb980 .delay (10000,10000,10000) L_0x2bfb980/d; -v0x2b9ab40_0 .net "A", 0 0, L_0x2bfc0c0; 1 drivers -v0x2b9ac00_0 .net "AandB", 0 0, L_0x2bfb980; 1 drivers -v0x2b9ac80_0 .net "AnandB", 0 0, L_0x2bfb650; 1 drivers -v0x2b9ad30_0 .net "AndNandOut", 0 0, L_0x2bfbdb0; 1 drivers -v0x2b9ae10_0 .net "B", 0 0, L_0x2bfb830; 1 drivers -v0x2b9ae90_0 .alias "Command", 2 0, v0x2bc67a0_0; -L_0x2bfbf80 .part v0x2bc78e0_0, 0, 1; -S_0x2b9a5f0 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0x2b9a500; - .timescale -9 -12; -L_0x2bfba90/d .functor NOT 1, L_0x2bfbf80, C4<0>, C4<0>, C4<0>; -L_0x2bfba90 .delay (10000,10000,10000) L_0x2bfba90/d; -L_0x2bfbb50/d .functor AND 1, L_0x2bfb980, L_0x2bfba90, C4<1>, C4<1>; -L_0x2bfbb50 .delay (20000,20000,20000) L_0x2bfbb50/d; -L_0x2bfbc60/d .functor AND 1, L_0x2bfb650, L_0x2bfbf80, C4<1>, C4<1>; -L_0x2bfbc60 .delay (20000,20000,20000) L_0x2bfbc60/d; -L_0x2bfbdb0/d .functor OR 1, L_0x2bfbb50, L_0x2bfbc60, C4<0>, C4<0>; -L_0x2bfbdb0 .delay (20000,20000,20000) L_0x2bfbdb0/d; -v0x2b9a6e0_0 .net "S", 0 0, L_0x2bfbf80; 1 drivers -v0x2b9a760_0 .alias "in0", 0 0, v0x2b9ac00_0; -v0x2b9a800_0 .alias "in1", 0 0, v0x2b9ac80_0; -v0x2b9a8a0_0 .net "nS", 0 0, L_0x2bfba90; 1 drivers -v0x2b9a920_0 .net "out0", 0 0, L_0x2bfbb50; 1 drivers -v0x2b9a9c0_0 .net "out1", 0 0, L_0x2bfbc60; 1 drivers -v0x2b9aaa0_0 .alias "outfinal", 0 0, v0x2b9ad30_0; -S_0x2b997d0 .scope generate, "andbits[12]" "andbits[12]" 3 169, 3 169, S_0x2b8b740; - .timescale -9 -12; -P_0x2b998c8 .param/l "i" 3 169, +C4<01100>; -S_0x2b99940 .scope module, "attempt" "AndNand" 3 171, 3 48, S_0x2b997d0; - .timescale -9 -12; -L_0x2bfc270/d .functor NAND 1, L_0x2bfc160, L_0x2bfcc50, C4<1>, C4<1>; -L_0x2bfc270 .delay (10000,10000,10000) L_0x2bfc270/d; -L_0x2bfc3d0/d .functor NOT 1, L_0x2bfc270, C4<0>, C4<0>, C4<0>; -L_0x2bfc3d0 .delay (10000,10000,10000) L_0x2bfc3d0/d; -v0x2b99f80_0 .net "A", 0 0, L_0x2bfc160; 1 drivers -v0x2b9a040_0 .net "AandB", 0 0, L_0x2bfc3d0; 1 drivers -v0x2b9a0c0_0 .net "AnandB", 0 0, L_0x2bfc270; 1 drivers -v0x2b9a170_0 .net "AndNandOut", 0 0, L_0x2bfc820; 1 drivers -v0x2b9a250_0 .net "B", 0 0, L_0x2bfcc50; 1 drivers -v0x2b9a2d0_0 .alias "Command", 2 0, v0x2bc67a0_0; -L_0x2bfc9f0 .part v0x2bc78e0_0, 0, 1; -S_0x2b99a30 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0x2b99940; - .timescale -9 -12; -L_0x2bfc500/d .functor NOT 1, L_0x2bfc9f0, C4<0>, C4<0>, C4<0>; -L_0x2bfc500 .delay (10000,10000,10000) L_0x2bfc500/d; -L_0x2bfc5c0/d .functor AND 1, L_0x2bfc3d0, L_0x2bfc500, C4<1>, C4<1>; -L_0x2bfc5c0 .delay (20000,20000,20000) L_0x2bfc5c0/d; -L_0x2bfc6d0/d .functor AND 1, L_0x2bfc270, L_0x2bfc9f0, C4<1>, C4<1>; -L_0x2bfc6d0 .delay (20000,20000,20000) L_0x2bfc6d0/d; -L_0x2bfc820/d .functor OR 1, L_0x2bfc5c0, L_0x2bfc6d0, C4<0>, C4<0>; -L_0x2bfc820 .delay (20000,20000,20000) L_0x2bfc820/d; -v0x2b99b20_0 .net "S", 0 0, L_0x2bfc9f0; 1 drivers -v0x2b99ba0_0 .alias "in0", 0 0, v0x2b9a040_0; -v0x2b99c40_0 .alias "in1", 0 0, v0x2b9a0c0_0; -v0x2b99ce0_0 .net "nS", 0 0, L_0x2bfc500; 1 drivers -v0x2b99d60_0 .net "out0", 0 0, L_0x2bfc5c0; 1 drivers -v0x2b99e00_0 .net "out1", 0 0, L_0x2bfc6d0; 1 drivers -v0x2b99ee0_0 .alias "outfinal", 0 0, v0x2b9a170_0; -S_0x2b98c10 .scope generate, "andbits[13]" "andbits[13]" 3 169, 3 169, S_0x2b8b740; - .timescale -9 -12; -P_0x2b98d08 .param/l "i" 3 169, +C4<01101>; -S_0x2b98d80 .scope module, "attempt" "AndNand" 3 171, 3 48, S_0x2b98c10; - .timescale -9 -12; -L_0x2bfcb30/d .functor NAND 1, L_0x2bf8130, L_0x2bfccf0, C4<1>, C4<1>; -L_0x2bfcb30 .delay (10000,10000,10000) L_0x2bfcb30/d; -L_0x2bfce70/d .functor NOT 1, L_0x2bfcb30, C4<0>, C4<0>, C4<0>; -L_0x2bfce70 .delay (10000,10000,10000) L_0x2bfce70/d; -v0x2b993c0_0 .net "A", 0 0, L_0x2bf8130; 1 drivers -v0x2b99480_0 .net "AandB", 0 0, L_0x2bfce70; 1 drivers -v0x2b99500_0 .net "AnandB", 0 0, L_0x2bfcb30; 1 drivers -v0x2b995b0_0 .net "AndNandOut", 0 0, L_0x2bfd2a0; 1 drivers -v0x2b99690_0 .net "B", 0 0, L_0x2bfccf0; 1 drivers -v0x2b99710_0 .alias "Command", 2 0, v0x2bc67a0_0; -L_0x2bfd470 .part v0x2bc78e0_0, 0, 1; -S_0x2b98e70 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0x2b98d80; - .timescale -9 -12; -L_0x2bfcf80/d .functor NOT 1, L_0x2bfd470, C4<0>, C4<0>, C4<0>; -L_0x2bfcf80 .delay (10000,10000,10000) L_0x2bfcf80/d; -L_0x2bfd040/d .functor AND 1, L_0x2bfce70, L_0x2bfcf80, C4<1>, C4<1>; -L_0x2bfd040 .delay (20000,20000,20000) L_0x2bfd040/d; -L_0x2bfd150/d .functor AND 1, L_0x2bfcb30, L_0x2bfd470, C4<1>, C4<1>; -L_0x2bfd150 .delay (20000,20000,20000) L_0x2bfd150/d; -L_0x2bfd2a0/d .functor OR 1, L_0x2bfd040, L_0x2bfd150, C4<0>, C4<0>; -L_0x2bfd2a0 .delay (20000,20000,20000) L_0x2bfd2a0/d; -v0x2b98f60_0 .net "S", 0 0, L_0x2bfd470; 1 drivers -v0x2b98fe0_0 .alias "in0", 0 0, v0x2b99480_0; -v0x2b99080_0 .alias "in1", 0 0, v0x2b99500_0; -v0x2b99120_0 .net "nS", 0 0, L_0x2bfcf80; 1 drivers -v0x2b991a0_0 .net "out0", 0 0, L_0x2bfd040; 1 drivers -v0x2b99240_0 .net "out1", 0 0, L_0x2bfd150; 1 drivers -v0x2b99320_0 .alias "outfinal", 0 0, v0x2b995b0_0; -S_0x2b98050 .scope generate, "andbits[14]" "andbits[14]" 3 169, 3 169, S_0x2b8b740; - .timescale -9 -12; -P_0x2b98148 .param/l "i" 3 169, +C4<01110>; -S_0x2b981c0 .scope module, "attempt" "AndNand" 3 171, 3 48, S_0x2b98050; - .timescale -9 -12; -L_0x2bf81d0/d .functor NAND 1, L_0x2bfd7c0, L_0x2bfd860, C4<1>, C4<1>; -L_0x2bf81d0 .delay (10000,10000,10000) L_0x2bf81d0/d; -L_0x2bfd9e0/d .functor NOT 1, L_0x2bf81d0, C4<0>, C4<0>, C4<0>; -L_0x2bfd9e0 .delay (10000,10000,10000) L_0x2bfd9e0/d; -v0x2b98800_0 .net "A", 0 0, L_0x2bfd7c0; 1 drivers -v0x2b988c0_0 .net "AandB", 0 0, L_0x2bfd9e0; 1 drivers -v0x2b98940_0 .net "AnandB", 0 0, L_0x2bf81d0; 1 drivers -v0x2b989f0_0 .net "AndNandOut", 0 0, L_0x2bfde10; 1 drivers -v0x2b98ad0_0 .net "B", 0 0, L_0x2bfd860; 1 drivers -v0x2b98b50_0 .alias "Command", 2 0, v0x2bc67a0_0; -L_0x2bfdfe0 .part v0x2bc78e0_0, 0, 1; -S_0x2b982b0 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0x2b981c0; - .timescale -9 -12; -L_0x2bfdaf0/d .functor NOT 1, L_0x2bfdfe0, C4<0>, C4<0>, C4<0>; -L_0x2bfdaf0 .delay (10000,10000,10000) L_0x2bfdaf0/d; -L_0x2bfdbb0/d .functor AND 1, L_0x2bfd9e0, L_0x2bfdaf0, C4<1>, C4<1>; -L_0x2bfdbb0 .delay (20000,20000,20000) L_0x2bfdbb0/d; -L_0x2bfdcc0/d .functor AND 1, L_0x2bf81d0, L_0x2bfdfe0, C4<1>, C4<1>; -L_0x2bfdcc0 .delay (20000,20000,20000) L_0x2bfdcc0/d; -L_0x2bfde10/d .functor OR 1, L_0x2bfdbb0, L_0x2bfdcc0, C4<0>, C4<0>; -L_0x2bfde10 .delay (20000,20000,20000) L_0x2bfde10/d; -v0x2b983a0_0 .net "S", 0 0, L_0x2bfdfe0; 1 drivers -v0x2b98420_0 .alias "in0", 0 0, v0x2b988c0_0; -v0x2b984c0_0 .alias "in1", 0 0, v0x2b98940_0; -v0x2b98560_0 .net "nS", 0 0, L_0x2bfdaf0; 1 drivers -v0x2b985e0_0 .net "out0", 0 0, L_0x2bfdbb0; 1 drivers -v0x2b98680_0 .net "out1", 0 0, L_0x2bfdcc0; 1 drivers -v0x2b98760_0 .alias "outfinal", 0 0, v0x2b989f0_0; -S_0x2b97490 .scope generate, "andbits[15]" "andbits[15]" 3 169, 3 169, S_0x2b8b740; - .timescale -9 -12; -P_0x2b97588 .param/l "i" 3 169, +C4<01111>; -S_0x2b97600 .scope module, "attempt" "AndNand" 3 171, 3 48, S_0x2b97490; - .timescale -9 -12; -L_0x2bfe120/d .functor NAND 1, L_0x2bfeb90, L_0x2bfe2c0, C4<1>, C4<1>; -L_0x2bfe120 .delay (10000,10000,10000) L_0x2bfe120/d; -L_0x2bfe470/d .functor NOT 1, L_0x2bfe120, C4<0>, C4<0>, C4<0>; -L_0x2bfe470 .delay (10000,10000,10000) L_0x2bfe470/d; -v0x2b97c40_0 .net "A", 0 0, L_0x2bfeb90; 1 drivers -v0x2b97d00_0 .net "AandB", 0 0, L_0x2bfe470; 1 drivers -v0x2b97d80_0 .net "AnandB", 0 0, L_0x2bfe120; 1 drivers -v0x2b97e30_0 .net "AndNandOut", 0 0, L_0x2bfe880; 1 drivers -v0x2b97f10_0 .net "B", 0 0, L_0x2bfe2c0; 1 drivers -v0x2b97f90_0 .alias "Command", 2 0, v0x2bc67a0_0; -L_0x2bfea50 .part v0x2bc78e0_0, 0, 1; -S_0x2b976f0 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0x2b97600; - .timescale -9 -12; -L_0x2bfe560/d .functor NOT 1, L_0x2bfea50, C4<0>, C4<0>, C4<0>; -L_0x2bfe560 .delay (10000,10000,10000) L_0x2bfe560/d; -L_0x2bfe620/d .functor AND 1, L_0x2bfe470, L_0x2bfe560, C4<1>, C4<1>; -L_0x2bfe620 .delay (20000,20000,20000) L_0x2bfe620/d; -L_0x2bfe730/d .functor AND 1, L_0x2bfe120, L_0x2bfea50, C4<1>, C4<1>; -L_0x2bfe730 .delay (20000,20000,20000) L_0x2bfe730/d; -L_0x2bfe880/d .functor OR 1, L_0x2bfe620, L_0x2bfe730, C4<0>, C4<0>; -L_0x2bfe880 .delay (20000,20000,20000) L_0x2bfe880/d; -v0x2b977e0_0 .net "S", 0 0, L_0x2bfea50; 1 drivers -v0x2b97860_0 .alias "in0", 0 0, v0x2b97d00_0; -v0x2b97900_0 .alias "in1", 0 0, v0x2b97d80_0; -v0x2b979a0_0 .net "nS", 0 0, L_0x2bfe560; 1 drivers -v0x2b97a20_0 .net "out0", 0 0, L_0x2bfe620; 1 drivers -v0x2b97ac0_0 .net "out1", 0 0, L_0x2bfe730; 1 drivers -v0x2b97ba0_0 .alias "outfinal", 0 0, v0x2b97e30_0; -S_0x2b968d0 .scope generate, "andbits[16]" "andbits[16]" 3 169, 3 169, S_0x2b8b740; - .timescale -9 -12; -P_0x2b969c8 .param/l "i" 3 169, +C4<010000>; -S_0x2b96a40 .scope module, "attempt" "AndNand" 3 171, 3 48, S_0x2b968d0; - .timescale -9 -12; -L_0x2bfe3b0/d .functor NAND 1, L_0x2bfec30, L_0x2bfecd0, C4<1>, C4<1>; -L_0x2bfe3b0 .delay (10000,10000,10000) L_0x2bfe3b0/d; -L_0x2bfeea0/d .functor NOT 1, L_0x2bfe3b0, C4<0>, C4<0>, C4<0>; -L_0x2bfeea0 .delay (10000,10000,10000) L_0x2bfeea0/d; -v0x2b97080_0 .net "A", 0 0, L_0x2bfec30; 1 drivers -v0x2b97140_0 .net "AandB", 0 0, L_0x2bfeea0; 1 drivers -v0x2b971c0_0 .net "AnandB", 0 0, L_0x2bfe3b0; 1 drivers -v0x2b97270_0 .net "AndNandOut", 0 0, L_0x2bff2f0; 1 drivers -v0x2b97350_0 .net "B", 0 0, L_0x2bfecd0; 1 drivers -v0x2b973d0_0 .alias "Command", 2 0, v0x2bc67a0_0; -L_0x2bff4c0 .part v0x2bc78e0_0, 0, 1; -S_0x2b96b30 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0x2b96a40; - .timescale -9 -12; -L_0x2bfefd0/d .functor NOT 1, L_0x2bff4c0, C4<0>, C4<0>, C4<0>; -L_0x2bfefd0 .delay (10000,10000,10000) L_0x2bfefd0/d; -L_0x2bff090/d .functor AND 1, L_0x2bfeea0, L_0x2bfefd0, C4<1>, C4<1>; -L_0x2bff090 .delay (20000,20000,20000) L_0x2bff090/d; -L_0x2bff1a0/d .functor AND 1, L_0x2bfe3b0, L_0x2bff4c0, C4<1>, C4<1>; -L_0x2bff1a0 .delay (20000,20000,20000) L_0x2bff1a0/d; -L_0x2bff2f0/d .functor OR 1, L_0x2bff090, L_0x2bff1a0, C4<0>, C4<0>; -L_0x2bff2f0 .delay (20000,20000,20000) L_0x2bff2f0/d; -v0x2b96c20_0 .net "S", 0 0, L_0x2bff4c0; 1 drivers -v0x2b96ca0_0 .alias "in0", 0 0, v0x2b97140_0; -v0x2b96d40_0 .alias "in1", 0 0, v0x2b971c0_0; -v0x2b96de0_0 .net "nS", 0 0, L_0x2bfefd0; 1 drivers -v0x2b96e60_0 .net "out0", 0 0, L_0x2bff090; 1 drivers -v0x2b96f00_0 .net "out1", 0 0, L_0x2bff1a0; 1 drivers -v0x2b96fe0_0 .alias "outfinal", 0 0, v0x2b97270_0; -S_0x2b95d10 .scope generate, "andbits[17]" "andbits[17]" 3 169, 3 169, S_0x2b8b740; - .timescale -9 -12; -P_0x2b95e08 .param/l "i" 3 169, +C4<010001>; -S_0x2b95e80 .scope module, "attempt" "AndNand" 3 171, 3 48, S_0x2b95d10; - .timescale -9 -12; -L_0x2bff600/d .functor NAND 1, L_0x2c00080, L_0x2bff7d0, C4<1>, C4<1>; -L_0x2bff600 .delay (10000,10000,10000) L_0x2bff600/d; -L_0x2bff960/d .functor NOT 1, L_0x2bff600, C4<0>, C4<0>, C4<0>; -L_0x2bff960 .delay (10000,10000,10000) L_0x2bff960/d; -v0x2b964c0_0 .net "A", 0 0, L_0x2c00080; 1 drivers -v0x2b96580_0 .net "AandB", 0 0, L_0x2bff960; 1 drivers -v0x2b96600_0 .net "AnandB", 0 0, L_0x2bff600; 1 drivers -v0x2b966b0_0 .net "AndNandOut", 0 0, L_0x2bffd70; 1 drivers -v0x2b96790_0 .net "B", 0 0, L_0x2bff7d0; 1 drivers -v0x2b96810_0 .alias "Command", 2 0, v0x2bc67a0_0; -L_0x2bfff40 .part v0x2bc78e0_0, 0, 1; -S_0x2b95f70 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0x2b95e80; - .timescale -9 -12; -L_0x2bffa50/d .functor NOT 1, L_0x2bfff40, C4<0>, C4<0>, C4<0>; -L_0x2bffa50 .delay (10000,10000,10000) L_0x2bffa50/d; -L_0x2bffb10/d .functor AND 1, L_0x2bff960, L_0x2bffa50, C4<1>, C4<1>; -L_0x2bffb10 .delay (20000,20000,20000) L_0x2bffb10/d; -L_0x2bffc20/d .functor AND 1, L_0x2bff600, L_0x2bfff40, C4<1>, C4<1>; -L_0x2bffc20 .delay (20000,20000,20000) L_0x2bffc20/d; -L_0x2bffd70/d .functor OR 1, L_0x2bffb10, L_0x2bffc20, C4<0>, C4<0>; -L_0x2bffd70 .delay (20000,20000,20000) L_0x2bffd70/d; -v0x2b96060_0 .net "S", 0 0, L_0x2bfff40; 1 drivers -v0x2b960e0_0 .alias "in0", 0 0, v0x2b96580_0; -v0x2b96180_0 .alias "in1", 0 0, v0x2b96600_0; -v0x2b96220_0 .net "nS", 0 0, L_0x2bffa50; 1 drivers -v0x2b962a0_0 .net "out0", 0 0, L_0x2bffb10; 1 drivers -v0x2b96340_0 .net "out1", 0 0, L_0x2bffc20; 1 drivers -v0x2b96420_0 .alias "outfinal", 0 0, v0x2b966b0_0; -S_0x2b95150 .scope generate, "andbits[18]" "andbits[18]" 3 169, 3 169, S_0x2b8b740; - .timescale -9 -12; -P_0x2b95248 .param/l "i" 3 169, +C4<010010>; -S_0x2b952c0 .scope module, "attempt" "AndNand" 3 171, 3 48, S_0x2b95150; - .timescale -9 -12; -L_0x2bff8c0/d .functor NAND 1, L_0x2c00120, L_0x2c001c0, C4<1>, C4<1>; -L_0x2bff8c0 .delay (10000,10000,10000) L_0x2bff8c0/d; -L_0x2c003a0/d .functor NOT 1, L_0x2bff8c0, C4<0>, C4<0>, C4<0>; -L_0x2c003a0 .delay (10000,10000,10000) L_0x2c003a0/d; -v0x2b95900_0 .net "A", 0 0, L_0x2c00120; 1 drivers -v0x2b959c0_0 .net "AandB", 0 0, L_0x2c003a0; 1 drivers -v0x2b95a40_0 .net "AnandB", 0 0, L_0x2bff8c0; 1 drivers -v0x2b95af0_0 .net "AndNandOut", 0 0, L_0x2c007d0; 1 drivers -v0x2b95bd0_0 .net "B", 0 0, L_0x2c001c0; 1 drivers -v0x2b95c50_0 .alias "Command", 2 0, v0x2bc67a0_0; -L_0x2c009a0 .part v0x2bc78e0_0, 0, 1; -S_0x2b953b0 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0x2b952c0; - .timescale -9 -12; -L_0x2c004b0/d .functor NOT 1, L_0x2c009a0, C4<0>, C4<0>, C4<0>; -L_0x2c004b0 .delay (10000,10000,10000) L_0x2c004b0/d; -L_0x2c00570/d .functor AND 1, L_0x2c003a0, L_0x2c004b0, C4<1>, C4<1>; -L_0x2c00570 .delay (20000,20000,20000) L_0x2c00570/d; -L_0x2c00680/d .functor AND 1, L_0x2bff8c0, L_0x2c009a0, C4<1>, C4<1>; -L_0x2c00680 .delay (20000,20000,20000) L_0x2c00680/d; -L_0x2c007d0/d .functor OR 1, L_0x2c00570, L_0x2c00680, C4<0>, C4<0>; -L_0x2c007d0 .delay (20000,20000,20000) L_0x2c007d0/d; -v0x2b954a0_0 .net "S", 0 0, L_0x2c009a0; 1 drivers -v0x2b95520_0 .alias "in0", 0 0, v0x2b959c0_0; -v0x2b955c0_0 .alias "in1", 0 0, v0x2b95a40_0; -v0x2b95660_0 .net "nS", 0 0, L_0x2c004b0; 1 drivers -v0x2b956e0_0 .net "out0", 0 0, L_0x2c00570; 1 drivers -v0x2b95780_0 .net "out1", 0 0, L_0x2c00680; 1 drivers -v0x2b95860_0 .alias "outfinal", 0 0, v0x2b95af0_0; -S_0x2b94590 .scope generate, "andbits[19]" "andbits[19]" 3 169, 3 169, S_0x2b8b740; - .timescale -9 -12; -P_0x2b94688 .param/l "i" 3 169, +C4<010011>; -S_0x2b94700 .scope module, "attempt" "AndNand" 3 171, 3 48, S_0x2b94590; - .timescale -9 -12; -L_0x2c00ca0/d .functor NAND 1, L_0x2c01560, L_0x2c00ae0, C4<1>, C4<1>; -L_0x2c00ca0 .delay (10000,10000,10000) L_0x2c00ca0/d; -L_0x2c00e00/d .functor NOT 1, L_0x2c00ca0, C4<0>, C4<0>, C4<0>; -L_0x2c00e00 .delay (10000,10000,10000) L_0x2c00e00/d; -v0x2b94d40_0 .net "A", 0 0, L_0x2c01560; 1 drivers -v0x2b94e00_0 .net "AandB", 0 0, L_0x2c00e00; 1 drivers -v0x2b94e80_0 .net "AnandB", 0 0, L_0x2c00ca0; 1 drivers -v0x2b94f30_0 .net "AndNandOut", 0 0, L_0x2c01250; 1 drivers -v0x2b95010_0 .net "B", 0 0, L_0x2c00ae0; 1 drivers -v0x2b95090_0 .alias "Command", 2 0, v0x2bc67a0_0; -L_0x2c01420 .part v0x2bc78e0_0, 0, 1; -S_0x2b947f0 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0x2b94700; - .timescale -9 -12; -L_0x2c00f30/d .functor NOT 1, L_0x2c01420, C4<0>, C4<0>, C4<0>; -L_0x2c00f30 .delay (10000,10000,10000) L_0x2c00f30/d; -L_0x2c00ff0/d .functor AND 1, L_0x2c00e00, L_0x2c00f30, C4<1>, C4<1>; -L_0x2c00ff0 .delay (20000,20000,20000) L_0x2c00ff0/d; -L_0x2c01100/d .functor AND 1, L_0x2c00ca0, L_0x2c01420, C4<1>, C4<1>; -L_0x2c01100 .delay (20000,20000,20000) L_0x2c01100/d; -L_0x2c01250/d .functor OR 1, L_0x2c00ff0, L_0x2c01100, C4<0>, C4<0>; -L_0x2c01250 .delay (20000,20000,20000) L_0x2c01250/d; -v0x2b948e0_0 .net "S", 0 0, L_0x2c01420; 1 drivers -v0x2b94960_0 .alias "in0", 0 0, v0x2b94e00_0; -v0x2b94a00_0 .alias "in1", 0 0, v0x2b94e80_0; -v0x2b94aa0_0 .net "nS", 0 0, L_0x2c00f30; 1 drivers -v0x2b94b20_0 .net "out0", 0 0, L_0x2c00ff0; 1 drivers -v0x2b94bc0_0 .net "out1", 0 0, L_0x2c01100; 1 drivers -v0x2b94ca0_0 .alias "outfinal", 0 0, v0x2b94f30_0; -S_0x2b939d0 .scope generate, "andbits[20]" "andbits[20]" 3 169, 3 169, S_0x2b8b740; - .timescale -9 -12; -P_0x2b93ac8 .param/l "i" 3 169, +C4<010100>; -S_0x2b93b40 .scope module, "attempt" "AndNand" 3 171, 3 48, S_0x2b939d0; - .timescale -9 -12; -L_0x2c00bd0/d .functor NAND 1, L_0x2c01600, L_0x2c016a0, C4<1>, C4<1>; -L_0x2c00bd0 .delay (10000,10000,10000) L_0x2c00bd0/d; -L_0x2c01860/d .functor NOT 1, L_0x2c00bd0, C4<0>, C4<0>, C4<0>; -L_0x2c01860 .delay (10000,10000,10000) L_0x2c01860/d; -v0x2b94180_0 .net "A", 0 0, L_0x2c01600; 1 drivers -v0x2b94240_0 .net "AandB", 0 0, L_0x2c01860; 1 drivers -v0x2b942c0_0 .net "AnandB", 0 0, L_0x2c00bd0; 1 drivers -v0x2b94370_0 .net "AndNandOut", 0 0, L_0x2c01cb0; 1 drivers -v0x2b94450_0 .net "B", 0 0, L_0x2c016a0; 1 drivers -v0x2b944d0_0 .alias "Command", 2 0, v0x2bc67a0_0; -L_0x2c01e80 .part v0x2bc78e0_0, 0, 1; -S_0x2b93c30 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0x2b93b40; - .timescale -9 -12; -L_0x2c01990/d .functor NOT 1, L_0x2c01e80, C4<0>, C4<0>, C4<0>; -L_0x2c01990 .delay (10000,10000,10000) L_0x2c01990/d; -L_0x2c01a50/d .functor AND 1, L_0x2c01860, L_0x2c01990, C4<1>, C4<1>; -L_0x2c01a50 .delay (20000,20000,20000) L_0x2c01a50/d; -L_0x2c01b60/d .functor AND 1, L_0x2c00bd0, L_0x2c01e80, C4<1>, C4<1>; -L_0x2c01b60 .delay (20000,20000,20000) L_0x2c01b60/d; -L_0x2c01cb0/d .functor OR 1, L_0x2c01a50, L_0x2c01b60, C4<0>, C4<0>; -L_0x2c01cb0 .delay (20000,20000,20000) L_0x2c01cb0/d; -v0x2b93d20_0 .net "S", 0 0, L_0x2c01e80; 1 drivers -v0x2b93da0_0 .alias "in0", 0 0, v0x2b94240_0; -v0x2b93e40_0 .alias "in1", 0 0, v0x2b942c0_0; -v0x2b93ee0_0 .net "nS", 0 0, L_0x2c01990; 1 drivers -v0x2b93f60_0 .net "out0", 0 0, L_0x2c01a50; 1 drivers -v0x2b94000_0 .net "out1", 0 0, L_0x2c01b60; 1 drivers -v0x2b940e0_0 .alias "outfinal", 0 0, v0x2b94370_0; -S_0x2b92e10 .scope generate, "andbits[21]" "andbits[21]" 3 169, 3 169, S_0x2b8b740; - .timescale -9 -12; -P_0x2b92f08 .param/l "i" 3 169, +C4<010101>; -S_0x2b92f80 .scope module, "attempt" "AndNand" 3 171, 3 48, S_0x2b92e10; - .timescale -9 -12; -L_0x2c021b0/d .functor NAND 1, L_0x2c02a30, L_0x2c01fc0, C4<1>, C4<1>; -L_0x2c021b0 .delay (10000,10000,10000) L_0x2c021b0/d; -L_0x2c022f0/d .functor NOT 1, L_0x2c021b0, C4<0>, C4<0>, C4<0>; -L_0x2c022f0 .delay (10000,10000,10000) L_0x2c022f0/d; -v0x2b935c0_0 .net "A", 0 0, L_0x2c02a30; 1 drivers -v0x2b93680_0 .net "AandB", 0 0, L_0x2c022f0; 1 drivers -v0x2b93700_0 .net "AnandB", 0 0, L_0x2c021b0; 1 drivers -v0x2b937b0_0 .net "AndNandOut", 0 0, L_0x2c02720; 1 drivers -v0x2b93890_0 .net "B", 0 0, L_0x2c01fc0; 1 drivers -v0x2b93910_0 .alias "Command", 2 0, v0x2bc67a0_0; -L_0x2c028f0 .part v0x2bc78e0_0, 0, 1; -S_0x2b93070 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0x2b92f80; - .timescale -9 -12; -L_0x2c02400/d .functor NOT 1, L_0x2c028f0, C4<0>, C4<0>, C4<0>; -L_0x2c02400 .delay (10000,10000,10000) L_0x2c02400/d; -L_0x2c024c0/d .functor AND 1, L_0x2c022f0, L_0x2c02400, C4<1>, C4<1>; -L_0x2c024c0 .delay (20000,20000,20000) L_0x2c024c0/d; -L_0x2c025d0/d .functor AND 1, L_0x2c021b0, L_0x2c028f0, C4<1>, C4<1>; -L_0x2c025d0 .delay (20000,20000,20000) L_0x2c025d0/d; -L_0x2c02720/d .functor OR 1, L_0x2c024c0, L_0x2c025d0, C4<0>, C4<0>; -L_0x2c02720 .delay (20000,20000,20000) L_0x2c02720/d; -v0x2b93160_0 .net "S", 0 0, L_0x2c028f0; 1 drivers -v0x2b931e0_0 .alias "in0", 0 0, v0x2b93680_0; -v0x2b93280_0 .alias "in1", 0 0, v0x2b93700_0; -v0x2b93320_0 .net "nS", 0 0, L_0x2c02400; 1 drivers -v0x2b933a0_0 .net "out0", 0 0, L_0x2c024c0; 1 drivers -v0x2b93440_0 .net "out1", 0 0, L_0x2c025d0; 1 drivers -v0x2b93520_0 .alias "outfinal", 0 0, v0x2b937b0_0; -S_0x2b92250 .scope generate, "andbits[22]" "andbits[22]" 3 169, 3 169, S_0x2b8b740; - .timescale -9 -12; -P_0x2b92348 .param/l "i" 3 169, +C4<010110>; -S_0x2b923c0 .scope module, "attempt" "AndNand" 3 171, 3 48, S_0x2b92250; - .timescale -9 -12; -L_0x2c020b0/d .functor NAND 1, L_0x2c02ad0, L_0x2c02b70, C4<1>, C4<1>; -L_0x2c020b0 .delay (10000,10000,10000) L_0x2c020b0/d; -L_0x2c02d60/d .functor NOT 1, L_0x2c020b0, C4<0>, C4<0>, C4<0>; -L_0x2c02d60 .delay (10000,10000,10000) L_0x2c02d60/d; -v0x2b92a00_0 .net "A", 0 0, L_0x2c02ad0; 1 drivers -v0x2b92ac0_0 .net "AandB", 0 0, L_0x2c02d60; 1 drivers -v0x2b92b40_0 .net "AnandB", 0 0, L_0x2c020b0; 1 drivers -v0x2b92bf0_0 .net "AndNandOut", 0 0, L_0x2c03190; 1 drivers -v0x2b92cd0_0 .net "B", 0 0, L_0x2c02b70; 1 drivers -v0x2b92d50_0 .alias "Command", 2 0, v0x2bc67a0_0; -L_0x2c03360 .part v0x2bc78e0_0, 0, 1; -S_0x2b924b0 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0x2b923c0; - .timescale -9 -12; -L_0x2c02e70/d .functor NOT 1, L_0x2c03360, C4<0>, C4<0>, C4<0>; -L_0x2c02e70 .delay (10000,10000,10000) L_0x2c02e70/d; -L_0x2c02f30/d .functor AND 1, L_0x2c02d60, L_0x2c02e70, C4<1>, C4<1>; -L_0x2c02f30 .delay (20000,20000,20000) L_0x2c02f30/d; -L_0x2c03040/d .functor AND 1, L_0x2c020b0, L_0x2c03360, C4<1>, C4<1>; -L_0x2c03040 .delay (20000,20000,20000) L_0x2c03040/d; -L_0x2c03190/d .functor OR 1, L_0x2c02f30, L_0x2c03040, C4<0>, C4<0>; -L_0x2c03190 .delay (20000,20000,20000) L_0x2c03190/d; -v0x2b925a0_0 .net "S", 0 0, L_0x2c03360; 1 drivers -v0x2b92620_0 .alias "in0", 0 0, v0x2b92ac0_0; -v0x2b926c0_0 .alias "in1", 0 0, v0x2b92b40_0; -v0x2b92760_0 .net "nS", 0 0, L_0x2c02e70; 1 drivers -v0x2b927e0_0 .net "out0", 0 0, L_0x2c02f30; 1 drivers -v0x2b92880_0 .net "out1", 0 0, L_0x2c03040; 1 drivers -v0x2b92960_0 .alias "outfinal", 0 0, v0x2b92bf0_0; -S_0x2b91690 .scope generate, "andbits[23]" "andbits[23]" 3 169, 3 169, S_0x2b8b740; - .timescale -9 -12; -P_0x2b91788 .param/l "i" 3 169, +C4<010111>; -S_0x2b91800 .scope module, "attempt" "AndNand" 3 171, 3 48, S_0x2b91690; - .timescale -9 -12; -L_0x2c02c60/d .functor NAND 1, L_0x2c03f20, L_0x2c034a0, C4<1>, C4<1>; -L_0x2c02c60 .delay (10000,10000,10000) L_0x2c02c60/d; -L_0x2c037c0/d .functor NOT 1, L_0x2c02c60, C4<0>, C4<0>, C4<0>; -L_0x2c037c0 .delay (10000,10000,10000) L_0x2c037c0/d; -v0x2b91e40_0 .net "A", 0 0, L_0x2c03f20; 1 drivers -v0x2b91f00_0 .net "AandB", 0 0, L_0x2c037c0; 1 drivers -v0x2b91f80_0 .net "AnandB", 0 0, L_0x2c02c60; 1 drivers -v0x2b92030_0 .net "AndNandOut", 0 0, L_0x2c03c10; 1 drivers -v0x2b92110_0 .net "B", 0 0, L_0x2c034a0; 1 drivers -v0x2b92190_0 .alias "Command", 2 0, v0x2bc67a0_0; -L_0x2c03de0 .part v0x2bc78e0_0, 0, 1; -S_0x2b918f0 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0x2b91800; - .timescale -9 -12; -L_0x2c038f0/d .functor NOT 1, L_0x2c03de0, C4<0>, C4<0>, C4<0>; -L_0x2c038f0 .delay (10000,10000,10000) L_0x2c038f0/d; -L_0x2c039b0/d .functor AND 1, L_0x2c037c0, L_0x2c038f0, C4<1>, C4<1>; -L_0x2c039b0 .delay (20000,20000,20000) L_0x2c039b0/d; -L_0x2c03ac0/d .functor AND 1, L_0x2c02c60, L_0x2c03de0, C4<1>, C4<1>; -L_0x2c03ac0 .delay (20000,20000,20000) L_0x2c03ac0/d; -L_0x2c03c10/d .functor OR 1, L_0x2c039b0, L_0x2c03ac0, C4<0>, C4<0>; -L_0x2c03c10 .delay (20000,20000,20000) L_0x2c03c10/d; -v0x2b919e0_0 .net "S", 0 0, L_0x2c03de0; 1 drivers -v0x2b91a60_0 .alias "in0", 0 0, v0x2b91f00_0; -v0x2b91b00_0 .alias "in1", 0 0, v0x2b91f80_0; -v0x2b91ba0_0 .net "nS", 0 0, L_0x2c038f0; 1 drivers -v0x2b91c20_0 .net "out0", 0 0, L_0x2c039b0; 1 drivers -v0x2b91cc0_0 .net "out1", 0 0, L_0x2c03ac0; 1 drivers -v0x2b91da0_0 .alias "outfinal", 0 0, v0x2b92030_0; -S_0x2b90ad0 .scope generate, "andbits[24]" "andbits[24]" 3 169, 3 169, S_0x2b8b740; - .timescale -9 -12; -P_0x2b90bc8 .param/l "i" 3 169, +C4<011000>; -S_0x2b90c40 .scope module, "attempt" "AndNand" 3 171, 3 48, S_0x2b90ad0; - .timescale -9 -12; -L_0x2c03590/d .functor NAND 1, L_0x2c03fc0, L_0x2c04060, C4<1>, C4<1>; -L_0x2c03590 .delay (10000,10000,10000) L_0x2c03590/d; -L_0x2c04240/d .functor NOT 1, L_0x2c03590, C4<0>, C4<0>, C4<0>; -L_0x2c04240 .delay (10000,10000,10000) L_0x2c04240/d; -v0x2b91280_0 .net "A", 0 0, L_0x2c03fc0; 1 drivers -v0x2b91340_0 .net "AandB", 0 0, L_0x2c04240; 1 drivers -v0x2b913c0_0 .net "AnandB", 0 0, L_0x2c03590; 1 drivers -v0x2b91470_0 .net "AndNandOut", 0 0, L_0x2c04670; 1 drivers -v0x2b91550_0 .net "B", 0 0, L_0x2c04060; 1 drivers -v0x2b915d0_0 .alias "Command", 2 0, v0x2bc67a0_0; -L_0x2c04840 .part v0x2bc78e0_0, 0, 1; -S_0x2b90d30 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0x2b90c40; - .timescale -9 -12; -L_0x2c04350/d .functor NOT 1, L_0x2c04840, C4<0>, C4<0>, C4<0>; -L_0x2c04350 .delay (10000,10000,10000) L_0x2c04350/d; -L_0x2c04410/d .functor AND 1, L_0x2c04240, L_0x2c04350, C4<1>, C4<1>; -L_0x2c04410 .delay (20000,20000,20000) L_0x2c04410/d; -L_0x2c04520/d .functor AND 1, L_0x2c03590, L_0x2c04840, C4<1>, C4<1>; -L_0x2c04520 .delay (20000,20000,20000) L_0x2c04520/d; -L_0x2c04670/d .functor OR 1, L_0x2c04410, L_0x2c04520, C4<0>, C4<0>; -L_0x2c04670 .delay (20000,20000,20000) L_0x2c04670/d; -v0x2b90e20_0 .net "S", 0 0, L_0x2c04840; 1 drivers -v0x2b90ea0_0 .alias "in0", 0 0, v0x2b91340_0; -v0x2b90f40_0 .alias "in1", 0 0, v0x2b913c0_0; -v0x2b90fe0_0 .net "nS", 0 0, L_0x2c04350; 1 drivers -v0x2b91060_0 .net "out0", 0 0, L_0x2c04410; 1 drivers -v0x2b91100_0 .net "out1", 0 0, L_0x2c04520; 1 drivers -v0x2b911e0_0 .alias "outfinal", 0 0, v0x2b91470_0; -S_0x2b8ff10 .scope generate, "andbits[25]" "andbits[25]" 3 169, 3 169, S_0x2b8b740; - .timescale -9 -12; -P_0x2b90008 .param/l "i" 3 169, +C4<011001>; -S_0x2b90080 .scope module, "attempt" "AndNand" 3 171, 3 48, S_0x2b8ff10; - .timescale -9 -12; -L_0x2c04150/d .functor NAND 1, L_0x2c053f0, L_0x2bea340, C4<1>, C4<1>; -L_0x2c04150 .delay (10000,10000,10000) L_0x2c04150/d; -L_0x2c04cb0/d .functor NOT 1, L_0x2c04150, C4<0>, C4<0>, C4<0>; -L_0x2c04cb0 .delay (10000,10000,10000) L_0x2c04cb0/d; -v0x2b906c0_0 .net "A", 0 0, L_0x2c053f0; 1 drivers -v0x2b90780_0 .net "AandB", 0 0, L_0x2c04cb0; 1 drivers -v0x2b90800_0 .net "AnandB", 0 0, L_0x2c04150; 1 drivers -v0x2b908b0_0 .net "AndNandOut", 0 0, L_0x2c050e0; 1 drivers -v0x2b90990_0 .net "B", 0 0, L_0x2bea340; 1 drivers -v0x2b90a10_0 .alias "Command", 2 0, v0x2bc67a0_0; -L_0x2c052b0 .part v0x2bc78e0_0, 0, 1; -S_0x2b90170 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0x2b90080; - .timescale -9 -12; -L_0x2c04dc0/d .functor NOT 1, L_0x2c052b0, C4<0>, C4<0>, C4<0>; -L_0x2c04dc0 .delay (10000,10000,10000) L_0x2c04dc0/d; -L_0x2c04e80/d .functor AND 1, L_0x2c04cb0, L_0x2c04dc0, C4<1>, C4<1>; -L_0x2c04e80 .delay (20000,20000,20000) L_0x2c04e80/d; -L_0x2c04f90/d .functor AND 1, L_0x2c04150, L_0x2c052b0, C4<1>, C4<1>; -L_0x2c04f90 .delay (20000,20000,20000) L_0x2c04f90/d; -L_0x2c050e0/d .functor OR 1, L_0x2c04e80, L_0x2c04f90, C4<0>, C4<0>; -L_0x2c050e0 .delay (20000,20000,20000) L_0x2c050e0/d; -v0x2b90260_0 .net "S", 0 0, L_0x2c052b0; 1 drivers -v0x2b902e0_0 .alias "in0", 0 0, v0x2b90780_0; -v0x2b90380_0 .alias "in1", 0 0, v0x2b90800_0; -v0x2b90420_0 .net "nS", 0 0, L_0x2c04dc0; 1 drivers -v0x2b904a0_0 .net "out0", 0 0, L_0x2c04e80; 1 drivers -v0x2b90540_0 .net "out1", 0 0, L_0x2c04f90; 1 drivers -v0x2b90620_0 .alias "outfinal", 0 0, v0x2b908b0_0; -S_0x2b8f350 .scope generate, "andbits[26]" "andbits[26]" 3 169, 3 169, S_0x2b8b740; - .timescale -9 -12; -P_0x2b8f448 .param/l "i" 3 169, +C4<011010>; -S_0x2b8f4c0 .scope module, "attempt" "AndNand" 3 171, 3 48, S_0x2b8f350; - .timescale -9 -12; -L_0x2bf7860/d .functor NAND 1, L_0x2bea0e0, L_0x2bea180, C4<1>, C4<1>; -L_0x2bf7860 .delay (10000,10000,10000) L_0x2bf7860/d; -L_0x2c049d0/d .functor NOT 1, L_0x2bf7860, C4<0>, C4<0>, C4<0>; -L_0x2c049d0 .delay (10000,10000,10000) L_0x2c049d0/d; -v0x2b8fb00_0 .net "A", 0 0, L_0x2bea0e0; 1 drivers -v0x2b8fbc0_0 .net "AandB", 0 0, L_0x2c049d0; 1 drivers -v0x2b8fc40_0 .net "AnandB", 0 0, L_0x2bf7860; 1 drivers -v0x2b8fcf0_0 .net "AndNandOut", 0 0, L_0x2be9ea0; 1 drivers -v0x2b8fdd0_0 .net "B", 0 0, L_0x2bea180; 1 drivers -v0x2b8fe50_0 .alias "Command", 2 0, v0x2bc67a0_0; -L_0x2c064b0 .part v0x2bc78e0_0, 0, 1; -S_0x2b8f5b0 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0x2b8f4c0; - .timescale -9 -12; -L_0x2c04b00/d .functor NOT 1, L_0x2c064b0, C4<0>, C4<0>, C4<0>; -L_0x2c04b00 .delay (10000,10000,10000) L_0x2c04b00/d; -L_0x2be9c40/d .functor AND 1, L_0x2c049d0, L_0x2c04b00, C4<1>, C4<1>; -L_0x2be9c40 .delay (20000,20000,20000) L_0x2be9c40/d; -L_0x2be9d50/d .functor AND 1, L_0x2bf7860, L_0x2c064b0, C4<1>, C4<1>; -L_0x2be9d50 .delay (20000,20000,20000) L_0x2be9d50/d; -L_0x2be9ea0/d .functor OR 1, L_0x2be9c40, L_0x2be9d50, C4<0>, C4<0>; -L_0x2be9ea0 .delay (20000,20000,20000) L_0x2be9ea0/d; -v0x2b8f6a0_0 .net "S", 0 0, L_0x2c064b0; 1 drivers -v0x2b8f720_0 .alias "in0", 0 0, v0x2b8fbc0_0; -v0x2b8f7c0_0 .alias "in1", 0 0, v0x2b8fc40_0; -v0x2b8f860_0 .net "nS", 0 0, L_0x2c04b00; 1 drivers -v0x2b8f8e0_0 .net "out0", 0 0, L_0x2be9c40; 1 drivers -v0x2b8f980_0 .net "out1", 0 0, L_0x2be9d50; 1 drivers -v0x2b8fa60_0 .alias "outfinal", 0 0, v0x2b8fcf0_0; -S_0x2b8e790 .scope generate, "andbits[27]" "andbits[27]" 3 169, 3 169, S_0x2b8b740; - .timescale -9 -12; -P_0x2b8e888 .param/l "i" 3 169, +C4<011011>; -S_0x2b8e900 .scope module, "attempt" "AndNand" 3 171, 3 48, S_0x2b8e790; - .timescale -9 -12; -L_0x2bea270/d .functor NAND 1, L_0x2c06f80, L_0x2c065f0, C4<1>, C4<1>; -L_0x2bea270 .delay (10000,10000,10000) L_0x2bea270/d; -L_0x2c06900/d .functor NOT 1, L_0x2bea270, C4<0>, C4<0>, C4<0>; -L_0x2c06900 .delay (10000,10000,10000) L_0x2c06900/d; -v0x2b8ef40_0 .net "A", 0 0, L_0x2c06f80; 1 drivers -v0x2b8f000_0 .net "AandB", 0 0, L_0x2c06900; 1 drivers -v0x2b8f080_0 .net "AnandB", 0 0, L_0x2bea270; 1 drivers -v0x2b8f130_0 .net "AndNandOut", 0 0, L_0x2c06cb0; 1 drivers -v0x2b8f210_0 .net "B", 0 0, L_0x2c065f0; 1 drivers -v0x2b8f290_0 .alias "Command", 2 0, v0x2bc67a0_0; -L_0x2c06e40 .part v0x2bc78e0_0, 0, 1; -S_0x2b8e9f0 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0x2b8e900; - .timescale -9 -12; -L_0x2c069f0/d .functor NOT 1, L_0x2c06e40, C4<0>, C4<0>, C4<0>; -L_0x2c069f0 .delay (10000,10000,10000) L_0x2c069f0/d; -L_0x2c06a90/d .functor AND 1, L_0x2c06900, L_0x2c069f0, C4<1>, C4<1>; -L_0x2c06a90 .delay (20000,20000,20000) L_0x2c06a90/d; -L_0x2c06b80/d .functor AND 1, L_0x2bea270, L_0x2c06e40, C4<1>, C4<1>; -L_0x2c06b80 .delay (20000,20000,20000) L_0x2c06b80/d; -L_0x2c06cb0/d .functor OR 1, L_0x2c06a90, L_0x2c06b80, C4<0>, C4<0>; -L_0x2c06cb0 .delay (20000,20000,20000) L_0x2c06cb0/d; -v0x2b8eae0_0 .net "S", 0 0, L_0x2c06e40; 1 drivers -v0x2b8eb60_0 .alias "in0", 0 0, v0x2b8f000_0; -v0x2b8ec00_0 .alias "in1", 0 0, v0x2b8f080_0; -v0x2b8eca0_0 .net "nS", 0 0, L_0x2c069f0; 1 drivers -v0x2b8ed20_0 .net "out0", 0 0, L_0x2c06a90; 1 drivers -v0x2b8edc0_0 .net "out1", 0 0, L_0x2c06b80; 1 drivers -v0x2b8eea0_0 .alias "outfinal", 0 0, v0x2b8f130_0; -S_0x2b8dbd0 .scope generate, "andbits[28]" "andbits[28]" 3 169, 3 169, S_0x2b8b740; - .timescale -9 -12; -P_0x2b8dcc8 .param/l "i" 3 169, +C4<011100>; -S_0x2b8dd40 .scope module, "attempt" "AndNand" 3 171, 3 48, S_0x2b8dbd0; - .timescale -9 -12; -L_0x2c066e0/d .functor NAND 1, L_0x2c07020, L_0x2c070c0, C4<1>, C4<1>; -L_0x2c066e0 .delay (10000,10000,10000) L_0x2c066e0/d; -L_0x2c072b0/d .functor NOT 1, L_0x2c066e0, C4<0>, C4<0>, C4<0>; -L_0x2c072b0 .delay (10000,10000,10000) L_0x2c072b0/d; -v0x2b8e380_0 .net "A", 0 0, L_0x2c07020; 1 drivers -v0x2b8e440_0 .net "AandB", 0 0, L_0x2c072b0; 1 drivers -v0x2b8e4c0_0 .net "AnandB", 0 0, L_0x2c066e0; 1 drivers -v0x2b8e570_0 .net "AndNandOut", 0 0, L_0x2c07660; 1 drivers -v0x2b8e650_0 .net "B", 0 0, L_0x2c070c0; 1 drivers -v0x2b8e6d0_0 .alias "Command", 2 0, v0x2bc67a0_0; -L_0x2c077f0 .part v0x2bc78e0_0, 0, 1; -S_0x2b8de30 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0x2b8dd40; - .timescale -9 -12; -L_0x2c073a0/d .functor NOT 1, L_0x2c077f0, C4<0>, C4<0>, C4<0>; -L_0x2c073a0 .delay (10000,10000,10000) L_0x2c073a0/d; -L_0x2c07440/d .functor AND 1, L_0x2c072b0, L_0x2c073a0, C4<1>, C4<1>; -L_0x2c07440 .delay (20000,20000,20000) L_0x2c07440/d; -L_0x2c07530/d .functor AND 1, L_0x2c066e0, L_0x2c077f0, C4<1>, C4<1>; -L_0x2c07530 .delay (20000,20000,20000) L_0x2c07530/d; -L_0x2c07660/d .functor OR 1, L_0x2c07440, L_0x2c07530, C4<0>, C4<0>; -L_0x2c07660 .delay (20000,20000,20000) L_0x2c07660/d; -v0x2b8df20_0 .net "S", 0 0, L_0x2c077f0; 1 drivers -v0x2b8dfa0_0 .alias "in0", 0 0, v0x2b8e440_0; -v0x2b8e040_0 .alias "in1", 0 0, v0x2b8e4c0_0; -v0x2b8e0e0_0 .net "nS", 0 0, L_0x2c073a0; 1 drivers -v0x2b8e160_0 .net "out0", 0 0, L_0x2c07440; 1 drivers -v0x2b8e200_0 .net "out1", 0 0, L_0x2c07530; 1 drivers -v0x2b8e2e0_0 .alias "outfinal", 0 0, v0x2b8e570_0; -S_0x2b8d010 .scope generate, "andbits[29]" "andbits[29]" 3 169, 3 169, S_0x2b8b740; - .timescale -9 -12; -P_0x2b8d108 .param/l "i" 3 169, +C4<011101>; -S_0x2b8d180 .scope module, "attempt" "AndNand" 3 171, 3 48, S_0x2b8d010; - .timescale -9 -12; -L_0x2c071b0/d .functor NAND 1, L_0x2bfd5b0, L_0x2bfd650, C4<1>, C4<1>; -L_0x2c071b0 .delay (10000,10000,10000) L_0x2c071b0/d; -L_0x2c07c70/d .functor NOT 1, L_0x2c071b0, C4<0>, C4<0>, C4<0>; -L_0x2c07c70 .delay (10000,10000,10000) L_0x2c07c70/d; -v0x2b8d7c0_0 .net "A", 0 0, L_0x2bfd5b0; 1 drivers -v0x2b8d880_0 .net "AandB", 0 0, L_0x2c07c70; 1 drivers -v0x2b8d900_0 .net "AnandB", 0 0, L_0x2c071b0; 1 drivers -v0x2b8d9b0_0 .net "AndNandOut", 0 0, L_0x2c08020; 1 drivers -v0x2b8da90_0 .net "B", 0 0, L_0x2bfd650; 1 drivers -v0x2b8db10_0 .alias "Command", 2 0, v0x2bc67a0_0; -L_0x2c081b0 .part v0x2bc78e0_0, 0, 1; -S_0x2b8d270 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0x2b8d180; - .timescale -9 -12; -L_0x2c07d60/d .functor NOT 1, L_0x2c081b0, C4<0>, C4<0>, C4<0>; -L_0x2c07d60 .delay (10000,10000,10000) L_0x2c07d60/d; -L_0x2c07e00/d .functor AND 1, L_0x2c07c70, L_0x2c07d60, C4<1>, C4<1>; -L_0x2c07e00 .delay (20000,20000,20000) L_0x2c07e00/d; -L_0x2c07ef0/d .functor AND 1, L_0x2c071b0, L_0x2c081b0, C4<1>, C4<1>; -L_0x2c07ef0 .delay (20000,20000,20000) L_0x2c07ef0/d; -L_0x2c08020/d .functor OR 1, L_0x2c07e00, L_0x2c07ef0, C4<0>, C4<0>; -L_0x2c08020 .delay (20000,20000,20000) L_0x2c08020/d; -v0x2b8d360_0 .net "S", 0 0, L_0x2c081b0; 1 drivers -v0x2b8d3e0_0 .alias "in0", 0 0, v0x2b8d880_0; -v0x2b8d480_0 .alias "in1", 0 0, v0x2b8d900_0; -v0x2b8d520_0 .net "nS", 0 0, L_0x2c07d60; 1 drivers -v0x2b8d5a0_0 .net "out0", 0 0, L_0x2c07e00; 1 drivers -v0x2b8d640_0 .net "out1", 0 0, L_0x2c07ef0; 1 drivers -v0x2b8d720_0 .alias "outfinal", 0 0, v0x2b8d9b0_0; -S_0x2b8c450 .scope generate, "andbits[30]" "andbits[30]" 3 169, 3 169, S_0x2b8b740; - .timescale -9 -12; -P_0x2b8c548 .param/l "i" 3 169, +C4<011110>; -S_0x2b8c5c0 .scope module, "attempt" "AndNand" 3 171, 3 48, S_0x2b8c450; - .timescale -9 -12; -L_0x2bfd740/d .functor NAND 1, L_0x2c08700, L_0x2c087a0, C4<1>, C4<1>; -L_0x2bfd740 .delay (10000,10000,10000) L_0x2bfd740/d; -L_0x2c07a10/d .functor NOT 1, L_0x2bfd740, C4<0>, C4<0>, C4<0>; -L_0x2c07a10 .delay (10000,10000,10000) L_0x2c07a10/d; -v0x2b8cc00_0 .net "A", 0 0, L_0x2c08700; 1 drivers -v0x2b8ccc0_0 .net "AandB", 0 0, L_0x2c07a10; 1 drivers -v0x2b8cd40_0 .net "AnandB", 0 0, L_0x2bfd740; 1 drivers -v0x2b8cdf0_0 .net "AndNandOut", 0 0, L_0x2c08be0; 1 drivers -v0x2b8ced0_0 .net "B", 0 0, L_0x2c087a0; 1 drivers -v0x2b8cf50_0 .alias "Command", 2 0, v0x2bc67a0_0; -L_0x2c08d70 .part v0x2bc78e0_0, 0, 1; -S_0x2b8c6b0 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0x2b8c5c0; - .timescale -9 -12; -L_0x2c07b40/d .functor NOT 1, L_0x2c08d70, C4<0>, C4<0>, C4<0>; -L_0x2c07b40 .delay (10000,10000,10000) L_0x2c07b40/d; -L_0x2c089c0/d .functor AND 1, L_0x2c07a10, L_0x2c07b40, C4<1>, C4<1>; -L_0x2c089c0 .delay (20000,20000,20000) L_0x2c089c0/d; -L_0x2c08ab0/d .functor AND 1, L_0x2bfd740, L_0x2c08d70, C4<1>, C4<1>; -L_0x2c08ab0 .delay (20000,20000,20000) L_0x2c08ab0/d; -L_0x2c08be0/d .functor OR 1, L_0x2c089c0, L_0x2c08ab0, C4<0>, C4<0>; -L_0x2c08be0 .delay (20000,20000,20000) L_0x2c08be0/d; -v0x2b8c7a0_0 .net "S", 0 0, L_0x2c08d70; 1 drivers -v0x2b8c820_0 .alias "in0", 0 0, v0x2b8ccc0_0; -v0x2b8c8c0_0 .alias "in1", 0 0, v0x2b8cd40_0; -v0x2b8c960_0 .net "nS", 0 0, L_0x2c07b40; 1 drivers -v0x2b8c9e0_0 .net "out0", 0 0, L_0x2c089c0; 1 drivers -v0x2b8ca80_0 .net "out1", 0 0, L_0x2c08ab0; 1 drivers -v0x2b8cb60_0 .alias "outfinal", 0 0, v0x2b8cdf0_0; -S_0x2b8b870 .scope generate, "andbits[31]" "andbits[31]" 3 169, 3 169, S_0x2b8b740; - .timescale -9 -12; -P_0x2b8b968 .param/l "i" 3 169, +C4<011111>; -S_0x2b8b9e0 .scope module, "attempt" "AndNand" 3 171, 3 48, S_0x2b8b870; - .timescale -9 -12; -L_0x2c08890/d .functor NAND 1, L_0x2c09860, L_0x2c08eb0, C4<1>, C4<1>; -L_0x2c08890 .delay (10000,10000,10000) L_0x2c08890/d; -L_0x2c091e0/d .functor NOT 1, L_0x2c08890, C4<0>, C4<0>, C4<0>; -L_0x2c091e0 .delay (10000,10000,10000) L_0x2c091e0/d; -v0x2b8c040_0 .net "A", 0 0, L_0x2c09860; 1 drivers -v0x2b8c100_0 .net "AandB", 0 0, L_0x2c091e0; 1 drivers -v0x2b8c180_0 .net "AnandB", 0 0, L_0x2c08890; 1 drivers -v0x2b8c230_0 .net "AndNandOut", 0 0, L_0x2c09590; 1 drivers -v0x2b8c310_0 .net "B", 0 0, L_0x2c08eb0; 1 drivers -v0x2b8c390_0 .alias "Command", 2 0, v0x2bc67a0_0; -L_0x2c09720 .part v0x2bc78e0_0, 0, 1; -S_0x2b8bad0 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0x2b8b9e0; - .timescale -9 -12; -L_0x2c092d0/d .functor NOT 1, L_0x2c09720, C4<0>, C4<0>, C4<0>; -L_0x2c092d0 .delay (10000,10000,10000) L_0x2c092d0/d; -L_0x2c09370/d .functor AND 1, L_0x2c091e0, L_0x2c092d0, C4<1>, C4<1>; -L_0x2c09370 .delay (20000,20000,20000) L_0x2c09370/d; -L_0x2c09460/d .functor AND 1, L_0x2c08890, L_0x2c09720, C4<1>, C4<1>; -L_0x2c09460 .delay (20000,20000,20000) L_0x2c09460/d; -L_0x2c09590/d .functor OR 1, L_0x2c09370, L_0x2c09460, C4<0>, C4<0>; -L_0x2c09590 .delay (20000,20000,20000) L_0x2c09590/d; -v0x2b8bbc0_0 .net "S", 0 0, L_0x2c09720; 1 drivers -v0x2b8bc60_0 .alias "in0", 0 0, v0x2b8c100_0; -v0x2b8bd00_0 .alias "in1", 0 0, v0x2b8c180_0; -v0x2b8bda0_0 .net "nS", 0 0, L_0x2c092d0; 1 drivers -v0x2b8be20_0 .net "out0", 0 0, L_0x2c09370; 1 drivers -v0x2b8bec0_0 .net "out1", 0 0, L_0x2c09460; 1 drivers -v0x2b8bfa0_0 .alias "outfinal", 0 0, v0x2b8c230_0; -S_0x2b62fd0 .scope module, "trial2" "OrNorXor32" 2 145, 3 177, S_0x270e6d0; - .timescale -9 -12; -P_0x2b5fb08 .param/l "size" 3 184, +C4<0100000>; -v0x2b8b420_0 .alias "A", 31 0, v0x2bc6580_0; -v0x2b8b530_0 .alias "B", 31 0, v0x2bc66a0_0; -v0x2b8b640_0 .alias "Command", 2 0, v0x2bc67a0_0; -v0x2b8b6c0_0 .alias "OrNorXorOut", 31 0, v0x2bc79e0_0; -L_0x2c0b350 .part/pv L_0x2c0b120, 1, 1, 32; -L_0x2c0b480 .part v0x2bc7660_0, 1, 1; -L_0x2c0b520 .part v0x2bc7860_0, 1, 1; -L_0x2c0c590 .part/pv L_0x2c0c320, 2, 1, 32; -L_0x2c0c630 .part v0x2bc7660_0, 2, 1; -L_0x2c0c6d0 .part v0x2bc7860_0, 2, 1; -L_0x2c0d7c0 .part/pv L_0x2c0d590, 3, 1, 32; -L_0x2c0d860 .part v0x2bc7660_0, 3, 1; -L_0x2c0d900 .part v0x2bc7860_0, 3, 1; -L_0x2c0ea70 .part/pv L_0x2c0e800, 4, 1, 32; -L_0x2c0eb70 .part v0x2bc7660_0, 4, 1; -L_0x2c0ec10 .part v0x2bc7860_0, 4, 1; -L_0x2c0fd70 .part/pv L_0x2c0fb00, 5, 1, 32; -L_0x2c0ff20 .part v0x2bc7660_0, 5, 1; -L_0x2c0ffc0 .part v0x2bc7860_0, 5, 1; -L_0x2c11160 .part/pv L_0x2c10ef0, 6, 1, 32; -L_0x2c11200 .part v0x2bc7660_0, 6, 1; -L_0x2c112a0 .part v0x2bc7860_0, 6, 1; -L_0x2c12460 .part/pv L_0x2c121f0, 7, 1, 32; -L_0x2c12500 .part v0x2bc7660_0, 7, 1; -L_0x2c11340 .part v0x2bc7860_0, 7, 1; -L_0x2c13750 .part/pv L_0x2c134e0, 8, 1, 32; -L_0x2c125a0 .part v0x2bc7660_0, 8, 1; -L_0x2c138b0 .part v0x2bc7860_0, 8, 1; -L_0x2c14a60 .part/pv L_0x2c147f0, 9, 1, 32; -L_0x2c14b00 .part v0x2bc7660_0, 9, 1; -L_0x2c13950 .part v0x2bc7860_0, 9, 1; -L_0x2c15d60 .part/pv L_0x2c15af0, 10, 1, 32; -L_0x2c14ba0 .part v0x2bc7660_0, 10, 1; -L_0x2c15ef0 .part v0x2bc7860_0, 10, 1; -L_0x2c17060 .part/pv L_0x2c16df0, 11, 1, 32; -L_0x2c17100 .part v0x2bc7660_0, 11, 1; -L_0x2c15f90 .part v0x2bc7860_0, 11, 1; -L_0x2c18350 .part/pv L_0x2c180e0, 12, 1, 32; -L_0x2c171a0 .part v0x2bc7660_0, 12, 1; -L_0x2c18510 .part v0x2bc7860_0, 12, 1; -L_0x2c19670 .part/pv L_0x2c19400, 13, 1, 32; -L_0x2c0fe10 .part v0x2bc7660_0, 13, 1; -L_0x2c185b0 .part v0x2bc7860_0, 13, 1; -L_0x2c1aa80 .part/pv L_0x2c1a810, 14, 1, 32; -L_0x2c19920 .part v0x2bc7660_0, 14, 1; -L_0x2c199c0 .part v0x2bc7860_0, 14, 1; -L_0x2c1bd80 .part/pv L_0x2c1bb10, 15, 1, 32; -L_0x2c1be20 .part v0x2bc7660_0, 15, 1; -L_0x2c1ab20 .part v0x2bc7860_0, 15, 1; -L_0x2c1d070 .part/pv L_0x2c1ce00, 16, 1, 32; -L_0x2c1bec0 .part v0x2bc7660_0, 16, 1; -L_0x2c1bf60 .part v0x2bc7860_0, 16, 1; -L_0x2c1e380 .part/pv L_0x2c1e110, 17, 1, 32; -L_0x2c1e420 .part v0x2bc7660_0, 17, 1; -L_0x2c1d110 .part v0x2bc7860_0, 17, 1; -L_0x2c1f670 .part/pv L_0x2c1f400, 18, 1, 32; -L_0x2c1e4c0 .part v0x2bc7660_0, 18, 1; -L_0x2c1e560 .part v0x2bc7860_0, 18, 1; -L_0x2c20970 .part/pv L_0x2c20700, 19, 1, 32; -L_0x2c20a10 .part v0x2bc7660_0, 19, 1; -L_0x2c1f710 .part v0x2bc7860_0, 19, 1; -L_0x2c21c70 .part/pv L_0x2c21a00, 20, 1, 32; -L_0x2c20ab0 .part v0x2bc7660_0, 20, 1; -L_0x2c20b50 .part v0x2bc7860_0, 20, 1; -L_0x2c22f80 .part/pv L_0x2c22d10, 21, 1, 32; -L_0x2c23020 .part v0x2bc7660_0, 21, 1; -L_0x2c21d10 .part v0x2bc7860_0, 21, 1; -L_0x2c24270 .part/pv L_0x2c24000, 22, 1, 32; -L_0x2c230c0 .part v0x2bc7660_0, 22, 1; -L_0x2c23160 .part v0x2bc7860_0, 22, 1; -L_0x2c25570 .part/pv L_0x2c25300, 23, 1, 32; -L_0x2c25610 .part v0x2bc7660_0, 23, 1; -L_0x2c24310 .part v0x2bc7860_0, 23, 1; -L_0x2c26870 .part/pv L_0x2c26600, 24, 1, 32; -L_0x2c256b0 .part v0x2bc7660_0, 24, 1; -L_0x2c25750 .part v0x2bc7860_0, 24, 1; -L_0x2c27b70 .part/pv L_0x2c27900, 25, 1, 32; -L_0x2c27c10 .part v0x2bc7660_0, 25, 1; -L_0x2c26910 .part v0x2bc7860_0, 25, 1; -L_0x2c28e60 .part/pv L_0x2c28bf0, 26, 1, 32; -L_0x2c27cb0 .part v0x2bc7660_0, 26, 1; -L_0x2c27d50 .part v0x2bc7860_0, 26, 1; -L_0x2c2a170 .part/pv L_0x2c29f00, 27, 1, 32; -L_0x2c2a210 .part v0x2bc7660_0, 27, 1; -L_0x2c28f00 .part v0x2bc7860_0, 27, 1; -L_0x2c2b470 .part/pv L_0x2c2b200, 28, 1, 32; -L_0x2c2a2b0 .part v0x2bc7660_0, 28, 1; -L_0x2c2a350 .part v0x2bc7860_0, 28, 1; -L_0x2c2c770 .part/pv L_0x2c2c500, 29, 1, 32; -L_0x2c19710 .part v0x2bc7660_0, 29, 1; -L_0x2c197b0 .part v0x2bc7860_0, 29, 1; -L_0x2c2daa0 .part/pv L_0x2c2d870, 30, 1, 32; -L_0x2c2cc20 .part v0x2bc7660_0, 30, 1; -L_0x2c2ccc0 .part v0x2bc7860_0, 30, 1; -L_0x2c2ebf0 .part/pv L_0x2c2e9c0, 31, 1, 32; -L_0x2c2ec90 .part v0x2bc7660_0, 31, 1; -L_0x2c2db40 .part v0x2bc7860_0, 31, 1; -L_0x2c2fe80 .part/pv L_0x2c2fc10, 0, 1, 32; -L_0x2c2ed30 .part v0x2bc7660_0, 0, 1; -L_0x2c2edd0 .part v0x2bc7860_0, 0, 1; -S_0x2b8a1e0 .scope module, "attempt2" "OrNorXor" 3 192, 3 64, S_0x2b62fd0; - .timescale -9 -12; -L_0x2c2dbe0/d .functor NOR 1, L_0x2c2ed30, L_0x2c2edd0, C4<0>, C4<0>; -L_0x2c2dbe0 .delay (10000,10000,10000) L_0x2c2dbe0/d; -L_0x2c2dcd0/d .functor NOT 1, L_0x2c2dbe0, C4<0>, C4<0>, C4<0>; -L_0x2c2dcd0 .delay (10000,10000,10000) L_0x2c2dcd0/d; -L_0x2c2f020/d .functor NAND 1, L_0x2c2ed30, L_0x2c2edd0, C4<1>, C4<1>; -L_0x2c2f020 .delay (10000,10000,10000) L_0x2c2f020/d; -L_0x2c2f120/d .functor NAND 1, L_0x2c2f020, L_0x2c2dcd0, C4<1>, C4<1>; -L_0x2c2f120 .delay (10000,10000,10000) L_0x2c2f120/d; -L_0x2c2f210/d .functor NOT 1, L_0x2c2f120, C4<0>, C4<0>, C4<0>; -L_0x2c2f210 .delay (10000,10000,10000) L_0x2c2f210/d; -v0x2b8ad30_0 .net "A", 0 0, L_0x2c2ed30; 1 drivers -v0x2b8add0_0 .net "AnandB", 0 0, L_0x2c2f020; 1 drivers -v0x2b8ae70_0 .net "AnorB", 0 0, L_0x2c2dbe0; 1 drivers -v0x2b8af20_0 .net "AorB", 0 0, L_0x2c2dcd0; 1 drivers -v0x2b8b000_0 .net "AxorB", 0 0, L_0x2c2f210; 1 drivers -v0x2b8b0b0_0 .net "B", 0 0, L_0x2c2edd0; 1 drivers -v0x2b8b170_0 .alias "Command", 2 0, v0x2bc67a0_0; -v0x2b8b1f0_0 .net "OrNorXorOut", 0 0, L_0x2c2fc10; 1 drivers -v0x2b8b270_0 .net "XorNor", 0 0, L_0x2c2f690; 1 drivers -v0x2b8b340_0 .net "nXor", 0 0, L_0x2c2f120; 1 drivers -L_0x2c2f810 .part v0x2bc78e0_0, 2, 1; -L_0x2c2fde0 .part v0x2bc78e0_0, 0, 1; -S_0x2b8a7c0 .scope module, "mux0" "TwoInMux" 3 83, 3 8, S_0x2b8a1e0; - .timescale -9 -12; -L_0x2c2f370/d .functor NOT 1, L_0x2c2f810, C4<0>, C4<0>, C4<0>; -L_0x2c2f370 .delay (10000,10000,10000) L_0x2c2f370/d; -L_0x2c2f430/d .functor AND 1, L_0x2c2f210, L_0x2c2f370, C4<1>, C4<1>; -L_0x2c2f430 .delay (20000,20000,20000) L_0x2c2f430/d; -L_0x2c2f540/d .functor AND 1, L_0x2c2dbe0, L_0x2c2f810, C4<1>, C4<1>; -L_0x2c2f540 .delay (20000,20000,20000) L_0x2c2f540/d; -L_0x2c2f690/d .functor OR 1, L_0x2c2f430, L_0x2c2f540, C4<0>, C4<0>; -L_0x2c2f690 .delay (20000,20000,20000) L_0x2c2f690/d; -v0x2b8a8b0_0 .net "S", 0 0, L_0x2c2f810; 1 drivers -v0x2b8a970_0 .alias "in0", 0 0, v0x2b8b000_0; -v0x2b8aa10_0 .alias "in1", 0 0, v0x2b8ae70_0; -v0x2b8aab0_0 .net "nS", 0 0, L_0x2c2f370; 1 drivers -v0x2b8ab30_0 .net "out0", 0 0, L_0x2c2f430; 1 drivers -v0x2b8abd0_0 .net "out1", 0 0, L_0x2c2f540; 1 drivers -v0x2b8acb0_0 .alias "outfinal", 0 0, v0x2b8b270_0; -S_0x2b8a2d0 .scope module, "mux1" "TwoInMux" 3 84, 3 8, S_0x2b8a1e0; - .timescale -9 -12; -L_0x2c2f8b0/d .functor NOT 1, L_0x2c2fde0, C4<0>, C4<0>, C4<0>; -L_0x2c2f8b0 .delay (10000,10000,10000) L_0x2c2f8b0/d; -L_0x2c2f970/d .functor AND 1, L_0x2c2f690, L_0x2c2f8b0, C4<1>, C4<1>; -L_0x2c2f970 .delay (20000,20000,20000) L_0x2c2f970/d; -L_0x2c2fac0/d .functor AND 1, L_0x2c2dcd0, L_0x2c2fde0, C4<1>, C4<1>; -L_0x2c2fac0 .delay (20000,20000,20000) L_0x2c2fac0/d; -L_0x2c2fc10/d .functor OR 1, L_0x2c2f970, L_0x2c2fac0, C4<0>, C4<0>; -L_0x2c2fc10 .delay (20000,20000,20000) L_0x2c2fc10/d; -v0x2b8a3c0_0 .net "S", 0 0, L_0x2c2fde0; 1 drivers -v0x2b8a440_0 .alias "in0", 0 0, v0x2b8b270_0; -v0x2b8a4c0_0 .alias "in1", 0 0, v0x2b8af20_0; -v0x2b8a560_0 .net "nS", 0 0, L_0x2c2f8b0; 1 drivers -v0x2b8a5e0_0 .net "out0", 0 0, L_0x2c2f970; 1 drivers -v0x2b8a680_0 .net "out1", 0 0, L_0x2c2fac0; 1 drivers -v0x2b8a720_0 .alias "outfinal", 0 0, v0x2b8b1f0_0; -S_0x2b88e10 .scope generate, "orbits[1]" "orbits[1]" 3 196, 3 196, S_0x2b62fd0; - .timescale -9 -12; -P_0x2b88b28 .param/l "i" 3 196, +C4<01>; -S_0x2b88f40 .scope module, "attempt" "OrNorXor" 3 198, 3 64, S_0x2b88e10; - .timescale -9 -12; -L_0x2c09a90/d .functor NOR 1, L_0x2c0b480, L_0x2c0b520, C4<0>, C4<0>; -L_0x2c09a90 .delay (10000,10000,10000) L_0x2c09a90/d; -L_0x2c0a520/d .functor NOT 1, L_0x2c09a90, C4<0>, C4<0>, C4<0>; -L_0x2c0a520 .delay (10000,10000,10000) L_0x2c0a520/d; -L_0x2c0a610/d .functor NAND 1, L_0x2c0b480, L_0x2c0b520, C4<1>, C4<1>; -L_0x2c0a610 .delay (10000,10000,10000) L_0x2c0a610/d; -L_0x2c0a750/d .functor NAND 1, L_0x2c0a610, L_0x2c0a520, C4<1>, C4<1>; -L_0x2c0a750 .delay (10000,10000,10000) L_0x2c0a750/d; -L_0x2c0a840/d .functor NOT 1, L_0x2c0a750, C4<0>, C4<0>, C4<0>; -L_0x2c0a840 .delay (10000,10000,10000) L_0x2c0a840/d; -v0x2b89ab0_0 .net "A", 0 0, L_0x2c0b480; 1 drivers -v0x2b89b70_0 .net "AnandB", 0 0, L_0x2c0a610; 1 drivers -v0x2b89c10_0 .net "AnorB", 0 0, L_0x2c09a90; 1 drivers -v0x2b89c90_0 .net "AorB", 0 0, L_0x2c0a520; 1 drivers -v0x2b89d70_0 .net "AxorB", 0 0, L_0x2c0a840; 1 drivers -v0x2b89e20_0 .net "B", 0 0, L_0x2c0b520; 1 drivers -v0x2b89ee0_0 .alias "Command", 2 0, v0x2bc67a0_0; -v0x2b89f60_0 .net "OrNorXorOut", 0 0, L_0x2c0b120; 1 drivers -v0x2b8a030_0 .net "XorNor", 0 0, L_0x2c0ac40; 1 drivers -v0x2b8a100_0 .net "nXor", 0 0, L_0x2c0a750; 1 drivers -L_0x2c0ad80 .part v0x2bc78e0_0, 2, 1; -L_0x2c0b2b0 .part v0x2bc78e0_0, 0, 1; -S_0x2b89540 .scope module, "mux0" "TwoInMux" 3 83, 3 8, S_0x2b88f40; - .timescale -9 -12; -L_0x2c0a980/d .functor NOT 1, L_0x2c0ad80, C4<0>, C4<0>, C4<0>; -L_0x2c0a980 .delay (10000,10000,10000) L_0x2c0a980/d; -L_0x2c0aa20/d .functor AND 1, L_0x2c0a840, L_0x2c0a980, C4<1>, C4<1>; -L_0x2c0aa20 .delay (20000,20000,20000) L_0x2c0aa20/d; -L_0x2c0ab10/d .functor AND 1, L_0x2c09a90, L_0x2c0ad80, C4<1>, C4<1>; -L_0x2c0ab10 .delay (20000,20000,20000) L_0x2c0ab10/d; -L_0x2c0ac40/d .functor OR 1, L_0x2c0aa20, L_0x2c0ab10, C4<0>, C4<0>; -L_0x2c0ac40 .delay (20000,20000,20000) L_0x2c0ac40/d; -v0x2b89630_0 .net "S", 0 0, L_0x2c0ad80; 1 drivers -v0x2b896f0_0 .alias "in0", 0 0, v0x2b89d70_0; -v0x2b89790_0 .alias "in1", 0 0, v0x2b89c10_0; -v0x2b89830_0 .net "nS", 0 0, L_0x2c0a980; 1 drivers -v0x2b898b0_0 .net "out0", 0 0, L_0x2c0aa20; 1 drivers -v0x2b89950_0 .net "out1", 0 0, L_0x2c0ab10; 1 drivers -v0x2b89a30_0 .alias "outfinal", 0 0, v0x2b8a030_0; -S_0x2b89030 .scope module, "mux1" "TwoInMux" 3 84, 3 8, S_0x2b88f40; - .timescale -9 -12; -L_0x2c0ae20/d .functor NOT 1, L_0x2c0b2b0, C4<0>, C4<0>, C4<0>; -L_0x2c0ae20 .delay (10000,10000,10000) L_0x2c0ae20/d; -L_0x2c0aec0/d .functor AND 1, L_0x2c0ac40, L_0x2c0ae20, C4<1>, C4<1>; -L_0x2c0aec0 .delay (20000,20000,20000) L_0x2c0aec0/d; -L_0x2c0aff0/d .functor AND 1, L_0x2c0a520, L_0x2c0b2b0, C4<1>, C4<1>; -L_0x2c0aff0 .delay (20000,20000,20000) L_0x2c0aff0/d; -L_0x2c0b120/d .functor OR 1, L_0x2c0aec0, L_0x2c0aff0, C4<0>, C4<0>; -L_0x2c0b120 .delay (20000,20000,20000) L_0x2c0b120/d; -v0x2b89120_0 .net "S", 0 0, L_0x2c0b2b0; 1 drivers -v0x2b891a0_0 .alias "in0", 0 0, v0x2b8a030_0; -v0x2b89220_0 .alias "in1", 0 0, v0x2b89c90_0; -v0x2b892a0_0 .net "nS", 0 0, L_0x2c0ae20; 1 drivers -v0x2b89320_0 .net "out0", 0 0, L_0x2c0aec0; 1 drivers -v0x2b893c0_0 .net "out1", 0 0, L_0x2c0aff0; 1 drivers -v0x2b894a0_0 .alias "outfinal", 0 0, v0x2b89f60_0; -S_0x2b3c7e0 .scope generate, "orbits[2]" "orbits[2]" 3 196, 3 196, S_0x2b62fd0; - .timescale -9 -12; -P_0x2b86f48 .param/l "i" 3 196, +C4<010>; -S_0x2b3c910 .scope module, "attempt" "OrNorXor" 3 198, 3 64, S_0x2b3c7e0; - .timescale -9 -12; -L_0x2c0b5c0/d .functor NOR 1, L_0x2c0c630, L_0x2c0c6d0, C4<0>, C4<0>; -L_0x2c0b5c0 .delay (10000,10000,10000) L_0x2c0b5c0/d; -L_0x2c0b660/d .functor NOT 1, L_0x2c0b5c0, C4<0>, C4<0>, C4<0>; -L_0x2c0b660 .delay (10000,10000,10000) L_0x2c0b660/d; -L_0x2c0b750/d .functor NAND 1, L_0x2c0c630, L_0x2c0c6d0, C4<1>, C4<1>; -L_0x2c0b750 .delay (10000,10000,10000) L_0x2c0b750/d; -L_0x2c0b890/d .functor NAND 1, L_0x2c0b750, L_0x2c0b660, C4<1>, C4<1>; -L_0x2c0b890 .delay (10000,10000,10000) L_0x2c0b890/d; -L_0x2c0b980/d .functor NOT 1, L_0x2c0b890, C4<0>, C4<0>, C4<0>; -L_0x2c0b980 .delay (10000,10000,10000) L_0x2c0b980/d; -v0x2b88720_0 .net "A", 0 0, L_0x2c0c630; 1 drivers -v0x2b887c0_0 .net "AnandB", 0 0, L_0x2c0b750; 1 drivers -v0x2b88860_0 .net "AnorB", 0 0, L_0x2c0b5c0; 1 drivers -v0x2b88910_0 .net "AorB", 0 0, L_0x2c0b660; 1 drivers -v0x2b889f0_0 .net "AxorB", 0 0, L_0x2c0b980; 1 drivers -v0x2b88aa0_0 .net "B", 0 0, L_0x2c0c6d0; 1 drivers -v0x2b88b60_0 .alias "Command", 2 0, v0x2bc67a0_0; -v0x2b88be0_0 .net "OrNorXorOut", 0 0, L_0x2c0c320; 1 drivers -v0x2b88c60_0 .net "XorNor", 0 0, L_0x2c0bda0; 1 drivers -v0x2b88d30_0 .net "nXor", 0 0, L_0x2c0b890; 1 drivers -L_0x2c0bf20 .part v0x2bc78e0_0, 2, 1; -L_0x2c0c4f0 .part v0x2bc78e0_0, 0, 1; -S_0x2b881b0 .scope module, "mux0" "TwoInMux" 3 83, 3 8, S_0x2b3c910; - .timescale -9 -12; -L_0x2c0bac0/d .functor NOT 1, L_0x2c0bf20, C4<0>, C4<0>, C4<0>; -L_0x2c0bac0 .delay (10000,10000,10000) L_0x2c0bac0/d; -L_0x2c0bb60/d .functor AND 1, L_0x2c0b980, L_0x2c0bac0, C4<1>, C4<1>; -L_0x2c0bb60 .delay (20000,20000,20000) L_0x2c0bb60/d; -L_0x2c0bc50/d .functor AND 1, L_0x2c0b5c0, L_0x2c0bf20, C4<1>, C4<1>; -L_0x2c0bc50 .delay (20000,20000,20000) L_0x2c0bc50/d; -L_0x2c0bda0/d .functor OR 1, L_0x2c0bb60, L_0x2c0bc50, C4<0>, C4<0>; -L_0x2c0bda0 .delay (20000,20000,20000) L_0x2c0bda0/d; -v0x2b882a0_0 .net "S", 0 0, L_0x2c0bf20; 1 drivers -v0x2b88360_0 .alias "in0", 0 0, v0x2b889f0_0; -v0x2b88400_0 .alias "in1", 0 0, v0x2b88860_0; -v0x2b884a0_0 .net "nS", 0 0, L_0x2c0bac0; 1 drivers -v0x2b88520_0 .net "out0", 0 0, L_0x2c0bb60; 1 drivers -v0x2b885c0_0 .net "out1", 0 0, L_0x2c0bc50; 1 drivers -v0x2b886a0_0 .alias "outfinal", 0 0, v0x2b88c60_0; -S_0x2b3ca00 .scope module, "mux1" "TwoInMux" 3 84, 3 8, S_0x2b3c910; - .timescale -9 -12; -L_0x2c0bfc0/d .functor NOT 1, L_0x2c0c4f0, C4<0>, C4<0>, C4<0>; -L_0x2c0bfc0 .delay (10000,10000,10000) L_0x2c0bfc0/d; -L_0x2c0c080/d .functor AND 1, L_0x2c0bda0, L_0x2c0bfc0, C4<1>, C4<1>; -L_0x2c0c080 .delay (20000,20000,20000) L_0x2c0c080/d; -L_0x2c0c1d0/d .functor AND 1, L_0x2c0b660, L_0x2c0c4f0, C4<1>, C4<1>; -L_0x2c0c1d0 .delay (20000,20000,20000) L_0x2c0c1d0/d; -L_0x2c0c320/d .functor OR 1, L_0x2c0c080, L_0x2c0c1d0, C4<0>, C4<0>; -L_0x2c0c320 .delay (20000,20000,20000) L_0x2c0c320/d; -v0x2b3caf0_0 .net "S", 0 0, L_0x2c0c4f0; 1 drivers -v0x2b3cb70_0 .alias "in0", 0 0, v0x2b88c60_0; -v0x2b3cc10_0 .alias "in1", 0 0, v0x2b88910_0; -v0x2b3ccb0_0 .net "nS", 0 0, L_0x2c0bfc0; 1 drivers -v0x2b3cd30_0 .net "out0", 0 0, L_0x2c0c080; 1 drivers -v0x2b88030_0 .net "out1", 0 0, L_0x2c0c1d0; 1 drivers -v0x2b88110_0 .alias "outfinal", 0 0, v0x2b88be0_0; -S_0x2b85e60 .scope generate, "orbits[3]" "orbits[3]" 3 196, 3 196, S_0x2b62fd0; - .timescale -9 -12; -P_0x2b85b78 .param/l "i" 3 196, +C4<011>; -S_0x2b85f90 .scope module, "attempt" "OrNorXor" 3 198, 3 64, S_0x2b85e60; - .timescale -9 -12; -L_0x2c0c7b0/d .functor NOR 1, L_0x2c0d860, L_0x2c0d900, C4<0>, C4<0>; -L_0x2c0c7b0 .delay (10000,10000,10000) L_0x2c0c7b0/d; -L_0x2c0c8a0/d .functor NOT 1, L_0x2c0c7b0, C4<0>, C4<0>, C4<0>; -L_0x2c0c8a0 .delay (10000,10000,10000) L_0x2c0c8a0/d; -L_0x2c0c9b0/d .functor NAND 1, L_0x2c0d860, L_0x2c0d900, C4<1>, C4<1>; -L_0x2c0c9b0 .delay (10000,10000,10000) L_0x2c0c9b0/d; -L_0x2c0cb10/d .functor NAND 1, L_0x2c0c9b0, L_0x2c0c8a0, C4<1>, C4<1>; -L_0x2c0cb10 .delay (10000,10000,10000) L_0x2c0cb10/d; -L_0x2c0cc20/d .functor NOT 1, L_0x2c0cb10, C4<0>, C4<0>, C4<0>; -L_0x2c0cc20 .delay (10000,10000,10000) L_0x2c0cc20/d; -v0x2b86b40_0 .net "A", 0 0, L_0x2c0d860; 1 drivers -v0x2b86be0_0 .net "AnandB", 0 0, L_0x2c0c9b0; 1 drivers -v0x2b86c80_0 .net "AnorB", 0 0, L_0x2c0c7b0; 1 drivers -v0x2b86d30_0 .net "AorB", 0 0, L_0x2c0c8a0; 1 drivers -v0x2b86e10_0 .net "AxorB", 0 0, L_0x2c0cc20; 1 drivers -v0x2b86ec0_0 .net "B", 0 0, L_0x2c0d900; 1 drivers -v0x2b86f80_0 .alias "Command", 2 0, v0x2bc67a0_0; -v0x2b3c5b0_0 .net "OrNorXorOut", 0 0, L_0x2c0d590; 1 drivers -v0x2b3c630_0 .net "XorNor", 0 0, L_0x2c0d0b0; 1 drivers -v0x2b3c700_0 .net "nXor", 0 0, L_0x2c0cb10; 1 drivers -L_0x2c0d1f0 .part v0x2bc78e0_0, 2, 1; -L_0x2c0d720 .part v0x2bc78e0_0, 0, 1; -S_0x2b865d0 .scope module, "mux0" "TwoInMux" 3 83, 3 8, S_0x2b85f90; - .timescale -9 -12; -L_0x2c0cd80/d .functor NOT 1, L_0x2c0d1f0, C4<0>, C4<0>, C4<0>; -L_0x2c0cd80 .delay (10000,10000,10000) L_0x2c0cd80/d; -L_0x2c0ce40/d .functor AND 1, L_0x2c0cc20, L_0x2c0cd80, C4<1>, C4<1>; -L_0x2c0ce40 .delay (20000,20000,20000) L_0x2c0ce40/d; -L_0x2c0cf50/d .functor AND 1, L_0x2c0c7b0, L_0x2c0d1f0, C4<1>, C4<1>; -L_0x2c0cf50 .delay (20000,20000,20000) L_0x2c0cf50/d; -L_0x2c0d0b0/d .functor OR 1, L_0x2c0ce40, L_0x2c0cf50, C4<0>, C4<0>; -L_0x2c0d0b0 .delay (20000,20000,20000) L_0x2c0d0b0/d; -v0x2b866c0_0 .net "S", 0 0, L_0x2c0d1f0; 1 drivers -v0x2b86780_0 .alias "in0", 0 0, v0x2b86e10_0; -v0x2b86820_0 .alias "in1", 0 0, v0x2b86c80_0; -v0x2b868c0_0 .net "nS", 0 0, L_0x2c0cd80; 1 drivers -v0x2b86940_0 .net "out0", 0 0, L_0x2c0ce40; 1 drivers -v0x2b869e0_0 .net "out1", 0 0, L_0x2c0cf50; 1 drivers -v0x2b86ac0_0 .alias "outfinal", 0 0, v0x2b3c630_0; -S_0x2b86080 .scope module, "mux1" "TwoInMux" 3 84, 3 8, S_0x2b85f90; - .timescale -9 -12; -L_0x2c0d290/d .functor NOT 1, L_0x2c0d720, C4<0>, C4<0>, C4<0>; -L_0x2c0d290 .delay (10000,10000,10000) L_0x2c0d290/d; -L_0x2c0d330/d .functor AND 1, L_0x2c0d0b0, L_0x2c0d290, C4<1>, C4<1>; -L_0x2c0d330 .delay (20000,20000,20000) L_0x2c0d330/d; -L_0x2c0d460/d .functor AND 1, L_0x2c0c8a0, L_0x2c0d720, C4<1>, C4<1>; -L_0x2c0d460 .delay (20000,20000,20000) L_0x2c0d460/d; -L_0x2c0d590/d .functor OR 1, L_0x2c0d330, L_0x2c0d460, C4<0>, C4<0>; -L_0x2c0d590 .delay (20000,20000,20000) L_0x2c0d590/d; -v0x2b86170_0 .net "S", 0 0, L_0x2c0d720; 1 drivers -v0x2b861f0_0 .alias "in0", 0 0, v0x2b3c630_0; -v0x2b86290_0 .alias "in1", 0 0, v0x2b86d30_0; -v0x2b86330_0 .net "nS", 0 0, L_0x2c0d290; 1 drivers -v0x2b863b0_0 .net "out0", 0 0, L_0x2c0d330; 1 drivers -v0x2b86450_0 .net "out1", 0 0, L_0x2c0d460; 1 drivers -v0x2b86530_0 .alias "outfinal", 0 0, v0x2b3c5b0_0; -S_0x2b84a90 .scope generate, "orbits[4]" "orbits[4]" 3 196, 3 196, S_0x2b62fd0; - .timescale -9 -12; -P_0x2b847a8 .param/l "i" 3 196, +C4<0100>; -S_0x2b84bc0 .scope module, "attempt" "OrNorXor" 3 198, 3 64, S_0x2b84a90; - .timescale -9 -12; -L_0x2c0d9a0/d .functor NOR 1, L_0x2c0eb70, L_0x2c0ec10, C4<0>, C4<0>; -L_0x2c0d9a0 .delay (10000,10000,10000) L_0x2c0d9a0/d; -L_0x2c0daa0/d .functor NOT 1, L_0x2c0d9a0, C4<0>, C4<0>, C4<0>; -L_0x2c0daa0 .delay (10000,10000,10000) L_0x2c0daa0/d; -L_0x2c0db90/d .functor NAND 1, L_0x2c0eb70, L_0x2c0ec10, C4<1>, C4<1>; -L_0x2c0db90 .delay (10000,10000,10000) L_0x2c0db90/d; -L_0x2c0dcf0/d .functor NAND 1, L_0x2c0db90, L_0x2c0daa0, C4<1>, C4<1>; -L_0x2c0dcf0 .delay (10000,10000,10000) L_0x2c0dcf0/d; -L_0x2c0de00/d .functor NOT 1, L_0x2c0dcf0, C4<0>, C4<0>, C4<0>; -L_0x2c0de00 .delay (10000,10000,10000) L_0x2c0de00/d; -v0x2b85770_0 .net "A", 0 0, L_0x2c0eb70; 1 drivers -v0x2b85810_0 .net "AnandB", 0 0, L_0x2c0db90; 1 drivers -v0x2b858b0_0 .net "AnorB", 0 0, L_0x2c0d9a0; 1 drivers -v0x2b85960_0 .net "AorB", 0 0, L_0x2c0daa0; 1 drivers -v0x2b85a40_0 .net "AxorB", 0 0, L_0x2c0de00; 1 drivers -v0x2b85af0_0 .net "B", 0 0, L_0x2c0ec10; 1 drivers -v0x2b85bb0_0 .alias "Command", 2 0, v0x2bc67a0_0; -v0x2b85c30_0 .net "OrNorXorOut", 0 0, L_0x2c0e800; 1 drivers -v0x2b85cb0_0 .net "XorNor", 0 0, L_0x2c0e280; 1 drivers -v0x2b85d80_0 .net "nXor", 0 0, L_0x2c0dcf0; 1 drivers -L_0x2c0e400 .part v0x2bc78e0_0, 2, 1; -L_0x2c0e9d0 .part v0x2bc78e0_0, 0, 1; -S_0x2b85200 .scope module, "mux0" "TwoInMux" 3 83, 3 8, S_0x2b84bc0; - .timescale -9 -12; -L_0x2c0df60/d .functor NOT 1, L_0x2c0e400, C4<0>, C4<0>, C4<0>; -L_0x2c0df60 .delay (10000,10000,10000) L_0x2c0df60/d; -L_0x2c0e020/d .functor AND 1, L_0x2c0de00, L_0x2c0df60, C4<1>, C4<1>; -L_0x2c0e020 .delay (20000,20000,20000) L_0x2c0e020/d; -L_0x2c0e130/d .functor AND 1, L_0x2c0d9a0, L_0x2c0e400, C4<1>, C4<1>; -L_0x2c0e130 .delay (20000,20000,20000) L_0x2c0e130/d; -L_0x2c0e280/d .functor OR 1, L_0x2c0e020, L_0x2c0e130, C4<0>, C4<0>; -L_0x2c0e280 .delay (20000,20000,20000) L_0x2c0e280/d; -v0x2b852f0_0 .net "S", 0 0, L_0x2c0e400; 1 drivers -v0x2b853b0_0 .alias "in0", 0 0, v0x2b85a40_0; -v0x2b85450_0 .alias "in1", 0 0, v0x2b858b0_0; -v0x2b854f0_0 .net "nS", 0 0, L_0x2c0df60; 1 drivers -v0x2b85570_0 .net "out0", 0 0, L_0x2c0e020; 1 drivers -v0x2b85610_0 .net "out1", 0 0, L_0x2c0e130; 1 drivers -v0x2b856f0_0 .alias "outfinal", 0 0, v0x2b85cb0_0; -S_0x2b84cb0 .scope module, "mux1" "TwoInMux" 3 84, 3 8, S_0x2b84bc0; - .timescale -9 -12; -L_0x2c0e4a0/d .functor NOT 1, L_0x2c0e9d0, C4<0>, C4<0>, C4<0>; -L_0x2c0e4a0 .delay (10000,10000,10000) L_0x2c0e4a0/d; -L_0x2c0e560/d .functor AND 1, L_0x2c0e280, L_0x2c0e4a0, C4<1>, C4<1>; -L_0x2c0e560 .delay (20000,20000,20000) L_0x2c0e560/d; -L_0x2c0e6b0/d .functor AND 1, L_0x2c0daa0, L_0x2c0e9d0, C4<1>, C4<1>; -L_0x2c0e6b0 .delay (20000,20000,20000) L_0x2c0e6b0/d; -L_0x2c0e800/d .functor OR 1, L_0x2c0e560, L_0x2c0e6b0, C4<0>, C4<0>; -L_0x2c0e800 .delay (20000,20000,20000) L_0x2c0e800/d; -v0x2b84da0_0 .net "S", 0 0, L_0x2c0e9d0; 1 drivers -v0x2b84e20_0 .alias "in0", 0 0, v0x2b85cb0_0; -v0x2b84ec0_0 .alias "in1", 0 0, v0x2b85960_0; -v0x2b84f60_0 .net "nS", 0 0, L_0x2c0e4a0; 1 drivers -v0x2b84fe0_0 .net "out0", 0 0, L_0x2c0e560; 1 drivers -v0x2b85080_0 .net "out1", 0 0, L_0x2c0e6b0; 1 drivers -v0x2b85160_0 .alias "outfinal", 0 0, v0x2b85c30_0; -S_0x2b836c0 .scope generate, "orbits[5]" "orbits[5]" 3 196, 3 196, S_0x2b62fd0; - .timescale -9 -12; -P_0x2b833d8 .param/l "i" 3 196, +C4<0101>; -S_0x2b837f0 .scope module, "attempt" "OrNorXor" 3 198, 3 64, S_0x2b836c0; - .timescale -9 -12; -L_0x2c0eb10/d .functor NOR 1, L_0x2c0ff20, L_0x2c0ffc0, C4<0>, C4<0>; -L_0x2c0eb10 .delay (10000,10000,10000) L_0x2c0eb10/d; -L_0x2c0ed60/d .functor NOT 1, L_0x2c0eb10, C4<0>, C4<0>, C4<0>; -L_0x2c0ed60 .delay (10000,10000,10000) L_0x2c0ed60/d; -L_0x2c0ee90/d .functor NAND 1, L_0x2c0ff20, L_0x2c0ffc0, C4<1>, C4<1>; -L_0x2c0ee90 .delay (10000,10000,10000) L_0x2c0ee90/d; -L_0x2c0eff0/d .functor NAND 1, L_0x2c0ee90, L_0x2c0ed60, C4<1>, C4<1>; -L_0x2c0eff0 .delay (10000,10000,10000) L_0x2c0eff0/d; -L_0x2c0f100/d .functor NOT 1, L_0x2c0eff0, C4<0>, C4<0>, C4<0>; -L_0x2c0f100 .delay (10000,10000,10000) L_0x2c0f100/d; -v0x2b843a0_0 .net "A", 0 0, L_0x2c0ff20; 1 drivers -v0x2b84440_0 .net "AnandB", 0 0, L_0x2c0ee90; 1 drivers -v0x2b844e0_0 .net "AnorB", 0 0, L_0x2c0eb10; 1 drivers -v0x2b84590_0 .net "AorB", 0 0, L_0x2c0ed60; 1 drivers -v0x2b84670_0 .net "AxorB", 0 0, L_0x2c0f100; 1 drivers -v0x2b84720_0 .net "B", 0 0, L_0x2c0ffc0; 1 drivers -v0x2b847e0_0 .alias "Command", 2 0, v0x2bc67a0_0; -v0x2b84860_0 .net "OrNorXorOut", 0 0, L_0x2c0fb00; 1 drivers -v0x2b848e0_0 .net "XorNor", 0 0, L_0x2c0f580; 1 drivers -v0x2b849b0_0 .net "nXor", 0 0, L_0x2c0eff0; 1 drivers -L_0x2c0f700 .part v0x2bc78e0_0, 2, 1; -L_0x2c0fcd0 .part v0x2bc78e0_0, 0, 1; -S_0x2b83e30 .scope module, "mux0" "TwoInMux" 3 83, 3 8, S_0x2b837f0; - .timescale -9 -12; -L_0x2c0f260/d .functor NOT 1, L_0x2c0f700, C4<0>, C4<0>, C4<0>; -L_0x2c0f260 .delay (10000,10000,10000) L_0x2c0f260/d; -L_0x2c0f320/d .functor AND 1, L_0x2c0f100, L_0x2c0f260, C4<1>, C4<1>; -L_0x2c0f320 .delay (20000,20000,20000) L_0x2c0f320/d; -L_0x2c0f430/d .functor AND 1, L_0x2c0eb10, L_0x2c0f700, C4<1>, C4<1>; -L_0x2c0f430 .delay (20000,20000,20000) L_0x2c0f430/d; -L_0x2c0f580/d .functor OR 1, L_0x2c0f320, L_0x2c0f430, C4<0>, C4<0>; -L_0x2c0f580 .delay (20000,20000,20000) L_0x2c0f580/d; -v0x2b83f20_0 .net "S", 0 0, L_0x2c0f700; 1 drivers -v0x2b83fe0_0 .alias "in0", 0 0, v0x2b84670_0; -v0x2b84080_0 .alias "in1", 0 0, v0x2b844e0_0; -v0x2b84120_0 .net "nS", 0 0, L_0x2c0f260; 1 drivers -v0x2b841a0_0 .net "out0", 0 0, L_0x2c0f320; 1 drivers -v0x2b84240_0 .net "out1", 0 0, L_0x2c0f430; 1 drivers -v0x2b84320_0 .alias "outfinal", 0 0, v0x2b848e0_0; -S_0x2b838e0 .scope module, "mux1" "TwoInMux" 3 84, 3 8, S_0x2b837f0; - .timescale -9 -12; -L_0x2c0f7a0/d .functor NOT 1, L_0x2c0fcd0, C4<0>, C4<0>, C4<0>; -L_0x2c0f7a0 .delay (10000,10000,10000) L_0x2c0f7a0/d; -L_0x2c0f860/d .functor AND 1, L_0x2c0f580, L_0x2c0f7a0, C4<1>, C4<1>; -L_0x2c0f860 .delay (20000,20000,20000) L_0x2c0f860/d; -L_0x2c0f9b0/d .functor AND 1, L_0x2c0ed60, L_0x2c0fcd0, C4<1>, C4<1>; -L_0x2c0f9b0 .delay (20000,20000,20000) L_0x2c0f9b0/d; -L_0x2c0fb00/d .functor OR 1, L_0x2c0f860, L_0x2c0f9b0, C4<0>, C4<0>; -L_0x2c0fb00 .delay (20000,20000,20000) L_0x2c0fb00/d; -v0x2b839d0_0 .net "S", 0 0, L_0x2c0fcd0; 1 drivers -v0x2b83a50_0 .alias "in0", 0 0, v0x2b848e0_0; -v0x2b83af0_0 .alias "in1", 0 0, v0x2b84590_0; -v0x2b83b90_0 .net "nS", 0 0, L_0x2c0f7a0; 1 drivers -v0x2b83c10_0 .net "out0", 0 0, L_0x2c0f860; 1 drivers -v0x2b83cb0_0 .net "out1", 0 0, L_0x2c0f9b0; 1 drivers -v0x2b83d90_0 .alias "outfinal", 0 0, v0x2b84860_0; -S_0x2b822f0 .scope generate, "orbits[6]" "orbits[6]" 3 196, 3 196, S_0x2b62fd0; - .timescale -9 -12; -P_0x2b82008 .param/l "i" 3 196, +C4<0110>; -S_0x2b82420 .scope module, "attempt" "OrNorXor" 3 198, 3 64, S_0x2b822f0; - .timescale -9 -12; -L_0x2c10060/d .functor NOR 1, L_0x2c11200, L_0x2c112a0, C4<0>, C4<0>; -L_0x2c10060 .delay (10000,10000,10000) L_0x2c10060/d; -L_0x2c10150/d .functor NOT 1, L_0x2c10060, C4<0>, C4<0>, C4<0>; -L_0x2c10150 .delay (10000,10000,10000) L_0x2c10150/d; -L_0x2c10280/d .functor NAND 1, L_0x2c11200, L_0x2c112a0, C4<1>, C4<1>; -L_0x2c10280 .delay (10000,10000,10000) L_0x2c10280/d; -L_0x2c103e0/d .functor NAND 1, L_0x2c10280, L_0x2c10150, C4<1>, C4<1>; -L_0x2c103e0 .delay (10000,10000,10000) L_0x2c103e0/d; -L_0x2c104f0/d .functor NOT 1, L_0x2c103e0, C4<0>, C4<0>, C4<0>; -L_0x2c104f0 .delay (10000,10000,10000) L_0x2c104f0/d; -v0x2b82fd0_0 .net "A", 0 0, L_0x2c11200; 1 drivers -v0x2b83070_0 .net "AnandB", 0 0, L_0x2c10280; 1 drivers -v0x2b83110_0 .net "AnorB", 0 0, L_0x2c10060; 1 drivers -v0x2b831c0_0 .net "AorB", 0 0, L_0x2c10150; 1 drivers -v0x2b832a0_0 .net "AxorB", 0 0, L_0x2c104f0; 1 drivers -v0x2b83350_0 .net "B", 0 0, L_0x2c112a0; 1 drivers -v0x2b83410_0 .alias "Command", 2 0, v0x2bc67a0_0; -v0x2b83490_0 .net "OrNorXorOut", 0 0, L_0x2c10ef0; 1 drivers -v0x2b83510_0 .net "XorNor", 0 0, L_0x2c10970; 1 drivers -v0x2b835e0_0 .net "nXor", 0 0, L_0x2c103e0; 1 drivers -L_0x2c10af0 .part v0x2bc78e0_0, 2, 1; -L_0x2c110c0 .part v0x2bc78e0_0, 0, 1; -S_0x2b82a60 .scope module, "mux0" "TwoInMux" 3 83, 3 8, S_0x2b82420; - .timescale -9 -12; -L_0x2c10650/d .functor NOT 1, L_0x2c10af0, C4<0>, C4<0>, C4<0>; -L_0x2c10650 .delay (10000,10000,10000) L_0x2c10650/d; -L_0x2c10710/d .functor AND 1, L_0x2c104f0, L_0x2c10650, C4<1>, C4<1>; -L_0x2c10710 .delay (20000,20000,20000) L_0x2c10710/d; -L_0x2c10820/d .functor AND 1, L_0x2c10060, L_0x2c10af0, C4<1>, C4<1>; -L_0x2c10820 .delay (20000,20000,20000) L_0x2c10820/d; -L_0x2c10970/d .functor OR 1, L_0x2c10710, L_0x2c10820, C4<0>, C4<0>; -L_0x2c10970 .delay (20000,20000,20000) L_0x2c10970/d; -v0x2b82b50_0 .net "S", 0 0, L_0x2c10af0; 1 drivers -v0x2b82c10_0 .alias "in0", 0 0, v0x2b832a0_0; -v0x2b82cb0_0 .alias "in1", 0 0, v0x2b83110_0; -v0x2b82d50_0 .net "nS", 0 0, L_0x2c10650; 1 drivers -v0x2b82dd0_0 .net "out0", 0 0, L_0x2c10710; 1 drivers -v0x2b82e70_0 .net "out1", 0 0, L_0x2c10820; 1 drivers -v0x2b82f50_0 .alias "outfinal", 0 0, v0x2b83510_0; -S_0x2b82510 .scope module, "mux1" "TwoInMux" 3 84, 3 8, S_0x2b82420; - .timescale -9 -12; -L_0x2c10b90/d .functor NOT 1, L_0x2c110c0, C4<0>, C4<0>, C4<0>; -L_0x2c10b90 .delay (10000,10000,10000) L_0x2c10b90/d; -L_0x2c10c50/d .functor AND 1, L_0x2c10970, L_0x2c10b90, C4<1>, C4<1>; -L_0x2c10c50 .delay (20000,20000,20000) L_0x2c10c50/d; -L_0x2c10da0/d .functor AND 1, L_0x2c10150, L_0x2c110c0, C4<1>, C4<1>; -L_0x2c10da0 .delay (20000,20000,20000) L_0x2c10da0/d; -L_0x2c10ef0/d .functor OR 1, L_0x2c10c50, L_0x2c10da0, C4<0>, C4<0>; -L_0x2c10ef0 .delay (20000,20000,20000) L_0x2c10ef0/d; -v0x2b82600_0 .net "S", 0 0, L_0x2c110c0; 1 drivers -v0x2b82680_0 .alias "in0", 0 0, v0x2b83510_0; -v0x2b82720_0 .alias "in1", 0 0, v0x2b831c0_0; -v0x2b827c0_0 .net "nS", 0 0, L_0x2c10b90; 1 drivers -v0x2b82840_0 .net "out0", 0 0, L_0x2c10c50; 1 drivers -v0x2b828e0_0 .net "out1", 0 0, L_0x2c10da0; 1 drivers -v0x2b829c0_0 .alias "outfinal", 0 0, v0x2b83490_0; -S_0x2b80f20 .scope generate, "orbits[7]" "orbits[7]" 3 196, 3 196, S_0x2b62fd0; - .timescale -9 -12; -P_0x2b80c38 .param/l "i" 3 196, +C4<0111>; -S_0x2b81050 .scope module, "attempt" "OrNorXor" 3 198, 3 64, S_0x2b80f20; - .timescale -9 -12; -L_0x2c0b3f0/d .functor NOR 1, L_0x2c12500, L_0x2c11340, C4<0>, C4<0>; -L_0x2c0b3f0 .delay (10000,10000,10000) L_0x2c0b3f0/d; -L_0x2c11470/d .functor NOT 1, L_0x2c0b3f0, C4<0>, C4<0>, C4<0>; -L_0x2c11470 .delay (10000,10000,10000) L_0x2c11470/d; -L_0x2c11580/d .functor NAND 1, L_0x2c12500, L_0x2c11340, C4<1>, C4<1>; -L_0x2c11580 .delay (10000,10000,10000) L_0x2c11580/d; -L_0x2c116e0/d .functor NAND 1, L_0x2c11580, L_0x2c11470, C4<1>, C4<1>; -L_0x2c116e0 .delay (10000,10000,10000) L_0x2c116e0/d; -L_0x2c117f0/d .functor NOT 1, L_0x2c116e0, C4<0>, C4<0>, C4<0>; -L_0x2c117f0 .delay (10000,10000,10000) L_0x2c117f0/d; -v0x2b81c00_0 .net "A", 0 0, L_0x2c12500; 1 drivers -v0x2b81ca0_0 .net "AnandB", 0 0, L_0x2c11580; 1 drivers -v0x2b81d40_0 .net "AnorB", 0 0, L_0x2c0b3f0; 1 drivers -v0x2b81df0_0 .net "AorB", 0 0, L_0x2c11470; 1 drivers -v0x2b81ed0_0 .net "AxorB", 0 0, L_0x2c117f0; 1 drivers -v0x2b81f80_0 .net "B", 0 0, L_0x2c11340; 1 drivers -v0x2b82040_0 .alias "Command", 2 0, v0x2bc67a0_0; -v0x2b820c0_0 .net "OrNorXorOut", 0 0, L_0x2c121f0; 1 drivers -v0x2b82140_0 .net "XorNor", 0 0, L_0x2c11c70; 1 drivers -v0x2b82210_0 .net "nXor", 0 0, L_0x2c116e0; 1 drivers -L_0x2c11df0 .part v0x2bc78e0_0, 2, 1; -L_0x2c123c0 .part v0x2bc78e0_0, 0, 1; -S_0x2b81690 .scope module, "mux0" "TwoInMux" 3 83, 3 8, S_0x2b81050; - .timescale -9 -12; -L_0x2c11950/d .functor NOT 1, L_0x2c11df0, C4<0>, C4<0>, C4<0>; -L_0x2c11950 .delay (10000,10000,10000) L_0x2c11950/d; -L_0x2c11a10/d .functor AND 1, L_0x2c117f0, L_0x2c11950, C4<1>, C4<1>; -L_0x2c11a10 .delay (20000,20000,20000) L_0x2c11a10/d; -L_0x2c11b20/d .functor AND 1, L_0x2c0b3f0, L_0x2c11df0, C4<1>, C4<1>; -L_0x2c11b20 .delay (20000,20000,20000) L_0x2c11b20/d; -L_0x2c11c70/d .functor OR 1, L_0x2c11a10, L_0x2c11b20, C4<0>, C4<0>; -L_0x2c11c70 .delay (20000,20000,20000) L_0x2c11c70/d; -v0x2b81780_0 .net "S", 0 0, L_0x2c11df0; 1 drivers -v0x2b81840_0 .alias "in0", 0 0, v0x2b81ed0_0; -v0x2b818e0_0 .alias "in1", 0 0, v0x2b81d40_0; -v0x2b81980_0 .net "nS", 0 0, L_0x2c11950; 1 drivers -v0x2b81a00_0 .net "out0", 0 0, L_0x2c11a10; 1 drivers -v0x2b81aa0_0 .net "out1", 0 0, L_0x2c11b20; 1 drivers -v0x2b81b80_0 .alias "outfinal", 0 0, v0x2b82140_0; -S_0x2b81140 .scope module, "mux1" "TwoInMux" 3 84, 3 8, S_0x2b81050; - .timescale -9 -12; -L_0x2c11e90/d .functor NOT 1, L_0x2c123c0, C4<0>, C4<0>, C4<0>; -L_0x2c11e90 .delay (10000,10000,10000) L_0x2c11e90/d; -L_0x2c11f50/d .functor AND 1, L_0x2c11c70, L_0x2c11e90, C4<1>, C4<1>; -L_0x2c11f50 .delay (20000,20000,20000) L_0x2c11f50/d; -L_0x2c120a0/d .functor AND 1, L_0x2c11470, L_0x2c123c0, C4<1>, C4<1>; -L_0x2c120a0 .delay (20000,20000,20000) L_0x2c120a0/d; -L_0x2c121f0/d .functor OR 1, L_0x2c11f50, L_0x2c120a0, C4<0>, C4<0>; -L_0x2c121f0 .delay (20000,20000,20000) L_0x2c121f0/d; -v0x2b81230_0 .net "S", 0 0, L_0x2c123c0; 1 drivers -v0x2b812b0_0 .alias "in0", 0 0, v0x2b82140_0; -v0x2b81350_0 .alias "in1", 0 0, v0x2b81df0_0; -v0x2b813f0_0 .net "nS", 0 0, L_0x2c11e90; 1 drivers -v0x2b81470_0 .net "out0", 0 0, L_0x2c11f50; 1 drivers -v0x2b81510_0 .net "out1", 0 0, L_0x2c120a0; 1 drivers -v0x2b815f0_0 .alias "outfinal", 0 0, v0x2b820c0_0; -S_0x2b7fb50 .scope generate, "orbits[8]" "orbits[8]" 3 196, 3 196, S_0x2b62fd0; - .timescale -9 -12; -P_0x2b7f868 .param/l "i" 3 196, +C4<01000>; -S_0x2b7fc80 .scope module, "attempt" "OrNorXor" 3 198, 3 64, S_0x2b7fb50; - .timescale -9 -12; -L_0x2c12650/d .functor NOR 1, L_0x2c125a0, L_0x2c138b0, C4<0>, C4<0>; -L_0x2c12650 .delay (10000,10000,10000) L_0x2c12650/d; -L_0x2c12740/d .functor NOT 1, L_0x2c12650, C4<0>, C4<0>, C4<0>; -L_0x2c12740 .delay (10000,10000,10000) L_0x2c12740/d; -L_0x2c12870/d .functor NAND 1, L_0x2c125a0, L_0x2c138b0, C4<1>, C4<1>; -L_0x2c12870 .delay (10000,10000,10000) L_0x2c12870/d; -L_0x2c129d0/d .functor NAND 1, L_0x2c12870, L_0x2c12740, C4<1>, C4<1>; -L_0x2c129d0 .delay (10000,10000,10000) L_0x2c129d0/d; -L_0x2c12ae0/d .functor NOT 1, L_0x2c129d0, C4<0>, C4<0>, C4<0>; -L_0x2c12ae0 .delay (10000,10000,10000) L_0x2c12ae0/d; -v0x2b80830_0 .net "A", 0 0, L_0x2c125a0; 1 drivers -v0x2b808d0_0 .net "AnandB", 0 0, L_0x2c12870; 1 drivers -v0x2b80970_0 .net "AnorB", 0 0, L_0x2c12650; 1 drivers -v0x2b80a20_0 .net "AorB", 0 0, L_0x2c12740; 1 drivers -v0x2b80b00_0 .net "AxorB", 0 0, L_0x2c12ae0; 1 drivers -v0x2b80bb0_0 .net "B", 0 0, L_0x2c138b0; 1 drivers -v0x2b80c70_0 .alias "Command", 2 0, v0x2bc67a0_0; -v0x2b80cf0_0 .net "OrNorXorOut", 0 0, L_0x2c134e0; 1 drivers -v0x2b80d70_0 .net "XorNor", 0 0, L_0x2c12f60; 1 drivers -v0x2b80e40_0 .net "nXor", 0 0, L_0x2c129d0; 1 drivers -L_0x2c130e0 .part v0x2bc78e0_0, 2, 1; -L_0x2c136b0 .part v0x2bc78e0_0, 0, 1; -S_0x2b802c0 .scope module, "mux0" "TwoInMux" 3 83, 3 8, S_0x2b7fc80; - .timescale -9 -12; -L_0x2c12c40/d .functor NOT 1, L_0x2c130e0, C4<0>, C4<0>, C4<0>; -L_0x2c12c40 .delay (10000,10000,10000) L_0x2c12c40/d; -L_0x2c12d00/d .functor AND 1, L_0x2c12ae0, L_0x2c12c40, C4<1>, C4<1>; -L_0x2c12d00 .delay (20000,20000,20000) L_0x2c12d00/d; -L_0x2c12e10/d .functor AND 1, L_0x2c12650, L_0x2c130e0, C4<1>, C4<1>; -L_0x2c12e10 .delay (20000,20000,20000) L_0x2c12e10/d; -L_0x2c12f60/d .functor OR 1, L_0x2c12d00, L_0x2c12e10, C4<0>, C4<0>; -L_0x2c12f60 .delay (20000,20000,20000) L_0x2c12f60/d; -v0x2b803b0_0 .net "S", 0 0, L_0x2c130e0; 1 drivers -v0x2b80470_0 .alias "in0", 0 0, v0x2b80b00_0; -v0x2b80510_0 .alias "in1", 0 0, v0x2b80970_0; -v0x2b805b0_0 .net "nS", 0 0, L_0x2c12c40; 1 drivers -v0x2b80630_0 .net "out0", 0 0, L_0x2c12d00; 1 drivers -v0x2b806d0_0 .net "out1", 0 0, L_0x2c12e10; 1 drivers -v0x2b807b0_0 .alias "outfinal", 0 0, v0x2b80d70_0; -S_0x2b7fd70 .scope module, "mux1" "TwoInMux" 3 84, 3 8, S_0x2b7fc80; - .timescale -9 -12; -L_0x2c13180/d .functor NOT 1, L_0x2c136b0, C4<0>, C4<0>, C4<0>; -L_0x2c13180 .delay (10000,10000,10000) L_0x2c13180/d; -L_0x2c13240/d .functor AND 1, L_0x2c12f60, L_0x2c13180, C4<1>, C4<1>; -L_0x2c13240 .delay (20000,20000,20000) L_0x2c13240/d; -L_0x2c13390/d .functor AND 1, L_0x2c12740, L_0x2c136b0, C4<1>, C4<1>; -L_0x2c13390 .delay (20000,20000,20000) L_0x2c13390/d; -L_0x2c134e0/d .functor OR 1, L_0x2c13240, L_0x2c13390, C4<0>, C4<0>; -L_0x2c134e0 .delay (20000,20000,20000) L_0x2c134e0/d; -v0x2b7fe60_0 .net "S", 0 0, L_0x2c136b0; 1 drivers -v0x2b7fee0_0 .alias "in0", 0 0, v0x2b80d70_0; -v0x2b7ff80_0 .alias "in1", 0 0, v0x2b80a20_0; -v0x2b80020_0 .net "nS", 0 0, L_0x2c13180; 1 drivers -v0x2b800a0_0 .net "out0", 0 0, L_0x2c13240; 1 drivers -v0x2b80140_0 .net "out1", 0 0, L_0x2c13390; 1 drivers -v0x2b80220_0 .alias "outfinal", 0 0, v0x2b80cf0_0; -S_0x2b7e780 .scope generate, "orbits[9]" "orbits[9]" 3 196, 3 196, S_0x2b62fd0; - .timescale -9 -12; -P_0x2b7e498 .param/l "i" 3 196, +C4<01001>; -S_0x2b7e8b0 .scope module, "attempt" "OrNorXor" 3 198, 3 64, S_0x2b7e780; - .timescale -9 -12; -L_0x2c137f0/d .functor NOR 1, L_0x2c14b00, L_0x2c13950, C4<0>, C4<0>; -L_0x2c137f0 .delay (10000,10000,10000) L_0x2c137f0/d; -L_0x2c13a70/d .functor NOT 1, L_0x2c137f0, C4<0>, C4<0>, C4<0>; -L_0x2c13a70 .delay (10000,10000,10000) L_0x2c13a70/d; -L_0x2c13b80/d .functor NAND 1, L_0x2c14b00, L_0x2c13950, C4<1>, C4<1>; -L_0x2c13b80 .delay (10000,10000,10000) L_0x2c13b80/d; -L_0x2c13ce0/d .functor NAND 1, L_0x2c13b80, L_0x2c13a70, C4<1>, C4<1>; -L_0x2c13ce0 .delay (10000,10000,10000) L_0x2c13ce0/d; -L_0x2c13df0/d .functor NOT 1, L_0x2c13ce0, C4<0>, C4<0>, C4<0>; -L_0x2c13df0 .delay (10000,10000,10000) L_0x2c13df0/d; -v0x2b7f460_0 .net "A", 0 0, L_0x2c14b00; 1 drivers -v0x2b7f500_0 .net "AnandB", 0 0, L_0x2c13b80; 1 drivers -v0x2b7f5a0_0 .net "AnorB", 0 0, L_0x2c137f0; 1 drivers -v0x2b7f650_0 .net "AorB", 0 0, L_0x2c13a70; 1 drivers -v0x2b7f730_0 .net "AxorB", 0 0, L_0x2c13df0; 1 drivers -v0x2b7f7e0_0 .net "B", 0 0, L_0x2c13950; 1 drivers -v0x2b7f8a0_0 .alias "Command", 2 0, v0x2bc67a0_0; -v0x2b7f920_0 .net "OrNorXorOut", 0 0, L_0x2c147f0; 1 drivers -v0x2b7f9a0_0 .net "XorNor", 0 0, L_0x2c14270; 1 drivers -v0x2b7fa70_0 .net "nXor", 0 0, L_0x2c13ce0; 1 drivers -L_0x2c143f0 .part v0x2bc78e0_0, 2, 1; -L_0x2c149c0 .part v0x2bc78e0_0, 0, 1; -S_0x2b7eef0 .scope module, "mux0" "TwoInMux" 3 83, 3 8, S_0x2b7e8b0; - .timescale -9 -12; -L_0x2c13f50/d .functor NOT 1, L_0x2c143f0, C4<0>, C4<0>, C4<0>; -L_0x2c13f50 .delay (10000,10000,10000) L_0x2c13f50/d; -L_0x2c14010/d .functor AND 1, L_0x2c13df0, L_0x2c13f50, C4<1>, C4<1>; -L_0x2c14010 .delay (20000,20000,20000) L_0x2c14010/d; -L_0x2c14120/d .functor AND 1, L_0x2c137f0, L_0x2c143f0, C4<1>, C4<1>; -L_0x2c14120 .delay (20000,20000,20000) L_0x2c14120/d; -L_0x2c14270/d .functor OR 1, L_0x2c14010, L_0x2c14120, C4<0>, C4<0>; -L_0x2c14270 .delay (20000,20000,20000) L_0x2c14270/d; -v0x2b7efe0_0 .net "S", 0 0, L_0x2c143f0; 1 drivers -v0x2b7f0a0_0 .alias "in0", 0 0, v0x2b7f730_0; -v0x2b7f140_0 .alias "in1", 0 0, v0x2b7f5a0_0; -v0x2b7f1e0_0 .net "nS", 0 0, L_0x2c13f50; 1 drivers -v0x2b7f260_0 .net "out0", 0 0, L_0x2c14010; 1 drivers -v0x2b7f300_0 .net "out1", 0 0, L_0x2c14120; 1 drivers -v0x2b7f3e0_0 .alias "outfinal", 0 0, v0x2b7f9a0_0; -S_0x2b7e9a0 .scope module, "mux1" "TwoInMux" 3 84, 3 8, S_0x2b7e8b0; - .timescale -9 -12; -L_0x2c14490/d .functor NOT 1, L_0x2c149c0, C4<0>, C4<0>, C4<0>; -L_0x2c14490 .delay (10000,10000,10000) L_0x2c14490/d; -L_0x2c14550/d .functor AND 1, L_0x2c14270, L_0x2c14490, C4<1>, C4<1>; -L_0x2c14550 .delay (20000,20000,20000) L_0x2c14550/d; -L_0x2c146a0/d .functor AND 1, L_0x2c13a70, L_0x2c149c0, C4<1>, C4<1>; -L_0x2c146a0 .delay (20000,20000,20000) L_0x2c146a0/d; -L_0x2c147f0/d .functor OR 1, L_0x2c14550, L_0x2c146a0, C4<0>, C4<0>; -L_0x2c147f0 .delay (20000,20000,20000) L_0x2c147f0/d; -v0x2b7ea90_0 .net "S", 0 0, L_0x2c149c0; 1 drivers -v0x2b7eb10_0 .alias "in0", 0 0, v0x2b7f9a0_0; -v0x2b7ebb0_0 .alias "in1", 0 0, v0x2b7f650_0; -v0x2b7ec50_0 .net "nS", 0 0, L_0x2c14490; 1 drivers -v0x2b7ecd0_0 .net "out0", 0 0, L_0x2c14550; 1 drivers -v0x2b7ed70_0 .net "out1", 0 0, L_0x2c146a0; 1 drivers -v0x2b7ee50_0 .alias "outfinal", 0 0, v0x2b7f920_0; -S_0x2b7d3b0 .scope generate, "orbits[10]" "orbits[10]" 3 196, 3 196, S_0x2b62fd0; - .timescale -9 -12; -P_0x2b7d0c8 .param/l "i" 3 196, +C4<01010>; -S_0x2b7d4e0 .scope module, "attempt" "OrNorXor" 3 198, 3 64, S_0x2b7d3b0; - .timescale -9 -12; -L_0x2c14c80/d .functor NOR 1, L_0x2c14ba0, L_0x2c15ef0, C4<0>, C4<0>; -L_0x2c14c80 .delay (10000,10000,10000) L_0x2c14c80/d; -L_0x2c14d70/d .functor NOT 1, L_0x2c14c80, C4<0>, C4<0>, C4<0>; -L_0x2c14d70 .delay (10000,10000,10000) L_0x2c14d70/d; -L_0x2c14e80/d .functor NAND 1, L_0x2c14ba0, L_0x2c15ef0, C4<1>, C4<1>; -L_0x2c14e80 .delay (10000,10000,10000) L_0x2c14e80/d; -L_0x2c14fe0/d .functor NAND 1, L_0x2c14e80, L_0x2c14d70, C4<1>, C4<1>; -L_0x2c14fe0 .delay (10000,10000,10000) L_0x2c14fe0/d; -L_0x2c150f0/d .functor NOT 1, L_0x2c14fe0, C4<0>, C4<0>, C4<0>; -L_0x2c150f0 .delay (10000,10000,10000) L_0x2c150f0/d; -v0x2b7e090_0 .net "A", 0 0, L_0x2c14ba0; 1 drivers -v0x2b7e130_0 .net "AnandB", 0 0, L_0x2c14e80; 1 drivers -v0x2b7e1d0_0 .net "AnorB", 0 0, L_0x2c14c80; 1 drivers -v0x2b7e280_0 .net "AorB", 0 0, L_0x2c14d70; 1 drivers -v0x2b7e360_0 .net "AxorB", 0 0, L_0x2c150f0; 1 drivers -v0x2b7e410_0 .net "B", 0 0, L_0x2c15ef0; 1 drivers -v0x2b7e4d0_0 .alias "Command", 2 0, v0x2bc67a0_0; -v0x2b7e550_0 .net "OrNorXorOut", 0 0, L_0x2c15af0; 1 drivers -v0x2b7e5d0_0 .net "XorNor", 0 0, L_0x2c15570; 1 drivers -v0x2b7e6a0_0 .net "nXor", 0 0, L_0x2c14fe0; 1 drivers -L_0x2c156f0 .part v0x2bc78e0_0, 2, 1; -L_0x2c15cc0 .part v0x2bc78e0_0, 0, 1; -S_0x2b7db20 .scope module, "mux0" "TwoInMux" 3 83, 3 8, S_0x2b7d4e0; - .timescale -9 -12; -L_0x2c15250/d .functor NOT 1, L_0x2c156f0, C4<0>, C4<0>, C4<0>; -L_0x2c15250 .delay (10000,10000,10000) L_0x2c15250/d; -L_0x2c15310/d .functor AND 1, L_0x2c150f0, L_0x2c15250, C4<1>, C4<1>; -L_0x2c15310 .delay (20000,20000,20000) L_0x2c15310/d; -L_0x2c15420/d .functor AND 1, L_0x2c14c80, L_0x2c156f0, C4<1>, C4<1>; -L_0x2c15420 .delay (20000,20000,20000) L_0x2c15420/d; -L_0x2c15570/d .functor OR 1, L_0x2c15310, L_0x2c15420, C4<0>, C4<0>; -L_0x2c15570 .delay (20000,20000,20000) L_0x2c15570/d; -v0x2b7dc10_0 .net "S", 0 0, L_0x2c156f0; 1 drivers -v0x2b7dcd0_0 .alias "in0", 0 0, v0x2b7e360_0; -v0x2b7dd70_0 .alias "in1", 0 0, v0x2b7e1d0_0; -v0x2b7de10_0 .net "nS", 0 0, L_0x2c15250; 1 drivers -v0x2b7de90_0 .net "out0", 0 0, L_0x2c15310; 1 drivers -v0x2b7df30_0 .net "out1", 0 0, L_0x2c15420; 1 drivers -v0x2b7e010_0 .alias "outfinal", 0 0, v0x2b7e5d0_0; -S_0x2b7d5d0 .scope module, "mux1" "TwoInMux" 3 84, 3 8, S_0x2b7d4e0; - .timescale -9 -12; -L_0x2c15790/d .functor NOT 1, L_0x2c15cc0, C4<0>, C4<0>, C4<0>; -L_0x2c15790 .delay (10000,10000,10000) L_0x2c15790/d; -L_0x2c15850/d .functor AND 1, L_0x2c15570, L_0x2c15790, C4<1>, C4<1>; -L_0x2c15850 .delay (20000,20000,20000) L_0x2c15850/d; -L_0x2c159a0/d .functor AND 1, L_0x2c14d70, L_0x2c15cc0, C4<1>, C4<1>; -L_0x2c159a0 .delay (20000,20000,20000) L_0x2c159a0/d; -L_0x2c15af0/d .functor OR 1, L_0x2c15850, L_0x2c159a0, C4<0>, C4<0>; -L_0x2c15af0 .delay (20000,20000,20000) L_0x2c15af0/d; -v0x2b7d6c0_0 .net "S", 0 0, L_0x2c15cc0; 1 drivers -v0x2b7d740_0 .alias "in0", 0 0, v0x2b7e5d0_0; -v0x2b7d7e0_0 .alias "in1", 0 0, v0x2b7e280_0; -v0x2b7d880_0 .net "nS", 0 0, L_0x2c15790; 1 drivers -v0x2b7d900_0 .net "out0", 0 0, L_0x2c15850; 1 drivers -v0x2b7d9a0_0 .net "out1", 0 0, L_0x2c159a0; 1 drivers -v0x2b7da80_0 .alias "outfinal", 0 0, v0x2b7e550_0; -S_0x2b7bfe0 .scope generate, "orbits[11]" "orbits[11]" 3 196, 3 196, S_0x2b62fd0; - .timescale -9 -12; -P_0x2b7bcf8 .param/l "i" 3 196, +C4<01011>; -S_0x2b7c110 .scope module, "attempt" "OrNorXor" 3 198, 3 64, S_0x2b7bfe0; - .timescale -9 -12; -L_0x2c15e00/d .functor NOR 1, L_0x2c17100, L_0x2c15f90, C4<0>, C4<0>; -L_0x2c15e00 .delay (10000,10000,10000) L_0x2c15e00/d; -L_0x2c16090/d .functor NOT 1, L_0x2c15e00, C4<0>, C4<0>, C4<0>; -L_0x2c16090 .delay (10000,10000,10000) L_0x2c16090/d; -L_0x2c16180/d .functor NAND 1, L_0x2c17100, L_0x2c15f90, C4<1>, C4<1>; -L_0x2c16180 .delay (10000,10000,10000) L_0x2c16180/d; -L_0x2c162e0/d .functor NAND 1, L_0x2c16180, L_0x2c16090, C4<1>, C4<1>; -L_0x2c162e0 .delay (10000,10000,10000) L_0x2c162e0/d; -L_0x2c163f0/d .functor NOT 1, L_0x2c162e0, C4<0>, C4<0>, C4<0>; -L_0x2c163f0 .delay (10000,10000,10000) L_0x2c163f0/d; -v0x2b7ccc0_0 .net "A", 0 0, L_0x2c17100; 1 drivers -v0x2b7cd60_0 .net "AnandB", 0 0, L_0x2c16180; 1 drivers -v0x2b7ce00_0 .net "AnorB", 0 0, L_0x2c15e00; 1 drivers -v0x2b7ceb0_0 .net "AorB", 0 0, L_0x2c16090; 1 drivers -v0x2b7cf90_0 .net "AxorB", 0 0, L_0x2c163f0; 1 drivers -v0x2b7d040_0 .net "B", 0 0, L_0x2c15f90; 1 drivers -v0x2b7d100_0 .alias "Command", 2 0, v0x2bc67a0_0; -v0x2b7d180_0 .net "OrNorXorOut", 0 0, L_0x2c16df0; 1 drivers -v0x2b7d200_0 .net "XorNor", 0 0, L_0x2c16870; 1 drivers -v0x2b7d2d0_0 .net "nXor", 0 0, L_0x2c162e0; 1 drivers -L_0x2c169f0 .part v0x2bc78e0_0, 2, 1; -L_0x2c16fc0 .part v0x2bc78e0_0, 0, 1; -S_0x2b7c750 .scope module, "mux0" "TwoInMux" 3 83, 3 8, S_0x2b7c110; - .timescale -9 -12; -L_0x2c16550/d .functor NOT 1, L_0x2c169f0, C4<0>, C4<0>, C4<0>; -L_0x2c16550 .delay (10000,10000,10000) L_0x2c16550/d; -L_0x2c16610/d .functor AND 1, L_0x2c163f0, L_0x2c16550, C4<1>, C4<1>; -L_0x2c16610 .delay (20000,20000,20000) L_0x2c16610/d; -L_0x2c16720/d .functor AND 1, L_0x2c15e00, L_0x2c169f0, C4<1>, C4<1>; -L_0x2c16720 .delay (20000,20000,20000) L_0x2c16720/d; -L_0x2c16870/d .functor OR 1, L_0x2c16610, L_0x2c16720, C4<0>, C4<0>; -L_0x2c16870 .delay (20000,20000,20000) L_0x2c16870/d; -v0x2b7c840_0 .net "S", 0 0, L_0x2c169f0; 1 drivers -v0x2b7c900_0 .alias "in0", 0 0, v0x2b7cf90_0; -v0x2b7c9a0_0 .alias "in1", 0 0, v0x2b7ce00_0; -v0x2b7ca40_0 .net "nS", 0 0, L_0x2c16550; 1 drivers -v0x2b7cac0_0 .net "out0", 0 0, L_0x2c16610; 1 drivers -v0x2b7cb60_0 .net "out1", 0 0, L_0x2c16720; 1 drivers -v0x2b7cc40_0 .alias "outfinal", 0 0, v0x2b7d200_0; -S_0x2b7c200 .scope module, "mux1" "TwoInMux" 3 84, 3 8, S_0x2b7c110; - .timescale -9 -12; -L_0x2c16a90/d .functor NOT 1, L_0x2c16fc0, C4<0>, C4<0>, C4<0>; -L_0x2c16a90 .delay (10000,10000,10000) L_0x2c16a90/d; -L_0x2c16b50/d .functor AND 1, L_0x2c16870, L_0x2c16a90, C4<1>, C4<1>; -L_0x2c16b50 .delay (20000,20000,20000) L_0x2c16b50/d; -L_0x2c16ca0/d .functor AND 1, L_0x2c16090, L_0x2c16fc0, C4<1>, C4<1>; -L_0x2c16ca0 .delay (20000,20000,20000) L_0x2c16ca0/d; -L_0x2c16df0/d .functor OR 1, L_0x2c16b50, L_0x2c16ca0, C4<0>, C4<0>; -L_0x2c16df0 .delay (20000,20000,20000) L_0x2c16df0/d; -v0x2b7c2f0_0 .net "S", 0 0, L_0x2c16fc0; 1 drivers -v0x2b7c370_0 .alias "in0", 0 0, v0x2b7d200_0; -v0x2b7c410_0 .alias "in1", 0 0, v0x2b7ceb0_0; -v0x2b7c4b0_0 .net "nS", 0 0, L_0x2c16a90; 1 drivers -v0x2b7c530_0 .net "out0", 0 0, L_0x2c16b50; 1 drivers -v0x2b7c5d0_0 .net "out1", 0 0, L_0x2c16ca0; 1 drivers -v0x2b7c6b0_0 .alias "outfinal", 0 0, v0x2b7d180_0; -S_0x2b7ac10 .scope generate, "orbits[12]" "orbits[12]" 3 196, 3 196, S_0x2b62fd0; - .timescale -9 -12; -P_0x2b7a928 .param/l "i" 3 196, +C4<01100>; -S_0x2b7ad40 .scope module, "attempt" "OrNorXor" 3 198, 3 64, S_0x2b7ac10; - .timescale -9 -12; -L_0x2c16030/d .functor NOR 1, L_0x2c171a0, L_0x2c18510, C4<0>, C4<0>; -L_0x2c16030 .delay (10000,10000,10000) L_0x2c16030/d; -L_0x2c17340/d .functor NOT 1, L_0x2c16030, C4<0>, C4<0>, C4<0>; -L_0x2c17340 .delay (10000,10000,10000) L_0x2c17340/d; -L_0x2c17470/d .functor NAND 1, L_0x2c171a0, L_0x2c18510, C4<1>, C4<1>; -L_0x2c17470 .delay (10000,10000,10000) L_0x2c17470/d; -L_0x2c175d0/d .functor NAND 1, L_0x2c17470, L_0x2c17340, C4<1>, C4<1>; -L_0x2c175d0 .delay (10000,10000,10000) L_0x2c175d0/d; -L_0x2c176e0/d .functor NOT 1, L_0x2c175d0, C4<0>, C4<0>, C4<0>; -L_0x2c176e0 .delay (10000,10000,10000) L_0x2c176e0/d; -v0x2b7b8f0_0 .net "A", 0 0, L_0x2c171a0; 1 drivers -v0x2b7b990_0 .net "AnandB", 0 0, L_0x2c17470; 1 drivers -v0x2b7ba30_0 .net "AnorB", 0 0, L_0x2c16030; 1 drivers -v0x2b7bae0_0 .net "AorB", 0 0, L_0x2c17340; 1 drivers -v0x2b7bbc0_0 .net "AxorB", 0 0, L_0x2c176e0; 1 drivers -v0x2b7bc70_0 .net "B", 0 0, L_0x2c18510; 1 drivers -v0x2b7bd30_0 .alias "Command", 2 0, v0x2bc67a0_0; -v0x2b7bdb0_0 .net "OrNorXorOut", 0 0, L_0x2c180e0; 1 drivers -v0x2b7be30_0 .net "XorNor", 0 0, L_0x2c17b60; 1 drivers -v0x2b7bf00_0 .net "nXor", 0 0, L_0x2c175d0; 1 drivers -L_0x2c17ce0 .part v0x2bc78e0_0, 2, 1; -L_0x2c182b0 .part v0x2bc78e0_0, 0, 1; -S_0x2b7b380 .scope module, "mux0" "TwoInMux" 3 83, 3 8, S_0x2b7ad40; - .timescale -9 -12; -L_0x2c17840/d .functor NOT 1, L_0x2c17ce0, C4<0>, C4<0>, C4<0>; -L_0x2c17840 .delay (10000,10000,10000) L_0x2c17840/d; -L_0x2c17900/d .functor AND 1, L_0x2c176e0, L_0x2c17840, C4<1>, C4<1>; -L_0x2c17900 .delay (20000,20000,20000) L_0x2c17900/d; -L_0x2c17a10/d .functor AND 1, L_0x2c16030, L_0x2c17ce0, C4<1>, C4<1>; -L_0x2c17a10 .delay (20000,20000,20000) L_0x2c17a10/d; -L_0x2c17b60/d .functor OR 1, L_0x2c17900, L_0x2c17a10, C4<0>, C4<0>; -L_0x2c17b60 .delay (20000,20000,20000) L_0x2c17b60/d; -v0x2b7b470_0 .net "S", 0 0, L_0x2c17ce0; 1 drivers -v0x2b7b530_0 .alias "in0", 0 0, v0x2b7bbc0_0; -v0x2b7b5d0_0 .alias "in1", 0 0, v0x2b7ba30_0; -v0x2b7b670_0 .net "nS", 0 0, L_0x2c17840; 1 drivers -v0x2b7b6f0_0 .net "out0", 0 0, L_0x2c17900; 1 drivers -v0x2b7b790_0 .net "out1", 0 0, L_0x2c17a10; 1 drivers -v0x2b7b870_0 .alias "outfinal", 0 0, v0x2b7be30_0; -S_0x2b7ae30 .scope module, "mux1" "TwoInMux" 3 84, 3 8, S_0x2b7ad40; - .timescale -9 -12; -L_0x2c17d80/d .functor NOT 1, L_0x2c182b0, C4<0>, C4<0>, C4<0>; -L_0x2c17d80 .delay (10000,10000,10000) L_0x2c17d80/d; -L_0x2c17e40/d .functor AND 1, L_0x2c17b60, L_0x2c17d80, C4<1>, C4<1>; -L_0x2c17e40 .delay (20000,20000,20000) L_0x2c17e40/d; -L_0x2c17f90/d .functor AND 1, L_0x2c17340, L_0x2c182b0, C4<1>, C4<1>; -L_0x2c17f90 .delay (20000,20000,20000) L_0x2c17f90/d; -L_0x2c180e0/d .functor OR 1, L_0x2c17e40, L_0x2c17f90, C4<0>, C4<0>; -L_0x2c180e0 .delay (20000,20000,20000) L_0x2c180e0/d; -v0x2b7af20_0 .net "S", 0 0, L_0x2c182b0; 1 drivers -v0x2b7afa0_0 .alias "in0", 0 0, v0x2b7be30_0; -v0x2b7b040_0 .alias "in1", 0 0, v0x2b7bae0_0; -v0x2b7b0e0_0 .net "nS", 0 0, L_0x2c17d80; 1 drivers -v0x2b7b160_0 .net "out0", 0 0, L_0x2c17e40; 1 drivers -v0x2b7b200_0 .net "out1", 0 0, L_0x2c17f90; 1 drivers -v0x2b7b2e0_0 .alias "outfinal", 0 0, v0x2b7bdb0_0; -S_0x2b79840 .scope generate, "orbits[13]" "orbits[13]" 3 196, 3 196, S_0x2b62fd0; - .timescale -9 -12; -P_0x2b79558 .param/l "i" 3 196, +C4<01101>; -S_0x2b79970 .scope module, "attempt" "OrNorXor" 3 198, 3 64, S_0x2b79840; - .timescale -9 -12; -L_0x2c17240/d .functor NOR 1, L_0x2c0fe10, L_0x2c185b0, C4<0>, C4<0>; -L_0x2c17240 .delay (10000,10000,10000) L_0x2c17240/d; -L_0x2c18480/d .functor NOT 1, L_0x2c17240, C4<0>, C4<0>, C4<0>; -L_0x2c18480 .delay (10000,10000,10000) L_0x2c18480/d; -L_0x2c18790/d .functor NAND 1, L_0x2c0fe10, L_0x2c185b0, C4<1>, C4<1>; -L_0x2c18790 .delay (10000,10000,10000) L_0x2c18790/d; -L_0x2c188f0/d .functor NAND 1, L_0x2c18790, L_0x2c18480, C4<1>, C4<1>; -L_0x2c188f0 .delay (10000,10000,10000) L_0x2c188f0/d; -L_0x2c18a00/d .functor NOT 1, L_0x2c188f0, C4<0>, C4<0>, C4<0>; -L_0x2c18a00 .delay (10000,10000,10000) L_0x2c18a00/d; -v0x2b7a520_0 .net "A", 0 0, L_0x2c0fe10; 1 drivers -v0x2b7a5c0_0 .net "AnandB", 0 0, L_0x2c18790; 1 drivers -v0x2b7a660_0 .net "AnorB", 0 0, L_0x2c17240; 1 drivers -v0x2b7a710_0 .net "AorB", 0 0, L_0x2c18480; 1 drivers -v0x2b7a7f0_0 .net "AxorB", 0 0, L_0x2c18a00; 1 drivers -v0x2b7a8a0_0 .net "B", 0 0, L_0x2c185b0; 1 drivers -v0x2b7a960_0 .alias "Command", 2 0, v0x2bc67a0_0; -v0x2b7a9e0_0 .net "OrNorXorOut", 0 0, L_0x2c19400; 1 drivers -v0x2b7aa60_0 .net "XorNor", 0 0, L_0x2c18e80; 1 drivers -v0x2b7ab30_0 .net "nXor", 0 0, L_0x2c188f0; 1 drivers -L_0x2c19000 .part v0x2bc78e0_0, 2, 1; -L_0x2c195d0 .part v0x2bc78e0_0, 0, 1; -S_0x2b79fb0 .scope module, "mux0" "TwoInMux" 3 83, 3 8, S_0x2b79970; - .timescale -9 -12; -L_0x2c18b60/d .functor NOT 1, L_0x2c19000, C4<0>, C4<0>, C4<0>; -L_0x2c18b60 .delay (10000,10000,10000) L_0x2c18b60/d; -L_0x2c18c20/d .functor AND 1, L_0x2c18a00, L_0x2c18b60, C4<1>, C4<1>; -L_0x2c18c20 .delay (20000,20000,20000) L_0x2c18c20/d; -L_0x2c18d30/d .functor AND 1, L_0x2c17240, L_0x2c19000, C4<1>, C4<1>; -L_0x2c18d30 .delay (20000,20000,20000) L_0x2c18d30/d; -L_0x2c18e80/d .functor OR 1, L_0x2c18c20, L_0x2c18d30, C4<0>, C4<0>; -L_0x2c18e80 .delay (20000,20000,20000) L_0x2c18e80/d; -v0x2b7a0a0_0 .net "S", 0 0, L_0x2c19000; 1 drivers -v0x2b7a160_0 .alias "in0", 0 0, v0x2b7a7f0_0; -v0x2b7a200_0 .alias "in1", 0 0, v0x2b7a660_0; -v0x2b7a2a0_0 .net "nS", 0 0, L_0x2c18b60; 1 drivers -v0x2b7a320_0 .net "out0", 0 0, L_0x2c18c20; 1 drivers -v0x2b7a3c0_0 .net "out1", 0 0, L_0x2c18d30; 1 drivers -v0x2b7a4a0_0 .alias "outfinal", 0 0, v0x2b7aa60_0; -S_0x2b79a60 .scope module, "mux1" "TwoInMux" 3 84, 3 8, S_0x2b79970; - .timescale -9 -12; -L_0x2c190a0/d .functor NOT 1, L_0x2c195d0, C4<0>, C4<0>, C4<0>; -L_0x2c190a0 .delay (10000,10000,10000) L_0x2c190a0/d; -L_0x2c19160/d .functor AND 1, L_0x2c18e80, L_0x2c190a0, C4<1>, C4<1>; -L_0x2c19160 .delay (20000,20000,20000) L_0x2c19160/d; -L_0x2c192b0/d .functor AND 1, L_0x2c18480, L_0x2c195d0, C4<1>, C4<1>; -L_0x2c192b0 .delay (20000,20000,20000) L_0x2c192b0/d; -L_0x2c19400/d .functor OR 1, L_0x2c19160, L_0x2c192b0, C4<0>, C4<0>; -L_0x2c19400 .delay (20000,20000,20000) L_0x2c19400/d; -v0x2b79b50_0 .net "S", 0 0, L_0x2c195d0; 1 drivers -v0x2b79bd0_0 .alias "in0", 0 0, v0x2b7aa60_0; -v0x2b79c70_0 .alias "in1", 0 0, v0x2b7a710_0; -v0x2b79d10_0 .net "nS", 0 0, L_0x2c190a0; 1 drivers -v0x2b79d90_0 .net "out0", 0 0, L_0x2c19160; 1 drivers -v0x2b79e30_0 .net "out1", 0 0, L_0x2c192b0; 1 drivers -v0x2b79f10_0 .alias "outfinal", 0 0, v0x2b7a9e0_0; -S_0x2b78470 .scope generate, "orbits[14]" "orbits[14]" 3 196, 3 196, S_0x2b62fd0; - .timescale -9 -12; -P_0x2b78188 .param/l "i" 3 196, +C4<01110>; -S_0x2b785a0 .scope module, "attempt" "OrNorXor" 3 198, 3 64, S_0x2b78470; - .timescale -9 -12; -L_0x2c18650/d .functor NOR 1, L_0x2c19920, L_0x2c199c0, C4<0>, C4<0>; -L_0x2c18650 .delay (10000,10000,10000) L_0x2c18650/d; -L_0x2c19ab0/d .functor NOT 1, L_0x2c18650, C4<0>, C4<0>, C4<0>; -L_0x2c19ab0 .delay (10000,10000,10000) L_0x2c19ab0/d; -L_0x2c19ba0/d .functor NAND 1, L_0x2c19920, L_0x2c199c0, C4<1>, C4<1>; -L_0x2c19ba0 .delay (10000,10000,10000) L_0x2c19ba0/d; -L_0x2c19d00/d .functor NAND 1, L_0x2c19ba0, L_0x2c19ab0, C4<1>, C4<1>; -L_0x2c19d00 .delay (10000,10000,10000) L_0x2c19d00/d; -L_0x2c19e10/d .functor NOT 1, L_0x2c19d00, C4<0>, C4<0>, C4<0>; -L_0x2c19e10 .delay (10000,10000,10000) L_0x2c19e10/d; -v0x2b79150_0 .net "A", 0 0, L_0x2c19920; 1 drivers -v0x2b791f0_0 .net "AnandB", 0 0, L_0x2c19ba0; 1 drivers -v0x2b79290_0 .net "AnorB", 0 0, L_0x2c18650; 1 drivers -v0x2b79340_0 .net "AorB", 0 0, L_0x2c19ab0; 1 drivers -v0x2b79420_0 .net "AxorB", 0 0, L_0x2c19e10; 1 drivers -v0x2b794d0_0 .net "B", 0 0, L_0x2c199c0; 1 drivers -v0x2b79590_0 .alias "Command", 2 0, v0x2bc67a0_0; -v0x2b79610_0 .net "OrNorXorOut", 0 0, L_0x2c1a810; 1 drivers -v0x2b79690_0 .net "XorNor", 0 0, L_0x2c1a290; 1 drivers -v0x2b79760_0 .net "nXor", 0 0, L_0x2c19d00; 1 drivers -L_0x2c1a410 .part v0x2bc78e0_0, 2, 1; -L_0x2c1a9e0 .part v0x2bc78e0_0, 0, 1; -S_0x2b78be0 .scope module, "mux0" "TwoInMux" 3 83, 3 8, S_0x2b785a0; - .timescale -9 -12; -L_0x2c19f70/d .functor NOT 1, L_0x2c1a410, C4<0>, C4<0>, C4<0>; -L_0x2c19f70 .delay (10000,10000,10000) L_0x2c19f70/d; -L_0x2c1a030/d .functor AND 1, L_0x2c19e10, L_0x2c19f70, C4<1>, C4<1>; -L_0x2c1a030 .delay (20000,20000,20000) L_0x2c1a030/d; -L_0x2c1a140/d .functor AND 1, L_0x2c18650, L_0x2c1a410, C4<1>, C4<1>; -L_0x2c1a140 .delay (20000,20000,20000) L_0x2c1a140/d; -L_0x2c1a290/d .functor OR 1, L_0x2c1a030, L_0x2c1a140, C4<0>, C4<0>; -L_0x2c1a290 .delay (20000,20000,20000) L_0x2c1a290/d; -v0x2b78cd0_0 .net "S", 0 0, L_0x2c1a410; 1 drivers -v0x2b78d90_0 .alias "in0", 0 0, v0x2b79420_0; -v0x2b78e30_0 .alias "in1", 0 0, v0x2b79290_0; -v0x2b78ed0_0 .net "nS", 0 0, L_0x2c19f70; 1 drivers -v0x2b78f50_0 .net "out0", 0 0, L_0x2c1a030; 1 drivers -v0x2b78ff0_0 .net "out1", 0 0, L_0x2c1a140; 1 drivers -v0x2b790d0_0 .alias "outfinal", 0 0, v0x2b79690_0; -S_0x2b78690 .scope module, "mux1" "TwoInMux" 3 84, 3 8, S_0x2b785a0; - .timescale -9 -12; -L_0x2c1a4b0/d .functor NOT 1, L_0x2c1a9e0, C4<0>, C4<0>, C4<0>; -L_0x2c1a4b0 .delay (10000,10000,10000) L_0x2c1a4b0/d; -L_0x2c1a570/d .functor AND 1, L_0x2c1a290, L_0x2c1a4b0, C4<1>, C4<1>; -L_0x2c1a570 .delay (20000,20000,20000) L_0x2c1a570/d; -L_0x2c1a6c0/d .functor AND 1, L_0x2c19ab0, L_0x2c1a9e0, C4<1>, C4<1>; -L_0x2c1a6c0 .delay (20000,20000,20000) L_0x2c1a6c0/d; -L_0x2c1a810/d .functor OR 1, L_0x2c1a570, L_0x2c1a6c0, C4<0>, C4<0>; -L_0x2c1a810 .delay (20000,20000,20000) L_0x2c1a810/d; -v0x2b78780_0 .net "S", 0 0, L_0x2c1a9e0; 1 drivers -v0x2b78800_0 .alias "in0", 0 0, v0x2b79690_0; -v0x2b788a0_0 .alias "in1", 0 0, v0x2b79340_0; -v0x2b78940_0 .net "nS", 0 0, L_0x2c1a4b0; 1 drivers -v0x2b789c0_0 .net "out0", 0 0, L_0x2c1a570; 1 drivers -v0x2b78a60_0 .net "out1", 0 0, L_0x2c1a6c0; 1 drivers -v0x2b78b40_0 .alias "outfinal", 0 0, v0x2b79610_0; -S_0x2b770a0 .scope generate, "orbits[15]" "orbits[15]" 3 196, 3 196, S_0x2b62fd0; - .timescale -9 -12; -P_0x2b76db8 .param/l "i" 3 196, +C4<01111>; -S_0x2b771d0 .scope module, "attempt" "OrNorXor" 3 198, 3 64, S_0x2b770a0; - .timescale -9 -12; -L_0x2c1ac80/d .functor NOR 1, L_0x2c1be20, L_0x2c1ab20, C4<0>, C4<0>; -L_0x2c1ac80 .delay (10000,10000,10000) L_0x2c1ac80/d; -L_0x2c1ad70/d .functor NOT 1, L_0x2c1ac80, C4<0>, C4<0>, C4<0>; -L_0x2c1ad70 .delay (10000,10000,10000) L_0x2c1ad70/d; -L_0x2c1aea0/d .functor NAND 1, L_0x2c1be20, L_0x2c1ab20, C4<1>, C4<1>; -L_0x2c1aea0 .delay (10000,10000,10000) L_0x2c1aea0/d; -L_0x2c1b000/d .functor NAND 1, L_0x2c1aea0, L_0x2c1ad70, C4<1>, C4<1>; -L_0x2c1b000 .delay (10000,10000,10000) L_0x2c1b000/d; -L_0x2c1b110/d .functor NOT 1, L_0x2c1b000, C4<0>, C4<0>, C4<0>; -L_0x2c1b110 .delay (10000,10000,10000) L_0x2c1b110/d; -v0x2b77d80_0 .net "A", 0 0, L_0x2c1be20; 1 drivers -v0x2b77e20_0 .net "AnandB", 0 0, L_0x2c1aea0; 1 drivers -v0x2b77ec0_0 .net "AnorB", 0 0, L_0x2c1ac80; 1 drivers -v0x2b77f70_0 .net "AorB", 0 0, L_0x2c1ad70; 1 drivers -v0x2b78050_0 .net "AxorB", 0 0, L_0x2c1b110; 1 drivers -v0x2b78100_0 .net "B", 0 0, L_0x2c1ab20; 1 drivers -v0x2b781c0_0 .alias "Command", 2 0, v0x2bc67a0_0; -v0x2b78240_0 .net "OrNorXorOut", 0 0, L_0x2c1bb10; 1 drivers -v0x2b782c0_0 .net "XorNor", 0 0, L_0x2c1b590; 1 drivers -v0x2b78390_0 .net "nXor", 0 0, L_0x2c1b000; 1 drivers -L_0x2c1b710 .part v0x2bc78e0_0, 2, 1; -L_0x2c1bce0 .part v0x2bc78e0_0, 0, 1; -S_0x2b77810 .scope module, "mux0" "TwoInMux" 3 83, 3 8, S_0x2b771d0; - .timescale -9 -12; -L_0x2c1b270/d .functor NOT 1, L_0x2c1b710, C4<0>, C4<0>, C4<0>; -L_0x2c1b270 .delay (10000,10000,10000) L_0x2c1b270/d; -L_0x2c1b330/d .functor AND 1, L_0x2c1b110, L_0x2c1b270, C4<1>, C4<1>; -L_0x2c1b330 .delay (20000,20000,20000) L_0x2c1b330/d; -L_0x2c1b440/d .functor AND 1, L_0x2c1ac80, L_0x2c1b710, C4<1>, C4<1>; -L_0x2c1b440 .delay (20000,20000,20000) L_0x2c1b440/d; -L_0x2c1b590/d .functor OR 1, L_0x2c1b330, L_0x2c1b440, C4<0>, C4<0>; -L_0x2c1b590 .delay (20000,20000,20000) L_0x2c1b590/d; -v0x2b77900_0 .net "S", 0 0, L_0x2c1b710; 1 drivers -v0x2b779c0_0 .alias "in0", 0 0, v0x2b78050_0; -v0x2b77a60_0 .alias "in1", 0 0, v0x2b77ec0_0; -v0x2b77b00_0 .net "nS", 0 0, L_0x2c1b270; 1 drivers -v0x2b77b80_0 .net "out0", 0 0, L_0x2c1b330; 1 drivers -v0x2b77c20_0 .net "out1", 0 0, L_0x2c1b440; 1 drivers -v0x2b77d00_0 .alias "outfinal", 0 0, v0x2b782c0_0; -S_0x2b772c0 .scope module, "mux1" "TwoInMux" 3 84, 3 8, S_0x2b771d0; - .timescale -9 -12; -L_0x2c1b7b0/d .functor NOT 1, L_0x2c1bce0, C4<0>, C4<0>, C4<0>; -L_0x2c1b7b0 .delay (10000,10000,10000) L_0x2c1b7b0/d; -L_0x2c1b870/d .functor AND 1, L_0x2c1b590, L_0x2c1b7b0, C4<1>, C4<1>; -L_0x2c1b870 .delay (20000,20000,20000) L_0x2c1b870/d; -L_0x2c1b9c0/d .functor AND 1, L_0x2c1ad70, L_0x2c1bce0, C4<1>, C4<1>; -L_0x2c1b9c0 .delay (20000,20000,20000) L_0x2c1b9c0/d; -L_0x2c1bb10/d .functor OR 1, L_0x2c1b870, L_0x2c1b9c0, C4<0>, C4<0>; -L_0x2c1bb10 .delay (20000,20000,20000) L_0x2c1bb10/d; -v0x2b773b0_0 .net "S", 0 0, L_0x2c1bce0; 1 drivers -v0x2b77430_0 .alias "in0", 0 0, v0x2b782c0_0; -v0x2b774d0_0 .alias "in1", 0 0, v0x2b77f70_0; -v0x2b77570_0 .net "nS", 0 0, L_0x2c1b7b0; 1 drivers -v0x2b775f0_0 .net "out0", 0 0, L_0x2c1b870; 1 drivers -v0x2b77690_0 .net "out1", 0 0, L_0x2c1b9c0; 1 drivers -v0x2b77770_0 .alias "outfinal", 0 0, v0x2b78240_0; -S_0x2b75cd0 .scope generate, "orbits[16]" "orbits[16]" 3 196, 3 196, S_0x2b62fd0; - .timescale -9 -12; -P_0x2b759e8 .param/l "i" 3 196, +C4<010000>; -S_0x2b75e00 .scope module, "attempt" "OrNorXor" 3 198, 3 64, S_0x2b75cd0; - .timescale -9 -12; -L_0x2c1abc0/d .functor NOR 1, L_0x2c1bec0, L_0x2c1bf60, C4<0>, C4<0>; -L_0x2c1abc0 .delay (10000,10000,10000) L_0x2c1abc0/d; -L_0x2c1c080/d .functor NOT 1, L_0x2c1abc0, C4<0>, C4<0>, C4<0>; -L_0x2c1c080 .delay (10000,10000,10000) L_0x2c1c080/d; -L_0x2c1c190/d .functor NAND 1, L_0x2c1bec0, L_0x2c1bf60, C4<1>, C4<1>; -L_0x2c1c190 .delay (10000,10000,10000) L_0x2c1c190/d; -L_0x2c1c2f0/d .functor NAND 1, L_0x2c1c190, L_0x2c1c080, C4<1>, C4<1>; -L_0x2c1c2f0 .delay (10000,10000,10000) L_0x2c1c2f0/d; -L_0x2c1c400/d .functor NOT 1, L_0x2c1c2f0, C4<0>, C4<0>, C4<0>; -L_0x2c1c400 .delay (10000,10000,10000) L_0x2c1c400/d; -v0x2b769b0_0 .net "A", 0 0, L_0x2c1bec0; 1 drivers -v0x2b76a50_0 .net "AnandB", 0 0, L_0x2c1c190; 1 drivers -v0x2b76af0_0 .net "AnorB", 0 0, L_0x2c1abc0; 1 drivers -v0x2b76ba0_0 .net "AorB", 0 0, L_0x2c1c080; 1 drivers -v0x2b76c80_0 .net "AxorB", 0 0, L_0x2c1c400; 1 drivers -v0x2b76d30_0 .net "B", 0 0, L_0x2c1bf60; 1 drivers -v0x2b76df0_0 .alias "Command", 2 0, v0x2bc67a0_0; -v0x2b76e70_0 .net "OrNorXorOut", 0 0, L_0x2c1ce00; 1 drivers -v0x2b76ef0_0 .net "XorNor", 0 0, L_0x2c1c880; 1 drivers -v0x2b76fc0_0 .net "nXor", 0 0, L_0x2c1c2f0; 1 drivers -L_0x2c1ca00 .part v0x2bc78e0_0, 2, 1; -L_0x2c1cfd0 .part v0x2bc78e0_0, 0, 1; -S_0x2b76440 .scope module, "mux0" "TwoInMux" 3 83, 3 8, S_0x2b75e00; - .timescale -9 -12; -L_0x2c1c560/d .functor NOT 1, L_0x2c1ca00, C4<0>, C4<0>, C4<0>; -L_0x2c1c560 .delay (10000,10000,10000) L_0x2c1c560/d; -L_0x2c1c620/d .functor AND 1, L_0x2c1c400, L_0x2c1c560, C4<1>, C4<1>; -L_0x2c1c620 .delay (20000,20000,20000) L_0x2c1c620/d; -L_0x2c1c730/d .functor AND 1, L_0x2c1abc0, L_0x2c1ca00, C4<1>, C4<1>; -L_0x2c1c730 .delay (20000,20000,20000) L_0x2c1c730/d; -L_0x2c1c880/d .functor OR 1, L_0x2c1c620, L_0x2c1c730, C4<0>, C4<0>; -L_0x2c1c880 .delay (20000,20000,20000) L_0x2c1c880/d; -v0x2b76530_0 .net "S", 0 0, L_0x2c1ca00; 1 drivers -v0x2b765f0_0 .alias "in0", 0 0, v0x2b76c80_0; -v0x2b76690_0 .alias "in1", 0 0, v0x2b76af0_0; -v0x2b76730_0 .net "nS", 0 0, L_0x2c1c560; 1 drivers -v0x2b767b0_0 .net "out0", 0 0, L_0x2c1c620; 1 drivers -v0x2b76850_0 .net "out1", 0 0, L_0x2c1c730; 1 drivers -v0x2b76930_0 .alias "outfinal", 0 0, v0x2b76ef0_0; -S_0x2b75ef0 .scope module, "mux1" "TwoInMux" 3 84, 3 8, S_0x2b75e00; - .timescale -9 -12; -L_0x2c1caa0/d .functor NOT 1, L_0x2c1cfd0, C4<0>, C4<0>, C4<0>; -L_0x2c1caa0 .delay (10000,10000,10000) L_0x2c1caa0/d; -L_0x2c1cb60/d .functor AND 1, L_0x2c1c880, L_0x2c1caa0, C4<1>, C4<1>; -L_0x2c1cb60 .delay (20000,20000,20000) L_0x2c1cb60/d; -L_0x2c1ccb0/d .functor AND 1, L_0x2c1c080, L_0x2c1cfd0, C4<1>, C4<1>; -L_0x2c1ccb0 .delay (20000,20000,20000) L_0x2c1ccb0/d; -L_0x2c1ce00/d .functor OR 1, L_0x2c1cb60, L_0x2c1ccb0, C4<0>, C4<0>; -L_0x2c1ce00 .delay (20000,20000,20000) L_0x2c1ce00/d; -v0x2b75fe0_0 .net "S", 0 0, L_0x2c1cfd0; 1 drivers -v0x2b76060_0 .alias "in0", 0 0, v0x2b76ef0_0; -v0x2b76100_0 .alias "in1", 0 0, v0x2b76ba0_0; -v0x2b761a0_0 .net "nS", 0 0, L_0x2c1caa0; 1 drivers -v0x2b76220_0 .net "out0", 0 0, L_0x2c1cb60; 1 drivers -v0x2b762c0_0 .net "out1", 0 0, L_0x2c1ccb0; 1 drivers -v0x2b763a0_0 .alias "outfinal", 0 0, v0x2b76e70_0; -S_0x2b74900 .scope generate, "orbits[17]" "orbits[17]" 3 196, 3 196, S_0x2b62fd0; - .timescale -9 -12; -P_0x2b74618 .param/l "i" 3 196, +C4<010001>; -S_0x2b74a30 .scope module, "attempt" "OrNorXor" 3 198, 3 64, S_0x2b74900; - .timescale -9 -12; -L_0x2c1d2a0/d .functor NOR 1, L_0x2c1e420, L_0x2c1d110, C4<0>, C4<0>; -L_0x2c1d2a0 .delay (10000,10000,10000) L_0x2c1d2a0/d; -L_0x2c1d390/d .functor NOT 1, L_0x2c1d2a0, C4<0>, C4<0>, C4<0>; -L_0x2c1d390 .delay (10000,10000,10000) L_0x2c1d390/d; -L_0x2c1d4a0/d .functor NAND 1, L_0x2c1e420, L_0x2c1d110, C4<1>, C4<1>; -L_0x2c1d4a0 .delay (10000,10000,10000) L_0x2c1d4a0/d; -L_0x2c1d600/d .functor NAND 1, L_0x2c1d4a0, L_0x2c1d390, C4<1>, C4<1>; -L_0x2c1d600 .delay (10000,10000,10000) L_0x2c1d600/d; -L_0x2c1d710/d .functor NOT 1, L_0x2c1d600, C4<0>, C4<0>, C4<0>; -L_0x2c1d710 .delay (10000,10000,10000) L_0x2c1d710/d; -v0x2b755e0_0 .net "A", 0 0, L_0x2c1e420; 1 drivers -v0x2b75680_0 .net "AnandB", 0 0, L_0x2c1d4a0; 1 drivers -v0x2b75720_0 .net "AnorB", 0 0, L_0x2c1d2a0; 1 drivers -v0x2b757d0_0 .net "AorB", 0 0, L_0x2c1d390; 1 drivers -v0x2b758b0_0 .net "AxorB", 0 0, L_0x2c1d710; 1 drivers -v0x2b75960_0 .net "B", 0 0, L_0x2c1d110; 1 drivers -v0x2b75a20_0 .alias "Command", 2 0, v0x2bc67a0_0; -v0x2b75aa0_0 .net "OrNorXorOut", 0 0, L_0x2c1e110; 1 drivers -v0x2b75b20_0 .net "XorNor", 0 0, L_0x2c1db90; 1 drivers -v0x2b75bf0_0 .net "nXor", 0 0, L_0x2c1d600; 1 drivers -L_0x2c1dd10 .part v0x2bc78e0_0, 2, 1; -L_0x2c1e2e0 .part v0x2bc78e0_0, 0, 1; -S_0x2b75070 .scope module, "mux0" "TwoInMux" 3 83, 3 8, S_0x2b74a30; - .timescale -9 -12; -L_0x2c1d870/d .functor NOT 1, L_0x2c1dd10, C4<0>, C4<0>, C4<0>; -L_0x2c1d870 .delay (10000,10000,10000) L_0x2c1d870/d; -L_0x2c1d930/d .functor AND 1, L_0x2c1d710, L_0x2c1d870, C4<1>, C4<1>; -L_0x2c1d930 .delay (20000,20000,20000) L_0x2c1d930/d; -L_0x2c1da40/d .functor AND 1, L_0x2c1d2a0, L_0x2c1dd10, C4<1>, C4<1>; -L_0x2c1da40 .delay (20000,20000,20000) L_0x2c1da40/d; -L_0x2c1db90/d .functor OR 1, L_0x2c1d930, L_0x2c1da40, C4<0>, C4<0>; -L_0x2c1db90 .delay (20000,20000,20000) L_0x2c1db90/d; -v0x2b75160_0 .net "S", 0 0, L_0x2c1dd10; 1 drivers -v0x2b75220_0 .alias "in0", 0 0, v0x2b758b0_0; -v0x2b752c0_0 .alias "in1", 0 0, v0x2b75720_0; -v0x2b75360_0 .net "nS", 0 0, L_0x2c1d870; 1 drivers -v0x2b753e0_0 .net "out0", 0 0, L_0x2c1d930; 1 drivers -v0x2b75480_0 .net "out1", 0 0, L_0x2c1da40; 1 drivers -v0x2b75560_0 .alias "outfinal", 0 0, v0x2b75b20_0; -S_0x2b74b20 .scope module, "mux1" "TwoInMux" 3 84, 3 8, S_0x2b74a30; - .timescale -9 -12; -L_0x2c1ddb0/d .functor NOT 1, L_0x2c1e2e0, C4<0>, C4<0>, C4<0>; -L_0x2c1ddb0 .delay (10000,10000,10000) L_0x2c1ddb0/d; -L_0x2c1de70/d .functor AND 1, L_0x2c1db90, L_0x2c1ddb0, C4<1>, C4<1>; -L_0x2c1de70 .delay (20000,20000,20000) L_0x2c1de70/d; -L_0x2c1dfc0/d .functor AND 1, L_0x2c1d390, L_0x2c1e2e0, C4<1>, C4<1>; -L_0x2c1dfc0 .delay (20000,20000,20000) L_0x2c1dfc0/d; -L_0x2c1e110/d .functor OR 1, L_0x2c1de70, L_0x2c1dfc0, C4<0>, C4<0>; -L_0x2c1e110 .delay (20000,20000,20000) L_0x2c1e110/d; -v0x2b74c10_0 .net "S", 0 0, L_0x2c1e2e0; 1 drivers -v0x2b74c90_0 .alias "in0", 0 0, v0x2b75b20_0; -v0x2b74d30_0 .alias "in1", 0 0, v0x2b757d0_0; -v0x2b74dd0_0 .net "nS", 0 0, L_0x2c1ddb0; 1 drivers -v0x2b74e50_0 .net "out0", 0 0, L_0x2c1de70; 1 drivers -v0x2b74ef0_0 .net "out1", 0 0, L_0x2c1dfc0; 1 drivers -v0x2b74fd0_0 .alias "outfinal", 0 0, v0x2b75aa0_0; -S_0x2b73530 .scope generate, "orbits[18]" "orbits[18]" 3 196, 3 196, S_0x2b62fd0; - .timescale -9 -12; -P_0x2b73248 .param/l "i" 3 196, +C4<010010>; -S_0x2b73660 .scope module, "attempt" "OrNorXor" 3 198, 3 64, S_0x2b73530; - .timescale -9 -12; -L_0x2c1d1b0/d .functor NOR 1, L_0x2c1e4c0, L_0x2c1e560, C4<0>, C4<0>; -L_0x2c1d1b0 .delay (10000,10000,10000) L_0x2c1d1b0/d; -L_0x2c1e660/d .functor NOT 1, L_0x2c1d1b0, C4<0>, C4<0>, C4<0>; -L_0x2c1e660 .delay (10000,10000,10000) L_0x2c1e660/d; -L_0x2c1e790/d .functor NAND 1, L_0x2c1e4c0, L_0x2c1e560, C4<1>, C4<1>; -L_0x2c1e790 .delay (10000,10000,10000) L_0x2c1e790/d; -L_0x2c1e8f0/d .functor NAND 1, L_0x2c1e790, L_0x2c1e660, C4<1>, C4<1>; -L_0x2c1e8f0 .delay (10000,10000,10000) L_0x2c1e8f0/d; -L_0x2c1ea00/d .functor NOT 1, L_0x2c1e8f0, C4<0>, C4<0>, C4<0>; -L_0x2c1ea00 .delay (10000,10000,10000) L_0x2c1ea00/d; -v0x2b74210_0 .net "A", 0 0, L_0x2c1e4c0; 1 drivers -v0x2b742b0_0 .net "AnandB", 0 0, L_0x2c1e790; 1 drivers -v0x2b74350_0 .net "AnorB", 0 0, L_0x2c1d1b0; 1 drivers -v0x2b74400_0 .net "AorB", 0 0, L_0x2c1e660; 1 drivers -v0x2b744e0_0 .net "AxorB", 0 0, L_0x2c1ea00; 1 drivers -v0x2b74590_0 .net "B", 0 0, L_0x2c1e560; 1 drivers -v0x2b74650_0 .alias "Command", 2 0, v0x2bc67a0_0; -v0x2b746d0_0 .net "OrNorXorOut", 0 0, L_0x2c1f400; 1 drivers -v0x2b74750_0 .net "XorNor", 0 0, L_0x2c1ee80; 1 drivers -v0x2b74820_0 .net "nXor", 0 0, L_0x2c1e8f0; 1 drivers -L_0x2c1f000 .part v0x2bc78e0_0, 2, 1; -L_0x2c1f5d0 .part v0x2bc78e0_0, 0, 1; -S_0x2b73ca0 .scope module, "mux0" "TwoInMux" 3 83, 3 8, S_0x2b73660; - .timescale -9 -12; -L_0x2c1eb60/d .functor NOT 1, L_0x2c1f000, C4<0>, C4<0>, C4<0>; -L_0x2c1eb60 .delay (10000,10000,10000) L_0x2c1eb60/d; -L_0x2c1ec20/d .functor AND 1, L_0x2c1ea00, L_0x2c1eb60, C4<1>, C4<1>; -L_0x2c1ec20 .delay (20000,20000,20000) L_0x2c1ec20/d; -L_0x2c1ed30/d .functor AND 1, L_0x2c1d1b0, L_0x2c1f000, C4<1>, C4<1>; -L_0x2c1ed30 .delay (20000,20000,20000) L_0x2c1ed30/d; -L_0x2c1ee80/d .functor OR 1, L_0x2c1ec20, L_0x2c1ed30, C4<0>, C4<0>; -L_0x2c1ee80 .delay (20000,20000,20000) L_0x2c1ee80/d; -v0x2b73d90_0 .net "S", 0 0, L_0x2c1f000; 1 drivers -v0x2b73e50_0 .alias "in0", 0 0, v0x2b744e0_0; -v0x2b73ef0_0 .alias "in1", 0 0, v0x2b74350_0; -v0x2b73f90_0 .net "nS", 0 0, L_0x2c1eb60; 1 drivers -v0x2b74010_0 .net "out0", 0 0, L_0x2c1ec20; 1 drivers -v0x2b740b0_0 .net "out1", 0 0, L_0x2c1ed30; 1 drivers -v0x2b74190_0 .alias "outfinal", 0 0, v0x2b74750_0; -S_0x2b73750 .scope module, "mux1" "TwoInMux" 3 84, 3 8, S_0x2b73660; - .timescale -9 -12; -L_0x2c1f0a0/d .functor NOT 1, L_0x2c1f5d0, C4<0>, C4<0>, C4<0>; -L_0x2c1f0a0 .delay (10000,10000,10000) L_0x2c1f0a0/d; -L_0x2c1f160/d .functor AND 1, L_0x2c1ee80, L_0x2c1f0a0, C4<1>, C4<1>; -L_0x2c1f160 .delay (20000,20000,20000) L_0x2c1f160/d; -L_0x2c1f2b0/d .functor AND 1, L_0x2c1e660, L_0x2c1f5d0, C4<1>, C4<1>; -L_0x2c1f2b0 .delay (20000,20000,20000) L_0x2c1f2b0/d; -L_0x2c1f400/d .functor OR 1, L_0x2c1f160, L_0x2c1f2b0, C4<0>, C4<0>; -L_0x2c1f400 .delay (20000,20000,20000) L_0x2c1f400/d; -v0x2b73840_0 .net "S", 0 0, L_0x2c1f5d0; 1 drivers -v0x2b738c0_0 .alias "in0", 0 0, v0x2b74750_0; -v0x2b73960_0 .alias "in1", 0 0, v0x2b74400_0; -v0x2b73a00_0 .net "nS", 0 0, L_0x2c1f0a0; 1 drivers -v0x2b73a80_0 .net "out0", 0 0, L_0x2c1f160; 1 drivers -v0x2b73b20_0 .net "out1", 0 0, L_0x2c1f2b0; 1 drivers -v0x2b73c00_0 .alias "outfinal", 0 0, v0x2b746d0_0; -S_0x2b72160 .scope generate, "orbits[19]" "orbits[19]" 3 196, 3 196, S_0x2b62fd0; - .timescale -9 -12; -P_0x2b71e78 .param/l "i" 3 196, +C4<010011>; -S_0x2b72290 .scope module, "attempt" "OrNorXor" 3 198, 3 64, S_0x2b72160; - .timescale -9 -12; -L_0x2c1e600/d .functor NOR 1, L_0x2c20a10, L_0x2c1f710, C4<0>, C4<0>; -L_0x2c1e600 .delay (10000,10000,10000) L_0x2c1e600/d; -L_0x2c1f960/d .functor NOT 1, L_0x2c1e600, C4<0>, C4<0>, C4<0>; -L_0x2c1f960 .delay (10000,10000,10000) L_0x2c1f960/d; -L_0x2c1fa90/d .functor NAND 1, L_0x2c20a10, L_0x2c1f710, C4<1>, C4<1>; -L_0x2c1fa90 .delay (10000,10000,10000) L_0x2c1fa90/d; -L_0x2c1fbf0/d .functor NAND 1, L_0x2c1fa90, L_0x2c1f960, C4<1>, C4<1>; -L_0x2c1fbf0 .delay (10000,10000,10000) L_0x2c1fbf0/d; -L_0x2c1fd00/d .functor NOT 1, L_0x2c1fbf0, C4<0>, C4<0>, C4<0>; -L_0x2c1fd00 .delay (10000,10000,10000) L_0x2c1fd00/d; -v0x2b72e40_0 .net "A", 0 0, L_0x2c20a10; 1 drivers -v0x2b72ee0_0 .net "AnandB", 0 0, L_0x2c1fa90; 1 drivers -v0x2b72f80_0 .net "AnorB", 0 0, L_0x2c1e600; 1 drivers -v0x2b73030_0 .net "AorB", 0 0, L_0x2c1f960; 1 drivers -v0x2b73110_0 .net "AxorB", 0 0, L_0x2c1fd00; 1 drivers -v0x2b731c0_0 .net "B", 0 0, L_0x2c1f710; 1 drivers -v0x2b73280_0 .alias "Command", 2 0, v0x2bc67a0_0; -v0x2b73300_0 .net "OrNorXorOut", 0 0, L_0x2c20700; 1 drivers -v0x2b73380_0 .net "XorNor", 0 0, L_0x2c20180; 1 drivers -v0x2b73450_0 .net "nXor", 0 0, L_0x2c1fbf0; 1 drivers -L_0x2c20300 .part v0x2bc78e0_0, 2, 1; -L_0x2c208d0 .part v0x2bc78e0_0, 0, 1; -S_0x2b728d0 .scope module, "mux0" "TwoInMux" 3 83, 3 8, S_0x2b72290; - .timescale -9 -12; -L_0x2c1fe60/d .functor NOT 1, L_0x2c20300, C4<0>, C4<0>, C4<0>; -L_0x2c1fe60 .delay (10000,10000,10000) L_0x2c1fe60/d; -L_0x2c1ff20/d .functor AND 1, L_0x2c1fd00, L_0x2c1fe60, C4<1>, C4<1>; -L_0x2c1ff20 .delay (20000,20000,20000) L_0x2c1ff20/d; -L_0x2c20030/d .functor AND 1, L_0x2c1e600, L_0x2c20300, C4<1>, C4<1>; -L_0x2c20030 .delay (20000,20000,20000) L_0x2c20030/d; -L_0x2c20180/d .functor OR 1, L_0x2c1ff20, L_0x2c20030, C4<0>, C4<0>; -L_0x2c20180 .delay (20000,20000,20000) L_0x2c20180/d; -v0x2b729c0_0 .net "S", 0 0, L_0x2c20300; 1 drivers -v0x2b72a80_0 .alias "in0", 0 0, v0x2b73110_0; -v0x2b72b20_0 .alias "in1", 0 0, v0x2b72f80_0; -v0x2b72bc0_0 .net "nS", 0 0, L_0x2c1fe60; 1 drivers -v0x2b72c40_0 .net "out0", 0 0, L_0x2c1ff20; 1 drivers -v0x2b72ce0_0 .net "out1", 0 0, L_0x2c20030; 1 drivers -v0x2b72dc0_0 .alias "outfinal", 0 0, v0x2b73380_0; -S_0x2b72380 .scope module, "mux1" "TwoInMux" 3 84, 3 8, S_0x2b72290; - .timescale -9 -12; -L_0x2c203a0/d .functor NOT 1, L_0x2c208d0, C4<0>, C4<0>, C4<0>; -L_0x2c203a0 .delay (10000,10000,10000) L_0x2c203a0/d; -L_0x2c20460/d .functor AND 1, L_0x2c20180, L_0x2c203a0, C4<1>, C4<1>; -L_0x2c20460 .delay (20000,20000,20000) L_0x2c20460/d; -L_0x2c205b0/d .functor AND 1, L_0x2c1f960, L_0x2c208d0, C4<1>, C4<1>; -L_0x2c205b0 .delay (20000,20000,20000) L_0x2c205b0/d; -L_0x2c20700/d .functor OR 1, L_0x2c20460, L_0x2c205b0, C4<0>, C4<0>; -L_0x2c20700 .delay (20000,20000,20000) L_0x2c20700/d; -v0x2b72470_0 .net "S", 0 0, L_0x2c208d0; 1 drivers -v0x2b724f0_0 .alias "in0", 0 0, v0x2b73380_0; -v0x2b72590_0 .alias "in1", 0 0, v0x2b73030_0; -v0x2b72630_0 .net "nS", 0 0, L_0x2c203a0; 1 drivers -v0x2b726b0_0 .net "out0", 0 0, L_0x2c20460; 1 drivers -v0x2b72750_0 .net "out1", 0 0, L_0x2c205b0; 1 drivers -v0x2b72830_0 .alias "outfinal", 0 0, v0x2b73300_0; -S_0x2b70d90 .scope generate, "orbits[20]" "orbits[20]" 3 196, 3 196, S_0x2b62fd0; - .timescale -9 -12; -P_0x2b70aa8 .param/l "i" 3 196, +C4<010100>; -S_0x2b70ec0 .scope module, "attempt" "OrNorXor" 3 198, 3 64, S_0x2b70d90; - .timescale -9 -12; -L_0x2c1f7b0/d .functor NOR 1, L_0x2c20ab0, L_0x2c20b50, C4<0>, C4<0>; -L_0x2c1f7b0 .delay (10000,10000,10000) L_0x2c1f7b0/d; -L_0x2c20c80/d .functor NOT 1, L_0x2c1f7b0, C4<0>, C4<0>, C4<0>; -L_0x2c20c80 .delay (10000,10000,10000) L_0x2c20c80/d; -L_0x2c20d90/d .functor NAND 1, L_0x2c20ab0, L_0x2c20b50, C4<1>, C4<1>; -L_0x2c20d90 .delay (10000,10000,10000) L_0x2c20d90/d; -L_0x2c20ef0/d .functor NAND 1, L_0x2c20d90, L_0x2c20c80, C4<1>, C4<1>; -L_0x2c20ef0 .delay (10000,10000,10000) L_0x2c20ef0/d; -L_0x2c21000/d .functor NOT 1, L_0x2c20ef0, C4<0>, C4<0>, C4<0>; -L_0x2c21000 .delay (10000,10000,10000) L_0x2c21000/d; -v0x2b71a70_0 .net "A", 0 0, L_0x2c20ab0; 1 drivers -v0x2b71b10_0 .net "AnandB", 0 0, L_0x2c20d90; 1 drivers -v0x2b71bb0_0 .net "AnorB", 0 0, L_0x2c1f7b0; 1 drivers -v0x2b71c60_0 .net "AorB", 0 0, L_0x2c20c80; 1 drivers -v0x2b71d40_0 .net "AxorB", 0 0, L_0x2c21000; 1 drivers -v0x2b71df0_0 .net "B", 0 0, L_0x2c20b50; 1 drivers -v0x2b71eb0_0 .alias "Command", 2 0, v0x2bc67a0_0; -v0x2b71f30_0 .net "OrNorXorOut", 0 0, L_0x2c21a00; 1 drivers -v0x2b71fb0_0 .net "XorNor", 0 0, L_0x2c21480; 1 drivers -v0x2b72080_0 .net "nXor", 0 0, L_0x2c20ef0; 1 drivers -L_0x2c21600 .part v0x2bc78e0_0, 2, 1; -L_0x2c21bd0 .part v0x2bc78e0_0, 0, 1; -S_0x2b71500 .scope module, "mux0" "TwoInMux" 3 83, 3 8, S_0x2b70ec0; - .timescale -9 -12; -L_0x2c21160/d .functor NOT 1, L_0x2c21600, C4<0>, C4<0>, C4<0>; -L_0x2c21160 .delay (10000,10000,10000) L_0x2c21160/d; -L_0x2c21220/d .functor AND 1, L_0x2c21000, L_0x2c21160, C4<1>, C4<1>; -L_0x2c21220 .delay (20000,20000,20000) L_0x2c21220/d; -L_0x2c21330/d .functor AND 1, L_0x2c1f7b0, L_0x2c21600, C4<1>, C4<1>; -L_0x2c21330 .delay (20000,20000,20000) L_0x2c21330/d; -L_0x2c21480/d .functor OR 1, L_0x2c21220, L_0x2c21330, C4<0>, C4<0>; -L_0x2c21480 .delay (20000,20000,20000) L_0x2c21480/d; -v0x2b715f0_0 .net "S", 0 0, L_0x2c21600; 1 drivers -v0x2b716b0_0 .alias "in0", 0 0, v0x2b71d40_0; -v0x2b71750_0 .alias "in1", 0 0, v0x2b71bb0_0; -v0x2b717f0_0 .net "nS", 0 0, L_0x2c21160; 1 drivers -v0x2b71870_0 .net "out0", 0 0, L_0x2c21220; 1 drivers -v0x2b71910_0 .net "out1", 0 0, L_0x2c21330; 1 drivers -v0x2b719f0_0 .alias "outfinal", 0 0, v0x2b71fb0_0; -S_0x2b70fb0 .scope module, "mux1" "TwoInMux" 3 84, 3 8, S_0x2b70ec0; - .timescale -9 -12; -L_0x2c216a0/d .functor NOT 1, L_0x2c21bd0, C4<0>, C4<0>, C4<0>; -L_0x2c216a0 .delay (10000,10000,10000) L_0x2c216a0/d; -L_0x2c21760/d .functor AND 1, L_0x2c21480, L_0x2c216a0, C4<1>, C4<1>; -L_0x2c21760 .delay (20000,20000,20000) L_0x2c21760/d; -L_0x2c218b0/d .functor AND 1, L_0x2c20c80, L_0x2c21bd0, C4<1>, C4<1>; -L_0x2c218b0 .delay (20000,20000,20000) L_0x2c218b0/d; -L_0x2c21a00/d .functor OR 1, L_0x2c21760, L_0x2c218b0, C4<0>, C4<0>; -L_0x2c21a00 .delay (20000,20000,20000) L_0x2c21a00/d; -v0x2b710a0_0 .net "S", 0 0, L_0x2c21bd0; 1 drivers -v0x2b71120_0 .alias "in0", 0 0, v0x2b71fb0_0; -v0x2b711c0_0 .alias "in1", 0 0, v0x2b71c60_0; -v0x2b71260_0 .net "nS", 0 0, L_0x2c216a0; 1 drivers -v0x2b712e0_0 .net "out0", 0 0, L_0x2c21760; 1 drivers -v0x2b71380_0 .net "out1", 0 0, L_0x2c218b0; 1 drivers -v0x2b71460_0 .alias "outfinal", 0 0, v0x2b71f30_0; -S_0x2b6f9c0 .scope generate, "orbits[21]" "orbits[21]" 3 196, 3 196, S_0x2b62fd0; - .timescale -9 -12; -P_0x2b6f6d8 .param/l "i" 3 196, +C4<010101>; -S_0x2b6faf0 .scope module, "attempt" "OrNorXor" 3 198, 3 64, S_0x2b6f9c0; - .timescale -9 -12; -L_0x2c20bf0/d .functor NOR 1, L_0x2c23020, L_0x2c21d10, C4<0>, C4<0>; -L_0x2c20bf0 .delay (10000,10000,10000) L_0x2c20bf0/d; -L_0x2c21f90/d .functor NOT 1, L_0x2c20bf0, C4<0>, C4<0>, C4<0>; -L_0x2c21f90 .delay (10000,10000,10000) L_0x2c21f90/d; -L_0x2c220a0/d .functor NAND 1, L_0x2c23020, L_0x2c21d10, C4<1>, C4<1>; -L_0x2c220a0 .delay (10000,10000,10000) L_0x2c220a0/d; -L_0x2c22200/d .functor NAND 1, L_0x2c220a0, L_0x2c21f90, C4<1>, C4<1>; -L_0x2c22200 .delay (10000,10000,10000) L_0x2c22200/d; -L_0x2c22310/d .functor NOT 1, L_0x2c22200, C4<0>, C4<0>, C4<0>; -L_0x2c22310 .delay (10000,10000,10000) L_0x2c22310/d; -v0x2b706a0_0 .net "A", 0 0, L_0x2c23020; 1 drivers -v0x2b70740_0 .net "AnandB", 0 0, L_0x2c220a0; 1 drivers -v0x2b707e0_0 .net "AnorB", 0 0, L_0x2c20bf0; 1 drivers -v0x2b70890_0 .net "AorB", 0 0, L_0x2c21f90; 1 drivers -v0x2b70970_0 .net "AxorB", 0 0, L_0x2c22310; 1 drivers -v0x2b70a20_0 .net "B", 0 0, L_0x2c21d10; 1 drivers -v0x2b70ae0_0 .alias "Command", 2 0, v0x2bc67a0_0; -v0x2b70b60_0 .net "OrNorXorOut", 0 0, L_0x2c22d10; 1 drivers -v0x2b70be0_0 .net "XorNor", 0 0, L_0x2c22790; 1 drivers -v0x2b70cb0_0 .net "nXor", 0 0, L_0x2c22200; 1 drivers -L_0x2c22910 .part v0x2bc78e0_0, 2, 1; -L_0x2c22ee0 .part v0x2bc78e0_0, 0, 1; -S_0x2b70130 .scope module, "mux0" "TwoInMux" 3 83, 3 8, S_0x2b6faf0; - .timescale -9 -12; -L_0x2c22470/d .functor NOT 1, L_0x2c22910, C4<0>, C4<0>, C4<0>; -L_0x2c22470 .delay (10000,10000,10000) L_0x2c22470/d; -L_0x2c22530/d .functor AND 1, L_0x2c22310, L_0x2c22470, C4<1>, C4<1>; -L_0x2c22530 .delay (20000,20000,20000) L_0x2c22530/d; -L_0x2c22640/d .functor AND 1, L_0x2c20bf0, L_0x2c22910, C4<1>, C4<1>; -L_0x2c22640 .delay (20000,20000,20000) L_0x2c22640/d; -L_0x2c22790/d .functor OR 1, L_0x2c22530, L_0x2c22640, C4<0>, C4<0>; -L_0x2c22790 .delay (20000,20000,20000) L_0x2c22790/d; -v0x2b70220_0 .net "S", 0 0, L_0x2c22910; 1 drivers -v0x2b702e0_0 .alias "in0", 0 0, v0x2b70970_0; -v0x2b70380_0 .alias "in1", 0 0, v0x2b707e0_0; -v0x2b70420_0 .net "nS", 0 0, L_0x2c22470; 1 drivers -v0x2b704a0_0 .net "out0", 0 0, L_0x2c22530; 1 drivers -v0x2b70540_0 .net "out1", 0 0, L_0x2c22640; 1 drivers -v0x2b70620_0 .alias "outfinal", 0 0, v0x2b70be0_0; -S_0x2b6fbe0 .scope module, "mux1" "TwoInMux" 3 84, 3 8, S_0x2b6faf0; - .timescale -9 -12; -L_0x2c229b0/d .functor NOT 1, L_0x2c22ee0, C4<0>, C4<0>, C4<0>; -L_0x2c229b0 .delay (10000,10000,10000) L_0x2c229b0/d; -L_0x2c22a70/d .functor AND 1, L_0x2c22790, L_0x2c229b0, C4<1>, C4<1>; -L_0x2c22a70 .delay (20000,20000,20000) L_0x2c22a70/d; -L_0x2c22bc0/d .functor AND 1, L_0x2c21f90, L_0x2c22ee0, C4<1>, C4<1>; -L_0x2c22bc0 .delay (20000,20000,20000) L_0x2c22bc0/d; -L_0x2c22d10/d .functor OR 1, L_0x2c22a70, L_0x2c22bc0, C4<0>, C4<0>; -L_0x2c22d10 .delay (20000,20000,20000) L_0x2c22d10/d; -v0x2b6fcd0_0 .net "S", 0 0, L_0x2c22ee0; 1 drivers -v0x2b6fd50_0 .alias "in0", 0 0, v0x2b70be0_0; -v0x2b6fdf0_0 .alias "in1", 0 0, v0x2b70890_0; -v0x2b6fe90_0 .net "nS", 0 0, L_0x2c229b0; 1 drivers -v0x2b6ff10_0 .net "out0", 0 0, L_0x2c22a70; 1 drivers -v0x2b6ffb0_0 .net "out1", 0 0, L_0x2c22bc0; 1 drivers -v0x2b70090_0 .alias "outfinal", 0 0, v0x2b70b60_0; -S_0x2b6e5f0 .scope generate, "orbits[22]" "orbits[22]" 3 196, 3 196, S_0x2b62fd0; - .timescale -9 -12; -P_0x2b6e308 .param/l "i" 3 196, +C4<010110>; -S_0x2b6e720 .scope module, "attempt" "OrNorXor" 3 198, 3 64, S_0x2b6e5f0; - .timescale -9 -12; -L_0x2c21db0/d .functor NOR 1, L_0x2c230c0, L_0x2c23160, C4<0>, C4<0>; -L_0x2c21db0 .delay (10000,10000,10000) L_0x2c21db0/d; -L_0x2c21ea0/d .functor NOT 1, L_0x2c21db0, C4<0>, C4<0>, C4<0>; -L_0x2c21ea0 .delay (10000,10000,10000) L_0x2c21ea0/d; -L_0x2c23390/d .functor NAND 1, L_0x2c230c0, L_0x2c23160, C4<1>, C4<1>; -L_0x2c23390 .delay (10000,10000,10000) L_0x2c23390/d; -L_0x2c234f0/d .functor NAND 1, L_0x2c23390, L_0x2c21ea0, C4<1>, C4<1>; -L_0x2c234f0 .delay (10000,10000,10000) L_0x2c234f0/d; -L_0x2c23600/d .functor NOT 1, L_0x2c234f0, C4<0>, C4<0>, C4<0>; -L_0x2c23600 .delay (10000,10000,10000) L_0x2c23600/d; -v0x2b6f2d0_0 .net "A", 0 0, L_0x2c230c0; 1 drivers -v0x2b6f370_0 .net "AnandB", 0 0, L_0x2c23390; 1 drivers -v0x2b6f410_0 .net "AnorB", 0 0, L_0x2c21db0; 1 drivers -v0x2b6f4c0_0 .net "AorB", 0 0, L_0x2c21ea0; 1 drivers -v0x2b6f5a0_0 .net "AxorB", 0 0, L_0x2c23600; 1 drivers -v0x2b6f650_0 .net "B", 0 0, L_0x2c23160; 1 drivers -v0x2b6f710_0 .alias "Command", 2 0, v0x2bc67a0_0; -v0x2b6f790_0 .net "OrNorXorOut", 0 0, L_0x2c24000; 1 drivers -v0x2b6f810_0 .net "XorNor", 0 0, L_0x2c23a80; 1 drivers -v0x2b6f8e0_0 .net "nXor", 0 0, L_0x2c234f0; 1 drivers -L_0x2c23c00 .part v0x2bc78e0_0, 2, 1; -L_0x2c241d0 .part v0x2bc78e0_0, 0, 1; -S_0x2b6ed60 .scope module, "mux0" "TwoInMux" 3 83, 3 8, S_0x2b6e720; - .timescale -9 -12; -L_0x2c23760/d .functor NOT 1, L_0x2c23c00, C4<0>, C4<0>, C4<0>; -L_0x2c23760 .delay (10000,10000,10000) L_0x2c23760/d; -L_0x2c23820/d .functor AND 1, L_0x2c23600, L_0x2c23760, C4<1>, C4<1>; -L_0x2c23820 .delay (20000,20000,20000) L_0x2c23820/d; -L_0x2c23930/d .functor AND 1, L_0x2c21db0, L_0x2c23c00, C4<1>, C4<1>; -L_0x2c23930 .delay (20000,20000,20000) L_0x2c23930/d; -L_0x2c23a80/d .functor OR 1, L_0x2c23820, L_0x2c23930, C4<0>, C4<0>; -L_0x2c23a80 .delay (20000,20000,20000) L_0x2c23a80/d; -v0x2b6ee50_0 .net "S", 0 0, L_0x2c23c00; 1 drivers -v0x2b6ef10_0 .alias "in0", 0 0, v0x2b6f5a0_0; -v0x2b6efb0_0 .alias "in1", 0 0, v0x2b6f410_0; -v0x2b6f050_0 .net "nS", 0 0, L_0x2c23760; 1 drivers -v0x2b6f0d0_0 .net "out0", 0 0, L_0x2c23820; 1 drivers -v0x2b6f170_0 .net "out1", 0 0, L_0x2c23930; 1 drivers -v0x2b6f250_0 .alias "outfinal", 0 0, v0x2b6f810_0; -S_0x2b6e810 .scope module, "mux1" "TwoInMux" 3 84, 3 8, S_0x2b6e720; - .timescale -9 -12; -L_0x2c23ca0/d .functor NOT 1, L_0x2c241d0, C4<0>, C4<0>, C4<0>; -L_0x2c23ca0 .delay (10000,10000,10000) L_0x2c23ca0/d; -L_0x2c23d60/d .functor AND 1, L_0x2c23a80, L_0x2c23ca0, C4<1>, C4<1>; -L_0x2c23d60 .delay (20000,20000,20000) L_0x2c23d60/d; -L_0x2c23eb0/d .functor AND 1, L_0x2c21ea0, L_0x2c241d0, C4<1>, C4<1>; -L_0x2c23eb0 .delay (20000,20000,20000) L_0x2c23eb0/d; -L_0x2c24000/d .functor OR 1, L_0x2c23d60, L_0x2c23eb0, C4<0>, C4<0>; -L_0x2c24000 .delay (20000,20000,20000) L_0x2c24000/d; -v0x2b6e900_0 .net "S", 0 0, L_0x2c241d0; 1 drivers -v0x2b6e980_0 .alias "in0", 0 0, v0x2b6f810_0; -v0x2b6ea20_0 .alias "in1", 0 0, v0x2b6f4c0_0; -v0x2b6eac0_0 .net "nS", 0 0, L_0x2c23ca0; 1 drivers -v0x2b6eb40_0 .net "out0", 0 0, L_0x2c23d60; 1 drivers -v0x2b6ebe0_0 .net "out1", 0 0, L_0x2c23eb0; 1 drivers -v0x2b6ecc0_0 .alias "outfinal", 0 0, v0x2b6f790_0; -S_0x2b6d220 .scope generate, "orbits[23]" "orbits[23]" 3 196, 3 196, S_0x2b62fd0; - .timescale -9 -12; -P_0x2b6cf38 .param/l "i" 3 196, +C4<010111>; -S_0x2b6d350 .scope module, "attempt" "OrNorXor" 3 198, 3 64, S_0x2b6d220; - .timescale -9 -12; -L_0x2c23200/d .functor NOR 1, L_0x2c25610, L_0x2c24310, C4<0>, C4<0>; -L_0x2c23200 .delay (10000,10000,10000) L_0x2c23200/d; -L_0x2c24580/d .functor NOT 1, L_0x2c23200, C4<0>, C4<0>, C4<0>; -L_0x2c24580 .delay (10000,10000,10000) L_0x2c24580/d; -L_0x2c24690/d .functor NAND 1, L_0x2c25610, L_0x2c24310, C4<1>, C4<1>; -L_0x2c24690 .delay (10000,10000,10000) L_0x2c24690/d; -L_0x2c247f0/d .functor NAND 1, L_0x2c24690, L_0x2c24580, C4<1>, C4<1>; -L_0x2c247f0 .delay (10000,10000,10000) L_0x2c247f0/d; -L_0x2c24900/d .functor NOT 1, L_0x2c247f0, C4<0>, C4<0>, C4<0>; -L_0x2c24900 .delay (10000,10000,10000) L_0x2c24900/d; -v0x2b6df00_0 .net "A", 0 0, L_0x2c25610; 1 drivers -v0x2b6dfa0_0 .net "AnandB", 0 0, L_0x2c24690; 1 drivers -v0x2b6e040_0 .net "AnorB", 0 0, L_0x2c23200; 1 drivers -v0x2b6e0f0_0 .net "AorB", 0 0, L_0x2c24580; 1 drivers -v0x2b6e1d0_0 .net "AxorB", 0 0, L_0x2c24900; 1 drivers -v0x2b6e280_0 .net "B", 0 0, L_0x2c24310; 1 drivers -v0x2b6e340_0 .alias "Command", 2 0, v0x2bc67a0_0; -v0x2b6e3c0_0 .net "OrNorXorOut", 0 0, L_0x2c25300; 1 drivers -v0x2b6e440_0 .net "XorNor", 0 0, L_0x2c24d80; 1 drivers -v0x2b6e510_0 .net "nXor", 0 0, L_0x2c247f0; 1 drivers -L_0x2c24f00 .part v0x2bc78e0_0, 2, 1; -L_0x2c254d0 .part v0x2bc78e0_0, 0, 1; -S_0x2b6d990 .scope module, "mux0" "TwoInMux" 3 83, 3 8, S_0x2b6d350; - .timescale -9 -12; -L_0x2c24a60/d .functor NOT 1, L_0x2c24f00, C4<0>, C4<0>, C4<0>; -L_0x2c24a60 .delay (10000,10000,10000) L_0x2c24a60/d; -L_0x2c24b20/d .functor AND 1, L_0x2c24900, L_0x2c24a60, C4<1>, C4<1>; -L_0x2c24b20 .delay (20000,20000,20000) L_0x2c24b20/d; -L_0x2c24c30/d .functor AND 1, L_0x2c23200, L_0x2c24f00, C4<1>, C4<1>; -L_0x2c24c30 .delay (20000,20000,20000) L_0x2c24c30/d; -L_0x2c24d80/d .functor OR 1, L_0x2c24b20, L_0x2c24c30, C4<0>, C4<0>; -L_0x2c24d80 .delay (20000,20000,20000) L_0x2c24d80/d; -v0x2b6da80_0 .net "S", 0 0, L_0x2c24f00; 1 drivers -v0x2b6db40_0 .alias "in0", 0 0, v0x2b6e1d0_0; -v0x2b6dbe0_0 .alias "in1", 0 0, v0x2b6e040_0; -v0x2b6dc80_0 .net "nS", 0 0, L_0x2c24a60; 1 drivers -v0x2b6dd00_0 .net "out0", 0 0, L_0x2c24b20; 1 drivers -v0x2b6dda0_0 .net "out1", 0 0, L_0x2c24c30; 1 drivers -v0x2b6de80_0 .alias "outfinal", 0 0, v0x2b6e440_0; -S_0x2b6d440 .scope module, "mux1" "TwoInMux" 3 84, 3 8, S_0x2b6d350; - .timescale -9 -12; -L_0x2c24fa0/d .functor NOT 1, L_0x2c254d0, C4<0>, C4<0>, C4<0>; -L_0x2c24fa0 .delay (10000,10000,10000) L_0x2c24fa0/d; -L_0x2c25060/d .functor AND 1, L_0x2c24d80, L_0x2c24fa0, C4<1>, C4<1>; -L_0x2c25060 .delay (20000,20000,20000) L_0x2c25060/d; -L_0x2c251b0/d .functor AND 1, L_0x2c24580, L_0x2c254d0, C4<1>, C4<1>; -L_0x2c251b0 .delay (20000,20000,20000) L_0x2c251b0/d; -L_0x2c25300/d .functor OR 1, L_0x2c25060, L_0x2c251b0, C4<0>, C4<0>; -L_0x2c25300 .delay (20000,20000,20000) L_0x2c25300/d; -v0x2b6d530_0 .net "S", 0 0, L_0x2c254d0; 1 drivers -v0x2b6d5b0_0 .alias "in0", 0 0, v0x2b6e440_0; -v0x2b6d650_0 .alias "in1", 0 0, v0x2b6e0f0_0; -v0x2b6d6f0_0 .net "nS", 0 0, L_0x2c24fa0; 1 drivers -v0x2b6d770_0 .net "out0", 0 0, L_0x2c25060; 1 drivers -v0x2b6d810_0 .net "out1", 0 0, L_0x2c251b0; 1 drivers -v0x2b6d8f0_0 .alias "outfinal", 0 0, v0x2b6e3c0_0; -S_0x2b6be50 .scope generate, "orbits[24]" "orbits[24]" 3 196, 3 196, S_0x2b62fd0; - .timescale -9 -12; -P_0x2b6bb68 .param/l "i" 3 196, +C4<011000>; -S_0x2b6bf80 .scope module, "attempt" "OrNorXor" 3 198, 3 64, S_0x2b6be50; - .timescale -9 -12; -L_0x2c243b0/d .functor NOR 1, L_0x2c256b0, L_0x2c25750, C4<0>, C4<0>; -L_0x2c243b0 .delay (10000,10000,10000) L_0x2c243b0/d; -L_0x2c244a0/d .functor NOT 1, L_0x2c243b0, C4<0>, C4<0>, C4<0>; -L_0x2c244a0 .delay (10000,10000,10000) L_0x2c244a0/d; -L_0x2c25990/d .functor NAND 1, L_0x2c256b0, L_0x2c25750, C4<1>, C4<1>; -L_0x2c25990 .delay (10000,10000,10000) L_0x2c25990/d; -L_0x2c25af0/d .functor NAND 1, L_0x2c25990, L_0x2c244a0, C4<1>, C4<1>; -L_0x2c25af0 .delay (10000,10000,10000) L_0x2c25af0/d; -L_0x2c25c00/d .functor NOT 1, L_0x2c25af0, C4<0>, C4<0>, C4<0>; -L_0x2c25c00 .delay (10000,10000,10000) L_0x2c25c00/d; -v0x2b6cb30_0 .net "A", 0 0, L_0x2c256b0; 1 drivers -v0x2b6cbd0_0 .net "AnandB", 0 0, L_0x2c25990; 1 drivers -v0x2b6cc70_0 .net "AnorB", 0 0, L_0x2c243b0; 1 drivers -v0x2b6cd20_0 .net "AorB", 0 0, L_0x2c244a0; 1 drivers -v0x2b6ce00_0 .net "AxorB", 0 0, L_0x2c25c00; 1 drivers -v0x2b6ceb0_0 .net "B", 0 0, L_0x2c25750; 1 drivers -v0x2b6cf70_0 .alias "Command", 2 0, v0x2bc67a0_0; -v0x2b6cff0_0 .net "OrNorXorOut", 0 0, L_0x2c26600; 1 drivers -v0x2b6d070_0 .net "XorNor", 0 0, L_0x2c26080; 1 drivers -v0x2b6d140_0 .net "nXor", 0 0, L_0x2c25af0; 1 drivers -L_0x2c26200 .part v0x2bc78e0_0, 2, 1; -L_0x2c267d0 .part v0x2bc78e0_0, 0, 1; -S_0x2b6c5c0 .scope module, "mux0" "TwoInMux" 3 83, 3 8, S_0x2b6bf80; - .timescale -9 -12; -L_0x2c25d60/d .functor NOT 1, L_0x2c26200, C4<0>, C4<0>, C4<0>; -L_0x2c25d60 .delay (10000,10000,10000) L_0x2c25d60/d; -L_0x2c25e20/d .functor AND 1, L_0x2c25c00, L_0x2c25d60, C4<1>, C4<1>; -L_0x2c25e20 .delay (20000,20000,20000) L_0x2c25e20/d; -L_0x2c25f30/d .functor AND 1, L_0x2c243b0, L_0x2c26200, C4<1>, C4<1>; -L_0x2c25f30 .delay (20000,20000,20000) L_0x2c25f30/d; -L_0x2c26080/d .functor OR 1, L_0x2c25e20, L_0x2c25f30, C4<0>, C4<0>; -L_0x2c26080 .delay (20000,20000,20000) L_0x2c26080/d; -v0x2b6c6b0_0 .net "S", 0 0, L_0x2c26200; 1 drivers -v0x2b6c770_0 .alias "in0", 0 0, v0x2b6ce00_0; -v0x2b6c810_0 .alias "in1", 0 0, v0x2b6cc70_0; -v0x2b6c8b0_0 .net "nS", 0 0, L_0x2c25d60; 1 drivers -v0x2b6c930_0 .net "out0", 0 0, L_0x2c25e20; 1 drivers -v0x2b6c9d0_0 .net "out1", 0 0, L_0x2c25f30; 1 drivers -v0x2b6cab0_0 .alias "outfinal", 0 0, v0x2b6d070_0; -S_0x2b6c070 .scope module, "mux1" "TwoInMux" 3 84, 3 8, S_0x2b6bf80; - .timescale -9 -12; -L_0x2c262a0/d .functor NOT 1, L_0x2c267d0, C4<0>, C4<0>, C4<0>; -L_0x2c262a0 .delay (10000,10000,10000) L_0x2c262a0/d; -L_0x2c26360/d .functor AND 1, L_0x2c26080, L_0x2c262a0, C4<1>, C4<1>; -L_0x2c26360 .delay (20000,20000,20000) L_0x2c26360/d; -L_0x2c264b0/d .functor AND 1, L_0x2c244a0, L_0x2c267d0, C4<1>, C4<1>; -L_0x2c264b0 .delay (20000,20000,20000) L_0x2c264b0/d; -L_0x2c26600/d .functor OR 1, L_0x2c26360, L_0x2c264b0, C4<0>, C4<0>; -L_0x2c26600 .delay (20000,20000,20000) L_0x2c26600/d; -v0x2b6c160_0 .net "S", 0 0, L_0x2c267d0; 1 drivers -v0x2b6c1e0_0 .alias "in0", 0 0, v0x2b6d070_0; -v0x2b6c280_0 .alias "in1", 0 0, v0x2b6cd20_0; -v0x2b6c320_0 .net "nS", 0 0, L_0x2c262a0; 1 drivers -v0x2b6c3a0_0 .net "out0", 0 0, L_0x2c26360; 1 drivers -v0x2b6c440_0 .net "out1", 0 0, L_0x2c264b0; 1 drivers -v0x2b6c520_0 .alias "outfinal", 0 0, v0x2b6cff0_0; -S_0x2b6aa80 .scope generate, "orbits[25]" "orbits[25]" 3 196, 3 196, S_0x2b62fd0; - .timescale -9 -12; -P_0x2b6a798 .param/l "i" 3 196, +C4<011001>; -S_0x2b6abb0 .scope module, "attempt" "OrNorXor" 3 198, 3 64, S_0x2b6aa80; - .timescale -9 -12; -L_0x2c257f0/d .functor NOR 1, L_0x2c27c10, L_0x2c26910, C4<0>, C4<0>; -L_0x2c257f0 .delay (10000,10000,10000) L_0x2c257f0/d; -L_0x2c26b60/d .functor NOT 1, L_0x2c257f0, C4<0>, C4<0>, C4<0>; -L_0x2c26b60 .delay (10000,10000,10000) L_0x2c26b60/d; -L_0x2c26c90/d .functor NAND 1, L_0x2c27c10, L_0x2c26910, C4<1>, C4<1>; -L_0x2c26c90 .delay (10000,10000,10000) L_0x2c26c90/d; -L_0x2c26df0/d .functor NAND 1, L_0x2c26c90, L_0x2c26b60, C4<1>, C4<1>; -L_0x2c26df0 .delay (10000,10000,10000) L_0x2c26df0/d; -L_0x2c26f00/d .functor NOT 1, L_0x2c26df0, C4<0>, C4<0>, C4<0>; -L_0x2c26f00 .delay (10000,10000,10000) L_0x2c26f00/d; -v0x2b6b760_0 .net "A", 0 0, L_0x2c27c10; 1 drivers -v0x2b6b800_0 .net "AnandB", 0 0, L_0x2c26c90; 1 drivers -v0x2b6b8a0_0 .net "AnorB", 0 0, L_0x2c257f0; 1 drivers -v0x2b6b950_0 .net "AorB", 0 0, L_0x2c26b60; 1 drivers -v0x2b6ba30_0 .net "AxorB", 0 0, L_0x2c26f00; 1 drivers -v0x2b6bae0_0 .net "B", 0 0, L_0x2c26910; 1 drivers -v0x2b6bba0_0 .alias "Command", 2 0, v0x2bc67a0_0; -v0x2b6bc20_0 .net "OrNorXorOut", 0 0, L_0x2c27900; 1 drivers -v0x2b6bca0_0 .net "XorNor", 0 0, L_0x2c27380; 1 drivers -v0x2b6bd70_0 .net "nXor", 0 0, L_0x2c26df0; 1 drivers -L_0x2c27500 .part v0x2bc78e0_0, 2, 1; -L_0x2c27ad0 .part v0x2bc78e0_0, 0, 1; -S_0x2b6b1f0 .scope module, "mux0" "TwoInMux" 3 83, 3 8, S_0x2b6abb0; - .timescale -9 -12; -L_0x2c27060/d .functor NOT 1, L_0x2c27500, C4<0>, C4<0>, C4<0>; -L_0x2c27060 .delay (10000,10000,10000) L_0x2c27060/d; -L_0x2c27120/d .functor AND 1, L_0x2c26f00, L_0x2c27060, C4<1>, C4<1>; -L_0x2c27120 .delay (20000,20000,20000) L_0x2c27120/d; -L_0x2c27230/d .functor AND 1, L_0x2c257f0, L_0x2c27500, C4<1>, C4<1>; -L_0x2c27230 .delay (20000,20000,20000) L_0x2c27230/d; -L_0x2c27380/d .functor OR 1, L_0x2c27120, L_0x2c27230, C4<0>, C4<0>; -L_0x2c27380 .delay (20000,20000,20000) L_0x2c27380/d; -v0x2b6b2e0_0 .net "S", 0 0, L_0x2c27500; 1 drivers -v0x2b6b3a0_0 .alias "in0", 0 0, v0x2b6ba30_0; -v0x2b6b440_0 .alias "in1", 0 0, v0x2b6b8a0_0; -v0x2b6b4e0_0 .net "nS", 0 0, L_0x2c27060; 1 drivers -v0x2b6b560_0 .net "out0", 0 0, L_0x2c27120; 1 drivers -v0x2b6b600_0 .net "out1", 0 0, L_0x2c27230; 1 drivers -v0x2b6b6e0_0 .alias "outfinal", 0 0, v0x2b6bca0_0; -S_0x2b6aca0 .scope module, "mux1" "TwoInMux" 3 84, 3 8, S_0x2b6abb0; - .timescale -9 -12; -L_0x2c275a0/d .functor NOT 1, L_0x2c27ad0, C4<0>, C4<0>, C4<0>; -L_0x2c275a0 .delay (10000,10000,10000) L_0x2c275a0/d; -L_0x2c27660/d .functor AND 1, L_0x2c27380, L_0x2c275a0, C4<1>, C4<1>; -L_0x2c27660 .delay (20000,20000,20000) L_0x2c27660/d; -L_0x2c277b0/d .functor AND 1, L_0x2c26b60, L_0x2c27ad0, C4<1>, C4<1>; -L_0x2c277b0 .delay (20000,20000,20000) L_0x2c277b0/d; -L_0x2c27900/d .functor OR 1, L_0x2c27660, L_0x2c277b0, C4<0>, C4<0>; -L_0x2c27900 .delay (20000,20000,20000) L_0x2c27900/d; -v0x2b6ad90_0 .net "S", 0 0, L_0x2c27ad0; 1 drivers -v0x2b6ae10_0 .alias "in0", 0 0, v0x2b6bca0_0; -v0x2b6aeb0_0 .alias "in1", 0 0, v0x2b6b950_0; -v0x2b6af50_0 .net "nS", 0 0, L_0x2c275a0; 1 drivers -v0x2b6afd0_0 .net "out0", 0 0, L_0x2c27660; 1 drivers -v0x2b6b070_0 .net "out1", 0 0, L_0x2c277b0; 1 drivers -v0x2b6b150_0 .alias "outfinal", 0 0, v0x2b6bc20_0; -S_0x2b696b0 .scope generate, "orbits[26]" "orbits[26]" 3 196, 3 196, S_0x2b62fd0; - .timescale -9 -12; -P_0x2b693c8 .param/l "i" 3 196, +C4<011010>; -S_0x2b697e0 .scope module, "attempt" "OrNorXor" 3 198, 3 64, S_0x2b696b0; - .timescale -9 -12; -L_0x2c269b0/d .functor NOR 1, L_0x2c27cb0, L_0x2c27d50, C4<0>, C4<0>; -L_0x2c269b0 .delay (10000,10000,10000) L_0x2c269b0/d; -L_0x2c26aa0/d .functor NOT 1, L_0x2c269b0, C4<0>, C4<0>, C4<0>; -L_0x2c26aa0 .delay (10000,10000,10000) L_0x2c26aa0/d; -L_0x2c27f80/d .functor NAND 1, L_0x2c27cb0, L_0x2c27d50, C4<1>, C4<1>; -L_0x2c27f80 .delay (10000,10000,10000) L_0x2c27f80/d; -L_0x2c280e0/d .functor NAND 1, L_0x2c27f80, L_0x2c26aa0, C4<1>, C4<1>; -L_0x2c280e0 .delay (10000,10000,10000) L_0x2c280e0/d; -L_0x2c281f0/d .functor NOT 1, L_0x2c280e0, C4<0>, C4<0>, C4<0>; -L_0x2c281f0 .delay (10000,10000,10000) L_0x2c281f0/d; -v0x2b6a390_0 .net "A", 0 0, L_0x2c27cb0; 1 drivers -v0x2b6a430_0 .net "AnandB", 0 0, L_0x2c27f80; 1 drivers -v0x2b6a4d0_0 .net "AnorB", 0 0, L_0x2c269b0; 1 drivers -v0x2b6a580_0 .net "AorB", 0 0, L_0x2c26aa0; 1 drivers -v0x2b6a660_0 .net "AxorB", 0 0, L_0x2c281f0; 1 drivers -v0x2b6a710_0 .net "B", 0 0, L_0x2c27d50; 1 drivers -v0x2b6a7d0_0 .alias "Command", 2 0, v0x2bc67a0_0; -v0x2b6a850_0 .net "OrNorXorOut", 0 0, L_0x2c28bf0; 1 drivers -v0x2b6a8d0_0 .net "XorNor", 0 0, L_0x2c28670; 1 drivers -v0x2b6a9a0_0 .net "nXor", 0 0, L_0x2c280e0; 1 drivers -L_0x2c287f0 .part v0x2bc78e0_0, 2, 1; -L_0x2c28dc0 .part v0x2bc78e0_0, 0, 1; -S_0x2b69e20 .scope module, "mux0" "TwoInMux" 3 83, 3 8, S_0x2b697e0; - .timescale -9 -12; -L_0x2c28350/d .functor NOT 1, L_0x2c287f0, C4<0>, C4<0>, C4<0>; -L_0x2c28350 .delay (10000,10000,10000) L_0x2c28350/d; -L_0x2c28410/d .functor AND 1, L_0x2c281f0, L_0x2c28350, C4<1>, C4<1>; -L_0x2c28410 .delay (20000,20000,20000) L_0x2c28410/d; -L_0x2c28520/d .functor AND 1, L_0x2c269b0, L_0x2c287f0, C4<1>, C4<1>; -L_0x2c28520 .delay (20000,20000,20000) L_0x2c28520/d; -L_0x2c28670/d .functor OR 1, L_0x2c28410, L_0x2c28520, C4<0>, C4<0>; -L_0x2c28670 .delay (20000,20000,20000) L_0x2c28670/d; -v0x2b69f10_0 .net "S", 0 0, L_0x2c287f0; 1 drivers -v0x2b69fd0_0 .alias "in0", 0 0, v0x2b6a660_0; -v0x2b6a070_0 .alias "in1", 0 0, v0x2b6a4d0_0; -v0x2b6a110_0 .net "nS", 0 0, L_0x2c28350; 1 drivers -v0x2b6a190_0 .net "out0", 0 0, L_0x2c28410; 1 drivers -v0x2b6a230_0 .net "out1", 0 0, L_0x2c28520; 1 drivers -v0x2b6a310_0 .alias "outfinal", 0 0, v0x2b6a8d0_0; -S_0x2b698d0 .scope module, "mux1" "TwoInMux" 3 84, 3 8, S_0x2b697e0; - .timescale -9 -12; -L_0x2c28890/d .functor NOT 1, L_0x2c28dc0, C4<0>, C4<0>, C4<0>; -L_0x2c28890 .delay (10000,10000,10000) L_0x2c28890/d; -L_0x2c28950/d .functor AND 1, L_0x2c28670, L_0x2c28890, C4<1>, C4<1>; -L_0x2c28950 .delay (20000,20000,20000) L_0x2c28950/d; -L_0x2c28aa0/d .functor AND 1, L_0x2c26aa0, L_0x2c28dc0, C4<1>, C4<1>; -L_0x2c28aa0 .delay (20000,20000,20000) L_0x2c28aa0/d; -L_0x2c28bf0/d .functor OR 1, L_0x2c28950, L_0x2c28aa0, C4<0>, C4<0>; -L_0x2c28bf0 .delay (20000,20000,20000) L_0x2c28bf0/d; -v0x2b699c0_0 .net "S", 0 0, L_0x2c28dc0; 1 drivers -v0x2b69a40_0 .alias "in0", 0 0, v0x2b6a8d0_0; -v0x2b69ae0_0 .alias "in1", 0 0, v0x2b6a580_0; -v0x2b69b80_0 .net "nS", 0 0, L_0x2c28890; 1 drivers -v0x2b69c00_0 .net "out0", 0 0, L_0x2c28950; 1 drivers -v0x2b69ca0_0 .net "out1", 0 0, L_0x2c28aa0; 1 drivers -v0x2b69d80_0 .alias "outfinal", 0 0, v0x2b6a850_0; -S_0x2b682c0 .scope generate, "orbits[27]" "orbits[27]" 3 196, 3 196, S_0x2b62fd0; - .timescale -9 -12; -P_0x2b683b8 .param/l "i" 3 196, +C4<011011>; -S_0x2b68430 .scope module, "attempt" "OrNorXor" 3 198, 3 64, S_0x2b682c0; - .timescale -9 -12; -L_0x2c27df0/d .functor NOR 1, L_0x2c2a210, L_0x2c28f00, C4<0>, C4<0>; -L_0x2c27df0 .delay (10000,10000,10000) L_0x2c27df0/d; -L_0x2c29180/d .functor NOT 1, L_0x2c27df0, C4<0>, C4<0>, C4<0>; -L_0x2c29180 .delay (10000,10000,10000) L_0x2c29180/d; -L_0x2c29290/d .functor NAND 1, L_0x2c2a210, L_0x2c28f00, C4<1>, C4<1>; -L_0x2c29290 .delay (10000,10000,10000) L_0x2c29290/d; -L_0x2c293f0/d .functor NAND 1, L_0x2c29290, L_0x2c29180, C4<1>, C4<1>; -L_0x2c293f0 .delay (10000,10000,10000) L_0x2c293f0/d; -L_0x2c29500/d .functor NOT 1, L_0x2c293f0, C4<0>, C4<0>, C4<0>; -L_0x2c29500 .delay (10000,10000,10000) L_0x2c29500/d; -v0x2b68fc0_0 .net "A", 0 0, L_0x2c2a210; 1 drivers -v0x2b69060_0 .net "AnandB", 0 0, L_0x2c29290; 1 drivers -v0x2b69100_0 .net "AnorB", 0 0, L_0x2c27df0; 1 drivers -v0x2b691b0_0 .net "AorB", 0 0, L_0x2c29180; 1 drivers -v0x2b69290_0 .net "AxorB", 0 0, L_0x2c29500; 1 drivers -v0x2b69340_0 .net "B", 0 0, L_0x2c28f00; 1 drivers -v0x2b69400_0 .alias "Command", 2 0, v0x2bc67a0_0; -v0x2b69480_0 .net "OrNorXorOut", 0 0, L_0x2c29f00; 1 drivers -v0x2b69500_0 .net "XorNor", 0 0, L_0x2c29980; 1 drivers -v0x2b695d0_0 .net "nXor", 0 0, L_0x2c293f0; 1 drivers -L_0x2c29b00 .part v0x2bc78e0_0, 2, 1; -L_0x2c2a0d0 .part v0x2bc78e0_0, 0, 1; -S_0x2b68a50 .scope module, "mux0" "TwoInMux" 3 83, 3 8, S_0x2b68430; - .timescale -9 -12; -L_0x2c29660/d .functor NOT 1, L_0x2c29b00, C4<0>, C4<0>, C4<0>; -L_0x2c29660 .delay (10000,10000,10000) L_0x2c29660/d; -L_0x2c29720/d .functor AND 1, L_0x2c29500, L_0x2c29660, C4<1>, C4<1>; -L_0x2c29720 .delay (20000,20000,20000) L_0x2c29720/d; -L_0x2c29830/d .functor AND 1, L_0x2c27df0, L_0x2c29b00, C4<1>, C4<1>; -L_0x2c29830 .delay (20000,20000,20000) L_0x2c29830/d; -L_0x2c29980/d .functor OR 1, L_0x2c29720, L_0x2c29830, C4<0>, C4<0>; -L_0x2c29980 .delay (20000,20000,20000) L_0x2c29980/d; -v0x2b68b40_0 .net "S", 0 0, L_0x2c29b00; 1 drivers -v0x2b68c00_0 .alias "in0", 0 0, v0x2b69290_0; -v0x2b68ca0_0 .alias "in1", 0 0, v0x2b69100_0; -v0x2b68d40_0 .net "nS", 0 0, L_0x2c29660; 1 drivers -v0x2b68dc0_0 .net "out0", 0 0, L_0x2c29720; 1 drivers -v0x2b68e60_0 .net "out1", 0 0, L_0x2c29830; 1 drivers -v0x2b68f40_0 .alias "outfinal", 0 0, v0x2b69500_0; -S_0x2b68520 .scope module, "mux1" "TwoInMux" 3 84, 3 8, S_0x2b68430; - .timescale -9 -12; -L_0x2c29ba0/d .functor NOT 1, L_0x2c2a0d0, C4<0>, C4<0>, C4<0>; -L_0x2c29ba0 .delay (10000,10000,10000) L_0x2c29ba0/d; -L_0x2c29c60/d .functor AND 1, L_0x2c29980, L_0x2c29ba0, C4<1>, C4<1>; -L_0x2c29c60 .delay (20000,20000,20000) L_0x2c29c60/d; -L_0x2c29db0/d .functor AND 1, L_0x2c29180, L_0x2c2a0d0, C4<1>, C4<1>; -L_0x2c29db0 .delay (20000,20000,20000) L_0x2c29db0/d; -L_0x2c29f00/d .functor OR 1, L_0x2c29c60, L_0x2c29db0, C4<0>, C4<0>; -L_0x2c29f00 .delay (20000,20000,20000) L_0x2c29f00/d; -v0x2b68610_0 .net "S", 0 0, L_0x2c2a0d0; 1 drivers -v0x2b68690_0 .alias "in0", 0 0, v0x2b69500_0; -v0x2b68710_0 .alias "in1", 0 0, v0x2b691b0_0; -v0x2b687b0_0 .net "nS", 0 0, L_0x2c29ba0; 1 drivers -v0x2b68830_0 .net "out0", 0 0, L_0x2c29c60; 1 drivers -v0x2b688d0_0 .net "out1", 0 0, L_0x2c29db0; 1 drivers -v0x2b689b0_0 .alias "outfinal", 0 0, v0x2b69480_0; -S_0x2b66f80 .scope generate, "orbits[28]" "orbits[28]" 3 196, 3 196, S_0x2b62fd0; - .timescale -9 -12; -P_0x2b66c98 .param/l "i" 3 196, +C4<011100>; -S_0x2b670b0 .scope module, "attempt" "OrNorXor" 3 198, 3 64, S_0x2b66f80; - .timescale -9 -12; -L_0x2c28fa0/d .functor NOR 1, L_0x2c2a2b0, L_0x2c2a350, C4<0>, C4<0>; -L_0x2c28fa0 .delay (10000,10000,10000) L_0x2c28fa0/d; -L_0x2c29090/d .functor NOT 1, L_0x2c28fa0, C4<0>, C4<0>, C4<0>; -L_0x2c29090 .delay (10000,10000,10000) L_0x2c29090/d; -L_0x2c2a590/d .functor NAND 1, L_0x2c2a2b0, L_0x2c2a350, C4<1>, C4<1>; -L_0x2c2a590 .delay (10000,10000,10000) L_0x2c2a590/d; -L_0x2c2a6f0/d .functor NAND 1, L_0x2c2a590, L_0x2c29090, C4<1>, C4<1>; -L_0x2c2a6f0 .delay (10000,10000,10000) L_0x2c2a6f0/d; -L_0x2c2a800/d .functor NOT 1, L_0x2c2a6f0, C4<0>, C4<0>, C4<0>; -L_0x2c2a800 .delay (10000,10000,10000) L_0x2c2a800/d; -v0x2b67c60_0 .net "A", 0 0, L_0x2c2a2b0; 1 drivers -v0x2b67d00_0 .net "AnandB", 0 0, L_0x2c2a590; 1 drivers -v0x2b67da0_0 .net "AnorB", 0 0, L_0x2c28fa0; 1 drivers -v0x2b67e50_0 .net "AorB", 0 0, L_0x2c29090; 1 drivers -v0x2b67f30_0 .net "AxorB", 0 0, L_0x2c2a800; 1 drivers -v0x2b67fe0_0 .net "B", 0 0, L_0x2c2a350; 1 drivers -v0x2b68060_0 .alias "Command", 2 0, v0x2bc67a0_0; -v0x2b680e0_0 .net "OrNorXorOut", 0 0, L_0x2c2b200; 1 drivers -v0x2b68160_0 .net "XorNor", 0 0, L_0x2c2ac80; 1 drivers -v0x2b681e0_0 .net "nXor", 0 0, L_0x2c2a6f0; 1 drivers -L_0x2c2ae00 .part v0x2bc78e0_0, 2, 1; -L_0x2c2b3d0 .part v0x2bc78e0_0, 0, 1; -S_0x2b676f0 .scope module, "mux0" "TwoInMux" 3 83, 3 8, S_0x2b670b0; - .timescale -9 -12; -L_0x2c2a960/d .functor NOT 1, L_0x2c2ae00, C4<0>, C4<0>, C4<0>; -L_0x2c2a960 .delay (10000,10000,10000) L_0x2c2a960/d; -L_0x2c2aa20/d .functor AND 1, L_0x2c2a800, L_0x2c2a960, C4<1>, C4<1>; -L_0x2c2aa20 .delay (20000,20000,20000) L_0x2c2aa20/d; -L_0x2c2ab30/d .functor AND 1, L_0x2c28fa0, L_0x2c2ae00, C4<1>, C4<1>; -L_0x2c2ab30 .delay (20000,20000,20000) L_0x2c2ab30/d; -L_0x2c2ac80/d .functor OR 1, L_0x2c2aa20, L_0x2c2ab30, C4<0>, C4<0>; -L_0x2c2ac80 .delay (20000,20000,20000) L_0x2c2ac80/d; -v0x2b677e0_0 .net "S", 0 0, L_0x2c2ae00; 1 drivers -v0x2b678a0_0 .alias "in0", 0 0, v0x2b67f30_0; -v0x2b67940_0 .alias "in1", 0 0, v0x2b67da0_0; -v0x2b679e0_0 .net "nS", 0 0, L_0x2c2a960; 1 drivers -v0x2b67a60_0 .net "out0", 0 0, L_0x2c2aa20; 1 drivers -v0x2b67b00_0 .net "out1", 0 0, L_0x2c2ab30; 1 drivers -v0x2b67be0_0 .alias "outfinal", 0 0, v0x2b68160_0; -S_0x2b671a0 .scope module, "mux1" "TwoInMux" 3 84, 3 8, S_0x2b670b0; - .timescale -9 -12; -L_0x2c2aea0/d .functor NOT 1, L_0x2c2b3d0, C4<0>, C4<0>, C4<0>; -L_0x2c2aea0 .delay (10000,10000,10000) L_0x2c2aea0/d; -L_0x2c2af60/d .functor AND 1, L_0x2c2ac80, L_0x2c2aea0, C4<1>, C4<1>; -L_0x2c2af60 .delay (20000,20000,20000) L_0x2c2af60/d; -L_0x2c2b0b0/d .functor AND 1, L_0x2c29090, L_0x2c2b3d0, C4<1>, C4<1>; -L_0x2c2b0b0 .delay (20000,20000,20000) L_0x2c2b0b0/d; -L_0x2c2b200/d .functor OR 1, L_0x2c2af60, L_0x2c2b0b0, C4<0>, C4<0>; -L_0x2c2b200 .delay (20000,20000,20000) L_0x2c2b200/d; -v0x2b67290_0 .net "S", 0 0, L_0x2c2b3d0; 1 drivers -v0x2b67310_0 .alias "in0", 0 0, v0x2b68160_0; -v0x2b673b0_0 .alias "in1", 0 0, v0x2b67e50_0; -v0x2b67450_0 .net "nS", 0 0, L_0x2c2aea0; 1 drivers -v0x2b674d0_0 .net "out0", 0 0, L_0x2c2af60; 1 drivers -v0x2b67570_0 .net "out1", 0 0, L_0x2c2b0b0; 1 drivers -v0x2b67650_0 .alias "outfinal", 0 0, v0x2b680e0_0; -S_0x2b65bb0 .scope generate, "orbits[29]" "orbits[29]" 3 196, 3 196, S_0x2b62fd0; - .timescale -9 -12; -P_0x2b658c8 .param/l "i" 3 196, +C4<011101>; -S_0x2b65ce0 .scope module, "attempt" "OrNorXor" 3 198, 3 64, S_0x2b65bb0; - .timescale -9 -12; -L_0x2c2a3f0/d .functor NOR 1, L_0x2c19710, L_0x2c197b0, C4<0>, C4<0>; -L_0x2c2a3f0 .delay (10000,10000,10000) L_0x2c2a3f0/d; -L_0x2c2a4e0/d .functor NOT 1, L_0x2c2a3f0, C4<0>, C4<0>, C4<0>; -L_0x2c2a4e0 .delay (10000,10000,10000) L_0x2c2a4e0/d; -L_0x2c2b890/d .functor NAND 1, L_0x2c19710, L_0x2c197b0, C4<1>, C4<1>; -L_0x2c2b890 .delay (10000,10000,10000) L_0x2c2b890/d; -L_0x2c2b9f0/d .functor NAND 1, L_0x2c2b890, L_0x2c2a4e0, C4<1>, C4<1>; -L_0x2c2b9f0 .delay (10000,10000,10000) L_0x2c2b9f0/d; -L_0x2c2bb00/d .functor NOT 1, L_0x2c2b9f0, C4<0>, C4<0>, C4<0>; -L_0x2c2bb00 .delay (10000,10000,10000) L_0x2c2bb00/d; -v0x2b66890_0 .net "A", 0 0, L_0x2c19710; 1 drivers -v0x2b66930_0 .net "AnandB", 0 0, L_0x2c2b890; 1 drivers -v0x2b669d0_0 .net "AnorB", 0 0, L_0x2c2a3f0; 1 drivers -v0x2b66a80_0 .net "AorB", 0 0, L_0x2c2a4e0; 1 drivers -v0x2b66b60_0 .net "AxorB", 0 0, L_0x2c2bb00; 1 drivers -v0x2b66c10_0 .net "B", 0 0, L_0x2c197b0; 1 drivers -v0x2b66cd0_0 .alias "Command", 2 0, v0x2bc67a0_0; -v0x2b66d50_0 .net "OrNorXorOut", 0 0, L_0x2c2c500; 1 drivers -v0x2b66dd0_0 .net "XorNor", 0 0, L_0x2c2bf80; 1 drivers -v0x2b66ea0_0 .net "nXor", 0 0, L_0x2c2b9f0; 1 drivers -L_0x2c2c100 .part v0x2bc78e0_0, 2, 1; -L_0x2c2c6d0 .part v0x2bc78e0_0, 0, 1; -S_0x2b66320 .scope module, "mux0" "TwoInMux" 3 83, 3 8, S_0x2b65ce0; - .timescale -9 -12; -L_0x2c2bc60/d .functor NOT 1, L_0x2c2c100, C4<0>, C4<0>, C4<0>; -L_0x2c2bc60 .delay (10000,10000,10000) L_0x2c2bc60/d; -L_0x2c2bd20/d .functor AND 1, L_0x2c2bb00, L_0x2c2bc60, C4<1>, C4<1>; -L_0x2c2bd20 .delay (20000,20000,20000) L_0x2c2bd20/d; -L_0x2c2be30/d .functor AND 1, L_0x2c2a3f0, L_0x2c2c100, C4<1>, C4<1>; -L_0x2c2be30 .delay (20000,20000,20000) L_0x2c2be30/d; -L_0x2c2bf80/d .functor OR 1, L_0x2c2bd20, L_0x2c2be30, C4<0>, C4<0>; -L_0x2c2bf80 .delay (20000,20000,20000) L_0x2c2bf80/d; -v0x2b66410_0 .net "S", 0 0, L_0x2c2c100; 1 drivers -v0x2b664d0_0 .alias "in0", 0 0, v0x2b66b60_0; -v0x2b66570_0 .alias "in1", 0 0, v0x2b669d0_0; -v0x2b66610_0 .net "nS", 0 0, L_0x2c2bc60; 1 drivers -v0x2b66690_0 .net "out0", 0 0, L_0x2c2bd20; 1 drivers -v0x2b66730_0 .net "out1", 0 0, L_0x2c2be30; 1 drivers -v0x2b66810_0 .alias "outfinal", 0 0, v0x2b66dd0_0; -S_0x2b65dd0 .scope module, "mux1" "TwoInMux" 3 84, 3 8, S_0x2b65ce0; - .timescale -9 -12; -L_0x2c2c1a0/d .functor NOT 1, L_0x2c2c6d0, C4<0>, C4<0>, C4<0>; -L_0x2c2c1a0 .delay (10000,10000,10000) L_0x2c2c1a0/d; -L_0x2c2c260/d .functor AND 1, L_0x2c2bf80, L_0x2c2c1a0, C4<1>, C4<1>; -L_0x2c2c260 .delay (20000,20000,20000) L_0x2c2c260/d; -L_0x2c2c3b0/d .functor AND 1, L_0x2c2a4e0, L_0x2c2c6d0, C4<1>, C4<1>; -L_0x2c2c3b0 .delay (20000,20000,20000) L_0x2c2c3b0/d; -L_0x2c2c500/d .functor OR 1, L_0x2c2c260, L_0x2c2c3b0, C4<0>, C4<0>; -L_0x2c2c500 .delay (20000,20000,20000) L_0x2c2c500/d; -v0x2b65ec0_0 .net "S", 0 0, L_0x2c2c6d0; 1 drivers -v0x2b65f40_0 .alias "in0", 0 0, v0x2b66dd0_0; -v0x2b65fe0_0 .alias "in1", 0 0, v0x2b66a80_0; -v0x2b66080_0 .net "nS", 0 0, L_0x2c2c1a0; 1 drivers -v0x2b66100_0 .net "out0", 0 0, L_0x2c2c260; 1 drivers -v0x2b661a0_0 .net "out1", 0 0, L_0x2c2c3b0; 1 drivers -v0x2b66280_0 .alias "outfinal", 0 0, v0x2b66d50_0; -S_0x2b647e0 .scope generate, "orbits[30]" "orbits[30]" 3 196, 3 196, S_0x2b62fd0; - .timescale -9 -12; -P_0x2b64558 .param/l "i" 3 196, +C4<011110>; -S_0x2b64910 .scope module, "attempt" "OrNorXor" 3 198, 3 64, S_0x2b647e0; - .timescale -9 -12; -L_0x2c19850/d .functor NOR 1, L_0x2c2cc20, L_0x2c2ccc0, C4<0>, C4<0>; -L_0x2c19850 .delay (10000,10000,10000) L_0x2c19850/d; -L_0x2c2b510/d .functor NOT 1, L_0x2c19850, C4<0>, C4<0>, C4<0>; -L_0x2c2b510 .delay (10000,10000,10000) L_0x2c2b510/d; -L_0x2c2b620/d .functor NAND 1, L_0x2c2cc20, L_0x2c2ccc0, C4<1>, C4<1>; -L_0x2c2b620 .delay (10000,10000,10000) L_0x2c2b620/d; -L_0x2c2cee0/d .functor NAND 1, L_0x2c2b620, L_0x2c2b510, C4<1>, C4<1>; -L_0x2c2cee0 .delay (10000,10000,10000) L_0x2c2cee0/d; -L_0x2c2cf90/d .functor NOT 1, L_0x2c2cee0, C4<0>, C4<0>, C4<0>; -L_0x2c2cf90 .delay (10000,10000,10000) L_0x2c2cf90/d; -v0x2b654c0_0 .net "A", 0 0, L_0x2c2cc20; 1 drivers -v0x2b65560_0 .net "AnandB", 0 0, L_0x2c2b620; 1 drivers -v0x2b65600_0 .net "AnorB", 0 0, L_0x2c19850; 1 drivers -v0x2b656b0_0 .net "AorB", 0 0, L_0x2c2b510; 1 drivers -v0x2b65790_0 .net "AxorB", 0 0, L_0x2c2cf90; 1 drivers -v0x2b65840_0 .net "B", 0 0, L_0x2c2ccc0; 1 drivers -v0x2b65900_0 .alias "Command", 2 0, v0x2bc67a0_0; -v0x2b65980_0 .net "OrNorXorOut", 0 0, L_0x2c2d870; 1 drivers -v0x2b65a00_0 .net "XorNor", 0 0, L_0x2c2d390; 1 drivers -v0x2b65ad0_0 .net "nXor", 0 0, L_0x2c2cee0; 1 drivers -L_0x2c2d4d0 .part v0x2bc78e0_0, 2, 1; -L_0x2c2da00 .part v0x2bc78e0_0, 0, 1; -S_0x2b64f50 .scope module, "mux0" "TwoInMux" 3 83, 3 8, S_0x2b64910; - .timescale -9 -12; -L_0x2c2d0d0/d .functor NOT 1, L_0x2c2d4d0, C4<0>, C4<0>, C4<0>; -L_0x2c2d0d0 .delay (10000,10000,10000) L_0x2c2d0d0/d; -L_0x2c2d170/d .functor AND 1, L_0x2c2cf90, L_0x2c2d0d0, C4<1>, C4<1>; -L_0x2c2d170 .delay (20000,20000,20000) L_0x2c2d170/d; -L_0x2c2d260/d .functor AND 1, L_0x2c19850, L_0x2c2d4d0, C4<1>, C4<1>; -L_0x2c2d260 .delay (20000,20000,20000) L_0x2c2d260/d; -L_0x2c2d390/d .functor OR 1, L_0x2c2d170, L_0x2c2d260, C4<0>, C4<0>; -L_0x2c2d390 .delay (20000,20000,20000) L_0x2c2d390/d; -v0x2b65040_0 .net "S", 0 0, L_0x2c2d4d0; 1 drivers -v0x2b65100_0 .alias "in0", 0 0, v0x2b65790_0; -v0x2b651a0_0 .alias "in1", 0 0, v0x2b65600_0; -v0x2b65240_0 .net "nS", 0 0, L_0x2c2d0d0; 1 drivers -v0x2b652c0_0 .net "out0", 0 0, L_0x2c2d170; 1 drivers -v0x2b65360_0 .net "out1", 0 0, L_0x2c2d260; 1 drivers -v0x2b65440_0 .alias "outfinal", 0 0, v0x2b65a00_0; -S_0x2b64a00 .scope module, "mux1" "TwoInMux" 3 84, 3 8, S_0x2b64910; - .timescale -9 -12; -L_0x2c2d570/d .functor NOT 1, L_0x2c2da00, C4<0>, C4<0>, C4<0>; -L_0x2c2d570 .delay (10000,10000,10000) L_0x2c2d570/d; -L_0x2c2d610/d .functor AND 1, L_0x2c2d390, L_0x2c2d570, C4<1>, C4<1>; -L_0x2c2d610 .delay (20000,20000,20000) L_0x2c2d610/d; -L_0x2c2d740/d .functor AND 1, L_0x2c2b510, L_0x2c2da00, C4<1>, C4<1>; -L_0x2c2d740 .delay (20000,20000,20000) L_0x2c2d740/d; -L_0x2c2d870/d .functor OR 1, L_0x2c2d610, L_0x2c2d740, C4<0>, C4<0>; -L_0x2c2d870 .delay (20000,20000,20000) L_0x2c2d870/d; -v0x2b64af0_0 .net "S", 0 0, L_0x2c2da00; 1 drivers -v0x2b64b70_0 .alias "in0", 0 0, v0x2b65a00_0; -v0x2b64c10_0 .alias "in1", 0 0, v0x2b656b0_0; -v0x2b64cb0_0 .net "nS", 0 0, L_0x2c2d570; 1 drivers -v0x2b64d30_0 .net "out0", 0 0, L_0x2c2d610; 1 drivers -v0x2b64dd0_0 .net "out1", 0 0, L_0x2c2d740; 1 drivers -v0x2b64eb0_0 .alias "outfinal", 0 0, v0x2b65980_0; -S_0x2b63450 .scope generate, "orbits[31]" "orbits[31]" 3 196, 3 196, S_0x2b62fd0; - .timescale -9 -12; -P_0x2b63138 .param/l "i" 3 196, +C4<011111>; -S_0x2b63580 .scope module, "attempt" "OrNorXor" 3 198, 3 64, S_0x2b63450; - .timescale -9 -12; -L_0x2c2cd60/d .functor NOR 1, L_0x2c2ec90, L_0x2c2db40, C4<0>, C4<0>; -L_0x2c2cd60 .delay (10000,10000,10000) L_0x2c2cd60/d; -L_0x2c2ce50/d .functor NOT 1, L_0x2c2cd60, C4<0>, C4<0>, C4<0>; -L_0x2c2ce50 .delay (10000,10000,10000) L_0x2c2ce50/d; -L_0x2c2deb0/d .functor NAND 1, L_0x2c2ec90, L_0x2c2db40, C4<1>, C4<1>; -L_0x2c2deb0 .delay (10000,10000,10000) L_0x2c2deb0/d; -L_0x2c2dfa0/d .functor NAND 1, L_0x2c2deb0, L_0x2c2ce50, C4<1>, C4<1>; -L_0x2c2dfa0 .delay (10000,10000,10000) L_0x2c2dfa0/d; -L_0x2c2e0e0/d .functor NOT 1, L_0x2c2dfa0, C4<0>, C4<0>, C4<0>; -L_0x2c2e0e0 .delay (10000,10000,10000) L_0x2c2e0e0/d; -v0x2b64150_0 .net "A", 0 0, L_0x2c2ec90; 1 drivers -v0x2b641f0_0 .net "AnandB", 0 0, L_0x2c2deb0; 1 drivers -v0x2b64290_0 .net "AnorB", 0 0, L_0x2c2cd60; 1 drivers -v0x2b64340_0 .net "AorB", 0 0, L_0x2c2ce50; 1 drivers -v0x2b64420_0 .net "AxorB", 0 0, L_0x2c2e0e0; 1 drivers -v0x2b644d0_0 .net "B", 0 0, L_0x2c2db40; 1 drivers -v0x2b64590_0 .alias "Command", 2 0, v0x2bc67a0_0; -v0x2b64610_0 .net "OrNorXorOut", 0 0, L_0x2c2e9c0; 1 drivers -v0x2b64690_0 .net "XorNor", 0 0, L_0x2c2e4e0; 1 drivers -v0x2b64760_0 .net "nXor", 0 0, L_0x2c2dfa0; 1 drivers -L_0x2c2e620 .part v0x2bc78e0_0, 2, 1; -L_0x2c2eb50 .part v0x2bc78e0_0, 0, 1; -S_0x2b63be0 .scope module, "mux0" "TwoInMux" 3 83, 3 8, S_0x2b63580; - .timescale -9 -12; -L_0x2c2e220/d .functor NOT 1, L_0x2c2e620, C4<0>, C4<0>, C4<0>; -L_0x2c2e220 .delay (10000,10000,10000) L_0x2c2e220/d; -L_0x2c2e2c0/d .functor AND 1, L_0x2c2e0e0, L_0x2c2e220, C4<1>, C4<1>; -L_0x2c2e2c0 .delay (20000,20000,20000) L_0x2c2e2c0/d; -L_0x2c2e3b0/d .functor AND 1, L_0x2c2cd60, L_0x2c2e620, C4<1>, C4<1>; -L_0x2c2e3b0 .delay (20000,20000,20000) L_0x2c2e3b0/d; -L_0x2c2e4e0/d .functor OR 1, L_0x2c2e2c0, L_0x2c2e3b0, C4<0>, C4<0>; -L_0x2c2e4e0 .delay (20000,20000,20000) L_0x2c2e4e0/d; -v0x2b63cd0_0 .net "S", 0 0, L_0x2c2e620; 1 drivers -v0x2b63d90_0 .alias "in0", 0 0, v0x2b64420_0; -v0x2b63e30_0 .alias "in1", 0 0, v0x2b64290_0; -v0x2b63ed0_0 .net "nS", 0 0, L_0x2c2e220; 1 drivers -v0x2b63f50_0 .net "out0", 0 0, L_0x2c2e2c0; 1 drivers -v0x2b63ff0_0 .net "out1", 0 0, L_0x2c2e3b0; 1 drivers -v0x2b640d0_0 .alias "outfinal", 0 0, v0x2b64690_0; -S_0x2b63670 .scope module, "mux1" "TwoInMux" 3 84, 3 8, S_0x2b63580; - .timescale -9 -12; -L_0x2c2e6c0/d .functor NOT 1, L_0x2c2eb50, C4<0>, C4<0>, C4<0>; -L_0x2c2e6c0 .delay (10000,10000,10000) L_0x2c2e6c0/d; -L_0x2c2e760/d .functor AND 1, L_0x2c2e4e0, L_0x2c2e6c0, C4<1>, C4<1>; -L_0x2c2e760 .delay (20000,20000,20000) L_0x2c2e760/d; -L_0x2c2e890/d .functor AND 1, L_0x2c2ce50, L_0x2c2eb50, C4<1>, C4<1>; -L_0x2c2e890 .delay (20000,20000,20000) L_0x2c2e890/d; -L_0x2c2e9c0/d .functor OR 1, L_0x2c2e760, L_0x2c2e890, C4<0>, C4<0>; -L_0x2c2e9c0 .delay (20000,20000,20000) L_0x2c2e9c0/d; -v0x2b63760_0 .net "S", 0 0, L_0x2c2eb50; 1 drivers -v0x2b63800_0 .alias "in0", 0 0, v0x2b64690_0; -v0x2b638a0_0 .alias "in1", 0 0, v0x2b64340_0; -v0x2b63940_0 .net "nS", 0 0, L_0x2c2e6c0; 1 drivers -v0x2b639c0_0 .net "out0", 0 0, L_0x2c2e760; 1 drivers -v0x2b63a60_0 .net "out1", 0 0, L_0x2c2e890; 1 drivers -v0x2b63b40_0 .alias "outfinal", 0 0, v0x2b64610_0; -S_0x29738d0 .scope module, "superalu" "Bitslice32" 2 147, 3 256, S_0x270e6d0; - .timescale -9 -12; -P_0x26c6208 .param/l "size" 3 273, +C4<0100000>; -L_0x2c58ef0/d .functor AND 1, L_0x2c43660, L_0x2c43700, C4<1>, C4<1>; -L_0x2c58ef0 .delay (20000,20000,20000) L_0x2c58ef0/d; -L_0x2c437f0/d .functor NOT 1, L_0x2c438e0, C4<0>, C4<0>, C4<0>; -L_0x2c437f0 .delay (10000,10000,10000) L_0x2c437f0/d; -L_0x2c43980/d .functor AND 1, L_0x2c437f0, L_0x2c437f0, C4<1>, C4<1>; -L_0x2c43980 .delay (20000,20000,20000) L_0x2c43980/d; -v0x2b60fd0_0 .alias "A", 31 0, v0x2bc6580_0; -v0x2b611c0_0 .alias "AddSubSLTSum", 31 0, v0x2bc76e0_0; -v0x2b61240_0 .alias "AllZeros", 0 0, v0x2bc7760_0; -v0x2b612c0_0 .alias "AndNandOut", 31 0, v0x2bc77e0_0; -v0x2b61370_0 .alias "B", 31 0, v0x2bc66a0_0; -RS_0x7f99c4320ec8/0/0 .resolv tri, L_0x2c30990, L_0x2c33340, L_0x2c35cb0, L_0x2c384c0; -RS_0x7f99c4320ec8/0/4 .resolv tri, L_0x2c3aef0, L_0x2c3d700, L_0x2c3fd30, L_0x2c42490; -RS_0x7f99c4320ec8/0/8 .resolv tri, L_0x2c450c0, L_0x2c47c20, L_0x2c4a7e0, L_0x2c4cf50; -RS_0x7f99c4320ec8/0/12 .resolv tri, L_0x2c4f700, L_0x2c51e30, L_0x2c545c0, L_0x2c57150; -RS_0x7f99c4320ec8/0/16 .resolv tri, L_0x2c5a110, L_0x2c5c880, L_0x2c5e350, L_0x2c60810; -RS_0x7f99c4320ec8/0/20 .resolv tri, L_0x2c63ee0, L_0x2c66650, L_0x2c67f00, L_0x2c6a680; -RS_0x7f99c4320ec8/0/24 .resolv tri, L_0x2c6cde0, L_0x2be19c0, L_0x2c736c0, L_0x2c75e70; -RS_0x7f99c4320ec8/0/28 .resolv tri, L_0x2c78950, L_0x2c7af00, L_0x2c7d710, L_0x2ce9150; -RS_0x7f99c4320ec8/1/0 .resolv tri, RS_0x7f99c4320ec8/0/0, RS_0x7f99c4320ec8/0/4, RS_0x7f99c4320ec8/0/8, RS_0x7f99c4320ec8/0/12; -RS_0x7f99c4320ec8/1/4 .resolv tri, RS_0x7f99c4320ec8/0/16, RS_0x7f99c4320ec8/0/20, RS_0x7f99c4320ec8/0/24, RS_0x7f99c4320ec8/0/28; -RS_0x7f99c4320ec8 .resolv tri, RS_0x7f99c4320ec8/1/0, RS_0x7f99c4320ec8/1/4, C4, C4; -v0x2b613f0_0 .net8 "Cmd0Start", 31 0, RS_0x7f99c4320ec8; 32 drivers -RS_0x7f99c4320ef8/0/0 .resolv tri, L_0x2c31870, L_0x2c34200, L_0x2c36b60, L_0x2c39350; -RS_0x7f99c4320ef8/0/4 .resolv tri, L_0x2c3bda0, L_0x2c3e590, L_0x2c40ba0, L_0x2c43350; -RS_0x7f99c4320ef8/0/8 .resolv tri, L_0x2c46340, L_0x2c48ac0, L_0x2c4b660, L_0x2c4dde0; -RS_0x7f99c4320ef8/0/12 .resolv tri, L_0x2c50590, L_0x2c52cc0, L_0x2c55450, L_0x2c57fb0; -RS_0x7f99c4320ef8/0/16 .resolv tri, L_0x2c5af80, L_0x2c5d6e0, L_0x2c5fe80, L_0x2c61820; -RS_0x7f99c4320ef8/0/20 .resolv tri, L_0x2c63660, L_0x2c67500, L_0x2c69cf0, L_0x2c6c470; -RS_0x7f99c4320ef8/0/24 .resolv tri, L_0x2be2160, L_0x2c72140, L_0x2c749a0, L_0x2c76f50; -RS_0x7f99c4320ef8/0/28 .resolv tri, L_0x2c79760, L_0x2c7bf20, L_0x2c45f50, L_0x2c83420; -RS_0x7f99c4320ef8/1/0 .resolv tri, RS_0x7f99c4320ef8/0/0, RS_0x7f99c4320ef8/0/4, RS_0x7f99c4320ef8/0/8, RS_0x7f99c4320ef8/0/12; -RS_0x7f99c4320ef8/1/4 .resolv tri, RS_0x7f99c4320ef8/0/16, RS_0x7f99c4320ef8/0/20, RS_0x7f99c4320ef8/0/24, RS_0x7f99c4320ef8/0/28; -RS_0x7f99c4320ef8 .resolv tri, RS_0x7f99c4320ef8/1/0, RS_0x7f99c4320ef8/1/4, C4, C4; -v0x2b61470_0 .net8 "Cmd1Start", 31 0, RS_0x7f99c4320ef8; 32 drivers -v0x2b614f0_0 .alias "Command", 2 0, v0x2bc67a0_0; -v0x2b61570_0 .alias "OneBitFinalOut", 31 0, v0x2bc7960_0; -v0x2b61610_0 .alias "OrNorXorOut", 31 0, v0x2bc79e0_0; -v0x2b61690_0 .alias "SLTflag", 0 0, v0x2bc7a60_0; -v0x2b61740_0 .alias "ZeroFlag", 31 0, v0x2bc7ae0_0; -v0x2b617c0_0 .net *"_s121", 0 0, L_0x2c3c500; 1 drivers -v0x2b61840_0 .net *"_s146", 0 0, L_0x2c3ea80; 1 drivers -v0x2b61960_0 .net *"_s171", 0 0, L_0x2c41410; 1 drivers -v0x2b61a00_0 .net *"_s196", 0 0, L_0x2c3a2c0; 1 drivers -v0x2b618c0_0 .net *"_s21", 0 0, L_0x2c32930; 1 drivers -v0x2b61b50_0 .net *"_s221", 0 0, L_0x2c46660; 1 drivers -v0x2b61c70_0 .net *"_s246", 0 0, L_0x2c48e70; 1 drivers -v0x2b61cf0_0 .net *"_s271", 0 0, L_0x2c4b980; 1 drivers -v0x2b61bd0_0 .net *"_s296", 0 0, L_0x2c4e2d0; 1 drivers -v0x2b61e20_0 .net *"_s321", 0 0, L_0x2c508b0; 1 drivers -v0x2b61d70_0 .net *"_s346", 0 0, L_0x2c53020; 1 drivers -v0x2b61f60_0 .net *"_s371", 0 0, L_0x2c55070; 1 drivers -v0x2b61ec0_0 .net *"_s396", 0 0, L_0x2c44580; 1 drivers -v0x2b620b0_0 .net *"_s421", 0 0, L_0x2c5b0c0; 1 drivers -v0x2b62000_0 .net *"_s446", 0 0, L_0x2c5d8b0; 1 drivers -v0x2b62210_0 .net *"_s46", 0 0, L_0x2c34850; 1 drivers -v0x2b62150_0 .net *"_s471", 0 0, L_0x2c60c30; 1 drivers -v0x2b62380_0 .net *"_s496", 0 0, L_0x2c62600; 1 drivers -v0x2b62290_0 .net *"_s521", 0 0, L_0x2c64b40; 1 drivers -v0x2b62500_0 .net *"_s546", 0 0, L_0x2c672d0; 1 drivers -v0x2b62400_0 .net *"_s571", 0 0, L_0x2c692d0; 1 drivers -v0x2b62690_0 .net *"_s596", 0 0, L_0x2c6b960; 1 drivers -v0x2b62580_0 .net *"_s621", 0 0, L_0x2be0ef0; 1 drivers -v0x2b62830_0 .net *"_s646", 0 0, L_0x2c72bf0; 1 drivers -v0x2b62710_0 .net *"_s671", 0 0, L_0x2c753e0; 1 drivers -v0x2b627b0_0 .net *"_s696", 0 0, L_0x2c77e50; 1 drivers -v0x2b629f0_0 .net *"_s71", 0 0, L_0x2c37800; 1 drivers -v0x2b62a70_0 .net *"_s721", 0 0, L_0x2c7a4a0; 1 drivers -v0x2b628b0_0 .net *"_s746", 0 0, L_0x2c7cc40; 1 drivers -v0x2b62950_0 .net *"_s771", 0 0, L_0x2c49a50; 1 drivers -v0x2b62c50_0 .net *"_s811", 0 0, L_0x2c58ef0; 1 drivers -v0x2b62cd0_0 .net *"_s814", 0 0, L_0x2c43660; 1 drivers -v0x2b62af0_0 .net *"_s816", 0 0, L_0x2c43700; 1 drivers -v0x2b62b90_0 .net *"_s818", 0 0, L_0x2c438e0; 1 drivers -v0x2b62ed0_0 .net *"_s96", 0 0, L_0x2c34f80; 1 drivers -v0x2b62f50_0 .alias "carryin", 31 0, v0x2bc71d0_0; -v0x2b62d80_0 .alias "carryout", 0 0, v0x2bc7be0_0; -v0x2b62e30_0 .alias "overflow", 0 0, v0x2bc7c60_0; -v0x2b631a0_0 .alias "subtract", 31 0, v0x2bc7ce0_0; -v0x2b63220_0 .net "yeszero", 0 0, L_0x2c437f0; 1 drivers -L_0x2c30990 .part/pv L_0x2c30780, 1, 1, 32; -L_0x2c30a30 .part v0x2bc78e0_0, 0, 1; -L_0x2c30b60 .part v0x2bc78e0_0, 1, 1; -L_0x2c30c90 .part RS_0x7f99c4320aa8, 1, 1; -L_0x2c30d30 .part RS_0x7f99c4320aa8, 1, 1; -L_0x2c30dd0 .part RS_0x7f99c4316848, 1, 1; -L_0x2c30f00 .part RS_0x7f99c4320aa8, 1, 1; -L_0x2c31870 .part/pv L_0x2c31630, 1, 1, 32; -L_0x2c31960 .part v0x2bc78e0_0, 0, 1; -L_0x2c31a90 .part v0x2bc78e0_0, 1, 1; -L_0x2c31c20 .part RS_0x7f99c4319e78, 1, 1; -L_0x2c31cc0 .part RS_0x7f99c4319e78, 1, 1; -L_0x2c31dd0 .part RS_0x7f99c4316848, 1, 1; -L_0x2c31e70 .part RS_0x7f99c4316848, 1, 1; -L_0x2c32350 .part/pv L_0x2c32210, 1, 1, 32; -L_0x2c32440 .part v0x2bc78e0_0, 2, 1; -L_0x2c32570 .part RS_0x7f99c4320ec8, 1, 1; -L_0x2c326b0 .part RS_0x7f99c4320ef8, 1, 1; -L_0x2c32890 .part/pv L_0x2c32930, 1, 1, 32; -L_0x2c32a30 .part RS_0x7f99c4320f58, 0, 1; -L_0x2c327f0 .part RS_0x7f99c4320f28, 1, 1; -L_0x2c33340 .part/pv L_0x2c33160, 2, 1, 32; -L_0x2c32ad0 .part v0x2bc78e0_0, 0, 1; -L_0x2c33530 .part v0x2bc78e0_0, 1, 1; -L_0x2c333e0 .part RS_0x7f99c4320aa8, 2, 1; -L_0x2c33730 .part RS_0x7f99c4320aa8, 2, 1; -L_0x2c33660 .part RS_0x7f99c4316848, 2, 1; -L_0x2c33900 .part RS_0x7f99c4320aa8, 2, 1; -L_0x2c34200 .part/pv L_0x2c33ff0, 2, 1, 32; -L_0x2c342a0 .part v0x2bc78e0_0, 0, 1; -L_0x2c339f0 .part v0x2bc78e0_0, 1, 1; -L_0x2c34560 .part RS_0x7f99c4319e78, 2, 1; -L_0x2c343d0 .part RS_0x7f99c4319e78, 2, 1; -L_0x2c34710 .part RS_0x7f99c4316848, 2, 1; -L_0x2c34600 .part RS_0x7f99c4316848, 2, 1; -L_0x2c34c80 .part/pv L_0x2c34b40, 2, 1, 32; -L_0x2c347b0 .part v0x2bc78e0_0, 2, 1; -L_0x2c34ee0 .part RS_0x7f99c4320ec8, 2, 1; -L_0x2c34db0 .part RS_0x7f99c4320ef8, 2, 1; -L_0x2c35150 .part/pv L_0x2c34850, 2, 1, 32; -L_0x2c35050 .part RS_0x7f99c4320f58, 1, 1; -L_0x2c353d0 .part RS_0x7f99c4320f28, 2, 1; -L_0x2c35cb0 .part/pv L_0x2c35aa0, 3, 1, 32; -L_0x2c35d50 .part v0x2bc78e0_0, 0, 1; -L_0x2c35470 .part v0x2bc78e0_0, 1, 1; -L_0x2c35ff0 .part RS_0x7f99c4320aa8, 3, 1; -L_0x2c35e80 .part RS_0x7f99c4320aa8, 3, 1; -L_0x2c35f20 .part RS_0x7f99c4316848, 3, 1; -L_0x2c36090 .part RS_0x7f99c4320aa8, 3, 1; -L_0x2c36b60 .part/pv L_0x2c36950, 3, 1, 32; -L_0x2c36260 .part v0x2bc78e0_0, 0, 1; -L_0x2c36da0 .part v0x2bc78e0_0, 1, 1; -L_0x2c36c00 .part RS_0x7f99c4319e78, 3, 1; -L_0x2c36ca0 .part RS_0x7f99c4319e78, 3, 1; -L_0x2c37090 .part RS_0x7f99c4316848, 3, 1; -L_0x2c37130 .part RS_0x7f99c4316848, 3, 1; -L_0x2c37620 .part/pv L_0x2c374e0, 3, 1, 32; -L_0x2c376c0 .part v0x2bc78e0_0, 2, 1; -L_0x2c371d0 .part RS_0x7f99c4320ec8, 3, 1; -L_0x2c372c0 .part RS_0x7f99c4320ef8, 3, 1; -L_0x2c37760 .part/pv L_0x2c37800, 3, 1, 32; -L_0x2c37b80 .part RS_0x7f99c4320f58, 2, 1; -L_0x2c37990 .part RS_0x7f99c4320f28, 3, 1; -L_0x2c384c0 .part/pv L_0x2c382b0, 4, 1, 32; -L_0x2c37c20 .part v0x2bc78e0_0, 0, 1; -L_0x2c37d50 .part v0x2bc78e0_0, 1, 1; -L_0x2c38560 .part RS_0x7f99c4320aa8, 4, 1; -L_0x2c38600 .part RS_0x7f99c4320aa8, 4, 1; -L_0x2c386a0 .part RS_0x7f99c4316848, 4, 1; -L_0x2c38a80 .part RS_0x7f99c4320aa8, 4, 1; -L_0x2c39350 .part/pv L_0x2c39140, 4, 1, 32; -L_0x2c393f0 .part v0x2bc78e0_0, 0, 1; -L_0x2c38b70 .part v0x2bc78e0_0, 1, 1; -L_0x2c38ca0 .part RS_0x7f99c4319e78, 4, 1; -L_0x2c39780 .part RS_0x7f99c4319e78, 4, 1; -L_0x2c39820 .part RS_0x7f99c4316848, 4, 1; -L_0x2c39520 .part RS_0x7f99c4316848, 4, 1; -L_0x2c39df0 .part/pv L_0x2c39cb0, 4, 1, 32; -L_0x2c398c0 .part v0x2bc78e0_0, 2, 1; -L_0x2c39960 .part RS_0x7f99c4320ec8, 4, 1; -L_0x2c39a50 .part RS_0x7f99c4320ef8, 4, 1; -L_0x2c3a0b0 .part/pv L_0x2c34f80, 4, 1, 32; -L_0x2c3a150 .part RS_0x7f99c4320f58, 3, 1; -L_0x2c3a330 .part RS_0x7f99c4320f28, 4, 1; -L_0x2c3aef0 .part/pv L_0x2c3ace0, 5, 1, 32; -L_0x2c3af90 .part v0x2bc78e0_0, 0, 1; -L_0x2c3a6d0 .part v0x2bc78e0_0, 1, 1; -L_0x2c3a800 .part RS_0x7f99c4320aa8, 5, 1; -L_0x2c3a8a0 .part RS_0x7f99c4320aa8, 5, 1; -L_0x2c3b390 .part RS_0x7f99c4316848, 5, 1; -L_0x2c3b0c0 .part RS_0x7f99c4320aa8, 5, 1; -L_0x2c3bda0 .part/pv L_0x2c3bb90, 5, 1, 32; -L_0x2c3b480 .part v0x2bc78e0_0, 0, 1; -L_0x2c3b5b0 .part v0x2bc78e0_0, 1, 1; -L_0x2c3c140 .part RS_0x7f99c4319e78, 5, 1; -L_0x2c3c1e0 .part RS_0x7f99c4319e78, 5, 1; -L_0x2c3be40 .part RS_0x7f99c4316848, 5, 1; -L_0x2c3bf30 .part RS_0x7f99c4316848, 5, 1; -L_0x2c3c860 .part/pv L_0x2c3c720, 5, 1, 32; -L_0x2c3c900 .part v0x2bc78e0_0, 2, 1; -L_0x2c3c280 .part RS_0x7f99c4320ec8, 5, 1; -L_0x2c3c370 .part RS_0x7f99c4320ef8, 5, 1; -L_0x2c3c460 .part/pv L_0x2c3c500, 5, 1, 32; -L_0x2c3cd80 .part RS_0x7f99c4320f58, 4, 1; -L_0x2c3c9a0 .part RS_0x7f99c4320f28, 5, 1; -L_0x2c3d700 .part/pv L_0x2c3d4f0, 6, 1, 32; -L_0x2c3ce20 .part v0x2bc78e0_0, 0, 1; -L_0x2c3cf50 .part v0x2bc78e0_0, 1, 1; -L_0x2c3d080 .part RS_0x7f99c4320aa8, 6, 1; -L_0x2c3db10 .part RS_0x7f99c4320aa8, 6, 1; -L_0x2c3d7a0 .part RS_0x7f99c4316848, 6, 1; -L_0x2c3d840 .part RS_0x7f99c4320aa8, 6, 1; -L_0x2c3e590 .part/pv L_0x2c3e380, 6, 1, 32; -L_0x2c3e630 .part v0x2bc78e0_0, 0, 1; -L_0x2c3dbb0 .part v0x2bc78e0_0, 1, 1; -L_0x2c3dce0 .part RS_0x7f99c4319e78, 6, 1; -L_0x2c3dd80 .part RS_0x7f99c4319e78, 6, 1; -L_0x2c3de20 .part RS_0x7f99c4316848, 6, 1; -L_0x2c3eb20 .part RS_0x7f99c4316848, 6, 1; -L_0x2c3f020 .part/pv L_0x2c3eee0, 6, 1, 32; -L_0x2c3e760 .part v0x2bc78e0_0, 2, 1; -L_0x2c3e800 .part RS_0x7f99c4320ec8, 6, 1; -L_0x2c3e8f0 .part RS_0x7f99c4320ef8, 6, 1; -L_0x2c3e9e0 .part/pv L_0x2c3ea80, 6, 1, 32; -L_0x2c3f550 .part RS_0x7f99c4320f58, 5, 1; -L_0x2c3f5f0 .part RS_0x7f99c4320f28, 6, 1; -L_0x2c3fd30 .part/pv L_0x2c3fb20, 7, 1, 32; -L_0x2c3fdd0 .part v0x2bc78e0_0, 0, 1; -L_0x2c3f6e0 .part v0x2bc78e0_0, 1, 1; -L_0x2c3f810 .part RS_0x7f99c4320aa8, 7, 1; -L_0x2c3f8b0 .part RS_0x7f99c4320aa8, 7, 1; -L_0x2c3f950 .part RS_0x7f99c4316848, 7, 1; -L_0x2c3fa40 .part RS_0x7f99c4320aa8, 7, 1; -L_0x2c40ba0 .part/pv L_0x2c40990, 7, 1, 32; -L_0x2c3ff00 .part v0x2bc78e0_0, 0, 1; -L_0x2c40030 .part v0x2bc78e0_0, 1, 1; -L_0x2c40160 .part RS_0x7f99c4319e78, 7, 1; -L_0x2c40200 .part RS_0x7f99c4319e78, 7, 1; -L_0x2c410a0 .part RS_0x7f99c4316848, 7, 1; -L_0x2c41140 .part RS_0x7f99c4316848, 7, 1; -L_0x2c40fb0 .part/pv L_0x2c40e70, 7, 1, 32; -L_0x2c41650 .part v0x2bc78e0_0, 2, 1; -L_0x2c411e0 .part RS_0x7f99c4320ec8, 7, 1; -L_0x2c41280 .part RS_0x7f99c4320ef8, 7, 1; -L_0x2c41370 .part/pv L_0x2c41410, 7, 1, 32; -L_0x2c41550 .part RS_0x7f99c4320f58, 6, 1; -L_0x2c41b90 .part RS_0x7f99c4320f28, 7, 1; -L_0x2c42490 .part/pv L_0x2c42280, 8, 1, 32; -L_0x2c416f0 .part v0x2bc78e0_0, 0, 1; -L_0x2c41820 .part v0x2bc78e0_0, 1, 1; -L_0x2c41950 .part RS_0x7f99c4320aa8, 8, 1; -L_0x2c419f0 .part RS_0x7f99c4320aa8, 8, 1; -L_0x2c41a90 .part RS_0x7f99c4316848, 8, 1; -L_0x2c42a00 .part RS_0x7f99c4320aa8, 8, 1; -L_0x2c43350 .part/pv L_0x2c43140, 8, 1, 32; -L_0x2c433f0 .part v0x2bc78e0_0, 0, 1; -L_0x2c42af0 .part v0x2bc78e0_0, 1, 1; -L_0x2c42c20 .part RS_0x7f99c4319e78, 8, 1; -L_0x2c42cc0 .part RS_0x7f99c4319e78, 8, 1; -L_0x2c42d60 .part RS_0x7f99c4316848, 8, 1; -L_0x2c42e50 .part RS_0x7f99c4316848, 8, 1; -L_0x2c43da0 .part/pv L_0x2c43c60, 8, 1, 32; -L_0x2c39e90 .part v0x2bc78e0_0, 2, 1; -L_0x2c43520 .part RS_0x7f99c4320ec8, 8, 1; -L_0x2c3a220 .part RS_0x7f99c4320ef8, 8, 1; -L_0x2c39f80 .part/pv L_0x2c3a2c0, 8, 1, 32; -L_0x2c3a610 .part RS_0x7f99c4320f58, 7, 1; -L_0x2c44050 .part RS_0x7f99c4320f28, 8, 1; -L_0x2c450c0 .part/pv L_0x2c44eb0, 9, 1, 32; -L_0x2c45160 .part v0x2bc78e0_0, 0, 1; -L_0x2c44790 .part v0x2bc78e0_0, 1, 1; -L_0x2c448c0 .part RS_0x7f99c4320aa8, 9, 1; -L_0x2c44960 .part RS_0x7f99c4320aa8, 9, 1; -L_0x2c44a00 .part RS_0x7f99c4316848, 9, 1; -L_0x2c44af0 .part RS_0x7f99c4320aa8, 9, 1; -L_0x2c46340 .part/pv L_0x2c46130, 9, 1, 32; -L_0x2c45290 .part v0x2bc78e0_0, 0, 1; -L_0x2c453c0 .part v0x2bc78e0_0, 1, 1; -L_0x2c454f0 .part RS_0x7f99c4319e78, 9, 1; -L_0x2c45590 .part RS_0x7f99c4319e78, 9, 1; -L_0x2c45630 .part RS_0x7f99c4316848, 9, 1; -L_0x2c45720 .part RS_0x7f99c4316848, 9, 1; -L_0x2c46d50 .part/pv L_0x2c46c10, 9, 1, 32; -L_0x2c46df0 .part v0x2bc78e0_0, 2, 1; -L_0x2c463e0 .part RS_0x7f99c4320ec8, 9, 1; -L_0x2c464d0 .part RS_0x7f99c4320ef8, 9, 1; -L_0x2c465c0 .part/pv L_0x2c46660, 9, 1, 32; -L_0x2c467a0 .part RS_0x7f99c4320f58, 8, 1; -L_0x2c46840 .part RS_0x7f99c4320f28, 9, 1; -L_0x2c47c20 .part/pv L_0x2c47a10, 10, 1, 32; -L_0x2c46e90 .part v0x2bc78e0_0, 0, 1; -L_0x2c46fc0 .part v0x2bc78e0_0, 1, 1; -L_0x2c470f0 .part RS_0x7f99c4320aa8, 10, 1; -L_0x2c47190 .part RS_0x7f99c4320aa8, 10, 1; -L_0x2c47230 .part RS_0x7f99c4316848, 10, 1; -L_0x2c47320 .part RS_0x7f99c4320aa8, 10, 1; -L_0x2c48ac0 .part/pv L_0x2c488b0, 10, 1, 32; -L_0x2c48b60 .part v0x2bc78e0_0, 0, 1; -L_0x2c47cc0 .part v0x2bc78e0_0, 1, 1; -L_0x2c47df0 .part RS_0x7f99c4319e78, 10, 1; -L_0x2c47e90 .part RS_0x7f99c4319e78, 10, 1; -L_0x2c47f30 .part RS_0x7f99c4316848, 10, 1; -L_0x2c48020 .part RS_0x7f99c4316848, 10, 1; -L_0x2c2ca00 .part/pv L_0x2c2c8c0, 10, 1, 32; -L_0x2c2caa0 .part v0x2bc78e0_0, 2, 1; -L_0x2c2cb40 .part RS_0x7f99c4320ec8, 10, 1; -L_0x2c48ce0 .part RS_0x7f99c4320ef8, 10, 1; -L_0x2c48dd0 .part/pv L_0x2c48e70, 10, 1, 32; -L_0x2c48f70 .part RS_0x7f99c4320f58, 9, 1; -L_0x2c49010 .part RS_0x7f99c4320f28, 10, 1; -L_0x2c4a7e0 .part/pv L_0x2c4a5d0, 11, 1, 32; -L_0x2c4a880 .part v0x2bc78e0_0, 0, 1; -L_0x2c49af0 .part v0x2bc78e0_0, 1, 1; -L_0x2c49c20 .part RS_0x7f99c4320aa8, 11, 1; -L_0x2c49cc0 .part RS_0x7f99c4320aa8, 11, 1; -L_0x2c49d60 .part RS_0x7f99c4316848, 11, 1; -L_0x2c49e50 .part RS_0x7f99c4320aa8, 11, 1; -L_0x2c4b660 .part/pv L_0x2c4b450, 11, 1, 32; -L_0x2c4a9b0 .part v0x2bc78e0_0, 0, 1; -L_0x2c4aae0 .part v0x2bc78e0_0, 1, 1; -L_0x2c4ac10 .part RS_0x7f99c4319e78, 11, 1; -L_0x2c4acb0 .part RS_0x7f99c4319e78, 11, 1; -L_0x2c4ad50 .part RS_0x7f99c4316848, 11, 1; -L_0x2c4ae40 .part RS_0x7f99c4316848, 11, 1; -L_0x2c4c090 .part/pv L_0x2c4bf50, 11, 1, 32; -L_0x2c4c130 .part v0x2bc78e0_0, 2, 1; -L_0x2c4b700 .part RS_0x7f99c4320ec8, 11, 1; -L_0x2c4b7f0 .part RS_0x7f99c4320ef8, 11, 1; -L_0x2c4b8e0 .part/pv L_0x2c4b980, 11, 1, 32; -L_0x2c4bac0 .part RS_0x7f99c4320f58, 10, 1; -L_0x2c4bb60 .part RS_0x7f99c4320f28, 11, 1; -L_0x2c4cf50 .part/pv L_0x2c4cd40, 12, 1, 32; -L_0x2c4c1d0 .part v0x2bc78e0_0, 0, 1; -L_0x2c4c300 .part v0x2bc78e0_0, 1, 1; -L_0x2c4c430 .part RS_0x7f99c4320aa8, 12, 1; -L_0x2c4c4d0 .part RS_0x7f99c4320aa8, 12, 1; -L_0x2c4c570 .part RS_0x7f99c4316848, 12, 1; -L_0x2c4c660 .part RS_0x7f99c4320aa8, 12, 1; -L_0x2c4dde0 .part/pv L_0x2c4dbd0, 12, 1, 32; -L_0x2c4de80 .part v0x2bc78e0_0, 0, 1; -L_0x2c4cff0 .part v0x2bc78e0_0, 1, 1; -L_0x2c4d120 .part RS_0x7f99c4319e78, 12, 1; -L_0x2c4d1c0 .part RS_0x7f99c4319e78, 12, 1; -L_0x2c4d260 .part RS_0x7f99c4316848, 12, 1; -L_0x2c4d350 .part RS_0x7f99c4316848, 12, 1; -L_0x2c4e800 .part/pv L_0x2c4d6d0, 12, 1, 32; -L_0x2c4dfb0 .part v0x2bc78e0_0, 2, 1; -L_0x2c4e050 .part RS_0x7f99c4320ec8, 12, 1; -L_0x2c4e140 .part RS_0x7f99c4320ef8, 12, 1; -L_0x2c4e230 .part/pv L_0x2c4e2d0, 12, 1, 32; -L_0x2c4e410 .part RS_0x7f99c4320f58, 11, 1; -L_0x2c4e4b0 .part RS_0x7f99c4320f28, 12, 1; -L_0x2c4f700 .part/pv L_0x2c4f4f0, 13, 1, 32; -L_0x2c4f7a0 .part v0x2bc78e0_0, 0, 1; -L_0x2c4e8a0 .part v0x2bc78e0_0, 1, 1; -L_0x2c4e9d0 .part RS_0x7f99c4320aa8, 13, 1; -L_0x2c4ea70 .part RS_0x7f99c4320aa8, 13, 1; -L_0x2c4eb10 .part RS_0x7f99c4316848, 13, 1; -L_0x2c4ec00 .part RS_0x7f99c4320aa8, 13, 1; -L_0x2c50590 .part/pv L_0x2c50380, 13, 1, 32; -L_0x2c4f8d0 .part v0x2bc78e0_0, 0, 1; -L_0x2c4fa00 .part v0x2bc78e0_0, 1, 1; -L_0x2c4fb30 .part RS_0x7f99c4319e78, 13, 1; -L_0x2c4fbd0 .part RS_0x7f99c4319e78, 13, 1; -L_0x2c4fc70 .part RS_0x7f99c4316848, 13, 1; -L_0x2c4fd60 .part RS_0x7f99c4316848, 13, 1; -L_0x2c50fd0 .part/pv L_0x2c50e90, 13, 1, 32; -L_0x2c51070 .part v0x2bc78e0_0, 2, 1; -L_0x2c50630 .part RS_0x7f99c4320ec8, 13, 1; -L_0x2c50720 .part RS_0x7f99c4320ef8, 13, 1; -L_0x2c50810 .part/pv L_0x2c508b0, 13, 1, 32; -L_0x2c509f0 .part RS_0x7f99c4320f58, 12, 1; -L_0x2c50a90 .part RS_0x7f99c4320f28, 13, 1; -L_0x2c51e30 .part/pv L_0x2c51c20, 14, 1, 32; -L_0x2c51110 .part v0x2bc78e0_0, 0, 1; -L_0x2c51240 .part v0x2bc78e0_0, 1, 1; -L_0x2c51370 .part RS_0x7f99c4320aa8, 14, 1; -L_0x2c51410 .part RS_0x7f99c4320aa8, 14, 1; -L_0x2c514b0 .part RS_0x7f99c4316848, 14, 1; -L_0x2c515a0 .part RS_0x7f99c4320aa8, 14, 1; -L_0x2c52cc0 .part/pv L_0x2c52ab0, 14, 1, 32; -L_0x2c52d60 .part v0x2bc78e0_0, 0, 1; -L_0x2c51ed0 .part v0x2bc78e0_0, 1, 1; -L_0x2c52000 .part RS_0x7f99c4319e78, 14, 1; -L_0x2c520a0 .part RS_0x7f99c4319e78, 14, 1; -L_0x2c52140 .part RS_0x7f99c4316848, 14, 1; -L_0x2c52230 .part RS_0x7f99c4316848, 14, 1; -L_0x2c526f0 .part/pv L_0x2c525b0, 14, 1, 32; -L_0x2c537a0 .part v0x2bc78e0_0, 2, 1; -L_0x2c53840 .part RS_0x7f99c4320ec8, 14, 1; -L_0x2c52e90 .part RS_0x7f99c4320ef8, 14, 1; -L_0x2c52f80 .part/pv L_0x2c53020, 14, 1, 32; -L_0x2c53160 .part RS_0x7f99c4320f58, 13, 1; -L_0x2c53200 .part RS_0x7f99c4320f28, 14, 1; -L_0x2c545c0 .part/pv L_0x2c543b0, 15, 1, 32; -L_0x2c54660 .part v0x2bc78e0_0, 0, 1; -L_0x2c53930 .part v0x2bc78e0_0, 1, 1; -L_0x2c53a60 .part RS_0x7f99c4320aa8, 15, 1; -L_0x2c53b00 .part RS_0x7f99c4320aa8, 15, 1; -L_0x2c53ba0 .part RS_0x7f99c4316848, 15, 1; -L_0x2c53c90 .part RS_0x7f99c4320aa8, 15, 1; -L_0x2c55450 .part/pv L_0x2c55240, 15, 1, 32; -L_0x2c54790 .part v0x2bc78e0_0, 0, 1; -L_0x2c548c0 .part v0x2bc78e0_0, 1, 1; -L_0x2c549f0 .part RS_0x7f99c4319e78, 15, 1; -L_0x2c082f0 .part RS_0x7f99c4319e78, 15, 1; -L_0x2c08390 .part RS_0x7f99c4316848, 15, 1; -L_0x2c08480 .part RS_0x7f99c4316848, 15, 1; -L_0x2c54cb0 .part/pv L_0x2c54b70, 15, 1, 32; -L_0x2c54d50 .part v0x2bc78e0_0, 2, 1; -L_0x2c54df0 .part RS_0x7f99c4320ec8, 15, 1; -L_0x2c54ee0 .part RS_0x7f99c4320ef8, 15, 1; -L_0x2c54fd0 .part/pv L_0x2c55070, 15, 1, 32; -L_0x2c555d0 .part RS_0x7f99c4320f58, 14, 1; -L_0x2c55670 .part RS_0x7f99c4320f28, 15, 1; -L_0x2c57150 .part/pv L_0x2c55d20, 16, 1, 32; -L_0x2c56690 .part v0x2bc78e0_0, 0, 1; -L_0x2c567c0 .part v0x2bc78e0_0, 1, 1; -L_0x2c568f0 .part RS_0x7f99c4320aa8, 16, 1; -L_0x2c56990 .part RS_0x7f99c4320aa8, 16, 1; -L_0x2c56a30 .part RS_0x7f99c4316848, 16, 1; -L_0x2c56b20 .part RS_0x7f99c4320aa8, 16, 1; -L_0x2c57fb0 .part/pv L_0x2c57da0, 16, 1, 32; -L_0x2c58050 .part v0x2bc78e0_0, 0, 1; -L_0x2c571f0 .part v0x2bc78e0_0, 1, 1; -L_0x2c57320 .part RS_0x7f99c4319e78, 16, 1; -L_0x2c573c0 .part RS_0x7f99c4319e78, 16, 1; -L_0x2c57460 .part RS_0x7f99c4316848, 16, 1; -L_0x2c57550 .part RS_0x7f99c4316848, 16, 1; -L_0x2c57a10 .part/pv L_0x2c578d0, 16, 1, 32; -L_0x2c57ab0 .part v0x2bc78e0_0, 2, 1; -L_0x2c57b50 .part RS_0x7f99c4320ec8, 16, 1; -L_0x2c43e90 .part RS_0x7f99c4320ef8, 16, 1; -L_0x2c43f80 .part/pv L_0x2c44580, 16, 1, 32; -L_0x2c446c0 .part RS_0x7f99c4320f58, 15, 1; -L_0x2c589a0 .part RS_0x7f99c4320f28, 16, 1; -L_0x2c5a110 .part/pv L_0x2c59f00, 17, 1, 32; -L_0x2c5a1b0 .part v0x2bc78e0_0, 0, 1; -L_0x2c58fe0 .part v0x2bc78e0_0, 1, 1; -L_0x2c59110 .part RS_0x7f99c4320aa8, 17, 1; -L_0x2c591b0 .part RS_0x7f99c4320aa8, 17, 1; -L_0x2c59250 .part RS_0x7f99c4316848, 17, 1; -L_0x2c59340 .part RS_0x7f99c4320aa8, 17, 1; -L_0x2c5af80 .part/pv L_0x2c5ada0, 17, 1, 32; -L_0x2c5a2e0 .part v0x2bc78e0_0, 0, 1; -L_0x2c5a410 .part v0x2bc78e0_0, 1, 1; -L_0x2c5a540 .part RS_0x7f99c4319e78, 17, 1; -L_0x2c5a5e0 .part RS_0x7f99c4319e78, 17, 1; -L_0x2c5a680 .part RS_0x7f99c4316848, 17, 1; -L_0x2c5a770 .part RS_0x7f99c4316848, 17, 1; -L_0x2c5ac10 .part/pv L_0x2c5aad0, 17, 1, 32; -L_0x2c5acb0 .part v0x2bc78e0_0, 2, 1; -L_0x2c5bb30 .part RS_0x7f99c4320ec8, 17, 1; -L_0x2c5bbd0 .part RS_0x7f99c4320ef8, 17, 1; -L_0x2c5b020 .part/pv L_0x2c5b0c0, 17, 1, 32; -L_0x2c5b200 .part RS_0x7f99c4320f58, 16, 1; -L_0x2c5b2a0 .part RS_0x7f99c4320f28, 17, 1; -L_0x2c5c880 .part/pv L_0x2c5b980, 18, 1, 32; -L_0x2c5bcc0 .part v0x2bc78e0_0, 0, 1; -L_0x2c5bdf0 .part v0x2bc78e0_0, 1, 1; -L_0x2c5bf20 .part RS_0x7f99c4320aa8, 18, 1; -L_0x2c5bfc0 .part RS_0x7f99c4320aa8, 18, 1; -L_0x2c5c060 .part RS_0x7f99c4316848, 18, 1; -L_0x2c5c150 .part RS_0x7f99c4320aa8, 18, 1; -L_0x2c5d6e0 .part/pv L_0x2c5d4d0, 18, 1, 32; -L_0x2c5d780 .part v0x2bc78e0_0, 0, 1; -L_0x2c5c920 .part v0x2bc78e0_0, 1, 1; -L_0x2c5ca50 .part RS_0x7f99c4319e78, 18, 1; -L_0x2c5caf0 .part RS_0x7f99c4319e78, 18, 1; -L_0x2c5cb90 .part RS_0x7f99c4316848, 18, 1; -L_0x2c5cc80 .part RS_0x7f99c4316848, 18, 1; -L_0x2c5d140 .part/pv L_0x2c5d000, 18, 1, 32; -L_0x2c5d1e0 .part v0x2bc78e0_0, 2, 1; -L_0x2c5d280 .part RS_0x7f99c4320ec8, 18, 1; -L_0x2c5d370 .part RS_0x7f99c4320ef8, 18, 1; -L_0x2c5e470 .part/pv L_0x2c5d8b0, 18, 1, 32; -L_0x2c5d9f0 .part RS_0x7f99c4320f58, 17, 1; -L_0x2c5da90 .part RS_0x7f99c4320f28, 18, 1; -L_0x2c5e350 .part/pv L_0x2c5e140, 19, 1, 32; -L_0x2c5f0f0 .part v0x2bc78e0_0, 0, 1; -L_0x2c5e510 .part v0x2bc78e0_0, 1, 1; -L_0x2c5e640 .part RS_0x7f99c4320aa8, 19, 1; -L_0x2c5e6e0 .part RS_0x7f99c4320aa8, 19, 1; -L_0x2c5e780 .part RS_0x7f99c4316848, 19, 1; -L_0x2c5e870 .part RS_0x7f99c4320aa8, 19, 1; -L_0x2c5fe80 .part/pv L_0x2c5ef70, 19, 1, 32; -L_0x2c5f220 .part v0x2bc78e0_0, 0, 1; -L_0x2c5f350 .part v0x2bc78e0_0, 1, 1; -L_0x2c5f480 .part RS_0x7f99c4319e78, 19, 1; -L_0x2c5f520 .part RS_0x7f99c4319e78, 19, 1; -L_0x2c5f5c0 .part RS_0x7f99c4316848, 19, 1; -L_0x2c5f6b0 .part RS_0x7f99c4316848, 19, 1; -L_0x2c5fb10 .part/pv L_0x2c5f9d0, 19, 1, 32; -L_0x2c5fbb0 .part v0x2bc78e0_0, 2, 1; -L_0x2c5fc50 .part RS_0x7f99c4320ec8, 19, 1; -L_0x2c5fd40 .part RS_0x7f99c4320ef8, 19, 1; -L_0x2c60b90 .part/pv L_0x2c60c30, 19, 1, 32; -L_0x2c60d70 .part RS_0x7f99c4320f58, 18, 1; -L_0x2c5ff20 .part RS_0x7f99c4320f28, 19, 1; -L_0x2c60810 .part/pv L_0x2c60600, 20, 1, 32; -L_0x2c608b0 .part v0x2bc78e0_0, 0, 1; -L_0x2c609e0 .part v0x2bc78e0_0, 1, 1; -L_0x2c61ab0 .part RS_0x7f99c4320aa8, 20, 1; -L_0x2c61b50 .part RS_0x7f99c4320aa8, 20, 1; -L_0x2c60e10 .part RS_0x7f99c4316848, 20, 1; -L_0x2c60f00 .part RS_0x7f99c4320aa8, 20, 1; -L_0x2c61820 .part/pv L_0x2c61610, 20, 1, 32; -L_0x2c618c0 .part v0x2bc78e0_0, 0, 1; -L_0x2c619f0 .part v0x2bc78e0_0, 1, 1; -L_0x2c62950 .part RS_0x7f99c4319e78, 20, 1; -L_0x2c61bf0 .part RS_0x7f99c4319e78, 20, 1; -L_0x2c61c90 .part RS_0x7f99c4316848, 20, 1; -L_0x2c61d80 .part RS_0x7f99c4316848, 20, 1; -L_0x2c62240 .part/pv L_0x2c62100, 20, 1, 32; -L_0x2c622e0 .part v0x2bc78e0_0, 2, 1; -L_0x2c62380 .part RS_0x7f99c4320ec8, 20, 1; -L_0x2c62470 .part RS_0x7f99c4320ef8, 20, 1; -L_0x2c62560 .part/pv L_0x2c62600, 20, 1, 32; -L_0x2c62740 .part RS_0x7f99c4320f58, 19, 1; -L_0x2c627e0 .part RS_0x7f99c4320f28, 20, 1; -L_0x2c63ee0 .part/pv L_0x2c63cd0, 21, 1, 32; -L_0x2c63f80 .part v0x2bc78e0_0, 0, 1; -L_0x2c629f0 .part v0x2bc78e0_0, 1, 1; -L_0x2c62b20 .part RS_0x7f99c4320aa8, 21, 1; -L_0x2c62bc0 .part RS_0x7f99c4320aa8, 21, 1; -L_0x2c62c60 .part RS_0x7f99c4316848, 21, 1; -L_0x2c62d50 .part RS_0x7f99c4320aa8, 21, 1; -L_0x2c63660 .part/pv L_0x2c63450, 21, 1, 32; -L_0x2c64e20 .part v0x2bc78e0_0, 0, 1; -L_0x2c64f50 .part v0x2bc78e0_0, 1, 1; -L_0x2c640b0 .part RS_0x7f99c4319e78, 21, 1; -L_0x2c64150 .part RS_0x7f99c4319e78, 21, 1; -L_0x2c641f0 .part RS_0x7f99c4316848, 21, 1; -L_0x2c642e0 .part RS_0x7f99c4316848, 21, 1; -L_0x2c64780 .part/pv L_0x2c64640, 21, 1, 32; -L_0x2c64820 .part v0x2bc78e0_0, 2, 1; -L_0x2c648c0 .part RS_0x7f99c4320ec8, 21, 1; -L_0x2c649b0 .part RS_0x7f99c4320ef8, 21, 1; -L_0x2c64aa0 .part/pv L_0x2c64b40, 21, 1, 32; -L_0x2c64c80 .part RS_0x7f99c4320f58, 20, 1; -L_0x2c64d20 .part RS_0x7f99c4320f28, 21, 1; -L_0x2c66650 .part/pv L_0x2c66440, 22, 1, 32; -L_0x2c65080 .part v0x2bc78e0_0, 0, 1; -L_0x2c651b0 .part v0x2bc78e0_0, 1, 1; -L_0x2c652e0 .part RS_0x7f99c4320aa8, 22, 1; -L_0x2c65380 .part RS_0x7f99c4320aa8, 22, 1; -L_0x2c65420 .part RS_0x7f99c4316848, 22, 1; -L_0x2c65510 .part RS_0x7f99c4320aa8, 22, 1; -L_0x2c67500 .part/pv L_0x2c65c20, 22, 1, 32; -L_0x2c675a0 .part v0x2bc78e0_0, 0, 1; -L_0x2c666f0 .part v0x2bc78e0_0, 1, 1; -L_0x2c66820 .part RS_0x7f99c4319e78, 22, 1; -L_0x2c668c0 .part RS_0x7f99c4319e78, 22, 1; -L_0x2c66960 .part RS_0x7f99c4316848, 22, 1; -L_0x2c66a50 .part RS_0x7f99c4316848, 22, 1; -L_0x2c66f10 .part/pv L_0x2c66dd0, 22, 1, 32; -L_0x2c66fb0 .part v0x2bc78e0_0, 2, 1; -L_0x2c67050 .part RS_0x7f99c4320ec8, 22, 1; -L_0x2c67140 .part RS_0x7f99c4320ef8, 22, 1; -L_0x2c67230 .part/pv L_0x2c672d0, 22, 1, 32; -L_0x2c67410 .part RS_0x7f99c4320f58, 21, 1; -L_0x2c68540 .part RS_0x7f99c4320f28, 22, 1; -L_0x2c67f00 .part/pv L_0x2c67cf0, 23, 1, 32; -L_0x2c67fa0 .part v0x2bc78e0_0, 0, 1; -L_0x2c680d0 .part v0x2bc78e0_0, 1, 1; -L_0x2c68200 .part RS_0x7f99c4320aa8, 23, 1; -L_0x2c682a0 .part RS_0x7f99c4320aa8, 23, 1; -L_0x2c68340 .part RS_0x7f99c4316848, 23, 1; -L_0x2c68430 .part RS_0x7f99c4320aa8, 23, 1; -L_0x2c69cf0 .part/pv L_0x2c69ae0, 23, 1, 32; -L_0x2c685e0 .part v0x2bc78e0_0, 0, 1; -L_0x2c68710 .part v0x2bc78e0_0, 1, 1; -L_0x2c68840 .part RS_0x7f99c4319e78, 23, 1; -L_0x2c688e0 .part RS_0x7f99c4319e78, 23, 1; -L_0x2c68980 .part RS_0x7f99c4316848, 23, 1; -L_0x2c68a70 .part RS_0x7f99c4316848, 23, 1; -L_0x2c68f10 .part/pv L_0x2c68dd0, 23, 1, 32; -L_0x2c68fb0 .part v0x2bc78e0_0, 2, 1; -L_0x2c69050 .part RS_0x7f99c4320ec8, 23, 1; -L_0x2c69140 .part RS_0x7f99c4320ef8, 23, 1; -L_0x2c69230 .part/pv L_0x2c692d0, 23, 1, 32; -L_0x2c6aca0 .part RS_0x7f99c4320f58, 22, 1; -L_0x2c69d90 .part RS_0x7f99c4320f28, 23, 1; -L_0x2c6a680 .part/pv L_0x2c6a470, 24, 1, 32; -L_0x2c6a720 .part v0x2bc78e0_0, 0, 1; -L_0x2c6a850 .part v0x2bc78e0_0, 1, 1; -L_0x2c6a980 .part RS_0x7f99c4320aa8, 24, 1; -L_0x2c6aa20 .part RS_0x7f99c4320aa8, 24, 1; -L_0x2c6aac0 .part RS_0x7f99c4316848, 24, 1; -L_0x2c6abb0 .part RS_0x7f99c4320aa8, 24, 1; -L_0x2c6c470 .part/pv L_0x2c6c260, 24, 1, 32; -L_0x2c6c510 .part v0x2bc78e0_0, 0, 1; -L_0x2c6ad40 .part v0x2bc78e0_0, 1, 1; -L_0x2c6ae70 .part RS_0x7f99c4319e78, 24, 1; -L_0x2c6af10 .part RS_0x7f99c4319e78, 24, 1; -L_0x2c6afb0 .part RS_0x7f99c4316848, 24, 1; -L_0x2c6b0a0 .part RS_0x7f99c4316848, 24, 1; -L_0x2c6b5a0 .part/pv L_0x2c6b460, 24, 1, 32; -L_0x2c6b640 .part v0x2bc78e0_0, 2, 1; -L_0x2c6b6e0 .part RS_0x7f99c4320ec8, 24, 1; -L_0x2c6b7d0 .part RS_0x7f99c4320ef8, 24, 1; -L_0x2c6b8c0 .part/pv L_0x2c6b960, 24, 1, 32; -L_0x2c6baa0 .part RS_0x7f99c4320f58, 23, 1; -L_0x2c6bb40 .part RS_0x7f99c4320f28, 24, 1; -L_0x2c6cde0 .part/pv L_0x2c6cbd0, 25, 1, 32; -L_0x2c6ce80 .part v0x2bc78e0_0, 0, 1; -L_0x2c6cfb0 .part v0x2bc78e0_0, 1, 1; -L_0x2c6d0e0 .part RS_0x7f99c4320aa8, 25, 1; -L_0x2c6d180 .part RS_0x7f99c4320aa8, 25, 1; -L_0x2c6d220 .part RS_0x7f99c4316848, 25, 1; -L_0x2c6d310 .part RS_0x7f99c4320aa8, 25, 1; -L_0x2be2160 .part/pv L_0x2be1f50, 25, 1, 32; -L_0x2be2200 .part v0x2bc78e0_0, 0, 1; -L_0x2be2330 .part v0x2bc78e0_0, 1, 1; -L_0x2be2460 .part RS_0x7f99c4319e78, 25, 1; -L_0x2be2500 .part RS_0x7f99c4319e78, 25, 1; -L_0x2be25a0 .part RS_0x7f99c4316848, 25, 1; -L_0x2be2690 .part RS_0x7f99c4316848, 25, 1; -L_0x2be0b30 .part/pv L_0x2be29f0, 25, 1, 32; -L_0x2be0bd0 .part v0x2bc78e0_0, 2, 1; -L_0x2be0c70 .part RS_0x7f99c4320ec8, 25, 1; -L_0x2be0d60 .part RS_0x7f99c4320ef8, 25, 1; -L_0x2be0e50 .part/pv L_0x2be0ef0, 25, 1, 32; -L_0x2be1030 .part RS_0x7f99c4320f58, 24, 1; -L_0x2be10d0 .part RS_0x7f99c4320f28, 25, 1; -L_0x2be19c0 .part/pv L_0x2be17b0, 26, 1, 32; -L_0x2c72670 .part v0x2bc78e0_0, 0, 1; -L_0x2c727a0 .part v0x2bc78e0_0, 1, 1; -L_0x2c715f0 .part RS_0x7f99c4320aa8, 26, 1; -L_0x2c71690 .part RS_0x7f99c4320aa8, 26, 1; -L_0x2c71730 .part RS_0x7f99c4316848, 26, 1; -L_0x2c71820 .part RS_0x7f99c4320aa8, 26, 1; -L_0x2c72140 .part/pv L_0x2c71f30, 26, 1, 32; -L_0x2c721e0 .part v0x2bc78e0_0, 0, 1; -L_0x2c72310 .part v0x2bc78e0_0, 1, 1; -L_0x2c72440 .part RS_0x7f99c4319e78, 26, 1; -L_0x2c724e0 .part RS_0x7f99c4319e78, 26, 1; -L_0x2c72580 .part RS_0x7f99c4316848, 26, 1; -L_0x2c739b0 .part RS_0x7f99c4316848, 26, 1; -L_0x2c73e60 .part/pv L_0x2c73d20, 26, 1, 32; -L_0x2c728d0 .part v0x2bc78e0_0, 2, 1; -L_0x2c72970 .part RS_0x7f99c4320ec8, 26, 1; -L_0x2c72a60 .part RS_0x7f99c4320ef8, 26, 1; -L_0x2c72b50 .part/pv L_0x2c72bf0, 26, 1, 32; -L_0x2c72d30 .part RS_0x7f99c4320f58, 25, 1; -L_0x2c72dd0 .part RS_0x7f99c4320f28, 26, 1; -L_0x2c736c0 .part/pv L_0x2c734b0, 27, 1, 32; -L_0x2c73760 .part v0x2bc78e0_0, 0, 1; -L_0x2c73890 .part v0x2bc78e0_0, 1, 1; -L_0x2c750c0 .part RS_0x7f99c4320aa8, 27, 1; -L_0x2c73f00 .part RS_0x7f99c4320aa8, 27, 1; -L_0x2c73fa0 .part RS_0x7f99c4316848, 27, 1; -L_0x2c74090 .part RS_0x7f99c4320aa8, 27, 1; -L_0x2c749a0 .part/pv L_0x2c74790, 27, 1, 32; -L_0x2c74a40 .part v0x2bc78e0_0, 0, 1; -L_0x2c74b70 .part v0x2bc78e0_0, 1, 1; -L_0x2c74ca0 .part RS_0x7f99c4319e78, 27, 1; -L_0x2c74d40 .part RS_0x7f99c4319e78, 27, 1; -L_0x2c74de0 .part RS_0x7f99c4316848, 27, 1; -L_0x2c74ed0 .part RS_0x7f99c4316848, 27, 1; -L_0x2c76620 .part/pv L_0x2c764e0, 27, 1, 32; -L_0x2c766c0 .part v0x2bc78e0_0, 2, 1; -L_0x2c75160 .part RS_0x7f99c4320ec8, 27, 1; -L_0x2c75250 .part RS_0x7f99c4320ef8, 27, 1; -L_0x2c75340 .part/pv L_0x2c753e0, 27, 1, 32; -L_0x2c754e0 .part RS_0x7f99c4320f58, 26, 1; -L_0x2c75580 .part RS_0x7f99c4320f28, 27, 1; -L_0x2c75e70 .part/pv L_0x2c75c60, 28, 1, 32; -L_0x2c75f10 .part v0x2bc78e0_0, 0, 1; -L_0x2c76040 .part v0x2bc78e0_0, 1, 1; -L_0x2c76170 .part RS_0x7f99c4320aa8, 28, 1; -L_0x2c76210 .part RS_0x7f99c4320aa8, 28, 1; -L_0x2c77950 .part RS_0x7f99c4316848, 28, 1; -L_0x2c77a40 .part RS_0x7f99c4320aa8, 28, 1; -L_0x2c76f50 .part/pv L_0x2c76d40, 28, 1, 32; -L_0x2c76ff0 .part v0x2bc78e0_0, 0, 1; -L_0x2c77120 .part v0x2bc78e0_0, 1, 1; -L_0x2c77250 .part RS_0x7f99c4319e78, 28, 1; -L_0x2c772f0 .part RS_0x7f99c4319e78, 28, 1; -L_0x2c77390 .part RS_0x7f99c4316848, 28, 1; -L_0x2c77480 .part RS_0x7f99c4316848, 28, 1; -L_0x2c78db0 .part/pv L_0x2c77840, 28, 1, 32; -L_0x2c77b30 .part v0x2bc78e0_0, 2, 1; -L_0x2c77bd0 .part RS_0x7f99c4320ec8, 28, 1; -L_0x2c77cc0 .part RS_0x7f99c4320ef8, 28, 1; -L_0x2c77db0 .part/pv L_0x2c77e50, 28, 1, 32; -L_0x2c77f90 .part RS_0x7f99c4320f58, 27, 1; -L_0x2c78030 .part RS_0x7f99c4320f28, 28, 1; -L_0x2c78950 .part/pv L_0x2c78740, 29, 1, 32; -L_0x2c789f0 .part v0x2bc78e0_0, 0, 1; -L_0x2c78b20 .part v0x2bc78e0_0, 1, 1; -L_0x2c78c50 .part RS_0x7f99c4320aa8, 29, 1; -L_0x2c7a0e0 .part RS_0x7f99c4320aa8, 29, 1; -L_0x2c7a180 .part RS_0x7f99c4316848, 29, 1; -L_0x2c78e50 .part RS_0x7f99c4320aa8, 29, 1; -L_0x2c79760 .part/pv L_0x2c79550, 29, 1, 32; -L_0x2c79800 .part v0x2bc78e0_0, 0, 1; -L_0x2c79930 .part v0x2bc78e0_0, 1, 1; -L_0x2c79a60 .part RS_0x7f99c4319e78, 29, 1; -L_0x2c79b00 .part RS_0x7f99c4319e78, 29, 1; -L_0x2c79ba0 .part RS_0x7f99c4316848, 29, 1; -L_0x2c79c90 .part RS_0x7f99c4316848, 29, 1; -L_0x2c7b5e0 .part/pv L_0x2c7a050, 29, 1, 32; -L_0x2c7b680 .part v0x2bc78e0_0, 2, 1; -L_0x2c7a220 .part RS_0x7f99c4320ec8, 29, 1; -L_0x2c7a310 .part RS_0x7f99c4320ef8, 29, 1; -L_0x2c7a400 .part/pv L_0x2c7a4a0, 29, 1, 32; -L_0x2c7a5a0 .part RS_0x7f99c4320f58, 28, 1; -L_0x2c7a640 .part RS_0x7f99c4320f28, 29, 1; -L_0x2c7af00 .part/pv L_0x2c7acf0, 30, 1, 32; -L_0x2c7afa0 .part v0x2bc78e0_0, 0, 1; -L_0x2c7b0d0 .part v0x2bc78e0_0, 1, 1; -L_0x2c7b200 .part RS_0x7f99c4320aa8, 30, 1; -L_0x2c7b2a0 .part RS_0x7f99c4320aa8, 30, 1; -L_0x2c7b340 .part RS_0x7f99c4316848, 30, 1; -L_0x2c7b430 .part RS_0x7f99c4320aa8, 30, 1; -L_0x2c7bf20 .part/pv L_0x2c7bd10, 30, 1, 32; -L_0x2c7bfc0 .part v0x2bc78e0_0, 0, 1; -L_0x2c7c0f0 .part v0x2bc78e0_0, 1, 1; -L_0x2c7c220 .part RS_0x7f99c4319e78, 30, 1; -L_0x2c7c2c0 .part RS_0x7f99c4319e78, 30, 1; -L_0x2c7c360 .part RS_0x7f99c4316848, 30, 1; -L_0x2c7c450 .part RS_0x7f99c4316848, 30, 1; -L_0x2c7c950 .part/pv L_0x2c7c810, 30, 1, 32; -L_0x2c7de40 .part v0x2bc78e0_0, 2, 1; -L_0x2c7dee0 .part RS_0x7f99c4320ec8, 30, 1; -L_0x2c7cab0 .part RS_0x7f99c4320ef8, 30, 1; -L_0x2c7cba0 .part/pv L_0x2c7cc40, 30, 1, 32; -L_0x2c7cd80 .part RS_0x7f99c4320f58, 29, 1; -L_0x2c7ce20 .part RS_0x7f99c4320f28, 30, 1; -L_0x2c7d710 .part/pv L_0x2c7d500, 31, 1, 32; -L_0x2c7d7b0 .part v0x2bc78e0_0, 0, 1; -L_0x2c7d8e0 .part v0x2bc78e0_0, 1, 1; -L_0x2c7da10 .part RS_0x7f99c4320aa8, 31, 1; -L_0x2c7dab0 .part RS_0x7f99c4320aa8, 31, 1; -L_0x2c7db50 .part RS_0x7f99c4316848, 31, 1; -L_0x2c7dc40 .part RS_0x7f99c4320aa8, 31, 1; -L_0x2c45f50 .part/pv L_0x2c45d40, 31, 1, 32; -L_0x2c7df80 .part v0x2bc78e0_0, 0, 1; -L_0x2c7e0b0 .part v0x2bc78e0_0, 1, 1; -L_0x2c7e1e0 .part RS_0x7f99c4319e78, 31, 1; -L_0x2c7e280 .part RS_0x7f99c4319e78, 31, 1; -L_0x2c7e320 .part RS_0x7f99c4316848, 31, 1; -L_0x2c7e410 .part RS_0x7f99c4316848, 31, 1; -L_0x2c49690 .part/pv L_0x2c49550, 31, 1, 32; -L_0x2c49730 .part v0x2bc78e0_0, 2, 1; -L_0x2c497d0 .part RS_0x7f99c4320ec8, 31, 1; -L_0x2c498c0 .part RS_0x7f99c4320ef8, 31, 1; -L_0x2c499b0 .part/pv L_0x2c49a50, 31, 1, 32; -L_0x2c7e5a0 .part RS_0x7f99c4320f58, 30, 1; -L_0x2c7e640 .part RS_0x7f99c4320f28, 31, 1; -L_0x2ce9150 .part/pv L_0x2ce8f70, 0, 1, 32; -L_0x2c82790 .part v0x2bc78e0_0, 0, 1; -L_0x2c828c0 .part v0x2bc78e0_0, 1, 1; -L_0x2c829f0 .part RS_0x7f99c4320aa8, 0, 1; -L_0x2c82a90 .part RS_0x7f99c4320aa8, 0, 1; -L_0x2c82b30 .part RS_0x7f99c4316848, 0, 1; -L_0x2c82c20 .part RS_0x7f99c4320aa8, 0, 1; -L_0x2c83420 .part/pv L_0x2c83240, 0, 1, 32; -L_0x2c834c0 .part v0x2bc78e0_0, 0, 1; -L_0x2c835f0 .part v0x2bc78e0_0, 1, 1; -L_0x2c83720 .part RS_0x7f99c4319e78, 0, 1; -L_0x2c837c0 .part RS_0x7f99c4319e78, 0, 1; -L_0x2c83860 .part RS_0x7f99c4316848, 0, 1; -L_0x2c83950 .part RS_0x7f99c4316848, 0, 1; -L_0x2cea940 .part/pv L_0x2cea800, 0, 1, 32; -L_0x2c58bd0 .part v0x2bc78e0_0, 2, 1; -L_0x2c58c70 .part RS_0x7f99c4320ec8, 0, 1; -L_0x2c58d60 .part RS_0x7f99c4320ef8, 0, 1; -L_0x2c58e50 .part/pv L_0x2c58ef0, 0, 1, 32; -L_0x2c43660 .part RS_0x7f99c4320f28, 0, 1; -L_0x2c43700 .part RS_0x7f99c4320f28, 0, 1; -L_0x2c438e0 .part RS_0x7f99c4320f58, 31, 1; -S_0x2851a90 .scope module, "trial" "AddSubSLT32" 3 279, 3 205, S_0x29738d0; - .timescale -9 -12; -P_0x2851b88 .param/l "size" 3 228, +C4<0100000>; -L_0x2cab160/d .functor OR 1, L_0x2cab1e0, C4<0>, C4<0>, C4<0>; -L_0x2cab160 .delay (20000,20000,20000) L_0x2cab160/d; -L_0x2cab310/d .functor XOR 1, RS_0x7f99c4320da8, L_0x2c964e0, C4<0>, C4<0>; -L_0x2cab310 .delay (40000,40000,40000) L_0x2cab310/d; -L_0x2c96580/d .functor AND 1, L_0x2c96690, L_0x2c96730, C4<1>, C4<1>; -L_0x2c96580 .delay (20000,20000,20000) L_0x2c96580/d; -L_0x2c96820/d .functor NOT 1, RS_0x7f99c4320e38, C4<0>, C4<0>, C4<0>; -L_0x2c96820 .delay (10000,10000,10000) L_0x2c96820/d; -L_0x2cac400/d .functor NOT 1, L_0x2cac4a0, C4<0>, C4<0>, C4<0>; -L_0x2cac400 .delay (10000,10000,10000) L_0x2cac400/d; -L_0x2cac540/d .functor AND 1, L_0x2c96820, L_0x2cac6c0, C4<1>, C4<1>; -L_0x2cac540 .delay (20000,20000,20000) L_0x2cac540/d; -L_0x2cac760/d .functor AND 1, RS_0x7f99c4320e38, L_0x2cac400, C4<1>, C4<1>; -L_0x2cac760 .delay (20000,20000,20000) L_0x2cac760/d; -L_0x2cac8a0/d .functor AND 1, L_0x2cac540, L_0x2c96580, C4<1>, C4<1>; -L_0x2cac8a0 .delay (20000,20000,20000) L_0x2cac8a0/d; -L_0x2cad830/d .functor AND 1, L_0x2cac760, L_0x2c96580, C4<1>, C4<1>; -L_0x2cad830 .delay (20000,20000,20000) L_0x2cad830/d; -L_0x2cad930/d .functor OR 1, L_0x2cac8a0, L_0x2cad830, C4<0>, C4<0>; -L_0x2cad930 .delay (20000,20000,20000) L_0x2cad930/d; -v0x2b600f0_0 .alias "A", 31 0, v0x2bc6580_0; -v0x2b60190_0 .alias "AddSubSLTSum", 31 0, v0x2bc76e0_0; -v0x2b60230_0 .alias "B", 31 0, v0x2bc66a0_0; -RS_0x7f99c4320ad8/0/0 .resolv tri, L_0x2c80790, L_0x2c83fa0, L_0x2c853a0, L_0x2c86880; -RS_0x7f99c4320ad8/0/4 .resolv tri, L_0x2c87d20, L_0x2c89110, L_0x2c8a510, L_0x2c8b970; -RS_0x7f99c4320ad8/0/8 .resolv tri, L_0x2c8cf80, L_0x2c8e490, L_0x2c8f9a0, L_0x2c90eb0; -RS_0x7f99c4320ad8/0/12 .resolv tri, L_0x2c922c0, L_0x2c93710, L_0x2c94b80, L_0x2c96000; -RS_0x7f99c4320ad8/0/16 .resolv tri, L_0x2c976c0, L_0x2c98b30, L_0x2c99fe0, L_0x2c9b450; -RS_0x7f99c4320ad8/0/20 .resolv tri, L_0x2c9c950, L_0x2c9de60, L_0x2c9f220, L_0x2ca06a0; -RS_0x7f99c4320ad8/0/24 .resolv tri, L_0x2ca1b90, L_0x2c063d0, L_0x2ca5540, L_0x2ca6e30; -RS_0x7f99c4320ad8/0/28 .resolv tri, L_0x2ca8320, L_0x2ca9820, L_0x2caad10, L_0x2cac200; -RS_0x7f99c4320ad8/1/0 .resolv tri, RS_0x7f99c4320ad8/0/0, RS_0x7f99c4320ad8/0/4, RS_0x7f99c4320ad8/0/8, RS_0x7f99c4320ad8/0/12; -RS_0x7f99c4320ad8/1/4 .resolv tri, RS_0x7f99c4320ad8/0/16, RS_0x7f99c4320ad8/0/20, RS_0x7f99c4320ad8/0/24, RS_0x7f99c4320ad8/0/28; -RS_0x7f99c4320ad8 .resolv tri, RS_0x7f99c4320ad8/1/0, RS_0x7f99c4320ad8/1/4, C4, C4; -v0x2b60300_0 .net8 "CarryoutWire", 31 0, RS_0x7f99c4320ad8; 32 drivers -v0x2b60380_0 .alias "Command", 2 0, v0x2bc67a0_0; -v0x2b60400_0 .net "Res0OF1", 0 0, L_0x2cac760; 1 drivers -v0x2b604a0_0 .net "Res1OF0", 0 0, L_0x2cac540; 1 drivers -v0x2b60540_0 .alias "SLTflag", 0 0, v0x2bc7a60_0; -v0x2b60630_0 .net "SLTflag0", 0 0, L_0x2cac8a0; 1 drivers -v0x2b606d0_0 .net "SLTflag1", 0 0, L_0x2cad830; 1 drivers -v0x2b60770_0 .net "SLTon", 0 0, L_0x2c96580; 1 drivers -v0x2b60810_0 .net *"_s292", 0 0, L_0x2cab1e0; 1 drivers -v0x2b608b0_0 .net/s *"_s293", 0 0, C4<0>; 1 drivers -v0x2b60950_0 .net *"_s296", 0 0, L_0x2c964e0; 1 drivers -v0x2b60a70_0 .net *"_s298", 0 0, L_0x2c96690; 1 drivers -v0x2b60b10_0 .net *"_s300", 0 0, L_0x2c96730; 1 drivers -v0x2b609d0_0 .net *"_s302", 0 0, L_0x2cac4a0; 1 drivers -v0x2b60c60_0 .net *"_s304", 0 0, L_0x2cac6c0; 1 drivers -v0x2b60d80_0 .alias "carryin", 31 0, v0x2bc71d0_0; -v0x2b60e00_0 .alias "carryout", 0 0, v0x2bc7be0_0; -v0x2b60ce0_0 .net "nAddSubSLTSum", 0 0, L_0x2cac400; 1 drivers -v0x2b60f30_0 .net "nOF", 0 0, L_0x2c96820; 1 drivers -v0x2b60e80_0 .alias "overflow", 0 0, v0x2bc7c60_0; -v0x2b61070_0 .alias "subtract", 31 0, v0x2bc7ce0_0; -L_0x2c806a0 .part/pv L_0x2c7f180, 1, 1, 32; -L_0x2c80790 .part/pv L_0x2c80560, 1, 1, 32; -L_0x2c80880 .part/pv L_0x2c7eeb0, 1, 1, 32; -L_0x2c80970 .part v0x2bc7660_0, 1, 1; -L_0x2c80a10 .part v0x2bc7860_0, 1, 1; -L_0x2c80b40 .part RS_0x7f99c4320ad8, 0, 1; -L_0x2c83eb0 .part/pv L_0x2c81630, 2, 1, 32; -L_0x2c83fa0 .part/pv L_0x2c83d70, 2, 1, 32; -L_0x2c840e0 .part/pv L_0x2c81360, 2, 1, 32; -L_0x2c841d0 .part v0x2bc7660_0, 2, 1; -L_0x2c842d0 .part v0x2bc7860_0, 2, 1; -L_0x2c84400 .part RS_0x7f99c4320ad8, 1, 1; -L_0x2c852b0 .part/pv L_0x2c84e20, 3, 1, 32; -L_0x2c853a0 .part/pv L_0x2c85170, 3, 1, 32; -L_0x2c85510 .part/pv L_0x2c84b50, 3, 1, 32; -L_0x2c85600 .part v0x2bc7660_0, 3, 1; -L_0x2c85730 .part v0x2bc7860_0, 3, 1; -L_0x2c85860 .part RS_0x7f99c4320ad8, 2, 1; -L_0x2c86790 .part/pv L_0x2c86300, 4, 1, 32; -L_0x2c86880 .part/pv L_0x2c86650, 4, 1, 32; -L_0x2c85900 .part/pv L_0x2c86030, 4, 1, 32; -L_0x2c86a70 .part v0x2bc7660_0, 4, 1; -L_0x2c86970 .part v0x2bc7860_0, 4, 1; -L_0x2c86c60 .part RS_0x7f99c4320ad8, 3, 1; -L_0x2c87c30 .part/pv L_0x2c877a0, 5, 1, 32; -L_0x2c87d20 .part/pv L_0x2c87af0, 5, 1, 32; -L_0x2c86e10 .part/pv L_0x2c874d0, 5, 1, 32; -L_0x2c87f40 .part v0x2bc7660_0, 5, 1; -L_0x2c87e10 .part v0x2bc7860_0, 5, 1; -L_0x2c88160 .part RS_0x7f99c4320ad8, 4, 1; -L_0x2c89020 .part/pv L_0x2c88b90, 6, 1, 32; -L_0x2c89110 .part/pv L_0x2c88ee0, 6, 1, 32; -L_0x2c88200 .part/pv L_0x2c888c0, 6, 1, 32; -L_0x2c89310 .part v0x2bc7660_0, 6, 1; -L_0x2c89200 .part v0x2bc7860_0, 6, 1; -L_0x2c89560 .part RS_0x7f99c4320ad8, 5, 1; -L_0x2c8a420 .part/pv L_0x2c89f90, 7, 1, 32; -L_0x2c8a510 .part/pv L_0x2c8a2e0, 7, 1, 32; -L_0x2c89600 .part/pv L_0x2c89cc0, 7, 1, 32; -L_0x2c8a740 .part v0x2bc7660_0, 7, 1; -L_0x2c8a600 .part v0x2bc7860_0, 7, 1; -L_0x2c8a930 .part RS_0x7f99c4320ad8, 6, 1; -L_0x2c8b880 .part/pv L_0x2c8b3b0, 8, 1, 32; -L_0x2c8b970 .part/pv L_0x2c8b720, 8, 1, 32; -L_0x2c8a9d0 .part/pv L_0x2c8b0e0, 8, 1, 32; -L_0x2c8bbd0 .part v0x2bc7660_0, 8, 1; -L_0x2c8ba60 .part v0x2bc7860_0, 8, 1; -L_0x2c8bdf0 .part RS_0x7f99c4320ad8, 7, 1; -L_0x2c8ce90 .part/pv L_0x2c8c9e0, 9, 1, 32; -L_0x2c8cf80 .part/pv L_0x2c8cd30, 9, 1, 32; -L_0x2c8c0a0 .part/pv L_0x2c8c710, 9, 1, 32; -L_0x2c8c190 .part v0x2bc7660_0, 9, 1; -L_0x2c8d220 .part v0x2bc7860_0, 9, 1; -L_0x2c8d350 .part RS_0x7f99c4320ad8, 8, 1; -L_0x2c8e3a0 .part/pv L_0x2c8def0, 10, 1, 32; -L_0x2c8e490 .part/pv L_0x2c8e240, 10, 1, 32; -L_0x2c8d3f0 .part/pv L_0x2c8dc20, 10, 1, 32; -L_0x2c8d4e0 .part v0x2bc7660_0, 10, 1; -L_0x2c8e760 .part v0x2bc7860_0, 10, 1; -L_0x2c8e890 .part RS_0x7f99c4320ad8, 9, 1; -L_0x2c8f8b0 .part/pv L_0x2c8f400, 11, 1, 32; -L_0x2c8f9a0 .part/pv L_0x2c8f750, 11, 1, 32; -L_0x2c8e930 .part/pv L_0x2c8f130, 11, 1, 32; -L_0x2c8ea20 .part v0x2bc7660_0, 11, 1; -L_0x2c8fca0 .part v0x2bc7860_0, 11, 1; -L_0x2c8fdd0 .part RS_0x7f99c4320ad8, 10, 1; -L_0x2c90dc0 .part/pv L_0x2c90910, 12, 1, 32; -L_0x2c90eb0 .part/pv L_0x2c90c60, 12, 1, 32; -L_0x2c8fe70 .part/pv L_0x2c90640, 12, 1, 32; -L_0x2c8ff60 .part v0x2bc7660_0, 12, 1; -L_0x2c911e0 .part v0x2bc7860_0, 12, 1; -L_0x2c91280 .part RS_0x7f99c4320ad8, 11, 1; -L_0x2c921d0 .part/pv L_0x2c91e10, 13, 1, 32; -L_0x2c922c0 .part/pv L_0x2c92090, 13, 1, 32; -L_0x2c91320 .part/pv L_0x2c91b40, 13, 1, 32; -L_0x2c91410 .part v0x2bc7660_0, 13, 1; -L_0x2c914b0 .part v0x2bc7860_0, 13, 1; -L_0x2c926b0 .part RS_0x7f99c4320ad8, 12, 1; -L_0x2c93620 .part/pv L_0x2c93190, 14, 1, 32; -L_0x2c93710 .part/pv L_0x2c934e0, 14, 1, 32; -L_0x2c92750 .part/pv L_0x2c92ec0, 14, 1, 32; -L_0x2c92840 .part v0x2bc7660_0, 14, 1; -L_0x2c928e0 .part v0x2bc7860_0, 14, 1; -L_0x2c93b30 .part RS_0x7f99c4320ad8, 13, 1; -L_0x2c94a90 .part/pv L_0x2c94600, 15, 1, 32; -L_0x2c94b80 .part/pv L_0x2c94950, 15, 1, 32; -L_0x2c93bd0 .part/pv L_0x2c94330, 15, 1, 32; -L_0x2c93cc0 .part v0x2bc7660_0, 15, 1; -L_0x2c93d60 .part v0x2bc7860_0, 15, 1; -L_0x2c94fd0 .part RS_0x7f99c4320ad8, 14, 1; -L_0x2c95f10 .part/pv L_0x2c95a80, 16, 1, 32; -L_0x2c96000 .part/pv L_0x2c95dd0, 16, 1, 32; -L_0x2c95070 .part/pv L_0x2c957b0, 16, 1, 32; -L_0x2c95160 .part v0x2bc7660_0, 16, 1; -L_0x2c95200 .part v0x2bc7860_0, 16, 1; -L_0x2c963f0 .part RS_0x7f99c4320ad8, 15, 1; -L_0x2c975d0 .part/pv L_0x2c97140, 17, 1, 32; -L_0x2c976c0 .part/pv L_0x2c97490, 17, 1, 32; -L_0x2c968a0 .part/pv L_0x2c96e70, 17, 1, 32; -L_0x2c96990 .part v0x2bc7660_0, 17, 1; -L_0x2c96a30 .part v0x2bc7860_0, 17, 1; -L_0x2c97ae0 .part RS_0x7f99c4320ad8, 16, 1; -L_0x2c98a40 .part/pv L_0x2c985b0, 18, 1, 32; -L_0x2c98b30 .part/pv L_0x2c98900, 18, 1, 32; -L_0x2c97b80 .part/pv L_0x2c982e0, 18, 1, 32; -L_0x2c97c70 .part v0x2bc7660_0, 18, 1; -L_0x2c97d10 .part v0x2bc7860_0, 18, 1; -L_0x2c98f80 .part RS_0x7f99c4320ad8, 17, 1; -L_0x2c99ef0 .part/pv L_0x2c99a60, 19, 1, 32; -L_0x2c99fe0 .part/pv L_0x2c99db0, 19, 1, 32; -L_0x2c99020 .part/pv L_0x2c99790, 19, 1, 32; -L_0x2c99110 .part v0x2bc7660_0, 19, 1; -L_0x2c991b0 .part v0x2bc7860_0, 19, 1; -L_0x2c992e0 .part RS_0x7f99c4320ad8, 18, 1; -L_0x2c9b360 .part/pv L_0x2c9ae90, 20, 1, 32; -L_0x2c9b450 .part/pv L_0x2c9b200, 20, 1, 32; -L_0x2c9a0d0 .part/pv L_0x2c9abc0, 20, 1, 32; -L_0x2c9a1c0 .part v0x2bc7660_0, 20, 1; -L_0x2c9a260 .part v0x2bc7860_0, 20, 1; -L_0x2c9a390 .part RS_0x7f99c4320ad8, 19, 1; -L_0x2c9c860 .part/pv L_0x2c9c3b0, 21, 1, 32; -L_0x2c9c950 .part/pv L_0x2c9c700, 21, 1, 32; -L_0x2c9b540 .part/pv L_0x2c9c0e0, 21, 1, 32; -L_0x2c9b630 .part v0x2bc7660_0, 21, 1; -L_0x2c9b6d0 .part v0x2bc7860_0, 21, 1; -L_0x2c9b800 .part RS_0x7f99c4320ad8, 20, 1; -L_0x2c9dd70 .part/pv L_0x2c9d8c0, 22, 1, 32; -L_0x2c9de60 .part/pv L_0x2c9dc10, 22, 1, 32; -L_0x2c9ca40 .part/pv L_0x2c9d5f0, 22, 1, 32; -L_0x2c9cb30 .part v0x2bc7660_0, 22, 1; -L_0x2c9cbd0 .part v0x2bc7860_0, 22, 1; -L_0x2c9cd00 .part RS_0x7f99c4320ad8, 21, 1; -L_0x2c9f130 .part/pv L_0x2c9eca0, 23, 1, 32; -L_0x2c9f220 .part/pv L_0x2c9eff0, 23, 1, 32; -L_0x2c9df50 .part/pv L_0x2c9e9d0, 23, 1, 32; -L_0x2c9e040 .part v0x2bc7660_0, 23, 1; -L_0x2c9e0e0 .part v0x2bc7860_0, 23, 1; -L_0x2c9e210 .part RS_0x7f99c4320ad8, 22, 1; -L_0x2ca05b0 .part/pv L_0x2ca0080, 24, 1, 32; -L_0x2ca06a0 .part/pv L_0x2ca0450, 24, 1, 32; -L_0x2c9f310 .part/pv L_0x2c9fdb0, 24, 1, 32; -L_0x2c9f400 .part v0x2bc7660_0, 24, 1; -L_0x2c9f4a0 .part v0x2bc7860_0, 24, 1; -L_0x2c9f5d0 .part RS_0x7f99c4320ad8, 23, 1; -L_0x2ca1aa0 .part/pv L_0x2ca1570, 25, 1, 32; -L_0x2ca1b90 .part/pv L_0x2ca1940, 25, 1, 32; -L_0x2ca0790 .part/pv L_0x2ca12a0, 25, 1, 32; -L_0x2ca0880 .part v0x2bc7660_0, 25, 1; -L_0x2ca0920 .part v0x2bc7860_0, 25, 1; -L_0x2ca0a50 .part RS_0x7f99c4320ad8, 24, 1; -L_0x2c062e0 .part/pv L_0x2c05de0, 26, 1, 32; -L_0x2c063d0 .part/pv L_0x2c06180, 26, 1, 32; -L_0x2c05490 .part/pv L_0x2c05b10, 26, 1, 32; -L_0x2c05580 .part v0x2bc7660_0, 26, 1; -L_0x2c05620 .part v0x2bc7860_0, 26, 1; -L_0x2c05750 .part RS_0x7f99c4320ad8, 25, 1; -L_0x2ca5450 .part/pv L_0x2ca4f20, 27, 1, 32; -L_0x2ca5540 .part/pv L_0x2ca52f0, 27, 1, 32; -L_0x2ca4190 .part/pv L_0x2ca4c50, 27, 1, 32; -L_0x2bedf50 .part v0x2bc7660_0, 27, 1; -L_0x2bedff0 .part v0x2bc7860_0, 27, 1; -L_0x2bee120 .part RS_0x7f99c4320ad8, 26, 1; -L_0x2ca6d40 .part/pv L_0x2ca68b0, 28, 1, 32; -L_0x2ca6e30 .part/pv L_0x2ca6c00, 28, 1, 32; -L_0x2ca6340 .part/pv L_0x2ca58a0, 28, 1, 32; -L_0x2ca6430 .part v0x2bc7660_0, 28, 1; -L_0x2ca64d0 .part v0x2bc7860_0, 28, 1; -L_0x2ca6600 .part RS_0x7f99c4320ad8, 27, 1; -L_0x2ca8230 .part/pv L_0x2ca7d20, 29, 1, 32; -L_0x2ca8320 .part/pv L_0x2ca80d0, 29, 1, 32; -L_0x2ca6f20 .part/pv L_0x2ca7a20, 29, 1, 32; -L_0x2ca7010 .part v0x2bc7660_0, 29, 1; -L_0x2ca70b0 .part v0x2bc7860_0, 29, 1; -L_0x2ca71e0 .part RS_0x7f99c4320ad8, 28, 1; -L_0x2ca9730 .part/pv L_0x2ca9220, 30, 1, 32; -L_0x2ca9820 .part/pv L_0x2ca95d0, 30, 1, 32; -L_0x2ca8410 .part/pv L_0x2ca8f20, 30, 1, 32; -L_0x2ca8500 .part v0x2bc7660_0, 30, 1; -L_0x2ca85a0 .part v0x2bc7860_0, 30, 1; -L_0x2ca86d0 .part RS_0x7f99c4320ad8, 29, 1; -L_0x2caac20 .part/pv L_0x2caa710, 31, 1, 32; -L_0x2caad10 .part/pv L_0x2caaac0, 31, 1, 32; -L_0x2ca9910 .part/pv L_0x2caa410, 31, 1, 32; -L_0x2ca9a00 .part v0x2bc7660_0, 31, 1; -L_0x2ca9aa0 .part v0x2bc7860_0, 31, 1; -L_0x2ca9bd0 .part RS_0x7f99c4320ad8, 30, 1; -L_0x2cac110 .part/pv L_0x2cabc00, 0, 1, 32; -L_0x2cac200 .part/pv L_0x2cabfb0, 0, 1, 32; -L_0x2caae00 .part/pv L_0x2cab930, 0, 1, 32; -L_0x2caaef0 .part v0x2bc7660_0, 0, 1; -L_0x2caaf90 .part v0x2bc7860_0, 0, 1; -L_0x2cab0c0 .part RS_0x7f99c4320e68, 0, 1; -L_0x2cab1e0 .part RS_0x7f99c4320ad8, 31, 1; -L_0x2c964e0 .part RS_0x7f99c4320ad8, 30, 1; -L_0x2c96690 .part v0x2bc78e0_0, 1, 1; -L_0x2c96730 .part RS_0x7f99c4320e68, 0, 1; -L_0x2cac4a0 .part RS_0x7f99c4320aa8, 31, 1; -L_0x2cac6c0 .part RS_0x7f99c4320aa8, 31, 1; -S_0x2b5f0e0 .scope module, "attempt2" "MiddleAddSubSLT" 3 225, 3 89, S_0x2851a90; - .timescale -9 -12; -L_0x2ca9c70/d .functor NOT 1, L_0x2caaf90, C4<0>, C4<0>, C4<0>; -L_0x2ca9c70 .delay (10000,10000,10000) L_0x2ca9c70/d; -L_0x2cab7f0/d .functor NOT 1, L_0x2cab890, C4<0>, C4<0>, C4<0>; -L_0x2cab7f0 .delay (10000,10000,10000) L_0x2cab7f0/d; -L_0x2cab930/d .functor AND 1, L_0x2caba70, L_0x2cab7f0, C4<1>, C4<1>; -L_0x2cab930 .delay (20000,20000,20000) L_0x2cab930/d; -L_0x2cabb10/d .functor XOR 1, L_0x2caaef0, L_0x2cab5c0, C4<0>, C4<0>; -L_0x2cabb10 .delay (40000,40000,40000) L_0x2cabb10/d; -L_0x2cabc00/d .functor XOR 1, L_0x2cabb10, L_0x2cab0c0, C4<0>, C4<0>; -L_0x2cabc00 .delay (40000,40000,40000) L_0x2cabc00/d; -L_0x2cabd20/d .functor AND 1, L_0x2caaef0, L_0x2cab5c0, C4<1>, C4<1>; -L_0x2cabd20 .delay (20000,20000,20000) L_0x2cabd20/d; -L_0x2cabec0/d .functor AND 1, L_0x2cabb10, L_0x2cab0c0, C4<1>, C4<1>; -L_0x2cabec0 .delay (20000,20000,20000) L_0x2cabec0/d; -L_0x2cabfb0/d .functor OR 1, L_0x2cabd20, L_0x2cabec0, C4<0>, C4<0>; -L_0x2cabfb0 .delay (20000,20000,20000) L_0x2cabfb0/d; -v0x2b5f750_0 .net "A", 0 0, L_0x2caaef0; 1 drivers -v0x2b5f810_0 .net "AandB", 0 0, L_0x2cabd20; 1 drivers -v0x2b5f8b0_0 .net "AddSubSLTSum", 0 0, L_0x2cabc00; 1 drivers -v0x2b5f950_0 .net "AxorB", 0 0, L_0x2cabb10; 1 drivers -v0x2b5f9d0_0 .net "B", 0 0, L_0x2caaf90; 1 drivers -v0x2b5fa80_0 .net "BornB", 0 0, L_0x2cab5c0; 1 drivers -v0x2b5fb40_0 .net "CINandAxorB", 0 0, L_0x2cabec0; 1 drivers -v0x2b5fbc0_0 .alias "Command", 2 0, v0x2bc67a0_0; -v0x2b5fc40_0 .net *"_s3", 0 0, L_0x2cab890; 1 drivers -v0x2b5fcc0_0 .net *"_s5", 0 0, L_0x2caba70; 1 drivers -v0x2b5fd60_0 .net "carryin", 0 0, L_0x2cab0c0; 1 drivers -v0x2b5fe00_0 .net "carryout", 0 0, L_0x2cabfb0; 1 drivers -v0x2b5fea0_0 .net "nB", 0 0, L_0x2ca9c70; 1 drivers -v0x2b5ff50_0 .net "nCmd2", 0 0, L_0x2cab7f0; 1 drivers -v0x2b60050_0 .net "subtract", 0 0, L_0x2cab930; 1 drivers -L_0x2cab750 .part v0x2bc78e0_0, 0, 1; -L_0x2cab890 .part v0x2bc78e0_0, 2, 1; -L_0x2caba70 .part v0x2bc78e0_0, 0, 1; -S_0x2b5f1d0 .scope module, "mux0" "TwoInMux" 3 105, 3 8, S_0x2b5f0e0; - .timescale -9 -12; -L_0x2ca9dd0/d .functor NOT 1, L_0x2cab750, C4<0>, C4<0>, C4<0>; -L_0x2ca9dd0 .delay (10000,10000,10000) L_0x2ca9dd0/d; -L_0x2cab3e0/d .functor AND 1, L_0x2caaf90, L_0x2ca9dd0, C4<1>, C4<1>; -L_0x2cab3e0 .delay (20000,20000,20000) L_0x2cab3e0/d; -L_0x2cab4d0/d .functor AND 1, L_0x2ca9c70, L_0x2cab750, C4<1>, C4<1>; -L_0x2cab4d0 .delay (20000,20000,20000) L_0x2cab4d0/d; -L_0x2cab5c0/d .functor OR 1, L_0x2cab3e0, L_0x2cab4d0, C4<0>, C4<0>; -L_0x2cab5c0 .delay (20000,20000,20000) L_0x2cab5c0/d; -v0x2b5f2c0_0 .net "S", 0 0, L_0x2cab750; 1 drivers -v0x2b5f380_0 .alias "in0", 0 0, v0x2b5f9d0_0; -v0x2b5f420_0 .alias "in1", 0 0, v0x2b5fea0_0; -v0x2b5f4c0_0 .net "nS", 0 0, L_0x2ca9dd0; 1 drivers -v0x2b5f570_0 .net "out0", 0 0, L_0x2cab3e0; 1 drivers -v0x2b5f610_0 .net "out1", 0 0, L_0x2cab4d0; 1 drivers -v0x2b5f6b0_0 .alias "outfinal", 0 0, v0x2b5fa80_0; -S_0x2b5df40 .scope generate, "addbits[1]" "addbits[1]" 3 230, 3 230, S_0x2851a90; - .timescale -9 -12; -P_0x2b5d958 .param/l "i" 3 230, +C4<01>; -S_0x2b5e0b0 .scope module, "attempt" "MiddleAddSubSLT" 3 232, 3 89, S_0x2b5df40; - .timescale -9 -12; -L_0x2c7e730/d .functor NOT 1, L_0x2c80a10, C4<0>, C4<0>, C4<0>; -L_0x2c7e730 .delay (10000,10000,10000) L_0x2c7e730/d; -L_0x2c7ed70/d .functor NOT 1, L_0x2c7ee10, C4<0>, C4<0>, C4<0>; -L_0x2c7ed70 .delay (10000,10000,10000) L_0x2c7ed70/d; -L_0x2c7eeb0/d .functor AND 1, L_0x2c7eff0, L_0x2c7ed70, C4<1>, C4<1>; -L_0x2c7eeb0 .delay (20000,20000,20000) L_0x2c7eeb0/d; -L_0x2c7f090/d .functor XOR 1, L_0x2c80970, L_0x2c7eb40, C4<0>, C4<0>; -L_0x2c7f090 .delay (40000,40000,40000) L_0x2c7f090/d; -L_0x2c7f180/d .functor XOR 1, L_0x2c7f090, L_0x2c80b40, C4<0>, C4<0>; -L_0x2c7f180 .delay (40000,40000,40000) L_0x2c7f180/d; -L_0x2c7f270/d .functor AND 1, L_0x2c80970, L_0x2c7eb40, C4<1>, C4<1>; -L_0x2c7f270 .delay (20000,20000,20000) L_0x2c7f270/d; -L_0x2c80470/d .functor AND 1, L_0x2c7f090, L_0x2c80b40, C4<1>, C4<1>; -L_0x2c80470 .delay (20000,20000,20000) L_0x2c80470/d; -L_0x2c80560/d .functor OR 1, L_0x2c7f270, L_0x2c80470, C4<0>, C4<0>; -L_0x2c80560 .delay (20000,20000,20000) L_0x2c80560/d; -v0x2b5e740_0 .net "A", 0 0, L_0x2c80970; 1 drivers -v0x2b5e800_0 .net "AandB", 0 0, L_0x2c7f270; 1 drivers -v0x2b5e8a0_0 .net "AddSubSLTSum", 0 0, L_0x2c7f180; 1 drivers -v0x2b5e940_0 .net "AxorB", 0 0, L_0x2c7f090; 1 drivers -v0x2b5e9c0_0 .net "B", 0 0, L_0x2c80a10; 1 drivers -v0x2b5ea70_0 .net "BornB", 0 0, L_0x2c7eb40; 1 drivers -v0x2b5eb30_0 .net "CINandAxorB", 0 0, L_0x2c80470; 1 drivers -v0x2b5ebb0_0 .alias "Command", 2 0, v0x2bc67a0_0; -v0x2b5ec30_0 .net *"_s3", 0 0, L_0x2c7ee10; 1 drivers -v0x2b5ecb0_0 .net *"_s5", 0 0, L_0x2c7eff0; 1 drivers -v0x2b5ed50_0 .net "carryin", 0 0, L_0x2c80b40; 1 drivers -v0x2b5edf0_0 .net "carryout", 0 0, L_0x2c80560; 1 drivers -v0x2b5ee90_0 .net "nB", 0 0, L_0x2c7e730; 1 drivers -v0x2b5ef40_0 .net "nCmd2", 0 0, L_0x2c7ed70; 1 drivers -v0x2b5f040_0 .net "subtract", 0 0, L_0x2c7eeb0; 1 drivers -L_0x2c7ecd0 .part v0x2bc78e0_0, 0, 1; -L_0x2c7ee10 .part v0x2bc78e0_0, 2, 1; -L_0x2c7eff0 .part v0x2bc78e0_0, 0, 1; -S_0x2b5e1a0 .scope module, "mux0" "TwoInMux" 3 105, 3 8, S_0x2b5e0b0; - .timescale -9 -12; -L_0x2c7e8c0/d .functor NOT 1, L_0x2c7ecd0, C4<0>, C4<0>, C4<0>; -L_0x2c7e8c0 .delay (10000,10000,10000) L_0x2c7e8c0/d; -L_0x2c7e960/d .functor AND 1, L_0x2c80a10, L_0x2c7e8c0, C4<1>, C4<1>; -L_0x2c7e960 .delay (20000,20000,20000) L_0x2c7e960/d; -L_0x2c7ea50/d .functor AND 1, L_0x2c7e730, L_0x2c7ecd0, C4<1>, C4<1>; -L_0x2c7ea50 .delay (20000,20000,20000) L_0x2c7ea50/d; -L_0x2c7eb40/d .functor OR 1, L_0x2c7e960, L_0x2c7ea50, C4<0>, C4<0>; -L_0x2c7eb40 .delay (20000,20000,20000) L_0x2c7eb40/d; -v0x2b5e290_0 .net "S", 0 0, L_0x2c7ecd0; 1 drivers -v0x2b5e330_0 .alias "in0", 0 0, v0x2b5e9c0_0; -v0x2b5e3d0_0 .alias "in1", 0 0, v0x2b5ee90_0; -v0x2b5e470_0 .net "nS", 0 0, L_0x2c7e8c0; 1 drivers -v0x2b5e520_0 .net "out0", 0 0, L_0x2c7e960; 1 drivers -v0x2b5e5c0_0 .net "out1", 0 0, L_0x2c7ea50; 1 drivers -v0x2b5e6a0_0 .alias "outfinal", 0 0, v0x2b5ea70_0; -S_0x2b5cda0 .scope generate, "addbits[2]" "addbits[2]" 3 230, 3 230, S_0x2851a90; - .timescale -9 -12; -P_0x2b5c7b8 .param/l "i" 3 230, +C4<010>; -S_0x2b5cf10 .scope module, "attempt" "MiddleAddSubSLT" 3 232, 3 89, S_0x2b5cda0; - .timescale -9 -12; -L_0x2c80be0/d .functor NOT 1, L_0x2c842d0, C4<0>, C4<0>, C4<0>; -L_0x2c80be0 .delay (10000,10000,10000) L_0x2c80be0/d; -L_0x2c81220/d .functor NOT 1, L_0x2c812c0, C4<0>, C4<0>, C4<0>; -L_0x2c81220 .delay (10000,10000,10000) L_0x2c81220/d; -L_0x2c81360/d .functor AND 1, L_0x2c814a0, L_0x2c81220, C4<1>, C4<1>; -L_0x2c81360 .delay (20000,20000,20000) L_0x2c81360/d; -L_0x2c81540/d .functor XOR 1, L_0x2c841d0, L_0x2c80ff0, C4<0>, C4<0>; -L_0x2c81540 .delay (40000,40000,40000) L_0x2c81540/d; -L_0x2c81630/d .functor XOR 1, L_0x2c81540, L_0x2c84400, C4<0>, C4<0>; -L_0x2c81630 .delay (40000,40000,40000) L_0x2c81630/d; -L_0x2c81720/d .functor AND 1, L_0x2c841d0, L_0x2c80ff0, C4<1>, C4<1>; -L_0x2c81720 .delay (20000,20000,20000) L_0x2c81720/d; -L_0x2c83c80/d .functor AND 1, L_0x2c81540, L_0x2c84400, C4<1>, C4<1>; -L_0x2c83c80 .delay (20000,20000,20000) L_0x2c83c80/d; -L_0x2c83d70/d .functor OR 1, L_0x2c81720, L_0x2c83c80, C4<0>, C4<0>; -L_0x2c83d70 .delay (20000,20000,20000) L_0x2c83d70/d; -v0x2b5d5a0_0 .net "A", 0 0, L_0x2c841d0; 1 drivers -v0x2b5d660_0 .net "AandB", 0 0, L_0x2c81720; 1 drivers -v0x2b5d700_0 .net "AddSubSLTSum", 0 0, L_0x2c81630; 1 drivers -v0x2b5d7a0_0 .net "AxorB", 0 0, L_0x2c81540; 1 drivers -v0x2b5d820_0 .net "B", 0 0, L_0x2c842d0; 1 drivers -v0x2b5d8d0_0 .net "BornB", 0 0, L_0x2c80ff0; 1 drivers -v0x2b5d990_0 .net "CINandAxorB", 0 0, L_0x2c83c80; 1 drivers -v0x2b5da10_0 .alias "Command", 2 0, v0x2bc67a0_0; -v0x2b5da90_0 .net *"_s3", 0 0, L_0x2c812c0; 1 drivers -v0x2b5db10_0 .net *"_s5", 0 0, L_0x2c814a0; 1 drivers -v0x2b5dbb0_0 .net "carryin", 0 0, L_0x2c84400; 1 drivers -v0x2b5dc50_0 .net "carryout", 0 0, L_0x2c83d70; 1 drivers -v0x2b5dcf0_0 .net "nB", 0 0, L_0x2c80be0; 1 drivers -v0x2b5dda0_0 .net "nCmd2", 0 0, L_0x2c81220; 1 drivers -v0x2b5dea0_0 .net "subtract", 0 0, L_0x2c81360; 1 drivers -L_0x2c81180 .part v0x2bc78e0_0, 0, 1; -L_0x2c812c0 .part v0x2bc78e0_0, 2, 1; -L_0x2c814a0 .part v0x2bc78e0_0, 0, 1; -S_0x2b5d000 .scope module, "mux0" "TwoInMux" 3 105, 3 8, S_0x2b5cf10; - .timescale -9 -12; -L_0x2c80d70/d .functor NOT 1, L_0x2c81180, C4<0>, C4<0>, C4<0>; -L_0x2c80d70 .delay (10000,10000,10000) L_0x2c80d70/d; -L_0x2c80e10/d .functor AND 1, L_0x2c842d0, L_0x2c80d70, C4<1>, C4<1>; -L_0x2c80e10 .delay (20000,20000,20000) L_0x2c80e10/d; -L_0x2c80f00/d .functor AND 1, L_0x2c80be0, L_0x2c81180, C4<1>, C4<1>; -L_0x2c80f00 .delay (20000,20000,20000) L_0x2c80f00/d; -L_0x2c80ff0/d .functor OR 1, L_0x2c80e10, L_0x2c80f00, C4<0>, C4<0>; -L_0x2c80ff0 .delay (20000,20000,20000) L_0x2c80ff0/d; -v0x2b5d0f0_0 .net "S", 0 0, L_0x2c81180; 1 drivers -v0x2b5d190_0 .alias "in0", 0 0, v0x2b5d820_0; -v0x2b5d230_0 .alias "in1", 0 0, v0x2b5dcf0_0; -v0x2b5d2d0_0 .net "nS", 0 0, L_0x2c80d70; 1 drivers -v0x2b5d380_0 .net "out0", 0 0, L_0x2c80e10; 1 drivers -v0x2b5d420_0 .net "out1", 0 0, L_0x2c80f00; 1 drivers -v0x2b5d500_0 .alias "outfinal", 0 0, v0x2b5d8d0_0; -S_0x2b5bc00 .scope generate, "addbits[3]" "addbits[3]" 3 230, 3 230, S_0x2851a90; - .timescale -9 -12; -P_0x2b5b618 .param/l "i" 3 230, +C4<011>; -S_0x2b5bd70 .scope module, "attempt" "MiddleAddSubSLT" 3 232, 3 89, S_0x2b5bc00; - .timescale -9 -12; -L_0x2c84270/d .functor NOT 1, L_0x2c85730, C4<0>, C4<0>, C4<0>; -L_0x2c84270 .delay (10000,10000,10000) L_0x2c84270/d; -L_0x2c84a10/d .functor NOT 1, L_0x2c84ab0, C4<0>, C4<0>, C4<0>; -L_0x2c84a10 .delay (10000,10000,10000) L_0x2c84a10/d; -L_0x2c84b50/d .functor AND 1, L_0x2c84c90, L_0x2c84a10, C4<1>, C4<1>; -L_0x2c84b50 .delay (20000,20000,20000) L_0x2c84b50/d; -L_0x2c84d30/d .functor XOR 1, L_0x2c85600, L_0x2c847e0, C4<0>, C4<0>; -L_0x2c84d30 .delay (40000,40000,40000) L_0x2c84d30/d; -L_0x2c84e20/d .functor XOR 1, L_0x2c84d30, L_0x2c85860, C4<0>, C4<0>; -L_0x2c84e20 .delay (40000,40000,40000) L_0x2c84e20/d; -L_0x2c84f10/d .functor AND 1, L_0x2c85600, L_0x2c847e0, C4<1>, C4<1>; -L_0x2c84f10 .delay (20000,20000,20000) L_0x2c84f10/d; -L_0x2c85080/d .functor AND 1, L_0x2c84d30, L_0x2c85860, C4<1>, C4<1>; -L_0x2c85080 .delay (20000,20000,20000) L_0x2c85080/d; -L_0x2c85170/d .functor OR 1, L_0x2c84f10, L_0x2c85080, C4<0>, C4<0>; -L_0x2c85170 .delay (20000,20000,20000) L_0x2c85170/d; -v0x2b5c400_0 .net "A", 0 0, L_0x2c85600; 1 drivers -v0x2b5c4c0_0 .net "AandB", 0 0, L_0x2c84f10; 1 drivers -v0x2b5c560_0 .net "AddSubSLTSum", 0 0, L_0x2c84e20; 1 drivers -v0x2b5c600_0 .net "AxorB", 0 0, L_0x2c84d30; 1 drivers -v0x2b5c680_0 .net "B", 0 0, L_0x2c85730; 1 drivers -v0x2b5c730_0 .net "BornB", 0 0, L_0x2c847e0; 1 drivers -v0x2b5c7f0_0 .net "CINandAxorB", 0 0, L_0x2c85080; 1 drivers -v0x2b5c870_0 .alias "Command", 2 0, v0x2bc67a0_0; -v0x2b5c8f0_0 .net *"_s3", 0 0, L_0x2c84ab0; 1 drivers -v0x2b5c970_0 .net *"_s5", 0 0, L_0x2c84c90; 1 drivers -v0x2b5ca10_0 .net "carryin", 0 0, L_0x2c85860; 1 drivers -v0x2b5cab0_0 .net "carryout", 0 0, L_0x2c85170; 1 drivers -v0x2b5cb50_0 .net "nB", 0 0, L_0x2c84270; 1 drivers -v0x2b5cc00_0 .net "nCmd2", 0 0, L_0x2c84a10; 1 drivers -v0x2b5cd00_0 .net "subtract", 0 0, L_0x2c84b50; 1 drivers -L_0x2c84970 .part v0x2bc78e0_0, 0, 1; -L_0x2c84ab0 .part v0x2bc78e0_0, 2, 1; -L_0x2c84c90 .part v0x2bc78e0_0, 0, 1; -S_0x2b5be60 .scope module, "mux0" "TwoInMux" 3 105, 3 8, S_0x2b5bd70; - .timescale -9 -12; -L_0x2c845a0/d .functor NOT 1, L_0x2c84970, C4<0>, C4<0>, C4<0>; -L_0x2c845a0 .delay (10000,10000,10000) L_0x2c845a0/d; -L_0x2c84600/d .functor AND 1, L_0x2c85730, L_0x2c845a0, C4<1>, C4<1>; -L_0x2c84600 .delay (20000,20000,20000) L_0x2c84600/d; -L_0x2c846f0/d .functor AND 1, L_0x2c84270, L_0x2c84970, C4<1>, C4<1>; -L_0x2c846f0 .delay (20000,20000,20000) L_0x2c846f0/d; -L_0x2c847e0/d .functor OR 1, L_0x2c84600, L_0x2c846f0, C4<0>, C4<0>; -L_0x2c847e0 .delay (20000,20000,20000) L_0x2c847e0/d; -v0x2b5bf50_0 .net "S", 0 0, L_0x2c84970; 1 drivers -v0x2b5bff0_0 .alias "in0", 0 0, v0x2b5c680_0; -v0x2b5c090_0 .alias "in1", 0 0, v0x2b5cb50_0; -v0x2b5c130_0 .net "nS", 0 0, L_0x2c845a0; 1 drivers -v0x2b5c1e0_0 .net "out0", 0 0, L_0x2c84600; 1 drivers -v0x2b5c280_0 .net "out1", 0 0, L_0x2c846f0; 1 drivers -v0x2b5c360_0 .alias "outfinal", 0 0, v0x2b5c730_0; -S_0x2b5aa60 .scope generate, "addbits[4]" "addbits[4]" 3 230, 3 230, S_0x2851a90; - .timescale -9 -12; -P_0x2b5a478 .param/l "i" 3 230, +C4<0100>; -S_0x2b5abd0 .scope module, "attempt" "MiddleAddSubSLT" 3 232, 3 89, S_0x2b5aa60; - .timescale -9 -12; -L_0x2c856a0/d .functor NOT 1, L_0x2c86970, C4<0>, C4<0>, C4<0>; -L_0x2c856a0 .delay (10000,10000,10000) L_0x2c856a0/d; -L_0x2c85ef0/d .functor NOT 1, L_0x2c85f90, C4<0>, C4<0>, C4<0>; -L_0x2c85ef0 .delay (10000,10000,10000) L_0x2c85ef0/d; -L_0x2c86030/d .functor AND 1, L_0x2c86170, L_0x2c85ef0, C4<1>, C4<1>; -L_0x2c86030 .delay (20000,20000,20000) L_0x2c86030/d; -L_0x2c86210/d .functor XOR 1, L_0x2c86a70, L_0x2c85cc0, C4<0>, C4<0>; -L_0x2c86210 .delay (40000,40000,40000) L_0x2c86210/d; -L_0x2c86300/d .functor XOR 1, L_0x2c86210, L_0x2c86c60, C4<0>, C4<0>; -L_0x2c86300 .delay (40000,40000,40000) L_0x2c86300/d; -L_0x2c863f0/d .functor AND 1, L_0x2c86a70, L_0x2c85cc0, C4<1>, C4<1>; -L_0x2c863f0 .delay (20000,20000,20000) L_0x2c863f0/d; -L_0x2c86560/d .functor AND 1, L_0x2c86210, L_0x2c86c60, C4<1>, C4<1>; -L_0x2c86560 .delay (20000,20000,20000) L_0x2c86560/d; -L_0x2c86650/d .functor OR 1, L_0x2c863f0, L_0x2c86560, C4<0>, C4<0>; -L_0x2c86650 .delay (20000,20000,20000) L_0x2c86650/d; -v0x2b5b260_0 .net "A", 0 0, L_0x2c86a70; 1 drivers -v0x2b5b320_0 .net "AandB", 0 0, L_0x2c863f0; 1 drivers -v0x2b5b3c0_0 .net "AddSubSLTSum", 0 0, L_0x2c86300; 1 drivers -v0x2b5b460_0 .net "AxorB", 0 0, L_0x2c86210; 1 drivers -v0x2b5b4e0_0 .net "B", 0 0, L_0x2c86970; 1 drivers -v0x2b5b590_0 .net "BornB", 0 0, L_0x2c85cc0; 1 drivers -v0x2b5b650_0 .net "CINandAxorB", 0 0, L_0x2c86560; 1 drivers -v0x2b5b6d0_0 .alias "Command", 2 0, v0x2bc67a0_0; -v0x2b5b750_0 .net *"_s3", 0 0, L_0x2c85f90; 1 drivers -v0x2b5b7d0_0 .net *"_s5", 0 0, L_0x2c86170; 1 drivers -v0x2b5b870_0 .net "carryin", 0 0, L_0x2c86c60; 1 drivers -v0x2b5b910_0 .net "carryout", 0 0, L_0x2c86650; 1 drivers -v0x2b5b9b0_0 .net "nB", 0 0, L_0x2c856a0; 1 drivers -v0x2b5ba60_0 .net "nCmd2", 0 0, L_0x2c85ef0; 1 drivers -v0x2b5bb60_0 .net "subtract", 0 0, L_0x2c86030; 1 drivers -L_0x2c85e50 .part v0x2bc78e0_0, 0, 1; -L_0x2c85f90 .part v0x2bc78e0_0, 2, 1; -L_0x2c86170 .part v0x2bc78e0_0, 0, 1; -S_0x2b5acc0 .scope module, "mux0" "TwoInMux" 3 105, 3 8, S_0x2b5abd0; - .timescale -9 -12; -L_0x2c85a40/d .functor NOT 1, L_0x2c85e50, C4<0>, C4<0>, C4<0>; -L_0x2c85a40 .delay (10000,10000,10000) L_0x2c85a40/d; -L_0x2c85ae0/d .functor AND 1, L_0x2c86970, L_0x2c85a40, C4<1>, C4<1>; -L_0x2c85ae0 .delay (20000,20000,20000) L_0x2c85ae0/d; -L_0x2c85bd0/d .functor AND 1, L_0x2c856a0, L_0x2c85e50, C4<1>, C4<1>; -L_0x2c85bd0 .delay (20000,20000,20000) L_0x2c85bd0/d; -L_0x2c85cc0/d .functor OR 1, L_0x2c85ae0, L_0x2c85bd0, C4<0>, C4<0>; -L_0x2c85cc0 .delay (20000,20000,20000) L_0x2c85cc0/d; -v0x2b5adb0_0 .net "S", 0 0, L_0x2c85e50; 1 drivers -v0x2b5ae50_0 .alias "in0", 0 0, v0x2b5b4e0_0; -v0x2b5aef0_0 .alias "in1", 0 0, v0x2b5b9b0_0; -v0x2b5af90_0 .net "nS", 0 0, L_0x2c85a40; 1 drivers -v0x2b5b040_0 .net "out0", 0 0, L_0x2c85ae0; 1 drivers -v0x2b5b0e0_0 .net "out1", 0 0, L_0x2c85bd0; 1 drivers -v0x2b5b1c0_0 .alias "outfinal", 0 0, v0x2b5b590_0; -S_0x2b598c0 .scope generate, "addbits[5]" "addbits[5]" 3 230, 3 230, S_0x2851a90; - .timescale -9 -12; -P_0x2b592d8 .param/l "i" 3 230, +C4<0101>; -S_0x2b59a30 .scope module, "attempt" "MiddleAddSubSLT" 3 232, 3 89, S_0x2b598c0; - .timescale -9 -12; -L_0x2c844a0/d .functor NOT 1, L_0x2c87e10, C4<0>, C4<0>, C4<0>; -L_0x2c844a0 .delay (10000,10000,10000) L_0x2c844a0/d; -L_0x2c87390/d .functor NOT 1, L_0x2c87430, C4<0>, C4<0>, C4<0>; -L_0x2c87390 .delay (10000,10000,10000) L_0x2c87390/d; -L_0x2c874d0/d .functor AND 1, L_0x2c87610, L_0x2c87390, C4<1>, C4<1>; -L_0x2c874d0 .delay (20000,20000,20000) L_0x2c874d0/d; -L_0x2c876b0/d .functor XOR 1, L_0x2c87f40, L_0x2c87160, C4<0>, C4<0>; -L_0x2c876b0 .delay (40000,40000,40000) L_0x2c876b0/d; -L_0x2c877a0/d .functor XOR 1, L_0x2c876b0, L_0x2c88160, C4<0>, C4<0>; -L_0x2c877a0 .delay (40000,40000,40000) L_0x2c877a0/d; -L_0x2c87890/d .functor AND 1, L_0x2c87f40, L_0x2c87160, C4<1>, C4<1>; -L_0x2c87890 .delay (20000,20000,20000) L_0x2c87890/d; -L_0x2c87a00/d .functor AND 1, L_0x2c876b0, L_0x2c88160, C4<1>, C4<1>; -L_0x2c87a00 .delay (20000,20000,20000) L_0x2c87a00/d; -L_0x2c87af0/d .functor OR 1, L_0x2c87890, L_0x2c87a00, C4<0>, C4<0>; -L_0x2c87af0 .delay (20000,20000,20000) L_0x2c87af0/d; -v0x2b5a0c0_0 .net "A", 0 0, L_0x2c87f40; 1 drivers -v0x2b5a180_0 .net "AandB", 0 0, L_0x2c87890; 1 drivers -v0x2b5a220_0 .net "AddSubSLTSum", 0 0, L_0x2c877a0; 1 drivers -v0x2b5a2c0_0 .net "AxorB", 0 0, L_0x2c876b0; 1 drivers -v0x2b5a340_0 .net "B", 0 0, L_0x2c87e10; 1 drivers -v0x2b5a3f0_0 .net "BornB", 0 0, L_0x2c87160; 1 drivers -v0x2b5a4b0_0 .net "CINandAxorB", 0 0, L_0x2c87a00; 1 drivers -v0x2b5a530_0 .alias "Command", 2 0, v0x2bc67a0_0; -v0x2b5a5b0_0 .net *"_s3", 0 0, L_0x2c87430; 1 drivers -v0x2b5a630_0 .net *"_s5", 0 0, L_0x2c87610; 1 drivers -v0x2b5a6d0_0 .net "carryin", 0 0, L_0x2c88160; 1 drivers -v0x2b5a770_0 .net "carryout", 0 0, L_0x2c87af0; 1 drivers -v0x2b5a810_0 .net "nB", 0 0, L_0x2c844a0; 1 drivers -v0x2b5a8c0_0 .net "nCmd2", 0 0, L_0x2c87390; 1 drivers -v0x2b5a9c0_0 .net "subtract", 0 0, L_0x2c874d0; 1 drivers -L_0x2c872f0 .part v0x2bc78e0_0, 0, 1; -L_0x2c87430 .part v0x2bc78e0_0, 2, 1; -L_0x2c87610 .part v0x2bc78e0_0, 0, 1; -S_0x2b59b20 .scope module, "mux0" "TwoInMux" 3 105, 3 8, S_0x2b59a30; - .timescale -9 -12; -L_0x2c86ee0/d .functor NOT 1, L_0x2c872f0, C4<0>, C4<0>, C4<0>; -L_0x2c86ee0 .delay (10000,10000,10000) L_0x2c86ee0/d; -L_0x2c86f80/d .functor AND 1, L_0x2c87e10, L_0x2c86ee0, C4<1>, C4<1>; -L_0x2c86f80 .delay (20000,20000,20000) L_0x2c86f80/d; -L_0x2c87070/d .functor AND 1, L_0x2c844a0, L_0x2c872f0, C4<1>, C4<1>; -L_0x2c87070 .delay (20000,20000,20000) L_0x2c87070/d; -L_0x2c87160/d .functor OR 1, L_0x2c86f80, L_0x2c87070, C4<0>, C4<0>; -L_0x2c87160 .delay (20000,20000,20000) L_0x2c87160/d; -v0x2b59c10_0 .net "S", 0 0, L_0x2c872f0; 1 drivers -v0x2b59cb0_0 .alias "in0", 0 0, v0x2b5a340_0; -v0x2b59d50_0 .alias "in1", 0 0, v0x2b5a810_0; -v0x2b59df0_0 .net "nS", 0 0, L_0x2c86ee0; 1 drivers -v0x2b59ea0_0 .net "out0", 0 0, L_0x2c86f80; 1 drivers -v0x2b59f40_0 .net "out1", 0 0, L_0x2c87070; 1 drivers -v0x2b5a020_0 .alias "outfinal", 0 0, v0x2b5a3f0_0; -S_0x2b58720 .scope generate, "addbits[6]" "addbits[6]" 3 230, 3 230, S_0x2851a90; - .timescale -9 -12; -P_0x2b58138 .param/l "i" 3 230, +C4<0110>; -S_0x2b58890 .scope module, "attempt" "MiddleAddSubSLT" 3 232, 3 89, S_0x2b58720; - .timescale -9 -12; -L_0x2c87fe0/d .functor NOT 1, L_0x2c89200, C4<0>, C4<0>, C4<0>; -L_0x2c87fe0 .delay (10000,10000,10000) L_0x2c87fe0/d; -L_0x2c88780/d .functor NOT 1, L_0x2c88820, C4<0>, C4<0>, C4<0>; -L_0x2c88780 .delay (10000,10000,10000) L_0x2c88780/d; -L_0x2c888c0/d .functor AND 1, L_0x2c88a00, L_0x2c88780, C4<1>, C4<1>; -L_0x2c888c0 .delay (20000,20000,20000) L_0x2c888c0/d; -L_0x2c88aa0/d .functor XOR 1, L_0x2c89310, L_0x2c88550, C4<0>, C4<0>; -L_0x2c88aa0 .delay (40000,40000,40000) L_0x2c88aa0/d; -L_0x2c88b90/d .functor XOR 1, L_0x2c88aa0, L_0x2c89560, C4<0>, C4<0>; -L_0x2c88b90 .delay (40000,40000,40000) L_0x2c88b90/d; -L_0x2c88c80/d .functor AND 1, L_0x2c89310, L_0x2c88550, C4<1>, C4<1>; -L_0x2c88c80 .delay (20000,20000,20000) L_0x2c88c80/d; -L_0x2c88df0/d .functor AND 1, L_0x2c88aa0, L_0x2c89560, C4<1>, C4<1>; -L_0x2c88df0 .delay (20000,20000,20000) L_0x2c88df0/d; -L_0x2c88ee0/d .functor OR 1, L_0x2c88c80, L_0x2c88df0, C4<0>, C4<0>; -L_0x2c88ee0 .delay (20000,20000,20000) L_0x2c88ee0/d; -v0x2b58f20_0 .net "A", 0 0, L_0x2c89310; 1 drivers -v0x2b58fe0_0 .net "AandB", 0 0, L_0x2c88c80; 1 drivers -v0x2b59080_0 .net "AddSubSLTSum", 0 0, L_0x2c88b90; 1 drivers -v0x2b59120_0 .net "AxorB", 0 0, L_0x2c88aa0; 1 drivers -v0x2b591a0_0 .net "B", 0 0, L_0x2c89200; 1 drivers -v0x2b59250_0 .net "BornB", 0 0, L_0x2c88550; 1 drivers -v0x2b59310_0 .net "CINandAxorB", 0 0, L_0x2c88df0; 1 drivers -v0x2b59390_0 .alias "Command", 2 0, v0x2bc67a0_0; -v0x2b59410_0 .net *"_s3", 0 0, L_0x2c88820; 1 drivers -v0x2b59490_0 .net *"_s5", 0 0, L_0x2c88a00; 1 drivers -v0x2b59530_0 .net "carryin", 0 0, L_0x2c89560; 1 drivers -v0x2b595d0_0 .net "carryout", 0 0, L_0x2c88ee0; 1 drivers -v0x2b59670_0 .net "nB", 0 0, L_0x2c87fe0; 1 drivers -v0x2b59720_0 .net "nCmd2", 0 0, L_0x2c88780; 1 drivers -v0x2b59820_0 .net "subtract", 0 0, L_0x2c888c0; 1 drivers -L_0x2c886e0 .part v0x2bc78e0_0, 0, 1; -L_0x2c88820 .part v0x2bc78e0_0, 2, 1; -L_0x2c88a00 .part v0x2bc78e0_0, 0, 1; -S_0x2b58980 .scope module, "mux0" "TwoInMux" 3 105, 3 8, S_0x2b58890; - .timescale -9 -12; -L_0x2c88350/d .functor NOT 1, L_0x2c886e0, C4<0>, C4<0>, C4<0>; -L_0x2c88350 .delay (10000,10000,10000) L_0x2c88350/d; -L_0x2c883b0/d .functor AND 1, L_0x2c89200, L_0x2c88350, C4<1>, C4<1>; -L_0x2c883b0 .delay (20000,20000,20000) L_0x2c883b0/d; -L_0x2c88460/d .functor AND 1, L_0x2c87fe0, L_0x2c886e0, C4<1>, C4<1>; -L_0x2c88460 .delay (20000,20000,20000) L_0x2c88460/d; -L_0x2c88550/d .functor OR 1, L_0x2c883b0, L_0x2c88460, C4<0>, C4<0>; -L_0x2c88550 .delay (20000,20000,20000) L_0x2c88550/d; -v0x2b58a70_0 .net "S", 0 0, L_0x2c886e0; 1 drivers -v0x2b58b10_0 .alias "in0", 0 0, v0x2b591a0_0; -v0x2b58bb0_0 .alias "in1", 0 0, v0x2b59670_0; -v0x2b58c50_0 .net "nS", 0 0, L_0x2c88350; 1 drivers -v0x2b58d00_0 .net "out0", 0 0, L_0x2c883b0; 1 drivers -v0x2b58da0_0 .net "out1", 0 0, L_0x2c88460; 1 drivers -v0x2b58e80_0 .alias "outfinal", 0 0, v0x2b59250_0; -S_0x2b57580 .scope generate, "addbits[7]" "addbits[7]" 3 230, 3 230, S_0x2851a90; - .timescale -9 -12; -P_0x2b56f98 .param/l "i" 3 230, +C4<0111>; -S_0x2b576f0 .scope module, "attempt" "MiddleAddSubSLT" 3 232, 3 89, S_0x2b57580; - .timescale -9 -12; -L_0x2c892a0/d .functor NOT 1, L_0x2c8a600, C4<0>, C4<0>, C4<0>; -L_0x2c892a0 .delay (10000,10000,10000) L_0x2c892a0/d; -L_0x2c89b80/d .functor NOT 1, L_0x2c89c20, C4<0>, C4<0>, C4<0>; -L_0x2c89b80 .delay (10000,10000,10000) L_0x2c89b80/d; -L_0x2c89cc0/d .functor AND 1, L_0x2c89e00, L_0x2c89b80, C4<1>, C4<1>; -L_0x2c89cc0 .delay (20000,20000,20000) L_0x2c89cc0/d; -L_0x2c89ea0/d .functor XOR 1, L_0x2c8a740, L_0x2c89950, C4<0>, C4<0>; -L_0x2c89ea0 .delay (40000,40000,40000) L_0x2c89ea0/d; -L_0x2c89f90/d .functor XOR 1, L_0x2c89ea0, L_0x2c8a930, C4<0>, C4<0>; -L_0x2c89f90 .delay (40000,40000,40000) L_0x2c89f90/d; -L_0x2c8a080/d .functor AND 1, L_0x2c8a740, L_0x2c89950, C4<1>, C4<1>; -L_0x2c8a080 .delay (20000,20000,20000) L_0x2c8a080/d; -L_0x2c8a1f0/d .functor AND 1, L_0x2c89ea0, L_0x2c8a930, C4<1>, C4<1>; -L_0x2c8a1f0 .delay (20000,20000,20000) L_0x2c8a1f0/d; -L_0x2c8a2e0/d .functor OR 1, L_0x2c8a080, L_0x2c8a1f0, C4<0>, C4<0>; -L_0x2c8a2e0 .delay (20000,20000,20000) L_0x2c8a2e0/d; -v0x2b57d80_0 .net "A", 0 0, L_0x2c8a740; 1 drivers -v0x2b57e40_0 .net "AandB", 0 0, L_0x2c8a080; 1 drivers -v0x2b57ee0_0 .net "AddSubSLTSum", 0 0, L_0x2c89f90; 1 drivers -v0x2b57f80_0 .net "AxorB", 0 0, L_0x2c89ea0; 1 drivers -v0x2b58000_0 .net "B", 0 0, L_0x2c8a600; 1 drivers -v0x2b580b0_0 .net "BornB", 0 0, L_0x2c89950; 1 drivers -v0x2b58170_0 .net "CINandAxorB", 0 0, L_0x2c8a1f0; 1 drivers -v0x2b581f0_0 .alias "Command", 2 0, v0x2bc67a0_0; -v0x2b58270_0 .net *"_s3", 0 0, L_0x2c89c20; 1 drivers -v0x2b582f0_0 .net *"_s5", 0 0, L_0x2c89e00; 1 drivers -v0x2b58390_0 .net "carryin", 0 0, L_0x2c8a930; 1 drivers -v0x2b58430_0 .net "carryout", 0 0, L_0x2c8a2e0; 1 drivers -v0x2b584d0_0 .net "nB", 0 0, L_0x2c892a0; 1 drivers -v0x2b58580_0 .net "nCmd2", 0 0, L_0x2c89b80; 1 drivers -v0x2b58680_0 .net "subtract", 0 0, L_0x2c89cc0; 1 drivers -L_0x2c89ae0 .part v0x2bc78e0_0, 0, 1; -L_0x2c89c20 .part v0x2bc78e0_0, 2, 1; -L_0x2c89e00 .part v0x2bc78e0_0, 0, 1; -S_0x2b577e0 .scope module, "mux0" "TwoInMux" 3 105, 3 8, S_0x2b576f0; - .timescale -9 -12; -L_0x2c89450/d .functor NOT 1, L_0x2c89ae0, C4<0>, C4<0>, C4<0>; -L_0x2c89450 .delay (10000,10000,10000) L_0x2c89450/d; -L_0x2c89770/d .functor AND 1, L_0x2c8a600, L_0x2c89450, C4<1>, C4<1>; -L_0x2c89770 .delay (20000,20000,20000) L_0x2c89770/d; -L_0x2c89860/d .functor AND 1, L_0x2c892a0, L_0x2c89ae0, C4<1>, C4<1>; -L_0x2c89860 .delay (20000,20000,20000) L_0x2c89860/d; -L_0x2c89950/d .functor OR 1, L_0x2c89770, L_0x2c89860, C4<0>, C4<0>; -L_0x2c89950 .delay (20000,20000,20000) L_0x2c89950/d; -v0x2b578d0_0 .net "S", 0 0, L_0x2c89ae0; 1 drivers -v0x2b57970_0 .alias "in0", 0 0, v0x2b58000_0; -v0x2b57a10_0 .alias "in1", 0 0, v0x2b584d0_0; -v0x2b57ab0_0 .net "nS", 0 0, L_0x2c89450; 1 drivers -v0x2b57b60_0 .net "out0", 0 0, L_0x2c89770; 1 drivers -v0x2b57c00_0 .net "out1", 0 0, L_0x2c89860; 1 drivers -v0x2b57ce0_0 .alias "outfinal", 0 0, v0x2b580b0_0; -S_0x2b563e0 .scope generate, "addbits[8]" "addbits[8]" 3 230, 3 230, S_0x2851a90; - .timescale -9 -12; -P_0x2b55df8 .param/l "i" 3 230, +C4<01000>; -S_0x2b56550 .scope module, "attempt" "MiddleAddSubSLT" 3 232, 3 89, S_0x2b563e0; - .timescale -9 -12; -L_0x2c8a7e0/d .functor NOT 1, L_0x2c8ba60, C4<0>, C4<0>, C4<0>; -L_0x2c8a7e0 .delay (10000,10000,10000) L_0x2c8a7e0/d; -L_0x2c8afa0/d .functor NOT 1, L_0x2c8b040, C4<0>, C4<0>, C4<0>; -L_0x2c8afa0 .delay (10000,10000,10000) L_0x2c8afa0/d; -L_0x2c8b0e0/d .functor AND 1, L_0x2c8b220, L_0x2c8afa0, C4<1>, C4<1>; -L_0x2c8b0e0 .delay (20000,20000,20000) L_0x2c8b0e0/d; -L_0x2c8b2c0/d .functor XOR 1, L_0x2c8bbd0, L_0x2c8ad70, C4<0>, C4<0>; -L_0x2c8b2c0 .delay (40000,40000,40000) L_0x2c8b2c0/d; -L_0x2c8b3b0/d .functor XOR 1, L_0x2c8b2c0, L_0x2c8bdf0, C4<0>, C4<0>; -L_0x2c8b3b0 .delay (40000,40000,40000) L_0x2c8b3b0/d; -L_0x2c8b4a0/d .functor AND 1, L_0x2c8bbd0, L_0x2c8ad70, C4<1>, C4<1>; -L_0x2c8b4a0 .delay (20000,20000,20000) L_0x2c8b4a0/d; -L_0x2c8b610/d .functor AND 1, L_0x2c8b2c0, L_0x2c8bdf0, C4<1>, C4<1>; -L_0x2c8b610 .delay (20000,20000,20000) L_0x2c8b610/d; -L_0x2c8b720/d .functor OR 1, L_0x2c8b4a0, L_0x2c8b610, C4<0>, C4<0>; -L_0x2c8b720 .delay (20000,20000,20000) L_0x2c8b720/d; -v0x2b56be0_0 .net "A", 0 0, L_0x2c8bbd0; 1 drivers -v0x2b56ca0_0 .net "AandB", 0 0, L_0x2c8b4a0; 1 drivers -v0x2b56d40_0 .net "AddSubSLTSum", 0 0, L_0x2c8b3b0; 1 drivers -v0x2b56de0_0 .net "AxorB", 0 0, L_0x2c8b2c0; 1 drivers -v0x2b56e60_0 .net "B", 0 0, L_0x2c8ba60; 1 drivers -v0x2b56f10_0 .net "BornB", 0 0, L_0x2c8ad70; 1 drivers -v0x2b56fd0_0 .net "CINandAxorB", 0 0, L_0x2c8b610; 1 drivers -v0x2b57050_0 .alias "Command", 2 0, v0x2bc67a0_0; -v0x2b570d0_0 .net *"_s3", 0 0, L_0x2c8b040; 1 drivers -v0x2b57150_0 .net *"_s5", 0 0, L_0x2c8b220; 1 drivers -v0x2b571f0_0 .net "carryin", 0 0, L_0x2c8bdf0; 1 drivers -v0x2b57290_0 .net "carryout", 0 0, L_0x2c8b720; 1 drivers -v0x2b57330_0 .net "nB", 0 0, L_0x2c8a7e0; 1 drivers -v0x2b573e0_0 .net "nCmd2", 0 0, L_0x2c8afa0; 1 drivers -v0x2b574e0_0 .net "subtract", 0 0, L_0x2c8b0e0; 1 drivers -L_0x2c8af00 .part v0x2bc78e0_0, 0, 1; -L_0x2c8b040 .part v0x2bc78e0_0, 2, 1; -L_0x2c8b220 .part v0x2bc78e0_0, 0, 1; -S_0x2b56640 .scope module, "mux0" "TwoInMux" 3 105, 3 8, S_0x2b56550; - .timescale -9 -12; -L_0x2c8ab30/d .functor NOT 1, L_0x2c8af00, C4<0>, C4<0>, C4<0>; -L_0x2c8ab30 .delay (10000,10000,10000) L_0x2c8ab30/d; -L_0x2c8ab90/d .functor AND 1, L_0x2c8ba60, L_0x2c8ab30, C4<1>, C4<1>; -L_0x2c8ab90 .delay (20000,20000,20000) L_0x2c8ab90/d; -L_0x2c8ac80/d .functor AND 1, L_0x2c8a7e0, L_0x2c8af00, C4<1>, C4<1>; -L_0x2c8ac80 .delay (20000,20000,20000) L_0x2c8ac80/d; -L_0x2c8ad70/d .functor OR 1, L_0x2c8ab90, L_0x2c8ac80, C4<0>, C4<0>; -L_0x2c8ad70 .delay (20000,20000,20000) L_0x2c8ad70/d; -v0x2b56730_0 .net "S", 0 0, L_0x2c8af00; 1 drivers -v0x2b567d0_0 .alias "in0", 0 0, v0x2b56e60_0; -v0x2b56870_0 .alias "in1", 0 0, v0x2b57330_0; -v0x2b56910_0 .net "nS", 0 0, L_0x2c8ab30; 1 drivers -v0x2b569c0_0 .net "out0", 0 0, L_0x2c8ab90; 1 drivers -v0x2b56a60_0 .net "out1", 0 0, L_0x2c8ac80; 1 drivers -v0x2b56b40_0 .alias "outfinal", 0 0, v0x2b56f10_0; -S_0x2b55240 .scope generate, "addbits[9]" "addbits[9]" 3 230, 3 230, S_0x2851a90; - .timescale -9 -12; -P_0x2b54c58 .param/l "i" 3 230, +C4<01001>; -S_0x2b553b0 .scope module, "attempt" "MiddleAddSubSLT" 3 232, 3 89, S_0x2b55240; - .timescale -9 -12; -L_0x2c8aac0/d .functor NOT 1, L_0x2c8d220, C4<0>, C4<0>, C4<0>; -L_0x2c8aac0 .delay (10000,10000,10000) L_0x2c8aac0/d; -L_0x2c8c5b0/d .functor NOT 1, L_0x2c8c670, C4<0>, C4<0>, C4<0>; -L_0x2c8c5b0 .delay (10000,10000,10000) L_0x2c8c5b0/d; -L_0x2c8c710/d .functor AND 1, L_0x2c8c850, L_0x2c8c5b0, C4<1>, C4<1>; -L_0x2c8c710 .delay (20000,20000,20000) L_0x2c8c710/d; -L_0x2c8c8f0/d .functor XOR 1, L_0x2c8c190, L_0x2c8c340, C4<0>, C4<0>; -L_0x2c8c8f0 .delay (40000,40000,40000) L_0x2c8c8f0/d; -L_0x2c8c9e0/d .functor XOR 1, L_0x2c8c8f0, L_0x2c8d350, C4<0>, C4<0>; -L_0x2c8c9e0 .delay (40000,40000,40000) L_0x2c8c9e0/d; -L_0x2c8cad0/d .functor AND 1, L_0x2c8c190, L_0x2c8c340, C4<1>, C4<1>; -L_0x2c8cad0 .delay (20000,20000,20000) L_0x2c8cad0/d; -L_0x2c8cc40/d .functor AND 1, L_0x2c8c8f0, L_0x2c8d350, C4<1>, C4<1>; -L_0x2c8cc40 .delay (20000,20000,20000) L_0x2c8cc40/d; -L_0x2c8cd30/d .functor OR 1, L_0x2c8cad0, L_0x2c8cc40, C4<0>, C4<0>; -L_0x2c8cd30 .delay (20000,20000,20000) L_0x2c8cd30/d; -v0x2b55a40_0 .net "A", 0 0, L_0x2c8c190; 1 drivers -v0x2b55b00_0 .net "AandB", 0 0, L_0x2c8cad0; 1 drivers -v0x2b55ba0_0 .net "AddSubSLTSum", 0 0, L_0x2c8c9e0; 1 drivers -v0x2b55c40_0 .net "AxorB", 0 0, L_0x2c8c8f0; 1 drivers -v0x2b55cc0_0 .net "B", 0 0, L_0x2c8d220; 1 drivers -v0x2b55d70_0 .net "BornB", 0 0, L_0x2c8c340; 1 drivers -v0x2b55e30_0 .net "CINandAxorB", 0 0, L_0x2c8cc40; 1 drivers -v0x2b55eb0_0 .alias "Command", 2 0, v0x2bc67a0_0; -v0x2b55f30_0 .net *"_s3", 0 0, L_0x2c8c670; 1 drivers -v0x2b55fb0_0 .net *"_s5", 0 0, L_0x2c8c850; 1 drivers -v0x2b56050_0 .net "carryin", 0 0, L_0x2c8d350; 1 drivers -v0x2b560f0_0 .net "carryout", 0 0, L_0x2c8cd30; 1 drivers -v0x2b56190_0 .net "nB", 0 0, L_0x2c8aac0; 1 drivers -v0x2b56240_0 .net "nCmd2", 0 0, L_0x2c8c5b0; 1 drivers -v0x2b56340_0 .net "subtract", 0 0, L_0x2c8c710; 1 drivers -L_0x2c8c510 .part v0x2bc78e0_0, 0, 1; -L_0x2c8c670 .part v0x2bc78e0_0, 2, 1; -L_0x2c8c850 .part v0x2bc78e0_0, 0, 1; -S_0x2b554a0 .scope module, "mux0" "TwoInMux" 3 105, 3 8, S_0x2b553b0; - .timescale -9 -12; -L_0x2c8bc70/d .functor NOT 1, L_0x2c8c510, C4<0>, C4<0>, C4<0>; -L_0x2c8bc70 .delay (10000,10000,10000) L_0x2c8bc70/d; -L_0x2c8bd30/d .functor AND 1, L_0x2c8d220, L_0x2c8bc70, C4<1>, C4<1>; -L_0x2c8bd30 .delay (20000,20000,20000) L_0x2c8bd30/d; -L_0x2c8c230/d .functor AND 1, L_0x2c8aac0, L_0x2c8c510, C4<1>, C4<1>; -L_0x2c8c230 .delay (20000,20000,20000) L_0x2c8c230/d; -L_0x2c8c340/d .functor OR 1, L_0x2c8bd30, L_0x2c8c230, C4<0>, C4<0>; -L_0x2c8c340 .delay (20000,20000,20000) L_0x2c8c340/d; -v0x2b55590_0 .net "S", 0 0, L_0x2c8c510; 1 drivers -v0x2b55630_0 .alias "in0", 0 0, v0x2b55cc0_0; -v0x2b556d0_0 .alias "in1", 0 0, v0x2b56190_0; -v0x2b55770_0 .net "nS", 0 0, L_0x2c8bc70; 1 drivers -v0x2b55820_0 .net "out0", 0 0, L_0x2c8bd30; 1 drivers -v0x2b558c0_0 .net "out1", 0 0, L_0x2c8c230; 1 drivers -v0x2b559a0_0 .alias "outfinal", 0 0, v0x2b55d70_0; -S_0x2b540a0 .scope generate, "addbits[10]" "addbits[10]" 3 230, 3 230, S_0x2851a90; - .timescale -9 -12; -P_0x2b53ab8 .param/l "i" 3 230, +C4<01010>; -S_0x2b54210 .scope module, "attempt" "MiddleAddSubSLT" 3 232, 3 89, S_0x2b540a0; - .timescale -9 -12; -L_0x2c8d070/d .functor NOT 1, L_0x2c8e760, C4<0>, C4<0>, C4<0>; -L_0x2c8d070 .delay (10000,10000,10000) L_0x2c8d070/d; -L_0x2c8dac0/d .functor NOT 1, L_0x2c8db80, C4<0>, C4<0>, C4<0>; -L_0x2c8dac0 .delay (10000,10000,10000) L_0x2c8dac0/d; -L_0x2c8dc20/d .functor AND 1, L_0x2c8dd60, L_0x2c8dac0, C4<1>, C4<1>; -L_0x2c8dc20 .delay (20000,20000,20000) L_0x2c8dc20/d; -L_0x2c8de00/d .functor XOR 1, L_0x2c8d4e0, L_0x2c8d850, C4<0>, C4<0>; -L_0x2c8de00 .delay (40000,40000,40000) L_0x2c8de00/d; -L_0x2c8def0/d .functor XOR 1, L_0x2c8de00, L_0x2c8e890, C4<0>, C4<0>; -L_0x2c8def0 .delay (40000,40000,40000) L_0x2c8def0/d; -L_0x2c8dfe0/d .functor AND 1, L_0x2c8d4e0, L_0x2c8d850, C4<1>, C4<1>; -L_0x2c8dfe0 .delay (20000,20000,20000) L_0x2c8dfe0/d; -L_0x2c8e150/d .functor AND 1, L_0x2c8de00, L_0x2c8e890, C4<1>, C4<1>; -L_0x2c8e150 .delay (20000,20000,20000) L_0x2c8e150/d; -L_0x2c8e240/d .functor OR 1, L_0x2c8dfe0, L_0x2c8e150, C4<0>, C4<0>; -L_0x2c8e240 .delay (20000,20000,20000) L_0x2c8e240/d; -v0x2b548a0_0 .net "A", 0 0, L_0x2c8d4e0; 1 drivers -v0x2b54960_0 .net "AandB", 0 0, L_0x2c8dfe0; 1 drivers -v0x2b54a00_0 .net "AddSubSLTSum", 0 0, L_0x2c8def0; 1 drivers -v0x2b54aa0_0 .net "AxorB", 0 0, L_0x2c8de00; 1 drivers -v0x2b54b20_0 .net "B", 0 0, L_0x2c8e760; 1 drivers -v0x2b54bd0_0 .net "BornB", 0 0, L_0x2c8d850; 1 drivers -v0x2b54c90_0 .net "CINandAxorB", 0 0, L_0x2c8e150; 1 drivers -v0x2b54d10_0 .alias "Command", 2 0, v0x2bc67a0_0; -v0x2b54d90_0 .net *"_s3", 0 0, L_0x2c8db80; 1 drivers -v0x2b54e10_0 .net *"_s5", 0 0, L_0x2c8dd60; 1 drivers -v0x2b54eb0_0 .net "carryin", 0 0, L_0x2c8e890; 1 drivers -v0x2b54f50_0 .net "carryout", 0 0, L_0x2c8e240; 1 drivers -v0x2b54ff0_0 .net "nB", 0 0, L_0x2c8d070; 1 drivers -v0x2b550a0_0 .net "nCmd2", 0 0, L_0x2c8dac0; 1 drivers -v0x2b551a0_0 .net "subtract", 0 0, L_0x2c8dc20; 1 drivers -L_0x2c8da20 .part v0x2bc78e0_0, 0, 1; -L_0x2c8db80 .part v0x2bc78e0_0, 2, 1; -L_0x2c8dd60 .part v0x2bc78e0_0, 0, 1; -S_0x2b54300 .scope module, "mux0" "TwoInMux" 3 105, 3 8, S_0x2b54210; - .timescale -9 -12; -L_0x2c8d5b0/d .functor NOT 1, L_0x2c8da20, C4<0>, C4<0>, C4<0>; -L_0x2c8d5b0 .delay (10000,10000,10000) L_0x2c8d5b0/d; -L_0x2c8d650/d .functor AND 1, L_0x2c8e760, L_0x2c8d5b0, C4<1>, C4<1>; -L_0x2c8d650 .delay (20000,20000,20000) L_0x2c8d650/d; -L_0x2c8d740/d .functor AND 1, L_0x2c8d070, L_0x2c8da20, C4<1>, C4<1>; -L_0x2c8d740 .delay (20000,20000,20000) L_0x2c8d740/d; -L_0x2c8d850/d .functor OR 1, L_0x2c8d650, L_0x2c8d740, C4<0>, C4<0>; -L_0x2c8d850 .delay (20000,20000,20000) L_0x2c8d850/d; -v0x2b543f0_0 .net "S", 0 0, L_0x2c8da20; 1 drivers -v0x2b54490_0 .alias "in0", 0 0, v0x2b54b20_0; -v0x2b54530_0 .alias "in1", 0 0, v0x2b54ff0_0; -v0x2b545d0_0 .net "nS", 0 0, L_0x2c8d5b0; 1 drivers -v0x2b54680_0 .net "out0", 0 0, L_0x2c8d650; 1 drivers -v0x2b54720_0 .net "out1", 0 0, L_0x2c8d740; 1 drivers -v0x2b54800_0 .alias "outfinal", 0 0, v0x2b54bd0_0; -S_0x2b52f00 .scope generate, "addbits[11]" "addbits[11]" 3 230, 3 230, S_0x2851a90; - .timescale -9 -12; -P_0x2b52918 .param/l "i" 3 230, +C4<01011>; -S_0x2b53070 .scope module, "attempt" "MiddleAddSubSLT" 3 232, 3 89, S_0x2b52f00; - .timescale -9 -12; -L_0x2c8e580/d .functor NOT 1, L_0x2c8fca0, C4<0>, C4<0>, C4<0>; -L_0x2c8e580 .delay (10000,10000,10000) L_0x2c8e580/d; -L_0x2c8efd0/d .functor NOT 1, L_0x2c8f090, C4<0>, C4<0>, C4<0>; -L_0x2c8efd0 .delay (10000,10000,10000) L_0x2c8efd0/d; -L_0x2c8f130/d .functor AND 1, L_0x2c8f270, L_0x2c8efd0, C4<1>, C4<1>; -L_0x2c8f130 .delay (20000,20000,20000) L_0x2c8f130/d; -L_0x2c8f310/d .functor XOR 1, L_0x2c8ea20, L_0x2c8ed60, C4<0>, C4<0>; -L_0x2c8f310 .delay (40000,40000,40000) L_0x2c8f310/d; -L_0x2c8f400/d .functor XOR 1, L_0x2c8f310, L_0x2c8fdd0, C4<0>, C4<0>; -L_0x2c8f400 .delay (40000,40000,40000) L_0x2c8f400/d; -L_0x2c8f4f0/d .functor AND 1, L_0x2c8ea20, L_0x2c8ed60, C4<1>, C4<1>; -L_0x2c8f4f0 .delay (20000,20000,20000) L_0x2c8f4f0/d; -L_0x2c8f660/d .functor AND 1, L_0x2c8f310, L_0x2c8fdd0, C4<1>, C4<1>; -L_0x2c8f660 .delay (20000,20000,20000) L_0x2c8f660/d; -L_0x2c8f750/d .functor OR 1, L_0x2c8f4f0, L_0x2c8f660, C4<0>, C4<0>; -L_0x2c8f750 .delay (20000,20000,20000) L_0x2c8f750/d; -v0x2b53700_0 .net "A", 0 0, L_0x2c8ea20; 1 drivers -v0x2b537c0_0 .net "AandB", 0 0, L_0x2c8f4f0; 1 drivers -v0x2b53860_0 .net "AddSubSLTSum", 0 0, L_0x2c8f400; 1 drivers -v0x2b53900_0 .net "AxorB", 0 0, L_0x2c8f310; 1 drivers -v0x2b53980_0 .net "B", 0 0, L_0x2c8fca0; 1 drivers -v0x2b53a30_0 .net "BornB", 0 0, L_0x2c8ed60; 1 drivers -v0x2b53af0_0 .net "CINandAxorB", 0 0, L_0x2c8f660; 1 drivers -v0x2b53b70_0 .alias "Command", 2 0, v0x2bc67a0_0; -v0x2b53bf0_0 .net *"_s3", 0 0, L_0x2c8f090; 1 drivers -v0x2b53c70_0 .net *"_s5", 0 0, L_0x2c8f270; 1 drivers -v0x2b53d10_0 .net "carryin", 0 0, L_0x2c8fdd0; 1 drivers -v0x2b53db0_0 .net "carryout", 0 0, L_0x2c8f750; 1 drivers -v0x2b53e50_0 .net "nB", 0 0, L_0x2c8e580; 1 drivers -v0x2b53f00_0 .net "nCmd2", 0 0, L_0x2c8efd0; 1 drivers -v0x2b54000_0 .net "subtract", 0 0, L_0x2c8f130; 1 drivers -L_0x2c8ef30 .part v0x2bc78e0_0, 0, 1; -L_0x2c8f090 .part v0x2bc78e0_0, 2, 1; -L_0x2c8f270 .part v0x2bc78e0_0, 0, 1; -S_0x2b53160 .scope module, "mux0" "TwoInMux" 3 105, 3 8, S_0x2b53070; - .timescale -9 -12; -L_0x2c8e6e0/d .functor NOT 1, L_0x2c8ef30, C4<0>, C4<0>, C4<0>; -L_0x2c8e6e0 .delay (10000,10000,10000) L_0x2c8e6e0/d; -L_0x2c8eb60/d .functor AND 1, L_0x2c8fca0, L_0x2c8e6e0, C4<1>, C4<1>; -L_0x2c8eb60 .delay (20000,20000,20000) L_0x2c8eb60/d; -L_0x2c8ec50/d .functor AND 1, L_0x2c8e580, L_0x2c8ef30, C4<1>, C4<1>; -L_0x2c8ec50 .delay (20000,20000,20000) L_0x2c8ec50/d; -L_0x2c8ed60/d .functor OR 1, L_0x2c8eb60, L_0x2c8ec50, C4<0>, C4<0>; -L_0x2c8ed60 .delay (20000,20000,20000) L_0x2c8ed60/d; -v0x2b53250_0 .net "S", 0 0, L_0x2c8ef30; 1 drivers -v0x2b532f0_0 .alias "in0", 0 0, v0x2b53980_0; -v0x2b53390_0 .alias "in1", 0 0, v0x2b53e50_0; -v0x2b53430_0 .net "nS", 0 0, L_0x2c8e6e0; 1 drivers -v0x2b534e0_0 .net "out0", 0 0, L_0x2c8eb60; 1 drivers -v0x2b53580_0 .net "out1", 0 0, L_0x2c8ec50; 1 drivers -v0x2b53660_0 .alias "outfinal", 0 0, v0x2b53a30_0; -S_0x2b51d60 .scope generate, "addbits[12]" "addbits[12]" 3 230, 3 230, S_0x2851a90; - .timescale -9 -12; -P_0x2b51778 .param/l "i" 3 230, +C4<01100>; -S_0x2b51ed0 .scope module, "attempt" "MiddleAddSubSLT" 3 232, 3 89, S_0x2b51d60; - .timescale -9 -12; -L_0x2c8eac0/d .functor NOT 1, L_0x2c911e0, C4<0>, C4<0>, C4<0>; -L_0x2c8eac0 .delay (10000,10000,10000) L_0x2c8eac0/d; -L_0x2c904e0/d .functor NOT 1, L_0x2c905a0, C4<0>, C4<0>, C4<0>; -L_0x2c904e0 .delay (10000,10000,10000) L_0x2c904e0/d; -L_0x2c90640/d .functor AND 1, L_0x2c90780, L_0x2c904e0, C4<1>, C4<1>; -L_0x2c90640 .delay (20000,20000,20000) L_0x2c90640/d; -L_0x2c90820/d .functor XOR 1, L_0x2c8ff60, L_0x2c90270, C4<0>, C4<0>; -L_0x2c90820 .delay (40000,40000,40000) L_0x2c90820/d; -L_0x2c90910/d .functor XOR 1, L_0x2c90820, L_0x2c91280, C4<0>, C4<0>; -L_0x2c90910 .delay (40000,40000,40000) L_0x2c90910/d; -L_0x2c90a00/d .functor AND 1, L_0x2c8ff60, L_0x2c90270, C4<1>, C4<1>; -L_0x2c90a00 .delay (20000,20000,20000) L_0x2c90a00/d; -L_0x2c90b70/d .functor AND 1, L_0x2c90820, L_0x2c91280, C4<1>, C4<1>; -L_0x2c90b70 .delay (20000,20000,20000) L_0x2c90b70/d; -L_0x2c90c60/d .functor OR 1, L_0x2c90a00, L_0x2c90b70, C4<0>, C4<0>; -L_0x2c90c60 .delay (20000,20000,20000) L_0x2c90c60/d; -v0x2b52560_0 .net "A", 0 0, L_0x2c8ff60; 1 drivers -v0x2b52620_0 .net "AandB", 0 0, L_0x2c90a00; 1 drivers -v0x2b526c0_0 .net "AddSubSLTSum", 0 0, L_0x2c90910; 1 drivers -v0x2b52760_0 .net "AxorB", 0 0, L_0x2c90820; 1 drivers -v0x2b527e0_0 .net "B", 0 0, L_0x2c911e0; 1 drivers -v0x2b52890_0 .net "BornB", 0 0, L_0x2c90270; 1 drivers -v0x2b52950_0 .net "CINandAxorB", 0 0, L_0x2c90b70; 1 drivers -v0x2b529d0_0 .alias "Command", 2 0, v0x2bc67a0_0; -v0x2b52a50_0 .net *"_s3", 0 0, L_0x2c905a0; 1 drivers -v0x2b52ad0_0 .net *"_s5", 0 0, L_0x2c90780; 1 drivers -v0x2b52b70_0 .net "carryin", 0 0, L_0x2c91280; 1 drivers -v0x2b52c10_0 .net "carryout", 0 0, L_0x2c90c60; 1 drivers -v0x2b52cb0_0 .net "nB", 0 0, L_0x2c8eac0; 1 drivers -v0x2b52d60_0 .net "nCmd2", 0 0, L_0x2c904e0; 1 drivers -v0x2b52e60_0 .net "subtract", 0 0, L_0x2c90640; 1 drivers -L_0x2c90440 .part v0x2bc78e0_0, 0, 1; -L_0x2c905a0 .part v0x2bc78e0_0, 2, 1; -L_0x2c90780 .part v0x2bc78e0_0, 0, 1; -S_0x2b51fc0 .scope module, "mux0" "TwoInMux" 3 105, 3 8, S_0x2b51ed0; - .timescale -9 -12; -L_0x2c8fb90/d .functor NOT 1, L_0x2c90440, C4<0>, C4<0>, C4<0>; -L_0x2c8fb90 .delay (10000,10000,10000) L_0x2c8fb90/d; -L_0x2c90090/d .functor AND 1, L_0x2c911e0, L_0x2c8fb90, C4<1>, C4<1>; -L_0x2c90090 .delay (20000,20000,20000) L_0x2c90090/d; -L_0x2c90180/d .functor AND 1, L_0x2c8eac0, L_0x2c90440, C4<1>, C4<1>; -L_0x2c90180 .delay (20000,20000,20000) L_0x2c90180/d; -L_0x2c90270/d .functor OR 1, L_0x2c90090, L_0x2c90180, C4<0>, C4<0>; -L_0x2c90270 .delay (20000,20000,20000) L_0x2c90270/d; -v0x2b520b0_0 .net "S", 0 0, L_0x2c90440; 1 drivers -v0x2b52150_0 .alias "in0", 0 0, v0x2b527e0_0; -v0x2b521f0_0 .alias "in1", 0 0, v0x2b52cb0_0; -v0x2b52290_0 .net "nS", 0 0, L_0x2c8fb90; 1 drivers -v0x2b52340_0 .net "out0", 0 0, L_0x2c90090; 1 drivers -v0x2b523e0_0 .net "out1", 0 0, L_0x2c90180; 1 drivers -v0x2b524c0_0 .alias "outfinal", 0 0, v0x2b52890_0; -S_0x2b50bc0 .scope generate, "addbits[13]" "addbits[13]" 3 230, 3 230, S_0x2851a90; - .timescale -9 -12; -P_0x2b505d8 .param/l "i" 3 230, +C4<01101>; -S_0x2b50d30 .scope module, "attempt" "MiddleAddSubSLT" 3 232, 3 89, S_0x2b50bc0; - .timescale -9 -12; -L_0x2c90fa0/d .functor NOT 1, L_0x2c914b0, C4<0>, C4<0>, C4<0>; -L_0x2c90fa0 .delay (10000,10000,10000) L_0x2c90fa0/d; -L_0x2c919e0/d .functor NOT 1, L_0x2c91aa0, C4<0>, C4<0>, C4<0>; -L_0x2c919e0 .delay (10000,10000,10000) L_0x2c919e0/d; -L_0x2c91b40/d .functor AND 1, L_0x2c91c80, L_0x2c919e0, C4<1>, C4<1>; -L_0x2c91b40 .delay (20000,20000,20000) L_0x2c91b40/d; -L_0x2c91d20/d .functor XOR 1, L_0x2c91410, L_0x2c91770, C4<0>, C4<0>; -L_0x2c91d20 .delay (40000,40000,40000) L_0x2c91d20/d; -L_0x2c91e10/d .functor XOR 1, L_0x2c91d20, L_0x2c926b0, C4<0>, C4<0>; -L_0x2c91e10 .delay (40000,40000,40000) L_0x2c91e10/d; -L_0x2c91f00/d .functor AND 1, L_0x2c91410, L_0x2c91770, C4<1>, C4<1>; -L_0x2c91f00 .delay (20000,20000,20000) L_0x2c91f00/d; -L_0x2c84530/d .functor AND 1, L_0x2c91d20, L_0x2c926b0, C4<1>, C4<1>; -L_0x2c84530 .delay (20000,20000,20000) L_0x2c84530/d; -L_0x2c92090/d .functor OR 1, L_0x2c91f00, L_0x2c84530, C4<0>, C4<0>; -L_0x2c92090 .delay (20000,20000,20000) L_0x2c92090/d; -v0x2b513c0_0 .net "A", 0 0, L_0x2c91410; 1 drivers -v0x2b51480_0 .net "AandB", 0 0, L_0x2c91f00; 1 drivers -v0x2b51520_0 .net "AddSubSLTSum", 0 0, L_0x2c91e10; 1 drivers -v0x2b515c0_0 .net "AxorB", 0 0, L_0x2c91d20; 1 drivers -v0x2b51640_0 .net "B", 0 0, L_0x2c914b0; 1 drivers -v0x2b516f0_0 .net "BornB", 0 0, L_0x2c91770; 1 drivers -v0x2b517b0_0 .net "CINandAxorB", 0 0, L_0x2c84530; 1 drivers -v0x2b51830_0 .alias "Command", 2 0, v0x2bc67a0_0; -v0x2b518b0_0 .net *"_s3", 0 0, L_0x2c91aa0; 1 drivers -v0x2b51930_0 .net *"_s5", 0 0, L_0x2c91c80; 1 drivers -v0x2b519d0_0 .net "carryin", 0 0, L_0x2c926b0; 1 drivers -v0x2b51a70_0 .net "carryout", 0 0, L_0x2c92090; 1 drivers -v0x2b51b10_0 .net "nB", 0 0, L_0x2c90fa0; 1 drivers -v0x2b51bc0_0 .net "nCmd2", 0 0, L_0x2c919e0; 1 drivers -v0x2b51cc0_0 .net "subtract", 0 0, L_0x2c91b40; 1 drivers -L_0x2c91940 .part v0x2bc78e0_0, 0, 1; -L_0x2c91aa0 .part v0x2bc78e0_0, 2, 1; -L_0x2c91c80 .part v0x2bc78e0_0, 0, 1; -S_0x2b50e20 .scope module, "mux0" "TwoInMux" 3 105, 3 8, S_0x2b50d30; - .timescale -9 -12; -L_0x2c91100/d .functor NOT 1, L_0x2c91940, C4<0>, C4<0>, C4<0>; -L_0x2c91100 .delay (10000,10000,10000) L_0x2c91100/d; -L_0x2c91570/d .functor AND 1, L_0x2c914b0, L_0x2c91100, C4<1>, C4<1>; -L_0x2c91570 .delay (20000,20000,20000) L_0x2c91570/d; -L_0x2c91660/d .functor AND 1, L_0x2c90fa0, L_0x2c91940, C4<1>, C4<1>; -L_0x2c91660 .delay (20000,20000,20000) L_0x2c91660/d; -L_0x2c91770/d .functor OR 1, L_0x2c91570, L_0x2c91660, C4<0>, C4<0>; -L_0x2c91770 .delay (20000,20000,20000) L_0x2c91770/d; -v0x2b50f10_0 .net "S", 0 0, L_0x2c91940; 1 drivers -v0x2b50fb0_0 .alias "in0", 0 0, v0x2b51640_0; -v0x2b51050_0 .alias "in1", 0 0, v0x2b51b10_0; -v0x2b510f0_0 .net "nS", 0 0, L_0x2c91100; 1 drivers -v0x2b511a0_0 .net "out0", 0 0, L_0x2c91570; 1 drivers -v0x2b51240_0 .net "out1", 0 0, L_0x2c91660; 1 drivers -v0x2b51320_0 .alias "outfinal", 0 0, v0x2b516f0_0; -S_0x2b4fa20 .scope generate, "addbits[14]" "addbits[14]" 3 230, 3 230, S_0x2851a90; - .timescale -9 -12; -P_0x2b4f438 .param/l "i" 3 230, +C4<01110>; -S_0x2b4fb90 .scope module, "attempt" "MiddleAddSubSLT" 3 232, 3 89, S_0x2b4fa20; - .timescale -9 -12; -L_0x2c923b0/d .functor NOT 1, L_0x2c928e0, C4<0>, C4<0>, C4<0>; -L_0x2c923b0 .delay (10000,10000,10000) L_0x2c923b0/d; -L_0x2c92d80/d .functor NOT 1, L_0x2c92e20, C4<0>, C4<0>, C4<0>; -L_0x2c92d80 .delay (10000,10000,10000) L_0x2c92d80/d; -L_0x2c92ec0/d .functor AND 1, L_0x2c93000, L_0x2c92d80, C4<1>, C4<1>; -L_0x2c92ec0 .delay (20000,20000,20000) L_0x2c92ec0/d; -L_0x2c930a0/d .functor XOR 1, L_0x2c92840, L_0x2c92b50, C4<0>, C4<0>; -L_0x2c930a0 .delay (40000,40000,40000) L_0x2c930a0/d; -L_0x2c93190/d .functor XOR 1, L_0x2c930a0, L_0x2c93b30, C4<0>, C4<0>; -L_0x2c93190 .delay (40000,40000,40000) L_0x2c93190/d; -L_0x2c93280/d .functor AND 1, L_0x2c92840, L_0x2c92b50, C4<1>, C4<1>; -L_0x2c93280 .delay (20000,20000,20000) L_0x2c93280/d; -L_0x2c933f0/d .functor AND 1, L_0x2c930a0, L_0x2c93b30, C4<1>, C4<1>; -L_0x2c933f0 .delay (20000,20000,20000) L_0x2c933f0/d; -L_0x2c934e0/d .functor OR 1, L_0x2c93280, L_0x2c933f0, C4<0>, C4<0>; -L_0x2c934e0 .delay (20000,20000,20000) L_0x2c934e0/d; -v0x2b50220_0 .net "A", 0 0, L_0x2c92840; 1 drivers -v0x2b502e0_0 .net "AandB", 0 0, L_0x2c93280; 1 drivers -v0x2b50380_0 .net "AddSubSLTSum", 0 0, L_0x2c93190; 1 drivers -v0x2b50420_0 .net "AxorB", 0 0, L_0x2c930a0; 1 drivers -v0x2b504a0_0 .net "B", 0 0, L_0x2c928e0; 1 drivers -v0x2b50550_0 .net "BornB", 0 0, L_0x2c92b50; 1 drivers -v0x2b50610_0 .net "CINandAxorB", 0 0, L_0x2c933f0; 1 drivers -v0x2b50690_0 .alias "Command", 2 0, v0x2bc67a0_0; -v0x2b50710_0 .net *"_s3", 0 0, L_0x2c92e20; 1 drivers -v0x2b50790_0 .net *"_s5", 0 0, L_0x2c93000; 1 drivers -v0x2b50830_0 .net "carryin", 0 0, L_0x2c93b30; 1 drivers -v0x2b508d0_0 .net "carryout", 0 0, L_0x2c934e0; 1 drivers -v0x2b50970_0 .net "nB", 0 0, L_0x2c923b0; 1 drivers -v0x2b50a20_0 .net "nCmd2", 0 0, L_0x2c92d80; 1 drivers -v0x2b50b20_0 .net "subtract", 0 0, L_0x2c92ec0; 1 drivers -L_0x2c92ce0 .part v0x2bc78e0_0, 0, 1; -L_0x2c92e20 .part v0x2bc78e0_0, 2, 1; -L_0x2c93000 .part v0x2bc78e0_0, 0, 1; -S_0x2b4fc80 .scope module, "mux0" "TwoInMux" 3 105, 3 8, S_0x2b4fb90; - .timescale -9 -12; -L_0x2c924f0/d .functor NOT 1, L_0x2c92ce0, C4<0>, C4<0>, C4<0>; -L_0x2c924f0 .delay (10000,10000,10000) L_0x2c924f0/d; -L_0x2c925b0/d .functor AND 1, L_0x2c928e0, L_0x2c924f0, C4<1>, C4<1>; -L_0x2c925b0 .delay (20000,20000,20000) L_0x2c925b0/d; -L_0x2c92a60/d .functor AND 1, L_0x2c923b0, L_0x2c92ce0, C4<1>, C4<1>; -L_0x2c92a60 .delay (20000,20000,20000) L_0x2c92a60/d; -L_0x2c92b50/d .functor OR 1, L_0x2c925b0, L_0x2c92a60, C4<0>, C4<0>; -L_0x2c92b50 .delay (20000,20000,20000) L_0x2c92b50/d; -v0x2b4fd70_0 .net "S", 0 0, L_0x2c92ce0; 1 drivers -v0x2b4fe10_0 .alias "in0", 0 0, v0x2b504a0_0; -v0x2b4feb0_0 .alias "in1", 0 0, v0x2b50970_0; -v0x2b4ff50_0 .net "nS", 0 0, L_0x2c924f0; 1 drivers -v0x2b50000_0 .net "out0", 0 0, L_0x2c925b0; 1 drivers -v0x2b500a0_0 .net "out1", 0 0, L_0x2c92a60; 1 drivers -v0x2b50180_0 .alias "outfinal", 0 0, v0x2b50550_0; -S_0x2b4e880 .scope generate, "addbits[15]" "addbits[15]" 3 230, 3 230, S_0x2851a90; - .timescale -9 -12; -P_0x2b4e298 .param/l "i" 3 230, +C4<01111>; -S_0x2b4e9f0 .scope module, "attempt" "MiddleAddSubSLT" 3 232, 3 89, S_0x2b4e880; - .timescale -9 -12; -L_0x2c93800/d .functor NOT 1, L_0x2c93d60, C4<0>, C4<0>, C4<0>; -L_0x2c93800 .delay (10000,10000,10000) L_0x2c93800/d; -L_0x2c941f0/d .functor NOT 1, L_0x2c94290, C4<0>, C4<0>, C4<0>; -L_0x2c941f0 .delay (10000,10000,10000) L_0x2c941f0/d; -L_0x2c94330/d .functor AND 1, L_0x2c94470, L_0x2c941f0, C4<1>, C4<1>; -L_0x2c94330 .delay (20000,20000,20000) L_0x2c94330/d; -L_0x2c94510/d .functor XOR 1, L_0x2c93cc0, L_0x2c93fc0, C4<0>, C4<0>; -L_0x2c94510 .delay (40000,40000,40000) L_0x2c94510/d; -L_0x2c94600/d .functor XOR 1, L_0x2c94510, L_0x2c94fd0, C4<0>, C4<0>; -L_0x2c94600 .delay (40000,40000,40000) L_0x2c94600/d; -L_0x2c946f0/d .functor AND 1, L_0x2c93cc0, L_0x2c93fc0, C4<1>, C4<1>; -L_0x2c946f0 .delay (20000,20000,20000) L_0x2c946f0/d; -L_0x2c94860/d .functor AND 1, L_0x2c94510, L_0x2c94fd0, C4<1>, C4<1>; -L_0x2c94860 .delay (20000,20000,20000) L_0x2c94860/d; -L_0x2c94950/d .functor OR 1, L_0x2c946f0, L_0x2c94860, C4<0>, C4<0>; -L_0x2c94950 .delay (20000,20000,20000) L_0x2c94950/d; -v0x2b4f080_0 .net "A", 0 0, L_0x2c93cc0; 1 drivers -v0x2b4f140_0 .net "AandB", 0 0, L_0x2c946f0; 1 drivers -v0x2b4f1e0_0 .net "AddSubSLTSum", 0 0, L_0x2c94600; 1 drivers -v0x2b4f280_0 .net "AxorB", 0 0, L_0x2c94510; 1 drivers -v0x2b4f300_0 .net "B", 0 0, L_0x2c93d60; 1 drivers -v0x2b4f3b0_0 .net "BornB", 0 0, L_0x2c93fc0; 1 drivers -v0x2b4f470_0 .net "CINandAxorB", 0 0, L_0x2c94860; 1 drivers -v0x2b4f4f0_0 .alias "Command", 2 0, v0x2bc67a0_0; -v0x2b4f570_0 .net *"_s3", 0 0, L_0x2c94290; 1 drivers -v0x2b4f5f0_0 .net *"_s5", 0 0, L_0x2c94470; 1 drivers -v0x2b4f690_0 .net "carryin", 0 0, L_0x2c94fd0; 1 drivers -v0x2b4f730_0 .net "carryout", 0 0, L_0x2c94950; 1 drivers -v0x2b4f7d0_0 .net "nB", 0 0, L_0x2c93800; 1 drivers -v0x2b4f880_0 .net "nCmd2", 0 0, L_0x2c941f0; 1 drivers -v0x2b4f980_0 .net "subtract", 0 0, L_0x2c94330; 1 drivers -L_0x2c94150 .part v0x2bc78e0_0, 0, 1; -L_0x2c94290 .part v0x2bc78e0_0, 2, 1; -L_0x2c94470 .part v0x2bc78e0_0, 0, 1; -S_0x2b4eae0 .scope module, "mux0" "TwoInMux" 3 105, 3 8, S_0x2b4e9f0; - .timescale -9 -12; -L_0x2c93910/d .functor NOT 1, L_0x2c94150, C4<0>, C4<0>, C4<0>; -L_0x2c93910 .delay (10000,10000,10000) L_0x2c93910/d; -L_0x2c939d0/d .functor AND 1, L_0x2c93d60, L_0x2c93910, C4<1>, C4<1>; -L_0x2c939d0 .delay (20000,20000,20000) L_0x2c939d0/d; -L_0x2c93ed0/d .functor AND 1, L_0x2c93800, L_0x2c94150, C4<1>, C4<1>; -L_0x2c93ed0 .delay (20000,20000,20000) L_0x2c93ed0/d; -L_0x2c93fc0/d .functor OR 1, L_0x2c939d0, L_0x2c93ed0, C4<0>, C4<0>; -L_0x2c93fc0 .delay (20000,20000,20000) L_0x2c93fc0/d; -v0x2b4ebd0_0 .net "S", 0 0, L_0x2c94150; 1 drivers -v0x2b4ec70_0 .alias "in0", 0 0, v0x2b4f300_0; -v0x2b4ed10_0 .alias "in1", 0 0, v0x2b4f7d0_0; -v0x2b4edb0_0 .net "nS", 0 0, L_0x2c93910; 1 drivers -v0x2b4ee60_0 .net "out0", 0 0, L_0x2c939d0; 1 drivers -v0x2b4ef00_0 .net "out1", 0 0, L_0x2c93ed0; 1 drivers -v0x2b4efe0_0 .alias "outfinal", 0 0, v0x2b4f3b0_0; -S_0x2b4d6e0 .scope generate, "addbits[16]" "addbits[16]" 3 230, 3 230, S_0x2851a90; - .timescale -9 -12; -P_0x2b4d0f8 .param/l "i" 3 230, +C4<010000>; -S_0x2b4d850 .scope module, "attempt" "MiddleAddSubSLT" 3 232, 3 89, S_0x2b4d6e0; - .timescale -9 -12; -L_0x2c93e00/d .functor NOT 1, L_0x2c95200, C4<0>, C4<0>, C4<0>; -L_0x2c93e00 .delay (10000,10000,10000) L_0x2c93e00/d; -L_0x2c95670/d .functor NOT 1, L_0x2c95710, C4<0>, C4<0>, C4<0>; -L_0x2c95670 .delay (10000,10000,10000) L_0x2c95670/d; -L_0x2c957b0/d .functor AND 1, L_0x2c958f0, L_0x2c95670, C4<1>, C4<1>; -L_0x2c957b0 .delay (20000,20000,20000) L_0x2c957b0/d; -L_0x2c95990/d .functor XOR 1, L_0x2c95160, L_0x2c95440, C4<0>, C4<0>; -L_0x2c95990 .delay (40000,40000,40000) L_0x2c95990/d; -L_0x2c95a80/d .functor XOR 1, L_0x2c95990, L_0x2c963f0, C4<0>, C4<0>; -L_0x2c95a80 .delay (40000,40000,40000) L_0x2c95a80/d; -L_0x2c95b70/d .functor AND 1, L_0x2c95160, L_0x2c95440, C4<1>, C4<1>; -L_0x2c95b70 .delay (20000,20000,20000) L_0x2c95b70/d; -L_0x2c95ce0/d .functor AND 1, L_0x2c95990, L_0x2c963f0, C4<1>, C4<1>; -L_0x2c95ce0 .delay (20000,20000,20000) L_0x2c95ce0/d; -L_0x2c95dd0/d .functor OR 1, L_0x2c95b70, L_0x2c95ce0, C4<0>, C4<0>; -L_0x2c95dd0 .delay (20000,20000,20000) L_0x2c95dd0/d; -v0x2b4dee0_0 .net "A", 0 0, L_0x2c95160; 1 drivers -v0x2b4dfa0_0 .net "AandB", 0 0, L_0x2c95b70; 1 drivers -v0x2b4e040_0 .net "AddSubSLTSum", 0 0, L_0x2c95a80; 1 drivers -v0x2b4e0e0_0 .net "AxorB", 0 0, L_0x2c95990; 1 drivers -v0x2b4e160_0 .net "B", 0 0, L_0x2c95200; 1 drivers -v0x2b4e210_0 .net "BornB", 0 0, L_0x2c95440; 1 drivers -v0x2b4e2d0_0 .net "CINandAxorB", 0 0, L_0x2c95ce0; 1 drivers -v0x2b4e350_0 .alias "Command", 2 0, v0x2bc67a0_0; -v0x2b4e3d0_0 .net *"_s3", 0 0, L_0x2c95710; 1 drivers -v0x2b4e450_0 .net *"_s5", 0 0, L_0x2c958f0; 1 drivers -v0x2b4e4f0_0 .net "carryin", 0 0, L_0x2c963f0; 1 drivers -v0x2b4e590_0 .net "carryout", 0 0, L_0x2c95dd0; 1 drivers -v0x2b4e630_0 .net "nB", 0 0, L_0x2c93e00; 1 drivers -v0x2b4e6e0_0 .net "nCmd2", 0 0, L_0x2c95670; 1 drivers -v0x2b4e7e0_0 .net "subtract", 0 0, L_0x2c957b0; 1 drivers -L_0x2c955d0 .part v0x2bc78e0_0, 0, 1; -L_0x2c95710 .part v0x2bc78e0_0, 2, 1; -L_0x2c958f0 .part v0x2bc78e0_0, 0, 1; -S_0x2b4d940 .scope module, "mux0" "TwoInMux" 3 105, 3 8, S_0x2b4d850; - .timescale -9 -12; -L_0x2c94d50/d .functor NOT 1, L_0x2c955d0, C4<0>, C4<0>, C4<0>; -L_0x2c94d50 .delay (10000,10000,10000) L_0x2c94d50/d; -L_0x2c94e10/d .functor AND 1, L_0x2c95200, L_0x2c94d50, C4<1>, C4<1>; -L_0x2c94e10 .delay (20000,20000,20000) L_0x2c94e10/d; -L_0x2c95350/d .functor AND 1, L_0x2c93e00, L_0x2c955d0, C4<1>, C4<1>; -L_0x2c95350 .delay (20000,20000,20000) L_0x2c95350/d; -L_0x2c95440/d .functor OR 1, L_0x2c94e10, L_0x2c95350, C4<0>, C4<0>; -L_0x2c95440 .delay (20000,20000,20000) L_0x2c95440/d; -v0x2b4da30_0 .net "S", 0 0, L_0x2c955d0; 1 drivers -v0x2b4dad0_0 .alias "in0", 0 0, v0x2b4e160_0; -v0x2b4db70_0 .alias "in1", 0 0, v0x2b4e630_0; -v0x2b4dc10_0 .net "nS", 0 0, L_0x2c94d50; 1 drivers -v0x2b4dcc0_0 .net "out0", 0 0, L_0x2c94e10; 1 drivers -v0x2b4dd60_0 .net "out1", 0 0, L_0x2c95350; 1 drivers -v0x2b4de40_0 .alias "outfinal", 0 0, v0x2b4e210_0; -S_0x2b4c540 .scope generate, "addbits[17]" "addbits[17]" 3 230, 3 230, S_0x2851a90; - .timescale -9 -12; -P_0x2b4bf58 .param/l "i" 3 230, +C4<010001>; -S_0x2b4c6b0 .scope module, "attempt" "MiddleAddSubSLT" 3 232, 3 89, S_0x2b4c540; - .timescale -9 -12; -L_0x2c8be90/d .functor NOT 1, L_0x2c96a30, C4<0>, C4<0>, C4<0>; -L_0x2c8be90 .delay (10000,10000,10000) L_0x2c8be90/d; -L_0x2c96d30/d .functor NOT 1, L_0x2c96dd0, C4<0>, C4<0>, C4<0>; -L_0x2c96d30 .delay (10000,10000,10000) L_0x2c96d30/d; -L_0x2c96e70/d .functor AND 1, L_0x2c96fb0, L_0x2c96d30, C4<1>, C4<1>; -L_0x2c96e70 .delay (20000,20000,20000) L_0x2c96e70/d; -L_0x2c97050/d .functor XOR 1, L_0x2c96990, L_0x2c96310, C4<0>, C4<0>; -L_0x2c97050 .delay (40000,40000,40000) L_0x2c97050/d; -L_0x2c97140/d .functor XOR 1, L_0x2c97050, L_0x2c97ae0, C4<0>, C4<0>; -L_0x2c97140 .delay (40000,40000,40000) L_0x2c97140/d; -L_0x2c97230/d .functor AND 1, L_0x2c96990, L_0x2c96310, C4<1>, C4<1>; -L_0x2c97230 .delay (20000,20000,20000) L_0x2c97230/d; -L_0x2c973a0/d .functor AND 1, L_0x2c97050, L_0x2c97ae0, C4<1>, C4<1>; -L_0x2c973a0 .delay (20000,20000,20000) L_0x2c973a0/d; -L_0x2c97490/d .functor OR 1, L_0x2c97230, L_0x2c973a0, C4<0>, C4<0>; -L_0x2c97490 .delay (20000,20000,20000) L_0x2c97490/d; -v0x2b4cd40_0 .net "A", 0 0, L_0x2c96990; 1 drivers -v0x2b4ce00_0 .net "AandB", 0 0, L_0x2c97230; 1 drivers -v0x2b4cea0_0 .net "AddSubSLTSum", 0 0, L_0x2c97140; 1 drivers -v0x2b4cf40_0 .net "AxorB", 0 0, L_0x2c97050; 1 drivers -v0x2b4cfc0_0 .net "B", 0 0, L_0x2c96a30; 1 drivers -v0x2b4d070_0 .net "BornB", 0 0, L_0x2c96310; 1 drivers -v0x2b4d130_0 .net "CINandAxorB", 0 0, L_0x2c973a0; 1 drivers -v0x2b4d1b0_0 .alias "Command", 2 0, v0x2bc67a0_0; -v0x2b4d230_0 .net *"_s3", 0 0, L_0x2c96dd0; 1 drivers -v0x2b4d2b0_0 .net *"_s5", 0 0, L_0x2c96fb0; 1 drivers -v0x2b4d350_0 .net "carryin", 0 0, L_0x2c97ae0; 1 drivers -v0x2b4d3f0_0 .net "carryout", 0 0, L_0x2c97490; 1 drivers -v0x2b4d490_0 .net "nB", 0 0, L_0x2c8be90; 1 drivers -v0x2b4d540_0 .net "nCmd2", 0 0, L_0x2c96d30; 1 drivers -v0x2b4d640_0 .net "subtract", 0 0, L_0x2c96e70; 1 drivers -L_0x2c96c90 .part v0x2bc78e0_0, 0, 1; -L_0x2c96dd0 .part v0x2bc78e0_0, 2, 1; -L_0x2c96fb0 .part v0x2bc78e0_0, 0, 1; -S_0x2b4c7a0 .scope module, "mux0" "TwoInMux" 3 105, 3 8, S_0x2b4c6b0; - .timescale -9 -12; -L_0x2c8bfd0/d .functor NOT 1, L_0x2c96c90, C4<0>, C4<0>, C4<0>; -L_0x2c8bfd0 .delay (10000,10000,10000) L_0x2c8bfd0/d; -L_0x2c960f0/d .functor AND 1, L_0x2c96a30, L_0x2c8bfd0, C4<1>, C4<1>; -L_0x2c960f0 .delay (20000,20000,20000) L_0x2c960f0/d; -L_0x2c96200/d .functor AND 1, L_0x2c8be90, L_0x2c96c90, C4<1>, C4<1>; -L_0x2c96200 .delay (20000,20000,20000) L_0x2c96200/d; -L_0x2c96310/d .functor OR 1, L_0x2c960f0, L_0x2c96200, C4<0>, C4<0>; -L_0x2c96310 .delay (20000,20000,20000) L_0x2c96310/d; -v0x2b4c890_0 .net "S", 0 0, L_0x2c96c90; 1 drivers -v0x2b4c930_0 .alias "in0", 0 0, v0x2b4cfc0_0; -v0x2b4c9d0_0 .alias "in1", 0 0, v0x2b4d490_0; -v0x2b4ca70_0 .net "nS", 0 0, L_0x2c8bfd0; 1 drivers -v0x2b4cb20_0 .net "out0", 0 0, L_0x2c960f0; 1 drivers -v0x2b4cbc0_0 .net "out1", 0 0, L_0x2c96200; 1 drivers -v0x2b4cca0_0 .alias "outfinal", 0 0, v0x2b4d070_0; -S_0x2b4b3a0 .scope generate, "addbits[18]" "addbits[18]" 3 230, 3 230, S_0x2851a90; - .timescale -9 -12; -P_0x2b4adb8 .param/l "i" 3 230, +C4<010010>; -S_0x2b4b510 .scope module, "attempt" "MiddleAddSubSLT" 3 232, 3 89, S_0x2b4b3a0; - .timescale -9 -12; -L_0x2c977b0/d .functor NOT 1, L_0x2c97d10, C4<0>, C4<0>, C4<0>; -L_0x2c977b0 .delay (10000,10000,10000) L_0x2c977b0/d; -L_0x2c981a0/d .functor NOT 1, L_0x2c98240, C4<0>, C4<0>, C4<0>; -L_0x2c981a0 .delay (10000,10000,10000) L_0x2c981a0/d; -L_0x2c982e0/d .functor AND 1, L_0x2c98420, L_0x2c981a0, C4<1>, C4<1>; -L_0x2c982e0 .delay (20000,20000,20000) L_0x2c982e0/d; -L_0x2c984c0/d .functor XOR 1, L_0x2c97c70, L_0x2c97f70, C4<0>, C4<0>; -L_0x2c984c0 .delay (40000,40000,40000) L_0x2c984c0/d; -L_0x2c985b0/d .functor XOR 1, L_0x2c984c0, L_0x2c98f80, C4<0>, C4<0>; -L_0x2c985b0 .delay (40000,40000,40000) L_0x2c985b0/d; -L_0x2c986a0/d .functor AND 1, L_0x2c97c70, L_0x2c97f70, C4<1>, C4<1>; -L_0x2c986a0 .delay (20000,20000,20000) L_0x2c986a0/d; -L_0x2c98810/d .functor AND 1, L_0x2c984c0, L_0x2c98f80, C4<1>, C4<1>; -L_0x2c98810 .delay (20000,20000,20000) L_0x2c98810/d; -L_0x2c98900/d .functor OR 1, L_0x2c986a0, L_0x2c98810, C4<0>, C4<0>; -L_0x2c98900 .delay (20000,20000,20000) L_0x2c98900/d; -v0x2b4bba0_0 .net "A", 0 0, L_0x2c97c70; 1 drivers -v0x2b4bc60_0 .net "AandB", 0 0, L_0x2c986a0; 1 drivers -v0x2b4bd00_0 .net "AddSubSLTSum", 0 0, L_0x2c985b0; 1 drivers -v0x2b4bda0_0 .net "AxorB", 0 0, L_0x2c984c0; 1 drivers -v0x2b4be20_0 .net "B", 0 0, L_0x2c97d10; 1 drivers -v0x2b4bed0_0 .net "BornB", 0 0, L_0x2c97f70; 1 drivers -v0x2b4bf90_0 .net "CINandAxorB", 0 0, L_0x2c98810; 1 drivers -v0x2b4c010_0 .alias "Command", 2 0, v0x2bc67a0_0; -v0x2b4c090_0 .net *"_s3", 0 0, L_0x2c98240; 1 drivers -v0x2b4c110_0 .net *"_s5", 0 0, L_0x2c98420; 1 drivers -v0x2b4c1b0_0 .net "carryin", 0 0, L_0x2c98f80; 1 drivers -v0x2b4c250_0 .net "carryout", 0 0, L_0x2c98900; 1 drivers -v0x2b4c2f0_0 .net "nB", 0 0, L_0x2c977b0; 1 drivers -v0x2b4c3a0_0 .net "nCmd2", 0 0, L_0x2c981a0; 1 drivers -v0x2b4c4a0_0 .net "subtract", 0 0, L_0x2c982e0; 1 drivers -L_0x2c98100 .part v0x2bc78e0_0, 0, 1; -L_0x2c98240 .part v0x2bc78e0_0, 2, 1; -L_0x2c98420 .part v0x2bc78e0_0, 0, 1; -S_0x2b4b600 .scope module, "mux0" "TwoInMux" 3 105, 3 8, S_0x2b4b510; - .timescale -9 -12; -L_0x2c978c0/d .functor NOT 1, L_0x2c98100, C4<0>, C4<0>, C4<0>; -L_0x2c978c0 .delay (10000,10000,10000) L_0x2c978c0/d; -L_0x2c97980/d .functor AND 1, L_0x2c97d10, L_0x2c978c0, C4<1>, C4<1>; -L_0x2c97980 .delay (20000,20000,20000) L_0x2c97980/d; -L_0x2c97ec0/d .functor AND 1, L_0x2c977b0, L_0x2c98100, C4<1>, C4<1>; -L_0x2c97ec0 .delay (20000,20000,20000) L_0x2c97ec0/d; -L_0x2c97f70/d .functor OR 1, L_0x2c97980, L_0x2c97ec0, C4<0>, C4<0>; -L_0x2c97f70 .delay (20000,20000,20000) L_0x2c97f70/d; -v0x2b4b6f0_0 .net "S", 0 0, L_0x2c98100; 1 drivers -v0x2b4b790_0 .alias "in0", 0 0, v0x2b4be20_0; -v0x2b4b830_0 .alias "in1", 0 0, v0x2b4c2f0_0; -v0x2b4b8d0_0 .net "nS", 0 0, L_0x2c978c0; 1 drivers -v0x2b4b980_0 .net "out0", 0 0, L_0x2c97980; 1 drivers -v0x2b4ba20_0 .net "out1", 0 0, L_0x2c97ec0; 1 drivers -v0x2b4bb00_0 .alias "outfinal", 0 0, v0x2b4bed0_0; -S_0x2b4a200 .scope generate, "addbits[19]" "addbits[19]" 3 230, 3 230, S_0x2851a90; - .timescale -9 -12; -P_0x2b49c18 .param/l "i" 3 230, +C4<010011>; -S_0x2b4a370 .scope module, "attempt" "MiddleAddSubSLT" 3 232, 3 89, S_0x2b4a200; - .timescale -9 -12; -L_0x2c97e40/d .functor NOT 1, L_0x2c991b0, C4<0>, C4<0>, C4<0>; -L_0x2c97e40 .delay (10000,10000,10000) L_0x2c97e40/d; -L_0x2c99650/d .functor NOT 1, L_0x2c996f0, C4<0>, C4<0>, C4<0>; -L_0x2c99650 .delay (10000,10000,10000) L_0x2c99650/d; -L_0x2c99790/d .functor AND 1, L_0x2c998d0, L_0x2c99650, C4<1>, C4<1>; -L_0x2c99790 .delay (20000,20000,20000) L_0x2c99790/d; -L_0x2c99970/d .functor XOR 1, L_0x2c99110, L_0x2c99420, C4<0>, C4<0>; -L_0x2c99970 .delay (40000,40000,40000) L_0x2c99970/d; -L_0x2c99a60/d .functor XOR 1, L_0x2c99970, L_0x2c992e0, C4<0>, C4<0>; -L_0x2c99a60 .delay (40000,40000,40000) L_0x2c99a60/d; -L_0x2c99b50/d .functor AND 1, L_0x2c99110, L_0x2c99420, C4<1>, C4<1>; -L_0x2c99b50 .delay (20000,20000,20000) L_0x2c99b50/d; -L_0x2c99cc0/d .functor AND 1, L_0x2c99970, L_0x2c992e0, C4<1>, C4<1>; -L_0x2c99cc0 .delay (20000,20000,20000) L_0x2c99cc0/d; -L_0x2c99db0/d .functor OR 1, L_0x2c99b50, L_0x2c99cc0, C4<0>, C4<0>; -L_0x2c99db0 .delay (20000,20000,20000) L_0x2c99db0/d; -v0x2b4aa00_0 .net "A", 0 0, L_0x2c99110; 1 drivers -v0x2b4aac0_0 .net "AandB", 0 0, L_0x2c99b50; 1 drivers -v0x2b4ab60_0 .net "AddSubSLTSum", 0 0, L_0x2c99a60; 1 drivers -v0x2b4ac00_0 .net "AxorB", 0 0, L_0x2c99970; 1 drivers -v0x2b4ac80_0 .net "B", 0 0, L_0x2c991b0; 1 drivers -v0x2b4ad30_0 .net "BornB", 0 0, L_0x2c99420; 1 drivers -v0x2b4adf0_0 .net "CINandAxorB", 0 0, L_0x2c99cc0; 1 drivers -v0x2b4ae70_0 .alias "Command", 2 0, v0x2bc67a0_0; -v0x2b4aef0_0 .net *"_s3", 0 0, L_0x2c996f0; 1 drivers -v0x2b4af70_0 .net *"_s5", 0 0, L_0x2c998d0; 1 drivers -v0x2b4b010_0 .net "carryin", 0 0, L_0x2c992e0; 1 drivers -v0x2b4b0b0_0 .net "carryout", 0 0, L_0x2c99db0; 1 drivers -v0x2b4b150_0 .net "nB", 0 0, L_0x2c97e40; 1 drivers -v0x2b4b200_0 .net "nCmd2", 0 0, L_0x2c99650; 1 drivers -v0x2b4b300_0 .net "subtract", 0 0, L_0x2c99790; 1 drivers -L_0x2c995b0 .part v0x2bc78e0_0, 0, 1; -L_0x2c996f0 .part v0x2bc78e0_0, 2, 1; -L_0x2c998d0 .part v0x2bc78e0_0, 0, 1; -S_0x2b4a460 .scope module, "mux0" "TwoInMux" 3 105, 3 8, S_0x2b4a370; - .timescale -9 -12; -L_0x2c98d00/d .functor NOT 1, L_0x2c995b0, C4<0>, C4<0>, C4<0>; -L_0x2c98d00 .delay (10000,10000,10000) L_0x2c98d00/d; -L_0x2c98dc0/d .functor AND 1, L_0x2c991b0, L_0x2c98d00, C4<1>, C4<1>; -L_0x2c98dc0 .delay (20000,20000,20000) L_0x2c98dc0/d; -L_0x2c98ed0/d .functor AND 1, L_0x2c97e40, L_0x2c995b0, C4<1>, C4<1>; -L_0x2c98ed0 .delay (20000,20000,20000) L_0x2c98ed0/d; -L_0x2c99420/d .functor OR 1, L_0x2c98dc0, L_0x2c98ed0, C4<0>, C4<0>; -L_0x2c99420 .delay (20000,20000,20000) L_0x2c99420/d; -v0x2b4a550_0 .net "S", 0 0, L_0x2c995b0; 1 drivers -v0x2b4a5f0_0 .alias "in0", 0 0, v0x2b4ac80_0; -v0x2b4a690_0 .alias "in1", 0 0, v0x2b4b150_0; -v0x2b4a730_0 .net "nS", 0 0, L_0x2c98d00; 1 drivers -v0x2b4a7e0_0 .net "out0", 0 0, L_0x2c98dc0; 1 drivers -v0x2b4a880_0 .net "out1", 0 0, L_0x2c98ed0; 1 drivers -v0x2b4a960_0 .alias "outfinal", 0 0, v0x2b4ad30_0; -S_0x2b49060 .scope generate, "addbits[20]" "addbits[20]" 3 230, 3 230, S_0x2851a90; - .timescale -9 -12; -P_0x2b48a78 .param/l "i" 3 230, +C4<010100>; -S_0x2b491d0 .scope module, "attempt" "MiddleAddSubSLT" 3 232, 3 89, S_0x2b49060; - .timescale -9 -12; -L_0x2c9a470/d .functor NOT 1, L_0x2c9a260, C4<0>, C4<0>, C4<0>; -L_0x2c9a470 .delay (10000,10000,10000) L_0x2c9a470/d; -L_0x2c9aa60/d .functor NOT 1, L_0x2c9ab20, C4<0>, C4<0>, C4<0>; -L_0x2c9aa60 .delay (10000,10000,10000) L_0x2c9aa60/d; -L_0x2c9abc0/d .functor AND 1, L_0x2c9ad00, L_0x2c9aa60, C4<1>, C4<1>; -L_0x2c9abc0 .delay (20000,20000,20000) L_0x2c9abc0/d; -L_0x2c9ada0/d .functor XOR 1, L_0x2c9a1c0, L_0x2c9a7f0, C4<0>, C4<0>; -L_0x2c9ada0 .delay (40000,40000,40000) L_0x2c9ada0/d; -L_0x2c9ae90/d .functor XOR 1, L_0x2c9ada0, L_0x2c9a390, C4<0>, C4<0>; -L_0x2c9ae90 .delay (40000,40000,40000) L_0x2c9ae90/d; -L_0x2c9af80/d .functor AND 1, L_0x2c9a1c0, L_0x2c9a7f0, C4<1>, C4<1>; -L_0x2c9af80 .delay (20000,20000,20000) L_0x2c9af80/d; -L_0x2c9b0f0/d .functor AND 1, L_0x2c9ada0, L_0x2c9a390, C4<1>, C4<1>; -L_0x2c9b0f0 .delay (20000,20000,20000) L_0x2c9b0f0/d; -L_0x2c9b200/d .functor OR 1, L_0x2c9af80, L_0x2c9b0f0, C4<0>, C4<0>; -L_0x2c9b200 .delay (20000,20000,20000) L_0x2c9b200/d; -v0x2b49860_0 .net "A", 0 0, L_0x2c9a1c0; 1 drivers -v0x2b49920_0 .net "AandB", 0 0, L_0x2c9af80; 1 drivers -v0x2b499c0_0 .net "AddSubSLTSum", 0 0, L_0x2c9ae90; 1 drivers -v0x2b49a60_0 .net "AxorB", 0 0, L_0x2c9ada0; 1 drivers -v0x2b49ae0_0 .net "B", 0 0, L_0x2c9a260; 1 drivers -v0x2b49b90_0 .net "BornB", 0 0, L_0x2c9a7f0; 1 drivers -v0x2b49c50_0 .net "CINandAxorB", 0 0, L_0x2c9b0f0; 1 drivers -v0x2b49cd0_0 .alias "Command", 2 0, v0x2bc67a0_0; -v0x2b49d50_0 .net *"_s3", 0 0, L_0x2c9ab20; 1 drivers -v0x2b49dd0_0 .net *"_s5", 0 0, L_0x2c9ad00; 1 drivers -v0x2b49e70_0 .net "carryin", 0 0, L_0x2c9a390; 1 drivers -v0x2b49f10_0 .net "carryout", 0 0, L_0x2c9b200; 1 drivers -v0x2b49fb0_0 .net "nB", 0 0, L_0x2c9a470; 1 drivers -v0x2b4a060_0 .net "nCmd2", 0 0, L_0x2c9aa60; 1 drivers -v0x2b4a160_0 .net "subtract", 0 0, L_0x2c9abc0; 1 drivers -L_0x2c9a9c0 .part v0x2bc78e0_0, 0, 1; -L_0x2c9ab20 .part v0x2bc78e0_0, 2, 1; -L_0x2c9ad00 .part v0x2bc78e0_0, 0, 1; -S_0x2b492c0 .scope module, "mux0" "TwoInMux" 3 105, 3 8, S_0x2b491d0; - .timescale -9 -12; -L_0x2c9a570/d .functor NOT 1, L_0x2c9a9c0, C4<0>, C4<0>, C4<0>; -L_0x2c9a570 .delay (10000,10000,10000) L_0x2c9a570/d; -L_0x2c9a610/d .functor AND 1, L_0x2c9a260, L_0x2c9a570, C4<1>, C4<1>; -L_0x2c9a610 .delay (20000,20000,20000) L_0x2c9a610/d; -L_0x2c9a700/d .functor AND 1, L_0x2c9a470, L_0x2c9a9c0, C4<1>, C4<1>; -L_0x2c9a700 .delay (20000,20000,20000) L_0x2c9a700/d; -L_0x2c9a7f0/d .functor OR 1, L_0x2c9a610, L_0x2c9a700, C4<0>, C4<0>; -L_0x2c9a7f0 .delay (20000,20000,20000) L_0x2c9a7f0/d; -v0x2b493b0_0 .net "S", 0 0, L_0x2c9a9c0; 1 drivers -v0x2b49450_0 .alias "in0", 0 0, v0x2b49ae0_0; -v0x2b494f0_0 .alias "in1", 0 0, v0x2b49fb0_0; -v0x2b49590_0 .net "nS", 0 0, L_0x2c9a570; 1 drivers -v0x2b49640_0 .net "out0", 0 0, L_0x2c9a610; 1 drivers -v0x2b496e0_0 .net "out1", 0 0, L_0x2c9a700; 1 drivers -v0x2b497c0_0 .alias "outfinal", 0 0, v0x2b49b90_0; -S_0x2b47ef0 .scope generate, "addbits[21]" "addbits[21]" 3 230, 3 230, S_0x2851a90; - .timescale -9 -12; -P_0x2b477d8 .param/l "i" 3 230, +C4<010101>; -S_0x2b48060 .scope module, "attempt" "MiddleAddSubSLT" 3 232, 3 89, S_0x2b47ef0; - .timescale -9 -12; -L_0x2c9b910/d .functor NOT 1, L_0x2c9b6d0, C4<0>, C4<0>, C4<0>; -L_0x2c9b910 .delay (10000,10000,10000) L_0x2c9b910/d; -L_0x2c9bf80/d .functor NOT 1, L_0x2c9c040, C4<0>, C4<0>, C4<0>; -L_0x2c9bf80 .delay (10000,10000,10000) L_0x2c9bf80/d; -L_0x2c9c0e0/d .functor AND 1, L_0x2c9c220, L_0x2c9bf80, C4<1>, C4<1>; -L_0x2c9c0e0 .delay (20000,20000,20000) L_0x2c9c0e0/d; -L_0x2c9c2c0/d .functor XOR 1, L_0x2c9b630, L_0x2c9bd10, C4<0>, C4<0>; -L_0x2c9c2c0 .delay (40000,40000,40000) L_0x2c9c2c0/d; -L_0x2c9c3b0/d .functor XOR 1, L_0x2c9c2c0, L_0x2c9b800, C4<0>, C4<0>; -L_0x2c9c3b0 .delay (40000,40000,40000) L_0x2c9c3b0/d; -L_0x2c9c4a0/d .functor AND 1, L_0x2c9b630, L_0x2c9bd10, C4<1>, C4<1>; -L_0x2c9c4a0 .delay (20000,20000,20000) L_0x2c9c4a0/d; -L_0x2c9c610/d .functor AND 1, L_0x2c9c2c0, L_0x2c9b800, C4<1>, C4<1>; -L_0x2c9c610 .delay (20000,20000,20000) L_0x2c9c610/d; -L_0x2c9c700/d .functor OR 1, L_0x2c9c4a0, L_0x2c9c610, C4<0>, C4<0>; -L_0x2c9c700 .delay (20000,20000,20000) L_0x2c9c700/d; -v0x2b486c0_0 .net "A", 0 0, L_0x2c9b630; 1 drivers -v0x2b48780_0 .net "AandB", 0 0, L_0x2c9c4a0; 1 drivers -v0x2b48820_0 .net "AddSubSLTSum", 0 0, L_0x2c9c3b0; 1 drivers -v0x2b488c0_0 .net "AxorB", 0 0, L_0x2c9c2c0; 1 drivers -v0x2b48940_0 .net "B", 0 0, L_0x2c9b6d0; 1 drivers -v0x2b489f0_0 .net "BornB", 0 0, L_0x2c9bd10; 1 drivers -v0x2b48ab0_0 .net "CINandAxorB", 0 0, L_0x2c9c610; 1 drivers -v0x2b48b30_0 .alias "Command", 2 0, v0x2bc67a0_0; -v0x2b48bb0_0 .net *"_s3", 0 0, L_0x2c9c040; 1 drivers -v0x2b48c30_0 .net *"_s5", 0 0, L_0x2c9c220; 1 drivers -v0x2b48cd0_0 .net "carryin", 0 0, L_0x2c9b800; 1 drivers -v0x2b48d70_0 .net "carryout", 0 0, L_0x2c9c700; 1 drivers -v0x2b48e10_0 .net "nB", 0 0, L_0x2c9b910; 1 drivers -v0x2b48ec0_0 .net "nCmd2", 0 0, L_0x2c9bf80; 1 drivers -v0x2b48fc0_0 .net "subtract", 0 0, L_0x2c9c0e0; 1 drivers -L_0x2c9bee0 .part v0x2bc78e0_0, 0, 1; -L_0x2c9c040 .part v0x2bc78e0_0, 2, 1; -L_0x2c9c220 .part v0x2bc78e0_0, 0, 1; -S_0x2b48150 .scope module, "mux0" "TwoInMux" 3 105, 3 8, S_0x2b48060; - .timescale -9 -12; -L_0x2c9ba30/d .functor NOT 1, L_0x2c9bee0, C4<0>, C4<0>, C4<0>; -L_0x2c9ba30 .delay (10000,10000,10000) L_0x2c9ba30/d; -L_0x2c9baf0/d .functor AND 1, L_0x2c9b6d0, L_0x2c9ba30, C4<1>, C4<1>; -L_0x2c9baf0 .delay (20000,20000,20000) L_0x2c9baf0/d; -L_0x2c9bc00/d .functor AND 1, L_0x2c9b910, L_0x2c9bee0, C4<1>, C4<1>; -L_0x2c9bc00 .delay (20000,20000,20000) L_0x2c9bc00/d; -L_0x2c9bd10/d .functor OR 1, L_0x2c9baf0, L_0x2c9bc00, C4<0>, C4<0>; -L_0x2c9bd10 .delay (20000,20000,20000) L_0x2c9bd10/d; -v0x2b48240_0 .net "S", 0 0, L_0x2c9bee0; 1 drivers -v0x2b482e0_0 .alias "in0", 0 0, v0x2b48940_0; -v0x2b48380_0 .alias "in1", 0 0, v0x2b48e10_0; -v0x2b48420_0 .net "nS", 0 0, L_0x2c9ba30; 1 drivers -v0x2b484a0_0 .net "out0", 0 0, L_0x2c9baf0; 1 drivers -v0x2b48540_0 .net "out1", 0 0, L_0x2c9bc00; 1 drivers -v0x2b48620_0 .alias "outfinal", 0 0, v0x2b489f0_0; -S_0x2b46d20 .scope generate, "addbits[22]" "addbits[22]" 3 230, 3 230, S_0x2851a90; - .timescale -9 -12; -P_0x2b46738 .param/l "i" 3 230, +C4<010110>; -S_0x2b46e90 .scope module, "attempt" "MiddleAddSubSLT" 3 232, 3 89, S_0x2b46d20; - .timescale -9 -12; -L_0x2c9b8a0/d .functor NOT 1, L_0x2c9cbd0, C4<0>, C4<0>, C4<0>; -L_0x2c9b8a0 .delay (10000,10000,10000) L_0x2c9b8a0/d; -L_0x2c9d490/d .functor NOT 1, L_0x2c9d550, C4<0>, C4<0>, C4<0>; -L_0x2c9d490 .delay (10000,10000,10000) L_0x2c9d490/d; -L_0x2c9d5f0/d .functor AND 1, L_0x2c9d730, L_0x2c9d490, C4<1>, C4<1>; -L_0x2c9d5f0 .delay (20000,20000,20000) L_0x2c9d5f0/d; -L_0x2c9d7d0/d .functor XOR 1, L_0x2c9cb30, L_0x2c9d220, C4<0>, C4<0>; -L_0x2c9d7d0 .delay (40000,40000,40000) L_0x2c9d7d0/d; -L_0x2c9d8c0/d .functor XOR 1, L_0x2c9d7d0, L_0x2c9cd00, C4<0>, C4<0>; -L_0x2c9d8c0 .delay (40000,40000,40000) L_0x2c9d8c0/d; -L_0x2c9d9b0/d .functor AND 1, L_0x2c9cb30, L_0x2c9d220, C4<1>, C4<1>; -L_0x2c9d9b0 .delay (20000,20000,20000) L_0x2c9d9b0/d; -L_0x2c9db20/d .functor AND 1, L_0x2c9d7d0, L_0x2c9cd00, C4<1>, C4<1>; -L_0x2c9db20 .delay (20000,20000,20000) L_0x2c9db20/d; -L_0x2c9dc10/d .functor OR 1, L_0x2c9d9b0, L_0x2c9db20, C4<0>, C4<0>; -L_0x2c9dc10 .delay (20000,20000,20000) L_0x2c9dc10/d; -v0x2b473f0_0 .net "A", 0 0, L_0x2c9cb30; 1 drivers -v0x2b474b0_0 .net "AandB", 0 0, L_0x2c9d9b0; 1 drivers -v0x2b47550_0 .net "AddSubSLTSum", 0 0, L_0x2c9d8c0; 1 drivers -v0x2b475f0_0 .net "AxorB", 0 0, L_0x2c9d7d0; 1 drivers -v0x2b476a0_0 .net "B", 0 0, L_0x2c9cbd0; 1 drivers -v0x2b47750_0 .net "BornB", 0 0, L_0x2c9d220; 1 drivers -v0x2b47810_0 .net "CINandAxorB", 0 0, L_0x2c9db20; 1 drivers -v0x2b478b0_0 .alias "Command", 2 0, v0x2bc67a0_0; -v0x2b47980_0 .net *"_s3", 0 0, L_0x2c9d550; 1 drivers -v0x2b47a20_0 .net *"_s5", 0 0, L_0x2c9d730; 1 drivers -v0x2b47b20_0 .net "carryin", 0 0, L_0x2c9cd00; 1 drivers -v0x2b47bc0_0 .net "carryout", 0 0, L_0x2c9dc10; 1 drivers -v0x2b47cd0_0 .net "nB", 0 0, L_0x2c9b8a0; 1 drivers -v0x2b47d50_0 .net "nCmd2", 0 0, L_0x2c9d490; 1 drivers -v0x2b47e50_0 .net "subtract", 0 0, L_0x2c9d5f0; 1 drivers -L_0x2c9d3f0 .part v0x2bc78e0_0, 0, 1; -L_0x2c9d550 .part v0x2bc78e0_0, 2, 1; -L_0x2c9d730 .part v0x2bc78e0_0, 0, 1; -S_0x2b46f80 .scope module, "mux0" "TwoInMux" 3 105, 3 8, S_0x2b46e90; - .timescale -9 -12; -L_0x2c9cf40/d .functor NOT 1, L_0x2c9d3f0, C4<0>, C4<0>, C4<0>; -L_0x2c9cf40 .delay (10000,10000,10000) L_0x2c9cf40/d; -L_0x2c9d000/d .functor AND 1, L_0x2c9cbd0, L_0x2c9cf40, C4<1>, C4<1>; -L_0x2c9d000 .delay (20000,20000,20000) L_0x2c9d000/d; -L_0x2c9d110/d .functor AND 1, L_0x2c9b8a0, L_0x2c9d3f0, C4<1>, C4<1>; -L_0x2c9d110 .delay (20000,20000,20000) L_0x2c9d110/d; -L_0x2c9d220/d .functor OR 1, L_0x2c9d000, L_0x2c9d110, C4<0>, C4<0>; -L_0x2c9d220 .delay (20000,20000,20000) L_0x2c9d220/d; -v0x2b47070_0 .net "S", 0 0, L_0x2c9d3f0; 1 drivers -v0x2b470f0_0 .alias "in0", 0 0, v0x2b476a0_0; -v0x2b47170_0 .alias "in1", 0 0, v0x2b47cd0_0; -v0x2b471f0_0 .net "nS", 0 0, L_0x2c9cf40; 1 drivers -v0x2b47270_0 .net "out0", 0 0, L_0x2c9d000; 1 drivers -v0x2b472f0_0 .net "out1", 0 0, L_0x2c9d110; 1 drivers -v0x2b47370_0 .alias "outfinal", 0 0, v0x2b47750_0; -S_0x2b45b80 .scope generate, "addbits[23]" "addbits[23]" 3 230, 3 230, S_0x2851a90; - .timescale -9 -12; -P_0x2b45598 .param/l "i" 3 230, +C4<010111>; -S_0x2b45cf0 .scope module, "attempt" "MiddleAddSubSLT" 3 232, 3 89, S_0x2b45b80; - .timescale -9 -12; -L_0x2c9cda0/d .functor NOT 1, L_0x2c9e0e0, C4<0>, C4<0>, C4<0>; -L_0x2c9cda0 .delay (10000,10000,10000) L_0x2c9cda0/d; -L_0x2c9e890/d .functor NOT 1, L_0x2c9e930, C4<0>, C4<0>, C4<0>; -L_0x2c9e890 .delay (10000,10000,10000) L_0x2c9e890/d; -L_0x2c9e9d0/d .functor AND 1, L_0x2c9eb10, L_0x2c9e890, C4<1>, C4<1>; -L_0x2c9e9d0 .delay (20000,20000,20000) L_0x2c9e9d0/d; -L_0x2c9ebb0/d .functor XOR 1, L_0x2c9e040, L_0x2c9e660, C4<0>, C4<0>; -L_0x2c9ebb0 .delay (40000,40000,40000) L_0x2c9ebb0/d; -L_0x2c9eca0/d .functor XOR 1, L_0x2c9ebb0, L_0x2c9e210, C4<0>, C4<0>; -L_0x2c9eca0 .delay (40000,40000,40000) L_0x2c9eca0/d; -L_0x2c9ed90/d .functor AND 1, L_0x2c9e040, L_0x2c9e660, C4<1>, C4<1>; -L_0x2c9ed90 .delay (20000,20000,20000) L_0x2c9ed90/d; -L_0x2c9ef00/d .functor AND 1, L_0x2c9ebb0, L_0x2c9e210, C4<1>, C4<1>; -L_0x2c9ef00 .delay (20000,20000,20000) L_0x2c9ef00/d; -L_0x2c9eff0/d .functor OR 1, L_0x2c9ed90, L_0x2c9ef00, C4<0>, C4<0>; -L_0x2c9eff0 .delay (20000,20000,20000) L_0x2c9eff0/d; -v0x2b46380_0 .net "A", 0 0, L_0x2c9e040; 1 drivers -v0x2b46440_0 .net "AandB", 0 0, L_0x2c9ed90; 1 drivers -v0x2b464e0_0 .net "AddSubSLTSum", 0 0, L_0x2c9eca0; 1 drivers -v0x2b46580_0 .net "AxorB", 0 0, L_0x2c9ebb0; 1 drivers -v0x2b46600_0 .net "B", 0 0, L_0x2c9e0e0; 1 drivers -v0x2b466b0_0 .net "BornB", 0 0, L_0x2c9e660; 1 drivers -v0x2b46770_0 .net "CINandAxorB", 0 0, L_0x2c9ef00; 1 drivers -v0x2b467f0_0 .alias "Command", 2 0, v0x2bc67a0_0; -v0x2b46870_0 .net *"_s3", 0 0, L_0x2c9e930; 1 drivers -v0x2b468f0_0 .net *"_s5", 0 0, L_0x2c9eb10; 1 drivers -v0x2b46990_0 .net "carryin", 0 0, L_0x2c9e210; 1 drivers -v0x2b46a30_0 .net "carryout", 0 0, L_0x2c9eff0; 1 drivers -v0x2b46ad0_0 .net "nB", 0 0, L_0x2c9cda0; 1 drivers -v0x2b46b80_0 .net "nCmd2", 0 0, L_0x2c9e890; 1 drivers -v0x2b46c80_0 .net "subtract", 0 0, L_0x2c9e9d0; 1 drivers -L_0x2c9e7f0 .part v0x2bc78e0_0, 0, 1; -L_0x2c9e930 .part v0x2bc78e0_0, 2, 1; -L_0x2c9eb10 .part v0x2bc78e0_0, 0, 1; -S_0x2b45de0 .scope module, "mux0" "TwoInMux" 3 105, 3 8, S_0x2b45cf0; - .timescale -9 -12; -L_0x2c9e420/d .functor NOT 1, L_0x2c9e7f0, C4<0>, C4<0>, C4<0>; -L_0x2c9e420 .delay (10000,10000,10000) L_0x2c9e420/d; -L_0x2c9e480/d .functor AND 1, L_0x2c9e0e0, L_0x2c9e420, C4<1>, C4<1>; -L_0x2c9e480 .delay (20000,20000,20000) L_0x2c9e480/d; -L_0x2c9e570/d .functor AND 1, L_0x2c9cda0, L_0x2c9e7f0, C4<1>, C4<1>; -L_0x2c9e570 .delay (20000,20000,20000) L_0x2c9e570/d; -L_0x2c9e660/d .functor OR 1, L_0x2c9e480, L_0x2c9e570, C4<0>, C4<0>; -L_0x2c9e660 .delay (20000,20000,20000) L_0x2c9e660/d; -v0x2b45ed0_0 .net "S", 0 0, L_0x2c9e7f0; 1 drivers -v0x2b45f70_0 .alias "in0", 0 0, v0x2b46600_0; -v0x2b46010_0 .alias "in1", 0 0, v0x2b46ad0_0; -v0x2b460b0_0 .net "nS", 0 0, L_0x2c9e420; 1 drivers -v0x2b46160_0 .net "out0", 0 0, L_0x2c9e480; 1 drivers -v0x2b46200_0 .net "out1", 0 0, L_0x2c9e570; 1 drivers -v0x2b462e0_0 .alias "outfinal", 0 0, v0x2b466b0_0; -S_0x2b449e0 .scope generate, "addbits[24]" "addbits[24]" 3 230, 3 230, S_0x2851a90; - .timescale -9 -12; -P_0x2b443f8 .param/l "i" 3 230, +C4<011000>; -S_0x2b44b50 .scope module, "attempt" "MiddleAddSubSLT" 3 232, 3 89, S_0x2b449e0; - .timescale -9 -12; -L_0x2c9e2b0/d .functor NOT 1, L_0x2c9f4a0, C4<0>, C4<0>, C4<0>; -L_0x2c9e2b0 .delay (10000,10000,10000) L_0x2c9e2b0/d; -L_0x2c9fc70/d .functor NOT 1, L_0x2c9fd10, C4<0>, C4<0>, C4<0>; -L_0x2c9fc70 .delay (10000,10000,10000) L_0x2c9fc70/d; -L_0x2c9fdb0/d .functor AND 1, L_0x2c9fef0, L_0x2c9fc70, C4<1>, C4<1>; -L_0x2c9fdb0 .delay (20000,20000,20000) L_0x2c9fdb0/d; -L_0x2c9ff90/d .functor XOR 1, L_0x2c9f400, L_0x2c9fa40, C4<0>, C4<0>; -L_0x2c9ff90 .delay (40000,40000,40000) L_0x2c9ff90/d; -L_0x2ca0080/d .functor XOR 1, L_0x2c9ff90, L_0x2c9f5d0, C4<0>, C4<0>; -L_0x2ca0080 .delay (40000,40000,40000) L_0x2ca0080/d; -L_0x2ca01a0/d .functor AND 1, L_0x2c9f400, L_0x2c9fa40, C4<1>, C4<1>; -L_0x2ca01a0 .delay (20000,20000,20000) L_0x2ca01a0/d; -L_0x2ca0340/d .functor AND 1, L_0x2c9ff90, L_0x2c9f5d0, C4<1>, C4<1>; -L_0x2ca0340 .delay (20000,20000,20000) L_0x2ca0340/d; -L_0x2ca0450/d .functor OR 1, L_0x2ca01a0, L_0x2ca0340, C4<0>, C4<0>; -L_0x2ca0450 .delay (20000,20000,20000) L_0x2ca0450/d; -v0x2b451e0_0 .net "A", 0 0, L_0x2c9f400; 1 drivers -v0x2b452a0_0 .net "AandB", 0 0, L_0x2ca01a0; 1 drivers -v0x2b45340_0 .net "AddSubSLTSum", 0 0, L_0x2ca0080; 1 drivers -v0x2b453e0_0 .net "AxorB", 0 0, L_0x2c9ff90; 1 drivers -v0x2b45460_0 .net "B", 0 0, L_0x2c9f4a0; 1 drivers -v0x2b45510_0 .net "BornB", 0 0, L_0x2c9fa40; 1 drivers -v0x2b455d0_0 .net "CINandAxorB", 0 0, L_0x2ca0340; 1 drivers -v0x2b45650_0 .alias "Command", 2 0, v0x2bc67a0_0; -v0x2b456d0_0 .net *"_s3", 0 0, L_0x2c9fd10; 1 drivers -v0x2b45750_0 .net *"_s5", 0 0, L_0x2c9fef0; 1 drivers -v0x2b457f0_0 .net "carryin", 0 0, L_0x2c9f5d0; 1 drivers -v0x2b45890_0 .net "carryout", 0 0, L_0x2ca0450; 1 drivers -v0x2b45930_0 .net "nB", 0 0, L_0x2c9e2b0; 1 drivers -v0x2b459e0_0 .net "nCmd2", 0 0, L_0x2c9fc70; 1 drivers -v0x2b45ae0_0 .net "subtract", 0 0, L_0x2c9fdb0; 1 drivers -L_0x2c9fbd0 .part v0x2bc78e0_0, 0, 1; -L_0x2c9fd10 .part v0x2bc78e0_0, 2, 1; -L_0x2c9fef0 .part v0x2bc78e0_0, 0, 1; -S_0x2b44c40 .scope module, "mux0" "TwoInMux" 3 105, 3 8, S_0x2b44b50; - .timescale -9 -12; -L_0x2c9f7c0/d .functor NOT 1, L_0x2c9fbd0, C4<0>, C4<0>, C4<0>; -L_0x2c9f7c0 .delay (10000,10000,10000) L_0x2c9f7c0/d; -L_0x2c9f860/d .functor AND 1, L_0x2c9f4a0, L_0x2c9f7c0, C4<1>, C4<1>; -L_0x2c9f860 .delay (20000,20000,20000) L_0x2c9f860/d; -L_0x2c9f950/d .functor AND 1, L_0x2c9e2b0, L_0x2c9fbd0, C4<1>, C4<1>; -L_0x2c9f950 .delay (20000,20000,20000) L_0x2c9f950/d; -L_0x2c9fa40/d .functor OR 1, L_0x2c9f860, L_0x2c9f950, C4<0>, C4<0>; -L_0x2c9fa40 .delay (20000,20000,20000) L_0x2c9fa40/d; -v0x2b44d30_0 .net "S", 0 0, L_0x2c9fbd0; 1 drivers -v0x2b44dd0_0 .alias "in0", 0 0, v0x2b45460_0; -v0x2b44e70_0 .alias "in1", 0 0, v0x2b45930_0; -v0x2b44f10_0 .net "nS", 0 0, L_0x2c9f7c0; 1 drivers -v0x2b44fc0_0 .net "out0", 0 0, L_0x2c9f860; 1 drivers -v0x2b45060_0 .net "out1", 0 0, L_0x2c9f950; 1 drivers -v0x2b45140_0 .alias "outfinal", 0 0, v0x2b45510_0; -S_0x2b43840 .scope generate, "addbits[25]" "addbits[25]" 3 230, 3 230, S_0x2851a90; - .timescale -9 -12; -P_0x2b43258 .param/l "i" 3 230, +C4<011001>; -S_0x2b439b0 .scope module, "attempt" "MiddleAddSubSLT" 3 232, 3 89, S_0x2b43840; - .timescale -9 -12; -L_0x2c9f670/d .functor NOT 1, L_0x2ca0920, C4<0>, C4<0>, C4<0>; -L_0x2c9f670 .delay (10000,10000,10000) L_0x2c9f670/d; -L_0x2ca1140/d .functor NOT 1, L_0x2ca1200, C4<0>, C4<0>, C4<0>; -L_0x2ca1140 .delay (10000,10000,10000) L_0x2ca1140/d; -L_0x2ca12a0/d .functor AND 1, L_0x2ca13e0, L_0x2ca1140, C4<1>, C4<1>; -L_0x2ca12a0 .delay (20000,20000,20000) L_0x2ca12a0/d; -L_0x2ca1480/d .functor XOR 1, L_0x2ca0880, L_0x2ca0ef0, C4<0>, C4<0>; -L_0x2ca1480 .delay (40000,40000,40000) L_0x2ca1480/d; -L_0x2ca1570/d .functor XOR 1, L_0x2ca1480, L_0x2ca0a50, C4<0>, C4<0>; -L_0x2ca1570 .delay (40000,40000,40000) L_0x2ca1570/d; -L_0x2ca1690/d .functor AND 1, L_0x2ca0880, L_0x2ca0ef0, C4<1>, C4<1>; -L_0x2ca1690 .delay (20000,20000,20000) L_0x2ca1690/d; -L_0x2ca1830/d .functor AND 1, L_0x2ca1480, L_0x2ca0a50, C4<1>, C4<1>; -L_0x2ca1830 .delay (20000,20000,20000) L_0x2ca1830/d; -L_0x2ca1940/d .functor OR 1, L_0x2ca1690, L_0x2ca1830, C4<0>, C4<0>; -L_0x2ca1940 .delay (20000,20000,20000) L_0x2ca1940/d; -v0x2b44040_0 .net "A", 0 0, L_0x2ca0880; 1 drivers -v0x2b44100_0 .net "AandB", 0 0, L_0x2ca1690; 1 drivers -v0x2b441a0_0 .net "AddSubSLTSum", 0 0, L_0x2ca1570; 1 drivers -v0x2b44240_0 .net "AxorB", 0 0, L_0x2ca1480; 1 drivers -v0x2b442c0_0 .net "B", 0 0, L_0x2ca0920; 1 drivers -v0x2b44370_0 .net "BornB", 0 0, L_0x2ca0ef0; 1 drivers -v0x2b44430_0 .net "CINandAxorB", 0 0, L_0x2ca1830; 1 drivers -v0x2b444b0_0 .alias "Command", 2 0, v0x2bc67a0_0; -v0x2b44530_0 .net *"_s3", 0 0, L_0x2ca1200; 1 drivers -v0x2b445b0_0 .net *"_s5", 0 0, L_0x2ca13e0; 1 drivers -v0x2b44650_0 .net "carryin", 0 0, L_0x2ca0a50; 1 drivers -v0x2b446f0_0 .net "carryout", 0 0, L_0x2ca1940; 1 drivers -v0x2b44790_0 .net "nB", 0 0, L_0x2c9f670; 1 drivers -v0x2b44840_0 .net "nCmd2", 0 0, L_0x2ca1140; 1 drivers -v0x2b44940_0 .net "subtract", 0 0, L_0x2ca12a0; 1 drivers -L_0x2ca10a0 .part v0x2bc78e0_0, 0, 1; -L_0x2ca1200 .part v0x2bc78e0_0, 2, 1; -L_0x2ca13e0 .part v0x2bc78e0_0, 0, 1; -S_0x2b43aa0 .scope module, "mux0" "TwoInMux" 3 105, 3 8, S_0x2b439b0; - .timescale -9 -12; -L_0x2ca0c70/d .functor NOT 1, L_0x2ca10a0, C4<0>, C4<0>, C4<0>; -L_0x2ca0c70 .delay (10000,10000,10000) L_0x2ca0c70/d; -L_0x2ca0d10/d .functor AND 1, L_0x2ca0920, L_0x2ca0c70, C4<1>, C4<1>; -L_0x2ca0d10 .delay (20000,20000,20000) L_0x2ca0d10/d; -L_0x2ca0e00/d .functor AND 1, L_0x2c9f670, L_0x2ca10a0, C4<1>, C4<1>; -L_0x2ca0e00 .delay (20000,20000,20000) L_0x2ca0e00/d; -L_0x2ca0ef0/d .functor OR 1, L_0x2ca0d10, L_0x2ca0e00, C4<0>, C4<0>; -L_0x2ca0ef0 .delay (20000,20000,20000) L_0x2ca0ef0/d; -v0x2b43b90_0 .net "S", 0 0, L_0x2ca10a0; 1 drivers -v0x2b43c30_0 .alias "in0", 0 0, v0x2b442c0_0; -v0x2b43cd0_0 .alias "in1", 0 0, v0x2b44790_0; -v0x2b43d70_0 .net "nS", 0 0, L_0x2ca0c70; 1 drivers -v0x2b43e20_0 .net "out0", 0 0, L_0x2ca0d10; 1 drivers -v0x2b43ec0_0 .net "out1", 0 0, L_0x2ca0e00; 1 drivers -v0x2b43fa0_0 .alias "outfinal", 0 0, v0x2b44370_0; -S_0x2b426a0 .scope generate, "addbits[26]" "addbits[26]" 3 230, 3 230, S_0x2851a90; - .timescale -9 -12; -P_0x2b420b8 .param/l "i" 3 230, +C4<011010>; -S_0x2b42810 .scope module, "attempt" "MiddleAddSubSLT" 3 232, 3 89, S_0x2b426a0; - .timescale -9 -12; -L_0x2ca0af0/d .functor NOT 1, L_0x2c05620, C4<0>, C4<0>, C4<0>; -L_0x2ca0af0 .delay (10000,10000,10000) L_0x2ca0af0/d; -L_0x2c059f0/d .functor NOT 1, L_0x2c05a70, C4<0>, C4<0>, C4<0>; -L_0x2c059f0 .delay (10000,10000,10000) L_0x2c059f0/d; -L_0x2c05b10/d .functor AND 1, L_0x2c05c50, L_0x2c059f0, C4<1>, C4<1>; -L_0x2c05b10 .delay (20000,20000,20000) L_0x2c05b10/d; -L_0x2c05cf0/d .functor XOR 1, L_0x2c05580, L_0x2ca1f30, C4<0>, C4<0>; -L_0x2c05cf0 .delay (40000,40000,40000) L_0x2c05cf0/d; -L_0x2c05de0/d .functor XOR 1, L_0x2c05cf0, L_0x2c05750, C4<0>, C4<0>; -L_0x2c05de0 .delay (40000,40000,40000) L_0x2c05de0/d; -L_0x2c05ed0/d .functor AND 1, L_0x2c05580, L_0x2ca1f30, C4<1>, C4<1>; -L_0x2c05ed0 .delay (20000,20000,20000) L_0x2c05ed0/d; -L_0x2c06070/d .functor AND 1, L_0x2c05cf0, L_0x2c05750, C4<1>, C4<1>; -L_0x2c06070 .delay (20000,20000,20000) L_0x2c06070/d; -L_0x2c06180/d .functor OR 1, L_0x2c05ed0, L_0x2c06070, C4<0>, C4<0>; -L_0x2c06180 .delay (20000,20000,20000) L_0x2c06180/d; -v0x2b42ea0_0 .net "A", 0 0, L_0x2c05580; 1 drivers -v0x2b42f60_0 .net "AandB", 0 0, L_0x2c05ed0; 1 drivers -v0x2b43000_0 .net "AddSubSLTSum", 0 0, L_0x2c05de0; 1 drivers -v0x2b430a0_0 .net "AxorB", 0 0, L_0x2c05cf0; 1 drivers -v0x2b43120_0 .net "B", 0 0, L_0x2c05620; 1 drivers -v0x2b431d0_0 .net "BornB", 0 0, L_0x2ca1f30; 1 drivers -v0x2b43290_0 .net "CINandAxorB", 0 0, L_0x2c06070; 1 drivers -v0x2b43310_0 .alias "Command", 2 0, v0x2bc67a0_0; -v0x2b43390_0 .net *"_s3", 0 0, L_0x2c05a70; 1 drivers -v0x2b43410_0 .net *"_s5", 0 0, L_0x2c05c50; 1 drivers -v0x2b434b0_0 .net "carryin", 0 0, L_0x2c05750; 1 drivers -v0x2b43550_0 .net "carryout", 0 0, L_0x2c06180; 1 drivers -v0x2b435f0_0 .net "nB", 0 0, L_0x2ca0af0; 1 drivers -v0x2b436a0_0 .net "nCmd2", 0 0, L_0x2c059f0; 1 drivers -v0x2b437a0_0 .net "subtract", 0 0, L_0x2c05b10; 1 drivers -L_0x2c05950 .part v0x2bc78e0_0, 0, 1; -L_0x2c05a70 .part v0x2bc78e0_0, 2, 1; -L_0x2c05c50 .part v0x2bc78e0_0, 0, 1; -S_0x2b42900 .scope module, "mux0" "TwoInMux" 3 105, 3 8, S_0x2b42810; - .timescale -9 -12; -L_0x2ca0bc0/d .functor NOT 1, L_0x2c05950, C4<0>, C4<0>, C4<0>; -L_0x2ca0bc0 .delay (10000,10000,10000) L_0x2ca0bc0/d; -L_0x2ca1d10/d .functor AND 1, L_0x2c05620, L_0x2ca0bc0, C4<1>, C4<1>; -L_0x2ca1d10 .delay (20000,20000,20000) L_0x2ca1d10/d; -L_0x2ca1e20/d .functor AND 1, L_0x2ca0af0, L_0x2c05950, C4<1>, C4<1>; -L_0x2ca1e20 .delay (20000,20000,20000) L_0x2ca1e20/d; -L_0x2ca1f30/d .functor OR 1, L_0x2ca1d10, L_0x2ca1e20, C4<0>, C4<0>; -L_0x2ca1f30 .delay (20000,20000,20000) L_0x2ca1f30/d; -v0x2b429f0_0 .net "S", 0 0, L_0x2c05950; 1 drivers -v0x2b42a90_0 .alias "in0", 0 0, v0x2b43120_0; -v0x2b42b30_0 .alias "in1", 0 0, v0x2b435f0_0; -v0x2b42bd0_0 .net "nS", 0 0, L_0x2ca0bc0; 1 drivers -v0x2b42c80_0 .net "out0", 0 0, L_0x2ca1d10; 1 drivers -v0x2b42d20_0 .net "out1", 0 0, L_0x2ca1e20; 1 drivers -v0x2b42e00_0 .alias "outfinal", 0 0, v0x2b431d0_0; -S_0x2b41500 .scope generate, "addbits[27]" "addbits[27]" 3 230, 3 230, S_0x2851a90; - .timescale -9 -12; -P_0x2b40f18 .param/l "i" 3 230, +C4<011011>; -S_0x2b41670 .scope module, "attempt" "MiddleAddSubSLT" 3 232, 3 89, S_0x2b41500; - .timescale -9 -12; -L_0x2c057f0/d .functor NOT 1, L_0x2bedff0, C4<0>, C4<0>, C4<0>; -L_0x2c057f0 .delay (10000,10000,10000) L_0x2c057f0/d; -L_0x2ca4af0/d .functor NOT 1, L_0x2ca4bb0, C4<0>, C4<0>, C4<0>; -L_0x2ca4af0 .delay (10000,10000,10000) L_0x2ca4af0/d; -L_0x2ca4c50/d .functor AND 1, L_0x2ca4d90, L_0x2ca4af0, C4<1>, C4<1>; -L_0x2ca4c50 .delay (20000,20000,20000) L_0x2ca4c50/d; -L_0x2ca4e30/d .functor XOR 1, L_0x2bedf50, L_0x2ca4880, C4<0>, C4<0>; -L_0x2ca4e30 .delay (40000,40000,40000) L_0x2ca4e30/d; -L_0x2ca4f20/d .functor XOR 1, L_0x2ca4e30, L_0x2bee120, C4<0>, C4<0>; -L_0x2ca4f20 .delay (40000,40000,40000) L_0x2ca4f20/d; -L_0x2ca5040/d .functor AND 1, L_0x2bedf50, L_0x2ca4880, C4<1>, C4<1>; -L_0x2ca5040 .delay (20000,20000,20000) L_0x2ca5040/d; -L_0x2ca51e0/d .functor AND 1, L_0x2ca4e30, L_0x2bee120, C4<1>, C4<1>; -L_0x2ca51e0 .delay (20000,20000,20000) L_0x2ca51e0/d; -L_0x2ca52f0/d .functor OR 1, L_0x2ca5040, L_0x2ca51e0, C4<0>, C4<0>; -L_0x2ca52f0 .delay (20000,20000,20000) L_0x2ca52f0/d; -v0x2b41d00_0 .net "A", 0 0, L_0x2bedf50; 1 drivers -v0x2b41dc0_0 .net "AandB", 0 0, L_0x2ca5040; 1 drivers -v0x2b41e60_0 .net "AddSubSLTSum", 0 0, L_0x2ca4f20; 1 drivers -v0x2b41f00_0 .net "AxorB", 0 0, L_0x2ca4e30; 1 drivers -v0x2b41f80_0 .net "B", 0 0, L_0x2bedff0; 1 drivers -v0x2b42030_0 .net "BornB", 0 0, L_0x2ca4880; 1 drivers -v0x2b420f0_0 .net "CINandAxorB", 0 0, L_0x2ca51e0; 1 drivers -v0x2b42170_0 .alias "Command", 2 0, v0x2bc67a0_0; -v0x2b421f0_0 .net *"_s3", 0 0, L_0x2ca4bb0; 1 drivers -v0x2b42270_0 .net *"_s5", 0 0, L_0x2ca4d90; 1 drivers -v0x2b42310_0 .net "carryin", 0 0, L_0x2bee120; 1 drivers -v0x2b423b0_0 .net "carryout", 0 0, L_0x2ca52f0; 1 drivers -v0x2b42450_0 .net "nB", 0 0, L_0x2c057f0; 1 drivers -v0x2b42500_0 .net "nCmd2", 0 0, L_0x2ca4af0; 1 drivers -v0x2b42600_0 .net "subtract", 0 0, L_0x2ca4c50; 1 drivers -L_0x2ca4a50 .part v0x2bc78e0_0, 0, 1; -L_0x2ca4bb0 .part v0x2bc78e0_0, 2, 1; -L_0x2ca4d90 .part v0x2bc78e0_0, 0, 1; -S_0x2b41760 .scope module, "mux0" "TwoInMux" 3 105, 3 8, S_0x2b41670; - .timescale -9 -12; -L_0x2ca4680/d .functor NOT 1, L_0x2ca4a50, C4<0>, C4<0>, C4<0>; -L_0x2ca4680 .delay (10000,10000,10000) L_0x2ca4680/d; -L_0x2ca46e0/d .functor AND 1, L_0x2bedff0, L_0x2ca4680, C4<1>, C4<1>; -L_0x2ca46e0 .delay (20000,20000,20000) L_0x2ca46e0/d; -L_0x2ca4790/d .functor AND 1, L_0x2c057f0, L_0x2ca4a50, C4<1>, C4<1>; -L_0x2ca4790 .delay (20000,20000,20000) L_0x2ca4790/d; -L_0x2ca4880/d .functor OR 1, L_0x2ca46e0, L_0x2ca4790, C4<0>, C4<0>; -L_0x2ca4880 .delay (20000,20000,20000) L_0x2ca4880/d; -v0x2b41850_0 .net "S", 0 0, L_0x2ca4a50; 1 drivers -v0x2b418f0_0 .alias "in0", 0 0, v0x2b41f80_0; -v0x2b41990_0 .alias "in1", 0 0, v0x2b42450_0; -v0x2b41a30_0 .net "nS", 0 0, L_0x2ca4680; 1 drivers -v0x2b41ae0_0 .net "out0", 0 0, L_0x2ca46e0; 1 drivers -v0x2b41b80_0 .net "out1", 0 0, L_0x2ca4790; 1 drivers -v0x2b41c60_0 .alias "outfinal", 0 0, v0x2b42030_0; -S_0x2b40360 .scope generate, "addbits[28]" "addbits[28]" 3 230, 3 230, S_0x2851a90; - .timescale -9 -12; -P_0x2b3fd78 .param/l "i" 3 230, +C4<011100>; -S_0x2b404d0 .scope module, "attempt" "MiddleAddSubSLT" 3 232, 3 89, S_0x2b40360; - .timescale -9 -12; -L_0x2bee1c0/d .functor NOT 1, L_0x2ca64d0, C4<0>, C4<0>, C4<0>; -L_0x2bee1c0 .delay (10000,10000,10000) L_0x2bee1c0/d; -L_0x2ca5740/d .functor NOT 1, L_0x2ca5800, C4<0>, C4<0>, C4<0>; -L_0x2ca5740 .delay (10000,10000,10000) L_0x2ca5740/d; -L_0x2ca58a0/d .functor AND 1, L_0x2ca59e0, L_0x2ca5740, C4<1>, C4<1>; -L_0x2ca58a0 .delay (20000,20000,20000) L_0x2ca58a0/d; -L_0x2ca5a80/d .functor XOR 1, L_0x2ca6430, L_0x2ca4510, C4<0>, C4<0>; -L_0x2ca5a80 .delay (40000,40000,40000) L_0x2ca5a80/d; -L_0x2ca68b0/d .functor XOR 1, L_0x2ca5a80, L_0x2ca6600, C4<0>, C4<0>; -L_0x2ca68b0 .delay (40000,40000,40000) L_0x2ca68b0/d; -L_0x2ca69a0/d .functor AND 1, L_0x2ca6430, L_0x2ca4510, C4<1>, C4<1>; -L_0x2ca69a0 .delay (20000,20000,20000) L_0x2ca69a0/d; -L_0x2ca6b10/d .functor AND 1, L_0x2ca5a80, L_0x2ca6600, C4<1>, C4<1>; -L_0x2ca6b10 .delay (20000,20000,20000) L_0x2ca6b10/d; -L_0x2ca6c00/d .functor OR 1, L_0x2ca69a0, L_0x2ca6b10, C4<0>, C4<0>; -L_0x2ca6c00 .delay (20000,20000,20000) L_0x2ca6c00/d; -v0x2b40b60_0 .net "A", 0 0, L_0x2ca6430; 1 drivers -v0x2b40c20_0 .net "AandB", 0 0, L_0x2ca69a0; 1 drivers -v0x2b40cc0_0 .net "AddSubSLTSum", 0 0, L_0x2ca68b0; 1 drivers -v0x2b40d60_0 .net "AxorB", 0 0, L_0x2ca5a80; 1 drivers -v0x2b40de0_0 .net "B", 0 0, L_0x2ca64d0; 1 drivers -v0x2b40e90_0 .net "BornB", 0 0, L_0x2ca4510; 1 drivers -v0x2b40f50_0 .net "CINandAxorB", 0 0, L_0x2ca6b10; 1 drivers -v0x2b40fd0_0 .alias "Command", 2 0, v0x2bc67a0_0; -v0x2b41050_0 .net *"_s3", 0 0, L_0x2ca5800; 1 drivers -v0x2b410d0_0 .net *"_s5", 0 0, L_0x2ca59e0; 1 drivers -v0x2b41170_0 .net "carryin", 0 0, L_0x2ca6600; 1 drivers -v0x2b41210_0 .net "carryout", 0 0, L_0x2ca6c00; 1 drivers -v0x2b412b0_0 .net "nB", 0 0, L_0x2bee1c0; 1 drivers -v0x2b41360_0 .net "nCmd2", 0 0, L_0x2ca5740; 1 drivers -v0x2b41460_0 .net "subtract", 0 0, L_0x2ca58a0; 1 drivers -L_0x2ca56a0 .part v0x2bc78e0_0, 0, 1; -L_0x2ca5800 .part v0x2bc78e0_0, 2, 1; -L_0x2ca59e0 .part v0x2bc78e0_0, 0, 1; -S_0x2b405c0 .scope module, "mux0" "TwoInMux" 3 105, 3 8, S_0x2b404d0; - .timescale -9 -12; -L_0x2ca4230/d .functor NOT 1, L_0x2ca56a0, C4<0>, C4<0>, C4<0>; -L_0x2ca4230 .delay (10000,10000,10000) L_0x2ca4230/d; -L_0x2ca42f0/d .functor AND 1, L_0x2ca64d0, L_0x2ca4230, C4<1>, C4<1>; -L_0x2ca42f0 .delay (20000,20000,20000) L_0x2ca42f0/d; -L_0x2ca4400/d .functor AND 1, L_0x2bee1c0, L_0x2ca56a0, C4<1>, C4<1>; -L_0x2ca4400 .delay (20000,20000,20000) L_0x2ca4400/d; -L_0x2ca4510/d .functor OR 1, L_0x2ca42f0, L_0x2ca4400, C4<0>, C4<0>; -L_0x2ca4510 .delay (20000,20000,20000) L_0x2ca4510/d; -v0x2b406b0_0 .net "S", 0 0, L_0x2ca56a0; 1 drivers -v0x2b40750_0 .alias "in0", 0 0, v0x2b40de0_0; -v0x2b407f0_0 .alias "in1", 0 0, v0x2b412b0_0; -v0x2b40890_0 .net "nS", 0 0, L_0x2ca4230; 1 drivers -v0x2b40940_0 .net "out0", 0 0, L_0x2ca42f0; 1 drivers -v0x2b409e0_0 .net "out1", 0 0, L_0x2ca4400; 1 drivers -v0x2b40ac0_0 .alias "outfinal", 0 0, v0x2b40e90_0; -S_0x2b3f1c0 .scope generate, "addbits[29]" "addbits[29]" 3 230, 3 230, S_0x2851a90; - .timescale -9 -12; -P_0x2b3ebd8 .param/l "i" 3 230, +C4<011101>; -S_0x2b3f330 .scope module, "attempt" "MiddleAddSubSLT" 3 232, 3 89, S_0x2b3f1c0; - .timescale -9 -12; -L_0x2ca66a0/d .functor NOT 1, L_0x2ca70b0, C4<0>, C4<0>, C4<0>; -L_0x2ca66a0 .delay (10000,10000,10000) L_0x2ca66a0/d; -L_0x2ca78c0/d .functor NOT 1, L_0x2ca7980, C4<0>, C4<0>, C4<0>; -L_0x2ca78c0 .delay (10000,10000,10000) L_0x2ca78c0/d; -L_0x2ca7a20/d .functor AND 1, L_0x2ca7b60, L_0x2ca78c0, C4<1>, C4<1>; -L_0x2ca7a20 .delay (20000,20000,20000) L_0x2ca7a20/d; -L_0x2ca7c00/d .functor XOR 1, L_0x2ca7010, L_0x2ca7690, C4<0>, C4<0>; -L_0x2ca7c00 .delay (40000,40000,40000) L_0x2ca7c00/d; -L_0x2ca7d20/d .functor XOR 1, L_0x2ca7c00, L_0x2ca71e0, C4<0>, C4<0>; -L_0x2ca7d20 .delay (40000,40000,40000) L_0x2ca7d20/d; -L_0x2ca7e40/d .functor AND 1, L_0x2ca7010, L_0x2ca7690, C4<1>, C4<1>; -L_0x2ca7e40 .delay (20000,20000,20000) L_0x2ca7e40/d; -L_0x2ca7fe0/d .functor AND 1, L_0x2ca7c00, L_0x2ca71e0, C4<1>, C4<1>; -L_0x2ca7fe0 .delay (20000,20000,20000) L_0x2ca7fe0/d; -L_0x2ca80d0/d .functor OR 1, L_0x2ca7e40, L_0x2ca7fe0, C4<0>, C4<0>; -L_0x2ca80d0 .delay (20000,20000,20000) L_0x2ca80d0/d; -v0x2b3f9c0_0 .net "A", 0 0, L_0x2ca7010; 1 drivers -v0x2b3fa80_0 .net "AandB", 0 0, L_0x2ca7e40; 1 drivers -v0x2b3fb20_0 .net "AddSubSLTSum", 0 0, L_0x2ca7d20; 1 drivers -v0x2b3fbc0_0 .net "AxorB", 0 0, L_0x2ca7c00; 1 drivers -v0x2b3fc40_0 .net "B", 0 0, L_0x2ca70b0; 1 drivers -v0x2b3fcf0_0 .net "BornB", 0 0, L_0x2ca7690; 1 drivers -v0x2b3fdb0_0 .net "CINandAxorB", 0 0, L_0x2ca7fe0; 1 drivers -v0x2b3fe30_0 .alias "Command", 2 0, v0x2bc67a0_0; -v0x2b3feb0_0 .net *"_s3", 0 0, L_0x2ca7980; 1 drivers -v0x2b3ff30_0 .net *"_s5", 0 0, L_0x2ca7b60; 1 drivers -v0x2b3ffd0_0 .net "carryin", 0 0, L_0x2ca71e0; 1 drivers -v0x2b40070_0 .net "carryout", 0 0, L_0x2ca80d0; 1 drivers -v0x2b40110_0 .net "nB", 0 0, L_0x2ca66a0; 1 drivers -v0x2b401c0_0 .net "nCmd2", 0 0, L_0x2ca78c0; 1 drivers -v0x2b402c0_0 .net "subtract", 0 0, L_0x2ca7a20; 1 drivers -L_0x2ca7820 .part v0x2bc78e0_0, 0, 1; -L_0x2ca7980 .part v0x2bc78e0_0, 2, 1; -L_0x2ca7b60 .part v0x2bc78e0_0, 0, 1; -S_0x2b3f420 .scope module, "mux0" "TwoInMux" 3 105, 3 8, S_0x2b3f330; - .timescale -9 -12; -L_0x2ca6800/d .functor NOT 1, L_0x2ca7820, C4<0>, C4<0>, C4<0>; -L_0x2ca6800 .delay (10000,10000,10000) L_0x2ca6800/d; -L_0x2ca74b0/d .functor AND 1, L_0x2ca70b0, L_0x2ca6800, C4<1>, C4<1>; -L_0x2ca74b0 .delay (20000,20000,20000) L_0x2ca74b0/d; -L_0x2ca75a0/d .functor AND 1, L_0x2ca66a0, L_0x2ca7820, C4<1>, C4<1>; -L_0x2ca75a0 .delay (20000,20000,20000) L_0x2ca75a0/d; -L_0x2ca7690/d .functor OR 1, L_0x2ca74b0, L_0x2ca75a0, C4<0>, C4<0>; -L_0x2ca7690 .delay (20000,20000,20000) L_0x2ca7690/d; -v0x2b3f510_0 .net "S", 0 0, L_0x2ca7820; 1 drivers -v0x2b3f5b0_0 .alias "in0", 0 0, v0x2b3fc40_0; -v0x2b3f650_0 .alias "in1", 0 0, v0x2b40110_0; -v0x2b3f6f0_0 .net "nS", 0 0, L_0x2ca6800; 1 drivers -v0x2b3f7a0_0 .net "out0", 0 0, L_0x2ca74b0; 1 drivers -v0x2b3f840_0 .net "out1", 0 0, L_0x2ca75a0; 1 drivers -v0x2b3f920_0 .alias "outfinal", 0 0, v0x2b3fcf0_0; -S_0x2b3e020 .scope generate, "addbits[30]" "addbits[30]" 3 230, 3 230, S_0x2851a90; - .timescale -9 -12; -P_0x2b3d918 .param/l "i" 3 230, +C4<011110>; -S_0x2b3e190 .scope module, "attempt" "MiddleAddSubSLT" 3 232, 3 89, S_0x2b3e020; - .timescale -9 -12; -L_0x2ca7280/d .functor NOT 1, L_0x2ca85a0, C4<0>, C4<0>, C4<0>; -L_0x2ca7280 .delay (10000,10000,10000) L_0x2ca7280/d; -L_0x2ca8de0/d .functor NOT 1, L_0x2ca8e80, C4<0>, C4<0>, C4<0>; -L_0x2ca8de0 .delay (10000,10000,10000) L_0x2ca8de0/d; -L_0x2ca8f20/d .functor AND 1, L_0x2ca9060, L_0x2ca8de0, C4<1>, C4<1>; -L_0x2ca8f20 .delay (20000,20000,20000) L_0x2ca8f20/d; -L_0x2ca9100/d .functor XOR 1, L_0x2ca8500, L_0x2ca8bb0, C4<0>, C4<0>; -L_0x2ca9100 .delay (40000,40000,40000) L_0x2ca9100/d; -L_0x2ca9220/d .functor XOR 1, L_0x2ca9100, L_0x2ca86d0, C4<0>, C4<0>; -L_0x2ca9220 .delay (40000,40000,40000) L_0x2ca9220/d; -L_0x2ca9340/d .functor AND 1, L_0x2ca8500, L_0x2ca8bb0, C4<1>, C4<1>; -L_0x2ca9340 .delay (20000,20000,20000) L_0x2ca9340/d; -L_0x2ca94e0/d .functor AND 1, L_0x2ca9100, L_0x2ca86d0, C4<1>, C4<1>; -L_0x2ca94e0 .delay (20000,20000,20000) L_0x2ca94e0/d; -L_0x2ca95d0/d .functor OR 1, L_0x2ca9340, L_0x2ca94e0, C4<0>, C4<0>; -L_0x2ca95d0 .delay (20000,20000,20000) L_0x2ca95d0/d; -v0x2b3e820_0 .net "A", 0 0, L_0x2ca8500; 1 drivers -v0x2b3e8e0_0 .net "AandB", 0 0, L_0x2ca9340; 1 drivers -v0x2b3e980_0 .net "AddSubSLTSum", 0 0, L_0x2ca9220; 1 drivers -v0x2b3ea20_0 .net "AxorB", 0 0, L_0x2ca9100; 1 drivers -v0x2b3eaa0_0 .net "B", 0 0, L_0x2ca85a0; 1 drivers -v0x2b3eb50_0 .net "BornB", 0 0, L_0x2ca8bb0; 1 drivers -v0x2b3ec10_0 .net "CINandAxorB", 0 0, L_0x2ca94e0; 1 drivers -v0x2b3ec90_0 .alias "Command", 2 0, v0x2bc67a0_0; -v0x2b3ed10_0 .net *"_s3", 0 0, L_0x2ca8e80; 1 drivers -v0x2b3ed90_0 .net *"_s5", 0 0, L_0x2ca9060; 1 drivers -v0x2b3ee30_0 .net "carryin", 0 0, L_0x2ca86d0; 1 drivers -v0x2b3eed0_0 .net "carryout", 0 0, L_0x2ca95d0; 1 drivers -v0x2b3ef70_0 .net "nB", 0 0, L_0x2ca7280; 1 drivers -v0x2b3f020_0 .net "nCmd2", 0 0, L_0x2ca8de0; 1 drivers -v0x2b3f120_0 .net "subtract", 0 0, L_0x2ca8f20; 1 drivers -L_0x2ca8d40 .part v0x2bc78e0_0, 0, 1; -L_0x2ca8e80 .part v0x2bc78e0_0, 2, 1; -L_0x2ca9060 .part v0x2bc78e0_0, 0, 1; -S_0x2b3e280 .scope module, "mux0" "TwoInMux" 3 105, 3 8, S_0x2b3e190; - .timescale -9 -12; -L_0x2ca73e0/d .functor NOT 1, L_0x2ca8d40, C4<0>, C4<0>, C4<0>; -L_0x2ca73e0 .delay (10000,10000,10000) L_0x2ca73e0/d; -L_0x2ca89d0/d .functor AND 1, L_0x2ca85a0, L_0x2ca73e0, C4<1>, C4<1>; -L_0x2ca89d0 .delay (20000,20000,20000) L_0x2ca89d0/d; -L_0x2ca8ac0/d .functor AND 1, L_0x2ca7280, L_0x2ca8d40, C4<1>, C4<1>; -L_0x2ca8ac0 .delay (20000,20000,20000) L_0x2ca8ac0/d; -L_0x2ca8bb0/d .functor OR 1, L_0x2ca89d0, L_0x2ca8ac0, C4<0>, C4<0>; -L_0x2ca8bb0 .delay (20000,20000,20000) L_0x2ca8bb0/d; -v0x2b3e370_0 .net "S", 0 0, L_0x2ca8d40; 1 drivers -v0x2b3e410_0 .alias "in0", 0 0, v0x2b3eaa0_0; -v0x2b3e4b0_0 .alias "in1", 0 0, v0x2b3ef70_0; -v0x2b3e550_0 .net "nS", 0 0, L_0x2ca73e0; 1 drivers -v0x2b3e600_0 .net "out0", 0 0, L_0x2ca89d0; 1 drivers -v0x2b3e6a0_0 .net "out1", 0 0, L_0x2ca8ac0; 1 drivers -v0x2b3e780_0 .alias "outfinal", 0 0, v0x2b3eb50_0; -S_0x2b3cdc0 .scope generate, "addbits[31]" "addbits[31]" 3 230, 3 230, S_0x2851a90; - .timescale -9 -12; -P_0x2851c08 .param/l "i" 3 230, +C4<011111>; -S_0x2b3cef0 .scope module, "attempt" "MiddleAddSubSLT" 3 232, 3 89, S_0x2b3cdc0; - .timescale -9 -12; -L_0x2ca8770/d .functor NOT 1, L_0x2ca9aa0, C4<0>, C4<0>, C4<0>; -L_0x2ca8770 .delay (10000,10000,10000) L_0x2ca8770/d; -L_0x2caa2d0/d .functor NOT 1, L_0x2caa370, C4<0>, C4<0>, C4<0>; -L_0x2caa2d0 .delay (10000,10000,10000) L_0x2caa2d0/d; -L_0x2caa410/d .functor AND 1, L_0x2caa550, L_0x2caa2d0, C4<1>, C4<1>; -L_0x2caa410 .delay (20000,20000,20000) L_0x2caa410/d; -L_0x2caa5f0/d .functor XOR 1, L_0x2ca9a00, L_0x2caa0a0, C4<0>, C4<0>; -L_0x2caa5f0 .delay (40000,40000,40000) L_0x2caa5f0/d; -L_0x2caa710/d .functor XOR 1, L_0x2caa5f0, L_0x2ca9bd0, C4<0>, C4<0>; -L_0x2caa710 .delay (40000,40000,40000) L_0x2caa710/d; -L_0x2caa830/d .functor AND 1, L_0x2ca9a00, L_0x2caa0a0, C4<1>, C4<1>; -L_0x2caa830 .delay (20000,20000,20000) L_0x2caa830/d; -L_0x2caa9d0/d .functor AND 1, L_0x2caa5f0, L_0x2ca9bd0, C4<1>, C4<1>; -L_0x2caa9d0 .delay (20000,20000,20000) L_0x2caa9d0/d; -L_0x2caaac0/d .functor OR 1, L_0x2caa830, L_0x2caa9d0, C4<0>, C4<0>; -L_0x2caaac0 .delay (20000,20000,20000) L_0x2caaac0/d; -v0x2b3d560_0 .net "A", 0 0, L_0x2ca9a00; 1 drivers -v0x2b3d620_0 .net "AandB", 0 0, L_0x2caa830; 1 drivers -v0x2b3d6c0_0 .net "AddSubSLTSum", 0 0, L_0x2caa710; 1 drivers -v0x2b3d760_0 .net "AxorB", 0 0, L_0x2caa5f0; 1 drivers -v0x2b3d7e0_0 .net "B", 0 0, L_0x2ca9aa0; 1 drivers -v0x2b3d890_0 .net "BornB", 0 0, L_0x2caa0a0; 1 drivers -v0x2b3d950_0 .net "CINandAxorB", 0 0, L_0x2caa9d0; 1 drivers -v0x2b3d9d0_0 .alias "Command", 2 0, v0x2bc67a0_0; -v0x2b3daa0_0 .net *"_s3", 0 0, L_0x2caa370; 1 drivers -v0x2b3db20_0 .net *"_s5", 0 0, L_0x2caa550; 1 drivers -v0x2b3dc20_0 .net "carryin", 0 0, L_0x2ca9bd0; 1 drivers -v0x2b3dcc0_0 .net "carryout", 0 0, L_0x2caaac0; 1 drivers -v0x2b3ddd0_0 .net "nB", 0 0, L_0x2ca8770; 1 drivers -v0x2b3de80_0 .net "nCmd2", 0 0, L_0x2caa2d0; 1 drivers -v0x2b3df80_0 .net "subtract", 0 0, L_0x2caa410; 1 drivers -L_0x2caa230 .part v0x2bc78e0_0, 0, 1; -L_0x2caa370 .part v0x2bc78e0_0, 2, 1; -L_0x2caa550 .part v0x2bc78e0_0, 0, 1; -S_0x2b3cfe0 .scope module, "mux0" "TwoInMux" 3 105, 3 8, S_0x2b3cef0; - .timescale -9 -12; -L_0x2ca88d0/d .functor NOT 1, L_0x2caa230, C4<0>, C4<0>, C4<0>; -L_0x2ca88d0 .delay (10000,10000,10000) L_0x2ca88d0/d; -L_0x2ca9ec0/d .functor AND 1, L_0x2ca9aa0, L_0x2ca88d0, C4<1>, C4<1>; -L_0x2ca9ec0 .delay (20000,20000,20000) L_0x2ca9ec0/d; -L_0x2ca9fb0/d .functor AND 1, L_0x2ca8770, L_0x2caa230, C4<1>, C4<1>; -L_0x2ca9fb0 .delay (20000,20000,20000) L_0x2ca9fb0/d; -L_0x2caa0a0/d .functor OR 1, L_0x2ca9ec0, L_0x2ca9fb0, C4<0>, C4<0>; -L_0x2caa0a0 .delay (20000,20000,20000) L_0x2caa0a0/d; -v0x2b3d0d0_0 .net "S", 0 0, L_0x2caa230; 1 drivers -v0x2b3d150_0 .alias "in0", 0 0, v0x2b3d7e0_0; -v0x2b3d1f0_0 .alias "in1", 0 0, v0x2b3ddd0_0; -v0x2b3d290_0 .net "nS", 0 0, L_0x2ca88d0; 1 drivers -v0x2b3d340_0 .net "out0", 0 0, L_0x2ca9ec0; 1 drivers -v0x2b3d3e0_0 .net "out1", 0 0, L_0x2ca9fb0; 1 drivers -v0x2b3d4c0_0 .alias "outfinal", 0 0, v0x2b3d890_0; -S_0x2ae82e0 .scope module, "trial1" "AndNand32" 3 280, 3 154, S_0x29738d0; - .timescale -9 -12; -P_0x2ad3738 .param/l "size" 3 161, +C4<0100000>; -v0x2851830_0 .alias "A", 31 0, v0x2bc6580_0; -v0x28518b0_0 .alias "AndNandOut", 31 0, v0x2bc77e0_0; -v0x2851930_0 .alias "B", 31 0, v0x2bc66a0_0; -v0x28519e0_0 .alias "Command", 2 0, v0x2bc67a0_0; -L_0x2cae270 .part/pv L_0x2cae000, 1, 1, 32; -L_0x2cae330 .part v0x2bc7660_0, 1, 1; -L_0x2cae3d0 .part v0x2bc7860_0, 1, 1; -L_0x2caece0 .part/pv L_0x2caea70, 2, 1, 32; -L_0x2caed80 .part v0x2bc7660_0, 2, 1; -L_0x2caee20 .part v0x2bc7860_0, 2, 1; -L_0x2caf750 .part/pv L_0x2caf4e0, 3, 1, 32; -L_0x2caf7f0 .part v0x2bc7660_0, 3, 1; -L_0x2caf8e0 .part v0x2bc7860_0, 3, 1; -L_0x2cb01b0 .part/pv L_0x2caff40, 4, 1, 32; -L_0x2cb02b0 .part v0x2bc7660_0, 4, 1; -L_0x2cb0350 .part v0x2bc7860_0, 4, 1; -L_0x2cb0c20 .part/pv L_0x2cb09b0, 5, 1, 32; -L_0x2cb0cc0 .part v0x2bc7660_0, 5, 1; -L_0x2cb0de0 .part v0x2bc7860_0, 5, 1; -L_0x2cb16f0 .part/pv L_0x2cb1480, 6, 1, 32; -L_0x2cb1820 .part v0x2bc7660_0, 6, 1; -L_0x2cb18c0 .part v0x2bc7860_0, 6, 1; -L_0x2cb21f0 .part/pv L_0x2cb1f80, 7, 1, 32; -L_0x2cb2290 .part v0x2bc7660_0, 7, 1; -L_0x2cb19b0 .part v0x2bc7860_0, 7, 1; -L_0x2cb2c50 .part/pv L_0x2cb29e0, 8, 1, 32; -L_0x2cb2330 .part v0x2bc7660_0, 8, 1; -L_0x2cb2db0 .part v0x2bc7860_0, 8, 1; -L_0x2cb3540 .part/pv L_0x2cb3310, 9, 1, 32; -L_0x2cb35e0 .part v0x2bc7660_0, 9, 1; -L_0x2cb2ea0 .part v0x2bc7860_0, 9, 1; -L_0x2cb3ed0 .part/pv L_0x2cb3ca0, 10, 1, 32; -L_0x2cb3680 .part v0x2bc7660_0, 10, 1; -L_0x2cb4060 .part v0x2bc7860_0, 10, 1; -L_0x2cb4880 .part/pv L_0x2cb4650, 11, 1, 32; -L_0x2cb4920 .part v0x2bc7660_0, 11, 1; -L_0x2cb4150 .part v0x2bc7860_0, 11, 1; -L_0x2cb52f0 .part/pv L_0x2cb5080, 12, 1, 32; -L_0x2cb49c0 .part v0x2bc7660_0, 12, 1; -L_0x2cb54b0 .part v0x2bc7860_0, 12, 1; -L_0x2cb5d70 .part/pv L_0x2cb5b00, 13, 1, 32; -L_0x2cb5e10 .part v0x2bc7660_0, 13, 1; -L_0x2cb5550 .part v0x2bc7860_0, 13, 1; -L_0x2cb6810 .part/pv L_0x2cb65a0, 14, 1, 32; -L_0x2cb5eb0 .part v0x2bc7660_0, 14, 1; -L_0x2cb5f50 .part v0x2bc7860_0, 14, 1; -L_0x2cb72c0 .part/pv L_0x2cb7050, 15, 1, 32; -L_0x2cb7360 .part v0x2bc7660_0, 15, 1; -L_0x2cb6a50 .part v0x2bc7860_0, 15, 1; -L_0x2cb7d70 .part/pv L_0x2cb7b00, 16, 1, 32; -L_0x2cb7400 .part v0x2bc7660_0, 16, 1; -L_0x2cb74a0 .part v0x2bc7860_0, 16, 1; -L_0x2cb8830 .part/pv L_0x2cb85c0, 17, 1, 32; -L_0x2cb88d0 .part v0x2bc7660_0, 17, 1; -L_0x2cb7fe0 .part v0x2bc7860_0, 17, 1; -L_0x2cb92d0 .part/pv L_0x2cb9060, 18, 1, 32; -L_0x2cb8970 .part v0x2bc7660_0, 18, 1; -L_0x2cb8a10 .part v0x2bc7860_0, 18, 1; -L_0x2cb9d90 .part/pv L_0x2cb9b20, 19, 1, 32; -L_0x2cb9e30 .part v0x2bc7660_0, 19, 1; -L_0x2cb9370 .part v0x2bc7860_0, 19, 1; -L_0x2cba7f0 .part/pv L_0x2cba580, 20, 1, 32; -L_0x2cb9ed0 .part v0x2bc7660_0, 20, 1; -L_0x2cb9f70 .part v0x2bc7860_0, 20, 1; -L_0x2cbb260 .part/pv L_0x2cbaff0, 21, 1, 32; -L_0x2cbb300 .part v0x2bc7660_0, 21, 1; -L_0x2cba890 .part v0x2bc7860_0, 21, 1; -L_0x2cbbcd0 .part/pv L_0x2cbba60, 22, 1, 32; -L_0x2cbb3a0 .part v0x2bc7660_0, 22, 1; -L_0x2cbb440 .part v0x2bc7860_0, 22, 1; -L_0x2cbc750 .part/pv L_0x2cbc4e0, 23, 1, 32; -L_0x2cbc7f0 .part v0x2bc7660_0, 23, 1; -L_0x2cbbd70 .part v0x2bc7860_0, 23, 1; -L_0x2cbd1b0 .part/pv L_0x2cbcf40, 24, 1, 32; -L_0x2cbc890 .part v0x2bc7660_0, 24, 1; -L_0x2cbc930 .part v0x2bc7860_0, 24, 1; -L_0x2cbdc20 .part/pv L_0x2cbd9b0, 25, 1, 32; -L_0x2cbdcc0 .part v0x2bc7660_0, 25, 1; -L_0x2cbd250 .part v0x2bc7860_0, 25, 1; -L_0x2cbe640 .part/pv L_0x2cbe410, 26, 1, 32; -L_0x2cbdd60 .part v0x2bc7660_0, 26, 1; -L_0x2cbde00 .part v0x2bc7860_0, 26, 1; -L_0x2cbf110 .part/pv L_0x2cbeea0, 27, 1, 32; -L_0x2cbf1b0 .part v0x2bc7660_0, 27, 1; -L_0x2cbe6e0 .part v0x2bc7860_0, 27, 1; -L_0x2cbfbc0 .part/pv L_0x2cbf950, 28, 1, 32; -L_0x2cbf250 .part v0x2bc7660_0, 28, 1; -L_0x2cbf2f0 .part v0x2bc7860_0, 28, 1; -L_0x2cc0640 .part/pv L_0x2cc03d0, 29, 1, 32; -L_0x2cc06e0 .part v0x2bc7660_0, 29, 1; -L_0x2cbfc60 .part v0x2bc7860_0, 29, 1; -L_0x2cc10a0 .part/pv L_0x2cc0e30, 30, 1, 32; -L_0x2cc0780 .part v0x2bc7660_0, 30, 1; -L_0x2cc0820 .part v0x2bc7860_0, 30, 1; -L_0x2cc1b10 .part/pv L_0x2cc18a0, 31, 1, 32; -L_0x2c55e80 .part v0x2bc7660_0, 31, 1; -L_0x2cc1140 .part v0x2bc7860_0, 31, 1; -L_0x2cc2c60 .part/pv L_0x2c56470, 0, 1, 32; -L_0x2c55f20 .part v0x2bc7660_0, 0, 1; -L_0x2c55fc0 .part v0x2bc7860_0, 0, 1; -S_0x2b3bb80 .scope module, "attempt2" "AndNand" 3 165, 3 48, S_0x2ae82e0; - .timescale -9 -12; -L_0x29b6d20/d .functor NAND 1, L_0x2c55f20, L_0x2c55fc0, C4<1>, C4<1>; -L_0x29b6d20 .delay (10000,10000,10000) L_0x29b6d20/d; -L_0x29d41b0/d .functor NOT 1, L_0x29b6d20, C4<0>, C4<0>, C4<0>; -L_0x29d41b0 .delay (10000,10000,10000) L_0x29d41b0/d; -v0x2b3c1a0_0 .net "A", 0 0, L_0x2c55f20; 1 drivers -v0x2b3c260_0 .net "AandB", 0 0, L_0x29d41b0; 1 drivers -v0x2b3c2e0_0 .net "AnandB", 0 0, L_0x29b6d20; 1 drivers -v0x2b3c390_0 .net "AndNandOut", 0 0, L_0x2c56470; 1 drivers -v0x2b3c470_0 .net "B", 0 0, L_0x2c55fc0; 1 drivers -v0x2b3c4f0_0 .alias "Command", 2 0, v0x2bc67a0_0; -L_0x2cc2bc0 .part v0x2bc78e0_0, 0, 1; -S_0x2b3bc70 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0x2b3bb80; - .timescale -9 -12; -L_0x2994d70/d .functor NOT 1, L_0x2cc2bc0, C4<0>, C4<0>, C4<0>; -L_0x2994d70 .delay (10000,10000,10000) L_0x2994d70/d; -L_0x2c56210/d .functor AND 1, L_0x29d41b0, L_0x2994d70, C4<1>, C4<1>; -L_0x2c56210 .delay (20000,20000,20000) L_0x2c56210/d; -L_0x2c56320/d .functor AND 1, L_0x29b6d20, L_0x2cc2bc0, C4<1>, C4<1>; -L_0x2c56320 .delay (20000,20000,20000) L_0x2c56320/d; -L_0x2c56470/d .functor OR 1, L_0x2c56210, L_0x2c56320, C4<0>, C4<0>; -L_0x2c56470 .delay (20000,20000,20000) L_0x2c56470/d; -v0x2b3bd60_0 .net "S", 0 0, L_0x2cc2bc0; 1 drivers -v0x2b3bde0_0 .alias "in0", 0 0, v0x2b3c260_0; -v0x2b3be60_0 .alias "in1", 0 0, v0x2b3c2e0_0; -v0x2b3bf00_0 .net "nS", 0 0, L_0x2994d70; 1 drivers -v0x2b3bf80_0 .net "out0", 0 0, L_0x2c56210; 1 drivers -v0x2b3c020_0 .net "out1", 0 0, L_0x2c56320; 1 drivers -v0x2b3c100_0 .alias "outfinal", 0 0, v0x2b3c390_0; -S_0x2b3afc0 .scope generate, "andbits[1]" "andbits[1]" 3 169, 3 169, S_0x2ae82e0; - .timescale -9 -12; -P_0x2b3b0b8 .param/l "i" 3 169, +C4<01>; -S_0x2b3b130 .scope module, "attempt" "AndNand" 3 171, 3 48, S_0x2b3afc0; - .timescale -9 -12; -L_0x2cadaf0/d .functor NAND 1, L_0x2cae330, L_0x2cae3d0, C4<1>, C4<1>; -L_0x2cadaf0 .delay (10000,10000,10000) L_0x2cadaf0/d; -L_0x2cadbb0/d .functor NOT 1, L_0x2cadaf0, C4<0>, C4<0>, C4<0>; -L_0x2cadbb0 .delay (10000,10000,10000) L_0x2cadbb0/d; -v0x2b3b770_0 .net "A", 0 0, L_0x2cae330; 1 drivers -v0x2b3b830_0 .net "AandB", 0 0, L_0x2cadbb0; 1 drivers -v0x2b3b8b0_0 .net "AnandB", 0 0, L_0x2cadaf0; 1 drivers -v0x2b3b960_0 .net "AndNandOut", 0 0, L_0x2cae000; 1 drivers -v0x2b3ba40_0 .net "B", 0 0, L_0x2cae3d0; 1 drivers -v0x2b3bac0_0 .alias "Command", 2 0, v0x2bc67a0_0; -L_0x2cae1d0 .part v0x2bc78e0_0, 0, 1; -S_0x2b3b220 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0x2b3b130; - .timescale -9 -12; -L_0x2cadce0/d .functor NOT 1, L_0x2cae1d0, C4<0>, C4<0>, C4<0>; -L_0x2cadce0 .delay (10000,10000,10000) L_0x2cadce0/d; -L_0x2cadda0/d .functor AND 1, L_0x2cadbb0, L_0x2cadce0, C4<1>, C4<1>; -L_0x2cadda0 .delay (20000,20000,20000) L_0x2cadda0/d; -L_0x2cadeb0/d .functor AND 1, L_0x2cadaf0, L_0x2cae1d0, C4<1>, C4<1>; -L_0x2cadeb0 .delay (20000,20000,20000) L_0x2cadeb0/d; -L_0x2cae000/d .functor OR 1, L_0x2cadda0, L_0x2cadeb0, C4<0>, C4<0>; -L_0x2cae000 .delay (20000,20000,20000) L_0x2cae000/d; -v0x2b3b310_0 .net "S", 0 0, L_0x2cae1d0; 1 drivers -v0x2b3b390_0 .alias "in0", 0 0, v0x2b3b830_0; -v0x2b3b430_0 .alias "in1", 0 0, v0x2b3b8b0_0; -v0x2b3b4d0_0 .net "nS", 0 0, L_0x2cadce0; 1 drivers -v0x2b3b550_0 .net "out0", 0 0, L_0x2cadda0; 1 drivers -v0x2b3b5f0_0 .net "out1", 0 0, L_0x2cadeb0; 1 drivers -v0x2b3b6d0_0 .alias "outfinal", 0 0, v0x2b3b960_0; -S_0x2b3a400 .scope generate, "andbits[2]" "andbits[2]" 3 169, 3 169, S_0x2ae82e0; - .timescale -9 -12; -P_0x2b3a4f8 .param/l "i" 3 169, +C4<010>; -S_0x2b3a570 .scope module, "attempt" "AndNand" 3 171, 3 48, S_0x2b3a400; - .timescale -9 -12; -L_0x2cae4c0/d .functor NAND 1, L_0x2caed80, L_0x2caee20, C4<1>, C4<1>; -L_0x2cae4c0 .delay (10000,10000,10000) L_0x2cae4c0/d; -L_0x2cae620/d .functor NOT 1, L_0x2cae4c0, C4<0>, C4<0>, C4<0>; -L_0x2cae620 .delay (10000,10000,10000) L_0x2cae620/d; -v0x2b3abb0_0 .net "A", 0 0, L_0x2caed80; 1 drivers -v0x2b3ac70_0 .net "AandB", 0 0, L_0x2cae620; 1 drivers -v0x2b3acf0_0 .net "AnandB", 0 0, L_0x2cae4c0; 1 drivers -v0x2b3ada0_0 .net "AndNandOut", 0 0, L_0x2caea70; 1 drivers -v0x2b3ae80_0 .net "B", 0 0, L_0x2caee20; 1 drivers -v0x2b3af00_0 .alias "Command", 2 0, v0x2bc67a0_0; -L_0x2caec40 .part v0x2bc78e0_0, 0, 1; -S_0x2b3a660 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0x2b3a570; - .timescale -9 -12; -L_0x2cae750/d .functor NOT 1, L_0x2caec40, C4<0>, C4<0>, C4<0>; -L_0x2cae750 .delay (10000,10000,10000) L_0x2cae750/d; -L_0x2cae810/d .functor AND 1, L_0x2cae620, L_0x2cae750, C4<1>, C4<1>; -L_0x2cae810 .delay (20000,20000,20000) L_0x2cae810/d; -L_0x2cae920/d .functor AND 1, L_0x2cae4c0, L_0x2caec40, C4<1>, C4<1>; -L_0x2cae920 .delay (20000,20000,20000) L_0x2cae920/d; -L_0x2caea70/d .functor OR 1, L_0x2cae810, L_0x2cae920, C4<0>, C4<0>; -L_0x2caea70 .delay (20000,20000,20000) L_0x2caea70/d; -v0x2b3a750_0 .net "S", 0 0, L_0x2caec40; 1 drivers -v0x2b3a7d0_0 .alias "in0", 0 0, v0x2b3ac70_0; -v0x2b3a870_0 .alias "in1", 0 0, v0x2b3acf0_0; -v0x2b3a910_0 .net "nS", 0 0, L_0x2cae750; 1 drivers -v0x2b3a990_0 .net "out0", 0 0, L_0x2cae810; 1 drivers -v0x2b3aa30_0 .net "out1", 0 0, L_0x2cae920; 1 drivers -v0x2b3ab10_0 .alias "outfinal", 0 0, v0x2b3ada0_0; -S_0x2b39840 .scope generate, "andbits[3]" "andbits[3]" 3 169, 3 169, S_0x2ae82e0; - .timescale -9 -12; -P_0x2b39938 .param/l "i" 3 169, +C4<011>; -S_0x2b399b0 .scope module, "attempt" "AndNand" 3 171, 3 48, S_0x2b39840; - .timescale -9 -12; -L_0x2caef50/d .functor NAND 1, L_0x2caf7f0, L_0x2caf8e0, C4<1>, C4<1>; -L_0x2caef50 .delay (10000,10000,10000) L_0x2caef50/d; -L_0x2caf090/d .functor NOT 1, L_0x2caef50, C4<0>, C4<0>, C4<0>; -L_0x2caf090 .delay (10000,10000,10000) L_0x2caf090/d; -v0x2b39ff0_0 .net "A", 0 0, L_0x2caf7f0; 1 drivers -v0x2b3a0b0_0 .net "AandB", 0 0, L_0x2caf090; 1 drivers -v0x2b3a130_0 .net "AnandB", 0 0, L_0x2caef50; 1 drivers -v0x2b3a1e0_0 .net "AndNandOut", 0 0, L_0x2caf4e0; 1 drivers -v0x2b3a2c0_0 .net "B", 0 0, L_0x2caf8e0; 1 drivers -v0x2b3a340_0 .alias "Command", 2 0, v0x2bc67a0_0; -L_0x2caf6b0 .part v0x2bc78e0_0, 0, 1; -S_0x2b39aa0 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0x2b399b0; - .timescale -9 -12; -L_0x2caf1c0/d .functor NOT 1, L_0x2caf6b0, C4<0>, C4<0>, C4<0>; -L_0x2caf1c0 .delay (10000,10000,10000) L_0x2caf1c0/d; -L_0x2caf280/d .functor AND 1, L_0x2caf090, L_0x2caf1c0, C4<1>, C4<1>; -L_0x2caf280 .delay (20000,20000,20000) L_0x2caf280/d; -L_0x2caf390/d .functor AND 1, L_0x2caef50, L_0x2caf6b0, C4<1>, C4<1>; -L_0x2caf390 .delay (20000,20000,20000) L_0x2caf390/d; -L_0x2caf4e0/d .functor OR 1, L_0x2caf280, L_0x2caf390, C4<0>, C4<0>; -L_0x2caf4e0 .delay (20000,20000,20000) L_0x2caf4e0/d; -v0x2b39b90_0 .net "S", 0 0, L_0x2caf6b0; 1 drivers -v0x2b39c10_0 .alias "in0", 0 0, v0x2b3a0b0_0; -v0x2b39cb0_0 .alias "in1", 0 0, v0x2b3a130_0; -v0x2b39d50_0 .net "nS", 0 0, L_0x2caf1c0; 1 drivers -v0x2b39dd0_0 .net "out0", 0 0, L_0x2caf280; 1 drivers -v0x2b39e70_0 .net "out1", 0 0, L_0x2caf390; 1 drivers -v0x2b39f50_0 .alias "outfinal", 0 0, v0x2b3a1e0_0; -S_0x2b38c80 .scope generate, "andbits[4]" "andbits[4]" 3 169, 3 169, S_0x2ae82e0; - .timescale -9 -12; -P_0x2b38d78 .param/l "i" 3 169, +C4<0100>; -S_0x2b38df0 .scope module, "attempt" "AndNand" 3 171, 3 48, S_0x2b38c80; - .timescale -9 -12; -L_0x2caf9d0/d .functor NAND 1, L_0x2cb02b0, L_0x2cb0350, C4<1>, C4<1>; -L_0x2caf9d0 .delay (10000,10000,10000) L_0x2caf9d0/d; -L_0x2cafaf0/d .functor NOT 1, L_0x2caf9d0, C4<0>, C4<0>, C4<0>; -L_0x2cafaf0 .delay (10000,10000,10000) L_0x2cafaf0/d; -v0x2b39430_0 .net "A", 0 0, L_0x2cb02b0; 1 drivers -v0x2b394f0_0 .net "AandB", 0 0, L_0x2cafaf0; 1 drivers -v0x2b39570_0 .net "AnandB", 0 0, L_0x2caf9d0; 1 drivers -v0x2b39620_0 .net "AndNandOut", 0 0, L_0x2caff40; 1 drivers -v0x2b39700_0 .net "B", 0 0, L_0x2cb0350; 1 drivers -v0x2b39780_0 .alias "Command", 2 0, v0x2bc67a0_0; -L_0x2cb0110 .part v0x2bc78e0_0, 0, 1; -S_0x2b38ee0 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0x2b38df0; - .timescale -9 -12; -L_0x2cafc20/d .functor NOT 1, L_0x2cb0110, C4<0>, C4<0>, C4<0>; -L_0x2cafc20 .delay (10000,10000,10000) L_0x2cafc20/d; -L_0x2cafce0/d .functor AND 1, L_0x2cafaf0, L_0x2cafc20, C4<1>, C4<1>; -L_0x2cafce0 .delay (20000,20000,20000) L_0x2cafce0/d; -L_0x2cafdf0/d .functor AND 1, L_0x2caf9d0, L_0x2cb0110, C4<1>, C4<1>; -L_0x2cafdf0 .delay (20000,20000,20000) L_0x2cafdf0/d; -L_0x2caff40/d .functor OR 1, L_0x2cafce0, L_0x2cafdf0, C4<0>, C4<0>; -L_0x2caff40 .delay (20000,20000,20000) L_0x2caff40/d; -v0x2b38fd0_0 .net "S", 0 0, L_0x2cb0110; 1 drivers -v0x2b39050_0 .alias "in0", 0 0, v0x2b394f0_0; -v0x2b390f0_0 .alias "in1", 0 0, v0x2b39570_0; -v0x2b39190_0 .net "nS", 0 0, L_0x2cafc20; 1 drivers -v0x2b39210_0 .net "out0", 0 0, L_0x2cafce0; 1 drivers -v0x2b392b0_0 .net "out1", 0 0, L_0x2cafdf0; 1 drivers -v0x2b39390_0 .alias "outfinal", 0 0, v0x2b39620_0; -S_0x2b380c0 .scope generate, "andbits[5]" "andbits[5]" 3 169, 3 169, S_0x2ae82e0; - .timescale -9 -12; -P_0x2b381b8 .param/l "i" 3 169, +C4<0101>; -S_0x2b38230 .scope module, "attempt" "AndNand" 3 171, 3 48, S_0x2b380c0; - .timescale -9 -12; -L_0x2cb0250/d .functor NAND 1, L_0x2cb0cc0, L_0x2cb0de0, C4<1>, C4<1>; -L_0x2cb0250 .delay (10000,10000,10000) L_0x2cb0250/d; -L_0x2cb0560/d .functor NOT 1, L_0x2cb0250, C4<0>, C4<0>, C4<0>; -L_0x2cb0560 .delay (10000,10000,10000) L_0x2cb0560/d; -v0x2b38870_0 .net "A", 0 0, L_0x2cb0cc0; 1 drivers -v0x2b38930_0 .net "AandB", 0 0, L_0x2cb0560; 1 drivers -v0x2b389b0_0 .net "AnandB", 0 0, L_0x2cb0250; 1 drivers -v0x2b38a60_0 .net "AndNandOut", 0 0, L_0x2cb09b0; 1 drivers -v0x2b38b40_0 .net "B", 0 0, L_0x2cb0de0; 1 drivers -v0x2b38bc0_0 .alias "Command", 2 0, v0x2bc67a0_0; -L_0x2cb0b80 .part v0x2bc78e0_0, 0, 1; -S_0x2b38320 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0x2b38230; - .timescale -9 -12; -L_0x2cb0690/d .functor NOT 1, L_0x2cb0b80, C4<0>, C4<0>, C4<0>; -L_0x2cb0690 .delay (10000,10000,10000) L_0x2cb0690/d; -L_0x2cb0750/d .functor AND 1, L_0x2cb0560, L_0x2cb0690, C4<1>, C4<1>; -L_0x2cb0750 .delay (20000,20000,20000) L_0x2cb0750/d; -L_0x2cb0860/d .functor AND 1, L_0x2cb0250, L_0x2cb0b80, C4<1>, C4<1>; -L_0x2cb0860 .delay (20000,20000,20000) L_0x2cb0860/d; -L_0x2cb09b0/d .functor OR 1, L_0x2cb0750, L_0x2cb0860, C4<0>, C4<0>; -L_0x2cb09b0 .delay (20000,20000,20000) L_0x2cb09b0/d; -v0x2b38410_0 .net "S", 0 0, L_0x2cb0b80; 1 drivers -v0x2b38490_0 .alias "in0", 0 0, v0x2b38930_0; -v0x2b38530_0 .alias "in1", 0 0, v0x2b389b0_0; -v0x2b385d0_0 .net "nS", 0 0, L_0x2cb0690; 1 drivers -v0x2b38650_0 .net "out0", 0 0, L_0x2cb0750; 1 drivers -v0x2b386f0_0 .net "out1", 0 0, L_0x2cb0860; 1 drivers -v0x2b387d0_0 .alias "outfinal", 0 0, v0x2b38a60_0; -S_0x2b37500 .scope generate, "andbits[6]" "andbits[6]" 3 169, 3 169, S_0x2ae82e0; - .timescale -9 -12; -P_0x2b375f8 .param/l "i" 3 169, +C4<0110>; -S_0x2b37670 .scope module, "attempt" "AndNand" 3 171, 3 48, S_0x2b37500; - .timescale -9 -12; -L_0x2cb0ed0/d .functor NAND 1, L_0x2cb1820, L_0x2cb18c0, C4<1>, C4<1>; -L_0x2cb0ed0 .delay (10000,10000,10000) L_0x2cb0ed0/d; -L_0x2cb1030/d .functor NOT 1, L_0x2cb0ed0, C4<0>, C4<0>, C4<0>; -L_0x2cb1030 .delay (10000,10000,10000) L_0x2cb1030/d; -v0x2b37cb0_0 .net "A", 0 0, L_0x2cb1820; 1 drivers -v0x2b37d70_0 .net "AandB", 0 0, L_0x2cb1030; 1 drivers -v0x2b37df0_0 .net "AnandB", 0 0, L_0x2cb0ed0; 1 drivers -v0x2b37ea0_0 .net "AndNandOut", 0 0, L_0x2cb1480; 1 drivers -v0x2b37f80_0 .net "B", 0 0, L_0x2cb18c0; 1 drivers -v0x2b38000_0 .alias "Command", 2 0, v0x2bc67a0_0; -L_0x2cb1650 .part v0x2bc78e0_0, 0, 1; -S_0x2b37760 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0x2b37670; - .timescale -9 -12; -L_0x2cb1160/d .functor NOT 1, L_0x2cb1650, C4<0>, C4<0>, C4<0>; -L_0x2cb1160 .delay (10000,10000,10000) L_0x2cb1160/d; -L_0x2cb1220/d .functor AND 1, L_0x2cb1030, L_0x2cb1160, C4<1>, C4<1>; -L_0x2cb1220 .delay (20000,20000,20000) L_0x2cb1220/d; -L_0x2cb1330/d .functor AND 1, L_0x2cb0ed0, L_0x2cb1650, C4<1>, C4<1>; -L_0x2cb1330 .delay (20000,20000,20000) L_0x2cb1330/d; -L_0x2cb1480/d .functor OR 1, L_0x2cb1220, L_0x2cb1330, C4<0>, C4<0>; -L_0x2cb1480 .delay (20000,20000,20000) L_0x2cb1480/d; -v0x2b37850_0 .net "S", 0 0, L_0x2cb1650; 1 drivers -v0x2b378d0_0 .alias "in0", 0 0, v0x2b37d70_0; -v0x2b37970_0 .alias "in1", 0 0, v0x2b37df0_0; -v0x2b37a10_0 .net "nS", 0 0, L_0x2cb1160; 1 drivers -v0x2b37a90_0 .net "out0", 0 0, L_0x2cb1220; 1 drivers -v0x2b37b30_0 .net "out1", 0 0, L_0x2cb1330; 1 drivers -v0x2b37c10_0 .alias "outfinal", 0 0, v0x2b37ea0_0; -S_0x2b36940 .scope generate, "andbits[7]" "andbits[7]" 3 169, 3 169, S_0x2ae82e0; - .timescale -9 -12; -P_0x2b36a38 .param/l "i" 3 169, +C4<0111>; -S_0x2b36ab0 .scope module, "attempt" "AndNand" 3 171, 3 48, S_0x2b36940; - .timescale -9 -12; -L_0x2cb1790/d .functor NAND 1, L_0x2cb2290, L_0x2cb19b0, C4<1>, C4<1>; -L_0x2cb1790 .delay (10000,10000,10000) L_0x2cb1790/d; -L_0x2cb1b30/d .functor NOT 1, L_0x2cb1790, C4<0>, C4<0>, C4<0>; -L_0x2cb1b30 .delay (10000,10000,10000) L_0x2cb1b30/d; -v0x2b370f0_0 .net "A", 0 0, L_0x2cb2290; 1 drivers -v0x2b371b0_0 .net "AandB", 0 0, L_0x2cb1b30; 1 drivers -v0x2b37230_0 .net "AnandB", 0 0, L_0x2cb1790; 1 drivers -v0x2b372e0_0 .net "AndNandOut", 0 0, L_0x2cb1f80; 1 drivers -v0x2b373c0_0 .net "B", 0 0, L_0x2cb19b0; 1 drivers -v0x2b37440_0 .alias "Command", 2 0, v0x2bc67a0_0; -L_0x2cb2150 .part v0x2bc78e0_0, 0, 1; -S_0x2b36ba0 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0x2b36ab0; - .timescale -9 -12; -L_0x2cb1c60/d .functor NOT 1, L_0x2cb2150, C4<0>, C4<0>, C4<0>; -L_0x2cb1c60 .delay (10000,10000,10000) L_0x2cb1c60/d; -L_0x2cb1d20/d .functor AND 1, L_0x2cb1b30, L_0x2cb1c60, C4<1>, C4<1>; -L_0x2cb1d20 .delay (20000,20000,20000) L_0x2cb1d20/d; -L_0x2cb1e30/d .functor AND 1, L_0x2cb1790, L_0x2cb2150, C4<1>, C4<1>; -L_0x2cb1e30 .delay (20000,20000,20000) L_0x2cb1e30/d; -L_0x2cb1f80/d .functor OR 1, L_0x2cb1d20, L_0x2cb1e30, C4<0>, C4<0>; -L_0x2cb1f80 .delay (20000,20000,20000) L_0x2cb1f80/d; -v0x2b36c90_0 .net "S", 0 0, L_0x2cb2150; 1 drivers -v0x2b36d10_0 .alias "in0", 0 0, v0x2b371b0_0; -v0x2b36db0_0 .alias "in1", 0 0, v0x2b37230_0; -v0x2b36e50_0 .net "nS", 0 0, L_0x2cb1c60; 1 drivers -v0x2b36ed0_0 .net "out0", 0 0, L_0x2cb1d20; 1 drivers -v0x2b36f70_0 .net "out1", 0 0, L_0x2cb1e30; 1 drivers -v0x2b37050_0 .alias "outfinal", 0 0, v0x2b372e0_0; -S_0x2b35d80 .scope generate, "andbits[8]" "andbits[8]" 3 169, 3 169, S_0x2ae82e0; - .timescale -9 -12; -P_0x2b35e78 .param/l "i" 3 169, +C4<01000>; -S_0x2b35ef0 .scope module, "attempt" "AndNand" 3 171, 3 48, S_0x2b35d80; - .timescale -9 -12; -L_0x2cb2430/d .functor NAND 1, L_0x2cb2330, L_0x2cb2db0, C4<1>, C4<1>; -L_0x2cb2430 .delay (10000,10000,10000) L_0x2cb2430/d; -L_0x2cb2590/d .functor NOT 1, L_0x2cb2430, C4<0>, C4<0>, C4<0>; -L_0x2cb2590 .delay (10000,10000,10000) L_0x2cb2590/d; -v0x2b36530_0 .net "A", 0 0, L_0x2cb2330; 1 drivers -v0x2b365f0_0 .net "AandB", 0 0, L_0x2cb2590; 1 drivers -v0x2b36670_0 .net "AnandB", 0 0, L_0x2cb2430; 1 drivers -v0x2b36720_0 .net "AndNandOut", 0 0, L_0x2cb29e0; 1 drivers -v0x2b36800_0 .net "B", 0 0, L_0x2cb2db0; 1 drivers -v0x2b36880_0 .alias "Command", 2 0, v0x2bc67a0_0; -L_0x2cb2bb0 .part v0x2bc78e0_0, 0, 1; -S_0x2b35fe0 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0x2b35ef0; - .timescale -9 -12; -L_0x2cb26c0/d .functor NOT 1, L_0x2cb2bb0, C4<0>, C4<0>, C4<0>; -L_0x2cb26c0 .delay (10000,10000,10000) L_0x2cb26c0/d; -L_0x2cb2780/d .functor AND 1, L_0x2cb2590, L_0x2cb26c0, C4<1>, C4<1>; -L_0x2cb2780 .delay (20000,20000,20000) L_0x2cb2780/d; -L_0x2cb2890/d .functor AND 1, L_0x2cb2430, L_0x2cb2bb0, C4<1>, C4<1>; -L_0x2cb2890 .delay (20000,20000,20000) L_0x2cb2890/d; -L_0x2cb29e0/d .functor OR 1, L_0x2cb2780, L_0x2cb2890, C4<0>, C4<0>; -L_0x2cb29e0 .delay (20000,20000,20000) L_0x2cb29e0/d; -v0x2b360d0_0 .net "S", 0 0, L_0x2cb2bb0; 1 drivers -v0x2b36150_0 .alias "in0", 0 0, v0x2b365f0_0; -v0x2b361f0_0 .alias "in1", 0 0, v0x2b36670_0; -v0x2b36290_0 .net "nS", 0 0, L_0x2cb26c0; 1 drivers -v0x2b36310_0 .net "out0", 0 0, L_0x2cb2780; 1 drivers -v0x2b363b0_0 .net "out1", 0 0, L_0x2cb2890; 1 drivers -v0x2b36490_0 .alias "outfinal", 0 0, v0x2b36720_0; -S_0x2b351c0 .scope generate, "andbits[9]" "andbits[9]" 3 169, 3 169, S_0x2ae82e0; - .timescale -9 -12; -P_0x2b352b8 .param/l "i" 3 169, +C4<01001>; -S_0x2b35330 .scope module, "attempt" "AndNand" 3 171, 3 48, S_0x2b351c0; - .timescale -9 -12; -L_0x2cb2cf0/d .functor NAND 1, L_0x2cb35e0, L_0x2cb2ea0, C4<1>, C4<1>; -L_0x2cb2cf0 .delay (10000,10000,10000) L_0x2cb2cf0/d; -L_0x2cb0d60/d .functor NOT 1, L_0x2cb2cf0, C4<0>, C4<0>, C4<0>; -L_0x2cb0d60 .delay (10000,10000,10000) L_0x2cb0d60/d; -v0x2b35970_0 .net "A", 0 0, L_0x2cb35e0; 1 drivers -v0x2b35a30_0 .net "AandB", 0 0, L_0x2cb0d60; 1 drivers -v0x2b35ab0_0 .net "AnandB", 0 0, L_0x2cb2cf0; 1 drivers -v0x2b35b60_0 .net "AndNandOut", 0 0, L_0x2cb3310; 1 drivers -v0x2b35c40_0 .net "B", 0 0, L_0x2cb2ea0; 1 drivers -v0x2b35cc0_0 .alias "Command", 2 0, v0x2bc67a0_0; -L_0x2cb34a0 .part v0x2bc78e0_0, 0, 1; -S_0x2b35420 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0x2b35330; - .timescale -9 -12; -L_0x2cb3050/d .functor NOT 1, L_0x2cb34a0, C4<0>, C4<0>, C4<0>; -L_0x2cb3050 .delay (10000,10000,10000) L_0x2cb3050/d; -L_0x2cb30f0/d .functor AND 1, L_0x2cb0d60, L_0x2cb3050, C4<1>, C4<1>; -L_0x2cb30f0 .delay (20000,20000,20000) L_0x2cb30f0/d; -L_0x2cb31e0/d .functor AND 1, L_0x2cb2cf0, L_0x2cb34a0, C4<1>, C4<1>; -L_0x2cb31e0 .delay (20000,20000,20000) L_0x2cb31e0/d; -L_0x2cb3310/d .functor OR 1, L_0x2cb30f0, L_0x2cb31e0, C4<0>, C4<0>; -L_0x2cb3310 .delay (20000,20000,20000) L_0x2cb3310/d; -v0x2b35510_0 .net "S", 0 0, L_0x2cb34a0; 1 drivers -v0x2b35590_0 .alias "in0", 0 0, v0x2b35a30_0; -v0x2b35630_0 .alias "in1", 0 0, v0x2b35ab0_0; -v0x2b356d0_0 .net "nS", 0 0, L_0x2cb3050; 1 drivers -v0x2b35750_0 .net "out0", 0 0, L_0x2cb30f0; 1 drivers -v0x2b357f0_0 .net "out1", 0 0, L_0x2cb31e0; 1 drivers -v0x2b358d0_0 .alias "outfinal", 0 0, v0x2b35b60_0; -S_0x2b34600 .scope generate, "andbits[10]" "andbits[10]" 3 169, 3 169, S_0x2ae82e0; - .timescale -9 -12; -P_0x2b346f8 .param/l "i" 3 169, +C4<01010>; -S_0x2b34770 .scope module, "attempt" "AndNand" 3 171, 3 48, S_0x2b34600; - .timescale -9 -12; -L_0x2cb37b0/d .functor NAND 1, L_0x2cb3680, L_0x2cb4060, C4<1>, C4<1>; -L_0x2cb37b0 .delay (10000,10000,10000) L_0x2cb37b0/d; -L_0x2cb38f0/d .functor NOT 1, L_0x2cb37b0, C4<0>, C4<0>, C4<0>; -L_0x2cb38f0 .delay (10000,10000,10000) L_0x2cb38f0/d; -v0x2b34db0_0 .net "A", 0 0, L_0x2cb3680; 1 drivers -v0x2b34e70_0 .net "AandB", 0 0, L_0x2cb38f0; 1 drivers -v0x2b34ef0_0 .net "AnandB", 0 0, L_0x2cb37b0; 1 drivers -v0x2b34fa0_0 .net "AndNandOut", 0 0, L_0x2cb3ca0; 1 drivers -v0x2b35080_0 .net "B", 0 0, L_0x2cb4060; 1 drivers -v0x2b35100_0 .alias "Command", 2 0, v0x2bc67a0_0; -L_0x2cb3e30 .part v0x2bc78e0_0, 0, 1; -S_0x2b34860 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0x2b34770; - .timescale -9 -12; -L_0x2cb39e0/d .functor NOT 1, L_0x2cb3e30, C4<0>, C4<0>, C4<0>; -L_0x2cb39e0 .delay (10000,10000,10000) L_0x2cb39e0/d; -L_0x2cb3a80/d .functor AND 1, L_0x2cb38f0, L_0x2cb39e0, C4<1>, C4<1>; -L_0x2cb3a80 .delay (20000,20000,20000) L_0x2cb3a80/d; -L_0x2cb3b70/d .functor AND 1, L_0x2cb37b0, L_0x2cb3e30, C4<1>, C4<1>; -L_0x2cb3b70 .delay (20000,20000,20000) L_0x2cb3b70/d; -L_0x2cb3ca0/d .functor OR 1, L_0x2cb3a80, L_0x2cb3b70, C4<0>, C4<0>; -L_0x2cb3ca0 .delay (20000,20000,20000) L_0x2cb3ca0/d; -v0x2b34950_0 .net "S", 0 0, L_0x2cb3e30; 1 drivers -v0x2b349d0_0 .alias "in0", 0 0, v0x2b34e70_0; -v0x2b34a70_0 .alias "in1", 0 0, v0x2b34ef0_0; -v0x2b34b10_0 .net "nS", 0 0, L_0x2cb39e0; 1 drivers -v0x2b34b90_0 .net "out0", 0 0, L_0x2cb3a80; 1 drivers -v0x2b34c30_0 .net "out1", 0 0, L_0x2cb3b70; 1 drivers -v0x2b34d10_0 .alias "outfinal", 0 0, v0x2b34fa0_0; -S_0x2b33a40 .scope generate, "andbits[11]" "andbits[11]" 3 169, 3 169, S_0x2ae82e0; - .timescale -9 -12; -P_0x2b33b38 .param/l "i" 3 169, +C4<01011>; -S_0x2b33bb0 .scope module, "attempt" "AndNand" 3 171, 3 48, S_0x2b33a40; - .timescale -9 -12; -L_0x2cb3f70/d .functor NAND 1, L_0x2cb4920, L_0x2cb4150, C4<1>, C4<1>; -L_0x2cb3f70 .delay (10000,10000,10000) L_0x2cb3f70/d; -L_0x2cb42a0/d .functor NOT 1, L_0x2cb3f70, C4<0>, C4<0>, C4<0>; -L_0x2cb42a0 .delay (10000,10000,10000) L_0x2cb42a0/d; -v0x2b341f0_0 .net "A", 0 0, L_0x2cb4920; 1 drivers -v0x2b342b0_0 .net "AandB", 0 0, L_0x2cb42a0; 1 drivers -v0x2b34330_0 .net "AnandB", 0 0, L_0x2cb3f70; 1 drivers -v0x2b343e0_0 .net "AndNandOut", 0 0, L_0x2cb4650; 1 drivers -v0x2b344c0_0 .net "B", 0 0, L_0x2cb4150; 1 drivers -v0x2b34540_0 .alias "Command", 2 0, v0x2bc67a0_0; -L_0x2cb47e0 .part v0x2bc78e0_0, 0, 1; -S_0x2b33ca0 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0x2b33bb0; - .timescale -9 -12; -L_0x2cb4390/d .functor NOT 1, L_0x2cb47e0, C4<0>, C4<0>, C4<0>; -L_0x2cb4390 .delay (10000,10000,10000) L_0x2cb4390/d; -L_0x2cb4430/d .functor AND 1, L_0x2cb42a0, L_0x2cb4390, C4<1>, C4<1>; -L_0x2cb4430 .delay (20000,20000,20000) L_0x2cb4430/d; -L_0x2cb4520/d .functor AND 1, L_0x2cb3f70, L_0x2cb47e0, C4<1>, C4<1>; -L_0x2cb4520 .delay (20000,20000,20000) L_0x2cb4520/d; -L_0x2cb4650/d .functor OR 1, L_0x2cb4430, L_0x2cb4520, C4<0>, C4<0>; -L_0x2cb4650 .delay (20000,20000,20000) L_0x2cb4650/d; -v0x2b33d90_0 .net "S", 0 0, L_0x2cb47e0; 1 drivers -v0x2b33e10_0 .alias "in0", 0 0, v0x2b342b0_0; -v0x2b33eb0_0 .alias "in1", 0 0, v0x2b34330_0; -v0x2b33f50_0 .net "nS", 0 0, L_0x2cb4390; 1 drivers -v0x2b33fd0_0 .net "out0", 0 0, L_0x2cb4430; 1 drivers -v0x2b34070_0 .net "out1", 0 0, L_0x2cb4520; 1 drivers -v0x2b34150_0 .alias "outfinal", 0 0, v0x2b343e0_0; -S_0x2b32e80 .scope generate, "andbits[12]" "andbits[12]" 3 169, 3 169, S_0x2ae82e0; - .timescale -9 -12; -P_0x2b32f78 .param/l "i" 3 169, +C4<01100>; -S_0x2b32ff0 .scope module, "attempt" "AndNand" 3 171, 3 48, S_0x2b32e80; - .timescale -9 -12; -L_0x2cb4ad0/d .functor NAND 1, L_0x2cb49c0, L_0x2cb54b0, C4<1>, C4<1>; -L_0x2cb4ad0 .delay (10000,10000,10000) L_0x2cb4ad0/d; -L_0x2cb4c30/d .functor NOT 1, L_0x2cb4ad0, C4<0>, C4<0>, C4<0>; -L_0x2cb4c30 .delay (10000,10000,10000) L_0x2cb4c30/d; -v0x2b33630_0 .net "A", 0 0, L_0x2cb49c0; 1 drivers -v0x2b336f0_0 .net "AandB", 0 0, L_0x2cb4c30; 1 drivers -v0x2b33770_0 .net "AnandB", 0 0, L_0x2cb4ad0; 1 drivers -v0x2b33820_0 .net "AndNandOut", 0 0, L_0x2cb5080; 1 drivers -v0x2b33900_0 .net "B", 0 0, L_0x2cb54b0; 1 drivers -v0x2b33980_0 .alias "Command", 2 0, v0x2bc67a0_0; -L_0x2cb5250 .part v0x2bc78e0_0, 0, 1; -S_0x2b330e0 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0x2b32ff0; - .timescale -9 -12; -L_0x2cb4d60/d .functor NOT 1, L_0x2cb5250, C4<0>, C4<0>, C4<0>; -L_0x2cb4d60 .delay (10000,10000,10000) L_0x2cb4d60/d; -L_0x2cb4e20/d .functor AND 1, L_0x2cb4c30, L_0x2cb4d60, C4<1>, C4<1>; -L_0x2cb4e20 .delay (20000,20000,20000) L_0x2cb4e20/d; -L_0x2cb4f30/d .functor AND 1, L_0x2cb4ad0, L_0x2cb5250, C4<1>, C4<1>; -L_0x2cb4f30 .delay (20000,20000,20000) L_0x2cb4f30/d; -L_0x2cb5080/d .functor OR 1, L_0x2cb4e20, L_0x2cb4f30, C4<0>, C4<0>; -L_0x2cb5080 .delay (20000,20000,20000) L_0x2cb5080/d; -v0x2b331d0_0 .net "S", 0 0, L_0x2cb5250; 1 drivers -v0x2b33250_0 .alias "in0", 0 0, v0x2b336f0_0; -v0x2b332f0_0 .alias "in1", 0 0, v0x2b33770_0; -v0x2b33390_0 .net "nS", 0 0, L_0x2cb4d60; 1 drivers -v0x2b33410_0 .net "out0", 0 0, L_0x2cb4e20; 1 drivers -v0x2b334b0_0 .net "out1", 0 0, L_0x2cb4f30; 1 drivers -v0x2b33590_0 .alias "outfinal", 0 0, v0x2b33820_0; -S_0x2b322d0 .scope generate, "andbits[13]" "andbits[13]" 3 169, 3 169, S_0x2ae82e0; - .timescale -9 -12; -P_0x2b323c8 .param/l "i" 3 169, +C4<01101>; -S_0x2b32440 .scope module, "attempt" "AndNand" 3 171, 3 48, S_0x2b322d0; - .timescale -9 -12; -L_0x2cb5390/d .functor NAND 1, L_0x2cb5e10, L_0x2cb5550, C4<1>, C4<1>; -L_0x2cb5390 .delay (10000,10000,10000) L_0x2cb5390/d; -L_0x2cb56d0/d .functor NOT 1, L_0x2cb5390, C4<0>, C4<0>, C4<0>; -L_0x2cb56d0 .delay (10000,10000,10000) L_0x2cb56d0/d; -v0x2b32aa0_0 .net "A", 0 0, L_0x2cb5e10; 1 drivers -v0x2b32b60_0 .net "AandB", 0 0, L_0x2cb56d0; 1 drivers -v0x2b32be0_0 .net "AnandB", 0 0, L_0x2cb5390; 1 drivers -v0x2b32c60_0 .net "AndNandOut", 0 0, L_0x2cb5b00; 1 drivers -v0x2b32d40_0 .net "B", 0 0, L_0x2cb5550; 1 drivers -v0x2b32dc0_0 .alias "Command", 2 0, v0x2bc67a0_0; -L_0x2cb5cd0 .part v0x2bc78e0_0, 0, 1; -S_0x2b32530 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0x2b32440; - .timescale -9 -12; -L_0x2cb57e0/d .functor NOT 1, L_0x2cb5cd0, C4<0>, C4<0>, C4<0>; -L_0x2cb57e0 .delay (10000,10000,10000) L_0x2cb57e0/d; -L_0x2cb58a0/d .functor AND 1, L_0x2cb56d0, L_0x2cb57e0, C4<1>, C4<1>; -L_0x2cb58a0 .delay (20000,20000,20000) L_0x2cb58a0/d; -L_0x2cb59b0/d .functor AND 1, L_0x2cb5390, L_0x2cb5cd0, C4<1>, C4<1>; -L_0x2cb59b0 .delay (20000,20000,20000) L_0x2cb59b0/d; -L_0x2cb5b00/d .functor OR 1, L_0x2cb58a0, L_0x2cb59b0, C4<0>, C4<0>; -L_0x2cb5b00 .delay (20000,20000,20000) L_0x2cb5b00/d; -v0x2b32620_0 .net "S", 0 0, L_0x2cb5cd0; 1 drivers -v0x2b326c0_0 .alias "in0", 0 0, v0x2b32b60_0; -v0x2b32760_0 .alias "in1", 0 0, v0x2b32be0_0; -v0x2b32800_0 .net "nS", 0 0, L_0x2cb57e0; 1 drivers -v0x2b32880_0 .net "out0", 0 0, L_0x2cb58a0; 1 drivers -v0x2b32920_0 .net "out1", 0 0, L_0x2cb59b0; 1 drivers -v0x2b32a00_0 .alias "outfinal", 0 0, v0x2b32c60_0; -S_0x2b31980 .scope generate, "andbits[14]" "andbits[14]" 3 169, 3 169, S_0x2ae82e0; - .timescale -9 -12; -P_0x2a16f78 .param/l "i" 3 169, +C4<01110>; -S_0x2b31a70 .scope module, "attempt" "AndNand" 3 171, 3 48, S_0x2b31980; - .timescale -9 -12; -L_0x2cb5ff0/d .functor NAND 1, L_0x2cb5eb0, L_0x2cb5f50, C4<1>, C4<1>; -L_0x2cb5ff0 .delay (10000,10000,10000) L_0x2cb5ff0/d; -L_0x2cb6130/d .functor NOT 1, L_0x2cb5ff0, C4<0>, C4<0>, C4<0>; -L_0x2cb6130 .delay (10000,10000,10000) L_0x2cb6130/d; -v0x2b31fd0_0 .net "A", 0 0, L_0x2cb5eb0; 1 drivers -v0x2b32050_0 .net "AandB", 0 0, L_0x2cb6130; 1 drivers -v0x2b320d0_0 .net "AnandB", 0 0, L_0x2cb5ff0; 1 drivers -v0x2b32150_0 .net "AndNandOut", 0 0, L_0x2cb65a0; 1 drivers -v0x2b321d0_0 .net "B", 0 0, L_0x2cb5f50; 1 drivers -v0x2b32250_0 .alias "Command", 2 0, v0x2bc67a0_0; -L_0x2cb6770 .part v0x2bc78e0_0, 0, 1; -S_0x2b31b60 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0x2b31a70; - .timescale -9 -12; -L_0x2cb6240/d .functor NOT 1, L_0x2cb6770, C4<0>, C4<0>, C4<0>; -L_0x2cb6240 .delay (10000,10000,10000) L_0x2cb6240/d; -L_0x2cb6320/d .functor AND 1, L_0x2cb6130, L_0x2cb6240, C4<1>, C4<1>; -L_0x2cb6320 .delay (20000,20000,20000) L_0x2cb6320/d; -L_0x2cb6430/d .functor AND 1, L_0x2cb5ff0, L_0x2cb6770, C4<1>, C4<1>; -L_0x2cb6430 .delay (20000,20000,20000) L_0x2cb6430/d; -L_0x2cb65a0/d .functor OR 1, L_0x2cb6320, L_0x2cb6430, C4<0>, C4<0>; -L_0x2cb65a0 .delay (20000,20000,20000) L_0x2cb65a0/d; -v0x2b31c50_0 .net "S", 0 0, L_0x2cb6770; 1 drivers -v0x2b31cd0_0 .alias "in0", 0 0, v0x2b32050_0; -v0x2b31d50_0 .alias "in1", 0 0, v0x2b320d0_0; -v0x2b31dd0_0 .net "nS", 0 0, L_0x2cb6240; 1 drivers -v0x2b31e50_0 .net "out0", 0 0, L_0x2cb6320; 1 drivers -v0x2b31ed0_0 .net "out1", 0 0, L_0x2cb6430; 1 drivers -v0x2b31f50_0 .alias "outfinal", 0 0, v0x2b32150_0; -S_0x2b31030 .scope generate, "andbits[15]" "andbits[15]" 3 169, 3 169, S_0x2ae82e0; - .timescale -9 -12; -P_0x29d1bf8 .param/l "i" 3 169, +C4<01111>; -S_0x2b31120 .scope module, "attempt" "AndNand" 3 171, 3 48, S_0x2b31030; - .timescale -9 -12; -L_0x2cb68b0/d .functor NAND 1, L_0x2cb7360, L_0x2cb6a50, C4<1>, C4<1>; -L_0x2cb68b0 .delay (10000,10000,10000) L_0x2cb68b0/d; -L_0x2cb6c00/d .functor NOT 1, L_0x2cb68b0, C4<0>, C4<0>, C4<0>; -L_0x2cb6c00 .delay (10000,10000,10000) L_0x2cb6c00/d; -v0x2b31680_0 .net "A", 0 0, L_0x2cb7360; 1 drivers -v0x2b31700_0 .net "AandB", 0 0, L_0x2cb6c00; 1 drivers -v0x2b31780_0 .net "AnandB", 0 0, L_0x2cb68b0; 1 drivers -v0x2b31800_0 .net "AndNandOut", 0 0, L_0x2cb7050; 1 drivers -v0x2b31880_0 .net "B", 0 0, L_0x2cb6a50; 1 drivers -v0x2b31900_0 .alias "Command", 2 0, v0x2bc67a0_0; -L_0x2cb7220 .part v0x2bc78e0_0, 0, 1; -S_0x2b31210 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0x2b31120; - .timescale -9 -12; -L_0x2cb6cf0/d .functor NOT 1, L_0x2cb7220, C4<0>, C4<0>, C4<0>; -L_0x2cb6cf0 .delay (10000,10000,10000) L_0x2cb6cf0/d; -L_0x2cb6dd0/d .functor AND 1, L_0x2cb6c00, L_0x2cb6cf0, C4<1>, C4<1>; -L_0x2cb6dd0 .delay (20000,20000,20000) L_0x2cb6dd0/d; -L_0x2cb6ee0/d .functor AND 1, L_0x2cb68b0, L_0x2cb7220, C4<1>, C4<1>; -L_0x2cb6ee0 .delay (20000,20000,20000) L_0x2cb6ee0/d; -L_0x2cb7050/d .functor OR 1, L_0x2cb6dd0, L_0x2cb6ee0, C4<0>, C4<0>; -L_0x2cb7050 .delay (20000,20000,20000) L_0x2cb7050/d; -v0x2b31300_0 .net "S", 0 0, L_0x2cb7220; 1 drivers -v0x2b31380_0 .alias "in0", 0 0, v0x2b31700_0; -v0x2b31400_0 .alias "in1", 0 0, v0x2b31780_0; -v0x2b31480_0 .net "nS", 0 0, L_0x2cb6cf0; 1 drivers -v0x2b31500_0 .net "out0", 0 0, L_0x2cb6dd0; 1 drivers -v0x2b31580_0 .net "out1", 0 0, L_0x2cb6ee0; 1 drivers -v0x2b31600_0 .alias "outfinal", 0 0, v0x2b31800_0; -S_0x2b306e0 .scope generate, "andbits[16]" "andbits[16]" 3 169, 3 169, S_0x2ae82e0; - .timescale -9 -12; -P_0x2996d58 .param/l "i" 3 169, +C4<010000>; -S_0x2b307d0 .scope module, "attempt" "AndNand" 3 171, 3 48, S_0x2b306e0; - .timescale -9 -12; -L_0x2cb6b40/d .functor NAND 1, L_0x2cb7400, L_0x2cb74a0, C4<1>, C4<1>; -L_0x2cb6b40 .delay (10000,10000,10000) L_0x2cb6b40/d; -L_0x2cb7670/d .functor NOT 1, L_0x2cb6b40, C4<0>, C4<0>, C4<0>; -L_0x2cb7670 .delay (10000,10000,10000) L_0x2cb7670/d; -v0x2b30d30_0 .net "A", 0 0, L_0x2cb7400; 1 drivers -v0x2b30db0_0 .net "AandB", 0 0, L_0x2cb7670; 1 drivers -v0x2b30e30_0 .net "AnandB", 0 0, L_0x2cb6b40; 1 drivers -v0x2b30eb0_0 .net "AndNandOut", 0 0, L_0x2cb7b00; 1 drivers -v0x2b30f30_0 .net "B", 0 0, L_0x2cb74a0; 1 drivers -v0x2b30fb0_0 .alias "Command", 2 0, v0x2bc67a0_0; -L_0x2cb7cd0 .part v0x2bc78e0_0, 0, 1; -S_0x2b308c0 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0x2b307d0; - .timescale -9 -12; -L_0x2cb77a0/d .functor NOT 1, L_0x2cb7cd0, C4<0>, C4<0>, C4<0>; -L_0x2cb77a0 .delay (10000,10000,10000) L_0x2cb77a0/d; -L_0x2cb7880/d .functor AND 1, L_0x2cb7670, L_0x2cb77a0, C4<1>, C4<1>; -L_0x2cb7880 .delay (20000,20000,20000) L_0x2cb7880/d; -L_0x2cb7990/d .functor AND 1, L_0x2cb6b40, L_0x2cb7cd0, C4<1>, C4<1>; -L_0x2cb7990 .delay (20000,20000,20000) L_0x2cb7990/d; -L_0x2cb7b00/d .functor OR 1, L_0x2cb7880, L_0x2cb7990, C4<0>, C4<0>; -L_0x2cb7b00 .delay (20000,20000,20000) L_0x2cb7b00/d; -v0x2b309b0_0 .net "S", 0 0, L_0x2cb7cd0; 1 drivers -v0x2b30a30_0 .alias "in0", 0 0, v0x2b30db0_0; -v0x2b30ab0_0 .alias "in1", 0 0, v0x2b30e30_0; -v0x2b30b30_0 .net "nS", 0 0, L_0x2cb77a0; 1 drivers -v0x2b30bb0_0 .net "out0", 0 0, L_0x2cb7880; 1 drivers -v0x2b30c30_0 .net "out1", 0 0, L_0x2cb7990; 1 drivers -v0x2b30cb0_0 .alias "outfinal", 0 0, v0x2b30eb0_0; -S_0x2b2fd90 .scope generate, "andbits[17]" "andbits[17]" 3 169, 3 169, S_0x2ae82e0; - .timescale -9 -12; -P_0x2a606b8 .param/l "i" 3 169, +C4<010001>; -S_0x2b2fe80 .scope module, "attempt" "AndNand" 3 171, 3 48, S_0x2b2fd90; - .timescale -9 -12; -L_0x2cb7e10/d .functor NAND 1, L_0x2cb88d0, L_0x2cb7fe0, C4<1>, C4<1>; -L_0x2cb7e10 .delay (10000,10000,10000) L_0x2cb7e10/d; -L_0x2cb8170/d .functor NOT 1, L_0x2cb7e10, C4<0>, C4<0>, C4<0>; -L_0x2cb8170 .delay (10000,10000,10000) L_0x2cb8170/d; -v0x2b303e0_0 .net "A", 0 0, L_0x2cb88d0; 1 drivers -v0x2b30460_0 .net "AandB", 0 0, L_0x2cb8170; 1 drivers -v0x2b304e0_0 .net "AnandB", 0 0, L_0x2cb7e10; 1 drivers -v0x2b30560_0 .net "AndNandOut", 0 0, L_0x2cb85c0; 1 drivers -v0x2b305e0_0 .net "B", 0 0, L_0x2cb7fe0; 1 drivers -v0x2b30660_0 .alias "Command", 2 0, v0x2bc67a0_0; -L_0x2cb8790 .part v0x2bc78e0_0, 0, 1; -S_0x2b2ff70 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0x2b2fe80; - .timescale -9 -12; -L_0x2cb8260/d .functor NOT 1, L_0x2cb8790, C4<0>, C4<0>, C4<0>; -L_0x2cb8260 .delay (10000,10000,10000) L_0x2cb8260/d; -L_0x2cb8340/d .functor AND 1, L_0x2cb8170, L_0x2cb8260, C4<1>, C4<1>; -L_0x2cb8340 .delay (20000,20000,20000) L_0x2cb8340/d; -L_0x2cb8450/d .functor AND 1, L_0x2cb7e10, L_0x2cb8790, C4<1>, C4<1>; -L_0x2cb8450 .delay (20000,20000,20000) L_0x2cb8450/d; -L_0x2cb85c0/d .functor OR 1, L_0x2cb8340, L_0x2cb8450, C4<0>, C4<0>; -L_0x2cb85c0 .delay (20000,20000,20000) L_0x2cb85c0/d; -v0x2b30060_0 .net "S", 0 0, L_0x2cb8790; 1 drivers -v0x2b300e0_0 .alias "in0", 0 0, v0x2b30460_0; -v0x2b30160_0 .alias "in1", 0 0, v0x2b304e0_0; -v0x2b301e0_0 .net "nS", 0 0, L_0x2cb8260; 1 drivers -v0x2b30260_0 .net "out0", 0 0, L_0x2cb8340; 1 drivers -v0x2b302e0_0 .net "out1", 0 0, L_0x2cb8450; 1 drivers -v0x2b30360_0 .alias "outfinal", 0 0, v0x2b30560_0; -S_0x2b2f440 .scope generate, "andbits[18]" "andbits[18]" 3 169, 3 169, S_0x2ae82e0; - .timescale -9 -12; -P_0x28b4f98 .param/l "i" 3 169, +C4<010010>; -S_0x2b2f530 .scope module, "attempt" "AndNand" 3 171, 3 48, S_0x2b2f440; - .timescale -9 -12; -L_0x2cb80d0/d .functor NAND 1, L_0x2cb8970, L_0x2cb8a10, C4<1>, C4<1>; -L_0x2cb80d0 .delay (10000,10000,10000) L_0x2cb80d0/d; -L_0x2cb8bf0/d .functor NOT 1, L_0x2cb80d0, C4<0>, C4<0>, C4<0>; -L_0x2cb8bf0 .delay (10000,10000,10000) L_0x2cb8bf0/d; -v0x2b2fa90_0 .net "A", 0 0, L_0x2cb8970; 1 drivers -v0x2b2fb10_0 .net "AandB", 0 0, L_0x2cb8bf0; 1 drivers -v0x2b2fb90_0 .net "AnandB", 0 0, L_0x2cb80d0; 1 drivers -v0x2b2fc10_0 .net "AndNandOut", 0 0, L_0x2cb9060; 1 drivers -v0x2b2fc90_0 .net "B", 0 0, L_0x2cb8a10; 1 drivers -v0x2b2fd10_0 .alias "Command", 2 0, v0x2bc67a0_0; -L_0x2cb9230 .part v0x2bc78e0_0, 0, 1; -S_0x2b2f620 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0x2b2f530; - .timescale -9 -12; -L_0x2cb8d00/d .functor NOT 1, L_0x2cb9230, C4<0>, C4<0>, C4<0>; -L_0x2cb8d00 .delay (10000,10000,10000) L_0x2cb8d00/d; -L_0x2cb8de0/d .functor AND 1, L_0x2cb8bf0, L_0x2cb8d00, C4<1>, C4<1>; -L_0x2cb8de0 .delay (20000,20000,20000) L_0x2cb8de0/d; -L_0x2cb8ef0/d .functor AND 1, L_0x2cb80d0, L_0x2cb9230, C4<1>, C4<1>; -L_0x2cb8ef0 .delay (20000,20000,20000) L_0x2cb8ef0/d; -L_0x2cb9060/d .functor OR 1, L_0x2cb8de0, L_0x2cb8ef0, C4<0>, C4<0>; -L_0x2cb9060 .delay (20000,20000,20000) L_0x2cb9060/d; -v0x2b2f710_0 .net "S", 0 0, L_0x2cb9230; 1 drivers -v0x2b2f790_0 .alias "in0", 0 0, v0x2b2fb10_0; -v0x2b2f810_0 .alias "in1", 0 0, v0x2b2fb90_0; -v0x2b2f890_0 .net "nS", 0 0, L_0x2cb8d00; 1 drivers -v0x2b2f910_0 .net "out0", 0 0, L_0x2cb8de0; 1 drivers -v0x2b2f990_0 .net "out1", 0 0, L_0x2cb8ef0; 1 drivers -v0x2b2fa10_0 .alias "outfinal", 0 0, v0x2b2fc10_0; -S_0x2b2eaf0 .scope generate, "andbits[19]" "andbits[19]" 3 169, 3 169, S_0x2ae82e0; - .timescale -9 -12; -P_0x28a9898 .param/l "i" 3 169, +C4<010011>; -S_0x2b2ebe0 .scope module, "attempt" "AndNand" 3 171, 3 48, S_0x2b2eaf0; - .timescale -9 -12; -L_0x2cb9530/d .functor NAND 1, L_0x2cb9e30, L_0x2cb9370, C4<1>, C4<1>; -L_0x2cb9530 .delay (10000,10000,10000) L_0x2cb9530/d; -L_0x2cb9690/d .functor NOT 1, L_0x2cb9530, C4<0>, C4<0>, C4<0>; -L_0x2cb9690 .delay (10000,10000,10000) L_0x2cb9690/d; -v0x2b2f140_0 .net "A", 0 0, L_0x2cb9e30; 1 drivers -v0x2b2f1c0_0 .net "AandB", 0 0, L_0x2cb9690; 1 drivers -v0x2b2f240_0 .net "AnandB", 0 0, L_0x2cb9530; 1 drivers -v0x2b2f2c0_0 .net "AndNandOut", 0 0, L_0x2cb9b20; 1 drivers -v0x2b2f340_0 .net "B", 0 0, L_0x2cb9370; 1 drivers -v0x2b2f3c0_0 .alias "Command", 2 0, v0x2bc67a0_0; -L_0x2cb9cf0 .part v0x2bc78e0_0, 0, 1; -S_0x2b2ecd0 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0x2b2ebe0; - .timescale -9 -12; -L_0x2cb97c0/d .functor NOT 1, L_0x2cb9cf0, C4<0>, C4<0>, C4<0>; -L_0x2cb97c0 .delay (10000,10000,10000) L_0x2cb97c0/d; -L_0x2cb9880/d .functor AND 1, L_0x2cb9690, L_0x2cb97c0, C4<1>, C4<1>; -L_0x2cb9880 .delay (20000,20000,20000) L_0x2cb9880/d; -L_0x2cb99b0/d .functor AND 1, L_0x2cb9530, L_0x2cb9cf0, C4<1>, C4<1>; -L_0x2cb99b0 .delay (20000,20000,20000) L_0x2cb99b0/d; -L_0x2cb9b20/d .functor OR 1, L_0x2cb9880, L_0x2cb99b0, C4<0>, C4<0>; -L_0x2cb9b20 .delay (20000,20000,20000) L_0x2cb9b20/d; -v0x2b2edc0_0 .net "S", 0 0, L_0x2cb9cf0; 1 drivers -v0x2b2ee40_0 .alias "in0", 0 0, v0x2b2f1c0_0; -v0x2b2eec0_0 .alias "in1", 0 0, v0x2b2f240_0; -v0x2b2ef40_0 .net "nS", 0 0, L_0x2cb97c0; 1 drivers -v0x2b2efc0_0 .net "out0", 0 0, L_0x2cb9880; 1 drivers -v0x2b2f040_0 .net "out1", 0 0, L_0x2cb99b0; 1 drivers -v0x2b2f0c0_0 .alias "outfinal", 0 0, v0x2b2f2c0_0; -S_0x2b2e1a0 .scope generate, "andbits[20]" "andbits[20]" 3 169, 3 169, S_0x2ae82e0; - .timescale -9 -12; -P_0x2927b78 .param/l "i" 3 169, +C4<010100>; -S_0x2b2e290 .scope module, "attempt" "AndNand" 3 171, 3 48, S_0x2b2e1a0; - .timescale -9 -12; -L_0x2cb9460/d .functor NAND 1, L_0x2cb9ed0, L_0x2cb9f70, C4<1>, C4<1>; -L_0x2cb9460 .delay (10000,10000,10000) L_0x2cb9460/d; -L_0x2cba130/d .functor NOT 1, L_0x2cb9460, C4<0>, C4<0>, C4<0>; -L_0x2cba130 .delay (10000,10000,10000) L_0x2cba130/d; -v0x2b2e7f0_0 .net "A", 0 0, L_0x2cb9ed0; 1 drivers -v0x2b2e870_0 .net "AandB", 0 0, L_0x2cba130; 1 drivers -v0x2b2e8f0_0 .net "AnandB", 0 0, L_0x2cb9460; 1 drivers -v0x2b2e970_0 .net "AndNandOut", 0 0, L_0x2cba580; 1 drivers -v0x2b2e9f0_0 .net "B", 0 0, L_0x2cb9f70; 1 drivers -v0x2b2ea70_0 .alias "Command", 2 0, v0x2bc67a0_0; -L_0x2cba750 .part v0x2bc78e0_0, 0, 1; -S_0x2b2e380 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0x2b2e290; - .timescale -9 -12; -L_0x2cba260/d .functor NOT 1, L_0x2cba750, C4<0>, C4<0>, C4<0>; -L_0x2cba260 .delay (10000,10000,10000) L_0x2cba260/d; -L_0x2cba320/d .functor AND 1, L_0x2cba130, L_0x2cba260, C4<1>, C4<1>; -L_0x2cba320 .delay (20000,20000,20000) L_0x2cba320/d; -L_0x2cba430/d .functor AND 1, L_0x2cb9460, L_0x2cba750, C4<1>, C4<1>; -L_0x2cba430 .delay (20000,20000,20000) L_0x2cba430/d; -L_0x2cba580/d .functor OR 1, L_0x2cba320, L_0x2cba430, C4<0>, C4<0>; -L_0x2cba580 .delay (20000,20000,20000) L_0x2cba580/d; -v0x2b2e470_0 .net "S", 0 0, L_0x2cba750; 1 drivers -v0x2b2e4f0_0 .alias "in0", 0 0, v0x2b2e870_0; -v0x2b2e570_0 .alias "in1", 0 0, v0x2b2e8f0_0; -v0x2b2e5f0_0 .net "nS", 0 0, L_0x2cba260; 1 drivers -v0x2b2e670_0 .net "out0", 0 0, L_0x2cba320; 1 drivers -v0x2b2e6f0_0 .net "out1", 0 0, L_0x2cba430; 1 drivers -v0x2b2e770_0 .alias "outfinal", 0 0, v0x2b2e970_0; -S_0x2b2d850 .scope generate, "andbits[21]" "andbits[21]" 3 169, 3 169, S_0x2ae82e0; - .timescale -9 -12; -P_0x2977a48 .param/l "i" 3 169, +C4<010101>; -S_0x2b2d940 .scope module, "attempt" "AndNand" 3 171, 3 48, S_0x2b2d850; - .timescale -9 -12; -L_0x2cbaa80/d .functor NAND 1, L_0x2cbb300, L_0x2cba890, C4<1>, C4<1>; -L_0x2cbaa80 .delay (10000,10000,10000) L_0x2cbaa80/d; -L_0x2cbabc0/d .functor NOT 1, L_0x2cbaa80, C4<0>, C4<0>, C4<0>; -L_0x2cbabc0 .delay (10000,10000,10000) L_0x2cbabc0/d; -v0x2b2dea0_0 .net "A", 0 0, L_0x2cbb300; 1 drivers -v0x2b2df20_0 .net "AandB", 0 0, L_0x2cbabc0; 1 drivers -v0x2b2dfa0_0 .net "AnandB", 0 0, L_0x2cbaa80; 1 drivers -v0x2b2e020_0 .net "AndNandOut", 0 0, L_0x2cbaff0; 1 drivers -v0x2b2e0a0_0 .net "B", 0 0, L_0x2cba890; 1 drivers -v0x2b2e120_0 .alias "Command", 2 0, v0x2bc67a0_0; -L_0x2cbb1c0 .part v0x2bc78e0_0, 0, 1; -S_0x2b2da30 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0x2b2d940; - .timescale -9 -12; -L_0x2cbacd0/d .functor NOT 1, L_0x2cbb1c0, C4<0>, C4<0>, C4<0>; -L_0x2cbacd0 .delay (10000,10000,10000) L_0x2cbacd0/d; -L_0x2cbad90/d .functor AND 1, L_0x2cbabc0, L_0x2cbacd0, C4<1>, C4<1>; -L_0x2cbad90 .delay (20000,20000,20000) L_0x2cbad90/d; -L_0x2cbaea0/d .functor AND 1, L_0x2cbaa80, L_0x2cbb1c0, C4<1>, C4<1>; -L_0x2cbaea0 .delay (20000,20000,20000) L_0x2cbaea0/d; -L_0x2cbaff0/d .functor OR 1, L_0x2cbad90, L_0x2cbaea0, C4<0>, C4<0>; -L_0x2cbaff0 .delay (20000,20000,20000) L_0x2cbaff0/d; -v0x2b2db20_0 .net "S", 0 0, L_0x2cbb1c0; 1 drivers -v0x2b2dba0_0 .alias "in0", 0 0, v0x2b2df20_0; -v0x2b2dc20_0 .alias "in1", 0 0, v0x2b2dfa0_0; -v0x2b2dca0_0 .net "nS", 0 0, L_0x2cbacd0; 1 drivers -v0x2b2dd20_0 .net "out0", 0 0, L_0x2cbad90; 1 drivers -v0x2b2dda0_0 .net "out1", 0 0, L_0x2cbaea0; 1 drivers -v0x2b2de20_0 .alias "outfinal", 0 0, v0x2b2e020_0; -S_0x2b2cf00 .scope generate, "andbits[22]" "andbits[22]" 3 169, 3 169, S_0x2ae82e0; - .timescale -9 -12; -P_0x29f7738 .param/l "i" 3 169, +C4<010110>; -S_0x2b2cff0 .scope module, "attempt" "AndNand" 3 171, 3 48, S_0x2b2cf00; - .timescale -9 -12; -L_0x2cba980/d .functor NAND 1, L_0x2cbb3a0, L_0x2cbb440, C4<1>, C4<1>; -L_0x2cba980 .delay (10000,10000,10000) L_0x2cba980/d; -L_0x2cbb630/d .functor NOT 1, L_0x2cba980, C4<0>, C4<0>, C4<0>; -L_0x2cbb630 .delay (10000,10000,10000) L_0x2cbb630/d; -v0x2b2d550_0 .net "A", 0 0, L_0x2cbb3a0; 1 drivers -v0x2b2d5d0_0 .net "AandB", 0 0, L_0x2cbb630; 1 drivers -v0x2b2d650_0 .net "AnandB", 0 0, L_0x2cba980; 1 drivers -v0x2b2d6d0_0 .net "AndNandOut", 0 0, L_0x2cbba60; 1 drivers -v0x2b2d750_0 .net "B", 0 0, L_0x2cbb440; 1 drivers -v0x2b2d7d0_0 .alias "Command", 2 0, v0x2bc67a0_0; -L_0x2cbbc30 .part v0x2bc78e0_0, 0, 1; -S_0x2b2d0e0 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0x2b2cff0; - .timescale -9 -12; -L_0x2cbb740/d .functor NOT 1, L_0x2cbbc30, C4<0>, C4<0>, C4<0>; -L_0x2cbb740 .delay (10000,10000,10000) L_0x2cbb740/d; -L_0x2cbb800/d .functor AND 1, L_0x2cbb630, L_0x2cbb740, C4<1>, C4<1>; -L_0x2cbb800 .delay (20000,20000,20000) L_0x2cbb800/d; -L_0x2cbb910/d .functor AND 1, L_0x2cba980, L_0x2cbbc30, C4<1>, C4<1>; -L_0x2cbb910 .delay (20000,20000,20000) L_0x2cbb910/d; -L_0x2cbba60/d .functor OR 1, L_0x2cbb800, L_0x2cbb910, C4<0>, C4<0>; -L_0x2cbba60 .delay (20000,20000,20000) L_0x2cbba60/d; -v0x2b2d1d0_0 .net "S", 0 0, L_0x2cbbc30; 1 drivers -v0x2b2d250_0 .alias "in0", 0 0, v0x2b2d5d0_0; -v0x2b2d2d0_0 .alias "in1", 0 0, v0x2b2d650_0; -v0x2b2d350_0 .net "nS", 0 0, L_0x2cbb740; 1 drivers -v0x2b2d3d0_0 .net "out0", 0 0, L_0x2cbb800; 1 drivers -v0x2b2d450_0 .net "out1", 0 0, L_0x2cbb910; 1 drivers -v0x2b2d4d0_0 .alias "outfinal", 0 0, v0x2b2d6d0_0; -S_0x2b2c5b0 .scope generate, "andbits[23]" "andbits[23]" 3 169, 3 169, S_0x2ae82e0; - .timescale -9 -12; -P_0x29e5958 .param/l "i" 3 169, +C4<010111>; -S_0x2b2c6a0 .scope module, "attempt" "AndNand" 3 171, 3 48, S_0x2b2c5b0; - .timescale -9 -12; -L_0x2cbb530/d .functor NAND 1, L_0x2cbc7f0, L_0x2cbbd70, C4<1>, C4<1>; -L_0x2cbb530 .delay (10000,10000,10000) L_0x2cbb530/d; -L_0x2cbc090/d .functor NOT 1, L_0x2cbb530, C4<0>, C4<0>, C4<0>; -L_0x2cbc090 .delay (10000,10000,10000) L_0x2cbc090/d; -v0x2b2cc00_0 .net "A", 0 0, L_0x2cbc7f0; 1 drivers -v0x2b2cc80_0 .net "AandB", 0 0, L_0x2cbc090; 1 drivers -v0x2b2cd00_0 .net "AnandB", 0 0, L_0x2cbb530; 1 drivers -v0x2b2cd80_0 .net "AndNandOut", 0 0, L_0x2cbc4e0; 1 drivers -v0x2b2ce00_0 .net "B", 0 0, L_0x2cbbd70; 1 drivers -v0x2b2ce80_0 .alias "Command", 2 0, v0x2bc67a0_0; -L_0x2cbc6b0 .part v0x2bc78e0_0, 0, 1; -S_0x2b2c790 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0x2b2c6a0; - .timescale -9 -12; -L_0x2cbc1c0/d .functor NOT 1, L_0x2cbc6b0, C4<0>, C4<0>, C4<0>; -L_0x2cbc1c0 .delay (10000,10000,10000) L_0x2cbc1c0/d; -L_0x2cbc280/d .functor AND 1, L_0x2cbc090, L_0x2cbc1c0, C4<1>, C4<1>; -L_0x2cbc280 .delay (20000,20000,20000) L_0x2cbc280/d; -L_0x2cbc390/d .functor AND 1, L_0x2cbb530, L_0x2cbc6b0, C4<1>, C4<1>; -L_0x2cbc390 .delay (20000,20000,20000) L_0x2cbc390/d; -L_0x2cbc4e0/d .functor OR 1, L_0x2cbc280, L_0x2cbc390, C4<0>, C4<0>; -L_0x2cbc4e0 .delay (20000,20000,20000) L_0x2cbc4e0/d; -v0x2b2c880_0 .net "S", 0 0, L_0x2cbc6b0; 1 drivers -v0x2b2c900_0 .alias "in0", 0 0, v0x2b2cc80_0; -v0x2b2c980_0 .alias "in1", 0 0, v0x2b2cd00_0; -v0x2b2ca00_0 .net "nS", 0 0, L_0x2cbc1c0; 1 drivers -v0x2b2ca80_0 .net "out0", 0 0, L_0x2cbc280; 1 drivers -v0x2b2cb00_0 .net "out1", 0 0, L_0x2cbc390; 1 drivers -v0x2b2cb80_0 .alias "outfinal", 0 0, v0x2b2cd80_0; -S_0x2b2bc60 .scope generate, "andbits[24]" "andbits[24]" 3 169, 3 169, S_0x2ae82e0; - .timescale -9 -12; -P_0x29bc5f8 .param/l "i" 3 169, +C4<011000>; -S_0x2b2bd50 .scope module, "attempt" "AndNand" 3 171, 3 48, S_0x2b2bc60; - .timescale -9 -12; -L_0x2cbbe60/d .functor NAND 1, L_0x2cbc890, L_0x2cbc930, C4<1>, C4<1>; -L_0x2cbbe60 .delay (10000,10000,10000) L_0x2cbbe60/d; -L_0x2cbcb10/d .functor NOT 1, L_0x2cbbe60, C4<0>, C4<0>, C4<0>; -L_0x2cbcb10 .delay (10000,10000,10000) L_0x2cbcb10/d; -v0x2b2c2b0_0 .net "A", 0 0, L_0x2cbc890; 1 drivers -v0x2b2c330_0 .net "AandB", 0 0, L_0x2cbcb10; 1 drivers -v0x2b2c3b0_0 .net "AnandB", 0 0, L_0x2cbbe60; 1 drivers -v0x2b2c430_0 .net "AndNandOut", 0 0, L_0x2cbcf40; 1 drivers -v0x2b2c4b0_0 .net "B", 0 0, L_0x2cbc930; 1 drivers -v0x2b2c530_0 .alias "Command", 2 0, v0x2bc67a0_0; -L_0x2cbd110 .part v0x2bc78e0_0, 0, 1; -S_0x2b2be40 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0x2b2bd50; - .timescale -9 -12; -L_0x2cbcc20/d .functor NOT 1, L_0x2cbd110, C4<0>, C4<0>, C4<0>; -L_0x2cbcc20 .delay (10000,10000,10000) L_0x2cbcc20/d; -L_0x2cbcce0/d .functor AND 1, L_0x2cbcb10, L_0x2cbcc20, C4<1>, C4<1>; -L_0x2cbcce0 .delay (20000,20000,20000) L_0x2cbcce0/d; -L_0x2cbcdf0/d .functor AND 1, L_0x2cbbe60, L_0x2cbd110, C4<1>, C4<1>; -L_0x2cbcdf0 .delay (20000,20000,20000) L_0x2cbcdf0/d; -L_0x2cbcf40/d .functor OR 1, L_0x2cbcce0, L_0x2cbcdf0, C4<0>, C4<0>; -L_0x2cbcf40 .delay (20000,20000,20000) L_0x2cbcf40/d; -v0x2b2bf30_0 .net "S", 0 0, L_0x2cbd110; 1 drivers -v0x2b2bfb0_0 .alias "in0", 0 0, v0x2b2c330_0; -v0x2b2c030_0 .alias "in1", 0 0, v0x2b2c3b0_0; -v0x2b2c0b0_0 .net "nS", 0 0, L_0x2cbcc20; 1 drivers -v0x2b2c130_0 .net "out0", 0 0, L_0x2cbcce0; 1 drivers -v0x2b2c1b0_0 .net "out1", 0 0, L_0x2cbcdf0; 1 drivers -v0x2b2c230_0 .alias "outfinal", 0 0, v0x2b2c430_0; -S_0x2b2b310 .scope generate, "andbits[25]" "andbits[25]" 3 169, 3 169, S_0x2ae82e0; - .timescale -9 -12; -P_0x299cb88 .param/l "i" 3 169, +C4<011001>; -S_0x2b2b400 .scope module, "attempt" "AndNand" 3 171, 3 48, S_0x2b2b310; - .timescale -9 -12; -L_0x2cbca20/d .functor NAND 1, L_0x2cbdcc0, L_0x2cbd250, C4<1>, C4<1>; -L_0x2cbca20 .delay (10000,10000,10000) L_0x2cbca20/d; -L_0x2cbd580/d .functor NOT 1, L_0x2cbca20, C4<0>, C4<0>, C4<0>; -L_0x2cbd580 .delay (10000,10000,10000) L_0x2cbd580/d; -v0x2b2b960_0 .net "A", 0 0, L_0x2cbdcc0; 1 drivers -v0x2b2b9e0_0 .net "AandB", 0 0, L_0x2cbd580; 1 drivers -v0x2b2ba60_0 .net "AnandB", 0 0, L_0x2cbca20; 1 drivers -v0x2b2bae0_0 .net "AndNandOut", 0 0, L_0x2cbd9b0; 1 drivers -v0x2b2bb60_0 .net "B", 0 0, L_0x2cbd250; 1 drivers -v0x2b2bbe0_0 .alias "Command", 2 0, v0x2bc67a0_0; -L_0x2cbdb80 .part v0x2bc78e0_0, 0, 1; -S_0x2b2b4f0 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0x2b2b400; - .timescale -9 -12; -L_0x2cbd690/d .functor NOT 1, L_0x2cbdb80, C4<0>, C4<0>, C4<0>; -L_0x2cbd690 .delay (10000,10000,10000) L_0x2cbd690/d; -L_0x2cbd750/d .functor AND 1, L_0x2cbd580, L_0x2cbd690, C4<1>, C4<1>; -L_0x2cbd750 .delay (20000,20000,20000) L_0x2cbd750/d; -L_0x2cbd860/d .functor AND 1, L_0x2cbca20, L_0x2cbdb80, C4<1>, C4<1>; -L_0x2cbd860 .delay (20000,20000,20000) L_0x2cbd860/d; -L_0x2cbd9b0/d .functor OR 1, L_0x2cbd750, L_0x2cbd860, C4<0>, C4<0>; -L_0x2cbd9b0 .delay (20000,20000,20000) L_0x2cbd9b0/d; -v0x2b2b5e0_0 .net "S", 0 0, L_0x2cbdb80; 1 drivers -v0x2b2b660_0 .alias "in0", 0 0, v0x2b2b9e0_0; -v0x2b2b6e0_0 .alias "in1", 0 0, v0x2b2ba60_0; -v0x2b2b760_0 .net "nS", 0 0, L_0x2cbd690; 1 drivers -v0x2b2b7e0_0 .net "out0", 0 0, L_0x2cbd750; 1 drivers -v0x2b2b860_0 .net "out1", 0 0, L_0x2cbd860; 1 drivers -v0x2b2b8e0_0 .alias "outfinal", 0 0, v0x2b2bae0_0; -S_0x2b2a9c0 .scope generate, "andbits[26]" "andbits[26]" 3 169, 3 169, S_0x2ae82e0; - .timescale -9 -12; -P_0x297c2c8 .param/l "i" 3 169, +C4<011010>; -S_0x2b2aab0 .scope module, "attempt" "AndNand" 3 171, 3 48, S_0x2b2a9c0; - .timescale -9 -12; -L_0x2cbd340/d .functor NAND 1, L_0x2cbdd60, L_0x2cbde00, C4<1>, C4<1>; -L_0x2cbd340 .delay (10000,10000,10000) L_0x2cbd340/d; -L_0x2cbdfc0/d .functor NOT 1, L_0x2cbd340, C4<0>, C4<0>, C4<0>; -L_0x2cbdfc0 .delay (10000,10000,10000) L_0x2cbdfc0/d; -v0x2b2b010_0 .net "A", 0 0, L_0x2cbdd60; 1 drivers -v0x2b2b090_0 .net "AandB", 0 0, L_0x2cbdfc0; 1 drivers -v0x2b2b110_0 .net "AnandB", 0 0, L_0x2cbd340; 1 drivers -v0x2b2b190_0 .net "AndNandOut", 0 0, L_0x2cbe410; 1 drivers -v0x2b2b210_0 .net "B", 0 0, L_0x2cbde00; 1 drivers -v0x2b2b290_0 .alias "Command", 2 0, v0x2bc67a0_0; -L_0x2cbe5a0 .part v0x2bc78e0_0, 0, 1; -S_0x2b2aba0 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0x2b2aab0; - .timescale -9 -12; -L_0x2cbe0f0/d .functor NOT 1, L_0x2cbe5a0, C4<0>, C4<0>, C4<0>; -L_0x2cbe0f0 .delay (10000,10000,10000) L_0x2cbe0f0/d; -L_0x2cbe1b0/d .functor AND 1, L_0x2cbdfc0, L_0x2cbe0f0, C4<1>, C4<1>; -L_0x2cbe1b0 .delay (20000,20000,20000) L_0x2cbe1b0/d; -L_0x2cbe2c0/d .functor AND 1, L_0x2cbd340, L_0x2cbe5a0, C4<1>, C4<1>; -L_0x2cbe2c0 .delay (20000,20000,20000) L_0x2cbe2c0/d; -L_0x2cbe410/d .functor OR 1, L_0x2cbe1b0, L_0x2cbe2c0, C4<0>, C4<0>; -L_0x2cbe410 .delay (20000,20000,20000) L_0x2cbe410/d; -v0x2b2ac90_0 .net "S", 0 0, L_0x2cbe5a0; 1 drivers -v0x2b2ad10_0 .alias "in0", 0 0, v0x2b2b090_0; -v0x2b2ad90_0 .alias "in1", 0 0, v0x2b2b110_0; -v0x2b2ae10_0 .net "nS", 0 0, L_0x2cbe0f0; 1 drivers -v0x2b2ae90_0 .net "out0", 0 0, L_0x2cbe1b0; 1 drivers -v0x2b2af10_0 .net "out1", 0 0, L_0x2cbe2c0; 1 drivers -v0x2b2af90_0 .alias "outfinal", 0 0, v0x2b2b190_0; -S_0x2b2a070 .scope generate, "andbits[27]" "andbits[27]" 3 169, 3 169, S_0x2ae82e0; - .timescale -9 -12; -P_0x270f708 .param/l "i" 3 169, +C4<011011>; -S_0x2b2a160 .scope module, "attempt" "AndNand" 3 171, 3 48, S_0x2b2a070; - .timescale -9 -12; -L_0x2cbdef0/d .functor NAND 1, L_0x2cbf1b0, L_0x2cbe6e0, C4<1>, C4<1>; -L_0x2cbdef0 .delay (10000,10000,10000) L_0x2cbdef0/d; -L_0x2cbea10/d .functor NOT 1, L_0x2cbdef0, C4<0>, C4<0>, C4<0>; -L_0x2cbea10 .delay (10000,10000,10000) L_0x2cbea10/d; -v0x2b2a6c0_0 .net "A", 0 0, L_0x2cbf1b0; 1 drivers -v0x2b2a740_0 .net "AandB", 0 0, L_0x2cbea10; 1 drivers -v0x2b2a7c0_0 .net "AnandB", 0 0, L_0x2cbdef0; 1 drivers -v0x2b2a840_0 .net "AndNandOut", 0 0, L_0x2cbeea0; 1 drivers -v0x2b2a8c0_0 .net "B", 0 0, L_0x2cbe6e0; 1 drivers -v0x2b2a940_0 .alias "Command", 2 0, v0x2bc67a0_0; -L_0x2cbf070 .part v0x2bc78e0_0, 0, 1; -S_0x2b2a250 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0x2b2a160; - .timescale -9 -12; -L_0x2cbeb40/d .functor NOT 1, L_0x2cbf070, C4<0>, C4<0>, C4<0>; -L_0x2cbeb40 .delay (10000,10000,10000) L_0x2cbeb40/d; -L_0x2cbec20/d .functor AND 1, L_0x2cbea10, L_0x2cbeb40, C4<1>, C4<1>; -L_0x2cbec20 .delay (20000,20000,20000) L_0x2cbec20/d; -L_0x2cbed50/d .functor AND 1, L_0x2cbdef0, L_0x2cbf070, C4<1>, C4<1>; -L_0x2cbed50 .delay (20000,20000,20000) L_0x2cbed50/d; -L_0x2cbeea0/d .functor OR 1, L_0x2cbec20, L_0x2cbed50, C4<0>, C4<0>; -L_0x2cbeea0 .delay (20000,20000,20000) L_0x2cbeea0/d; -v0x2b2a340_0 .net "S", 0 0, L_0x2cbf070; 1 drivers -v0x2b2a3c0_0 .alias "in0", 0 0, v0x2b2a740_0; -v0x2b2a440_0 .alias "in1", 0 0, v0x2b2a7c0_0; -v0x2b2a4c0_0 .net "nS", 0 0, L_0x2cbeb40; 1 drivers -v0x2b2a540_0 .net "out0", 0 0, L_0x2cbec20; 1 drivers -v0x2b2a5c0_0 .net "out1", 0 0, L_0x2cbed50; 1 drivers -v0x2b2a640_0 .alias "outfinal", 0 0, v0x2b2a840_0; -S_0x270f0b0 .scope generate, "andbits[28]" "andbits[28]" 3 169, 3 169, S_0x2ae82e0; - .timescale -9 -12; -P_0x270f1a8 .param/l "i" 3 169, +C4<011100>; -S_0x270f220 .scope module, "attempt" "AndNand" 3 171, 3 48, S_0x270f0b0; - .timescale -9 -12; -L_0x2cbe7d0/d .functor NAND 1, L_0x2cbf250, L_0x2cbf2f0, C4<1>, C4<1>; -L_0x2cbe7d0 .delay (10000,10000,10000) L_0x2cbe7d0/d; -L_0x2cbf4e0/d .functor NOT 1, L_0x2cbe7d0, C4<0>, C4<0>, C4<0>; -L_0x2cbf4e0 .delay (10000,10000,10000) L_0x2cbf4e0/d; -v0x2b29d70_0 .net "A", 0 0, L_0x2cbf250; 1 drivers -v0x2b29df0_0 .net "AandB", 0 0, L_0x2cbf4e0; 1 drivers -v0x2b29e70_0 .net "AnandB", 0 0, L_0x2cbe7d0; 1 drivers -v0x2b29ef0_0 .net "AndNandOut", 0 0, L_0x2cbf950; 1 drivers -v0x2b29f70_0 .net "B", 0 0, L_0x2cbf2f0; 1 drivers -v0x2b29ff0_0 .alias "Command", 2 0, v0x2bc67a0_0; -L_0x2cbfb20 .part v0x2bc78e0_0, 0, 1; -S_0x270f310 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0x270f220; - .timescale -9 -12; -L_0x2cbf610/d .functor NOT 1, L_0x2cbfb20, C4<0>, C4<0>, C4<0>; -L_0x2cbf610 .delay (10000,10000,10000) L_0x2cbf610/d; -L_0x2cbf6d0/d .functor AND 1, L_0x2cbf4e0, L_0x2cbf610, C4<1>, C4<1>; -L_0x2cbf6d0 .delay (20000,20000,20000) L_0x2cbf6d0/d; -L_0x2cbf7e0/d .functor AND 1, L_0x2cbe7d0, L_0x2cbfb20, C4<1>, C4<1>; -L_0x2cbf7e0 .delay (20000,20000,20000) L_0x2cbf7e0/d; -L_0x2cbf950/d .functor OR 1, L_0x2cbf6d0, L_0x2cbf7e0, C4<0>, C4<0>; -L_0x2cbf950 .delay (20000,20000,20000) L_0x2cbf950/d; -v0x270f400_0 .net "S", 0 0, L_0x2cbfb20; 1 drivers -v0x270f4a0_0 .alias "in0", 0 0, v0x2b29df0_0; -v0x270f540_0 .alias "in1", 0 0, v0x2b29e70_0; -v0x270f5e0_0 .net "nS", 0 0, L_0x2cbf610; 1 drivers -v0x270f660_0 .net "out0", 0 0, L_0x2cbf6d0; 1 drivers -v0x2b29c70_0 .net "out1", 0 0, L_0x2cbf7e0; 1 drivers -v0x2b29cf0_0 .alias "outfinal", 0 0, v0x2b29ef0_0; -S_0x2626690 .scope generate, "andbits[29]" "andbits[29]" 3 169, 3 169, S_0x2ae82e0; - .timescale -9 -12; -P_0x2626788 .param/l "i" 3 169, +C4<011101>; -S_0x2626800 .scope module, "attempt" "AndNand" 3 171, 3 48, S_0x2626690; - .timescale -9 -12; -L_0x2cbf3e0/d .functor NAND 1, L_0x2cc06e0, L_0x2cbfc60, C4<1>, C4<1>; -L_0x2cbf3e0 .delay (10000,10000,10000) L_0x2cbf3e0/d; -L_0x2cbffa0/d .functor NOT 1, L_0x2cbf3e0, C4<0>, C4<0>, C4<0>; -L_0x2cbffa0 .delay (10000,10000,10000) L_0x2cbffa0/d; -v0x2763de0_0 .net "A", 0 0, L_0x2cc06e0; 1 drivers -v0x2763ea0_0 .net "AandB", 0 0, L_0x2cbffa0; 1 drivers -v0x2763f20_0 .net "AnandB", 0 0, L_0x2cbf3e0; 1 drivers -v0x270eef0_0 .net "AndNandOut", 0 0, L_0x2cc03d0; 1 drivers -v0x270ef70_0 .net "B", 0 0, L_0x2cbfc60; 1 drivers -v0x270eff0_0 .alias "Command", 2 0, v0x2bc67a0_0; -L_0x2cc05a0 .part v0x2bc78e0_0, 0, 1; -S_0x26784a0 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0x2626800; - .timescale -9 -12; -L_0x2cc00b0/d .functor NOT 1, L_0x2cc05a0, C4<0>, C4<0>, C4<0>; -L_0x2cc00b0 .delay (10000,10000,10000) L_0x2cc00b0/d; -L_0x2cc0170/d .functor AND 1, L_0x2cbffa0, L_0x2cc00b0, C4<1>, C4<1>; -L_0x2cc0170 .delay (20000,20000,20000) L_0x2cc0170/d; -L_0x2cc0280/d .functor AND 1, L_0x2cbf3e0, L_0x2cc05a0, C4<1>, C4<1>; -L_0x2cc0280 .delay (20000,20000,20000) L_0x2cc0280/d; -L_0x2cc03d0/d .functor OR 1, L_0x2cc0170, L_0x2cc0280, C4<0>, C4<0>; -L_0x2cc03d0 .delay (20000,20000,20000) L_0x2cc03d0/d; -v0x2678590_0 .net "S", 0 0, L_0x2cc05a0; 1 drivers -v0x2678610_0 .alias "in0", 0 0, v0x2763ea0_0; -v0x26786b0_0 .alias "in1", 0 0, v0x2763f20_0; -v0x2763b40_0 .net "nS", 0 0, L_0x2cc00b0; 1 drivers -v0x2763bc0_0 .net "out0", 0 0, L_0x2cc0170; 1 drivers -v0x2763c60_0 .net "out1", 0 0, L_0x2cc0280; 1 drivers -v0x2763d40_0 .alias "outfinal", 0 0, v0x270eef0_0; -S_0x2670230 .scope generate, "andbits[30]" "andbits[30]" 3 169, 3 169, S_0x2ae82e0; - .timescale -9 -12; -P_0x2670328 .param/l "i" 3 169, +C4<011110>; -S_0x265c450 .scope module, "attempt" "AndNand" 3 171, 3 48, S_0x2670230; - .timescale -9 -12; -L_0x2cbfd50/d .functor NAND 1, L_0x2cc0780, L_0x2cc0820, C4<1>, C4<1>; -L_0x2cbfd50 .delay (10000,10000,10000) L_0x2cbfd50/d; -L_0x2cbfeb0/d .functor NOT 1, L_0x2cbfd50, C4<0>, C4<0>, C4<0>; -L_0x2cbfeb0 .delay (10000,10000,10000) L_0x2cbfeb0/d; -v0x2660790_0 .net "A", 0 0, L_0x2cc0780; 1 drivers -v0x2667ec0_0 .net "AandB", 0 0, L_0x2cbfeb0; 1 drivers -v0x2667f40_0 .net "AnandB", 0 0, L_0x2cbfd50; 1 drivers -v0x2667fc0_0 .net "AndNandOut", 0 0, L_0x2cc0e30; 1 drivers -v0x2668040_0 .net "B", 0 0, L_0x2cc0820; 1 drivers -v0x26680c0_0 .alias "Command", 2 0, v0x2bc67a0_0; -L_0x2cc1000 .part v0x2bc78e0_0, 0, 1; -S_0x265c540 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0x265c450; - .timescale -9 -12; -L_0x2cc0b10/d .functor NOT 1, L_0x2cc1000, C4<0>, C4<0>, C4<0>; -L_0x2cc0b10 .delay (10000,10000,10000) L_0x2cc0b10/d; -L_0x2cc0bd0/d .functor AND 1, L_0x2cbfeb0, L_0x2cc0b10, C4<1>, C4<1>; -L_0x2cc0bd0 .delay (20000,20000,20000) L_0x2cc0bd0/d; -L_0x2cc0ce0/d .functor AND 1, L_0x2cbfd50, L_0x2cc1000, C4<1>, C4<1>; -L_0x2cc0ce0 .delay (20000,20000,20000) L_0x2cc0ce0/d; -L_0x2cc0e30/d .functor OR 1, L_0x2cc0bd0, L_0x2cc0ce0, C4<0>, C4<0>; -L_0x2cc0e30 .delay (20000,20000,20000) L_0x2cc0e30/d; -v0x265c630_0 .net "S", 0 0, L_0x2cc1000; 1 drivers -v0x2662bb0_0 .alias "in0", 0 0, v0x2667ec0_0; -v0x2662c50_0 .alias "in1", 0 0, v0x2667f40_0; -v0x2662cf0_0 .net "nS", 0 0, L_0x2cc0b10; 1 drivers -v0x2662d70_0 .net "out0", 0 0, L_0x2cc0bd0; 1 drivers -v0x2660610_0 .net "out1", 0 0, L_0x2cc0ce0; 1 drivers -v0x26606f0_0 .alias "outfinal", 0 0, v0x2667fc0_0; -S_0x2ae83f0 .scope generate, "andbits[31]" "andbits[31]" 3 169, 3 169, S_0x2ae82e0; - .timescale -9 -12; -P_0x2ada678 .param/l "i" 3 169, +C4<011111>; -S_0x2aea7e0 .scope module, "attempt" "AndNand" 3 171, 3 48, S_0x2ae83f0; - .timescale -9 -12; -L_0x2cc0910/d .functor NAND 1, L_0x2c55e80, L_0x2cc1140, C4<1>, C4<1>; -L_0x2cc0910 .delay (10000,10000,10000) L_0x2cc0910/d; -L_0x2cc1470/d .functor NOT 1, L_0x2cc0910, C4<0>, C4<0>, C4<0>; -L_0x2cc1470 .delay (10000,10000,10000) L_0x2cc1470/d; -v0x2665cb0_0 .net "A", 0 0, L_0x2c55e80; 1 drivers -v0x2665d70_0 .net "AandB", 0 0, L_0x2cc1470; 1 drivers -v0x2665df0_0 .net "AnandB", 0 0, L_0x2cc0910; 1 drivers -v0x2665e70_0 .net "AndNandOut", 0 0, L_0x2cc18a0; 1 drivers -v0x2670130_0 .net "B", 0 0, L_0x2cc1140; 1 drivers -v0x26701b0_0 .alias "Command", 2 0, v0x2bc67a0_0; -L_0x2cc1a70 .part v0x2bc78e0_0, 0, 1; -S_0x2aea8d0 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0x2aea7e0; - .timescale -9 -12; -L_0x2cc1580/d .functor NOT 1, L_0x2cc1a70, C4<0>, C4<0>, C4<0>; -L_0x2cc1580 .delay (10000,10000,10000) L_0x2cc1580/d; -L_0x2cc1640/d .functor AND 1, L_0x2cc1470, L_0x2cc1580, C4<1>, C4<1>; -L_0x2cc1640 .delay (20000,20000,20000) L_0x2cc1640/d; -L_0x2cc1750/d .functor AND 1, L_0x2cc0910, L_0x2cc1a70, C4<1>, C4<1>; -L_0x2cc1750 .delay (20000,20000,20000) L_0x2cc1750/d; -L_0x2cc18a0/d .functor OR 1, L_0x2cc1640, L_0x2cc1750, C4<0>, C4<0>; -L_0x2cc18a0 .delay (20000,20000,20000) L_0x2cc18a0/d; -v0x266a3f0_0 .net "S", 0 0, L_0x2cc1a70; 1 drivers -v0x266a490_0 .alias "in0", 0 0, v0x2665d70_0; -v0x266a530_0 .alias "in1", 0 0, v0x2665df0_0; -v0x265f000_0 .net "nS", 0 0, L_0x2cc1580; 1 drivers -v0x265f080_0 .net "out0", 0 0, L_0x2cc1640; 1 drivers -v0x265f120_0 .net "out1", 0 0, L_0x2cc1750; 1 drivers -v0x265f1c0_0 .alias "outfinal", 0 0, v0x2665e70_0; -S_0x29fb160 .scope module, "trial2" "OrNorXor32" 3 281, 3 177, S_0x29738d0; - .timescale -9 -12; -P_0x29e8548 .param/l "size" 3 184, +C4<0100000>; -v0x2ae3a70_0 .alias "A", 31 0, v0x2bc6580_0; -v0x2ae5de0_0 .alias "B", 31 0, v0x2bc66a0_0; -v0x2ae5e80_0 .alias "Command", 2 0, v0x2bc67a0_0; -v0x2ae5f00_0 .alias "OrNorXorOut", 31 0, v0x2bc79e0_0; -L_0x2cc3e00 .part/pv L_0x2cc3bd0, 1, 1, 32; -L_0x2cc3ea0 .part v0x2bc7660_0, 1, 1; -L_0x2cc3f40 .part v0x2bc7860_0, 1, 1; -L_0x2cc4f00 .part/pv L_0x2cc4cd0, 2, 1, 32; -L_0x2cc4fa0 .part v0x2bc7660_0, 2, 1; -L_0x2cc5040 .part v0x2bc7860_0, 2, 1; -L_0x2cc6040 .part/pv L_0x2cc5e10, 3, 1, 32; -L_0x2cc60e0 .part v0x2bc7660_0, 3, 1; -L_0x2cc6180 .part v0x2bc7860_0, 3, 1; -L_0x2cc7210 .part/pv L_0x2cc6fa0, 4, 1, 32; -L_0x2cc7310 .part v0x2bc7660_0, 4, 1; -L_0x2cc73b0 .part v0x2bc7860_0, 4, 1; -L_0x2cc8510 .part/pv L_0x2cc82a0, 5, 1, 32; -L_0x2cc85b0 .part v0x2bc7660_0, 5, 1; -L_0x2cc86d0 .part v0x2bc7860_0, 5, 1; -L_0x2cc9870 .part/pv L_0x2cc9600, 6, 1, 32; -L_0x2cc99a0 .part v0x2bc7660_0, 6, 1; -L_0x2cc9a40 .part v0x2bc7860_0, 6, 1; -L_0x2ccac00 .part/pv L_0x2cca990, 7, 1, 32; -L_0x2ccaca0 .part v0x2bc7660_0, 7, 1; -L_0x2cc9ae0 .part v0x2bc7860_0, 7, 1; -L_0x2ccbef0 .part/pv L_0x2ccbc80, 8, 1, 32; -L_0x2ccad40 .part v0x2bc7660_0, 8, 1; -L_0x2ccc050 .part v0x2bc7860_0, 8, 1; -L_0x2ccd220 .part/pv L_0x2cccfb0, 9, 1, 32; -L_0x2ccd2c0 .part v0x2bc7660_0, 9, 1; -L_0x2ccc0f0 .part v0x2bc7860_0, 9, 1; -L_0x2cce530 .part/pv L_0x2cce2c0, 10, 1, 32; -L_0x2ccd360 .part v0x2bc7660_0, 10, 1; -L_0x2cce6c0 .part v0x2bc7860_0, 10, 1; -L_0x2ccf860 .part/pv L_0x2ccf5f0, 11, 1, 32; -L_0x2ccf900 .part v0x2bc7660_0, 11, 1; -L_0x2cce760 .part v0x2bc7860_0, 11, 1; -L_0x2cd0b90 .part/pv L_0x2cd0920, 12, 1, 32; -L_0x2ccf9a0 .part v0x2bc7660_0, 12, 1; -L_0x2cd0d50 .part v0x2bc7860_0, 12, 1; -L_0x2cd1ef0 .part/pv L_0x2cd1c80, 13, 1, 32; -L_0x2cd1f90 .part v0x2bc7660_0, 13, 1; -L_0x2cd0df0 .part v0x2bc7860_0, 13, 1; -L_0x2cd3290 .part/pv L_0x2cd3020, 14, 1, 32; -L_0x2cd2030 .part v0x2bc7660_0, 14, 1; -L_0x2cd20d0 .part v0x2bc7860_0, 14, 1; -L_0x2cd4490 .part/pv L_0x2cd4260, 15, 1, 32; -L_0x2cd4530 .part v0x2bc7660_0, 15, 1; -L_0x2cd3330 .part v0x2bc7860_0, 15, 1; -L_0x2cd55c0 .part/pv L_0x2cd5390, 16, 1, 32; -L_0x2cd45d0 .part v0x2bc7660_0, 16, 1; -L_0x2cd4670 .part v0x2bc7860_0, 16, 1; -L_0x2cd67d0 .part/pv L_0x2cd6560, 17, 1, 32; -L_0x2cd6870 .part v0x2bc7660_0, 17, 1; -L_0x2cd5660 .part v0x2bc7860_0, 17, 1; -L_0x2cd7b00 .part/pv L_0x2cd7890, 18, 1, 32; -L_0x2cd6910 .part v0x2bc7660_0, 18, 1; -L_0x2cd69b0 .part v0x2bc7860_0, 18, 1; -L_0x2cd8e40 .part/pv L_0x2cd8bd0, 19, 1, 32; -L_0x2cd8ee0 .part v0x2bc7660_0, 19, 1; -L_0x2cd7ba0 .part v0x2bc7860_0, 19, 1; -L_0x2cda180 .part/pv L_0x2cd9f10, 20, 1, 32; -L_0x2cd8f80 .part v0x2bc7660_0, 20, 1; -L_0x2cd9020 .part v0x2bc7860_0, 20, 1; -L_0x2cdb4d0 .part/pv L_0x2cdb260, 21, 1, 32; -L_0x2cdb570 .part v0x2bc7660_0, 21, 1; -L_0x2cda220 .part v0x2bc7860_0, 21, 1; -L_0x2cdc840 .part/pv L_0x2cdc5d0, 22, 1, 32; -L_0x2cdb610 .part v0x2bc7660_0, 22, 1; -L_0x2cdb6b0 .part v0x2bc7860_0, 22, 1; -L_0x2cddb80 .part/pv L_0x2cdd910, 23, 1, 32; -L_0x2cddc20 .part v0x2bc7660_0, 23, 1; -L_0x2cdc8e0 .part v0x2bc7860_0, 23, 1; -L_0x2cdeec0 .part/pv L_0x2cdec50, 24, 1, 32; -L_0x2cddcc0 .part v0x2bc7660_0, 24, 1; -L_0x2cddd60 .part v0x2bc7860_0, 24, 1; -L_0x2ce0200 .part/pv L_0x2cdff90, 25, 1, 32; -L_0x2ce02a0 .part v0x2bc7660_0, 25, 1; -L_0x2cdef60 .part v0x2bc7860_0, 25, 1; -L_0x2ce1570 .part/pv L_0x2ce1300, 26, 1, 32; -L_0x2ce0340 .part v0x2bc7660_0, 26, 1; -L_0x2ce03e0 .part v0x2bc7860_0, 26, 1; -L_0x2ce28c0 .part/pv L_0x2ce2650, 27, 1, 32; -L_0x2ce2960 .part v0x2bc7660_0, 27, 1; -L_0x2ce1610 .part v0x2bc7860_0, 27, 1; -L_0x2ce3c00 .part/pv L_0x2ce3990, 28, 1, 32; -L_0x2ce2a00 .part v0x2bc7660_0, 28, 1; -L_0x2ce2aa0 .part v0x2bc7860_0, 28, 1; -L_0x2ce4f00 .part/pv L_0x2ce4c90, 29, 1, 32; -L_0x2ce4fa0 .part v0x2bc7660_0, 29, 1; -L_0x2ce3ca0 .part v0x2bc7860_0, 29, 1; -L_0x2ce61f0 .part/pv L_0x2ce5f80, 30, 1, 32; -L_0x2ce5040 .part v0x2bc7660_0, 30, 1; -L_0x2ce50e0 .part v0x2bc7860_0, 30, 1; -L_0x2ce7520 .part/pv L_0x2ce72b0, 31, 1, 32; -L_0x2ce75c0 .part v0x2bc7660_0, 31, 1; -L_0x2ce6290 .part v0x2bc7860_0, 31, 1; -L_0x2ce8810 .part/pv L_0x2ce85a0, 0, 1, 32; -L_0x2ce7660 .part v0x2bc7660_0, 0, 1; -L_0x2ce7700 .part v0x2bc7860_0, 0, 1; -S_0x2acec70 .scope module, "attempt2" "OrNorXor" 3 192, 3 64, S_0x29fb160; - .timescale -9 -12; -L_0x2ce6330/d .functor NOR 1, L_0x2ce7660, L_0x2ce7700, C4<0>, C4<0>; -L_0x2ce6330 .delay (10000,10000,10000) L_0x2ce6330/d; -L_0x2ce6420/d .functor NOT 1, L_0x2ce6330, C4<0>, C4<0>, C4<0>; -L_0x2ce6420 .delay (10000,10000,10000) L_0x2ce6420/d; -L_0x2ce7950/d .functor NAND 1, L_0x2ce7660, L_0x2ce7700, C4<1>, C4<1>; -L_0x2ce7950 .delay (10000,10000,10000) L_0x2ce7950/d; -L_0x2ce7a90/d .functor NAND 1, L_0x2ce7950, L_0x2ce6420, C4<1>, C4<1>; -L_0x2ce7a90 .delay (10000,10000,10000) L_0x2ce7a90/d; -L_0x2ce7ba0/d .functor NOT 1, L_0x2ce7a90, C4<0>, C4<0>, C4<0>; -L_0x2ce7ba0 .delay (10000,10000,10000) L_0x2ce7ba0/d; -v0x2adeed0_0 .net "A", 0 0, L_0x2ce7660; 1 drivers -v0x2adef70_0 .net "AnandB", 0 0, L_0x2ce7950; 1 drivers -v0x2adf010_0 .net "AnorB", 0 0, L_0x2ce6330; 1 drivers -v0x2ae13e0_0 .net "AorB", 0 0, L_0x2ce6420; 1 drivers -v0x2ae1460_0 .net "AxorB", 0 0, L_0x2ce7ba0; 1 drivers -v0x2ae14e0_0 .net "B", 0 0, L_0x2ce7700; 1 drivers -v0x2ae1560_0 .alias "Command", 2 0, v0x2bc67a0_0; -v0x2ae38f0_0 .net "OrNorXorOut", 0 0, L_0x2ce85a0; 1 drivers -v0x2ae3970_0 .net "XorNor", 0 0, L_0x2ce8020; 1 drivers -v0x2ae39f0_0 .net "nXor", 0 0, L_0x2ce7a90; 1 drivers -L_0x2ce81a0 .part v0x2bc78e0_0, 2, 1; -L_0x2ce8770 .part v0x2bc78e0_0, 0, 1; -S_0x2ad7fa0 .scope module, "mux0" "TwoInMux" 3 83, 3 8, S_0x2acec70; - .timescale -9 -12; -L_0x2ce7d00/d .functor NOT 1, L_0x2ce81a0, C4<0>, C4<0>, C4<0>; -L_0x2ce7d00 .delay (10000,10000,10000) L_0x2ce7d00/d; -L_0x2ce7dc0/d .functor AND 1, L_0x2ce7ba0, L_0x2ce7d00, C4<1>, C4<1>; -L_0x2ce7dc0 .delay (20000,20000,20000) L_0x2ce7dc0/d; -L_0x2ce7ed0/d .functor AND 1, L_0x2ce6330, L_0x2ce81a0, C4<1>, C4<1>; -L_0x2ce7ed0 .delay (20000,20000,20000) L_0x2ce7ed0/d; -L_0x2ce8020/d .functor OR 1, L_0x2ce7dc0, L_0x2ce7ed0, C4<0>, C4<0>; -L_0x2ce8020 .delay (20000,20000,20000) L_0x2ce8020/d; -v0x2ad8090_0 .net "S", 0 0, L_0x2ce81a0; 1 drivers -v0x2ada4b0_0 .alias "in0", 0 0, v0x2ae1460_0; -v0x2ada550_0 .alias "in1", 0 0, v0x2adf010_0; -v0x2ada5f0_0 .net "nS", 0 0, L_0x2ce7d00; 1 drivers -v0x2adc9c0_0 .net "out0", 0 0, L_0x2ce7dc0; 1 drivers -v0x2adca60_0 .net "out1", 0 0, L_0x2ce7ed0; 1 drivers -v0x2adcb00_0 .alias "outfinal", 0 0, v0x2ae3970_0; -S_0x2ad1070 .scope module, "mux1" "TwoInMux" 3 84, 3 8, S_0x2acec70; - .timescale -9 -12; -L_0x2ce8240/d .functor NOT 1, L_0x2ce8770, C4<0>, C4<0>, C4<0>; -L_0x2ce8240 .delay (10000,10000,10000) L_0x2ce8240/d; -L_0x2ce8300/d .functor AND 1, L_0x2ce8020, L_0x2ce8240, C4<1>, C4<1>; -L_0x2ce8300 .delay (20000,20000,20000) L_0x2ce8300/d; -L_0x2ce8450/d .functor AND 1, L_0x2ce6420, L_0x2ce8770, C4<1>, C4<1>; -L_0x2ce8450 .delay (20000,20000,20000) L_0x2ce8450/d; -L_0x2ce85a0/d .functor OR 1, L_0x2ce8300, L_0x2ce8450, C4<0>, C4<0>; -L_0x2ce85a0 .delay (20000,20000,20000) L_0x2ce85a0/d; -v0x2ad1160_0 .net "S", 0 0, L_0x2ce8770; 1 drivers -v0x2ad3570_0 .alias "in0", 0 0, v0x2ae3970_0; -v0x2ad3610_0 .alias "in1", 0 0, v0x2ae13e0_0; -v0x2ad36b0_0 .net "nS", 0 0, L_0x2ce8240; 1 drivers -v0x2ad5a90_0 .net "out0", 0 0, L_0x2ce8300; 1 drivers -v0x2ad5b30_0 .net "out1", 0 0, L_0x2ce8450; 1 drivers -v0x2ad5bd0_0 .alias "outfinal", 0 0, v0x2ae38f0_0; -S_0x2ab9e20 .scope generate, "orbits[1]" "orbits[1]" 3 196, 3 196, S_0x29fb160; - .timescale -9 -12; -P_0x2aae6a8 .param/l "i" 3 196, +C4<01>; -S_0x2ab9f10 .scope module, "attempt" "OrNorXor" 3 198, 3 64, S_0x2ab9e20; - .timescale -9 -12; -L_0x2c56060/d .functor NOR 1, L_0x2cc3ea0, L_0x2cc3f40, C4<0>, C4<0>; -L_0x2c56060 .delay (10000,10000,10000) L_0x2c56060/d; -L_0x2cc3010/d .functor NOT 1, L_0x2c56060, C4<0>, C4<0>, C4<0>; -L_0x2cc3010 .delay (10000,10000,10000) L_0x2cc3010/d; -L_0x2cc30c0/d .functor NAND 1, L_0x2cc3ea0, L_0x2cc3f40, C4<1>, C4<1>; -L_0x2cc30c0 .delay (10000,10000,10000) L_0x2cc30c0/d; -L_0x2cc3200/d .functor NAND 1, L_0x2cc30c0, L_0x2cc3010, C4<1>, C4<1>; -L_0x2cc3200 .delay (10000,10000,10000) L_0x2cc3200/d; -L_0x2cc32f0/d .functor NOT 1, L_0x2cc3200, C4<0>, C4<0>, C4<0>; -L_0x2cc32f0 .delay (10000,10000,10000) L_0x2cc32f0/d; -v0x2ac7d90_0 .net "A", 0 0, L_0x2cc3ea0; 1 drivers -v0x2aca170_0 .net "AnandB", 0 0, L_0x2cc30c0; 1 drivers -v0x2aca210_0 .net "AnorB", 0 0, L_0x2c56060; 1 drivers -v0x2aca290_0 .net "AorB", 0 0, L_0x2cc3010; 1 drivers -v0x2acc670_0 .net "AxorB", 0 0, L_0x2cc32f0; 1 drivers -v0x2acc6f0_0 .net "B", 0 0, L_0x2cc3f40; 1 drivers -v0x2acc770_0 .alias "Command", 2 0, v0x2bc67a0_0; -v0x2acc7f0_0 .net "OrNorXorOut", 0 0, L_0x2cc3bd0; 1 drivers -v0x2aceb70_0 .net "XorNor", 0 0, L_0x2cc36f0; 1 drivers -v0x2acebf0_0 .net "nXor", 0 0, L_0x2cc3200; 1 drivers -L_0x2cc3830 .part v0x2bc78e0_0, 2, 1; -L_0x2cc3d60 .part v0x2bc78e0_0, 0, 1; -S_0x2ac3260 .scope module, "mux0" "TwoInMux" 3 83, 3 8, S_0x2ab9f10; - .timescale -9 -12; -L_0x2cc3430/d .functor NOT 1, L_0x2cc3830, C4<0>, C4<0>, C4<0>; -L_0x2cc3430 .delay (10000,10000,10000) L_0x2cc3430/d; -L_0x2cc34d0/d .functor AND 1, L_0x2cc32f0, L_0x2cc3430, C4<1>, C4<1>; -L_0x2cc34d0 .delay (20000,20000,20000) L_0x2cc34d0/d; -L_0x2cc35c0/d .functor AND 1, L_0x2c56060, L_0x2cc3830, C4<1>, C4<1>; -L_0x2cc35c0 .delay (20000,20000,20000) L_0x2cc35c0/d; -L_0x2cc36f0/d .functor OR 1, L_0x2cc34d0, L_0x2cc35c0, C4<0>, C4<0>; -L_0x2cc36f0 .delay (20000,20000,20000) L_0x2cc36f0/d; -v0x2ac3350_0 .net "S", 0 0, L_0x2cc3830; 1 drivers -v0x2ac0e90_0 .alias "in0", 0 0, v0x2acc670_0; -v0x2ac5770_0 .alias "in1", 0 0, v0x2aca210_0; -v0x2ac5810_0 .net "nS", 0 0, L_0x2cc3430; 1 drivers -v0x2ac5890_0 .net "out0", 0 0, L_0x2cc34d0; 1 drivers -v0x2ac7c70_0 .net "out1", 0 0, L_0x2cc35c0; 1 drivers -v0x2ac7d10_0 .alias "outfinal", 0 0, v0x2aceb70_0; -S_0x2abc330 .scope module, "mux1" "TwoInMux" 3 84, 3 8, S_0x2ab9f10; - .timescale -9 -12; -L_0x2cc38d0/d .functor NOT 1, L_0x2cc3d60, C4<0>, C4<0>, C4<0>; -L_0x2cc38d0 .delay (10000,10000,10000) L_0x2cc38d0/d; -L_0x2cc3970/d .functor AND 1, L_0x2cc36f0, L_0x2cc38d0, C4<1>, C4<1>; -L_0x2cc3970 .delay (20000,20000,20000) L_0x2cc3970/d; -L_0x2cc3aa0/d .functor AND 1, L_0x2cc3010, L_0x2cc3d60, C4<1>, C4<1>; -L_0x2cc3aa0 .delay (20000,20000,20000) L_0x2cc3aa0/d; -L_0x2cc3bd0/d .functor OR 1, L_0x2cc3970, L_0x2cc3aa0, C4<0>, C4<0>; -L_0x2cc3bd0 .delay (20000,20000,20000) L_0x2cc3bd0/d; -v0x2ab7a90_0 .net "S", 0 0, L_0x2cc3d60; 1 drivers -v0x2abc420_0 .alias "in0", 0 0, v0x2aceb70_0; -v0x2abe840_0 .alias "in1", 0 0, v0x2aca290_0; -v0x2abe8e0_0 .net "nS", 0 0, L_0x2cc38d0; 1 drivers -v0x2abe960_0 .net "out0", 0 0, L_0x2cc3970; 1 drivers -v0x2ac0d50_0 .net "out1", 0 0, L_0x2cc3aa0; 1 drivers -v0x2ac0df0_0 .alias "outfinal", 0 0, v0x2acc7f0_0; -S_0x2aecd60 .scope generate, "orbits[2]" "orbits[2]" 3 196, 3 196, S_0x29fb160; - .timescale -9 -12; -P_0x2a8a658 .param/l "i" 3 196, +C4<010>; -S_0x2aa5030 .scope module, "attempt" "OrNorXor" 3 198, 3 64, S_0x2aecd60; - .timescale -9 -12; -L_0x2cc3fe0/d .functor NOR 1, L_0x2cc4fa0, L_0x2cc5040, C4<0>, C4<0>; -L_0x2cc3fe0 .delay (10000,10000,10000) L_0x2cc3fe0/d; -L_0x2cc40d0/d .functor NOT 1, L_0x2cc3fe0, C4<0>, C4<0>, C4<0>; -L_0x2cc40d0 .delay (10000,10000,10000) L_0x2cc40d0/d; -L_0x2cc41c0/d .functor NAND 1, L_0x2cc4fa0, L_0x2cc5040, C4<1>, C4<1>; -L_0x2cc41c0 .delay (10000,10000,10000) L_0x2cc41c0/d; -L_0x2cc4300/d .functor NAND 1, L_0x2cc41c0, L_0x2cc40d0, C4<1>, C4<1>; -L_0x2cc4300 .delay (10000,10000,10000) L_0x2cc4300/d; -L_0x2cc43f0/d .functor NOT 1, L_0x2cc4300, C4<0>, C4<0>, C4<0>; -L_0x2cc43f0 .delay (10000,10000,10000) L_0x2cc43f0/d; -v0x2ab2ee0_0 .net "A", 0 0, L_0x2cc4fa0; 1 drivers -v0x2ab2f80_0 .net "AnandB", 0 0, L_0x2cc41c0; 1 drivers -v0x2ab3020_0 .net "AnorB", 0 0, L_0x2cc3fe0; 1 drivers -v0x2ab5400_0 .net "AorB", 0 0, L_0x2cc40d0; 1 drivers -v0x2ab5480_0 .net "AxorB", 0 0, L_0x2cc43f0; 1 drivers -v0x2ab5500_0 .net "B", 0 0, L_0x2cc5040; 1 drivers -v0x2ab5580_0 .alias "Command", 2 0, v0x2bc67a0_0; -v0x2ab7910_0 .net "OrNorXorOut", 0 0, L_0x2cc4cd0; 1 drivers -v0x2ab7990_0 .net "XorNor", 0 0, L_0x2cc47f0; 1 drivers -v0x2ab7a10_0 .net "nXor", 0 0, L_0x2cc4300; 1 drivers -L_0x2cc4930 .part v0x2bc78e0_0, 2, 1; -L_0x2cc4e60 .part v0x2bc78e0_0, 0, 1; -S_0x2aabfe0 .scope module, "mux0" "TwoInMux" 3 83, 3 8, S_0x2aa5030; - .timescale -9 -12; -L_0x2cc4530/d .functor NOT 1, L_0x2cc4930, C4<0>, C4<0>, C4<0>; -L_0x2cc4530 .delay (10000,10000,10000) L_0x2cc4530/d; -L_0x2cc45d0/d .functor AND 1, L_0x2cc43f0, L_0x2cc4530, C4<1>, C4<1>; -L_0x2cc45d0 .delay (20000,20000,20000) L_0x2cc45d0/d; -L_0x2cc46c0/d .functor AND 1, L_0x2cc3fe0, L_0x2cc4930, C4<1>, C4<1>; -L_0x2cc46c0 .delay (20000,20000,20000) L_0x2cc46c0/d; -L_0x2cc47f0/d .functor OR 1, L_0x2cc45d0, L_0x2cc46c0, C4<0>, C4<0>; -L_0x2cc47f0 .delay (20000,20000,20000) L_0x2cc47f0/d; -v0x2aac0d0_0 .net "S", 0 0, L_0x2cc4930; 1 drivers -v0x2aae4e0_0 .alias "in0", 0 0, v0x2ab5480_0; -v0x2aae580_0 .alias "in1", 0 0, v0x2ab3020_0; -v0x2aae620_0 .net "nS", 0 0, L_0x2cc4530; 1 drivers -v0x2ab09e0_0 .net "out0", 0 0, L_0x2cc45d0; 1 drivers -v0x2ab0a80_0 .net "out1", 0 0, L_0x2cc46c0; 1 drivers -v0x2ab0b20_0 .alias "outfinal", 0 0, v0x2ab7990_0; -S_0x2aa5120 .scope module, "mux1" "TwoInMux" 3 84, 3 8, S_0x2aa5030; - .timescale -9 -12; -L_0x2cc49d0/d .functor NOT 1, L_0x2cc4e60, C4<0>, C4<0>, C4<0>; -L_0x2cc49d0 .delay (10000,10000,10000) L_0x2cc49d0/d; -L_0x2cc4a70/d .functor AND 1, L_0x2cc47f0, L_0x2cc49d0, C4<1>, C4<1>; -L_0x2cc4a70 .delay (20000,20000,20000) L_0x2cc4a70/d; -L_0x2cc4ba0/d .functor AND 1, L_0x2cc40d0, L_0x2cc4e60, C4<1>, C4<1>; -L_0x2cc4ba0 .delay (20000,20000,20000) L_0x2cc4ba0/d; -L_0x2cc4cd0/d .functor OR 1, L_0x2cc4a70, L_0x2cc4ba0, C4<0>, C4<0>; -L_0x2cc4cd0 .delay (20000,20000,20000) L_0x2cc4cd0/d; -v0x2aece50_0 .net "S", 0 0, L_0x2cc4e60; 1 drivers -v0x2aa75e0_0 .alias "in0", 0 0, v0x2ab7990_0; -v0x2aa7660_0 .alias "in1", 0 0, v0x2ab5400_0; -v0x2aa7700_0 .net "nS", 0 0, L_0x2cc49d0; 1 drivers -v0x2aa9ae0_0 .net "out0", 0 0, L_0x2cc4a70; 1 drivers -v0x2aa9b80_0 .net "out1", 0 0, L_0x2cc4ba0; 1 drivers -v0x2aa9c20_0 .alias "outfinal", 0 0, v0x2ab7910_0; -S_0x2a86410 .scope generate, "orbits[3]" "orbits[3]" 3 196, 3 196, S_0x29fb160; - .timescale -9 -12; -P_0x2960cb8 .param/l "i" 3 196, +C4<011>; -S_0x2a87910 .scope module, "attempt" "OrNorXor" 3 198, 3 64, S_0x2a86410; - .timescale -9 -12; -L_0x2cc5120/d .functor NOR 1, L_0x2cc60e0, L_0x2cc6180, C4<0>, C4<0>; -L_0x2cc5120 .delay (10000,10000,10000) L_0x2cc5120/d; -L_0x2cc5210/d .functor NOT 1, L_0x2cc5120, C4<0>, C4<0>, C4<0>; -L_0x2cc5210 .delay (10000,10000,10000) L_0x2cc5210/d; -L_0x2cc5300/d .functor NAND 1, L_0x2cc60e0, L_0x2cc6180, C4<1>, C4<1>; -L_0x2cc5300 .delay (10000,10000,10000) L_0x2cc5300/d; -L_0x2cc5440/d .functor NAND 1, L_0x2cc5300, L_0x2cc5210, C4<1>, C4<1>; -L_0x2cc5440 .delay (10000,10000,10000) L_0x2cc5440/d; -L_0x2cc5530/d .functor NOT 1, L_0x2cc5440, C4<0>, C4<0>, C4<0>; -L_0x2cc5530 .delay (10000,10000,10000) L_0x2cc5530/d; -v0x2a8fc10_0 .net "A", 0 0, L_0x2cc60e0; 1 drivers -v0x2a8fcb0_0 .net "AnandB", 0 0, L_0x2cc5300; 1 drivers -v0x2a91110_0 .net "AnorB", 0 0, L_0x2cc5120; 1 drivers -v0x2a91190_0 .net "AorB", 0 0, L_0x2cc5210; 1 drivers -v0x2a91210_0 .net "AxorB", 0 0, L_0x2cc5530; 1 drivers -v0x2a91290_0 .net "B", 0 0, L_0x2cc6180; 1 drivers -v0x2a92710_0 .alias "Command", 2 0, v0x2bc67a0_0; -v0x2a92790_0 .net "OrNorXorOut", 0 0, L_0x2cc5e10; 1 drivers -v0x2a92810_0 .net "XorNor", 0 0, L_0x2cc5930; 1 drivers -v0x2aecce0_0 .net "nXor", 0 0, L_0x2cc5440; 1 drivers -L_0x2cc5a70 .part v0x2bc78e0_0, 2, 1; -L_0x2cc5fa0 .part v0x2bc78e0_0, 0, 1; -S_0x2a8bab0 .scope module, "mux0" "TwoInMux" 3 83, 3 8, S_0x2a87910; - .timescale -9 -12; -L_0x2cc5670/d .functor NOT 1, L_0x2cc5a70, C4<0>, C4<0>, C4<0>; -L_0x2cc5670 .delay (10000,10000,10000) L_0x2cc5670/d; -L_0x2cc5710/d .functor AND 1, L_0x2cc5530, L_0x2cc5670, C4<1>, C4<1>; -L_0x2cc5710 .delay (20000,20000,20000) L_0x2cc5710/d; -L_0x2cc5800/d .functor AND 1, L_0x2cc5120, L_0x2cc5a70, C4<1>, C4<1>; -L_0x2cc5800 .delay (20000,20000,20000) L_0x2cc5800/d; -L_0x2cc5930/d .functor OR 1, L_0x2cc5710, L_0x2cc5800, C4<0>, C4<0>; -L_0x2cc5930 .delay (20000,20000,20000) L_0x2cc5930/d; -v0x2a8d010_0 .net "S", 0 0, L_0x2cc5a70; 1 drivers -v0x2a8d0d0_0 .alias "in0", 0 0, v0x2a91210_0; -v0x2a8d170_0 .alias "in1", 0 0, v0x2a91110_0; -v0x2a8e590_0 .net "nS", 0 0, L_0x2cc5670; 1 drivers -v0x2a8e610_0 .net "out0", 0 0, L_0x2cc5710; 1 drivers -v0x2a8e6b0_0 .net "out1", 0 0, L_0x2cc5800; 1 drivers -v0x2a8fb90_0 .alias "outfinal", 0 0, v0x2a92810_0; -S_0x2a87a00 .scope module, "mux1" "TwoInMux" 3 84, 3 8, S_0x2a87910; - .timescale -9 -12; -L_0x2cc5b10/d .functor NOT 1, L_0x2cc5fa0, C4<0>, C4<0>, C4<0>; -L_0x2cc5b10 .delay (10000,10000,10000) L_0x2cc5b10/d; -L_0x2cc5bb0/d .functor AND 1, L_0x2cc5930, L_0x2cc5b10, C4<1>, C4<1>; -L_0x2cc5bb0 .delay (20000,20000,20000) L_0x2cc5bb0/d; -L_0x2cc5ce0/d .functor AND 1, L_0x2cc5210, L_0x2cc5fa0, C4<1>, C4<1>; -L_0x2cc5ce0 .delay (20000,20000,20000) L_0x2cc5ce0/d; -L_0x2cc5e10/d .functor OR 1, L_0x2cc5bb0, L_0x2cc5ce0, C4<0>, C4<0>; -L_0x2cc5e10 .delay (20000,20000,20000) L_0x2cc5e10/d; -v0x2a88e90_0 .net "S", 0 0, L_0x2cc5fa0; 1 drivers -v0x2a88f10_0 .alias "in0", 0 0, v0x2a92810_0; -v0x2a88fb0_0 .alias "in1", 0 0, v0x2a91190_0; -v0x2a8a490_0 .net "nS", 0 0, L_0x2cc5b10; 1 drivers -v0x2a8a510_0 .net "out0", 0 0, L_0x2cc5bb0; 1 drivers -v0x2a8a5b0_0 .net "out1", 0 0, L_0x2cc5ce0; 1 drivers -v0x2a8ba10_0 .alias "outfinal", 0 0, v0x2a92790_0; -S_0x2959d80 .scope generate, "orbits[4]" "orbits[4]" 3 196, 3 196, S_0x29fb160; - .timescale -9 -12; -P_0x294e968 .param/l "i" 3 196, +C4<0100>; -S_0x2959e70 .scope module, "attempt" "OrNorXor" 3 198, 3 64, S_0x2959d80; - .timescale -9 -12; -L_0x2cc6220/d .functor NOR 1, L_0x2cc7310, L_0x2cc73b0, C4<0>, C4<0>; -L_0x2cc6220 .delay (10000,10000,10000) L_0x2cc6220/d; -L_0x2cc6320/d .functor NOT 1, L_0x2cc6220, C4<0>, C4<0>, C4<0>; -L_0x2cc6320 .delay (10000,10000,10000) L_0x2cc6320/d; -L_0x2cc6410/d .functor NAND 1, L_0x2cc7310, L_0x2cc73b0, C4<1>, C4<1>; -L_0x2cc6410 .delay (10000,10000,10000) L_0x2cc6410/d; -L_0x2cc6550/d .functor NAND 1, L_0x2cc6410, L_0x2cc6320, C4<1>, C4<1>; -L_0x2cc6550 .delay (10000,10000,10000) L_0x2cc6550/d; -L_0x2cc6640/d .functor NOT 1, L_0x2cc6550, C4<0>, C4<0>, C4<0>; -L_0x2cc6640 .delay (10000,10000,10000) L_0x2cc6640/d; -v0x2a822f0_0 .net "A", 0 0, L_0x2cc7310; 1 drivers -v0x2a83790_0 .net "AnandB", 0 0, L_0x2cc6410; 1 drivers -v0x2a83830_0 .net "AnorB", 0 0, L_0x2cc6220; 1 drivers -v0x2a838b0_0 .net "AorB", 0 0, L_0x2cc6320; 1 drivers -v0x2a84d90_0 .net "AxorB", 0 0, L_0x2cc6640; 1 drivers -v0x2a84e10_0 .net "B", 0 0, L_0x2cc73b0; 1 drivers -v0x2a84e90_0 .alias "Command", 2 0, v0x2bc67a0_0; -v0x2a84f10_0 .net "OrNorXorOut", 0 0, L_0x2cc6fa0; 1 drivers -v0x2a86310_0 .net "XorNor", 0 0, L_0x2cc6a40; 1 drivers -v0x2a86390_0 .net "nXor", 0 0, L_0x2cc6550; 1 drivers -L_0x2cc6ba0 .part v0x2bc78e0_0, 2, 1; -L_0x2cc7170 .part v0x2bc78e0_0, 0, 1; -S_0x2a789d0 .scope module, "mux0" "TwoInMux" 3 83, 3 8, S_0x2959e70; - .timescale -9 -12; -L_0x2cc6780/d .functor NOT 1, L_0x2cc6ba0, C4<0>, C4<0>, C4<0>; -L_0x2cc6780 .delay (10000,10000,10000) L_0x2cc6780/d; -L_0x2cc6820/d .functor AND 1, L_0x2cc6640, L_0x2cc6780, C4<1>, C4<1>; -L_0x2cc6820 .delay (20000,20000,20000) L_0x2cc6820/d; -L_0x2cc6910/d .functor AND 1, L_0x2cc6220, L_0x2cc6ba0, C4<1>, C4<1>; -L_0x2cc6910 .delay (20000,20000,20000) L_0x2cc6910/d; -L_0x2cc6a40/d .functor OR 1, L_0x2cc6820, L_0x2cc6910, C4<0>, C4<0>; -L_0x2cc6a40 .delay (20000,20000,20000) L_0x2cc6a40/d; -v0x2a78ac0_0 .net "S", 0 0, L_0x2cc6ba0; 1 drivers -v0x2960c30_0 .alias "in0", 0 0, v0x2a84d90_0; -v0x2a7a020_0 .alias "in1", 0 0, v0x2a83830_0; -v0x2a7a0c0_0 .net "nS", 0 0, L_0x2cc6780; 1 drivers -v0x2a7a140_0 .net "out0", 0 0, L_0x2cc6820; 1 drivers -v0x2a821d0_0 .net "out1", 0 0, L_0x2cc6910; 1 drivers -v0x2a82270_0 .alias "outfinal", 0 0, v0x2a86310_0; -S_0x295c1e0 .scope module, "mux1" "TwoInMux" 3 84, 3 8, S_0x2959e70; - .timescale -9 -12; -L_0x2cc6c40/d .functor NOT 1, L_0x2cc7170, C4<0>, C4<0>, C4<0>; -L_0x2cc6c40 .delay (10000,10000,10000) L_0x2cc6c40/d; -L_0x2cc6d00/d .functor AND 1, L_0x2cc6a40, L_0x2cc6c40, C4<1>, C4<1>; -L_0x2cc6d00 .delay (20000,20000,20000) L_0x2cc6d00/d; -L_0x2cc6e50/d .functor AND 1, L_0x2cc6320, L_0x2cc7170, C4<1>, C4<1>; -L_0x2cc6e50 .delay (20000,20000,20000) L_0x2cc6e50/d; -L_0x2cc6fa0/d .functor OR 1, L_0x2cc6d00, L_0x2cc6e50, C4<0>, C4<0>; -L_0x2cc6fa0 .delay (20000,20000,20000) L_0x2cc6fa0/d; -v0x2957aa0_0 .net "S", 0 0, L_0x2cc7170; 1 drivers -v0x295c2d0_0 .alias "in0", 0 0, v0x2a86310_0; -v0x295e640_0 .alias "in1", 0 0, v0x2a838b0_0; -v0x295e6e0_0 .net "nS", 0 0, L_0x2cc6c40; 1 drivers -v0x295e760_0 .net "out0", 0 0, L_0x2cc6d00; 1 drivers -v0x2960af0_0 .net "out1", 0 0, L_0x2cc6e50; 1 drivers -v0x2960b90_0 .alias "outfinal", 0 0, v0x2a84f10_0; -S_0x29430b0 .scope generate, "orbits[5]" "orbits[5]" 3 196, 3 196, S_0x29fb160; - .timescale -9 -12; -P_0x2933208 .param/l "i" 3 196, +C4<0101>; -S_0x29454e0 .scope module, "attempt" "OrNorXor" 3 198, 3 64, S_0x29430b0; - .timescale -9 -12; -L_0x2cc72b0/d .functor NOR 1, L_0x2cc85b0, L_0x2cc86d0, C4<0>, C4<0>; -L_0x2cc72b0 .delay (10000,10000,10000) L_0x2cc72b0/d; -L_0x2cc7500/d .functor NOT 1, L_0x2cc72b0, C4<0>, C4<0>, C4<0>; -L_0x2cc7500 .delay (10000,10000,10000) L_0x2cc7500/d; -L_0x2cc7630/d .functor NAND 1, L_0x2cc85b0, L_0x2cc86d0, C4<1>, C4<1>; -L_0x2cc7630 .delay (10000,10000,10000) L_0x2cc7630/d; -L_0x2cc7790/d .functor NAND 1, L_0x2cc7630, L_0x2cc7500, C4<1>, C4<1>; -L_0x2cc7790 .delay (10000,10000,10000) L_0x2cc7790/d; -L_0x2cc78a0/d .functor NOT 1, L_0x2cc7790, C4<0>, C4<0>, C4<0>; -L_0x2cc78a0 .delay (10000,10000,10000) L_0x2cc78a0/d; -v0x2953060_0 .net "A", 0 0, L_0x2cc85b0; 1 drivers -v0x2953100_0 .net "AnandB", 0 0, L_0x2cc7630; 1 drivers -v0x29531a0_0 .net "AnorB", 0 0, L_0x2cc72b0; 1 drivers -v0x29554c0_0 .net "AorB", 0 0, L_0x2cc7500; 1 drivers -v0x2955540_0 .net "AxorB", 0 0, L_0x2cc78a0; 1 drivers -v0x29555c0_0 .net "B", 0 0, L_0x2cc86d0; 1 drivers -v0x2955640_0 .alias "Command", 2 0, v0x2bc67a0_0; -v0x2957920_0 .net "OrNorXorOut", 0 0, L_0x2cc82a0; 1 drivers -v0x29579a0_0 .net "XorNor", 0 0, L_0x2cc7d20; 1 drivers -v0x2957a20_0 .net "nXor", 0 0, L_0x2cc7790; 1 drivers -L_0x2cc7ea0 .part v0x2bc78e0_0, 2, 1; -L_0x2cc8470 .part v0x2bc78e0_0, 0, 1; -S_0x294c2f0 .scope module, "mux0" "TwoInMux" 3 83, 3 8, S_0x29454e0; - .timescale -9 -12; -L_0x2cc7a00/d .functor NOT 1, L_0x2cc7ea0, C4<0>, C4<0>, C4<0>; -L_0x2cc7a00 .delay (10000,10000,10000) L_0x2cc7a00/d; -L_0x2cc7ac0/d .functor AND 1, L_0x2cc78a0, L_0x2cc7a00, C4<1>, C4<1>; -L_0x2cc7ac0 .delay (20000,20000,20000) L_0x2cc7ac0/d; -L_0x2cc7bd0/d .functor AND 1, L_0x2cc72b0, L_0x2cc7ea0, C4<1>, C4<1>; -L_0x2cc7bd0 .delay (20000,20000,20000) L_0x2cc7bd0/d; -L_0x2cc7d20/d .functor OR 1, L_0x2cc7ac0, L_0x2cc7bd0, C4<0>, C4<0>; -L_0x2cc7d20 .delay (20000,20000,20000) L_0x2cc7d20/d; -v0x294c3e0_0 .net "S", 0 0, L_0x2cc7ea0; 1 drivers -v0x294e7a0_0 .alias "in0", 0 0, v0x2955540_0; -v0x294e840_0 .alias "in1", 0 0, v0x29531a0_0; -v0x294e8e0_0 .net "nS", 0 0, L_0x2cc7a00; 1 drivers -v0x2950c00_0 .net "out0", 0 0, L_0x2cc7ac0; 1 drivers -v0x2950ca0_0 .net "out1", 0 0, L_0x2cc7bd0; 1 drivers -v0x2950d40_0 .alias "outfinal", 0 0, v0x29579a0_0; -S_0x29455d0 .scope module, "mux1" "TwoInMux" 3 84, 3 8, S_0x29454e0; - .timescale -9 -12; -L_0x2cc7f40/d .functor NOT 1, L_0x2cc8470, C4<0>, C4<0>, C4<0>; -L_0x2cc7f40 .delay (10000,10000,10000) L_0x2cc7f40/d; -L_0x2cc8000/d .functor AND 1, L_0x2cc7d20, L_0x2cc7f40, C4<1>, C4<1>; -L_0x2cc8000 .delay (20000,20000,20000) L_0x2cc8000/d; -L_0x2cc8150/d .functor AND 1, L_0x2cc7500, L_0x2cc8470, C4<1>, C4<1>; -L_0x2cc8150 .delay (20000,20000,20000) L_0x2cc8150/d; -L_0x2cc82a0/d .functor OR 1, L_0x2cc8000, L_0x2cc8150, C4<0>, C4<0>; -L_0x2cc82a0 .delay (20000,20000,20000) L_0x2cc82a0/d; -v0x29431a0_0 .net "S", 0 0, L_0x2cc8470; 1 drivers -v0x2947990_0 .alias "in0", 0 0, v0x29579a0_0; -v0x2947a10_0 .alias "in1", 0 0, v0x29554c0_0; -v0x2947ab0_0 .net "nS", 0 0, L_0x2cc7f40; 1 drivers -v0x2949e40_0 .net "out0", 0 0, L_0x2cc8000; 1 drivers -v0x2949ee0_0 .net "out1", 0 0, L_0x2cc8150; 1 drivers -v0x2949f80_0 .alias "outfinal", 0 0, v0x2957920_0; -S_0x292c430 .scope generate, "orbits[6]" "orbits[6]" 3 196, 3 196, S_0x29fb160; - .timescale -9 -12; -P_0x291e8d8 .param/l "i" 3 196, +C4<0110>; -S_0x292e780 .scope module, "attempt" "OrNorXor" 3 198, 3 64, S_0x292c430; - .timescale -9 -12; -L_0x2cc8770/d .functor NOR 1, L_0x2cc99a0, L_0x2cc9a40, C4<0>, C4<0>; -L_0x2cc8770 .delay (10000,10000,10000) L_0x2cc8770/d; -L_0x2cc8860/d .functor NOT 1, L_0x2cc8770, C4<0>, C4<0>, C4<0>; -L_0x2cc8860 .delay (10000,10000,10000) L_0x2cc8860/d; -L_0x2cc8990/d .functor NAND 1, L_0x2cc99a0, L_0x2cc9a40, C4<1>, C4<1>; -L_0x2cc8990 .delay (10000,10000,10000) L_0x2cc8990/d; -L_0x2cc8af0/d .functor NAND 1, L_0x2cc8990, L_0x2cc8860, C4<1>, C4<1>; -L_0x2cc8af0 .delay (10000,10000,10000) L_0x2cc8af0/d; -L_0x2cc8c00/d .functor NOT 1, L_0x2cc8af0, C4<0>, C4<0>, C4<0>; -L_0x2cc8c00 .delay (10000,10000,10000) L_0x2cc8c00/d; -v0x293c240_0 .net "A", 0 0, L_0x2cc99a0; 1 drivers -v0x293c2e0_0 .net "AnandB", 0 0, L_0x2cc8990; 1 drivers -v0x293e6d0_0 .net "AnorB", 0 0, L_0x2cc8770; 1 drivers -v0x293e750_0 .net "AorB", 0 0, L_0x2cc8860; 1 drivers -v0x293e7d0_0 .net "AxorB", 0 0, L_0x2cc8c00; 1 drivers -v0x293e850_0 .net "B", 0 0, L_0x2cc9a40; 1 drivers -v0x2940b80_0 .alias "Command", 2 0, v0x2bc67a0_0; -v0x2940c00_0 .net "OrNorXorOut", 0 0, L_0x2cc9600; 1 drivers -v0x2940c80_0 .net "XorNor", 0 0, L_0x2cc9080; 1 drivers -v0x2943030_0 .net "nXor", 0 0, L_0x2cc8af0; 1 drivers -L_0x2cc9200 .part v0x2bc78e0_0, 2, 1; -L_0x2cc97d0 .part v0x2bc78e0_0, 0, 1; -S_0x2935540 .scope module, "mux0" "TwoInMux" 3 83, 3 8, S_0x292e780; - .timescale -9 -12; -L_0x2cc8d60/d .functor NOT 1, L_0x2cc9200, C4<0>, C4<0>, C4<0>; -L_0x2cc8d60 .delay (10000,10000,10000) L_0x2cc8d60/d; -L_0x2cc8e20/d .functor AND 1, L_0x2cc8c00, L_0x2cc8d60, C4<1>, C4<1>; -L_0x2cc8e20 .delay (20000,20000,20000) L_0x2cc8e20/d; -L_0x2cc8f30/d .functor AND 1, L_0x2cc8770, L_0x2cc9200, C4<1>, C4<1>; -L_0x2cc8f30 .delay (20000,20000,20000) L_0x2cc8f30/d; -L_0x2cc9080/d .functor OR 1, L_0x2cc8e20, L_0x2cc8f30, C4<0>, C4<0>; -L_0x2cc9080 .delay (20000,20000,20000) L_0x2cc9080/d; -v0x2937900_0 .net "S", 0 0, L_0x2cc9200; 1 drivers -v0x29379c0_0 .alias "in0", 0 0, v0x293e7d0_0; -v0x2937a60_0 .alias "in1", 0 0, v0x293e6d0_0; -v0x2939d60_0 .net "nS", 0 0, L_0x2cc8d60; 1 drivers -v0x2939de0_0 .net "out0", 0 0, L_0x2cc8e20; 1 drivers -v0x2939e80_0 .net "out1", 0 0, L_0x2cc8f30; 1 drivers -v0x293c1c0_0 .alias "outfinal", 0 0, v0x2940c80_0; -S_0x292e870 .scope module, "mux1" "TwoInMux" 3 84, 3 8, S_0x292e780; - .timescale -9 -12; -L_0x2cc92a0/d .functor NOT 1, L_0x2cc97d0, C4<0>, C4<0>, C4<0>; -L_0x2cc92a0 .delay (10000,10000,10000) L_0x2cc92a0/d; -L_0x2cc9360/d .functor AND 1, L_0x2cc9080, L_0x2cc92a0, C4<1>, C4<1>; -L_0x2cc9360 .delay (20000,20000,20000) L_0x2cc9360/d; -L_0x2cc94b0/d .functor AND 1, L_0x2cc8860, L_0x2cc97d0, C4<1>, C4<1>; -L_0x2cc94b0 .delay (20000,20000,20000) L_0x2cc94b0/d; -L_0x2cc9600/d .functor OR 1, L_0x2cc9360, L_0x2cc94b0, C4<0>, C4<0>; -L_0x2cc9600 .delay (20000,20000,20000) L_0x2cc9600/d; -v0x2930be0_0 .net "S", 0 0, L_0x2cc97d0; 1 drivers -v0x2930c60_0 .alias "in0", 0 0, v0x2940c80_0; -v0x2930d00_0 .alias "in1", 0 0, v0x293e750_0; -v0x2933040_0 .net "nS", 0 0, L_0x2cc92a0; 1 drivers -v0x29330c0_0 .net "out0", 0 0, L_0x2cc9360; 1 drivers -v0x2933160_0 .net "out1", 0 0, L_0x2cc94b0; 1 drivers -v0x29354a0_0 .alias "outfinal", 0 0, v0x2940c00_0; -S_0x290cab0 .scope generate, "orbits[7]" "orbits[7]" 3 196, 3 196, S_0x29fb160; - .timescale -9 -12; -P_0x2906238 .param/l "i" 3 196, +C4<0111>; -S_0x290cba0 .scope module, "attempt" "OrNorXor" 3 198, 3 64, S_0x290cab0; - .timescale -9 -12; -L_0x2cc9910/d .functor NOR 1, L_0x2ccaca0, L_0x2cc9ae0, C4<0>, C4<0>; -L_0x2cc9910 .delay (10000,10000,10000) L_0x2cc9910/d; -L_0x2cc9c10/d .functor NOT 1, L_0x2cc9910, C4<0>, C4<0>, C4<0>; -L_0x2cc9c10 .delay (10000,10000,10000) L_0x2cc9c10/d; -L_0x2cc9d20/d .functor NAND 1, L_0x2ccaca0, L_0x2cc9ae0, C4<1>, C4<1>; -L_0x2cc9d20 .delay (10000,10000,10000) L_0x2cc9d20/d; -L_0x2cc9e80/d .functor NAND 1, L_0x2cc9d20, L_0x2cc9c10, C4<1>, C4<1>; -L_0x2cc9e80 .delay (10000,10000,10000) L_0x2cc9e80/d; -L_0x2cc9f90/d .functor NOT 1, L_0x2cc9e80, C4<0>, C4<0>, C4<0>; -L_0x2cc9f90 .delay (10000,10000,10000) L_0x2cc9f90/d; -v0x2925640_0 .net "A", 0 0, L_0x2ccaca0; 1 drivers -v0x29279d0_0 .net "AnandB", 0 0, L_0x2cc9d20; 1 drivers -v0x2927a70_0 .net "AnorB", 0 0, L_0x2cc9910; 1 drivers -v0x2927af0_0 .net "AorB", 0 0, L_0x2cc9c10; 1 drivers -v0x2929e80_0 .net "AxorB", 0 0, L_0x2cc9f90; 1 drivers -v0x2929f00_0 .net "B", 0 0, L_0x2cc9ae0; 1 drivers -v0x2929f80_0 .alias "Command", 2 0, v0x2bc67a0_0; -v0x292a000_0 .net "OrNorXorOut", 0 0, L_0x2cca990; 1 drivers -v0x292c330_0 .net "XorNor", 0 0, L_0x2cca410; 1 drivers -v0x292c3b0_0 .net "nXor", 0 0, L_0x2cc9e80; 1 drivers -L_0x2cca590 .part v0x2bc78e0_0, 2, 1; -L_0x2ccab60 .part v0x2bc78e0_0, 0, 1; -S_0x2920bc0 .scope module, "mux0" "TwoInMux" 3 83, 3 8, S_0x290cba0; - .timescale -9 -12; -L_0x2cca0f0/d .functor NOT 1, L_0x2cca590, C4<0>, C4<0>, C4<0>; -L_0x2cca0f0 .delay (10000,10000,10000) L_0x2cca0f0/d; -L_0x2cca1b0/d .functor AND 1, L_0x2cc9f90, L_0x2cca0f0, C4<1>, C4<1>; -L_0x2cca1b0 .delay (20000,20000,20000) L_0x2cca1b0/d; -L_0x2cca2c0/d .functor AND 1, L_0x2cc9910, L_0x2cca590, C4<1>, C4<1>; -L_0x2cca2c0 .delay (20000,20000,20000) L_0x2cca2c0/d; -L_0x2cca410/d .functor OR 1, L_0x2cca1b0, L_0x2cca2c0, C4<0>, C4<0>; -L_0x2cca410 .delay (20000,20000,20000) L_0x2cca410/d; -v0x2920cb0_0 .net "S", 0 0, L_0x2cca590; 1 drivers -v0x291e850_0 .alias "in0", 0 0, v0x2929e80_0; -v0x2923070_0 .alias "in1", 0 0, v0x2927a70_0; -v0x2923110_0 .net "nS", 0 0, L_0x2cca0f0; 1 drivers -v0x2923190_0 .net "out0", 0 0, L_0x2cca1b0; 1 drivers -v0x2925520_0 .net "out1", 0 0, L_0x2cca2c0; 1 drivers -v0x29255c0_0 .alias "outfinal", 0 0, v0x292c330_0; -S_0x2962fa0 .scope module, "mux1" "TwoInMux" 3 84, 3 8, S_0x290cba0; - .timescale -9 -12; -L_0x2cca630/d .functor NOT 1, L_0x2ccab60, C4<0>, C4<0>, C4<0>; -L_0x2cca630 .delay (10000,10000,10000) L_0x2cca630/d; -L_0x2cca6f0/d .functor AND 1, L_0x2cca410, L_0x2cca630, C4<1>, C4<1>; -L_0x2cca6f0 .delay (20000,20000,20000) L_0x2cca6f0/d; -L_0x2cca840/d .functor AND 1, L_0x2cc9c10, L_0x2ccab60, C4<1>, C4<1>; -L_0x2cca840 .delay (20000,20000,20000) L_0x2cca840/d; -L_0x2cca990/d .functor OR 1, L_0x2cca6f0, L_0x2cca840, C4<0>, C4<0>; -L_0x2cca990 .delay (20000,20000,20000) L_0x2cca990/d; -v0x290b6f0_0 .net "S", 0 0, L_0x2ccab60; 1 drivers -v0x2963090_0 .alias "in0", 0 0, v0x292c330_0; -v0x291c1c0_0 .alias "in1", 0 0, v0x2927af0_0; -v0x291c260_0 .net "nS", 0 0, L_0x2cca630; 1 drivers -v0x291c2e0_0 .net "out0", 0 0, L_0x2cca6f0; 1 drivers -v0x291e710_0 .net "out1", 0 0, L_0x2cca840; 1 drivers -v0x291e7b0_0 .alias "outfinal", 0 0, v0x292a000_0; -S_0x28ff630 .scope generate, "orbits[8]" "orbits[8]" 3 196, 3 196, S_0x29fb160; - .timescale -9 -12; -P_0x28f23e8 .param/l "i" 3 196, +C4<01000>; -S_0x28ff740 .scope module, "attempt" "OrNorXor" 3 198, 3 64, S_0x28ff630; - .timescale -9 -12; -L_0x2ccadf0/d .functor NOR 1, L_0x2ccad40, L_0x2ccc050, C4<0>, C4<0>; -L_0x2ccadf0 .delay (10000,10000,10000) L_0x2ccadf0/d; -L_0x2ccaee0/d .functor NOT 1, L_0x2ccadf0, C4<0>, C4<0>, C4<0>; -L_0x2ccaee0 .delay (10000,10000,10000) L_0x2ccaee0/d; -L_0x2ccb010/d .functor NAND 1, L_0x2ccad40, L_0x2ccc050, C4<1>, C4<1>; -L_0x2ccb010 .delay (10000,10000,10000) L_0x2ccb010/d; -L_0x2ccb170/d .functor NAND 1, L_0x2ccb010, L_0x2ccaee0, C4<1>, C4<1>; -L_0x2ccb170 .delay (10000,10000,10000) L_0x2ccb170/d; -L_0x2ccb280/d .functor NOT 1, L_0x2ccb170, C4<0>, C4<0>, C4<0>; -L_0x2ccb280 .delay (10000,10000,10000) L_0x2ccb280/d; -v0x2908af0_0 .net "A", 0 0, L_0x2ccad40; 1 drivers -v0x2908b90_0 .net "AnandB", 0 0, L_0x2ccb010; 1 drivers -v0x2908c30_0 .net "AnorB", 0 0, L_0x2ccadf0; 1 drivers -v0x290a030_0 .net "AorB", 0 0, L_0x2ccaee0; 1 drivers -v0x290a0b0_0 .net "AxorB", 0 0, L_0x2ccb280; 1 drivers -v0x290a130_0 .net "B", 0 0, L_0x2ccc050; 1 drivers -v0x290a1b0_0 .alias "Command", 2 0, v0x2bc67a0_0; -v0x290b570_0 .net "OrNorXorOut", 0 0, L_0x2ccbc80; 1 drivers -v0x290b5f0_0 .net "XorNor", 0 0, L_0x2ccb700; 1 drivers -v0x290b670_0 .net "nXor", 0 0, L_0x2ccb170; 1 drivers -L_0x2ccb880 .part v0x2bc78e0_0, 2, 1; -L_0x2ccbe50 .part v0x2bc78e0_0, 0, 1; -S_0x2904b30 .scope module, "mux0" "TwoInMux" 3 83, 3 8, S_0x28ff740; - .timescale -9 -12; -L_0x2ccb3e0/d .functor NOT 1, L_0x2ccb880, C4<0>, C4<0>, C4<0>; -L_0x2ccb3e0 .delay (10000,10000,10000) L_0x2ccb3e0/d; -L_0x2ccb4a0/d .functor AND 1, L_0x2ccb280, L_0x2ccb3e0, C4<1>, C4<1>; -L_0x2ccb4a0 .delay (20000,20000,20000) L_0x2ccb4a0/d; -L_0x2ccb5b0/d .functor AND 1, L_0x2ccadf0, L_0x2ccb880, C4<1>, C4<1>; -L_0x2ccb5b0 .delay (20000,20000,20000) L_0x2ccb5b0/d; -L_0x2ccb700/d .functor OR 1, L_0x2ccb4a0, L_0x2ccb5b0, C4<0>, C4<0>; -L_0x2ccb700 .delay (20000,20000,20000) L_0x2ccb700/d; -v0x2904c20_0 .net "S", 0 0, L_0x2ccb880; 1 drivers -v0x2906070_0 .alias "in0", 0 0, v0x290a0b0_0; -v0x2906110_0 .alias "in1", 0 0, v0x2908c30_0; -v0x29061b0_0 .net "nS", 0 0, L_0x2ccb3e0; 1 drivers -v0x29075b0_0 .net "out0", 0 0, L_0x2ccb4a0; 1 drivers -v0x2907650_0 .net "out1", 0 0, L_0x2ccb5b0; 1 drivers -v0x29076f0_0 .alias "outfinal", 0 0, v0x290b5f0_0; -S_0x2900b70 .scope module, "mux1" "TwoInMux" 3 84, 3 8, S_0x28ff740; - .timescale -9 -12; -L_0x2ccb920/d .functor NOT 1, L_0x2ccbe50, C4<0>, C4<0>, C4<0>; -L_0x2ccb920 .delay (10000,10000,10000) L_0x2ccb920/d; -L_0x2ccb9e0/d .functor AND 1, L_0x2ccb700, L_0x2ccb920, C4<1>, C4<1>; -L_0x2ccb9e0 .delay (20000,20000,20000) L_0x2ccb9e0/d; -L_0x2ccbb30/d .functor AND 1, L_0x2ccaee0, L_0x2ccbe50, C4<1>, C4<1>; -L_0x2ccbb30 .delay (20000,20000,20000) L_0x2ccbb30/d; -L_0x2ccbc80/d .functor OR 1, L_0x2ccb9e0, L_0x2ccbb30, C4<0>, C4<0>; -L_0x2ccbc80 .delay (20000,20000,20000) L_0x2ccbc80/d; -v0x2900c60_0 .net "S", 0 0, L_0x2ccbe50; 1 drivers -v0x29020b0_0 .alias "in0", 0 0, v0x290b5f0_0; -v0x2902150_0 .alias "in1", 0 0, v0x290a030_0; -v0x29021f0_0 .net "nS", 0 0, L_0x2ccb920; 1 drivers -v0x29035f0_0 .net "out0", 0 0, L_0x2ccb9e0; 1 drivers -v0x2903690_0 .net "out1", 0 0, L_0x2ccbb30; 1 drivers -v0x2903730_0 .alias "outfinal", 0 0, v0x290b570_0; -S_0x297d500 .scope generate, "orbits[9]" "orbits[9]" 3 196, 3 196, S_0x29fb160; - .timescale -9 -12; -P_0x29b24f8 .param/l "i" 3 196, +C4<01001>; -S_0x297b490 .scope module, "attempt" "OrNorXor" 3 198, 3 64, S_0x297d500; - .timescale -9 -12; -L_0x2ccbf90/d .functor NOR 1, L_0x2ccd2c0, L_0x2ccc0f0, C4<0>, C4<0>; -L_0x2ccbf90 .delay (10000,10000,10000) L_0x2ccbf90/d; -L_0x2ccc210/d .functor NOT 1, L_0x2ccbf90, C4<0>, C4<0>, C4<0>; -L_0x2ccc210 .delay (10000,10000,10000) L_0x2ccc210/d; -L_0x2ccc340/d .functor NAND 1, L_0x2ccd2c0, L_0x2ccc0f0, C4<1>, C4<1>; -L_0x2ccc340 .delay (10000,10000,10000) L_0x2ccc340/d; -L_0x2ccc4a0/d .functor NAND 1, L_0x2ccc340, L_0x2ccc210, C4<1>, C4<1>; -L_0x2ccc4a0 .delay (10000,10000,10000) L_0x2ccc4a0/d; -L_0x2ccc5b0/d .functor NOT 1, L_0x2ccc4a0, C4<0>, C4<0>, C4<0>; -L_0x2ccc5b0 .delay (10000,10000,10000) L_0x2ccc5b0/d; -v0x2741210_0 .net "A", 0 0, L_0x2ccd2c0; 1 drivers -v0x28f0cf0_0 .net "AnandB", 0 0, L_0x2ccc340; 1 drivers -v0x28f0d90_0 .net "AnorB", 0 0, L_0x2ccbf90; 1 drivers -v0x28f0e10_0 .net "AorB", 0 0, L_0x2ccc210; 1 drivers -v0x28f22e0_0 .net "AxorB", 0 0, L_0x2ccc5b0; 1 drivers -v0x28f2360_0 .net "B", 0 0, L_0x2ccc0f0; 1 drivers -v0x28f2420_0 .alias "Command", 2 0, v0x2bc67a0_0; -v0x28fe0f0_0 .net "OrNorXorOut", 0 0, L_0x2cccfb0; 1 drivers -v0x28fe170_0 .net "XorNor", 0 0, L_0x2ccca30; 1 drivers -v0x28fe240_0 .net "nXor", 0 0, L_0x2ccc4a0; 1 drivers -L_0x2cccbb0 .part v0x2bc78e0_0, 2, 1; -L_0x2ccd180 .part v0x2bc78e0_0, 0, 1; -S_0x2764480 .scope module, "mux0" "TwoInMux" 3 83, 3 8, S_0x297b490; - .timescale -9 -12; -L_0x2ccc710/d .functor NOT 1, L_0x2cccbb0, C4<0>, C4<0>, C4<0>; -L_0x2ccc710 .delay (10000,10000,10000) L_0x2ccc710/d; -L_0x2ccc7d0/d .functor AND 1, L_0x2ccc5b0, L_0x2ccc710, C4<1>, C4<1>; -L_0x2ccc7d0 .delay (20000,20000,20000) L_0x2ccc7d0/d; -L_0x2ccc8e0/d .functor AND 1, L_0x2ccbf90, L_0x2cccbb0, C4<1>, C4<1>; -L_0x2ccc8e0 .delay (20000,20000,20000) L_0x2ccc8e0/d; -L_0x2ccca30/d .functor OR 1, L_0x2ccc7d0, L_0x2ccc8e0, C4<0>, C4<0>; -L_0x2ccca30 .delay (20000,20000,20000) L_0x2ccca30/d; -v0x282ef60_0 .net "S", 0 0, L_0x2cccbb0; 1 drivers -v0x27645b0_0 .alias "in0", 0 0, v0x28f22e0_0; -v0x270ecf0_0 .alias "in1", 0 0, v0x28f0d90_0; -v0x270ed90_0 .net "nS", 0 0, L_0x2ccc710; 1 drivers -v0x270ee10_0 .net "out0", 0 0, L_0x2ccc7d0; 1 drivers -v0x27410f0_0 .net "out1", 0 0, L_0x2ccc8e0; 1 drivers -v0x2741190_0 .alias "outfinal", 0 0, v0x28fe170_0; -S_0x2a10d70 .scope module, "mux1" "TwoInMux" 3 84, 3 8, S_0x297b490; - .timescale -9 -12; -L_0x2cccc50/d .functor NOT 1, L_0x2ccd180, C4<0>, C4<0>, C4<0>; -L_0x2cccc50 .delay (10000,10000,10000) L_0x2cccc50/d; -L_0x2cccd10/d .functor AND 1, L_0x2ccca30, L_0x2cccc50, C4<1>, C4<1>; -L_0x2cccd10 .delay (20000,20000,20000) L_0x2cccd10/d; -L_0x2ccce60/d .functor AND 1, L_0x2ccc210, L_0x2ccd180, C4<1>, C4<1>; -L_0x2ccce60 .delay (20000,20000,20000) L_0x2ccce60/d; -L_0x2cccfb0/d .functor OR 1, L_0x2cccd10, L_0x2ccce60, C4<0>, C4<0>; -L_0x2cccfb0 .delay (20000,20000,20000) L_0x2cccfb0/d; -v0x297b580_0 .net "S", 0 0, L_0x2ccd180; 1 drivers -v0x2a10e60_0 .alias "in0", 0 0, v0x28fe170_0; -v0x2852170_0 .alias "in1", 0 0, v0x28f0e10_0; -v0x2852210_0 .net "nS", 0 0, L_0x2cccc50; 1 drivers -v0x2852290_0 .net "out0", 0 0, L_0x2cccd10; 1 drivers -v0x282ee20_0 .net "out1", 0 0, L_0x2ccce60; 1 drivers -v0x282eec0_0 .alias "outfinal", 0 0, v0x28fe0f0_0; -S_0x29d38e0 .scope generate, "orbits[10]" "orbits[10]" 3 196, 3 196, S_0x29fb160; - .timescale -9 -12; -P_0x2971f08 .param/l "i" 3 196, +C4<01010>; -S_0x29bdff0 .scope module, "attempt" "OrNorXor" 3 198, 3 64, S_0x29d38e0; - .timescale -9 -12; -L_0x2ccd440/d .functor NOR 1, L_0x2ccd360, L_0x2cce6c0, C4<0>, C4<0>; -L_0x2ccd440 .delay (10000,10000,10000) L_0x2ccd440/d; -L_0x2ccd530/d .functor NOT 1, L_0x2ccd440, C4<0>, C4<0>, C4<0>; -L_0x2ccd530 .delay (10000,10000,10000) L_0x2ccd530/d; -L_0x2ccd640/d .functor NAND 1, L_0x2ccd360, L_0x2cce6c0, C4<1>, C4<1>; -L_0x2ccd640 .delay (10000,10000,10000) L_0x2ccd640/d; -L_0x2ccd7a0/d .functor NAND 1, L_0x2ccd640, L_0x2ccd530, C4<1>, C4<1>; -L_0x2ccd7a0 .delay (10000,10000,10000) L_0x2ccd7a0/d; -L_0x2ccd8b0/d .functor NOT 1, L_0x2ccd7a0, C4<0>, C4<0>, C4<0>; -L_0x2ccd8b0 .delay (10000,10000,10000) L_0x2ccd8b0/d; -v0x2998a40_0 .net "A", 0 0, L_0x2ccd360; 1 drivers -v0x2994c50_0 .net "AnandB", 0 0, L_0x2ccd640; 1 drivers -v0x2994cf0_0 .net "AnorB", 0 0, L_0x2ccd440; 1 drivers -v0x2992ba0_0 .net "AorB", 0 0, L_0x2ccd530; 1 drivers -v0x2992c20_0 .net "AxorB", 0 0, L_0x2ccd8b0; 1 drivers -v0x2992ca0_0 .net "B", 0 0, L_0x2cce6c0; 1 drivers -v0x298ee70_0 .alias "Command", 2 0, v0x2bc67a0_0; -v0x298eef0_0 .net "OrNorXorOut", 0 0, L_0x2cce2c0; 1 drivers -v0x298ef70_0 .net "XorNor", 0 0, L_0x2ccdd50; 1 drivers -v0x297d480_0 .net "nXor", 0 0, L_0x2ccd7a0; 1 drivers -L_0x2ccded0 .part v0x2bc78e0_0, 2, 1; -L_0x2cce490 .part v0x2bc78e0_0, 0, 1; -S_0x29b0300 .scope module, "mux0" "TwoInMux" 3 83, 3 8, S_0x29bdff0; - .timescale -9 -12; -L_0x2ccda10/d .functor NOT 1, L_0x2ccded0, C4<0>, C4<0>, C4<0>; -L_0x2ccda10 .delay (10000,10000,10000) L_0x2ccda10/d; -L_0x2ccdaf0/d .functor AND 1, L_0x2ccd8b0, L_0x2ccda10, C4<1>, C4<1>; -L_0x2ccdaf0 .delay (20000,20000,20000) L_0x2ccdaf0/d; -L_0x2ccdc00/d .functor AND 1, L_0x2ccd440, L_0x2ccded0, C4<1>, C4<1>; -L_0x2ccdc00 .delay (20000,20000,20000) L_0x2ccdc00/d; -L_0x2ccdd50/d .functor OR 1, L_0x2ccdaf0, L_0x2ccdc00, C4<0>, C4<0>; -L_0x2ccdd50 .delay (20000,20000,20000) L_0x2ccdd50/d; -v0x29b03f0_0 .net "S", 0 0, L_0x2ccded0; 1 drivers -v0x29b2450_0 .alias "in0", 0 0, v0x2992c20_0; -v0x299e7e0_0 .alias "in1", 0 0, v0x2994cf0_0; -v0x299e880_0 .net "nS", 0 0, L_0x2ccda10; 1 drivers -v0x299aa70_0 .net "out0", 0 0, L_0x2ccdaf0; 1 drivers -v0x299ab10_0 .net "out1", 0 0, L_0x2ccdc00; 1 drivers -v0x29989c0_0 .alias "outfinal", 0 0, v0x298ef70_0; -S_0x29bbf40 .scope module, "mux1" "TwoInMux" 3 84, 3 8, S_0x29bdff0; - .timescale -9 -12; -L_0x2ccdf70/d .functor NOT 1, L_0x2cce490, C4<0>, C4<0>, C4<0>; -L_0x2ccdf70 .delay (10000,10000,10000) L_0x2ccdf70/d; -L_0x2cce030/d .functor AND 1, L_0x2ccdd50, L_0x2ccdf70, C4<1>, C4<1>; -L_0x2cce030 .delay (20000,20000,20000) L_0x2cce030/d; -L_0x29c9dd0/d .functor AND 1, L_0x2ccd530, L_0x2cce490, C4<1>, C4<1>; -L_0x29c9dd0 .delay (20000,20000,20000) L_0x29c9dd0/d; -L_0x2cce2c0/d .functor OR 1, L_0x2cce030, L_0x29c9dd0, C4<0>, C4<0>; -L_0x2cce2c0 .delay (20000,20000,20000) L_0x2cce2c0/d; -v0x29be0e0_0 .net "S", 0 0, L_0x2cce490; 1 drivers -v0x29bc030_0 .alias "in0", 0 0, v0x298ef70_0; -v0x29b81d0_0 .alias "in1", 0 0, v0x2992ba0_0; -v0x29b8270_0 .net "nS", 0 0, L_0x2ccdf70; 1 drivers -v0x29b6120_0 .net "out0", 0 0, L_0x2cce030; 1 drivers -v0x29b61c0_0 .net "out1", 0 0, L_0x29c9dd0; 1 drivers -v0x29b23b0_0 .alias "outfinal", 0 0, v0x298eef0_0; -S_0x29759b0 .scope generate, "orbits[11]" "orbits[11]" 3 196, 3 196, S_0x29fb160; - .timescale -9 -12; -P_0x2a116d8 .param/l "i" 3 196, +C4<01011>; -S_0x29fecb0 .scope module, "attempt" "OrNorXor" 3 198, 3 64, S_0x29759b0; - .timescale -9 -12; -L_0x2cce5d0/d .functor NOR 1, L_0x2ccf900, L_0x2cce760, C4<0>, C4<0>; -L_0x2cce5d0 .delay (10000,10000,10000) L_0x2cce5d0/d; -L_0x2cce860/d .functor NOT 1, L_0x2cce5d0, C4<0>, C4<0>, C4<0>; -L_0x2cce860 .delay (10000,10000,10000) L_0x2cce860/d; -L_0x2cce950/d .functor NAND 1, L_0x2ccf900, L_0x2cce760, C4<1>, C4<1>; -L_0x2cce950 .delay (10000,10000,10000) L_0x2cce950/d; -L_0x2cceab0/d .functor NAND 1, L_0x2cce950, L_0x2cce860, C4<1>, C4<1>; -L_0x2cceab0 .delay (10000,10000,10000) L_0x2cceab0/d; -L_0x2ccebc0/d .functor NOT 1, L_0x2cceab0, C4<0>, C4<0>, C4<0>; -L_0x2ccebc0 .delay (10000,10000,10000) L_0x2ccebc0/d; -v0x29db7b0_0 .net "A", 0 0, L_0x2ccf900; 1 drivers -v0x29d9680_0 .net "AnandB", 0 0, L_0x2cce950; 1 drivers -v0x29d9720_0 .net "AnorB", 0 0, L_0x2cce5d0; 1 drivers -v0x296fdd0_0 .net "AorB", 0 0, L_0x2cce860; 1 drivers -v0x296fe50_0 .net "AxorB", 0 0, L_0x2ccebc0; 1 drivers -v0x296fed0_0 .net "B", 0 0, L_0x2cce760; 1 drivers -v0x29d5910_0 .alias "Command", 2 0, v0x2bc67a0_0; -v0x29d5990_0 .net "OrNorXorOut", 0 0, L_0x2ccf5f0; 1 drivers -v0x29d5a10_0 .net "XorNor", 0 0, L_0x2ccf060; 1 drivers -v0x29d3860_0 .net "nXor", 0 0, L_0x2cceab0; 1 drivers -L_0x2ccf1e0 .part v0x2bc78e0_0, 2, 1; -L_0x2ccf7c0 .part v0x2bc78e0_0, 0, 1; -S_0x29f0fa0 .scope module, "mux0" "TwoInMux" 3 83, 3 8, S_0x29fecb0; - .timescale -9 -12; -L_0x2cced20/d .functor NOT 1, L_0x2ccf1e0, C4<0>, C4<0>, C4<0>; -L_0x2cced20 .delay (10000,10000,10000) L_0x2cced20/d; -L_0x2ccee00/d .functor AND 1, L_0x2ccebc0, L_0x2cced20, C4<1>, C4<1>; -L_0x2ccee00 .delay (20000,20000,20000) L_0x2ccee00/d; -L_0x2ccef10/d .functor AND 1, L_0x2cce5d0, L_0x2ccf1e0, C4<1>, C4<1>; -L_0x2ccef10 .delay (20000,20000,20000) L_0x2ccef10/d; -L_0x2ccf060/d .functor OR 1, L_0x2ccee00, L_0x2ccef10, C4<0>, C4<0>; -L_0x2ccf060 .delay (20000,20000,20000) L_0x2ccf060/d; -v0x29f1090_0 .net "S", 0 0, L_0x2ccf1e0; 1 drivers -v0x29f3110_0 .alias "in0", 0 0, v0x296fe50_0; -v0x2971dc0_0 .alias "in1", 0 0, v0x29d9720_0; -v0x2971e60_0 .net "nS", 0 0, L_0x2cced20; 1 drivers -v0x29df4a0_0 .net "out0", 0 0, L_0x2ccee00; 1 drivers -v0x29df540_0 .net "out1", 0 0, L_0x2ccef10; 1 drivers -v0x29db730_0 .alias "outfinal", 0 0, v0x29d5a10_0; -S_0x29fcc00 .scope module, "mux1" "TwoInMux" 3 84, 3 8, S_0x29fecb0; - .timescale -9 -12; -L_0x2ccf280/d .functor NOT 1, L_0x2ccf7c0, C4<0>, C4<0>, C4<0>; -L_0x2ccf280 .delay (10000,10000,10000) L_0x2ccf280/d; -L_0x2ccf360/d .functor AND 1, L_0x2ccf060, L_0x2ccf280, C4<1>, C4<1>; -L_0x2ccf360 .delay (20000,20000,20000) L_0x2ccf360/d; -L_0x29cfc30/d .functor AND 1, L_0x2cce860, L_0x2ccf7c0, C4<1>, C4<1>; -L_0x29cfc30 .delay (20000,20000,20000) L_0x29cfc30/d; -L_0x2ccf5f0/d .functor OR 1, L_0x2ccf360, L_0x29cfc30, C4<0>, C4<0>; -L_0x2ccf5f0 .delay (20000,20000,20000) L_0x2ccf5f0/d; -v0x29feda0_0 .net "S", 0 0, L_0x2ccf7c0; 1 drivers -v0x29fccf0_0 .alias "in0", 0 0, v0x29d5a10_0; -v0x29f8e90_0 .alias "in1", 0 0, v0x296fdd0_0; -v0x29f8f30_0 .net "nS", 0 0, L_0x2ccf280; 1 drivers -v0x29f6de0_0 .net "out0", 0 0, L_0x2ccf360; 1 drivers -v0x29f6e80_0 .net "out1", 0 0, L_0x29cfc30; 1 drivers -v0x29f3070_0 .alias "outfinal", 0 0, v0x29d5990_0; -S_0x2a11070 .scope generate, "orbits[12]" "orbits[12]" 3 196, 3 196, S_0x29fb160; - .timescale -9 -12; -P_0x2a08ea8 .param/l "i" 3 196, +C4<01100>; -S_0x2a127f0 .scope module, "attempt" "OrNorXor" 3 198, 3 64, S_0x2a11070; - .timescale -9 -12; -L_0x2cce800/d .functor NOR 1, L_0x2ccf9a0, L_0x2cd0d50, C4<0>, C4<0>; -L_0x2cce800 .delay (10000,10000,10000) L_0x2cce800/d; -L_0x2ccfb40/d .functor NOT 1, L_0x2cce800, C4<0>, C4<0>, C4<0>; -L_0x2ccfb40 .delay (10000,10000,10000) L_0x2ccfb40/d; -L_0x2ccfc70/d .functor NAND 1, L_0x2ccf9a0, L_0x2cd0d50, C4<1>, C4<1>; -L_0x2ccfc70 .delay (10000,10000,10000) L_0x2ccfc70/d; -L_0x2ccfdd0/d .functor NAND 1, L_0x2ccfc70, L_0x2ccfb40, C4<1>, C4<1>; -L_0x2ccfdd0 .delay (10000,10000,10000) L_0x2ccfdd0/d; -L_0x2ccfee0/d .functor NOT 1, L_0x2ccfdd0, C4<0>, C4<0>, C4<0>; -L_0x2ccfee0 .delay (10000,10000,10000) L_0x2ccfee0/d; -v0x2a14b80_0 .net "A", 0 0, L_0x2ccf9a0; 1 drivers -v0x2977920_0 .net "AnandB", 0 0, L_0x2ccfc70; 1 drivers -v0x29779c0_0 .net "AnorB", 0 0, L_0x2cce800; 1 drivers -v0x2a165f0_0 .net "AorB", 0 0, L_0x2ccfb40; 1 drivers -v0x2a16670_0 .net "AxorB", 0 0, L_0x2ccfee0; 1 drivers -v0x2a166f0_0 .net "B", 0 0, L_0x2cd0d50; 1 drivers -v0x2a14540_0 .alias "Command", 2 0, v0x2bc67a0_0; -v0x2a145c0_0 .net "OrNorXorOut", 0 0, L_0x2cd0920; 1 drivers -v0x2a14640_0 .net "XorNor", 0 0, L_0x2cd03a0; 1 drivers -v0x2975930_0 .net "nXor", 0 0, L_0x2ccfdd0; 1 drivers -L_0x2cd0520 .part v0x2bc78e0_0, 2, 1; -L_0x2cd0af0 .part v0x2bc78e0_0, 0, 1; -S_0x2a15300 .scope module, "mux0" "TwoInMux" 3 83, 3 8, S_0x2a127f0; - .timescale -9 -12; -L_0x2cd0040/d .functor NOT 1, L_0x2cd0520, C4<0>, C4<0>, C4<0>; -L_0x2cd0040 .delay (10000,10000,10000) L_0x2cd0040/d; -L_0x2cd0120/d .functor AND 1, L_0x2ccfee0, L_0x2cd0040, C4<1>, C4<1>; -L_0x2cd0120 .delay (20000,20000,20000) L_0x2cd0120/d; -L_0x2cd0250/d .functor AND 1, L_0x2cce800, L_0x2cd0520, C4<1>, C4<1>; -L_0x2cd0250 .delay (20000,20000,20000) L_0x2cd0250/d; -L_0x2cd03a0/d .functor OR 1, L_0x2cd0120, L_0x2cd0250, C4<0>, C4<0>; -L_0x2cd03a0 .delay (20000,20000,20000) L_0x2cd03a0/d; -v0x2a16c90_0 .net "S", 0 0, L_0x2cd0520; 1 drivers -v0x2a15050_0 .alias "in0", 0 0, v0x2a16670_0; -v0x2a150f0_0 .alias "in1", 0 0, v0x29779c0_0; -v0x2a18610_0 .net "nS", 0 0, L_0x2cd0040; 1 drivers -v0x2a186b0_0 .net "out0", 0 0, L_0x2cd0120; 1 drivers -v0x2a14da0_0 .net "out1", 0 0, L_0x2cd0250; 1 drivers -v0x2a14b00_0 .alias "outfinal", 0 0, v0x2a14640_0; -S_0x2a0ec80 .scope module, "mux1" "TwoInMux" 3 84, 3 8, S_0x2a127f0; - .timescale -9 -12; -L_0x2cd05c0/d .functor NOT 1, L_0x2cd0af0, C4<0>, C4<0>, C4<0>; -L_0x2cd05c0 .delay (10000,10000,10000) L_0x2cd05c0/d; -L_0x2cd0680/d .functor AND 1, L_0x2cd03a0, L_0x2cd05c0, C4<1>, C4<1>; -L_0x2cd0680 .delay (20000,20000,20000) L_0x2cd0680/d; -L_0x2cd07d0/d .functor AND 1, L_0x2ccfb40, L_0x2cd0af0, C4<1>, C4<1>; -L_0x2cd07d0 .delay (20000,20000,20000) L_0x2cd07d0/d; -L_0x2cd0920/d .functor OR 1, L_0x2cd0680, L_0x2cd07d0, C4<0>, C4<0>; -L_0x2cd0920 .delay (20000,20000,20000) L_0x2cd0920/d; -v0x2a113a0_0 .net "S", 0 0, L_0x2cd0af0; 1 drivers -v0x2a173f0_0 .alias "in0", 0 0, v0x2a14640_0; -v0x2a17490_0 .alias "in1", 0 0, v0x2a165f0_0; -v0x2a17140_0 .net "nS", 0 0, L_0x2cd05c0; 1 drivers -v0x2a171c0_0 .net "out0", 0 0, L_0x2cd0680; 1 drivers -v0x2a16e90_0 .net "out1", 0 0, L_0x2cd07d0; 1 drivers -v0x2a16bf0_0 .alias "outfinal", 0 0, v0x2a145c0_0; -S_0x29f78f0 .scope generate, "orbits[13]" "orbits[13]" 3 196, 3 196, S_0x29fb160; - .timescale -9 -12; -P_0x29f97b8 .param/l "i" 3 196, +C4<01101>; -S_0x29faeb0 .scope module, "attempt" "OrNorXor" 3 198, 3 64, S_0x29f78f0; - .timescale -9 -12; -L_0x2ccfa40/d .functor NOR 1, L_0x2cd1f90, L_0x2cd0df0, C4<0>, C4<0>; -L_0x2ccfa40 .delay (10000,10000,10000) L_0x2ccfa40/d; -L_0x2cd0cc0/d .functor NOT 1, L_0x2ccfa40, C4<0>, C4<0>, C4<0>; -L_0x2cd0cc0 .delay (10000,10000,10000) L_0x2cd0cc0/d; -L_0x2cd0fd0/d .functor NAND 1, L_0x2cd1f90, L_0x2cd0df0, C4<1>, C4<1>; -L_0x2cd0fd0 .delay (10000,10000,10000) L_0x2cd0fd0/d; -L_0x2cd1130/d .functor NAND 1, L_0x2cd0fd0, L_0x2cd0cc0, C4<1>, C4<1>; -L_0x2cd1130 .delay (10000,10000,10000) L_0x2cd1130/d; -L_0x2cd1240/d .functor NOT 1, L_0x2cd1130, C4<0>, C4<0>, C4<0>; -L_0x2cd1240 .delay (10000,10000,10000) L_0x2cd1240/d; -v0x2a05130_0 .net "A", 0 0, L_0x2cd1f90; 1 drivers -v0x2a02fc0_0 .net "AnandB", 0 0, L_0x2cd0fd0; 1 drivers -v0x2a03060_0 .net "AnorB", 0 0, L_0x2ccfa40; 1 drivers -v0x2a0af10_0 .net "AorB", 0 0, L_0x2cd0cc0; 1 drivers -v0x2a0af90_0 .net "AxorB", 0 0, L_0x2cd1240; 1 drivers -v0x2a08e20_0 .net "B", 0 0, L_0x2cd0df0; 1 drivers -v0x2a08ee0_0 .alias "Command", 2 0, v0x2bc67a0_0; -v0x2a115d0_0 .net "OrNorXorOut", 0 0, L_0x2cd1c80; 1 drivers -v0x2a11650_0 .net "XorNor", 0 0, L_0x2cd1700; 1 drivers -v0x2a11320_0 .net "nXor", 0 0, L_0x2cd1130; 1 drivers -L_0x2cd1880 .part v0x2bc78e0_0, 2, 1; -L_0x2cd1e50 .part v0x2bc78e0_0, 0, 1; -S_0x29fd9c0 .scope module, "mux0" "TwoInMux" 3 83, 3 8, S_0x29faeb0; - .timescale -9 -12; -L_0x2cd13a0/d .functor NOT 1, L_0x2cd1880, C4<0>, C4<0>, C4<0>; -L_0x2cd13a0 .delay (10000,10000,10000) L_0x2cd13a0/d; -L_0x2cd1480/d .functor AND 1, L_0x2cd1240, L_0x2cd13a0, C4<1>, C4<1>; -L_0x2cd1480 .delay (20000,20000,20000) L_0x2cd1480/d; -L_0x2cd15b0/d .functor AND 1, L_0x2ccfa40, L_0x2cd1880, C4<1>, C4<1>; -L_0x2cd15b0 .delay (20000,20000,20000) L_0x2cd15b0/d; -L_0x2cd1700/d .functor OR 1, L_0x2cd1480, L_0x2cd15b0, C4<0>, C4<0>; -L_0x2cd1700 .delay (20000,20000,20000) L_0x2cd1700/d; -v0x29ff350_0 .net "S", 0 0, L_0x2cd1880; 1 drivers -v0x29fd710_0 .alias "in0", 0 0, v0x2a0af90_0; -v0x29fd7b0_0 .alias "in1", 0 0, v0x2a03060_0; -v0x29fd460_0 .net "nS", 0 0, L_0x2cd13a0; 1 drivers -v0x29fd500_0 .net "out0", 0 0, L_0x2cd1480; 1 drivers -v0x29fd1c0_0 .net "out1", 0 0, L_0x2cd15b0; 1 drivers -v0x2a050b0_0 .alias "outfinal", 0 0, v0x2a11650_0; -S_0x29f7640 .scope module, "mux1" "TwoInMux" 3 84, 3 8, S_0x29faeb0; - .timescale -9 -12; -L_0x2cd1920/d .functor NOT 1, L_0x2cd1e50, C4<0>, C4<0>, C4<0>; -L_0x2cd1920 .delay (10000,10000,10000) L_0x2cd1920/d; -L_0x2cd19e0/d .functor AND 1, L_0x2cd1700, L_0x2cd1920, C4<1>, C4<1>; -L_0x2cd19e0 .delay (20000,20000,20000) L_0x2cd19e0/d; -L_0x2cd1b30/d .functor AND 1, L_0x2cd0cc0, L_0x2cd1e50, C4<1>, C4<1>; -L_0x2cd1b30 .delay (20000,20000,20000) L_0x2cd1b30/d; -L_0x2cd1c80/d .functor OR 1, L_0x2cd19e0, L_0x2cd1b30, C4<0>, C4<0>; -L_0x2cd1c80 .delay (20000,20000,20000) L_0x2cd1c80/d; -v0x29f7c20_0 .net "S", 0 0, L_0x2cd1e50; 1 drivers -v0x29f73a0_0 .alias "in0", 0 0, v0x2a11650_0; -v0x29f7440_0 .alias "in1", 0 0, v0x2a0af10_0; -v0x29ff800_0 .net "nS", 0 0, L_0x2cd1920; 1 drivers -v0x29ff880_0 .net "out0", 0 0, L_0x2cd19e0; 1 drivers -v0x29ff550_0 .net "out1", 0 0, L_0x2cd1b30; 1 drivers -v0x29ff2b0_0 .alias "outfinal", 0 0, v0x2a115d0_0; -S_0x29e5860 .scope generate, "orbits[14]" "orbits[14]" 3 196, 3 196, S_0x29fb160; - .timescale -9 -12; -P_0x29e79d8 .param/l "i" 3 196, +C4<01110>; -S_0x29ed7b0 .scope module, "attempt" "OrNorXor" 3 198, 3 64, S_0x29e5860; - .timescale -9 -12; -L_0x2cd0e90/d .functor NOR 1, L_0x2cd2030, L_0x2cd20d0, C4<0>, C4<0>; -L_0x2cd0e90 .delay (10000,10000,10000) L_0x2cd0e90/d; -L_0x2cd2200/d .functor NOT 1, L_0x2cd0e90, C4<0>, C4<0>, C4<0>; -L_0x2cd2200 .delay (10000,10000,10000) L_0x2cd2200/d; -L_0x2cd2330/d .functor NAND 1, L_0x2cd2030, L_0x2cd20d0, C4<1>, C4<1>; -L_0x2cd2330 .delay (10000,10000,10000) L_0x2cd2330/d; -L_0x2cd2490/d .functor NAND 1, L_0x2cd2330, L_0x2cd2200, C4<1>, C4<1>; -L_0x2cd2490 .delay (10000,10000,10000) L_0x2cd2490/d; -L_0x2cd25a0/d .functor NOT 1, L_0x2cd2490, C4<0>, C4<0>, C4<0>; -L_0x2cd25a0 .delay (10000,10000,10000) L_0x2cd25a0/d; -v0x29f1600_0 .net "A", 0 0, L_0x2cd2030; 1 drivers -v0x29f9c90_0 .net "AnandB", 0 0, L_0x2cd2330; 1 drivers -v0x29f9d30_0 .net "AnorB", 0 0, L_0x2cd0e90; 1 drivers -v0x29f99e0_0 .net "AorB", 0 0, L_0x2cd2200; 1 drivers -v0x29f9a60_0 .net "AxorB", 0 0, L_0x2cd25a0; 1 drivers -v0x29f9730_0 .net "B", 0 0, L_0x2cd20d0; 1 drivers -v0x29f97f0_0 .alias "Command", 2 0, v0x2bc67a0_0; -v0x29f9490_0 .net "OrNorXorOut", 0 0, L_0x2cd3020; 1 drivers -v0x29f9510_0 .net "XorNor", 0 0, L_0x2cd2a80; 1 drivers -v0x29f7ba0_0 .net "nXor", 0 0, L_0x2cd2490; 1 drivers -L_0x2cd2c00 .part v0x2bc78e0_0, 2, 1; -L_0x2cd31f0 .part v0x2bc78e0_0, 0, 1; -S_0x29f1d80 .scope module, "mux0" "TwoInMux" 3 83, 3 8, S_0x29ed7b0; - .timescale -9 -12; -L_0x2cd2720/d .functor NOT 1, L_0x2cd2c00, C4<0>, C4<0>, C4<0>; -L_0x2cd2720 .delay (10000,10000,10000) L_0x2cd2720/d; -L_0x2cd2800/d .functor AND 1, L_0x2cd25a0, L_0x2cd2720, C4<1>, C4<1>; -L_0x2cd2800 .delay (20000,20000,20000) L_0x2cd2800/d; -L_0x2cd2930/d .functor AND 1, L_0x2cd0e90, L_0x2cd2c00, C4<1>, C4<1>; -L_0x2cd2930 .delay (20000,20000,20000) L_0x2cd2930/d; -L_0x2cd2a80/d .functor OR 1, L_0x2cd2800, L_0x2cd2930, C4<0>, C4<0>; -L_0x2cd2a80 .delay (20000,20000,20000) L_0x2cd2a80/d; -v0x29f3710_0 .net "S", 0 0, L_0x2cd2c00; 1 drivers -v0x29f1ad0_0 .alias "in0", 0 0, v0x29f9a60_0; -v0x29f1b70_0 .alias "in1", 0 0, v0x29f9d30_0; -v0x29f5090_0 .net "nS", 0 0, L_0x2cd2720; 1 drivers -v0x29f5130_0 .net "out0", 0 0, L_0x2cd2800; 1 drivers -v0x29f1820_0 .net "out1", 0 0, L_0x2cd2930; 1 drivers -v0x29f1580_0 .alias "outfinal", 0 0, v0x29f9510_0; -S_0x29eb6c0 .scope module, "mux1" "TwoInMux" 3 84, 3 8, S_0x29ed7b0; - .timescale -9 -12; -L_0x2cd2ca0/d .functor NOT 1, L_0x2cd31f0, C4<0>, C4<0>, C4<0>; -L_0x2cd2ca0 .delay (10000,10000,10000) L_0x2cd2ca0/d; -L_0x2cd2d60/d .functor AND 1, L_0x2cd2a80, L_0x2cd2ca0, C4<1>, C4<1>; -L_0x2cd2d60 .delay (20000,20000,20000) L_0x2cd2d60/d; -L_0x2cd2eb0/d .functor AND 1, L_0x2cd2200, L_0x2cd31f0, C4<1>, C4<1>; -L_0x2cd2eb0 .delay (20000,20000,20000) L_0x2cd2eb0/d; -L_0x2cd3020/d .functor OR 1, L_0x2cd2d60, L_0x2cd2eb0, C4<0>, C4<0>; -L_0x2cd3020 .delay (20000,20000,20000) L_0x2cd3020/d; -v0x29f3e70_0 .net "S", 0 0, L_0x2cd31f0; 1 drivers -v0x29f3f10_0 .alias "in0", 0 0, v0x29f9510_0; -v0x29f3bc0_0 .alias "in1", 0 0, v0x29f99e0_0; -v0x29f3c60_0 .net "nS", 0 0, L_0x2cd2ca0; 1 drivers -v0x29f3910_0 .net "out0", 0 0, L_0x2cd2d60; 1 drivers -v0x29f39b0_0 .net "out1", 0 0, L_0x2cd2eb0; 1 drivers -v0x29f3670_0 .alias "outfinal", 0 0, v0x29f9490_0; -S_0x29d4370 .scope generate, "orbits[15]" "orbits[15]" 3 196, 3 196, S_0x29fb160; - .timescale -9 -12; -P_0x29d6238 .param/l "i" 3 196, +C4<01111>; -S_0x29d7930 .scope module, "attempt" "OrNorXor" 3 198, 3 64, S_0x29d4370; - .timescale -9 -12; -L_0x2cd3490/d .functor NOR 1, L_0x2cd4530, L_0x2cd3330, C4<0>, C4<0>; -L_0x2cd3490 .delay (10000,10000,10000) L_0x2cd3490/d; -L_0x2cd3580/d .functor NOT 1, L_0x2cd3490, C4<0>, C4<0>, C4<0>; -L_0x2cd3580 .delay (10000,10000,10000) L_0x2cd3580/d; -L_0x2cd36b0/d .functor NAND 1, L_0x2cd4530, L_0x2cd3330, C4<1>, C4<1>; -L_0x2cd36b0 .delay (10000,10000,10000) L_0x2cd36b0/d; -L_0x2cd3810/d .functor NAND 1, L_0x2cd36b0, L_0x2cd3580, C4<1>, C4<1>; -L_0x2cd3810 .delay (10000,10000,10000) L_0x2cd3810/d; -L_0x2cd3920/d .functor NOT 1, L_0x2cd3810, C4<0>, C4<0>, C4<0>; -L_0x2cd3920 .delay (10000,10000,10000) L_0x2cd3920/d; -v0x29d9f60_0 .net "A", 0 0, L_0x2cd4530; 1 drivers -v0x29d9c40_0 .net "AnandB", 0 0, L_0x2cd36b0; 1 drivers -v0x29d9ce0_0 .net "AnorB", 0 0, L_0x2cd3490; 1 drivers -v0x29e1af0_0 .net "AorB", 0 0, L_0x2cd3580; 1 drivers -v0x29e1b70_0 .net "AxorB", 0 0, L_0x2cd3920; 1 drivers -v0x29e7950_0 .net "B", 0 0, L_0x2cd3330; 1 drivers -v0x29e7a10_0 .alias "Command", 2 0, v0x2bc67a0_0; -v0x266a600_0 .net "OrNorXorOut", 0 0, L_0x2cd4260; 1 drivers -v0x2986f40_0 .net "XorNor", 0 0, L_0x2cd3de0; 1 drivers -v0x2986fc0_0 .net "nXor", 0 0, L_0x2cd3810; 1 drivers -L_0x2cd3f60 .part v0x2bc78e0_0, 2, 1; -L_0x2cd43f0 .part v0x2bc78e0_0, 0, 1; -S_0x29dbd30 .scope module, "mux0" "TwoInMux" 3 83, 3 8, S_0x29d7930; - .timescale -9 -12; -L_0x2cd3a80/d .functor NOT 1, L_0x2cd3f60, C4<0>, C4<0>, C4<0>; -L_0x2cd3a80 .delay (10000,10000,10000) L_0x2cd3a80/d; -L_0x2cd3b60/d .functor AND 1, L_0x2cd3920, L_0x2cd3a80, C4<1>, C4<1>; -L_0x2cd3b60 .delay (20000,20000,20000) L_0x2cd3b60/d; -L_0x2cd3c90/d .functor AND 1, L_0x2cd3490, L_0x2cd3f60, C4<1>, C4<1>; -L_0x2cd3c90 .delay (20000,20000,20000) L_0x2cd3c90/d; -L_0x2cd3de0/d .functor OR 1, L_0x2cd3b60, L_0x2cd3c90, C4<0>, C4<0>; -L_0x2cd3de0 .delay (20000,20000,20000) L_0x2cd3de0/d; -v0x29dc070_0 .net "S", 0 0, L_0x2cd3f60; 1 drivers -v0x29da440_0 .alias "in0", 0 0, v0x29e1b70_0; -v0x29da4e0_0 .alias "in1", 0 0, v0x29d9ce0_0; -v0x29da190_0 .net "nS", 0 0, L_0x2cd3a80; 1 drivers -v0x29da230_0 .net "out0", 0 0, L_0x2cd3b60; 1 drivers -v0x29dd750_0 .net "out1", 0 0, L_0x2cd3c90; 1 drivers -v0x29d9ee0_0 .alias "outfinal", 0 0, v0x2986f40_0; -S_0x29d40c0 .scope module, "mux1" "TwoInMux" 3 84, 3 8, S_0x29d7930; - .timescale -9 -12; -L_0x2cc7450/d .functor NOT 1, L_0x2cd43f0, C4<0>, C4<0>, C4<0>; -L_0x2cc7450 .delay (10000,10000,10000) L_0x2cc7450/d; -L_0x2cd4000/d .functor AND 1, L_0x2cd3de0, L_0x2cc7450, C4<1>, C4<1>; -L_0x2cd4000 .delay (20000,20000,20000) L_0x2cd4000/d; -L_0x2cd4130/d .functor AND 1, L_0x2cd3580, L_0x2cd43f0, C4<1>, C4<1>; -L_0x2cd4130 .delay (20000,20000,20000) L_0x2cd4130/d; -L_0x2cd4260/d .functor OR 1, L_0x2cd4000, L_0x2cd4130, C4<0>, C4<0>; -L_0x2cd4260 .delay (20000,20000,20000) L_0x2cd4260/d; -v0x29d46a0_0 .net "S", 0 0, L_0x2cd43f0; 1 drivers -v0x29d3e20_0 .alias "in0", 0 0, v0x2986f40_0; -v0x29d3ec0_0 .alias "in1", 0 0, v0x29e1af0_0; -v0x29dc530_0 .net "nS", 0 0, L_0x2cc7450; 1 drivers -v0x29dc5b0_0 .net "out0", 0 0, L_0x2cd4000; 1 drivers -v0x29dc280_0 .net "out1", 0 0, L_0x2cd4130; 1 drivers -v0x29dbfd0_0 .alias "outfinal", 0 0, v0x266a600_0; -S_0x29bc7a0 .scope generate, "orbits[16]" "orbits[16]" 3 196, 3 196, S_0x29fb160; - .timescale -9 -12; -P_0x29be678 .param/l "i" 3 196, +C4<010000>; -S_0x29bc500 .scope module, "attempt" "OrNorXor" 3 198, 3 64, S_0x29bc7a0; - .timescale -9 -12; -L_0x2cd33d0/d .functor NOR 1, L_0x2cd45d0, L_0x2cd4670, C4<0>, C4<0>; -L_0x2cd33d0 .delay (10000,10000,10000) L_0x2cd33d0/d; -L_0x2cd4790/d .functor NOT 1, L_0x2cd33d0, C4<0>, C4<0>, C4<0>; -L_0x2cd4790 .delay (10000,10000,10000) L_0x2cd4790/d; -L_0x2cd4880/d .functor NAND 1, L_0x2cd45d0, L_0x2cd4670, C4<1>, C4<1>; -L_0x2cd4880 .delay (10000,10000,10000) L_0x2cd4880/d; -L_0x2cd49c0/d .functor NAND 1, L_0x2cd4880, L_0x2cd4790, C4<1>, C4<1>; -L_0x2cd49c0 .delay (10000,10000,10000) L_0x2cd49c0/d; -L_0x2cd4ab0/d .functor NOT 1, L_0x2cd49c0, C4<0>, C4<0>, C4<0>; -L_0x2cd4ab0 .delay (10000,10000,10000) L_0x2cd4ab0/d; -v0x29ce030_0 .net "A", 0 0, L_0x2cd45d0; 1 drivers -v0x29d6710_0 .net "AnandB", 0 0, L_0x2cd4880; 1 drivers -v0x29d67b0_0 .net "AnorB", 0 0, L_0x2cd33d0; 1 drivers -v0x29d6460_0 .net "AorB", 0 0, L_0x2cd4790; 1 drivers -v0x29d64e0_0 .net "AxorB", 0 0, L_0x2cd4ab0; 1 drivers -v0x29d61b0_0 .net "B", 0 0, L_0x2cd4670; 1 drivers -v0x29d6270_0 .alias "Command", 2 0, v0x2bc67a0_0; -v0x29d5f10_0 .net "OrNorXorOut", 0 0, L_0x2cd5390; 1 drivers -v0x29d5f90_0 .net "XorNor", 0 0, L_0x2cd4eb0; 1 drivers -v0x29d4620_0 .net "nXor", 0 0, L_0x2cd49c0; 1 drivers -L_0x2cd4ff0 .part v0x2bc78e0_0, 2, 1; -L_0x2cd5520 .part v0x2bc78e0_0, 0, 1; -S_0x29d0640 .scope module, "mux0" "TwoInMux" 3 83, 3 8, S_0x29bc500; - .timescale -9 -12; -L_0x2cd4bf0/d .functor NOT 1, L_0x2cd4ff0, C4<0>, C4<0>, C4<0>; -L_0x2cd4bf0 .delay (10000,10000,10000) L_0x2cd4bf0/d; -L_0x2cd4c90/d .functor AND 1, L_0x2cd4ab0, L_0x2cd4bf0, C4<1>, C4<1>; -L_0x2cd4c90 .delay (20000,20000,20000) L_0x2cd4c90/d; -L_0x2cd4d80/d .functor AND 1, L_0x2cd33d0, L_0x2cd4ff0, C4<1>, C4<1>; -L_0x2cd4d80 .delay (20000,20000,20000) L_0x2cd4d80/d; -L_0x2cd4eb0/d .functor OR 1, L_0x2cd4c90, L_0x2cd4d80, C4<0>, C4<0>; -L_0x2cd4eb0 .delay (20000,20000,20000) L_0x2cd4eb0/d; -v0x29d0990_0 .net "S", 0 0, L_0x2cd4ff0; 1 drivers -v0x29d0390_0 .alias "in0", 0 0, v0x29d64e0_0; -v0x29d0430_0 .alias "in1", 0 0, v0x29d67b0_0; -v0x29d00f0_0 .net "nS", 0 0, L_0x2cd4bf0; 1 drivers -v0x29d0190_0 .net "out0", 0 0, L_0x2cd4c90; 1 drivers -v0x29d1b10_0 .net "out1", 0 0, L_0x2cd4d80; 1 drivers -v0x29cdfb0_0 .alias "outfinal", 0 0, v0x29d5f90_0; -S_0x29c43e0 .scope module, "mux1" "TwoInMux" 3 84, 3 8, S_0x29bc500; - .timescale -9 -12; -L_0x2cd5090/d .functor NOT 1, L_0x2cd5520, C4<0>, C4<0>, C4<0>; -L_0x2cd5090 .delay (10000,10000,10000) L_0x2cd5090/d; -L_0x2cd5130/d .functor AND 1, L_0x2cd4eb0, L_0x2cd5090, C4<1>, C4<1>; -L_0x2cd5130 .delay (20000,20000,20000) L_0x2cd5130/d; -L_0x2cd5260/d .functor AND 1, L_0x2cd4790, L_0x2cd5520, C4<1>, C4<1>; -L_0x2cd5260 .delay (20000,20000,20000) L_0x2cd5260/d; -L_0x2cd5390/d .functor OR 1, L_0x2cd5130, L_0x2cd5260, C4<0>, C4<0>; -L_0x2cd5390 .delay (20000,20000,20000) L_0x2cd5390/d; -v0x29bcad0_0 .net "S", 0 0, L_0x2cd5520; 1 drivers -v0x29c22f0_0 .alias "in0", 0 0, v0x29d5f90_0; -v0x29c2390_0 .alias "in1", 0 0, v0x29d6460_0; -v0x29ca240_0 .net "nS", 0 0, L_0x2cd5090; 1 drivers -v0x29ca2c0_0 .net "out0", 0 0, L_0x2cd5130; 1 drivers -v0x29c8150_0 .net "out1", 0 0, L_0x2cd5260; 1 drivers -v0x29d08f0_0 .alias "outfinal", 0 0, v0x29d5f10_0; -S_0x29b0b60 .scope generate, "orbits[17]" "orbits[17]" 3 196, 3 196, S_0x29fb160; - .timescale -9 -12; -P_0x29b1148 .param/l "i" 3 196, +C4<010001>; -S_0x29b08c0 .scope module, "attempt" "OrNorXor" 3 198, 3 64, S_0x29b0b60; - .timescale -9 -12; -L_0x2cd57f0/d .functor NOR 1, L_0x2cd6870, L_0x2cd5660, C4<0>, C4<0>; -L_0x2cd57f0 .delay (10000,10000,10000) L_0x2cd57f0/d; -L_0x2cd58e0/d .functor NOT 1, L_0x2cd57f0, C4<0>, C4<0>, C4<0>; -L_0x2cd58e0 .delay (10000,10000,10000) L_0x2cd58e0/d; -L_0x2cd59d0/d .functor NAND 1, L_0x2cd6870, L_0x2cd5660, C4<1>, C4<1>; -L_0x2cd59d0 .delay (10000,10000,10000) L_0x2cd59d0/d; -L_0x2cd5b10/d .functor NAND 1, L_0x2cd59d0, L_0x2cd58e0, C4<1>, C4<1>; -L_0x2cd5b10 .delay (10000,10000,10000) L_0x2cd5b10/d; -L_0x2cd5c00/d .functor NOT 1, L_0x2cd5b10, C4<0>, C4<0>, C4<0>; -L_0x2cd5c00 .delay (10000,10000,10000) L_0x2cd5c00/d; -v0x29bee70_0 .net "A", 0 0, L_0x2cd6870; 1 drivers -v0x29beb40_0 .net "AnandB", 0 0, L_0x2cd59d0; 1 drivers -v0x29bebe0_0 .net "AnorB", 0 0, L_0x2cd57f0; 1 drivers -v0x29be890_0 .net "AorB", 0 0, L_0x2cd58e0; 1 drivers -v0x29be910_0 .net "AxorB", 0 0, L_0x2cd5c00; 1 drivers -v0x29be5f0_0 .net "B", 0 0, L_0x2cd5660; 1 drivers -v0x29be6b0_0 .alias "Command", 2 0, v0x2bc67a0_0; -v0x29bcd00_0 .net "OrNorXorOut", 0 0, L_0x2cd6560; 1 drivers -v0x29bcd80_0 .net "XorNor", 0 0, L_0x2cd6000; 1 drivers -v0x29bca50_0 .net "nXor", 0 0, L_0x2cd5b10; 1 drivers -L_0x2cd6140 .part v0x2bc78e0_0, 2, 1; -L_0x2cd6730 .part v0x2bc78e0_0, 0, 1; -S_0x29b6c30 .scope module, "mux0" "TwoInMux" 3 83, 3 8, S_0x29b08c0; - .timescale -9 -12; -L_0x2cd5d40/d .functor NOT 1, L_0x2cd6140, C4<0>, C4<0>, C4<0>; -L_0x2cd5d40 .delay (10000,10000,10000) L_0x2cd5d40/d; -L_0x2cd5de0/d .functor AND 1, L_0x2cd5c00, L_0x2cd5d40, C4<1>, C4<1>; -L_0x2cd5de0 .delay (20000,20000,20000) L_0x2cd5de0/d; -L_0x2cd5ed0/d .functor AND 1, L_0x2cd57f0, L_0x2cd6140, C4<1>, C4<1>; -L_0x2cd5ed0 .delay (20000,20000,20000) L_0x2cd5ed0/d; -L_0x2cd6000/d .functor OR 1, L_0x2cd5de0, L_0x2cd5ed0, C4<0>, C4<0>; -L_0x2cd6000 .delay (20000,20000,20000) L_0x2cd6000/d; -v0x29b6f80_0 .net "S", 0 0, L_0x2cd6140; 1 drivers -v0x29ba1f0_0 .alias "in0", 0 0, v0x29be910_0; -v0x29ba290_0 .alias "in1", 0 0, v0x29bebe0_0; -v0x29b6980_0 .net "nS", 0 0, L_0x2cd5d40; 1 drivers -v0x29b6a20_0 .net "out0", 0 0, L_0x2cd5de0; 1 drivers -v0x29b66e0_0 .net "out1", 0 0, L_0x2cd5ed0; 1 drivers -v0x29bedf0_0 .alias "outfinal", 0 0, v0x29bcd80_0; -S_0x29b8fd0 .scope module, "mux1" "TwoInMux" 3 84, 3 8, S_0x29b08c0; - .timescale -9 -12; -L_0x2cd6200/d .functor NOT 1, L_0x2cd6730, C4<0>, C4<0>, C4<0>; -L_0x2cd6200 .delay (10000,10000,10000) L_0x2cd6200/d; -L_0x2cd62c0/d .functor AND 1, L_0x2cd6000, L_0x2cd6200, C4<1>, C4<1>; -L_0x2cd62c0 .delay (20000,20000,20000) L_0x2cd62c0/d; -L_0x2cd6410/d .functor AND 1, L_0x2cd58e0, L_0x2cd6730, C4<1>, C4<1>; -L_0x2cd6410 .delay (20000,20000,20000) L_0x2cd6410/d; -L_0x2cd6560/d .functor OR 1, L_0x2cd62c0, L_0x2cd6410, C4<0>, C4<0>; -L_0x2cd6560 .delay (20000,20000,20000) L_0x2cd6560/d; -v0x29b4450_0 .net "S", 0 0, L_0x2cd6730; 1 drivers -v0x29b8d20_0 .alias "in0", 0 0, v0x29bcd80_0; -v0x29b8dc0_0 .alias "in1", 0 0, v0x29be890_0; -v0x29b8a70_0 .net "nS", 0 0, L_0x2cd6200; 1 drivers -v0x29b8af0_0 .net "out0", 0 0, L_0x2cd62c0; 1 drivers -v0x29b87d0_0 .net "out1", 0 0, L_0x2cd6410; 1 drivers -v0x29b6ee0_0 .alias "outfinal", 0 0, v0x29bcd00_0; -S_0x2999780 .scope generate, "orbits[18]" "orbits[18]" 3 196, 3 196, S_0x29fb160; - .timescale -9 -12; -P_0x299b648 .param/l "i" 3 196, +C4<010010>; -S_0x29994d0 .scope module, "attempt" "OrNorXor" 3 198, 3 64, S_0x2999780; - .timescale -9 -12; -L_0x2cd5700/d .functor NOR 1, L_0x2cd6910, L_0x2cd69b0, C4<0>, C4<0>; -L_0x2cd5700 .delay (10000,10000,10000) L_0x2cd5700/d; -L_0x2cd6ab0/d .functor NOT 1, L_0x2cd5700, C4<0>, C4<0>, C4<0>; -L_0x2cd6ab0 .delay (10000,10000,10000) L_0x2cd6ab0/d; -L_0x2cd6be0/d .functor NAND 1, L_0x2cd6910, L_0x2cd69b0, C4<1>, C4<1>; -L_0x2cd6be0 .delay (10000,10000,10000) L_0x2cd6be0/d; -L_0x2cd6d40/d .functor NAND 1, L_0x2cd6be0, L_0x2cd6ab0, C4<1>, C4<1>; -L_0x2cd6d40 .delay (10000,10000,10000) L_0x2cd6d40/d; -L_0x2cd6e50/d .functor NOT 1, L_0x2cd6d40, C4<0>, C4<0>, C4<0>; -L_0x2cd6e50 .delay (10000,10000,10000) L_0x2cd6e50/d; -v0x29b2f80_0 .net "A", 0 0, L_0x2cd6910; 1 drivers -v0x29b2c50_0 .net "AnandB", 0 0, L_0x2cd6be0; 1 drivers -v0x29b2cf0_0 .net "AnorB", 0 0, L_0x2cd5700; 1 drivers -v0x29b29b0_0 .net "AorB", 0 0, L_0x2cd6ab0; 1 drivers -v0x29b2a30_0 .net "AxorB", 0 0, L_0x2cd6e50; 1 drivers -v0x29b10c0_0 .net "B", 0 0, L_0x2cd69b0; 1 drivers -v0x29b1180_0 .alias "Command", 2 0, v0x2bc67a0_0; -v0x29b0e10_0 .net "OrNorXorOut", 0 0, L_0x2cd7890; 1 drivers -v0x29b0e90_0 .net "XorNor", 0 0, L_0x2cd7310; 1 drivers -v0x29b43d0_0 .net "nXor", 0 0, L_0x2cd6d40; 1 drivers -L_0x2cd7490 .part v0x2bc78e0_0, 2, 1; -L_0x2cd7a60 .part v0x2bc78e0_0, 0, 1; -S_0x29a4ba0 .scope module, "mux0" "TwoInMux" 3 83, 3 8, S_0x29994d0; - .timescale -9 -12; -L_0x2cd6fb0/d .functor NOT 1, L_0x2cd7490, C4<0>, C4<0>, C4<0>; -L_0x2cd6fb0 .delay (10000,10000,10000) L_0x2cd6fb0/d; -L_0x2cd7090/d .functor AND 1, L_0x2cd6e50, L_0x2cd6fb0, C4<1>, C4<1>; -L_0x2cd7090 .delay (20000,20000,20000) L_0x2cd7090/d; -L_0x2cd71c0/d .functor AND 1, L_0x2cd5700, L_0x2cd7490, C4<1>, C4<1>; -L_0x2cd71c0 .delay (20000,20000,20000) L_0x2cd71c0/d; -L_0x2cd7310/d .functor OR 1, L_0x2cd7090, L_0x2cd71c0, C4<0>, C4<0>; -L_0x2cd7310 .delay (20000,20000,20000) L_0x2cd7310/d; -v0x29a6d30_0 .net "S", 0 0, L_0x2cd7490; 1 drivers -v0x29acaf0_0 .alias "in0", 0 0, v0x29b2a30_0; -v0x29acb90_0 .alias "in1", 0 0, v0x29b2cf0_0; -v0x29aaa00_0 .net "nS", 0 0, L_0x2cd6fb0; 1 drivers -v0x29aaaa0_0 .net "out0", 0 0, L_0x2cd7090; 1 drivers -v0x29b31b0_0 .net "out1", 0 0, L_0x2cd71c0; 1 drivers -v0x29b2f00_0 .alias "outfinal", 0 0, v0x29b0e90_0; -S_0x299ca90 .scope module, "mux1" "TwoInMux" 3 84, 3 8, S_0x29994d0; - .timescale -9 -12; -L_0x2cd7530/d .functor NOT 1, L_0x2cd7a60, C4<0>, C4<0>, C4<0>; -L_0x2cd7530 .delay (10000,10000,10000) L_0x2cd7530/d; -L_0x2cd75f0/d .functor AND 1, L_0x2cd7310, L_0x2cd7530, C4<1>, C4<1>; -L_0x2cd75f0 .delay (20000,20000,20000) L_0x2cd75f0/d; -L_0x2cd7740/d .functor AND 1, L_0x2cd6ab0, L_0x2cd7a60, C4<1>, C4<1>; -L_0x2cd7740 .delay (20000,20000,20000) L_0x2cd7740/d; -L_0x2cd7890/d .functor OR 1, L_0x2cd75f0, L_0x2cd7740, C4<0>, C4<0>; -L_0x2cd7890 .delay (20000,20000,20000) L_0x2cd7890/d; -v0x299b0f0_0 .net "S", 0 0, L_0x2cd7a60; 1 drivers -v0x2999220_0 .alias "in0", 0 0, v0x29b0e90_0; -v0x29992c0_0 .alias "in1", 0 0, v0x29b29b0_0; -v0x2998f80_0 .net "nS", 0 0, L_0x2cd7530; 1 drivers -v0x2999000_0 .net "out0", 0 0, L_0x2cd75f0; 1 drivers -v0x29a0e30_0 .net "out1", 0 0, L_0x2cd7740; 1 drivers -v0x29a6c90_0 .alias "outfinal", 0 0, v0x29b0e10_0; -S_0x298f6d0 .scope generate, "orbits[19]" "orbits[19]" 3 196, 3 196, S_0x29fb160; - .timescale -9 -12; -P_0x2987508 .param/l "i" 3 196, +C4<010011>; -S_0x298f430 .scope module, "attempt" "OrNorXor" 3 198, 3 64, S_0x298f6d0; - .timescale -9 -12; -L_0x2cd6a50/d .functor NOR 1, L_0x2cd8ee0, L_0x2cd7ba0, C4<0>, C4<0>; -L_0x2cd6a50 .delay (10000,10000,10000) L_0x2cd6a50/d; -L_0x2cd7df0/d .functor NOT 1, L_0x2cd6a50, C4<0>, C4<0>, C4<0>; -L_0x2cd7df0 .delay (10000,10000,10000) L_0x2cd7df0/d; -L_0x2cd7f20/d .functor NAND 1, L_0x2cd8ee0, L_0x2cd7ba0, C4<1>, C4<1>; -L_0x2cd7f20 .delay (10000,10000,10000) L_0x2cd7f20/d; -L_0x2cd8080/d .functor NAND 1, L_0x2cd7f20, L_0x2cd7df0, C4<1>, C4<1>; -L_0x2cd8080 .delay (10000,10000,10000) L_0x2cd8080/d; -L_0x2cd8190/d .functor NOT 1, L_0x2cd8080, C4<0>, C4<0>, C4<0>; -L_0x2cd8190 .delay (10000,10000,10000) L_0x2cd8190/d; -v0x2993480_0 .net "A", 0 0, L_0x2cd8ee0; 1 drivers -v0x2993160_0 .net "AnandB", 0 0, L_0x2cd7f20; 1 drivers -v0x2993200_0 .net "AnorB", 0 0, L_0x2cd6a50; 1 drivers -v0x299b870_0 .net "AorB", 0 0, L_0x2cd7df0; 1 drivers -v0x299b8f0_0 .net "AxorB", 0 0, L_0x2cd8190; 1 drivers -v0x299b5c0_0 .net "B", 0 0, L_0x2cd7ba0; 1 drivers -v0x299b680_0 .alias "Command", 2 0, v0x2bc67a0_0; -v0x299b310_0 .net "OrNorXorOut", 0 0, L_0x2cd8bd0; 1 drivers -v0x299b390_0 .net "XorNor", 0 0, L_0x2cd8650; 1 drivers -v0x299b070_0 .net "nXor", 0 0, L_0x2cd8080; 1 drivers -L_0x2cd87d0 .part v0x2bc78e0_0, 2, 1; -L_0x2cd8da0 .part v0x2bc78e0_0, 0, 1; -S_0x2995250 .scope module, "mux0" "TwoInMux" 3 83, 3 8, S_0x298f430; - .timescale -9 -12; -L_0x2cd82f0/d .functor NOT 1, L_0x2cd87d0, C4<0>, C4<0>, C4<0>; -L_0x2cd82f0 .delay (10000,10000,10000) L_0x2cd82f0/d; -L_0x2cd83d0/d .functor AND 1, L_0x2cd8190, L_0x2cd82f0, C4<1>, C4<1>; -L_0x2cd83d0 .delay (20000,20000,20000) L_0x2cd83d0/d; -L_0x2cd8500/d .functor AND 1, L_0x2cd6a50, L_0x2cd87d0, C4<1>, C4<1>; -L_0x2cd8500 .delay (20000,20000,20000) L_0x2cd8500/d; -L_0x2cd8650/d .functor OR 1, L_0x2cd83d0, L_0x2cd8500, C4<0>, C4<0>; -L_0x2cd8650 .delay (20000,20000,20000) L_0x2cd8650/d; -v0x2995590_0 .net "S", 0 0, L_0x2cd87d0; 1 drivers -v0x2993960_0 .alias "in0", 0 0, v0x299b8f0_0; -v0x2993a00_0 .alias "in1", 0 0, v0x2993200_0; -v0x29936b0_0 .net "nS", 0 0, L_0x2cd82f0; 1 drivers -v0x2993750_0 .net "out0", 0 0, L_0x2cd83d0; 1 drivers -v0x2996c70_0 .net "out1", 0 0, L_0x2cd8500; 1 drivers -v0x2993400_0 .alias "outfinal", 0 0, v0x299b390_0; -S_0x2990e50 .scope module, "mux1" "TwoInMux" 3 84, 3 8, S_0x298f430; - .timescale -9 -12; -L_0x2cd8870/d .functor NOT 1, L_0x2cd8da0, C4<0>, C4<0>, C4<0>; -L_0x2cd8870 .delay (10000,10000,10000) L_0x2cd8870/d; -L_0x2cd8930/d .functor AND 1, L_0x2cd8650, L_0x2cd8870, C4<1>, C4<1>; -L_0x2cd8930 .delay (20000,20000,20000) L_0x2cd8930/d; -L_0x2cd8a80/d .functor AND 1, L_0x2cd7df0, L_0x2cd8da0, C4<1>, C4<1>; -L_0x2cd8a80 .delay (20000,20000,20000) L_0x2cd8a80/d; -L_0x2cd8bd0/d .functor OR 1, L_0x2cd8930, L_0x2cd8a80, C4<0>, C4<0>; -L_0x2cd8bd0 .delay (20000,20000,20000) L_0x2cd8bd0/d; -v0x298fa00_0 .net "S", 0 0, L_0x2cd8da0; 1 drivers -v0x298d2e0_0 .alias "in0", 0 0, v0x299b390_0; -v0x298d380_0 .alias "in1", 0 0, v0x299b870_0; -v0x2995a50_0 .net "nS", 0 0, L_0x2cd8870; 1 drivers -v0x2995ad0_0 .net "out0", 0 0, L_0x2cd8930; 1 drivers -v0x29957a0_0 .net "out1", 0 0, L_0x2cd8a80; 1 drivers -v0x29954f0_0 .alias "outfinal", 0 0, v0x299b310_0; -S_0x2979800 .scope generate, "orbits[20]" "orbits[20]" 3 196, 3 196, S_0x29fb160; - .timescale -9 -12; -P_0x2977f48 .param/l "i" 3 196, +C4<010100>; -S_0x2976150 .scope module, "attempt" "OrNorXor" 3 198, 3 64, S_0x2979800; - .timescale -9 -12; -L_0x2cd7c40/d .functor NOR 1, L_0x2cd8f80, L_0x2cd9020, C4<0>, C4<0>; -L_0x2cd7c40 .delay (10000,10000,10000) L_0x2cd7c40/d; -L_0x2cd9150/d .functor NOT 1, L_0x2cd7c40, C4<0>, C4<0>, C4<0>; -L_0x2cd9150 .delay (10000,10000,10000) L_0x2cd9150/d; -L_0x2cd9260/d .functor NAND 1, L_0x2cd8f80, L_0x2cd9020, C4<1>, C4<1>; -L_0x2cd9260 .delay (10000,10000,10000) L_0x2cd9260/d; -L_0x2cd93c0/d .functor NAND 1, L_0x2cd9260, L_0x2cd9150, C4<1>, C4<1>; -L_0x2cd93c0 .delay (10000,10000,10000) L_0x2cd93c0/d; -L_0x2cd94d0/d .functor NOT 1, L_0x2cd93c0, C4<0>, C4<0>, C4<0>; -L_0x2cd94d0 .delay (10000,10000,10000) L_0x2cd94d0/d; -v0x2983790_0 .net "A", 0 0, L_0x2cd8f80; 1 drivers -v0x2981620_0 .net "AnandB", 0 0, L_0x2cd9260; 1 drivers -v0x29816c0_0 .net "AnorB", 0 0, L_0x2cd7c40; 1 drivers -v0x2989570_0 .net "AorB", 0 0, L_0x2cd9150; 1 drivers -v0x29895f0_0 .net "AxorB", 0 0, L_0x2cd94d0; 1 drivers -v0x2987480_0 .net "B", 0 0, L_0x2cd9020; 1 drivers -v0x2987540_0 .alias "Command", 2 0, v0x2bc67a0_0; -v0x298fc30_0 .net "OrNorXorOut", 0 0, L_0x2cd9f10; 1 drivers -v0x298fcb0_0 .net "XorNor", 0 0, L_0x2cd9990; 1 drivers -v0x298f980_0 .net "nXor", 0 0, L_0x2cd93c0; 1 drivers -L_0x2cd9b10 .part v0x2bc78e0_0, 2, 1; -L_0x2cda0e0 .part v0x2bc78e0_0, 0, 1; -S_0x297c1d0 .scope module, "mux0" "TwoInMux" 3 83, 3 8, S_0x2976150; - .timescale -9 -12; -L_0x2cd9630/d .functor NOT 1, L_0x2cd9b10, C4<0>, C4<0>, C4<0>; -L_0x2cd9630 .delay (10000,10000,10000) L_0x2cd9630/d; -L_0x2cd9710/d .functor AND 1, L_0x2cd94d0, L_0x2cd9630, C4<1>, C4<1>; -L_0x2cd9710 .delay (20000,20000,20000) L_0x2cd9710/d; -L_0x2cd9840/d .functor AND 1, L_0x2cd7c40, L_0x2cd9b10, C4<1>, C4<1>; -L_0x2cd9840 .delay (20000,20000,20000) L_0x2cd9840/d; -L_0x2cd9990/d .functor OR 1, L_0x2cd9710, L_0x2cd9840, C4<0>, C4<0>; -L_0x2cd9990 .delay (20000,20000,20000) L_0x2cd9990/d; -v0x297dac0_0 .net "S", 0 0, L_0x2cd9b10; 1 drivers -v0x297bf40_0 .alias "in0", 0 0, v0x29895f0_0; -v0x297bfe0_0 .alias "in1", 0 0, v0x29816c0_0; -v0x297bcb0_0 .net "nS", 0 0, L_0x2cd9630; 1 drivers -v0x297bd50_0 .net "out0", 0 0, L_0x2cd9710; 1 drivers -v0x297ba30_0 .net "out1", 0 0, L_0x2cd9840; 1 drivers -v0x2983710_0 .alias "outfinal", 0 0, v0x298fcb0_0; -S_0x2975ed0 .scope module, "mux1" "TwoInMux" 3 84, 3 8, S_0x2976150; - .timescale -9 -12; -L_0x2cd9bb0/d .functor NOT 1, L_0x2cda0e0, C4<0>, C4<0>, C4<0>; -L_0x2cd9bb0 .delay (10000,10000,10000) L_0x2cd9bb0/d; -L_0x2cd9c70/d .functor AND 1, L_0x2cd9990, L_0x2cd9bb0, C4<1>, C4<1>; -L_0x2cd9c70 .delay (20000,20000,20000) L_0x2cd9c70/d; -L_0x2cd9dc0/d .functor AND 1, L_0x2cd9150, L_0x2cda0e0, C4<1>, C4<1>; -L_0x2cd9dc0 .delay (20000,20000,20000) L_0x2cd9dc0/d; -L_0x2cd9f10/d .functor OR 1, L_0x2cd9c70, L_0x2cd9dc0, C4<0>, C4<0>; -L_0x2cd9f10 .delay (20000,20000,20000) L_0x2cd9f10/d; -v0x2976460_0 .net "S", 0 0, L_0x2cda0e0; 1 drivers -v0x297e1c0_0 .alias "in0", 0 0, v0x298fcb0_0; -v0x297e260_0 .alias "in1", 0 0, v0x2989570_0; -v0x297df30_0 .net "nS", 0 0, L_0x2cd9bb0; 1 drivers -v0x297dfb0_0 .net "out0", 0 0, L_0x2cd9c70; 1 drivers -v0x297dca0_0 .net "out1", 0 0, L_0x2cd9dc0; 1 drivers -v0x297da20_0 .alias "outfinal", 0 0, v0x298fc30_0; -S_0x2a1c260 .scope generate, "orbits[21]" "orbits[21]" 3 196, 3 196, S_0x29fb160; - .timescale -9 -12; -P_0x2a54d58 .param/l "i" 3 196, +C4<010101>; -S_0x2a79160 .scope module, "attempt" "OrNorXor" 3 198, 3 64, S_0x2a1c260; - .timescale -9 -12; -L_0x2cd90c0/d .functor NOR 1, L_0x2cdb570, L_0x2cda220, C4<0>, C4<0>; -L_0x2cd90c0 .delay (10000,10000,10000) L_0x2cd90c0/d; -L_0x2cda4a0/d .functor NOT 1, L_0x2cd90c0, C4<0>, C4<0>, C4<0>; -L_0x2cda4a0 .delay (10000,10000,10000) L_0x2cda4a0/d; -L_0x2cda5b0/d .functor NAND 1, L_0x2cdb570, L_0x2cda220, C4<1>, C4<1>; -L_0x2cda5b0 .delay (10000,10000,10000) L_0x2cda5b0/d; -L_0x2cda710/d .functor NAND 1, L_0x2cda5b0, L_0x2cda4a0, C4<1>, C4<1>; -L_0x2cda710 .delay (10000,10000,10000) L_0x2cda710/d; -L_0x2cda820/d .functor NOT 1, L_0x2cda710, C4<0>, C4<0>, C4<0>; -L_0x2cda820 .delay (10000,10000,10000) L_0x2cda820/d; -v0x29786e0_0 .net "A", 0 0, L_0x2cdb570; 1 drivers -v0x29783d0_0 .net "AnandB", 0 0, L_0x2cda5b0; 1 drivers -v0x2978470_0 .net "AnorB", 0 0, L_0x2cd90c0; 1 drivers -v0x2978140_0 .net "AorB", 0 0, L_0x2cda4a0; 1 drivers -v0x29781c0_0 .net "AxorB", 0 0, L_0x2cda820; 1 drivers -v0x2977ec0_0 .net "B", 0 0, L_0x2cda220; 1 drivers -v0x2977f80_0 .alias "Command", 2 0, v0x2bc67a0_0; -v0x2976670_0 .net "OrNorXorOut", 0 0, L_0x2cdb260; 1 drivers -v0x29766f0_0 .net "XorNor", 0 0, L_0x2cdace0; 1 drivers -v0x29763e0_0 .net "nXor", 0 0, L_0x2cda710; 1 drivers -L_0x2cdae60 .part v0x2bc78e0_0, 2, 1; -L_0x2cdb430 .part v0x2bc78e0_0, 0, 1; -S_0x2970880 .scope module, "mux0" "TwoInMux" 3 83, 3 8, S_0x2a79160; - .timescale -9 -12; -L_0x2cda980/d .functor NOT 1, L_0x2cdae60, C4<0>, C4<0>, C4<0>; -L_0x2cda980 .delay (10000,10000,10000) L_0x2cda980/d; -L_0x2cdaa60/d .functor AND 1, L_0x2cda820, L_0x2cda980, C4<1>, C4<1>; -L_0x2cdaa60 .delay (20000,20000,20000) L_0x2cdaa60/d; -L_0x2cdab90/d .functor AND 1, L_0x2cd90c0, L_0x2cdae60, C4<1>, C4<1>; -L_0x2cdab90 .delay (20000,20000,20000) L_0x2cdab90/d; -L_0x2cdace0/d .functor OR 1, L_0x2cdaa60, L_0x2cdab90, C4<0>, C4<0>; -L_0x2cdace0 .delay (20000,20000,20000) L_0x2cdace0/d; -v0x2970bb0_0 .net "S", 0 0, L_0x2cdae60; 1 drivers -v0x2973ca0_0 .alias "in0", 0 0, v0x29781c0_0; -v0x2973d40_0 .alias "in1", 0 0, v0x2978470_0; -v0x29705f0_0 .net "nS", 0 0, L_0x2cda980; 1 drivers -v0x2970690_0 .net "out0", 0 0, L_0x2cdaa60; 1 drivers -v0x2970370_0 .net "out1", 0 0, L_0x2cdab90; 1 drivers -v0x2978660_0 .alias "outfinal", 0 0, v0x29766f0_0; -S_0x2972b00 .scope module, "mux1" "TwoInMux" 3 84, 3 8, S_0x2a79160; - .timescale -9 -12; -L_0x2cdaf00/d .functor NOT 1, L_0x2cdb430, C4<0>, C4<0>, C4<0>; -L_0x2cdaf00 .delay (10000,10000,10000) L_0x2cdaf00/d; -L_0x2cdafc0/d .functor AND 1, L_0x2cdace0, L_0x2cdaf00, C4<1>, C4<1>; -L_0x2cdafc0 .delay (20000,20000,20000) L_0x2cdafc0/d; -L_0x2cdb110/d .functor AND 1, L_0x2cda4a0, L_0x2cdb430, C4<1>, C4<1>; -L_0x2cdb110 .delay (20000,20000,20000) L_0x2cdb110/d; -L_0x2cdb260/d .functor OR 1, L_0x2cdafc0, L_0x2cdb110, C4<0>, C4<0>; -L_0x2cdb260 .delay (20000,20000,20000) L_0x2cdb260/d; -v0x2a3def0_0 .net "S", 0 0, L_0x2cdb430; 1 drivers -v0x2972870_0 .alias "in0", 0 0, v0x29766f0_0; -v0x2972910_0 .alias "in1", 0 0, v0x2978140_0; -v0x29725e0_0 .net "nS", 0 0, L_0x2cdaf00; 1 drivers -v0x2972660_0 .net "out0", 0 0, L_0x2cdafc0; 1 drivers -v0x2972360_0 .net "out1", 0 0, L_0x2cdb110; 1 drivers -v0x2970b10_0 .alias "outfinal", 0 0, v0x2976670_0; -S_0x29810e0 .scope generate, "orbits[22]" "orbits[22]" 3 196, 3 196, S_0x29fb160; - .timescale -9 -12; -P_0x2989098 .param/l "i" 3 196, +C4<010110>; -S_0x29643b0 .scope module, "attempt" "OrNorXor" 3 198, 3 64, S_0x29810e0; - .timescale -9 -12; -L_0x2cda2c0/d .functor NOR 1, L_0x2cdb610, L_0x2cdb6b0, C4<0>, C4<0>; -L_0x2cda2c0 .delay (10000,10000,10000) L_0x2cda2c0/d; -L_0x2cdb810/d .functor NOT 1, L_0x2cda2c0, C4<0>, C4<0>, C4<0>; -L_0x2cdb810 .delay (10000,10000,10000) L_0x2cdb810/d; -L_0x2cdb900/d .functor NAND 1, L_0x2cdb610, L_0x2cdb6b0, C4<1>, C4<1>; -L_0x2cdb900 .delay (10000,10000,10000) L_0x2cdb900/d; -L_0x2cdba60/d .functor NAND 1, L_0x2cdb900, L_0x2cdb810, C4<1>, C4<1>; -L_0x2cdba60 .delay (10000,10000,10000) L_0x2cdba60/d; -L_0x2cdbb70/d .functor NOT 1, L_0x2cdba60, C4<0>, C4<0>, C4<0>; -L_0x2cdbb70 .delay (10000,10000,10000) L_0x2cdbb70/d; -v0x2a5d810_0 .net "A", 0 0, L_0x2cdb610; 1 drivers -v0x2a5a950_0 .net "AnandB", 0 0, L_0x2cdb900; 1 drivers -v0x2a5a9f0_0 .net "AnorB", 0 0, L_0x2cda2c0; 1 drivers -v0x2a57b10_0 .net "AorB", 0 0, L_0x2cdb810; 1 drivers -v0x2a57b90_0 .net "AxorB", 0 0, L_0x2cdbb70; 1 drivers -v0x2a54cd0_0 .net "B", 0 0, L_0x2cdb6b0; 1 drivers -v0x2a54d90_0 .alias "Command", 2 0, v0x2bc67a0_0; -v0x2a21140_0 .net "OrNorXorOut", 0 0, L_0x2cdc5d0; 1 drivers -v0x2a211c0_0 .net "XorNor", 0 0, L_0x2cdc030; 1 drivers -v0x2a3de70_0 .net "nXor", 0 0, L_0x2cdba60; 1 drivers -L_0x2cdc1b0 .part v0x2bc78e0_0, 2, 1; -L_0x2cdc7a0 .part v0x2bc78e0_0, 0, 1; -S_0x2a74660 .scope module, "mux0" "TwoInMux" 3 83, 3 8, S_0x29643b0; - .timescale -9 -12; -L_0x2cdbcd0/d .functor NOT 1, L_0x2cdc1b0, C4<0>, C4<0>, C4<0>; -L_0x2cdbcd0 .delay (10000,10000,10000) L_0x2cdbcd0/d; -L_0x2cdbdb0/d .functor AND 1, L_0x2cdbb70, L_0x2cdbcd0, C4<1>, C4<1>; -L_0x2cdbdb0 .delay (20000,20000,20000) L_0x2cdbdb0/d; -L_0x2cdbee0/d .functor AND 1, L_0x2cda2c0, L_0x2cdc1b0, C4<1>, C4<1>; -L_0x2cdbee0 .delay (20000,20000,20000) L_0x2cdbee0/d; -L_0x2cdc030/d .functor OR 1, L_0x2cdbdb0, L_0x2cdbee0, C4<0>, C4<0>; -L_0x2cdc030 .delay (20000,20000,20000) L_0x2cdc030/d; -v0x2a32610_0 .net "S", 0 0, L_0x2cdc1b0; 1 drivers -v0x2a637b0_0 .alias "in0", 0 0, v0x2a57b90_0; -v0x2a63850_0 .alias "in1", 0 0, v0x2a5a9f0_0; -v0x2a63260_0 .net "nS", 0 0, L_0x2cdbcd0; 1 drivers -v0x2a63300_0 .net "out0", 0 0, L_0x2cdbdb0; 1 drivers -v0x2a605d0_0 .net "out1", 0 0, L_0x2cdbee0; 1 drivers -v0x2a5d790_0 .alias "outfinal", 0 0, v0x2a211c0_0; -S_0x2a3b030 .scope module, "mux1" "TwoInMux" 3 84, 3 8, S_0x29643b0; - .timescale -9 -12; -L_0x2cdc250/d .functor NOT 1, L_0x2cdc7a0, C4<0>, C4<0>, C4<0>; -L_0x2cdc250 .delay (10000,10000,10000) L_0x2cdc250/d; -L_0x2cdc310/d .functor AND 1, L_0x2cdc030, L_0x2cdc250, C4<1>, C4<1>; -L_0x2cdc310 .delay (20000,20000,20000) L_0x2cdc310/d; -L_0x2cdc460/d .functor AND 1, L_0x2cdb810, L_0x2cdc7a0, C4<1>, C4<1>; -L_0x2cdc460 .delay (20000,20000,20000) L_0x2cdc460/d; -L_0x2cdc5d0/d .functor OR 1, L_0x2cdc310, L_0x2cdc460, C4<0>, C4<0>; -L_0x2cdc5d0 .delay (20000,20000,20000) L_0x2cdc5d0/d; -v0x2a381f0_0 .net "S", 0 0, L_0x2cdc7a0; 1 drivers -v0x2a38290_0 .alias "in0", 0 0, v0x2a211c0_0; -v0x2a1e3c0_0 .alias "in1", 0 0, v0x2a57b10_0; -v0x2a1e460_0 .net "nS", 0 0, L_0x2cdc250; 1 drivers -v0x2a353b0_0 .net "out0", 0 0, L_0x2cdc310; 1 drivers -v0x2a35450_0 .net "out1", 0 0, L_0x2cdc460; 1 drivers -v0x2a32570_0 .alias "outfinal", 0 0, v0x2a21140_0; -S_0x29cfb40 .scope generate, "orbits[23]" "orbits[23]" 3 196, 3 196, S_0x29fb160; - .timescale -9 -12; -P_0x29e7478 .param/l "i" 3 196, +C4<010111>; -S_0x29cda70 .scope module, "attempt" "OrNorXor" 3 198, 3 64, S_0x29cfb40; - .timescale -9 -12; -L_0x2cdb750/d .functor NOR 1, L_0x2cddc20, L_0x2cdc8e0, C4<0>, C4<0>; -L_0x2cdb750 .delay (10000,10000,10000) L_0x2cdb750/d; -L_0x2cdcb50/d .functor NOT 1, L_0x2cdb750, C4<0>, C4<0>, C4<0>; -L_0x2cdcb50 .delay (10000,10000,10000) L_0x2cdcb50/d; -L_0x2cdcc60/d .functor NAND 1, L_0x2cddc20, L_0x2cdc8e0, C4<1>, C4<1>; -L_0x2cdcc60 .delay (10000,10000,10000) L_0x2cdcc60/d; -L_0x2cdcdc0/d .functor NAND 1, L_0x2cdcc60, L_0x2cdcb50, C4<1>, C4<1>; -L_0x2cdcdc0 .delay (10000,10000,10000) L_0x2cdcdc0/d; -L_0x2cdced0/d .functor NOT 1, L_0x2cdcdc0, C4<0>, C4<0>, C4<0>; -L_0x2cdced0 .delay (10000,10000,10000) L_0x2cdced0/d; -v0x29a0950_0 .net "A", 0 0, L_0x2cddc20; 1 drivers -v0x296a1c0_0 .net "AnandB", 0 0, L_0x2cdcc60; 1 drivers -v0x296a260_0 .net "AnorB", 0 0, L_0x2cdb750; 1 drivers -v0x298cda0_0 .net "AorB", 0 0, L_0x2cdcb50; 1 drivers -v0x298ce20_0 .net "AxorB", 0 0, L_0x2cdced0; 1 drivers -v0x2989010_0 .net "B", 0 0, L_0x2cdc8e0; 1 drivers -v0x29890d0_0 .alias "Command", 2 0, v0x2bc67a0_0; -v0x28d3b50_0 .net "OrNorXorOut", 0 0, L_0x2cdd910; 1 drivers -v0x29831b0_0 .net "XorNor", 0 0, L_0x2cdd390; 1 drivers -v0x2983230_0 .net "nXor", 0 0, L_0x2cdcdc0; 1 drivers -L_0x2cdd510 .part v0x2bc78e0_0, 2, 1; -L_0x2cddae0 .part v0x2bc78e0_0, 0, 1; -S_0x29ac590 .scope module, "mux0" "TwoInMux" 3 83, 3 8, S_0x29cda70; - .timescale -9 -12; -L_0x2cdd030/d .functor NOT 1, L_0x2cdd510, C4<0>, C4<0>, C4<0>; -L_0x2cdd030 .delay (10000,10000,10000) L_0x2cdd030/d; -L_0x2cdd110/d .functor AND 1, L_0x2cdced0, L_0x2cdd030, C4<1>, C4<1>; -L_0x2cdd110 .delay (20000,20000,20000) L_0x2cdd110/d; -L_0x2cdd240/d .functor AND 1, L_0x2cdb750, L_0x2cdd510, C4<1>, C4<1>; -L_0x2cdd240 .delay (20000,20000,20000) L_0x2cdd240/d; -L_0x2cdd390/d .functor OR 1, L_0x2cdd110, L_0x2cdd240, C4<0>, C4<0>; -L_0x2cdd390 .delay (20000,20000,20000) L_0x2cdd390/d; -v0x296c2a0_0 .net "S", 0 0, L_0x2cdd510; 1 drivers -v0x29aa4c0_0 .alias "in0", 0 0, v0x298ce20_0; -v0x29aa560_0 .alias "in1", 0 0, v0x296a260_0; -v0x29a6730_0 .net "nS", 0 0, L_0x2cdd030; 1 drivers -v0x29a67d0_0 .net "out0", 0 0, L_0x2cdd110; 1 drivers -v0x29a4660_0 .net "out1", 0 0, L_0x2cdd240; 1 drivers -v0x29a08d0_0 .alias "outfinal", 0 0, v0x29831b0_0; -S_0x29c9ce0 .scope module, "mux1" "TwoInMux" 3 84, 3 8, S_0x29cda70; - .timescale -9 -12; -L_0x2cdd5b0/d .functor NOT 1, L_0x2cddae0, C4<0>, C4<0>, C4<0>; -L_0x2cdd5b0 .delay (10000,10000,10000) L_0x2cdd5b0/d; -L_0x2cdd670/d .functor AND 1, L_0x2cdd390, L_0x2cdd5b0, C4<1>, C4<1>; -L_0x2cdd670 .delay (20000,20000,20000) L_0x2cdd670/d; -L_0x2cdd7c0/d .functor AND 1, L_0x2cdcb50, L_0x2cddae0, C4<1>, C4<1>; -L_0x2cdd7c0 .delay (20000,20000,20000) L_0x2cdd7c0/d; -L_0x2cdd910/d .functor OR 1, L_0x2cdd670, L_0x2cdd7c0, C4<0>, C4<0>; -L_0x2cdd910 .delay (20000,20000,20000) L_0x2cdd910/d; -v0x29e1610_0 .net "S", 0 0, L_0x2cddae0; 1 drivers -v0x29c7c10_0 .alias "in0", 0 0, v0x29831b0_0; -v0x29c7cb0_0 .alias "in1", 0 0, v0x298cda0_0; -v0x29c3e80_0 .net "nS", 0 0, L_0x2cdd5b0; 1 drivers -v0x29c3f00_0 .net "out0", 0 0, L_0x2cdd670; 1 drivers -v0x29c1db0_0 .net "out1", 0 0, L_0x2cdd7c0; 1 drivers -v0x296c200_0 .alias "outfinal", 0 0, v0x28d3b50_0; -S_0x2aef130 .scope generate, "orbits[24]" "orbits[24]" 3 196, 3 196, S_0x29fb160; - .timescale -9 -12; -P_0x2af0a98 .param/l "i" 3 196, +C4<011000>; -S_0x2aeee90 .scope module, "attempt" "OrNorXor" 3 198, 3 64, S_0x2aef130; - .timescale -9 -12; -L_0x2cdc980/d .functor NOR 1, L_0x2cddcc0, L_0x2cddd60, C4<0>, C4<0>; -L_0x2cdc980 .delay (10000,10000,10000) L_0x2cdc980/d; -L_0x2cdca70/d .functor NOT 1, L_0x2cdc980, C4<0>, C4<0>, C4<0>; -L_0x2cdca70 .delay (10000,10000,10000) L_0x2cdca70/d; -L_0x2cddfa0/d .functor NAND 1, L_0x2cddcc0, L_0x2cddd60, C4<1>, C4<1>; -L_0x2cddfa0 .delay (10000,10000,10000) L_0x2cddfa0/d; -L_0x2cde100/d .functor NAND 1, L_0x2cddfa0, L_0x2cdca70, C4<1>, C4<1>; -L_0x2cde100 .delay (10000,10000,10000) L_0x2cde100/d; -L_0x2cde210/d .functor NOT 1, L_0x2cde100, C4<0>, C4<0>, C4<0>; -L_0x2cde210 .delay (10000,10000,10000) L_0x2cde210/d; -v0x2a02b00_0 .net "A", 0 0, L_0x2cddcc0; 1 drivers -v0x29ed250_0 .net "AnandB", 0 0, L_0x2cddfa0; 1 drivers -v0x29ed2f0_0 .net "AnorB", 0 0, L_0x2cdc980; 1 drivers -v0x29eb180_0 .net "AorB", 0 0, L_0x2cdca70; 1 drivers -v0x29eb200_0 .net "AxorB", 0 0, L_0x2cde210; 1 drivers -v0x29e73f0_0 .net "B", 0 0, L_0x2cddd60; 1 drivers -v0x29e74b0_0 .alias "Command", 2 0, v0x2bc67a0_0; -v0x29e5320_0 .net "OrNorXorOut", 0 0, L_0x2cdec50; 1 drivers -v0x29e53a0_0 .net "XorNor", 0 0, L_0x2cde6d0; 1 drivers -v0x29e1590_0 .net "nXor", 0 0, L_0x2cde100; 1 drivers -L_0x2cde850 .part v0x2bc78e0_0, 2, 1; -L_0x2cdee20 .part v0x2bc78e0_0, 0, 1; -S_0x2a0e740 .scope module, "mux0" "TwoInMux" 3 83, 3 8, S_0x2aeee90; - .timescale -9 -12; -L_0x2cde370/d .functor NOT 1, L_0x2cde850, C4<0>, C4<0>, C4<0>; -L_0x2cde370 .delay (10000,10000,10000) L_0x2cde370/d; -L_0x2cde450/d .functor AND 1, L_0x2cde210, L_0x2cde370, C4<1>, C4<1>; -L_0x2cde450 .delay (20000,20000,20000) L_0x2cde450/d; -L_0x2cde580/d .functor AND 1, L_0x2cdc980, L_0x2cde850, C4<1>, C4<1>; -L_0x2cde580 .delay (20000,20000,20000) L_0x2cde580/d; -L_0x2cde6d0/d .functor OR 1, L_0x2cde450, L_0x2cde580, C4<0>, C4<0>; -L_0x2cde6d0 .delay (20000,20000,20000) L_0x2cde6d0/d; -v0x2a108b0_0 .net "S", 0 0, L_0x2cde850; 1 drivers -v0x2a0a9b0_0 .alias "in0", 0 0, v0x29eb200_0; -v0x2a0aa50_0 .alias "in1", 0 0, v0x29ed2f0_0; -v0x2a088e0_0 .net "nS", 0 0, L_0x2cde370; 1 drivers -v0x2a08980_0 .net "out0", 0 0, L_0x2cde450; 1 drivers -v0x2a04b50_0 .net "out1", 0 0, L_0x2cde580; 1 drivers -v0x2a02a80_0 .alias "outfinal", 0 0, v0x29e53a0_0; -S_0x2aeebf0 .scope module, "mux1" "TwoInMux" 3 84, 3 8, S_0x2aeee90; - .timescale -9 -12; -L_0x2cde8f0/d .functor NOT 1, L_0x2cdee20, C4<0>, C4<0>, C4<0>; -L_0x2cde8f0 .delay (10000,10000,10000) L_0x2cde8f0/d; -L_0x2cde9b0/d .functor AND 1, L_0x2cde6d0, L_0x2cde8f0, C4<1>, C4<1>; -L_0x2cde9b0 .delay (20000,20000,20000) L_0x2cde9b0/d; -L_0x2cdeb00/d .functor AND 1, L_0x2cdca70, L_0x2cdee20, C4<1>, C4<1>; -L_0x2cdeb00 .delay (20000,20000,20000) L_0x2cdeb00/d; -L_0x2cdec50/d .functor OR 1, L_0x2cde9b0, L_0x2cdeb00, C4<0>, C4<0>; -L_0x2cdec50 .delay (20000,20000,20000) L_0x2cdec50/d; -v0x2af0210_0 .net "S", 0 0, L_0x2cdee20; 1 drivers -v0x2aee950_0 .alias "in0", 0 0, v0x29e53a0_0; -v0x2aee9f0_0 .alias "in1", 0 0, v0x29eb180_0; -v0x2aee650_0 .net "nS", 0 0, L_0x2cde8f0; 1 drivers -v0x2aee6d0_0 .net "out0", 0 0, L_0x2cde9b0; 1 drivers -v0x2aee0d0_0 .net "out1", 0 0, L_0x2cdeb00; 1 drivers -v0x2a10810_0 .alias "outfinal", 0 0, v0x29e5320_0; -S_0x28bcf10 .scope generate, "orbits[25]" "orbits[25]" 3 196, 3 196, S_0x29fb160; - .timescale -9 -12; -P_0x28bfcb8 .param/l "i" 3 196, +C4<011001>; -S_0x28ba770 .scope module, "attempt" "OrNorXor" 3 198, 3 64, S_0x28bcf10; - .timescale -9 -12; -L_0x2cdde00/d .functor NOR 1, L_0x2ce02a0, L_0x2cdef60, C4<0>, C4<0>; -L_0x2cdde00 .delay (10000,10000,10000) L_0x2cdde00/d; -L_0x2cdf1b0/d .functor NOT 1, L_0x2cdde00, C4<0>, C4<0>, C4<0>; -L_0x2cdf1b0 .delay (10000,10000,10000) L_0x2cdf1b0/d; -L_0x2cdf2e0/d .functor NAND 1, L_0x2ce02a0, L_0x2cdef60, C4<1>, C4<1>; -L_0x2cdf2e0 .delay (10000,10000,10000) L_0x2cdf2e0/d; -L_0x2cdf440/d .functor NAND 1, L_0x2cdf2e0, L_0x2cdf1b0, C4<1>, C4<1>; -L_0x2cdf440 .delay (10000,10000,10000) L_0x2cdf440/d; -L_0x2cdf550/d .functor NOT 1, L_0x2cdf440, C4<0>, C4<0>, C4<0>; -L_0x2cdf550 .delay (10000,10000,10000) L_0x2cdf550/d; -v0x2966540_0 .net "A", 0 0, L_0x2ce02a0; 1 drivers -v0x2af0f50_0 .net "AnandB", 0 0, L_0x2cdf2e0; 1 drivers -v0x2af0ff0_0 .net "AnorB", 0 0, L_0x2cdde00; 1 drivers -v0x2af0cb0_0 .net "AorB", 0 0, L_0x2cdf1b0; 1 drivers -v0x2af0d30_0 .net "AxorB", 0 0, L_0x2cdf550; 1 drivers -v0x2af0a10_0 .net "B", 0 0, L_0x2cdef60; 1 drivers -v0x2af0ad0_0 .alias "Command", 2 0, v0x2bc67a0_0; -v0x2af0710_0 .net "OrNorXorOut", 0 0, L_0x2cdff90; 1 drivers -v0x2af0790_0 .net "XorNor", 0 0, L_0x2cdfa10; 1 drivers -v0x2af0190_0 .net "nXor", 0 0, L_0x2cdf440; 1 drivers -L_0x2cdfb90 .part v0x2bc78e0_0, 2, 1; -L_0x2ce0160 .part v0x2bc78e0_0, 0, 1; -S_0x28f1420 .scope module, "mux0" "TwoInMux" 3 83, 3 8, S_0x28ba770; - .timescale -9 -12; -L_0x2cdf6b0/d .functor NOT 1, L_0x2cdfb90, C4<0>, C4<0>, C4<0>; -L_0x2cdf6b0 .delay (10000,10000,10000) L_0x2cdf6b0/d; -L_0x2cdf790/d .functor AND 1, L_0x2cdf550, L_0x2cdf6b0, C4<1>, C4<1>; -L_0x2cdf790 .delay (20000,20000,20000) L_0x2cdf790/d; -L_0x2cdf8c0/d .functor AND 1, L_0x2cdde00, L_0x2cdfb90, C4<1>, C4<1>; -L_0x2cdf8c0 .delay (20000,20000,20000) L_0x2cdf8c0/d; -L_0x2cdfa10/d .functor OR 1, L_0x2cdf790, L_0x2cdf8c0, C4<0>, C4<0>; -L_0x2cdfa10 .delay (20000,20000,20000) L_0x2cdfa10/d; -v0x2896a30_0 .net "S", 0 0, L_0x2cdfb90; 1 drivers -v0x2af2400_0 .alias "in0", 0 0, v0x2af0d30_0; -v0x2af24a0_0 .alias "in1", 0 0, v0x2af0ff0_0; -v0x2af2160_0 .net "nS", 0 0, L_0x2cdf6b0; 1 drivers -v0x2af2200_0 .net "out0", 0 0, L_0x2cdf790; 1 drivers -v0x2af11f0_0 .net "out1", 0 0, L_0x2cdf8c0; 1 drivers -v0x29664c0_0 .alias "outfinal", 0 0, v0x2af0790_0; -S_0x28ba260 .scope module, "mux1" "TwoInMux" 3 84, 3 8, S_0x28ba770; - .timescale -9 -12; -L_0x2cdfc30/d .functor NOT 1, L_0x2ce0160, C4<0>, C4<0>, C4<0>; -L_0x2cdfc30 .delay (10000,10000,10000) L_0x2cdfc30/d; -L_0x2cdfcf0/d .functor AND 1, L_0x2cdfa10, L_0x2cdfc30, C4<1>, C4<1>; -L_0x2cdfcf0 .delay (20000,20000,20000) L_0x2cdfcf0/d; -L_0x2cdfe40/d .functor AND 1, L_0x2cdf1b0, L_0x2ce0160, C4<1>, C4<1>; -L_0x2cdfe40 .delay (20000,20000,20000) L_0x2cdfe40/d; -L_0x2cdff90/d .functor OR 1, L_0x2cdfcf0, L_0x2cdfe40, C4<0>, C4<0>; -L_0x2cdff90 .delay (20000,20000,20000) L_0x2cdff90/d; -v0x2898fa0_0 .net "S", 0 0, L_0x2ce0160; 1 drivers -v0x28b7b10_0 .alias "in0", 0 0, v0x2af0790_0; -v0x28b7bb0_0 .alias "in1", 0 0, v0x2af0cb0_0; -v0x28b7600_0 .net "nS", 0 0, L_0x2cdfc30; 1 drivers -v0x28b7680_0 .net "out0", 0 0, L_0x2cdfcf0; 1 drivers -v0x28b4eb0_0 .net "out1", 0 0, L_0x2cdfe40; 1 drivers -v0x2896990_0 .alias "outfinal", 0 0, v0x2af0710_0; -S_0x28d0ef0 .scope generate, "orbits[26]" "orbits[26]" 3 196, 3 196, S_0x29fb160; - .timescale -9 -12; -P_0x28d6328 .param/l "i" 3 196, +C4<011010>; -S_0x28d09e0 .scope module, "attempt" "OrNorXor" 3 198, 3 64, S_0x28d0ef0; - .timescale -9 -12; -L_0x2cdf000/d .functor NOR 1, L_0x2ce0340, L_0x2ce03e0, C4<0>, C4<0>; -L_0x2cdf000 .delay (10000,10000,10000) L_0x2cdf000/d; -L_0x2cdf110/d .functor NOT 1, L_0x2cdf000, C4<0>, C4<0>, C4<0>; -L_0x2cdf110 .delay (10000,10000,10000) L_0x2cdf110/d; -L_0x2ce0630/d .functor NAND 1, L_0x2ce0340, L_0x2ce03e0, C4<1>, C4<1>; -L_0x2ce0630 .delay (10000,10000,10000) L_0x2ce0630/d; -L_0x2ce0790/d .functor NAND 1, L_0x2ce0630, L_0x2cdf110, C4<1>, C4<1>; -L_0x2ce0790 .delay (10000,10000,10000) L_0x2ce0790/d; -L_0x2ce08a0/d .functor NOT 1, L_0x2ce0790, C4<0>, C4<0>, C4<0>; -L_0x2ce08a0 .delay (10000,10000,10000) L_0x2ce08a0/d; -v0x28c2f20_0 .net "A", 0 0, L_0x2ce0340; 1 drivers -v0x28c2950_0 .net "AnandB", 0 0, L_0x2ce0630; 1 drivers -v0x28c29f0_0 .net "AnorB", 0 0, L_0x2cdf000; 1 drivers -v0x28c0180_0 .net "AorB", 0 0, L_0x2cdf110; 1 drivers -v0x28c0200_0 .net "AxorB", 0 0, L_0x2ce08a0; 1 drivers -v0x28bfc30_0 .net "B", 0 0, L_0x2ce03e0; 1 drivers -v0x28bfcf0_0 .alias "Command", 2 0, v0x2bc67a0_0; -v0x28bd460_0 .net "OrNorXorOut", 0 0, L_0x2ce1300; 1 drivers -v0x28bd4e0_0 .net "XorNor", 0 0, L_0x2ce0d60; 1 drivers -v0x2898f20_0 .net "nXor", 0 0, L_0x2ce0790; 1 drivers -L_0x2ce0ee0 .part v0x2bc78e0_0, 2, 1; -L_0x2ce14d0 .part v0x2bc78e0_0, 0, 1; -S_0x28c88e0 .scope module, "mux0" "TwoInMux" 3 83, 3 8, S_0x28d09e0; - .timescale -9 -12; -L_0x2ce0a00/d .functor NOT 1, L_0x2ce0ee0, C4<0>, C4<0>, C4<0>; -L_0x2ce0a00 .delay (10000,10000,10000) L_0x2ce0a00/d; -L_0x2ce0ae0/d .functor AND 1, L_0x2ce08a0, L_0x2ce0a00, C4<1>, C4<1>; -L_0x2ce0ae0 .delay (20000,20000,20000) L_0x2ce0ae0/d; -L_0x2ce0c10/d .functor AND 1, L_0x2cdf000, L_0x2ce0ee0, C4<1>, C4<1>; -L_0x2ce0c10 .delay (20000,20000,20000) L_0x2ce0c10/d; -L_0x2ce0d60/d .functor OR 1, L_0x2ce0ae0, L_0x2ce0c10, C4<0>, C4<0>; -L_0x2ce0d60 .delay (20000,20000,20000) L_0x2ce0d60/d; -v0x28cb150_0 .net "S", 0 0, L_0x2ce0ee0; 1 drivers -v0x28c8390_0 .alias "in0", 0 0, v0x28c0200_0; -v0x28c8430_0 .alias "in1", 0 0, v0x28c29f0_0; -v0x28c5bc0_0 .net "nS", 0 0, L_0x2ce0a00; 1 drivers -v0x28c5c60_0 .net "out0", 0 0, L_0x2ce0ae0; 1 drivers -v0x28c5670_0 .net "out1", 0 0, L_0x2ce0c10; 1 drivers -v0x28c2ea0_0 .alias "outfinal", 0 0, v0x28bd4e0_0; -S_0x28ce290 .scope module, "mux1" "TwoInMux" 3 84, 3 8, S_0x28d09e0; - .timescale -9 -12; -L_0x2ce0f80/d .functor NOT 1, L_0x2ce14d0, C4<0>, C4<0>, C4<0>; -L_0x2ce0f80 .delay (10000,10000,10000) L_0x2ce0f80/d; -L_0x2ce1040/d .functor AND 1, L_0x2ce0d60, L_0x2ce0f80, C4<1>, C4<1>; -L_0x2ce1040 .delay (20000,20000,20000) L_0x2ce1040/d; -L_0x2ce1190/d .functor AND 1, L_0x2cdf110, L_0x2ce14d0, C4<1>, C4<1>; -L_0x2ce1190 .delay (20000,20000,20000) L_0x2ce1190/d; -L_0x2ce1300/d .functor OR 1, L_0x2ce1040, L_0x2ce1190, C4<0>, C4<0>; -L_0x2ce1300 .delay (20000,20000,20000) L_0x2ce1300/d; -v0x28cdd80_0 .net "S", 0 0, L_0x2ce14d0; 1 drivers -v0x28cde20_0 .alias "in0", 0 0, v0x28bd4e0_0; -v0x289b670_0 .alias "in1", 0 0, v0x28c0180_0; -v0x289b710_0 .net "nS", 0 0, L_0x2ce0f80; 1 drivers -v0x28cb600_0 .net "out0", 0 0, L_0x2ce1040; 1 drivers -v0x28cb6a0_0 .net "out1", 0 0, L_0x2ce1190; 1 drivers -v0x28cb0b0_0 .alias "outfinal", 0 0, v0x28bd460_0; -S_0x289e330 .scope generate, "orbits[27]" "orbits[27]" 3 196, 3 196, S_0x29fb160; - .timescale -9 -12; -P_0x28eca78 .param/l "i" 3 196, +C4<011011>; -S_0x28e7500 .scope module, "attempt" "OrNorXor" 3 198, 3 64, S_0x289e330; - .timescale -9 -12; -L_0x2ce0480/d .functor NOR 1, L_0x2ce2960, L_0x2ce1610, C4<0>, C4<0>; -L_0x2ce0480 .delay (10000,10000,10000) L_0x2ce0480/d; -L_0x2ce1890/d .functor NOT 1, L_0x2ce0480, C4<0>, C4<0>, C4<0>; -L_0x2ce1890 .delay (10000,10000,10000) L_0x2ce1890/d; -L_0x2ce19a0/d .functor NAND 1, L_0x2ce2960, L_0x2ce1610, C4<1>, C4<1>; -L_0x2ce19a0 .delay (10000,10000,10000) L_0x2ce19a0/d; -L_0x2ce1b00/d .functor NAND 1, L_0x2ce19a0, L_0x2ce1890, C4<1>, C4<1>; -L_0x2ce1b00 .delay (10000,10000,10000) L_0x2ce1b00/d; -L_0x2ce1c10/d .functor NOT 1, L_0x2ce1b00, C4<0>, C4<0>, C4<0>; -L_0x2ce1c10 .delay (10000,10000,10000) L_0x2ce1c10/d; -v0x28d9490_0 .net "A", 0 0, L_0x2ce2960; 1 drivers -v0x28d8f00_0 .net "AnandB", 0 0, L_0x2ce19a0; 1 drivers -v0x28d8fa0_0 .net "AnorB", 0 0, L_0x2ce0480; 1 drivers -v0x28d67b0_0 .net "AorB", 0 0, L_0x2ce1890; 1 drivers -v0x28d6830_0 .net "AxorB", 0 0, L_0x2ce1c10; 1 drivers -v0x28d62a0_0 .net "B", 0 0, L_0x2ce1610; 1 drivers -v0x28d6360_0 .alias "Command", 2 0, v0x2bc67a0_0; -v0x28d3be0_0 .net "OrNorXorOut", 0 0, L_0x2ce2650; 1 drivers -v0x28d3640_0 .net "XorNor", 0 0, L_0x2ce20d0; 1 drivers -v0x28d36c0_0 .net "nXor", 0 0, L_0x2ce1b00; 1 drivers -L_0x2ce2250 .part v0x2bc78e0_0, 2, 1; -L_0x2ce2820 .part v0x2bc78e0_0, 0, 1; -S_0x28deda0 .scope module, "mux0" "TwoInMux" 3 83, 3 8, S_0x28e7500; - .timescale -9 -12; -L_0x2ce1d70/d .functor NOT 1, L_0x2ce2250, C4<0>, C4<0>, C4<0>; -L_0x2ce1d70 .delay (10000,10000,10000) L_0x2ce1d70/d; -L_0x2ce1e50/d .functor AND 1, L_0x2ce1c10, L_0x2ce1d70, C4<1>, C4<1>; -L_0x2ce1e50 .delay (20000,20000,20000) L_0x2ce1e50/d; -L_0x2ce1f80/d .functor AND 1, L_0x2ce0480, L_0x2ce2250, C4<1>, C4<1>; -L_0x2ce1f80 .delay (20000,20000,20000) L_0x2ce1f80/d; -L_0x2ce20d0/d .functor OR 1, L_0x2ce1e50, L_0x2ce1f80, C4<0>, C4<0>; -L_0x2ce20d0 .delay (20000,20000,20000) L_0x2ce20d0/d; -v0x28e1610_0 .net "S", 0 0, L_0x2ce2250; 1 drivers -v0x28de850_0 .alias "in0", 0 0, v0x28d6830_0; -v0x28de8f0_0 .alias "in1", 0 0, v0x28d8fa0_0; -v0x28dc070_0 .net "nS", 0 0, L_0x2ce1d70; 1 drivers -v0x28dc110_0 .net "out0", 0 0, L_0x2ce1e50; 1 drivers -v0x28dbb60_0 .net "out1", 0 0, L_0x2ce1f80; 1 drivers -v0x28d9410_0 .alias "outfinal", 0 0, v0x28d3640_0; -S_0x28e6fb0 .scope module, "mux1" "TwoInMux" 3 84, 3 8, S_0x28e7500; - .timescale -9 -12; -L_0x2ce22f0/d .functor NOT 1, L_0x2ce2820, C4<0>, C4<0>, C4<0>; -L_0x2ce22f0 .delay (10000,10000,10000) L_0x2ce22f0/d; -L_0x2ce23b0/d .functor AND 1, L_0x2ce20d0, L_0x2ce22f0, C4<1>, C4<1>; -L_0x2ce23b0 .delay (20000,20000,20000) L_0x2ce23b0/d; -L_0x2ce2500/d .functor AND 1, L_0x2ce1890, L_0x2ce2820, C4<1>, C4<1>; -L_0x2ce2500 .delay (20000,20000,20000) L_0x2ce2500/d; -L_0x2ce2650/d .functor OR 1, L_0x2ce23b0, L_0x2ce2500, C4<0>, C4<0>; -L_0x2ce2650 .delay (20000,20000,20000) L_0x2ce2650/d; -v0x28e9d50_0 .net "S", 0 0, L_0x2ce2820; 1 drivers -v0x28e47e0_0 .alias "in0", 0 0, v0x28d3640_0; -v0x28e4880_0 .alias "in1", 0 0, v0x28d67b0_0; -v0x28e4290_0 .net "nS", 0 0, L_0x2ce22f0; 1 drivers -v0x28e4310_0 .net "out0", 0 0, L_0x2ce23b0; 1 drivers -v0x28e1ac0_0 .net "out1", 0 0, L_0x2ce2500; 1 drivers -v0x28e1570_0 .alias "outfinal", 0 0, v0x28d3be0_0; -S_0x28af5f0 .scope generate, "orbits[28]" "orbits[28]" 3 196, 3 196, S_0x29fb160; - .timescale -9 -12; -P_0x2a17788 .param/l "i" 3 196, +C4<011100>; -S_0x28af0e0 .scope module, "attempt" "OrNorXor" 3 198, 3 64, S_0x28af5f0; - .timescale -9 -12; -L_0x2ce16b0/d .functor NOR 1, L_0x2ce2a00, L_0x2ce2aa0, C4<0>, C4<0>; -L_0x2ce16b0 .delay (10000,10000,10000) L_0x2ce16b0/d; -L_0x2ce17a0/d .functor NOT 1, L_0x2ce16b0, C4<0>, C4<0>, C4<0>; -L_0x2ce17a0 .delay (10000,10000,10000) L_0x2ce17a0/d; -L_0x2ce2ce0/d .functor NAND 1, L_0x2ce2a00, L_0x2ce2aa0, C4<1>, C4<1>; -L_0x2ce2ce0 .delay (10000,10000,10000) L_0x2ce2ce0/d; -L_0x2ce2e40/d .functor NAND 1, L_0x2ce2ce0, L_0x2ce17a0, C4<1>, C4<1>; -L_0x2ce2e40 .delay (10000,10000,10000) L_0x2ce2e40/d; -L_0x2ce2f50/d .functor NOT 1, L_0x2ce2e40, C4<0>, C4<0>, C4<0>; -L_0x2ce2f50 .delay (10000,10000,10000) L_0x2ce2f50/d; -v0x28a10d0_0 .net "A", 0 0, L_0x2ce2a00; 1 drivers -v0x289e880_0 .net "AnandB", 0 0, L_0x2ce2ce0; 1 drivers -v0x289e920_0 .net "AnorB", 0 0, L_0x2ce16b0; 1 drivers -v0x28ecf40_0 .net "AorB", 0 0, L_0x2ce17a0; 1 drivers -v0x28ecfc0_0 .net "AxorB", 0 0, L_0x2ce2f50; 1 drivers -v0x28ec9f0_0 .net "B", 0 0, L_0x2ce2aa0; 1 drivers -v0x28ecab0_0 .alias "Command", 2 0, v0x2bc67a0_0; -v0x28ea220_0 .net "OrNorXorOut", 0 0, L_0x2ce3990; 1 drivers -v0x28ea2a0_0 .net "XorNor", 0 0, L_0x2ce3410; 1 drivers -v0x28e9cd0_0 .net "nXor", 0 0, L_0x2ce2e40; 1 drivers -L_0x2ce3590 .part v0x2bc78e0_0, 2, 1; -L_0x2ce3b60 .part v0x2bc78e0_0, 0, 1; -S_0x28a6a90 .scope module, "mux0" "TwoInMux" 3 83, 3 8, S_0x28af0e0; - .timescale -9 -12; -L_0x2ce30b0/d .functor NOT 1, L_0x2ce3590, C4<0>, C4<0>, C4<0>; -L_0x2ce30b0 .delay (10000,10000,10000) L_0x2ce30b0/d; -L_0x2ce3190/d .functor AND 1, L_0x2ce2f50, L_0x2ce30b0, C4<1>, C4<1>; -L_0x2ce3190 .delay (20000,20000,20000) L_0x2ce3190/d; -L_0x2ce32c0/d .functor AND 1, L_0x2ce16b0, L_0x2ce3590, C4<1>, C4<1>; -L_0x2ce32c0 .delay (20000,20000,20000) L_0x2ce32c0/d; -L_0x2ce3410/d .functor OR 1, L_0x2ce3190, L_0x2ce32c0, C4<0>, C4<0>; -L_0x2ce3410 .delay (20000,20000,20000) L_0x2ce3410/d; -v0x28a7080_0 .net "S", 0 0, L_0x2ce3590; 1 drivers -v0x28a42c0_0 .alias "in0", 0 0, v0x28ecfc0_0; -v0x28a4360_0 .alias "in1", 0 0, v0x289e920_0; -v0x28a3d70_0 .net "nS", 0 0, L_0x2ce30b0; 1 drivers -v0x28a3e10_0 .net "out0", 0 0, L_0x2ce3190; 1 drivers -v0x28a15a0_0 .net "out1", 0 0, L_0x2ce32c0; 1 drivers -v0x28a1050_0 .alias "outfinal", 0 0, v0x28ea2a0_0; -S_0x28ac990 .scope module, "mux1" "TwoInMux" 3 84, 3 8, S_0x28af0e0; - .timescale -9 -12; -L_0x2ce3630/d .functor NOT 1, L_0x2ce3b60, C4<0>, C4<0>, C4<0>; -L_0x2ce3630 .delay (10000,10000,10000) L_0x2ce3630/d; -L_0x2ce36f0/d .functor AND 1, L_0x2ce3410, L_0x2ce3630, C4<1>, C4<1>; -L_0x2ce36f0 .delay (20000,20000,20000) L_0x2ce36f0/d; -L_0x2ce3840/d .functor AND 1, L_0x2ce17a0, L_0x2ce3b60, C4<1>, C4<1>; -L_0x2ce3840 .delay (20000,20000,20000) L_0x2ce3840/d; -L_0x2ce3990/d .functor OR 1, L_0x2ce36f0, L_0x2ce3840, C4<0>, C4<0>; -L_0x2ce3990 .delay (20000,20000,20000) L_0x2ce3990/d; -v0x2898a90_0 .net "S", 0 0, L_0x2ce3b60; 1 drivers -v0x28ac480_0 .alias "in0", 0 0, v0x28ea2a0_0; -v0x28ac520_0 .alias "in1", 0 0, v0x28ecf40_0; -v0x28a9d00_0 .net "nS", 0 0, L_0x2ce3630; 1 drivers -v0x28a9d80_0 .net "out0", 0 0, L_0x2ce36f0; 1 drivers -v0x28a97b0_0 .net "out1", 0 0, L_0x2ce3840; 1 drivers -v0x28a6fe0_0 .alias "outfinal", 0 0, v0x28ea220_0; -S_0x2a12d50 .scope generate, "orbits[29]" "orbits[29]" 3 196, 3 196, S_0x29fb160; - .timescale -9 -12; -P_0x2a0bdb8 .param/l "i" 3 196, +C4<011101>; -S_0x2a12aa0 .scope module, "attempt" "OrNorXor" 3 198, 3 64, S_0x2a12d50; - .timescale -9 -12; -L_0x2ce2b40/d .functor NOR 1, L_0x2ce4fa0, L_0x2ce3ca0, C4<0>, C4<0>; -L_0x2ce2b40 .delay (10000,10000,10000) L_0x2ce2b40/d; -L_0x2ce2c30/d .functor NOT 1, L_0x2ce2b40, C4<0>, C4<0>, C4<0>; -L_0x2ce2c30 .delay (10000,10000,10000) L_0x2ce2c30/d; -L_0x2ce4020/d .functor NAND 1, L_0x2ce4fa0, L_0x2ce3ca0, C4<1>, C4<1>; -L_0x2ce4020 .delay (10000,10000,10000) L_0x2ce4020/d; -L_0x2ce4180/d .functor NAND 1, L_0x2ce4020, L_0x2ce2c30, C4<1>, C4<1>; -L_0x2ce4180 .delay (10000,10000,10000) L_0x2ce4180/d; -L_0x2ce4290/d .functor NOT 1, L_0x2ce4180, C4<0>, C4<0>, C4<0>; -L_0x2ce4290 .delay (10000,10000,10000) L_0x2ce4290/d; -v0x2b293c0_0 .net "A", 0 0, L_0x2ce4fa0; 1 drivers -v0x2672ab0_0 .net "AnandB", 0 0, L_0x2ce4020; 1 drivers -v0x2672b50_0 .net "AnorB", 0 0, L_0x2ce2b40; 1 drivers -v0x28b49a0_0 .net "AorB", 0 0, L_0x2ce2c30; 1 drivers -v0x28b4a20_0 .net "AxorB", 0 0, L_0x2ce4290; 1 drivers -v0x28b2250_0 .net "B", 0 0, L_0x2ce3ca0; 1 drivers -v0x28b22d0_0 .alias "Command", 2 0, v0x2bc67a0_0; -v0x28b1d40_0 .net "OrNorXorOut", 0 0, L_0x2ce4c90; 1 drivers -v0x28b1dc0_0 .net "XorNor", 0 0, L_0x2ce4710; 1 drivers -v0x2898a10_0 .net "nXor", 0 0, L_0x2ce4180; 1 drivers -L_0x2ce4890 .part v0x2bc78e0_0, 2, 1; -L_0x2ce4e60 .part v0x2bc78e0_0, 0, 1; -S_0x2a18b70 .scope module, "mux0" "TwoInMux" 3 83, 3 8, S_0x2a12aa0; - .timescale -9 -12; -L_0x2ce43f0/d .functor NOT 1, L_0x2ce4890, C4<0>, C4<0>, C4<0>; -L_0x2ce43f0 .delay (10000,10000,10000) L_0x2ce43f0/d; -L_0x2ce44b0/d .functor AND 1, L_0x2ce4290, L_0x2ce43f0, C4<1>, C4<1>; -L_0x2ce44b0 .delay (20000,20000,20000) L_0x2ce44b0/d; -L_0x2ce45c0/d .functor AND 1, L_0x2ce2b40, L_0x2ce4890, C4<1>, C4<1>; -L_0x2ce45c0 .delay (20000,20000,20000) L_0x2ce45c0/d; -L_0x2ce4710/d .functor OR 1, L_0x2ce44b0, L_0x2ce45c0, C4<0>, C4<0>; -L_0x2ce4710 .delay (20000,20000,20000) L_0x2ce4710/d; -v0x2a15630_0 .net "S", 0 0, L_0x2ce4890; 1 drivers -v0x2a188c0_0 .alias "in0", 0 0, v0x28b4a20_0; -v0x2a18940_0 .alias "in1", 0 0, v0x2672b50_0; -v0x2a17950_0 .net "nS", 0 0, L_0x2ce43f0; 1 drivers -v0x2a179d0_0 .net "out0", 0 0, L_0x2ce44b0; 1 drivers -v0x2a176a0_0 .net "out1", 0 0, L_0x2ce45c0; 1 drivers -v0x2b29340_0 .alias "outfinal", 0 0, v0x28b1dc0_0; -S_0x2a11b30 .scope module, "mux1" "TwoInMux" 3 84, 3 8, S_0x2a12aa0; - .timescale -9 -12; -L_0x2ce4930/d .functor NOT 1, L_0x2ce4e60, C4<0>, C4<0>, C4<0>; -L_0x2ce4930 .delay (10000,10000,10000) L_0x2ce4930/d; -L_0x2ce49f0/d .functor AND 1, L_0x2ce4710, L_0x2ce4930, C4<1>, C4<1>; -L_0x2ce49f0 .delay (20000,20000,20000) L_0x2ce49f0/d; -L_0x2ce4b40/d .functor AND 1, L_0x2ce2c30, L_0x2ce4e60, C4<1>, C4<1>; -L_0x2ce4b40 .delay (20000,20000,20000) L_0x2ce4b40/d; -L_0x2ce4c90/d .functor OR 1, L_0x2ce49f0, L_0x2ce4b40, C4<0>, C4<0>; -L_0x2ce4c90 .delay (20000,20000,20000) L_0x2ce4c90/d; -v0x2a0f2b0_0 .net "S", 0 0, L_0x2ce4e60; 1 drivers -v0x2a11880_0 .alias "in0", 0 0, v0x28b1dc0_0; -v0x2a11900_0 .alias "in1", 0 0, v0x28b49a0_0; -v0x2a0ef80_0 .net "nS", 0 0, L_0x2ce4930; 1 drivers -v0x2a0f000_0 .net "out0", 0 0, L_0x2ce49f0; 1 drivers -v0x2a15860_0 .net "out1", 0 0, L_0x2ce4b40; 1 drivers -v0x2a155b0_0 .alias "outfinal", 0 0, v0x28b1d40_0; -S_0x2a05bc0 .scope generate, "orbits[30]" "orbits[30]" 3 196, 3 196, S_0x29fb160; - .timescale -9 -12; -P_0x2a059d8 .param/l "i" 3 196, +C4<011110>; -S_0x2a032c0 .scope module, "attempt" "OrNorXor" 3 198, 3 64, S_0x2a05bc0; - .timescale -9 -12; -L_0x2ce3d40/d .functor NOR 1, L_0x2ce5040, L_0x2ce50e0, C4<0>, C4<0>; -L_0x2ce3d40 .delay (10000,10000,10000) L_0x2ce3d40/d; -L_0x2ce3e30/d .functor NOT 1, L_0x2ce3d40, C4<0>, C4<0>, C4<0>; -L_0x2ce3e30 .delay (10000,10000,10000) L_0x2ce3e30/d; -L_0x2ce3ef0/d .functor NAND 1, L_0x2ce5040, L_0x2ce50e0, C4<1>, C4<1>; -L_0x2ce3ef0 .delay (10000,10000,10000) L_0x2ce3ef0/d; -L_0x2ce5470/d .functor NAND 1, L_0x2ce3ef0, L_0x2ce3e30, C4<1>, C4<1>; -L_0x2ce5470 .delay (10000,10000,10000) L_0x2ce5470/d; -L_0x2ce5580/d .functor NOT 1, L_0x2ce5470, C4<0>, C4<0>, C4<0>; -L_0x2ce5580 .delay (10000,10000,10000) L_0x2ce5580/d; -v0x2a0baa0_0 .net "A", 0 0, L_0x2ce5040; 1 drivers -v0x2a09120_0 .net "AnandB", 0 0, L_0x2ce3ef0; 1 drivers -v0x2a091c0_0 .net "AnorB", 0 0, L_0x2ce3d40; 1 drivers -v0x2a0fa40_0 .net "AorB", 0 0, L_0x2ce3e30; 1 drivers -v0x2a0fac0_0 .net "AxorB", 0 0, L_0x2ce5580; 1 drivers -v0x2a0f790_0 .net "B", 0 0, L_0x2ce50e0; 1 drivers -v0x2a0f810_0 .alias "Command", 2 0, v0x2bc67a0_0; -v0x2a0f4e0_0 .net "OrNorXorOut", 0 0, L_0x2ce5f80; 1 drivers -v0x2a0f560_0 .net "XorNor", 0 0, L_0x2ce5a00; 1 drivers -v0x2a0f230_0 .net "nXor", 0 0, L_0x2ce5470; 1 drivers -L_0x2ce5b80 .part v0x2bc78e0_0, 2, 1; -L_0x2ce6150 .part v0x2bc78e0_0, 0, 1; -S_0x2a09680 .scope module, "mux0" "TwoInMux" 3 83, 3 8, S_0x2a032c0; - .timescale -9 -12; -L_0x2ce56e0/d .functor NOT 1, L_0x2ce5b80, C4<0>, C4<0>, C4<0>; -L_0x2ce56e0 .delay (10000,10000,10000) L_0x2ce56e0/d; -L_0x2ce57a0/d .functor AND 1, L_0x2ce5580, L_0x2ce56e0, C4<1>, C4<1>; -L_0x2ce57a0 .delay (20000,20000,20000) L_0x2ce57a0/d; -L_0x2ce58b0/d .functor AND 1, L_0x2ce3d40, L_0x2ce5b80, C4<1>, C4<1>; -L_0x2ce58b0 .delay (20000,20000,20000) L_0x2ce58b0/d; -L_0x2ce5a00/d .functor OR 1, L_0x2ce57a0, L_0x2ce58b0, C4<0>, C4<0>; -L_0x2ce5a00 .delay (20000,20000,20000) L_0x2ce5a00/d; -v0x2a093d0_0 .net "S", 0 0, L_0x2ce5b80; 1 drivers -v0x2a0cf10_0 .alias "in0", 0 0, v0x2a0fac0_0; -v0x2a0cfb0_0 .alias "in1", 0 0, v0x2a091c0_0; -v0x2a0cc60_0 .net "nS", 0 0, L_0x2ce56e0; 1 drivers -v0x2a0cce0_0 .net "out0", 0 0, L_0x2ce57a0; 1 drivers -v0x2a0bcd0_0 .net "out1", 0 0, L_0x2ce58b0; 1 drivers -v0x2a0ba20_0 .alias "outfinal", 0 0, v0x2a0f560_0; -S_0x2a0b770 .scope module, "mux1" "TwoInMux" 3 84, 3 8, S_0x2a032c0; - .timescale -9 -12; -L_0x2ce5c20/d .functor NOT 1, L_0x2ce6150, C4<0>, C4<0>, C4<0>; -L_0x2ce5c20 .delay (10000,10000,10000) L_0x2ce5c20/d; -L_0x2ce5ce0/d .functor AND 1, L_0x2ce5a00, L_0x2ce5c20, C4<1>, C4<1>; -L_0x2ce5ce0 .delay (20000,20000,20000) L_0x2ce5ce0/d; -L_0x2ce5e30/d .functor AND 1, L_0x2ce3e30, L_0x2ce6150, C4<1>, C4<1>; -L_0x2ce5e30 .delay (20000,20000,20000) L_0x2ce5e30/d; -L_0x2ce5f80/d .functor OR 1, L_0x2ce5ce0, L_0x2ce5e30, C4<0>, C4<0>; -L_0x2ce5f80 .delay (20000,20000,20000) L_0x2ce5f80/d; -v0x2a0b4c0_0 .net "S", 0 0, L_0x2ce6150; 1 drivers -v0x2a0b540_0 .alias "in0", 0 0, v0x2a0f560_0; -v0x2a0b210_0 .alias "in1", 0 0, v0x2a0fa40_0; -v0x2a0b290_0 .net "nS", 0 0, L_0x2ce5c20; 1 drivers -v0x2a09be0_0 .net "out0", 0 0, L_0x2ce5ce0; 1 drivers -v0x2a09c60_0 .net "out1", 0 0, L_0x2ce5e30; 1 drivers -v0x2a09970_0 .alias "outfinal", 0 0, v0x2a0f4e0_0; -S_0x29f9f40 .scope generate, "orbits[31]" "orbits[31]" 3 196, 3 196, S_0x29fb160; - .timescale -9 -12; -P_0x29fa238 .param/l "i" 3 196, +C4<011111>; -S_0x29ffab0 .scope module, "attempt" "OrNorXor" 3 198, 3 64, S_0x29f9f40; - .timescale -9 -12; -L_0x2ce5180/d .functor NOR 1, L_0x2ce75c0, L_0x2ce6290, C4<0>, C4<0>; -L_0x2ce5180 .delay (10000,10000,10000) L_0x2ce5180/d; -L_0x2ce5270/d .functor NOT 1, L_0x2ce5180, C4<0>, C4<0>, C4<0>; -L_0x2ce5270 .delay (10000,10000,10000) L_0x2ce5270/d; -L_0x2ce6620/d .functor NAND 1, L_0x2ce75c0, L_0x2ce6290, C4<1>, C4<1>; -L_0x2ce6620 .delay (10000,10000,10000) L_0x2ce6620/d; -L_0x2ce6780/d .functor NAND 1, L_0x2ce6620, L_0x2ce5270, C4<1>, C4<1>; -L_0x2ce6780 .delay (10000,10000,10000) L_0x2ce6780/d; -L_0x2ce6890/d .functor NOT 1, L_0x2ce6780, C4<0>, C4<0>, C4<0>; -L_0x2ce6890 .delay (10000,10000,10000) L_0x2ce6890/d; -v0x2a03ad0_0 .net "A", 0 0, L_0x2ce75c0; 1 drivers -v0x2a03820_0 .net "AnandB", 0 0, L_0x2ce6620; 1 drivers -v0x2a038c0_0 .net "AnorB", 0 0, L_0x2ce5180; 1 drivers -v0x2a03570_0 .net "AorB", 0 0, L_0x2ce5270; 1 drivers -v0x2a035f0_0 .net "AxorB", 0 0, L_0x2ce6890; 1 drivers -v0x2a070b0_0 .net "B", 0 0, L_0x2ce6290; 1 drivers -v0x2a06e00_0 .alias "Command", 2 0, v0x2bc67a0_0; -v0x2a06e80_0 .net "OrNorXorOut", 0 0, L_0x2ce72b0; 1 drivers -v0x2a05e70_0 .net "XorNor", 0 0, L_0x2ce6d10; 1 drivers -v0x2a05ef0_0 .net "nXor", 0 0, L_0x2ce6780; 1 drivers -L_0x2ce6e90 .part v0x2bc78e0_0, 2, 1; -L_0x2ce7480 .part v0x2bc78e0_0, 0, 1; -S_0x29ffd60 .scope module, "mux0" "TwoInMux" 3 83, 3 8, S_0x29ffab0; - .timescale -9 -12; -L_0x2ce69f0/d .functor NOT 1, L_0x2ce6e90, C4<0>, C4<0>, C4<0>; -L_0x2ce69f0 .delay (10000,10000,10000) L_0x2ce69f0/d; -L_0x2ce6ab0/d .functor AND 1, L_0x2ce6890, L_0x2ce69f0, C4<1>, C4<1>; -L_0x2ce6ab0 .delay (20000,20000,20000) L_0x2ce6ab0/d; -L_0x2ce6bc0/d .functor AND 1, L_0x2ce5180, L_0x2ce6e90, C4<1>, C4<1>; -L_0x2ce6bc0 .delay (20000,20000,20000) L_0x2ce6bc0/d; -L_0x2ce6d10/d .functor OR 1, L_0x2ce6ab0, L_0x2ce6bc0, C4<0>, C4<0>; -L_0x2ce6d10 .delay (20000,20000,20000) L_0x2ce6d10/d; -v0x2a05910_0 .net "S", 0 0, L_0x2ce6e90; 1 drivers -v0x2a05660_0 .alias "in0", 0 0, v0x2a035f0_0; -v0x2a05700_0 .alias "in1", 0 0, v0x2a038c0_0; -v0x2a053b0_0 .net "nS", 0 0, L_0x2ce69f0; 1 drivers -v0x2a05430_0 .net "out0", 0 0, L_0x2ce6ab0; 1 drivers -v0x2a03d80_0 .net "out1", 0 0, L_0x2ce6bc0; 1 drivers -v0x2a03e20_0 .alias "outfinal", 0 0, v0x2a05e70_0; -S_0x29fdf20 .scope module, "mux1" "TwoInMux" 3 84, 3 8, S_0x29ffab0; - .timescale -9 -12; -L_0x2ce6f30/d .functor NOT 1, L_0x2ce7480, C4<0>, C4<0>, C4<0>; -L_0x2ce6f30 .delay (10000,10000,10000) L_0x2ce6f30/d; -L_0x2ce7010/d .functor AND 1, L_0x2ce6d10, L_0x2ce6f30, C4<1>, C4<1>; -L_0x2ce7010 .delay (20000,20000,20000) L_0x2ce7010/d; -L_0x2ce7160/d .functor AND 1, L_0x2ce5270, L_0x2ce7480, C4<1>, C4<1>; -L_0x2ce7160 .delay (20000,20000,20000) L_0x2ce7160/d; -L_0x2ce72b0/d .functor OR 1, L_0x2ce7010, L_0x2ce7160, C4<0>, C4<0>; -L_0x2ce72b0 .delay (20000,20000,20000) L_0x2ce72b0/d; -v0x29fdc70_0 .net "S", 0 0, L_0x2ce7480; 1 drivers -v0x29fdd10_0 .alias "in0", 0 0, v0x2a05e70_0; -v0x2a01250_0 .alias "in1", 0 0, v0x2a03570_0; -v0x2a012f0_0 .net "nS", 0 0, L_0x2ce6f30; 1 drivers -v0x2a00fa0_0 .net "out0", 0 0, L_0x2ce7010; 1 drivers -v0x2a01040_0 .net "out1", 0 0, L_0x2ce7160; 1 drivers -v0x2a00070_0 .alias "outfinal", 0 0, v0x2a06e80_0; -S_0x29f2030 .scope module, "ZeroMux0case" "FourInMux" 3 283, 3 24, S_0x29738d0; - .timescale -9 -12; -L_0x2ce77a0/d .functor NOT 1, L_0x2c82790, C4<0>, C4<0>, C4<0>; -L_0x2ce77a0 .delay (10000,10000,10000) L_0x2ce77a0/d; -L_0x2ce7840/d .functor NOT 1, L_0x2c828c0, C4<0>, C4<0>, C4<0>; -L_0x2ce7840 .delay (10000,10000,10000) L_0x2ce7840/d; -L_0x2ce8bc0/d .functor NAND 1, L_0x2ce77a0, L_0x2ce7840, L_0x2c829f0, C4<1>; -L_0x2ce8bc0 .delay (10000,10000,10000) L_0x2ce8bc0/d; -L_0x2ce8cb0/d .functor NAND 1, L_0x2c82790, L_0x2ce7840, L_0x2c82a90, C4<1>; -L_0x2ce8cb0 .delay (10000,10000,10000) L_0x2ce8cb0/d; -L_0x2ce8da0/d .functor NAND 1, L_0x2ce77a0, L_0x2c828c0, L_0x2c82b30, C4<1>; -L_0x2ce8da0 .delay (10000,10000,10000) L_0x2ce8da0/d; -L_0x2ce8e90/d .functor NAND 1, L_0x2c82790, L_0x2c828c0, L_0x2c82c20, C4<1>; -L_0x2ce8e90 .delay (10000,10000,10000) L_0x2ce8e90/d; -L_0x2ce8f70/d .functor NAND 1, L_0x2ce8bc0, L_0x2ce8cb0, L_0x2ce8da0, L_0x2ce8e90; -L_0x2ce8f70 .delay (10000,10000,10000) L_0x2ce8f70/d; -v0x29f2380_0 .net "S0", 0 0, L_0x2c82790; 1 drivers -v0x29f55f0_0 .net "S1", 0 0, L_0x2c828c0; 1 drivers -v0x29f5690_0 .net "in0", 0 0, L_0x2c829f0; 1 drivers -v0x29f5340_0 .net "in1", 0 0, L_0x2c82a90; 1 drivers -v0x29f53c0_0 .net "in2", 0 0, L_0x2c82b30; 1 drivers -v0x29f43d0_0 .net "in3", 0 0, L_0x2c82c20; 1 drivers -v0x29f4470_0 .net "nS0", 0 0, L_0x2ce77a0; 1 drivers -v0x29f4140_0 .net "nS1", 0 0, L_0x2ce7840; 1 drivers -v0x29f8100_0 .net "out", 0 0, L_0x2ce8f70; 1 drivers -v0x29f81a0_0 .net "out0", 0 0, L_0x2ce8bc0; 1 drivers -v0x29f7e50_0 .net "out1", 0 0, L_0x2ce8cb0; 1 drivers -v0x29f7ef0_0 .net "out2", 0 0, L_0x2ce8da0; 1 drivers -v0x29fb4a0_0 .net "out3", 0 0, L_0x2ce8e90; 1 drivers -S_0x29ec1d0 .scope module, "OneMux0case" "FourInMux" 3 284, 3 24, S_0x29738d0; - .timescale -9 -12; -L_0x29f41c0/d .functor NOT 1, L_0x2c834c0, C4<0>, C4<0>, C4<0>; -L_0x29f41c0 .delay (10000,10000,10000) L_0x29f41c0/d; -L_0x2c82da0/d .functor NOT 1, L_0x2c835f0, C4<0>, C4<0>, C4<0>; -L_0x2c82da0 .delay (10000,10000,10000) L_0x2c82da0/d; -L_0x2c82e40/d .functor NAND 1, L_0x29f41c0, L_0x2c82da0, L_0x2c83720, C4<1>; -L_0x2c82e40 .delay (10000,10000,10000) L_0x2c82e40/d; -L_0x2c82f80/d .functor NAND 1, L_0x2c834c0, L_0x2c82da0, L_0x2c837c0, C4<1>; -L_0x2c82f80 .delay (10000,10000,10000) L_0x2c82f80/d; -L_0x2c83070/d .functor NAND 1, L_0x29f41c0, L_0x2c835f0, L_0x2c83860, C4<1>; -L_0x2c83070 .delay (10000,10000,10000) L_0x2c83070/d; -L_0x2c83160/d .functor NAND 1, L_0x2c834c0, L_0x2c835f0, L_0x2c83950, C4<1>; -L_0x2c83160 .delay (10000,10000,10000) L_0x2c83160/d; -L_0x2c83240/d .functor NAND 1, L_0x2c82e40, L_0x2c82f80, L_0x2c83070, L_0x2c83160; -L_0x2c83240 .delay (10000,10000,10000) L_0x2c83240/d; -v0x29ebf20_0 .net "S0", 0 0, L_0x2c834c0; 1 drivers -v0x29ebc70_0 .net "S1", 0 0, L_0x2c835f0; 1 drivers -v0x29ebd10_0 .net "in0", 0 0, L_0x2c83720; 1 drivers -v0x29ef7b0_0 .net "in1", 0 0, L_0x2c837c0; 1 drivers -v0x29ef830_0 .net "in2", 0 0, L_0x2c83860; 1 drivers -v0x29ef500_0 .net "in3", 0 0, L_0x2c83950; 1 drivers -v0x29ef5a0_0 .net "nS0", 0 0, L_0x29f41c0; 1 drivers -v0x29ee570_0 .net "nS1", 0 0, L_0x2c82da0; 1 drivers -v0x29ee610_0 .net "out", 0 0, L_0x2c83240; 1 drivers -v0x29ee2c0_0 .net "out0", 0 0, L_0x2c82e40; 1 drivers -v0x29ee340_0 .net "out1", 0 0, L_0x2c82f80; 1 drivers -v0x29eb9c0_0 .net "out2", 0 0, L_0x2c83070; 1 drivers -v0x29f22e0_0 .net "out3", 0 0, L_0x2c83160; 1 drivers -S_0x29e5b60 .scope module, "TwoMux0case" "TwoInMux" 3 285, 3 8, S_0x29738d0; - .timescale -9 -12; -L_0x2c83a40/d .functor NOT 1, L_0x2c58bd0, C4<0>, C4<0>, C4<0>; -L_0x2c83a40 .delay (10000,10000,10000) L_0x2c83a40/d; -L_0x2c83b30/d .functor AND 1, L_0x2c58c70, L_0x2c83a40, C4<1>, C4<1>; -L_0x2c83b30 .delay (20000,20000,20000) L_0x2c83b30/d; -L_0x2cea710/d .functor AND 1, L_0x2c58d60, L_0x2c58bd0, C4<1>, C4<1>; -L_0x2cea710 .delay (20000,20000,20000) L_0x2cea710/d; -L_0x2cea800/d .functor OR 1, L_0x2c83b30, L_0x2cea710, C4<0>, C4<0>; -L_0x2cea800 .delay (20000,20000,20000) L_0x2cea800/d; -v0x29ee010_0 .net "S", 0 0, L_0x2c58bd0; 1 drivers -v0x29edd60_0 .net "in0", 0 0, L_0x2c58c70; 1 drivers -v0x29ede00_0 .net "in1", 0 0, L_0x2c58d60; 1 drivers -v0x29edab0_0 .net "nS", 0 0, L_0x2c83a40; 1 drivers -v0x29edb30_0 .net "out0", 0 0, L_0x2c83b30; 1 drivers -v0x29ec480_0 .net "out1", 0 0, L_0x2cea710; 1 drivers -v0x29ec520_0 .net "outfinal", 0 0, L_0x2cea800; 1 drivers -S_0x29dc7e0 .scope generate, "muxbits[1]" "muxbits[1]" 3 290, 3 290, S_0x29738d0; - .timescale -9 -12; -P_0x29d1dc8 .param/l "i" 3 290, +C4<01>; -L_0x2c32930/d .functor OR 1, L_0x2c32a30, L_0x2c327f0, C4<0>, C4<0>; -L_0x2c32930 .delay (20000,20000,20000) L_0x2c32930/d; -v0x29e87b0_0 .net *"_s15", 0 0, L_0x2c32a30; 1 drivers -v0x29e8480_0 .net *"_s16", 0 0, L_0x2c327f0; 1 drivers -S_0x29e7f00 .scope module, "ZeroMux" "FourInMux" 3 292, 3 24, S_0x29dc7e0; - .timescale -9 -12; -L_0x2c2ee70/d .functor NOT 1, L_0x2c30a30, C4<0>, C4<0>, C4<0>; -L_0x2c2ee70 .delay (10000,10000,10000) L_0x2c2ee70/d; -L_0x2c2ef10/d .functor NOT 1, L_0x2c30b60, C4<0>, C4<0>, C4<0>; -L_0x2c2ef10 .delay (10000,10000,10000) L_0x2c2ef10/d; -L_0x2c30230/d .functor NAND 1, L_0x2c2ee70, L_0x2c2ef10, L_0x2c30c90, C4<1>; -L_0x2c30230 .delay (10000,10000,10000) L_0x2c30230/d; -L_0x2c30370/d .functor NAND 1, L_0x2c30a30, L_0x2c2ef10, L_0x2c30d30, C4<1>; -L_0x2c30370 .delay (10000,10000,10000) L_0x2c30370/d; -L_0x2c304c0/d .functor NAND 1, L_0x2c2ee70, L_0x2c30b60, L_0x2c30dd0, C4<1>; -L_0x2c304c0 .delay (10000,10000,10000) L_0x2c304c0/d; -L_0x2c30610/d .functor NAND 1, L_0x2c30a30, L_0x2c30b60, L_0x2c30f00, C4<1>; -L_0x2c30610 .delay (10000,10000,10000) L_0x2c30610/d; -L_0x2c30780/d .functor NAND 1, L_0x2c30230, L_0x2c30370, L_0x2c304c0, L_0x2c30610; -L_0x2c30780 .delay (10000,10000,10000) L_0x2c30780/d; -v0x29e7c50_0 .net "S0", 0 0, L_0x2c30a30; 1 drivers -v0x29e7cf0_0 .net "S1", 0 0, L_0x2c30b60; 1 drivers -v0x29e6620_0 .net "in0", 0 0, L_0x2c30c90; 1 drivers -v0x29e66c0_0 .net "in1", 0 0, L_0x2c30d30; 1 drivers -v0x29e6370_0 .net "in2", 0 0, L_0x2c30dd0; 1 drivers -v0x29e6410_0 .net "in3", 0 0, L_0x2c30f00; 1 drivers -v0x29e60e0_0 .net "nS0", 0 0, L_0x2c2ee70; 1 drivers -v0x29e5e10_0 .net "nS1", 0 0, L_0x2c2ef10; 1 drivers -v0x29e5eb0_0 .net "out", 0 0, L_0x2c30780; 1 drivers -v0x29e9950_0 .net "out0", 0 0, L_0x2c30230; 1 drivers -v0x29e99f0_0 .net "out1", 0 0, L_0x2c30370; 1 drivers -v0x29e96a0_0 .net "out2", 0 0, L_0x2c304c0; 1 drivers -v0x29e8710_0 .net "out3", 0 0, L_0x2c30610; 1 drivers -S_0x29dffb0 .scope module, "OneMux" "FourInMux" 3 293, 3 24, S_0x29dc7e0; - .timescale -9 -12; -L_0x2c30ff0/d .functor NOT 1, L_0x2c31960, C4<0>, C4<0>, C4<0>; -L_0x2c30ff0 .delay (10000,10000,10000) L_0x2c30ff0/d; -L_0x2c310e0/d .functor NOT 1, L_0x2c31a90, C4<0>, C4<0>, C4<0>; -L_0x2c310e0 .delay (10000,10000,10000) L_0x2c310e0/d; -L_0x2c31180/d .functor NAND 1, L_0x2c30ff0, L_0x2c310e0, L_0x2c31c20, C4<1>; -L_0x2c31180 .delay (10000,10000,10000) L_0x2c31180/d; -L_0x2c312c0/d .functor NAND 1, L_0x2c31960, L_0x2c310e0, L_0x2c31cc0, C4<1>; -L_0x2c312c0 .delay (10000,10000,10000) L_0x2c312c0/d; -L_0x2c313b0/d .functor NAND 1, L_0x2c30ff0, L_0x2c31a90, L_0x2c31dd0, C4<1>; -L_0x2c313b0 .delay (10000,10000,10000) L_0x2c313b0/d; -L_0x2c31500/d .functor NAND 1, L_0x2c31960, L_0x2c31a90, L_0x2c31e70, C4<1>; -L_0x2c31500 .delay (10000,10000,10000) L_0x2c31500/d; -L_0x2c31630/d .functor NAND 1, L_0x2c31180, L_0x2c312c0, L_0x2c313b0, L_0x2c31500; -L_0x2c31630 .delay (10000,10000,10000) L_0x2c31630/d; -v0x29e0300_0 .net "S0", 0 0, L_0x2c31960; 1 drivers -v0x29e3af0_0 .net "S1", 0 0, L_0x2c31a90; 1 drivers -v0x29e3b70_0 .net "in0", 0 0, L_0x2c31c20; 1 drivers -v0x29e3840_0 .net "in1", 0 0, L_0x2c31cc0; 1 drivers -v0x29e38e0_0 .net "in2", 0 0, L_0x2c31dd0; 1 drivers -v0x29e28b0_0 .net "in3", 0 0, L_0x2c31e70; 1 drivers -v0x29e2950_0 .net "nS0", 0 0, L_0x2c30ff0; 1 drivers -v0x29e2620_0 .net "nS1", 0 0, L_0x2c310e0; 1 drivers -v0x29dfd00_0 .net "out", 0 0, L_0x2c31630; 1 drivers -v0x29dfda0_0 .net "out0", 0 0, L_0x2c31180; 1 drivers -v0x29dfa60_0 .net "out1", 0 0, L_0x2c312c0; 1 drivers -v0x29dfb00_0 .net "out2", 0 0, L_0x2c313b0; 1 drivers -v0x29e8240_0 .net "out3", 0 0, L_0x2c31500; 1 drivers -S_0x29e2350 .scope module, "TwoMux" "TwoInMux" 3 294, 3 8, S_0x29dc7e0; - .timescale -9 -12; -L_0x2c31bc0/d .functor NOT 1, L_0x2c32440, C4<0>, C4<0>, C4<0>; -L_0x2c31bc0 .delay (10000,10000,10000) L_0x2c31bc0/d; -L_0x2c32030/d .functor AND 1, L_0x2c32570, L_0x2c31bc0, C4<1>, C4<1>; -L_0x2c32030 .delay (20000,20000,20000) L_0x2c32030/d; -L_0x2c32120/d .functor AND 1, L_0x2c326b0, L_0x2c32440, C4<1>, C4<1>; -L_0x2c32120 .delay (20000,20000,20000) L_0x2c32120/d; -L_0x2c32210/d .functor OR 1, L_0x2c32030, L_0x2c32120, C4<0>, C4<0>; -L_0x2c32210 .delay (20000,20000,20000) L_0x2c32210/d; -v0x29e20a0_0 .net "S", 0 0, L_0x2c32440; 1 drivers -v0x29e2140_0 .net "in0", 0 0, L_0x2c32570; 1 drivers -v0x29e1df0_0 .net "in1", 0 0, L_0x2c326b0; 1 drivers -v0x29e1e90_0 .net "nS", 0 0, L_0x2c31bc0; 1 drivers -v0x29e07e0_0 .net "out0", 0 0, L_0x2c32030; 1 drivers -v0x29e0510_0 .net "out1", 0 0, L_0x2c32120; 1 drivers -v0x29e0260_0 .net "outfinal", 0 0, L_0x2c32210; 1 drivers -S_0x29cc240 .scope generate, "muxbits[2]" "muxbits[2]" 3 290, 3 290, S_0x29738d0; - .timescale -9 -12; -P_0x29bf438 .param/l "i" 3 290, +C4<010>; -L_0x2c34850/d .functor OR 1, L_0x2c35050, L_0x2c353d0, C4<0>, C4<0>; -L_0x2c34850 .delay (20000,20000,20000) L_0x2c34850/d; -v0x29ddaa0_0 .net *"_s15", 0 0, L_0x2c35050; 1 drivers -v0x29dca90_0 .net *"_s16", 0 0, L_0x2c353d0; 1 drivers -S_0x29d48d0 .scope module, "ZeroMux" "FourInMux" 3 292, 3 24, S_0x29cc240; - .timescale -9 -12; -L_0x2c32bd0/d .functor NOT 1, L_0x2c32ad0, C4<0>, C4<0>, C4<0>; -L_0x2c32bd0 .delay (10000,10000,10000) L_0x2c32bd0/d; -L_0x2c32cc0/d .functor NOT 1, L_0x2c33530, C4<0>, C4<0>, C4<0>; -L_0x2c32cc0 .delay (10000,10000,10000) L_0x2c32cc0/d; -L_0x2c32d60/d .functor NAND 1, L_0x2c32bd0, L_0x2c32cc0, L_0x2c333e0, C4<1>; -L_0x2c32d60 .delay (10000,10000,10000) L_0x2c32d60/d; -L_0x2c32ea0/d .functor NAND 1, L_0x2c32ad0, L_0x2c32cc0, L_0x2c33730, C4<1>; -L_0x2c32ea0 .delay (10000,10000,10000) L_0x2c32ea0/d; -L_0x2c32f90/d .functor NAND 1, L_0x2c32bd0, L_0x2c33530, L_0x2c33660, C4<1>; -L_0x2c32f90 .delay (10000,10000,10000) L_0x2c32f90/d; -L_0x2c33080/d .functor NAND 1, L_0x2c32ad0, L_0x2c33530, L_0x2c33900, C4<1>; -L_0x2c33080 .delay (10000,10000,10000) L_0x2c33080/d; -L_0x2c33160/d .functor NAND 1, L_0x2c32d60, L_0x2c32ea0, L_0x2c32f90, L_0x2c33080; -L_0x2c33160 .delay (10000,10000,10000) L_0x2c33160/d; -v0x29d7e90_0 .net "S0", 0 0, L_0x2c32ad0; 1 drivers -v0x29d7be0_0 .net "S1", 0 0, L_0x2c33530; 1 drivers -v0x29d7c80_0 .net "in0", 0 0, L_0x2c333e0; 1 drivers -v0x29d6c70_0 .net "in1", 0 0, L_0x2c33730; 1 drivers -v0x29d6cf0_0 .net "in2", 0 0, L_0x2c33660; 1 drivers -v0x29d69c0_0 .net "in3", 0 0, L_0x2c33900; 1 drivers -v0x29d6a60_0 .net "nS0", 0 0, L_0x2c32bd0; 1 drivers -v0x29da9a0_0 .net "nS1", 0 0, L_0x2c32cc0; 1 drivers -v0x29daa40_0 .net "out", 0 0, L_0x2c33160; 1 drivers -v0x29da6f0_0 .net "out0", 0 0, L_0x2c32d60; 1 drivers -v0x29da770_0 .net "out1", 0 0, L_0x2c32ea0; 1 drivers -v0x29ddcb0_0 .net "out2", 0 0, L_0x2c32f90; 1 drivers -v0x29dda00_0 .net "out3", 0 0, L_0x2c33080; 1 drivers -S_0x29ceac0 .scope module, "OneMux" "FourInMux" 3 293, 3 24, S_0x29cc240; - .timescale -9 -12; -L_0x2c337d0/d .functor NOT 1, L_0x2c342a0, C4<0>, C4<0>, C4<0>; -L_0x2c337d0 .delay (10000,10000,10000) L_0x2c337d0/d; -L_0x2c33b30/d .functor NOT 1, L_0x2c339f0, C4<0>, C4<0>, C4<0>; -L_0x2c33b30 .delay (10000,10000,10000) L_0x2c33b30/d; -L_0x2c33b90/d .functor NAND 1, L_0x2c337d0, L_0x2c33b30, L_0x2c34560, C4<1>; -L_0x2c33b90 .delay (10000,10000,10000) L_0x2c33b90/d; -L_0x2c33cd0/d .functor NAND 1, L_0x2c342a0, L_0x2c33b30, L_0x2c343d0, C4<1>; -L_0x2c33cd0 .delay (10000,10000,10000) L_0x2c33cd0/d; -L_0x2c33dc0/d .functor NAND 1, L_0x2c337d0, L_0x2c339f0, L_0x2c34710, C4<1>; -L_0x2c33dc0 .delay (10000,10000,10000) L_0x2c33dc0/d; -L_0x2c33eb0/d .functor NAND 1, L_0x2c342a0, L_0x2c339f0, L_0x2c34600, C4<1>; -L_0x2c33eb0 .delay (10000,10000,10000) L_0x2c33eb0/d; -L_0x2c33ff0/d .functor NAND 1, L_0x2c33b90, L_0x2c33cd0, L_0x2c33dc0, L_0x2c33eb0; -L_0x2c33ff0 .delay (10000,10000,10000) L_0x2c33ff0/d; -v0x29ce810_0 .net "S0", 0 0, L_0x2c342a0; 1 drivers -v0x29ce8b0_0 .net "S1", 0 0, L_0x2c339f0; 1 drivers -v0x29ce560_0 .net "in0", 0 0, L_0x2c34560; 1 drivers -v0x29ce600_0 .net "in1", 0 0, L_0x2c343d0; 1 drivers -v0x29d2070_0 .net "in2", 0 0, L_0x2c34710; 1 drivers -v0x29d2110_0 .net "in3", 0 0, L_0x2c34600; 1 drivers -v0x29d1e20_0 .net "nS0", 0 0, L_0x2c337d0; 1 drivers -v0x29d0e50_0 .net "nS1", 0 0, L_0x2c33b30; 1 drivers -v0x29d0ed0_0 .net "out", 0 0, L_0x2c33ff0; 1 drivers -v0x29d0ba0_0 .net "out0", 0 0, L_0x2c33b90; 1 drivers -v0x29d0c40_0 .net "out1", 0 0, L_0x2c33cd0; 1 drivers -v0x29ce2d0_0 .net "out2", 0 0, L_0x2c33dc0; 1 drivers -v0x29d4ba0_0 .net "out3", 0 0, L_0x2c33eb0; 1 drivers -S_0x29cbf90 .scope module, "TwoMux" "TwoInMux" 3 294, 3 8, S_0x29cc240; - .timescale -9 -12; -L_0x2c346a0/d .functor NOT 1, L_0x2c347b0, C4<0>, C4<0>, C4<0>; -L_0x2c346a0 .delay (10000,10000,10000) L_0x2c346a0/d; -L_0x2c34960/d .functor AND 1, L_0x2c34ee0, L_0x2c346a0, C4<1>, C4<1>; -L_0x2c34960 .delay (20000,20000,20000) L_0x2c34960/d; -L_0x2c34a50/d .functor AND 1, L_0x2c34db0, L_0x2c347b0, C4<1>, C4<1>; -L_0x2c34a50 .delay (20000,20000,20000) L_0x2c34a50/d; -L_0x2c34b40/d .functor OR 1, L_0x2c34960, L_0x2c34a50, C4<0>, C4<0>; -L_0x2c34b40 .delay (20000,20000,20000) L_0x2c34b40/d; -v0x29cb000_0 .net "S", 0 0, L_0x2c347b0; 1 drivers -v0x29cb0a0_0 .net "in0", 0 0, L_0x2c34ee0; 1 drivers -v0x29cad50_0 .net "in1", 0 0, L_0x2c34db0; 1 drivers -v0x29cadf0_0 .net "nS", 0 0, L_0x2c346a0; 1 drivers -v0x29c8450_0 .net "out0", 0 0, L_0x2c34960; 1 drivers -v0x29c84f0_0 .net "out1", 0 0, L_0x2c34a50; 1 drivers -v0x29cedd0_0 .net "outfinal", 0 0, L_0x2c34b40; 1 drivers -S_0x29bcfb0 .scope generate, "muxbits[3]" "muxbits[3]" 3 290, 3 290, S_0x29738d0; - .timescale -9 -12; -P_0x29ad608 .param/l "i" 3 290, +C4<011>; -L_0x2c37800/d .functor OR 1, L_0x2c37b80, L_0x2c37990, C4<0>, C4<0>; -L_0x2c37800 .delay (20000,20000,20000) L_0x2c37800/d; -v0x29c8a50_0 .net *"_s15", 0 0, L_0x2c37b80; 1 drivers -v0x29c8720_0 .net *"_s16", 0 0, L_0x2c37990; 1 drivers -S_0x29c51a0 .scope module, "ZeroMux" "FourInMux" 3 292, 3 24, S_0x29bcfb0; - .timescale -9 -12; -L_0x2c35280/d .functor NOT 1, L_0x2c35d50, C4<0>, C4<0>, C4<0>; -L_0x2c35280 .delay (10000,10000,10000) L_0x2c35280/d; -L_0x2c35370/d .functor NOT 1, L_0x2c35470, C4<0>, C4<0>, C4<0>; -L_0x2c35370 .delay (10000,10000,10000) L_0x2c35370/d; -L_0x2c35610/d .functor NAND 1, L_0x2c35280, L_0x2c35370, L_0x2c35ff0, C4<1>; -L_0x2c35610 .delay (10000,10000,10000) L_0x2c35610/d; -L_0x2c35750/d .functor NAND 1, L_0x2c35d50, L_0x2c35370, L_0x2c35e80, C4<1>; -L_0x2c35750 .delay (10000,10000,10000) L_0x2c35750/d; -L_0x2c35840/d .functor NAND 1, L_0x2c35280, L_0x2c35470, L_0x2c35f20, C4<1>; -L_0x2c35840 .delay (10000,10000,10000) L_0x2c35840/d; -L_0x2c35930/d .functor NAND 1, L_0x2c35d50, L_0x2c35470, L_0x2c36090, C4<1>; -L_0x2c35930 .delay (10000,10000,10000) L_0x2c35930/d; -L_0x2c35aa0/d .functor NAND 1, L_0x2c35610, L_0x2c35750, L_0x2c35840, L_0x2c35930; -L_0x2c35aa0 .delay (10000,10000,10000) L_0x2c35aa0/d; -v0x29c4ef0_0 .net "S0", 0 0, L_0x2c35d50; 1 drivers -v0x29c4f90_0 .net "S1", 0 0, L_0x2c35470; 1 drivers -v0x29c25f0_0 .net "in0", 0 0, L_0x2c35ff0; 1 drivers -v0x29c2690_0 .net "in1", 0 0, L_0x2c35e80; 1 drivers -v0x29caaa0_0 .net "in2", 0 0, L_0x2c35f20; 1 drivers -v0x29cab40_0 .net "in3", 0 0, L_0x2c36090; 1 drivers -v0x29ca810_0 .net "nS0", 0 0, L_0x2c35280; 1 drivers -v0x29ca540_0 .net "nS1", 0 0, L_0x2c35370; 1 drivers -v0x29ca5e0_0 .net "out", 0 0, L_0x2c35aa0; 1 drivers -v0x29c8f10_0 .net "out0", 0 0, L_0x2c35610; 1 drivers -v0x29c8fb0_0 .net "out1", 0 0, L_0x2c35750; 1 drivers -v0x29c8c60_0 .net "out2", 0 0, L_0x2c35840; 1 drivers -v0x29c89b0_0 .net "out3", 0 0, L_0x2c35930; 1 drivers -S_0x29c4990 .scope module, "OneMux" "FourInMux" 3 293, 3 24, S_0x29bcfb0; - .timescale -9 -12; -L_0x2c36180/d .functor NOT 1, L_0x2c36260, C4<0>, C4<0>, C4<0>; -L_0x2c36180 .delay (10000,10000,10000) L_0x2c36180/d; -L_0x2c36480/d .functor NOT 1, L_0x2c36da0, C4<0>, C4<0>, C4<0>; -L_0x2c36480 .delay (10000,10000,10000) L_0x2c36480/d; -L_0x2c36520/d .functor NAND 1, L_0x2c36180, L_0x2c36480, L_0x2c36c00, C4<1>; -L_0x2c36520 .delay (10000,10000,10000) L_0x2c36520/d; -L_0x2c36660/d .functor NAND 1, L_0x2c36260, L_0x2c36480, L_0x2c36ca0, C4<1>; -L_0x2c36660 .delay (10000,10000,10000) L_0x2c36660/d; -L_0x2c36750/d .functor NAND 1, L_0x2c36180, L_0x2c36da0, L_0x2c37090, C4<1>; -L_0x2c36750 .delay (10000,10000,10000) L_0x2c36750/d; -L_0x2c36840/d .functor NAND 1, L_0x2c36260, L_0x2c36da0, L_0x2c37130, C4<1>; -L_0x2c36840 .delay (10000,10000,10000) L_0x2c36840/d; -L_0x2c36950/d .functor NAND 1, L_0x2c36520, L_0x2c36660, L_0x2c36750, L_0x2c36840; -L_0x2c36950 .delay (10000,10000,10000) L_0x2c36950/d; -v0x29c4ce0_0 .net "S0", 0 0, L_0x2c36260; 1 drivers -v0x29c46e0_0 .net "S1", 0 0, L_0x2c36da0; 1 drivers -v0x29c4760_0 .net "in0", 0 0, L_0x2c36c00; 1 drivers -v0x29c30b0_0 .net "in1", 0 0, L_0x2c36ca0; 1 drivers -v0x29c3150_0 .net "in2", 0 0, L_0x2c37090; 1 drivers -v0x29c2e00_0 .net "in3", 0 0, L_0x2c37130; 1 drivers -v0x29c2ea0_0 .net "nS0", 0 0, L_0x2c36180; 1 drivers -v0x29c2b70_0 .net "nS1", 0 0, L_0x2c36480; 1 drivers -v0x29c28a0_0 .net "out", 0 0, L_0x2c36950; 1 drivers -v0x29c2940_0 .net "out0", 0 0, L_0x2c36520; 1 drivers -v0x29c63e0_0 .net "out1", 0 0, L_0x2c36660; 1 drivers -v0x29c6480_0 .net "out2", 0 0, L_0x2c36750; 1 drivers -v0x29c61c0_0 .net "out3", 0 0, L_0x2c36840; 1 drivers -S_0x29c0570 .scope module, "TwoMux" "TwoInMux" 3 294, 3 8, S_0x29bcfb0; - .timescale -9 -12; -L_0x2c36ed0/d .functor NOT 1, L_0x2c376c0, C4<0>, C4<0>, C4<0>; -L_0x2c36ed0 .delay (10000,10000,10000) L_0x2c36ed0/d; -L_0x2c36fc0/d .functor AND 1, L_0x2c371d0, L_0x2c36ed0, C4<1>, C4<1>; -L_0x2c36fc0 .delay (20000,20000,20000) L_0x2c36fc0/d; -L_0x2c373f0/d .functor AND 1, L_0x2c372c0, L_0x2c376c0, C4<1>, C4<1>; -L_0x2c373f0 .delay (20000,20000,20000) L_0x2c373f0/d; -L_0x2c374e0/d .functor OR 1, L_0x2c36fc0, L_0x2c373f0, C4<0>, C4<0>; -L_0x2c374e0 .delay (20000,20000,20000) L_0x2c374e0/d; -v0x29c02c0_0 .net "S", 0 0, L_0x2c376c0; 1 drivers -v0x29c0360_0 .net "in0", 0 0, L_0x2c371d0; 1 drivers -v0x29c0010_0 .net "in1", 0 0, L_0x2c372c0; 1 drivers -v0x29c00b0_0 .net "nS", 0 0, L_0x2c36ed0; 1 drivers -v0x29bf370_0 .net "out0", 0 0, L_0x2c36fc0; 1 drivers -v0x29bf0a0_0 .net "out1", 0 0, L_0x2c373f0; 1 drivers -v0x29c4c40_0 .net "outfinal", 0 0, L_0x2c374e0; 1 drivers -S_0x29ad350 .scope generate, "muxbits[4]" "muxbits[4]" 3 290, 3 290, S_0x29738d0; - .timescale -9 -12; -P_0x299f938 .param/l "i" 3 290, +C4<0100>; -L_0x2c34f80/d .functor OR 1, L_0x2c3a150, L_0x2c3a330, C4<0>, C4<0>; -L_0x2c34f80 .delay (20000,20000,20000) L_0x2c34f80/d; -v0x29b9320_0 .net *"_s15", 0 0, L_0x2c3a150; 1 drivers -v0x29bd260_0 .net *"_s16", 0 0, L_0x2c3a330; 1 drivers -S_0x29b4680 .scope module, "ZeroMux" "FourInMux" 3 292, 3 24, S_0x29ad350; - .timescale -9 -12; -L_0x2c37a80/d .functor NOT 1, L_0x2c37c20, C4<0>, C4<0>, C4<0>; -L_0x2c37a80 .delay (10000,10000,10000) L_0x2c37a80/d; -L_0x2c37e20/d .functor NOT 1, L_0x2c37d50, C4<0>, C4<0>, C4<0>; -L_0x2c37e20 .delay (10000,10000,10000) L_0x2c37e20/d; -L_0x2c37e80/d .functor NAND 1, L_0x2c37a80, L_0x2c37e20, L_0x2c38560, C4<1>; -L_0x2c37e80 .delay (10000,10000,10000) L_0x2c37e80/d; -L_0x2c37fc0/d .functor NAND 1, L_0x2c37c20, L_0x2c37e20, L_0x2c38600, C4<1>; -L_0x2c37fc0 .delay (10000,10000,10000) L_0x2c37fc0/d; -L_0x2c380b0/d .functor NAND 1, L_0x2c37a80, L_0x2c37d50, L_0x2c386a0, C4<1>; -L_0x2c380b0 .delay (10000,10000,10000) L_0x2c380b0/d; -L_0x2c381a0/d .functor NAND 1, L_0x2c37c20, L_0x2c37d50, L_0x2c38a80, C4<1>; -L_0x2c381a0 .delay (10000,10000,10000) L_0x2c381a0/d; -L_0x2c382b0/d .functor NAND 1, L_0x2c37e80, L_0x2c37fc0, L_0x2c380b0, L_0x2c381a0; -L_0x2c382b0 .delay (10000,10000,10000) L_0x2c382b0/d; -v0x29b3710_0 .net "S0", 0 0, L_0x2c37c20; 1 drivers -v0x29b3460_0 .net "S1", 0 0, L_0x2c37d50; 1 drivers -v0x29b3500_0 .net "in0", 0 0, L_0x2c38560; 1 drivers -v0x29b7440_0 .net "in1", 0 0, L_0x2c38600; 1 drivers -v0x29b74c0_0 .net "in2", 0 0, L_0x2c386a0; 1 drivers -v0x29b7190_0 .net "in3", 0 0, L_0x2c38a80; 1 drivers -v0x29b7230_0 .net "nS0", 0 0, L_0x2c37a80; 1 drivers -v0x29ba750_0 .net "nS1", 0 0, L_0x2c37e20; 1 drivers -v0x29ba7f0_0 .net "out", 0 0, L_0x2c382b0; 1 drivers -v0x29ba4a0_0 .net "out0", 0 0, L_0x2c37e80; 1 drivers -v0x29ba520_0 .net "out1", 0 0, L_0x2c37fc0; 1 drivers -v0x29b9530_0 .net "out2", 0 0, L_0x2c380b0; 1 drivers -v0x29b9280_0 .net "out3", 0 0, L_0x2c381a0; 1 drivers -S_0x29aafb0 .scope module, "OneMux" "FourInMux" 3 293, 3 24, S_0x29ad350; - .timescale -9 -12; -L_0x2c38800/d .functor NOT 1, L_0x2c393f0, C4<0>, C4<0>, C4<0>; -L_0x2c38800 .delay (10000,10000,10000) L_0x2c38800/d; -L_0x2c388f0/d .functor NOT 1, L_0x2c38b70, C4<0>, C4<0>, C4<0>; -L_0x2c388f0 .delay (10000,10000,10000) L_0x2c388f0/d; -L_0x2c38990/d .functor NAND 1, L_0x2c38800, L_0x2c388f0, L_0x2c38ca0, C4<1>; -L_0x2c38990 .delay (10000,10000,10000) L_0x2c38990/d; -L_0x2c38e50/d .functor NAND 1, L_0x2c393f0, L_0x2c388f0, L_0x2c39780, C4<1>; -L_0x2c38e50 .delay (10000,10000,10000) L_0x2c38e50/d; -L_0x2c38f40/d .functor NAND 1, L_0x2c38800, L_0x2c38b70, L_0x2c39820, C4<1>; -L_0x2c38f40 .delay (10000,10000,10000) L_0x2c38f40/d; -L_0x2c39030/d .functor NAND 1, L_0x2c393f0, L_0x2c38b70, L_0x2c39520, C4<1>; -L_0x2c39030 .delay (10000,10000,10000) L_0x2c39030/d; -L_0x2c39140/d .functor NAND 1, L_0x2c38990, L_0x2c38e50, L_0x2c38f40, L_0x2c39030; -L_0x2c39140 .delay (10000,10000,10000) L_0x2c39140/d; -v0x29aeaf0_0 .net "S0", 0 0, L_0x2c393f0; 1 drivers -v0x29aeb90_0 .net "S1", 0 0, L_0x2c38b70; 1 drivers -v0x29ae840_0 .net "in0", 0 0, L_0x2c38ca0; 1 drivers -v0x29ae8e0_0 .net "in1", 0 0, L_0x2c39780; 1 drivers -v0x29ad8b0_0 .net "in2", 0 0, L_0x2c39820; 1 drivers -v0x29ad950_0 .net "in3", 0 0, L_0x2c39520; 1 drivers -v0x29ad660_0 .net "nS0", 0 0, L_0x2c38800; 1 drivers -v0x29aad00_0 .net "nS1", 0 0, L_0x2c388f0; 1 drivers -v0x29aad80_0 .net "out", 0 0, L_0x2c39140; 1 drivers -v0x29b1620_0 .net "out0", 0 0, L_0x2c38990; 1 drivers -v0x29b16c0_0 .net "out1", 0 0, L_0x2c38e50; 1 drivers -v0x29b1390_0 .net "out2", 0 0, L_0x2c38f40; 1 drivers -v0x29b4950_0 .net "out3", 0 0, L_0x2c39030; 1 drivers -S_0x29ad0a0 .scope module, "TwoMux" "TwoInMux" 3 294, 3 8, S_0x29ad350; - .timescale -9 -12; -L_0x2c39610/d .functor NOT 1, L_0x2c398c0, C4<0>, C4<0>, C4<0>; -L_0x2c39610 .delay (10000,10000,10000) L_0x2c39610/d; -L_0x2c39700/d .functor AND 1, L_0x2c39960, L_0x2c39610, C4<1>, C4<1>; -L_0x2c39700 .delay (20000,20000,20000) L_0x2c39700/d; -L_0x2c39bc0/d .functor AND 1, L_0x2c39a50, L_0x2c398c0, C4<1>, C4<1>; -L_0x2c39bc0 .delay (20000,20000,20000) L_0x2c39bc0/d; -L_0x2c39cb0/d .functor OR 1, L_0x2c39700, L_0x2c39bc0, C4<0>, C4<0>; -L_0x2c39cb0 .delay (20000,20000,20000) L_0x2c39cb0/d; -v0x29acdf0_0 .net "S", 0 0, L_0x2c398c0; 1 drivers -v0x29ace90_0 .net "in0", 0 0, L_0x2c39960; 1 drivers -v0x29ab7c0_0 .net "in1", 0 0, L_0x2c39a50; 1 drivers -v0x29ab860_0 .net "nS", 0 0, L_0x2c39610; 1 drivers -v0x29ab510_0 .net "out0", 0 0, L_0x2c39700; 1 drivers -v0x29ab5b0_0 .net "out1", 0 0, L_0x2c39bc0; 1 drivers -v0x29ab2c0_0 .net "outfinal", 0 0, L_0x2c39cb0; 1 drivers -S_0x29a1690 .scope generate, "muxbits[5]" "muxbits[5]" 3 290, 3 290, S_0x29738d0; - .timescale -9 -12; -P_0x2990198 .param/l "i" 3 290, +C4<0101>; -L_0x2c3c500/d .functor OR 1, L_0x2c3cd80, L_0x2c3c9a0, C4<0>, C4<0>; -L_0x2c3c500 .delay (20000,20000,20000) L_0x2c3c500/d; -v0x29a7840_0 .net *"_s15", 0 0, L_0x2c3cd80; 1 drivers -v0x29a4ec0_0 .net *"_s16", 0 0, L_0x2c3c9a0; 1 drivers -S_0x29a6f90 .scope module, "ZeroMux" "FourInMux" 3 292, 3 24, S_0x29a1690; - .timescale -9 -12; -L_0x2c3a420/d .functor NOT 1, L_0x2c3af90, C4<0>, C4<0>, C4<0>; -L_0x2c3a420 .delay (10000,10000,10000) L_0x2c3a420/d; -L_0x2c3a4d0/d .functor NOT 1, L_0x2c3a6d0, C4<0>, C4<0>, C4<0>; -L_0x2c3a4d0 .delay (10000,10000,10000) L_0x2c3a4d0/d; -L_0x2c3a530/d .functor NAND 1, L_0x2c3a420, L_0x2c3a4d0, L_0x2c3a800, C4<1>; -L_0x2c3a530 .delay (10000,10000,10000) L_0x2c3a530/d; -L_0x2c3aa20/d .functor NAND 1, L_0x2c3af90, L_0x2c3a4d0, L_0x2c3a8a0, C4<1>; -L_0x2c3aa20 .delay (10000,10000,10000) L_0x2c3aa20/d; -L_0x2c3ab10/d .functor NAND 1, L_0x2c3a420, L_0x2c3a6d0, L_0x2c3b390, C4<1>; -L_0x2c3ab10 .delay (10000,10000,10000) L_0x2c3ab10/d; -L_0x2c3ac00/d .functor NAND 1, L_0x2c3af90, L_0x2c3a6d0, L_0x2c3b0c0, C4<1>; -L_0x2c3ac00 .delay (10000,10000,10000) L_0x2c3ac00/d; -L_0x2c3ace0/d .functor NAND 1, L_0x2c3a530, L_0x2c3aa20, L_0x2c3ab10, L_0x2c3ac00; -L_0x2c3ace0 .delay (10000,10000,10000) L_0x2c3ace0/d; -v0x29a5960_0 .net "S0", 0 0, L_0x2c3af90; 1 drivers -v0x29a5a00_0 .net "S1", 0 0, L_0x2c3a6d0; 1 drivers -v0x29a56b0_0 .net "in0", 0 0, L_0x2c3a800; 1 drivers -v0x29a5750_0 .net "in1", 0 0, L_0x2c3a8a0; 1 drivers -v0x29a5400_0 .net "in2", 0 0, L_0x2c3b390; 1 drivers -v0x29a54a0_0 .net "in3", 0 0, L_0x2c3b0c0; 1 drivers -v0x29a5170_0 .net "nS0", 0 0, L_0x2c3a420; 1 drivers -v0x29a8c90_0 .net "nS1", 0 0, L_0x2c3a4d0; 1 drivers -v0x29a8d30_0 .net "out", 0 0, L_0x2c3ace0; 1 drivers -v0x29a89e0_0 .net "out0", 0 0, L_0x2c3a530; 1 drivers -v0x29a8a80_0 .net "out1", 0 0, L_0x2c3aa20; 1 drivers -v0x29a7a50_0 .net "out2", 0 0, L_0x2c3ab10; 1 drivers -v0x29a77a0_0 .net "out3", 0 0, L_0x2c3ac00; 1 drivers -S_0x29a2e30 .scope module, "OneMux" "FourInMux" 3 293, 3 24, S_0x29a1690; - .timescale -9 -12; -L_0x2c3b1b0/d .functor NOT 1, L_0x2c3b480, C4<0>, C4<0>, C4<0>; -L_0x2c3b1b0 .delay (10000,10000,10000) L_0x2c3b1b0/d; -L_0x2c3b260/d .functor NOT 1, L_0x2c3b5b0, C4<0>, C4<0>, C4<0>; -L_0x2c3b260 .delay (10000,10000,10000) L_0x2c3b260/d; -L_0x2c3b300/d .functor NAND 1, L_0x2c3b1b0, L_0x2c3b260, L_0x2c3c140, C4<1>; -L_0x2c3b300 .delay (10000,10000,10000) L_0x2c3b300/d; -L_0x2c3b840/d .functor NAND 1, L_0x2c3b480, L_0x2c3b260, L_0x2c3c1e0, C4<1>; -L_0x2c3b840 .delay (10000,10000,10000) L_0x2c3b840/d; -L_0x2c3b930/d .functor NAND 1, L_0x2c3b1b0, L_0x2c3b5b0, L_0x2c3be40, C4<1>; -L_0x2c3b930 .delay (10000,10000,10000) L_0x2c3b930/d; -L_0x2c3ba20/d .functor NAND 1, L_0x2c3b480, L_0x2c3b5b0, L_0x2c3bf30, C4<1>; -L_0x2c3ba20 .delay (10000,10000,10000) L_0x2c3ba20/d; -L_0x2c3bb90/d .functor NAND 1, L_0x2c3b300, L_0x2c3b840, L_0x2c3b930, L_0x2c3ba20; -L_0x2c3bb90 .delay (10000,10000,10000) L_0x2c3bb90/d; -v0x299f390_0 .net "S0", 0 0, L_0x2c3b480; 1 drivers -v0x29a2b80_0 .net "S1", 0 0, L_0x2c3b5b0; 1 drivers -v0x29a2c00_0 .net "in0", 0 0, L_0x2c3c140; 1 drivers -v0x29a1bf0_0 .net "in1", 0 0, L_0x2c3c1e0; 1 drivers -v0x29a1c90_0 .net "in2", 0 0, L_0x2c3be40; 1 drivers -v0x29a1940_0 .net "in3", 0 0, L_0x2c3bf30; 1 drivers -v0x29a19e0_0 .net "nS0", 0 0, L_0x2c3b1b0; 1 drivers -v0x299f060_0 .net "nS1", 0 0, L_0x2c3b260; 1 drivers -v0x299eda0_0 .net "out", 0 0, L_0x2c3bb90; 1 drivers -v0x299ee40_0 .net "out0", 0 0, L_0x2c3b300; 1 drivers -v0x29a74f0_0 .net "out1", 0 0, L_0x2c3b840; 1 drivers -v0x29a7590_0 .net "out2", 0 0, L_0x2c3b930; 1 drivers -v0x29a72d0_0 .net "out3", 0 0, L_0x2c3ba20; 1 drivers -S_0x29a13e0 .scope module, "TwoMux" "TwoInMux" 3 294, 3 8, S_0x29a1690; - .timescale -9 -12; -L_0x2c3c020/d .functor NOT 1, L_0x2c3c900, C4<0>, C4<0>, C4<0>; -L_0x2c3c020 .delay (10000,10000,10000) L_0x2c3c020/d; -L_0x2c3b6e0/d .functor AND 1, L_0x2c3c280, L_0x2c3c020, C4<1>, C4<1>; -L_0x2c3b6e0 .delay (20000,20000,20000) L_0x2c3b6e0/d; -L_0x2c3c630/d .functor AND 1, L_0x2c3c370, L_0x2c3c900, C4<1>, C4<1>; -L_0x2c3c630 .delay (20000,20000,20000) L_0x2c3c630/d; -L_0x2c3c720/d .functor OR 1, L_0x2c3b6e0, L_0x2c3c630, C4<0>, C4<0>; -L_0x2c3c720 .delay (20000,20000,20000) L_0x2c3c720/d; -v0x29a1130_0 .net "S", 0 0, L_0x2c3c900; 1 drivers -v0x29a11d0_0 .net "in0", 0 0, L_0x2c3c280; 1 drivers -v0x299fb00_0 .net "in1", 0 0, L_0x2c3c370; 1 drivers -v0x299fba0_0 .net "nS", 0 0, L_0x2c3c020; 1 drivers -v0x299f870_0 .net "out0", 0 0, L_0x2c3b6e0; 1 drivers -v0x299f5a0_0 .net "out1", 0 0, L_0x2c3c630; 1 drivers -v0x299f2f0_0 .net "outfinal", 0 0, L_0x2c3c720; 1 drivers -S_0x298b2c0 .scope generate, "muxbits[6]" "muxbits[6]" 3 290, 3 290, S_0x29738d0; - .timescale -9 -12; -P_0x297e538 .param/l "i" 3 290, +C4<0110>; -L_0x2c3ea80/d .functor OR 1, L_0x2c3f550, L_0x2c3f5f0, C4<0>, C4<0>; -L_0x2c3ea80 .delay (20000,20000,20000) L_0x2c3ea80/d; -v0x299be70_0 .net *"_s15", 0 0, L_0x2c3f550; 1 drivers -v0x299bb20_0 .net *"_s16", 0 0, L_0x2c3f5f0; 1 drivers -S_0x29971d0 .scope module, "ZeroMux" "FourInMux" 3 292, 3 24, S_0x298b2c0; - .timescale -9 -12; -L_0x2c3ca90/d .functor NOT 1, L_0x2c3ce20, C4<0>, C4<0>, C4<0>; -L_0x2c3ca90 .delay (10000,10000,10000) L_0x2c3ca90/d; -L_0x2c3cb80/d .functor NOT 1, L_0x2c3cf50, C4<0>, C4<0>, C4<0>; -L_0x2c3cb80 .delay (10000,10000,10000) L_0x2c3cb80/d; -L_0x2c3cc20/d .functor NAND 1, L_0x2c3ca90, L_0x2c3cb80, L_0x2c3d080, C4<1>; -L_0x2c3cc20 .delay (10000,10000,10000) L_0x2c3cc20/d; -L_0x2c3d200/d .functor NAND 1, L_0x2c3ce20, L_0x2c3cb80, L_0x2c3db10, C4<1>; -L_0x2c3d200 .delay (10000,10000,10000) L_0x2c3d200/d; -L_0x2c3d2f0/d .functor NAND 1, L_0x2c3ca90, L_0x2c3cf50, L_0x2c3d7a0, C4<1>; -L_0x2c3d2f0 .delay (10000,10000,10000) L_0x2c3d2f0/d; -L_0x2c3d3e0/d .functor NAND 1, L_0x2c3ce20, L_0x2c3cf50, L_0x2c3d840, C4<1>; -L_0x2c3d3e0 .delay (10000,10000,10000) L_0x2c3d3e0/d; -L_0x2c3d4f0/d .functor NAND 1, L_0x2c3cc20, L_0x2c3d200, L_0x2c3d2f0, L_0x2c3d3e0; -L_0x2c3d4f0 .delay (10000,10000,10000) L_0x2c3d4f0/d; -v0x2996f20_0 .net "S0", 0 0, L_0x2c3ce20; 1 drivers -v0x2995fb0_0 .net "S1", 0 0, L_0x2c3cf50; 1 drivers -v0x2996050_0 .net "in0", 0 0, L_0x2c3d080; 1 drivers -v0x2995d00_0 .net "in1", 0 0, L_0x2c3db10; 1 drivers -v0x2995d80_0 .net "in2", 0 0, L_0x2c3d7a0; 1 drivers -v0x2999ce0_0 .net "in3", 0 0, L_0x2c3d840; 1 drivers -v0x2999d80_0 .net "nS0", 0 0, L_0x2c3ca90; 1 drivers -v0x2999a30_0 .net "nS1", 0 0, L_0x2c3cb80; 1 drivers -v0x2999ad0_0 .net "out", 0 0, L_0x2c3d4f0; 1 drivers -v0x299cff0_0 .net "out0", 0 0, L_0x2c3cc20; 1 drivers -v0x299d070_0 .net "out1", 0 0, L_0x2c3d200; 1 drivers -v0x299cd40_0 .net "out2", 0 0, L_0x2c3d2f0; 1 drivers -v0x299bdd0_0 .net "out3", 0 0, L_0x2c3d3e0; 1 drivers -S_0x298db40 .scope module, "OneMux" "FourInMux" 3 293, 3 24, S_0x298b2c0; - .timescale -9 -12; -L_0x2c3d930/d .functor NOT 1, L_0x2c3e630, C4<0>, C4<0>, C4<0>; -L_0x2c3d930 .delay (10000,10000,10000) L_0x2c3d930/d; -L_0x2c3da20/d .functor NOT 1, L_0x2c3dbb0, C4<0>, C4<0>, C4<0>; -L_0x2c3da20 .delay (10000,10000,10000) L_0x2c3da20/d; -L_0x2c3df40/d .functor NAND 1, L_0x2c3d930, L_0x2c3da20, L_0x2c3dce0, C4<1>; -L_0x2c3df40 .delay (10000,10000,10000) L_0x2c3df40/d; -L_0x2c3e030/d .functor NAND 1, L_0x2c3e630, L_0x2c3da20, L_0x2c3dd80, C4<1>; -L_0x2c3e030 .delay (10000,10000,10000) L_0x2c3e030/d; -L_0x2c3e120/d .functor NAND 1, L_0x2c3d930, L_0x2c3dbb0, L_0x2c3de20, C4<1>; -L_0x2c3e120 .delay (10000,10000,10000) L_0x2c3e120/d; -L_0x2c3e210/d .functor NAND 1, L_0x2c3e630, L_0x2c3dbb0, L_0x2c3eb20, C4<1>; -L_0x2c3e210 .delay (10000,10000,10000) L_0x2c3e210/d; -L_0x2c3e380/d .functor NAND 1, L_0x2c3df40, L_0x2c3e030, L_0x2c3e120, L_0x2c3e210; -L_0x2c3e380 .delay (10000,10000,10000) L_0x2c3e380/d; -v0x298d890_0 .net "S0", 0 0, L_0x2c3e630; 1 drivers -v0x298d930_0 .net "S1", 0 0, L_0x2c3dbb0; 1 drivers -v0x29913b0_0 .net "in0", 0 0, L_0x2c3dce0; 1 drivers -v0x2991450_0 .net "in1", 0 0, L_0x2c3dd80; 1 drivers -v0x2991100_0 .net "in2", 0 0, L_0x2c3de20; 1 drivers -v0x29911a0_0 .net "in3", 0 0, L_0x2c3eb20; 1 drivers -v0x29901f0_0 .net "nS0", 0 0, L_0x2c3d930; 1 drivers -v0x298fee0_0 .net "nS1", 0 0, L_0x2c3da20; 1 drivers -v0x298ff60_0 .net "out", 0 0, L_0x2c3e380; 1 drivers -v0x298d5e0_0 .net "out0", 0 0, L_0x2c3df40; 1 drivers -v0x298d680_0 .net "out1", 0 0, L_0x2c3e030; 1 drivers -v0x2993ee0_0 .net "out2", 0 0, L_0x2c3e120; 1 drivers -v0x2993c30_0 .net "out3", 0 0, L_0x2c3e210; 1 drivers -S_0x298a330 .scope module, "TwoMux" "TwoInMux" 3 294, 3 8, S_0x298b2c0; - .timescale -9 -12; -L_0x2c3ec10/d .functor NOT 1, L_0x2c3e760, C4<0>, C4<0>, C4<0>; -L_0x2c3ec10 .delay (10000,10000,10000) L_0x2c3ec10/d; -L_0x2c3ed00/d .functor AND 1, L_0x2c3e800, L_0x2c3ec10, C4<1>, C4<1>; -L_0x2c3ed00 .delay (20000,20000,20000) L_0x2c3ed00/d; -L_0x2c3edf0/d .functor AND 1, L_0x2c3e8f0, L_0x2c3e760, C4<1>, C4<1>; -L_0x2c3edf0 .delay (20000,20000,20000) L_0x2c3edf0/d; -L_0x2c3eee0/d .functor OR 1, L_0x2c3ed00, L_0x2c3edf0, C4<0>, C4<0>; -L_0x2c3eee0 .delay (20000,20000,20000) L_0x2c3eee0/d; -v0x298a080_0 .net "S", 0 0, L_0x2c3e760; 1 drivers -v0x298a120_0 .net "in0", 0 0, L_0x2c3e800; 1 drivers -v0x2987780_0 .net "in1", 0 0, L_0x2c3e8f0; 1 drivers -v0x2987820_0 .net "nS", 0 0, L_0x2c3ec10; 1 drivers -v0x298e0a0_0 .net "out0", 0 0, L_0x2c3ed00; 1 drivers -v0x298e140_0 .net "out1", 0 0, L_0x2c3edf0; 1 drivers -v0x298de50_0 .net "outfinal", 0 0, L_0x2c3eee0; 1 drivers -S_0x297f8c0 .scope generate, "muxbits[7]" "muxbits[7]" 3 290, 3 290, S_0x29738d0; - .timescale -9 -12; -P_0x296a708 .param/l "i" 3 290, +C4<0111>; -L_0x2c41410/d .functor OR 1, L_0x2c41550, L_0x2c41b90, C4<0>, C4<0>; -L_0x2c41410 .delay (20000,20000,20000) L_0x2c41410/d; -v0x2987ad0_0 .net *"_s15", 0 0, L_0x2c41550; 1 drivers -v0x298b590_0 .net *"_s16", 0 0, L_0x2c41b90; 1 drivers -S_0x2984220 .scope module, "ZeroMux" "FourInMux" 3 292, 3 24, S_0x297f8c0; - .timescale -9 -12; -L_0x2c31d60/d .functor NOT 1, L_0x2c3fdd0, C4<0>, C4<0>, C4<0>; -L_0x2c31d60 .delay (10000,10000,10000) L_0x2c31d60/d; -L_0x2c3f0c0/d .functor NOT 1, L_0x2c3f6e0, C4<0>, C4<0>, C4<0>; -L_0x2c3f0c0 .delay (10000,10000,10000) L_0x2c3f0c0/d; -L_0x2c3f120/d .functor NAND 1, L_0x2c31d60, L_0x2c3f0c0, L_0x2c3f810, C4<1>; -L_0x2c3f120 .delay (10000,10000,10000) L_0x2c3f120/d; -L_0x2c3f220/d .functor NAND 1, L_0x2c3fdd0, L_0x2c3f0c0, L_0x2c3f8b0, C4<1>; -L_0x2c3f220 .delay (10000,10000,10000) L_0x2c3f220/d; -L_0x2c3f2d0/d .functor NAND 1, L_0x2c31d60, L_0x2c3f6e0, L_0x2c3f950, C4<1>; -L_0x2c3f2d0 .delay (10000,10000,10000) L_0x2c3f2d0/d; -L_0x2c3f3c0/d .functor NAND 1, L_0x2c3fdd0, L_0x2c3f6e0, L_0x2c3fa40, C4<1>; -L_0x2c3f3c0 .delay (10000,10000,10000) L_0x2c3f3c0/d; -L_0x2c3fb20/d .functor NAND 1, L_0x2c3f120, L_0x2c3f220, L_0x2c3f2d0, L_0x2c3f3c0; -L_0x2c3fb20 .delay (10000,10000,10000) L_0x2c3fb20/d; -v0x2981920_0 .net "S0", 0 0, L_0x2c3fdd0; 1 drivers -v0x29819c0_0 .net "S1", 0 0, L_0x2c3f6e0; 1 drivers -v0x2989dd0_0 .net "in0", 0 0, L_0x2c3f810; 1 drivers -v0x2989e70_0 .net "in1", 0 0, L_0x2c3f8b0; 1 drivers -v0x2989b20_0 .net "in2", 0 0, L_0x2c3f950; 1 drivers -v0x2989bc0_0 .net "in3", 0 0, L_0x2c3fa40; 1 drivers -v0x2989890_0 .net "nS0", 0 0, L_0x2c31d60; 1 drivers -v0x2988240_0 .net "nS1", 0 0, L_0x2c3f0c0; 1 drivers -v0x29882e0_0 .net "out", 0 0, L_0x2c3fb20; 1 drivers -v0x2987f90_0 .net "out0", 0 0, L_0x2c3f120; 1 drivers -v0x2988030_0 .net "out1", 0 0, L_0x2c3f220; 1 drivers -v0x2987ce0_0 .net "out2", 0 0, L_0x2c3f2d0; 1 drivers -v0x2987a30_0 .net "out3", 0 0, L_0x2c3f3c0; 1 drivers -S_0x2983a10 .scope module, "OneMux" "FourInMux" 3 293, 3 24, S_0x297f8c0; - .timescale -9 -12; -L_0x2c40380/d .functor NOT 1, L_0x2c3ff00, C4<0>, C4<0>, C4<0>; -L_0x2c40380 .delay (10000,10000,10000) L_0x2c40380/d; -L_0x2c40430/d .functor NOT 1, L_0x2c40030, C4<0>, C4<0>, C4<0>; -L_0x2c40430 .delay (10000,10000,10000) L_0x2c40430/d; -L_0x2c404d0/d .functor NAND 1, L_0x2c40380, L_0x2c40430, L_0x2c40160, C4<1>; -L_0x2c404d0 .delay (10000,10000,10000) L_0x2c404d0/d; -L_0x2c40610/d .functor NAND 1, L_0x2c3ff00, L_0x2c40430, L_0x2c40200, C4<1>; -L_0x2c40610 .delay (10000,10000,10000) L_0x2c40610/d; -L_0x2c40700/d .functor NAND 1, L_0x2c40380, L_0x2c40030, L_0x2c410a0, C4<1>; -L_0x2c40700 .delay (10000,10000,10000) L_0x2c40700/d; -L_0x2c40820/d .functor NAND 1, L_0x2c3ff00, L_0x2c40030, L_0x2c41140, C4<1>; -L_0x2c40820 .delay (10000,10000,10000) L_0x2c40820/d; -L_0x2c40990/d .functor NAND 1, L_0x2c404d0, L_0x2c40610, L_0x2c40700, L_0x2c40820; -L_0x2c40990 .delay (10000,10000,10000) L_0x2c40990/d; -v0x2983d60_0 .net "S0", 0 0, L_0x2c3ff00; 1 drivers -v0x29823e0_0 .net "S1", 0 0, L_0x2c40030; 1 drivers -v0x2982460_0 .net "in0", 0 0, L_0x2c40160; 1 drivers -v0x2982130_0 .net "in1", 0 0, L_0x2c40200; 1 drivers -v0x29821d0_0 .net "in2", 0 0, L_0x2c410a0; 1 drivers -v0x2981e80_0 .net "in3", 0 0, L_0x2c41140; 1 drivers -v0x2981f20_0 .net "nS0", 0 0, L_0x2c40380; 1 drivers -v0x2981bf0_0 .net "nS1", 0 0, L_0x2c40430; 1 drivers -v0x2985710_0 .net "out", 0 0, L_0x2c40990; 1 drivers -v0x29857b0_0 .net "out0", 0 0, L_0x2c404d0; 1 drivers -v0x2985460_0 .net "out1", 0 0, L_0x2c40610; 1 drivers -v0x2985500_0 .net "out2", 0 0, L_0x2c40700; 1 drivers -v0x2984560_0 .net "out3", 0 0, L_0x2c40820; 1 drivers -S_0x297f610 .scope module, "TwoMux" "TwoInMux" 3 294, 3 8, S_0x297f8c0; - .timescale -9 -12; -L_0x2c408b0/d .functor NOT 1, L_0x2c41650, C4<0>, C4<0>, C4<0>; -L_0x2c408b0 .delay (10000,10000,10000) L_0x2c408b0/d; -L_0x2c40c90/d .functor AND 1, L_0x2c411e0, L_0x2c408b0, C4<1>, C4<1>; -L_0x2c40c90 .delay (20000,20000,20000) L_0x2c40c90/d; -L_0x2c40d80/d .functor AND 1, L_0x2c41280, L_0x2c41650, C4<1>, C4<1>; -L_0x2c40d80 .delay (20000,20000,20000) L_0x2c40d80/d; -L_0x2c40e70/d .functor OR 1, L_0x2c40c90, L_0x2c40d80, C4<0>, C4<0>; -L_0x2c40e70 .delay (20000,20000,20000) L_0x2c40e70/d; -v0x297f380_0 .net "S", 0 0, L_0x2c41650; 1 drivers -v0x297f420_0 .net "in0", 0 0, L_0x2c411e0; 1 drivers -v0x297e6e0_0 .net "in1", 0 0, L_0x2c41280; 1 drivers -v0x297e780_0 .net "nS", 0 0, L_0x2c408b0; 1 drivers -v0x297e470_0 .net "out0", 0 0, L_0x2c40c90; 1 drivers -v0x2983f70_0 .net "out1", 0 0, L_0x2c40d80; 1 drivers -v0x2983cc0_0 .net "outfinal", 0 0, L_0x2c40e70; 1 drivers -S_0x296c740 .scope generate, "muxbits[8]" "muxbits[8]" 3 290, 3 290, S_0x29738d0; - .timescale -9 -12; -P_0x2ae54d8 .param/l "i" 3 290, +C4<01000>; -L_0x2c3a2c0/d .functor OR 1, L_0x2c3a610, L_0x2c44050, C4<0>, C4<0>; -L_0x2c3a2c0 .delay (20000,20000,20000) L_0x2c3a2c0/d; -v0x297c790_0 .net *"_s15", 0 0, L_0x2c3a610; 1 drivers -v0x297c460_0 .net *"_s16", 0 0, L_0x2c44050; 1 drivers -S_0x2973020 .scope module, "ZeroMux" "FourInMux" 3 292, 3 24, S_0x296c740; - .timescale -9 -12; -L_0x2c41c30/d .functor NOT 1, L_0x2c416f0, C4<0>, C4<0>, C4<0>; -L_0x2c41c30 .delay (10000,10000,10000) L_0x2c41c30/d; -L_0x2c41d20/d .functor NOT 1, L_0x2c41820, C4<0>, C4<0>, C4<0>; -L_0x2c41d20 .delay (10000,10000,10000) L_0x2c41d20/d; -L_0x2c41dc0/d .functor NAND 1, L_0x2c41c30, L_0x2c41d20, L_0x2c41950, C4<1>; -L_0x2c41dc0 .delay (10000,10000,10000) L_0x2c41dc0/d; -L_0x2c41f00/d .functor NAND 1, L_0x2c416f0, L_0x2c41d20, L_0x2c419f0, C4<1>; -L_0x2c41f00 .delay (10000,10000,10000) L_0x2c41f00/d; -L_0x2c41ff0/d .functor NAND 1, L_0x2c41c30, L_0x2c41820, L_0x2c41a90, C4<1>; -L_0x2c41ff0 .delay (10000,10000,10000) L_0x2c41ff0/d; -L_0x2c42140/d .functor NAND 1, L_0x2c416f0, L_0x2c41820, L_0x2c42a00, C4<1>; -L_0x2c42140 .delay (10000,10000,10000) L_0x2c42140/d; -L_0x2c42280/d .functor NAND 1, L_0x2c41dc0, L_0x2c41f00, L_0x2c41ff0, L_0x2c42140; -L_0x2c42280 .delay (10000,10000,10000) L_0x2c42280/d; -v0x2972d90_0 .net "S0", 0 0, L_0x2c416f0; 1 drivers -v0x2976b90_0 .net "S1", 0 0, L_0x2c41820; 1 drivers -v0x2976c30_0 .net "in0", 0 0, L_0x2c41950; 1 drivers -v0x2976900_0 .net "in1", 0 0, L_0x2c419f0; 1 drivers -v0x2976980_0 .net "in2", 0 0, L_0x2c41a90; 1 drivers -v0x2979d20_0 .net "in3", 0 0, L_0x2c42a00; 1 drivers -v0x2979dc0_0 .net "nS0", 0 0, L_0x2c41c30; 1 drivers -v0x2979a90_0 .net "nS1", 0 0, L_0x2c41d20; 1 drivers -v0x2979b30_0 .net "out", 0 0, L_0x2c42280; 1 drivers -v0x2978b80_0 .net "out0", 0 0, L_0x2c41dc0; 1 drivers -v0x2978c00_0 .net "out1", 0 0, L_0x2c41f00; 1 drivers -v0x29788f0_0 .net "out2", 0 0, L_0x2c41ff0; 1 drivers -v0x297c6f0_0 .net "out3", 0 0, L_0x2c42140; 1 drivers -S_0x296e3d0 .scope module, "OneMux" "FourInMux" 3 293, 3 24, S_0x296c740; - .timescale -9 -12; -L_0x2c421a0/d .functor NOT 1, L_0x2c433f0, C4<0>, C4<0>, C4<0>; -L_0x2c421a0 .delay (10000,10000,10000) L_0x2c421a0/d; -L_0x2c425c0/d .functor NOT 1, L_0x2c42af0, C4<0>, C4<0>, C4<0>; -L_0x2c425c0 .delay (10000,10000,10000) L_0x2c425c0/d; -L_0x2c42660/d .functor NAND 1, L_0x2c421a0, L_0x2c425c0, L_0x2c42c20, C4<1>; -L_0x2c42660 .delay (10000,10000,10000) L_0x2c42660/d; -L_0x2c427a0/d .functor NAND 1, L_0x2c433f0, L_0x2c425c0, L_0x2c42cc0, C4<1>; -L_0x2c427a0 .delay (10000,10000,10000) L_0x2c427a0/d; -L_0x2c42890/d .functor NAND 1, L_0x2c421a0, L_0x2c42af0, L_0x2c42d60, C4<1>; -L_0x2c42890 .delay (10000,10000,10000) L_0x2c42890/d; -L_0x2c42fd0/d .functor NAND 1, L_0x2c433f0, L_0x2c42af0, L_0x2c42e50, C4<1>; -L_0x2c42fd0 .delay (10000,10000,10000) L_0x2c42fd0/d; -L_0x2c43140/d .functor NAND 1, L_0x2c42660, L_0x2c427a0, L_0x2c42890, L_0x2c42fd0; -L_0x2c43140 .delay (10000,10000,10000) L_0x2c43140/d; -v0x296e110_0 .net "S0", 0 0, L_0x2c433f0; 1 drivers -v0x296e1b0_0 .net "S1", 0 0, L_0x2c42af0; 1 drivers -v0x296d470_0 .net "in0", 0 0, L_0x2c42c20; 1 drivers -v0x296d510_0 .net "in1", 0 0, L_0x2c42cc0; 1 drivers -v0x296d1e0_0 .net "in2", 0 0, L_0x2c42d60; 1 drivers -v0x296d280_0 .net "in3", 0 0, L_0x2c42e50; 1 drivers -v0x296a760_0 .net "nS0", 0 0, L_0x2c421a0; 1 drivers -v0x2971030_0 .net "nS1", 0 0, L_0x2c425c0; 1 drivers -v0x29710b0_0 .net "out", 0 0, L_0x2c43140; 1 drivers -v0x2970da0_0 .net "out0", 0 0, L_0x2c42660; 1 drivers -v0x2970e40_0 .net "out1", 0 0, L_0x2c427a0; 1 drivers -v0x29741e0_0 .net "out2", 0 0, L_0x2c42890; 1 drivers -v0x2973f50_0 .net "out3", 0 0, L_0x2c42fd0; 1 drivers -S_0x296b430 .scope module, "TwoMux" "TwoInMux" 3 294, 3 8, S_0x296c740; - .timescale -9 -12; -L_0x2c42f40/d .functor NOT 1, L_0x2c39e90, C4<0>, C4<0>, C4<0>; -L_0x2c42f40 .delay (10000,10000,10000) L_0x2c42f40/d; -L_0x2c43a80/d .functor AND 1, L_0x2c43520, L_0x2c42f40, C4<1>, C4<1>; -L_0x2c43a80 .delay (20000,20000,20000) L_0x2c43a80/d; -L_0x2c43b70/d .functor AND 1, L_0x2c3a220, L_0x2c39e90, C4<1>, C4<1>; -L_0x2c43b70 .delay (20000,20000,20000) L_0x2c43b70/d; -L_0x2c43c60/d .functor OR 1, L_0x2c43a80, L_0x2c43b70, C4<0>, C4<0>; -L_0x2c43c60 .delay (20000,20000,20000) L_0x2c43c60/d; -v0x296b1a0_0 .net "S", 0 0, L_0x2c39e90; 1 drivers -v0x296b240_0 .net "in0", 0 0, L_0x2c43520; 1 drivers -v0x296af10_0 .net "in1", 0 0, L_0x2c3a220; 1 drivers -v0x296afb0_0 .net "nS", 0 0, L_0x2c42f40; 1 drivers -v0x296ac80_0 .net "out0", 0 0, L_0x2c43a80; 1 drivers -v0x296ad20_0 .net "out1", 0 0, L_0x2c43b70; 1 drivers -v0x296e6c0_0 .net "outfinal", 0 0, L_0x2c43c60; 1 drivers -S_0x2ae3dc0 .scope generate, "muxbits[9]" "muxbits[9]" 3 290, 3 290, S_0x29738d0; - .timescale -9 -12; -P_0x2ad8478 .param/l "i" 3 290, +C4<01001>; -L_0x2c46660/d .functor OR 1, L_0x2c467a0, L_0x2c46840, C4<0>, C4<0>; -L_0x2c46660 .delay (20000,20000,20000) L_0x2c46660/d; -v0x296cff0_0 .net *"_s15", 0 0, L_0x2c467a0; 1 drivers -v0x296cce0_0 .net *"_s16", 0 0, L_0x2c46840; 1 drivers -S_0x2965430 .scope module, "ZeroMux" "FourInMux" 3 292, 3 24, S_0x2ae3dc0; - .timescale -9 -12; -L_0x2c44140/d .functor NOT 1, L_0x2c45160, C4<0>, C4<0>, C4<0>; -L_0x2c44140 .delay (10000,10000,10000) L_0x2c44140/d; -L_0x2c44230/d .functor NOT 1, L_0x2c44790, C4<0>, C4<0>, C4<0>; -L_0x2c44230 .delay (10000,10000,10000) L_0x2c44230/d; -L_0x2c442d0/d .functor NAND 1, L_0x2c44140, L_0x2c44230, L_0x2c448c0, C4<1>; -L_0x2c442d0 .delay (10000,10000,10000) L_0x2c442d0/d; -L_0x2c44410/d .functor NAND 1, L_0x2c45160, L_0x2c44230, L_0x2c44960, C4<1>; -L_0x2c44410 .delay (10000,10000,10000) L_0x2c44410/d; -L_0x2c44500/d .functor NAND 1, L_0x2c44140, L_0x2c44790, L_0x2c44a00, C4<1>; -L_0x2c44500 .delay (10000,10000,10000) L_0x2c44500/d; -L_0x2c44d70/d .functor NAND 1, L_0x2c45160, L_0x2c44790, L_0x2c44af0, C4<1>; -L_0x2c44d70 .delay (10000,10000,10000) L_0x2c44d70/d; -L_0x2c44eb0/d .functor NAND 1, L_0x2c442d0, L_0x2c44410, L_0x2c44500, L_0x2c44d70; -L_0x2c44eb0 .delay (10000,10000,10000) L_0x2c44eb0/d; -v0x29651a0_0 .net "S0", 0 0, L_0x2c45160; 1 drivers -v0x2965240_0 .net "S1", 0 0, L_0x2c44790; 1 drivers -v0x2964ee0_0 .net "in0", 0 0, L_0x2c448c0; 1 drivers -v0x2964f80_0 .net "in1", 0 0, L_0x2c44960; 1 drivers -v0x29689d0_0 .net "in2", 0 0, L_0x2c44a00; 1 drivers -v0x2968a70_0 .net "in3", 0 0, L_0x2c44af0; 1 drivers -v0x2968760_0 .net "nS0", 0 0, L_0x2c44140; 1 drivers -v0x29677a0_0 .net "nS1", 0 0, L_0x2c44230; 1 drivers -v0x2967840_0 .net "out", 0 0, L_0x2c44eb0; 1 drivers -v0x2967510_0 .net "out0", 0 0, L_0x2c442d0; 1 drivers -v0x29675b0_0 .net "out1", 0 0, L_0x2c44410; 1 drivers -v0x2964960_0 .net "out2", 0 0, L_0x2c44500; 1 drivers -v0x296cf50_0 .net "out3", 0 0, L_0x2c44d70; 1 drivers -S_0x2ae78f0 .scope module, "OneMux" "FourInMux" 3 293, 3 24, S_0x2ae3dc0; - .timescale -9 -12; -L_0x2c44dd0/d .functor NOT 1, L_0x2c45290, C4<0>, C4<0>, C4<0>; -L_0x2c44dd0 .delay (10000,10000,10000) L_0x2c44dd0/d; -L_0x2c44c30/d .functor NOT 1, L_0x2c453c0, C4<0>, C4<0>, C4<0>; -L_0x2c44c30 .delay (10000,10000,10000) L_0x2c44c30/d; -L_0x2bef2b0/d .functor NAND 1, L_0x2c44dd0, L_0x2c44c30, L_0x2c454f0, C4<1>; -L_0x2bef2b0 .delay (10000,10000,10000) L_0x2bef2b0/d; -L_0x2bef3f0/d .functor NAND 1, L_0x2c45290, L_0x2c44c30, L_0x2c45590, C4<1>; -L_0x2bef3f0 .delay (10000,10000,10000) L_0x2bef3f0/d; -L_0x2bef510/d .functor NAND 1, L_0x2c44dd0, L_0x2c453c0, L_0x2c45630, C4<1>; -L_0x2bef510 .delay (10000,10000,10000) L_0x2bef510/d; -L_0x2bef660/d .functor NAND 1, L_0x2c45290, L_0x2c453c0, L_0x2c45720, C4<1>; -L_0x2bef660 .delay (10000,10000,10000) L_0x2bef660/d; -L_0x2c46130/d .functor NAND 1, L_0x2bef2b0, L_0x2bef3f0, L_0x2bef510, L_0x2bef660; -L_0x2c46130 .delay (10000,10000,10000) L_0x2c46130/d; -v0x2ae8860_0 .net "S0", 0 0, L_0x2c45290; 1 drivers -v0x2aeaf40_0 .net "S1", 0 0, L_0x2c453c0; 1 drivers -v0x2aeafc0_0 .net "in0", 0 0, L_0x2c454f0; 1 drivers -v0x2aeacc0_0 .net "in1", 0 0, L_0x2c45590; 1 drivers -v0x2aead60_0 .net "in2", 0 0, L_0x2c45630; 1 drivers -v0x2ae9df0_0 .net "in3", 0 0, L_0x2c45720; 1 drivers -v0x2ae9e90_0 .net "nS0", 0 0, L_0x2c44dd0; 1 drivers -v0x29672a0_0 .net "nS1", 0 0, L_0x2c44c30; 1 drivers -v0x2966fc0_0 .net "out", 0 0, L_0x2c46130; 1 drivers -v0x2967060_0 .net "out0", 0 0, L_0x2bef2b0; 1 drivers -v0x2966a40_0 .net "out1", 0 0, L_0x2bef3f0; 1 drivers -v0x2966ae0_0 .net "out2", 0 0, L_0x2bef510; 1 drivers -v0x2965780_0 .net "out3", 0 0, L_0x2bef660; 1 drivers -S_0x2ae2ed0 .scope module, "TwoMux" "TwoInMux" 3 294, 3 8, S_0x2ae3dc0; - .timescale -9 -12; -L_0x2967320/d .functor NOT 1, L_0x2c46df0, C4<0>, C4<0>, C4<0>; -L_0x2967320 .delay (10000,10000,10000) L_0x2967320/d; -L_0x2c46a30/d .functor AND 1, L_0x2c463e0, L_0x2967320, C4<1>, C4<1>; -L_0x2c46a30 .delay (20000,20000,20000) L_0x2c46a30/d; -L_0x2c46b20/d .functor AND 1, L_0x2c464d0, L_0x2c46df0, C4<1>, C4<1>; -L_0x2c46b20 .delay (20000,20000,20000) L_0x2c46b20/d; -L_0x2c46c10/d .functor OR 1, L_0x2c46a30, L_0x2c46b20, C4<0>, C4<0>; -L_0x2c46c10 .delay (20000,20000,20000) L_0x2c46c10/d; -v0x2ae6540_0 .net "S", 0 0, L_0x2c46df0; 1 drivers -v0x2ae65e0_0 .net "in0", 0 0, L_0x2c463e0; 1 drivers -v0x2ae62c0_0 .net "in1", 0 0, L_0x2c464d0; 1 drivers -v0x2ae6360_0 .net "nS", 0 0, L_0x2967320; 1 drivers -v0x2ae5410_0 .net "out0", 0 0, L_0x2c46a30; 1 drivers -v0x2ae8a40_0 .net "out1", 0 0, L_0x2c46b20; 1 drivers -v0x2ae87c0_0 .net "outfinal", 0 0, L_0x2c46c10; 1 drivers -S_0x2ad17d0 .scope generate, "muxbits[10]" "muxbits[10]" 3 290, 3 290, S_0x29738d0; - .timescale -9 -12; -P_0x2ac1588 .param/l "i" 3 290, +C4<01010>; -L_0x2c48e70/d .functor OR 1, L_0x2c48f70, L_0x2c49010, C4<0>, C4<0>; -L_0x2c48e70 .delay (20000,20000,20000) L_0x2c48e70/d; -v0x2ae0a60_0 .net *"_s15", 0 0, L_0x2c48f70; 1 drivers -v0x2ae4040_0 .net *"_s16", 0 0, L_0x2c49010; 1 drivers -S_0x2add110 .scope module, "ZeroMux" "FourInMux" 3 292, 3 24, S_0x2ad17d0; - .timescale -9 -12; -L_0x2c46930/d .functor NOT 1, L_0x2c46e90, C4<0>, C4<0>, C4<0>; -L_0x2c46930 .delay (10000,10000,10000) L_0x2c46930/d; -L_0x2c47510/d .functor NOT 1, L_0x2c46fc0, C4<0>, C4<0>, C4<0>; -L_0x2c47510 .delay (10000,10000,10000) L_0x2c47510/d; -L_0x2c475b0/d .functor NAND 1, L_0x2c46930, L_0x2c47510, L_0x2c470f0, C4<1>; -L_0x2c475b0 .delay (10000,10000,10000) L_0x2c475b0/d; -L_0x2c476f0/d .functor NAND 1, L_0x2c46e90, L_0x2c47510, L_0x2c47190, C4<1>; -L_0x2c476f0 .delay (10000,10000,10000) L_0x2c476f0/d; -L_0x2c477e0/d .functor NAND 1, L_0x2c46930, L_0x2c46fc0, L_0x2c47230, C4<1>; -L_0x2c477e0 .delay (10000,10000,10000) L_0x2c477e0/d; -L_0x2c478d0/d .functor NAND 1, L_0x2c46e90, L_0x2c46fc0, L_0x2c47320, C4<1>; -L_0x2c478d0 .delay (10000,10000,10000) L_0x2c478d0/d; -L_0x2c47a10/d .functor NAND 1, L_0x2c475b0, L_0x2c476f0, L_0x2c477e0, L_0x2c478d0; -L_0x2c47a10 .delay (10000,10000,10000) L_0x2c47a10/d; -v0x2adce90_0 .net "S0", 0 0, L_0x2c46e90; 1 drivers -v0x2adbfa0_0 .net "S1", 0 0, L_0x2c46fc0; 1 drivers -v0x2adc040_0 .net "in0", 0 0, L_0x2c470f0; 1 drivers -v0x2adf620_0 .net "in1", 0 0, L_0x2c47190; 1 drivers -v0x2adf6a0_0 .net "in2", 0 0, L_0x2c47230; 1 drivers -v0x2adf3a0_0 .net "in3", 0 0, L_0x2c47320; 1 drivers -v0x2adf440_0 .net "nS0", 0 0, L_0x2c46930; 1 drivers -v0x2ade4b0_0 .net "nS1", 0 0, L_0x2c47510; 1 drivers -v0x2ade550_0 .net "out", 0 0, L_0x2c47a10; 1 drivers -v0x2ae1b30_0 .net "out0", 0 0, L_0x2c475b0; 1 drivers -v0x2ae1bb0_0 .net "out1", 0 0, L_0x2c476f0; 1 drivers -v0x2ae18b0_0 .net "out2", 0 0, L_0x2c477e0; 1 drivers -v0x2ae09c0_0 .net "out3", 0 0, L_0x2c478d0; 1 drivers -S_0x2ad61e0 .scope module, "OneMux" "FourInMux" 3 293, 3 24, S_0x2ad17d0; - .timescale -9 -12; -L_0x2c47410/d .functor NOT 1, L_0x2c48b60, C4<0>, C4<0>, C4<0>; -L_0x2c47410 .delay (10000,10000,10000) L_0x2c47410/d; -L_0x2c48380/d .functor NOT 1, L_0x2c47cc0, C4<0>, C4<0>, C4<0>; -L_0x2c48380 .delay (10000,10000,10000) L_0x2c48380/d; -L_0x2c48420/d .functor NAND 1, L_0x2c47410, L_0x2c48380, L_0x2c47df0, C4<1>; -L_0x2c48420 .delay (10000,10000,10000) L_0x2c48420/d; -L_0x2c48560/d .functor NAND 1, L_0x2c48b60, L_0x2c48380, L_0x2c47e90, C4<1>; -L_0x2c48560 .delay (10000,10000,10000) L_0x2c48560/d; -L_0x2c48650/d .functor NAND 1, L_0x2c47410, L_0x2c47cc0, L_0x2c47f30, C4<1>; -L_0x2c48650 .delay (10000,10000,10000) L_0x2c48650/d; -L_0x2c48740/d .functor NAND 1, L_0x2c48b60, L_0x2c47cc0, L_0x2c48020, C4<1>; -L_0x2c48740 .delay (10000,10000,10000) L_0x2c48740/d; -L_0x2c488b0/d .functor NAND 1, L_0x2c48420, L_0x2c48560, L_0x2c48650, L_0x2c48740; -L_0x2c488b0 .delay (10000,10000,10000) L_0x2c488b0/d; -v0x2ad5f60_0 .net "S0", 0 0, L_0x2c48b60; 1 drivers -v0x2ad6000_0 .net "S1", 0 0, L_0x2c47cc0; 1 drivers -v0x2ad5070_0 .net "in0", 0 0, L_0x2c47df0; 1 drivers -v0x2ad5110_0 .net "in1", 0 0, L_0x2c47e90; 1 drivers -v0x2ad86f0_0 .net "in2", 0 0, L_0x2c47f30; 1 drivers -v0x2ad8790_0 .net "in3", 0 0, L_0x2c48020; 1 drivers -v0x2ad84d0_0 .net "nS0", 0 0, L_0x2c47410; 1 drivers -v0x2ad7580_0 .net "nS1", 0 0, L_0x2c48380; 1 drivers -v0x2ad7600_0 .net "out", 0 0, L_0x2c488b0; 1 drivers -v0x2adac00_0 .net "out0", 0 0, L_0x2c48420; 1 drivers -v0x2adaca0_0 .net "out1", 0 0, L_0x2c48560; 1 drivers -v0x2ada9a0_0 .net "out2", 0 0, L_0x2c48650; 1 drivers -v0x2ad9ab0_0 .net "out3", 0 0, L_0x2c48740; 1 drivers -S_0x2ad1550 .scope module, "TwoMux" "TwoInMux" 3 294, 3 8, S_0x2ad17d0; - .timescale -9 -12; -L_0x2c48110/d .functor NOT 1, L_0x2c2caa0, C4<0>, C4<0>, C4<0>; -L_0x2c48110 .delay (10000,10000,10000) L_0x2c48110/d; -L_0x2c481c0/d .functor AND 1, L_0x2c2cb40, L_0x2c48110, C4<1>, C4<1>; -L_0x2c481c0 .delay (20000,20000,20000) L_0x2c481c0/d; -L_0x2c2c810/d .functor AND 1, L_0x2c48ce0, L_0x2c2caa0, C4<1>, C4<1>; -L_0x2c2c810 .delay (20000,20000,20000) L_0x2c2c810/d; -L_0x2c2c8c0/d .functor OR 1, L_0x2c481c0, L_0x2c2c810, C4<0>, C4<0>; -L_0x2c2c8c0 .delay (20000,20000,20000) L_0x2c2c8c0/d; -v0x2ad0680_0 .net "S", 0 0, L_0x2c2caa0; 1 drivers -v0x2ad0720_0 .net "in0", 0 0, L_0x2c2cb40; 1 drivers -v0x2ad3cd0_0 .net "in1", 0 0, L_0x2c48ce0; 1 drivers -v0x2ad3d70_0 .net "nS", 0 0, L_0x2c48110; 1 drivers -v0x2ad3a50_0 .net "out0", 0 0, L_0x2c481c0; 1 drivers -v0x2ad3af0_0 .net "out1", 0 0, L_0x2c2c810; 1 drivers -v0x2ad2be0_0 .net "outfinal", 0 0, L_0x2c2c8c0; 1 drivers -S_0x2abb910 .scope generate, "muxbits[11]" "muxbits[11]" 3 290, 3 290, S_0x29738d0; - .timescale -9 -12; -P_0x2aafff8 .param/l "i" 3 290, +C4<01011>; -L_0x2c4b980/d .functor OR 1, L_0x2c4bac0, L_0x2c4bb60, C4<0>, C4<0>; -L_0x2c4b980 .delay (20000,20000,20000) L_0x2c4b980/d; -v0x2acf0f0_0 .net *"_s15", 0 0, L_0x2c4bac0; 1 drivers -v0x2ace1a0_0 .net *"_s16", 0 0, L_0x2c4bb60; 1 drivers -S_0x2ac7280 .scope module, "ZeroMux" "FourInMux" 3 292, 3 24, S_0x2abb910; - .timescale -9 -12; -L_0x2c49100/d .functor NOT 1, L_0x2c4a880, C4<0>, C4<0>, C4<0>; -L_0x2c49100 .delay (10000,10000,10000) L_0x2c49100/d; -L_0x2c491f0/d .functor NOT 1, L_0x2c49af0, C4<0>, C4<0>, C4<0>; -L_0x2c491f0 .delay (10000,10000,10000) L_0x2c491f0/d; -L_0x2c4a190/d .functor NAND 1, L_0x2c49100, L_0x2c491f0, L_0x2c49c20, C4<1>; -L_0x2c4a190 .delay (10000,10000,10000) L_0x2c4a190/d; -L_0x2c4a280/d .functor NAND 1, L_0x2c4a880, L_0x2c491f0, L_0x2c49cc0, C4<1>; -L_0x2c4a280 .delay (10000,10000,10000) L_0x2c4a280/d; -L_0x2c4a370/d .functor NAND 1, L_0x2c49100, L_0x2c49af0, L_0x2c49d60, C4<1>; -L_0x2c4a370 .delay (10000,10000,10000) L_0x2c4a370/d; -L_0x2c4a460/d .functor NAND 1, L_0x2c4a880, L_0x2c49af0, L_0x2c49e50, C4<1>; -L_0x2c4a460 .delay (10000,10000,10000) L_0x2c4a460/d; -L_0x2c4a5d0/d .functor NAND 1, L_0x2c4a190, L_0x2c4a280, L_0x2c4a370, L_0x2c4a460; -L_0x2c4a5d0 .delay (10000,10000,10000) L_0x2c4a5d0/d; -v0x2aca8d0_0 .net "S0", 0 0, L_0x2c4a880; 1 drivers -v0x2aca970_0 .net "S1", 0 0, L_0x2c49af0; 1 drivers -v0x2aca650_0 .net "in0", 0 0, L_0x2c49c20; 1 drivers -v0x2aca6f0_0 .net "in1", 0 0, L_0x2c49cc0; 1 drivers -v0x2ac9780_0 .net "in2", 0 0, L_0x2c49d60; 1 drivers -v0x2ac9820_0 .net "in3", 0 0, L_0x2c49e50; 1 drivers -v0x2accdf0_0 .net "nS0", 0 0, L_0x2c49100; 1 drivers -v0x2accb50_0 .net "nS1", 0 0, L_0x2c491f0; 1 drivers -v0x2accbf0_0 .net "out", 0 0, L_0x2c4a5d0; 1 drivers -v0x2acbc80_0 .net "out0", 0 0, L_0x2c4a190; 1 drivers -v0x2acbd20_0 .net "out1", 0 0, L_0x2c4a280; 1 drivers -v0x2acf2d0_0 .net "out2", 0 0, L_0x2c4a370; 1 drivers -v0x2acf050_0 .net "out3", 0 0, L_0x2c4a460; 1 drivers -S_0x2ac39d0 .scope module, "OneMux" "FourInMux" 3 293, 3 24, S_0x2abb910; - .timescale -9 -12; -L_0x2c49f40/d .functor NOT 1, L_0x2c4a9b0, C4<0>, C4<0>, C4<0>; -L_0x2c49f40 .delay (10000,10000,10000) L_0x2c49f40/d; -L_0x2c49ff0/d .functor NOT 1, L_0x2c4aae0, C4<0>, C4<0>, C4<0>; -L_0x2c49ff0 .delay (10000,10000,10000) L_0x2c49ff0/d; -L_0x2c4a090/d .functor NAND 1, L_0x2c49f40, L_0x2c49ff0, L_0x2c4ac10, C4<1>; -L_0x2c4a090 .delay (10000,10000,10000) L_0x2c4a090/d; -L_0x2c4b0d0/d .functor NAND 1, L_0x2c4a9b0, L_0x2c49ff0, L_0x2c4acb0, C4<1>; -L_0x2c4b0d0 .delay (10000,10000,10000) L_0x2c4b0d0/d; -L_0x2c4b1c0/d .functor NAND 1, L_0x2c49f40, L_0x2c4aae0, L_0x2c4ad50, C4<1>; -L_0x2c4b1c0 .delay (10000,10000,10000) L_0x2c4b1c0/d; -L_0x2c4b2e0/d .functor NAND 1, L_0x2c4a9b0, L_0x2c4aae0, L_0x2c4ae40, C4<1>; -L_0x2c4b2e0 .delay (10000,10000,10000) L_0x2c4b2e0/d; -L_0x2c4b450/d .functor NAND 1, L_0x2c4a090, L_0x2c4b0d0, L_0x2c4b1c0, L_0x2c4b2e0; -L_0x2c4b450 .delay (10000,10000,10000) L_0x2c4b450/d; -v0x2ac03d0_0 .net "S0", 0 0, L_0x2c4a9b0; 1 drivers -v0x2ac3720_0 .net "S1", 0 0, L_0x2c4aae0; 1 drivers -v0x2ac37a0_0 .net "in0", 0 0, L_0x2c4ac10; 1 drivers -v0x2ac2840_0 .net "in1", 0 0, L_0x2c4acb0; 1 drivers -v0x2ac28e0_0 .net "in2", 0 0, L_0x2c4ad50; 1 drivers -v0x2ac5ed0_0 .net "in3", 0 0, L_0x2c4ae40; 1 drivers -v0x2ac5f70_0 .net "nS0", 0 0, L_0x2c49f40; 1 drivers -v0x2ac5c70_0 .net "nS1", 0 0, L_0x2c49ff0; 1 drivers -v0x2ac4d80_0 .net "out", 0 0, L_0x2c4b450; 1 drivers -v0x2ac4e20_0 .net "out0", 0 0, L_0x2c4a090; 1 drivers -v0x2ac83d0_0 .net "out1", 0 0, L_0x2c4b0d0; 1 drivers -v0x2ac8470_0 .net "out2", 0 0, L_0x2c4b1c0; 1 drivers -v0x2ac81e0_0 .net "out3", 0 0, L_0x2c4b2e0; 1 drivers -S_0x2abef90 .scope module, "TwoMux" "TwoInMux" 3 294, 3 8, S_0x2abb910; - .timescale -9 -12; -L_0x2ac5cf0/d .functor NOT 1, L_0x2c4c130, C4<0>, C4<0>, C4<0>; -L_0x2ac5cf0 .delay (10000,10000,10000) L_0x2ac5cf0/d; -L_0x2c4afc0/d .functor AND 1, L_0x2c4b700, L_0x2ac5cf0, C4<1>, C4<1>; -L_0x2c4afc0 .delay (20000,20000,20000) L_0x2c4afc0/d; -L_0x2c4be60/d .functor AND 1, L_0x2c4b7f0, L_0x2c4c130, C4<1>, C4<1>; -L_0x2c4be60 .delay (20000,20000,20000) L_0x2c4be60/d; -L_0x2c4bf50/d .functor OR 1, L_0x2c4afc0, L_0x2c4be60, C4<0>, C4<0>; -L_0x2c4bf50 .delay (20000,20000,20000) L_0x2c4bf50/d; -v0x2abed10_0 .net "S", 0 0, L_0x2c4c130; 1 drivers -v0x2abedb0_0 .net "in0", 0 0, L_0x2c4b700; 1 drivers -v0x2abde20_0 .net "in1", 0 0, L_0x2c4b7f0; 1 drivers -v0x2abdec0_0 .net "nS", 0 0, L_0x2ac5cf0; 1 drivers -v0x2ac14c0_0 .net "out0", 0 0, L_0x2c4afc0; 1 drivers -v0x2ac1220_0 .net "out1", 0 0, L_0x2c4be60; 1 drivers -v0x2ac0330_0 .net "outfinal", 0 0, L_0x2c4bf50; 1 drivers -S_0x2aa9fc0 .scope generate, "muxbits[12]" "muxbits[12]" 3 290, 3 290, S_0x29738d0; - .timescale -9 -12; -P_0x2a9dab8 .param/l "i" 3 290, +C4<01100>; -L_0x2c4e2d0/d .functor OR 1, L_0x2c4e410, L_0x2c4e4b0, C4<0>, C4<0>; -L_0x2c4e2d0 .delay (20000,20000,20000) L_0x2c4e2d0/d; -v0x2abcb20_0 .net *"_s15", 0 0, L_0x2c4e410; 1 drivers -v0x2abc800_0 .net *"_s16", 0 0, L_0x2c4e4b0; 1 drivers -S_0x2ab58d0 .scope module, "ZeroMux" "FourInMux" 3 292, 3 24, S_0x2aa9fc0; - .timescale -9 -12; -L_0x2c4bc50/d .functor NOT 1, L_0x2c4c1d0, C4<0>, C4<0>, C4<0>; -L_0x2c4bc50 .delay (10000,10000,10000) L_0x2c4bc50/d; -L_0x2c4bd40/d .functor NOT 1, L_0x2c4c300, C4<0>, C4<0>, C4<0>; -L_0x2c4bd40 .delay (10000,10000,10000) L_0x2c4bd40/d; -L_0x2c4c910/d .functor NAND 1, L_0x2c4bc50, L_0x2c4bd40, L_0x2c4c430, C4<1>; -L_0x2c4c910 .delay (10000,10000,10000) L_0x2c4c910/d; -L_0x2c4ca50/d .functor NAND 1, L_0x2c4c1d0, L_0x2c4bd40, L_0x2c4c4d0, C4<1>; -L_0x2c4ca50 .delay (10000,10000,10000) L_0x2c4ca50/d; -L_0x2c4cb40/d .functor NAND 1, L_0x2c4bc50, L_0x2c4c300, L_0x2c4c570, C4<1>; -L_0x2c4cb40 .delay (10000,10000,10000) L_0x2c4cb40/d; -L_0x2c4cc30/d .functor NAND 1, L_0x2c4c1d0, L_0x2c4c300, L_0x2c4c660, C4<1>; -L_0x2c4cc30 .delay (10000,10000,10000) L_0x2c4cc30/d; -L_0x2c4cd40/d .functor NAND 1, L_0x2c4c910, L_0x2c4ca50, L_0x2c4cb40, L_0x2c4cc30; -L_0x2c4cd40 .delay (10000,10000,10000) L_0x2c4cd40/d; -v0x2ab49e0_0 .net "S0", 0 0, L_0x2c4c1d0; 1 drivers -v0x2ab8060_0 .net "S1", 0 0, L_0x2c4c300; 1 drivers -v0x2ab8100_0 .net "in0", 0 0, L_0x2c4c430; 1 drivers -v0x2ab7de0_0 .net "in1", 0 0, L_0x2c4c4d0; 1 drivers -v0x2ab7e60_0 .net "in2", 0 0, L_0x2c4c570; 1 drivers -v0x2ab6ef0_0 .net "in3", 0 0, L_0x2c4c660; 1 drivers -v0x2ab6f90_0 .net "nS0", 0 0, L_0x2c4bc50; 1 drivers -v0x2aba570_0 .net "nS1", 0 0, L_0x2c4bd40; 1 drivers -v0x2aba610_0 .net "out", 0 0, L_0x2c4cd40; 1 drivers -v0x2aba2f0_0 .net "out0", 0 0, L_0x2c4c910; 1 drivers -v0x2aba370_0 .net "out1", 0 0, L_0x2c4ca50; 1 drivers -v0x2ab9400_0 .net "out2", 0 0, L_0x2c4cb40; 1 drivers -v0x2abca80_0 .net "out3", 0 0, L_0x2c4cc30; 1 drivers -S_0x2aae9c0 .scope module, "OneMux" "FourInMux" 3 293, 3 24, S_0x2aa9fc0; - .timescale -9 -12; -L_0x2c4c750/d .functor NOT 1, L_0x2c4de80, C4<0>, C4<0>, C4<0>; -L_0x2c4c750 .delay (10000,10000,10000) L_0x2c4c750/d; -L_0x2c4c840/d .functor NOT 1, L_0x2c4cff0, C4<0>, C4<0>, C4<0>; -L_0x2c4c840 .delay (10000,10000,10000) L_0x2c4c840/d; -L_0x2c4d770/d .functor NAND 1, L_0x2c4c750, L_0x2c4c840, L_0x2c4d120, C4<1>; -L_0x2c4d770 .delay (10000,10000,10000) L_0x2c4d770/d; -L_0x2c4d8b0/d .functor NAND 1, L_0x2c4de80, L_0x2c4c840, L_0x2c4d1c0, C4<1>; -L_0x2c4d8b0 .delay (10000,10000,10000) L_0x2c4d8b0/d; -L_0x2c4d9a0/d .functor NAND 1, L_0x2c4c750, L_0x2c4cff0, L_0x2c4d260, C4<1>; -L_0x2c4d9a0 .delay (10000,10000,10000) L_0x2c4d9a0/d; -L_0x2c4da90/d .functor NAND 1, L_0x2c4de80, L_0x2c4cff0, L_0x2c4d350, C4<1>; -L_0x2c4da90 .delay (10000,10000,10000) L_0x2c4da90/d; -L_0x2c4dbd0/d .functor NAND 1, L_0x2c4d770, L_0x2c4d8b0, L_0x2c4d9a0, L_0x2c4da90; -L_0x2c4dbd0 .delay (10000,10000,10000) L_0x2c4dbd0/d; -v0x2aadaf0_0 .net "S0", 0 0, L_0x2c4de80; 1 drivers -v0x2aadb90_0 .net "S1", 0 0, L_0x2c4cff0; 1 drivers -v0x2ab1140_0 .net "in0", 0 0, L_0x2c4d120; 1 drivers -v0x2ab11e0_0 .net "in1", 0 0, L_0x2c4d1c0; 1 drivers -v0x2ab0ec0_0 .net "in2", 0 0, L_0x2c4d260; 1 drivers -v0x2ab0f60_0 .net "in3", 0 0, L_0x2c4d350; 1 drivers -v0x2ab0050_0 .net "nS0", 0 0, L_0x2c4c750; 1 drivers -v0x2ab3640_0 .net "nS1", 0 0, L_0x2c4c840; 1 drivers -v0x2ab36c0_0 .net "out", 0 0, L_0x2c4dbd0; 1 drivers -v0x2ab33c0_0 .net "out0", 0 0, L_0x2c4d770; 1 drivers -v0x2ab3460_0 .net "out1", 0 0, L_0x2c4d8b0; 1 drivers -v0x2ab2510_0 .net "out2", 0 0, L_0x2c4d9a0; 1 drivers -v0x2ab5b70_0 .net "out3", 0 0, L_0x2c4da90; 1 drivers -S_0x2aa90f0 .scope module, "TwoMux" "TwoInMux" 3 294, 3 8, S_0x2aa9fc0; - .timescale -9 -12; -L_0x2c4d440/d .functor NOT 1, L_0x2c4dfb0, C4<0>, C4<0>, C4<0>; -L_0x2c4d440 .delay (10000,10000,10000) L_0x2c4d440/d; -L_0x2c4d4f0/d .functor AND 1, L_0x2c4e050, L_0x2c4d440, C4<1>, C4<1>; -L_0x2c4d4f0 .delay (20000,20000,20000) L_0x2c4d4f0/d; -L_0x2c4d5e0/d .functor AND 1, L_0x2c4e140, L_0x2c4dfb0, C4<1>, C4<1>; -L_0x2c4d5e0 .delay (20000,20000,20000) L_0x2c4d5e0/d; -L_0x2c4d6d0/d .functor OR 1, L_0x2c4d4f0, L_0x2c4d5e0, C4<0>, C4<0>; -L_0x2c4d6d0 .delay (20000,20000,20000) L_0x2c4d6d0/d; -v0x2aac740_0 .net "S", 0 0, L_0x2c4dfb0; 1 drivers -v0x2aac7e0_0 .net "in0", 0 0, L_0x2c4e050; 1 drivers -v0x2aac4c0_0 .net "in1", 0 0, L_0x2c4e140; 1 drivers -v0x2aac560_0 .net "nS", 0 0, L_0x2c4d440; 1 drivers -v0x2aab5f0_0 .net "out0", 0 0, L_0x2c4d4f0; 1 drivers -v0x2aab690_0 .net "out1", 0 0, L_0x2c4d5e0; 1 drivers -v0x2aaeca0_0 .net "outfinal", 0 0, L_0x2c4d6d0; 1 drivers -S_0x2a9c690 .scope generate, "muxbits[13]" "muxbits[13]" 3 290, 3 290, S_0x29738d0; - .timescale -9 -12; -P_0x2a959d8 .param/l "i" 3 290, +C4<01101>; -L_0x2c508b0/d .functor OR 1, L_0x2c509f0, L_0x2c50a90, C4<0>, C4<0>; -L_0x2c508b0 .delay (20000,20000,20000) L_0x2c508b0/d; -v0x2aa6c60_0 .net *"_s15", 0 0, L_0x2c509f0; 1 drivers -v0x2aaa260_0 .net *"_s16", 0 0, L_0x2c50a90; 1 drivers -S_0x2aed420 .scope module, "ZeroMux" "FourInMux" 3 292, 3 24, S_0x2a9c690; - .timescale -9 -12; -L_0x2c4e5a0/d .functor NOT 1, L_0x2c4f7a0, C4<0>, C4<0>, C4<0>; -L_0x2c4e5a0 .delay (10000,10000,10000) L_0x2c4e5a0/d; -L_0x2c4e690/d .functor NOT 1, L_0x2c4e8a0, C4<0>, C4<0>, C4<0>; -L_0x2c4e690 .delay (10000,10000,10000) L_0x2c4e690/d; -L_0x2c4f090/d .functor NAND 1, L_0x2c4e5a0, L_0x2c4e690, L_0x2c4e9d0, C4<1>; -L_0x2c4f090 .delay (10000,10000,10000) L_0x2c4f090/d; -L_0x2c4f1d0/d .functor NAND 1, L_0x2c4f7a0, L_0x2c4e690, L_0x2c4ea70, C4<1>; -L_0x2c4f1d0 .delay (10000,10000,10000) L_0x2c4f1d0/d; -L_0x2c4f2c0/d .functor NAND 1, L_0x2c4e5a0, L_0x2c4e8a0, L_0x2c4eb10, C4<1>; -L_0x2c4f2c0 .delay (10000,10000,10000) L_0x2c4f2c0/d; -L_0x2c4f3b0/d .functor NAND 1, L_0x2c4f7a0, L_0x2c4e8a0, L_0x2c4ec00, C4<1>; -L_0x2c4f3b0 .delay (10000,10000,10000) L_0x2c4f3b0/d; -L_0x2c4f4f0/d .functor NAND 1, L_0x2c4f090, L_0x2c4f1d0, L_0x2c4f2c0, L_0x2c4f3b0; -L_0x2c4f4f0 .delay (10000,10000,10000) L_0x2c4f4f0/d; -v0x2aed1b0_0 .net "S0", 0 0, L_0x2c4f7a0; 1 drivers -v0x2aed250_0 .net "S1", 0 0, L_0x2c4e8a0; 1 drivers -v0x2aec2f0_0 .net "in0", 0 0, L_0x2c4e9d0; 1 drivers -v0x2aec390_0 .net "in1", 0 0, L_0x2c4ea70; 1 drivers -v0x2aa57d0_0 .net "in2", 0 0, L_0x2c4eb10; 1 drivers -v0x2aa5870_0 .net "in3", 0 0, L_0x2c4ec00; 1 drivers -v0x2aa5510_0 .net "nS0", 0 0, L_0x2c4e5a0; 1 drivers -v0x2aa4640_0 .net "nS1", 0 0, L_0x2c4e690; 1 drivers -v0x2aa46e0_0 .net "out", 0 0, L_0x2c4f4f0; 1 drivers -v0x2aa7d40_0 .net "out0", 0 0, L_0x2c4f090; 1 drivers -v0x2aa7de0_0 .net "out1", 0 0, L_0x2c4f1d0; 1 drivers -v0x2aa7ac0_0 .net "out2", 0 0, L_0x2c4f2c0; 1 drivers -v0x2aa6bc0_0 .net "out3", 0 0, L_0x2c4f3b0; 1 drivers -S_0x2a9ef90 .scope module, "OneMux" "FourInMux" 3 293, 3 24, S_0x2a9c690; - .timescale -9 -12; -L_0x2c4ecf0/d .functor NOT 1, L_0x2c4f8d0, C4<0>, C4<0>, C4<0>; -L_0x2c4ecf0 .delay (10000,10000,10000) L_0x2c4ecf0/d; -L_0x2c4eda0/d .functor NOT 1, L_0x2c4fa00, C4<0>, C4<0>, C4<0>; -L_0x2c4eda0 .delay (10000,10000,10000) L_0x2c4eda0/d; -L_0x2c4ee40/d .functor NAND 1, L_0x2c4ecf0, L_0x2c4eda0, L_0x2c4fb30, C4<1>; -L_0x2c4ee40 .delay (10000,10000,10000) L_0x2c4ee40/d; -L_0x2c4ef80/d .functor NAND 1, L_0x2c4f8d0, L_0x2c4eda0, L_0x2c4fbd0, C4<1>; -L_0x2c4ef80 .delay (10000,10000,10000) L_0x2c4ef80/d; -L_0x2c500f0/d .functor NAND 1, L_0x2c4ecf0, L_0x2c4fa00, L_0x2c4fc70, C4<1>; -L_0x2c500f0 .delay (10000,10000,10000) L_0x2c500f0/d; -L_0x2c50210/d .functor NAND 1, L_0x2c4f8d0, L_0x2c4fa00, L_0x2c4fd60, C4<1>; -L_0x2c50210 .delay (10000,10000,10000) L_0x2c50210/d; -L_0x2c50380/d .functor NAND 1, L_0x2c4ee40, L_0x2c4ef80, L_0x2c500f0, L_0x2c50210; -L_0x2c50380 .delay (10000,10000,10000) L_0x2c50380/d; -v0x2a9f2b0_0 .net "S0", 0 0, L_0x2c4f8d0; 1 drivers -v0x2a9ea90_0 .net "S1", 0 0, L_0x2c4fa00; 1 drivers -v0x2a9eb10_0 .net "in0", 0 0, L_0x2c4fb30; 1 drivers -v0x2aa07d0_0 .net "in1", 0 0, L_0x2c4fbd0; 1 drivers -v0x2aa0870_0 .net "in2", 0 0, L_0x2c4fc70; 1 drivers -v0x2aa0550_0 .net "in3", 0 0, L_0x2c4fd60; 1 drivers -v0x2aa05f0_0 .net "nS0", 0 0, L_0x2c4ecf0; 1 drivers -v0x2aa0070_0 .net "nS1", 0 0, L_0x2c4eda0; 1 drivers -v0x2aa1d90_0 .net "out", 0 0, L_0x2c50380; 1 drivers -v0x2aa1e30_0 .net "out0", 0 0, L_0x2c4ee40; 1 drivers -v0x2aa1b10_0 .net "out1", 0 0, L_0x2c4ef80; 1 drivers -v0x2aa1bb0_0 .net "out2", 0 0, L_0x2c500f0; 1 drivers -v0x2aa16a0_0 .net "out3", 0 0, L_0x2c50210; 1 drivers -S_0x2a9c410 .scope module, "TwoMux" "TwoInMux" 3 294, 3 8, S_0x2a9c690; - .timescale -9 -12; -L_0x2aa00f0/d .functor NOT 1, L_0x2c51070, C4<0>, C4<0>, C4<0>; -L_0x2aa00f0 .delay (10000,10000,10000) L_0x2aa00f0/d; -L_0x2c4fee0/d .functor AND 1, L_0x2c50630, L_0x2aa00f0, C4<1>, C4<1>; -L_0x2c4fee0 .delay (20000,20000,20000) L_0x2c4fee0/d; -L_0x2c4ffd0/d .functor AND 1, L_0x2c50720, L_0x2c51070, C4<1>, C4<1>; -L_0x2c4ffd0 .delay (20000,20000,20000) L_0x2c4ffd0/d; -L_0x2c50e90/d .functor OR 1, L_0x2c4fee0, L_0x2c4ffd0, C4<0>, C4<0>; -L_0x2c50e90 .delay (20000,20000,20000) L_0x2c50e90/d; -v0x2a9bf10_0 .net "S", 0 0, L_0x2c51070; 1 drivers -v0x2a9bfb0_0 .net "in0", 0 0, L_0x2c50630; 1 drivers -v0x2a9dc50_0 .net "in1", 0 0, L_0x2c50720; 1 drivers -v0x2a9dcf0_0 .net "nS", 0 0, L_0x2aa00f0; 1 drivers -v0x2a9d9f0_0 .net "out0", 0 0, L_0x2c4fee0; 1 drivers -v0x2a9d4d0_0 .net "out1", 0 0, L_0x2c4ffd0; 1 drivers -v0x2a9f210_0 .net "outfinal", 0 0, L_0x2c50e90; 1 drivers -S_0x2a8ea90 .scope generate, "muxbits[14]" "muxbits[14]" 3 290, 3 290, S_0x29738d0; - .timescale -9 -12; -P_0x2a81298 .param/l "i" 3 290, +C4<01110>; -L_0x2c53020/d .functor OR 1, L_0x2c53160, L_0x2c53200, C4<0>, C4<0>; -L_0x2c53020 .delay (20000,20000,20000) L_0x2c53020/d; -v0x2a9aef0_0 .net *"_s15", 0 0, L_0x2c53160; 1 drivers -v0x2a9a950_0 .net *"_s16", 0 0, L_0x2c53200; 1 drivers -S_0x2a96810 .scope module, "ZeroMux" "FourInMux" 3 292, 3 24, S_0x2a8ea90; - .timescale -9 -12; -L_0x2c50b80/d .functor NOT 1, L_0x2c51110, C4<0>, C4<0>, C4<0>; -L_0x2c50b80 .delay (10000,10000,10000) L_0x2c50b80/d; -L_0x2c50c70/d .functor NOT 1, L_0x2c51240, C4<0>, C4<0>, C4<0>; -L_0x2c50c70 .delay (10000,10000,10000) L_0x2c50c70/d; -L_0x2c50d10/d .functor NAND 1, L_0x2c50b80, L_0x2c50c70, L_0x2c51370, C4<1>; -L_0x2c50d10 .delay (10000,10000,10000) L_0x2c50d10/d; -L_0x2c519a0/d .functor NAND 1, L_0x2c51110, L_0x2c50c70, L_0x2c51410, C4<1>; -L_0x2c519a0 .delay (10000,10000,10000) L_0x2c519a0/d; -L_0x2c51a50/d .functor NAND 1, L_0x2c50b80, L_0x2c51240, L_0x2c514b0, C4<1>; -L_0x2c51a50 .delay (10000,10000,10000) L_0x2c51a50/d; -L_0x2c51b40/d .functor NAND 1, L_0x2c51110, L_0x2c51240, L_0x2c515a0, C4<1>; -L_0x2c51b40 .delay (10000,10000,10000) L_0x2c51b40/d; -L_0x2c51c20/d .functor NAND 1, L_0x2c50d10, L_0x2c519a0, L_0x2c51a50, L_0x2c51b40; -L_0x2c51c20 .delay (10000,10000,10000) L_0x2c51c20/d; -v0x2a98550_0 .net "S0", 0 0, L_0x2c51110; 1 drivers -v0x2a982d0_0 .net "S1", 0 0, L_0x2c51240; 1 drivers -v0x2a98370_0 .net "in0", 0 0, L_0x2c51370; 1 drivers -v0x2a97dd0_0 .net "in1", 0 0, L_0x2c51410; 1 drivers -v0x2a97e50_0 .net "in2", 0 0, L_0x2c514b0; 1 drivers -v0x2a99b10_0 .net "in3", 0 0, L_0x2c515a0; 1 drivers -v0x2a99bb0_0 .net "nS0", 0 0, L_0x2c50b80; 1 drivers -v0x2a99890_0 .net "nS1", 0 0, L_0x2c50c70; 1 drivers -v0x2a99930_0 .net "out", 0 0, L_0x2c51c20; 1 drivers -v0x2a99390_0 .net "out0", 0 0, L_0x2c50d10; 1 drivers -v0x2a99410_0 .net "out1", 0 0, L_0x2c519a0; 1 drivers -v0x2a9b0d0_0 .net "out2", 0 0, L_0x2c51a50; 1 drivers -v0x2a9ae50_0 .net "out3", 0 0, L_0x2c51b40; 1 drivers -S_0x2a92bb0 .scope module, "OneMux" "FourInMux" 3 293, 3 24, S_0x2a8ea90; - .timescale -9 -12; -L_0x2c51690/d .functor NOT 1, L_0x2c52d60, C4<0>, C4<0>, C4<0>; -L_0x2c51690 .delay (10000,10000,10000) L_0x2c51690/d; -L_0x2c51780/d .functor NOT 1, L_0x2c51ed0, C4<0>, C4<0>, C4<0>; -L_0x2c51780 .delay (10000,10000,10000) L_0x2c51780/d; -L_0x2c51820/d .functor NAND 1, L_0x2c51690, L_0x2c51780, L_0x2c52000, C4<1>; -L_0x2c51820 .delay (10000,10000,10000) L_0x2c51820/d; -L_0x2c527a0/d .functor NAND 1, L_0x2c52d60, L_0x2c51780, L_0x2c520a0, C4<1>; -L_0x2c527a0 .delay (10000,10000,10000) L_0x2c527a0/d; -L_0x2c52850/d .functor NAND 1, L_0x2c51690, L_0x2c51ed0, L_0x2c52140, C4<1>; -L_0x2c52850 .delay (10000,10000,10000) L_0x2c52850/d; -L_0x2c52940/d .functor NAND 1, L_0x2c52d60, L_0x2c51ed0, L_0x2c52230, C4<1>; -L_0x2c52940 .delay (10000,10000,10000) L_0x2c52940/d; -L_0x2c52ab0/d .functor NAND 1, L_0x2c51820, L_0x2c527a0, L_0x2c52850, L_0x2c52940; -L_0x2c52ab0 .delay (10000,10000,10000) L_0x2c52ab0/d; -v0x2a94410_0 .net "S0", 0 0, L_0x2c52d60; 1 drivers -v0x2a944b0_0 .net "S1", 0 0, L_0x2c51ed0; 1 drivers -v0x2a94190_0 .net "in0", 0 0, L_0x2c52000; 1 drivers -v0x2a94230_0 .net "in1", 0 0, L_0x2c520a0; 1 drivers -v0x2a93c90_0 .net "in2", 0 0, L_0x2c52140; 1 drivers -v0x2a93d30_0 .net "in3", 0 0, L_0x2c52230; 1 drivers -v0x2a95a30_0 .net "nS0", 0 0, L_0x2c51690; 1 drivers -v0x2a95750_0 .net "nS1", 0 0, L_0x2c51780; 1 drivers -v0x2a957d0_0 .net "out", 0 0, L_0x2c52ab0; 1 drivers -v0x2a95250_0 .net "out0", 0 0, L_0x2c51820; 1 drivers -v0x2a952f0_0 .net "out1", 0 0, L_0x2c527a0; 1 drivers -v0x2a96fb0_0 .net "out2", 0 0, L_0x2c52850; 1 drivers -v0x2a96d30_0 .net "out3", 0 0, L_0x2c52940; 1 drivers -S_0x2a902d0 .scope module, "TwoMux" "TwoInMux" 3 294, 3 8, S_0x2a8ea90; - .timescale -9 -12; -L_0x2c52320/d .functor NOT 1, L_0x2c537a0, C4<0>, C4<0>, C4<0>; -L_0x2c52320 .delay (10000,10000,10000) L_0x2c52320/d; -L_0x2c523d0/d .functor AND 1, L_0x2c53840, L_0x2c52320, C4<1>, C4<1>; -L_0x2c523d0 .delay (20000,20000,20000) L_0x2c523d0/d; -L_0x2c524c0/d .functor AND 1, L_0x2c52e90, L_0x2c537a0, C4<1>, C4<1>; -L_0x2c524c0 .delay (20000,20000,20000) L_0x2c524c0/d; -L_0x2c525b0/d .functor OR 1, L_0x2c523d0, L_0x2c524c0, C4<0>, C4<0>; -L_0x2c525b0 .delay (20000,20000,20000) L_0x2c525b0/d; -v0x2a90030_0 .net "S", 0 0, L_0x2c537a0; 1 drivers -v0x2a900d0_0 .net "in0", 0 0, L_0x2c53840; 1 drivers -v0x2a91890_0 .net "in1", 0 0, L_0x2c52e90; 1 drivers -v0x2a91930_0 .net "nS", 0 0, L_0x2c52320; 1 drivers -v0x2a91610_0 .net "out0", 0 0, L_0x2c523d0; 1 drivers -v0x2a916b0_0 .net "out1", 0 0, L_0x2c524c0; 1 drivers -v0x2a92eb0_0 .net "outfinal", 0 0, L_0x2c525b0; 1 drivers -S_0x2a7fe70 .scope generate, "muxbits[15]" "muxbits[15]" 3 290, 3 290, S_0x29738d0; - .timescale -9 -12; -P_0x2aa3338 .param/l "i" 3 290, +C4<01111>; -L_0x2c55070/d .functor OR 1, L_0x2c555d0, L_0x2c55670, C4<0>, C4<0>; -L_0x2c55070 .delay (20000,20000,20000) L_0x2c55070/d; -v0x2a8d550_0 .net *"_s15", 0 0, L_0x2c555d0; 1 drivers -v0x2a8ed30_0 .net *"_s16", 0 0, L_0x2c55670; 1 drivers -S_0x2a87db0 .scope module, "ZeroMux" "FourInMux" 3 292, 3 24, S_0x2a7fe70; - .timescale -9 -12; -L_0x2c532f0/d .functor NOT 1, L_0x2c54660, C4<0>, C4<0>, C4<0>; -L_0x2c532f0 .delay (10000,10000,10000) L_0x2c532f0/d; -L_0x2c533e0/d .functor NOT 1, L_0x2c53930, C4<0>, C4<0>, C4<0>; -L_0x2c533e0 .delay (10000,10000,10000) L_0x2c533e0/d; -L_0x2c53480/d .functor NAND 1, L_0x2c532f0, L_0x2c533e0, L_0x2c53a60, C4<1>; -L_0x2c53480 .delay (10000,10000,10000) L_0x2c53480/d; -L_0x2c535c0/d .functor NAND 1, L_0x2c54660, L_0x2c533e0, L_0x2c53b00, C4<1>; -L_0x2c535c0 .delay (10000,10000,10000) L_0x2c535c0/d; -L_0x2c536b0/d .functor NAND 1, L_0x2c532f0, L_0x2c53930, L_0x2c53ba0, C4<1>; -L_0x2c536b0 .delay (10000,10000,10000) L_0x2c536b0/d; -L_0x2c54270/d .functor NAND 1, L_0x2c54660, L_0x2c53930, L_0x2c53c90, C4<1>; -L_0x2c54270 .delay (10000,10000,10000) L_0x2c54270/d; -L_0x2c543b0/d .functor NAND 1, L_0x2c53480, L_0x2c535c0, L_0x2c536b0, L_0x2c54270; -L_0x2c543b0 .delay (10000,10000,10000) L_0x2c543b0/d; -v0x2a89610_0 .net "S0", 0 0, L_0x2c54660; 1 drivers -v0x2a896b0_0 .net "S1", 0 0, L_0x2c53930; 1 drivers -v0x2a89390_0 .net "in0", 0 0, L_0x2c53a60; 1 drivers -v0x2a89430_0 .net "in1", 0 0, L_0x2c53b00; 1 drivers -v0x2a8abd0_0 .net "in2", 0 0, L_0x2c53ba0; 1 drivers -v0x2a8ac70_0 .net "in3", 0 0, L_0x2c53c90; 1 drivers -v0x2a8a950_0 .net "nS0", 0 0, L_0x2c532f0; 1 drivers -v0x2a8c190_0 .net "nS1", 0 0, L_0x2c533e0; 1 drivers -v0x2a8c230_0 .net "out", 0 0, L_0x2c543b0; 1 drivers -v0x2a8bf10_0 .net "out0", 0 0, L_0x2c53480; 1 drivers -v0x2a8bfb0_0 .net "out1", 0 0, L_0x2c535c0; 1 drivers -v0x2a8d750_0 .net "out2", 0 0, L_0x2c536b0; 1 drivers -v0x2a8d4b0_0 .net "out3", 0 0, L_0x2c54270; 1 drivers -S_0x2a826d0 .scope module, "OneMux" "FourInMux" 3 293, 3 24, S_0x2a7fe70; - .timescale -9 -12; -L_0x2c53d80/d .functor NOT 1, L_0x2c54790, C4<0>, C4<0>, C4<0>; -L_0x2c53d80 .delay (10000,10000,10000) L_0x2c53d80/d; -L_0x2c53e30/d .functor NOT 1, L_0x2c548c0, C4<0>, C4<0>, C4<0>; -L_0x2c53e30 .delay (10000,10000,10000) L_0x2c53e30/d; -L_0x2c53ed0/d .functor NAND 1, L_0x2c53d80, L_0x2c53e30, L_0x2c549f0, C4<1>; -L_0x2c53ed0 .delay (10000,10000,10000) L_0x2c53ed0/d; -L_0x2c54010/d .functor NAND 1, L_0x2c54790, L_0x2c53e30, L_0x2c082f0, C4<1>; -L_0x2c54010 .delay (10000,10000,10000) L_0x2c54010/d; -L_0x2c54100/d .functor NAND 1, L_0x2c53d80, L_0x2c548c0, L_0x2c08390, C4<1>; -L_0x2c54100 .delay (10000,10000,10000) L_0x2c54100/d; -L_0x2c55100/d .functor NAND 1, L_0x2c54790, L_0x2c548c0, L_0x2c08480, C4<1>; -L_0x2c55100 .delay (10000,10000,10000) L_0x2c55100/d; -L_0x2c55240/d .functor NAND 1, L_0x2c53ed0, L_0x2c54010, L_0x2c54100, L_0x2c55100; -L_0x2c55240 .delay (10000,10000,10000) L_0x2c55240/d; -v0x2a829f0_0 .net "S0", 0 0, L_0x2c54790; 1 drivers -v0x2a83f10_0 .net "S1", 0 0, L_0x2c548c0; 1 drivers -v0x2a83f90_0 .net "in0", 0 0, L_0x2c549f0; 1 drivers -v0x2a83c90_0 .net "in1", 0 0, L_0x2c082f0; 1 drivers -v0x2a83d30_0 .net "in2", 0 0, L_0x2c08390; 1 drivers -v0x2a854d0_0 .net "in3", 0 0, L_0x2c08480; 1 drivers -v0x2a85570_0 .net "nS0", 0 0, L_0x2c53d80; 1 drivers -v0x2a85250_0 .net "nS1", 0 0, L_0x2c53e30; 1 drivers -v0x2a86a90_0 .net "out", 0 0, L_0x2c55240; 1 drivers -v0x2a86b30_0 .net "out0", 0 0, L_0x2c53ed0; 1 drivers -v0x2a86810_0 .net "out1", 0 0, L_0x2c54010; 1 drivers -v0x2a868b0_0 .net "out2", 0 0, L_0x2c54100; 1 drivers -v0x2a880e0_0 .net "out3", 0 0, L_0x2c55100; 1 drivers -S_0x2a7fbf0 .scope module, "TwoMux" "TwoInMux" 3 294, 3 8, S_0x2a7fe70; - .timescale -9 -12; -L_0x2a852d0/d .functor NOT 1, L_0x2c54d50, C4<0>, C4<0>, C4<0>; -L_0x2a852d0 .delay (10000,10000,10000) L_0x2a852d0/d; -L_0x2c08600/d .functor AND 1, L_0x2c54df0, L_0x2a852d0, C4<1>, C4<1>; -L_0x2c08600 .delay (20000,20000,20000) L_0x2c08600/d; -L_0x2c086a0/d .functor AND 1, L_0x2c54ee0, L_0x2c54d50, C4<1>, C4<1>; -L_0x2c086a0 .delay (20000,20000,20000) L_0x2c086a0/d; -L_0x2c54b70/d .functor OR 1, L_0x2c08600, L_0x2c086a0, C4<0>, C4<0>; -L_0x2c54b70 .delay (20000,20000,20000) L_0x2c54b70/d; -v0x2a7f6f0_0 .net "S", 0 0, L_0x2c54d50; 1 drivers -v0x2a7f790_0 .net "in0", 0 0, L_0x2c54df0; 1 drivers -v0x2a81430_0 .net "in1", 0 0, L_0x2c54ee0; 1 drivers -v0x2a814d0_0 .net "nS", 0 0, L_0x2a852d0; 1 drivers -v0x2a811d0_0 .net "out0", 0 0, L_0x2c08600; 1 drivers -v0x2a80cb0_0 .net "out1", 0 0, L_0x2c086a0; 1 drivers -v0x2a82950_0 .net "outfinal", 0 0, L_0x2c54b70; 1 drivers -S_0x2a6c960 .scope generate, "muxbits[16]" "muxbits[16]" 3 290, 3 290, S_0x29738d0; - .timescale -9 -12; -P_0x2a569f8 .param/l "i" 3 290, +C4<010000>; -L_0x2c44580/d .functor OR 1, L_0x2c446c0, L_0x2c589a0, C4<0>, C4<0>; -L_0x2c44580 .delay (20000,20000,20000) L_0x2c44580/d; -v0x2a7e6d0_0 .net *"_s15", 0 0, L_0x2c446c0; 1 drivers -v0x2a7e130_0 .net *"_s16", 0 0, L_0x2c589a0; 1 drivers -S_0x2a7a4f0 .scope module, "ZeroMux" "FourInMux" 3 292, 3 24, S_0x2a6c960; - .timescale -9 -12; -L_0x2c55760/d .functor NOT 1, L_0x2c56690, C4<0>, C4<0>, C4<0>; -L_0x2c55760 .delay (10000,10000,10000) L_0x2c55760/d; -L_0x2c55850/d .functor NOT 1, L_0x2c567c0, C4<0>, C4<0>, C4<0>; -L_0x2c55850 .delay (10000,10000,10000) L_0x2c55850/d; -L_0x2c558f0/d .functor NAND 1, L_0x2c55760, L_0x2c55850, L_0x2c568f0, C4<1>; -L_0x2c558f0 .delay (10000,10000,10000) L_0x2c558f0/d; -L_0x2c55a30/d .functor NAND 1, L_0x2c56690, L_0x2c55850, L_0x2c56990, C4<1>; -L_0x2c55a30 .delay (10000,10000,10000) L_0x2c55a30/d; -L_0x2c55b20/d .functor NAND 1, L_0x2c55760, L_0x2c567c0, L_0x2c56a30, C4<1>; -L_0x2c55b20 .delay (10000,10000,10000) L_0x2c55b20/d; -L_0x2c55c10/d .functor NAND 1, L_0x2c56690, L_0x2c567c0, L_0x2c56b20, C4<1>; -L_0x2c55c10 .delay (10000,10000,10000) L_0x2c55c10/d; -L_0x2c55d20/d .functor NAND 1, L_0x2c558f0, L_0x2c55a30, L_0x2c55b20, L_0x2c55c10; -L_0x2c55d20 .delay (10000,10000,10000) L_0x2c55d20/d; -v0x2a7bd30_0 .net "S0", 0 0, L_0x2c56690; 1 drivers -v0x2a7bab0_0 .net "S1", 0 0, L_0x2c567c0; 1 drivers -v0x2a7bb50_0 .net "in0", 0 0, L_0x2c568f0; 1 drivers -v0x2a7b5b0_0 .net "in1", 0 0, L_0x2c56990; 1 drivers -v0x2a7b630_0 .net "in2", 0 0, L_0x2c56a30; 1 drivers -v0x2a7d2f0_0 .net "in3", 0 0, L_0x2c56b20; 1 drivers -v0x2a7d390_0 .net "nS0", 0 0, L_0x2c55760; 1 drivers -v0x2a7d070_0 .net "nS1", 0 0, L_0x2c55850; 1 drivers -v0x2a7d110_0 .net "out", 0 0, L_0x2c55d20; 1 drivers -v0x2a7cb70_0 .net "out0", 0 0, L_0x2c558f0; 1 drivers -v0x2a7cbf0_0 .net "out1", 0 0, L_0x2c55a30; 1 drivers -v0x2a7e8b0_0 .net "out2", 0 0, L_0x2c55b20; 1 drivers -v0x2a7e630_0 .net "out3", 0 0, L_0x2c55c10; 1 drivers -S_0x2a6d870 .scope module, "OneMux" "FourInMux" 3 293, 3 24, S_0x2a6c960; - .timescale -9 -12; -L_0x2c56c10/d .functor NOT 1, L_0x2c58050, C4<0>, C4<0>, C4<0>; -L_0x2c56c10 .delay (10000,10000,10000) L_0x2c56c10/d; -L_0x2c56d00/d .functor NOT 1, L_0x2c571f0, C4<0>, C4<0>, C4<0>; -L_0x2c56d00 .delay (10000,10000,10000) L_0x2c56d00/d; -L_0x2c56da0/d .functor NAND 1, L_0x2c56c10, L_0x2c56d00, L_0x2c57320, C4<1>; -L_0x2c56da0 .delay (10000,10000,10000) L_0x2c56da0/d; -L_0x2c56ee0/d .functor NAND 1, L_0x2c58050, L_0x2c56d00, L_0x2c573c0, C4<1>; -L_0x2c56ee0 .delay (10000,10000,10000) L_0x2c56ee0/d; -L_0x2c56fd0/d .functor NAND 1, L_0x2c56c10, L_0x2c571f0, L_0x2c57460, C4<1>; -L_0x2c56fd0 .delay (10000,10000,10000) L_0x2c56fd0/d; -L_0x2c57c60/d .functor NAND 1, L_0x2c58050, L_0x2c571f0, L_0x2c57550, C4<1>; -L_0x2c57c60 .delay (10000,10000,10000) L_0x2c57c60/d; -L_0x2c57da0/d .functor NAND 1, L_0x2c56da0, L_0x2c56ee0, L_0x2c56fd0, L_0x2c57c60; -L_0x2c57da0 .delay (10000,10000,10000) L_0x2c57da0/d; -v0x2a72560_0 .net "S0", 0 0, L_0x2c58050; 1 drivers -v0x2a72600_0 .net "S1", 0 0, L_0x2c571f0; 1 drivers -v0x2a722b0_0 .net "in0", 0 0, L_0x2c57320; 1 drivers -v0x2a72350_0 .net "in1", 0 0, L_0x2c573c0; 1 drivers -v0x2a70670_0 .net "in2", 0 0, L_0x2c57460; 1 drivers -v0x2a70710_0 .net "in3", 0 0, L_0x2c57550; 1 drivers -v0x2aa3390_0 .net "nS0", 0 0, L_0x2c56c10; 1 drivers -v0x2aa30c0_0 .net "nS1", 0 0, L_0x2c56d00; 1 drivers -v0x2aa3140_0 .net "out", 0 0, L_0x2c57da0; 1 drivers -v0x2aa2bd0_0 .net "out0", 0 0, L_0x2c56da0; 1 drivers -v0x2aa2c70_0 .net "out1", 0 0, L_0x2c56ee0; 1 drivers -v0x2a78ea0_0 .net "out2", 0 0, L_0x2c56fd0; 1 drivers -v0x2a7a790_0 .net "out3", 0 0, L_0x2c57c60; 1 drivers -S_0x2a6c6b0 .scope module, "TwoMux" "TwoInMux" 3 294, 3 8, S_0x2a6c960; - .timescale -9 -12; -L_0x2c57640/d .functor NOT 1, L_0x2c57ab0, C4<0>, C4<0>, C4<0>; -L_0x2c57640 .delay (10000,10000,10000) L_0x2c57640/d; -L_0x2c576f0/d .functor AND 1, L_0x2c57b50, L_0x2c57640, C4<1>, C4<1>; -L_0x2c576f0 .delay (20000,20000,20000) L_0x2c576f0/d; -L_0x2c577e0/d .functor AND 1, L_0x2c43e90, L_0x2c57ab0, C4<1>, C4<1>; -L_0x2c577e0 .delay (20000,20000,20000) L_0x2c577e0/d; -L_0x2c578d0/d .functor OR 1, L_0x2c576f0, L_0x2c577e0, C4<0>, C4<0>; -L_0x2c578d0 .delay (20000,20000,20000) L_0x2c578d0/d; -v0x2a6aa70_0 .net "S", 0 0, L_0x2c57ab0; 1 drivers -v0x2a6ab10_0 .net "in0", 0 0, L_0x2c57b50; 1 drivers -v0x2a6f9c0_0 .net "in1", 0 0, L_0x2c43e90; 1 drivers -v0x2a6fa60_0 .net "nS", 0 0, L_0x2c57640; 1 drivers -v0x2a6f760_0 .net "out0", 0 0, L_0x2c576f0; 1 drivers -v0x2a6f800_0 .net "out1", 0 0, L_0x2c577e0; 1 drivers -v0x2a6f510_0 .net "outfinal", 0 0, L_0x2c578d0; 1 drivers -S_0x2a55760 .scope generate, "muxbits[17]" "muxbits[17]" 3 290, 3 290, S_0x29738d0; - .timescale -9 -12; -P_0x2a4a1d8 .param/l "i" 3 290, +C4<010001>; -L_0x2c5b0c0/d .functor OR 1, L_0x2c5b200, L_0x2c5b2a0, C4<0>, C4<0>; -L_0x2c5b0c0 .delay (20000,20000,20000) L_0x2c5b0c0/d; -v0x2a67d10_0 .net *"_s15", 0 0, L_0x2c5b200; 1 drivers -v0x2a6cbe0_0 .net *"_s16", 0 0, L_0x2c5b2a0; 1 drivers -S_0x2a63f60 .scope module, "ZeroMux" "FourInMux" 3 292, 3 24, S_0x2a55760; - .timescale -9 -12; -L_0x2c58a90/d .functor NOT 1, L_0x2c5a1b0, C4<0>, C4<0>, C4<0>; -L_0x2c58a90 .delay (10000,10000,10000) L_0x2c58a90/d; -L_0x2c59a70/d .functor NOT 1, L_0x2c58fe0, C4<0>, C4<0>, C4<0>; -L_0x2c59a70 .delay (10000,10000,10000) L_0x2c59a70/d; -L_0x2c59ad0/d .functor NAND 1, L_0x2c58a90, L_0x2c59a70, L_0x2c59110, C4<1>; -L_0x2c59ad0 .delay (10000,10000,10000) L_0x2c59ad0/d; -L_0x2c59c10/d .functor NAND 1, L_0x2c5a1b0, L_0x2c59a70, L_0x2c591b0, C4<1>; -L_0x2c59c10 .delay (10000,10000,10000) L_0x2c59c10/d; -L_0x2c59d00/d .functor NAND 1, L_0x2c58a90, L_0x2c58fe0, L_0x2c59250, C4<1>; -L_0x2c59d00 .delay (10000,10000,10000) L_0x2c59d00/d; -L_0x2c59df0/d .functor NAND 1, L_0x2c5a1b0, L_0x2c58fe0, L_0x2c59340, C4<1>; -L_0x2c59df0 .delay (10000,10000,10000) L_0x2c59df0/d; -L_0x2c59f00/d .functor NAND 1, L_0x2c59ad0, L_0x2c59c10, L_0x2c59d00, L_0x2c59df0; -L_0x2c59f00 .delay (10000,10000,10000) L_0x2c59f00/d; -v0x2a66fc0_0 .net "S0", 0 0, L_0x2c5a1b0; 1 drivers -v0x2a67060_0 .net "S1", 0 0, L_0x2c58fe0; 1 drivers -v0x2a66d60_0 .net "in0", 0 0, L_0x2c59110; 1 drivers -v0x2a66e00_0 .net "in1", 0 0, L_0x2c591b0; 1 drivers -v0x2a66ab0_0 .net "in2", 0 0, L_0x2c59250; 1 drivers -v0x2a66b50_0 .net "in3", 0 0, L_0x2c59340; 1 drivers -v0x2a64e90_0 .net "nS0", 0 0, L_0x2c58a90; 1 drivers -v0x2a69dc0_0 .net "nS1", 0 0, L_0x2c59a70; 1 drivers -v0x2a69e60_0 .net "out", 0 0, L_0x2c59f00; 1 drivers -v0x2a69b60_0 .net "out0", 0 0, L_0x2c59ad0; 1 drivers -v0x2a69c00_0 .net "out1", 0 0, L_0x2c59c10; 1 drivers -v0x2a698b0_0 .net "out2", 0 0, L_0x2c59d00; 1 drivers -v0x2a67c70_0 .net "out3", 0 0, L_0x2c59df0; 1 drivers -S_0x2a59750 .scope module, "OneMux" "FourInMux" 3 293, 3 24, S_0x2a55760; - .timescale -9 -12; -L_0x2c59430/d .functor NOT 1, L_0x2c5a2e0, C4<0>, C4<0>, C4<0>; -L_0x2c59430 .delay (10000,10000,10000) L_0x2c59430/d; -L_0x2c594e0/d .functor NOT 1, L_0x2c5a410, C4<0>, C4<0>, C4<0>; -L_0x2c594e0 .delay (10000,10000,10000) L_0x2c594e0/d; -L_0x2c59580/d .functor NAND 1, L_0x2c59430, L_0x2c594e0, L_0x2c5a540, C4<1>; -L_0x2c59580 .delay (10000,10000,10000) L_0x2c59580/d; -L_0x2c596c0/d .functor NAND 1, L_0x2c5a2e0, L_0x2c594e0, L_0x2c5a5e0, C4<1>; -L_0x2c596c0 .delay (10000,10000,10000) L_0x2c596c0/d; -L_0x2c597b0/d .functor NAND 1, L_0x2c59430, L_0x2c5a410, L_0x2c5a680, C4<1>; -L_0x2c597b0 .delay (10000,10000,10000) L_0x2c597b0/d; -L_0x2c598d0/d .functor NAND 1, L_0x2c5a2e0, L_0x2c5a410, L_0x2c5a770, C4<1>; -L_0x2c598d0 .delay (10000,10000,10000) L_0x2c598d0/d; -L_0x2c5ada0/d .functor NAND 1, L_0x2c59580, L_0x2c596c0, L_0x2c597b0, L_0x2c598d0; -L_0x2c5ada0 .delay (10000,10000,10000) L_0x2c5ada0/d; -v0x2a5b480_0 .net "S0", 0 0, L_0x2c5a2e0; 1 drivers -v0x2a5e4d0_0 .net "S1", 0 0, L_0x2c5a410; 1 drivers -v0x2a5e550_0 .net "in0", 0 0, L_0x2c5a540; 1 drivers -v0x2a5e220_0 .net "in1", 0 0, L_0x2c5a5e0; 1 drivers -v0x2a5e2c0_0 .net "in2", 0 0, L_0x2c5a680; 1 drivers -v0x2a5c590_0 .net "in3", 0 0, L_0x2c5a770; 1 drivers -v0x2a5c630_0 .net "nS0", 0 0, L_0x2c59430; 1 drivers -v0x2a61330_0 .net "nS1", 0 0, L_0x2c594e0; 1 drivers -v0x2a61060_0 .net "out", 0 0, L_0x2c5ada0; 1 drivers -v0x2a61100_0 .net "out0", 0 0, L_0x2c59580; 1 drivers -v0x2a5f3d0_0 .net "out1", 0 0, L_0x2c596c0; 1 drivers -v0x2a5f470_0 .net "out2", 0 0, L_0x2c597b0; 1 drivers -v0x2a64250_0 .net "out3", 0 0, L_0x2c598d0; 1 drivers -S_0x2a53ad0 .scope module, "TwoMux" "TwoInMux" 3 294, 3 8, S_0x2a55760; - .timescale -9 -12; -L_0x2a613b0/d .functor NOT 1, L_0x2c5acb0, C4<0>, C4<0>, C4<0>; -L_0x2a613b0 .delay (10000,10000,10000) L_0x2a613b0/d; -L_0x2c5a8f0/d .functor AND 1, L_0x2c5bb30, L_0x2a613b0, C4<1>, C4<1>; -L_0x2c5a8f0 .delay (20000,20000,20000) L_0x2c5a8f0/d; -L_0x2c5a9e0/d .functor AND 1, L_0x2c5bbd0, L_0x2c5acb0, C4<1>, C4<1>; -L_0x2c5a9e0 .delay (20000,20000,20000) L_0x2c5a9e0/d; -L_0x2c5aad0/d .functor OR 1, L_0x2c5a8f0, L_0x2c5a9e0, C4<0>, C4<0>; -L_0x2c5aad0 .delay (20000,20000,20000) L_0x2c5aad0/d; -v0x2a58850_0 .net "S", 0 0, L_0x2c5acb0; 1 drivers -v0x2a588f0_0 .net "in0", 0 0, L_0x2c5bb30; 1 drivers -v0x2a585a0_0 .net "in1", 0 0, L_0x2c5bbd0; 1 drivers -v0x2a58640_0 .net "nS", 0 0, L_0x2a613b0; 1 drivers -v0x2a56930_0 .net "out0", 0 0, L_0x2c5a8f0; 1 drivers -v0x2a5b690_0 .net "out1", 0 0, L_0x2c5a9e0; 1 drivers -v0x2a5b3e0_0 .net "outfinal", 0 0, L_0x2c5aad0; 1 drivers -S_0x2a3fab0 .scope generate, "muxbits[18]" "muxbits[18]" 3 290, 3 290, S_0x29738d0; - .timescale -9 -12; -P_0x2a30548 .param/l "i" 3 290, +C4<010010>; -L_0x2c5d8b0/d .functor OR 1, L_0x2c5d9f0, L_0x2c5da90, C4<0>, C4<0>; -L_0x2c5d8b0 .delay (20000,20000,20000) L_0x2c5d8b0/d; -v0x2a50d80_0 .net *"_s15", 0 0, L_0x2c5d9f0; 1 drivers -v0x2a55a10_0 .net *"_s16", 0 0, L_0x2c5da90; 1 drivers -S_0x2a4cd20 .scope module, "ZeroMux" "FourInMux" 3 292, 3 24, S_0x2a3fab0; - .timescale -9 -12; -L_0x2c5b390/d .functor NOT 1, L_0x2c5bcc0, C4<0>, C4<0>, C4<0>; -L_0x2c5b390 .delay (10000,10000,10000) L_0x2c5b390/d; -L_0x2c5b480/d .functor NOT 1, L_0x2c5bdf0, C4<0>, C4<0>, C4<0>; -L_0x2c5b480 .delay (10000,10000,10000) L_0x2c5b480/d; -L_0x2c5b520/d .functor NAND 1, L_0x2c5b390, L_0x2c5b480, L_0x2c5bf20, C4<1>; -L_0x2c5b520 .delay (10000,10000,10000) L_0x2c5b520/d; -L_0x2c5b660/d .functor NAND 1, L_0x2c5bcc0, L_0x2c5b480, L_0x2c5bfc0, C4<1>; -L_0x2c5b660 .delay (10000,10000,10000) L_0x2c5b660/d; -L_0x2c5b750/d .functor NAND 1, L_0x2c5b390, L_0x2c5bdf0, L_0x2c5c060, C4<1>; -L_0x2c5b750 .delay (10000,10000,10000) L_0x2c5b750/d; -L_0x2c5b840/d .functor NAND 1, L_0x2c5bcc0, L_0x2c5bdf0, L_0x2c5c150, C4<1>; -L_0x2c5b840 .delay (10000,10000,10000) L_0x2c5b840/d; -L_0x2c5b980/d .functor NAND 1, L_0x2c5b520, L_0x2c5b660, L_0x2c5b750, L_0x2c5b840; -L_0x2c5b980 .delay (10000,10000,10000) L_0x2c5b980/d; -v0x2a4b0e0_0 .net "S0", 0 0, L_0x2c5bcc0; 1 drivers -v0x2a50030_0 .net "S1", 0 0, L_0x2c5bdf0; 1 drivers -v0x2a500d0_0 .net "in0", 0 0, L_0x2c5bf20; 1 drivers -v0x2a4fdd0_0 .net "in1", 0 0, L_0x2c5bfc0; 1 drivers -v0x2a4fe50_0 .net "in2", 0 0, L_0x2c5c060; 1 drivers -v0x2a4fb20_0 .net "in3", 0 0, L_0x2c5c150; 1 drivers -v0x2a4fbc0_0 .net "nS0", 0 0, L_0x2c5b390; 1 drivers -v0x2a4dee0_0 .net "nS1", 0 0, L_0x2c5b480; 1 drivers -v0x2a4df80_0 .net "out", 0 0, L_0x2c5b980; 1 drivers -v0x2a52bd0_0 .net "out0", 0 0, L_0x2c5b520; 1 drivers -v0x2a52c50_0 .net "out1", 0 0, L_0x2c5b660; 1 drivers -v0x2a52920_0 .net "out2", 0 0, L_0x2c5b750; 1 drivers -v0x2a50ce0_0 .net "out3", 0 0, L_0x2c5b840; 1 drivers -S_0x2a473d0 .scope module, "OneMux" "FourInMux" 3 293, 3 24, S_0x2a3fab0; - .timescale -9 -12; -L_0x2c5c240/d .functor NOT 1, L_0x2c5d780, C4<0>, C4<0>, C4<0>; -L_0x2c5c240 .delay (10000,10000,10000) L_0x2c5c240/d; -L_0x2c5c330/d .functor NOT 1, L_0x2c5c920, C4<0>, C4<0>, C4<0>; -L_0x2c5c330 .delay (10000,10000,10000) L_0x2c5c330/d; -L_0x2c5c3d0/d .functor NAND 1, L_0x2c5c240, L_0x2c5c330, L_0x2c5ca50, C4<1>; -L_0x2c5c3d0 .delay (10000,10000,10000) L_0x2c5c3d0/d; -L_0x2c5c510/d .functor NAND 1, L_0x2c5d780, L_0x2c5c330, L_0x2c5caf0, C4<1>; -L_0x2c5c510 .delay (10000,10000,10000) L_0x2c5c510/d; -L_0x2c5c600/d .functor NAND 1, L_0x2c5c240, L_0x2c5c920, L_0x2c5cb90, C4<1>; -L_0x2c5c600 .delay (10000,10000,10000) L_0x2c5c600/d; -L_0x2c5c6f0/d .functor NAND 1, L_0x2c5d780, L_0x2c5c920, L_0x2c5cc80, C4<1>; -L_0x2c5c6f0 .delay (10000,10000,10000) L_0x2c5c6f0/d; -L_0x2c5d4d0/d .functor NAND 1, L_0x2c5c3d0, L_0x2c5c510, L_0x2c5c600, L_0x2c5c6f0; -L_0x2c5d4d0 .delay (10000,10000,10000) L_0x2c5d4d0/d; -v0x2a47120_0 .net "S0", 0 0, L_0x2c5d780; 1 drivers -v0x2a471c0_0 .net "S1", 0 0, L_0x2c5c920; 1 drivers -v0x2a454e0_0 .net "in0", 0 0, L_0x2c5ca50; 1 drivers -v0x2a45580_0 .net "in1", 0 0, L_0x2c5caf0; 1 drivers -v0x2a4a430_0 .net "in2", 0 0, L_0x2c5cb90; 1 drivers -v0x2a4a4d0_0 .net "in3", 0 0, L_0x2c5cc80; 1 drivers -v0x2a4a230_0 .net "nS0", 0 0, L_0x2c5c240; 1 drivers -v0x2a49f20_0 .net "nS1", 0 0, L_0x2c5c330; 1 drivers -v0x2a49fa0_0 .net "out", 0 0, L_0x2c5d4d0; 1 drivers -v0x2a482e0_0 .net "out0", 0 0, L_0x2c5c3d0; 1 drivers -v0x2a48380_0 .net "out1", 0 0, L_0x2c5c510; 1 drivers -v0x2a4d250_0 .net "out2", 0 0, L_0x2c5c600; 1 drivers -v0x2a4cff0_0 .net "out3", 0 0, L_0x2c5c6f0; 1 drivers -S_0x2a44830 .scope module, "TwoMux" "TwoInMux" 3 294, 3 8, S_0x2a3fab0; - .timescale -9 -12; -L_0x2c5cd70/d .functor NOT 1, L_0x2c5d1e0, C4<0>, C4<0>, C4<0>; -L_0x2c5cd70 .delay (10000,10000,10000) L_0x2c5cd70/d; -L_0x2c5ce20/d .functor AND 1, L_0x2c5d280, L_0x2c5cd70, C4<1>, C4<1>; -L_0x2c5ce20 .delay (20000,20000,20000) L_0x2c5ce20/d; -L_0x2c5cf10/d .functor AND 1, L_0x2c5d370, L_0x2c5d1e0, C4<1>, C4<1>; -L_0x2c5cf10 .delay (20000,20000,20000) L_0x2c5cf10/d; -L_0x2c5d000/d .functor OR 1, L_0x2c5ce20, L_0x2c5cf10, C4<0>, C4<0>; -L_0x2c5d000 .delay (20000,20000,20000) L_0x2c5d000/d; -v0x2a445d0_0 .net "S", 0 0, L_0x2c5d1e0; 1 drivers -v0x2a44670_0 .net "in0", 0 0, L_0x2c5d280; 1 drivers -v0x2a44320_0 .net "in1", 0 0, L_0x2c5d370; 1 drivers -v0x2a443c0_0 .net "nS", 0 0, L_0x2c5cd70; 1 drivers -v0x2a426e0_0 .net "out0", 0 0, L_0x2c5ce20; 1 drivers -v0x2a42780_0 .net "out1", 0 0, L_0x2c5cf10; 1 drivers -v0x2a47690_0 .net "outfinal", 0 0, L_0x2c5d000; 1 drivers -S_0x2a2d660 .scope generate, "muxbits[19]" "muxbits[19]" 3 290, 3 290, S_0x29738d0; - .timescale -9 -12; -P_0x2a21e68 .param/l "i" 3 290, +C4<010011>; -L_0x2c60c30/d .functor OR 1, L_0x2c60d70, L_0x2c5ff20, C4<0>, C4<0>; -L_0x2c60c30 .delay (20000,20000,20000) L_0x2c60c30/d; -v0x2a41870_0 .net *"_s15", 0 0, L_0x2c60d70; 1 drivers -v0x2a41540_0 .net *"_s16", 0 0, L_0x2c5ff20; 1 drivers -S_0x2a36ff0 .scope module, "ZeroMux" "FourInMux" 3 292, 3 24, S_0x2a2d660; - .timescale -9 -12; -L_0x2c5db80/d .functor NOT 1, L_0x2c5f0f0, C4<0>, C4<0>, C4<0>; -L_0x2c5db80 .delay (10000,10000,10000) L_0x2c5db80/d; -L_0x2c5dc70/d .functor NOT 1, L_0x2c5e510, C4<0>, C4<0>, C4<0>; -L_0x2c5dc70 .delay (10000,10000,10000) L_0x2c5dc70/d; -L_0x2c5dd10/d .functor NAND 1, L_0x2c5db80, L_0x2c5dc70, L_0x2c5e640, C4<1>; -L_0x2c5dd10 .delay (10000,10000,10000) L_0x2c5dd10/d; -L_0x2c5de50/d .functor NAND 1, L_0x2c5f0f0, L_0x2c5dc70, L_0x2c5e6e0, C4<1>; -L_0x2c5de50 .delay (10000,10000,10000) L_0x2c5de50/d; -L_0x2c5df40/d .functor NAND 1, L_0x2c5db80, L_0x2c5e510, L_0x2c5e780, C4<1>; -L_0x2c5df40 .delay (10000,10000,10000) L_0x2c5df40/d; -L_0x2c5e030/d .functor NAND 1, L_0x2c5f0f0, L_0x2c5e510, L_0x2c5e870, C4<1>; -L_0x2c5e030 .delay (10000,10000,10000) L_0x2c5e030/d; -L_0x2c5e140/d .functor NAND 1, L_0x2c5dd10, L_0x2c5de50, L_0x2c5df40, L_0x2c5e030; -L_0x2c5e140 .delay (10000,10000,10000) L_0x2c5e140/d; -v0x2a3bd70_0 .net "S0", 0 0, L_0x2c5f0f0; 1 drivers -v0x2a3be10_0 .net "S1", 0 0, L_0x2c5e510; 1 drivers -v0x2a3bac0_0 .net "in0", 0 0, L_0x2c5e640; 1 drivers -v0x2a3bb60_0 .net "in1", 0 0, L_0x2c5e6e0; 1 drivers -v0x2a39e30_0 .net "in2", 0 0, L_0x2c5e780; 1 drivers -v0x2a39ed0_0 .net "in3", 0 0, L_0x2c5e870; 1 drivers -v0x2a3ebd0_0 .net "nS0", 0 0, L_0x2c5db80; 1 drivers -v0x2a3e900_0 .net "nS1", 0 0, L_0x2c5dc70; 1 drivers -v0x2a3e9a0_0 .net "out", 0 0, L_0x2c5e140; 1 drivers -v0x2a3cc70_0 .net "out0", 0 0, L_0x2c5dd10; 1 drivers -v0x2a3cd10_0 .net "out1", 0 0, L_0x2c5de50; 1 drivers -v0x2a41a30_0 .net "out2", 0 0, L_0x2c5df40; 1 drivers -v0x2a417d0_0 .net "out3", 0 0, L_0x2c5e030; 1 drivers -S_0x2a332b0 .scope module, "OneMux" "FourInMux" 3 293, 3 24, S_0x2a2d660; - .timescale -9 -12; -L_0x2c5e960/d .functor NOT 1, L_0x2c5f220, C4<0>, C4<0>, C4<0>; -L_0x2c5e960 .delay (10000,10000,10000) L_0x2c5e960/d; -L_0x2c5ea10/d .functor NOT 1, L_0x2c5f350, C4<0>, C4<0>, C4<0>; -L_0x2c5ea10 .delay (10000,10000,10000) L_0x2c5ea10/d; -L_0x2c5eab0/d .functor NAND 1, L_0x2c5e960, L_0x2c5ea10, L_0x2c5f480, C4<1>; -L_0x2c5eab0 .delay (10000,10000,10000) L_0x2c5eab0/d; -L_0x2c5ebf0/d .functor NAND 1, L_0x2c5f220, L_0x2c5ea10, L_0x2c5f520, C4<1>; -L_0x2c5ebf0 .delay (10000,10000,10000) L_0x2c5ebf0/d; -L_0x2c5ece0/d .functor NAND 1, L_0x2c5e960, L_0x2c5f350, L_0x2c5f5c0, C4<1>; -L_0x2c5ece0 .delay (10000,10000,10000) L_0x2c5ece0/d; -L_0x2c5ee00/d .functor NAND 1, L_0x2c5f220, L_0x2c5f350, L_0x2c5f6b0, C4<1>; -L_0x2c5ee00 .delay (10000,10000,10000) L_0x2c5ee00/d; -L_0x2c5ef70/d .functor NAND 1, L_0x2c5eab0, L_0x2c5ebf0, L_0x2c5ece0, L_0x2c5ee00; -L_0x2c5ef70 .delay (10000,10000,10000) L_0x2c5ef70/d; -v0x2a2e610_0 .net "S0", 0 0, L_0x2c5f220; 1 drivers -v0x2a33000_0 .net "S1", 0 0, L_0x2c5f350; 1 drivers -v0x2a33080_0 .net "in0", 0 0, L_0x2c5f480; 1 drivers -v0x2a31370_0 .net "in1", 0 0, L_0x2c5f520; 1 drivers -v0x2a31410_0 .net "in2", 0 0, L_0x2c5f5c0; 1 drivers -v0x2a360f0_0 .net "in3", 0 0, L_0x2c5f6b0; 1 drivers -v0x2a36190_0 .net "nS0", 0 0, L_0x2c5e960; 1 drivers -v0x2a35e60_0 .net "nS1", 0 0, L_0x2c5ea10; 1 drivers -v0x2a341b0_0 .net "out", 0 0, L_0x2c5ef70; 1 drivers -v0x2a34250_0 .net "out0", 0 0, L_0x2c5eab0; 1 drivers -v0x2a38f30_0 .net "out1", 0 0, L_0x2c5ebf0; 1 drivers -v0x2a38fd0_0 .net "out2", 0 0, L_0x2c5ece0; 1 drivers -v0x2a38d10_0 .net "out3", 0 0, L_0x2c5ee00; 1 drivers -S_0x2a2d3b0 .scope module, "TwoMux" "TwoInMux" 3 294, 3 8, S_0x2a2d660; - .timescale -9 -12; -L_0x2a35ee0/d .functor NOT 1, L_0x2c5fbb0, C4<0>, C4<0>, C4<0>; -L_0x2a35ee0 .delay (10000,10000,10000) L_0x2a35ee0/d; -L_0x2c5f7f0/d .functor AND 1, L_0x2c5fc50, L_0x2a35ee0, C4<1>, C4<1>; -L_0x2c5f7f0 .delay (20000,20000,20000) L_0x2c5f7f0/d; -L_0x2c5f8e0/d .functor AND 1, L_0x2c5fd40, L_0x2c5fbb0, C4<1>, C4<1>; -L_0x2c5f8e0 .delay (20000,20000,20000) L_0x2c5f8e0/d; -L_0x2c5f9d0/d .functor OR 1, L_0x2c5f7f0, L_0x2c5f8e0, C4<0>, C4<0>; -L_0x2c5f9d0 .delay (20000,20000,20000) L_0x2c5f9d0/d; -v0x2a2b770_0 .net "S", 0 0, L_0x2c5fbb0; 1 drivers -v0x2a2b810_0 .net "in0", 0 0, L_0x2c5fc50; 1 drivers -v0x2a306c0_0 .net "in1", 0 0, L_0x2c5fd40; 1 drivers -v0x2a30760_0 .net "nS", 0 0, L_0x2a35ee0; 1 drivers -v0x2a30480_0 .net "out0", 0 0, L_0x2c5f7f0; 1 drivers -v0x2a301b0_0 .net "out1", 0 0, L_0x2c5f8e0; 1 drivers -v0x2a2e570_0 .net "outfinal", 0 0, L_0x2c5f9d0; 1 drivers -S_0x2a40cb0 .scope generate, "muxbits[20]" "muxbits[20]" 3 290, 3 290, S_0x29738d0; - .timescale -9 -12; -P_0x2a63688 .param/l "i" 3 290, +C4<010100>; -L_0x2c62600/d .functor OR 1, L_0x2c62740, L_0x2c627e0, C4<0>, C4<0>; -L_0x2c62600 .delay (20000,20000,20000) L_0x2c62600/d; -v0x2a28a10_0 .net *"_s15", 0 0, L_0x2c62740; 1 drivers -v0x2a2d8c0_0 .net *"_s16", 0 0, L_0x2c627e0; 1 drivers -S_0x2a22d70 .scope module, "ZeroMux" "FourInMux" 3 292, 3 24, S_0x2a40cb0; - .timescale -9 -12; -L_0x2c60010/d .functor NOT 1, L_0x2c608b0, C4<0>, C4<0>, C4<0>; -L_0x2c60010 .delay (10000,10000,10000) L_0x2c60010/d; -L_0x2c60100/d .functor NOT 1, L_0x2c609e0, C4<0>, C4<0>, C4<0>; -L_0x2c60100 .delay (10000,10000,10000) L_0x2c60100/d; -L_0x2c601a0/d .functor NAND 1, L_0x2c60010, L_0x2c60100, L_0x2c61ab0, C4<1>; -L_0x2c601a0 .delay (10000,10000,10000) L_0x2c601a0/d; -L_0x2c602e0/d .functor NAND 1, L_0x2c608b0, L_0x2c60100, L_0x2c61b50, C4<1>; -L_0x2c602e0 .delay (10000,10000,10000) L_0x2c602e0/d; -L_0x2c603d0/d .functor NAND 1, L_0x2c60010, L_0x2c609e0, L_0x2c60e10, C4<1>; -L_0x2c603d0 .delay (10000,10000,10000) L_0x2c603d0/d; -L_0x2c604c0/d .functor NAND 1, L_0x2c608b0, L_0x2c609e0, L_0x2c60f00, C4<1>; -L_0x2c604c0 .delay (10000,10000,10000) L_0x2c604c0/d; -L_0x2c60600/d .functor NAND 1, L_0x2c601a0, L_0x2c602e0, L_0x2c603d0, L_0x2c604c0; -L_0x2c60600 .delay (10000,10000,10000) L_0x2c60600/d; -v0x2a27cc0_0 .net "S0", 0 0, L_0x2c608b0; 1 drivers -v0x2a27a60_0 .net "S1", 0 0, L_0x2c609e0; 1 drivers -v0x2a27b00_0 .net "in0", 0 0, L_0x2c61ab0; 1 drivers -v0x2a277b0_0 .net "in1", 0 0, L_0x2c61b50; 1 drivers -v0x2a27830_0 .net "in2", 0 0, L_0x2c60e10; 1 drivers -v0x2a25b70_0 .net "in3", 0 0, L_0x2c60f00; 1 drivers -v0x2a25c10_0 .net "nS0", 0 0, L_0x2c60010; 1 drivers -v0x2a2aac0_0 .net "nS1", 0 0, L_0x2c60100; 1 drivers -v0x2a2ab60_0 .net "out", 0 0, L_0x2c60600; 1 drivers -v0x2a2a860_0 .net "out0", 0 0, L_0x2c601a0; 1 drivers -v0x2a2a8e0_0 .net "out1", 0 0, L_0x2c602e0; 1 drivers -v0x2a2a5b0_0 .net "out2", 0 0, L_0x2c603d0; 1 drivers -v0x2a28970_0 .net "out3", 0 0, L_0x2c604c0; 1 drivers -S_0x2a1f100 .scope module, "OneMux" "FourInMux" 3 293, 3 24, S_0x2a40cb0; - .timescale -9 -12; -L_0x2c60ff0/d .functor NOT 1, L_0x2c618c0, C4<0>, C4<0>, C4<0>; -L_0x2c60ff0 .delay (10000,10000,10000) L_0x2c60ff0/d; -L_0x2c610e0/d .functor NOT 1, L_0x2c619f0, C4<0>, C4<0>, C4<0>; -L_0x2c610e0 .delay (10000,10000,10000) L_0x2c610e0/d; -L_0x2c61180/d .functor NAND 1, L_0x2c60ff0, L_0x2c610e0, L_0x2c62950, C4<1>; -L_0x2c61180 .delay (10000,10000,10000) L_0x2c61180/d; -L_0x2c612c0/d .functor NAND 1, L_0x2c618c0, L_0x2c610e0, L_0x2c61bf0, C4<1>; -L_0x2c612c0 .delay (10000,10000,10000) L_0x2c612c0/d; -L_0x2c613b0/d .functor NAND 1, L_0x2c60ff0, L_0x2c619f0, L_0x2c61c90, C4<1>; -L_0x2c613b0 .delay (10000,10000,10000) L_0x2c613b0/d; -L_0x2c614a0/d .functor NAND 1, L_0x2c618c0, L_0x2c619f0, L_0x2c61d80, C4<1>; -L_0x2c614a0 .delay (10000,10000,10000) L_0x2c614a0/d; -L_0x2c61610/d .functor NAND 1, L_0x2c61180, L_0x2c612c0, L_0x2c613b0, L_0x2c614a0; -L_0x2c61610 .delay (10000,10000,10000) L_0x2c61610/d; -v0x2a1ee50_0 .net "S0", 0 0, L_0x2c618c0; 1 drivers -v0x2a1eef0_0 .net "S1", 0 0, L_0x2c619f0; 1 drivers -v0x2a1d1c0_0 .net "in0", 0 0, L_0x2c62950; 1 drivers -v0x2a1d260_0 .net "in1", 0 0, L_0x2c61bf0; 1 drivers -v0x2a220c0_0 .net "in2", 0 0, L_0x2c61c90; 1 drivers -v0x2a22160_0 .net "in3", 0 0, L_0x2c61d80; 1 drivers -v0x2a21ec0_0 .net "nS0", 0 0, L_0x2c60ff0; 1 drivers -v0x2a20000_0 .net "nS1", 0 0, L_0x2c610e0; 1 drivers -v0x2a20080_0 .net "out", 0 0, L_0x2c61610; 1 drivers -v0x2a24ec0_0 .net "out0", 0 0, L_0x2c61180; 1 drivers -v0x2a24f60_0 .net "out1", 0 0, L_0x2c612c0; 1 drivers -v0x2a24c80_0 .net "out2", 0 0, L_0x2c613b0; 1 drivers -v0x2a249d0_0 .net "out3", 0 0, L_0x2c614a0; 1 drivers -S_0x2a3e430 .scope module, "TwoMux" "TwoInMux" 3 294, 3 8, S_0x2a40cb0; - .timescale -9 -12; -L_0x2c61e70/d .functor NOT 1, L_0x2c622e0, C4<0>, C4<0>, C4<0>; -L_0x2c61e70 .delay (10000,10000,10000) L_0x2c61e70/d; -L_0x2c61f20/d .functor AND 1, L_0x2c62380, L_0x2c61e70, C4<1>, C4<1>; -L_0x2c61f20 .delay (20000,20000,20000) L_0x2c61f20/d; -L_0x2c62010/d .functor AND 1, L_0x2c62470, L_0x2c622e0, C4<1>, C4<1>; -L_0x2c62010 .delay (20000,20000,20000) L_0x2c62010/d; -L_0x2c62100/d .functor OR 1, L_0x2c61f20, L_0x2c62010, C4<0>, C4<0>; -L_0x2c62100 .delay (20000,20000,20000) L_0x2c62100/d; -v0x2a3b5f0_0 .net "S", 0 0, L_0x2c622e0; 1 drivers -v0x2a3b690_0 .net "in0", 0 0, L_0x2c62380; 1 drivers -v0x2a73460_0 .net "in1", 0 0, L_0x2c62470; 1 drivers -v0x2a73500_0 .net "nS", 0 0, L_0x2c61e70; 1 drivers -v0x2a1bf80_0 .net "out0", 0 0, L_0x2c61f20; 1 drivers -v0x2a1c020_0 .net "out1", 0 0, L_0x2c62010; 1 drivers -v0x2a1a2c0_0 .net "outfinal", 0 0, L_0x2c62100; 1 drivers -S_0x2a69410 .scope generate, "muxbits[21]" "muxbits[21]" 3 290, 3 290, S_0x29738d0; - .timescale -9 -12; -P_0x2a27318 .param/l "i" 3 290, +C4<010101>; -L_0x2c64b40/d .functor OR 1, L_0x2c64c80, L_0x2c64d20, C4<0>, C4<0>; -L_0x2c64b40 .delay (20000,20000,20000) L_0x2c64b40/d; -v0x2a1ea20_0 .net *"_s15", 0 0, L_0x2c64c80; 1 drivers -v0x2a43920_0 .net *"_s16", 0 0, L_0x2c64d20; 1 drivers -S_0x2a4f100 .scope module, "ZeroMux" "FourInMux" 3 292, 3 24, S_0x2a69410; - .timescale -9 -12; -L_0x2c63720/d .functor NOT 1, L_0x2c63f80, C4<0>, C4<0>, C4<0>; -L_0x2c63720 .delay (10000,10000,10000) L_0x2c63720/d; -L_0x2c637d0/d .functor NOT 1, L_0x2c629f0, C4<0>, C4<0>, C4<0>; -L_0x2c637d0 .delay (10000,10000,10000) L_0x2c637d0/d; -L_0x2c63870/d .functor NAND 1, L_0x2c63720, L_0x2c637d0, L_0x2c62b20, C4<1>; -L_0x2c63870 .delay (10000,10000,10000) L_0x2c63870/d; -L_0x2c639b0/d .functor NAND 1, L_0x2c63f80, L_0x2c637d0, L_0x2c62bc0, C4<1>; -L_0x2c639b0 .delay (10000,10000,10000) L_0x2c639b0/d; -L_0x2c63aa0/d .functor NAND 1, L_0x2c63720, L_0x2c629f0, L_0x2c62c60, C4<1>; -L_0x2c63aa0 .delay (10000,10000,10000) L_0x2c63aa0/d; -L_0x2c63b90/d .functor NAND 1, L_0x2c63f80, L_0x2c629f0, L_0x2c62d50, C4<1>; -L_0x2c63b90 .delay (10000,10000,10000) L_0x2c63b90/d; -L_0x2c63cd0/d .functor NAND 1, L_0x2c63870, L_0x2c639b0, L_0x2c63aa0, L_0x2c63b90; -L_0x2c63cd0 .delay (10000,10000,10000) L_0x2c63cd0/d; -v0x2a4c880_0 .net "S0", 0 0, L_0x2c63f80; 1 drivers -v0x2a4c920_0 .net "S1", 0 0, L_0x2c629f0; 1 drivers -v0x2a4c300_0 .net "in0", 0 0, L_0x2c62b20; 1 drivers -v0x2a4c3a0_0 .net "in1", 0 0, L_0x2c62bc0; 1 drivers -v0x2a49a80_0 .net "in2", 0 0, L_0x2c62c60; 1 drivers -v0x2a49b20_0 .net "in3", 0 0, L_0x2c62d50; 1 drivers -v0x2a49520_0 .net "nS0", 0 0, L_0x2c63720; 1 drivers -v0x2a46c80_0 .net "nS1", 0 0, L_0x2c637d0; 1 drivers -v0x2a46d20_0 .net "out", 0 0, L_0x2c63cd0; 1 drivers -v0x2a46700_0 .net "out0", 0 0, L_0x2c63870; 1 drivers -v0x2a467a0_0 .net "out1", 0 0, L_0x2c639b0; 1 drivers -v0x2a43e80_0 .net "out2", 0 0, L_0x2c63aa0; 1 drivers -v0x2a1e980_0 .net "out3", 0 0, L_0x2c63b90; 1 drivers -S_0x2a5dd50 .scope module, "OneMux" "FourInMux" 3 293, 3 24, S_0x2a69410; - .timescale -9 -12; -L_0x2c62e40/d .functor NOT 1, L_0x2c64e20, C4<0>, C4<0>, C4<0>; -L_0x2c62e40 .delay (10000,10000,10000) L_0x2c62e40/d; -L_0x2c62ef0/d .functor NOT 1, L_0x2c64f50, C4<0>, C4<0>, C4<0>; -L_0x2c62ef0 .delay (10000,10000,10000) L_0x2c62ef0/d; -L_0x2c62f90/d .functor NAND 1, L_0x2c62e40, L_0x2c62ef0, L_0x2c640b0, C4<1>; -L_0x2c62f90 .delay (10000,10000,10000) L_0x2c62f90/d; -L_0x2c630d0/d .functor NAND 1, L_0x2c64e20, L_0x2c62ef0, L_0x2c64150, C4<1>; -L_0x2c630d0 .delay (10000,10000,10000) L_0x2c630d0/d; -L_0x2c631c0/d .functor NAND 1, L_0x2c62e40, L_0x2c64f50, L_0x2c641f0, C4<1>; -L_0x2c631c0 .delay (10000,10000,10000) L_0x2c631c0/d; -L_0x2c632e0/d .functor NAND 1, L_0x2c64e20, L_0x2c64f50, L_0x2c642e0, C4<1>; -L_0x2c632e0 .delay (10000,10000,10000) L_0x2c632e0/d; -L_0x2c63450/d .functor NAND 1, L_0x2c62f90, L_0x2c630d0, L_0x2c631c0, L_0x2c632e0; -L_0x2c63450 .delay (10000,10000,10000) L_0x2c63450/d; -v0x2a21780_0 .net "S0", 0 0, L_0x2c64e20; 1 drivers -v0x2a5af10_0 .net "S1", 0 0, L_0x2c64f50; 1 drivers -v0x2a5af90_0 .net "in0", 0 0, L_0x2c640b0; 1 drivers -v0x2a21480_0 .net "in1", 0 0, L_0x2c64150; 1 drivers -v0x2a21520_0 .net "in2", 0 0, L_0x2c641f0; 1 drivers -v0x2a580d0_0 .net "in3", 0 0, L_0x2c642e0; 1 drivers -v0x2a58170_0 .net "nS0", 0 0, L_0x2c62e40; 1 drivers -v0x2a552b0_0 .net "nS1", 0 0, L_0x2c62ef0; 1 drivers -v0x2a52480_0 .net "out", 0 0, L_0x2c63450; 1 drivers -v0x2a52520_0 .net "out0", 0 0, L_0x2c62f90; 1 drivers -v0x2a51f00_0 .net "out1", 0 0, L_0x2c630d0; 1 drivers -v0x2a51fa0_0 .net "out2", 0 0, L_0x2c631c0; 1 drivers -v0x2a4f710_0 .net "out3", 0 0, L_0x2c632e0; 1 drivers -S_0x2a68e90 .scope module, "TwoMux" "TwoInMux" 3 294, 3 8, S_0x2a69410; - .timescale -9 -12; -L_0x2a55330/d .functor NOT 1, L_0x2c64820, C4<0>, C4<0>, C4<0>; -L_0x2a55330 .delay (10000,10000,10000) L_0x2a55330/d; -L_0x2c64460/d .functor AND 1, L_0x2c648c0, L_0x2a55330, C4<1>, C4<1>; -L_0x2c64460 .delay (20000,20000,20000) L_0x2c64460/d; -L_0x2c64550/d .functor AND 1, L_0x2c649b0, L_0x2c64820, C4<1>, C4<1>; -L_0x2c64550 .delay (20000,20000,20000) L_0x2c64550/d; -L_0x2c64640/d .functor OR 1, L_0x2c64460, L_0x2c64550, C4<0>, C4<0>; -L_0x2c64640 .delay (20000,20000,20000) L_0x2c64640/d; -v0x2a66610_0 .net "S", 0 0, L_0x2c64820; 1 drivers -v0x2a666b0_0 .net "in0", 0 0, L_0x2c648c0; 1 drivers -v0x2a66090_0 .net "in1", 0 0, L_0x2c649b0; 1 drivers -v0x2a66130_0 .net "nS", 0 0, L_0x2a55330; 1 drivers -v0x2a635c0_0 .net "out0", 0 0, L_0x2c64460; 1 drivers -v0x2a60b90_0 .net "out1", 0 0, L_0x2c64550; 1 drivers -v0x2a216e0_0 .net "outfinal", 0 0, L_0x2c64640; 1 drivers -S_0x2aef3d0 .scope generate, "muxbits[22]" "muxbits[22]" 3 290, 3 290, S_0x29738d0; - .timescale -9 -12; -P_0x2952758 .param/l "i" 3 290, +C4<010110>; -L_0x2c672d0/d .functor OR 1, L_0x2c67410, L_0x2c68540, C4<0>, C4<0>; -L_0x2c672d0 .delay (20000,20000,20000) L_0x2c672d0/d; -v0x2a6c2b0_0 .net *"_s15", 0 0, L_0x2c67410; 1 drivers -v0x2a6bc90_0 .net *"_s16", 0 0, L_0x2c68540; 1 drivers -S_0x2a75380 .scope module, "ZeroMux" "FourInMux" 3 292, 3 24, S_0x2aef3d0; - .timescale -9 -12; -L_0x2c65e50/d .functor NOT 1, L_0x2c65080, C4<0>, C4<0>, C4<0>; -L_0x2c65e50 .delay (10000,10000,10000) L_0x2c65e50/d; -L_0x2c65f40/d .functor NOT 1, L_0x2c651b0, C4<0>, C4<0>, C4<0>; -L_0x2c65f40 .delay (10000,10000,10000) L_0x2c65f40/d; -L_0x2c65fe0/d .functor NAND 1, L_0x2c65e50, L_0x2c65f40, L_0x2c652e0, C4<1>; -L_0x2c65fe0 .delay (10000,10000,10000) L_0x2c65fe0/d; -L_0x2c66120/d .functor NAND 1, L_0x2c65080, L_0x2c65f40, L_0x2c65380, C4<1>; -L_0x2c66120 .delay (10000,10000,10000) L_0x2c66120/d; -L_0x2c66210/d .functor NAND 1, L_0x2c65e50, L_0x2c651b0, L_0x2c65420, C4<1>; -L_0x2c66210 .delay (10000,10000,10000) L_0x2c66210/d; -L_0x2c66300/d .functor NAND 1, L_0x2c65080, L_0x2c651b0, L_0x2c65510, C4<1>; -L_0x2c66300 .delay (10000,10000,10000) L_0x2c66300/d; -L_0x2c66440/d .functor NAND 1, L_0x2c65fe0, L_0x2c66120, L_0x2c66210, L_0x2c66300; -L_0x2c66440 .delay (10000,10000,10000) L_0x2c66440/d; -v0x2a750e0_0 .net "S0", 0 0, L_0x2c65080; 1 drivers -v0x2a74c20_0 .net "S1", 0 0, L_0x2c651b0; 1 drivers -v0x2a74cc0_0 .net "in0", 0 0, L_0x2c652e0; 1 drivers -v0x2a71e10_0 .net "in1", 0 0, L_0x2c65380; 1 drivers -v0x2a71e90_0 .net "in2", 0 0, L_0x2c65420; 1 drivers -v0x2a71890_0 .net "in3", 0 0, L_0x2c65510; 1 drivers -v0x2a71930_0 .net "nS0", 0 0, L_0x2c65e50; 1 drivers -v0x2a23f90_0 .net "nS1", 0 0, L_0x2c65f40; 1 drivers -v0x2a24030_0 .net "out", 0 0, L_0x2c66440; 1 drivers -v0x2a6f010_0 .net "out0", 0 0, L_0x2c65fe0; 1 drivers -v0x2a6f090_0 .net "out1", 0 0, L_0x2c66120; 1 drivers -v0x2a6ea90_0 .net "out2", 0 0, L_0x2c66210; 1 drivers -v0x2a6c210_0 .net "out3", 0 0, L_0x2c66300; 1 drivers -S_0x2a2cf10 .scope module, "OneMux" "FourInMux" 3 293, 3 24, S_0x2aef3d0; - .timescale -9 -12; -L_0x2c65600/d .functor NOT 1, L_0x2c675a0, C4<0>, C4<0>, C4<0>; -L_0x2c65600 .delay (10000,10000,10000) L_0x2c65600/d; -L_0x2c656f0/d .functor NOT 1, L_0x2c666f0, C4<0>, C4<0>, C4<0>; -L_0x2c656f0 .delay (10000,10000,10000) L_0x2c656f0/d; -L_0x2c65790/d .functor NAND 1, L_0x2c65600, L_0x2c656f0, L_0x2c66820, C4<1>; -L_0x2c65790 .delay (10000,10000,10000) L_0x2c65790/d; -L_0x2c658d0/d .functor NAND 1, L_0x2c675a0, L_0x2c656f0, L_0x2c668c0, C4<1>; -L_0x2c658d0 .delay (10000,10000,10000) L_0x2c658d0/d; -L_0x2c659c0/d .functor NAND 1, L_0x2c65600, L_0x2c666f0, L_0x2c66960, C4<1>; -L_0x2c659c0 .delay (10000,10000,10000) L_0x2c659c0/d; -L_0x2c65ab0/d .functor NAND 1, L_0x2c675a0, L_0x2c666f0, L_0x2c66a50, C4<1>; -L_0x2c65ab0 .delay (10000,10000,10000) L_0x2c65ab0/d; -L_0x2c65c20/d .functor NAND 1, L_0x2c65790, L_0x2c658d0, L_0x2c659c0, L_0x2c65ab0; -L_0x2c65c20 .delay (10000,10000,10000) L_0x2c65c20/d; -v0x2a2c990_0 .net "S0", 0 0, L_0x2c675a0; 1 drivers -v0x2a2ca30_0 .net "S1", 0 0, L_0x2c666f0; 1 drivers -v0x2a2a110_0 .net "in0", 0 0, L_0x2c66820; 1 drivers -v0x2a2a1b0_0 .net "in1", 0 0, L_0x2c668c0; 1 drivers -v0x2a29b90_0 .net "in2", 0 0, L_0x2c66960; 1 drivers -v0x2a29c30_0 .net "in3", 0 0, L_0x2c66a50; 1 drivers -v0x2a27370_0 .net "nS0", 0 0, L_0x2c65600; 1 drivers -v0x2a1bab0_0 .net "nS1", 0 0, L_0x2c656f0; 1 drivers -v0x2a1bb30_0 .net "out", 0 0, L_0x2c65c20; 1 drivers -v0x2a26d90_0 .net "out0", 0 0, L_0x2c65790; 1 drivers -v0x2a26e30_0 .net "out1", 0 0, L_0x2c658d0; 1 drivers -v0x2a24530_0 .net "out2", 0 0, L_0x2c659c0; 1 drivers -v0x2a75610_0 .net "out3", 0 0, L_0x2c65ab0; 1 drivers -S_0x2a387b0 .scope module, "TwoMux" "TwoInMux" 3 294, 3 8, S_0x2aef3d0; - .timescale -9 -12; -L_0x2c66b40/d .functor NOT 1, L_0x2c66fb0, C4<0>, C4<0>, C4<0>; -L_0x2c66b40 .delay (10000,10000,10000) L_0x2c66b40/d; -L_0x2c66bf0/d .functor AND 1, L_0x2c67050, L_0x2c66b40, C4<1>, C4<1>; -L_0x2c66bf0 .delay (20000,20000,20000) L_0x2c66bf0/d; -L_0x2c66ce0/d .functor AND 1, L_0x2c67140, L_0x2c66fb0, C4<1>, C4<1>; -L_0x2c66ce0 .delay (20000,20000,20000) L_0x2c66ce0/d; -L_0x2c66dd0/d .functor OR 1, L_0x2c66bf0, L_0x2c66ce0, C4<0>, C4<0>; -L_0x2c66dd0 .delay (20000,20000,20000) L_0x2c66dd0/d; -v0x2a35970_0 .net "S", 0 0, L_0x2c66fb0; 1 drivers -v0x2a35a10_0 .net "in0", 0 0, L_0x2c67050; 1 drivers -v0x2a32b30_0 .net "in1", 0 0, L_0x2c67140; 1 drivers -v0x2a32bd0_0 .net "nS", 0 0, L_0x2c66b40; 1 drivers -v0x2a2fd10_0 .net "out0", 0 0, L_0x2c66bf0; 1 drivers -v0x2a2fdb0_0 .net "out1", 0 0, L_0x2c66ce0; 1 drivers -v0x2a2f7f0_0 .net "outfinal", 0 0, L_0x2c66dd0; 1 drivers -S_0x2951070 .scope generate, "muxbits[23]" "muxbits[23]" 3 290, 3 290, S_0x29738d0; - .timescale -9 -12; -P_0x2945988 .param/l "i" 3 290, +C4<010111>; -L_0x2c692d0/d .functor OR 1, L_0x2c6aca0, L_0x2c69d90, C4<0>, C4<0>; -L_0x2c692d0 .delay (20000,20000,20000) L_0x2c692d0/d; -v0x2af2740_0 .net *"_s15", 0 0, L_0x2c6aca0; 1 drivers -v0x2af14b0_0 .net *"_s16", 0 0, L_0x2c69d90; 1 drivers -S_0x295c650 .scope module, "ZeroMux" "FourInMux" 3 292, 3 24, S_0x2951070; - .timescale -9 -12; -L_0x2c676d0/d .functor NOT 1, L_0x2c67fa0, C4<0>, C4<0>, C4<0>; -L_0x2c676d0 .delay (10000,10000,10000) L_0x2c676d0/d; -L_0x2c677c0/d .functor NOT 1, L_0x2c680d0, C4<0>, C4<0>, C4<0>; -L_0x2c677c0 .delay (10000,10000,10000) L_0x2c677c0/d; -L_0x2c67860/d .functor NAND 1, L_0x2c676d0, L_0x2c677c0, L_0x2c68200, C4<1>; -L_0x2c67860 .delay (10000,10000,10000) L_0x2c67860/d; -L_0x2c679a0/d .functor NAND 1, L_0x2c67fa0, L_0x2c677c0, L_0x2c682a0, C4<1>; -L_0x2c679a0 .delay (10000,10000,10000) L_0x2c679a0/d; -L_0x2c67a90/d .functor NAND 1, L_0x2c676d0, L_0x2c680d0, L_0x2c68340, C4<1>; -L_0x2c67a90 .delay (10000,10000,10000) L_0x2c67a90/d; -L_0x2c67b80/d .functor NAND 1, L_0x2c67fa0, L_0x2c680d0, L_0x2c68430, C4<1>; -L_0x2c67b80 .delay (10000,10000,10000) L_0x2c67b80/d; -L_0x2c67cf0/d .functor NAND 1, L_0x2c67860, L_0x2c679a0, L_0x2c67a90, L_0x2c67b80; -L_0x2c67cf0 .delay (10000,10000,10000) L_0x2c67cf0/d; -v0x295b7f0_0 .net "S0", 0 0, L_0x2c67fa0; 1 drivers -v0x295b890_0 .net "S1", 0 0, L_0x2c680d0; 1 drivers -v0x295ed40_0 .net "in0", 0 0, L_0x2c68200; 1 drivers -v0x295ede0_0 .net "in1", 0 0, L_0x2c682a0; 1 drivers -v0x295eae0_0 .net "in2", 0 0, L_0x2c68340; 1 drivers -v0x295eb80_0 .net "in3", 0 0, L_0x2c68430; 1 drivers -v0x295dc70_0 .net "nS0", 0 0, L_0x2c676d0; 1 drivers -v0x29611f0_0 .net "nS1", 0 0, L_0x2c677c0; 1 drivers -v0x2961290_0 .net "out", 0 0, L_0x2c67cf0; 1 drivers -v0x2960f90_0 .net "out0", 0 0, L_0x2c67860; 1 drivers -v0x2961030_0 .net "out1", 0 0, L_0x2c679a0; 1 drivers -v0x2960100_0 .net "out2", 0 0, L_0x2c67a90; 1 drivers -v0x2af26a0_0 .net "out3", 0 0, L_0x2c67b80; 1 drivers -S_0x2954ad0 .scope module, "OneMux" "FourInMux" 3 293, 3 24, S_0x2951070; - .timescale -9 -12; -L_0x2c69490/d .functor NOT 1, L_0x2c685e0, C4<0>, C4<0>, C4<0>; -L_0x2c69490 .delay (10000,10000,10000) L_0x2c69490/d; -L_0x2c69580/d .functor NOT 1, L_0x2c68710, C4<0>, C4<0>, C4<0>; -L_0x2c69580 .delay (10000,10000,10000) L_0x2c69580/d; -L_0x2c69620/d .functor NAND 1, L_0x2c69490, L_0x2c69580, L_0x2c68840, C4<1>; -L_0x2c69620 .delay (10000,10000,10000) L_0x2c69620/d; -L_0x2c69760/d .functor NAND 1, L_0x2c685e0, L_0x2c69580, L_0x2c688e0, C4<1>; -L_0x2c69760 .delay (10000,10000,10000) L_0x2c69760/d; -L_0x2c69850/d .functor NAND 1, L_0x2c69490, L_0x2c68710, L_0x2c68980, C4<1>; -L_0x2c69850 .delay (10000,10000,10000) L_0x2c69850/d; -L_0x2c69970/d .functor NAND 1, L_0x2c685e0, L_0x2c68710, L_0x2c68a70, C4<1>; -L_0x2c69970 .delay (10000,10000,10000) L_0x2c69970/d; -L_0x2c69ae0/d .functor NAND 1, L_0x2c69620, L_0x2c69760, L_0x2c69850, L_0x2c69970; -L_0x2c69ae0 .delay (10000,10000,10000) L_0x2c69ae0/d; -v0x29559d0_0 .net "S0", 0 0, L_0x2c685e0; 1 drivers -v0x2957ff0_0 .net "S1", 0 0, L_0x2c68710; 1 drivers -v0x2958070_0 .net "in0", 0 0, L_0x2c68840; 1 drivers -v0x2957d90_0 .net "in1", 0 0, L_0x2c688e0; 1 drivers -v0x2957e30_0 .net "in2", 0 0, L_0x2c68980; 1 drivers -v0x2956f30_0 .net "in3", 0 0, L_0x2c68a70; 1 drivers -v0x2956fd0_0 .net "nS0", 0 0, L_0x2c69490; 1 drivers -v0x295a470_0 .net "nS1", 0 0, L_0x2c69580; 1 drivers -v0x295a1f0_0 .net "out", 0 0, L_0x2c69ae0; 1 drivers -v0x295a290_0 .net "out0", 0 0, L_0x2c69620; 1 drivers -v0x2959390_0 .net "out1", 0 0, L_0x2c69760; 1 drivers -v0x2959430_0 .net "out2", 0 0, L_0x2c69850; 1 drivers -v0x295c940_0 .net "out3", 0 0, L_0x2c69970; 1 drivers -S_0x2950210 .scope module, "TwoMux" "TwoInMux" 3 294, 3 8, S_0x2951070; - .timescale -9 -12; -L_0x295a4f0/d .functor NOT 1, L_0x2c68fb0, C4<0>, C4<0>, C4<0>; -L_0x295a4f0 .delay (10000,10000,10000) L_0x295a4f0/d; -L_0x2c68bf0/d .functor AND 1, L_0x2c69050, L_0x295a4f0, C4<1>, C4<1>; -L_0x2c68bf0 .delay (20000,20000,20000) L_0x2c68bf0/d; -L_0x2c68ce0/d .functor AND 1, L_0x2c69140, L_0x2c68fb0, C4<1>, C4<1>; -L_0x2c68ce0 .delay (20000,20000,20000) L_0x2c68ce0/d; -L_0x2c68dd0/d .functor OR 1, L_0x2c68bf0, L_0x2c68ce0, C4<0>, C4<0>; -L_0x2c68dd0 .delay (20000,20000,20000) L_0x2c68dd0/d; -v0x2953730_0 .net "S", 0 0, L_0x2c68fb0; 1 drivers -v0x29537d0_0 .net "in0", 0 0, L_0x2c69050; 1 drivers -v0x29534d0_0 .net "in1", 0 0, L_0x2c69140; 1 drivers -v0x2953570_0 .net "nS", 0 0, L_0x295a4f0; 1 drivers -v0x2952690_0 .net "out0", 0 0, L_0x2c68bf0; 1 drivers -v0x2955b90_0 .net "out1", 0 0, L_0x2c68ce0; 1 drivers -v0x2955930_0 .net "outfinal", 0 0, L_0x2c68dd0; 1 drivers -S_0x293b7d0 .scope generate, "muxbits[24]" "muxbits[24]" 3 290, 3 290, S_0x29738d0; - .timescale -9 -12; -P_0x292ba28 .param/l "i" 3 290, +C4<011000>; -L_0x2c6b960/d .functor OR 1, L_0x2c6baa0, L_0x2c6bb40, C4<0>, C4<0>; -L_0x2c6b960 .delay (20000,20000,20000) L_0x2c6b960/d; -v0x294de50_0 .net *"_s15", 0 0, L_0x2c6baa0; 1 drivers -v0x29512d0_0 .net *"_s16", 0 0, L_0x2c6bb40; 1 drivers -S_0x294a540 .scope module, "ZeroMux" "FourInMux" 3 292, 3 24, S_0x293b7d0; - .timescale -9 -12; -L_0x2c69e80/d .functor NOT 1, L_0x2c6a720, C4<0>, C4<0>, C4<0>; -L_0x2c69e80 .delay (10000,10000,10000) L_0x2c69e80/d; -L_0x2c69f70/d .functor NOT 1, L_0x2c6a850, C4<0>, C4<0>, C4<0>; -L_0x2c69f70 .delay (10000,10000,10000) L_0x2c69f70/d; -L_0x2c6a010/d .functor NAND 1, L_0x2c69e80, L_0x2c69f70, L_0x2c6a980, C4<1>; -L_0x2c6a010 .delay (10000,10000,10000) L_0x2c6a010/d; -L_0x2c6a150/d .functor NAND 1, L_0x2c6a720, L_0x2c69f70, L_0x2c6aa20, C4<1>; -L_0x2c6a150 .delay (10000,10000,10000) L_0x2c6a150/d; -L_0x2c6a240/d .functor NAND 1, L_0x2c69e80, L_0x2c6a850, L_0x2c6aac0, C4<1>; -L_0x2c6a240 .delay (10000,10000,10000) L_0x2c6a240/d; -L_0x2c6a330/d .functor NAND 1, L_0x2c6a720, L_0x2c6a850, L_0x2c6abb0, C4<1>; -L_0x2c6a330 .delay (10000,10000,10000) L_0x2c6a330/d; -L_0x2c6a470/d .functor NAND 1, L_0x2c6a010, L_0x2c6a150, L_0x2c6a240, L_0x2c6a330; -L_0x2c6a470 .delay (10000,10000,10000) L_0x2c6a470/d; -v0x294a2e0_0 .net "S0", 0 0, L_0x2c6a720; 1 drivers -v0x2949450_0 .net "S1", 0 0, L_0x2c6a850; 1 drivers -v0x29494f0_0 .net "in0", 0 0, L_0x2c6a980; 1 drivers -v0x294c9f0_0 .net "in1", 0 0, L_0x2c6aa20; 1 drivers -v0x294ca70_0 .net "in2", 0 0, L_0x2c6aac0; 1 drivers -v0x294c790_0 .net "in3", 0 0, L_0x2c6abb0; 1 drivers -v0x294c830_0 .net "nS0", 0 0, L_0x2c69e80; 1 drivers -v0x294b900_0 .net "nS1", 0 0, L_0x2c69f70; 1 drivers -v0x294b9a0_0 .net "out", 0 0, L_0x2c6a470; 1 drivers -v0x294ee70_0 .net "out0", 0 0, L_0x2c6a010; 1 drivers -v0x294eef0_0 .net "out1", 0 0, L_0x2c6a150; 1 drivers -v0x294ec10_0 .net "out2", 0 0, L_0x2c6a240; 1 drivers -v0x294ddb0_0 .net "out3", 0 0, L_0x2c6a330; 1 drivers -S_0x2943730 .scope module, "OneMux" "FourInMux" 3 293, 3 24, S_0x293b7d0; - .timescale -9 -12; -L_0x2c69410/d .functor NOT 1, L_0x2c6c510, C4<0>, C4<0>, C4<0>; -L_0x2c69410 .delay (10000,10000,10000) L_0x2c69410/d; -L_0x2c6bd30/d .functor NOT 1, L_0x2c6ad40, C4<0>, C4<0>, C4<0>; -L_0x2c6bd30 .delay (10000,10000,10000) L_0x2c6bd30/d; -L_0x2c6bdd0/d .functor NAND 1, L_0x2c69410, L_0x2c6bd30, L_0x2c6ae70, C4<1>; -L_0x2c6bdd0 .delay (10000,10000,10000) L_0x2c6bdd0/d; -L_0x2c6bf10/d .functor NAND 1, L_0x2c6c510, L_0x2c6bd30, L_0x2c6af10, C4<1>; -L_0x2c6bf10 .delay (10000,10000,10000) L_0x2c6bf10/d; -L_0x2c6c000/d .functor NAND 1, L_0x2c69410, L_0x2c6ad40, L_0x2c6afb0, C4<1>; -L_0x2c6c000 .delay (10000,10000,10000) L_0x2c6c000/d; -L_0x2c6c0f0/d .functor NAND 1, L_0x2c6c510, L_0x2c6ad40, L_0x2c6b0a0, C4<1>; -L_0x2c6c0f0 .delay (10000,10000,10000) L_0x2c6c0f0/d; -L_0x2c6c260/d .functor NAND 1, L_0x2c6bdd0, L_0x2c6bf10, L_0x2c6c000, L_0x2c6c0f0; -L_0x2c6c260 .delay (10000,10000,10000) L_0x2c6c260/d; -v0x29434d0_0 .net "S0", 0 0, L_0x2c6c510; 1 drivers -v0x2943570_0 .net "S1", 0 0, L_0x2c6ad40; 1 drivers -v0x2942640_0 .net "in0", 0 0, L_0x2c6ae70; 1 drivers -v0x29426e0_0 .net "in1", 0 0, L_0x2c6af10; 1 drivers -v0x2945be0_0 .net "in2", 0 0, L_0x2c6afb0; 1 drivers -v0x2945c80_0 .net "in3", 0 0, L_0x2c6b0a0; 1 drivers -v0x29459e0_0 .net "nS0", 0 0, L_0x2c69410; 1 drivers -v0x2944af0_0 .net "nS1", 0 0, L_0x2c6bd30; 1 drivers -v0x2944b70_0 .net "out", 0 0, L_0x2c6c260; 1 drivers -v0x2948090_0 .net "out0", 0 0, L_0x2c6bdd0; 1 drivers -v0x2948130_0 .net "out1", 0 0, L_0x2c6bf10; 1 drivers -v0x2947e50_0 .net "out2", 0 0, L_0x2c6c000; 1 drivers -v0x2946fc0_0 .net "out3", 0 0, L_0x2c6c0f0; 1 drivers -S_0x293edd0 .scope module, "TwoMux" "TwoInMux" 3 294, 3 8, S_0x293b7d0; - .timescale -9 -12; -L_0x2c6b190/d .functor NOT 1, L_0x2c6b640, C4<0>, C4<0>, C4<0>; -L_0x2c6b190 .delay (10000,10000,10000) L_0x2c6b190/d; -L_0x2c6b280/d .functor AND 1, L_0x2c6b6e0, L_0x2c6b190, C4<1>, C4<1>; -L_0x2c6b280 .delay (20000,20000,20000) L_0x2c6b280/d; -L_0x2c6b370/d .functor AND 1, L_0x2c6b7d0, L_0x2c6b640, C4<1>, C4<1>; -L_0x2c6b370 .delay (20000,20000,20000) L_0x2c6b370/d; -L_0x2c6b460/d .functor OR 1, L_0x2c6b280, L_0x2c6b370, C4<0>, C4<0>; -L_0x2c6b460 .delay (20000,20000,20000) L_0x2c6b460/d; -v0x293eb70_0 .net "S", 0 0, L_0x2c6b640; 1 drivers -v0x293ec10_0 .net "in0", 0 0, L_0x2c6b6e0; 1 drivers -v0x2941280_0 .net "in1", 0 0, L_0x2c6b7d0; 1 drivers -v0x2941320_0 .net "nS", 0 0, L_0x2c6b190; 1 drivers -v0x2941020_0 .net "out0", 0 0, L_0x2c6b280; 1 drivers -v0x29410c0_0 .net "out1", 0 0, L_0x2c6b370; 1 drivers -v0x29401f0_0 .net "outfinal", 0 0, L_0x2c6b460; 1 drivers -S_0x292a320 .scope generate, "muxbits[25]" "muxbits[25]" 3 290, 3 290, S_0x29738d0; - .timescale -9 -12; -P_0x291ebb8 .param/l "i" 3 290, +C4<011001>; -L_0x2be0ef0/d .functor OR 1, L_0x2be1030, L_0x2be10d0, C4<0>, C4<0>; -L_0x2be0ef0 .delay (20000,20000,20000) L_0x2be0ef0/d; -v0x293c930_0 .net *"_s15", 0 0, L_0x2be1030; 1 drivers -v0x293c650_0 .net *"_s16", 0 0, L_0x2be10d0; 1 drivers -S_0x2935910 .scope module, "ZeroMux" "FourInMux" 3 292, 3 24, S_0x292a320; - .timescale -9 -12; -L_0x2c6bc30/d .functor NOT 1, L_0x2c6ce80, C4<0>, C4<0>, C4<0>; -L_0x2c6bc30 .delay (10000,10000,10000) L_0x2c6bc30/d; -L_0x2c6c6d0/d .functor NOT 1, L_0x2c6cfb0, C4<0>, C4<0>, C4<0>; -L_0x2c6c6d0 .delay (10000,10000,10000) L_0x2c6c6d0/d; -L_0x2c6c770/d .functor NAND 1, L_0x2c6bc30, L_0x2c6c6d0, L_0x2c6d0e0, C4<1>; -L_0x2c6c770 .delay (10000,10000,10000) L_0x2c6c770/d; -L_0x2c6c8b0/d .functor NAND 1, L_0x2c6ce80, L_0x2c6c6d0, L_0x2c6d180, C4<1>; -L_0x2c6c8b0 .delay (10000,10000,10000) L_0x2c6c8b0/d; -L_0x2c6c9a0/d .functor NAND 1, L_0x2c6bc30, L_0x2c6cfb0, L_0x2c6d220, C4<1>; -L_0x2c6c9a0 .delay (10000,10000,10000) L_0x2c6c9a0/d; -L_0x2c6ca90/d .functor NAND 1, L_0x2c6ce80, L_0x2c6cfb0, L_0x2c6d310, C4<1>; -L_0x2c6ca90 .delay (10000,10000,10000) L_0x2c6ca90/d; -L_0x2c6cbd0/d .functor NAND 1, L_0x2c6c770, L_0x2c6c8b0, L_0x2c6c9a0, L_0x2c6ca90; -L_0x2c6cbd0 .delay (10000,10000,10000) L_0x2c6cbd0/d; -v0x2934ab0_0 .net "S0", 0 0, L_0x2c6ce80; 1 drivers -v0x2934b50_0 .net "S1", 0 0, L_0x2c6cfb0; 1 drivers -v0x2937fd0_0 .net "in0", 0 0, L_0x2c6d0e0; 1 drivers -v0x2938070_0 .net "in1", 0 0, L_0x2c6d180; 1 drivers -v0x2937d70_0 .net "in2", 0 0, L_0x2c6d220; 1 drivers -v0x2937e10_0 .net "in3", 0 0, L_0x2c6d310; 1 drivers -v0x2936f30_0 .net "nS0", 0 0, L_0x2c6bc30; 1 drivers -v0x293a430_0 .net "nS1", 0 0, L_0x2c6c6d0; 1 drivers -v0x293a4d0_0 .net "out", 0 0, L_0x2c6cbd0; 1 drivers -v0x293a1d0_0 .net "out0", 0 0, L_0x2c6c770; 1 drivers -v0x293a270_0 .net "out1", 0 0, L_0x2c6c8b0; 1 drivers -v0x2939370_0 .net "out2", 0 0, L_0x2c6c9a0; 1 drivers -v0x293c890_0 .net "out3", 0 0, L_0x2c6ca90; 1 drivers -S_0x292dd90 .scope module, "OneMux" "FourInMux" 3 293, 3 24, S_0x292a320; - .timescale -9 -12; -L_0x2c6d400/d .functor NOT 1, L_0x2be2200, C4<0>, C4<0>, C4<0>; -L_0x2c6d400 .delay (10000,10000,10000) L_0x2c6d400/d; -L_0x2c6d4f0/d .functor NOT 1, L_0x2be2330, C4<0>, C4<0>, C4<0>; -L_0x2c6d4f0 .delay (10000,10000,10000) L_0x2c6d4f0/d; -L_0x2be1ae0/d .functor NAND 1, L_0x2c6d400, L_0x2c6d4f0, L_0x2be2460, C4<1>; -L_0x2be1ae0 .delay (10000,10000,10000) L_0x2be1ae0/d; -L_0x2be1bd0/d .functor NAND 1, L_0x2be2200, L_0x2c6d4f0, L_0x2be2500, C4<1>; -L_0x2be1bd0 .delay (10000,10000,10000) L_0x2be1bd0/d; -L_0x2be1cc0/d .functor NAND 1, L_0x2c6d400, L_0x2be2330, L_0x2be25a0, C4<1>; -L_0x2be1cc0 .delay (10000,10000,10000) L_0x2be1cc0/d; -L_0x2be1de0/d .functor NAND 1, L_0x2be2200, L_0x2be2330, L_0x2be2690, C4<1>; -L_0x2be1de0 .delay (10000,10000,10000) L_0x2be1de0/d; -L_0x2be1f50/d .functor NAND 1, L_0x2be1ae0, L_0x2be1bd0, L_0x2be1cc0, L_0x2be1de0; -L_0x2be1f50 .delay (10000,10000,10000) L_0x2be1f50/d; -v0x292ec90_0 .net "S0", 0 0, L_0x2be2200; 1 drivers -v0x29312b0_0 .net "S1", 0 0, L_0x2be2330; 1 drivers -v0x2931330_0 .net "in0", 0 0, L_0x2be2460; 1 drivers -v0x2931050_0 .net "in1", 0 0, L_0x2be2500; 1 drivers -v0x29310f0_0 .net "in2", 0 0, L_0x2be25a0; 1 drivers -v0x29301f0_0 .net "in3", 0 0, L_0x2be2690; 1 drivers -v0x2930290_0 .net "nS0", 0 0, L_0x2c6d400; 1 drivers -v0x2933730_0 .net "nS1", 0 0, L_0x2c6d4f0; 1 drivers -v0x29334b0_0 .net "out", 0 0, L_0x2be1f50; 1 drivers -v0x2933550_0 .net "out0", 0 0, L_0x2be1ae0; 1 drivers -v0x2932650_0 .net "out1", 0 0, L_0x2be1bd0; 1 drivers -v0x29326f0_0 .net "out2", 0 0, L_0x2be1cc0; 1 drivers -v0x2935c00_0 .net "out3", 0 0, L_0x2be1de0; 1 drivers -S_0x2929490 .scope module, "TwoMux" "TwoInMux" 3 294, 3 8, S_0x292a320; - .timescale -9 -12; -L_0x29337b0/d .functor NOT 1, L_0x2be0bd0, C4<0>, C4<0>, C4<0>; -L_0x29337b0 .delay (10000,10000,10000) L_0x29337b0/d; -L_0x2be2810/d .functor AND 1, L_0x2be0c70, L_0x29337b0, C4<1>, C4<1>; -L_0x2be2810 .delay (20000,20000,20000) L_0x2be2810/d; -L_0x2be2900/d .functor AND 1, L_0x2be0d60, L_0x2be0bd0, C4<1>, C4<1>; -L_0x2be2900 .delay (20000,20000,20000) L_0x2be2900/d; -L_0x2be29f0/d .functor OR 1, L_0x2be2810, L_0x2be2900, C4<0>, C4<0>; -L_0x2be29f0 .delay (20000,20000,20000) L_0x2be29f0/d; -v0x292ca30_0 .net "S", 0 0, L_0x2be0bd0; 1 drivers -v0x292cad0_0 .net "in0", 0 0, L_0x2be0c70; 1 drivers -v0x292c7d0_0 .net "in1", 0 0, L_0x2be0d60; 1 drivers -v0x292c870_0 .net "nS", 0 0, L_0x29337b0; 1 drivers -v0x292b960_0 .net "out0", 0 0, L_0x2be2810; 1 drivers -v0x292ee50_0 .net "out1", 0 0, L_0x2be2900; 1 drivers -v0x292ebf0_0 .net "outfinal", 0 0, L_0x2be29f0; 1 drivers -S_0x2918fd0 .scope generate, "muxbits[26]" "muxbits[26]" 3 290, 3 290, S_0x29738d0; - .timescale -9 -12; -P_0x290fcd8 .param/l "i" 3 290, +C4<011010>; -L_0x2c72bf0/d .functor OR 1, L_0x2c72d30, L_0x2c72dd0, C4<0>, C4<0>; -L_0x2c72bf0 .delay (20000,20000,20000) L_0x2c72bf0/d; -v0x2927080_0 .net *"_s15", 0 0, L_0x2c72d30; 1 drivers -v0x292a580_0 .net *"_s16", 0 0, L_0x2c72dd0; 1 drivers -S_0x2923770 .scope module, "ZeroMux" "FourInMux" 3 292, 3 24, S_0x2918fd0; - .timescale -9 -12; -L_0x2be11c0/d .functor NOT 1, L_0x2c72670, C4<0>, C4<0>, C4<0>; -L_0x2be11c0 .delay (10000,10000,10000) L_0x2be11c0/d; -L_0x2be12b0/d .functor NOT 1, L_0x2c727a0, C4<0>, C4<0>, C4<0>; -L_0x2be12b0 .delay (10000,10000,10000) L_0x2be12b0/d; -L_0x2be1350/d .functor NAND 1, L_0x2be11c0, L_0x2be12b0, L_0x2c715f0, C4<1>; -L_0x2be1350 .delay (10000,10000,10000) L_0x2be1350/d; -L_0x2be1490/d .functor NAND 1, L_0x2c72670, L_0x2be12b0, L_0x2c71690, C4<1>; -L_0x2be1490 .delay (10000,10000,10000) L_0x2be1490/d; -L_0x2be1580/d .functor NAND 1, L_0x2be11c0, L_0x2c727a0, L_0x2c71730, C4<1>; -L_0x2be1580 .delay (10000,10000,10000) L_0x2be1580/d; -L_0x2be1670/d .functor NAND 1, L_0x2c72670, L_0x2c727a0, L_0x2c71820, C4<1>; -L_0x2be1670 .delay (10000,10000,10000) L_0x2be1670/d; -L_0x2be17b0/d .functor NAND 1, L_0x2be1350, L_0x2be1490, L_0x2be1580, L_0x2be1670; -L_0x2be17b0 .delay (10000,10000,10000) L_0x2be17b0/d; -v0x2923510_0 .net "S0", 0 0, L_0x2c72670; 1 drivers -v0x2922680_0 .net "S1", 0 0, L_0x2c727a0; 1 drivers -v0x2922720_0 .net "in0", 0 0, L_0x2c715f0; 1 drivers -v0x2925c20_0 .net "in1", 0 0, L_0x2c71690; 1 drivers -v0x2925ca0_0 .net "in2", 0 0, L_0x2c71730; 1 drivers -v0x29259c0_0 .net "in3", 0 0, L_0x2c71820; 1 drivers -v0x2925a60_0 .net "nS0", 0 0, L_0x2be11c0; 1 drivers -v0x2924b30_0 .net "nS1", 0 0, L_0x2be12b0; 1 drivers -v0x2924bd0_0 .net "out", 0 0, L_0x2be17b0; 1 drivers -v0x29280d0_0 .net "out0", 0 0, L_0x2be1350; 1 drivers -v0x2928150_0 .net "out1", 0 0, L_0x2be1490; 1 drivers -v0x2927e70_0 .net "out2", 0 0, L_0x2be1580; 1 drivers -v0x2926fe0_0 .net "out3", 0 0, L_0x2be1670; 1 drivers -S_0x291c8f0 .scope module, "OneMux" "FourInMux" 3 293, 3 24, S_0x2918fd0; - .timescale -9 -12; -L_0x2c71910/d .functor NOT 1, L_0x2c721e0, C4<0>, C4<0>, C4<0>; -L_0x2c71910 .delay (10000,10000,10000) L_0x2c71910/d; -L_0x2c71a00/d .functor NOT 1, L_0x2c72310, C4<0>, C4<0>, C4<0>; -L_0x2c71a00 .delay (10000,10000,10000) L_0x2c71a00/d; -L_0x2c71aa0/d .functor NAND 1, L_0x2c71910, L_0x2c71a00, L_0x2c72440, C4<1>; -L_0x2c71aa0 .delay (10000,10000,10000) L_0x2c71aa0/d; -L_0x2c71be0/d .functor NAND 1, L_0x2c721e0, L_0x2c71a00, L_0x2c724e0, C4<1>; -L_0x2c71be0 .delay (10000,10000,10000) L_0x2c71be0/d; -L_0x2c71cd0/d .functor NAND 1, L_0x2c71910, L_0x2c72310, L_0x2c72580, C4<1>; -L_0x2c71cd0 .delay (10000,10000,10000) L_0x2c71cd0/d; -L_0x2c71dc0/d .functor NAND 1, L_0x2c721e0, L_0x2c72310, L_0x2c739b0, C4<1>; -L_0x2c71dc0 .delay (10000,10000,10000) L_0x2c71dc0/d; -L_0x2c71f30/d .functor NAND 1, L_0x2c71aa0, L_0x2c71be0, L_0x2c71cd0, L_0x2c71dc0; -L_0x2c71f30 .delay (10000,10000,10000) L_0x2c71f30/d; -v0x291c630_0 .net "S0", 0 0, L_0x2c721e0; 1 drivers -v0x291c6d0_0 .net "S1", 0 0, L_0x2c72310; 1 drivers -v0x291b7d0_0 .net "in0", 0 0, L_0x2c72440; 1 drivers -v0x291b870_0 .net "in1", 0 0, L_0x2c724e0; 1 drivers -v0x291ee10_0 .net "in2", 0 0, L_0x2c72580; 1 drivers -v0x291eeb0_0 .net "in3", 0 0, L_0x2c739b0; 1 drivers -v0x291ec10_0 .net "nS0", 0 0, L_0x2c71910; 1 drivers -v0x291dd20_0 .net "nS1", 0 0, L_0x2c71a00; 1 drivers -v0x291dda0_0 .net "out", 0 0, L_0x2c71f30; 1 drivers -v0x29212c0_0 .net "out0", 0 0, L_0x2c71aa0; 1 drivers -v0x2921360_0 .net "out1", 0 0, L_0x2c71be0; 1 drivers -v0x2921080_0 .net "out2", 0 0, L_0x2c71cd0; 1 drivers -v0x29201f0_0 .net "out3", 0 0, L_0x2c71dc0; 1 drivers -S_0x2918d70 .scope module, "TwoMux" "TwoInMux" 3 294, 3 8, S_0x2918fd0; - .timescale -9 -12; -L_0x2c73a50/d .functor NOT 1, L_0x2c728d0, C4<0>, C4<0>, C4<0>; -L_0x2c73a50 .delay (10000,10000,10000) L_0x2c73a50/d; -L_0x2c73b40/d .functor AND 1, L_0x2c72970, L_0x2c73a50, C4<1>, C4<1>; -L_0x2c73b40 .delay (20000,20000,20000) L_0x2c73b40/d; -L_0x2c73c30/d .functor AND 1, L_0x2c72a60, L_0x2c728d0, C4<1>, C4<1>; -L_0x2c73c30 .delay (20000,20000,20000) L_0x2c73c30/d; -L_0x2c73d20/d .functor OR 1, L_0x2c73b40, L_0x2c73c30, C4<0>, C4<0>; -L_0x2c73d20 .delay (20000,20000,20000) L_0x2c73d20/d; -v0x29188d0_0 .net "S", 0 0, L_0x2c728d0; 1 drivers -v0x2918970_0 .net "in0", 0 0, L_0x2c72970; 1 drivers -v0x2963680_0 .net "in1", 0 0, L_0x2c72a60; 1 drivers -v0x2963720_0 .net "nS", 0 0, L_0x2c73a50; 1 drivers -v0x2963430_0 .net "out0", 0 0, L_0x2c73b40; 1 drivers -v0x29634d0_0 .net "out1", 0 0, L_0x2c73c30; 1 drivers -v0x2962610_0 .net "outfinal", 0 0, L_0x2c73d20; 1 drivers -S_0x290cf50 .scope generate, "muxbits[27]" "muxbits[27]" 3 290, 3 290, S_0x29738d0; - .timescale -9 -12; -P_0x2903cf8 .param/l "i" 3 290, +C4<011011>; -L_0x2c753e0/d .functor OR 1, L_0x2c754e0, L_0x2c75580, C4<0>, C4<0>; -L_0x2c753e0 .delay (20000,20000,20000) L_0x2c753e0/d; -v0x29178f0_0 .net *"_s15", 0 0, L_0x2c754e0; 1 drivers -v0x29173d0_0 .net *"_s16", 0 0, L_0x2c75580; 1 drivers -S_0x2913450 .scope module, "ZeroMux" "FourInMux" 3 292, 3 24, S_0x290cf50; - .timescale -9 -12; -L_0x2c72ec0/d .functor NOT 1, L_0x2c73760, C4<0>, C4<0>, C4<0>; -L_0x2c72ec0 .delay (10000,10000,10000) L_0x2c72ec0/d; -L_0x2c72fb0/d .functor NOT 1, L_0x2c73890, C4<0>, C4<0>, C4<0>; -L_0x2c72fb0 .delay (10000,10000,10000) L_0x2c72fb0/d; -L_0x2c73050/d .functor NAND 1, L_0x2c72ec0, L_0x2c72fb0, L_0x2c750c0, C4<1>; -L_0x2c73050 .delay (10000,10000,10000) L_0x2c73050/d; -L_0x2c73190/d .functor NAND 1, L_0x2c73760, L_0x2c72fb0, L_0x2c73f00, C4<1>; -L_0x2c73190 .delay (10000,10000,10000) L_0x2c73190/d; -L_0x2c73280/d .functor NAND 1, L_0x2c72ec0, L_0x2c73890, L_0x2c73fa0, C4<1>; -L_0x2c73280 .delay (10000,10000,10000) L_0x2c73280/d; -L_0x2c73370/d .functor NAND 1, L_0x2c73760, L_0x2c73890, L_0x2c74090, C4<1>; -L_0x2c73370 .delay (10000,10000,10000) L_0x2c73370/d; -L_0x2c734b0/d .functor NAND 1, L_0x2c73050, L_0x2c73190, L_0x2c73280, L_0x2c73370; -L_0x2c734b0 .delay (10000,10000,10000) L_0x2c734b0/d; -v0x2915070_0 .net "S0", 0 0, L_0x2c73760; 1 drivers -v0x2915110_0 .net "S1", 0 0, L_0x2c73890; 1 drivers -v0x2914e10_0 .net "in0", 0 0, L_0x2c750c0; 1 drivers -v0x2914eb0_0 .net "in1", 0 0, L_0x2c73f00; 1 drivers -v0x2914970_0 .net "in2", 0 0, L_0x2c73fa0; 1 drivers -v0x2914a10_0 .net "in3", 0 0, L_0x2c74090; 1 drivers -v0x29165b0_0 .net "nS0", 0 0, L_0x2c72ec0; 1 drivers -v0x2916330_0 .net "nS1", 0 0, L_0x2c72fb0; 1 drivers -v0x29163d0_0 .net "out", 0 0, L_0x2c734b0; 1 drivers -v0x2915e90_0 .net "out0", 0 0, L_0x2c73050; 1 drivers -v0x2915f30_0 .net "out1", 0 0, L_0x2c73190; 1 drivers -v0x2917ab0_0 .net "out2", 0 0, L_0x2c73280; 1 drivers -v0x2917850_0 .net "out3", 0 0, L_0x2c73370; 1 drivers -S_0x2911110 .scope module, "OneMux" "FourInMux" 3 293, 3 24, S_0x290cf50; - .timescale -9 -12; -L_0x2c74180/d .functor NOT 1, L_0x2c74a40, C4<0>, C4<0>, C4<0>; -L_0x2c74180 .delay (10000,10000,10000) L_0x2c74180/d; -L_0x2c74230/d .functor NOT 1, L_0x2c74b70, C4<0>, C4<0>, C4<0>; -L_0x2c74230 .delay (10000,10000,10000) L_0x2c74230/d; -L_0x2c742d0/d .functor NAND 1, L_0x2c74180, L_0x2c74230, L_0x2c74ca0, C4<1>; -L_0x2c742d0 .delay (10000,10000,10000) L_0x2c742d0/d; -L_0x2c74410/d .functor NAND 1, L_0x2c74a40, L_0x2c74230, L_0x2c74d40, C4<1>; -L_0x2c74410 .delay (10000,10000,10000) L_0x2c74410/d; -L_0x2c74500/d .functor NAND 1, L_0x2c74180, L_0x2c74b70, L_0x2c74de0, C4<1>; -L_0x2c74500 .delay (10000,10000,10000) L_0x2c74500/d; -L_0x2c74620/d .functor NAND 1, L_0x2c74a40, L_0x2c74b70, L_0x2c74ed0, C4<1>; -L_0x2c74620 .delay (10000,10000,10000) L_0x2c74620/d; -L_0x2c74790/d .functor NAND 1, L_0x2c742d0, L_0x2c74410, L_0x2c74500, L_0x2c74620; -L_0x2c74790 .delay (10000,10000,10000) L_0x2c74790/d; -v0x290f590_0 .net "S0", 0 0, L_0x2c74a40; 1 drivers -v0x2910eb0_0 .net "S1", 0 0, L_0x2c74b70; 1 drivers -v0x2910f30_0 .net "in0", 0 0, L_0x2c74ca0; 1 drivers -v0x2910a10_0 .net "in1", 0 0, L_0x2c74d40; 1 drivers -v0x2910ab0_0 .net "in2", 0 0, L_0x2c74de0; 1 drivers -v0x2912630_0 .net "in3", 0 0, L_0x2c74ed0; 1 drivers -v0x29126d0_0 .net "nS0", 0 0, L_0x2c74180; 1 drivers -v0x29123f0_0 .net "nS1", 0 0, L_0x2c74230; 1 drivers -v0x2911f30_0 .net "out", 0 0, L_0x2c74790; 1 drivers -v0x2911fd0_0 .net "out0", 0 0, L_0x2c742d0; 1 drivers -v0x2913b50_0 .net "out1", 0 0, L_0x2c74410; 1 drivers -v0x2913bf0_0 .net "out2", 0 0, L_0x2c74500; 1 drivers -v0x2913980_0 .net "out3", 0 0, L_0x2c74620; 1 drivers -S_0x290e6d0 .scope module, "TwoMux" "TwoInMux" 3 294, 3 8, S_0x290cf50; - .timescale -9 -12; -L_0x2c74fc0/d .functor NOT 1, L_0x2c766c0, C4<0>, C4<0>, C4<0>; -L_0x2c74fc0 .delay (10000,10000,10000) L_0x2c74fc0/d; -L_0x2c76340/d .functor AND 1, L_0x2c75160, L_0x2c74fc0, C4<1>, C4<1>; -L_0x2c76340 .delay (20000,20000,20000) L_0x2c76340/d; -L_0x2c763f0/d .functor AND 1, L_0x2c75250, L_0x2c766c0, C4<1>, C4<1>; -L_0x2c763f0 .delay (20000,20000,20000) L_0x2c763f0/d; -L_0x2c764e0/d .functor OR 1, L_0x2c76340, L_0x2c763f0, C4<0>, C4<0>; -L_0x2c764e0 .delay (20000,20000,20000) L_0x2c764e0/d; -v0x290e470_0 .net "S", 0 0, L_0x2c766c0; 1 drivers -v0x290e510_0 .net "in0", 0 0, L_0x2c75160; 1 drivers -v0x290dfd0_0 .net "in1", 0 0, L_0x2c75250; 1 drivers -v0x290e070_0 .net "nS", 0 0, L_0x2c74fc0; 1 drivers -v0x290fc10_0 .net "out0", 0 0, L_0x2c76340; 1 drivers -v0x290f990_0 .net "out1", 0 0, L_0x2c763f0; 1 drivers -v0x290f4f0_0 .net "outfinal", 0 0, L_0x2c764e0; 1 drivers -S_0x28fd050 .scope generate, "muxbits[28]" "muxbits[28]" 3 290, 3 290, S_0x29738d0; - .timescale -9 -12; -P_0x28f3d58 .param/l "i" 3 290, +C4<011100>; -L_0x2c77e50/d .functor OR 1, L_0x2c77f90, L_0x2c78030, C4<0>, C4<0>; -L_0x2c77e50 .delay (20000,20000,20000) L_0x2c77e50/d; -v0x290bab0_0 .net *"_s15", 0 0, L_0x2c77f90; 1 drivers -v0x290d1b0_0 .net *"_s16", 0 0, L_0x2c78030; 1 drivers -S_0x2906510 .scope module, "ZeroMux" "FourInMux" 3 292, 3 24, S_0x28fd050; - .timescale -9 -12; -L_0x2c75670/d .functor NOT 1, L_0x2c75f10, C4<0>, C4<0>, C4<0>; -L_0x2c75670 .delay (10000,10000,10000) L_0x2c75670/d; -L_0x2c75760/d .functor NOT 1, L_0x2c76040, C4<0>, C4<0>, C4<0>; -L_0x2c75760 .delay (10000,10000,10000) L_0x2c75760/d; -L_0x2c75800/d .functor NAND 1, L_0x2c75670, L_0x2c75760, L_0x2c76170, C4<1>; -L_0x2c75800 .delay (10000,10000,10000) L_0x2c75800/d; -L_0x2c75940/d .functor NAND 1, L_0x2c75f10, L_0x2c75760, L_0x2c76210, C4<1>; -L_0x2c75940 .delay (10000,10000,10000) L_0x2c75940/d; -L_0x2c75a30/d .functor NAND 1, L_0x2c75670, L_0x2c76040, L_0x2c77950, C4<1>; -L_0x2c75a30 .delay (10000,10000,10000) L_0x2c75a30/d; -L_0x2c75b20/d .functor NAND 1, L_0x2c75f10, L_0x2c76040, L_0x2c77a40, C4<1>; -L_0x2c75b20 .delay (10000,10000,10000) L_0x2c75b20/d; -L_0x2c75c60/d .functor NAND 1, L_0x2c75800, L_0x2c75940, L_0x2c75a30, L_0x2c75b20; -L_0x2c75c60 .delay (10000,10000,10000) L_0x2c75c60/d; -v0x2907cb0_0 .net "S0", 0 0, L_0x2c75f10; 1 drivers -v0x2907a50_0 .net "S1", 0 0, L_0x2c76040; 1 drivers -v0x2907af0_0 .net "in0", 0 0, L_0x2c76170; 1 drivers -v0x29091f0_0 .net "in1", 0 0, L_0x2c76210; 1 drivers -v0x2909270_0 .net "in2", 0 0, L_0x2c77950; 1 drivers -v0x2908f90_0 .net "in3", 0 0, L_0x2c77a40; 1 drivers -v0x2909030_0 .net "nS0", 0 0, L_0x2c75670; 1 drivers -v0x290a730_0 .net "nS1", 0 0, L_0x2c75760; 1 drivers -v0x290a7d0_0 .net "out", 0 0, L_0x2c75c60; 1 drivers -v0x290a4d0_0 .net "out0", 0 0, L_0x2c75800; 1 drivers -v0x290a550_0 .net "out1", 0 0, L_0x2c75940; 1 drivers -v0x290bc70_0 .net "out2", 0 0, L_0x2c75a30; 1 drivers -v0x290ba10_0 .net "out3", 0 0, L_0x2c75b20; 1 drivers -S_0x2901270 .scope module, "OneMux" "FourInMux" 3 293, 3 24, S_0x28fd050; - .timescale -9 -12; -L_0x2c75b80/d .functor NOT 1, L_0x2c76ff0, C4<0>, C4<0>, C4<0>; -L_0x2c75b80 .delay (10000,10000,10000) L_0x2c75b80/d; -L_0x2c767b0/d .functor NOT 1, L_0x2c77120, C4<0>, C4<0>, C4<0>; -L_0x2c767b0 .delay (10000,10000,10000) L_0x2c767b0/d; -L_0x2c76850/d .functor NAND 1, L_0x2c75b80, L_0x2c767b0, L_0x2c77250, C4<1>; -L_0x2c76850 .delay (10000,10000,10000) L_0x2c76850/d; -L_0x2c76990/d .functor NAND 1, L_0x2c76ff0, L_0x2c767b0, L_0x2c772f0, C4<1>; -L_0x2c76990 .delay (10000,10000,10000) L_0x2c76990/d; -L_0x2c76a80/d .functor NAND 1, L_0x2c75b80, L_0x2c77120, L_0x2c77390, C4<1>; -L_0x2c76a80 .delay (10000,10000,10000) L_0x2c76a80/d; -L_0x2c76bd0/d .functor NAND 1, L_0x2c76ff0, L_0x2c77120, L_0x2c77480, C4<1>; -L_0x2c76bd0 .delay (10000,10000,10000) L_0x2c76bd0/d; -L_0x2c76d40/d .functor NAND 1, L_0x2c76850, L_0x2c76990, L_0x2c76a80, L_0x2c76bd0; -L_0x2c76d40 .delay (10000,10000,10000) L_0x2c76d40/d; -v0x2901010_0 .net "S0", 0 0, L_0x2c76ff0; 1 drivers -v0x29010b0_0 .net "S1", 0 0, L_0x2c77120; 1 drivers -v0x29027b0_0 .net "in0", 0 0, L_0x2c77250; 1 drivers -v0x2902850_0 .net "in1", 0 0, L_0x2c772f0; 1 drivers -v0x2902550_0 .net "in2", 0 0, L_0x2c77390; 1 drivers -v0x29025f0_0 .net "in3", 0 0, L_0x2c77480; 1 drivers -v0x2903d50_0 .net "nS0", 0 0, L_0x2c75b80; 1 drivers -v0x2903a90_0 .net "nS1", 0 0, L_0x2c767b0; 1 drivers -v0x2903b10_0 .net "out", 0 0, L_0x2c76d40; 1 drivers -v0x2905230_0 .net "out0", 0 0, L_0x2c76850; 1 drivers -v0x29052d0_0 .net "out1", 0 0, L_0x2c76990; 1 drivers -v0x2904ff0_0 .net "out2", 0 0, L_0x2c76a80; 1 drivers -v0x2906790_0 .net "out3", 0 0, L_0x2c76bd0; 1 drivers -S_0x28fcbb0 .scope module, "TwoMux" "TwoInMux" 3 294, 3 8, S_0x28fd050; - .timescale -9 -12; -L_0x2c77570/d .functor NOT 1, L_0x2c77b30, C4<0>, C4<0>, C4<0>; -L_0x2c77570 .delay (10000,10000,10000) L_0x2c77570/d; -L_0x2c77660/d .functor AND 1, L_0x2c77bd0, L_0x2c77570, C4<1>, C4<1>; -L_0x2c77660 .delay (20000,20000,20000) L_0x2c77660/d; -L_0x2c77750/d .functor AND 1, L_0x2c77cc0, L_0x2c77b30, C4<1>, C4<1>; -L_0x2c77750 .delay (20000,20000,20000) L_0x2c77750/d; -L_0x2c77840/d .functor OR 1, L_0x2c77660, L_0x2c77750, C4<0>, C4<0>; -L_0x2c77840 .delay (20000,20000,20000) L_0x2c77840/d; -v0x28fe7f0_0 .net "S", 0 0, L_0x2c77b30; 1 drivers -v0x28fe890_0 .net "in0", 0 0, L_0x2c77bd0; 1 drivers -v0x28fe590_0 .net "in1", 0 0, L_0x2c77cc0; 1 drivers -v0x28fe630_0 .net "nS", 0 0, L_0x2c77570; 1 drivers -v0x28ffd30_0 .net "out0", 0 0, L_0x2c77660; 1 drivers -v0x28ffdd0_0 .net "out1", 0 0, L_0x2c77750; 1 drivers -v0x28ffb30_0 .net "outfinal", 0 0, L_0x2c77840; 1 drivers -S_0x28f1160 .scope generate, "muxbits[29]" "muxbits[29]" 3 290, 3 290, S_0x29738d0; - .timescale -9 -12; -P_0x28dc518 .param/l "i" 3 290, +C4<011101>; -L_0x2c7a4a0/d .functor OR 1, L_0x2c7a5a0, L_0x2c7a640, C4<0>, C4<0>; -L_0x2c7a4a0 .delay (20000,20000,20000) L_0x2c7a4a0/d; -v0x28fb730_0 .net *"_s15", 0 0, L_0x2c7a5a0; 1 drivers -v0x28fd2d0_0 .net *"_s16", 0 0, L_0x2c7a640; 1 drivers -S_0x28f9350 .scope module, "ZeroMux" "FourInMux" 3 292, 3 24, S_0x28f1160; - .timescale -9 -12; -L_0x2c78120/d .functor NOT 1, L_0x2c789f0, C4<0>, C4<0>, C4<0>; -L_0x2c78120 .delay (10000,10000,10000) L_0x2c78120/d; -L_0x2c78210/d .functor NOT 1, L_0x2c78b20, C4<0>, C4<0>, C4<0>; -L_0x2c78210 .delay (10000,10000,10000) L_0x2c78210/d; -L_0x2c782b0/d .functor NAND 1, L_0x2c78120, L_0x2c78210, L_0x2c78c50, C4<1>; -L_0x2c782b0 .delay (10000,10000,10000) L_0x2c782b0/d; -L_0x2c783f0/d .functor NAND 1, L_0x2c789f0, L_0x2c78210, L_0x2c7a0e0, C4<1>; -L_0x2c783f0 .delay (10000,10000,10000) L_0x2c783f0/d; -L_0x2c784e0/d .functor NAND 1, L_0x2c78120, L_0x2c78b20, L_0x2c7a180, C4<1>; -L_0x2c784e0 .delay (10000,10000,10000) L_0x2c784e0/d; -L_0x2c785d0/d .functor NAND 1, L_0x2c789f0, L_0x2c78b20, L_0x2c78e50, C4<1>; -L_0x2c785d0 .delay (10000,10000,10000) L_0x2c785d0/d; -L_0x2c78740/d .functor NAND 1, L_0x2c782b0, L_0x2c783f0, L_0x2c784e0, L_0x2c785d0; -L_0x2c78740 .delay (10000,10000,10000) L_0x2c78740/d; -v0x28f90f0_0 .net "S0", 0 0, L_0x2c789f0; 1 drivers -v0x28f9190_0 .net "S1", 0 0, L_0x2c78b20; 1 drivers -v0x28f8c50_0 .net "in0", 0 0, L_0x2c78c50; 1 drivers -v0x28f8cf0_0 .net "in1", 0 0, L_0x2c7a0e0; 1 drivers -v0x28fa870_0 .net "in2", 0 0, L_0x2c7a180; 1 drivers -v0x28fa910_0 .net "in3", 0 0, L_0x2c78e50; 1 drivers -v0x28fa630_0 .net "nS0", 0 0, L_0x2c78120; 1 drivers -v0x28fa170_0 .net "nS1", 0 0, L_0x2c78210; 1 drivers -v0x28fa210_0 .net "out", 0 0, L_0x2c78740; 1 drivers -v0x28fbd90_0 .net "out0", 0 0, L_0x2c782b0; 1 drivers -v0x28fbe30_0 .net "out1", 0 0, L_0x2c783f0; 1 drivers -v0x28fbb30_0 .net "out2", 0 0, L_0x2c784e0; 1 drivers -v0x28fb690_0 .net "out3", 0 0, L_0x2c785d0; 1 drivers -S_0x28f5190 .scope module, "OneMux" "FourInMux" 3 293, 3 24, S_0x28f1160; - .timescale -9 -12; -L_0x2c78f40/d .functor NOT 1, L_0x2c79800, C4<0>, C4<0>, C4<0>; -L_0x2c78f40 .delay (10000,10000,10000) L_0x2c78f40/d; -L_0x2c78ff0/d .functor NOT 1, L_0x2c79930, C4<0>, C4<0>, C4<0>; -L_0x2c78ff0 .delay (10000,10000,10000) L_0x2c78ff0/d; -L_0x2c79090/d .functor NAND 1, L_0x2c78f40, L_0x2c78ff0, L_0x2c79a60, C4<1>; -L_0x2c79090 .delay (10000,10000,10000) L_0x2c79090/d; -L_0x2c791d0/d .functor NAND 1, L_0x2c79800, L_0x2c78ff0, L_0x2c79b00, C4<1>; -L_0x2c791d0 .delay (10000,10000,10000) L_0x2c791d0/d; -L_0x2c792c0/d .functor NAND 1, L_0x2c78f40, L_0x2c79930, L_0x2c79ba0, C4<1>; -L_0x2c792c0 .delay (10000,10000,10000) L_0x2c792c0/d; -L_0x2c793e0/d .functor NAND 1, L_0x2c79800, L_0x2c79930, L_0x2c79c90, C4<1>; -L_0x2c793e0 .delay (10000,10000,10000) L_0x2c793e0/d; -L_0x2c79550/d .functor NAND 1, L_0x2c79090, L_0x2c791d0, L_0x2c792c0, L_0x2c793e0; -L_0x2c79550 .delay (10000,10000,10000) L_0x2c79550/d; -v0x28f5490_0 .net "S0", 0 0, L_0x2c79800; 1 drivers -v0x28f4cf0_0 .net "S1", 0 0, L_0x2c79930; 1 drivers -v0x28f4d70_0 .net "in0", 0 0, L_0x2c79a60; 1 drivers -v0x28f6910_0 .net "in1", 0 0, L_0x2c79b00; 1 drivers -v0x28f69b0_0 .net "in2", 0 0, L_0x2c79ba0; 1 drivers -v0x28f66b0_0 .net "in3", 0 0, L_0x2c79c90; 1 drivers -v0x28f6750_0 .net "nS0", 0 0, L_0x2c78f40; 1 drivers -v0x28f6230_0 .net "nS1", 0 0, L_0x2c78ff0; 1 drivers -v0x28f7e30_0 .net "out", 0 0, L_0x2c79550; 1 drivers -v0x28f7ed0_0 .net "out0", 0 0, L_0x2c79090; 1 drivers -v0x28f7bd0_0 .net "out1", 0 0, L_0x2c791d0; 1 drivers -v0x28f7c70_0 .net "out2", 0 0, L_0x2c792c0; 1 drivers -v0x28f77c0_0 .net "out3", 0 0, L_0x2c793e0; 1 drivers -S_0x28f29b0 .scope module, "TwoMux" "TwoInMux" 3 294, 3 8, S_0x28f1160; - .timescale -9 -12; -L_0x2c79d80/d .functor NOT 1, L_0x2c7b680, C4<0>, C4<0>, C4<0>; -L_0x2c79d80 .delay (10000,10000,10000) L_0x2c79d80/d; -L_0x2c79e70/d .functor AND 1, L_0x2c7a220, L_0x2c79d80, C4<1>, C4<1>; -L_0x2c79e70 .delay (20000,20000,20000) L_0x2c79e70/d; -L_0x2c79f60/d .functor AND 1, L_0x2c7a310, L_0x2c7b680, C4<1>, C4<1>; -L_0x2c79f60 .delay (20000,20000,20000) L_0x2c79f60/d; -L_0x2c7a050/d .functor OR 1, L_0x2c79e70, L_0x2c79f60, C4<0>, C4<0>; -L_0x2c7a050 .delay (20000,20000,20000) L_0x2c7a050/d; -v0x28f2750_0 .net "S", 0 0, L_0x2c7b680; 1 drivers -v0x28f27f0_0 .net "in0", 0 0, L_0x2c7a220; 1 drivers -v0x28f3ed0_0 .net "in1", 0 0, L_0x2c7a310; 1 drivers -v0x28f3f70_0 .net "nS", 0 0, L_0x2c79d80; 1 drivers -v0x28f3c90_0 .net "out0", 0 0, L_0x2c79e70; 1 drivers -v0x28f37d0_0 .net "out1", 0 0, L_0x2c79f60; 1 drivers -v0x28f53f0_0 .net "outfinal", 0 0, L_0x2c7a050; 1 drivers -S_0x28d4280 .scope generate, "muxbits[30]" "muxbits[30]" 3 290, 3 290, S_0x29738d0; - .timescale -9 -12; -P_0x28c0b88 .param/l "i" 3 290, +C4<011110>; -L_0x2c7cc40/d .functor OR 1, L_0x2c7cd80, L_0x2c7ce20, C4<0>, C4<0>; -L_0x2c7cc40 .delay (20000,20000,20000) L_0x2c7cc40/d; -v0x291a320_0 .net *"_s15", 0 0, L_0x2c7cd80; 1 drivers -v0x2919df0_0 .net *"_s16", 0 0, L_0x2c7ce20; 1 drivers -S_0x28e03c0 .scope module, "ZeroMux" "FourInMux" 3 292, 3 24, S_0x28d4280; - .timescale -9 -12; -L_0x2c7a730/d .functor NOT 1, L_0x2c7afa0, C4<0>, C4<0>, C4<0>; -L_0x2c7a730 .delay (10000,10000,10000) L_0x2c7a730/d; -L_0x2c7a820/d .functor NOT 1, L_0x2c7b0d0, C4<0>, C4<0>, C4<0>; -L_0x2c7a820 .delay (10000,10000,10000) L_0x2c7a820/d; -L_0x2c7a8c0/d .functor NAND 1, L_0x2c7a730, L_0x2c7a820, L_0x2c7b200, C4<1>; -L_0x2c7a8c0 .delay (10000,10000,10000) L_0x2c7a8c0/d; -L_0x2c7aa00/d .functor NAND 1, L_0x2c7afa0, L_0x2c7a820, L_0x2c7b2a0, C4<1>; -L_0x2c7aa00 .delay (10000,10000,10000) L_0x2c7aa00/d; -L_0x2c7aaf0/d .functor NAND 1, L_0x2c7a730, L_0x2c7b0d0, L_0x2c7b340, C4<1>; -L_0x2c7aaf0 .delay (10000,10000,10000) L_0x2c7aaf0/d; -L_0x2c7abe0/d .functor NAND 1, L_0x2c7afa0, L_0x2c7b0d0, L_0x2c7b430, C4<1>; -L_0x2c7abe0 .delay (10000,10000,10000) L_0x2c7abe0/d; -L_0x2c7acf0/d .functor NAND 1, L_0x2c7a8c0, L_0x2c7aa00, L_0x2c7aaf0, L_0x2c7abe0; -L_0x2c7acf0 .delay (10000,10000,10000) L_0x2c7acf0/d; -v0x28e5160_0 .net "S0", 0 0, L_0x2c7afa0; 1 drivers -v0x28e30e0_0 .net "S1", 0 0, L_0x2c7b0d0; 1 drivers -v0x28e3180_0 .net "in0", 0 0, L_0x2c7b200; 1 drivers -v0x28e7e80_0 .net "in1", 0 0, L_0x2c7b2a0; 1 drivers -v0x28e7f00_0 .net "in2", 0 0, L_0x2c7b340; 1 drivers -v0x28e5e00_0 .net "in3", 0 0, L_0x2c7b430; 1 drivers -v0x28e5ea0_0 .net "nS0", 0 0, L_0x2c7a730; 1 drivers -v0x28eaba0_0 .net "nS1", 0 0, L_0x2c7a820; 1 drivers -v0x28eac40_0 .net "out", 0 0, L_0x2c7acf0; 1 drivers -v0x28e8b20_0 .net "out0", 0 0, L_0x2c7a8c0; 1 drivers -v0x28e8ba0_0 .net "out1", 0 0, L_0x2c7aa00; 1 drivers -v0x291a4d0_0 .net "out2", 0 0, L_0x2c7aaf0; 1 drivers -v0x291a280_0 .net "out3", 0 0, L_0x2c7abe0; 1 drivers -S_0x28d9b40 .scope module, "OneMux" "FourInMux" 3 293, 3 24, S_0x28d4280; - .timescale -9 -12; -L_0x2c7b720/d .functor NOT 1, L_0x2c7bfc0, C4<0>, C4<0>, C4<0>; -L_0x2c7b720 .delay (10000,10000,10000) L_0x2c7b720/d; -L_0x2c7b810/d .functor NOT 1, L_0x2c7c0f0, C4<0>, C4<0>, C4<0>; -L_0x2c7b810 .delay (10000,10000,10000) L_0x2c7b810/d; -L_0x2c7b8b0/d .functor NAND 1, L_0x2c7b720, L_0x2c7b810, L_0x2c7c220, C4<1>; -L_0x2c7b8b0 .delay (10000,10000,10000) L_0x2c7b8b0/d; -L_0x2c7b9f0/d .functor NAND 1, L_0x2c7bfc0, L_0x2c7b810, L_0x2c7c2c0, C4<1>; -L_0x2c7b9f0 .delay (10000,10000,10000) L_0x2c7b9f0/d; -L_0x2c7bae0/d .functor NAND 1, L_0x2c7b720, L_0x2c7c0f0, L_0x2c7c360, C4<1>; -L_0x2c7bae0 .delay (10000,10000,10000) L_0x2c7bae0/d; -L_0x2c7bbd0/d .functor NAND 1, L_0x2c7bfc0, L_0x2c7c0f0, L_0x2c7c450, C4<1>; -L_0x2c7bbd0 .delay (10000,10000,10000) L_0x2c7bbd0/d; -L_0x2c7bd10/d .functor NAND 1, L_0x2c7b8b0, L_0x2c7b9f0, L_0x2c7bae0, L_0x2c7bbd0; -L_0x2c7bd10 .delay (10000,10000,10000) L_0x2c7bd10/d; -v0x28d98b0_0 .net "S0", 0 0, L_0x2c7bfc0; 1 drivers -v0x28d9950_0 .net "S1", 0 0, L_0x2c7c0f0; 1 drivers -v0x28d7da0_0 .net "in0", 0 0, L_0x2c7c220; 1 drivers -v0x28d7e40_0 .net "in1", 0 0, L_0x2c7c2c0; 1 drivers -v0x28dc7a0_0 .net "in2", 0 0, L_0x2c7c360; 1 drivers -v0x28dc840_0 .net "in3", 0 0, L_0x2c7c450; 1 drivers -v0x28dc570_0 .net "nS0", 0 0, L_0x2c7b720; 1 drivers -v0x28daa00_0 .net "nS1", 0 0, L_0x2c7b810; 1 drivers -v0x28daa80_0 .net "out", 0 0, L_0x2c7bd10; 1 drivers -v0x28df720_0 .net "out0", 0 0, L_0x2c7b8b0; 1 drivers -v0x28df7c0_0 .net "out1", 0 0, L_0x2c7b9f0; 1 drivers -v0x28dd6c0_0 .net "out2", 0 0, L_0x2c7bae0; 1 drivers -v0x28e2460_0 .net "out3", 0 0, L_0x2c7bbd0; 1 drivers -S_0x28d3ff0 .scope module, "TwoMux" "TwoInMux" 3 294, 3 8, S_0x28d4280; - .timescale -9 -12; -L_0x2c7c540/d .functor NOT 1, L_0x2c7de40, C4<0>, C4<0>, C4<0>; -L_0x2c7c540 .delay (10000,10000,10000) L_0x2c7c540/d; -L_0x2c7c630/d .functor AND 1, L_0x2c7dee0, L_0x2c7c540, C4<1>, C4<1>; -L_0x2c7c630 .delay (20000,20000,20000) L_0x2c7c630/d; -L_0x2c7c720/d .functor AND 1, L_0x2c7cab0, L_0x2c7de40, C4<1>, C4<1>; -L_0x2c7c720 .delay (20000,20000,20000) L_0x2c7c720/d; -L_0x2c7c810/d .functor OR 1, L_0x2c7c630, L_0x2c7c720, C4<0>, C4<0>; -L_0x2c7c810 .delay (20000,20000,20000) L_0x2c7c810/d; -v0x28d24e0_0 .net "S", 0 0, L_0x2c7de40; 1 drivers -v0x28d2580_0 .net "in0", 0 0, L_0x2c7dee0; 1 drivers -v0x28d6ee0_0 .net "in1", 0 0, L_0x2c7cab0; 1 drivers -v0x28d6f80_0 .net "nS", 0 0, L_0x2c7c540; 1 drivers -v0x28d6c50_0 .net "out0", 0 0, L_0x2c7c630; 1 drivers -v0x28d6cf0_0 .net "out1", 0 0, L_0x2c7c720; 1 drivers -v0x28d51a0_0 .net "outfinal", 0 0, L_0x2c7c810; 1 drivers -S_0x2979430 .scope generate, "muxbits[31]" "muxbits[31]" 3 290, 3 290, S_0x29738d0; - .timescale -9 -12; -P_0x28b1f38 .param/l "i" 3 290, +C4<011111>; -L_0x2c49a50/d .functor OR 1, L_0x2c7e5a0, L_0x2c7e640, C4<0>, C4<0>; -L_0x2c49a50 .delay (20000,20000,20000) L_0x2c49a50/d; -v0x28d1430_0 .net *"_s15", 0 0, L_0x2c7e5a0; 1 drivers -v0x28cf880_0 .net *"_s16", 0 0, L_0x2c7e640; 1 drivers -S_0x28c9260 .scope module, "ZeroMux" "FourInMux" 3 292, 3 24, S_0x2979430; - .timescale -9 -12; -L_0x2c7cf10/d .functor NOT 1, L_0x2c7d7b0, C4<0>, C4<0>, C4<0>; -L_0x2c7cf10 .delay (10000,10000,10000) L_0x2c7cf10/d; -L_0x2c7d000/d .functor NOT 1, L_0x2c7d8e0, C4<0>, C4<0>, C4<0>; -L_0x2c7d000 .delay (10000,10000,10000) L_0x2c7d000/d; -L_0x2c7d0a0/d .functor NAND 1, L_0x2c7cf10, L_0x2c7d000, L_0x2c7da10, C4<1>; -L_0x2c7d0a0 .delay (10000,10000,10000) L_0x2c7d0a0/d; -L_0x2c7d1e0/d .functor NAND 1, L_0x2c7d7b0, L_0x2c7d000, L_0x2c7dab0, C4<1>; -L_0x2c7d1e0 .delay (10000,10000,10000) L_0x2c7d1e0/d; -L_0x2c7d2d0/d .functor NAND 1, L_0x2c7cf10, L_0x2c7d8e0, L_0x2c7db50, C4<1>; -L_0x2c7d2d0 .delay (10000,10000,10000) L_0x2c7d2d0/d; -L_0x2c7d3c0/d .functor NAND 1, L_0x2c7d7b0, L_0x2c7d8e0, L_0x2c7dc40, C4<1>; -L_0x2c7d3c0 .delay (10000,10000,10000) L_0x2c7d3c0/d; -L_0x2c7d500/d .functor NAND 1, L_0x2c7d0a0, L_0x2c7d1e0, L_0x2c7d2d0, L_0x2c7d3c0; -L_0x2c7d500 .delay (10000,10000,10000) L_0x2c7d500/d; -v0x28c4540_0 .net "S0", 0 0, L_0x2c7d7b0; 1 drivers -v0x28c71e0_0 .net "S1", 0 0, L_0x2c7d8e0; 1 drivers -v0x28c7280_0 .net "in0", 0 0, L_0x2c7da10; 1 drivers -v0x28cbfa0_0 .net "in1", 0 0, L_0x2c7dab0; 1 drivers -v0x28cc020_0 .net "in2", 0 0, L_0x2c7db50; 1 drivers -v0x28c9f20_0 .net "in3", 0 0, L_0x2c7dc40; 1 drivers -v0x28ce9c0_0 .net "nS0", 0 0, L_0x2c7cf10; 1 drivers -v0x28cea60_0 .net "nS1", 0 0, L_0x2c7d000; 1 drivers -v0x28ce730_0 .net "out", 0 0, L_0x2c7d500; 1 drivers -v0x28ce7d0_0 .net "out0", 0 0, L_0x2c7d0a0; 1 drivers -v0x28ccca0_0 .net "out1", 0 0, L_0x2c7d1e0; 1 drivers -v0x28d1620_0 .net "out2", 0 0, L_0x2c7d2d0; 1 drivers -v0x28d1390_0 .net "out3", 0 0, L_0x2c7d3c0; 1 drivers -S_0x28b9100 .scope module, "OneMux" "FourInMux" 3 293, 3 24, S_0x2979430; - .timescale -9 -12; -L_0x2c7dd30/d .functor NOT 1, L_0x2c7df80, C4<0>, C4<0>, C4<0>; -L_0x2c7dd30 .delay (10000,10000,10000) L_0x2c7dd30/d; -L_0x2c45810/d .functor NOT 1, L_0x2c7e0b0, C4<0>, C4<0>, C4<0>; -L_0x2c45810 .delay (10000,10000,10000) L_0x2c45810/d; -L_0x2c458b0/d .functor NAND 1, L_0x2c7dd30, L_0x2c45810, L_0x2c7e1e0, C4<1>; -L_0x2c458b0 .delay (10000,10000,10000) L_0x2c458b0/d; -L_0x2c459f0/d .functor NAND 1, L_0x2c7df80, L_0x2c45810, L_0x2c7e280, C4<1>; -L_0x2c459f0 .delay (10000,10000,10000) L_0x2c459f0/d; -L_0x2c45ae0/d .functor NAND 1, L_0x2c7dd30, L_0x2c7e0b0, L_0x2c7e320, C4<1>; -L_0x2c45ae0 .delay (10000,10000,10000) L_0x2c45ae0/d; -L_0x2c45bd0/d .functor NAND 1, L_0x2c7df80, L_0x2c7e0b0, L_0x2c7e410, C4<1>; -L_0x2c45bd0 .delay (10000,10000,10000) L_0x2c45bd0/d; -L_0x2c45d40/d .functor NAND 1, L_0x2c458b0, L_0x2c459f0, L_0x2c45ae0, L_0x2c45bd0; -L_0x2c45d40 .delay (10000,10000,10000) L_0x2c45d40/d; -v0x28bacb0_0 .net "S0", 0 0, L_0x2c7df80; 1 drivers -v0x28bdde0_0 .net "S1", 0 0, L_0x2c7e0b0; 1 drivers -v0x28bde60_0 .net "in0", 0 0, L_0x2c7e1e0; 1 drivers -v0x28bbd60_0 .net "in1", 0 0, L_0x2c7e280; 1 drivers -v0x28bbe00_0 .net "in2", 0 0, L_0x2c7e320; 1 drivers -v0x28c0b00_0 .net "in3", 0 0, L_0x2c7e410; 1 drivers -v0x28bea80_0 .net "nS0", 0 0, L_0x2c7dd30; 1 drivers -v0x28beb20_0 .net "nS1", 0 0, L_0x2c45810; 1 drivers -v0x28c3890_0 .net "out", 0 0, L_0x2c45d40; 1 drivers -v0x28c17a0_0 .net "out0", 0 0, L_0x2c458b0; 1 drivers -v0x28c6540_0 .net "out1", 0 0, L_0x2c459f0; 1 drivers -v0x28c65e0_0 .net "out2", 0 0, L_0x2c45ae0; 1 drivers -v0x28c44c0_0 .net "out3", 0 0, L_0x2c45bd0; 1 drivers -S_0x2990a40 .scope module, "TwoMux" "TwoInMux" 3 294, 3 8, S_0x2979430; - .timescale -9 -12; -L_0x2c45c60/d .functor NOT 1, L_0x2c49730, C4<0>, C4<0>, C4<0>; -L_0x2c45c60 .delay (10000,10000,10000) L_0x2c45c60/d; -L_0x2c49370/d .functor AND 1, L_0x2c497d0, L_0x2c45c60, C4<1>, C4<1>; -L_0x2c49370 .delay (20000,20000,20000) L_0x2c49370/d; -L_0x2c49460/d .functor AND 1, L_0x2c498c0, L_0x2c49730, C4<1>, C4<1>; -L_0x2c49460 .delay (20000,20000,20000) L_0x2c49460/d; -L_0x2c49550/d .functor OR 1, L_0x2c49370, L_0x2c49460, C4<0>, C4<0>; -L_0x2c49550 .delay (20000,20000,20000) L_0x2c49550/d; -v0x2663a40_0 .net "S", 0 0, L_0x2c49730; 1 drivers -v0x28b82c0_0 .net "in0", 0 0, L_0x2c497d0; 1 drivers -v0x28b7fb0_0 .net "in1", 0 0, L_0x2c498c0; 1 drivers -v0x28b8050_0 .net "nS", 0 0, L_0x2c45c60; 1 drivers -v0x28b64d0_0 .net "out0", 0 0, L_0x2c49370; 1 drivers -v0x28baea0_0 .net "out1", 0 0, L_0x2c49460; 1 drivers -v0x28bac10_0 .net "outfinal", 0 0, L_0x2c49550; 1 drivers - .scope S_0x270e6d0; +S_0x22690e0 .scope module, "Bitslice32" "Bitslice32" 2 256; + .timescale -9 -12; +P_0x2104ab8 .param/l "size" 2 273, +C4<0100000>; +L_0x249f5b0/d .functor AND 1, L_0x249f6f0, L_0x2492a20, C4<1>, C4<1>; +L_0x249f5b0 .delay (20000,20000,20000) L_0x249f5b0/d; +L_0x2492b10/d .functor NOT 1, L_0x2492c00, C4<0>, C4<0>, C4<0>; +L_0x2492b10 .delay (10000,10000,10000) L_0x2492b10/d; +L_0x2492ca0/d .functor AND 1, L_0x2492b10, L_0x2492b10, C4<1>, C4<1>; +L_0x2492ca0 .delay (20000,20000,20000) L_0x2492ca0/d; +v0x2462f10_0 .net "A", 31 0, C4; 0 drivers +RS_0x7fd6f9610aa8/0/0 .resolv tri, L_0x2478890, L_0x24bb770, L_0x24bcb70, L_0x24be000; +RS_0x7fd6f9610aa8/0/4 .resolv tri, L_0x24bf4a0, L_0x24c0a90, L_0x24c1fd0, L_0x24c3550; +RS_0x7fd6f9610aa8/0/8 .resolv tri, L_0x24c4b60, L_0x24c6070, L_0x24c7580, L_0x24c8a90; +RS_0x7fd6f9610aa8/0/12 .resolv tri, L_0x24c9f90, L_0x24cb6b0, L_0x24ccbc0, L_0x24ce1d0; +RS_0x7fd6f9610aa8/0/16 .resolv tri, L_0x24cf800, L_0x24d0c70, L_0x24d2120, L_0x24d34f0; +RS_0x7fd6f9610aa8/0/20 .resolv tri, L_0x24d4930, L_0x24d5e40, L_0x24d7200, L_0x24d8650; +RS_0x7fd6f9610aa8/0/24 .resolv tri, L_0x24d9b40, L_0x24db020, L_0x24dc500, L_0x24dda00; +RS_0x7fd6f9610aa8/0/28 .resolv tri, L_0x24deef0, L_0x24e07c0, L_0x24e1cb0, L_0x24e33a0; +RS_0x7fd6f9610aa8/1/0 .resolv tri, RS_0x7fd6f9610aa8/0/0, RS_0x7fd6f9610aa8/0/4, RS_0x7fd6f9610aa8/0/8, RS_0x7fd6f9610aa8/0/12; +RS_0x7fd6f9610aa8/1/4 .resolv tri, RS_0x7fd6f9610aa8/0/16, RS_0x7fd6f9610aa8/0/20, RS_0x7fd6f9610aa8/0/24, RS_0x7fd6f9610aa8/0/28; +RS_0x7fd6f9610aa8 .resolv tri, RS_0x7fd6f9610aa8/1/0, RS_0x7fd6f9610aa8/1/4, C4, C4; +v0x2463100_0 .net8 "AddSubSLTSum", 31 0, RS_0x7fd6f9610aa8; 32 drivers +v0x2463180_0 .net "AllZeros", 0 0, L_0x2492ca0; 1 drivers +RS_0x7fd6f9609e78/0/0 .resolv tri, L_0x24e5dd0, L_0x24e6b80, L_0x24e7610, L_0x24e8070; +RS_0x7fd6f9609e78/0/4 .resolv tri, L_0x24e8ae0, L_0x24e95b0, L_0x24ea0b0, L_0x24eab10; +RS_0x7fd6f9609e78/0/8 .resolv tri, L_0x24eb590, L_0x24ec000, L_0x24eca70, L_0x24ed4e0; +RS_0x7fd6f9609e78/0/12 .resolv tri, L_0x24edf60, L_0x24ee9c0, L_0x24ef430, L_0x24efea0; +RS_0x7fd6f9609e78/0/16 .resolv tri, L_0x24f0920, L_0x24f1380, L_0x24f1e00, L_0x24f2860; +RS_0x7fd6f9609e78/0/20 .resolv tri, L_0x24f32d0, L_0x24f3d40, L_0x24f47c0, L_0x24f5220; +RS_0x7fd6f9609e78/0/24 .resolv tri, L_0x24f5c90, L_0x24f66f0, L_0x24f7160, L_0x24f7bd0; +RS_0x7fd6f9609e78/0/28 .resolv tri, L_0x24f8650, L_0x24f97b0, L_0x24fa160, L_0x24fab10; +RS_0x7fd6f9609e78/1/0 .resolv tri, RS_0x7fd6f9609e78/0/0, RS_0x7fd6f9609e78/0/4, RS_0x7fd6f9609e78/0/8, RS_0x7fd6f9609e78/0/12; +RS_0x7fd6f9609e78/1/4 .resolv tri, RS_0x7fd6f9609e78/0/16, RS_0x7fd6f9609e78/0/20, RS_0x7fd6f9609e78/0/24, RS_0x7fd6f9609e78/0/28; +RS_0x7fd6f9609e78 .resolv tri, RS_0x7fd6f9609e78/1/0, RS_0x7fd6f9609e78/1/4, C4, C4; +v0x2463200_0 .net8 "AndNandOut", 31 0, RS_0x7fd6f9609e78; 32 drivers +v0x24632b0_0 .net "B", 31 0, C4; 0 drivers +RS_0x7fd6f9610ec8/0/0 .resolv tri, L_0x2469c90, L_0x246c730, L_0x246f0d0, L_0x2471a70; +RS_0x7fd6f9610ec8/0/4 .resolv tri, L_0x2474510, L_0x2476df0, L_0x2479b60, L_0x247c1d0; +RS_0x7fd6f9610ec8/0/8 .resolv tri, L_0x247ee10, L_0x2481480, L_0x2483b10, L_0x2486610; +RS_0x7fd6f9610ec8/0/12 .resolv tri, L_0x2488d20, L_0x248b450, L_0x248dad0, L_0x24900b0; +RS_0x7fd6f9610ec8/0/16 .resolv tri, L_0x2491ea0, L_0x2495870, L_0x2497340, L_0x2499800; +RS_0x7fd6f9610ec8/0/20 .resolv tri, L_0x249ced0, L_0x249e890, L_0x24a1700, L_0x24a3ed0; +RS_0x7fd6f9610ec8/0/24 .resolv tri, L_0x24a7600, L_0x24a9d40, L_0x24ac500, L_0x24aec80; +RS_0x7fd6f9610ec8/0/28 .resolv tri, L_0x24b1470, L_0x24b2380, L_0x24b4ea0, L_0x2520e60; +RS_0x7fd6f9610ec8/1/0 .resolv tri, RS_0x7fd6f9610ec8/0/0, RS_0x7fd6f9610ec8/0/4, RS_0x7fd6f9610ec8/0/8, RS_0x7fd6f9610ec8/0/12; +RS_0x7fd6f9610ec8/1/4 .resolv tri, RS_0x7fd6f9610ec8/0/16, RS_0x7fd6f9610ec8/0/20, RS_0x7fd6f9610ec8/0/24, RS_0x7fd6f9610ec8/0/28; +RS_0x7fd6f9610ec8 .resolv tri, RS_0x7fd6f9610ec8/1/0, RS_0x7fd6f9610ec8/1/4, C4, C4; +v0x2463330_0 .net8 "Cmd0Start", 31 0, RS_0x7fd6f9610ec8; 32 drivers +RS_0x7fd6f9610ef8/0/0 .resolv tri, L_0x246ac00, L_0x246d620, L_0x2470080, L_0x2472930; +RS_0x7fd6f9610ef8/0/4 .resolv tri, L_0x24753d0, L_0x2477bc0, L_0x247a920, L_0x247cfd0; +RS_0x7fd6f9610ef8/0/8 .resolv tri, L_0x247fbd0, L_0x2482260, L_0x2484260, L_0x2487410; +RS_0x7fd6f9610ef8/0/12 .resolv tri, L_0x2489b50, L_0x248c220, L_0x248e870, L_0x2490e80; +RS_0x7fd6f9610ef8/0/16 .resolv tri, L_0x2493f70, L_0x24966d0, L_0x2498e70, L_0x249a810; +RS_0x7fd6f9610ef8/0/20 .resolv tri, L_0x249e180, L_0x24a0d00, L_0x24a3540, L_0x24a5cc0; +RS_0x7fd6f9610ef8/0/24 .resolv tri, L_0x24a6b00, L_0x24a96e0, L_0x24abc40, L_0x24ae790; +RS_0x7fd6f9610ef8/0/28 .resolv tri, L_0x24b0cd0, L_0x24b36a0, L_0x24b72a0, L_0x24b7ff0; +RS_0x7fd6f9610ef8/1/0 .resolv tri, RS_0x7fd6f9610ef8/0/0, RS_0x7fd6f9610ef8/0/4, RS_0x7fd6f9610ef8/0/8, RS_0x7fd6f9610ef8/0/12; +RS_0x7fd6f9610ef8/1/4 .resolv tri, RS_0x7fd6f9610ef8/0/16, RS_0x7fd6f9610ef8/0/20, RS_0x7fd6f9610ef8/0/24, RS_0x7fd6f9610ef8/0/28; +RS_0x7fd6f9610ef8 .resolv tri, RS_0x7fd6f9610ef8/1/0, RS_0x7fd6f9610ef8/1/4, C4, C4; +v0x24633b0_0 .net8 "Cmd1Start", 31 0, RS_0x7fd6f9610ef8; 32 drivers +v0x2463430_0 .net "Command", 2 0, C4; 0 drivers +RS_0x7fd6f9610f28/0/0 .resolv tri, L_0x246b680, L_0x246e0f0, L_0x2470b40, L_0x2473480; +RS_0x7fd6f9610f28/0/4 .resolv tri, L_0x2475a80, L_0x243e8f0, L_0x247b420, L_0x247db60; +RS_0x7fd6f9610f28/0/8 .resolv tri, L_0x2480640, L_0x2482cc0, L_0x24857b0, L_0x2487e70; +RS_0x7fd6f9610f28/0/12 .resolv tri, L_0x248a5e0, L_0x248ccf0, L_0x248f2c0, L_0x2491af0; +RS_0x7fd6f9610f28/0/16 .resolv tri, L_0x2493760, L_0x2496130, L_0x2498b00, L_0x249b230; +RS_0x7fd6f9610f28/0/20 .resolv tri, L_0x2484710, L_0x24a0020, L_0x24a2760, L_0x24a4df0; +RS_0x7fd6f9610f28/0/24 .resolv tri, L_0x24a7d00, L_0x24aa3e0, L_0x24aca40, L_0x24af1e0; +RS_0x7fd6f9610f28/0/28 .resolv tri, L_0x24b2d30, L_0x24b40d0, L_0x24b60c0, L_0x249f1f0; +RS_0x7fd6f9610f28/1/0 .resolv tri, RS_0x7fd6f9610f28/0/0, RS_0x7fd6f9610f28/0/4, RS_0x7fd6f9610f28/0/8, RS_0x7fd6f9610f28/0/12; +RS_0x7fd6f9610f28/1/4 .resolv tri, RS_0x7fd6f9610f28/0/16, RS_0x7fd6f9610f28/0/20, RS_0x7fd6f9610f28/0/24, RS_0x7fd6f9610f28/0/28; +RS_0x7fd6f9610f28 .resolv tri, RS_0x7fd6f9610f28/1/0, RS_0x7fd6f9610f28/1/4, C4, C4; +v0x24634b0_0 .net8 "OneBitFinalOut", 31 0, RS_0x7fd6f9610f28; 32 drivers +RS_0x7fd6f9606848/0/0 .resolv tri, L_0x24fbcf0, L_0x24fcdf0, L_0x24fdf50, L_0x24ff200; +RS_0x7fd6f9606848/0/4 .resolv tri, L_0x25003e0, L_0x2501740, L_0x2502ad0, L_0x2503dc0; +RS_0x7fd6f9606848/0/8 .resolv tri, L_0x25050d0, L_0x25063d0, L_0x25076d0, L_0x25089c0; +RS_0x7fd6f9606848/0/12 .resolv tri, L_0x2509ce0, L_0x250afe0, L_0x250c2e0, L_0x250d5d0; +RS_0x7fd6f9606848/0/16 .resolv tri, L_0x250e8e0, L_0x250fbd0, L_0x2510ed0, L_0x25121d0; +RS_0x7fd6f9606848/0/20 .resolv tri, L_0x25134e0, L_0x25147d0, L_0x2515ad0, L_0x2516dd0; +RS_0x7fd6f9606848/0/24 .resolv tri, L_0x25180d0, L_0x25193e0, L_0x251a6e0, L_0x251b9d0; +RS_0x7fd6f9606848/0/28 .resolv tri, L_0x251cd50, L_0x251e060, L_0x251f370, L_0x2520520; +RS_0x7fd6f9606848/1/0 .resolv tri, RS_0x7fd6f9606848/0/0, RS_0x7fd6f9606848/0/4, RS_0x7fd6f9606848/0/8, RS_0x7fd6f9606848/0/12; +RS_0x7fd6f9606848/1/4 .resolv tri, RS_0x7fd6f9606848/0/16, RS_0x7fd6f9606848/0/20, RS_0x7fd6f9606848/0/24, RS_0x7fd6f9606848/0/28; +RS_0x7fd6f9606848 .resolv tri, RS_0x7fd6f9606848/1/0, RS_0x7fd6f9606848/1/4, C4, C4; +v0x2463550_0 .net8 "OrNorXorOut", 31 0, RS_0x7fd6f9606848; 32 drivers +v0x24635d0_0 .net "SLTflag", 0 0, L_0x24e4440; 1 drivers +RS_0x7fd6f9610f58/0/0 .resolv tri, L_0x246bb70, L_0x246e530, L_0x2470c80, L_0x2473630; +RS_0x7fd6f9610f58/0/4 .resolv tri, L_0x2475dd0, L_0x243ec10, L_0x247b190, L_0x2473520; +RS_0x7fd6f9610f58/0/8 .resolv tri, L_0x247fe50, L_0x24826b0, L_0x2485230, L_0x2487860; +RS_0x7fd6f9610f58/0/12 .resolv tri, L_0x2489dd0, L_0x248c670, L_0x248eaf0, L_0x2491a00; +RS_0x7fd6f9610f58/0/16 .resolv tri, L_0x2494010, L_0x2497460, L_0x2499b80, L_0x249b550; +RS_0x7fd6f9610f58/0/20 .resolv tri, L_0x249d8a0, L_0x24a0340, L_0x24a2a80, L_0x24a5110; +RS_0x7fd6f9610f58/0/24 .resolv tri, L_0x24a8020, L_0x24aa700, L_0x24acd60, L_0x24af500; +RS_0x7fd6f9610f58/0/28 .resolv tri, L_0x24b1820, L_0x24b4340, L_0x24b63e0, L_0x249f510; +RS_0x7fd6f9610f58/1/0 .resolv tri, RS_0x7fd6f9610f58/0/0, RS_0x7fd6f9610f58/0/4, RS_0x7fd6f9610f58/0/8, RS_0x7fd6f9610f58/0/12; +RS_0x7fd6f9610f58/1/4 .resolv tri, RS_0x7fd6f9610f58/0/16, RS_0x7fd6f9610f58/0/20, RS_0x7fd6f9610f58/0/24, RS_0x7fd6f9610f58/0/28; +RS_0x7fd6f9610f58 .resolv tri, RS_0x7fd6f9610f58/1/0, RS_0x7fd6f9610f58/1/4, C4, C4; +v0x2463680_0 .net8 "ZeroFlag", 31 0, RS_0x7fd6f9610f58; 32 drivers +v0x2463700_0 .net *"_s121", 0 0, L_0x2475e70; 1 drivers +v0x2463780_0 .net *"_s146", 0 0, L_0x243e4e0; 1 drivers +v0x24638a0_0 .net *"_s171", 0 0, L_0x247b230; 1 drivers +v0x2463940_0 .net *"_s196", 0 0, L_0x24735c0; 1 drivers +v0x2463800_0 .net *"_s21", 0 0, L_0x246b7c0; 1 drivers +v0x2463a90_0 .net *"_s221", 0 0, L_0x247fef0; 1 drivers +v0x2463bb0_0 .net *"_s246", 0 0, L_0x2482750; 1 drivers +v0x2463c30_0 .net *"_s271", 0 0, L_0x24852d0; 1 drivers +v0x2463b10_0 .net *"_s296", 0 0, L_0x2487900; 1 drivers +v0x2463d60_0 .net *"_s321", 0 0, L_0x2489e70; 1 drivers +v0x2463cb0_0 .net *"_s346", 0 0, L_0x248c710; 1 drivers +v0x2463ea0_0 .net *"_s371", 0 0, L_0x248eb90; 1 drivers +v0x2463e00_0 .net *"_s396", 0 0, L_0x247d420; 1 drivers +v0x2463ff0_0 .net *"_s421", 0 0, L_0x24940b0; 1 drivers +v0x2463f40_0 .net *"_s446", 0 0, L_0x24968a0; 1 drivers +v0x2464150_0 .net *"_s46", 0 0, L_0x246e3f0; 1 drivers +v0x2464090_0 .net *"_s471", 0 0, L_0x2499c20; 1 drivers +v0x24642c0_0 .net *"_s496", 0 0, L_0x249b5f0; 1 drivers +v0x24641d0_0 .net *"_s521", 0 0, L_0x249d940; 1 drivers +v0x2464440_0 .net *"_s546", 0 0, L_0x24a03e0; 1 drivers +v0x2464340_0 .net *"_s571", 0 0, L_0x24a2b20; 1 drivers +v0x24645d0_0 .net *"_s596", 0 0, L_0x24a51b0; 1 drivers +v0x24644c0_0 .net *"_s621", 0 0, L_0x24a80c0; 1 drivers +v0x2464770_0 .net *"_s646", 0 0, L_0x24aa7a0; 1 drivers +v0x2464650_0 .net *"_s671", 0 0, L_0x24ace00; 1 drivers +v0x24646f0_0 .net *"_s696", 0 0, L_0x24af5a0; 1 drivers +v0x2464930_0 .net *"_s71", 0 0, L_0x2470d20; 1 drivers +v0x24649b0_0 .net *"_s721", 0 0, L_0x24b18c0; 1 drivers +v0x24647f0_0 .net *"_s746", 0 0, L_0x24b43e0; 1 drivers +v0x2464890_0 .net *"_s771", 0 0, L_0x24b6480; 1 drivers +v0x2464b90_0 .net *"_s811", 0 0, L_0x249f5b0; 1 drivers +v0x2464c10_0 .net *"_s814", 0 0, L_0x249f6f0; 1 drivers +v0x2464a30_0 .net *"_s816", 0 0, L_0x2492a20; 1 drivers +v0x2464ad0_0 .net *"_s818", 0 0, L_0x2492c00; 1 drivers +v0x2464e10_0 .net *"_s96", 0 0, L_0x24736d0; 1 drivers +v0x2464e90_0 .net "carryin", 31 0, C4; 0 drivers +v0x2464cc0_0 .net "carryout", 0 0, L_0x24e21f0; 1 drivers +v0x2464d70_0 .net "overflow", 0 0, L_0x24e2410; 1 drivers +RS_0x7fd6f9610e68/0/0 .resolv tri, L_0x2478a70, L_0x24bb9a0, L_0x24bcdd0, L_0x24bd200; +RS_0x7fd6f9610e68/0/4 .resolv tri, L_0x24be680, L_0x24bfc00, L_0x24c1070, L_0x24c24a0; +RS_0x7fd6f9610e68/0/8 .resolv tri, L_0x24c3d70, L_0x24c50c0, L_0x24c6600, L_0x24c7b40; +RS_0x7fd6f9610e68/0/12 .resolv tri, L_0x24c8ff0, L_0x24ca5e0, L_0x24cbc60, L_0x24cd240; +RS_0x7fd6f9610e68/0/16 .resolv tri, L_0x24ceb60, L_0x24cfdb0, L_0x24d1250, L_0x24d2300; +RS_0x7fd6f9610e68/0/20 .resolv tri, L_0x24d36d0, L_0x24d4b10, L_0x24d6020, L_0x24d73e0; +RS_0x7fd6f9610e68/0/24 .resolv tri, L_0x24d8830, L_0x24d9d20, L_0x24db200, L_0x24dc6e0; +RS_0x7fd6f9610e68/0/28 .resolv tri, L_0x24ddbe0, L_0x24dfa40, L_0x24e09a0, L_0x24e1e90; +RS_0x7fd6f9610e68/1/0 .resolv tri, RS_0x7fd6f9610e68/0/0, RS_0x7fd6f9610e68/0/4, RS_0x7fd6f9610e68/0/8, RS_0x7fd6f9610e68/0/12; +RS_0x7fd6f9610e68/1/4 .resolv tri, RS_0x7fd6f9610e68/0/16, RS_0x7fd6f9610e68/0/20, RS_0x7fd6f9610e68/0/24, RS_0x7fd6f9610e68/0/28; +RS_0x7fd6f9610e68 .resolv tri, RS_0x7fd6f9610e68/1/0, RS_0x7fd6f9610e68/1/4, C4, C4; +v0x24650e0_0 .net8 "subtract", 31 0, RS_0x7fd6f9610e68; 32 drivers +v0x2465160_0 .net "yeszero", 0 0, L_0x2492b10; 1 drivers +L_0x2469c90 .part/pv L_0x2469a80, 1, 1, 32; +L_0x2469d30 .part C4, 0, 1; +L_0x2469e60 .part C4, 1, 1; +L_0x2469f90 .part RS_0x7fd6f9610aa8, 1, 1; +L_0x246a030 .part RS_0x7fd6f9610aa8, 1, 1; +L_0x246a120 .part RS_0x7fd6f9606848, 1, 1; +L_0x246a2a0 .part RS_0x7fd6f9610aa8, 1, 1; +L_0x246ac00 .part/pv L_0x246a9f0, 1, 1, 32; +L_0x246acf0 .part C4, 0, 1; +L_0x246ae20 .part C4, 1, 1; +L_0x246afb0 .part RS_0x7fd6f9609e78, 1, 1; +L_0x246b050 .part RS_0x7fd6f9609e78, 1, 1; +L_0x246b0f0 .part RS_0x7fd6f9606848, 1, 1; +L_0x246b1e0 .part RS_0x7fd6f9606848, 1, 1; +L_0x246b680 .part/pv L_0x246b540, 1, 1, 32; +L_0x246b720 .part C4, 2, 1; +L_0x246b850 .part RS_0x7fd6f9610ec8, 1, 1; +L_0x246b990 .part RS_0x7fd6f9610ef8, 1, 1; +L_0x246bb70 .part/pv L_0x246b7c0, 1, 1, 32; +L_0x246bcf0 .part RS_0x7fd6f9610f58, 0, 1; +L_0x246bad0 .part RS_0x7fd6f9610f28, 1, 1; +L_0x246c730 .part/pv L_0x246c520, 2, 1, 32; +L_0x246bde0 .part C4, 0, 1; +L_0x246c920 .part C4, 1, 1; +L_0x246c7d0 .part RS_0x7fd6f9610aa8, 2, 1; +L_0x246cb20 .part RS_0x7fd6f9610aa8, 2, 1; +L_0x246ca50 .part RS_0x7fd6f9606848, 2, 1; +L_0x246ccf0 .part RS_0x7fd6f9610aa8, 2, 1; +L_0x246d620 .part/pv L_0x246d410, 2, 1, 32; +L_0x246d6c0 .part C4, 0, 1; +L_0x246cde0 .part C4, 1, 1; +L_0x246d980 .part RS_0x7fd6f9609e78, 2, 1; +L_0x246d7f0 .part RS_0x7fd6f9609e78, 2, 1; +L_0x246dbc0 .part RS_0x7fd6f9606848, 2, 1; +L_0x246dab0 .part RS_0x7fd6f9606848, 2, 1; +L_0x246e0f0 .part/pv L_0x246dfb0, 2, 1, 32; +L_0x246dc60 .part C4, 2, 1; +L_0x246e2c0 .part RS_0x7fd6f9610ec8, 2, 1; +L_0x246e190 .part RS_0x7fd6f9610ef8, 2, 1; +L_0x246e530 .part/pv L_0x246e3f0, 2, 1, 32; +L_0x246e720 .part RS_0x7fd6f9610f58, 1, 1; +L_0x246e850 .part RS_0x7fd6f9610f28, 2, 1; +L_0x246f0d0 .part/pv L_0x246eec0, 3, 1, 32; +L_0x246f170 .part C4, 0, 1; +L_0x246e980 .part C4, 1, 1; +L_0x246f410 .part RS_0x7fd6f9610aa8, 3, 1; +L_0x246f2a0 .part RS_0x7fd6f9610aa8, 3, 1; +L_0x246f340 .part RS_0x7fd6f9606848, 3, 1; +L_0x246f5c0 .part RS_0x7fd6f9610aa8, 3, 1; +L_0x2470080 .part/pv L_0x246fe70, 3, 1, 32; +L_0x246f850 .part C4, 0, 1; +L_0x24702c0 .part C4, 1, 1; +L_0x2470120 .part RS_0x7fd6f9609e78, 3, 1; +L_0x24701c0 .part RS_0x7fd6f9609e78, 3, 1; +L_0x24705b0 .part RS_0x7fd6f9606848, 3, 1; +L_0x2470650 .part RS_0x7fd6f9606848, 3, 1; +L_0x2470b40 .part/pv L_0x2470a00, 3, 1, 32; +L_0x2470be0 .part C4, 2, 1; +L_0x24706f0 .part RS_0x7fd6f9610ec8, 3, 1; +L_0x24707e0 .part RS_0x7fd6f9610ef8, 3, 1; +L_0x2470c80 .part/pv L_0x2470d20, 3, 1, 32; +L_0x24710a0 .part RS_0x7fd6f9610f58, 2, 1; +L_0x2470eb0 .part RS_0x7fd6f9610f28, 3, 1; +L_0x2471a70 .part/pv L_0x2471860, 4, 1, 32; +L_0x2471140 .part C4, 0, 1; +L_0x2471270 .part C4, 1, 1; +L_0x2471b10 .part RS_0x7fd6f9610aa8, 4, 1; +L_0x2471bb0 .part RS_0x7fd6f9610aa8, 4, 1; +L_0x2471c50 .part RS_0x7fd6f9606848, 4, 1; +L_0x2472030 .part RS_0x7fd6f9610aa8, 4, 1; +L_0x2472930 .part/pv L_0x2472720, 4, 1, 32; +L_0x24729d0 .part C4, 0, 1; +L_0x2472120 .part C4, 1, 1; +L_0x2472250 .part RS_0x7fd6f9609e78, 4, 1; +L_0x2472b00 .part RS_0x7fd6f9609e78, 4, 1; +L_0x2472ba0 .part RS_0x7fd6f9606848, 4, 1; +L_0x2472c90 .part RS_0x7fd6f9606848, 4, 1; +L_0x2473480 .part/pv L_0x2473340, 4, 1, 32; +L_0x2472e60 .part C4, 2, 1; +L_0x2472f00 .part RS_0x7fd6f9610ec8, 4, 1; +L_0x2472ff0 .part RS_0x7fd6f9610ef8, 4, 1; +L_0x2473630 .part/pv L_0x24736d0, 4, 1, 32; +L_0x2473b50 .part RS_0x7fd6f9610f58, 3, 1; +L_0x2473d00 .part RS_0x7fd6f9610f28, 4, 1; +L_0x2474510 .part/pv L_0x2474330, 5, 1, 32; +L_0x24745b0 .part C4, 0, 1; +L_0x2473eb0 .part C4, 1, 1; +L_0x2473fe0 .part RS_0x7fd6f9610aa8, 5, 1; +L_0x2474080 .part RS_0x7fd6f9610aa8, 5, 1; +L_0x24749b0 .part RS_0x7fd6f9606848, 5, 1; +L_0x24746e0 .part RS_0x7fd6f9610aa8, 5, 1; +L_0x24753d0 .part/pv L_0x24751f0, 5, 1, 32; +L_0x2474aa0 .part C4, 0, 1; +L_0x2474bd0 .part C4, 1, 1; +L_0x2475770 .part RS_0x7fd6f9609e78, 5, 1; +L_0x2475810 .part RS_0x7fd6f9609e78, 5, 1; +L_0x2475470 .part RS_0x7fd6f9606848, 5, 1; +L_0x2475560 .part RS_0x7fd6f9606848, 5, 1; +L_0x2475a80 .part/pv L_0x2475940, 5, 1, 32; +L_0x2475b20 .part C4, 2, 1; +L_0x2476100 .part RS_0x7fd6f9610ec8, 5, 1; +L_0x24761f0 .part RS_0x7fd6f9610ef8, 5, 1; +L_0x2475dd0 .part/pv L_0x2475e70, 5, 1, 32; +L_0x2475fb0 .part RS_0x7fd6f9610f58, 4, 1; +L_0x2476050 .part RS_0x7fd6f9610f28, 5, 1; +L_0x2476df0 .part/pv L_0x2476c10, 6, 1, 32; +L_0x24762e0 .part C4, 0, 1; +L_0x2476410 .part C4, 1, 1; +L_0x2476540 .part RS_0x7fd6f9610aa8, 6, 1; +L_0x2477200 .part RS_0x7fd6f9610aa8, 6, 1; +L_0x2476e90 .part RS_0x7fd6f9606848, 6, 1; +L_0x2476f30 .part RS_0x7fd6f9610aa8, 6, 1; +L_0x2477bc0 .part/pv L_0x24779e0, 6, 1, 32; +L_0x2477c60 .part C4, 0, 1; +L_0x24772a0 .part C4, 1, 1; +L_0x24773d0 .part RS_0x7fd6f9609e78, 6, 1; +L_0x2477470 .part RS_0x7fd6f9609e78, 6, 1; +L_0x2477510 .part RS_0x7fd6f9606848, 6, 1; +L_0x2477d90 .part RS_0x7fd6f9606848, 6, 1; +L_0x243e8f0 .part/pv L_0x24780d0, 6, 1, 32; +L_0x243e990 .part C4, 2, 1; +L_0x243ea30 .part RS_0x7fd6f9610ec8, 6, 1; +L_0x243eb20 .part RS_0x7fd6f9610ef8, 6, 1; +L_0x243ec10 .part/pv L_0x243e4e0, 6, 1, 32; +L_0x243e5e0 .part RS_0x7fd6f9610f58, 5, 1; +L_0x243e680 .part RS_0x7fd6f9610f28, 6, 1; +L_0x2479b60 .part/pv L_0x2479980, 7, 1, 32; +L_0x2479c00 .part C4, 0, 1; +L_0x2479140 .part C4, 1, 1; +L_0x2479270 .part RS_0x7fd6f9610aa8, 7, 1; +L_0x2479310 .part RS_0x7fd6f9610aa8, 7, 1; +L_0x24793b0 .part RS_0x7fd6f9606848, 7, 1; +L_0x24794a0 .part RS_0x7fd6f9610aa8, 7, 1; +L_0x247a920 .part/pv L_0x247a740, 7, 1, 32; +L_0x2479d30 .part C4, 0, 1; +L_0x2479e60 .part C4, 1, 1; +L_0x2479f90 .part RS_0x7fd6f9609e78, 7, 1; +L_0x247a030 .part RS_0x7fd6f9609e78, 7, 1; +L_0x247ae20 .part RS_0x7fd6f9606848, 7, 1; +L_0x247aec0 .part RS_0x7fd6f9606848, 7, 1; +L_0x247b420 .part/pv L_0x247ac50, 7, 1, 32; +L_0x247b4c0 .part C4, 2, 1; +L_0x247afb0 .part RS_0x7fd6f9610ec8, 7, 1; +L_0x247b0a0 .part RS_0x7fd6f9610ef8, 7, 1; +L_0x247b190 .part/pv L_0x247b230, 7, 1, 32; +L_0x247b370 .part RS_0x7fd6f9610f58, 6, 1; +L_0x247ba00 .part RS_0x7fd6f9610f28, 7, 1; +L_0x247c1d0 .part/pv L_0x247bff0, 8, 1, 32; +L_0x247b560 .part C4, 0, 1; +L_0x247b690 .part C4, 1, 1; +L_0x247b7c0 .part RS_0x7fd6f9610aa8, 8, 1; +L_0x247b860 .part RS_0x7fd6f9610aa8, 8, 1; +L_0x247b900 .part RS_0x7fd6f9606848, 8, 1; +L_0x247c740 .part RS_0x7fd6f9610aa8, 8, 1; +L_0x247cfd0 .part/pv L_0x247cdf0, 8, 1, 32; +L_0x247d070 .part C4, 0, 1; +L_0x247c830 .part C4, 1, 1; +L_0x247c960 .part RS_0x7fd6f9609e78, 8, 1; +L_0x247cc10 .part RS_0x7fd6f9609e78, 8, 1; +L_0x2472d50 .part RS_0x7fd6f9606848, 8, 1; +L_0x247d6b0 .part RS_0x7fd6f9606848, 8, 1; +L_0x247db60 .part/pv L_0x247da20, 8, 1, 32; +L_0x247d1a0 .part C4, 2, 1; +L_0x247d240 .part RS_0x7fd6f9610ec8, 8, 1; +L_0x24737a0 .part RS_0x7fd6f9610ef8, 8, 1; +L_0x2473520 .part/pv L_0x24735c0, 8, 1, 32; +L_0x247dc00 .part RS_0x7fd6f9610f58, 7, 1; +L_0x2473bf0 .part RS_0x7fd6f9610f28, 8, 1; +L_0x247ee10 .part/pv L_0x247ec30, 9, 1, 32; +L_0x247eeb0 .part C4, 0, 1; +L_0x247e340 .part C4, 1, 1; +L_0x247e470 .part RS_0x7fd6f9610aa8, 9, 1; +L_0x247e510 .part RS_0x7fd6f9610aa8, 9, 1; +L_0x247e5b0 .part RS_0x7fd6f9606848, 9, 1; +L_0x247e6a0 .part RS_0x7fd6f9610aa8, 9, 1; +L_0x247fbd0 .part/pv L_0x247f9f0, 9, 1, 32; +L_0x247efe0 .part C4, 0, 1; +L_0x247f110 .part C4, 1, 1; +L_0x247f240 .part RS_0x7fd6f9609e78, 9, 1; +L_0x247f2e0 .part RS_0x7fd6f9609e78, 9, 1; +L_0x247f380 .part RS_0x7fd6f9606848, 9, 1; +L_0x247f470 .part RS_0x7fd6f9606848, 9, 1; +L_0x2480640 .part/pv L_0x2480500, 9, 1, 32; +L_0x24806e0 .part C4, 2, 1; +L_0x247fc70 .part RS_0x7fd6f9610ec8, 9, 1; +L_0x247fd60 .part RS_0x7fd6f9610ef8, 9, 1; +L_0x247fe50 .part/pv L_0x247fef0, 9, 1, 32; +L_0x2480030 .part RS_0x7fd6f9610f58, 8, 1; +L_0x24800d0 .part RS_0x7fd6f9610f28, 9, 1; +L_0x2481480 .part/pv L_0x24812a0, 10, 1, 32; +L_0x2480780 .part C4, 0, 1; +L_0x24808b0 .part C4, 1, 1; +L_0x24809e0 .part RS_0x7fd6f9610aa8, 10, 1; +L_0x2480a80 .part RS_0x7fd6f9610aa8, 10, 1; +L_0x2480b20 .part RS_0x7fd6f9606848, 10, 1; +L_0x2480c10 .part RS_0x7fd6f9610aa8, 10, 1; +L_0x2482260 .part/pv L_0x2482080, 10, 1, 32; +L_0x2482300 .part C4, 0, 1; +L_0x2481520 .part C4, 1, 1; +L_0x2481650 .part RS_0x7fd6f9609e78, 10, 1; +L_0x24816f0 .part RS_0x7fd6f9609e78, 10, 1; +L_0x2481790 .part RS_0x7fd6f9606848, 10, 1; +L_0x2481880 .part RS_0x7fd6f9606848, 10, 1; +L_0x2482cc0 .part/pv L_0x2482b80, 10, 1, 32; +L_0x2482430 .part C4, 2, 1; +L_0x24824d0 .part RS_0x7fd6f9610ec8, 10, 1; +L_0x24825c0 .part RS_0x7fd6f9610ef8, 10, 1; +L_0x24826b0 .part/pv L_0x2482750, 10, 1, 32; +L_0x2482890 .part RS_0x7fd6f9610f58, 9, 1; +L_0x2482930 .part RS_0x7fd6f9610f28, 10, 1; +L_0x2483b10 .part/pv L_0x2483930, 11, 1, 32; +L_0x2483bb0 .part C4, 0, 1; +L_0x2482d60 .part C4, 1, 1; +L_0x2482e90 .part RS_0x7fd6f9610aa8, 11, 1; +L_0x2483340 .part RS_0x7fd6f9610aa8, 11, 1; +L_0x2474d80 .part RS_0x7fd6f9606848, 11, 1; +L_0x2474e70 .part RS_0x7fd6f9610aa8, 11, 1; +L_0x2484260 .part/pv L_0x2484080, 11, 1, 32; +L_0x2484300 .part C4, 0, 1; +L_0x2484f20 .part C4, 1, 1; +L_0x24847b0 .part RS_0x7fd6f9609e78, 11, 1; +L_0x2484850 .part RS_0x7fd6f9609e78, 11, 1; +L_0x24848f0 .part RS_0x7fd6f9606848, 11, 1; +L_0x24849e0 .part RS_0x7fd6f9606848, 11, 1; +L_0x24857b0 .part/pv L_0x2484da0, 11, 1, 32; +L_0x2485850 .part C4, 2, 1; +L_0x2485050 .part RS_0x7fd6f9610ec8, 11, 1; +L_0x2485140 .part RS_0x7fd6f9610ef8, 11, 1; +L_0x2485230 .part/pv L_0x24852d0, 11, 1, 32; +L_0x2485410 .part RS_0x7fd6f9610f58, 10, 1; +L_0x24854b0 .part RS_0x7fd6f9610f28, 11, 1; +L_0x2486610 .part/pv L_0x2486430, 12, 1, 32; +L_0x24858f0 .part C4, 0, 1; +L_0x2485a20 .part C4, 1, 1; +L_0x2485b50 .part RS_0x7fd6f9610aa8, 12, 1; +L_0x2485bf0 .part RS_0x7fd6f9610aa8, 12, 1; +L_0x2485c90 .part RS_0x7fd6f9606848, 12, 1; +L_0x2485d80 .part RS_0x7fd6f9610aa8, 12, 1; +L_0x2487410 .part/pv L_0x2487230, 12, 1, 32; +L_0x24874b0 .part C4, 0, 1; +L_0x24866b0 .part C4, 1, 1; +L_0x24867e0 .part RS_0x7fd6f9609e78, 12, 1; +L_0x2486880 .part RS_0x7fd6f9609e78, 12, 1; +L_0x2486920 .part RS_0x7fd6f9606848, 12, 1; +L_0x2486a10 .part RS_0x7fd6f9606848, 12, 1; +L_0x2487e70 .part/pv L_0x2486dd0, 12, 1, 32; +L_0x24875e0 .part C4, 2, 1; +L_0x2487680 .part RS_0x7fd6f9610ec8, 12, 1; +L_0x2487770 .part RS_0x7fd6f9610ef8, 12, 1; +L_0x2487860 .part/pv L_0x2487900, 12, 1, 32; +L_0x2487a40 .part RS_0x7fd6f9610f58, 11, 1; +L_0x2487ae0 .part RS_0x7fd6f9610f28, 12, 1; +L_0x2488d20 .part/pv L_0x2488b40, 13, 1, 32; +L_0x2488dc0 .part C4, 0, 1; +L_0x2487f10 .part C4, 1, 1; +L_0x2488040 .part RS_0x7fd6f9610aa8, 13, 1; +L_0x24880e0 .part RS_0x7fd6f9610aa8, 13, 1; +L_0x2488180 .part RS_0x7fd6f9606848, 13, 1; +L_0x2488270 .part RS_0x7fd6f9610aa8, 13, 1; +L_0x2489b50 .part/pv L_0x2489970, 13, 1, 32; +L_0x2488ef0 .part C4, 0, 1; +L_0x2489020 .part C4, 1, 1; +L_0x2489150 .part RS_0x7fd6f9609e78, 13, 1; +L_0x24891f0 .part RS_0x7fd6f9609e78, 13, 1; +L_0x2489290 .part RS_0x7fd6f9606848, 13, 1; +L_0x2489380 .part RS_0x7fd6f9606848, 13, 1; +L_0x248a5e0 .part/pv L_0x248a4a0, 13, 1, 32; +L_0x248a680 .part C4, 2, 1; +L_0x2489bf0 .part RS_0x7fd6f9610ec8, 13, 1; +L_0x2489ce0 .part RS_0x7fd6f9610ef8, 13, 1; +L_0x2489dd0 .part/pv L_0x2489e70, 13, 1, 32; +L_0x2489fb0 .part RS_0x7fd6f9610f58, 12, 1; +L_0x248a050 .part RS_0x7fd6f9610f28, 13, 1; +L_0x248b450 .part/pv L_0x248b270, 14, 1, 32; +L_0x248a720 .part C4, 0, 1; +L_0x248a850 .part C4, 1, 1; +L_0x248a980 .part RS_0x7fd6f9610aa8, 14, 1; +L_0x248aa20 .part RS_0x7fd6f9610aa8, 14, 1; +L_0x248aac0 .part RS_0x7fd6f9606848, 14, 1; +L_0x248abb0 .part RS_0x7fd6f9610aa8, 14, 1; +L_0x248c220 .part/pv L_0x248c040, 14, 1, 32; +L_0x248c2c0 .part C4, 0, 1; +L_0x248b4f0 .part C4, 1, 1; +L_0x248b620 .part RS_0x7fd6f9609e78, 14, 1; +L_0x248b6c0 .part RS_0x7fd6f9609e78, 14, 1; +L_0x248b760 .part RS_0x7fd6f9606848, 14, 1; +L_0x248b850 .part RS_0x7fd6f9606848, 14, 1; +L_0x248ccf0 .part/pv L_0x248bc10, 14, 1, 32; +L_0x248c3f0 .part C4, 2, 1; +L_0x248c490 .part RS_0x7fd6f9610ec8, 14, 1; +L_0x248c580 .part RS_0x7fd6f9610ef8, 14, 1; +L_0x248c670 .part/pv L_0x248c710, 14, 1, 32; +L_0x248c850 .part RS_0x7fd6f9610f58, 13, 1; +L_0x248c8f0 .part RS_0x7fd6f9610f28, 14, 1; +L_0x248dad0 .part/pv L_0x248d8f0, 15, 1, 32; +L_0x248db70 .part C4, 0, 1; +L_0x248cd90 .part C4, 1, 1; +L_0x248cec0 .part RS_0x7fd6f9610aa8, 15, 1; +L_0x248cf60 .part RS_0x7fd6f9610aa8, 15, 1; +L_0x248d000 .part RS_0x7fd6f9606848, 15, 1; +L_0x248d0f0 .part RS_0x7fd6f9610aa8, 15, 1; +L_0x248e870 .part/pv L_0x248e690, 15, 1, 32; +L_0x248dca0 .part C4, 0, 1; +L_0x248ddd0 .part C4, 1, 1; +L_0x248df00 .part RS_0x7fd6f9609e78, 15, 1; +L_0x248dfa0 .part RS_0x7fd6f9609e78, 15, 1; +L_0x248e040 .part RS_0x7fd6f9606848, 15, 1; +L_0x248e130 .part RS_0x7fd6f9606848, 15, 1; +L_0x248f2c0 .part/pv L_0x248e490, 15, 1, 32; +L_0x248f360 .part C4, 2, 1; +L_0x248e910 .part RS_0x7fd6f9610ec8, 15, 1; +L_0x248ea00 .part RS_0x7fd6f9610ef8, 15, 1; +L_0x248eaf0 .part/pv L_0x248eb90, 15, 1, 32; +L_0x248ec90 .part RS_0x7fd6f9610f58, 14, 1; +L_0x248ed30 .part RS_0x7fd6f9610f28, 15, 1; +L_0x24900b0 .part/pv L_0x248fed0, 16, 1, 32; +L_0x248f400 .part C4, 0, 1; +L_0x248f530 .part C4, 1, 1; +L_0x248f660 .part RS_0x7fd6f9610aa8, 16, 1; +L_0x248f700 .part RS_0x7fd6f9610aa8, 16, 1; +L_0x248f7a0 .part RS_0x7fd6f9606848, 16, 1; +L_0x248f890 .part RS_0x7fd6f9610aa8, 16, 1; +L_0x2490e80 .part/pv L_0x2490ca0, 16, 1, 32; +L_0x2490f20 .part C4, 0, 1; +L_0x2490150 .part C4, 1, 1; +L_0x2490280 .part RS_0x7fd6f9609e78, 16, 1; +L_0x247ca00 .part RS_0x7fd6f9609e78, 16, 1; +L_0x247caa0 .part RS_0x7fd6f9606848, 16, 1; +L_0x2490730 .part RS_0x7fd6f9606848, 16, 1; +L_0x2491af0 .part/pv L_0x2490ab0, 16, 1, 32; +L_0x2491050 .part C4, 2, 1; +L_0x24910f0 .part RS_0x7fd6f9610ec8, 16, 1; +L_0x247d330 .part RS_0x7fd6f9610ef8, 16, 1; +L_0x2491a00 .part/pv L_0x247d420, 16, 1, 32; +L_0x247e130 .part RS_0x7fd6f9610f58, 15, 1; +L_0x247e1d0 .part RS_0x7fd6f9610f28, 16, 1; +L_0x2491ea0 .part/pv L_0x2491cc0, 17, 1, 32; +L_0x2491f40 .part C4, 0, 1; +L_0x2492070 .part C4, 1, 1; +L_0x24921a0 .part RS_0x7fd6f9610aa8, 17, 1; +L_0x2492240 .part RS_0x7fd6f9610aa8, 17, 1; +L_0x24922e0 .part RS_0x7fd6f9606848, 17, 1; +L_0x24923d0 .part RS_0x7fd6f9610aa8, 17, 1; +L_0x2493f70 .part/pv L_0x2493d60, 17, 1, 32; +L_0x2492e30 .part C4, 0, 1; +L_0x2492f60 .part C4, 1, 1; +L_0x2493090 .part RS_0x7fd6f9609e78, 17, 1; +L_0x2493130 .part RS_0x7fd6f9609e78, 17, 1; +L_0x24931d0 .part RS_0x7fd6f9606848, 17, 1; +L_0x24932c0 .part RS_0x7fd6f9606848, 17, 1; +L_0x2493760 .part/pv L_0x2493620, 17, 1, 32; +L_0x2493800 .part C4, 2, 1; +L_0x2494b20 .part RS_0x7fd6f9610ec8, 17, 1; +L_0x2494bc0 .part RS_0x7fd6f9610ef8, 17, 1; +L_0x2494010 .part/pv L_0x24940b0, 17, 1, 32; +L_0x24941f0 .part RS_0x7fd6f9610f58, 16, 1; +L_0x2494290 .part RS_0x7fd6f9610f28, 17, 1; +L_0x2495870 .part/pv L_0x2494970, 18, 1, 32; +L_0x2494cb0 .part C4, 0, 1; +L_0x2494de0 .part C4, 1, 1; +L_0x2494f10 .part RS_0x7fd6f9610aa8, 18, 1; +L_0x2494fb0 .part RS_0x7fd6f9610aa8, 18, 1; +L_0x2495050 .part RS_0x7fd6f9606848, 18, 1; +L_0x2495140 .part RS_0x7fd6f9610aa8, 18, 1; +L_0x24966d0 .part/pv L_0x24964c0, 18, 1, 32; +L_0x2496770 .part C4, 0, 1; +L_0x2495910 .part C4, 1, 1; +L_0x2495a40 .part RS_0x7fd6f9609e78, 18, 1; +L_0x2495ae0 .part RS_0x7fd6f9609e78, 18, 1; +L_0x2495b80 .part RS_0x7fd6f9606848, 18, 1; +L_0x2495c70 .part RS_0x7fd6f9606848, 18, 1; +L_0x2496130 .part/pv L_0x2495ff0, 18, 1, 32; +L_0x24961d0 .part C4, 2, 1; +L_0x2496270 .part RS_0x7fd6f9610ec8, 18, 1; +L_0x2496360 .part RS_0x7fd6f9610ef8, 18, 1; +L_0x2497460 .part/pv L_0x24968a0, 18, 1, 32; +L_0x24969e0 .part RS_0x7fd6f9610f58, 17, 1; +L_0x2496a80 .part RS_0x7fd6f9610f28, 18, 1; +L_0x2497340 .part/pv L_0x2497130, 19, 1, 32; +L_0x24980e0 .part C4, 0, 1; +L_0x2497500 .part C4, 1, 1; +L_0x2497630 .part RS_0x7fd6f9610aa8, 19, 1; +L_0x24976d0 .part RS_0x7fd6f9610aa8, 19, 1; +L_0x2497770 .part RS_0x7fd6f9606848, 19, 1; +L_0x2497860 .part RS_0x7fd6f9610aa8, 19, 1; +L_0x2498e70 .part/pv L_0x2497f60, 19, 1, 32; +L_0x2498210 .part C4, 0, 1; +L_0x2498340 .part C4, 1, 1; +L_0x2498470 .part RS_0x7fd6f9609e78, 19, 1; +L_0x2498510 .part RS_0x7fd6f9609e78, 19, 1; +L_0x24985b0 .part RS_0x7fd6f9606848, 19, 1; +L_0x24986a0 .part RS_0x7fd6f9606848, 19, 1; +L_0x2498b00 .part/pv L_0x24989c0, 19, 1, 32; +L_0x2498ba0 .part C4, 2, 1; +L_0x2498c40 .part RS_0x7fd6f9610ec8, 19, 1; +L_0x2498d30 .part RS_0x7fd6f9610ef8, 19, 1; +L_0x2499b80 .part/pv L_0x2499c20, 19, 1, 32; +L_0x2499d60 .part RS_0x7fd6f9610f58, 18, 1; +L_0x2498f10 .part RS_0x7fd6f9610f28, 19, 1; +L_0x2499800 .part/pv L_0x24995f0, 20, 1, 32; +L_0x24998a0 .part C4, 0, 1; +L_0x24999d0 .part C4, 1, 1; +L_0x249aaa0 .part RS_0x7fd6f9610aa8, 20, 1; +L_0x249ab40 .part RS_0x7fd6f9610aa8, 20, 1; +L_0x2499e00 .part RS_0x7fd6f9606848, 20, 1; +L_0x2499ef0 .part RS_0x7fd6f9610aa8, 20, 1; +L_0x249a810 .part/pv L_0x249a600, 20, 1, 32; +L_0x249a8b0 .part C4, 0, 1; +L_0x249a9e0 .part C4, 1, 1; +L_0x249b940 .part RS_0x7fd6f9609e78, 20, 1; +L_0x249abe0 .part RS_0x7fd6f9609e78, 20, 1; +L_0x249ac80 .part RS_0x7fd6f9606848, 20, 1; +L_0x249ad70 .part RS_0x7fd6f9606848, 20, 1; +L_0x249b230 .part/pv L_0x249b0f0, 20, 1, 32; +L_0x249b2d0 .part C4, 2, 1; +L_0x249b370 .part RS_0x7fd6f9610ec8, 20, 1; +L_0x249b460 .part RS_0x7fd6f9610ef8, 20, 1; +L_0x249b550 .part/pv L_0x249b5f0, 20, 1, 32; +L_0x249b730 .part RS_0x7fd6f9610f58, 19, 1; +L_0x249b7d0 .part RS_0x7fd6f9610f28, 20, 1; +L_0x249ced0 .part/pv L_0x249ccc0, 21, 1, 32; +L_0x249cf70 .part C4, 0, 1; +L_0x249b9e0 .part C4, 1, 1; +L_0x249bb10 .part RS_0x7fd6f9610aa8, 21, 1; +L_0x249bbb0 .part RS_0x7fd6f9610aa8, 21, 1; +L_0x249bc50 .part RS_0x7fd6f9606848, 21, 1; +L_0x249bd40 .part RS_0x7fd6f9610aa8, 21, 1; +L_0x249e180 .part/pv L_0x249df70, 21, 1, 32; +L_0x249d0a0 .part C4, 0, 1; +L_0x249d1d0 .part C4, 1, 1; +L_0x249d300 .part RS_0x7fd6f9609e78, 21, 1; +L_0x249d3a0 .part RS_0x7fd6f9609e78, 21, 1; +L_0x249d440 .part RS_0x7fd6f9606848, 21, 1; +L_0x249d530 .part RS_0x7fd6f9606848, 21, 1; +L_0x2484710 .part/pv L_0x24845d0, 21, 1, 32; +L_0x249d620 .part C4, 2, 1; +L_0x249d6c0 .part RS_0x7fd6f9610ec8, 21, 1; +L_0x249d7b0 .part RS_0x7fd6f9610ef8, 21, 1; +L_0x249d8a0 .part/pv L_0x249d940, 21, 1, 32; +L_0x249da80 .part RS_0x7fd6f9610f58, 20, 1; +L_0x249db20 .part RS_0x7fd6f9610f28, 21, 1; +L_0x249e890 .part/pv L_0x249e680, 22, 1, 32; +L_0x249e930 .part C4, 0, 1; +L_0x249ea60 .part C4, 1, 1; +L_0x249eb90 .part RS_0x7fd6f9610aa8, 22, 1; +L_0x249ec30 .part RS_0x7fd6f9610aa8, 22, 1; +L_0x249ecd0 .part RS_0x7fd6f9606848, 22, 1; +L_0x249edc0 .part RS_0x7fd6f9610aa8, 22, 1; +L_0x24a0d00 .part/pv L_0x24a0af0, 22, 1, 32; +L_0x24a0da0 .part C4, 0, 1; +L_0x249f7c0 .part C4, 1, 1; +L_0x249f8f0 .part RS_0x7fd6f9609e78, 22, 1; +L_0x249f990 .part RS_0x7fd6f9609e78, 22, 1; +L_0x249fa30 .part RS_0x7fd6f9606848, 22, 1; +L_0x249fb20 .part RS_0x7fd6f9606848, 22, 1; +L_0x24a0020 .part/pv L_0x249fee0, 22, 1, 32; +L_0x24a00c0 .part C4, 2, 1; +L_0x24a0160 .part RS_0x7fd6f9610ec8, 22, 1; +L_0x24a0250 .part RS_0x7fd6f9610ef8, 22, 1; +L_0x24a0340 .part/pv L_0x24a03e0, 22, 1, 32; +L_0x24a0520 .part RS_0x7fd6f9610f58, 21, 1; +L_0x24a1d40 .part RS_0x7fd6f9610f28, 22, 1; +L_0x24a1700 .part/pv L_0x24a14f0, 23, 1, 32; +L_0x24a17a0 .part C4, 0, 1; +L_0x24a18d0 .part C4, 1, 1; +L_0x24a1a00 .part RS_0x7fd6f9610aa8, 23, 1; +L_0x24a1aa0 .part RS_0x7fd6f9610aa8, 23, 1; +L_0x24a1b40 .part RS_0x7fd6f9606848, 23, 1; +L_0x24a1c30 .part RS_0x7fd6f9610aa8, 23, 1; +L_0x24a3540 .part/pv L_0x24a3330, 23, 1, 32; +L_0x24a1e30 .part C4, 0, 1; +L_0x24a1f60 .part C4, 1, 1; +L_0x24a2090 .part RS_0x7fd6f9609e78, 23, 1; +L_0x24a2130 .part RS_0x7fd6f9609e78, 23, 1; +L_0x24a21d0 .part RS_0x7fd6f9606848, 23, 1; +L_0x24a22c0 .part RS_0x7fd6f9606848, 23, 1; +L_0x24a2760 .part/pv L_0x24a2620, 23, 1, 32; +L_0x24a2800 .part C4, 2, 1; +L_0x24a28a0 .part RS_0x7fd6f9610ec8, 23, 1; +L_0x24a2990 .part RS_0x7fd6f9610ef8, 23, 1; +L_0x24a2a80 .part/pv L_0x24a2b20, 23, 1, 32; +L_0x24a44f0 .part RS_0x7fd6f9610f58, 22, 1; +L_0x24a35e0 .part RS_0x7fd6f9610f28, 23, 1; +L_0x24a3ed0 .part/pv L_0x24a3cc0, 24, 1, 32; +L_0x24a3f70 .part C4, 0, 1; +L_0x24a40a0 .part C4, 1, 1; +L_0x24a41d0 .part RS_0x7fd6f9610aa8, 24, 1; +L_0x24a4270 .part RS_0x7fd6f9610aa8, 24, 1; +L_0x24a4310 .part RS_0x7fd6f9606848, 24, 1; +L_0x24a4400 .part RS_0x7fd6f9610aa8, 24, 1; +L_0x24a5cc0 .part/pv L_0x24a5ab0, 24, 1, 32; +L_0x24a5d60 .part C4, 0, 1; +L_0x24a4590 .part C4, 1, 1; +L_0x24a46c0 .part RS_0x7fd6f9609e78, 24, 1; +L_0x24a4760 .part RS_0x7fd6f9609e78, 24, 1; +L_0x24a4800 .part RS_0x7fd6f9606848, 24, 1; +L_0x24a48f0 .part RS_0x7fd6f9606848, 24, 1; +L_0x24a4df0 .part/pv L_0x24a4cb0, 24, 1, 32; +L_0x24a4e90 .part C4, 2, 1; +L_0x24a4f30 .part RS_0x7fd6f9610ec8, 24, 1; +L_0x24a5020 .part RS_0x7fd6f9610ef8, 24, 1; +L_0x24a5110 .part/pv L_0x24a51b0, 24, 1, 32; +L_0x24a52f0 .part RS_0x7fd6f9610f58, 23, 1; +L_0x24a5390 .part RS_0x7fd6f9610f28, 24, 1; +L_0x24a7600 .part/pv L_0x24a73f0, 25, 1, 32; +L_0x24a76a0 .part C4, 0, 1; +L_0x24a5e90 .part C4, 1, 1; +L_0x24a5fc0 .part RS_0x7fd6f9610aa8, 25, 1; +L_0x24a6060 .part RS_0x7fd6f9610aa8, 25, 1; +L_0x24a6100 .part RS_0x7fd6f9606848, 25, 1; +L_0x24a61f0 .part RS_0x7fd6f9610aa8, 25, 1; +L_0x24a6b00 .part/pv L_0x24a68f0, 25, 1, 32; +L_0x24a6ba0 .part C4, 0, 1; +L_0x24a6cd0 .part C4, 1, 1; +L_0x24a87f0 .part RS_0x7fd6f9609e78, 25, 1; +L_0x24a8890 .part RS_0x7fd6f9609e78, 25, 1; +L_0x24a77d0 .part RS_0x7fd6f9606848, 25, 1; +L_0x24a78c0 .part RS_0x7fd6f9606848, 25, 1; +L_0x24a7d00 .part/pv L_0x24a7bc0, 25, 1, 32; +L_0x24a7da0 .part C4, 2, 1; +L_0x24a7e40 .part RS_0x7fd6f9610ec8, 25, 1; +L_0x24a7f30 .part RS_0x7fd6f9610ef8, 25, 1; +L_0x24a8020 .part/pv L_0x24a80c0, 25, 1, 32; +L_0x24a8200 .part RS_0x7fd6f9610f58, 24, 1; +L_0x24a82a0 .part RS_0x7fd6f9610f28, 25, 1; +L_0x24a9d40 .part/pv L_0x24a9b30, 26, 1, 32; +L_0x24a8930 .part C4, 0, 1; +L_0x24a8a60 .part C4, 1, 1; +L_0x24a8b90 .part RS_0x7fd6f9610aa8, 26, 1; +L_0x24a8c30 .part RS_0x7fd6f9610aa8, 26, 1; +L_0x24a8cd0 .part RS_0x7fd6f9606848, 26, 1; +L_0x24a8dc0 .part RS_0x7fd6f9610aa8, 26, 1; +L_0x24a96e0 .part/pv L_0x24a94d0, 26, 1, 32; +L_0x24a9780 .part C4, 0, 1; +L_0x24a98b0 .part C4, 1, 1; +L_0x24aaf30 .part RS_0x7fd6f9609e78, 26, 1; +L_0x24a9de0 .part RS_0x7fd6f9609e78, 26, 1; +L_0x24a9e80 .part RS_0x7fd6f9606848, 26, 1; +L_0x24a9f20 .part RS_0x7fd6f9606848, 26, 1; +L_0x24aa3e0 .part/pv L_0x24aa2a0, 26, 1, 32; +L_0x24aa480 .part C4, 2, 1; +L_0x24aa520 .part RS_0x7fd6f9610ec8, 26, 1; +L_0x24aa610 .part RS_0x7fd6f9610ef8, 26, 1; +L_0x24aa700 .part/pv L_0x24aa7a0, 26, 1, 32; +L_0x24aa8e0 .part RS_0x7fd6f9610f58, 25, 1; +L_0x24aa980 .part RS_0x7fd6f9610f28, 26, 1; +L_0x24ac500 .part/pv L_0x24ac2f0, 27, 1, 32; +L_0x24ac5a0 .part C4, 0, 1; +L_0x24aafd0 .part C4, 1, 1; +L_0x24ab100 .part RS_0x7fd6f9610aa8, 27, 1; +L_0x24ab1a0 .part RS_0x7fd6f9610aa8, 27, 1; +L_0x24ab240 .part RS_0x7fd6f9606848, 27, 1; +L_0x24ab330 .part RS_0x7fd6f9610aa8, 27, 1; +L_0x24abc40 .part/pv L_0x24aba30, 27, 1, 32; +L_0x24abce0 .part C4, 0, 1; +L_0x24abe10 .part C4, 1, 1; +L_0x24abf40 .part RS_0x7fd6f9609e78, 27, 1; +L_0x24abfe0 .part RS_0x7fd6f9609e78, 27, 1; +L_0x24ad850 .part RS_0x7fd6f9606848, 27, 1; +L_0x24ad8f0 .part RS_0x7fd6f9606848, 27, 1; +L_0x24aca40 .part/pv L_0x24ac900, 27, 1, 32; +L_0x24acae0 .part C4, 2, 1; +L_0x24acb80 .part RS_0x7fd6f9610ec8, 27, 1; +L_0x24acc70 .part RS_0x7fd6f9610ef8, 27, 1; +L_0x24acd60 .part/pv L_0x24ace00, 27, 1, 32; +L_0x24acf40 .part RS_0x7fd6f9610f58, 26, 1; +L_0x24acfe0 .part RS_0x7fd6f9610f28, 27, 1; +L_0x24aec80 .part/pv L_0x24ad720, 28, 1, 32; +L_0x24ad9e0 .part C4, 0, 1; +L_0x24adb10 .part C4, 1, 1; +L_0x24adc40 .part RS_0x7fd6f9610aa8, 28, 1; +L_0x24adce0 .part RS_0x7fd6f9610aa8, 28, 1; +L_0x24add80 .part RS_0x7fd6f9606848, 28, 1; +L_0x24ade70 .part RS_0x7fd6f9610aa8, 28, 1; +L_0x24ae790 .part/pv L_0x24ae580, 28, 1, 32; +L_0x24ae830 .part C4, 0, 1; +L_0x24ae960 .part C4, 1, 1; +L_0x24aea90 .part RS_0x7fd6f9609e78, 28, 1; +L_0x24aff40 .part RS_0x7fd6f9609e78, 28, 1; +L_0x24affe0 .part RS_0x7fd6f9606848, 28, 1; +L_0x24aed20 .part RS_0x7fd6f9606848, 28, 1; +L_0x24af1e0 .part/pv L_0x24af0a0, 28, 1, 32; +L_0x24af280 .part C4, 2, 1; +L_0x24af320 .part RS_0x7fd6f9610ec8, 28, 1; +L_0x24af410 .part RS_0x7fd6f9610ef8, 28, 1; +L_0x24af500 .part/pv L_0x24af5a0, 28, 1, 32; +L_0x24af6e0 .part RS_0x7fd6f9610f58, 27, 1; +L_0x24af780 .part RS_0x7fd6f9610f28, 28, 1; +L_0x24b1470 .part/pv L_0x24afe90, 29, 1, 32; +L_0x24b1510 .part C4, 0, 1; +L_0x24b0080 .part C4, 1, 1; +L_0x24b01b0 .part RS_0x7fd6f9610aa8, 29, 1; +L_0x24b0250 .part RS_0x7fd6f9610aa8, 29, 1; +L_0x24b02f0 .part RS_0x7fd6f9606848, 29, 1; +L_0x24b0390 .part RS_0x7fd6f9610aa8, 29, 1; +L_0x24b0cd0 .part/pv L_0x24b0ac0, 29, 1, 32; +L_0x24b0d70 .part C4, 0, 1; +L_0x24b0ea0 .part C4, 1, 1; +L_0x24b0fd0 .part RS_0x7fd6f9609e78, 29, 1; +L_0x24b1070 .part RS_0x7fd6f9609e78, 29, 1; +L_0x24b1110 .part RS_0x7fd6f9606848, 29, 1; +L_0x24b1200 .part RS_0x7fd6f9606848, 29, 1; +L_0x24b2d30 .part/pv L_0x24b2bf0, 29, 1, 32; +L_0x24b2dd0 .part C4, 2, 1; +L_0x24b1640 .part RS_0x7fd6f9610ec8, 29, 1; +L_0x24b1730 .part RS_0x7fd6f9610ef8, 29, 1; +L_0x24b1820 .part/pv L_0x24b18c0, 29, 1, 32; +L_0x24b19c0 .part RS_0x7fd6f9610f58, 28, 1; +L_0x24b1a60 .part RS_0x7fd6f9610f28, 29, 1; +L_0x24b2380 .part/pv L_0x24b2170, 30, 1, 32; +L_0x24b2420 .part C4, 0, 1; +L_0x24b2550 .part C4, 1, 1; +L_0x24b2680 .part RS_0x7fd6f9610aa8, 30, 1; +L_0x24b2720 .part RS_0x7fd6f9610aa8, 30, 1; +L_0x24b27c0 .part RS_0x7fd6f9606848, 30, 1; +L_0x24b41b0 .part RS_0x7fd6f9610aa8, 30, 1; +L_0x24b36a0 .part/pv L_0x24b3490, 30, 1, 32; +L_0x24b3740 .part C4, 0, 1; +L_0x24b3870 .part C4, 1, 1; +L_0x24b39a0 .part RS_0x7fd6f9609e78, 30, 1; +L_0x24b3a40 .part RS_0x7fd6f9609e78, 30, 1; +L_0x24b3ae0 .part RS_0x7fd6f9606848, 30, 1; +L_0x24b3bd0 .part RS_0x7fd6f9606848, 30, 1; +L_0x24b40d0 .part/pv L_0x24b3f90, 30, 1, 32; +L_0x24b55e0 .part C4, 2, 1; +L_0x24b5680 .part RS_0x7fd6f9610ec8, 30, 1; +L_0x24b4250 .part RS_0x7fd6f9610ef8, 30, 1; +L_0x24b4340 .part/pv L_0x24b43e0, 30, 1, 32; +L_0x24b44e0 .part RS_0x7fd6f9610f58, 29, 1; +L_0x24b4580 .part RS_0x7fd6f9610f28, 30, 1; +L_0x24b4ea0 .part/pv L_0x24b4c90, 31, 1, 32; +L_0x24b4f40 .part C4, 0, 1; +L_0x24b5070 .part C4, 1, 1; +L_0x24b51a0 .part RS_0x7fd6f9610aa8, 31, 1; +L_0x24b5240 .part RS_0x7fd6f9610aa8, 31, 1; +L_0x24b52e0 .part RS_0x7fd6f9606848, 31, 1; +L_0x24b53d0 .part RS_0x7fd6f9610aa8, 31, 1; +L_0x24b72a0 .part/pv L_0x24b7090, 31, 1, 32; +L_0x24b5770 .part C4, 0, 1; +L_0x24b58a0 .part C4, 1, 1; +L_0x24b59d0 .part RS_0x7fd6f9609e78, 31, 1; +L_0x24b5a70 .part RS_0x7fd6f9609e78, 31, 1; +L_0x24b5b10 .part RS_0x7fd6f9606848, 31, 1; +L_0x24b5c00 .part RS_0x7fd6f9606848, 31, 1; +L_0x24b60c0 .part/pv L_0x24b5f80, 31, 1, 32; +L_0x24b6160 .part C4, 2, 1; +L_0x24b6200 .part RS_0x7fd6f9610ec8, 31, 1; +L_0x24b62f0 .part RS_0x7fd6f9610ef8, 31, 1; +L_0x24b63e0 .part/pv L_0x24b6480, 31, 1, 32; +L_0x24b65c0 .part RS_0x7fd6f9610f58, 30, 1; +L_0x24b6660 .part RS_0x7fd6f9610f28, 31, 1; +L_0x2520e60 .part/pv L_0x2520c80, 0, 1, 32; +L_0x24b7340 .part C4, 0, 1; +L_0x24b7470 .part C4, 1, 1; +L_0x24b75a0 .part RS_0x7fd6f9610aa8, 0, 1; +L_0x24b7640 .part RS_0x7fd6f9610aa8, 0, 1; +L_0x24b76e0 .part RS_0x7fd6f9606848, 0, 1; +L_0x24b77d0 .part RS_0x7fd6f9610aa8, 0, 1; +L_0x24b7ff0 .part/pv L_0x24b7e10, 0, 1, 32; +L_0x24b8090 .part C4, 0, 1; +L_0x24b81c0 .part C4, 1, 1; +L_0x24b82f0 .part RS_0x7fd6f9609e78, 0, 1; +L_0x24b8390 .part RS_0x7fd6f9609e78, 0, 1; +L_0x24b8430 .part RS_0x7fd6f9606848, 0, 1; +L_0x24b8520 .part RS_0x7fd6f9606848, 0, 1; +L_0x249f1f0 .part/pv L_0x249f0b0, 0, 1, 32; +L_0x249f290 .part C4, 2, 1; +L_0x249f330 .part RS_0x7fd6f9610ec8, 0, 1; +L_0x249f420 .part RS_0x7fd6f9610ef8, 0, 1; +L_0x249f510 .part/pv L_0x249f5b0, 0, 1, 32; +L_0x249f6f0 .part RS_0x7fd6f9610f28, 0, 1; +L_0x2492a20 .part RS_0x7fd6f9610f28, 0, 1; +L_0x2492c00 .part RS_0x7fd6f9610f58, 31, 1; +S_0x2426ca0 .scope module, "trial" "AddSubSLT32" 2 279, 2 205, S_0x22690e0; + .timescale -9 -12; +P_0x2426d98 .param/l "size" 2 228, +C4<0100000>; +L_0x24e21f0/d .functor OR 1, L_0x24e22c0, C4<0>, C4<0>, C4<0>; +L_0x24e21f0 .delay (20000,20000,20000) L_0x24e21f0/d; +L_0x24e2410/d .functor XOR 1, L_0x24e21f0, L_0x24ce830, C4<0>, C4<0>; +L_0x24e2410 .delay (40000,40000,40000) L_0x24e2410/d; +L_0x24ce8d0/d .functor AND 1, L_0x24ce9e0, L_0x24cea80, C4<1>, C4<1>; +L_0x24ce8d0 .delay (20000,20000,20000) L_0x24ce8d0/d; +L_0x24e35d0/d .functor NOT 1, L_0x24e2410, C4<0>, C4<0>, C4<0>; +L_0x24e35d0 .delay (10000,10000,10000) L_0x24e35d0/d; +L_0x24e3680/d .functor NOT 1, L_0x24e3720, C4<0>, C4<0>, C4<0>; +L_0x24e3680 .delay (10000,10000,10000) L_0x24e3680/d; +L_0x24e37c0/d .functor AND 1, L_0x24e35d0, L_0x24e3940, C4<1>, C4<1>; +L_0x24e37c0 .delay (20000,20000,20000) L_0x24e37c0/d; +L_0x24e39e0/d .functor AND 1, L_0x24e2410, L_0x24e3680, C4<1>, C4<1>; +L_0x24e39e0 .delay (20000,20000,20000) L_0x24e39e0/d; +L_0x249c470/d .functor AND 1, L_0x24e37c0, L_0x24ce8d0, C4<1>, C4<1>; +L_0x249c470 .delay (20000,20000,20000) L_0x249c470/d; +L_0x249c5d0/d .functor AND 1, L_0x24e39e0, L_0x24ce8d0, C4<1>, C4<1>; +L_0x249c5d0 .delay (20000,20000,20000) L_0x249c5d0/d; +L_0x24e4440/d .functor OR 1, L_0x249c470, L_0x249c5d0, C4<0>, C4<0>; +L_0x24e4440 .delay (20000,20000,20000) L_0x24e4440/d; +v0x2462030_0 .alias "A", 31 0, v0x2462f10_0; +v0x24620d0_0 .alias "AddSubSLTSum", 31 0, v0x2463100_0; +v0x2462170_0 .alias "B", 31 0, v0x24632b0_0; +RS_0x7fd6f9610ad8/0/0 .resolv tri, L_0x2478980, L_0x24bb860, L_0x24bcc60, L_0x24be0f0; +RS_0x7fd6f9610ad8/0/4 .resolv tri, L_0x24bf590, L_0x24c0b80, L_0x24c20c0, L_0x24c3640; +RS_0x7fd6f9610ad8/0/8 .resolv tri, L_0x24c4c50, L_0x24c6160, L_0x24c7670, L_0x24c8b80; +RS_0x7fd6f9610ad8/0/12 .resolv tri, L_0x24ca080, L_0x24cb7a0, L_0x24cccb0, L_0x24ce2c0; +RS_0x7fd6f9610ad8/0/16 .resolv tri, L_0x24cf8f0, L_0x24d0d60, L_0x24d2210, L_0x24d35e0; +RS_0x7fd6f9610ad8/0/20 .resolv tri, L_0x24d4a20, L_0x24d5f30, L_0x24d72f0, L_0x24d8740; +RS_0x7fd6f9610ad8/0/24 .resolv tri, L_0x24d9c30, L_0x24db110, L_0x24dc5f0, L_0x24ddaf0; +RS_0x7fd6f9610ad8/0/28 .resolv tri, L_0x24defe0, L_0x24e08b0, L_0x24e1da0, L_0x24e3490; +RS_0x7fd6f9610ad8/1/0 .resolv tri, RS_0x7fd6f9610ad8/0/0, RS_0x7fd6f9610ad8/0/4, RS_0x7fd6f9610ad8/0/8, RS_0x7fd6f9610ad8/0/12; +RS_0x7fd6f9610ad8/1/4 .resolv tri, RS_0x7fd6f9610ad8/0/16, RS_0x7fd6f9610ad8/0/20, RS_0x7fd6f9610ad8/0/24, RS_0x7fd6f9610ad8/0/28; +RS_0x7fd6f9610ad8 .resolv tri, RS_0x7fd6f9610ad8/1/0, RS_0x7fd6f9610ad8/1/4, C4, C4; +v0x2462240_0 .net8 "CarryoutWire", 31 0, RS_0x7fd6f9610ad8; 32 drivers +v0x24622c0_0 .alias "Command", 2 0, v0x2463430_0; +v0x2462340_0 .net "Res0OF1", 0 0, L_0x24e39e0; 1 drivers +v0x24623e0_0 .net "Res1OF0", 0 0, L_0x24e37c0; 1 drivers +v0x2462480_0 .alias "SLTflag", 0 0, v0x24635d0_0; +v0x2462570_0 .net "SLTflag0", 0 0, L_0x249c470; 1 drivers +v0x2462610_0 .net "SLTflag1", 0 0, L_0x249c5d0; 1 drivers +v0x24626b0_0 .net "SLTon", 0 0, L_0x24ce8d0; 1 drivers +v0x2462750_0 .net *"_s292", 0 0, L_0x24e22c0; 1 drivers +v0x24627f0_0 .net/s *"_s293", 0 0, C4<0>; 1 drivers +v0x2462890_0 .net *"_s296", 0 0, L_0x24ce830; 1 drivers +v0x24629b0_0 .net *"_s298", 0 0, L_0x24ce9e0; 1 drivers +v0x2462a50_0 .net *"_s300", 0 0, L_0x24cea80; 1 drivers +v0x2462910_0 .net *"_s302", 0 0, L_0x24e3720; 1 drivers +v0x2462ba0_0 .net *"_s304", 0 0, L_0x24e3940; 1 drivers +v0x2462cc0_0 .alias "carryin", 31 0, v0x2464e90_0; +v0x2462d40_0 .alias "carryout", 0 0, v0x2464cc0_0; +v0x2462c20_0 .net "nAddSubSLTSum", 0 0, L_0x24e3680; 1 drivers +v0x2462e70_0 .net "nOF", 0 0, L_0x24e35d0; 1 drivers +v0x2462dc0_0 .alias "overflow", 0 0, v0x2464d70_0; +v0x2462fb0_0 .alias "subtract", 31 0, v0x24650e0_0; +L_0x2478890 .part/pv L_0x2478400, 1, 1, 32; +L_0x2478980 .part/pv L_0x2478750, 1, 1, 32; +L_0x2478a70 .part/pv L_0x2478130, 1, 1, 32; +L_0x2478bb0 .part C4, 1, 1; +L_0x2478ce0 .part C4, 1, 1; +L_0x2478ea0 .part RS_0x7fd6f9610ad8, 0, 1; +L_0x24bb770 .part/pv L_0x24bb2e0, 2, 1, 32; +L_0x24bb860 .part/pv L_0x24bb630, 2, 1, 32; +L_0x24bb9a0 .part/pv L_0x24bb010, 2, 1, 32; +L_0x24bba90 .part C4, 2, 1; +L_0x24bbb90 .part C4, 2, 1; +L_0x24bbcc0 .part RS_0x7fd6f9610ad8, 1, 1; +L_0x24bcb70 .part/pv L_0x24bc6e0, 3, 1, 32; +L_0x24bcc60 .part/pv L_0x24bca30, 3, 1, 32; +L_0x24bcdd0 .part/pv L_0x24bc410, 3, 1, 32; +L_0x24bcf00 .part C4, 3, 1; +L_0x24bd030 .part C4, 3, 1; +L_0x24bd160 .part RS_0x7fd6f9610ad8, 2, 1; +L_0x24be000 .part/pv L_0x24bdb70, 4, 1, 32; +L_0x24be0f0 .part/pv L_0x24bdec0, 4, 1, 32; +L_0x24bd200 .part/pv L_0x24bd8a0, 4, 1, 32; +L_0x24be2e0 .part C4, 4, 1; +L_0x24be1e0 .part C4, 4, 1; +L_0x24be4d0 .part RS_0x7fd6f9610ad8, 3, 1; +L_0x24bf4a0 .part/pv L_0x24bf010, 5, 1, 32; +L_0x24bf590 .part/pv L_0x24bf360, 5, 1, 32; +L_0x24be680 .part/pv L_0x24bed40, 5, 1, 32; +L_0x24bf7b0 .part C4, 5, 1; +L_0x24bf680 .part C4, 5, 1; +L_0x24bfb60 .part RS_0x7fd6f9610ad8, 4, 1; +L_0x24c0a90 .part/pv L_0x24c05c0, 6, 1, 32; +L_0x24c0b80 .part/pv L_0x24c0930, 6, 1, 32; +L_0x24bfc00 .part/pv L_0x24c02f0, 6, 1, 32; +L_0x24c0d80 .part C4, 6, 1; +L_0x24c0c70 .part C4, 6, 1; +L_0x24c0fd0 .part RS_0x7fd6f9610ad8, 5, 1; +L_0x24c1fd0 .part/pv L_0x24c1b00, 7, 1, 32; +L_0x24c20c0 .part/pv L_0x24c1e50, 7, 1, 32; +L_0x24c1070 .part/pv L_0x24c1830, 7, 1, 32; +L_0x24c2400 .part C4, 7, 1; +L_0x24c21b0 .part C4, 7, 1; +L_0x24c2250 .part RS_0x7fd6f9610ad8, 6, 1; +L_0x24c3550 .part/pv L_0x24c30a0, 8, 1, 32; +L_0x24c3640 .part/pv L_0x24c33f0, 8, 1, 32; +L_0x24c24a0 .part/pv L_0x24c2dd0, 8, 1, 32; +L_0x24c38a0 .part C4, 8, 1; +L_0x24c3730 .part C4, 8, 1; +L_0x24c3ac0 .part RS_0x7fd6f9610ad8, 7, 1; +L_0x24c4b60 .part/pv L_0x24c46b0, 9, 1, 32; +L_0x24c4c50 .part/pv L_0x24c4a00, 9, 1, 32; +L_0x24c3d70 .part/pv L_0x24c43e0, 9, 1, 32; +L_0x24c3e60 .part C4, 9, 1; +L_0x24c4ef0 .part C4, 9, 1; +L_0x24c5020 .part RS_0x7fd6f9610ad8, 8, 1; +L_0x24c6070 .part/pv L_0x24c5bc0, 10, 1, 32; +L_0x24c6160 .part/pv L_0x24c5f10, 10, 1, 32; +L_0x24c50c0 .part/pv L_0x24c58f0, 10, 1, 32; +L_0x24c51b0 .part C4, 10, 1; +L_0x24c6430 .part C4, 10, 1; +L_0x24c6560 .part RS_0x7fd6f9610ad8, 9, 1; +L_0x24c7580 .part/pv L_0x24c70d0, 11, 1, 32; +L_0x24c7670 .part/pv L_0x24c7420, 11, 1, 32; +L_0x24c6600 .part/pv L_0x24c6e00, 11, 1, 32; +L_0x24c66f0 .part C4, 11, 1; +L_0x24c7970 .part C4, 11, 1; +L_0x24c7aa0 .part RS_0x7fd6f9610ad8, 10, 1; +L_0x24c8a90 .part/pv L_0x24c85e0, 12, 1, 32; +L_0x24c8b80 .part/pv L_0x24c8930, 12, 1, 32; +L_0x24c7b40 .part/pv L_0x24c8310, 12, 1, 32; +L_0x24c7c30 .part C4, 12, 1; +L_0x24c8eb0 .part C4, 12, 1; +L_0x24c8f50 .part RS_0x7fd6f9610ad8, 11, 1; +L_0x24c9f90 .part/pv L_0x24c9ae0, 13, 1, 32; +L_0x24ca080 .part/pv L_0x24c9e30, 13, 1, 32; +L_0x24c8ff0 .part/pv L_0x24c9810, 13, 1, 32; +L_0x24c90e0 .part C4, 13, 1; +L_0x24c9180 .part C4, 13, 1; +L_0x24bfa50 .part RS_0x7fd6f9610ad8, 12, 1; +L_0x24cb6b0 .part/pv L_0x24cb200, 14, 1, 32; +L_0x24cb7a0 .part/pv L_0x24cb550, 14, 1, 32; +L_0x24ca5e0 .part/pv L_0x24caf30, 14, 1, 32; +L_0x24ca6d0 .part C4, 14, 1; +L_0x24ca770 .part C4, 14, 1; +L_0x24cbbc0 .part RS_0x7fd6f9610ad8, 13, 1; +L_0x24ccbc0 .part/pv L_0x24cc710, 15, 1, 32; +L_0x24cccb0 .part/pv L_0x24cca60, 15, 1, 32; +L_0x24cbc60 .part/pv L_0x24cc440, 15, 1, 32; +L_0x24c2340 .part C4, 15, 1; +L_0x24cd070 .part C4, 15, 1; +L_0x24cd1a0 .part RS_0x7fd6f9610ad8, 14, 1; +L_0x24ce1d0 .part/pv L_0x24cdd20, 16, 1, 32; +L_0x24ce2c0 .part/pv L_0x24ce070, 16, 1, 32; +L_0x24cd240 .part/pv L_0x24cda50, 16, 1, 32; +L_0x24cd330 .part C4, 16, 1; +L_0x24cd3d0 .part C4, 16, 1; +L_0x24ce6b0 .part RS_0x7fd6f9610ad8, 15, 1; +L_0x24cf800 .part/pv L_0x24cf370, 17, 1, 32; +L_0x24cf8f0 .part/pv L_0x24cf6c0, 17, 1, 32; +L_0x24ceb60 .part/pv L_0x24cf0a0, 17, 1, 32; +L_0x24cec50 .part C4, 17, 1; +L_0x24cecf0 .part C4, 17, 1; +L_0x24cfd10 .part RS_0x7fd6f9610ad8, 16, 1; +L_0x24d0c70 .part/pv L_0x24d07e0, 18, 1, 32; +L_0x24d0d60 .part/pv L_0x24d0b30, 18, 1, 32; +L_0x24cfdb0 .part/pv L_0x24d0510, 18, 1, 32; +L_0x24cfea0 .part C4, 18, 1; +L_0x24cff40 .part C4, 18, 1; +L_0x24d11b0 .part RS_0x7fd6f9610ad8, 17, 1; +L_0x24d2120 .part/pv L_0x24d1c90, 19, 1, 32; +L_0x24d2210 .part/pv L_0x24d1fe0, 19, 1, 32; +L_0x24d1250 .part/pv L_0x24d19c0, 19, 1, 32; +L_0x24d1340 .part C4, 19, 1; +L_0x24d13e0 .part C4, 19, 1; +L_0x24d1510 .part RS_0x7fd6f9610ad8, 18, 1; +L_0x24d34f0 .part/pv L_0x24d3060, 20, 1, 32; +L_0x24d35e0 .part/pv L_0x24d33b0, 20, 1, 32; +L_0x24d2300 .part/pv L_0x24d2d90, 20, 1, 32; +L_0x24d23f0 .part C4, 20, 1; +L_0x24d2490 .part C4, 20, 1; +L_0x24d25c0 .part RS_0x7fd6f9610ad8, 19, 1; +L_0x24d4930 .part/pv L_0x24d4460, 21, 1, 32; +L_0x24d4a20 .part/pv L_0x24d47d0, 21, 1, 32; +L_0x24d36d0 .part/pv L_0x24d4190, 21, 1, 32; +L_0x24d37c0 .part C4, 21, 1; +L_0x24d3860 .part C4, 21, 1; +L_0x24d3990 .part RS_0x7fd6f9610ad8, 20, 1; +L_0x24d5e40 .part/pv L_0x24d5990, 22, 1, 32; +L_0x24d5f30 .part/pv L_0x24d5ce0, 22, 1, 32; +L_0x24d4b10 .part/pv L_0x24d56c0, 22, 1, 32; +L_0x24d4c00 .part C4, 22, 1; +L_0x24d4ca0 .part C4, 22, 1; +L_0x24d4dd0 .part RS_0x7fd6f9610ad8, 21, 1; +L_0x24d7200 .part/pv L_0x24d6d70, 23, 1, 32; +L_0x24d72f0 .part/pv L_0x24d70c0, 23, 1, 32; +L_0x24d6020 .part/pv L_0x24d6aa0, 23, 1, 32; +L_0x24d6110 .part C4, 23, 1; +L_0x24d61b0 .part C4, 23, 1; +L_0x24d62e0 .part RS_0x7fd6f9610ad8, 22, 1; +L_0x24d8650 .part/pv L_0x24d8150, 24, 1, 32; +L_0x24d8740 .part/pv L_0x24d84f0, 24, 1, 32; +L_0x24d73e0 .part/pv L_0x24d7e80, 24, 1, 32; +L_0x24d74d0 .part C4, 24, 1; +L_0x24d7570 .part C4, 24, 1; +L_0x24d76a0 .part RS_0x7fd6f9610ad8, 23, 1; +L_0x24d9b40 .part/pv L_0x24d9610, 25, 1, 32; +L_0x24d9c30 .part/pv L_0x24d99e0, 25, 1, 32; +L_0x24d8830 .part/pv L_0x24d9340, 25, 1, 32; +L_0x24d8920 .part C4, 25, 1; +L_0x24d89c0 .part C4, 25, 1; +L_0x24d8af0 .part RS_0x7fd6f9610ad8, 24, 1; +L_0x24db020 .part/pv L_0x24daaf0, 26, 1, 32; +L_0x24db110 .part/pv L_0x24daec0, 26, 1, 32; +L_0x24d9d20 .part/pv L_0x24da820, 26, 1, 32; +L_0x24d9e10 .part C4, 26, 1; +L_0x24d9eb0 .part C4, 26, 1; +L_0x24d9fe0 .part RS_0x7fd6f9610ad8, 25, 1; +L_0x24dc500 .part/pv L_0x24dbfd0, 27, 1, 32; +L_0x24dc5f0 .part/pv L_0x24dc3a0, 27, 1, 32; +L_0x24db200 .part/pv L_0x24dbd00, 27, 1, 32; +L_0x24db2f0 .part C4, 27, 1; +L_0x24db390 .part C4, 27, 1; +L_0x24db4c0 .part RS_0x7fd6f9610ad8, 26, 1; +L_0x24dda00 .part/pv L_0x24dd4f0, 28, 1, 32; +L_0x24ddaf0 .part/pv L_0x24dd8a0, 28, 1, 32; +L_0x24dc6e0 .part/pv L_0x24dd1f0, 28, 1, 32; +L_0x24dc7d0 .part C4, 28, 1; +L_0x24dc870 .part C4, 28, 1; +L_0x24dc9a0 .part RS_0x7fd6f9610ad8, 27, 1; +L_0x24deef0 .part/pv L_0x24de9e0, 29, 1, 32; +L_0x24defe0 .part/pv L_0x24ded90, 29, 1, 32; +L_0x24ddbe0 .part/pv L_0x24de6e0, 29, 1, 32; +L_0x24ddcd0 .part C4, 29, 1; +L_0x24ca3d0 .part C4, 29, 1; +L_0x24ca500 .part RS_0x7fd6f9610ad8, 28, 1; +L_0x24e07c0 .part/pv L_0x24e0330, 30, 1, 32; +L_0x24e08b0 .part/pv L_0x24e0680, 30, 1, 32; +L_0x24dfa40 .part/pv L_0x24e0060, 30, 1, 32; +L_0x24dfb30 .part C4, 30, 1; +L_0x24dfbd0 .part C4, 30, 1; +L_0x24dfd00 .part RS_0x7fd6f9610ad8, 29, 1; +L_0x24e1cb0 .part/pv L_0x24e17a0, 31, 1, 32; +L_0x24e1da0 .part/pv L_0x24e1b50, 31, 1, 32; +L_0x24e09a0 .part/pv L_0x24e14a0, 31, 1, 32; +L_0x24e0ea0 .part C4, 31, 1; +L_0x24cbd00 .part C4, 31, 1; +L_0x24cbe30 .part RS_0x7fd6f9610ad8, 30, 1; +L_0x24e33a0 .part/pv L_0x24e2e70, 0, 1, 32; +L_0x24e3490 .part/pv L_0x24e3240, 0, 1, 32; +L_0x24e1e90 .part/pv L_0x24e2ba0, 0, 1, 32; +L_0x24e1f80 .part C4, 0, 1; +L_0x24e2020 .part C4, 0, 1; +L_0x24e2150 .part RS_0x7fd6f9610e68, 0, 1; +L_0x24e22c0 .part RS_0x7fd6f9610ad8, 31, 1; +L_0x24ce830 .part RS_0x7fd6f9610ad8, 30, 1; +L_0x24ce9e0 .part C4, 1, 1; +L_0x24cea80 .part RS_0x7fd6f9610e68, 0, 1; +L_0x24e3720 .part RS_0x7fd6f9610aa8, 31, 1; +L_0x24e3940 .part RS_0x7fd6f9610aa8, 31, 1; +S_0x2461020 .scope module, "attempt2" "MiddleAddSubSLT" 2 225, 2 89, S_0x2426ca0; + .timescale -9 -12; +L_0x24e2470/d .functor NOT 1, L_0x24e2020, C4<0>, C4<0>, C4<0>; +L_0x24e2470 .delay (10000,10000,10000) L_0x24e2470/d; +L_0x24e2a40/d .functor NOT 1, L_0x24e2b00, C4<0>, C4<0>, C4<0>; +L_0x24e2a40 .delay (10000,10000,10000) L_0x24e2a40/d; +L_0x24e2ba0/d .functor AND 1, L_0x24e2ce0, L_0x24e2a40, C4<1>, C4<1>; +L_0x24e2ba0 .delay (20000,20000,20000) L_0x24e2ba0/d; +L_0x24e2d80/d .functor XOR 1, L_0x24e1f80, L_0x24e27d0, C4<0>, C4<0>; +L_0x24e2d80 .delay (40000,40000,40000) L_0x24e2d80/d; +L_0x24e2e70/d .functor XOR 1, L_0x24e2d80, L_0x24e2150, C4<0>, C4<0>; +L_0x24e2e70 .delay (40000,40000,40000) L_0x24e2e70/d; +L_0x24e2f90/d .functor AND 1, L_0x24e1f80, L_0x24e27d0, C4<1>, C4<1>; +L_0x24e2f90 .delay (20000,20000,20000) L_0x24e2f90/d; +L_0x24e3130/d .functor AND 1, L_0x24e2d80, L_0x24e2150, C4<1>, C4<1>; +L_0x24e3130 .delay (20000,20000,20000) L_0x24e3130/d; +L_0x24e3240/d .functor OR 1, L_0x24e2f90, L_0x24e3130, C4<0>, C4<0>; +L_0x24e3240 .delay (20000,20000,20000) L_0x24e3240/d; +v0x2461690_0 .net "A", 0 0, L_0x24e1f80; 1 drivers +v0x2461750_0 .net "AandB", 0 0, L_0x24e2f90; 1 drivers +v0x24617f0_0 .net "AddSubSLTSum", 0 0, L_0x24e2e70; 1 drivers +v0x2461890_0 .net "AxorB", 0 0, L_0x24e2d80; 1 drivers +v0x2461910_0 .net "B", 0 0, L_0x24e2020; 1 drivers +v0x24619c0_0 .net "BornB", 0 0, L_0x24e27d0; 1 drivers +v0x2461a80_0 .net "CINandAxorB", 0 0, L_0x24e3130; 1 drivers +v0x2461b00_0 .alias "Command", 2 0, v0x2463430_0; +v0x2461b80_0 .net *"_s3", 0 0, L_0x24e2b00; 1 drivers +v0x2461c00_0 .net *"_s5", 0 0, L_0x24e2ce0; 1 drivers +v0x2461ca0_0 .net "carryin", 0 0, L_0x24e2150; 1 drivers +v0x2461d40_0 .net "carryout", 0 0, L_0x24e3240; 1 drivers +v0x2461de0_0 .net "nB", 0 0, L_0x24e2470; 1 drivers +v0x2461e90_0 .net "nCmd2", 0 0, L_0x24e2a40; 1 drivers +v0x2461f90_0 .net "subtract", 0 0, L_0x24e2ba0; 1 drivers +L_0x24e29a0 .part C4, 0, 1; +L_0x24e2b00 .part C4, 2, 1; +L_0x24e2ce0 .part C4, 0, 1; +S_0x2461110 .scope module, "mux0" "TwoInMux" 2 105, 2 8, S_0x2461020; + .timescale -9 -12; +L_0x24e2570/d .functor NOT 1, L_0x24e29a0, C4<0>, C4<0>, C4<0>; +L_0x24e2570 .delay (10000,10000,10000) L_0x24e2570/d; +L_0x24e25d0/d .functor AND 1, L_0x24e2020, L_0x24e2570, C4<1>, C4<1>; +L_0x24e25d0 .delay (20000,20000,20000) L_0x24e25d0/d; +L_0x24e26c0/d .functor AND 1, L_0x24e2470, L_0x24e29a0, C4<1>, C4<1>; +L_0x24e26c0 .delay (20000,20000,20000) L_0x24e26c0/d; +L_0x24e27d0/d .functor OR 1, L_0x24e25d0, L_0x24e26c0, C4<0>, C4<0>; +L_0x24e27d0 .delay (20000,20000,20000) L_0x24e27d0/d; +v0x2461200_0 .net "S", 0 0, L_0x24e29a0; 1 drivers +v0x24612c0_0 .alias "in0", 0 0, v0x2461910_0; +v0x2461360_0 .alias "in1", 0 0, v0x2461de0_0; +v0x2461400_0 .net "nS", 0 0, L_0x24e2570; 1 drivers +v0x24614b0_0 .net "out0", 0 0, L_0x24e25d0; 1 drivers +v0x2461550_0 .net "out1", 0 0, L_0x24e26c0; 1 drivers +v0x24615f0_0 .alias "outfinal", 0 0, v0x24619c0_0; +S_0x245fe80 .scope generate, "addbits[1]" "addbits[1]" 2 230, 2 230, S_0x2426ca0; + .timescale -9 -12; +P_0x245f898 .param/l "i" 2 230, +C4<01>; +S_0x245fff0 .scope module, "attempt" "MiddleAddSubSLT" 2 232, 2 89, S_0x245fe80; + .timescale -9 -12; +L_0x24b6750/d .functor NOT 1, L_0x2478ce0, C4<0>, C4<0>, C4<0>; +L_0x24b6750 .delay (10000,10000,10000) L_0x24b6750/d; +L_0x24b89d0/d .functor NOT 1, L_0x24b8a70, C4<0>, C4<0>, C4<0>; +L_0x24b89d0 .delay (10000,10000,10000) L_0x24b89d0/d; +L_0x2478130/d .functor AND 1, L_0x2478270, L_0x24b89d0, C4<1>, C4<1>; +L_0x2478130 .delay (20000,20000,20000) L_0x2478130/d; +L_0x2478310/d .functor XOR 1, L_0x2478bb0, L_0x24b87a0, C4<0>, C4<0>; +L_0x2478310 .delay (40000,40000,40000) L_0x2478310/d; +L_0x2478400/d .functor XOR 1, L_0x2478310, L_0x2478ea0, C4<0>, C4<0>; +L_0x2478400 .delay (40000,40000,40000) L_0x2478400/d; +L_0x24784f0/d .functor AND 1, L_0x2478bb0, L_0x24b87a0, C4<1>, C4<1>; +L_0x24784f0 .delay (20000,20000,20000) L_0x24784f0/d; +L_0x2478660/d .functor AND 1, L_0x2478310, L_0x2478ea0, C4<1>, C4<1>; +L_0x2478660 .delay (20000,20000,20000) L_0x2478660/d; +L_0x2478750/d .functor OR 1, L_0x24784f0, L_0x2478660, C4<0>, C4<0>; +L_0x2478750 .delay (20000,20000,20000) L_0x2478750/d; +v0x2460680_0 .net "A", 0 0, L_0x2478bb0; 1 drivers +v0x2460740_0 .net "AandB", 0 0, L_0x24784f0; 1 drivers +v0x24607e0_0 .net "AddSubSLTSum", 0 0, L_0x2478400; 1 drivers +v0x2460880_0 .net "AxorB", 0 0, L_0x2478310; 1 drivers +v0x2460900_0 .net "B", 0 0, L_0x2478ce0; 1 drivers +v0x24609b0_0 .net "BornB", 0 0, L_0x24b87a0; 1 drivers +v0x2460a70_0 .net "CINandAxorB", 0 0, L_0x2478660; 1 drivers +v0x2460af0_0 .alias "Command", 2 0, v0x2463430_0; +v0x2460b70_0 .net *"_s3", 0 0, L_0x24b8a70; 1 drivers +v0x2460bf0_0 .net *"_s5", 0 0, L_0x2478270; 1 drivers +v0x2460c90_0 .net "carryin", 0 0, L_0x2478ea0; 1 drivers +v0x2460d30_0 .net "carryout", 0 0, L_0x2478750; 1 drivers +v0x2460dd0_0 .net "nB", 0 0, L_0x24b6750; 1 drivers +v0x2460e80_0 .net "nCmd2", 0 0, L_0x24b89d0; 1 drivers +v0x2460f80_0 .net "subtract", 0 0, L_0x2478130; 1 drivers +L_0x24b8930 .part C4, 0, 1; +L_0x24b8a70 .part C4, 2, 1; +L_0x2478270 .part C4, 0, 1; +S_0x24600e0 .scope module, "mux0" "TwoInMux" 2 105, 2 8, S_0x245fff0; + .timescale -9 -12; +L_0x24b68e0/d .functor NOT 1, L_0x24b8930, C4<0>, C4<0>, C4<0>; +L_0x24b68e0 .delay (10000,10000,10000) L_0x24b68e0/d; +L_0x24b6980/d .functor AND 1, L_0x2478ce0, L_0x24b68e0, C4<1>, C4<1>; +L_0x24b6980 .delay (20000,20000,20000) L_0x24b6980/d; +L_0x24b6a70/d .functor AND 1, L_0x24b6750, L_0x24b8930, C4<1>, C4<1>; +L_0x24b6a70 .delay (20000,20000,20000) L_0x24b6a70/d; +L_0x24b87a0/d .functor OR 1, L_0x24b6980, L_0x24b6a70, C4<0>, C4<0>; +L_0x24b87a0 .delay (20000,20000,20000) L_0x24b87a0/d; +v0x24601d0_0 .net "S", 0 0, L_0x24b8930; 1 drivers +v0x2460270_0 .alias "in0", 0 0, v0x2460900_0; +v0x2460310_0 .alias "in1", 0 0, v0x2460dd0_0; +v0x24603b0_0 .net "nS", 0 0, L_0x24b68e0; 1 drivers +v0x2460460_0 .net "out0", 0 0, L_0x24b6980; 1 drivers +v0x2460500_0 .net "out1", 0 0, L_0x24b6a70; 1 drivers +v0x24605e0_0 .alias "outfinal", 0 0, v0x24609b0_0; +S_0x245ece0 .scope generate, "addbits[2]" "addbits[2]" 2 230, 2 230, S_0x2426ca0; + .timescale -9 -12; +P_0x245e6f8 .param/l "i" 2 230, +C4<010>; +S_0x245ee50 .scope module, "attempt" "MiddleAddSubSLT" 2 232, 2 89, S_0x245ece0; + .timescale -9 -12; +L_0x2478f40/d .functor NOT 1, L_0x24bbb90, C4<0>, C4<0>, C4<0>; +L_0x2478f40 .delay (10000,10000,10000) L_0x2478f40/d; +L_0x24baed0/d .functor NOT 1, L_0x24baf70, C4<0>, C4<0>, C4<0>; +L_0x24baed0 .delay (10000,10000,10000) L_0x24baed0/d; +L_0x24bb010/d .functor AND 1, L_0x24bb150, L_0x24baed0, C4<1>, C4<1>; +L_0x24bb010 .delay (20000,20000,20000) L_0x24bb010/d; +L_0x24bb1f0/d .functor XOR 1, L_0x24bba90, L_0x24baca0, C4<0>, C4<0>; +L_0x24bb1f0 .delay (40000,40000,40000) L_0x24bb1f0/d; +L_0x24bb2e0/d .functor XOR 1, L_0x24bb1f0, L_0x24bbcc0, C4<0>, C4<0>; +L_0x24bb2e0 .delay (40000,40000,40000) L_0x24bb2e0/d; +L_0x24bb3d0/d .functor AND 1, L_0x24bba90, L_0x24baca0, C4<1>, C4<1>; +L_0x24bb3d0 .delay (20000,20000,20000) L_0x24bb3d0/d; +L_0x24bb540/d .functor AND 1, L_0x24bb1f0, L_0x24bbcc0, C4<1>, C4<1>; +L_0x24bb540 .delay (20000,20000,20000) L_0x24bb540/d; +L_0x24bb630/d .functor OR 1, L_0x24bb3d0, L_0x24bb540, C4<0>, C4<0>; +L_0x24bb630 .delay (20000,20000,20000) L_0x24bb630/d; +v0x245f4e0_0 .net "A", 0 0, L_0x24bba90; 1 drivers +v0x245f5a0_0 .net "AandB", 0 0, L_0x24bb3d0; 1 drivers +v0x245f640_0 .net "AddSubSLTSum", 0 0, L_0x24bb2e0; 1 drivers +v0x245f6e0_0 .net "AxorB", 0 0, L_0x24bb1f0; 1 drivers +v0x245f760_0 .net "B", 0 0, L_0x24bbb90; 1 drivers +v0x245f810_0 .net "BornB", 0 0, L_0x24baca0; 1 drivers +v0x245f8d0_0 .net "CINandAxorB", 0 0, L_0x24bb540; 1 drivers +v0x245f950_0 .alias "Command", 2 0, v0x2463430_0; +v0x245f9d0_0 .net *"_s3", 0 0, L_0x24baf70; 1 drivers +v0x245fa50_0 .net *"_s5", 0 0, L_0x24bb150; 1 drivers +v0x245faf0_0 .net "carryin", 0 0, L_0x24bbcc0; 1 drivers +v0x245fb90_0 .net "carryout", 0 0, L_0x24bb630; 1 drivers +v0x245fc30_0 .net "nB", 0 0, L_0x2478f40; 1 drivers +v0x245fce0_0 .net "nCmd2", 0 0, L_0x24baed0; 1 drivers +v0x245fde0_0 .net "subtract", 0 0, L_0x24bb010; 1 drivers +L_0x24bae30 .part C4, 0, 1; +L_0x24baf70 .part C4, 2, 1; +L_0x24bb150 .part C4, 0, 1; +S_0x245ef40 .scope module, "mux0" "TwoInMux" 2 105, 2 8, S_0x245ee50; + .timescale -9 -12; +L_0x2479030/d .functor NOT 1, L_0x24bae30, C4<0>, C4<0>, C4<0>; +L_0x2479030 .delay (10000,10000,10000) L_0x2479030/d; +L_0x24790d0/d .functor AND 1, L_0x24bbb90, L_0x2479030, C4<1>, C4<1>; +L_0x24790d0 .delay (20000,20000,20000) L_0x24790d0/d; +L_0x24babb0/d .functor AND 1, L_0x2478f40, L_0x24bae30, C4<1>, C4<1>; +L_0x24babb0 .delay (20000,20000,20000) L_0x24babb0/d; +L_0x24baca0/d .functor OR 1, L_0x24790d0, L_0x24babb0, C4<0>, C4<0>; +L_0x24baca0 .delay (20000,20000,20000) L_0x24baca0/d; +v0x245f030_0 .net "S", 0 0, L_0x24bae30; 1 drivers +v0x245f0d0_0 .alias "in0", 0 0, v0x245f760_0; +v0x245f170_0 .alias "in1", 0 0, v0x245fc30_0; +v0x245f210_0 .net "nS", 0 0, L_0x2479030; 1 drivers +v0x245f2c0_0 .net "out0", 0 0, L_0x24790d0; 1 drivers +v0x245f360_0 .net "out1", 0 0, L_0x24babb0; 1 drivers +v0x245f440_0 .alias "outfinal", 0 0, v0x245f810_0; +S_0x245db40 .scope generate, "addbits[3]" "addbits[3]" 2 230, 2 230, S_0x2426ca0; + .timescale -9 -12; +P_0x245d558 .param/l "i" 2 230, +C4<011>; +S_0x245dcb0 .scope module, "attempt" "MiddleAddSubSLT" 2 232, 2 89, S_0x245db40; + .timescale -9 -12; +L_0x24bbb30/d .functor NOT 1, L_0x24bd030, C4<0>, C4<0>, C4<0>; +L_0x24bbb30 .delay (10000,10000,10000) L_0x24bbb30/d; +L_0x24bc2d0/d .functor NOT 1, L_0x24bc370, C4<0>, C4<0>, C4<0>; +L_0x24bc2d0 .delay (10000,10000,10000) L_0x24bc2d0/d; +L_0x24bc410/d .functor AND 1, L_0x24bc550, L_0x24bc2d0, C4<1>, C4<1>; +L_0x24bc410 .delay (20000,20000,20000) L_0x24bc410/d; +L_0x24bc5f0/d .functor XOR 1, L_0x24bcf00, L_0x24bc0a0, C4<0>, C4<0>; +L_0x24bc5f0 .delay (40000,40000,40000) L_0x24bc5f0/d; +L_0x24bc6e0/d .functor XOR 1, L_0x24bc5f0, L_0x24bd160, C4<0>, C4<0>; +L_0x24bc6e0 .delay (40000,40000,40000) L_0x24bc6e0/d; +L_0x24bc7d0/d .functor AND 1, L_0x24bcf00, L_0x24bc0a0, C4<1>, C4<1>; +L_0x24bc7d0 .delay (20000,20000,20000) L_0x24bc7d0/d; +L_0x24bc940/d .functor AND 1, L_0x24bc5f0, L_0x24bd160, C4<1>, C4<1>; +L_0x24bc940 .delay (20000,20000,20000) L_0x24bc940/d; +L_0x24bca30/d .functor OR 1, L_0x24bc7d0, L_0x24bc940, C4<0>, C4<0>; +L_0x24bca30 .delay (20000,20000,20000) L_0x24bca30/d; +v0x245e340_0 .net "A", 0 0, L_0x24bcf00; 1 drivers +v0x245e400_0 .net "AandB", 0 0, L_0x24bc7d0; 1 drivers +v0x245e4a0_0 .net "AddSubSLTSum", 0 0, L_0x24bc6e0; 1 drivers +v0x245e540_0 .net "AxorB", 0 0, L_0x24bc5f0; 1 drivers +v0x245e5c0_0 .net "B", 0 0, L_0x24bd030; 1 drivers +v0x245e670_0 .net "BornB", 0 0, L_0x24bc0a0; 1 drivers +v0x245e730_0 .net "CINandAxorB", 0 0, L_0x24bc940; 1 drivers +v0x245e7b0_0 .alias "Command", 2 0, v0x2463430_0; +v0x245e830_0 .net *"_s3", 0 0, L_0x24bc370; 1 drivers +v0x245e8b0_0 .net *"_s5", 0 0, L_0x24bc550; 1 drivers +v0x245e950_0 .net "carryin", 0 0, L_0x24bd160; 1 drivers +v0x245e9f0_0 .net "carryout", 0 0, L_0x24bca30; 1 drivers +v0x245ea90_0 .net "nB", 0 0, L_0x24bbb30; 1 drivers +v0x245eb40_0 .net "nCmd2", 0 0, L_0x24bc2d0; 1 drivers +v0x245ec40_0 .net "subtract", 0 0, L_0x24bc410; 1 drivers +L_0x24bc230 .part C4, 0, 1; +L_0x24bc370 .part C4, 2, 1; +L_0x24bc550 .part C4, 0, 1; +S_0x245dda0 .scope module, "mux0" "TwoInMux" 2 105, 2 8, S_0x245dcb0; + .timescale -9 -12; +L_0x24bbe60/d .functor NOT 1, L_0x24bc230, C4<0>, C4<0>, C4<0>; +L_0x24bbe60 .delay (10000,10000,10000) L_0x24bbe60/d; +L_0x24bbec0/d .functor AND 1, L_0x24bd030, L_0x24bbe60, C4<1>, C4<1>; +L_0x24bbec0 .delay (20000,20000,20000) L_0x24bbec0/d; +L_0x24bbfb0/d .functor AND 1, L_0x24bbb30, L_0x24bc230, C4<1>, C4<1>; +L_0x24bbfb0 .delay (20000,20000,20000) L_0x24bbfb0/d; +L_0x24bc0a0/d .functor OR 1, L_0x24bbec0, L_0x24bbfb0, C4<0>, C4<0>; +L_0x24bc0a0 .delay (20000,20000,20000) L_0x24bc0a0/d; +v0x245de90_0 .net "S", 0 0, L_0x24bc230; 1 drivers +v0x245df30_0 .alias "in0", 0 0, v0x245e5c0_0; +v0x245dfd0_0 .alias "in1", 0 0, v0x245ea90_0; +v0x245e070_0 .net "nS", 0 0, L_0x24bbe60; 1 drivers +v0x245e120_0 .net "out0", 0 0, L_0x24bbec0; 1 drivers +v0x245e1c0_0 .net "out1", 0 0, L_0x24bbfb0; 1 drivers +v0x245e2a0_0 .alias "outfinal", 0 0, v0x245e670_0; +S_0x245c9a0 .scope generate, "addbits[4]" "addbits[4]" 2 230, 2 230, S_0x2426ca0; + .timescale -9 -12; +P_0x245c3b8 .param/l "i" 2 230, +C4<0100>; +S_0x245cb10 .scope module, "attempt" "MiddleAddSubSLT" 2 232, 2 89, S_0x245c9a0; + .timescale -9 -12; +L_0x24bbdf0/d .functor NOT 1, L_0x24be1e0, C4<0>, C4<0>, C4<0>; +L_0x24bbdf0 .delay (10000,10000,10000) L_0x24bbdf0/d; +L_0x24bd760/d .functor NOT 1, L_0x24bd800, C4<0>, C4<0>, C4<0>; +L_0x24bd760 .delay (10000,10000,10000) L_0x24bd760/d; +L_0x24bd8a0/d .functor AND 1, L_0x24bd9e0, L_0x24bd760, C4<1>, C4<1>; +L_0x24bd8a0 .delay (20000,20000,20000) L_0x24bd8a0/d; +L_0x24bda80/d .functor XOR 1, L_0x24be2e0, L_0x24bd530, C4<0>, C4<0>; +L_0x24bda80 .delay (40000,40000,40000) L_0x24bda80/d; +L_0x24bdb70/d .functor XOR 1, L_0x24bda80, L_0x24be4d0, C4<0>, C4<0>; +L_0x24bdb70 .delay (40000,40000,40000) L_0x24bdb70/d; +L_0x24bdc60/d .functor AND 1, L_0x24be2e0, L_0x24bd530, C4<1>, C4<1>; +L_0x24bdc60 .delay (20000,20000,20000) L_0x24bdc60/d; +L_0x24bddd0/d .functor AND 1, L_0x24bda80, L_0x24be4d0, C4<1>, C4<1>; +L_0x24bddd0 .delay (20000,20000,20000) L_0x24bddd0/d; +L_0x24bdec0/d .functor OR 1, L_0x24bdc60, L_0x24bddd0, C4<0>, C4<0>; +L_0x24bdec0 .delay (20000,20000,20000) L_0x24bdec0/d; +v0x245d1a0_0 .net "A", 0 0, L_0x24be2e0; 1 drivers +v0x245d260_0 .net "AandB", 0 0, L_0x24bdc60; 1 drivers +v0x245d300_0 .net "AddSubSLTSum", 0 0, L_0x24bdb70; 1 drivers +v0x245d3a0_0 .net "AxorB", 0 0, L_0x24bda80; 1 drivers +v0x245d420_0 .net "B", 0 0, L_0x24be1e0; 1 drivers +v0x245d4d0_0 .net "BornB", 0 0, L_0x24bd530; 1 drivers +v0x245d590_0 .net "CINandAxorB", 0 0, L_0x24bddd0; 1 drivers +v0x245d610_0 .alias "Command", 2 0, v0x2463430_0; +v0x245d690_0 .net *"_s3", 0 0, L_0x24bd800; 1 drivers +v0x245d710_0 .net *"_s5", 0 0, L_0x24bd9e0; 1 drivers +v0x245d7b0_0 .net "carryin", 0 0, L_0x24be4d0; 1 drivers +v0x245d850_0 .net "carryout", 0 0, L_0x24bdec0; 1 drivers +v0x245d8f0_0 .net "nB", 0 0, L_0x24bbdf0; 1 drivers +v0x245d9a0_0 .net "nCmd2", 0 0, L_0x24bd760; 1 drivers +v0x245daa0_0 .net "subtract", 0 0, L_0x24bd8a0; 1 drivers +L_0x24bd6c0 .part C4, 0, 1; +L_0x24bd800 .part C4, 2, 1; +L_0x24bd9e0 .part C4, 0, 1; +S_0x245cc00 .scope module, "mux0" "TwoInMux" 2 105, 2 8, S_0x245cb10; + .timescale -9 -12; +L_0x24bd2f0/d .functor NOT 1, L_0x24bd6c0, C4<0>, C4<0>, C4<0>; +L_0x24bd2f0 .delay (10000,10000,10000) L_0x24bd2f0/d; +L_0x24bd350/d .functor AND 1, L_0x24be1e0, L_0x24bd2f0, C4<1>, C4<1>; +L_0x24bd350 .delay (20000,20000,20000) L_0x24bd350/d; +L_0x24bd440/d .functor AND 1, L_0x24bbdf0, L_0x24bd6c0, C4<1>, C4<1>; +L_0x24bd440 .delay (20000,20000,20000) L_0x24bd440/d; +L_0x24bd530/d .functor OR 1, L_0x24bd350, L_0x24bd440, C4<0>, C4<0>; +L_0x24bd530 .delay (20000,20000,20000) L_0x24bd530/d; +v0x245ccf0_0 .net "S", 0 0, L_0x24bd6c0; 1 drivers +v0x245cd90_0 .alias "in0", 0 0, v0x245d420_0; +v0x245ce30_0 .alias "in1", 0 0, v0x245d8f0_0; +v0x245ced0_0 .net "nS", 0 0, L_0x24bd2f0; 1 drivers +v0x245cf80_0 .net "out0", 0 0, L_0x24bd350; 1 drivers +v0x245d020_0 .net "out1", 0 0, L_0x24bd440; 1 drivers +v0x245d100_0 .alias "outfinal", 0 0, v0x245d4d0_0; +S_0x245b800 .scope generate, "addbits[5]" "addbits[5]" 2 230, 2 230, S_0x2426ca0; + .timescale -9 -12; +P_0x245b218 .param/l "i" 2 230, +C4<0101>; +S_0x245b970 .scope module, "attempt" "MiddleAddSubSLT" 2 232, 2 89, S_0x245b800; + .timescale -9 -12; +L_0x24bbd60/d .functor NOT 1, L_0x24bf680, C4<0>, C4<0>, C4<0>; +L_0x24bbd60 .delay (10000,10000,10000) L_0x24bbd60/d; +L_0x24bec00/d .functor NOT 1, L_0x24beca0, C4<0>, C4<0>, C4<0>; +L_0x24bec00 .delay (10000,10000,10000) L_0x24bec00/d; +L_0x24bed40/d .functor AND 1, L_0x24bee80, L_0x24bec00, C4<1>, C4<1>; +L_0x24bed40 .delay (20000,20000,20000) L_0x24bed40/d; +L_0x24bef20/d .functor XOR 1, L_0x24bf7b0, L_0x24be9d0, C4<0>, C4<0>; +L_0x24bef20 .delay (40000,40000,40000) L_0x24bef20/d; +L_0x24bf010/d .functor XOR 1, L_0x24bef20, L_0x24bfb60, C4<0>, C4<0>; +L_0x24bf010 .delay (40000,40000,40000) L_0x24bf010/d; +L_0x24bf100/d .functor AND 1, L_0x24bf7b0, L_0x24be9d0, C4<1>, C4<1>; +L_0x24bf100 .delay (20000,20000,20000) L_0x24bf100/d; +L_0x24bf270/d .functor AND 1, L_0x24bef20, L_0x24bfb60, C4<1>, C4<1>; +L_0x24bf270 .delay (20000,20000,20000) L_0x24bf270/d; +L_0x24bf360/d .functor OR 1, L_0x24bf100, L_0x24bf270, C4<0>, C4<0>; +L_0x24bf360 .delay (20000,20000,20000) L_0x24bf360/d; +v0x245c000_0 .net "A", 0 0, L_0x24bf7b0; 1 drivers +v0x245c0c0_0 .net "AandB", 0 0, L_0x24bf100; 1 drivers +v0x245c160_0 .net "AddSubSLTSum", 0 0, L_0x24bf010; 1 drivers +v0x245c200_0 .net "AxorB", 0 0, L_0x24bef20; 1 drivers +v0x245c280_0 .net "B", 0 0, L_0x24bf680; 1 drivers +v0x245c330_0 .net "BornB", 0 0, L_0x24be9d0; 1 drivers +v0x245c3f0_0 .net "CINandAxorB", 0 0, L_0x24bf270; 1 drivers +v0x245c470_0 .alias "Command", 2 0, v0x2463430_0; +v0x245c4f0_0 .net *"_s3", 0 0, L_0x24beca0; 1 drivers +v0x245c570_0 .net *"_s5", 0 0, L_0x24bee80; 1 drivers +v0x245c610_0 .net "carryin", 0 0, L_0x24bfb60; 1 drivers +v0x245c6b0_0 .net "carryout", 0 0, L_0x24bf360; 1 drivers +v0x245c750_0 .net "nB", 0 0, L_0x24bbd60; 1 drivers +v0x245c800_0 .net "nCmd2", 0 0, L_0x24bec00; 1 drivers +v0x245c900_0 .net "subtract", 0 0, L_0x24bed40; 1 drivers +L_0x24beb60 .part C4, 0, 1; +L_0x24beca0 .part C4, 2, 1; +L_0x24bee80 .part C4, 0, 1; +S_0x245ba60 .scope module, "mux0" "TwoInMux" 2 105, 2 8, S_0x245b970; + .timescale -9 -12; +L_0x24be750/d .functor NOT 1, L_0x24beb60, C4<0>, C4<0>, C4<0>; +L_0x24be750 .delay (10000,10000,10000) L_0x24be750/d; +L_0x24be7f0/d .functor AND 1, L_0x24bf680, L_0x24be750, C4<1>, C4<1>; +L_0x24be7f0 .delay (20000,20000,20000) L_0x24be7f0/d; +L_0x24be8e0/d .functor AND 1, L_0x24bbd60, L_0x24beb60, C4<1>, C4<1>; +L_0x24be8e0 .delay (20000,20000,20000) L_0x24be8e0/d; +L_0x24be9d0/d .functor OR 1, L_0x24be7f0, L_0x24be8e0, C4<0>, C4<0>; +L_0x24be9d0 .delay (20000,20000,20000) L_0x24be9d0/d; +v0x245bb50_0 .net "S", 0 0, L_0x24beb60; 1 drivers +v0x245bbf0_0 .alias "in0", 0 0, v0x245c280_0; +v0x245bc90_0 .alias "in1", 0 0, v0x245c750_0; +v0x245bd30_0 .net "nS", 0 0, L_0x24be750; 1 drivers +v0x245bde0_0 .net "out0", 0 0, L_0x24be7f0; 1 drivers +v0x245be80_0 .net "out1", 0 0, L_0x24be8e0; 1 drivers +v0x245bf60_0 .alias "outfinal", 0 0, v0x245c330_0; +S_0x245a620 .scope generate, "addbits[6]" "addbits[6]" 2 230, 2 230, S_0x2426ca0; + .timescale -9 -12; +P_0x245a718 .param/l "i" 2 230, +C4<0110>; +S_0x245a7d0 .scope module, "attempt" "MiddleAddSubSLT" 2 232, 2 89, S_0x245a620; + .timescale -9 -12; +L_0x2478e10/d .functor NOT 1, L_0x24c0c70, C4<0>, C4<0>, C4<0>; +L_0x2478e10 .delay (10000,10000,10000) L_0x2478e10/d; +L_0x24c0190/d .functor NOT 1, L_0x24c0250, C4<0>, C4<0>, C4<0>; +L_0x24c0190 .delay (10000,10000,10000) L_0x24c0190/d; +L_0x24c02f0/d .functor AND 1, L_0x24c0430, L_0x24c0190, C4<1>, C4<1>; +L_0x24c02f0 .delay (20000,20000,20000) L_0x24c02f0/d; +L_0x24c04d0/d .functor XOR 1, L_0x24c0d80, L_0x24bff40, C4<0>, C4<0>; +L_0x24c04d0 .delay (40000,40000,40000) L_0x24c04d0/d; +L_0x24c05c0/d .functor XOR 1, L_0x24c04d0, L_0x24c0fd0, C4<0>, C4<0>; +L_0x24c05c0 .delay (40000,40000,40000) L_0x24c05c0/d; +L_0x24c06b0/d .functor AND 1, L_0x24c0d80, L_0x24bff40, C4<1>, C4<1>; +L_0x24c06b0 .delay (20000,20000,20000) L_0x24c06b0/d; +L_0x24c0820/d .functor AND 1, L_0x24c04d0, L_0x24c0fd0, C4<1>, C4<1>; +L_0x24c0820 .delay (20000,20000,20000) L_0x24c0820/d; +L_0x24c0930/d .functor OR 1, L_0x24c06b0, L_0x24c0820, C4<0>, C4<0>; +L_0x24c0930 .delay (20000,20000,20000) L_0x24c0930/d; +v0x245ae60_0 .net "A", 0 0, L_0x24c0d80; 1 drivers +v0x245af20_0 .net "AandB", 0 0, L_0x24c06b0; 1 drivers +v0x245afc0_0 .net "AddSubSLTSum", 0 0, L_0x24c05c0; 1 drivers +v0x245b060_0 .net "AxorB", 0 0, L_0x24c04d0; 1 drivers +v0x245b0e0_0 .net "B", 0 0, L_0x24c0c70; 1 drivers +v0x245b190_0 .net "BornB", 0 0, L_0x24bff40; 1 drivers +v0x245b250_0 .net "CINandAxorB", 0 0, L_0x24c0820; 1 drivers +v0x245b2d0_0 .alias "Command", 2 0, v0x2463430_0; +v0x245b350_0 .net *"_s3", 0 0, L_0x24c0250; 1 drivers +v0x245b3d0_0 .net *"_s5", 0 0, L_0x24c0430; 1 drivers +v0x245b470_0 .net "carryin", 0 0, L_0x24c0fd0; 1 drivers +v0x245b510_0 .net "carryout", 0 0, L_0x24c0930; 1 drivers +v0x245b5b0_0 .net "nB", 0 0, L_0x2478e10; 1 drivers +v0x245b660_0 .net "nCmd2", 0 0, L_0x24c0190; 1 drivers +v0x245b760_0 .net "subtract", 0 0, L_0x24c02f0; 1 drivers +L_0x24c00f0 .part C4, 0, 1; +L_0x24c0250 .part C4, 2, 1; +L_0x24c0430 .part C4, 0, 1; +S_0x245a8c0 .scope module, "mux0" "TwoInMux" 2 105, 2 8, S_0x245a7d0; + .timescale -9 -12; +L_0x24bfd00/d .functor NOT 1, L_0x24c00f0, C4<0>, C4<0>, C4<0>; +L_0x24bfd00 .delay (10000,10000,10000) L_0x24bfd00/d; +L_0x24bfd60/d .functor AND 1, L_0x24c0c70, L_0x24bfd00, C4<1>, C4<1>; +L_0x24bfd60 .delay (20000,20000,20000) L_0x24bfd60/d; +L_0x24bfe50/d .functor AND 1, L_0x2478e10, L_0x24c00f0, C4<1>, C4<1>; +L_0x24bfe50 .delay (20000,20000,20000) L_0x24bfe50/d; +L_0x24bff40/d .functor OR 1, L_0x24bfd60, L_0x24bfe50, C4<0>, C4<0>; +L_0x24bff40 .delay (20000,20000,20000) L_0x24bff40/d; +v0x245a9b0_0 .net "S", 0 0, L_0x24c00f0; 1 drivers +v0x245aa50_0 .alias "in0", 0 0, v0x245b0e0_0; +v0x245aaf0_0 .alias "in1", 0 0, v0x245b5b0_0; +v0x245ab90_0 .net "nS", 0 0, L_0x24bfd00; 1 drivers +v0x245ac40_0 .net "out0", 0 0, L_0x24bfd60; 1 drivers +v0x245ace0_0 .net "out1", 0 0, L_0x24bfe50; 1 drivers +v0x245adc0_0 .alias "outfinal", 0 0, v0x245b190_0; +S_0x24594b0 .scope generate, "addbits[7]" "addbits[7]" 2 230, 2 230, S_0x2426ca0; + .timescale -9 -12; +P_0x2458ec8 .param/l "i" 2 230, +C4<0111>; +S_0x2459620 .scope module, "attempt" "MiddleAddSubSLT" 2 232, 2 89, S_0x24594b0; + .timescale -9 -12; +L_0x24c0d10/d .functor NOT 1, L_0x24c21b0, C4<0>, C4<0>, C4<0>; +L_0x24c0d10 .delay (10000,10000,10000) L_0x24c0d10/d; +L_0x24c16d0/d .functor NOT 1, L_0x24c1790, C4<0>, C4<0>, C4<0>; +L_0x24c16d0 .delay (10000,10000,10000) L_0x24c16d0/d; +L_0x24c1830/d .functor AND 1, L_0x24c1970, L_0x24c16d0, C4<1>, C4<1>; +L_0x24c1830 .delay (20000,20000,20000) L_0x24c1830/d; +L_0x24c1a10/d .functor XOR 1, L_0x24c2400, L_0x24c1460, C4<0>, C4<0>; +L_0x24c1a10 .delay (40000,40000,40000) L_0x24c1a10/d; +L_0x24c1b00/d .functor XOR 1, L_0x24c1a10, L_0x24c2250, C4<0>, C4<0>; +L_0x24c1b00 .delay (40000,40000,40000) L_0x24c1b00/d; +L_0x24c1bf0/d .functor AND 1, L_0x24c2400, L_0x24c1460, C4<1>, C4<1>; +L_0x24c1bf0 .delay (20000,20000,20000) L_0x24c1bf0/d; +L_0x24c1d60/d .functor AND 1, L_0x24c1a10, L_0x24c2250, C4<1>, C4<1>; +L_0x24c1d60 .delay (20000,20000,20000) L_0x24c1d60/d; +L_0x24c1e50/d .functor OR 1, L_0x24c1bf0, L_0x24c1d60, C4<0>, C4<0>; +L_0x24c1e50 .delay (20000,20000,20000) L_0x24c1e50/d; +v0x2459cb0_0 .net "A", 0 0, L_0x24c2400; 1 drivers +v0x2459d70_0 .net "AandB", 0 0, L_0x24c1bf0; 1 drivers +v0x2459e10_0 .net "AddSubSLTSum", 0 0, L_0x24c1b00; 1 drivers +v0x2459eb0_0 .net "AxorB", 0 0, L_0x24c1a10; 1 drivers +v0x2459f30_0 .net "B", 0 0, L_0x24c21b0; 1 drivers +v0x2459fe0_0 .net "BornB", 0 0, L_0x24c1460; 1 drivers +v0x245a060_0 .net "CINandAxorB", 0 0, L_0x24c1d60; 1 drivers +v0x245a0e0_0 .alias "Command", 2 0, v0x2463430_0; +v0x245a160_0 .net *"_s3", 0 0, L_0x24c1790; 1 drivers +v0x245a1e0_0 .net *"_s5", 0 0, L_0x24c1970; 1 drivers +v0x245a260_0 .net "carryin", 0 0, L_0x24c2250; 1 drivers +v0x245a2e0_0 .net "carryout", 0 0, L_0x24c1e50; 1 drivers +v0x245a3d0_0 .net "nB", 0 0, L_0x24c0d10; 1 drivers +v0x245a480_0 .net "nCmd2", 0 0, L_0x24c16d0; 1 drivers +v0x245a580_0 .net "subtract", 0 0, L_0x24c1830; 1 drivers +L_0x24c1630 .part C4, 0, 1; +L_0x24c1790 .part C4, 2, 1; +L_0x24c1970 .part C4, 0, 1; +S_0x2459710 .scope module, "mux0" "TwoInMux" 2 105, 2 8, S_0x2459620; + .timescale -9 -12; +L_0x24c11a0/d .functor NOT 1, L_0x24c1630, C4<0>, C4<0>, C4<0>; +L_0x24c11a0 .delay (10000,10000,10000) L_0x24c11a0/d; +L_0x24c1240/d .functor AND 1, L_0x24c21b0, L_0x24c11a0, C4<1>, C4<1>; +L_0x24c1240 .delay (20000,20000,20000) L_0x24c1240/d; +L_0x24c1350/d .functor AND 1, L_0x24c0d10, L_0x24c1630, C4<1>, C4<1>; +L_0x24c1350 .delay (20000,20000,20000) L_0x24c1350/d; +L_0x24c1460/d .functor OR 1, L_0x24c1240, L_0x24c1350, C4<0>, C4<0>; +L_0x24c1460 .delay (20000,20000,20000) L_0x24c1460/d; +v0x2459800_0 .net "S", 0 0, L_0x24c1630; 1 drivers +v0x24598a0_0 .alias "in0", 0 0, v0x2459f30_0; +v0x2459940_0 .alias "in1", 0 0, v0x245a3d0_0; +v0x24599e0_0 .net "nS", 0 0, L_0x24c11a0; 1 drivers +v0x2459a90_0 .net "out0", 0 0, L_0x24c1240; 1 drivers +v0x2459b30_0 .net "out1", 0 0, L_0x24c1350; 1 drivers +v0x2459c10_0 .alias "outfinal", 0 0, v0x2459fe0_0; +S_0x2458310 .scope generate, "addbits[8]" "addbits[8]" 2 230, 2 230, S_0x2426ca0; + .timescale -9 -12; +P_0x2457d28 .param/l "i" 2 230, +C4<01000>; +S_0x2458480 .scope module, "attempt" "MiddleAddSubSLT" 2 232, 2 89, S_0x2458310; + .timescale -9 -12; +L_0x24c2600/d .functor NOT 1, L_0x24c3730, C4<0>, C4<0>, C4<0>; +L_0x24c2600 .delay (10000,10000,10000) L_0x24c2600/d; +L_0x24c2c70/d .functor NOT 1, L_0x24c2d30, C4<0>, C4<0>, C4<0>; +L_0x24c2c70 .delay (10000,10000,10000) L_0x24c2c70/d; +L_0x24c2dd0/d .functor AND 1, L_0x24c2f10, L_0x24c2c70, C4<1>, C4<1>; +L_0x24c2dd0 .delay (20000,20000,20000) L_0x24c2dd0/d; +L_0x24c2fb0/d .functor XOR 1, L_0x24c38a0, L_0x24c2a00, C4<0>, C4<0>; +L_0x24c2fb0 .delay (40000,40000,40000) L_0x24c2fb0/d; +L_0x24c30a0/d .functor XOR 1, L_0x24c2fb0, L_0x24c3ac0, C4<0>, C4<0>; +L_0x24c30a0 .delay (40000,40000,40000) L_0x24c30a0/d; +L_0x24c3190/d .functor AND 1, L_0x24c38a0, L_0x24c2a00, C4<1>, C4<1>; +L_0x24c3190 .delay (20000,20000,20000) L_0x24c3190/d; +L_0x24c3300/d .functor AND 1, L_0x24c2fb0, L_0x24c3ac0, C4<1>, C4<1>; +L_0x24c3300 .delay (20000,20000,20000) L_0x24c3300/d; +L_0x24c33f0/d .functor OR 1, L_0x24c3190, L_0x24c3300, C4<0>, C4<0>; +L_0x24c33f0 .delay (20000,20000,20000) L_0x24c33f0/d; +v0x2458b10_0 .net "A", 0 0, L_0x24c38a0; 1 drivers +v0x2458bd0_0 .net "AandB", 0 0, L_0x24c3190; 1 drivers +v0x2458c70_0 .net "AddSubSLTSum", 0 0, L_0x24c30a0; 1 drivers +v0x2458d10_0 .net "AxorB", 0 0, L_0x24c2fb0; 1 drivers +v0x2458d90_0 .net "B", 0 0, L_0x24c3730; 1 drivers +v0x2458e40_0 .net "BornB", 0 0, L_0x24c2a00; 1 drivers +v0x2458f00_0 .net "CINandAxorB", 0 0, L_0x24c3300; 1 drivers +v0x2458f80_0 .alias "Command", 2 0, v0x2463430_0; +v0x2459000_0 .net *"_s3", 0 0, L_0x24c2d30; 1 drivers +v0x2459080_0 .net *"_s5", 0 0, L_0x24c2f10; 1 drivers +v0x2459120_0 .net "carryin", 0 0, L_0x24c3ac0; 1 drivers +v0x24591c0_0 .net "carryout", 0 0, L_0x24c33f0; 1 drivers +v0x2459260_0 .net "nB", 0 0, L_0x24c2600; 1 drivers +v0x2459310_0 .net "nCmd2", 0 0, L_0x24c2c70; 1 drivers +v0x2459410_0 .net "subtract", 0 0, L_0x24c2dd0; 1 drivers +L_0x24c2bd0 .part C4, 0, 1; +L_0x24c2d30 .part C4, 2, 1; +L_0x24c2f10 .part C4, 0, 1; +S_0x2458570 .scope module, "mux0" "TwoInMux" 2 105, 2 8, S_0x2458480; + .timescale -9 -12; +L_0x24c2720/d .functor NOT 1, L_0x24c2bd0, C4<0>, C4<0>, C4<0>; +L_0x24c2720 .delay (10000,10000,10000) L_0x24c2720/d; +L_0x24c27e0/d .functor AND 1, L_0x24c3730, L_0x24c2720, C4<1>, C4<1>; +L_0x24c27e0 .delay (20000,20000,20000) L_0x24c27e0/d; +L_0x24c28f0/d .functor AND 1, L_0x24c2600, L_0x24c2bd0, C4<1>, C4<1>; +L_0x24c28f0 .delay (20000,20000,20000) L_0x24c28f0/d; +L_0x24c2a00/d .functor OR 1, L_0x24c27e0, L_0x24c28f0, C4<0>, C4<0>; +L_0x24c2a00 .delay (20000,20000,20000) L_0x24c2a00/d; +v0x2458660_0 .net "S", 0 0, L_0x24c2bd0; 1 drivers +v0x2458700_0 .alias "in0", 0 0, v0x2458d90_0; +v0x24587a0_0 .alias "in1", 0 0, v0x2459260_0; +v0x2458840_0 .net "nS", 0 0, L_0x24c2720; 1 drivers +v0x24588f0_0 .net "out0", 0 0, L_0x24c27e0; 1 drivers +v0x2458990_0 .net "out1", 0 0, L_0x24c28f0; 1 drivers +v0x2458a70_0 .alias "outfinal", 0 0, v0x2458e40_0; +S_0x2457170 .scope generate, "addbits[9]" "addbits[9]" 2 230, 2 230, S_0x2426ca0; + .timescale -9 -12; +P_0x2456b88 .param/l "i" 2 230, +C4<01001>; +S_0x24572e0 .scope module, "attempt" "MiddleAddSubSLT" 2 232, 2 89, S_0x2457170; + .timescale -9 -12; +L_0x24c2590/d .functor NOT 1, L_0x24c4ef0, C4<0>, C4<0>, C4<0>; +L_0x24c2590 .delay (10000,10000,10000) L_0x24c2590/d; +L_0x24c4280/d .functor NOT 1, L_0x24c4340, C4<0>, C4<0>, C4<0>; +L_0x24c4280 .delay (10000,10000,10000) L_0x24c4280/d; +L_0x24c43e0/d .functor AND 1, L_0x24c4520, L_0x24c4280, C4<1>, C4<1>; +L_0x24c43e0 .delay (20000,20000,20000) L_0x24c43e0/d; +L_0x24c45c0/d .functor XOR 1, L_0x24c3e60, L_0x24c4010, C4<0>, C4<0>; +L_0x24c45c0 .delay (40000,40000,40000) L_0x24c45c0/d; +L_0x24c46b0/d .functor XOR 1, L_0x24c45c0, L_0x24c5020, C4<0>, C4<0>; +L_0x24c46b0 .delay (40000,40000,40000) L_0x24c46b0/d; +L_0x24c47a0/d .functor AND 1, L_0x24c3e60, L_0x24c4010, C4<1>, C4<1>; +L_0x24c47a0 .delay (20000,20000,20000) L_0x24c47a0/d; +L_0x24c4910/d .functor AND 1, L_0x24c45c0, L_0x24c5020, C4<1>, C4<1>; +L_0x24c4910 .delay (20000,20000,20000) L_0x24c4910/d; +L_0x24c4a00/d .functor OR 1, L_0x24c47a0, L_0x24c4910, C4<0>, C4<0>; +L_0x24c4a00 .delay (20000,20000,20000) L_0x24c4a00/d; +v0x2457970_0 .net "A", 0 0, L_0x24c3e60; 1 drivers +v0x2457a30_0 .net "AandB", 0 0, L_0x24c47a0; 1 drivers +v0x2457ad0_0 .net "AddSubSLTSum", 0 0, L_0x24c46b0; 1 drivers +v0x2457b70_0 .net "AxorB", 0 0, L_0x24c45c0; 1 drivers +v0x2457bf0_0 .net "B", 0 0, L_0x24c4ef0; 1 drivers +v0x2457ca0_0 .net "BornB", 0 0, L_0x24c4010; 1 drivers +v0x2457d60_0 .net "CINandAxorB", 0 0, L_0x24c4910; 1 drivers +v0x2457de0_0 .alias "Command", 2 0, v0x2463430_0; +v0x2457e60_0 .net *"_s3", 0 0, L_0x24c4340; 1 drivers +v0x2457ee0_0 .net *"_s5", 0 0, L_0x24c4520; 1 drivers +v0x2457f80_0 .net "carryin", 0 0, L_0x24c5020; 1 drivers +v0x2458020_0 .net "carryout", 0 0, L_0x24c4a00; 1 drivers +v0x24580c0_0 .net "nB", 0 0, L_0x24c2590; 1 drivers +v0x2458170_0 .net "nCmd2", 0 0, L_0x24c4280; 1 drivers +v0x2458270_0 .net "subtract", 0 0, L_0x24c43e0; 1 drivers +L_0x24c41e0 .part C4, 0, 1; +L_0x24c4340 .part C4, 2, 1; +L_0x24c4520 .part C4, 0, 1; +S_0x24573d0 .scope module, "mux0" "TwoInMux" 2 105, 2 8, S_0x24572e0; + .timescale -9 -12; +L_0x24c3940/d .functor NOT 1, L_0x24c41e0, C4<0>, C4<0>, C4<0>; +L_0x24c3940 .delay (10000,10000,10000) L_0x24c3940/d; +L_0x24c3a00/d .functor AND 1, L_0x24c4ef0, L_0x24c3940, C4<1>, C4<1>; +L_0x24c3a00 .delay (20000,20000,20000) L_0x24c3a00/d; +L_0x24c3f00/d .functor AND 1, L_0x24c2590, L_0x24c41e0, C4<1>, C4<1>; +L_0x24c3f00 .delay (20000,20000,20000) L_0x24c3f00/d; +L_0x24c4010/d .functor OR 1, L_0x24c3a00, L_0x24c3f00, C4<0>, C4<0>; +L_0x24c4010 .delay (20000,20000,20000) L_0x24c4010/d; +v0x24574c0_0 .net "S", 0 0, L_0x24c41e0; 1 drivers +v0x2457560_0 .alias "in0", 0 0, v0x2457bf0_0; +v0x2457600_0 .alias "in1", 0 0, v0x24580c0_0; +v0x24576a0_0 .net "nS", 0 0, L_0x24c3940; 1 drivers +v0x2457750_0 .net "out0", 0 0, L_0x24c3a00; 1 drivers +v0x24577f0_0 .net "out1", 0 0, L_0x24c3f00; 1 drivers +v0x24578d0_0 .alias "outfinal", 0 0, v0x2457ca0_0; +S_0x2455fd0 .scope generate, "addbits[10]" "addbits[10]" 2 230, 2 230, S_0x2426ca0; + .timescale -9 -12; +P_0x24559e8 .param/l "i" 2 230, +C4<01010>; +S_0x2456140 .scope module, "attempt" "MiddleAddSubSLT" 2 232, 2 89, S_0x2455fd0; + .timescale -9 -12; +L_0x24c4d40/d .functor NOT 1, L_0x24c6430, C4<0>, C4<0>, C4<0>; +L_0x24c4d40 .delay (10000,10000,10000) L_0x24c4d40/d; +L_0x24c5790/d .functor NOT 1, L_0x24c5850, C4<0>, C4<0>, C4<0>; +L_0x24c5790 .delay (10000,10000,10000) L_0x24c5790/d; +L_0x24c58f0/d .functor AND 1, L_0x24c5a30, L_0x24c5790, C4<1>, C4<1>; +L_0x24c58f0 .delay (20000,20000,20000) L_0x24c58f0/d; +L_0x24c5ad0/d .functor XOR 1, L_0x24c51b0, L_0x24c5520, C4<0>, C4<0>; +L_0x24c5ad0 .delay (40000,40000,40000) L_0x24c5ad0/d; +L_0x24c5bc0/d .functor XOR 1, L_0x24c5ad0, L_0x24c6560, C4<0>, C4<0>; +L_0x24c5bc0 .delay (40000,40000,40000) L_0x24c5bc0/d; +L_0x24c5cb0/d .functor AND 1, L_0x24c51b0, L_0x24c5520, C4<1>, C4<1>; +L_0x24c5cb0 .delay (20000,20000,20000) L_0x24c5cb0/d; +L_0x24c5e20/d .functor AND 1, L_0x24c5ad0, L_0x24c6560, C4<1>, C4<1>; +L_0x24c5e20 .delay (20000,20000,20000) L_0x24c5e20/d; +L_0x24c5f10/d .functor OR 1, L_0x24c5cb0, L_0x24c5e20, C4<0>, C4<0>; +L_0x24c5f10 .delay (20000,20000,20000) L_0x24c5f10/d; +v0x24567d0_0 .net "A", 0 0, L_0x24c51b0; 1 drivers +v0x2456890_0 .net "AandB", 0 0, L_0x24c5cb0; 1 drivers +v0x2456930_0 .net "AddSubSLTSum", 0 0, L_0x24c5bc0; 1 drivers +v0x24569d0_0 .net "AxorB", 0 0, L_0x24c5ad0; 1 drivers +v0x2456a50_0 .net "B", 0 0, L_0x24c6430; 1 drivers +v0x2456b00_0 .net "BornB", 0 0, L_0x24c5520; 1 drivers +v0x2456bc0_0 .net "CINandAxorB", 0 0, L_0x24c5e20; 1 drivers +v0x2456c40_0 .alias "Command", 2 0, v0x2463430_0; +v0x2456cc0_0 .net *"_s3", 0 0, L_0x24c5850; 1 drivers +v0x2456d40_0 .net *"_s5", 0 0, L_0x24c5a30; 1 drivers +v0x2456de0_0 .net "carryin", 0 0, L_0x24c6560; 1 drivers +v0x2456e80_0 .net "carryout", 0 0, L_0x24c5f10; 1 drivers +v0x2456f20_0 .net "nB", 0 0, L_0x24c4d40; 1 drivers +v0x2456fd0_0 .net "nCmd2", 0 0, L_0x24c5790; 1 drivers +v0x24570d0_0 .net "subtract", 0 0, L_0x24c58f0; 1 drivers +L_0x24c56f0 .part C4, 0, 1; +L_0x24c5850 .part C4, 2, 1; +L_0x24c5a30 .part C4, 0, 1; +S_0x2456230 .scope module, "mux0" "TwoInMux" 2 105, 2 8, S_0x2456140; + .timescale -9 -12; +L_0x24c5280/d .functor NOT 1, L_0x24c56f0, C4<0>, C4<0>, C4<0>; +L_0x24c5280 .delay (10000,10000,10000) L_0x24c5280/d; +L_0x24c5320/d .functor AND 1, L_0x24c6430, L_0x24c5280, C4<1>, C4<1>; +L_0x24c5320 .delay (20000,20000,20000) L_0x24c5320/d; +L_0x24c5410/d .functor AND 1, L_0x24c4d40, L_0x24c56f0, C4<1>, C4<1>; +L_0x24c5410 .delay (20000,20000,20000) L_0x24c5410/d; +L_0x24c5520/d .functor OR 1, L_0x24c5320, L_0x24c5410, C4<0>, C4<0>; +L_0x24c5520 .delay (20000,20000,20000) L_0x24c5520/d; +v0x2456320_0 .net "S", 0 0, L_0x24c56f0; 1 drivers +v0x24563c0_0 .alias "in0", 0 0, v0x2456a50_0; +v0x2456460_0 .alias "in1", 0 0, v0x2456f20_0; +v0x2456500_0 .net "nS", 0 0, L_0x24c5280; 1 drivers +v0x24565b0_0 .net "out0", 0 0, L_0x24c5320; 1 drivers +v0x2456650_0 .net "out1", 0 0, L_0x24c5410; 1 drivers +v0x2456730_0 .alias "outfinal", 0 0, v0x2456b00_0; +S_0x2454e30 .scope generate, "addbits[11]" "addbits[11]" 2 230, 2 230, S_0x2426ca0; + .timescale -9 -12; +P_0x2454848 .param/l "i" 2 230, +C4<01011>; +S_0x2454fa0 .scope module, "attempt" "MiddleAddSubSLT" 2 232, 2 89, S_0x2454e30; + .timescale -9 -12; +L_0x24c6250/d .functor NOT 1, L_0x24c7970, C4<0>, C4<0>, C4<0>; +L_0x24c6250 .delay (10000,10000,10000) L_0x24c6250/d; +L_0x24c6ca0/d .functor NOT 1, L_0x24c6d60, C4<0>, C4<0>, C4<0>; +L_0x24c6ca0 .delay (10000,10000,10000) L_0x24c6ca0/d; +L_0x24c6e00/d .functor AND 1, L_0x24c6f40, L_0x24c6ca0, C4<1>, C4<1>; +L_0x24c6e00 .delay (20000,20000,20000) L_0x24c6e00/d; +L_0x24c6fe0/d .functor XOR 1, L_0x24c66f0, L_0x24c6a30, C4<0>, C4<0>; +L_0x24c6fe0 .delay (40000,40000,40000) L_0x24c6fe0/d; +L_0x24c70d0/d .functor XOR 1, L_0x24c6fe0, L_0x24c7aa0, C4<0>, C4<0>; +L_0x24c70d0 .delay (40000,40000,40000) L_0x24c70d0/d; +L_0x24c71c0/d .functor AND 1, L_0x24c66f0, L_0x24c6a30, C4<1>, C4<1>; +L_0x24c71c0 .delay (20000,20000,20000) L_0x24c71c0/d; +L_0x24c7330/d .functor AND 1, L_0x24c6fe0, L_0x24c7aa0, C4<1>, C4<1>; +L_0x24c7330 .delay (20000,20000,20000) L_0x24c7330/d; +L_0x24c7420/d .functor OR 1, L_0x24c71c0, L_0x24c7330, C4<0>, C4<0>; +L_0x24c7420 .delay (20000,20000,20000) L_0x24c7420/d; +v0x2455630_0 .net "A", 0 0, L_0x24c66f0; 1 drivers +v0x24556f0_0 .net "AandB", 0 0, L_0x24c71c0; 1 drivers +v0x2455790_0 .net "AddSubSLTSum", 0 0, L_0x24c70d0; 1 drivers +v0x2455830_0 .net "AxorB", 0 0, L_0x24c6fe0; 1 drivers +v0x24558b0_0 .net "B", 0 0, L_0x24c7970; 1 drivers +v0x2455960_0 .net "BornB", 0 0, L_0x24c6a30; 1 drivers +v0x2455a20_0 .net "CINandAxorB", 0 0, L_0x24c7330; 1 drivers +v0x2455aa0_0 .alias "Command", 2 0, v0x2463430_0; +v0x2455b20_0 .net *"_s3", 0 0, L_0x24c6d60; 1 drivers +v0x2455ba0_0 .net *"_s5", 0 0, L_0x24c6f40; 1 drivers +v0x2455c40_0 .net "carryin", 0 0, L_0x24c7aa0; 1 drivers +v0x2455ce0_0 .net "carryout", 0 0, L_0x24c7420; 1 drivers +v0x2455d80_0 .net "nB", 0 0, L_0x24c6250; 1 drivers +v0x2455e30_0 .net "nCmd2", 0 0, L_0x24c6ca0; 1 drivers +v0x2455f30_0 .net "subtract", 0 0, L_0x24c6e00; 1 drivers +L_0x24c6c00 .part C4, 0, 1; +L_0x24c6d60 .part C4, 2, 1; +L_0x24c6f40 .part C4, 0, 1; +S_0x2455090 .scope module, "mux0" "TwoInMux" 2 105, 2 8, S_0x2454fa0; + .timescale -9 -12; +L_0x24c63b0/d .functor NOT 1, L_0x24c6c00, C4<0>, C4<0>, C4<0>; +L_0x24c63b0 .delay (10000,10000,10000) L_0x24c63b0/d; +L_0x24c6830/d .functor AND 1, L_0x24c7970, L_0x24c63b0, C4<1>, C4<1>; +L_0x24c6830 .delay (20000,20000,20000) L_0x24c6830/d; +L_0x24c6920/d .functor AND 1, L_0x24c6250, L_0x24c6c00, C4<1>, C4<1>; +L_0x24c6920 .delay (20000,20000,20000) L_0x24c6920/d; +L_0x24c6a30/d .functor OR 1, L_0x24c6830, L_0x24c6920, C4<0>, C4<0>; +L_0x24c6a30 .delay (20000,20000,20000) L_0x24c6a30/d; +v0x2455180_0 .net "S", 0 0, L_0x24c6c00; 1 drivers +v0x2455220_0 .alias "in0", 0 0, v0x24558b0_0; +v0x24552c0_0 .alias "in1", 0 0, v0x2455d80_0; +v0x2455360_0 .net "nS", 0 0, L_0x24c63b0; 1 drivers +v0x2455410_0 .net "out0", 0 0, L_0x24c6830; 1 drivers +v0x24554b0_0 .net "out1", 0 0, L_0x24c6920; 1 drivers +v0x2455590_0 .alias "outfinal", 0 0, v0x2455960_0; +S_0x2453c90 .scope generate, "addbits[12]" "addbits[12]" 2 230, 2 230, S_0x2426ca0; + .timescale -9 -12; +P_0x24536a8 .param/l "i" 2 230, +C4<01100>; +S_0x2453e00 .scope module, "attempt" "MiddleAddSubSLT" 2 232, 2 89, S_0x2453c90; + .timescale -9 -12; +L_0x24c6790/d .functor NOT 1, L_0x24c8eb0, C4<0>, C4<0>, C4<0>; +L_0x24c6790 .delay (10000,10000,10000) L_0x24c6790/d; +L_0x24c81b0/d .functor NOT 1, L_0x24c8270, C4<0>, C4<0>, C4<0>; +L_0x24c81b0 .delay (10000,10000,10000) L_0x24c81b0/d; +L_0x24c8310/d .functor AND 1, L_0x24c8450, L_0x24c81b0, C4<1>, C4<1>; +L_0x24c8310 .delay (20000,20000,20000) L_0x24c8310/d; +L_0x24c84f0/d .functor XOR 1, L_0x24c7c30, L_0x24c7f40, C4<0>, C4<0>; +L_0x24c84f0 .delay (40000,40000,40000) L_0x24c84f0/d; +L_0x24c85e0/d .functor XOR 1, L_0x24c84f0, L_0x24c8f50, C4<0>, C4<0>; +L_0x24c85e0 .delay (40000,40000,40000) L_0x24c85e0/d; +L_0x24c86d0/d .functor AND 1, L_0x24c7c30, L_0x24c7f40, C4<1>, C4<1>; +L_0x24c86d0 .delay (20000,20000,20000) L_0x24c86d0/d; +L_0x24c8840/d .functor AND 1, L_0x24c84f0, L_0x24c8f50, C4<1>, C4<1>; +L_0x24c8840 .delay (20000,20000,20000) L_0x24c8840/d; +L_0x24c8930/d .functor OR 1, L_0x24c86d0, L_0x24c8840, C4<0>, C4<0>; +L_0x24c8930 .delay (20000,20000,20000) L_0x24c8930/d; +v0x2454490_0 .net "A", 0 0, L_0x24c7c30; 1 drivers +v0x2454550_0 .net "AandB", 0 0, L_0x24c86d0; 1 drivers +v0x24545f0_0 .net "AddSubSLTSum", 0 0, L_0x24c85e0; 1 drivers +v0x2454690_0 .net "AxorB", 0 0, L_0x24c84f0; 1 drivers +v0x2454710_0 .net "B", 0 0, L_0x24c8eb0; 1 drivers +v0x24547c0_0 .net "BornB", 0 0, L_0x24c7f40; 1 drivers +v0x2454880_0 .net "CINandAxorB", 0 0, L_0x24c8840; 1 drivers +v0x2454900_0 .alias "Command", 2 0, v0x2463430_0; +v0x2454980_0 .net *"_s3", 0 0, L_0x24c8270; 1 drivers +v0x2454a00_0 .net *"_s5", 0 0, L_0x24c8450; 1 drivers +v0x2454aa0_0 .net "carryin", 0 0, L_0x24c8f50; 1 drivers +v0x2454b40_0 .net "carryout", 0 0, L_0x24c8930; 1 drivers +v0x2454be0_0 .net "nB", 0 0, L_0x24c6790; 1 drivers +v0x2454c90_0 .net "nCmd2", 0 0, L_0x24c81b0; 1 drivers +v0x2454d90_0 .net "subtract", 0 0, L_0x24c8310; 1 drivers +L_0x24c8110 .part C4, 0, 1; +L_0x24c8270 .part C4, 2, 1; +L_0x24c8450 .part C4, 0, 1; +S_0x2453ef0 .scope module, "mux0" "TwoInMux" 2 105, 2 8, S_0x2453e00; + .timescale -9 -12; +L_0x24c7860/d .functor NOT 1, L_0x24c8110, C4<0>, C4<0>, C4<0>; +L_0x24c7860 .delay (10000,10000,10000) L_0x24c7860/d; +L_0x24c7d60/d .functor AND 1, L_0x24c8eb0, L_0x24c7860, C4<1>, C4<1>; +L_0x24c7d60 .delay (20000,20000,20000) L_0x24c7d60/d; +L_0x24c7e50/d .functor AND 1, L_0x24c6790, L_0x24c8110, C4<1>, C4<1>; +L_0x24c7e50 .delay (20000,20000,20000) L_0x24c7e50/d; +L_0x24c7f40/d .functor OR 1, L_0x24c7d60, L_0x24c7e50, C4<0>, C4<0>; +L_0x24c7f40 .delay (20000,20000,20000) L_0x24c7f40/d; +v0x2453fe0_0 .net "S", 0 0, L_0x24c8110; 1 drivers +v0x2454080_0 .alias "in0", 0 0, v0x2454710_0; +v0x2454120_0 .alias "in1", 0 0, v0x2454be0_0; +v0x24541c0_0 .net "nS", 0 0, L_0x24c7860; 1 drivers +v0x2454270_0 .net "out0", 0 0, L_0x24c7d60; 1 drivers +v0x2454310_0 .net "out1", 0 0, L_0x24c7e50; 1 drivers +v0x24543f0_0 .alias "outfinal", 0 0, v0x24547c0_0; +S_0x2452af0 .scope generate, "addbits[13]" "addbits[13]" 2 230, 2 230, S_0x2426ca0; + .timescale -9 -12; +P_0x2452508 .param/l "i" 2 230, +C4<01101>; +S_0x2452c60 .scope module, "attempt" "MiddleAddSubSLT" 2 232, 2 89, S_0x2452af0; + .timescale -9 -12; +L_0x24c8c70/d .functor NOT 1, L_0x24c9180, C4<0>, C4<0>, C4<0>; +L_0x24c8c70 .delay (10000,10000,10000) L_0x24c8c70/d; +L_0x24c96b0/d .functor NOT 1, L_0x24c9770, C4<0>, C4<0>, C4<0>; +L_0x24c96b0 .delay (10000,10000,10000) L_0x24c96b0/d; +L_0x24c9810/d .functor AND 1, L_0x24c9950, L_0x24c96b0, C4<1>, C4<1>; +L_0x24c9810 .delay (20000,20000,20000) L_0x24c9810/d; +L_0x24c99f0/d .functor XOR 1, L_0x24c90e0, L_0x24c9440, C4<0>, C4<0>; +L_0x24c99f0 .delay (40000,40000,40000) L_0x24c99f0/d; +L_0x24c9ae0/d .functor XOR 1, L_0x24c99f0, L_0x24bfa50, C4<0>, C4<0>; +L_0x24c9ae0 .delay (40000,40000,40000) L_0x24c9ae0/d; +L_0x24c9bd0/d .functor AND 1, L_0x24c90e0, L_0x24c9440, C4<1>, C4<1>; +L_0x24c9bd0 .delay (20000,20000,20000) L_0x24c9bd0/d; +L_0x24c9d40/d .functor AND 1, L_0x24c99f0, L_0x24bfa50, C4<1>, C4<1>; +L_0x24c9d40 .delay (20000,20000,20000) L_0x24c9d40/d; +L_0x24c9e30/d .functor OR 1, L_0x24c9bd0, L_0x24c9d40, C4<0>, C4<0>; +L_0x24c9e30 .delay (20000,20000,20000) L_0x24c9e30/d; +v0x24532f0_0 .net "A", 0 0, L_0x24c90e0; 1 drivers +v0x24533b0_0 .net "AandB", 0 0, L_0x24c9bd0; 1 drivers +v0x2453450_0 .net "AddSubSLTSum", 0 0, L_0x24c9ae0; 1 drivers +v0x24534f0_0 .net "AxorB", 0 0, L_0x24c99f0; 1 drivers +v0x2453570_0 .net "B", 0 0, L_0x24c9180; 1 drivers +v0x2453620_0 .net "BornB", 0 0, L_0x24c9440; 1 drivers +v0x24536e0_0 .net "CINandAxorB", 0 0, L_0x24c9d40; 1 drivers +v0x2453760_0 .alias "Command", 2 0, v0x2463430_0; +v0x24537e0_0 .net *"_s3", 0 0, L_0x24c9770; 1 drivers +v0x2453860_0 .net *"_s5", 0 0, L_0x24c9950; 1 drivers +v0x2453900_0 .net "carryin", 0 0, L_0x24bfa50; 1 drivers +v0x24539a0_0 .net "carryout", 0 0, L_0x24c9e30; 1 drivers +v0x2453a40_0 .net "nB", 0 0, L_0x24c8c70; 1 drivers +v0x2453af0_0 .net "nCmd2", 0 0, L_0x24c96b0; 1 drivers +v0x2453bf0_0 .net "subtract", 0 0, L_0x24c9810; 1 drivers +L_0x24c9610 .part C4, 0, 1; +L_0x24c9770 .part C4, 2, 1; +L_0x24c9950 .part C4, 0, 1; +S_0x2452d50 .scope module, "mux0" "TwoInMux" 2 105, 2 8, S_0x2452c60; + .timescale -9 -12; +L_0x24c8dd0/d .functor NOT 1, L_0x24c9610, C4<0>, C4<0>, C4<0>; +L_0x24c8dd0 .delay (10000,10000,10000) L_0x24c8dd0/d; +L_0x24c9240/d .functor AND 1, L_0x24c9180, L_0x24c8dd0, C4<1>, C4<1>; +L_0x24c9240 .delay (20000,20000,20000) L_0x24c9240/d; +L_0x24c9330/d .functor AND 1, L_0x24c8c70, L_0x24c9610, C4<1>, C4<1>; +L_0x24c9330 .delay (20000,20000,20000) L_0x24c9330/d; +L_0x24c9440/d .functor OR 1, L_0x24c9240, L_0x24c9330, C4<0>, C4<0>; +L_0x24c9440 .delay (20000,20000,20000) L_0x24c9440/d; +v0x2452e40_0 .net "S", 0 0, L_0x24c9610; 1 drivers +v0x2452ee0_0 .alias "in0", 0 0, v0x2453570_0; +v0x2452f80_0 .alias "in1", 0 0, v0x2453a40_0; +v0x2453020_0 .net "nS", 0 0, L_0x24c8dd0; 1 drivers +v0x24530d0_0 .net "out0", 0 0, L_0x24c9240; 1 drivers +v0x2453170_0 .net "out1", 0 0, L_0x24c9330; 1 drivers +v0x2453250_0 .alias "outfinal", 0 0, v0x2453620_0; +S_0x2451950 .scope generate, "addbits[14]" "addbits[14]" 2 230, 2 230, S_0x2426ca0; + .timescale -9 -12; +P_0x2451368 .param/l "i" 2 230, +C4<01110>; +S_0x2451ac0 .scope module, "attempt" "MiddleAddSubSLT" 2 232, 2 89, S_0x2451950; + .timescale -9 -12; +L_0x24bfaf0/d .functor NOT 1, L_0x24ca770, C4<0>, C4<0>, C4<0>; +L_0x24bfaf0 .delay (10000,10000,10000) L_0x24bfaf0/d; +L_0x24cadd0/d .functor NOT 1, L_0x24cae90, C4<0>, C4<0>, C4<0>; +L_0x24cadd0 .delay (10000,10000,10000) L_0x24cadd0/d; +L_0x24caf30/d .functor AND 1, L_0x24cb070, L_0x24cadd0, C4<1>, C4<1>; +L_0x24caf30 .delay (20000,20000,20000) L_0x24caf30/d; +L_0x24cb110/d .functor XOR 1, L_0x24ca6d0, L_0x24cab60, C4<0>, C4<0>; +L_0x24cb110 .delay (40000,40000,40000) L_0x24cb110/d; +L_0x24cb200/d .functor XOR 1, L_0x24cb110, L_0x24cbbc0, C4<0>, C4<0>; +L_0x24cb200 .delay (40000,40000,40000) L_0x24cb200/d; +L_0x24cb2f0/d .functor AND 1, L_0x24ca6d0, L_0x24cab60, C4<1>, C4<1>; +L_0x24cb2f0 .delay (20000,20000,20000) L_0x24cb2f0/d; +L_0x24cb460/d .functor AND 1, L_0x24cb110, L_0x24cbbc0, C4<1>, C4<1>; +L_0x24cb460 .delay (20000,20000,20000) L_0x24cb460/d; +L_0x24cb550/d .functor OR 1, L_0x24cb2f0, L_0x24cb460, C4<0>, C4<0>; +L_0x24cb550 .delay (20000,20000,20000) L_0x24cb550/d; +v0x2452150_0 .net "A", 0 0, L_0x24ca6d0; 1 drivers +v0x2452210_0 .net "AandB", 0 0, L_0x24cb2f0; 1 drivers +v0x24522b0_0 .net "AddSubSLTSum", 0 0, L_0x24cb200; 1 drivers +v0x2452350_0 .net "AxorB", 0 0, L_0x24cb110; 1 drivers +v0x24523d0_0 .net "B", 0 0, L_0x24ca770; 1 drivers +v0x2452480_0 .net "BornB", 0 0, L_0x24cab60; 1 drivers +v0x2452540_0 .net "CINandAxorB", 0 0, L_0x24cb460; 1 drivers +v0x24525c0_0 .alias "Command", 2 0, v0x2463430_0; +v0x2452640_0 .net *"_s3", 0 0, L_0x24cae90; 1 drivers +v0x24526c0_0 .net *"_s5", 0 0, L_0x24cb070; 1 drivers +v0x2452760_0 .net "carryin", 0 0, L_0x24cbbc0; 1 drivers +v0x2452800_0 .net "carryout", 0 0, L_0x24cb550; 1 drivers +v0x24528a0_0 .net "nB", 0 0, L_0x24bfaf0; 1 drivers +v0x2452950_0 .net "nCmd2", 0 0, L_0x24cadd0; 1 drivers +v0x2452a50_0 .net "subtract", 0 0, L_0x24caf30; 1 drivers +L_0x24cad30 .part C4, 0, 1; +L_0x24cae90 .part C4, 2, 1; +L_0x24cb070 .part C4, 0, 1; +S_0x2451bb0 .scope module, "mux0" "TwoInMux" 2 105, 2 8, S_0x2451ac0; + .timescale -9 -12; +L_0x24ca880/d .functor NOT 1, L_0x24cad30, C4<0>, C4<0>, C4<0>; +L_0x24ca880 .delay (10000,10000,10000) L_0x24ca880/d; +L_0x24ca940/d .functor AND 1, L_0x24ca770, L_0x24ca880, C4<1>, C4<1>; +L_0x24ca940 .delay (20000,20000,20000) L_0x24ca940/d; +L_0x24caa50/d .functor AND 1, L_0x24bfaf0, L_0x24cad30, C4<1>, C4<1>; +L_0x24caa50 .delay (20000,20000,20000) L_0x24caa50/d; +L_0x24cab60/d .functor OR 1, L_0x24ca940, L_0x24caa50, C4<0>, C4<0>; +L_0x24cab60 .delay (20000,20000,20000) L_0x24cab60/d; +v0x2451ca0_0 .net "S", 0 0, L_0x24cad30; 1 drivers +v0x2451d40_0 .alias "in0", 0 0, v0x24523d0_0; +v0x2451de0_0 .alias "in1", 0 0, v0x24528a0_0; +v0x2451e80_0 .net "nS", 0 0, L_0x24ca880; 1 drivers +v0x2451f30_0 .net "out0", 0 0, L_0x24ca940; 1 drivers +v0x2451fd0_0 .net "out1", 0 0, L_0x24caa50; 1 drivers +v0x24520b0_0 .alias "outfinal", 0 0, v0x2452480_0; +S_0x24507b0 .scope generate, "addbits[15]" "addbits[15]" 2 230, 2 230, S_0x2426ca0; + .timescale -9 -12; +P_0x24501c8 .param/l "i" 2 230, +C4<01111>; +S_0x2450920 .scope module, "attempt" "MiddleAddSubSLT" 2 232, 2 89, S_0x24507b0; + .timescale -9 -12; +L_0x24cb890/d .functor NOT 1, L_0x24cd070, C4<0>, C4<0>, C4<0>; +L_0x24cb890 .delay (10000,10000,10000) L_0x24cb890/d; +L_0x24cc2e0/d .functor NOT 1, L_0x24cc3a0, C4<0>, C4<0>, C4<0>; +L_0x24cc2e0 .delay (10000,10000,10000) L_0x24cc2e0/d; +L_0x24cc440/d .functor AND 1, L_0x24cc580, L_0x24cc2e0, C4<1>, C4<1>; +L_0x24cc440 .delay (20000,20000,20000) L_0x24cc440/d; +L_0x24cc620/d .functor XOR 1, L_0x24c2340, L_0x24cc070, C4<0>, C4<0>; +L_0x24cc620 .delay (40000,40000,40000) L_0x24cc620/d; +L_0x24cc710/d .functor XOR 1, L_0x24cc620, L_0x24cd1a0, C4<0>, C4<0>; +L_0x24cc710 .delay (40000,40000,40000) L_0x24cc710/d; +L_0x24cc800/d .functor AND 1, L_0x24c2340, L_0x24cc070, C4<1>, C4<1>; +L_0x24cc800 .delay (20000,20000,20000) L_0x24cc800/d; +L_0x24cc970/d .functor AND 1, L_0x24cc620, L_0x24cd1a0, C4<1>, C4<1>; +L_0x24cc970 .delay (20000,20000,20000) L_0x24cc970/d; +L_0x24cca60/d .functor OR 1, L_0x24cc800, L_0x24cc970, C4<0>, C4<0>; +L_0x24cca60 .delay (20000,20000,20000) L_0x24cca60/d; +v0x2450fb0_0 .net "A", 0 0, L_0x24c2340; 1 drivers +v0x2451070_0 .net "AandB", 0 0, L_0x24cc800; 1 drivers +v0x2451110_0 .net "AddSubSLTSum", 0 0, L_0x24cc710; 1 drivers +v0x24511b0_0 .net "AxorB", 0 0, L_0x24cc620; 1 drivers +v0x2451230_0 .net "B", 0 0, L_0x24cd070; 1 drivers +v0x24512e0_0 .net "BornB", 0 0, L_0x24cc070; 1 drivers +v0x24513a0_0 .net "CINandAxorB", 0 0, L_0x24cc970; 1 drivers +v0x2451420_0 .alias "Command", 2 0, v0x2463430_0; +v0x24514a0_0 .net *"_s3", 0 0, L_0x24cc3a0; 1 drivers +v0x2451520_0 .net *"_s5", 0 0, L_0x24cc580; 1 drivers +v0x24515c0_0 .net "carryin", 0 0, L_0x24cd1a0; 1 drivers +v0x2451660_0 .net "carryout", 0 0, L_0x24cca60; 1 drivers +v0x2451700_0 .net "nB", 0 0, L_0x24cb890; 1 drivers +v0x24517b0_0 .net "nCmd2", 0 0, L_0x24cc2e0; 1 drivers +v0x24518b0_0 .net "subtract", 0 0, L_0x24cc440; 1 drivers +L_0x24cc240 .part C4, 0, 1; +L_0x24cc3a0 .part C4, 2, 1; +L_0x24cc580 .part C4, 0, 1; +S_0x2450a10 .scope module, "mux0" "TwoInMux" 2 105, 2 8, S_0x2450920; + .timescale -9 -12; +L_0x24cb9a0/d .functor NOT 1, L_0x24cc240, C4<0>, C4<0>, C4<0>; +L_0x24cb9a0 .delay (10000,10000,10000) L_0x24cb9a0/d; +L_0x24cba60/d .functor AND 1, L_0x24cd070, L_0x24cb9a0, C4<1>, C4<1>; +L_0x24cba60 .delay (20000,20000,20000) L_0x24cba60/d; +L_0x24cbf60/d .functor AND 1, L_0x24cb890, L_0x24cc240, C4<1>, C4<1>; +L_0x24cbf60 .delay (20000,20000,20000) L_0x24cbf60/d; +L_0x24cc070/d .functor OR 1, L_0x24cba60, L_0x24cbf60, C4<0>, C4<0>; +L_0x24cc070 .delay (20000,20000,20000) L_0x24cc070/d; +v0x2450b00_0 .net "S", 0 0, L_0x24cc240; 1 drivers +v0x2450ba0_0 .alias "in0", 0 0, v0x2451230_0; +v0x2450c40_0 .alias "in1", 0 0, v0x2451700_0; +v0x2450ce0_0 .net "nS", 0 0, L_0x24cb9a0; 1 drivers +v0x2450d90_0 .net "out0", 0 0, L_0x24cba60; 1 drivers +v0x2450e30_0 .net "out1", 0 0, L_0x24cbf60; 1 drivers +v0x2450f10_0 .alias "outfinal", 0 0, v0x24512e0_0; +S_0x244f610 .scope generate, "addbits[16]" "addbits[16]" 2 230, 2 230, S_0x2426ca0; + .timescale -9 -12; +P_0x244f028 .param/l "i" 2 230, +C4<010000>; +S_0x244f780 .scope module, "attempt" "MiddleAddSubSLT" 2 232, 2 89, S_0x244f610; + .timescale -9 -12; +L_0x24ccda0/d .functor NOT 1, L_0x24cd3d0, C4<0>, C4<0>, C4<0>; +L_0x24ccda0 .delay (10000,10000,10000) L_0x24ccda0/d; +L_0x24cd8f0/d .functor NOT 1, L_0x24cd9b0, C4<0>, C4<0>, C4<0>; +L_0x24cd8f0 .delay (10000,10000,10000) L_0x24cd8f0/d; +L_0x24cda50/d .functor AND 1, L_0x24cdb90, L_0x24cd8f0, C4<1>, C4<1>; +L_0x24cda50 .delay (20000,20000,20000) L_0x24cda50/d; +L_0x24cdc30/d .functor XOR 1, L_0x24cd330, L_0x24cd680, C4<0>, C4<0>; +L_0x24cdc30 .delay (40000,40000,40000) L_0x24cdc30/d; +L_0x24cdd20/d .functor XOR 1, L_0x24cdc30, L_0x24ce6b0, C4<0>, C4<0>; +L_0x24cdd20 .delay (40000,40000,40000) L_0x24cdd20/d; +L_0x24cde10/d .functor AND 1, L_0x24cd330, L_0x24cd680, C4<1>, C4<1>; +L_0x24cde10 .delay (20000,20000,20000) L_0x24cde10/d; +L_0x24cdf80/d .functor AND 1, L_0x24cdc30, L_0x24ce6b0, C4<1>, C4<1>; +L_0x24cdf80 .delay (20000,20000,20000) L_0x24cdf80/d; +L_0x24ce070/d .functor OR 1, L_0x24cde10, L_0x24cdf80, C4<0>, C4<0>; +L_0x24ce070 .delay (20000,20000,20000) L_0x24ce070/d; +v0x244fe10_0 .net "A", 0 0, L_0x24cd330; 1 drivers +v0x244fed0_0 .net "AandB", 0 0, L_0x24cde10; 1 drivers +v0x244ff70_0 .net "AddSubSLTSum", 0 0, L_0x24cdd20; 1 drivers +v0x2450010_0 .net "AxorB", 0 0, L_0x24cdc30; 1 drivers +v0x2450090_0 .net "B", 0 0, L_0x24cd3d0; 1 drivers +v0x2450140_0 .net "BornB", 0 0, L_0x24cd680; 1 drivers +v0x2450200_0 .net "CINandAxorB", 0 0, L_0x24cdf80; 1 drivers +v0x2450280_0 .alias "Command", 2 0, v0x2463430_0; +v0x2450300_0 .net *"_s3", 0 0, L_0x24cd9b0; 1 drivers +v0x2450380_0 .net *"_s5", 0 0, L_0x24cdb90; 1 drivers +v0x2450420_0 .net "carryin", 0 0, L_0x24ce6b0; 1 drivers +v0x24504c0_0 .net "carryout", 0 0, L_0x24ce070; 1 drivers +v0x2450560_0 .net "nB", 0 0, L_0x24ccda0; 1 drivers +v0x2450610_0 .net "nCmd2", 0 0, L_0x24cd8f0; 1 drivers +v0x2450710_0 .net "subtract", 0 0, L_0x24cda50; 1 drivers +L_0x24cd850 .part C4, 0, 1; +L_0x24cd9b0 .part C4, 2, 1; +L_0x24cdb90 .part C4, 0, 1; +S_0x244f870 .scope module, "mux0" "TwoInMux" 2 105, 2 8, S_0x244f780; + .timescale -9 -12; +L_0x24ccee0/d .functor NOT 1, L_0x24cd850, C4<0>, C4<0>, C4<0>; +L_0x24ccee0 .delay (10000,10000,10000) L_0x24ccee0/d; +L_0x24ccfa0/d .functor AND 1, L_0x24cd3d0, L_0x24ccee0, C4<1>, C4<1>; +L_0x24ccfa0 .delay (20000,20000,20000) L_0x24ccfa0/d; +L_0x24cd570/d .functor AND 1, L_0x24ccda0, L_0x24cd850, C4<1>, C4<1>; +L_0x24cd570 .delay (20000,20000,20000) L_0x24cd570/d; +L_0x24cd680/d .functor OR 1, L_0x24ccfa0, L_0x24cd570, C4<0>, C4<0>; +L_0x24cd680 .delay (20000,20000,20000) L_0x24cd680/d; +v0x244f960_0 .net "S", 0 0, L_0x24cd850; 1 drivers +v0x244fa00_0 .alias "in0", 0 0, v0x2450090_0; +v0x244faa0_0 .alias "in1", 0 0, v0x2450560_0; +v0x244fb40_0 .net "nS", 0 0, L_0x24ccee0; 1 drivers +v0x244fbf0_0 .net "out0", 0 0, L_0x24ccfa0; 1 drivers +v0x244fc90_0 .net "out1", 0 0, L_0x24cd570; 1 drivers +v0x244fd70_0 .alias "outfinal", 0 0, v0x2450140_0; +S_0x244e470 .scope generate, "addbits[17]" "addbits[17]" 2 230, 2 230, S_0x2426ca0; + .timescale -9 -12; +P_0x244de88 .param/l "i" 2 230, +C4<010001>; +S_0x244e5e0 .scope module, "attempt" "MiddleAddSubSLT" 2 232, 2 89, S_0x244e470; + .timescale -9 -12; +L_0x24bcd50/d .functor NOT 1, L_0x24cecf0, C4<0>, C4<0>, C4<0>; +L_0x24bcd50 .delay (10000,10000,10000) L_0x24bcd50/d; +L_0x24cef60/d .functor NOT 1, L_0x24cf000, C4<0>, C4<0>, C4<0>; +L_0x24cef60 .delay (10000,10000,10000) L_0x24cef60/d; +L_0x24cf0a0/d .functor AND 1, L_0x24cf1e0, L_0x24cef60, C4<1>, C4<1>; +L_0x24cf0a0 .delay (20000,20000,20000) L_0x24cf0a0/d; +L_0x24cf280/d .functor XOR 1, L_0x24cec50, L_0x24ce550, C4<0>, C4<0>; +L_0x24cf280 .delay (40000,40000,40000) L_0x24cf280/d; +L_0x24cf370/d .functor XOR 1, L_0x24cf280, L_0x24cfd10, C4<0>, C4<0>; +L_0x24cf370 .delay (40000,40000,40000) L_0x24cf370/d; +L_0x24cf460/d .functor AND 1, L_0x24cec50, L_0x24ce550, C4<1>, C4<1>; +L_0x24cf460 .delay (20000,20000,20000) L_0x24cf460/d; +L_0x24cf5d0/d .functor AND 1, L_0x24cf280, L_0x24cfd10, C4<1>, C4<1>; +L_0x24cf5d0 .delay (20000,20000,20000) L_0x24cf5d0/d; +L_0x24cf6c0/d .functor OR 1, L_0x24cf460, L_0x24cf5d0, C4<0>, C4<0>; +L_0x24cf6c0 .delay (20000,20000,20000) L_0x24cf6c0/d; +v0x244ec70_0 .net "A", 0 0, L_0x24cec50; 1 drivers +v0x244ed30_0 .net "AandB", 0 0, L_0x24cf460; 1 drivers +v0x244edd0_0 .net "AddSubSLTSum", 0 0, L_0x24cf370; 1 drivers +v0x244ee70_0 .net "AxorB", 0 0, L_0x24cf280; 1 drivers +v0x244eef0_0 .net "B", 0 0, L_0x24cecf0; 1 drivers +v0x244efa0_0 .net "BornB", 0 0, L_0x24ce550; 1 drivers +v0x244f060_0 .net "CINandAxorB", 0 0, L_0x24cf5d0; 1 drivers +v0x244f0e0_0 .alias "Command", 2 0, v0x2463430_0; +v0x244f160_0 .net *"_s3", 0 0, L_0x24cf000; 1 drivers +v0x244f1e0_0 .net *"_s5", 0 0, L_0x24cf1e0; 1 drivers +v0x244f280_0 .net "carryin", 0 0, L_0x24cfd10; 1 drivers +v0x244f320_0 .net "carryout", 0 0, L_0x24cf6c0; 1 drivers +v0x244f3c0_0 .net "nB", 0 0, L_0x24bcd50; 1 drivers +v0x244f470_0 .net "nCmd2", 0 0, L_0x24cef60; 1 drivers +v0x244f570_0 .net "subtract", 0 0, L_0x24cf0a0; 1 drivers +L_0x24ceec0 .part C4, 0, 1; +L_0x24cf000 .part C4, 2, 1; +L_0x24cf1e0 .part C4, 0, 1; +S_0x244e6d0 .scope module, "mux0" "TwoInMux" 2 105, 2 8, S_0x244e5e0; + .timescale -9 -12; +L_0x24c3c20/d .functor NOT 1, L_0x24ceec0, C4<0>, C4<0>, C4<0>; +L_0x24c3c20 .delay (10000,10000,10000) L_0x24c3c20/d; +L_0x24c3ce0/d .functor AND 1, L_0x24cecf0, L_0x24c3c20, C4<1>, C4<1>; +L_0x24c3ce0 .delay (20000,20000,20000) L_0x24c3ce0/d; +L_0x24ce440/d .functor AND 1, L_0x24bcd50, L_0x24ceec0, C4<1>, C4<1>; +L_0x24ce440 .delay (20000,20000,20000) L_0x24ce440/d; +L_0x24ce550/d .functor OR 1, L_0x24c3ce0, L_0x24ce440, C4<0>, C4<0>; +L_0x24ce550 .delay (20000,20000,20000) L_0x24ce550/d; +v0x244e7c0_0 .net "S", 0 0, L_0x24ceec0; 1 drivers +v0x244e860_0 .alias "in0", 0 0, v0x244eef0_0; +v0x244e900_0 .alias "in1", 0 0, v0x244f3c0_0; +v0x244e9a0_0 .net "nS", 0 0, L_0x24c3c20; 1 drivers +v0x244ea50_0 .net "out0", 0 0, L_0x24c3ce0; 1 drivers +v0x244eaf0_0 .net "out1", 0 0, L_0x24ce440; 1 drivers +v0x244ebd0_0 .alias "outfinal", 0 0, v0x244efa0_0; +S_0x244d2d0 .scope generate, "addbits[18]" "addbits[18]" 2 230, 2 230, S_0x2426ca0; + .timescale -9 -12; +P_0x244cce8 .param/l "i" 2 230, +C4<010010>; +S_0x244d440 .scope module, "attempt" "MiddleAddSubSLT" 2 232, 2 89, S_0x244d2d0; + .timescale -9 -12; +L_0x24cf9e0/d .functor NOT 1, L_0x24cff40, C4<0>, C4<0>, C4<0>; +L_0x24cf9e0 .delay (10000,10000,10000) L_0x24cf9e0/d; +L_0x24d03d0/d .functor NOT 1, L_0x24d0470, C4<0>, C4<0>, C4<0>; +L_0x24d03d0 .delay (10000,10000,10000) L_0x24d03d0/d; +L_0x24d0510/d .functor AND 1, L_0x24d0650, L_0x24d03d0, C4<1>, C4<1>; +L_0x24d0510 .delay (20000,20000,20000) L_0x24d0510/d; +L_0x24d06f0/d .functor XOR 1, L_0x24cfea0, L_0x24d01a0, C4<0>, C4<0>; +L_0x24d06f0 .delay (40000,40000,40000) L_0x24d06f0/d; +L_0x24d07e0/d .functor XOR 1, L_0x24d06f0, L_0x24d11b0, C4<0>, C4<0>; +L_0x24d07e0 .delay (40000,40000,40000) L_0x24d07e0/d; +L_0x24d08d0/d .functor AND 1, L_0x24cfea0, L_0x24d01a0, C4<1>, C4<1>; +L_0x24d08d0 .delay (20000,20000,20000) L_0x24d08d0/d; +L_0x24d0a40/d .functor AND 1, L_0x24d06f0, L_0x24d11b0, C4<1>, C4<1>; +L_0x24d0a40 .delay (20000,20000,20000) L_0x24d0a40/d; +L_0x24d0b30/d .functor OR 1, L_0x24d08d0, L_0x24d0a40, C4<0>, C4<0>; +L_0x24d0b30 .delay (20000,20000,20000) L_0x24d0b30/d; +v0x244dad0_0 .net "A", 0 0, L_0x24cfea0; 1 drivers +v0x244db90_0 .net "AandB", 0 0, L_0x24d08d0; 1 drivers +v0x244dc30_0 .net "AddSubSLTSum", 0 0, L_0x24d07e0; 1 drivers +v0x244dcd0_0 .net "AxorB", 0 0, L_0x24d06f0; 1 drivers +v0x244dd50_0 .net "B", 0 0, L_0x24cff40; 1 drivers +v0x244de00_0 .net "BornB", 0 0, L_0x24d01a0; 1 drivers +v0x244dec0_0 .net "CINandAxorB", 0 0, L_0x24d0a40; 1 drivers +v0x244df40_0 .alias "Command", 2 0, v0x2463430_0; +v0x244dfc0_0 .net *"_s3", 0 0, L_0x24d0470; 1 drivers +v0x244e040_0 .net *"_s5", 0 0, L_0x24d0650; 1 drivers +v0x244e0e0_0 .net "carryin", 0 0, L_0x24d11b0; 1 drivers +v0x244e180_0 .net "carryout", 0 0, L_0x24d0b30; 1 drivers +v0x244e220_0 .net "nB", 0 0, L_0x24cf9e0; 1 drivers +v0x244e2d0_0 .net "nCmd2", 0 0, L_0x24d03d0; 1 drivers +v0x244e3d0_0 .net "subtract", 0 0, L_0x24d0510; 1 drivers +L_0x24d0330 .part C4, 0, 1; +L_0x24d0470 .part C4, 2, 1; +L_0x24d0650 .part C4, 0, 1; +S_0x244d530 .scope module, "mux0" "TwoInMux" 2 105, 2 8, S_0x244d440; + .timescale -9 -12; +L_0x24cfaf0/d .functor NOT 1, L_0x24d0330, C4<0>, C4<0>, C4<0>; +L_0x24cfaf0 .delay (10000,10000,10000) L_0x24cfaf0/d; +L_0x24cfbb0/d .functor AND 1, L_0x24cff40, L_0x24cfaf0, C4<1>, C4<1>; +L_0x24cfbb0 .delay (20000,20000,20000) L_0x24cfbb0/d; +L_0x24d00f0/d .functor AND 1, L_0x24cf9e0, L_0x24d0330, C4<1>, C4<1>; +L_0x24d00f0 .delay (20000,20000,20000) L_0x24d00f0/d; +L_0x24d01a0/d .functor OR 1, L_0x24cfbb0, L_0x24d00f0, C4<0>, C4<0>; +L_0x24d01a0 .delay (20000,20000,20000) L_0x24d01a0/d; +v0x244d620_0 .net "S", 0 0, L_0x24d0330; 1 drivers +v0x244d6c0_0 .alias "in0", 0 0, v0x244dd50_0; +v0x244d760_0 .alias "in1", 0 0, v0x244e220_0; +v0x244d800_0 .net "nS", 0 0, L_0x24cfaf0; 1 drivers +v0x244d8b0_0 .net "out0", 0 0, L_0x24cfbb0; 1 drivers +v0x244d950_0 .net "out1", 0 0, L_0x24d00f0; 1 drivers +v0x244da30_0 .alias "outfinal", 0 0, v0x244de00_0; +S_0x244c130 .scope generate, "addbits[19]" "addbits[19]" 2 230, 2 230, S_0x2426ca0; + .timescale -9 -12; +P_0x244bb48 .param/l "i" 2 230, +C4<010011>; +S_0x244c2a0 .scope module, "attempt" "MiddleAddSubSLT" 2 232, 2 89, S_0x244c130; + .timescale -9 -12; +L_0x24d0070/d .functor NOT 1, L_0x24d13e0, C4<0>, C4<0>, C4<0>; +L_0x24d0070 .delay (10000,10000,10000) L_0x24d0070/d; +L_0x24d1880/d .functor NOT 1, L_0x24d1920, C4<0>, C4<0>, C4<0>; +L_0x24d1880 .delay (10000,10000,10000) L_0x24d1880/d; +L_0x24d19c0/d .functor AND 1, L_0x24d1b00, L_0x24d1880, C4<1>, C4<1>; +L_0x24d19c0 .delay (20000,20000,20000) L_0x24d19c0/d; +L_0x24d1ba0/d .functor XOR 1, L_0x24d1340, L_0x24d1650, C4<0>, C4<0>; +L_0x24d1ba0 .delay (40000,40000,40000) L_0x24d1ba0/d; +L_0x24d1c90/d .functor XOR 1, L_0x24d1ba0, L_0x24d1510, C4<0>, C4<0>; +L_0x24d1c90 .delay (40000,40000,40000) L_0x24d1c90/d; +L_0x24d1d80/d .functor AND 1, L_0x24d1340, L_0x24d1650, C4<1>, C4<1>; +L_0x24d1d80 .delay (20000,20000,20000) L_0x24d1d80/d; +L_0x24d1ef0/d .functor AND 1, L_0x24d1ba0, L_0x24d1510, C4<1>, C4<1>; +L_0x24d1ef0 .delay (20000,20000,20000) L_0x24d1ef0/d; +L_0x24d1fe0/d .functor OR 1, L_0x24d1d80, L_0x24d1ef0, C4<0>, C4<0>; +L_0x24d1fe0 .delay (20000,20000,20000) L_0x24d1fe0/d; +v0x244c930_0 .net "A", 0 0, L_0x24d1340; 1 drivers +v0x244c9f0_0 .net "AandB", 0 0, L_0x24d1d80; 1 drivers +v0x244ca90_0 .net "AddSubSLTSum", 0 0, L_0x24d1c90; 1 drivers +v0x244cb30_0 .net "AxorB", 0 0, L_0x24d1ba0; 1 drivers +v0x244cbb0_0 .net "B", 0 0, L_0x24d13e0; 1 drivers +v0x244cc60_0 .net "BornB", 0 0, L_0x24d1650; 1 drivers +v0x244cd20_0 .net "CINandAxorB", 0 0, L_0x24d1ef0; 1 drivers +v0x244cda0_0 .alias "Command", 2 0, v0x2463430_0; +v0x244ce20_0 .net *"_s3", 0 0, L_0x24d1920; 1 drivers +v0x244cea0_0 .net *"_s5", 0 0, L_0x24d1b00; 1 drivers +v0x244cf40_0 .net "carryin", 0 0, L_0x24d1510; 1 drivers +v0x244cfe0_0 .net "carryout", 0 0, L_0x24d1fe0; 1 drivers +v0x244d080_0 .net "nB", 0 0, L_0x24d0070; 1 drivers +v0x244d130_0 .net "nCmd2", 0 0, L_0x24d1880; 1 drivers +v0x244d230_0 .net "subtract", 0 0, L_0x24d19c0; 1 drivers +L_0x24d17e0 .part C4, 0, 1; +L_0x24d1920 .part C4, 2, 1; +L_0x24d1b00 .part C4, 0, 1; +S_0x244c390 .scope module, "mux0" "TwoInMux" 2 105, 2 8, S_0x244c2a0; + .timescale -9 -12; +L_0x24d0f30/d .functor NOT 1, L_0x24d17e0, C4<0>, C4<0>, C4<0>; +L_0x24d0f30 .delay (10000,10000,10000) L_0x24d0f30/d; +L_0x24d0ff0/d .functor AND 1, L_0x24d13e0, L_0x24d0f30, C4<1>, C4<1>; +L_0x24d0ff0 .delay (20000,20000,20000) L_0x24d0ff0/d; +L_0x24d1100/d .functor AND 1, L_0x24d0070, L_0x24d17e0, C4<1>, C4<1>; +L_0x24d1100 .delay (20000,20000,20000) L_0x24d1100/d; +L_0x24d1650/d .functor OR 1, L_0x24d0ff0, L_0x24d1100, C4<0>, C4<0>; +L_0x24d1650 .delay (20000,20000,20000) L_0x24d1650/d; +v0x244c480_0 .net "S", 0 0, L_0x24d17e0; 1 drivers +v0x244c520_0 .alias "in0", 0 0, v0x244cbb0_0; +v0x244c5c0_0 .alias "in1", 0 0, v0x244d080_0; +v0x244c660_0 .net "nS", 0 0, L_0x24d0f30; 1 drivers +v0x244c710_0 .net "out0", 0 0, L_0x24d0ff0; 1 drivers +v0x244c7b0_0 .net "out1", 0 0, L_0x24d1100; 1 drivers +v0x244c890_0 .alias "outfinal", 0 0, v0x244cc60_0; +S_0x244af90 .scope generate, "addbits[20]" "addbits[20]" 2 230, 2 230, S_0x2426ca0; + .timescale -9 -12; +P_0x244a9a8 .param/l "i" 2 230, +C4<010100>; +S_0x244b100 .scope module, "attempt" "MiddleAddSubSLT" 2 232, 2 89, S_0x244af90; + .timescale -9 -12; +L_0x24d26a0/d .functor NOT 1, L_0x24d2490, C4<0>, C4<0>, C4<0>; +L_0x24d26a0 .delay (10000,10000,10000) L_0x24d26a0/d; +L_0x24d2c50/d .functor NOT 1, L_0x24d2cf0, C4<0>, C4<0>, C4<0>; +L_0x24d2c50 .delay (10000,10000,10000) L_0x24d2c50/d; +L_0x24d2d90/d .functor AND 1, L_0x24d2ed0, L_0x24d2c50, C4<1>, C4<1>; +L_0x24d2d90 .delay (20000,20000,20000) L_0x24d2d90/d; +L_0x24d2f70/d .functor XOR 1, L_0x24d23f0, L_0x24d2a20, C4<0>, C4<0>; +L_0x24d2f70 .delay (40000,40000,40000) L_0x24d2f70/d; +L_0x24d3060/d .functor XOR 1, L_0x24d2f70, L_0x24d25c0, C4<0>, C4<0>; +L_0x24d3060 .delay (40000,40000,40000) L_0x24d3060/d; +L_0x24d3150/d .functor AND 1, L_0x24d23f0, L_0x24d2a20, C4<1>, C4<1>; +L_0x24d3150 .delay (20000,20000,20000) L_0x24d3150/d; +L_0x24d32c0/d .functor AND 1, L_0x24d2f70, L_0x24d25c0, C4<1>, C4<1>; +L_0x24d32c0 .delay (20000,20000,20000) L_0x24d32c0/d; +L_0x24d33b0/d .functor OR 1, L_0x24d3150, L_0x24d32c0, C4<0>, C4<0>; +L_0x24d33b0 .delay (20000,20000,20000) L_0x24d33b0/d; +v0x244b790_0 .net "A", 0 0, L_0x24d23f0; 1 drivers +v0x244b850_0 .net "AandB", 0 0, L_0x24d3150; 1 drivers +v0x244b8f0_0 .net "AddSubSLTSum", 0 0, L_0x24d3060; 1 drivers +v0x244b990_0 .net "AxorB", 0 0, L_0x24d2f70; 1 drivers +v0x244ba10_0 .net "B", 0 0, L_0x24d2490; 1 drivers +v0x244bac0_0 .net "BornB", 0 0, L_0x24d2a20; 1 drivers +v0x244bb80_0 .net "CINandAxorB", 0 0, L_0x24d32c0; 1 drivers +v0x244bc00_0 .alias "Command", 2 0, v0x2463430_0; +v0x244bc80_0 .net *"_s3", 0 0, L_0x24d2cf0; 1 drivers +v0x244bd00_0 .net *"_s5", 0 0, L_0x24d2ed0; 1 drivers +v0x244bda0_0 .net "carryin", 0 0, L_0x24d25c0; 1 drivers +v0x244be40_0 .net "carryout", 0 0, L_0x24d33b0; 1 drivers +v0x244bee0_0 .net "nB", 0 0, L_0x24d26a0; 1 drivers +v0x244bf90_0 .net "nCmd2", 0 0, L_0x24d2c50; 1 drivers +v0x244c090_0 .net "subtract", 0 0, L_0x24d2d90; 1 drivers +L_0x24d2bb0 .part C4, 0, 1; +L_0x24d2cf0 .part C4, 2, 1; +L_0x24d2ed0 .part C4, 0, 1; +S_0x244b1f0 .scope module, "mux0" "TwoInMux" 2 105, 2 8, S_0x244b100; + .timescale -9 -12; +L_0x24d27a0/d .functor NOT 1, L_0x24d2bb0, C4<0>, C4<0>, C4<0>; +L_0x24d27a0 .delay (10000,10000,10000) L_0x24d27a0/d; +L_0x24d2840/d .functor AND 1, L_0x24d2490, L_0x24d27a0, C4<1>, C4<1>; +L_0x24d2840 .delay (20000,20000,20000) L_0x24d2840/d; +L_0x24d2930/d .functor AND 1, L_0x24d26a0, L_0x24d2bb0, C4<1>, C4<1>; +L_0x24d2930 .delay (20000,20000,20000) L_0x24d2930/d; +L_0x24d2a20/d .functor OR 1, L_0x24d2840, L_0x24d2930, C4<0>, C4<0>; +L_0x24d2a20 .delay (20000,20000,20000) L_0x24d2a20/d; +v0x244b2e0_0 .net "S", 0 0, L_0x24d2bb0; 1 drivers +v0x244b380_0 .alias "in0", 0 0, v0x244ba10_0; +v0x244b420_0 .alias "in1", 0 0, v0x244bee0_0; +v0x244b4c0_0 .net "nS", 0 0, L_0x24d27a0; 1 drivers +v0x244b570_0 .net "out0", 0 0, L_0x24d2840; 1 drivers +v0x244b610_0 .net "out1", 0 0, L_0x24d2930; 1 drivers +v0x244b6f0_0 .alias "outfinal", 0 0, v0x244bac0_0; +S_0x2449df0 .scope generate, "addbits[21]" "addbits[21]" 2 230, 2 230, S_0x2426ca0; + .timescale -9 -12; +P_0x2449808 .param/l "i" 2 230, +C4<010101>; +S_0x2449f60 .scope module, "attempt" "MiddleAddSubSLT" 2 232, 2 89, S_0x2449df0; + .timescale -9 -12; +L_0x24d3aa0/d .functor NOT 1, L_0x24d3860, C4<0>, C4<0>, C4<0>; +L_0x24d3aa0 .delay (10000,10000,10000) L_0x24d3aa0/d; +L_0x24d4030/d .functor NOT 1, L_0x24d40f0, C4<0>, C4<0>, C4<0>; +L_0x24d4030 .delay (10000,10000,10000) L_0x24d4030/d; +L_0x24d4190/d .functor AND 1, L_0x24d42d0, L_0x24d4030, C4<1>, C4<1>; +L_0x24d4190 .delay (20000,20000,20000) L_0x24d4190/d; +L_0x24d4370/d .functor XOR 1, L_0x24d37c0, L_0x24d3de0, C4<0>, C4<0>; +L_0x24d4370 .delay (40000,40000,40000) L_0x24d4370/d; +L_0x24d4460/d .functor XOR 1, L_0x24d4370, L_0x24d3990, C4<0>, C4<0>; +L_0x24d4460 .delay (40000,40000,40000) L_0x24d4460/d; +L_0x24d4550/d .functor AND 1, L_0x24d37c0, L_0x24d3de0, C4<1>, C4<1>; +L_0x24d4550 .delay (20000,20000,20000) L_0x24d4550/d; +L_0x24d46c0/d .functor AND 1, L_0x24d4370, L_0x24d3990, C4<1>, C4<1>; +L_0x24d46c0 .delay (20000,20000,20000) L_0x24d46c0/d; +L_0x24d47d0/d .functor OR 1, L_0x24d4550, L_0x24d46c0, C4<0>, C4<0>; +L_0x24d47d0 .delay (20000,20000,20000) L_0x24d47d0/d; +v0x244a5f0_0 .net "A", 0 0, L_0x24d37c0; 1 drivers +v0x244a6b0_0 .net "AandB", 0 0, L_0x24d4550; 1 drivers +v0x244a750_0 .net "AddSubSLTSum", 0 0, L_0x24d4460; 1 drivers +v0x244a7f0_0 .net "AxorB", 0 0, L_0x24d4370; 1 drivers +v0x244a870_0 .net "B", 0 0, L_0x24d3860; 1 drivers +v0x244a920_0 .net "BornB", 0 0, L_0x24d3de0; 1 drivers +v0x244a9e0_0 .net "CINandAxorB", 0 0, L_0x24d46c0; 1 drivers +v0x244aa60_0 .alias "Command", 2 0, v0x2463430_0; +v0x244aae0_0 .net *"_s3", 0 0, L_0x24d40f0; 1 drivers +v0x244ab60_0 .net *"_s5", 0 0, L_0x24d42d0; 1 drivers +v0x244ac00_0 .net "carryin", 0 0, L_0x24d3990; 1 drivers +v0x244aca0_0 .net "carryout", 0 0, L_0x24d47d0; 1 drivers +v0x244ad40_0 .net "nB", 0 0, L_0x24d3aa0; 1 drivers +v0x244adf0_0 .net "nCmd2", 0 0, L_0x24d4030; 1 drivers +v0x244aef0_0 .net "subtract", 0 0, L_0x24d4190; 1 drivers +L_0x24d3f90 .part C4, 0, 1; +L_0x24d40f0 .part C4, 2, 1; +L_0x24d42d0 .part C4, 0, 1; +S_0x244a050 .scope module, "mux0" "TwoInMux" 2 105, 2 8, S_0x2449f60; + .timescale -9 -12; +L_0x24d3ba0/d .functor NOT 1, L_0x24d3f90, C4<0>, C4<0>, C4<0>; +L_0x24d3ba0 .delay (10000,10000,10000) L_0x24d3ba0/d; +L_0x24d3c00/d .functor AND 1, L_0x24d3860, L_0x24d3ba0, C4<1>, C4<1>; +L_0x24d3c00 .delay (20000,20000,20000) L_0x24d3c00/d; +L_0x24d3cf0/d .functor AND 1, L_0x24d3aa0, L_0x24d3f90, C4<1>, C4<1>; +L_0x24d3cf0 .delay (20000,20000,20000) L_0x24d3cf0/d; +L_0x24d3de0/d .functor OR 1, L_0x24d3c00, L_0x24d3cf0, C4<0>, C4<0>; +L_0x24d3de0 .delay (20000,20000,20000) L_0x24d3de0/d; +v0x244a140_0 .net "S", 0 0, L_0x24d3f90; 1 drivers +v0x244a1e0_0 .alias "in0", 0 0, v0x244a870_0; +v0x244a280_0 .alias "in1", 0 0, v0x244ad40_0; +v0x244a320_0 .net "nS", 0 0, L_0x24d3ba0; 1 drivers +v0x244a3d0_0 .net "out0", 0 0, L_0x24d3c00; 1 drivers +v0x244a470_0 .net "out1", 0 0, L_0x24d3cf0; 1 drivers +v0x244a550_0 .alias "outfinal", 0 0, v0x244a920_0; +S_0x2448c50 .scope generate, "addbits[22]" "addbits[22]" 2 230, 2 230, S_0x2426ca0; + .timescale -9 -12; +P_0x2448668 .param/l "i" 2 230, +C4<010110>; +S_0x2448dc0 .scope module, "attempt" "MiddleAddSubSLT" 2 232, 2 89, S_0x2448c50; + .timescale -9 -12; +L_0x24d3a30/d .functor NOT 1, L_0x24d4ca0, C4<0>, C4<0>, C4<0>; +L_0x24d3a30 .delay (10000,10000,10000) L_0x24d3a30/d; +L_0x24d5560/d .functor NOT 1, L_0x24d5620, C4<0>, C4<0>, C4<0>; +L_0x24d5560 .delay (10000,10000,10000) L_0x24d5560/d; +L_0x24d56c0/d .functor AND 1, L_0x24d5800, L_0x24d5560, C4<1>, C4<1>; +L_0x24d56c0 .delay (20000,20000,20000) L_0x24d56c0/d; +L_0x24d58a0/d .functor XOR 1, L_0x24d4c00, L_0x24d52f0, C4<0>, C4<0>; +L_0x24d58a0 .delay (40000,40000,40000) L_0x24d58a0/d; +L_0x24d5990/d .functor XOR 1, L_0x24d58a0, L_0x24d4dd0, C4<0>, C4<0>; +L_0x24d5990 .delay (40000,40000,40000) L_0x24d5990/d; +L_0x24d5a80/d .functor AND 1, L_0x24d4c00, L_0x24d52f0, C4<1>, C4<1>; +L_0x24d5a80 .delay (20000,20000,20000) L_0x24d5a80/d; +L_0x24d5bf0/d .functor AND 1, L_0x24d58a0, L_0x24d4dd0, C4<1>, C4<1>; +L_0x24d5bf0 .delay (20000,20000,20000) L_0x24d5bf0/d; +L_0x24d5ce0/d .functor OR 1, L_0x24d5a80, L_0x24d5bf0, C4<0>, C4<0>; +L_0x24d5ce0 .delay (20000,20000,20000) L_0x24d5ce0/d; +v0x2449450_0 .net "A", 0 0, L_0x24d4c00; 1 drivers +v0x2449510_0 .net "AandB", 0 0, L_0x24d5a80; 1 drivers +v0x24495b0_0 .net "AddSubSLTSum", 0 0, L_0x24d5990; 1 drivers +v0x2449650_0 .net "AxorB", 0 0, L_0x24d58a0; 1 drivers +v0x24496d0_0 .net "B", 0 0, L_0x24d4ca0; 1 drivers +v0x2449780_0 .net "BornB", 0 0, L_0x24d52f0; 1 drivers +v0x2449840_0 .net "CINandAxorB", 0 0, L_0x24d5bf0; 1 drivers +v0x24498c0_0 .alias "Command", 2 0, v0x2463430_0; +v0x2449940_0 .net *"_s3", 0 0, L_0x24d5620; 1 drivers +v0x24499c0_0 .net *"_s5", 0 0, L_0x24d5800; 1 drivers +v0x2449a60_0 .net "carryin", 0 0, L_0x24d4dd0; 1 drivers +v0x2449b00_0 .net "carryout", 0 0, L_0x24d5ce0; 1 drivers +v0x2449ba0_0 .net "nB", 0 0, L_0x24d3a30; 1 drivers +v0x2449c50_0 .net "nCmd2", 0 0, L_0x24d5560; 1 drivers +v0x2449d50_0 .net "subtract", 0 0, L_0x24d56c0; 1 drivers +L_0x24d54c0 .part C4, 0, 1; +L_0x24d5620 .part C4, 2, 1; +L_0x24d5800 .part C4, 0, 1; +S_0x2448eb0 .scope module, "mux0" "TwoInMux" 2 105, 2 8, S_0x2448dc0; + .timescale -9 -12; +L_0x24d5010/d .functor NOT 1, L_0x24d54c0, C4<0>, C4<0>, C4<0>; +L_0x24d5010 .delay (10000,10000,10000) L_0x24d5010/d; +L_0x24d50d0/d .functor AND 1, L_0x24d4ca0, L_0x24d5010, C4<1>, C4<1>; +L_0x24d50d0 .delay (20000,20000,20000) L_0x24d50d0/d; +L_0x24d51e0/d .functor AND 1, L_0x24d3a30, L_0x24d54c0, C4<1>, C4<1>; +L_0x24d51e0 .delay (20000,20000,20000) L_0x24d51e0/d; +L_0x24d52f0/d .functor OR 1, L_0x24d50d0, L_0x24d51e0, C4<0>, C4<0>; +L_0x24d52f0 .delay (20000,20000,20000) L_0x24d52f0/d; +v0x2448fa0_0 .net "S", 0 0, L_0x24d54c0; 1 drivers +v0x2449040_0 .alias "in0", 0 0, v0x24496d0_0; +v0x24490e0_0 .alias "in1", 0 0, v0x2449ba0_0; +v0x2449180_0 .net "nS", 0 0, L_0x24d5010; 1 drivers +v0x2449230_0 .net "out0", 0 0, L_0x24d50d0; 1 drivers +v0x24492d0_0 .net "out1", 0 0, L_0x24d51e0; 1 drivers +v0x24493b0_0 .alias "outfinal", 0 0, v0x2449780_0; +S_0x2447ab0 .scope generate, "addbits[23]" "addbits[23]" 2 230, 2 230, S_0x2426ca0; + .timescale -9 -12; +P_0x24474c8 .param/l "i" 2 230, +C4<010111>; +S_0x2447c20 .scope module, "attempt" "MiddleAddSubSLT" 2 232, 2 89, S_0x2447ab0; + .timescale -9 -12; +L_0x24d4e70/d .functor NOT 1, L_0x24d61b0, C4<0>, C4<0>, C4<0>; +L_0x24d4e70 .delay (10000,10000,10000) L_0x24d4e70/d; +L_0x24d6960/d .functor NOT 1, L_0x24d6a00, C4<0>, C4<0>, C4<0>; +L_0x24d6960 .delay (10000,10000,10000) L_0x24d6960/d; +L_0x24d6aa0/d .functor AND 1, L_0x24d6be0, L_0x24d6960, C4<1>, C4<1>; +L_0x24d6aa0 .delay (20000,20000,20000) L_0x24d6aa0/d; +L_0x24d6c80/d .functor XOR 1, L_0x24d6110, L_0x24d6730, C4<0>, C4<0>; +L_0x24d6c80 .delay (40000,40000,40000) L_0x24d6c80/d; +L_0x24d6d70/d .functor XOR 1, L_0x24d6c80, L_0x24d62e0, C4<0>, C4<0>; +L_0x24d6d70 .delay (40000,40000,40000) L_0x24d6d70/d; +L_0x24d6e60/d .functor AND 1, L_0x24d6110, L_0x24d6730, C4<1>, C4<1>; +L_0x24d6e60 .delay (20000,20000,20000) L_0x24d6e60/d; +L_0x24d6fd0/d .functor AND 1, L_0x24d6c80, L_0x24d62e0, C4<1>, C4<1>; +L_0x24d6fd0 .delay (20000,20000,20000) L_0x24d6fd0/d; +L_0x24d70c0/d .functor OR 1, L_0x24d6e60, L_0x24d6fd0, C4<0>, C4<0>; +L_0x24d70c0 .delay (20000,20000,20000) L_0x24d70c0/d; +v0x24482b0_0 .net "A", 0 0, L_0x24d6110; 1 drivers +v0x2448370_0 .net "AandB", 0 0, L_0x24d6e60; 1 drivers +v0x2448410_0 .net "AddSubSLTSum", 0 0, L_0x24d6d70; 1 drivers +v0x24484b0_0 .net "AxorB", 0 0, L_0x24d6c80; 1 drivers +v0x2448530_0 .net "B", 0 0, L_0x24d61b0; 1 drivers +v0x24485e0_0 .net "BornB", 0 0, L_0x24d6730; 1 drivers +v0x24486a0_0 .net "CINandAxorB", 0 0, L_0x24d6fd0; 1 drivers +v0x2448720_0 .alias "Command", 2 0, v0x2463430_0; +v0x24487a0_0 .net *"_s3", 0 0, L_0x24d6a00; 1 drivers +v0x2448820_0 .net *"_s5", 0 0, L_0x24d6be0; 1 drivers +v0x24488c0_0 .net "carryin", 0 0, L_0x24d62e0; 1 drivers +v0x2448960_0 .net "carryout", 0 0, L_0x24d70c0; 1 drivers +v0x2448a00_0 .net "nB", 0 0, L_0x24d4e70; 1 drivers +v0x2448ab0_0 .net "nCmd2", 0 0, L_0x24d6960; 1 drivers +v0x2448bb0_0 .net "subtract", 0 0, L_0x24d6aa0; 1 drivers +L_0x24d68c0 .part C4, 0, 1; +L_0x24d6a00 .part C4, 2, 1; +L_0x24d6be0 .part C4, 0, 1; +S_0x2447d10 .scope module, "mux0" "TwoInMux" 2 105, 2 8, S_0x2447c20; + .timescale -9 -12; +L_0x24d64f0/d .functor NOT 1, L_0x24d68c0, C4<0>, C4<0>, C4<0>; +L_0x24d64f0 .delay (10000,10000,10000) L_0x24d64f0/d; +L_0x24d6550/d .functor AND 1, L_0x24d61b0, L_0x24d64f0, C4<1>, C4<1>; +L_0x24d6550 .delay (20000,20000,20000) L_0x24d6550/d; +L_0x24d6640/d .functor AND 1, L_0x24d4e70, L_0x24d68c0, C4<1>, C4<1>; +L_0x24d6640 .delay (20000,20000,20000) L_0x24d6640/d; +L_0x24d6730/d .functor OR 1, L_0x24d6550, L_0x24d6640, C4<0>, C4<0>; +L_0x24d6730 .delay (20000,20000,20000) L_0x24d6730/d; +v0x2447e00_0 .net "S", 0 0, L_0x24d68c0; 1 drivers +v0x2447ea0_0 .alias "in0", 0 0, v0x2448530_0; +v0x2447f40_0 .alias "in1", 0 0, v0x2448a00_0; +v0x2447fe0_0 .net "nS", 0 0, L_0x24d64f0; 1 drivers +v0x2448090_0 .net "out0", 0 0, L_0x24d6550; 1 drivers +v0x2448130_0 .net "out1", 0 0, L_0x24d6640; 1 drivers +v0x2448210_0 .alias "outfinal", 0 0, v0x24485e0_0; +S_0x2446910 .scope generate, "addbits[24]" "addbits[24]" 2 230, 2 230, S_0x2426ca0; + .timescale -9 -12; +P_0x2446328 .param/l "i" 2 230, +C4<011000>; +S_0x2446a80 .scope module, "attempt" "MiddleAddSubSLT" 2 232, 2 89, S_0x2446910; + .timescale -9 -12; +L_0x24d6380/d .functor NOT 1, L_0x24d7570, C4<0>, C4<0>, C4<0>; +L_0x24d6380 .delay (10000,10000,10000) L_0x24d6380/d; +L_0x24d7d40/d .functor NOT 1, L_0x24d7de0, C4<0>, C4<0>, C4<0>; +L_0x24d7d40 .delay (10000,10000,10000) L_0x24d7d40/d; +L_0x24d7e80/d .functor AND 1, L_0x24d7fc0, L_0x24d7d40, C4<1>, C4<1>; +L_0x24d7e80 .delay (20000,20000,20000) L_0x24d7e80/d; +L_0x24d8060/d .functor XOR 1, L_0x24d74d0, L_0x24d7b10, C4<0>, C4<0>; +L_0x24d8060 .delay (40000,40000,40000) L_0x24d8060/d; +L_0x24d8150/d .functor XOR 1, L_0x24d8060, L_0x24d76a0, C4<0>, C4<0>; +L_0x24d8150 .delay (40000,40000,40000) L_0x24d8150/d; +L_0x24d8240/d .functor AND 1, L_0x24d74d0, L_0x24d7b10, C4<1>, C4<1>; +L_0x24d8240 .delay (20000,20000,20000) L_0x24d8240/d; +L_0x24d83e0/d .functor AND 1, L_0x24d8060, L_0x24d76a0, C4<1>, C4<1>; +L_0x24d83e0 .delay (20000,20000,20000) L_0x24d83e0/d; +L_0x24d84f0/d .functor OR 1, L_0x24d8240, L_0x24d83e0, C4<0>, C4<0>; +L_0x24d84f0 .delay (20000,20000,20000) L_0x24d84f0/d; +v0x2447110_0 .net "A", 0 0, L_0x24d74d0; 1 drivers +v0x24471d0_0 .net "AandB", 0 0, L_0x24d8240; 1 drivers +v0x2447270_0 .net "AddSubSLTSum", 0 0, L_0x24d8150; 1 drivers +v0x2447310_0 .net "AxorB", 0 0, L_0x24d8060; 1 drivers +v0x2447390_0 .net "B", 0 0, L_0x24d7570; 1 drivers +v0x2447440_0 .net "BornB", 0 0, L_0x24d7b10; 1 drivers +v0x2447500_0 .net "CINandAxorB", 0 0, L_0x24d83e0; 1 drivers +v0x2447580_0 .alias "Command", 2 0, v0x2463430_0; +v0x2447600_0 .net *"_s3", 0 0, L_0x24d7de0; 1 drivers +v0x2447680_0 .net *"_s5", 0 0, L_0x24d7fc0; 1 drivers +v0x2447720_0 .net "carryin", 0 0, L_0x24d76a0; 1 drivers +v0x24477c0_0 .net "carryout", 0 0, L_0x24d84f0; 1 drivers +v0x2447860_0 .net "nB", 0 0, L_0x24d6380; 1 drivers +v0x2447910_0 .net "nCmd2", 0 0, L_0x24d7d40; 1 drivers +v0x2447a10_0 .net "subtract", 0 0, L_0x24d7e80; 1 drivers +L_0x24d7ca0 .part C4, 0, 1; +L_0x24d7de0 .part C4, 2, 1; +L_0x24d7fc0 .part C4, 0, 1; +S_0x2446b70 .scope module, "mux0" "TwoInMux" 2 105, 2 8, S_0x2446a80; + .timescale -9 -12; +L_0x24d7890/d .functor NOT 1, L_0x24d7ca0, C4<0>, C4<0>, C4<0>; +L_0x24d7890 .delay (10000,10000,10000) L_0x24d7890/d; +L_0x24d7930/d .functor AND 1, L_0x24d7570, L_0x24d7890, C4<1>, C4<1>; +L_0x24d7930 .delay (20000,20000,20000) L_0x24d7930/d; +L_0x24d7a20/d .functor AND 1, L_0x24d6380, L_0x24d7ca0, C4<1>, C4<1>; +L_0x24d7a20 .delay (20000,20000,20000) L_0x24d7a20/d; +L_0x24d7b10/d .functor OR 1, L_0x24d7930, L_0x24d7a20, C4<0>, C4<0>; +L_0x24d7b10 .delay (20000,20000,20000) L_0x24d7b10/d; +v0x2446c60_0 .net "S", 0 0, L_0x24d7ca0; 1 drivers +v0x2446d00_0 .alias "in0", 0 0, v0x2447390_0; +v0x2446da0_0 .alias "in1", 0 0, v0x2447860_0; +v0x2446e40_0 .net "nS", 0 0, L_0x24d7890; 1 drivers +v0x2446ef0_0 .net "out0", 0 0, L_0x24d7930; 1 drivers +v0x2446f90_0 .net "out1", 0 0, L_0x24d7a20; 1 drivers +v0x2447070_0 .alias "outfinal", 0 0, v0x2447440_0; +S_0x2445770 .scope generate, "addbits[25]" "addbits[25]" 2 230, 2 230, S_0x2426ca0; + .timescale -9 -12; +P_0x2445188 .param/l "i" 2 230, +C4<011001>; +S_0x24458e0 .scope module, "attempt" "MiddleAddSubSLT" 2 232, 2 89, S_0x2445770; + .timescale -9 -12; +L_0x24d7740/d .functor NOT 1, L_0x24d89c0, C4<0>, C4<0>, C4<0>; +L_0x24d7740 .delay (10000,10000,10000) L_0x24d7740/d; +L_0x24d91e0/d .functor NOT 1, L_0x24d92a0, C4<0>, C4<0>, C4<0>; +L_0x24d91e0 .delay (10000,10000,10000) L_0x24d91e0/d; +L_0x24d9340/d .functor AND 1, L_0x24d9480, L_0x24d91e0, C4<1>, C4<1>; +L_0x24d9340 .delay (20000,20000,20000) L_0x24d9340/d; +L_0x24d9520/d .functor XOR 1, L_0x24d8920, L_0x24d8f90, C4<0>, C4<0>; +L_0x24d9520 .delay (40000,40000,40000) L_0x24d9520/d; +L_0x24d9610/d .functor XOR 1, L_0x24d9520, L_0x24d8af0, C4<0>, C4<0>; +L_0x24d9610 .delay (40000,40000,40000) L_0x24d9610/d; +L_0x24d9730/d .functor AND 1, L_0x24d8920, L_0x24d8f90, C4<1>, C4<1>; +L_0x24d9730 .delay (20000,20000,20000) L_0x24d9730/d; +L_0x24d98d0/d .functor AND 1, L_0x24d9520, L_0x24d8af0, C4<1>, C4<1>; +L_0x24d98d0 .delay (20000,20000,20000) L_0x24d98d0/d; +L_0x24d99e0/d .functor OR 1, L_0x24d9730, L_0x24d98d0, C4<0>, C4<0>; +L_0x24d99e0 .delay (20000,20000,20000) L_0x24d99e0/d; +v0x2445f70_0 .net "A", 0 0, L_0x24d8920; 1 drivers +v0x2446030_0 .net "AandB", 0 0, L_0x24d9730; 1 drivers +v0x24460d0_0 .net "AddSubSLTSum", 0 0, L_0x24d9610; 1 drivers +v0x2446170_0 .net "AxorB", 0 0, L_0x24d9520; 1 drivers +v0x24461f0_0 .net "B", 0 0, L_0x24d89c0; 1 drivers +v0x24462a0_0 .net "BornB", 0 0, L_0x24d8f90; 1 drivers +v0x2446360_0 .net "CINandAxorB", 0 0, L_0x24d98d0; 1 drivers +v0x24463e0_0 .alias "Command", 2 0, v0x2463430_0; +v0x2446460_0 .net *"_s3", 0 0, L_0x24d92a0; 1 drivers +v0x24464e0_0 .net *"_s5", 0 0, L_0x24d9480; 1 drivers +v0x2446580_0 .net "carryin", 0 0, L_0x24d8af0; 1 drivers +v0x2446620_0 .net "carryout", 0 0, L_0x24d99e0; 1 drivers +v0x24466c0_0 .net "nB", 0 0, L_0x24d7740; 1 drivers +v0x2446770_0 .net "nCmd2", 0 0, L_0x24d91e0; 1 drivers +v0x2446870_0 .net "subtract", 0 0, L_0x24d9340; 1 drivers +L_0x24d9140 .part C4, 0, 1; +L_0x24d92a0 .part C4, 2, 1; +L_0x24d9480 .part C4, 0, 1; +S_0x24459d0 .scope module, "mux0" "TwoInMux" 2 105, 2 8, S_0x24458e0; + .timescale -9 -12; +L_0x24d8d10/d .functor NOT 1, L_0x24d9140, C4<0>, C4<0>, C4<0>; +L_0x24d8d10 .delay (10000,10000,10000) L_0x24d8d10/d; +L_0x24d8db0/d .functor AND 1, L_0x24d89c0, L_0x24d8d10, C4<1>, C4<1>; +L_0x24d8db0 .delay (20000,20000,20000) L_0x24d8db0/d; +L_0x24d8ea0/d .functor AND 1, L_0x24d7740, L_0x24d9140, C4<1>, C4<1>; +L_0x24d8ea0 .delay (20000,20000,20000) L_0x24d8ea0/d; +L_0x24d8f90/d .functor OR 1, L_0x24d8db0, L_0x24d8ea0, C4<0>, C4<0>; +L_0x24d8f90 .delay (20000,20000,20000) L_0x24d8f90/d; +v0x2445ac0_0 .net "S", 0 0, L_0x24d9140; 1 drivers +v0x2445b60_0 .alias "in0", 0 0, v0x24461f0_0; +v0x2445c00_0 .alias "in1", 0 0, v0x24466c0_0; +v0x2445ca0_0 .net "nS", 0 0, L_0x24d8d10; 1 drivers +v0x2445d50_0 .net "out0", 0 0, L_0x24d8db0; 1 drivers +v0x2445df0_0 .net "out1", 0 0, L_0x24d8ea0; 1 drivers +v0x2445ed0_0 .alias "outfinal", 0 0, v0x24462a0_0; +S_0x24445d0 .scope generate, "addbits[26]" "addbits[26]" 2 230, 2 230, S_0x2426ca0; + .timescale -9 -12; +P_0x2443fe8 .param/l "i" 2 230, +C4<011010>; +S_0x2444740 .scope module, "attempt" "MiddleAddSubSLT" 2 232, 2 89, S_0x24445d0; + .timescale -9 -12; +L_0x24d8b90/d .functor NOT 1, L_0x24d9eb0, C4<0>, C4<0>, C4<0>; +L_0x24d8b90 .delay (10000,10000,10000) L_0x24d8b90/d; +L_0x24da6c0/d .functor NOT 1, L_0x24da780, C4<0>, C4<0>, C4<0>; +L_0x24da6c0 .delay (10000,10000,10000) L_0x24da6c0/d; +L_0x24da820/d .functor AND 1, L_0x24da960, L_0x24da6c0, C4<1>, C4<1>; +L_0x24da820 .delay (20000,20000,20000) L_0x24da820/d; +L_0x24daa00/d .functor XOR 1, L_0x24d9e10, L_0x24da450, C4<0>, C4<0>; +L_0x24daa00 .delay (40000,40000,40000) L_0x24daa00/d; +L_0x24daaf0/d .functor XOR 1, L_0x24daa00, L_0x24d9fe0, C4<0>, C4<0>; +L_0x24daaf0 .delay (40000,40000,40000) L_0x24daaf0/d; +L_0x24dac10/d .functor AND 1, L_0x24d9e10, L_0x24da450, C4<1>, C4<1>; +L_0x24dac10 .delay (20000,20000,20000) L_0x24dac10/d; +L_0x24dadb0/d .functor AND 1, L_0x24daa00, L_0x24d9fe0, C4<1>, C4<1>; +L_0x24dadb0 .delay (20000,20000,20000) L_0x24dadb0/d; +L_0x24daec0/d .functor OR 1, L_0x24dac10, L_0x24dadb0, C4<0>, C4<0>; +L_0x24daec0 .delay (20000,20000,20000) L_0x24daec0/d; +v0x2444dd0_0 .net "A", 0 0, L_0x24d9e10; 1 drivers +v0x2444e90_0 .net "AandB", 0 0, L_0x24dac10; 1 drivers +v0x2444f30_0 .net "AddSubSLTSum", 0 0, L_0x24daaf0; 1 drivers +v0x2444fd0_0 .net "AxorB", 0 0, L_0x24daa00; 1 drivers +v0x2445050_0 .net "B", 0 0, L_0x24d9eb0; 1 drivers +v0x2445100_0 .net "BornB", 0 0, L_0x24da450; 1 drivers +v0x24451c0_0 .net "CINandAxorB", 0 0, L_0x24dadb0; 1 drivers +v0x2445240_0 .alias "Command", 2 0, v0x2463430_0; +v0x24452c0_0 .net *"_s3", 0 0, L_0x24da780; 1 drivers +v0x2445340_0 .net *"_s5", 0 0, L_0x24da960; 1 drivers +v0x24453e0_0 .net "carryin", 0 0, L_0x24d9fe0; 1 drivers +v0x2445480_0 .net "carryout", 0 0, L_0x24daec0; 1 drivers +v0x2445520_0 .net "nB", 0 0, L_0x24d8b90; 1 drivers +v0x24455d0_0 .net "nCmd2", 0 0, L_0x24da6c0; 1 drivers +v0x24456d0_0 .net "subtract", 0 0, L_0x24da820; 1 drivers +L_0x24da620 .part C4, 0, 1; +L_0x24da780 .part C4, 2, 1; +L_0x24da960 .part C4, 0, 1; +S_0x2444830 .scope module, "mux0" "TwoInMux" 2 105, 2 8, S_0x2444740; + .timescale -9 -12; +L_0x24d8c60/d .functor NOT 1, L_0x24da620, C4<0>, C4<0>, C4<0>; +L_0x24d8c60 .delay (10000,10000,10000) L_0x24d8c60/d; +L_0x24da270/d .functor AND 1, L_0x24d9eb0, L_0x24d8c60, C4<1>, C4<1>; +L_0x24da270 .delay (20000,20000,20000) L_0x24da270/d; +L_0x24da360/d .functor AND 1, L_0x24d8b90, L_0x24da620, C4<1>, C4<1>; +L_0x24da360 .delay (20000,20000,20000) L_0x24da360/d; +L_0x24da450/d .functor OR 1, L_0x24da270, L_0x24da360, C4<0>, C4<0>; +L_0x24da450 .delay (20000,20000,20000) L_0x24da450/d; +v0x2444920_0 .net "S", 0 0, L_0x24da620; 1 drivers +v0x24449c0_0 .alias "in0", 0 0, v0x2445050_0; +v0x2444a60_0 .alias "in1", 0 0, v0x2445520_0; +v0x2444b00_0 .net "nS", 0 0, L_0x24d8c60; 1 drivers +v0x2444bb0_0 .net "out0", 0 0, L_0x24da270; 1 drivers +v0x2444c50_0 .net "out1", 0 0, L_0x24da360; 1 drivers +v0x2444d30_0 .alias "outfinal", 0 0, v0x2445100_0; +S_0x2443430 .scope generate, "addbits[27]" "addbits[27]" 2 230, 2 230, S_0x2426ca0; + .timescale -9 -12; +P_0x2442e48 .param/l "i" 2 230, +C4<011011>; +S_0x24435a0 .scope module, "attempt" "MiddleAddSubSLT" 2 232, 2 89, S_0x2443430; + .timescale -9 -12; +L_0x24da080/d .functor NOT 1, L_0x24db390, C4<0>, C4<0>, C4<0>; +L_0x24da080 .delay (10000,10000,10000) L_0x24da080/d; +L_0x24dbba0/d .functor NOT 1, L_0x24dbc60, C4<0>, C4<0>, C4<0>; +L_0x24dbba0 .delay (10000,10000,10000) L_0x24dbba0/d; +L_0x24dbd00/d .functor AND 1, L_0x24dbe40, L_0x24dbba0, C4<1>, C4<1>; +L_0x24dbd00 .delay (20000,20000,20000) L_0x24dbd00/d; +L_0x24dbee0/d .functor XOR 1, L_0x24db2f0, L_0x24db930, C4<0>, C4<0>; +L_0x24dbee0 .delay (40000,40000,40000) L_0x24dbee0/d; +L_0x24dbfd0/d .functor XOR 1, L_0x24dbee0, L_0x24db4c0, C4<0>, C4<0>; +L_0x24dbfd0 .delay (40000,40000,40000) L_0x24dbfd0/d; +L_0x24dc0f0/d .functor AND 1, L_0x24db2f0, L_0x24db930, C4<1>, C4<1>; +L_0x24dc0f0 .delay (20000,20000,20000) L_0x24dc0f0/d; +L_0x24dc290/d .functor AND 1, L_0x24dbee0, L_0x24db4c0, C4<1>, C4<1>; +L_0x24dc290 .delay (20000,20000,20000) L_0x24dc290/d; +L_0x24dc3a0/d .functor OR 1, L_0x24dc0f0, L_0x24dc290, C4<0>, C4<0>; +L_0x24dc3a0 .delay (20000,20000,20000) L_0x24dc3a0/d; +v0x2443c30_0 .net "A", 0 0, L_0x24db2f0; 1 drivers +v0x2443cf0_0 .net "AandB", 0 0, L_0x24dc0f0; 1 drivers +v0x2443d90_0 .net "AddSubSLTSum", 0 0, L_0x24dbfd0; 1 drivers +v0x2443e30_0 .net "AxorB", 0 0, L_0x24dbee0; 1 drivers +v0x2443eb0_0 .net "B", 0 0, L_0x24db390; 1 drivers +v0x2443f60_0 .net "BornB", 0 0, L_0x24db930; 1 drivers +v0x2444020_0 .net "CINandAxorB", 0 0, L_0x24dc290; 1 drivers +v0x24440a0_0 .alias "Command", 2 0, v0x2463430_0; +v0x2444120_0 .net *"_s3", 0 0, L_0x24dbc60; 1 drivers +v0x24441a0_0 .net *"_s5", 0 0, L_0x24dbe40; 1 drivers +v0x2444240_0 .net "carryin", 0 0, L_0x24db4c0; 1 drivers +v0x24442e0_0 .net "carryout", 0 0, L_0x24dc3a0; 1 drivers +v0x2444380_0 .net "nB", 0 0, L_0x24da080; 1 drivers +v0x2444430_0 .net "nCmd2", 0 0, L_0x24dbba0; 1 drivers +v0x2444530_0 .net "subtract", 0 0, L_0x24dbd00; 1 drivers +L_0x24dbb00 .part C4, 0, 1; +L_0x24dbc60 .part C4, 2, 1; +L_0x24dbe40 .part C4, 0, 1; +S_0x2443690 .scope module, "mux0" "TwoInMux" 2 105, 2 8, S_0x24435a0; + .timescale -9 -12; +L_0x24db6f0/d .functor NOT 1, L_0x24dbb00, C4<0>, C4<0>, C4<0>; +L_0x24db6f0 .delay (10000,10000,10000) L_0x24db6f0/d; +L_0x24db750/d .functor AND 1, L_0x24db390, L_0x24db6f0, C4<1>, C4<1>; +L_0x24db750 .delay (20000,20000,20000) L_0x24db750/d; +L_0x24db840/d .functor AND 1, L_0x24da080, L_0x24dbb00, C4<1>, C4<1>; +L_0x24db840 .delay (20000,20000,20000) L_0x24db840/d; +L_0x24db930/d .functor OR 1, L_0x24db750, L_0x24db840, C4<0>, C4<0>; +L_0x24db930 .delay (20000,20000,20000) L_0x24db930/d; +v0x2443780_0 .net "S", 0 0, L_0x24dbb00; 1 drivers +v0x2443820_0 .alias "in0", 0 0, v0x2443eb0_0; +v0x24438c0_0 .alias "in1", 0 0, v0x2444380_0; +v0x2443960_0 .net "nS", 0 0, L_0x24db6f0; 1 drivers +v0x2443a10_0 .net "out0", 0 0, L_0x24db750; 1 drivers +v0x2443ab0_0 .net "out1", 0 0, L_0x24db840; 1 drivers +v0x2443b90_0 .alias "outfinal", 0 0, v0x2443f60_0; +S_0x2442290 .scope generate, "addbits[28]" "addbits[28]" 2 230, 2 230, S_0x2426ca0; + .timescale -9 -12; +P_0x2441ca8 .param/l "i" 2 230, +C4<011100>; +S_0x2442400 .scope module, "attempt" "MiddleAddSubSLT" 2 232, 2 89, S_0x2442290; + .timescale -9 -12; +L_0x24db560/d .functor NOT 1, L_0x24dc870, C4<0>, C4<0>, C4<0>; +L_0x24db560 .delay (10000,10000,10000) L_0x24db560/d; +L_0x24dd0b0/d .functor NOT 1, L_0x24dd150, C4<0>, C4<0>, C4<0>; +L_0x24dd0b0 .delay (10000,10000,10000) L_0x24dd0b0/d; +L_0x24dd1f0/d .functor AND 1, L_0x24dd330, L_0x24dd0b0, C4<1>, C4<1>; +L_0x24dd1f0 .delay (20000,20000,20000) L_0x24dd1f0/d; +L_0x24dd3d0/d .functor XOR 1, L_0x24dc7d0, L_0x24dce80, C4<0>, C4<0>; +L_0x24dd3d0 .delay (40000,40000,40000) L_0x24dd3d0/d; +L_0x24dd4f0/d .functor XOR 1, L_0x24dd3d0, L_0x24dc9a0, C4<0>, C4<0>; +L_0x24dd4f0 .delay (40000,40000,40000) L_0x24dd4f0/d; +L_0x24dd610/d .functor AND 1, L_0x24dc7d0, L_0x24dce80, C4<1>, C4<1>; +L_0x24dd610 .delay (20000,20000,20000) L_0x24dd610/d; +L_0x24dd7b0/d .functor AND 1, L_0x24dd3d0, L_0x24dc9a0, C4<1>, C4<1>; +L_0x24dd7b0 .delay (20000,20000,20000) L_0x24dd7b0/d; +L_0x24dd8a0/d .functor OR 1, L_0x24dd610, L_0x24dd7b0, C4<0>, C4<0>; +L_0x24dd8a0 .delay (20000,20000,20000) L_0x24dd8a0/d; +v0x2442a90_0 .net "A", 0 0, L_0x24dc7d0; 1 drivers +v0x2442b50_0 .net "AandB", 0 0, L_0x24dd610; 1 drivers +v0x2442bf0_0 .net "AddSubSLTSum", 0 0, L_0x24dd4f0; 1 drivers +v0x2442c90_0 .net "AxorB", 0 0, L_0x24dd3d0; 1 drivers +v0x2442d10_0 .net "B", 0 0, L_0x24dc870; 1 drivers +v0x2442dc0_0 .net "BornB", 0 0, L_0x24dce80; 1 drivers +v0x2442e80_0 .net "CINandAxorB", 0 0, L_0x24dd7b0; 1 drivers +v0x2442f00_0 .alias "Command", 2 0, v0x2463430_0; +v0x2442f80_0 .net *"_s3", 0 0, L_0x24dd150; 1 drivers +v0x2443000_0 .net *"_s5", 0 0, L_0x24dd330; 1 drivers +v0x24430a0_0 .net "carryin", 0 0, L_0x24dc9a0; 1 drivers +v0x2443140_0 .net "carryout", 0 0, L_0x24dd8a0; 1 drivers +v0x24431e0_0 .net "nB", 0 0, L_0x24db560; 1 drivers +v0x2443290_0 .net "nCmd2", 0 0, L_0x24dd0b0; 1 drivers +v0x2443390_0 .net "subtract", 0 0, L_0x24dd1f0; 1 drivers +L_0x24dd010 .part C4, 0, 1; +L_0x24dd150 .part C4, 2, 1; +L_0x24dd330 .part C4, 0, 1; +S_0x24424f0 .scope module, "mux0" "TwoInMux" 2 105, 2 8, S_0x2442400; + .timescale -9 -12; +L_0x24dcc00/d .functor NOT 1, L_0x24dd010, C4<0>, C4<0>, C4<0>; +L_0x24dcc00 .delay (10000,10000,10000) L_0x24dcc00/d; +L_0x24dcca0/d .functor AND 1, L_0x24dc870, L_0x24dcc00, C4<1>, C4<1>; +L_0x24dcca0 .delay (20000,20000,20000) L_0x24dcca0/d; +L_0x24dcd90/d .functor AND 1, L_0x24db560, L_0x24dd010, C4<1>, C4<1>; +L_0x24dcd90 .delay (20000,20000,20000) L_0x24dcd90/d; +L_0x24dce80/d .functor OR 1, L_0x24dcca0, L_0x24dcd90, C4<0>, C4<0>; +L_0x24dce80 .delay (20000,20000,20000) L_0x24dce80/d; +v0x24425e0_0 .net "S", 0 0, L_0x24dd010; 1 drivers +v0x2442680_0 .alias "in0", 0 0, v0x2442d10_0; +v0x2442720_0 .alias "in1", 0 0, v0x24431e0_0; +v0x24427c0_0 .net "nS", 0 0, L_0x24dcc00; 1 drivers +v0x2442870_0 .net "out0", 0 0, L_0x24dcca0; 1 drivers +v0x2442910_0 .net "out1", 0 0, L_0x24dcd90; 1 drivers +v0x24429f0_0 .alias "outfinal", 0 0, v0x2442dc0_0; +S_0x24410f0 .scope generate, "addbits[29]" "addbits[29]" 2 230, 2 230, S_0x2426ca0; + .timescale -9 -12; +P_0x2440b08 .param/l "i" 2 230, +C4<011101>; +S_0x2441260 .scope module, "attempt" "MiddleAddSubSLT" 2 232, 2 89, S_0x24410f0; + .timescale -9 -12; +L_0x24dca40/d .functor NOT 1, L_0x24ca3d0, C4<0>, C4<0>, C4<0>; +L_0x24dca40 .delay (10000,10000,10000) L_0x24dca40/d; +L_0x24de580/d .functor NOT 1, L_0x24de640, C4<0>, C4<0>, C4<0>; +L_0x24de580 .delay (10000,10000,10000) L_0x24de580/d; +L_0x24de6e0/d .functor AND 1, L_0x24de820, L_0x24de580, C4<1>, C4<1>; +L_0x24de6e0 .delay (20000,20000,20000) L_0x24de6e0/d; +L_0x24de8c0/d .functor XOR 1, L_0x24ddcd0, L_0x24de350, C4<0>, C4<0>; +L_0x24de8c0 .delay (40000,40000,40000) L_0x24de8c0/d; +L_0x24de9e0/d .functor XOR 1, L_0x24de8c0, L_0x24ca500, C4<0>, C4<0>; +L_0x24de9e0 .delay (40000,40000,40000) L_0x24de9e0/d; +L_0x24deb00/d .functor AND 1, L_0x24ddcd0, L_0x24de350, C4<1>, C4<1>; +L_0x24deb00 .delay (20000,20000,20000) L_0x24deb00/d; +L_0x24deca0/d .functor AND 1, L_0x24de8c0, L_0x24ca500, C4<1>, C4<1>; +L_0x24deca0 .delay (20000,20000,20000) L_0x24deca0/d; +L_0x24ded90/d .functor OR 1, L_0x24deb00, L_0x24deca0, C4<0>, C4<0>; +L_0x24ded90 .delay (20000,20000,20000) L_0x24ded90/d; +v0x24418f0_0 .net "A", 0 0, L_0x24ddcd0; 1 drivers +v0x24419b0_0 .net "AandB", 0 0, L_0x24deb00; 1 drivers +v0x2441a50_0 .net "AddSubSLTSum", 0 0, L_0x24de9e0; 1 drivers +v0x2441af0_0 .net "AxorB", 0 0, L_0x24de8c0; 1 drivers +v0x2441b70_0 .net "B", 0 0, L_0x24ca3d0; 1 drivers +v0x2441c20_0 .net "BornB", 0 0, L_0x24de350; 1 drivers +v0x2441ce0_0 .net "CINandAxorB", 0 0, L_0x24deca0; 1 drivers +v0x2441d60_0 .alias "Command", 2 0, v0x2463430_0; +v0x2441de0_0 .net *"_s3", 0 0, L_0x24de640; 1 drivers +v0x2441e60_0 .net *"_s5", 0 0, L_0x24de820; 1 drivers +v0x2441f00_0 .net "carryin", 0 0, L_0x24ca500; 1 drivers +v0x2441fa0_0 .net "carryout", 0 0, L_0x24ded90; 1 drivers +v0x2442040_0 .net "nB", 0 0, L_0x24dca40; 1 drivers +v0x24420f0_0 .net "nCmd2", 0 0, L_0x24de580; 1 drivers +v0x24421f0_0 .net "subtract", 0 0, L_0x24de6e0; 1 drivers +L_0x24de4e0 .part C4, 0, 1; +L_0x24de640 .part C4, 2, 1; +L_0x24de820 .part C4, 0, 1; +S_0x2441350 .scope module, "mux0" "TwoInMux" 2 105, 2 8, S_0x2441260; + .timescale -9 -12; +L_0x24dcba0/d .functor NOT 1, L_0x24de4e0, C4<0>, C4<0>, C4<0>; +L_0x24dcba0 .delay (10000,10000,10000) L_0x24dcba0/d; +L_0x24de170/d .functor AND 1, L_0x24ca3d0, L_0x24dcba0, C4<1>, C4<1>; +L_0x24de170 .delay (20000,20000,20000) L_0x24de170/d; +L_0x24de260/d .functor AND 1, L_0x24dca40, L_0x24de4e0, C4<1>, C4<1>; +L_0x24de260 .delay (20000,20000,20000) L_0x24de260/d; +L_0x24de350/d .functor OR 1, L_0x24de170, L_0x24de260, C4<0>, C4<0>; +L_0x24de350 .delay (20000,20000,20000) L_0x24de350/d; +v0x2441440_0 .net "S", 0 0, L_0x24de4e0; 1 drivers +v0x24414e0_0 .alias "in0", 0 0, v0x2441b70_0; +v0x2441580_0 .alias "in1", 0 0, v0x2442040_0; +v0x2441620_0 .net "nS", 0 0, L_0x24dcba0; 1 drivers +v0x24416d0_0 .net "out0", 0 0, L_0x24de170; 1 drivers +v0x2441770_0 .net "out1", 0 0, L_0x24de260; 1 drivers +v0x2441850_0 .alias "outfinal", 0 0, v0x2441c20_0; +S_0x243ff50 .scope generate, "addbits[30]" "addbits[30]" 2 230, 2 230, S_0x2426ca0; + .timescale -9 -12; +P_0x243f848 .param/l "i" 2 230, +C4<011110>; +S_0x24400c0 .scope module, "attempt" "MiddleAddSubSLT" 2 232, 2 89, S_0x243ff50; + .timescale -9 -12; +L_0x24df4e0/d .functor NOT 1, L_0x24dfbd0, C4<0>, C4<0>, C4<0>; +L_0x24df4e0 .delay (10000,10000,10000) L_0x24df4e0/d; +L_0x24de070/d .functor NOT 1, L_0x24dffc0, C4<0>, C4<0>, C4<0>; +L_0x24de070 .delay (10000,10000,10000) L_0x24de070/d; +L_0x24e0060/d .functor AND 1, L_0x24e01a0, L_0x24de070, C4<1>, C4<1>; +L_0x24e0060 .delay (20000,20000,20000) L_0x24e0060/d; +L_0x24e0240/d .functor XOR 1, L_0x24dfb30, L_0x24dde00, C4<0>, C4<0>; +L_0x24e0240 .delay (40000,40000,40000) L_0x24e0240/d; +L_0x24e0330/d .functor XOR 1, L_0x24e0240, L_0x24dfd00, C4<0>, C4<0>; +L_0x24e0330 .delay (40000,40000,40000) L_0x24e0330/d; +L_0x24e0420/d .functor AND 1, L_0x24dfb30, L_0x24dde00, C4<1>, C4<1>; +L_0x24e0420 .delay (20000,20000,20000) L_0x24e0420/d; +L_0x24e0590/d .functor AND 1, L_0x24e0240, L_0x24dfd00, C4<1>, C4<1>; +L_0x24e0590 .delay (20000,20000,20000) L_0x24e0590/d; +L_0x24e0680/d .functor OR 1, L_0x24e0420, L_0x24e0590, C4<0>, C4<0>; +L_0x24e0680 .delay (20000,20000,20000) L_0x24e0680/d; +v0x2440750_0 .net "A", 0 0, L_0x24dfb30; 1 drivers +v0x2440810_0 .net "AandB", 0 0, L_0x24e0420; 1 drivers +v0x24408b0_0 .net "AddSubSLTSum", 0 0, L_0x24e0330; 1 drivers +v0x2440950_0 .net "AxorB", 0 0, L_0x24e0240; 1 drivers +v0x24409d0_0 .net "B", 0 0, L_0x24dfbd0; 1 drivers +v0x2440a80_0 .net "BornB", 0 0, L_0x24dde00; 1 drivers +v0x2440b40_0 .net "CINandAxorB", 0 0, L_0x24e0590; 1 drivers +v0x2440bc0_0 .alias "Command", 2 0, v0x2463430_0; +v0x2440c40_0 .net *"_s3", 0 0, L_0x24dffc0; 1 drivers +v0x2440cc0_0 .net *"_s5", 0 0, L_0x24e01a0; 1 drivers +v0x2440d60_0 .net "carryin", 0 0, L_0x24dfd00; 1 drivers +v0x2440e00_0 .net "carryout", 0 0, L_0x24e0680; 1 drivers +v0x2440ea0_0 .net "nB", 0 0, L_0x24df4e0; 1 drivers +v0x2440f50_0 .net "nCmd2", 0 0, L_0x24de070; 1 drivers +v0x2441050_0 .net "subtract", 0 0, L_0x24e0060; 1 drivers +L_0x24ddfd0 .part C4, 0, 1; +L_0x24dffc0 .part C4, 2, 1; +L_0x24e01a0 .part C4, 0, 1; +S_0x24401b0 .scope module, "mux0" "TwoInMux" 2 105, 2 8, S_0x24400c0; + .timescale -9 -12; +L_0x24ca170/d .functor NOT 1, L_0x24ddfd0, C4<0>, C4<0>, C4<0>; +L_0x24ca170 .delay (10000,10000,10000) L_0x24ca170/d; +L_0x24ca1f0/d .functor AND 1, L_0x24dfbd0, L_0x24ca170, C4<1>, C4<1>; +L_0x24ca1f0 .delay (20000,20000,20000) L_0x24ca1f0/d; +L_0x24ca300/d .functor AND 1, L_0x24df4e0, L_0x24ddfd0, C4<1>, C4<1>; +L_0x24ca300 .delay (20000,20000,20000) L_0x24ca300/d; +L_0x24dde00/d .functor OR 1, L_0x24ca1f0, L_0x24ca300, C4<0>, C4<0>; +L_0x24dde00 .delay (20000,20000,20000) L_0x24dde00/d; +v0x24402a0_0 .net "S", 0 0, L_0x24ddfd0; 1 drivers +v0x2440340_0 .alias "in0", 0 0, v0x24409d0_0; +v0x24403e0_0 .alias "in1", 0 0, v0x2440ea0_0; +v0x2440480_0 .net "nS", 0 0, L_0x24ca170; 1 drivers +v0x2440530_0 .net "out0", 0 0, L_0x24ca1f0; 1 drivers +v0x24405d0_0 .net "out1", 0 0, L_0x24ca300; 1 drivers +v0x24406b0_0 .alias "outfinal", 0 0, v0x2440a80_0; +S_0x243ecf0 .scope generate, "addbits[31]" "addbits[31]" 2 230, 2 230, S_0x2426ca0; + .timescale -9 -12; +P_0x2426e18 .param/l "i" 2 230, +C4<011111>; +S_0x243ee20 .scope module, "attempt" "MiddleAddSubSLT" 2 232, 2 89, S_0x243ecf0; + .timescale -9 -12; +L_0x24dfda0/d .functor NOT 1, L_0x24cbd00, C4<0>, C4<0>, C4<0>; +L_0x24dfda0 .delay (10000,10000,10000) L_0x24dfda0/d; +L_0x24e1360/d .functor NOT 1, L_0x24e1400, C4<0>, C4<0>, C4<0>; +L_0x24e1360 .delay (10000,10000,10000) L_0x24e1360/d; +L_0x24e14a0/d .functor AND 1, L_0x24e15e0, L_0x24e1360, C4<1>, C4<1>; +L_0x24e14a0 .delay (20000,20000,20000) L_0x24e14a0/d; +L_0x24e1680/d .functor XOR 1, L_0x24e0ea0, L_0x24e1130, C4<0>, C4<0>; +L_0x24e1680 .delay (40000,40000,40000) L_0x24e1680/d; +L_0x24e17a0/d .functor XOR 1, L_0x24e1680, L_0x24cbe30, C4<0>, C4<0>; +L_0x24e17a0 .delay (40000,40000,40000) L_0x24e17a0/d; +L_0x24e18c0/d .functor AND 1, L_0x24e0ea0, L_0x24e1130, C4<1>, C4<1>; +L_0x24e18c0 .delay (20000,20000,20000) L_0x24e18c0/d; +L_0x24e1a60/d .functor AND 1, L_0x24e1680, L_0x24cbe30, C4<1>, C4<1>; +L_0x24e1a60 .delay (20000,20000,20000) L_0x24e1a60/d; +L_0x24e1b50/d .functor OR 1, L_0x24e18c0, L_0x24e1a60, C4<0>, C4<0>; +L_0x24e1b50 .delay (20000,20000,20000) L_0x24e1b50/d; +v0x243f490_0 .net "A", 0 0, L_0x24e0ea0; 1 drivers +v0x243f550_0 .net "AandB", 0 0, L_0x24e18c0; 1 drivers +v0x243f5f0_0 .net "AddSubSLTSum", 0 0, L_0x24e17a0; 1 drivers +v0x243f690_0 .net "AxorB", 0 0, L_0x24e1680; 1 drivers +v0x243f710_0 .net "B", 0 0, L_0x24cbd00; 1 drivers +v0x243f7c0_0 .net "BornB", 0 0, L_0x24e1130; 1 drivers +v0x243f880_0 .net "CINandAxorB", 0 0, L_0x24e1a60; 1 drivers +v0x243f900_0 .alias "Command", 2 0, v0x2463430_0; +v0x243f9d0_0 .net *"_s3", 0 0, L_0x24e1400; 1 drivers +v0x243fa50_0 .net *"_s5", 0 0, L_0x24e15e0; 1 drivers +v0x243fb50_0 .net "carryin", 0 0, L_0x24cbe30; 1 drivers +v0x243fbf0_0 .net "carryout", 0 0, L_0x24e1b50; 1 drivers +v0x243fd00_0 .net "nB", 0 0, L_0x24dfda0; 1 drivers +v0x243fdb0_0 .net "nCmd2", 0 0, L_0x24e1360; 1 drivers +v0x243feb0_0 .net "subtract", 0 0, L_0x24e14a0; 1 drivers +L_0x24e12c0 .part C4, 0, 1; +L_0x24e1400 .part C4, 2, 1; +L_0x24e15e0 .part C4, 0, 1; +S_0x243ef10 .scope module, "mux0" "TwoInMux" 2 105, 2 8, S_0x243ee20; + .timescale -9 -12; +L_0x24dff00/d .functor NOT 1, L_0x24e12c0, C4<0>, C4<0>, C4<0>; +L_0x24dff00 .delay (10000,10000,10000) L_0x24dff00/d; +L_0x24e0f50/d .functor AND 1, L_0x24cbd00, L_0x24dff00, C4<1>, C4<1>; +L_0x24e0f50 .delay (20000,20000,20000) L_0x24e0f50/d; +L_0x24e1040/d .functor AND 1, L_0x24dfda0, L_0x24e12c0, C4<1>, C4<1>; +L_0x24e1040 .delay (20000,20000,20000) L_0x24e1040/d; +L_0x24e1130/d .functor OR 1, L_0x24e0f50, L_0x24e1040, C4<0>, C4<0>; +L_0x24e1130 .delay (20000,20000,20000) L_0x24e1130/d; +v0x243f000_0 .net "S", 0 0, L_0x24e12c0; 1 drivers +v0x243f080_0 .alias "in0", 0 0, v0x243f710_0; +v0x243f120_0 .alias "in1", 0 0, v0x243fd00_0; +v0x243f1c0_0 .net "nS", 0 0, L_0x24dff00; 1 drivers +v0x243f270_0 .net "out0", 0 0, L_0x24e0f50; 1 drivers +v0x243f310_0 .net "out1", 0 0, L_0x24e1040; 1 drivers +v0x243f3f0_0 .alias "outfinal", 0 0, v0x243f7c0_0; +S_0x2413e60 .scope module, "trial1" "AndNand32" 2 280, 2 154, S_0x22690e0; + .timescale -9 -12; +P_0x24265d8 .param/l "size" 2 161, +C4<0100000>; +v0x2426a40_0 .alias "A", 31 0, v0x2462f10_0; +v0x2426ac0_0 .alias "AndNandOut", 31 0, v0x2463200_0; +v0x2426b40_0 .alias "B", 31 0, v0x24632b0_0; +v0x2426bf0_0 .alias "Command", 2 0, v0x2463430_0; +L_0x24e5dd0 .part/pv L_0x24e5ba0, 1, 1, 32; +L_0x2490320 .part C4, 1, 1; +L_0x24903c0 .part C4, 1, 1; +L_0x24e6b80 .part/pv L_0x24e6930, 2, 1, 32; +L_0x24e6c20 .part C4, 2, 1; +L_0x24e6cc0 .part C4, 2, 1; +L_0x24e7610 .part/pv L_0x24e73a0, 3, 1, 32; +L_0x24e76b0 .part C4, 3, 1; +L_0x24e77a0 .part C4, 3, 1; +L_0x24e8070 .part/pv L_0x24e7e00, 4, 1, 32; +L_0x24e8170 .part C4, 4, 1; +L_0x24e8210 .part C4, 4, 1; +L_0x24e8ae0 .part/pv L_0x24e8870, 5, 1, 32; +L_0x24e8b80 .part C4, 5, 1; +L_0x24e8ca0 .part C4, 5, 1; +L_0x24e95b0 .part/pv L_0x24e9340, 6, 1, 32; +L_0x24e96e0 .part C4, 6, 1; +L_0x24e9780 .part C4, 6, 1; +L_0x24ea0b0 .part/pv L_0x24e9e40, 7, 1, 32; +L_0x24ea150 .part C4, 7, 1; +L_0x24e9870 .part C4, 7, 1; +L_0x24eab10 .part/pv L_0x24ea8a0, 8, 1, 32; +L_0x24ea1f0 .part C4, 8, 1; +L_0x24eac70 .part C4, 8, 1; +L_0x24eb590 .part/pv L_0x24eb320, 9, 1, 32; +L_0x24eb630 .part C4, 9, 1; +L_0x24ead60 .part C4, 9, 1; +L_0x24ec000 .part/pv L_0x24ebd90, 10, 1, 32; +L_0x24eb6d0 .part C4, 10, 1; +L_0x24ec190 .part C4, 10, 1; +L_0x24eca70 .part/pv L_0x24ec800, 11, 1, 32; +L_0x24ecb10 .part C4, 11, 1; +L_0x24ec280 .part C4, 11, 1; +L_0x24ed4e0 .part/pv L_0x24ed270, 12, 1, 32; +L_0x24ecbb0 .part C4, 12, 1; +L_0x24ed6a0 .part C4, 12, 1; +L_0x24edf60 .part/pv L_0x24edcf0, 13, 1, 32; +L_0x24ee000 .part C4, 13, 1; +L_0x24ed740 .part C4, 13, 1; +L_0x24ee9c0 .part/pv L_0x24ee750, 14, 1, 32; +L_0x24ee0a0 .part C4, 14, 1; +L_0x24ee140 .part C4, 14, 1; +L_0x24ef430 .part/pv L_0x24ef1c0, 15, 1, 32; +L_0x24ef4d0 .part C4, 15, 1; +L_0x24eec00 .part C4, 15, 1; +L_0x24efea0 .part/pv L_0x24efc30, 16, 1, 32; +L_0x24ef570 .part C4, 16, 1; +L_0x24ef610 .part C4, 16, 1; +L_0x24f0920 .part/pv L_0x24f06b0, 17, 1, 32; +L_0x24f09c0 .part C4, 17, 1; +L_0x24f0110 .part C4, 17, 1; +L_0x24f1380 .part/pv L_0x24f1110, 18, 1, 32; +L_0x24f0a60 .part C4, 18, 1; +L_0x24f0b00 .part C4, 18, 1; +L_0x24f1e00 .part/pv L_0x24f1b90, 19, 1, 32; +L_0x24f1ea0 .part C4, 19, 1; +L_0x24f1420 .part C4, 19, 1; +L_0x24f2860 .part/pv L_0x24f25f0, 20, 1, 32; +L_0x24f1f40 .part C4, 20, 1; +L_0x24f1fe0 .part C4, 20, 1; +L_0x24f32d0 .part/pv L_0x24f3060, 21, 1, 32; +L_0x24f3370 .part C4, 21, 1; +L_0x24f2900 .part C4, 21, 1; +L_0x24f3d40 .part/pv L_0x24f3ad0, 22, 1, 32; +L_0x24f3410 .part C4, 22, 1; +L_0x24f34b0 .part C4, 22, 1; +L_0x24f47c0 .part/pv L_0x24f4550, 23, 1, 32; +L_0x24f4860 .part C4, 23, 1; +L_0x24f3de0 .part C4, 23, 1; +L_0x24f5220 .part/pv L_0x24f4fb0, 24, 1, 32; +L_0x24f4900 .part C4, 24, 1; +L_0x24f49a0 .part C4, 24, 1; +L_0x24f5c90 .part/pv L_0x24f5a20, 25, 1, 32; +L_0x24f5d30 .part C4, 25, 1; +L_0x24f52c0 .part C4, 25, 1; +L_0x24f66f0 .part/pv L_0x24f6480, 26, 1, 32; +L_0x24f5dd0 .part C4, 26, 1; +L_0x24f5e70 .part C4, 26, 1; +L_0x24f7160 .part/pv L_0x24f6ef0, 27, 1, 32; +L_0x24f7200 .part C4, 27, 1; +L_0x24f6790 .part C4, 27, 1; +L_0x24f7bd0 .part/pv L_0x24f7960, 28, 1, 32; +L_0x24f72a0 .part C4, 28, 1; +L_0x24f7340 .part C4, 28, 1; +L_0x24f8650 .part/pv L_0x24f83e0, 29, 1, 32; +L_0x24f86f0 .part C4, 29, 1; +L_0x24df8f0 .part C4, 29, 1; +L_0x24f97b0 .part/pv L_0x24df9e0, 30, 1, 32; +L_0x24df630 .part C4, 30, 1; +L_0x24df6d0 .part C4, 30, 1; +L_0x24fa160 .part/pv L_0x24f9f30, 31, 1, 32; +L_0x24fa200 .part C4, 31, 1; +L_0x24f9850 .part C4, 31, 1; +L_0x24fab10 .part/pv L_0x24fa8e0, 0, 1, 32; +L_0x24fa2a0 .part C4, 0, 1; +L_0x24fa340 .part C4, 0, 1; +S_0x243dab0 .scope module, "attempt2" "AndNand" 2 165, 2 48, S_0x2413e60; + .timescale -9 -12; +L_0x24f9940/d .functor NAND 1, L_0x24fa2a0, L_0x24fa340, C4<1>, C4<1>; +L_0x24f9940 .delay (10000,10000,10000) L_0x24f9940/d; +L_0x24f9aa0/d .functor NOT 1, L_0x24f9940, C4<0>, C4<0>, C4<0>; +L_0x24f9aa0 .delay (10000,10000,10000) L_0x24f9aa0/d; +v0x243e0d0_0 .net "A", 0 0, L_0x24fa2a0; 1 drivers +v0x243e190_0 .net "AandB", 0 0, L_0x24f9aa0; 1 drivers +v0x243e210_0 .net "AnandB", 0 0, L_0x24f9940; 1 drivers +v0x243e2c0_0 .net "AndNandOut", 0 0, L_0x24fa8e0; 1 drivers +v0x243e3a0_0 .net "B", 0 0, L_0x24fa340; 1 drivers +v0x243e420_0 .alias "Command", 2 0, v0x2463430_0; +L_0x24faa70 .part C4, 0, 1; +S_0x243dba0 .scope module, "potato" "TwoInMux" 2 60, 2 8, S_0x243dab0; + .timescale -9 -12; +L_0x24fa620/d .functor NOT 1, L_0x24faa70, C4<0>, C4<0>, C4<0>; +L_0x24fa620 .delay (10000,10000,10000) L_0x24fa620/d; +L_0x24fa6c0/d .functor AND 1, L_0x24f9aa0, L_0x24fa620, C4<1>, C4<1>; +L_0x24fa6c0 .delay (20000,20000,20000) L_0x24fa6c0/d; +L_0x24fa7b0/d .functor AND 1, L_0x24f9940, L_0x24faa70, C4<1>, C4<1>; +L_0x24fa7b0 .delay (20000,20000,20000) L_0x24fa7b0/d; +L_0x24fa8e0/d .functor OR 1, L_0x24fa6c0, L_0x24fa7b0, C4<0>, C4<0>; +L_0x24fa8e0 .delay (20000,20000,20000) L_0x24fa8e0/d; +v0x243dc90_0 .net "S", 0 0, L_0x24faa70; 1 drivers +v0x243dd10_0 .alias "in0", 0 0, v0x243e190_0; +v0x243dd90_0 .alias "in1", 0 0, v0x243e210_0; +v0x243de30_0 .net "nS", 0 0, L_0x24fa620; 1 drivers +v0x243deb0_0 .net "out0", 0 0, L_0x24fa6c0; 1 drivers +v0x243df50_0 .net "out1", 0 0, L_0x24fa7b0; 1 drivers +v0x243e030_0 .alias "outfinal", 0 0, v0x243e2c0_0; +S_0x243cef0 .scope generate, "andbits[1]" "andbits[1]" 2 169, 2 169, S_0x2413e60; + .timescale -9 -12; +P_0x243cfe8 .param/l "i" 2 169, +C4<01>; +S_0x243d060 .scope module, "attempt" "AndNand" 2 171, 2 48, S_0x243cef0; + .timescale -9 -12; +L_0x24e4670/d .functor NAND 1, L_0x2490320, L_0x24903c0, C4<1>, C4<1>; +L_0x24e4670 .delay (10000,10000,10000) L_0x24e4670/d; +L_0x24e4730/d .functor NOT 1, L_0x24e4670, C4<0>, C4<0>, C4<0>; +L_0x24e4730 .delay (10000,10000,10000) L_0x24e4730/d; +v0x243d6a0_0 .net "A", 0 0, L_0x2490320; 1 drivers +v0x243d760_0 .net "AandB", 0 0, L_0x24e4730; 1 drivers +v0x243d7e0_0 .net "AnandB", 0 0, L_0x24e4670; 1 drivers +v0x243d890_0 .net "AndNandOut", 0 0, L_0x24e5ba0; 1 drivers +v0x243d970_0 .net "B", 0 0, L_0x24903c0; 1 drivers +v0x243d9f0_0 .alias "Command", 2 0, v0x2463430_0; +L_0x24e5d30 .part C4, 0, 1; +S_0x243d150 .scope module, "potato" "TwoInMux" 2 60, 2 8, S_0x243d060; + .timescale -9 -12; +L_0x24e4860/d .functor NOT 1, L_0x24e5d30, C4<0>, C4<0>, C4<0>; +L_0x24e4860 .delay (10000,10000,10000) L_0x24e4860/d; +L_0x24e4920/d .functor AND 1, L_0x24e4730, L_0x24e4860, C4<1>, C4<1>; +L_0x24e4920 .delay (20000,20000,20000) L_0x24e4920/d; +L_0x24e5a70/d .functor AND 1, L_0x24e4670, L_0x24e5d30, C4<1>, C4<1>; +L_0x24e5a70 .delay (20000,20000,20000) L_0x24e5a70/d; +L_0x24e5ba0/d .functor OR 1, L_0x24e4920, L_0x24e5a70, C4<0>, C4<0>; +L_0x24e5ba0 .delay (20000,20000,20000) L_0x24e5ba0/d; +v0x243d240_0 .net "S", 0 0, L_0x24e5d30; 1 drivers +v0x243d2c0_0 .alias "in0", 0 0, v0x243d760_0; +v0x243d360_0 .alias "in1", 0 0, v0x243d7e0_0; +v0x243d400_0 .net "nS", 0 0, L_0x24e4860; 1 drivers +v0x243d480_0 .net "out0", 0 0, L_0x24e4920; 1 drivers +v0x243d520_0 .net "out1", 0 0, L_0x24e5a70; 1 drivers +v0x243d600_0 .alias "outfinal", 0 0, v0x243d890_0; +S_0x243c330 .scope generate, "andbits[2]" "andbits[2]" 2 169, 2 169, S_0x2413e60; + .timescale -9 -12; +P_0x243c428 .param/l "i" 2 169, +C4<010>; +S_0x243c4a0 .scope module, "attempt" "AndNand" 2 171, 2 48, S_0x243c330; + .timescale -9 -12; +L_0x24904b0/d .functor NAND 1, L_0x24e6c20, L_0x24e6cc0, C4<1>, C4<1>; +L_0x24904b0 .delay (10000,10000,10000) L_0x24904b0/d; +L_0x2490610/d .functor NOT 1, L_0x24904b0, C4<0>, C4<0>, C4<0>; +L_0x2490610 .delay (10000,10000,10000) L_0x2490610/d; +v0x243cae0_0 .net "A", 0 0, L_0x24e6c20; 1 drivers +v0x243cba0_0 .net "AandB", 0 0, L_0x2490610; 1 drivers +v0x243cc20_0 .net "AnandB", 0 0, L_0x24904b0; 1 drivers +v0x243ccd0_0 .net "AndNandOut", 0 0, L_0x24e6930; 1 drivers +v0x243cdb0_0 .net "B", 0 0, L_0x24e6cc0; 1 drivers +v0x243ce30_0 .alias "Command", 2 0, v0x2463430_0; +L_0x24e6ae0 .part C4, 0, 1; +S_0x243c590 .scope module, "potato" "TwoInMux" 2 60, 2 8, S_0x243c4a0; + .timescale -9 -12; +L_0x24906d0/d .functor NOT 1, L_0x24e6ae0, C4<0>, C4<0>, C4<0>; +L_0x24906d0 .delay (10000,10000,10000) L_0x24906d0/d; +L_0x24e6710/d .functor AND 1, L_0x2490610, L_0x24906d0, C4<1>, C4<1>; +L_0x24e6710 .delay (20000,20000,20000) L_0x24e6710/d; +L_0x24e6800/d .functor AND 1, L_0x24904b0, L_0x24e6ae0, C4<1>, C4<1>; +L_0x24e6800 .delay (20000,20000,20000) L_0x24e6800/d; +L_0x24e6930/d .functor OR 1, L_0x24e6710, L_0x24e6800, C4<0>, C4<0>; +L_0x24e6930 .delay (20000,20000,20000) L_0x24e6930/d; +v0x243c680_0 .net "S", 0 0, L_0x24e6ae0; 1 drivers +v0x243c700_0 .alias "in0", 0 0, v0x243cba0_0; +v0x243c7a0_0 .alias "in1", 0 0, v0x243cc20_0; +v0x243c840_0 .net "nS", 0 0, L_0x24906d0; 1 drivers +v0x243c8c0_0 .net "out0", 0 0, L_0x24e6710; 1 drivers +v0x243c960_0 .net "out1", 0 0, L_0x24e6800; 1 drivers +v0x243ca40_0 .alias "outfinal", 0 0, v0x243ccd0_0; +S_0x243b770 .scope generate, "andbits[3]" "andbits[3]" 2 169, 2 169, S_0x2413e60; + .timescale -9 -12; +P_0x243b868 .param/l "i" 2 169, +C4<011>; +S_0x243b8e0 .scope module, "attempt" "AndNand" 2 171, 2 48, S_0x243b770; + .timescale -9 -12; +L_0x24e6df0/d .functor NAND 1, L_0x24e76b0, L_0x24e77a0, C4<1>, C4<1>; +L_0x24e6df0 .delay (10000,10000,10000) L_0x24e6df0/d; +L_0x24e6f50/d .functor NOT 1, L_0x24e6df0, C4<0>, C4<0>, C4<0>; +L_0x24e6f50 .delay (10000,10000,10000) L_0x24e6f50/d; +v0x243bf20_0 .net "A", 0 0, L_0x24e76b0; 1 drivers +v0x243bfe0_0 .net "AandB", 0 0, L_0x24e6f50; 1 drivers +v0x243c060_0 .net "AnandB", 0 0, L_0x24e6df0; 1 drivers +v0x243c110_0 .net "AndNandOut", 0 0, L_0x24e73a0; 1 drivers +v0x243c1f0_0 .net "B", 0 0, L_0x24e77a0; 1 drivers +v0x243c270_0 .alias "Command", 2 0, v0x2463430_0; +L_0x24e7570 .part C4, 0, 1; +S_0x243b9d0 .scope module, "potato" "TwoInMux" 2 60, 2 8, S_0x243b8e0; + .timescale -9 -12; +L_0x24e7080/d .functor NOT 1, L_0x24e7570, C4<0>, C4<0>, C4<0>; +L_0x24e7080 .delay (10000,10000,10000) L_0x24e7080/d; +L_0x24e7140/d .functor AND 1, L_0x24e6f50, L_0x24e7080, C4<1>, C4<1>; +L_0x24e7140 .delay (20000,20000,20000) L_0x24e7140/d; +L_0x24e7250/d .functor AND 1, L_0x24e6df0, L_0x24e7570, C4<1>, C4<1>; +L_0x24e7250 .delay (20000,20000,20000) L_0x24e7250/d; +L_0x24e73a0/d .functor OR 1, L_0x24e7140, L_0x24e7250, C4<0>, C4<0>; +L_0x24e73a0 .delay (20000,20000,20000) L_0x24e73a0/d; +v0x243bac0_0 .net "S", 0 0, L_0x24e7570; 1 drivers +v0x243bb40_0 .alias "in0", 0 0, v0x243bfe0_0; +v0x243bbe0_0 .alias "in1", 0 0, v0x243c060_0; +v0x243bc80_0 .net "nS", 0 0, L_0x24e7080; 1 drivers +v0x243bd00_0 .net "out0", 0 0, L_0x24e7140; 1 drivers +v0x243bda0_0 .net "out1", 0 0, L_0x24e7250; 1 drivers +v0x243be80_0 .alias "outfinal", 0 0, v0x243c110_0; +S_0x243abb0 .scope generate, "andbits[4]" "andbits[4]" 2 169, 2 169, S_0x2413e60; + .timescale -9 -12; +P_0x243aca8 .param/l "i" 2 169, +C4<0100>; +S_0x243ad20 .scope module, "attempt" "AndNand" 2 171, 2 48, S_0x243abb0; + .timescale -9 -12; +L_0x24e7890/d .functor NAND 1, L_0x24e8170, L_0x24e8210, C4<1>, C4<1>; +L_0x24e7890 .delay (10000,10000,10000) L_0x24e7890/d; +L_0x24e79b0/d .functor NOT 1, L_0x24e7890, C4<0>, C4<0>, C4<0>; +L_0x24e79b0 .delay (10000,10000,10000) L_0x24e79b0/d; +v0x243b360_0 .net "A", 0 0, L_0x24e8170; 1 drivers +v0x243b420_0 .net "AandB", 0 0, L_0x24e79b0; 1 drivers +v0x243b4a0_0 .net "AnandB", 0 0, L_0x24e7890; 1 drivers +v0x243b550_0 .net "AndNandOut", 0 0, L_0x24e7e00; 1 drivers +v0x243b630_0 .net "B", 0 0, L_0x24e8210; 1 drivers +v0x243b6b0_0 .alias "Command", 2 0, v0x2463430_0; +L_0x24e7fd0 .part C4, 0, 1; +S_0x243ae10 .scope module, "potato" "TwoInMux" 2 60, 2 8, S_0x243ad20; + .timescale -9 -12; +L_0x24e7ae0/d .functor NOT 1, L_0x24e7fd0, C4<0>, C4<0>, C4<0>; +L_0x24e7ae0 .delay (10000,10000,10000) L_0x24e7ae0/d; +L_0x24e7ba0/d .functor AND 1, L_0x24e79b0, L_0x24e7ae0, C4<1>, C4<1>; +L_0x24e7ba0 .delay (20000,20000,20000) L_0x24e7ba0/d; +L_0x24e7cb0/d .functor AND 1, L_0x24e7890, L_0x24e7fd0, C4<1>, C4<1>; +L_0x24e7cb0 .delay (20000,20000,20000) L_0x24e7cb0/d; +L_0x24e7e00/d .functor OR 1, L_0x24e7ba0, L_0x24e7cb0, C4<0>, C4<0>; +L_0x24e7e00 .delay (20000,20000,20000) L_0x24e7e00/d; +v0x243af00_0 .net "S", 0 0, L_0x24e7fd0; 1 drivers +v0x243af80_0 .alias "in0", 0 0, v0x243b420_0; +v0x243b020_0 .alias "in1", 0 0, v0x243b4a0_0; +v0x243b0c0_0 .net "nS", 0 0, L_0x24e7ae0; 1 drivers +v0x243b140_0 .net "out0", 0 0, L_0x24e7ba0; 1 drivers +v0x243b1e0_0 .net "out1", 0 0, L_0x24e7cb0; 1 drivers +v0x243b2c0_0 .alias "outfinal", 0 0, v0x243b550_0; +S_0x2439ff0 .scope generate, "andbits[5]" "andbits[5]" 2 169, 2 169, S_0x2413e60; + .timescale -9 -12; +P_0x243a0e8 .param/l "i" 2 169, +C4<0101>; +S_0x243a160 .scope module, "attempt" "AndNand" 2 171, 2 48, S_0x2439ff0; + .timescale -9 -12; +L_0x24e8110/d .functor NAND 1, L_0x24e8b80, L_0x24e8ca0, C4<1>, C4<1>; +L_0x24e8110 .delay (10000,10000,10000) L_0x24e8110/d; +L_0x24e8420/d .functor NOT 1, L_0x24e8110, C4<0>, C4<0>, C4<0>; +L_0x24e8420 .delay (10000,10000,10000) L_0x24e8420/d; +v0x243a7a0_0 .net "A", 0 0, L_0x24e8b80; 1 drivers +v0x243a860_0 .net "AandB", 0 0, L_0x24e8420; 1 drivers +v0x243a8e0_0 .net "AnandB", 0 0, L_0x24e8110; 1 drivers +v0x243a990_0 .net "AndNandOut", 0 0, L_0x24e8870; 1 drivers +v0x243aa70_0 .net "B", 0 0, L_0x24e8ca0; 1 drivers +v0x243aaf0_0 .alias "Command", 2 0, v0x2463430_0; +L_0x24e8a40 .part C4, 0, 1; +S_0x243a250 .scope module, "potato" "TwoInMux" 2 60, 2 8, S_0x243a160; + .timescale -9 -12; +L_0x24e8550/d .functor NOT 1, L_0x24e8a40, C4<0>, C4<0>, C4<0>; +L_0x24e8550 .delay (10000,10000,10000) L_0x24e8550/d; +L_0x24e8610/d .functor AND 1, L_0x24e8420, L_0x24e8550, C4<1>, C4<1>; +L_0x24e8610 .delay (20000,20000,20000) L_0x24e8610/d; +L_0x24e8720/d .functor AND 1, L_0x24e8110, L_0x24e8a40, C4<1>, C4<1>; +L_0x24e8720 .delay (20000,20000,20000) L_0x24e8720/d; +L_0x24e8870/d .functor OR 1, L_0x24e8610, L_0x24e8720, C4<0>, C4<0>; +L_0x24e8870 .delay (20000,20000,20000) L_0x24e8870/d; +v0x243a340_0 .net "S", 0 0, L_0x24e8a40; 1 drivers +v0x243a3c0_0 .alias "in0", 0 0, v0x243a860_0; +v0x243a460_0 .alias "in1", 0 0, v0x243a8e0_0; +v0x243a500_0 .net "nS", 0 0, L_0x24e8550; 1 drivers +v0x243a580_0 .net "out0", 0 0, L_0x24e8610; 1 drivers +v0x243a620_0 .net "out1", 0 0, L_0x24e8720; 1 drivers +v0x243a700_0 .alias "outfinal", 0 0, v0x243a990_0; +S_0x2439440 .scope generate, "andbits[6]" "andbits[6]" 2 169, 2 169, S_0x2413e60; + .timescale -9 -12; +P_0x2439538 .param/l "i" 2 169, +C4<0110>; +S_0x24395b0 .scope module, "attempt" "AndNand" 2 171, 2 48, S_0x2439440; + .timescale -9 -12; +L_0x24e8d90/d .functor NAND 1, L_0x24e96e0, L_0x24e9780, C4<1>, C4<1>; +L_0x24e8d90 .delay (10000,10000,10000) L_0x24e8d90/d; +L_0x24e8ef0/d .functor NOT 1, L_0x24e8d90, C4<0>, C4<0>, C4<0>; +L_0x24e8ef0 .delay (10000,10000,10000) L_0x24e8ef0/d; +v0x2439c10_0 .net "A", 0 0, L_0x24e96e0; 1 drivers +v0x2439cd0_0 .net "AandB", 0 0, L_0x24e8ef0; 1 drivers +v0x2439d50_0 .net "AnandB", 0 0, L_0x24e8d90; 1 drivers +v0x2439dd0_0 .net "AndNandOut", 0 0, L_0x24e9340; 1 drivers +v0x2439eb0_0 .net "B", 0 0, L_0x24e9780; 1 drivers +v0x2439f30_0 .alias "Command", 2 0, v0x2463430_0; +L_0x24e9510 .part C4, 0, 1; +S_0x24396a0 .scope module, "potato" "TwoInMux" 2 60, 2 8, S_0x24395b0; + .timescale -9 -12; +L_0x24e9020/d .functor NOT 1, L_0x24e9510, C4<0>, C4<0>, C4<0>; +L_0x24e9020 .delay (10000,10000,10000) L_0x24e9020/d; +L_0x24e90e0/d .functor AND 1, L_0x24e8ef0, L_0x24e9020, C4<1>, C4<1>; +L_0x24e90e0 .delay (20000,20000,20000) L_0x24e90e0/d; +L_0x24e91f0/d .functor AND 1, L_0x24e8d90, L_0x24e9510, C4<1>, C4<1>; +L_0x24e91f0 .delay (20000,20000,20000) L_0x24e91f0/d; +L_0x24e9340/d .functor OR 1, L_0x24e90e0, L_0x24e91f0, C4<0>, C4<0>; +L_0x24e9340 .delay (20000,20000,20000) L_0x24e9340/d; +v0x2439790_0 .net "S", 0 0, L_0x24e9510; 1 drivers +v0x2439830_0 .alias "in0", 0 0, v0x2439cd0_0; +v0x24398d0_0 .alias "in1", 0 0, v0x2439d50_0; +v0x2439970_0 .net "nS", 0 0, L_0x24e9020; 1 drivers +v0x24399f0_0 .net "out0", 0 0, L_0x24e90e0; 1 drivers +v0x2439a90_0 .net "out1", 0 0, L_0x24e91f0; 1 drivers +v0x2439b70_0 .alias "outfinal", 0 0, v0x2439dd0_0; +S_0x2438870 .scope generate, "andbits[7]" "andbits[7]" 2 169, 2 169, S_0x2413e60; + .timescale -9 -12; +P_0x2438968 .param/l "i" 2 169, +C4<0111>; +S_0x24389e0 .scope module, "attempt" "AndNand" 2 171, 2 48, S_0x2438870; + .timescale -9 -12; +L_0x24e9650/d .functor NAND 1, L_0x24ea150, L_0x24e9870, C4<1>, C4<1>; +L_0x24e9650 .delay (10000,10000,10000) L_0x24e9650/d; +L_0x24e99f0/d .functor NOT 1, L_0x24e9650, C4<0>, C4<0>, C4<0>; +L_0x24e99f0 .delay (10000,10000,10000) L_0x24e99f0/d; +v0x2439000_0 .net "A", 0 0, L_0x24ea150; 1 drivers +v0x24390c0_0 .net "AandB", 0 0, L_0x24e99f0; 1 drivers +v0x2439170_0 .net "AnandB", 0 0, L_0x24e9650; 1 drivers +v0x2439220_0 .net "AndNandOut", 0 0, L_0x24e9e40; 1 drivers +v0x2439300_0 .net "B", 0 0, L_0x24e9870; 1 drivers +v0x2439380_0 .alias "Command", 2 0, v0x2463430_0; +L_0x24ea010 .part C4, 0, 1; +S_0x2438ad0 .scope module, "potato" "TwoInMux" 2 60, 2 8, S_0x24389e0; + .timescale -9 -12; +L_0x24e9b20/d .functor NOT 1, L_0x24ea010, C4<0>, C4<0>, C4<0>; +L_0x24e9b20 .delay (10000,10000,10000) L_0x24e9b20/d; +L_0x24e9be0/d .functor AND 1, L_0x24e99f0, L_0x24e9b20, C4<1>, C4<1>; +L_0x24e9be0 .delay (20000,20000,20000) L_0x24e9be0/d; +L_0x24e9cf0/d .functor AND 1, L_0x24e9650, L_0x24ea010, C4<1>, C4<1>; +L_0x24e9cf0 .delay (20000,20000,20000) L_0x24e9cf0/d; +L_0x24e9e40/d .functor OR 1, L_0x24e9be0, L_0x24e9cf0, C4<0>, C4<0>; +L_0x24e9e40 .delay (20000,20000,20000) L_0x24e9e40/d; +v0x2438bc0_0 .net "S", 0 0, L_0x24ea010; 1 drivers +v0x2438c40_0 .alias "in0", 0 0, v0x24390c0_0; +v0x2438ce0_0 .alias "in1", 0 0, v0x2439170_0; +v0x2438d80_0 .net "nS", 0 0, L_0x24e9b20; 1 drivers +v0x2438e00_0 .net "out0", 0 0, L_0x24e9be0; 1 drivers +v0x2438ea0_0 .net "out1", 0 0, L_0x24e9cf0; 1 drivers +v0x2438f80_0 .alias "outfinal", 0 0, v0x2439220_0; +S_0x2437cb0 .scope generate, "andbits[8]" "andbits[8]" 2 169, 2 169, S_0x2413e60; + .timescale -9 -12; +P_0x2437da8 .param/l "i" 2 169, +C4<01000>; +S_0x2437e20 .scope module, "attempt" "AndNand" 2 171, 2 48, S_0x2437cb0; + .timescale -9 -12; +L_0x24ea2f0/d .functor NAND 1, L_0x24ea1f0, L_0x24eac70, C4<1>, C4<1>; +L_0x24ea2f0 .delay (10000,10000,10000) L_0x24ea2f0/d; +L_0x24ea450/d .functor NOT 1, L_0x24ea2f0, C4<0>, C4<0>, C4<0>; +L_0x24ea450 .delay (10000,10000,10000) L_0x24ea450/d; +v0x2438460_0 .net "A", 0 0, L_0x24ea1f0; 1 drivers +v0x2438520_0 .net "AandB", 0 0, L_0x24ea450; 1 drivers +v0x24385a0_0 .net "AnandB", 0 0, L_0x24ea2f0; 1 drivers +v0x2438650_0 .net "AndNandOut", 0 0, L_0x24ea8a0; 1 drivers +v0x2438730_0 .net "B", 0 0, L_0x24eac70; 1 drivers +v0x24387b0_0 .alias "Command", 2 0, v0x2463430_0; +L_0x24eaa70 .part C4, 0, 1; +S_0x2437f10 .scope module, "potato" "TwoInMux" 2 60, 2 8, S_0x2437e20; + .timescale -9 -12; +L_0x24ea580/d .functor NOT 1, L_0x24eaa70, C4<0>, C4<0>, C4<0>; +L_0x24ea580 .delay (10000,10000,10000) L_0x24ea580/d; +L_0x24ea640/d .functor AND 1, L_0x24ea450, L_0x24ea580, C4<1>, C4<1>; +L_0x24ea640 .delay (20000,20000,20000) L_0x24ea640/d; +L_0x24ea750/d .functor AND 1, L_0x24ea2f0, L_0x24eaa70, C4<1>, C4<1>; +L_0x24ea750 .delay (20000,20000,20000) L_0x24ea750/d; +L_0x24ea8a0/d .functor OR 1, L_0x24ea640, L_0x24ea750, C4<0>, C4<0>; +L_0x24ea8a0 .delay (20000,20000,20000) L_0x24ea8a0/d; +v0x2438000_0 .net "S", 0 0, L_0x24eaa70; 1 drivers +v0x2438080_0 .alias "in0", 0 0, v0x2438520_0; +v0x2438120_0 .alias "in1", 0 0, v0x24385a0_0; +v0x24381c0_0 .net "nS", 0 0, L_0x24ea580; 1 drivers +v0x2438240_0 .net "out0", 0 0, L_0x24ea640; 1 drivers +v0x24382e0_0 .net "out1", 0 0, L_0x24ea750; 1 drivers +v0x24383c0_0 .alias "outfinal", 0 0, v0x2438650_0; +S_0x24370f0 .scope generate, "andbits[9]" "andbits[9]" 2 169, 2 169, S_0x2413e60; + .timescale -9 -12; +P_0x24371e8 .param/l "i" 2 169, +C4<01001>; +S_0x2437260 .scope module, "attempt" "AndNand" 2 171, 2 48, S_0x24370f0; + .timescale -9 -12; +L_0x24eabb0/d .functor NAND 1, L_0x24eb630, L_0x24ead60, C4<1>, C4<1>; +L_0x24eabb0 .delay (10000,10000,10000) L_0x24eabb0/d; +L_0x24eaed0/d .functor NOT 1, L_0x24eabb0, C4<0>, C4<0>, C4<0>; +L_0x24eaed0 .delay (10000,10000,10000) L_0x24eaed0/d; +v0x24378a0_0 .net "A", 0 0, L_0x24eb630; 1 drivers +v0x2437960_0 .net "AandB", 0 0, L_0x24eaed0; 1 drivers +v0x24379e0_0 .net "AnandB", 0 0, L_0x24eabb0; 1 drivers +v0x2437a90_0 .net "AndNandOut", 0 0, L_0x24eb320; 1 drivers +v0x2437b70_0 .net "B", 0 0, L_0x24ead60; 1 drivers +v0x2437bf0_0 .alias "Command", 2 0, v0x2463430_0; +L_0x24eb4f0 .part C4, 0, 1; +S_0x2437350 .scope module, "potato" "TwoInMux" 2 60, 2 8, S_0x2437260; + .timescale -9 -12; +L_0x24eb000/d .functor NOT 1, L_0x24eb4f0, C4<0>, C4<0>, C4<0>; +L_0x24eb000 .delay (10000,10000,10000) L_0x24eb000/d; +L_0x24eb0c0/d .functor AND 1, L_0x24eaed0, L_0x24eb000, C4<1>, C4<1>; +L_0x24eb0c0 .delay (20000,20000,20000) L_0x24eb0c0/d; +L_0x24eb1d0/d .functor AND 1, L_0x24eabb0, L_0x24eb4f0, C4<1>, C4<1>; +L_0x24eb1d0 .delay (20000,20000,20000) L_0x24eb1d0/d; +L_0x24eb320/d .functor OR 1, L_0x24eb0c0, L_0x24eb1d0, C4<0>, C4<0>; +L_0x24eb320 .delay (20000,20000,20000) L_0x24eb320/d; +v0x2437440_0 .net "S", 0 0, L_0x24eb4f0; 1 drivers +v0x24374c0_0 .alias "in0", 0 0, v0x2437960_0; +v0x2437560_0 .alias "in1", 0 0, v0x24379e0_0; +v0x2437600_0 .net "nS", 0 0, L_0x24eb000; 1 drivers +v0x2437680_0 .net "out0", 0 0, L_0x24eb0c0; 1 drivers +v0x2437720_0 .net "out1", 0 0, L_0x24eb1d0; 1 drivers +v0x2437800_0 .alias "outfinal", 0 0, v0x2437a90_0; +S_0x2436530 .scope generate, "andbits[10]" "andbits[10]" 2 169, 2 169, S_0x2413e60; + .timescale -9 -12; +P_0x2436628 .param/l "i" 2 169, +C4<01010>; +S_0x24366a0 .scope module, "attempt" "AndNand" 2 171, 2 48, S_0x2436530; + .timescale -9 -12; +L_0x24eb800/d .functor NAND 1, L_0x24eb6d0, L_0x24ec190, C4<1>, C4<1>; +L_0x24eb800 .delay (10000,10000,10000) L_0x24eb800/d; +L_0x24eb940/d .functor NOT 1, L_0x24eb800, C4<0>, C4<0>, C4<0>; +L_0x24eb940 .delay (10000,10000,10000) L_0x24eb940/d; +v0x2436ce0_0 .net "A", 0 0, L_0x24eb6d0; 1 drivers +v0x2436da0_0 .net "AandB", 0 0, L_0x24eb940; 1 drivers +v0x2436e20_0 .net "AnandB", 0 0, L_0x24eb800; 1 drivers +v0x2436ed0_0 .net "AndNandOut", 0 0, L_0x24ebd90; 1 drivers +v0x2436fb0_0 .net "B", 0 0, L_0x24ec190; 1 drivers +v0x2437030_0 .alias "Command", 2 0, v0x2463430_0; +L_0x24ebf60 .part C4, 0, 1; +S_0x2436790 .scope module, "potato" "TwoInMux" 2 60, 2 8, S_0x24366a0; + .timescale -9 -12; +L_0x24eba70/d .functor NOT 1, L_0x24ebf60, C4<0>, C4<0>, C4<0>; +L_0x24eba70 .delay (10000,10000,10000) L_0x24eba70/d; +L_0x24ebb30/d .functor AND 1, L_0x24eb940, L_0x24eba70, C4<1>, C4<1>; +L_0x24ebb30 .delay (20000,20000,20000) L_0x24ebb30/d; +L_0x24ebc40/d .functor AND 1, L_0x24eb800, L_0x24ebf60, C4<1>, C4<1>; +L_0x24ebc40 .delay (20000,20000,20000) L_0x24ebc40/d; +L_0x24ebd90/d .functor OR 1, L_0x24ebb30, L_0x24ebc40, C4<0>, C4<0>; +L_0x24ebd90 .delay (20000,20000,20000) L_0x24ebd90/d; +v0x2436880_0 .net "S", 0 0, L_0x24ebf60; 1 drivers +v0x2436900_0 .alias "in0", 0 0, v0x2436da0_0; +v0x24369a0_0 .alias "in1", 0 0, v0x2436e20_0; +v0x2436a40_0 .net "nS", 0 0, L_0x24eba70; 1 drivers +v0x2436ac0_0 .net "out0", 0 0, L_0x24ebb30; 1 drivers +v0x2436b60_0 .net "out1", 0 0, L_0x24ebc40; 1 drivers +v0x2436c40_0 .alias "outfinal", 0 0, v0x2436ed0_0; +S_0x2435970 .scope generate, "andbits[11]" "andbits[11]" 2 169, 2 169, S_0x2413e60; + .timescale -9 -12; +P_0x2435a68 .param/l "i" 2 169, +C4<01011>; +S_0x2435ae0 .scope module, "attempt" "AndNand" 2 171, 2 48, S_0x2435970; + .timescale -9 -12; +L_0x24ec0a0/d .functor NAND 1, L_0x24ecb10, L_0x24ec280, C4<1>, C4<1>; +L_0x24ec0a0 .delay (10000,10000,10000) L_0x24ec0a0/d; +L_0x24ec3d0/d .functor NOT 1, L_0x24ec0a0, C4<0>, C4<0>, C4<0>; +L_0x24ec3d0 .delay (10000,10000,10000) L_0x24ec3d0/d; +v0x2436120_0 .net "A", 0 0, L_0x24ecb10; 1 drivers +v0x24361e0_0 .net "AandB", 0 0, L_0x24ec3d0; 1 drivers +v0x2436260_0 .net "AnandB", 0 0, L_0x24ec0a0; 1 drivers +v0x2436310_0 .net "AndNandOut", 0 0, L_0x24ec800; 1 drivers +v0x24363f0_0 .net "B", 0 0, L_0x24ec280; 1 drivers +v0x2436470_0 .alias "Command", 2 0, v0x2463430_0; +L_0x24ec9d0 .part C4, 0, 1; +S_0x2435bd0 .scope module, "potato" "TwoInMux" 2 60, 2 8, S_0x2435ae0; + .timescale -9 -12; +L_0x24ec4e0/d .functor NOT 1, L_0x24ec9d0, C4<0>, C4<0>, C4<0>; +L_0x24ec4e0 .delay (10000,10000,10000) L_0x24ec4e0/d; +L_0x24ec5a0/d .functor AND 1, L_0x24ec3d0, L_0x24ec4e0, C4<1>, C4<1>; +L_0x24ec5a0 .delay (20000,20000,20000) L_0x24ec5a0/d; +L_0x24ec6b0/d .functor AND 1, L_0x24ec0a0, L_0x24ec9d0, C4<1>, C4<1>; +L_0x24ec6b0 .delay (20000,20000,20000) L_0x24ec6b0/d; +L_0x24ec800/d .functor OR 1, L_0x24ec5a0, L_0x24ec6b0, C4<0>, C4<0>; +L_0x24ec800 .delay (20000,20000,20000) L_0x24ec800/d; +v0x2435cc0_0 .net "S", 0 0, L_0x24ec9d0; 1 drivers +v0x2435d40_0 .alias "in0", 0 0, v0x24361e0_0; +v0x2435de0_0 .alias "in1", 0 0, v0x2436260_0; +v0x2435e80_0 .net "nS", 0 0, L_0x24ec4e0; 1 drivers +v0x2435f00_0 .net "out0", 0 0, L_0x24ec5a0; 1 drivers +v0x2435fa0_0 .net "out1", 0 0, L_0x24ec6b0; 1 drivers +v0x2436080_0 .alias "outfinal", 0 0, v0x2436310_0; +S_0x2434db0 .scope generate, "andbits[12]" "andbits[12]" 2 169, 2 169, S_0x2413e60; + .timescale -9 -12; +P_0x2434ea8 .param/l "i" 2 169, +C4<01100>; +S_0x2434f20 .scope module, "attempt" "AndNand" 2 171, 2 48, S_0x2434db0; + .timescale -9 -12; +L_0x24eccc0/d .functor NAND 1, L_0x24ecbb0, L_0x24ed6a0, C4<1>, C4<1>; +L_0x24eccc0 .delay (10000,10000,10000) L_0x24eccc0/d; +L_0x24ece20/d .functor NOT 1, L_0x24eccc0, C4<0>, C4<0>, C4<0>; +L_0x24ece20 .delay (10000,10000,10000) L_0x24ece20/d; +v0x2435560_0 .net "A", 0 0, L_0x24ecbb0; 1 drivers +v0x2435620_0 .net "AandB", 0 0, L_0x24ece20; 1 drivers +v0x24356a0_0 .net "AnandB", 0 0, L_0x24eccc0; 1 drivers +v0x2435750_0 .net "AndNandOut", 0 0, L_0x24ed270; 1 drivers +v0x2435830_0 .net "B", 0 0, L_0x24ed6a0; 1 drivers +v0x24358b0_0 .alias "Command", 2 0, v0x2463430_0; +L_0x24ed440 .part C4, 0, 1; +S_0x2435010 .scope module, "potato" "TwoInMux" 2 60, 2 8, S_0x2434f20; + .timescale -9 -12; +L_0x24ecf50/d .functor NOT 1, L_0x24ed440, C4<0>, C4<0>, C4<0>; +L_0x24ecf50 .delay (10000,10000,10000) L_0x24ecf50/d; +L_0x24ed010/d .functor AND 1, L_0x24ece20, L_0x24ecf50, C4<1>, C4<1>; +L_0x24ed010 .delay (20000,20000,20000) L_0x24ed010/d; +L_0x24ed120/d .functor AND 1, L_0x24eccc0, L_0x24ed440, C4<1>, C4<1>; +L_0x24ed120 .delay (20000,20000,20000) L_0x24ed120/d; +L_0x24ed270/d .functor OR 1, L_0x24ed010, L_0x24ed120, C4<0>, C4<0>; +L_0x24ed270 .delay (20000,20000,20000) L_0x24ed270/d; +v0x2435100_0 .net "S", 0 0, L_0x24ed440; 1 drivers +v0x2435180_0 .alias "in0", 0 0, v0x2435620_0; +v0x2435220_0 .alias "in1", 0 0, v0x24356a0_0; +v0x24352c0_0 .net "nS", 0 0, L_0x24ecf50; 1 drivers +v0x2435340_0 .net "out0", 0 0, L_0x24ed010; 1 drivers +v0x24353e0_0 .net "out1", 0 0, L_0x24ed120; 1 drivers +v0x24354c0_0 .alias "outfinal", 0 0, v0x2435750_0; +S_0x24341f0 .scope generate, "andbits[13]" "andbits[13]" 2 169, 2 169, S_0x2413e60; + .timescale -9 -12; +P_0x24342e8 .param/l "i" 2 169, +C4<01101>; +S_0x2434360 .scope module, "attempt" "AndNand" 2 171, 2 48, S_0x24341f0; + .timescale -9 -12; +L_0x24ed580/d .functor NAND 1, L_0x24ee000, L_0x24ed740, C4<1>, C4<1>; +L_0x24ed580 .delay (10000,10000,10000) L_0x24ed580/d; +L_0x24ed8c0/d .functor NOT 1, L_0x24ed580, C4<0>, C4<0>, C4<0>; +L_0x24ed8c0 .delay (10000,10000,10000) L_0x24ed8c0/d; +v0x24349a0_0 .net "A", 0 0, L_0x24ee000; 1 drivers +v0x2434a60_0 .net "AandB", 0 0, L_0x24ed8c0; 1 drivers +v0x2434ae0_0 .net "AnandB", 0 0, L_0x24ed580; 1 drivers +v0x2434b90_0 .net "AndNandOut", 0 0, L_0x24edcf0; 1 drivers +v0x2434c70_0 .net "B", 0 0, L_0x24ed740; 1 drivers +v0x2434cf0_0 .alias "Command", 2 0, v0x2463430_0; +L_0x24edec0 .part C4, 0, 1; +S_0x2434450 .scope module, "potato" "TwoInMux" 2 60, 2 8, S_0x2434360; + .timescale -9 -12; +L_0x24ed9d0/d .functor NOT 1, L_0x24edec0, C4<0>, C4<0>, C4<0>; +L_0x24ed9d0 .delay (10000,10000,10000) L_0x24ed9d0/d; +L_0x24eda90/d .functor AND 1, L_0x24ed8c0, L_0x24ed9d0, C4<1>, C4<1>; +L_0x24eda90 .delay (20000,20000,20000) L_0x24eda90/d; +L_0x24edba0/d .functor AND 1, L_0x24ed580, L_0x24edec0, C4<1>, C4<1>; +L_0x24edba0 .delay (20000,20000,20000) L_0x24edba0/d; +L_0x24edcf0/d .functor OR 1, L_0x24eda90, L_0x24edba0, C4<0>, C4<0>; +L_0x24edcf0 .delay (20000,20000,20000) L_0x24edcf0/d; +v0x2434540_0 .net "S", 0 0, L_0x24edec0; 1 drivers +v0x24345c0_0 .alias "in0", 0 0, v0x2434a60_0; +v0x2434660_0 .alias "in1", 0 0, v0x2434ae0_0; +v0x2434700_0 .net "nS", 0 0, L_0x24ed9d0; 1 drivers +v0x2434780_0 .net "out0", 0 0, L_0x24eda90; 1 drivers +v0x2434820_0 .net "out1", 0 0, L_0x24edba0; 1 drivers +v0x2434900_0 .alias "outfinal", 0 0, v0x2434b90_0; +S_0x2433630 .scope generate, "andbits[14]" "andbits[14]" 2 169, 2 169, S_0x2413e60; + .timescale -9 -12; +P_0x2433728 .param/l "i" 2 169, +C4<01110>; +S_0x24337a0 .scope module, "attempt" "AndNand" 2 171, 2 48, S_0x2433630; + .timescale -9 -12; +L_0x24ee1e0/d .functor NAND 1, L_0x24ee0a0, L_0x24ee140, C4<1>, C4<1>; +L_0x24ee1e0 .delay (10000,10000,10000) L_0x24ee1e0/d; +L_0x24ee320/d .functor NOT 1, L_0x24ee1e0, C4<0>, C4<0>, C4<0>; +L_0x24ee320 .delay (10000,10000,10000) L_0x24ee320/d; +v0x2433de0_0 .net "A", 0 0, L_0x24ee0a0; 1 drivers +v0x2433ea0_0 .net "AandB", 0 0, L_0x24ee320; 1 drivers +v0x2433f20_0 .net "AnandB", 0 0, L_0x24ee1e0; 1 drivers +v0x2433fd0_0 .net "AndNandOut", 0 0, L_0x24ee750; 1 drivers +v0x24340b0_0 .net "B", 0 0, L_0x24ee140; 1 drivers +v0x2434130_0 .alias "Command", 2 0, v0x2463430_0; +L_0x24ee920 .part C4, 0, 1; +S_0x2433890 .scope module, "potato" "TwoInMux" 2 60, 2 8, S_0x24337a0; + .timescale -9 -12; +L_0x24ee430/d .functor NOT 1, L_0x24ee920, C4<0>, C4<0>, C4<0>; +L_0x24ee430 .delay (10000,10000,10000) L_0x24ee430/d; +L_0x24ee4f0/d .functor AND 1, L_0x24ee320, L_0x24ee430, C4<1>, C4<1>; +L_0x24ee4f0 .delay (20000,20000,20000) L_0x24ee4f0/d; +L_0x24ee600/d .functor AND 1, L_0x24ee1e0, L_0x24ee920, C4<1>, C4<1>; +L_0x24ee600 .delay (20000,20000,20000) L_0x24ee600/d; +L_0x24ee750/d .functor OR 1, L_0x24ee4f0, L_0x24ee600, C4<0>, C4<0>; +L_0x24ee750 .delay (20000,20000,20000) L_0x24ee750/d; +v0x2433980_0 .net "S", 0 0, L_0x24ee920; 1 drivers +v0x2433a00_0 .alias "in0", 0 0, v0x2433ea0_0; +v0x2433aa0_0 .alias "in1", 0 0, v0x2433f20_0; +v0x2433b40_0 .net "nS", 0 0, L_0x24ee430; 1 drivers +v0x2433bc0_0 .net "out0", 0 0, L_0x24ee4f0; 1 drivers +v0x2433c60_0 .net "out1", 0 0, L_0x24ee600; 1 drivers +v0x2433d40_0 .alias "outfinal", 0 0, v0x2433fd0_0; +S_0x2432a70 .scope generate, "andbits[15]" "andbits[15]" 2 169, 2 169, S_0x2413e60; + .timescale -9 -12; +P_0x2432b68 .param/l "i" 2 169, +C4<01111>; +S_0x2432be0 .scope module, "attempt" "AndNand" 2 171, 2 48, S_0x2432a70; + .timescale -9 -12; +L_0x24eea60/d .functor NAND 1, L_0x24ef4d0, L_0x24eec00, C4<1>, C4<1>; +L_0x24eea60 .delay (10000,10000,10000) L_0x24eea60/d; +L_0x24eedb0/d .functor NOT 1, L_0x24eea60, C4<0>, C4<0>, C4<0>; +L_0x24eedb0 .delay (10000,10000,10000) L_0x24eedb0/d; +v0x2433220_0 .net "A", 0 0, L_0x24ef4d0; 1 drivers +v0x24332e0_0 .net "AandB", 0 0, L_0x24eedb0; 1 drivers +v0x2433360_0 .net "AnandB", 0 0, L_0x24eea60; 1 drivers +v0x2433410_0 .net "AndNandOut", 0 0, L_0x24ef1c0; 1 drivers +v0x24334f0_0 .net "B", 0 0, L_0x24eec00; 1 drivers +v0x2433570_0 .alias "Command", 2 0, v0x2463430_0; +L_0x24ef390 .part C4, 0, 1; +S_0x2432cd0 .scope module, "potato" "TwoInMux" 2 60, 2 8, S_0x2432be0; + .timescale -9 -12; +L_0x24eeea0/d .functor NOT 1, L_0x24ef390, C4<0>, C4<0>, C4<0>; +L_0x24eeea0 .delay (10000,10000,10000) L_0x24eeea0/d; +L_0x24eef60/d .functor AND 1, L_0x24eedb0, L_0x24eeea0, C4<1>, C4<1>; +L_0x24eef60 .delay (20000,20000,20000) L_0x24eef60/d; +L_0x24ef070/d .functor AND 1, L_0x24eea60, L_0x24ef390, C4<1>, C4<1>; +L_0x24ef070 .delay (20000,20000,20000) L_0x24ef070/d; +L_0x24ef1c0/d .functor OR 1, L_0x24eef60, L_0x24ef070, C4<0>, C4<0>; +L_0x24ef1c0 .delay (20000,20000,20000) L_0x24ef1c0/d; +v0x2432dc0_0 .net "S", 0 0, L_0x24ef390; 1 drivers +v0x2432e40_0 .alias "in0", 0 0, v0x24332e0_0; +v0x2432ee0_0 .alias "in1", 0 0, v0x2433360_0; +v0x2432f80_0 .net "nS", 0 0, L_0x24eeea0; 1 drivers +v0x2433000_0 .net "out0", 0 0, L_0x24eef60; 1 drivers +v0x24330a0_0 .net "out1", 0 0, L_0x24ef070; 1 drivers +v0x2433180_0 .alias "outfinal", 0 0, v0x2433410_0; +S_0x2431eb0 .scope generate, "andbits[16]" "andbits[16]" 2 169, 2 169, S_0x2413e60; + .timescale -9 -12; +P_0x2431fa8 .param/l "i" 2 169, +C4<010000>; +S_0x2432020 .scope module, "attempt" "AndNand" 2 171, 2 48, S_0x2431eb0; + .timescale -9 -12; +L_0x24eecf0/d .functor NAND 1, L_0x24ef570, L_0x24ef610, C4<1>, C4<1>; +L_0x24eecf0 .delay (10000,10000,10000) L_0x24eecf0/d; +L_0x24ef7e0/d .functor NOT 1, L_0x24eecf0, C4<0>, C4<0>, C4<0>; +L_0x24ef7e0 .delay (10000,10000,10000) L_0x24ef7e0/d; +v0x2432660_0 .net "A", 0 0, L_0x24ef570; 1 drivers +v0x2432720_0 .net "AandB", 0 0, L_0x24ef7e0; 1 drivers +v0x24327a0_0 .net "AnandB", 0 0, L_0x24eecf0; 1 drivers +v0x2432850_0 .net "AndNandOut", 0 0, L_0x24efc30; 1 drivers +v0x2432930_0 .net "B", 0 0, L_0x24ef610; 1 drivers +v0x24329b0_0 .alias "Command", 2 0, v0x2463430_0; +L_0x24efe00 .part C4, 0, 1; +S_0x2432110 .scope module, "potato" "TwoInMux" 2 60, 2 8, S_0x2432020; + .timescale -9 -12; +L_0x24ef910/d .functor NOT 1, L_0x24efe00, C4<0>, C4<0>, C4<0>; +L_0x24ef910 .delay (10000,10000,10000) L_0x24ef910/d; +L_0x24ef9d0/d .functor AND 1, L_0x24ef7e0, L_0x24ef910, C4<1>, C4<1>; +L_0x24ef9d0 .delay (20000,20000,20000) L_0x24ef9d0/d; +L_0x24efae0/d .functor AND 1, L_0x24eecf0, L_0x24efe00, C4<1>, C4<1>; +L_0x24efae0 .delay (20000,20000,20000) L_0x24efae0/d; +L_0x24efc30/d .functor OR 1, L_0x24ef9d0, L_0x24efae0, C4<0>, C4<0>; +L_0x24efc30 .delay (20000,20000,20000) L_0x24efc30/d; +v0x2432200_0 .net "S", 0 0, L_0x24efe00; 1 drivers +v0x2432280_0 .alias "in0", 0 0, v0x2432720_0; +v0x2432320_0 .alias "in1", 0 0, v0x24327a0_0; +v0x24323c0_0 .net "nS", 0 0, L_0x24ef910; 1 drivers +v0x2432440_0 .net "out0", 0 0, L_0x24ef9d0; 1 drivers +v0x24324e0_0 .net "out1", 0 0, L_0x24efae0; 1 drivers +v0x24325c0_0 .alias "outfinal", 0 0, v0x2432850_0; +S_0x24312f0 .scope generate, "andbits[17]" "andbits[17]" 2 169, 2 169, S_0x2413e60; + .timescale -9 -12; +P_0x24313e8 .param/l "i" 2 169, +C4<010001>; +S_0x2431460 .scope module, "attempt" "AndNand" 2 171, 2 48, S_0x24312f0; + .timescale -9 -12; +L_0x24eff40/d .functor NAND 1, L_0x24f09c0, L_0x24f0110, C4<1>, C4<1>; +L_0x24eff40 .delay (10000,10000,10000) L_0x24eff40/d; +L_0x24f02a0/d .functor NOT 1, L_0x24eff40, C4<0>, C4<0>, C4<0>; +L_0x24f02a0 .delay (10000,10000,10000) L_0x24f02a0/d; +v0x2431aa0_0 .net "A", 0 0, L_0x24f09c0; 1 drivers +v0x2431b60_0 .net "AandB", 0 0, L_0x24f02a0; 1 drivers +v0x2431be0_0 .net "AnandB", 0 0, L_0x24eff40; 1 drivers +v0x2431c90_0 .net "AndNandOut", 0 0, L_0x24f06b0; 1 drivers +v0x2431d70_0 .net "B", 0 0, L_0x24f0110; 1 drivers +v0x2431df0_0 .alias "Command", 2 0, v0x2463430_0; +L_0x24f0880 .part C4, 0, 1; +S_0x2431550 .scope module, "potato" "TwoInMux" 2 60, 2 8, S_0x2431460; + .timescale -9 -12; +L_0x24f0390/d .functor NOT 1, L_0x24f0880, C4<0>, C4<0>, C4<0>; +L_0x24f0390 .delay (10000,10000,10000) L_0x24f0390/d; +L_0x24f0450/d .functor AND 1, L_0x24f02a0, L_0x24f0390, C4<1>, C4<1>; +L_0x24f0450 .delay (20000,20000,20000) L_0x24f0450/d; +L_0x24f0560/d .functor AND 1, L_0x24eff40, L_0x24f0880, C4<1>, C4<1>; +L_0x24f0560 .delay (20000,20000,20000) L_0x24f0560/d; +L_0x24f06b0/d .functor OR 1, L_0x24f0450, L_0x24f0560, C4<0>, C4<0>; +L_0x24f06b0 .delay (20000,20000,20000) L_0x24f06b0/d; +v0x2431640_0 .net "S", 0 0, L_0x24f0880; 1 drivers +v0x24316c0_0 .alias "in0", 0 0, v0x2431b60_0; +v0x2431760_0 .alias "in1", 0 0, v0x2431be0_0; +v0x2431800_0 .net "nS", 0 0, L_0x24f0390; 1 drivers +v0x2431880_0 .net "out0", 0 0, L_0x24f0450; 1 drivers +v0x2431920_0 .net "out1", 0 0, L_0x24f0560; 1 drivers +v0x2431a00_0 .alias "outfinal", 0 0, v0x2431c90_0; +S_0x2430730 .scope generate, "andbits[18]" "andbits[18]" 2 169, 2 169, S_0x2413e60; + .timescale -9 -12; +P_0x2430828 .param/l "i" 2 169, +C4<010010>; +S_0x24308a0 .scope module, "attempt" "AndNand" 2 171, 2 48, S_0x2430730; + .timescale -9 -12; +L_0x24f0200/d .functor NAND 1, L_0x24f0a60, L_0x24f0b00, C4<1>, C4<1>; +L_0x24f0200 .delay (10000,10000,10000) L_0x24f0200/d; +L_0x24f0ce0/d .functor NOT 1, L_0x24f0200, C4<0>, C4<0>, C4<0>; +L_0x24f0ce0 .delay (10000,10000,10000) L_0x24f0ce0/d; +v0x2430ee0_0 .net "A", 0 0, L_0x24f0a60; 1 drivers +v0x2430fa0_0 .net "AandB", 0 0, L_0x24f0ce0; 1 drivers +v0x2431020_0 .net "AnandB", 0 0, L_0x24f0200; 1 drivers +v0x24310d0_0 .net "AndNandOut", 0 0, L_0x24f1110; 1 drivers +v0x24311b0_0 .net "B", 0 0, L_0x24f0b00; 1 drivers +v0x2431230_0 .alias "Command", 2 0, v0x2463430_0; +L_0x24f12e0 .part C4, 0, 1; +S_0x2430990 .scope module, "potato" "TwoInMux" 2 60, 2 8, S_0x24308a0; + .timescale -9 -12; +L_0x24f0df0/d .functor NOT 1, L_0x24f12e0, C4<0>, C4<0>, C4<0>; +L_0x24f0df0 .delay (10000,10000,10000) L_0x24f0df0/d; +L_0x24f0eb0/d .functor AND 1, L_0x24f0ce0, L_0x24f0df0, C4<1>, C4<1>; +L_0x24f0eb0 .delay (20000,20000,20000) L_0x24f0eb0/d; +L_0x24f0fc0/d .functor AND 1, L_0x24f0200, L_0x24f12e0, C4<1>, C4<1>; +L_0x24f0fc0 .delay (20000,20000,20000) L_0x24f0fc0/d; +L_0x24f1110/d .functor OR 1, L_0x24f0eb0, L_0x24f0fc0, C4<0>, C4<0>; +L_0x24f1110 .delay (20000,20000,20000) L_0x24f1110/d; +v0x2430a80_0 .net "S", 0 0, L_0x24f12e0; 1 drivers +v0x2430b00_0 .alias "in0", 0 0, v0x2430fa0_0; +v0x2430ba0_0 .alias "in1", 0 0, v0x2431020_0; +v0x2430c40_0 .net "nS", 0 0, L_0x24f0df0; 1 drivers +v0x2430cc0_0 .net "out0", 0 0, L_0x24f0eb0; 1 drivers +v0x2430d60_0 .net "out1", 0 0, L_0x24f0fc0; 1 drivers +v0x2430e40_0 .alias "outfinal", 0 0, v0x24310d0_0; +S_0x242fb70 .scope generate, "andbits[19]" "andbits[19]" 2 169, 2 169, S_0x2413e60; + .timescale -9 -12; +P_0x242fc68 .param/l "i" 2 169, +C4<010011>; +S_0x242fce0 .scope module, "attempt" "AndNand" 2 171, 2 48, S_0x242fb70; + .timescale -9 -12; +L_0x24f15e0/d .functor NAND 1, L_0x24f1ea0, L_0x24f1420, C4<1>, C4<1>; +L_0x24f15e0 .delay (10000,10000,10000) L_0x24f15e0/d; +L_0x24f1740/d .functor NOT 1, L_0x24f15e0, C4<0>, C4<0>, C4<0>; +L_0x24f1740 .delay (10000,10000,10000) L_0x24f1740/d; +v0x2430320_0 .net "A", 0 0, L_0x24f1ea0; 1 drivers +v0x24303e0_0 .net "AandB", 0 0, L_0x24f1740; 1 drivers +v0x2430460_0 .net "AnandB", 0 0, L_0x24f15e0; 1 drivers +v0x2430510_0 .net "AndNandOut", 0 0, L_0x24f1b90; 1 drivers +v0x24305f0_0 .net "B", 0 0, L_0x24f1420; 1 drivers +v0x2430670_0 .alias "Command", 2 0, v0x2463430_0; +L_0x24f1d60 .part C4, 0, 1; +S_0x242fdd0 .scope module, "potato" "TwoInMux" 2 60, 2 8, S_0x242fce0; + .timescale -9 -12; +L_0x24f1870/d .functor NOT 1, L_0x24f1d60, C4<0>, C4<0>, C4<0>; +L_0x24f1870 .delay (10000,10000,10000) L_0x24f1870/d; +L_0x24f1930/d .functor AND 1, L_0x24f1740, L_0x24f1870, C4<1>, C4<1>; +L_0x24f1930 .delay (20000,20000,20000) L_0x24f1930/d; +L_0x24f1a40/d .functor AND 1, L_0x24f15e0, L_0x24f1d60, C4<1>, C4<1>; +L_0x24f1a40 .delay (20000,20000,20000) L_0x24f1a40/d; +L_0x24f1b90/d .functor OR 1, L_0x24f1930, L_0x24f1a40, C4<0>, C4<0>; +L_0x24f1b90 .delay (20000,20000,20000) L_0x24f1b90/d; +v0x242fec0_0 .net "S", 0 0, L_0x24f1d60; 1 drivers +v0x242ff40_0 .alias "in0", 0 0, v0x24303e0_0; +v0x242ffe0_0 .alias "in1", 0 0, v0x2430460_0; +v0x2430080_0 .net "nS", 0 0, L_0x24f1870; 1 drivers +v0x2430100_0 .net "out0", 0 0, L_0x24f1930; 1 drivers +v0x24301a0_0 .net "out1", 0 0, L_0x24f1a40; 1 drivers +v0x2430280_0 .alias "outfinal", 0 0, v0x2430510_0; +S_0x242efb0 .scope generate, "andbits[20]" "andbits[20]" 2 169, 2 169, S_0x2413e60; + .timescale -9 -12; +P_0x242f0a8 .param/l "i" 2 169, +C4<010100>; +S_0x242f120 .scope module, "attempt" "AndNand" 2 171, 2 48, S_0x242efb0; + .timescale -9 -12; +L_0x24f1510/d .functor NAND 1, L_0x24f1f40, L_0x24f1fe0, C4<1>, C4<1>; +L_0x24f1510 .delay (10000,10000,10000) L_0x24f1510/d; +L_0x24f21a0/d .functor NOT 1, L_0x24f1510, C4<0>, C4<0>, C4<0>; +L_0x24f21a0 .delay (10000,10000,10000) L_0x24f21a0/d; +v0x242f760_0 .net "A", 0 0, L_0x24f1f40; 1 drivers +v0x242f820_0 .net "AandB", 0 0, L_0x24f21a0; 1 drivers +v0x242f8a0_0 .net "AnandB", 0 0, L_0x24f1510; 1 drivers +v0x242f950_0 .net "AndNandOut", 0 0, L_0x24f25f0; 1 drivers +v0x242fa30_0 .net "B", 0 0, L_0x24f1fe0; 1 drivers +v0x242fab0_0 .alias "Command", 2 0, v0x2463430_0; +L_0x24f27c0 .part C4, 0, 1; +S_0x242f210 .scope module, "potato" "TwoInMux" 2 60, 2 8, S_0x242f120; + .timescale -9 -12; +L_0x24f22d0/d .functor NOT 1, L_0x24f27c0, C4<0>, C4<0>, C4<0>; +L_0x24f22d0 .delay (10000,10000,10000) L_0x24f22d0/d; +L_0x24f2390/d .functor AND 1, L_0x24f21a0, L_0x24f22d0, C4<1>, C4<1>; +L_0x24f2390 .delay (20000,20000,20000) L_0x24f2390/d; +L_0x24f24a0/d .functor AND 1, L_0x24f1510, L_0x24f27c0, C4<1>, C4<1>; +L_0x24f24a0 .delay (20000,20000,20000) L_0x24f24a0/d; +L_0x24f25f0/d .functor OR 1, L_0x24f2390, L_0x24f24a0, C4<0>, C4<0>; +L_0x24f25f0 .delay (20000,20000,20000) L_0x24f25f0/d; +v0x242f300_0 .net "S", 0 0, L_0x24f27c0; 1 drivers +v0x242f380_0 .alias "in0", 0 0, v0x242f820_0; +v0x242f420_0 .alias "in1", 0 0, v0x242f8a0_0; +v0x242f4c0_0 .net "nS", 0 0, L_0x24f22d0; 1 drivers +v0x242f540_0 .net "out0", 0 0, L_0x24f2390; 1 drivers +v0x242f5e0_0 .net "out1", 0 0, L_0x24f24a0; 1 drivers +v0x242f6c0_0 .alias "outfinal", 0 0, v0x242f950_0; +S_0x242e3f0 .scope generate, "andbits[21]" "andbits[21]" 2 169, 2 169, S_0x2413e60; + .timescale -9 -12; +P_0x242e4e8 .param/l "i" 2 169, +C4<010101>; +S_0x242e560 .scope module, "attempt" "AndNand" 2 171, 2 48, S_0x242e3f0; + .timescale -9 -12; +L_0x24f2af0/d .functor NAND 1, L_0x24f3370, L_0x24f2900, C4<1>, C4<1>; +L_0x24f2af0 .delay (10000,10000,10000) L_0x24f2af0/d; +L_0x24f2c30/d .functor NOT 1, L_0x24f2af0, C4<0>, C4<0>, C4<0>; +L_0x24f2c30 .delay (10000,10000,10000) L_0x24f2c30/d; +v0x242eba0_0 .net "A", 0 0, L_0x24f3370; 1 drivers +v0x242ec60_0 .net "AandB", 0 0, L_0x24f2c30; 1 drivers +v0x242ece0_0 .net "AnandB", 0 0, L_0x24f2af0; 1 drivers +v0x242ed90_0 .net "AndNandOut", 0 0, L_0x24f3060; 1 drivers +v0x242ee70_0 .net "B", 0 0, L_0x24f2900; 1 drivers +v0x242eef0_0 .alias "Command", 2 0, v0x2463430_0; +L_0x24f3230 .part C4, 0, 1; +S_0x242e650 .scope module, "potato" "TwoInMux" 2 60, 2 8, S_0x242e560; + .timescale -9 -12; +L_0x24f2d40/d .functor NOT 1, L_0x24f3230, C4<0>, C4<0>, C4<0>; +L_0x24f2d40 .delay (10000,10000,10000) L_0x24f2d40/d; +L_0x24f2e00/d .functor AND 1, L_0x24f2c30, L_0x24f2d40, C4<1>, C4<1>; +L_0x24f2e00 .delay (20000,20000,20000) L_0x24f2e00/d; +L_0x24f2f10/d .functor AND 1, L_0x24f2af0, L_0x24f3230, C4<1>, C4<1>; +L_0x24f2f10 .delay (20000,20000,20000) L_0x24f2f10/d; +L_0x24f3060/d .functor OR 1, L_0x24f2e00, L_0x24f2f10, C4<0>, C4<0>; +L_0x24f3060 .delay (20000,20000,20000) L_0x24f3060/d; +v0x242e740_0 .net "S", 0 0, L_0x24f3230; 1 drivers +v0x242e7c0_0 .alias "in0", 0 0, v0x242ec60_0; +v0x242e860_0 .alias "in1", 0 0, v0x242ece0_0; +v0x242e900_0 .net "nS", 0 0, L_0x24f2d40; 1 drivers +v0x242e980_0 .net "out0", 0 0, L_0x24f2e00; 1 drivers +v0x242ea20_0 .net "out1", 0 0, L_0x24f2f10; 1 drivers +v0x242eb00_0 .alias "outfinal", 0 0, v0x242ed90_0; +S_0x242d830 .scope generate, "andbits[22]" "andbits[22]" 2 169, 2 169, S_0x2413e60; + .timescale -9 -12; +P_0x242d928 .param/l "i" 2 169, +C4<010110>; +S_0x242d9a0 .scope module, "attempt" "AndNand" 2 171, 2 48, S_0x242d830; + .timescale -9 -12; +L_0x24f29f0/d .functor NAND 1, L_0x24f3410, L_0x24f34b0, C4<1>, C4<1>; +L_0x24f29f0 .delay (10000,10000,10000) L_0x24f29f0/d; +L_0x24f36a0/d .functor NOT 1, L_0x24f29f0, C4<0>, C4<0>, C4<0>; +L_0x24f36a0 .delay (10000,10000,10000) L_0x24f36a0/d; +v0x242dfe0_0 .net "A", 0 0, L_0x24f3410; 1 drivers +v0x242e0a0_0 .net "AandB", 0 0, L_0x24f36a0; 1 drivers +v0x242e120_0 .net "AnandB", 0 0, L_0x24f29f0; 1 drivers +v0x242e1d0_0 .net "AndNandOut", 0 0, L_0x24f3ad0; 1 drivers +v0x242e2b0_0 .net "B", 0 0, L_0x24f34b0; 1 drivers +v0x242e330_0 .alias "Command", 2 0, v0x2463430_0; +L_0x24f3ca0 .part C4, 0, 1; +S_0x242da90 .scope module, "potato" "TwoInMux" 2 60, 2 8, S_0x242d9a0; + .timescale -9 -12; +L_0x24f37b0/d .functor NOT 1, L_0x24f3ca0, C4<0>, C4<0>, C4<0>; +L_0x24f37b0 .delay (10000,10000,10000) L_0x24f37b0/d; +L_0x24f3870/d .functor AND 1, L_0x24f36a0, L_0x24f37b0, C4<1>, C4<1>; +L_0x24f3870 .delay (20000,20000,20000) L_0x24f3870/d; +L_0x24f3980/d .functor AND 1, L_0x24f29f0, L_0x24f3ca0, C4<1>, C4<1>; +L_0x24f3980 .delay (20000,20000,20000) L_0x24f3980/d; +L_0x24f3ad0/d .functor OR 1, L_0x24f3870, L_0x24f3980, C4<0>, C4<0>; +L_0x24f3ad0 .delay (20000,20000,20000) L_0x24f3ad0/d; +v0x242db80_0 .net "S", 0 0, L_0x24f3ca0; 1 drivers +v0x242dc00_0 .alias "in0", 0 0, v0x242e0a0_0; +v0x242dca0_0 .alias "in1", 0 0, v0x242e120_0; +v0x242dd40_0 .net "nS", 0 0, L_0x24f37b0; 1 drivers +v0x242ddc0_0 .net "out0", 0 0, L_0x24f3870; 1 drivers +v0x242de60_0 .net "out1", 0 0, L_0x24f3980; 1 drivers +v0x242df40_0 .alias "outfinal", 0 0, v0x242e1d0_0; +S_0x242cc70 .scope generate, "andbits[23]" "andbits[23]" 2 169, 2 169, S_0x2413e60; + .timescale -9 -12; +P_0x242cd68 .param/l "i" 2 169, +C4<010111>; +S_0x242cde0 .scope module, "attempt" "AndNand" 2 171, 2 48, S_0x242cc70; + .timescale -9 -12; +L_0x24f35a0/d .functor NAND 1, L_0x24f4860, L_0x24f3de0, C4<1>, C4<1>; +L_0x24f35a0 .delay (10000,10000,10000) L_0x24f35a0/d; +L_0x24f4100/d .functor NOT 1, L_0x24f35a0, C4<0>, C4<0>, C4<0>; +L_0x24f4100 .delay (10000,10000,10000) L_0x24f4100/d; +v0x242d420_0 .net "A", 0 0, L_0x24f4860; 1 drivers +v0x242d4e0_0 .net "AandB", 0 0, L_0x24f4100; 1 drivers +v0x242d560_0 .net "AnandB", 0 0, L_0x24f35a0; 1 drivers +v0x242d610_0 .net "AndNandOut", 0 0, L_0x24f4550; 1 drivers +v0x242d6f0_0 .net "B", 0 0, L_0x24f3de0; 1 drivers +v0x242d770_0 .alias "Command", 2 0, v0x2463430_0; +L_0x24f4720 .part C4, 0, 1; +S_0x242ced0 .scope module, "potato" "TwoInMux" 2 60, 2 8, S_0x242cde0; + .timescale -9 -12; +L_0x24f4230/d .functor NOT 1, L_0x24f4720, C4<0>, C4<0>, C4<0>; +L_0x24f4230 .delay (10000,10000,10000) L_0x24f4230/d; +L_0x24f42f0/d .functor AND 1, L_0x24f4100, L_0x24f4230, C4<1>, C4<1>; +L_0x24f42f0 .delay (20000,20000,20000) L_0x24f42f0/d; +L_0x24f4400/d .functor AND 1, L_0x24f35a0, L_0x24f4720, C4<1>, C4<1>; +L_0x24f4400 .delay (20000,20000,20000) L_0x24f4400/d; +L_0x24f4550/d .functor OR 1, L_0x24f42f0, L_0x24f4400, C4<0>, C4<0>; +L_0x24f4550 .delay (20000,20000,20000) L_0x24f4550/d; +v0x242cfc0_0 .net "S", 0 0, L_0x24f4720; 1 drivers +v0x242d040_0 .alias "in0", 0 0, v0x242d4e0_0; +v0x242d0e0_0 .alias "in1", 0 0, v0x242d560_0; +v0x242d180_0 .net "nS", 0 0, L_0x24f4230; 1 drivers +v0x242d200_0 .net "out0", 0 0, L_0x24f42f0; 1 drivers +v0x242d2a0_0 .net "out1", 0 0, L_0x24f4400; 1 drivers +v0x242d380_0 .alias "outfinal", 0 0, v0x242d610_0; +S_0x242c0b0 .scope generate, "andbits[24]" "andbits[24]" 2 169, 2 169, S_0x2413e60; + .timescale -9 -12; +P_0x242c1a8 .param/l "i" 2 169, +C4<011000>; +S_0x242c220 .scope module, "attempt" "AndNand" 2 171, 2 48, S_0x242c0b0; + .timescale -9 -12; +L_0x24f3ed0/d .functor NAND 1, L_0x24f4900, L_0x24f49a0, C4<1>, C4<1>; +L_0x24f3ed0 .delay (10000,10000,10000) L_0x24f3ed0/d; +L_0x24f4b80/d .functor NOT 1, L_0x24f3ed0, C4<0>, C4<0>, C4<0>; +L_0x24f4b80 .delay (10000,10000,10000) L_0x24f4b80/d; +v0x242c860_0 .net "A", 0 0, L_0x24f4900; 1 drivers +v0x242c920_0 .net "AandB", 0 0, L_0x24f4b80; 1 drivers +v0x242c9a0_0 .net "AnandB", 0 0, L_0x24f3ed0; 1 drivers +v0x242ca50_0 .net "AndNandOut", 0 0, L_0x24f4fb0; 1 drivers +v0x242cb30_0 .net "B", 0 0, L_0x24f49a0; 1 drivers +v0x242cbb0_0 .alias "Command", 2 0, v0x2463430_0; +L_0x24f5180 .part C4, 0, 1; +S_0x242c310 .scope module, "potato" "TwoInMux" 2 60, 2 8, S_0x242c220; + .timescale -9 -12; +L_0x24f4c90/d .functor NOT 1, L_0x24f5180, C4<0>, C4<0>, C4<0>; +L_0x24f4c90 .delay (10000,10000,10000) L_0x24f4c90/d; +L_0x24f4d50/d .functor AND 1, L_0x24f4b80, L_0x24f4c90, C4<1>, C4<1>; +L_0x24f4d50 .delay (20000,20000,20000) L_0x24f4d50/d; +L_0x24f4e60/d .functor AND 1, L_0x24f3ed0, L_0x24f5180, C4<1>, C4<1>; +L_0x24f4e60 .delay (20000,20000,20000) L_0x24f4e60/d; +L_0x24f4fb0/d .functor OR 1, L_0x24f4d50, L_0x24f4e60, C4<0>, C4<0>; +L_0x24f4fb0 .delay (20000,20000,20000) L_0x24f4fb0/d; +v0x242c400_0 .net "S", 0 0, L_0x24f5180; 1 drivers +v0x242c480_0 .alias "in0", 0 0, v0x242c920_0; +v0x242c520_0 .alias "in1", 0 0, v0x242c9a0_0; +v0x242c5c0_0 .net "nS", 0 0, L_0x24f4c90; 1 drivers +v0x242c640_0 .net "out0", 0 0, L_0x24f4d50; 1 drivers +v0x242c6e0_0 .net "out1", 0 0, L_0x24f4e60; 1 drivers +v0x242c7c0_0 .alias "outfinal", 0 0, v0x242ca50_0; +S_0x242b4f0 .scope generate, "andbits[25]" "andbits[25]" 2 169, 2 169, S_0x2413e60; + .timescale -9 -12; +P_0x242b5e8 .param/l "i" 2 169, +C4<011001>; +S_0x242b660 .scope module, "attempt" "AndNand" 2 171, 2 48, S_0x242b4f0; + .timescale -9 -12; +L_0x24f4a90/d .functor NAND 1, L_0x24f5d30, L_0x24f52c0, C4<1>, C4<1>; +L_0x24f4a90 .delay (10000,10000,10000) L_0x24f4a90/d; +L_0x24f55f0/d .functor NOT 1, L_0x24f4a90, C4<0>, C4<0>, C4<0>; +L_0x24f55f0 .delay (10000,10000,10000) L_0x24f55f0/d; +v0x242bca0_0 .net "A", 0 0, L_0x24f5d30; 1 drivers +v0x242bd60_0 .net "AandB", 0 0, L_0x24f55f0; 1 drivers +v0x242bde0_0 .net "AnandB", 0 0, L_0x24f4a90; 1 drivers +v0x242be90_0 .net "AndNandOut", 0 0, L_0x24f5a20; 1 drivers +v0x242bf70_0 .net "B", 0 0, L_0x24f52c0; 1 drivers +v0x242bff0_0 .alias "Command", 2 0, v0x2463430_0; +L_0x24f5bf0 .part C4, 0, 1; +S_0x242b750 .scope module, "potato" "TwoInMux" 2 60, 2 8, S_0x242b660; + .timescale -9 -12; +L_0x24f5700/d .functor NOT 1, L_0x24f5bf0, C4<0>, C4<0>, C4<0>; +L_0x24f5700 .delay (10000,10000,10000) L_0x24f5700/d; +L_0x24f57c0/d .functor AND 1, L_0x24f55f0, L_0x24f5700, C4<1>, C4<1>; +L_0x24f57c0 .delay (20000,20000,20000) L_0x24f57c0/d; +L_0x24f58d0/d .functor AND 1, L_0x24f4a90, L_0x24f5bf0, C4<1>, C4<1>; +L_0x24f58d0 .delay (20000,20000,20000) L_0x24f58d0/d; +L_0x24f5a20/d .functor OR 1, L_0x24f57c0, L_0x24f58d0, C4<0>, C4<0>; +L_0x24f5a20 .delay (20000,20000,20000) L_0x24f5a20/d; +v0x242b840_0 .net "S", 0 0, L_0x24f5bf0; 1 drivers +v0x242b8c0_0 .alias "in0", 0 0, v0x242bd60_0; +v0x242b960_0 .alias "in1", 0 0, v0x242bde0_0; +v0x242ba00_0 .net "nS", 0 0, L_0x24f5700; 1 drivers +v0x242ba80_0 .net "out0", 0 0, L_0x24f57c0; 1 drivers +v0x242bb20_0 .net "out1", 0 0, L_0x24f58d0; 1 drivers +v0x242bc00_0 .alias "outfinal", 0 0, v0x242be90_0; +S_0x242a930 .scope generate, "andbits[26]" "andbits[26]" 2 169, 2 169, S_0x2413e60; + .timescale -9 -12; +P_0x242aa28 .param/l "i" 2 169, +C4<011010>; +S_0x242aaa0 .scope module, "attempt" "AndNand" 2 171, 2 48, S_0x242a930; + .timescale -9 -12; +L_0x24f53b0/d .functor NAND 1, L_0x24f5dd0, L_0x24f5e70, C4<1>, C4<1>; +L_0x24f53b0 .delay (10000,10000,10000) L_0x24f53b0/d; +L_0x24f6030/d .functor NOT 1, L_0x24f53b0, C4<0>, C4<0>, C4<0>; +L_0x24f6030 .delay (10000,10000,10000) L_0x24f6030/d; +v0x242b0e0_0 .net "A", 0 0, L_0x24f5dd0; 1 drivers +v0x242b1a0_0 .net "AandB", 0 0, L_0x24f6030; 1 drivers +v0x242b220_0 .net "AnandB", 0 0, L_0x24f53b0; 1 drivers +v0x242b2d0_0 .net "AndNandOut", 0 0, L_0x24f6480; 1 drivers +v0x242b3b0_0 .net "B", 0 0, L_0x24f5e70; 1 drivers +v0x242b430_0 .alias "Command", 2 0, v0x2463430_0; +L_0x24f6650 .part C4, 0, 1; +S_0x242ab90 .scope module, "potato" "TwoInMux" 2 60, 2 8, S_0x242aaa0; + .timescale -9 -12; +L_0x24f6160/d .functor NOT 1, L_0x24f6650, C4<0>, C4<0>, C4<0>; +L_0x24f6160 .delay (10000,10000,10000) L_0x24f6160/d; +L_0x24f6220/d .functor AND 1, L_0x24f6030, L_0x24f6160, C4<1>, C4<1>; +L_0x24f6220 .delay (20000,20000,20000) L_0x24f6220/d; +L_0x24f6330/d .functor AND 1, L_0x24f53b0, L_0x24f6650, C4<1>, C4<1>; +L_0x24f6330 .delay (20000,20000,20000) L_0x24f6330/d; +L_0x24f6480/d .functor OR 1, L_0x24f6220, L_0x24f6330, C4<0>, C4<0>; +L_0x24f6480 .delay (20000,20000,20000) L_0x24f6480/d; +v0x242ac80_0 .net "S", 0 0, L_0x24f6650; 1 drivers +v0x242ad00_0 .alias "in0", 0 0, v0x242b1a0_0; +v0x242ada0_0 .alias "in1", 0 0, v0x242b220_0; +v0x242ae40_0 .net "nS", 0 0, L_0x24f6160; 1 drivers +v0x242aec0_0 .net "out0", 0 0, L_0x24f6220; 1 drivers +v0x242af60_0 .net "out1", 0 0, L_0x24f6330; 1 drivers +v0x242b040_0 .alias "outfinal", 0 0, v0x242b2d0_0; +S_0x2429d70 .scope generate, "andbits[27]" "andbits[27]" 2 169, 2 169, S_0x2413e60; + .timescale -9 -12; +P_0x2429e68 .param/l "i" 2 169, +C4<011011>; +S_0x2429ee0 .scope module, "attempt" "AndNand" 2 171, 2 48, S_0x2429d70; + .timescale -9 -12; +L_0x24f5f60/d .functor NAND 1, L_0x24f7200, L_0x24f6790, C4<1>, C4<1>; +L_0x24f5f60 .delay (10000,10000,10000) L_0x24f5f60/d; +L_0x24f6aa0/d .functor NOT 1, L_0x24f5f60, C4<0>, C4<0>, C4<0>; +L_0x24f6aa0 .delay (10000,10000,10000) L_0x24f6aa0/d; +v0x242a520_0 .net "A", 0 0, L_0x24f7200; 1 drivers +v0x242a5e0_0 .net "AandB", 0 0, L_0x24f6aa0; 1 drivers +v0x242a660_0 .net "AnandB", 0 0, L_0x24f5f60; 1 drivers +v0x242a710_0 .net "AndNandOut", 0 0, L_0x24f6ef0; 1 drivers +v0x242a7f0_0 .net "B", 0 0, L_0x24f6790; 1 drivers +v0x242a870_0 .alias "Command", 2 0, v0x2463430_0; +L_0x24f70c0 .part C4, 0, 1; +S_0x2429fd0 .scope module, "potato" "TwoInMux" 2 60, 2 8, S_0x2429ee0; + .timescale -9 -12; +L_0x24f6bd0/d .functor NOT 1, L_0x24f70c0, C4<0>, C4<0>, C4<0>; +L_0x24f6bd0 .delay (10000,10000,10000) L_0x24f6bd0/d; +L_0x24f6c90/d .functor AND 1, L_0x24f6aa0, L_0x24f6bd0, C4<1>, C4<1>; +L_0x24f6c90 .delay (20000,20000,20000) L_0x24f6c90/d; +L_0x24f6da0/d .functor AND 1, L_0x24f5f60, L_0x24f70c0, C4<1>, C4<1>; +L_0x24f6da0 .delay (20000,20000,20000) L_0x24f6da0/d; +L_0x24f6ef0/d .functor OR 1, L_0x24f6c90, L_0x24f6da0, C4<0>, C4<0>; +L_0x24f6ef0 .delay (20000,20000,20000) L_0x24f6ef0/d; +v0x242a0c0_0 .net "S", 0 0, L_0x24f70c0; 1 drivers +v0x242a140_0 .alias "in0", 0 0, v0x242a5e0_0; +v0x242a1e0_0 .alias "in1", 0 0, v0x242a660_0; +v0x242a280_0 .net "nS", 0 0, L_0x24f6bd0; 1 drivers +v0x242a300_0 .net "out0", 0 0, L_0x24f6c90; 1 drivers +v0x242a3a0_0 .net "out1", 0 0, L_0x24f6da0; 1 drivers +v0x242a480_0 .alias "outfinal", 0 0, v0x242a710_0; +S_0x24291b0 .scope generate, "andbits[28]" "andbits[28]" 2 169, 2 169, S_0x2413e60; + .timescale -9 -12; +P_0x24292a8 .param/l "i" 2 169, +C4<011100>; +S_0x2429320 .scope module, "attempt" "AndNand" 2 171, 2 48, S_0x24291b0; + .timescale -9 -12; +L_0x24f6880/d .functor NAND 1, L_0x24f72a0, L_0x24f7340, C4<1>, C4<1>; +L_0x24f6880 .delay (10000,10000,10000) L_0x24f6880/d; +L_0x24f7530/d .functor NOT 1, L_0x24f6880, C4<0>, C4<0>, C4<0>; +L_0x24f7530 .delay (10000,10000,10000) L_0x24f7530/d; +v0x2429960_0 .net "A", 0 0, L_0x24f72a0; 1 drivers +v0x2429a20_0 .net "AandB", 0 0, L_0x24f7530; 1 drivers +v0x2429aa0_0 .net "AnandB", 0 0, L_0x24f6880; 1 drivers +v0x2429b50_0 .net "AndNandOut", 0 0, L_0x24f7960; 1 drivers +v0x2429c30_0 .net "B", 0 0, L_0x24f7340; 1 drivers +v0x2429cb0_0 .alias "Command", 2 0, v0x2463430_0; +L_0x24f7b30 .part C4, 0, 1; +S_0x2429410 .scope module, "potato" "TwoInMux" 2 60, 2 8, S_0x2429320; + .timescale -9 -12; +L_0x24f7640/d .functor NOT 1, L_0x24f7b30, C4<0>, C4<0>, C4<0>; +L_0x24f7640 .delay (10000,10000,10000) L_0x24f7640/d; +L_0x24f7700/d .functor AND 1, L_0x24f7530, L_0x24f7640, C4<1>, C4<1>; +L_0x24f7700 .delay (20000,20000,20000) L_0x24f7700/d; +L_0x24f7810/d .functor AND 1, L_0x24f6880, L_0x24f7b30, C4<1>, C4<1>; +L_0x24f7810 .delay (20000,20000,20000) L_0x24f7810/d; +L_0x24f7960/d .functor OR 1, L_0x24f7700, L_0x24f7810, C4<0>, C4<0>; +L_0x24f7960 .delay (20000,20000,20000) L_0x24f7960/d; +v0x2429500_0 .net "S", 0 0, L_0x24f7b30; 1 drivers +v0x2429580_0 .alias "in0", 0 0, v0x2429a20_0; +v0x2429620_0 .alias "in1", 0 0, v0x2429aa0_0; +v0x24296c0_0 .net "nS", 0 0, L_0x24f7640; 1 drivers +v0x2429740_0 .net "out0", 0 0, L_0x24f7700; 1 drivers +v0x24297e0_0 .net "out1", 0 0, L_0x24f7810; 1 drivers +v0x24298c0_0 .alias "outfinal", 0 0, v0x2429b50_0; +S_0x24285f0 .scope generate, "andbits[29]" "andbits[29]" 2 169, 2 169, S_0x2413e60; + .timescale -9 -12; +P_0x24286e8 .param/l "i" 2 169, +C4<011101>; +S_0x2428760 .scope module, "attempt" "AndNand" 2 171, 2 48, S_0x24285f0; + .timescale -9 -12; +L_0x24f7430/d .functor NAND 1, L_0x24f86f0, L_0x24df8f0, C4<1>, C4<1>; +L_0x24f7430 .delay (10000,10000,10000) L_0x24f7430/d; +L_0x24f7fb0/d .functor NOT 1, L_0x24f7430, C4<0>, C4<0>, C4<0>; +L_0x24f7fb0 .delay (10000,10000,10000) L_0x24f7fb0/d; +v0x2428da0_0 .net "A", 0 0, L_0x24f86f0; 1 drivers +v0x2428e60_0 .net "AandB", 0 0, L_0x24f7fb0; 1 drivers +v0x2428ee0_0 .net "AnandB", 0 0, L_0x24f7430; 1 drivers +v0x2428f90_0 .net "AndNandOut", 0 0, L_0x24f83e0; 1 drivers +v0x2429070_0 .net "B", 0 0, L_0x24df8f0; 1 drivers +v0x24290f0_0 .alias "Command", 2 0, v0x2463430_0; +L_0x24f85b0 .part C4, 0, 1; +S_0x2428850 .scope module, "potato" "TwoInMux" 2 60, 2 8, S_0x2428760; + .timescale -9 -12; +L_0x24f80c0/d .functor NOT 1, L_0x24f85b0, C4<0>, C4<0>, C4<0>; +L_0x24f80c0 .delay (10000,10000,10000) L_0x24f80c0/d; +L_0x24f8180/d .functor AND 1, L_0x24f7fb0, L_0x24f80c0, C4<1>, C4<1>; +L_0x24f8180 .delay (20000,20000,20000) L_0x24f8180/d; +L_0x24f8290/d .functor AND 1, L_0x24f7430, L_0x24f85b0, C4<1>, C4<1>; +L_0x24f8290 .delay (20000,20000,20000) L_0x24f8290/d; +L_0x24f83e0/d .functor OR 1, L_0x24f8180, L_0x24f8290, C4<0>, C4<0>; +L_0x24f83e0 .delay (20000,20000,20000) L_0x24f83e0/d; +v0x2428940_0 .net "S", 0 0, L_0x24f85b0; 1 drivers +v0x24289c0_0 .alias "in0", 0 0, v0x2428e60_0; +v0x2428a60_0 .alias "in1", 0 0, v0x2428ee0_0; +v0x2428b00_0 .net "nS", 0 0, L_0x24f80c0; 1 drivers +v0x2428b80_0 .net "out0", 0 0, L_0x24f8180; 1 drivers +v0x2428c20_0 .net "out1", 0 0, L_0x24f8290; 1 drivers +v0x2428d00_0 .alias "outfinal", 0 0, v0x2428f90_0; +S_0x2427a30 .scope generate, "andbits[30]" "andbits[30]" 2 169, 2 169, S_0x2413e60; + .timescale -9 -12; +P_0x2427b28 .param/l "i" 2 169, +C4<011110>; +S_0x2427ba0 .scope module, "attempt" "AndNand" 2 171, 2 48, S_0x2427a30; + .timescale -9 -12; +L_0x24386d0/d .functor NAND 1, L_0x24df630, L_0x24df6d0, C4<1>, C4<1>; +L_0x24386d0 .delay (10000,10000,10000) L_0x24386d0/d; +L_0x24f7c70/d .functor NOT 1, L_0x24386d0, C4<0>, C4<0>, C4<0>; +L_0x24f7c70 .delay (10000,10000,10000) L_0x24f7c70/d; +v0x24281e0_0 .net "A", 0 0, L_0x24df630; 1 drivers +v0x24282a0_0 .net "AandB", 0 0, L_0x24f7c70; 1 drivers +v0x2428320_0 .net "AnandB", 0 0, L_0x24386d0; 1 drivers +v0x24283d0_0 .net "AndNandOut", 0 0, L_0x24df9e0; 1 drivers +v0x24284b0_0 .net "B", 0 0, L_0x24df6d0; 1 drivers +v0x2428530_0 .alias "Command", 2 0, v0x2463430_0; +L_0x24df430 .part C4, 0, 1; +S_0x2427c90 .scope module, "potato" "TwoInMux" 2 60, 2 8, S_0x2427ba0; + .timescale -9 -12; +L_0x24f7da0/d .functor NOT 1, L_0x24df430, C4<0>, C4<0>, C4<0>; +L_0x24f7da0 .delay (10000,10000,10000) L_0x24f7da0/d; +L_0x24f7e60/d .functor AND 1, L_0x24f7c70, L_0x24f7da0, C4<1>, C4<1>; +L_0x24f7e60 .delay (20000,20000,20000) L_0x24f7e60/d; +L_0x24df120/d .functor AND 1, L_0x24386d0, L_0x24df430, C4<1>, C4<1>; +L_0x24df120 .delay (20000,20000,20000) L_0x24df120/d; +L_0x24df9e0/d .functor OR 1, L_0x24f7e60, L_0x24df120, C4<0>, C4<0>; +L_0x24df9e0 .delay (20000,20000,20000) L_0x24df9e0/d; +v0x2427d80_0 .net "S", 0 0, L_0x24df430; 1 drivers +v0x2427e00_0 .alias "in0", 0 0, v0x24282a0_0; +v0x2427ea0_0 .alias "in1", 0 0, v0x2428320_0; +v0x2427f40_0 .net "nS", 0 0, L_0x24f7da0; 1 drivers +v0x2427fc0_0 .net "out0", 0 0, L_0x24f7e60; 1 drivers +v0x2428060_0 .net "out1", 0 0, L_0x24df120; 1 drivers +v0x2428140_0 .alias "outfinal", 0 0, v0x24283d0_0; +S_0x2426e50 .scope generate, "andbits[31]" "andbits[31]" 2 169, 2 169, S_0x2413e60; + .timescale -9 -12; +P_0x2418e68 .param/l "i" 2 169, +C4<011111>; +S_0x2426fc0 .scope module, "attempt" "AndNand" 2 171, 2 48, S_0x2426e50; + .timescale -9 -12; +L_0x24df7c0/d .functor NAND 1, L_0x24fa200, L_0x24f9850, C4<1>, C4<1>; +L_0x24df7c0 .delay (10000,10000,10000) L_0x24df7c0/d; +L_0x24f9b80/d .functor NOT 1, L_0x24df7c0, C4<0>, C4<0>, C4<0>; +L_0x24f9b80 .delay (10000,10000,10000) L_0x24f9b80/d; +v0x2427620_0 .net "A", 0 0, L_0x24fa200; 1 drivers +v0x24276e0_0 .net "AandB", 0 0, L_0x24f9b80; 1 drivers +v0x2427760_0 .net "AnandB", 0 0, L_0x24df7c0; 1 drivers +v0x2427810_0 .net "AndNandOut", 0 0, L_0x24f9f30; 1 drivers +v0x24278f0_0 .net "B", 0 0, L_0x24f9850; 1 drivers +v0x2427970_0 .alias "Command", 2 0, v0x2463430_0; +L_0x24fa0c0 .part C4, 0, 1; +S_0x24270b0 .scope module, "potato" "TwoInMux" 2 60, 2 8, S_0x2426fc0; + .timescale -9 -12; +L_0x24f9c70/d .functor NOT 1, L_0x24fa0c0, C4<0>, C4<0>, C4<0>; +L_0x24f9c70 .delay (10000,10000,10000) L_0x24f9c70/d; +L_0x24f9d10/d .functor AND 1, L_0x24f9b80, L_0x24f9c70, C4<1>, C4<1>; +L_0x24f9d10 .delay (20000,20000,20000) L_0x24f9d10/d; +L_0x24f9e00/d .functor AND 1, L_0x24df7c0, L_0x24fa0c0, C4<1>, C4<1>; +L_0x24f9e00 .delay (20000,20000,20000) L_0x24f9e00/d; +L_0x24f9f30/d .functor OR 1, L_0x24f9d10, L_0x24f9e00, C4<0>, C4<0>; +L_0x24f9f30 .delay (20000,20000,20000) L_0x24f9f30/d; +v0x24271a0_0 .net "S", 0 0, L_0x24fa0c0; 1 drivers +v0x2427240_0 .alias "in0", 0 0, v0x24276e0_0; +v0x24272e0_0 .alias "in1", 0 0, v0x2427760_0; +v0x2427380_0 .net "nS", 0 0, L_0x24f9c70; 1 drivers +v0x2427400_0 .net "out0", 0 0, L_0x24f9d10; 1 drivers +v0x24274a0_0 .net "out1", 0 0, L_0x24f9e00; 1 drivers +v0x2427580_0 .alias "outfinal", 0 0, v0x2427810_0; +S_0x23d9540 .scope module, "trial2" "OrNorXor32" 2 281, 2 177, S_0x22690e0; + .timescale -9 -12; +P_0x2386008 .param/l "size" 2 184, +C4<0100000>; +v0x24268c0_0 .alias "A", 31 0, v0x2462f10_0; +v0x2426940_0 .alias "B", 31 0, v0x24632b0_0; +v0x24269c0_0 .alias "Command", 2 0, v0x2463430_0; +v0x2413de0_0 .alias "OrNorXorOut", 31 0, v0x2463550_0; +L_0x24fbcf0 .part/pv L_0x24fbac0, 1, 1, 32; +L_0x24fbd90 .part C4, 1, 1; +L_0x24fbe30 .part C4, 1, 1; +L_0x24fcdf0 .part/pv L_0x24fcbc0, 2, 1, 32; +L_0x24fce90 .part C4, 2, 1; +L_0x24fcf30 .part C4, 2, 1; +L_0x24fdf50 .part/pv L_0x24fdd00, 3, 1, 32; +L_0x24fdff0 .part C4, 3, 1; +L_0x24fe090 .part C4, 3, 1; +L_0x24ff200 .part/pv L_0x24fefd0, 4, 1, 32; +L_0x24ff300 .part C4, 4, 1; +L_0x24ff3a0 .part C4, 4, 1; +L_0x25003e0 .part/pv L_0x2500170, 5, 1, 32; +L_0x2500480 .part C4, 5, 1; +L_0x25005a0 .part C4, 5, 1; +L_0x2501740 .part/pv L_0x25014d0, 6, 1, 32; +L_0x2501870 .part C4, 6, 1; +L_0x2501910 .part C4, 6, 1; +L_0x2502ad0 .part/pv L_0x2502860, 7, 1, 32; +L_0x2502b70 .part C4, 7, 1; +L_0x25019b0 .part C4, 7, 1; +L_0x2503dc0 .part/pv L_0x2503b50, 8, 1, 32; +L_0x2502c10 .part C4, 8, 1; +L_0x2503f20 .part C4, 8, 1; +L_0x25050d0 .part/pv L_0x2504e60, 9, 1, 32; +L_0x2505170 .part C4, 9, 1; +L_0x2503fc0 .part C4, 9, 1; +L_0x25063d0 .part/pv L_0x2506160, 10, 1, 32; +L_0x2505210 .part C4, 10, 1; +L_0x2506560 .part C4, 10, 1; +L_0x25076d0 .part/pv L_0x2507460, 11, 1, 32; +L_0x2507770 .part C4, 11, 1; +L_0x2506600 .part C4, 11, 1; +L_0x25089c0 .part/pv L_0x2508750, 12, 1, 32; +L_0x2507810 .part C4, 12, 1; +L_0x2508b80 .part C4, 12, 1; +L_0x2509ce0 .part/pv L_0x2509a70, 13, 1, 32; +L_0x2509d80 .part C4, 13, 1; +L_0x2508c20 .part C4, 13, 1; +L_0x250afe0 .part/pv L_0x250ad70, 14, 1, 32; +L_0x2509e20 .part C4, 14, 1; +L_0x2509ec0 .part C4, 14, 1; +L_0x250c2e0 .part/pv L_0x250c070, 15, 1, 32; +L_0x250c380 .part C4, 15, 1; +L_0x250b080 .part C4, 15, 1; +L_0x250d5d0 .part/pv L_0x250d360, 16, 1, 32; +L_0x250c420 .part C4, 16, 1; +L_0x250c4c0 .part C4, 16, 1; +L_0x250e8e0 .part/pv L_0x250e670, 17, 1, 32; +L_0x250e980 .part C4, 17, 1; +L_0x250d670 .part C4, 17, 1; +L_0x250fbd0 .part/pv L_0x250f960, 18, 1, 32; +L_0x250ea20 .part C4, 18, 1; +L_0x250eac0 .part C4, 18, 1; +L_0x2510ed0 .part/pv L_0x2510c60, 19, 1, 32; +L_0x2510f70 .part C4, 19, 1; +L_0x250fc70 .part C4, 19, 1; +L_0x25121d0 .part/pv L_0x2511f60, 20, 1, 32; +L_0x2511010 .part C4, 20, 1; +L_0x25110b0 .part C4, 20, 1; +L_0x25134e0 .part/pv L_0x2513270, 21, 1, 32; +L_0x2513580 .part C4, 21, 1; +L_0x2512270 .part C4, 21, 1; +L_0x25147d0 .part/pv L_0x2514560, 22, 1, 32; +L_0x2513620 .part C4, 22, 1; +L_0x25136c0 .part C4, 22, 1; +L_0x2515ad0 .part/pv L_0x2515860, 23, 1, 32; +L_0x2515b70 .part C4, 23, 1; +L_0x2514870 .part C4, 23, 1; +L_0x2516dd0 .part/pv L_0x2516b60, 24, 1, 32; +L_0x2515c10 .part C4, 24, 1; +L_0x2515cb0 .part C4, 24, 1; +L_0x25180d0 .part/pv L_0x2517e60, 25, 1, 32; +L_0x2518170 .part C4, 25, 1; +L_0x2516e70 .part C4, 25, 1; +L_0x25193e0 .part/pv L_0x2519170, 26, 1, 32; +L_0x2518210 .part C4, 26, 1; +L_0x25182b0 .part C4, 26, 1; +L_0x251a6e0 .part/pv L_0x251a470, 27, 1, 32; +L_0x251a780 .part C4, 27, 1; +L_0x2519480 .part C4, 27, 1; +L_0x251b9d0 .part/pv L_0x251b760, 28, 1, 32; +L_0x251a820 .part C4, 28, 1; +L_0x251a8c0 .part C4, 28, 1; +L_0x251cd50 .part/pv L_0x251cae0, 29, 1, 32; +L_0x251cdf0 .part C4, 29, 1; +L_0x251ba70 .part C4, 29, 1; +L_0x251e060 .part/pv L_0x251ddf0, 30, 1, 32; +L_0x251ce90 .part C4, 30, 1; +L_0x251cf30 .part C4, 30, 1; +L_0x251f370 .part/pv L_0x251f100, 31, 1, 32; +L_0x251f410 .part C4, 31, 1; +L_0x251e100 .part C4, 31, 1; +L_0x2520520 .part/pv L_0x25202f0, 0, 1, 32; +L_0x251f4b0 .part C4, 0, 1; +L_0x251f550 .part C4, 0, 1; +S_0x2425680 .scope module, "attempt2" "OrNorXor" 2 192, 2 64, S_0x23d9540; + .timescale -9 -12; +L_0x251e1a0/d .functor NOR 1, L_0x251f4b0, L_0x251f550, C4<0>, C4<0>; +L_0x251e1a0 .delay (10000,10000,10000) L_0x251e1a0/d; +L_0x251e290/d .functor NOT 1, L_0x251e1a0, C4<0>, C4<0>, C4<0>; +L_0x251e290 .delay (10000,10000,10000) L_0x251e290/d; +L_0x251f7a0/d .functor NAND 1, L_0x251f4b0, L_0x251f550, C4<1>, C4<1>; +L_0x251f7a0 .delay (10000,10000,10000) L_0x251f7a0/d; +L_0x251f8e0/d .functor NAND 1, L_0x251f7a0, L_0x251e290, C4<1>, C4<1>; +L_0x251f8e0 .delay (10000,10000,10000) L_0x251f8e0/d; +L_0x251f9f0/d .functor NOT 1, L_0x251f8e0, C4<0>, C4<0>, C4<0>; +L_0x251f9f0 .delay (10000,10000,10000) L_0x251f9f0/d; +v0x24261d0_0 .net "A", 0 0, L_0x251f4b0; 1 drivers +v0x2426270_0 .net "AnandB", 0 0, L_0x251f7a0; 1 drivers +v0x2426310_0 .net "AnorB", 0 0, L_0x251e1a0; 1 drivers +v0x24263c0_0 .net "AorB", 0 0, L_0x251e290; 1 drivers +v0x24264a0_0 .net "AxorB", 0 0, L_0x251f9f0; 1 drivers +v0x2426550_0 .net "B", 0 0, L_0x251f550; 1 drivers +v0x2426610_0 .alias "Command", 2 0, v0x2463430_0; +v0x2426690_0 .net "OrNorXorOut", 0 0, L_0x25202f0; 1 drivers +v0x2426710_0 .net "XorNor", 0 0, L_0x251fe70; 1 drivers +v0x24267e0_0 .net "nXor", 0 0, L_0x251f8e0; 1 drivers +L_0x251fff0 .part C4, 2, 1; +L_0x2520480 .part C4, 0, 1; +S_0x2425c60 .scope module, "mux0" "TwoInMux" 2 83, 2 8, S_0x2425680; + .timescale -9 -12; +L_0x251fb50/d .functor NOT 1, L_0x251fff0, C4<0>, C4<0>, C4<0>; +L_0x251fb50 .delay (10000,10000,10000) L_0x251fb50/d; +L_0x251fc10/d .functor AND 1, L_0x251f9f0, L_0x251fb50, C4<1>, C4<1>; +L_0x251fc10 .delay (20000,20000,20000) L_0x251fc10/d; +L_0x251fd20/d .functor AND 1, L_0x251e1a0, L_0x251fff0, C4<1>, C4<1>; +L_0x251fd20 .delay (20000,20000,20000) L_0x251fd20/d; +L_0x251fe70/d .functor OR 1, L_0x251fc10, L_0x251fd20, C4<0>, C4<0>; +L_0x251fe70 .delay (20000,20000,20000) L_0x251fe70/d; +v0x2425d50_0 .net "S", 0 0, L_0x251fff0; 1 drivers +v0x2425e10_0 .alias "in0", 0 0, v0x24264a0_0; +v0x2425eb0_0 .alias "in1", 0 0, v0x2426310_0; +v0x2425f50_0 .net "nS", 0 0, L_0x251fb50; 1 drivers +v0x2425fd0_0 .net "out0", 0 0, L_0x251fc10; 1 drivers +v0x2426070_0 .net "out1", 0 0, L_0x251fd20; 1 drivers +v0x2426150_0 .alias "outfinal", 0 0, v0x2426710_0; +S_0x2425770 .scope module, "mux1" "TwoInMux" 2 84, 2 8, S_0x2425680; + .timescale -9 -12; +L_0x24ff440/d .functor NOT 1, L_0x2520480, C4<0>, C4<0>, C4<0>; +L_0x24ff440 .delay (10000,10000,10000) L_0x24ff440/d; +L_0x2520090/d .functor AND 1, L_0x251fe70, L_0x24ff440, C4<1>, C4<1>; +L_0x2520090 .delay (20000,20000,20000) L_0x2520090/d; +L_0x25201c0/d .functor AND 1, L_0x251e290, L_0x2520480, C4<1>, C4<1>; +L_0x25201c0 .delay (20000,20000,20000) L_0x25201c0/d; +L_0x25202f0/d .functor OR 1, L_0x2520090, L_0x25201c0, C4<0>, C4<0>; +L_0x25202f0 .delay (20000,20000,20000) L_0x25202f0/d; +v0x2425860_0 .net "S", 0 0, L_0x2520480; 1 drivers +v0x24258e0_0 .alias "in0", 0 0, v0x2426710_0; +v0x2425960_0 .alias "in1", 0 0, v0x24263c0_0; +v0x2425a00_0 .net "nS", 0 0, L_0x24ff440; 1 drivers +v0x2425a80_0 .net "out0", 0 0, L_0x2520090; 1 drivers +v0x2425b20_0 .net "out1", 0 0, L_0x25201c0; 1 drivers +v0x2425bc0_0 .alias "outfinal", 0 0, v0x2426690_0; +S_0x24242b0 .scope generate, "orbits[1]" "orbits[1]" 2 196, 2 196, S_0x23d9540; + .timescale -9 -12; +P_0x2423fc8 .param/l "i" 2 196, +C4<01>; +S_0x24243e0 .scope module, "attempt" "OrNorXor" 2 198, 2 64, S_0x24242b0; + .timescale -9 -12; +L_0x24fa430/d .functor NOR 1, L_0x24fbd90, L_0x24fbe30, C4<0>, C4<0>; +L_0x24fa430 .delay (10000,10000,10000) L_0x24fa430/d; +L_0x24faec0/d .functor NOT 1, L_0x24fa430, C4<0>, C4<0>, C4<0>; +L_0x24faec0 .delay (10000,10000,10000) L_0x24faec0/d; +L_0x24fafb0/d .functor NAND 1, L_0x24fbd90, L_0x24fbe30, C4<1>, C4<1>; +L_0x24fafb0 .delay (10000,10000,10000) L_0x24fafb0/d; +L_0x24fb0f0/d .functor NAND 1, L_0x24fafb0, L_0x24faec0, C4<1>, C4<1>; +L_0x24fb0f0 .delay (10000,10000,10000) L_0x24fb0f0/d; +L_0x24fb1e0/d .functor NOT 1, L_0x24fb0f0, C4<0>, C4<0>, C4<0>; +L_0x24fb1e0 .delay (10000,10000,10000) L_0x24fb1e0/d; +v0x2424f90_0 .net "A", 0 0, L_0x24fbd90; 1 drivers +v0x2425030_0 .net "AnandB", 0 0, L_0x24fafb0; 1 drivers +v0x24250d0_0 .net "AnorB", 0 0, L_0x24fa430; 1 drivers +v0x2425180_0 .net "AorB", 0 0, L_0x24faec0; 1 drivers +v0x2425260_0 .net "AxorB", 0 0, L_0x24fb1e0; 1 drivers +v0x2425310_0 .net "B", 0 0, L_0x24fbe30; 1 drivers +v0x24253d0_0 .alias "Command", 2 0, v0x2463430_0; +v0x2425450_0 .net "OrNorXorOut", 0 0, L_0x24fbac0; 1 drivers +v0x24254d0_0 .net "XorNor", 0 0, L_0x24fb5e0; 1 drivers +v0x24255a0_0 .net "nXor", 0 0, L_0x24fb0f0; 1 drivers +L_0x24fb720 .part C4, 2, 1; +L_0x24fbc50 .part C4, 0, 1; +S_0x2424a20 .scope module, "mux0" "TwoInMux" 2 83, 2 8, S_0x24243e0; + .timescale -9 -12; +L_0x24fb320/d .functor NOT 1, L_0x24fb720, C4<0>, C4<0>, C4<0>; +L_0x24fb320 .delay (10000,10000,10000) L_0x24fb320/d; +L_0x24fb3c0/d .functor AND 1, L_0x24fb1e0, L_0x24fb320, C4<1>, C4<1>; +L_0x24fb3c0 .delay (20000,20000,20000) L_0x24fb3c0/d; +L_0x24fb4b0/d .functor AND 1, L_0x24fa430, L_0x24fb720, C4<1>, C4<1>; +L_0x24fb4b0 .delay (20000,20000,20000) L_0x24fb4b0/d; +L_0x24fb5e0/d .functor OR 1, L_0x24fb3c0, L_0x24fb4b0, C4<0>, C4<0>; +L_0x24fb5e0 .delay (20000,20000,20000) L_0x24fb5e0/d; +v0x2424b10_0 .net "S", 0 0, L_0x24fb720; 1 drivers +v0x2424bd0_0 .alias "in0", 0 0, v0x2425260_0; +v0x2424c70_0 .alias "in1", 0 0, v0x24250d0_0; +v0x2424d10_0 .net "nS", 0 0, L_0x24fb320; 1 drivers +v0x2424d90_0 .net "out0", 0 0, L_0x24fb3c0; 1 drivers +v0x2424e30_0 .net "out1", 0 0, L_0x24fb4b0; 1 drivers +v0x2424f10_0 .alias "outfinal", 0 0, v0x24254d0_0; +S_0x24244d0 .scope module, "mux1" "TwoInMux" 2 84, 2 8, S_0x24243e0; + .timescale -9 -12; +L_0x24fb7c0/d .functor NOT 1, L_0x24fbc50, C4<0>, C4<0>, C4<0>; +L_0x24fb7c0 .delay (10000,10000,10000) L_0x24fb7c0/d; +L_0x24fb860/d .functor AND 1, L_0x24fb5e0, L_0x24fb7c0, C4<1>, C4<1>; +L_0x24fb860 .delay (20000,20000,20000) L_0x24fb860/d; +L_0x24fb990/d .functor AND 1, L_0x24faec0, L_0x24fbc50, C4<1>, C4<1>; +L_0x24fb990 .delay (20000,20000,20000) L_0x24fb990/d; +L_0x24fbac0/d .functor OR 1, L_0x24fb860, L_0x24fb990, C4<0>, C4<0>; +L_0x24fbac0 .delay (20000,20000,20000) L_0x24fbac0/d; +v0x24245c0_0 .net "S", 0 0, L_0x24fbc50; 1 drivers +v0x2424640_0 .alias "in0", 0 0, v0x24254d0_0; +v0x24246e0_0 .alias "in1", 0 0, v0x2425180_0; +v0x2424780_0 .net "nS", 0 0, L_0x24fb7c0; 1 drivers +v0x2424800_0 .net "out0", 0 0, L_0x24fb860; 1 drivers +v0x24248a0_0 .net "out1", 0 0, L_0x24fb990; 1 drivers +v0x2424980_0 .alias "outfinal", 0 0, v0x2425450_0; +S_0x2422ee0 .scope generate, "orbits[2]" "orbits[2]" 2 196, 2 196, S_0x23d9540; + .timescale -9 -12; +P_0x2422bf8 .param/l "i" 2 196, +C4<010>; +S_0x2423010 .scope module, "attempt" "OrNorXor" 2 198, 2 64, S_0x2422ee0; + .timescale -9 -12; +L_0x24fbed0/d .functor NOR 1, L_0x24fce90, L_0x24fcf30, C4<0>, C4<0>; +L_0x24fbed0 .delay (10000,10000,10000) L_0x24fbed0/d; +L_0x24fbfc0/d .functor NOT 1, L_0x24fbed0, C4<0>, C4<0>, C4<0>; +L_0x24fbfc0 .delay (10000,10000,10000) L_0x24fbfc0/d; +L_0x24fc0b0/d .functor NAND 1, L_0x24fce90, L_0x24fcf30, C4<1>, C4<1>; +L_0x24fc0b0 .delay (10000,10000,10000) L_0x24fc0b0/d; +L_0x24fc1f0/d .functor NAND 1, L_0x24fc0b0, L_0x24fbfc0, C4<1>, C4<1>; +L_0x24fc1f0 .delay (10000,10000,10000) L_0x24fc1f0/d; +L_0x24fc2e0/d .functor NOT 1, L_0x24fc1f0, C4<0>, C4<0>, C4<0>; +L_0x24fc2e0 .delay (10000,10000,10000) L_0x24fc2e0/d; +v0x2423bc0_0 .net "A", 0 0, L_0x24fce90; 1 drivers +v0x2423c60_0 .net "AnandB", 0 0, L_0x24fc0b0; 1 drivers +v0x2423d00_0 .net "AnorB", 0 0, L_0x24fbed0; 1 drivers +v0x2423db0_0 .net "AorB", 0 0, L_0x24fbfc0; 1 drivers +v0x2423e90_0 .net "AxorB", 0 0, L_0x24fc2e0; 1 drivers +v0x2423f40_0 .net "B", 0 0, L_0x24fcf30; 1 drivers +v0x2424000_0 .alias "Command", 2 0, v0x2463430_0; +v0x2424080_0 .net "OrNorXorOut", 0 0, L_0x24fcbc0; 1 drivers +v0x2424100_0 .net "XorNor", 0 0, L_0x24fc6e0; 1 drivers +v0x24241d0_0 .net "nXor", 0 0, L_0x24fc1f0; 1 drivers +L_0x24fc820 .part C4, 2, 1; +L_0x24fcd50 .part C4, 0, 1; +S_0x2423650 .scope module, "mux0" "TwoInMux" 2 83, 2 8, S_0x2423010; + .timescale -9 -12; +L_0x24fc420/d .functor NOT 1, L_0x24fc820, C4<0>, C4<0>, C4<0>; +L_0x24fc420 .delay (10000,10000,10000) L_0x24fc420/d; +L_0x24fc4c0/d .functor AND 1, L_0x24fc2e0, L_0x24fc420, C4<1>, C4<1>; +L_0x24fc4c0 .delay (20000,20000,20000) L_0x24fc4c0/d; +L_0x24fc5b0/d .functor AND 1, L_0x24fbed0, L_0x24fc820, C4<1>, C4<1>; +L_0x24fc5b0 .delay (20000,20000,20000) L_0x24fc5b0/d; +L_0x24fc6e0/d .functor OR 1, L_0x24fc4c0, L_0x24fc5b0, C4<0>, C4<0>; +L_0x24fc6e0 .delay (20000,20000,20000) L_0x24fc6e0/d; +v0x2423740_0 .net "S", 0 0, L_0x24fc820; 1 drivers +v0x2423800_0 .alias "in0", 0 0, v0x2423e90_0; +v0x24238a0_0 .alias "in1", 0 0, v0x2423d00_0; +v0x2423940_0 .net "nS", 0 0, L_0x24fc420; 1 drivers +v0x24239c0_0 .net "out0", 0 0, L_0x24fc4c0; 1 drivers +v0x2423a60_0 .net "out1", 0 0, L_0x24fc5b0; 1 drivers +v0x2423b40_0 .alias "outfinal", 0 0, v0x2424100_0; +S_0x2423100 .scope module, "mux1" "TwoInMux" 2 84, 2 8, S_0x2423010; + .timescale -9 -12; +L_0x24fc8c0/d .functor NOT 1, L_0x24fcd50, C4<0>, C4<0>, C4<0>; +L_0x24fc8c0 .delay (10000,10000,10000) L_0x24fc8c0/d; +L_0x24fc960/d .functor AND 1, L_0x24fc6e0, L_0x24fc8c0, C4<1>, C4<1>; +L_0x24fc960 .delay (20000,20000,20000) L_0x24fc960/d; +L_0x24fca90/d .functor AND 1, L_0x24fbfc0, L_0x24fcd50, C4<1>, C4<1>; +L_0x24fca90 .delay (20000,20000,20000) L_0x24fca90/d; +L_0x24fcbc0/d .functor OR 1, L_0x24fc960, L_0x24fca90, C4<0>, C4<0>; +L_0x24fcbc0 .delay (20000,20000,20000) L_0x24fcbc0/d; +v0x24231f0_0 .net "S", 0 0, L_0x24fcd50; 1 drivers +v0x2423270_0 .alias "in0", 0 0, v0x2424100_0; +v0x2423310_0 .alias "in1", 0 0, v0x2423db0_0; +v0x24233b0_0 .net "nS", 0 0, L_0x24fc8c0; 1 drivers +v0x2423430_0 .net "out0", 0 0, L_0x24fc960; 1 drivers +v0x24234d0_0 .net "out1", 0 0, L_0x24fca90; 1 drivers +v0x24235b0_0 .alias "outfinal", 0 0, v0x2424080_0; +S_0x2421b10 .scope generate, "orbits[3]" "orbits[3]" 2 196, 2 196, S_0x23d9540; + .timescale -9 -12; +P_0x2421828 .param/l "i" 2 196, +C4<011>; +S_0x2421c40 .scope module, "attempt" "OrNorXor" 2 198, 2 64, S_0x2421b10; + .timescale -9 -12; +L_0x24fd010/d .functor NOR 1, L_0x24fdff0, L_0x24fe090, C4<0>, C4<0>; +L_0x24fd010 .delay (10000,10000,10000) L_0x24fd010/d; +L_0x24fd100/d .functor NOT 1, L_0x24fd010, C4<0>, C4<0>, C4<0>; +L_0x24fd100 .delay (10000,10000,10000) L_0x24fd100/d; +L_0x24fd1f0/d .functor NAND 1, L_0x24fdff0, L_0x24fe090, C4<1>, C4<1>; +L_0x24fd1f0 .delay (10000,10000,10000) L_0x24fd1f0/d; +L_0x24fd330/d .functor NAND 1, L_0x24fd1f0, L_0x24fd100, C4<1>, C4<1>; +L_0x24fd330 .delay (10000,10000,10000) L_0x24fd330/d; +L_0x24fd420/d .functor NOT 1, L_0x24fd330, C4<0>, C4<0>, C4<0>; +L_0x24fd420 .delay (10000,10000,10000) L_0x24fd420/d; +v0x24227f0_0 .net "A", 0 0, L_0x24fdff0; 1 drivers +v0x2422890_0 .net "AnandB", 0 0, L_0x24fd1f0; 1 drivers +v0x2422930_0 .net "AnorB", 0 0, L_0x24fd010; 1 drivers +v0x24229e0_0 .net "AorB", 0 0, L_0x24fd100; 1 drivers +v0x2422ac0_0 .net "AxorB", 0 0, L_0x24fd420; 1 drivers +v0x2422b70_0 .net "B", 0 0, L_0x24fe090; 1 drivers +v0x2422c30_0 .alias "Command", 2 0, v0x2463430_0; +v0x2422cb0_0 .net "OrNorXorOut", 0 0, L_0x24fdd00; 1 drivers +v0x2422d30_0 .net "XorNor", 0 0, L_0x24fd820; 1 drivers +v0x2422e00_0 .net "nXor", 0 0, L_0x24fd330; 1 drivers +L_0x24fd960 .part C4, 2, 1; +L_0x24fdeb0 .part C4, 0, 1; +S_0x2422280 .scope module, "mux0" "TwoInMux" 2 83, 2 8, S_0x2421c40; + .timescale -9 -12; +L_0x24fd560/d .functor NOT 1, L_0x24fd960, C4<0>, C4<0>, C4<0>; +L_0x24fd560 .delay (10000,10000,10000) L_0x24fd560/d; +L_0x24fd600/d .functor AND 1, L_0x24fd420, L_0x24fd560, C4<1>, C4<1>; +L_0x24fd600 .delay (20000,20000,20000) L_0x24fd600/d; +L_0x24fd6f0/d .functor AND 1, L_0x24fd010, L_0x24fd960, C4<1>, C4<1>; +L_0x24fd6f0 .delay (20000,20000,20000) L_0x24fd6f0/d; +L_0x24fd820/d .functor OR 1, L_0x24fd600, L_0x24fd6f0, C4<0>, C4<0>; +L_0x24fd820 .delay (20000,20000,20000) L_0x24fd820/d; +v0x2422370_0 .net "S", 0 0, L_0x24fd960; 1 drivers +v0x2422430_0 .alias "in0", 0 0, v0x2422ac0_0; +v0x24224d0_0 .alias "in1", 0 0, v0x2422930_0; +v0x2422570_0 .net "nS", 0 0, L_0x24fd560; 1 drivers +v0x24225f0_0 .net "out0", 0 0, L_0x24fd600; 1 drivers +v0x2422690_0 .net "out1", 0 0, L_0x24fd6f0; 1 drivers +v0x2422770_0 .alias "outfinal", 0 0, v0x2422d30_0; +S_0x2421d30 .scope module, "mux1" "TwoInMux" 2 84, 2 8, S_0x2421c40; + .timescale -9 -12; +L_0x24fda00/d .functor NOT 1, L_0x24fdeb0, C4<0>, C4<0>, C4<0>; +L_0x24fda00 .delay (10000,10000,10000) L_0x24fda00/d; +L_0x24fdaa0/d .functor AND 1, L_0x24fd820, L_0x24fda00, C4<1>, C4<1>; +L_0x24fdaa0 .delay (20000,20000,20000) L_0x24fdaa0/d; +L_0x24fdbd0/d .functor AND 1, L_0x24fd100, L_0x24fdeb0, C4<1>, C4<1>; +L_0x24fdbd0 .delay (20000,20000,20000) L_0x24fdbd0/d; +L_0x24fdd00/d .functor OR 1, L_0x24fdaa0, L_0x24fdbd0, C4<0>, C4<0>; +L_0x24fdd00 .delay (20000,20000,20000) L_0x24fdd00/d; +v0x2421e20_0 .net "S", 0 0, L_0x24fdeb0; 1 drivers +v0x2421ea0_0 .alias "in0", 0 0, v0x2422d30_0; +v0x2421f40_0 .alias "in1", 0 0, v0x24229e0_0; +v0x2421fe0_0 .net "nS", 0 0, L_0x24fda00; 1 drivers +v0x2422060_0 .net "out0", 0 0, L_0x24fdaa0; 1 drivers +v0x2422100_0 .net "out1", 0 0, L_0x24fdbd0; 1 drivers +v0x24221e0_0 .alias "outfinal", 0 0, v0x2422cb0_0; +S_0x2420740 .scope generate, "orbits[4]" "orbits[4]" 2 196, 2 196, S_0x23d9540; + .timescale -9 -12; +P_0x2420458 .param/l "i" 2 196, +C4<0100>; +S_0x2420870 .scope module, "attempt" "OrNorXor" 2 198, 2 64, S_0x2420740; + .timescale -9 -12; +L_0x24fe130/d .functor NOR 1, L_0x24ff300, L_0x24ff3a0, C4<0>, C4<0>; +L_0x24fe130 .delay (10000,10000,10000) L_0x24fe130/d; +L_0x24fe230/d .functor NOT 1, L_0x24fe130, C4<0>, C4<0>, C4<0>; +L_0x24fe230 .delay (10000,10000,10000) L_0x24fe230/d; +L_0x24fe360/d .functor NAND 1, L_0x24ff300, L_0x24ff3a0, C4<1>, C4<1>; +L_0x24fe360 .delay (10000,10000,10000) L_0x24fe360/d; +L_0x24fe4c0/d .functor NAND 1, L_0x24fe360, L_0x24fe230, C4<1>, C4<1>; +L_0x24fe4c0 .delay (10000,10000,10000) L_0x24fe4c0/d; +L_0x24fe5d0/d .functor NOT 1, L_0x24fe4c0, C4<0>, C4<0>, C4<0>; +L_0x24fe5d0 .delay (10000,10000,10000) L_0x24fe5d0/d; +v0x2421420_0 .net "A", 0 0, L_0x24ff300; 1 drivers +v0x24214c0_0 .net "AnandB", 0 0, L_0x24fe360; 1 drivers +v0x2421560_0 .net "AnorB", 0 0, L_0x24fe130; 1 drivers +v0x2421610_0 .net "AorB", 0 0, L_0x24fe230; 1 drivers +v0x24216f0_0 .net "AxorB", 0 0, L_0x24fe5d0; 1 drivers +v0x24217a0_0 .net "B", 0 0, L_0x24ff3a0; 1 drivers +v0x2421860_0 .alias "Command", 2 0, v0x2463430_0; +v0x24218e0_0 .net "OrNorXorOut", 0 0, L_0x24fefd0; 1 drivers +v0x2421960_0 .net "XorNor", 0 0, L_0x24fea50; 1 drivers +v0x2421a30_0 .net "nXor", 0 0, L_0x24fe4c0; 1 drivers +L_0x24febd0 .part C4, 2, 1; +L_0x24ff160 .part C4, 0, 1; +S_0x2420eb0 .scope module, "mux0" "TwoInMux" 2 83, 2 8, S_0x2420870; + .timescale -9 -12; +L_0x24fe730/d .functor NOT 1, L_0x24febd0, C4<0>, C4<0>, C4<0>; +L_0x24fe730 .delay (10000,10000,10000) L_0x24fe730/d; +L_0x24fe7f0/d .functor AND 1, L_0x24fe5d0, L_0x24fe730, C4<1>, C4<1>; +L_0x24fe7f0 .delay (20000,20000,20000) L_0x24fe7f0/d; +L_0x24fe900/d .functor AND 1, L_0x24fe130, L_0x24febd0, C4<1>, C4<1>; +L_0x24fe900 .delay (20000,20000,20000) L_0x24fe900/d; +L_0x24fea50/d .functor OR 1, L_0x24fe7f0, L_0x24fe900, C4<0>, C4<0>; +L_0x24fea50 .delay (20000,20000,20000) L_0x24fea50/d; +v0x2420fa0_0 .net "S", 0 0, L_0x24febd0; 1 drivers +v0x2421060_0 .alias "in0", 0 0, v0x24216f0_0; +v0x2421100_0 .alias "in1", 0 0, v0x2421560_0; +v0x24211a0_0 .net "nS", 0 0, L_0x24fe730; 1 drivers +v0x2421220_0 .net "out0", 0 0, L_0x24fe7f0; 1 drivers +v0x24212c0_0 .net "out1", 0 0, L_0x24fe900; 1 drivers +v0x24213a0_0 .alias "outfinal", 0 0, v0x2421960_0; +S_0x2420960 .scope module, "mux1" "TwoInMux" 2 84, 2 8, S_0x2420870; + .timescale -9 -12; +L_0x24fec70/d .functor NOT 1, L_0x24ff160, C4<0>, C4<0>, C4<0>; +L_0x24fec70 .delay (10000,10000,10000) L_0x24fec70/d; +L_0x24fed30/d .functor AND 1, L_0x24fea50, L_0x24fec70, C4<1>, C4<1>; +L_0x24fed30 .delay (20000,20000,20000) L_0x24fed30/d; +L_0x24fee80/d .functor AND 1, L_0x24fe230, L_0x24ff160, C4<1>, C4<1>; +L_0x24fee80 .delay (20000,20000,20000) L_0x24fee80/d; +L_0x24fefd0/d .functor OR 1, L_0x24fed30, L_0x24fee80, C4<0>, C4<0>; +L_0x24fefd0 .delay (20000,20000,20000) L_0x24fefd0/d; +v0x2420a50_0 .net "S", 0 0, L_0x24ff160; 1 drivers +v0x2420ad0_0 .alias "in0", 0 0, v0x2421960_0; +v0x2420b70_0 .alias "in1", 0 0, v0x2421610_0; +v0x2420c10_0 .net "nS", 0 0, L_0x24fec70; 1 drivers +v0x2420c90_0 .net "out0", 0 0, L_0x24fed30; 1 drivers +v0x2420d30_0 .net "out1", 0 0, L_0x24fee80; 1 drivers +v0x2420e10_0 .alias "outfinal", 0 0, v0x24218e0_0; +S_0x241f370 .scope generate, "orbits[5]" "orbits[5]" 2 196, 2 196, S_0x23d9540; + .timescale -9 -12; +P_0x241f088 .param/l "i" 2 196, +C4<0101>; +S_0x241f4a0 .scope module, "attempt" "OrNorXor" 2 198, 2 64, S_0x241f370; + .timescale -9 -12; +L_0x24ff2a0/d .functor NOR 1, L_0x2500480, L_0x25005a0, C4<0>, C4<0>; +L_0x24ff2a0 .delay (10000,10000,10000) L_0x24ff2a0/d; +L_0x24ff4f0/d .functor NOT 1, L_0x24ff2a0, C4<0>, C4<0>, C4<0>; +L_0x24ff4f0 .delay (10000,10000,10000) L_0x24ff4f0/d; +L_0x24ff5e0/d .functor NAND 1, L_0x2500480, L_0x25005a0, C4<1>, C4<1>; +L_0x24ff5e0 .delay (10000,10000,10000) L_0x24ff5e0/d; +L_0x24ff720/d .functor NAND 1, L_0x24ff5e0, L_0x24ff4f0, C4<1>, C4<1>; +L_0x24ff720 .delay (10000,10000,10000) L_0x24ff720/d; +L_0x24ff810/d .functor NOT 1, L_0x24ff720, C4<0>, C4<0>, C4<0>; +L_0x24ff810 .delay (10000,10000,10000) L_0x24ff810/d; +v0x2420050_0 .net "A", 0 0, L_0x2500480; 1 drivers +v0x24200f0_0 .net "AnandB", 0 0, L_0x24ff5e0; 1 drivers +v0x2420190_0 .net "AnorB", 0 0, L_0x24ff2a0; 1 drivers +v0x2420240_0 .net "AorB", 0 0, L_0x24ff4f0; 1 drivers +v0x2420320_0 .net "AxorB", 0 0, L_0x24ff810; 1 drivers +v0x24203d0_0 .net "B", 0 0, L_0x25005a0; 1 drivers +v0x2420490_0 .alias "Command", 2 0, v0x2463430_0; +v0x2420510_0 .net "OrNorXorOut", 0 0, L_0x2500170; 1 drivers +v0x2420590_0 .net "XorNor", 0 0, L_0x24ffc10; 1 drivers +v0x2420660_0 .net "nXor", 0 0, L_0x24ff720; 1 drivers +L_0x24ffd70 .part C4, 2, 1; +L_0x2500340 .part C4, 0, 1; +S_0x241fae0 .scope module, "mux0" "TwoInMux" 2 83, 2 8, S_0x241f4a0; + .timescale -9 -12; +L_0x24ff950/d .functor NOT 1, L_0x24ffd70, C4<0>, C4<0>, C4<0>; +L_0x24ff950 .delay (10000,10000,10000) L_0x24ff950/d; +L_0x24ff9f0/d .functor AND 1, L_0x24ff810, L_0x24ff950, C4<1>, C4<1>; +L_0x24ff9f0 .delay (20000,20000,20000) L_0x24ff9f0/d; +L_0x24ffae0/d .functor AND 1, L_0x24ff2a0, L_0x24ffd70, C4<1>, C4<1>; +L_0x24ffae0 .delay (20000,20000,20000) L_0x24ffae0/d; +L_0x24ffc10/d .functor OR 1, L_0x24ff9f0, L_0x24ffae0, C4<0>, C4<0>; +L_0x24ffc10 .delay (20000,20000,20000) L_0x24ffc10/d; +v0x241fbd0_0 .net "S", 0 0, L_0x24ffd70; 1 drivers +v0x241fc90_0 .alias "in0", 0 0, v0x2420320_0; +v0x241fd30_0 .alias "in1", 0 0, v0x2420190_0; +v0x241fdd0_0 .net "nS", 0 0, L_0x24ff950; 1 drivers +v0x241fe50_0 .net "out0", 0 0, L_0x24ff9f0; 1 drivers +v0x241fef0_0 .net "out1", 0 0, L_0x24ffae0; 1 drivers +v0x241ffd0_0 .alias "outfinal", 0 0, v0x2420590_0; +S_0x241f590 .scope module, "mux1" "TwoInMux" 2 84, 2 8, S_0x241f4a0; + .timescale -9 -12; +L_0x24ffe10/d .functor NOT 1, L_0x2500340, C4<0>, C4<0>, C4<0>; +L_0x24ffe10 .delay (10000,10000,10000) L_0x24ffe10/d; +L_0x24ffed0/d .functor AND 1, L_0x24ffc10, L_0x24ffe10, C4<1>, C4<1>; +L_0x24ffed0 .delay (20000,20000,20000) L_0x24ffed0/d; +L_0x2500020/d .functor AND 1, L_0x24ff4f0, L_0x2500340, C4<1>, C4<1>; +L_0x2500020 .delay (20000,20000,20000) L_0x2500020/d; +L_0x2500170/d .functor OR 1, L_0x24ffed0, L_0x2500020, C4<0>, C4<0>; +L_0x2500170 .delay (20000,20000,20000) L_0x2500170/d; +v0x241f680_0 .net "S", 0 0, L_0x2500340; 1 drivers +v0x241f700_0 .alias "in0", 0 0, v0x2420590_0; +v0x241f7a0_0 .alias "in1", 0 0, v0x2420240_0; +v0x241f840_0 .net "nS", 0 0, L_0x24ffe10; 1 drivers +v0x241f8c0_0 .net "out0", 0 0, L_0x24ffed0; 1 drivers +v0x241f960_0 .net "out1", 0 0, L_0x2500020; 1 drivers +v0x241fa40_0 .alias "outfinal", 0 0, v0x2420510_0; +S_0x241dfa0 .scope generate, "orbits[6]" "orbits[6]" 2 196, 2 196, S_0x23d9540; + .timescale -9 -12; +P_0x241dcb8 .param/l "i" 2 196, +C4<0110>; +S_0x241e0d0 .scope module, "attempt" "OrNorXor" 2 198, 2 64, S_0x241dfa0; + .timescale -9 -12; +L_0x2500640/d .functor NOR 1, L_0x2501870, L_0x2501910, C4<0>, C4<0>; +L_0x2500640 .delay (10000,10000,10000) L_0x2500640/d; +L_0x2500730/d .functor NOT 1, L_0x2500640, C4<0>, C4<0>, C4<0>; +L_0x2500730 .delay (10000,10000,10000) L_0x2500730/d; +L_0x2500860/d .functor NAND 1, L_0x2501870, L_0x2501910, C4<1>, C4<1>; +L_0x2500860 .delay (10000,10000,10000) L_0x2500860/d; +L_0x25009c0/d .functor NAND 1, L_0x2500860, L_0x2500730, C4<1>, C4<1>; +L_0x25009c0 .delay (10000,10000,10000) L_0x25009c0/d; +L_0x2500ad0/d .functor NOT 1, L_0x25009c0, C4<0>, C4<0>, C4<0>; +L_0x2500ad0 .delay (10000,10000,10000) L_0x2500ad0/d; +v0x241ec80_0 .net "A", 0 0, L_0x2501870; 1 drivers +v0x241ed20_0 .net "AnandB", 0 0, L_0x2500860; 1 drivers +v0x241edc0_0 .net "AnorB", 0 0, L_0x2500640; 1 drivers +v0x241ee70_0 .net "AorB", 0 0, L_0x2500730; 1 drivers +v0x241ef50_0 .net "AxorB", 0 0, L_0x2500ad0; 1 drivers +v0x241f000_0 .net "B", 0 0, L_0x2501910; 1 drivers +v0x241f0c0_0 .alias "Command", 2 0, v0x2463430_0; +v0x241f140_0 .net "OrNorXorOut", 0 0, L_0x25014d0; 1 drivers +v0x241f1c0_0 .net "XorNor", 0 0, L_0x2500f50; 1 drivers +v0x241f290_0 .net "nXor", 0 0, L_0x25009c0; 1 drivers +L_0x25010d0 .part C4, 2, 1; +L_0x25016a0 .part C4, 0, 1; +S_0x241e710 .scope module, "mux0" "TwoInMux" 2 83, 2 8, S_0x241e0d0; + .timescale -9 -12; +L_0x2500c30/d .functor NOT 1, L_0x25010d0, C4<0>, C4<0>, C4<0>; +L_0x2500c30 .delay (10000,10000,10000) L_0x2500c30/d; +L_0x2500cf0/d .functor AND 1, L_0x2500ad0, L_0x2500c30, C4<1>, C4<1>; +L_0x2500cf0 .delay (20000,20000,20000) L_0x2500cf0/d; +L_0x2500e00/d .functor AND 1, L_0x2500640, L_0x25010d0, C4<1>, C4<1>; +L_0x2500e00 .delay (20000,20000,20000) L_0x2500e00/d; +L_0x2500f50/d .functor OR 1, L_0x2500cf0, L_0x2500e00, C4<0>, C4<0>; +L_0x2500f50 .delay (20000,20000,20000) L_0x2500f50/d; +v0x241e800_0 .net "S", 0 0, L_0x25010d0; 1 drivers +v0x241e8c0_0 .alias "in0", 0 0, v0x241ef50_0; +v0x241e960_0 .alias "in1", 0 0, v0x241edc0_0; +v0x241ea00_0 .net "nS", 0 0, L_0x2500c30; 1 drivers +v0x241ea80_0 .net "out0", 0 0, L_0x2500cf0; 1 drivers +v0x241eb20_0 .net "out1", 0 0, L_0x2500e00; 1 drivers +v0x241ec00_0 .alias "outfinal", 0 0, v0x241f1c0_0; +S_0x241e1c0 .scope module, "mux1" "TwoInMux" 2 84, 2 8, S_0x241e0d0; + .timescale -9 -12; +L_0x2501170/d .functor NOT 1, L_0x25016a0, C4<0>, C4<0>, C4<0>; +L_0x2501170 .delay (10000,10000,10000) L_0x2501170/d; +L_0x2501230/d .functor AND 1, L_0x2500f50, L_0x2501170, C4<1>, C4<1>; +L_0x2501230 .delay (20000,20000,20000) L_0x2501230/d; +L_0x2501380/d .functor AND 1, L_0x2500730, L_0x25016a0, C4<1>, C4<1>; +L_0x2501380 .delay (20000,20000,20000) L_0x2501380/d; +L_0x25014d0/d .functor OR 1, L_0x2501230, L_0x2501380, C4<0>, C4<0>; +L_0x25014d0 .delay (20000,20000,20000) L_0x25014d0/d; +v0x241e2b0_0 .net "S", 0 0, L_0x25016a0; 1 drivers +v0x241e330_0 .alias "in0", 0 0, v0x241f1c0_0; +v0x241e3d0_0 .alias "in1", 0 0, v0x241ee70_0; +v0x241e470_0 .net "nS", 0 0, L_0x2501170; 1 drivers +v0x241e4f0_0 .net "out0", 0 0, L_0x2501230; 1 drivers +v0x241e590_0 .net "out1", 0 0, L_0x2501380; 1 drivers +v0x241e670_0 .alias "outfinal", 0 0, v0x241f140_0; +S_0x241cbd0 .scope generate, "orbits[7]" "orbits[7]" 2 196, 2 196, S_0x23d9540; + .timescale -9 -12; +P_0x241c8e8 .param/l "i" 2 196, +C4<0111>; +S_0x241cd00 .scope module, "attempt" "OrNorXor" 2 198, 2 64, S_0x241cbd0; + .timescale -9 -12; +L_0x25017e0/d .functor NOR 1, L_0x2502b70, L_0x25019b0, C4<0>, C4<0>; +L_0x25017e0 .delay (10000,10000,10000) L_0x25017e0/d; +L_0x2501ae0/d .functor NOT 1, L_0x25017e0, C4<0>, C4<0>, C4<0>; +L_0x2501ae0 .delay (10000,10000,10000) L_0x2501ae0/d; +L_0x2501bf0/d .functor NAND 1, L_0x2502b70, L_0x25019b0, C4<1>, C4<1>; +L_0x2501bf0 .delay (10000,10000,10000) L_0x2501bf0/d; +L_0x2501d50/d .functor NAND 1, L_0x2501bf0, L_0x2501ae0, C4<1>, C4<1>; +L_0x2501d50 .delay (10000,10000,10000) L_0x2501d50/d; +L_0x2501e60/d .functor NOT 1, L_0x2501d50, C4<0>, C4<0>, C4<0>; +L_0x2501e60 .delay (10000,10000,10000) L_0x2501e60/d; +v0x241d8b0_0 .net "A", 0 0, L_0x2502b70; 1 drivers +v0x241d950_0 .net "AnandB", 0 0, L_0x2501bf0; 1 drivers +v0x241d9f0_0 .net "AnorB", 0 0, L_0x25017e0; 1 drivers +v0x241daa0_0 .net "AorB", 0 0, L_0x2501ae0; 1 drivers +v0x241db80_0 .net "AxorB", 0 0, L_0x2501e60; 1 drivers +v0x241dc30_0 .net "B", 0 0, L_0x25019b0; 1 drivers +v0x241dcf0_0 .alias "Command", 2 0, v0x2463430_0; +v0x241dd70_0 .net "OrNorXorOut", 0 0, L_0x2502860; 1 drivers +v0x241ddf0_0 .net "XorNor", 0 0, L_0x25022e0; 1 drivers +v0x241dec0_0 .net "nXor", 0 0, L_0x2501d50; 1 drivers +L_0x2502460 .part C4, 2, 1; +L_0x2502a30 .part C4, 0, 1; +S_0x241d340 .scope module, "mux0" "TwoInMux" 2 83, 2 8, S_0x241cd00; + .timescale -9 -12; +L_0x2501fc0/d .functor NOT 1, L_0x2502460, C4<0>, C4<0>, C4<0>; +L_0x2501fc0 .delay (10000,10000,10000) L_0x2501fc0/d; +L_0x2502080/d .functor AND 1, L_0x2501e60, L_0x2501fc0, C4<1>, C4<1>; +L_0x2502080 .delay (20000,20000,20000) L_0x2502080/d; +L_0x2502190/d .functor AND 1, L_0x25017e0, L_0x2502460, C4<1>, C4<1>; +L_0x2502190 .delay (20000,20000,20000) L_0x2502190/d; +L_0x25022e0/d .functor OR 1, L_0x2502080, L_0x2502190, C4<0>, C4<0>; +L_0x25022e0 .delay (20000,20000,20000) L_0x25022e0/d; +v0x241d430_0 .net "S", 0 0, L_0x2502460; 1 drivers +v0x241d4f0_0 .alias "in0", 0 0, v0x241db80_0; +v0x241d590_0 .alias "in1", 0 0, v0x241d9f0_0; +v0x241d630_0 .net "nS", 0 0, L_0x2501fc0; 1 drivers +v0x241d6b0_0 .net "out0", 0 0, L_0x2502080; 1 drivers +v0x241d750_0 .net "out1", 0 0, L_0x2502190; 1 drivers +v0x241d830_0 .alias "outfinal", 0 0, v0x241ddf0_0; +S_0x241cdf0 .scope module, "mux1" "TwoInMux" 2 84, 2 8, S_0x241cd00; + .timescale -9 -12; +L_0x2502500/d .functor NOT 1, L_0x2502a30, C4<0>, C4<0>, C4<0>; +L_0x2502500 .delay (10000,10000,10000) L_0x2502500/d; +L_0x25025c0/d .functor AND 1, L_0x25022e0, L_0x2502500, C4<1>, C4<1>; +L_0x25025c0 .delay (20000,20000,20000) L_0x25025c0/d; +L_0x2502710/d .functor AND 1, L_0x2501ae0, L_0x2502a30, C4<1>, C4<1>; +L_0x2502710 .delay (20000,20000,20000) L_0x2502710/d; +L_0x2502860/d .functor OR 1, L_0x25025c0, L_0x2502710, C4<0>, C4<0>; +L_0x2502860 .delay (20000,20000,20000) L_0x2502860/d; +v0x241cee0_0 .net "S", 0 0, L_0x2502a30; 1 drivers +v0x241cf60_0 .alias "in0", 0 0, v0x241ddf0_0; +v0x241d000_0 .alias "in1", 0 0, v0x241daa0_0; +v0x241d0a0_0 .net "nS", 0 0, L_0x2502500; 1 drivers +v0x241d120_0 .net "out0", 0 0, L_0x25025c0; 1 drivers +v0x241d1c0_0 .net "out1", 0 0, L_0x2502710; 1 drivers +v0x241d2a0_0 .alias "outfinal", 0 0, v0x241dd70_0; +S_0x241b800 .scope generate, "orbits[8]" "orbits[8]" 2 196, 2 196, S_0x23d9540; + .timescale -9 -12; +P_0x241b518 .param/l "i" 2 196, +C4<01000>; +S_0x241b930 .scope module, "attempt" "OrNorXor" 2 198, 2 64, S_0x241b800; + .timescale -9 -12; +L_0x2502cc0/d .functor NOR 1, L_0x2502c10, L_0x2503f20, C4<0>, C4<0>; +L_0x2502cc0 .delay (10000,10000,10000) L_0x2502cc0/d; +L_0x2502db0/d .functor NOT 1, L_0x2502cc0, C4<0>, C4<0>, C4<0>; +L_0x2502db0 .delay (10000,10000,10000) L_0x2502db0/d; +L_0x2502ee0/d .functor NAND 1, L_0x2502c10, L_0x2503f20, C4<1>, C4<1>; +L_0x2502ee0 .delay (10000,10000,10000) L_0x2502ee0/d; +L_0x2503040/d .functor NAND 1, L_0x2502ee0, L_0x2502db0, C4<1>, C4<1>; +L_0x2503040 .delay (10000,10000,10000) L_0x2503040/d; +L_0x2503150/d .functor NOT 1, L_0x2503040, C4<0>, C4<0>, C4<0>; +L_0x2503150 .delay (10000,10000,10000) L_0x2503150/d; +v0x241c4e0_0 .net "A", 0 0, L_0x2502c10; 1 drivers +v0x241c580_0 .net "AnandB", 0 0, L_0x2502ee0; 1 drivers +v0x241c620_0 .net "AnorB", 0 0, L_0x2502cc0; 1 drivers +v0x241c6d0_0 .net "AorB", 0 0, L_0x2502db0; 1 drivers +v0x241c7b0_0 .net "AxorB", 0 0, L_0x2503150; 1 drivers +v0x241c860_0 .net "B", 0 0, L_0x2503f20; 1 drivers +v0x241c920_0 .alias "Command", 2 0, v0x2463430_0; +v0x241c9a0_0 .net "OrNorXorOut", 0 0, L_0x2503b50; 1 drivers +v0x241ca20_0 .net "XorNor", 0 0, L_0x25035d0; 1 drivers +v0x241caf0_0 .net "nXor", 0 0, L_0x2503040; 1 drivers +L_0x2503750 .part C4, 2, 1; +L_0x2503d20 .part C4, 0, 1; +S_0x241bf70 .scope module, "mux0" "TwoInMux" 2 83, 2 8, S_0x241b930; + .timescale -9 -12; +L_0x25032b0/d .functor NOT 1, L_0x2503750, C4<0>, C4<0>, C4<0>; +L_0x25032b0 .delay (10000,10000,10000) L_0x25032b0/d; +L_0x2503370/d .functor AND 1, L_0x2503150, L_0x25032b0, C4<1>, C4<1>; +L_0x2503370 .delay (20000,20000,20000) L_0x2503370/d; +L_0x2503480/d .functor AND 1, L_0x2502cc0, L_0x2503750, C4<1>, C4<1>; +L_0x2503480 .delay (20000,20000,20000) L_0x2503480/d; +L_0x25035d0/d .functor OR 1, L_0x2503370, L_0x2503480, C4<0>, C4<0>; +L_0x25035d0 .delay (20000,20000,20000) L_0x25035d0/d; +v0x241c060_0 .net "S", 0 0, L_0x2503750; 1 drivers +v0x241c120_0 .alias "in0", 0 0, v0x241c7b0_0; +v0x241c1c0_0 .alias "in1", 0 0, v0x241c620_0; +v0x241c260_0 .net "nS", 0 0, L_0x25032b0; 1 drivers +v0x241c2e0_0 .net "out0", 0 0, L_0x2503370; 1 drivers +v0x241c380_0 .net "out1", 0 0, L_0x2503480; 1 drivers +v0x241c460_0 .alias "outfinal", 0 0, v0x241ca20_0; +S_0x241ba20 .scope module, "mux1" "TwoInMux" 2 84, 2 8, S_0x241b930; + .timescale -9 -12; +L_0x25037f0/d .functor NOT 1, L_0x2503d20, C4<0>, C4<0>, C4<0>; +L_0x25037f0 .delay (10000,10000,10000) L_0x25037f0/d; +L_0x25038b0/d .functor AND 1, L_0x25035d0, L_0x25037f0, C4<1>, C4<1>; +L_0x25038b0 .delay (20000,20000,20000) L_0x25038b0/d; +L_0x2503a00/d .functor AND 1, L_0x2502db0, L_0x2503d20, C4<1>, C4<1>; +L_0x2503a00 .delay (20000,20000,20000) L_0x2503a00/d; +L_0x2503b50/d .functor OR 1, L_0x25038b0, L_0x2503a00, C4<0>, C4<0>; +L_0x2503b50 .delay (20000,20000,20000) L_0x2503b50/d; +v0x241bb10_0 .net "S", 0 0, L_0x2503d20; 1 drivers +v0x241bb90_0 .alias "in0", 0 0, v0x241ca20_0; +v0x241bc30_0 .alias "in1", 0 0, v0x241c6d0_0; +v0x241bcd0_0 .net "nS", 0 0, L_0x25037f0; 1 drivers +v0x241bd50_0 .net "out0", 0 0, L_0x25038b0; 1 drivers +v0x241bdf0_0 .net "out1", 0 0, L_0x2503a00; 1 drivers +v0x241bed0_0 .alias "outfinal", 0 0, v0x241c9a0_0; +S_0x241a430 .scope generate, "orbits[9]" "orbits[9]" 2 196, 2 196, S_0x23d9540; + .timescale -9 -12; +P_0x241a148 .param/l "i" 2 196, +C4<01001>; +S_0x241a560 .scope module, "attempt" "OrNorXor" 2 198, 2 64, S_0x241a430; + .timescale -9 -12; +L_0x2503e60/d .functor NOR 1, L_0x2505170, L_0x2503fc0, C4<0>, C4<0>; +L_0x2503e60 .delay (10000,10000,10000) L_0x2503e60/d; +L_0x25040e0/d .functor NOT 1, L_0x2503e60, C4<0>, C4<0>, C4<0>; +L_0x25040e0 .delay (10000,10000,10000) L_0x25040e0/d; +L_0x25041f0/d .functor NAND 1, L_0x2505170, L_0x2503fc0, C4<1>, C4<1>; +L_0x25041f0 .delay (10000,10000,10000) L_0x25041f0/d; +L_0x2504350/d .functor NAND 1, L_0x25041f0, L_0x25040e0, C4<1>, C4<1>; +L_0x2504350 .delay (10000,10000,10000) L_0x2504350/d; +L_0x2504460/d .functor NOT 1, L_0x2504350, C4<0>, C4<0>, C4<0>; +L_0x2504460 .delay (10000,10000,10000) L_0x2504460/d; +v0x241b110_0 .net "A", 0 0, L_0x2505170; 1 drivers +v0x241b1b0_0 .net "AnandB", 0 0, L_0x25041f0; 1 drivers +v0x241b250_0 .net "AnorB", 0 0, L_0x2503e60; 1 drivers +v0x241b300_0 .net "AorB", 0 0, L_0x25040e0; 1 drivers +v0x241b3e0_0 .net "AxorB", 0 0, L_0x2504460; 1 drivers +v0x241b490_0 .net "B", 0 0, L_0x2503fc0; 1 drivers +v0x241b550_0 .alias "Command", 2 0, v0x2463430_0; +v0x241b5d0_0 .net "OrNorXorOut", 0 0, L_0x2504e60; 1 drivers +v0x241b650_0 .net "XorNor", 0 0, L_0x25048e0; 1 drivers +v0x241b720_0 .net "nXor", 0 0, L_0x2504350; 1 drivers +L_0x2504a60 .part C4, 2, 1; +L_0x2505030 .part C4, 0, 1; +S_0x241aba0 .scope module, "mux0" "TwoInMux" 2 83, 2 8, S_0x241a560; + .timescale -9 -12; +L_0x25045c0/d .functor NOT 1, L_0x2504a60, C4<0>, C4<0>, C4<0>; +L_0x25045c0 .delay (10000,10000,10000) L_0x25045c0/d; +L_0x2504680/d .functor AND 1, L_0x2504460, L_0x25045c0, C4<1>, C4<1>; +L_0x2504680 .delay (20000,20000,20000) L_0x2504680/d; +L_0x2504790/d .functor AND 1, L_0x2503e60, L_0x2504a60, C4<1>, C4<1>; +L_0x2504790 .delay (20000,20000,20000) L_0x2504790/d; +L_0x25048e0/d .functor OR 1, L_0x2504680, L_0x2504790, C4<0>, C4<0>; +L_0x25048e0 .delay (20000,20000,20000) L_0x25048e0/d; +v0x241ac90_0 .net "S", 0 0, L_0x2504a60; 1 drivers +v0x241ad50_0 .alias "in0", 0 0, v0x241b3e0_0; +v0x241adf0_0 .alias "in1", 0 0, v0x241b250_0; +v0x241ae90_0 .net "nS", 0 0, L_0x25045c0; 1 drivers +v0x241af10_0 .net "out0", 0 0, L_0x2504680; 1 drivers +v0x241afb0_0 .net "out1", 0 0, L_0x2504790; 1 drivers +v0x241b090_0 .alias "outfinal", 0 0, v0x241b650_0; +S_0x241a650 .scope module, "mux1" "TwoInMux" 2 84, 2 8, S_0x241a560; + .timescale -9 -12; +L_0x2504b00/d .functor NOT 1, L_0x2505030, C4<0>, C4<0>, C4<0>; +L_0x2504b00 .delay (10000,10000,10000) L_0x2504b00/d; +L_0x2504bc0/d .functor AND 1, L_0x25048e0, L_0x2504b00, C4<1>, C4<1>; +L_0x2504bc0 .delay (20000,20000,20000) L_0x2504bc0/d; +L_0x2504d10/d .functor AND 1, L_0x25040e0, L_0x2505030, C4<1>, C4<1>; +L_0x2504d10 .delay (20000,20000,20000) L_0x2504d10/d; +L_0x2504e60/d .functor OR 1, L_0x2504bc0, L_0x2504d10, C4<0>, C4<0>; +L_0x2504e60 .delay (20000,20000,20000) L_0x2504e60/d; +v0x241a740_0 .net "S", 0 0, L_0x2505030; 1 drivers +v0x241a7c0_0 .alias "in0", 0 0, v0x241b650_0; +v0x241a860_0 .alias "in1", 0 0, v0x241b300_0; +v0x241a900_0 .net "nS", 0 0, L_0x2504b00; 1 drivers +v0x241a980_0 .net "out0", 0 0, L_0x2504bc0; 1 drivers +v0x241aa20_0 .net "out1", 0 0, L_0x2504d10; 1 drivers +v0x241ab00_0 .alias "outfinal", 0 0, v0x241b5d0_0; +S_0x2419060 .scope generate, "orbits[10]" "orbits[10]" 2 196, 2 196, S_0x23d9540; + .timescale -9 -12; +P_0x2418d28 .param/l "i" 2 196, +C4<01010>; +S_0x2419190 .scope module, "attempt" "OrNorXor" 2 198, 2 64, S_0x2419060; + .timescale -9 -12; +L_0x25052f0/d .functor NOR 1, L_0x2505210, L_0x2506560, C4<0>, C4<0>; +L_0x25052f0 .delay (10000,10000,10000) L_0x25052f0/d; +L_0x25053e0/d .functor NOT 1, L_0x25052f0, C4<0>, C4<0>, C4<0>; +L_0x25053e0 .delay (10000,10000,10000) L_0x25053e0/d; +L_0x25054f0/d .functor NAND 1, L_0x2505210, L_0x2506560, C4<1>, C4<1>; +L_0x25054f0 .delay (10000,10000,10000) L_0x25054f0/d; +L_0x2505650/d .functor NAND 1, L_0x25054f0, L_0x25053e0, C4<1>, C4<1>; +L_0x2505650 .delay (10000,10000,10000) L_0x2505650/d; +L_0x2505760/d .functor NOT 1, L_0x2505650, C4<0>, C4<0>, C4<0>; +L_0x2505760 .delay (10000,10000,10000) L_0x2505760/d; +v0x2419d40_0 .net "A", 0 0, L_0x2505210; 1 drivers +v0x2419de0_0 .net "AnandB", 0 0, L_0x25054f0; 1 drivers +v0x2419e80_0 .net "AnorB", 0 0, L_0x25052f0; 1 drivers +v0x2419f30_0 .net "AorB", 0 0, L_0x25053e0; 1 drivers +v0x241a010_0 .net "AxorB", 0 0, L_0x2505760; 1 drivers +v0x241a0c0_0 .net "B", 0 0, L_0x2506560; 1 drivers +v0x241a180_0 .alias "Command", 2 0, v0x2463430_0; +v0x241a200_0 .net "OrNorXorOut", 0 0, L_0x2506160; 1 drivers +v0x241a280_0 .net "XorNor", 0 0, L_0x2505be0; 1 drivers +v0x241a350_0 .net "nXor", 0 0, L_0x2505650; 1 drivers +L_0x2505d60 .part C4, 2, 1; +L_0x2506330 .part C4, 0, 1; +S_0x24197d0 .scope module, "mux0" "TwoInMux" 2 83, 2 8, S_0x2419190; + .timescale -9 -12; +L_0x25058c0/d .functor NOT 1, L_0x2505d60, C4<0>, C4<0>, C4<0>; +L_0x25058c0 .delay (10000,10000,10000) L_0x25058c0/d; +L_0x2505980/d .functor AND 1, L_0x2505760, L_0x25058c0, C4<1>, C4<1>; +L_0x2505980 .delay (20000,20000,20000) L_0x2505980/d; +L_0x2505a90/d .functor AND 1, L_0x25052f0, L_0x2505d60, C4<1>, C4<1>; +L_0x2505a90 .delay (20000,20000,20000) L_0x2505a90/d; +L_0x2505be0/d .functor OR 1, L_0x2505980, L_0x2505a90, C4<0>, C4<0>; +L_0x2505be0 .delay (20000,20000,20000) L_0x2505be0/d; +v0x24198c0_0 .net "S", 0 0, L_0x2505d60; 1 drivers +v0x2419980_0 .alias "in0", 0 0, v0x241a010_0; +v0x2419a20_0 .alias "in1", 0 0, v0x2419e80_0; +v0x2419ac0_0 .net "nS", 0 0, L_0x25058c0; 1 drivers +v0x2419b40_0 .net "out0", 0 0, L_0x2505980; 1 drivers +v0x2419be0_0 .net "out1", 0 0, L_0x2505a90; 1 drivers +v0x2419cc0_0 .alias "outfinal", 0 0, v0x241a280_0; +S_0x2419280 .scope module, "mux1" "TwoInMux" 2 84, 2 8, S_0x2419190; + .timescale -9 -12; +L_0x2505e00/d .functor NOT 1, L_0x2506330, C4<0>, C4<0>, C4<0>; +L_0x2505e00 .delay (10000,10000,10000) L_0x2505e00/d; +L_0x2505ec0/d .functor AND 1, L_0x2505be0, L_0x2505e00, C4<1>, C4<1>; +L_0x2505ec0 .delay (20000,20000,20000) L_0x2505ec0/d; +L_0x2506010/d .functor AND 1, L_0x25053e0, L_0x2506330, C4<1>, C4<1>; +L_0x2506010 .delay (20000,20000,20000) L_0x2506010/d; +L_0x2506160/d .functor OR 1, L_0x2505ec0, L_0x2506010, C4<0>, C4<0>; +L_0x2506160 .delay (20000,20000,20000) L_0x2506160/d; +v0x2419370_0 .net "S", 0 0, L_0x2506330; 1 drivers +v0x24193f0_0 .alias "in0", 0 0, v0x241a280_0; +v0x2419490_0 .alias "in1", 0 0, v0x2419f30_0; +v0x2419530_0 .net "nS", 0 0, L_0x2505e00; 1 drivers +v0x24195b0_0 .net "out0", 0 0, L_0x2505ec0; 1 drivers +v0x2419650_0 .net "out1", 0 0, L_0x2506010; 1 drivers +v0x2419730_0 .alias "outfinal", 0 0, v0x241a200_0; +S_0x2417c90 .scope generate, "orbits[11]" "orbits[11]" 2 196, 2 196, S_0x23d9540; + .timescale -9 -12; +P_0x24179a8 .param/l "i" 2 196, +C4<01011>; +S_0x2417dc0 .scope module, "attempt" "OrNorXor" 2 198, 2 64, S_0x2417c90; + .timescale -9 -12; +L_0x2506470/d .functor NOR 1, L_0x2507770, L_0x2506600, C4<0>, C4<0>; +L_0x2506470 .delay (10000,10000,10000) L_0x2506470/d; +L_0x2506700/d .functor NOT 1, L_0x2506470, C4<0>, C4<0>, C4<0>; +L_0x2506700 .delay (10000,10000,10000) L_0x2506700/d; +L_0x25067f0/d .functor NAND 1, L_0x2507770, L_0x2506600, C4<1>, C4<1>; +L_0x25067f0 .delay (10000,10000,10000) L_0x25067f0/d; +L_0x2506950/d .functor NAND 1, L_0x25067f0, L_0x2506700, C4<1>, C4<1>; +L_0x2506950 .delay (10000,10000,10000) L_0x2506950/d; +L_0x2506a60/d .functor NOT 1, L_0x2506950, C4<0>, C4<0>, C4<0>; +L_0x2506a60 .delay (10000,10000,10000) L_0x2506a60/d; +v0x2418920_0 .net "A", 0 0, L_0x2507770; 1 drivers +v0x24189c0_0 .net "AnandB", 0 0, L_0x25067f0; 1 drivers +v0x2418a60_0 .net "AnorB", 0 0, L_0x2506470; 1 drivers +v0x2418b10_0 .net "AorB", 0 0, L_0x2506700; 1 drivers +v0x2418bf0_0 .net "AxorB", 0 0, L_0x2506a60; 1 drivers +v0x2418ca0_0 .net "B", 0 0, L_0x2506600; 1 drivers +v0x2418d60_0 .alias "Command", 2 0, v0x2463430_0; +v0x2418de0_0 .net "OrNorXorOut", 0 0, L_0x2507460; 1 drivers +v0x2418eb0_0 .net "XorNor", 0 0, L_0x2506ee0; 1 drivers +v0x2418f80_0 .net "nXor", 0 0, L_0x2506950; 1 drivers +L_0x2507060 .part C4, 2, 1; +L_0x2507630 .part C4, 0, 1; +S_0x24183b0 .scope module, "mux0" "TwoInMux" 2 83, 2 8, S_0x2417dc0; + .timescale -9 -12; +L_0x2506bc0/d .functor NOT 1, L_0x2507060, C4<0>, C4<0>, C4<0>; +L_0x2506bc0 .delay (10000,10000,10000) L_0x2506bc0/d; +L_0x2506c80/d .functor AND 1, L_0x2506a60, L_0x2506bc0, C4<1>, C4<1>; +L_0x2506c80 .delay (20000,20000,20000) L_0x2506c80/d; +L_0x2506d90/d .functor AND 1, L_0x2506470, L_0x2507060, C4<1>, C4<1>; +L_0x2506d90 .delay (20000,20000,20000) L_0x2506d90/d; +L_0x2506ee0/d .functor OR 1, L_0x2506c80, L_0x2506d90, C4<0>, C4<0>; +L_0x2506ee0 .delay (20000,20000,20000) L_0x2506ee0/d; +v0x24184a0_0 .net "S", 0 0, L_0x2507060; 1 drivers +v0x2418560_0 .alias "in0", 0 0, v0x2418bf0_0; +v0x2418600_0 .alias "in1", 0 0, v0x2418a60_0; +v0x24186a0_0 .net "nS", 0 0, L_0x2506bc0; 1 drivers +v0x2418720_0 .net "out0", 0 0, L_0x2506c80; 1 drivers +v0x24187c0_0 .net "out1", 0 0, L_0x2506d90; 1 drivers +v0x24188a0_0 .alias "outfinal", 0 0, v0x2418eb0_0; +S_0x2417eb0 .scope module, "mux1" "TwoInMux" 2 84, 2 8, S_0x2417dc0; + .timescale -9 -12; +L_0x2507100/d .functor NOT 1, L_0x2507630, C4<0>, C4<0>, C4<0>; +L_0x2507100 .delay (10000,10000,10000) L_0x2507100/d; +L_0x25071c0/d .functor AND 1, L_0x2506ee0, L_0x2507100, C4<1>, C4<1>; +L_0x25071c0 .delay (20000,20000,20000) L_0x25071c0/d; +L_0x2507310/d .functor AND 1, L_0x2506700, L_0x2507630, C4<1>, C4<1>; +L_0x2507310 .delay (20000,20000,20000) L_0x2507310/d; +L_0x2507460/d .functor OR 1, L_0x25071c0, L_0x2507310, C4<0>, C4<0>; +L_0x2507460 .delay (20000,20000,20000) L_0x2507460/d; +v0x23de0c0_0 .net "S", 0 0, L_0x2507630; 1 drivers +v0x2417fa0_0 .alias "in0", 0 0, v0x2418eb0_0; +v0x2418040_0 .alias "in1", 0 0, v0x2418b10_0; +v0x24180e0_0 .net "nS", 0 0, L_0x2507100; 1 drivers +v0x2418190_0 .net "out0", 0 0, L_0x25071c0; 1 drivers +v0x2418230_0 .net "out1", 0 0, L_0x2507310; 1 drivers +v0x2418310_0 .alias "outfinal", 0 0, v0x2418de0_0; +S_0x24168c0 .scope generate, "orbits[12]" "orbits[12]" 2 196, 2 196, S_0x23d9540; + .timescale -9 -12; +P_0x24165d8 .param/l "i" 2 196, +C4<01100>; +S_0x24169f0 .scope module, "attempt" "OrNorXor" 2 198, 2 64, S_0x24168c0; + .timescale -9 -12; +L_0x25066a0/d .functor NOR 1, L_0x2507810, L_0x2508b80, C4<0>, C4<0>; +L_0x25066a0 .delay (10000,10000,10000) L_0x25066a0/d; +L_0x25079b0/d .functor NOT 1, L_0x25066a0, C4<0>, C4<0>, C4<0>; +L_0x25079b0 .delay (10000,10000,10000) L_0x25079b0/d; +L_0x2507ae0/d .functor NAND 1, L_0x2507810, L_0x2508b80, C4<1>, C4<1>; +L_0x2507ae0 .delay (10000,10000,10000) L_0x2507ae0/d; +L_0x2507c40/d .functor NAND 1, L_0x2507ae0, L_0x25079b0, C4<1>, C4<1>; +L_0x2507c40 .delay (10000,10000,10000) L_0x2507c40/d; +L_0x2507d50/d .functor NOT 1, L_0x2507c40, C4<0>, C4<0>, C4<0>; +L_0x2507d50 .delay (10000,10000,10000) L_0x2507d50/d; +v0x24175a0_0 .net "A", 0 0, L_0x2507810; 1 drivers +v0x2417640_0 .net "AnandB", 0 0, L_0x2507ae0; 1 drivers +v0x24176e0_0 .net "AnorB", 0 0, L_0x25066a0; 1 drivers +v0x2417790_0 .net "AorB", 0 0, L_0x25079b0; 1 drivers +v0x2417870_0 .net "AxorB", 0 0, L_0x2507d50; 1 drivers +v0x2417920_0 .net "B", 0 0, L_0x2508b80; 1 drivers +v0x24179e0_0 .alias "Command", 2 0, v0x2463430_0; +v0x2417a60_0 .net "OrNorXorOut", 0 0, L_0x2508750; 1 drivers +v0x2417ae0_0 .net "XorNor", 0 0, L_0x25081d0; 1 drivers +v0x2417bb0_0 .net "nXor", 0 0, L_0x2507c40; 1 drivers +L_0x2508350 .part C4, 2, 1; +L_0x2508920 .part C4, 0, 1; +S_0x2417030 .scope module, "mux0" "TwoInMux" 2 83, 2 8, S_0x24169f0; + .timescale -9 -12; +L_0x2507eb0/d .functor NOT 1, L_0x2508350, C4<0>, C4<0>, C4<0>; +L_0x2507eb0 .delay (10000,10000,10000) L_0x2507eb0/d; +L_0x2507f70/d .functor AND 1, L_0x2507d50, L_0x2507eb0, C4<1>, C4<1>; +L_0x2507f70 .delay (20000,20000,20000) L_0x2507f70/d; +L_0x2508080/d .functor AND 1, L_0x25066a0, L_0x2508350, C4<1>, C4<1>; +L_0x2508080 .delay (20000,20000,20000) L_0x2508080/d; +L_0x25081d0/d .functor OR 1, L_0x2507f70, L_0x2508080, C4<0>, C4<0>; +L_0x25081d0 .delay (20000,20000,20000) L_0x25081d0/d; +v0x2417120_0 .net "S", 0 0, L_0x2508350; 1 drivers +v0x24171e0_0 .alias "in0", 0 0, v0x2417870_0; +v0x2417280_0 .alias "in1", 0 0, v0x24176e0_0; +v0x2417320_0 .net "nS", 0 0, L_0x2507eb0; 1 drivers +v0x24173a0_0 .net "out0", 0 0, L_0x2507f70; 1 drivers +v0x2417440_0 .net "out1", 0 0, L_0x2508080; 1 drivers +v0x2417520_0 .alias "outfinal", 0 0, v0x2417ae0_0; +S_0x2416ae0 .scope module, "mux1" "TwoInMux" 2 84, 2 8, S_0x24169f0; + .timescale -9 -12; +L_0x25083f0/d .functor NOT 1, L_0x2508920, C4<0>, C4<0>, C4<0>; +L_0x25083f0 .delay (10000,10000,10000) L_0x25083f0/d; +L_0x25084b0/d .functor AND 1, L_0x25081d0, L_0x25083f0, C4<1>, C4<1>; +L_0x25084b0 .delay (20000,20000,20000) L_0x25084b0/d; +L_0x2508600/d .functor AND 1, L_0x25079b0, L_0x2508920, C4<1>, C4<1>; +L_0x2508600 .delay (20000,20000,20000) L_0x2508600/d; +L_0x2508750/d .functor OR 1, L_0x25084b0, L_0x2508600, C4<0>, C4<0>; +L_0x2508750 .delay (20000,20000,20000) L_0x2508750/d; +v0x2416bd0_0 .net "S", 0 0, L_0x2508920; 1 drivers +v0x2416c50_0 .alias "in0", 0 0, v0x2417ae0_0; +v0x2416cf0_0 .alias "in1", 0 0, v0x2417790_0; +v0x2416d90_0 .net "nS", 0 0, L_0x25083f0; 1 drivers +v0x2416e10_0 .net "out0", 0 0, L_0x25084b0; 1 drivers +v0x2416eb0_0 .net "out1", 0 0, L_0x2508600; 1 drivers +v0x2416f90_0 .alias "outfinal", 0 0, v0x2417a60_0; +S_0x24154f0 .scope generate, "orbits[13]" "orbits[13]" 2 196, 2 196, S_0x23d9540; + .timescale -9 -12; +P_0x2415208 .param/l "i" 2 196, +C4<01101>; +S_0x2415620 .scope module, "attempt" "OrNorXor" 2 198, 2 64, S_0x24154f0; + .timescale -9 -12; +L_0x25078b0/d .functor NOR 1, L_0x2509d80, L_0x2508c20, C4<0>, C4<0>; +L_0x25078b0 .delay (10000,10000,10000) L_0x25078b0/d; +L_0x2508af0/d .functor NOT 1, L_0x25078b0, C4<0>, C4<0>, C4<0>; +L_0x2508af0 .delay (10000,10000,10000) L_0x2508af0/d; +L_0x2508e00/d .functor NAND 1, L_0x2509d80, L_0x2508c20, C4<1>, C4<1>; +L_0x2508e00 .delay (10000,10000,10000) L_0x2508e00/d; +L_0x2508f60/d .functor NAND 1, L_0x2508e00, L_0x2508af0, C4<1>, C4<1>; +L_0x2508f60 .delay (10000,10000,10000) L_0x2508f60/d; +L_0x2509070/d .functor NOT 1, L_0x2508f60, C4<0>, C4<0>, C4<0>; +L_0x2509070 .delay (10000,10000,10000) L_0x2509070/d; +v0x24161d0_0 .net "A", 0 0, L_0x2509d80; 1 drivers +v0x2416270_0 .net "AnandB", 0 0, L_0x2508e00; 1 drivers +v0x2416310_0 .net "AnorB", 0 0, L_0x25078b0; 1 drivers +v0x24163c0_0 .net "AorB", 0 0, L_0x2508af0; 1 drivers +v0x24164a0_0 .net "AxorB", 0 0, L_0x2509070; 1 drivers +v0x2416550_0 .net "B", 0 0, L_0x2508c20; 1 drivers +v0x2416610_0 .alias "Command", 2 0, v0x2463430_0; +v0x2416690_0 .net "OrNorXorOut", 0 0, L_0x2509a70; 1 drivers +v0x2416710_0 .net "XorNor", 0 0, L_0x25094f0; 1 drivers +v0x24167e0_0 .net "nXor", 0 0, L_0x2508f60; 1 drivers +L_0x2509670 .part C4, 2, 1; +L_0x2509c40 .part C4, 0, 1; +S_0x2415c60 .scope module, "mux0" "TwoInMux" 2 83, 2 8, S_0x2415620; + .timescale -9 -12; +L_0x25091d0/d .functor NOT 1, L_0x2509670, C4<0>, C4<0>, C4<0>; +L_0x25091d0 .delay (10000,10000,10000) L_0x25091d0/d; +L_0x2509290/d .functor AND 1, L_0x2509070, L_0x25091d0, C4<1>, C4<1>; +L_0x2509290 .delay (20000,20000,20000) L_0x2509290/d; +L_0x25093a0/d .functor AND 1, L_0x25078b0, L_0x2509670, C4<1>, C4<1>; +L_0x25093a0 .delay (20000,20000,20000) L_0x25093a0/d; +L_0x25094f0/d .functor OR 1, L_0x2509290, L_0x25093a0, C4<0>, C4<0>; +L_0x25094f0 .delay (20000,20000,20000) L_0x25094f0/d; +v0x2415d50_0 .net "S", 0 0, L_0x2509670; 1 drivers +v0x2415e10_0 .alias "in0", 0 0, v0x24164a0_0; +v0x2415eb0_0 .alias "in1", 0 0, v0x2416310_0; +v0x2415f50_0 .net "nS", 0 0, L_0x25091d0; 1 drivers +v0x2415fd0_0 .net "out0", 0 0, L_0x2509290; 1 drivers +v0x2416070_0 .net "out1", 0 0, L_0x25093a0; 1 drivers +v0x2416150_0 .alias "outfinal", 0 0, v0x2416710_0; +S_0x2415710 .scope module, "mux1" "TwoInMux" 2 84, 2 8, S_0x2415620; + .timescale -9 -12; +L_0x2509710/d .functor NOT 1, L_0x2509c40, C4<0>, C4<0>, C4<0>; +L_0x2509710 .delay (10000,10000,10000) L_0x2509710/d; +L_0x25097d0/d .functor AND 1, L_0x25094f0, L_0x2509710, C4<1>, C4<1>; +L_0x25097d0 .delay (20000,20000,20000) L_0x25097d0/d; +L_0x2509920/d .functor AND 1, L_0x2508af0, L_0x2509c40, C4<1>, C4<1>; +L_0x2509920 .delay (20000,20000,20000) L_0x2509920/d; +L_0x2509a70/d .functor OR 1, L_0x25097d0, L_0x2509920, C4<0>, C4<0>; +L_0x2509a70 .delay (20000,20000,20000) L_0x2509a70/d; +v0x2415800_0 .net "S", 0 0, L_0x2509c40; 1 drivers +v0x2415880_0 .alias "in0", 0 0, v0x2416710_0; +v0x2415920_0 .alias "in1", 0 0, v0x24163c0_0; +v0x24159c0_0 .net "nS", 0 0, L_0x2509710; 1 drivers +v0x2415a40_0 .net "out0", 0 0, L_0x25097d0; 1 drivers +v0x2415ae0_0 .net "out1", 0 0, L_0x2509920; 1 drivers +v0x2415bc0_0 .alias "outfinal", 0 0, v0x2416690_0; +S_0x2414120 .scope generate, "orbits[14]" "orbits[14]" 2 196, 2 196, S_0x23d9540; + .timescale -9 -12; +P_0x2413d28 .param/l "i" 2 196, +C4<01110>; +S_0x2414250 .scope module, "attempt" "OrNorXor" 2 198, 2 64, S_0x2414120; + .timescale -9 -12; +L_0x2508cc0/d .functor NOR 1, L_0x2509e20, L_0x2509ec0, C4<0>, C4<0>; +L_0x2508cc0 .delay (10000,10000,10000) L_0x2508cc0/d; +L_0x2509ff0/d .functor NOT 1, L_0x2508cc0, C4<0>, C4<0>, C4<0>; +L_0x2509ff0 .delay (10000,10000,10000) L_0x2509ff0/d; +L_0x250a100/d .functor NAND 1, L_0x2509e20, L_0x2509ec0, C4<1>, C4<1>; +L_0x250a100 .delay (10000,10000,10000) L_0x250a100/d; +L_0x250a260/d .functor NAND 1, L_0x250a100, L_0x2509ff0, C4<1>, C4<1>; +L_0x250a260 .delay (10000,10000,10000) L_0x250a260/d; +L_0x250a370/d .functor NOT 1, L_0x250a260, C4<0>, C4<0>, C4<0>; +L_0x250a370 .delay (10000,10000,10000) L_0x250a370/d; +v0x2414e00_0 .net "A", 0 0, L_0x2509e20; 1 drivers +v0x2414ea0_0 .net "AnandB", 0 0, L_0x250a100; 1 drivers +v0x2414f40_0 .net "AnorB", 0 0, L_0x2508cc0; 1 drivers +v0x2414ff0_0 .net "AorB", 0 0, L_0x2509ff0; 1 drivers +v0x24150d0_0 .net "AxorB", 0 0, L_0x250a370; 1 drivers +v0x2415180_0 .net "B", 0 0, L_0x2509ec0; 1 drivers +v0x2415240_0 .alias "Command", 2 0, v0x2463430_0; +v0x24152c0_0 .net "OrNorXorOut", 0 0, L_0x250ad70; 1 drivers +v0x2415340_0 .net "XorNor", 0 0, L_0x250a7f0; 1 drivers +v0x2415410_0 .net "nXor", 0 0, L_0x250a260; 1 drivers +L_0x250a970 .part C4, 2, 1; +L_0x250af40 .part C4, 0, 1; +S_0x2414890 .scope module, "mux0" "TwoInMux" 2 83, 2 8, S_0x2414250; + .timescale -9 -12; +L_0x250a4d0/d .functor NOT 1, L_0x250a970, C4<0>, C4<0>, C4<0>; +L_0x250a4d0 .delay (10000,10000,10000) L_0x250a4d0/d; +L_0x250a590/d .functor AND 1, L_0x250a370, L_0x250a4d0, C4<1>, C4<1>; +L_0x250a590 .delay (20000,20000,20000) L_0x250a590/d; +L_0x250a6a0/d .functor AND 1, L_0x2508cc0, L_0x250a970, C4<1>, C4<1>; +L_0x250a6a0 .delay (20000,20000,20000) L_0x250a6a0/d; +L_0x250a7f0/d .functor OR 1, L_0x250a590, L_0x250a6a0, C4<0>, C4<0>; +L_0x250a7f0 .delay (20000,20000,20000) L_0x250a7f0/d; +v0x2414980_0 .net "S", 0 0, L_0x250a970; 1 drivers +v0x2414a40_0 .alias "in0", 0 0, v0x24150d0_0; +v0x2414ae0_0 .alias "in1", 0 0, v0x2414f40_0; +v0x2414b80_0 .net "nS", 0 0, L_0x250a4d0; 1 drivers +v0x2414c00_0 .net "out0", 0 0, L_0x250a590; 1 drivers +v0x2414ca0_0 .net "out1", 0 0, L_0x250a6a0; 1 drivers +v0x2414d80_0 .alias "outfinal", 0 0, v0x2415340_0; +S_0x2414340 .scope module, "mux1" "TwoInMux" 2 84, 2 8, S_0x2414250; + .timescale -9 -12; +L_0x250aa10/d .functor NOT 1, L_0x250af40, C4<0>, C4<0>, C4<0>; +L_0x250aa10 .delay (10000,10000,10000) L_0x250aa10/d; +L_0x250aad0/d .functor AND 1, L_0x250a7f0, L_0x250aa10, C4<1>, C4<1>; +L_0x250aad0 .delay (20000,20000,20000) L_0x250aad0/d; +L_0x250ac20/d .functor AND 1, L_0x2509ff0, L_0x250af40, C4<1>, C4<1>; +L_0x250ac20 .delay (20000,20000,20000) L_0x250ac20/d; +L_0x250ad70/d .functor OR 1, L_0x250aad0, L_0x250ac20, C4<0>, C4<0>; +L_0x250ad70 .delay (20000,20000,20000) L_0x250ad70/d; +v0x2414430_0 .net "S", 0 0, L_0x250af40; 1 drivers +v0x24144b0_0 .alias "in0", 0 0, v0x2415340_0; +v0x2414550_0 .alias "in1", 0 0, v0x2414ff0_0; +v0x24145f0_0 .net "nS", 0 0, L_0x250aa10; 1 drivers +v0x2414670_0 .net "out0", 0 0, L_0x250aad0; 1 drivers +v0x2414710_0 .net "out1", 0 0, L_0x250ac20; 1 drivers +v0x24147f0_0 .alias "outfinal", 0 0, v0x24152c0_0; +S_0x2412c40 .scope generate, "orbits[15]" "orbits[15]" 2 196, 2 196, S_0x23d9540; + .timescale -9 -12; +P_0x2412958 .param/l "i" 2 196, +C4<01111>; +S_0x2412d70 .scope module, "attempt" "OrNorXor" 2 198, 2 64, S_0x2412c40; + .timescale -9 -12; +L_0x250b1e0/d .functor NOR 1, L_0x250c380, L_0x250b080, C4<0>, C4<0>; +L_0x250b1e0 .delay (10000,10000,10000) L_0x250b1e0/d; +L_0x250b2d0/d .functor NOT 1, L_0x250b1e0, C4<0>, C4<0>, C4<0>; +L_0x250b2d0 .delay (10000,10000,10000) L_0x250b2d0/d; +L_0x250b400/d .functor NAND 1, L_0x250c380, L_0x250b080, C4<1>, C4<1>; +L_0x250b400 .delay (10000,10000,10000) L_0x250b400/d; +L_0x250b560/d .functor NAND 1, L_0x250b400, L_0x250b2d0, C4<1>, C4<1>; +L_0x250b560 .delay (10000,10000,10000) L_0x250b560/d; +L_0x250b670/d .functor NOT 1, L_0x250b560, C4<0>, C4<0>, C4<0>; +L_0x250b670 .delay (10000,10000,10000) L_0x250b670/d; +v0x2413920_0 .net "A", 0 0, L_0x250c380; 1 drivers +v0x24139c0_0 .net "AnandB", 0 0, L_0x250b400; 1 drivers +v0x2413a60_0 .net "AnorB", 0 0, L_0x250b1e0; 1 drivers +v0x2413b10_0 .net "AorB", 0 0, L_0x250b2d0; 1 drivers +v0x2413bf0_0 .net "AxorB", 0 0, L_0x250b670; 1 drivers +v0x2413ca0_0 .net "B", 0 0, L_0x250b080; 1 drivers +v0x2413d60_0 .alias "Command", 2 0, v0x2463430_0; +v0x240a1d0_0 .net "OrNorXorOut", 0 0, L_0x250c070; 1 drivers +v0x240a250_0 .net "XorNor", 0 0, L_0x250baf0; 1 drivers +v0x2414040_0 .net "nXor", 0 0, L_0x250b560; 1 drivers +L_0x250bc70 .part C4, 2, 1; +L_0x250c240 .part C4, 0, 1; +S_0x24133b0 .scope module, "mux0" "TwoInMux" 2 83, 2 8, S_0x2412d70; + .timescale -9 -12; +L_0x250b7d0/d .functor NOT 1, L_0x250bc70, C4<0>, C4<0>, C4<0>; +L_0x250b7d0 .delay (10000,10000,10000) L_0x250b7d0/d; +L_0x250b890/d .functor AND 1, L_0x250b670, L_0x250b7d0, C4<1>, C4<1>; +L_0x250b890 .delay (20000,20000,20000) L_0x250b890/d; +L_0x250b9a0/d .functor AND 1, L_0x250b1e0, L_0x250bc70, C4<1>, C4<1>; +L_0x250b9a0 .delay (20000,20000,20000) L_0x250b9a0/d; +L_0x250baf0/d .functor OR 1, L_0x250b890, L_0x250b9a0, C4<0>, C4<0>; +L_0x250baf0 .delay (20000,20000,20000) L_0x250baf0/d; +v0x24134a0_0 .net "S", 0 0, L_0x250bc70; 1 drivers +v0x2413560_0 .alias "in0", 0 0, v0x2413bf0_0; +v0x2413600_0 .alias "in1", 0 0, v0x2413a60_0; +v0x24136a0_0 .net "nS", 0 0, L_0x250b7d0; 1 drivers +v0x2413720_0 .net "out0", 0 0, L_0x250b890; 1 drivers +v0x24137c0_0 .net "out1", 0 0, L_0x250b9a0; 1 drivers +v0x24138a0_0 .alias "outfinal", 0 0, v0x240a250_0; +S_0x2412e60 .scope module, "mux1" "TwoInMux" 2 84, 2 8, S_0x2412d70; + .timescale -9 -12; +L_0x250bd10/d .functor NOT 1, L_0x250c240, C4<0>, C4<0>, C4<0>; +L_0x250bd10 .delay (10000,10000,10000) L_0x250bd10/d; +L_0x250bdd0/d .functor AND 1, L_0x250baf0, L_0x250bd10, C4<1>, C4<1>; +L_0x250bdd0 .delay (20000,20000,20000) L_0x250bdd0/d; +L_0x250bf20/d .functor AND 1, L_0x250b2d0, L_0x250c240, C4<1>, C4<1>; +L_0x250bf20 .delay (20000,20000,20000) L_0x250bf20/d; +L_0x250c070/d .functor OR 1, L_0x250bdd0, L_0x250bf20, C4<0>, C4<0>; +L_0x250c070 .delay (20000,20000,20000) L_0x250c070/d; +v0x2412f50_0 .net "S", 0 0, L_0x250c240; 1 drivers +v0x2412fd0_0 .alias "in0", 0 0, v0x240a250_0; +v0x2413070_0 .alias "in1", 0 0, v0x2413b10_0; +v0x2413110_0 .net "nS", 0 0, L_0x250bd10; 1 drivers +v0x2413190_0 .net "out0", 0 0, L_0x250bdd0; 1 drivers +v0x2413230_0 .net "out1", 0 0, L_0x250bf20; 1 drivers +v0x2413310_0 .alias "outfinal", 0 0, v0x240a1d0_0; +S_0x2411870 .scope generate, "orbits[16]" "orbits[16]" 2 196, 2 196, S_0x23d9540; + .timescale -9 -12; +P_0x2411588 .param/l "i" 2 196, +C4<010000>; +S_0x24119a0 .scope module, "attempt" "OrNorXor" 2 198, 2 64, S_0x2411870; + .timescale -9 -12; +L_0x250b120/d .functor NOR 1, L_0x250c420, L_0x250c4c0, C4<0>, C4<0>; +L_0x250b120 .delay (10000,10000,10000) L_0x250b120/d; +L_0x250c5e0/d .functor NOT 1, L_0x250b120, C4<0>, C4<0>, C4<0>; +L_0x250c5e0 .delay (10000,10000,10000) L_0x250c5e0/d; +L_0x250c6f0/d .functor NAND 1, L_0x250c420, L_0x250c4c0, C4<1>, C4<1>; +L_0x250c6f0 .delay (10000,10000,10000) L_0x250c6f0/d; +L_0x250c850/d .functor NAND 1, L_0x250c6f0, L_0x250c5e0, C4<1>, C4<1>; +L_0x250c850 .delay (10000,10000,10000) L_0x250c850/d; +L_0x250c960/d .functor NOT 1, L_0x250c850, C4<0>, C4<0>, C4<0>; +L_0x250c960 .delay (10000,10000,10000) L_0x250c960/d; +v0x2412550_0 .net "A", 0 0, L_0x250c420; 1 drivers +v0x24125f0_0 .net "AnandB", 0 0, L_0x250c6f0; 1 drivers +v0x2412690_0 .net "AnorB", 0 0, L_0x250b120; 1 drivers +v0x2412740_0 .net "AorB", 0 0, L_0x250c5e0; 1 drivers +v0x2412820_0 .net "AxorB", 0 0, L_0x250c960; 1 drivers +v0x24128d0_0 .net "B", 0 0, L_0x250c4c0; 1 drivers +v0x2412990_0 .alias "Command", 2 0, v0x2463430_0; +v0x2412a10_0 .net "OrNorXorOut", 0 0, L_0x250d360; 1 drivers +v0x2412a90_0 .net "XorNor", 0 0, L_0x250cde0; 1 drivers +v0x2412b60_0 .net "nXor", 0 0, L_0x250c850; 1 drivers +L_0x250cf60 .part C4, 2, 1; +L_0x250d530 .part C4, 0, 1; +S_0x2411fe0 .scope module, "mux0" "TwoInMux" 2 83, 2 8, S_0x24119a0; + .timescale -9 -12; +L_0x250cac0/d .functor NOT 1, L_0x250cf60, C4<0>, C4<0>, C4<0>; +L_0x250cac0 .delay (10000,10000,10000) L_0x250cac0/d; +L_0x250cb80/d .functor AND 1, L_0x250c960, L_0x250cac0, C4<1>, C4<1>; +L_0x250cb80 .delay (20000,20000,20000) L_0x250cb80/d; +L_0x250cc90/d .functor AND 1, L_0x250b120, L_0x250cf60, C4<1>, C4<1>; +L_0x250cc90 .delay (20000,20000,20000) L_0x250cc90/d; +L_0x250cde0/d .functor OR 1, L_0x250cb80, L_0x250cc90, C4<0>, C4<0>; +L_0x250cde0 .delay (20000,20000,20000) L_0x250cde0/d; +v0x24120d0_0 .net "S", 0 0, L_0x250cf60; 1 drivers +v0x2412190_0 .alias "in0", 0 0, v0x2412820_0; +v0x2412230_0 .alias "in1", 0 0, v0x2412690_0; +v0x24122d0_0 .net "nS", 0 0, L_0x250cac0; 1 drivers +v0x2412350_0 .net "out0", 0 0, L_0x250cb80; 1 drivers +v0x24123f0_0 .net "out1", 0 0, L_0x250cc90; 1 drivers +v0x24124d0_0 .alias "outfinal", 0 0, v0x2412a90_0; +S_0x2411a90 .scope module, "mux1" "TwoInMux" 2 84, 2 8, S_0x24119a0; + .timescale -9 -12; +L_0x250d000/d .functor NOT 1, L_0x250d530, C4<0>, C4<0>, C4<0>; +L_0x250d000 .delay (10000,10000,10000) L_0x250d000/d; +L_0x250d0c0/d .functor AND 1, L_0x250cde0, L_0x250d000, C4<1>, C4<1>; +L_0x250d0c0 .delay (20000,20000,20000) L_0x250d0c0/d; +L_0x250d210/d .functor AND 1, L_0x250c5e0, L_0x250d530, C4<1>, C4<1>; +L_0x250d210 .delay (20000,20000,20000) L_0x250d210/d; +L_0x250d360/d .functor OR 1, L_0x250d0c0, L_0x250d210, C4<0>, C4<0>; +L_0x250d360 .delay (20000,20000,20000) L_0x250d360/d; +v0x2411b80_0 .net "S", 0 0, L_0x250d530; 1 drivers +v0x2411c00_0 .alias "in0", 0 0, v0x2412a90_0; +v0x2411ca0_0 .alias "in1", 0 0, v0x2412740_0; +v0x2411d40_0 .net "nS", 0 0, L_0x250d000; 1 drivers +v0x2411dc0_0 .net "out0", 0 0, L_0x250d0c0; 1 drivers +v0x2411e60_0 .net "out1", 0 0, L_0x250d210; 1 drivers +v0x2411f40_0 .alias "outfinal", 0 0, v0x2412a10_0; +S_0x24104a0 .scope generate, "orbits[17]" "orbits[17]" 2 196, 2 196, S_0x23d9540; + .timescale -9 -12; +P_0x24101b8 .param/l "i" 2 196, +C4<010001>; +S_0x24105d0 .scope module, "attempt" "OrNorXor" 2 198, 2 64, S_0x24104a0; + .timescale -9 -12; +L_0x250d800/d .functor NOR 1, L_0x250e980, L_0x250d670, C4<0>, C4<0>; +L_0x250d800 .delay (10000,10000,10000) L_0x250d800/d; +L_0x250d8f0/d .functor NOT 1, L_0x250d800, C4<0>, C4<0>, C4<0>; +L_0x250d8f0 .delay (10000,10000,10000) L_0x250d8f0/d; +L_0x250da00/d .functor NAND 1, L_0x250e980, L_0x250d670, C4<1>, C4<1>; +L_0x250da00 .delay (10000,10000,10000) L_0x250da00/d; +L_0x250db60/d .functor NAND 1, L_0x250da00, L_0x250d8f0, C4<1>, C4<1>; +L_0x250db60 .delay (10000,10000,10000) L_0x250db60/d; +L_0x250dc70/d .functor NOT 1, L_0x250db60, C4<0>, C4<0>, C4<0>; +L_0x250dc70 .delay (10000,10000,10000) L_0x250dc70/d; +v0x2411180_0 .net "A", 0 0, L_0x250e980; 1 drivers +v0x2411220_0 .net "AnandB", 0 0, L_0x250da00; 1 drivers +v0x24112c0_0 .net "AnorB", 0 0, L_0x250d800; 1 drivers +v0x2411370_0 .net "AorB", 0 0, L_0x250d8f0; 1 drivers +v0x2411450_0 .net "AxorB", 0 0, L_0x250dc70; 1 drivers +v0x2411500_0 .net "B", 0 0, L_0x250d670; 1 drivers +v0x24115c0_0 .alias "Command", 2 0, v0x2463430_0; +v0x2411640_0 .net "OrNorXorOut", 0 0, L_0x250e670; 1 drivers +v0x24116c0_0 .net "XorNor", 0 0, L_0x250e0f0; 1 drivers +v0x2411790_0 .net "nXor", 0 0, L_0x250db60; 1 drivers +L_0x250e270 .part C4, 2, 1; +L_0x250e840 .part C4, 0, 1; +S_0x2410c10 .scope module, "mux0" "TwoInMux" 2 83, 2 8, S_0x24105d0; + .timescale -9 -12; +L_0x250ddd0/d .functor NOT 1, L_0x250e270, C4<0>, C4<0>, C4<0>; +L_0x250ddd0 .delay (10000,10000,10000) L_0x250ddd0/d; +L_0x250de90/d .functor AND 1, L_0x250dc70, L_0x250ddd0, C4<1>, C4<1>; +L_0x250de90 .delay (20000,20000,20000) L_0x250de90/d; +L_0x250dfa0/d .functor AND 1, L_0x250d800, L_0x250e270, C4<1>, C4<1>; +L_0x250dfa0 .delay (20000,20000,20000) L_0x250dfa0/d; +L_0x250e0f0/d .functor OR 1, L_0x250de90, L_0x250dfa0, C4<0>, C4<0>; +L_0x250e0f0 .delay (20000,20000,20000) L_0x250e0f0/d; +v0x2410d00_0 .net "S", 0 0, L_0x250e270; 1 drivers +v0x2410dc0_0 .alias "in0", 0 0, v0x2411450_0; +v0x2410e60_0 .alias "in1", 0 0, v0x24112c0_0; +v0x2410f00_0 .net "nS", 0 0, L_0x250ddd0; 1 drivers +v0x2410f80_0 .net "out0", 0 0, L_0x250de90; 1 drivers +v0x2411020_0 .net "out1", 0 0, L_0x250dfa0; 1 drivers +v0x2411100_0 .alias "outfinal", 0 0, v0x24116c0_0; +S_0x24106c0 .scope module, "mux1" "TwoInMux" 2 84, 2 8, S_0x24105d0; + .timescale -9 -12; +L_0x250e310/d .functor NOT 1, L_0x250e840, C4<0>, C4<0>, C4<0>; +L_0x250e310 .delay (10000,10000,10000) L_0x250e310/d; +L_0x250e3d0/d .functor AND 1, L_0x250e0f0, L_0x250e310, C4<1>, C4<1>; +L_0x250e3d0 .delay (20000,20000,20000) L_0x250e3d0/d; +L_0x250e520/d .functor AND 1, L_0x250d8f0, L_0x250e840, C4<1>, C4<1>; +L_0x250e520 .delay (20000,20000,20000) L_0x250e520/d; +L_0x250e670/d .functor OR 1, L_0x250e3d0, L_0x250e520, C4<0>, C4<0>; +L_0x250e670 .delay (20000,20000,20000) L_0x250e670/d; +v0x24107b0_0 .net "S", 0 0, L_0x250e840; 1 drivers +v0x2410830_0 .alias "in0", 0 0, v0x24116c0_0; +v0x24108d0_0 .alias "in1", 0 0, v0x2411370_0; +v0x2410970_0 .net "nS", 0 0, L_0x250e310; 1 drivers +v0x24109f0_0 .net "out0", 0 0, L_0x250e3d0; 1 drivers +v0x2410a90_0 .net "out1", 0 0, L_0x250e520; 1 drivers +v0x2410b70_0 .alias "outfinal", 0 0, v0x2411640_0; +S_0x240f0d0 .scope generate, "orbits[18]" "orbits[18]" 2 196, 2 196, S_0x23d9540; + .timescale -9 -12; +P_0x240ede8 .param/l "i" 2 196, +C4<010010>; +S_0x240f200 .scope module, "attempt" "OrNorXor" 2 198, 2 64, S_0x240f0d0; + .timescale -9 -12; +L_0x250d710/d .functor NOR 1, L_0x250ea20, L_0x250eac0, C4<0>, C4<0>; +L_0x250d710 .delay (10000,10000,10000) L_0x250d710/d; +L_0x250ebc0/d .functor NOT 1, L_0x250d710, C4<0>, C4<0>, C4<0>; +L_0x250ebc0 .delay (10000,10000,10000) L_0x250ebc0/d; +L_0x250ecf0/d .functor NAND 1, L_0x250ea20, L_0x250eac0, C4<1>, C4<1>; +L_0x250ecf0 .delay (10000,10000,10000) L_0x250ecf0/d; +L_0x250ee50/d .functor NAND 1, L_0x250ecf0, L_0x250ebc0, C4<1>, C4<1>; +L_0x250ee50 .delay (10000,10000,10000) L_0x250ee50/d; +L_0x250ef60/d .functor NOT 1, L_0x250ee50, C4<0>, C4<0>, C4<0>; +L_0x250ef60 .delay (10000,10000,10000) L_0x250ef60/d; +v0x240fdb0_0 .net "A", 0 0, L_0x250ea20; 1 drivers +v0x240fe50_0 .net "AnandB", 0 0, L_0x250ecf0; 1 drivers +v0x240fef0_0 .net "AnorB", 0 0, L_0x250d710; 1 drivers +v0x240ffa0_0 .net "AorB", 0 0, L_0x250ebc0; 1 drivers +v0x2410080_0 .net "AxorB", 0 0, L_0x250ef60; 1 drivers +v0x2410130_0 .net "B", 0 0, L_0x250eac0; 1 drivers +v0x24101f0_0 .alias "Command", 2 0, v0x2463430_0; +v0x2410270_0 .net "OrNorXorOut", 0 0, L_0x250f960; 1 drivers +v0x24102f0_0 .net "XorNor", 0 0, L_0x250f3e0; 1 drivers +v0x24103c0_0 .net "nXor", 0 0, L_0x250ee50; 1 drivers +L_0x250f560 .part C4, 2, 1; +L_0x250fb30 .part C4, 0, 1; +S_0x240f840 .scope module, "mux0" "TwoInMux" 2 83, 2 8, S_0x240f200; + .timescale -9 -12; +L_0x250f0c0/d .functor NOT 1, L_0x250f560, C4<0>, C4<0>, C4<0>; +L_0x250f0c0 .delay (10000,10000,10000) L_0x250f0c0/d; +L_0x250f180/d .functor AND 1, L_0x250ef60, L_0x250f0c0, C4<1>, C4<1>; +L_0x250f180 .delay (20000,20000,20000) L_0x250f180/d; +L_0x250f290/d .functor AND 1, L_0x250d710, L_0x250f560, C4<1>, C4<1>; +L_0x250f290 .delay (20000,20000,20000) L_0x250f290/d; +L_0x250f3e0/d .functor OR 1, L_0x250f180, L_0x250f290, C4<0>, C4<0>; +L_0x250f3e0 .delay (20000,20000,20000) L_0x250f3e0/d; +v0x240f930_0 .net "S", 0 0, L_0x250f560; 1 drivers +v0x240f9f0_0 .alias "in0", 0 0, v0x2410080_0; +v0x240fa90_0 .alias "in1", 0 0, v0x240fef0_0; +v0x240fb30_0 .net "nS", 0 0, L_0x250f0c0; 1 drivers +v0x240fbb0_0 .net "out0", 0 0, L_0x250f180; 1 drivers +v0x240fc50_0 .net "out1", 0 0, L_0x250f290; 1 drivers +v0x240fd30_0 .alias "outfinal", 0 0, v0x24102f0_0; +S_0x240f2f0 .scope module, "mux1" "TwoInMux" 2 84, 2 8, S_0x240f200; + .timescale -9 -12; +L_0x250f600/d .functor NOT 1, L_0x250fb30, C4<0>, C4<0>, C4<0>; +L_0x250f600 .delay (10000,10000,10000) L_0x250f600/d; +L_0x250f6c0/d .functor AND 1, L_0x250f3e0, L_0x250f600, C4<1>, C4<1>; +L_0x250f6c0 .delay (20000,20000,20000) L_0x250f6c0/d; +L_0x250f810/d .functor AND 1, L_0x250ebc0, L_0x250fb30, C4<1>, C4<1>; +L_0x250f810 .delay (20000,20000,20000) L_0x250f810/d; +L_0x250f960/d .functor OR 1, L_0x250f6c0, L_0x250f810, C4<0>, C4<0>; +L_0x250f960 .delay (20000,20000,20000) L_0x250f960/d; +v0x240f3e0_0 .net "S", 0 0, L_0x250fb30; 1 drivers +v0x240f460_0 .alias "in0", 0 0, v0x24102f0_0; +v0x240f500_0 .alias "in1", 0 0, v0x240ffa0_0; +v0x240f5a0_0 .net "nS", 0 0, L_0x250f600; 1 drivers +v0x240f620_0 .net "out0", 0 0, L_0x250f6c0; 1 drivers +v0x240f6c0_0 .net "out1", 0 0, L_0x250f810; 1 drivers +v0x240f7a0_0 .alias "outfinal", 0 0, v0x2410270_0; +S_0x240ddc0 .scope generate, "orbits[19]" "orbits[19]" 2 196, 2 196, S_0x23d9540; + .timescale -9 -12; +P_0x240dad8 .param/l "i" 2 196, +C4<010011>; +S_0x240def0 .scope module, "attempt" "OrNorXor" 2 198, 2 64, S_0x240ddc0; + .timescale -9 -12; +L_0x250eb60/d .functor NOR 1, L_0x2510f70, L_0x250fc70, C4<0>, C4<0>; +L_0x250eb60 .delay (10000,10000,10000) L_0x250eb60/d; +L_0x250fec0/d .functor NOT 1, L_0x250eb60, C4<0>, C4<0>, C4<0>; +L_0x250fec0 .delay (10000,10000,10000) L_0x250fec0/d; +L_0x250fff0/d .functor NAND 1, L_0x2510f70, L_0x250fc70, C4<1>, C4<1>; +L_0x250fff0 .delay (10000,10000,10000) L_0x250fff0/d; +L_0x2510150/d .functor NAND 1, L_0x250fff0, L_0x250fec0, C4<1>, C4<1>; +L_0x2510150 .delay (10000,10000,10000) L_0x2510150/d; +L_0x2510260/d .functor NOT 1, L_0x2510150, C4<0>, C4<0>, C4<0>; +L_0x2510260 .delay (10000,10000,10000) L_0x2510260/d; +v0x240eaa0_0 .net "A", 0 0, L_0x2510f70; 1 drivers +v0x240eb40_0 .net "AnandB", 0 0, L_0x250fff0; 1 drivers +v0x240ebe0_0 .net "AnorB", 0 0, L_0x250eb60; 1 drivers +v0x240ec60_0 .net "AorB", 0 0, L_0x250fec0; 1 drivers +v0x240ece0_0 .net "AxorB", 0 0, L_0x2510260; 1 drivers +v0x240ed60_0 .net "B", 0 0, L_0x250fc70; 1 drivers +v0x240ee20_0 .alias "Command", 2 0, v0x2463430_0; +v0x240eea0_0 .net "OrNorXorOut", 0 0, L_0x2510c60; 1 drivers +v0x240ef20_0 .net "XorNor", 0 0, L_0x25106e0; 1 drivers +v0x240eff0_0 .net "nXor", 0 0, L_0x2510150; 1 drivers +L_0x2510860 .part C4, 2, 1; +L_0x2510e30 .part C4, 0, 1; +S_0x240e530 .scope module, "mux0" "TwoInMux" 2 83, 2 8, S_0x240def0; + .timescale -9 -12; +L_0x25103c0/d .functor NOT 1, L_0x2510860, C4<0>, C4<0>, C4<0>; +L_0x25103c0 .delay (10000,10000,10000) L_0x25103c0/d; +L_0x2510480/d .functor AND 1, L_0x2510260, L_0x25103c0, C4<1>, C4<1>; +L_0x2510480 .delay (20000,20000,20000) L_0x2510480/d; +L_0x2510590/d .functor AND 1, L_0x250eb60, L_0x2510860, C4<1>, C4<1>; +L_0x2510590 .delay (20000,20000,20000) L_0x2510590/d; +L_0x25106e0/d .functor OR 1, L_0x2510480, L_0x2510590, C4<0>, C4<0>; +L_0x25106e0 .delay (20000,20000,20000) L_0x25106e0/d; +v0x240e620_0 .net "S", 0 0, L_0x2510860; 1 drivers +v0x240e6e0_0 .alias "in0", 0 0, v0x240ece0_0; +v0x240e780_0 .alias "in1", 0 0, v0x240ebe0_0; +v0x240e820_0 .net "nS", 0 0, L_0x25103c0; 1 drivers +v0x240e8a0_0 .net "out0", 0 0, L_0x2510480; 1 drivers +v0x240e940_0 .net "out1", 0 0, L_0x2510590; 1 drivers +v0x240ea20_0 .alias "outfinal", 0 0, v0x240ef20_0; +S_0x240dfe0 .scope module, "mux1" "TwoInMux" 2 84, 2 8, S_0x240def0; + .timescale -9 -12; +L_0x2510900/d .functor NOT 1, L_0x2510e30, C4<0>, C4<0>, C4<0>; +L_0x2510900 .delay (10000,10000,10000) L_0x2510900/d; +L_0x25109c0/d .functor AND 1, L_0x25106e0, L_0x2510900, C4<1>, C4<1>; +L_0x25109c0 .delay (20000,20000,20000) L_0x25109c0/d; +L_0x2510b10/d .functor AND 1, L_0x250fec0, L_0x2510e30, C4<1>, C4<1>; +L_0x2510b10 .delay (20000,20000,20000) L_0x2510b10/d; +L_0x2510c60/d .functor OR 1, L_0x25109c0, L_0x2510b10, C4<0>, C4<0>; +L_0x2510c60 .delay (20000,20000,20000) L_0x2510c60/d; +v0x240e0d0_0 .net "S", 0 0, L_0x2510e30; 1 drivers +v0x240e150_0 .alias "in0", 0 0, v0x240ef20_0; +v0x240e1f0_0 .alias "in1", 0 0, v0x240ec60_0; +v0x240e290_0 .net "nS", 0 0, L_0x2510900; 1 drivers +v0x240e310_0 .net "out0", 0 0, L_0x25109c0; 1 drivers +v0x240e3b0_0 .net "out1", 0 0, L_0x2510b10; 1 drivers +v0x240e490_0 .alias "outfinal", 0 0, v0x240eea0_0; +S_0x240cab0 .scope generate, "orbits[20]" "orbits[20]" 2 196, 2 196, S_0x23d9540; + .timescale -9 -12; +P_0x240c7c8 .param/l "i" 2 196, +C4<010100>; +S_0x240cbe0 .scope module, "attempt" "OrNorXor" 2 198, 2 64, S_0x240cab0; + .timescale -9 -12; +L_0x250fd10/d .functor NOR 1, L_0x2511010, L_0x25110b0, C4<0>, C4<0>; +L_0x250fd10 .delay (10000,10000,10000) L_0x250fd10/d; +L_0x25111e0/d .functor NOT 1, L_0x250fd10, C4<0>, C4<0>, C4<0>; +L_0x25111e0 .delay (10000,10000,10000) L_0x25111e0/d; +L_0x25112f0/d .functor NAND 1, L_0x2511010, L_0x25110b0, C4<1>, C4<1>; +L_0x25112f0 .delay (10000,10000,10000) L_0x25112f0/d; +L_0x2511450/d .functor NAND 1, L_0x25112f0, L_0x25111e0, C4<1>, C4<1>; +L_0x2511450 .delay (10000,10000,10000) L_0x2511450/d; +L_0x2511560/d .functor NOT 1, L_0x2511450, C4<0>, C4<0>, C4<0>; +L_0x2511560 .delay (10000,10000,10000) L_0x2511560/d; +v0x240d790_0 .net "A", 0 0, L_0x2511010; 1 drivers +v0x240d830_0 .net "AnandB", 0 0, L_0x25112f0; 1 drivers +v0x240d8d0_0 .net "AnorB", 0 0, L_0x250fd10; 1 drivers +v0x240d950_0 .net "AorB", 0 0, L_0x25111e0; 1 drivers +v0x240d9d0_0 .net "AxorB", 0 0, L_0x2511560; 1 drivers +v0x240da50_0 .net "B", 0 0, L_0x25110b0; 1 drivers +v0x240db10_0 .alias "Command", 2 0, v0x2463430_0; +v0x240db90_0 .net "OrNorXorOut", 0 0, L_0x2511f60; 1 drivers +v0x240dc10_0 .net "XorNor", 0 0, L_0x25119e0; 1 drivers +v0x240dce0_0 .net "nXor", 0 0, L_0x2511450; 1 drivers +L_0x2511b60 .part C4, 2, 1; +L_0x2512130 .part C4, 0, 1; +S_0x240d220 .scope module, "mux0" "TwoInMux" 2 83, 2 8, S_0x240cbe0; + .timescale -9 -12; +L_0x25116c0/d .functor NOT 1, L_0x2511b60, C4<0>, C4<0>, C4<0>; +L_0x25116c0 .delay (10000,10000,10000) L_0x25116c0/d; +L_0x2511780/d .functor AND 1, L_0x2511560, L_0x25116c0, C4<1>, C4<1>; +L_0x2511780 .delay (20000,20000,20000) L_0x2511780/d; +L_0x2511890/d .functor AND 1, L_0x250fd10, L_0x2511b60, C4<1>, C4<1>; +L_0x2511890 .delay (20000,20000,20000) L_0x2511890/d; +L_0x25119e0/d .functor OR 1, L_0x2511780, L_0x2511890, C4<0>, C4<0>; +L_0x25119e0 .delay (20000,20000,20000) L_0x25119e0/d; +v0x240d310_0 .net "S", 0 0, L_0x2511b60; 1 drivers +v0x240d3d0_0 .alias "in0", 0 0, v0x240d9d0_0; +v0x240d470_0 .alias "in1", 0 0, v0x240d8d0_0; +v0x240d510_0 .net "nS", 0 0, L_0x25116c0; 1 drivers +v0x240d590_0 .net "out0", 0 0, L_0x2511780; 1 drivers +v0x240d630_0 .net "out1", 0 0, L_0x2511890; 1 drivers +v0x240d710_0 .alias "outfinal", 0 0, v0x240dc10_0; +S_0x240ccd0 .scope module, "mux1" "TwoInMux" 2 84, 2 8, S_0x240cbe0; + .timescale -9 -12; +L_0x2511c00/d .functor NOT 1, L_0x2512130, C4<0>, C4<0>, C4<0>; +L_0x2511c00 .delay (10000,10000,10000) L_0x2511c00/d; +L_0x2511cc0/d .functor AND 1, L_0x25119e0, L_0x2511c00, C4<1>, C4<1>; +L_0x2511cc0 .delay (20000,20000,20000) L_0x2511cc0/d; +L_0x2511e10/d .functor AND 1, L_0x25111e0, L_0x2512130, C4<1>, C4<1>; +L_0x2511e10 .delay (20000,20000,20000) L_0x2511e10/d; +L_0x2511f60/d .functor OR 1, L_0x2511cc0, L_0x2511e10, C4<0>, C4<0>; +L_0x2511f60 .delay (20000,20000,20000) L_0x2511f60/d; +v0x240cdc0_0 .net "S", 0 0, L_0x2512130; 1 drivers +v0x240ce40_0 .alias "in0", 0 0, v0x240dc10_0; +v0x240cee0_0 .alias "in1", 0 0, v0x240d950_0; +v0x240cf80_0 .net "nS", 0 0, L_0x2511c00; 1 drivers +v0x240d000_0 .net "out0", 0 0, L_0x2511cc0; 1 drivers +v0x240d0a0_0 .net "out1", 0 0, L_0x2511e10; 1 drivers +v0x240d180_0 .alias "outfinal", 0 0, v0x240db90_0; +S_0x240b7a0 .scope generate, "orbits[21]" "orbits[21]" 2 196, 2 196, S_0x23d9540; + .timescale -9 -12; +P_0x240b4b8 .param/l "i" 2 196, +C4<010101>; +S_0x240b8d0 .scope module, "attempt" "OrNorXor" 2 198, 2 64, S_0x240b7a0; + .timescale -9 -12; +L_0x2511150/d .functor NOR 1, L_0x2513580, L_0x2512270, C4<0>, C4<0>; +L_0x2511150 .delay (10000,10000,10000) L_0x2511150/d; +L_0x25124f0/d .functor NOT 1, L_0x2511150, C4<0>, C4<0>, C4<0>; +L_0x25124f0 .delay (10000,10000,10000) L_0x25124f0/d; +L_0x2512600/d .functor NAND 1, L_0x2513580, L_0x2512270, C4<1>, C4<1>; +L_0x2512600 .delay (10000,10000,10000) L_0x2512600/d; +L_0x2512760/d .functor NAND 1, L_0x2512600, L_0x25124f0, C4<1>, C4<1>; +L_0x2512760 .delay (10000,10000,10000) L_0x2512760/d; +L_0x2512870/d .functor NOT 1, L_0x2512760, C4<0>, C4<0>, C4<0>; +L_0x2512870 .delay (10000,10000,10000) L_0x2512870/d; +v0x240c480_0 .net "A", 0 0, L_0x2513580; 1 drivers +v0x240c520_0 .net "AnandB", 0 0, L_0x2512600; 1 drivers +v0x240c5c0_0 .net "AnorB", 0 0, L_0x2511150; 1 drivers +v0x240c640_0 .net "AorB", 0 0, L_0x25124f0; 1 drivers +v0x240c6c0_0 .net "AxorB", 0 0, L_0x2512870; 1 drivers +v0x240c740_0 .net "B", 0 0, L_0x2512270; 1 drivers +v0x240c800_0 .alias "Command", 2 0, v0x2463430_0; +v0x240c880_0 .net "OrNorXorOut", 0 0, L_0x2513270; 1 drivers +v0x240c900_0 .net "XorNor", 0 0, L_0x2512cf0; 1 drivers +v0x240c9d0_0 .net "nXor", 0 0, L_0x2512760; 1 drivers +L_0x2512e70 .part C4, 2, 1; +L_0x2513440 .part C4, 0, 1; +S_0x240bf10 .scope module, "mux0" "TwoInMux" 2 83, 2 8, S_0x240b8d0; + .timescale -9 -12; +L_0x25129d0/d .functor NOT 1, L_0x2512e70, C4<0>, C4<0>, C4<0>; +L_0x25129d0 .delay (10000,10000,10000) L_0x25129d0/d; +L_0x2512a90/d .functor AND 1, L_0x2512870, L_0x25129d0, C4<1>, C4<1>; +L_0x2512a90 .delay (20000,20000,20000) L_0x2512a90/d; +L_0x2512ba0/d .functor AND 1, L_0x2511150, L_0x2512e70, C4<1>, C4<1>; +L_0x2512ba0 .delay (20000,20000,20000) L_0x2512ba0/d; +L_0x2512cf0/d .functor OR 1, L_0x2512a90, L_0x2512ba0, C4<0>, C4<0>; +L_0x2512cf0 .delay (20000,20000,20000) L_0x2512cf0/d; +v0x240c000_0 .net "S", 0 0, L_0x2512e70; 1 drivers +v0x240c0c0_0 .alias "in0", 0 0, v0x240c6c0_0; +v0x240c160_0 .alias "in1", 0 0, v0x240c5c0_0; +v0x240c200_0 .net "nS", 0 0, L_0x25129d0; 1 drivers +v0x240c280_0 .net "out0", 0 0, L_0x2512a90; 1 drivers +v0x240c320_0 .net "out1", 0 0, L_0x2512ba0; 1 drivers +v0x240c400_0 .alias "outfinal", 0 0, v0x240c900_0; +S_0x240b9c0 .scope module, "mux1" "TwoInMux" 2 84, 2 8, S_0x240b8d0; + .timescale -9 -12; +L_0x2512f10/d .functor NOT 1, L_0x2513440, C4<0>, C4<0>, C4<0>; +L_0x2512f10 .delay (10000,10000,10000) L_0x2512f10/d; +L_0x2512fd0/d .functor AND 1, L_0x2512cf0, L_0x2512f10, C4<1>, C4<1>; +L_0x2512fd0 .delay (20000,20000,20000) L_0x2512fd0/d; +L_0x2513120/d .functor AND 1, L_0x25124f0, L_0x2513440, C4<1>, C4<1>; +L_0x2513120 .delay (20000,20000,20000) L_0x2513120/d; +L_0x2513270/d .functor OR 1, L_0x2512fd0, L_0x2513120, C4<0>, C4<0>; +L_0x2513270 .delay (20000,20000,20000) L_0x2513270/d; +v0x240bab0_0 .net "S", 0 0, L_0x2513440; 1 drivers +v0x240bb30_0 .alias "in0", 0 0, v0x240c900_0; +v0x240bbd0_0 .alias "in1", 0 0, v0x240c640_0; +v0x240bc70_0 .net "nS", 0 0, L_0x2512f10; 1 drivers +v0x240bcf0_0 .net "out0", 0 0, L_0x2512fd0; 1 drivers +v0x240bd90_0 .net "out1", 0 0, L_0x2513120; 1 drivers +v0x240be70_0 .alias "outfinal", 0 0, v0x240c880_0; +S_0x240a490 .scope generate, "orbits[22]" "orbits[22]" 2 196, 2 196, S_0x23d9540; + .timescale -9 -12; +P_0x240a118 .param/l "i" 2 196, +C4<010110>; +S_0x240a5c0 .scope module, "attempt" "OrNorXor" 2 198, 2 64, S_0x240a490; + .timescale -9 -12; +L_0x2512310/d .functor NOR 1, L_0x2513620, L_0x25136c0, C4<0>, C4<0>; +L_0x2512310 .delay (10000,10000,10000) L_0x2512310/d; +L_0x2512400/d .functor NOT 1, L_0x2512310, C4<0>, C4<0>, C4<0>; +L_0x2512400 .delay (10000,10000,10000) L_0x2512400/d; +L_0x25138f0/d .functor NAND 1, L_0x2513620, L_0x25136c0, C4<1>, C4<1>; +L_0x25138f0 .delay (10000,10000,10000) L_0x25138f0/d; +L_0x2513a50/d .functor NAND 1, L_0x25138f0, L_0x2512400, C4<1>, C4<1>; +L_0x2513a50 .delay (10000,10000,10000) L_0x2513a50/d; +L_0x2513b60/d .functor NOT 1, L_0x2513a50, C4<0>, C4<0>, C4<0>; +L_0x2513b60 .delay (10000,10000,10000) L_0x2513b60/d; +v0x240b170_0 .net "A", 0 0, L_0x2513620; 1 drivers +v0x240b210_0 .net "AnandB", 0 0, L_0x25138f0; 1 drivers +v0x240b2b0_0 .net "AnorB", 0 0, L_0x2512310; 1 drivers +v0x240b330_0 .net "AorB", 0 0, L_0x2512400; 1 drivers +v0x240b3b0_0 .net "AxorB", 0 0, L_0x2513b60; 1 drivers +v0x240b430_0 .net "B", 0 0, L_0x25136c0; 1 drivers +v0x240b4f0_0 .alias "Command", 2 0, v0x2463430_0; +v0x240b570_0 .net "OrNorXorOut", 0 0, L_0x2514560; 1 drivers +v0x240b5f0_0 .net "XorNor", 0 0, L_0x2513fe0; 1 drivers +v0x240b6c0_0 .net "nXor", 0 0, L_0x2513a50; 1 drivers +L_0x2514160 .part C4, 2, 1; +L_0x2514730 .part C4, 0, 1; +S_0x240ac00 .scope module, "mux0" "TwoInMux" 2 83, 2 8, S_0x240a5c0; + .timescale -9 -12; +L_0x2513cc0/d .functor NOT 1, L_0x2514160, C4<0>, C4<0>, C4<0>; +L_0x2513cc0 .delay (10000,10000,10000) L_0x2513cc0/d; +L_0x2513d80/d .functor AND 1, L_0x2513b60, L_0x2513cc0, C4<1>, C4<1>; +L_0x2513d80 .delay (20000,20000,20000) L_0x2513d80/d; +L_0x2513e90/d .functor AND 1, L_0x2512310, L_0x2514160, C4<1>, C4<1>; +L_0x2513e90 .delay (20000,20000,20000) L_0x2513e90/d; +L_0x2513fe0/d .functor OR 1, L_0x2513d80, L_0x2513e90, C4<0>, C4<0>; +L_0x2513fe0 .delay (20000,20000,20000) L_0x2513fe0/d; +v0x240acf0_0 .net "S", 0 0, L_0x2514160; 1 drivers +v0x240adb0_0 .alias "in0", 0 0, v0x240b3b0_0; +v0x240ae50_0 .alias "in1", 0 0, v0x240b2b0_0; +v0x240aef0_0 .net "nS", 0 0, L_0x2513cc0; 1 drivers +v0x240af70_0 .net "out0", 0 0, L_0x2513d80; 1 drivers +v0x240b010_0 .net "out1", 0 0, L_0x2513e90; 1 drivers +v0x240b0f0_0 .alias "outfinal", 0 0, v0x240b5f0_0; +S_0x240a6b0 .scope module, "mux1" "TwoInMux" 2 84, 2 8, S_0x240a5c0; + .timescale -9 -12; +L_0x2514200/d .functor NOT 1, L_0x2514730, C4<0>, C4<0>, C4<0>; +L_0x2514200 .delay (10000,10000,10000) L_0x2514200/d; +L_0x25142c0/d .functor AND 1, L_0x2513fe0, L_0x2514200, C4<1>, C4<1>; +L_0x25142c0 .delay (20000,20000,20000) L_0x25142c0/d; +L_0x2514410/d .functor AND 1, L_0x2512400, L_0x2514730, C4<1>, C4<1>; +L_0x2514410 .delay (20000,20000,20000) L_0x2514410/d; +L_0x2514560/d .functor OR 1, L_0x25142c0, L_0x2514410, C4<0>, C4<0>; +L_0x2514560 .delay (20000,20000,20000) L_0x2514560/d; +v0x240a7a0_0 .net "S", 0 0, L_0x2514730; 1 drivers +v0x240a820_0 .alias "in0", 0 0, v0x240b5f0_0; +v0x240a8c0_0 .alias "in1", 0 0, v0x240b330_0; +v0x240a960_0 .net "nS", 0 0, L_0x2514200; 1 drivers +v0x240a9e0_0 .net "out0", 0 0, L_0x25142c0; 1 drivers +v0x240aa80_0 .net "out1", 0 0, L_0x2514410; 1 drivers +v0x240ab60_0 .alias "outfinal", 0 0, v0x240b570_0; +S_0x24090f0 .scope generate, "orbits[23]" "orbits[23]" 2 196, 2 196, S_0x23d9540; + .timescale -9 -12; +P_0x2408e08 .param/l "i" 2 196, +C4<010111>; +S_0x2409220 .scope module, "attempt" "OrNorXor" 2 198, 2 64, S_0x24090f0; + .timescale -9 -12; +L_0x2513760/d .functor NOR 1, L_0x2515b70, L_0x2514870, C4<0>, C4<0>; +L_0x2513760 .delay (10000,10000,10000) L_0x2513760/d; +L_0x2514ae0/d .functor NOT 1, L_0x2513760, C4<0>, C4<0>, C4<0>; +L_0x2514ae0 .delay (10000,10000,10000) L_0x2514ae0/d; +L_0x2514bf0/d .functor NAND 1, L_0x2515b70, L_0x2514870, C4<1>, C4<1>; +L_0x2514bf0 .delay (10000,10000,10000) L_0x2514bf0/d; +L_0x2514d50/d .functor NAND 1, L_0x2514bf0, L_0x2514ae0, C4<1>, C4<1>; +L_0x2514d50 .delay (10000,10000,10000) L_0x2514d50/d; +L_0x2514e60/d .functor NOT 1, L_0x2514d50, C4<0>, C4<0>, C4<0>; +L_0x2514e60 .delay (10000,10000,10000) L_0x2514e60/d; +v0x2409dd0_0 .net "A", 0 0, L_0x2515b70; 1 drivers +v0x2409e70_0 .net "AnandB", 0 0, L_0x2514bf0; 1 drivers +v0x2409f10_0 .net "AnorB", 0 0, L_0x2513760; 1 drivers +v0x2409f90_0 .net "AorB", 0 0, L_0x2514ae0; 1 drivers +v0x240a010_0 .net "AxorB", 0 0, L_0x2514e60; 1 drivers +v0x240a090_0 .net "B", 0 0, L_0x2514870; 1 drivers +v0x240a150_0 .alias "Command", 2 0, v0x2463430_0; +v0x2405790_0 .net "OrNorXorOut", 0 0, L_0x2515860; 1 drivers +v0x240a2e0_0 .net "XorNor", 0 0, L_0x25152e0; 1 drivers +v0x240a3b0_0 .net "nXor", 0 0, L_0x2514d50; 1 drivers +L_0x2515460 .part C4, 2, 1; +L_0x2515a30 .part C4, 0, 1; +S_0x2409860 .scope module, "mux0" "TwoInMux" 2 83, 2 8, S_0x2409220; + .timescale -9 -12; +L_0x2514fc0/d .functor NOT 1, L_0x2515460, C4<0>, C4<0>, C4<0>; +L_0x2514fc0 .delay (10000,10000,10000) L_0x2514fc0/d; +L_0x2515080/d .functor AND 1, L_0x2514e60, L_0x2514fc0, C4<1>, C4<1>; +L_0x2515080 .delay (20000,20000,20000) L_0x2515080/d; +L_0x2515190/d .functor AND 1, L_0x2513760, L_0x2515460, C4<1>, C4<1>; +L_0x2515190 .delay (20000,20000,20000) L_0x2515190/d; +L_0x25152e0/d .functor OR 1, L_0x2515080, L_0x2515190, C4<0>, C4<0>; +L_0x25152e0 .delay (20000,20000,20000) L_0x25152e0/d; +v0x2409950_0 .net "S", 0 0, L_0x2515460; 1 drivers +v0x2409a10_0 .alias "in0", 0 0, v0x240a010_0; +v0x2409ab0_0 .alias "in1", 0 0, v0x2409f10_0; +v0x2409b50_0 .net "nS", 0 0, L_0x2514fc0; 1 drivers +v0x2409bd0_0 .net "out0", 0 0, L_0x2515080; 1 drivers +v0x2409c70_0 .net "out1", 0 0, L_0x2515190; 1 drivers +v0x2409d50_0 .alias "outfinal", 0 0, v0x240a2e0_0; +S_0x2409310 .scope module, "mux1" "TwoInMux" 2 84, 2 8, S_0x2409220; + .timescale -9 -12; +L_0x2515500/d .functor NOT 1, L_0x2515a30, C4<0>, C4<0>, C4<0>; +L_0x2515500 .delay (10000,10000,10000) L_0x2515500/d; +L_0x25155c0/d .functor AND 1, L_0x25152e0, L_0x2515500, C4<1>, C4<1>; +L_0x25155c0 .delay (20000,20000,20000) L_0x25155c0/d; +L_0x2515710/d .functor AND 1, L_0x2514ae0, L_0x2515a30, C4<1>, C4<1>; +L_0x2515710 .delay (20000,20000,20000) L_0x2515710/d; +L_0x2515860/d .functor OR 1, L_0x25155c0, L_0x2515710, C4<0>, C4<0>; +L_0x2515860 .delay (20000,20000,20000) L_0x2515860/d; +v0x2409400_0 .net "S", 0 0, L_0x2515a30; 1 drivers +v0x2409480_0 .alias "in0", 0 0, v0x240a2e0_0; +v0x2409520_0 .alias "in1", 0 0, v0x2409f90_0; +v0x24095c0_0 .net "nS", 0 0, L_0x2515500; 1 drivers +v0x2409640_0 .net "out0", 0 0, L_0x25155c0; 1 drivers +v0x24096e0_0 .net "out1", 0 0, L_0x2515710; 1 drivers +v0x24097c0_0 .alias "outfinal", 0 0, v0x2405790_0; +S_0x2407de0 .scope generate, "orbits[24]" "orbits[24]" 2 196, 2 196, S_0x23d9540; + .timescale -9 -12; +P_0x2407af8 .param/l "i" 2 196, +C4<011000>; +S_0x2407f10 .scope module, "attempt" "OrNorXor" 2 198, 2 64, S_0x2407de0; + .timescale -9 -12; +L_0x2514910/d .functor NOR 1, L_0x2515c10, L_0x2515cb0, C4<0>, C4<0>; +L_0x2514910 .delay (10000,10000,10000) L_0x2514910/d; +L_0x2514a00/d .functor NOT 1, L_0x2514910, C4<0>, C4<0>, C4<0>; +L_0x2514a00 .delay (10000,10000,10000) L_0x2514a00/d; +L_0x2515ef0/d .functor NAND 1, L_0x2515c10, L_0x2515cb0, C4<1>, C4<1>; +L_0x2515ef0 .delay (10000,10000,10000) L_0x2515ef0/d; +L_0x2516050/d .functor NAND 1, L_0x2515ef0, L_0x2514a00, C4<1>, C4<1>; +L_0x2516050 .delay (10000,10000,10000) L_0x2516050/d; +L_0x2516160/d .functor NOT 1, L_0x2516050, C4<0>, C4<0>, C4<0>; +L_0x2516160 .delay (10000,10000,10000) L_0x2516160/d; +v0x2408ac0_0 .net "A", 0 0, L_0x2515c10; 1 drivers +v0x2408b60_0 .net "AnandB", 0 0, L_0x2515ef0; 1 drivers +v0x2408c00_0 .net "AnorB", 0 0, L_0x2514910; 1 drivers +v0x2408c80_0 .net "AorB", 0 0, L_0x2514a00; 1 drivers +v0x2408d00_0 .net "AxorB", 0 0, L_0x2516160; 1 drivers +v0x2408d80_0 .net "B", 0 0, L_0x2515cb0; 1 drivers +v0x2408e40_0 .alias "Command", 2 0, v0x2463430_0; +v0x2408ec0_0 .net "OrNorXorOut", 0 0, L_0x2516b60; 1 drivers +v0x2408f40_0 .net "XorNor", 0 0, L_0x25165e0; 1 drivers +v0x2409010_0 .net "nXor", 0 0, L_0x2516050; 1 drivers +L_0x2516760 .part C4, 2, 1; +L_0x2516d30 .part C4, 0, 1; +S_0x2408550 .scope module, "mux0" "TwoInMux" 2 83, 2 8, S_0x2407f10; + .timescale -9 -12; +L_0x25162c0/d .functor NOT 1, L_0x2516760, C4<0>, C4<0>, C4<0>; +L_0x25162c0 .delay (10000,10000,10000) L_0x25162c0/d; +L_0x2516380/d .functor AND 1, L_0x2516160, L_0x25162c0, C4<1>, C4<1>; +L_0x2516380 .delay (20000,20000,20000) L_0x2516380/d; +L_0x2516490/d .functor AND 1, L_0x2514910, L_0x2516760, C4<1>, C4<1>; +L_0x2516490 .delay (20000,20000,20000) L_0x2516490/d; +L_0x25165e0/d .functor OR 1, L_0x2516380, L_0x2516490, C4<0>, C4<0>; +L_0x25165e0 .delay (20000,20000,20000) L_0x25165e0/d; +v0x2408640_0 .net "S", 0 0, L_0x2516760; 1 drivers +v0x2408700_0 .alias "in0", 0 0, v0x2408d00_0; +v0x24087a0_0 .alias "in1", 0 0, v0x2408c00_0; +v0x2408840_0 .net "nS", 0 0, L_0x25162c0; 1 drivers +v0x24088c0_0 .net "out0", 0 0, L_0x2516380; 1 drivers +v0x2408960_0 .net "out1", 0 0, L_0x2516490; 1 drivers +v0x2408a40_0 .alias "outfinal", 0 0, v0x2408f40_0; +S_0x2408000 .scope module, "mux1" "TwoInMux" 2 84, 2 8, S_0x2407f10; + .timescale -9 -12; +L_0x2516800/d .functor NOT 1, L_0x2516d30, C4<0>, C4<0>, C4<0>; +L_0x2516800 .delay (10000,10000,10000) L_0x2516800/d; +L_0x25168c0/d .functor AND 1, L_0x25165e0, L_0x2516800, C4<1>, C4<1>; +L_0x25168c0 .delay (20000,20000,20000) L_0x25168c0/d; +L_0x2516a10/d .functor AND 1, L_0x2514a00, L_0x2516d30, C4<1>, C4<1>; +L_0x2516a10 .delay (20000,20000,20000) L_0x2516a10/d; +L_0x2516b60/d .functor OR 1, L_0x25168c0, L_0x2516a10, C4<0>, C4<0>; +L_0x2516b60 .delay (20000,20000,20000) L_0x2516b60/d; +v0x24080f0_0 .net "S", 0 0, L_0x2516d30; 1 drivers +v0x2408170_0 .alias "in0", 0 0, v0x2408f40_0; +v0x2408210_0 .alias "in1", 0 0, v0x2408c80_0; +v0x24082b0_0 .net "nS", 0 0, L_0x2516800; 1 drivers +v0x2408330_0 .net "out0", 0 0, L_0x25168c0; 1 drivers +v0x24083d0_0 .net "out1", 0 0, L_0x2516a10; 1 drivers +v0x24084b0_0 .alias "outfinal", 0 0, v0x2408ec0_0; +S_0x2406ad0 .scope generate, "orbits[25]" "orbits[25]" 2 196, 2 196, S_0x23d9540; + .timescale -9 -12; +P_0x24067e8 .param/l "i" 2 196, +C4<011001>; +S_0x2406c00 .scope module, "attempt" "OrNorXor" 2 198, 2 64, S_0x2406ad0; + .timescale -9 -12; +L_0x2515d50/d .functor NOR 1, L_0x2518170, L_0x2516e70, C4<0>, C4<0>; +L_0x2515d50 .delay (10000,10000,10000) L_0x2515d50/d; +L_0x25170c0/d .functor NOT 1, L_0x2515d50, C4<0>, C4<0>, C4<0>; +L_0x25170c0 .delay (10000,10000,10000) L_0x25170c0/d; +L_0x25171f0/d .functor NAND 1, L_0x2518170, L_0x2516e70, C4<1>, C4<1>; +L_0x25171f0 .delay (10000,10000,10000) L_0x25171f0/d; +L_0x2517350/d .functor NAND 1, L_0x25171f0, L_0x25170c0, C4<1>, C4<1>; +L_0x2517350 .delay (10000,10000,10000) L_0x2517350/d; +L_0x2517460/d .functor NOT 1, L_0x2517350, C4<0>, C4<0>, C4<0>; +L_0x2517460 .delay (10000,10000,10000) L_0x2517460/d; +v0x24077b0_0 .net "A", 0 0, L_0x2518170; 1 drivers +v0x2407850_0 .net "AnandB", 0 0, L_0x25171f0; 1 drivers +v0x24078f0_0 .net "AnorB", 0 0, L_0x2515d50; 1 drivers +v0x2407970_0 .net "AorB", 0 0, L_0x25170c0; 1 drivers +v0x24079f0_0 .net "AxorB", 0 0, L_0x2517460; 1 drivers +v0x2407a70_0 .net "B", 0 0, L_0x2516e70; 1 drivers +v0x2407b30_0 .alias "Command", 2 0, v0x2463430_0; +v0x2407bb0_0 .net "OrNorXorOut", 0 0, L_0x2517e60; 1 drivers +v0x2407c30_0 .net "XorNor", 0 0, L_0x25178e0; 1 drivers +v0x2407d00_0 .net "nXor", 0 0, L_0x2517350; 1 drivers +L_0x2517a60 .part C4, 2, 1; +L_0x2518030 .part C4, 0, 1; +S_0x2407240 .scope module, "mux0" "TwoInMux" 2 83, 2 8, S_0x2406c00; + .timescale -9 -12; +L_0x25175c0/d .functor NOT 1, L_0x2517a60, C4<0>, C4<0>, C4<0>; +L_0x25175c0 .delay (10000,10000,10000) L_0x25175c0/d; +L_0x2517680/d .functor AND 1, L_0x2517460, L_0x25175c0, C4<1>, C4<1>; +L_0x2517680 .delay (20000,20000,20000) L_0x2517680/d; +L_0x2517790/d .functor AND 1, L_0x2515d50, L_0x2517a60, C4<1>, C4<1>; +L_0x2517790 .delay (20000,20000,20000) L_0x2517790/d; +L_0x25178e0/d .functor OR 1, L_0x2517680, L_0x2517790, C4<0>, C4<0>; +L_0x25178e0 .delay (20000,20000,20000) L_0x25178e0/d; +v0x2407330_0 .net "S", 0 0, L_0x2517a60; 1 drivers +v0x24073f0_0 .alias "in0", 0 0, v0x24079f0_0; +v0x2407490_0 .alias "in1", 0 0, v0x24078f0_0; +v0x2407530_0 .net "nS", 0 0, L_0x25175c0; 1 drivers +v0x24075b0_0 .net "out0", 0 0, L_0x2517680; 1 drivers +v0x2407650_0 .net "out1", 0 0, L_0x2517790; 1 drivers +v0x2407730_0 .alias "outfinal", 0 0, v0x2407c30_0; +S_0x2406cf0 .scope module, "mux1" "TwoInMux" 2 84, 2 8, S_0x2406c00; + .timescale -9 -12; +L_0x2517b00/d .functor NOT 1, L_0x2518030, C4<0>, C4<0>, C4<0>; +L_0x2517b00 .delay (10000,10000,10000) L_0x2517b00/d; +L_0x2517bc0/d .functor AND 1, L_0x25178e0, L_0x2517b00, C4<1>, C4<1>; +L_0x2517bc0 .delay (20000,20000,20000) L_0x2517bc0/d; +L_0x2517d10/d .functor AND 1, L_0x25170c0, L_0x2518030, C4<1>, C4<1>; +L_0x2517d10 .delay (20000,20000,20000) L_0x2517d10/d; +L_0x2517e60/d .functor OR 1, L_0x2517bc0, L_0x2517d10, C4<0>, C4<0>; +L_0x2517e60 .delay (20000,20000,20000) L_0x2517e60/d; +v0x2406de0_0 .net "S", 0 0, L_0x2518030; 1 drivers +v0x2406e60_0 .alias "in0", 0 0, v0x2407c30_0; +v0x2406f00_0 .alias "in1", 0 0, v0x2407970_0; +v0x2406fa0_0 .net "nS", 0 0, L_0x2517b00; 1 drivers +v0x2407020_0 .net "out0", 0 0, L_0x2517bc0; 1 drivers +v0x24070c0_0 .net "out1", 0 0, L_0x2517d10; 1 drivers +v0x24071a0_0 .alias "outfinal", 0 0, v0x2407bb0_0; +S_0x24059a0 .scope generate, "orbits[26]" "orbits[26]" 2 196, 2 196, S_0x23d9540; + .timescale -9 -12; +P_0x2308908 .param/l "i" 2 196, +C4<011010>; +S_0x2405a90 .scope module, "attempt" "OrNorXor" 2 198, 2 64, S_0x24059a0; + .timescale -9 -12; +L_0x2516f10/d .functor NOR 1, L_0x2518210, L_0x25182b0, C4<0>, C4<0>; +L_0x2516f10 .delay (10000,10000,10000) L_0x2516f10/d; +L_0x2517000/d .functor NOT 1, L_0x2516f10, C4<0>, C4<0>, C4<0>; +L_0x2517000 .delay (10000,10000,10000) L_0x2517000/d; +L_0x25184e0/d .functor NAND 1, L_0x2518210, L_0x25182b0, C4<1>, C4<1>; +L_0x25184e0 .delay (10000,10000,10000) L_0x25184e0/d; +L_0x2518640/d .functor NAND 1, L_0x25184e0, L_0x2517000, C4<1>, C4<1>; +L_0x2518640 .delay (10000,10000,10000) L_0x2518640/d; +L_0x2518750/d .functor NOT 1, L_0x2518640, C4<0>, C4<0>, C4<0>; +L_0x2518750 .delay (10000,10000,10000) L_0x2518750/d; +v0x24064a0_0 .net "A", 0 0, L_0x2518210; 1 drivers +v0x2406540_0 .net "AnandB", 0 0, L_0x25184e0; 1 drivers +v0x24065e0_0 .net "AnorB", 0 0, L_0x2516f10; 1 drivers +v0x2406660_0 .net "AorB", 0 0, L_0x2517000; 1 drivers +v0x24066e0_0 .net "AxorB", 0 0, L_0x2518750; 1 drivers +v0x2406760_0 .net "B", 0 0, L_0x25182b0; 1 drivers +v0x2406820_0 .alias "Command", 2 0, v0x2463430_0; +v0x24068a0_0 .net "OrNorXorOut", 0 0, L_0x2519170; 1 drivers +v0x2406920_0 .net "XorNor", 0 0, L_0x2518bf0; 1 drivers +v0x24069f0_0 .net "nXor", 0 0, L_0x2518640; 1 drivers +L_0x2518d70 .part C4, 2, 1; +L_0x2519340 .part C4, 0, 1; +S_0x2405ff0 .scope module, "mux0" "TwoInMux" 2 83, 2 8, S_0x2405a90; + .timescale -9 -12; +L_0x25188b0/d .functor NOT 1, L_0x2518d70, C4<0>, C4<0>, C4<0>; +L_0x25188b0 .delay (10000,10000,10000) L_0x25188b0/d; +L_0x2518970/d .functor AND 1, L_0x2518750, L_0x25188b0, C4<1>, C4<1>; +L_0x2518970 .delay (20000,20000,20000) L_0x2518970/d; +L_0x2518a80/d .functor AND 1, L_0x2516f10, L_0x2518d70, C4<1>, C4<1>; +L_0x2518a80 .delay (20000,20000,20000) L_0x2518a80/d; +L_0x2518bf0/d .functor OR 1, L_0x2518970, L_0x2518a80, C4<0>, C4<0>; +L_0x2518bf0 .delay (20000,20000,20000) L_0x2518bf0/d; +v0x24060e0_0 .net "S", 0 0, L_0x2518d70; 1 drivers +v0x2406160_0 .alias "in0", 0 0, v0x24066e0_0; +v0x24061e0_0 .alias "in1", 0 0, v0x24065e0_0; +v0x2406260_0 .net "nS", 0 0, L_0x25188b0; 1 drivers +v0x24062e0_0 .net "out0", 0 0, L_0x2518970; 1 drivers +v0x2406360_0 .net "out1", 0 0, L_0x2518a80; 1 drivers +v0x2406420_0 .alias "outfinal", 0 0, v0x2406920_0; +S_0x2405b80 .scope module, "mux1" "TwoInMux" 2 84, 2 8, S_0x2405a90; + .timescale -9 -12; +L_0x2518e10/d .functor NOT 1, L_0x2519340, C4<0>, C4<0>, C4<0>; +L_0x2518e10 .delay (10000,10000,10000) L_0x2518e10/d; +L_0x2518ed0/d .functor AND 1, L_0x2518bf0, L_0x2518e10, C4<1>, C4<1>; +L_0x2518ed0 .delay (20000,20000,20000) L_0x2518ed0/d; +L_0x2519020/d .functor AND 1, L_0x2517000, L_0x2519340, C4<1>, C4<1>; +L_0x2519020 .delay (20000,20000,20000) L_0x2519020/d; +L_0x2519170/d .functor OR 1, L_0x2518ed0, L_0x2519020, C4<0>, C4<0>; +L_0x2519170 .delay (20000,20000,20000) L_0x2519170/d; +v0x2405c70_0 .net "S", 0 0, L_0x2519340; 1 drivers +v0x2405cf0_0 .alias "in0", 0 0, v0x2406920_0; +v0x2405d70_0 .alias "in1", 0 0, v0x2406660_0; +v0x2405df0_0 .net "nS", 0 0, L_0x2518e10; 1 drivers +v0x2405e70_0 .net "out0", 0 0, L_0x2518ed0; 1 drivers +v0x2405ef0_0 .net "out1", 0 0, L_0x2519020; 1 drivers +v0x2405f70_0 .alias "outfinal", 0 0, v0x24068a0_0; +S_0x2404950 .scope generate, "orbits[27]" "orbits[27]" 2 196, 2 196, S_0x23d9540; + .timescale -9 -12; +P_0x22d5938 .param/l "i" 2 196, +C4<011011>; +S_0x2404a40 .scope module, "attempt" "OrNorXor" 2 198, 2 64, S_0x2404950; + .timescale -9 -12; +L_0x2518350/d .functor NOR 1, L_0x251a780, L_0x2519480, C4<0>, C4<0>; +L_0x2518350 .delay (10000,10000,10000) L_0x2518350/d; +L_0x2519700/d .functor NOT 1, L_0x2518350, C4<0>, C4<0>, C4<0>; +L_0x2519700 .delay (10000,10000,10000) L_0x2519700/d; +L_0x2519810/d .functor NAND 1, L_0x251a780, L_0x2519480, C4<1>, C4<1>; +L_0x2519810 .delay (10000,10000,10000) L_0x2519810/d; +L_0x2519970/d .functor NAND 1, L_0x2519810, L_0x2519700, C4<1>, C4<1>; +L_0x2519970 .delay (10000,10000,10000) L_0x2519970/d; +L_0x2519a80/d .functor NOT 1, L_0x2519970, C4<0>, C4<0>, C4<0>; +L_0x2519a80 .delay (10000,10000,10000) L_0x2519a80/d; +v0x2405410_0 .net "A", 0 0, L_0x251a780; 1 drivers +v0x2405490_0 .net "AnandB", 0 0, L_0x2519810; 1 drivers +v0x2405510_0 .net "AnorB", 0 0, L_0x2518350; 1 drivers +v0x2405590_0 .net "AorB", 0 0, L_0x2519700; 1 drivers +v0x2405610_0 .net "AxorB", 0 0, L_0x2519a80; 1 drivers +v0x2405690_0 .net "B", 0 0, L_0x2519480; 1 drivers +v0x2405710_0 .alias "Command", 2 0, v0x2463430_0; +v0x2405820_0 .net "OrNorXorOut", 0 0, L_0x251a470; 1 drivers +v0x24058a0_0 .net "XorNor", 0 0, L_0x2519f00; 1 drivers +v0x2405920_0 .net "nXor", 0 0, L_0x2519970; 1 drivers +L_0x251a080 .part C4, 2, 1; +L_0x251a640 .part C4, 0, 1; +S_0x2404fa0 .scope module, "mux0" "TwoInMux" 2 83, 2 8, S_0x2404a40; + .timescale -9 -12; +L_0x2519be0/d .functor NOT 1, L_0x251a080, C4<0>, C4<0>, C4<0>; +L_0x2519be0 .delay (10000,10000,10000) L_0x2519be0/d; +L_0x2519ca0/d .functor AND 1, L_0x2519a80, L_0x2519be0, C4<1>, C4<1>; +L_0x2519ca0 .delay (20000,20000,20000) L_0x2519ca0/d; +L_0x2519db0/d .functor AND 1, L_0x2518350, L_0x251a080, C4<1>, C4<1>; +L_0x2519db0 .delay (20000,20000,20000) L_0x2519db0/d; +L_0x2519f00/d .functor OR 1, L_0x2519ca0, L_0x2519db0, C4<0>, C4<0>; +L_0x2519f00 .delay (20000,20000,20000) L_0x2519f00/d; +v0x2405090_0 .net "S", 0 0, L_0x251a080; 1 drivers +v0x2405110_0 .alias "in0", 0 0, v0x2405610_0; +v0x2405190_0 .alias "in1", 0 0, v0x2405510_0; +v0x2405210_0 .net "nS", 0 0, L_0x2519be0; 1 drivers +v0x2405290_0 .net "out0", 0 0, L_0x2519ca0; 1 drivers +v0x2405310_0 .net "out1", 0 0, L_0x2519db0; 1 drivers +v0x2405390_0 .alias "outfinal", 0 0, v0x24058a0_0; +S_0x2404b30 .scope module, "mux1" "TwoInMux" 2 84, 2 8, S_0x2404a40; + .timescale -9 -12; +L_0x251a120/d .functor NOT 1, L_0x251a640, C4<0>, C4<0>, C4<0>; +L_0x251a120 .delay (10000,10000,10000) L_0x251a120/d; +L_0x251a1e0/d .functor AND 1, L_0x2519f00, L_0x251a120, C4<1>, C4<1>; +L_0x251a1e0 .delay (20000,20000,20000) L_0x251a1e0/d; +L_0x22ec750/d .functor AND 1, L_0x2519700, L_0x251a640, C4<1>, C4<1>; +L_0x22ec750 .delay (20000,20000,20000) L_0x22ec750/d; +L_0x251a470/d .functor OR 1, L_0x251a1e0, L_0x22ec750, C4<0>, C4<0>; +L_0x251a470 .delay (20000,20000,20000) L_0x251a470/d; +v0x2404c20_0 .net "S", 0 0, L_0x251a640; 1 drivers +v0x2404ca0_0 .alias "in0", 0 0, v0x24058a0_0; +v0x2404d20_0 .alias "in1", 0 0, v0x2405590_0; +v0x2404da0_0 .net "nS", 0 0, L_0x251a120; 1 drivers +v0x2404e20_0 .net "out0", 0 0, L_0x251a1e0; 1 drivers +v0x2404ea0_0 .net "out1", 0 0, L_0x22ec750; 1 drivers +v0x2404f20_0 .alias "outfinal", 0 0, v0x2405820_0; +S_0x2403990 .scope generate, "orbits[28]" "orbits[28]" 2 196, 2 196, S_0x23d9540; + .timescale -9 -12; +P_0x228a328 .param/l "i" 2 196, +C4<011100>; +S_0x2403a80 .scope module, "attempt" "OrNorXor" 2 198, 2 64, S_0x2403990; + .timescale -9 -12; +L_0x2519520/d .functor NOR 1, L_0x251a820, L_0x251a8c0, C4<0>, C4<0>; +L_0x2519520 .delay (10000,10000,10000) L_0x2519520/d; +L_0x2519610/d .functor NOT 1, L_0x2519520, C4<0>, C4<0>, C4<0>; +L_0x2519610 .delay (10000,10000,10000) L_0x2519610/d; +L_0x251ab00/d .functor NAND 1, L_0x251a820, L_0x251a8c0, C4<1>, C4<1>; +L_0x251ab00 .delay (10000,10000,10000) L_0x251ab00/d; +L_0x251ac60/d .functor NAND 1, L_0x251ab00, L_0x2519610, C4<1>, C4<1>; +L_0x251ac60 .delay (10000,10000,10000) L_0x251ac60/d; +L_0x251ad70/d .functor NOT 1, L_0x251ac60, C4<0>, C4<0>, C4<0>; +L_0x251ad70 .delay (10000,10000,10000) L_0x251ad70/d; +v0x2404450_0 .net "A", 0 0, L_0x251a820; 1 drivers +v0x24044d0_0 .net "AnandB", 0 0, L_0x251ab00; 1 drivers +v0x2404550_0 .net "AnorB", 0 0, L_0x2519520; 1 drivers +v0x24045d0_0 .net "AorB", 0 0, L_0x2519610; 1 drivers +v0x2404650_0 .net "AxorB", 0 0, L_0x251ad70; 1 drivers +v0x24046d0_0 .net "B", 0 0, L_0x251a8c0; 1 drivers +v0x2404750_0 .alias "Command", 2 0, v0x2463430_0; +v0x24047d0_0 .net "OrNorXorOut", 0 0, L_0x251b760; 1 drivers +v0x2404850_0 .net "XorNor", 0 0, L_0x251b1f0; 1 drivers +v0x24048d0_0 .net "nXor", 0 0, L_0x251ac60; 1 drivers +L_0x251b370 .part C4, 2, 1; +L_0x251b930 .part C4, 0, 1; +S_0x2403fe0 .scope module, "mux0" "TwoInMux" 2 83, 2 8, S_0x2403a80; + .timescale -9 -12; +L_0x251aed0/d .functor NOT 1, L_0x251b370, C4<0>, C4<0>, C4<0>; +L_0x251aed0 .delay (10000,10000,10000) L_0x251aed0/d; +L_0x251af90/d .functor AND 1, L_0x251ad70, L_0x251aed0, C4<1>, C4<1>; +L_0x251af90 .delay (20000,20000,20000) L_0x251af90/d; +L_0x251b0a0/d .functor AND 1, L_0x2519520, L_0x251b370, C4<1>, C4<1>; +L_0x251b0a0 .delay (20000,20000,20000) L_0x251b0a0/d; +L_0x251b1f0/d .functor OR 1, L_0x251af90, L_0x251b0a0, C4<0>, C4<0>; +L_0x251b1f0 .delay (20000,20000,20000) L_0x251b1f0/d; +v0x24040d0_0 .net "S", 0 0, L_0x251b370; 1 drivers +v0x2404150_0 .alias "in0", 0 0, v0x2404650_0; +v0x24041d0_0 .alias "in1", 0 0, v0x2404550_0; +v0x2404250_0 .net "nS", 0 0, L_0x251aed0; 1 drivers +v0x24042d0_0 .net "out0", 0 0, L_0x251af90; 1 drivers +v0x2404350_0 .net "out1", 0 0, L_0x251b0a0; 1 drivers +v0x24043d0_0 .alias "outfinal", 0 0, v0x2404850_0; +S_0x2403b70 .scope module, "mux1" "TwoInMux" 2 84, 2 8, S_0x2403a80; + .timescale -9 -12; +L_0x251b410/d .functor NOT 1, L_0x251b930, C4<0>, C4<0>, C4<0>; +L_0x251b410 .delay (10000,10000,10000) L_0x251b410/d; +L_0x251b4d0/d .functor AND 1, L_0x251b1f0, L_0x251b410, C4<1>, C4<1>; +L_0x251b4d0 .delay (20000,20000,20000) L_0x251b4d0/d; +L_0x22c76b0/d .functor AND 1, L_0x2519610, L_0x251b930, C4<1>, C4<1>; +L_0x22c76b0 .delay (20000,20000,20000) L_0x22c76b0/d; +L_0x251b760/d .functor OR 1, L_0x251b4d0, L_0x22c76b0, C4<0>, C4<0>; +L_0x251b760 .delay (20000,20000,20000) L_0x251b760/d; +v0x2403c60_0 .net "S", 0 0, L_0x251b930; 1 drivers +v0x2403ce0_0 .alias "in0", 0 0, v0x2404850_0; +v0x2403d60_0 .alias "in1", 0 0, v0x24045d0_0; +v0x2403de0_0 .net "nS", 0 0, L_0x251b410; 1 drivers +v0x2403e60_0 .net "out0", 0 0, L_0x251b4d0; 1 drivers +v0x2403ee0_0 .net "out1", 0 0, L_0x22c76b0; 1 drivers +v0x2403f60_0 .alias "outfinal", 0 0, v0x24047d0_0; +S_0x24029d0 .scope generate, "orbits[29]" "orbits[29]" 2 196, 2 196, S_0x23d9540; + .timescale -9 -12; +P_0x23cb8b8 .param/l "i" 2 196, +C4<011101>; +S_0x2402ac0 .scope module, "attempt" "OrNorXor" 2 198, 2 64, S_0x24029d0; + .timescale -9 -12; +L_0x251a960/d .functor NOR 1, L_0x251cdf0, L_0x251ba70, C4<0>, C4<0>; +L_0x251a960 .delay (10000,10000,10000) L_0x251a960/d; +L_0x251bd20/d .functor NOT 1, L_0x251a960, C4<0>, C4<0>, C4<0>; +L_0x251bd20 .delay (10000,10000,10000) L_0x251bd20/d; +L_0x251be10/d .functor NAND 1, L_0x251cdf0, L_0x251ba70, C4<1>, C4<1>; +L_0x251be10 .delay (10000,10000,10000) L_0x251be10/d; +L_0x251bf70/d .functor NAND 1, L_0x251be10, L_0x251bd20, C4<1>, C4<1>; +L_0x251bf70 .delay (10000,10000,10000) L_0x251bf70/d; +L_0x251c080/d .functor NOT 1, L_0x251bf70, C4<0>, C4<0>, C4<0>; +L_0x251c080 .delay (10000,10000,10000) L_0x251c080/d; +v0x2403490_0 .net "A", 0 0, L_0x251cdf0; 1 drivers +v0x2403510_0 .net "AnandB", 0 0, L_0x251be10; 1 drivers +v0x2403590_0 .net "AnorB", 0 0, L_0x251a960; 1 drivers +v0x2403610_0 .net "AorB", 0 0, L_0x251bd20; 1 drivers +v0x2403690_0 .net "AxorB", 0 0, L_0x251c080; 1 drivers +v0x2403710_0 .net "B", 0 0, L_0x251ba70; 1 drivers +v0x2403790_0 .alias "Command", 2 0, v0x2463430_0; +v0x2403810_0 .net "OrNorXorOut", 0 0, L_0x251cae0; 1 drivers +v0x2403890_0 .net "XorNor", 0 0, L_0x251c500; 1 drivers +v0x2403910_0 .net "nXor", 0 0, L_0x251bf70; 1 drivers +L_0x251c680 .part C4, 2, 1; +L_0x251ccb0 .part C4, 0, 1; +S_0x2403020 .scope module, "mux0" "TwoInMux" 2 83, 2 8, S_0x2402ac0; + .timescale -9 -12; +L_0x251c1e0/d .functor NOT 1, L_0x251c680, C4<0>, C4<0>, C4<0>; +L_0x251c1e0 .delay (10000,10000,10000) L_0x251c1e0/d; +L_0x251c2a0/d .functor AND 1, L_0x251c080, L_0x251c1e0, C4<1>, C4<1>; +L_0x251c2a0 .delay (20000,20000,20000) L_0x251c2a0/d; +L_0x251c3b0/d .functor AND 1, L_0x251a960, L_0x251c680, C4<1>, C4<1>; +L_0x251c3b0 .delay (20000,20000,20000) L_0x251c3b0/d; +L_0x251c500/d .functor OR 1, L_0x251c2a0, L_0x251c3b0, C4<0>, C4<0>; +L_0x251c500 .delay (20000,20000,20000) L_0x251c500/d; +v0x2403110_0 .net "S", 0 0, L_0x251c680; 1 drivers +v0x2403190_0 .alias "in0", 0 0, v0x2403690_0; +v0x2403210_0 .alias "in1", 0 0, v0x2403590_0; +v0x2403290_0 .net "nS", 0 0, L_0x251c1e0; 1 drivers +v0x2403310_0 .net "out0", 0 0, L_0x251c2a0; 1 drivers +v0x2403390_0 .net "out1", 0 0, L_0x251c3b0; 1 drivers +v0x2403410_0 .alias "outfinal", 0 0, v0x2403890_0; +S_0x2402bb0 .scope module, "mux1" "TwoInMux" 2 84, 2 8, S_0x2402ac0; + .timescale -9 -12; +L_0x251c720/d .functor NOT 1, L_0x251ccb0, C4<0>, C4<0>, C4<0>; +L_0x251c720 .delay (10000,10000,10000) L_0x251c720/d; +L_0x251c800/d .functor AND 1, L_0x251c500, L_0x251c720, C4<1>, C4<1>; +L_0x251c800 .delay (20000,20000,20000) L_0x251c800/d; +L_0x251c970/d .functor AND 1, L_0x251bd20, L_0x251ccb0, C4<1>, C4<1>; +L_0x251c970 .delay (20000,20000,20000) L_0x251c970/d; +L_0x251cae0/d .functor OR 1, L_0x251c800, L_0x251c970, C4<0>, C4<0>; +L_0x251cae0 .delay (20000,20000,20000) L_0x251cae0/d; +v0x2402ca0_0 .net "S", 0 0, L_0x251ccb0; 1 drivers +v0x2402d20_0 .alias "in0", 0 0, v0x2403890_0; +v0x2402da0_0 .alias "in1", 0 0, v0x2403610_0; +v0x2402e20_0 .net "nS", 0 0, L_0x251c720; 1 drivers +v0x2402ea0_0 .net "out0", 0 0, L_0x251c800; 1 drivers +v0x2402f20_0 .net "out1", 0 0, L_0x251c970; 1 drivers +v0x2402fa0_0 .alias "outfinal", 0 0, v0x2403810_0; +S_0x2101cb0 .scope generate, "orbits[30]" "orbits[30]" 2 196, 2 196, S_0x23d9540; + .timescale -9 -12; +P_0x23bff88 .param/l "i" 2 196, +C4<011110>; +S_0x20ff610 .scope module, "attempt" "OrNorXor" 2 198, 2 64, S_0x2101cb0; + .timescale -9 -12; +L_0x251bb10/d .functor NOR 1, L_0x251ce90, L_0x251cf30, C4<0>, C4<0>; +L_0x251bb10 .delay (10000,10000,10000) L_0x251bb10/d; +L_0x251bc00/d .functor NOT 1, L_0x251bb10, C4<0>, C4<0>, C4<0>; +L_0x251bc00 .delay (10000,10000,10000) L_0x251bc00/d; +L_0x251bcc0/d .functor NAND 1, L_0x251ce90, L_0x251cf30, C4<1>, C4<1>; +L_0x251bcc0 .delay (10000,10000,10000) L_0x251bcc0/d; +L_0x251d2c0/d .functor NAND 1, L_0x251bcc0, L_0x251bc00, C4<1>, C4<1>; +L_0x251d2c0 .delay (10000,10000,10000) L_0x251d2c0/d; +L_0x251d3d0/d .functor NOT 1, L_0x251d2c0, C4<0>, C4<0>, C4<0>; +L_0x251d3d0 .delay (10000,10000,10000) L_0x251d3d0/d; +v0x220f870_0 .net "A", 0 0, L_0x251ce90; 1 drivers +v0x220f910_0 .net "AnandB", 0 0, L_0x251bcc0; 1 drivers +v0x220f9b0_0 .net "AnorB", 0 0, L_0x251bb10; 1 drivers +v0x220fa30_0 .net "AorB", 0 0, L_0x251bc00; 1 drivers +v0x220fab0_0 .net "AxorB", 0 0, L_0x251d3d0; 1 drivers +v0x220fb30_0 .net "B", 0 0, L_0x251cf30; 1 drivers +v0x24027d0_0 .alias "Command", 2 0, v0x2463430_0; +v0x2402850_0 .net "OrNorXorOut", 0 0, L_0x251ddf0; 1 drivers +v0x24028d0_0 .net "XorNor", 0 0, L_0x251d850; 1 drivers +v0x2402950_0 .net "nXor", 0 0, L_0x251d2c0; 1 drivers +L_0x251d9d0 .part C4, 2, 1; +L_0x251dfc0 .part C4, 0, 1; +S_0x20c5730 .scope module, "mux0" "TwoInMux" 2 83, 2 8, S_0x20ff610; + .timescale -9 -12; +L_0x251d530/d .functor NOT 1, L_0x251d9d0, C4<0>, C4<0>, C4<0>; +L_0x251d530 .delay (10000,10000,10000) L_0x251d530/d; +L_0x251d5f0/d .functor AND 1, L_0x251d3d0, L_0x251d530, C4<1>, C4<1>; +L_0x251d5f0 .delay (20000,20000,20000) L_0x251d5f0/d; +L_0x251d700/d .functor AND 1, L_0x251bb10, L_0x251d9d0, C4<1>, C4<1>; +L_0x251d700 .delay (20000,20000,20000) L_0x251d700/d; +L_0x251d850/d .functor OR 1, L_0x251d5f0, L_0x251d700, C4<0>, C4<0>; +L_0x251d850 .delay (20000,20000,20000) L_0x251d850/d; +v0x20c5820_0 .net "S", 0 0, L_0x251d9d0; 1 drivers +v0x21174a0_0 .alias "in0", 0 0, v0x220fab0_0; +v0x2117540_0 .alias "in1", 0 0, v0x220f9b0_0; +v0x21175e0_0 .net "nS", 0 0, L_0x251d530; 1 drivers +v0x2117660_0 .net "out0", 0 0, L_0x251d5f0; 1 drivers +v0x220f750_0 .net "out1", 0 0, L_0x251d700; 1 drivers +v0x220f7f0_0 .alias "outfinal", 0 0, v0x24028d0_0; +S_0x20ff700 .scope module, "mux1" "TwoInMux" 2 84, 2 8, S_0x20ff610; + .timescale -9 -12; +L_0x251da70/d .functor NOT 1, L_0x251dfc0, C4<0>, C4<0>, C4<0>; +L_0x251da70 .delay (10000,10000,10000) L_0x251da70/d; +L_0x251db50/d .functor AND 1, L_0x251d850, L_0x251da70, C4<1>, C4<1>; +L_0x251db50 .delay (20000,20000,20000) L_0x251db50/d; +L_0x251dca0/d .functor AND 1, L_0x251bc00, L_0x251dfc0, C4<1>, C4<1>; +L_0x251dca0 .delay (20000,20000,20000) L_0x251dca0/d; +L_0x251ddf0/d .functor OR 1, L_0x251db50, L_0x251dca0, C4<0>, C4<0>; +L_0x251ddf0 .delay (20000,20000,20000) L_0x251ddf0/d; +v0x20ff7f0_0 .net "S", 0 0, L_0x251dfc0; 1 drivers +v0x2101da0_0 .alias "in0", 0 0, v0x24028d0_0; +v0x2106ec0_0 .alias "in1", 0 0, v0x220fa30_0; +v0x2106f60_0 .net "nS", 0 0, L_0x251da70; 1 drivers +v0x2106fe0_0 .net "out0", 0 0, L_0x251db50; 1 drivers +v0x2107080_0 .net "out1", 0 0, L_0x251dca0; 1 drivers +v0x20c5690_0 .alias "outfinal", 0 0, v0x2402850_0; +S_0x23d9630 .scope generate, "orbits[31]" "orbits[31]" 2 196, 2 196, S_0x23d9540; + .timescale -9 -12; +P_0x23ab248 .param/l "i" 2 196, +C4<011111>; +S_0x23dba40 .scope module, "attempt" "OrNorXor" 2 198, 2 64, S_0x23d9630; + .timescale -9 -12; +L_0x251cfd0/d .functor NOR 1, L_0x251f410, L_0x251e100, C4<0>, C4<0>; +L_0x251cfd0 .delay (10000,10000,10000) L_0x251cfd0/d; +L_0x251d0c0/d .functor NOT 1, L_0x251cfd0, C4<0>, C4<0>, C4<0>; +L_0x251d0c0 .delay (10000,10000,10000) L_0x251d0c0/d; +L_0x251e490/d .functor NAND 1, L_0x251f410, L_0x251e100, C4<1>, C4<1>; +L_0x251e490 .delay (10000,10000,10000) L_0x251e490/d; +L_0x251e5f0/d .functor NAND 1, L_0x251e490, L_0x251d0c0, C4<1>, C4<1>; +L_0x251e5f0 .delay (10000,10000,10000) L_0x251e5f0/d; +L_0x251e700/d .functor NOT 1, L_0x251e5f0, C4<0>, C4<0>, C4<0>; +L_0x251e700 .delay (10000,10000,10000) L_0x251e700/d; +v0x210f1b0_0 .net "A", 0 0, L_0x251f410; 1 drivers +v0x210f250_0 .net "AnandB", 0 0, L_0x251e490; 1 drivers +v0x210f2f0_0 .net "AnorB", 0 0, L_0x251cfd0; 1 drivers +v0x20fb450_0 .net "AorB", 0 0, L_0x251d0c0; 1 drivers +v0x20fb4d0_0 .net "AxorB", 0 0, L_0x251e700; 1 drivers +v0x20fb550_0 .net "B", 0 0, L_0x251e100; 1 drivers +v0x20fb5d0_0 .alias "Command", 2 0, v0x2463430_0; +v0x20fb650_0 .net "OrNorXorOut", 0 0, L_0x251f100; 1 drivers +v0x2101bb0_0 .net "XorNor", 0 0, L_0x251eb80; 1 drivers +v0x2101c30_0 .net "nXor", 0 0, L_0x251e5f0; 1 drivers +L_0x251ed00 .part C4, 2, 1; +L_0x251f2d0 .part C4, 0, 1; +S_0x20fe000 .scope module, "mux0" "TwoInMux" 2 83, 2 8, S_0x23dba40; + .timescale -9 -12; +L_0x251e860/d .functor NOT 1, L_0x251ed00, C4<0>, C4<0>, C4<0>; +L_0x251e860 .delay (10000,10000,10000) L_0x251e860/d; +L_0x251e920/d .functor AND 1, L_0x251e700, L_0x251e860, C4<1>, C4<1>; +L_0x251e920 .delay (20000,20000,20000) L_0x251e920/d; +L_0x251ea30/d .functor AND 1, L_0x251cfd0, L_0x251ed00, C4<1>, C4<1>; +L_0x251ea30 .delay (20000,20000,20000) L_0x251ea30/d; +L_0x251eb80/d .functor OR 1, L_0x251e920, L_0x251ea30, C4<0>, C4<0>; +L_0x251eb80 .delay (20000,20000,20000) L_0x251eb80/d; +v0x20fe0f0_0 .net "S", 0 0, L_0x251ed00; 1 drivers +v0x20fe1b0_0 .alias "in0", 0 0, v0x20fb4d0_0; +v0x2104cb0_0 .alias "in1", 0 0, v0x210f2f0_0; +v0x2104d50_0 .net "nS", 0 0, L_0x251e860; 1 drivers +v0x2104dd0_0 .net "out0", 0 0, L_0x251e920; 1 drivers +v0x2104e70_0 .net "out1", 0 0, L_0x251ea30; 1 drivers +v0x210f130_0 .alias "outfinal", 0 0, v0x2101bb0_0; +S_0x23dbb30 .scope module, "mux1" "TwoInMux" 2 84, 2 8, S_0x23dba40; + .timescale -9 -12; +L_0x251eda0/d .functor NOT 1, L_0x251f2d0, C4<0>, C4<0>, C4<0>; +L_0x251eda0 .delay (10000,10000,10000) L_0x251eda0/d; +L_0x251ee60/d .functor AND 1, L_0x251eb80, L_0x251eda0, C4<1>, C4<1>; +L_0x251ee60 .delay (20000,20000,20000) L_0x251ee60/d; +L_0x251efb0/d .functor AND 1, L_0x251d0c0, L_0x251f2d0, C4<1>, C4<1>; +L_0x251efb0 .delay (20000,20000,20000) L_0x251efb0/d; +L_0x251f100/d .functor OR 1, L_0x251ee60, L_0x251efb0, C4<0>, C4<0>; +L_0x251f100 .delay (20000,20000,20000) L_0x251f100/d; +v0x23ddf40_0 .net "S", 0 0, L_0x251f2d0; 1 drivers +v0x23ddfc0_0 .alias "in0", 0 0, v0x2101bb0_0; +v0x23de040_0 .alias "in1", 0 0, v0x20fb450_0; +v0x21093f0_0 .net "nS", 0 0, L_0x251eda0; 1 drivers +v0x2109470_0 .net "out0", 0 0, L_0x251ee60; 1 drivers +v0x2109510_0 .net "out1", 0 0, L_0x251efb0; 1 drivers +v0x21095b0_0 .alias "outfinal", 0 0, v0x20fb650_0; +S_0x23cdc00 .scope module, "ZeroMux0case" "FourInMux" 2 283, 2 24, S_0x22690e0; + .timescale -9 -12; +L_0x251f5f0/d .functor NOT 1, L_0x24b7340, C4<0>, C4<0>, C4<0>; +L_0x251f5f0 .delay (10000,10000,10000) L_0x251f5f0/d; +L_0x251f690/d .functor NOT 1, L_0x24b7470, C4<0>, C4<0>, C4<0>; +L_0x251f690 .delay (10000,10000,10000) L_0x251f690/d; +L_0x25208d0/d .functor NAND 1, L_0x251f5f0, L_0x251f690, L_0x24b75a0, C4<1>; +L_0x25208d0 .delay (10000,10000,10000) L_0x25208d0/d; +L_0x25209c0/d .functor NAND 1, L_0x24b7340, L_0x251f690, L_0x24b7640, C4<1>; +L_0x25209c0 .delay (10000,10000,10000) L_0x25209c0/d; +L_0x2520ab0/d .functor NAND 1, L_0x251f5f0, L_0x24b7470, L_0x24b76e0, C4<1>; +L_0x2520ab0 .delay (10000,10000,10000) L_0x2520ab0/d; +L_0x2520ba0/d .functor NAND 1, L_0x24b7340, L_0x24b7470, L_0x24b77d0, C4<1>; +L_0x2520ba0 .delay (10000,10000,10000) L_0x2520ba0/d; +L_0x2520c80/d .functor NAND 1, L_0x25208d0, L_0x25209c0, L_0x2520ab0, L_0x2520ba0; +L_0x2520c80 .delay (10000,10000,10000) L_0x2520c80/d; +v0x23cdcf0_0 .net "S0", 0 0, L_0x24b7340; 1 drivers +v0x23d0110_0 .net "S1", 0 0, L_0x24b7470; 1 drivers +v0x23d01b0_0 .net "in0", 0 0, L_0x24b75a0; 1 drivers +v0x23d0250_0 .net "in1", 0 0, L_0x24b7640; 1 drivers +v0x23d2620_0 .net "in2", 0 0, L_0x24b76e0; 1 drivers +v0x23d26c0_0 .net "in3", 0 0, L_0x24b77d0; 1 drivers +v0x23d2760_0 .net "nS0", 0 0, L_0x251f5f0; 1 drivers +v0x23d4b30_0 .net "nS1", 0 0, L_0x251f690; 1 drivers +v0x23d4bb0_0 .net "out", 0 0, L_0x2520c80; 1 drivers +v0x23d4c50_0 .net "out0", 0 0, L_0x25208d0; 1 drivers +v0x23d7040_0 .net "out1", 0 0, L_0x25209c0; 1 drivers +v0x23d70e0_0 .net "out2", 0 0, L_0x2520ab0; 1 drivers +v0x23d7180_0 .net "out3", 0 0, L_0x2520ba0; 1 drivers +S_0x23c22c0 .scope module, "OneMux0case" "FourInMux" 2 284, 2 24, S_0x22690e0; + .timescale -9 -12; +L_0x24b78c0/d .functor NOT 1, L_0x24b8090, C4<0>, C4<0>, C4<0>; +L_0x24b78c0 .delay (10000,10000,10000) L_0x24b78c0/d; +L_0x24b7970/d .functor NOT 1, L_0x24b81c0, C4<0>, C4<0>, C4<0>; +L_0x24b7970 .delay (10000,10000,10000) L_0x24b7970/d; +L_0x24b7a10/d .functor NAND 1, L_0x24b78c0, L_0x24b7970, L_0x24b82f0, C4<1>; +L_0x24b7a10 .delay (10000,10000,10000) L_0x24b7a10/d; +L_0x24b7b50/d .functor NAND 1, L_0x24b8090, L_0x24b7970, L_0x24b8390, C4<1>; +L_0x24b7b50 .delay (10000,10000,10000) L_0x24b7b50/d; +L_0x24b7c40/d .functor NAND 1, L_0x24b78c0, L_0x24b81c0, L_0x24b8430, C4<1>; +L_0x24b7c40 .delay (10000,10000,10000) L_0x24b7c40/d; +L_0x24b7d30/d .functor NAND 1, L_0x24b8090, L_0x24b81c0, L_0x24b8520, C4<1>; +L_0x24b7d30 .delay (10000,10000,10000) L_0x24b7d30/d; +L_0x24b7e10/d .functor NAND 1, L_0x24b7a10, L_0x24b7b50, L_0x24b7c40, L_0x24b7d30; +L_0x24b7e10 .delay (10000,10000,10000) L_0x24b7e10/d; +v0x23c23b0_0 .net "S0", 0 0, L_0x24b8090; 1 drivers +v0x23c47c0_0 .net "S1", 0 0, L_0x24b81c0; 1 drivers +v0x23c4860_0 .net "in0", 0 0, L_0x24b82f0; 1 drivers +v0x23c4900_0 .net "in1", 0 0, L_0x24b8390; 1 drivers +v0x23c6cc0_0 .net "in2", 0 0, L_0x24b8430; 1 drivers +v0x23c6d60_0 .net "in3", 0 0, L_0x24b8520; 1 drivers +v0x23c6e00_0 .net "nS0", 0 0, L_0x24b78c0; 1 drivers +v0x23c91e0_0 .net "nS1", 0 0, L_0x24b7970; 1 drivers +v0x23c9260_0 .net "out", 0 0, L_0x24b7e10; 1 drivers +v0x23c9300_0 .net "out0", 0 0, L_0x24b7a10; 1 drivers +v0x23cb6f0_0 .net "out1", 0 0, L_0x24b7b50; 1 drivers +v0x23cb790_0 .net "out2", 0 0, L_0x24b7c40; 1 drivers +v0x23cb830_0 .net "out3", 0 0, L_0x24b7d30; 1 drivers +S_0x23bb3c0 .scope module, "TwoMux0case" "TwoInMux" 2 285, 2 8, S_0x22690e0; + .timescale -9 -12; +L_0x24b8610/d .functor NOT 1, L_0x249f290, C4<0>, C4<0>, C4<0>; +L_0x24b8610 .delay (10000,10000,10000) L_0x24b8610/d; +L_0x24b86c0/d .functor AND 1, L_0x249f330, L_0x24b8610, C4<1>, C4<1>; +L_0x24b86c0 .delay (20000,20000,20000) L_0x24b86c0/d; +L_0x249f000/d .functor AND 1, L_0x249f420, L_0x249f290, C4<1>, C4<1>; +L_0x249f000 .delay (20000,20000,20000) L_0x249f000/d; +L_0x249f0b0/d .functor OR 1, L_0x24b86c0, L_0x249f000, C4<0>, C4<0>; +L_0x249f0b0 .delay (20000,20000,20000) L_0x249f0b0/d; +v0x23bb4b0_0 .net "S", 0 0, L_0x249f290; 1 drivers +v0x23bd8c0_0 .net "in0", 0 0, L_0x249f330; 1 drivers +v0x23bd960_0 .net "in1", 0 0, L_0x249f420; 1 drivers +v0x23bda00_0 .net "nS", 0 0, L_0x24b8610; 1 drivers +v0x23bfdc0_0 .net "out0", 0 0, L_0x24b86c0; 1 drivers +v0x23bfe60_0 .net "out1", 0 0, L_0x249f000; 1 drivers +v0x23bff00_0 .net "outfinal", 0 0, L_0x249f0b0; 1 drivers +S_0x239ad50 .scope generate, "muxbits[1]" "muxbits[1]" 2 290, 2 290, S_0x22690e0; + .timescale -9 -12; +P_0x22934a8 .param/l "i" 2 290, +C4<01>; +L_0x246b7c0/d .functor OR 1, L_0x246bcf0, L_0x246bad0, C4<0>, C4<0>; +L_0x246b7c0 .delay (20000,20000,20000) L_0x246b7c0/d; +v0x23b8f60_0 .net *"_s15", 0 0, L_0x246bcf0; 1 drivers +v0x23b9020_0 .net *"_s16", 0 0, L_0x246bad0; 1 drivers +S_0x23ad630 .scope module, "ZeroMux" "FourInMux" 2 292, 2 24, S_0x239ad50; + .timescale -9 -12; +L_0x2467a80/d .functor NOT 1, L_0x2469d30, C4<0>, C4<0>, C4<0>; +L_0x2467a80 .delay (10000,10000,10000) L_0x2467a80/d; +L_0x24693d0/d .functor NOT 1, L_0x2469e60, C4<0>, C4<0>, C4<0>; +L_0x24693d0 .delay (10000,10000,10000) L_0x24693d0/d; +L_0x24694d0/d .functor NAND 1, L_0x2467a80, L_0x24693d0, L_0x2469f90, C4<1>; +L_0x24694d0 .delay (10000,10000,10000) L_0x24694d0/d; +L_0x2469670/d .functor NAND 1, L_0x2469d30, L_0x24693d0, L_0x246a030, C4<1>; +L_0x2469670 .delay (10000,10000,10000) L_0x2469670/d; +L_0x24697c0/d .functor NAND 1, L_0x2467a80, L_0x2469e60, L_0x246a120, C4<1>; +L_0x24697c0 .delay (10000,10000,10000) L_0x24697c0/d; +L_0x2469910/d .functor NAND 1, L_0x2469d30, L_0x2469e60, L_0x246a2a0, C4<1>; +L_0x2469910 .delay (10000,10000,10000) L_0x2469910/d; +L_0x2469a80/d .functor NAND 1, L_0x24694d0, L_0x2469670, L_0x24697c0, L_0x2469910; +L_0x2469a80 .delay (10000,10000,10000) L_0x2469a80/d; +v0x23afaa0_0 .net "S0", 0 0, L_0x2469d30; 1 drivers +v0x23afb60_0 .net "S1", 0 0, L_0x2469e60; 1 drivers +v0x23afc00_0 .net "in0", 0 0, L_0x2469f90; 1 drivers +v0x23b1fb0_0 .net "in1", 0 0, L_0x246a030; 1 drivers +v0x23b2030_0 .net "in2", 0 0, L_0x246a120; 1 drivers +v0x23b20d0_0 .net "in3", 0 0, L_0x246a2a0; 1 drivers +v0x23b44c0_0 .net "nS0", 0 0, L_0x2467a80; 1 drivers +v0x23b4560_0 .net "nS1", 0 0, L_0x24693d0; 1 drivers +v0x23b4600_0 .net "out", 0 0, L_0x2469a80; 1 drivers +v0x23b69d0_0 .net "out0", 0 0, L_0x24694d0; 1 drivers +v0x23b6a50_0 .net "out1", 0 0, L_0x2469670; 1 drivers +v0x23b6af0_0 .net "out2", 0 0, L_0x24697c0; 1 drivers +v0x23b8ec0_0 .net "out3", 0 0, L_0x2469910; 1 drivers +S_0x23a1cf0 .scope module, "OneMux" "FourInMux" 2 293, 2 24, S_0x239ad50; + .timescale -9 -12; +L_0x246a420/d .functor NOT 1, L_0x246acf0, C4<0>, C4<0>, C4<0>; +L_0x246a420 .delay (10000,10000,10000) L_0x246a420/d; +L_0x246a4c0/d .functor NOT 1, L_0x246ae20, C4<0>, C4<0>, C4<0>; +L_0x246a4c0 .delay (10000,10000,10000) L_0x246a4c0/d; +L_0x246a560/d .functor NAND 1, L_0x246a420, L_0x246a4c0, L_0x246afb0, C4<1>; +L_0x246a560 .delay (10000,10000,10000) L_0x246a560/d; +L_0x246a6a0/d .functor NAND 1, L_0x246acf0, L_0x246a4c0, L_0x246b050, C4<1>; +L_0x246a6a0 .delay (10000,10000,10000) L_0x246a6a0/d; +L_0x246a790/d .functor NAND 1, L_0x246a420, L_0x246ae20, L_0x246b0f0, C4<1>; +L_0x246a790 .delay (10000,10000,10000) L_0x246a790/d; +L_0x246a880/d .functor NAND 1, L_0x246acf0, L_0x246ae20, L_0x246b1e0, C4<1>; +L_0x246a880 .delay (10000,10000,10000) L_0x246a880/d; +L_0x246a9f0/d .functor NAND 1, L_0x246a560, L_0x246a6a0, L_0x246a790, L_0x246a880; +L_0x246a9f0 .delay (10000,10000,10000) L_0x246a9f0/d; +v0x23a4150_0 .net "S0", 0 0, L_0x246acf0; 1 drivers +v0x23a4210_0 .net "S1", 0 0, L_0x246ae20; 1 drivers +v0x23a42b0_0 .net "in0", 0 0, L_0x246afb0; 1 drivers +v0x23a6650_0 .net "in1", 0 0, L_0x246b050; 1 drivers +v0x23a66d0_0 .net "in2", 0 0, L_0x246b0f0; 1 drivers +v0x23a6770_0 .net "in3", 0 0, L_0x246b1e0; 1 drivers +v0x23a8b70_0 .net "nS0", 0 0, L_0x246a420; 1 drivers +v0x23a8c10_0 .net "nS1", 0 0, L_0x246a4c0; 1 drivers +v0x23a8cb0_0 .net "out", 0 0, L_0x246a9f0; 1 drivers +v0x23ab080_0 .net "out0", 0 0, L_0x246a560; 1 drivers +v0x23ab100_0 .net "out1", 0 0, L_0x246a6a0; 1 drivers +v0x23ab1a0_0 .net "out2", 0 0, L_0x246a790; 1 drivers +v0x23ad590_0 .net "out3", 0 0, L_0x246a880; 1 drivers +S_0x239d250 .scope module, "TwoMux" "TwoInMux" 2 294, 2 8, S_0x239ad50; + .timescale -9 -12; +L_0x246af50/d .functor NOT 1, L_0x246b720, C4<0>, C4<0>, C4<0>; +L_0x246af50 .delay (10000,10000,10000) L_0x246af50/d; +L_0x246b360/d .functor AND 1, L_0x246b850, L_0x246af50, C4<1>, C4<1>; +L_0x246b360 .delay (20000,20000,20000) L_0x246b360/d; +L_0x246b450/d .functor AND 1, L_0x246b990, L_0x246b720, C4<1>, C4<1>; +L_0x246b450 .delay (20000,20000,20000) L_0x246b450/d; +L_0x246b540/d .functor OR 1, L_0x246b360, L_0x246b450, C4<0>, C4<0>; +L_0x246b540 .delay (20000,20000,20000) L_0x246b540/d; +v0x239d340_0 .net "S", 0 0, L_0x246b720; 1 drivers +v0x23988e0_0 .net "in0", 0 0, L_0x246b850; 1 drivers +v0x239ae80_0 .net "in1", 0 0, L_0x246b990; 1 drivers +v0x239f750_0 .net "nS", 0 0, L_0x246af50; 1 drivers +v0x239f7d0_0 .net "out0", 0 0, L_0x246b360; 1 drivers +v0x239f870_0 .net "out1", 0 0, L_0x246b450; 1 drivers +v0x23a1c50_0 .net "outfinal", 0 0, L_0x246b540; 1 drivers +S_0x236d7a0 .scope generate, "muxbits[2]" "muxbits[2]" 2 290, 2 290, S_0x22690e0; + .timescale -9 -12; +P_0x22d4e38 .param/l "i" 2 290, +C4<010>; +L_0x246e3f0/d .functor OR 1, L_0x246e720, L_0x246e850, C4<0>, C4<0>; +L_0x246e3f0 .delay (20000,20000,20000) L_0x246e3f0/d; +v0x23987a0_0 .net *"_s15", 0 0, L_0x246e720; 1 drivers +v0x2398840_0 .net *"_s16", 0 0, L_0x246e850; 1 drivers +S_0x2381dc0 .scope module, "ZeroMux" "FourInMux" 2 292, 2 24, S_0x236d7a0; + .timescale -9 -12; +L_0x246bf30/d .functor NOT 1, L_0x246bde0, C4<0>, C4<0>, C4<0>; +L_0x246bf30 .delay (10000,10000,10000) L_0x246bf30/d; +L_0x246c020/d .functor NOT 1, L_0x246c920, C4<0>, C4<0>, C4<0>; +L_0x246c020 .delay (10000,10000,10000) L_0x246c020/d; +L_0x246c0c0/d .functor NAND 1, L_0x246bf30, L_0x246c020, L_0x246c7d0, C4<1>; +L_0x246c0c0 .delay (10000,10000,10000) L_0x246c0c0/d; +L_0x246c200/d .functor NAND 1, L_0x246bde0, L_0x246c020, L_0x246cb20, C4<1>; +L_0x246c200 .delay (10000,10000,10000) L_0x246c200/d; +L_0x246c2f0/d .functor NAND 1, L_0x246bf30, L_0x246c920, L_0x246ca50, C4<1>; +L_0x246c2f0 .delay (10000,10000,10000) L_0x246c2f0/d; +L_0x246c3e0/d .functor NAND 1, L_0x246bde0, L_0x246c920, L_0x246ccf0, C4<1>; +L_0x246c3e0 .delay (10000,10000,10000) L_0x246c3e0/d; +L_0x246c520/d .functor NAND 1, L_0x246c0c0, L_0x246c200, L_0x246c2f0, L_0x246c3e0; +L_0x246c520 .delay (10000,10000,10000) L_0x246c520/d; +v0x2381eb0_0 .net "S0", 0 0, L_0x246bde0; 1 drivers +v0x23832c0_0 .net "S1", 0 0, L_0x246c920; 1 drivers +v0x2383360_0 .net "in0", 0 0, L_0x246c7d0; 1 drivers +v0x2383400_0 .net "in1", 0 0, L_0x246cb20; 1 drivers +v0x23848c0_0 .net "in2", 0 0, L_0x246ca50; 1 drivers +v0x2384960_0 .net "in3", 0 0, L_0x246ccf0; 1 drivers +v0x2384a00_0 .net "nS0", 0 0, L_0x246bf30; 1 drivers +v0x2385e40_0 .net "nS1", 0 0, L_0x246c020; 1 drivers +v0x2385ec0_0 .net "out", 0 0, L_0x246c520; 1 drivers +v0x2385f60_0 .net "out0", 0 0, L_0x246c0c0; 1 drivers +v0x23e0440_0 .net "out1", 0 0, L_0x246c200; 1 drivers +v0x23e04e0_0 .net "out2", 0 0, L_0x246c2f0; 1 drivers +v0x23e0580_0 .net "out3", 0 0, L_0x246c3e0; 1 drivers +S_0x237b0e0 .scope module, "OneMux" "FourInMux" 2 293, 2 24, S_0x236d7a0; + .timescale -9 -12; +L_0x246cbc0/d .functor NOT 1, L_0x246d6c0, C4<0>, C4<0>, C4<0>; +L_0x246cbc0 .delay (10000,10000,10000) L_0x246cbc0/d; +L_0x246cf20/d .functor NOT 1, L_0x246cde0, C4<0>, C4<0>, C4<0>; +L_0x246cf20 .delay (10000,10000,10000) L_0x246cf20/d; +L_0x246cf80/d .functor NAND 1, L_0x246cbc0, L_0x246cf20, L_0x246d980, C4<1>; +L_0x246cf80 .delay (10000,10000,10000) L_0x246cf80/d; +L_0x246d0c0/d .functor NAND 1, L_0x246d6c0, L_0x246cf20, L_0x246d7f0, C4<1>; +L_0x246d0c0 .delay (10000,10000,10000) L_0x246d0c0/d; +L_0x246d1b0/d .functor NAND 1, L_0x246cbc0, L_0x246cde0, L_0x246dbc0, C4<1>; +L_0x246d1b0 .delay (10000,10000,10000) L_0x246d1b0/d; +L_0x246d2a0/d .functor NAND 1, L_0x246d6c0, L_0x246cde0, L_0x246dab0, C4<1>; +L_0x246d2a0 .delay (10000,10000,10000) L_0x246d2a0/d; +L_0x246d410/d .functor NAND 1, L_0x246cf80, L_0x246d0c0, L_0x246d1b0, L_0x246d2a0; +L_0x246d410 .delay (10000,10000,10000) L_0x246d410/d; +v0x237c640_0 .net "S0", 0 0, L_0x246d6c0; 1 drivers +v0x237c700_0 .net "S1", 0 0, L_0x246cde0; 1 drivers +v0x237c7a0_0 .net "in0", 0 0, L_0x246d980; 1 drivers +v0x237dbc0_0 .net "in1", 0 0, L_0x246d7f0; 1 drivers +v0x237dc40_0 .net "in2", 0 0, L_0x246dbc0; 1 drivers +v0x237dce0_0 .net "in3", 0 0, L_0x246dab0; 1 drivers +v0x237f1c0_0 .net "nS0", 0 0, L_0x246cbc0; 1 drivers +v0x237f260_0 .net "nS1", 0 0, L_0x246cf20; 1 drivers +v0x237f300_0 .net "out", 0 0, L_0x246d410; 1 drivers +v0x2380740_0 .net "out0", 0 0, L_0x246cf80; 1 drivers +v0x23807e0_0 .net "out1", 0 0, L_0x246d0c0; 1 drivers +v0x2380880_0 .net "out2", 0 0, L_0x246d1b0; 1 drivers +v0x2381d40_0 .net "out3", 0 0, L_0x246d2a0; 1 drivers +S_0x23784c0 .scope module, "TwoMux" "TwoInMux" 2 294, 2 8, S_0x236d7a0; + .timescale -9 -12; +L_0x246d890/d .functor NOT 1, L_0x246dc60, C4<0>, C4<0>, C4<0>; +L_0x246d890 .delay (10000,10000,10000) L_0x246d890/d; +L_0x246ddd0/d .functor AND 1, L_0x246e2c0, L_0x246d890, C4<1>, C4<1>; +L_0x246ddd0 .delay (20000,20000,20000) L_0x246ddd0/d; +L_0x246dec0/d .functor AND 1, L_0x246e190, L_0x246dc60, C4<1>, C4<1>; +L_0x246dec0 .delay (20000,20000,20000) L_0x246dec0/d; +L_0x246dfb0/d .functor OR 1, L_0x246ddd0, L_0x246dec0, C4<0>, C4<0>; +L_0x246dfb0 .delay (20000,20000,20000) L_0x246dfb0/d; +v0x23785b0_0 .net "S", 0 0, L_0x246dc60; 1 drivers +v0x236c2b0_0 .net "in0", 0 0, L_0x246e2c0; 1 drivers +v0x236d8d0_0 .net "in1", 0 0, L_0x246e190; 1 drivers +v0x2379ac0_0 .net "nS", 0 0, L_0x246d890; 1 drivers +v0x2379b40_0 .net "out0", 0 0, L_0x246ddd0; 1 drivers +v0x2379be0_0 .net "out1", 0 0, L_0x246dec0; 1 drivers +v0x237b040_0 .net "outfinal", 0 0, L_0x246dfb0; 1 drivers +S_0x22c6fe0 .scope generate, "muxbits[3]" "muxbits[3]" 2 290, 2 290, S_0x22690e0; + .timescale -9 -12; +P_0x226d278 .param/l "i" 2 290, +C4<011>; +L_0x2470d20/d .functor OR 1, L_0x24710a0, L_0x2470eb0, C4<0>, C4<0>; +L_0x2470d20 .delay (20000,20000,20000) L_0x2470d20/d; +v0x236c150_0 .net *"_s15", 0 0, L_0x24710a0; 1 drivers +v0x236c210_0 .net *"_s16", 0 0, L_0x2470eb0; 1 drivers +S_0x2270ca0 .scope module, "ZeroMux" "FourInMux" 2 292, 2 24, S_0x22c6fe0; + .timescale -9 -12; +L_0x246e5d0/d .functor NOT 1, L_0x246f170, C4<0>, C4<0>, C4<0>; +L_0x246e5d0 .delay (10000,10000,10000) L_0x246e5d0/d; +L_0x246e670/d .functor NOT 1, L_0x246e980, C4<0>, C4<0>, C4<0>; +L_0x246e670 .delay (10000,10000,10000) L_0x246e670/d; +L_0x246eae0/d .functor NAND 1, L_0x246e5d0, L_0x246e670, L_0x246f410, C4<1>; +L_0x246eae0 .delay (10000,10000,10000) L_0x246eae0/d; +L_0x246ebd0/d .functor NAND 1, L_0x246f170, L_0x246e670, L_0x246f2a0, C4<1>; +L_0x246ebd0 .delay (10000,10000,10000) L_0x246ebd0/d; +L_0x246ecc0/d .functor NAND 1, L_0x246e5d0, L_0x246e980, L_0x246f340, C4<1>; +L_0x246ecc0 .delay (10000,10000,10000) L_0x246ecc0/d; +L_0x246edb0/d .functor NAND 1, L_0x246f170, L_0x246e980, L_0x246f5c0, C4<1>; +L_0x246edb0 .delay (10000,10000,10000) L_0x246edb0/d; +L_0x246eec0/d .functor NAND 1, L_0x246eae0, L_0x246ebd0, L_0x246ecc0, L_0x246edb0; +L_0x246eec0 .delay (10000,10000,10000) L_0x246eec0/d; +v0x2270d90_0 .net "S0", 0 0, L_0x246f170; 1 drivers +v0x22a4d80_0 .net "S1", 0 0, L_0x246e980; 1 drivers +v0x22a4e20_0 .net "in0", 0 0, L_0x246f410; 1 drivers +v0x22e6db0_0 .net "in1", 0 0, L_0x246f2a0; 1 drivers +v0x22e6e30_0 .net "in2", 0 0, L_0x246f340; 1 drivers +v0x2210090_0 .net "in3", 0 0, L_0x246f5c0; 1 drivers +v0x2210130_0 .net "nS0", 0 0, L_0x246e5d0; 1 drivers +v0x22101d0_0 .net "nS1", 0 0, L_0x246e670; 1 drivers +v0x21ecd40_0 .net "out", 0 0, L_0x246eec0; 1 drivers +v0x21ecdc0_0 .net "out0", 0 0, L_0x246eae0; 1 drivers +v0x21ece60_0 .net "out1", 0 0, L_0x246ebd0; 1 drivers +v0x2376fb0_0 .net "out2", 0 0, L_0x246ecc0; 1 drivers +v0x23770c0_0 .net "out3", 0 0, L_0x246edb0; 1 drivers +S_0x22a6850 .scope module, "OneMux" "FourInMux" 2 293, 2 24, S_0x22c6fe0; + .timescale -9 -12; +L_0x246f6b0/d .functor NOT 1, L_0x246f850, C4<0>, C4<0>, C4<0>; +L_0x246f6b0 .delay (10000,10000,10000) L_0x246f6b0/d; +L_0x246f9e0/d .functor NOT 1, L_0x24702c0, C4<0>, C4<0>, C4<0>; +L_0x246f9e0 .delay (10000,10000,10000) L_0x246f9e0/d; +L_0x246fa40/d .functor NAND 1, L_0x246f6b0, L_0x246f9e0, L_0x2470120, C4<1>; +L_0x246fa40 .delay (10000,10000,10000) L_0x246fa40/d; +L_0x246fb80/d .functor NAND 1, L_0x246f850, L_0x246f9e0, L_0x24701c0, C4<1>; +L_0x246fb80 .delay (10000,10000,10000) L_0x246fb80/d; +L_0x246fc70/d .functor NAND 1, L_0x246f6b0, L_0x24702c0, L_0x24705b0, C4<1>; +L_0x246fc70 .delay (10000,10000,10000) L_0x246fc70/d; +L_0x246fd60/d .functor NAND 1, L_0x246f850, L_0x24702c0, L_0x2470650, C4<1>; +L_0x246fd60 .delay (10000,10000,10000) L_0x246fd60/d; +L_0x246fe70/d .functor NAND 1, L_0x246fa40, L_0x246fb80, L_0x246fc70, L_0x246fd60; +L_0x246fe70 .delay (10000,10000,10000) L_0x246fe70/d; +v0x22a6940_0 .net "S0", 0 0, L_0x246f850; 1 drivers +v0x2293360_0 .net "S1", 0 0, L_0x24702c0; 1 drivers +v0x2293400_0 .net "in0", 0 0, L_0x2470120; 1 drivers +v0x228f7f0_0 .net "in1", 0 0, L_0x24701c0; 1 drivers +v0x228f870_0 .net "in2", 0 0, L_0x24705b0; 1 drivers +v0x228d800_0 .net "in3", 0 0, L_0x2470650; 1 drivers +v0x228d8a0_0 .net "nS0", 0 0, L_0x246f6b0; 1 drivers +v0x2289c90_0 .net "nS1", 0 0, L_0x246f9e0; 1 drivers +v0x2289d30_0 .net "out", 0 0, L_0x246fe70; 1 drivers +v0x2287ca0_0 .net "out0", 0 0, L_0x246fa40; 1 drivers +v0x2287d40_0 .net "out1", 0 0, L_0x246fb80; 1 drivers +v0x2272c90_0 .net "out2", 0 0, L_0x246fc70; 1 drivers +v0x2272d30_0 .net "out3", 0 0, L_0x246fd60; 1 drivers +S_0x22b1f10 .scope module, "TwoMux" "TwoInMux" 2 294, 2 8, S_0x22c6fe0; + .timescale -9 -12; +L_0x24703f0/d .functor NOT 1, L_0x2470be0, C4<0>, C4<0>, C4<0>; +L_0x24703f0 .delay (10000,10000,10000) L_0x24703f0/d; +L_0x24704e0/d .functor AND 1, L_0x24706f0, L_0x24703f0, C4<1>, C4<1>; +L_0x24704e0 .delay (20000,20000,20000) L_0x24704e0/d; +L_0x2470910/d .functor AND 1, L_0x24707e0, L_0x2470be0, C4<1>, C4<1>; +L_0x2470910 .delay (20000,20000,20000) L_0x2470910/d; +L_0x2470a00/d .functor OR 1, L_0x24704e0, L_0x2470910, C4<0>, C4<0>; +L_0x2470a00 .delay (20000,20000,20000) L_0x2470a00/d; +v0x22b2000_0 .net "S", 0 0, L_0x2470be0; 1 drivers +v0x22aff20_0 .net "in0", 0 0, L_0x24706f0; 1 drivers +v0x22affa0_0 .net "in1", 0 0, L_0x24707e0; 1 drivers +v0x22ac3b0_0 .net "nS", 0 0, L_0x24703f0; 1 drivers +v0x22ac430_0 .net "out0", 0 0, L_0x24704e0; 1 drivers +v0x22aa3c0_0 .net "out1", 0 0, L_0x2470910; 1 drivers +v0x22aa460_0 .net "outfinal", 0 0, L_0x2470a00; 1 drivers +S_0x2308aa0 .scope generate, "muxbits[4]" "muxbits[4]" 2 290, 2 290, S_0x22690e0; + .timescale -9 -12; +P_0x22f0f38 .param/l "i" 2 290, +C4<0100>; +L_0x24736d0/d .functor OR 1, L_0x2473b50, L_0x2473d00, C4<0>, C4<0>; +L_0x24736d0 .delay (20000,20000,20000) L_0x24736d0/d; +v0x22c90b0_0 .net *"_s15", 0 0, L_0x2473b50; 1 drivers +v0x22c9170_0 .net *"_s16", 0 0, L_0x2473d00; 1 drivers +S_0x22ea580 .scope module, "ZeroMux" "FourInMux" 2 292, 2 24, S_0x2308aa0; + .timescale -9 -12; +L_0x2470fa0/d .functor NOT 1, L_0x2471140, C4<0>, C4<0>, C4<0>; +L_0x2470fa0 .delay (10000,10000,10000) L_0x2470fa0/d; +L_0x2471340/d .functor NOT 1, L_0x2471270, C4<0>, C4<0>, C4<0>; +L_0x2471340 .delay (10000,10000,10000) L_0x2471340/d; +L_0x24713a0/d .functor NAND 1, L_0x2470fa0, L_0x2471340, L_0x2471b10, C4<1>; +L_0x24713a0 .delay (10000,10000,10000) L_0x24713a0/d; +L_0x24714e0/d .functor NAND 1, L_0x2471140, L_0x2471340, L_0x2471bb0, C4<1>; +L_0x24714e0 .delay (10000,10000,10000) L_0x24714e0/d; +L_0x24715d0/d .functor NAND 1, L_0x2470fa0, L_0x2471270, L_0x2471c50, C4<1>; +L_0x24715d0 .delay (10000,10000,10000) L_0x24715d0/d; +L_0x24716f0/d .functor NAND 1, L_0x2471140, L_0x2471270, L_0x2472030, C4<1>; +L_0x24716f0 .delay (10000,10000,10000) L_0x24716f0/d; +L_0x2471860/d .functor NAND 1, L_0x24713a0, L_0x24714e0, L_0x24715d0, L_0x24716f0; +L_0x2471860 .delay (10000,10000,10000) L_0x2471860/d; +v0x22ea670_0 .net "S0", 0 0, L_0x2471140; 1 drivers +v0x22ec6d0_0 .net "S1", 0 0, L_0x2471270; 1 drivers +v0x22675d0_0 .net "in0", 0 0, L_0x2471b10; 1 drivers +v0x2267670_0 .net "in1", 0 0, L_0x2471bb0; 1 drivers +v0x22d4cf0_0 .net "in2", 0 0, L_0x2471c50; 1 drivers +v0x22d4d90_0 .net "in3", 0 0, L_0x2472030; 1 drivers +v0x22d2c40_0 .net "nS0", 0 0, L_0x2470fa0; 1 drivers +v0x22d2ce0_0 .net "nS1", 0 0, L_0x2471340; 1 drivers +v0x22ceed0_0 .net "out", 0 0, L_0x2471860; 1 drivers +v0x22cef70_0 .net "out0", 0 0, L_0x24713a0; 1 drivers +v0x22cce20_0 .net "out1", 0 0, L_0x24714e0; 1 drivers +v0x22ccec0_0 .net "out2", 0 0, L_0x24715d0; 1 drivers +v0x2265670_0 .net "out3", 0 0, L_0x24716f0; 1 drivers +S_0x2309d90 .scope module, "OneMux" "FourInMux" 2 293, 2 24, S_0x2308aa0; + .timescale -9 -12; +L_0x2471db0/d .functor NOT 1, L_0x24729d0, C4<0>, C4<0>, C4<0>; +L_0x2471db0 .delay (10000,10000,10000) L_0x2471db0/d; +L_0x2471ea0/d .functor NOT 1, L_0x2472120, C4<0>, C4<0>, C4<0>; +L_0x2471ea0 .delay (10000,10000,10000) L_0x2471ea0/d; +L_0x2471f40/d .functor NAND 1, L_0x2471db0, L_0x2471ea0, L_0x2472250, C4<1>; +L_0x2471f40 .delay (10000,10000,10000) L_0x2471f40/d; +L_0x2472400/d .functor NAND 1, L_0x24729d0, L_0x2471ea0, L_0x2472b00, C4<1>; +L_0x2472400 .delay (10000,10000,10000) L_0x2472400/d; +L_0x24724f0/d .functor NAND 1, L_0x2471db0, L_0x2472120, L_0x2472ba0, C4<1>; +L_0x24724f0 .delay (10000,10000,10000) L_0x24724f0/d; +L_0x24725e0/d .functor NAND 1, L_0x24729d0, L_0x2472120, L_0x2472c90, C4<1>; +L_0x24725e0 .delay (10000,10000,10000) L_0x24725e0/d; +L_0x2472720/d .functor NAND 1, L_0x2471f40, L_0x2472400, L_0x24724f0, L_0x24725e0; +L_0x2472720 .delay (10000,10000,10000) L_0x2472720/d; +v0x2309e80_0 .net "S0", 0 0, L_0x24729d0; 1 drivers +v0x226d1d0_0 .net "S1", 0 0, L_0x2472120; 1 drivers +v0x2307cc0_0 .net "in0", 0 0, L_0x2472250; 1 drivers +v0x2307d60_0 .net "in1", 0 0, L_0x2472b00; 1 drivers +v0x226b140_0 .net "in2", 0 0, L_0x2472ba0; 1 drivers +v0x226b1e0_0 .net "in3", 0 0, L_0x2472c90; 1 drivers +v0x22f61c0_0 .net "nS0", 0 0, L_0x2471db0; 1 drivers +v0x22f6260_0 .net "nS1", 0 0, L_0x2471ea0; 1 drivers +v0x22f2450_0 .net "out", 0 0, L_0x2472720; 1 drivers +v0x22f24f0_0 .net "out0", 0 0, L_0x2471f40; 1 drivers +v0x22f03a0_0 .net "out1", 0 0, L_0x2472400; 1 drivers +v0x22f0440_0 .net "out2", 0 0, L_0x24724f0; 1 drivers +v0x22ec630_0 .net "out3", 0 0, L_0x24725e0; 1 drivers +S_0x23087f0 .scope module, "TwoMux" "TwoInMux" 2 294, 2 8, S_0x2308aa0; + .timescale -9 -12; +L_0x246da20/d .functor NOT 1, L_0x2472e60, C4<0>, C4<0>, C4<0>; +L_0x246da20 .delay (10000,10000,10000) L_0x246da20/d; +L_0x2473160/d .functor AND 1, L_0x2472f00, L_0x246da20, C4<1>, C4<1>; +L_0x2473160 .delay (20000,20000,20000) L_0x2473160/d; +L_0x2473250/d .functor AND 1, L_0x2472ff0, L_0x2472e60, C4<1>, C4<1>; +L_0x2473250 .delay (20000,20000,20000) L_0x2473250/d; +L_0x2473340/d .functor OR 1, L_0x2473160, L_0x2473250, C4<0>, C4<0>; +L_0x2473340 .delay (20000,20000,20000) L_0x2473340/d; +v0x230a410_0 .net "S", 0 0, L_0x2472e60; 1 drivers +v0x230bdb0_0 .net "in0", 0 0, L_0x2472f00; 1 drivers +v0x230be50_0 .net "in1", 0 0, L_0x2472ff0; 1 drivers +v0x2308540_0 .net "nS", 0 0, L_0x246da20; 1 drivers +v0x23085c0_0 .net "out0", 0 0, L_0x2473160; 1 drivers +v0x23082a0_0 .net "out1", 0 0, L_0x2473250; 1 drivers +v0x226d130_0 .net "outfinal", 0 0, L_0x2473340; 1 drivers +S_0x22eb090 .scope generate, "muxbits[5]" "muxbits[5]" 2 290, 2 290, S_0x22690e0; + .timescale -9 -12; +P_0x22d9088 .param/l "i" 2 290, +C4<0101>; +L_0x2475e70/d .functor OR 1, L_0x2475fb0, L_0x2476050, C4<0>, C4<0>; +L_0x2475e70 .delay (20000,20000,20000) L_0x2475e70/d; +v0x230a6d0_0 .net *"_s15", 0 0, L_0x2475fb0; 1 drivers +v0x230a390_0 .net *"_s16", 0 0, L_0x2476050; 1 drivers +S_0x22f6780 .scope module, "ZeroMux" "FourInMux" 2 292, 2 24, S_0x22eb090; + .timescale -9 -12; +L_0x246e8f0/d .functor NOT 1, L_0x24745b0, C4<0>, C4<0>, C4<0>; +L_0x246e8f0 .delay (10000,10000,10000) L_0x246e8f0/d; +L_0x2473900/d .functor NOT 1, L_0x2473eb0, C4<0>, C4<0>, C4<0>; +L_0x2473900 .delay (10000,10000,10000) L_0x2473900/d; +L_0x2473960/d .functor NAND 1, L_0x246e8f0, L_0x2473900, L_0x2473fe0, C4<1>; +L_0x2473960 .delay (10000,10000,10000) L_0x2473960/d; +L_0x2473a60/d .functor NAND 1, L_0x24745b0, L_0x2473900, L_0x2474080, C4<1>; +L_0x2473a60 .delay (10000,10000,10000) L_0x2473a60/d; +L_0x2474160/d .functor NAND 1, L_0x246e8f0, L_0x2473eb0, L_0x24749b0, C4<1>; +L_0x2474160 .delay (10000,10000,10000) L_0x2474160/d; +L_0x2474250/d .functor NAND 1, L_0x24745b0, L_0x2473eb0, L_0x24746e0, C4<1>; +L_0x2474250 .delay (10000,10000,10000) L_0x2474250/d; +L_0x2474330/d .functor NAND 1, L_0x2473960, L_0x2473a60, L_0x2474160, L_0x2474250; +L_0x2474330 .delay (10000,10000,10000) L_0x2474330/d; +v0x22f88b0_0 .net "S0", 0 0, L_0x24745b0; 1 drivers +v0x22fe670_0 .net "S1", 0 0, L_0x2473eb0; 1 drivers +v0x22fe710_0 .net "in0", 0 0, L_0x2473fe0; 1 drivers +v0x22fc580_0 .net "in1", 0 0, L_0x2474080; 1 drivers +v0x22fc620_0 .net "in2", 0 0, L_0x24749b0; 1 drivers +v0x23044d0_0 .net "in3", 0 0, L_0x24746e0; 1 drivers +v0x2304570_0 .net "nS0", 0 0, L_0x246e8f0; 1 drivers +v0x23023e0_0 .net "nS1", 0 0, L_0x2473900; 1 drivers +v0x2302480_0 .net "out", 0 0, L_0x2474330; 1 drivers +v0x230ab90_0 .net "out0", 0 0, L_0x2473960; 1 drivers +v0x230ac30_0 .net "out1", 0 0, L_0x2473a60; 1 drivers +v0x230a8e0_0 .net "out2", 0 0, L_0x2474160; 1 drivers +v0x230a630_0 .net "out3", 0 0, L_0x2474250; 1 drivers +S_0x22f2cf0 .scope module, "OneMux" "FourInMux" 2 293, 2 24, S_0x22eb090; + .timescale -9 -12; +L_0x246f4b0/d .functor NOT 1, L_0x2474aa0, C4<0>, C4<0>, C4<0>; +L_0x246f4b0 .delay (10000,10000,10000) L_0x246f4b0/d; +L_0x246f560/d .functor NOT 1, L_0x2474bd0, C4<0>, C4<0>, C4<0>; +L_0x246f560 .delay (10000,10000,10000) L_0x246f560/d; +L_0x2474810/d .functor NAND 1, L_0x246f4b0, L_0x246f560, L_0x2475770, C4<1>; +L_0x2474810 .delay (10000,10000,10000) L_0x2474810/d; +L_0x2474950/d .functor NAND 1, L_0x2474aa0, L_0x246f560, L_0x2475810, C4<1>; +L_0x2474950 .delay (10000,10000,10000) L_0x2474950/d; +L_0x2475020/d .functor NAND 1, L_0x246f4b0, L_0x2474bd0, L_0x2475470, C4<1>; +L_0x2475020 .delay (10000,10000,10000) L_0x2475020/d; +L_0x2475110/d .functor NAND 1, L_0x2474aa0, L_0x2474bd0, L_0x2475560, C4<1>; +L_0x2475110 .delay (10000,10000,10000) L_0x2475110/d; +L_0x24751f0/d .functor NAND 1, L_0x2474810, L_0x2474950, L_0x2475020, L_0x2475110; +L_0x24751f0 .delay (10000,10000,10000) L_0x24751f0/d; +v0x22f3040_0 .net "S0", 0 0, L_0x2474aa0; 1 drivers +v0x22f2a50_0 .net "S1", 0 0, L_0x2474bd0; 1 drivers +v0x22f2af0_0 .net "in0", 0 0, L_0x2475770; 1 drivers +v0x22f1160_0 .net "in1", 0 0, L_0x2475810; 1 drivers +v0x22f1200_0 .net "in2", 0 0, L_0x2475470; 1 drivers +v0x22f0eb0_0 .net "in3", 0 0, L_0x2475560; 1 drivers +v0x22f4470_0 .net "nS0", 0 0, L_0x246f4b0; 1 drivers +v0x22f4510_0 .net "nS1", 0 0, L_0x246f560; 1 drivers +v0x22f0c00_0 .net "out", 0 0, L_0x24751f0; 1 drivers +v0x22f0ca0_0 .net "out0", 0 0, L_0x2474810; 1 drivers +v0x22f0960_0 .net "out1", 0 0, L_0x2474950; 1 drivers +v0x22f0a00_0 .net "out2", 0 0, L_0x2475020; 1 drivers +v0x22f8810_0 .net "out3", 0 0, L_0x2475110; 1 drivers +S_0x22ee650 .scope module, "TwoMux" "TwoInMux" 2 294, 2 8, S_0x22eb090; + .timescale -9 -12; +L_0x2474d00/d .functor NOT 1, L_0x2475b20, C4<0>, C4<0>, C4<0>; +L_0x2474d00 .delay (10000,10000,10000) L_0x2474d00/d; +L_0x246f7d0/d .functor AND 1, L_0x2476100, L_0x2474d00, C4<1>, C4<1>; +L_0x246f7d0 .delay (20000,20000,20000) L_0x246f7d0/d; +L_0x24756e0/d .functor AND 1, L_0x24761f0, L_0x2475b20, C4<1>, C4<1>; +L_0x24756e0 .delay (20000,20000,20000) L_0x24756e0/d; +L_0x2475940/d .functor OR 1, L_0x246f7d0, L_0x24756e0, C4<0>, C4<0>; +L_0x2475940 .delay (20000,20000,20000) L_0x2475940/d; +v0x22eade0_0 .net "S", 0 0, L_0x2475b20; 1 drivers +v0x22eae80_0 .net "in0", 0 0, L_0x2476100; 1 drivers +v0x22eab40_0 .net "in1", 0 0, L_0x24761f0; 1 drivers +v0x22eabe0_0 .net "nS", 0 0, L_0x2474d00; 1 drivers +v0x22f3250_0 .net "out0", 0 0, L_0x246f7d0; 1 drivers +v0x22f32f0_0 .net "out1", 0 0, L_0x24756e0; 1 drivers +v0x22f2fa0_0 .net "outfinal", 0 0, L_0x2475940; 1 drivers +S_0x22cd3e0 .scope generate, "muxbits[6]" "muxbits[6]" 2 290, 2 290, S_0x22690e0; + .timescale -9 -12; +P_0x22c9738 .param/l "i" 2 290, +C4<0110>; +L_0x243e4e0/d .functor OR 1, L_0x243e5e0, L_0x243e680, C4<0>, C4<0>; +L_0x243e4e0 .delay (20000,20000,20000) L_0x243e4e0/d; +v0x22eb340_0 .net *"_s15", 0 0, L_0x243e5e0; 1 drivers +v0x22eb400_0 .net *"_s16", 0 0, L_0x243e680; 1 drivers +S_0x22e70b0 .scope module, "ZeroMux" "FourInMux" 2 292, 2 24, S_0x22cd3e0; + .timescale -9 -12; +L_0x2476680/d .functor NOT 1, L_0x24762e0, C4<0>, C4<0>, C4<0>; +L_0x2476680 .delay (10000,10000,10000) L_0x2476680/d; +L_0x2476770/d .functor NOT 1, L_0x2476410, C4<0>, C4<0>, C4<0>; +L_0x2476770 .delay (10000,10000,10000) L_0x2476770/d; +L_0x2476810/d .functor NAND 1, L_0x2476680, L_0x2476770, L_0x2476540, C4<1>; +L_0x2476810 .delay (10000,10000,10000) L_0x2476810/d; +L_0x2476950/d .functor NAND 1, L_0x24762e0, L_0x2476770, L_0x2477200, C4<1>; +L_0x2476950 .delay (10000,10000,10000) L_0x2476950/d; +L_0x2476a40/d .functor NAND 1, L_0x2476680, L_0x2476410, L_0x2476e90, C4<1>; +L_0x2476a40 .delay (10000,10000,10000) L_0x2476a40/d; +L_0x2476b30/d .functor NAND 1, L_0x24762e0, L_0x2476410, L_0x2476f30, C4<1>; +L_0x2476b30 .delay (10000,10000,10000) L_0x2476b30/d; +L_0x2476c10/d .functor NAND 1, L_0x2476810, L_0x2476950, L_0x2476a40, L_0x2476b30; +L_0x2476c10 .delay (10000,10000,10000) L_0x2476c10/d; +v0x22e7400_0 .net "S0", 0 0, L_0x24762e0; 1 drivers +v0x22e8830_0 .net "S1", 0 0, L_0x2476410; 1 drivers +v0x22e88d0_0 .net "in0", 0 0, L_0x2476540; 1 drivers +v0x22e4cc0_0 .net "in1", 0 0, L_0x2477200; 1 drivers +v0x22e4d60_0 .net "in2", 0 0, L_0x2476e90; 1 drivers +v0x22ed430_0 .net "in3", 0 0, L_0x2476f30; 1 drivers +v0x22ed4d0_0 .net "nS0", 0 0, L_0x2476680; 1 drivers +v0x22ed180_0 .net "nS1", 0 0, L_0x2476770; 1 drivers +v0x22ed220_0 .net "out", 0 0, L_0x2476c10; 1 drivers +v0x22eced0_0 .net "out0", 0 0, L_0x2476810; 1 drivers +v0x22ecf70_0 .net "out1", 0 0, L_0x2476950; 1 drivers +v0x22ecc30_0 .net "out2", 0 0, L_0x2476a40; 1 drivers +v0x22eccd0_0 .net "out3", 0 0, L_0x2476b30; 1 drivers +S_0x22d34a0 .scope module, "OneMux" "FourInMux" 2 293, 2 24, S_0x22cd3e0; + .timescale -9 -12; +L_0x2477020/d .functor NOT 1, L_0x2477c60, C4<0>, C4<0>, C4<0>; +L_0x2477020 .delay (10000,10000,10000) L_0x2477020/d; +L_0x2477110/d .functor NOT 1, L_0x24772a0, C4<0>, C4<0>, C4<0>; +L_0x2477110 .delay (10000,10000,10000) L_0x2477110/d; +L_0x2477630/d .functor NAND 1, L_0x2477020, L_0x2477110, L_0x24773d0, C4<1>; +L_0x2477630 .delay (10000,10000,10000) L_0x2477630/d; +L_0x2477720/d .functor NAND 1, L_0x2477c60, L_0x2477110, L_0x2477470, C4<1>; +L_0x2477720 .delay (10000,10000,10000) L_0x2477720/d; +L_0x2477810/d .functor NAND 1, L_0x2477020, L_0x24772a0, L_0x2477510, C4<1>; +L_0x2477810 .delay (10000,10000,10000) L_0x2477810/d; +L_0x2477900/d .functor NAND 1, L_0x2477c60, L_0x24772a0, L_0x2477d90, C4<1>; +L_0x2477900 .delay (10000,10000,10000) L_0x2477900/d; +L_0x24779e0/d .functor NAND 1, L_0x2477630, L_0x2477720, L_0x2477810, L_0x2477900; +L_0x24779e0 .delay (10000,10000,10000) L_0x24779e0/d; +v0x22d37f0_0 .net "S0", 0 0, L_0x2477c60; 1 drivers +v0x22d3200_0 .net "S1", 0 0, L_0x24772a0; 1 drivers +v0x22d32a0_0 .net "in0", 0 0, L_0x24773d0; 1 drivers +v0x22db0f0_0 .net "in1", 0 0, L_0x2477470; 1 drivers +v0x22db190_0 .net "in2", 0 0, L_0x2477510; 1 drivers +v0x22d9000_0 .net "in3", 0 0, L_0x2477d90; 1 drivers +v0x22e0f50_0 .net "nS0", 0 0, L_0x2477020; 1 drivers +v0x22e0ff0_0 .net "nS1", 0 0, L_0x2477110; 1 drivers +v0x22dee60_0 .net "out", 0 0, L_0x24779e0; 1 drivers +v0x22def00_0 .net "out0", 0 0, L_0x2477630; 1 drivers +v0x22e7610_0 .net "out1", 0 0, L_0x2477720; 1 drivers +v0x22e76b0_0 .net "out2", 0 0, L_0x2477810; 1 drivers +v0x22e7360_0 .net "out3", 0 0, L_0x2477900; 1 drivers +S_0x22d5840 .scope module, "TwoMux" "TwoInMux" 2 294, 2 8, S_0x22cd3e0; + .timescale -9 -12; +L_0x2477e80/d .functor NOT 1, L_0x243e990, C4<0>, C4<0>, C4<0>; +L_0x2477e80 .delay (10000,10000,10000) L_0x2477e80/d; +L_0x2477f30/d .functor AND 1, L_0x243ea30, L_0x2477e80, C4<1>, C4<1>; +L_0x2477f30 .delay (20000,20000,20000) L_0x2477f30/d; +L_0x2477fe0/d .functor AND 1, L_0x243eb20, L_0x243e990, C4<1>, C4<1>; +L_0x2477fe0 .delay (20000,20000,20000) L_0x2477fe0/d; +L_0x24780d0/d .functor OR 1, L_0x2477f30, L_0x2477fe0, C4<0>, C4<0>; +L_0x24780d0 .delay (20000,20000,20000) L_0x24780d0/d; +v0x22cd700_0 .net "S", 0 0, L_0x243e990; 1 drivers +v0x22d5590_0 .net "in0", 0 0, L_0x243ea30; 1 drivers +v0x22d5630_0 .net "in1", 0 0, L_0x243eb20; 1 drivers +v0x22d52f0_0 .net "nS", 0 0, L_0x2477e80; 1 drivers +v0x22d5370_0 .net "out0", 0 0, L_0x2477f30; 1 drivers +v0x22d3a00_0 .net "out1", 0 0, L_0x2477fe0; 1 drivers +v0x22d3750_0 .net "outfinal", 0 0, L_0x24780d0; 1 drivers +S_0x22b24b0 .scope generate, "muxbits[7]" "muxbits[7]" 2 290, 2 290, S_0x22690e0; + .timescale -9 -12; +P_0x22a5108 .param/l "i" 2 290, +C4<0111>; +L_0x247b230/d .functor OR 1, L_0x247b370, L_0x247ba00, C4<0>, C4<0>; +L_0x247b230 .delay (20000,20000,20000) L_0x247b230/d; +v0x22d0f90_0 .net *"_s15", 0 0, L_0x247b370; 1 drivers +v0x22cd680_0 .net *"_s16", 0 0, L_0x247ba00; 1 drivers +S_0x22c75c0 .scope module, "ZeroMux" "FourInMux" 2 292, 2 24, S_0x22b24b0; + .timescale -9 -12; +L_0x243e770/d .functor NOT 1, L_0x2479c00, C4<0>, C4<0>, C4<0>; +L_0x243e770 .delay (10000,10000,10000) L_0x243e770/d; +L_0x243e820/d .functor NOT 1, L_0x2479140, C4<0>, C4<0>, C4<0>; +L_0x243e820 .delay (10000,10000,10000) L_0x243e820/d; +L_0x2479580/d .functor NAND 1, L_0x243e770, L_0x243e820, L_0x2479270, C4<1>; +L_0x2479580 .delay (10000,10000,10000) L_0x2479580/d; +L_0x24796c0/d .functor NAND 1, L_0x2479c00, L_0x243e820, L_0x2479310, C4<1>; +L_0x24796c0 .delay (10000,10000,10000) L_0x24796c0/d; +L_0x24797b0/d .functor NAND 1, L_0x243e770, L_0x2479140, L_0x24793b0, C4<1>; +L_0x24797b0 .delay (10000,10000,10000) L_0x24797b0/d; +L_0x24798a0/d .functor NAND 1, L_0x2479c00, L_0x2479140, L_0x24794a0, C4<1>; +L_0x24798a0 .delay (10000,10000,10000) L_0x24798a0/d; +L_0x2479980/d .functor NAND 1, L_0x2479580, L_0x24796c0, L_0x24797b0, L_0x24798a0; +L_0x2479980 .delay (10000,10000,10000) L_0x2479980/d; +v0x22c7900_0 .net "S0", 0 0, L_0x2479c00; 1 drivers +v0x22cfcd0_0 .net "S1", 0 0, L_0x2479140; 1 drivers +v0x22cfd70_0 .net "in0", 0 0, L_0x2479270; 1 drivers +v0x22cfa20_0 .net "in1", 0 0, L_0x2479310; 1 drivers +v0x22cfac0_0 .net "in2", 0 0, L_0x24793b0; 1 drivers +v0x22cf770_0 .net "in3", 0 0, L_0x24794a0; 1 drivers +v0x22cf810_0 .net "nS0", 0 0, L_0x243e770; 1 drivers +v0x22cf4d0_0 .net "nS1", 0 0, L_0x243e820; 1 drivers +v0x22cf570_0 .net "out", 0 0, L_0x2479980; 1 drivers +v0x22cdbe0_0 .net "out0", 0 0, L_0x2479580; 1 drivers +v0x22cdc80_0 .net "out1", 0 0, L_0x24796c0; 1 drivers +v0x22cd930_0 .net "out2", 0 0, L_0x24797b0; 1 drivers +v0x22d0ef0_0 .net "out3", 0 0, L_0x24798a0; 1 drivers +S_0x22c9eb0 .scope module, "OneMux" "FourInMux" 2 293, 2 24, S_0x22b24b0; + .timescale -9 -12; +L_0x247a1b0/d .functor NOT 1, L_0x2479d30, C4<0>, C4<0>, C4<0>; +L_0x247a1b0 .delay (10000,10000,10000) L_0x247a1b0/d; +L_0x247a2a0/d .functor NOT 1, L_0x2479e60, C4<0>, C4<0>, C4<0>; +L_0x247a2a0 .delay (10000,10000,10000) L_0x247a2a0/d; +L_0x247a340/d .functor NAND 1, L_0x247a1b0, L_0x247a2a0, L_0x2479f90, C4<1>; +L_0x247a340 .delay (10000,10000,10000) L_0x247a340/d; +L_0x247a480/d .functor NAND 1, L_0x2479d30, L_0x247a2a0, L_0x247a030, C4<1>; +L_0x247a480 .delay (10000,10000,10000) L_0x247a480/d; +L_0x247a570/d .functor NAND 1, L_0x247a1b0, L_0x2479e60, L_0x247ae20, C4<1>; +L_0x247a570 .delay (10000,10000,10000) L_0x247a570/d; +L_0x247a660/d .functor NAND 1, L_0x2479d30, L_0x2479e60, L_0x247aec0, C4<1>; +L_0x247a660 .delay (10000,10000,10000) L_0x247a660/d; +L_0x247a740/d .functor NAND 1, L_0x247a340, L_0x247a480, L_0x247a570, L_0x247a660; +L_0x247a740 .delay (10000,10000,10000) L_0x247a740/d; +v0x22b0560_0 .net "S0", 0 0, L_0x2479d30; 1 drivers +v0x22c9c00_0 .net "S1", 0 0, L_0x2479e60; 1 drivers +v0x22c9ca0_0 .net "in0", 0 0, L_0x2479f90; 1 drivers +v0x22c9950_0 .net "in1", 0 0, L_0x247a030; 1 drivers +v0x22c99f0_0 .net "in2", 0 0, L_0x247ae20; 1 drivers +v0x22c96b0_0 .net "in3", 0 0, L_0x247aec0; 1 drivers +v0x22c7dc0_0 .net "nS0", 0 0, L_0x247a1b0; 1 drivers +v0x22c7e60_0 .net "nS1", 0 0, L_0x247a2a0; 1 drivers +v0x22c7b10_0 .net "out", 0 0, L_0x247a740; 1 drivers +v0x22c7bb0_0 .net "out0", 0 0, L_0x247a340; 1 drivers +v0x22cb0d0_0 .net "out1", 0 0, L_0x247a480; 1 drivers +v0x22cb170_0 .net "out2", 0 0, L_0x247a570; 1 drivers +v0x22c7860_0 .net "out3", 0 0, L_0x247a660; 1 drivers +S_0x22b0c60 .scope module, "TwoMux" "TwoInMux" 2 294, 2 8, S_0x22b24b0; + .timescale -9 -12; +L_0x247a9c0/d .functor NOT 1, L_0x247b4c0, C4<0>, C4<0>, C4<0>; +L_0x247a9c0 .delay (10000,10000,10000) L_0x247a9c0/d; +L_0x247aa70/d .functor AND 1, L_0x247afb0, L_0x247a9c0, C4<1>, C4<1>; +L_0x247aa70 .delay (20000,20000,20000) L_0x247aa70/d; +L_0x247ab60/d .functor AND 1, L_0x247b0a0, L_0x247b4c0, C4<1>, C4<1>; +L_0x247ab60 .delay (20000,20000,20000) L_0x247ab60/d; +L_0x247ac50/d .functor OR 1, L_0x247aa70, L_0x247ab60, C4<0>, C4<0>; +L_0x247ac50 .delay (20000,20000,20000) L_0x247ac50/d; +v0x22b09d0_0 .net "S", 0 0, L_0x247b4c0; 1 drivers +v0x22b0a70_0 .net "in0", 0 0, L_0x247afb0; 1 drivers +v0x22b3df0_0 .net "in1", 0 0, L_0x247b0a0; 1 drivers +v0x22b3e90_0 .net "nS", 0 0, L_0x247a9c0; 1 drivers +v0x22b0740_0 .net "out0", 0 0, L_0x247aa70; 1 drivers +v0x22b07e0_0 .net "out1", 0 0, L_0x247ab60; 1 drivers +v0x22b04c0_0 .net "outfinal", 0 0, L_0x247ac50; 1 drivers +S_0x2293b80 .scope generate, "muxbits[8]" "muxbits[8]" 2 290, 2 290, S_0x22690e0; + .timescale -9 -12; +P_0x228bbf8 .param/l "i" 2 290, +C4<01000>; +L_0x24735c0/d .functor OR 1, L_0x247dc00, L_0x2473bf0, C4<0>, C4<0>; +L_0x24735c0 .delay (20000,20000,20000) L_0x24735c0/d; +v0x22b2730_0 .net *"_s15", 0 0, L_0x247dc00; 1 drivers +v0x22b27f0_0 .net *"_s16", 0 0, L_0x2473bf0; 1 drivers +S_0x22ab100 .scope module, "ZeroMux" "FourInMux" 2 292, 2 24, S_0x2293b80; + .timescale -9 -12; +L_0x247baa0/d .functor NOT 1, L_0x247b560, C4<0>, C4<0>, C4<0>; +L_0x247baa0 .delay (10000,10000,10000) L_0x247baa0/d; +L_0x247bb50/d .functor NOT 1, L_0x247b690, C4<0>, C4<0>, C4<0>; +L_0x247bb50 .delay (10000,10000,10000) L_0x247bb50/d; +L_0x247bbf0/d .functor NAND 1, L_0x247baa0, L_0x247bb50, L_0x247b7c0, C4<1>; +L_0x247bbf0 .delay (10000,10000,10000) L_0x247bbf0/d; +L_0x247bd30/d .functor NAND 1, L_0x247b560, L_0x247bb50, L_0x247b860, C4<1>; +L_0x247bd30 .delay (10000,10000,10000) L_0x247bd30/d; +L_0x247be20/d .functor NAND 1, L_0x247baa0, L_0x247b690, L_0x247b900, C4<1>; +L_0x247be20 .delay (10000,10000,10000) L_0x247be20/d; +L_0x247bf10/d .functor NAND 1, L_0x247b560, L_0x247b690, L_0x247c740, C4<1>; +L_0x247bf10 .delay (10000,10000,10000) L_0x247bf10/d; +L_0x247bff0/d .functor NAND 1, L_0x247bbf0, L_0x247bd30, L_0x247be20, L_0x247bf10; +L_0x247bff0 .delay (10000,10000,10000) L_0x247bff0/d; +v0x22ac9f0_0 .net "S0", 0 0, L_0x247b560; 1 drivers +v0x22aae70_0 .net "S1", 0 0, L_0x247b690; 1 drivers +v0x22aaf10_0 .net "in0", 0 0, L_0x247b7c0; 1 drivers +v0x22ae290_0 .net "in1", 0 0, L_0x247b860; 1 drivers +v0x22ae330_0 .net "in2", 0 0, L_0x247b900; 1 drivers +v0x22aabe0_0 .net "in3", 0 0, L_0x247c740; 1 drivers +v0x22aac80_0 .net "nS0", 0 0, L_0x247baa0; 1 drivers +v0x22aa960_0 .net "nS1", 0 0, L_0x247bb50; 1 drivers +v0x22aaa00_0 .net "out", 0 0, L_0x247bff0; 1 drivers +v0x22b2c50_0 .net "out0", 0 0, L_0x247bbf0; 1 drivers +v0x22b2cf0_0 .net "out1", 0 0, L_0x247bd30; 1 drivers +v0x22b29c0_0 .net "out2", 0 0, L_0x247be20; 1 drivers +v0x22b2a60_0 .net "out3", 0 0, L_0x247bf10; 1 drivers +S_0x22a55a0 .scope module, "OneMux" "FourInMux" 2 293, 2 24, S_0x2293b80; + .timescale -9 -12; +L_0x247c270/d .functor NOT 1, L_0x247d070, C4<0>, C4<0>, C4<0>; +L_0x247c270 .delay (10000,10000,10000) L_0x247c270/d; +L_0x247c360/d .functor NOT 1, L_0x247c830, C4<0>, C4<0>, C4<0>; +L_0x247c360 .delay (10000,10000,10000) L_0x247c360/d; +L_0x247c400/d .functor NAND 1, L_0x247c270, L_0x247c360, L_0x247c960, C4<1>; +L_0x247c400 .delay (10000,10000,10000) L_0x247c400/d; +L_0x247c540/d .functor NAND 1, L_0x247d070, L_0x247c360, L_0x247cc10, C4<1>; +L_0x247c540 .delay (10000,10000,10000) L_0x247c540/d; +L_0x247c630/d .functor NAND 1, L_0x247c270, L_0x247c830, L_0x2472d50, C4<1>; +L_0x247c630 .delay (10000,10000,10000) L_0x247c630/d; +L_0x247cd10/d .functor NAND 1, L_0x247d070, L_0x247c830, L_0x247d6b0, C4<1>; +L_0x247cd10 .delay (10000,10000,10000) L_0x247cd10/d; +L_0x247cdf0/d .functor NAND 1, L_0x247c400, L_0x247c540, L_0x247c630, L_0x247cd10; +L_0x247cdf0 .delay (10000,10000,10000) L_0x247cdf0/d; +v0x22a6e90_0 .net "S0", 0 0, L_0x247d070; 1 drivers +v0x22a5310_0 .net "S1", 0 0, L_0x247c830; 1 drivers +v0x22a53b0_0 .net "in0", 0 0, L_0x247c960; 1 drivers +v0x22a8730_0 .net "in1", 0 0, L_0x247cc10; 1 drivers +v0x22a87d0_0 .net "in2", 0 0, L_0x2472d50; 1 drivers +v0x22a5080_0 .net "in3", 0 0, L_0x247d6b0; 1 drivers +v0x22ad0f0_0 .net "nS0", 0 0, L_0x247c270; 1 drivers +v0x22ad190_0 .net "nS1", 0 0, L_0x247c360; 1 drivers +v0x22ace60_0 .net "out", 0 0, L_0x247cdf0; 1 drivers +v0x22acf00_0 .net "out0", 0 0, L_0x247c400; 1 drivers +v0x22acbd0_0 .net "out1", 0 0, L_0x247c540; 1 drivers +v0x22acc70_0 .net "out2", 0 0, L_0x247c630; 1 drivers +v0x22ac950_0 .net "out3", 0 0, L_0x247cd10; 1 drivers +S_0x2293900 .scope module, "TwoMux" "TwoInMux" 2 294, 2 8, S_0x2293b80; + .timescale -9 -12; +L_0x247d750/d .functor NOT 1, L_0x247d1a0, C4<0>, C4<0>, C4<0>; +L_0x247d750 .delay (10000,10000,10000) L_0x247d750/d; +L_0x247d840/d .functor AND 1, L_0x247d240, L_0x247d750, C4<1>, C4<1>; +L_0x247d840 .delay (20000,20000,20000) L_0x247d840/d; +L_0x247d930/d .functor AND 1, L_0x24737a0, L_0x247d1a0, C4<1>, C4<1>; +L_0x247d930 .delay (20000,20000,20000) L_0x247d930/d; +L_0x247da20/d .functor OR 1, L_0x247d840, L_0x247d930, C4<0>, C4<0>; +L_0x247da20 .delay (20000,20000,20000) L_0x247da20/d; +v0x2293e90_0 .net "S", 0 0, L_0x247d1a0; 1 drivers +v0x22a7590_0 .net "in0", 0 0, L_0x247d240; 1 drivers +v0x22a7630_0 .net "in1", 0 0, L_0x24737a0; 1 drivers +v0x22a7300_0 .net "nS", 0 0, L_0x247d750; 1 drivers +v0x22a7380_0 .net "out0", 0 0, L_0x247d840; 1 drivers +v0x22a7070_0 .net "out1", 0 0, L_0x247d930; 1 drivers +v0x22a6df0_0 .net "outfinal", 0 0, L_0x247da20; 1 drivers +S_0x2271240 .scope generate, "muxbits[9]" "muxbits[9]" 2 290, 2 290, S_0x22690e0; + .timescale -9 -12; +P_0x226d758 .param/l "i" 2 290, +C4<01001>; +L_0x247fef0/d .functor OR 1, L_0x2480030, L_0x24800d0, C4<0>, C4<0>; +L_0x247fef0 .delay (20000,20000,20000) L_0x247fef0/d; +v0x2294140_0 .net *"_s15", 0 0, L_0x2480030; 1 drivers +v0x2293e10_0 .net *"_s16", 0 0, L_0x24800d0; 1 drivers +S_0x2290010 .scope module, "ZeroMux" "FourInMux" 2 292, 2 24, S_0x2271240; + .timescale -9 -12; +L_0x247e0c0/d .functor NOT 1, L_0x247eeb0, C4<0>, C4<0>, C4<0>; +L_0x247e0c0 .delay (10000,10000,10000) L_0x247e0c0/d; +L_0x2473da0/d .functor NOT 1, L_0x247e340, C4<0>, C4<0>, C4<0>; +L_0x2473da0 .delay (10000,10000,10000) L_0x2473da0/d; +L_0x2473e40/d .functor NAND 1, L_0x247e0c0, L_0x2473da0, L_0x247e470, C4<1>; +L_0x2473e40 .delay (10000,10000,10000) L_0x2473e40/d; +L_0x247e970/d .functor NAND 1, L_0x247eeb0, L_0x2473da0, L_0x247e510, C4<1>; +L_0x247e970 .delay (10000,10000,10000) L_0x247e970/d; +L_0x247ea60/d .functor NAND 1, L_0x247e0c0, L_0x247e340, L_0x247e5b0, C4<1>; +L_0x247ea60 .delay (10000,10000,10000) L_0x247ea60/d; +L_0x247eb50/d .functor NAND 1, L_0x247eeb0, L_0x247e340, L_0x247e6a0, C4<1>; +L_0x247eb50 .delay (10000,10000,10000) L_0x247eb50/d; +L_0x247ec30/d .functor NAND 1, L_0x2473e40, L_0x247e970, L_0x247ea60, L_0x247eb50; +L_0x247ec30 .delay (10000,10000,10000) L_0x247ec30/d; +v0x2290340_0 .net "S0", 0 0, L_0x247eeb0; 1 drivers +v0x228fd90_0 .net "S1", 0 0, L_0x247e340; 1 drivers +v0x228fe30_0 .net "in0", 0 0, L_0x247e470; 1 drivers +v0x228e540_0 .net "in1", 0 0, L_0x247e510; 1 drivers +v0x228e5e0_0 .net "in2", 0 0, L_0x247e5b0; 1 drivers +v0x228e2b0_0 .net "in3", 0 0, L_0x247e6a0; 1 drivers +v0x228e350_0 .net "nS0", 0 0, L_0x247e0c0; 1 drivers +v0x22916d0_0 .net "nS1", 0 0, L_0x2473da0; 1 drivers +v0x2291770_0 .net "out", 0 0, L_0x247ec30; 1 drivers +v0x228e020_0 .net "out0", 0 0, L_0x2473e40; 1 drivers +v0x228e0c0_0 .net "out1", 0 0, L_0x247e970; 1 drivers +v0x228dda0_0 .net "out2", 0 0, L_0x247ea60; 1 drivers +v0x22940a0_0 .net "out3", 0 0, L_0x247eb50; 1 drivers +S_0x228a230 .scope module, "OneMux" "FourInMux" 2 293, 2 24, S_0x2271240; + .timescale -9 -12; +L_0x247e790/d .functor NOT 1, L_0x247efe0, C4<0>, C4<0>, C4<0>; +L_0x247e790 .delay (10000,10000,10000) L_0x247e790/d; +L_0x247e830/d .functor NOT 1, L_0x247f110, C4<0>, C4<0>, C4<0>; +L_0x247e830 .delay (10000,10000,10000) L_0x247e830/d; +L_0x247f5f0/d .functor NAND 1, L_0x247e790, L_0x247e830, L_0x247f240, C4<1>; +L_0x247f5f0 .delay (10000,10000,10000) L_0x247f5f0/d; +L_0x247f730/d .functor NAND 1, L_0x247efe0, L_0x247e830, L_0x247f2e0, C4<1>; +L_0x247f730 .delay (10000,10000,10000) L_0x247f730/d; +L_0x247f820/d .functor NAND 1, L_0x247e790, L_0x247f110, L_0x247f380, C4<1>; +L_0x247f820 .delay (10000,10000,10000) L_0x247f820/d; +L_0x247f910/d .functor NAND 1, L_0x247efe0, L_0x247f110, L_0x247f470, C4<1>; +L_0x247f910 .delay (10000,10000,10000) L_0x247f910/d; +L_0x247f9f0/d .functor NAND 1, L_0x247f5f0, L_0x247f730, L_0x247f820, L_0x247f910; +L_0x247f9f0 .delay (10000,10000,10000) L_0x247f9f0/d; +v0x228a550_0 .net "S0", 0 0, L_0x247efe0; 1 drivers +v0x22889e0_0 .net "S1", 0 0, L_0x247f110; 1 drivers +v0x2288a80_0 .net "in0", 0 0, L_0x247f240; 1 drivers +v0x2288750_0 .net "in1", 0 0, L_0x247f2e0; 1 drivers +v0x22887f0_0 .net "in2", 0 0, L_0x247f380; 1 drivers +v0x228bb70_0 .net "in3", 0 0, L_0x247f470; 1 drivers +v0x22884c0_0 .net "nS0", 0 0, L_0x247e790; 1 drivers +v0x2288560_0 .net "nS1", 0 0, L_0x247e830; 1 drivers +v0x2288240_0 .net "out", 0 0, L_0x247f9f0; 1 drivers +v0x22882e0_0 .net "out0", 0 0, L_0x247f5f0; 1 drivers +v0x2290530_0 .net "out1", 0 0, L_0x247f730; 1 drivers +v0x22905d0_0 .net "out2", 0 0, L_0x247f820; 1 drivers +v0x22902a0_0 .net "out3", 0 0, L_0x247f910; 1 drivers +S_0x2284e70 .scope module, "TwoMux" "TwoInMux" 2 294, 2 8, S_0x2271240; + .timescale -9 -12; +L_0x2480230/d .functor NOT 1, L_0x24806e0, C4<0>, C4<0>, C4<0>; +L_0x2480230 .delay (10000,10000,10000) L_0x2480230/d; +L_0x2480320/d .functor AND 1, L_0x247fc70, L_0x2480230, C4<1>, C4<1>; +L_0x2480320 .delay (20000,20000,20000) L_0x2480320/d; +L_0x2480410/d .functor AND 1, L_0x247fd60, L_0x24806e0, C4<1>, C4<1>; +L_0x2480410 .delay (20000,20000,20000) L_0x2480410/d; +L_0x2480500/d .functor OR 1, L_0x2480320, L_0x2480410, C4<0>, C4<0>; +L_0x2480500 .delay (20000,20000,20000) L_0x2480500/d; +v0x2286010_0 .net "S", 0 0, L_0x24806e0; 1 drivers +v0x22860b0_0 .net "in0", 0 0, L_0x247fc70; 1 drivers +v0x228a9d0_0 .net "in1", 0 0, L_0x247fd60; 1 drivers +v0x228aa70_0 .net "nS", 0 0, L_0x2480230; 1 drivers +v0x228a740_0 .net "out0", 0 0, L_0x2480320; 1 drivers +v0x228a7e0_0 .net "out1", 0 0, L_0x2480410; 1 drivers +v0x228a4b0_0 .net "outfinal", 0 0, L_0x2480500; 1 drivers +S_0x2267b70 .scope generate, "muxbits[10]" "muxbits[10]" 2 290, 2 290, S_0x22690e0; + .timescale -9 -12; +P_0x2353df8 .param/l "i" 2 290, +C4<01010>; +L_0x2482750/d .functor OR 1, L_0x2482890, L_0x2482930, C4<0>, C4<0>; +L_0x2482750 .delay (20000,20000,20000) L_0x2482750/d; +v0x22714c0_0 .net *"_s15", 0 0, L_0x2482890; 1 drivers +v0x2271580_0 .net *"_s16", 0 0, L_0x2482930; 1 drivers +S_0x226b6e0 .scope module, "ZeroMux" "FourInMux" 2 292, 2 24, S_0x2267b70; + .timescale -9 -12; +L_0x24801c0/d .functor NOT 1, L_0x2480780, C4<0>, C4<0>, C4<0>; +L_0x24801c0 .delay (10000,10000,10000) L_0x24801c0/d; +L_0x2480e00/d .functor NOT 1, L_0x24808b0, C4<0>, C4<0>, C4<0>; +L_0x2480e00 .delay (10000,10000,10000) L_0x2480e00/d; +L_0x2480ea0/d .functor NAND 1, L_0x24801c0, L_0x2480e00, L_0x24809e0, C4<1>; +L_0x2480ea0 .delay (10000,10000,10000) L_0x2480ea0/d; +L_0x2480fe0/d .functor NAND 1, L_0x2480780, L_0x2480e00, L_0x2480a80, C4<1>; +L_0x2480fe0 .delay (10000,10000,10000) L_0x2480fe0/d; +L_0x24810d0/d .functor NAND 1, L_0x24801c0, L_0x24808b0, L_0x2480b20, C4<1>; +L_0x24810d0 .delay (10000,10000,10000) L_0x24810d0/d; +L_0x24811c0/d .functor NAND 1, L_0x2480780, L_0x24808b0, L_0x2480c10, C4<1>; +L_0x24811c0 .delay (10000,10000,10000) L_0x24811c0/d; +L_0x24812a0/d .functor NAND 1, L_0x2480ea0, L_0x2480fe0, L_0x24810d0, L_0x24811c0; +L_0x24812a0 .delay (10000,10000,10000) L_0x24812a0/d; +v0x226ba00_0 .net "S0", 0 0, L_0x2480780; 1 drivers +v0x22739d0_0 .net "S1", 0 0, L_0x24808b0; 1 drivers +v0x2273a70_0 .net "in0", 0 0, L_0x24809e0; 1 drivers +v0x2273740_0 .net "in1", 0 0, L_0x2480a80; 1 drivers +v0x22737e0_0 .net "in2", 0 0, L_0x2480b20; 1 drivers +v0x22734b0_0 .net "in3", 0 0, L_0x2480c10; 1 drivers +v0x2273550_0 .net "nS0", 0 0, L_0x24801c0; 1 drivers +v0x2273230_0 .net "nS1", 0 0, L_0x2480e00; 1 drivers +v0x22732d0_0 .net "out", 0 0, L_0x24812a0; 1 drivers +v0x22719e0_0 .net "out0", 0 0, L_0x2480ea0; 1 drivers +v0x2271a80_0 .net "out1", 0 0, L_0x2480fe0; 1 drivers +v0x2271750_0 .net "out2", 0 0, L_0x24810d0; 1 drivers +v0x22717f0_0 .net "out3", 0 0, L_0x24811c0; 1 drivers +S_0x226de70 .scope module, "OneMux" "FourInMux" 2 293, 2 24, S_0x2267b70; + .timescale -9 -12; +L_0x2480d00/d .functor NOT 1, L_0x2482300, C4<0>, C4<0>, C4<0>; +L_0x2480d00 .delay (10000,10000,10000) L_0x2480d00/d; +L_0x2481be0/d .functor NOT 1, L_0x2481520, C4<0>, C4<0>, C4<0>; +L_0x2481be0 .delay (10000,10000,10000) L_0x2481be0/d; +L_0x2481c80/d .functor NAND 1, L_0x2480d00, L_0x2481be0, L_0x2481650, C4<1>; +L_0x2481c80 .delay (10000,10000,10000) L_0x2481c80/d; +L_0x2481dc0/d .functor NAND 1, L_0x2482300, L_0x2481be0, L_0x24816f0, C4<1>; +L_0x2481dc0 .delay (10000,10000,10000) L_0x2481dc0/d; +L_0x2481eb0/d .functor NAND 1, L_0x2480d00, L_0x2481520, L_0x2481790, C4<1>; +L_0x2481eb0 .delay (10000,10000,10000) L_0x2481eb0/d; +L_0x2481fa0/d .functor NAND 1, L_0x2482300, L_0x2481520, L_0x2481880, C4<1>; +L_0x2481fa0 .delay (10000,10000,10000) L_0x2481fa0/d; +L_0x2482080/d .functor NAND 1, L_0x2481c80, L_0x2481dc0, L_0x2481eb0, L_0x2481fa0; +L_0x2482080 .delay (10000,10000,10000) L_0x2482080/d; +v0x2265c20_0 .net "S0", 0 0, L_0x2482300; 1 drivers +v0x226dbe0_0 .net "S1", 0 0, L_0x2481520; 1 drivers +v0x226dc80_0 .net "in0", 0 0, L_0x2481650; 1 drivers +v0x226d950_0 .net "in1", 0 0, L_0x24816f0; 1 drivers +v0x226d9f0_0 .net "in2", 0 0, L_0x2481790; 1 drivers +v0x226d6d0_0 .net "in3", 0 0, L_0x2481880; 1 drivers +v0x226be80_0 .net "nS0", 0 0, L_0x2480d00; 1 drivers +v0x226bf20_0 .net "nS1", 0 0, L_0x2481be0; 1 drivers +v0x226bbf0_0 .net "out", 0 0, L_0x2482080; 1 drivers +v0x226bc90_0 .net "out0", 0 0, L_0x2481c80; 1 drivers +v0x226f010_0 .net "out1", 0 0, L_0x2481dc0; 1 drivers +v0x226f0b0_0 .net "out2", 0 0, L_0x2481eb0; 1 drivers +v0x226b960_0 .net "out3", 0 0, L_0x2481fa0; 1 drivers +S_0x2266320 .scope module, "TwoMux" "TwoInMux" 2 294, 2 8, S_0x2267b70; + .timescale -9 -12; +L_0x2481970/d .functor NOT 1, L_0x2482430, C4<0>, C4<0>, C4<0>; +L_0x2481970 .delay (10000,10000,10000) L_0x2481970/d; +L_0x2481a60/d .functor AND 1, L_0x24824d0, L_0x2481970, C4<1>, C4<1>; +L_0x2481a60 .delay (20000,20000,20000) L_0x2481a60/d; +L_0x2482a90/d .functor AND 1, L_0x24825c0, L_0x2482430, C4<1>, C4<1>; +L_0x2482a90 .delay (20000,20000,20000) L_0x2482a90/d; +L_0x2482b80/d .functor OR 1, L_0x2481a60, L_0x2482a90, C4<0>, C4<0>; +L_0x2482b80 .delay (20000,20000,20000) L_0x2482b80/d; +v0x2267e70_0 .net "S", 0 0, L_0x2482430; 1 drivers +v0x2266090_0 .net "in0", 0 0, L_0x24824d0; 1 drivers +v0x2266130_0 .net "in1", 0 0, L_0x24825c0; 1 drivers +v0x22694b0_0 .net "nS", 0 0, L_0x2481970; 1 drivers +v0x2269530_0 .net "out0", 0 0, L_0x2481a60; 1 drivers +v0x2265e00_0 .net "out1", 0 0, L_0x2482a90; 1 drivers +v0x2265b80_0 .net "outfinal", 0 0, L_0x2482b80; 1 drivers +S_0x2278880 .scope generate, "muxbits[11]" "muxbits[11]" 2 290, 2 290, S_0x22690e0; + .timescale -9 -12; +P_0x23e1ea8 .param/l "i" 2 290, +C4<01011>; +L_0x24852d0/d .functor OR 1, L_0x2485410, L_0x24854b0, C4<0>, C4<0>; +L_0x24852d0 .delay (20000,20000,20000) L_0x24852d0/d; +v0x2268120_0 .net *"_s15", 0 0, L_0x2485410; 1 drivers +v0x2267df0_0 .net *"_s16", 0 0, L_0x24854b0; 1 drivers +S_0x23149a0 .scope module, "ZeroMux" "FourInMux" 2 292, 2 24, S_0x2278880; + .timescale -9 -12; +L_0x2482a20/d .functor NOT 1, L_0x2483bb0, C4<0>, C4<0>, C4<0>; +L_0x2482a20 .delay (10000,10000,10000) L_0x2482a20/d; +L_0x2483490/d .functor NOT 1, L_0x2482d60, C4<0>, C4<0>, C4<0>; +L_0x2483490 .delay (10000,10000,10000) L_0x2483490/d; +L_0x2483530/d .functor NAND 1, L_0x2482a20, L_0x2483490, L_0x2482e90, C4<1>; +L_0x2483530 .delay (10000,10000,10000) L_0x2483530/d; +L_0x2483670/d .functor NAND 1, L_0x2483bb0, L_0x2483490, L_0x2483340, C4<1>; +L_0x2483670 .delay (10000,10000,10000) L_0x2483670/d; +L_0x2483760/d .functor NAND 1, L_0x2482a20, L_0x2482d60, L_0x2474d80, C4<1>; +L_0x2483760 .delay (10000,10000,10000) L_0x2483760/d; +L_0x2483850/d .functor NAND 1, L_0x2483bb0, L_0x2482d60, L_0x2474e70, C4<1>; +L_0x2483850 .delay (10000,10000,10000) L_0x2483850/d; +L_0x2483930/d .functor NAND 1, L_0x2483530, L_0x2483670, L_0x2483760, L_0x2483850; +L_0x2483930 .delay (10000,10000,10000) L_0x2483930/d; +v0x2348510_0 .net "S0", 0 0, L_0x2483bb0; 1 drivers +v0x23370b0_0 .net "S1", 0 0, L_0x2482d60; 1 drivers +v0x2337150_0 .net "in0", 0 0, L_0x2482e90; 1 drivers +v0x2334380_0 .net "in1", 0 0, L_0x2483340; 1 drivers +v0x2334420_0 .net "in2", 0 0, L_0x2474d80; 1 drivers +v0x2331540_0 .net "in3", 0 0, L_0x2474e70; 1 drivers +v0x23315e0_0 .net "nS0", 0 0, L_0x2482a20; 1 drivers +v0x230fa00_0 .net "nS1", 0 0, L_0x2483490; 1 drivers +v0x230faa0_0 .net "out", 0 0, L_0x2483930; 1 drivers +v0x236c8e0_0 .net "out0", 0 0, L_0x2483530; 1 drivers +v0x236c980_0 .net "out1", 0 0, L_0x2483670; 1 drivers +v0x2268310_0 .net "out2", 0 0, L_0x2483760; 1 drivers +v0x2268080_0 .net "out3", 0 0, L_0x2483850; 1 drivers +S_0x2328aa0 .scope module, "OneMux" "FourInMux" 2 293, 2 24, S_0x2278880; + .timescale -9 -12; +L_0x2475bc0/d .functor NOT 1, L_0x2484300, C4<0>, C4<0>, C4<0>; +L_0x2475bc0 .delay (10000,10000,10000) L_0x2475bc0/d; +L_0x2475cb0/d .functor NOT 1, L_0x2484f20, C4<0>, C4<0>, C4<0>; +L_0x2475cb0 .delay (10000,10000,10000) L_0x2475cb0/d; +L_0x2475d50/d .functor NAND 1, L_0x2475bc0, L_0x2475cb0, L_0x24847b0, C4<1>; +L_0x2475d50 .delay (10000,10000,10000) L_0x2475d50/d; +L_0x2483dc0/d .functor NAND 1, L_0x2484300, L_0x2475cb0, L_0x2484850, C4<1>; +L_0x2483dc0 .delay (10000,10000,10000) L_0x2483dc0/d; +L_0x2483eb0/d .functor NAND 1, L_0x2475bc0, L_0x2484f20, L_0x24848f0, C4<1>; +L_0x2483eb0 .delay (10000,10000,10000) L_0x2483eb0/d; +L_0x2483fa0/d .functor NAND 1, L_0x2484300, L_0x2484f20, L_0x24849e0, C4<1>; +L_0x2483fa0 .delay (10000,10000,10000) L_0x2483fa0/d; +L_0x2484080/d .functor NAND 1, L_0x2475d50, L_0x2483dc0, L_0x2483eb0, L_0x2483fa0; +L_0x2484080 .delay (10000,10000,10000) L_0x2484080/d; +v0x2311c00_0 .net "S0", 0 0, L_0x2484300; 1 drivers +v0x2367de0_0 .net "S1", 0 0, L_0x2484f20; 1 drivers +v0x2367e80_0 .net "in0", 0 0, L_0x24847b0; 1 drivers +v0x2317690_0 .net "in1", 0 0, L_0x2484850; 1 drivers +v0x2317730_0 .net "in2", 0 0, L_0x24848f0; 1 drivers +v0x2353d70_0 .net "in3", 0 0, L_0x24849e0; 1 drivers +v0x2350f30_0 .net "nS0", 0 0, L_0x2475bc0; 1 drivers +v0x2350fd0_0 .net "nS1", 0 0, L_0x2475cb0; 1 drivers +v0x234e0f0_0 .net "out", 0 0, L_0x2484080; 1 drivers +v0x234e190_0 .net "out0", 0 0, L_0x2475d50; 1 drivers +v0x234b2b0_0 .net "out1", 0 0, L_0x2483dc0; 1 drivers +v0x234b350_0 .net "out2", 0 0, L_0x2483eb0; 1 drivers +v0x2348470_0 .net "out3", 0 0, L_0x2483fa0; 1 drivers +S_0x2276840 .scope module, "TwoMux" "TwoInMux" 2 294, 2 8, S_0x2278880; + .timescale -9 -12; +L_0x2484ad0/d .functor NOT 1, L_0x2485850, C4<0>, C4<0>, C4<0>; +L_0x2484ad0 .delay (10000,10000,10000) L_0x2484ad0/d; +L_0x2484bc0/d .functor AND 1, L_0x2485050, L_0x2484ad0, C4<1>, C4<1>; +L_0x2484bc0 .delay (20000,20000,20000) L_0x2484bc0/d; +L_0x2484cb0/d .functor AND 1, L_0x2485140, L_0x2485850, C4<1>, C4<1>; +L_0x2484cb0 .delay (20000,20000,20000) L_0x2484cb0/d; +L_0x2484da0/d .functor OR 1, L_0x2484bc0, L_0x2484cb0, C4<0>, C4<0>; +L_0x2484da0 .delay (20000,20000,20000) L_0x2484da0/d; +v0x2259bc0_0 .net "S", 0 0, L_0x2485850; 1 drivers +v0x2259c60_0 .net "in0", 0 0, L_0x2485050; 1 drivers +v0x232e700_0 .net "in1", 0 0, L_0x2485140; 1 drivers +v0x232e7a0_0 .net "nS", 0 0, L_0x2484ad0; 1 drivers +v0x232b8c0_0 .net "out0", 0 0, L_0x2484bc0; 1 drivers +v0x232b960_0 .net "out1", 0 0, L_0x2484cb0; 1 drivers +v0x2311b60_0 .net "outfinal", 0 0, L_0x2484da0; 1 drivers +S_0x22e09f0 .scope generate, "muxbits[12]" "muxbits[12]" 2 290, 2 290, S_0x22690e0; + .timescale -9 -12; +P_0x23e3978 .param/l "i" 2 290, +C4<01100>; +L_0x2487900/d .functor OR 1, L_0x2487a40, L_0x2487ae0, C4<0>, C4<0>; +L_0x2487900 .delay (20000,20000,20000) L_0x2487900/d; +v0x227c490_0 .net *"_s15", 0 0, L_0x2487a40; 1 drivers +v0x227c550_0 .net *"_s16", 0 0, L_0x2487ae0; 1 drivers +S_0x229ebf0 .scope module, "ZeroMux" "FourInMux" 2 292, 2 24, S_0x22e09f0; + .timescale -9 -12; +L_0x24855a0/d .functor NOT 1, L_0x24858f0, C4<0>, C4<0>, C4<0>; +L_0x24855a0 .delay (10000,10000,10000) L_0x24855a0/d; +L_0x2485690/d .functor NOT 1, L_0x2485a20, C4<0>, C4<0>, C4<0>; +L_0x2485690 .delay (10000,10000,10000) L_0x2485690/d; +L_0x2486030/d .functor NAND 1, L_0x24855a0, L_0x2485690, L_0x2485b50, C4<1>; +L_0x2486030 .delay (10000,10000,10000) L_0x2486030/d; +L_0x2486170/d .functor NAND 1, L_0x24858f0, L_0x2485690, L_0x2485bf0, C4<1>; +L_0x2486170 .delay (10000,10000,10000) L_0x2486170/d; +L_0x2486260/d .functor NAND 1, L_0x24855a0, L_0x2485a20, L_0x2485c90, C4<1>; +L_0x2486260 .delay (10000,10000,10000) L_0x2486260/d; +L_0x2486350/d .functor NAND 1, L_0x24858f0, L_0x2485a20, L_0x2485d80, C4<1>; +L_0x2486350 .delay (10000,10000,10000) L_0x2486350/d; +L_0x2486430/d .functor NAND 1, L_0x2486030, L_0x2486170, L_0x2486260, L_0x2486350; +L_0x2486430 .delay (10000,10000,10000) L_0x2486430/d; +v0x229afe0_0 .net "S0", 0 0, L_0x24858f0; 1 drivers +v0x229b0a0_0 .net "S1", 0 0, L_0x2485a20; 1 drivers +v0x2298fa0_0 .net "in0", 0 0, L_0x2485b50; 1 drivers +v0x2299040_0 .net "in1", 0 0, L_0x2485bf0; 1 drivers +v0x2295390_0 .net "in2", 0 0, L_0x2485c90; 1 drivers +v0x2295430_0 .net "in3", 0 0, L_0x2485d80; 1 drivers +v0x225f9d0_0 .net "nS0", 0 0, L_0x24855a0; 1 drivers +v0x225fa70_0 .net "nS1", 0 0, L_0x2485690; 1 drivers +v0x2284120_0 .net "out", 0 0, L_0x2486430; 1 drivers +v0x22841c0_0 .net "out0", 0 0, L_0x2486030; 1 drivers +v0x22820e0_0 .net "out1", 0 0, L_0x2486170; 1 drivers +v0x2282180_0 .net "out2", 0 0, L_0x2486260; 1 drivers +v0x227e560_0 .net "out3", 0 0, L_0x2486350; 1 drivers +S_0x22c1360 .scope module, "OneMux" "FourInMux" 2 293, 2 24, S_0x22e09f0; + .timescale -9 -12; +L_0x2485e70/d .functor NOT 1, L_0x24874b0, C4<0>, C4<0>, C4<0>; +L_0x2485e70 .delay (10000,10000,10000) L_0x2485e70/d; +L_0x2485f60/d .functor NOT 1, L_0x24866b0, C4<0>, C4<0>, C4<0>; +L_0x2485f60 .delay (10000,10000,10000) L_0x2485f60/d; +L_0x2486e30/d .functor NAND 1, L_0x2485e70, L_0x2485f60, L_0x24867e0, C4<1>; +L_0x2486e30 .delay (10000,10000,10000) L_0x2486e30/d; +L_0x2486f70/d .functor NAND 1, L_0x24874b0, L_0x2485f60, L_0x2486880, C4<1>; +L_0x2486f70 .delay (10000,10000,10000) L_0x2486f70/d; +L_0x2487060/d .functor NAND 1, L_0x2485e70, L_0x24866b0, L_0x2486920, C4<1>; +L_0x2487060 .delay (10000,10000,10000) L_0x2487060/d; +L_0x2487150/d .functor NAND 1, L_0x24874b0, L_0x24866b0, L_0x2486a10, C4<1>; +L_0x2487150 .delay (10000,10000,10000) L_0x2487150/d; +L_0x2487230/d .functor NAND 1, L_0x2486e30, L_0x2486f70, L_0x2487060, L_0x2487150; +L_0x2487230 .delay (10000,10000,10000) L_0x2487230/d; +v0x22bd750_0 .net "S0", 0 0, L_0x24874b0; 1 drivers +v0x22bd810_0 .net "S1", 0 0, L_0x24866b0; 1 drivers +v0x22bb710_0 .net "in0", 0 0, L_0x24867e0; 1 drivers +v0x22bb7b0_0 .net "in1", 0 0, L_0x2486880; 1 drivers +v0x22b7b00_0 .net "in2", 0 0, L_0x2486920; 1 drivers +v0x22b7ba0_0 .net "in3", 0 0, L_0x2486a10; 1 drivers +v0x22b5ac0_0 .net "nS0", 0 0, L_0x2485e70; 1 drivers +v0x22b5b60_0 .net "nS1", 0 0, L_0x2485f60; 1 drivers +v0x2261a10_0 .net "out", 0 0, L_0x2487230; 1 drivers +v0x2261ab0_0 .net "out0", 0 0, L_0x2486e30; 1 drivers +v0x22a4840_0 .net "out1", 0 0, L_0x2486f70; 1 drivers +v0x22a48e0_0 .net "out2", 0 0, L_0x2487060; 1 drivers +v0x22a0cc0_0 .net "out3", 0 0, L_0x2487150; 1 drivers +S_0x22de920 .scope module, "TwoMux" "TwoInMux" 2 294, 2 8, S_0x22e09f0; + .timescale -9 -12; +L_0x2486b00/d .functor NOT 1, L_0x24875e0, C4<0>, C4<0>, C4<0>; +L_0x2486b00 .delay (10000,10000,10000) L_0x2486b00/d; +L_0x2486bf0/d .functor AND 1, L_0x2487680, L_0x2486b00, C4<1>, C4<1>; +L_0x2486bf0 .delay (20000,20000,20000) L_0x2486bf0/d; +L_0x2486ce0/d .functor AND 1, L_0x2487770, L_0x24875e0, C4<1>, C4<1>; +L_0x2486ce0 .delay (20000,20000,20000) L_0x2486ce0/d; +L_0x2486dd0/d .functor OR 1, L_0x2486bf0, L_0x2486ce0, C4<0>, C4<0>; +L_0x2486dd0 .delay (20000,20000,20000) L_0x2486dd0/d; +v0x22e4800_0 .net "S", 0 0, L_0x24875e0; 1 drivers +v0x22dab90_0 .net "in0", 0 0, L_0x2487680; 1 drivers +v0x22dac30_0 .net "in1", 0 0, L_0x2487770; 1 drivers +v0x22d8ac0_0 .net "nS", 0 0, L_0x2486b00; 1 drivers +v0x22d8b40_0 .net "out0", 0 0, L_0x2486bf0; 1 drivers +v0x22c33a0_0 .net "out1", 0 0, L_0x2486ce0; 1 drivers +v0x22c3440_0 .net "outfinal", 0 0, L_0x2486dd0; 1 drivers +S_0x2111ab0 .scope generate, "muxbits[13]" "muxbits[13]" 2 290, 2 290, S_0x22690e0; + .timescale -9 -12; +P_0x23031a8 .param/l "i" 2 290, +C4<01101>; +L_0x2489e70/d .functor OR 1, L_0x2489fb0, L_0x248a050, C4<0>, C4<0>; +L_0x2489e70 .delay (20000,20000,20000) L_0x2489e70/d; +v0x22e68f0_0 .net *"_s15", 0 0, L_0x2489fb0; 1 drivers +v0x22e4780_0 .net *"_s16", 0 0, L_0x248a050; 1 drivers +S_0x23e1db0 .scope module, "ZeroMux" "FourInMux" 2 292, 2 24, S_0x2111ab0; + .timescale -9 -12; +L_0x2487bd0/d .functor NOT 1, L_0x2488dc0, C4<0>, C4<0>, C4<0>; +L_0x2487bd0 .delay (10000,10000,10000) L_0x2487bd0/d; +L_0x2487d20/d .functor NOT 1, L_0x2487f10, C4<0>, C4<0>, C4<0>; +L_0x2487d20 .delay (10000,10000,10000) L_0x2487d20/d; +L_0x2488740/d .functor NAND 1, L_0x2487bd0, L_0x2487d20, L_0x2488040, C4<1>; +L_0x2488740 .delay (10000,10000,10000) L_0x2488740/d; +L_0x2488880/d .functor NAND 1, L_0x2488dc0, L_0x2487d20, L_0x24880e0, C4<1>; +L_0x2488880 .delay (10000,10000,10000) L_0x2488880/d; +L_0x2488970/d .functor NAND 1, L_0x2487bd0, L_0x2487f10, L_0x2488180, C4<1>; +L_0x2488970 .delay (10000,10000,10000) L_0x2488970/d; +L_0x2488a60/d .functor NAND 1, L_0x2488dc0, L_0x2487f10, L_0x2488270, C4<1>; +L_0x2488a60 .delay (10000,10000,10000) L_0x2488a60/d; +L_0x2488b40/d .functor NAND 1, L_0x2488740, L_0x2488880, L_0x2488970, L_0x2488a60; +L_0x2488b40 .delay (10000,10000,10000) L_0x2488b40/d; +v0x23e2150_0 .net "S0", 0 0, L_0x2488dc0; 1 drivers +v0x23e1830_0 .net "S1", 0 0, L_0x2487f10; 1 drivers +v0x23e18d0_0 .net "in0", 0 0, L_0x2488040; 1 drivers +v0x2303f70_0 .net "in1", 0 0, L_0x24880e0; 1 drivers +v0x2304010_0 .net "in2", 0 0, L_0x2488180; 1 drivers +v0x2301ea0_0 .net "in3", 0 0, L_0x2488270; 1 drivers +v0x2301f40_0 .net "nS0", 0 0, L_0x2487bd0; 1 drivers +v0x22fe110_0 .net "nS1", 0 0, L_0x2487d20; 1 drivers +v0x22fe1b0_0 .net "out", 0 0, L_0x2488b40; 1 drivers +v0x22fc040_0 .net "out0", 0 0, L_0x2488740; 1 drivers +v0x22fc0e0_0 .net "out1", 0 0, L_0x2488880; 1 drivers +v0x22f82b0_0 .net "out2", 0 0, L_0x2488970; 1 drivers +v0x22e6850_0 .net "out3", 0 0, L_0x2488a60; 1 drivers +S_0x23e4410 .scope module, "OneMux" "FourInMux" 2 293, 2 24, S_0x2111ab0; + .timescale -9 -12; +L_0x2488360/d .functor NOT 1, L_0x2488ef0, C4<0>, C4<0>, C4<0>; +L_0x2488360 .delay (10000,10000,10000) L_0x2488360/d; +L_0x2488450/d .functor NOT 1, L_0x2489020, C4<0>, C4<0>, C4<0>; +L_0x2488450 .delay (10000,10000,10000) L_0x2488450/d; +L_0x2488510/d .functor NAND 1, L_0x2488360, L_0x2488450, L_0x2489150, C4<1>; +L_0x2488510 .delay (10000,10000,10000) L_0x2488510/d; +L_0x2488670/d .functor NAND 1, L_0x2488ef0, L_0x2488450, L_0x24891f0, C4<1>; +L_0x2488670 .delay (10000,10000,10000) L_0x2488670/d; +L_0x24897a0/d .functor NAND 1, L_0x2488360, L_0x2489020, L_0x2489290, C4<1>; +L_0x24897a0 .delay (10000,10000,10000) L_0x24897a0/d; +L_0x2489890/d .functor NAND 1, L_0x2488ef0, L_0x2489020, L_0x2489380, C4<1>; +L_0x2489890 .delay (10000,10000,10000) L_0x2489890/d; +L_0x2489970/d .functor NAND 1, L_0x2488510, L_0x2488670, L_0x24897a0, L_0x2489890; +L_0x2489970 .delay (10000,10000,10000) L_0x2489970/d; +v0x23e4750_0 .net "S0", 0 0, L_0x2488ef0; 1 drivers +v0x23e4170_0 .net "S1", 0 0, L_0x2489020; 1 drivers +v0x23e4210_0 .net "in0", 0 0, L_0x2489150; 1 drivers +v0x23e3e70_0 .net "in1", 0 0, L_0x24891f0; 1 drivers +v0x23e3f10_0 .net "in2", 0 0, L_0x2489290; 1 drivers +v0x23e38f0_0 .net "in3", 0 0, L_0x2489380; 1 drivers +v0x23e2890_0 .net "nS0", 0 0, L_0x2488360; 1 drivers +v0x23e2930_0 .net "nS1", 0 0, L_0x2488450; 1 drivers +v0x23e25f0_0 .net "out", 0 0, L_0x2489970; 1 drivers +v0x23e2690_0 .net "out0", 0 0, L_0x2488510; 1 drivers +v0x23e2350_0 .net "out1", 0 0, L_0x2488670; 1 drivers +v0x23e23f0_0 .net "out2", 0 0, L_0x24897a0; 1 drivers +v0x23e20b0_0 .net "out3", 0 0, L_0x2489890; 1 drivers +S_0x23e5b60 .scope module, "TwoMux" "TwoInMux" 2 294, 2 8, S_0x2111ab0; + .timescale -9 -12; +L_0x2489470/d .functor NOT 1, L_0x248a680, C4<0>, C4<0>, C4<0>; +L_0x2489470 .delay (10000,10000,10000) L_0x2489470/d; +L_0x2489560/d .functor AND 1, L_0x2489bf0, L_0x2489470, C4<1>, C4<1>; +L_0x2489560 .delay (20000,20000,20000) L_0x2489560/d; +L_0x2489650/d .functor AND 1, L_0x2489ce0, L_0x248a680, C4<1>, C4<1>; +L_0x2489650 .delay (20000,20000,20000) L_0x2489650/d; +L_0x248a4a0/d .functor OR 1, L_0x2489560, L_0x2489650, C4<0>, C4<0>; +L_0x248a4a0 .delay (20000,20000,20000) L_0x248a4a0/d; +v0x23e58c0_0 .net "S", 0 0, L_0x248a680; 1 drivers +v0x23e5960_0 .net "in0", 0 0, L_0x2489bf0; 1 drivers +v0x23e4950_0 .net "in1", 0 0, L_0x2489ce0; 1 drivers +v0x23e49f0_0 .net "nS", 0 0, L_0x2489470; 1 drivers +v0x225bcd0_0 .net "out0", 0 0, L_0x2489560; 1 drivers +v0x225bd70_0 .net "out1", 0 0, L_0x2489650; 1 drivers +v0x23e46b0_0 .net "outfinal", 0 0, L_0x248a4a0; 1 drivers +S_0x22fcde0 .scope generate, "muxbits[14]" "muxbits[14]" 2 290, 2 290, S_0x22690e0; + .timescale -9 -12; +P_0x22f4ab8 .param/l "i" 2 290, +C4<01110>; +L_0x248c710/d .functor OR 1, L_0x248c850, L_0x248c8f0, C4<0>, C4<0>; +L_0x248c710 .delay (20000,20000,20000) L_0x248c710/d; +v0x230b190_0 .net *"_s15", 0 0, L_0x248c850; 1 drivers +v0x230ae40_0 .net *"_s16", 0 0, L_0x248c8f0; 1 drivers +S_0x2306220 .scope module, "ZeroMux" "FourInMux" 2 292, 2 24, S_0x22fcde0; + .timescale -9 -12; +L_0x248a140/d .functor NOT 1, L_0x248a720, C4<0>, C4<0>, C4<0>; +L_0x248a140 .delay (10000,10000,10000) L_0x248a140/d; +L_0x248a250/d .functor NOT 1, L_0x248a850, C4<0>, C4<0>, C4<0>; +L_0x248a250 .delay (10000,10000,10000) L_0x248a250/d; +L_0x248a310/d .functor NAND 1, L_0x248a140, L_0x248a250, L_0x248a980, C4<1>; +L_0x248a310 .delay (10000,10000,10000) L_0x248a310/d; +L_0x248afb0/d .functor NAND 1, L_0x248a720, L_0x248a250, L_0x248aa20, C4<1>; +L_0x248afb0 .delay (10000,10000,10000) L_0x248afb0/d; +L_0x248b0a0/d .functor NAND 1, L_0x248a140, L_0x248a850, L_0x248aac0, C4<1>; +L_0x248b0a0 .delay (10000,10000,10000) L_0x248b0a0/d; +L_0x248b190/d .functor NAND 1, L_0x248a720, L_0x248a850, L_0x248abb0, C4<1>; +L_0x248b190 .delay (10000,10000,10000) L_0x248b190/d; +L_0x248b270/d .functor NAND 1, L_0x248a310, L_0x248afb0, L_0x248b0a0, L_0x248b190; +L_0x248b270 .delay (10000,10000,10000) L_0x248b270/d; +v0x2305290_0 .net "S0", 0 0, L_0x248a720; 1 drivers +v0x2304fe0_0 .net "S1", 0 0, L_0x248a850; 1 drivers +v0x2305080_0 .net "in0", 0 0, L_0x248a980; 1 drivers +v0x23026e0_0 .net "in1", 0 0, L_0x248aa20; 1 drivers +v0x2302760_0 .net "in2", 0 0, L_0x248aac0; 1 drivers +v0x2309000_0 .net "in3", 0 0, L_0x248abb0; 1 drivers +v0x23090a0_0 .net "nS0", 0 0, L_0x248a140; 1 drivers +v0x2308d50_0 .net "nS1", 0 0, L_0x248a250; 1 drivers +v0x2308df0_0 .net "out", 0 0, L_0x248b270; 1 drivers +v0x230c310_0 .net "out0", 0 0, L_0x248a310; 1 drivers +v0x230c390_0 .net "out1", 0 0, L_0x248afb0; 1 drivers +v0x230c060_0 .net "out2", 0 0, L_0x248b0a0; 1 drivers +v0x230b0f0_0 .net "out3", 0 0, L_0x248b190; 1 drivers +S_0x22fc880 .scope module, "OneMux" "FourInMux" 2 293, 2 24, S_0x22fcde0; + .timescale -9 -12; +L_0x248aca0/d .functor NOT 1, L_0x248c2c0, C4<0>, C4<0>, C4<0>; +L_0x248aca0 .delay (10000,10000,10000) L_0x248aca0/d; +L_0x248ad90/d .functor NOT 1, L_0x248b4f0, C4<0>, C4<0>, C4<0>; +L_0x248ad90 .delay (10000,10000,10000) L_0x248ad90/d; +L_0x248ae30/d .functor NAND 1, L_0x248aca0, L_0x248ad90, L_0x248b620, C4<1>; +L_0x248ae30 .delay (10000,10000,10000) L_0x248ae30/d; +L_0x248bdc0/d .functor NAND 1, L_0x248c2c0, L_0x248ad90, L_0x248b6c0, C4<1>; +L_0x248bdc0 .delay (10000,10000,10000) L_0x248bdc0/d; +L_0x248be70/d .functor NAND 1, L_0x248aca0, L_0x248b4f0, L_0x248b760, C4<1>; +L_0x248be70 .delay (10000,10000,10000) L_0x248be70/d; +L_0x248bf60/d .functor NAND 1, L_0x248c2c0, L_0x248b4f0, L_0x248b850, C4<1>; +L_0x248bf60 .delay (10000,10000,10000) L_0x248bf60/d; +L_0x248c040/d .functor NAND 1, L_0x248ae30, L_0x248bdc0, L_0x248be70, L_0x248bf60; +L_0x248c040 .delay (10000,10000,10000) L_0x248c040/d; +v0x2304d30_0 .net "S0", 0 0, L_0x248c2c0; 1 drivers +v0x2304dd0_0 .net "S1", 0 0, L_0x248b4f0; 1 drivers +v0x2304a80_0 .net "in0", 0 0, L_0x248b620; 1 drivers +v0x2304b20_0 .net "in1", 0 0, L_0x248b6c0; 1 drivers +v0x23047d0_0 .net "in2", 0 0, L_0x248b760; 1 drivers +v0x2304870_0 .net "in3", 0 0, L_0x248b850; 1 drivers +v0x2303200_0 .net "nS0", 0 0, L_0x248aca0; 1 drivers +v0x2302ef0_0 .net "nS1", 0 0, L_0x248ad90; 1 drivers +v0x2302f70_0 .net "out", 0 0, L_0x248c040; 1 drivers +v0x2302c40_0 .net "out0", 0 0, L_0x248ae30; 1 drivers +v0x2302ce0_0 .net "out1", 0 0, L_0x248bdc0; 1 drivers +v0x23029b0_0 .net "out2", 0 0, L_0x248be70; 1 drivers +v0x23064f0_0 .net "out3", 0 0, L_0x248bf60; 1 drivers +S_0x22fcb30 .scope module, "TwoMux" "TwoInMux" 2 294, 2 8, S_0x22fcde0; + .timescale -9 -12; +L_0x248b940/d .functor NOT 1, L_0x248c3f0, C4<0>, C4<0>, C4<0>; +L_0x248b940 .delay (10000,10000,10000) L_0x248b940/d; +L_0x248ba30/d .functor AND 1, L_0x248c490, L_0x248b940, C4<1>, C4<1>; +L_0x248ba30 .delay (20000,20000,20000) L_0x248ba30/d; +L_0x248bb20/d .functor AND 1, L_0x248c580, L_0x248c3f0, C4<1>, C4<1>; +L_0x248bb20 .delay (20000,20000,20000) L_0x248bb20/d; +L_0x248bc10/d .functor OR 1, L_0x248ba30, L_0x248bb20, C4<0>, C4<0>; +L_0x248bc10 .delay (20000,20000,20000) L_0x248bc10/d; +v0x2300670_0 .net "S", 0 0, L_0x248c3f0; 1 drivers +v0x2300710_0 .net "in0", 0 0, L_0x248c490; 1 drivers +v0x23003c0_0 .net "in1", 0 0, L_0x248c580; 1 drivers +v0x2300460_0 .net "nS", 0 0, L_0x248b940; 1 drivers +v0x22ff430_0 .net "out0", 0 0, L_0x248ba30; 1 drivers +v0x22ff4d0_0 .net "out1", 0 0, L_0x248bb20; 1 drivers +v0x22ff1e0_0 .net "outfinal", 0 0, L_0x248bc10; 1 drivers +S_0x22ed990 .scope generate, "muxbits[15]" "muxbits[15]" 2 290, 2 290, S_0x22690e0; + .timescale -9 -12; +P_0x22e1a68 .param/l "i" 2 290, +C4<01111>; +L_0x248eb90/d .functor OR 1, L_0x248ec90, L_0x248ed30, C4<0>, C4<0>; +L_0x248eb90 .delay (20000,20000,20000) L_0x248eb90/d; +v0x22fd3e0_0 .net *"_s15", 0 0, L_0x248ec90; 1 drivers +v0x22fd0b0_0 .net *"_s16", 0 0, L_0x248ed30; 1 drivers +S_0x22fa810 .scope module, "ZeroMux" "FourInMux" 2 292, 2 24, S_0x22ed990; + .timescale -9 -12; +L_0x248c9e0/d .functor NOT 1, L_0x248db70, C4<0>, C4<0>, C4<0>; +L_0x248c9e0 .delay (10000,10000,10000) L_0x248c9e0/d; +L_0x248cad0/d .functor NOT 1, L_0x248cd90, C4<0>, C4<0>, C4<0>; +L_0x248cad0 .delay (10000,10000,10000) L_0x248cad0/d; +L_0x248cb70/d .functor NAND 1, L_0x248c9e0, L_0x248cad0, L_0x248cec0, C4<1>; +L_0x248cb70 .delay (10000,10000,10000) L_0x248cb70/d; +L_0x248bd50/d .functor NAND 1, L_0x248db70, L_0x248cad0, L_0x248cf60, C4<1>; +L_0x248bd50 .delay (10000,10000,10000) L_0x248bd50/d; +L_0x248d720/d .functor NAND 1, L_0x248c9e0, L_0x248cd90, L_0x248d000, C4<1>; +L_0x248d720 .delay (10000,10000,10000) L_0x248d720/d; +L_0x248d810/d .functor NAND 1, L_0x248db70, L_0x248cd90, L_0x248d0f0, C4<1>; +L_0x248d810 .delay (10000,10000,10000) L_0x248d810/d; +L_0x248d8f0/d .functor NAND 1, L_0x248cb70, L_0x248bd50, L_0x248d720, L_0x248d810; +L_0x248d8f0 .delay (10000,10000,10000) L_0x248d8f0/d; +v0x22fa560_0 .net "S0", 0 0, L_0x248db70; 1 drivers +v0x22fa600_0 .net "S1", 0 0, L_0x248cd90; 1 drivers +v0x22f95d0_0 .net "in0", 0 0, L_0x248cec0; 1 drivers +v0x22f9670_0 .net "in1", 0 0, L_0x248cf60; 1 drivers +v0x22f9320_0 .net "in2", 0 0, L_0x248d000; 1 drivers +v0x22f93c0_0 .net "in3", 0 0, L_0x248d0f0; 1 drivers +v0x22f6a40_0 .net "nS0", 0 0, L_0x248c9e0; 1 drivers +v0x22feed0_0 .net "nS1", 0 0, L_0x248cad0; 1 drivers +v0x22fef70_0 .net "out", 0 0, L_0x248d8f0; 1 drivers +v0x22fec20_0 .net "out0", 0 0, L_0x248cb70; 1 drivers +v0x22fecc0_0 .net "out1", 0 0, L_0x248bd50; 1 drivers +v0x22fe970_0 .net "out2", 0 0, L_0x248d720; 1 drivers +v0x22fd340_0 .net "out3", 0 0, L_0x248d810; 1 drivers +S_0x22f3500 .scope module, "OneMux" "FourInMux" 2 293, 2 24, S_0x22ed990; + .timescale -9 -12; +L_0x248d1e0/d .functor NOT 1, L_0x248dca0, C4<0>, C4<0>, C4<0>; +L_0x248d1e0 .delay (10000,10000,10000) L_0x248d1e0/d; +L_0x248d290/d .functor NOT 1, L_0x248ddd0, C4<0>, C4<0>, C4<0>; +L_0x248d290 .delay (10000,10000,10000) L_0x248d290/d; +L_0x248d330/d .functor NAND 1, L_0x248d1e0, L_0x248d290, L_0x248df00, C4<1>; +L_0x248d330 .delay (10000,10000,10000) L_0x248d330/d; +L_0x248d470/d .functor NAND 1, L_0x248dca0, L_0x248d290, L_0x248dfa0, C4<1>; +L_0x248d470 .delay (10000,10000,10000) L_0x248d470/d; +L_0x248d560/d .functor NAND 1, L_0x248d1e0, L_0x248ddd0, L_0x248e040, C4<1>; +L_0x248d560 .delay (10000,10000,10000) L_0x248d560/d; +L_0x248d650/d .functor NAND 1, L_0x248dca0, L_0x248ddd0, L_0x248e130, C4<1>; +L_0x248d650 .delay (10000,10000,10000) L_0x248d650/d; +L_0x248e690/d .functor NAND 1, L_0x248d330, L_0x248d470, L_0x248d560, L_0x248d650; +L_0x248e690 .delay (10000,10000,10000) L_0x248e690/d; +v0x22f3850_0 .net "S0", 0 0, L_0x248dca0; 1 drivers +v0x22f9070_0 .net "S1", 0 0, L_0x248ddd0; 1 drivers +v0x22f90f0_0 .net "in0", 0 0, L_0x248df00; 1 drivers +v0x22f8dc0_0 .net "in1", 0 0, L_0x248dfa0; 1 drivers +v0x22f8e60_0 .net "in2", 0 0, L_0x248e040; 1 drivers +v0x22f8b10_0 .net "in3", 0 0, L_0x248e130; 1 drivers +v0x22f8bb0_0 .net "nS0", 0 0, L_0x248d1e0; 1 drivers +v0x22f7500_0 .net "nS1", 0 0, L_0x248d290; 1 drivers +v0x22f7230_0 .net "out", 0 0, L_0x248e690; 1 drivers +v0x22f72d0_0 .net "out0", 0 0, L_0x248d330; 1 drivers +v0x22f6f80_0 .net "out1", 0 0, L_0x248d470; 1 drivers +v0x22f7020_0 .net "out2", 0 0, L_0x248d560; 1 drivers +v0x22f6d60_0 .net "out3", 0 0, L_0x248d650; 1 drivers +S_0x22ed6e0 .scope module, "TwoMux" "TwoInMux" 2 294, 2 8, S_0x22ed990; + .timescale -9 -12; +L_0x22f7580/d .functor NOT 1, L_0x248f360, C4<0>, C4<0>, C4<0>; +L_0x22f7580 .delay (10000,10000,10000) L_0x22f7580/d; +L_0x248e2b0/d .functor AND 1, L_0x248e910, L_0x22f7580, C4<1>, C4<1>; +L_0x248e2b0 .delay (20000,20000,20000) L_0x248e2b0/d; +L_0x248e3a0/d .functor AND 1, L_0x248ea00, L_0x248f360, C4<1>, C4<1>; +L_0x248e3a0 .delay (20000,20000,20000) L_0x248e3a0/d; +L_0x248e490/d .functor OR 1, L_0x248e2b0, L_0x248e3a0, C4<0>, C4<0>; +L_0x248e490 .delay (20000,20000,20000) L_0x248e490/d; +v0x22f16c0_0 .net "S", 0 0, L_0x248f360; 1 drivers +v0x22f1760_0 .net "in0", 0 0, L_0x248e910; 1 drivers +v0x22f1410_0 .net "in1", 0 0, L_0x248ea00; 1 drivers +v0x22f14b0_0 .net "nS", 0 0, L_0x22f7580; 1 drivers +v0x22f49f0_0 .net "out0", 0 0, L_0x248e2b0; 1 drivers +v0x22f4720_0 .net "out1", 0 0, L_0x248e3a0; 1 drivers +v0x22f37b0_0 .net "outfinal", 0 0, L_0x248e490; 1 drivers +S_0x22e17b0 .scope generate, "muxbits[16]" "muxbits[16]" 2 290, 2 290, S_0x22690e0; + .timescale -9 -12; +P_0x22d0318 .param/l "i" 2 290, +C4<010000>; +L_0x247d420/d .functor OR 1, L_0x247e130, L_0x247e1d0, C4<0>, C4<0>; +L_0x247d420 .delay (20000,20000,20000) L_0x247d420/d; +v0x22eec50_0 .net *"_s15", 0 0, L_0x247e130; 1 drivers +v0x22ee900_0 .net *"_s16", 0 0, L_0x247e1d0; 1 drivers +S_0x22e5270 .scope module, "ZeroMux" "FourInMux" 2 292, 2 24, S_0x22e17b0; + .timescale -9 -12; +L_0x248ee20/d .functor NOT 1, L_0x248f400, C4<0>, C4<0>, C4<0>; +L_0x248ee20 .delay (10000,10000,10000) L_0x248ee20/d; +L_0x248ef10/d .functor NOT 1, L_0x248f530, C4<0>, C4<0>, C4<0>; +L_0x248ef10 .delay (10000,10000,10000) L_0x248ef10/d; +L_0x248efb0/d .functor NAND 1, L_0x248ee20, L_0x248ef10, L_0x248f660, C4<1>; +L_0x248efb0 .delay (10000,10000,10000) L_0x248efb0/d; +L_0x248f0f0/d .functor NAND 1, L_0x248f400, L_0x248ef10, L_0x248f700, C4<1>; +L_0x248f0f0 .delay (10000,10000,10000) L_0x248f0f0/d; +L_0x248f1e0/d .functor NAND 1, L_0x248ee20, L_0x248f530, L_0x248f7a0, C4<1>; +L_0x248f1e0 .delay (10000,10000,10000) L_0x248f1e0/d; +L_0x248fe30/d .functor NAND 1, L_0x248f400, L_0x248f530, L_0x248f890, C4<1>; +L_0x248fe30 .delay (10000,10000,10000) L_0x248fe30/d; +L_0x248fed0/d .functor NAND 1, L_0x248efb0, L_0x248f0f0, L_0x248f1e0, L_0x248fe30; +L_0x248fed0 .delay (10000,10000,10000) L_0x248fed0/d; +v0x22e8d90_0 .net "S0", 0 0, L_0x248f400; 1 drivers +v0x22e8ae0_0 .net "S1", 0 0, L_0x248f530; 1 drivers +v0x22e8b80_0 .net "in0", 0 0, L_0x248f660; 1 drivers +v0x22e7b70_0 .net "in1", 0 0, L_0x248f700; 1 drivers +v0x22e7bf0_0 .net "in2", 0 0, L_0x248f7a0; 1 drivers +v0x22e78c0_0 .net "in3", 0 0, L_0x248f890; 1 drivers +v0x22e7960_0 .net "nS0", 0 0, L_0x248ee20; 1 drivers +v0x22e4fc0_0 .net "nS1", 0 0, L_0x248ef10; 1 drivers +v0x22e5060_0 .net "out", 0 0, L_0x248fed0; 1 drivers +v0x22eb8a0_0 .net "out0", 0 0, L_0x248efb0; 1 drivers +v0x22eb920_0 .net "out1", 0 0, L_0x248f0f0; 1 drivers +v0x22eb5f0_0 .net "out2", 0 0, L_0x248f1e0; 1 drivers +v0x22eebb0_0 .net "out3", 0 0, L_0x248fe30; 1 drivers +S_0x22df410 .scope module, "OneMux" "FourInMux" 2 293, 2 24, S_0x22e17b0; + .timescale -9 -12; +L_0x248f980/d .functor NOT 1, L_0x2490f20, C4<0>, C4<0>, C4<0>; +L_0x248f980 .delay (10000,10000,10000) L_0x248f980/d; +L_0x248fa70/d .functor NOT 1, L_0x2490150, C4<0>, C4<0>, C4<0>; +L_0x248fa70 .delay (10000,10000,10000) L_0x248fa70/d; +L_0x248fb10/d .functor NAND 1, L_0x248f980, L_0x248fa70, L_0x2490280, C4<1>; +L_0x248fb10 .delay (10000,10000,10000) L_0x248fb10/d; +L_0x248fc50/d .functor NAND 1, L_0x2490f20, L_0x248fa70, L_0x247ca00, C4<1>; +L_0x248fc50 .delay (10000,10000,10000) L_0x248fc50/d; +L_0x248fd40/d .functor NAND 1, L_0x248f980, L_0x2490150, L_0x247caa0, C4<1>; +L_0x248fd40 .delay (10000,10000,10000) L_0x248fd40/d; +L_0x2490bc0/d .functor NAND 1, L_0x2490f20, L_0x2490150, L_0x2490730, C4<1>; +L_0x2490bc0 .delay (10000,10000,10000) L_0x2490bc0/d; +L_0x2490ca0/d .functor NAND 1, L_0x248fb10, L_0x248fc50, L_0x248fd40, L_0x2490bc0; +L_0x2490ca0 .delay (10000,10000,10000) L_0x2490ca0/d; +v0x22e2f50_0 .net "S0", 0 0, L_0x2490f20; 1 drivers +v0x22e2ff0_0 .net "S1", 0 0, L_0x2490150; 1 drivers +v0x22e2ca0_0 .net "in0", 0 0, L_0x2490280; 1 drivers +v0x22e2d40_0 .net "in1", 0 0, L_0x247ca00; 1 drivers +v0x22e1d10_0 .net "in2", 0 0, L_0x247caa0; 1 drivers +v0x22e1db0_0 .net "in3", 0 0, L_0x2490730; 1 drivers +v0x22e1ac0_0 .net "nS0", 0 0, L_0x248f980; 1 drivers +v0x22df160_0 .net "nS1", 0 0, L_0x248fa70; 1 drivers +v0x22df1e0_0 .net "out", 0 0, L_0x2490ca0; 1 drivers +v0x22e5a80_0 .net "out0", 0 0, L_0x248fb10; 1 drivers +v0x22e5b20_0 .net "out1", 0 0, L_0x248fc50; 1 drivers +v0x22e57f0_0 .net "out2", 0 0, L_0x248fd40; 1 drivers +v0x22e5540_0 .net "out3", 0 0, L_0x2490bc0; 1 drivers +S_0x22e1500 .scope module, "TwoMux" "TwoInMux" 2 294, 2 8, S_0x22e17b0; + .timescale -9 -12; +L_0x2490820/d .functor NOT 1, L_0x2491050, C4<0>, C4<0>, C4<0>; +L_0x2490820 .delay (10000,10000,10000) L_0x2490820/d; +L_0x24908d0/d .functor AND 1, L_0x24910f0, L_0x2490820, C4<1>, C4<1>; +L_0x24908d0 .delay (20000,20000,20000) L_0x24908d0/d; +L_0x24909c0/d .functor AND 1, L_0x247d330, L_0x2491050, C4<1>, C4<1>; +L_0x24909c0 .delay (20000,20000,20000) L_0x24909c0/d; +L_0x2490ab0/d .functor OR 1, L_0x24908d0, L_0x24909c0, C4<0>, C4<0>; +L_0x2490ab0 .delay (20000,20000,20000) L_0x2490ab0/d; +v0x22e1250_0 .net "S", 0 0, L_0x2491050; 1 drivers +v0x22e12f0_0 .net "in0", 0 0, L_0x24910f0; 1 drivers +v0x22dfc20_0 .net "in1", 0 0, L_0x247d330; 1 drivers +v0x22dfcc0_0 .net "nS", 0 0, L_0x2490820; 1 drivers +v0x22df970_0 .net "out0", 0 0, L_0x24908d0; 1 drivers +v0x22dfa10_0 .net "out1", 0 0, L_0x24909c0; 1 drivers +v0x22df720_0 .net "outfinal", 0 0, L_0x2490ab0; 1 drivers +S_0x22ce140 .scope generate, "muxbits[17]" "muxbits[17]" 2 290, 2 290, S_0x22690e0; + .timescale -9 -12; +P_0x22c2348 .param/l "i" 2 290, +C4<010001>; +L_0x24940b0/d .functor OR 1, L_0x24941f0, L_0x2494290, C4<0>, C4<0>; +L_0x24940b0 .delay (20000,20000,20000) L_0x24940b0/d; +v0x22dbca0_0 .net *"_s15", 0 0, L_0x24941f0; 1 drivers +v0x22d9320_0 .net *"_s16", 0 0, L_0x2494290; 1 drivers +S_0x22db3f0 .scope module, "ZeroMux" "FourInMux" 2 292, 2 24, S_0x22ce140; + .timescale -9 -12; +L_0x247e2c0/d .functor NOT 1, L_0x2491f40, C4<0>, C4<0>, C4<0>; +L_0x247e2c0 .delay (10000,10000,10000) L_0x247e2c0/d; +L_0x247dd30/d .functor NOT 1, L_0x2492070, C4<0>, C4<0>, C4<0>; +L_0x247dd30 .delay (10000,10000,10000) L_0x247dd30/d; +L_0x247ddd0/d .functor NAND 1, L_0x247e2c0, L_0x247dd30, L_0x24921a0, C4<1>; +L_0x247ddd0 .delay (10000,10000,10000) L_0x247ddd0/d; +L_0x247df10/d .functor NAND 1, L_0x2491f40, L_0x247dd30, L_0x2492240, C4<1>; +L_0x247df10 .delay (10000,10000,10000) L_0x247df10/d; +L_0x247e000/d .functor NAND 1, L_0x247e2c0, L_0x2492070, L_0x24922e0, C4<1>; +L_0x247e000 .delay (10000,10000,10000) L_0x247e000/d; +L_0x2491be0/d .functor NAND 1, L_0x2491f40, L_0x2492070, L_0x24923d0, C4<1>; +L_0x2491be0 .delay (10000,10000,10000) L_0x2491be0/d; +L_0x2491cc0/d .functor NAND 1, L_0x247ddd0, L_0x247df10, L_0x247e000, L_0x2491be0; +L_0x2491cc0 .delay (10000,10000,10000) L_0x2491cc0/d; +v0x22d9dc0_0 .net "S0", 0 0, L_0x2491f40; 1 drivers +v0x22d9e60_0 .net "S1", 0 0, L_0x2492070; 1 drivers +v0x22d9b10_0 .net "in0", 0 0, L_0x24921a0; 1 drivers +v0x22d9bb0_0 .net "in1", 0 0, L_0x2492240; 1 drivers +v0x22d9860_0 .net "in2", 0 0, L_0x24922e0; 1 drivers +v0x22d9900_0 .net "in3", 0 0, L_0x24923d0; 1 drivers +v0x22d95d0_0 .net "nS0", 0 0, L_0x247e2c0; 1 drivers +v0x22dd0f0_0 .net "nS1", 0 0, L_0x247dd30; 1 drivers +v0x22dd190_0 .net "out", 0 0, L_0x2491cc0; 1 drivers +v0x22dce40_0 .net "out0", 0 0, L_0x247ddd0; 1 drivers +v0x22dcee0_0 .net "out1", 0 0, L_0x247df10; 1 drivers +v0x22dbeb0_0 .net "out2", 0 0, L_0x247e000; 1 drivers +v0x22dbc00_0 .net "out3", 0 0, L_0x2491be0; 1 drivers +S_0x22d3f60 .scope module, "OneMux" "FourInMux" 2 293, 2 24, S_0x22ce140; + .timescale -9 -12; +L_0x24924c0/d .functor NOT 1, L_0x2492e30, C4<0>, C4<0>, C4<0>; +L_0x24924c0 .delay (10000,10000,10000) L_0x24924c0/d; +L_0x24925b0/d .functor NOT 1, L_0x2492f60, C4<0>, C4<0>, C4<0>; +L_0x24925b0 .delay (10000,10000,10000) L_0x24925b0/d; +L_0x2493930/d .functor NAND 1, L_0x24924c0, L_0x24925b0, L_0x2493090, C4<1>; +L_0x2493930 .delay (10000,10000,10000) L_0x2493930/d; +L_0x2493a70/d .functor NAND 1, L_0x2492e30, L_0x24925b0, L_0x2493130, C4<1>; +L_0x2493a70 .delay (10000,10000,10000) L_0x2493a70/d; +L_0x2493b60/d .functor NAND 1, L_0x24924c0, L_0x2492f60, L_0x24931d0, C4<1>; +L_0x2493b60 .delay (10000,10000,10000) L_0x2493b60/d; +L_0x2493c50/d .functor NAND 1, L_0x2492e30, L_0x2492f60, L_0x24932c0, C4<1>; +L_0x2493c50 .delay (10000,10000,10000) L_0x2493c50/d; +L_0x2493d60/d .functor NAND 1, L_0x2493930, L_0x2493a70, L_0x2493b60, L_0x2493c50; +L_0x2493d60 .delay (10000,10000,10000) L_0x2493d60/d; +v0x22d5b90_0 .net "S0", 0 0, L_0x2492e30; 1 drivers +v0x22d3cb0_0 .net "S1", 0 0, L_0x2492f60; 1 drivers +v0x22d3d30_0 .net "in0", 0 0, L_0x2493090; 1 drivers +v0x22d7290_0 .net "in1", 0 0, L_0x2493130; 1 drivers +v0x22d7330_0 .net "in2", 0 0, L_0x24931d0; 1 drivers +v0x22d6fe0_0 .net "in3", 0 0, L_0x24932c0; 1 drivers +v0x22d7080_0 .net "nS0", 0 0, L_0x24924c0; 1 drivers +v0x22d6070_0 .net "nS1", 0 0, L_0x24925b0; 1 drivers +v0x22d5da0_0 .net "out", 0 0, L_0x2493d60; 1 drivers +v0x22d5e40_0 .net "out0", 0 0, L_0x2493930; 1 drivers +v0x22db950_0 .net "out1", 0 0, L_0x2493a70; 1 drivers +v0x22db9f0_0 .net "out2", 0 0, L_0x2493b60; 1 drivers +v0x22db730_0 .net "out3", 0 0, L_0x2493c50; 1 drivers +S_0x22cde90 .scope module, "TwoMux" "TwoInMux" 2 294, 2 8, S_0x22ce140; + .timescale -9 -12; +L_0x22d60f0/d .functor NOT 1, L_0x2493800, C4<0>, C4<0>, C4<0>; +L_0x22d60f0 .delay (10000,10000,10000) L_0x22d60f0/d; +L_0x2493440/d .functor AND 1, L_0x2494b20, L_0x22d60f0, C4<1>, C4<1>; +L_0x2493440 .delay (20000,20000,20000) L_0x2493440/d; +L_0x2493530/d .functor AND 1, L_0x2494bc0, L_0x2493800, C4<1>, C4<1>; +L_0x2493530 .delay (20000,20000,20000) L_0x2493530/d; +L_0x2493620/d .functor OR 1, L_0x2493440, L_0x2493530, C4<0>, C4<0>; +L_0x2493620 .delay (20000,20000,20000) L_0x2493620/d; +v0x22d1450_0 .net "S", 0 0, L_0x2493800; 1 drivers +v0x22d14f0_0 .net "in0", 0 0, L_0x2494b20; 1 drivers +v0x22d11a0_0 .net "in1", 0 0, L_0x2494bc0; 1 drivers +v0x22d1240_0 .net "nS", 0 0, L_0x22d60f0; 1 drivers +v0x22d0250_0 .net "out0", 0 0, L_0x2493440; 1 drivers +v0x22cff80_0 .net "out1", 0 0, L_0x2493530; 1 drivers +v0x22d5af0_0 .net "outfinal", 0 0, L_0x2493620; 1 drivers +S_0x22bfbb0 .scope generate, "muxbits[18]" "muxbits[18]" 2 290, 2 290, S_0x22690e0; + .timescale -9 -12; +P_0x22b2fc8 .param/l "i" 2 290, +C4<010010>; +L_0x24968a0/d .functor OR 1, L_0x24969e0, L_0x2496a80, C4<0>, C4<0>; +L_0x24968a0 .delay (20000,20000,20000) L_0x24968a0/d; +v0x22ca4b0_0 .net *"_s15", 0 0, L_0x24969e0; 1 drivers +v0x22ca160_0 .net *"_s16", 0 0, L_0x2496a80; 1 drivers +S_0x22c52b0 .scope module, "ZeroMux" "FourInMux" 2 292, 2 24, S_0x22bfbb0; + .timescale -9 -12; +L_0x2494380/d .functor NOT 1, L_0x2494cb0, C4<0>, C4<0>, C4<0>; +L_0x2494380 .delay (10000,10000,10000) L_0x2494380/d; +L_0x2494470/d .functor NOT 1, L_0x2494de0, C4<0>, C4<0>, C4<0>; +L_0x2494470 .delay (10000,10000,10000) L_0x2494470/d; +L_0x2494510/d .functor NAND 1, L_0x2494380, L_0x2494470, L_0x2494f10, C4<1>; +L_0x2494510 .delay (10000,10000,10000) L_0x2494510/d; +L_0x2494650/d .functor NAND 1, L_0x2494cb0, L_0x2494470, L_0x2494fb0, C4<1>; +L_0x2494650 .delay (10000,10000,10000) L_0x2494650/d; +L_0x2494740/d .functor NAND 1, L_0x2494380, L_0x2494de0, L_0x2495050, C4<1>; +L_0x2494740 .delay (10000,10000,10000) L_0x2494740/d; +L_0x2494830/d .functor NAND 1, L_0x2494cb0, L_0x2494de0, L_0x2495140, C4<1>; +L_0x2494830 .delay (10000,10000,10000) L_0x2494830/d; +L_0x2494970/d .functor NAND 1, L_0x2494510, L_0x2494650, L_0x2494740, L_0x2494830; +L_0x2494970 .delay (10000,10000,10000) L_0x2494970/d; +v0x22c4610_0 .net "S0", 0 0, L_0x2494cb0; 1 drivers +v0x22c4380_0 .net "S1", 0 0, L_0x2494de0; 1 drivers +v0x22c4420_0 .net "in0", 0 0, L_0x2494f10; 1 drivers +v0x22c18a0_0 .net "in1", 0 0, L_0x2494fb0; 1 drivers +v0x22c1920_0 .net "in2", 0 0, L_0x2495050; 1 drivers +v0x22c8320_0 .net "in3", 0 0, L_0x2495140; 1 drivers +v0x22c83c0_0 .net "nS0", 0 0, L_0x2494380; 1 drivers +v0x22c8070_0 .net "nS1", 0 0, L_0x2494470; 1 drivers +v0x22c8110_0 .net "out", 0 0, L_0x2494970; 1 drivers +v0x22cb630_0 .net "out0", 0 0, L_0x2494510; 1 drivers +v0x22cb6b0_0 .net "out1", 0 0, L_0x2494650; 1 drivers +v0x22cb380_0 .net "out2", 0 0, L_0x2494740; 1 drivers +v0x22ca410_0 .net "out3", 0 0, L_0x2494830; 1 drivers +S_0x22c40f0 .scope module, "OneMux" "FourInMux" 2 293, 2 24, S_0x22bfbb0; + .timescale -9 -12; +L_0x2495230/d .functor NOT 1, L_0x2496770, C4<0>, C4<0>, C4<0>; +L_0x2495230 .delay (10000,10000,10000) L_0x2495230/d; +L_0x2495320/d .functor NOT 1, L_0x2495910, C4<0>, C4<0>, C4<0>; +L_0x2495320 .delay (10000,10000,10000) L_0x2495320/d; +L_0x24953c0/d .functor NAND 1, L_0x2495230, L_0x2495320, L_0x2495a40, C4<1>; +L_0x24953c0 .delay (10000,10000,10000) L_0x24953c0/d; +L_0x2495500/d .functor NAND 1, L_0x2496770, L_0x2495320, L_0x2495ae0, C4<1>; +L_0x2495500 .delay (10000,10000,10000) L_0x2495500/d; +L_0x24955f0/d .functor NAND 1, L_0x2495230, L_0x2495910, L_0x2495b80, C4<1>; +L_0x24955f0 .delay (10000,10000,10000) L_0x24955f0/d; +L_0x24956e0/d .functor NAND 1, L_0x2496770, L_0x2495910, L_0x2495c70, C4<1>; +L_0x24956e0 .delay (10000,10000,10000) L_0x24956e0/d; +L_0x24964c0/d .functor NAND 1, L_0x24953c0, L_0x2495500, L_0x24955f0, L_0x24956e0; +L_0x24964c0 .delay (10000,10000,10000) L_0x24964c0/d; +v0x22c3e60_0 .net "S0", 0 0, L_0x2496770; 1 drivers +v0x22c3f00_0 .net "S1", 0 0, L_0x2495910; 1 drivers +v0x22c38e0_0 .net "in0", 0 0, L_0x2495a40; 1 drivers +v0x22c3980_0 .net "in1", 0 0, L_0x2495ae0; 1 drivers +v0x22c25d0_0 .net "in2", 0 0, L_0x2495b80; 1 drivers +v0x22c2670_0 .net "in3", 0 0, L_0x2495c70; 1 drivers +v0x22c23a0_0 .net "nS0", 0 0, L_0x2495230; 1 drivers +v0x22c20b0_0 .net "nS1", 0 0, L_0x2495320; 1 drivers +v0x22c2130_0 .net "out", 0 0, L_0x24964c0; 1 drivers +v0x22c1e20_0 .net "out0", 0 0, L_0x24953c0; 1 drivers +v0x22c1ec0_0 .net "out1", 0 0, L_0x2495500; 1 drivers +v0x22c5820_0 .net "out2", 0 0, L_0x24955f0; 1 drivers +v0x22c5590_0 .net "out3", 0 0, L_0x24956e0; 1 drivers +S_0x22bf920 .scope module, "TwoMux" "TwoInMux" 2 294, 2 8, S_0x22bfbb0; + .timescale -9 -12; +L_0x2495d60/d .functor NOT 1, L_0x24961d0, C4<0>, C4<0>, C4<0>; +L_0x2495d60 .delay (10000,10000,10000) L_0x2495d60/d; +L_0x2495e10/d .functor AND 1, L_0x2496270, L_0x2495d60, C4<1>, C4<1>; +L_0x2495e10 .delay (20000,20000,20000) L_0x2495e10/d; +L_0x2495f00/d .functor AND 1, L_0x2496360, L_0x24961d0, C4<1>, C4<1>; +L_0x2495f00 .delay (20000,20000,20000) L_0x2495f00/d; +L_0x2495ff0/d .functor OR 1, L_0x2495e10, L_0x2495f00, C4<0>, C4<0>; +L_0x2495ff0 .delay (20000,20000,20000) L_0x2495ff0/d; +v0x22bf660_0 .net "S", 0 0, L_0x24961d0; 1 drivers +v0x22bf700_0 .net "in0", 0 0, L_0x2496270; 1 drivers +v0x22be9c0_0 .net "in1", 0 0, L_0x2496360; 1 drivers +v0x22bea60_0 .net "nS", 0 0, L_0x2495d60; 1 drivers +v0x22be730_0 .net "out0", 0 0, L_0x2495e10; 1 drivers +v0x22be7d0_0 .net "out1", 0 0, L_0x2495f00; 1 drivers +v0x22bbcb0_0 .net "outfinal", 0 0, L_0x2495ff0; 1 drivers +S_0x22b0ef0 .scope generate, "muxbits[19]" "muxbits[19]" 2 290, 2 290, S_0x22690e0; + .timescale -9 -12; +P_0x22a1c18 .param/l "i" 2 290, +C4<010011>; +L_0x2499c20/d .functor OR 1, L_0x2499d60, L_0x2498f10, C4<0>, C4<0>; +L_0x2499c20 .delay (20000,20000,20000) L_0x2499c20/d; +v0x22bc500_0 .net *"_s15", 0 0, L_0x2499d60; 1 drivers +v0x22bc1f0_0 .net *"_s16", 0 0, L_0x2498f10; 1 drivers +S_0x22b8d70 .scope module, "ZeroMux" "FourInMux" 2 292, 2 24, S_0x22b0ef0; + .timescale -9 -12; +L_0x2496b70/d .functor NOT 1, L_0x24980e0, C4<0>, C4<0>, C4<0>; +L_0x2496b70 .delay (10000,10000,10000) L_0x2496b70/d; +L_0x2496c60/d .functor NOT 1, L_0x2497500, C4<0>, C4<0>, C4<0>; +L_0x2496c60 .delay (10000,10000,10000) L_0x2496c60/d; +L_0x2496d00/d .functor NAND 1, L_0x2496b70, L_0x2496c60, L_0x2497630, C4<1>; +L_0x2496d00 .delay (10000,10000,10000) L_0x2496d00/d; +L_0x2496e40/d .functor NAND 1, L_0x24980e0, L_0x2496c60, L_0x24976d0, C4<1>; +L_0x2496e40 .delay (10000,10000,10000) L_0x2496e40/d; +L_0x2496f30/d .functor NAND 1, L_0x2496b70, L_0x2497500, L_0x2497770, C4<1>; +L_0x2496f30 .delay (10000,10000,10000) L_0x2496f30/d; +L_0x2497020/d .functor NAND 1, L_0x24980e0, L_0x2497500, L_0x2497860, C4<1>; +L_0x2497020 .delay (10000,10000,10000) L_0x2497020/d; +L_0x2497130/d .functor NAND 1, L_0x2496d00, L_0x2496e40, L_0x2496f30, L_0x2497020; +L_0x2497130 .delay (10000,10000,10000) L_0x2497130/d; +v0x22b8ae0_0 .net "S0", 0 0, L_0x24980e0; 1 drivers +v0x22b8b80_0 .net "S1", 0 0, L_0x2497500; 1 drivers +v0x22b6000_0 .net "in0", 0 0, L_0x2497630; 1 drivers +v0x22b60a0_0 .net "in1", 0 0, L_0x24976d0; 1 drivers +v0x22be4a0_0 .net "in2", 0 0, L_0x2497770; 1 drivers +v0x22be540_0 .net "in3", 0 0, L_0x2497860; 1 drivers +v0x22be230_0 .net "nS0", 0 0, L_0x2496b70; 1 drivers +v0x22bdc90_0 .net "nS1", 0 0, L_0x2496c60; 1 drivers +v0x22bdd30_0 .net "out", 0 0, L_0x2497130; 1 drivers +v0x22bc980_0 .net "out0", 0 0, L_0x2496d00; 1 drivers +v0x22bca20_0 .net "out1", 0 0, L_0x2496e40; 1 drivers +v0x22bc6f0_0 .net "out2", 0 0, L_0x2496f30; 1 drivers +v0x22bc460_0 .net "out3", 0 0, L_0x2497020; 1 drivers +S_0x22b8040 .scope module, "OneMux" "FourInMux" 2 293, 2 24, S_0x22b0ef0; + .timescale -9 -12; +L_0x2497950/d .functor NOT 1, L_0x2498210, C4<0>, C4<0>, C4<0>; +L_0x2497950 .delay (10000,10000,10000) L_0x2497950/d; +L_0x2497a00/d .functor NOT 1, L_0x2498340, C4<0>, C4<0>, C4<0>; +L_0x2497a00 .delay (10000,10000,10000) L_0x2497a00/d; +L_0x2497aa0/d .functor NAND 1, L_0x2497950, L_0x2497a00, L_0x2498470, C4<1>; +L_0x2497aa0 .delay (10000,10000,10000) L_0x2497aa0/d; +L_0x2497be0/d .functor NAND 1, L_0x2498210, L_0x2497a00, L_0x2498510, C4<1>; +L_0x2497be0 .delay (10000,10000,10000) L_0x2497be0/d; +L_0x2497cd0/d .functor NAND 1, L_0x2497950, L_0x2498340, L_0x24985b0, C4<1>; +L_0x2497cd0 .delay (10000,10000,10000) L_0x2497cd0/d; +L_0x2497df0/d .functor NAND 1, L_0x2498210, L_0x2498340, L_0x24986a0, C4<1>; +L_0x2497df0 .delay (10000,10000,10000) L_0x2497df0/d; +L_0x2497f60/d .functor NAND 1, L_0x2497aa0, L_0x2497be0, L_0x2497cd0, L_0x2497df0; +L_0x2497f60 .delay (10000,10000,10000) L_0x2497f60/d; +v0x22b8660_0 .net "S0", 0 0, L_0x2498210; 1 drivers +v0x22b6d30_0 .net "S1", 0 0, L_0x2498340; 1 drivers +v0x22b6db0_0 .net "in0", 0 0, L_0x2498470; 1 drivers +v0x22b6aa0_0 .net "in1", 0 0, L_0x2498510; 1 drivers +v0x22b6b40_0 .net "in2", 0 0, L_0x24985b0; 1 drivers +v0x22b6810_0 .net "in3", 0 0, L_0x24986a0; 1 drivers +v0x22b68b0_0 .net "nS0", 0 0, L_0x2497950; 1 drivers +v0x22b65a0_0 .net "nS1", 0 0, L_0x2497a00; 1 drivers +v0x22b9f60_0 .net "out", 0 0, L_0x2497f60; 1 drivers +v0x22ba000_0 .net "out0", 0 0, L_0x2497aa0; 1 drivers +v0x22b9cd0_0 .net "out1", 0 0, L_0x2497be0; 1 drivers +v0x22b9d70_0 .net "out2", 0 0, L_0x2497cd0; 1 drivers +v0x22b9aa0_0 .net "out3", 0 0, L_0x2497df0; 1 drivers +S_0x22b4310 .scope module, "TwoMux" "TwoInMux" 2 294, 2 8, S_0x22b0ef0; + .timescale -9 -12; +L_0x22b6620/d .functor NOT 1, L_0x2498ba0, C4<0>, C4<0>, C4<0>; +L_0x22b6620 .delay (10000,10000,10000) L_0x22b6620/d; +L_0x24987e0/d .functor AND 1, L_0x2498c40, L_0x22b6620, C4<1>, C4<1>; +L_0x24987e0 .delay (20000,20000,20000) L_0x24987e0/d; +L_0x24988d0/d .functor AND 1, L_0x2498d30, L_0x2498ba0, C4<1>, C4<1>; +L_0x24988d0 .delay (20000,20000,20000) L_0x24988d0/d; +L_0x24989c0/d .functor OR 1, L_0x24987e0, L_0x24988d0, C4<0>, C4<0>; +L_0x24989c0 .delay (20000,20000,20000) L_0x24989c0/d; +v0x22b4080_0 .net "S", 0 0, L_0x2498ba0; 1 drivers +v0x22b4120_0 .net "in0", 0 0, L_0x2498c40; 1 drivers +v0x22b3170_0 .net "in1", 0 0, L_0x2498d30; 1 drivers +v0x22b3210_0 .net "nS", 0 0, L_0x22b6620; 1 drivers +v0x22b2f00_0 .net "out0", 0 0, L_0x24987e0; 1 drivers +v0x22b8850_0 .net "out1", 0 0, L_0x24988d0; 1 drivers +v0x22b85c0_0 .net "outfinal", 0 0, L_0x24989c0; 1 drivers +S_0x22a16f0 .scope generate, "muxbits[20]" "muxbits[20]" 2 290, 2 290, S_0x22690e0; + .timescale -9 -12; +P_0x22946a8 .param/l "i" 2 290, +C4<010100>; +L_0x249b5f0/d .functor OR 1, L_0x249b730, L_0x249b7d0, C4<0>, C4<0>; +L_0x249b5f0 .delay (20000,20000,20000) L_0x249b5f0/d; +v0x22ad420_0 .net *"_s15", 0 0, L_0x249b730; 1 drivers +v0x22b1180_0 .net *"_s16", 0 0, L_0x249b7d0; 1 drivers +S_0x22a89c0 .scope module, "ZeroMux" "FourInMux" 2 292, 2 24, S_0x22a16f0; + .timescale -9 -12; +L_0x2499000/d .functor NOT 1, L_0x24998a0, C4<0>, C4<0>, C4<0>; +L_0x2499000 .delay (10000,10000,10000) L_0x2499000/d; +L_0x24990f0/d .functor NOT 1, L_0x24999d0, C4<0>, C4<0>, C4<0>; +L_0x24990f0 .delay (10000,10000,10000) L_0x24990f0/d; +L_0x2499190/d .functor NAND 1, L_0x2499000, L_0x24990f0, L_0x249aaa0, C4<1>; +L_0x2499190 .delay (10000,10000,10000) L_0x2499190/d; +L_0x24992d0/d .functor NAND 1, L_0x24998a0, L_0x24990f0, L_0x249ab40, C4<1>; +L_0x24992d0 .delay (10000,10000,10000) L_0x24992d0/d; +L_0x24993c0/d .functor NAND 1, L_0x2499000, L_0x24999d0, L_0x2499e00, C4<1>; +L_0x24993c0 .delay (10000,10000,10000) L_0x24993c0/d; +L_0x24994b0/d .functor NAND 1, L_0x24998a0, L_0x24999d0, L_0x2499ef0, C4<1>; +L_0x24994b0 .delay (10000,10000,10000) L_0x24994b0/d; +L_0x24995f0/d .functor NAND 1, L_0x2499190, L_0x24992d0, L_0x24993c0, L_0x24994b0; +L_0x24995f0 .delay (10000,10000,10000) L_0x24995f0/d; +v0x22a7ab0_0 .net "S0", 0 0, L_0x24998a0; 1 drivers +v0x22a7820_0 .net "S1", 0 0, L_0x24999d0; 1 drivers +v0x22a78c0_0 .net "in0", 0 0, L_0x249aaa0; 1 drivers +v0x22ab620_0 .net "in1", 0 0, L_0x249ab40; 1 drivers +v0x22ab6a0_0 .net "in2", 0 0, L_0x2499e00; 1 drivers +v0x22ab390_0 .net "in3", 0 0, L_0x2499ef0; 1 drivers +v0x22ab430_0 .net "nS0", 0 0, L_0x2499000; 1 drivers +v0x22ae7b0_0 .net "nS1", 0 0, L_0x24990f0; 1 drivers +v0x22ae850_0 .net "out", 0 0, L_0x24995f0; 1 drivers +v0x22ae520_0 .net "out0", 0 0, L_0x2499190; 1 drivers +v0x22ae5a0_0 .net "out1", 0 0, L_0x24992d0; 1 drivers +v0x22ad610_0 .net "out2", 0 0, L_0x24993c0; 1 drivers +v0x22ad380_0 .net "out3", 0 0, L_0x24994b0; 1 drivers +S_0x22a3090 .scope module, "OneMux" "FourInMux" 2 293, 2 24, S_0x22a16f0; + .timescale -9 -12; +L_0x2499fe0/d .functor NOT 1, L_0x249a8b0, C4<0>, C4<0>, C4<0>; +L_0x2499fe0 .delay (10000,10000,10000) L_0x2499fe0/d; +L_0x249a0d0/d .functor NOT 1, L_0x249a9e0, C4<0>, C4<0>, C4<0>; +L_0x249a0d0 .delay (10000,10000,10000) L_0x249a0d0/d; +L_0x249a170/d .functor NAND 1, L_0x2499fe0, L_0x249a0d0, L_0x249b940, C4<1>; +L_0x249a170 .delay (10000,10000,10000) L_0x249a170/d; +L_0x249a2b0/d .functor NAND 1, L_0x249a8b0, L_0x249a0d0, L_0x249abe0, C4<1>; +L_0x249a2b0 .delay (10000,10000,10000) L_0x249a2b0/d; +L_0x249a3a0/d .functor NAND 1, L_0x2499fe0, L_0x249a9e0, L_0x249ac80, C4<1>; +L_0x249a3a0 .delay (10000,10000,10000) L_0x249a3a0/d; +L_0x249a490/d .functor NAND 1, L_0x249a8b0, L_0x249a9e0, L_0x249ad70, C4<1>; +L_0x249a490 .delay (10000,10000,10000) L_0x249a490/d; +L_0x249a600/d .functor NAND 1, L_0x249a170, L_0x249a2b0, L_0x249a3a0, L_0x249a490; +L_0x249a600 .delay (10000,10000,10000) L_0x249a600/d; +v0x22a2e00_0 .net "S0", 0 0, L_0x249a8b0; 1 drivers +v0x22a2ea0_0 .net "S1", 0 0, L_0x249a9e0; 1 drivers +v0x22a2b40_0 .net "in0", 0 0, L_0x249b940; 1 drivers +v0x22a2be0_0 .net "in1", 0 0, L_0x249abe0; 1 drivers +v0x22a1ea0_0 .net "in2", 0 0, L_0x249ac80; 1 drivers +v0x22a1f40_0 .net "in3", 0 0, L_0x249ad70; 1 drivers +v0x22a1c70_0 .net "nS0", 0 0, L_0x2499fe0; 1 drivers +v0x229f130_0 .net "nS1", 0 0, L_0x249a0d0; 1 drivers +v0x229f1b0_0 .net "out", 0 0, L_0x249a600; 1 drivers +v0x22a5ac0_0 .net "out0", 0 0, L_0x249a170; 1 drivers +v0x22a5b60_0 .net "out1", 0 0, L_0x249a2b0; 1 drivers +v0x22a5850_0 .net "out2", 0 0, L_0x249a3a0; 1 drivers +v0x22a8c70_0 .net "out3", 0 0, L_0x249a490; 1 drivers +S_0x22a1170 .scope module, "TwoMux" "TwoInMux" 2 294, 2 8, S_0x22a16f0; + .timescale -9 -12; +L_0x249ae60/d .functor NOT 1, L_0x249b2d0, C4<0>, C4<0>, C4<0>; +L_0x249ae60 .delay (10000,10000,10000) L_0x249ae60/d; +L_0x249af10/d .functor AND 1, L_0x249b370, L_0x249ae60, C4<1>, C4<1>; +L_0x249af10 .delay (20000,20000,20000) L_0x249af10/d; +L_0x249b000/d .functor AND 1, L_0x249b460, L_0x249b2d0, C4<1>, C4<1>; +L_0x249b000 .delay (20000,20000,20000) L_0x249b000/d; +L_0x249b0f0/d .functor OR 1, L_0x249af10, L_0x249b000, C4<0>, C4<0>; +L_0x249b0f0 .delay (20000,20000,20000) L_0x249b0f0/d; +v0x229fe60_0 .net "S", 0 0, L_0x249b2d0; 1 drivers +v0x229ff00_0 .net "in0", 0 0, L_0x249b370; 1 drivers +v0x229fbd0_0 .net "in1", 0 0, L_0x249b460; 1 drivers +v0x229fc70_0 .net "nS", 0 0, L_0x249ae60; 1 drivers +v0x229f940_0 .net "out0", 0 0, L_0x249af10; 1 drivers +v0x229f9e0_0 .net "out1", 0 0, L_0x249b000; 1 drivers +v0x229f710_0 .net "outfinal", 0 0, L_0x249b0f0; 1 drivers +S_0x22907c0 .scope generate, "muxbits[21]" "muxbits[21]" 2 290, 2 290, S_0x22690e0; + .timescale -9 -12; +P_0x22862a8 .param/l "i" 2 290, +C4<010101>; +L_0x249d940/d .functor OR 1, L_0x249da80, L_0x249db20, C4<0>, C4<0>; +L_0x249d940 .delay (20000,20000,20000) L_0x249d940/d; +v0x2299580_0 .net *"_s15", 0 0, L_0x249da80; 1 drivers +v0x22a19a0_0 .net *"_s16", 0 0, L_0x249db20; 1 drivers +S_0x2299f80 .scope module, "ZeroMux" "FourInMux" 2 292, 2 24, S_0x22907c0; + .timescale -9 -12; +L_0x249c710/d .functor NOT 1, L_0x249cf70, C4<0>, C4<0>, C4<0>; +L_0x249c710 .delay (10000,10000,10000) L_0x249c710/d; +L_0x249c7c0/d .functor NOT 1, L_0x249b9e0, C4<0>, C4<0>, C4<0>; +L_0x249c7c0 .delay (10000,10000,10000) L_0x249c7c0/d; +L_0x249c860/d .functor NAND 1, L_0x249c710, L_0x249c7c0, L_0x249bb10, C4<1>; +L_0x249c860 .delay (10000,10000,10000) L_0x249c860/d; +L_0x249c9a0/d .functor NAND 1, L_0x249cf70, L_0x249c7c0, L_0x249bbb0, C4<1>; +L_0x249c9a0 .delay (10000,10000,10000) L_0x249c9a0/d; +L_0x249ca90/d .functor NAND 1, L_0x249c710, L_0x249b9e0, L_0x249bc50, C4<1>; +L_0x249ca90 .delay (10000,10000,10000) L_0x249ca90/d; +L_0x249cb80/d .functor NAND 1, L_0x249cf70, L_0x249b9e0, L_0x249bd40, C4<1>; +L_0x249cb80 .delay (10000,10000,10000) L_0x249cb80/d; +L_0x249ccc0/d .functor NAND 1, L_0x249c860, L_0x249c9a0, L_0x249ca90, L_0x249cb80; +L_0x249ccc0 .delay (10000,10000,10000) L_0x249ccc0/d; +v0x2299cf0_0 .net "S0", 0 0, L_0x249cf70; 1 drivers +v0x2299d90_0 .net "S1", 0 0, L_0x249b9e0; 1 drivers +v0x2299a60_0 .net "in0", 0 0, L_0x249bb10; 1 drivers +v0x2299b00_0 .net "in1", 0 0, L_0x249bbb0; 1 drivers +v0x229d440_0 .net "in2", 0 0, L_0x249bc50; 1 drivers +v0x229d4e0_0 .net "in3", 0 0, L_0x249bd40; 1 drivers +v0x229d1d0_0 .net "nS0", 0 0, L_0x249c710; 1 drivers +v0x229cef0_0 .net "nS1", 0 0, L_0x249c7c0; 1 drivers +v0x229cf90_0 .net "out", 0 0, L_0x249ccc0; 1 drivers +v0x229c250_0 .net "out0", 0 0, L_0x249c860; 1 drivers +v0x229c2f0_0 .net "out1", 0 0, L_0x249c9a0; 1 drivers +v0x229bfc0_0 .net "out2", 0 0, L_0x249ca90; 1 drivers +v0x22994e0_0 .net "out3", 0 0, L_0x249cb80; 1 drivers +S_0x2297560 .scope module, "OneMux" "FourInMux" 2 293, 2 24, S_0x22907c0; + .timescale -9 -12; +L_0x249cbe0/d .functor NOT 1, L_0x249d0a0, C4<0>, C4<0>, C4<0>; +L_0x249cbe0 .delay (10000,10000,10000) L_0x249cbe0/d; +L_0x249c690/d .functor NOT 1, L_0x249d1d0, C4<0>, C4<0>, C4<0>; +L_0x249c690 .delay (10000,10000,10000) L_0x249c690/d; +L_0x2482f70/d .functor NAND 1, L_0x249cbe0, L_0x249c690, L_0x249d300, C4<1>; +L_0x2482f70 .delay (10000,10000,10000) L_0x2482f70/d; +L_0x24830b0/d .functor NAND 1, L_0x249d0a0, L_0x249c690, L_0x249d3a0, C4<1>; +L_0x24830b0 .delay (10000,10000,10000) L_0x24830b0/d; +L_0x24831d0/d .functor NAND 1, L_0x249cbe0, L_0x249d1d0, L_0x249d440, C4<1>; +L_0x24831d0 .delay (10000,10000,10000) L_0x24831d0/d; +L_0x249de00/d .functor NAND 1, L_0x249d0a0, L_0x249d1d0, L_0x249d530, C4<1>; +L_0x249de00 .delay (10000,10000,10000) L_0x249de00/d; +L_0x249df70/d .functor NAND 1, L_0x2482f70, L_0x24830b0, L_0x24831d0, L_0x249de00; +L_0x249df70 .delay (10000,10000,10000) L_0x249df70/d; +v0x2297890_0 .net "S0", 0 0, L_0x249d0a0; 1 drivers +v0x22972a0_0 .net "S1", 0 0, L_0x249d1d0; 1 drivers +v0x2297320_0 .net "in0", 0 0, L_0x249d300; 1 drivers +v0x2296600_0 .net "in1", 0 0, L_0x249d3a0; 1 drivers +v0x22966a0_0 .net "in2", 0 0, L_0x249d440; 1 drivers +v0x2296370_0 .net "in3", 0 0, L_0x249d530; 1 drivers +v0x2296410_0 .net "nS0", 0 0, L_0x249cbe0; 1 drivers +v0x229bd50_0 .net "nS1", 0 0, L_0x249c690; 1 drivers +v0x229baa0_0 .net "out", 0 0, L_0x249df70; 1 drivers +v0x229bb40_0 .net "out0", 0 0, L_0x2482f70; 1 drivers +v0x229b520_0 .net "out1", 0 0, L_0x24830b0; 1 drivers +v0x229b5c0_0 .net "out2", 0 0, L_0x24831d0; 1 drivers +v0x229a2a0_0 .net "out3", 0 0, L_0x249de00; 1 drivers +S_0x22960e0 .scope module, "TwoMux" "TwoInMux" 2 294, 2 8, S_0x22907c0; + .timescale -9 -12; +L_0x229bdd0/d .functor NOT 1, L_0x249d620, C4<0>, C4<0>, C4<0>; +L_0x229bdd0 .delay (10000,10000,10000) L_0x229bdd0/d; +L_0x24843f0/d .functor AND 1, L_0x249d6c0, L_0x229bdd0, C4<1>, C4<1>; +L_0x24843f0 .delay (20000,20000,20000) L_0x24843f0/d; +L_0x24844e0/d .functor AND 1, L_0x249d7b0, L_0x249d620, C4<1>, C4<1>; +L_0x24844e0 .delay (20000,20000,20000) L_0x24844e0/d; +L_0x24845d0/d .functor OR 1, L_0x24843f0, L_0x24844e0, C4<0>, C4<0>; +L_0x24845d0 .delay (20000,20000,20000) L_0x24845d0/d; +v0x2295e50_0 .net "S", 0 0, L_0x249d620; 1 drivers +v0x2295ef0_0 .net "in0", 0 0, L_0x249d6c0; 1 drivers +v0x22958d0_0 .net "in1", 0 0, L_0x249d7b0; 1 drivers +v0x2295970_0 .net "nS", 0 0, L_0x229bdd0; 1 drivers +v0x22945e0_0 .net "out0", 0 0, L_0x24843f0; 1 drivers +v0x2294330_0 .net "out1", 0 0, L_0x24844e0; 1 drivers +v0x22977f0_0 .net "outfinal", 0 0, L_0x24845d0; 1 drivers +S_0x227f740 .scope generate, "muxbits[22]" "muxbits[22]" 2 290, 2 290, S_0x22690e0; + .timescale -9 -12; +P_0x2278ea8 .param/l "i" 2 290, +C4<010110>; +L_0x24a03e0/d .functor OR 1, L_0x24a0520, L_0x24a1d40, C4<0>, C4<0>; +L_0x24a03e0 .delay (20000,20000,20000) L_0x24a03e0/d; +v0x2291a00_0 .net *"_s15", 0 0, L_0x24a0520; 1 drivers +v0x2290a50_0 .net *"_s16", 0 0, L_0x24a1d40; 1 drivers +S_0x2288c70 .scope module, "ZeroMux" "FourInMux" 2 292, 2 24, S_0x227f740; + .timescale -9 -12; +L_0x249dc10/d .functor NOT 1, L_0x249e930, C4<0>, C4<0>, C4<0>; +L_0x249dc10 .delay (10000,10000,10000) L_0x249dc10/d; +L_0x249dd00/d .functor NOT 1, L_0x249ea60, C4<0>, C4<0>, C4<0>; +L_0x249dd00 .delay (10000,10000,10000) L_0x249dd00/d; +L_0x249dda0/d .functor NAND 1, L_0x249dc10, L_0x249dd00, L_0x249eb90, C4<1>; +L_0x249dda0 .delay (10000,10000,10000) L_0x249dda0/d; +L_0x249e300/d .functor NAND 1, L_0x249e930, L_0x249dd00, L_0x249ec30, C4<1>; +L_0x249e300 .delay (10000,10000,10000) L_0x249e300/d; +L_0x249e3f0/d .functor NAND 1, L_0x249dc10, L_0x249ea60, L_0x249ecd0, C4<1>; +L_0x249e3f0 .delay (10000,10000,10000) L_0x249e3f0/d; +L_0x249e540/d .functor NAND 1, L_0x249e930, L_0x249ea60, L_0x249edc0, C4<1>; +L_0x249e540 .delay (10000,10000,10000) L_0x249e540/d; +L_0x249e680/d .functor NAND 1, L_0x249dda0, L_0x249e300, L_0x249e3f0, L_0x249e540; +L_0x249e680 .delay (10000,10000,10000) L_0x249e680/d; +v0x228c090_0 .net "S0", 0 0, L_0x249e930; 1 drivers +v0x228be00_0 .net "S1", 0 0, L_0x249ea60; 1 drivers +v0x228bea0_0 .net "in0", 0 0, L_0x249eb90; 1 drivers +v0x228aef0_0 .net "in1", 0 0, L_0x249ec30; 1 drivers +v0x228af70_0 .net "in2", 0 0, L_0x249ecd0; 1 drivers +v0x228ac60_0 .net "in3", 0 0, L_0x249edc0; 1 drivers +v0x228ad00_0 .net "nS0", 0 0, L_0x249dc10; 1 drivers +v0x228ea60_0 .net "nS1", 0 0, L_0x249dd00; 1 drivers +v0x228eb00_0 .net "out", 0 0, L_0x249e680; 1 drivers +v0x228e7d0_0 .net "out0", 0 0, L_0x249dda0; 1 drivers +v0x228e850_0 .net "out1", 0 0, L_0x249e300; 1 drivers +v0x2291bf0_0 .net "out2", 0 0, L_0x249e3f0; 1 drivers +v0x2291960_0 .net "out3", 0 0, L_0x249e540; 1 drivers +S_0x22830c0 .scope module, "OneMux" "FourInMux" 2 293, 2 24, S_0x227f740; + .timescale -9 -12; +L_0x249eeb0/d .functor NOT 1, L_0x24a0da0, C4<0>, C4<0>, C4<0>; +L_0x249eeb0 .delay (10000,10000,10000) L_0x249eeb0/d; +L_0x249ef50/d .functor NOT 1, L_0x249f7c0, C4<0>, C4<0>, C4<0>; +L_0x249ef50 .delay (10000,10000,10000) L_0x249ef50/d; +L_0x24a0660/d .functor NAND 1, L_0x249eeb0, L_0x249ef50, L_0x249f8f0, C4<1>; +L_0x24a0660 .delay (10000,10000,10000) L_0x24a0660/d; +L_0x24a07a0/d .functor NAND 1, L_0x24a0da0, L_0x249ef50, L_0x249f990, C4<1>; +L_0x24a07a0 .delay (10000,10000,10000) L_0x24a07a0/d; +L_0x24a0890/d .functor NAND 1, L_0x249eeb0, L_0x249f7c0, L_0x249fa30, C4<1>; +L_0x24a0890 .delay (10000,10000,10000) L_0x24a0890/d; +L_0x24a0980/d .functor NAND 1, L_0x24a0da0, L_0x249f7c0, L_0x249fb20, C4<1>; +L_0x24a0980 .delay (10000,10000,10000) L_0x24a0980/d; +L_0x24a0af0/d .functor NAND 1, L_0x24a0660, L_0x24a07a0, L_0x24a0890, L_0x24a0980; +L_0x24a0af0 .delay (10000,10000,10000) L_0x24a0af0/d; +v0x2282e30_0 .net "S0", 0 0, L_0x24a0da0; 1 drivers +v0x2282ed0_0 .net "S1", 0 0, L_0x249f7c0; 1 drivers +v0x2282ba0_0 .net "in0", 0 0, L_0x249f8f0; 1 drivers +v0x2282c40_0 .net "in1", 0 0, L_0x249f990; 1 drivers +v0x2286530_0 .net "in2", 0 0, L_0x249fa30; 1 drivers +v0x22865d0_0 .net "in3", 0 0, L_0x249fb20; 1 drivers +v0x2286300_0 .net "nS0", 0 0, L_0x249eeb0; 1 drivers +v0x2285390_0 .net "nS1", 0 0, L_0x249ef50; 1 drivers +v0x2285410_0 .net "out", 0 0, L_0x24a0af0; 1 drivers +v0x2285100_0 .net "out0", 0 0, L_0x24a0660; 1 drivers +v0x22851a0_0 .net "out1", 0 0, L_0x24a07a0; 1 drivers +v0x2282640_0 .net "out2", 0 0, L_0x24a0890; 1 drivers +v0x2288f20_0 .net "out3", 0 0, L_0x24a0980; 1 drivers +S_0x227f4b0 .scope module, "TwoMux" "TwoInMux" 2 294, 2 8, S_0x227f740; + .timescale -9 -12; +L_0x249fc10/d .functor NOT 1, L_0x24a00c0, C4<0>, C4<0>, C4<0>; +L_0x249fc10 .delay (10000,10000,10000) L_0x249fc10/d; +L_0x249fd00/d .functor AND 1, L_0x24a0160, L_0x249fc10, C4<1>, C4<1>; +L_0x249fd00 .delay (20000,20000,20000) L_0x249fd00/d; +L_0x249fdf0/d .functor AND 1, L_0x24a0250, L_0x24a00c0, C4<1>, C4<1>; +L_0x249fdf0 .delay (20000,20000,20000) L_0x249fdf0/d; +L_0x249fee0/d .functor OR 1, L_0x249fd00, L_0x249fdf0, C4<0>, C4<0>; +L_0x249fee0 .delay (20000,20000,20000) L_0x249fee0/d; +v0x227c9d0_0 .net "S", 0 0, L_0x24a00c0; 1 drivers +v0x227ca70_0 .net "in0", 0 0, L_0x24a0160; 1 drivers +v0x2284be0_0 .net "in1", 0 0, L_0x24a0250; 1 drivers +v0x2284c80_0 .net "nS", 0 0, L_0x249fc10; 1 drivers +v0x2284660_0 .net "out0", 0 0, L_0x249fd00; 1 drivers +v0x2284700_0 .net "out1", 0 0, L_0x249fdf0; 1 drivers +v0x22833b0_0 .net "outfinal", 0 0, L_0x249fee0; 1 drivers +S_0x2273ef0 .scope generate, "muxbits[23]" "muxbits[23]" 2 290, 2 290, S_0x22690e0; + .timescale -9 -12; +P_0x22699d8 .param/l "i" 2 290, +C4<010111>; +L_0x24a2b20/d .functor OR 1, L_0x24a44f0, L_0x24a35e0, C4<0>, C4<0>; +L_0x24a2b20 .delay (20000,20000,20000) L_0x24a2b20/d; +v0x2280740_0 .net *"_s15", 0 0, L_0x24a44f0; 1 drivers +v0x2280400_0 .net *"_s16", 0 0, L_0x24a35e0; 1 drivers +S_0x227f220 .scope module, "ZeroMux" "FourInMux" 2 292, 2 24, S_0x2273ef0; + .timescale -9 -12; +L_0x24a0ed0/d .functor NOT 1, L_0x24a17a0, C4<0>, C4<0>, C4<0>; +L_0x24a0ed0 .delay (10000,10000,10000) L_0x24a0ed0/d; +L_0x24a0fc0/d .functor NOT 1, L_0x24a18d0, C4<0>, C4<0>, C4<0>; +L_0x24a0fc0 .delay (10000,10000,10000) L_0x24a0fc0/d; +L_0x24a1060/d .functor NAND 1, L_0x24a0ed0, L_0x24a0fc0, L_0x24a1a00, C4<1>; +L_0x24a1060 .delay (10000,10000,10000) L_0x24a1060/d; +L_0x24a11a0/d .functor NAND 1, L_0x24a17a0, L_0x24a0fc0, L_0x24a1aa0, C4<1>; +L_0x24a11a0 .delay (10000,10000,10000) L_0x24a11a0/d; +L_0x24a1290/d .functor NAND 1, L_0x24a0ed0, L_0x24a18d0, L_0x24a1b40, C4<1>; +L_0x24a1290 .delay (10000,10000,10000) L_0x24a1290/d; +L_0x24a1380/d .functor NAND 1, L_0x24a17a0, L_0x24a18d0, L_0x24a1c30, C4<1>; +L_0x24a1380 .delay (10000,10000,10000) L_0x24a1380/d; +L_0x24a14f0/d .functor NAND 1, L_0x24a1060, L_0x24a11a0, L_0x24a1290, L_0x24a1380; +L_0x24a14f0 .delay (10000,10000,10000) L_0x24a14f0/d; +v0x227ef90_0 .net "S0", 0 0, L_0x24a17a0; 1 drivers +v0x227f030_0 .net "S1", 0 0, L_0x24a18d0; 1 drivers +v0x227ea10_0 .net "in0", 0 0, L_0x24a1a00; 1 drivers +v0x227eab0_0 .net "in1", 0 0, L_0x24a1aa0; 1 drivers +v0x227d700_0 .net "in2", 0 0, L_0x24a1b40; 1 drivers +v0x227d7a0_0 .net "in3", 0 0, L_0x24a1c30; 1 drivers +v0x227d490_0 .net "nS0", 0 0, L_0x24a0ed0; 1 drivers +v0x227d1e0_0 .net "nS1", 0 0, L_0x24a0fc0; 1 drivers +v0x227d280_0 .net "out", 0 0, L_0x24a14f0; 1 drivers +v0x227cf50_0 .net "out0", 0 0, L_0x24a1060; 1 drivers +v0x227cff0_0 .net "out1", 0 0, L_0x24a11a0; 1 drivers +v0x2280930_0 .net "out2", 0 0, L_0x24a1290; 1 drivers +v0x22806a0_0 .net "out3", 0 0, L_0x24a1380; 1 drivers +S_0x2277590 .scope module, "OneMux" "FourInMux" 2 293, 2 24, S_0x2273ef0; + .timescale -9 -12; +L_0x24a2ce0/d .functor NOT 1, L_0x24a1e30, C4<0>, C4<0>, C4<0>; +L_0x24a2ce0 .delay (10000,10000,10000) L_0x24a2ce0/d; +L_0x24a2dd0/d .functor NOT 1, L_0x24a1f60, C4<0>, C4<0>, C4<0>; +L_0x24a2dd0 .delay (10000,10000,10000) L_0x24a2dd0/d; +L_0x24a2e70/d .functor NAND 1, L_0x24a2ce0, L_0x24a2dd0, L_0x24a2090, C4<1>; +L_0x24a2e70 .delay (10000,10000,10000) L_0x24a2e70/d; +L_0x24a2fb0/d .functor NAND 1, L_0x24a1e30, L_0x24a2dd0, L_0x24a2130, C4<1>; +L_0x24a2fb0 .delay (10000,10000,10000) L_0x24a2fb0/d; +L_0x24a30a0/d .functor NAND 1, L_0x24a2ce0, L_0x24a1f60, L_0x24a21d0, C4<1>; +L_0x24a30a0 .delay (10000,10000,10000) L_0x24a30a0/d; +L_0x24a31c0/d .functor NAND 1, L_0x24a1e30, L_0x24a1f60, L_0x24a22c0, C4<1>; +L_0x24a31c0 .delay (10000,10000,10000) L_0x24a31c0/d; +L_0x24a3330/d .functor NAND 1, L_0x24a2e70, L_0x24a2fb0, L_0x24a30a0, L_0x24a31c0; +L_0x24a3330 .delay (10000,10000,10000) L_0x24a3330/d; +v0x22778c0_0 .net "S0", 0 0, L_0x24a1e30; 1 drivers +v0x2277300_0 .net "S1", 0 0, L_0x24a1f60; 1 drivers +v0x2277380_0 .net "in0", 0 0, L_0x24a2090; 1 drivers +v0x227ace0_0 .net "in1", 0 0, L_0x24a2130; 1 drivers +v0x227ad80_0 .net "in2", 0 0, L_0x24a21d0; 1 drivers +v0x227aa50_0 .net "in3", 0 0, L_0x24a22c0; 1 drivers +v0x227aaf0_0 .net "nS0", 0 0, L_0x24a2ce0; 1 drivers +v0x227a7b0_0 .net "nS1", 0 0, L_0x24a2dd0; 1 drivers +v0x2279af0_0 .net "out", 0 0, L_0x24a3330; 1 drivers +v0x2279b90_0 .net "out0", 0 0, L_0x24a2e70; 1 drivers +v0x2279860_0 .net "out1", 0 0, L_0x24a2fb0; 1 drivers +v0x2279900_0 .net "out2", 0 0, L_0x24a30a0; 1 drivers +v0x2276e10_0 .net "out3", 0 0, L_0x24a31c0; 1 drivers +S_0x2273c60 .scope module, "TwoMux" "TwoInMux" 2 294, 2 8, S_0x2273ef0; + .timescale -9 -12; +L_0x227a830/d .functor NOT 1, L_0x24a2800, C4<0>, C4<0>, C4<0>; +L_0x227a830 .delay (10000,10000,10000) L_0x227a830/d; +L_0x24a2440/d .functor AND 1, L_0x24a28a0, L_0x227a830, C4<1>, C4<1>; +L_0x24a2440 .delay (20000,20000,20000) L_0x24a2440/d; +L_0x24a2530/d .functor AND 1, L_0x24a2990, L_0x24a2800, C4<1>, C4<1>; +L_0x24a2530 .delay (20000,20000,20000) L_0x24a2530/d; +L_0x24a2620/d .functor OR 1, L_0x24a2440, L_0x24a2530, C4<0>, C4<0>; +L_0x24a2620 .delay (20000,20000,20000) L_0x24a2620/d; +v0x22795d0_0 .net "S", 0 0, L_0x24a2800; 1 drivers +v0x2279670_0 .net "in0", 0 0, L_0x24a28a0; 1 drivers +v0x2279340_0 .net "in1", 0 0, L_0x24a2990; 1 drivers +v0x22793e0_0 .net "nS", 0 0, L_0x227a830; 1 drivers +v0x2278de0_0 .net "out0", 0 0, L_0x24a2440; 1 drivers +v0x2277ab0_0 .net "out1", 0 0, L_0x24a2530; 1 drivers +v0x2277820_0 .net "outfinal", 0 0, L_0x24a2620; 1 drivers +S_0x2260720 .scope generate, "muxbits[24]" "muxbits[24]" 2 290, 2 290, S_0x22690e0; + .timescale -9 -12; +P_0x23db138 .param/l "i" 2 290, +C4<011000>; +L_0x24a51b0/d .functor OR 1, L_0x24a52f0, L_0x24a5390, C4<0>, C4<0>; +L_0x24a51b0 .delay (20000,20000,20000) L_0x24a51b0/d; +v0x2274ea0_0 .net *"_s15", 0 0, L_0x24a52f0; 1 drivers +v0x2274b70_0 .net *"_s16", 0 0, L_0x24a5390; 1 drivers +S_0x226c110 .scope module, "ZeroMux" "FourInMux" 2 292, 2 24, S_0x2260720; + .timescale -9 -12; +L_0x24a36d0/d .functor NOT 1, L_0x24a3f70, C4<0>, C4<0>, C4<0>; +L_0x24a36d0 .delay (10000,10000,10000) L_0x24a36d0/d; +L_0x24a37c0/d .functor NOT 1, L_0x24a40a0, C4<0>, C4<0>, C4<0>; +L_0x24a37c0 .delay (10000,10000,10000) L_0x24a37c0/d; +L_0x24a3860/d .functor NAND 1, L_0x24a36d0, L_0x24a37c0, L_0x24a41d0, C4<1>; +L_0x24a3860 .delay (10000,10000,10000) L_0x24a3860/d; +L_0x24a39a0/d .functor NAND 1, L_0x24a3f70, L_0x24a37c0, L_0x24a4270, C4<1>; +L_0x24a39a0 .delay (10000,10000,10000) L_0x24a39a0/d; +L_0x24a3a90/d .functor NAND 1, L_0x24a36d0, L_0x24a40a0, L_0x24a4310, C4<1>; +L_0x24a3a90 .delay (10000,10000,10000) L_0x24a3a90/d; +L_0x24a3b80/d .functor NAND 1, L_0x24a3f70, L_0x24a40a0, L_0x24a4400, C4<1>; +L_0x24a3b80 .delay (10000,10000,10000) L_0x24a3b80/d; +L_0x24a3cc0/d .functor NAND 1, L_0x24a3860, L_0x24a39a0, L_0x24a3a90, L_0x24a3b80; +L_0x24a3cc0 .delay (10000,10000,10000) L_0x24a3cc0/d; +v0x226f530_0 .net "S0", 0 0, L_0x24a3f70; 1 drivers +v0x226f2a0_0 .net "S1", 0 0, L_0x24a40a0; 1 drivers +v0x226f340_0 .net "in0", 0 0, L_0x24a41d0; 1 drivers +v0x226e390_0 .net "in1", 0 0, L_0x24a4270; 1 drivers +v0x226e410_0 .net "in2", 0 0, L_0x24a4310; 1 drivers +v0x226e100_0 .net "in3", 0 0, L_0x24a4400; 1 drivers +v0x226e1a0_0 .net "nS0", 0 0, L_0x24a36d0; 1 drivers +v0x2271f00_0 .net "nS1", 0 0, L_0x24a37c0; 1 drivers +v0x2271fa0_0 .net "out", 0 0, L_0x24a3cc0; 1 drivers +v0x2271c70_0 .net "out0", 0 0, L_0x24a3860; 1 drivers +v0x2271cf0_0 .net "out1", 0 0, L_0x24a39a0; 1 drivers +v0x2275090_0 .net "out2", 0 0, L_0x24a3a90; 1 drivers +v0x2274e00_0 .net "out3", 0 0, L_0x24a3b80; 1 drivers +S_0x22629f0 .scope module, "OneMux" "FourInMux" 2 293, 2 24, S_0x2260720; + .timescale -9 -12; +L_0x24a2c60/d .functor NOT 1, L_0x24a5d60, C4<0>, C4<0>, C4<0>; +L_0x24a2c60 .delay (10000,10000,10000) L_0x24a2c60/d; +L_0x24a5580/d .functor NOT 1, L_0x24a4590, C4<0>, C4<0>, C4<0>; +L_0x24a5580 .delay (10000,10000,10000) L_0x24a5580/d; +L_0x24a5620/d .functor NAND 1, L_0x24a2c60, L_0x24a5580, L_0x24a46c0, C4<1>; +L_0x24a5620 .delay (10000,10000,10000) L_0x24a5620/d; +L_0x24a5760/d .functor NAND 1, L_0x24a5d60, L_0x24a5580, L_0x24a4760, C4<1>; +L_0x24a5760 .delay (10000,10000,10000) L_0x24a5760/d; +L_0x24a5850/d .functor NAND 1, L_0x24a2c60, L_0x24a4590, L_0x24a4800, C4<1>; +L_0x24a5850 .delay (10000,10000,10000) L_0x24a5850/d; +L_0x24a5940/d .functor NAND 1, L_0x24a5d60, L_0x24a4590, L_0x24a48f0, C4<1>; +L_0x24a5940 .delay (10000,10000,10000) L_0x24a5940/d; +L_0x24a5ab0/d .functor NAND 1, L_0x24a5620, L_0x24a5760, L_0x24a5850, L_0x24a5940; +L_0x24a5ab0 .delay (10000,10000,10000) L_0x24a5ab0/d; +v0x225ff10_0 .net "S0", 0 0, L_0x24a5d60; 1 drivers +v0x225ffb0_0 .net "S1", 0 0, L_0x24a4590; 1 drivers +v0x2266840_0 .net "in0", 0 0, L_0x24a46c0; 1 drivers +v0x22668e0_0 .net "in1", 0 0, L_0x24a4760; 1 drivers +v0x22665b0_0 .net "in2", 0 0, L_0x24a4800; 1 drivers +v0x2266650_0 .net "in3", 0 0, L_0x24a48f0; 1 drivers +v0x2269a30_0 .net "nS0", 0 0, L_0x24a2c60; 1 drivers +v0x2269740_0 .net "nS1", 0 0, L_0x24a5580; 1 drivers +v0x22697c0_0 .net "out", 0 0, L_0x24a5ab0; 1 drivers +v0x2268830_0 .net "out0", 0 0, L_0x24a5620; 1 drivers +v0x22688d0_0 .net "out1", 0 0, L_0x24a5760; 1 drivers +v0x22685c0_0 .net "out2", 0 0, L_0x24a5850; 1 drivers +v0x226c3c0_0 .net "out3", 0 0, L_0x24a5940; 1 drivers +S_0x2260490 .scope module, "TwoMux" "TwoInMux" 2 294, 2 8, S_0x2260720; + .timescale -9 -12; +L_0x24a49e0/d .functor NOT 1, L_0x24a4e90, C4<0>, C4<0>, C4<0>; +L_0x24a49e0 .delay (10000,10000,10000) L_0x24a49e0/d; +L_0x24a4ad0/d .functor AND 1, L_0x24a4f30, L_0x24a49e0, C4<1>, C4<1>; +L_0x24a4ad0 .delay (20000,20000,20000) L_0x24a4ad0/d; +L_0x24a4bc0/d .functor AND 1, L_0x24a5020, L_0x24a4e90, C4<1>, C4<1>; +L_0x24a4bc0 .delay (20000,20000,20000) L_0x24a4bc0/d; +L_0x24a4cb0/d .functor OR 1, L_0x24a4ad0, L_0x24a4bc0, C4<0>, C4<0>; +L_0x24a4cb0 .delay (20000,20000,20000) L_0x24a4cb0/d; +v0x2263e70_0 .net "S", 0 0, L_0x24a4e90; 1 drivers +v0x2263f10_0 .net "in0", 0 0, L_0x24a4f30; 1 drivers +v0x2263be0_0 .net "in1", 0 0, L_0x24a5020; 1 drivers +v0x2263c80_0 .net "nS", 0 0, L_0x24a49e0; 1 drivers +v0x2263920_0 .net "out0", 0 0, L_0x24a4ad0; 1 drivers +v0x22639c0_0 .net "out1", 0 0, L_0x24a4bc0; 1 drivers +v0x2262ce0_0 .net "outfinal", 0 0, L_0x24a4cb0; 1 drivers +S_0x23d9a20 .scope generate, "muxbits[25]" "muxbits[25]" 2 290, 2 290, S_0x22690e0; + .timescale -9 -12; +P_0x23ce0d8 .param/l "i" 2 290, +C4<011001>; +L_0x24a80c0/d .functor OR 1, L_0x24a8200, L_0x24a82a0, C4<0>, C4<0>; +L_0x24a80c0 .delay (20000,20000,20000) L_0x24a80c0/d; +v0x2260ce0_0 .net *"_s15", 0 0, L_0x24a8200; 1 drivers +v0x22609d0_0 .net *"_s16", 0 0, L_0x24a82a0; 1 drivers +S_0x225e1e0 .scope module, "ZeroMux" "FourInMux" 2 292, 2 24, S_0x23d9a20; + .timescale -9 -12; +L_0x24a5480/d .functor NOT 1, L_0x24a76a0, C4<0>, C4<0>, C4<0>; +L_0x24a5480 .delay (10000,10000,10000) L_0x24a5480/d; +L_0x24a6ef0/d .functor NOT 1, L_0x24a5e90, C4<0>, C4<0>, C4<0>; +L_0x24a6ef0 .delay (10000,10000,10000) L_0x24a6ef0/d; +L_0x24a6f90/d .functor NAND 1, L_0x24a5480, L_0x24a6ef0, L_0x24a5fc0, C4<1>; +L_0x24a6f90 .delay (10000,10000,10000) L_0x24a6f90/d; +L_0x24a70d0/d .functor NAND 1, L_0x24a76a0, L_0x24a6ef0, L_0x24a6060, C4<1>; +L_0x24a70d0 .delay (10000,10000,10000) L_0x24a70d0/d; +L_0x24a71c0/d .functor NAND 1, L_0x24a5480, L_0x24a5e90, L_0x24a6100, C4<1>; +L_0x24a71c0 .delay (10000,10000,10000) L_0x24a71c0/d; +L_0x24a72b0/d .functor NAND 1, L_0x24a76a0, L_0x24a5e90, L_0x24a61f0, C4<1>; +L_0x24a72b0 .delay (10000,10000,10000) L_0x24a72b0/d; +L_0x24a73f0/d .functor NAND 1, L_0x24a6f90, L_0x24a70d0, L_0x24a71c0, L_0x24a72b0; +L_0x24a73f0 .delay (10000,10000,10000) L_0x24a73f0/d; +v0x225df50_0 .net "S0", 0 0, L_0x24a76a0; 1 drivers +v0x225dff0_0 .net "S1", 0 0, L_0x24a5e90; 1 drivers +v0x225cfb0_0 .net "in0", 0 0, L_0x24a5fc0; 1 drivers +v0x225d050_0 .net "in1", 0 0, L_0x24a6060; 1 drivers +v0x225cd20_0 .net "in2", 0 0, L_0x24a6100; 1 drivers +v0x225cdc0_0 .net "in3", 0 0, L_0x24a61f0; 1 drivers +v0x225a190_0 .net "nS0", 0 0, L_0x24a5480; 1 drivers +v0x2262760_0 .net "nS1", 0 0, L_0x24a6ef0; 1 drivers +v0x2262800_0 .net "out", 0 0, L_0x24a73f0; 1 drivers +v0x22624d0_0 .net "out0", 0 0, L_0x24a6f90; 1 drivers +v0x2262570_0 .net "out1", 0 0, L_0x24a70d0; 1 drivers +v0x2261f50_0 .net "out2", 0 0, L_0x24a71c0; 1 drivers +v0x2260c40_0 .net "out3", 0 0, L_0x24a72b0; 1 drivers +S_0x23dd550 .scope module, "OneMux" "FourInMux" 2 293, 2 24, S_0x23d9a20; + .timescale -9 -12; +L_0x24a62e0/d .functor NOT 1, L_0x24a6ba0, C4<0>, C4<0>, C4<0>; +L_0x24a62e0 .delay (10000,10000,10000) L_0x24a62e0/d; +L_0x24a6390/d .functor NOT 1, L_0x24a6cd0, C4<0>, C4<0>, C4<0>; +L_0x24a6390 .delay (10000,10000,10000) L_0x24a6390/d; +L_0x24a6430/d .functor NAND 1, L_0x24a62e0, L_0x24a6390, L_0x24a87f0, C4<1>; +L_0x24a6430 .delay (10000,10000,10000) L_0x24a6430/d; +L_0x24a6570/d .functor NAND 1, L_0x24a6ba0, L_0x24a6390, L_0x24a8890, C4<1>; +L_0x24a6570 .delay (10000,10000,10000) L_0x24a6570/d; +L_0x24a6660/d .functor NAND 1, L_0x24a62e0, L_0x24a6cd0, L_0x24a77d0, C4<1>; +L_0x24a6660 .delay (10000,10000,10000) L_0x24a6660/d; +L_0x24a6780/d .functor NAND 1, L_0x24a6ba0, L_0x24a6cd0, L_0x24a78c0, C4<1>; +L_0x24a6780 .delay (10000,10000,10000) L_0x24a6780/d; +L_0x24a68f0/d .functor NAND 1, L_0x24a6430, L_0x24a6570, L_0x24a6660, L_0x24a6780; +L_0x24a68f0 .delay (10000,10000,10000) L_0x24a68f0/d; +v0x23de4c0_0 .net "S0", 0 0, L_0x24a6ba0; 1 drivers +v0x225ca90_0 .net "S1", 0 0, L_0x24a6cd0; 1 drivers +v0x225cb10_0 .net "in0", 0 0, L_0x24a87f0; 1 drivers +v0x225c7d0_0 .net "in1", 0 0, L_0x24a8890; 1 drivers +v0x225c870_0 .net "in2", 0 0, L_0x24a77d0; 1 drivers +v0x225c250_0 .net "in3", 0 0, L_0x24a78c0; 1 drivers +v0x225c2f0_0 .net "nS0", 0 0, L_0x24a62e0; 1 drivers +v0x225af20_0 .net "nS1", 0 0, L_0x24a6390; 1 drivers +v0x225ac40_0 .net "out", 0 0, L_0x24a68f0; 1 drivers +v0x225ace0_0 .net "out0", 0 0, L_0x24a6430; 1 drivers +v0x225a9b0_0 .net "out1", 0 0, L_0x24a6570; 1 drivers +v0x225aa50_0 .net "out2", 0 0, L_0x24a6660; 1 drivers +v0x225a780_0 .net "out3", 0 0, L_0x24a6780; 1 drivers +S_0x23d8b50 .scope module, "TwoMux" "TwoInMux" 2 294, 2 8, S_0x23d9a20; + .timescale -9 -12; +L_0x24a6e00/d .functor NOT 1, L_0x24a7da0, C4<0>, C4<0>, C4<0>; +L_0x24a6e00 .delay (10000,10000,10000) L_0x24a6e00/d; +L_0x225afa0/d .functor AND 1, L_0x24a7e40, L_0x24a6e00, C4<1>, C4<1>; +L_0x225afa0 .delay (20000,20000,20000) L_0x225afa0/d; +L_0x24a7ad0/d .functor AND 1, L_0x24a7f30, L_0x24a7da0, C4<1>, C4<1>; +L_0x24a7ad0 .delay (20000,20000,20000) L_0x24a7ad0/d; +L_0x24a7bc0/d .functor OR 1, L_0x225afa0, L_0x24a7ad0, C4<0>, C4<0>; +L_0x24a7bc0 .delay (20000,20000,20000) L_0x24a7bc0/d; +v0x23dc1a0_0 .net "S", 0 0, L_0x24a7da0; 1 drivers +v0x23dc240_0 .net "in0", 0 0, L_0x24a7e40; 1 drivers +v0x23dbf20_0 .net "in1", 0 0, L_0x24a7f30; 1 drivers +v0x23dbfc0_0 .net "nS", 0 0, L_0x24a6e00; 1 drivers +v0x23db070_0 .net "out0", 0 0, L_0x225afa0; 1 drivers +v0x23de6a0_0 .net "out1", 0 0, L_0x24a7ad0; 1 drivers +v0x23de420_0 .net "outfinal", 0 0, L_0x24a7bc0; 1 drivers +S_0x23c7420 .scope generate, "muxbits[26]" "muxbits[26]" 2 290, 2 290, S_0x22690e0; + .timescale -9 -12; +P_0x23b7208 .param/l "i" 2 290, +C4<011010>; +L_0x24aa7a0/d .functor OR 1, L_0x24aa8e0, L_0x24aa980, C4<0>, C4<0>; +L_0x24aa7a0 .delay (20000,20000,20000) L_0x24aa7a0/d; +v0x23d66c0_0 .net *"_s15", 0 0, L_0x24aa8e0; 1 drivers +v0x23d9ca0_0 .net *"_s16", 0 0, L_0x24aa980; 1 drivers +S_0x23d2d70 .scope module, "ZeroMux" "FourInMux" 2 292, 2 24, S_0x23c7420; + .timescale -9 -12; +L_0x24a8390/d .functor NOT 1, L_0x24a8930, C4<0>, C4<0>, C4<0>; +L_0x24a8390 .delay (10000,10000,10000) L_0x24a8390/d; +L_0x24a8480/d .functor NOT 1, L_0x24a8a60, C4<0>, C4<0>, C4<0>; +L_0x24a8480 .delay (10000,10000,10000) L_0x24a8480/d; +L_0x24a8520/d .functor NAND 1, L_0x24a8390, L_0x24a8480, L_0x24a8b90, C4<1>; +L_0x24a8520 .delay (10000,10000,10000) L_0x24a8520/d; +L_0x24a8660/d .functor NAND 1, L_0x24a8930, L_0x24a8480, L_0x24a8c30, C4<1>; +L_0x24a8660 .delay (10000,10000,10000) L_0x24a8660/d; +L_0x24a8750/d .functor NAND 1, L_0x24a8390, L_0x24a8a60, L_0x24a8cd0, C4<1>; +L_0x24a8750 .delay (10000,10000,10000) L_0x24a8750/d; +L_0x24a99f0/d .functor NAND 1, L_0x24a8930, L_0x24a8a60, L_0x24a8dc0, C4<1>; +L_0x24a99f0 .delay (10000,10000,10000) L_0x24a99f0/d; +L_0x24a9b30/d .functor NAND 1, L_0x24a8520, L_0x24a8660, L_0x24a8750, L_0x24a99f0; +L_0x24a9b30 .delay (10000,10000,10000) L_0x24a9b30/d; +v0x23d2af0_0 .net "S0", 0 0, L_0x24a8930; 1 drivers +v0x23d1c00_0 .net "S1", 0 0, L_0x24a8a60; 1 drivers +v0x23d1ca0_0 .net "in0", 0 0, L_0x24a8b90; 1 drivers +v0x23d5280_0 .net "in1", 0 0, L_0x24a8c30; 1 drivers +v0x23d5300_0 .net "in2", 0 0, L_0x24a8cd0; 1 drivers +v0x23d5000_0 .net "in3", 0 0, L_0x24a8dc0; 1 drivers +v0x23d50a0_0 .net "nS0", 0 0, L_0x24a8390; 1 drivers +v0x23d4110_0 .net "nS1", 0 0, L_0x24a8480; 1 drivers +v0x23d41b0_0 .net "out", 0 0, L_0x24a9b30; 1 drivers +v0x23d77a0_0 .net "out0", 0 0, L_0x24a8520; 1 drivers +v0x23d7820_0 .net "out1", 0 0, L_0x24a8660; 1 drivers +v0x23d7520_0 .net "out2", 0 0, L_0x24a8750; 1 drivers +v0x23d6620_0 .net "out3", 0 0, L_0x24a99f0; 1 drivers +S_0x23cbe40 .scope module, "OneMux" "FourInMux" 2 293, 2 24, S_0x23c7420; + .timescale -9 -12; +L_0x24a8eb0/d .functor NOT 1, L_0x24a9780, C4<0>, C4<0>, C4<0>; +L_0x24a8eb0 .delay (10000,10000,10000) L_0x24a8eb0/d; +L_0x24a8fa0/d .functor NOT 1, L_0x24a98b0, C4<0>, C4<0>, C4<0>; +L_0x24a8fa0 .delay (10000,10000,10000) L_0x24a8fa0/d; +L_0x24a9040/d .functor NAND 1, L_0x24a8eb0, L_0x24a8fa0, L_0x24aaf30, C4<1>; +L_0x24a9040 .delay (10000,10000,10000) L_0x24a9040/d; +L_0x24a9180/d .functor NAND 1, L_0x24a9780, L_0x24a8fa0, L_0x24a9de0, C4<1>; +L_0x24a9180 .delay (10000,10000,10000) L_0x24a9180/d; +L_0x24a9270/d .functor NAND 1, L_0x24a8eb0, L_0x24a98b0, L_0x24a9e80, C4<1>; +L_0x24a9270 .delay (10000,10000,10000) L_0x24a9270/d; +L_0x24a9360/d .functor NAND 1, L_0x24a9780, L_0x24a98b0, L_0x24a9f20, C4<1>; +L_0x24a9360 .delay (10000,10000,10000) L_0x24a9360/d; +L_0x24a94d0/d .functor NAND 1, L_0x24a9040, L_0x24a9180, L_0x24a9270, L_0x24a9360; +L_0x24a94d0 .delay (10000,10000,10000) L_0x24a94d0/d; +v0x23cbbc0_0 .net "S0", 0 0, L_0x24a9780; 1 drivers +v0x23cbc60_0 .net "S1", 0 0, L_0x24a98b0; 1 drivers +v0x23cacd0_0 .net "in0", 0 0, L_0x24aaf30; 1 drivers +v0x23cad70_0 .net "in1", 0 0, L_0x24a9de0; 1 drivers +v0x23ce350_0 .net "in2", 0 0, L_0x24a9e80; 1 drivers +v0x23ce3f0_0 .net "in3", 0 0, L_0x24a9f20; 1 drivers +v0x23ce130_0 .net "nS0", 0 0, L_0x24a8eb0; 1 drivers +v0x23cd1e0_0 .net "nS1", 0 0, L_0x24a8fa0; 1 drivers +v0x23cd260_0 .net "out", 0 0, L_0x24a94d0; 1 drivers +v0x23d0860_0 .net "out0", 0 0, L_0x24a9040; 1 drivers +v0x23d0900_0 .net "out1", 0 0, L_0x24a9180; 1 drivers +v0x23d0600_0 .net "out2", 0 0, L_0x24a9270; 1 drivers +v0x23cf710_0 .net "out3", 0 0, L_0x24a9360; 1 drivers +S_0x23c71a0 .scope module, "TwoMux" "TwoInMux" 2 294, 2 8, S_0x23c7420; + .timescale -9 -12; +L_0x24aa010/d .functor NOT 1, L_0x24aa480, C4<0>, C4<0>, C4<0>; +L_0x24aa010 .delay (10000,10000,10000) L_0x24aa010/d; +L_0x24aa0c0/d .functor AND 1, L_0x24aa520, L_0x24aa010, C4<1>, C4<1>; +L_0x24aa0c0 .delay (20000,20000,20000) L_0x24aa0c0/d; +L_0x24aa1b0/d .functor AND 1, L_0x24aa610, L_0x24aa480, C4<1>, C4<1>; +L_0x24aa1b0 .delay (20000,20000,20000) L_0x24aa1b0/d; +L_0x24aa2a0/d .functor OR 1, L_0x24aa0c0, L_0x24aa1b0, C4<0>, C4<0>; +L_0x24aa2a0 .delay (20000,20000,20000) L_0x24aa2a0/d; +v0x23c62d0_0 .net "S", 0 0, L_0x24aa480; 1 drivers +v0x23c6370_0 .net "in0", 0 0, L_0x24aa520; 1 drivers +v0x23c9930_0 .net "in1", 0 0, L_0x24aa610; 1 drivers +v0x23c99d0_0 .net "nS", 0 0, L_0x24aa010; 1 drivers +v0x23c96b0_0 .net "out0", 0 0, L_0x24aa0c0; 1 drivers +v0x23c9750_0 .net "out1", 0 0, L_0x24aa1b0; 1 drivers +v0x23c8820_0 .net "outfinal", 0 0, L_0x24aa2a0; 1 drivers +S_0x23b1590 .scope generate, "muxbits[27]" "muxbits[27]" 2 290, 2 290, S_0x22690e0; + .timescale -9 -12; +P_0x23a5c68 .param/l "i" 2 290, +C4<011011>; +L_0x24ace00/d .functor OR 1, L_0x24acf40, L_0x24acfe0, C4<0>, C4<0>; +L_0x24ace00 .delay (20000,20000,20000) L_0x24ace00/d; +v0x23c4d40_0 .net *"_s15", 0 0, L_0x24acf40; 1 drivers +v0x23c3df0_0 .net *"_s16", 0 0, L_0x24acfe0; 1 drivers +S_0x23bced0 .scope module, "ZeroMux" "FourInMux" 2 292, 2 24, S_0x23b1590; + .timescale -9 -12; +L_0x24aaa70/d .functor NOT 1, L_0x24ac5a0, C4<0>, C4<0>, C4<0>; +L_0x24aaa70 .delay (10000,10000,10000) L_0x24aaa70/d; +L_0x24aab60/d .functor NOT 1, L_0x24aafd0, C4<0>, C4<0>, C4<0>; +L_0x24aab60 .delay (10000,10000,10000) L_0x24aab60/d; +L_0x24aac00/d .functor NAND 1, L_0x24aaa70, L_0x24aab60, L_0x24ab100, C4<1>; +L_0x24aac00 .delay (10000,10000,10000) L_0x24aac00/d; +L_0x24aad40/d .functor NAND 1, L_0x24ac5a0, L_0x24aab60, L_0x24ab1a0, C4<1>; +L_0x24aad40 .delay (10000,10000,10000) L_0x24aad40/d; +L_0x24aae30/d .functor NAND 1, L_0x24aaa70, L_0x24aafd0, L_0x24ab240, C4<1>; +L_0x24aae30 .delay (10000,10000,10000) L_0x24aae30/d; +L_0x24ac180/d .functor NAND 1, L_0x24ac5a0, L_0x24aafd0, L_0x24ab330, C4<1>; +L_0x24ac180 .delay (10000,10000,10000) L_0x24ac180/d; +L_0x24ac2f0/d .functor NAND 1, L_0x24aac00, L_0x24aad40, L_0x24aae30, L_0x24ac180; +L_0x24ac2f0 .delay (10000,10000,10000) L_0x24ac2f0/d; +v0x23c0520_0 .net "S0", 0 0, L_0x24ac5a0; 1 drivers +v0x23c05c0_0 .net "S1", 0 0, L_0x24aafd0; 1 drivers +v0x23c02a0_0 .net "in0", 0 0, L_0x24ab100; 1 drivers +v0x23c0340_0 .net "in1", 0 0, L_0x24ab1a0; 1 drivers +v0x23bf3d0_0 .net "in2", 0 0, L_0x24ab240; 1 drivers +v0x23bf470_0 .net "in3", 0 0, L_0x24ab330; 1 drivers +v0x23c2a40_0 .net "nS0", 0 0, L_0x24aaa70; 1 drivers +v0x23c27a0_0 .net "nS1", 0 0, L_0x24aab60; 1 drivers +v0x23c2840_0 .net "out", 0 0, L_0x24ac2f0; 1 drivers +v0x23c18d0_0 .net "out0", 0 0, L_0x24aac00; 1 drivers +v0x23c1970_0 .net "out1", 0 0, L_0x24aad40; 1 drivers +v0x23c4f20_0 .net "out2", 0 0, L_0x24aae30; 1 drivers +v0x23c4ca0_0 .net "out3", 0 0, L_0x24ac180; 1 drivers +S_0x23b9620 .scope module, "OneMux" "FourInMux" 2 293, 2 24, S_0x23b1590; + .timescale -9 -12; +L_0x24ab420/d .functor NOT 1, L_0x24abce0, C4<0>, C4<0>, C4<0>; +L_0x24ab420 .delay (10000,10000,10000) L_0x24ab420/d; +L_0x24ab4d0/d .functor NOT 1, L_0x24abe10, C4<0>, C4<0>, C4<0>; +L_0x24ab4d0 .delay (10000,10000,10000) L_0x24ab4d0/d; +L_0x24ab570/d .functor NAND 1, L_0x24ab420, L_0x24ab4d0, L_0x24abf40, C4<1>; +L_0x24ab570 .delay (10000,10000,10000) L_0x24ab570/d; +L_0x24ab6b0/d .functor NAND 1, L_0x24abce0, L_0x24ab4d0, L_0x24abfe0, C4<1>; +L_0x24ab6b0 .delay (10000,10000,10000) L_0x24ab6b0/d; +L_0x24ab7a0/d .functor NAND 1, L_0x24ab420, L_0x24abe10, L_0x24ad850, C4<1>; +L_0x24ab7a0 .delay (10000,10000,10000) L_0x24ab7a0/d; +L_0x24ab8c0/d .functor NAND 1, L_0x24abce0, L_0x24abe10, L_0x24ad8f0, C4<1>; +L_0x24ab8c0 .delay (10000,10000,10000) L_0x24ab8c0/d; +L_0x24aba30/d .functor NAND 1, L_0x24ab570, L_0x24ab6b0, L_0x24ab7a0, L_0x24ab8c0; +L_0x24aba30 .delay (10000,10000,10000) L_0x24aba30/d; +v0x23b6050_0 .net "S0", 0 0, L_0x24abce0; 1 drivers +v0x23b93a0_0 .net "S1", 0 0, L_0x24abe10; 1 drivers +v0x23b9420_0 .net "in0", 0 0, L_0x24abf40; 1 drivers +v0x23b84d0_0 .net "in1", 0 0, L_0x24abfe0; 1 drivers +v0x23b8570_0 .net "in2", 0 0, L_0x24ad850; 1 drivers +v0x23bbb20_0 .net "in3", 0 0, L_0x24ad8f0; 1 drivers +v0x23bbbc0_0 .net "nS0", 0 0, L_0x24ab420; 1 drivers +v0x23bb8c0_0 .net "nS1", 0 0, L_0x24ab4d0; 1 drivers +v0x23ba9d0_0 .net "out", 0 0, L_0x24aba30; 1 drivers +v0x23baa70_0 .net "out0", 0 0, L_0x24ab570; 1 drivers +v0x23be020_0 .net "out1", 0 0, L_0x24ab6b0; 1 drivers +v0x23be0c0_0 .net "out2", 0 0, L_0x24ab7a0; 1 drivers +v0x23bde30_0 .net "out3", 0 0, L_0x24ab8c0; 1 drivers +S_0x23b4c10 .scope module, "TwoMux" "TwoInMux" 2 294, 2 8, S_0x23b1590; + .timescale -9 -12; +L_0x23bb940/d .functor NOT 1, L_0x24acae0, C4<0>, C4<0>, C4<0>; +L_0x23bb940 .delay (10000,10000,10000) L_0x23bb940/d; +L_0x24ac720/d .functor AND 1, L_0x24acb80, L_0x23bb940, C4<1>, C4<1>; +L_0x24ac720 .delay (20000,20000,20000) L_0x24ac720/d; +L_0x24ac810/d .functor AND 1, L_0x24acc70, L_0x24acae0, C4<1>, C4<1>; +L_0x24ac810 .delay (20000,20000,20000) L_0x24ac810/d; +L_0x24ac900/d .functor OR 1, L_0x24ac720, L_0x24ac810, C4<0>, C4<0>; +L_0x24ac900 .delay (20000,20000,20000) L_0x24ac900/d; +v0x23b4990_0 .net "S", 0 0, L_0x24acae0; 1 drivers +v0x23b4a30_0 .net "in0", 0 0, L_0x24acb80; 1 drivers +v0x23b3aa0_0 .net "in1", 0 0, L_0x24acc70; 1 drivers +v0x23b3b40_0 .net "nS", 0 0, L_0x23bb940; 1 drivers +v0x23b7140_0 .net "out0", 0 0, L_0x24ac720; 1 drivers +v0x23b6ea0_0 .net "out1", 0 0, L_0x24ac810; 1 drivers +v0x23b5fb0_0 .net "outfinal", 0 0, L_0x24ac900; 1 drivers +S_0x239fc30 .scope generate, "muxbits[28]" "muxbits[28]" 2 290, 2 290, S_0x22690e0; + .timescale -9 -12; +P_0x23927e8 .param/l "i" 2 290, +C4<011100>; +L_0x24af5a0/d .functor OR 1, L_0x24af6e0, L_0x24af780, C4<0>, C4<0>; +L_0x24af5a0 .delay (20000,20000,20000) L_0x24af5a0/d; +v0x23b27a0_0 .net *"_s15", 0 0, L_0x24af6e0; 1 drivers +v0x23b2480_0 .net *"_s16", 0 0, L_0x24af780; 1 drivers +S_0x23ab550 .scope module, "ZeroMux" "FourInMux" 2 292, 2 24, S_0x239fc30; + .timescale -9 -12; +L_0x24ad0d0/d .functor NOT 1, L_0x24ad9e0, C4<0>, C4<0>, C4<0>; +L_0x24ad0d0 .delay (10000,10000,10000) L_0x24ad0d0/d; +L_0x24ad1c0/d .functor NOT 1, L_0x24adb10, C4<0>, C4<0>, C4<0>; +L_0x24ad1c0 .delay (10000,10000,10000) L_0x24ad1c0/d; +L_0x24ad260/d .functor NAND 1, L_0x24ad0d0, L_0x24ad1c0, L_0x24adc40, C4<1>; +L_0x24ad260 .delay (10000,10000,10000) L_0x24ad260/d; +L_0x24ad3a0/d .functor NAND 1, L_0x24ad9e0, L_0x24ad1c0, L_0x24adce0, C4<1>; +L_0x24ad3a0 .delay (10000,10000,10000) L_0x24ad3a0/d; +L_0x24ad490/d .functor NAND 1, L_0x24ad0d0, L_0x24adb10, L_0x24add80, C4<1>; +L_0x24ad490 .delay (10000,10000,10000) L_0x24ad490/d; +L_0x24ad5e0/d .functor NAND 1, L_0x24ad9e0, L_0x24adb10, L_0x24ade70, C4<1>; +L_0x24ad5e0 .delay (10000,10000,10000) L_0x24ad5e0/d; +L_0x24ad720/d .functor NAND 1, L_0x24ad260, L_0x24ad3a0, L_0x24ad490, L_0x24ad5e0; +L_0x24ad720 .delay (10000,10000,10000) L_0x24ad720/d; +v0x23aa660_0 .net "S0", 0 0, L_0x24ad9e0; 1 drivers +v0x23adce0_0 .net "S1", 0 0, L_0x24adb10; 1 drivers +v0x23add80_0 .net "in0", 0 0, L_0x24adc40; 1 drivers +v0x23ada60_0 .net "in1", 0 0, L_0x24adce0; 1 drivers +v0x23adae0_0 .net "in2", 0 0, L_0x24add80; 1 drivers +v0x23acb70_0 .net "in3", 0 0, L_0x24ade70; 1 drivers +v0x23acc10_0 .net "nS0", 0 0, L_0x24ad0d0; 1 drivers +v0x23b01f0_0 .net "nS1", 0 0, L_0x24ad1c0; 1 drivers +v0x23b0290_0 .net "out", 0 0, L_0x24ad720; 1 drivers +v0x23aff70_0 .net "out0", 0 0, L_0x24ad260; 1 drivers +v0x23afff0_0 .net "out1", 0 0, L_0x24ad3a0; 1 drivers +v0x23af080_0 .net "out2", 0 0, L_0x24ad490; 1 drivers +v0x23b2700_0 .net "out3", 0 0, L_0x24ad5e0; 1 drivers +S_0x23a4630 .scope module, "OneMux" "FourInMux" 2 293, 2 24, S_0x239fc30; + .timescale -9 -12; +L_0x24adf60/d .functor NOT 1, L_0x24ae830, C4<0>, C4<0>, C4<0>; +L_0x24adf60 .delay (10000,10000,10000) L_0x24adf60/d; +L_0x24ae050/d .functor NOT 1, L_0x24ae960, C4<0>, C4<0>, C4<0>; +L_0x24ae050 .delay (10000,10000,10000) L_0x24ae050/d; +L_0x24ae0f0/d .functor NAND 1, L_0x24adf60, L_0x24ae050, L_0x24aea90, C4<1>; +L_0x24ae0f0 .delay (10000,10000,10000) L_0x24ae0f0/d; +L_0x24ae230/d .functor NAND 1, L_0x24ae830, L_0x24ae050, L_0x24aff40, C4<1>; +L_0x24ae230 .delay (10000,10000,10000) L_0x24ae230/d; +L_0x24ae320/d .functor NAND 1, L_0x24adf60, L_0x24ae960, L_0x24affe0, C4<1>; +L_0x24ae320 .delay (10000,10000,10000) L_0x24ae320/d; +L_0x24ae410/d .functor NAND 1, L_0x24ae830, L_0x24ae960, L_0x24aed20, C4<1>; +L_0x24ae410 .delay (10000,10000,10000) L_0x24ae410/d; +L_0x24ae580/d .functor NAND 1, L_0x24ae0f0, L_0x24ae230, L_0x24ae320, L_0x24ae410; +L_0x24ae580 .delay (10000,10000,10000) L_0x24ae580/d; +v0x23a3760_0 .net "S0", 0 0, L_0x24ae830; 1 drivers +v0x23a3800_0 .net "S1", 0 0, L_0x24ae960; 1 drivers +v0x23a6db0_0 .net "in0", 0 0, L_0x24aea90; 1 drivers +v0x23a6e50_0 .net "in1", 0 0, L_0x24aff40; 1 drivers +v0x23a6b30_0 .net "in2", 0 0, L_0x24affe0; 1 drivers +v0x23a6bd0_0 .net "in3", 0 0, L_0x24aed20; 1 drivers +v0x23a5cc0_0 .net "nS0", 0 0, L_0x24adf60; 1 drivers +v0x23a92c0_0 .net "nS1", 0 0, L_0x24ae050; 1 drivers +v0x23a9340_0 .net "out", 0 0, L_0x24ae580; 1 drivers +v0x23a9040_0 .net "out0", 0 0, L_0x24ae0f0; 1 drivers +v0x23a90e0_0 .net "out1", 0 0, L_0x24ae230; 1 drivers +v0x23a8170_0 .net "out2", 0 0, L_0x24ae320; 1 drivers +v0x23ab7f0_0 .net "out3", 0 0, L_0x24ae410; 1 drivers +S_0x239ed60 .scope module, "TwoMux" "TwoInMux" 2 294, 2 8, S_0x239fc30; + .timescale -9 -12; +L_0x24aee10/d .functor NOT 1, L_0x24af280, C4<0>, C4<0>, C4<0>; +L_0x24aee10 .delay (10000,10000,10000) L_0x24aee10/d; +L_0x24aeec0/d .functor AND 1, L_0x24af320, L_0x24aee10, C4<1>, C4<1>; +L_0x24aeec0 .delay (20000,20000,20000) L_0x24aeec0/d; +L_0x24aefb0/d .functor AND 1, L_0x24af410, L_0x24af280, C4<1>, C4<1>; +L_0x24aefb0 .delay (20000,20000,20000) L_0x24aefb0/d; +L_0x24af0a0/d .functor OR 1, L_0x24aeec0, L_0x24aefb0, C4<0>, C4<0>; +L_0x24af0a0 .delay (20000,20000,20000) L_0x24af0a0/d; +v0x23a23b0_0 .net "S", 0 0, L_0x24af280; 1 drivers +v0x23a2450_0 .net "in0", 0 0, L_0x24af320; 1 drivers +v0x23a2130_0 .net "in1", 0 0, L_0x24af410; 1 drivers +v0x23a21d0_0 .net "nS", 0 0, L_0x24aee10; 1 drivers +v0x23a1260_0 .net "out0", 0 0, L_0x24aeec0; 1 drivers +v0x23a1300_0 .net "out1", 0 0, L_0x24aefb0; 1 drivers +v0x23a4910_0 .net "outfinal", 0 0, L_0x24af0a0; 1 drivers +S_0x23913c0 .scope generate, "muxbits[29]" "muxbits[29]" 2 290, 2 290, S_0x22690e0; + .timescale -9 -12; +P_0x23838a8 .param/l "i" 2 290, +C4<011101>; +L_0x24b18c0/d .functor OR 1, L_0x24b19c0, L_0x24b1a60, C4<0>, C4<0>; +L_0x24b18c0 .delay (20000,20000,20000) L_0x24b18c0/d; +v0x239c900_0 .net *"_s15", 0 0, L_0x24b19c0; 1 drivers +v0x239fed0_0 .net *"_s16", 0 0, L_0x24b1a60; 1 drivers +S_0x2398f40 .scope module, "ZeroMux" "FourInMux" 2 292, 2 24, S_0x23913c0; + .timescale -9 -12; +L_0x24af870/d .functor NOT 1, L_0x24b1510, C4<0>, C4<0>, C4<0>; +L_0x24af870 .delay (10000,10000,10000) L_0x24af870/d; +L_0x24af960/d .functor NOT 1, L_0x24b0080, C4<0>, C4<0>, C4<0>; +L_0x24af960 .delay (10000,10000,10000) L_0x24af960/d; +L_0x24afa00/d .functor NAND 1, L_0x24af870, L_0x24af960, L_0x24b01b0, C4<1>; +L_0x24afa00 .delay (10000,10000,10000) L_0x24afa00/d; +L_0x24afb40/d .functor NAND 1, L_0x24b1510, L_0x24af960, L_0x24b0250, C4<1>; +L_0x24afb40 .delay (10000,10000,10000) L_0x24afb40/d; +L_0x24afc30/d .functor NAND 1, L_0x24af870, L_0x24b0080, L_0x24b02f0, C4<1>; +L_0x24afc30 .delay (10000,10000,10000) L_0x24afc30/d; +L_0x24afd20/d .functor NAND 1, L_0x24b1510, L_0x24b0080, L_0x24b0390, C4<1>; +L_0x24afd20 .delay (10000,10000,10000) L_0x24afd20/d; +L_0x24afe90/d .functor NAND 1, L_0x24afa00, L_0x24afb40, L_0x24afc30, L_0x24afd20; +L_0x24afe90 .delay (10000,10000,10000) L_0x24afe90/d; +v0x2398c60_0 .net "S0", 0 0, L_0x24b1510; 1 drivers +v0x2398d00_0 .net "S1", 0 0, L_0x24b0080; 1 drivers +v0x2397db0_0 .net "in0", 0 0, L_0x24b01b0; 1 drivers +v0x2397e50_0 .net "in1", 0 0, L_0x24b0250; 1 drivers +v0x239b4b0_0 .net "in2", 0 0, L_0x24b02f0; 1 drivers +v0x239b550_0 .net "in3", 0 0, L_0x24b0390; 1 drivers +v0x239b250_0 .net "nS0", 0 0, L_0x24af870; 1 drivers +v0x239a330_0 .net "nS1", 0 0, L_0x24af960; 1 drivers +v0x239a3d0_0 .net "out", 0 0, L_0x24afe90; 1 drivers +v0x239d9b0_0 .net "out0", 0 0, L_0x24afa00; 1 drivers +v0x239da50_0 .net "out1", 0 0, L_0x24afb40; 1 drivers +v0x239d730_0 .net "out2", 0 0, L_0x24afc30; 1 drivers +v0x239c860_0 .net "out3", 0 0, L_0x24afd20; 1 drivers +S_0x2393cc0 .scope module, "OneMux" "FourInMux" 2 293, 2 24, S_0x23913c0; + .timescale -9 -12; +L_0x24b0480/d .functor NOT 1, L_0x24b0d70, C4<0>, C4<0>, C4<0>; +L_0x24b0480 .delay (10000,10000,10000) L_0x24b0480/d; +L_0x24b0530/d .functor NOT 1, L_0x24b0ea0, C4<0>, C4<0>, C4<0>; +L_0x24b0530 .delay (10000,10000,10000) L_0x24b0530/d; +L_0x24b05d0/d .functor NAND 1, L_0x24b0480, L_0x24b0530, L_0x24b0fd0, C4<1>; +L_0x24b05d0 .delay (10000,10000,10000) L_0x24b05d0/d; +L_0x24b0710/d .functor NAND 1, L_0x24b0d70, L_0x24b0530, L_0x24b1070, C4<1>; +L_0x24b0710 .delay (10000,10000,10000) L_0x24b0710/d; +L_0x24b0800/d .functor NAND 1, L_0x24b0480, L_0x24b0ea0, L_0x24b1110, C4<1>; +L_0x24b0800 .delay (10000,10000,10000) L_0x24b0800/d; +L_0x24b0950/d .functor NAND 1, L_0x24b0d70, L_0x24b0ea0, L_0x24b1200, C4<1>; +L_0x24b0950 .delay (10000,10000,10000) L_0x24b0950/d; +L_0x24b0ac0/d .functor NAND 1, L_0x24b05d0, L_0x24b0710, L_0x24b0800, L_0x24b0950; +L_0x24b0ac0 .delay (10000,10000,10000) L_0x24b0ac0/d; +v0x2393fe0_0 .net "S0", 0 0, L_0x24b0d70; 1 drivers +v0x23937c0_0 .net "S1", 0 0, L_0x24b0ea0; 1 drivers +v0x2393840_0 .net "in0", 0 0, L_0x24b0fd0; 1 drivers +v0x2395500_0 .net "in1", 0 0, L_0x24b1070; 1 drivers +v0x23955a0_0 .net "in2", 0 0, L_0x24b1110; 1 drivers +v0x2395280_0 .net "in3", 0 0, L_0x24b1200; 1 drivers +v0x2395320_0 .net "nS0", 0 0, L_0x24b0480; 1 drivers +v0x2394da0_0 .net "nS1", 0 0, L_0x24b0530; 1 drivers +v0x23e0b80_0 .net "out", 0 0, L_0x24b0ac0; 1 drivers +v0x23e0c20_0 .net "out0", 0 0, L_0x24b05d0; 1 drivers +v0x23e0910_0 .net "out1", 0 0, L_0x24b0710; 1 drivers +v0x23e09b0_0 .net "out2", 0 0, L_0x24b0800; 1 drivers +v0x23dfae0_0 .net "out3", 0 0, L_0x24b0950; 1 drivers +S_0x2391140 .scope module, "TwoMux" "TwoInMux" 2 294, 2 8, S_0x23913c0; + .timescale -9 -12; +L_0x24b2920/d .functor NOT 1, L_0x24b2dd0, C4<0>, C4<0>, C4<0>; +L_0x24b2920 .delay (10000,10000,10000) L_0x24b2920/d; +L_0x24b2a10/d .functor AND 1, L_0x24b1640, L_0x24b2920, C4<1>, C4<1>; +L_0x24b2a10 .delay (20000,20000,20000) L_0x24b2a10/d; +L_0x24b2b00/d .functor AND 1, L_0x24b1730, L_0x24b2dd0, C4<1>, C4<1>; +L_0x24b2b00 .delay (20000,20000,20000) L_0x24b2b00/d; +L_0x24b2bf0/d .functor OR 1, L_0x24b2a10, L_0x24b2b00, C4<0>, C4<0>; +L_0x24b2bf0 .delay (20000,20000,20000) L_0x24b2bf0/d; +v0x2390c40_0 .net "S", 0 0, L_0x24b2dd0; 1 drivers +v0x2390ce0_0 .net "in0", 0 0, L_0x24b1640; 1 drivers +v0x2392980_0 .net "in1", 0 0, L_0x24b1730; 1 drivers +v0x2392a20_0 .net "nS", 0 0, L_0x24b2920; 1 drivers +v0x2392720_0 .net "out0", 0 0, L_0x24b2a10; 1 drivers +v0x2392200_0 .net "out1", 0 0, L_0x24b2b00; 1 drivers +v0x2393f40_0 .net "outfinal", 0 0, L_0x24b2bf0; 1 drivers +S_0x2385000 .scope generate, "muxbits[30]" "muxbits[30]" 2 290, 2 290, S_0x22690e0; + .timescale -9 -12; +P_0x237a288 .param/l "i" 2 290, +C4<011110>; +L_0x24b43e0/d .functor OR 1, L_0x24b44e0, L_0x24b4580, C4<0>, C4<0>; +L_0x24b43e0 .delay (20000,20000,20000) L_0x24b43e0/d; +v0x238fc20_0 .net *"_s15", 0 0, L_0x24b44e0; 1 drivers +v0x238f680_0 .net *"_s16", 0 0, L_0x24b4580; 1 drivers +S_0x238b540 .scope module, "ZeroMux" "FourInMux" 2 292, 2 24, S_0x2385000; + .timescale -9 -12; +L_0x24b1b50/d .functor NOT 1, L_0x24b2420, C4<0>, C4<0>, C4<0>; +L_0x24b1b50 .delay (10000,10000,10000) L_0x24b1b50/d; +L_0x24b1c40/d .functor NOT 1, L_0x24b2550, C4<0>, C4<0>, C4<0>; +L_0x24b1c40 .delay (10000,10000,10000) L_0x24b1c40/d; +L_0x24b1ce0/d .functor NAND 1, L_0x24b1b50, L_0x24b1c40, L_0x24b2680, C4<1>; +L_0x24b1ce0 .delay (10000,10000,10000) L_0x24b1ce0/d; +L_0x24b1e20/d .functor NAND 1, L_0x24b2420, L_0x24b1c40, L_0x24b2720, C4<1>; +L_0x24b1e20 .delay (10000,10000,10000) L_0x24b1e20/d; +L_0x24b1f10/d .functor NAND 1, L_0x24b1b50, L_0x24b2550, L_0x24b27c0, C4<1>; +L_0x24b1f10 .delay (10000,10000,10000) L_0x24b1f10/d; +L_0x24b2030/d .functor NAND 1, L_0x24b2420, L_0x24b2550, L_0x24b41b0, C4<1>; +L_0x24b2030 .delay (10000,10000,10000) L_0x24b2030/d; +L_0x24b2170/d .functor NAND 1, L_0x24b1ce0, L_0x24b1e20, L_0x24b1f10, L_0x24b2030; +L_0x24b2170 .delay (10000,10000,10000) L_0x24b2170/d; +v0x238bae0_0 .net "S0", 0 0, L_0x24b2420; 1 drivers +v0x238d2a0_0 .net "S1", 0 0, L_0x24b2550; 1 drivers +v0x238d000_0 .net "in0", 0 0, L_0x24b2680; 1 drivers +v0x238d0a0_0 .net "in1", 0 0, L_0x24b2720; 1 drivers +v0x238cb00_0 .net "in2", 0 0, L_0x24b27c0; 1 drivers +v0x238cba0_0 .net "in3", 0 0, L_0x24b41b0; 1 drivers +v0x238e840_0 .net "nS0", 0 0, L_0x24b1b50; 1 drivers +v0x238e8c0_0 .net "nS1", 0 0, L_0x24b1c40; 1 drivers +v0x238e5c0_0 .net "out", 0 0, L_0x24b2170; 1 drivers +v0x238e660_0 .net "out0", 0 0, L_0x24b1ce0; 1 drivers +v0x238e0e0_0 .net "out1", 0 0, L_0x24b1e20; 1 drivers +v0x238fe00_0 .net "out2", 0 0, L_0x24b1f10; 1 drivers +v0x238fb80_0 .net "out3", 0 0, L_0x24b2030; 1 drivers +S_0x2389140 .scope module, "OneMux" "FourInMux" 2 293, 2 24, S_0x2385000; + .timescale -9 -12; +L_0x24b2090/d .functor NOT 1, L_0x24b3740, C4<0>, C4<0>, C4<0>; +L_0x24b2090 .delay (10000,10000,10000) L_0x24b2090/d; +L_0x24b2f00/d .functor NOT 1, L_0x24b3870, C4<0>, C4<0>, C4<0>; +L_0x24b2f00 .delay (10000,10000,10000) L_0x24b2f00/d; +L_0x24b2fa0/d .functor NAND 1, L_0x24b2090, L_0x24b2f00, L_0x24b39a0, C4<1>; +L_0x24b2fa0 .delay (10000,10000,10000) L_0x24b2fa0/d; +L_0x24b30e0/d .functor NAND 1, L_0x24b3740, L_0x24b2f00, L_0x24b3a40, C4<1>; +L_0x24b30e0 .delay (10000,10000,10000) L_0x24b30e0/d; +L_0x24b3200/d .functor NAND 1, L_0x24b2090, L_0x24b3870, L_0x24b3ae0, C4<1>; +L_0x24b3200 .delay (10000,10000,10000) L_0x24b3200/d; +L_0x24b3350/d .functor NAND 1, L_0x24b3740, L_0x24b3870, L_0x24b3bd0, C4<1>; +L_0x24b3350 .delay (10000,10000,10000) L_0x24b3350/d; +L_0x24b3490/d .functor NAND 1, L_0x24b2fa0, L_0x24b30e0, L_0x24b3200, L_0x24b3350; +L_0x24b3490 .delay (10000,10000,10000) L_0x24b3490/d; +v0x23874a0_0 .net "S0", 0 0, L_0x24b3740; 1 drivers +v0x2388ec0_0 .net "S1", 0 0, L_0x24b3870; 1 drivers +v0x2388f40_0 .net "in0", 0 0, L_0x24b39a0; 1 drivers +v0x23889c0_0 .net "in1", 0 0, L_0x24b3a40; 1 drivers +v0x2388a60_0 .net "in2", 0 0, L_0x24b3ae0; 1 drivers +v0x238a700_0 .net "in3", 0 0, L_0x24b3bd0; 1 drivers +v0x238a7a0_0 .net "nS0", 0 0, L_0x24b2090; 1 drivers +v0x238a480_0 .net "nS1", 0 0, L_0x24b2f00; 1 drivers +v0x238a520_0 .net "out", 0 0, L_0x24b3490; 1 drivers +v0x2389f80_0 .net "out0", 0 0, L_0x24b2fa0; 1 drivers +v0x238a000_0 .net "out1", 0 0, L_0x24b30e0; 1 drivers +v0x238bcc0_0 .net "out2", 0 0, L_0x24b3200; 1 drivers +v0x238ba40_0 .net "out3", 0 0, L_0x24b3350; 1 drivers +S_0x2384d60 .scope module, "TwoMux" "TwoInMux" 2 294, 2 8, S_0x2385000; + .timescale -9 -12; +L_0x24b3cc0/d .functor NOT 1, L_0x24b55e0, C4<0>, C4<0>, C4<0>; +L_0x24b3cc0 .delay (10000,10000,10000) L_0x24b3cc0/d; +L_0x24b3db0/d .functor AND 1, L_0x24b5680, L_0x24b3cc0, C4<1>, C4<1>; +L_0x24b3db0 .delay (20000,20000,20000) L_0x24b3db0/d; +L_0x24b3ea0/d .functor AND 1, L_0x24b4250, L_0x24b55e0, C4<1>, C4<1>; +L_0x24b3ea0 .delay (20000,20000,20000) L_0x24b3ea0/d; +L_0x24b3f90/d .functor OR 1, L_0x24b3db0, L_0x24b3ea0, C4<0>, C4<0>; +L_0x24b3f90 .delay (20000,20000,20000) L_0x24b3f90/d; +v0x23865c0_0 .net "S", 0 0, L_0x24b55e0; 1 drivers +v0x2386340_0 .net "in0", 0 0, L_0x24b5680; 1 drivers +v0x23863e0_0 .net "in1", 0 0, L_0x24b4250; 1 drivers +v0x2387b80_0 .net "nS", 0 0, L_0x24b3cc0; 1 drivers +v0x2387c00_0 .net "out0", 0 0, L_0x24b3db0; 1 drivers +v0x2387900_0 .net "out1", 0 0, L_0x24b3ea0; 1 drivers +v0x2387400_0 .net "outfinal", 0 0, L_0x24b3f90; 1 drivers +S_0x22747a0 .scope generate, "muxbits[31]" "muxbits[31]" 2 290, 2 290, S_0x22690e0; + .timescale -9 -12; +P_0x2165518 .param/l "i" 2 290, +C4<011111>; +L_0x24b6480/d .functor OR 1, L_0x24b65c0, L_0x24b6660, C4<0>, C4<0>; +L_0x24b6480 .delay (20000,20000,20000) L_0x24b6480/d; +v0x2383a60_0 .net *"_s15", 0 0, L_0x24b65c0; 1 drivers +v0x23837c0_0 .net *"_s16", 0 0, L_0x24b6660; 1 drivers +S_0x237e340 .scope module, "ZeroMux" "FourInMux" 2 292, 2 24, S_0x22747a0; + .timescale -9 -12; +L_0x24b4670/d .functor NOT 1, L_0x24b4f40, C4<0>, C4<0>, C4<0>; +L_0x24b4670 .delay (10000,10000,10000) L_0x24b4670/d; +L_0x24b4760/d .functor NOT 1, L_0x24b5070, C4<0>, C4<0>, C4<0>; +L_0x24b4760 .delay (10000,10000,10000) L_0x24b4760/d; +L_0x24b4800/d .functor NAND 1, L_0x24b4670, L_0x24b4760, L_0x24b51a0, C4<1>; +L_0x24b4800 .delay (10000,10000,10000) L_0x24b4800/d; +L_0x24b4940/d .functor NAND 1, L_0x24b4f40, L_0x24b4760, L_0x24b5240, C4<1>; +L_0x24b4940 .delay (10000,10000,10000) L_0x24b4940/d; +L_0x24b4a30/d .functor NAND 1, L_0x24b4670, L_0x24b5070, L_0x24b52e0, C4<1>; +L_0x24b4a30 .delay (10000,10000,10000) L_0x24b4a30/d; +L_0x24b4b20/d .functor NAND 1, L_0x24b4f40, L_0x24b5070, L_0x24b53d0, C4<1>; +L_0x24b4b20 .delay (10000,10000,10000) L_0x24b4b20/d; +L_0x24b4c90/d .functor NAND 1, L_0x24b4800, L_0x24b4940, L_0x24b4a30, L_0x24b4b20; +L_0x24b4c90 .delay (10000,10000,10000) L_0x24b4c90/d; +v0x237cb80_0 .net "S0", 0 0, L_0x24b4f40; 1 drivers +v0x237e0c0_0 .net "S1", 0 0, L_0x24b5070; 1 drivers +v0x237e160_0 .net "in0", 0 0, L_0x24b51a0; 1 drivers +v0x237f920_0 .net "in1", 0 0, L_0x24b5240; 1 drivers +v0x237f660_0 .net "in2", 0 0, L_0x24b52e0; 1 drivers +v0x237f700_0 .net "in3", 0 0, L_0x24b53d0; 1 drivers +v0x2380ec0_0 .net "nS0", 0 0, L_0x24b4670; 1 drivers +v0x2380f60_0 .net "nS1", 0 0, L_0x24b4760; 1 drivers +v0x2380c40_0 .net "out", 0 0, L_0x24b4c90; 1 drivers +v0x2380cc0_0 .net "out0", 0 0, L_0x24b4800; 1 drivers +v0x2382480_0 .net "out1", 0 0, L_0x24b4940; 1 drivers +v0x2382520_0 .net "out2", 0 0, L_0x24b4a30; 1 drivers +v0x2382270_0 .net "out3", 0 0, L_0x24b4b20; 1 drivers +S_0x23773d0 .scope module, "OneMux" "FourInMux" 2 293, 2 24, S_0x22747a0; + .timescale -9 -12; +L_0x24b54c0/d .functor NOT 1, L_0x24b5770, C4<0>, C4<0>, C4<0>; +L_0x24b54c0 .delay (10000,10000,10000) L_0x24b54c0/d; +L_0x24b6b60/d .functor NOT 1, L_0x24b58a0, C4<0>, C4<0>, C4<0>; +L_0x24b6b60 .delay (10000,10000,10000) L_0x24b6b60/d; +L_0x24b6c00/d .functor NAND 1, L_0x24b54c0, L_0x24b6b60, L_0x24b59d0, C4<1>; +L_0x24b6c00 .delay (10000,10000,10000) L_0x24b6c00/d; +L_0x24b6d40/d .functor NAND 1, L_0x24b5770, L_0x24b6b60, L_0x24b5a70, C4<1>; +L_0x24b6d40 .delay (10000,10000,10000) L_0x24b6d40/d; +L_0x24b6e30/d .functor NAND 1, L_0x24b54c0, L_0x24b58a0, L_0x24b5b10, C4<1>; +L_0x24b6e30 .delay (10000,10000,10000) L_0x24b6e30/d; +L_0x24b6f20/d .functor NAND 1, L_0x24b5770, L_0x24b58a0, L_0x24b5c00, C4<1>; +L_0x24b6f20 .delay (10000,10000,10000) L_0x24b6f20/d; +L_0x24b7090/d .functor NAND 1, L_0x24b6c00, L_0x24b6d40, L_0x24b6e30, L_0x24b6f20; +L_0x24b7090 .delay (10000,10000,10000) L_0x24b7090/d; +v0x2377720_0 .net "S0", 0 0, L_0x24b5770; 1 drivers +v0x2378c40_0 .net "S1", 0 0, L_0x24b58a0; 1 drivers +v0x2378cc0_0 .net "in0", 0 0, L_0x24b59d0; 1 drivers +v0x23789c0_0 .net "in1", 0 0, L_0x24b5a70; 1 drivers +v0x2378a60_0 .net "in2", 0 0, L_0x24b5b10; 1 drivers +v0x237a200_0 .net "in3", 0 0, L_0x24b5c00; 1 drivers +v0x2379f60_0 .net "nS0", 0 0, L_0x24b54c0; 1 drivers +v0x237a000_0 .net "nS1", 0 0, L_0x24b6b60; 1 drivers +v0x237b7c0_0 .net "out", 0 0, L_0x24b7090; 1 drivers +v0x237b840_0 .net "out0", 0 0, L_0x24b6c00; 1 drivers +v0x237b5a0_0 .net "out1", 0 0, L_0x24b6d40; 1 drivers +v0x237cd80_0 .net "out2", 0 0, L_0x24b6e30; 1 drivers +v0x237cae0_0 .net "out3", 0 0, L_0x24b6f20; 1 drivers +S_0x2285c40 .scope module, "TwoMux" "TwoInMux" 2 294, 2 8, S_0x22747a0; + .timescale -9 -12; +L_0x24b5cf0/d .functor NOT 1, L_0x24b6160, C4<0>, C4<0>, C4<0>; +L_0x24b5cf0 .delay (10000,10000,10000) L_0x24b5cf0/d; +L_0x24b5da0/d .functor AND 1, L_0x24b6200, L_0x24b5cf0, C4<1>, C4<1>; +L_0x24b5da0 .delay (20000,20000,20000) L_0x24b5da0/d; +L_0x24b5e90/d .functor AND 1, L_0x24b62f0, L_0x24b6160, C4<1>, C4<1>; +L_0x24b5e90 .delay (20000,20000,20000) L_0x24b5e90/d; +L_0x24b5f80/d .functor OR 1, L_0x24b5da0, L_0x24b5e90, C4<0>, C4<0>; +L_0x24b5f80 .delay (20000,20000,20000) L_0x24b5f80/d; +v0x2117b80_0 .net "S", 0 0, L_0x24b6160; 1 drivers +v0x2374490_0 .net "in0", 0 0, L_0x24b6200; 1 drivers +v0x2376170_0 .net "in1", 0 0, L_0x24b62f0; 1 drivers +v0x23761f0_0 .net "nS", 0 0, L_0x24b5cf0; 1 drivers +v0x2375f20_0 .net "out0", 0 0, L_0x24b5da0; 1 drivers +v0x23759f0_0 .net "out1", 0 0, L_0x24b5e90; 1 drivers +v0x2377680_0 .net "outfinal", 0 0, L_0x24b5f80; 1 drivers +S_0x226ec40 .scope module, "testBasicFunctions" "testBasicFunctions" 3 6; + .timescale -9 -12; +v0x2468770_0 .var "A", 0 0; +v0x2468810_0 .net "AddSubSLTSum", 0 0, L_0x2525bc0; 1 drivers +v0x2468890_0 .net "AndNandOut", 0 0, L_0x25265f0; 1 drivers +v0x2468910_0 .var "B", 0 0; +v0x2468a20_0 .var "Command", 2 0; +v0x2468aa0_0 .net "OrNorXorOut", 0 0, L_0x2527800; 1 drivers +v0x2468b20_0 .var "S0", 0 0; +v0x2468ba0_0 .var "S1", 0 0; +v0x2468c70_0 .var "carryin", 0 0; +v0x2468d20_0 .net "carryout", 0 0, L_0x2525f60; 1 drivers +v0x2468dd0_0 .var "in0", 0 0; +v0x2468e80_0 .var "in1", 0 0; +v0x2468fa0_0 .var "in2", 0 0; +v0x2469050_0 .var "in3", 0 0; +v0x2469180_0 .net "muxout", 0 0, L_0x2522210; 1 drivers +v0x2469230_0 .net "subtract", 0 0, L_0x25258b0; 1 drivers +S_0x2467e60 .scope module, "testmux" "FourInMux" 3 20, 2 24, S_0x226ec40; + .timescale -9 -12; +L_0x2492610/d .functor NOT 1, v0x2468b20_0, C4<0>, C4<0>, C4<0>; +L_0x2492610 .delay (10000,10000,10000) L_0x2492610/d; +L_0x24926b0/d .functor NOT 1, v0x2468ba0_0, C4<0>, C4<0>, C4<0>; +L_0x24926b0 .delay (10000,10000,10000) L_0x24926b0/d; +L_0x24927a0/d .functor NAND 1, L_0x2492610, L_0x24926b0, v0x2468dd0_0, C4<1>; +L_0x24927a0 .delay (10000,10000,10000) L_0x24927a0/d; +L_0x2492930/d .functor NAND 1, v0x2468b20_0, L_0x24926b0, v0x2468e80_0, C4<1>; +L_0x2492930 .delay (10000,10000,10000) L_0x2492930/d; +L_0x2521f20/d .functor NAND 1, L_0x2492610, v0x2468ba0_0, v0x2468fa0_0, C4<1>; +L_0x2521f20 .delay (10000,10000,10000) L_0x2521f20/d; +L_0x2522010/d .functor NAND 1, v0x2468b20_0, v0x2468ba0_0, v0x2469050_0, C4<1>; +L_0x2522010 .delay (10000,10000,10000) L_0x2522010/d; +L_0x2522210/d .functor NAND 1, L_0x24927a0, L_0x2492930, L_0x2521f20, L_0x2522010; +L_0x2522210 .delay (10000,10000,10000) L_0x2522210/d; +v0x2467f50_0 .net "S0", 0 0, v0x2468b20_0; 1 drivers +v0x2468010_0 .net "S1", 0 0, v0x2468ba0_0; 1 drivers +v0x24680b0_0 .net "in0", 0 0, v0x2468dd0_0; 1 drivers +v0x2468150_0 .net "in1", 0 0, v0x2468e80_0; 1 drivers +v0x24681d0_0 .net "in2", 0 0, v0x2468fa0_0; 1 drivers +v0x2468270_0 .net "in3", 0 0, v0x2469050_0; 1 drivers +v0x2468310_0 .net "nS0", 0 0, L_0x2492610; 1 drivers +v0x24683b0_0 .net "nS1", 0 0, L_0x24926b0; 1 drivers +v0x2468450_0 .alias "out", 0 0, v0x2469180_0; +v0x24684f0_0 .net "out0", 0 0, L_0x24927a0; 1 drivers +v0x2468590_0 .net "out1", 0 0, L_0x2492930; 1 drivers +v0x2468630_0 .net "out2", 0 0, L_0x2521f20; 1 drivers +v0x24686d0_0 .net "out3", 0 0, L_0x2522010; 1 drivers +S_0x2466e50 .scope module, "testadd" "MiddleAddSubSLT" 3 22, 2 89, S_0x226ec40; + .timescale -9 -12; +L_0x2525140/d .functor NOT 1, v0x2468910_0, C4<0>, C4<0>, C4<0>; +L_0x2525140 .delay (10000,10000,10000) L_0x2525140/d; +L_0x2525770/d .functor NOT 1, L_0x2525810, C4<0>, C4<0>, C4<0>; +L_0x2525770 .delay (10000,10000,10000) L_0x2525770/d; +L_0x25258b0/d .functor AND 1, L_0x25259f0, L_0x2525770, C4<1>, C4<1>; +L_0x25258b0 .delay (20000,20000,20000) L_0x25258b0/d; +L_0x2525a90/d .functor XOR 1, v0x2468770_0, L_0x25254b0, C4<0>, C4<0>; +L_0x2525a90 .delay (40000,40000,40000) L_0x2525a90/d; +L_0x2525bc0/d .functor XOR 1, L_0x2525a90, v0x2468c70_0, C4<0>, C4<0>; +L_0x2525bc0 .delay (40000,40000,40000) L_0x2525bc0/d; +L_0x2525d50/d .functor AND 1, v0x2468770_0, L_0x25254b0, C4<1>, C4<1>; +L_0x2525d50 .delay (20000,20000,20000) L_0x2525d50/d; +L_0x2525ec0/d .functor AND 1, L_0x2525a90, v0x2468c70_0, C4<1>, C4<1>; +L_0x2525ec0 .delay (20000,20000,20000) L_0x2525ec0/d; +L_0x2525f60/d .functor OR 1, L_0x2525d50, L_0x2525ec0, C4<0>, C4<0>; +L_0x2525f60 .delay (20000,20000,20000) L_0x2525f60/d; +v0x24673f0_0 .net "A", 0 0, v0x2468770_0; 1 drivers +v0x24674c0_0 .net "AandB", 0 0, L_0x2525d50; 1 drivers +v0x2467560_0 .alias "AddSubSLTSum", 0 0, v0x2468810_0; +v0x2467600_0 .net "AxorB", 0 0, L_0x2525a90; 1 drivers +v0x2467680_0 .net "B", 0 0, v0x2468910_0; 1 drivers +v0x2467700_0 .net "BornB", 0 0, L_0x25254b0; 1 drivers +v0x24677c0_0 .net "CINandAxorB", 0 0, L_0x2525ec0; 1 drivers +v0x2467840_0 .net "Command", 2 0, v0x2468a20_0; 1 drivers +v0x2467960_0 .net *"_s3", 0 0, L_0x2525810; 1 drivers +v0x2467a00_0 .net *"_s5", 0 0, L_0x25259f0; 1 drivers +v0x2467b00_0 .net "carryin", 0 0, v0x2468c70_0; 1 drivers +v0x2467ba0_0 .alias "carryout", 0 0, v0x2468d20_0; +v0x2467c40_0 .net "nB", 0 0, L_0x2525140; 1 drivers +v0x2467cc0_0 .net "nCmd2", 0 0, L_0x2525770; 1 drivers +v0x2467dc0_0 .alias "subtract", 0 0, v0x2469230_0; +L_0x2525640 .part v0x2468a20_0, 0, 1; +L_0x2525810 .part v0x2468a20_0, 2, 1; +L_0x25259f0 .part v0x2468a20_0, 0, 1; +S_0x2466f40 .scope module, "mux0" "TwoInMux" 2 105, 2 8, S_0x2466e50; + .timescale -9 -12; +L_0x2525230/d .functor NOT 1, L_0x2525640, C4<0>, C4<0>, C4<0>; +L_0x2525230 .delay (10000,10000,10000) L_0x2525230/d; +L_0x25252d0/d .functor AND 1, v0x2468910_0, L_0x2525230, C4<1>, C4<1>; +L_0x25252d0 .delay (20000,20000,20000) L_0x25252d0/d; +L_0x25253c0/d .functor AND 1, L_0x2525140, L_0x2525640, C4<1>, C4<1>; +L_0x25253c0 .delay (20000,20000,20000) L_0x25253c0/d; +L_0x25254b0/d .functor OR 1, L_0x25252d0, L_0x25253c0, C4<0>, C4<0>; +L_0x25254b0 .delay (20000,20000,20000) L_0x25254b0/d; +v0x2467030_0 .net "S", 0 0, L_0x2525640; 1 drivers +v0x24670b0_0 .alias "in0", 0 0, v0x2467680_0; +v0x2467130_0 .alias "in1", 0 0, v0x2467c40_0; +v0x24671b0_0 .net "nS", 0 0, L_0x2525230; 1 drivers +v0x2467230_0 .net "out0", 0 0, L_0x25252d0; 1 drivers +v0x24672b0_0 .net "out1", 0 0, L_0x25253c0; 1 drivers +v0x2467370_0 .alias "outfinal", 0 0, v0x2467700_0; +S_0x24663e0 .scope module, "testand" "AndNand" 3 24, 2 48, S_0x226ec40; + .timescale -9 -12; +L_0x25260a0/d .functor NAND 1, v0x2468770_0, v0x2468910_0, C4<1>, C4<1>; +L_0x25260a0 .delay (10000,10000,10000) L_0x25260a0/d; +L_0x25261a0/d .functor NOT 1, L_0x25260a0, C4<0>, C4<0>, C4<0>; +L_0x25261a0 .delay (10000,10000,10000) L_0x25261a0/d; +v0x2466a00_0 .alias "A", 0 0, v0x24673f0_0; +v0x2466aa0_0 .net "AandB", 0 0, L_0x25261a0; 1 drivers +v0x2466b50_0 .net "AnandB", 0 0, L_0x25260a0; 1 drivers +v0x2466c00_0 .alias "AndNandOut", 0 0, v0x2468890_0; +v0x2466ce0_0 .alias "B", 0 0, v0x2467680_0; +v0x2466d90_0 .alias "Command", 2 0, v0x2467840_0; +L_0x2526770 .part v0x2468a20_0, 0, 1; +S_0x24664d0 .scope module, "potato" "TwoInMux" 2 60, 2 8, S_0x24663e0; + .timescale -9 -12; +L_0x25262d0/d .functor NOT 1, L_0x2526770, C4<0>, C4<0>, C4<0>; +L_0x25262d0 .delay (10000,10000,10000) L_0x25262d0/d; +L_0x2526390/d .functor AND 1, L_0x25261a0, L_0x25262d0, C4<1>, C4<1>; +L_0x2526390 .delay (20000,20000,20000) L_0x2526390/d; +L_0x25264a0/d .functor AND 1, L_0x25260a0, L_0x2526770, C4<1>, C4<1>; +L_0x25264a0 .delay (20000,20000,20000) L_0x25264a0/d; +L_0x25265f0/d .functor OR 1, L_0x2526390, L_0x25264a0, C4<0>, C4<0>; +L_0x25265f0 .delay (20000,20000,20000) L_0x25265f0/d; +v0x24665c0_0 .net "S", 0 0, L_0x2526770; 1 drivers +v0x2466660_0 .alias "in0", 0 0, v0x2466aa0_0; +v0x2466700_0 .alias "in1", 0 0, v0x2466b50_0; +v0x24667a0_0 .net "nS", 0 0, L_0x25262d0; 1 drivers +v0x2466820_0 .net "out0", 0 0, L_0x2526390; 1 drivers +v0x24668c0_0 .net "out1", 0 0, L_0x25264a0; 1 drivers +v0x2466960_0 .alias "outfinal", 0 0, v0x2468890_0; +S_0x2464f10 .scope module, "testor" "OrNorXor" 3 26, 2 64, S_0x226ec40; + .timescale -9 -12; +L_0x2526810/d .functor NOR 1, v0x2468770_0, v0x2468910_0, C4<0>, C4<0>; +L_0x2526810 .delay (10000,10000,10000) L_0x2526810/d; +L_0x25269e0/d .functor NOT 1, L_0x2526810, C4<0>, C4<0>, C4<0>; +L_0x25269e0 .delay (10000,10000,10000) L_0x25269e0/d; +L_0x2526b10/d .functor NAND 1, v0x2468770_0, v0x2468910_0, C4<1>, C4<1>; +L_0x2526b10 .delay (10000,10000,10000) L_0x2526b10/d; +L_0x2526ca0/d .functor NAND 1, L_0x2526b10, L_0x25269e0, C4<1>, C4<1>; +L_0x2526ca0 .delay (10000,10000,10000) L_0x2526ca0/d; +L_0x2526d90/d .functor NOT 1, L_0x2526ca0, C4<0>, C4<0>, C4<0>; +L_0x2526d90 .delay (10000,10000,10000) L_0x2526d90/d; +v0x2465d80_0 .alias "A", 0 0, v0x24673f0_0; +v0x2465e20_0 .net "AnandB", 0 0, L_0x2526b10; 1 drivers +v0x2465ec0_0 .net "AnorB", 0 0, L_0x2526810; 1 drivers +v0x2465f70_0 .net "AorB", 0 0, L_0x25269e0; 1 drivers +v0x2466050_0 .net "AxorB", 0 0, L_0x2526d90; 1 drivers +v0x24660d0_0 .alias "B", 0 0, v0x2467680_0; +v0x2466190_0 .alias "Command", 2 0, v0x2467840_0; +v0x2466210_0 .alias "OrNorXorOut", 0 0, v0x2468aa0_0; +v0x2466290_0 .net "XorNor", 0 0, L_0x25271f0; 1 drivers +v0x2466360_0 .net "nXor", 0 0, L_0x2526ca0; 1 drivers +L_0x2527370 .part v0x2468a20_0, 2, 1; +L_0x2527980 .part v0x2468a20_0, 0, 1; +S_0x2465810 .scope module, "mux0" "TwoInMux" 2 83, 2 8, S_0x2464f10; + .timescale -9 -12; +L_0x2526ed0/d .functor NOT 1, L_0x2527370, C4<0>, C4<0>, C4<0>; +L_0x2526ed0 .delay (10000,10000,10000) L_0x2526ed0/d; +L_0x2526f90/d .functor AND 1, L_0x2526d90, L_0x2526ed0, C4<1>, C4<1>; +L_0x2526f90 .delay (20000,20000,20000) L_0x2526f90/d; +L_0x25270a0/d .functor AND 1, L_0x2526810, L_0x2527370, C4<1>, C4<1>; +L_0x25270a0 .delay (20000,20000,20000) L_0x25270a0/d; +L_0x25271f0/d .functor OR 1, L_0x2526f90, L_0x25270a0, C4<0>, C4<0>; +L_0x25271f0 .delay (20000,20000,20000) L_0x25271f0/d; +v0x2465900_0 .net "S", 0 0, L_0x2527370; 1 drivers +v0x24659c0_0 .alias "in0", 0 0, v0x2466050_0; +v0x2465a60_0 .alias "in1", 0 0, v0x2465ec0_0; +v0x2465b00_0 .net "nS", 0 0, L_0x2526ed0; 1 drivers +v0x2465b80_0 .net "out0", 0 0, L_0x2526f90; 1 drivers +v0x2465c20_0 .net "out1", 0 0, L_0x25270a0; 1 drivers +v0x2465d00_0 .alias "outfinal", 0 0, v0x2466290_0; +S_0x2465390 .scope module, "mux1" "TwoInMux" 2 84, 2 8, S_0x2464f10; + .timescale -9 -12; +L_0x25256e0/d .functor NOT 1, L_0x2527980, C4<0>, C4<0>, C4<0>; +L_0x25256e0 .delay (10000,10000,10000) L_0x25256e0/d; +L_0x2527560/d .functor AND 1, L_0x25271f0, L_0x25256e0, C4<1>, C4<1>; +L_0x2527560 .delay (20000,20000,20000) L_0x2527560/d; +L_0x25276b0/d .functor AND 1, L_0x25269e0, L_0x2527980, C4<1>, C4<1>; +L_0x25276b0 .delay (20000,20000,20000) L_0x25276b0/d; +L_0x2527800/d .functor OR 1, L_0x2527560, L_0x25276b0, C4<0>, C4<0>; +L_0x2527800 .delay (20000,20000,20000) L_0x2527800/d; +v0x2465000_0 .net "S", 0 0, L_0x2527980; 1 drivers +v0x2465480_0 .alias "in0", 0 0, v0x2466290_0; +v0x2465500_0 .alias "in1", 0 0, v0x2465f70_0; +v0x2465580_0 .net "nS", 0 0, L_0x25256e0; 1 drivers +v0x2465630_0 .net "out0", 0 0, L_0x2527560; 1 drivers +v0x24656d0_0 .net "out1", 0 0, L_0x25276b0; 1 drivers +v0x2465770_0 .alias "outfinal", 0 0, v0x2468aa0_0; + .scope S_0x226ec40; T_0 ; - %vpi_call 2 150 "$dumpfile", "FullALU.vcd"; - %vpi_call 2 151 "$dumpvars"; - %vpi_call 2 153 "$display", "Test 4 Bit Adder Functionality"; - %vpi_call 2 155 "$display", " A | B |Command| Out|ExpectedOut|Cout|OF"; - %movi 8, 2, 32; - %set/v v0x2bc7660_0, 8, 32; - %movi 8, 4, 32; - %set/v v0x2bc7860_0, 8, 32; - %set/v v0x2bc78e0_0, 0, 3; + %vpi_call 3 28 "$dumpfile", "SmallALU.vcd"; + %vpi_call 3 29 "$dumpvars"; + %vpi_call 3 44 "$display", "Adder/Subtractor"; + %vpi_call 3 45 "$display", "A B | Command |Out|ExpectOut|Carryout-Add"; + %set/v v0x2468770_0, 1, 1; + %set/v v0x2468910_0, 1, 1; + %set/v v0x2468a20_0, 0, 3; + %set/v v0x2468c70_0, 0, 1; %delay 1000000, 0; - %vpi_call 2 159 "$display", "%b | %b | %b | %b | Expect 0110| %b | %b ", v0x2bc7660_0, v0x2bc7860_0, v0x2bc78e0_0, v0x2bc76e0_0, v0x2bc7be0_0, v0x2bc7c60_0; - %movi 8, 1, 32; - %set/v v0x2bc7660_0, 8, 32; - %movi 8, 6, 32; - %set/v v0x2bc7860_0, 8, 32; - %set/v v0x2bc78e0_0, 0, 3; + %vpi_call 3 48 "$display", "%b %b | %b | %b | 0 | %b", v0x2468770_0, v0x2468910_0, v0x2468a20_0, v0x2468810_0, v0x2468d20_0; + %set/v v0x2468770_0, 1, 1; + %set/v v0x2468910_0, 0, 1; + %set/v v0x2468a20_0, 0, 3; + %set/v v0x2468c70_0, 0, 1; %delay 1000000, 0; - %vpi_call 2 163 "$display", "%b | %b | %b | %b | Expect 0111| %b | %b ", v0x2bc7660_0, v0x2bc7860_0, v0x2bc78e0_0, v0x2bc76e0_0, v0x2bc7be0_0, v0x2bc7c60_0; - %movi 8, 5, 32; - %set/v v0x2bc7660_0, 8, 32; - %movi 8, 13, 32; - %set/v v0x2bc7860_0, 8, 32; - %set/v v0x2bc78e0_0, 0, 3; + %vpi_call 3 50 "$display", "%b %b | %b | %b | 1 | %b", v0x2468770_0, v0x2468910_0, v0x2468a20_0, v0x2468810_0, v0x2468d20_0; + %set/v v0x2468770_0, 0, 1; + %set/v v0x2468910_0, 1, 1; + %set/v v0x2468a20_0, 0, 3; + %set/v v0x2468c70_0, 0, 1; %delay 1000000, 0; - %vpi_call 2 167 "$display", "%b | %b | %b | %b | Expect 0010| %b | %b ", v0x2bc7660_0, v0x2bc7860_0, v0x2bc78e0_0, v0x2bc76e0_0, v0x2bc7be0_0, v0x2bc7c60_0; - %movi 8, 2, 32; - %set/v v0x2bc7660_0, 8, 32; - %movi 8, 15, 32; - %set/v v0x2bc7860_0, 8, 32; - %set/v v0x2bc78e0_0, 0, 3; + %vpi_call 3 52 "$display", "%b %b | %b | %b | 1 | %b", v0x2468770_0, v0x2468910_0, v0x2468a20_0, v0x2468810_0, v0x2468d20_0; + %set/v v0x2468770_0, 0, 1; + %set/v v0x2468910_0, 0, 1; + %set/v v0x2468a20_0, 0, 3; + %set/v v0x2468c70_0, 0, 1; %delay 1000000, 0; - %vpi_call 2 171 "$display", "%b | %b | %b | %b | Expect 0001| %b | %b ", v0x2bc7660_0, v0x2bc7860_0, v0x2bc78e0_0, v0x2bc76e0_0, v0x2bc7be0_0, v0x2bc7c60_0; - %movi 8, 8, 32; - %set/v v0x2bc7660_0, 8, 32; - %movi 8, 3, 32; - %set/v v0x2bc7860_0, 8, 32; - %set/v v0x2bc78e0_0, 0, 3; - %delay 1000000, 0; - %vpi_call 2 175 "$display", "%b | %b | %b | %b | Expect 1011| %b | %b ", v0x2bc7660_0, v0x2bc7860_0, v0x2bc78e0_0, v0x2bc76e0_0, v0x2bc7be0_0, v0x2bc7c60_0; - %movi 8, 12, 32; - %set/v v0x2bc7660_0, 8, 32; - %movi 8, 2, 32; - %set/v v0x2bc7860_0, 8, 32; - %set/v v0x2bc78e0_0, 0, 3; - %delay 1000000, 0; - %vpi_call 2 179 "$display", "%b | %b | %b | %b | Expect 1110| %b | %b ", v0x2bc7660_0, v0x2bc7860_0, v0x2bc78e0_0, v0x2bc76e0_0, v0x2bc7be0_0, v0x2bc7c60_0; - %movi 8, 11, 32; - %set/v v0x2bc7660_0, 8, 32; - %movi 8, 5, 32; - %set/v v0x2bc7860_0, 8, 32; - %set/v v0x2bc78e0_0, 0, 3; - %delay 1000000, 0; - %vpi_call 2 183 "$display", "%b | %b | %b | %b | Expect 0110| %b | %b ", v0x2bc7660_0, v0x2bc7860_0, v0x2bc78e0_0, v0x2bc76e0_0, v0x2bc7be0_0, v0x2bc7c60_0; - %movi 8, 7, 32; - %set/v v0x2bc7660_0, 8, 32; - %movi 8, 9, 32; - %set/v v0x2bc7860_0, 8, 32; - %set/v v0x2bc78e0_0, 0, 3; - %delay 1000000, 0; - %vpi_call 2 187 "$display", "%b | %b | %b | %b | Expect 0000| %b | %b ", v0x2bc7660_0, v0x2bc7860_0, v0x2bc78e0_0, v0x2bc76e0_0, v0x2bc7be0_0, v0x2bc7c60_0; - %movi 8, 13, 32; - %set/v v0x2bc7660_0, 8, 32; - %movi 8, 12, 32; - %set/v v0x2bc7860_0, 8, 32; - %set/v v0x2bc78e0_0, 0, 3; - %delay 1000000, 0; - %vpi_call 2 191 "$display", "%b | %b | %b | %b | Expect 1001| %b | %b ", v0x2bc7660_0, v0x2bc7860_0, v0x2bc78e0_0, v0x2bc76e0_0, v0x2bc7be0_0, v0x2bc7c60_0; - %movi 8, 14, 32; - %set/v v0x2bc7660_0, 8, 32; - %movi 8, 10, 32; - %set/v v0x2bc7860_0, 8, 32; - %set/v v0x2bc78e0_0, 0, 3; - %delay 1000000, 0; - %vpi_call 2 195 "$display", "%b | %b | %b | %b | Expect 1000| %b | %b ", v0x2bc7660_0, v0x2bc7860_0, v0x2bc78e0_0, v0x2bc76e0_0, v0x2bc7be0_0, v0x2bc7c60_0; - %movi 8, 5, 32; - %set/v v0x2bc7660_0, 8, 32; - %movi 8, 6, 32; - %set/v v0x2bc7860_0, 8, 32; - %set/v v0x2bc78e0_0, 0, 3; - %delay 1000000, 0; - %vpi_call 2 199 "$display", "%b | %b | %b | %b | Expect XXXX| %b | %b ", v0x2bc7660_0, v0x2bc7860_0, v0x2bc78e0_0, v0x2bc76e0_0, v0x2bc7be0_0, v0x2bc7c60_0; - %movi 8, 2, 32; - %set/v v0x2bc7660_0, 8, 32; - %movi 8, 7, 32; - %set/v v0x2bc7860_0, 8, 32; - %set/v v0x2bc78e0_0, 0, 3; - %delay 1000000, 0; - %vpi_call 2 203 "$display", "%b | %b | %b | %b | Expect XXXX| %b | %b ", v0x2bc7660_0, v0x2bc7860_0, v0x2bc78e0_0, v0x2bc76e0_0, v0x2bc7be0_0, v0x2bc7c60_0; - %movi 8, 7, 32; - %set/v v0x2bc7660_0, 8, 32; - %movi 8, 7, 32; - %set/v v0x2bc7860_0, 8, 32; - %set/v v0x2bc78e0_0, 0, 3; - %delay 1000000, 0; - %vpi_call 2 207 "$display", "%b | %b | %b | %b | Expect XXXX| %b | %b ", v0x2bc7660_0, v0x2bc7860_0, v0x2bc78e0_0, v0x2bc76e0_0, v0x2bc7be0_0, v0x2bc7c60_0; - %movi 8, 8, 32; - %set/v v0x2bc7660_0, 8, 32; - %movi 8, 15, 32; - %set/v v0x2bc7860_0, 8, 32; - %set/v v0x2bc78e0_0, 0, 3; - %delay 1000000, 0; - %vpi_call 2 211 "$display", "%b | %b | %b | %b | Expect XXXX| %b | %b ", v0x2bc7660_0, v0x2bc7860_0, v0x2bc78e0_0, v0x2bc76e0_0, v0x2bc7be0_0, v0x2bc7c60_0; - %movi 8, 8, 32; - %set/v v0x2bc7660_0, 8, 32; - %movi 8, 13, 32; - %set/v v0x2bc7860_0, 8, 32; - %set/v v0x2bc78e0_0, 0, 3; - %delay 1000000, 0; - %vpi_call 2 215 "$display", "%b | %b | %b | %b | Expect XXXX| %b | %b ", v0x2bc7660_0, v0x2bc7860_0, v0x2bc78e0_0, v0x2bc76e0_0, v0x2bc7be0_0, v0x2bc7c60_0; - %movi 8, 11, 32; - %set/v v0x2bc7660_0, 8, 32; - %movi 8, 12, 32; - %set/v v0x2bc7860_0, 8, 32; - %set/v v0x2bc78e0_0, 0, 3; - %delay 1000000, 0; - %vpi_call 2 219 "$display", "%b | %b | %b | %b | Expect XXXX| %b | %b ", v0x2bc7660_0, v0x2bc7860_0, v0x2bc78e0_0, v0x2bc76e0_0, v0x2bc7be0_0, v0x2bc7c60_0; - %vpi_call 2 221 "$display", "Test 4 Bit SLT Functionality"; - %vpi_call 2 223 "$display", " A | B |Command| Out|ExpectedOut|Cout|OF |SLTflag"; - %movi 8, 2, 32; - %set/v v0x2bc7660_0, 8, 32; - %movi 8, 4, 32; - %set/v v0x2bc7860_0, 8, 32; - %movi 8, 3, 3; - %set/v v0x2bc78e0_0, 8, 3; - %delay 1000000, 0; - %vpi_call 2 227 "$display", "%b | %b | %b | %b | Expect 1110| %b | %b | %b", v0x2bc7660_0, v0x2bc7860_0, v0x2bc78e0_0, v0x2bc76e0_0, v0x2bc7be0_0, v0x2bc7c60_0, v0x2bc7a60_0; - %movi 8, 4, 32; - %set/v v0x2bc7660_0, 8, 32; - %movi 8, 2, 32; - %set/v v0x2bc7860_0, 8, 32; - %movi 8, 3, 3; - %set/v v0x2bc78e0_0, 8, 3; + %vpi_call 3 54 "$display", "%b %b | %b | %b | 0 | %b", v0x2468770_0, v0x2468910_0, v0x2468a20_0, v0x2468810_0, v0x2468d20_0; + %vpi_call 3 56 "$display", "A B | Command |Out|ExpectOut|Carryout-Sub"; + %set/v v0x2468770_0, 1, 1; + %set/v v0x2468910_0, 1, 1; + %movi 8, 1, 3; + %set/v v0x2468a20_0, 8, 3; + %set/v v0x2468c70_0, 1, 1; %delay 1000000, 0; - %vpi_call 2 231 "$display", "%b | %b | %b | %b | Expect 0010| %b | %b | %b", v0x2bc7660_0, v0x2bc7860_0, v0x2bc78e0_0, v0x2bc76e0_0, v0x2bc7be0_0, v0x2bc7c60_0, v0x2bc7a60_0; - %movi 8, 14, 32; - %set/v v0x2bc7660_0, 8, 32; - %movi 8, 4, 32; - %set/v v0x2bc7860_0, 8, 32; - %movi 8, 3, 3; - %set/v v0x2bc78e0_0, 8, 3; + %vpi_call 3 58 "$display", "%b %b | %b | %b | 0 | %b", v0x2468770_0, v0x2468910_0, v0x2468a20_0, v0x2468810_0, v0x2468d20_0; + %set/v v0x2468770_0, 1, 1; + %set/v v0x2468910_0, 0, 1; + %movi 8, 1, 3; + %set/v v0x2468a20_0, 8, 3; + %set/v v0x2468c70_0, 1, 1; %delay 1000000, 0; - %vpi_call 2 235 "$display", "%b | %b | %b | %b | Expect 1010| %b | %b | %b", v0x2bc7660_0, v0x2bc7860_0, v0x2bc78e0_0, v0x2bc76e0_0, v0x2bc7be0_0, v0x2bc7c60_0, v0x2bc7a60_0; - %movi 8, 4, 32; - %set/v v0x2bc7660_0, 8, 32; - %movi 8, 14, 32; - %set/v v0x2bc7860_0, 8, 32; - %movi 8, 3, 3; - %set/v v0x2bc78e0_0, 8, 3; + %vpi_call 3 60 "$display", "%b %b | %b | %b | 1 | %b", v0x2468770_0, v0x2468910_0, v0x2468a20_0, v0x2468810_0, v0x2468d20_0; + %set/v v0x2468770_0, 0, 1; + %set/v v0x2468910_0, 1, 1; + %movi 8, 1, 3; + %set/v v0x2468a20_0, 8, 3; + %set/v v0x2468c70_0, 1, 1; %delay 1000000, 0; - %vpi_call 2 239 "$display", "%b | %b | %b | %b | Expect 0110| %b | %b | %b", v0x2bc7660_0, v0x2bc7860_0, v0x2bc78e0_0, v0x2bc76e0_0, v0x2bc7be0_0, v0x2bc7c60_0, v0x2bc7a60_0; - %movi 8, 14, 32; - %set/v v0x2bc7660_0, 8, 32; - %movi 8, 15, 32; - %set/v v0x2bc7860_0, 8, 32; - %movi 8, 3, 3; - %set/v v0x2bc78e0_0, 8, 3; + %vpi_call 3 62 "$display", "%b %b | %b | %b | 1 | %b", v0x2468770_0, v0x2468910_0, v0x2468a20_0, v0x2468810_0, v0x2468d20_0; + %set/v v0x2468770_0, 0, 1; + %set/v v0x2468910_0, 0, 1; + %movi 8, 1, 3; + %set/v v0x2468a20_0, 8, 3; + %set/v v0x2468c70_0, 1, 1; %delay 1000000, 0; - %vpi_call 2 243 "$display", "%b | %b | %b | %b | Expect 1111| %b | %b | %b", v0x2bc7660_0, v0x2bc7860_0, v0x2bc78e0_0, v0x2bc76e0_0, v0x2bc7be0_0, v0x2bc7c60_0, v0x2bc7a60_0; - %movi 8, 15, 32; - %set/v v0x2bc7660_0, 8, 32; - %movi 8, 14, 32; - %set/v v0x2bc7860_0, 8, 32; + %vpi_call 3 64 "$display", "%b %b | %b | %b | 0 | %b", v0x2468770_0, v0x2468910_0, v0x2468a20_0, v0x2468810_0, v0x2468d20_0; + %vpi_call 3 66 "$display", "A B | Command |Out|ExpectOut|Carryout-SLT"; + %set/v v0x2468770_0, 1, 1; + %set/v v0x2468910_0, 1, 1; %movi 8, 3, 3; - %set/v v0x2bc78e0_0, 8, 3; + %set/v v0x2468a20_0, 8, 3; + %set/v v0x2468c70_0, 1, 1; %delay 1000000, 0; - %vpi_call 2 247 "$display", "%b | %b | %b | %b | Expect 0001| %b | %b | %b", v0x2bc7660_0, v0x2bc7860_0, v0x2bc78e0_0, v0x2bc76e0_0, v0x2bc7be0_0, v0x2bc7c60_0, v0x2bc7a60_0; - %movi 8, 13, 32; - %set/v v0x2bc7660_0, 8, 32; - %movi 8, 13, 32; - %set/v v0x2bc7860_0, 8, 32; + %vpi_call 3 68 "$display", "%b %b | %b | %b | 0 | %b", v0x2468770_0, v0x2468910_0, v0x2468a20_0, v0x2468810_0, v0x2468d20_0; + %set/v v0x2468770_0, 1, 1; + %set/v v0x2468910_0, 0, 1; %movi 8, 3, 3; - %set/v v0x2bc78e0_0, 8, 3; + %set/v v0x2468a20_0, 8, 3; + %set/v v0x2468c70_0, 1, 1; %delay 1000000, 0; - %vpi_call 2 251 "$display", "%b | %b | %b | %b | Expect 0000| %b | %b | %b", v0x2bc7660_0, v0x2bc7860_0, v0x2bc78e0_0, v0x2bc76e0_0, v0x2bc7be0_0, v0x2bc7c60_0, v0x2bc7a60_0; - %movi 8, 5, 32; - %set/v v0x2bc7660_0, 8, 32; - %movi 8, 5, 32; - %set/v v0x2bc7860_0, 8, 32; + %vpi_call 3 70 "$display", "%b %b | %b | %b | 1 | %b", v0x2468770_0, v0x2468910_0, v0x2468a20_0, v0x2468810_0, v0x2468d20_0; + %set/v v0x2468770_0, 0, 1; + %set/v v0x2468910_0, 1, 1; %movi 8, 3, 3; - %set/v v0x2bc78e0_0, 8, 3; + %set/v v0x2468a20_0, 8, 3; + %set/v v0x2468c70_0, 1, 1; %delay 1000000, 0; - %vpi_call 2 255 "$display", "%b | %b | %b | %b | Expect 0000| %b | %b | %b", v0x2bc7660_0, v0x2bc7860_0, v0x2bc78e0_0, v0x2bc76e0_0, v0x2bc7be0_0, v0x2bc7c60_0, v0x2bc7a60_0; - %movi 8, 9, 32; - %set/v v0x2bc7660_0, 8, 32; - %movi 8, 5, 32; - %set/v v0x2bc7860_0, 8, 32; + %vpi_call 3 72 "$display", "%b %b | %b | %b | 1 | %b", v0x2468770_0, v0x2468910_0, v0x2468a20_0, v0x2468810_0, v0x2468d20_0; + %set/v v0x2468770_0, 0, 1; + %set/v v0x2468910_0, 0, 1; %movi 8, 3, 3; - %set/v v0x2bc78e0_0, 8, 3; + %set/v v0x2468a20_0, 8, 3; + %set/v v0x2468c70_0, 1, 1; %delay 1000000, 0; - %vpi_call 2 259 "$display", "%b | %b | %b | %b | Expect XXXX| %b | %b | %b", v0x2bc7660_0, v0x2bc7860_0, v0x2bc78e0_0, v0x2bc76e0_0, v0x2bc7be0_0, v0x2bc7c60_0, v0x2bc7a60_0; - %vpi_call 2 261 "$display", "Test 4 Bit AND/NAND Functionality"; - %vpi_call 2 263 "$display", " A | B |Command| Out |ExpectedOut-AND"; - %movi 8, 15, 32; - %set/v v0x2bc7660_0, 8, 32; - %movi 8, 15, 32; - %set/v v0x2bc7860_0, 8, 32; + %vpi_call 3 74 "$display", "%b %b | %b | %b | 0 | %b", v0x2468770_0, v0x2468910_0, v0x2468a20_0, v0x2468810_0, v0x2468d20_0; + %vpi_call 3 76 "$display", "A B |Command|Out|ExpectOut-AND"; + %set/v v0x2468770_0, 0, 1; + %set/v v0x2468910_0, 0, 1; %movi 8, 4, 3; - %set/v v0x2bc78e0_0, 8, 3; + %set/v v0x2468a20_0, 8, 3; %delay 1000000, 0; - %vpi_call 2 267 "$display", "%b | %b | %b | %b | 1111", v0x2bc7660_0, v0x2bc7860_0, v0x2bc78e0_0, v0x2bc77e0_0; - %movi 8, 15, 32; - %set/v v0x2bc7660_0, 8, 32; - %movi 8, 10, 32; - %set/v v0x2bc7860_0, 8, 32; + %vpi_call 3 78 "$display", "%b %b | %b | %b | 0", v0x2468770_0, v0x2468910_0, v0x2468a20_0, v0x2468890_0; + %set/v v0x2468770_0, 0, 1; + %set/v v0x2468910_0, 1, 1; %movi 8, 4, 3; - %set/v v0x2bc78e0_0, 8, 3; + %set/v v0x2468a20_0, 8, 3; %delay 1000000, 0; - %vpi_call 2 271 "$display", "%b | %b | %b | %b | 1010", v0x2bc7660_0, v0x2bc7860_0, v0x2bc78e0_0, v0x2bc77e0_0; - %movi 8, 15, 32; - %set/v v0x2bc7660_0, 8, 32; - %movi 8, 5, 32; - %set/v v0x2bc7860_0, 8, 32; + %vpi_call 3 80 "$display", "%b %b | %b | %b | 0", v0x2468770_0, v0x2468910_0, v0x2468a20_0, v0x2468890_0; + %set/v v0x2468770_0, 1, 1; + %set/v v0x2468910_0, 0, 1; %movi 8, 4, 3; - %set/v v0x2bc78e0_0, 8, 3; + %set/v v0x2468a20_0, 8, 3; %delay 1000000, 0; - %vpi_call 2 275 "$display", "%b | %b | %b | %b | 0101", v0x2bc7660_0, v0x2bc7860_0, v0x2bc78e0_0, v0x2bc77e0_0; - %movi 8, 15, 32; - %set/v v0x2bc7660_0, 8, 32; - %set/v v0x2bc7860_0, 0, 32; + %vpi_call 3 82 "$display", "%b %b | %b | %b | 0", v0x2468770_0, v0x2468910_0, v0x2468a20_0, v0x2468890_0; + %set/v v0x2468770_0, 1, 1; + %set/v v0x2468910_0, 1, 1; %movi 8, 4, 3; - %set/v v0x2bc78e0_0, 8, 3; + %set/v v0x2468a20_0, 8, 3; %delay 1000000, 0; - %vpi_call 2 279 "$display", "%b | %b | %b | %b | 0000", v0x2bc7660_0, v0x2bc7860_0, v0x2bc78e0_0, v0x2bc77e0_0; - %vpi_call 2 282 "$display", " A | B |Command| Out |ExpectedOut-NAND"; - %movi 8, 15, 32; - %set/v v0x2bc7660_0, 8, 32; - %movi 8, 15, 32; - %set/v v0x2bc7860_0, 8, 32; + %vpi_call 3 84 "$display", "%b %b | %b | %b | 1", v0x2468770_0, v0x2468910_0, v0x2468a20_0, v0x2468890_0; + %vpi_call 3 85 "$display", "A B |Command|Out|ExpectOut-NAND"; + %set/v v0x2468770_0, 0, 1; + %set/v v0x2468910_0, 0, 1; %movi 8, 5, 3; - %set/v v0x2bc78e0_0, 8, 3; + %set/v v0x2468a20_0, 8, 3; %delay 1000000, 0; - %vpi_call 2 286 "$display", "%b | %b | %b | %b | 0000", v0x2bc7660_0, v0x2bc7860_0, v0x2bc78e0_0, v0x2bc77e0_0; - %movi 8, 15, 32; - %set/v v0x2bc7660_0, 8, 32; - %movi 8, 10, 32; - %set/v v0x2bc7860_0, 8, 32; + %vpi_call 3 87 "$display", "%b %b | %b | %b | 1", v0x2468770_0, v0x2468910_0, v0x2468a20_0, v0x2468890_0; + %set/v v0x2468770_0, 0, 1; + %set/v v0x2468910_0, 1, 1; %movi 8, 5, 3; - %set/v v0x2bc78e0_0, 8, 3; + %set/v v0x2468a20_0, 8, 3; %delay 1000000, 0; - %vpi_call 2 290 "$display", "%b | %b | %b | %b | 0101", v0x2bc7660_0, v0x2bc7860_0, v0x2bc78e0_0, v0x2bc77e0_0; - %movi 8, 15, 32; - %set/v v0x2bc7660_0, 8, 32; - %movi 8, 5, 32; - %set/v v0x2bc7860_0, 8, 32; + %vpi_call 3 89 "$display", "%b %b | %b | %b | 1", v0x2468770_0, v0x2468910_0, v0x2468a20_0, v0x2468890_0; + %set/v v0x2468770_0, 1, 1; + %set/v v0x2468910_0, 0, 1; %movi 8, 5, 3; - %set/v v0x2bc78e0_0, 8, 3; + %set/v v0x2468a20_0, 8, 3; %delay 1000000, 0; - %vpi_call 2 294 "$display", "%b | %b | %b | %b | 1010", v0x2bc7660_0, v0x2bc7860_0, v0x2bc78e0_0, v0x2bc77e0_0; - %movi 8, 15, 32; - %set/v v0x2bc7660_0, 8, 32; - %set/v v0x2bc7860_0, 0, 32; + %vpi_call 3 91 "$display", "%b %b | %b | %b | 1", v0x2468770_0, v0x2468910_0, v0x2468a20_0, v0x2468890_0; + %set/v v0x2468770_0, 1, 1; + %set/v v0x2468910_0, 1, 1; %movi 8, 5, 3; - %set/v v0x2bc78e0_0, 8, 3; + %set/v v0x2468a20_0, 8, 3; + %delay 1000000, 0; + %vpi_call 3 93 "$display", "%b %b | %b | %b | 0", v0x2468770_0, v0x2468910_0, v0x2468a20_0, v0x2468890_0; + %vpi_call 3 95 "$display", "A B |Command|Out|ExpectOut-OR"; + %set/v v0x2468770_0, 1, 1; + %set/v v0x2468910_0, 1, 1; + %set/v v0x2468a20_0, 1, 3; %delay 1000000, 0; - %vpi_call 2 298 "$display", "%b | %b | %b | %b | 1111", v0x2bc7660_0, v0x2bc7860_0, v0x2bc78e0_0, v0x2bc77e0_0; - %vpi_call 2 300 "$display", "Test 4 Bit OR/NOR/XOR Functionality"; - %vpi_call 2 302 "$display", " A | B |Command | Out |ExpectedOut-OR"; - %movi 8, 10, 32; - %set/v v0x2bc7660_0, 8, 32; - %movi 8, 5, 32; - %set/v v0x2bc7860_0, 8, 32; - %set/v v0x2bc78e0_0, 1, 3; + %vpi_call 3 97 "$display", "%b %b | %b | %b | 1", v0x2468770_0, v0x2468910_0, v0x2468a20_0, v0x2468aa0_0; + %set/v v0x2468770_0, 1, 1; + %set/v v0x2468910_0, 0, 1; + %set/v v0x2468a20_0, 1, 3; %delay 1000000, 0; - %vpi_call 2 306 "$display", "%b | %b | %b | %b | 1111", v0x2bc7660_0, v0x2bc7860_0, v0x2bc78e0_0, v0x2bc79e0_0; - %movi 8, 15, 32; - %set/v v0x2bc7660_0, 8, 32; - %movi 8, 5, 32; - %set/v v0x2bc7860_0, 8, 32; - %set/v v0x2bc78e0_0, 1, 3; + %vpi_call 3 99 "$display", "%b %b | %b | %b | 1", v0x2468770_0, v0x2468910_0, v0x2468a20_0, v0x2468aa0_0; + %set/v v0x2468770_0, 0, 1; + %set/v v0x2468910_0, 1, 1; + %set/v v0x2468a20_0, 1, 3; %delay 1000000, 0; - %vpi_call 2 310 "$display", "%b | %b | %b | %b | 1111", v0x2bc7660_0, v0x2bc7860_0, v0x2bc78e0_0, v0x2bc79e0_0; - %movi 8, 11, 32; - %set/v v0x2bc7660_0, 8, 32; - %set/v v0x2bc7860_0, 0, 32; - %set/v v0x2bc78e0_0, 1, 3; + %vpi_call 3 101 "$display", "%b %b | %b | %b | 1", v0x2468770_0, v0x2468910_0, v0x2468a20_0, v0x2468aa0_0; + %set/v v0x2468770_0, 0, 1; + %set/v v0x2468910_0, 0, 1; + %set/v v0x2468a20_0, 1, 3; %delay 1000000, 0; - %vpi_call 2 314 "$display", "%b | %b | %b | %b | 1011", v0x2bc7660_0, v0x2bc7860_0, v0x2bc78e0_0, v0x2bc79e0_0; - %vpi_call 2 316 "$display", " A | B |Command | Out |ExpectedOut-NOR"; - %movi 8, 10, 32; - %set/v v0x2bc7660_0, 8, 32; - %movi 8, 5, 32; - %set/v v0x2bc7860_0, 8, 32; + %vpi_call 3 103 "$display", "%b %b | %b | %b | 0", v0x2468770_0, v0x2468910_0, v0x2468a20_0, v0x2468aa0_0; + %vpi_call 3 104 "$display", "A B |Command|Out|ExpectOut-NOR"; + %set/v v0x2468770_0, 1, 1; + %set/v v0x2468910_0, 1, 1; %movi 8, 6, 3; - %set/v v0x2bc78e0_0, 8, 3; + %set/v v0x2468a20_0, 8, 3; %delay 1000000, 0; - %vpi_call 2 320 "$display", "%b | %b | %b | %b | 0000", v0x2bc7660_0, v0x2bc7860_0, v0x2bc78e0_0, v0x2bc79e0_0; - %movi 8, 15, 32; - %set/v v0x2bc7660_0, 8, 32; - %movi 8, 5, 32; - %set/v v0x2bc7860_0, 8, 32; + %vpi_call 3 106 "$display", "%b %b | %b | %b | 0", v0x2468770_0, v0x2468910_0, v0x2468a20_0, v0x2468aa0_0; + %set/v v0x2468770_0, 1, 1; + %set/v v0x2468910_0, 0, 1; %movi 8, 6, 3; - %set/v v0x2bc78e0_0, 8, 3; + %set/v v0x2468a20_0, 8, 3; %delay 1000000, 0; - %vpi_call 2 324 "$display", "%b | %b | %b | %b | 0000", v0x2bc7660_0, v0x2bc7860_0, v0x2bc78e0_0, v0x2bc79e0_0; - %movi 8, 11, 32; - %set/v v0x2bc7660_0, 8, 32; - %set/v v0x2bc7860_0, 0, 32; + %vpi_call 3 108 "$display", "%b %b | %b | %b | 0", v0x2468770_0, v0x2468910_0, v0x2468a20_0, v0x2468aa0_0; + %set/v v0x2468770_0, 0, 1; + %set/v v0x2468910_0, 1, 1; %movi 8, 6, 3; - %set/v v0x2bc78e0_0, 8, 3; + %set/v v0x2468a20_0, 8, 3; %delay 1000000, 0; - %vpi_call 2 328 "$display", "%b | %b | %b | %b | 0100", v0x2bc7660_0, v0x2bc7860_0, v0x2bc78e0_0, v0x2bc79e0_0; - %vpi_call 2 330 "$display", " A | B |Command | Out |ExpectedOut-XOR"; - %movi 8, 10, 32; - %set/v v0x2bc7660_0, 8, 32; - %movi 8, 5, 32; - %set/v v0x2bc7860_0, 8, 32; - %movi 8, 2, 3; - %set/v v0x2bc78e0_0, 8, 3; + %vpi_call 3 110 "$display", "%b %b | %b | %b | 0", v0x2468770_0, v0x2468910_0, v0x2468a20_0, v0x2468aa0_0; + %set/v v0x2468770_0, 0, 1; + %set/v v0x2468910_0, 0, 1; + %movi 8, 6, 3; + %set/v v0x2468a20_0, 8, 3; %delay 1000000, 0; - %vpi_call 2 334 "$display", "%b | %b | %b | %b | 1111", v0x2bc7660_0, v0x2bc7860_0, v0x2bc78e0_0, v0x2bc79e0_0; - %movi 8, 15, 32; - %set/v v0x2bc7660_0, 8, 32; - %movi 8, 5, 32; - %set/v v0x2bc7860_0, 8, 32; + %vpi_call 3 112 "$display", "%b %b | %b | %b | 1", v0x2468770_0, v0x2468910_0, v0x2468a20_0, v0x2468aa0_0; + %vpi_call 3 113 "$display", "A B |Command|Out|ExpectOut-XOR"; + %set/v v0x2468770_0, 1, 1; + %set/v v0x2468910_0, 1, 1; %movi 8, 2, 3; - %set/v v0x2bc78e0_0, 8, 3; + %set/v v0x2468a20_0, 8, 3; %delay 1000000, 0; - %vpi_call 2 338 "$display", "%b | %b | %b | %b | 1010", v0x2bc7660_0, v0x2bc7860_0, v0x2bc78e0_0, v0x2bc79e0_0; - %movi 8, 11, 32; - %set/v v0x2bc7660_0, 8, 32; - %set/v v0x2bc7860_0, 0, 32; + %vpi_call 3 115 "$display", "%b %b | %b | %b | 0", v0x2468770_0, v0x2468910_0, v0x2468a20_0, v0x2468aa0_0; + %set/v v0x2468770_0, 1, 1; + %set/v v0x2468910_0, 0, 1; %movi 8, 2, 3; - %set/v v0x2bc78e0_0, 8, 3; - %delay 1000000, 0; - %vpi_call 2 342 "$display", "%b | %b | %b | %b | 1011", v0x2bc7660_0, v0x2bc7860_0, v0x2bc78e0_0, v0x2bc79e0_0; - %vpi_call 2 344 "$display", "Test 4 Bit ALU Functionality"; - %vpi_call 2 346 "$display", " A | B |Command | Out |ExpectedOut | COut | OF |SLT|Zero"; - %movi 8, 15, 32; - %set/v v0x2bc7660_0, 8, 32; - %movi 8, 15, 32; - %set/v v0x2bc7860_0, 8, 32; - %movi 8, 4, 3; - %set/v v0x2bc78e0_0, 8, 3; - %delay 1000000, 0; - %vpi_call 2 351 "$display", "%b | %b | %b - AND | %b | 1111 | %b | %b | %b | %b", v0x2bc7660_0, v0x2bc7860_0, v0x2bc78e0_0, v0x2bc7960_0, v0x2bc7be0_0, v0x2bc7c60_0, v0x2bc7a60_0, v0x2bc7760_0; - %movi 8, 15, 32; - %set/v v0x2bc7660_0, 8, 32; - %set/v v0x2bc7860_0, 0, 32; - %movi 8, 5, 3; - %set/v v0x2bc78e0_0, 8, 3; - %delay 1000000, 0; - %vpi_call 2 356 "$display", "%b | %b | %b - NAND | %b | 1111 | %b | %b | %b | %b", v0x2bc7660_0, v0x2bc7860_0, v0x2bc78e0_0, v0x2bc7960_0, v0x2bc7be0_0, v0x2bc7c60_0, v0x2bc7a60_0, v0x2bc7760_0; - %movi 8, 15, 32; - %set/v v0x2bc7660_0, 8, 32; - %movi 8, 5, 32; - %set/v v0x2bc7860_0, 8, 32; - %set/v v0x2bc78e0_0, 1, 3; - %delay 1000000, 0; - %vpi_call 2 361 "$display", "%b | %b | %b - OR | %b | 1111 | %b | %b | %b | %b", v0x2bc7660_0, v0x2bc7860_0, v0x2bc78e0_0, v0x2bc7960_0, v0x2bc7be0_0, v0x2bc7c60_0, v0x2bc7a60_0, v0x2bc7760_0; - %movi 8, 11, 32; - %set/v v0x2bc7660_0, 8, 32; - %set/v v0x2bc7860_0, 0, 32; - %movi 8, 6, 3; - %set/v v0x2bc78e0_0, 8, 3; + %set/v v0x2468a20_0, 8, 3; %delay 1000000, 0; - %vpi_call 2 366 "$display", "%b | %b | %b - NOR | %b | 0100 | %b | %b | %b | %b", v0x2bc7660_0, v0x2bc7860_0, v0x2bc78e0_0, v0x2bc7960_0, v0x2bc7be0_0, v0x2bc7c60_0, v0x2bc7a60_0, v0x2bc7760_0; - %movi 8, 11, 32; - %set/v v0x2bc7660_0, 8, 32; - %set/v v0x2bc7860_0, 0, 32; + %vpi_call 3 117 "$display", "%b %b | %b | %b | 1", v0x2468770_0, v0x2468910_0, v0x2468a20_0, v0x2468aa0_0; + %set/v v0x2468770_0, 0, 1; + %set/v v0x2468910_0, 1, 1; %movi 8, 2, 3; - %set/v v0x2bc78e0_0, 8, 3; - %delay 1000000, 0; - %vpi_call 2 371 "$display", "%b | %b | %b - XOR | %b | 1011 | %b | %b | %b | %b", v0x2bc7660_0, v0x2bc7860_0, v0x2bc78e0_0, v0x2bc7960_0, v0x2bc7be0_0, v0x2bc7c60_0, v0x2bc7a60_0, v0x2bc7760_0; - %movi 8, 2, 32; - %set/v v0x2bc7660_0, 8, 32; - %movi 8, 4, 32; - %set/v v0x2bc7860_0, 8, 32; - %set/v v0x2bc78e0_0, 0, 3; - %delay 1000000, 0; - %vpi_call 2 376 "$display", "%b | %b | %b - ADD | %b | 0110 | %b | %b | %b | %b", v0x2bc7660_0, v0x2bc7860_0, v0x2bc78e0_0, v0x2bc7960_0, v0x2bc7be0_0, v0x2bc7c60_0, v0x2bc7a60_0, v0x2bc7760_0; - %movi 8, 11, 32; - %set/v v0x2bc7660_0, 8, 32; - %movi 8, 12, 32; - %set/v v0x2bc7860_0, 8, 32; - %set/v v0x2bc78e0_0, 0, 3; - %delay 1000000, 0; - %vpi_call 2 380 "$display", "%b | %b | %b - ADD | %b | XXXX | %b | %b | %b | %b", v0x2bc7660_0, v0x2bc7860_0, v0x2bc78e0_0, v0x2bc7960_0, v0x2bc7be0_0, v0x2bc7c60_0, v0x2bc7a60_0, v0x2bc7760_0; - %movi 8, 2, 32; - %set/v v0x2bc7660_0, 8, 32; - %movi 8, 4, 32; - %set/v v0x2bc7860_0, 8, 32; - %movi 8, 1, 3; - %set/v v0x2bc78e0_0, 8, 3; - %delay 1000000, 0; - %vpi_call 2 385 "$display", "%b | %b | %b - SUB | %b | 1110 | %b | %b | %b | %b", v0x2bc7660_0, v0x2bc7860_0, v0x2bc78e0_0, v0x2bc7960_0, v0x2bc7be0_0, v0x2bc7c60_0, v0x2bc7a60_0, v0x2bc7760_0; - %movi 8, 9, 32; - %set/v v0x2bc7660_0, 8, 32; - %movi 8, 3, 32; - %set/v v0x2bc7860_0, 8, 32; - %movi 8, 1, 3; - %set/v v0x2bc78e0_0, 8, 3; - %delay 1000000, 0; - %vpi_call 2 389 "$display", "%b | %b | %b - SUB | %b | XXXX | %b | %b | %b | %b", v0x2bc7660_0, v0x2bc7860_0, v0x2bc78e0_0, v0x2bc7960_0, v0x2bc7be0_0, v0x2bc7c60_0, v0x2bc7a60_0, v0x2bc7760_0; - %movi 8, 4, 32; - %set/v v0x2bc7660_0, 8, 32; - %movi 8, 2, 32; - %set/v v0x2bc7860_0, 8, 32; - %movi 8, 3, 3; - %set/v v0x2bc78e0_0, 8, 3; - %delay 1000000, 0; - %vpi_call 2 395 "$display", "%b | %b | %b - SLT | %b | 0010 | %b | %b | %b | %b", v0x2bc7660_0, v0x2bc7860_0, v0x2bc78e0_0, v0x2bc7960_0, v0x2bc7be0_0, v0x2bc7c60_0, v0x2bc7a60_0, v0x2bc7760_0; - %movi 8, 9, 32; - %set/v v0x2bc7660_0, 8, 32; - %movi 8, 5, 32; - %set/v v0x2bc7860_0, 8, 32; - %movi 8, 3, 3; - %set/v v0x2bc78e0_0, 8, 3; + %set/v v0x2468a20_0, 8, 3; %delay 1000000, 0; - %vpi_call 2 399 "$display", "%b | %b | %b - SLT | %b | XXXX | %b | %b | %b | %b", v0x2bc7660_0, v0x2bc7860_0, v0x2bc78e0_0, v0x2bc7960_0, v0x2bc7be0_0, v0x2bc7c60_0, v0x2bc7a60_0, v0x2bc7760_0; - %set/v v0x2bc7660_0, 0, 32; - %movi 8, 15, 32; - %set/v v0x2bc7860_0, 8, 32; - %movi 8, 4, 3; - %set/v v0x2bc78e0_0, 8, 3; - %delay 1000000, 0; - %vpi_call 2 405 "$display", "%b | %b | %b - AND | %b | 0000 | %b | %b | %b | %b", v0x2bc7660_0, v0x2bc7860_0, v0x2bc78e0_0, v0x2bc7960_0, v0x2bc7be0_0, v0x2bc7c60_0, v0x2bc7a60_0, v0x2bc7760_0; - %movi 8, 15, 32; - %set/v v0x2bc7660_0, 8, 32; - %movi 8, 15, 32; - %set/v v0x2bc7860_0, 8, 32; - %movi 8, 5, 3; - %set/v v0x2bc78e0_0, 8, 3; - %delay 1000000, 0; - %vpi_call 2 408 "$display", "%b | %b | %b - NAND | %b | 0000 | %b | %b | %b | %b", v0x2bc7660_0, v0x2bc7860_0, v0x2bc78e0_0, v0x2bc7960_0, v0x2bc7be0_0, v0x2bc7c60_0, v0x2bc7a60_0, v0x2bc7760_0; - %set/v v0x2bc7660_0, 0, 32; - %set/v v0x2bc7860_0, 0, 32; - %set/v v0x2bc78e0_0, 1, 3; - %delay 1000000, 0; - %vpi_call 2 411 "$display", "%b | %b | %b - OR | %b | 0000 | %b | %b | %b | %b", v0x2bc7660_0, v0x2bc7860_0, v0x2bc78e0_0, v0x2bc7960_0, v0x2bc7be0_0, v0x2bc7c60_0, v0x2bc7a60_0, v0x2bc7760_0; - %movi 8, 11, 32; - %set/v v0x2bc7660_0, 8, 32; - %movi 8, 4, 32; - %set/v v0x2bc7860_0, 8, 32; - %movi 8, 6, 3; - %set/v v0x2bc78e0_0, 8, 3; - %delay 1000000, 0; - %vpi_call 2 413 "$display", "%b | %b | %b - NOR | %b | 0000 | %b | %b | %b | %b", v0x2bc7660_0, v0x2bc7860_0, v0x2bc78e0_0, v0x2bc7960_0, v0x2bc7be0_0, v0x2bc7c60_0, v0x2bc7a60_0, v0x2bc7760_0; - %movi 8, 11, 32; - %set/v v0x2bc7660_0, 8, 32; - %movi 8, 11, 32; - %set/v v0x2bc7860_0, 8, 32; + %vpi_call 3 119 "$display", "%b %b | %b | %b | 1 ", v0x2468770_0, v0x2468910_0, v0x2468a20_0, v0x2468aa0_0; + %set/v v0x2468770_0, 0, 1; + %set/v v0x2468910_0, 0, 1; %movi 8, 2, 3; - %set/v v0x2bc78e0_0, 8, 3; + %set/v v0x2468a20_0, 8, 3; %delay 1000000, 0; - %vpi_call 2 416 "$display", "%b | %b | %b - XOR | %b | 0000 | %b | %b | %b | %b", v0x2bc7660_0, v0x2bc7860_0, v0x2bc78e0_0, v0x2bc7960_0, v0x2bc7be0_0, v0x2bc7c60_0, v0x2bc7a60_0, v0x2bc7760_0; - %movi 8, 2, 32; - %set/v v0x2bc7660_0, 8, 32; - %movi 8, 14, 32; - %set/v v0x2bc7860_0, 8, 32; - %set/v v0x2bc78e0_0, 0, 3; - %delay 1000000, 0; - %vpi_call 2 419 "$display", "%b | %b | %b - ADD | %b | 0000 | %b | %b | %b | %b", v0x2bc7660_0, v0x2bc7860_0, v0x2bc78e0_0, v0x2bc7960_0, v0x2bc7be0_0, v0x2bc7c60_0, v0x2bc7a60_0, v0x2bc7760_0; - %movi 8, 2, 32; - %set/v v0x2bc7660_0, 8, 32; - %movi 8, 2, 32; - %set/v v0x2bc7860_0, 8, 32; - %movi 8, 1, 3; - %set/v v0x2bc78e0_0, 8, 3; - %delay 1000000, 0; - %vpi_call 2 422 "$display", "%b | %b | %b - SUB | %b | 0000 | %b | %b | %b | %b", v0x2bc7660_0, v0x2bc7860_0, v0x2bc78e0_0, v0x2bc7960_0, v0x2bc7be0_0, v0x2bc7c60_0, v0x2bc7a60_0, v0x2bc7760_0; - %set/v v0x2bc7660_0, 0, 32; - %set/v v0x2bc7860_0, 0, 32; - %movi 8, 3, 3; - %set/v v0x2bc78e0_0, 8, 3; - %delay 1000000, 0; - %vpi_call 2 426 "$display", "%b | %b | %b - SLT | %b | 0000 | %b | %b | %b | %b", v0x2bc7660_0, v0x2bc7860_0, v0x2bc78e0_0, v0x2bc7960_0, v0x2bc7be0_0, v0x2bc7c60_0, v0x2bc7a60_0, v0x2bc7760_0; + %vpi_call 3 121 "$display", "%b %b | %b | %b | 0", v0x2468770_0, v0x2468910_0, v0x2468a20_0, v0x2468aa0_0; %end; .thread T_0; # The file index is used to find the file name in the following table. :file_names 4; "N/A"; ""; - "testing.t.v"; "./alu.v"; + "testing.t.v"; diff --git a/testing.t.v b/testing.t.v index 922f06b..d2c43b6 100644 --- a/testing.t.v +++ b/testing.t.v @@ -25,8 +25,12 @@ wire muxout; // test OR/NOR/XOR OrNorXor testor(OrNorXorOut, A, B, Command); initial begin + $dumpfile("SmallALU.vcd"); + $dumpvars(); + + // test mux - $display("Four Input Multiplexer"); + /*$display("Four Input Multiplexer"); $display("S0 S1 |in0 in1 in2 in3| Output"); S0 = 0; S1 = 0; in0 = 1'bx; in1 = 0; in2 = 0; in3 = 0; #1000 $display(" %b %b | %b %b %b %b | %b", S0, S1, in0, in1, in2, in3, muxout); @@ -35,7 +39,7 @@ initial begin S0 = 0; S1 = 1; in0 = 0; in1 = 0; in2 = 1'bx; in3 = 0; #1000 $display(" %b %b | %b %b %b %b | %b", S0, S1, in0, in1, in2, in3, muxout); S0 = 1; S1 = 1; in0 = 0; in1 = 0; in2 = 0; in3 = 1'bx; #1000 - $display(" %b %b | %b %b %b %b | %b", S0, S1, in0, in1, in2, in3, muxout); + $display(" %b %b | %b %b %b %b | %b", S0, S1, in0, in1, in2, in3, muxout);*/ // just the adder - proper behavior $display("Adder/Subtractor"); $display("A B | Command |Out|ExpectOut|Carryout-Add"); From 37ab443fe94581b64625ad9b3691e1535d3d4d95 Mon Sep 17 00:00:00 2001 From: mjakus Date: Tue, 10 Oct 2017 14:52:08 -0400 Subject: [PATCH 22/28] Testing time --- SmallALU.vcd | 7467 ++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 7467 insertions(+) create mode 100644 SmallALU.vcd diff --git a/SmallALU.vcd b/SmallALU.vcd new file mode 100644 index 0000000..c81aaaf --- /dev/null +++ b/SmallALU.vcd @@ -0,0 +1,7467 @@ +$date + Tue Oct 10 14:48:25 2017 +$end +$version + Icarus Verilog +$end +$timescale + 1ps +$end +$scope module Bitslice32 $end +$var wire 32 ! A [31:0] $end +$var wire 32 " AddSubSLTSum [31:0] $end +$var wire 1 # AllZeros $end +$var wire 32 $ AndNandOut [31:0] $end +$var wire 32 % B [31:0] $end +$var wire 32 & Cmd0Start [31:0] $end +$var wire 32 ' Cmd1Start [31:0] $end +$var wire 3 ( Command [2:0] $end +$var wire 32 ) OneBitFinalOut [31:0] $end +$var wire 32 * OrNorXorOut [31:0] $end +$var wire 1 + SLTflag $end +$var wire 32 , ZeroFlag [31:0] $end +$var wire 32 - carryin [31:0] $end +$var wire 1 . carryout $end +$var wire 1 / overflow $end +$var wire 32 0 subtract [31:0] $end +$var wire 1 1 yeszero $end +$scope module trial $end +$var wire 32 2 A [31:0] $end +$var wire 32 3 AddSubSLTSum [31:0] $end +$var wire 32 4 B [31:0] $end +$var wire 32 5 CarryoutWire [31:0] $end +$var wire 3 6 Command [2:0] $end +$var wire 1 7 Res0OF1 $end +$var wire 1 8 Res1OF0 $end +$var wire 1 + SLTflag $end +$var wire 1 9 SLTflag0 $end +$var wire 1 : SLTflag1 $end +$var wire 1 ; SLTon $end +$var wire 32 < carryin [31:0] $end +$var wire 1 . carryout $end +$var wire 1 = nAddSubSLTSum $end +$var wire 1 > nOF $end +$var wire 1 / overflow $end +$var wire 32 ? subtract [31:0] $end +$scope module attempt2 $end +$var wire 1 @ A $end +$var wire 1 A AandB $end +$var wire 1 B AddSubSLTSum $end +$var wire 1 C AxorB $end +$var wire 1 D B $end +$var wire 1 E BornB $end +$var wire 1 F CINandAxorB $end +$var wire 3 G Command [2:0] $end +$var wire 1 H carryin $end +$var wire 1 I carryout $end +$var wire 1 J nB $end +$var wire 1 K nCmd2 $end +$var wire 1 L subtract $end +$scope module mux0 $end +$var wire 1 M S $end +$var wire 1 D in0 $end +$var wire 1 J in1 $end +$var wire 1 N nS $end +$var wire 1 O out0 $end +$var wire 1 P out1 $end +$var wire 1 E outfinal $end +$upscope $end +$upscope $end +$scope begin addbits[1] $end +$scope module attempt $end +$var wire 1 Q A $end +$var wire 1 R AandB $end +$var wire 1 S AddSubSLTSum $end +$var wire 1 T AxorB $end +$var wire 1 U B $end +$var wire 1 V BornB $end +$var wire 1 W CINandAxorB $end +$var wire 3 X Command [2:0] $end +$var wire 1 Y carryin $end +$var wire 1 Z carryout $end +$var wire 1 [ nB $end +$var wire 1 \ nCmd2 $end +$var wire 1 ] subtract $end +$scope module mux0 $end +$var wire 1 ^ S $end +$var wire 1 U in0 $end +$var wire 1 [ in1 $end +$var wire 1 _ nS $end +$var wire 1 ` out0 $end +$var wire 1 a out1 $end +$var wire 1 V outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin addbits[2] $end +$scope module attempt $end +$var wire 1 b A $end +$var wire 1 c AandB $end +$var wire 1 d AddSubSLTSum $end +$var wire 1 e AxorB $end +$var wire 1 f B $end +$var wire 1 g BornB $end +$var wire 1 h CINandAxorB $end +$var wire 3 i Command [2:0] $end +$var wire 1 j carryin $end +$var wire 1 k carryout $end +$var wire 1 l nB $end +$var wire 1 m nCmd2 $end +$var wire 1 n subtract $end +$scope module mux0 $end +$var wire 1 o S $end +$var wire 1 f in0 $end +$var wire 1 l in1 $end +$var wire 1 p nS $end +$var wire 1 q out0 $end +$var wire 1 r out1 $end +$var wire 1 g outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin addbits[3] $end +$scope module attempt $end +$var wire 1 s A $end +$var wire 1 t AandB $end +$var wire 1 u AddSubSLTSum $end +$var wire 1 v AxorB $end +$var wire 1 w B $end +$var wire 1 x BornB $end +$var wire 1 y CINandAxorB $end +$var wire 3 z Command [2:0] $end +$var wire 1 { carryin $end +$var wire 1 | carryout $end +$var wire 1 } nB $end +$var wire 1 ~ nCmd2 $end +$var wire 1 !" subtract $end +$scope module mux0 $end +$var wire 1 "" S $end +$var wire 1 w in0 $end +$var wire 1 } in1 $end +$var wire 1 #" nS $end +$var wire 1 $" out0 $end +$var wire 1 %" out1 $end +$var wire 1 x outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin addbits[4] $end +$scope module attempt $end +$var wire 1 &" A $end +$var wire 1 '" AandB $end +$var wire 1 (" AddSubSLTSum $end +$var wire 1 )" AxorB $end +$var wire 1 *" B $end +$var wire 1 +" BornB $end +$var wire 1 ," CINandAxorB $end +$var wire 3 -" Command [2:0] $end +$var wire 1 ." carryin $end +$var wire 1 /" carryout $end +$var wire 1 0" nB $end +$var wire 1 1" nCmd2 $end +$var wire 1 2" subtract $end +$scope module mux0 $end +$var wire 1 3" S $end +$var wire 1 *" in0 $end +$var wire 1 0" in1 $end +$var wire 1 4" nS $end +$var wire 1 5" out0 $end +$var wire 1 6" out1 $end +$var wire 1 +" outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin addbits[5] $end +$scope module attempt $end +$var wire 1 7" A $end +$var wire 1 8" AandB $end +$var wire 1 9" AddSubSLTSum $end +$var wire 1 :" AxorB $end +$var wire 1 ;" B $end +$var wire 1 <" BornB $end +$var wire 1 =" CINandAxorB $end +$var wire 3 >" Command [2:0] $end +$var wire 1 ?" carryin $end +$var wire 1 @" carryout $end +$var wire 1 A" nB $end +$var wire 1 B" nCmd2 $end +$var wire 1 C" subtract $end +$scope module mux0 $end +$var wire 1 D" S $end +$var wire 1 ;" in0 $end +$var wire 1 A" in1 $end +$var wire 1 E" nS $end +$var wire 1 F" out0 $end +$var wire 1 G" out1 $end +$var wire 1 <" outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin addbits[6] $end +$scope module attempt $end +$var wire 1 H" A $end +$var wire 1 I" AandB $end +$var wire 1 J" AddSubSLTSum $end +$var wire 1 K" AxorB $end +$var wire 1 L" B $end +$var wire 1 M" BornB $end +$var wire 1 N" CINandAxorB $end +$var wire 3 O" Command [2:0] $end +$var wire 1 P" carryin $end +$var wire 1 Q" carryout $end +$var wire 1 R" nB $end +$var wire 1 S" nCmd2 $end +$var wire 1 T" subtract $end +$scope module mux0 $end +$var wire 1 U" S $end +$var wire 1 L" in0 $end +$var wire 1 R" in1 $end +$var wire 1 V" nS $end +$var wire 1 W" out0 $end +$var wire 1 X" out1 $end +$var wire 1 M" outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin addbits[7] $end +$scope module attempt $end +$var wire 1 Y" A $end +$var wire 1 Z" AandB $end +$var wire 1 [" AddSubSLTSum $end +$var wire 1 \" AxorB $end +$var wire 1 ]" B $end +$var wire 1 ^" BornB $end +$var wire 1 _" CINandAxorB $end +$var wire 3 `" Command [2:0] $end +$var wire 1 a" carryin $end +$var wire 1 b" carryout $end +$var wire 1 c" nB $end +$var wire 1 d" nCmd2 $end +$var wire 1 e" subtract $end +$scope module mux0 $end +$var wire 1 f" S $end +$var wire 1 ]" in0 $end +$var wire 1 c" in1 $end +$var wire 1 g" nS $end +$var wire 1 h" out0 $end +$var wire 1 i" out1 $end +$var wire 1 ^" outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin addbits[8] $end +$scope module attempt $end +$var wire 1 j" A $end +$var wire 1 k" AandB $end +$var wire 1 l" AddSubSLTSum $end +$var wire 1 m" AxorB $end +$var wire 1 n" B $end +$var wire 1 o" BornB $end +$var wire 1 p" CINandAxorB $end +$var wire 3 q" Command [2:0] $end +$var wire 1 r" carryin $end +$var wire 1 s" carryout $end +$var wire 1 t" nB $end +$var wire 1 u" nCmd2 $end +$var wire 1 v" subtract $end +$scope module mux0 $end +$var wire 1 w" S $end +$var wire 1 n" in0 $end +$var wire 1 t" in1 $end +$var wire 1 x" nS $end +$var wire 1 y" out0 $end +$var wire 1 z" out1 $end +$var wire 1 o" outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin addbits[9] $end +$scope module attempt $end +$var wire 1 {" A $end +$var wire 1 |" AandB $end +$var wire 1 }" AddSubSLTSum $end +$var wire 1 ~" AxorB $end +$var wire 1 !# B $end +$var wire 1 "# BornB $end +$var wire 1 ## CINandAxorB $end +$var wire 3 $# Command [2:0] $end +$var wire 1 %# carryin $end +$var wire 1 &# carryout $end +$var wire 1 '# nB $end +$var wire 1 (# nCmd2 $end +$var wire 1 )# subtract $end +$scope module mux0 $end +$var wire 1 *# S $end +$var wire 1 !# in0 $end +$var wire 1 '# in1 $end +$var wire 1 +# nS $end +$var wire 1 ,# out0 $end +$var wire 1 -# out1 $end +$var wire 1 "# outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin addbits[10] $end +$scope module attempt $end +$var wire 1 .# A $end +$var wire 1 /# AandB $end +$var wire 1 0# AddSubSLTSum $end +$var wire 1 1# AxorB $end +$var wire 1 2# B $end +$var wire 1 3# BornB $end +$var wire 1 4# CINandAxorB $end +$var wire 3 5# Command [2:0] $end +$var wire 1 6# carryin $end +$var wire 1 7# carryout $end +$var wire 1 8# nB $end +$var wire 1 9# nCmd2 $end +$var wire 1 :# subtract $end +$scope module mux0 $end +$var wire 1 ;# S $end +$var wire 1 2# in0 $end +$var wire 1 8# in1 $end +$var wire 1 <# nS $end +$var wire 1 =# out0 $end +$var wire 1 ># out1 $end +$var wire 1 3# outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin addbits[11] $end +$scope module attempt $end +$var wire 1 ?# A $end +$var wire 1 @# AandB $end +$var wire 1 A# AddSubSLTSum $end +$var wire 1 B# AxorB $end +$var wire 1 C# B $end +$var wire 1 D# BornB $end +$var wire 1 E# CINandAxorB $end +$var wire 3 F# Command [2:0] $end +$var wire 1 G# carryin $end +$var wire 1 H# carryout $end +$var wire 1 I# nB $end +$var wire 1 J# nCmd2 $end +$var wire 1 K# subtract $end +$scope module mux0 $end +$var wire 1 L# S $end +$var wire 1 C# in0 $end +$var wire 1 I# in1 $end +$var wire 1 M# nS $end +$var wire 1 N# out0 $end +$var wire 1 O# out1 $end +$var wire 1 D# outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin addbits[12] $end +$scope module attempt $end +$var wire 1 P# A $end +$var wire 1 Q# AandB $end +$var wire 1 R# AddSubSLTSum $end +$var wire 1 S# AxorB $end +$var wire 1 T# B $end +$var wire 1 U# BornB $end +$var wire 1 V# CINandAxorB $end +$var wire 3 W# Command [2:0] $end +$var wire 1 X# carryin $end +$var wire 1 Y# carryout $end +$var wire 1 Z# nB $end +$var wire 1 [# nCmd2 $end +$var wire 1 \# subtract $end +$scope module mux0 $end +$var wire 1 ]# S $end +$var wire 1 T# in0 $end +$var wire 1 Z# in1 $end +$var wire 1 ^# nS $end +$var wire 1 _# out0 $end +$var wire 1 `# out1 $end +$var wire 1 U# outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin addbits[13] $end +$scope module attempt $end +$var wire 1 a# A $end +$var wire 1 b# AandB $end +$var wire 1 c# AddSubSLTSum $end +$var wire 1 d# AxorB $end +$var wire 1 e# B $end +$var wire 1 f# BornB $end +$var wire 1 g# CINandAxorB $end +$var wire 3 h# Command [2:0] $end +$var wire 1 i# carryin $end +$var wire 1 j# carryout $end +$var wire 1 k# nB $end +$var wire 1 l# nCmd2 $end +$var wire 1 m# subtract $end +$scope module mux0 $end +$var wire 1 n# S $end +$var wire 1 e# in0 $end +$var wire 1 k# in1 $end +$var wire 1 o# nS $end +$var wire 1 p# out0 $end +$var wire 1 q# out1 $end +$var wire 1 f# outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin addbits[14] $end +$scope module attempt $end +$var wire 1 r# A $end +$var wire 1 s# AandB $end +$var wire 1 t# AddSubSLTSum $end +$var wire 1 u# AxorB $end +$var wire 1 v# B $end +$var wire 1 w# BornB $end +$var wire 1 x# CINandAxorB $end +$var wire 3 y# Command [2:0] $end +$var wire 1 z# carryin $end +$var wire 1 {# carryout $end +$var wire 1 |# nB $end +$var wire 1 }# nCmd2 $end +$var wire 1 ~# subtract $end +$scope module mux0 $end +$var wire 1 !$ S $end +$var wire 1 v# in0 $end +$var wire 1 |# in1 $end +$var wire 1 "$ nS $end +$var wire 1 #$ out0 $end +$var wire 1 $$ out1 $end +$var wire 1 w# outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin addbits[15] $end +$scope module attempt $end +$var wire 1 %$ A $end +$var wire 1 &$ AandB $end +$var wire 1 '$ AddSubSLTSum $end +$var wire 1 ($ AxorB $end +$var wire 1 )$ B $end +$var wire 1 *$ BornB $end +$var wire 1 +$ CINandAxorB $end +$var wire 3 ,$ Command [2:0] $end +$var wire 1 -$ carryin $end +$var wire 1 .$ carryout $end +$var wire 1 /$ nB $end +$var wire 1 0$ nCmd2 $end +$var wire 1 1$ subtract $end +$scope module mux0 $end +$var wire 1 2$ S $end +$var wire 1 )$ in0 $end +$var wire 1 /$ in1 $end +$var wire 1 3$ nS $end +$var wire 1 4$ out0 $end +$var wire 1 5$ out1 $end +$var wire 1 *$ outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin addbits[16] $end +$scope module attempt $end +$var wire 1 6$ A $end +$var wire 1 7$ AandB $end +$var wire 1 8$ AddSubSLTSum $end +$var wire 1 9$ AxorB $end +$var wire 1 :$ B $end +$var wire 1 ;$ BornB $end +$var wire 1 <$ CINandAxorB $end +$var wire 3 =$ Command [2:0] $end +$var wire 1 >$ carryin $end +$var wire 1 ?$ carryout $end +$var wire 1 @$ nB $end +$var wire 1 A$ nCmd2 $end +$var wire 1 B$ subtract $end +$scope module mux0 $end +$var wire 1 C$ S $end +$var wire 1 :$ in0 $end +$var wire 1 @$ in1 $end +$var wire 1 D$ nS $end +$var wire 1 E$ out0 $end +$var wire 1 F$ out1 $end +$var wire 1 ;$ outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin addbits[17] $end +$scope module attempt $end +$var wire 1 G$ A $end +$var wire 1 H$ AandB $end +$var wire 1 I$ AddSubSLTSum $end +$var wire 1 J$ AxorB $end +$var wire 1 K$ B $end +$var wire 1 L$ BornB $end +$var wire 1 M$ CINandAxorB $end +$var wire 3 N$ Command [2:0] $end +$var wire 1 O$ carryin $end +$var wire 1 P$ carryout $end +$var wire 1 Q$ nB $end +$var wire 1 R$ nCmd2 $end +$var wire 1 S$ subtract $end +$scope module mux0 $end +$var wire 1 T$ S $end +$var wire 1 K$ in0 $end +$var wire 1 Q$ in1 $end +$var wire 1 U$ nS $end +$var wire 1 V$ out0 $end +$var wire 1 W$ out1 $end +$var wire 1 L$ outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin addbits[18] $end +$scope module attempt $end +$var wire 1 X$ A $end +$var wire 1 Y$ AandB $end +$var wire 1 Z$ AddSubSLTSum $end +$var wire 1 [$ AxorB $end +$var wire 1 \$ B $end +$var wire 1 ]$ BornB $end +$var wire 1 ^$ CINandAxorB $end +$var wire 3 _$ Command [2:0] $end +$var wire 1 `$ carryin $end +$var wire 1 a$ carryout $end +$var wire 1 b$ nB $end +$var wire 1 c$ nCmd2 $end +$var wire 1 d$ subtract $end +$scope module mux0 $end +$var wire 1 e$ S $end +$var wire 1 \$ in0 $end +$var wire 1 b$ in1 $end +$var wire 1 f$ nS $end +$var wire 1 g$ out0 $end +$var wire 1 h$ out1 $end +$var wire 1 ]$ outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin addbits[19] $end +$scope module attempt $end +$var wire 1 i$ A $end +$var wire 1 j$ AandB $end +$var wire 1 k$ AddSubSLTSum $end +$var wire 1 l$ AxorB $end +$var wire 1 m$ B $end +$var wire 1 n$ BornB $end +$var wire 1 o$ CINandAxorB $end +$var wire 3 p$ Command [2:0] $end +$var wire 1 q$ carryin $end +$var wire 1 r$ carryout $end +$var wire 1 s$ nB $end +$var wire 1 t$ nCmd2 $end +$var wire 1 u$ subtract $end +$scope module mux0 $end +$var wire 1 v$ S $end +$var wire 1 m$ in0 $end +$var wire 1 s$ in1 $end +$var wire 1 w$ nS $end +$var wire 1 x$ out0 $end +$var wire 1 y$ out1 $end +$var wire 1 n$ outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin addbits[20] $end +$scope module attempt $end +$var wire 1 z$ A $end +$var wire 1 {$ AandB $end +$var wire 1 |$ AddSubSLTSum $end +$var wire 1 }$ AxorB $end +$var wire 1 ~$ B $end +$var wire 1 !% BornB $end +$var wire 1 "% CINandAxorB $end +$var wire 3 #% Command [2:0] $end +$var wire 1 $% carryin $end +$var wire 1 %% carryout $end +$var wire 1 &% nB $end +$var wire 1 '% nCmd2 $end +$var wire 1 (% subtract $end +$scope module mux0 $end +$var wire 1 )% S $end +$var wire 1 ~$ in0 $end +$var wire 1 &% in1 $end +$var wire 1 *% nS $end +$var wire 1 +% out0 $end +$var wire 1 ,% out1 $end +$var wire 1 !% outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin addbits[21] $end +$scope module attempt $end +$var wire 1 -% A $end +$var wire 1 .% AandB $end +$var wire 1 /% AddSubSLTSum $end +$var wire 1 0% AxorB $end +$var wire 1 1% B $end +$var wire 1 2% BornB $end +$var wire 1 3% CINandAxorB $end +$var wire 3 4% Command [2:0] $end +$var wire 1 5% carryin $end +$var wire 1 6% carryout $end +$var wire 1 7% nB $end +$var wire 1 8% nCmd2 $end +$var wire 1 9% subtract $end +$scope module mux0 $end +$var wire 1 :% S $end +$var wire 1 1% in0 $end +$var wire 1 7% in1 $end +$var wire 1 ;% nS $end +$var wire 1 <% out0 $end +$var wire 1 =% out1 $end +$var wire 1 2% outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin addbits[22] $end +$scope module attempt $end +$var wire 1 >% A $end +$var wire 1 ?% AandB $end +$var wire 1 @% AddSubSLTSum $end +$var wire 1 A% AxorB $end +$var wire 1 B% B $end +$var wire 1 C% BornB $end +$var wire 1 D% CINandAxorB $end +$var wire 3 E% Command [2:0] $end +$var wire 1 F% carryin $end +$var wire 1 G% carryout $end +$var wire 1 H% nB $end +$var wire 1 I% nCmd2 $end +$var wire 1 J% subtract $end +$scope module mux0 $end +$var wire 1 K% S $end +$var wire 1 B% in0 $end +$var wire 1 H% in1 $end +$var wire 1 L% nS $end +$var wire 1 M% out0 $end +$var wire 1 N% out1 $end +$var wire 1 C% outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin addbits[23] $end +$scope module attempt $end +$var wire 1 O% A $end +$var wire 1 P% AandB $end +$var wire 1 Q% AddSubSLTSum $end +$var wire 1 R% AxorB $end +$var wire 1 S% B $end +$var wire 1 T% BornB $end +$var wire 1 U% CINandAxorB $end +$var wire 3 V% Command [2:0] $end +$var wire 1 W% carryin $end +$var wire 1 X% carryout $end +$var wire 1 Y% nB $end +$var wire 1 Z% nCmd2 $end +$var wire 1 [% subtract $end +$scope module mux0 $end +$var wire 1 \% S $end +$var wire 1 S% in0 $end +$var wire 1 Y% in1 $end +$var wire 1 ]% nS $end +$var wire 1 ^% out0 $end +$var wire 1 _% out1 $end +$var wire 1 T% outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin addbits[24] $end +$scope module attempt $end +$var wire 1 `% A $end +$var wire 1 a% AandB $end +$var wire 1 b% AddSubSLTSum $end +$var wire 1 c% AxorB $end +$var wire 1 d% B $end +$var wire 1 e% BornB $end +$var wire 1 f% CINandAxorB $end +$var wire 3 g% Command [2:0] $end +$var wire 1 h% carryin $end +$var wire 1 i% carryout $end +$var wire 1 j% nB $end +$var wire 1 k% nCmd2 $end +$var wire 1 l% subtract $end +$scope module mux0 $end +$var wire 1 m% S $end +$var wire 1 d% in0 $end +$var wire 1 j% in1 $end +$var wire 1 n% nS $end +$var wire 1 o% out0 $end +$var wire 1 p% out1 $end +$var wire 1 e% outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin addbits[25] $end +$scope module attempt $end +$var wire 1 q% A $end +$var wire 1 r% AandB $end +$var wire 1 s% AddSubSLTSum $end +$var wire 1 t% AxorB $end +$var wire 1 u% B $end +$var wire 1 v% BornB $end +$var wire 1 w% CINandAxorB $end +$var wire 3 x% Command [2:0] $end +$var wire 1 y% carryin $end +$var wire 1 z% carryout $end +$var wire 1 {% nB $end +$var wire 1 |% nCmd2 $end +$var wire 1 }% subtract $end +$scope module mux0 $end +$var wire 1 ~% S $end +$var wire 1 u% in0 $end +$var wire 1 {% in1 $end +$var wire 1 !& nS $end +$var wire 1 "& out0 $end +$var wire 1 #& out1 $end +$var wire 1 v% outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin addbits[26] $end +$scope module attempt $end +$var wire 1 $& A $end +$var wire 1 %& AandB $end +$var wire 1 && AddSubSLTSum $end +$var wire 1 '& AxorB $end +$var wire 1 (& B $end +$var wire 1 )& BornB $end +$var wire 1 *& CINandAxorB $end +$var wire 3 +& Command [2:0] $end +$var wire 1 ,& carryin $end +$var wire 1 -& carryout $end +$var wire 1 .& nB $end +$var wire 1 /& nCmd2 $end +$var wire 1 0& subtract $end +$scope module mux0 $end +$var wire 1 1& S $end +$var wire 1 (& in0 $end +$var wire 1 .& in1 $end +$var wire 1 2& nS $end +$var wire 1 3& out0 $end +$var wire 1 4& out1 $end +$var wire 1 )& outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin addbits[27] $end +$scope module attempt $end +$var wire 1 5& A $end +$var wire 1 6& AandB $end +$var wire 1 7& AddSubSLTSum $end +$var wire 1 8& AxorB $end +$var wire 1 9& B $end +$var wire 1 :& BornB $end +$var wire 1 ;& CINandAxorB $end +$var wire 3 <& Command [2:0] $end +$var wire 1 =& carryin $end +$var wire 1 >& carryout $end +$var wire 1 ?& nB $end +$var wire 1 @& nCmd2 $end +$var wire 1 A& subtract $end +$scope module mux0 $end +$var wire 1 B& S $end +$var wire 1 9& in0 $end +$var wire 1 ?& in1 $end +$var wire 1 C& nS $end +$var wire 1 D& out0 $end +$var wire 1 E& out1 $end +$var wire 1 :& outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin addbits[28] $end +$scope module attempt $end +$var wire 1 F& A $end +$var wire 1 G& AandB $end +$var wire 1 H& AddSubSLTSum $end +$var wire 1 I& AxorB $end +$var wire 1 J& B $end +$var wire 1 K& BornB $end +$var wire 1 L& CINandAxorB $end +$var wire 3 M& Command [2:0] $end +$var wire 1 N& carryin $end +$var wire 1 O& carryout $end +$var wire 1 P& nB $end +$var wire 1 Q& nCmd2 $end +$var wire 1 R& subtract $end +$scope module mux0 $end +$var wire 1 S& S $end +$var wire 1 J& in0 $end +$var wire 1 P& in1 $end +$var wire 1 T& nS $end +$var wire 1 U& out0 $end +$var wire 1 V& out1 $end +$var wire 1 K& outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin addbits[29] $end +$scope module attempt $end +$var wire 1 W& A $end +$var wire 1 X& AandB $end +$var wire 1 Y& AddSubSLTSum $end +$var wire 1 Z& AxorB $end +$var wire 1 [& B $end +$var wire 1 \& BornB $end +$var wire 1 ]& CINandAxorB $end +$var wire 3 ^& Command [2:0] $end +$var wire 1 _& carryin $end +$var wire 1 `& carryout $end +$var wire 1 a& nB $end +$var wire 1 b& nCmd2 $end +$var wire 1 c& subtract $end +$scope module mux0 $end +$var wire 1 d& S $end +$var wire 1 [& in0 $end +$var wire 1 a& in1 $end +$var wire 1 e& nS $end +$var wire 1 f& out0 $end +$var wire 1 g& out1 $end +$var wire 1 \& outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin addbits[30] $end +$scope module attempt $end +$var wire 1 h& A $end +$var wire 1 i& AandB $end +$var wire 1 j& AddSubSLTSum $end +$var wire 1 k& AxorB $end +$var wire 1 l& B $end +$var wire 1 m& BornB $end +$var wire 1 n& CINandAxorB $end +$var wire 3 o& Command [2:0] $end +$var wire 1 p& carryin $end +$var wire 1 q& carryout $end +$var wire 1 r& nB $end +$var wire 1 s& nCmd2 $end +$var wire 1 t& subtract $end +$scope module mux0 $end +$var wire 1 u& S $end +$var wire 1 l& in0 $end +$var wire 1 r& in1 $end +$var wire 1 v& nS $end +$var wire 1 w& out0 $end +$var wire 1 x& out1 $end +$var wire 1 m& outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin addbits[31] $end +$scope module attempt $end +$var wire 1 y& A $end +$var wire 1 z& AandB $end +$var wire 1 {& AddSubSLTSum $end +$var wire 1 |& AxorB $end +$var wire 1 }& B $end +$var wire 1 ~& BornB $end +$var wire 1 !' CINandAxorB $end +$var wire 3 "' Command [2:0] $end +$var wire 1 #' carryin $end +$var wire 1 $' carryout $end +$var wire 1 %' nB $end +$var wire 1 &' nCmd2 $end +$var wire 1 '' subtract $end +$scope module mux0 $end +$var wire 1 (' S $end +$var wire 1 }& in0 $end +$var wire 1 %' in1 $end +$var wire 1 )' nS $end +$var wire 1 *' out0 $end +$var wire 1 +' out1 $end +$var wire 1 ~& outfinal $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope module trial1 $end +$var wire 32 ,' A [31:0] $end +$var wire 32 -' AndNandOut [31:0] $end +$var wire 32 .' B [31:0] $end +$var wire 3 /' Command [2:0] $end +$scope module attempt2 $end +$var wire 1 0' A $end +$var wire 1 1' AandB $end +$var wire 1 2' AnandB $end +$var wire 1 3' AndNandOut $end +$var wire 1 4' B $end +$var wire 3 5' Command [2:0] $end +$scope module potato $end +$var wire 1 6' S $end +$var wire 1 1' in0 $end +$var wire 1 2' in1 $end +$var wire 1 7' nS $end +$var wire 1 8' out0 $end +$var wire 1 9' out1 $end +$var wire 1 3' outfinal $end +$upscope $end +$upscope $end +$scope begin andbits[1] $end +$scope module attempt $end +$var wire 1 :' A $end +$var wire 1 ;' AandB $end +$var wire 1 <' AnandB $end +$var wire 1 =' AndNandOut $end +$var wire 1 >' B $end +$var wire 3 ?' Command [2:0] $end +$scope module potato $end +$var wire 1 @' S $end +$var wire 1 ;' in0 $end +$var wire 1 <' in1 $end +$var wire 1 A' nS $end +$var wire 1 B' out0 $end +$var wire 1 C' out1 $end +$var wire 1 =' outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin andbits[2] $end +$scope module attempt $end +$var wire 1 D' A $end +$var wire 1 E' AandB $end +$var wire 1 F' AnandB $end +$var wire 1 G' AndNandOut $end +$var wire 1 H' B $end +$var wire 3 I' Command [2:0] $end +$scope module potato $end +$var wire 1 J' S $end +$var wire 1 E' in0 $end +$var wire 1 F' in1 $end +$var wire 1 K' nS $end +$var wire 1 L' out0 $end +$var wire 1 M' out1 $end +$var wire 1 G' outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin andbits[3] $end +$scope module attempt $end +$var wire 1 N' A $end +$var wire 1 O' AandB $end +$var wire 1 P' AnandB $end +$var wire 1 Q' AndNandOut $end +$var wire 1 R' B $end +$var wire 3 S' Command [2:0] $end +$scope module potato $end +$var wire 1 T' S $end +$var wire 1 O' in0 $end +$var wire 1 P' in1 $end +$var wire 1 U' nS $end +$var wire 1 V' out0 $end +$var wire 1 W' out1 $end +$var wire 1 Q' outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin andbits[4] $end +$scope module attempt $end +$var wire 1 X' A $end +$var wire 1 Y' AandB $end +$var wire 1 Z' AnandB $end +$var wire 1 [' AndNandOut $end +$var wire 1 \' B $end +$var wire 3 ]' Command [2:0] $end +$scope module potato $end +$var wire 1 ^' S $end +$var wire 1 Y' in0 $end +$var wire 1 Z' in1 $end +$var wire 1 _' nS $end +$var wire 1 `' out0 $end +$var wire 1 a' out1 $end +$var wire 1 [' outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin andbits[5] $end +$scope module attempt $end +$var wire 1 b' A $end +$var wire 1 c' AandB $end +$var wire 1 d' AnandB $end +$var wire 1 e' AndNandOut $end +$var wire 1 f' B $end +$var wire 3 g' Command [2:0] $end +$scope module potato $end +$var wire 1 h' S $end +$var wire 1 c' in0 $end +$var wire 1 d' in1 $end +$var wire 1 i' nS $end +$var wire 1 j' out0 $end +$var wire 1 k' out1 $end +$var wire 1 e' outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin andbits[6] $end +$scope module attempt $end +$var wire 1 l' A $end +$var wire 1 m' AandB $end +$var wire 1 n' AnandB $end +$var wire 1 o' AndNandOut $end +$var wire 1 p' B $end +$var wire 3 q' Command [2:0] $end +$scope module potato $end +$var wire 1 r' S $end +$var wire 1 m' in0 $end +$var wire 1 n' in1 $end +$var wire 1 s' nS $end +$var wire 1 t' out0 $end +$var wire 1 u' out1 $end +$var wire 1 o' outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin andbits[7] $end +$scope module attempt $end +$var wire 1 v' A $end +$var wire 1 w' AandB $end +$var wire 1 x' AnandB $end +$var wire 1 y' AndNandOut $end +$var wire 1 z' B $end +$var wire 3 {' Command [2:0] $end +$scope module potato $end +$var wire 1 |' S $end +$var wire 1 w' in0 $end +$var wire 1 x' in1 $end +$var wire 1 }' nS $end +$var wire 1 ~' out0 $end +$var wire 1 !( out1 $end +$var wire 1 y' outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin andbits[8] $end +$scope module attempt $end +$var wire 1 "( A $end +$var wire 1 #( AandB $end +$var wire 1 $( AnandB $end +$var wire 1 %( AndNandOut $end +$var wire 1 &( B $end +$var wire 3 '( Command [2:0] $end +$scope module potato $end +$var wire 1 (( S $end +$var wire 1 #( in0 $end +$var wire 1 $( in1 $end +$var wire 1 )( nS $end +$var wire 1 *( out0 $end +$var wire 1 +( out1 $end +$var wire 1 %( outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin andbits[9] $end +$scope module attempt $end +$var wire 1 ,( A $end +$var wire 1 -( AandB $end +$var wire 1 .( AnandB $end +$var wire 1 /( AndNandOut $end +$var wire 1 0( B $end +$var wire 3 1( Command [2:0] $end +$scope module potato $end +$var wire 1 2( S $end +$var wire 1 -( in0 $end +$var wire 1 .( in1 $end +$var wire 1 3( nS $end +$var wire 1 4( out0 $end +$var wire 1 5( out1 $end +$var wire 1 /( outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin andbits[10] $end +$scope module attempt $end +$var wire 1 6( A $end +$var wire 1 7( AandB $end +$var wire 1 8( AnandB $end +$var wire 1 9( AndNandOut $end +$var wire 1 :( B $end +$var wire 3 ;( Command [2:0] $end +$scope module potato $end +$var wire 1 <( S $end +$var wire 1 7( in0 $end +$var wire 1 8( in1 $end +$var wire 1 =( nS $end +$var wire 1 >( out0 $end +$var wire 1 ?( out1 $end +$var wire 1 9( outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin andbits[11] $end +$scope module attempt $end +$var wire 1 @( A $end +$var wire 1 A( AandB $end +$var wire 1 B( AnandB $end +$var wire 1 C( AndNandOut $end +$var wire 1 D( B $end +$var wire 3 E( Command [2:0] $end +$scope module potato $end +$var wire 1 F( S $end +$var wire 1 A( in0 $end +$var wire 1 B( in1 $end +$var wire 1 G( nS $end +$var wire 1 H( out0 $end +$var wire 1 I( out1 $end +$var wire 1 C( outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin andbits[12] $end +$scope module attempt $end +$var wire 1 J( A $end +$var wire 1 K( AandB $end +$var wire 1 L( AnandB $end +$var wire 1 M( AndNandOut $end +$var wire 1 N( B $end +$var wire 3 O( Command [2:0] $end +$scope module potato $end +$var wire 1 P( S $end +$var wire 1 K( in0 $end +$var wire 1 L( in1 $end +$var wire 1 Q( nS $end +$var wire 1 R( out0 $end +$var wire 1 S( out1 $end +$var wire 1 M( outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin andbits[13] $end +$scope module attempt $end +$var wire 1 T( A $end +$var wire 1 U( AandB $end +$var wire 1 V( AnandB $end +$var wire 1 W( AndNandOut $end +$var wire 1 X( B $end +$var wire 3 Y( Command [2:0] $end +$scope module potato $end +$var wire 1 Z( S $end +$var wire 1 U( in0 $end +$var wire 1 V( in1 $end +$var wire 1 [( nS $end +$var wire 1 \( out0 $end +$var wire 1 ]( out1 $end +$var wire 1 W( outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin andbits[14] $end +$scope module attempt $end +$var wire 1 ^( A $end +$var wire 1 _( AandB $end +$var wire 1 `( AnandB $end +$var wire 1 a( AndNandOut $end +$var wire 1 b( B $end +$var wire 3 c( Command [2:0] $end +$scope module potato $end +$var wire 1 d( S $end +$var wire 1 _( in0 $end +$var wire 1 `( in1 $end +$var wire 1 e( nS $end +$var wire 1 f( out0 $end +$var wire 1 g( out1 $end +$var wire 1 a( outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin andbits[15] $end +$scope module attempt $end +$var wire 1 h( A $end +$var wire 1 i( AandB $end +$var wire 1 j( AnandB $end +$var wire 1 k( AndNandOut $end +$var wire 1 l( B $end +$var wire 3 m( Command [2:0] $end +$scope module potato $end +$var wire 1 n( S $end +$var wire 1 i( in0 $end +$var wire 1 j( in1 $end +$var wire 1 o( nS $end +$var wire 1 p( out0 $end +$var wire 1 q( out1 $end +$var wire 1 k( outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin andbits[16] $end +$scope module attempt $end +$var wire 1 r( A $end +$var wire 1 s( AandB $end +$var wire 1 t( AnandB $end +$var wire 1 u( AndNandOut $end +$var wire 1 v( B $end +$var wire 3 w( Command [2:0] $end +$scope module potato $end +$var wire 1 x( S $end +$var wire 1 s( in0 $end +$var wire 1 t( in1 $end +$var wire 1 y( nS $end +$var wire 1 z( out0 $end +$var wire 1 {( out1 $end +$var wire 1 u( outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin andbits[17] $end +$scope module attempt $end +$var wire 1 |( A $end +$var wire 1 }( AandB $end +$var wire 1 ~( AnandB $end +$var wire 1 !) AndNandOut $end +$var wire 1 ") B $end +$var wire 3 #) Command [2:0] $end +$scope module potato $end +$var wire 1 $) S $end +$var wire 1 }( in0 $end +$var wire 1 ~( in1 $end +$var wire 1 %) nS $end +$var wire 1 &) out0 $end +$var wire 1 ') out1 $end +$var wire 1 !) outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin andbits[18] $end +$scope module attempt $end +$var wire 1 () A $end +$var wire 1 )) AandB $end +$var wire 1 *) AnandB $end +$var wire 1 +) AndNandOut $end +$var wire 1 ,) B $end +$var wire 3 -) Command [2:0] $end +$scope module potato $end +$var wire 1 .) S $end +$var wire 1 )) in0 $end +$var wire 1 *) in1 $end +$var wire 1 /) nS $end +$var wire 1 0) out0 $end +$var wire 1 1) out1 $end +$var wire 1 +) outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin andbits[19] $end +$scope module attempt $end +$var wire 1 2) A $end +$var wire 1 3) AandB $end +$var wire 1 4) AnandB $end +$var wire 1 5) AndNandOut $end +$var wire 1 6) B $end +$var wire 3 7) Command [2:0] $end +$scope module potato $end +$var wire 1 8) S $end +$var wire 1 3) in0 $end +$var wire 1 4) in1 $end +$var wire 1 9) nS $end +$var wire 1 :) out0 $end +$var wire 1 ;) out1 $end +$var wire 1 5) outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin andbits[20] $end +$scope module attempt $end +$var wire 1 <) A $end +$var wire 1 =) AandB $end +$var wire 1 >) AnandB $end +$var wire 1 ?) AndNandOut $end +$var wire 1 @) B $end +$var wire 3 A) Command [2:0] $end +$scope module potato $end +$var wire 1 B) S $end +$var wire 1 =) in0 $end +$var wire 1 >) in1 $end +$var wire 1 C) nS $end +$var wire 1 D) out0 $end +$var wire 1 E) out1 $end +$var wire 1 ?) outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin andbits[21] $end +$scope module attempt $end +$var wire 1 F) A $end +$var wire 1 G) AandB $end +$var wire 1 H) AnandB $end +$var wire 1 I) AndNandOut $end +$var wire 1 J) B $end +$var wire 3 K) Command [2:0] $end +$scope module potato $end +$var wire 1 L) S $end +$var wire 1 G) in0 $end +$var wire 1 H) in1 $end +$var wire 1 M) nS $end +$var wire 1 N) out0 $end +$var wire 1 O) out1 $end +$var wire 1 I) outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin andbits[22] $end +$scope module attempt $end +$var wire 1 P) A $end +$var wire 1 Q) AandB $end +$var wire 1 R) AnandB $end +$var wire 1 S) AndNandOut $end +$var wire 1 T) B $end +$var wire 3 U) Command [2:0] $end +$scope module potato $end +$var wire 1 V) S $end +$var wire 1 Q) in0 $end +$var wire 1 R) in1 $end +$var wire 1 W) nS $end +$var wire 1 X) out0 $end +$var wire 1 Y) out1 $end +$var wire 1 S) outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin andbits[23] $end +$scope module attempt $end +$var wire 1 Z) A $end +$var wire 1 [) AandB $end +$var wire 1 \) AnandB $end +$var wire 1 ]) AndNandOut $end +$var wire 1 ^) B $end +$var wire 3 _) Command [2:0] $end +$scope module potato $end +$var wire 1 `) S $end +$var wire 1 [) in0 $end +$var wire 1 \) in1 $end +$var wire 1 a) nS $end +$var wire 1 b) out0 $end +$var wire 1 c) out1 $end +$var wire 1 ]) outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin andbits[24] $end +$scope module attempt $end +$var wire 1 d) A $end +$var wire 1 e) AandB $end +$var wire 1 f) AnandB $end +$var wire 1 g) AndNandOut $end +$var wire 1 h) B $end +$var wire 3 i) Command [2:0] $end +$scope module potato $end +$var wire 1 j) S $end +$var wire 1 e) in0 $end +$var wire 1 f) in1 $end +$var wire 1 k) nS $end +$var wire 1 l) out0 $end +$var wire 1 m) out1 $end +$var wire 1 g) outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin andbits[25] $end +$scope module attempt $end +$var wire 1 n) A $end +$var wire 1 o) AandB $end +$var wire 1 p) AnandB $end +$var wire 1 q) AndNandOut $end +$var wire 1 r) B $end +$var wire 3 s) Command [2:0] $end +$scope module potato $end +$var wire 1 t) S $end +$var wire 1 o) in0 $end +$var wire 1 p) in1 $end +$var wire 1 u) nS $end +$var wire 1 v) out0 $end +$var wire 1 w) out1 $end +$var wire 1 q) outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin andbits[26] $end +$scope module attempt $end +$var wire 1 x) A $end +$var wire 1 y) AandB $end +$var wire 1 z) AnandB $end +$var wire 1 {) AndNandOut $end +$var wire 1 |) B $end +$var wire 3 }) Command [2:0] $end +$scope module potato $end +$var wire 1 ~) S $end +$var wire 1 y) in0 $end +$var wire 1 z) in1 $end +$var wire 1 !* nS $end +$var wire 1 "* out0 $end +$var wire 1 #* out1 $end +$var wire 1 {) outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin andbits[27] $end +$scope module attempt $end +$var wire 1 $* A $end +$var wire 1 %* AandB $end +$var wire 1 &* AnandB $end +$var wire 1 '* AndNandOut $end +$var wire 1 (* B $end +$var wire 3 )* Command [2:0] $end +$scope module potato $end +$var wire 1 ** S $end +$var wire 1 %* in0 $end +$var wire 1 &* in1 $end +$var wire 1 +* nS $end +$var wire 1 ,* out0 $end +$var wire 1 -* out1 $end +$var wire 1 '* outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin andbits[28] $end +$scope module attempt $end +$var wire 1 .* A $end +$var wire 1 /* AandB $end +$var wire 1 0* AnandB $end +$var wire 1 1* AndNandOut $end +$var wire 1 2* B $end +$var wire 3 3* Command [2:0] $end +$scope module potato $end +$var wire 1 4* S $end +$var wire 1 /* in0 $end +$var wire 1 0* in1 $end +$var wire 1 5* nS $end +$var wire 1 6* out0 $end +$var wire 1 7* out1 $end +$var wire 1 1* outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin andbits[29] $end +$scope module attempt $end +$var wire 1 8* A $end +$var wire 1 9* AandB $end +$var wire 1 :* AnandB $end +$var wire 1 ;* AndNandOut $end +$var wire 1 <* B $end +$var wire 3 =* Command [2:0] $end +$scope module potato $end +$var wire 1 >* S $end +$var wire 1 9* in0 $end +$var wire 1 :* in1 $end +$var wire 1 ?* nS $end +$var wire 1 @* out0 $end +$var wire 1 A* out1 $end +$var wire 1 ;* outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin andbits[30] $end +$scope module attempt $end +$var wire 1 B* A $end +$var wire 1 C* AandB $end +$var wire 1 D* AnandB $end +$var wire 1 E* AndNandOut $end +$var wire 1 F* B $end +$var wire 3 G* Command [2:0] $end +$scope module potato $end +$var wire 1 H* S $end +$var wire 1 C* in0 $end +$var wire 1 D* in1 $end +$var wire 1 I* nS $end +$var wire 1 J* out0 $end +$var wire 1 K* out1 $end +$var wire 1 E* outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin andbits[31] $end +$scope module attempt $end +$var wire 1 L* A $end +$var wire 1 M* AandB $end +$var wire 1 N* AnandB $end +$var wire 1 O* AndNandOut $end +$var wire 1 P* B $end +$var wire 3 Q* Command [2:0] $end +$scope module potato $end +$var wire 1 R* S $end +$var wire 1 M* in0 $end +$var wire 1 N* in1 $end +$var wire 1 S* nS $end +$var wire 1 T* out0 $end +$var wire 1 U* out1 $end +$var wire 1 O* outfinal $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope module trial2 $end +$var wire 32 V* A [31:0] $end +$var wire 32 W* B [31:0] $end +$var wire 3 X* Command [2:0] $end +$var wire 32 Y* OrNorXorOut [31:0] $end +$scope module attempt2 $end +$var wire 1 Z* A $end +$var wire 1 [* AnandB $end +$var wire 1 \* AnorB $end +$var wire 1 ]* AorB $end +$var wire 1 ^* AxorB $end +$var wire 1 _* B $end +$var wire 3 `* Command [2:0] $end +$var wire 1 a* OrNorXorOut $end +$var wire 1 b* XorNor $end +$var wire 1 c* nXor $end +$scope module mux0 $end +$var wire 1 d* S $end +$var wire 1 ^* in0 $end +$var wire 1 \* in1 $end +$var wire 1 e* nS $end +$var wire 1 f* out0 $end +$var wire 1 g* out1 $end +$var wire 1 b* outfinal $end +$upscope $end +$scope module mux1 $end +$var wire 1 h* S $end +$var wire 1 b* in0 $end +$var wire 1 ]* in1 $end +$var wire 1 i* nS $end +$var wire 1 j* out0 $end +$var wire 1 k* out1 $end +$var wire 1 a* outfinal $end +$upscope $end +$upscope $end +$scope begin orbits[1] $end +$scope module attempt $end +$var wire 1 l* A $end +$var wire 1 m* AnandB $end +$var wire 1 n* AnorB $end +$var wire 1 o* AorB $end +$var wire 1 p* AxorB $end +$var wire 1 q* B $end +$var wire 3 r* Command [2:0] $end +$var wire 1 s* OrNorXorOut $end +$var wire 1 t* XorNor $end +$var wire 1 u* nXor $end +$scope module mux0 $end +$var wire 1 v* S $end +$var wire 1 p* in0 $end +$var wire 1 n* in1 $end +$var wire 1 w* nS $end +$var wire 1 x* out0 $end +$var wire 1 y* out1 $end +$var wire 1 t* outfinal $end +$upscope $end +$scope module mux1 $end +$var wire 1 z* S $end +$var wire 1 t* in0 $end +$var wire 1 o* in1 $end +$var wire 1 {* nS $end +$var wire 1 |* out0 $end +$var wire 1 }* out1 $end +$var wire 1 s* outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin orbits[2] $end +$scope module attempt $end +$var wire 1 ~* A $end +$var wire 1 !+ AnandB $end +$var wire 1 "+ AnorB $end +$var wire 1 #+ AorB $end +$var wire 1 $+ AxorB $end +$var wire 1 %+ B $end +$var wire 3 &+ Command [2:0] $end +$var wire 1 '+ OrNorXorOut $end +$var wire 1 (+ XorNor $end +$var wire 1 )+ nXor $end +$scope module mux0 $end +$var wire 1 *+ S $end +$var wire 1 $+ in0 $end +$var wire 1 "+ in1 $end +$var wire 1 ++ nS $end +$var wire 1 ,+ out0 $end +$var wire 1 -+ out1 $end +$var wire 1 (+ outfinal $end +$upscope $end +$scope module mux1 $end +$var wire 1 .+ S $end +$var wire 1 (+ in0 $end +$var wire 1 #+ in1 $end +$var wire 1 /+ nS $end +$var wire 1 0+ out0 $end +$var wire 1 1+ out1 $end +$var wire 1 '+ outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin orbits[3] $end +$scope module attempt $end +$var wire 1 2+ A $end +$var wire 1 3+ AnandB $end +$var wire 1 4+ AnorB $end +$var wire 1 5+ AorB $end +$var wire 1 6+ AxorB $end +$var wire 1 7+ B $end +$var wire 3 8+ Command [2:0] $end +$var wire 1 9+ OrNorXorOut $end +$var wire 1 :+ XorNor $end +$var wire 1 ;+ nXor $end +$scope module mux0 $end +$var wire 1 <+ S $end +$var wire 1 6+ in0 $end +$var wire 1 4+ in1 $end +$var wire 1 =+ nS $end +$var wire 1 >+ out0 $end +$var wire 1 ?+ out1 $end +$var wire 1 :+ outfinal $end +$upscope $end +$scope module mux1 $end +$var wire 1 @+ S $end +$var wire 1 :+ in0 $end +$var wire 1 5+ in1 $end +$var wire 1 A+ nS $end +$var wire 1 B+ out0 $end +$var wire 1 C+ out1 $end +$var wire 1 9+ outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin orbits[4] $end +$scope module attempt $end +$var wire 1 D+ A $end +$var wire 1 E+ AnandB $end +$var wire 1 F+ AnorB $end +$var wire 1 G+ AorB $end +$var wire 1 H+ AxorB $end +$var wire 1 I+ B $end +$var wire 3 J+ Command [2:0] $end +$var wire 1 K+ OrNorXorOut $end +$var wire 1 L+ XorNor $end +$var wire 1 M+ nXor $end +$scope module mux0 $end +$var wire 1 N+ S $end +$var wire 1 H+ in0 $end +$var wire 1 F+ in1 $end +$var wire 1 O+ nS $end +$var wire 1 P+ out0 $end +$var wire 1 Q+ out1 $end +$var wire 1 L+ outfinal $end +$upscope $end +$scope module mux1 $end +$var wire 1 R+ S $end +$var wire 1 L+ in0 $end +$var wire 1 G+ in1 $end +$var wire 1 S+ nS $end +$var wire 1 T+ out0 $end +$var wire 1 U+ out1 $end +$var wire 1 K+ outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin orbits[5] $end +$scope module attempt $end +$var wire 1 V+ A $end +$var wire 1 W+ AnandB $end +$var wire 1 X+ AnorB $end +$var wire 1 Y+ AorB $end +$var wire 1 Z+ AxorB $end +$var wire 1 [+ B $end +$var wire 3 \+ Command [2:0] $end +$var wire 1 ]+ OrNorXorOut $end +$var wire 1 ^+ XorNor $end +$var wire 1 _+ nXor $end +$scope module mux0 $end +$var wire 1 `+ S $end +$var wire 1 Z+ in0 $end +$var wire 1 X+ in1 $end +$var wire 1 a+ nS $end +$var wire 1 b+ out0 $end +$var wire 1 c+ out1 $end +$var wire 1 ^+ outfinal $end +$upscope $end +$scope module mux1 $end +$var wire 1 d+ S $end +$var wire 1 ^+ in0 $end +$var wire 1 Y+ in1 $end +$var wire 1 e+ nS $end +$var wire 1 f+ out0 $end +$var wire 1 g+ out1 $end +$var wire 1 ]+ outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin orbits[6] $end +$scope module attempt $end +$var wire 1 h+ A $end +$var wire 1 i+ AnandB $end +$var wire 1 j+ AnorB $end +$var wire 1 k+ AorB $end +$var wire 1 l+ AxorB $end +$var wire 1 m+ B $end +$var wire 3 n+ Command [2:0] $end +$var wire 1 o+ OrNorXorOut $end +$var wire 1 p+ XorNor $end +$var wire 1 q+ nXor $end +$scope module mux0 $end +$var wire 1 r+ S $end +$var wire 1 l+ in0 $end +$var wire 1 j+ in1 $end +$var wire 1 s+ nS $end +$var wire 1 t+ out0 $end +$var wire 1 u+ out1 $end +$var wire 1 p+ outfinal $end +$upscope $end +$scope module mux1 $end +$var wire 1 v+ S $end +$var wire 1 p+ in0 $end +$var wire 1 k+ in1 $end +$var wire 1 w+ nS $end +$var wire 1 x+ out0 $end +$var wire 1 y+ out1 $end +$var wire 1 o+ outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin orbits[7] $end +$scope module attempt $end +$var wire 1 z+ A $end +$var wire 1 {+ AnandB $end +$var wire 1 |+ AnorB $end +$var wire 1 }+ AorB $end +$var wire 1 ~+ AxorB $end +$var wire 1 !, B $end +$var wire 3 ", Command [2:0] $end +$var wire 1 #, OrNorXorOut $end +$var wire 1 $, XorNor $end +$var wire 1 %, nXor $end +$scope module mux0 $end +$var wire 1 &, S $end +$var wire 1 ~+ in0 $end +$var wire 1 |+ in1 $end +$var wire 1 ', nS $end +$var wire 1 (, out0 $end +$var wire 1 ), out1 $end +$var wire 1 $, outfinal $end +$upscope $end +$scope module mux1 $end +$var wire 1 *, S $end +$var wire 1 $, in0 $end +$var wire 1 }+ in1 $end +$var wire 1 +, nS $end +$var wire 1 ,, out0 $end +$var wire 1 -, out1 $end +$var wire 1 #, outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin orbits[8] $end +$scope module attempt $end +$var wire 1 ., A $end +$var wire 1 /, AnandB $end +$var wire 1 0, AnorB $end +$var wire 1 1, AorB $end +$var wire 1 2, AxorB $end +$var wire 1 3, B $end +$var wire 3 4, Command [2:0] $end +$var wire 1 5, OrNorXorOut $end +$var wire 1 6, XorNor $end +$var wire 1 7, nXor $end +$scope module mux0 $end +$var wire 1 8, S $end +$var wire 1 2, in0 $end +$var wire 1 0, in1 $end +$var wire 1 9, nS $end +$var wire 1 :, out0 $end +$var wire 1 ;, out1 $end +$var wire 1 6, outfinal $end +$upscope $end +$scope module mux1 $end +$var wire 1 <, S $end +$var wire 1 6, in0 $end +$var wire 1 1, in1 $end +$var wire 1 =, nS $end +$var wire 1 >, out0 $end +$var wire 1 ?, out1 $end +$var wire 1 5, outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin orbits[9] $end +$scope module attempt $end +$var wire 1 @, A $end +$var wire 1 A, AnandB $end +$var wire 1 B, AnorB $end +$var wire 1 C, AorB $end +$var wire 1 D, AxorB $end +$var wire 1 E, B $end +$var wire 3 F, Command [2:0] $end +$var wire 1 G, OrNorXorOut $end +$var wire 1 H, XorNor $end +$var wire 1 I, nXor $end +$scope module mux0 $end +$var wire 1 J, S $end +$var wire 1 D, in0 $end +$var wire 1 B, in1 $end +$var wire 1 K, nS $end +$var wire 1 L, out0 $end +$var wire 1 M, out1 $end +$var wire 1 H, outfinal $end +$upscope $end +$scope module mux1 $end +$var wire 1 N, S $end +$var wire 1 H, in0 $end +$var wire 1 C, in1 $end +$var wire 1 O, nS $end +$var wire 1 P, out0 $end +$var wire 1 Q, out1 $end +$var wire 1 G, outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin orbits[10] $end +$scope module attempt $end +$var wire 1 R, A $end +$var wire 1 S, AnandB $end +$var wire 1 T, AnorB $end +$var wire 1 U, AorB $end +$var wire 1 V, AxorB $end +$var wire 1 W, B $end +$var wire 3 X, Command [2:0] $end +$var wire 1 Y, OrNorXorOut $end +$var wire 1 Z, XorNor $end +$var wire 1 [, nXor $end +$scope module mux0 $end +$var wire 1 \, S $end +$var wire 1 V, in0 $end +$var wire 1 T, in1 $end +$var wire 1 ], nS $end +$var wire 1 ^, out0 $end +$var wire 1 _, out1 $end +$var wire 1 Z, outfinal $end +$upscope $end +$scope module mux1 $end +$var wire 1 `, S $end +$var wire 1 Z, in0 $end +$var wire 1 U, in1 $end +$var wire 1 a, nS $end +$var wire 1 b, out0 $end +$var wire 1 c, out1 $end +$var wire 1 Y, outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin orbits[11] $end +$scope module attempt $end +$var wire 1 d, A $end +$var wire 1 e, AnandB $end +$var wire 1 f, AnorB $end +$var wire 1 g, AorB $end +$var wire 1 h, AxorB $end +$var wire 1 i, B $end +$var wire 3 j, Command [2:0] $end +$var wire 1 k, OrNorXorOut $end +$var wire 1 l, XorNor $end +$var wire 1 m, nXor $end +$scope module mux0 $end +$var wire 1 n, S $end +$var wire 1 h, in0 $end +$var wire 1 f, in1 $end +$var wire 1 o, nS $end +$var wire 1 p, out0 $end +$var wire 1 q, out1 $end +$var wire 1 l, outfinal $end +$upscope $end +$scope module mux1 $end +$var wire 1 r, S $end +$var wire 1 l, in0 $end +$var wire 1 g, in1 $end +$var wire 1 s, nS $end +$var wire 1 t, out0 $end +$var wire 1 u, out1 $end +$var wire 1 k, outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin orbits[12] $end +$scope module attempt $end +$var wire 1 v, A $end +$var wire 1 w, AnandB $end +$var wire 1 x, AnorB $end +$var wire 1 y, AorB $end +$var wire 1 z, AxorB $end +$var wire 1 {, B $end +$var wire 3 |, Command [2:0] $end +$var wire 1 }, OrNorXorOut $end +$var wire 1 ~, XorNor $end +$var wire 1 !- nXor $end +$scope module mux0 $end +$var wire 1 "- S $end +$var wire 1 z, in0 $end +$var wire 1 x, in1 $end +$var wire 1 #- nS $end +$var wire 1 $- out0 $end +$var wire 1 %- out1 $end +$var wire 1 ~, outfinal $end +$upscope $end +$scope module mux1 $end +$var wire 1 &- S $end +$var wire 1 ~, in0 $end +$var wire 1 y, in1 $end +$var wire 1 '- nS $end +$var wire 1 (- out0 $end +$var wire 1 )- out1 $end +$var wire 1 }, outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin orbits[13] $end +$scope module attempt $end +$var wire 1 *- A $end +$var wire 1 +- AnandB $end +$var wire 1 ,- AnorB $end +$var wire 1 -- AorB $end +$var wire 1 .- AxorB $end +$var wire 1 /- B $end +$var wire 3 0- Command [2:0] $end +$var wire 1 1- OrNorXorOut $end +$var wire 1 2- XorNor $end +$var wire 1 3- nXor $end +$scope module mux0 $end +$var wire 1 4- S $end +$var wire 1 .- in0 $end +$var wire 1 ,- in1 $end +$var wire 1 5- nS $end +$var wire 1 6- out0 $end +$var wire 1 7- out1 $end +$var wire 1 2- outfinal $end +$upscope $end +$scope module mux1 $end +$var wire 1 8- S $end +$var wire 1 2- in0 $end +$var wire 1 -- in1 $end +$var wire 1 9- nS $end +$var wire 1 :- out0 $end +$var wire 1 ;- out1 $end +$var wire 1 1- outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin orbits[14] $end +$scope module attempt $end +$var wire 1 <- A $end +$var wire 1 =- AnandB $end +$var wire 1 >- AnorB $end +$var wire 1 ?- AorB $end +$var wire 1 @- AxorB $end +$var wire 1 A- B $end +$var wire 3 B- Command [2:0] $end +$var wire 1 C- OrNorXorOut $end +$var wire 1 D- XorNor $end +$var wire 1 E- nXor $end +$scope module mux0 $end +$var wire 1 F- S $end +$var wire 1 @- in0 $end +$var wire 1 >- in1 $end +$var wire 1 G- nS $end +$var wire 1 H- out0 $end +$var wire 1 I- out1 $end +$var wire 1 D- outfinal $end +$upscope $end +$scope module mux1 $end +$var wire 1 J- S $end +$var wire 1 D- in0 $end +$var wire 1 ?- in1 $end +$var wire 1 K- nS $end +$var wire 1 L- out0 $end +$var wire 1 M- out1 $end +$var wire 1 C- outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin orbits[15] $end +$scope module attempt $end +$var wire 1 N- A $end +$var wire 1 O- AnandB $end +$var wire 1 P- AnorB $end +$var wire 1 Q- AorB $end +$var wire 1 R- AxorB $end +$var wire 1 S- B $end +$var wire 3 T- Command [2:0] $end +$var wire 1 U- OrNorXorOut $end +$var wire 1 V- XorNor $end +$var wire 1 W- nXor $end +$scope module mux0 $end +$var wire 1 X- S $end +$var wire 1 R- in0 $end +$var wire 1 P- in1 $end +$var wire 1 Y- nS $end +$var wire 1 Z- out0 $end +$var wire 1 [- out1 $end +$var wire 1 V- outfinal $end +$upscope $end +$scope module mux1 $end +$var wire 1 \- S $end +$var wire 1 V- in0 $end +$var wire 1 Q- in1 $end +$var wire 1 ]- nS $end +$var wire 1 ^- out0 $end +$var wire 1 _- out1 $end +$var wire 1 U- outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin orbits[16] $end +$scope module attempt $end +$var wire 1 `- A $end +$var wire 1 a- AnandB $end +$var wire 1 b- AnorB $end +$var wire 1 c- AorB $end +$var wire 1 d- AxorB $end +$var wire 1 e- B $end +$var wire 3 f- Command [2:0] $end +$var wire 1 g- OrNorXorOut $end +$var wire 1 h- XorNor $end +$var wire 1 i- nXor $end +$scope module mux0 $end +$var wire 1 j- S $end +$var wire 1 d- in0 $end +$var wire 1 b- in1 $end +$var wire 1 k- nS $end +$var wire 1 l- out0 $end +$var wire 1 m- out1 $end +$var wire 1 h- outfinal $end +$upscope $end +$scope module mux1 $end +$var wire 1 n- S $end +$var wire 1 h- in0 $end +$var wire 1 c- in1 $end +$var wire 1 o- nS $end +$var wire 1 p- out0 $end +$var wire 1 q- out1 $end +$var wire 1 g- outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin orbits[17] $end +$scope module attempt $end +$var wire 1 r- A $end +$var wire 1 s- AnandB $end +$var wire 1 t- AnorB $end +$var wire 1 u- AorB $end +$var wire 1 v- AxorB $end +$var wire 1 w- B $end +$var wire 3 x- Command [2:0] $end +$var wire 1 y- OrNorXorOut $end +$var wire 1 z- XorNor $end +$var wire 1 {- nXor $end +$scope module mux0 $end +$var wire 1 |- S $end +$var wire 1 v- in0 $end +$var wire 1 t- in1 $end +$var wire 1 }- nS $end +$var wire 1 ~- out0 $end +$var wire 1 !. out1 $end +$var wire 1 z- outfinal $end +$upscope $end +$scope module mux1 $end +$var wire 1 ". S $end +$var wire 1 z- in0 $end +$var wire 1 u- in1 $end +$var wire 1 #. nS $end +$var wire 1 $. out0 $end +$var wire 1 %. out1 $end +$var wire 1 y- outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin orbits[18] $end +$scope module attempt $end +$var wire 1 &. A $end +$var wire 1 '. AnandB $end +$var wire 1 (. AnorB $end +$var wire 1 ). AorB $end +$var wire 1 *. AxorB $end +$var wire 1 +. B $end +$var wire 3 ,. Command [2:0] $end +$var wire 1 -. OrNorXorOut $end +$var wire 1 .. XorNor $end +$var wire 1 /. nXor $end +$scope module mux0 $end +$var wire 1 0. S $end +$var wire 1 *. in0 $end +$var wire 1 (. in1 $end +$var wire 1 1. nS $end +$var wire 1 2. out0 $end +$var wire 1 3. out1 $end +$var wire 1 .. outfinal $end +$upscope $end +$scope module mux1 $end +$var wire 1 4. S $end +$var wire 1 .. in0 $end +$var wire 1 ). in1 $end +$var wire 1 5. nS $end +$var wire 1 6. out0 $end +$var wire 1 7. out1 $end +$var wire 1 -. outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin orbits[19] $end +$scope module attempt $end +$var wire 1 8. A $end +$var wire 1 9. AnandB $end +$var wire 1 :. AnorB $end +$var wire 1 ;. AorB $end +$var wire 1 <. AxorB $end +$var wire 1 =. B $end +$var wire 3 >. Command [2:0] $end +$var wire 1 ?. OrNorXorOut $end +$var wire 1 @. XorNor $end +$var wire 1 A. nXor $end +$scope module mux0 $end +$var wire 1 B. S $end +$var wire 1 <. in0 $end +$var wire 1 :. in1 $end +$var wire 1 C. nS $end +$var wire 1 D. out0 $end +$var wire 1 E. out1 $end +$var wire 1 @. outfinal $end +$upscope $end +$scope module mux1 $end +$var wire 1 F. S $end +$var wire 1 @. in0 $end +$var wire 1 ;. in1 $end +$var wire 1 G. nS $end +$var wire 1 H. out0 $end +$var wire 1 I. out1 $end +$var wire 1 ?. outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin orbits[20] $end +$scope module attempt $end +$var wire 1 J. A $end +$var wire 1 K. AnandB $end +$var wire 1 L. AnorB $end +$var wire 1 M. AorB $end +$var wire 1 N. AxorB $end +$var wire 1 O. B $end +$var wire 3 P. Command [2:0] $end +$var wire 1 Q. OrNorXorOut $end +$var wire 1 R. XorNor $end +$var wire 1 S. nXor $end +$scope module mux0 $end +$var wire 1 T. S $end +$var wire 1 N. in0 $end +$var wire 1 L. in1 $end +$var wire 1 U. nS $end +$var wire 1 V. out0 $end +$var wire 1 W. out1 $end +$var wire 1 R. outfinal $end +$upscope $end +$scope module mux1 $end +$var wire 1 X. S $end +$var wire 1 R. in0 $end +$var wire 1 M. in1 $end +$var wire 1 Y. nS $end +$var wire 1 Z. out0 $end +$var wire 1 [. out1 $end +$var wire 1 Q. outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin orbits[21] $end +$scope module attempt $end +$var wire 1 \. A $end +$var wire 1 ]. AnandB $end +$var wire 1 ^. AnorB $end +$var wire 1 _. AorB $end +$var wire 1 `. AxorB $end +$var wire 1 a. B $end +$var wire 3 b. Command [2:0] $end +$var wire 1 c. OrNorXorOut $end +$var wire 1 d. XorNor $end +$var wire 1 e. nXor $end +$scope module mux0 $end +$var wire 1 f. S $end +$var wire 1 `. in0 $end +$var wire 1 ^. in1 $end +$var wire 1 g. nS $end +$var wire 1 h. out0 $end +$var wire 1 i. out1 $end +$var wire 1 d. outfinal $end +$upscope $end +$scope module mux1 $end +$var wire 1 j. S $end +$var wire 1 d. in0 $end +$var wire 1 _. in1 $end +$var wire 1 k. nS $end +$var wire 1 l. out0 $end +$var wire 1 m. out1 $end +$var wire 1 c. outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin orbits[22] $end +$scope module attempt $end +$var wire 1 n. A $end +$var wire 1 o. AnandB $end +$var wire 1 p. AnorB $end +$var wire 1 q. AorB $end +$var wire 1 r. AxorB $end +$var wire 1 s. B $end +$var wire 3 t. Command [2:0] $end +$var wire 1 u. OrNorXorOut $end +$var wire 1 v. XorNor $end +$var wire 1 w. nXor $end +$scope module mux0 $end +$var wire 1 x. S $end +$var wire 1 r. in0 $end +$var wire 1 p. in1 $end +$var wire 1 y. nS $end +$var wire 1 z. out0 $end +$var wire 1 {. out1 $end +$var wire 1 v. outfinal $end +$upscope $end +$scope module mux1 $end +$var wire 1 |. S $end +$var wire 1 v. in0 $end +$var wire 1 q. in1 $end +$var wire 1 }. nS $end +$var wire 1 ~. out0 $end +$var wire 1 !/ out1 $end +$var wire 1 u. outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin orbits[23] $end +$scope module attempt $end +$var wire 1 "/ A $end +$var wire 1 #/ AnandB $end +$var wire 1 $/ AnorB $end +$var wire 1 %/ AorB $end +$var wire 1 &/ AxorB $end +$var wire 1 '/ B $end +$var wire 3 (/ Command [2:0] $end +$var wire 1 )/ OrNorXorOut $end +$var wire 1 */ XorNor $end +$var wire 1 +/ nXor $end +$scope module mux0 $end +$var wire 1 ,/ S $end +$var wire 1 &/ in0 $end +$var wire 1 $/ in1 $end +$var wire 1 -/ nS $end +$var wire 1 ./ out0 $end +$var wire 1 // out1 $end +$var wire 1 */ outfinal $end +$upscope $end +$scope module mux1 $end +$var wire 1 0/ S $end +$var wire 1 */ in0 $end +$var wire 1 %/ in1 $end +$var wire 1 1/ nS $end +$var wire 1 2/ out0 $end +$var wire 1 3/ out1 $end +$var wire 1 )/ outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin orbits[24] $end +$scope module attempt $end +$var wire 1 4/ A $end +$var wire 1 5/ AnandB $end +$var wire 1 6/ AnorB $end +$var wire 1 7/ AorB $end +$var wire 1 8/ AxorB $end +$var wire 1 9/ B $end +$var wire 3 :/ Command [2:0] $end +$var wire 1 ;/ OrNorXorOut $end +$var wire 1 / S $end +$var wire 1 8/ in0 $end +$var wire 1 6/ in1 $end +$var wire 1 ?/ nS $end +$var wire 1 @/ out0 $end +$var wire 1 A/ out1 $end +$var wire 1 0 S $end +$var wire 1 80 in0 $end +$var wire 1 30 in1 $end +$var wire 1 ?0 nS $end +$var wire 1 @0 out0 $end +$var wire 1 A0 out1 $end +$var wire 1 70 outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin orbits[30] $end +$scope module attempt $end +$var wire 1 B0 A $end +$var wire 1 C0 AnandB $end +$var wire 1 D0 AnorB $end +$var wire 1 E0 AorB $end +$var wire 1 F0 AxorB $end +$var wire 1 G0 B $end +$var wire 3 H0 Command [2:0] $end +$var wire 1 I0 OrNorXorOut $end +$var wire 1 J0 XorNor $end +$var wire 1 K0 nXor $end +$scope module mux0 $end +$var wire 1 L0 S $end +$var wire 1 F0 in0 $end +$var wire 1 D0 in1 $end +$var wire 1 M0 nS $end +$var wire 1 N0 out0 $end +$var wire 1 O0 out1 $end +$var wire 1 J0 outfinal $end +$upscope $end +$scope module mux1 $end +$var wire 1 P0 S $end +$var wire 1 J0 in0 $end +$var wire 1 E0 in1 $end +$var wire 1 Q0 nS $end +$var wire 1 R0 out0 $end +$var wire 1 S0 out1 $end +$var wire 1 I0 outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin orbits[31] $end +$scope module attempt $end +$var wire 1 T0 A $end +$var wire 1 U0 AnandB $end +$var wire 1 V0 AnorB $end +$var wire 1 W0 AorB $end +$var wire 1 X0 AxorB $end +$var wire 1 Y0 B $end +$var wire 3 Z0 Command [2:0] $end +$var wire 1 [0 OrNorXorOut $end +$var wire 1 \0 XorNor $end +$var wire 1 ]0 nXor $end +$scope module mux0 $end +$var wire 1 ^0 S $end +$var wire 1 X0 in0 $end +$var wire 1 V0 in1 $end +$var wire 1 _0 nS $end +$var wire 1 `0 out0 $end +$var wire 1 a0 out1 $end +$var wire 1 \0 outfinal $end +$upscope $end +$scope module mux1 $end +$var wire 1 b0 S $end +$var wire 1 \0 in0 $end +$var wire 1 W0 in1 $end +$var wire 1 c0 nS $end +$var wire 1 d0 out0 $end +$var wire 1 e0 out1 $end +$var wire 1 [0 outfinal $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope module ZeroMux0case $end +$var wire 1 f0 S0 $end +$var wire 1 g0 S1 $end +$var wire 1 h0 in0 $end +$var wire 1 i0 in1 $end +$var wire 1 j0 in2 $end +$var wire 1 k0 in3 $end +$var wire 1 l0 nS0 $end +$var wire 1 m0 nS1 $end +$var wire 1 n0 out $end +$var wire 1 o0 out0 $end +$var wire 1 p0 out1 $end +$var wire 1 q0 out2 $end +$var wire 1 r0 out3 $end +$upscope $end +$scope module OneMux0case $end +$var wire 1 s0 S0 $end +$var wire 1 t0 S1 $end +$var wire 1 u0 in0 $end +$var wire 1 v0 in1 $end +$var wire 1 w0 in2 $end +$var wire 1 x0 in3 $end +$var wire 1 y0 nS0 $end +$var wire 1 z0 nS1 $end +$var wire 1 {0 out $end +$var wire 1 |0 out0 $end +$var wire 1 }0 out1 $end +$var wire 1 ~0 out2 $end +$var wire 1 !1 out3 $end +$upscope $end +$scope module TwoMux0case $end +$var wire 1 "1 S $end +$var wire 1 #1 in0 $end +$var wire 1 $1 in1 $end +$var wire 1 %1 nS $end +$var wire 1 &1 out0 $end +$var wire 1 '1 out1 $end +$var wire 1 (1 outfinal $end +$upscope $end +$scope begin muxbits[1] $end +$scope module ZeroMux $end +$var wire 1 )1 S0 $end +$var wire 1 *1 S1 $end +$var wire 1 +1 in0 $end +$var wire 1 ,1 in1 $end +$var wire 1 -1 in2 $end +$var wire 1 .1 in3 $end +$var wire 1 /1 nS0 $end +$var wire 1 01 nS1 $end +$var wire 1 11 out $end +$var wire 1 21 out0 $end +$var wire 1 31 out1 $end +$var wire 1 41 out2 $end +$var wire 1 51 out3 $end +$upscope $end +$scope module OneMux $end +$var wire 1 61 S0 $end +$var wire 1 71 S1 $end +$var wire 1 81 in0 $end +$var wire 1 91 in1 $end +$var wire 1 :1 in2 $end +$var wire 1 ;1 in3 $end +$var wire 1 <1 nS0 $end +$var wire 1 =1 nS1 $end +$var wire 1 >1 out $end +$var wire 1 ?1 out0 $end +$var wire 1 @1 out1 $end +$var wire 1 A1 out2 $end +$var wire 1 B1 out3 $end +$upscope $end +$scope module TwoMux $end +$var wire 1 C1 S $end +$var wire 1 D1 in0 $end +$var wire 1 E1 in1 $end +$var wire 1 F1 nS $end +$var wire 1 G1 out0 $end +$var wire 1 H1 out1 $end +$var wire 1 I1 outfinal $end +$upscope $end +$upscope $end +$scope begin muxbits[2] $end +$scope module ZeroMux $end +$var wire 1 J1 S0 $end +$var wire 1 K1 S1 $end +$var wire 1 L1 in0 $end +$var wire 1 M1 in1 $end +$var wire 1 N1 in2 $end +$var wire 1 O1 in3 $end +$var wire 1 P1 nS0 $end +$var wire 1 Q1 nS1 $end +$var wire 1 R1 out $end +$var wire 1 S1 out0 $end +$var wire 1 T1 out1 $end +$var wire 1 U1 out2 $end +$var wire 1 V1 out3 $end +$upscope $end +$scope module OneMux $end +$var wire 1 W1 S0 $end +$var wire 1 X1 S1 $end +$var wire 1 Y1 in0 $end +$var wire 1 Z1 in1 $end +$var wire 1 [1 in2 $end +$var wire 1 \1 in3 $end +$var wire 1 ]1 nS0 $end +$var wire 1 ^1 nS1 $end +$var wire 1 _1 out $end +$var wire 1 `1 out0 $end +$var wire 1 a1 out1 $end +$var wire 1 b1 out2 $end +$var wire 1 c1 out3 $end +$upscope $end +$scope module TwoMux $end +$var wire 1 d1 S $end +$var wire 1 e1 in0 $end +$var wire 1 f1 in1 $end +$var wire 1 g1 nS $end +$var wire 1 h1 out0 $end +$var wire 1 i1 out1 $end +$var wire 1 j1 outfinal $end +$upscope $end +$upscope $end +$scope begin muxbits[3] $end +$scope module ZeroMux $end +$var wire 1 k1 S0 $end +$var wire 1 l1 S1 $end +$var wire 1 m1 in0 $end +$var wire 1 n1 in1 $end +$var wire 1 o1 in2 $end +$var wire 1 p1 in3 $end +$var wire 1 q1 nS0 $end +$var wire 1 r1 nS1 $end +$var wire 1 s1 out $end +$var wire 1 t1 out0 $end +$var wire 1 u1 out1 $end +$var wire 1 v1 out2 $end +$var wire 1 w1 out3 $end +$upscope $end +$scope module OneMux $end +$var wire 1 x1 S0 $end +$var wire 1 y1 S1 $end +$var wire 1 z1 in0 $end +$var wire 1 {1 in1 $end +$var wire 1 |1 in2 $end +$var wire 1 }1 in3 $end +$var wire 1 ~1 nS0 $end +$var wire 1 !2 nS1 $end +$var wire 1 "2 out $end +$var wire 1 #2 out0 $end +$var wire 1 $2 out1 $end +$var wire 1 %2 out2 $end +$var wire 1 &2 out3 $end +$upscope $end +$scope module TwoMux $end +$var wire 1 '2 S $end +$var wire 1 (2 in0 $end +$var wire 1 )2 in1 $end +$var wire 1 *2 nS $end +$var wire 1 +2 out0 $end +$var wire 1 ,2 out1 $end +$var wire 1 -2 outfinal $end +$upscope $end +$upscope $end +$scope begin muxbits[4] $end +$scope module ZeroMux $end +$var wire 1 .2 S0 $end +$var wire 1 /2 S1 $end +$var wire 1 02 in0 $end +$var wire 1 12 in1 $end +$var wire 1 22 in2 $end +$var wire 1 32 in3 $end +$var wire 1 42 nS0 $end +$var wire 1 52 nS1 $end +$var wire 1 62 out $end +$var wire 1 72 out0 $end +$var wire 1 82 out1 $end +$var wire 1 92 out2 $end +$var wire 1 :2 out3 $end +$upscope $end +$scope module OneMux $end +$var wire 1 ;2 S0 $end +$var wire 1 <2 S1 $end +$var wire 1 =2 in0 $end +$var wire 1 >2 in1 $end +$var wire 1 ?2 in2 $end +$var wire 1 @2 in3 $end +$var wire 1 A2 nS0 $end +$var wire 1 B2 nS1 $end +$var wire 1 C2 out $end +$var wire 1 D2 out0 $end +$var wire 1 E2 out1 $end +$var wire 1 F2 out2 $end +$var wire 1 G2 out3 $end +$upscope $end +$scope module TwoMux $end +$var wire 1 H2 S $end +$var wire 1 I2 in0 $end +$var wire 1 J2 in1 $end +$var wire 1 K2 nS $end +$var wire 1 L2 out0 $end +$var wire 1 M2 out1 $end +$var wire 1 N2 outfinal $end +$upscope $end +$upscope $end +$scope begin muxbits[5] $end +$scope module ZeroMux $end +$var wire 1 O2 S0 $end +$var wire 1 P2 S1 $end +$var wire 1 Q2 in0 $end +$var wire 1 R2 in1 $end +$var wire 1 S2 in2 $end +$var wire 1 T2 in3 $end +$var wire 1 U2 nS0 $end +$var wire 1 V2 nS1 $end +$var wire 1 W2 out $end +$var wire 1 X2 out0 $end +$var wire 1 Y2 out1 $end +$var wire 1 Z2 out2 $end +$var wire 1 [2 out3 $end +$upscope $end +$scope module OneMux $end +$var wire 1 \2 S0 $end +$var wire 1 ]2 S1 $end +$var wire 1 ^2 in0 $end +$var wire 1 _2 in1 $end +$var wire 1 `2 in2 $end +$var wire 1 a2 in3 $end +$var wire 1 b2 nS0 $end +$var wire 1 c2 nS1 $end +$var wire 1 d2 out $end +$var wire 1 e2 out0 $end +$var wire 1 f2 out1 $end +$var wire 1 g2 out2 $end +$var wire 1 h2 out3 $end +$upscope $end +$scope module TwoMux $end +$var wire 1 i2 S $end +$var wire 1 j2 in0 $end +$var wire 1 k2 in1 $end +$var wire 1 l2 nS $end +$var wire 1 m2 out0 $end +$var wire 1 n2 out1 $end +$var wire 1 o2 outfinal $end +$upscope $end +$upscope $end +$scope begin muxbits[6] $end +$scope module ZeroMux $end +$var wire 1 p2 S0 $end +$var wire 1 q2 S1 $end +$var wire 1 r2 in0 $end +$var wire 1 s2 in1 $end +$var wire 1 t2 in2 $end +$var wire 1 u2 in3 $end +$var wire 1 v2 nS0 $end +$var wire 1 w2 nS1 $end +$var wire 1 x2 out $end +$var wire 1 y2 out0 $end +$var wire 1 z2 out1 $end +$var wire 1 {2 out2 $end +$var wire 1 |2 out3 $end +$upscope $end +$scope module OneMux $end +$var wire 1 }2 S0 $end +$var wire 1 ~2 S1 $end +$var wire 1 !3 in0 $end +$var wire 1 "3 in1 $end +$var wire 1 #3 in2 $end +$var wire 1 $3 in3 $end +$var wire 1 %3 nS0 $end +$var wire 1 &3 nS1 $end +$var wire 1 '3 out $end +$var wire 1 (3 out0 $end +$var wire 1 )3 out1 $end +$var wire 1 *3 out2 $end +$var wire 1 +3 out3 $end +$upscope $end +$scope module TwoMux $end +$var wire 1 ,3 S $end +$var wire 1 -3 in0 $end +$var wire 1 .3 in1 $end +$var wire 1 /3 nS $end +$var wire 1 03 out0 $end +$var wire 1 13 out1 $end +$var wire 1 23 outfinal $end +$upscope $end +$upscope $end +$scope begin muxbits[7] $end +$scope module ZeroMux $end +$var wire 1 33 S0 $end +$var wire 1 43 S1 $end +$var wire 1 53 in0 $end +$var wire 1 63 in1 $end +$var wire 1 73 in2 $end +$var wire 1 83 in3 $end +$var wire 1 93 nS0 $end +$var wire 1 :3 nS1 $end +$var wire 1 ;3 out $end +$var wire 1 <3 out0 $end +$var wire 1 =3 out1 $end +$var wire 1 >3 out2 $end +$var wire 1 ?3 out3 $end +$upscope $end +$scope module OneMux $end +$var wire 1 @3 S0 $end +$var wire 1 A3 S1 $end +$var wire 1 B3 in0 $end +$var wire 1 C3 in1 $end +$var wire 1 D3 in2 $end +$var wire 1 E3 in3 $end +$var wire 1 F3 nS0 $end +$var wire 1 G3 nS1 $end +$var wire 1 H3 out $end +$var wire 1 I3 out0 $end +$var wire 1 J3 out1 $end +$var wire 1 K3 out2 $end +$var wire 1 L3 out3 $end +$upscope $end +$scope module TwoMux $end +$var wire 1 M3 S $end +$var wire 1 N3 in0 $end +$var wire 1 O3 in1 $end +$var wire 1 P3 nS $end +$var wire 1 Q3 out0 $end +$var wire 1 R3 out1 $end +$var wire 1 S3 outfinal $end +$upscope $end +$upscope $end +$scope begin muxbits[8] $end +$scope module ZeroMux $end +$var wire 1 T3 S0 $end +$var wire 1 U3 S1 $end +$var wire 1 V3 in0 $end +$var wire 1 W3 in1 $end +$var wire 1 X3 in2 $end +$var wire 1 Y3 in3 $end +$var wire 1 Z3 nS0 $end +$var wire 1 [3 nS1 $end +$var wire 1 \3 out $end +$var wire 1 ]3 out0 $end +$var wire 1 ^3 out1 $end +$var wire 1 _3 out2 $end +$var wire 1 `3 out3 $end +$upscope $end +$scope module OneMux $end +$var wire 1 a3 S0 $end +$var wire 1 b3 S1 $end +$var wire 1 c3 in0 $end +$var wire 1 d3 in1 $end +$var wire 1 e3 in2 $end +$var wire 1 f3 in3 $end +$var wire 1 g3 nS0 $end +$var wire 1 h3 nS1 $end +$var wire 1 i3 out $end +$var wire 1 j3 out0 $end +$var wire 1 k3 out1 $end +$var wire 1 l3 out2 $end +$var wire 1 m3 out3 $end +$upscope $end +$scope module TwoMux $end +$var wire 1 n3 S $end +$var wire 1 o3 in0 $end +$var wire 1 p3 in1 $end +$var wire 1 q3 nS $end +$var wire 1 r3 out0 $end +$var wire 1 s3 out1 $end +$var wire 1 t3 outfinal $end +$upscope $end +$upscope $end +$scope begin muxbits[9] $end +$scope module ZeroMux $end +$var wire 1 u3 S0 $end +$var wire 1 v3 S1 $end +$var wire 1 w3 in0 $end +$var wire 1 x3 in1 $end +$var wire 1 y3 in2 $end +$var wire 1 z3 in3 $end +$var wire 1 {3 nS0 $end +$var wire 1 |3 nS1 $end +$var wire 1 }3 out $end +$var wire 1 ~3 out0 $end +$var wire 1 !4 out1 $end +$var wire 1 "4 out2 $end +$var wire 1 #4 out3 $end +$upscope $end +$scope module OneMux $end +$var wire 1 $4 S0 $end +$var wire 1 %4 S1 $end +$var wire 1 &4 in0 $end +$var wire 1 '4 in1 $end +$var wire 1 (4 in2 $end +$var wire 1 )4 in3 $end +$var wire 1 *4 nS0 $end +$var wire 1 +4 nS1 $end +$var wire 1 ,4 out $end +$var wire 1 -4 out0 $end +$var wire 1 .4 out1 $end +$var wire 1 /4 out2 $end +$var wire 1 04 out3 $end +$upscope $end +$scope module TwoMux $end +$var wire 1 14 S $end +$var wire 1 24 in0 $end +$var wire 1 34 in1 $end +$var wire 1 44 nS $end +$var wire 1 54 out0 $end +$var wire 1 64 out1 $end +$var wire 1 74 outfinal $end +$upscope $end +$upscope $end +$scope begin muxbits[10] $end +$scope module ZeroMux $end +$var wire 1 84 S0 $end +$var wire 1 94 S1 $end +$var wire 1 :4 in0 $end +$var wire 1 ;4 in1 $end +$var wire 1 <4 in2 $end +$var wire 1 =4 in3 $end +$var wire 1 >4 nS0 $end +$var wire 1 ?4 nS1 $end +$var wire 1 @4 out $end +$var wire 1 A4 out0 $end +$var wire 1 B4 out1 $end +$var wire 1 C4 out2 $end +$var wire 1 D4 out3 $end +$upscope $end +$scope module OneMux $end +$var wire 1 E4 S0 $end +$var wire 1 F4 S1 $end +$var wire 1 G4 in0 $end +$var wire 1 H4 in1 $end +$var wire 1 I4 in2 $end +$var wire 1 J4 in3 $end +$var wire 1 K4 nS0 $end +$var wire 1 L4 nS1 $end +$var wire 1 M4 out $end +$var wire 1 N4 out0 $end +$var wire 1 O4 out1 $end +$var wire 1 P4 out2 $end +$var wire 1 Q4 out3 $end +$upscope $end +$scope module TwoMux $end +$var wire 1 R4 S $end +$var wire 1 S4 in0 $end +$var wire 1 T4 in1 $end +$var wire 1 U4 nS $end +$var wire 1 V4 out0 $end +$var wire 1 W4 out1 $end +$var wire 1 X4 outfinal $end +$upscope $end +$upscope $end +$scope begin muxbits[11] $end +$scope module ZeroMux $end +$var wire 1 Y4 S0 $end +$var wire 1 Z4 S1 $end +$var wire 1 [4 in0 $end +$var wire 1 \4 in1 $end +$var wire 1 ]4 in2 $end +$var wire 1 ^4 in3 $end +$var wire 1 _4 nS0 $end +$var wire 1 `4 nS1 $end +$var wire 1 a4 out $end +$var wire 1 b4 out0 $end +$var wire 1 c4 out1 $end +$var wire 1 d4 out2 $end +$var wire 1 e4 out3 $end +$upscope $end +$scope module OneMux $end +$var wire 1 f4 S0 $end +$var wire 1 g4 S1 $end +$var wire 1 h4 in0 $end +$var wire 1 i4 in1 $end +$var wire 1 j4 in2 $end +$var wire 1 k4 in3 $end +$var wire 1 l4 nS0 $end +$var wire 1 m4 nS1 $end +$var wire 1 n4 out $end +$var wire 1 o4 out0 $end +$var wire 1 p4 out1 $end +$var wire 1 q4 out2 $end +$var wire 1 r4 out3 $end +$upscope $end +$scope module TwoMux $end +$var wire 1 s4 S $end +$var wire 1 t4 in0 $end +$var wire 1 u4 in1 $end +$var wire 1 v4 nS $end +$var wire 1 w4 out0 $end +$var wire 1 x4 out1 $end +$var wire 1 y4 outfinal $end +$upscope $end +$upscope $end +$scope begin muxbits[12] $end +$scope module ZeroMux $end +$var wire 1 z4 S0 $end +$var wire 1 {4 S1 $end +$var wire 1 |4 in0 $end +$var wire 1 }4 in1 $end +$var wire 1 ~4 in2 $end +$var wire 1 !5 in3 $end +$var wire 1 "5 nS0 $end +$var wire 1 #5 nS1 $end +$var wire 1 $5 out $end +$var wire 1 %5 out0 $end +$var wire 1 &5 out1 $end +$var wire 1 '5 out2 $end +$var wire 1 (5 out3 $end +$upscope $end +$scope module OneMux $end +$var wire 1 )5 S0 $end +$var wire 1 *5 S1 $end +$var wire 1 +5 in0 $end +$var wire 1 ,5 in1 $end +$var wire 1 -5 in2 $end +$var wire 1 .5 in3 $end +$var wire 1 /5 nS0 $end +$var wire 1 05 nS1 $end +$var wire 1 15 out $end +$var wire 1 25 out0 $end +$var wire 1 35 out1 $end +$var wire 1 45 out2 $end +$var wire 1 55 out3 $end +$upscope $end +$scope module TwoMux $end +$var wire 1 65 S $end +$var wire 1 75 in0 $end +$var wire 1 85 in1 $end +$var wire 1 95 nS $end +$var wire 1 :5 out0 $end +$var wire 1 ;5 out1 $end +$var wire 1 <5 outfinal $end +$upscope $end +$upscope $end +$scope begin muxbits[13] $end +$scope module ZeroMux $end +$var wire 1 =5 S0 $end +$var wire 1 >5 S1 $end +$var wire 1 ?5 in0 $end +$var wire 1 @5 in1 $end +$var wire 1 A5 in2 $end +$var wire 1 B5 in3 $end +$var wire 1 C5 nS0 $end +$var wire 1 D5 nS1 $end +$var wire 1 E5 out $end +$var wire 1 F5 out0 $end +$var wire 1 G5 out1 $end +$var wire 1 H5 out2 $end +$var wire 1 I5 out3 $end +$upscope $end +$scope module OneMux $end +$var wire 1 J5 S0 $end +$var wire 1 K5 S1 $end +$var wire 1 L5 in0 $end +$var wire 1 M5 in1 $end +$var wire 1 N5 in2 $end +$var wire 1 O5 in3 $end +$var wire 1 P5 nS0 $end +$var wire 1 Q5 nS1 $end +$var wire 1 R5 out $end +$var wire 1 S5 out0 $end +$var wire 1 T5 out1 $end +$var wire 1 U5 out2 $end +$var wire 1 V5 out3 $end +$upscope $end +$scope module TwoMux $end +$var wire 1 W5 S $end +$var wire 1 X5 in0 $end +$var wire 1 Y5 in1 $end +$var wire 1 Z5 nS $end +$var wire 1 [5 out0 $end +$var wire 1 \5 out1 $end +$var wire 1 ]5 outfinal $end +$upscope $end +$upscope $end +$scope begin muxbits[14] $end +$scope module ZeroMux $end +$var wire 1 ^5 S0 $end +$var wire 1 _5 S1 $end +$var wire 1 `5 in0 $end +$var wire 1 a5 in1 $end +$var wire 1 b5 in2 $end +$var wire 1 c5 in3 $end +$var wire 1 d5 nS0 $end +$var wire 1 e5 nS1 $end +$var wire 1 f5 out $end +$var wire 1 g5 out0 $end +$var wire 1 h5 out1 $end +$var wire 1 i5 out2 $end +$var wire 1 j5 out3 $end +$upscope $end +$scope module OneMux $end +$var wire 1 k5 S0 $end +$var wire 1 l5 S1 $end +$var wire 1 m5 in0 $end +$var wire 1 n5 in1 $end +$var wire 1 o5 in2 $end +$var wire 1 p5 in3 $end +$var wire 1 q5 nS0 $end +$var wire 1 r5 nS1 $end +$var wire 1 s5 out $end +$var wire 1 t5 out0 $end +$var wire 1 u5 out1 $end +$var wire 1 v5 out2 $end +$var wire 1 w5 out3 $end +$upscope $end +$scope module TwoMux $end +$var wire 1 x5 S $end +$var wire 1 y5 in0 $end +$var wire 1 z5 in1 $end +$var wire 1 {5 nS $end +$var wire 1 |5 out0 $end +$var wire 1 }5 out1 $end +$var wire 1 ~5 outfinal $end +$upscope $end +$upscope $end +$scope begin muxbits[15] $end +$scope module ZeroMux $end +$var wire 1 !6 S0 $end +$var wire 1 "6 S1 $end +$var wire 1 #6 in0 $end +$var wire 1 $6 in1 $end +$var wire 1 %6 in2 $end +$var wire 1 &6 in3 $end +$var wire 1 '6 nS0 $end +$var wire 1 (6 nS1 $end +$var wire 1 )6 out $end +$var wire 1 *6 out0 $end +$var wire 1 +6 out1 $end +$var wire 1 ,6 out2 $end +$var wire 1 -6 out3 $end +$upscope $end +$scope module OneMux $end +$var wire 1 .6 S0 $end +$var wire 1 /6 S1 $end +$var wire 1 06 in0 $end +$var wire 1 16 in1 $end +$var wire 1 26 in2 $end +$var wire 1 36 in3 $end +$var wire 1 46 nS0 $end +$var wire 1 56 nS1 $end +$var wire 1 66 out $end +$var wire 1 76 out0 $end +$var wire 1 86 out1 $end +$var wire 1 96 out2 $end +$var wire 1 :6 out3 $end +$upscope $end +$scope module TwoMux $end +$var wire 1 ;6 S $end +$var wire 1 <6 in0 $end +$var wire 1 =6 in1 $end +$var wire 1 >6 nS $end +$var wire 1 ?6 out0 $end +$var wire 1 @6 out1 $end +$var wire 1 A6 outfinal $end +$upscope $end +$upscope $end +$scope begin muxbits[16] $end +$scope module ZeroMux $end +$var wire 1 B6 S0 $end +$var wire 1 C6 S1 $end +$var wire 1 D6 in0 $end +$var wire 1 E6 in1 $end +$var wire 1 F6 in2 $end +$var wire 1 G6 in3 $end +$var wire 1 H6 nS0 $end +$var wire 1 I6 nS1 $end +$var wire 1 J6 out $end +$var wire 1 K6 out0 $end +$var wire 1 L6 out1 $end +$var wire 1 M6 out2 $end +$var wire 1 N6 out3 $end +$upscope $end +$scope module OneMux $end +$var wire 1 O6 S0 $end +$var wire 1 P6 S1 $end +$var wire 1 Q6 in0 $end +$var wire 1 R6 in1 $end +$var wire 1 S6 in2 $end +$var wire 1 T6 in3 $end +$var wire 1 U6 nS0 $end +$var wire 1 V6 nS1 $end +$var wire 1 W6 out $end +$var wire 1 X6 out0 $end +$var wire 1 Y6 out1 $end +$var wire 1 Z6 out2 $end +$var wire 1 [6 out3 $end +$upscope $end +$scope module TwoMux $end +$var wire 1 \6 S $end +$var wire 1 ]6 in0 $end +$var wire 1 ^6 in1 $end +$var wire 1 _6 nS $end +$var wire 1 `6 out0 $end +$var wire 1 a6 out1 $end +$var wire 1 b6 outfinal $end +$upscope $end +$upscope $end +$scope begin muxbits[17] $end +$scope module ZeroMux $end +$var wire 1 c6 S0 $end +$var wire 1 d6 S1 $end +$var wire 1 e6 in0 $end +$var wire 1 f6 in1 $end +$var wire 1 g6 in2 $end +$var wire 1 h6 in3 $end +$var wire 1 i6 nS0 $end +$var wire 1 j6 nS1 $end +$var wire 1 k6 out $end +$var wire 1 l6 out0 $end +$var wire 1 m6 out1 $end +$var wire 1 n6 out2 $end +$var wire 1 o6 out3 $end +$upscope $end +$scope module OneMux $end +$var wire 1 p6 S0 $end +$var wire 1 q6 S1 $end +$var wire 1 r6 in0 $end +$var wire 1 s6 in1 $end +$var wire 1 t6 in2 $end +$var wire 1 u6 in3 $end +$var wire 1 v6 nS0 $end +$var wire 1 w6 nS1 $end +$var wire 1 x6 out $end +$var wire 1 y6 out0 $end +$var wire 1 z6 out1 $end +$var wire 1 {6 out2 $end +$var wire 1 |6 out3 $end +$upscope $end +$scope module TwoMux $end +$var wire 1 }6 S $end +$var wire 1 ~6 in0 $end +$var wire 1 !7 in1 $end +$var wire 1 "7 nS $end +$var wire 1 #7 out0 $end +$var wire 1 $7 out1 $end +$var wire 1 %7 outfinal $end +$upscope $end +$upscope $end +$scope begin muxbits[18] $end +$scope module ZeroMux $end +$var wire 1 &7 S0 $end +$var wire 1 '7 S1 $end +$var wire 1 (7 in0 $end +$var wire 1 )7 in1 $end +$var wire 1 *7 in2 $end +$var wire 1 +7 in3 $end +$var wire 1 ,7 nS0 $end +$var wire 1 -7 nS1 $end +$var wire 1 .7 out $end +$var wire 1 /7 out0 $end +$var wire 1 07 out1 $end +$var wire 1 17 out2 $end +$var wire 1 27 out3 $end +$upscope $end +$scope module OneMux $end +$var wire 1 37 S0 $end +$var wire 1 47 S1 $end +$var wire 1 57 in0 $end +$var wire 1 67 in1 $end +$var wire 1 77 in2 $end +$var wire 1 87 in3 $end +$var wire 1 97 nS0 $end +$var wire 1 :7 nS1 $end +$var wire 1 ;7 out $end +$var wire 1 <7 out0 $end +$var wire 1 =7 out1 $end +$var wire 1 >7 out2 $end +$var wire 1 ?7 out3 $end +$upscope $end +$scope module TwoMux $end +$var wire 1 @7 S $end +$var wire 1 A7 in0 $end +$var wire 1 B7 in1 $end +$var wire 1 C7 nS $end +$var wire 1 D7 out0 $end +$var wire 1 E7 out1 $end +$var wire 1 F7 outfinal $end +$upscope $end +$upscope $end +$scope begin muxbits[19] $end +$scope module ZeroMux $end +$var wire 1 G7 S0 $end +$var wire 1 H7 S1 $end +$var wire 1 I7 in0 $end +$var wire 1 J7 in1 $end +$var wire 1 K7 in2 $end +$var wire 1 L7 in3 $end +$var wire 1 M7 nS0 $end +$var wire 1 N7 nS1 $end +$var wire 1 O7 out $end +$var wire 1 P7 out0 $end +$var wire 1 Q7 out1 $end +$var wire 1 R7 out2 $end +$var wire 1 S7 out3 $end +$upscope $end +$scope module OneMux $end +$var wire 1 T7 S0 $end +$var wire 1 U7 S1 $end +$var wire 1 V7 in0 $end +$var wire 1 W7 in1 $end +$var wire 1 X7 in2 $end +$var wire 1 Y7 in3 $end +$var wire 1 Z7 nS0 $end +$var wire 1 [7 nS1 $end +$var wire 1 \7 out $end +$var wire 1 ]7 out0 $end +$var wire 1 ^7 out1 $end +$var wire 1 _7 out2 $end +$var wire 1 `7 out3 $end +$upscope $end +$scope module TwoMux $end +$var wire 1 a7 S $end +$var wire 1 b7 in0 $end +$var wire 1 c7 in1 $end +$var wire 1 d7 nS $end +$var wire 1 e7 out0 $end +$var wire 1 f7 out1 $end +$var wire 1 g7 outfinal $end +$upscope $end +$upscope $end +$scope begin muxbits[20] $end +$scope module ZeroMux $end +$var wire 1 h7 S0 $end +$var wire 1 i7 S1 $end +$var wire 1 j7 in0 $end +$var wire 1 k7 in1 $end +$var wire 1 l7 in2 $end +$var wire 1 m7 in3 $end +$var wire 1 n7 nS0 $end +$var wire 1 o7 nS1 $end +$var wire 1 p7 out $end +$var wire 1 q7 out0 $end +$var wire 1 r7 out1 $end +$var wire 1 s7 out2 $end +$var wire 1 t7 out3 $end +$upscope $end +$scope module OneMux $end +$var wire 1 u7 S0 $end +$var wire 1 v7 S1 $end +$var wire 1 w7 in0 $end +$var wire 1 x7 in1 $end +$var wire 1 y7 in2 $end +$var wire 1 z7 in3 $end +$var wire 1 {7 nS0 $end +$var wire 1 |7 nS1 $end +$var wire 1 }7 out $end +$var wire 1 ~7 out0 $end +$var wire 1 !8 out1 $end +$var wire 1 "8 out2 $end +$var wire 1 #8 out3 $end +$upscope $end +$scope module TwoMux $end +$var wire 1 $8 S $end +$var wire 1 %8 in0 $end +$var wire 1 &8 in1 $end +$var wire 1 '8 nS $end +$var wire 1 (8 out0 $end +$var wire 1 )8 out1 $end +$var wire 1 *8 outfinal $end +$upscope $end +$upscope $end +$scope begin muxbits[21] $end +$scope module ZeroMux $end +$var wire 1 +8 S0 $end +$var wire 1 ,8 S1 $end +$var wire 1 -8 in0 $end +$var wire 1 .8 in1 $end +$var wire 1 /8 in2 $end +$var wire 1 08 in3 $end +$var wire 1 18 nS0 $end +$var wire 1 28 nS1 $end +$var wire 1 38 out $end +$var wire 1 48 out0 $end +$var wire 1 58 out1 $end +$var wire 1 68 out2 $end +$var wire 1 78 out3 $end +$upscope $end +$scope module OneMux $end +$var wire 1 88 S0 $end +$var wire 1 98 S1 $end +$var wire 1 :8 in0 $end +$var wire 1 ;8 in1 $end +$var wire 1 <8 in2 $end +$var wire 1 =8 in3 $end +$var wire 1 >8 nS0 $end +$var wire 1 ?8 nS1 $end +$var wire 1 @8 out $end +$var wire 1 A8 out0 $end +$var wire 1 B8 out1 $end +$var wire 1 C8 out2 $end +$var wire 1 D8 out3 $end +$upscope $end +$scope module TwoMux $end +$var wire 1 E8 S $end +$var wire 1 F8 in0 $end +$var wire 1 G8 in1 $end +$var wire 1 H8 nS $end +$var wire 1 I8 out0 $end +$var wire 1 J8 out1 $end +$var wire 1 K8 outfinal $end +$upscope $end +$upscope $end +$scope begin muxbits[22] $end +$scope module ZeroMux $end +$var wire 1 L8 S0 $end +$var wire 1 M8 S1 $end +$var wire 1 N8 in0 $end +$var wire 1 O8 in1 $end +$var wire 1 P8 in2 $end +$var wire 1 Q8 in3 $end +$var wire 1 R8 nS0 $end +$var wire 1 S8 nS1 $end +$var wire 1 T8 out $end +$var wire 1 U8 out0 $end +$var wire 1 V8 out1 $end +$var wire 1 W8 out2 $end +$var wire 1 X8 out3 $end +$upscope $end +$scope module OneMux $end +$var wire 1 Y8 S0 $end +$var wire 1 Z8 S1 $end +$var wire 1 [8 in0 $end +$var wire 1 \8 in1 $end +$var wire 1 ]8 in2 $end +$var wire 1 ^8 in3 $end +$var wire 1 _8 nS0 $end +$var wire 1 `8 nS1 $end +$var wire 1 a8 out $end +$var wire 1 b8 out0 $end +$var wire 1 c8 out1 $end +$var wire 1 d8 out2 $end +$var wire 1 e8 out3 $end +$upscope $end +$scope module TwoMux $end +$var wire 1 f8 S $end +$var wire 1 g8 in0 $end +$var wire 1 h8 in1 $end +$var wire 1 i8 nS $end +$var wire 1 j8 out0 $end +$var wire 1 k8 out1 $end +$var wire 1 l8 outfinal $end +$upscope $end +$upscope $end +$scope begin muxbits[23] $end +$scope module ZeroMux $end +$var wire 1 m8 S0 $end +$var wire 1 n8 S1 $end +$var wire 1 o8 in0 $end +$var wire 1 p8 in1 $end +$var wire 1 q8 in2 $end +$var wire 1 r8 in3 $end +$var wire 1 s8 nS0 $end +$var wire 1 t8 nS1 $end +$var wire 1 u8 out $end +$var wire 1 v8 out0 $end +$var wire 1 w8 out1 $end +$var wire 1 x8 out2 $end +$var wire 1 y8 out3 $end +$upscope $end +$scope module OneMux $end +$var wire 1 z8 S0 $end +$var wire 1 {8 S1 $end +$var wire 1 |8 in0 $end +$var wire 1 }8 in1 $end +$var wire 1 ~8 in2 $end +$var wire 1 !9 in3 $end +$var wire 1 "9 nS0 $end +$var wire 1 #9 nS1 $end +$var wire 1 $9 out $end +$var wire 1 %9 out0 $end +$var wire 1 &9 out1 $end +$var wire 1 '9 out2 $end +$var wire 1 (9 out3 $end +$upscope $end +$scope module TwoMux $end +$var wire 1 )9 S $end +$var wire 1 *9 in0 $end +$var wire 1 +9 in1 $end +$var wire 1 ,9 nS $end +$var wire 1 -9 out0 $end +$var wire 1 .9 out1 $end +$var wire 1 /9 outfinal $end +$upscope $end +$upscope $end +$scope begin muxbits[24] $end +$scope module ZeroMux $end +$var wire 1 09 S0 $end +$var wire 1 19 S1 $end +$var wire 1 29 in0 $end +$var wire 1 39 in1 $end +$var wire 1 49 in2 $end +$var wire 1 59 in3 $end +$var wire 1 69 nS0 $end +$var wire 1 79 nS1 $end +$var wire 1 89 out $end +$var wire 1 99 out0 $end +$var wire 1 :9 out1 $end +$var wire 1 ;9 out2 $end +$var wire 1 <9 out3 $end +$upscope $end +$scope module OneMux $end +$var wire 1 =9 S0 $end +$var wire 1 >9 S1 $end +$var wire 1 ?9 in0 $end +$var wire 1 @9 in1 $end +$var wire 1 A9 in2 $end +$var wire 1 B9 in3 $end +$var wire 1 C9 nS0 $end +$var wire 1 D9 nS1 $end +$var wire 1 E9 out $end +$var wire 1 F9 out0 $end +$var wire 1 G9 out1 $end +$var wire 1 H9 out2 $end +$var wire 1 I9 out3 $end +$upscope $end +$scope module TwoMux $end +$var wire 1 J9 S $end +$var wire 1 K9 in0 $end +$var wire 1 L9 in1 $end +$var wire 1 M9 nS $end +$var wire 1 N9 out0 $end +$var wire 1 O9 out1 $end +$var wire 1 P9 outfinal $end +$upscope $end +$upscope $end +$scope begin muxbits[25] $end +$scope module ZeroMux $end +$var wire 1 Q9 S0 $end +$var wire 1 R9 S1 $end +$var wire 1 S9 in0 $end +$var wire 1 T9 in1 $end +$var wire 1 U9 in2 $end +$var wire 1 V9 in3 $end +$var wire 1 W9 nS0 $end +$var wire 1 X9 nS1 $end +$var wire 1 Y9 out $end +$var wire 1 Z9 out0 $end +$var wire 1 [9 out1 $end +$var wire 1 \9 out2 $end +$var wire 1 ]9 out3 $end +$upscope $end +$scope module OneMux $end +$var wire 1 ^9 S0 $end +$var wire 1 _9 S1 $end +$var wire 1 `9 in0 $end +$var wire 1 a9 in1 $end +$var wire 1 b9 in2 $end +$var wire 1 c9 in3 $end +$var wire 1 d9 nS0 $end +$var wire 1 e9 nS1 $end +$var wire 1 f9 out $end +$var wire 1 g9 out0 $end +$var wire 1 h9 out1 $end +$var wire 1 i9 out2 $end +$var wire 1 j9 out3 $end +$upscope $end +$scope module TwoMux $end +$var wire 1 k9 S $end +$var wire 1 l9 in0 $end +$var wire 1 m9 in1 $end +$var wire 1 n9 nS $end +$var wire 1 o9 out0 $end +$var wire 1 p9 out1 $end +$var wire 1 q9 outfinal $end +$upscope $end +$upscope $end +$scope begin muxbits[26] $end +$scope module ZeroMux $end +$var wire 1 r9 S0 $end +$var wire 1 s9 S1 $end +$var wire 1 t9 in0 $end +$var wire 1 u9 in1 $end +$var wire 1 v9 in2 $end +$var wire 1 w9 in3 $end +$var wire 1 x9 nS0 $end +$var wire 1 y9 nS1 $end +$var wire 1 z9 out $end +$var wire 1 {9 out0 $end +$var wire 1 |9 out1 $end +$var wire 1 }9 out2 $end +$var wire 1 ~9 out3 $end +$upscope $end +$scope module OneMux $end +$var wire 1 !: S0 $end +$var wire 1 ": S1 $end +$var wire 1 #: in0 $end +$var wire 1 $: in1 $end +$var wire 1 %: in2 $end +$var wire 1 &: in3 $end +$var wire 1 ': nS0 $end +$var wire 1 (: nS1 $end +$var wire 1 ): out $end +$var wire 1 *: out0 $end +$var wire 1 +: out1 $end +$var wire 1 ,: out2 $end +$var wire 1 -: out3 $end +$upscope $end +$scope module TwoMux $end +$var wire 1 .: S $end +$var wire 1 /: in0 $end +$var wire 1 0: in1 $end +$var wire 1 1: nS $end +$var wire 1 2: out0 $end +$var wire 1 3: out1 $end +$var wire 1 4: outfinal $end +$upscope $end +$upscope $end +$scope begin muxbits[27] $end +$scope module ZeroMux $end +$var wire 1 5: S0 $end +$var wire 1 6: S1 $end +$var wire 1 7: in0 $end +$var wire 1 8: in1 $end +$var wire 1 9: in2 $end +$var wire 1 :: in3 $end +$var wire 1 ;: nS0 $end +$var wire 1 <: nS1 $end +$var wire 1 =: out $end +$var wire 1 >: out0 $end +$var wire 1 ?: out1 $end +$var wire 1 @: out2 $end +$var wire 1 A: out3 $end +$upscope $end +$scope module OneMux $end +$var wire 1 B: S0 $end +$var wire 1 C: S1 $end +$var wire 1 D: in0 $end +$var wire 1 E: in1 $end +$var wire 1 F: in2 $end +$var wire 1 G: in3 $end +$var wire 1 H: nS0 $end +$var wire 1 I: nS1 $end +$var wire 1 J: out $end +$var wire 1 K: out0 $end +$var wire 1 L: out1 $end +$var wire 1 M: out2 $end +$var wire 1 N: out3 $end +$upscope $end +$scope module TwoMux $end +$var wire 1 O: S $end +$var wire 1 P: in0 $end +$var wire 1 Q: in1 $end +$var wire 1 R: nS $end +$var wire 1 S: out0 $end +$var wire 1 T: out1 $end +$var wire 1 U: outfinal $end +$upscope $end +$upscope $end +$scope begin muxbits[28] $end +$scope module ZeroMux $end +$var wire 1 V: S0 $end +$var wire 1 W: S1 $end +$var wire 1 X: in0 $end +$var wire 1 Y: in1 $end +$var wire 1 Z: in2 $end +$var wire 1 [: in3 $end +$var wire 1 \: nS0 $end +$var wire 1 ]: nS1 $end +$var wire 1 ^: out $end +$var wire 1 _: out0 $end +$var wire 1 `: out1 $end +$var wire 1 a: out2 $end +$var wire 1 b: out3 $end +$upscope $end +$scope module OneMux $end +$var wire 1 c: S0 $end +$var wire 1 d: S1 $end +$var wire 1 e: in0 $end +$var wire 1 f: in1 $end +$var wire 1 g: in2 $end +$var wire 1 h: in3 $end +$var wire 1 i: nS0 $end +$var wire 1 j: nS1 $end +$var wire 1 k: out $end +$var wire 1 l: out0 $end +$var wire 1 m: out1 $end +$var wire 1 n: out2 $end +$var wire 1 o: out3 $end +$upscope $end +$scope module TwoMux $end +$var wire 1 p: S $end +$var wire 1 q: in0 $end +$var wire 1 r: in1 $end +$var wire 1 s: nS $end +$var wire 1 t: out0 $end +$var wire 1 u: out1 $end +$var wire 1 v: outfinal $end +$upscope $end +$upscope $end +$scope begin muxbits[29] $end +$scope module ZeroMux $end +$var wire 1 w: S0 $end +$var wire 1 x: S1 $end +$var wire 1 y: in0 $end +$var wire 1 z: in1 $end +$var wire 1 {: in2 $end +$var wire 1 |: in3 $end +$var wire 1 }: nS0 $end +$var wire 1 ~: nS1 $end +$var wire 1 !; out $end +$var wire 1 "; out0 $end +$var wire 1 #; out1 $end +$var wire 1 $; out2 $end +$var wire 1 %; out3 $end +$upscope $end +$scope module OneMux $end +$var wire 1 &; S0 $end +$var wire 1 '; S1 $end +$var wire 1 (; in0 $end +$var wire 1 ); in1 $end +$var wire 1 *; in2 $end +$var wire 1 +; in3 $end +$var wire 1 ,; nS0 $end +$var wire 1 -; nS1 $end +$var wire 1 .; out $end +$var wire 1 /; out0 $end +$var wire 1 0; out1 $end +$var wire 1 1; out2 $end +$var wire 1 2; out3 $end +$upscope $end +$scope module TwoMux $end +$var wire 1 3; S $end +$var wire 1 4; in0 $end +$var wire 1 5; in1 $end +$var wire 1 6; nS $end +$var wire 1 7; out0 $end +$var wire 1 8; out1 $end +$var wire 1 9; outfinal $end +$upscope $end +$upscope $end +$scope begin muxbits[30] $end +$scope module ZeroMux $end +$var wire 1 :; S0 $end +$var wire 1 ;; S1 $end +$var wire 1 <; in0 $end +$var wire 1 =; in1 $end +$var wire 1 >; in2 $end +$var wire 1 ?; in3 $end +$var wire 1 @; nS0 $end +$var wire 1 A; nS1 $end +$var wire 1 B; out $end +$var wire 1 C; out0 $end +$var wire 1 D; out1 $end +$var wire 1 E; out2 $end +$var wire 1 F; out3 $end +$upscope $end +$scope module OneMux $end +$var wire 1 G; S0 $end +$var wire 1 H; S1 $end +$var wire 1 I; in0 $end +$var wire 1 J; in1 $end +$var wire 1 K; in2 $end +$var wire 1 L; in3 $end +$var wire 1 M; nS0 $end +$var wire 1 N; nS1 $end +$var wire 1 O; out $end +$var wire 1 P; out0 $end +$var wire 1 Q; out1 $end +$var wire 1 R; out2 $end +$var wire 1 S; out3 $end +$upscope $end +$scope module TwoMux $end +$var wire 1 T; S $end +$var wire 1 U; in0 $end +$var wire 1 V; in1 $end +$var wire 1 W; nS $end +$var wire 1 X; out0 $end +$var wire 1 Y; out1 $end +$var wire 1 Z; outfinal $end +$upscope $end +$upscope $end +$scope begin muxbits[31] $end +$scope module ZeroMux $end +$var wire 1 [; S0 $end +$var wire 1 \; S1 $end +$var wire 1 ]; in0 $end +$var wire 1 ^; in1 $end +$var wire 1 _; in2 $end +$var wire 1 `; in3 $end +$var wire 1 a; nS0 $end +$var wire 1 b; nS1 $end +$var wire 1 c; out $end +$var wire 1 d; out0 $end +$var wire 1 e; out1 $end +$var wire 1 f; out2 $end +$var wire 1 g; out3 $end +$upscope $end +$scope module OneMux $end +$var wire 1 h; S0 $end +$var wire 1 i; S1 $end +$var wire 1 j; in0 $end +$var wire 1 k; in1 $end +$var wire 1 l; in2 $end +$var wire 1 m; in3 $end +$var wire 1 n; nS0 $end +$var wire 1 o; nS1 $end +$var wire 1 p; out $end +$var wire 1 q; out0 $end +$var wire 1 r; out1 $end +$var wire 1 s; out2 $end +$var wire 1 t; out3 $end +$upscope $end +$scope module TwoMux $end +$var wire 1 u; S $end +$var wire 1 v; in0 $end +$var wire 1 w; in1 $end +$var wire 1 x; nS $end +$var wire 1 y; out0 $end +$var wire 1 z; out1 $end +$var wire 1 {; outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope module testBasicFunctions $end +$var wire 1 |; AddSubSLTSum $end +$var wire 1 }; AndNandOut $end +$var wire 1 ~; OrNorXorOut $end +$var wire 1 !< carryout $end +$var wire 1 "< muxout $end +$var wire 1 #< subtract $end +$var reg 1 $< A $end +$var reg 1 %< B $end +$var reg 3 &< Command [2:0] $end +$var reg 1 '< S0 $end +$var reg 1 (< S1 $end +$var reg 1 )< carryin $end +$var reg 1 *< in0 $end +$var reg 1 +< in1 $end +$var reg 1 ,< in2 $end +$var reg 1 -< in3 $end +$scope module testmux $end +$var wire 1 .< S0 $end +$var wire 1 /< S1 $end +$var wire 1 0< in0 $end +$var wire 1 1< in1 $end +$var wire 1 2< in2 $end +$var wire 1 3< in3 $end +$var wire 1 4< nS0 $end +$var wire 1 5< nS1 $end +$var wire 1 "< out $end +$var wire 1 6< out0 $end +$var wire 1 7< out1 $end +$var wire 1 8< out2 $end +$var wire 1 9< out3 $end +$upscope $end +$scope module testadd $end +$var wire 1 :< A $end +$var wire 1 ;< AandB $end +$var wire 1 |; AddSubSLTSum $end +$var wire 1 << AxorB $end +$var wire 1 =< B $end +$var wire 1 >< BornB $end +$var wire 1 ?< CINandAxorB $end +$var wire 3 @< Command [2:0] $end +$var wire 1 A< carryin $end +$var wire 1 !< carryout $end +$var wire 1 B< nB $end +$var wire 1 C< nCmd2 $end +$var wire 1 #< subtract $end +$scope module mux0 $end +$var wire 1 D< S $end +$var wire 1 =< in0 $end +$var wire 1 B< in1 $end +$var wire 1 E< nS $end +$var wire 1 F< out0 $end +$var wire 1 G< out1 $end +$var wire 1 >< outfinal $end +$upscope $end +$upscope $end +$scope module testand $end +$var wire 1 :< A $end +$var wire 1 H< AandB $end +$var wire 1 I< AnandB $end +$var wire 1 }; AndNandOut $end +$var wire 1 =< B $end +$var wire 3 J< Command [2:0] $end +$scope module potato $end +$var wire 1 K< S $end +$var wire 1 H< in0 $end +$var wire 1 I< in1 $end +$var wire 1 L< nS $end +$var wire 1 M< out0 $end +$var wire 1 N< out1 $end +$var wire 1 }; outfinal $end +$upscope $end +$upscope $end +$scope module testor $end +$var wire 1 :< A $end +$var wire 1 O< AnandB $end +$var wire 1 P< AnorB $end +$var wire 1 Q< AorB $end +$var wire 1 R< AxorB $end +$var wire 1 =< B $end +$var wire 3 S< Command [2:0] $end +$var wire 1 ~; OrNorXorOut $end +$var wire 1 T< XorNor $end +$var wire 1 U< nXor $end +$scope module mux0 $end +$var wire 1 V< S $end +$var wire 1 R< in0 $end +$var wire 1 P< in1 $end +$var wire 1 W< nS $end +$var wire 1 X< out0 $end +$var wire 1 Y< out1 $end +$var wire 1 T< outfinal $end +$upscope $end +$scope module mux1 $end +$var wire 1 Z< S $end +$var wire 1 T< in0 $end +$var wire 1 Q< in1 $end +$var wire 1 [< nS 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+0:< +#30010000 +0B< +#30020000 +1F< +#30040000 +1>< +0<< +#30060000 +0?< +#30080000 +0!< +1<< +1|; +#30100000 +1?< +#30120000 +1!< +0|; +#31000000 +0%< +0=< +#31010000 +1B< +1P< +#31020000 +0Q< +0F< +#31030000 +1U< +#31040000 +0R< +0>< +#31060000 +0X< +#31080000 +0T< +0<< +#31100000 +0\< +0?< +#31120000 +0~; +0!< +1|; +#32000000 From 13ef3c960a34e3ada50877bd9e4fc78bf9f2a399 Mon Sep 17 00:00:00 2001 From: mjakus Date: Tue, 10 Oct 2017 17:35:13 -0400 Subject: [PATCH 23/28] Making moves re: SLT --- FullALU.vcd | 88454 +++++++++++-------------------------------------- SmallALU.vcd | 2 +- alu.v | 48 +- test | 11486 ++----- testing.t.v | 15 +- 5 files changed, 21124 insertions(+), 78881 deletions(-) diff --git a/FullALU.vcd b/FullALU.vcd index 043d1dd..42feeac 100644 --- a/FullALU.vcd +++ b/FullALU.vcd @@ -1,5 +1,5 @@ $date - Tue Oct 10 14:34:59 2017 + Tue Oct 10 17:34:37 2017 $end $version Icarus Verilog @@ -8,479 +8,498 @@ $timescale 1ps $end $scope module test32Adder $end -$var wire 32 ! AddSubSLTSum [31:0] $end +$var wire 4 ! AddSubSLTSum [3:0] $end $var wire 1 " AllZeros $end -$var wire 32 # AndNandOut [31:0] $end -$var wire 32 $ OneBitFinalOut [31:0] $end -$var wire 32 % OrNorXorOut [31:0] $end +$var wire 4 # AndNandOut [3:0] $end +$var wire 4 $ OneBitFinalOut [3:0] $end +$var wire 4 % OrNorXorOut [3:0] $end $var wire 1 & SLTflag $end -$var wire 32 ' ZeroFlag [31:0] $end +$var wire 4 ' ZeroFlag [3:0] $end $var wire 1 ( carryout $end $var wire 1 ) overflow $end -$var wire 32 * subtract [31:0] $end -$var reg 32 + A [31:0] $end -$var reg 32 , B [31:0] $end +$var wire 4 * subtract [3:0] $end +$var reg 4 + A [3:0] $end +$var reg 4 , B [3:0] $end $var reg 3 - Command [2:0] $end -$var reg 32 . carryin [31:0] $end +$var reg 4 . carryin [3:0] $end $scope module trial $end -$var wire 32 / A [31:0] $end -$var wire 32 0 AddSubSLTSum [31:0] $end -$var wire 32 1 B [31:0] $end -$var wire 32 2 CarryoutWire [31:0] $end +$var wire 4 / A [3:0] $end +$var wire 4 0 AddSubSLTSum [3:0] $end +$var wire 4 1 B [3:0] $end +$var wire 4 2 CarryoutWire [3:0] $end $var wire 3 3 Command [2:0] $end -$var wire 1 4 Res0OF1 $end -$var wire 1 5 Res1OF0 $end +$var wire 4 4 NewVal [3:0] $end +$var wire 1 5 Res0OF1 $end +$var wire 1 6 Res1OF0 $end $var wire 1 & SLTflag $end -$var wire 1 6 SLTflag0 $end -$var wire 1 7 SLTflag1 $end -$var wire 1 8 SLTon $end -$var wire 32 9 carryin [31:0] $end +$var wire 1 7 SLTflag0 $end +$var wire 1 8 SLTflag1 $end +$var wire 1 9 SLTon $end +$var wire 4 : carryin [3:0] $end $var wire 1 ( carryout $end -$var wire 1 : nAddSubSLTSum $end -$var wire 1 ; nOF $end +$var wire 1 ; nAddSubSLTSum $end +$var wire 1 < nCmd2 $end +$var wire 1 = nOF $end $var wire 1 ) overflow $end -$var wire 32 < subtract [31:0] $end +$var wire 4 > subtract [3:0] $end $scope module attempt2 $end -$var wire 1 = A $end -$var wire 1 > AandB $end -$var wire 1 ? AddSubSLTSum $end -$var wire 1 @ AxorB $end -$var wire 1 A B $end -$var wire 1 B BornB $end -$var wire 1 C CINandAxorB $end -$var wire 3 D Command [2:0] $end -$var wire 1 E carryin $end -$var wire 1 F carryout $end -$var wire 1 G nB $end -$var wire 1 H nCmd2 $end -$var wire 1 I subtract $end +$var wire 1 ? A $end +$var wire 1 @ AandB $end +$var wire 1 A AddSubSLTSum $end +$var wire 1 B AxorB $end +$var wire 1 C B $end +$var wire 1 D BornB $end +$var wire 1 E CINandAxorB $end +$var wire 3 F Command [2:0] $end +$var wire 1 G carryin $end +$var wire 1 H carryout $end +$var wire 1 I nB $end +$var wire 1 J nCmd2 $end +$var wire 1 K subtract $end $scope module mux0 $end -$var wire 1 J S $end -$var wire 1 A in0 $end -$var wire 1 G in1 $end -$var wire 1 K nS $end -$var wire 1 L out0 $end -$var wire 1 M out1 $end -$var wire 1 B outfinal $end -$upscope $end +$var wire 1 L S $end +$var wire 1 C in0 $end +$var wire 1 I in1 $end +$var wire 1 M nS $end +$var wire 1 N out0 $end +$var wire 1 O out1 $end +$var wire 1 D outfinal $end +$upscope $end +$upscope $end +$scope module setSLTres $end +$var wire 1 9 S $end +$var wire 1 P in0 $end +$var wire 1 Q in1 $end +$var wire 1 R nS $end +$var wire 1 S out0 $end +$var wire 1 T out1 $end +$var wire 1 U outfinal $end $upscope $end $scope begin addbits[1] $end $scope module attempt $end -$var wire 1 N A $end -$var wire 1 O AandB $end -$var wire 1 P AddSubSLTSum $end -$var wire 1 Q AxorB $end -$var wire 1 R B $end -$var wire 1 S BornB $end -$var wire 1 T CINandAxorB $end -$var wire 3 U Command [2:0] $end -$var wire 1 V carryin $end -$var wire 1 W carryout $end -$var wire 1 X nB $end -$var wire 1 Y nCmd2 $end -$var wire 1 Z subtract $end +$var wire 1 V A $end +$var wire 1 W AandB $end +$var wire 1 X AddSubSLTSum $end +$var wire 1 Y AxorB $end +$var wire 1 Z B $end +$var wire 1 [ BornB $end +$var wire 1 \ CINandAxorB $end +$var wire 3 ] Command [2:0] $end +$var wire 1 ^ carryin $end +$var wire 1 _ carryout $end +$var wire 1 ` nB $end +$var wire 1 a nCmd2 $end +$var wire 1 b subtract $end $scope module mux0 $end -$var wire 1 [ S $end -$var wire 1 R in0 $end -$var wire 1 X in1 $end -$var wire 1 \ nS $end -$var wire 1 ] out0 $end -$var wire 1 ^ out1 $end -$var wire 1 S outfinal $end +$var wire 1 c S $end +$var wire 1 Z in0 $end +$var wire 1 ` in1 $end +$var wire 1 d nS $end +$var wire 1 e out0 $end +$var wire 1 f out1 $end +$var wire 1 [ outfinal $end +$upscope $end $upscope $end +$scope module setSLTres $end +$var wire 1 9 S $end +$var wire 1 g in0 $end +$var wire 1 h in1 $end +$var wire 1 i nS $end +$var wire 1 j out0 $end +$var wire 1 k out1 $end +$var wire 1 l outfinal $end $upscope $end $upscope $end $scope begin addbits[2] $end $scope module attempt $end -$var wire 1 _ A $end -$var wire 1 ` AandB $end -$var wire 1 a AddSubSLTSum $end -$var wire 1 b AxorB $end -$var wire 1 c B $end -$var wire 1 d BornB $end -$var wire 1 e CINandAxorB $end -$var wire 3 f Command [2:0] $end -$var wire 1 g carryin $end -$var wire 1 h carryout $end -$var wire 1 i nB $end -$var wire 1 j nCmd2 $end -$var wire 1 k subtract $end +$var wire 1 m A $end +$var wire 1 n AandB $end +$var wire 1 o AddSubSLTSum $end +$var wire 1 p AxorB $end +$var wire 1 q B $end +$var wire 1 r BornB $end +$var wire 1 s CINandAxorB $end +$var wire 3 t Command [2:0] $end +$var wire 1 u carryin $end +$var wire 1 v carryout $end +$var wire 1 w nB $end +$var wire 1 x nCmd2 $end +$var wire 1 y subtract $end $scope module mux0 $end -$var wire 1 l S $end -$var wire 1 c in0 $end -$var wire 1 i in1 $end -$var wire 1 m nS $end -$var wire 1 n out0 $end -$var wire 1 o out1 $end -$var wire 1 d outfinal $end +$var wire 1 z S $end +$var wire 1 q in0 $end +$var wire 1 w in1 $end +$var wire 1 { nS $end +$var wire 1 | out0 $end +$var wire 1 } out1 $end +$var wire 1 r outfinal $end $upscope $end $upscope $end +$scope module setSLTres $end +$var wire 1 9 S $end +$var wire 1 ~ in0 $end +$var wire 1 !" in1 $end +$var wire 1 "" nS $end +$var wire 1 #" out0 $end +$var wire 1 $" out1 $end +$var wire 1 %" outfinal $end +$upscope $end $upscope $end $scope begin addbits[3] $end $scope module attempt $end -$var wire 1 p A $end -$var wire 1 q AandB $end -$var wire 1 r AddSubSLTSum $end -$var wire 1 s AxorB $end -$var wire 1 t B $end -$var wire 1 u BornB $end -$var wire 1 v CINandAxorB $end -$var wire 3 w Command [2:0] $end -$var wire 1 x carryin $end -$var wire 1 y carryout $end -$var wire 1 z nB $end -$var wire 1 { nCmd2 $end -$var wire 1 | subtract $end +$var wire 1 &" A $end +$var wire 1 '" AandB $end +$var wire 1 (" AddSubSLTSum $end +$var wire 1 )" AxorB $end +$var wire 1 *" B $end +$var wire 1 +" BornB $end +$var wire 1 ," CINandAxorB $end +$var wire 3 -" Command [2:0] $end +$var wire 1 ." carryin $end +$var wire 1 /" carryout $end +$var wire 1 0" nB $end +$var wire 1 1" nCmd2 $end +$var wire 1 2" subtract $end $scope module mux0 $end -$var wire 1 } S $end -$var wire 1 t in0 $end -$var wire 1 z in1 $end -$var wire 1 ~ nS $end -$var wire 1 !" out0 $end -$var wire 1 "" out1 $end -$var wire 1 u outfinal $end +$var wire 1 3" S $end +$var wire 1 *" in0 $end +$var wire 1 0" in1 $end +$var wire 1 4" nS $end +$var wire 1 5" out0 $end +$var wire 1 6" out1 $end +$var wire 1 +" outfinal $end $upscope $end $upscope $end +$scope module setSLTres $end +$var wire 1 9 S $end +$var wire 1 7" in0 $end +$var wire 1 8" in1 $end +$var wire 1 9" nS $end +$var wire 1 :" out0 $end +$var wire 1 ;" out1 $end +$var wire 1 <" outfinal $end +$upscope $end $upscope $end -$scope begin addbits[4] $end -$scope module attempt $end -$var wire 1 #" A $end -$var wire 1 $" AandB $end -$var wire 1 %" AddSubSLTSum $end -$var wire 1 &" AxorB $end -$var wire 1 '" B $end -$var wire 1 (" BornB $end -$var wire 1 )" CINandAxorB $end -$var wire 3 *" Command [2:0] $end -$var wire 1 +" carryin $end -$var wire 1 ," carryout $end -$var wire 1 -" nB $end -$var wire 1 ." nCmd2 $end -$var wire 1 /" subtract $end -$scope module mux0 $end -$var wire 1 0" S $end -$var wire 1 '" in0 $end -$var wire 1 -" in1 $end -$var wire 1 1" nS $end -$var wire 1 2" out0 $end -$var wire 1 3" out1 $end -$var wire 1 (" outfinal $end $upscope $end +$scope module trial1 $end +$var wire 4 =" A [3:0] $end +$var wire 4 >" AndNandOut [3:0] $end +$var wire 4 ?" B [3:0] $end +$var wire 3 @" Command [2:0] $end +$scope module attempt2 $end +$var wire 1 A" A $end +$var wire 1 B" AandB $end +$var wire 1 C" AnandB $end +$var wire 1 D" AndNandOut $end +$var wire 1 E" B $end +$var wire 3 F" Command [2:0] $end +$scope module potato $end +$var wire 1 G" S $end +$var wire 1 B" in0 $end +$var wire 1 C" in1 $end +$var wire 1 H" nS $end +$var wire 1 I" out0 $end +$var wire 1 J" out1 $end +$var wire 1 D" outfinal $end $upscope $end $upscope $end -$scope begin addbits[5] $end +$scope begin andbits[1] $end $scope module attempt $end -$var wire 1 4" A $end -$var wire 1 5" AandB $end -$var wire 1 6" AddSubSLTSum $end -$var wire 1 7" AxorB $end -$var wire 1 8" B $end -$var wire 1 9" BornB $end -$var wire 1 :" CINandAxorB $end -$var wire 3 ;" Command [2:0] $end -$var wire 1 <" carryin $end -$var wire 1 =" carryout $end -$var wire 1 >" nB $end -$var wire 1 ?" nCmd2 $end -$var wire 1 @" subtract $end -$scope module mux0 $end -$var wire 1 A" S $end -$var wire 1 8" in0 $end -$var wire 1 >" in1 $end -$var wire 1 B" nS $end -$var wire 1 C" out0 $end -$var wire 1 D" out1 $end -$var wire 1 9" outfinal $end +$var wire 1 K" A $end +$var wire 1 L" AandB $end +$var wire 1 M" AnandB $end +$var wire 1 N" AndNandOut $end +$var wire 1 O" B $end +$var wire 3 P" Command [2:0] $end +$scope module potato $end +$var wire 1 Q" S $end +$var wire 1 L" in0 $end +$var wire 1 M" in1 $end +$var wire 1 R" nS $end +$var wire 1 S" out0 $end +$var wire 1 T" out1 $end +$var wire 1 N" outfinal $end $upscope $end $upscope $end $upscope $end -$scope begin addbits[6] $end +$scope begin andbits[2] $end $scope module attempt $end -$var wire 1 E" A $end -$var wire 1 F" AandB $end -$var wire 1 G" AddSubSLTSum $end -$var wire 1 H" AxorB $end -$var wire 1 I" B $end -$var wire 1 J" BornB $end -$var wire 1 K" CINandAxorB $end -$var wire 3 L" Command [2:0] $end -$var wire 1 M" carryin $end -$var wire 1 N" carryout $end -$var wire 1 O" nB $end -$var wire 1 P" nCmd2 $end -$var wire 1 Q" subtract $end -$scope module mux0 $end -$var wire 1 R" S $end -$var wire 1 I" in0 $end -$var wire 1 O" in1 $end -$var wire 1 S" nS $end -$var wire 1 T" out0 $end -$var wire 1 U" out1 $end -$var wire 1 J" outfinal $end +$var wire 1 U" A $end +$var wire 1 V" AandB $end +$var wire 1 W" AnandB $end +$var wire 1 X" AndNandOut $end +$var wire 1 Y" B $end +$var wire 3 Z" Command [2:0] $end +$scope module potato $end +$var wire 1 [" S $end +$var wire 1 V" in0 $end +$var wire 1 W" in1 $end +$var wire 1 \" nS $end +$var wire 1 ]" out0 $end +$var wire 1 ^" out1 $end +$var wire 1 X" outfinal $end $upscope $end $upscope $end $upscope $end -$scope begin addbits[7] $end +$scope begin andbits[3] $end $scope module attempt $end -$var wire 1 V" A $end -$var wire 1 W" AandB $end -$var wire 1 X" AddSubSLTSum $end -$var wire 1 Y" AxorB $end -$var wire 1 Z" B $end -$var wire 1 [" BornB $end -$var wire 1 \" CINandAxorB $end -$var wire 3 ]" Command [2:0] $end -$var wire 1 ^" carryin $end -$var wire 1 _" carryout $end -$var wire 1 `" nB $end -$var wire 1 a" nCmd2 $end -$var wire 1 b" subtract $end -$scope module mux0 $end -$var wire 1 c" S $end -$var wire 1 Z" in0 $end -$var wire 1 `" in1 $end -$var wire 1 d" nS $end -$var wire 1 e" out0 $end -$var wire 1 f" out1 $end -$var wire 1 [" outfinal $end +$var wire 1 _" A $end +$var wire 1 `" AandB $end +$var wire 1 a" AnandB $end +$var wire 1 b" AndNandOut $end +$var wire 1 c" B $end +$var wire 3 d" Command [2:0] $end +$scope module potato $end +$var wire 1 e" S $end +$var wire 1 `" in0 $end +$var wire 1 a" in1 $end +$var wire 1 f" nS $end +$var wire 1 g" out0 $end +$var wire 1 h" out1 $end +$var wire 1 b" outfinal $end $upscope $end $upscope $end $upscope $end -$scope begin addbits[8] $end -$scope module attempt $end -$var wire 1 g" A $end -$var wire 1 h" AandB $end -$var wire 1 i" AddSubSLTSum $end -$var wire 1 j" AxorB $end -$var wire 1 k" B $end -$var wire 1 l" BornB $end -$var wire 1 m" CINandAxorB $end -$var wire 3 n" Command [2:0] $end -$var wire 1 o" carryin $end -$var wire 1 p" carryout $end -$var wire 1 q" nB $end -$var wire 1 r" nCmd2 $end -$var wire 1 s" subtract $end +$upscope $end +$scope module trial2 $end +$var wire 4 i" A [3:0] $end +$var wire 4 j" B [3:0] $end +$var wire 3 k" Command [2:0] $end +$var wire 4 l" OrNorXorOut [3:0] $end +$scope module attempt2 $end +$var wire 1 m" A $end +$var wire 1 n" AnandB $end +$var wire 1 o" AnorB $end +$var wire 1 p" AorB $end +$var wire 1 q" AxorB $end +$var wire 1 r" B $end +$var wire 3 s" Command [2:0] $end +$var wire 1 t" OrNorXorOut $end +$var wire 1 u" XorNor $end +$var wire 1 v" nXor $end $scope module mux0 $end -$var wire 1 t" S $end -$var wire 1 k" in0 $end -$var wire 1 q" in1 $end -$var wire 1 u" nS $end -$var wire 1 v" out0 $end -$var wire 1 w" out1 $end -$var wire 1 l" outfinal $end +$var wire 1 w" S $end +$var wire 1 q" in0 $end +$var wire 1 o" in1 $end +$var wire 1 x" nS $end +$var wire 1 y" out0 $end +$var wire 1 z" out1 $end +$var wire 1 u" outfinal $end $upscope $end +$scope module mux1 $end +$var wire 1 {" S $end +$var wire 1 u" in0 $end +$var wire 1 p" in1 $end +$var wire 1 |" nS $end +$var wire 1 }" out0 $end +$var wire 1 ~" out1 $end +$var wire 1 t" outfinal $end $upscope $end $upscope $end -$scope begin addbits[9] $end +$scope begin orbits[1] $end $scope module attempt $end -$var wire 1 x" A $end -$var wire 1 y" AandB $end -$var wire 1 z" AddSubSLTSum $end -$var wire 1 {" AxorB $end -$var wire 1 |" B $end -$var wire 1 }" BornB $end -$var wire 1 ~" CINandAxorB $end -$var wire 3 !# Command [2:0] $end -$var wire 1 "# carryin $end -$var wire 1 ## carryout $end -$var wire 1 $# nB $end -$var wire 1 %# nCmd2 $end -$var wire 1 &# subtract $end +$var wire 1 !# A $end +$var wire 1 "# AnandB $end +$var wire 1 ## AnorB $end +$var wire 1 $# AorB $end +$var wire 1 %# AxorB $end +$var wire 1 &# B $end +$var wire 3 '# Command [2:0] $end +$var wire 1 (# OrNorXorOut $end +$var wire 1 )# XorNor $end +$var wire 1 *# nXor $end $scope module mux0 $end -$var wire 1 '# S $end -$var wire 1 |" in0 $end +$var wire 1 +# S $end +$var wire 1 %# in0 $end +$var wire 1 ## in1 $end +$var wire 1 ,# nS $end +$var wire 1 -# out0 $end +$var wire 1 .# out1 $end +$var wire 1 )# outfinal $end +$upscope $end +$scope module mux1 $end +$var wire 1 /# S $end +$var wire 1 )# in0 $end $var wire 1 $# in1 $end -$var wire 1 (# nS $end -$var wire 1 )# out0 $end -$var wire 1 *# out1 $end -$var wire 1 }" outfinal $end +$var wire 1 0# nS $end +$var wire 1 1# out0 $end +$var wire 1 2# out1 $end +$var wire 1 (# outfinal $end $upscope $end $upscope $end $upscope $end -$scope begin addbits[10] $end +$scope begin orbits[2] $end $scope module attempt $end -$var wire 1 +# A $end -$var wire 1 ,# AandB $end -$var wire 1 -# AddSubSLTSum $end -$var wire 1 .# AxorB $end -$var wire 1 /# B $end -$var wire 1 0# BornB $end -$var wire 1 1# CINandAxorB $end -$var wire 3 2# Command [2:0] $end -$var wire 1 3# carryin $end -$var wire 1 4# carryout $end -$var wire 1 5# nB $end -$var wire 1 6# nCmd2 $end -$var wire 1 7# subtract $end +$var wire 1 3# A $end +$var wire 1 4# AnandB $end +$var wire 1 5# AnorB $end +$var wire 1 6# AorB $end +$var wire 1 7# AxorB $end +$var wire 1 8# B $end +$var wire 3 9# Command [2:0] $end +$var wire 1 :# OrNorXorOut $end +$var wire 1 ;# XorNor $end +$var wire 1 <# nXor $end $scope module mux0 $end -$var wire 1 8# S $end -$var wire 1 /# in0 $end +$var wire 1 =# S $end +$var wire 1 7# in0 $end $var wire 1 5# in1 $end -$var wire 1 9# nS $end -$var wire 1 :# out0 $end -$var wire 1 ;# out1 $end -$var wire 1 0# outfinal $end -$upscope $end +$var wire 1 ># nS $end +$var wire 1 ?# out0 $end +$var wire 1 @# out1 $end +$var wire 1 ;# outfinal $end $upscope $end -$upscope $end -$scope begin addbits[11] $end -$scope module attempt $end -$var wire 1 <# A $end -$var wire 1 =# AandB $end -$var wire 1 ># AddSubSLTSum $end -$var wire 1 ?# AxorB $end -$var wire 1 @# B $end -$var wire 1 A# BornB $end -$var wire 1 B# CINandAxorB $end -$var wire 3 C# Command [2:0] $end -$var wire 1 D# carryin $end -$var wire 1 E# carryout $end -$var wire 1 F# nB $end -$var wire 1 G# nCmd2 $end -$var wire 1 H# subtract $end -$scope module mux0 $end -$var wire 1 I# S $end -$var wire 1 @# in0 $end -$var wire 1 F# in1 $end -$var wire 1 J# nS $end -$var wire 1 K# out0 $end -$var wire 1 L# out1 $end -$var wire 1 A# outfinal $end +$scope module mux1 $end +$var wire 1 A# S $end +$var wire 1 ;# in0 $end +$var wire 1 6# in1 $end +$var wire 1 B# nS $end +$var wire 1 C# out0 $end +$var wire 1 D# out1 $end +$var wire 1 :# outfinal $end $upscope $end $upscope $end $upscope $end -$scope begin addbits[12] $end +$scope begin orbits[3] $end $scope module attempt $end -$var wire 1 M# A $end -$var wire 1 N# AandB $end -$var wire 1 O# AddSubSLTSum $end -$var wire 1 P# AxorB $end -$var wire 1 Q# B $end -$var wire 1 R# BornB $end -$var wire 1 S# CINandAxorB $end -$var wire 3 T# Command [2:0] $end -$var wire 1 U# carryin $end -$var wire 1 V# carryout $end -$var wire 1 W# nB $end -$var wire 1 X# nCmd2 $end -$var wire 1 Y# subtract $end +$var wire 1 E# A $end +$var wire 1 F# AnandB $end +$var wire 1 G# AnorB $end +$var wire 1 H# AorB $end +$var wire 1 I# AxorB $end +$var wire 1 J# B $end +$var wire 3 K# Command [2:0] $end +$var wire 1 L# OrNorXorOut $end +$var wire 1 M# XorNor $end +$var wire 1 N# nXor $end $scope module mux0 $end -$var wire 1 Z# S $end -$var wire 1 Q# in0 $end -$var wire 1 W# in1 $end -$var wire 1 [# nS $end -$var wire 1 \# out0 $end -$var wire 1 ]# out1 $end -$var wire 1 R# outfinal $end -$upscope $end +$var wire 1 O# S $end +$var wire 1 I# in0 $end +$var wire 1 G# in1 $end +$var wire 1 P# nS $end +$var wire 1 Q# out0 $end +$var wire 1 R# out1 $end +$var wire 1 M# outfinal $end $upscope $end +$scope module mux1 $end +$var wire 1 S# S $end +$var wire 1 M# in0 $end +$var wire 1 H# in1 $end +$var wire 1 T# nS $end +$var wire 1 U# out0 $end +$var wire 1 V# out1 $end +$var wire 1 L# outfinal $end $upscope $end -$scope begin addbits[13] $end -$scope module attempt $end -$var wire 1 ^# A $end -$var wire 1 _# AandB $end -$var wire 1 `# AddSubSLTSum $end -$var wire 1 a# AxorB $end -$var wire 1 b# B $end -$var wire 1 c# BornB $end -$var wire 1 d# CINandAxorB $end -$var wire 3 e# Command [2:0] $end -$var wire 1 f# carryin $end -$var wire 1 g# carryout $end -$var wire 1 h# nB $end -$var wire 1 i# nCmd2 $end -$var wire 1 j# subtract $end -$scope module mux0 $end -$var wire 1 k# S $end -$var wire 1 b# in0 $end -$var wire 1 h# in1 $end -$var wire 1 l# nS $end -$var wire 1 m# out0 $end -$var wire 1 n# out1 $end -$var wire 1 c# outfinal $end $upscope $end $upscope $end $upscope $end -$scope begin addbits[14] $end -$scope module attempt $end -$var wire 1 o# A $end -$var wire 1 p# AandB $end -$var wire 1 q# AddSubSLTSum $end -$var wire 1 r# AxorB $end -$var wire 1 s# B $end -$var wire 1 t# BornB $end -$var wire 1 u# CINandAxorB $end -$var wire 3 v# Command [2:0] $end -$var wire 1 w# carryin $end -$var wire 1 x# carryout $end -$var wire 1 y# nB $end -$var wire 1 z# nCmd2 $end -$var wire 1 {# subtract $end +$scope module superalu $end +$var wire 4 W# A [3:0] $end +$var wire 4 X# AddSubSLTSum [3:0] $end +$var wire 1 " AllZeros $end +$var wire 4 Y# AndNandOut [3:0] $end +$var wire 4 Z# B [3:0] $end +$var wire 4 [# Cmd0Start [3:0] $end +$var wire 4 \# Cmd1Start [3:0] $end +$var wire 3 ]# Command [2:0] $end +$var wire 4 ^# OneBitFinalOut [3:0] $end +$var wire 4 _# OrNorXorOut [3:0] $end +$var wire 1 & SLTflag $end +$var wire 4 `# ZeroFlag [3:0] $end +$var wire 4 a# carryin [3:0] $end +$var wire 1 ( carryout $end +$var wire 1 ) overflow $end +$var wire 4 b# subtract [3:0] $end +$var wire 1 c# yeszero $end +$scope module trial $end +$var wire 4 d# A [3:0] $end +$var wire 4 e# AddSubSLTSum [3:0] $end +$var wire 4 f# B [3:0] $end +$var wire 4 g# CarryoutWire [3:0] $end +$var wire 3 h# Command [2:0] $end +$var wire 4 i# NewVal [3:0] $end +$var wire 1 j# Res0OF1 $end +$var wire 1 k# Res1OF0 $end +$var wire 1 & SLTflag $end +$var wire 1 l# SLTflag0 $end +$var wire 1 m# SLTflag1 $end +$var wire 1 n# SLTon $end +$var wire 4 o# carryin [3:0] $end +$var wire 1 ( carryout $end +$var wire 1 p# nAddSubSLTSum $end +$var wire 1 q# nCmd2 $end +$var wire 1 r# nOF $end +$var wire 1 ) overflow $end +$var wire 4 s# subtract [3:0] $end +$scope module attempt2 $end +$var wire 1 t# A $end +$var wire 1 u# AandB $end +$var wire 1 v# AddSubSLTSum $end +$var wire 1 w# AxorB $end +$var wire 1 x# B $end +$var wire 1 y# BornB $end +$var wire 1 z# CINandAxorB $end +$var wire 3 {# Command [2:0] $end +$var wire 1 |# carryin $end +$var wire 1 }# carryout $end +$var wire 1 ~# nB $end +$var wire 1 !$ nCmd2 $end +$var wire 1 "$ subtract $end $scope module mux0 $end -$var wire 1 |# S $end -$var wire 1 s# in0 $end -$var wire 1 y# in1 $end -$var wire 1 }# nS $end -$var wire 1 ~# out0 $end -$var wire 1 !$ out1 $end -$var wire 1 t# outfinal $end +$var wire 1 #$ S $end +$var wire 1 x# in0 $end +$var wire 1 ~# in1 $end +$var wire 1 $$ nS $end +$var wire 1 %$ out0 $end +$var wire 1 &$ out1 $end +$var wire 1 y# outfinal $end +$upscope $end +$upscope $end +$scope module setSLTres $end +$var wire 1 n# S $end +$var wire 1 '$ in0 $end +$var wire 1 ($ in1 $end +$var wire 1 )$ nS $end +$var wire 1 *$ out0 $end +$var wire 1 +$ out1 $end +$var wire 1 ,$ outfinal $end $upscope $end -$upscope $end -$upscope $end -$scope begin addbits[15] $end +$scope begin addbits[1] $end $scope module attempt $end -$var wire 1 "$ A $end -$var wire 1 #$ AandB $end -$var wire 1 $$ AddSubSLTSum $end -$var wire 1 %$ AxorB $end -$var wire 1 &$ B $end -$var wire 1 '$ BornB $end -$var wire 1 ($ CINandAxorB $end -$var wire 3 )$ Command [2:0] $end -$var wire 1 *$ carryin $end -$var wire 1 +$ carryout $end -$var wire 1 ,$ nB $end -$var wire 1 -$ nCmd2 $end -$var wire 1 .$ subtract $end +$var wire 1 -$ A $end +$var wire 1 .$ AandB $end +$var wire 1 /$ AddSubSLTSum $end +$var wire 1 0$ AxorB $end +$var wire 1 1$ B $end +$var wire 1 2$ BornB $end +$var wire 1 3$ CINandAxorB $end +$var wire 3 4$ Command [2:0] $end +$var wire 1 5$ carryin $end +$var wire 1 6$ carryout $end +$var wire 1 7$ nB $end +$var wire 1 8$ nCmd2 $end +$var wire 1 9$ subtract $end $scope module mux0 $end -$var wire 1 /$ S $end -$var wire 1 &$ in0 $end -$var wire 1 ,$ in1 $end -$var wire 1 0$ nS $end -$var wire 1 1$ out0 $end -$var wire 1 2$ out1 $end -$var wire 1 '$ outfinal $end -$upscope $end +$var wire 1 :$ S $end +$var wire 1 1$ in0 $end +$var wire 1 7$ in1 $end +$var wire 1 ;$ nS $end +$var wire 1 <$ out0 $end +$var wire 1 =$ out1 $end +$var wire 1 2$ outfinal $end $upscope $end $upscope $end -$scope begin addbits[16] $end -$scope module attempt $end -$var wire 1 3$ A $end -$var wire 1 4$ AandB $end -$var wire 1 5$ AddSubSLTSum $end -$var wire 1 6$ AxorB $end -$var wire 1 7$ B $end -$var wire 1 8$ BornB $end -$var wire 1 9$ CINandAxorB $end -$var wire 3 :$ Command [2:0] $end -$var wire 1 ;$ carryin $end -$var wire 1 <$ carryout $end -$var wire 1 =$ nB $end -$var wire 1 >$ nCmd2 $end -$var wire 1 ?$ subtract $end -$scope module mux0 $end -$var wire 1 @$ S $end -$var wire 1 7$ in0 $end -$var wire 1 =$ in1 $end -$var wire 1 A$ nS $end -$var wire 1 B$ out0 $end -$var wire 1 C$ out1 $end -$var wire 1 8$ outfinal $end +$scope module setSLTres $end +$var wire 1 n# S $end +$var wire 1 >$ in0 $end +$var wire 1 ?$ in1 $end +$var wire 1 @$ nS $end +$var wire 1 A$ out0 $end +$var wire 1 B$ out1 $end +$var wire 1 C$ outfinal $end $upscope $end $upscope $end -$upscope $end -$scope begin addbits[17] $end +$scope begin addbits[2] $end $scope module attempt $end $var wire 1 D$ A $end $var wire 1 E$ AandB $end @@ -505,5827 +524,424 @@ $var wire 1 T$ out1 $end $var wire 1 I$ outfinal $end $upscope $end $upscope $end -$upscope $end -$scope begin addbits[18] $end -$scope module attempt $end -$var wire 1 U$ A $end -$var wire 1 V$ AandB $end -$var wire 1 W$ AddSubSLTSum $end -$var wire 1 X$ AxorB $end -$var wire 1 Y$ B $end -$var wire 1 Z$ BornB $end -$var wire 1 [$ CINandAxorB $end -$var wire 3 \$ Command [2:0] $end -$var wire 1 ]$ carryin $end -$var wire 1 ^$ carryout $end -$var wire 1 _$ nB $end -$var wire 1 `$ nCmd2 $end -$var wire 1 a$ subtract $end -$scope module mux0 $end -$var wire 1 b$ S $end -$var wire 1 Y$ in0 $end -$var wire 1 _$ in1 $end -$var wire 1 c$ nS $end -$var wire 1 d$ out0 $end -$var wire 1 e$ out1 $end +$scope module setSLTres $end +$var wire 1 n# S $end +$var wire 1 U$ in0 $end +$var wire 1 V$ in1 $end +$var wire 1 W$ nS $end +$var wire 1 X$ out0 $end +$var wire 1 Y$ out1 $end $var wire 1 Z$ outfinal $end $upscope $end $upscope $end -$upscope $end -$scope begin addbits[19] $end -$scope module attempt $end -$var wire 1 f$ A $end -$var wire 1 g$ AandB $end -$var wire 1 h$ AddSubSLTSum $end -$var wire 1 i$ AxorB $end -$var wire 1 j$ B $end -$var wire 1 k$ BornB $end -$var wire 1 l$ CINandAxorB $end -$var wire 3 m$ Command [2:0] $end -$var wire 1 n$ carryin $end -$var wire 1 o$ carryout $end -$var wire 1 p$ nB $end -$var wire 1 q$ nCmd2 $end -$var wire 1 r$ subtract $end -$scope module mux0 $end -$var wire 1 s$ S $end -$var wire 1 j$ in0 $end -$var wire 1 p$ in1 $end -$var wire 1 t$ nS $end -$var wire 1 u$ out0 $end -$var wire 1 v$ out1 $end -$var wire 1 k$ outfinal $end -$upscope $end -$upscope $end -$upscope $end -$scope begin addbits[20] $end -$scope module attempt $end -$var wire 1 w$ A $end -$var wire 1 x$ AandB $end -$var wire 1 y$ AddSubSLTSum $end -$var wire 1 z$ AxorB $end -$var wire 1 {$ B $end -$var wire 1 |$ BornB $end -$var wire 1 }$ CINandAxorB $end -$var wire 3 ~$ Command [2:0] $end -$var wire 1 !% carryin $end -$var wire 1 "% carryout $end -$var wire 1 #% nB $end -$var wire 1 $% nCmd2 $end -$var wire 1 %% subtract $end -$scope module mux0 $end -$var wire 1 &% S $end -$var wire 1 {$ in0 $end -$var wire 1 #% in1 $end -$var wire 1 '% nS $end -$var wire 1 (% out0 $end -$var wire 1 )% out1 $end -$var wire 1 |$ outfinal $end -$upscope $end -$upscope $end -$upscope $end -$scope begin addbits[21] $end -$scope module attempt $end -$var wire 1 *% A $end -$var wire 1 +% AandB $end -$var wire 1 ,% AddSubSLTSum $end -$var wire 1 -% AxorB $end -$var wire 1 .% B $end -$var wire 1 /% BornB $end -$var wire 1 0% CINandAxorB $end -$var wire 3 1% Command [2:0] $end -$var wire 1 2% carryin $end -$var wire 1 3% carryout $end -$var wire 1 4% nB $end -$var wire 1 5% nCmd2 $end -$var wire 1 6% subtract $end -$scope module mux0 $end -$var wire 1 7% S $end -$var wire 1 .% in0 $end -$var wire 1 4% in1 $end -$var wire 1 8% nS $end -$var wire 1 9% out0 $end -$var wire 1 :% out1 $end -$var wire 1 /% outfinal $end -$upscope $end -$upscope $end -$upscope $end -$scope begin addbits[22] $end -$scope module attempt $end -$var wire 1 ;% A $end -$var wire 1 <% AandB $end -$var wire 1 =% AddSubSLTSum $end -$var wire 1 >% AxorB $end -$var wire 1 ?% B $end -$var wire 1 @% BornB $end -$var wire 1 A% CINandAxorB $end -$var wire 3 B% Command [2:0] $end -$var wire 1 C% carryin $end -$var wire 1 D% carryout $end -$var wire 1 E% nB $end -$var wire 1 F% nCmd2 $end -$var wire 1 G% subtract $end -$scope module mux0 $end -$var wire 1 H% S $end -$var wire 1 ?% in0 $end -$var wire 1 E% in1 $end -$var wire 1 I% nS $end -$var wire 1 J% out0 $end -$var wire 1 K% out1 $end -$var wire 1 @% outfinal $end -$upscope $end -$upscope $end -$upscope $end -$scope begin addbits[23] $end -$scope module attempt $end -$var wire 1 L% A $end -$var wire 1 M% AandB $end -$var wire 1 N% AddSubSLTSum $end -$var wire 1 O% AxorB $end -$var wire 1 P% B $end -$var wire 1 Q% BornB $end -$var wire 1 R% CINandAxorB $end -$var wire 3 S% Command [2:0] $end -$var wire 1 T% carryin $end -$var wire 1 U% carryout $end -$var wire 1 V% nB $end -$var wire 1 W% nCmd2 $end -$var wire 1 X% subtract $end -$scope module mux0 $end -$var wire 1 Y% S $end -$var wire 1 P% in0 $end -$var wire 1 V% in1 $end -$var wire 1 Z% nS $end -$var wire 1 [% out0 $end -$var wire 1 \% out1 $end -$var wire 1 Q% outfinal $end -$upscope $end -$upscope $end -$upscope $end -$scope begin addbits[24] $end -$scope module attempt $end -$var wire 1 ]% A $end -$var wire 1 ^% AandB $end -$var wire 1 _% AddSubSLTSum $end -$var wire 1 `% AxorB $end -$var wire 1 a% B $end -$var wire 1 b% BornB $end -$var wire 1 c% CINandAxorB $end -$var wire 3 d% Command [2:0] $end -$var wire 1 e% carryin $end -$var wire 1 f% carryout $end -$var wire 1 g% nB $end -$var wire 1 h% nCmd2 $end -$var wire 1 i% subtract $end -$scope module mux0 $end -$var wire 1 j% S $end -$var wire 1 a% in0 $end -$var wire 1 g% in1 $end -$var wire 1 k% nS $end -$var wire 1 l% out0 $end -$var wire 1 m% out1 $end -$var wire 1 b% outfinal $end -$upscope $end -$upscope $end -$upscope $end -$scope begin addbits[25] $end -$scope module attempt $end -$var wire 1 n% A $end -$var wire 1 o% AandB $end -$var wire 1 p% AddSubSLTSum $end -$var wire 1 q% AxorB $end -$var wire 1 r% B $end -$var wire 1 s% BornB $end -$var wire 1 t% CINandAxorB $end -$var wire 3 u% Command [2:0] $end -$var wire 1 v% carryin $end -$var wire 1 w% carryout $end -$var wire 1 x% nB $end -$var wire 1 y% nCmd2 $end -$var wire 1 z% subtract $end -$scope module mux0 $end -$var wire 1 {% S $end -$var wire 1 r% in0 $end -$var wire 1 x% in1 $end -$var wire 1 |% nS $end -$var wire 1 }% out0 $end -$var wire 1 ~% out1 $end -$var wire 1 s% outfinal $end -$upscope $end -$upscope $end -$upscope $end -$scope begin addbits[26] $end -$scope module attempt $end -$var wire 1 !& A $end -$var wire 1 "& AandB $end -$var wire 1 #& AddSubSLTSum $end -$var wire 1 $& AxorB $end -$var wire 1 %& B $end -$var wire 1 && BornB $end -$var wire 1 '& CINandAxorB $end -$var wire 3 (& Command [2:0] $end -$var wire 1 )& carryin $end -$var wire 1 *& carryout $end -$var wire 1 +& nB $end -$var wire 1 ,& nCmd2 $end -$var wire 1 -& subtract $end -$scope module mux0 $end -$var wire 1 .& S $end -$var wire 1 %& in0 $end -$var wire 1 +& in1 $end -$var wire 1 /& nS $end -$var wire 1 0& out0 $end -$var wire 1 1& out1 $end -$var wire 1 && outfinal $end -$upscope $end -$upscope $end -$upscope $end -$scope begin addbits[27] $end -$scope module attempt $end -$var wire 1 2& A $end -$var wire 1 3& AandB $end -$var wire 1 4& AddSubSLTSum $end -$var wire 1 5& AxorB $end -$var wire 1 6& B $end -$var wire 1 7& BornB $end -$var wire 1 8& CINandAxorB $end -$var wire 3 9& Command [2:0] $end -$var wire 1 :& carryin $end -$var wire 1 ;& carryout $end -$var wire 1 <& nB $end -$var wire 1 =& nCmd2 $end -$var wire 1 >& subtract $end -$scope module mux0 $end -$var wire 1 ?& S $end -$var wire 1 6& in0 $end -$var wire 1 <& in1 $end -$var wire 1 @& nS $end -$var wire 1 A& out0 $end -$var wire 1 B& out1 $end -$var wire 1 7& outfinal $end -$upscope $end -$upscope $end -$upscope $end -$scope begin addbits[28] $end -$scope module attempt $end -$var wire 1 C& A $end -$var wire 1 D& AandB $end -$var wire 1 E& AddSubSLTSum $end -$var wire 1 F& AxorB $end -$var wire 1 G& B $end -$var wire 1 H& BornB $end -$var wire 1 I& CINandAxorB $end -$var wire 3 J& Command [2:0] $end -$var wire 1 K& carryin $end -$var wire 1 L& carryout $end -$var wire 1 M& nB $end -$var wire 1 N& nCmd2 $end -$var wire 1 O& subtract $end -$scope module mux0 $end -$var wire 1 P& S $end -$var wire 1 G& in0 $end -$var wire 1 M& in1 $end -$var wire 1 Q& nS $end -$var wire 1 R& out0 $end -$var wire 1 S& out1 $end -$var wire 1 H& outfinal $end -$upscope $end -$upscope $end -$upscope $end -$scope begin addbits[29] $end -$scope module attempt $end -$var wire 1 T& A $end -$var wire 1 U& AandB $end -$var wire 1 V& AddSubSLTSum $end -$var wire 1 W& AxorB $end -$var wire 1 X& B $end -$var wire 1 Y& BornB $end -$var wire 1 Z& CINandAxorB $end -$var wire 3 [& Command [2:0] $end -$var wire 1 \& carryin $end -$var wire 1 ]& carryout $end -$var wire 1 ^& nB $end -$var wire 1 _& nCmd2 $end -$var wire 1 `& subtract $end -$scope module mux0 $end -$var wire 1 a& S $end -$var wire 1 X& in0 $end -$var wire 1 ^& in1 $end -$var wire 1 b& nS $end -$var wire 1 c& out0 $end -$var wire 1 d& out1 $end -$var wire 1 Y& outfinal $end -$upscope $end -$upscope $end -$upscope $end -$scope begin addbits[30] $end +$scope begin addbits[3] $end $scope module attempt $end -$var wire 1 e& A $end -$var wire 1 f& AandB $end -$var wire 1 g& AddSubSLTSum $end -$var wire 1 h& AxorB $end -$var wire 1 i& B $end -$var wire 1 j& BornB $end -$var wire 1 k& CINandAxorB $end -$var wire 3 l& Command [2:0] $end -$var wire 1 m& carryin $end -$var wire 1 n& carryout $end -$var wire 1 o& nB $end -$var wire 1 p& nCmd2 $end -$var wire 1 q& subtract $end +$var wire 1 [$ A $end +$var wire 1 \$ AandB $end +$var wire 1 ]$ AddSubSLTSum $end +$var wire 1 ^$ AxorB $end +$var wire 1 _$ B $end +$var wire 1 `$ BornB $end +$var wire 1 a$ CINandAxorB $end +$var wire 3 b$ Command [2:0] $end +$var wire 1 c$ carryin $end +$var wire 1 d$ carryout $end +$var wire 1 e$ nB $end +$var wire 1 f$ nCmd2 $end +$var wire 1 g$ subtract $end $scope module mux0 $end -$var wire 1 r& S $end -$var wire 1 i& in0 $end -$var wire 1 o& in1 $end -$var wire 1 s& nS $end -$var wire 1 t& out0 $end -$var wire 1 u& out1 $end -$var wire 1 j& outfinal $end -$upscope $end +$var wire 1 h$ S $end +$var wire 1 _$ in0 $end +$var wire 1 e$ in1 $end +$var wire 1 i$ nS $end +$var wire 1 j$ out0 $end +$var wire 1 k$ out1 $end +$var wire 1 `$ outfinal $end $upscope $end $upscope $end -$scope begin addbits[31] $end -$scope module attempt $end -$var wire 1 v& A $end -$var wire 1 w& AandB $end -$var wire 1 x& AddSubSLTSum $end -$var wire 1 y& AxorB $end -$var wire 1 z& B $end -$var wire 1 {& BornB $end -$var wire 1 |& CINandAxorB $end -$var wire 3 }& Command [2:0] $end -$var wire 1 ~& carryin $end -$var wire 1 !' carryout $end -$var wire 1 "' nB $end -$var wire 1 #' nCmd2 $end -$var wire 1 $' subtract $end -$scope module mux0 $end -$var wire 1 %' S $end -$var wire 1 z& in0 $end -$var wire 1 "' in1 $end -$var wire 1 &' nS $end -$var wire 1 '' out0 $end -$var wire 1 (' out1 $end -$var wire 1 {& outfinal $end -$upscope $end +$scope module setSLTres $end +$var wire 1 n# S $end +$var wire 1 l$ in0 $end +$var wire 1 m$ in1 $end +$var wire 1 n$ nS $end +$var wire 1 o$ out0 $end +$var wire 1 p$ out1 $end +$var wire 1 q$ outfinal $end $upscope $end $upscope $end $upscope $end $scope module trial1 $end -$var wire 32 )' A [31:0] $end -$var wire 32 *' AndNandOut [31:0] $end -$var wire 32 +' B [31:0] $end -$var wire 3 ,' Command [2:0] $end +$var wire 4 r$ A [3:0] $end +$var wire 4 s$ AndNandOut [3:0] $end +$var wire 4 t$ B [3:0] $end +$var wire 3 u$ Command [2:0] $end $scope module attempt2 $end -$var wire 1 -' A $end -$var wire 1 .' AandB $end -$var wire 1 /' AnandB $end -$var wire 1 0' AndNandOut $end -$var wire 1 1' B $end -$var wire 3 2' Command [2:0] $end +$var wire 1 v$ A $end +$var wire 1 w$ AandB $end +$var wire 1 x$ AnandB $end +$var wire 1 y$ AndNandOut $end +$var wire 1 z$ B $end +$var wire 3 {$ Command [2:0] $end $scope module potato $end -$var wire 1 3' S $end -$var wire 1 .' in0 $end -$var wire 1 /' in1 $end -$var wire 1 4' nS $end -$var wire 1 5' out0 $end -$var wire 1 6' out1 $end -$var wire 1 0' outfinal $end +$var wire 1 |$ S $end +$var wire 1 w$ in0 $end +$var wire 1 x$ in1 $end +$var wire 1 }$ nS $end +$var wire 1 ~$ out0 $end +$var wire 1 !% out1 $end +$var wire 1 y$ outfinal $end $upscope $end $upscope $end $scope begin andbits[1] $end $scope module attempt $end -$var wire 1 7' A $end -$var wire 1 8' AandB $end -$var wire 1 9' AnandB $end -$var wire 1 :' AndNandOut $end -$var wire 1 ;' B $end -$var wire 3 <' Command [2:0] $end +$var wire 1 "% A $end +$var wire 1 #% AandB $end +$var wire 1 $% AnandB $end +$var wire 1 %% AndNandOut $end +$var wire 1 &% B $end +$var wire 3 '% Command [2:0] $end $scope module potato $end -$var wire 1 =' S $end -$var wire 1 8' in0 $end -$var wire 1 9' in1 $end -$var wire 1 >' nS $end -$var wire 1 ?' out0 $end -$var wire 1 @' out1 $end -$var wire 1 :' outfinal $end +$var wire 1 (% S $end +$var wire 1 #% in0 $end +$var wire 1 $% in1 $end +$var wire 1 )% nS $end +$var wire 1 *% out0 $end +$var wire 1 +% out1 $end +$var wire 1 %% outfinal $end $upscope $end $upscope $end $upscope $end $scope begin andbits[2] $end $scope module attempt $end -$var wire 1 A' A $end -$var wire 1 B' AandB $end -$var wire 1 C' AnandB $end -$var wire 1 D' AndNandOut $end -$var wire 1 E' B $end -$var wire 3 F' Command [2:0] $end +$var wire 1 ,% A $end +$var wire 1 -% AandB $end +$var wire 1 .% AnandB $end +$var wire 1 /% AndNandOut $end +$var wire 1 0% B $end +$var wire 3 1% Command [2:0] $end $scope module potato $end -$var wire 1 G' S $end -$var wire 1 B' in0 $end -$var wire 1 C' in1 $end -$var wire 1 H' nS $end -$var wire 1 I' out0 $end -$var wire 1 J' out1 $end -$var wire 1 D' outfinal $end +$var wire 1 2% S $end +$var wire 1 -% in0 $end +$var wire 1 .% in1 $end +$var wire 1 3% nS $end +$var wire 1 4% out0 $end +$var wire 1 5% out1 $end +$var wire 1 /% outfinal $end $upscope $end $upscope $end $upscope $end $scope begin andbits[3] $end $scope module attempt $end -$var wire 1 K' A $end -$var wire 1 L' AandB $end -$var wire 1 M' AnandB $end -$var wire 1 N' AndNandOut $end -$var wire 1 O' B $end -$var wire 3 P' Command [2:0] $end -$scope module potato $end -$var wire 1 Q' S $end -$var wire 1 L' in0 $end -$var wire 1 M' in1 $end -$var wire 1 R' nS $end -$var wire 1 S' out0 $end -$var wire 1 T' out1 $end -$var wire 1 N' outfinal $end -$upscope $end -$upscope $end -$upscope $end -$scope begin andbits[4] $end -$scope module attempt $end -$var wire 1 U' A $end -$var wire 1 V' AandB $end -$var wire 1 W' AnandB $end -$var wire 1 X' AndNandOut $end -$var wire 1 Y' B $end -$var wire 3 Z' Command [2:0] $end -$scope module potato $end -$var wire 1 [' S $end -$var wire 1 V' in0 $end -$var wire 1 W' in1 $end -$var wire 1 \' nS $end -$var wire 1 ]' out0 $end -$var wire 1 ^' out1 $end -$var wire 1 X' outfinal $end -$upscope $end -$upscope $end -$upscope $end -$scope begin andbits[5] $end -$scope module attempt $end -$var wire 1 _' A $end -$var wire 1 `' AandB $end -$var wire 1 a' AnandB $end -$var wire 1 b' AndNandOut $end -$var wire 1 c' B $end -$var wire 3 d' Command [2:0] $end -$scope module potato $end -$var wire 1 e' S $end -$var wire 1 `' in0 $end -$var wire 1 a' in1 $end -$var wire 1 f' nS $end -$var wire 1 g' out0 $end -$var wire 1 h' out1 $end -$var wire 1 b' outfinal $end -$upscope $end -$upscope $end -$upscope $end -$scope begin andbits[6] $end -$scope module attempt $end -$var wire 1 i' A $end -$var wire 1 j' AandB $end -$var wire 1 k' AnandB $end -$var wire 1 l' AndNandOut $end -$var wire 1 m' B $end -$var wire 3 n' Command [2:0] $end -$scope module potato $end -$var wire 1 o' S $end -$var wire 1 j' in0 $end -$var wire 1 k' in1 $end -$var wire 1 p' nS $end -$var wire 1 q' out0 $end -$var wire 1 r' out1 $end -$var wire 1 l' outfinal $end -$upscope $end -$upscope $end -$upscope $end -$scope begin andbits[7] $end -$scope module attempt $end -$var wire 1 s' A $end -$var wire 1 t' AandB $end -$var wire 1 u' AnandB $end -$var wire 1 v' AndNandOut $end -$var wire 1 w' B $end -$var wire 3 x' Command [2:0] $end -$scope module potato $end -$var wire 1 y' S $end -$var wire 1 t' in0 $end -$var wire 1 u' in1 $end -$var wire 1 z' nS $end -$var wire 1 {' out0 $end -$var wire 1 |' out1 $end -$var wire 1 v' outfinal $end -$upscope $end -$upscope $end -$upscope $end -$scope begin andbits[8] $end -$scope module attempt $end -$var wire 1 }' A $end -$var wire 1 ~' AandB $end -$var wire 1 !( AnandB $end -$var wire 1 "( AndNandOut $end -$var wire 1 #( B $end -$var wire 3 $( Command [2:0] $end -$scope module potato $end -$var wire 1 %( S $end -$var wire 1 ~' in0 $end -$var wire 1 !( in1 $end -$var wire 1 &( nS $end -$var wire 1 '( out0 $end -$var wire 1 (( out1 $end -$var wire 1 "( outfinal $end -$upscope $end -$upscope $end -$upscope $end -$scope begin andbits[9] $end -$scope module attempt $end -$var wire 1 )( A $end -$var wire 1 *( AandB $end -$var wire 1 +( AnandB $end -$var wire 1 ,( AndNandOut $end -$var wire 1 -( B $end -$var wire 3 .( Command [2:0] $end +$var wire 1 6% A $end +$var wire 1 7% AandB $end +$var wire 1 8% AnandB $end +$var wire 1 9% AndNandOut $end +$var wire 1 :% B $end +$var wire 3 ;% Command [2:0] $end $scope module potato $end -$var wire 1 /( S $end -$var wire 1 *( in0 $end -$var wire 1 +( in1 $end -$var wire 1 0( nS $end -$var wire 1 1( out0 $end -$var wire 1 2( out1 $end -$var wire 1 ,( outfinal $end -$upscope $end -$upscope $end -$upscope $end -$scope begin andbits[10] $end -$scope module attempt $end -$var wire 1 3( A $end -$var wire 1 4( AandB $end -$var wire 1 5( AnandB $end -$var wire 1 6( AndNandOut $end -$var wire 1 7( B $end -$var wire 3 8( Command [2:0] $end -$scope module potato $end -$var wire 1 9( S $end -$var wire 1 4( in0 $end -$var wire 1 5( in1 $end -$var wire 1 :( nS $end -$var wire 1 ;( out0 $end -$var wire 1 <( out1 $end -$var wire 1 6( outfinal $end -$upscope $end -$upscope $end -$upscope $end -$scope begin andbits[11] $end -$scope module attempt $end -$var wire 1 =( A $end -$var wire 1 >( AandB $end -$var wire 1 ?( AnandB $end -$var wire 1 @( AndNandOut $end -$var wire 1 A( B $end -$var wire 3 B( Command [2:0] $end -$scope module potato $end -$var wire 1 C( S $end -$var wire 1 >( in0 $end -$var wire 1 ?( in1 $end -$var wire 1 D( nS $end -$var wire 1 E( out0 $end -$var wire 1 F( out1 $end -$var wire 1 @( outfinal $end -$upscope $end -$upscope $end -$upscope $end -$scope begin andbits[12] $end -$scope module attempt $end -$var wire 1 G( A $end -$var wire 1 H( AandB $end -$var wire 1 I( AnandB $end -$var wire 1 J( AndNandOut $end -$var wire 1 K( B $end -$var wire 3 L( Command [2:0] $end -$scope module potato $end -$var wire 1 M( S $end -$var wire 1 H( in0 $end -$var wire 1 I( in1 $end -$var wire 1 N( nS $end -$var wire 1 O( out0 $end -$var wire 1 P( out1 $end -$var wire 1 J( outfinal $end -$upscope $end -$upscope $end -$upscope $end -$scope begin andbits[13] $end -$scope module attempt $end -$var wire 1 Q( A $end -$var wire 1 R( AandB $end -$var wire 1 S( AnandB $end -$var wire 1 T( AndNandOut $end -$var wire 1 U( B $end -$var wire 3 V( Command [2:0] $end -$scope module potato $end -$var wire 1 W( S $end -$var wire 1 R( in0 $end -$var wire 1 S( in1 $end -$var wire 1 X( nS $end -$var wire 1 Y( out0 $end -$var wire 1 Z( out1 $end -$var wire 1 T( outfinal $end -$upscope $end -$upscope $end -$upscope $end -$scope begin andbits[14] $end -$scope module attempt $end -$var wire 1 [( A $end -$var wire 1 \( AandB $end -$var wire 1 ]( AnandB $end -$var wire 1 ^( AndNandOut $end -$var wire 1 _( B $end -$var wire 3 `( Command [2:0] $end -$scope module potato $end -$var wire 1 a( S $end -$var wire 1 \( in0 $end -$var wire 1 ]( in1 $end -$var wire 1 b( nS $end -$var wire 1 c( out0 $end -$var wire 1 d( out1 $end -$var wire 1 ^( outfinal $end -$upscope $end -$upscope $end -$upscope $end -$scope begin andbits[15] $end -$scope module attempt $end -$var wire 1 e( A $end -$var wire 1 f( AandB $end -$var wire 1 g( AnandB $end -$var wire 1 h( AndNandOut $end -$var wire 1 i( B $end -$var wire 3 j( Command [2:0] $end -$scope module potato $end -$var wire 1 k( S $end -$var wire 1 f( in0 $end -$var wire 1 g( in1 $end -$var wire 1 l( nS $end -$var wire 1 m( out0 $end -$var wire 1 n( out1 $end -$var wire 1 h( outfinal $end -$upscope $end -$upscope $end +$var wire 1 <% S $end +$var wire 1 7% in0 $end +$var wire 1 8% in1 $end +$var wire 1 =% nS $end +$var wire 1 >% out0 $end +$var wire 1 ?% out1 $end +$var wire 1 9% outfinal $end $upscope $end -$scope begin andbits[16] $end -$scope module attempt $end -$var wire 1 o( A $end -$var wire 1 p( AandB $end -$var wire 1 q( AnandB $end -$var wire 1 r( AndNandOut $end -$var wire 1 s( B $end -$var wire 3 t( Command [2:0] $end -$scope module potato $end -$var wire 1 u( S $end -$var wire 1 p( in0 $end -$var wire 1 q( in1 $end -$var wire 1 v( nS $end -$var wire 1 w( out0 $end -$var wire 1 x( out1 $end -$var wire 1 r( outfinal $end $upscope $end $upscope $end $upscope $end -$scope begin andbits[17] $end -$scope module attempt $end -$var wire 1 y( A $end -$var wire 1 z( AandB $end -$var wire 1 {( AnandB $end -$var wire 1 |( AndNandOut $end -$var wire 1 }( B $end -$var wire 3 ~( Command [2:0] $end -$scope module potato $end -$var wire 1 !) S $end -$var wire 1 z( in0 $end -$var wire 1 {( in1 $end -$var wire 1 ") nS $end -$var wire 1 #) out0 $end -$var wire 1 $) out1 $end -$var wire 1 |( outfinal $end +$scope module trial2 $end +$var wire 4 @% A [3:0] $end +$var wire 4 A% B [3:0] $end +$var wire 3 B% Command [2:0] $end +$var wire 4 C% OrNorXorOut [3:0] $end +$scope module attempt2 $end +$var wire 1 D% A $end +$var wire 1 E% AnandB $end +$var wire 1 F% AnorB $end +$var wire 1 G% AorB $end +$var wire 1 H% AxorB $end +$var wire 1 I% B $end +$var wire 3 J% Command [2:0] $end +$var wire 1 K% OrNorXorOut $end +$var wire 1 L% XorNor $end +$var wire 1 M% nXor $end +$scope module mux0 $end +$var wire 1 N% S $end +$var wire 1 H% in0 $end +$var wire 1 F% in1 $end +$var wire 1 O% nS $end +$var wire 1 P% out0 $end +$var wire 1 Q% out1 $end +$var wire 1 L% outfinal $end $upscope $end +$scope module mux1 $end +$var wire 1 R% S $end +$var wire 1 L% in0 $end +$var wire 1 G% in1 $end +$var wire 1 S% nS $end +$var wire 1 T% out0 $end +$var wire 1 U% out1 $end +$var wire 1 K% outfinal $end $upscope $end $upscope $end -$scope begin andbits[18] $end +$scope begin orbits[1] $end $scope module attempt $end -$var wire 1 %) A $end -$var wire 1 &) AandB $end -$var wire 1 ') AnandB $end -$var wire 1 () AndNandOut $end -$var wire 1 )) B $end -$var wire 3 *) Command [2:0] $end -$scope module potato $end -$var wire 1 +) S $end -$var wire 1 &) in0 $end -$var wire 1 ') in1 $end -$var wire 1 ,) nS $end -$var wire 1 -) out0 $end -$var wire 1 .) out1 $end -$var wire 1 () outfinal $end -$upscope $end -$upscope $end +$var wire 1 V% A $end +$var wire 1 W% AnandB $end +$var wire 1 X% AnorB $end +$var wire 1 Y% AorB $end +$var wire 1 Z% AxorB $end +$var wire 1 [% B $end +$var wire 3 \% Command [2:0] $end +$var wire 1 ]% OrNorXorOut $end +$var wire 1 ^% XorNor $end +$var wire 1 _% nXor $end +$scope module mux0 $end +$var wire 1 `% S $end +$var wire 1 Z% in0 $end +$var wire 1 X% in1 $end +$var wire 1 a% nS $end +$var wire 1 b% out0 $end +$var wire 1 c% out1 $end +$var wire 1 ^% outfinal $end $upscope $end -$scope begin andbits[19] $end -$scope module attempt $end -$var wire 1 /) A $end -$var wire 1 0) AandB $end -$var wire 1 1) AnandB $end -$var wire 1 2) AndNandOut $end -$var wire 1 3) B $end -$var wire 3 4) Command [2:0] $end -$scope module potato $end -$var wire 1 5) S $end -$var wire 1 0) in0 $end -$var wire 1 1) in1 $end -$var wire 1 6) nS $end -$var wire 1 7) out0 $end -$var wire 1 8) out1 $end -$var wire 1 2) outfinal $end +$scope module mux1 $end +$var wire 1 d% S $end +$var wire 1 ^% in0 $end +$var wire 1 Y% in1 $end +$var wire 1 e% nS $end +$var wire 1 f% out0 $end +$var wire 1 g% out1 $end +$var wire 1 ]% outfinal $end $upscope $end $upscope $end $upscope $end -$scope begin andbits[20] $end +$scope begin orbits[2] $end $scope module attempt $end -$var wire 1 9) A $end -$var wire 1 :) AandB $end -$var wire 1 ;) AnandB $end -$var wire 1 <) AndNandOut $end -$var wire 1 =) B $end -$var wire 3 >) Command [2:0] $end -$scope module potato $end -$var wire 1 ?) S $end -$var wire 1 :) in0 $end -$var wire 1 ;) in1 $end -$var wire 1 @) nS $end -$var wire 1 A) out0 $end -$var wire 1 B) out1 $end -$var wire 1 <) outfinal $end -$upscope $end -$upscope $end +$var wire 1 h% A $end +$var wire 1 i% AnandB $end +$var wire 1 j% AnorB $end +$var wire 1 k% AorB $end +$var wire 1 l% AxorB $end +$var wire 1 m% B $end +$var wire 3 n% Command [2:0] $end +$var wire 1 o% OrNorXorOut $end +$var wire 1 p% XorNor $end +$var wire 1 q% nXor $end +$scope module mux0 $end +$var wire 1 r% S $end +$var wire 1 l% in0 $end +$var wire 1 j% in1 $end +$var wire 1 s% nS $end +$var wire 1 t% out0 $end +$var wire 1 u% out1 $end +$var wire 1 p% outfinal $end $upscope $end -$scope begin andbits[21] $end -$scope module attempt $end -$var wire 1 C) A $end -$var wire 1 D) AandB $end -$var wire 1 E) AnandB $end -$var wire 1 F) AndNandOut $end -$var wire 1 G) B $end -$var wire 3 H) Command [2:0] $end -$scope module potato $end -$var wire 1 I) S $end -$var wire 1 D) in0 $end -$var wire 1 E) in1 $end -$var wire 1 J) nS $end -$var wire 1 K) out0 $end -$var wire 1 L) out1 $end -$var wire 1 F) outfinal $end +$scope module mux1 $end +$var wire 1 v% S $end +$var wire 1 p% in0 $end +$var wire 1 k% in1 $end +$var wire 1 w% nS $end +$var wire 1 x% out0 $end +$var wire 1 y% out1 $end +$var wire 1 o% outfinal $end $upscope $end $upscope $end $upscope $end -$scope begin andbits[22] $end +$scope begin orbits[3] $end $scope module attempt $end -$var wire 1 M) A $end -$var wire 1 N) AandB $end -$var wire 1 O) AnandB $end -$var wire 1 P) AndNandOut $end -$var wire 1 Q) B $end -$var wire 3 R) Command [2:0] $end -$scope module potato $end -$var wire 1 S) S $end -$var wire 1 N) in0 $end -$var wire 1 O) in1 $end -$var wire 1 T) nS $end -$var wire 1 U) out0 $end -$var wire 1 V) out1 $end -$var wire 1 P) outfinal $end -$upscope $end +$var wire 1 z% A $end +$var wire 1 {% AnandB $end +$var wire 1 |% AnorB $end +$var wire 1 }% AorB $end +$var wire 1 ~% AxorB $end +$var wire 1 !& B $end +$var wire 3 "& Command [2:0] $end +$var wire 1 #& OrNorXorOut $end +$var wire 1 $& XorNor $end +$var wire 1 %& nXor $end +$scope module mux0 $end +$var wire 1 && S $end +$var wire 1 ~% in0 $end +$var wire 1 |% in1 $end +$var wire 1 '& nS $end +$var wire 1 (& out0 $end +$var wire 1 )& out1 $end +$var wire 1 $& outfinal $end $upscope $end +$scope module mux1 $end +$var wire 1 *& S $end +$var wire 1 $& in0 $end +$var wire 1 }% in1 $end +$var wire 1 +& nS $end +$var wire 1 ,& out0 $end +$var wire 1 -& out1 $end +$var wire 1 #& outfinal $end $upscope $end -$scope begin andbits[23] $end -$scope module attempt $end -$var wire 1 W) A $end -$var wire 1 X) AandB $end -$var wire 1 Y) AnandB $end -$var wire 1 Z) AndNandOut $end -$var wire 1 [) B $end -$var wire 3 \) Command [2:0] $end -$scope module potato $end -$var wire 1 ]) S $end -$var wire 1 X) in0 $end -$var wire 1 Y) in1 $end -$var wire 1 ^) nS $end -$var wire 1 _) out0 $end -$var wire 1 `) out1 $end -$var wire 1 Z) outfinal $end $upscope $end $upscope $end $upscope $end -$scope begin andbits[24] $end -$scope module attempt $end -$var wire 1 a) A $end -$var wire 1 b) AandB $end -$var wire 1 c) AnandB $end -$var wire 1 d) AndNandOut $end -$var wire 1 e) B $end -$var wire 3 f) Command [2:0] $end -$scope module potato $end -$var wire 1 g) S $end -$var wire 1 b) in0 $end -$var wire 1 c) in1 $end -$var wire 1 h) nS $end -$var wire 1 i) out0 $end -$var wire 1 j) out1 $end -$var wire 1 d) outfinal $end +$scope module ZeroMux0case $end +$var wire 1 .& S0 $end +$var wire 1 /& S1 $end +$var wire 1 0& in0 $end +$var wire 1 1& in1 $end +$var wire 1 2& in2 $end +$var wire 1 3& in3 $end +$var wire 1 4& nS0 $end +$var wire 1 5& nS1 $end +$var wire 1 6& out $end +$var wire 1 7& out0 $end +$var wire 1 8& out1 $end +$var wire 1 9& out2 $end +$var wire 1 :& out3 $end $upscope $end +$scope module OneMux0case $end +$var wire 1 ;& S0 $end +$var wire 1 <& S1 $end +$var wire 1 =& in0 $end +$var wire 1 >& in1 $end +$var wire 1 ?& in2 $end +$var wire 1 @& in3 $end +$var wire 1 A& nS0 $end +$var wire 1 B& nS1 $end +$var wire 1 C& out $end +$var wire 1 D& out0 $end +$var wire 1 E& out1 $end +$var wire 1 F& out2 $end +$var wire 1 G& out3 $end $upscope $end +$scope module TwoMux0case $end +$var wire 1 H& S $end +$var wire 1 I& in0 $end +$var wire 1 J& in1 $end +$var wire 1 K& nS $end +$var wire 1 L& out0 $end +$var wire 1 M& out1 $end +$var wire 1 N& outfinal $end $upscope $end -$scope begin andbits[25] $end -$scope module attempt $end -$var wire 1 k) A $end -$var wire 1 l) AandB $end -$var wire 1 m) AnandB $end -$var wire 1 n) AndNandOut $end -$var wire 1 o) B $end -$var wire 3 p) Command [2:0] $end -$scope module potato $end -$var wire 1 q) S $end -$var wire 1 l) in0 $end -$var wire 1 m) in1 $end -$var wire 1 r) nS $end -$var wire 1 s) out0 $end -$var wire 1 t) out1 $end -$var wire 1 n) outfinal $end +$scope begin muxbits[1] $end +$scope module ZeroMux $end +$var wire 1 O& S0 $end +$var wire 1 P& S1 $end +$var wire 1 Q& in0 $end +$var wire 1 R& in1 $end +$var wire 1 S& in2 $end +$var wire 1 T& in3 $end +$var wire 1 U& nS0 $end +$var wire 1 V& nS1 $end +$var wire 1 W& out $end +$var wire 1 X& out0 $end +$var wire 1 Y& out1 $end +$var wire 1 Z& out2 $end +$var wire 1 [& out3 $end $upscope $end +$scope module OneMux $end +$var wire 1 \& S0 $end +$var wire 1 ]& S1 $end +$var wire 1 ^& in0 $end +$var wire 1 _& in1 $end +$var wire 1 `& in2 $end +$var wire 1 a& in3 $end +$var wire 1 b& nS0 $end +$var wire 1 c& nS1 $end +$var wire 1 d& out $end +$var wire 1 e& out0 $end +$var wire 1 f& out1 $end +$var wire 1 g& out2 $end +$var wire 1 h& out3 $end $upscope $end +$scope module TwoMux $end +$var wire 1 i& S $end +$var wire 1 j& in0 $end +$var wire 1 k& in1 $end +$var wire 1 l& nS $end +$var wire 1 m& out0 $end +$var wire 1 n& out1 $end +$var wire 1 o& outfinal $end $upscope $end -$scope begin andbits[26] $end -$scope module attempt $end -$var wire 1 u) A $end -$var wire 1 v) AandB $end -$var wire 1 w) AnandB $end -$var wire 1 x) AndNandOut $end -$var wire 1 y) B $end -$var wire 3 z) Command [2:0] $end -$scope module potato $end -$var wire 1 {) S $end -$var wire 1 v) in0 $end -$var wire 1 w) in1 $end -$var wire 1 |) nS $end -$var wire 1 }) out0 $end -$var wire 1 ~) out1 $end -$var wire 1 x) outfinal $end $upscope $end +$scope begin muxbits[2] $end +$scope module ZeroMux $end +$var wire 1 p& S0 $end +$var wire 1 q& S1 $end +$var wire 1 r& in0 $end +$var wire 1 s& in1 $end +$var wire 1 t& in2 $end +$var wire 1 u& in3 $end +$var wire 1 v& nS0 $end +$var wire 1 w& nS1 $end +$var wire 1 x& out $end +$var wire 1 y& out0 $end +$var wire 1 z& out1 $end +$var wire 1 {& out2 $end +$var wire 1 |& out3 $end $upscope $end +$scope module OneMux $end +$var wire 1 }& S0 $end +$var wire 1 ~& S1 $end +$var wire 1 !' in0 $end +$var wire 1 "' in1 $end +$var wire 1 #' in2 $end +$var wire 1 $' in3 $end +$var wire 1 %' nS0 $end +$var wire 1 &' nS1 $end +$var wire 1 '' out $end +$var wire 1 (' out0 $end +$var wire 1 )' out1 $end +$var wire 1 *' out2 $end +$var wire 1 +' out3 $end $upscope $end -$scope begin andbits[27] $end -$scope module attempt $end -$var wire 1 !* A $end -$var wire 1 "* AandB $end -$var wire 1 #* AnandB $end -$var wire 1 $* AndNandOut $end -$var wire 1 %* B $end -$var wire 3 &* Command [2:0] $end -$scope module potato $end -$var wire 1 '* S $end -$var wire 1 "* in0 $end -$var wire 1 #* in1 $end -$var wire 1 (* nS $end -$var wire 1 )* out0 $end -$var wire 1 ** out1 $end -$var wire 1 $* outfinal $end +$scope module TwoMux $end +$var wire 1 ,' S $end +$var wire 1 -' in0 $end +$var wire 1 .' in1 $end +$var wire 1 /' nS $end +$var wire 1 0' out0 $end +$var wire 1 1' out1 $end +$var wire 1 2' outfinal $end $upscope $end $upscope $end +$scope begin muxbits[3] $end +$scope module ZeroMux $end +$var wire 1 3' S0 $end +$var wire 1 4' S1 $end +$var wire 1 5' in0 $end +$var wire 1 6' in1 $end +$var wire 1 7' in2 $end +$var wire 1 8' in3 $end +$var wire 1 9' nS0 $end +$var wire 1 :' nS1 $end +$var wire 1 ;' out $end +$var wire 1 <' out0 $end +$var wire 1 =' out1 $end +$var wire 1 >' out2 $end +$var wire 1 ?' out3 $end $upscope $end -$scope begin andbits[28] $end -$scope module attempt $end -$var wire 1 +* A $end -$var wire 1 ,* AandB $end -$var wire 1 -* AnandB $end -$var wire 1 .* AndNandOut $end -$var wire 1 /* B $end -$var wire 3 0* Command [2:0] $end -$scope module potato $end -$var wire 1 1* S $end -$var wire 1 ,* in0 $end -$var wire 1 -* in1 $end -$var wire 1 2* nS $end -$var wire 1 3* out0 $end -$var wire 1 4* out1 $end -$var wire 1 .* outfinal $end +$scope module OneMux $end +$var wire 1 @' S0 $end +$var wire 1 A' S1 $end +$var wire 1 B' in0 $end +$var wire 1 C' in1 $end +$var wire 1 D' in2 $end +$var wire 1 E' in3 $end +$var wire 1 F' nS0 $end +$var wire 1 G' nS1 $end +$var wire 1 H' out $end +$var wire 1 I' out0 $end +$var wire 1 J' out1 $end +$var wire 1 K' out2 $end +$var wire 1 L' out3 $end $upscope $end -$upscope $end -$upscope $end -$scope begin andbits[29] $end -$scope module attempt $end -$var wire 1 5* A $end -$var wire 1 6* AandB $end -$var wire 1 7* AnandB $end -$var wire 1 8* AndNandOut $end -$var wire 1 9* B $end -$var wire 3 :* Command [2:0] $end -$scope module potato $end -$var wire 1 ;* S $end -$var wire 1 6* in0 $end -$var wire 1 7* in1 $end -$var wire 1 <* nS $end -$var wire 1 =* out0 $end -$var wire 1 >* out1 $end -$var wire 1 8* outfinal $end -$upscope $end -$upscope $end -$upscope $end -$scope begin andbits[30] $end -$scope module attempt $end -$var wire 1 ?* A $end -$var wire 1 @* AandB $end -$var wire 1 A* AnandB $end -$var wire 1 B* AndNandOut $end -$var wire 1 C* B $end -$var wire 3 D* Command [2:0] $end -$scope module potato $end -$var wire 1 E* S $end -$var wire 1 @* in0 $end -$var wire 1 A* in1 $end -$var wire 1 F* nS $end -$var wire 1 G* out0 $end -$var wire 1 H* out1 $end -$var wire 1 B* outfinal $end -$upscope $end -$upscope $end -$upscope $end -$scope begin andbits[31] $end -$scope module attempt $end -$var wire 1 I* A $end -$var wire 1 J* AandB $end -$var wire 1 K* AnandB $end -$var wire 1 L* AndNandOut $end -$var wire 1 M* B $end -$var wire 3 N* Command [2:0] $end -$scope module potato $end -$var wire 1 O* S $end -$var wire 1 J* in0 $end -$var wire 1 K* in1 $end -$var wire 1 P* nS $end -$var wire 1 Q* out0 $end -$var wire 1 R* out1 $end -$var wire 1 L* outfinal $end -$upscope $end -$upscope $end -$upscope $end -$upscope $end -$scope module trial2 $end -$var wire 32 S* A [31:0] $end -$var wire 32 T* B [31:0] $end -$var wire 3 U* Command [2:0] $end -$var wire 32 V* OrNorXorOut [31:0] $end -$scope module attempt2 $end -$var wire 1 W* A $end -$var wire 1 X* AnandB $end -$var wire 1 Y* AnorB $end -$var wire 1 Z* AorB $end -$var wire 1 [* AxorB $end -$var wire 1 \* B $end -$var wire 3 ]* Command [2:0] $end -$var wire 1 ^* OrNorXorOut $end -$var wire 1 _* XorNor $end -$var wire 1 `* nXor $end -$scope module mux0 $end -$var wire 1 a* S $end -$var wire 1 [* in0 $end -$var wire 1 Y* in1 $end -$var wire 1 b* nS $end -$var wire 1 c* out0 $end -$var wire 1 d* out1 $end -$var wire 1 _* outfinal $end -$upscope $end -$scope module mux1 $end -$var wire 1 e* S $end -$var wire 1 _* in0 $end -$var wire 1 Z* in1 $end -$var wire 1 f* nS $end -$var wire 1 g* out0 $end -$var wire 1 h* out1 $end -$var wire 1 ^* outfinal $end -$upscope $end -$upscope $end -$scope begin orbits[1] $end -$scope module attempt $end -$var wire 1 i* A $end -$var wire 1 j* AnandB $end -$var wire 1 k* AnorB $end -$var wire 1 l* AorB $end -$var wire 1 m* AxorB $end -$var wire 1 n* B $end -$var wire 3 o* Command [2:0] $end -$var wire 1 p* OrNorXorOut $end -$var wire 1 q* XorNor $end -$var wire 1 r* nXor $end -$scope module mux0 $end -$var wire 1 s* S $end -$var wire 1 m* in0 $end -$var wire 1 k* in1 $end -$var wire 1 t* nS $end -$var wire 1 u* out0 $end -$var wire 1 v* out1 $end -$var wire 1 q* outfinal $end -$upscope $end -$scope module mux1 $end -$var wire 1 w* S $end -$var wire 1 q* in0 $end -$var wire 1 l* in1 $end -$var wire 1 x* nS $end -$var wire 1 y* out0 $end -$var wire 1 z* out1 $end -$var wire 1 p* outfinal $end -$upscope $end -$upscope $end -$upscope $end -$scope begin orbits[2] $end -$scope module attempt $end -$var wire 1 {* A $end -$var wire 1 |* AnandB $end -$var wire 1 }* AnorB $end -$var wire 1 ~* AorB $end -$var wire 1 !+ AxorB $end -$var wire 1 "+ B $end -$var wire 3 #+ Command [2:0] $end -$var wire 1 $+ OrNorXorOut $end -$var wire 1 %+ XorNor $end -$var wire 1 &+ nXor $end -$scope module mux0 $end -$var wire 1 '+ S $end -$var wire 1 !+ in0 $end -$var wire 1 }* in1 $end -$var wire 1 (+ nS $end -$var wire 1 )+ out0 $end -$var wire 1 *+ out1 $end -$var wire 1 %+ outfinal $end -$upscope $end -$scope module mux1 $end -$var wire 1 ++ S $end -$var wire 1 %+ in0 $end -$var wire 1 ~* in1 $end -$var wire 1 ,+ nS $end -$var wire 1 -+ out0 $end -$var wire 1 .+ out1 $end -$var wire 1 $+ outfinal $end -$upscope $end -$upscope $end -$upscope $end -$scope begin orbits[3] $end -$scope module attempt $end -$var wire 1 /+ A $end -$var wire 1 0+ AnandB $end -$var wire 1 1+ AnorB $end -$var wire 1 2+ AorB $end -$var wire 1 3+ AxorB $end -$var wire 1 4+ B $end -$var wire 3 5+ Command [2:0] $end -$var wire 1 6+ OrNorXorOut $end -$var wire 1 7+ XorNor $end -$var wire 1 8+ nXor $end -$scope module mux0 $end -$var wire 1 9+ S $end -$var wire 1 3+ in0 $end -$var wire 1 1+ in1 $end -$var wire 1 :+ nS $end -$var wire 1 ;+ out0 $end -$var wire 1 <+ out1 $end -$var wire 1 7+ outfinal $end -$upscope $end -$scope module mux1 $end -$var wire 1 =+ S $end -$var wire 1 7+ in0 $end -$var wire 1 2+ in1 $end -$var wire 1 >+ nS $end -$var wire 1 ?+ out0 $end -$var wire 1 @+ out1 $end -$var wire 1 6+ outfinal $end -$upscope $end -$upscope $end -$upscope $end -$scope begin orbits[4] $end -$scope module attempt $end -$var wire 1 A+ A $end -$var wire 1 B+ AnandB $end -$var wire 1 C+ AnorB $end -$var wire 1 D+ AorB $end -$var wire 1 E+ AxorB $end -$var wire 1 F+ B $end -$var wire 3 G+ Command [2:0] $end -$var wire 1 H+ OrNorXorOut $end -$var wire 1 I+ XorNor $end -$var wire 1 J+ nXor $end -$scope module mux0 $end -$var wire 1 K+ S $end -$var wire 1 E+ in0 $end -$var wire 1 C+ in1 $end -$var wire 1 L+ nS $end -$var wire 1 M+ out0 $end -$var wire 1 N+ out1 $end -$var wire 1 I+ outfinal $end -$upscope $end -$scope module mux1 $end -$var wire 1 O+ S $end -$var wire 1 I+ in0 $end -$var wire 1 D+ in1 $end -$var wire 1 P+ nS $end -$var wire 1 Q+ out0 $end -$var wire 1 R+ out1 $end -$var wire 1 H+ outfinal $end -$upscope $end -$upscope $end -$upscope $end -$scope begin orbits[5] $end -$scope module attempt $end -$var wire 1 S+ A $end -$var wire 1 T+ AnandB $end -$var wire 1 U+ AnorB $end -$var wire 1 V+ AorB $end -$var wire 1 W+ AxorB $end -$var wire 1 X+ B $end -$var wire 3 Y+ Command [2:0] $end -$var wire 1 Z+ OrNorXorOut $end -$var wire 1 [+ XorNor $end -$var wire 1 \+ nXor $end -$scope module mux0 $end -$var wire 1 ]+ S $end -$var wire 1 W+ in0 $end -$var wire 1 U+ in1 $end -$var wire 1 ^+ nS $end -$var wire 1 _+ out0 $end -$var wire 1 `+ out1 $end -$var wire 1 [+ outfinal $end -$upscope $end -$scope module mux1 $end -$var wire 1 a+ S $end -$var wire 1 [+ in0 $end -$var wire 1 V+ in1 $end -$var wire 1 b+ nS $end -$var wire 1 c+ out0 $end -$var wire 1 d+ out1 $end -$var wire 1 Z+ outfinal $end -$upscope $end -$upscope $end -$upscope $end -$scope begin orbits[6] $end -$scope module attempt $end -$var wire 1 e+ A $end -$var wire 1 f+ AnandB $end -$var wire 1 g+ AnorB $end -$var wire 1 h+ AorB $end -$var wire 1 i+ AxorB $end -$var wire 1 j+ B $end -$var wire 3 k+ Command [2:0] $end -$var wire 1 l+ OrNorXorOut $end -$var wire 1 m+ XorNor $end -$var wire 1 n+ nXor $end -$scope module mux0 $end -$var wire 1 o+ S $end -$var wire 1 i+ in0 $end -$var wire 1 g+ in1 $end -$var wire 1 p+ nS $end -$var wire 1 q+ out0 $end -$var wire 1 r+ out1 $end -$var wire 1 m+ outfinal $end -$upscope $end -$scope module mux1 $end -$var wire 1 s+ S $end -$var wire 1 m+ in0 $end -$var wire 1 h+ in1 $end -$var wire 1 t+ nS $end -$var wire 1 u+ out0 $end -$var wire 1 v+ out1 $end -$var wire 1 l+ outfinal $end -$upscope $end -$upscope $end -$upscope $end -$scope begin orbits[7] $end -$scope module attempt $end -$var wire 1 w+ A $end -$var wire 1 x+ AnandB $end -$var wire 1 y+ AnorB $end -$var wire 1 z+ AorB $end -$var wire 1 {+ AxorB $end -$var wire 1 |+ B $end -$var wire 3 }+ Command [2:0] $end -$var wire 1 ~+ OrNorXorOut $end -$var wire 1 !, XorNor $end -$var wire 1 ", nXor $end -$scope module mux0 $end -$var wire 1 #, S $end -$var wire 1 {+ in0 $end -$var wire 1 y+ in1 $end -$var wire 1 $, nS $end -$var wire 1 %, out0 $end -$var wire 1 &, out1 $end -$var wire 1 !, outfinal $end -$upscope $end -$scope module mux1 $end -$var wire 1 ', S $end -$var wire 1 !, in0 $end -$var wire 1 z+ in1 $end -$var wire 1 (, nS $end -$var wire 1 ), out0 $end -$var wire 1 *, out1 $end -$var wire 1 ~+ outfinal $end -$upscope $end -$upscope $end -$upscope $end -$scope begin orbits[8] $end -$scope module attempt $end -$var wire 1 +, A $end -$var wire 1 ,, AnandB $end -$var wire 1 -, AnorB $end -$var wire 1 ., AorB $end -$var wire 1 /, AxorB $end -$var wire 1 0, B $end -$var wire 3 1, Command [2:0] $end -$var wire 1 2, OrNorXorOut $end -$var wire 1 3, XorNor $end -$var wire 1 4, nXor $end -$scope module mux0 $end -$var wire 1 5, S $end -$var wire 1 /, in0 $end -$var wire 1 -, in1 $end -$var wire 1 6, nS $end -$var wire 1 7, out0 $end -$var wire 1 8, out1 $end -$var wire 1 3, outfinal $end -$upscope $end -$scope module mux1 $end -$var wire 1 9, S $end -$var wire 1 3, in0 $end -$var wire 1 ., in1 $end -$var wire 1 :, nS $end -$var wire 1 ;, out0 $end -$var wire 1 <, out1 $end -$var wire 1 2, outfinal $end -$upscope $end -$upscope $end -$upscope $end -$scope begin orbits[9] $end -$scope module attempt $end -$var wire 1 =, A $end -$var wire 1 >, AnandB $end -$var wire 1 ?, AnorB $end -$var wire 1 @, AorB $end -$var wire 1 A, AxorB $end -$var wire 1 B, B $end -$var wire 3 C, Command [2:0] $end -$var wire 1 D, OrNorXorOut $end -$var wire 1 E, XorNor $end -$var wire 1 F, nXor $end -$scope module mux0 $end -$var wire 1 G, S $end -$var wire 1 A, in0 $end -$var wire 1 ?, in1 $end -$var wire 1 H, nS $end -$var wire 1 I, out0 $end -$var wire 1 J, out1 $end -$var wire 1 E, outfinal $end -$upscope $end -$scope module mux1 $end -$var wire 1 K, S $end -$var wire 1 E, in0 $end -$var wire 1 @, in1 $end -$var wire 1 L, nS $end -$var wire 1 M, out0 $end -$var wire 1 N, out1 $end -$var wire 1 D, outfinal $end -$upscope $end -$upscope $end -$upscope $end -$scope begin orbits[10] $end -$scope module attempt $end -$var wire 1 O, A $end -$var wire 1 P, AnandB $end -$var wire 1 Q, AnorB $end -$var wire 1 R, AorB $end -$var wire 1 S, AxorB $end -$var wire 1 T, B $end -$var wire 3 U, Command [2:0] $end -$var wire 1 V, OrNorXorOut $end -$var wire 1 W, XorNor $end -$var wire 1 X, nXor $end -$scope module mux0 $end -$var wire 1 Y, S $end -$var wire 1 S, in0 $end -$var wire 1 Q, in1 $end -$var wire 1 Z, nS $end -$var wire 1 [, out0 $end -$var wire 1 \, out1 $end -$var wire 1 W, outfinal $end -$upscope $end -$scope module mux1 $end -$var wire 1 ], S $end -$var wire 1 W, in0 $end -$var wire 1 R, in1 $end -$var wire 1 ^, nS $end -$var wire 1 _, out0 $end -$var wire 1 `, out1 $end -$var wire 1 V, outfinal $end -$upscope $end -$upscope $end -$upscope $end -$scope begin orbits[11] $end -$scope module attempt $end -$var wire 1 a, A $end -$var wire 1 b, AnandB $end -$var wire 1 c, AnorB $end -$var wire 1 d, AorB $end -$var wire 1 e, AxorB $end -$var wire 1 f, B $end -$var wire 3 g, Command [2:0] $end -$var wire 1 h, OrNorXorOut $end -$var wire 1 i, XorNor $end -$var wire 1 j, nXor $end -$scope module mux0 $end -$var wire 1 k, S $end -$var wire 1 e, in0 $end -$var wire 1 c, in1 $end -$var wire 1 l, nS $end -$var wire 1 m, out0 $end -$var wire 1 n, out1 $end -$var wire 1 i, outfinal $end -$upscope $end -$scope module mux1 $end -$var wire 1 o, S $end -$var wire 1 i, in0 $end -$var wire 1 d, in1 $end -$var wire 1 p, nS $end -$var wire 1 q, out0 $end -$var wire 1 r, out1 $end -$var wire 1 h, outfinal $end -$upscope $end -$upscope $end -$upscope $end -$scope begin orbits[12] $end -$scope module attempt $end -$var wire 1 s, A $end -$var wire 1 t, AnandB $end -$var wire 1 u, AnorB $end -$var wire 1 v, AorB $end -$var wire 1 w, AxorB $end -$var wire 1 x, B $end -$var wire 3 y, Command [2:0] $end -$var wire 1 z, OrNorXorOut $end -$var wire 1 {, XorNor $end -$var wire 1 |, nXor $end -$scope module mux0 $end -$var wire 1 }, S $end -$var wire 1 w, in0 $end -$var wire 1 u, in1 $end -$var wire 1 ~, nS $end -$var wire 1 !- out0 $end -$var wire 1 "- out1 $end -$var wire 1 {, outfinal $end -$upscope $end -$scope module mux1 $end -$var wire 1 #- S $end -$var wire 1 {, in0 $end -$var wire 1 v, in1 $end -$var wire 1 $- nS $end -$var wire 1 %- out0 $end -$var wire 1 &- out1 $end -$var wire 1 z, outfinal $end -$upscope $end -$upscope $end -$upscope $end -$scope begin orbits[13] $end -$scope module attempt $end -$var wire 1 '- A $end -$var wire 1 (- AnandB $end -$var wire 1 )- AnorB $end -$var wire 1 *- AorB $end -$var wire 1 +- AxorB $end -$var wire 1 ,- B $end -$var wire 3 -- Command [2:0] $end -$var wire 1 .- OrNorXorOut $end -$var wire 1 /- XorNor $end -$var wire 1 0- nXor $end -$scope module mux0 $end -$var wire 1 1- S $end -$var wire 1 +- in0 $end -$var wire 1 )- in1 $end -$var wire 1 2- nS $end -$var wire 1 3- out0 $end -$var wire 1 4- out1 $end -$var wire 1 /- outfinal $end -$upscope $end -$scope module mux1 $end -$var wire 1 5- S $end -$var wire 1 /- in0 $end -$var wire 1 *- in1 $end -$var wire 1 6- nS $end -$var wire 1 7- out0 $end -$var wire 1 8- out1 $end -$var wire 1 .- outfinal $end -$upscope $end -$upscope $end -$upscope $end -$scope begin orbits[14] $end -$scope module attempt $end -$var wire 1 9- A $end -$var wire 1 :- AnandB $end -$var wire 1 ;- AnorB $end -$var wire 1 <- AorB $end -$var wire 1 =- AxorB $end -$var wire 1 >- B $end -$var wire 3 ?- Command [2:0] $end -$var wire 1 @- OrNorXorOut $end -$var wire 1 A- XorNor $end -$var wire 1 B- nXor $end -$scope module mux0 $end -$var wire 1 C- S $end -$var wire 1 =- in0 $end -$var wire 1 ;- in1 $end -$var wire 1 D- nS $end -$var wire 1 E- out0 $end -$var wire 1 F- out1 $end -$var wire 1 A- outfinal $end -$upscope $end -$scope module mux1 $end -$var wire 1 G- S $end -$var wire 1 A- in0 $end -$var wire 1 <- in1 $end -$var wire 1 H- nS $end -$var wire 1 I- out0 $end -$var wire 1 J- out1 $end -$var wire 1 @- outfinal $end -$upscope $end -$upscope $end -$upscope $end -$scope begin orbits[15] $end -$scope module attempt $end -$var wire 1 K- A $end -$var wire 1 L- AnandB $end -$var wire 1 M- AnorB $end -$var wire 1 N- AorB $end -$var wire 1 O- AxorB $end -$var wire 1 P- B $end -$var wire 3 Q- Command [2:0] $end -$var wire 1 R- OrNorXorOut $end -$var wire 1 S- XorNor $end -$var wire 1 T- nXor $end -$scope module mux0 $end -$var wire 1 U- S $end -$var wire 1 O- in0 $end -$var wire 1 M- in1 $end -$var wire 1 V- nS $end -$var wire 1 W- out0 $end -$var wire 1 X- out1 $end -$var wire 1 S- outfinal $end -$upscope $end -$scope module mux1 $end -$var wire 1 Y- S $end -$var wire 1 S- in0 $end -$var wire 1 N- in1 $end -$var wire 1 Z- nS $end -$var wire 1 [- out0 $end -$var wire 1 \- out1 $end -$var wire 1 R- outfinal $end -$upscope $end -$upscope $end -$upscope $end -$scope begin orbits[16] $end -$scope module attempt $end -$var wire 1 ]- A $end -$var wire 1 ^- AnandB $end -$var wire 1 _- AnorB $end -$var wire 1 `- AorB $end -$var wire 1 a- AxorB $end -$var wire 1 b- B $end -$var wire 3 c- Command [2:0] $end -$var wire 1 d- OrNorXorOut $end -$var wire 1 e- XorNor $end -$var wire 1 f- nXor $end -$scope module mux0 $end -$var wire 1 g- S $end -$var wire 1 a- in0 $end -$var wire 1 _- in1 $end -$var wire 1 h- nS $end -$var wire 1 i- out0 $end -$var wire 1 j- out1 $end -$var wire 1 e- outfinal $end -$upscope $end -$scope module mux1 $end -$var wire 1 k- S $end -$var wire 1 e- in0 $end -$var wire 1 `- in1 $end -$var wire 1 l- nS $end -$var wire 1 m- out0 $end -$var wire 1 n- out1 $end -$var wire 1 d- outfinal $end -$upscope $end -$upscope $end -$upscope $end -$scope begin orbits[17] $end -$scope module attempt $end -$var wire 1 o- A $end -$var wire 1 p- AnandB $end -$var wire 1 q- AnorB $end -$var wire 1 r- AorB $end -$var wire 1 s- AxorB $end -$var wire 1 t- B $end -$var wire 3 u- Command [2:0] $end -$var wire 1 v- OrNorXorOut $end -$var wire 1 w- XorNor $end -$var wire 1 x- nXor $end -$scope module mux0 $end -$var wire 1 y- S $end -$var wire 1 s- in0 $end -$var wire 1 q- in1 $end -$var wire 1 z- nS $end -$var wire 1 {- out0 $end -$var wire 1 |- out1 $end -$var wire 1 w- outfinal $end -$upscope $end -$scope module mux1 $end -$var wire 1 }- S $end -$var wire 1 w- in0 $end -$var wire 1 r- in1 $end -$var wire 1 ~- nS $end -$var wire 1 !. out0 $end -$var wire 1 ". out1 $end -$var wire 1 v- outfinal $end -$upscope $end -$upscope $end -$upscope $end -$scope begin orbits[18] $end -$scope module attempt $end -$var wire 1 #. A $end -$var wire 1 $. AnandB $end -$var wire 1 %. AnorB $end -$var wire 1 &. AorB $end -$var wire 1 '. AxorB $end -$var wire 1 (. B $end -$var wire 3 ). Command [2:0] $end -$var wire 1 *. OrNorXorOut $end -$var wire 1 +. XorNor $end -$var wire 1 ,. nXor $end -$scope module mux0 $end -$var wire 1 -. S $end -$var wire 1 '. in0 $end -$var wire 1 %. in1 $end -$var wire 1 .. nS $end -$var wire 1 /. out0 $end -$var wire 1 0. out1 $end -$var wire 1 +. outfinal $end -$upscope $end -$scope module mux1 $end -$var wire 1 1. S $end -$var wire 1 +. in0 $end -$var wire 1 &. in1 $end -$var wire 1 2. nS $end -$var wire 1 3. out0 $end -$var wire 1 4. out1 $end -$var wire 1 *. outfinal $end -$upscope $end -$upscope $end -$upscope $end -$scope begin orbits[19] $end -$scope module attempt $end -$var wire 1 5. A $end -$var wire 1 6. AnandB $end -$var wire 1 7. AnorB $end -$var wire 1 8. AorB $end -$var wire 1 9. AxorB $end -$var wire 1 :. B $end -$var wire 3 ;. Command [2:0] $end -$var wire 1 <. OrNorXorOut $end -$var wire 1 =. XorNor $end -$var wire 1 >. nXor $end -$scope module mux0 $end -$var wire 1 ?. S $end -$var wire 1 9. in0 $end -$var wire 1 7. in1 $end -$var wire 1 @. nS $end -$var wire 1 A. out0 $end -$var wire 1 B. out1 $end -$var wire 1 =. outfinal $end -$upscope $end -$scope module mux1 $end -$var wire 1 C. S $end -$var wire 1 =. in0 $end -$var wire 1 8. in1 $end -$var wire 1 D. nS $end -$var wire 1 E. out0 $end -$var wire 1 F. out1 $end -$var wire 1 <. outfinal $end -$upscope $end -$upscope $end -$upscope $end -$scope begin orbits[20] $end -$scope module attempt $end -$var wire 1 G. A $end -$var wire 1 H. AnandB $end -$var wire 1 I. AnorB $end -$var wire 1 J. AorB $end -$var wire 1 K. AxorB $end -$var wire 1 L. B $end -$var wire 3 M. Command [2:0] $end -$var wire 1 N. OrNorXorOut $end -$var wire 1 O. XorNor $end -$var wire 1 P. nXor $end -$scope module mux0 $end -$var wire 1 Q. S $end -$var wire 1 K. in0 $end -$var wire 1 I. in1 $end -$var wire 1 R. nS $end -$var wire 1 S. out0 $end -$var wire 1 T. out1 $end -$var wire 1 O. outfinal $end -$upscope $end -$scope module mux1 $end -$var wire 1 U. S $end -$var wire 1 O. in0 $end -$var wire 1 J. in1 $end -$var wire 1 V. nS $end -$var wire 1 W. out0 $end -$var wire 1 X. out1 $end -$var wire 1 N. outfinal $end -$upscope $end -$upscope $end -$upscope $end -$scope begin orbits[21] $end -$scope module attempt $end -$var wire 1 Y. A $end -$var wire 1 Z. AnandB $end -$var wire 1 [. AnorB $end -$var wire 1 \. AorB $end -$var wire 1 ]. AxorB $end -$var wire 1 ^. B $end -$var wire 3 _. Command [2:0] $end -$var wire 1 `. OrNorXorOut $end -$var wire 1 a. XorNor $end -$var wire 1 b. nXor $end -$scope module mux0 $end -$var wire 1 c. S $end -$var wire 1 ]. in0 $end -$var wire 1 [. in1 $end -$var wire 1 d. nS $end -$var wire 1 e. out0 $end -$var wire 1 f. out1 $end -$var wire 1 a. outfinal $end -$upscope $end -$scope module mux1 $end -$var wire 1 g. S $end -$var wire 1 a. in0 $end -$var wire 1 \. in1 $end -$var wire 1 h. nS $end -$var wire 1 i. out0 $end -$var wire 1 j. out1 $end -$var wire 1 `. outfinal $end -$upscope $end -$upscope $end -$upscope $end -$scope begin orbits[22] $end -$scope module attempt $end -$var wire 1 k. A $end -$var wire 1 l. AnandB $end -$var wire 1 m. AnorB $end -$var wire 1 n. AorB $end -$var wire 1 o. AxorB $end -$var wire 1 p. B $end -$var wire 3 q. Command [2:0] $end -$var wire 1 r. OrNorXorOut $end -$var wire 1 s. XorNor $end -$var wire 1 t. nXor $end -$scope module mux0 $end -$var wire 1 u. S $end -$var wire 1 o. in0 $end -$var wire 1 m. in1 $end -$var wire 1 v. nS $end -$var wire 1 w. out0 $end -$var wire 1 x. out1 $end -$var wire 1 s. outfinal $end -$upscope $end -$scope module mux1 $end -$var wire 1 y. S $end -$var wire 1 s. in0 $end -$var wire 1 n. in1 $end -$var wire 1 z. nS $end -$var wire 1 {. out0 $end -$var wire 1 |. out1 $end -$var wire 1 r. outfinal $end -$upscope $end -$upscope $end -$upscope $end -$scope begin orbits[23] $end -$scope module attempt $end -$var wire 1 }. A $end -$var wire 1 ~. AnandB $end -$var wire 1 !/ AnorB $end -$var wire 1 "/ AorB $end -$var wire 1 #/ AxorB $end -$var wire 1 $/ B $end -$var wire 3 %/ Command [2:0] $end -$var wire 1 &/ OrNorXorOut $end -$var wire 1 '/ XorNor $end -$var wire 1 (/ nXor $end -$scope module mux0 $end -$var wire 1 )/ S $end -$var wire 1 #/ in0 $end -$var wire 1 !/ in1 $end -$var wire 1 */ nS $end -$var wire 1 +/ out0 $end -$var wire 1 ,/ out1 $end -$var wire 1 '/ outfinal $end -$upscope $end -$scope module mux1 $end -$var wire 1 -/ S $end -$var wire 1 '/ in0 $end -$var wire 1 "/ in1 $end -$var wire 1 ./ nS $end -$var wire 1 // out0 $end -$var wire 1 0/ out1 $end -$var wire 1 &/ outfinal $end -$upscope $end -$upscope $end -$upscope $end -$scope begin orbits[24] $end -$scope module attempt $end -$var wire 1 1/ A $end -$var wire 1 2/ AnandB $end -$var wire 1 3/ AnorB $end -$var wire 1 4/ AorB $end -$var wire 1 5/ AxorB $end -$var wire 1 6/ B $end -$var wire 3 7/ Command [2:0] $end -$var wire 1 8/ OrNorXorOut $end -$var wire 1 9/ XorNor $end -$var wire 1 :/ nXor $end -$scope module mux0 $end -$var wire 1 ;/ S $end -$var wire 1 5/ in0 $end -$var wire 1 3/ in1 $end -$var wire 1 / out1 $end -$var wire 1 9/ outfinal $end -$upscope $end -$scope module mux1 $end -$var wire 1 ?/ S $end -$var wire 1 9/ in0 $end -$var wire 1 4/ in1 $end -$var wire 1 @/ nS $end -$var wire 1 A/ out0 $end -$var wire 1 B/ out1 $end -$var wire 1 8/ outfinal $end -$upscope $end -$upscope $end -$upscope $end -$scope begin orbits[25] $end -$scope module attempt $end -$var wire 1 C/ A $end -$var wire 1 D/ AnandB $end -$var wire 1 E/ AnorB $end -$var wire 1 F/ AorB $end -$var wire 1 G/ AxorB $end -$var wire 1 H/ B $end -$var wire 3 I/ Command [2:0] $end -$var wire 1 J/ OrNorXorOut $end -$var wire 1 K/ XorNor $end -$var wire 1 L/ nXor $end -$scope module mux0 $end -$var wire 1 M/ S $end -$var wire 1 G/ in0 $end -$var wire 1 E/ in1 $end -$var wire 1 N/ nS $end -$var wire 1 O/ out0 $end -$var wire 1 P/ out1 $end -$var wire 1 K/ outfinal $end -$upscope $end -$scope module mux1 $end -$var wire 1 Q/ S $end -$var wire 1 K/ in0 $end -$var wire 1 F/ in1 $end -$var wire 1 R/ nS $end -$var wire 1 S/ out0 $end -$var wire 1 T/ out1 $end -$var wire 1 J/ outfinal $end -$upscope $end -$upscope $end -$upscope $end -$scope begin orbits[26] $end -$scope module attempt $end -$var wire 1 U/ A $end -$var wire 1 V/ AnandB $end -$var wire 1 W/ AnorB $end -$var wire 1 X/ AorB $end -$var wire 1 Y/ AxorB $end -$var wire 1 Z/ B $end -$var wire 3 [/ Command [2:0] $end -$var wire 1 \/ OrNorXorOut $end -$var wire 1 ]/ XorNor $end -$var wire 1 ^/ nXor $end -$scope module mux0 $end -$var wire 1 _/ S $end -$var wire 1 Y/ in0 $end -$var wire 1 W/ in1 $end -$var wire 1 `/ nS $end -$var wire 1 a/ out0 $end -$var wire 1 b/ out1 $end -$var wire 1 ]/ outfinal $end -$upscope $end -$scope module mux1 $end -$var wire 1 c/ S $end -$var wire 1 ]/ in0 $end -$var wire 1 X/ in1 $end -$var wire 1 d/ nS $end -$var wire 1 e/ out0 $end -$var wire 1 f/ out1 $end -$var wire 1 \/ outfinal $end -$upscope $end -$upscope $end -$upscope $end -$scope begin orbits[27] $end -$scope module attempt $end -$var wire 1 g/ A $end -$var wire 1 h/ AnandB $end -$var wire 1 i/ AnorB $end -$var wire 1 j/ AorB $end -$var wire 1 k/ AxorB $end -$var wire 1 l/ B $end -$var wire 3 m/ Command [2:0] $end -$var wire 1 n/ OrNorXorOut $end -$var wire 1 o/ XorNor $end -$var wire 1 p/ nXor $end -$scope module mux0 $end -$var wire 1 q/ S $end -$var wire 1 k/ in0 $end -$var wire 1 i/ in1 $end -$var wire 1 r/ nS $end -$var wire 1 s/ out0 $end -$var wire 1 t/ out1 $end -$var wire 1 o/ outfinal $end -$upscope $end -$scope module mux1 $end -$var wire 1 u/ S $end -$var wire 1 o/ in0 $end -$var wire 1 j/ in1 $end -$var wire 1 v/ nS $end -$var wire 1 w/ out0 $end -$var wire 1 x/ out1 $end -$var wire 1 n/ outfinal $end -$upscope $end -$upscope $end -$upscope $end -$scope begin orbits[28] $end -$scope module attempt $end -$var wire 1 y/ A $end -$var wire 1 z/ AnandB $end -$var wire 1 {/ AnorB $end -$var wire 1 |/ AorB $end -$var wire 1 }/ AxorB $end -$var wire 1 ~/ B $end -$var wire 3 !0 Command [2:0] $end -$var wire 1 "0 OrNorXorOut $end -$var wire 1 #0 XorNor $end -$var wire 1 $0 nXor $end -$scope module mux0 $end -$var wire 1 %0 S $end -$var wire 1 }/ in0 $end -$var wire 1 {/ in1 $end -$var wire 1 &0 nS $end -$var wire 1 '0 out0 $end -$var wire 1 (0 out1 $end -$var wire 1 #0 outfinal $end -$upscope $end -$scope module mux1 $end -$var wire 1 )0 S $end -$var wire 1 #0 in0 $end -$var wire 1 |/ in1 $end -$var wire 1 *0 nS $end -$var wire 1 +0 out0 $end -$var wire 1 ,0 out1 $end -$var wire 1 "0 outfinal $end -$upscope $end -$upscope $end -$upscope $end -$scope begin orbits[29] $end -$scope module attempt $end -$var wire 1 -0 A $end -$var wire 1 .0 AnandB $end -$var wire 1 /0 AnorB $end -$var wire 1 00 AorB $end -$var wire 1 10 AxorB $end -$var wire 1 20 B $end -$var wire 3 30 Command [2:0] $end -$var wire 1 40 OrNorXorOut $end -$var wire 1 50 XorNor $end -$var wire 1 60 nXor $end -$scope module mux0 $end -$var wire 1 70 S $end -$var wire 1 10 in0 $end -$var wire 1 /0 in1 $end -$var wire 1 80 nS $end -$var wire 1 90 out0 $end -$var wire 1 :0 out1 $end -$var wire 1 50 outfinal $end -$upscope $end -$scope module mux1 $end -$var wire 1 ;0 S $end -$var wire 1 50 in0 $end -$var wire 1 00 in1 $end -$var wire 1 <0 nS $end -$var wire 1 =0 out0 $end -$var wire 1 >0 out1 $end -$var wire 1 40 outfinal $end -$upscope $end -$upscope $end -$upscope $end -$scope begin orbits[30] $end -$scope module attempt $end -$var wire 1 ?0 A $end -$var wire 1 @0 AnandB $end -$var wire 1 A0 AnorB $end -$var wire 1 B0 AorB $end -$var wire 1 C0 AxorB $end -$var wire 1 D0 B $end -$var wire 3 E0 Command [2:0] $end -$var wire 1 F0 OrNorXorOut $end -$var wire 1 G0 XorNor $end -$var wire 1 H0 nXor $end -$scope module mux0 $end -$var wire 1 I0 S $end -$var wire 1 C0 in0 $end -$var wire 1 A0 in1 $end -$var wire 1 J0 nS $end -$var wire 1 K0 out0 $end -$var wire 1 L0 out1 $end -$var wire 1 G0 outfinal $end -$upscope $end -$scope module mux1 $end -$var wire 1 M0 S $end -$var wire 1 G0 in0 $end -$var wire 1 B0 in1 $end -$var wire 1 N0 nS $end -$var wire 1 O0 out0 $end -$var wire 1 P0 out1 $end -$var wire 1 F0 outfinal $end -$upscope $end -$upscope $end -$upscope $end -$scope begin orbits[31] $end -$scope module attempt $end -$var wire 1 Q0 A $end -$var wire 1 R0 AnandB $end -$var wire 1 S0 AnorB $end -$var wire 1 T0 AorB $end -$var wire 1 U0 AxorB $end -$var wire 1 V0 B $end -$var wire 3 W0 Command [2:0] $end -$var wire 1 X0 OrNorXorOut $end -$var wire 1 Y0 XorNor $end -$var wire 1 Z0 nXor $end -$scope module mux0 $end -$var wire 1 [0 S $end -$var wire 1 U0 in0 $end -$var wire 1 S0 in1 $end -$var wire 1 \0 nS $end -$var wire 1 ]0 out0 $end -$var wire 1 ^0 out1 $end -$var wire 1 Y0 outfinal $end -$upscope $end -$scope module mux1 $end -$var wire 1 _0 S $end -$var wire 1 Y0 in0 $end -$var wire 1 T0 in1 $end -$var wire 1 `0 nS $end -$var wire 1 a0 out0 $end -$var wire 1 b0 out1 $end -$var wire 1 X0 outfinal $end -$upscope $end -$upscope $end -$upscope $end -$upscope $end -$scope module superalu $end -$var wire 32 c0 A [31:0] $end -$var wire 32 d0 AddSubSLTSum [31:0] $end -$var wire 1 " AllZeros $end -$var wire 32 e0 AndNandOut [31:0] $end -$var wire 32 f0 B [31:0] $end -$var wire 32 g0 Cmd0Start [31:0] $end -$var wire 32 h0 Cmd1Start [31:0] $end -$var wire 3 i0 Command [2:0] $end -$var wire 32 j0 OneBitFinalOut [31:0] $end -$var wire 32 k0 OrNorXorOut [31:0] $end -$var wire 1 & SLTflag $end -$var wire 32 l0 ZeroFlag [31:0] $end -$var wire 32 m0 carryin [31:0] $end -$var wire 1 ( carryout $end -$var wire 1 ) overflow $end -$var wire 32 n0 subtract [31:0] $end -$var wire 1 o0 yeszero $end -$scope module trial $end -$var wire 32 p0 A [31:0] $end -$var wire 32 q0 AddSubSLTSum [31:0] $end -$var wire 32 r0 B [31:0] $end -$var wire 32 s0 CarryoutWire [31:0] $end -$var wire 3 t0 Command [2:0] $end -$var wire 1 u0 Res0OF1 $end -$var wire 1 v0 Res1OF0 $end -$var wire 1 & SLTflag $end -$var wire 1 w0 SLTflag0 $end -$var wire 1 x0 SLTflag1 $end -$var wire 1 y0 SLTon $end -$var wire 32 z0 carryin [31:0] $end -$var wire 1 ( carryout $end -$var wire 1 {0 nAddSubSLTSum $end -$var wire 1 |0 nOF $end -$var wire 1 ) overflow $end -$var wire 32 }0 subtract [31:0] $end -$scope module attempt2 $end -$var wire 1 ~0 A $end -$var wire 1 !1 AandB $end -$var wire 1 "1 AddSubSLTSum $end -$var wire 1 #1 AxorB $end -$var wire 1 $1 B $end -$var wire 1 %1 BornB $end -$var wire 1 &1 CINandAxorB $end -$var wire 3 '1 Command [2:0] $end -$var wire 1 (1 carryin $end -$var wire 1 )1 carryout $end -$var wire 1 *1 nB $end -$var wire 1 +1 nCmd2 $end -$var wire 1 ,1 subtract $end -$scope module mux0 $end -$var wire 1 -1 S $end -$var wire 1 $1 in0 $end -$var wire 1 *1 in1 $end -$var wire 1 .1 nS $end -$var wire 1 /1 out0 $end -$var wire 1 01 out1 $end -$var wire 1 %1 outfinal $end -$upscope $end -$upscope $end -$scope begin addbits[1] $end -$scope module attempt $end -$var wire 1 11 A $end -$var wire 1 21 AandB $end -$var wire 1 31 AddSubSLTSum $end -$var wire 1 41 AxorB $end -$var wire 1 51 B $end -$var wire 1 61 BornB $end -$var wire 1 71 CINandAxorB $end -$var wire 3 81 Command [2:0] $end -$var wire 1 91 carryin $end -$var wire 1 :1 carryout $end -$var wire 1 ;1 nB $end -$var wire 1 <1 nCmd2 $end -$var wire 1 =1 subtract $end -$scope module mux0 $end -$var wire 1 >1 S $end -$var wire 1 51 in0 $end -$var wire 1 ;1 in1 $end -$var wire 1 ?1 nS $end -$var wire 1 @1 out0 $end -$var wire 1 A1 out1 $end -$var wire 1 61 outfinal $end -$upscope $end -$upscope $end -$upscope $end -$scope begin addbits[2] $end -$scope module attempt $end -$var wire 1 B1 A $end -$var wire 1 C1 AandB $end -$var wire 1 D1 AddSubSLTSum $end -$var wire 1 E1 AxorB $end -$var wire 1 F1 B $end -$var wire 1 G1 BornB $end -$var wire 1 H1 CINandAxorB $end -$var wire 3 I1 Command [2:0] $end -$var wire 1 J1 carryin $end -$var wire 1 K1 carryout $end -$var wire 1 L1 nB $end -$var wire 1 M1 nCmd2 $end -$var wire 1 N1 subtract $end -$scope module mux0 $end -$var wire 1 O1 S $end -$var wire 1 F1 in0 $end -$var wire 1 L1 in1 $end -$var wire 1 P1 nS $end -$var wire 1 Q1 out0 $end -$var wire 1 R1 out1 $end -$var wire 1 G1 outfinal $end -$upscope $end -$upscope $end -$upscope $end -$scope begin addbits[3] $end -$scope module attempt $end -$var wire 1 S1 A $end -$var wire 1 T1 AandB $end -$var wire 1 U1 AddSubSLTSum $end -$var wire 1 V1 AxorB $end -$var wire 1 W1 B $end -$var wire 1 X1 BornB $end -$var wire 1 Y1 CINandAxorB $end -$var wire 3 Z1 Command [2:0] $end -$var wire 1 [1 carryin $end -$var wire 1 \1 carryout $end -$var wire 1 ]1 nB $end -$var wire 1 ^1 nCmd2 $end -$var wire 1 _1 subtract $end -$scope module mux0 $end -$var wire 1 `1 S $end -$var wire 1 W1 in0 $end -$var wire 1 ]1 in1 $end -$var wire 1 a1 nS $end -$var wire 1 b1 out0 $end -$var wire 1 c1 out1 $end -$var wire 1 X1 outfinal $end -$upscope $end -$upscope $end -$upscope $end -$scope begin addbits[4] $end -$scope module attempt $end -$var wire 1 d1 A $end -$var wire 1 e1 AandB $end -$var wire 1 f1 AddSubSLTSum $end -$var wire 1 g1 AxorB $end -$var wire 1 h1 B $end -$var wire 1 i1 BornB $end -$var wire 1 j1 CINandAxorB $end -$var wire 3 k1 Command [2:0] $end -$var wire 1 l1 carryin $end -$var wire 1 m1 carryout $end -$var wire 1 n1 nB $end -$var wire 1 o1 nCmd2 $end -$var wire 1 p1 subtract $end -$scope module mux0 $end -$var wire 1 q1 S $end -$var wire 1 h1 in0 $end -$var wire 1 n1 in1 $end -$var wire 1 r1 nS $end -$var wire 1 s1 out0 $end -$var wire 1 t1 out1 $end -$var wire 1 i1 outfinal $end -$upscope $end -$upscope $end -$upscope $end -$scope begin addbits[5] $end -$scope module attempt $end -$var wire 1 u1 A $end -$var wire 1 v1 AandB $end -$var wire 1 w1 AddSubSLTSum $end -$var wire 1 x1 AxorB $end -$var wire 1 y1 B $end -$var wire 1 z1 BornB $end -$var wire 1 {1 CINandAxorB $end -$var wire 3 |1 Command [2:0] $end -$var wire 1 }1 carryin $end -$var wire 1 ~1 carryout $end -$var wire 1 !2 nB $end -$var wire 1 "2 nCmd2 $end -$var wire 1 #2 subtract $end -$scope module mux0 $end -$var wire 1 $2 S $end -$var wire 1 y1 in0 $end -$var wire 1 !2 in1 $end -$var wire 1 %2 nS $end -$var wire 1 &2 out0 $end -$var wire 1 '2 out1 $end -$var wire 1 z1 outfinal $end -$upscope $end -$upscope $end -$upscope $end -$scope begin addbits[6] $end -$scope module attempt $end -$var wire 1 (2 A $end -$var wire 1 )2 AandB $end -$var wire 1 *2 AddSubSLTSum $end -$var wire 1 +2 AxorB $end -$var wire 1 ,2 B $end -$var wire 1 -2 BornB $end -$var wire 1 .2 CINandAxorB $end -$var wire 3 /2 Command [2:0] $end -$var wire 1 02 carryin $end -$var wire 1 12 carryout $end -$var wire 1 22 nB $end -$var wire 1 32 nCmd2 $end -$var wire 1 42 subtract $end -$scope module mux0 $end -$var wire 1 52 S $end -$var wire 1 ,2 in0 $end -$var wire 1 22 in1 $end -$var wire 1 62 nS $end -$var wire 1 72 out0 $end -$var wire 1 82 out1 $end -$var wire 1 -2 outfinal $end -$upscope $end -$upscope $end -$upscope $end -$scope begin addbits[7] $end -$scope module attempt $end -$var wire 1 92 A $end -$var wire 1 :2 AandB $end -$var wire 1 ;2 AddSubSLTSum $end -$var wire 1 <2 AxorB $end -$var wire 1 =2 B $end -$var wire 1 >2 BornB $end -$var wire 1 ?2 CINandAxorB $end -$var wire 3 @2 Command [2:0] $end -$var wire 1 A2 carryin $end -$var wire 1 B2 carryout $end -$var wire 1 C2 nB $end -$var wire 1 D2 nCmd2 $end -$var wire 1 E2 subtract $end -$scope module mux0 $end -$var wire 1 F2 S $end -$var wire 1 =2 in0 $end -$var wire 1 C2 in1 $end -$var wire 1 G2 nS $end -$var wire 1 H2 out0 $end -$var wire 1 I2 out1 $end -$var wire 1 >2 outfinal $end -$upscope $end -$upscope $end -$upscope $end -$scope begin addbits[8] $end -$scope module attempt $end -$var wire 1 J2 A $end -$var wire 1 K2 AandB $end -$var wire 1 L2 AddSubSLTSum $end -$var wire 1 M2 AxorB $end -$var wire 1 N2 B $end -$var wire 1 O2 BornB $end -$var wire 1 P2 CINandAxorB $end -$var wire 3 Q2 Command [2:0] $end -$var wire 1 R2 carryin $end -$var wire 1 S2 carryout $end -$var wire 1 T2 nB $end -$var wire 1 U2 nCmd2 $end -$var wire 1 V2 subtract $end -$scope module mux0 $end -$var wire 1 W2 S $end -$var wire 1 N2 in0 $end -$var wire 1 T2 in1 $end -$var wire 1 X2 nS $end -$var wire 1 Y2 out0 $end -$var wire 1 Z2 out1 $end -$var wire 1 O2 outfinal $end -$upscope $end -$upscope $end -$upscope $end -$scope begin addbits[9] $end -$scope module attempt $end -$var wire 1 [2 A $end -$var wire 1 \2 AandB $end -$var wire 1 ]2 AddSubSLTSum $end -$var wire 1 ^2 AxorB $end -$var wire 1 _2 B $end -$var wire 1 `2 BornB $end -$var wire 1 a2 CINandAxorB $end -$var wire 3 b2 Command [2:0] $end -$var wire 1 c2 carryin $end -$var wire 1 d2 carryout $end -$var wire 1 e2 nB $end -$var wire 1 f2 nCmd2 $end -$var wire 1 g2 subtract $end -$scope module mux0 $end -$var wire 1 h2 S $end -$var wire 1 _2 in0 $end -$var wire 1 e2 in1 $end -$var wire 1 i2 nS $end -$var wire 1 j2 out0 $end -$var wire 1 k2 out1 $end -$var wire 1 `2 outfinal $end -$upscope $end -$upscope $end -$upscope $end -$scope begin addbits[10] $end -$scope module attempt $end -$var wire 1 l2 A $end -$var wire 1 m2 AandB $end -$var wire 1 n2 AddSubSLTSum $end -$var wire 1 o2 AxorB $end -$var wire 1 p2 B $end -$var wire 1 q2 BornB $end -$var wire 1 r2 CINandAxorB $end -$var wire 3 s2 Command [2:0] $end -$var wire 1 t2 carryin $end -$var wire 1 u2 carryout $end -$var wire 1 v2 nB $end -$var wire 1 w2 nCmd2 $end -$var wire 1 x2 subtract $end -$scope module mux0 $end -$var wire 1 y2 S $end -$var wire 1 p2 in0 $end -$var wire 1 v2 in1 $end -$var wire 1 z2 nS $end -$var wire 1 {2 out0 $end -$var wire 1 |2 out1 $end -$var wire 1 q2 outfinal $end -$upscope $end -$upscope $end -$upscope $end -$scope begin addbits[11] $end -$scope module attempt $end -$var wire 1 }2 A $end -$var wire 1 ~2 AandB $end -$var wire 1 !3 AddSubSLTSum $end -$var wire 1 "3 AxorB $end -$var wire 1 #3 B $end -$var wire 1 $3 BornB $end -$var wire 1 %3 CINandAxorB $end -$var wire 3 &3 Command [2:0] $end -$var wire 1 '3 carryin $end -$var wire 1 (3 carryout $end -$var wire 1 )3 nB $end -$var wire 1 *3 nCmd2 $end -$var wire 1 +3 subtract $end -$scope module mux0 $end -$var wire 1 ,3 S $end -$var wire 1 #3 in0 $end -$var wire 1 )3 in1 $end -$var wire 1 -3 nS $end -$var wire 1 .3 out0 $end -$var wire 1 /3 out1 $end -$var wire 1 $3 outfinal $end -$upscope $end -$upscope $end -$upscope $end -$scope begin addbits[12] $end -$scope module attempt $end -$var wire 1 03 A $end -$var wire 1 13 AandB $end -$var wire 1 23 AddSubSLTSum $end -$var wire 1 33 AxorB $end -$var wire 1 43 B $end -$var wire 1 53 BornB $end -$var wire 1 63 CINandAxorB $end -$var wire 3 73 Command [2:0] $end -$var wire 1 83 carryin $end -$var wire 1 93 carryout $end -$var wire 1 :3 nB $end -$var wire 1 ;3 nCmd2 $end -$var wire 1 <3 subtract $end -$scope module mux0 $end -$var wire 1 =3 S $end -$var wire 1 43 in0 $end -$var wire 1 :3 in1 $end -$var wire 1 >3 nS $end -$var wire 1 ?3 out0 $end -$var wire 1 @3 out1 $end -$var wire 1 53 outfinal $end -$upscope $end -$upscope $end -$upscope $end -$scope begin addbits[13] $end -$scope module attempt $end -$var wire 1 A3 A $end -$var wire 1 B3 AandB $end -$var wire 1 C3 AddSubSLTSum $end -$var wire 1 D3 AxorB $end -$var wire 1 E3 B $end -$var wire 1 F3 BornB $end -$var wire 1 G3 CINandAxorB $end -$var wire 3 H3 Command [2:0] $end -$var wire 1 I3 carryin $end -$var wire 1 J3 carryout $end -$var wire 1 K3 nB $end -$var wire 1 L3 nCmd2 $end -$var wire 1 M3 subtract $end -$scope module mux0 $end -$var wire 1 N3 S $end -$var wire 1 E3 in0 $end -$var wire 1 K3 in1 $end -$var wire 1 O3 nS $end -$var wire 1 P3 out0 $end -$var wire 1 Q3 out1 $end -$var wire 1 F3 outfinal $end -$upscope $end -$upscope $end -$upscope $end -$scope begin addbits[14] $end -$scope module attempt $end -$var wire 1 R3 A $end -$var wire 1 S3 AandB $end -$var wire 1 T3 AddSubSLTSum $end -$var wire 1 U3 AxorB $end -$var wire 1 V3 B $end -$var wire 1 W3 BornB $end -$var wire 1 X3 CINandAxorB $end -$var wire 3 Y3 Command [2:0] $end -$var wire 1 Z3 carryin $end -$var wire 1 [3 carryout $end -$var wire 1 \3 nB $end -$var wire 1 ]3 nCmd2 $end -$var wire 1 ^3 subtract $end -$scope module mux0 $end -$var wire 1 _3 S $end -$var wire 1 V3 in0 $end -$var wire 1 \3 in1 $end -$var wire 1 `3 nS $end -$var wire 1 a3 out0 $end -$var wire 1 b3 out1 $end -$var wire 1 W3 outfinal $end -$upscope $end -$upscope $end -$upscope $end -$scope begin addbits[15] $end -$scope module attempt $end -$var wire 1 c3 A $end -$var wire 1 d3 AandB $end -$var wire 1 e3 AddSubSLTSum $end -$var wire 1 f3 AxorB $end -$var wire 1 g3 B $end -$var wire 1 h3 BornB $end -$var wire 1 i3 CINandAxorB $end -$var wire 3 j3 Command [2:0] $end -$var wire 1 k3 carryin $end -$var wire 1 l3 carryout $end -$var wire 1 m3 nB $end -$var wire 1 n3 nCmd2 $end -$var wire 1 o3 subtract $end -$scope module mux0 $end -$var wire 1 p3 S $end -$var wire 1 g3 in0 $end -$var wire 1 m3 in1 $end -$var wire 1 q3 nS $end -$var wire 1 r3 out0 $end -$var wire 1 s3 out1 $end -$var wire 1 h3 outfinal $end -$upscope $end -$upscope $end -$upscope $end -$scope begin addbits[16] $end -$scope module attempt $end -$var wire 1 t3 A $end -$var wire 1 u3 AandB $end -$var wire 1 v3 AddSubSLTSum $end -$var wire 1 w3 AxorB $end -$var wire 1 x3 B $end -$var wire 1 y3 BornB $end -$var wire 1 z3 CINandAxorB $end -$var wire 3 {3 Command [2:0] $end -$var wire 1 |3 carryin $end -$var wire 1 }3 carryout $end -$var wire 1 ~3 nB $end -$var wire 1 !4 nCmd2 $end -$var wire 1 "4 subtract $end -$scope module mux0 $end -$var wire 1 #4 S $end -$var wire 1 x3 in0 $end -$var wire 1 ~3 in1 $end -$var wire 1 $4 nS $end -$var wire 1 %4 out0 $end -$var wire 1 &4 out1 $end -$var wire 1 y3 outfinal $end -$upscope $end -$upscope $end -$upscope $end -$scope begin addbits[17] $end -$scope module attempt $end -$var wire 1 '4 A $end -$var wire 1 (4 AandB $end -$var wire 1 )4 AddSubSLTSum $end -$var wire 1 *4 AxorB $end -$var wire 1 +4 B $end -$var wire 1 ,4 BornB $end -$var wire 1 -4 CINandAxorB $end -$var wire 3 .4 Command [2:0] $end -$var wire 1 /4 carryin $end -$var wire 1 04 carryout $end -$var wire 1 14 nB $end -$var wire 1 24 nCmd2 $end -$var wire 1 34 subtract $end -$scope module mux0 $end -$var wire 1 44 S $end -$var wire 1 +4 in0 $end -$var wire 1 14 in1 $end -$var wire 1 54 nS $end -$var wire 1 64 out0 $end -$var wire 1 74 out1 $end -$var wire 1 ,4 outfinal $end -$upscope $end -$upscope $end -$upscope $end -$scope begin addbits[18] $end -$scope module attempt $end -$var wire 1 84 A $end -$var wire 1 94 AandB $end -$var wire 1 :4 AddSubSLTSum $end -$var wire 1 ;4 AxorB $end -$var wire 1 <4 B $end -$var wire 1 =4 BornB $end -$var wire 1 >4 CINandAxorB $end -$var wire 3 ?4 Command [2:0] $end -$var wire 1 @4 carryin $end -$var wire 1 A4 carryout $end -$var wire 1 B4 nB $end -$var wire 1 C4 nCmd2 $end -$var wire 1 D4 subtract $end -$scope module mux0 $end -$var wire 1 E4 S $end -$var wire 1 <4 in0 $end -$var wire 1 B4 in1 $end -$var wire 1 F4 nS $end -$var wire 1 G4 out0 $end -$var wire 1 H4 out1 $end -$var wire 1 =4 outfinal $end -$upscope $end -$upscope $end -$upscope $end -$scope begin addbits[19] $end -$scope module attempt $end -$var wire 1 I4 A $end -$var wire 1 J4 AandB $end -$var wire 1 K4 AddSubSLTSum $end -$var wire 1 L4 AxorB $end -$var wire 1 M4 B $end -$var wire 1 N4 BornB $end -$var wire 1 O4 CINandAxorB $end -$var wire 3 P4 Command [2:0] $end -$var wire 1 Q4 carryin $end -$var wire 1 R4 carryout $end -$var wire 1 S4 nB $end -$var wire 1 T4 nCmd2 $end -$var wire 1 U4 subtract $end -$scope module mux0 $end -$var wire 1 V4 S $end -$var wire 1 M4 in0 $end -$var wire 1 S4 in1 $end -$var wire 1 W4 nS $end -$var wire 1 X4 out0 $end -$var wire 1 Y4 out1 $end -$var wire 1 N4 outfinal $end -$upscope $end -$upscope $end -$upscope $end -$scope begin addbits[20] $end -$scope module attempt $end -$var wire 1 Z4 A $end -$var wire 1 [4 AandB $end -$var wire 1 \4 AddSubSLTSum $end -$var wire 1 ]4 AxorB $end -$var wire 1 ^4 B $end -$var wire 1 _4 BornB $end -$var wire 1 `4 CINandAxorB $end -$var wire 3 a4 Command [2:0] $end -$var wire 1 b4 carryin $end -$var wire 1 c4 carryout $end -$var wire 1 d4 nB $end -$var wire 1 e4 nCmd2 $end -$var wire 1 f4 subtract $end -$scope module mux0 $end -$var wire 1 g4 S $end -$var wire 1 ^4 in0 $end -$var wire 1 d4 in1 $end -$var wire 1 h4 nS $end -$var wire 1 i4 out0 $end -$var wire 1 j4 out1 $end -$var wire 1 _4 outfinal $end -$upscope $end -$upscope $end -$upscope $end -$scope begin addbits[21] $end -$scope module attempt $end -$var wire 1 k4 A $end -$var wire 1 l4 AandB $end -$var wire 1 m4 AddSubSLTSum $end -$var wire 1 n4 AxorB $end -$var wire 1 o4 B $end -$var wire 1 p4 BornB $end -$var wire 1 q4 CINandAxorB $end -$var wire 3 r4 Command [2:0] $end -$var wire 1 s4 carryin $end -$var wire 1 t4 carryout $end -$var wire 1 u4 nB $end -$var wire 1 v4 nCmd2 $end -$var wire 1 w4 subtract $end -$scope module mux0 $end -$var wire 1 x4 S $end -$var wire 1 o4 in0 $end -$var wire 1 u4 in1 $end -$var wire 1 y4 nS $end -$var wire 1 z4 out0 $end -$var wire 1 {4 out1 $end -$var wire 1 p4 outfinal $end -$upscope $end -$upscope $end -$upscope $end -$scope begin addbits[22] $end -$scope module attempt $end -$var wire 1 |4 A $end -$var wire 1 }4 AandB $end -$var wire 1 ~4 AddSubSLTSum $end -$var wire 1 !5 AxorB $end -$var wire 1 "5 B $end -$var wire 1 #5 BornB $end -$var wire 1 $5 CINandAxorB $end -$var wire 3 %5 Command [2:0] $end -$var wire 1 &5 carryin $end -$var wire 1 '5 carryout $end -$var wire 1 (5 nB $end -$var wire 1 )5 nCmd2 $end -$var wire 1 *5 subtract $end -$scope module mux0 $end -$var wire 1 +5 S $end -$var wire 1 "5 in0 $end -$var wire 1 (5 in1 $end -$var wire 1 ,5 nS $end -$var wire 1 -5 out0 $end -$var wire 1 .5 out1 $end -$var wire 1 #5 outfinal $end -$upscope $end -$upscope $end -$upscope $end -$scope begin addbits[23] $end -$scope module attempt $end -$var wire 1 /5 A $end -$var wire 1 05 AandB $end -$var wire 1 15 AddSubSLTSum $end -$var wire 1 25 AxorB $end -$var wire 1 35 B $end -$var wire 1 45 BornB $end -$var wire 1 55 CINandAxorB $end -$var wire 3 65 Command [2:0] $end -$var wire 1 75 carryin $end -$var wire 1 85 carryout $end -$var wire 1 95 nB $end -$var wire 1 :5 nCmd2 $end -$var wire 1 ;5 subtract $end -$scope module mux0 $end -$var wire 1 <5 S $end -$var wire 1 35 in0 $end -$var wire 1 95 in1 $end -$var wire 1 =5 nS $end -$var wire 1 >5 out0 $end -$var wire 1 ?5 out1 $end -$var wire 1 45 outfinal $end -$upscope $end -$upscope $end -$upscope $end -$scope begin addbits[24] $end -$scope module attempt $end -$var wire 1 @5 A $end -$var wire 1 A5 AandB $end -$var wire 1 B5 AddSubSLTSum $end -$var wire 1 C5 AxorB $end -$var wire 1 D5 B $end -$var wire 1 E5 BornB $end -$var wire 1 F5 CINandAxorB $end -$var wire 3 G5 Command [2:0] $end -$var wire 1 H5 carryin $end -$var wire 1 I5 carryout $end -$var wire 1 J5 nB $end -$var wire 1 K5 nCmd2 $end -$var wire 1 L5 subtract $end -$scope module mux0 $end -$var wire 1 M5 S $end -$var wire 1 D5 in0 $end -$var wire 1 J5 in1 $end -$var wire 1 N5 nS $end -$var wire 1 O5 out0 $end -$var wire 1 P5 out1 $end -$var wire 1 E5 outfinal $end -$upscope $end -$upscope $end -$upscope $end -$scope begin addbits[25] $end -$scope module attempt $end -$var wire 1 Q5 A $end -$var wire 1 R5 AandB $end -$var wire 1 S5 AddSubSLTSum $end -$var wire 1 T5 AxorB $end -$var wire 1 U5 B $end -$var wire 1 V5 BornB $end -$var wire 1 W5 CINandAxorB $end -$var wire 3 X5 Command [2:0] $end -$var wire 1 Y5 carryin $end -$var wire 1 Z5 carryout $end -$var wire 1 [5 nB $end -$var wire 1 \5 nCmd2 $end -$var wire 1 ]5 subtract $end -$scope module mux0 $end -$var wire 1 ^5 S $end -$var wire 1 U5 in0 $end -$var wire 1 [5 in1 $end -$var wire 1 _5 nS $end -$var wire 1 `5 out0 $end -$var wire 1 a5 out1 $end -$var wire 1 V5 outfinal $end -$upscope $end -$upscope $end -$upscope $end -$scope begin addbits[26] $end -$scope module attempt $end -$var wire 1 b5 A $end -$var wire 1 c5 AandB $end -$var wire 1 d5 AddSubSLTSum $end -$var wire 1 e5 AxorB $end -$var wire 1 f5 B $end -$var wire 1 g5 BornB $end -$var wire 1 h5 CINandAxorB $end -$var wire 3 i5 Command [2:0] $end -$var wire 1 j5 carryin $end -$var wire 1 k5 carryout $end -$var wire 1 l5 nB $end -$var wire 1 m5 nCmd2 $end -$var wire 1 n5 subtract $end -$scope module mux0 $end -$var wire 1 o5 S $end -$var wire 1 f5 in0 $end -$var wire 1 l5 in1 $end -$var wire 1 p5 nS $end -$var wire 1 q5 out0 $end -$var wire 1 r5 out1 $end -$var wire 1 g5 outfinal $end -$upscope $end -$upscope $end -$upscope $end -$scope begin addbits[27] $end -$scope module attempt $end -$var wire 1 s5 A $end -$var wire 1 t5 AandB $end -$var wire 1 u5 AddSubSLTSum $end -$var wire 1 v5 AxorB $end -$var wire 1 w5 B $end -$var wire 1 x5 BornB $end -$var wire 1 y5 CINandAxorB $end -$var wire 3 z5 Command [2:0] $end -$var wire 1 {5 carryin $end -$var wire 1 |5 carryout $end -$var wire 1 }5 nB $end -$var wire 1 ~5 nCmd2 $end -$var wire 1 !6 subtract $end -$scope module mux0 $end -$var wire 1 "6 S $end -$var wire 1 w5 in0 $end -$var wire 1 }5 in1 $end -$var wire 1 #6 nS $end -$var wire 1 $6 out0 $end -$var wire 1 %6 out1 $end -$var wire 1 x5 outfinal $end -$upscope $end -$upscope $end -$upscope $end -$scope begin addbits[28] $end -$scope module attempt $end -$var wire 1 &6 A $end -$var wire 1 '6 AandB $end -$var wire 1 (6 AddSubSLTSum $end -$var wire 1 )6 AxorB $end -$var wire 1 *6 B $end -$var wire 1 +6 BornB $end -$var wire 1 ,6 CINandAxorB $end -$var wire 3 -6 Command [2:0] $end -$var wire 1 .6 carryin $end -$var wire 1 /6 carryout $end -$var wire 1 06 nB $end -$var wire 1 16 nCmd2 $end -$var wire 1 26 subtract $end -$scope module mux0 $end -$var wire 1 36 S $end -$var wire 1 *6 in0 $end -$var wire 1 06 in1 $end -$var wire 1 46 nS $end -$var wire 1 56 out0 $end -$var wire 1 66 out1 $end -$var wire 1 +6 outfinal $end -$upscope $end -$upscope $end -$upscope $end -$scope begin addbits[29] $end -$scope module attempt $end -$var wire 1 76 A $end -$var wire 1 86 AandB $end -$var wire 1 96 AddSubSLTSum $end -$var wire 1 :6 AxorB $end -$var wire 1 ;6 B $end -$var wire 1 <6 BornB $end -$var wire 1 =6 CINandAxorB $end -$var wire 3 >6 Command [2:0] $end -$var wire 1 ?6 carryin $end -$var wire 1 @6 carryout $end -$var wire 1 A6 nB $end -$var wire 1 B6 nCmd2 $end -$var wire 1 C6 subtract $end -$scope module mux0 $end -$var wire 1 D6 S $end -$var wire 1 ;6 in0 $end -$var wire 1 A6 in1 $end -$var wire 1 E6 nS $end -$var wire 1 F6 out0 $end -$var wire 1 G6 out1 $end -$var wire 1 <6 outfinal $end -$upscope $end -$upscope $end -$upscope $end -$scope begin addbits[30] $end -$scope module attempt $end -$var wire 1 H6 A $end -$var wire 1 I6 AandB $end -$var wire 1 J6 AddSubSLTSum $end -$var wire 1 K6 AxorB $end -$var wire 1 L6 B $end -$var wire 1 M6 BornB $end -$var wire 1 N6 CINandAxorB $end -$var wire 3 O6 Command [2:0] $end -$var wire 1 P6 carryin $end -$var wire 1 Q6 carryout $end -$var wire 1 R6 nB $end -$var wire 1 S6 nCmd2 $end -$var wire 1 T6 subtract $end -$scope module mux0 $end -$var wire 1 U6 S $end -$var wire 1 L6 in0 $end -$var wire 1 R6 in1 $end -$var wire 1 V6 nS $end -$var wire 1 W6 out0 $end -$var wire 1 X6 out1 $end -$var wire 1 M6 outfinal $end -$upscope $end -$upscope $end -$upscope $end -$scope begin addbits[31] $end -$scope module attempt $end -$var wire 1 Y6 A $end -$var wire 1 Z6 AandB $end -$var wire 1 [6 AddSubSLTSum $end -$var wire 1 \6 AxorB $end -$var wire 1 ]6 B $end -$var wire 1 ^6 BornB $end -$var wire 1 _6 CINandAxorB $end -$var wire 3 `6 Command [2:0] $end -$var wire 1 a6 carryin $end -$var wire 1 b6 carryout $end -$var wire 1 c6 nB $end -$var wire 1 d6 nCmd2 $end -$var wire 1 e6 subtract $end -$scope module mux0 $end -$var wire 1 f6 S $end -$var wire 1 ]6 in0 $end -$var wire 1 c6 in1 $end -$var wire 1 g6 nS $end -$var wire 1 h6 out0 $end -$var wire 1 i6 out1 $end -$var wire 1 ^6 outfinal $end -$upscope $end -$upscope $end -$upscope $end -$upscope $end -$scope module trial1 $end -$var wire 32 j6 A [31:0] $end -$var wire 32 k6 AndNandOut [31:0] $end -$var wire 32 l6 B [31:0] $end -$var wire 3 m6 Command [2:0] $end -$scope module attempt2 $end -$var wire 1 n6 A $end -$var wire 1 o6 AandB $end -$var wire 1 p6 AnandB $end -$var wire 1 q6 AndNandOut $end -$var wire 1 r6 B $end -$var wire 3 s6 Command [2:0] $end -$scope module potato $end -$var wire 1 t6 S $end -$var wire 1 o6 in0 $end -$var wire 1 p6 in1 $end -$var wire 1 u6 nS $end -$var wire 1 v6 out0 $end -$var wire 1 w6 out1 $end -$var wire 1 q6 outfinal $end -$upscope $end -$upscope $end -$scope begin andbits[1] $end -$scope module attempt $end -$var wire 1 x6 A $end -$var wire 1 y6 AandB $end -$var wire 1 z6 AnandB $end -$var wire 1 {6 AndNandOut $end -$var wire 1 |6 B $end -$var wire 3 }6 Command [2:0] $end -$scope module potato $end -$var wire 1 ~6 S $end -$var wire 1 y6 in0 $end -$var wire 1 z6 in1 $end -$var wire 1 !7 nS $end -$var wire 1 "7 out0 $end -$var wire 1 #7 out1 $end -$var wire 1 {6 outfinal $end -$upscope $end -$upscope $end -$upscope $end -$scope begin andbits[2] $end -$scope module attempt $end -$var wire 1 $7 A $end -$var wire 1 %7 AandB $end -$var wire 1 &7 AnandB $end -$var wire 1 '7 AndNandOut $end -$var wire 1 (7 B $end -$var wire 3 )7 Command [2:0] $end -$scope module potato $end -$var wire 1 *7 S $end -$var wire 1 %7 in0 $end -$var wire 1 &7 in1 $end -$var wire 1 +7 nS $end -$var wire 1 ,7 out0 $end -$var wire 1 -7 out1 $end -$var wire 1 '7 outfinal $end -$upscope $end -$upscope $end -$upscope $end -$scope begin andbits[3] $end -$scope module attempt $end -$var wire 1 .7 A $end -$var wire 1 /7 AandB $end -$var wire 1 07 AnandB $end -$var wire 1 17 AndNandOut $end -$var wire 1 27 B $end -$var wire 3 37 Command [2:0] $end -$scope module potato $end -$var wire 1 47 S $end -$var wire 1 /7 in0 $end -$var wire 1 07 in1 $end -$var wire 1 57 nS $end -$var wire 1 67 out0 $end -$var wire 1 77 out1 $end -$var wire 1 17 outfinal $end -$upscope $end -$upscope $end -$upscope $end -$scope begin andbits[4] $end -$scope module attempt $end -$var wire 1 87 A $end -$var wire 1 97 AandB $end -$var wire 1 :7 AnandB $end -$var wire 1 ;7 AndNandOut $end -$var wire 1 <7 B $end -$var wire 3 =7 Command [2:0] $end -$scope module potato $end -$var wire 1 >7 S $end -$var wire 1 97 in0 $end -$var wire 1 :7 in1 $end -$var wire 1 ?7 nS $end -$var wire 1 @7 out0 $end -$var wire 1 A7 out1 $end -$var wire 1 ;7 outfinal $end -$upscope $end -$upscope $end -$upscope $end -$scope begin andbits[5] $end -$scope module attempt $end -$var wire 1 B7 A $end -$var wire 1 C7 AandB $end -$var wire 1 D7 AnandB $end -$var wire 1 E7 AndNandOut $end -$var wire 1 F7 B $end -$var wire 3 G7 Command [2:0] $end -$scope module potato $end -$var wire 1 H7 S $end -$var wire 1 C7 in0 $end -$var wire 1 D7 in1 $end -$var wire 1 I7 nS $end -$var wire 1 J7 out0 $end -$var wire 1 K7 out1 $end -$var wire 1 E7 outfinal $end -$upscope $end -$upscope $end -$upscope $end -$scope begin andbits[6] $end -$scope module attempt $end -$var wire 1 L7 A $end -$var wire 1 M7 AandB $end -$var wire 1 N7 AnandB $end -$var wire 1 O7 AndNandOut $end -$var wire 1 P7 B $end -$var wire 3 Q7 Command [2:0] $end -$scope module potato $end -$var wire 1 R7 S $end -$var wire 1 M7 in0 $end -$var wire 1 N7 in1 $end -$var wire 1 S7 nS $end -$var wire 1 T7 out0 $end -$var wire 1 U7 out1 $end -$var wire 1 O7 outfinal $end -$upscope $end -$upscope $end -$upscope $end -$scope begin andbits[7] $end -$scope module attempt $end -$var wire 1 V7 A $end -$var wire 1 W7 AandB $end -$var wire 1 X7 AnandB $end -$var wire 1 Y7 AndNandOut $end -$var wire 1 Z7 B $end -$var wire 3 [7 Command [2:0] $end -$scope module potato $end -$var wire 1 \7 S $end -$var wire 1 W7 in0 $end -$var wire 1 X7 in1 $end -$var wire 1 ]7 nS $end -$var wire 1 ^7 out0 $end -$var wire 1 _7 out1 $end -$var wire 1 Y7 outfinal $end -$upscope $end -$upscope $end -$upscope $end -$scope begin andbits[8] $end -$scope module attempt $end -$var wire 1 `7 A $end -$var wire 1 a7 AandB $end -$var wire 1 b7 AnandB $end -$var wire 1 c7 AndNandOut $end -$var wire 1 d7 B $end -$var wire 3 e7 Command [2:0] $end -$scope module potato $end -$var wire 1 f7 S $end -$var wire 1 a7 in0 $end -$var wire 1 b7 in1 $end -$var wire 1 g7 nS $end -$var wire 1 h7 out0 $end -$var wire 1 i7 out1 $end -$var wire 1 c7 outfinal $end -$upscope $end -$upscope $end -$upscope $end -$scope begin andbits[9] $end -$scope module attempt $end -$var wire 1 j7 A $end -$var wire 1 k7 AandB $end -$var wire 1 l7 AnandB $end -$var wire 1 m7 AndNandOut $end -$var wire 1 n7 B $end -$var wire 3 o7 Command [2:0] $end -$scope module potato $end -$var wire 1 p7 S $end -$var wire 1 k7 in0 $end -$var wire 1 l7 in1 $end -$var wire 1 q7 nS $end -$var wire 1 r7 out0 $end -$var wire 1 s7 out1 $end -$var wire 1 m7 outfinal $end -$upscope $end -$upscope $end -$upscope $end -$scope begin andbits[10] $end -$scope module attempt $end -$var wire 1 t7 A $end -$var wire 1 u7 AandB $end -$var wire 1 v7 AnandB $end -$var wire 1 w7 AndNandOut $end -$var wire 1 x7 B $end -$var wire 3 y7 Command [2:0] $end -$scope module potato $end -$var wire 1 z7 S $end -$var wire 1 u7 in0 $end -$var wire 1 v7 in1 $end -$var wire 1 {7 nS $end -$var wire 1 |7 out0 $end -$var wire 1 }7 out1 $end -$var wire 1 w7 outfinal $end -$upscope $end -$upscope $end -$upscope $end -$scope begin andbits[11] $end -$scope module attempt $end -$var wire 1 ~7 A $end -$var wire 1 !8 AandB $end -$var wire 1 "8 AnandB $end -$var wire 1 #8 AndNandOut $end -$var wire 1 $8 B $end -$var wire 3 %8 Command [2:0] $end -$scope module potato $end -$var wire 1 &8 S $end -$var wire 1 !8 in0 $end -$var wire 1 "8 in1 $end -$var wire 1 '8 nS $end -$var wire 1 (8 out0 $end -$var wire 1 )8 out1 $end -$var wire 1 #8 outfinal $end -$upscope $end -$upscope $end -$upscope $end -$scope begin andbits[12] $end -$scope module attempt $end -$var wire 1 *8 A $end -$var wire 1 +8 AandB $end -$var wire 1 ,8 AnandB $end -$var wire 1 -8 AndNandOut $end -$var wire 1 .8 B $end -$var wire 3 /8 Command [2:0] $end -$scope module potato $end -$var wire 1 08 S $end -$var wire 1 +8 in0 $end -$var wire 1 ,8 in1 $end -$var wire 1 18 nS $end -$var wire 1 28 out0 $end -$var wire 1 38 out1 $end -$var wire 1 -8 outfinal $end -$upscope $end -$upscope $end -$upscope $end -$scope begin andbits[13] $end -$scope module attempt $end -$var wire 1 48 A $end -$var wire 1 58 AandB $end -$var wire 1 68 AnandB $end -$var wire 1 78 AndNandOut $end -$var wire 1 88 B $end -$var wire 3 98 Command [2:0] $end -$scope module potato $end -$var wire 1 :8 S $end -$var wire 1 58 in0 $end -$var wire 1 68 in1 $end -$var wire 1 ;8 nS $end -$var wire 1 <8 out0 $end -$var wire 1 =8 out1 $end -$var wire 1 78 outfinal $end -$upscope $end -$upscope $end -$upscope $end -$scope begin andbits[14] $end -$scope module attempt $end -$var wire 1 >8 A $end -$var wire 1 ?8 AandB $end -$var wire 1 @8 AnandB $end -$var wire 1 A8 AndNandOut $end -$var wire 1 B8 B $end -$var wire 3 C8 Command [2:0] $end -$scope module potato $end -$var wire 1 D8 S $end -$var wire 1 ?8 in0 $end -$var wire 1 @8 in1 $end -$var wire 1 E8 nS $end -$var wire 1 F8 out0 $end -$var wire 1 G8 out1 $end -$var wire 1 A8 outfinal $end -$upscope $end -$upscope $end -$upscope $end -$scope begin andbits[15] $end -$scope module attempt $end -$var wire 1 H8 A $end -$var wire 1 I8 AandB $end -$var wire 1 J8 AnandB $end -$var wire 1 K8 AndNandOut $end -$var wire 1 L8 B $end -$var wire 3 M8 Command [2:0] $end -$scope module potato $end -$var wire 1 N8 S $end -$var wire 1 I8 in0 $end -$var wire 1 J8 in1 $end -$var wire 1 O8 nS $end -$var wire 1 P8 out0 $end -$var wire 1 Q8 out1 $end -$var wire 1 K8 outfinal $end -$upscope $end -$upscope $end -$upscope $end -$scope begin andbits[16] $end -$scope module attempt $end -$var wire 1 R8 A $end -$var wire 1 S8 AandB $end -$var wire 1 T8 AnandB $end -$var wire 1 U8 AndNandOut $end -$var wire 1 V8 B $end -$var wire 3 W8 Command [2:0] $end -$scope module potato $end -$var wire 1 X8 S $end -$var wire 1 S8 in0 $end -$var wire 1 T8 in1 $end -$var wire 1 Y8 nS $end -$var wire 1 Z8 out0 $end -$var wire 1 [8 out1 $end -$var wire 1 U8 outfinal $end -$upscope $end -$upscope $end -$upscope $end -$scope begin andbits[17] $end -$scope module attempt $end -$var wire 1 \8 A $end -$var wire 1 ]8 AandB $end -$var wire 1 ^8 AnandB $end -$var wire 1 _8 AndNandOut $end -$var wire 1 `8 B $end -$var wire 3 a8 Command [2:0] $end -$scope module potato $end -$var wire 1 b8 S $end -$var wire 1 ]8 in0 $end -$var wire 1 ^8 in1 $end -$var wire 1 c8 nS $end -$var wire 1 d8 out0 $end -$var wire 1 e8 out1 $end -$var wire 1 _8 outfinal $end -$upscope $end -$upscope $end -$upscope $end -$scope begin andbits[18] $end -$scope module attempt $end -$var wire 1 f8 A $end -$var wire 1 g8 AandB $end -$var wire 1 h8 AnandB $end -$var wire 1 i8 AndNandOut $end -$var wire 1 j8 B $end -$var wire 3 k8 Command [2:0] $end -$scope module potato $end -$var wire 1 l8 S $end -$var wire 1 g8 in0 $end -$var wire 1 h8 in1 $end -$var wire 1 m8 nS $end -$var wire 1 n8 out0 $end -$var wire 1 o8 out1 $end -$var wire 1 i8 outfinal $end -$upscope $end -$upscope $end -$upscope $end -$scope begin andbits[19] $end -$scope module attempt $end -$var wire 1 p8 A $end -$var wire 1 q8 AandB $end -$var wire 1 r8 AnandB $end -$var wire 1 s8 AndNandOut $end -$var wire 1 t8 B $end -$var wire 3 u8 Command [2:0] $end -$scope module potato $end -$var wire 1 v8 S $end -$var wire 1 q8 in0 $end -$var wire 1 r8 in1 $end -$var wire 1 w8 nS $end -$var wire 1 x8 out0 $end -$var wire 1 y8 out1 $end -$var wire 1 s8 outfinal $end -$upscope $end -$upscope $end -$upscope $end -$scope begin andbits[20] $end -$scope module attempt $end -$var wire 1 z8 A $end -$var wire 1 {8 AandB $end -$var wire 1 |8 AnandB $end -$var wire 1 }8 AndNandOut $end -$var wire 1 ~8 B $end -$var wire 3 !9 Command [2:0] $end -$scope module potato $end -$var wire 1 "9 S $end -$var wire 1 {8 in0 $end -$var wire 1 |8 in1 $end -$var wire 1 #9 nS $end -$var wire 1 $9 out0 $end -$var wire 1 %9 out1 $end -$var wire 1 }8 outfinal $end -$upscope $end -$upscope $end -$upscope $end -$scope begin andbits[21] $end -$scope module attempt $end -$var wire 1 &9 A $end -$var wire 1 '9 AandB $end -$var wire 1 (9 AnandB $end -$var wire 1 )9 AndNandOut $end -$var wire 1 *9 B $end -$var wire 3 +9 Command [2:0] $end -$scope module potato $end -$var wire 1 ,9 S $end -$var wire 1 '9 in0 $end -$var wire 1 (9 in1 $end -$var wire 1 -9 nS $end -$var wire 1 .9 out0 $end -$var wire 1 /9 out1 $end -$var wire 1 )9 outfinal $end -$upscope $end -$upscope $end -$upscope $end -$scope begin andbits[22] $end -$scope module attempt $end -$var wire 1 09 A $end -$var wire 1 19 AandB $end -$var wire 1 29 AnandB $end -$var wire 1 39 AndNandOut $end -$var wire 1 49 B $end -$var wire 3 59 Command [2:0] $end -$scope module potato $end -$var wire 1 69 S $end -$var wire 1 19 in0 $end -$var wire 1 29 in1 $end -$var wire 1 79 nS $end -$var wire 1 89 out0 $end -$var wire 1 99 out1 $end -$var wire 1 39 outfinal $end -$upscope $end -$upscope $end -$upscope $end -$scope begin andbits[23] $end -$scope module attempt $end -$var wire 1 :9 A $end -$var wire 1 ;9 AandB $end -$var wire 1 <9 AnandB $end -$var wire 1 =9 AndNandOut $end -$var wire 1 >9 B $end -$var wire 3 ?9 Command [2:0] $end -$scope module potato $end -$var wire 1 @9 S $end -$var wire 1 ;9 in0 $end -$var wire 1 <9 in1 $end -$var wire 1 A9 nS $end -$var wire 1 B9 out0 $end -$var wire 1 C9 out1 $end -$var wire 1 =9 outfinal $end -$upscope $end -$upscope $end -$upscope $end -$scope begin andbits[24] $end -$scope module attempt $end -$var wire 1 D9 A $end -$var wire 1 E9 AandB $end -$var wire 1 F9 AnandB $end -$var wire 1 G9 AndNandOut $end -$var wire 1 H9 B $end -$var wire 3 I9 Command [2:0] $end -$scope module potato $end -$var wire 1 J9 S $end -$var wire 1 E9 in0 $end -$var wire 1 F9 in1 $end -$var wire 1 K9 nS $end -$var wire 1 L9 out0 $end -$var wire 1 M9 out1 $end -$var wire 1 G9 outfinal $end -$upscope $end -$upscope $end -$upscope $end -$scope begin andbits[25] $end -$scope module attempt $end -$var wire 1 N9 A $end -$var wire 1 O9 AandB $end -$var wire 1 P9 AnandB $end -$var wire 1 Q9 AndNandOut $end -$var wire 1 R9 B $end -$var wire 3 S9 Command [2:0] $end -$scope module potato $end -$var wire 1 T9 S $end -$var wire 1 O9 in0 $end -$var wire 1 P9 in1 $end -$var wire 1 U9 nS $end -$var wire 1 V9 out0 $end -$var wire 1 W9 out1 $end -$var wire 1 Q9 outfinal $end -$upscope $end -$upscope $end -$upscope $end -$scope begin andbits[26] $end -$scope module attempt $end -$var wire 1 X9 A $end -$var wire 1 Y9 AandB $end -$var wire 1 Z9 AnandB $end -$var wire 1 [9 AndNandOut $end -$var wire 1 \9 B $end -$var wire 3 ]9 Command [2:0] $end -$scope module potato $end -$var wire 1 ^9 S $end -$var wire 1 Y9 in0 $end -$var wire 1 Z9 in1 $end -$var wire 1 _9 nS $end -$var wire 1 `9 out0 $end -$var wire 1 a9 out1 $end -$var wire 1 [9 outfinal $end -$upscope $end -$upscope $end -$upscope $end -$scope begin andbits[27] $end -$scope module attempt $end -$var wire 1 b9 A $end -$var wire 1 c9 AandB $end -$var wire 1 d9 AnandB $end -$var wire 1 e9 AndNandOut $end -$var wire 1 f9 B $end -$var wire 3 g9 Command [2:0] $end -$scope module potato $end -$var wire 1 h9 S $end -$var wire 1 c9 in0 $end -$var wire 1 d9 in1 $end -$var wire 1 i9 nS $end -$var wire 1 j9 out0 $end -$var wire 1 k9 out1 $end -$var wire 1 e9 outfinal $end -$upscope $end -$upscope $end -$upscope $end -$scope begin andbits[28] $end -$scope module attempt $end -$var wire 1 l9 A $end -$var wire 1 m9 AandB $end -$var wire 1 n9 AnandB $end -$var wire 1 o9 AndNandOut $end -$var wire 1 p9 B $end -$var wire 3 q9 Command [2:0] $end -$scope module potato $end -$var wire 1 r9 S $end -$var wire 1 m9 in0 $end -$var wire 1 n9 in1 $end -$var wire 1 s9 nS $end -$var wire 1 t9 out0 $end -$var wire 1 u9 out1 $end -$var wire 1 o9 outfinal $end -$upscope $end -$upscope $end -$upscope $end -$scope begin andbits[29] $end -$scope module attempt $end -$var wire 1 v9 A $end -$var wire 1 w9 AandB $end -$var wire 1 x9 AnandB $end -$var wire 1 y9 AndNandOut $end -$var wire 1 z9 B $end -$var wire 3 {9 Command [2:0] $end -$scope module potato $end -$var wire 1 |9 S $end -$var wire 1 w9 in0 $end -$var wire 1 x9 in1 $end -$var wire 1 }9 nS $end -$var wire 1 ~9 out0 $end -$var wire 1 !: out1 $end -$var wire 1 y9 outfinal $end -$upscope $end -$upscope $end -$upscope $end -$scope begin andbits[30] $end -$scope module attempt $end -$var wire 1 ": A $end -$var wire 1 #: AandB $end -$var wire 1 $: AnandB $end -$var wire 1 %: AndNandOut $end -$var wire 1 &: B $end -$var wire 3 ': Command [2:0] $end -$scope module potato $end -$var wire 1 (: S $end -$var wire 1 #: in0 $end -$var wire 1 $: in1 $end -$var wire 1 ): nS $end -$var wire 1 *: out0 $end -$var wire 1 +: out1 $end -$var wire 1 %: outfinal $end -$upscope $end -$upscope $end -$upscope $end -$scope begin andbits[31] $end -$scope module attempt $end -$var wire 1 ,: A $end -$var wire 1 -: AandB $end -$var wire 1 .: AnandB $end -$var wire 1 /: AndNandOut $end -$var wire 1 0: B $end -$var wire 3 1: Command [2:0] $end -$scope module potato $end -$var wire 1 2: S $end -$var wire 1 -: in0 $end -$var wire 1 .: in1 $end -$var wire 1 3: nS $end -$var wire 1 4: out0 $end -$var wire 1 5: out1 $end -$var wire 1 /: outfinal $end -$upscope $end -$upscope $end -$upscope $end -$upscope $end -$scope module trial2 $end -$var wire 32 6: A [31:0] $end -$var wire 32 7: B [31:0] $end -$var wire 3 8: Command [2:0] $end -$var wire 32 9: OrNorXorOut [31:0] $end -$scope module attempt2 $end -$var wire 1 :: A $end -$var wire 1 ;: AnandB $end -$var wire 1 <: AnorB $end -$var wire 1 =: AorB $end -$var wire 1 >: AxorB $end -$var wire 1 ?: B $end -$var wire 3 @: Command [2:0] $end -$var wire 1 A: OrNorXorOut $end -$var wire 1 B: XorNor $end -$var wire 1 C: nXor $end -$scope module mux0 $end -$var wire 1 D: S $end -$var wire 1 >: in0 $end -$var wire 1 <: in1 $end -$var wire 1 E: nS $end -$var wire 1 F: out0 $end -$var wire 1 G: out1 $end -$var wire 1 B: outfinal $end -$upscope $end -$scope module mux1 $end -$var wire 1 H: S $end -$var wire 1 B: in0 $end -$var wire 1 =: in1 $end -$var wire 1 I: nS $end -$var wire 1 J: out0 $end -$var wire 1 K: out1 $end -$var wire 1 A: outfinal $end -$upscope $end -$upscope $end -$scope begin orbits[1] $end -$scope module attempt $end -$var wire 1 L: A $end -$var wire 1 M: AnandB $end -$var wire 1 N: AnorB $end -$var wire 1 O: AorB $end -$var wire 1 P: AxorB $end -$var wire 1 Q: B $end -$var wire 3 R: Command [2:0] $end -$var wire 1 S: OrNorXorOut $end -$var wire 1 T: XorNor $end -$var wire 1 U: nXor $end -$scope module mux0 $end -$var wire 1 V: S $end -$var wire 1 P: in0 $end -$var wire 1 N: in1 $end -$var wire 1 W: nS $end -$var wire 1 X: out0 $end -$var wire 1 Y: out1 $end -$var wire 1 T: outfinal $end -$upscope $end -$scope module mux1 $end -$var wire 1 Z: S $end -$var wire 1 T: in0 $end -$var wire 1 O: in1 $end -$var wire 1 [: nS $end -$var wire 1 \: out0 $end -$var wire 1 ]: out1 $end -$var wire 1 S: outfinal $end -$upscope $end -$upscope $end -$upscope $end -$scope begin orbits[2] $end -$scope module attempt $end -$var wire 1 ^: A $end -$var wire 1 _: AnandB $end -$var wire 1 `: AnorB $end -$var wire 1 a: AorB $end -$var wire 1 b: AxorB $end -$var wire 1 c: B $end -$var wire 3 d: Command [2:0] $end -$var wire 1 e: OrNorXorOut $end -$var wire 1 f: XorNor $end -$var wire 1 g: nXor $end -$scope module mux0 $end -$var wire 1 h: S $end -$var wire 1 b: in0 $end -$var wire 1 `: in1 $end -$var wire 1 i: nS $end -$var wire 1 j: out0 $end -$var wire 1 k: out1 $end -$var wire 1 f: outfinal $end -$upscope $end -$scope module mux1 $end -$var wire 1 l: S $end -$var wire 1 f: in0 $end -$var wire 1 a: in1 $end -$var wire 1 m: nS $end -$var wire 1 n: out0 $end -$var wire 1 o: out1 $end -$var wire 1 e: outfinal $end -$upscope $end -$upscope $end -$upscope $end -$scope begin orbits[3] $end -$scope module attempt $end -$var wire 1 p: A $end -$var wire 1 q: AnandB $end -$var wire 1 r: AnorB $end -$var wire 1 s: AorB $end -$var wire 1 t: AxorB $end -$var wire 1 u: B $end -$var wire 3 v: Command [2:0] $end -$var wire 1 w: OrNorXorOut $end -$var wire 1 x: XorNor $end -$var wire 1 y: nXor $end -$scope module mux0 $end -$var wire 1 z: S $end -$var wire 1 t: in0 $end -$var wire 1 r: in1 $end -$var wire 1 {: nS $end -$var wire 1 |: out0 $end -$var wire 1 }: out1 $end -$var wire 1 x: outfinal $end -$upscope $end -$scope module mux1 $end -$var wire 1 ~: S $end -$var wire 1 x: in0 $end -$var wire 1 s: in1 $end -$var wire 1 !; nS $end -$var wire 1 "; out0 $end -$var wire 1 #; out1 $end -$var wire 1 w: outfinal $end -$upscope $end -$upscope $end -$upscope $end -$scope begin orbits[4] $end -$scope module attempt $end -$var wire 1 $; A $end -$var wire 1 %; AnandB $end -$var wire 1 &; AnorB $end -$var wire 1 '; AorB $end -$var wire 1 (; AxorB $end -$var wire 1 ); B $end -$var wire 3 *; Command [2:0] $end -$var wire 1 +; OrNorXorOut $end -$var wire 1 ,; XorNor $end -$var wire 1 -; nXor $end -$scope module mux0 $end -$var wire 1 .; S $end -$var wire 1 (; in0 $end -$var wire 1 &; in1 $end -$var wire 1 /; nS $end -$var wire 1 0; out0 $end -$var wire 1 1; out1 $end -$var wire 1 ,; outfinal $end -$upscope $end -$scope module mux1 $end -$var wire 1 2; S $end -$var wire 1 ,; in0 $end -$var wire 1 '; in1 $end -$var wire 1 3; nS $end -$var wire 1 4; out0 $end -$var wire 1 5; out1 $end -$var wire 1 +; outfinal $end -$upscope $end -$upscope $end -$upscope $end -$scope begin orbits[5] $end -$scope module attempt $end -$var wire 1 6; A $end -$var wire 1 7; AnandB $end -$var wire 1 8; AnorB $end -$var wire 1 9; AorB $end -$var wire 1 :; AxorB $end -$var wire 1 ;; B $end -$var wire 3 <; Command [2:0] $end -$var wire 1 =; OrNorXorOut $end -$var wire 1 >; XorNor $end -$var wire 1 ?; nXor $end -$scope module mux0 $end -$var wire 1 @; S $end -$var wire 1 :; in0 $end -$var wire 1 8; in1 $end -$var wire 1 A; nS $end -$var wire 1 B; out0 $end -$var wire 1 C; out1 $end -$var wire 1 >; outfinal $end -$upscope $end -$scope module mux1 $end -$var wire 1 D; S $end -$var wire 1 >; in0 $end -$var wire 1 9; in1 $end -$var wire 1 E; nS $end -$var wire 1 F; out0 $end -$var wire 1 G; out1 $end -$var wire 1 =; outfinal $end -$upscope $end -$upscope $end -$upscope $end -$scope begin orbits[6] $end -$scope module attempt $end -$var wire 1 H; A $end -$var wire 1 I; AnandB $end -$var wire 1 J; AnorB $end -$var wire 1 K; AorB $end -$var wire 1 L; AxorB $end -$var wire 1 M; B $end -$var wire 3 N; Command [2:0] $end -$var wire 1 O; OrNorXorOut $end -$var wire 1 P; XorNor $end -$var wire 1 Q; nXor $end -$scope module mux0 $end -$var wire 1 R; S $end -$var wire 1 L; in0 $end -$var wire 1 J; in1 $end -$var wire 1 S; nS $end -$var wire 1 T; out0 $end -$var wire 1 U; out1 $end -$var wire 1 P; outfinal $end -$upscope $end -$scope module mux1 $end -$var wire 1 V; S $end -$var wire 1 P; in0 $end -$var wire 1 K; in1 $end -$var wire 1 W; nS $end -$var wire 1 X; out0 $end -$var wire 1 Y; out1 $end -$var wire 1 O; outfinal $end -$upscope $end -$upscope $end -$upscope $end -$scope begin orbits[7] $end -$scope module attempt $end -$var wire 1 Z; A $end -$var wire 1 [; AnandB $end -$var wire 1 \; AnorB $end -$var wire 1 ]; AorB $end -$var wire 1 ^; AxorB $end -$var wire 1 _; B $end -$var wire 3 `; Command [2:0] $end -$var wire 1 a; OrNorXorOut $end -$var wire 1 b; XorNor $end -$var wire 1 c; nXor $end -$scope module mux0 $end -$var wire 1 d; S $end -$var wire 1 ^; in0 $end -$var wire 1 \; in1 $end -$var wire 1 e; nS $end -$var wire 1 f; out0 $end -$var wire 1 g; out1 $end -$var wire 1 b; outfinal $end -$upscope $end -$scope module mux1 $end -$var wire 1 h; S $end -$var wire 1 b; in0 $end -$var wire 1 ]; in1 $end -$var wire 1 i; nS $end -$var wire 1 j; out0 $end -$var wire 1 k; out1 $end -$var wire 1 a; outfinal $end -$upscope $end -$upscope $end -$upscope $end -$scope begin orbits[8] $end -$scope module attempt $end -$var wire 1 l; A $end -$var wire 1 m; AnandB $end -$var wire 1 n; AnorB $end -$var wire 1 o; AorB $end -$var wire 1 p; AxorB $end -$var wire 1 q; B $end -$var wire 3 r; Command [2:0] $end -$var wire 1 s; OrNorXorOut $end -$var wire 1 t; XorNor $end -$var wire 1 u; nXor $end -$scope module mux0 $end -$var wire 1 v; S $end -$var wire 1 p; in0 $end -$var wire 1 n; in1 $end -$var wire 1 w; nS $end -$var wire 1 x; out0 $end -$var wire 1 y; out1 $end -$var wire 1 t; outfinal $end -$upscope $end -$scope module mux1 $end -$var wire 1 z; S $end -$var wire 1 t; in0 $end -$var wire 1 o; in1 $end -$var wire 1 {; nS $end -$var wire 1 |; out0 $end -$var wire 1 }; out1 $end -$var wire 1 s; outfinal $end -$upscope $end -$upscope $end -$upscope $end -$scope begin orbits[9] $end -$scope module attempt $end -$var wire 1 ~; A $end -$var wire 1 !< AnandB $end -$var wire 1 "< AnorB $end -$var wire 1 #< AorB $end -$var wire 1 $< AxorB $end -$var wire 1 %< B $end -$var wire 3 &< Command [2:0] $end -$var wire 1 '< OrNorXorOut $end -$var wire 1 (< XorNor $end -$var wire 1 )< nXor $end -$scope module mux0 $end -$var wire 1 *< S $end -$var wire 1 $< in0 $end -$var wire 1 "< in1 $end -$var wire 1 +< nS $end -$var wire 1 ,< out0 $end -$var wire 1 -< out1 $end -$var wire 1 (< outfinal $end -$upscope $end -$scope module mux1 $end -$var wire 1 .< S $end -$var wire 1 (< in0 $end -$var wire 1 #< in1 $end -$var wire 1 /< nS $end -$var wire 1 0< out0 $end -$var wire 1 1< out1 $end -$var wire 1 '< outfinal $end -$upscope $end -$upscope $end -$upscope $end -$scope begin orbits[10] $end -$scope module attempt $end -$var wire 1 2< A $end -$var wire 1 3< AnandB $end -$var wire 1 4< AnorB $end -$var wire 1 5< AorB $end -$var wire 1 6< AxorB $end -$var wire 1 7< B $end -$var wire 3 8< Command [2:0] $end -$var wire 1 9< OrNorXorOut $end -$var wire 1 :< XorNor $end -$var wire 1 ;< nXor $end -$scope module mux0 $end -$var wire 1 << S $end -$var wire 1 6< in0 $end -$var wire 1 4< in1 $end -$var wire 1 =< nS $end -$var wire 1 >< out0 $end -$var wire 1 ?< out1 $end -$var wire 1 :< outfinal $end -$upscope $end -$scope module mux1 $end -$var wire 1 @< S $end -$var wire 1 :< in0 $end -$var wire 1 5< in1 $end -$var wire 1 A< nS $end -$var wire 1 B< out0 $end -$var wire 1 C< out1 $end -$var wire 1 9< outfinal $end -$upscope $end -$upscope $end -$upscope $end -$scope begin orbits[11] $end -$scope module attempt $end -$var wire 1 D< A $end -$var wire 1 E< AnandB $end -$var wire 1 F< AnorB $end -$var wire 1 G< AorB $end -$var wire 1 H< AxorB $end -$var wire 1 I< B $end -$var wire 3 J< Command [2:0] $end -$var wire 1 K< OrNorXorOut $end -$var wire 1 L< XorNor $end -$var wire 1 M< nXor $end -$scope module mux0 $end -$var wire 1 N< S $end -$var wire 1 H< in0 $end -$var wire 1 F< in1 $end -$var wire 1 O< nS $end -$var wire 1 P< out0 $end -$var wire 1 Q< out1 $end -$var wire 1 L< outfinal $end -$upscope $end -$scope module mux1 $end -$var wire 1 R< S $end -$var wire 1 L< in0 $end -$var wire 1 G< in1 $end -$var wire 1 S< nS $end -$var wire 1 T< out0 $end -$var wire 1 U< out1 $end -$var wire 1 K< outfinal $end -$upscope $end -$upscope $end -$upscope $end -$scope begin orbits[12] $end -$scope module attempt $end -$var wire 1 V< A $end -$var wire 1 W< AnandB $end -$var wire 1 X< AnorB $end -$var wire 1 Y< AorB $end -$var wire 1 Z< AxorB $end -$var wire 1 [< B $end -$var wire 3 \< Command [2:0] $end -$var wire 1 ]< OrNorXorOut $end -$var wire 1 ^< XorNor $end -$var wire 1 _< nXor $end -$scope module mux0 $end -$var wire 1 `< S $end -$var wire 1 Z< in0 $end -$var wire 1 X< in1 $end -$var wire 1 a< nS $end -$var wire 1 b< out0 $end -$var wire 1 c< out1 $end -$var wire 1 ^< outfinal $end -$upscope $end -$scope module mux1 $end -$var wire 1 d< S $end -$var wire 1 ^< in0 $end -$var wire 1 Y< in1 $end -$var wire 1 e< nS $end -$var wire 1 f< out0 $end -$var wire 1 g< out1 $end -$var wire 1 ]< outfinal $end -$upscope $end -$upscope $end -$upscope $end -$scope begin orbits[13] $end -$scope module attempt $end -$var wire 1 h< A $end -$var wire 1 i< AnandB $end -$var wire 1 j< AnorB $end -$var wire 1 k< AorB $end -$var wire 1 l< AxorB $end -$var wire 1 m< B $end -$var wire 3 n< Command [2:0] $end -$var wire 1 o< OrNorXorOut $end -$var wire 1 p< XorNor $end -$var wire 1 q< nXor $end -$scope module mux0 $end -$var wire 1 r< S $end -$var wire 1 l< in0 $end -$var wire 1 j< in1 $end -$var wire 1 s< nS $end -$var wire 1 t< out0 $end -$var wire 1 u< out1 $end -$var wire 1 p< outfinal $end -$upscope $end -$scope module mux1 $end -$var wire 1 v< S $end -$var wire 1 p< in0 $end -$var wire 1 k< in1 $end -$var wire 1 w< nS $end -$var wire 1 x< out0 $end -$var wire 1 y< out1 $end -$var wire 1 o< outfinal $end -$upscope $end -$upscope $end -$upscope $end -$scope begin orbits[14] $end -$scope module attempt $end -$var wire 1 z< A $end -$var wire 1 {< AnandB $end -$var wire 1 |< AnorB $end -$var wire 1 }< AorB $end -$var wire 1 ~< AxorB $end -$var wire 1 != B $end -$var wire 3 "= Command [2:0] $end -$var wire 1 #= OrNorXorOut $end -$var wire 1 $= XorNor $end -$var wire 1 %= nXor $end -$scope module mux0 $end -$var wire 1 &= S $end -$var wire 1 ~< in0 $end -$var wire 1 |< in1 $end -$var wire 1 '= nS $end -$var wire 1 (= out0 $end -$var wire 1 )= out1 $end -$var wire 1 $= outfinal $end -$upscope $end -$scope module mux1 $end -$var wire 1 *= S $end -$var wire 1 $= in0 $end -$var wire 1 }< in1 $end -$var wire 1 += nS $end -$var wire 1 ,= out0 $end -$var wire 1 -= out1 $end -$var wire 1 #= outfinal $end -$upscope $end -$upscope $end -$upscope $end -$scope begin orbits[15] $end -$scope module attempt $end -$var wire 1 .= A $end -$var wire 1 /= AnandB $end -$var wire 1 0= AnorB $end -$var wire 1 1= AorB $end -$var wire 1 2= AxorB $end -$var wire 1 3= B $end -$var wire 3 4= Command [2:0] $end -$var wire 1 5= OrNorXorOut $end -$var wire 1 6= XorNor $end -$var wire 1 7= nXor $end -$scope module mux0 $end -$var wire 1 8= S $end -$var wire 1 2= in0 $end -$var wire 1 0= in1 $end -$var wire 1 9= nS $end -$var wire 1 := out0 $end -$var wire 1 ;= out1 $end -$var wire 1 6= outfinal $end -$upscope $end -$scope module mux1 $end -$var wire 1 <= S $end -$var wire 1 6= in0 $end -$var wire 1 1= in1 $end -$var wire 1 == nS $end -$var wire 1 >= out0 $end -$var wire 1 ?= out1 $end -$var wire 1 5= outfinal $end -$upscope $end -$upscope $end -$upscope $end -$scope begin orbits[16] $end -$scope module attempt $end -$var wire 1 @= A $end -$var wire 1 A= AnandB $end -$var wire 1 B= AnorB $end -$var wire 1 C= AorB $end -$var wire 1 D= AxorB $end -$var wire 1 E= B $end -$var wire 3 F= Command [2:0] $end -$var wire 1 G= OrNorXorOut $end -$var wire 1 H= XorNor $end -$var wire 1 I= nXor $end -$scope module mux0 $end -$var wire 1 J= S $end -$var wire 1 D= in0 $end -$var wire 1 B= in1 $end -$var wire 1 K= nS $end -$var wire 1 L= out0 $end -$var wire 1 M= out1 $end -$var wire 1 H= outfinal $end -$upscope $end -$scope module mux1 $end -$var wire 1 N= S $end -$var wire 1 H= in0 $end -$var wire 1 C= in1 $end -$var wire 1 O= nS $end -$var wire 1 P= out0 $end -$var wire 1 Q= out1 $end -$var wire 1 G= outfinal $end -$upscope $end -$upscope $end -$upscope $end -$scope begin orbits[17] $end -$scope module attempt $end -$var wire 1 R= A $end -$var wire 1 S= AnandB $end -$var wire 1 T= AnorB $end -$var wire 1 U= AorB $end -$var wire 1 V= AxorB $end -$var wire 1 W= B $end -$var wire 3 X= Command [2:0] $end -$var wire 1 Y= OrNorXorOut $end -$var wire 1 Z= XorNor $end -$var wire 1 [= nXor $end -$scope module mux0 $end -$var wire 1 \= S $end -$var wire 1 V= in0 $end -$var wire 1 T= in1 $end -$var wire 1 ]= nS $end -$var wire 1 ^= out0 $end -$var wire 1 _= out1 $end -$var wire 1 Z= outfinal $end -$upscope $end -$scope module mux1 $end -$var wire 1 `= S $end -$var wire 1 Z= in0 $end -$var wire 1 U= in1 $end -$var wire 1 a= nS $end -$var wire 1 b= out0 $end -$var wire 1 c= out1 $end -$var wire 1 Y= outfinal $end -$upscope $end -$upscope $end -$upscope $end -$scope begin orbits[18] $end -$scope module attempt $end -$var wire 1 d= A $end -$var wire 1 e= AnandB $end -$var wire 1 f= AnorB $end -$var wire 1 g= AorB $end -$var wire 1 h= AxorB $end -$var wire 1 i= B $end -$var wire 3 j= Command [2:0] $end -$var wire 1 k= OrNorXorOut $end -$var wire 1 l= XorNor $end -$var wire 1 m= nXor $end -$scope module mux0 $end -$var wire 1 n= S $end -$var wire 1 h= in0 $end -$var wire 1 f= in1 $end -$var wire 1 o= nS $end -$var wire 1 p= out0 $end -$var wire 1 q= out1 $end -$var wire 1 l= outfinal $end -$upscope $end -$scope module mux1 $end -$var wire 1 r= S $end -$var wire 1 l= in0 $end -$var wire 1 g= in1 $end -$var wire 1 s= nS $end -$var wire 1 t= out0 $end -$var wire 1 u= out1 $end -$var wire 1 k= outfinal $end -$upscope $end -$upscope $end -$upscope $end -$scope begin orbits[19] $end -$scope module attempt $end -$var wire 1 v= A $end -$var wire 1 w= AnandB $end -$var wire 1 x= AnorB $end -$var wire 1 y= AorB $end -$var wire 1 z= AxorB $end -$var wire 1 {= B $end -$var wire 3 |= Command [2:0] $end -$var wire 1 }= OrNorXorOut $end -$var wire 1 ~= XorNor $end -$var wire 1 !> nXor $end -$scope module mux0 $end -$var wire 1 "> S $end -$var wire 1 z= in0 $end -$var wire 1 x= in1 $end -$var wire 1 #> nS $end -$var wire 1 $> out0 $end -$var wire 1 %> out1 $end -$var wire 1 ~= outfinal $end -$upscope $end -$scope module mux1 $end -$var wire 1 &> S $end -$var wire 1 ~= in0 $end -$var wire 1 y= in1 $end -$var wire 1 '> nS $end -$var wire 1 (> out0 $end -$var wire 1 )> out1 $end -$var wire 1 }= outfinal $end -$upscope $end -$upscope $end -$upscope $end -$scope begin orbits[20] $end -$scope module attempt $end -$var wire 1 *> A $end -$var wire 1 +> AnandB $end -$var wire 1 ,> AnorB $end -$var wire 1 -> AorB $end -$var wire 1 .> AxorB $end -$var wire 1 /> B $end -$var wire 3 0> Command [2:0] $end -$var wire 1 1> OrNorXorOut $end -$var wire 1 2> XorNor $end -$var wire 1 3> nXor $end -$scope module mux0 $end -$var wire 1 4> S $end -$var wire 1 .> in0 $end -$var wire 1 ,> in1 $end -$var wire 1 5> nS $end -$var wire 1 6> out0 $end -$var wire 1 7> out1 $end -$var wire 1 2> outfinal $end -$upscope $end -$scope module mux1 $end -$var wire 1 8> S $end -$var wire 1 2> in0 $end -$var wire 1 -> in1 $end -$var wire 1 9> nS $end -$var wire 1 :> out0 $end -$var wire 1 ;> out1 $end -$var wire 1 1> outfinal $end -$upscope $end -$upscope $end -$upscope $end -$scope begin orbits[21] $end -$scope module attempt $end -$var wire 1 <> A $end -$var wire 1 => AnandB $end -$var wire 1 >> AnorB $end -$var wire 1 ?> AorB $end -$var wire 1 @> AxorB $end -$var wire 1 A> B $end -$var wire 3 B> Command [2:0] $end -$var wire 1 C> OrNorXorOut $end -$var wire 1 D> XorNor $end -$var wire 1 E> nXor $end -$scope module mux0 $end -$var wire 1 F> S $end -$var wire 1 @> in0 $end -$var wire 1 >> in1 $end -$var wire 1 G> nS $end -$var wire 1 H> out0 $end -$var wire 1 I> out1 $end -$var wire 1 D> outfinal $end -$upscope $end -$scope module mux1 $end -$var wire 1 J> S $end -$var wire 1 D> in0 $end -$var wire 1 ?> in1 $end -$var wire 1 K> nS $end -$var wire 1 L> out0 $end -$var wire 1 M> out1 $end -$var wire 1 C> outfinal $end -$upscope $end -$upscope $end -$upscope $end -$scope begin orbits[22] $end -$scope module attempt $end -$var wire 1 N> A $end -$var wire 1 O> AnandB $end -$var wire 1 P> AnorB $end -$var wire 1 Q> AorB $end -$var wire 1 R> AxorB $end -$var wire 1 S> B $end -$var wire 3 T> Command [2:0] $end -$var wire 1 U> OrNorXorOut $end -$var wire 1 V> XorNor $end -$var wire 1 W> nXor $end -$scope module mux0 $end -$var wire 1 X> S $end -$var wire 1 R> in0 $end -$var wire 1 P> in1 $end -$var wire 1 Y> nS $end -$var wire 1 Z> out0 $end -$var wire 1 [> out1 $end -$var wire 1 V> outfinal $end -$upscope $end -$scope module mux1 $end -$var wire 1 \> S $end -$var wire 1 V> in0 $end -$var wire 1 Q> in1 $end -$var wire 1 ]> nS $end -$var wire 1 ^> out0 $end -$var wire 1 _> out1 $end -$var wire 1 U> outfinal $end -$upscope $end -$upscope $end -$upscope $end -$scope begin orbits[23] $end -$scope module attempt $end -$var wire 1 `> A $end -$var wire 1 a> AnandB $end -$var wire 1 b> AnorB $end -$var wire 1 c> AorB $end -$var wire 1 d> AxorB $end -$var wire 1 e> B $end -$var wire 3 f> Command [2:0] $end -$var wire 1 g> OrNorXorOut $end -$var wire 1 h> XorNor $end -$var wire 1 i> nXor $end -$scope module mux0 $end -$var wire 1 j> S $end -$var wire 1 d> in0 $end -$var wire 1 b> in1 $end -$var wire 1 k> nS $end -$var wire 1 l> out0 $end -$var wire 1 m> out1 $end -$var wire 1 h> outfinal $end -$upscope $end -$scope module mux1 $end -$var wire 1 n> S $end -$var wire 1 h> in0 $end -$var wire 1 c> in1 $end -$var wire 1 o> nS $end -$var wire 1 p> out0 $end -$var wire 1 q> out1 $end -$var wire 1 g> outfinal $end -$upscope $end -$upscope $end -$upscope $end -$scope begin orbits[24] $end -$scope module attempt $end -$var wire 1 r> A $end -$var wire 1 s> AnandB $end -$var wire 1 t> AnorB $end -$var wire 1 u> AorB $end -$var wire 1 v> AxorB $end -$var wire 1 w> B $end -$var wire 3 x> Command [2:0] $end -$var wire 1 y> OrNorXorOut $end -$var wire 1 z> XorNor $end -$var wire 1 {> nXor $end -$scope module mux0 $end -$var wire 1 |> S $end -$var wire 1 v> in0 $end -$var wire 1 t> in1 $end -$var wire 1 }> nS $end -$var wire 1 ~> out0 $end -$var wire 1 !? out1 $end -$var wire 1 z> outfinal $end -$upscope $end -$scope module mux1 $end -$var wire 1 "? S $end -$var wire 1 z> in0 $end -$var wire 1 u> in1 $end -$var wire 1 #? nS $end -$var wire 1 $? out0 $end -$var wire 1 %? out1 $end -$var wire 1 y> outfinal $end -$upscope $end -$upscope $end -$upscope $end -$scope begin orbits[25] $end -$scope module attempt $end -$var wire 1 &? A $end -$var wire 1 '? AnandB $end -$var wire 1 (? AnorB $end -$var wire 1 )? AorB $end -$var wire 1 *? AxorB $end -$var wire 1 +? B $end -$var wire 3 ,? Command [2:0] $end -$var wire 1 -? OrNorXorOut $end -$var wire 1 .? XorNor $end -$var wire 1 /? nXor $end -$scope module mux0 $end -$var wire 1 0? S $end -$var wire 1 *? in0 $end -$var wire 1 (? in1 $end -$var wire 1 1? nS $end -$var wire 1 2? out0 $end -$var wire 1 3? out1 $end -$var wire 1 .? outfinal $end -$upscope $end -$scope module mux1 $end -$var wire 1 4? S $end -$var wire 1 .? in0 $end -$var wire 1 )? in1 $end -$var wire 1 5? nS $end -$var wire 1 6? out0 $end -$var wire 1 7? out1 $end -$var wire 1 -? outfinal $end -$upscope $end -$upscope $end -$upscope $end -$scope begin orbits[26] $end -$scope module attempt $end -$var wire 1 8? A $end -$var wire 1 9? AnandB $end -$var wire 1 :? AnorB $end -$var wire 1 ;? AorB $end -$var wire 1 ? Command [2:0] $end -$var wire 1 ?? OrNorXorOut $end -$var wire 1 @? XorNor $end -$var wire 1 A? nXor $end -$scope module mux0 $end -$var wire 1 B? S $end -$var wire 1 @ S $end -$var wire 1 8@ in0 $end -$var wire 1 6@ in1 $end -$var wire 1 ?@ nS $end -$var wire 1 @@ out0 $end -$var wire 1 A@ out1 $end -$var wire 1 <@ outfinal $end -$upscope $end -$scope module mux1 $end -$var wire 1 B@ S $end -$var wire 1 <@ in0 $end -$var wire 1 7@ in1 $end -$var wire 1 C@ nS $end -$var wire 1 D@ out0 $end -$var wire 1 E@ out1 $end -$var wire 1 ;@ outfinal $end -$upscope $end -$upscope $end -$upscope $end -$upscope $end -$scope module ZeroMux0case $end -$var wire 1 F@ S0 $end -$var wire 1 G@ S1 $end -$var wire 1 H@ in0 $end -$var wire 1 I@ in1 $end -$var wire 1 J@ in2 $end -$var wire 1 K@ in3 $end -$var wire 1 L@ nS0 $end -$var wire 1 M@ nS1 $end -$var wire 1 N@ out $end -$var wire 1 O@ out0 $end -$var wire 1 P@ out1 $end -$var wire 1 Q@ out2 $end -$var wire 1 R@ out3 $end -$upscope $end -$scope module OneMux0case $end -$var wire 1 S@ S0 $end -$var wire 1 T@ S1 $end -$var wire 1 U@ in0 $end -$var wire 1 V@ in1 $end -$var wire 1 W@ in2 $end -$var wire 1 X@ in3 $end -$var wire 1 Y@ nS0 $end -$var wire 1 Z@ nS1 $end -$var wire 1 [@ out $end -$var wire 1 \@ out0 $end -$var wire 1 ]@ out1 $end -$var wire 1 ^@ out2 $end -$var wire 1 _@ out3 $end -$upscope $end -$scope module TwoMux0case $end -$var wire 1 `@ S $end -$var wire 1 a@ in0 $end -$var wire 1 b@ in1 $end -$var wire 1 c@ nS $end -$var wire 1 d@ out0 $end -$var wire 1 e@ out1 $end -$var wire 1 f@ outfinal $end -$upscope $end -$scope begin muxbits[1] $end -$scope module ZeroMux $end -$var wire 1 g@ S0 $end -$var wire 1 h@ S1 $end -$var wire 1 i@ in0 $end -$var wire 1 j@ in1 $end -$var wire 1 k@ in2 $end -$var wire 1 l@ in3 $end -$var wire 1 m@ nS0 $end -$var wire 1 n@ nS1 $end -$var wire 1 o@ out $end -$var wire 1 p@ out0 $end -$var wire 1 q@ out1 $end -$var wire 1 r@ out2 $end -$var wire 1 s@ out3 $end -$upscope $end -$scope module OneMux $end -$var wire 1 t@ S0 $end -$var wire 1 u@ S1 $end -$var wire 1 v@ in0 $end -$var wire 1 w@ in1 $end -$var wire 1 x@ in2 $end -$var wire 1 y@ in3 $end -$var wire 1 z@ nS0 $end -$var wire 1 {@ nS1 $end -$var wire 1 |@ out $end -$var wire 1 }@ out0 $end -$var wire 1 ~@ out1 $end -$var wire 1 !A out2 $end -$var wire 1 "A out3 $end -$upscope $end -$scope module TwoMux $end -$var wire 1 #A S $end -$var wire 1 $A in0 $end -$var wire 1 %A in1 $end -$var wire 1 &A nS $end -$var wire 1 'A out0 $end -$var wire 1 (A out1 $end -$var wire 1 )A outfinal $end -$upscope $end -$upscope $end -$scope begin muxbits[2] $end -$scope module ZeroMux $end -$var wire 1 *A S0 $end -$var wire 1 +A S1 $end -$var wire 1 ,A in0 $end -$var wire 1 -A in1 $end -$var wire 1 .A in2 $end -$var wire 1 /A in3 $end -$var wire 1 0A nS0 $end -$var wire 1 1A nS1 $end -$var wire 1 2A out $end -$var wire 1 3A out0 $end -$var wire 1 4A out1 $end -$var wire 1 5A out2 $end -$var wire 1 6A out3 $end -$upscope $end -$scope module OneMux $end -$var wire 1 7A S0 $end -$var wire 1 8A S1 $end -$var wire 1 9A in0 $end -$var wire 1 :A in1 $end -$var wire 1 ;A in2 $end -$var wire 1 A nS1 $end -$var wire 1 ?A out $end -$var wire 1 @A out0 $end -$var wire 1 AA out1 $end -$var wire 1 BA out2 $end -$var wire 1 CA out3 $end -$upscope $end -$scope module TwoMux $end -$var wire 1 DA S $end -$var wire 1 EA in0 $end -$var wire 1 FA in1 $end -$var wire 1 GA nS $end -$var wire 1 HA out0 $end -$var wire 1 IA out1 $end -$var wire 1 JA outfinal $end -$upscope $end -$upscope $end -$scope begin muxbits[3] $end -$scope module ZeroMux $end -$var wire 1 KA S0 $end -$var wire 1 LA S1 $end -$var wire 1 MA in0 $end -$var wire 1 NA in1 $end -$var wire 1 OA in2 $end -$var wire 1 PA in3 $end -$var wire 1 QA nS0 $end -$var wire 1 RA nS1 $end -$var wire 1 SA out $end -$var wire 1 TA out0 $end -$var wire 1 UA out1 $end -$var wire 1 VA out2 $end -$var wire 1 WA out3 $end -$upscope $end -$scope module OneMux $end -$var wire 1 XA S0 $end -$var wire 1 YA S1 $end -$var wire 1 ZA in0 $end -$var wire 1 [A in1 $end -$var wire 1 \A in2 $end -$var wire 1 ]A in3 $end -$var wire 1 ^A nS0 $end -$var wire 1 _A nS1 $end -$var wire 1 `A out $end -$var wire 1 aA out0 $end -$var wire 1 bA out1 $end -$var wire 1 cA out2 $end -$var wire 1 dA out3 $end -$upscope $end -$scope module TwoMux $end -$var wire 1 eA S $end -$var wire 1 fA in0 $end -$var wire 1 gA in1 $end -$var wire 1 hA nS $end -$var wire 1 iA out0 $end -$var wire 1 jA out1 $end -$var wire 1 kA outfinal $end -$upscope $end -$upscope $end -$scope begin muxbits[4] $end -$scope module ZeroMux $end -$var wire 1 lA S0 $end -$var wire 1 mA S1 $end -$var wire 1 nA in0 $end -$var wire 1 oA in1 $end -$var wire 1 pA in2 $end -$var wire 1 qA in3 $end -$var wire 1 rA nS0 $end -$var wire 1 sA nS1 $end -$var wire 1 tA out $end -$var wire 1 uA out0 $end -$var wire 1 vA out1 $end -$var wire 1 wA out2 $end -$var wire 1 xA out3 $end -$upscope $end -$scope module OneMux $end -$var wire 1 yA S0 $end -$var wire 1 zA S1 $end -$var wire 1 {A in0 $end -$var wire 1 |A in1 $end -$var wire 1 }A in2 $end -$var wire 1 ~A in3 $end -$var wire 1 !B nS0 $end -$var wire 1 "B nS1 $end -$var wire 1 #B out $end -$var wire 1 $B out0 $end -$var wire 1 %B out1 $end -$var wire 1 &B out2 $end -$var wire 1 'B out3 $end -$upscope $end -$scope module TwoMux $end -$var wire 1 (B S $end -$var wire 1 )B in0 $end -$var wire 1 *B in1 $end -$var wire 1 +B nS $end -$var wire 1 ,B out0 $end -$var wire 1 -B out1 $end -$var wire 1 .B outfinal $end -$upscope $end -$upscope $end -$scope begin muxbits[5] $end -$scope module ZeroMux $end -$var wire 1 /B S0 $end -$var wire 1 0B S1 $end -$var wire 1 1B in0 $end -$var wire 1 2B in1 $end -$var wire 1 3B in2 $end -$var wire 1 4B in3 $end -$var wire 1 5B nS0 $end -$var wire 1 6B nS1 $end -$var wire 1 7B out $end -$var wire 1 8B out0 $end -$var wire 1 9B out1 $end -$var wire 1 :B out2 $end -$var wire 1 ;B out3 $end -$upscope $end -$scope module OneMux $end -$var wire 1 B in0 $end -$var wire 1 ?B in1 $end -$var wire 1 @B in2 $end -$var wire 1 AB in3 $end -$var wire 1 BB nS0 $end -$var wire 1 CB nS1 $end -$var wire 1 DB out $end -$var wire 1 EB out0 $end -$var wire 1 FB out1 $end -$var wire 1 GB out2 $end -$var wire 1 HB out3 $end -$upscope $end -$scope module TwoMux $end -$var wire 1 IB S $end -$var wire 1 JB in0 $end -$var wire 1 KB in1 $end -$var wire 1 LB nS $end -$var wire 1 MB out0 $end -$var wire 1 NB out1 $end -$var wire 1 OB outfinal $end -$upscope $end -$upscope $end -$scope begin muxbits[6] $end -$scope module ZeroMux $end -$var wire 1 PB S0 $end -$var wire 1 QB S1 $end -$var wire 1 RB in0 $end -$var wire 1 SB in1 $end -$var wire 1 TB in2 $end -$var wire 1 UB in3 $end -$var wire 1 VB nS0 $end -$var wire 1 WB nS1 $end -$var wire 1 XB out $end -$var wire 1 YB out0 $end -$var wire 1 ZB out1 $end -$var wire 1 [B out2 $end -$var wire 1 \B out3 $end -$upscope $end -$scope module OneMux $end -$var wire 1 ]B S0 $end -$var wire 1 ^B S1 $end -$var wire 1 _B in0 $end -$var wire 1 `B in1 $end -$var wire 1 aB in2 $end -$var wire 1 bB in3 $end -$var wire 1 cB nS0 $end -$var wire 1 dB nS1 $end -$var wire 1 eB out $end -$var wire 1 fB out0 $end -$var wire 1 gB out1 $end -$var wire 1 hB out2 $end -$var wire 1 iB out3 $end -$upscope $end -$scope module TwoMux $end -$var wire 1 jB S $end -$var wire 1 kB in0 $end -$var wire 1 lB in1 $end -$var wire 1 mB nS $end -$var wire 1 nB out0 $end -$var wire 1 oB out1 $end -$var wire 1 pB outfinal $end -$upscope $end -$upscope $end -$scope begin muxbits[7] $end -$scope module ZeroMux $end -$var wire 1 qB S0 $end -$var wire 1 rB S1 $end -$var wire 1 sB in0 $end -$var wire 1 tB in1 $end -$var wire 1 uB in2 $end -$var wire 1 vB in3 $end -$var wire 1 wB nS0 $end -$var wire 1 xB nS1 $end -$var wire 1 yB out $end -$var wire 1 zB out0 $end -$var wire 1 {B out1 $end -$var wire 1 |B out2 $end -$var wire 1 }B out3 $end -$upscope $end -$scope module OneMux $end -$var wire 1 ~B S0 $end -$var wire 1 !C S1 $end -$var wire 1 "C in0 $end -$var wire 1 #C in1 $end -$var wire 1 $C in2 $end -$var wire 1 %C in3 $end -$var wire 1 &C nS0 $end -$var wire 1 'C nS1 $end -$var wire 1 (C out $end -$var wire 1 )C out0 $end -$var wire 1 *C out1 $end -$var wire 1 +C out2 $end -$var wire 1 ,C out3 $end -$upscope $end -$scope module TwoMux $end -$var wire 1 -C S $end -$var wire 1 .C in0 $end -$var wire 1 /C in1 $end -$var wire 1 0C nS $end -$var wire 1 1C out0 $end -$var wire 1 2C out1 $end -$var wire 1 3C outfinal $end -$upscope $end -$upscope $end -$scope begin muxbits[8] $end -$scope module ZeroMux $end -$var wire 1 4C S0 $end -$var wire 1 5C S1 $end -$var wire 1 6C in0 $end -$var wire 1 7C in1 $end -$var wire 1 8C in2 $end -$var wire 1 9C in3 $end -$var wire 1 :C nS0 $end -$var wire 1 ;C nS1 $end -$var wire 1 C out1 $end -$var wire 1 ?C out2 $end -$var wire 1 @C out3 $end -$upscope $end -$scope module OneMux $end -$var wire 1 AC S0 $end -$var wire 1 BC S1 $end -$var wire 1 CC in0 $end -$var wire 1 DC in1 $end -$var wire 1 EC in2 $end -$var wire 1 FC in3 $end -$var wire 1 GC nS0 $end -$var wire 1 HC nS1 $end -$var wire 1 IC out $end -$var wire 1 JC out0 $end -$var wire 1 KC out1 $end -$var wire 1 LC out2 $end -$var wire 1 MC out3 $end -$upscope $end -$scope module TwoMux $end -$var wire 1 NC S $end -$var wire 1 OC in0 $end -$var wire 1 PC in1 $end -$var wire 1 QC nS $end -$var wire 1 RC out0 $end -$var wire 1 SC out1 $end -$var wire 1 TC outfinal $end -$upscope $end -$upscope $end -$scope begin muxbits[9] $end -$scope module ZeroMux $end -$var wire 1 UC S0 $end -$var wire 1 VC S1 $end -$var wire 1 WC in0 $end -$var wire 1 XC in1 $end -$var wire 1 YC in2 $end -$var wire 1 ZC in3 $end -$var wire 1 [C nS0 $end -$var wire 1 \C nS1 $end -$var wire 1 ]C out $end -$var wire 1 ^C out0 $end -$var wire 1 _C out1 $end -$var wire 1 `C out2 $end -$var wire 1 aC out3 $end -$upscope $end -$scope module OneMux $end -$var wire 1 bC S0 $end -$var wire 1 cC S1 $end -$var wire 1 dC in0 $end -$var wire 1 eC in1 $end -$var wire 1 fC in2 $end -$var wire 1 gC in3 $end -$var wire 1 hC nS0 $end -$var wire 1 iC nS1 $end -$var wire 1 jC out $end -$var wire 1 kC out0 $end -$var wire 1 lC out1 $end -$var wire 1 mC out2 $end -$var wire 1 nC out3 $end -$upscope $end -$scope module TwoMux $end -$var wire 1 oC S $end -$var wire 1 pC in0 $end -$var wire 1 qC in1 $end -$var wire 1 rC nS $end -$var wire 1 sC out0 $end -$var wire 1 tC out1 $end -$var wire 1 uC outfinal $end -$upscope $end -$upscope $end -$scope begin muxbits[10] $end -$scope module ZeroMux $end -$var wire 1 vC S0 $end -$var wire 1 wC S1 $end -$var wire 1 xC in0 $end -$var wire 1 yC in1 $end -$var wire 1 zC in2 $end -$var wire 1 {C in3 $end -$var wire 1 |C nS0 $end -$var wire 1 }C nS1 $end -$var wire 1 ~C out $end -$var wire 1 !D out0 $end -$var wire 1 "D out1 $end -$var wire 1 #D out2 $end -$var wire 1 $D out3 $end -$upscope $end -$scope module OneMux $end -$var wire 1 %D S0 $end -$var wire 1 &D S1 $end -$var wire 1 'D in0 $end -$var wire 1 (D in1 $end -$var wire 1 )D in2 $end -$var wire 1 *D in3 $end -$var wire 1 +D nS0 $end -$var wire 1 ,D nS1 $end -$var wire 1 -D out $end -$var wire 1 .D out0 $end -$var wire 1 /D out1 $end -$var wire 1 0D out2 $end -$var wire 1 1D out3 $end -$upscope $end -$scope module TwoMux $end -$var wire 1 2D S $end -$var wire 1 3D in0 $end -$var wire 1 4D in1 $end -$var wire 1 5D nS $end -$var wire 1 6D out0 $end -$var wire 1 7D out1 $end -$var wire 1 8D outfinal $end -$upscope $end -$upscope $end -$scope begin muxbits[11] $end -$scope module ZeroMux $end -$var wire 1 9D S0 $end -$var wire 1 :D S1 $end -$var wire 1 ;D in0 $end -$var wire 1 D in3 $end -$var wire 1 ?D nS0 $end -$var wire 1 @D nS1 $end -$var wire 1 AD out $end -$var wire 1 BD out0 $end -$var wire 1 CD out1 $end -$var wire 1 DD out2 $end -$var wire 1 ED out3 $end -$upscope $end -$scope module OneMux $end -$var wire 1 FD S0 $end -$var wire 1 GD S1 $end -$var wire 1 HD in0 $end -$var wire 1 ID in1 $end -$var wire 1 JD in2 $end -$var wire 1 KD in3 $end -$var wire 1 LD nS0 $end -$var wire 1 MD nS1 $end -$var wire 1 ND out $end -$var wire 1 OD out0 $end -$var wire 1 PD out1 $end -$var wire 1 QD out2 $end -$var wire 1 RD out3 $end -$upscope $end -$scope module TwoMux $end -$var wire 1 SD S $end -$var wire 1 TD in0 $end -$var wire 1 UD in1 $end -$var wire 1 VD nS $end -$var wire 1 WD out0 $end -$var wire 1 XD out1 $end -$var wire 1 YD outfinal $end -$upscope $end -$upscope $end -$scope begin muxbits[12] $end -$scope module ZeroMux $end -$var wire 1 ZD S0 $end -$var wire 1 [D S1 $end -$var wire 1 \D in0 $end -$var wire 1 ]D in1 $end -$var wire 1 ^D in2 $end -$var wire 1 _D in3 $end -$var wire 1 `D nS0 $end -$var wire 1 aD nS1 $end -$var wire 1 bD out $end -$var wire 1 cD out0 $end -$var wire 1 dD out1 $end -$var wire 1 eD out2 $end -$var wire 1 fD out3 $end -$upscope $end -$scope module OneMux $end -$var wire 1 gD S0 $end -$var wire 1 hD S1 $end -$var wire 1 iD in0 $end -$var wire 1 jD in1 $end -$var wire 1 kD in2 $end -$var wire 1 lD in3 $end -$var wire 1 mD nS0 $end -$var wire 1 nD nS1 $end -$var wire 1 oD out $end -$var wire 1 pD out0 $end -$var wire 1 qD out1 $end -$var wire 1 rD out2 $end -$var wire 1 sD out3 $end -$upscope $end -$scope module TwoMux $end -$var wire 1 tD S $end -$var wire 1 uD in0 $end -$var wire 1 vD in1 $end -$var wire 1 wD nS $end -$var wire 1 xD out0 $end -$var wire 1 yD out1 $end -$var wire 1 zD outfinal $end -$upscope $end -$upscope $end -$scope begin muxbits[13] $end -$scope module ZeroMux $end -$var wire 1 {D S0 $end -$var wire 1 |D S1 $end -$var wire 1 }D in0 $end -$var wire 1 ~D in1 $end -$var wire 1 !E in2 $end -$var wire 1 "E in3 $end -$var wire 1 #E nS0 $end -$var wire 1 $E nS1 $end -$var wire 1 %E out $end -$var wire 1 &E out0 $end -$var wire 1 'E out1 $end -$var wire 1 (E out2 $end -$var wire 1 )E out3 $end -$upscope $end -$scope module OneMux $end -$var wire 1 *E S0 $end -$var wire 1 +E S1 $end -$var wire 1 ,E in0 $end -$var wire 1 -E in1 $end -$var wire 1 .E in2 $end -$var wire 1 /E in3 $end -$var wire 1 0E nS0 $end -$var wire 1 1E nS1 $end -$var wire 1 2E out $end -$var wire 1 3E out0 $end -$var wire 1 4E out1 $end -$var wire 1 5E out2 $end -$var wire 1 6E out3 $end -$upscope $end -$scope module TwoMux $end -$var wire 1 7E S $end -$var wire 1 8E in0 $end -$var wire 1 9E in1 $end -$var wire 1 :E nS $end -$var wire 1 ;E out0 $end -$var wire 1 E S0 $end -$var wire 1 ?E S1 $end -$var wire 1 @E in0 $end -$var wire 1 AE in1 $end -$var wire 1 BE in2 $end -$var wire 1 CE in3 $end -$var wire 1 DE nS0 $end -$var wire 1 EE nS1 $end -$var wire 1 FE out $end -$var wire 1 GE out0 $end -$var wire 1 HE out1 $end -$var wire 1 IE out2 $end -$var wire 1 JE out3 $end -$upscope $end -$scope module OneMux $end -$var wire 1 KE S0 $end -$var wire 1 LE S1 $end -$var wire 1 ME in0 $end -$var wire 1 NE in1 $end -$var wire 1 OE in2 $end -$var wire 1 PE in3 $end -$var wire 1 QE nS0 $end -$var wire 1 RE nS1 $end -$var wire 1 SE out $end -$var wire 1 TE out0 $end -$var wire 1 UE out1 $end -$var wire 1 VE out2 $end -$var wire 1 WE out3 $end -$upscope $end -$scope module TwoMux $end -$var wire 1 XE S $end -$var wire 1 YE in0 $end -$var wire 1 ZE in1 $end -$var wire 1 [E nS $end -$var wire 1 \E out0 $end -$var wire 1 ]E out1 $end -$var wire 1 ^E outfinal $end -$upscope $end -$upscope $end -$scope begin muxbits[15] $end -$scope module ZeroMux $end -$var wire 1 _E S0 $end -$var wire 1 `E S1 $end -$var wire 1 aE in0 $end -$var wire 1 bE in1 $end -$var wire 1 cE in2 $end -$var wire 1 dE in3 $end -$var wire 1 eE nS0 $end -$var wire 1 fE nS1 $end -$var wire 1 gE out $end -$var wire 1 hE out0 $end -$var wire 1 iE out1 $end -$var wire 1 jE out2 $end -$var wire 1 kE out3 $end -$upscope $end -$scope module OneMux $end -$var wire 1 lE S0 $end -$var wire 1 mE S1 $end -$var wire 1 nE in0 $end -$var wire 1 oE in1 $end -$var wire 1 pE in2 $end -$var wire 1 qE in3 $end -$var wire 1 rE nS0 $end -$var wire 1 sE nS1 $end -$var wire 1 tE out $end -$var wire 1 uE out0 $end -$var wire 1 vE out1 $end -$var wire 1 wE out2 $end -$var wire 1 xE out3 $end -$upscope $end -$scope module TwoMux $end -$var wire 1 yE S $end -$var wire 1 zE in0 $end -$var wire 1 {E in1 $end -$var wire 1 |E nS $end -$var wire 1 }E out0 $end -$var wire 1 ~E out1 $end -$var wire 1 !F outfinal $end -$upscope $end -$upscope $end -$scope begin muxbits[16] $end -$scope module ZeroMux $end -$var wire 1 "F S0 $end -$var wire 1 #F S1 $end -$var wire 1 $F in0 $end -$var wire 1 %F in1 $end -$var wire 1 &F in2 $end -$var wire 1 'F in3 $end -$var wire 1 (F nS0 $end -$var wire 1 )F nS1 $end -$var wire 1 *F out $end -$var wire 1 +F out0 $end -$var wire 1 ,F out1 $end -$var wire 1 -F out2 $end -$var wire 1 .F out3 $end -$upscope $end -$scope module OneMux $end -$var wire 1 /F S0 $end -$var wire 1 0F S1 $end -$var wire 1 1F in0 $end -$var wire 1 2F in1 $end -$var wire 1 3F in2 $end -$var wire 1 4F in3 $end -$var wire 1 5F nS0 $end -$var wire 1 6F nS1 $end -$var wire 1 7F out $end -$var wire 1 8F out0 $end -$var wire 1 9F out1 $end -$var wire 1 :F out2 $end -$var wire 1 ;F out3 $end -$upscope $end -$scope module TwoMux $end -$var wire 1 F in1 $end -$var wire 1 ?F nS $end -$var wire 1 @F out0 $end -$var wire 1 AF out1 $end -$var wire 1 BF outfinal $end -$upscope $end -$upscope $end -$scope begin muxbits[17] $end -$scope module ZeroMux $end -$var wire 1 CF S0 $end -$var wire 1 DF S1 $end -$var wire 1 EF in0 $end -$var wire 1 FF in1 $end -$var wire 1 GF in2 $end -$var wire 1 HF in3 $end -$var wire 1 IF nS0 $end -$var wire 1 JF nS1 $end -$var wire 1 KF out $end -$var wire 1 LF out0 $end -$var wire 1 MF out1 $end -$var wire 1 NF out2 $end -$var wire 1 OF out3 $end -$upscope $end -$scope module OneMux $end -$var wire 1 PF S0 $end -$var wire 1 QF S1 $end -$var wire 1 RF in0 $end -$var wire 1 SF in1 $end -$var wire 1 TF in2 $end -$var wire 1 UF in3 $end -$var wire 1 VF nS0 $end -$var wire 1 WF nS1 $end -$var wire 1 XF out $end -$var wire 1 YF out0 $end -$var wire 1 ZF out1 $end -$var wire 1 [F out2 $end -$var wire 1 \F out3 $end -$upscope $end -$scope module TwoMux $end -$var wire 1 ]F S $end -$var wire 1 ^F in0 $end -$var wire 1 _F in1 $end -$var wire 1 `F nS $end -$var wire 1 aF out0 $end -$var wire 1 bF out1 $end -$var wire 1 cF outfinal $end -$upscope $end -$upscope $end -$scope begin muxbits[18] $end -$scope module ZeroMux $end -$var wire 1 dF S0 $end -$var wire 1 eF S1 $end -$var wire 1 fF in0 $end -$var wire 1 gF in1 $end -$var wire 1 hF in2 $end -$var wire 1 iF in3 $end -$var wire 1 jF nS0 $end -$var wire 1 kF nS1 $end -$var wire 1 lF out $end -$var wire 1 mF out0 $end -$var wire 1 nF out1 $end -$var wire 1 oF out2 $end -$var wire 1 pF out3 $end -$upscope $end -$scope module OneMux $end -$var wire 1 qF S0 $end -$var wire 1 rF S1 $end -$var wire 1 sF in0 $end -$var wire 1 tF in1 $end -$var wire 1 uF in2 $end -$var wire 1 vF in3 $end -$var wire 1 wF nS0 $end -$var wire 1 xF nS1 $end -$var wire 1 yF out $end -$var wire 1 zF out0 $end -$var wire 1 {F out1 $end -$var wire 1 |F out2 $end -$var wire 1 }F out3 $end -$upscope $end -$scope module TwoMux $end -$var wire 1 ~F S $end -$var wire 1 !G in0 $end -$var wire 1 "G in1 $end -$var wire 1 #G nS $end -$var wire 1 $G out0 $end -$var wire 1 %G out1 $end -$var wire 1 &G outfinal $end -$upscope $end -$upscope $end -$scope begin muxbits[19] $end -$scope module ZeroMux $end -$var wire 1 'G S0 $end -$var wire 1 (G S1 $end -$var wire 1 )G in0 $end -$var wire 1 *G in1 $end -$var wire 1 +G in2 $end -$var wire 1 ,G in3 $end -$var wire 1 -G nS0 $end -$var wire 1 .G nS1 $end -$var wire 1 /G out $end -$var wire 1 0G out0 $end -$var wire 1 1G out1 $end -$var wire 1 2G out2 $end -$var wire 1 3G out3 $end -$upscope $end -$scope module OneMux $end -$var wire 1 4G S0 $end -$var wire 1 5G S1 $end -$var wire 1 6G in0 $end -$var wire 1 7G in1 $end -$var wire 1 8G in2 $end -$var wire 1 9G in3 $end -$var wire 1 :G nS0 $end -$var wire 1 ;G nS1 $end -$var wire 1 G out1 $end -$var wire 1 ?G out2 $end -$var wire 1 @G out3 $end -$upscope $end -$scope module TwoMux $end -$var wire 1 AG S $end -$var wire 1 BG in0 $end -$var wire 1 CG in1 $end -$var wire 1 DG nS $end -$var wire 1 EG out0 $end -$var wire 1 FG out1 $end -$var wire 1 GG outfinal $end -$upscope $end -$upscope $end -$scope begin muxbits[20] $end -$scope module ZeroMux $end -$var wire 1 HG S0 $end -$var wire 1 IG S1 $end -$var wire 1 JG in0 $end -$var wire 1 KG in1 $end -$var wire 1 LG in2 $end -$var wire 1 MG in3 $end -$var wire 1 NG nS0 $end -$var wire 1 OG nS1 $end -$var wire 1 PG out $end -$var wire 1 QG out0 $end -$var wire 1 RG out1 $end -$var wire 1 SG out2 $end -$var wire 1 TG out3 $end -$upscope $end -$scope module OneMux $end -$var wire 1 UG S0 $end -$var wire 1 VG S1 $end -$var wire 1 WG in0 $end -$var wire 1 XG in1 $end -$var wire 1 YG in2 $end -$var wire 1 ZG in3 $end -$var wire 1 [G nS0 $end -$var wire 1 \G nS1 $end -$var wire 1 ]G out $end -$var wire 1 ^G out0 $end -$var wire 1 _G out1 $end -$var wire 1 `G out2 $end -$var wire 1 aG out3 $end -$upscope $end -$scope module TwoMux $end -$var wire 1 bG S $end -$var wire 1 cG in0 $end -$var wire 1 dG in1 $end -$var wire 1 eG nS $end -$var wire 1 fG out0 $end -$var wire 1 gG out1 $end -$var wire 1 hG outfinal $end -$upscope $end -$upscope $end -$scope begin muxbits[21] $end -$scope module ZeroMux $end -$var wire 1 iG S0 $end -$var wire 1 jG S1 $end -$var wire 1 kG in0 $end -$var wire 1 lG in1 $end -$var wire 1 mG in2 $end -$var wire 1 nG in3 $end -$var wire 1 oG nS0 $end -$var wire 1 pG nS1 $end -$var wire 1 qG out $end -$var wire 1 rG out0 $end -$var wire 1 sG out1 $end -$var wire 1 tG out2 $end -$var wire 1 uG out3 $end -$upscope $end -$scope module OneMux $end -$var wire 1 vG S0 $end -$var wire 1 wG S1 $end -$var wire 1 xG in0 $end -$var wire 1 yG in1 $end -$var wire 1 zG in2 $end -$var wire 1 {G in3 $end -$var wire 1 |G nS0 $end -$var wire 1 }G nS1 $end -$var wire 1 ~G out $end -$var wire 1 !H out0 $end -$var wire 1 "H out1 $end -$var wire 1 #H out2 $end -$var wire 1 $H out3 $end -$upscope $end -$scope module TwoMux $end -$var wire 1 %H S $end -$var wire 1 &H in0 $end -$var wire 1 'H in1 $end -$var wire 1 (H nS $end -$var wire 1 )H out0 $end -$var wire 1 *H out1 $end -$var wire 1 +H outfinal $end -$upscope $end -$upscope $end -$scope begin muxbits[22] $end -$scope module ZeroMux $end -$var wire 1 ,H S0 $end -$var wire 1 -H S1 $end -$var wire 1 .H in0 $end -$var wire 1 /H in1 $end -$var wire 1 0H in2 $end -$var wire 1 1H in3 $end -$var wire 1 2H nS0 $end -$var wire 1 3H nS1 $end -$var wire 1 4H out $end -$var wire 1 5H out0 $end -$var wire 1 6H out1 $end -$var wire 1 7H out2 $end -$var wire 1 8H out3 $end -$upscope $end -$scope module OneMux $end -$var wire 1 9H S0 $end -$var wire 1 :H S1 $end -$var wire 1 ;H in0 $end -$var wire 1 H in3 $end -$var wire 1 ?H nS0 $end -$var wire 1 @H nS1 $end -$var wire 1 AH out $end -$var wire 1 BH out0 $end -$var wire 1 CH out1 $end -$var wire 1 DH out2 $end -$var wire 1 EH out3 $end -$upscope $end -$scope module TwoMux $end -$var wire 1 FH S $end -$var wire 1 GH in0 $end -$var wire 1 HH in1 $end -$var wire 1 IH nS $end -$var wire 1 JH out0 $end -$var wire 1 KH out1 $end -$var wire 1 LH outfinal $end -$upscope $end -$upscope $end -$scope begin muxbits[23] $end -$scope module ZeroMux $end -$var wire 1 MH S0 $end -$var wire 1 NH S1 $end -$var wire 1 OH in0 $end -$var wire 1 PH in1 $end -$var wire 1 QH in2 $end -$var wire 1 RH in3 $end -$var wire 1 SH nS0 $end -$var wire 1 TH nS1 $end -$var wire 1 UH out $end -$var wire 1 VH out0 $end -$var wire 1 WH out1 $end -$var wire 1 XH out2 $end -$var wire 1 YH out3 $end -$upscope $end -$scope module OneMux $end -$var wire 1 ZH S0 $end -$var wire 1 [H S1 $end -$var wire 1 \H in0 $end -$var wire 1 ]H in1 $end -$var wire 1 ^H in2 $end -$var wire 1 _H in3 $end -$var wire 1 `H nS0 $end -$var wire 1 aH nS1 $end -$var wire 1 bH out $end -$var wire 1 cH out0 $end -$var wire 1 dH out1 $end -$var wire 1 eH out2 $end -$var wire 1 fH out3 $end -$upscope $end -$scope module TwoMux $end -$var wire 1 gH S $end -$var wire 1 hH in0 $end -$var wire 1 iH in1 $end -$var wire 1 jH nS $end -$var wire 1 kH out0 $end -$var wire 1 lH out1 $end -$var wire 1 mH outfinal $end -$upscope $end -$upscope $end -$scope begin muxbits[24] $end -$scope module ZeroMux $end -$var wire 1 nH S0 $end -$var wire 1 oH S1 $end -$var wire 1 pH in0 $end -$var wire 1 qH in1 $end -$var wire 1 rH in2 $end -$var wire 1 sH in3 $end -$var wire 1 tH nS0 $end -$var wire 1 uH nS1 $end -$var wire 1 vH out $end -$var wire 1 wH out0 $end -$var wire 1 xH out1 $end -$var wire 1 yH out2 $end -$var wire 1 zH out3 $end -$upscope $end -$scope module OneMux $end -$var wire 1 {H S0 $end -$var wire 1 |H S1 $end -$var wire 1 }H in0 $end -$var wire 1 ~H in1 $end -$var wire 1 !I in2 $end -$var wire 1 "I in3 $end -$var wire 1 #I nS0 $end -$var wire 1 $I nS1 $end -$var wire 1 %I out $end -$var wire 1 &I out0 $end -$var wire 1 'I out1 $end -$var wire 1 (I out2 $end -$var wire 1 )I out3 $end -$upscope $end -$scope module TwoMux $end -$var wire 1 *I S $end -$var wire 1 +I in0 $end -$var wire 1 ,I in1 $end -$var wire 1 -I nS $end -$var wire 1 .I out0 $end -$var wire 1 /I out1 $end -$var wire 1 0I outfinal $end -$upscope $end -$upscope $end -$scope begin muxbits[25] $end -$scope module ZeroMux $end -$var wire 1 1I S0 $end -$var wire 1 2I S1 $end -$var wire 1 3I in0 $end -$var wire 1 4I in1 $end -$var wire 1 5I in2 $end -$var wire 1 6I in3 $end -$var wire 1 7I nS0 $end -$var wire 1 8I nS1 $end -$var wire 1 9I out $end -$var wire 1 :I out0 $end -$var wire 1 ;I out1 $end -$var wire 1 I S0 $end -$var wire 1 ?I S1 $end -$var wire 1 @I in0 $end -$var wire 1 AI in1 $end -$var wire 1 BI in2 $end -$var wire 1 CI in3 $end -$var wire 1 DI nS0 $end -$var wire 1 EI nS1 $end -$var wire 1 FI out $end -$var wire 1 GI out0 $end -$var wire 1 HI out1 $end -$var wire 1 II out2 $end -$var wire 1 JI out3 $end -$upscope $end -$scope module TwoMux $end -$var wire 1 KI S $end -$var wire 1 LI in0 $end -$var wire 1 MI in1 $end -$var wire 1 NI nS $end -$var wire 1 OI out0 $end -$var wire 1 PI out1 $end -$var wire 1 QI outfinal $end -$upscope $end -$upscope $end -$scope begin muxbits[26] $end -$scope module ZeroMux $end -$var wire 1 RI S0 $end -$var wire 1 SI S1 $end -$var wire 1 TI in0 $end -$var wire 1 UI in1 $end -$var wire 1 VI in2 $end -$var wire 1 WI in3 $end -$var wire 1 XI nS0 $end -$var wire 1 YI nS1 $end -$var wire 1 ZI out $end -$var wire 1 [I out0 $end -$var wire 1 \I out1 $end -$var wire 1 ]I out2 $end -$var wire 1 ^I out3 $end -$upscope $end -$scope module OneMux $end -$var wire 1 _I S0 $end -$var wire 1 `I S1 $end -$var wire 1 aI in0 $end -$var wire 1 bI in1 $end -$var wire 1 cI in2 $end -$var wire 1 dI in3 $end -$var wire 1 eI nS0 $end -$var wire 1 fI nS1 $end -$var wire 1 gI out $end -$var wire 1 hI out0 $end -$var wire 1 iI out1 $end -$var wire 1 jI out2 $end -$var wire 1 kI out3 $end -$upscope $end -$scope module TwoMux $end -$var wire 1 lI S $end -$var wire 1 mI in0 $end -$var wire 1 nI in1 $end -$var wire 1 oI nS $end -$var wire 1 pI out0 $end -$var wire 1 qI out1 $end -$var wire 1 rI outfinal $end -$upscope $end -$upscope $end -$scope begin muxbits[27] $end -$scope module ZeroMux $end -$var wire 1 sI S0 $end -$var wire 1 tI S1 $end -$var wire 1 uI in0 $end -$var wire 1 vI in1 $end -$var wire 1 wI in2 $end -$var wire 1 xI in3 $end -$var wire 1 yI nS0 $end -$var wire 1 zI nS1 $end -$var wire 1 {I out $end -$var wire 1 |I out0 $end -$var wire 1 }I out1 $end -$var wire 1 ~I out2 $end -$var wire 1 !J out3 $end -$upscope $end -$scope module OneMux $end -$var wire 1 "J S0 $end -$var wire 1 #J S1 $end -$var wire 1 $J in0 $end -$var wire 1 %J in1 $end -$var wire 1 &J in2 $end -$var wire 1 'J in3 $end -$var wire 1 (J nS0 $end -$var wire 1 )J nS1 $end -$var wire 1 *J out $end -$var wire 1 +J out0 $end -$var wire 1 ,J out1 $end -$var wire 1 -J out2 $end -$var wire 1 .J out3 $end -$upscope $end -$scope module TwoMux $end -$var wire 1 /J S $end -$var wire 1 0J in0 $end -$var wire 1 1J in1 $end -$var wire 1 2J nS $end -$var wire 1 3J out0 $end -$var wire 1 4J out1 $end -$var wire 1 5J outfinal $end -$upscope $end -$upscope $end -$scope begin muxbits[28] $end -$scope module ZeroMux $end -$var wire 1 6J S0 $end -$var wire 1 7J S1 $end -$var wire 1 8J in0 $end -$var wire 1 9J in1 $end -$var wire 1 :J in2 $end -$var wire 1 ;J in3 $end -$var wire 1 J out $end -$var wire 1 ?J out0 $end -$var wire 1 @J out1 $end -$var wire 1 AJ out2 $end -$var wire 1 BJ out3 $end -$upscope $end -$scope module OneMux $end -$var wire 1 CJ S0 $end -$var wire 1 DJ S1 $end -$var wire 1 EJ in0 $end -$var wire 1 FJ in1 $end -$var wire 1 GJ in2 $end -$var wire 1 HJ in3 $end -$var wire 1 IJ nS0 $end -$var wire 1 JJ nS1 $end -$var wire 1 KJ out $end -$var wire 1 LJ out0 $end -$var wire 1 MJ out1 $end -$var wire 1 NJ out2 $end -$var wire 1 OJ out3 $end -$upscope $end -$scope module TwoMux $end -$var wire 1 PJ S $end -$var wire 1 QJ in0 $end -$var wire 1 RJ in1 $end -$var wire 1 SJ nS $end -$var wire 1 TJ out0 $end -$var wire 1 UJ out1 $end -$var wire 1 VJ outfinal $end -$upscope $end -$upscope $end -$scope begin muxbits[29] $end -$scope module ZeroMux $end -$var wire 1 WJ S0 $end -$var wire 1 XJ S1 $end -$var wire 1 YJ in0 $end -$var wire 1 ZJ in1 $end -$var wire 1 [J in2 $end -$var wire 1 \J in3 $end -$var wire 1 ]J nS0 $end -$var wire 1 ^J nS1 $end -$var wire 1 _J out $end -$var wire 1 `J out0 $end -$var wire 1 aJ out1 $end -$var wire 1 bJ out2 $end -$var wire 1 cJ out3 $end -$upscope $end -$scope module OneMux $end -$var wire 1 dJ S0 $end -$var wire 1 eJ S1 $end -$var wire 1 fJ in0 $end -$var wire 1 gJ in1 $end -$var wire 1 hJ in2 $end -$var wire 1 iJ in3 $end -$var wire 1 jJ nS0 $end -$var wire 1 kJ nS1 $end -$var wire 1 lJ out $end -$var wire 1 mJ out0 $end -$var wire 1 nJ out1 $end -$var wire 1 oJ out2 $end -$var wire 1 pJ out3 $end -$upscope $end -$scope module TwoMux $end -$var wire 1 qJ S $end -$var wire 1 rJ in0 $end -$var wire 1 sJ in1 $end -$var wire 1 tJ nS $end -$var wire 1 uJ out0 $end -$var wire 1 vJ out1 $end -$var wire 1 wJ outfinal $end -$upscope $end -$upscope $end -$scope begin muxbits[30] $end -$scope module ZeroMux $end -$var wire 1 xJ S0 $end -$var wire 1 yJ S1 $end -$var wire 1 zJ in0 $end -$var wire 1 {J in1 $end -$var wire 1 |J in2 $end -$var wire 1 }J in3 $end -$var wire 1 ~J nS0 $end -$var wire 1 !K nS1 $end -$var wire 1 "K out $end -$var wire 1 #K out0 $end -$var wire 1 $K out1 $end -$var wire 1 %K out2 $end -$var wire 1 &K out3 $end -$upscope $end -$scope module OneMux $end -$var wire 1 'K S0 $end -$var wire 1 (K S1 $end -$var wire 1 )K in0 $end -$var wire 1 *K in1 $end -$var wire 1 +K in2 $end -$var wire 1 ,K in3 $end -$var wire 1 -K nS0 $end -$var wire 1 .K nS1 $end -$var wire 1 /K out $end -$var wire 1 0K out0 $end -$var wire 1 1K out1 $end -$var wire 1 2K out2 $end -$var wire 1 3K out3 $end -$upscope $end -$scope module TwoMux $end -$var wire 1 4K S $end -$var wire 1 5K in0 $end -$var wire 1 6K in1 $end -$var wire 1 7K nS $end -$var wire 1 8K out0 $end -$var wire 1 9K out1 $end -$var wire 1 :K outfinal $end -$upscope $end -$upscope $end -$scope begin muxbits[31] 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-1.I -0w% -b11111100111111111111111111111111 2 -0Z5 -b11111100111111111111111111111111 s0 -1p% -1S5 -b11000000000000000000000000 ! -b11000000000000000000000000 0 -b11000000000000000000000000 d0 -b11000000000000000000000000 q0 -#61050000 -1v% -1Y5 -0pH -0qH -0sH -0=I -0kH -b11111111100000000000000000000000 ' -b11111111100000000000000000000000 l0 -1f% -b11111101111111111111111111111111 2 -1I5 -b11111101111111111111111111111111 s0 -0_% -0B5 -b10000000000000000000000000 ! -b10000000000000000000000000 0 -b10000000000000000000000000 d0 -b10000000000000000000000000 q0 -#61060000 -1LI -1zH -19I -b11000000000000000000000000 g0 -0'& -0h5 -10I -b1100000000000000000000000 $ -b1100000000000000000000000 j0 -#61070000 -0+I -0vH -b10000000000000000000000000 g0 -1t% -1W5 -0mH -b1000000000000000000000000 $ -b1000000000000000000000000 j0 -#61080000 -0:& -0{5 -1TI -1UI -1WI -1OI -0*& -b11111001111111111111111111111111 2 -0k5 -b11111001111111111111111111111111 s0 -1#& -1d5 -b110000000000000000000000000 ! -b110000000000000000000000000 0 -b110000000000000000000000000 d0 -b110000000000000000000000000 q0 -#61090000 -1)& -1j5 -03I -04I -06I -0^I -0.I -b11111111000000000000000000000000 ' -b11111111000000000000000000000000 l0 -1w% -b11111011111111111111111111111111 2 -1Z5 -b11111011111111111111111111111111 s0 -0p% -0S5 -b100000000000000000000000000 ! -b100000000000000000000000000 0 -b100000000000000000000000000 d0 -b100000000000000000000000000 q0 -#61100000 -1mI -1=I -1ZI -b110000000000000000000000000 g0 -08& -0y5 -1QI -b11000000000000000000000000 $ -b11000000000000000000000000 j0 -#61110000 -0LI -09I -b100000000000000000000000000 g0 -1'& -1h5 -00I -b10000000000000000000000000 $ -b10000000000000000000000000 j0 -#61120000 -0K& -0.6 -1uI -1vI -1xI -1pI -0;& -b11110011111111111111111111111111 2 -0|5 -b11110011111111111111111111111111 s0 -14& -1u5 -b1100000000000000000000000000 ! -b1100000000000000000000000000 0 -b1100000000000000000000000000 d0 -b1100000000000000000000000000 q0 -#61130000 -1:& -1{5 -0TI -0UI -0WI -0!J -0OI -b11111110000000000000000000000000 ' -b11111110000000000000000000000000 l0 -1*& -b11110111111111111111111111111111 2 -1k5 -b11110111111111111111111111111111 s0 -0#& -0d5 -b1000000000000000000000000000 ! -b1000000000000000000000000000 0 -b1000000000000000000000000000 d0 -b1000000000000000000000000000 q0 -#61140000 -10J -1^I -1{I -b1100000000000000000000000000 g0 -0I& -0,6 -1rI -b110000000000000000000000000 $ -b110000000000000000000000000 j0 -#61150000 -0mI -0ZI -b1000000000000000000000000000 g0 -18& -1y5 -0QI -b100000000000000000000000000 $ -b100000000000000000000000000 j0 -#61160000 -0\& -0?6 -18J -19J -1;J -13J -0L& -b11100111111111111111111111111111 2 -0/6 -b11100111111111111111111111111111 s0 -1E& -1(6 -b11000000000000000000000000000 ! -b11000000000000000000000000000 0 -b11000000000000000000000000000 d0 -b11000000000000000000000000000 q0 -#61170000 -1K& -1.6 -0uI -0vI -0xI -0BJ -0pI -b11111100000000000000000000000000 ' -b11111100000000000000000000000000 l0 -1;& -b11101111111111111111111111111111 2 -1|5 -b11101111111111111111111111111111 s0 -04& -0u5 -b10000000000000000000000000000 ! -b10000000000000000000000000000 0 -b10000000000000000000000000000 d0 -b10000000000000000000000000000 q0 -#61180000 -1QJ -1!J -1>J -b11000000000000000000000000000 g0 -0Z& -0=6 -15J -b1100000000000000000000000000 $ -b1100000000000000000000000000 j0 -#61190000 -00J -0{I -b10000000000000000000000000000 g0 -1I& -1,6 -0rI -b1000000000000000000000000000 $ -b1000000000000000000000000000 j0 -#61200000 -0m& -0P6 -1YJ -1ZJ -1\J -1TJ -0]& -b11001111111111111111111111111111 2 -0@6 -b11001111111111111111111111111111 s0 -1V& -196 -b110000000000000000000000000000 ! -b110000000000000000000000000000 0 -b110000000000000000000000000000 d0 -b110000000000000000000000000000 q0 -#61210000 -1\& -1?6 -08J -09J -0;J -0cJ -03J -b11111000000000000000000000000000 ' -b11111000000000000000000000000000 l0 -1L& -b11011111111111111111111111111111 2 -1/6 -b11011111111111111111111111111111 s0 -0E& -0(6 -b100000000000000000000000000000 ! -b100000000000000000000000000000 0 -b100000000000000000000000000000 d0 -b100000000000000000000000000000 q0 -#61220000 -1rJ -1BJ -1_J -b110000000000000000000000000000 g0 -0k& -0N6 -1VJ -b11000000000000000000000000000 $ -b11000000000000000000000000000 j0 -#61230000 -0QJ -0>J -b100000000000000000000000000000 g0 -1Z& -1=6 -05J -b10000000000000000000000000000 $ -b10000000000000000000000000000 j0 -#61240000 -0~& -0a6 -1zJ -1{J -1}J -1uJ -0n& -b10011111111111111111111111111111 2 -0Q6 -b10011111111111111111111111111111 s0 -1g& -1J6 -b1100000000000000000000000000000 ! -b1100000000000000000000000000000 0 -b1100000000000000000000000000000 d0 -b1100000000000000000000000000000 q0 -#61250000 -1m& -1P6 -0YJ -0ZJ -0\J -0&K -0TJ -b11110000000000000000000000000000 ' -b11110000000000000000000000000000 l0 -1]& -b10111111111111111111111111111111 2 -1@6 -b10111111111111111111111111111111 s0 -0V& -096 -b1000000000000000000000000000000 ! -b1000000000000000000000000000000 0 -b1000000000000000000000000000000 d0 -b1000000000000000000000000000000 q0 -#61260000 -15K -1cJ -1"K -b1100000000000000000000000000000 g0 -0|& -0_6 -1wJ -b110000000000000000000000000000 $ -b110000000000000000000000000000 j0 -#61270000 -0rJ -0_J -b1000000000000000000000000000000 g0 -1k& -1N6 -0VJ -b100000000000000000000000000000 $ -b100000000000000000000000000000 j0 -#61280000 -1=K -1>K -1@K -18K -0!' -b111111111111111111111111111111 2 -0b6 -b111111111111111111111111111111 s0 -1x& -1[6 -b11000000000000000000000000000000 ! -b11000000000000000000000000000000 0 -b11000000000000000000000000000000 d0 -b11000000000000000000000000000000 q0 -1) -#61290000 -1~& -1a6 -0zJ -0{J -0}J -0: -0GK -0{0 -0; -0|0 -0uJ -b11100000000000000000000000000000 ' -b11100000000000000000000000000000 l0 -1n& -b1111111111111111111111111111111 2 -1Q6 -b1111111111111111111111111111111 s0 -0g& -0J6 -b10000000000000000000000000000000 ! -b10000000000000000000000000000000 0 -b10000000000000000000000000000000 d0 -b10000000000000000000000000000000 q0 -#61300000 -1VK -1&K -1CK -b11000000000000000000000000000000 g0 +b1000 i# +#60180000 0( -1:K -b1100000000000000000000000000000 $ -b1100000000000000000000000000000 j0 -#61310000 -05K -0"K -b10000000000000000000000000000000 g0 -1|& -1_6 -0wJ -b1000000000000000000000000000000 $ -b1000000000000000000000000000000 j0 -#61320000 -1YK -#61330000 -0=K -0>K -0@K -08K -b11000000000000000000000000000000 ' -b11000000000000000000000000000000 l0 -1!' -b11111111111111111111111111111111 2 -1b6 -b11111111111111111111111111111111 s0 -0x& -0[6 -b0 ! -b0 0 -b0 d0 -b0 q0 -#61340000 -1: -1GK -1{0 -1[K -b11000000000000000000000000000000 $ -b11000000000000000000000000000000 j0 -#61350000 -0VK -0CK -b0 g0 +15 +1j# +#60190000 +1," +1a$ +#60200000 +18 +1m# +#60210000 +07" +0l$ +1/" +b1111 2 +1d$ +b1111 g# +0(" +b0 4 +0]$ +b0 i# +#60220000 +1& +#60230000 1( -0:K -b10000000000000000000000000000000 $ -b10000000000000000000000000000000 j0 -#61360000 -14 -1u0 -#61370000 -0YK -b10000000000000000000000000000000 ' -b10000000000000000000000000000000 l0 -#61380000 -17 -1x0 -#61390000 -0[K -b0 $ -b0 j0 +#60270000 0) -#61400000 -1; -1|0 -1& -#61410000 -b0 ' -b0 l0 -04 -0u0 -#61420000 -1o0 -#61430000 -07 -0x0 -#61440000 -1" -#61450000 +#60280000 +1= +1r# +#60290000 +05 +0j# +#60310000 +08 +0m# +#60330000 0& +#61000000 diff --git a/SmallALU.vcd b/SmallALU.vcd index c81aaaf..20369c7 100644 --- a/SmallALU.vcd +++ b/SmallALU.vcd @@ -1,5 +1,5 @@ $date - Tue Oct 10 14:48:25 2017 + Tue Oct 10 14:53:02 2017 $end $version Icarus Verilog diff --git a/alu.v b/alu.v index aa7cf83..415432c 100644 --- a/alu.v +++ b/alu.v @@ -158,7 +158,7 @@ input [size-1:0] A, input [size-1:0] B, input[2:0] Command ); - parameter size = 32; // set the parameter size to whatever length you want + parameter size = 4; // set the parameter size to whatever length you want wire AnandB; wire AandB; @@ -181,7 +181,7 @@ input [size-1:0] A, input [size-1:0] B, input[2:0] Command ); - parameter size = 32; // set the parameter size to whatever length you want + parameter size = 4; // set the parameter size to whatever length you want wire AnorB; wire AorB; wire AnandB; @@ -214,6 +214,8 @@ input [2:0] Command, input [size-1:0]carryin // we think this doesn't do anything but don't want to break everything ); wire [size-1:0] CarryoutWire; // this is used to internally connect each of the 32 bitslices + wire [size-1:0] NewVal; // this is used to internally connect each of the 32 bitslices + wire SLTon; wire nOF; wire nAddSubSLTSum; @@ -221,17 +223,39 @@ input [size-1:0]carryin // we think this doesn't do anything but don't want to wire Res0OF1; wire SLTflag0; wire SLTflag1; + wire nCmd2; - MiddleAddSubSLT attempt2(AddSubSLTSum[0], CarryoutWire[0], subtract[0], A[0], B[0], Command, subtract[0]); - + + + `NOT n0(nCmd2, Command[2]); + + //`AND subtractchoose(subtract, Command[0], nCmd2); + + `AND sltcheck0(SLTon, Command[0], Command[1], nCmd2); + MiddleAddSubSLT attempt2(NewVal[0], CarryoutWire[0], subtract[0], A[0], B[0], Command, subtract[0]); + TwoInMux setSLTres(AddSubSLTSum[0], SLTon, NewVal[0], 0); + + + + genvar i; - parameter size = 32; + parameter size = 4; generate for (i=1; i; -L_0x249f5b0/d .functor AND 1, L_0x249f6f0, L_0x2492a20, C4<1>, C4<1>; -L_0x249f5b0 .delay (20000,20000,20000) L_0x249f5b0/d; -L_0x2492b10/d .functor NOT 1, L_0x2492c00, C4<0>, C4<0>, C4<0>; -L_0x2492b10 .delay (10000,10000,10000) L_0x2492b10/d; -L_0x2492ca0/d .functor AND 1, L_0x2492b10, L_0x2492b10, C4<1>, C4<1>; -L_0x2492ca0 .delay (20000,20000,20000) L_0x2492ca0/d; -v0x2462f10_0 .net "A", 31 0, C4; 0 drivers -RS_0x7fd6f9610aa8/0/0 .resolv tri, L_0x2478890, L_0x24bb770, L_0x24bcb70, L_0x24be000; -RS_0x7fd6f9610aa8/0/4 .resolv tri, L_0x24bf4a0, L_0x24c0a90, L_0x24c1fd0, L_0x24c3550; -RS_0x7fd6f9610aa8/0/8 .resolv tri, L_0x24c4b60, L_0x24c6070, L_0x24c7580, L_0x24c8a90; -RS_0x7fd6f9610aa8/0/12 .resolv tri, L_0x24c9f90, L_0x24cb6b0, L_0x24ccbc0, L_0x24ce1d0; -RS_0x7fd6f9610aa8/0/16 .resolv tri, L_0x24cf800, L_0x24d0c70, L_0x24d2120, L_0x24d34f0; -RS_0x7fd6f9610aa8/0/20 .resolv tri, L_0x24d4930, L_0x24d5e40, L_0x24d7200, L_0x24d8650; -RS_0x7fd6f9610aa8/0/24 .resolv tri, L_0x24d9b40, L_0x24db020, L_0x24dc500, L_0x24dda00; -RS_0x7fd6f9610aa8/0/28 .resolv tri, L_0x24deef0, L_0x24e07c0, L_0x24e1cb0, L_0x24e33a0; -RS_0x7fd6f9610aa8/1/0 .resolv tri, RS_0x7fd6f9610aa8/0/0, RS_0x7fd6f9610aa8/0/4, RS_0x7fd6f9610aa8/0/8, RS_0x7fd6f9610aa8/0/12; -RS_0x7fd6f9610aa8/1/4 .resolv tri, RS_0x7fd6f9610aa8/0/16, RS_0x7fd6f9610aa8/0/20, RS_0x7fd6f9610aa8/0/24, RS_0x7fd6f9610aa8/0/28; -RS_0x7fd6f9610aa8 .resolv tri, RS_0x7fd6f9610aa8/1/0, RS_0x7fd6f9610aa8/1/4, C4, C4; -v0x2463100_0 .net8 "AddSubSLTSum", 31 0, RS_0x7fd6f9610aa8; 32 drivers -v0x2463180_0 .net "AllZeros", 0 0, L_0x2492ca0; 1 drivers -RS_0x7fd6f9609e78/0/0 .resolv tri, L_0x24e5dd0, L_0x24e6b80, L_0x24e7610, L_0x24e8070; -RS_0x7fd6f9609e78/0/4 .resolv tri, L_0x24e8ae0, L_0x24e95b0, L_0x24ea0b0, L_0x24eab10; -RS_0x7fd6f9609e78/0/8 .resolv tri, L_0x24eb590, L_0x24ec000, L_0x24eca70, L_0x24ed4e0; -RS_0x7fd6f9609e78/0/12 .resolv tri, L_0x24edf60, L_0x24ee9c0, L_0x24ef430, L_0x24efea0; -RS_0x7fd6f9609e78/0/16 .resolv tri, L_0x24f0920, L_0x24f1380, L_0x24f1e00, L_0x24f2860; -RS_0x7fd6f9609e78/0/20 .resolv tri, L_0x24f32d0, L_0x24f3d40, L_0x24f47c0, L_0x24f5220; -RS_0x7fd6f9609e78/0/24 .resolv tri, L_0x24f5c90, L_0x24f66f0, L_0x24f7160, L_0x24f7bd0; -RS_0x7fd6f9609e78/0/28 .resolv tri, L_0x24f8650, L_0x24f97b0, L_0x24fa160, L_0x24fab10; -RS_0x7fd6f9609e78/1/0 .resolv tri, RS_0x7fd6f9609e78/0/0, RS_0x7fd6f9609e78/0/4, RS_0x7fd6f9609e78/0/8, RS_0x7fd6f9609e78/0/12; -RS_0x7fd6f9609e78/1/4 .resolv tri, RS_0x7fd6f9609e78/0/16, RS_0x7fd6f9609e78/0/20, RS_0x7fd6f9609e78/0/24, RS_0x7fd6f9609e78/0/28; -RS_0x7fd6f9609e78 .resolv tri, RS_0x7fd6f9609e78/1/0, RS_0x7fd6f9609e78/1/4, C4, C4; -v0x2463200_0 .net8 "AndNandOut", 31 0, RS_0x7fd6f9609e78; 32 drivers -v0x24632b0_0 .net "B", 31 0, C4; 0 drivers -RS_0x7fd6f9610ec8/0/0 .resolv tri, L_0x2469c90, L_0x246c730, L_0x246f0d0, L_0x2471a70; -RS_0x7fd6f9610ec8/0/4 .resolv tri, L_0x2474510, L_0x2476df0, L_0x2479b60, L_0x247c1d0; -RS_0x7fd6f9610ec8/0/8 .resolv tri, L_0x247ee10, L_0x2481480, L_0x2483b10, L_0x2486610; -RS_0x7fd6f9610ec8/0/12 .resolv tri, L_0x2488d20, L_0x248b450, L_0x248dad0, L_0x24900b0; -RS_0x7fd6f9610ec8/0/16 .resolv tri, L_0x2491ea0, L_0x2495870, L_0x2497340, L_0x2499800; -RS_0x7fd6f9610ec8/0/20 .resolv tri, L_0x249ced0, L_0x249e890, L_0x24a1700, L_0x24a3ed0; -RS_0x7fd6f9610ec8/0/24 .resolv tri, L_0x24a7600, L_0x24a9d40, L_0x24ac500, L_0x24aec80; -RS_0x7fd6f9610ec8/0/28 .resolv tri, L_0x24b1470, L_0x24b2380, L_0x24b4ea0, L_0x2520e60; -RS_0x7fd6f9610ec8/1/0 .resolv tri, RS_0x7fd6f9610ec8/0/0, RS_0x7fd6f9610ec8/0/4, RS_0x7fd6f9610ec8/0/8, RS_0x7fd6f9610ec8/0/12; -RS_0x7fd6f9610ec8/1/4 .resolv tri, RS_0x7fd6f9610ec8/0/16, RS_0x7fd6f9610ec8/0/20, RS_0x7fd6f9610ec8/0/24, RS_0x7fd6f9610ec8/0/28; -RS_0x7fd6f9610ec8 .resolv tri, RS_0x7fd6f9610ec8/1/0, RS_0x7fd6f9610ec8/1/4, C4, C4; -v0x2463330_0 .net8 "Cmd0Start", 31 0, RS_0x7fd6f9610ec8; 32 drivers -RS_0x7fd6f9610ef8/0/0 .resolv tri, L_0x246ac00, L_0x246d620, L_0x2470080, L_0x2472930; -RS_0x7fd6f9610ef8/0/4 .resolv tri, L_0x24753d0, L_0x2477bc0, L_0x247a920, L_0x247cfd0; -RS_0x7fd6f9610ef8/0/8 .resolv tri, L_0x247fbd0, L_0x2482260, L_0x2484260, L_0x2487410; -RS_0x7fd6f9610ef8/0/12 .resolv tri, L_0x2489b50, L_0x248c220, L_0x248e870, L_0x2490e80; -RS_0x7fd6f9610ef8/0/16 .resolv tri, L_0x2493f70, L_0x24966d0, L_0x2498e70, L_0x249a810; -RS_0x7fd6f9610ef8/0/20 .resolv tri, L_0x249e180, L_0x24a0d00, L_0x24a3540, L_0x24a5cc0; -RS_0x7fd6f9610ef8/0/24 .resolv tri, L_0x24a6b00, L_0x24a96e0, L_0x24abc40, L_0x24ae790; -RS_0x7fd6f9610ef8/0/28 .resolv tri, L_0x24b0cd0, L_0x24b36a0, L_0x24b72a0, L_0x24b7ff0; -RS_0x7fd6f9610ef8/1/0 .resolv tri, RS_0x7fd6f9610ef8/0/0, RS_0x7fd6f9610ef8/0/4, RS_0x7fd6f9610ef8/0/8, RS_0x7fd6f9610ef8/0/12; -RS_0x7fd6f9610ef8/1/4 .resolv tri, RS_0x7fd6f9610ef8/0/16, RS_0x7fd6f9610ef8/0/20, RS_0x7fd6f9610ef8/0/24, RS_0x7fd6f9610ef8/0/28; -RS_0x7fd6f9610ef8 .resolv tri, RS_0x7fd6f9610ef8/1/0, RS_0x7fd6f9610ef8/1/4, C4, C4; -v0x24633b0_0 .net8 "Cmd1Start", 31 0, RS_0x7fd6f9610ef8; 32 drivers -v0x2463430_0 .net "Command", 2 0, C4; 0 drivers -RS_0x7fd6f9610f28/0/0 .resolv tri, L_0x246b680, L_0x246e0f0, L_0x2470b40, L_0x2473480; -RS_0x7fd6f9610f28/0/4 .resolv tri, L_0x2475a80, L_0x243e8f0, L_0x247b420, L_0x247db60; -RS_0x7fd6f9610f28/0/8 .resolv tri, L_0x2480640, L_0x2482cc0, L_0x24857b0, L_0x2487e70; -RS_0x7fd6f9610f28/0/12 .resolv tri, L_0x248a5e0, L_0x248ccf0, L_0x248f2c0, L_0x2491af0; -RS_0x7fd6f9610f28/0/16 .resolv tri, L_0x2493760, L_0x2496130, L_0x2498b00, L_0x249b230; -RS_0x7fd6f9610f28/0/20 .resolv tri, L_0x2484710, L_0x24a0020, L_0x24a2760, L_0x24a4df0; -RS_0x7fd6f9610f28/0/24 .resolv tri, L_0x24a7d00, L_0x24aa3e0, L_0x24aca40, L_0x24af1e0; -RS_0x7fd6f9610f28/0/28 .resolv tri, L_0x24b2d30, L_0x24b40d0, L_0x24b60c0, L_0x249f1f0; -RS_0x7fd6f9610f28/1/0 .resolv tri, RS_0x7fd6f9610f28/0/0, RS_0x7fd6f9610f28/0/4, RS_0x7fd6f9610f28/0/8, RS_0x7fd6f9610f28/0/12; -RS_0x7fd6f9610f28/1/4 .resolv tri, RS_0x7fd6f9610f28/0/16, RS_0x7fd6f9610f28/0/20, RS_0x7fd6f9610f28/0/24, RS_0x7fd6f9610f28/0/28; -RS_0x7fd6f9610f28 .resolv tri, RS_0x7fd6f9610f28/1/0, RS_0x7fd6f9610f28/1/4, C4, C4; -v0x24634b0_0 .net8 "OneBitFinalOut", 31 0, RS_0x7fd6f9610f28; 32 drivers -RS_0x7fd6f9606848/0/0 .resolv tri, L_0x24fbcf0, L_0x24fcdf0, L_0x24fdf50, L_0x24ff200; -RS_0x7fd6f9606848/0/4 .resolv tri, L_0x25003e0, L_0x2501740, L_0x2502ad0, L_0x2503dc0; -RS_0x7fd6f9606848/0/8 .resolv tri, L_0x25050d0, L_0x25063d0, L_0x25076d0, L_0x25089c0; -RS_0x7fd6f9606848/0/12 .resolv tri, L_0x2509ce0, L_0x250afe0, L_0x250c2e0, L_0x250d5d0; -RS_0x7fd6f9606848/0/16 .resolv tri, L_0x250e8e0, L_0x250fbd0, L_0x2510ed0, L_0x25121d0; -RS_0x7fd6f9606848/0/20 .resolv tri, L_0x25134e0, L_0x25147d0, L_0x2515ad0, L_0x2516dd0; -RS_0x7fd6f9606848/0/24 .resolv tri, L_0x25180d0, L_0x25193e0, L_0x251a6e0, L_0x251b9d0; -RS_0x7fd6f9606848/0/28 .resolv tri, L_0x251cd50, L_0x251e060, L_0x251f370, L_0x2520520; -RS_0x7fd6f9606848/1/0 .resolv tri, RS_0x7fd6f9606848/0/0, RS_0x7fd6f9606848/0/4, RS_0x7fd6f9606848/0/8, RS_0x7fd6f9606848/0/12; -RS_0x7fd6f9606848/1/4 .resolv tri, RS_0x7fd6f9606848/0/16, RS_0x7fd6f9606848/0/20, RS_0x7fd6f9606848/0/24, RS_0x7fd6f9606848/0/28; -RS_0x7fd6f9606848 .resolv tri, RS_0x7fd6f9606848/1/0, RS_0x7fd6f9606848/1/4, C4, C4; -v0x2463550_0 .net8 "OrNorXorOut", 31 0, RS_0x7fd6f9606848; 32 drivers -v0x24635d0_0 .net "SLTflag", 0 0, L_0x24e4440; 1 drivers -RS_0x7fd6f9610f58/0/0 .resolv tri, L_0x246bb70, L_0x246e530, L_0x2470c80, L_0x2473630; -RS_0x7fd6f9610f58/0/4 .resolv tri, L_0x2475dd0, L_0x243ec10, L_0x247b190, L_0x2473520; -RS_0x7fd6f9610f58/0/8 .resolv tri, L_0x247fe50, L_0x24826b0, L_0x2485230, L_0x2487860; -RS_0x7fd6f9610f58/0/12 .resolv tri, L_0x2489dd0, L_0x248c670, L_0x248eaf0, L_0x2491a00; -RS_0x7fd6f9610f58/0/16 .resolv tri, L_0x2494010, L_0x2497460, L_0x2499b80, L_0x249b550; -RS_0x7fd6f9610f58/0/20 .resolv tri, L_0x249d8a0, L_0x24a0340, L_0x24a2a80, L_0x24a5110; -RS_0x7fd6f9610f58/0/24 .resolv tri, L_0x24a8020, L_0x24aa700, L_0x24acd60, L_0x24af500; -RS_0x7fd6f9610f58/0/28 .resolv tri, L_0x24b1820, L_0x24b4340, L_0x24b63e0, L_0x249f510; -RS_0x7fd6f9610f58/1/0 .resolv tri, RS_0x7fd6f9610f58/0/0, RS_0x7fd6f9610f58/0/4, RS_0x7fd6f9610f58/0/8, RS_0x7fd6f9610f58/0/12; -RS_0x7fd6f9610f58/1/4 .resolv tri, RS_0x7fd6f9610f58/0/16, RS_0x7fd6f9610f58/0/20, RS_0x7fd6f9610f58/0/24, RS_0x7fd6f9610f58/0/28; -RS_0x7fd6f9610f58 .resolv tri, RS_0x7fd6f9610f58/1/0, RS_0x7fd6f9610f58/1/4, C4, C4; -v0x2463680_0 .net8 "ZeroFlag", 31 0, RS_0x7fd6f9610f58; 32 drivers -v0x2463700_0 .net *"_s121", 0 0, L_0x2475e70; 1 drivers -v0x2463780_0 .net *"_s146", 0 0, L_0x243e4e0; 1 drivers -v0x24638a0_0 .net *"_s171", 0 0, L_0x247b230; 1 drivers -v0x2463940_0 .net *"_s196", 0 0, L_0x24735c0; 1 drivers -v0x2463800_0 .net *"_s21", 0 0, L_0x246b7c0; 1 drivers -v0x2463a90_0 .net *"_s221", 0 0, L_0x247fef0; 1 drivers -v0x2463bb0_0 .net *"_s246", 0 0, L_0x2482750; 1 drivers -v0x2463c30_0 .net *"_s271", 0 0, L_0x24852d0; 1 drivers -v0x2463b10_0 .net *"_s296", 0 0, L_0x2487900; 1 drivers -v0x2463d60_0 .net *"_s321", 0 0, L_0x2489e70; 1 drivers -v0x2463cb0_0 .net *"_s346", 0 0, L_0x248c710; 1 drivers -v0x2463ea0_0 .net *"_s371", 0 0, L_0x248eb90; 1 drivers -v0x2463e00_0 .net *"_s396", 0 0, L_0x247d420; 1 drivers -v0x2463ff0_0 .net *"_s421", 0 0, L_0x24940b0; 1 drivers -v0x2463f40_0 .net *"_s446", 0 0, L_0x24968a0; 1 drivers -v0x2464150_0 .net *"_s46", 0 0, L_0x246e3f0; 1 drivers -v0x2464090_0 .net *"_s471", 0 0, L_0x2499c20; 1 drivers -v0x24642c0_0 .net *"_s496", 0 0, L_0x249b5f0; 1 drivers -v0x24641d0_0 .net *"_s521", 0 0, L_0x249d940; 1 drivers -v0x2464440_0 .net *"_s546", 0 0, L_0x24a03e0; 1 drivers -v0x2464340_0 .net *"_s571", 0 0, L_0x24a2b20; 1 drivers -v0x24645d0_0 .net *"_s596", 0 0, L_0x24a51b0; 1 drivers -v0x24644c0_0 .net *"_s621", 0 0, L_0x24a80c0; 1 drivers -v0x2464770_0 .net *"_s646", 0 0, L_0x24aa7a0; 1 drivers -v0x2464650_0 .net *"_s671", 0 0, L_0x24ace00; 1 drivers -v0x24646f0_0 .net *"_s696", 0 0, L_0x24af5a0; 1 drivers -v0x2464930_0 .net *"_s71", 0 0, L_0x2470d20; 1 drivers -v0x24649b0_0 .net *"_s721", 0 0, L_0x24b18c0; 1 drivers -v0x24647f0_0 .net *"_s746", 0 0, L_0x24b43e0; 1 drivers -v0x2464890_0 .net *"_s771", 0 0, L_0x24b6480; 1 drivers -v0x2464b90_0 .net *"_s811", 0 0, L_0x249f5b0; 1 drivers -v0x2464c10_0 .net *"_s814", 0 0, L_0x249f6f0; 1 drivers -v0x2464a30_0 .net *"_s816", 0 0, L_0x2492a20; 1 drivers -v0x2464ad0_0 .net *"_s818", 0 0, L_0x2492c00; 1 drivers -v0x2464e10_0 .net *"_s96", 0 0, L_0x24736d0; 1 drivers -v0x2464e90_0 .net "carryin", 31 0, C4; 0 drivers -v0x2464cc0_0 .net "carryout", 0 0, L_0x24e21f0; 1 drivers -v0x2464d70_0 .net "overflow", 0 0, L_0x24e2410; 1 drivers -RS_0x7fd6f9610e68/0/0 .resolv tri, L_0x2478a70, L_0x24bb9a0, L_0x24bcdd0, L_0x24bd200; -RS_0x7fd6f9610e68/0/4 .resolv tri, L_0x24be680, L_0x24bfc00, L_0x24c1070, L_0x24c24a0; -RS_0x7fd6f9610e68/0/8 .resolv tri, L_0x24c3d70, L_0x24c50c0, L_0x24c6600, L_0x24c7b40; -RS_0x7fd6f9610e68/0/12 .resolv tri, L_0x24c8ff0, L_0x24ca5e0, L_0x24cbc60, L_0x24cd240; -RS_0x7fd6f9610e68/0/16 .resolv tri, L_0x24ceb60, L_0x24cfdb0, L_0x24d1250, L_0x24d2300; -RS_0x7fd6f9610e68/0/20 .resolv tri, L_0x24d36d0, L_0x24d4b10, L_0x24d6020, L_0x24d73e0; -RS_0x7fd6f9610e68/0/24 .resolv tri, L_0x24d8830, L_0x24d9d20, L_0x24db200, L_0x24dc6e0; -RS_0x7fd6f9610e68/0/28 .resolv tri, L_0x24ddbe0, L_0x24dfa40, L_0x24e09a0, L_0x24e1e90; -RS_0x7fd6f9610e68/1/0 .resolv tri, RS_0x7fd6f9610e68/0/0, RS_0x7fd6f9610e68/0/4, RS_0x7fd6f9610e68/0/8, RS_0x7fd6f9610e68/0/12; -RS_0x7fd6f9610e68/1/4 .resolv tri, RS_0x7fd6f9610e68/0/16, RS_0x7fd6f9610e68/0/20, RS_0x7fd6f9610e68/0/24, RS_0x7fd6f9610e68/0/28; -RS_0x7fd6f9610e68 .resolv tri, RS_0x7fd6f9610e68/1/0, RS_0x7fd6f9610e68/1/4, C4, C4; -v0x24650e0_0 .net8 "subtract", 31 0, RS_0x7fd6f9610e68; 32 drivers -v0x2465160_0 .net "yeszero", 0 0, L_0x2492b10; 1 drivers -L_0x2469c90 .part/pv L_0x2469a80, 1, 1, 32; -L_0x2469d30 .part C4, 0, 1; -L_0x2469e60 .part C4, 1, 1; -L_0x2469f90 .part RS_0x7fd6f9610aa8, 1, 1; -L_0x246a030 .part RS_0x7fd6f9610aa8, 1, 1; -L_0x246a120 .part RS_0x7fd6f9606848, 1, 1; -L_0x246a2a0 .part RS_0x7fd6f9610aa8, 1, 1; -L_0x246ac00 .part/pv L_0x246a9f0, 1, 1, 32; -L_0x246acf0 .part C4, 0, 1; -L_0x246ae20 .part C4, 1, 1; -L_0x246afb0 .part RS_0x7fd6f9609e78, 1, 1; -L_0x246b050 .part RS_0x7fd6f9609e78, 1, 1; -L_0x246b0f0 .part RS_0x7fd6f9606848, 1, 1; -L_0x246b1e0 .part RS_0x7fd6f9606848, 1, 1; -L_0x246b680 .part/pv L_0x246b540, 1, 1, 32; -L_0x246b720 .part C4, 2, 1; -L_0x246b850 .part RS_0x7fd6f9610ec8, 1, 1; -L_0x246b990 .part RS_0x7fd6f9610ef8, 1, 1; -L_0x246bb70 .part/pv L_0x246b7c0, 1, 1, 32; -L_0x246bcf0 .part RS_0x7fd6f9610f58, 0, 1; -L_0x246bad0 .part RS_0x7fd6f9610f28, 1, 1; -L_0x246c730 .part/pv L_0x246c520, 2, 1, 32; -L_0x246bde0 .part C4, 0, 1; -L_0x246c920 .part C4, 1, 1; -L_0x246c7d0 .part RS_0x7fd6f9610aa8, 2, 1; -L_0x246cb20 .part RS_0x7fd6f9610aa8, 2, 1; -L_0x246ca50 .part RS_0x7fd6f9606848, 2, 1; -L_0x246ccf0 .part RS_0x7fd6f9610aa8, 2, 1; -L_0x246d620 .part/pv L_0x246d410, 2, 1, 32; -L_0x246d6c0 .part C4, 0, 1; -L_0x246cde0 .part C4, 1, 1; -L_0x246d980 .part RS_0x7fd6f9609e78, 2, 1; -L_0x246d7f0 .part RS_0x7fd6f9609e78, 2, 1; -L_0x246dbc0 .part RS_0x7fd6f9606848, 2, 1; -L_0x246dab0 .part RS_0x7fd6f9606848, 2, 1; -L_0x246e0f0 .part/pv L_0x246dfb0, 2, 1, 32; -L_0x246dc60 .part C4, 2, 1; -L_0x246e2c0 .part RS_0x7fd6f9610ec8, 2, 1; -L_0x246e190 .part RS_0x7fd6f9610ef8, 2, 1; -L_0x246e530 .part/pv L_0x246e3f0, 2, 1, 32; -L_0x246e720 .part RS_0x7fd6f9610f58, 1, 1; -L_0x246e850 .part RS_0x7fd6f9610f28, 2, 1; -L_0x246f0d0 .part/pv L_0x246eec0, 3, 1, 32; -L_0x246f170 .part C4, 0, 1; -L_0x246e980 .part C4, 1, 1; -L_0x246f410 .part RS_0x7fd6f9610aa8, 3, 1; -L_0x246f2a0 .part RS_0x7fd6f9610aa8, 3, 1; -L_0x246f340 .part RS_0x7fd6f9606848, 3, 1; -L_0x246f5c0 .part RS_0x7fd6f9610aa8, 3, 1; -L_0x2470080 .part/pv L_0x246fe70, 3, 1, 32; -L_0x246f850 .part C4, 0, 1; -L_0x24702c0 .part C4, 1, 1; -L_0x2470120 .part RS_0x7fd6f9609e78, 3, 1; -L_0x24701c0 .part RS_0x7fd6f9609e78, 3, 1; -L_0x24705b0 .part RS_0x7fd6f9606848, 3, 1; -L_0x2470650 .part RS_0x7fd6f9606848, 3, 1; -L_0x2470b40 .part/pv L_0x2470a00, 3, 1, 32; -L_0x2470be0 .part C4, 2, 1; -L_0x24706f0 .part RS_0x7fd6f9610ec8, 3, 1; -L_0x24707e0 .part RS_0x7fd6f9610ef8, 3, 1; -L_0x2470c80 .part/pv L_0x2470d20, 3, 1, 32; -L_0x24710a0 .part RS_0x7fd6f9610f58, 2, 1; -L_0x2470eb0 .part RS_0x7fd6f9610f28, 3, 1; -L_0x2471a70 .part/pv L_0x2471860, 4, 1, 32; -L_0x2471140 .part C4, 0, 1; -L_0x2471270 .part C4, 1, 1; -L_0x2471b10 .part RS_0x7fd6f9610aa8, 4, 1; -L_0x2471bb0 .part RS_0x7fd6f9610aa8, 4, 1; -L_0x2471c50 .part RS_0x7fd6f9606848, 4, 1; -L_0x2472030 .part RS_0x7fd6f9610aa8, 4, 1; -L_0x2472930 .part/pv L_0x2472720, 4, 1, 32; -L_0x24729d0 .part C4, 0, 1; -L_0x2472120 .part C4, 1, 1; -L_0x2472250 .part RS_0x7fd6f9609e78, 4, 1; -L_0x2472b00 .part RS_0x7fd6f9609e78, 4, 1; -L_0x2472ba0 .part RS_0x7fd6f9606848, 4, 1; -L_0x2472c90 .part RS_0x7fd6f9606848, 4, 1; -L_0x2473480 .part/pv L_0x2473340, 4, 1, 32; -L_0x2472e60 .part C4, 2, 1; -L_0x2472f00 .part RS_0x7fd6f9610ec8, 4, 1; -L_0x2472ff0 .part RS_0x7fd6f9610ef8, 4, 1; -L_0x2473630 .part/pv L_0x24736d0, 4, 1, 32; -L_0x2473b50 .part RS_0x7fd6f9610f58, 3, 1; -L_0x2473d00 .part RS_0x7fd6f9610f28, 4, 1; -L_0x2474510 .part/pv L_0x2474330, 5, 1, 32; -L_0x24745b0 .part C4, 0, 1; -L_0x2473eb0 .part C4, 1, 1; -L_0x2473fe0 .part RS_0x7fd6f9610aa8, 5, 1; -L_0x2474080 .part RS_0x7fd6f9610aa8, 5, 1; -L_0x24749b0 .part RS_0x7fd6f9606848, 5, 1; -L_0x24746e0 .part RS_0x7fd6f9610aa8, 5, 1; -L_0x24753d0 .part/pv L_0x24751f0, 5, 1, 32; -L_0x2474aa0 .part C4, 0, 1; -L_0x2474bd0 .part C4, 1, 1; -L_0x2475770 .part RS_0x7fd6f9609e78, 5, 1; -L_0x2475810 .part RS_0x7fd6f9609e78, 5, 1; -L_0x2475470 .part RS_0x7fd6f9606848, 5, 1; -L_0x2475560 .part RS_0x7fd6f9606848, 5, 1; -L_0x2475a80 .part/pv L_0x2475940, 5, 1, 32; -L_0x2475b20 .part C4, 2, 1; -L_0x2476100 .part RS_0x7fd6f9610ec8, 5, 1; -L_0x24761f0 .part RS_0x7fd6f9610ef8, 5, 1; -L_0x2475dd0 .part/pv L_0x2475e70, 5, 1, 32; -L_0x2475fb0 .part RS_0x7fd6f9610f58, 4, 1; -L_0x2476050 .part RS_0x7fd6f9610f28, 5, 1; -L_0x2476df0 .part/pv L_0x2476c10, 6, 1, 32; -L_0x24762e0 .part C4, 0, 1; -L_0x2476410 .part C4, 1, 1; -L_0x2476540 .part RS_0x7fd6f9610aa8, 6, 1; -L_0x2477200 .part RS_0x7fd6f9610aa8, 6, 1; -L_0x2476e90 .part RS_0x7fd6f9606848, 6, 1; -L_0x2476f30 .part RS_0x7fd6f9610aa8, 6, 1; -L_0x2477bc0 .part/pv L_0x24779e0, 6, 1, 32; -L_0x2477c60 .part C4, 0, 1; -L_0x24772a0 .part C4, 1, 1; -L_0x24773d0 .part RS_0x7fd6f9609e78, 6, 1; -L_0x2477470 .part RS_0x7fd6f9609e78, 6, 1; -L_0x2477510 .part RS_0x7fd6f9606848, 6, 1; -L_0x2477d90 .part RS_0x7fd6f9606848, 6, 1; -L_0x243e8f0 .part/pv L_0x24780d0, 6, 1, 32; -L_0x243e990 .part C4, 2, 1; -L_0x243ea30 .part RS_0x7fd6f9610ec8, 6, 1; -L_0x243eb20 .part RS_0x7fd6f9610ef8, 6, 1; -L_0x243ec10 .part/pv L_0x243e4e0, 6, 1, 32; -L_0x243e5e0 .part RS_0x7fd6f9610f58, 5, 1; -L_0x243e680 .part RS_0x7fd6f9610f28, 6, 1; -L_0x2479b60 .part/pv L_0x2479980, 7, 1, 32; -L_0x2479c00 .part C4, 0, 1; -L_0x2479140 .part C4, 1, 1; -L_0x2479270 .part RS_0x7fd6f9610aa8, 7, 1; -L_0x2479310 .part RS_0x7fd6f9610aa8, 7, 1; -L_0x24793b0 .part RS_0x7fd6f9606848, 7, 1; -L_0x24794a0 .part RS_0x7fd6f9610aa8, 7, 1; -L_0x247a920 .part/pv L_0x247a740, 7, 1, 32; -L_0x2479d30 .part C4, 0, 1; -L_0x2479e60 .part C4, 1, 1; -L_0x2479f90 .part RS_0x7fd6f9609e78, 7, 1; -L_0x247a030 .part RS_0x7fd6f9609e78, 7, 1; -L_0x247ae20 .part RS_0x7fd6f9606848, 7, 1; -L_0x247aec0 .part RS_0x7fd6f9606848, 7, 1; -L_0x247b420 .part/pv L_0x247ac50, 7, 1, 32; -L_0x247b4c0 .part C4, 2, 1; -L_0x247afb0 .part RS_0x7fd6f9610ec8, 7, 1; -L_0x247b0a0 .part RS_0x7fd6f9610ef8, 7, 1; -L_0x247b190 .part/pv L_0x247b230, 7, 1, 32; -L_0x247b370 .part RS_0x7fd6f9610f58, 6, 1; -L_0x247ba00 .part RS_0x7fd6f9610f28, 7, 1; -L_0x247c1d0 .part/pv L_0x247bff0, 8, 1, 32; -L_0x247b560 .part C4, 0, 1; -L_0x247b690 .part C4, 1, 1; -L_0x247b7c0 .part RS_0x7fd6f9610aa8, 8, 1; -L_0x247b860 .part RS_0x7fd6f9610aa8, 8, 1; -L_0x247b900 .part RS_0x7fd6f9606848, 8, 1; -L_0x247c740 .part RS_0x7fd6f9610aa8, 8, 1; -L_0x247cfd0 .part/pv L_0x247cdf0, 8, 1, 32; -L_0x247d070 .part C4, 0, 1; -L_0x247c830 .part C4, 1, 1; -L_0x247c960 .part RS_0x7fd6f9609e78, 8, 1; -L_0x247cc10 .part RS_0x7fd6f9609e78, 8, 1; -L_0x2472d50 .part RS_0x7fd6f9606848, 8, 1; -L_0x247d6b0 .part RS_0x7fd6f9606848, 8, 1; -L_0x247db60 .part/pv L_0x247da20, 8, 1, 32; -L_0x247d1a0 .part C4, 2, 1; -L_0x247d240 .part RS_0x7fd6f9610ec8, 8, 1; -L_0x24737a0 .part RS_0x7fd6f9610ef8, 8, 1; -L_0x2473520 .part/pv L_0x24735c0, 8, 1, 32; -L_0x247dc00 .part RS_0x7fd6f9610f58, 7, 1; -L_0x2473bf0 .part RS_0x7fd6f9610f28, 8, 1; -L_0x247ee10 .part/pv L_0x247ec30, 9, 1, 32; -L_0x247eeb0 .part C4, 0, 1; -L_0x247e340 .part C4, 1, 1; -L_0x247e470 .part RS_0x7fd6f9610aa8, 9, 1; -L_0x247e510 .part RS_0x7fd6f9610aa8, 9, 1; -L_0x247e5b0 .part RS_0x7fd6f9606848, 9, 1; -L_0x247e6a0 .part RS_0x7fd6f9610aa8, 9, 1; -L_0x247fbd0 .part/pv L_0x247f9f0, 9, 1, 32; -L_0x247efe0 .part C4, 0, 1; -L_0x247f110 .part C4, 1, 1; -L_0x247f240 .part RS_0x7fd6f9609e78, 9, 1; -L_0x247f2e0 .part RS_0x7fd6f9609e78, 9, 1; -L_0x247f380 .part RS_0x7fd6f9606848, 9, 1; -L_0x247f470 .part RS_0x7fd6f9606848, 9, 1; -L_0x2480640 .part/pv L_0x2480500, 9, 1, 32; -L_0x24806e0 .part C4, 2, 1; -L_0x247fc70 .part RS_0x7fd6f9610ec8, 9, 1; -L_0x247fd60 .part RS_0x7fd6f9610ef8, 9, 1; -L_0x247fe50 .part/pv L_0x247fef0, 9, 1, 32; -L_0x2480030 .part RS_0x7fd6f9610f58, 8, 1; -L_0x24800d0 .part RS_0x7fd6f9610f28, 9, 1; -L_0x2481480 .part/pv L_0x24812a0, 10, 1, 32; -L_0x2480780 .part C4, 0, 1; -L_0x24808b0 .part C4, 1, 1; -L_0x24809e0 .part RS_0x7fd6f9610aa8, 10, 1; -L_0x2480a80 .part RS_0x7fd6f9610aa8, 10, 1; -L_0x2480b20 .part RS_0x7fd6f9606848, 10, 1; -L_0x2480c10 .part RS_0x7fd6f9610aa8, 10, 1; -L_0x2482260 .part/pv L_0x2482080, 10, 1, 32; -L_0x2482300 .part C4, 0, 1; -L_0x2481520 .part C4, 1, 1; -L_0x2481650 .part RS_0x7fd6f9609e78, 10, 1; -L_0x24816f0 .part RS_0x7fd6f9609e78, 10, 1; -L_0x2481790 .part RS_0x7fd6f9606848, 10, 1; -L_0x2481880 .part RS_0x7fd6f9606848, 10, 1; -L_0x2482cc0 .part/pv L_0x2482b80, 10, 1, 32; -L_0x2482430 .part C4, 2, 1; -L_0x24824d0 .part RS_0x7fd6f9610ec8, 10, 1; -L_0x24825c0 .part RS_0x7fd6f9610ef8, 10, 1; -L_0x24826b0 .part/pv L_0x2482750, 10, 1, 32; -L_0x2482890 .part RS_0x7fd6f9610f58, 9, 1; -L_0x2482930 .part RS_0x7fd6f9610f28, 10, 1; -L_0x2483b10 .part/pv L_0x2483930, 11, 1, 32; -L_0x2483bb0 .part C4, 0, 1; -L_0x2482d60 .part C4, 1, 1; -L_0x2482e90 .part RS_0x7fd6f9610aa8, 11, 1; -L_0x2483340 .part RS_0x7fd6f9610aa8, 11, 1; -L_0x2474d80 .part RS_0x7fd6f9606848, 11, 1; -L_0x2474e70 .part RS_0x7fd6f9610aa8, 11, 1; -L_0x2484260 .part/pv L_0x2484080, 11, 1, 32; -L_0x2484300 .part C4, 0, 1; -L_0x2484f20 .part C4, 1, 1; -L_0x24847b0 .part RS_0x7fd6f9609e78, 11, 1; -L_0x2484850 .part RS_0x7fd6f9609e78, 11, 1; -L_0x24848f0 .part RS_0x7fd6f9606848, 11, 1; -L_0x24849e0 .part RS_0x7fd6f9606848, 11, 1; -L_0x24857b0 .part/pv L_0x2484da0, 11, 1, 32; -L_0x2485850 .part C4, 2, 1; -L_0x2485050 .part RS_0x7fd6f9610ec8, 11, 1; -L_0x2485140 .part RS_0x7fd6f9610ef8, 11, 1; -L_0x2485230 .part/pv L_0x24852d0, 11, 1, 32; -L_0x2485410 .part RS_0x7fd6f9610f58, 10, 1; -L_0x24854b0 .part RS_0x7fd6f9610f28, 11, 1; -L_0x2486610 .part/pv L_0x2486430, 12, 1, 32; -L_0x24858f0 .part C4, 0, 1; -L_0x2485a20 .part C4, 1, 1; -L_0x2485b50 .part RS_0x7fd6f9610aa8, 12, 1; -L_0x2485bf0 .part RS_0x7fd6f9610aa8, 12, 1; -L_0x2485c90 .part RS_0x7fd6f9606848, 12, 1; -L_0x2485d80 .part RS_0x7fd6f9610aa8, 12, 1; -L_0x2487410 .part/pv L_0x2487230, 12, 1, 32; -L_0x24874b0 .part C4, 0, 1; -L_0x24866b0 .part C4, 1, 1; -L_0x24867e0 .part RS_0x7fd6f9609e78, 12, 1; -L_0x2486880 .part RS_0x7fd6f9609e78, 12, 1; -L_0x2486920 .part RS_0x7fd6f9606848, 12, 1; -L_0x2486a10 .part RS_0x7fd6f9606848, 12, 1; -L_0x2487e70 .part/pv L_0x2486dd0, 12, 1, 32; -L_0x24875e0 .part C4, 2, 1; -L_0x2487680 .part RS_0x7fd6f9610ec8, 12, 1; -L_0x2487770 .part RS_0x7fd6f9610ef8, 12, 1; -L_0x2487860 .part/pv L_0x2487900, 12, 1, 32; -L_0x2487a40 .part RS_0x7fd6f9610f58, 11, 1; -L_0x2487ae0 .part RS_0x7fd6f9610f28, 12, 1; -L_0x2488d20 .part/pv L_0x2488b40, 13, 1, 32; -L_0x2488dc0 .part C4, 0, 1; -L_0x2487f10 .part C4, 1, 1; -L_0x2488040 .part RS_0x7fd6f9610aa8, 13, 1; -L_0x24880e0 .part RS_0x7fd6f9610aa8, 13, 1; -L_0x2488180 .part RS_0x7fd6f9606848, 13, 1; -L_0x2488270 .part RS_0x7fd6f9610aa8, 13, 1; -L_0x2489b50 .part/pv L_0x2489970, 13, 1, 32; -L_0x2488ef0 .part C4, 0, 1; -L_0x2489020 .part C4, 1, 1; -L_0x2489150 .part RS_0x7fd6f9609e78, 13, 1; -L_0x24891f0 .part RS_0x7fd6f9609e78, 13, 1; -L_0x2489290 .part RS_0x7fd6f9606848, 13, 1; -L_0x2489380 .part RS_0x7fd6f9606848, 13, 1; -L_0x248a5e0 .part/pv L_0x248a4a0, 13, 1, 32; -L_0x248a680 .part C4, 2, 1; -L_0x2489bf0 .part RS_0x7fd6f9610ec8, 13, 1; -L_0x2489ce0 .part RS_0x7fd6f9610ef8, 13, 1; -L_0x2489dd0 .part/pv L_0x2489e70, 13, 1, 32; -L_0x2489fb0 .part RS_0x7fd6f9610f58, 12, 1; -L_0x248a050 .part RS_0x7fd6f9610f28, 13, 1; -L_0x248b450 .part/pv L_0x248b270, 14, 1, 32; -L_0x248a720 .part C4, 0, 1; -L_0x248a850 .part C4, 1, 1; -L_0x248a980 .part RS_0x7fd6f9610aa8, 14, 1; -L_0x248aa20 .part RS_0x7fd6f9610aa8, 14, 1; -L_0x248aac0 .part RS_0x7fd6f9606848, 14, 1; -L_0x248abb0 .part RS_0x7fd6f9610aa8, 14, 1; -L_0x248c220 .part/pv L_0x248c040, 14, 1, 32; -L_0x248c2c0 .part C4, 0, 1; -L_0x248b4f0 .part C4, 1, 1; -L_0x248b620 .part RS_0x7fd6f9609e78, 14, 1; -L_0x248b6c0 .part RS_0x7fd6f9609e78, 14, 1; -L_0x248b760 .part RS_0x7fd6f9606848, 14, 1; -L_0x248b850 .part RS_0x7fd6f9606848, 14, 1; -L_0x248ccf0 .part/pv L_0x248bc10, 14, 1, 32; -L_0x248c3f0 .part C4, 2, 1; -L_0x248c490 .part RS_0x7fd6f9610ec8, 14, 1; -L_0x248c580 .part RS_0x7fd6f9610ef8, 14, 1; -L_0x248c670 .part/pv L_0x248c710, 14, 1, 32; -L_0x248c850 .part RS_0x7fd6f9610f58, 13, 1; -L_0x248c8f0 .part RS_0x7fd6f9610f28, 14, 1; -L_0x248dad0 .part/pv L_0x248d8f0, 15, 1, 32; -L_0x248db70 .part C4, 0, 1; -L_0x248cd90 .part C4, 1, 1; -L_0x248cec0 .part RS_0x7fd6f9610aa8, 15, 1; -L_0x248cf60 .part RS_0x7fd6f9610aa8, 15, 1; -L_0x248d000 .part RS_0x7fd6f9606848, 15, 1; -L_0x248d0f0 .part RS_0x7fd6f9610aa8, 15, 1; -L_0x248e870 .part/pv L_0x248e690, 15, 1, 32; -L_0x248dca0 .part C4, 0, 1; -L_0x248ddd0 .part C4, 1, 1; -L_0x248df00 .part RS_0x7fd6f9609e78, 15, 1; -L_0x248dfa0 .part RS_0x7fd6f9609e78, 15, 1; -L_0x248e040 .part RS_0x7fd6f9606848, 15, 1; -L_0x248e130 .part RS_0x7fd6f9606848, 15, 1; -L_0x248f2c0 .part/pv L_0x248e490, 15, 1, 32; -L_0x248f360 .part C4, 2, 1; -L_0x248e910 .part RS_0x7fd6f9610ec8, 15, 1; -L_0x248ea00 .part RS_0x7fd6f9610ef8, 15, 1; -L_0x248eaf0 .part/pv L_0x248eb90, 15, 1, 32; -L_0x248ec90 .part RS_0x7fd6f9610f58, 14, 1; -L_0x248ed30 .part RS_0x7fd6f9610f28, 15, 1; -L_0x24900b0 .part/pv L_0x248fed0, 16, 1, 32; -L_0x248f400 .part C4, 0, 1; -L_0x248f530 .part C4, 1, 1; -L_0x248f660 .part RS_0x7fd6f9610aa8, 16, 1; -L_0x248f700 .part RS_0x7fd6f9610aa8, 16, 1; -L_0x248f7a0 .part RS_0x7fd6f9606848, 16, 1; -L_0x248f890 .part RS_0x7fd6f9610aa8, 16, 1; -L_0x2490e80 .part/pv L_0x2490ca0, 16, 1, 32; -L_0x2490f20 .part C4, 0, 1; -L_0x2490150 .part C4, 1, 1; -L_0x2490280 .part RS_0x7fd6f9609e78, 16, 1; -L_0x247ca00 .part RS_0x7fd6f9609e78, 16, 1; -L_0x247caa0 .part RS_0x7fd6f9606848, 16, 1; -L_0x2490730 .part RS_0x7fd6f9606848, 16, 1; -L_0x2491af0 .part/pv L_0x2490ab0, 16, 1, 32; -L_0x2491050 .part C4, 2, 1; -L_0x24910f0 .part RS_0x7fd6f9610ec8, 16, 1; -L_0x247d330 .part RS_0x7fd6f9610ef8, 16, 1; -L_0x2491a00 .part/pv L_0x247d420, 16, 1, 32; -L_0x247e130 .part RS_0x7fd6f9610f58, 15, 1; -L_0x247e1d0 .part RS_0x7fd6f9610f28, 16, 1; -L_0x2491ea0 .part/pv L_0x2491cc0, 17, 1, 32; -L_0x2491f40 .part C4, 0, 1; -L_0x2492070 .part C4, 1, 1; -L_0x24921a0 .part RS_0x7fd6f9610aa8, 17, 1; -L_0x2492240 .part RS_0x7fd6f9610aa8, 17, 1; -L_0x24922e0 .part RS_0x7fd6f9606848, 17, 1; -L_0x24923d0 .part RS_0x7fd6f9610aa8, 17, 1; -L_0x2493f70 .part/pv L_0x2493d60, 17, 1, 32; -L_0x2492e30 .part C4, 0, 1; -L_0x2492f60 .part C4, 1, 1; -L_0x2493090 .part RS_0x7fd6f9609e78, 17, 1; -L_0x2493130 .part RS_0x7fd6f9609e78, 17, 1; -L_0x24931d0 .part RS_0x7fd6f9606848, 17, 1; -L_0x24932c0 .part RS_0x7fd6f9606848, 17, 1; -L_0x2493760 .part/pv L_0x2493620, 17, 1, 32; -L_0x2493800 .part C4, 2, 1; -L_0x2494b20 .part RS_0x7fd6f9610ec8, 17, 1; -L_0x2494bc0 .part RS_0x7fd6f9610ef8, 17, 1; -L_0x2494010 .part/pv L_0x24940b0, 17, 1, 32; -L_0x24941f0 .part RS_0x7fd6f9610f58, 16, 1; -L_0x2494290 .part RS_0x7fd6f9610f28, 17, 1; -L_0x2495870 .part/pv L_0x2494970, 18, 1, 32; -L_0x2494cb0 .part C4, 0, 1; -L_0x2494de0 .part C4, 1, 1; -L_0x2494f10 .part RS_0x7fd6f9610aa8, 18, 1; -L_0x2494fb0 .part RS_0x7fd6f9610aa8, 18, 1; -L_0x2495050 .part RS_0x7fd6f9606848, 18, 1; -L_0x2495140 .part RS_0x7fd6f9610aa8, 18, 1; -L_0x24966d0 .part/pv L_0x24964c0, 18, 1, 32; -L_0x2496770 .part C4, 0, 1; -L_0x2495910 .part C4, 1, 1; -L_0x2495a40 .part RS_0x7fd6f9609e78, 18, 1; -L_0x2495ae0 .part RS_0x7fd6f9609e78, 18, 1; -L_0x2495b80 .part RS_0x7fd6f9606848, 18, 1; -L_0x2495c70 .part RS_0x7fd6f9606848, 18, 1; -L_0x2496130 .part/pv L_0x2495ff0, 18, 1, 32; -L_0x24961d0 .part C4, 2, 1; -L_0x2496270 .part RS_0x7fd6f9610ec8, 18, 1; -L_0x2496360 .part RS_0x7fd6f9610ef8, 18, 1; -L_0x2497460 .part/pv L_0x24968a0, 18, 1, 32; -L_0x24969e0 .part RS_0x7fd6f9610f58, 17, 1; -L_0x2496a80 .part RS_0x7fd6f9610f28, 18, 1; -L_0x2497340 .part/pv L_0x2497130, 19, 1, 32; -L_0x24980e0 .part C4, 0, 1; -L_0x2497500 .part C4, 1, 1; -L_0x2497630 .part RS_0x7fd6f9610aa8, 19, 1; -L_0x24976d0 .part RS_0x7fd6f9610aa8, 19, 1; -L_0x2497770 .part RS_0x7fd6f9606848, 19, 1; -L_0x2497860 .part RS_0x7fd6f9610aa8, 19, 1; -L_0x2498e70 .part/pv L_0x2497f60, 19, 1, 32; -L_0x2498210 .part C4, 0, 1; -L_0x2498340 .part C4, 1, 1; -L_0x2498470 .part RS_0x7fd6f9609e78, 19, 1; -L_0x2498510 .part RS_0x7fd6f9609e78, 19, 1; -L_0x24985b0 .part RS_0x7fd6f9606848, 19, 1; -L_0x24986a0 .part RS_0x7fd6f9606848, 19, 1; -L_0x2498b00 .part/pv L_0x24989c0, 19, 1, 32; -L_0x2498ba0 .part C4, 2, 1; -L_0x2498c40 .part RS_0x7fd6f9610ec8, 19, 1; -L_0x2498d30 .part RS_0x7fd6f9610ef8, 19, 1; -L_0x2499b80 .part/pv L_0x2499c20, 19, 1, 32; -L_0x2499d60 .part RS_0x7fd6f9610f58, 18, 1; -L_0x2498f10 .part RS_0x7fd6f9610f28, 19, 1; -L_0x2499800 .part/pv L_0x24995f0, 20, 1, 32; -L_0x24998a0 .part C4, 0, 1; -L_0x24999d0 .part C4, 1, 1; -L_0x249aaa0 .part RS_0x7fd6f9610aa8, 20, 1; -L_0x249ab40 .part RS_0x7fd6f9610aa8, 20, 1; -L_0x2499e00 .part RS_0x7fd6f9606848, 20, 1; -L_0x2499ef0 .part RS_0x7fd6f9610aa8, 20, 1; -L_0x249a810 .part/pv L_0x249a600, 20, 1, 32; -L_0x249a8b0 .part C4, 0, 1; -L_0x249a9e0 .part C4, 1, 1; -L_0x249b940 .part RS_0x7fd6f9609e78, 20, 1; -L_0x249abe0 .part RS_0x7fd6f9609e78, 20, 1; -L_0x249ac80 .part RS_0x7fd6f9606848, 20, 1; -L_0x249ad70 .part RS_0x7fd6f9606848, 20, 1; -L_0x249b230 .part/pv L_0x249b0f0, 20, 1, 32; -L_0x249b2d0 .part C4, 2, 1; -L_0x249b370 .part RS_0x7fd6f9610ec8, 20, 1; -L_0x249b460 .part RS_0x7fd6f9610ef8, 20, 1; -L_0x249b550 .part/pv L_0x249b5f0, 20, 1, 32; -L_0x249b730 .part RS_0x7fd6f9610f58, 19, 1; -L_0x249b7d0 .part RS_0x7fd6f9610f28, 20, 1; -L_0x249ced0 .part/pv L_0x249ccc0, 21, 1, 32; -L_0x249cf70 .part C4, 0, 1; -L_0x249b9e0 .part C4, 1, 1; -L_0x249bb10 .part RS_0x7fd6f9610aa8, 21, 1; -L_0x249bbb0 .part RS_0x7fd6f9610aa8, 21, 1; -L_0x249bc50 .part RS_0x7fd6f9606848, 21, 1; -L_0x249bd40 .part RS_0x7fd6f9610aa8, 21, 1; -L_0x249e180 .part/pv L_0x249df70, 21, 1, 32; -L_0x249d0a0 .part C4, 0, 1; -L_0x249d1d0 .part C4, 1, 1; -L_0x249d300 .part RS_0x7fd6f9609e78, 21, 1; -L_0x249d3a0 .part RS_0x7fd6f9609e78, 21, 1; -L_0x249d440 .part RS_0x7fd6f9606848, 21, 1; -L_0x249d530 .part RS_0x7fd6f9606848, 21, 1; -L_0x2484710 .part/pv L_0x24845d0, 21, 1, 32; -L_0x249d620 .part C4, 2, 1; -L_0x249d6c0 .part RS_0x7fd6f9610ec8, 21, 1; -L_0x249d7b0 .part RS_0x7fd6f9610ef8, 21, 1; -L_0x249d8a0 .part/pv L_0x249d940, 21, 1, 32; -L_0x249da80 .part RS_0x7fd6f9610f58, 20, 1; -L_0x249db20 .part RS_0x7fd6f9610f28, 21, 1; -L_0x249e890 .part/pv L_0x249e680, 22, 1, 32; -L_0x249e930 .part C4, 0, 1; -L_0x249ea60 .part C4, 1, 1; -L_0x249eb90 .part RS_0x7fd6f9610aa8, 22, 1; -L_0x249ec30 .part RS_0x7fd6f9610aa8, 22, 1; -L_0x249ecd0 .part RS_0x7fd6f9606848, 22, 1; -L_0x249edc0 .part RS_0x7fd6f9610aa8, 22, 1; -L_0x24a0d00 .part/pv L_0x24a0af0, 22, 1, 32; -L_0x24a0da0 .part C4, 0, 1; -L_0x249f7c0 .part C4, 1, 1; -L_0x249f8f0 .part RS_0x7fd6f9609e78, 22, 1; -L_0x249f990 .part RS_0x7fd6f9609e78, 22, 1; -L_0x249fa30 .part RS_0x7fd6f9606848, 22, 1; -L_0x249fb20 .part RS_0x7fd6f9606848, 22, 1; -L_0x24a0020 .part/pv L_0x249fee0, 22, 1, 32; -L_0x24a00c0 .part C4, 2, 1; -L_0x24a0160 .part RS_0x7fd6f9610ec8, 22, 1; -L_0x24a0250 .part RS_0x7fd6f9610ef8, 22, 1; -L_0x24a0340 .part/pv L_0x24a03e0, 22, 1, 32; -L_0x24a0520 .part RS_0x7fd6f9610f58, 21, 1; -L_0x24a1d40 .part RS_0x7fd6f9610f28, 22, 1; -L_0x24a1700 .part/pv L_0x24a14f0, 23, 1, 32; -L_0x24a17a0 .part C4, 0, 1; -L_0x24a18d0 .part C4, 1, 1; -L_0x24a1a00 .part RS_0x7fd6f9610aa8, 23, 1; -L_0x24a1aa0 .part RS_0x7fd6f9610aa8, 23, 1; -L_0x24a1b40 .part RS_0x7fd6f9606848, 23, 1; -L_0x24a1c30 .part RS_0x7fd6f9610aa8, 23, 1; -L_0x24a3540 .part/pv L_0x24a3330, 23, 1, 32; -L_0x24a1e30 .part C4, 0, 1; -L_0x24a1f60 .part C4, 1, 1; -L_0x24a2090 .part RS_0x7fd6f9609e78, 23, 1; -L_0x24a2130 .part RS_0x7fd6f9609e78, 23, 1; -L_0x24a21d0 .part RS_0x7fd6f9606848, 23, 1; -L_0x24a22c0 .part RS_0x7fd6f9606848, 23, 1; -L_0x24a2760 .part/pv L_0x24a2620, 23, 1, 32; -L_0x24a2800 .part C4, 2, 1; -L_0x24a28a0 .part RS_0x7fd6f9610ec8, 23, 1; -L_0x24a2990 .part RS_0x7fd6f9610ef8, 23, 1; -L_0x24a2a80 .part/pv L_0x24a2b20, 23, 1, 32; -L_0x24a44f0 .part RS_0x7fd6f9610f58, 22, 1; -L_0x24a35e0 .part RS_0x7fd6f9610f28, 23, 1; -L_0x24a3ed0 .part/pv L_0x24a3cc0, 24, 1, 32; -L_0x24a3f70 .part C4, 0, 1; -L_0x24a40a0 .part C4, 1, 1; -L_0x24a41d0 .part RS_0x7fd6f9610aa8, 24, 1; -L_0x24a4270 .part RS_0x7fd6f9610aa8, 24, 1; -L_0x24a4310 .part RS_0x7fd6f9606848, 24, 1; -L_0x24a4400 .part RS_0x7fd6f9610aa8, 24, 1; -L_0x24a5cc0 .part/pv L_0x24a5ab0, 24, 1, 32; -L_0x24a5d60 .part C4, 0, 1; -L_0x24a4590 .part C4, 1, 1; -L_0x24a46c0 .part RS_0x7fd6f9609e78, 24, 1; -L_0x24a4760 .part RS_0x7fd6f9609e78, 24, 1; -L_0x24a4800 .part RS_0x7fd6f9606848, 24, 1; -L_0x24a48f0 .part RS_0x7fd6f9606848, 24, 1; -L_0x24a4df0 .part/pv L_0x24a4cb0, 24, 1, 32; -L_0x24a4e90 .part C4, 2, 1; -L_0x24a4f30 .part RS_0x7fd6f9610ec8, 24, 1; -L_0x24a5020 .part RS_0x7fd6f9610ef8, 24, 1; -L_0x24a5110 .part/pv L_0x24a51b0, 24, 1, 32; -L_0x24a52f0 .part RS_0x7fd6f9610f58, 23, 1; -L_0x24a5390 .part RS_0x7fd6f9610f28, 24, 1; -L_0x24a7600 .part/pv L_0x24a73f0, 25, 1, 32; -L_0x24a76a0 .part C4, 0, 1; -L_0x24a5e90 .part C4, 1, 1; -L_0x24a5fc0 .part RS_0x7fd6f9610aa8, 25, 1; -L_0x24a6060 .part RS_0x7fd6f9610aa8, 25, 1; -L_0x24a6100 .part RS_0x7fd6f9606848, 25, 1; -L_0x24a61f0 .part RS_0x7fd6f9610aa8, 25, 1; -L_0x24a6b00 .part/pv L_0x24a68f0, 25, 1, 32; -L_0x24a6ba0 .part C4, 0, 1; -L_0x24a6cd0 .part C4, 1, 1; -L_0x24a87f0 .part RS_0x7fd6f9609e78, 25, 1; -L_0x24a8890 .part RS_0x7fd6f9609e78, 25, 1; -L_0x24a77d0 .part RS_0x7fd6f9606848, 25, 1; -L_0x24a78c0 .part RS_0x7fd6f9606848, 25, 1; -L_0x24a7d00 .part/pv L_0x24a7bc0, 25, 1, 32; -L_0x24a7da0 .part C4, 2, 1; -L_0x24a7e40 .part RS_0x7fd6f9610ec8, 25, 1; -L_0x24a7f30 .part RS_0x7fd6f9610ef8, 25, 1; -L_0x24a8020 .part/pv L_0x24a80c0, 25, 1, 32; -L_0x24a8200 .part RS_0x7fd6f9610f58, 24, 1; -L_0x24a82a0 .part RS_0x7fd6f9610f28, 25, 1; -L_0x24a9d40 .part/pv L_0x24a9b30, 26, 1, 32; -L_0x24a8930 .part C4, 0, 1; -L_0x24a8a60 .part C4, 1, 1; -L_0x24a8b90 .part RS_0x7fd6f9610aa8, 26, 1; -L_0x24a8c30 .part RS_0x7fd6f9610aa8, 26, 1; -L_0x24a8cd0 .part RS_0x7fd6f9606848, 26, 1; -L_0x24a8dc0 .part RS_0x7fd6f9610aa8, 26, 1; -L_0x24a96e0 .part/pv L_0x24a94d0, 26, 1, 32; -L_0x24a9780 .part C4, 0, 1; -L_0x24a98b0 .part C4, 1, 1; -L_0x24aaf30 .part RS_0x7fd6f9609e78, 26, 1; -L_0x24a9de0 .part RS_0x7fd6f9609e78, 26, 1; -L_0x24a9e80 .part RS_0x7fd6f9606848, 26, 1; -L_0x24a9f20 .part RS_0x7fd6f9606848, 26, 1; -L_0x24aa3e0 .part/pv L_0x24aa2a0, 26, 1, 32; -L_0x24aa480 .part C4, 2, 1; -L_0x24aa520 .part RS_0x7fd6f9610ec8, 26, 1; -L_0x24aa610 .part RS_0x7fd6f9610ef8, 26, 1; -L_0x24aa700 .part/pv L_0x24aa7a0, 26, 1, 32; -L_0x24aa8e0 .part RS_0x7fd6f9610f58, 25, 1; -L_0x24aa980 .part RS_0x7fd6f9610f28, 26, 1; -L_0x24ac500 .part/pv L_0x24ac2f0, 27, 1, 32; -L_0x24ac5a0 .part C4, 0, 1; -L_0x24aafd0 .part C4, 1, 1; -L_0x24ab100 .part RS_0x7fd6f9610aa8, 27, 1; -L_0x24ab1a0 .part RS_0x7fd6f9610aa8, 27, 1; -L_0x24ab240 .part RS_0x7fd6f9606848, 27, 1; -L_0x24ab330 .part RS_0x7fd6f9610aa8, 27, 1; -L_0x24abc40 .part/pv L_0x24aba30, 27, 1, 32; -L_0x24abce0 .part C4, 0, 1; -L_0x24abe10 .part C4, 1, 1; -L_0x24abf40 .part RS_0x7fd6f9609e78, 27, 1; -L_0x24abfe0 .part RS_0x7fd6f9609e78, 27, 1; -L_0x24ad850 .part RS_0x7fd6f9606848, 27, 1; -L_0x24ad8f0 .part RS_0x7fd6f9606848, 27, 1; -L_0x24aca40 .part/pv L_0x24ac900, 27, 1, 32; -L_0x24acae0 .part C4, 2, 1; -L_0x24acb80 .part RS_0x7fd6f9610ec8, 27, 1; -L_0x24acc70 .part RS_0x7fd6f9610ef8, 27, 1; -L_0x24acd60 .part/pv L_0x24ace00, 27, 1, 32; -L_0x24acf40 .part RS_0x7fd6f9610f58, 26, 1; -L_0x24acfe0 .part RS_0x7fd6f9610f28, 27, 1; -L_0x24aec80 .part/pv L_0x24ad720, 28, 1, 32; -L_0x24ad9e0 .part C4, 0, 1; -L_0x24adb10 .part C4, 1, 1; -L_0x24adc40 .part RS_0x7fd6f9610aa8, 28, 1; -L_0x24adce0 .part RS_0x7fd6f9610aa8, 28, 1; -L_0x24add80 .part RS_0x7fd6f9606848, 28, 1; -L_0x24ade70 .part RS_0x7fd6f9610aa8, 28, 1; -L_0x24ae790 .part/pv L_0x24ae580, 28, 1, 32; -L_0x24ae830 .part C4, 0, 1; -L_0x24ae960 .part C4, 1, 1; -L_0x24aea90 .part RS_0x7fd6f9609e78, 28, 1; -L_0x24aff40 .part RS_0x7fd6f9609e78, 28, 1; -L_0x24affe0 .part RS_0x7fd6f9606848, 28, 1; -L_0x24aed20 .part RS_0x7fd6f9606848, 28, 1; -L_0x24af1e0 .part/pv L_0x24af0a0, 28, 1, 32; -L_0x24af280 .part C4, 2, 1; -L_0x24af320 .part RS_0x7fd6f9610ec8, 28, 1; -L_0x24af410 .part RS_0x7fd6f9610ef8, 28, 1; -L_0x24af500 .part/pv L_0x24af5a0, 28, 1, 32; -L_0x24af6e0 .part RS_0x7fd6f9610f58, 27, 1; -L_0x24af780 .part RS_0x7fd6f9610f28, 28, 1; -L_0x24b1470 .part/pv L_0x24afe90, 29, 1, 32; -L_0x24b1510 .part C4, 0, 1; -L_0x24b0080 .part C4, 1, 1; -L_0x24b01b0 .part RS_0x7fd6f9610aa8, 29, 1; -L_0x24b0250 .part RS_0x7fd6f9610aa8, 29, 1; -L_0x24b02f0 .part RS_0x7fd6f9606848, 29, 1; -L_0x24b0390 .part RS_0x7fd6f9610aa8, 29, 1; -L_0x24b0cd0 .part/pv L_0x24b0ac0, 29, 1, 32; -L_0x24b0d70 .part C4, 0, 1; -L_0x24b0ea0 .part C4, 1, 1; -L_0x24b0fd0 .part RS_0x7fd6f9609e78, 29, 1; -L_0x24b1070 .part RS_0x7fd6f9609e78, 29, 1; -L_0x24b1110 .part RS_0x7fd6f9606848, 29, 1; -L_0x24b1200 .part RS_0x7fd6f9606848, 29, 1; -L_0x24b2d30 .part/pv L_0x24b2bf0, 29, 1, 32; -L_0x24b2dd0 .part C4, 2, 1; -L_0x24b1640 .part RS_0x7fd6f9610ec8, 29, 1; -L_0x24b1730 .part RS_0x7fd6f9610ef8, 29, 1; -L_0x24b1820 .part/pv L_0x24b18c0, 29, 1, 32; -L_0x24b19c0 .part RS_0x7fd6f9610f58, 28, 1; -L_0x24b1a60 .part RS_0x7fd6f9610f28, 29, 1; -L_0x24b2380 .part/pv L_0x24b2170, 30, 1, 32; -L_0x24b2420 .part C4, 0, 1; -L_0x24b2550 .part C4, 1, 1; -L_0x24b2680 .part RS_0x7fd6f9610aa8, 30, 1; -L_0x24b2720 .part RS_0x7fd6f9610aa8, 30, 1; -L_0x24b27c0 .part RS_0x7fd6f9606848, 30, 1; -L_0x24b41b0 .part RS_0x7fd6f9610aa8, 30, 1; -L_0x24b36a0 .part/pv L_0x24b3490, 30, 1, 32; -L_0x24b3740 .part C4, 0, 1; -L_0x24b3870 .part C4, 1, 1; -L_0x24b39a0 .part RS_0x7fd6f9609e78, 30, 1; -L_0x24b3a40 .part RS_0x7fd6f9609e78, 30, 1; -L_0x24b3ae0 .part RS_0x7fd6f9606848, 30, 1; -L_0x24b3bd0 .part RS_0x7fd6f9606848, 30, 1; -L_0x24b40d0 .part/pv L_0x24b3f90, 30, 1, 32; -L_0x24b55e0 .part C4, 2, 1; -L_0x24b5680 .part RS_0x7fd6f9610ec8, 30, 1; -L_0x24b4250 .part RS_0x7fd6f9610ef8, 30, 1; -L_0x24b4340 .part/pv L_0x24b43e0, 30, 1, 32; -L_0x24b44e0 .part RS_0x7fd6f9610f58, 29, 1; -L_0x24b4580 .part RS_0x7fd6f9610f28, 30, 1; -L_0x24b4ea0 .part/pv L_0x24b4c90, 31, 1, 32; -L_0x24b4f40 .part C4, 0, 1; -L_0x24b5070 .part C4, 1, 1; -L_0x24b51a0 .part RS_0x7fd6f9610aa8, 31, 1; -L_0x24b5240 .part RS_0x7fd6f9610aa8, 31, 1; -L_0x24b52e0 .part RS_0x7fd6f9606848, 31, 1; -L_0x24b53d0 .part RS_0x7fd6f9610aa8, 31, 1; -L_0x24b72a0 .part/pv L_0x24b7090, 31, 1, 32; -L_0x24b5770 .part C4, 0, 1; -L_0x24b58a0 .part C4, 1, 1; -L_0x24b59d0 .part RS_0x7fd6f9609e78, 31, 1; -L_0x24b5a70 .part RS_0x7fd6f9609e78, 31, 1; -L_0x24b5b10 .part RS_0x7fd6f9606848, 31, 1; -L_0x24b5c00 .part RS_0x7fd6f9606848, 31, 1; -L_0x24b60c0 .part/pv L_0x24b5f80, 31, 1, 32; -L_0x24b6160 .part C4, 2, 1; -L_0x24b6200 .part RS_0x7fd6f9610ec8, 31, 1; -L_0x24b62f0 .part RS_0x7fd6f9610ef8, 31, 1; -L_0x24b63e0 .part/pv L_0x24b6480, 31, 1, 32; -L_0x24b65c0 .part RS_0x7fd6f9610f58, 30, 1; -L_0x24b6660 .part RS_0x7fd6f9610f28, 31, 1; -L_0x2520e60 .part/pv L_0x2520c80, 0, 1, 32; -L_0x24b7340 .part C4, 0, 1; -L_0x24b7470 .part C4, 1, 1; -L_0x24b75a0 .part RS_0x7fd6f9610aa8, 0, 1; -L_0x24b7640 .part RS_0x7fd6f9610aa8, 0, 1; -L_0x24b76e0 .part RS_0x7fd6f9606848, 0, 1; -L_0x24b77d0 .part RS_0x7fd6f9610aa8, 0, 1; -L_0x24b7ff0 .part/pv L_0x24b7e10, 0, 1, 32; -L_0x24b8090 .part C4, 0, 1; -L_0x24b81c0 .part C4, 1, 1; -L_0x24b82f0 .part RS_0x7fd6f9609e78, 0, 1; -L_0x24b8390 .part RS_0x7fd6f9609e78, 0, 1; -L_0x24b8430 .part RS_0x7fd6f9606848, 0, 1; -L_0x24b8520 .part RS_0x7fd6f9606848, 0, 1; -L_0x249f1f0 .part/pv L_0x249f0b0, 0, 1, 32; -L_0x249f290 .part C4, 2, 1; -L_0x249f330 .part RS_0x7fd6f9610ec8, 0, 1; -L_0x249f420 .part RS_0x7fd6f9610ef8, 0, 1; -L_0x249f510 .part/pv L_0x249f5b0, 0, 1, 32; -L_0x249f6f0 .part RS_0x7fd6f9610f28, 0, 1; -L_0x2492a20 .part RS_0x7fd6f9610f28, 0, 1; -L_0x2492c00 .part RS_0x7fd6f9610f58, 31, 1; -S_0x2426ca0 .scope module, "trial" "AddSubSLT32" 2 279, 2 205, S_0x22690e0; - .timescale -9 -12; -P_0x2426d98 .param/l "size" 2 228, +C4<0100000>; -L_0x24e21f0/d .functor OR 1, L_0x24e22c0, C4<0>, C4<0>, C4<0>; -L_0x24e21f0 .delay (20000,20000,20000) L_0x24e21f0/d; -L_0x24e2410/d .functor XOR 1, L_0x24e21f0, L_0x24ce830, C4<0>, C4<0>; -L_0x24e2410 .delay (40000,40000,40000) L_0x24e2410/d; -L_0x24ce8d0/d .functor AND 1, L_0x24ce9e0, L_0x24cea80, C4<1>, C4<1>; -L_0x24ce8d0 .delay (20000,20000,20000) L_0x24ce8d0/d; -L_0x24e35d0/d .functor NOT 1, L_0x24e2410, C4<0>, C4<0>, C4<0>; -L_0x24e35d0 .delay (10000,10000,10000) L_0x24e35d0/d; -L_0x24e3680/d .functor NOT 1, L_0x24e3720, C4<0>, C4<0>, C4<0>; -L_0x24e3680 .delay (10000,10000,10000) L_0x24e3680/d; -L_0x24e37c0/d .functor AND 1, L_0x24e35d0, L_0x24e3940, C4<1>, C4<1>; -L_0x24e37c0 .delay (20000,20000,20000) L_0x24e37c0/d; -L_0x24e39e0/d .functor AND 1, L_0x24e2410, L_0x24e3680, C4<1>, C4<1>; -L_0x24e39e0 .delay (20000,20000,20000) L_0x24e39e0/d; -L_0x249c470/d .functor AND 1, L_0x24e37c0, L_0x24ce8d0, C4<1>, C4<1>; -L_0x249c470 .delay (20000,20000,20000) L_0x249c470/d; -L_0x249c5d0/d .functor AND 1, L_0x24e39e0, L_0x24ce8d0, C4<1>, C4<1>; -L_0x249c5d0 .delay (20000,20000,20000) L_0x249c5d0/d; -L_0x24e4440/d .functor OR 1, L_0x249c470, L_0x249c5d0, C4<0>, C4<0>; -L_0x24e4440 .delay (20000,20000,20000) L_0x24e4440/d; -v0x2462030_0 .alias "A", 31 0, v0x2462f10_0; -v0x24620d0_0 .alias "AddSubSLTSum", 31 0, v0x2463100_0; -v0x2462170_0 .alias "B", 31 0, v0x24632b0_0; -RS_0x7fd6f9610ad8/0/0 .resolv tri, L_0x2478980, L_0x24bb860, L_0x24bcc60, L_0x24be0f0; -RS_0x7fd6f9610ad8/0/4 .resolv tri, L_0x24bf590, L_0x24c0b80, L_0x24c20c0, L_0x24c3640; -RS_0x7fd6f9610ad8/0/8 .resolv tri, L_0x24c4c50, L_0x24c6160, L_0x24c7670, L_0x24c8b80; -RS_0x7fd6f9610ad8/0/12 .resolv tri, L_0x24ca080, L_0x24cb7a0, L_0x24cccb0, L_0x24ce2c0; -RS_0x7fd6f9610ad8/0/16 .resolv tri, L_0x24cf8f0, L_0x24d0d60, L_0x24d2210, L_0x24d35e0; -RS_0x7fd6f9610ad8/0/20 .resolv tri, L_0x24d4a20, L_0x24d5f30, L_0x24d72f0, L_0x24d8740; -RS_0x7fd6f9610ad8/0/24 .resolv tri, L_0x24d9c30, L_0x24db110, L_0x24dc5f0, L_0x24ddaf0; -RS_0x7fd6f9610ad8/0/28 .resolv tri, L_0x24defe0, L_0x24e08b0, L_0x24e1da0, L_0x24e3490; -RS_0x7fd6f9610ad8/1/0 .resolv tri, RS_0x7fd6f9610ad8/0/0, RS_0x7fd6f9610ad8/0/4, RS_0x7fd6f9610ad8/0/8, RS_0x7fd6f9610ad8/0/12; -RS_0x7fd6f9610ad8/1/4 .resolv tri, RS_0x7fd6f9610ad8/0/16, RS_0x7fd6f9610ad8/0/20, RS_0x7fd6f9610ad8/0/24, RS_0x7fd6f9610ad8/0/28; -RS_0x7fd6f9610ad8 .resolv tri, RS_0x7fd6f9610ad8/1/0, RS_0x7fd6f9610ad8/1/4, C4, C4; -v0x2462240_0 .net8 "CarryoutWire", 31 0, RS_0x7fd6f9610ad8; 32 drivers -v0x24622c0_0 .alias "Command", 2 0, v0x2463430_0; -v0x2462340_0 .net "Res0OF1", 0 0, L_0x24e39e0; 1 drivers -v0x24623e0_0 .net "Res1OF0", 0 0, L_0x24e37c0; 1 drivers -v0x2462480_0 .alias "SLTflag", 0 0, v0x24635d0_0; -v0x2462570_0 .net "SLTflag0", 0 0, L_0x249c470; 1 drivers -v0x2462610_0 .net "SLTflag1", 0 0, L_0x249c5d0; 1 drivers -v0x24626b0_0 .net "SLTon", 0 0, L_0x24ce8d0; 1 drivers -v0x2462750_0 .net *"_s292", 0 0, L_0x24e22c0; 1 drivers -v0x24627f0_0 .net/s *"_s293", 0 0, C4<0>; 1 drivers -v0x2462890_0 .net *"_s296", 0 0, L_0x24ce830; 1 drivers -v0x24629b0_0 .net *"_s298", 0 0, L_0x24ce9e0; 1 drivers -v0x2462a50_0 .net *"_s300", 0 0, L_0x24cea80; 1 drivers -v0x2462910_0 .net *"_s302", 0 0, L_0x24e3720; 1 drivers -v0x2462ba0_0 .net *"_s304", 0 0, L_0x24e3940; 1 drivers -v0x2462cc0_0 .alias "carryin", 31 0, v0x2464e90_0; -v0x2462d40_0 .alias "carryout", 0 0, v0x2464cc0_0; -v0x2462c20_0 .net "nAddSubSLTSum", 0 0, L_0x24e3680; 1 drivers -v0x2462e70_0 .net "nOF", 0 0, L_0x24e35d0; 1 drivers -v0x2462dc0_0 .alias "overflow", 0 0, v0x2464d70_0; -v0x2462fb0_0 .alias "subtract", 31 0, v0x24650e0_0; -L_0x2478890 .part/pv L_0x2478400, 1, 1, 32; -L_0x2478980 .part/pv L_0x2478750, 1, 1, 32; -L_0x2478a70 .part/pv L_0x2478130, 1, 1, 32; -L_0x2478bb0 .part C4, 1, 1; -L_0x2478ce0 .part C4, 1, 1; -L_0x2478ea0 .part RS_0x7fd6f9610ad8, 0, 1; -L_0x24bb770 .part/pv L_0x24bb2e0, 2, 1, 32; -L_0x24bb860 .part/pv L_0x24bb630, 2, 1, 32; -L_0x24bb9a0 .part/pv L_0x24bb010, 2, 1, 32; -L_0x24bba90 .part C4, 2, 1; -L_0x24bbb90 .part C4, 2, 1; -L_0x24bbcc0 .part RS_0x7fd6f9610ad8, 1, 1; -L_0x24bcb70 .part/pv L_0x24bc6e0, 3, 1, 32; -L_0x24bcc60 .part/pv L_0x24bca30, 3, 1, 32; -L_0x24bcdd0 .part/pv L_0x24bc410, 3, 1, 32; -L_0x24bcf00 .part C4, 3, 1; -L_0x24bd030 .part C4, 3, 1; -L_0x24bd160 .part RS_0x7fd6f9610ad8, 2, 1; -L_0x24be000 .part/pv L_0x24bdb70, 4, 1, 32; -L_0x24be0f0 .part/pv L_0x24bdec0, 4, 1, 32; -L_0x24bd200 .part/pv L_0x24bd8a0, 4, 1, 32; -L_0x24be2e0 .part C4, 4, 1; -L_0x24be1e0 .part C4, 4, 1; -L_0x24be4d0 .part RS_0x7fd6f9610ad8, 3, 1; -L_0x24bf4a0 .part/pv L_0x24bf010, 5, 1, 32; -L_0x24bf590 .part/pv L_0x24bf360, 5, 1, 32; -L_0x24be680 .part/pv L_0x24bed40, 5, 1, 32; -L_0x24bf7b0 .part C4, 5, 1; -L_0x24bf680 .part C4, 5, 1; -L_0x24bfb60 .part RS_0x7fd6f9610ad8, 4, 1; -L_0x24c0a90 .part/pv L_0x24c05c0, 6, 1, 32; -L_0x24c0b80 .part/pv L_0x24c0930, 6, 1, 32; -L_0x24bfc00 .part/pv L_0x24c02f0, 6, 1, 32; -L_0x24c0d80 .part C4, 6, 1; -L_0x24c0c70 .part C4, 6, 1; -L_0x24c0fd0 .part RS_0x7fd6f9610ad8, 5, 1; -L_0x24c1fd0 .part/pv L_0x24c1b00, 7, 1, 32; -L_0x24c20c0 .part/pv L_0x24c1e50, 7, 1, 32; -L_0x24c1070 .part/pv L_0x24c1830, 7, 1, 32; -L_0x24c2400 .part C4, 7, 1; -L_0x24c21b0 .part C4, 7, 1; -L_0x24c2250 .part RS_0x7fd6f9610ad8, 6, 1; -L_0x24c3550 .part/pv L_0x24c30a0, 8, 1, 32; -L_0x24c3640 .part/pv L_0x24c33f0, 8, 1, 32; -L_0x24c24a0 .part/pv L_0x24c2dd0, 8, 1, 32; -L_0x24c38a0 .part C4, 8, 1; -L_0x24c3730 .part C4, 8, 1; -L_0x24c3ac0 .part RS_0x7fd6f9610ad8, 7, 1; -L_0x24c4b60 .part/pv L_0x24c46b0, 9, 1, 32; -L_0x24c4c50 .part/pv L_0x24c4a00, 9, 1, 32; -L_0x24c3d70 .part/pv L_0x24c43e0, 9, 1, 32; -L_0x24c3e60 .part C4, 9, 1; -L_0x24c4ef0 .part C4, 9, 1; -L_0x24c5020 .part RS_0x7fd6f9610ad8, 8, 1; -L_0x24c6070 .part/pv L_0x24c5bc0, 10, 1, 32; -L_0x24c6160 .part/pv L_0x24c5f10, 10, 1, 32; -L_0x24c50c0 .part/pv L_0x24c58f0, 10, 1, 32; -L_0x24c51b0 .part C4, 10, 1; -L_0x24c6430 .part C4, 10, 1; -L_0x24c6560 .part RS_0x7fd6f9610ad8, 9, 1; -L_0x24c7580 .part/pv L_0x24c70d0, 11, 1, 32; -L_0x24c7670 .part/pv L_0x24c7420, 11, 1, 32; -L_0x24c6600 .part/pv L_0x24c6e00, 11, 1, 32; -L_0x24c66f0 .part C4, 11, 1; -L_0x24c7970 .part C4, 11, 1; -L_0x24c7aa0 .part RS_0x7fd6f9610ad8, 10, 1; -L_0x24c8a90 .part/pv L_0x24c85e0, 12, 1, 32; -L_0x24c8b80 .part/pv L_0x24c8930, 12, 1, 32; -L_0x24c7b40 .part/pv L_0x24c8310, 12, 1, 32; -L_0x24c7c30 .part C4, 12, 1; -L_0x24c8eb0 .part C4, 12, 1; -L_0x24c8f50 .part RS_0x7fd6f9610ad8, 11, 1; -L_0x24c9f90 .part/pv L_0x24c9ae0, 13, 1, 32; -L_0x24ca080 .part/pv L_0x24c9e30, 13, 1, 32; -L_0x24c8ff0 .part/pv L_0x24c9810, 13, 1, 32; -L_0x24c90e0 .part C4, 13, 1; -L_0x24c9180 .part C4, 13, 1; -L_0x24bfa50 .part RS_0x7fd6f9610ad8, 12, 1; -L_0x24cb6b0 .part/pv L_0x24cb200, 14, 1, 32; -L_0x24cb7a0 .part/pv L_0x24cb550, 14, 1, 32; -L_0x24ca5e0 .part/pv L_0x24caf30, 14, 1, 32; -L_0x24ca6d0 .part C4, 14, 1; -L_0x24ca770 .part C4, 14, 1; -L_0x24cbbc0 .part RS_0x7fd6f9610ad8, 13, 1; -L_0x24ccbc0 .part/pv L_0x24cc710, 15, 1, 32; -L_0x24cccb0 .part/pv L_0x24cca60, 15, 1, 32; -L_0x24cbc60 .part/pv L_0x24cc440, 15, 1, 32; -L_0x24c2340 .part C4, 15, 1; -L_0x24cd070 .part C4, 15, 1; -L_0x24cd1a0 .part RS_0x7fd6f9610ad8, 14, 1; -L_0x24ce1d0 .part/pv L_0x24cdd20, 16, 1, 32; -L_0x24ce2c0 .part/pv L_0x24ce070, 16, 1, 32; -L_0x24cd240 .part/pv L_0x24cda50, 16, 1, 32; -L_0x24cd330 .part C4, 16, 1; -L_0x24cd3d0 .part C4, 16, 1; -L_0x24ce6b0 .part RS_0x7fd6f9610ad8, 15, 1; -L_0x24cf800 .part/pv L_0x24cf370, 17, 1, 32; -L_0x24cf8f0 .part/pv L_0x24cf6c0, 17, 1, 32; -L_0x24ceb60 .part/pv L_0x24cf0a0, 17, 1, 32; -L_0x24cec50 .part C4, 17, 1; -L_0x24cecf0 .part C4, 17, 1; -L_0x24cfd10 .part RS_0x7fd6f9610ad8, 16, 1; -L_0x24d0c70 .part/pv L_0x24d07e0, 18, 1, 32; -L_0x24d0d60 .part/pv L_0x24d0b30, 18, 1, 32; -L_0x24cfdb0 .part/pv L_0x24d0510, 18, 1, 32; -L_0x24cfea0 .part C4, 18, 1; -L_0x24cff40 .part C4, 18, 1; -L_0x24d11b0 .part RS_0x7fd6f9610ad8, 17, 1; -L_0x24d2120 .part/pv L_0x24d1c90, 19, 1, 32; -L_0x24d2210 .part/pv L_0x24d1fe0, 19, 1, 32; -L_0x24d1250 .part/pv L_0x24d19c0, 19, 1, 32; -L_0x24d1340 .part C4, 19, 1; -L_0x24d13e0 .part C4, 19, 1; -L_0x24d1510 .part RS_0x7fd6f9610ad8, 18, 1; -L_0x24d34f0 .part/pv L_0x24d3060, 20, 1, 32; -L_0x24d35e0 .part/pv L_0x24d33b0, 20, 1, 32; -L_0x24d2300 .part/pv L_0x24d2d90, 20, 1, 32; -L_0x24d23f0 .part C4, 20, 1; -L_0x24d2490 .part C4, 20, 1; -L_0x24d25c0 .part RS_0x7fd6f9610ad8, 19, 1; -L_0x24d4930 .part/pv L_0x24d4460, 21, 1, 32; -L_0x24d4a20 .part/pv L_0x24d47d0, 21, 1, 32; -L_0x24d36d0 .part/pv L_0x24d4190, 21, 1, 32; -L_0x24d37c0 .part C4, 21, 1; -L_0x24d3860 .part C4, 21, 1; -L_0x24d3990 .part RS_0x7fd6f9610ad8, 20, 1; -L_0x24d5e40 .part/pv L_0x24d5990, 22, 1, 32; -L_0x24d5f30 .part/pv L_0x24d5ce0, 22, 1, 32; -L_0x24d4b10 .part/pv L_0x24d56c0, 22, 1, 32; -L_0x24d4c00 .part C4, 22, 1; -L_0x24d4ca0 .part C4, 22, 1; -L_0x24d4dd0 .part RS_0x7fd6f9610ad8, 21, 1; -L_0x24d7200 .part/pv L_0x24d6d70, 23, 1, 32; -L_0x24d72f0 .part/pv L_0x24d70c0, 23, 1, 32; -L_0x24d6020 .part/pv L_0x24d6aa0, 23, 1, 32; -L_0x24d6110 .part C4, 23, 1; -L_0x24d61b0 .part C4, 23, 1; -L_0x24d62e0 .part RS_0x7fd6f9610ad8, 22, 1; -L_0x24d8650 .part/pv L_0x24d8150, 24, 1, 32; -L_0x24d8740 .part/pv L_0x24d84f0, 24, 1, 32; -L_0x24d73e0 .part/pv L_0x24d7e80, 24, 1, 32; -L_0x24d74d0 .part C4, 24, 1; -L_0x24d7570 .part C4, 24, 1; -L_0x24d76a0 .part RS_0x7fd6f9610ad8, 23, 1; -L_0x24d9b40 .part/pv L_0x24d9610, 25, 1, 32; -L_0x24d9c30 .part/pv L_0x24d99e0, 25, 1, 32; -L_0x24d8830 .part/pv L_0x24d9340, 25, 1, 32; -L_0x24d8920 .part C4, 25, 1; -L_0x24d89c0 .part C4, 25, 1; -L_0x24d8af0 .part RS_0x7fd6f9610ad8, 24, 1; -L_0x24db020 .part/pv L_0x24daaf0, 26, 1, 32; -L_0x24db110 .part/pv L_0x24daec0, 26, 1, 32; -L_0x24d9d20 .part/pv L_0x24da820, 26, 1, 32; -L_0x24d9e10 .part C4, 26, 1; -L_0x24d9eb0 .part C4, 26, 1; -L_0x24d9fe0 .part RS_0x7fd6f9610ad8, 25, 1; -L_0x24dc500 .part/pv L_0x24dbfd0, 27, 1, 32; -L_0x24dc5f0 .part/pv L_0x24dc3a0, 27, 1, 32; -L_0x24db200 .part/pv L_0x24dbd00, 27, 1, 32; -L_0x24db2f0 .part C4, 27, 1; -L_0x24db390 .part C4, 27, 1; -L_0x24db4c0 .part RS_0x7fd6f9610ad8, 26, 1; -L_0x24dda00 .part/pv L_0x24dd4f0, 28, 1, 32; -L_0x24ddaf0 .part/pv L_0x24dd8a0, 28, 1, 32; -L_0x24dc6e0 .part/pv L_0x24dd1f0, 28, 1, 32; -L_0x24dc7d0 .part C4, 28, 1; -L_0x24dc870 .part C4, 28, 1; -L_0x24dc9a0 .part RS_0x7fd6f9610ad8, 27, 1; -L_0x24deef0 .part/pv L_0x24de9e0, 29, 1, 32; -L_0x24defe0 .part/pv L_0x24ded90, 29, 1, 32; -L_0x24ddbe0 .part/pv L_0x24de6e0, 29, 1, 32; -L_0x24ddcd0 .part C4, 29, 1; -L_0x24ca3d0 .part C4, 29, 1; -L_0x24ca500 .part RS_0x7fd6f9610ad8, 28, 1; -L_0x24e07c0 .part/pv L_0x24e0330, 30, 1, 32; -L_0x24e08b0 .part/pv L_0x24e0680, 30, 1, 32; -L_0x24dfa40 .part/pv L_0x24e0060, 30, 1, 32; -L_0x24dfb30 .part C4, 30, 1; -L_0x24dfbd0 .part C4, 30, 1; -L_0x24dfd00 .part RS_0x7fd6f9610ad8, 29, 1; -L_0x24e1cb0 .part/pv L_0x24e17a0, 31, 1, 32; -L_0x24e1da0 .part/pv L_0x24e1b50, 31, 1, 32; -L_0x24e09a0 .part/pv L_0x24e14a0, 31, 1, 32; -L_0x24e0ea0 .part C4, 31, 1; -L_0x24cbd00 .part C4, 31, 1; -L_0x24cbe30 .part RS_0x7fd6f9610ad8, 30, 1; -L_0x24e33a0 .part/pv L_0x24e2e70, 0, 1, 32; -L_0x24e3490 .part/pv L_0x24e3240, 0, 1, 32; -L_0x24e1e90 .part/pv L_0x24e2ba0, 0, 1, 32; -L_0x24e1f80 .part C4, 0, 1; -L_0x24e2020 .part C4, 0, 1; -L_0x24e2150 .part RS_0x7fd6f9610e68, 0, 1; -L_0x24e22c0 .part RS_0x7fd6f9610ad8, 31, 1; -L_0x24ce830 .part RS_0x7fd6f9610ad8, 30, 1; -L_0x24ce9e0 .part C4, 1, 1; -L_0x24cea80 .part RS_0x7fd6f9610e68, 0, 1; -L_0x24e3720 .part RS_0x7fd6f9610aa8, 31, 1; -L_0x24e3940 .part RS_0x7fd6f9610aa8, 31, 1; -S_0x2461020 .scope module, "attempt2" "MiddleAddSubSLT" 2 225, 2 89, S_0x2426ca0; - .timescale -9 -12; -L_0x24e2470/d .functor NOT 1, L_0x24e2020, C4<0>, C4<0>, C4<0>; -L_0x24e2470 .delay (10000,10000,10000) L_0x24e2470/d; -L_0x24e2a40/d .functor NOT 1, L_0x24e2b00, C4<0>, C4<0>, C4<0>; -L_0x24e2a40 .delay (10000,10000,10000) L_0x24e2a40/d; -L_0x24e2ba0/d .functor AND 1, L_0x24e2ce0, L_0x24e2a40, C4<1>, C4<1>; -L_0x24e2ba0 .delay (20000,20000,20000) L_0x24e2ba0/d; -L_0x24e2d80/d .functor XOR 1, L_0x24e1f80, L_0x24e27d0, C4<0>, C4<0>; -L_0x24e2d80 .delay (40000,40000,40000) L_0x24e2d80/d; -L_0x24e2e70/d .functor XOR 1, L_0x24e2d80, L_0x24e2150, C4<0>, C4<0>; -L_0x24e2e70 .delay (40000,40000,40000) L_0x24e2e70/d; -L_0x24e2f90/d .functor AND 1, L_0x24e1f80, L_0x24e27d0, C4<1>, C4<1>; -L_0x24e2f90 .delay (20000,20000,20000) L_0x24e2f90/d; -L_0x24e3130/d .functor AND 1, L_0x24e2d80, L_0x24e2150, C4<1>, C4<1>; -L_0x24e3130 .delay (20000,20000,20000) L_0x24e3130/d; -L_0x24e3240/d .functor OR 1, L_0x24e2f90, L_0x24e3130, C4<0>, C4<0>; -L_0x24e3240 .delay (20000,20000,20000) L_0x24e3240/d; -v0x2461690_0 .net "A", 0 0, L_0x24e1f80; 1 drivers -v0x2461750_0 .net "AandB", 0 0, L_0x24e2f90; 1 drivers -v0x24617f0_0 .net "AddSubSLTSum", 0 0, L_0x24e2e70; 1 drivers -v0x2461890_0 .net "AxorB", 0 0, L_0x24e2d80; 1 drivers -v0x2461910_0 .net "B", 0 0, L_0x24e2020; 1 drivers -v0x24619c0_0 .net "BornB", 0 0, L_0x24e27d0; 1 drivers -v0x2461a80_0 .net "CINandAxorB", 0 0, L_0x24e3130; 1 drivers -v0x2461b00_0 .alias "Command", 2 0, v0x2463430_0; -v0x2461b80_0 .net *"_s3", 0 0, L_0x24e2b00; 1 drivers -v0x2461c00_0 .net *"_s5", 0 0, L_0x24e2ce0; 1 drivers -v0x2461ca0_0 .net "carryin", 0 0, L_0x24e2150; 1 drivers -v0x2461d40_0 .net "carryout", 0 0, L_0x24e3240; 1 drivers -v0x2461de0_0 .net "nB", 0 0, L_0x24e2470; 1 drivers -v0x2461e90_0 .net "nCmd2", 0 0, L_0x24e2a40; 1 drivers -v0x2461f90_0 .net "subtract", 0 0, L_0x24e2ba0; 1 drivers -L_0x24e29a0 .part C4, 0, 1; -L_0x24e2b00 .part C4, 2, 1; -L_0x24e2ce0 .part C4, 0, 1; -S_0x2461110 .scope module, "mux0" "TwoInMux" 2 105, 2 8, S_0x2461020; - .timescale -9 -12; -L_0x24e2570/d .functor NOT 1, L_0x24e29a0, C4<0>, C4<0>, C4<0>; -L_0x24e2570 .delay (10000,10000,10000) L_0x24e2570/d; -L_0x24e25d0/d .functor AND 1, L_0x24e2020, L_0x24e2570, C4<1>, C4<1>; -L_0x24e25d0 .delay (20000,20000,20000) L_0x24e25d0/d; -L_0x24e26c0/d .functor AND 1, L_0x24e2470, L_0x24e29a0, C4<1>, C4<1>; -L_0x24e26c0 .delay (20000,20000,20000) L_0x24e26c0/d; -L_0x24e27d0/d .functor OR 1, L_0x24e25d0, L_0x24e26c0, C4<0>, C4<0>; -L_0x24e27d0 .delay (20000,20000,20000) L_0x24e27d0/d; -v0x2461200_0 .net "S", 0 0, L_0x24e29a0; 1 drivers -v0x24612c0_0 .alias "in0", 0 0, v0x2461910_0; -v0x2461360_0 .alias "in1", 0 0, v0x2461de0_0; -v0x2461400_0 .net "nS", 0 0, L_0x24e2570; 1 drivers -v0x24614b0_0 .net "out0", 0 0, L_0x24e25d0; 1 drivers -v0x2461550_0 .net "out1", 0 0, L_0x24e26c0; 1 drivers -v0x24615f0_0 .alias "outfinal", 0 0, v0x24619c0_0; -S_0x245fe80 .scope generate, "addbits[1]" "addbits[1]" 2 230, 2 230, S_0x2426ca0; - .timescale -9 -12; -P_0x245f898 .param/l "i" 2 230, +C4<01>; -S_0x245fff0 .scope module, "attempt" "MiddleAddSubSLT" 2 232, 2 89, S_0x245fe80; - .timescale -9 -12; -L_0x24b6750/d .functor NOT 1, L_0x2478ce0, C4<0>, C4<0>, C4<0>; -L_0x24b6750 .delay (10000,10000,10000) L_0x24b6750/d; -L_0x24b89d0/d .functor NOT 1, L_0x24b8a70, C4<0>, C4<0>, C4<0>; -L_0x24b89d0 .delay (10000,10000,10000) L_0x24b89d0/d; -L_0x2478130/d .functor AND 1, L_0x2478270, L_0x24b89d0, C4<1>, C4<1>; -L_0x2478130 .delay (20000,20000,20000) L_0x2478130/d; -L_0x2478310/d .functor XOR 1, L_0x2478bb0, L_0x24b87a0, C4<0>, C4<0>; -L_0x2478310 .delay (40000,40000,40000) L_0x2478310/d; -L_0x2478400/d .functor XOR 1, L_0x2478310, L_0x2478ea0, C4<0>, C4<0>; -L_0x2478400 .delay (40000,40000,40000) L_0x2478400/d; -L_0x24784f0/d .functor AND 1, L_0x2478bb0, L_0x24b87a0, C4<1>, C4<1>; -L_0x24784f0 .delay (20000,20000,20000) L_0x24784f0/d; -L_0x2478660/d .functor AND 1, L_0x2478310, L_0x2478ea0, C4<1>, C4<1>; -L_0x2478660 .delay (20000,20000,20000) L_0x2478660/d; -L_0x2478750/d .functor OR 1, L_0x24784f0, L_0x2478660, C4<0>, C4<0>; -L_0x2478750 .delay (20000,20000,20000) L_0x2478750/d; -v0x2460680_0 .net "A", 0 0, L_0x2478bb0; 1 drivers -v0x2460740_0 .net "AandB", 0 0, L_0x24784f0; 1 drivers -v0x24607e0_0 .net "AddSubSLTSum", 0 0, L_0x2478400; 1 drivers -v0x2460880_0 .net "AxorB", 0 0, L_0x2478310; 1 drivers -v0x2460900_0 .net "B", 0 0, L_0x2478ce0; 1 drivers -v0x24609b0_0 .net "BornB", 0 0, L_0x24b87a0; 1 drivers -v0x2460a70_0 .net "CINandAxorB", 0 0, L_0x2478660; 1 drivers -v0x2460af0_0 .alias "Command", 2 0, v0x2463430_0; -v0x2460b70_0 .net *"_s3", 0 0, L_0x24b8a70; 1 drivers -v0x2460bf0_0 .net *"_s5", 0 0, L_0x2478270; 1 drivers -v0x2460c90_0 .net "carryin", 0 0, L_0x2478ea0; 1 drivers -v0x2460d30_0 .net "carryout", 0 0, L_0x2478750; 1 drivers -v0x2460dd0_0 .net "nB", 0 0, L_0x24b6750; 1 drivers -v0x2460e80_0 .net "nCmd2", 0 0, L_0x24b89d0; 1 drivers -v0x2460f80_0 .net "subtract", 0 0, L_0x2478130; 1 drivers -L_0x24b8930 .part C4, 0, 1; -L_0x24b8a70 .part C4, 2, 1; -L_0x2478270 .part C4, 0, 1; -S_0x24600e0 .scope module, "mux0" "TwoInMux" 2 105, 2 8, S_0x245fff0; - .timescale -9 -12; -L_0x24b68e0/d .functor NOT 1, L_0x24b8930, C4<0>, C4<0>, C4<0>; -L_0x24b68e0 .delay (10000,10000,10000) L_0x24b68e0/d; -L_0x24b6980/d .functor AND 1, L_0x2478ce0, L_0x24b68e0, C4<1>, C4<1>; -L_0x24b6980 .delay (20000,20000,20000) L_0x24b6980/d; -L_0x24b6a70/d .functor AND 1, L_0x24b6750, L_0x24b8930, C4<1>, C4<1>; -L_0x24b6a70 .delay (20000,20000,20000) L_0x24b6a70/d; -L_0x24b87a0/d .functor OR 1, L_0x24b6980, L_0x24b6a70, C4<0>, C4<0>; -L_0x24b87a0 .delay (20000,20000,20000) L_0x24b87a0/d; -v0x24601d0_0 .net "S", 0 0, L_0x24b8930; 1 drivers -v0x2460270_0 .alias "in0", 0 0, v0x2460900_0; -v0x2460310_0 .alias "in1", 0 0, v0x2460dd0_0; -v0x24603b0_0 .net "nS", 0 0, L_0x24b68e0; 1 drivers -v0x2460460_0 .net "out0", 0 0, L_0x24b6980; 1 drivers -v0x2460500_0 .net "out1", 0 0, L_0x24b6a70; 1 drivers -v0x24605e0_0 .alias "outfinal", 0 0, v0x24609b0_0; -S_0x245ece0 .scope generate, "addbits[2]" "addbits[2]" 2 230, 2 230, S_0x2426ca0; - .timescale -9 -12; -P_0x245e6f8 .param/l "i" 2 230, +C4<010>; -S_0x245ee50 .scope module, "attempt" "MiddleAddSubSLT" 2 232, 2 89, S_0x245ece0; - .timescale -9 -12; -L_0x2478f40/d .functor NOT 1, L_0x24bbb90, C4<0>, C4<0>, C4<0>; -L_0x2478f40 .delay (10000,10000,10000) L_0x2478f40/d; -L_0x24baed0/d .functor NOT 1, L_0x24baf70, C4<0>, C4<0>, C4<0>; -L_0x24baed0 .delay (10000,10000,10000) L_0x24baed0/d; -L_0x24bb010/d .functor AND 1, L_0x24bb150, L_0x24baed0, C4<1>, C4<1>; -L_0x24bb010 .delay (20000,20000,20000) L_0x24bb010/d; -L_0x24bb1f0/d .functor XOR 1, L_0x24bba90, L_0x24baca0, C4<0>, C4<0>; -L_0x24bb1f0 .delay (40000,40000,40000) L_0x24bb1f0/d; -L_0x24bb2e0/d .functor XOR 1, L_0x24bb1f0, L_0x24bbcc0, C4<0>, C4<0>; -L_0x24bb2e0 .delay (40000,40000,40000) L_0x24bb2e0/d; -L_0x24bb3d0/d .functor AND 1, L_0x24bba90, L_0x24baca0, C4<1>, C4<1>; -L_0x24bb3d0 .delay (20000,20000,20000) L_0x24bb3d0/d; -L_0x24bb540/d .functor AND 1, L_0x24bb1f0, L_0x24bbcc0, C4<1>, C4<1>; -L_0x24bb540 .delay (20000,20000,20000) L_0x24bb540/d; -L_0x24bb630/d .functor OR 1, L_0x24bb3d0, L_0x24bb540, C4<0>, C4<0>; -L_0x24bb630 .delay (20000,20000,20000) L_0x24bb630/d; -v0x245f4e0_0 .net "A", 0 0, L_0x24bba90; 1 drivers -v0x245f5a0_0 .net "AandB", 0 0, L_0x24bb3d0; 1 drivers -v0x245f640_0 .net "AddSubSLTSum", 0 0, L_0x24bb2e0; 1 drivers -v0x245f6e0_0 .net "AxorB", 0 0, L_0x24bb1f0; 1 drivers -v0x245f760_0 .net "B", 0 0, L_0x24bbb90; 1 drivers -v0x245f810_0 .net "BornB", 0 0, L_0x24baca0; 1 drivers -v0x245f8d0_0 .net "CINandAxorB", 0 0, L_0x24bb540; 1 drivers -v0x245f950_0 .alias "Command", 2 0, v0x2463430_0; -v0x245f9d0_0 .net *"_s3", 0 0, L_0x24baf70; 1 drivers -v0x245fa50_0 .net *"_s5", 0 0, L_0x24bb150; 1 drivers -v0x245faf0_0 .net "carryin", 0 0, L_0x24bbcc0; 1 drivers -v0x245fb90_0 .net "carryout", 0 0, L_0x24bb630; 1 drivers -v0x245fc30_0 .net "nB", 0 0, L_0x2478f40; 1 drivers -v0x245fce0_0 .net "nCmd2", 0 0, L_0x24baed0; 1 drivers -v0x245fde0_0 .net "subtract", 0 0, L_0x24bb010; 1 drivers -L_0x24bae30 .part C4, 0, 1; -L_0x24baf70 .part C4, 2, 1; -L_0x24bb150 .part C4, 0, 1; -S_0x245ef40 .scope module, "mux0" "TwoInMux" 2 105, 2 8, S_0x245ee50; - .timescale -9 -12; -L_0x2479030/d .functor NOT 1, L_0x24bae30, C4<0>, C4<0>, C4<0>; -L_0x2479030 .delay (10000,10000,10000) L_0x2479030/d; -L_0x24790d0/d .functor AND 1, L_0x24bbb90, L_0x2479030, C4<1>, C4<1>; -L_0x24790d0 .delay (20000,20000,20000) L_0x24790d0/d; -L_0x24babb0/d .functor AND 1, L_0x2478f40, L_0x24bae30, C4<1>, C4<1>; -L_0x24babb0 .delay (20000,20000,20000) L_0x24babb0/d; -L_0x24baca0/d .functor OR 1, L_0x24790d0, L_0x24babb0, C4<0>, C4<0>; -L_0x24baca0 .delay (20000,20000,20000) L_0x24baca0/d; -v0x245f030_0 .net "S", 0 0, L_0x24bae30; 1 drivers -v0x245f0d0_0 .alias "in0", 0 0, v0x245f760_0; -v0x245f170_0 .alias "in1", 0 0, v0x245fc30_0; -v0x245f210_0 .net "nS", 0 0, L_0x2479030; 1 drivers -v0x245f2c0_0 .net "out0", 0 0, L_0x24790d0; 1 drivers -v0x245f360_0 .net "out1", 0 0, L_0x24babb0; 1 drivers -v0x245f440_0 .alias "outfinal", 0 0, v0x245f810_0; -S_0x245db40 .scope generate, "addbits[3]" "addbits[3]" 2 230, 2 230, S_0x2426ca0; - .timescale -9 -12; -P_0x245d558 .param/l "i" 2 230, +C4<011>; -S_0x245dcb0 .scope module, "attempt" "MiddleAddSubSLT" 2 232, 2 89, S_0x245db40; - .timescale -9 -12; -L_0x24bbb30/d .functor NOT 1, L_0x24bd030, C4<0>, C4<0>, C4<0>; -L_0x24bbb30 .delay (10000,10000,10000) L_0x24bbb30/d; -L_0x24bc2d0/d .functor NOT 1, L_0x24bc370, C4<0>, C4<0>, C4<0>; -L_0x24bc2d0 .delay (10000,10000,10000) L_0x24bc2d0/d; -L_0x24bc410/d .functor AND 1, L_0x24bc550, L_0x24bc2d0, C4<1>, C4<1>; -L_0x24bc410 .delay (20000,20000,20000) L_0x24bc410/d; -L_0x24bc5f0/d .functor XOR 1, L_0x24bcf00, L_0x24bc0a0, C4<0>, C4<0>; -L_0x24bc5f0 .delay (40000,40000,40000) L_0x24bc5f0/d; -L_0x24bc6e0/d .functor XOR 1, L_0x24bc5f0, L_0x24bd160, C4<0>, C4<0>; -L_0x24bc6e0 .delay (40000,40000,40000) L_0x24bc6e0/d; -L_0x24bc7d0/d .functor AND 1, L_0x24bcf00, L_0x24bc0a0, C4<1>, C4<1>; -L_0x24bc7d0 .delay (20000,20000,20000) L_0x24bc7d0/d; -L_0x24bc940/d .functor AND 1, L_0x24bc5f0, L_0x24bd160, C4<1>, C4<1>; -L_0x24bc940 .delay (20000,20000,20000) L_0x24bc940/d; -L_0x24bca30/d .functor OR 1, L_0x24bc7d0, L_0x24bc940, C4<0>, C4<0>; -L_0x24bca30 .delay (20000,20000,20000) L_0x24bca30/d; -v0x245e340_0 .net "A", 0 0, L_0x24bcf00; 1 drivers -v0x245e400_0 .net "AandB", 0 0, L_0x24bc7d0; 1 drivers -v0x245e4a0_0 .net "AddSubSLTSum", 0 0, L_0x24bc6e0; 1 drivers -v0x245e540_0 .net "AxorB", 0 0, L_0x24bc5f0; 1 drivers -v0x245e5c0_0 .net "B", 0 0, L_0x24bd030; 1 drivers -v0x245e670_0 .net "BornB", 0 0, L_0x24bc0a0; 1 drivers -v0x245e730_0 .net "CINandAxorB", 0 0, L_0x24bc940; 1 drivers -v0x245e7b0_0 .alias "Command", 2 0, v0x2463430_0; -v0x245e830_0 .net *"_s3", 0 0, L_0x24bc370; 1 drivers -v0x245e8b0_0 .net *"_s5", 0 0, L_0x24bc550; 1 drivers -v0x245e950_0 .net "carryin", 0 0, L_0x24bd160; 1 drivers -v0x245e9f0_0 .net "carryout", 0 0, L_0x24bca30; 1 drivers -v0x245ea90_0 .net "nB", 0 0, L_0x24bbb30; 1 drivers -v0x245eb40_0 .net "nCmd2", 0 0, L_0x24bc2d0; 1 drivers -v0x245ec40_0 .net "subtract", 0 0, L_0x24bc410; 1 drivers -L_0x24bc230 .part C4, 0, 1; -L_0x24bc370 .part C4, 2, 1; -L_0x24bc550 .part C4, 0, 1; -S_0x245dda0 .scope module, "mux0" "TwoInMux" 2 105, 2 8, S_0x245dcb0; - .timescale -9 -12; -L_0x24bbe60/d .functor NOT 1, L_0x24bc230, C4<0>, C4<0>, C4<0>; -L_0x24bbe60 .delay (10000,10000,10000) L_0x24bbe60/d; -L_0x24bbec0/d .functor AND 1, L_0x24bd030, L_0x24bbe60, C4<1>, C4<1>; -L_0x24bbec0 .delay (20000,20000,20000) L_0x24bbec0/d; -L_0x24bbfb0/d .functor AND 1, L_0x24bbb30, L_0x24bc230, C4<1>, C4<1>; -L_0x24bbfb0 .delay (20000,20000,20000) L_0x24bbfb0/d; -L_0x24bc0a0/d .functor OR 1, L_0x24bbec0, L_0x24bbfb0, C4<0>, C4<0>; -L_0x24bc0a0 .delay (20000,20000,20000) L_0x24bc0a0/d; -v0x245de90_0 .net "S", 0 0, L_0x24bc230; 1 drivers -v0x245df30_0 .alias "in0", 0 0, v0x245e5c0_0; -v0x245dfd0_0 .alias "in1", 0 0, v0x245ea90_0; -v0x245e070_0 .net "nS", 0 0, L_0x24bbe60; 1 drivers -v0x245e120_0 .net "out0", 0 0, L_0x24bbec0; 1 drivers -v0x245e1c0_0 .net "out1", 0 0, L_0x24bbfb0; 1 drivers -v0x245e2a0_0 .alias "outfinal", 0 0, v0x245e670_0; -S_0x245c9a0 .scope generate, "addbits[4]" "addbits[4]" 2 230, 2 230, S_0x2426ca0; - .timescale -9 -12; -P_0x245c3b8 .param/l "i" 2 230, +C4<0100>; -S_0x245cb10 .scope module, "attempt" "MiddleAddSubSLT" 2 232, 2 89, S_0x245c9a0; - .timescale -9 -12; -L_0x24bbdf0/d .functor NOT 1, L_0x24be1e0, C4<0>, C4<0>, C4<0>; -L_0x24bbdf0 .delay (10000,10000,10000) L_0x24bbdf0/d; -L_0x24bd760/d .functor NOT 1, L_0x24bd800, C4<0>, C4<0>, C4<0>; -L_0x24bd760 .delay (10000,10000,10000) L_0x24bd760/d; -L_0x24bd8a0/d .functor AND 1, L_0x24bd9e0, L_0x24bd760, C4<1>, C4<1>; -L_0x24bd8a0 .delay (20000,20000,20000) L_0x24bd8a0/d; -L_0x24bda80/d .functor XOR 1, L_0x24be2e0, L_0x24bd530, C4<0>, C4<0>; -L_0x24bda80 .delay (40000,40000,40000) L_0x24bda80/d; -L_0x24bdb70/d .functor XOR 1, L_0x24bda80, L_0x24be4d0, C4<0>, C4<0>; -L_0x24bdb70 .delay (40000,40000,40000) L_0x24bdb70/d; -L_0x24bdc60/d .functor AND 1, L_0x24be2e0, L_0x24bd530, C4<1>, C4<1>; -L_0x24bdc60 .delay (20000,20000,20000) L_0x24bdc60/d; -L_0x24bddd0/d .functor AND 1, L_0x24bda80, L_0x24be4d0, C4<1>, C4<1>; -L_0x24bddd0 .delay (20000,20000,20000) L_0x24bddd0/d; -L_0x24bdec0/d .functor OR 1, L_0x24bdc60, L_0x24bddd0, C4<0>, C4<0>; -L_0x24bdec0 .delay (20000,20000,20000) L_0x24bdec0/d; -v0x245d1a0_0 .net "A", 0 0, L_0x24be2e0; 1 drivers -v0x245d260_0 .net "AandB", 0 0, L_0x24bdc60; 1 drivers -v0x245d300_0 .net "AddSubSLTSum", 0 0, L_0x24bdb70; 1 drivers -v0x245d3a0_0 .net "AxorB", 0 0, L_0x24bda80; 1 drivers -v0x245d420_0 .net "B", 0 0, L_0x24be1e0; 1 drivers -v0x245d4d0_0 .net "BornB", 0 0, L_0x24bd530; 1 drivers -v0x245d590_0 .net "CINandAxorB", 0 0, L_0x24bddd0; 1 drivers -v0x245d610_0 .alias "Command", 2 0, v0x2463430_0; -v0x245d690_0 .net *"_s3", 0 0, L_0x24bd800; 1 drivers -v0x245d710_0 .net *"_s5", 0 0, L_0x24bd9e0; 1 drivers -v0x245d7b0_0 .net "carryin", 0 0, L_0x24be4d0; 1 drivers -v0x245d850_0 .net "carryout", 0 0, L_0x24bdec0; 1 drivers -v0x245d8f0_0 .net "nB", 0 0, L_0x24bbdf0; 1 drivers -v0x245d9a0_0 .net "nCmd2", 0 0, L_0x24bd760; 1 drivers -v0x245daa0_0 .net "subtract", 0 0, L_0x24bd8a0; 1 drivers -L_0x24bd6c0 .part C4, 0, 1; -L_0x24bd800 .part C4, 2, 1; -L_0x24bd9e0 .part C4, 0, 1; -S_0x245cc00 .scope module, "mux0" "TwoInMux" 2 105, 2 8, S_0x245cb10; - .timescale -9 -12; -L_0x24bd2f0/d .functor NOT 1, L_0x24bd6c0, C4<0>, C4<0>, C4<0>; -L_0x24bd2f0 .delay (10000,10000,10000) L_0x24bd2f0/d; -L_0x24bd350/d .functor AND 1, L_0x24be1e0, L_0x24bd2f0, C4<1>, C4<1>; -L_0x24bd350 .delay (20000,20000,20000) L_0x24bd350/d; -L_0x24bd440/d .functor AND 1, L_0x24bbdf0, L_0x24bd6c0, C4<1>, C4<1>; -L_0x24bd440 .delay (20000,20000,20000) L_0x24bd440/d; -L_0x24bd530/d .functor OR 1, L_0x24bd350, L_0x24bd440, C4<0>, C4<0>; -L_0x24bd530 .delay (20000,20000,20000) L_0x24bd530/d; -v0x245ccf0_0 .net "S", 0 0, L_0x24bd6c0; 1 drivers -v0x245cd90_0 .alias "in0", 0 0, v0x245d420_0; -v0x245ce30_0 .alias "in1", 0 0, v0x245d8f0_0; -v0x245ced0_0 .net "nS", 0 0, L_0x24bd2f0; 1 drivers -v0x245cf80_0 .net "out0", 0 0, L_0x24bd350; 1 drivers -v0x245d020_0 .net "out1", 0 0, L_0x24bd440; 1 drivers -v0x245d100_0 .alias "outfinal", 0 0, v0x245d4d0_0; -S_0x245b800 .scope generate, "addbits[5]" "addbits[5]" 2 230, 2 230, S_0x2426ca0; - .timescale -9 -12; -P_0x245b218 .param/l "i" 2 230, +C4<0101>; -S_0x245b970 .scope module, "attempt" "MiddleAddSubSLT" 2 232, 2 89, S_0x245b800; - .timescale -9 -12; -L_0x24bbd60/d .functor NOT 1, L_0x24bf680, C4<0>, C4<0>, C4<0>; -L_0x24bbd60 .delay (10000,10000,10000) L_0x24bbd60/d; -L_0x24bec00/d .functor NOT 1, L_0x24beca0, C4<0>, C4<0>, C4<0>; -L_0x24bec00 .delay (10000,10000,10000) L_0x24bec00/d; -L_0x24bed40/d .functor AND 1, L_0x24bee80, L_0x24bec00, C4<1>, C4<1>; -L_0x24bed40 .delay (20000,20000,20000) L_0x24bed40/d; -L_0x24bef20/d .functor XOR 1, L_0x24bf7b0, L_0x24be9d0, C4<0>, C4<0>; -L_0x24bef20 .delay (40000,40000,40000) L_0x24bef20/d; -L_0x24bf010/d .functor XOR 1, L_0x24bef20, L_0x24bfb60, C4<0>, C4<0>; -L_0x24bf010 .delay (40000,40000,40000) L_0x24bf010/d; -L_0x24bf100/d .functor AND 1, L_0x24bf7b0, L_0x24be9d0, C4<1>, C4<1>; -L_0x24bf100 .delay (20000,20000,20000) L_0x24bf100/d; -L_0x24bf270/d .functor AND 1, L_0x24bef20, L_0x24bfb60, C4<1>, C4<1>; -L_0x24bf270 .delay (20000,20000,20000) L_0x24bf270/d; -L_0x24bf360/d .functor OR 1, L_0x24bf100, L_0x24bf270, C4<0>, C4<0>; -L_0x24bf360 .delay (20000,20000,20000) L_0x24bf360/d; -v0x245c000_0 .net "A", 0 0, L_0x24bf7b0; 1 drivers -v0x245c0c0_0 .net "AandB", 0 0, L_0x24bf100; 1 drivers -v0x245c160_0 .net "AddSubSLTSum", 0 0, L_0x24bf010; 1 drivers -v0x245c200_0 .net "AxorB", 0 0, L_0x24bef20; 1 drivers -v0x245c280_0 .net "B", 0 0, L_0x24bf680; 1 drivers -v0x245c330_0 .net "BornB", 0 0, L_0x24be9d0; 1 drivers -v0x245c3f0_0 .net "CINandAxorB", 0 0, L_0x24bf270; 1 drivers -v0x245c470_0 .alias "Command", 2 0, v0x2463430_0; -v0x245c4f0_0 .net *"_s3", 0 0, L_0x24beca0; 1 drivers -v0x245c570_0 .net *"_s5", 0 0, L_0x24bee80; 1 drivers -v0x245c610_0 .net "carryin", 0 0, L_0x24bfb60; 1 drivers -v0x245c6b0_0 .net "carryout", 0 0, L_0x24bf360; 1 drivers -v0x245c750_0 .net "nB", 0 0, L_0x24bbd60; 1 drivers -v0x245c800_0 .net "nCmd2", 0 0, L_0x24bec00; 1 drivers -v0x245c900_0 .net "subtract", 0 0, L_0x24bed40; 1 drivers -L_0x24beb60 .part C4, 0, 1; -L_0x24beca0 .part C4, 2, 1; -L_0x24bee80 .part C4, 0, 1; -S_0x245ba60 .scope module, "mux0" "TwoInMux" 2 105, 2 8, S_0x245b970; - .timescale -9 -12; -L_0x24be750/d .functor NOT 1, L_0x24beb60, C4<0>, C4<0>, C4<0>; -L_0x24be750 .delay (10000,10000,10000) L_0x24be750/d; -L_0x24be7f0/d .functor AND 1, L_0x24bf680, L_0x24be750, C4<1>, C4<1>; -L_0x24be7f0 .delay (20000,20000,20000) L_0x24be7f0/d; -L_0x24be8e0/d .functor AND 1, L_0x24bbd60, L_0x24beb60, C4<1>, C4<1>; -L_0x24be8e0 .delay (20000,20000,20000) L_0x24be8e0/d; -L_0x24be9d0/d .functor OR 1, L_0x24be7f0, L_0x24be8e0, C4<0>, C4<0>; -L_0x24be9d0 .delay (20000,20000,20000) L_0x24be9d0/d; -v0x245bb50_0 .net "S", 0 0, L_0x24beb60; 1 drivers -v0x245bbf0_0 .alias "in0", 0 0, v0x245c280_0; -v0x245bc90_0 .alias "in1", 0 0, v0x245c750_0; -v0x245bd30_0 .net "nS", 0 0, L_0x24be750; 1 drivers -v0x245bde0_0 .net "out0", 0 0, L_0x24be7f0; 1 drivers -v0x245be80_0 .net "out1", 0 0, L_0x24be8e0; 1 drivers -v0x245bf60_0 .alias "outfinal", 0 0, v0x245c330_0; -S_0x245a620 .scope generate, "addbits[6]" "addbits[6]" 2 230, 2 230, S_0x2426ca0; - .timescale -9 -12; -P_0x245a718 .param/l "i" 2 230, +C4<0110>; -S_0x245a7d0 .scope module, "attempt" "MiddleAddSubSLT" 2 232, 2 89, S_0x245a620; - .timescale -9 -12; -L_0x2478e10/d .functor NOT 1, L_0x24c0c70, C4<0>, C4<0>, C4<0>; -L_0x2478e10 .delay (10000,10000,10000) L_0x2478e10/d; -L_0x24c0190/d .functor NOT 1, L_0x24c0250, C4<0>, C4<0>, C4<0>; -L_0x24c0190 .delay (10000,10000,10000) L_0x24c0190/d; -L_0x24c02f0/d .functor AND 1, L_0x24c0430, L_0x24c0190, C4<1>, C4<1>; -L_0x24c02f0 .delay (20000,20000,20000) L_0x24c02f0/d; -L_0x24c04d0/d .functor XOR 1, L_0x24c0d80, L_0x24bff40, C4<0>, C4<0>; -L_0x24c04d0 .delay (40000,40000,40000) L_0x24c04d0/d; -L_0x24c05c0/d .functor XOR 1, L_0x24c04d0, L_0x24c0fd0, C4<0>, C4<0>; -L_0x24c05c0 .delay (40000,40000,40000) L_0x24c05c0/d; -L_0x24c06b0/d .functor AND 1, L_0x24c0d80, L_0x24bff40, C4<1>, C4<1>; -L_0x24c06b0 .delay (20000,20000,20000) L_0x24c06b0/d; -L_0x24c0820/d .functor AND 1, L_0x24c04d0, L_0x24c0fd0, C4<1>, C4<1>; -L_0x24c0820 .delay (20000,20000,20000) L_0x24c0820/d; -L_0x24c0930/d .functor OR 1, L_0x24c06b0, L_0x24c0820, C4<0>, C4<0>; -L_0x24c0930 .delay (20000,20000,20000) L_0x24c0930/d; -v0x245ae60_0 .net "A", 0 0, L_0x24c0d80; 1 drivers -v0x245af20_0 .net "AandB", 0 0, L_0x24c06b0; 1 drivers -v0x245afc0_0 .net "AddSubSLTSum", 0 0, L_0x24c05c0; 1 drivers -v0x245b060_0 .net "AxorB", 0 0, L_0x24c04d0; 1 drivers -v0x245b0e0_0 .net "B", 0 0, L_0x24c0c70; 1 drivers -v0x245b190_0 .net "BornB", 0 0, L_0x24bff40; 1 drivers -v0x245b250_0 .net "CINandAxorB", 0 0, L_0x24c0820; 1 drivers -v0x245b2d0_0 .alias "Command", 2 0, v0x2463430_0; -v0x245b350_0 .net *"_s3", 0 0, L_0x24c0250; 1 drivers -v0x245b3d0_0 .net *"_s5", 0 0, L_0x24c0430; 1 drivers -v0x245b470_0 .net "carryin", 0 0, L_0x24c0fd0; 1 drivers -v0x245b510_0 .net "carryout", 0 0, L_0x24c0930; 1 drivers -v0x245b5b0_0 .net "nB", 0 0, L_0x2478e10; 1 drivers -v0x245b660_0 .net "nCmd2", 0 0, L_0x24c0190; 1 drivers -v0x245b760_0 .net "subtract", 0 0, L_0x24c02f0; 1 drivers -L_0x24c00f0 .part C4, 0, 1; -L_0x24c0250 .part C4, 2, 1; -L_0x24c0430 .part C4, 0, 1; -S_0x245a8c0 .scope module, "mux0" "TwoInMux" 2 105, 2 8, S_0x245a7d0; - .timescale -9 -12; -L_0x24bfd00/d .functor NOT 1, L_0x24c00f0, C4<0>, C4<0>, C4<0>; -L_0x24bfd00 .delay (10000,10000,10000) L_0x24bfd00/d; -L_0x24bfd60/d .functor AND 1, L_0x24c0c70, L_0x24bfd00, C4<1>, C4<1>; -L_0x24bfd60 .delay (20000,20000,20000) L_0x24bfd60/d; -L_0x24bfe50/d .functor AND 1, L_0x2478e10, L_0x24c00f0, C4<1>, C4<1>; -L_0x24bfe50 .delay (20000,20000,20000) L_0x24bfe50/d; -L_0x24bff40/d .functor OR 1, L_0x24bfd60, L_0x24bfe50, C4<0>, C4<0>; -L_0x24bff40 .delay (20000,20000,20000) L_0x24bff40/d; -v0x245a9b0_0 .net "S", 0 0, L_0x24c00f0; 1 drivers -v0x245aa50_0 .alias "in0", 0 0, v0x245b0e0_0; -v0x245aaf0_0 .alias "in1", 0 0, v0x245b5b0_0; -v0x245ab90_0 .net "nS", 0 0, L_0x24bfd00; 1 drivers -v0x245ac40_0 .net "out0", 0 0, L_0x24bfd60; 1 drivers -v0x245ace0_0 .net "out1", 0 0, L_0x24bfe50; 1 drivers -v0x245adc0_0 .alias "outfinal", 0 0, v0x245b190_0; -S_0x24594b0 .scope generate, "addbits[7]" "addbits[7]" 2 230, 2 230, S_0x2426ca0; - .timescale -9 -12; -P_0x2458ec8 .param/l "i" 2 230, +C4<0111>; -S_0x2459620 .scope module, "attempt" "MiddleAddSubSLT" 2 232, 2 89, S_0x24594b0; - .timescale -9 -12; -L_0x24c0d10/d .functor NOT 1, L_0x24c21b0, C4<0>, C4<0>, C4<0>; -L_0x24c0d10 .delay (10000,10000,10000) L_0x24c0d10/d; -L_0x24c16d0/d .functor NOT 1, L_0x24c1790, C4<0>, C4<0>, C4<0>; -L_0x24c16d0 .delay (10000,10000,10000) L_0x24c16d0/d; -L_0x24c1830/d .functor AND 1, L_0x24c1970, L_0x24c16d0, C4<1>, C4<1>; -L_0x24c1830 .delay (20000,20000,20000) L_0x24c1830/d; -L_0x24c1a10/d .functor XOR 1, L_0x24c2400, L_0x24c1460, C4<0>, C4<0>; -L_0x24c1a10 .delay (40000,40000,40000) L_0x24c1a10/d; -L_0x24c1b00/d .functor XOR 1, L_0x24c1a10, L_0x24c2250, C4<0>, C4<0>; -L_0x24c1b00 .delay (40000,40000,40000) L_0x24c1b00/d; -L_0x24c1bf0/d .functor AND 1, L_0x24c2400, L_0x24c1460, C4<1>, C4<1>; -L_0x24c1bf0 .delay (20000,20000,20000) L_0x24c1bf0/d; -L_0x24c1d60/d .functor AND 1, L_0x24c1a10, L_0x24c2250, C4<1>, C4<1>; -L_0x24c1d60 .delay (20000,20000,20000) L_0x24c1d60/d; -L_0x24c1e50/d .functor OR 1, L_0x24c1bf0, L_0x24c1d60, C4<0>, C4<0>; -L_0x24c1e50 .delay (20000,20000,20000) L_0x24c1e50/d; -v0x2459cb0_0 .net "A", 0 0, L_0x24c2400; 1 drivers -v0x2459d70_0 .net "AandB", 0 0, L_0x24c1bf0; 1 drivers -v0x2459e10_0 .net "AddSubSLTSum", 0 0, L_0x24c1b00; 1 drivers -v0x2459eb0_0 .net "AxorB", 0 0, L_0x24c1a10; 1 drivers -v0x2459f30_0 .net "B", 0 0, L_0x24c21b0; 1 drivers -v0x2459fe0_0 .net "BornB", 0 0, L_0x24c1460; 1 drivers -v0x245a060_0 .net "CINandAxorB", 0 0, L_0x24c1d60; 1 drivers -v0x245a0e0_0 .alias "Command", 2 0, v0x2463430_0; -v0x245a160_0 .net *"_s3", 0 0, L_0x24c1790; 1 drivers -v0x245a1e0_0 .net *"_s5", 0 0, L_0x24c1970; 1 drivers -v0x245a260_0 .net "carryin", 0 0, L_0x24c2250; 1 drivers -v0x245a2e0_0 .net "carryout", 0 0, L_0x24c1e50; 1 drivers -v0x245a3d0_0 .net "nB", 0 0, L_0x24c0d10; 1 drivers -v0x245a480_0 .net "nCmd2", 0 0, L_0x24c16d0; 1 drivers -v0x245a580_0 .net "subtract", 0 0, L_0x24c1830; 1 drivers -L_0x24c1630 .part C4, 0, 1; -L_0x24c1790 .part C4, 2, 1; -L_0x24c1970 .part C4, 0, 1; -S_0x2459710 .scope module, "mux0" "TwoInMux" 2 105, 2 8, S_0x2459620; - .timescale -9 -12; -L_0x24c11a0/d .functor NOT 1, L_0x24c1630, C4<0>, C4<0>, C4<0>; -L_0x24c11a0 .delay (10000,10000,10000) L_0x24c11a0/d; -L_0x24c1240/d .functor AND 1, L_0x24c21b0, L_0x24c11a0, C4<1>, C4<1>; -L_0x24c1240 .delay (20000,20000,20000) L_0x24c1240/d; -L_0x24c1350/d .functor AND 1, L_0x24c0d10, L_0x24c1630, C4<1>, C4<1>; -L_0x24c1350 .delay (20000,20000,20000) L_0x24c1350/d; -L_0x24c1460/d .functor OR 1, L_0x24c1240, L_0x24c1350, C4<0>, C4<0>; -L_0x24c1460 .delay (20000,20000,20000) L_0x24c1460/d; -v0x2459800_0 .net "S", 0 0, L_0x24c1630; 1 drivers -v0x24598a0_0 .alias "in0", 0 0, v0x2459f30_0; -v0x2459940_0 .alias "in1", 0 0, v0x245a3d0_0; -v0x24599e0_0 .net "nS", 0 0, L_0x24c11a0; 1 drivers -v0x2459a90_0 .net "out0", 0 0, L_0x24c1240; 1 drivers -v0x2459b30_0 .net "out1", 0 0, L_0x24c1350; 1 drivers -v0x2459c10_0 .alias "outfinal", 0 0, v0x2459fe0_0; -S_0x2458310 .scope generate, "addbits[8]" "addbits[8]" 2 230, 2 230, S_0x2426ca0; - .timescale -9 -12; -P_0x2457d28 .param/l "i" 2 230, +C4<01000>; -S_0x2458480 .scope module, "attempt" "MiddleAddSubSLT" 2 232, 2 89, S_0x2458310; - .timescale -9 -12; -L_0x24c2600/d .functor NOT 1, L_0x24c3730, C4<0>, C4<0>, C4<0>; -L_0x24c2600 .delay (10000,10000,10000) L_0x24c2600/d; -L_0x24c2c70/d .functor NOT 1, L_0x24c2d30, C4<0>, C4<0>, C4<0>; -L_0x24c2c70 .delay (10000,10000,10000) L_0x24c2c70/d; -L_0x24c2dd0/d .functor AND 1, L_0x24c2f10, L_0x24c2c70, C4<1>, C4<1>; -L_0x24c2dd0 .delay (20000,20000,20000) L_0x24c2dd0/d; -L_0x24c2fb0/d .functor XOR 1, L_0x24c38a0, L_0x24c2a00, C4<0>, C4<0>; -L_0x24c2fb0 .delay (40000,40000,40000) L_0x24c2fb0/d; -L_0x24c30a0/d .functor XOR 1, L_0x24c2fb0, L_0x24c3ac0, C4<0>, C4<0>; -L_0x24c30a0 .delay (40000,40000,40000) L_0x24c30a0/d; -L_0x24c3190/d .functor AND 1, L_0x24c38a0, L_0x24c2a00, C4<1>, C4<1>; -L_0x24c3190 .delay (20000,20000,20000) L_0x24c3190/d; -L_0x24c3300/d .functor AND 1, L_0x24c2fb0, L_0x24c3ac0, C4<1>, C4<1>; -L_0x24c3300 .delay (20000,20000,20000) L_0x24c3300/d; -L_0x24c33f0/d .functor OR 1, L_0x24c3190, L_0x24c3300, C4<0>, C4<0>; -L_0x24c33f0 .delay (20000,20000,20000) L_0x24c33f0/d; -v0x2458b10_0 .net "A", 0 0, L_0x24c38a0; 1 drivers -v0x2458bd0_0 .net "AandB", 0 0, L_0x24c3190; 1 drivers -v0x2458c70_0 .net "AddSubSLTSum", 0 0, L_0x24c30a0; 1 drivers -v0x2458d10_0 .net "AxorB", 0 0, L_0x24c2fb0; 1 drivers -v0x2458d90_0 .net "B", 0 0, L_0x24c3730; 1 drivers -v0x2458e40_0 .net "BornB", 0 0, L_0x24c2a00; 1 drivers -v0x2458f00_0 .net "CINandAxorB", 0 0, L_0x24c3300; 1 drivers -v0x2458f80_0 .alias "Command", 2 0, v0x2463430_0; -v0x2459000_0 .net *"_s3", 0 0, L_0x24c2d30; 1 drivers -v0x2459080_0 .net *"_s5", 0 0, L_0x24c2f10; 1 drivers -v0x2459120_0 .net "carryin", 0 0, L_0x24c3ac0; 1 drivers -v0x24591c0_0 .net "carryout", 0 0, L_0x24c33f0; 1 drivers -v0x2459260_0 .net "nB", 0 0, L_0x24c2600; 1 drivers -v0x2459310_0 .net "nCmd2", 0 0, L_0x24c2c70; 1 drivers -v0x2459410_0 .net "subtract", 0 0, L_0x24c2dd0; 1 drivers -L_0x24c2bd0 .part C4, 0, 1; -L_0x24c2d30 .part C4, 2, 1; -L_0x24c2f10 .part C4, 0, 1; -S_0x2458570 .scope module, "mux0" "TwoInMux" 2 105, 2 8, S_0x2458480; - .timescale -9 -12; -L_0x24c2720/d .functor NOT 1, L_0x24c2bd0, C4<0>, C4<0>, C4<0>; -L_0x24c2720 .delay (10000,10000,10000) L_0x24c2720/d; -L_0x24c27e0/d .functor AND 1, L_0x24c3730, L_0x24c2720, C4<1>, C4<1>; -L_0x24c27e0 .delay (20000,20000,20000) L_0x24c27e0/d; -L_0x24c28f0/d .functor AND 1, L_0x24c2600, L_0x24c2bd0, C4<1>, C4<1>; -L_0x24c28f0 .delay (20000,20000,20000) L_0x24c28f0/d; -L_0x24c2a00/d .functor OR 1, L_0x24c27e0, L_0x24c28f0, C4<0>, C4<0>; -L_0x24c2a00 .delay (20000,20000,20000) L_0x24c2a00/d; -v0x2458660_0 .net "S", 0 0, L_0x24c2bd0; 1 drivers -v0x2458700_0 .alias "in0", 0 0, v0x2458d90_0; -v0x24587a0_0 .alias "in1", 0 0, v0x2459260_0; -v0x2458840_0 .net "nS", 0 0, L_0x24c2720; 1 drivers -v0x24588f0_0 .net "out0", 0 0, L_0x24c27e0; 1 drivers -v0x2458990_0 .net "out1", 0 0, L_0x24c28f0; 1 drivers -v0x2458a70_0 .alias "outfinal", 0 0, v0x2458e40_0; -S_0x2457170 .scope generate, "addbits[9]" "addbits[9]" 2 230, 2 230, S_0x2426ca0; - .timescale -9 -12; -P_0x2456b88 .param/l "i" 2 230, +C4<01001>; -S_0x24572e0 .scope module, "attempt" "MiddleAddSubSLT" 2 232, 2 89, S_0x2457170; - .timescale -9 -12; -L_0x24c2590/d .functor NOT 1, L_0x24c4ef0, C4<0>, C4<0>, C4<0>; -L_0x24c2590 .delay (10000,10000,10000) L_0x24c2590/d; -L_0x24c4280/d .functor NOT 1, L_0x24c4340, C4<0>, C4<0>, C4<0>; -L_0x24c4280 .delay (10000,10000,10000) L_0x24c4280/d; -L_0x24c43e0/d .functor AND 1, L_0x24c4520, L_0x24c4280, C4<1>, C4<1>; -L_0x24c43e0 .delay (20000,20000,20000) L_0x24c43e0/d; -L_0x24c45c0/d .functor XOR 1, L_0x24c3e60, L_0x24c4010, C4<0>, C4<0>; -L_0x24c45c0 .delay (40000,40000,40000) L_0x24c45c0/d; -L_0x24c46b0/d .functor XOR 1, L_0x24c45c0, L_0x24c5020, C4<0>, C4<0>; -L_0x24c46b0 .delay (40000,40000,40000) L_0x24c46b0/d; -L_0x24c47a0/d .functor AND 1, L_0x24c3e60, L_0x24c4010, C4<1>, C4<1>; -L_0x24c47a0 .delay (20000,20000,20000) L_0x24c47a0/d; -L_0x24c4910/d .functor AND 1, L_0x24c45c0, L_0x24c5020, C4<1>, C4<1>; -L_0x24c4910 .delay (20000,20000,20000) L_0x24c4910/d; -L_0x24c4a00/d .functor OR 1, L_0x24c47a0, L_0x24c4910, C4<0>, C4<0>; -L_0x24c4a00 .delay (20000,20000,20000) L_0x24c4a00/d; -v0x2457970_0 .net "A", 0 0, L_0x24c3e60; 1 drivers -v0x2457a30_0 .net "AandB", 0 0, L_0x24c47a0; 1 drivers -v0x2457ad0_0 .net "AddSubSLTSum", 0 0, L_0x24c46b0; 1 drivers -v0x2457b70_0 .net "AxorB", 0 0, L_0x24c45c0; 1 drivers -v0x2457bf0_0 .net "B", 0 0, L_0x24c4ef0; 1 drivers -v0x2457ca0_0 .net "BornB", 0 0, L_0x24c4010; 1 drivers -v0x2457d60_0 .net "CINandAxorB", 0 0, L_0x24c4910; 1 drivers -v0x2457de0_0 .alias "Command", 2 0, v0x2463430_0; -v0x2457e60_0 .net *"_s3", 0 0, L_0x24c4340; 1 drivers -v0x2457ee0_0 .net *"_s5", 0 0, L_0x24c4520; 1 drivers -v0x2457f80_0 .net "carryin", 0 0, L_0x24c5020; 1 drivers -v0x2458020_0 .net "carryout", 0 0, L_0x24c4a00; 1 drivers -v0x24580c0_0 .net "nB", 0 0, L_0x24c2590; 1 drivers -v0x2458170_0 .net "nCmd2", 0 0, L_0x24c4280; 1 drivers -v0x2458270_0 .net "subtract", 0 0, L_0x24c43e0; 1 drivers -L_0x24c41e0 .part C4, 0, 1; -L_0x24c4340 .part C4, 2, 1; -L_0x24c4520 .part C4, 0, 1; -S_0x24573d0 .scope module, "mux0" "TwoInMux" 2 105, 2 8, S_0x24572e0; - .timescale -9 -12; -L_0x24c3940/d .functor NOT 1, L_0x24c41e0, C4<0>, C4<0>, C4<0>; -L_0x24c3940 .delay (10000,10000,10000) L_0x24c3940/d; -L_0x24c3a00/d .functor AND 1, L_0x24c4ef0, L_0x24c3940, C4<1>, C4<1>; -L_0x24c3a00 .delay (20000,20000,20000) L_0x24c3a00/d; -L_0x24c3f00/d .functor AND 1, L_0x24c2590, L_0x24c41e0, C4<1>, C4<1>; -L_0x24c3f00 .delay (20000,20000,20000) L_0x24c3f00/d; -L_0x24c4010/d .functor OR 1, L_0x24c3a00, L_0x24c3f00, C4<0>, C4<0>; -L_0x24c4010 .delay (20000,20000,20000) L_0x24c4010/d; -v0x24574c0_0 .net "S", 0 0, L_0x24c41e0; 1 drivers -v0x2457560_0 .alias "in0", 0 0, v0x2457bf0_0; -v0x2457600_0 .alias "in1", 0 0, v0x24580c0_0; -v0x24576a0_0 .net "nS", 0 0, L_0x24c3940; 1 drivers -v0x2457750_0 .net "out0", 0 0, L_0x24c3a00; 1 drivers -v0x24577f0_0 .net "out1", 0 0, L_0x24c3f00; 1 drivers -v0x24578d0_0 .alias "outfinal", 0 0, v0x2457ca0_0; -S_0x2455fd0 .scope generate, "addbits[10]" "addbits[10]" 2 230, 2 230, S_0x2426ca0; - .timescale -9 -12; -P_0x24559e8 .param/l "i" 2 230, +C4<01010>; -S_0x2456140 .scope module, "attempt" "MiddleAddSubSLT" 2 232, 2 89, S_0x2455fd0; - .timescale -9 -12; -L_0x24c4d40/d .functor NOT 1, L_0x24c6430, C4<0>, C4<0>, C4<0>; -L_0x24c4d40 .delay (10000,10000,10000) L_0x24c4d40/d; -L_0x24c5790/d .functor NOT 1, L_0x24c5850, C4<0>, C4<0>, C4<0>; -L_0x24c5790 .delay (10000,10000,10000) L_0x24c5790/d; -L_0x24c58f0/d .functor AND 1, L_0x24c5a30, L_0x24c5790, C4<1>, C4<1>; -L_0x24c58f0 .delay (20000,20000,20000) L_0x24c58f0/d; -L_0x24c5ad0/d .functor XOR 1, L_0x24c51b0, L_0x24c5520, C4<0>, C4<0>; -L_0x24c5ad0 .delay (40000,40000,40000) L_0x24c5ad0/d; -L_0x24c5bc0/d .functor XOR 1, L_0x24c5ad0, L_0x24c6560, C4<0>, C4<0>; -L_0x24c5bc0 .delay (40000,40000,40000) L_0x24c5bc0/d; -L_0x24c5cb0/d .functor AND 1, L_0x24c51b0, L_0x24c5520, C4<1>, C4<1>; -L_0x24c5cb0 .delay (20000,20000,20000) L_0x24c5cb0/d; -L_0x24c5e20/d .functor AND 1, L_0x24c5ad0, L_0x24c6560, C4<1>, C4<1>; -L_0x24c5e20 .delay (20000,20000,20000) L_0x24c5e20/d; -L_0x24c5f10/d .functor OR 1, L_0x24c5cb0, L_0x24c5e20, C4<0>, C4<0>; -L_0x24c5f10 .delay (20000,20000,20000) L_0x24c5f10/d; -v0x24567d0_0 .net "A", 0 0, L_0x24c51b0; 1 drivers -v0x2456890_0 .net "AandB", 0 0, L_0x24c5cb0; 1 drivers -v0x2456930_0 .net "AddSubSLTSum", 0 0, L_0x24c5bc0; 1 drivers -v0x24569d0_0 .net "AxorB", 0 0, L_0x24c5ad0; 1 drivers -v0x2456a50_0 .net "B", 0 0, L_0x24c6430; 1 drivers -v0x2456b00_0 .net "BornB", 0 0, L_0x24c5520; 1 drivers -v0x2456bc0_0 .net "CINandAxorB", 0 0, L_0x24c5e20; 1 drivers -v0x2456c40_0 .alias "Command", 2 0, v0x2463430_0; -v0x2456cc0_0 .net *"_s3", 0 0, L_0x24c5850; 1 drivers -v0x2456d40_0 .net *"_s5", 0 0, L_0x24c5a30; 1 drivers -v0x2456de0_0 .net "carryin", 0 0, L_0x24c6560; 1 drivers -v0x2456e80_0 .net "carryout", 0 0, L_0x24c5f10; 1 drivers -v0x2456f20_0 .net "nB", 0 0, L_0x24c4d40; 1 drivers -v0x2456fd0_0 .net "nCmd2", 0 0, L_0x24c5790; 1 drivers -v0x24570d0_0 .net "subtract", 0 0, L_0x24c58f0; 1 drivers -L_0x24c56f0 .part C4, 0, 1; -L_0x24c5850 .part C4, 2, 1; -L_0x24c5a30 .part C4, 0, 1; -S_0x2456230 .scope module, "mux0" "TwoInMux" 2 105, 2 8, S_0x2456140; - .timescale -9 -12; -L_0x24c5280/d .functor NOT 1, L_0x24c56f0, C4<0>, C4<0>, C4<0>; -L_0x24c5280 .delay (10000,10000,10000) L_0x24c5280/d; -L_0x24c5320/d .functor AND 1, L_0x24c6430, L_0x24c5280, C4<1>, C4<1>; -L_0x24c5320 .delay (20000,20000,20000) L_0x24c5320/d; -L_0x24c5410/d .functor AND 1, L_0x24c4d40, L_0x24c56f0, C4<1>, C4<1>; -L_0x24c5410 .delay (20000,20000,20000) L_0x24c5410/d; -L_0x24c5520/d .functor OR 1, L_0x24c5320, L_0x24c5410, C4<0>, C4<0>; -L_0x24c5520 .delay (20000,20000,20000) L_0x24c5520/d; -v0x2456320_0 .net "S", 0 0, L_0x24c56f0; 1 drivers -v0x24563c0_0 .alias "in0", 0 0, v0x2456a50_0; -v0x2456460_0 .alias "in1", 0 0, v0x2456f20_0; -v0x2456500_0 .net "nS", 0 0, L_0x24c5280; 1 drivers -v0x24565b0_0 .net "out0", 0 0, L_0x24c5320; 1 drivers -v0x2456650_0 .net "out1", 0 0, L_0x24c5410; 1 drivers -v0x2456730_0 .alias "outfinal", 0 0, v0x2456b00_0; -S_0x2454e30 .scope generate, "addbits[11]" "addbits[11]" 2 230, 2 230, S_0x2426ca0; - .timescale -9 -12; -P_0x2454848 .param/l "i" 2 230, +C4<01011>; -S_0x2454fa0 .scope module, "attempt" "MiddleAddSubSLT" 2 232, 2 89, S_0x2454e30; - .timescale -9 -12; -L_0x24c6250/d .functor NOT 1, L_0x24c7970, C4<0>, C4<0>, C4<0>; -L_0x24c6250 .delay (10000,10000,10000) L_0x24c6250/d; -L_0x24c6ca0/d .functor NOT 1, L_0x24c6d60, C4<0>, C4<0>, C4<0>; -L_0x24c6ca0 .delay (10000,10000,10000) L_0x24c6ca0/d; -L_0x24c6e00/d .functor AND 1, L_0x24c6f40, L_0x24c6ca0, C4<1>, C4<1>; -L_0x24c6e00 .delay (20000,20000,20000) L_0x24c6e00/d; -L_0x24c6fe0/d .functor XOR 1, L_0x24c66f0, L_0x24c6a30, C4<0>, C4<0>; -L_0x24c6fe0 .delay (40000,40000,40000) L_0x24c6fe0/d; -L_0x24c70d0/d .functor XOR 1, L_0x24c6fe0, L_0x24c7aa0, C4<0>, C4<0>; -L_0x24c70d0 .delay (40000,40000,40000) L_0x24c70d0/d; -L_0x24c71c0/d .functor AND 1, L_0x24c66f0, L_0x24c6a30, C4<1>, C4<1>; -L_0x24c71c0 .delay (20000,20000,20000) L_0x24c71c0/d; -L_0x24c7330/d .functor AND 1, L_0x24c6fe0, L_0x24c7aa0, C4<1>, C4<1>; -L_0x24c7330 .delay (20000,20000,20000) L_0x24c7330/d; -L_0x24c7420/d .functor OR 1, L_0x24c71c0, L_0x24c7330, C4<0>, C4<0>; -L_0x24c7420 .delay (20000,20000,20000) L_0x24c7420/d; -v0x2455630_0 .net "A", 0 0, L_0x24c66f0; 1 drivers -v0x24556f0_0 .net "AandB", 0 0, L_0x24c71c0; 1 drivers -v0x2455790_0 .net "AddSubSLTSum", 0 0, L_0x24c70d0; 1 drivers -v0x2455830_0 .net "AxorB", 0 0, L_0x24c6fe0; 1 drivers -v0x24558b0_0 .net "B", 0 0, L_0x24c7970; 1 drivers -v0x2455960_0 .net "BornB", 0 0, L_0x24c6a30; 1 drivers -v0x2455a20_0 .net "CINandAxorB", 0 0, L_0x24c7330; 1 drivers -v0x2455aa0_0 .alias "Command", 2 0, v0x2463430_0; -v0x2455b20_0 .net *"_s3", 0 0, L_0x24c6d60; 1 drivers -v0x2455ba0_0 .net *"_s5", 0 0, L_0x24c6f40; 1 drivers -v0x2455c40_0 .net "carryin", 0 0, L_0x24c7aa0; 1 drivers -v0x2455ce0_0 .net "carryout", 0 0, L_0x24c7420; 1 drivers -v0x2455d80_0 .net "nB", 0 0, L_0x24c6250; 1 drivers -v0x2455e30_0 .net "nCmd2", 0 0, L_0x24c6ca0; 1 drivers -v0x2455f30_0 .net "subtract", 0 0, L_0x24c6e00; 1 drivers -L_0x24c6c00 .part C4, 0, 1; -L_0x24c6d60 .part C4, 2, 1; -L_0x24c6f40 .part C4, 0, 1; -S_0x2455090 .scope module, "mux0" "TwoInMux" 2 105, 2 8, S_0x2454fa0; - .timescale -9 -12; -L_0x24c63b0/d .functor NOT 1, L_0x24c6c00, C4<0>, C4<0>, C4<0>; -L_0x24c63b0 .delay (10000,10000,10000) L_0x24c63b0/d; -L_0x24c6830/d .functor AND 1, L_0x24c7970, L_0x24c63b0, C4<1>, C4<1>; -L_0x24c6830 .delay (20000,20000,20000) L_0x24c6830/d; -L_0x24c6920/d .functor AND 1, L_0x24c6250, L_0x24c6c00, C4<1>, C4<1>; -L_0x24c6920 .delay (20000,20000,20000) L_0x24c6920/d; -L_0x24c6a30/d .functor OR 1, L_0x24c6830, L_0x24c6920, C4<0>, C4<0>; -L_0x24c6a30 .delay (20000,20000,20000) L_0x24c6a30/d; -v0x2455180_0 .net "S", 0 0, L_0x24c6c00; 1 drivers -v0x2455220_0 .alias "in0", 0 0, v0x24558b0_0; -v0x24552c0_0 .alias "in1", 0 0, v0x2455d80_0; -v0x2455360_0 .net "nS", 0 0, L_0x24c63b0; 1 drivers -v0x2455410_0 .net "out0", 0 0, L_0x24c6830; 1 drivers -v0x24554b0_0 .net "out1", 0 0, L_0x24c6920; 1 drivers -v0x2455590_0 .alias "outfinal", 0 0, v0x2455960_0; -S_0x2453c90 .scope generate, "addbits[12]" "addbits[12]" 2 230, 2 230, S_0x2426ca0; - .timescale -9 -12; -P_0x24536a8 .param/l "i" 2 230, +C4<01100>; -S_0x2453e00 .scope module, "attempt" "MiddleAddSubSLT" 2 232, 2 89, S_0x2453c90; - .timescale -9 -12; -L_0x24c6790/d .functor NOT 1, L_0x24c8eb0, C4<0>, C4<0>, C4<0>; -L_0x24c6790 .delay (10000,10000,10000) L_0x24c6790/d; -L_0x24c81b0/d .functor NOT 1, L_0x24c8270, C4<0>, C4<0>, C4<0>; -L_0x24c81b0 .delay (10000,10000,10000) L_0x24c81b0/d; -L_0x24c8310/d .functor AND 1, L_0x24c8450, L_0x24c81b0, C4<1>, C4<1>; -L_0x24c8310 .delay (20000,20000,20000) L_0x24c8310/d; -L_0x24c84f0/d .functor XOR 1, L_0x24c7c30, L_0x24c7f40, C4<0>, C4<0>; -L_0x24c84f0 .delay (40000,40000,40000) L_0x24c84f0/d; -L_0x24c85e0/d .functor XOR 1, L_0x24c84f0, L_0x24c8f50, C4<0>, C4<0>; -L_0x24c85e0 .delay (40000,40000,40000) L_0x24c85e0/d; -L_0x24c86d0/d .functor AND 1, L_0x24c7c30, L_0x24c7f40, C4<1>, C4<1>; -L_0x24c86d0 .delay (20000,20000,20000) L_0x24c86d0/d; -L_0x24c8840/d .functor AND 1, L_0x24c84f0, L_0x24c8f50, C4<1>, C4<1>; -L_0x24c8840 .delay (20000,20000,20000) L_0x24c8840/d; -L_0x24c8930/d .functor OR 1, L_0x24c86d0, L_0x24c8840, C4<0>, C4<0>; -L_0x24c8930 .delay (20000,20000,20000) L_0x24c8930/d; -v0x2454490_0 .net "A", 0 0, L_0x24c7c30; 1 drivers -v0x2454550_0 .net "AandB", 0 0, L_0x24c86d0; 1 drivers -v0x24545f0_0 .net "AddSubSLTSum", 0 0, L_0x24c85e0; 1 drivers -v0x2454690_0 .net "AxorB", 0 0, L_0x24c84f0; 1 drivers -v0x2454710_0 .net "B", 0 0, L_0x24c8eb0; 1 drivers -v0x24547c0_0 .net "BornB", 0 0, L_0x24c7f40; 1 drivers -v0x2454880_0 .net "CINandAxorB", 0 0, L_0x24c8840; 1 drivers -v0x2454900_0 .alias "Command", 2 0, v0x2463430_0; -v0x2454980_0 .net *"_s3", 0 0, L_0x24c8270; 1 drivers -v0x2454a00_0 .net *"_s5", 0 0, L_0x24c8450; 1 drivers -v0x2454aa0_0 .net "carryin", 0 0, L_0x24c8f50; 1 drivers -v0x2454b40_0 .net "carryout", 0 0, L_0x24c8930; 1 drivers -v0x2454be0_0 .net "nB", 0 0, L_0x24c6790; 1 drivers -v0x2454c90_0 .net "nCmd2", 0 0, L_0x24c81b0; 1 drivers -v0x2454d90_0 .net "subtract", 0 0, L_0x24c8310; 1 drivers -L_0x24c8110 .part C4, 0, 1; -L_0x24c8270 .part C4, 2, 1; -L_0x24c8450 .part C4, 0, 1; -S_0x2453ef0 .scope module, "mux0" "TwoInMux" 2 105, 2 8, S_0x2453e00; - .timescale -9 -12; -L_0x24c7860/d .functor NOT 1, L_0x24c8110, C4<0>, C4<0>, C4<0>; -L_0x24c7860 .delay (10000,10000,10000) L_0x24c7860/d; -L_0x24c7d60/d .functor AND 1, L_0x24c8eb0, L_0x24c7860, C4<1>, C4<1>; -L_0x24c7d60 .delay (20000,20000,20000) L_0x24c7d60/d; -L_0x24c7e50/d .functor AND 1, L_0x24c6790, L_0x24c8110, C4<1>, C4<1>; -L_0x24c7e50 .delay (20000,20000,20000) L_0x24c7e50/d; -L_0x24c7f40/d .functor OR 1, L_0x24c7d60, L_0x24c7e50, C4<0>, C4<0>; -L_0x24c7f40 .delay (20000,20000,20000) L_0x24c7f40/d; -v0x2453fe0_0 .net "S", 0 0, L_0x24c8110; 1 drivers -v0x2454080_0 .alias "in0", 0 0, v0x2454710_0; -v0x2454120_0 .alias "in1", 0 0, v0x2454be0_0; -v0x24541c0_0 .net "nS", 0 0, L_0x24c7860; 1 drivers -v0x2454270_0 .net "out0", 0 0, L_0x24c7d60; 1 drivers -v0x2454310_0 .net "out1", 0 0, L_0x24c7e50; 1 drivers -v0x24543f0_0 .alias "outfinal", 0 0, v0x24547c0_0; -S_0x2452af0 .scope generate, "addbits[13]" "addbits[13]" 2 230, 2 230, S_0x2426ca0; - .timescale -9 -12; -P_0x2452508 .param/l "i" 2 230, +C4<01101>; -S_0x2452c60 .scope module, "attempt" "MiddleAddSubSLT" 2 232, 2 89, S_0x2452af0; - .timescale -9 -12; -L_0x24c8c70/d .functor NOT 1, L_0x24c9180, C4<0>, C4<0>, C4<0>; -L_0x24c8c70 .delay (10000,10000,10000) L_0x24c8c70/d; -L_0x24c96b0/d .functor NOT 1, L_0x24c9770, C4<0>, C4<0>, C4<0>; -L_0x24c96b0 .delay (10000,10000,10000) L_0x24c96b0/d; -L_0x24c9810/d .functor AND 1, L_0x24c9950, L_0x24c96b0, C4<1>, C4<1>; -L_0x24c9810 .delay (20000,20000,20000) L_0x24c9810/d; -L_0x24c99f0/d .functor XOR 1, L_0x24c90e0, L_0x24c9440, C4<0>, C4<0>; -L_0x24c99f0 .delay (40000,40000,40000) L_0x24c99f0/d; -L_0x24c9ae0/d .functor XOR 1, L_0x24c99f0, L_0x24bfa50, C4<0>, C4<0>; -L_0x24c9ae0 .delay (40000,40000,40000) L_0x24c9ae0/d; -L_0x24c9bd0/d .functor AND 1, L_0x24c90e0, L_0x24c9440, C4<1>, C4<1>; -L_0x24c9bd0 .delay (20000,20000,20000) L_0x24c9bd0/d; -L_0x24c9d40/d .functor AND 1, L_0x24c99f0, L_0x24bfa50, C4<1>, C4<1>; -L_0x24c9d40 .delay (20000,20000,20000) L_0x24c9d40/d; -L_0x24c9e30/d .functor OR 1, L_0x24c9bd0, L_0x24c9d40, C4<0>, C4<0>; -L_0x24c9e30 .delay (20000,20000,20000) L_0x24c9e30/d; -v0x24532f0_0 .net "A", 0 0, L_0x24c90e0; 1 drivers -v0x24533b0_0 .net "AandB", 0 0, L_0x24c9bd0; 1 drivers -v0x2453450_0 .net "AddSubSLTSum", 0 0, L_0x24c9ae0; 1 drivers -v0x24534f0_0 .net "AxorB", 0 0, L_0x24c99f0; 1 drivers -v0x2453570_0 .net "B", 0 0, L_0x24c9180; 1 drivers -v0x2453620_0 .net "BornB", 0 0, L_0x24c9440; 1 drivers -v0x24536e0_0 .net "CINandAxorB", 0 0, L_0x24c9d40; 1 drivers -v0x2453760_0 .alias "Command", 2 0, v0x2463430_0; -v0x24537e0_0 .net *"_s3", 0 0, L_0x24c9770; 1 drivers -v0x2453860_0 .net *"_s5", 0 0, L_0x24c9950; 1 drivers -v0x2453900_0 .net "carryin", 0 0, L_0x24bfa50; 1 drivers -v0x24539a0_0 .net "carryout", 0 0, L_0x24c9e30; 1 drivers -v0x2453a40_0 .net "nB", 0 0, L_0x24c8c70; 1 drivers -v0x2453af0_0 .net "nCmd2", 0 0, L_0x24c96b0; 1 drivers -v0x2453bf0_0 .net "subtract", 0 0, L_0x24c9810; 1 drivers -L_0x24c9610 .part C4, 0, 1; -L_0x24c9770 .part C4, 2, 1; -L_0x24c9950 .part C4, 0, 1; -S_0x2452d50 .scope module, "mux0" "TwoInMux" 2 105, 2 8, S_0x2452c60; - .timescale -9 -12; -L_0x24c8dd0/d .functor NOT 1, L_0x24c9610, C4<0>, C4<0>, C4<0>; -L_0x24c8dd0 .delay (10000,10000,10000) L_0x24c8dd0/d; -L_0x24c9240/d .functor AND 1, L_0x24c9180, L_0x24c8dd0, C4<1>, C4<1>; -L_0x24c9240 .delay (20000,20000,20000) L_0x24c9240/d; -L_0x24c9330/d .functor AND 1, L_0x24c8c70, L_0x24c9610, C4<1>, C4<1>; -L_0x24c9330 .delay (20000,20000,20000) L_0x24c9330/d; -L_0x24c9440/d .functor OR 1, L_0x24c9240, L_0x24c9330, C4<0>, C4<0>; -L_0x24c9440 .delay (20000,20000,20000) L_0x24c9440/d; -v0x2452e40_0 .net "S", 0 0, L_0x24c9610; 1 drivers -v0x2452ee0_0 .alias "in0", 0 0, v0x2453570_0; -v0x2452f80_0 .alias "in1", 0 0, v0x2453a40_0; -v0x2453020_0 .net "nS", 0 0, L_0x24c8dd0; 1 drivers -v0x24530d0_0 .net "out0", 0 0, L_0x24c9240; 1 drivers -v0x2453170_0 .net "out1", 0 0, L_0x24c9330; 1 drivers -v0x2453250_0 .alias "outfinal", 0 0, v0x2453620_0; -S_0x2451950 .scope generate, "addbits[14]" "addbits[14]" 2 230, 2 230, S_0x2426ca0; - .timescale -9 -12; -P_0x2451368 .param/l "i" 2 230, +C4<01110>; -S_0x2451ac0 .scope module, "attempt" "MiddleAddSubSLT" 2 232, 2 89, S_0x2451950; - .timescale -9 -12; -L_0x24bfaf0/d .functor NOT 1, L_0x24ca770, C4<0>, C4<0>, C4<0>; -L_0x24bfaf0 .delay (10000,10000,10000) L_0x24bfaf0/d; -L_0x24cadd0/d .functor NOT 1, L_0x24cae90, C4<0>, C4<0>, C4<0>; -L_0x24cadd0 .delay (10000,10000,10000) L_0x24cadd0/d; -L_0x24caf30/d .functor AND 1, L_0x24cb070, L_0x24cadd0, C4<1>, C4<1>; -L_0x24caf30 .delay (20000,20000,20000) L_0x24caf30/d; -L_0x24cb110/d .functor XOR 1, L_0x24ca6d0, L_0x24cab60, C4<0>, C4<0>; -L_0x24cb110 .delay (40000,40000,40000) L_0x24cb110/d; -L_0x24cb200/d .functor XOR 1, L_0x24cb110, L_0x24cbbc0, C4<0>, C4<0>; -L_0x24cb200 .delay (40000,40000,40000) L_0x24cb200/d; -L_0x24cb2f0/d .functor AND 1, L_0x24ca6d0, L_0x24cab60, C4<1>, C4<1>; -L_0x24cb2f0 .delay (20000,20000,20000) L_0x24cb2f0/d; -L_0x24cb460/d .functor AND 1, L_0x24cb110, L_0x24cbbc0, C4<1>, C4<1>; -L_0x24cb460 .delay (20000,20000,20000) L_0x24cb460/d; -L_0x24cb550/d .functor OR 1, L_0x24cb2f0, L_0x24cb460, C4<0>, C4<0>; -L_0x24cb550 .delay (20000,20000,20000) L_0x24cb550/d; -v0x2452150_0 .net "A", 0 0, L_0x24ca6d0; 1 drivers -v0x2452210_0 .net "AandB", 0 0, L_0x24cb2f0; 1 drivers -v0x24522b0_0 .net "AddSubSLTSum", 0 0, L_0x24cb200; 1 drivers -v0x2452350_0 .net "AxorB", 0 0, L_0x24cb110; 1 drivers -v0x24523d0_0 .net "B", 0 0, L_0x24ca770; 1 drivers -v0x2452480_0 .net "BornB", 0 0, L_0x24cab60; 1 drivers -v0x2452540_0 .net "CINandAxorB", 0 0, L_0x24cb460; 1 drivers -v0x24525c0_0 .alias "Command", 2 0, v0x2463430_0; -v0x2452640_0 .net *"_s3", 0 0, L_0x24cae90; 1 drivers -v0x24526c0_0 .net *"_s5", 0 0, L_0x24cb070; 1 drivers -v0x2452760_0 .net "carryin", 0 0, L_0x24cbbc0; 1 drivers -v0x2452800_0 .net "carryout", 0 0, L_0x24cb550; 1 drivers -v0x24528a0_0 .net "nB", 0 0, L_0x24bfaf0; 1 drivers -v0x2452950_0 .net "nCmd2", 0 0, L_0x24cadd0; 1 drivers -v0x2452a50_0 .net "subtract", 0 0, L_0x24caf30; 1 drivers -L_0x24cad30 .part C4, 0, 1; -L_0x24cae90 .part C4, 2, 1; -L_0x24cb070 .part C4, 0, 1; -S_0x2451bb0 .scope module, "mux0" "TwoInMux" 2 105, 2 8, S_0x2451ac0; - .timescale -9 -12; -L_0x24ca880/d .functor NOT 1, L_0x24cad30, C4<0>, C4<0>, C4<0>; -L_0x24ca880 .delay (10000,10000,10000) L_0x24ca880/d; -L_0x24ca940/d .functor AND 1, L_0x24ca770, L_0x24ca880, C4<1>, C4<1>; -L_0x24ca940 .delay (20000,20000,20000) L_0x24ca940/d; -L_0x24caa50/d .functor AND 1, L_0x24bfaf0, L_0x24cad30, C4<1>, C4<1>; -L_0x24caa50 .delay (20000,20000,20000) L_0x24caa50/d; -L_0x24cab60/d .functor OR 1, L_0x24ca940, L_0x24caa50, C4<0>, C4<0>; -L_0x24cab60 .delay (20000,20000,20000) L_0x24cab60/d; -v0x2451ca0_0 .net "S", 0 0, L_0x24cad30; 1 drivers -v0x2451d40_0 .alias "in0", 0 0, v0x24523d0_0; -v0x2451de0_0 .alias "in1", 0 0, v0x24528a0_0; -v0x2451e80_0 .net "nS", 0 0, L_0x24ca880; 1 drivers -v0x2451f30_0 .net "out0", 0 0, L_0x24ca940; 1 drivers -v0x2451fd0_0 .net "out1", 0 0, L_0x24caa50; 1 drivers -v0x24520b0_0 .alias "outfinal", 0 0, v0x2452480_0; -S_0x24507b0 .scope generate, "addbits[15]" "addbits[15]" 2 230, 2 230, S_0x2426ca0; - .timescale -9 -12; -P_0x24501c8 .param/l "i" 2 230, +C4<01111>; -S_0x2450920 .scope module, "attempt" "MiddleAddSubSLT" 2 232, 2 89, S_0x24507b0; - .timescale -9 -12; -L_0x24cb890/d .functor NOT 1, L_0x24cd070, C4<0>, C4<0>, C4<0>; -L_0x24cb890 .delay (10000,10000,10000) L_0x24cb890/d; -L_0x24cc2e0/d .functor NOT 1, L_0x24cc3a0, C4<0>, C4<0>, C4<0>; -L_0x24cc2e0 .delay (10000,10000,10000) L_0x24cc2e0/d; -L_0x24cc440/d .functor AND 1, L_0x24cc580, L_0x24cc2e0, C4<1>, C4<1>; -L_0x24cc440 .delay (20000,20000,20000) L_0x24cc440/d; -L_0x24cc620/d .functor XOR 1, L_0x24c2340, L_0x24cc070, C4<0>, C4<0>; -L_0x24cc620 .delay (40000,40000,40000) L_0x24cc620/d; -L_0x24cc710/d .functor XOR 1, L_0x24cc620, L_0x24cd1a0, C4<0>, C4<0>; -L_0x24cc710 .delay (40000,40000,40000) L_0x24cc710/d; -L_0x24cc800/d .functor AND 1, L_0x24c2340, L_0x24cc070, C4<1>, C4<1>; -L_0x24cc800 .delay (20000,20000,20000) L_0x24cc800/d; -L_0x24cc970/d .functor AND 1, L_0x24cc620, L_0x24cd1a0, C4<1>, C4<1>; -L_0x24cc970 .delay (20000,20000,20000) L_0x24cc970/d; -L_0x24cca60/d .functor OR 1, L_0x24cc800, L_0x24cc970, C4<0>, C4<0>; -L_0x24cca60 .delay (20000,20000,20000) L_0x24cca60/d; -v0x2450fb0_0 .net "A", 0 0, L_0x24c2340; 1 drivers -v0x2451070_0 .net "AandB", 0 0, L_0x24cc800; 1 drivers -v0x2451110_0 .net "AddSubSLTSum", 0 0, L_0x24cc710; 1 drivers -v0x24511b0_0 .net "AxorB", 0 0, L_0x24cc620; 1 drivers -v0x2451230_0 .net "B", 0 0, L_0x24cd070; 1 drivers -v0x24512e0_0 .net "BornB", 0 0, L_0x24cc070; 1 drivers -v0x24513a0_0 .net "CINandAxorB", 0 0, L_0x24cc970; 1 drivers -v0x2451420_0 .alias "Command", 2 0, v0x2463430_0; -v0x24514a0_0 .net *"_s3", 0 0, L_0x24cc3a0; 1 drivers -v0x2451520_0 .net *"_s5", 0 0, L_0x24cc580; 1 drivers -v0x24515c0_0 .net "carryin", 0 0, L_0x24cd1a0; 1 drivers -v0x2451660_0 .net "carryout", 0 0, L_0x24cca60; 1 drivers -v0x2451700_0 .net "nB", 0 0, L_0x24cb890; 1 drivers -v0x24517b0_0 .net "nCmd2", 0 0, L_0x24cc2e0; 1 drivers -v0x24518b0_0 .net "subtract", 0 0, L_0x24cc440; 1 drivers -L_0x24cc240 .part C4, 0, 1; -L_0x24cc3a0 .part C4, 2, 1; -L_0x24cc580 .part C4, 0, 1; -S_0x2450a10 .scope module, "mux0" "TwoInMux" 2 105, 2 8, S_0x2450920; - .timescale -9 -12; -L_0x24cb9a0/d .functor NOT 1, L_0x24cc240, C4<0>, C4<0>, C4<0>; -L_0x24cb9a0 .delay (10000,10000,10000) L_0x24cb9a0/d; -L_0x24cba60/d .functor AND 1, L_0x24cd070, L_0x24cb9a0, C4<1>, C4<1>; -L_0x24cba60 .delay (20000,20000,20000) L_0x24cba60/d; -L_0x24cbf60/d .functor AND 1, L_0x24cb890, L_0x24cc240, C4<1>, C4<1>; -L_0x24cbf60 .delay (20000,20000,20000) L_0x24cbf60/d; -L_0x24cc070/d .functor OR 1, L_0x24cba60, L_0x24cbf60, C4<0>, C4<0>; -L_0x24cc070 .delay (20000,20000,20000) L_0x24cc070/d; -v0x2450b00_0 .net "S", 0 0, L_0x24cc240; 1 drivers -v0x2450ba0_0 .alias "in0", 0 0, v0x2451230_0; -v0x2450c40_0 .alias "in1", 0 0, v0x2451700_0; -v0x2450ce0_0 .net "nS", 0 0, L_0x24cb9a0; 1 drivers -v0x2450d90_0 .net "out0", 0 0, L_0x24cba60; 1 drivers -v0x2450e30_0 .net "out1", 0 0, L_0x24cbf60; 1 drivers -v0x2450f10_0 .alias "outfinal", 0 0, v0x24512e0_0; -S_0x244f610 .scope generate, "addbits[16]" "addbits[16]" 2 230, 2 230, S_0x2426ca0; - .timescale -9 -12; -P_0x244f028 .param/l "i" 2 230, +C4<010000>; -S_0x244f780 .scope module, "attempt" "MiddleAddSubSLT" 2 232, 2 89, S_0x244f610; - .timescale -9 -12; -L_0x24ccda0/d .functor NOT 1, L_0x24cd3d0, C4<0>, C4<0>, C4<0>; -L_0x24ccda0 .delay (10000,10000,10000) L_0x24ccda0/d; -L_0x24cd8f0/d .functor NOT 1, L_0x24cd9b0, C4<0>, C4<0>, C4<0>; -L_0x24cd8f0 .delay (10000,10000,10000) L_0x24cd8f0/d; -L_0x24cda50/d .functor AND 1, L_0x24cdb90, L_0x24cd8f0, C4<1>, C4<1>; -L_0x24cda50 .delay (20000,20000,20000) L_0x24cda50/d; -L_0x24cdc30/d .functor XOR 1, L_0x24cd330, L_0x24cd680, C4<0>, C4<0>; -L_0x24cdc30 .delay (40000,40000,40000) L_0x24cdc30/d; -L_0x24cdd20/d .functor XOR 1, L_0x24cdc30, L_0x24ce6b0, C4<0>, C4<0>; -L_0x24cdd20 .delay (40000,40000,40000) L_0x24cdd20/d; -L_0x24cde10/d .functor AND 1, L_0x24cd330, L_0x24cd680, C4<1>, C4<1>; -L_0x24cde10 .delay (20000,20000,20000) L_0x24cde10/d; -L_0x24cdf80/d .functor AND 1, L_0x24cdc30, L_0x24ce6b0, C4<1>, C4<1>; -L_0x24cdf80 .delay (20000,20000,20000) L_0x24cdf80/d; -L_0x24ce070/d .functor OR 1, L_0x24cde10, L_0x24cdf80, C4<0>, C4<0>; -L_0x24ce070 .delay (20000,20000,20000) L_0x24ce070/d; -v0x244fe10_0 .net "A", 0 0, L_0x24cd330; 1 drivers -v0x244fed0_0 .net "AandB", 0 0, L_0x24cde10; 1 drivers -v0x244ff70_0 .net "AddSubSLTSum", 0 0, L_0x24cdd20; 1 drivers -v0x2450010_0 .net "AxorB", 0 0, L_0x24cdc30; 1 drivers -v0x2450090_0 .net "B", 0 0, L_0x24cd3d0; 1 drivers -v0x2450140_0 .net "BornB", 0 0, L_0x24cd680; 1 drivers -v0x2450200_0 .net "CINandAxorB", 0 0, L_0x24cdf80; 1 drivers -v0x2450280_0 .alias "Command", 2 0, v0x2463430_0; -v0x2450300_0 .net *"_s3", 0 0, L_0x24cd9b0; 1 drivers -v0x2450380_0 .net *"_s5", 0 0, L_0x24cdb90; 1 drivers -v0x2450420_0 .net "carryin", 0 0, L_0x24ce6b0; 1 drivers -v0x24504c0_0 .net "carryout", 0 0, L_0x24ce070; 1 drivers -v0x2450560_0 .net "nB", 0 0, L_0x24ccda0; 1 drivers -v0x2450610_0 .net "nCmd2", 0 0, L_0x24cd8f0; 1 drivers -v0x2450710_0 .net "subtract", 0 0, L_0x24cda50; 1 drivers -L_0x24cd850 .part C4, 0, 1; -L_0x24cd9b0 .part C4, 2, 1; -L_0x24cdb90 .part C4, 0, 1; -S_0x244f870 .scope module, "mux0" "TwoInMux" 2 105, 2 8, S_0x244f780; - .timescale -9 -12; -L_0x24ccee0/d .functor NOT 1, L_0x24cd850, C4<0>, C4<0>, C4<0>; -L_0x24ccee0 .delay (10000,10000,10000) L_0x24ccee0/d; -L_0x24ccfa0/d .functor AND 1, L_0x24cd3d0, L_0x24ccee0, C4<1>, C4<1>; -L_0x24ccfa0 .delay (20000,20000,20000) L_0x24ccfa0/d; -L_0x24cd570/d .functor AND 1, L_0x24ccda0, L_0x24cd850, C4<1>, C4<1>; -L_0x24cd570 .delay (20000,20000,20000) L_0x24cd570/d; -L_0x24cd680/d .functor OR 1, L_0x24ccfa0, L_0x24cd570, C4<0>, C4<0>; -L_0x24cd680 .delay (20000,20000,20000) L_0x24cd680/d; -v0x244f960_0 .net "S", 0 0, L_0x24cd850; 1 drivers -v0x244fa00_0 .alias "in0", 0 0, v0x2450090_0; -v0x244faa0_0 .alias "in1", 0 0, v0x2450560_0; -v0x244fb40_0 .net "nS", 0 0, L_0x24ccee0; 1 drivers -v0x244fbf0_0 .net "out0", 0 0, L_0x24ccfa0; 1 drivers -v0x244fc90_0 .net "out1", 0 0, L_0x24cd570; 1 drivers -v0x244fd70_0 .alias "outfinal", 0 0, v0x2450140_0; -S_0x244e470 .scope generate, "addbits[17]" "addbits[17]" 2 230, 2 230, S_0x2426ca0; - .timescale -9 -12; -P_0x244de88 .param/l "i" 2 230, +C4<010001>; -S_0x244e5e0 .scope module, "attempt" "MiddleAddSubSLT" 2 232, 2 89, S_0x244e470; - .timescale -9 -12; -L_0x24bcd50/d .functor NOT 1, L_0x24cecf0, C4<0>, C4<0>, C4<0>; -L_0x24bcd50 .delay (10000,10000,10000) L_0x24bcd50/d; -L_0x24cef60/d .functor NOT 1, L_0x24cf000, C4<0>, C4<0>, C4<0>; -L_0x24cef60 .delay (10000,10000,10000) L_0x24cef60/d; -L_0x24cf0a0/d .functor AND 1, L_0x24cf1e0, L_0x24cef60, C4<1>, C4<1>; -L_0x24cf0a0 .delay (20000,20000,20000) L_0x24cf0a0/d; -L_0x24cf280/d .functor XOR 1, L_0x24cec50, L_0x24ce550, C4<0>, C4<0>; -L_0x24cf280 .delay (40000,40000,40000) L_0x24cf280/d; -L_0x24cf370/d .functor XOR 1, L_0x24cf280, L_0x24cfd10, C4<0>, C4<0>; -L_0x24cf370 .delay (40000,40000,40000) L_0x24cf370/d; -L_0x24cf460/d .functor AND 1, L_0x24cec50, L_0x24ce550, C4<1>, C4<1>; -L_0x24cf460 .delay (20000,20000,20000) L_0x24cf460/d; -L_0x24cf5d0/d .functor AND 1, L_0x24cf280, L_0x24cfd10, C4<1>, C4<1>; -L_0x24cf5d0 .delay (20000,20000,20000) L_0x24cf5d0/d; -L_0x24cf6c0/d .functor OR 1, L_0x24cf460, L_0x24cf5d0, C4<0>, C4<0>; -L_0x24cf6c0 .delay (20000,20000,20000) L_0x24cf6c0/d; -v0x244ec70_0 .net "A", 0 0, L_0x24cec50; 1 drivers -v0x244ed30_0 .net "AandB", 0 0, L_0x24cf460; 1 drivers -v0x244edd0_0 .net "AddSubSLTSum", 0 0, L_0x24cf370; 1 drivers -v0x244ee70_0 .net "AxorB", 0 0, L_0x24cf280; 1 drivers -v0x244eef0_0 .net "B", 0 0, L_0x24cecf0; 1 drivers -v0x244efa0_0 .net "BornB", 0 0, L_0x24ce550; 1 drivers -v0x244f060_0 .net "CINandAxorB", 0 0, L_0x24cf5d0; 1 drivers -v0x244f0e0_0 .alias "Command", 2 0, v0x2463430_0; -v0x244f160_0 .net *"_s3", 0 0, L_0x24cf000; 1 drivers -v0x244f1e0_0 .net *"_s5", 0 0, L_0x24cf1e0; 1 drivers -v0x244f280_0 .net "carryin", 0 0, L_0x24cfd10; 1 drivers -v0x244f320_0 .net "carryout", 0 0, L_0x24cf6c0; 1 drivers -v0x244f3c0_0 .net "nB", 0 0, L_0x24bcd50; 1 drivers -v0x244f470_0 .net "nCmd2", 0 0, L_0x24cef60; 1 drivers -v0x244f570_0 .net "subtract", 0 0, L_0x24cf0a0; 1 drivers -L_0x24ceec0 .part C4, 0, 1; -L_0x24cf000 .part C4, 2, 1; -L_0x24cf1e0 .part C4, 0, 1; -S_0x244e6d0 .scope module, "mux0" "TwoInMux" 2 105, 2 8, S_0x244e5e0; - .timescale -9 -12; -L_0x24c3c20/d .functor NOT 1, L_0x24ceec0, C4<0>, C4<0>, C4<0>; -L_0x24c3c20 .delay (10000,10000,10000) L_0x24c3c20/d; -L_0x24c3ce0/d .functor AND 1, L_0x24cecf0, L_0x24c3c20, C4<1>, C4<1>; -L_0x24c3ce0 .delay (20000,20000,20000) L_0x24c3ce0/d; -L_0x24ce440/d .functor AND 1, L_0x24bcd50, L_0x24ceec0, C4<1>, C4<1>; -L_0x24ce440 .delay (20000,20000,20000) L_0x24ce440/d; -L_0x24ce550/d .functor OR 1, L_0x24c3ce0, L_0x24ce440, C4<0>, C4<0>; -L_0x24ce550 .delay (20000,20000,20000) L_0x24ce550/d; -v0x244e7c0_0 .net "S", 0 0, L_0x24ceec0; 1 drivers -v0x244e860_0 .alias "in0", 0 0, v0x244eef0_0; -v0x244e900_0 .alias "in1", 0 0, v0x244f3c0_0; -v0x244e9a0_0 .net "nS", 0 0, L_0x24c3c20; 1 drivers -v0x244ea50_0 .net "out0", 0 0, L_0x24c3ce0; 1 drivers -v0x244eaf0_0 .net "out1", 0 0, L_0x24ce440; 1 drivers -v0x244ebd0_0 .alias "outfinal", 0 0, v0x244efa0_0; -S_0x244d2d0 .scope generate, "addbits[18]" "addbits[18]" 2 230, 2 230, S_0x2426ca0; - .timescale -9 -12; -P_0x244cce8 .param/l "i" 2 230, +C4<010010>; -S_0x244d440 .scope module, "attempt" "MiddleAddSubSLT" 2 232, 2 89, S_0x244d2d0; - .timescale -9 -12; -L_0x24cf9e0/d .functor NOT 1, L_0x24cff40, C4<0>, C4<0>, C4<0>; -L_0x24cf9e0 .delay (10000,10000,10000) L_0x24cf9e0/d; -L_0x24d03d0/d .functor NOT 1, L_0x24d0470, C4<0>, C4<0>, C4<0>; -L_0x24d03d0 .delay (10000,10000,10000) L_0x24d03d0/d; -L_0x24d0510/d .functor AND 1, L_0x24d0650, L_0x24d03d0, C4<1>, C4<1>; -L_0x24d0510 .delay (20000,20000,20000) L_0x24d0510/d; -L_0x24d06f0/d .functor XOR 1, L_0x24cfea0, L_0x24d01a0, C4<0>, C4<0>; -L_0x24d06f0 .delay (40000,40000,40000) L_0x24d06f0/d; -L_0x24d07e0/d .functor XOR 1, L_0x24d06f0, L_0x24d11b0, C4<0>, C4<0>; -L_0x24d07e0 .delay (40000,40000,40000) L_0x24d07e0/d; -L_0x24d08d0/d .functor AND 1, L_0x24cfea0, L_0x24d01a0, C4<1>, C4<1>; -L_0x24d08d0 .delay (20000,20000,20000) L_0x24d08d0/d; -L_0x24d0a40/d .functor AND 1, L_0x24d06f0, L_0x24d11b0, C4<1>, C4<1>; -L_0x24d0a40 .delay (20000,20000,20000) L_0x24d0a40/d; -L_0x24d0b30/d .functor OR 1, L_0x24d08d0, L_0x24d0a40, C4<0>, C4<0>; -L_0x24d0b30 .delay (20000,20000,20000) L_0x24d0b30/d; -v0x244dad0_0 .net "A", 0 0, L_0x24cfea0; 1 drivers -v0x244db90_0 .net "AandB", 0 0, L_0x24d08d0; 1 drivers -v0x244dc30_0 .net "AddSubSLTSum", 0 0, L_0x24d07e0; 1 drivers -v0x244dcd0_0 .net "AxorB", 0 0, L_0x24d06f0; 1 drivers -v0x244dd50_0 .net "B", 0 0, L_0x24cff40; 1 drivers -v0x244de00_0 .net "BornB", 0 0, L_0x24d01a0; 1 drivers -v0x244dec0_0 .net "CINandAxorB", 0 0, L_0x24d0a40; 1 drivers -v0x244df40_0 .alias "Command", 2 0, v0x2463430_0; -v0x244dfc0_0 .net *"_s3", 0 0, L_0x24d0470; 1 drivers -v0x244e040_0 .net *"_s5", 0 0, L_0x24d0650; 1 drivers -v0x244e0e0_0 .net "carryin", 0 0, L_0x24d11b0; 1 drivers -v0x244e180_0 .net "carryout", 0 0, L_0x24d0b30; 1 drivers -v0x244e220_0 .net "nB", 0 0, L_0x24cf9e0; 1 drivers -v0x244e2d0_0 .net "nCmd2", 0 0, L_0x24d03d0; 1 drivers -v0x244e3d0_0 .net "subtract", 0 0, L_0x24d0510; 1 drivers -L_0x24d0330 .part C4, 0, 1; -L_0x24d0470 .part C4, 2, 1; -L_0x24d0650 .part C4, 0, 1; -S_0x244d530 .scope module, "mux0" "TwoInMux" 2 105, 2 8, S_0x244d440; - .timescale -9 -12; -L_0x24cfaf0/d .functor NOT 1, L_0x24d0330, C4<0>, C4<0>, C4<0>; -L_0x24cfaf0 .delay (10000,10000,10000) L_0x24cfaf0/d; -L_0x24cfbb0/d .functor AND 1, L_0x24cff40, L_0x24cfaf0, C4<1>, C4<1>; -L_0x24cfbb0 .delay (20000,20000,20000) L_0x24cfbb0/d; -L_0x24d00f0/d .functor AND 1, L_0x24cf9e0, L_0x24d0330, C4<1>, C4<1>; -L_0x24d00f0 .delay (20000,20000,20000) L_0x24d00f0/d; -L_0x24d01a0/d .functor OR 1, L_0x24cfbb0, L_0x24d00f0, C4<0>, C4<0>; -L_0x24d01a0 .delay (20000,20000,20000) L_0x24d01a0/d; -v0x244d620_0 .net "S", 0 0, L_0x24d0330; 1 drivers -v0x244d6c0_0 .alias "in0", 0 0, v0x244dd50_0; -v0x244d760_0 .alias "in1", 0 0, v0x244e220_0; -v0x244d800_0 .net "nS", 0 0, L_0x24cfaf0; 1 drivers -v0x244d8b0_0 .net "out0", 0 0, L_0x24cfbb0; 1 drivers -v0x244d950_0 .net "out1", 0 0, L_0x24d00f0; 1 drivers -v0x244da30_0 .alias "outfinal", 0 0, v0x244de00_0; -S_0x244c130 .scope generate, "addbits[19]" "addbits[19]" 2 230, 2 230, S_0x2426ca0; - .timescale -9 -12; -P_0x244bb48 .param/l "i" 2 230, +C4<010011>; -S_0x244c2a0 .scope module, "attempt" "MiddleAddSubSLT" 2 232, 2 89, S_0x244c130; - .timescale -9 -12; -L_0x24d0070/d .functor NOT 1, L_0x24d13e0, C4<0>, C4<0>, C4<0>; -L_0x24d0070 .delay (10000,10000,10000) L_0x24d0070/d; -L_0x24d1880/d .functor NOT 1, L_0x24d1920, C4<0>, C4<0>, C4<0>; -L_0x24d1880 .delay (10000,10000,10000) L_0x24d1880/d; -L_0x24d19c0/d .functor AND 1, L_0x24d1b00, L_0x24d1880, C4<1>, C4<1>; -L_0x24d19c0 .delay (20000,20000,20000) L_0x24d19c0/d; -L_0x24d1ba0/d .functor XOR 1, L_0x24d1340, L_0x24d1650, C4<0>, C4<0>; -L_0x24d1ba0 .delay (40000,40000,40000) L_0x24d1ba0/d; -L_0x24d1c90/d .functor XOR 1, L_0x24d1ba0, L_0x24d1510, C4<0>, C4<0>; -L_0x24d1c90 .delay (40000,40000,40000) L_0x24d1c90/d; -L_0x24d1d80/d .functor AND 1, L_0x24d1340, L_0x24d1650, C4<1>, C4<1>; -L_0x24d1d80 .delay (20000,20000,20000) L_0x24d1d80/d; -L_0x24d1ef0/d .functor AND 1, L_0x24d1ba0, L_0x24d1510, C4<1>, C4<1>; -L_0x24d1ef0 .delay (20000,20000,20000) L_0x24d1ef0/d; -L_0x24d1fe0/d .functor OR 1, L_0x24d1d80, L_0x24d1ef0, C4<0>, C4<0>; -L_0x24d1fe0 .delay (20000,20000,20000) L_0x24d1fe0/d; -v0x244c930_0 .net "A", 0 0, L_0x24d1340; 1 drivers -v0x244c9f0_0 .net "AandB", 0 0, L_0x24d1d80; 1 drivers -v0x244ca90_0 .net "AddSubSLTSum", 0 0, L_0x24d1c90; 1 drivers -v0x244cb30_0 .net "AxorB", 0 0, L_0x24d1ba0; 1 drivers -v0x244cbb0_0 .net "B", 0 0, L_0x24d13e0; 1 drivers -v0x244cc60_0 .net "BornB", 0 0, L_0x24d1650; 1 drivers -v0x244cd20_0 .net "CINandAxorB", 0 0, L_0x24d1ef0; 1 drivers -v0x244cda0_0 .alias "Command", 2 0, v0x2463430_0; -v0x244ce20_0 .net *"_s3", 0 0, L_0x24d1920; 1 drivers -v0x244cea0_0 .net *"_s5", 0 0, L_0x24d1b00; 1 drivers -v0x244cf40_0 .net "carryin", 0 0, L_0x24d1510; 1 drivers -v0x244cfe0_0 .net "carryout", 0 0, L_0x24d1fe0; 1 drivers -v0x244d080_0 .net "nB", 0 0, L_0x24d0070; 1 drivers -v0x244d130_0 .net "nCmd2", 0 0, L_0x24d1880; 1 drivers -v0x244d230_0 .net "subtract", 0 0, L_0x24d19c0; 1 drivers -L_0x24d17e0 .part C4, 0, 1; -L_0x24d1920 .part C4, 2, 1; -L_0x24d1b00 .part C4, 0, 1; -S_0x244c390 .scope module, "mux0" "TwoInMux" 2 105, 2 8, S_0x244c2a0; - .timescale -9 -12; -L_0x24d0f30/d .functor NOT 1, L_0x24d17e0, C4<0>, C4<0>, C4<0>; -L_0x24d0f30 .delay (10000,10000,10000) L_0x24d0f30/d; -L_0x24d0ff0/d .functor AND 1, L_0x24d13e0, L_0x24d0f30, C4<1>, C4<1>; -L_0x24d0ff0 .delay (20000,20000,20000) L_0x24d0ff0/d; -L_0x24d1100/d .functor AND 1, L_0x24d0070, L_0x24d17e0, C4<1>, C4<1>; -L_0x24d1100 .delay (20000,20000,20000) L_0x24d1100/d; -L_0x24d1650/d .functor OR 1, L_0x24d0ff0, L_0x24d1100, C4<0>, C4<0>; -L_0x24d1650 .delay (20000,20000,20000) L_0x24d1650/d; -v0x244c480_0 .net "S", 0 0, L_0x24d17e0; 1 drivers -v0x244c520_0 .alias "in0", 0 0, v0x244cbb0_0; -v0x244c5c0_0 .alias "in1", 0 0, v0x244d080_0; -v0x244c660_0 .net "nS", 0 0, L_0x24d0f30; 1 drivers -v0x244c710_0 .net "out0", 0 0, L_0x24d0ff0; 1 drivers -v0x244c7b0_0 .net "out1", 0 0, L_0x24d1100; 1 drivers -v0x244c890_0 .alias "outfinal", 0 0, v0x244cc60_0; -S_0x244af90 .scope generate, "addbits[20]" "addbits[20]" 2 230, 2 230, S_0x2426ca0; - .timescale -9 -12; -P_0x244a9a8 .param/l "i" 2 230, +C4<010100>; -S_0x244b100 .scope module, "attempt" "MiddleAddSubSLT" 2 232, 2 89, S_0x244af90; - .timescale -9 -12; -L_0x24d26a0/d .functor NOT 1, L_0x24d2490, C4<0>, C4<0>, C4<0>; -L_0x24d26a0 .delay (10000,10000,10000) L_0x24d26a0/d; -L_0x24d2c50/d .functor NOT 1, L_0x24d2cf0, C4<0>, C4<0>, C4<0>; -L_0x24d2c50 .delay (10000,10000,10000) L_0x24d2c50/d; -L_0x24d2d90/d .functor AND 1, L_0x24d2ed0, L_0x24d2c50, C4<1>, C4<1>; -L_0x24d2d90 .delay (20000,20000,20000) L_0x24d2d90/d; -L_0x24d2f70/d .functor XOR 1, L_0x24d23f0, L_0x24d2a20, C4<0>, C4<0>; -L_0x24d2f70 .delay (40000,40000,40000) L_0x24d2f70/d; -L_0x24d3060/d .functor XOR 1, L_0x24d2f70, L_0x24d25c0, C4<0>, C4<0>; -L_0x24d3060 .delay (40000,40000,40000) L_0x24d3060/d; -L_0x24d3150/d .functor AND 1, L_0x24d23f0, L_0x24d2a20, C4<1>, C4<1>; -L_0x24d3150 .delay (20000,20000,20000) L_0x24d3150/d; -L_0x24d32c0/d .functor AND 1, L_0x24d2f70, L_0x24d25c0, C4<1>, C4<1>; -L_0x24d32c0 .delay (20000,20000,20000) L_0x24d32c0/d; -L_0x24d33b0/d .functor OR 1, L_0x24d3150, L_0x24d32c0, C4<0>, C4<0>; -L_0x24d33b0 .delay (20000,20000,20000) L_0x24d33b0/d; -v0x244b790_0 .net "A", 0 0, L_0x24d23f0; 1 drivers -v0x244b850_0 .net "AandB", 0 0, L_0x24d3150; 1 drivers -v0x244b8f0_0 .net "AddSubSLTSum", 0 0, L_0x24d3060; 1 drivers -v0x244b990_0 .net "AxorB", 0 0, L_0x24d2f70; 1 drivers -v0x244ba10_0 .net "B", 0 0, L_0x24d2490; 1 drivers -v0x244bac0_0 .net "BornB", 0 0, L_0x24d2a20; 1 drivers -v0x244bb80_0 .net "CINandAxorB", 0 0, L_0x24d32c0; 1 drivers -v0x244bc00_0 .alias "Command", 2 0, v0x2463430_0; -v0x244bc80_0 .net *"_s3", 0 0, L_0x24d2cf0; 1 drivers -v0x244bd00_0 .net *"_s5", 0 0, L_0x24d2ed0; 1 drivers -v0x244bda0_0 .net "carryin", 0 0, L_0x24d25c0; 1 drivers -v0x244be40_0 .net "carryout", 0 0, L_0x24d33b0; 1 drivers -v0x244bee0_0 .net "nB", 0 0, L_0x24d26a0; 1 drivers -v0x244bf90_0 .net "nCmd2", 0 0, L_0x24d2c50; 1 drivers -v0x244c090_0 .net "subtract", 0 0, L_0x24d2d90; 1 drivers -L_0x24d2bb0 .part C4, 0, 1; -L_0x24d2cf0 .part C4, 2, 1; -L_0x24d2ed0 .part C4, 0, 1; -S_0x244b1f0 .scope module, "mux0" "TwoInMux" 2 105, 2 8, S_0x244b100; - .timescale -9 -12; -L_0x24d27a0/d .functor NOT 1, L_0x24d2bb0, C4<0>, C4<0>, C4<0>; -L_0x24d27a0 .delay (10000,10000,10000) L_0x24d27a0/d; -L_0x24d2840/d .functor AND 1, L_0x24d2490, L_0x24d27a0, C4<1>, C4<1>; -L_0x24d2840 .delay (20000,20000,20000) L_0x24d2840/d; -L_0x24d2930/d .functor AND 1, L_0x24d26a0, L_0x24d2bb0, C4<1>, C4<1>; -L_0x24d2930 .delay (20000,20000,20000) L_0x24d2930/d; -L_0x24d2a20/d .functor OR 1, L_0x24d2840, L_0x24d2930, C4<0>, C4<0>; -L_0x24d2a20 .delay (20000,20000,20000) L_0x24d2a20/d; -v0x244b2e0_0 .net "S", 0 0, L_0x24d2bb0; 1 drivers -v0x244b380_0 .alias "in0", 0 0, v0x244ba10_0; -v0x244b420_0 .alias "in1", 0 0, v0x244bee0_0; -v0x244b4c0_0 .net "nS", 0 0, L_0x24d27a0; 1 drivers -v0x244b570_0 .net "out0", 0 0, L_0x24d2840; 1 drivers -v0x244b610_0 .net "out1", 0 0, L_0x24d2930; 1 drivers -v0x244b6f0_0 .alias "outfinal", 0 0, v0x244bac0_0; -S_0x2449df0 .scope generate, "addbits[21]" "addbits[21]" 2 230, 2 230, S_0x2426ca0; - .timescale -9 -12; -P_0x2449808 .param/l "i" 2 230, +C4<010101>; -S_0x2449f60 .scope module, "attempt" "MiddleAddSubSLT" 2 232, 2 89, S_0x2449df0; - .timescale -9 -12; -L_0x24d3aa0/d .functor NOT 1, L_0x24d3860, C4<0>, C4<0>, C4<0>; -L_0x24d3aa0 .delay (10000,10000,10000) L_0x24d3aa0/d; -L_0x24d4030/d .functor NOT 1, L_0x24d40f0, C4<0>, C4<0>, C4<0>; -L_0x24d4030 .delay (10000,10000,10000) L_0x24d4030/d; -L_0x24d4190/d .functor AND 1, L_0x24d42d0, L_0x24d4030, C4<1>, C4<1>; -L_0x24d4190 .delay (20000,20000,20000) L_0x24d4190/d; -L_0x24d4370/d .functor XOR 1, L_0x24d37c0, L_0x24d3de0, C4<0>, C4<0>; -L_0x24d4370 .delay (40000,40000,40000) L_0x24d4370/d; -L_0x24d4460/d .functor XOR 1, L_0x24d4370, L_0x24d3990, C4<0>, C4<0>; -L_0x24d4460 .delay (40000,40000,40000) L_0x24d4460/d; -L_0x24d4550/d .functor AND 1, L_0x24d37c0, L_0x24d3de0, C4<1>, C4<1>; -L_0x24d4550 .delay (20000,20000,20000) L_0x24d4550/d; -L_0x24d46c0/d .functor AND 1, L_0x24d4370, L_0x24d3990, C4<1>, C4<1>; -L_0x24d46c0 .delay (20000,20000,20000) L_0x24d46c0/d; -L_0x24d47d0/d .functor OR 1, L_0x24d4550, L_0x24d46c0, C4<0>, C4<0>; -L_0x24d47d0 .delay (20000,20000,20000) L_0x24d47d0/d; -v0x244a5f0_0 .net "A", 0 0, L_0x24d37c0; 1 drivers -v0x244a6b0_0 .net "AandB", 0 0, L_0x24d4550; 1 drivers -v0x244a750_0 .net "AddSubSLTSum", 0 0, L_0x24d4460; 1 drivers -v0x244a7f0_0 .net "AxorB", 0 0, L_0x24d4370; 1 drivers -v0x244a870_0 .net "B", 0 0, L_0x24d3860; 1 drivers -v0x244a920_0 .net "BornB", 0 0, L_0x24d3de0; 1 drivers -v0x244a9e0_0 .net "CINandAxorB", 0 0, L_0x24d46c0; 1 drivers -v0x244aa60_0 .alias "Command", 2 0, v0x2463430_0; -v0x244aae0_0 .net *"_s3", 0 0, L_0x24d40f0; 1 drivers -v0x244ab60_0 .net *"_s5", 0 0, L_0x24d42d0; 1 drivers -v0x244ac00_0 .net "carryin", 0 0, L_0x24d3990; 1 drivers -v0x244aca0_0 .net "carryout", 0 0, L_0x24d47d0; 1 drivers -v0x244ad40_0 .net "nB", 0 0, L_0x24d3aa0; 1 drivers -v0x244adf0_0 .net "nCmd2", 0 0, L_0x24d4030; 1 drivers -v0x244aef0_0 .net "subtract", 0 0, L_0x24d4190; 1 drivers -L_0x24d3f90 .part C4, 0, 1; -L_0x24d40f0 .part C4, 2, 1; -L_0x24d42d0 .part C4, 0, 1; -S_0x244a050 .scope module, "mux0" "TwoInMux" 2 105, 2 8, S_0x2449f60; - .timescale -9 -12; -L_0x24d3ba0/d .functor NOT 1, L_0x24d3f90, C4<0>, C4<0>, C4<0>; -L_0x24d3ba0 .delay (10000,10000,10000) L_0x24d3ba0/d; -L_0x24d3c00/d .functor AND 1, L_0x24d3860, L_0x24d3ba0, C4<1>, C4<1>; -L_0x24d3c00 .delay (20000,20000,20000) L_0x24d3c00/d; -L_0x24d3cf0/d .functor AND 1, L_0x24d3aa0, L_0x24d3f90, C4<1>, C4<1>; -L_0x24d3cf0 .delay (20000,20000,20000) L_0x24d3cf0/d; -L_0x24d3de0/d .functor OR 1, L_0x24d3c00, L_0x24d3cf0, C4<0>, C4<0>; -L_0x24d3de0 .delay (20000,20000,20000) L_0x24d3de0/d; -v0x244a140_0 .net "S", 0 0, L_0x24d3f90; 1 drivers -v0x244a1e0_0 .alias "in0", 0 0, v0x244a870_0; -v0x244a280_0 .alias "in1", 0 0, v0x244ad40_0; -v0x244a320_0 .net "nS", 0 0, L_0x24d3ba0; 1 drivers -v0x244a3d0_0 .net "out0", 0 0, L_0x24d3c00; 1 drivers -v0x244a470_0 .net "out1", 0 0, L_0x24d3cf0; 1 drivers -v0x244a550_0 .alias "outfinal", 0 0, v0x244a920_0; -S_0x2448c50 .scope generate, "addbits[22]" "addbits[22]" 2 230, 2 230, S_0x2426ca0; - .timescale -9 -12; -P_0x2448668 .param/l "i" 2 230, +C4<010110>; -S_0x2448dc0 .scope module, "attempt" "MiddleAddSubSLT" 2 232, 2 89, S_0x2448c50; - .timescale -9 -12; -L_0x24d3a30/d .functor NOT 1, L_0x24d4ca0, C4<0>, C4<0>, C4<0>; -L_0x24d3a30 .delay (10000,10000,10000) L_0x24d3a30/d; -L_0x24d5560/d .functor NOT 1, L_0x24d5620, C4<0>, C4<0>, C4<0>; -L_0x24d5560 .delay (10000,10000,10000) L_0x24d5560/d; -L_0x24d56c0/d .functor AND 1, L_0x24d5800, L_0x24d5560, C4<1>, C4<1>; -L_0x24d56c0 .delay (20000,20000,20000) L_0x24d56c0/d; -L_0x24d58a0/d .functor XOR 1, L_0x24d4c00, L_0x24d52f0, C4<0>, C4<0>; -L_0x24d58a0 .delay (40000,40000,40000) L_0x24d58a0/d; -L_0x24d5990/d .functor XOR 1, L_0x24d58a0, L_0x24d4dd0, C4<0>, C4<0>; -L_0x24d5990 .delay (40000,40000,40000) L_0x24d5990/d; -L_0x24d5a80/d .functor AND 1, L_0x24d4c00, L_0x24d52f0, C4<1>, C4<1>; -L_0x24d5a80 .delay (20000,20000,20000) L_0x24d5a80/d; -L_0x24d5bf0/d .functor AND 1, L_0x24d58a0, L_0x24d4dd0, C4<1>, C4<1>; -L_0x24d5bf0 .delay (20000,20000,20000) L_0x24d5bf0/d; -L_0x24d5ce0/d .functor OR 1, L_0x24d5a80, L_0x24d5bf0, C4<0>, C4<0>; -L_0x24d5ce0 .delay (20000,20000,20000) L_0x24d5ce0/d; -v0x2449450_0 .net "A", 0 0, L_0x24d4c00; 1 drivers -v0x2449510_0 .net "AandB", 0 0, L_0x24d5a80; 1 drivers -v0x24495b0_0 .net "AddSubSLTSum", 0 0, L_0x24d5990; 1 drivers -v0x2449650_0 .net "AxorB", 0 0, L_0x24d58a0; 1 drivers -v0x24496d0_0 .net "B", 0 0, L_0x24d4ca0; 1 drivers -v0x2449780_0 .net "BornB", 0 0, L_0x24d52f0; 1 drivers -v0x2449840_0 .net "CINandAxorB", 0 0, L_0x24d5bf0; 1 drivers -v0x24498c0_0 .alias "Command", 2 0, v0x2463430_0; -v0x2449940_0 .net *"_s3", 0 0, L_0x24d5620; 1 drivers -v0x24499c0_0 .net *"_s5", 0 0, L_0x24d5800; 1 drivers -v0x2449a60_0 .net "carryin", 0 0, L_0x24d4dd0; 1 drivers -v0x2449b00_0 .net "carryout", 0 0, L_0x24d5ce0; 1 drivers -v0x2449ba0_0 .net "nB", 0 0, L_0x24d3a30; 1 drivers -v0x2449c50_0 .net "nCmd2", 0 0, L_0x24d5560; 1 drivers -v0x2449d50_0 .net "subtract", 0 0, L_0x24d56c0; 1 drivers -L_0x24d54c0 .part C4, 0, 1; -L_0x24d5620 .part C4, 2, 1; -L_0x24d5800 .part C4, 0, 1; -S_0x2448eb0 .scope module, "mux0" "TwoInMux" 2 105, 2 8, S_0x2448dc0; - .timescale -9 -12; -L_0x24d5010/d .functor NOT 1, L_0x24d54c0, C4<0>, C4<0>, C4<0>; -L_0x24d5010 .delay (10000,10000,10000) L_0x24d5010/d; -L_0x24d50d0/d .functor AND 1, L_0x24d4ca0, L_0x24d5010, C4<1>, C4<1>; -L_0x24d50d0 .delay (20000,20000,20000) L_0x24d50d0/d; -L_0x24d51e0/d .functor AND 1, L_0x24d3a30, L_0x24d54c0, C4<1>, C4<1>; -L_0x24d51e0 .delay (20000,20000,20000) L_0x24d51e0/d; -L_0x24d52f0/d .functor OR 1, L_0x24d50d0, L_0x24d51e0, C4<0>, C4<0>; -L_0x24d52f0 .delay (20000,20000,20000) L_0x24d52f0/d; -v0x2448fa0_0 .net "S", 0 0, L_0x24d54c0; 1 drivers -v0x2449040_0 .alias "in0", 0 0, v0x24496d0_0; -v0x24490e0_0 .alias "in1", 0 0, v0x2449ba0_0; -v0x2449180_0 .net "nS", 0 0, L_0x24d5010; 1 drivers -v0x2449230_0 .net "out0", 0 0, L_0x24d50d0; 1 drivers -v0x24492d0_0 .net "out1", 0 0, L_0x24d51e0; 1 drivers -v0x24493b0_0 .alias "outfinal", 0 0, v0x2449780_0; -S_0x2447ab0 .scope generate, "addbits[23]" "addbits[23]" 2 230, 2 230, S_0x2426ca0; - .timescale -9 -12; -P_0x24474c8 .param/l "i" 2 230, +C4<010111>; -S_0x2447c20 .scope module, "attempt" "MiddleAddSubSLT" 2 232, 2 89, S_0x2447ab0; - .timescale -9 -12; -L_0x24d4e70/d .functor NOT 1, L_0x24d61b0, C4<0>, C4<0>, C4<0>; -L_0x24d4e70 .delay (10000,10000,10000) L_0x24d4e70/d; -L_0x24d6960/d .functor NOT 1, L_0x24d6a00, C4<0>, C4<0>, C4<0>; -L_0x24d6960 .delay (10000,10000,10000) L_0x24d6960/d; -L_0x24d6aa0/d .functor AND 1, L_0x24d6be0, L_0x24d6960, C4<1>, C4<1>; -L_0x24d6aa0 .delay (20000,20000,20000) L_0x24d6aa0/d; -L_0x24d6c80/d .functor XOR 1, L_0x24d6110, L_0x24d6730, C4<0>, C4<0>; -L_0x24d6c80 .delay (40000,40000,40000) L_0x24d6c80/d; -L_0x24d6d70/d .functor XOR 1, L_0x24d6c80, L_0x24d62e0, C4<0>, C4<0>; -L_0x24d6d70 .delay (40000,40000,40000) L_0x24d6d70/d; -L_0x24d6e60/d .functor AND 1, L_0x24d6110, L_0x24d6730, C4<1>, C4<1>; -L_0x24d6e60 .delay (20000,20000,20000) L_0x24d6e60/d; -L_0x24d6fd0/d .functor AND 1, L_0x24d6c80, L_0x24d62e0, C4<1>, C4<1>; -L_0x24d6fd0 .delay (20000,20000,20000) L_0x24d6fd0/d; -L_0x24d70c0/d .functor OR 1, L_0x24d6e60, L_0x24d6fd0, C4<0>, C4<0>; -L_0x24d70c0 .delay (20000,20000,20000) L_0x24d70c0/d; -v0x24482b0_0 .net "A", 0 0, L_0x24d6110; 1 drivers -v0x2448370_0 .net "AandB", 0 0, L_0x24d6e60; 1 drivers -v0x2448410_0 .net "AddSubSLTSum", 0 0, L_0x24d6d70; 1 drivers -v0x24484b0_0 .net "AxorB", 0 0, L_0x24d6c80; 1 drivers -v0x2448530_0 .net "B", 0 0, L_0x24d61b0; 1 drivers -v0x24485e0_0 .net "BornB", 0 0, L_0x24d6730; 1 drivers -v0x24486a0_0 .net "CINandAxorB", 0 0, L_0x24d6fd0; 1 drivers -v0x2448720_0 .alias "Command", 2 0, v0x2463430_0; -v0x24487a0_0 .net *"_s3", 0 0, L_0x24d6a00; 1 drivers -v0x2448820_0 .net *"_s5", 0 0, L_0x24d6be0; 1 drivers -v0x24488c0_0 .net "carryin", 0 0, L_0x24d62e0; 1 drivers -v0x2448960_0 .net "carryout", 0 0, L_0x24d70c0; 1 drivers -v0x2448a00_0 .net "nB", 0 0, L_0x24d4e70; 1 drivers -v0x2448ab0_0 .net "nCmd2", 0 0, L_0x24d6960; 1 drivers -v0x2448bb0_0 .net "subtract", 0 0, L_0x24d6aa0; 1 drivers -L_0x24d68c0 .part C4, 0, 1; -L_0x24d6a00 .part C4, 2, 1; -L_0x24d6be0 .part C4, 0, 1; -S_0x2447d10 .scope module, "mux0" "TwoInMux" 2 105, 2 8, S_0x2447c20; - .timescale -9 -12; -L_0x24d64f0/d .functor NOT 1, L_0x24d68c0, C4<0>, C4<0>, C4<0>; -L_0x24d64f0 .delay (10000,10000,10000) L_0x24d64f0/d; -L_0x24d6550/d .functor AND 1, L_0x24d61b0, L_0x24d64f0, C4<1>, C4<1>; -L_0x24d6550 .delay (20000,20000,20000) L_0x24d6550/d; -L_0x24d6640/d .functor AND 1, L_0x24d4e70, L_0x24d68c0, C4<1>, C4<1>; -L_0x24d6640 .delay (20000,20000,20000) L_0x24d6640/d; -L_0x24d6730/d .functor OR 1, L_0x24d6550, L_0x24d6640, C4<0>, C4<0>; -L_0x24d6730 .delay (20000,20000,20000) L_0x24d6730/d; -v0x2447e00_0 .net "S", 0 0, L_0x24d68c0; 1 drivers -v0x2447ea0_0 .alias "in0", 0 0, v0x2448530_0; -v0x2447f40_0 .alias "in1", 0 0, v0x2448a00_0; -v0x2447fe0_0 .net "nS", 0 0, L_0x24d64f0; 1 drivers -v0x2448090_0 .net "out0", 0 0, L_0x24d6550; 1 drivers -v0x2448130_0 .net "out1", 0 0, L_0x24d6640; 1 drivers -v0x2448210_0 .alias "outfinal", 0 0, v0x24485e0_0; -S_0x2446910 .scope generate, "addbits[24]" "addbits[24]" 2 230, 2 230, S_0x2426ca0; - .timescale -9 -12; -P_0x2446328 .param/l "i" 2 230, +C4<011000>; -S_0x2446a80 .scope module, "attempt" "MiddleAddSubSLT" 2 232, 2 89, S_0x2446910; - .timescale -9 -12; -L_0x24d6380/d .functor NOT 1, L_0x24d7570, C4<0>, C4<0>, C4<0>; -L_0x24d6380 .delay (10000,10000,10000) L_0x24d6380/d; -L_0x24d7d40/d .functor NOT 1, L_0x24d7de0, C4<0>, C4<0>, C4<0>; -L_0x24d7d40 .delay (10000,10000,10000) L_0x24d7d40/d; -L_0x24d7e80/d .functor AND 1, L_0x24d7fc0, L_0x24d7d40, C4<1>, C4<1>; -L_0x24d7e80 .delay (20000,20000,20000) L_0x24d7e80/d; -L_0x24d8060/d .functor XOR 1, L_0x24d74d0, L_0x24d7b10, C4<0>, C4<0>; -L_0x24d8060 .delay (40000,40000,40000) L_0x24d8060/d; -L_0x24d8150/d .functor XOR 1, L_0x24d8060, L_0x24d76a0, C4<0>, C4<0>; -L_0x24d8150 .delay (40000,40000,40000) L_0x24d8150/d; -L_0x24d8240/d .functor AND 1, L_0x24d74d0, L_0x24d7b10, C4<1>, C4<1>; -L_0x24d8240 .delay (20000,20000,20000) L_0x24d8240/d; -L_0x24d83e0/d .functor AND 1, L_0x24d8060, L_0x24d76a0, C4<1>, C4<1>; -L_0x24d83e0 .delay (20000,20000,20000) L_0x24d83e0/d; -L_0x24d84f0/d .functor OR 1, L_0x24d8240, L_0x24d83e0, C4<0>, C4<0>; -L_0x24d84f0 .delay (20000,20000,20000) L_0x24d84f0/d; -v0x2447110_0 .net "A", 0 0, L_0x24d74d0; 1 drivers -v0x24471d0_0 .net "AandB", 0 0, L_0x24d8240; 1 drivers -v0x2447270_0 .net "AddSubSLTSum", 0 0, L_0x24d8150; 1 drivers -v0x2447310_0 .net "AxorB", 0 0, L_0x24d8060; 1 drivers -v0x2447390_0 .net "B", 0 0, L_0x24d7570; 1 drivers -v0x2447440_0 .net "BornB", 0 0, L_0x24d7b10; 1 drivers -v0x2447500_0 .net "CINandAxorB", 0 0, L_0x24d83e0; 1 drivers -v0x2447580_0 .alias "Command", 2 0, v0x2463430_0; -v0x2447600_0 .net *"_s3", 0 0, L_0x24d7de0; 1 drivers -v0x2447680_0 .net *"_s5", 0 0, L_0x24d7fc0; 1 drivers -v0x2447720_0 .net "carryin", 0 0, L_0x24d76a0; 1 drivers -v0x24477c0_0 .net "carryout", 0 0, L_0x24d84f0; 1 drivers -v0x2447860_0 .net "nB", 0 0, L_0x24d6380; 1 drivers -v0x2447910_0 .net "nCmd2", 0 0, L_0x24d7d40; 1 drivers -v0x2447a10_0 .net "subtract", 0 0, L_0x24d7e80; 1 drivers -L_0x24d7ca0 .part C4, 0, 1; -L_0x24d7de0 .part C4, 2, 1; -L_0x24d7fc0 .part C4, 0, 1; -S_0x2446b70 .scope module, "mux0" "TwoInMux" 2 105, 2 8, S_0x2446a80; - .timescale -9 -12; -L_0x24d7890/d .functor NOT 1, L_0x24d7ca0, C4<0>, C4<0>, C4<0>; -L_0x24d7890 .delay (10000,10000,10000) L_0x24d7890/d; -L_0x24d7930/d .functor AND 1, L_0x24d7570, L_0x24d7890, C4<1>, C4<1>; -L_0x24d7930 .delay (20000,20000,20000) L_0x24d7930/d; -L_0x24d7a20/d .functor AND 1, L_0x24d6380, L_0x24d7ca0, C4<1>, C4<1>; -L_0x24d7a20 .delay (20000,20000,20000) L_0x24d7a20/d; -L_0x24d7b10/d .functor OR 1, L_0x24d7930, L_0x24d7a20, C4<0>, C4<0>; -L_0x24d7b10 .delay (20000,20000,20000) L_0x24d7b10/d; -v0x2446c60_0 .net "S", 0 0, L_0x24d7ca0; 1 drivers -v0x2446d00_0 .alias "in0", 0 0, v0x2447390_0; -v0x2446da0_0 .alias "in1", 0 0, v0x2447860_0; -v0x2446e40_0 .net "nS", 0 0, L_0x24d7890; 1 drivers -v0x2446ef0_0 .net "out0", 0 0, L_0x24d7930; 1 drivers -v0x2446f90_0 .net "out1", 0 0, L_0x24d7a20; 1 drivers -v0x2447070_0 .alias "outfinal", 0 0, v0x2447440_0; -S_0x2445770 .scope generate, "addbits[25]" "addbits[25]" 2 230, 2 230, S_0x2426ca0; - .timescale -9 -12; -P_0x2445188 .param/l "i" 2 230, +C4<011001>; -S_0x24458e0 .scope module, "attempt" "MiddleAddSubSLT" 2 232, 2 89, S_0x2445770; - .timescale -9 -12; -L_0x24d7740/d .functor NOT 1, L_0x24d89c0, C4<0>, C4<0>, C4<0>; -L_0x24d7740 .delay (10000,10000,10000) L_0x24d7740/d; -L_0x24d91e0/d .functor NOT 1, L_0x24d92a0, C4<0>, C4<0>, C4<0>; -L_0x24d91e0 .delay (10000,10000,10000) L_0x24d91e0/d; -L_0x24d9340/d .functor AND 1, L_0x24d9480, L_0x24d91e0, C4<1>, C4<1>; -L_0x24d9340 .delay (20000,20000,20000) L_0x24d9340/d; -L_0x24d9520/d .functor XOR 1, L_0x24d8920, L_0x24d8f90, C4<0>, C4<0>; -L_0x24d9520 .delay (40000,40000,40000) L_0x24d9520/d; -L_0x24d9610/d .functor XOR 1, L_0x24d9520, L_0x24d8af0, C4<0>, C4<0>; -L_0x24d9610 .delay (40000,40000,40000) L_0x24d9610/d; -L_0x24d9730/d .functor AND 1, L_0x24d8920, L_0x24d8f90, C4<1>, C4<1>; -L_0x24d9730 .delay (20000,20000,20000) L_0x24d9730/d; -L_0x24d98d0/d .functor AND 1, L_0x24d9520, L_0x24d8af0, C4<1>, C4<1>; -L_0x24d98d0 .delay (20000,20000,20000) L_0x24d98d0/d; -L_0x24d99e0/d .functor OR 1, L_0x24d9730, L_0x24d98d0, C4<0>, C4<0>; -L_0x24d99e0 .delay (20000,20000,20000) L_0x24d99e0/d; -v0x2445f70_0 .net "A", 0 0, L_0x24d8920; 1 drivers -v0x2446030_0 .net "AandB", 0 0, L_0x24d9730; 1 drivers -v0x24460d0_0 .net "AddSubSLTSum", 0 0, L_0x24d9610; 1 drivers -v0x2446170_0 .net "AxorB", 0 0, L_0x24d9520; 1 drivers -v0x24461f0_0 .net "B", 0 0, L_0x24d89c0; 1 drivers -v0x24462a0_0 .net "BornB", 0 0, L_0x24d8f90; 1 drivers -v0x2446360_0 .net "CINandAxorB", 0 0, L_0x24d98d0; 1 drivers -v0x24463e0_0 .alias "Command", 2 0, v0x2463430_0; -v0x2446460_0 .net *"_s3", 0 0, L_0x24d92a0; 1 drivers -v0x24464e0_0 .net *"_s5", 0 0, L_0x24d9480; 1 drivers -v0x2446580_0 .net "carryin", 0 0, L_0x24d8af0; 1 drivers -v0x2446620_0 .net "carryout", 0 0, L_0x24d99e0; 1 drivers -v0x24466c0_0 .net "nB", 0 0, L_0x24d7740; 1 drivers -v0x2446770_0 .net "nCmd2", 0 0, L_0x24d91e0; 1 drivers -v0x2446870_0 .net "subtract", 0 0, L_0x24d9340; 1 drivers -L_0x24d9140 .part C4, 0, 1; -L_0x24d92a0 .part C4, 2, 1; -L_0x24d9480 .part C4, 0, 1; -S_0x24459d0 .scope module, "mux0" "TwoInMux" 2 105, 2 8, S_0x24458e0; - .timescale -9 -12; -L_0x24d8d10/d .functor NOT 1, L_0x24d9140, C4<0>, C4<0>, C4<0>; -L_0x24d8d10 .delay (10000,10000,10000) L_0x24d8d10/d; -L_0x24d8db0/d .functor AND 1, L_0x24d89c0, L_0x24d8d10, C4<1>, C4<1>; -L_0x24d8db0 .delay (20000,20000,20000) L_0x24d8db0/d; -L_0x24d8ea0/d .functor AND 1, L_0x24d7740, L_0x24d9140, C4<1>, C4<1>; -L_0x24d8ea0 .delay (20000,20000,20000) L_0x24d8ea0/d; -L_0x24d8f90/d .functor OR 1, L_0x24d8db0, L_0x24d8ea0, C4<0>, C4<0>; -L_0x24d8f90 .delay (20000,20000,20000) L_0x24d8f90/d; -v0x2445ac0_0 .net "S", 0 0, L_0x24d9140; 1 drivers -v0x2445b60_0 .alias "in0", 0 0, v0x24461f0_0; -v0x2445c00_0 .alias "in1", 0 0, v0x24466c0_0; -v0x2445ca0_0 .net "nS", 0 0, L_0x24d8d10; 1 drivers -v0x2445d50_0 .net "out0", 0 0, L_0x24d8db0; 1 drivers -v0x2445df0_0 .net "out1", 0 0, L_0x24d8ea0; 1 drivers -v0x2445ed0_0 .alias "outfinal", 0 0, v0x24462a0_0; -S_0x24445d0 .scope generate, "addbits[26]" "addbits[26]" 2 230, 2 230, S_0x2426ca0; - .timescale -9 -12; -P_0x2443fe8 .param/l "i" 2 230, +C4<011010>; -S_0x2444740 .scope module, "attempt" "MiddleAddSubSLT" 2 232, 2 89, S_0x24445d0; - .timescale -9 -12; -L_0x24d8b90/d .functor NOT 1, L_0x24d9eb0, C4<0>, C4<0>, C4<0>; -L_0x24d8b90 .delay (10000,10000,10000) L_0x24d8b90/d; -L_0x24da6c0/d .functor NOT 1, L_0x24da780, C4<0>, C4<0>, C4<0>; -L_0x24da6c0 .delay (10000,10000,10000) L_0x24da6c0/d; -L_0x24da820/d .functor AND 1, L_0x24da960, L_0x24da6c0, C4<1>, C4<1>; -L_0x24da820 .delay (20000,20000,20000) L_0x24da820/d; -L_0x24daa00/d .functor XOR 1, L_0x24d9e10, L_0x24da450, C4<0>, C4<0>; -L_0x24daa00 .delay (40000,40000,40000) L_0x24daa00/d; -L_0x24daaf0/d .functor XOR 1, L_0x24daa00, L_0x24d9fe0, C4<0>, C4<0>; -L_0x24daaf0 .delay (40000,40000,40000) L_0x24daaf0/d; -L_0x24dac10/d .functor AND 1, L_0x24d9e10, L_0x24da450, C4<1>, C4<1>; -L_0x24dac10 .delay (20000,20000,20000) L_0x24dac10/d; -L_0x24dadb0/d .functor AND 1, L_0x24daa00, L_0x24d9fe0, C4<1>, C4<1>; -L_0x24dadb0 .delay (20000,20000,20000) L_0x24dadb0/d; -L_0x24daec0/d .functor OR 1, L_0x24dac10, L_0x24dadb0, C4<0>, C4<0>; -L_0x24daec0 .delay (20000,20000,20000) L_0x24daec0/d; -v0x2444dd0_0 .net "A", 0 0, L_0x24d9e10; 1 drivers -v0x2444e90_0 .net "AandB", 0 0, L_0x24dac10; 1 drivers -v0x2444f30_0 .net "AddSubSLTSum", 0 0, L_0x24daaf0; 1 drivers -v0x2444fd0_0 .net "AxorB", 0 0, L_0x24daa00; 1 drivers -v0x2445050_0 .net "B", 0 0, L_0x24d9eb0; 1 drivers -v0x2445100_0 .net "BornB", 0 0, L_0x24da450; 1 drivers -v0x24451c0_0 .net "CINandAxorB", 0 0, L_0x24dadb0; 1 drivers -v0x2445240_0 .alias "Command", 2 0, v0x2463430_0; -v0x24452c0_0 .net *"_s3", 0 0, L_0x24da780; 1 drivers -v0x2445340_0 .net *"_s5", 0 0, L_0x24da960; 1 drivers -v0x24453e0_0 .net "carryin", 0 0, L_0x24d9fe0; 1 drivers -v0x2445480_0 .net "carryout", 0 0, L_0x24daec0; 1 drivers -v0x2445520_0 .net "nB", 0 0, L_0x24d8b90; 1 drivers -v0x24455d0_0 .net "nCmd2", 0 0, L_0x24da6c0; 1 drivers -v0x24456d0_0 .net "subtract", 0 0, L_0x24da820; 1 drivers -L_0x24da620 .part C4, 0, 1; -L_0x24da780 .part C4, 2, 1; -L_0x24da960 .part C4, 0, 1; -S_0x2444830 .scope module, "mux0" "TwoInMux" 2 105, 2 8, S_0x2444740; - .timescale -9 -12; -L_0x24d8c60/d .functor NOT 1, L_0x24da620, C4<0>, C4<0>, C4<0>; -L_0x24d8c60 .delay (10000,10000,10000) L_0x24d8c60/d; -L_0x24da270/d .functor AND 1, L_0x24d9eb0, L_0x24d8c60, C4<1>, C4<1>; -L_0x24da270 .delay (20000,20000,20000) L_0x24da270/d; -L_0x24da360/d .functor AND 1, L_0x24d8b90, L_0x24da620, C4<1>, C4<1>; -L_0x24da360 .delay (20000,20000,20000) L_0x24da360/d; -L_0x24da450/d .functor OR 1, L_0x24da270, L_0x24da360, C4<0>, C4<0>; -L_0x24da450 .delay (20000,20000,20000) L_0x24da450/d; -v0x2444920_0 .net "S", 0 0, L_0x24da620; 1 drivers -v0x24449c0_0 .alias "in0", 0 0, v0x2445050_0; -v0x2444a60_0 .alias "in1", 0 0, v0x2445520_0; -v0x2444b00_0 .net "nS", 0 0, L_0x24d8c60; 1 drivers -v0x2444bb0_0 .net "out0", 0 0, L_0x24da270; 1 drivers -v0x2444c50_0 .net "out1", 0 0, L_0x24da360; 1 drivers -v0x2444d30_0 .alias "outfinal", 0 0, v0x2445100_0; -S_0x2443430 .scope generate, "addbits[27]" "addbits[27]" 2 230, 2 230, S_0x2426ca0; - .timescale -9 -12; -P_0x2442e48 .param/l "i" 2 230, +C4<011011>; -S_0x24435a0 .scope module, "attempt" "MiddleAddSubSLT" 2 232, 2 89, S_0x2443430; - .timescale -9 -12; -L_0x24da080/d .functor NOT 1, L_0x24db390, C4<0>, C4<0>, C4<0>; -L_0x24da080 .delay (10000,10000,10000) L_0x24da080/d; -L_0x24dbba0/d .functor NOT 1, L_0x24dbc60, C4<0>, C4<0>, C4<0>; -L_0x24dbba0 .delay (10000,10000,10000) L_0x24dbba0/d; -L_0x24dbd00/d .functor AND 1, L_0x24dbe40, L_0x24dbba0, C4<1>, C4<1>; -L_0x24dbd00 .delay (20000,20000,20000) L_0x24dbd00/d; -L_0x24dbee0/d .functor XOR 1, L_0x24db2f0, L_0x24db930, C4<0>, C4<0>; -L_0x24dbee0 .delay (40000,40000,40000) L_0x24dbee0/d; -L_0x24dbfd0/d .functor XOR 1, L_0x24dbee0, L_0x24db4c0, C4<0>, C4<0>; -L_0x24dbfd0 .delay (40000,40000,40000) L_0x24dbfd0/d; -L_0x24dc0f0/d .functor AND 1, L_0x24db2f0, L_0x24db930, C4<1>, C4<1>; -L_0x24dc0f0 .delay (20000,20000,20000) L_0x24dc0f0/d; -L_0x24dc290/d .functor AND 1, L_0x24dbee0, L_0x24db4c0, C4<1>, C4<1>; -L_0x24dc290 .delay (20000,20000,20000) L_0x24dc290/d; -L_0x24dc3a0/d .functor OR 1, L_0x24dc0f0, L_0x24dc290, C4<0>, C4<0>; -L_0x24dc3a0 .delay (20000,20000,20000) L_0x24dc3a0/d; -v0x2443c30_0 .net "A", 0 0, L_0x24db2f0; 1 drivers -v0x2443cf0_0 .net "AandB", 0 0, L_0x24dc0f0; 1 drivers -v0x2443d90_0 .net "AddSubSLTSum", 0 0, L_0x24dbfd0; 1 drivers -v0x2443e30_0 .net "AxorB", 0 0, L_0x24dbee0; 1 drivers -v0x2443eb0_0 .net "B", 0 0, L_0x24db390; 1 drivers -v0x2443f60_0 .net "BornB", 0 0, L_0x24db930; 1 drivers -v0x2444020_0 .net "CINandAxorB", 0 0, L_0x24dc290; 1 drivers -v0x24440a0_0 .alias "Command", 2 0, v0x2463430_0; -v0x2444120_0 .net *"_s3", 0 0, L_0x24dbc60; 1 drivers -v0x24441a0_0 .net *"_s5", 0 0, L_0x24dbe40; 1 drivers -v0x2444240_0 .net "carryin", 0 0, L_0x24db4c0; 1 drivers -v0x24442e0_0 .net "carryout", 0 0, L_0x24dc3a0; 1 drivers -v0x2444380_0 .net "nB", 0 0, L_0x24da080; 1 drivers -v0x2444430_0 .net "nCmd2", 0 0, L_0x24dbba0; 1 drivers -v0x2444530_0 .net "subtract", 0 0, L_0x24dbd00; 1 drivers -L_0x24dbb00 .part C4, 0, 1; -L_0x24dbc60 .part C4, 2, 1; -L_0x24dbe40 .part C4, 0, 1; -S_0x2443690 .scope module, "mux0" "TwoInMux" 2 105, 2 8, S_0x24435a0; - .timescale -9 -12; -L_0x24db6f0/d .functor NOT 1, L_0x24dbb00, C4<0>, C4<0>, C4<0>; -L_0x24db6f0 .delay (10000,10000,10000) L_0x24db6f0/d; -L_0x24db750/d .functor AND 1, L_0x24db390, L_0x24db6f0, C4<1>, C4<1>; -L_0x24db750 .delay (20000,20000,20000) L_0x24db750/d; -L_0x24db840/d .functor AND 1, L_0x24da080, L_0x24dbb00, C4<1>, C4<1>; -L_0x24db840 .delay (20000,20000,20000) L_0x24db840/d; -L_0x24db930/d .functor OR 1, L_0x24db750, L_0x24db840, C4<0>, C4<0>; -L_0x24db930 .delay (20000,20000,20000) L_0x24db930/d; -v0x2443780_0 .net "S", 0 0, L_0x24dbb00; 1 drivers -v0x2443820_0 .alias "in0", 0 0, v0x2443eb0_0; -v0x24438c0_0 .alias "in1", 0 0, v0x2444380_0; -v0x2443960_0 .net "nS", 0 0, L_0x24db6f0; 1 drivers -v0x2443a10_0 .net "out0", 0 0, L_0x24db750; 1 drivers -v0x2443ab0_0 .net "out1", 0 0, L_0x24db840; 1 drivers -v0x2443b90_0 .alias "outfinal", 0 0, v0x2443f60_0; -S_0x2442290 .scope generate, "addbits[28]" "addbits[28]" 2 230, 2 230, S_0x2426ca0; - .timescale -9 -12; -P_0x2441ca8 .param/l "i" 2 230, +C4<011100>; -S_0x2442400 .scope module, "attempt" "MiddleAddSubSLT" 2 232, 2 89, S_0x2442290; - .timescale -9 -12; -L_0x24db560/d .functor NOT 1, L_0x24dc870, C4<0>, C4<0>, C4<0>; -L_0x24db560 .delay (10000,10000,10000) L_0x24db560/d; -L_0x24dd0b0/d .functor NOT 1, L_0x24dd150, C4<0>, C4<0>, C4<0>; -L_0x24dd0b0 .delay (10000,10000,10000) L_0x24dd0b0/d; -L_0x24dd1f0/d .functor AND 1, L_0x24dd330, L_0x24dd0b0, C4<1>, C4<1>; -L_0x24dd1f0 .delay (20000,20000,20000) L_0x24dd1f0/d; -L_0x24dd3d0/d .functor XOR 1, L_0x24dc7d0, L_0x24dce80, C4<0>, C4<0>; -L_0x24dd3d0 .delay (40000,40000,40000) L_0x24dd3d0/d; -L_0x24dd4f0/d .functor XOR 1, L_0x24dd3d0, L_0x24dc9a0, C4<0>, C4<0>; -L_0x24dd4f0 .delay (40000,40000,40000) L_0x24dd4f0/d; -L_0x24dd610/d .functor AND 1, L_0x24dc7d0, L_0x24dce80, C4<1>, C4<1>; -L_0x24dd610 .delay (20000,20000,20000) L_0x24dd610/d; -L_0x24dd7b0/d .functor AND 1, L_0x24dd3d0, L_0x24dc9a0, C4<1>, C4<1>; -L_0x24dd7b0 .delay (20000,20000,20000) L_0x24dd7b0/d; -L_0x24dd8a0/d .functor OR 1, L_0x24dd610, L_0x24dd7b0, C4<0>, C4<0>; -L_0x24dd8a0 .delay (20000,20000,20000) L_0x24dd8a0/d; -v0x2442a90_0 .net "A", 0 0, L_0x24dc7d0; 1 drivers -v0x2442b50_0 .net "AandB", 0 0, L_0x24dd610; 1 drivers -v0x2442bf0_0 .net "AddSubSLTSum", 0 0, L_0x24dd4f0; 1 drivers -v0x2442c90_0 .net "AxorB", 0 0, L_0x24dd3d0; 1 drivers -v0x2442d10_0 .net "B", 0 0, L_0x24dc870; 1 drivers -v0x2442dc0_0 .net "BornB", 0 0, L_0x24dce80; 1 drivers -v0x2442e80_0 .net "CINandAxorB", 0 0, L_0x24dd7b0; 1 drivers -v0x2442f00_0 .alias "Command", 2 0, v0x2463430_0; -v0x2442f80_0 .net *"_s3", 0 0, L_0x24dd150; 1 drivers -v0x2443000_0 .net *"_s5", 0 0, L_0x24dd330; 1 drivers -v0x24430a0_0 .net "carryin", 0 0, L_0x24dc9a0; 1 drivers -v0x2443140_0 .net "carryout", 0 0, L_0x24dd8a0; 1 drivers -v0x24431e0_0 .net "nB", 0 0, L_0x24db560; 1 drivers -v0x2443290_0 .net "nCmd2", 0 0, L_0x24dd0b0; 1 drivers -v0x2443390_0 .net "subtract", 0 0, L_0x24dd1f0; 1 drivers -L_0x24dd010 .part C4, 0, 1; -L_0x24dd150 .part C4, 2, 1; -L_0x24dd330 .part C4, 0, 1; -S_0x24424f0 .scope module, "mux0" "TwoInMux" 2 105, 2 8, S_0x2442400; - .timescale -9 -12; -L_0x24dcc00/d .functor NOT 1, L_0x24dd010, C4<0>, C4<0>, C4<0>; -L_0x24dcc00 .delay (10000,10000,10000) L_0x24dcc00/d; -L_0x24dcca0/d .functor AND 1, L_0x24dc870, L_0x24dcc00, C4<1>, C4<1>; -L_0x24dcca0 .delay (20000,20000,20000) L_0x24dcca0/d; -L_0x24dcd90/d .functor AND 1, L_0x24db560, L_0x24dd010, C4<1>, C4<1>; -L_0x24dcd90 .delay (20000,20000,20000) L_0x24dcd90/d; -L_0x24dce80/d .functor OR 1, L_0x24dcca0, L_0x24dcd90, C4<0>, C4<0>; -L_0x24dce80 .delay (20000,20000,20000) L_0x24dce80/d; -v0x24425e0_0 .net "S", 0 0, L_0x24dd010; 1 drivers -v0x2442680_0 .alias "in0", 0 0, v0x2442d10_0; -v0x2442720_0 .alias "in1", 0 0, v0x24431e0_0; -v0x24427c0_0 .net "nS", 0 0, L_0x24dcc00; 1 drivers -v0x2442870_0 .net "out0", 0 0, L_0x24dcca0; 1 drivers -v0x2442910_0 .net "out1", 0 0, L_0x24dcd90; 1 drivers -v0x24429f0_0 .alias "outfinal", 0 0, v0x2442dc0_0; -S_0x24410f0 .scope generate, "addbits[29]" "addbits[29]" 2 230, 2 230, S_0x2426ca0; - .timescale -9 -12; -P_0x2440b08 .param/l "i" 2 230, +C4<011101>; -S_0x2441260 .scope module, "attempt" "MiddleAddSubSLT" 2 232, 2 89, S_0x24410f0; - .timescale -9 -12; -L_0x24dca40/d .functor NOT 1, L_0x24ca3d0, C4<0>, C4<0>, C4<0>; -L_0x24dca40 .delay (10000,10000,10000) L_0x24dca40/d; -L_0x24de580/d .functor NOT 1, L_0x24de640, C4<0>, C4<0>, C4<0>; -L_0x24de580 .delay (10000,10000,10000) L_0x24de580/d; -L_0x24de6e0/d .functor AND 1, L_0x24de820, L_0x24de580, C4<1>, C4<1>; -L_0x24de6e0 .delay (20000,20000,20000) L_0x24de6e0/d; -L_0x24de8c0/d .functor XOR 1, L_0x24ddcd0, L_0x24de350, C4<0>, C4<0>; -L_0x24de8c0 .delay (40000,40000,40000) L_0x24de8c0/d; -L_0x24de9e0/d .functor XOR 1, L_0x24de8c0, L_0x24ca500, C4<0>, C4<0>; -L_0x24de9e0 .delay (40000,40000,40000) L_0x24de9e0/d; -L_0x24deb00/d .functor AND 1, L_0x24ddcd0, L_0x24de350, C4<1>, C4<1>; -L_0x24deb00 .delay (20000,20000,20000) L_0x24deb00/d; -L_0x24deca0/d .functor AND 1, L_0x24de8c0, L_0x24ca500, C4<1>, C4<1>; -L_0x24deca0 .delay (20000,20000,20000) L_0x24deca0/d; -L_0x24ded90/d .functor OR 1, L_0x24deb00, L_0x24deca0, C4<0>, C4<0>; -L_0x24ded90 .delay (20000,20000,20000) L_0x24ded90/d; -v0x24418f0_0 .net "A", 0 0, L_0x24ddcd0; 1 drivers -v0x24419b0_0 .net "AandB", 0 0, L_0x24deb00; 1 drivers -v0x2441a50_0 .net "AddSubSLTSum", 0 0, L_0x24de9e0; 1 drivers -v0x2441af0_0 .net "AxorB", 0 0, L_0x24de8c0; 1 drivers -v0x2441b70_0 .net "B", 0 0, L_0x24ca3d0; 1 drivers -v0x2441c20_0 .net "BornB", 0 0, L_0x24de350; 1 drivers -v0x2441ce0_0 .net "CINandAxorB", 0 0, L_0x24deca0; 1 drivers -v0x2441d60_0 .alias "Command", 2 0, v0x2463430_0; -v0x2441de0_0 .net *"_s3", 0 0, L_0x24de640; 1 drivers -v0x2441e60_0 .net *"_s5", 0 0, L_0x24de820; 1 drivers -v0x2441f00_0 .net "carryin", 0 0, L_0x24ca500; 1 drivers -v0x2441fa0_0 .net "carryout", 0 0, L_0x24ded90; 1 drivers -v0x2442040_0 .net "nB", 0 0, L_0x24dca40; 1 drivers -v0x24420f0_0 .net "nCmd2", 0 0, L_0x24de580; 1 drivers -v0x24421f0_0 .net "subtract", 0 0, L_0x24de6e0; 1 drivers -L_0x24de4e0 .part C4, 0, 1; -L_0x24de640 .part C4, 2, 1; -L_0x24de820 .part C4, 0, 1; -S_0x2441350 .scope module, "mux0" "TwoInMux" 2 105, 2 8, S_0x2441260; - .timescale -9 -12; -L_0x24dcba0/d .functor NOT 1, L_0x24de4e0, C4<0>, C4<0>, C4<0>; -L_0x24dcba0 .delay (10000,10000,10000) L_0x24dcba0/d; -L_0x24de170/d .functor AND 1, L_0x24ca3d0, L_0x24dcba0, C4<1>, C4<1>; -L_0x24de170 .delay (20000,20000,20000) L_0x24de170/d; -L_0x24de260/d .functor AND 1, L_0x24dca40, L_0x24de4e0, C4<1>, C4<1>; -L_0x24de260 .delay (20000,20000,20000) L_0x24de260/d; -L_0x24de350/d .functor OR 1, L_0x24de170, L_0x24de260, C4<0>, C4<0>; -L_0x24de350 .delay (20000,20000,20000) L_0x24de350/d; -v0x2441440_0 .net "S", 0 0, L_0x24de4e0; 1 drivers -v0x24414e0_0 .alias "in0", 0 0, v0x2441b70_0; -v0x2441580_0 .alias "in1", 0 0, v0x2442040_0; -v0x2441620_0 .net "nS", 0 0, L_0x24dcba0; 1 drivers -v0x24416d0_0 .net "out0", 0 0, L_0x24de170; 1 drivers -v0x2441770_0 .net "out1", 0 0, L_0x24de260; 1 drivers -v0x2441850_0 .alias "outfinal", 0 0, v0x2441c20_0; -S_0x243ff50 .scope generate, "addbits[30]" "addbits[30]" 2 230, 2 230, S_0x2426ca0; - .timescale -9 -12; -P_0x243f848 .param/l "i" 2 230, +C4<011110>; -S_0x24400c0 .scope module, "attempt" "MiddleAddSubSLT" 2 232, 2 89, S_0x243ff50; - .timescale -9 -12; -L_0x24df4e0/d .functor NOT 1, L_0x24dfbd0, C4<0>, C4<0>, C4<0>; -L_0x24df4e0 .delay (10000,10000,10000) L_0x24df4e0/d; -L_0x24de070/d .functor NOT 1, L_0x24dffc0, C4<0>, C4<0>, C4<0>; -L_0x24de070 .delay (10000,10000,10000) L_0x24de070/d; -L_0x24e0060/d .functor AND 1, L_0x24e01a0, L_0x24de070, C4<1>, C4<1>; -L_0x24e0060 .delay (20000,20000,20000) L_0x24e0060/d; -L_0x24e0240/d .functor XOR 1, L_0x24dfb30, L_0x24dde00, C4<0>, C4<0>; -L_0x24e0240 .delay (40000,40000,40000) L_0x24e0240/d; -L_0x24e0330/d .functor XOR 1, L_0x24e0240, L_0x24dfd00, C4<0>, C4<0>; -L_0x24e0330 .delay (40000,40000,40000) L_0x24e0330/d; -L_0x24e0420/d .functor AND 1, L_0x24dfb30, L_0x24dde00, C4<1>, C4<1>; -L_0x24e0420 .delay (20000,20000,20000) L_0x24e0420/d; -L_0x24e0590/d .functor AND 1, L_0x24e0240, L_0x24dfd00, C4<1>, C4<1>; -L_0x24e0590 .delay (20000,20000,20000) L_0x24e0590/d; -L_0x24e0680/d .functor OR 1, L_0x24e0420, L_0x24e0590, C4<0>, C4<0>; -L_0x24e0680 .delay (20000,20000,20000) L_0x24e0680/d; -v0x2440750_0 .net "A", 0 0, L_0x24dfb30; 1 drivers -v0x2440810_0 .net "AandB", 0 0, L_0x24e0420; 1 drivers -v0x24408b0_0 .net "AddSubSLTSum", 0 0, L_0x24e0330; 1 drivers -v0x2440950_0 .net "AxorB", 0 0, L_0x24e0240; 1 drivers -v0x24409d0_0 .net "B", 0 0, L_0x24dfbd0; 1 drivers -v0x2440a80_0 .net "BornB", 0 0, L_0x24dde00; 1 drivers -v0x2440b40_0 .net "CINandAxorB", 0 0, L_0x24e0590; 1 drivers -v0x2440bc0_0 .alias "Command", 2 0, v0x2463430_0; -v0x2440c40_0 .net *"_s3", 0 0, L_0x24dffc0; 1 drivers -v0x2440cc0_0 .net *"_s5", 0 0, L_0x24e01a0; 1 drivers -v0x2440d60_0 .net "carryin", 0 0, L_0x24dfd00; 1 drivers -v0x2440e00_0 .net "carryout", 0 0, L_0x24e0680; 1 drivers -v0x2440ea0_0 .net "nB", 0 0, L_0x24df4e0; 1 drivers -v0x2440f50_0 .net "nCmd2", 0 0, L_0x24de070; 1 drivers -v0x2441050_0 .net "subtract", 0 0, L_0x24e0060; 1 drivers -L_0x24ddfd0 .part C4, 0, 1; -L_0x24dffc0 .part C4, 2, 1; -L_0x24e01a0 .part C4, 0, 1; -S_0x24401b0 .scope module, "mux0" "TwoInMux" 2 105, 2 8, S_0x24400c0; - .timescale -9 -12; -L_0x24ca170/d .functor NOT 1, L_0x24ddfd0, C4<0>, C4<0>, C4<0>; -L_0x24ca170 .delay (10000,10000,10000) L_0x24ca170/d; -L_0x24ca1f0/d .functor AND 1, L_0x24dfbd0, L_0x24ca170, C4<1>, C4<1>; -L_0x24ca1f0 .delay (20000,20000,20000) L_0x24ca1f0/d; -L_0x24ca300/d .functor AND 1, L_0x24df4e0, L_0x24ddfd0, C4<1>, C4<1>; -L_0x24ca300 .delay (20000,20000,20000) L_0x24ca300/d; -L_0x24dde00/d .functor OR 1, L_0x24ca1f0, L_0x24ca300, C4<0>, C4<0>; -L_0x24dde00 .delay (20000,20000,20000) L_0x24dde00/d; -v0x24402a0_0 .net "S", 0 0, L_0x24ddfd0; 1 drivers -v0x2440340_0 .alias "in0", 0 0, v0x24409d0_0; -v0x24403e0_0 .alias "in1", 0 0, v0x2440ea0_0; -v0x2440480_0 .net "nS", 0 0, L_0x24ca170; 1 drivers -v0x2440530_0 .net "out0", 0 0, L_0x24ca1f0; 1 drivers -v0x24405d0_0 .net "out1", 0 0, L_0x24ca300; 1 drivers -v0x24406b0_0 .alias "outfinal", 0 0, v0x2440a80_0; -S_0x243ecf0 .scope generate, "addbits[31]" "addbits[31]" 2 230, 2 230, S_0x2426ca0; - .timescale -9 -12; -P_0x2426e18 .param/l "i" 2 230, +C4<011111>; -S_0x243ee20 .scope module, "attempt" "MiddleAddSubSLT" 2 232, 2 89, S_0x243ecf0; - .timescale -9 -12; -L_0x24dfda0/d .functor NOT 1, L_0x24cbd00, C4<0>, C4<0>, C4<0>; -L_0x24dfda0 .delay (10000,10000,10000) L_0x24dfda0/d; -L_0x24e1360/d .functor NOT 1, L_0x24e1400, C4<0>, C4<0>, C4<0>; -L_0x24e1360 .delay (10000,10000,10000) L_0x24e1360/d; -L_0x24e14a0/d .functor AND 1, L_0x24e15e0, L_0x24e1360, C4<1>, C4<1>; -L_0x24e14a0 .delay (20000,20000,20000) L_0x24e14a0/d; -L_0x24e1680/d .functor XOR 1, L_0x24e0ea0, L_0x24e1130, C4<0>, C4<0>; -L_0x24e1680 .delay (40000,40000,40000) L_0x24e1680/d; -L_0x24e17a0/d .functor XOR 1, L_0x24e1680, L_0x24cbe30, C4<0>, C4<0>; -L_0x24e17a0 .delay (40000,40000,40000) L_0x24e17a0/d; -L_0x24e18c0/d .functor AND 1, L_0x24e0ea0, L_0x24e1130, C4<1>, C4<1>; -L_0x24e18c0 .delay (20000,20000,20000) L_0x24e18c0/d; -L_0x24e1a60/d .functor AND 1, L_0x24e1680, L_0x24cbe30, C4<1>, C4<1>; -L_0x24e1a60 .delay (20000,20000,20000) L_0x24e1a60/d; -L_0x24e1b50/d .functor OR 1, L_0x24e18c0, L_0x24e1a60, C4<0>, C4<0>; -L_0x24e1b50 .delay (20000,20000,20000) L_0x24e1b50/d; -v0x243f490_0 .net "A", 0 0, L_0x24e0ea0; 1 drivers -v0x243f550_0 .net "AandB", 0 0, L_0x24e18c0; 1 drivers -v0x243f5f0_0 .net "AddSubSLTSum", 0 0, L_0x24e17a0; 1 drivers -v0x243f690_0 .net "AxorB", 0 0, L_0x24e1680; 1 drivers -v0x243f710_0 .net "B", 0 0, L_0x24cbd00; 1 drivers -v0x243f7c0_0 .net "BornB", 0 0, L_0x24e1130; 1 drivers -v0x243f880_0 .net "CINandAxorB", 0 0, L_0x24e1a60; 1 drivers -v0x243f900_0 .alias "Command", 2 0, v0x2463430_0; -v0x243f9d0_0 .net *"_s3", 0 0, L_0x24e1400; 1 drivers -v0x243fa50_0 .net *"_s5", 0 0, L_0x24e15e0; 1 drivers -v0x243fb50_0 .net "carryin", 0 0, L_0x24cbe30; 1 drivers -v0x243fbf0_0 .net "carryout", 0 0, L_0x24e1b50; 1 drivers -v0x243fd00_0 .net "nB", 0 0, L_0x24dfda0; 1 drivers -v0x243fdb0_0 .net "nCmd2", 0 0, L_0x24e1360; 1 drivers -v0x243feb0_0 .net "subtract", 0 0, L_0x24e14a0; 1 drivers -L_0x24e12c0 .part C4, 0, 1; -L_0x24e1400 .part C4, 2, 1; -L_0x24e15e0 .part C4, 0, 1; -S_0x243ef10 .scope module, "mux0" "TwoInMux" 2 105, 2 8, S_0x243ee20; - .timescale -9 -12; -L_0x24dff00/d .functor NOT 1, L_0x24e12c0, C4<0>, C4<0>, C4<0>; -L_0x24dff00 .delay (10000,10000,10000) L_0x24dff00/d; -L_0x24e0f50/d .functor AND 1, L_0x24cbd00, L_0x24dff00, C4<1>, C4<1>; -L_0x24e0f50 .delay (20000,20000,20000) L_0x24e0f50/d; -L_0x24e1040/d .functor AND 1, L_0x24dfda0, L_0x24e12c0, C4<1>, C4<1>; -L_0x24e1040 .delay (20000,20000,20000) L_0x24e1040/d; -L_0x24e1130/d .functor OR 1, L_0x24e0f50, L_0x24e1040, C4<0>, C4<0>; -L_0x24e1130 .delay (20000,20000,20000) L_0x24e1130/d; -v0x243f000_0 .net "S", 0 0, L_0x24e12c0; 1 drivers -v0x243f080_0 .alias "in0", 0 0, v0x243f710_0; -v0x243f120_0 .alias "in1", 0 0, v0x243fd00_0; -v0x243f1c0_0 .net "nS", 0 0, L_0x24dff00; 1 drivers -v0x243f270_0 .net "out0", 0 0, L_0x24e0f50; 1 drivers -v0x243f310_0 .net "out1", 0 0, L_0x24e1040; 1 drivers -v0x243f3f0_0 .alias "outfinal", 0 0, v0x243f7c0_0; -S_0x2413e60 .scope module, "trial1" "AndNand32" 2 280, 2 154, S_0x22690e0; - .timescale -9 -12; -P_0x24265d8 .param/l "size" 2 161, +C4<0100000>; -v0x2426a40_0 .alias "A", 31 0, v0x2462f10_0; -v0x2426ac0_0 .alias "AndNandOut", 31 0, v0x2463200_0; -v0x2426b40_0 .alias "B", 31 0, v0x24632b0_0; -v0x2426bf0_0 .alias "Command", 2 0, v0x2463430_0; -L_0x24e5dd0 .part/pv L_0x24e5ba0, 1, 1, 32; -L_0x2490320 .part C4, 1, 1; -L_0x24903c0 .part C4, 1, 1; -L_0x24e6b80 .part/pv L_0x24e6930, 2, 1, 32; -L_0x24e6c20 .part C4, 2, 1; -L_0x24e6cc0 .part C4, 2, 1; -L_0x24e7610 .part/pv L_0x24e73a0, 3, 1, 32; -L_0x24e76b0 .part C4, 3, 1; -L_0x24e77a0 .part C4, 3, 1; -L_0x24e8070 .part/pv L_0x24e7e00, 4, 1, 32; -L_0x24e8170 .part C4, 4, 1; -L_0x24e8210 .part C4, 4, 1; -L_0x24e8ae0 .part/pv L_0x24e8870, 5, 1, 32; -L_0x24e8b80 .part C4, 5, 1; -L_0x24e8ca0 .part C4, 5, 1; -L_0x24e95b0 .part/pv L_0x24e9340, 6, 1, 32; -L_0x24e96e0 .part C4, 6, 1; -L_0x24e9780 .part C4, 6, 1; -L_0x24ea0b0 .part/pv L_0x24e9e40, 7, 1, 32; -L_0x24ea150 .part C4, 7, 1; -L_0x24e9870 .part C4, 7, 1; -L_0x24eab10 .part/pv L_0x24ea8a0, 8, 1, 32; -L_0x24ea1f0 .part C4, 8, 1; -L_0x24eac70 .part C4, 8, 1; -L_0x24eb590 .part/pv L_0x24eb320, 9, 1, 32; -L_0x24eb630 .part C4, 9, 1; -L_0x24ead60 .part C4, 9, 1; -L_0x24ec000 .part/pv L_0x24ebd90, 10, 1, 32; -L_0x24eb6d0 .part C4, 10, 1; -L_0x24ec190 .part C4, 10, 1; -L_0x24eca70 .part/pv L_0x24ec800, 11, 1, 32; -L_0x24ecb10 .part C4, 11, 1; -L_0x24ec280 .part C4, 11, 1; -L_0x24ed4e0 .part/pv L_0x24ed270, 12, 1, 32; -L_0x24ecbb0 .part C4, 12, 1; -L_0x24ed6a0 .part C4, 12, 1; -L_0x24edf60 .part/pv L_0x24edcf0, 13, 1, 32; -L_0x24ee000 .part C4, 13, 1; -L_0x24ed740 .part C4, 13, 1; -L_0x24ee9c0 .part/pv L_0x24ee750, 14, 1, 32; -L_0x24ee0a0 .part C4, 14, 1; -L_0x24ee140 .part C4, 14, 1; -L_0x24ef430 .part/pv L_0x24ef1c0, 15, 1, 32; -L_0x24ef4d0 .part C4, 15, 1; -L_0x24eec00 .part C4, 15, 1; -L_0x24efea0 .part/pv L_0x24efc30, 16, 1, 32; -L_0x24ef570 .part C4, 16, 1; -L_0x24ef610 .part C4, 16, 1; -L_0x24f0920 .part/pv L_0x24f06b0, 17, 1, 32; -L_0x24f09c0 .part C4, 17, 1; -L_0x24f0110 .part C4, 17, 1; -L_0x24f1380 .part/pv L_0x24f1110, 18, 1, 32; -L_0x24f0a60 .part C4, 18, 1; -L_0x24f0b00 .part C4, 18, 1; -L_0x24f1e00 .part/pv L_0x24f1b90, 19, 1, 32; -L_0x24f1ea0 .part C4, 19, 1; -L_0x24f1420 .part C4, 19, 1; -L_0x24f2860 .part/pv L_0x24f25f0, 20, 1, 32; -L_0x24f1f40 .part C4, 20, 1; -L_0x24f1fe0 .part C4, 20, 1; -L_0x24f32d0 .part/pv L_0x24f3060, 21, 1, 32; -L_0x24f3370 .part C4, 21, 1; -L_0x24f2900 .part C4, 21, 1; -L_0x24f3d40 .part/pv L_0x24f3ad0, 22, 1, 32; -L_0x24f3410 .part C4, 22, 1; -L_0x24f34b0 .part C4, 22, 1; -L_0x24f47c0 .part/pv L_0x24f4550, 23, 1, 32; -L_0x24f4860 .part C4, 23, 1; -L_0x24f3de0 .part C4, 23, 1; -L_0x24f5220 .part/pv L_0x24f4fb0, 24, 1, 32; -L_0x24f4900 .part C4, 24, 1; -L_0x24f49a0 .part C4, 24, 1; -L_0x24f5c90 .part/pv L_0x24f5a20, 25, 1, 32; -L_0x24f5d30 .part C4, 25, 1; -L_0x24f52c0 .part C4, 25, 1; -L_0x24f66f0 .part/pv L_0x24f6480, 26, 1, 32; -L_0x24f5dd0 .part C4, 26, 1; -L_0x24f5e70 .part C4, 26, 1; -L_0x24f7160 .part/pv L_0x24f6ef0, 27, 1, 32; -L_0x24f7200 .part C4, 27, 1; -L_0x24f6790 .part C4, 27, 1; -L_0x24f7bd0 .part/pv L_0x24f7960, 28, 1, 32; -L_0x24f72a0 .part C4, 28, 1; -L_0x24f7340 .part C4, 28, 1; -L_0x24f8650 .part/pv L_0x24f83e0, 29, 1, 32; -L_0x24f86f0 .part C4, 29, 1; -L_0x24df8f0 .part C4, 29, 1; -L_0x24f97b0 .part/pv L_0x24df9e0, 30, 1, 32; -L_0x24df630 .part C4, 30, 1; -L_0x24df6d0 .part C4, 30, 1; -L_0x24fa160 .part/pv L_0x24f9f30, 31, 1, 32; -L_0x24fa200 .part C4, 31, 1; -L_0x24f9850 .part C4, 31, 1; -L_0x24fab10 .part/pv L_0x24fa8e0, 0, 1, 32; -L_0x24fa2a0 .part C4, 0, 1; -L_0x24fa340 .part C4, 0, 1; -S_0x243dab0 .scope module, "attempt2" "AndNand" 2 165, 2 48, S_0x2413e60; - .timescale -9 -12; -L_0x24f9940/d .functor NAND 1, L_0x24fa2a0, L_0x24fa340, C4<1>, C4<1>; -L_0x24f9940 .delay (10000,10000,10000) L_0x24f9940/d; -L_0x24f9aa0/d .functor NOT 1, L_0x24f9940, C4<0>, C4<0>, C4<0>; -L_0x24f9aa0 .delay (10000,10000,10000) L_0x24f9aa0/d; -v0x243e0d0_0 .net "A", 0 0, L_0x24fa2a0; 1 drivers -v0x243e190_0 .net "AandB", 0 0, L_0x24f9aa0; 1 drivers -v0x243e210_0 .net "AnandB", 0 0, L_0x24f9940; 1 drivers -v0x243e2c0_0 .net "AndNandOut", 0 0, L_0x24fa8e0; 1 drivers -v0x243e3a0_0 .net "B", 0 0, L_0x24fa340; 1 drivers -v0x243e420_0 .alias "Command", 2 0, v0x2463430_0; -L_0x24faa70 .part C4, 0, 1; -S_0x243dba0 .scope module, "potato" "TwoInMux" 2 60, 2 8, S_0x243dab0; - .timescale -9 -12; -L_0x24fa620/d .functor NOT 1, L_0x24faa70, C4<0>, C4<0>, C4<0>; -L_0x24fa620 .delay (10000,10000,10000) L_0x24fa620/d; -L_0x24fa6c0/d .functor AND 1, L_0x24f9aa0, L_0x24fa620, C4<1>, C4<1>; -L_0x24fa6c0 .delay (20000,20000,20000) L_0x24fa6c0/d; -L_0x24fa7b0/d .functor AND 1, L_0x24f9940, L_0x24faa70, C4<1>, C4<1>; -L_0x24fa7b0 .delay (20000,20000,20000) L_0x24fa7b0/d; -L_0x24fa8e0/d .functor OR 1, L_0x24fa6c0, L_0x24fa7b0, C4<0>, C4<0>; -L_0x24fa8e0 .delay (20000,20000,20000) L_0x24fa8e0/d; -v0x243dc90_0 .net "S", 0 0, L_0x24faa70; 1 drivers -v0x243dd10_0 .alias "in0", 0 0, v0x243e190_0; -v0x243dd90_0 .alias "in1", 0 0, v0x243e210_0; -v0x243de30_0 .net "nS", 0 0, L_0x24fa620; 1 drivers -v0x243deb0_0 .net "out0", 0 0, L_0x24fa6c0; 1 drivers -v0x243df50_0 .net "out1", 0 0, L_0x24fa7b0; 1 drivers -v0x243e030_0 .alias "outfinal", 0 0, v0x243e2c0_0; -S_0x243cef0 .scope generate, "andbits[1]" "andbits[1]" 2 169, 2 169, S_0x2413e60; - .timescale -9 -12; -P_0x243cfe8 .param/l "i" 2 169, +C4<01>; -S_0x243d060 .scope module, "attempt" "AndNand" 2 171, 2 48, S_0x243cef0; - .timescale -9 -12; -L_0x24e4670/d .functor NAND 1, L_0x2490320, L_0x24903c0, C4<1>, C4<1>; -L_0x24e4670 .delay (10000,10000,10000) L_0x24e4670/d; -L_0x24e4730/d .functor NOT 1, L_0x24e4670, C4<0>, C4<0>, C4<0>; -L_0x24e4730 .delay (10000,10000,10000) L_0x24e4730/d; -v0x243d6a0_0 .net "A", 0 0, L_0x2490320; 1 drivers -v0x243d760_0 .net "AandB", 0 0, L_0x24e4730; 1 drivers -v0x243d7e0_0 .net "AnandB", 0 0, L_0x24e4670; 1 drivers -v0x243d890_0 .net "AndNandOut", 0 0, L_0x24e5ba0; 1 drivers -v0x243d970_0 .net "B", 0 0, L_0x24903c0; 1 drivers -v0x243d9f0_0 .alias "Command", 2 0, v0x2463430_0; -L_0x24e5d30 .part C4, 0, 1; -S_0x243d150 .scope module, "potato" "TwoInMux" 2 60, 2 8, S_0x243d060; - .timescale -9 -12; -L_0x24e4860/d .functor NOT 1, L_0x24e5d30, C4<0>, C4<0>, C4<0>; -L_0x24e4860 .delay (10000,10000,10000) L_0x24e4860/d; -L_0x24e4920/d .functor AND 1, L_0x24e4730, L_0x24e4860, C4<1>, C4<1>; -L_0x24e4920 .delay (20000,20000,20000) L_0x24e4920/d; -L_0x24e5a70/d .functor AND 1, L_0x24e4670, L_0x24e5d30, C4<1>, C4<1>; -L_0x24e5a70 .delay (20000,20000,20000) L_0x24e5a70/d; -L_0x24e5ba0/d .functor OR 1, L_0x24e4920, L_0x24e5a70, C4<0>, C4<0>; -L_0x24e5ba0 .delay (20000,20000,20000) L_0x24e5ba0/d; -v0x243d240_0 .net "S", 0 0, L_0x24e5d30; 1 drivers -v0x243d2c0_0 .alias "in0", 0 0, v0x243d760_0; -v0x243d360_0 .alias "in1", 0 0, v0x243d7e0_0; -v0x243d400_0 .net "nS", 0 0, L_0x24e4860; 1 drivers -v0x243d480_0 .net "out0", 0 0, L_0x24e4920; 1 drivers -v0x243d520_0 .net "out1", 0 0, L_0x24e5a70; 1 drivers -v0x243d600_0 .alias "outfinal", 0 0, v0x243d890_0; -S_0x243c330 .scope generate, "andbits[2]" "andbits[2]" 2 169, 2 169, S_0x2413e60; - .timescale -9 -12; -P_0x243c428 .param/l "i" 2 169, +C4<010>; -S_0x243c4a0 .scope module, "attempt" "AndNand" 2 171, 2 48, S_0x243c330; - .timescale -9 -12; -L_0x24904b0/d .functor NAND 1, L_0x24e6c20, L_0x24e6cc0, C4<1>, C4<1>; -L_0x24904b0 .delay (10000,10000,10000) L_0x24904b0/d; -L_0x2490610/d .functor NOT 1, L_0x24904b0, C4<0>, C4<0>, C4<0>; -L_0x2490610 .delay (10000,10000,10000) L_0x2490610/d; -v0x243cae0_0 .net "A", 0 0, L_0x24e6c20; 1 drivers -v0x243cba0_0 .net "AandB", 0 0, L_0x2490610; 1 drivers -v0x243cc20_0 .net "AnandB", 0 0, L_0x24904b0; 1 drivers -v0x243ccd0_0 .net "AndNandOut", 0 0, L_0x24e6930; 1 drivers -v0x243cdb0_0 .net "B", 0 0, L_0x24e6cc0; 1 drivers -v0x243ce30_0 .alias "Command", 2 0, v0x2463430_0; -L_0x24e6ae0 .part C4, 0, 1; -S_0x243c590 .scope module, "potato" "TwoInMux" 2 60, 2 8, S_0x243c4a0; - .timescale -9 -12; -L_0x24906d0/d .functor NOT 1, L_0x24e6ae0, C4<0>, C4<0>, C4<0>; -L_0x24906d0 .delay (10000,10000,10000) L_0x24906d0/d; -L_0x24e6710/d .functor AND 1, L_0x2490610, L_0x24906d0, C4<1>, C4<1>; -L_0x24e6710 .delay (20000,20000,20000) L_0x24e6710/d; -L_0x24e6800/d .functor AND 1, L_0x24904b0, L_0x24e6ae0, C4<1>, C4<1>; -L_0x24e6800 .delay (20000,20000,20000) L_0x24e6800/d; -L_0x24e6930/d .functor OR 1, L_0x24e6710, L_0x24e6800, C4<0>, C4<0>; -L_0x24e6930 .delay (20000,20000,20000) L_0x24e6930/d; -v0x243c680_0 .net "S", 0 0, L_0x24e6ae0; 1 drivers -v0x243c700_0 .alias "in0", 0 0, v0x243cba0_0; -v0x243c7a0_0 .alias "in1", 0 0, v0x243cc20_0; -v0x243c840_0 .net "nS", 0 0, L_0x24906d0; 1 drivers -v0x243c8c0_0 .net "out0", 0 0, L_0x24e6710; 1 drivers -v0x243c960_0 .net "out1", 0 0, L_0x24e6800; 1 drivers -v0x243ca40_0 .alias "outfinal", 0 0, v0x243ccd0_0; -S_0x243b770 .scope generate, "andbits[3]" "andbits[3]" 2 169, 2 169, S_0x2413e60; - .timescale -9 -12; -P_0x243b868 .param/l "i" 2 169, +C4<011>; -S_0x243b8e0 .scope module, "attempt" "AndNand" 2 171, 2 48, S_0x243b770; - .timescale -9 -12; -L_0x24e6df0/d .functor NAND 1, L_0x24e76b0, L_0x24e77a0, C4<1>, C4<1>; -L_0x24e6df0 .delay (10000,10000,10000) L_0x24e6df0/d; -L_0x24e6f50/d .functor NOT 1, L_0x24e6df0, C4<0>, C4<0>, C4<0>; -L_0x24e6f50 .delay (10000,10000,10000) L_0x24e6f50/d; -v0x243bf20_0 .net "A", 0 0, L_0x24e76b0; 1 drivers -v0x243bfe0_0 .net "AandB", 0 0, L_0x24e6f50; 1 drivers -v0x243c060_0 .net "AnandB", 0 0, L_0x24e6df0; 1 drivers -v0x243c110_0 .net "AndNandOut", 0 0, L_0x24e73a0; 1 drivers -v0x243c1f0_0 .net "B", 0 0, L_0x24e77a0; 1 drivers -v0x243c270_0 .alias "Command", 2 0, v0x2463430_0; -L_0x24e7570 .part C4, 0, 1; -S_0x243b9d0 .scope module, "potato" "TwoInMux" 2 60, 2 8, S_0x243b8e0; - .timescale -9 -12; -L_0x24e7080/d .functor NOT 1, L_0x24e7570, C4<0>, C4<0>, C4<0>; -L_0x24e7080 .delay (10000,10000,10000) L_0x24e7080/d; -L_0x24e7140/d .functor AND 1, L_0x24e6f50, L_0x24e7080, C4<1>, C4<1>; -L_0x24e7140 .delay (20000,20000,20000) L_0x24e7140/d; -L_0x24e7250/d .functor AND 1, L_0x24e6df0, L_0x24e7570, C4<1>, C4<1>; -L_0x24e7250 .delay (20000,20000,20000) L_0x24e7250/d; -L_0x24e73a0/d .functor OR 1, L_0x24e7140, L_0x24e7250, C4<0>, C4<0>; -L_0x24e73a0 .delay (20000,20000,20000) L_0x24e73a0/d; -v0x243bac0_0 .net "S", 0 0, L_0x24e7570; 1 drivers -v0x243bb40_0 .alias "in0", 0 0, v0x243bfe0_0; -v0x243bbe0_0 .alias "in1", 0 0, v0x243c060_0; -v0x243bc80_0 .net "nS", 0 0, L_0x24e7080; 1 drivers -v0x243bd00_0 .net "out0", 0 0, L_0x24e7140; 1 drivers -v0x243bda0_0 .net "out1", 0 0, L_0x24e7250; 1 drivers -v0x243be80_0 .alias "outfinal", 0 0, v0x243c110_0; -S_0x243abb0 .scope generate, "andbits[4]" "andbits[4]" 2 169, 2 169, S_0x2413e60; - .timescale -9 -12; -P_0x243aca8 .param/l "i" 2 169, +C4<0100>; -S_0x243ad20 .scope module, "attempt" "AndNand" 2 171, 2 48, S_0x243abb0; - .timescale -9 -12; -L_0x24e7890/d .functor NAND 1, L_0x24e8170, L_0x24e8210, C4<1>, C4<1>; -L_0x24e7890 .delay (10000,10000,10000) L_0x24e7890/d; -L_0x24e79b0/d .functor NOT 1, L_0x24e7890, C4<0>, C4<0>, C4<0>; -L_0x24e79b0 .delay (10000,10000,10000) L_0x24e79b0/d; -v0x243b360_0 .net "A", 0 0, L_0x24e8170; 1 drivers -v0x243b420_0 .net "AandB", 0 0, L_0x24e79b0; 1 drivers -v0x243b4a0_0 .net "AnandB", 0 0, L_0x24e7890; 1 drivers -v0x243b550_0 .net "AndNandOut", 0 0, L_0x24e7e00; 1 drivers -v0x243b630_0 .net "B", 0 0, L_0x24e8210; 1 drivers -v0x243b6b0_0 .alias "Command", 2 0, v0x2463430_0; -L_0x24e7fd0 .part C4, 0, 1; -S_0x243ae10 .scope module, "potato" "TwoInMux" 2 60, 2 8, S_0x243ad20; - .timescale -9 -12; -L_0x24e7ae0/d .functor NOT 1, L_0x24e7fd0, C4<0>, C4<0>, C4<0>; -L_0x24e7ae0 .delay (10000,10000,10000) L_0x24e7ae0/d; -L_0x24e7ba0/d .functor AND 1, L_0x24e79b0, L_0x24e7ae0, C4<1>, C4<1>; -L_0x24e7ba0 .delay (20000,20000,20000) L_0x24e7ba0/d; -L_0x24e7cb0/d .functor AND 1, L_0x24e7890, L_0x24e7fd0, C4<1>, C4<1>; -L_0x24e7cb0 .delay (20000,20000,20000) L_0x24e7cb0/d; -L_0x24e7e00/d .functor OR 1, L_0x24e7ba0, L_0x24e7cb0, C4<0>, C4<0>; -L_0x24e7e00 .delay (20000,20000,20000) L_0x24e7e00/d; -v0x243af00_0 .net "S", 0 0, L_0x24e7fd0; 1 drivers -v0x243af80_0 .alias "in0", 0 0, v0x243b420_0; -v0x243b020_0 .alias "in1", 0 0, v0x243b4a0_0; -v0x243b0c0_0 .net "nS", 0 0, L_0x24e7ae0; 1 drivers -v0x243b140_0 .net "out0", 0 0, L_0x24e7ba0; 1 drivers -v0x243b1e0_0 .net "out1", 0 0, L_0x24e7cb0; 1 drivers -v0x243b2c0_0 .alias "outfinal", 0 0, v0x243b550_0; -S_0x2439ff0 .scope generate, "andbits[5]" "andbits[5]" 2 169, 2 169, S_0x2413e60; - .timescale -9 -12; -P_0x243a0e8 .param/l "i" 2 169, +C4<0101>; -S_0x243a160 .scope module, "attempt" "AndNand" 2 171, 2 48, S_0x2439ff0; - .timescale -9 -12; -L_0x24e8110/d .functor NAND 1, L_0x24e8b80, L_0x24e8ca0, C4<1>, C4<1>; -L_0x24e8110 .delay (10000,10000,10000) L_0x24e8110/d; -L_0x24e8420/d .functor NOT 1, L_0x24e8110, C4<0>, C4<0>, C4<0>; -L_0x24e8420 .delay (10000,10000,10000) L_0x24e8420/d; -v0x243a7a0_0 .net "A", 0 0, L_0x24e8b80; 1 drivers -v0x243a860_0 .net "AandB", 0 0, L_0x24e8420; 1 drivers -v0x243a8e0_0 .net "AnandB", 0 0, L_0x24e8110; 1 drivers -v0x243a990_0 .net "AndNandOut", 0 0, L_0x24e8870; 1 drivers -v0x243aa70_0 .net "B", 0 0, L_0x24e8ca0; 1 drivers -v0x243aaf0_0 .alias "Command", 2 0, v0x2463430_0; -L_0x24e8a40 .part C4, 0, 1; -S_0x243a250 .scope module, "potato" "TwoInMux" 2 60, 2 8, S_0x243a160; - .timescale -9 -12; -L_0x24e8550/d .functor NOT 1, L_0x24e8a40, C4<0>, C4<0>, C4<0>; -L_0x24e8550 .delay (10000,10000,10000) L_0x24e8550/d; -L_0x24e8610/d .functor AND 1, L_0x24e8420, L_0x24e8550, C4<1>, C4<1>; -L_0x24e8610 .delay (20000,20000,20000) L_0x24e8610/d; -L_0x24e8720/d .functor AND 1, L_0x24e8110, L_0x24e8a40, C4<1>, C4<1>; -L_0x24e8720 .delay (20000,20000,20000) L_0x24e8720/d; -L_0x24e8870/d .functor OR 1, L_0x24e8610, L_0x24e8720, C4<0>, C4<0>; -L_0x24e8870 .delay (20000,20000,20000) L_0x24e8870/d; -v0x243a340_0 .net "S", 0 0, L_0x24e8a40; 1 drivers -v0x243a3c0_0 .alias "in0", 0 0, v0x243a860_0; -v0x243a460_0 .alias "in1", 0 0, v0x243a8e0_0; -v0x243a500_0 .net "nS", 0 0, L_0x24e8550; 1 drivers -v0x243a580_0 .net "out0", 0 0, L_0x24e8610; 1 drivers -v0x243a620_0 .net "out1", 0 0, L_0x24e8720; 1 drivers -v0x243a700_0 .alias "outfinal", 0 0, v0x243a990_0; -S_0x2439440 .scope generate, "andbits[6]" "andbits[6]" 2 169, 2 169, S_0x2413e60; - .timescale -9 -12; -P_0x2439538 .param/l "i" 2 169, +C4<0110>; -S_0x24395b0 .scope module, "attempt" "AndNand" 2 171, 2 48, S_0x2439440; - .timescale -9 -12; -L_0x24e8d90/d .functor NAND 1, L_0x24e96e0, L_0x24e9780, C4<1>, C4<1>; -L_0x24e8d90 .delay (10000,10000,10000) L_0x24e8d90/d; -L_0x24e8ef0/d .functor NOT 1, L_0x24e8d90, C4<0>, C4<0>, C4<0>; -L_0x24e8ef0 .delay (10000,10000,10000) L_0x24e8ef0/d; -v0x2439c10_0 .net "A", 0 0, L_0x24e96e0; 1 drivers -v0x2439cd0_0 .net "AandB", 0 0, L_0x24e8ef0; 1 drivers -v0x2439d50_0 .net "AnandB", 0 0, L_0x24e8d90; 1 drivers -v0x2439dd0_0 .net "AndNandOut", 0 0, L_0x24e9340; 1 drivers -v0x2439eb0_0 .net "B", 0 0, L_0x24e9780; 1 drivers -v0x2439f30_0 .alias "Command", 2 0, v0x2463430_0; -L_0x24e9510 .part C4, 0, 1; -S_0x24396a0 .scope module, "potato" "TwoInMux" 2 60, 2 8, S_0x24395b0; - .timescale -9 -12; -L_0x24e9020/d .functor NOT 1, L_0x24e9510, C4<0>, C4<0>, C4<0>; -L_0x24e9020 .delay (10000,10000,10000) L_0x24e9020/d; -L_0x24e90e0/d .functor AND 1, L_0x24e8ef0, L_0x24e9020, C4<1>, C4<1>; -L_0x24e90e0 .delay (20000,20000,20000) L_0x24e90e0/d; -L_0x24e91f0/d .functor AND 1, L_0x24e8d90, L_0x24e9510, C4<1>, C4<1>; -L_0x24e91f0 .delay (20000,20000,20000) L_0x24e91f0/d; -L_0x24e9340/d .functor OR 1, L_0x24e90e0, L_0x24e91f0, C4<0>, C4<0>; -L_0x24e9340 .delay (20000,20000,20000) L_0x24e9340/d; -v0x2439790_0 .net "S", 0 0, L_0x24e9510; 1 drivers -v0x2439830_0 .alias "in0", 0 0, v0x2439cd0_0; -v0x24398d0_0 .alias "in1", 0 0, v0x2439d50_0; -v0x2439970_0 .net "nS", 0 0, L_0x24e9020; 1 drivers -v0x24399f0_0 .net "out0", 0 0, L_0x24e90e0; 1 drivers -v0x2439a90_0 .net "out1", 0 0, L_0x24e91f0; 1 drivers -v0x2439b70_0 .alias "outfinal", 0 0, v0x2439dd0_0; -S_0x2438870 .scope generate, "andbits[7]" "andbits[7]" 2 169, 2 169, S_0x2413e60; - .timescale -9 -12; -P_0x2438968 .param/l "i" 2 169, +C4<0111>; -S_0x24389e0 .scope module, "attempt" "AndNand" 2 171, 2 48, S_0x2438870; - .timescale -9 -12; -L_0x24e9650/d .functor NAND 1, L_0x24ea150, L_0x24e9870, C4<1>, C4<1>; -L_0x24e9650 .delay (10000,10000,10000) L_0x24e9650/d; -L_0x24e99f0/d .functor NOT 1, L_0x24e9650, C4<0>, C4<0>, C4<0>; -L_0x24e99f0 .delay (10000,10000,10000) L_0x24e99f0/d; -v0x2439000_0 .net "A", 0 0, L_0x24ea150; 1 drivers -v0x24390c0_0 .net "AandB", 0 0, L_0x24e99f0; 1 drivers -v0x2439170_0 .net "AnandB", 0 0, L_0x24e9650; 1 drivers -v0x2439220_0 .net "AndNandOut", 0 0, L_0x24e9e40; 1 drivers -v0x2439300_0 .net "B", 0 0, L_0x24e9870; 1 drivers -v0x2439380_0 .alias "Command", 2 0, v0x2463430_0; -L_0x24ea010 .part C4, 0, 1; -S_0x2438ad0 .scope module, "potato" "TwoInMux" 2 60, 2 8, S_0x24389e0; - .timescale -9 -12; -L_0x24e9b20/d .functor NOT 1, L_0x24ea010, C4<0>, C4<0>, C4<0>; -L_0x24e9b20 .delay (10000,10000,10000) L_0x24e9b20/d; -L_0x24e9be0/d .functor AND 1, L_0x24e99f0, L_0x24e9b20, C4<1>, C4<1>; -L_0x24e9be0 .delay (20000,20000,20000) L_0x24e9be0/d; -L_0x24e9cf0/d .functor AND 1, L_0x24e9650, L_0x24ea010, C4<1>, C4<1>; -L_0x24e9cf0 .delay (20000,20000,20000) L_0x24e9cf0/d; -L_0x24e9e40/d .functor OR 1, L_0x24e9be0, L_0x24e9cf0, C4<0>, C4<0>; -L_0x24e9e40 .delay (20000,20000,20000) L_0x24e9e40/d; -v0x2438bc0_0 .net "S", 0 0, L_0x24ea010; 1 drivers -v0x2438c40_0 .alias "in0", 0 0, v0x24390c0_0; -v0x2438ce0_0 .alias "in1", 0 0, v0x2439170_0; -v0x2438d80_0 .net "nS", 0 0, L_0x24e9b20; 1 drivers -v0x2438e00_0 .net "out0", 0 0, L_0x24e9be0; 1 drivers -v0x2438ea0_0 .net "out1", 0 0, L_0x24e9cf0; 1 drivers -v0x2438f80_0 .alias "outfinal", 0 0, v0x2439220_0; -S_0x2437cb0 .scope generate, "andbits[8]" "andbits[8]" 2 169, 2 169, S_0x2413e60; - .timescale -9 -12; -P_0x2437da8 .param/l "i" 2 169, +C4<01000>; -S_0x2437e20 .scope module, "attempt" "AndNand" 2 171, 2 48, S_0x2437cb0; - .timescale -9 -12; -L_0x24ea2f0/d .functor NAND 1, L_0x24ea1f0, L_0x24eac70, C4<1>, C4<1>; -L_0x24ea2f0 .delay (10000,10000,10000) L_0x24ea2f0/d; -L_0x24ea450/d .functor NOT 1, L_0x24ea2f0, C4<0>, C4<0>, C4<0>; -L_0x24ea450 .delay (10000,10000,10000) L_0x24ea450/d; -v0x2438460_0 .net "A", 0 0, L_0x24ea1f0; 1 drivers -v0x2438520_0 .net "AandB", 0 0, L_0x24ea450; 1 drivers -v0x24385a0_0 .net "AnandB", 0 0, L_0x24ea2f0; 1 drivers -v0x2438650_0 .net "AndNandOut", 0 0, L_0x24ea8a0; 1 drivers -v0x2438730_0 .net "B", 0 0, L_0x24eac70; 1 drivers -v0x24387b0_0 .alias "Command", 2 0, v0x2463430_0; -L_0x24eaa70 .part C4, 0, 1; -S_0x2437f10 .scope module, "potato" "TwoInMux" 2 60, 2 8, S_0x2437e20; - .timescale -9 -12; -L_0x24ea580/d .functor NOT 1, L_0x24eaa70, C4<0>, C4<0>, C4<0>; -L_0x24ea580 .delay (10000,10000,10000) L_0x24ea580/d; -L_0x24ea640/d .functor AND 1, L_0x24ea450, L_0x24ea580, C4<1>, C4<1>; -L_0x24ea640 .delay (20000,20000,20000) L_0x24ea640/d; -L_0x24ea750/d .functor AND 1, L_0x24ea2f0, L_0x24eaa70, C4<1>, C4<1>; -L_0x24ea750 .delay (20000,20000,20000) L_0x24ea750/d; -L_0x24ea8a0/d .functor OR 1, L_0x24ea640, L_0x24ea750, C4<0>, C4<0>; -L_0x24ea8a0 .delay (20000,20000,20000) L_0x24ea8a0/d; -v0x2438000_0 .net "S", 0 0, L_0x24eaa70; 1 drivers -v0x2438080_0 .alias "in0", 0 0, v0x2438520_0; -v0x2438120_0 .alias "in1", 0 0, v0x24385a0_0; -v0x24381c0_0 .net "nS", 0 0, L_0x24ea580; 1 drivers -v0x2438240_0 .net "out0", 0 0, L_0x24ea640; 1 drivers -v0x24382e0_0 .net "out1", 0 0, L_0x24ea750; 1 drivers -v0x24383c0_0 .alias "outfinal", 0 0, v0x2438650_0; -S_0x24370f0 .scope generate, "andbits[9]" "andbits[9]" 2 169, 2 169, S_0x2413e60; - .timescale -9 -12; -P_0x24371e8 .param/l "i" 2 169, +C4<01001>; -S_0x2437260 .scope module, "attempt" "AndNand" 2 171, 2 48, S_0x24370f0; - .timescale -9 -12; -L_0x24eabb0/d .functor NAND 1, L_0x24eb630, L_0x24ead60, C4<1>, C4<1>; -L_0x24eabb0 .delay (10000,10000,10000) L_0x24eabb0/d; -L_0x24eaed0/d .functor NOT 1, L_0x24eabb0, C4<0>, C4<0>, C4<0>; -L_0x24eaed0 .delay (10000,10000,10000) L_0x24eaed0/d; -v0x24378a0_0 .net "A", 0 0, L_0x24eb630; 1 drivers -v0x2437960_0 .net "AandB", 0 0, L_0x24eaed0; 1 drivers -v0x24379e0_0 .net "AnandB", 0 0, L_0x24eabb0; 1 drivers -v0x2437a90_0 .net "AndNandOut", 0 0, L_0x24eb320; 1 drivers -v0x2437b70_0 .net "B", 0 0, L_0x24ead60; 1 drivers -v0x2437bf0_0 .alias "Command", 2 0, v0x2463430_0; -L_0x24eb4f0 .part C4, 0, 1; -S_0x2437350 .scope module, "potato" "TwoInMux" 2 60, 2 8, S_0x2437260; - .timescale -9 -12; -L_0x24eb000/d .functor NOT 1, L_0x24eb4f0, C4<0>, C4<0>, C4<0>; -L_0x24eb000 .delay (10000,10000,10000) L_0x24eb000/d; -L_0x24eb0c0/d .functor AND 1, L_0x24eaed0, L_0x24eb000, C4<1>, C4<1>; -L_0x24eb0c0 .delay (20000,20000,20000) L_0x24eb0c0/d; -L_0x24eb1d0/d .functor AND 1, L_0x24eabb0, L_0x24eb4f0, C4<1>, C4<1>; -L_0x24eb1d0 .delay (20000,20000,20000) L_0x24eb1d0/d; -L_0x24eb320/d .functor OR 1, L_0x24eb0c0, L_0x24eb1d0, C4<0>, C4<0>; -L_0x24eb320 .delay (20000,20000,20000) L_0x24eb320/d; -v0x2437440_0 .net "S", 0 0, L_0x24eb4f0; 1 drivers -v0x24374c0_0 .alias "in0", 0 0, v0x2437960_0; -v0x2437560_0 .alias "in1", 0 0, v0x24379e0_0; -v0x2437600_0 .net "nS", 0 0, L_0x24eb000; 1 drivers -v0x2437680_0 .net "out0", 0 0, L_0x24eb0c0; 1 drivers -v0x2437720_0 .net "out1", 0 0, L_0x24eb1d0; 1 drivers -v0x2437800_0 .alias "outfinal", 0 0, v0x2437a90_0; -S_0x2436530 .scope generate, "andbits[10]" "andbits[10]" 2 169, 2 169, S_0x2413e60; - .timescale -9 -12; -P_0x2436628 .param/l "i" 2 169, +C4<01010>; -S_0x24366a0 .scope module, "attempt" "AndNand" 2 171, 2 48, S_0x2436530; - .timescale -9 -12; -L_0x24eb800/d .functor NAND 1, L_0x24eb6d0, L_0x24ec190, C4<1>, C4<1>; -L_0x24eb800 .delay (10000,10000,10000) L_0x24eb800/d; -L_0x24eb940/d .functor NOT 1, L_0x24eb800, C4<0>, C4<0>, C4<0>; -L_0x24eb940 .delay (10000,10000,10000) L_0x24eb940/d; -v0x2436ce0_0 .net "A", 0 0, L_0x24eb6d0; 1 drivers -v0x2436da0_0 .net "AandB", 0 0, L_0x24eb940; 1 drivers -v0x2436e20_0 .net "AnandB", 0 0, L_0x24eb800; 1 drivers -v0x2436ed0_0 .net "AndNandOut", 0 0, L_0x24ebd90; 1 drivers -v0x2436fb0_0 .net "B", 0 0, L_0x24ec190; 1 drivers -v0x2437030_0 .alias "Command", 2 0, v0x2463430_0; -L_0x24ebf60 .part C4, 0, 1; -S_0x2436790 .scope module, "potato" "TwoInMux" 2 60, 2 8, S_0x24366a0; - .timescale -9 -12; -L_0x24eba70/d .functor NOT 1, L_0x24ebf60, C4<0>, C4<0>, C4<0>; -L_0x24eba70 .delay (10000,10000,10000) L_0x24eba70/d; -L_0x24ebb30/d .functor AND 1, L_0x24eb940, L_0x24eba70, C4<1>, C4<1>; -L_0x24ebb30 .delay (20000,20000,20000) L_0x24ebb30/d; -L_0x24ebc40/d .functor AND 1, L_0x24eb800, L_0x24ebf60, C4<1>, C4<1>; -L_0x24ebc40 .delay (20000,20000,20000) L_0x24ebc40/d; -L_0x24ebd90/d .functor OR 1, L_0x24ebb30, L_0x24ebc40, C4<0>, C4<0>; -L_0x24ebd90 .delay (20000,20000,20000) L_0x24ebd90/d; -v0x2436880_0 .net "S", 0 0, L_0x24ebf60; 1 drivers -v0x2436900_0 .alias "in0", 0 0, v0x2436da0_0; -v0x24369a0_0 .alias "in1", 0 0, v0x2436e20_0; -v0x2436a40_0 .net "nS", 0 0, L_0x24eba70; 1 drivers -v0x2436ac0_0 .net "out0", 0 0, L_0x24ebb30; 1 drivers -v0x2436b60_0 .net "out1", 0 0, L_0x24ebc40; 1 drivers -v0x2436c40_0 .alias "outfinal", 0 0, v0x2436ed0_0; -S_0x2435970 .scope generate, "andbits[11]" "andbits[11]" 2 169, 2 169, S_0x2413e60; - .timescale -9 -12; -P_0x2435a68 .param/l "i" 2 169, +C4<01011>; -S_0x2435ae0 .scope module, "attempt" "AndNand" 2 171, 2 48, S_0x2435970; - .timescale -9 -12; -L_0x24ec0a0/d .functor NAND 1, L_0x24ecb10, L_0x24ec280, C4<1>, C4<1>; -L_0x24ec0a0 .delay (10000,10000,10000) L_0x24ec0a0/d; -L_0x24ec3d0/d .functor NOT 1, L_0x24ec0a0, C4<0>, C4<0>, C4<0>; -L_0x24ec3d0 .delay (10000,10000,10000) L_0x24ec3d0/d; -v0x2436120_0 .net "A", 0 0, L_0x24ecb10; 1 drivers -v0x24361e0_0 .net "AandB", 0 0, L_0x24ec3d0; 1 drivers -v0x2436260_0 .net "AnandB", 0 0, L_0x24ec0a0; 1 drivers -v0x2436310_0 .net "AndNandOut", 0 0, L_0x24ec800; 1 drivers -v0x24363f0_0 .net "B", 0 0, L_0x24ec280; 1 drivers -v0x2436470_0 .alias "Command", 2 0, v0x2463430_0; -L_0x24ec9d0 .part C4, 0, 1; -S_0x2435bd0 .scope module, "potato" "TwoInMux" 2 60, 2 8, S_0x2435ae0; - .timescale -9 -12; -L_0x24ec4e0/d .functor NOT 1, L_0x24ec9d0, C4<0>, C4<0>, C4<0>; -L_0x24ec4e0 .delay (10000,10000,10000) L_0x24ec4e0/d; -L_0x24ec5a0/d .functor AND 1, L_0x24ec3d0, L_0x24ec4e0, C4<1>, C4<1>; -L_0x24ec5a0 .delay (20000,20000,20000) L_0x24ec5a0/d; -L_0x24ec6b0/d .functor AND 1, L_0x24ec0a0, L_0x24ec9d0, C4<1>, C4<1>; -L_0x24ec6b0 .delay (20000,20000,20000) L_0x24ec6b0/d; -L_0x24ec800/d .functor OR 1, L_0x24ec5a0, L_0x24ec6b0, C4<0>, C4<0>; -L_0x24ec800 .delay (20000,20000,20000) L_0x24ec800/d; -v0x2435cc0_0 .net "S", 0 0, L_0x24ec9d0; 1 drivers -v0x2435d40_0 .alias "in0", 0 0, v0x24361e0_0; -v0x2435de0_0 .alias "in1", 0 0, v0x2436260_0; -v0x2435e80_0 .net "nS", 0 0, L_0x24ec4e0; 1 drivers -v0x2435f00_0 .net "out0", 0 0, L_0x24ec5a0; 1 drivers -v0x2435fa0_0 .net "out1", 0 0, L_0x24ec6b0; 1 drivers -v0x2436080_0 .alias "outfinal", 0 0, v0x2436310_0; -S_0x2434db0 .scope generate, "andbits[12]" "andbits[12]" 2 169, 2 169, S_0x2413e60; - .timescale -9 -12; -P_0x2434ea8 .param/l "i" 2 169, +C4<01100>; -S_0x2434f20 .scope module, "attempt" "AndNand" 2 171, 2 48, S_0x2434db0; - .timescale -9 -12; -L_0x24eccc0/d .functor NAND 1, L_0x24ecbb0, L_0x24ed6a0, C4<1>, C4<1>; -L_0x24eccc0 .delay (10000,10000,10000) L_0x24eccc0/d; -L_0x24ece20/d .functor NOT 1, L_0x24eccc0, C4<0>, C4<0>, C4<0>; -L_0x24ece20 .delay (10000,10000,10000) L_0x24ece20/d; -v0x2435560_0 .net "A", 0 0, L_0x24ecbb0; 1 drivers -v0x2435620_0 .net "AandB", 0 0, L_0x24ece20; 1 drivers -v0x24356a0_0 .net "AnandB", 0 0, L_0x24eccc0; 1 drivers -v0x2435750_0 .net "AndNandOut", 0 0, L_0x24ed270; 1 drivers -v0x2435830_0 .net "B", 0 0, L_0x24ed6a0; 1 drivers -v0x24358b0_0 .alias "Command", 2 0, v0x2463430_0; -L_0x24ed440 .part C4, 0, 1; -S_0x2435010 .scope module, "potato" "TwoInMux" 2 60, 2 8, S_0x2434f20; - .timescale -9 -12; -L_0x24ecf50/d .functor NOT 1, L_0x24ed440, C4<0>, C4<0>, C4<0>; -L_0x24ecf50 .delay (10000,10000,10000) L_0x24ecf50/d; -L_0x24ed010/d .functor AND 1, L_0x24ece20, L_0x24ecf50, C4<1>, C4<1>; -L_0x24ed010 .delay (20000,20000,20000) L_0x24ed010/d; -L_0x24ed120/d .functor AND 1, L_0x24eccc0, L_0x24ed440, C4<1>, C4<1>; -L_0x24ed120 .delay (20000,20000,20000) L_0x24ed120/d; -L_0x24ed270/d .functor OR 1, L_0x24ed010, L_0x24ed120, C4<0>, C4<0>; -L_0x24ed270 .delay (20000,20000,20000) L_0x24ed270/d; -v0x2435100_0 .net "S", 0 0, L_0x24ed440; 1 drivers -v0x2435180_0 .alias "in0", 0 0, v0x2435620_0; -v0x2435220_0 .alias "in1", 0 0, v0x24356a0_0; -v0x24352c0_0 .net "nS", 0 0, L_0x24ecf50; 1 drivers -v0x2435340_0 .net "out0", 0 0, L_0x24ed010; 1 drivers -v0x24353e0_0 .net "out1", 0 0, L_0x24ed120; 1 drivers -v0x24354c0_0 .alias "outfinal", 0 0, v0x2435750_0; -S_0x24341f0 .scope generate, "andbits[13]" "andbits[13]" 2 169, 2 169, S_0x2413e60; - .timescale -9 -12; -P_0x24342e8 .param/l "i" 2 169, +C4<01101>; -S_0x2434360 .scope module, "attempt" "AndNand" 2 171, 2 48, S_0x24341f0; - .timescale -9 -12; -L_0x24ed580/d .functor NAND 1, L_0x24ee000, L_0x24ed740, C4<1>, C4<1>; -L_0x24ed580 .delay (10000,10000,10000) L_0x24ed580/d; -L_0x24ed8c0/d .functor NOT 1, L_0x24ed580, C4<0>, C4<0>, C4<0>; -L_0x24ed8c0 .delay (10000,10000,10000) L_0x24ed8c0/d; -v0x24349a0_0 .net "A", 0 0, L_0x24ee000; 1 drivers -v0x2434a60_0 .net "AandB", 0 0, L_0x24ed8c0; 1 drivers -v0x2434ae0_0 .net "AnandB", 0 0, L_0x24ed580; 1 drivers -v0x2434b90_0 .net "AndNandOut", 0 0, L_0x24edcf0; 1 drivers -v0x2434c70_0 .net "B", 0 0, L_0x24ed740; 1 drivers -v0x2434cf0_0 .alias "Command", 2 0, v0x2463430_0; -L_0x24edec0 .part C4, 0, 1; -S_0x2434450 .scope module, "potato" "TwoInMux" 2 60, 2 8, S_0x2434360; - .timescale -9 -12; -L_0x24ed9d0/d .functor NOT 1, L_0x24edec0, C4<0>, C4<0>, C4<0>; -L_0x24ed9d0 .delay (10000,10000,10000) L_0x24ed9d0/d; -L_0x24eda90/d .functor AND 1, L_0x24ed8c0, L_0x24ed9d0, C4<1>, C4<1>; -L_0x24eda90 .delay (20000,20000,20000) L_0x24eda90/d; -L_0x24edba0/d .functor AND 1, L_0x24ed580, L_0x24edec0, C4<1>, C4<1>; -L_0x24edba0 .delay (20000,20000,20000) L_0x24edba0/d; -L_0x24edcf0/d .functor OR 1, L_0x24eda90, L_0x24edba0, C4<0>, C4<0>; -L_0x24edcf0 .delay (20000,20000,20000) L_0x24edcf0/d; -v0x2434540_0 .net "S", 0 0, L_0x24edec0; 1 drivers -v0x24345c0_0 .alias "in0", 0 0, v0x2434a60_0; -v0x2434660_0 .alias "in1", 0 0, v0x2434ae0_0; -v0x2434700_0 .net "nS", 0 0, L_0x24ed9d0; 1 drivers -v0x2434780_0 .net "out0", 0 0, L_0x24eda90; 1 drivers -v0x2434820_0 .net "out1", 0 0, L_0x24edba0; 1 drivers -v0x2434900_0 .alias "outfinal", 0 0, v0x2434b90_0; -S_0x2433630 .scope generate, "andbits[14]" "andbits[14]" 2 169, 2 169, S_0x2413e60; - .timescale -9 -12; -P_0x2433728 .param/l "i" 2 169, +C4<01110>; -S_0x24337a0 .scope module, "attempt" "AndNand" 2 171, 2 48, S_0x2433630; - .timescale -9 -12; -L_0x24ee1e0/d .functor NAND 1, L_0x24ee0a0, L_0x24ee140, C4<1>, C4<1>; -L_0x24ee1e0 .delay (10000,10000,10000) L_0x24ee1e0/d; -L_0x24ee320/d .functor NOT 1, L_0x24ee1e0, C4<0>, C4<0>, C4<0>; -L_0x24ee320 .delay (10000,10000,10000) L_0x24ee320/d; -v0x2433de0_0 .net "A", 0 0, L_0x24ee0a0; 1 drivers -v0x2433ea0_0 .net "AandB", 0 0, L_0x24ee320; 1 drivers -v0x2433f20_0 .net "AnandB", 0 0, L_0x24ee1e0; 1 drivers -v0x2433fd0_0 .net "AndNandOut", 0 0, L_0x24ee750; 1 drivers -v0x24340b0_0 .net "B", 0 0, L_0x24ee140; 1 drivers -v0x2434130_0 .alias "Command", 2 0, v0x2463430_0; -L_0x24ee920 .part C4, 0, 1; -S_0x2433890 .scope module, "potato" "TwoInMux" 2 60, 2 8, S_0x24337a0; - .timescale -9 -12; -L_0x24ee430/d .functor NOT 1, L_0x24ee920, C4<0>, C4<0>, C4<0>; -L_0x24ee430 .delay (10000,10000,10000) L_0x24ee430/d; -L_0x24ee4f0/d .functor AND 1, L_0x24ee320, L_0x24ee430, C4<1>, C4<1>; -L_0x24ee4f0 .delay (20000,20000,20000) L_0x24ee4f0/d; -L_0x24ee600/d .functor AND 1, L_0x24ee1e0, L_0x24ee920, C4<1>, C4<1>; -L_0x24ee600 .delay (20000,20000,20000) L_0x24ee600/d; -L_0x24ee750/d .functor OR 1, L_0x24ee4f0, L_0x24ee600, C4<0>, C4<0>; -L_0x24ee750 .delay (20000,20000,20000) L_0x24ee750/d; -v0x2433980_0 .net "S", 0 0, L_0x24ee920; 1 drivers -v0x2433a00_0 .alias "in0", 0 0, v0x2433ea0_0; -v0x2433aa0_0 .alias "in1", 0 0, v0x2433f20_0; -v0x2433b40_0 .net "nS", 0 0, L_0x24ee430; 1 drivers -v0x2433bc0_0 .net "out0", 0 0, L_0x24ee4f0; 1 drivers -v0x2433c60_0 .net "out1", 0 0, L_0x24ee600; 1 drivers -v0x2433d40_0 .alias "outfinal", 0 0, v0x2433fd0_0; -S_0x2432a70 .scope generate, "andbits[15]" "andbits[15]" 2 169, 2 169, S_0x2413e60; - .timescale -9 -12; -P_0x2432b68 .param/l "i" 2 169, +C4<01111>; -S_0x2432be0 .scope module, "attempt" "AndNand" 2 171, 2 48, S_0x2432a70; - .timescale -9 -12; -L_0x24eea60/d .functor NAND 1, L_0x24ef4d0, L_0x24eec00, C4<1>, C4<1>; -L_0x24eea60 .delay (10000,10000,10000) L_0x24eea60/d; -L_0x24eedb0/d .functor NOT 1, L_0x24eea60, C4<0>, C4<0>, C4<0>; -L_0x24eedb0 .delay (10000,10000,10000) L_0x24eedb0/d; -v0x2433220_0 .net "A", 0 0, L_0x24ef4d0; 1 drivers -v0x24332e0_0 .net "AandB", 0 0, L_0x24eedb0; 1 drivers -v0x2433360_0 .net "AnandB", 0 0, L_0x24eea60; 1 drivers -v0x2433410_0 .net "AndNandOut", 0 0, L_0x24ef1c0; 1 drivers -v0x24334f0_0 .net "B", 0 0, L_0x24eec00; 1 drivers -v0x2433570_0 .alias "Command", 2 0, v0x2463430_0; -L_0x24ef390 .part C4, 0, 1; -S_0x2432cd0 .scope module, "potato" "TwoInMux" 2 60, 2 8, S_0x2432be0; - .timescale -9 -12; -L_0x24eeea0/d .functor NOT 1, L_0x24ef390, C4<0>, C4<0>, C4<0>; -L_0x24eeea0 .delay (10000,10000,10000) L_0x24eeea0/d; -L_0x24eef60/d .functor AND 1, L_0x24eedb0, L_0x24eeea0, C4<1>, C4<1>; -L_0x24eef60 .delay (20000,20000,20000) L_0x24eef60/d; -L_0x24ef070/d .functor AND 1, L_0x24eea60, L_0x24ef390, C4<1>, C4<1>; -L_0x24ef070 .delay (20000,20000,20000) L_0x24ef070/d; -L_0x24ef1c0/d .functor OR 1, L_0x24eef60, L_0x24ef070, C4<0>, C4<0>; -L_0x24ef1c0 .delay (20000,20000,20000) L_0x24ef1c0/d; -v0x2432dc0_0 .net "S", 0 0, L_0x24ef390; 1 drivers -v0x2432e40_0 .alias "in0", 0 0, v0x24332e0_0; -v0x2432ee0_0 .alias "in1", 0 0, v0x2433360_0; -v0x2432f80_0 .net "nS", 0 0, L_0x24eeea0; 1 drivers -v0x2433000_0 .net "out0", 0 0, L_0x24eef60; 1 drivers -v0x24330a0_0 .net "out1", 0 0, L_0x24ef070; 1 drivers -v0x2433180_0 .alias "outfinal", 0 0, v0x2433410_0; -S_0x2431eb0 .scope generate, "andbits[16]" "andbits[16]" 2 169, 2 169, S_0x2413e60; - .timescale -9 -12; -P_0x2431fa8 .param/l "i" 2 169, +C4<010000>; -S_0x2432020 .scope module, "attempt" "AndNand" 2 171, 2 48, S_0x2431eb0; - .timescale -9 -12; -L_0x24eecf0/d .functor NAND 1, L_0x24ef570, L_0x24ef610, C4<1>, C4<1>; -L_0x24eecf0 .delay (10000,10000,10000) L_0x24eecf0/d; -L_0x24ef7e0/d .functor NOT 1, L_0x24eecf0, C4<0>, C4<0>, C4<0>; -L_0x24ef7e0 .delay (10000,10000,10000) L_0x24ef7e0/d; -v0x2432660_0 .net "A", 0 0, L_0x24ef570; 1 drivers -v0x2432720_0 .net "AandB", 0 0, L_0x24ef7e0; 1 drivers -v0x24327a0_0 .net "AnandB", 0 0, L_0x24eecf0; 1 drivers -v0x2432850_0 .net "AndNandOut", 0 0, L_0x24efc30; 1 drivers -v0x2432930_0 .net "B", 0 0, L_0x24ef610; 1 drivers -v0x24329b0_0 .alias "Command", 2 0, v0x2463430_0; -L_0x24efe00 .part C4, 0, 1; -S_0x2432110 .scope module, "potato" "TwoInMux" 2 60, 2 8, S_0x2432020; - .timescale -9 -12; -L_0x24ef910/d .functor NOT 1, L_0x24efe00, C4<0>, C4<0>, C4<0>; -L_0x24ef910 .delay (10000,10000,10000) L_0x24ef910/d; -L_0x24ef9d0/d .functor AND 1, L_0x24ef7e0, L_0x24ef910, C4<1>, C4<1>; -L_0x24ef9d0 .delay (20000,20000,20000) L_0x24ef9d0/d; -L_0x24efae0/d .functor AND 1, L_0x24eecf0, L_0x24efe00, C4<1>, C4<1>; -L_0x24efae0 .delay (20000,20000,20000) L_0x24efae0/d; -L_0x24efc30/d .functor OR 1, L_0x24ef9d0, L_0x24efae0, C4<0>, C4<0>; -L_0x24efc30 .delay (20000,20000,20000) L_0x24efc30/d; -v0x2432200_0 .net "S", 0 0, L_0x24efe00; 1 drivers -v0x2432280_0 .alias "in0", 0 0, v0x2432720_0; -v0x2432320_0 .alias "in1", 0 0, v0x24327a0_0; -v0x24323c0_0 .net "nS", 0 0, L_0x24ef910; 1 drivers -v0x2432440_0 .net "out0", 0 0, L_0x24ef9d0; 1 drivers -v0x24324e0_0 .net "out1", 0 0, L_0x24efae0; 1 drivers -v0x24325c0_0 .alias "outfinal", 0 0, v0x2432850_0; -S_0x24312f0 .scope generate, "andbits[17]" "andbits[17]" 2 169, 2 169, S_0x2413e60; - .timescale -9 -12; -P_0x24313e8 .param/l "i" 2 169, +C4<010001>; -S_0x2431460 .scope module, "attempt" "AndNand" 2 171, 2 48, S_0x24312f0; - .timescale -9 -12; -L_0x24eff40/d .functor NAND 1, L_0x24f09c0, L_0x24f0110, C4<1>, C4<1>; -L_0x24eff40 .delay (10000,10000,10000) L_0x24eff40/d; -L_0x24f02a0/d .functor NOT 1, L_0x24eff40, C4<0>, C4<0>, C4<0>; -L_0x24f02a0 .delay (10000,10000,10000) L_0x24f02a0/d; -v0x2431aa0_0 .net "A", 0 0, L_0x24f09c0; 1 drivers -v0x2431b60_0 .net "AandB", 0 0, L_0x24f02a0; 1 drivers -v0x2431be0_0 .net "AnandB", 0 0, L_0x24eff40; 1 drivers -v0x2431c90_0 .net "AndNandOut", 0 0, L_0x24f06b0; 1 drivers -v0x2431d70_0 .net "B", 0 0, L_0x24f0110; 1 drivers -v0x2431df0_0 .alias "Command", 2 0, v0x2463430_0; -L_0x24f0880 .part C4, 0, 1; -S_0x2431550 .scope module, "potato" "TwoInMux" 2 60, 2 8, S_0x2431460; - .timescale -9 -12; -L_0x24f0390/d .functor NOT 1, L_0x24f0880, C4<0>, C4<0>, C4<0>; -L_0x24f0390 .delay (10000,10000,10000) L_0x24f0390/d; -L_0x24f0450/d .functor AND 1, L_0x24f02a0, L_0x24f0390, C4<1>, C4<1>; -L_0x24f0450 .delay (20000,20000,20000) L_0x24f0450/d; -L_0x24f0560/d .functor AND 1, L_0x24eff40, L_0x24f0880, C4<1>, C4<1>; -L_0x24f0560 .delay (20000,20000,20000) L_0x24f0560/d; -L_0x24f06b0/d .functor OR 1, L_0x24f0450, L_0x24f0560, C4<0>, C4<0>; -L_0x24f06b0 .delay (20000,20000,20000) L_0x24f06b0/d; -v0x2431640_0 .net "S", 0 0, L_0x24f0880; 1 drivers -v0x24316c0_0 .alias "in0", 0 0, v0x2431b60_0; -v0x2431760_0 .alias "in1", 0 0, v0x2431be0_0; -v0x2431800_0 .net "nS", 0 0, L_0x24f0390; 1 drivers -v0x2431880_0 .net "out0", 0 0, L_0x24f0450; 1 drivers -v0x2431920_0 .net "out1", 0 0, L_0x24f0560; 1 drivers -v0x2431a00_0 .alias "outfinal", 0 0, v0x2431c90_0; -S_0x2430730 .scope generate, "andbits[18]" "andbits[18]" 2 169, 2 169, S_0x2413e60; - .timescale -9 -12; -P_0x2430828 .param/l "i" 2 169, +C4<010010>; -S_0x24308a0 .scope module, "attempt" "AndNand" 2 171, 2 48, S_0x2430730; - .timescale -9 -12; -L_0x24f0200/d .functor NAND 1, L_0x24f0a60, L_0x24f0b00, C4<1>, C4<1>; -L_0x24f0200 .delay (10000,10000,10000) L_0x24f0200/d; -L_0x24f0ce0/d .functor NOT 1, L_0x24f0200, C4<0>, C4<0>, C4<0>; -L_0x24f0ce0 .delay (10000,10000,10000) L_0x24f0ce0/d; -v0x2430ee0_0 .net "A", 0 0, L_0x24f0a60; 1 drivers -v0x2430fa0_0 .net "AandB", 0 0, L_0x24f0ce0; 1 drivers -v0x2431020_0 .net "AnandB", 0 0, L_0x24f0200; 1 drivers -v0x24310d0_0 .net "AndNandOut", 0 0, L_0x24f1110; 1 drivers -v0x24311b0_0 .net "B", 0 0, L_0x24f0b00; 1 drivers -v0x2431230_0 .alias "Command", 2 0, v0x2463430_0; -L_0x24f12e0 .part C4, 0, 1; -S_0x2430990 .scope module, "potato" "TwoInMux" 2 60, 2 8, S_0x24308a0; - .timescale -9 -12; -L_0x24f0df0/d .functor NOT 1, L_0x24f12e0, C4<0>, C4<0>, C4<0>; -L_0x24f0df0 .delay (10000,10000,10000) L_0x24f0df0/d; -L_0x24f0eb0/d .functor AND 1, L_0x24f0ce0, L_0x24f0df0, C4<1>, C4<1>; -L_0x24f0eb0 .delay (20000,20000,20000) L_0x24f0eb0/d; -L_0x24f0fc0/d .functor AND 1, L_0x24f0200, L_0x24f12e0, C4<1>, C4<1>; -L_0x24f0fc0 .delay (20000,20000,20000) L_0x24f0fc0/d; -L_0x24f1110/d .functor OR 1, L_0x24f0eb0, L_0x24f0fc0, C4<0>, C4<0>; -L_0x24f1110 .delay (20000,20000,20000) L_0x24f1110/d; -v0x2430a80_0 .net "S", 0 0, L_0x24f12e0; 1 drivers -v0x2430b00_0 .alias "in0", 0 0, v0x2430fa0_0; -v0x2430ba0_0 .alias "in1", 0 0, v0x2431020_0; -v0x2430c40_0 .net "nS", 0 0, L_0x24f0df0; 1 drivers -v0x2430cc0_0 .net "out0", 0 0, L_0x24f0eb0; 1 drivers -v0x2430d60_0 .net "out1", 0 0, L_0x24f0fc0; 1 drivers -v0x2430e40_0 .alias "outfinal", 0 0, v0x24310d0_0; -S_0x242fb70 .scope generate, "andbits[19]" "andbits[19]" 2 169, 2 169, S_0x2413e60; - .timescale -9 -12; -P_0x242fc68 .param/l "i" 2 169, +C4<010011>; -S_0x242fce0 .scope module, "attempt" "AndNand" 2 171, 2 48, S_0x242fb70; - .timescale -9 -12; -L_0x24f15e0/d .functor NAND 1, L_0x24f1ea0, L_0x24f1420, C4<1>, C4<1>; -L_0x24f15e0 .delay (10000,10000,10000) L_0x24f15e0/d; -L_0x24f1740/d .functor NOT 1, L_0x24f15e0, C4<0>, C4<0>, C4<0>; -L_0x24f1740 .delay (10000,10000,10000) L_0x24f1740/d; -v0x2430320_0 .net "A", 0 0, L_0x24f1ea0; 1 drivers -v0x24303e0_0 .net "AandB", 0 0, L_0x24f1740; 1 drivers -v0x2430460_0 .net "AnandB", 0 0, L_0x24f15e0; 1 drivers -v0x2430510_0 .net "AndNandOut", 0 0, L_0x24f1b90; 1 drivers -v0x24305f0_0 .net "B", 0 0, L_0x24f1420; 1 drivers -v0x2430670_0 .alias "Command", 2 0, v0x2463430_0; -L_0x24f1d60 .part C4, 0, 1; -S_0x242fdd0 .scope module, "potato" "TwoInMux" 2 60, 2 8, S_0x242fce0; - .timescale -9 -12; -L_0x24f1870/d .functor NOT 1, L_0x24f1d60, C4<0>, C4<0>, C4<0>; -L_0x24f1870 .delay (10000,10000,10000) L_0x24f1870/d; -L_0x24f1930/d .functor AND 1, L_0x24f1740, L_0x24f1870, C4<1>, C4<1>; -L_0x24f1930 .delay (20000,20000,20000) L_0x24f1930/d; -L_0x24f1a40/d .functor AND 1, L_0x24f15e0, L_0x24f1d60, C4<1>, C4<1>; -L_0x24f1a40 .delay (20000,20000,20000) L_0x24f1a40/d; -L_0x24f1b90/d .functor OR 1, L_0x24f1930, L_0x24f1a40, C4<0>, C4<0>; -L_0x24f1b90 .delay (20000,20000,20000) L_0x24f1b90/d; -v0x242fec0_0 .net "S", 0 0, L_0x24f1d60; 1 drivers -v0x242ff40_0 .alias "in0", 0 0, v0x24303e0_0; -v0x242ffe0_0 .alias "in1", 0 0, v0x2430460_0; -v0x2430080_0 .net "nS", 0 0, L_0x24f1870; 1 drivers -v0x2430100_0 .net "out0", 0 0, L_0x24f1930; 1 drivers -v0x24301a0_0 .net "out1", 0 0, L_0x24f1a40; 1 drivers -v0x2430280_0 .alias "outfinal", 0 0, v0x2430510_0; -S_0x242efb0 .scope generate, "andbits[20]" "andbits[20]" 2 169, 2 169, S_0x2413e60; - .timescale -9 -12; -P_0x242f0a8 .param/l "i" 2 169, +C4<010100>; -S_0x242f120 .scope module, "attempt" "AndNand" 2 171, 2 48, S_0x242efb0; - .timescale -9 -12; -L_0x24f1510/d .functor NAND 1, L_0x24f1f40, L_0x24f1fe0, C4<1>, C4<1>; -L_0x24f1510 .delay (10000,10000,10000) L_0x24f1510/d; -L_0x24f21a0/d .functor NOT 1, L_0x24f1510, C4<0>, C4<0>, C4<0>; -L_0x24f21a0 .delay (10000,10000,10000) L_0x24f21a0/d; -v0x242f760_0 .net "A", 0 0, L_0x24f1f40; 1 drivers -v0x242f820_0 .net "AandB", 0 0, L_0x24f21a0; 1 drivers -v0x242f8a0_0 .net "AnandB", 0 0, L_0x24f1510; 1 drivers -v0x242f950_0 .net "AndNandOut", 0 0, L_0x24f25f0; 1 drivers -v0x242fa30_0 .net "B", 0 0, L_0x24f1fe0; 1 drivers -v0x242fab0_0 .alias "Command", 2 0, v0x2463430_0; -L_0x24f27c0 .part C4, 0, 1; -S_0x242f210 .scope module, "potato" "TwoInMux" 2 60, 2 8, S_0x242f120; - .timescale -9 -12; -L_0x24f22d0/d .functor NOT 1, L_0x24f27c0, C4<0>, C4<0>, C4<0>; -L_0x24f22d0 .delay (10000,10000,10000) L_0x24f22d0/d; -L_0x24f2390/d .functor AND 1, L_0x24f21a0, L_0x24f22d0, C4<1>, C4<1>; -L_0x24f2390 .delay (20000,20000,20000) L_0x24f2390/d; -L_0x24f24a0/d .functor AND 1, L_0x24f1510, L_0x24f27c0, C4<1>, C4<1>; -L_0x24f24a0 .delay (20000,20000,20000) L_0x24f24a0/d; -L_0x24f25f0/d .functor OR 1, L_0x24f2390, L_0x24f24a0, C4<0>, C4<0>; -L_0x24f25f0 .delay (20000,20000,20000) L_0x24f25f0/d; -v0x242f300_0 .net "S", 0 0, L_0x24f27c0; 1 drivers -v0x242f380_0 .alias "in0", 0 0, v0x242f820_0; -v0x242f420_0 .alias "in1", 0 0, v0x242f8a0_0; -v0x242f4c0_0 .net "nS", 0 0, L_0x24f22d0; 1 drivers -v0x242f540_0 .net "out0", 0 0, L_0x24f2390; 1 drivers -v0x242f5e0_0 .net "out1", 0 0, L_0x24f24a0; 1 drivers -v0x242f6c0_0 .alias "outfinal", 0 0, v0x242f950_0; -S_0x242e3f0 .scope generate, "andbits[21]" "andbits[21]" 2 169, 2 169, S_0x2413e60; - .timescale -9 -12; -P_0x242e4e8 .param/l "i" 2 169, +C4<010101>; -S_0x242e560 .scope module, "attempt" "AndNand" 2 171, 2 48, S_0x242e3f0; - .timescale -9 -12; -L_0x24f2af0/d .functor NAND 1, L_0x24f3370, L_0x24f2900, C4<1>, C4<1>; -L_0x24f2af0 .delay (10000,10000,10000) L_0x24f2af0/d; -L_0x24f2c30/d .functor NOT 1, L_0x24f2af0, C4<0>, C4<0>, C4<0>; -L_0x24f2c30 .delay (10000,10000,10000) L_0x24f2c30/d; -v0x242eba0_0 .net "A", 0 0, L_0x24f3370; 1 drivers -v0x242ec60_0 .net "AandB", 0 0, L_0x24f2c30; 1 drivers -v0x242ece0_0 .net "AnandB", 0 0, L_0x24f2af0; 1 drivers -v0x242ed90_0 .net "AndNandOut", 0 0, L_0x24f3060; 1 drivers -v0x242ee70_0 .net "B", 0 0, L_0x24f2900; 1 drivers -v0x242eef0_0 .alias "Command", 2 0, v0x2463430_0; -L_0x24f3230 .part C4, 0, 1; -S_0x242e650 .scope module, "potato" "TwoInMux" 2 60, 2 8, S_0x242e560; - .timescale -9 -12; -L_0x24f2d40/d .functor NOT 1, L_0x24f3230, C4<0>, C4<0>, C4<0>; -L_0x24f2d40 .delay (10000,10000,10000) L_0x24f2d40/d; -L_0x24f2e00/d .functor AND 1, L_0x24f2c30, L_0x24f2d40, C4<1>, C4<1>; -L_0x24f2e00 .delay (20000,20000,20000) L_0x24f2e00/d; -L_0x24f2f10/d .functor AND 1, L_0x24f2af0, L_0x24f3230, C4<1>, C4<1>; -L_0x24f2f10 .delay (20000,20000,20000) L_0x24f2f10/d; -L_0x24f3060/d .functor OR 1, L_0x24f2e00, L_0x24f2f10, C4<0>, C4<0>; -L_0x24f3060 .delay (20000,20000,20000) L_0x24f3060/d; -v0x242e740_0 .net "S", 0 0, L_0x24f3230; 1 drivers -v0x242e7c0_0 .alias "in0", 0 0, v0x242ec60_0; -v0x242e860_0 .alias "in1", 0 0, v0x242ece0_0; -v0x242e900_0 .net "nS", 0 0, L_0x24f2d40; 1 drivers -v0x242e980_0 .net "out0", 0 0, L_0x24f2e00; 1 drivers -v0x242ea20_0 .net "out1", 0 0, L_0x24f2f10; 1 drivers -v0x242eb00_0 .alias "outfinal", 0 0, v0x242ed90_0; -S_0x242d830 .scope generate, "andbits[22]" "andbits[22]" 2 169, 2 169, S_0x2413e60; - .timescale -9 -12; -P_0x242d928 .param/l "i" 2 169, +C4<010110>; -S_0x242d9a0 .scope module, "attempt" "AndNand" 2 171, 2 48, S_0x242d830; - .timescale -9 -12; -L_0x24f29f0/d .functor NAND 1, L_0x24f3410, L_0x24f34b0, C4<1>, C4<1>; -L_0x24f29f0 .delay (10000,10000,10000) L_0x24f29f0/d; -L_0x24f36a0/d .functor NOT 1, L_0x24f29f0, C4<0>, C4<0>, C4<0>; -L_0x24f36a0 .delay (10000,10000,10000) L_0x24f36a0/d; -v0x242dfe0_0 .net "A", 0 0, L_0x24f3410; 1 drivers -v0x242e0a0_0 .net "AandB", 0 0, L_0x24f36a0; 1 drivers -v0x242e120_0 .net "AnandB", 0 0, L_0x24f29f0; 1 drivers -v0x242e1d0_0 .net "AndNandOut", 0 0, L_0x24f3ad0; 1 drivers -v0x242e2b0_0 .net "B", 0 0, L_0x24f34b0; 1 drivers -v0x242e330_0 .alias "Command", 2 0, v0x2463430_0; -L_0x24f3ca0 .part C4, 0, 1; -S_0x242da90 .scope module, "potato" "TwoInMux" 2 60, 2 8, S_0x242d9a0; - .timescale -9 -12; -L_0x24f37b0/d .functor NOT 1, L_0x24f3ca0, C4<0>, C4<0>, C4<0>; -L_0x24f37b0 .delay (10000,10000,10000) L_0x24f37b0/d; -L_0x24f3870/d .functor AND 1, L_0x24f36a0, L_0x24f37b0, C4<1>, C4<1>; -L_0x24f3870 .delay (20000,20000,20000) L_0x24f3870/d; -L_0x24f3980/d .functor AND 1, L_0x24f29f0, L_0x24f3ca0, C4<1>, C4<1>; -L_0x24f3980 .delay (20000,20000,20000) L_0x24f3980/d; -L_0x24f3ad0/d .functor OR 1, L_0x24f3870, L_0x24f3980, C4<0>, C4<0>; -L_0x24f3ad0 .delay (20000,20000,20000) L_0x24f3ad0/d; -v0x242db80_0 .net "S", 0 0, L_0x24f3ca0; 1 drivers -v0x242dc00_0 .alias "in0", 0 0, v0x242e0a0_0; -v0x242dca0_0 .alias "in1", 0 0, v0x242e120_0; -v0x242dd40_0 .net "nS", 0 0, L_0x24f37b0; 1 drivers -v0x242ddc0_0 .net "out0", 0 0, L_0x24f3870; 1 drivers -v0x242de60_0 .net "out1", 0 0, L_0x24f3980; 1 drivers -v0x242df40_0 .alias "outfinal", 0 0, v0x242e1d0_0; -S_0x242cc70 .scope generate, "andbits[23]" "andbits[23]" 2 169, 2 169, S_0x2413e60; - .timescale -9 -12; -P_0x242cd68 .param/l "i" 2 169, +C4<010111>; -S_0x242cde0 .scope module, "attempt" "AndNand" 2 171, 2 48, S_0x242cc70; - .timescale -9 -12; -L_0x24f35a0/d .functor NAND 1, L_0x24f4860, L_0x24f3de0, C4<1>, C4<1>; -L_0x24f35a0 .delay (10000,10000,10000) L_0x24f35a0/d; -L_0x24f4100/d .functor NOT 1, L_0x24f35a0, C4<0>, C4<0>, C4<0>; -L_0x24f4100 .delay (10000,10000,10000) L_0x24f4100/d; -v0x242d420_0 .net "A", 0 0, L_0x24f4860; 1 drivers -v0x242d4e0_0 .net "AandB", 0 0, L_0x24f4100; 1 drivers -v0x242d560_0 .net "AnandB", 0 0, L_0x24f35a0; 1 drivers -v0x242d610_0 .net "AndNandOut", 0 0, L_0x24f4550; 1 drivers -v0x242d6f0_0 .net "B", 0 0, L_0x24f3de0; 1 drivers -v0x242d770_0 .alias "Command", 2 0, v0x2463430_0; -L_0x24f4720 .part C4, 0, 1; -S_0x242ced0 .scope module, "potato" "TwoInMux" 2 60, 2 8, S_0x242cde0; - .timescale -9 -12; -L_0x24f4230/d .functor NOT 1, L_0x24f4720, C4<0>, C4<0>, C4<0>; -L_0x24f4230 .delay (10000,10000,10000) L_0x24f4230/d; -L_0x24f42f0/d .functor AND 1, L_0x24f4100, L_0x24f4230, C4<1>, C4<1>; -L_0x24f42f0 .delay (20000,20000,20000) L_0x24f42f0/d; -L_0x24f4400/d .functor AND 1, L_0x24f35a0, L_0x24f4720, C4<1>, C4<1>; -L_0x24f4400 .delay (20000,20000,20000) L_0x24f4400/d; -L_0x24f4550/d .functor OR 1, L_0x24f42f0, L_0x24f4400, C4<0>, C4<0>; -L_0x24f4550 .delay (20000,20000,20000) L_0x24f4550/d; -v0x242cfc0_0 .net "S", 0 0, L_0x24f4720; 1 drivers -v0x242d040_0 .alias "in0", 0 0, v0x242d4e0_0; -v0x242d0e0_0 .alias "in1", 0 0, v0x242d560_0; -v0x242d180_0 .net "nS", 0 0, L_0x24f4230; 1 drivers -v0x242d200_0 .net "out0", 0 0, L_0x24f42f0; 1 drivers -v0x242d2a0_0 .net "out1", 0 0, L_0x24f4400; 1 drivers -v0x242d380_0 .alias "outfinal", 0 0, v0x242d610_0; -S_0x242c0b0 .scope generate, "andbits[24]" "andbits[24]" 2 169, 2 169, S_0x2413e60; - .timescale -9 -12; -P_0x242c1a8 .param/l "i" 2 169, +C4<011000>; -S_0x242c220 .scope module, "attempt" "AndNand" 2 171, 2 48, S_0x242c0b0; - .timescale -9 -12; -L_0x24f3ed0/d .functor NAND 1, L_0x24f4900, L_0x24f49a0, C4<1>, C4<1>; -L_0x24f3ed0 .delay (10000,10000,10000) L_0x24f3ed0/d; -L_0x24f4b80/d .functor NOT 1, L_0x24f3ed0, C4<0>, C4<0>, C4<0>; -L_0x24f4b80 .delay (10000,10000,10000) L_0x24f4b80/d; -v0x242c860_0 .net "A", 0 0, L_0x24f4900; 1 drivers -v0x242c920_0 .net "AandB", 0 0, L_0x24f4b80; 1 drivers -v0x242c9a0_0 .net "AnandB", 0 0, L_0x24f3ed0; 1 drivers -v0x242ca50_0 .net "AndNandOut", 0 0, L_0x24f4fb0; 1 drivers -v0x242cb30_0 .net "B", 0 0, L_0x24f49a0; 1 drivers -v0x242cbb0_0 .alias "Command", 2 0, v0x2463430_0; -L_0x24f5180 .part C4, 0, 1; -S_0x242c310 .scope module, "potato" "TwoInMux" 2 60, 2 8, S_0x242c220; - .timescale -9 -12; -L_0x24f4c90/d .functor NOT 1, L_0x24f5180, C4<0>, C4<0>, C4<0>; -L_0x24f4c90 .delay (10000,10000,10000) L_0x24f4c90/d; -L_0x24f4d50/d .functor AND 1, L_0x24f4b80, L_0x24f4c90, C4<1>, C4<1>; -L_0x24f4d50 .delay (20000,20000,20000) L_0x24f4d50/d; -L_0x24f4e60/d .functor AND 1, L_0x24f3ed0, L_0x24f5180, C4<1>, C4<1>; -L_0x24f4e60 .delay (20000,20000,20000) L_0x24f4e60/d; -L_0x24f4fb0/d .functor OR 1, L_0x24f4d50, L_0x24f4e60, C4<0>, C4<0>; -L_0x24f4fb0 .delay (20000,20000,20000) L_0x24f4fb0/d; -v0x242c400_0 .net "S", 0 0, L_0x24f5180; 1 drivers -v0x242c480_0 .alias "in0", 0 0, v0x242c920_0; -v0x242c520_0 .alias "in1", 0 0, v0x242c9a0_0; -v0x242c5c0_0 .net "nS", 0 0, L_0x24f4c90; 1 drivers -v0x242c640_0 .net "out0", 0 0, L_0x24f4d50; 1 drivers -v0x242c6e0_0 .net "out1", 0 0, L_0x24f4e60; 1 drivers -v0x242c7c0_0 .alias "outfinal", 0 0, v0x242ca50_0; -S_0x242b4f0 .scope generate, "andbits[25]" "andbits[25]" 2 169, 2 169, S_0x2413e60; - .timescale -9 -12; -P_0x242b5e8 .param/l "i" 2 169, +C4<011001>; -S_0x242b660 .scope module, "attempt" "AndNand" 2 171, 2 48, S_0x242b4f0; - .timescale -9 -12; -L_0x24f4a90/d .functor NAND 1, L_0x24f5d30, L_0x24f52c0, C4<1>, C4<1>; -L_0x24f4a90 .delay (10000,10000,10000) L_0x24f4a90/d; -L_0x24f55f0/d .functor NOT 1, L_0x24f4a90, C4<0>, C4<0>, C4<0>; -L_0x24f55f0 .delay (10000,10000,10000) L_0x24f55f0/d; -v0x242bca0_0 .net "A", 0 0, L_0x24f5d30; 1 drivers -v0x242bd60_0 .net "AandB", 0 0, L_0x24f55f0; 1 drivers -v0x242bde0_0 .net "AnandB", 0 0, L_0x24f4a90; 1 drivers -v0x242be90_0 .net "AndNandOut", 0 0, L_0x24f5a20; 1 drivers -v0x242bf70_0 .net "B", 0 0, L_0x24f52c0; 1 drivers -v0x242bff0_0 .alias "Command", 2 0, v0x2463430_0; -L_0x24f5bf0 .part C4, 0, 1; -S_0x242b750 .scope module, "potato" "TwoInMux" 2 60, 2 8, S_0x242b660; - .timescale -9 -12; -L_0x24f5700/d .functor NOT 1, L_0x24f5bf0, C4<0>, C4<0>, C4<0>; -L_0x24f5700 .delay (10000,10000,10000) L_0x24f5700/d; -L_0x24f57c0/d .functor AND 1, L_0x24f55f0, L_0x24f5700, C4<1>, C4<1>; -L_0x24f57c0 .delay (20000,20000,20000) L_0x24f57c0/d; -L_0x24f58d0/d .functor AND 1, L_0x24f4a90, L_0x24f5bf0, C4<1>, C4<1>; -L_0x24f58d0 .delay (20000,20000,20000) L_0x24f58d0/d; -L_0x24f5a20/d .functor OR 1, L_0x24f57c0, L_0x24f58d0, C4<0>, C4<0>; -L_0x24f5a20 .delay (20000,20000,20000) L_0x24f5a20/d; -v0x242b840_0 .net "S", 0 0, L_0x24f5bf0; 1 drivers -v0x242b8c0_0 .alias "in0", 0 0, v0x242bd60_0; -v0x242b960_0 .alias "in1", 0 0, v0x242bde0_0; -v0x242ba00_0 .net "nS", 0 0, L_0x24f5700; 1 drivers -v0x242ba80_0 .net "out0", 0 0, L_0x24f57c0; 1 drivers -v0x242bb20_0 .net "out1", 0 0, L_0x24f58d0; 1 drivers -v0x242bc00_0 .alias "outfinal", 0 0, v0x242be90_0; -S_0x242a930 .scope generate, "andbits[26]" "andbits[26]" 2 169, 2 169, S_0x2413e60; - .timescale -9 -12; -P_0x242aa28 .param/l "i" 2 169, +C4<011010>; -S_0x242aaa0 .scope module, "attempt" "AndNand" 2 171, 2 48, S_0x242a930; - .timescale -9 -12; -L_0x24f53b0/d .functor NAND 1, L_0x24f5dd0, L_0x24f5e70, C4<1>, C4<1>; -L_0x24f53b0 .delay (10000,10000,10000) L_0x24f53b0/d; -L_0x24f6030/d .functor NOT 1, L_0x24f53b0, C4<0>, C4<0>, C4<0>; -L_0x24f6030 .delay (10000,10000,10000) L_0x24f6030/d; -v0x242b0e0_0 .net "A", 0 0, L_0x24f5dd0; 1 drivers -v0x242b1a0_0 .net "AandB", 0 0, L_0x24f6030; 1 drivers -v0x242b220_0 .net "AnandB", 0 0, L_0x24f53b0; 1 drivers -v0x242b2d0_0 .net "AndNandOut", 0 0, L_0x24f6480; 1 drivers -v0x242b3b0_0 .net "B", 0 0, L_0x24f5e70; 1 drivers -v0x242b430_0 .alias "Command", 2 0, v0x2463430_0; -L_0x24f6650 .part C4, 0, 1; -S_0x242ab90 .scope module, "potato" "TwoInMux" 2 60, 2 8, S_0x242aaa0; - .timescale -9 -12; -L_0x24f6160/d .functor NOT 1, L_0x24f6650, C4<0>, C4<0>, C4<0>; -L_0x24f6160 .delay (10000,10000,10000) L_0x24f6160/d; -L_0x24f6220/d .functor AND 1, L_0x24f6030, L_0x24f6160, C4<1>, C4<1>; -L_0x24f6220 .delay (20000,20000,20000) L_0x24f6220/d; -L_0x24f6330/d .functor AND 1, L_0x24f53b0, L_0x24f6650, C4<1>, C4<1>; -L_0x24f6330 .delay (20000,20000,20000) L_0x24f6330/d; -L_0x24f6480/d .functor OR 1, L_0x24f6220, L_0x24f6330, C4<0>, C4<0>; -L_0x24f6480 .delay (20000,20000,20000) L_0x24f6480/d; -v0x242ac80_0 .net "S", 0 0, L_0x24f6650; 1 drivers -v0x242ad00_0 .alias "in0", 0 0, v0x242b1a0_0; -v0x242ada0_0 .alias "in1", 0 0, v0x242b220_0; -v0x242ae40_0 .net "nS", 0 0, L_0x24f6160; 1 drivers -v0x242aec0_0 .net "out0", 0 0, L_0x24f6220; 1 drivers -v0x242af60_0 .net "out1", 0 0, L_0x24f6330; 1 drivers -v0x242b040_0 .alias "outfinal", 0 0, v0x242b2d0_0; -S_0x2429d70 .scope generate, "andbits[27]" "andbits[27]" 2 169, 2 169, S_0x2413e60; - .timescale -9 -12; -P_0x2429e68 .param/l "i" 2 169, +C4<011011>; -S_0x2429ee0 .scope module, "attempt" "AndNand" 2 171, 2 48, S_0x2429d70; - .timescale -9 -12; -L_0x24f5f60/d .functor NAND 1, L_0x24f7200, L_0x24f6790, C4<1>, C4<1>; -L_0x24f5f60 .delay (10000,10000,10000) L_0x24f5f60/d; -L_0x24f6aa0/d .functor NOT 1, L_0x24f5f60, C4<0>, C4<0>, C4<0>; -L_0x24f6aa0 .delay (10000,10000,10000) L_0x24f6aa0/d; -v0x242a520_0 .net "A", 0 0, L_0x24f7200; 1 drivers -v0x242a5e0_0 .net "AandB", 0 0, L_0x24f6aa0; 1 drivers -v0x242a660_0 .net "AnandB", 0 0, L_0x24f5f60; 1 drivers -v0x242a710_0 .net "AndNandOut", 0 0, L_0x24f6ef0; 1 drivers -v0x242a7f0_0 .net "B", 0 0, L_0x24f6790; 1 drivers -v0x242a870_0 .alias "Command", 2 0, v0x2463430_0; -L_0x24f70c0 .part C4, 0, 1; -S_0x2429fd0 .scope module, "potato" "TwoInMux" 2 60, 2 8, S_0x2429ee0; - .timescale -9 -12; -L_0x24f6bd0/d .functor NOT 1, L_0x24f70c0, C4<0>, C4<0>, C4<0>; -L_0x24f6bd0 .delay (10000,10000,10000) L_0x24f6bd0/d; -L_0x24f6c90/d .functor AND 1, L_0x24f6aa0, L_0x24f6bd0, C4<1>, C4<1>; -L_0x24f6c90 .delay (20000,20000,20000) L_0x24f6c90/d; -L_0x24f6da0/d .functor AND 1, L_0x24f5f60, L_0x24f70c0, C4<1>, C4<1>; -L_0x24f6da0 .delay (20000,20000,20000) L_0x24f6da0/d; -L_0x24f6ef0/d .functor OR 1, L_0x24f6c90, L_0x24f6da0, C4<0>, C4<0>; -L_0x24f6ef0 .delay (20000,20000,20000) L_0x24f6ef0/d; -v0x242a0c0_0 .net "S", 0 0, L_0x24f70c0; 1 drivers -v0x242a140_0 .alias "in0", 0 0, v0x242a5e0_0; -v0x242a1e0_0 .alias "in1", 0 0, v0x242a660_0; -v0x242a280_0 .net "nS", 0 0, L_0x24f6bd0; 1 drivers -v0x242a300_0 .net "out0", 0 0, L_0x24f6c90; 1 drivers -v0x242a3a0_0 .net "out1", 0 0, L_0x24f6da0; 1 drivers -v0x242a480_0 .alias "outfinal", 0 0, v0x242a710_0; -S_0x24291b0 .scope generate, "andbits[28]" "andbits[28]" 2 169, 2 169, S_0x2413e60; - .timescale -9 -12; -P_0x24292a8 .param/l "i" 2 169, +C4<011100>; -S_0x2429320 .scope module, "attempt" "AndNand" 2 171, 2 48, S_0x24291b0; - .timescale -9 -12; -L_0x24f6880/d .functor NAND 1, L_0x24f72a0, L_0x24f7340, C4<1>, C4<1>; -L_0x24f6880 .delay (10000,10000,10000) L_0x24f6880/d; -L_0x24f7530/d .functor NOT 1, L_0x24f6880, C4<0>, C4<0>, C4<0>; -L_0x24f7530 .delay (10000,10000,10000) L_0x24f7530/d; -v0x2429960_0 .net "A", 0 0, L_0x24f72a0; 1 drivers -v0x2429a20_0 .net "AandB", 0 0, L_0x24f7530; 1 drivers -v0x2429aa0_0 .net "AnandB", 0 0, L_0x24f6880; 1 drivers -v0x2429b50_0 .net "AndNandOut", 0 0, L_0x24f7960; 1 drivers -v0x2429c30_0 .net "B", 0 0, L_0x24f7340; 1 drivers -v0x2429cb0_0 .alias "Command", 2 0, v0x2463430_0; -L_0x24f7b30 .part C4, 0, 1; -S_0x2429410 .scope module, "potato" "TwoInMux" 2 60, 2 8, S_0x2429320; - .timescale -9 -12; -L_0x24f7640/d .functor NOT 1, L_0x24f7b30, C4<0>, C4<0>, C4<0>; -L_0x24f7640 .delay (10000,10000,10000) L_0x24f7640/d; -L_0x24f7700/d .functor AND 1, L_0x24f7530, L_0x24f7640, C4<1>, C4<1>; -L_0x24f7700 .delay (20000,20000,20000) L_0x24f7700/d; -L_0x24f7810/d .functor AND 1, L_0x24f6880, L_0x24f7b30, C4<1>, C4<1>; -L_0x24f7810 .delay (20000,20000,20000) L_0x24f7810/d; -L_0x24f7960/d .functor OR 1, L_0x24f7700, L_0x24f7810, C4<0>, C4<0>; -L_0x24f7960 .delay (20000,20000,20000) L_0x24f7960/d; -v0x2429500_0 .net "S", 0 0, L_0x24f7b30; 1 drivers -v0x2429580_0 .alias "in0", 0 0, v0x2429a20_0; -v0x2429620_0 .alias "in1", 0 0, v0x2429aa0_0; -v0x24296c0_0 .net "nS", 0 0, L_0x24f7640; 1 drivers -v0x2429740_0 .net "out0", 0 0, L_0x24f7700; 1 drivers -v0x24297e0_0 .net "out1", 0 0, L_0x24f7810; 1 drivers -v0x24298c0_0 .alias "outfinal", 0 0, v0x2429b50_0; -S_0x24285f0 .scope generate, "andbits[29]" "andbits[29]" 2 169, 2 169, S_0x2413e60; - .timescale -9 -12; -P_0x24286e8 .param/l "i" 2 169, +C4<011101>; -S_0x2428760 .scope module, "attempt" "AndNand" 2 171, 2 48, S_0x24285f0; - .timescale -9 -12; -L_0x24f7430/d .functor NAND 1, L_0x24f86f0, L_0x24df8f0, C4<1>, C4<1>; -L_0x24f7430 .delay (10000,10000,10000) L_0x24f7430/d; -L_0x24f7fb0/d .functor NOT 1, L_0x24f7430, C4<0>, C4<0>, C4<0>; -L_0x24f7fb0 .delay (10000,10000,10000) L_0x24f7fb0/d; -v0x2428da0_0 .net "A", 0 0, L_0x24f86f0; 1 drivers -v0x2428e60_0 .net "AandB", 0 0, L_0x24f7fb0; 1 drivers -v0x2428ee0_0 .net "AnandB", 0 0, L_0x24f7430; 1 drivers -v0x2428f90_0 .net "AndNandOut", 0 0, L_0x24f83e0; 1 drivers -v0x2429070_0 .net "B", 0 0, L_0x24df8f0; 1 drivers -v0x24290f0_0 .alias "Command", 2 0, v0x2463430_0; -L_0x24f85b0 .part C4, 0, 1; -S_0x2428850 .scope module, "potato" "TwoInMux" 2 60, 2 8, S_0x2428760; - .timescale -9 -12; -L_0x24f80c0/d .functor NOT 1, L_0x24f85b0, C4<0>, C4<0>, C4<0>; -L_0x24f80c0 .delay (10000,10000,10000) L_0x24f80c0/d; -L_0x24f8180/d .functor AND 1, L_0x24f7fb0, L_0x24f80c0, C4<1>, C4<1>; -L_0x24f8180 .delay (20000,20000,20000) L_0x24f8180/d; -L_0x24f8290/d .functor AND 1, L_0x24f7430, L_0x24f85b0, C4<1>, C4<1>; -L_0x24f8290 .delay (20000,20000,20000) L_0x24f8290/d; -L_0x24f83e0/d .functor OR 1, L_0x24f8180, L_0x24f8290, C4<0>, C4<0>; -L_0x24f83e0 .delay (20000,20000,20000) L_0x24f83e0/d; -v0x2428940_0 .net "S", 0 0, L_0x24f85b0; 1 drivers -v0x24289c0_0 .alias "in0", 0 0, v0x2428e60_0; -v0x2428a60_0 .alias "in1", 0 0, v0x2428ee0_0; -v0x2428b00_0 .net "nS", 0 0, L_0x24f80c0; 1 drivers -v0x2428b80_0 .net "out0", 0 0, L_0x24f8180; 1 drivers -v0x2428c20_0 .net "out1", 0 0, L_0x24f8290; 1 drivers -v0x2428d00_0 .alias "outfinal", 0 0, v0x2428f90_0; -S_0x2427a30 .scope generate, "andbits[30]" "andbits[30]" 2 169, 2 169, S_0x2413e60; - .timescale -9 -12; -P_0x2427b28 .param/l "i" 2 169, +C4<011110>; -S_0x2427ba0 .scope module, "attempt" "AndNand" 2 171, 2 48, S_0x2427a30; - .timescale -9 -12; -L_0x24386d0/d .functor NAND 1, L_0x24df630, L_0x24df6d0, C4<1>, C4<1>; -L_0x24386d0 .delay (10000,10000,10000) L_0x24386d0/d; -L_0x24f7c70/d .functor NOT 1, L_0x24386d0, C4<0>, C4<0>, C4<0>; -L_0x24f7c70 .delay (10000,10000,10000) L_0x24f7c70/d; -v0x24281e0_0 .net "A", 0 0, L_0x24df630; 1 drivers -v0x24282a0_0 .net "AandB", 0 0, L_0x24f7c70; 1 drivers -v0x2428320_0 .net "AnandB", 0 0, L_0x24386d0; 1 drivers -v0x24283d0_0 .net "AndNandOut", 0 0, L_0x24df9e0; 1 drivers -v0x24284b0_0 .net "B", 0 0, L_0x24df6d0; 1 drivers -v0x2428530_0 .alias "Command", 2 0, v0x2463430_0; -L_0x24df430 .part C4, 0, 1; -S_0x2427c90 .scope module, "potato" "TwoInMux" 2 60, 2 8, S_0x2427ba0; - .timescale -9 -12; -L_0x24f7da0/d .functor NOT 1, L_0x24df430, C4<0>, C4<0>, C4<0>; -L_0x24f7da0 .delay (10000,10000,10000) L_0x24f7da0/d; -L_0x24f7e60/d .functor AND 1, L_0x24f7c70, L_0x24f7da0, C4<1>, C4<1>; -L_0x24f7e60 .delay (20000,20000,20000) L_0x24f7e60/d; -L_0x24df120/d .functor AND 1, L_0x24386d0, L_0x24df430, C4<1>, C4<1>; -L_0x24df120 .delay (20000,20000,20000) L_0x24df120/d; -L_0x24df9e0/d .functor OR 1, L_0x24f7e60, L_0x24df120, C4<0>, C4<0>; -L_0x24df9e0 .delay (20000,20000,20000) L_0x24df9e0/d; -v0x2427d80_0 .net "S", 0 0, L_0x24df430; 1 drivers -v0x2427e00_0 .alias "in0", 0 0, v0x24282a0_0; -v0x2427ea0_0 .alias "in1", 0 0, v0x2428320_0; -v0x2427f40_0 .net "nS", 0 0, L_0x24f7da0; 1 drivers -v0x2427fc0_0 .net "out0", 0 0, L_0x24f7e60; 1 drivers -v0x2428060_0 .net "out1", 0 0, L_0x24df120; 1 drivers -v0x2428140_0 .alias "outfinal", 0 0, v0x24283d0_0; -S_0x2426e50 .scope generate, "andbits[31]" "andbits[31]" 2 169, 2 169, S_0x2413e60; - .timescale -9 -12; -P_0x2418e68 .param/l "i" 2 169, +C4<011111>; -S_0x2426fc0 .scope module, "attempt" "AndNand" 2 171, 2 48, S_0x2426e50; - .timescale -9 -12; -L_0x24df7c0/d .functor NAND 1, L_0x24fa200, L_0x24f9850, C4<1>, C4<1>; -L_0x24df7c0 .delay (10000,10000,10000) L_0x24df7c0/d; -L_0x24f9b80/d .functor NOT 1, L_0x24df7c0, C4<0>, C4<0>, C4<0>; -L_0x24f9b80 .delay (10000,10000,10000) L_0x24f9b80/d; -v0x2427620_0 .net "A", 0 0, L_0x24fa200; 1 drivers -v0x24276e0_0 .net "AandB", 0 0, L_0x24f9b80; 1 drivers -v0x2427760_0 .net "AnandB", 0 0, L_0x24df7c0; 1 drivers -v0x2427810_0 .net "AndNandOut", 0 0, L_0x24f9f30; 1 drivers -v0x24278f0_0 .net "B", 0 0, L_0x24f9850; 1 drivers -v0x2427970_0 .alias "Command", 2 0, v0x2463430_0; -L_0x24fa0c0 .part C4, 0, 1; -S_0x24270b0 .scope module, "potato" "TwoInMux" 2 60, 2 8, S_0x2426fc0; - .timescale -9 -12; -L_0x24f9c70/d .functor NOT 1, L_0x24fa0c0, C4<0>, C4<0>, C4<0>; -L_0x24f9c70 .delay (10000,10000,10000) L_0x24f9c70/d; -L_0x24f9d10/d .functor AND 1, L_0x24f9b80, L_0x24f9c70, C4<1>, C4<1>; -L_0x24f9d10 .delay (20000,20000,20000) L_0x24f9d10/d; -L_0x24f9e00/d .functor AND 1, L_0x24df7c0, L_0x24fa0c0, C4<1>, C4<1>; -L_0x24f9e00 .delay (20000,20000,20000) L_0x24f9e00/d; -L_0x24f9f30/d .functor OR 1, L_0x24f9d10, L_0x24f9e00, C4<0>, C4<0>; -L_0x24f9f30 .delay (20000,20000,20000) L_0x24f9f30/d; -v0x24271a0_0 .net "S", 0 0, L_0x24fa0c0; 1 drivers -v0x2427240_0 .alias "in0", 0 0, v0x24276e0_0; -v0x24272e0_0 .alias "in1", 0 0, v0x2427760_0; -v0x2427380_0 .net "nS", 0 0, L_0x24f9c70; 1 drivers -v0x2427400_0 .net "out0", 0 0, L_0x24f9d10; 1 drivers -v0x24274a0_0 .net "out1", 0 0, L_0x24f9e00; 1 drivers -v0x2427580_0 .alias "outfinal", 0 0, v0x2427810_0; -S_0x23d9540 .scope module, "trial2" "OrNorXor32" 2 281, 2 177, S_0x22690e0; - .timescale -9 -12; -P_0x2386008 .param/l "size" 2 184, +C4<0100000>; -v0x24268c0_0 .alias "A", 31 0, v0x2462f10_0; -v0x2426940_0 .alias "B", 31 0, v0x24632b0_0; -v0x24269c0_0 .alias "Command", 2 0, v0x2463430_0; -v0x2413de0_0 .alias "OrNorXorOut", 31 0, v0x2463550_0; -L_0x24fbcf0 .part/pv L_0x24fbac0, 1, 1, 32; -L_0x24fbd90 .part C4, 1, 1; -L_0x24fbe30 .part C4, 1, 1; -L_0x24fcdf0 .part/pv L_0x24fcbc0, 2, 1, 32; -L_0x24fce90 .part C4, 2, 1; -L_0x24fcf30 .part C4, 2, 1; -L_0x24fdf50 .part/pv L_0x24fdd00, 3, 1, 32; -L_0x24fdff0 .part C4, 3, 1; -L_0x24fe090 .part C4, 3, 1; -L_0x24ff200 .part/pv L_0x24fefd0, 4, 1, 32; -L_0x24ff300 .part C4, 4, 1; -L_0x24ff3a0 .part C4, 4, 1; -L_0x25003e0 .part/pv L_0x2500170, 5, 1, 32; -L_0x2500480 .part C4, 5, 1; -L_0x25005a0 .part C4, 5, 1; -L_0x2501740 .part/pv L_0x25014d0, 6, 1, 32; -L_0x2501870 .part C4, 6, 1; -L_0x2501910 .part C4, 6, 1; -L_0x2502ad0 .part/pv L_0x2502860, 7, 1, 32; -L_0x2502b70 .part C4, 7, 1; -L_0x25019b0 .part C4, 7, 1; -L_0x2503dc0 .part/pv L_0x2503b50, 8, 1, 32; -L_0x2502c10 .part C4, 8, 1; -L_0x2503f20 .part C4, 8, 1; -L_0x25050d0 .part/pv L_0x2504e60, 9, 1, 32; -L_0x2505170 .part C4, 9, 1; -L_0x2503fc0 .part C4, 9, 1; -L_0x25063d0 .part/pv L_0x2506160, 10, 1, 32; -L_0x2505210 .part C4, 10, 1; -L_0x2506560 .part C4, 10, 1; -L_0x25076d0 .part/pv L_0x2507460, 11, 1, 32; -L_0x2507770 .part C4, 11, 1; -L_0x2506600 .part C4, 11, 1; -L_0x25089c0 .part/pv L_0x2508750, 12, 1, 32; -L_0x2507810 .part C4, 12, 1; -L_0x2508b80 .part C4, 12, 1; -L_0x2509ce0 .part/pv L_0x2509a70, 13, 1, 32; -L_0x2509d80 .part C4, 13, 1; -L_0x2508c20 .part C4, 13, 1; -L_0x250afe0 .part/pv L_0x250ad70, 14, 1, 32; -L_0x2509e20 .part C4, 14, 1; -L_0x2509ec0 .part C4, 14, 1; -L_0x250c2e0 .part/pv L_0x250c070, 15, 1, 32; -L_0x250c380 .part C4, 15, 1; -L_0x250b080 .part C4, 15, 1; -L_0x250d5d0 .part/pv L_0x250d360, 16, 1, 32; -L_0x250c420 .part C4, 16, 1; -L_0x250c4c0 .part C4, 16, 1; -L_0x250e8e0 .part/pv L_0x250e670, 17, 1, 32; -L_0x250e980 .part C4, 17, 1; -L_0x250d670 .part C4, 17, 1; -L_0x250fbd0 .part/pv L_0x250f960, 18, 1, 32; -L_0x250ea20 .part C4, 18, 1; -L_0x250eac0 .part C4, 18, 1; -L_0x2510ed0 .part/pv L_0x2510c60, 19, 1, 32; -L_0x2510f70 .part C4, 19, 1; -L_0x250fc70 .part C4, 19, 1; -L_0x25121d0 .part/pv L_0x2511f60, 20, 1, 32; -L_0x2511010 .part C4, 20, 1; -L_0x25110b0 .part C4, 20, 1; -L_0x25134e0 .part/pv L_0x2513270, 21, 1, 32; -L_0x2513580 .part C4, 21, 1; -L_0x2512270 .part C4, 21, 1; -L_0x25147d0 .part/pv L_0x2514560, 22, 1, 32; -L_0x2513620 .part C4, 22, 1; -L_0x25136c0 .part C4, 22, 1; -L_0x2515ad0 .part/pv L_0x2515860, 23, 1, 32; -L_0x2515b70 .part C4, 23, 1; -L_0x2514870 .part C4, 23, 1; -L_0x2516dd0 .part/pv L_0x2516b60, 24, 1, 32; -L_0x2515c10 .part C4, 24, 1; -L_0x2515cb0 .part C4, 24, 1; -L_0x25180d0 .part/pv L_0x2517e60, 25, 1, 32; -L_0x2518170 .part C4, 25, 1; -L_0x2516e70 .part C4, 25, 1; -L_0x25193e0 .part/pv L_0x2519170, 26, 1, 32; -L_0x2518210 .part C4, 26, 1; -L_0x25182b0 .part C4, 26, 1; -L_0x251a6e0 .part/pv L_0x251a470, 27, 1, 32; -L_0x251a780 .part C4, 27, 1; -L_0x2519480 .part C4, 27, 1; -L_0x251b9d0 .part/pv L_0x251b760, 28, 1, 32; -L_0x251a820 .part C4, 28, 1; -L_0x251a8c0 .part C4, 28, 1; -L_0x251cd50 .part/pv L_0x251cae0, 29, 1, 32; -L_0x251cdf0 .part C4, 29, 1; -L_0x251ba70 .part C4, 29, 1; -L_0x251e060 .part/pv L_0x251ddf0, 30, 1, 32; -L_0x251ce90 .part C4, 30, 1; -L_0x251cf30 .part C4, 30, 1; -L_0x251f370 .part/pv L_0x251f100, 31, 1, 32; -L_0x251f410 .part C4, 31, 1; -L_0x251e100 .part C4, 31, 1; -L_0x2520520 .part/pv L_0x25202f0, 0, 1, 32; -L_0x251f4b0 .part C4, 0, 1; -L_0x251f550 .part C4, 0, 1; -S_0x2425680 .scope module, "attempt2" "OrNorXor" 2 192, 2 64, S_0x23d9540; - .timescale -9 -12; -L_0x251e1a0/d .functor NOR 1, L_0x251f4b0, L_0x251f550, C4<0>, C4<0>; -L_0x251e1a0 .delay (10000,10000,10000) L_0x251e1a0/d; -L_0x251e290/d .functor NOT 1, L_0x251e1a0, C4<0>, C4<0>, C4<0>; -L_0x251e290 .delay (10000,10000,10000) L_0x251e290/d; -L_0x251f7a0/d .functor NAND 1, L_0x251f4b0, L_0x251f550, C4<1>, C4<1>; -L_0x251f7a0 .delay (10000,10000,10000) L_0x251f7a0/d; -L_0x251f8e0/d .functor NAND 1, L_0x251f7a0, L_0x251e290, C4<1>, C4<1>; -L_0x251f8e0 .delay (10000,10000,10000) L_0x251f8e0/d; -L_0x251f9f0/d .functor NOT 1, L_0x251f8e0, C4<0>, C4<0>, C4<0>; -L_0x251f9f0 .delay (10000,10000,10000) L_0x251f9f0/d; -v0x24261d0_0 .net "A", 0 0, L_0x251f4b0; 1 drivers -v0x2426270_0 .net "AnandB", 0 0, L_0x251f7a0; 1 drivers -v0x2426310_0 .net "AnorB", 0 0, L_0x251e1a0; 1 drivers -v0x24263c0_0 .net "AorB", 0 0, L_0x251e290; 1 drivers -v0x24264a0_0 .net "AxorB", 0 0, L_0x251f9f0; 1 drivers -v0x2426550_0 .net "B", 0 0, L_0x251f550; 1 drivers -v0x2426610_0 .alias "Command", 2 0, v0x2463430_0; -v0x2426690_0 .net "OrNorXorOut", 0 0, L_0x25202f0; 1 drivers -v0x2426710_0 .net "XorNor", 0 0, L_0x251fe70; 1 drivers -v0x24267e0_0 .net "nXor", 0 0, L_0x251f8e0; 1 drivers -L_0x251fff0 .part C4, 2, 1; -L_0x2520480 .part C4, 0, 1; -S_0x2425c60 .scope module, "mux0" "TwoInMux" 2 83, 2 8, S_0x2425680; - .timescale -9 -12; -L_0x251fb50/d .functor NOT 1, L_0x251fff0, C4<0>, C4<0>, C4<0>; -L_0x251fb50 .delay (10000,10000,10000) L_0x251fb50/d; -L_0x251fc10/d .functor AND 1, L_0x251f9f0, L_0x251fb50, C4<1>, C4<1>; -L_0x251fc10 .delay (20000,20000,20000) L_0x251fc10/d; -L_0x251fd20/d .functor AND 1, L_0x251e1a0, L_0x251fff0, C4<1>, C4<1>; -L_0x251fd20 .delay (20000,20000,20000) L_0x251fd20/d; -L_0x251fe70/d .functor OR 1, L_0x251fc10, L_0x251fd20, C4<0>, C4<0>; -L_0x251fe70 .delay (20000,20000,20000) L_0x251fe70/d; -v0x2425d50_0 .net "S", 0 0, L_0x251fff0; 1 drivers -v0x2425e10_0 .alias "in0", 0 0, v0x24264a0_0; -v0x2425eb0_0 .alias "in1", 0 0, v0x2426310_0; -v0x2425f50_0 .net "nS", 0 0, L_0x251fb50; 1 drivers -v0x2425fd0_0 .net "out0", 0 0, L_0x251fc10; 1 drivers -v0x2426070_0 .net "out1", 0 0, L_0x251fd20; 1 drivers -v0x2426150_0 .alias "outfinal", 0 0, v0x2426710_0; -S_0x2425770 .scope module, "mux1" "TwoInMux" 2 84, 2 8, S_0x2425680; - .timescale -9 -12; -L_0x24ff440/d .functor NOT 1, L_0x2520480, C4<0>, C4<0>, C4<0>; -L_0x24ff440 .delay (10000,10000,10000) L_0x24ff440/d; -L_0x2520090/d .functor AND 1, L_0x251fe70, L_0x24ff440, C4<1>, C4<1>; -L_0x2520090 .delay (20000,20000,20000) L_0x2520090/d; -L_0x25201c0/d .functor AND 1, L_0x251e290, L_0x2520480, C4<1>, C4<1>; -L_0x25201c0 .delay (20000,20000,20000) L_0x25201c0/d; -L_0x25202f0/d .functor OR 1, L_0x2520090, L_0x25201c0, C4<0>, C4<0>; -L_0x25202f0 .delay (20000,20000,20000) L_0x25202f0/d; -v0x2425860_0 .net "S", 0 0, L_0x2520480; 1 drivers -v0x24258e0_0 .alias "in0", 0 0, v0x2426710_0; -v0x2425960_0 .alias "in1", 0 0, v0x24263c0_0; -v0x2425a00_0 .net "nS", 0 0, L_0x24ff440; 1 drivers -v0x2425a80_0 .net "out0", 0 0, L_0x2520090; 1 drivers -v0x2425b20_0 .net "out1", 0 0, L_0x25201c0; 1 drivers -v0x2425bc0_0 .alias "outfinal", 0 0, v0x2426690_0; -S_0x24242b0 .scope generate, "orbits[1]" "orbits[1]" 2 196, 2 196, S_0x23d9540; - .timescale -9 -12; -P_0x2423fc8 .param/l "i" 2 196, +C4<01>; -S_0x24243e0 .scope module, "attempt" "OrNorXor" 2 198, 2 64, S_0x24242b0; - .timescale -9 -12; -L_0x24fa430/d .functor NOR 1, L_0x24fbd90, L_0x24fbe30, C4<0>, C4<0>; -L_0x24fa430 .delay (10000,10000,10000) L_0x24fa430/d; -L_0x24faec0/d .functor NOT 1, L_0x24fa430, C4<0>, C4<0>, C4<0>; -L_0x24faec0 .delay (10000,10000,10000) L_0x24faec0/d; -L_0x24fafb0/d .functor NAND 1, L_0x24fbd90, L_0x24fbe30, C4<1>, C4<1>; -L_0x24fafb0 .delay (10000,10000,10000) L_0x24fafb0/d; -L_0x24fb0f0/d .functor NAND 1, L_0x24fafb0, L_0x24faec0, C4<1>, C4<1>; -L_0x24fb0f0 .delay (10000,10000,10000) L_0x24fb0f0/d; -L_0x24fb1e0/d .functor NOT 1, L_0x24fb0f0, C4<0>, C4<0>, C4<0>; -L_0x24fb1e0 .delay (10000,10000,10000) L_0x24fb1e0/d; -v0x2424f90_0 .net "A", 0 0, L_0x24fbd90; 1 drivers -v0x2425030_0 .net "AnandB", 0 0, L_0x24fafb0; 1 drivers -v0x24250d0_0 .net "AnorB", 0 0, L_0x24fa430; 1 drivers -v0x2425180_0 .net "AorB", 0 0, L_0x24faec0; 1 drivers -v0x2425260_0 .net "AxorB", 0 0, L_0x24fb1e0; 1 drivers -v0x2425310_0 .net "B", 0 0, L_0x24fbe30; 1 drivers -v0x24253d0_0 .alias "Command", 2 0, v0x2463430_0; -v0x2425450_0 .net "OrNorXorOut", 0 0, L_0x24fbac0; 1 drivers -v0x24254d0_0 .net "XorNor", 0 0, L_0x24fb5e0; 1 drivers -v0x24255a0_0 .net "nXor", 0 0, L_0x24fb0f0; 1 drivers -L_0x24fb720 .part C4, 2, 1; -L_0x24fbc50 .part C4, 0, 1; -S_0x2424a20 .scope module, "mux0" "TwoInMux" 2 83, 2 8, S_0x24243e0; - .timescale -9 -12; -L_0x24fb320/d .functor NOT 1, L_0x24fb720, C4<0>, C4<0>, C4<0>; -L_0x24fb320 .delay (10000,10000,10000) L_0x24fb320/d; -L_0x24fb3c0/d .functor AND 1, L_0x24fb1e0, L_0x24fb320, C4<1>, C4<1>; -L_0x24fb3c0 .delay (20000,20000,20000) L_0x24fb3c0/d; -L_0x24fb4b0/d .functor AND 1, L_0x24fa430, L_0x24fb720, C4<1>, C4<1>; -L_0x24fb4b0 .delay (20000,20000,20000) L_0x24fb4b0/d; -L_0x24fb5e0/d .functor OR 1, L_0x24fb3c0, L_0x24fb4b0, C4<0>, C4<0>; -L_0x24fb5e0 .delay (20000,20000,20000) L_0x24fb5e0/d; -v0x2424b10_0 .net "S", 0 0, L_0x24fb720; 1 drivers -v0x2424bd0_0 .alias "in0", 0 0, v0x2425260_0; -v0x2424c70_0 .alias "in1", 0 0, v0x24250d0_0; -v0x2424d10_0 .net "nS", 0 0, L_0x24fb320; 1 drivers -v0x2424d90_0 .net "out0", 0 0, L_0x24fb3c0; 1 drivers -v0x2424e30_0 .net "out1", 0 0, L_0x24fb4b0; 1 drivers -v0x2424f10_0 .alias "outfinal", 0 0, v0x24254d0_0; -S_0x24244d0 .scope module, "mux1" "TwoInMux" 2 84, 2 8, S_0x24243e0; - .timescale -9 -12; -L_0x24fb7c0/d .functor NOT 1, L_0x24fbc50, C4<0>, C4<0>, C4<0>; -L_0x24fb7c0 .delay (10000,10000,10000) L_0x24fb7c0/d; -L_0x24fb860/d .functor AND 1, L_0x24fb5e0, L_0x24fb7c0, C4<1>, C4<1>; -L_0x24fb860 .delay (20000,20000,20000) L_0x24fb860/d; -L_0x24fb990/d .functor AND 1, L_0x24faec0, L_0x24fbc50, C4<1>, C4<1>; -L_0x24fb990 .delay (20000,20000,20000) L_0x24fb990/d; -L_0x24fbac0/d .functor OR 1, L_0x24fb860, L_0x24fb990, C4<0>, C4<0>; -L_0x24fbac0 .delay (20000,20000,20000) L_0x24fbac0/d; -v0x24245c0_0 .net "S", 0 0, L_0x24fbc50; 1 drivers -v0x2424640_0 .alias "in0", 0 0, v0x24254d0_0; -v0x24246e0_0 .alias "in1", 0 0, v0x2425180_0; -v0x2424780_0 .net "nS", 0 0, L_0x24fb7c0; 1 drivers -v0x2424800_0 .net "out0", 0 0, L_0x24fb860; 1 drivers -v0x24248a0_0 .net "out1", 0 0, L_0x24fb990; 1 drivers -v0x2424980_0 .alias "outfinal", 0 0, v0x2425450_0; -S_0x2422ee0 .scope generate, "orbits[2]" "orbits[2]" 2 196, 2 196, S_0x23d9540; - .timescale -9 -12; -P_0x2422bf8 .param/l "i" 2 196, +C4<010>; -S_0x2423010 .scope module, "attempt" "OrNorXor" 2 198, 2 64, S_0x2422ee0; - .timescale -9 -12; -L_0x24fbed0/d .functor NOR 1, L_0x24fce90, L_0x24fcf30, C4<0>, C4<0>; -L_0x24fbed0 .delay (10000,10000,10000) L_0x24fbed0/d; -L_0x24fbfc0/d .functor NOT 1, L_0x24fbed0, C4<0>, C4<0>, C4<0>; -L_0x24fbfc0 .delay (10000,10000,10000) L_0x24fbfc0/d; -L_0x24fc0b0/d .functor NAND 1, L_0x24fce90, L_0x24fcf30, C4<1>, C4<1>; -L_0x24fc0b0 .delay (10000,10000,10000) L_0x24fc0b0/d; -L_0x24fc1f0/d .functor NAND 1, L_0x24fc0b0, L_0x24fbfc0, C4<1>, C4<1>; -L_0x24fc1f0 .delay (10000,10000,10000) L_0x24fc1f0/d; -L_0x24fc2e0/d .functor NOT 1, L_0x24fc1f0, C4<0>, C4<0>, C4<0>; -L_0x24fc2e0 .delay (10000,10000,10000) L_0x24fc2e0/d; -v0x2423bc0_0 .net "A", 0 0, L_0x24fce90; 1 drivers -v0x2423c60_0 .net "AnandB", 0 0, L_0x24fc0b0; 1 drivers -v0x2423d00_0 .net "AnorB", 0 0, L_0x24fbed0; 1 drivers -v0x2423db0_0 .net "AorB", 0 0, L_0x24fbfc0; 1 drivers -v0x2423e90_0 .net "AxorB", 0 0, L_0x24fc2e0; 1 drivers -v0x2423f40_0 .net "B", 0 0, L_0x24fcf30; 1 drivers -v0x2424000_0 .alias "Command", 2 0, v0x2463430_0; -v0x2424080_0 .net "OrNorXorOut", 0 0, L_0x24fcbc0; 1 drivers -v0x2424100_0 .net "XorNor", 0 0, L_0x24fc6e0; 1 drivers -v0x24241d0_0 .net "nXor", 0 0, L_0x24fc1f0; 1 drivers -L_0x24fc820 .part C4, 2, 1; -L_0x24fcd50 .part C4, 0, 1; -S_0x2423650 .scope module, "mux0" "TwoInMux" 2 83, 2 8, S_0x2423010; - .timescale -9 -12; -L_0x24fc420/d .functor NOT 1, L_0x24fc820, C4<0>, C4<0>, C4<0>; -L_0x24fc420 .delay (10000,10000,10000) L_0x24fc420/d; -L_0x24fc4c0/d .functor AND 1, L_0x24fc2e0, L_0x24fc420, C4<1>, C4<1>; -L_0x24fc4c0 .delay (20000,20000,20000) L_0x24fc4c0/d; -L_0x24fc5b0/d .functor AND 1, L_0x24fbed0, L_0x24fc820, C4<1>, C4<1>; -L_0x24fc5b0 .delay (20000,20000,20000) L_0x24fc5b0/d; -L_0x24fc6e0/d .functor OR 1, L_0x24fc4c0, L_0x24fc5b0, C4<0>, C4<0>; -L_0x24fc6e0 .delay (20000,20000,20000) L_0x24fc6e0/d; -v0x2423740_0 .net "S", 0 0, L_0x24fc820; 1 drivers -v0x2423800_0 .alias "in0", 0 0, v0x2423e90_0; -v0x24238a0_0 .alias "in1", 0 0, v0x2423d00_0; -v0x2423940_0 .net "nS", 0 0, L_0x24fc420; 1 drivers -v0x24239c0_0 .net "out0", 0 0, L_0x24fc4c0; 1 drivers -v0x2423a60_0 .net "out1", 0 0, L_0x24fc5b0; 1 drivers -v0x2423b40_0 .alias "outfinal", 0 0, v0x2424100_0; -S_0x2423100 .scope module, "mux1" "TwoInMux" 2 84, 2 8, S_0x2423010; - .timescale -9 -12; -L_0x24fc8c0/d .functor NOT 1, L_0x24fcd50, C4<0>, C4<0>, C4<0>; -L_0x24fc8c0 .delay (10000,10000,10000) L_0x24fc8c0/d; -L_0x24fc960/d .functor AND 1, L_0x24fc6e0, L_0x24fc8c0, C4<1>, C4<1>; -L_0x24fc960 .delay (20000,20000,20000) L_0x24fc960/d; -L_0x24fca90/d .functor AND 1, L_0x24fbfc0, L_0x24fcd50, C4<1>, C4<1>; -L_0x24fca90 .delay (20000,20000,20000) L_0x24fca90/d; -L_0x24fcbc0/d .functor OR 1, L_0x24fc960, L_0x24fca90, C4<0>, C4<0>; -L_0x24fcbc0 .delay (20000,20000,20000) L_0x24fcbc0/d; -v0x24231f0_0 .net "S", 0 0, L_0x24fcd50; 1 drivers -v0x2423270_0 .alias "in0", 0 0, v0x2424100_0; -v0x2423310_0 .alias "in1", 0 0, v0x2423db0_0; -v0x24233b0_0 .net "nS", 0 0, L_0x24fc8c0; 1 drivers -v0x2423430_0 .net "out0", 0 0, L_0x24fc960; 1 drivers -v0x24234d0_0 .net "out1", 0 0, L_0x24fca90; 1 drivers -v0x24235b0_0 .alias "outfinal", 0 0, v0x2424080_0; -S_0x2421b10 .scope generate, "orbits[3]" "orbits[3]" 2 196, 2 196, S_0x23d9540; - .timescale -9 -12; -P_0x2421828 .param/l "i" 2 196, +C4<011>; -S_0x2421c40 .scope module, "attempt" "OrNorXor" 2 198, 2 64, S_0x2421b10; - .timescale -9 -12; -L_0x24fd010/d .functor NOR 1, L_0x24fdff0, L_0x24fe090, C4<0>, C4<0>; -L_0x24fd010 .delay (10000,10000,10000) L_0x24fd010/d; -L_0x24fd100/d .functor NOT 1, L_0x24fd010, C4<0>, C4<0>, C4<0>; -L_0x24fd100 .delay (10000,10000,10000) L_0x24fd100/d; -L_0x24fd1f0/d .functor NAND 1, L_0x24fdff0, L_0x24fe090, C4<1>, C4<1>; -L_0x24fd1f0 .delay (10000,10000,10000) L_0x24fd1f0/d; -L_0x24fd330/d .functor NAND 1, L_0x24fd1f0, L_0x24fd100, C4<1>, C4<1>; -L_0x24fd330 .delay (10000,10000,10000) L_0x24fd330/d; -L_0x24fd420/d .functor NOT 1, L_0x24fd330, C4<0>, C4<0>, C4<0>; -L_0x24fd420 .delay (10000,10000,10000) L_0x24fd420/d; -v0x24227f0_0 .net "A", 0 0, L_0x24fdff0; 1 drivers -v0x2422890_0 .net "AnandB", 0 0, L_0x24fd1f0; 1 drivers -v0x2422930_0 .net "AnorB", 0 0, L_0x24fd010; 1 drivers -v0x24229e0_0 .net "AorB", 0 0, L_0x24fd100; 1 drivers -v0x2422ac0_0 .net "AxorB", 0 0, L_0x24fd420; 1 drivers -v0x2422b70_0 .net "B", 0 0, L_0x24fe090; 1 drivers -v0x2422c30_0 .alias "Command", 2 0, v0x2463430_0; -v0x2422cb0_0 .net "OrNorXorOut", 0 0, L_0x24fdd00; 1 drivers -v0x2422d30_0 .net "XorNor", 0 0, L_0x24fd820; 1 drivers -v0x2422e00_0 .net "nXor", 0 0, L_0x24fd330; 1 drivers -L_0x24fd960 .part C4, 2, 1; -L_0x24fdeb0 .part C4, 0, 1; -S_0x2422280 .scope module, "mux0" "TwoInMux" 2 83, 2 8, S_0x2421c40; - .timescale -9 -12; -L_0x24fd560/d .functor NOT 1, L_0x24fd960, C4<0>, C4<0>, C4<0>; -L_0x24fd560 .delay (10000,10000,10000) L_0x24fd560/d; -L_0x24fd600/d .functor AND 1, L_0x24fd420, L_0x24fd560, C4<1>, C4<1>; -L_0x24fd600 .delay (20000,20000,20000) L_0x24fd600/d; -L_0x24fd6f0/d .functor AND 1, L_0x24fd010, L_0x24fd960, C4<1>, C4<1>; -L_0x24fd6f0 .delay (20000,20000,20000) L_0x24fd6f0/d; -L_0x24fd820/d .functor OR 1, L_0x24fd600, L_0x24fd6f0, C4<0>, C4<0>; -L_0x24fd820 .delay (20000,20000,20000) L_0x24fd820/d; -v0x2422370_0 .net "S", 0 0, L_0x24fd960; 1 drivers -v0x2422430_0 .alias "in0", 0 0, v0x2422ac0_0; -v0x24224d0_0 .alias "in1", 0 0, v0x2422930_0; -v0x2422570_0 .net "nS", 0 0, L_0x24fd560; 1 drivers -v0x24225f0_0 .net "out0", 0 0, L_0x24fd600; 1 drivers -v0x2422690_0 .net "out1", 0 0, L_0x24fd6f0; 1 drivers -v0x2422770_0 .alias "outfinal", 0 0, v0x2422d30_0; -S_0x2421d30 .scope module, "mux1" "TwoInMux" 2 84, 2 8, S_0x2421c40; - .timescale -9 -12; -L_0x24fda00/d .functor NOT 1, L_0x24fdeb0, C4<0>, C4<0>, C4<0>; -L_0x24fda00 .delay (10000,10000,10000) L_0x24fda00/d; -L_0x24fdaa0/d .functor AND 1, L_0x24fd820, L_0x24fda00, C4<1>, C4<1>; -L_0x24fdaa0 .delay (20000,20000,20000) L_0x24fdaa0/d; -L_0x24fdbd0/d .functor AND 1, L_0x24fd100, L_0x24fdeb0, C4<1>, C4<1>; -L_0x24fdbd0 .delay (20000,20000,20000) L_0x24fdbd0/d; -L_0x24fdd00/d .functor OR 1, L_0x24fdaa0, L_0x24fdbd0, C4<0>, C4<0>; -L_0x24fdd00 .delay (20000,20000,20000) L_0x24fdd00/d; -v0x2421e20_0 .net "S", 0 0, L_0x24fdeb0; 1 drivers -v0x2421ea0_0 .alias "in0", 0 0, v0x2422d30_0; -v0x2421f40_0 .alias "in1", 0 0, v0x24229e0_0; -v0x2421fe0_0 .net "nS", 0 0, L_0x24fda00; 1 drivers -v0x2422060_0 .net "out0", 0 0, L_0x24fdaa0; 1 drivers -v0x2422100_0 .net "out1", 0 0, L_0x24fdbd0; 1 drivers -v0x24221e0_0 .alias "outfinal", 0 0, v0x2422cb0_0; -S_0x2420740 .scope generate, "orbits[4]" "orbits[4]" 2 196, 2 196, S_0x23d9540; - .timescale -9 -12; -P_0x2420458 .param/l "i" 2 196, +C4<0100>; -S_0x2420870 .scope module, "attempt" "OrNorXor" 2 198, 2 64, S_0x2420740; - .timescale -9 -12; -L_0x24fe130/d .functor NOR 1, L_0x24ff300, L_0x24ff3a0, C4<0>, C4<0>; -L_0x24fe130 .delay (10000,10000,10000) L_0x24fe130/d; -L_0x24fe230/d .functor NOT 1, L_0x24fe130, C4<0>, C4<0>, C4<0>; -L_0x24fe230 .delay (10000,10000,10000) L_0x24fe230/d; -L_0x24fe360/d .functor NAND 1, L_0x24ff300, L_0x24ff3a0, C4<1>, C4<1>; -L_0x24fe360 .delay (10000,10000,10000) L_0x24fe360/d; -L_0x24fe4c0/d .functor NAND 1, L_0x24fe360, L_0x24fe230, C4<1>, C4<1>; -L_0x24fe4c0 .delay (10000,10000,10000) L_0x24fe4c0/d; -L_0x24fe5d0/d .functor NOT 1, L_0x24fe4c0, C4<0>, C4<0>, C4<0>; -L_0x24fe5d0 .delay (10000,10000,10000) L_0x24fe5d0/d; -v0x2421420_0 .net "A", 0 0, L_0x24ff300; 1 drivers -v0x24214c0_0 .net "AnandB", 0 0, L_0x24fe360; 1 drivers -v0x2421560_0 .net "AnorB", 0 0, L_0x24fe130; 1 drivers -v0x2421610_0 .net "AorB", 0 0, L_0x24fe230; 1 drivers -v0x24216f0_0 .net "AxorB", 0 0, L_0x24fe5d0; 1 drivers -v0x24217a0_0 .net "B", 0 0, L_0x24ff3a0; 1 drivers -v0x2421860_0 .alias "Command", 2 0, v0x2463430_0; -v0x24218e0_0 .net "OrNorXorOut", 0 0, L_0x24fefd0; 1 drivers -v0x2421960_0 .net "XorNor", 0 0, L_0x24fea50; 1 drivers -v0x2421a30_0 .net "nXor", 0 0, L_0x24fe4c0; 1 drivers -L_0x24febd0 .part C4, 2, 1; -L_0x24ff160 .part C4, 0, 1; -S_0x2420eb0 .scope module, "mux0" "TwoInMux" 2 83, 2 8, S_0x2420870; - .timescale -9 -12; -L_0x24fe730/d .functor NOT 1, L_0x24febd0, C4<0>, C4<0>, C4<0>; -L_0x24fe730 .delay (10000,10000,10000) L_0x24fe730/d; -L_0x24fe7f0/d .functor AND 1, L_0x24fe5d0, L_0x24fe730, C4<1>, C4<1>; -L_0x24fe7f0 .delay (20000,20000,20000) L_0x24fe7f0/d; -L_0x24fe900/d .functor AND 1, L_0x24fe130, L_0x24febd0, C4<1>, C4<1>; -L_0x24fe900 .delay (20000,20000,20000) L_0x24fe900/d; -L_0x24fea50/d .functor OR 1, L_0x24fe7f0, L_0x24fe900, C4<0>, C4<0>; -L_0x24fea50 .delay (20000,20000,20000) L_0x24fea50/d; -v0x2420fa0_0 .net "S", 0 0, L_0x24febd0; 1 drivers -v0x2421060_0 .alias "in0", 0 0, v0x24216f0_0; -v0x2421100_0 .alias "in1", 0 0, v0x2421560_0; -v0x24211a0_0 .net "nS", 0 0, L_0x24fe730; 1 drivers -v0x2421220_0 .net "out0", 0 0, L_0x24fe7f0; 1 drivers -v0x24212c0_0 .net "out1", 0 0, L_0x24fe900; 1 drivers -v0x24213a0_0 .alias "outfinal", 0 0, v0x2421960_0; -S_0x2420960 .scope module, "mux1" "TwoInMux" 2 84, 2 8, S_0x2420870; - .timescale -9 -12; -L_0x24fec70/d .functor NOT 1, L_0x24ff160, C4<0>, C4<0>, C4<0>; -L_0x24fec70 .delay (10000,10000,10000) L_0x24fec70/d; -L_0x24fed30/d .functor AND 1, L_0x24fea50, L_0x24fec70, C4<1>, C4<1>; -L_0x24fed30 .delay (20000,20000,20000) L_0x24fed30/d; -L_0x24fee80/d .functor AND 1, L_0x24fe230, L_0x24ff160, C4<1>, C4<1>; -L_0x24fee80 .delay (20000,20000,20000) L_0x24fee80/d; -L_0x24fefd0/d .functor OR 1, L_0x24fed30, L_0x24fee80, C4<0>, C4<0>; -L_0x24fefd0 .delay (20000,20000,20000) L_0x24fefd0/d; -v0x2420a50_0 .net "S", 0 0, L_0x24ff160; 1 drivers -v0x2420ad0_0 .alias "in0", 0 0, v0x2421960_0; -v0x2420b70_0 .alias "in1", 0 0, v0x2421610_0; -v0x2420c10_0 .net "nS", 0 0, L_0x24fec70; 1 drivers -v0x2420c90_0 .net "out0", 0 0, L_0x24fed30; 1 drivers -v0x2420d30_0 .net "out1", 0 0, L_0x24fee80; 1 drivers -v0x2420e10_0 .alias "outfinal", 0 0, v0x24218e0_0; -S_0x241f370 .scope generate, "orbits[5]" "orbits[5]" 2 196, 2 196, S_0x23d9540; - .timescale -9 -12; -P_0x241f088 .param/l "i" 2 196, +C4<0101>; -S_0x241f4a0 .scope module, "attempt" "OrNorXor" 2 198, 2 64, S_0x241f370; - .timescale -9 -12; -L_0x24ff2a0/d .functor NOR 1, L_0x2500480, L_0x25005a0, C4<0>, C4<0>; -L_0x24ff2a0 .delay (10000,10000,10000) L_0x24ff2a0/d; -L_0x24ff4f0/d .functor NOT 1, L_0x24ff2a0, C4<0>, C4<0>, C4<0>; -L_0x24ff4f0 .delay (10000,10000,10000) L_0x24ff4f0/d; -L_0x24ff5e0/d .functor NAND 1, L_0x2500480, L_0x25005a0, C4<1>, C4<1>; -L_0x24ff5e0 .delay (10000,10000,10000) L_0x24ff5e0/d; -L_0x24ff720/d .functor NAND 1, L_0x24ff5e0, L_0x24ff4f0, C4<1>, C4<1>; -L_0x24ff720 .delay (10000,10000,10000) L_0x24ff720/d; -L_0x24ff810/d .functor NOT 1, L_0x24ff720, C4<0>, C4<0>, C4<0>; -L_0x24ff810 .delay (10000,10000,10000) L_0x24ff810/d; -v0x2420050_0 .net "A", 0 0, L_0x2500480; 1 drivers -v0x24200f0_0 .net "AnandB", 0 0, L_0x24ff5e0; 1 drivers -v0x2420190_0 .net "AnorB", 0 0, L_0x24ff2a0; 1 drivers -v0x2420240_0 .net "AorB", 0 0, L_0x24ff4f0; 1 drivers -v0x2420320_0 .net "AxorB", 0 0, L_0x24ff810; 1 drivers -v0x24203d0_0 .net "B", 0 0, L_0x25005a0; 1 drivers -v0x2420490_0 .alias "Command", 2 0, v0x2463430_0; -v0x2420510_0 .net "OrNorXorOut", 0 0, L_0x2500170; 1 drivers -v0x2420590_0 .net "XorNor", 0 0, L_0x24ffc10; 1 drivers -v0x2420660_0 .net "nXor", 0 0, L_0x24ff720; 1 drivers -L_0x24ffd70 .part C4, 2, 1; -L_0x2500340 .part C4, 0, 1; -S_0x241fae0 .scope module, "mux0" "TwoInMux" 2 83, 2 8, S_0x241f4a0; - .timescale -9 -12; -L_0x24ff950/d .functor NOT 1, L_0x24ffd70, C4<0>, C4<0>, C4<0>; -L_0x24ff950 .delay (10000,10000,10000) L_0x24ff950/d; -L_0x24ff9f0/d .functor AND 1, L_0x24ff810, L_0x24ff950, C4<1>, C4<1>; -L_0x24ff9f0 .delay (20000,20000,20000) L_0x24ff9f0/d; -L_0x24ffae0/d .functor AND 1, L_0x24ff2a0, L_0x24ffd70, C4<1>, C4<1>; -L_0x24ffae0 .delay (20000,20000,20000) L_0x24ffae0/d; -L_0x24ffc10/d .functor OR 1, L_0x24ff9f0, L_0x24ffae0, C4<0>, C4<0>; -L_0x24ffc10 .delay (20000,20000,20000) L_0x24ffc10/d; -v0x241fbd0_0 .net "S", 0 0, L_0x24ffd70; 1 drivers -v0x241fc90_0 .alias "in0", 0 0, v0x2420320_0; -v0x241fd30_0 .alias "in1", 0 0, v0x2420190_0; -v0x241fdd0_0 .net "nS", 0 0, L_0x24ff950; 1 drivers -v0x241fe50_0 .net "out0", 0 0, L_0x24ff9f0; 1 drivers -v0x241fef0_0 .net "out1", 0 0, L_0x24ffae0; 1 drivers -v0x241ffd0_0 .alias "outfinal", 0 0, v0x2420590_0; -S_0x241f590 .scope module, "mux1" "TwoInMux" 2 84, 2 8, S_0x241f4a0; - .timescale -9 -12; -L_0x24ffe10/d .functor NOT 1, L_0x2500340, C4<0>, C4<0>, C4<0>; -L_0x24ffe10 .delay (10000,10000,10000) L_0x24ffe10/d; -L_0x24ffed0/d .functor AND 1, L_0x24ffc10, L_0x24ffe10, C4<1>, C4<1>; -L_0x24ffed0 .delay (20000,20000,20000) L_0x24ffed0/d; -L_0x2500020/d .functor AND 1, L_0x24ff4f0, L_0x2500340, C4<1>, C4<1>; -L_0x2500020 .delay (20000,20000,20000) L_0x2500020/d; -L_0x2500170/d .functor OR 1, L_0x24ffed0, L_0x2500020, C4<0>, C4<0>; -L_0x2500170 .delay (20000,20000,20000) L_0x2500170/d; -v0x241f680_0 .net "S", 0 0, L_0x2500340; 1 drivers -v0x241f700_0 .alias "in0", 0 0, v0x2420590_0; -v0x241f7a0_0 .alias "in1", 0 0, v0x2420240_0; -v0x241f840_0 .net "nS", 0 0, L_0x24ffe10; 1 drivers -v0x241f8c0_0 .net "out0", 0 0, L_0x24ffed0; 1 drivers -v0x241f960_0 .net "out1", 0 0, L_0x2500020; 1 drivers -v0x241fa40_0 .alias "outfinal", 0 0, v0x2420510_0; -S_0x241dfa0 .scope generate, "orbits[6]" "orbits[6]" 2 196, 2 196, S_0x23d9540; - .timescale -9 -12; -P_0x241dcb8 .param/l "i" 2 196, +C4<0110>; -S_0x241e0d0 .scope module, "attempt" "OrNorXor" 2 198, 2 64, S_0x241dfa0; - .timescale -9 -12; -L_0x2500640/d .functor NOR 1, L_0x2501870, L_0x2501910, C4<0>, C4<0>; -L_0x2500640 .delay (10000,10000,10000) L_0x2500640/d; -L_0x2500730/d .functor NOT 1, L_0x2500640, C4<0>, C4<0>, C4<0>; -L_0x2500730 .delay (10000,10000,10000) L_0x2500730/d; -L_0x2500860/d .functor NAND 1, L_0x2501870, L_0x2501910, C4<1>, C4<1>; -L_0x2500860 .delay (10000,10000,10000) L_0x2500860/d; -L_0x25009c0/d .functor NAND 1, L_0x2500860, L_0x2500730, C4<1>, C4<1>; -L_0x25009c0 .delay (10000,10000,10000) L_0x25009c0/d; -L_0x2500ad0/d .functor NOT 1, L_0x25009c0, C4<0>, C4<0>, C4<0>; -L_0x2500ad0 .delay (10000,10000,10000) L_0x2500ad0/d; -v0x241ec80_0 .net "A", 0 0, L_0x2501870; 1 drivers -v0x241ed20_0 .net "AnandB", 0 0, L_0x2500860; 1 drivers -v0x241edc0_0 .net "AnorB", 0 0, L_0x2500640; 1 drivers -v0x241ee70_0 .net "AorB", 0 0, L_0x2500730; 1 drivers -v0x241ef50_0 .net "AxorB", 0 0, L_0x2500ad0; 1 drivers -v0x241f000_0 .net "B", 0 0, L_0x2501910; 1 drivers -v0x241f0c0_0 .alias "Command", 2 0, v0x2463430_0; -v0x241f140_0 .net "OrNorXorOut", 0 0, L_0x25014d0; 1 drivers -v0x241f1c0_0 .net "XorNor", 0 0, L_0x2500f50; 1 drivers -v0x241f290_0 .net "nXor", 0 0, L_0x25009c0; 1 drivers -L_0x25010d0 .part C4, 2, 1; -L_0x25016a0 .part C4, 0, 1; -S_0x241e710 .scope module, "mux0" "TwoInMux" 2 83, 2 8, S_0x241e0d0; - .timescale -9 -12; -L_0x2500c30/d .functor NOT 1, L_0x25010d0, C4<0>, C4<0>, C4<0>; -L_0x2500c30 .delay (10000,10000,10000) L_0x2500c30/d; -L_0x2500cf0/d .functor AND 1, L_0x2500ad0, L_0x2500c30, C4<1>, C4<1>; -L_0x2500cf0 .delay (20000,20000,20000) L_0x2500cf0/d; -L_0x2500e00/d .functor AND 1, L_0x2500640, L_0x25010d0, C4<1>, C4<1>; -L_0x2500e00 .delay (20000,20000,20000) L_0x2500e00/d; -L_0x2500f50/d .functor OR 1, L_0x2500cf0, L_0x2500e00, C4<0>, C4<0>; -L_0x2500f50 .delay (20000,20000,20000) L_0x2500f50/d; -v0x241e800_0 .net "S", 0 0, L_0x25010d0; 1 drivers -v0x241e8c0_0 .alias "in0", 0 0, v0x241ef50_0; -v0x241e960_0 .alias "in1", 0 0, v0x241edc0_0; -v0x241ea00_0 .net "nS", 0 0, L_0x2500c30; 1 drivers -v0x241ea80_0 .net "out0", 0 0, L_0x2500cf0; 1 drivers -v0x241eb20_0 .net "out1", 0 0, L_0x2500e00; 1 drivers -v0x241ec00_0 .alias "outfinal", 0 0, v0x241f1c0_0; -S_0x241e1c0 .scope module, "mux1" "TwoInMux" 2 84, 2 8, S_0x241e0d0; - .timescale -9 -12; -L_0x2501170/d .functor NOT 1, L_0x25016a0, C4<0>, C4<0>, C4<0>; -L_0x2501170 .delay (10000,10000,10000) L_0x2501170/d; -L_0x2501230/d .functor AND 1, L_0x2500f50, L_0x2501170, C4<1>, C4<1>; -L_0x2501230 .delay (20000,20000,20000) L_0x2501230/d; -L_0x2501380/d .functor AND 1, L_0x2500730, L_0x25016a0, C4<1>, C4<1>; -L_0x2501380 .delay (20000,20000,20000) L_0x2501380/d; -L_0x25014d0/d .functor OR 1, L_0x2501230, L_0x2501380, C4<0>, C4<0>; -L_0x25014d0 .delay (20000,20000,20000) L_0x25014d0/d; -v0x241e2b0_0 .net "S", 0 0, L_0x25016a0; 1 drivers -v0x241e330_0 .alias "in0", 0 0, v0x241f1c0_0; -v0x241e3d0_0 .alias "in1", 0 0, v0x241ee70_0; -v0x241e470_0 .net "nS", 0 0, L_0x2501170; 1 drivers -v0x241e4f0_0 .net "out0", 0 0, L_0x2501230; 1 drivers -v0x241e590_0 .net "out1", 0 0, L_0x2501380; 1 drivers -v0x241e670_0 .alias "outfinal", 0 0, v0x241f140_0; -S_0x241cbd0 .scope generate, "orbits[7]" "orbits[7]" 2 196, 2 196, S_0x23d9540; - .timescale -9 -12; -P_0x241c8e8 .param/l "i" 2 196, +C4<0111>; -S_0x241cd00 .scope module, "attempt" "OrNorXor" 2 198, 2 64, S_0x241cbd0; - .timescale -9 -12; -L_0x25017e0/d .functor NOR 1, L_0x2502b70, L_0x25019b0, C4<0>, C4<0>; -L_0x25017e0 .delay (10000,10000,10000) L_0x25017e0/d; -L_0x2501ae0/d .functor NOT 1, L_0x25017e0, C4<0>, C4<0>, C4<0>; -L_0x2501ae0 .delay (10000,10000,10000) L_0x2501ae0/d; -L_0x2501bf0/d .functor NAND 1, L_0x2502b70, L_0x25019b0, C4<1>, C4<1>; -L_0x2501bf0 .delay (10000,10000,10000) L_0x2501bf0/d; -L_0x2501d50/d .functor NAND 1, L_0x2501bf0, L_0x2501ae0, C4<1>, C4<1>; -L_0x2501d50 .delay (10000,10000,10000) L_0x2501d50/d; -L_0x2501e60/d .functor NOT 1, L_0x2501d50, C4<0>, C4<0>, C4<0>; -L_0x2501e60 .delay (10000,10000,10000) L_0x2501e60/d; -v0x241d8b0_0 .net "A", 0 0, L_0x2502b70; 1 drivers -v0x241d950_0 .net "AnandB", 0 0, L_0x2501bf0; 1 drivers -v0x241d9f0_0 .net "AnorB", 0 0, L_0x25017e0; 1 drivers -v0x241daa0_0 .net "AorB", 0 0, L_0x2501ae0; 1 drivers -v0x241db80_0 .net "AxorB", 0 0, L_0x2501e60; 1 drivers -v0x241dc30_0 .net "B", 0 0, L_0x25019b0; 1 drivers -v0x241dcf0_0 .alias "Command", 2 0, v0x2463430_0; -v0x241dd70_0 .net "OrNorXorOut", 0 0, L_0x2502860; 1 drivers -v0x241ddf0_0 .net "XorNor", 0 0, L_0x25022e0; 1 drivers -v0x241dec0_0 .net "nXor", 0 0, L_0x2501d50; 1 drivers -L_0x2502460 .part C4, 2, 1; -L_0x2502a30 .part C4, 0, 1; -S_0x241d340 .scope module, "mux0" "TwoInMux" 2 83, 2 8, S_0x241cd00; - .timescale -9 -12; -L_0x2501fc0/d .functor NOT 1, L_0x2502460, C4<0>, C4<0>, C4<0>; -L_0x2501fc0 .delay (10000,10000,10000) L_0x2501fc0/d; -L_0x2502080/d .functor AND 1, L_0x2501e60, L_0x2501fc0, C4<1>, C4<1>; -L_0x2502080 .delay (20000,20000,20000) L_0x2502080/d; -L_0x2502190/d .functor AND 1, L_0x25017e0, L_0x2502460, C4<1>, C4<1>; -L_0x2502190 .delay (20000,20000,20000) L_0x2502190/d; -L_0x25022e0/d .functor OR 1, L_0x2502080, L_0x2502190, C4<0>, C4<0>; -L_0x25022e0 .delay (20000,20000,20000) L_0x25022e0/d; -v0x241d430_0 .net "S", 0 0, L_0x2502460; 1 drivers -v0x241d4f0_0 .alias "in0", 0 0, v0x241db80_0; -v0x241d590_0 .alias "in1", 0 0, v0x241d9f0_0; -v0x241d630_0 .net "nS", 0 0, L_0x2501fc0; 1 drivers -v0x241d6b0_0 .net "out0", 0 0, L_0x2502080; 1 drivers -v0x241d750_0 .net "out1", 0 0, L_0x2502190; 1 drivers -v0x241d830_0 .alias "outfinal", 0 0, v0x241ddf0_0; -S_0x241cdf0 .scope module, "mux1" "TwoInMux" 2 84, 2 8, S_0x241cd00; - .timescale -9 -12; -L_0x2502500/d .functor NOT 1, L_0x2502a30, C4<0>, C4<0>, C4<0>; -L_0x2502500 .delay (10000,10000,10000) L_0x2502500/d; -L_0x25025c0/d .functor AND 1, L_0x25022e0, L_0x2502500, C4<1>, C4<1>; -L_0x25025c0 .delay (20000,20000,20000) L_0x25025c0/d; -L_0x2502710/d .functor AND 1, L_0x2501ae0, L_0x2502a30, C4<1>, C4<1>; -L_0x2502710 .delay (20000,20000,20000) L_0x2502710/d; -L_0x2502860/d .functor OR 1, L_0x25025c0, L_0x2502710, C4<0>, C4<0>; -L_0x2502860 .delay (20000,20000,20000) L_0x2502860/d; -v0x241cee0_0 .net "S", 0 0, L_0x2502a30; 1 drivers -v0x241cf60_0 .alias "in0", 0 0, v0x241ddf0_0; -v0x241d000_0 .alias "in1", 0 0, v0x241daa0_0; -v0x241d0a0_0 .net "nS", 0 0, L_0x2502500; 1 drivers -v0x241d120_0 .net "out0", 0 0, L_0x25025c0; 1 drivers -v0x241d1c0_0 .net "out1", 0 0, L_0x2502710; 1 drivers -v0x241d2a0_0 .alias "outfinal", 0 0, v0x241dd70_0; -S_0x241b800 .scope generate, "orbits[8]" "orbits[8]" 2 196, 2 196, S_0x23d9540; - .timescale -9 -12; -P_0x241b518 .param/l "i" 2 196, +C4<01000>; -S_0x241b930 .scope module, "attempt" "OrNorXor" 2 198, 2 64, S_0x241b800; - .timescale -9 -12; -L_0x2502cc0/d .functor NOR 1, L_0x2502c10, L_0x2503f20, C4<0>, C4<0>; -L_0x2502cc0 .delay (10000,10000,10000) L_0x2502cc0/d; -L_0x2502db0/d .functor NOT 1, L_0x2502cc0, C4<0>, C4<0>, C4<0>; -L_0x2502db0 .delay (10000,10000,10000) L_0x2502db0/d; -L_0x2502ee0/d .functor NAND 1, L_0x2502c10, L_0x2503f20, C4<1>, C4<1>; -L_0x2502ee0 .delay (10000,10000,10000) L_0x2502ee0/d; -L_0x2503040/d .functor NAND 1, L_0x2502ee0, L_0x2502db0, C4<1>, C4<1>; -L_0x2503040 .delay (10000,10000,10000) L_0x2503040/d; -L_0x2503150/d .functor NOT 1, L_0x2503040, C4<0>, C4<0>, C4<0>; -L_0x2503150 .delay (10000,10000,10000) L_0x2503150/d; -v0x241c4e0_0 .net "A", 0 0, L_0x2502c10; 1 drivers -v0x241c580_0 .net "AnandB", 0 0, L_0x2502ee0; 1 drivers -v0x241c620_0 .net "AnorB", 0 0, L_0x2502cc0; 1 drivers -v0x241c6d0_0 .net "AorB", 0 0, L_0x2502db0; 1 drivers -v0x241c7b0_0 .net "AxorB", 0 0, L_0x2503150; 1 drivers -v0x241c860_0 .net "B", 0 0, L_0x2503f20; 1 drivers -v0x241c920_0 .alias "Command", 2 0, v0x2463430_0; -v0x241c9a0_0 .net "OrNorXorOut", 0 0, L_0x2503b50; 1 drivers -v0x241ca20_0 .net "XorNor", 0 0, L_0x25035d0; 1 drivers -v0x241caf0_0 .net "nXor", 0 0, L_0x2503040; 1 drivers -L_0x2503750 .part C4, 2, 1; -L_0x2503d20 .part C4, 0, 1; -S_0x241bf70 .scope module, "mux0" "TwoInMux" 2 83, 2 8, S_0x241b930; - .timescale -9 -12; -L_0x25032b0/d .functor NOT 1, L_0x2503750, C4<0>, C4<0>, C4<0>; -L_0x25032b0 .delay (10000,10000,10000) L_0x25032b0/d; -L_0x2503370/d .functor AND 1, L_0x2503150, L_0x25032b0, C4<1>, C4<1>; -L_0x2503370 .delay (20000,20000,20000) L_0x2503370/d; -L_0x2503480/d .functor AND 1, L_0x2502cc0, L_0x2503750, C4<1>, C4<1>; -L_0x2503480 .delay (20000,20000,20000) L_0x2503480/d; -L_0x25035d0/d .functor OR 1, L_0x2503370, L_0x2503480, C4<0>, C4<0>; -L_0x25035d0 .delay (20000,20000,20000) L_0x25035d0/d; -v0x241c060_0 .net "S", 0 0, L_0x2503750; 1 drivers -v0x241c120_0 .alias "in0", 0 0, v0x241c7b0_0; -v0x241c1c0_0 .alias "in1", 0 0, v0x241c620_0; -v0x241c260_0 .net "nS", 0 0, L_0x25032b0; 1 drivers -v0x241c2e0_0 .net "out0", 0 0, L_0x2503370; 1 drivers -v0x241c380_0 .net "out1", 0 0, L_0x2503480; 1 drivers -v0x241c460_0 .alias "outfinal", 0 0, v0x241ca20_0; -S_0x241ba20 .scope module, "mux1" "TwoInMux" 2 84, 2 8, S_0x241b930; - .timescale -9 -12; -L_0x25037f0/d .functor NOT 1, L_0x2503d20, C4<0>, C4<0>, C4<0>; -L_0x25037f0 .delay (10000,10000,10000) L_0x25037f0/d; -L_0x25038b0/d .functor AND 1, L_0x25035d0, L_0x25037f0, C4<1>, C4<1>; -L_0x25038b0 .delay (20000,20000,20000) L_0x25038b0/d; -L_0x2503a00/d .functor AND 1, L_0x2502db0, L_0x2503d20, C4<1>, C4<1>; -L_0x2503a00 .delay (20000,20000,20000) L_0x2503a00/d; -L_0x2503b50/d .functor OR 1, L_0x25038b0, L_0x2503a00, C4<0>, C4<0>; -L_0x2503b50 .delay (20000,20000,20000) L_0x2503b50/d; -v0x241bb10_0 .net "S", 0 0, L_0x2503d20; 1 drivers -v0x241bb90_0 .alias "in0", 0 0, v0x241ca20_0; -v0x241bc30_0 .alias "in1", 0 0, v0x241c6d0_0; -v0x241bcd0_0 .net "nS", 0 0, L_0x25037f0; 1 drivers -v0x241bd50_0 .net "out0", 0 0, L_0x25038b0; 1 drivers -v0x241bdf0_0 .net "out1", 0 0, L_0x2503a00; 1 drivers -v0x241bed0_0 .alias "outfinal", 0 0, v0x241c9a0_0; -S_0x241a430 .scope generate, "orbits[9]" "orbits[9]" 2 196, 2 196, S_0x23d9540; - .timescale -9 -12; -P_0x241a148 .param/l "i" 2 196, +C4<01001>; -S_0x241a560 .scope module, "attempt" "OrNorXor" 2 198, 2 64, S_0x241a430; - .timescale -9 -12; -L_0x2503e60/d .functor NOR 1, L_0x2505170, L_0x2503fc0, C4<0>, C4<0>; -L_0x2503e60 .delay (10000,10000,10000) L_0x2503e60/d; -L_0x25040e0/d .functor NOT 1, L_0x2503e60, C4<0>, C4<0>, C4<0>; -L_0x25040e0 .delay (10000,10000,10000) L_0x25040e0/d; -L_0x25041f0/d .functor NAND 1, L_0x2505170, L_0x2503fc0, C4<1>, C4<1>; -L_0x25041f0 .delay (10000,10000,10000) L_0x25041f0/d; -L_0x2504350/d .functor NAND 1, L_0x25041f0, L_0x25040e0, C4<1>, C4<1>; -L_0x2504350 .delay (10000,10000,10000) L_0x2504350/d; -L_0x2504460/d .functor NOT 1, L_0x2504350, C4<0>, C4<0>, C4<0>; -L_0x2504460 .delay (10000,10000,10000) L_0x2504460/d; -v0x241b110_0 .net "A", 0 0, L_0x2505170; 1 drivers -v0x241b1b0_0 .net "AnandB", 0 0, L_0x25041f0; 1 drivers -v0x241b250_0 .net "AnorB", 0 0, L_0x2503e60; 1 drivers -v0x241b300_0 .net "AorB", 0 0, L_0x25040e0; 1 drivers -v0x241b3e0_0 .net "AxorB", 0 0, L_0x2504460; 1 drivers -v0x241b490_0 .net "B", 0 0, L_0x2503fc0; 1 drivers -v0x241b550_0 .alias "Command", 2 0, v0x2463430_0; -v0x241b5d0_0 .net "OrNorXorOut", 0 0, L_0x2504e60; 1 drivers -v0x241b650_0 .net "XorNor", 0 0, L_0x25048e0; 1 drivers -v0x241b720_0 .net "nXor", 0 0, L_0x2504350; 1 drivers -L_0x2504a60 .part C4, 2, 1; -L_0x2505030 .part C4, 0, 1; -S_0x241aba0 .scope module, "mux0" "TwoInMux" 2 83, 2 8, S_0x241a560; - .timescale -9 -12; -L_0x25045c0/d .functor NOT 1, L_0x2504a60, C4<0>, C4<0>, C4<0>; -L_0x25045c0 .delay (10000,10000,10000) L_0x25045c0/d; -L_0x2504680/d .functor AND 1, L_0x2504460, L_0x25045c0, C4<1>, C4<1>; -L_0x2504680 .delay (20000,20000,20000) L_0x2504680/d; -L_0x2504790/d .functor AND 1, L_0x2503e60, L_0x2504a60, C4<1>, C4<1>; -L_0x2504790 .delay (20000,20000,20000) L_0x2504790/d; -L_0x25048e0/d .functor OR 1, L_0x2504680, L_0x2504790, C4<0>, C4<0>; -L_0x25048e0 .delay (20000,20000,20000) L_0x25048e0/d; -v0x241ac90_0 .net "S", 0 0, L_0x2504a60; 1 drivers -v0x241ad50_0 .alias "in0", 0 0, v0x241b3e0_0; -v0x241adf0_0 .alias "in1", 0 0, v0x241b250_0; -v0x241ae90_0 .net "nS", 0 0, L_0x25045c0; 1 drivers -v0x241af10_0 .net "out0", 0 0, L_0x2504680; 1 drivers -v0x241afb0_0 .net "out1", 0 0, L_0x2504790; 1 drivers -v0x241b090_0 .alias "outfinal", 0 0, v0x241b650_0; -S_0x241a650 .scope module, "mux1" "TwoInMux" 2 84, 2 8, S_0x241a560; - .timescale -9 -12; -L_0x2504b00/d .functor NOT 1, L_0x2505030, C4<0>, C4<0>, C4<0>; -L_0x2504b00 .delay (10000,10000,10000) L_0x2504b00/d; -L_0x2504bc0/d .functor AND 1, L_0x25048e0, L_0x2504b00, C4<1>, C4<1>; -L_0x2504bc0 .delay (20000,20000,20000) L_0x2504bc0/d; -L_0x2504d10/d .functor AND 1, L_0x25040e0, L_0x2505030, C4<1>, C4<1>; -L_0x2504d10 .delay (20000,20000,20000) L_0x2504d10/d; -L_0x2504e60/d .functor OR 1, L_0x2504bc0, L_0x2504d10, C4<0>, C4<0>; -L_0x2504e60 .delay (20000,20000,20000) L_0x2504e60/d; -v0x241a740_0 .net "S", 0 0, L_0x2505030; 1 drivers -v0x241a7c0_0 .alias "in0", 0 0, v0x241b650_0; -v0x241a860_0 .alias "in1", 0 0, v0x241b300_0; -v0x241a900_0 .net "nS", 0 0, L_0x2504b00; 1 drivers -v0x241a980_0 .net "out0", 0 0, L_0x2504bc0; 1 drivers -v0x241aa20_0 .net "out1", 0 0, L_0x2504d10; 1 drivers -v0x241ab00_0 .alias "outfinal", 0 0, v0x241b5d0_0; -S_0x2419060 .scope generate, "orbits[10]" "orbits[10]" 2 196, 2 196, S_0x23d9540; - .timescale -9 -12; -P_0x2418d28 .param/l "i" 2 196, +C4<01010>; -S_0x2419190 .scope module, "attempt" "OrNorXor" 2 198, 2 64, S_0x2419060; - .timescale -9 -12; -L_0x25052f0/d .functor NOR 1, L_0x2505210, L_0x2506560, C4<0>, C4<0>; -L_0x25052f0 .delay (10000,10000,10000) L_0x25052f0/d; -L_0x25053e0/d .functor NOT 1, L_0x25052f0, C4<0>, C4<0>, C4<0>; -L_0x25053e0 .delay (10000,10000,10000) L_0x25053e0/d; -L_0x25054f0/d .functor NAND 1, L_0x2505210, L_0x2506560, C4<1>, C4<1>; -L_0x25054f0 .delay (10000,10000,10000) L_0x25054f0/d; -L_0x2505650/d .functor NAND 1, L_0x25054f0, L_0x25053e0, C4<1>, C4<1>; -L_0x2505650 .delay (10000,10000,10000) L_0x2505650/d; -L_0x2505760/d .functor NOT 1, L_0x2505650, C4<0>, C4<0>, C4<0>; -L_0x2505760 .delay (10000,10000,10000) L_0x2505760/d; -v0x2419d40_0 .net "A", 0 0, L_0x2505210; 1 drivers -v0x2419de0_0 .net "AnandB", 0 0, L_0x25054f0; 1 drivers -v0x2419e80_0 .net "AnorB", 0 0, L_0x25052f0; 1 drivers -v0x2419f30_0 .net "AorB", 0 0, L_0x25053e0; 1 drivers -v0x241a010_0 .net "AxorB", 0 0, L_0x2505760; 1 drivers -v0x241a0c0_0 .net "B", 0 0, L_0x2506560; 1 drivers -v0x241a180_0 .alias "Command", 2 0, v0x2463430_0; -v0x241a200_0 .net "OrNorXorOut", 0 0, L_0x2506160; 1 drivers -v0x241a280_0 .net "XorNor", 0 0, L_0x2505be0; 1 drivers -v0x241a350_0 .net "nXor", 0 0, L_0x2505650; 1 drivers -L_0x2505d60 .part C4, 2, 1; -L_0x2506330 .part C4, 0, 1; -S_0x24197d0 .scope module, "mux0" "TwoInMux" 2 83, 2 8, S_0x2419190; - .timescale -9 -12; -L_0x25058c0/d .functor NOT 1, L_0x2505d60, C4<0>, C4<0>, C4<0>; -L_0x25058c0 .delay (10000,10000,10000) L_0x25058c0/d; -L_0x2505980/d .functor AND 1, L_0x2505760, L_0x25058c0, C4<1>, C4<1>; -L_0x2505980 .delay (20000,20000,20000) L_0x2505980/d; -L_0x2505a90/d .functor AND 1, L_0x25052f0, L_0x2505d60, C4<1>, C4<1>; -L_0x2505a90 .delay (20000,20000,20000) L_0x2505a90/d; -L_0x2505be0/d .functor OR 1, L_0x2505980, L_0x2505a90, C4<0>, C4<0>; -L_0x2505be0 .delay (20000,20000,20000) L_0x2505be0/d; -v0x24198c0_0 .net "S", 0 0, L_0x2505d60; 1 drivers -v0x2419980_0 .alias "in0", 0 0, v0x241a010_0; -v0x2419a20_0 .alias "in1", 0 0, v0x2419e80_0; -v0x2419ac0_0 .net "nS", 0 0, L_0x25058c0; 1 drivers -v0x2419b40_0 .net "out0", 0 0, L_0x2505980; 1 drivers -v0x2419be0_0 .net "out1", 0 0, L_0x2505a90; 1 drivers -v0x2419cc0_0 .alias "outfinal", 0 0, v0x241a280_0; -S_0x2419280 .scope module, "mux1" "TwoInMux" 2 84, 2 8, S_0x2419190; - .timescale -9 -12; -L_0x2505e00/d .functor NOT 1, L_0x2506330, C4<0>, C4<0>, C4<0>; -L_0x2505e00 .delay (10000,10000,10000) L_0x2505e00/d; -L_0x2505ec0/d .functor AND 1, L_0x2505be0, L_0x2505e00, C4<1>, C4<1>; -L_0x2505ec0 .delay (20000,20000,20000) L_0x2505ec0/d; -L_0x2506010/d .functor AND 1, L_0x25053e0, L_0x2506330, C4<1>, C4<1>; -L_0x2506010 .delay (20000,20000,20000) L_0x2506010/d; -L_0x2506160/d .functor OR 1, L_0x2505ec0, L_0x2506010, C4<0>, C4<0>; -L_0x2506160 .delay (20000,20000,20000) L_0x2506160/d; -v0x2419370_0 .net "S", 0 0, L_0x2506330; 1 drivers -v0x24193f0_0 .alias "in0", 0 0, v0x241a280_0; -v0x2419490_0 .alias "in1", 0 0, v0x2419f30_0; -v0x2419530_0 .net "nS", 0 0, L_0x2505e00; 1 drivers -v0x24195b0_0 .net "out0", 0 0, L_0x2505ec0; 1 drivers -v0x2419650_0 .net "out1", 0 0, L_0x2506010; 1 drivers -v0x2419730_0 .alias "outfinal", 0 0, v0x241a200_0; -S_0x2417c90 .scope generate, "orbits[11]" "orbits[11]" 2 196, 2 196, S_0x23d9540; - .timescale -9 -12; -P_0x24179a8 .param/l "i" 2 196, +C4<01011>; -S_0x2417dc0 .scope module, "attempt" "OrNorXor" 2 198, 2 64, S_0x2417c90; - .timescale -9 -12; -L_0x2506470/d .functor NOR 1, L_0x2507770, L_0x2506600, C4<0>, C4<0>; -L_0x2506470 .delay (10000,10000,10000) L_0x2506470/d; -L_0x2506700/d .functor NOT 1, L_0x2506470, C4<0>, C4<0>, C4<0>; -L_0x2506700 .delay (10000,10000,10000) L_0x2506700/d; -L_0x25067f0/d .functor NAND 1, L_0x2507770, L_0x2506600, C4<1>, C4<1>; -L_0x25067f0 .delay (10000,10000,10000) L_0x25067f0/d; -L_0x2506950/d .functor NAND 1, L_0x25067f0, L_0x2506700, C4<1>, C4<1>; -L_0x2506950 .delay (10000,10000,10000) L_0x2506950/d; -L_0x2506a60/d .functor NOT 1, L_0x2506950, C4<0>, C4<0>, C4<0>; -L_0x2506a60 .delay (10000,10000,10000) L_0x2506a60/d; -v0x2418920_0 .net "A", 0 0, L_0x2507770; 1 drivers -v0x24189c0_0 .net "AnandB", 0 0, L_0x25067f0; 1 drivers -v0x2418a60_0 .net "AnorB", 0 0, L_0x2506470; 1 drivers -v0x2418b10_0 .net "AorB", 0 0, L_0x2506700; 1 drivers -v0x2418bf0_0 .net "AxorB", 0 0, L_0x2506a60; 1 drivers -v0x2418ca0_0 .net "B", 0 0, L_0x2506600; 1 drivers -v0x2418d60_0 .alias "Command", 2 0, v0x2463430_0; -v0x2418de0_0 .net "OrNorXorOut", 0 0, L_0x2507460; 1 drivers -v0x2418eb0_0 .net "XorNor", 0 0, L_0x2506ee0; 1 drivers -v0x2418f80_0 .net "nXor", 0 0, L_0x2506950; 1 drivers -L_0x2507060 .part C4, 2, 1; -L_0x2507630 .part C4, 0, 1; -S_0x24183b0 .scope module, "mux0" "TwoInMux" 2 83, 2 8, S_0x2417dc0; - .timescale -9 -12; -L_0x2506bc0/d .functor NOT 1, L_0x2507060, C4<0>, C4<0>, C4<0>; -L_0x2506bc0 .delay (10000,10000,10000) L_0x2506bc0/d; -L_0x2506c80/d .functor AND 1, L_0x2506a60, L_0x2506bc0, C4<1>, C4<1>; -L_0x2506c80 .delay (20000,20000,20000) L_0x2506c80/d; -L_0x2506d90/d .functor AND 1, L_0x2506470, L_0x2507060, C4<1>, C4<1>; -L_0x2506d90 .delay (20000,20000,20000) L_0x2506d90/d; -L_0x2506ee0/d .functor OR 1, L_0x2506c80, L_0x2506d90, C4<0>, C4<0>; -L_0x2506ee0 .delay (20000,20000,20000) L_0x2506ee0/d; -v0x24184a0_0 .net "S", 0 0, L_0x2507060; 1 drivers -v0x2418560_0 .alias "in0", 0 0, v0x2418bf0_0; -v0x2418600_0 .alias "in1", 0 0, v0x2418a60_0; -v0x24186a0_0 .net "nS", 0 0, L_0x2506bc0; 1 drivers -v0x2418720_0 .net "out0", 0 0, L_0x2506c80; 1 drivers -v0x24187c0_0 .net "out1", 0 0, L_0x2506d90; 1 drivers -v0x24188a0_0 .alias "outfinal", 0 0, v0x2418eb0_0; -S_0x2417eb0 .scope module, "mux1" "TwoInMux" 2 84, 2 8, S_0x2417dc0; - .timescale -9 -12; -L_0x2507100/d .functor NOT 1, L_0x2507630, C4<0>, C4<0>, C4<0>; -L_0x2507100 .delay (10000,10000,10000) L_0x2507100/d; -L_0x25071c0/d .functor AND 1, L_0x2506ee0, L_0x2507100, C4<1>, C4<1>; -L_0x25071c0 .delay (20000,20000,20000) L_0x25071c0/d; -L_0x2507310/d .functor AND 1, L_0x2506700, L_0x2507630, C4<1>, C4<1>; -L_0x2507310 .delay (20000,20000,20000) L_0x2507310/d; -L_0x2507460/d .functor OR 1, L_0x25071c0, L_0x2507310, C4<0>, C4<0>; -L_0x2507460 .delay (20000,20000,20000) L_0x2507460/d; -v0x23de0c0_0 .net "S", 0 0, L_0x2507630; 1 drivers -v0x2417fa0_0 .alias "in0", 0 0, v0x2418eb0_0; -v0x2418040_0 .alias "in1", 0 0, v0x2418b10_0; -v0x24180e0_0 .net "nS", 0 0, L_0x2507100; 1 drivers -v0x2418190_0 .net "out0", 0 0, L_0x25071c0; 1 drivers -v0x2418230_0 .net "out1", 0 0, L_0x2507310; 1 drivers -v0x2418310_0 .alias "outfinal", 0 0, v0x2418de0_0; -S_0x24168c0 .scope generate, "orbits[12]" "orbits[12]" 2 196, 2 196, S_0x23d9540; - .timescale -9 -12; -P_0x24165d8 .param/l "i" 2 196, +C4<01100>; -S_0x24169f0 .scope module, "attempt" "OrNorXor" 2 198, 2 64, S_0x24168c0; - .timescale -9 -12; -L_0x25066a0/d .functor NOR 1, L_0x2507810, L_0x2508b80, C4<0>, C4<0>; -L_0x25066a0 .delay (10000,10000,10000) L_0x25066a0/d; -L_0x25079b0/d .functor NOT 1, L_0x25066a0, C4<0>, C4<0>, C4<0>; -L_0x25079b0 .delay (10000,10000,10000) L_0x25079b0/d; -L_0x2507ae0/d .functor NAND 1, L_0x2507810, L_0x2508b80, C4<1>, C4<1>; -L_0x2507ae0 .delay (10000,10000,10000) L_0x2507ae0/d; -L_0x2507c40/d .functor NAND 1, L_0x2507ae0, L_0x25079b0, C4<1>, C4<1>; -L_0x2507c40 .delay (10000,10000,10000) L_0x2507c40/d; -L_0x2507d50/d .functor NOT 1, L_0x2507c40, C4<0>, C4<0>, C4<0>; -L_0x2507d50 .delay (10000,10000,10000) L_0x2507d50/d; -v0x24175a0_0 .net "A", 0 0, L_0x2507810; 1 drivers -v0x2417640_0 .net "AnandB", 0 0, L_0x2507ae0; 1 drivers -v0x24176e0_0 .net "AnorB", 0 0, L_0x25066a0; 1 drivers -v0x2417790_0 .net "AorB", 0 0, L_0x25079b0; 1 drivers -v0x2417870_0 .net "AxorB", 0 0, L_0x2507d50; 1 drivers -v0x2417920_0 .net "B", 0 0, L_0x2508b80; 1 drivers -v0x24179e0_0 .alias "Command", 2 0, v0x2463430_0; -v0x2417a60_0 .net "OrNorXorOut", 0 0, L_0x2508750; 1 drivers -v0x2417ae0_0 .net "XorNor", 0 0, L_0x25081d0; 1 drivers -v0x2417bb0_0 .net "nXor", 0 0, L_0x2507c40; 1 drivers -L_0x2508350 .part C4, 2, 1; -L_0x2508920 .part C4, 0, 1; -S_0x2417030 .scope module, "mux0" "TwoInMux" 2 83, 2 8, S_0x24169f0; - .timescale -9 -12; -L_0x2507eb0/d .functor NOT 1, L_0x2508350, C4<0>, C4<0>, C4<0>; -L_0x2507eb0 .delay (10000,10000,10000) L_0x2507eb0/d; -L_0x2507f70/d .functor AND 1, L_0x2507d50, L_0x2507eb0, C4<1>, C4<1>; -L_0x2507f70 .delay (20000,20000,20000) L_0x2507f70/d; -L_0x2508080/d .functor AND 1, L_0x25066a0, L_0x2508350, C4<1>, C4<1>; -L_0x2508080 .delay (20000,20000,20000) L_0x2508080/d; -L_0x25081d0/d .functor OR 1, L_0x2507f70, L_0x2508080, C4<0>, C4<0>; -L_0x25081d0 .delay (20000,20000,20000) L_0x25081d0/d; -v0x2417120_0 .net "S", 0 0, L_0x2508350; 1 drivers -v0x24171e0_0 .alias "in0", 0 0, v0x2417870_0; -v0x2417280_0 .alias "in1", 0 0, v0x24176e0_0; -v0x2417320_0 .net "nS", 0 0, L_0x2507eb0; 1 drivers -v0x24173a0_0 .net "out0", 0 0, L_0x2507f70; 1 drivers -v0x2417440_0 .net "out1", 0 0, L_0x2508080; 1 drivers -v0x2417520_0 .alias "outfinal", 0 0, v0x2417ae0_0; -S_0x2416ae0 .scope module, "mux1" "TwoInMux" 2 84, 2 8, S_0x24169f0; - .timescale -9 -12; -L_0x25083f0/d .functor NOT 1, L_0x2508920, C4<0>, C4<0>, C4<0>; -L_0x25083f0 .delay (10000,10000,10000) L_0x25083f0/d; -L_0x25084b0/d .functor AND 1, L_0x25081d0, L_0x25083f0, C4<1>, C4<1>; -L_0x25084b0 .delay (20000,20000,20000) L_0x25084b0/d; -L_0x2508600/d .functor AND 1, L_0x25079b0, L_0x2508920, C4<1>, C4<1>; -L_0x2508600 .delay (20000,20000,20000) L_0x2508600/d; -L_0x2508750/d .functor OR 1, L_0x25084b0, L_0x2508600, C4<0>, C4<0>; -L_0x2508750 .delay (20000,20000,20000) L_0x2508750/d; -v0x2416bd0_0 .net "S", 0 0, L_0x2508920; 1 drivers -v0x2416c50_0 .alias "in0", 0 0, v0x2417ae0_0; -v0x2416cf0_0 .alias "in1", 0 0, v0x2417790_0; -v0x2416d90_0 .net "nS", 0 0, L_0x25083f0; 1 drivers -v0x2416e10_0 .net "out0", 0 0, L_0x25084b0; 1 drivers -v0x2416eb0_0 .net "out1", 0 0, L_0x2508600; 1 drivers -v0x2416f90_0 .alias "outfinal", 0 0, v0x2417a60_0; -S_0x24154f0 .scope generate, "orbits[13]" "orbits[13]" 2 196, 2 196, S_0x23d9540; - .timescale -9 -12; -P_0x2415208 .param/l "i" 2 196, +C4<01101>; -S_0x2415620 .scope module, "attempt" "OrNorXor" 2 198, 2 64, S_0x24154f0; - .timescale -9 -12; -L_0x25078b0/d .functor NOR 1, L_0x2509d80, L_0x2508c20, C4<0>, C4<0>; -L_0x25078b0 .delay (10000,10000,10000) L_0x25078b0/d; -L_0x2508af0/d .functor NOT 1, L_0x25078b0, C4<0>, C4<0>, C4<0>; -L_0x2508af0 .delay (10000,10000,10000) L_0x2508af0/d; -L_0x2508e00/d .functor NAND 1, L_0x2509d80, L_0x2508c20, C4<1>, C4<1>; -L_0x2508e00 .delay (10000,10000,10000) L_0x2508e00/d; -L_0x2508f60/d .functor NAND 1, L_0x2508e00, L_0x2508af0, C4<1>, C4<1>; -L_0x2508f60 .delay (10000,10000,10000) L_0x2508f60/d; -L_0x2509070/d .functor NOT 1, L_0x2508f60, C4<0>, C4<0>, C4<0>; -L_0x2509070 .delay (10000,10000,10000) L_0x2509070/d; -v0x24161d0_0 .net "A", 0 0, L_0x2509d80; 1 drivers -v0x2416270_0 .net "AnandB", 0 0, L_0x2508e00; 1 drivers -v0x2416310_0 .net "AnorB", 0 0, L_0x25078b0; 1 drivers -v0x24163c0_0 .net "AorB", 0 0, L_0x2508af0; 1 drivers -v0x24164a0_0 .net "AxorB", 0 0, L_0x2509070; 1 drivers -v0x2416550_0 .net "B", 0 0, L_0x2508c20; 1 drivers -v0x2416610_0 .alias "Command", 2 0, v0x2463430_0; -v0x2416690_0 .net "OrNorXorOut", 0 0, L_0x2509a70; 1 drivers -v0x2416710_0 .net "XorNor", 0 0, L_0x25094f0; 1 drivers -v0x24167e0_0 .net "nXor", 0 0, L_0x2508f60; 1 drivers -L_0x2509670 .part C4, 2, 1; -L_0x2509c40 .part C4, 0, 1; -S_0x2415c60 .scope module, "mux0" "TwoInMux" 2 83, 2 8, S_0x2415620; - .timescale -9 -12; -L_0x25091d0/d .functor NOT 1, L_0x2509670, C4<0>, C4<0>, C4<0>; -L_0x25091d0 .delay (10000,10000,10000) L_0x25091d0/d; -L_0x2509290/d .functor AND 1, L_0x2509070, L_0x25091d0, C4<1>, C4<1>; -L_0x2509290 .delay (20000,20000,20000) L_0x2509290/d; -L_0x25093a0/d .functor AND 1, L_0x25078b0, L_0x2509670, C4<1>, C4<1>; -L_0x25093a0 .delay (20000,20000,20000) L_0x25093a0/d; -L_0x25094f0/d .functor OR 1, L_0x2509290, L_0x25093a0, C4<0>, C4<0>; -L_0x25094f0 .delay (20000,20000,20000) L_0x25094f0/d; -v0x2415d50_0 .net "S", 0 0, L_0x2509670; 1 drivers -v0x2415e10_0 .alias "in0", 0 0, v0x24164a0_0; -v0x2415eb0_0 .alias "in1", 0 0, v0x2416310_0; -v0x2415f50_0 .net "nS", 0 0, L_0x25091d0; 1 drivers -v0x2415fd0_0 .net "out0", 0 0, L_0x2509290; 1 drivers -v0x2416070_0 .net "out1", 0 0, L_0x25093a0; 1 drivers -v0x2416150_0 .alias "outfinal", 0 0, v0x2416710_0; -S_0x2415710 .scope module, "mux1" "TwoInMux" 2 84, 2 8, S_0x2415620; - .timescale -9 -12; -L_0x2509710/d .functor NOT 1, L_0x2509c40, C4<0>, C4<0>, C4<0>; -L_0x2509710 .delay (10000,10000,10000) L_0x2509710/d; -L_0x25097d0/d .functor AND 1, L_0x25094f0, L_0x2509710, C4<1>, C4<1>; -L_0x25097d0 .delay (20000,20000,20000) L_0x25097d0/d; -L_0x2509920/d .functor AND 1, L_0x2508af0, L_0x2509c40, C4<1>, C4<1>; -L_0x2509920 .delay (20000,20000,20000) L_0x2509920/d; -L_0x2509a70/d .functor OR 1, L_0x25097d0, L_0x2509920, C4<0>, C4<0>; -L_0x2509a70 .delay (20000,20000,20000) L_0x2509a70/d; -v0x2415800_0 .net "S", 0 0, L_0x2509c40; 1 drivers -v0x2415880_0 .alias "in0", 0 0, v0x2416710_0; -v0x2415920_0 .alias "in1", 0 0, v0x24163c0_0; -v0x24159c0_0 .net "nS", 0 0, L_0x2509710; 1 drivers -v0x2415a40_0 .net "out0", 0 0, L_0x25097d0; 1 drivers -v0x2415ae0_0 .net "out1", 0 0, L_0x2509920; 1 drivers -v0x2415bc0_0 .alias "outfinal", 0 0, v0x2416690_0; -S_0x2414120 .scope generate, "orbits[14]" "orbits[14]" 2 196, 2 196, S_0x23d9540; - .timescale -9 -12; -P_0x2413d28 .param/l "i" 2 196, +C4<01110>; -S_0x2414250 .scope module, "attempt" "OrNorXor" 2 198, 2 64, S_0x2414120; - .timescale -9 -12; -L_0x2508cc0/d .functor NOR 1, L_0x2509e20, L_0x2509ec0, C4<0>, C4<0>; -L_0x2508cc0 .delay (10000,10000,10000) L_0x2508cc0/d; -L_0x2509ff0/d .functor NOT 1, L_0x2508cc0, C4<0>, C4<0>, C4<0>; -L_0x2509ff0 .delay (10000,10000,10000) L_0x2509ff0/d; -L_0x250a100/d .functor NAND 1, L_0x2509e20, L_0x2509ec0, C4<1>, C4<1>; -L_0x250a100 .delay (10000,10000,10000) L_0x250a100/d; -L_0x250a260/d .functor NAND 1, L_0x250a100, L_0x2509ff0, C4<1>, C4<1>; -L_0x250a260 .delay (10000,10000,10000) L_0x250a260/d; -L_0x250a370/d .functor NOT 1, L_0x250a260, C4<0>, C4<0>, C4<0>; -L_0x250a370 .delay (10000,10000,10000) L_0x250a370/d; -v0x2414e00_0 .net "A", 0 0, L_0x2509e20; 1 drivers -v0x2414ea0_0 .net "AnandB", 0 0, L_0x250a100; 1 drivers -v0x2414f40_0 .net "AnorB", 0 0, L_0x2508cc0; 1 drivers -v0x2414ff0_0 .net "AorB", 0 0, L_0x2509ff0; 1 drivers -v0x24150d0_0 .net "AxorB", 0 0, L_0x250a370; 1 drivers -v0x2415180_0 .net "B", 0 0, L_0x2509ec0; 1 drivers -v0x2415240_0 .alias "Command", 2 0, v0x2463430_0; -v0x24152c0_0 .net "OrNorXorOut", 0 0, L_0x250ad70; 1 drivers -v0x2415340_0 .net "XorNor", 0 0, L_0x250a7f0; 1 drivers -v0x2415410_0 .net "nXor", 0 0, L_0x250a260; 1 drivers -L_0x250a970 .part C4, 2, 1; -L_0x250af40 .part C4, 0, 1; -S_0x2414890 .scope module, "mux0" "TwoInMux" 2 83, 2 8, S_0x2414250; - .timescale -9 -12; -L_0x250a4d0/d .functor NOT 1, L_0x250a970, C4<0>, C4<0>, C4<0>; -L_0x250a4d0 .delay (10000,10000,10000) L_0x250a4d0/d; -L_0x250a590/d .functor AND 1, L_0x250a370, L_0x250a4d0, C4<1>, C4<1>; -L_0x250a590 .delay (20000,20000,20000) L_0x250a590/d; -L_0x250a6a0/d .functor AND 1, L_0x2508cc0, L_0x250a970, C4<1>, C4<1>; -L_0x250a6a0 .delay (20000,20000,20000) L_0x250a6a0/d; -L_0x250a7f0/d .functor OR 1, L_0x250a590, L_0x250a6a0, C4<0>, C4<0>; -L_0x250a7f0 .delay (20000,20000,20000) L_0x250a7f0/d; -v0x2414980_0 .net "S", 0 0, L_0x250a970; 1 drivers -v0x2414a40_0 .alias "in0", 0 0, v0x24150d0_0; -v0x2414ae0_0 .alias "in1", 0 0, v0x2414f40_0; -v0x2414b80_0 .net "nS", 0 0, L_0x250a4d0; 1 drivers -v0x2414c00_0 .net "out0", 0 0, L_0x250a590; 1 drivers -v0x2414ca0_0 .net "out1", 0 0, L_0x250a6a0; 1 drivers -v0x2414d80_0 .alias "outfinal", 0 0, v0x2415340_0; -S_0x2414340 .scope module, "mux1" "TwoInMux" 2 84, 2 8, S_0x2414250; - .timescale -9 -12; -L_0x250aa10/d .functor NOT 1, L_0x250af40, C4<0>, C4<0>, C4<0>; -L_0x250aa10 .delay (10000,10000,10000) L_0x250aa10/d; -L_0x250aad0/d .functor AND 1, L_0x250a7f0, L_0x250aa10, C4<1>, C4<1>; -L_0x250aad0 .delay (20000,20000,20000) L_0x250aad0/d; -L_0x250ac20/d .functor AND 1, L_0x2509ff0, L_0x250af40, C4<1>, C4<1>; -L_0x250ac20 .delay (20000,20000,20000) L_0x250ac20/d; -L_0x250ad70/d .functor OR 1, L_0x250aad0, L_0x250ac20, C4<0>, C4<0>; -L_0x250ad70 .delay (20000,20000,20000) L_0x250ad70/d; -v0x2414430_0 .net "S", 0 0, L_0x250af40; 1 drivers -v0x24144b0_0 .alias "in0", 0 0, v0x2415340_0; -v0x2414550_0 .alias "in1", 0 0, v0x2414ff0_0; -v0x24145f0_0 .net "nS", 0 0, L_0x250aa10; 1 drivers -v0x2414670_0 .net "out0", 0 0, L_0x250aad0; 1 drivers -v0x2414710_0 .net "out1", 0 0, L_0x250ac20; 1 drivers -v0x24147f0_0 .alias "outfinal", 0 0, v0x24152c0_0; -S_0x2412c40 .scope generate, "orbits[15]" "orbits[15]" 2 196, 2 196, S_0x23d9540; - .timescale -9 -12; -P_0x2412958 .param/l "i" 2 196, +C4<01111>; -S_0x2412d70 .scope module, "attempt" "OrNorXor" 2 198, 2 64, S_0x2412c40; - .timescale -9 -12; -L_0x250b1e0/d .functor NOR 1, L_0x250c380, L_0x250b080, C4<0>, C4<0>; -L_0x250b1e0 .delay (10000,10000,10000) L_0x250b1e0/d; -L_0x250b2d0/d .functor NOT 1, L_0x250b1e0, C4<0>, C4<0>, C4<0>; -L_0x250b2d0 .delay (10000,10000,10000) L_0x250b2d0/d; -L_0x250b400/d .functor NAND 1, L_0x250c380, L_0x250b080, C4<1>, C4<1>; -L_0x250b400 .delay (10000,10000,10000) L_0x250b400/d; -L_0x250b560/d .functor NAND 1, L_0x250b400, L_0x250b2d0, C4<1>, C4<1>; -L_0x250b560 .delay (10000,10000,10000) L_0x250b560/d; -L_0x250b670/d .functor NOT 1, L_0x250b560, C4<0>, C4<0>, C4<0>; -L_0x250b670 .delay (10000,10000,10000) L_0x250b670/d; -v0x2413920_0 .net "A", 0 0, L_0x250c380; 1 drivers -v0x24139c0_0 .net "AnandB", 0 0, L_0x250b400; 1 drivers -v0x2413a60_0 .net "AnorB", 0 0, L_0x250b1e0; 1 drivers -v0x2413b10_0 .net "AorB", 0 0, L_0x250b2d0; 1 drivers -v0x2413bf0_0 .net "AxorB", 0 0, L_0x250b670; 1 drivers -v0x2413ca0_0 .net "B", 0 0, L_0x250b080; 1 drivers -v0x2413d60_0 .alias "Command", 2 0, v0x2463430_0; -v0x240a1d0_0 .net "OrNorXorOut", 0 0, L_0x250c070; 1 drivers -v0x240a250_0 .net "XorNor", 0 0, L_0x250baf0; 1 drivers -v0x2414040_0 .net "nXor", 0 0, L_0x250b560; 1 drivers -L_0x250bc70 .part C4, 2, 1; -L_0x250c240 .part C4, 0, 1; -S_0x24133b0 .scope module, "mux0" "TwoInMux" 2 83, 2 8, S_0x2412d70; - .timescale -9 -12; -L_0x250b7d0/d .functor NOT 1, L_0x250bc70, C4<0>, C4<0>, C4<0>; -L_0x250b7d0 .delay (10000,10000,10000) L_0x250b7d0/d; -L_0x250b890/d .functor AND 1, L_0x250b670, L_0x250b7d0, C4<1>, C4<1>; -L_0x250b890 .delay (20000,20000,20000) L_0x250b890/d; -L_0x250b9a0/d .functor AND 1, L_0x250b1e0, L_0x250bc70, C4<1>, C4<1>; -L_0x250b9a0 .delay (20000,20000,20000) L_0x250b9a0/d; -L_0x250baf0/d .functor OR 1, L_0x250b890, L_0x250b9a0, C4<0>, C4<0>; -L_0x250baf0 .delay (20000,20000,20000) L_0x250baf0/d; -v0x24134a0_0 .net "S", 0 0, L_0x250bc70; 1 drivers -v0x2413560_0 .alias "in0", 0 0, v0x2413bf0_0; -v0x2413600_0 .alias "in1", 0 0, v0x2413a60_0; -v0x24136a0_0 .net "nS", 0 0, L_0x250b7d0; 1 drivers -v0x2413720_0 .net "out0", 0 0, L_0x250b890; 1 drivers -v0x24137c0_0 .net "out1", 0 0, L_0x250b9a0; 1 drivers -v0x24138a0_0 .alias "outfinal", 0 0, v0x240a250_0; -S_0x2412e60 .scope module, "mux1" "TwoInMux" 2 84, 2 8, S_0x2412d70; - .timescale -9 -12; -L_0x250bd10/d .functor NOT 1, L_0x250c240, C4<0>, C4<0>, C4<0>; -L_0x250bd10 .delay (10000,10000,10000) L_0x250bd10/d; -L_0x250bdd0/d .functor AND 1, L_0x250baf0, L_0x250bd10, C4<1>, C4<1>; -L_0x250bdd0 .delay (20000,20000,20000) L_0x250bdd0/d; -L_0x250bf20/d .functor AND 1, L_0x250b2d0, L_0x250c240, C4<1>, C4<1>; -L_0x250bf20 .delay (20000,20000,20000) L_0x250bf20/d; -L_0x250c070/d .functor OR 1, L_0x250bdd0, L_0x250bf20, C4<0>, C4<0>; -L_0x250c070 .delay (20000,20000,20000) L_0x250c070/d; -v0x2412f50_0 .net "S", 0 0, L_0x250c240; 1 drivers -v0x2412fd0_0 .alias "in0", 0 0, v0x240a250_0; -v0x2413070_0 .alias "in1", 0 0, v0x2413b10_0; -v0x2413110_0 .net "nS", 0 0, L_0x250bd10; 1 drivers -v0x2413190_0 .net "out0", 0 0, L_0x250bdd0; 1 drivers -v0x2413230_0 .net "out1", 0 0, L_0x250bf20; 1 drivers -v0x2413310_0 .alias "outfinal", 0 0, v0x240a1d0_0; -S_0x2411870 .scope generate, "orbits[16]" "orbits[16]" 2 196, 2 196, S_0x23d9540; - .timescale -9 -12; -P_0x2411588 .param/l "i" 2 196, +C4<010000>; -S_0x24119a0 .scope module, "attempt" "OrNorXor" 2 198, 2 64, S_0x2411870; - .timescale -9 -12; -L_0x250b120/d .functor NOR 1, L_0x250c420, L_0x250c4c0, C4<0>, C4<0>; -L_0x250b120 .delay (10000,10000,10000) L_0x250b120/d; -L_0x250c5e0/d .functor NOT 1, L_0x250b120, C4<0>, C4<0>, C4<0>; -L_0x250c5e0 .delay (10000,10000,10000) L_0x250c5e0/d; -L_0x250c6f0/d .functor NAND 1, L_0x250c420, L_0x250c4c0, C4<1>, C4<1>; -L_0x250c6f0 .delay (10000,10000,10000) L_0x250c6f0/d; -L_0x250c850/d .functor NAND 1, L_0x250c6f0, L_0x250c5e0, C4<1>, C4<1>; -L_0x250c850 .delay (10000,10000,10000) L_0x250c850/d; -L_0x250c960/d .functor NOT 1, L_0x250c850, C4<0>, C4<0>, C4<0>; -L_0x250c960 .delay (10000,10000,10000) L_0x250c960/d; -v0x2412550_0 .net "A", 0 0, L_0x250c420; 1 drivers -v0x24125f0_0 .net "AnandB", 0 0, L_0x250c6f0; 1 drivers -v0x2412690_0 .net "AnorB", 0 0, L_0x250b120; 1 drivers -v0x2412740_0 .net "AorB", 0 0, L_0x250c5e0; 1 drivers -v0x2412820_0 .net "AxorB", 0 0, L_0x250c960; 1 drivers -v0x24128d0_0 .net "B", 0 0, L_0x250c4c0; 1 drivers -v0x2412990_0 .alias "Command", 2 0, v0x2463430_0; -v0x2412a10_0 .net "OrNorXorOut", 0 0, L_0x250d360; 1 drivers -v0x2412a90_0 .net "XorNor", 0 0, L_0x250cde0; 1 drivers -v0x2412b60_0 .net "nXor", 0 0, L_0x250c850; 1 drivers -L_0x250cf60 .part C4, 2, 1; -L_0x250d530 .part C4, 0, 1; -S_0x2411fe0 .scope module, "mux0" "TwoInMux" 2 83, 2 8, S_0x24119a0; - .timescale -9 -12; -L_0x250cac0/d .functor NOT 1, L_0x250cf60, C4<0>, C4<0>, C4<0>; -L_0x250cac0 .delay (10000,10000,10000) L_0x250cac0/d; -L_0x250cb80/d .functor AND 1, L_0x250c960, L_0x250cac0, C4<1>, C4<1>; -L_0x250cb80 .delay (20000,20000,20000) L_0x250cb80/d; -L_0x250cc90/d .functor AND 1, L_0x250b120, L_0x250cf60, C4<1>, C4<1>; -L_0x250cc90 .delay (20000,20000,20000) L_0x250cc90/d; -L_0x250cde0/d .functor OR 1, L_0x250cb80, L_0x250cc90, C4<0>, C4<0>; -L_0x250cde0 .delay (20000,20000,20000) L_0x250cde0/d; -v0x24120d0_0 .net "S", 0 0, L_0x250cf60; 1 drivers -v0x2412190_0 .alias "in0", 0 0, v0x2412820_0; -v0x2412230_0 .alias "in1", 0 0, v0x2412690_0; -v0x24122d0_0 .net "nS", 0 0, L_0x250cac0; 1 drivers -v0x2412350_0 .net "out0", 0 0, L_0x250cb80; 1 drivers -v0x24123f0_0 .net "out1", 0 0, L_0x250cc90; 1 drivers -v0x24124d0_0 .alias "outfinal", 0 0, v0x2412a90_0; -S_0x2411a90 .scope module, "mux1" "TwoInMux" 2 84, 2 8, S_0x24119a0; - .timescale -9 -12; -L_0x250d000/d .functor NOT 1, L_0x250d530, C4<0>, C4<0>, C4<0>; -L_0x250d000 .delay (10000,10000,10000) L_0x250d000/d; -L_0x250d0c0/d .functor AND 1, L_0x250cde0, L_0x250d000, C4<1>, C4<1>; -L_0x250d0c0 .delay (20000,20000,20000) L_0x250d0c0/d; -L_0x250d210/d .functor AND 1, L_0x250c5e0, L_0x250d530, C4<1>, C4<1>; -L_0x250d210 .delay (20000,20000,20000) L_0x250d210/d; -L_0x250d360/d .functor OR 1, L_0x250d0c0, L_0x250d210, C4<0>, C4<0>; -L_0x250d360 .delay (20000,20000,20000) L_0x250d360/d; -v0x2411b80_0 .net "S", 0 0, L_0x250d530; 1 drivers -v0x2411c00_0 .alias "in0", 0 0, v0x2412a90_0; -v0x2411ca0_0 .alias "in1", 0 0, v0x2412740_0; -v0x2411d40_0 .net "nS", 0 0, L_0x250d000; 1 drivers -v0x2411dc0_0 .net "out0", 0 0, L_0x250d0c0; 1 drivers -v0x2411e60_0 .net "out1", 0 0, L_0x250d210; 1 drivers -v0x2411f40_0 .alias "outfinal", 0 0, v0x2412a10_0; -S_0x24104a0 .scope generate, "orbits[17]" "orbits[17]" 2 196, 2 196, S_0x23d9540; - .timescale -9 -12; -P_0x24101b8 .param/l "i" 2 196, +C4<010001>; -S_0x24105d0 .scope module, "attempt" "OrNorXor" 2 198, 2 64, S_0x24104a0; - .timescale -9 -12; -L_0x250d800/d .functor NOR 1, L_0x250e980, L_0x250d670, C4<0>, C4<0>; -L_0x250d800 .delay (10000,10000,10000) L_0x250d800/d; -L_0x250d8f0/d .functor NOT 1, L_0x250d800, C4<0>, C4<0>, C4<0>; -L_0x250d8f0 .delay (10000,10000,10000) L_0x250d8f0/d; -L_0x250da00/d .functor NAND 1, L_0x250e980, L_0x250d670, C4<1>, C4<1>; -L_0x250da00 .delay (10000,10000,10000) L_0x250da00/d; -L_0x250db60/d .functor NAND 1, L_0x250da00, L_0x250d8f0, C4<1>, C4<1>; -L_0x250db60 .delay (10000,10000,10000) L_0x250db60/d; -L_0x250dc70/d .functor NOT 1, L_0x250db60, C4<0>, C4<0>, C4<0>; -L_0x250dc70 .delay (10000,10000,10000) L_0x250dc70/d; -v0x2411180_0 .net "A", 0 0, L_0x250e980; 1 drivers -v0x2411220_0 .net "AnandB", 0 0, L_0x250da00; 1 drivers -v0x24112c0_0 .net "AnorB", 0 0, L_0x250d800; 1 drivers -v0x2411370_0 .net "AorB", 0 0, L_0x250d8f0; 1 drivers -v0x2411450_0 .net "AxorB", 0 0, L_0x250dc70; 1 drivers -v0x2411500_0 .net "B", 0 0, L_0x250d670; 1 drivers -v0x24115c0_0 .alias "Command", 2 0, v0x2463430_0; -v0x2411640_0 .net "OrNorXorOut", 0 0, L_0x250e670; 1 drivers -v0x24116c0_0 .net "XorNor", 0 0, L_0x250e0f0; 1 drivers -v0x2411790_0 .net "nXor", 0 0, L_0x250db60; 1 drivers -L_0x250e270 .part C4, 2, 1; -L_0x250e840 .part C4, 0, 1; -S_0x2410c10 .scope module, "mux0" "TwoInMux" 2 83, 2 8, S_0x24105d0; - .timescale -9 -12; -L_0x250ddd0/d .functor NOT 1, L_0x250e270, C4<0>, C4<0>, C4<0>; -L_0x250ddd0 .delay (10000,10000,10000) L_0x250ddd0/d; -L_0x250de90/d .functor AND 1, L_0x250dc70, L_0x250ddd0, C4<1>, C4<1>; -L_0x250de90 .delay (20000,20000,20000) L_0x250de90/d; -L_0x250dfa0/d .functor AND 1, L_0x250d800, L_0x250e270, C4<1>, C4<1>; -L_0x250dfa0 .delay (20000,20000,20000) L_0x250dfa0/d; -L_0x250e0f0/d .functor OR 1, L_0x250de90, L_0x250dfa0, C4<0>, C4<0>; -L_0x250e0f0 .delay (20000,20000,20000) L_0x250e0f0/d; -v0x2410d00_0 .net "S", 0 0, L_0x250e270; 1 drivers -v0x2410dc0_0 .alias "in0", 0 0, v0x2411450_0; -v0x2410e60_0 .alias "in1", 0 0, v0x24112c0_0; -v0x2410f00_0 .net "nS", 0 0, L_0x250ddd0; 1 drivers -v0x2410f80_0 .net "out0", 0 0, L_0x250de90; 1 drivers -v0x2411020_0 .net "out1", 0 0, L_0x250dfa0; 1 drivers -v0x2411100_0 .alias "outfinal", 0 0, v0x24116c0_0; -S_0x24106c0 .scope module, "mux1" "TwoInMux" 2 84, 2 8, S_0x24105d0; - .timescale -9 -12; -L_0x250e310/d .functor NOT 1, L_0x250e840, C4<0>, C4<0>, C4<0>; -L_0x250e310 .delay (10000,10000,10000) L_0x250e310/d; -L_0x250e3d0/d .functor AND 1, L_0x250e0f0, L_0x250e310, C4<1>, C4<1>; -L_0x250e3d0 .delay (20000,20000,20000) L_0x250e3d0/d; -L_0x250e520/d .functor AND 1, L_0x250d8f0, L_0x250e840, C4<1>, C4<1>; -L_0x250e520 .delay (20000,20000,20000) L_0x250e520/d; -L_0x250e670/d .functor OR 1, L_0x250e3d0, L_0x250e520, C4<0>, C4<0>; -L_0x250e670 .delay (20000,20000,20000) L_0x250e670/d; -v0x24107b0_0 .net "S", 0 0, L_0x250e840; 1 drivers -v0x2410830_0 .alias "in0", 0 0, v0x24116c0_0; -v0x24108d0_0 .alias "in1", 0 0, v0x2411370_0; -v0x2410970_0 .net "nS", 0 0, L_0x250e310; 1 drivers -v0x24109f0_0 .net "out0", 0 0, L_0x250e3d0; 1 drivers -v0x2410a90_0 .net "out1", 0 0, L_0x250e520; 1 drivers -v0x2410b70_0 .alias "outfinal", 0 0, v0x2411640_0; -S_0x240f0d0 .scope generate, "orbits[18]" "orbits[18]" 2 196, 2 196, S_0x23d9540; - .timescale -9 -12; -P_0x240ede8 .param/l "i" 2 196, +C4<010010>; -S_0x240f200 .scope module, "attempt" "OrNorXor" 2 198, 2 64, S_0x240f0d0; - .timescale -9 -12; -L_0x250d710/d .functor NOR 1, L_0x250ea20, L_0x250eac0, C4<0>, C4<0>; -L_0x250d710 .delay (10000,10000,10000) L_0x250d710/d; -L_0x250ebc0/d .functor NOT 1, L_0x250d710, C4<0>, C4<0>, C4<0>; -L_0x250ebc0 .delay (10000,10000,10000) L_0x250ebc0/d; -L_0x250ecf0/d .functor NAND 1, L_0x250ea20, L_0x250eac0, C4<1>, C4<1>; -L_0x250ecf0 .delay (10000,10000,10000) L_0x250ecf0/d; -L_0x250ee50/d .functor NAND 1, L_0x250ecf0, L_0x250ebc0, C4<1>, C4<1>; -L_0x250ee50 .delay (10000,10000,10000) L_0x250ee50/d; -L_0x250ef60/d .functor NOT 1, L_0x250ee50, C4<0>, C4<0>, C4<0>; -L_0x250ef60 .delay (10000,10000,10000) L_0x250ef60/d; -v0x240fdb0_0 .net "A", 0 0, L_0x250ea20; 1 drivers -v0x240fe50_0 .net "AnandB", 0 0, L_0x250ecf0; 1 drivers -v0x240fef0_0 .net "AnorB", 0 0, L_0x250d710; 1 drivers -v0x240ffa0_0 .net "AorB", 0 0, L_0x250ebc0; 1 drivers -v0x2410080_0 .net "AxorB", 0 0, L_0x250ef60; 1 drivers -v0x2410130_0 .net "B", 0 0, L_0x250eac0; 1 drivers -v0x24101f0_0 .alias "Command", 2 0, v0x2463430_0; -v0x2410270_0 .net "OrNorXorOut", 0 0, L_0x250f960; 1 drivers -v0x24102f0_0 .net "XorNor", 0 0, L_0x250f3e0; 1 drivers -v0x24103c0_0 .net "nXor", 0 0, L_0x250ee50; 1 drivers -L_0x250f560 .part C4, 2, 1; -L_0x250fb30 .part C4, 0, 1; -S_0x240f840 .scope module, "mux0" "TwoInMux" 2 83, 2 8, S_0x240f200; - .timescale -9 -12; -L_0x250f0c0/d .functor NOT 1, L_0x250f560, C4<0>, C4<0>, C4<0>; -L_0x250f0c0 .delay (10000,10000,10000) L_0x250f0c0/d; -L_0x250f180/d .functor AND 1, L_0x250ef60, L_0x250f0c0, C4<1>, C4<1>; -L_0x250f180 .delay (20000,20000,20000) L_0x250f180/d; -L_0x250f290/d .functor AND 1, L_0x250d710, L_0x250f560, C4<1>, C4<1>; -L_0x250f290 .delay (20000,20000,20000) L_0x250f290/d; -L_0x250f3e0/d .functor OR 1, L_0x250f180, L_0x250f290, C4<0>, C4<0>; -L_0x250f3e0 .delay (20000,20000,20000) L_0x250f3e0/d; -v0x240f930_0 .net "S", 0 0, L_0x250f560; 1 drivers -v0x240f9f0_0 .alias "in0", 0 0, v0x2410080_0; -v0x240fa90_0 .alias "in1", 0 0, v0x240fef0_0; -v0x240fb30_0 .net "nS", 0 0, L_0x250f0c0; 1 drivers -v0x240fbb0_0 .net "out0", 0 0, L_0x250f180; 1 drivers -v0x240fc50_0 .net "out1", 0 0, L_0x250f290; 1 drivers -v0x240fd30_0 .alias "outfinal", 0 0, v0x24102f0_0; -S_0x240f2f0 .scope module, "mux1" "TwoInMux" 2 84, 2 8, S_0x240f200; - .timescale -9 -12; -L_0x250f600/d .functor NOT 1, L_0x250fb30, C4<0>, C4<0>, C4<0>; -L_0x250f600 .delay (10000,10000,10000) L_0x250f600/d; -L_0x250f6c0/d .functor AND 1, L_0x250f3e0, L_0x250f600, C4<1>, C4<1>; -L_0x250f6c0 .delay (20000,20000,20000) L_0x250f6c0/d; -L_0x250f810/d .functor AND 1, L_0x250ebc0, L_0x250fb30, C4<1>, C4<1>; -L_0x250f810 .delay (20000,20000,20000) L_0x250f810/d; -L_0x250f960/d .functor OR 1, L_0x250f6c0, L_0x250f810, C4<0>, C4<0>; -L_0x250f960 .delay (20000,20000,20000) L_0x250f960/d; -v0x240f3e0_0 .net "S", 0 0, L_0x250fb30; 1 drivers -v0x240f460_0 .alias "in0", 0 0, v0x24102f0_0; -v0x240f500_0 .alias "in1", 0 0, v0x240ffa0_0; -v0x240f5a0_0 .net "nS", 0 0, L_0x250f600; 1 drivers -v0x240f620_0 .net "out0", 0 0, L_0x250f6c0; 1 drivers -v0x240f6c0_0 .net "out1", 0 0, L_0x250f810; 1 drivers -v0x240f7a0_0 .alias "outfinal", 0 0, v0x2410270_0; -S_0x240ddc0 .scope generate, "orbits[19]" "orbits[19]" 2 196, 2 196, S_0x23d9540; - .timescale -9 -12; -P_0x240dad8 .param/l "i" 2 196, +C4<010011>; -S_0x240def0 .scope module, "attempt" "OrNorXor" 2 198, 2 64, S_0x240ddc0; - .timescale -9 -12; -L_0x250eb60/d .functor NOR 1, L_0x2510f70, L_0x250fc70, C4<0>, C4<0>; -L_0x250eb60 .delay (10000,10000,10000) L_0x250eb60/d; -L_0x250fec0/d .functor NOT 1, L_0x250eb60, C4<0>, C4<0>, C4<0>; -L_0x250fec0 .delay (10000,10000,10000) L_0x250fec0/d; -L_0x250fff0/d .functor NAND 1, L_0x2510f70, L_0x250fc70, C4<1>, C4<1>; -L_0x250fff0 .delay (10000,10000,10000) L_0x250fff0/d; -L_0x2510150/d .functor NAND 1, L_0x250fff0, L_0x250fec0, C4<1>, C4<1>; -L_0x2510150 .delay (10000,10000,10000) L_0x2510150/d; -L_0x2510260/d .functor NOT 1, L_0x2510150, C4<0>, C4<0>, C4<0>; -L_0x2510260 .delay (10000,10000,10000) L_0x2510260/d; -v0x240eaa0_0 .net "A", 0 0, L_0x2510f70; 1 drivers -v0x240eb40_0 .net "AnandB", 0 0, L_0x250fff0; 1 drivers -v0x240ebe0_0 .net "AnorB", 0 0, L_0x250eb60; 1 drivers -v0x240ec60_0 .net "AorB", 0 0, L_0x250fec0; 1 drivers -v0x240ece0_0 .net "AxorB", 0 0, L_0x2510260; 1 drivers -v0x240ed60_0 .net "B", 0 0, L_0x250fc70; 1 drivers -v0x240ee20_0 .alias "Command", 2 0, v0x2463430_0; -v0x240eea0_0 .net "OrNorXorOut", 0 0, L_0x2510c60; 1 drivers -v0x240ef20_0 .net "XorNor", 0 0, L_0x25106e0; 1 drivers -v0x240eff0_0 .net "nXor", 0 0, L_0x2510150; 1 drivers -L_0x2510860 .part C4, 2, 1; -L_0x2510e30 .part C4, 0, 1; -S_0x240e530 .scope module, "mux0" "TwoInMux" 2 83, 2 8, S_0x240def0; - .timescale -9 -12; -L_0x25103c0/d .functor NOT 1, L_0x2510860, C4<0>, C4<0>, C4<0>; -L_0x25103c0 .delay (10000,10000,10000) L_0x25103c0/d; -L_0x2510480/d .functor AND 1, L_0x2510260, L_0x25103c0, C4<1>, C4<1>; -L_0x2510480 .delay (20000,20000,20000) L_0x2510480/d; -L_0x2510590/d .functor AND 1, L_0x250eb60, L_0x2510860, C4<1>, C4<1>; -L_0x2510590 .delay (20000,20000,20000) L_0x2510590/d; -L_0x25106e0/d .functor OR 1, L_0x2510480, L_0x2510590, C4<0>, C4<0>; -L_0x25106e0 .delay (20000,20000,20000) L_0x25106e0/d; -v0x240e620_0 .net "S", 0 0, L_0x2510860; 1 drivers -v0x240e6e0_0 .alias "in0", 0 0, v0x240ece0_0; -v0x240e780_0 .alias "in1", 0 0, v0x240ebe0_0; -v0x240e820_0 .net "nS", 0 0, L_0x25103c0; 1 drivers -v0x240e8a0_0 .net "out0", 0 0, L_0x2510480; 1 drivers -v0x240e940_0 .net "out1", 0 0, L_0x2510590; 1 drivers -v0x240ea20_0 .alias "outfinal", 0 0, v0x240ef20_0; -S_0x240dfe0 .scope module, "mux1" "TwoInMux" 2 84, 2 8, S_0x240def0; - .timescale -9 -12; -L_0x2510900/d .functor NOT 1, L_0x2510e30, C4<0>, C4<0>, C4<0>; -L_0x2510900 .delay (10000,10000,10000) L_0x2510900/d; -L_0x25109c0/d .functor AND 1, L_0x25106e0, L_0x2510900, C4<1>, C4<1>; -L_0x25109c0 .delay (20000,20000,20000) L_0x25109c0/d; -L_0x2510b10/d .functor AND 1, L_0x250fec0, L_0x2510e30, C4<1>, C4<1>; -L_0x2510b10 .delay (20000,20000,20000) L_0x2510b10/d; -L_0x2510c60/d .functor OR 1, L_0x25109c0, L_0x2510b10, C4<0>, C4<0>; -L_0x2510c60 .delay (20000,20000,20000) L_0x2510c60/d; -v0x240e0d0_0 .net "S", 0 0, L_0x2510e30; 1 drivers -v0x240e150_0 .alias "in0", 0 0, v0x240ef20_0; -v0x240e1f0_0 .alias "in1", 0 0, v0x240ec60_0; -v0x240e290_0 .net "nS", 0 0, L_0x2510900; 1 drivers -v0x240e310_0 .net "out0", 0 0, L_0x25109c0; 1 drivers -v0x240e3b0_0 .net "out1", 0 0, L_0x2510b10; 1 drivers -v0x240e490_0 .alias "outfinal", 0 0, v0x240eea0_0; -S_0x240cab0 .scope generate, "orbits[20]" "orbits[20]" 2 196, 2 196, S_0x23d9540; - .timescale -9 -12; -P_0x240c7c8 .param/l "i" 2 196, +C4<010100>; -S_0x240cbe0 .scope module, "attempt" "OrNorXor" 2 198, 2 64, S_0x240cab0; - .timescale -9 -12; -L_0x250fd10/d .functor NOR 1, L_0x2511010, L_0x25110b0, C4<0>, C4<0>; -L_0x250fd10 .delay (10000,10000,10000) L_0x250fd10/d; -L_0x25111e0/d .functor NOT 1, L_0x250fd10, C4<0>, C4<0>, C4<0>; -L_0x25111e0 .delay (10000,10000,10000) L_0x25111e0/d; -L_0x25112f0/d .functor NAND 1, L_0x2511010, L_0x25110b0, C4<1>, C4<1>; -L_0x25112f0 .delay (10000,10000,10000) L_0x25112f0/d; -L_0x2511450/d .functor NAND 1, L_0x25112f0, L_0x25111e0, C4<1>, C4<1>; -L_0x2511450 .delay (10000,10000,10000) L_0x2511450/d; -L_0x2511560/d .functor NOT 1, L_0x2511450, C4<0>, C4<0>, C4<0>; -L_0x2511560 .delay (10000,10000,10000) L_0x2511560/d; -v0x240d790_0 .net "A", 0 0, L_0x2511010; 1 drivers -v0x240d830_0 .net "AnandB", 0 0, L_0x25112f0; 1 drivers -v0x240d8d0_0 .net "AnorB", 0 0, L_0x250fd10; 1 drivers -v0x240d950_0 .net "AorB", 0 0, L_0x25111e0; 1 drivers -v0x240d9d0_0 .net "AxorB", 0 0, L_0x2511560; 1 drivers -v0x240da50_0 .net "B", 0 0, L_0x25110b0; 1 drivers -v0x240db10_0 .alias "Command", 2 0, v0x2463430_0; -v0x240db90_0 .net "OrNorXorOut", 0 0, L_0x2511f60; 1 drivers -v0x240dc10_0 .net "XorNor", 0 0, L_0x25119e0; 1 drivers -v0x240dce0_0 .net "nXor", 0 0, L_0x2511450; 1 drivers -L_0x2511b60 .part C4, 2, 1; -L_0x2512130 .part C4, 0, 1; -S_0x240d220 .scope module, "mux0" "TwoInMux" 2 83, 2 8, S_0x240cbe0; - .timescale -9 -12; -L_0x25116c0/d .functor NOT 1, L_0x2511b60, C4<0>, C4<0>, C4<0>; -L_0x25116c0 .delay (10000,10000,10000) L_0x25116c0/d; -L_0x2511780/d .functor AND 1, L_0x2511560, L_0x25116c0, C4<1>, C4<1>; -L_0x2511780 .delay (20000,20000,20000) L_0x2511780/d; -L_0x2511890/d .functor AND 1, L_0x250fd10, L_0x2511b60, C4<1>, C4<1>; -L_0x2511890 .delay (20000,20000,20000) L_0x2511890/d; -L_0x25119e0/d .functor OR 1, L_0x2511780, L_0x2511890, C4<0>, C4<0>; -L_0x25119e0 .delay (20000,20000,20000) L_0x25119e0/d; -v0x240d310_0 .net "S", 0 0, L_0x2511b60; 1 drivers -v0x240d3d0_0 .alias "in0", 0 0, v0x240d9d0_0; -v0x240d470_0 .alias "in1", 0 0, v0x240d8d0_0; -v0x240d510_0 .net "nS", 0 0, L_0x25116c0; 1 drivers -v0x240d590_0 .net "out0", 0 0, L_0x2511780; 1 drivers -v0x240d630_0 .net "out1", 0 0, L_0x2511890; 1 drivers -v0x240d710_0 .alias "outfinal", 0 0, v0x240dc10_0; -S_0x240ccd0 .scope module, "mux1" "TwoInMux" 2 84, 2 8, S_0x240cbe0; - .timescale -9 -12; -L_0x2511c00/d .functor NOT 1, L_0x2512130, C4<0>, C4<0>, C4<0>; -L_0x2511c00 .delay (10000,10000,10000) L_0x2511c00/d; -L_0x2511cc0/d .functor AND 1, L_0x25119e0, L_0x2511c00, C4<1>, C4<1>; -L_0x2511cc0 .delay (20000,20000,20000) L_0x2511cc0/d; -L_0x2511e10/d .functor AND 1, L_0x25111e0, L_0x2512130, C4<1>, C4<1>; -L_0x2511e10 .delay (20000,20000,20000) L_0x2511e10/d; -L_0x2511f60/d .functor OR 1, L_0x2511cc0, L_0x2511e10, C4<0>, C4<0>; -L_0x2511f60 .delay (20000,20000,20000) L_0x2511f60/d; -v0x240cdc0_0 .net "S", 0 0, L_0x2512130; 1 drivers -v0x240ce40_0 .alias "in0", 0 0, v0x240dc10_0; -v0x240cee0_0 .alias "in1", 0 0, v0x240d950_0; -v0x240cf80_0 .net "nS", 0 0, L_0x2511c00; 1 drivers -v0x240d000_0 .net "out0", 0 0, L_0x2511cc0; 1 drivers -v0x240d0a0_0 .net "out1", 0 0, L_0x2511e10; 1 drivers -v0x240d180_0 .alias "outfinal", 0 0, v0x240db90_0; -S_0x240b7a0 .scope generate, "orbits[21]" "orbits[21]" 2 196, 2 196, S_0x23d9540; - .timescale -9 -12; -P_0x240b4b8 .param/l "i" 2 196, +C4<010101>; -S_0x240b8d0 .scope module, "attempt" "OrNorXor" 2 198, 2 64, S_0x240b7a0; - .timescale -9 -12; -L_0x2511150/d .functor NOR 1, L_0x2513580, L_0x2512270, C4<0>, C4<0>; -L_0x2511150 .delay (10000,10000,10000) L_0x2511150/d; -L_0x25124f0/d .functor NOT 1, L_0x2511150, C4<0>, C4<0>, C4<0>; -L_0x25124f0 .delay (10000,10000,10000) L_0x25124f0/d; -L_0x2512600/d .functor NAND 1, L_0x2513580, L_0x2512270, C4<1>, C4<1>; -L_0x2512600 .delay (10000,10000,10000) L_0x2512600/d; -L_0x2512760/d .functor NAND 1, L_0x2512600, L_0x25124f0, C4<1>, C4<1>; -L_0x2512760 .delay (10000,10000,10000) L_0x2512760/d; -L_0x2512870/d .functor NOT 1, L_0x2512760, C4<0>, C4<0>, C4<0>; -L_0x2512870 .delay (10000,10000,10000) L_0x2512870/d; -v0x240c480_0 .net "A", 0 0, L_0x2513580; 1 drivers -v0x240c520_0 .net "AnandB", 0 0, L_0x2512600; 1 drivers -v0x240c5c0_0 .net "AnorB", 0 0, L_0x2511150; 1 drivers -v0x240c640_0 .net "AorB", 0 0, L_0x25124f0; 1 drivers -v0x240c6c0_0 .net "AxorB", 0 0, L_0x2512870; 1 drivers -v0x240c740_0 .net "B", 0 0, L_0x2512270; 1 drivers -v0x240c800_0 .alias "Command", 2 0, v0x2463430_0; -v0x240c880_0 .net "OrNorXorOut", 0 0, L_0x2513270; 1 drivers -v0x240c900_0 .net "XorNor", 0 0, L_0x2512cf0; 1 drivers -v0x240c9d0_0 .net "nXor", 0 0, L_0x2512760; 1 drivers -L_0x2512e70 .part C4, 2, 1; -L_0x2513440 .part C4, 0, 1; -S_0x240bf10 .scope module, "mux0" "TwoInMux" 2 83, 2 8, S_0x240b8d0; - .timescale -9 -12; -L_0x25129d0/d .functor NOT 1, L_0x2512e70, C4<0>, C4<0>, C4<0>; -L_0x25129d0 .delay (10000,10000,10000) L_0x25129d0/d; -L_0x2512a90/d .functor AND 1, L_0x2512870, L_0x25129d0, C4<1>, C4<1>; -L_0x2512a90 .delay (20000,20000,20000) L_0x2512a90/d; -L_0x2512ba0/d .functor AND 1, L_0x2511150, L_0x2512e70, C4<1>, C4<1>; -L_0x2512ba0 .delay (20000,20000,20000) L_0x2512ba0/d; -L_0x2512cf0/d .functor OR 1, L_0x2512a90, L_0x2512ba0, C4<0>, C4<0>; -L_0x2512cf0 .delay (20000,20000,20000) L_0x2512cf0/d; -v0x240c000_0 .net "S", 0 0, L_0x2512e70; 1 drivers -v0x240c0c0_0 .alias "in0", 0 0, v0x240c6c0_0; -v0x240c160_0 .alias "in1", 0 0, v0x240c5c0_0; -v0x240c200_0 .net "nS", 0 0, L_0x25129d0; 1 drivers -v0x240c280_0 .net "out0", 0 0, L_0x2512a90; 1 drivers -v0x240c320_0 .net "out1", 0 0, L_0x2512ba0; 1 drivers -v0x240c400_0 .alias "outfinal", 0 0, v0x240c900_0; -S_0x240b9c0 .scope module, "mux1" "TwoInMux" 2 84, 2 8, S_0x240b8d0; - .timescale -9 -12; -L_0x2512f10/d .functor NOT 1, L_0x2513440, C4<0>, C4<0>, C4<0>; -L_0x2512f10 .delay (10000,10000,10000) L_0x2512f10/d; -L_0x2512fd0/d .functor AND 1, L_0x2512cf0, L_0x2512f10, C4<1>, C4<1>; -L_0x2512fd0 .delay (20000,20000,20000) L_0x2512fd0/d; -L_0x2513120/d .functor AND 1, L_0x25124f0, L_0x2513440, C4<1>, C4<1>; -L_0x2513120 .delay (20000,20000,20000) L_0x2513120/d; -L_0x2513270/d .functor OR 1, L_0x2512fd0, L_0x2513120, C4<0>, C4<0>; -L_0x2513270 .delay (20000,20000,20000) L_0x2513270/d; -v0x240bab0_0 .net "S", 0 0, L_0x2513440; 1 drivers -v0x240bb30_0 .alias "in0", 0 0, v0x240c900_0; -v0x240bbd0_0 .alias "in1", 0 0, v0x240c640_0; -v0x240bc70_0 .net "nS", 0 0, L_0x2512f10; 1 drivers -v0x240bcf0_0 .net "out0", 0 0, L_0x2512fd0; 1 drivers -v0x240bd90_0 .net "out1", 0 0, L_0x2513120; 1 drivers -v0x240be70_0 .alias "outfinal", 0 0, v0x240c880_0; -S_0x240a490 .scope generate, "orbits[22]" "orbits[22]" 2 196, 2 196, S_0x23d9540; - .timescale -9 -12; -P_0x240a118 .param/l "i" 2 196, +C4<010110>; -S_0x240a5c0 .scope module, "attempt" "OrNorXor" 2 198, 2 64, S_0x240a490; - .timescale -9 -12; -L_0x2512310/d .functor NOR 1, L_0x2513620, L_0x25136c0, C4<0>, C4<0>; -L_0x2512310 .delay (10000,10000,10000) L_0x2512310/d; -L_0x2512400/d .functor NOT 1, L_0x2512310, C4<0>, C4<0>, C4<0>; -L_0x2512400 .delay (10000,10000,10000) L_0x2512400/d; -L_0x25138f0/d .functor NAND 1, L_0x2513620, L_0x25136c0, C4<1>, C4<1>; -L_0x25138f0 .delay (10000,10000,10000) L_0x25138f0/d; -L_0x2513a50/d .functor NAND 1, L_0x25138f0, L_0x2512400, C4<1>, C4<1>; -L_0x2513a50 .delay (10000,10000,10000) L_0x2513a50/d; -L_0x2513b60/d .functor NOT 1, L_0x2513a50, C4<0>, C4<0>, C4<0>; -L_0x2513b60 .delay (10000,10000,10000) L_0x2513b60/d; -v0x240b170_0 .net "A", 0 0, L_0x2513620; 1 drivers -v0x240b210_0 .net "AnandB", 0 0, L_0x25138f0; 1 drivers -v0x240b2b0_0 .net "AnorB", 0 0, L_0x2512310; 1 drivers -v0x240b330_0 .net "AorB", 0 0, L_0x2512400; 1 drivers -v0x240b3b0_0 .net "AxorB", 0 0, L_0x2513b60; 1 drivers -v0x240b430_0 .net "B", 0 0, L_0x25136c0; 1 drivers -v0x240b4f0_0 .alias "Command", 2 0, v0x2463430_0; -v0x240b570_0 .net "OrNorXorOut", 0 0, L_0x2514560; 1 drivers -v0x240b5f0_0 .net "XorNor", 0 0, L_0x2513fe0; 1 drivers -v0x240b6c0_0 .net "nXor", 0 0, L_0x2513a50; 1 drivers -L_0x2514160 .part C4, 2, 1; -L_0x2514730 .part C4, 0, 1; -S_0x240ac00 .scope module, "mux0" "TwoInMux" 2 83, 2 8, S_0x240a5c0; - .timescale -9 -12; -L_0x2513cc0/d .functor NOT 1, L_0x2514160, C4<0>, C4<0>, C4<0>; -L_0x2513cc0 .delay (10000,10000,10000) L_0x2513cc0/d; -L_0x2513d80/d .functor AND 1, L_0x2513b60, L_0x2513cc0, C4<1>, C4<1>; -L_0x2513d80 .delay (20000,20000,20000) L_0x2513d80/d; -L_0x2513e90/d .functor AND 1, L_0x2512310, L_0x2514160, C4<1>, C4<1>; -L_0x2513e90 .delay (20000,20000,20000) L_0x2513e90/d; -L_0x2513fe0/d .functor OR 1, L_0x2513d80, L_0x2513e90, C4<0>, C4<0>; -L_0x2513fe0 .delay (20000,20000,20000) L_0x2513fe0/d; -v0x240acf0_0 .net "S", 0 0, L_0x2514160; 1 drivers -v0x240adb0_0 .alias "in0", 0 0, v0x240b3b0_0; -v0x240ae50_0 .alias "in1", 0 0, v0x240b2b0_0; -v0x240aef0_0 .net "nS", 0 0, L_0x2513cc0; 1 drivers -v0x240af70_0 .net "out0", 0 0, L_0x2513d80; 1 drivers -v0x240b010_0 .net "out1", 0 0, L_0x2513e90; 1 drivers -v0x240b0f0_0 .alias "outfinal", 0 0, v0x240b5f0_0; -S_0x240a6b0 .scope module, "mux1" "TwoInMux" 2 84, 2 8, S_0x240a5c0; - .timescale -9 -12; -L_0x2514200/d .functor NOT 1, L_0x2514730, C4<0>, C4<0>, C4<0>; -L_0x2514200 .delay (10000,10000,10000) L_0x2514200/d; -L_0x25142c0/d .functor AND 1, L_0x2513fe0, L_0x2514200, C4<1>, C4<1>; -L_0x25142c0 .delay (20000,20000,20000) L_0x25142c0/d; -L_0x2514410/d .functor AND 1, L_0x2512400, L_0x2514730, C4<1>, C4<1>; -L_0x2514410 .delay (20000,20000,20000) L_0x2514410/d; -L_0x2514560/d .functor OR 1, L_0x25142c0, L_0x2514410, C4<0>, C4<0>; -L_0x2514560 .delay (20000,20000,20000) L_0x2514560/d; -v0x240a7a0_0 .net "S", 0 0, L_0x2514730; 1 drivers -v0x240a820_0 .alias "in0", 0 0, v0x240b5f0_0; -v0x240a8c0_0 .alias "in1", 0 0, v0x240b330_0; -v0x240a960_0 .net "nS", 0 0, L_0x2514200; 1 drivers -v0x240a9e0_0 .net "out0", 0 0, L_0x25142c0; 1 drivers -v0x240aa80_0 .net "out1", 0 0, L_0x2514410; 1 drivers -v0x240ab60_0 .alias "outfinal", 0 0, v0x240b570_0; -S_0x24090f0 .scope generate, "orbits[23]" "orbits[23]" 2 196, 2 196, S_0x23d9540; - .timescale -9 -12; -P_0x2408e08 .param/l "i" 2 196, +C4<010111>; -S_0x2409220 .scope module, "attempt" "OrNorXor" 2 198, 2 64, S_0x24090f0; - .timescale -9 -12; -L_0x2513760/d .functor NOR 1, L_0x2515b70, L_0x2514870, C4<0>, C4<0>; -L_0x2513760 .delay (10000,10000,10000) L_0x2513760/d; -L_0x2514ae0/d .functor NOT 1, L_0x2513760, C4<0>, C4<0>, C4<0>; -L_0x2514ae0 .delay (10000,10000,10000) L_0x2514ae0/d; -L_0x2514bf0/d .functor NAND 1, L_0x2515b70, L_0x2514870, C4<1>, C4<1>; -L_0x2514bf0 .delay (10000,10000,10000) L_0x2514bf0/d; -L_0x2514d50/d .functor NAND 1, L_0x2514bf0, L_0x2514ae0, C4<1>, C4<1>; -L_0x2514d50 .delay (10000,10000,10000) L_0x2514d50/d; -L_0x2514e60/d .functor NOT 1, L_0x2514d50, C4<0>, C4<0>, C4<0>; -L_0x2514e60 .delay (10000,10000,10000) L_0x2514e60/d; -v0x2409dd0_0 .net "A", 0 0, L_0x2515b70; 1 drivers -v0x2409e70_0 .net "AnandB", 0 0, L_0x2514bf0; 1 drivers -v0x2409f10_0 .net "AnorB", 0 0, L_0x2513760; 1 drivers -v0x2409f90_0 .net "AorB", 0 0, L_0x2514ae0; 1 drivers -v0x240a010_0 .net "AxorB", 0 0, L_0x2514e60; 1 drivers -v0x240a090_0 .net "B", 0 0, L_0x2514870; 1 drivers -v0x240a150_0 .alias "Command", 2 0, v0x2463430_0; -v0x2405790_0 .net "OrNorXorOut", 0 0, L_0x2515860; 1 drivers -v0x240a2e0_0 .net "XorNor", 0 0, L_0x25152e0; 1 drivers -v0x240a3b0_0 .net "nXor", 0 0, L_0x2514d50; 1 drivers -L_0x2515460 .part C4, 2, 1; -L_0x2515a30 .part C4, 0, 1; -S_0x2409860 .scope module, "mux0" "TwoInMux" 2 83, 2 8, S_0x2409220; - .timescale -9 -12; -L_0x2514fc0/d .functor NOT 1, L_0x2515460, C4<0>, C4<0>, C4<0>; -L_0x2514fc0 .delay (10000,10000,10000) L_0x2514fc0/d; -L_0x2515080/d .functor AND 1, L_0x2514e60, L_0x2514fc0, C4<1>, C4<1>; -L_0x2515080 .delay (20000,20000,20000) L_0x2515080/d; -L_0x2515190/d .functor AND 1, L_0x2513760, L_0x2515460, C4<1>, C4<1>; -L_0x2515190 .delay (20000,20000,20000) L_0x2515190/d; -L_0x25152e0/d .functor OR 1, L_0x2515080, L_0x2515190, C4<0>, C4<0>; -L_0x25152e0 .delay (20000,20000,20000) L_0x25152e0/d; -v0x2409950_0 .net "S", 0 0, L_0x2515460; 1 drivers -v0x2409a10_0 .alias "in0", 0 0, v0x240a010_0; -v0x2409ab0_0 .alias "in1", 0 0, v0x2409f10_0; -v0x2409b50_0 .net "nS", 0 0, L_0x2514fc0; 1 drivers -v0x2409bd0_0 .net "out0", 0 0, L_0x2515080; 1 drivers -v0x2409c70_0 .net "out1", 0 0, L_0x2515190; 1 drivers -v0x2409d50_0 .alias "outfinal", 0 0, v0x240a2e0_0; -S_0x2409310 .scope module, "mux1" "TwoInMux" 2 84, 2 8, S_0x2409220; - .timescale -9 -12; -L_0x2515500/d .functor NOT 1, L_0x2515a30, C4<0>, C4<0>, C4<0>; -L_0x2515500 .delay (10000,10000,10000) L_0x2515500/d; -L_0x25155c0/d .functor AND 1, L_0x25152e0, L_0x2515500, C4<1>, C4<1>; -L_0x25155c0 .delay (20000,20000,20000) L_0x25155c0/d; -L_0x2515710/d .functor AND 1, L_0x2514ae0, L_0x2515a30, C4<1>, C4<1>; -L_0x2515710 .delay (20000,20000,20000) L_0x2515710/d; -L_0x2515860/d .functor OR 1, L_0x25155c0, L_0x2515710, C4<0>, C4<0>; -L_0x2515860 .delay (20000,20000,20000) L_0x2515860/d; -v0x2409400_0 .net "S", 0 0, L_0x2515a30; 1 drivers -v0x2409480_0 .alias "in0", 0 0, v0x240a2e0_0; -v0x2409520_0 .alias "in1", 0 0, v0x2409f90_0; -v0x24095c0_0 .net "nS", 0 0, L_0x2515500; 1 drivers -v0x2409640_0 .net "out0", 0 0, L_0x25155c0; 1 drivers -v0x24096e0_0 .net "out1", 0 0, L_0x2515710; 1 drivers -v0x24097c0_0 .alias "outfinal", 0 0, v0x2405790_0; -S_0x2407de0 .scope generate, "orbits[24]" "orbits[24]" 2 196, 2 196, S_0x23d9540; - .timescale -9 -12; -P_0x2407af8 .param/l "i" 2 196, +C4<011000>; -S_0x2407f10 .scope module, "attempt" "OrNorXor" 2 198, 2 64, S_0x2407de0; - .timescale -9 -12; -L_0x2514910/d .functor NOR 1, L_0x2515c10, L_0x2515cb0, C4<0>, C4<0>; -L_0x2514910 .delay (10000,10000,10000) L_0x2514910/d; -L_0x2514a00/d .functor NOT 1, L_0x2514910, C4<0>, C4<0>, C4<0>; -L_0x2514a00 .delay (10000,10000,10000) L_0x2514a00/d; -L_0x2515ef0/d .functor NAND 1, L_0x2515c10, L_0x2515cb0, C4<1>, C4<1>; -L_0x2515ef0 .delay (10000,10000,10000) L_0x2515ef0/d; -L_0x2516050/d .functor NAND 1, L_0x2515ef0, L_0x2514a00, C4<1>, C4<1>; -L_0x2516050 .delay (10000,10000,10000) L_0x2516050/d; -L_0x2516160/d .functor NOT 1, L_0x2516050, C4<0>, C4<0>, C4<0>; -L_0x2516160 .delay (10000,10000,10000) L_0x2516160/d; -v0x2408ac0_0 .net "A", 0 0, L_0x2515c10; 1 drivers -v0x2408b60_0 .net "AnandB", 0 0, L_0x2515ef0; 1 drivers -v0x2408c00_0 .net "AnorB", 0 0, L_0x2514910; 1 drivers -v0x2408c80_0 .net "AorB", 0 0, L_0x2514a00; 1 drivers -v0x2408d00_0 .net "AxorB", 0 0, L_0x2516160; 1 drivers -v0x2408d80_0 .net "B", 0 0, L_0x2515cb0; 1 drivers -v0x2408e40_0 .alias "Command", 2 0, v0x2463430_0; -v0x2408ec0_0 .net "OrNorXorOut", 0 0, L_0x2516b60; 1 drivers -v0x2408f40_0 .net "XorNor", 0 0, L_0x25165e0; 1 drivers -v0x2409010_0 .net "nXor", 0 0, L_0x2516050; 1 drivers -L_0x2516760 .part C4, 2, 1; -L_0x2516d30 .part C4, 0, 1; -S_0x2408550 .scope module, "mux0" "TwoInMux" 2 83, 2 8, S_0x2407f10; - .timescale -9 -12; -L_0x25162c0/d .functor NOT 1, L_0x2516760, C4<0>, C4<0>, C4<0>; -L_0x25162c0 .delay (10000,10000,10000) L_0x25162c0/d; -L_0x2516380/d .functor AND 1, L_0x2516160, L_0x25162c0, C4<1>, C4<1>; -L_0x2516380 .delay (20000,20000,20000) L_0x2516380/d; -L_0x2516490/d .functor AND 1, L_0x2514910, L_0x2516760, C4<1>, C4<1>; -L_0x2516490 .delay (20000,20000,20000) L_0x2516490/d; -L_0x25165e0/d .functor OR 1, L_0x2516380, L_0x2516490, C4<0>, C4<0>; -L_0x25165e0 .delay (20000,20000,20000) L_0x25165e0/d; -v0x2408640_0 .net "S", 0 0, L_0x2516760; 1 drivers -v0x2408700_0 .alias "in0", 0 0, v0x2408d00_0; -v0x24087a0_0 .alias "in1", 0 0, v0x2408c00_0; -v0x2408840_0 .net "nS", 0 0, L_0x25162c0; 1 drivers -v0x24088c0_0 .net "out0", 0 0, L_0x2516380; 1 drivers -v0x2408960_0 .net "out1", 0 0, L_0x2516490; 1 drivers -v0x2408a40_0 .alias "outfinal", 0 0, v0x2408f40_0; -S_0x2408000 .scope module, "mux1" "TwoInMux" 2 84, 2 8, S_0x2407f10; - .timescale -9 -12; -L_0x2516800/d .functor NOT 1, L_0x2516d30, C4<0>, C4<0>, C4<0>; -L_0x2516800 .delay (10000,10000,10000) L_0x2516800/d; -L_0x25168c0/d .functor AND 1, L_0x25165e0, L_0x2516800, C4<1>, C4<1>; -L_0x25168c0 .delay (20000,20000,20000) L_0x25168c0/d; -L_0x2516a10/d .functor AND 1, L_0x2514a00, L_0x2516d30, C4<1>, C4<1>; -L_0x2516a10 .delay (20000,20000,20000) L_0x2516a10/d; -L_0x2516b60/d .functor OR 1, L_0x25168c0, L_0x2516a10, C4<0>, C4<0>; -L_0x2516b60 .delay (20000,20000,20000) L_0x2516b60/d; -v0x24080f0_0 .net "S", 0 0, L_0x2516d30; 1 drivers -v0x2408170_0 .alias "in0", 0 0, v0x2408f40_0; -v0x2408210_0 .alias "in1", 0 0, v0x2408c80_0; -v0x24082b0_0 .net "nS", 0 0, L_0x2516800; 1 drivers -v0x2408330_0 .net "out0", 0 0, L_0x25168c0; 1 drivers -v0x24083d0_0 .net "out1", 0 0, L_0x2516a10; 1 drivers -v0x24084b0_0 .alias "outfinal", 0 0, v0x2408ec0_0; -S_0x2406ad0 .scope generate, "orbits[25]" "orbits[25]" 2 196, 2 196, S_0x23d9540; - .timescale -9 -12; -P_0x24067e8 .param/l "i" 2 196, +C4<011001>; -S_0x2406c00 .scope module, "attempt" "OrNorXor" 2 198, 2 64, S_0x2406ad0; - .timescale -9 -12; -L_0x2515d50/d .functor NOR 1, L_0x2518170, L_0x2516e70, C4<0>, C4<0>; -L_0x2515d50 .delay (10000,10000,10000) L_0x2515d50/d; -L_0x25170c0/d .functor NOT 1, L_0x2515d50, C4<0>, C4<0>, C4<0>; -L_0x25170c0 .delay (10000,10000,10000) L_0x25170c0/d; -L_0x25171f0/d .functor NAND 1, L_0x2518170, L_0x2516e70, C4<1>, C4<1>; -L_0x25171f0 .delay (10000,10000,10000) L_0x25171f0/d; -L_0x2517350/d .functor NAND 1, L_0x25171f0, L_0x25170c0, C4<1>, C4<1>; -L_0x2517350 .delay (10000,10000,10000) L_0x2517350/d; -L_0x2517460/d .functor NOT 1, L_0x2517350, C4<0>, C4<0>, C4<0>; -L_0x2517460 .delay (10000,10000,10000) L_0x2517460/d; -v0x24077b0_0 .net "A", 0 0, L_0x2518170; 1 drivers -v0x2407850_0 .net "AnandB", 0 0, L_0x25171f0; 1 drivers -v0x24078f0_0 .net "AnorB", 0 0, L_0x2515d50; 1 drivers -v0x2407970_0 .net "AorB", 0 0, L_0x25170c0; 1 drivers -v0x24079f0_0 .net "AxorB", 0 0, L_0x2517460; 1 drivers -v0x2407a70_0 .net "B", 0 0, L_0x2516e70; 1 drivers -v0x2407b30_0 .alias "Command", 2 0, v0x2463430_0; -v0x2407bb0_0 .net "OrNorXorOut", 0 0, L_0x2517e60; 1 drivers -v0x2407c30_0 .net "XorNor", 0 0, L_0x25178e0; 1 drivers -v0x2407d00_0 .net "nXor", 0 0, L_0x2517350; 1 drivers -L_0x2517a60 .part C4, 2, 1; -L_0x2518030 .part C4, 0, 1; -S_0x2407240 .scope module, "mux0" "TwoInMux" 2 83, 2 8, S_0x2406c00; - .timescale -9 -12; -L_0x25175c0/d .functor NOT 1, L_0x2517a60, C4<0>, C4<0>, C4<0>; -L_0x25175c0 .delay (10000,10000,10000) L_0x25175c0/d; -L_0x2517680/d .functor AND 1, L_0x2517460, L_0x25175c0, C4<1>, C4<1>; -L_0x2517680 .delay (20000,20000,20000) L_0x2517680/d; -L_0x2517790/d .functor AND 1, L_0x2515d50, L_0x2517a60, C4<1>, C4<1>; -L_0x2517790 .delay (20000,20000,20000) L_0x2517790/d; -L_0x25178e0/d .functor OR 1, L_0x2517680, L_0x2517790, C4<0>, C4<0>; -L_0x25178e0 .delay (20000,20000,20000) L_0x25178e0/d; -v0x2407330_0 .net "S", 0 0, L_0x2517a60; 1 drivers -v0x24073f0_0 .alias "in0", 0 0, v0x24079f0_0; -v0x2407490_0 .alias "in1", 0 0, v0x24078f0_0; -v0x2407530_0 .net "nS", 0 0, L_0x25175c0; 1 drivers -v0x24075b0_0 .net "out0", 0 0, L_0x2517680; 1 drivers -v0x2407650_0 .net "out1", 0 0, L_0x2517790; 1 drivers -v0x2407730_0 .alias "outfinal", 0 0, v0x2407c30_0; -S_0x2406cf0 .scope module, "mux1" "TwoInMux" 2 84, 2 8, S_0x2406c00; - .timescale -9 -12; -L_0x2517b00/d .functor NOT 1, L_0x2518030, C4<0>, C4<0>, C4<0>; -L_0x2517b00 .delay (10000,10000,10000) L_0x2517b00/d; -L_0x2517bc0/d .functor AND 1, L_0x25178e0, L_0x2517b00, C4<1>, C4<1>; -L_0x2517bc0 .delay (20000,20000,20000) L_0x2517bc0/d; -L_0x2517d10/d .functor AND 1, L_0x25170c0, L_0x2518030, C4<1>, C4<1>; -L_0x2517d10 .delay (20000,20000,20000) L_0x2517d10/d; -L_0x2517e60/d .functor OR 1, L_0x2517bc0, L_0x2517d10, C4<0>, C4<0>; -L_0x2517e60 .delay (20000,20000,20000) L_0x2517e60/d; -v0x2406de0_0 .net "S", 0 0, L_0x2518030; 1 drivers -v0x2406e60_0 .alias "in0", 0 0, v0x2407c30_0; -v0x2406f00_0 .alias "in1", 0 0, v0x2407970_0; -v0x2406fa0_0 .net "nS", 0 0, L_0x2517b00; 1 drivers -v0x2407020_0 .net "out0", 0 0, L_0x2517bc0; 1 drivers -v0x24070c0_0 .net "out1", 0 0, L_0x2517d10; 1 drivers -v0x24071a0_0 .alias "outfinal", 0 0, v0x2407bb0_0; -S_0x24059a0 .scope generate, "orbits[26]" "orbits[26]" 2 196, 2 196, S_0x23d9540; - .timescale -9 -12; -P_0x2308908 .param/l "i" 2 196, +C4<011010>; -S_0x2405a90 .scope module, "attempt" "OrNorXor" 2 198, 2 64, S_0x24059a0; - .timescale -9 -12; -L_0x2516f10/d .functor NOR 1, L_0x2518210, L_0x25182b0, C4<0>, C4<0>; -L_0x2516f10 .delay (10000,10000,10000) L_0x2516f10/d; -L_0x2517000/d .functor NOT 1, L_0x2516f10, C4<0>, C4<0>, C4<0>; -L_0x2517000 .delay (10000,10000,10000) L_0x2517000/d; -L_0x25184e0/d .functor NAND 1, L_0x2518210, L_0x25182b0, C4<1>, C4<1>; -L_0x25184e0 .delay (10000,10000,10000) L_0x25184e0/d; -L_0x2518640/d .functor NAND 1, L_0x25184e0, L_0x2517000, C4<1>, C4<1>; -L_0x2518640 .delay (10000,10000,10000) L_0x2518640/d; -L_0x2518750/d .functor NOT 1, L_0x2518640, C4<0>, C4<0>, C4<0>; -L_0x2518750 .delay (10000,10000,10000) L_0x2518750/d; -v0x24064a0_0 .net "A", 0 0, L_0x2518210; 1 drivers -v0x2406540_0 .net "AnandB", 0 0, L_0x25184e0; 1 drivers -v0x24065e0_0 .net "AnorB", 0 0, L_0x2516f10; 1 drivers -v0x2406660_0 .net "AorB", 0 0, L_0x2517000; 1 drivers -v0x24066e0_0 .net "AxorB", 0 0, L_0x2518750; 1 drivers -v0x2406760_0 .net "B", 0 0, L_0x25182b0; 1 drivers -v0x2406820_0 .alias "Command", 2 0, v0x2463430_0; -v0x24068a0_0 .net "OrNorXorOut", 0 0, L_0x2519170; 1 drivers -v0x2406920_0 .net "XorNor", 0 0, L_0x2518bf0; 1 drivers -v0x24069f0_0 .net "nXor", 0 0, L_0x2518640; 1 drivers -L_0x2518d70 .part C4, 2, 1; -L_0x2519340 .part C4, 0, 1; -S_0x2405ff0 .scope module, "mux0" "TwoInMux" 2 83, 2 8, S_0x2405a90; - .timescale -9 -12; -L_0x25188b0/d .functor NOT 1, L_0x2518d70, C4<0>, C4<0>, C4<0>; -L_0x25188b0 .delay (10000,10000,10000) L_0x25188b0/d; -L_0x2518970/d .functor AND 1, L_0x2518750, L_0x25188b0, C4<1>, C4<1>; -L_0x2518970 .delay (20000,20000,20000) L_0x2518970/d; -L_0x2518a80/d .functor AND 1, L_0x2516f10, L_0x2518d70, C4<1>, C4<1>; -L_0x2518a80 .delay (20000,20000,20000) L_0x2518a80/d; -L_0x2518bf0/d .functor OR 1, L_0x2518970, L_0x2518a80, C4<0>, C4<0>; -L_0x2518bf0 .delay (20000,20000,20000) L_0x2518bf0/d; -v0x24060e0_0 .net "S", 0 0, L_0x2518d70; 1 drivers -v0x2406160_0 .alias "in0", 0 0, v0x24066e0_0; -v0x24061e0_0 .alias "in1", 0 0, v0x24065e0_0; -v0x2406260_0 .net "nS", 0 0, L_0x25188b0; 1 drivers -v0x24062e0_0 .net "out0", 0 0, L_0x2518970; 1 drivers -v0x2406360_0 .net "out1", 0 0, L_0x2518a80; 1 drivers -v0x2406420_0 .alias "outfinal", 0 0, v0x2406920_0; -S_0x2405b80 .scope module, "mux1" "TwoInMux" 2 84, 2 8, S_0x2405a90; - .timescale -9 -12; -L_0x2518e10/d .functor NOT 1, L_0x2519340, C4<0>, C4<0>, C4<0>; -L_0x2518e10 .delay (10000,10000,10000) L_0x2518e10/d; -L_0x2518ed0/d .functor AND 1, L_0x2518bf0, L_0x2518e10, C4<1>, C4<1>; -L_0x2518ed0 .delay (20000,20000,20000) L_0x2518ed0/d; -L_0x2519020/d .functor AND 1, L_0x2517000, L_0x2519340, C4<1>, C4<1>; -L_0x2519020 .delay (20000,20000,20000) L_0x2519020/d; -L_0x2519170/d .functor OR 1, L_0x2518ed0, L_0x2519020, C4<0>, C4<0>; -L_0x2519170 .delay (20000,20000,20000) L_0x2519170/d; -v0x2405c70_0 .net "S", 0 0, L_0x2519340; 1 drivers -v0x2405cf0_0 .alias "in0", 0 0, v0x2406920_0; -v0x2405d70_0 .alias "in1", 0 0, v0x2406660_0; -v0x2405df0_0 .net "nS", 0 0, L_0x2518e10; 1 drivers -v0x2405e70_0 .net "out0", 0 0, L_0x2518ed0; 1 drivers -v0x2405ef0_0 .net "out1", 0 0, L_0x2519020; 1 drivers -v0x2405f70_0 .alias "outfinal", 0 0, v0x24068a0_0; -S_0x2404950 .scope generate, "orbits[27]" "orbits[27]" 2 196, 2 196, S_0x23d9540; - .timescale -9 -12; -P_0x22d5938 .param/l "i" 2 196, +C4<011011>; -S_0x2404a40 .scope module, "attempt" "OrNorXor" 2 198, 2 64, S_0x2404950; - .timescale -9 -12; -L_0x2518350/d .functor NOR 1, L_0x251a780, L_0x2519480, C4<0>, C4<0>; -L_0x2518350 .delay (10000,10000,10000) L_0x2518350/d; -L_0x2519700/d .functor NOT 1, L_0x2518350, C4<0>, C4<0>, C4<0>; -L_0x2519700 .delay (10000,10000,10000) L_0x2519700/d; -L_0x2519810/d .functor NAND 1, L_0x251a780, L_0x2519480, C4<1>, C4<1>; -L_0x2519810 .delay (10000,10000,10000) L_0x2519810/d; -L_0x2519970/d .functor NAND 1, L_0x2519810, L_0x2519700, C4<1>, C4<1>; -L_0x2519970 .delay (10000,10000,10000) L_0x2519970/d; -L_0x2519a80/d .functor NOT 1, L_0x2519970, C4<0>, C4<0>, C4<0>; -L_0x2519a80 .delay (10000,10000,10000) L_0x2519a80/d; -v0x2405410_0 .net "A", 0 0, L_0x251a780; 1 drivers -v0x2405490_0 .net "AnandB", 0 0, L_0x2519810; 1 drivers -v0x2405510_0 .net "AnorB", 0 0, L_0x2518350; 1 drivers -v0x2405590_0 .net "AorB", 0 0, L_0x2519700; 1 drivers -v0x2405610_0 .net "AxorB", 0 0, L_0x2519a80; 1 drivers -v0x2405690_0 .net "B", 0 0, L_0x2519480; 1 drivers -v0x2405710_0 .alias "Command", 2 0, v0x2463430_0; -v0x2405820_0 .net "OrNorXorOut", 0 0, L_0x251a470; 1 drivers -v0x24058a0_0 .net "XorNor", 0 0, L_0x2519f00; 1 drivers -v0x2405920_0 .net "nXor", 0 0, L_0x2519970; 1 drivers -L_0x251a080 .part C4, 2, 1; -L_0x251a640 .part C4, 0, 1; -S_0x2404fa0 .scope module, "mux0" "TwoInMux" 2 83, 2 8, S_0x2404a40; - .timescale -9 -12; -L_0x2519be0/d .functor NOT 1, L_0x251a080, C4<0>, C4<0>, C4<0>; -L_0x2519be0 .delay (10000,10000,10000) L_0x2519be0/d; -L_0x2519ca0/d .functor AND 1, L_0x2519a80, L_0x2519be0, C4<1>, C4<1>; -L_0x2519ca0 .delay (20000,20000,20000) L_0x2519ca0/d; -L_0x2519db0/d .functor AND 1, L_0x2518350, L_0x251a080, C4<1>, C4<1>; -L_0x2519db0 .delay (20000,20000,20000) L_0x2519db0/d; -L_0x2519f00/d .functor OR 1, L_0x2519ca0, L_0x2519db0, C4<0>, C4<0>; -L_0x2519f00 .delay (20000,20000,20000) L_0x2519f00/d; -v0x2405090_0 .net "S", 0 0, L_0x251a080; 1 drivers -v0x2405110_0 .alias "in0", 0 0, v0x2405610_0; -v0x2405190_0 .alias "in1", 0 0, v0x2405510_0; -v0x2405210_0 .net "nS", 0 0, L_0x2519be0; 1 drivers -v0x2405290_0 .net "out0", 0 0, L_0x2519ca0; 1 drivers -v0x2405310_0 .net "out1", 0 0, L_0x2519db0; 1 drivers -v0x2405390_0 .alias "outfinal", 0 0, v0x24058a0_0; -S_0x2404b30 .scope module, "mux1" "TwoInMux" 2 84, 2 8, S_0x2404a40; - .timescale -9 -12; -L_0x251a120/d .functor NOT 1, L_0x251a640, C4<0>, C4<0>, C4<0>; -L_0x251a120 .delay (10000,10000,10000) L_0x251a120/d; -L_0x251a1e0/d .functor AND 1, L_0x2519f00, L_0x251a120, C4<1>, C4<1>; -L_0x251a1e0 .delay (20000,20000,20000) L_0x251a1e0/d; -L_0x22ec750/d .functor AND 1, L_0x2519700, L_0x251a640, C4<1>, C4<1>; -L_0x22ec750 .delay (20000,20000,20000) L_0x22ec750/d; -L_0x251a470/d .functor OR 1, L_0x251a1e0, L_0x22ec750, C4<0>, C4<0>; -L_0x251a470 .delay (20000,20000,20000) L_0x251a470/d; -v0x2404c20_0 .net "S", 0 0, L_0x251a640; 1 drivers -v0x2404ca0_0 .alias "in0", 0 0, v0x24058a0_0; -v0x2404d20_0 .alias "in1", 0 0, v0x2405590_0; -v0x2404da0_0 .net "nS", 0 0, L_0x251a120; 1 drivers -v0x2404e20_0 .net "out0", 0 0, L_0x251a1e0; 1 drivers -v0x2404ea0_0 .net "out1", 0 0, L_0x22ec750; 1 drivers -v0x2404f20_0 .alias "outfinal", 0 0, v0x2405820_0; -S_0x2403990 .scope generate, "orbits[28]" "orbits[28]" 2 196, 2 196, S_0x23d9540; - .timescale -9 -12; -P_0x228a328 .param/l "i" 2 196, +C4<011100>; -S_0x2403a80 .scope module, "attempt" "OrNorXor" 2 198, 2 64, S_0x2403990; - .timescale -9 -12; -L_0x2519520/d .functor NOR 1, L_0x251a820, L_0x251a8c0, C4<0>, C4<0>; -L_0x2519520 .delay (10000,10000,10000) L_0x2519520/d; -L_0x2519610/d .functor NOT 1, L_0x2519520, C4<0>, C4<0>, C4<0>; -L_0x2519610 .delay (10000,10000,10000) L_0x2519610/d; -L_0x251ab00/d .functor NAND 1, L_0x251a820, L_0x251a8c0, C4<1>, C4<1>; -L_0x251ab00 .delay (10000,10000,10000) L_0x251ab00/d; -L_0x251ac60/d .functor NAND 1, L_0x251ab00, L_0x2519610, C4<1>, C4<1>; -L_0x251ac60 .delay (10000,10000,10000) L_0x251ac60/d; -L_0x251ad70/d .functor NOT 1, L_0x251ac60, C4<0>, C4<0>, C4<0>; -L_0x251ad70 .delay (10000,10000,10000) L_0x251ad70/d; -v0x2404450_0 .net "A", 0 0, L_0x251a820; 1 drivers -v0x24044d0_0 .net "AnandB", 0 0, L_0x251ab00; 1 drivers -v0x2404550_0 .net "AnorB", 0 0, L_0x2519520; 1 drivers -v0x24045d0_0 .net "AorB", 0 0, L_0x2519610; 1 drivers -v0x2404650_0 .net "AxorB", 0 0, L_0x251ad70; 1 drivers -v0x24046d0_0 .net "B", 0 0, L_0x251a8c0; 1 drivers -v0x2404750_0 .alias "Command", 2 0, v0x2463430_0; -v0x24047d0_0 .net "OrNorXorOut", 0 0, L_0x251b760; 1 drivers -v0x2404850_0 .net "XorNor", 0 0, L_0x251b1f0; 1 drivers -v0x24048d0_0 .net "nXor", 0 0, L_0x251ac60; 1 drivers -L_0x251b370 .part C4, 2, 1; -L_0x251b930 .part C4, 0, 1; -S_0x2403fe0 .scope module, "mux0" "TwoInMux" 2 83, 2 8, S_0x2403a80; - .timescale -9 -12; -L_0x251aed0/d .functor NOT 1, L_0x251b370, C4<0>, C4<0>, C4<0>; -L_0x251aed0 .delay (10000,10000,10000) L_0x251aed0/d; -L_0x251af90/d .functor AND 1, L_0x251ad70, L_0x251aed0, C4<1>, C4<1>; -L_0x251af90 .delay (20000,20000,20000) L_0x251af90/d; -L_0x251b0a0/d .functor AND 1, L_0x2519520, L_0x251b370, C4<1>, C4<1>; -L_0x251b0a0 .delay (20000,20000,20000) L_0x251b0a0/d; -L_0x251b1f0/d .functor OR 1, L_0x251af90, L_0x251b0a0, C4<0>, C4<0>; -L_0x251b1f0 .delay (20000,20000,20000) L_0x251b1f0/d; -v0x24040d0_0 .net "S", 0 0, L_0x251b370; 1 drivers -v0x2404150_0 .alias "in0", 0 0, v0x2404650_0; -v0x24041d0_0 .alias "in1", 0 0, v0x2404550_0; -v0x2404250_0 .net "nS", 0 0, L_0x251aed0; 1 drivers -v0x24042d0_0 .net "out0", 0 0, L_0x251af90; 1 drivers -v0x2404350_0 .net "out1", 0 0, L_0x251b0a0; 1 drivers -v0x24043d0_0 .alias "outfinal", 0 0, v0x2404850_0; -S_0x2403b70 .scope module, "mux1" "TwoInMux" 2 84, 2 8, S_0x2403a80; - .timescale -9 -12; -L_0x251b410/d .functor NOT 1, L_0x251b930, C4<0>, C4<0>, C4<0>; -L_0x251b410 .delay (10000,10000,10000) L_0x251b410/d; -L_0x251b4d0/d .functor AND 1, L_0x251b1f0, L_0x251b410, C4<1>, C4<1>; -L_0x251b4d0 .delay (20000,20000,20000) L_0x251b4d0/d; -L_0x22c76b0/d .functor AND 1, L_0x2519610, L_0x251b930, C4<1>, C4<1>; -L_0x22c76b0 .delay (20000,20000,20000) L_0x22c76b0/d; -L_0x251b760/d .functor OR 1, L_0x251b4d0, L_0x22c76b0, C4<0>, C4<0>; -L_0x251b760 .delay (20000,20000,20000) L_0x251b760/d; -v0x2403c60_0 .net "S", 0 0, L_0x251b930; 1 drivers -v0x2403ce0_0 .alias "in0", 0 0, v0x2404850_0; -v0x2403d60_0 .alias "in1", 0 0, v0x24045d0_0; -v0x2403de0_0 .net "nS", 0 0, L_0x251b410; 1 drivers -v0x2403e60_0 .net "out0", 0 0, L_0x251b4d0; 1 drivers -v0x2403ee0_0 .net "out1", 0 0, L_0x22c76b0; 1 drivers -v0x2403f60_0 .alias "outfinal", 0 0, v0x24047d0_0; -S_0x24029d0 .scope generate, "orbits[29]" "orbits[29]" 2 196, 2 196, S_0x23d9540; - .timescale -9 -12; -P_0x23cb8b8 .param/l "i" 2 196, +C4<011101>; -S_0x2402ac0 .scope module, "attempt" "OrNorXor" 2 198, 2 64, S_0x24029d0; - .timescale -9 -12; -L_0x251a960/d .functor NOR 1, L_0x251cdf0, L_0x251ba70, C4<0>, C4<0>; -L_0x251a960 .delay (10000,10000,10000) L_0x251a960/d; -L_0x251bd20/d .functor NOT 1, L_0x251a960, C4<0>, C4<0>, C4<0>; -L_0x251bd20 .delay (10000,10000,10000) L_0x251bd20/d; -L_0x251be10/d .functor NAND 1, L_0x251cdf0, L_0x251ba70, C4<1>, C4<1>; -L_0x251be10 .delay (10000,10000,10000) L_0x251be10/d; -L_0x251bf70/d .functor NAND 1, L_0x251be10, L_0x251bd20, C4<1>, C4<1>; -L_0x251bf70 .delay (10000,10000,10000) L_0x251bf70/d; -L_0x251c080/d .functor NOT 1, L_0x251bf70, C4<0>, C4<0>, C4<0>; -L_0x251c080 .delay (10000,10000,10000) L_0x251c080/d; -v0x2403490_0 .net "A", 0 0, L_0x251cdf0; 1 drivers -v0x2403510_0 .net "AnandB", 0 0, L_0x251be10; 1 drivers -v0x2403590_0 .net "AnorB", 0 0, L_0x251a960; 1 drivers -v0x2403610_0 .net "AorB", 0 0, L_0x251bd20; 1 drivers -v0x2403690_0 .net "AxorB", 0 0, L_0x251c080; 1 drivers -v0x2403710_0 .net "B", 0 0, L_0x251ba70; 1 drivers -v0x2403790_0 .alias "Command", 2 0, v0x2463430_0; -v0x2403810_0 .net "OrNorXorOut", 0 0, L_0x251cae0; 1 drivers -v0x2403890_0 .net "XorNor", 0 0, L_0x251c500; 1 drivers -v0x2403910_0 .net "nXor", 0 0, L_0x251bf70; 1 drivers -L_0x251c680 .part C4, 2, 1; -L_0x251ccb0 .part C4, 0, 1; -S_0x2403020 .scope module, "mux0" "TwoInMux" 2 83, 2 8, S_0x2402ac0; - .timescale -9 -12; -L_0x251c1e0/d .functor NOT 1, L_0x251c680, C4<0>, C4<0>, C4<0>; -L_0x251c1e0 .delay (10000,10000,10000) L_0x251c1e0/d; -L_0x251c2a0/d .functor AND 1, L_0x251c080, L_0x251c1e0, C4<1>, C4<1>; -L_0x251c2a0 .delay (20000,20000,20000) L_0x251c2a0/d; -L_0x251c3b0/d .functor AND 1, L_0x251a960, L_0x251c680, C4<1>, C4<1>; -L_0x251c3b0 .delay (20000,20000,20000) L_0x251c3b0/d; -L_0x251c500/d .functor OR 1, L_0x251c2a0, L_0x251c3b0, C4<0>, C4<0>; -L_0x251c500 .delay (20000,20000,20000) L_0x251c500/d; -v0x2403110_0 .net "S", 0 0, L_0x251c680; 1 drivers -v0x2403190_0 .alias "in0", 0 0, v0x2403690_0; -v0x2403210_0 .alias "in1", 0 0, v0x2403590_0; -v0x2403290_0 .net "nS", 0 0, L_0x251c1e0; 1 drivers -v0x2403310_0 .net "out0", 0 0, L_0x251c2a0; 1 drivers -v0x2403390_0 .net "out1", 0 0, L_0x251c3b0; 1 drivers -v0x2403410_0 .alias "outfinal", 0 0, v0x2403890_0; -S_0x2402bb0 .scope module, "mux1" "TwoInMux" 2 84, 2 8, S_0x2402ac0; - .timescale -9 -12; -L_0x251c720/d .functor NOT 1, L_0x251ccb0, C4<0>, C4<0>, C4<0>; -L_0x251c720 .delay (10000,10000,10000) L_0x251c720/d; -L_0x251c800/d .functor AND 1, L_0x251c500, L_0x251c720, C4<1>, C4<1>; -L_0x251c800 .delay (20000,20000,20000) L_0x251c800/d; -L_0x251c970/d .functor AND 1, L_0x251bd20, L_0x251ccb0, C4<1>, C4<1>; -L_0x251c970 .delay (20000,20000,20000) L_0x251c970/d; -L_0x251cae0/d .functor OR 1, L_0x251c800, L_0x251c970, C4<0>, C4<0>; -L_0x251cae0 .delay (20000,20000,20000) L_0x251cae0/d; -v0x2402ca0_0 .net "S", 0 0, L_0x251ccb0; 1 drivers -v0x2402d20_0 .alias "in0", 0 0, v0x2403890_0; -v0x2402da0_0 .alias "in1", 0 0, v0x2403610_0; -v0x2402e20_0 .net "nS", 0 0, L_0x251c720; 1 drivers -v0x2402ea0_0 .net "out0", 0 0, L_0x251c800; 1 drivers -v0x2402f20_0 .net "out1", 0 0, L_0x251c970; 1 drivers -v0x2402fa0_0 .alias "outfinal", 0 0, v0x2403810_0; -S_0x2101cb0 .scope generate, "orbits[30]" "orbits[30]" 2 196, 2 196, S_0x23d9540; - .timescale -9 -12; -P_0x23bff88 .param/l "i" 2 196, +C4<011110>; -S_0x20ff610 .scope module, "attempt" "OrNorXor" 2 198, 2 64, S_0x2101cb0; - .timescale -9 -12; -L_0x251bb10/d .functor NOR 1, L_0x251ce90, L_0x251cf30, C4<0>, C4<0>; -L_0x251bb10 .delay (10000,10000,10000) L_0x251bb10/d; -L_0x251bc00/d .functor NOT 1, L_0x251bb10, C4<0>, C4<0>, C4<0>; -L_0x251bc00 .delay (10000,10000,10000) L_0x251bc00/d; -L_0x251bcc0/d .functor NAND 1, L_0x251ce90, L_0x251cf30, C4<1>, C4<1>; -L_0x251bcc0 .delay (10000,10000,10000) L_0x251bcc0/d; -L_0x251d2c0/d .functor NAND 1, L_0x251bcc0, L_0x251bc00, C4<1>, C4<1>; -L_0x251d2c0 .delay (10000,10000,10000) L_0x251d2c0/d; -L_0x251d3d0/d .functor NOT 1, L_0x251d2c0, C4<0>, C4<0>, C4<0>; -L_0x251d3d0 .delay (10000,10000,10000) L_0x251d3d0/d; -v0x220f870_0 .net "A", 0 0, L_0x251ce90; 1 drivers -v0x220f910_0 .net "AnandB", 0 0, L_0x251bcc0; 1 drivers -v0x220f9b0_0 .net "AnorB", 0 0, L_0x251bb10; 1 drivers -v0x220fa30_0 .net "AorB", 0 0, L_0x251bc00; 1 drivers -v0x220fab0_0 .net "AxorB", 0 0, L_0x251d3d0; 1 drivers -v0x220fb30_0 .net "B", 0 0, L_0x251cf30; 1 drivers -v0x24027d0_0 .alias "Command", 2 0, v0x2463430_0; -v0x2402850_0 .net "OrNorXorOut", 0 0, L_0x251ddf0; 1 drivers -v0x24028d0_0 .net "XorNor", 0 0, L_0x251d850; 1 drivers -v0x2402950_0 .net "nXor", 0 0, L_0x251d2c0; 1 drivers -L_0x251d9d0 .part C4, 2, 1; -L_0x251dfc0 .part C4, 0, 1; -S_0x20c5730 .scope module, "mux0" "TwoInMux" 2 83, 2 8, S_0x20ff610; - .timescale -9 -12; -L_0x251d530/d .functor NOT 1, L_0x251d9d0, C4<0>, C4<0>, C4<0>; -L_0x251d530 .delay (10000,10000,10000) L_0x251d530/d; -L_0x251d5f0/d .functor AND 1, L_0x251d3d0, L_0x251d530, C4<1>, C4<1>; -L_0x251d5f0 .delay (20000,20000,20000) L_0x251d5f0/d; -L_0x251d700/d .functor AND 1, L_0x251bb10, L_0x251d9d0, C4<1>, C4<1>; -L_0x251d700 .delay (20000,20000,20000) L_0x251d700/d; -L_0x251d850/d .functor OR 1, L_0x251d5f0, L_0x251d700, C4<0>, C4<0>; -L_0x251d850 .delay (20000,20000,20000) L_0x251d850/d; -v0x20c5820_0 .net "S", 0 0, L_0x251d9d0; 1 drivers -v0x21174a0_0 .alias "in0", 0 0, v0x220fab0_0; -v0x2117540_0 .alias "in1", 0 0, v0x220f9b0_0; -v0x21175e0_0 .net "nS", 0 0, L_0x251d530; 1 drivers -v0x2117660_0 .net "out0", 0 0, L_0x251d5f0; 1 drivers -v0x220f750_0 .net "out1", 0 0, L_0x251d700; 1 drivers -v0x220f7f0_0 .alias "outfinal", 0 0, v0x24028d0_0; -S_0x20ff700 .scope module, "mux1" "TwoInMux" 2 84, 2 8, S_0x20ff610; - .timescale -9 -12; -L_0x251da70/d .functor NOT 1, L_0x251dfc0, C4<0>, C4<0>, C4<0>; -L_0x251da70 .delay (10000,10000,10000) L_0x251da70/d; -L_0x251db50/d .functor AND 1, L_0x251d850, L_0x251da70, C4<1>, C4<1>; -L_0x251db50 .delay (20000,20000,20000) L_0x251db50/d; -L_0x251dca0/d .functor AND 1, L_0x251bc00, L_0x251dfc0, C4<1>, C4<1>; -L_0x251dca0 .delay (20000,20000,20000) L_0x251dca0/d; -L_0x251ddf0/d .functor OR 1, L_0x251db50, L_0x251dca0, C4<0>, C4<0>; -L_0x251ddf0 .delay (20000,20000,20000) L_0x251ddf0/d; -v0x20ff7f0_0 .net "S", 0 0, L_0x251dfc0; 1 drivers -v0x2101da0_0 .alias "in0", 0 0, v0x24028d0_0; -v0x2106ec0_0 .alias "in1", 0 0, v0x220fa30_0; -v0x2106f60_0 .net "nS", 0 0, L_0x251da70; 1 drivers -v0x2106fe0_0 .net "out0", 0 0, L_0x251db50; 1 drivers -v0x2107080_0 .net "out1", 0 0, L_0x251dca0; 1 drivers -v0x20c5690_0 .alias "outfinal", 0 0, v0x2402850_0; -S_0x23d9630 .scope generate, "orbits[31]" "orbits[31]" 2 196, 2 196, S_0x23d9540; - .timescale -9 -12; -P_0x23ab248 .param/l "i" 2 196, +C4<011111>; -S_0x23dba40 .scope module, "attempt" "OrNorXor" 2 198, 2 64, S_0x23d9630; - .timescale -9 -12; -L_0x251cfd0/d .functor NOR 1, L_0x251f410, L_0x251e100, C4<0>, C4<0>; -L_0x251cfd0 .delay (10000,10000,10000) L_0x251cfd0/d; -L_0x251d0c0/d .functor NOT 1, L_0x251cfd0, C4<0>, C4<0>, C4<0>; -L_0x251d0c0 .delay (10000,10000,10000) L_0x251d0c0/d; -L_0x251e490/d .functor NAND 1, L_0x251f410, L_0x251e100, C4<1>, C4<1>; -L_0x251e490 .delay (10000,10000,10000) L_0x251e490/d; -L_0x251e5f0/d .functor NAND 1, L_0x251e490, L_0x251d0c0, C4<1>, C4<1>; -L_0x251e5f0 .delay (10000,10000,10000) L_0x251e5f0/d; -L_0x251e700/d .functor NOT 1, L_0x251e5f0, C4<0>, C4<0>, C4<0>; -L_0x251e700 .delay (10000,10000,10000) L_0x251e700/d; -v0x210f1b0_0 .net "A", 0 0, L_0x251f410; 1 drivers -v0x210f250_0 .net "AnandB", 0 0, L_0x251e490; 1 drivers -v0x210f2f0_0 .net "AnorB", 0 0, L_0x251cfd0; 1 drivers -v0x20fb450_0 .net "AorB", 0 0, L_0x251d0c0; 1 drivers -v0x20fb4d0_0 .net "AxorB", 0 0, L_0x251e700; 1 drivers -v0x20fb550_0 .net "B", 0 0, L_0x251e100; 1 drivers -v0x20fb5d0_0 .alias "Command", 2 0, v0x2463430_0; -v0x20fb650_0 .net "OrNorXorOut", 0 0, L_0x251f100; 1 drivers -v0x2101bb0_0 .net "XorNor", 0 0, L_0x251eb80; 1 drivers -v0x2101c30_0 .net "nXor", 0 0, L_0x251e5f0; 1 drivers -L_0x251ed00 .part C4, 2, 1; -L_0x251f2d0 .part C4, 0, 1; -S_0x20fe000 .scope module, "mux0" "TwoInMux" 2 83, 2 8, S_0x23dba40; - .timescale -9 -12; -L_0x251e860/d .functor NOT 1, L_0x251ed00, C4<0>, C4<0>, C4<0>; -L_0x251e860 .delay (10000,10000,10000) L_0x251e860/d; -L_0x251e920/d .functor AND 1, L_0x251e700, L_0x251e860, C4<1>, C4<1>; -L_0x251e920 .delay (20000,20000,20000) L_0x251e920/d; -L_0x251ea30/d .functor AND 1, L_0x251cfd0, L_0x251ed00, C4<1>, C4<1>; -L_0x251ea30 .delay (20000,20000,20000) L_0x251ea30/d; -L_0x251eb80/d .functor OR 1, L_0x251e920, L_0x251ea30, C4<0>, C4<0>; -L_0x251eb80 .delay (20000,20000,20000) L_0x251eb80/d; -v0x20fe0f0_0 .net "S", 0 0, L_0x251ed00; 1 drivers -v0x20fe1b0_0 .alias "in0", 0 0, v0x20fb4d0_0; -v0x2104cb0_0 .alias "in1", 0 0, v0x210f2f0_0; -v0x2104d50_0 .net "nS", 0 0, L_0x251e860; 1 drivers -v0x2104dd0_0 .net "out0", 0 0, L_0x251e920; 1 drivers -v0x2104e70_0 .net "out1", 0 0, L_0x251ea30; 1 drivers -v0x210f130_0 .alias "outfinal", 0 0, v0x2101bb0_0; -S_0x23dbb30 .scope module, "mux1" "TwoInMux" 2 84, 2 8, S_0x23dba40; - .timescale -9 -12; -L_0x251eda0/d .functor NOT 1, L_0x251f2d0, C4<0>, C4<0>, C4<0>; -L_0x251eda0 .delay (10000,10000,10000) L_0x251eda0/d; -L_0x251ee60/d .functor AND 1, L_0x251eb80, L_0x251eda0, C4<1>, C4<1>; -L_0x251ee60 .delay (20000,20000,20000) L_0x251ee60/d; -L_0x251efb0/d .functor AND 1, L_0x251d0c0, L_0x251f2d0, C4<1>, C4<1>; -L_0x251efb0 .delay (20000,20000,20000) L_0x251efb0/d; -L_0x251f100/d .functor OR 1, L_0x251ee60, L_0x251efb0, C4<0>, C4<0>; -L_0x251f100 .delay (20000,20000,20000) L_0x251f100/d; -v0x23ddf40_0 .net "S", 0 0, L_0x251f2d0; 1 drivers -v0x23ddfc0_0 .alias "in0", 0 0, v0x2101bb0_0; -v0x23de040_0 .alias "in1", 0 0, v0x20fb450_0; -v0x21093f0_0 .net "nS", 0 0, L_0x251eda0; 1 drivers -v0x2109470_0 .net "out0", 0 0, L_0x251ee60; 1 drivers -v0x2109510_0 .net "out1", 0 0, L_0x251efb0; 1 drivers -v0x21095b0_0 .alias "outfinal", 0 0, v0x20fb650_0; -S_0x23cdc00 .scope module, "ZeroMux0case" "FourInMux" 2 283, 2 24, S_0x22690e0; - .timescale -9 -12; -L_0x251f5f0/d .functor NOT 1, L_0x24b7340, C4<0>, C4<0>, C4<0>; -L_0x251f5f0 .delay (10000,10000,10000) L_0x251f5f0/d; -L_0x251f690/d .functor NOT 1, L_0x24b7470, C4<0>, C4<0>, C4<0>; -L_0x251f690 .delay (10000,10000,10000) L_0x251f690/d; -L_0x25208d0/d .functor NAND 1, L_0x251f5f0, L_0x251f690, L_0x24b75a0, C4<1>; -L_0x25208d0 .delay (10000,10000,10000) L_0x25208d0/d; -L_0x25209c0/d .functor NAND 1, L_0x24b7340, L_0x251f690, L_0x24b7640, C4<1>; -L_0x25209c0 .delay (10000,10000,10000) L_0x25209c0/d; -L_0x2520ab0/d .functor NAND 1, L_0x251f5f0, L_0x24b7470, L_0x24b76e0, C4<1>; -L_0x2520ab0 .delay (10000,10000,10000) L_0x2520ab0/d; -L_0x2520ba0/d .functor NAND 1, L_0x24b7340, L_0x24b7470, L_0x24b77d0, C4<1>; -L_0x2520ba0 .delay (10000,10000,10000) L_0x2520ba0/d; -L_0x2520c80/d .functor NAND 1, L_0x25208d0, L_0x25209c0, L_0x2520ab0, L_0x2520ba0; -L_0x2520c80 .delay (10000,10000,10000) L_0x2520c80/d; -v0x23cdcf0_0 .net "S0", 0 0, L_0x24b7340; 1 drivers -v0x23d0110_0 .net "S1", 0 0, L_0x24b7470; 1 drivers -v0x23d01b0_0 .net "in0", 0 0, L_0x24b75a0; 1 drivers -v0x23d0250_0 .net "in1", 0 0, L_0x24b7640; 1 drivers -v0x23d2620_0 .net "in2", 0 0, L_0x24b76e0; 1 drivers -v0x23d26c0_0 .net "in3", 0 0, L_0x24b77d0; 1 drivers -v0x23d2760_0 .net "nS0", 0 0, L_0x251f5f0; 1 drivers -v0x23d4b30_0 .net "nS1", 0 0, L_0x251f690; 1 drivers -v0x23d4bb0_0 .net "out", 0 0, L_0x2520c80; 1 drivers -v0x23d4c50_0 .net "out0", 0 0, L_0x25208d0; 1 drivers -v0x23d7040_0 .net "out1", 0 0, L_0x25209c0; 1 drivers -v0x23d70e0_0 .net "out2", 0 0, L_0x2520ab0; 1 drivers -v0x23d7180_0 .net "out3", 0 0, L_0x2520ba0; 1 drivers -S_0x23c22c0 .scope module, "OneMux0case" "FourInMux" 2 284, 2 24, S_0x22690e0; - .timescale -9 -12; -L_0x24b78c0/d .functor NOT 1, L_0x24b8090, C4<0>, C4<0>, C4<0>; -L_0x24b78c0 .delay (10000,10000,10000) L_0x24b78c0/d; -L_0x24b7970/d .functor NOT 1, L_0x24b81c0, C4<0>, C4<0>, C4<0>; -L_0x24b7970 .delay (10000,10000,10000) L_0x24b7970/d; -L_0x24b7a10/d .functor NAND 1, L_0x24b78c0, L_0x24b7970, L_0x24b82f0, C4<1>; -L_0x24b7a10 .delay (10000,10000,10000) L_0x24b7a10/d; -L_0x24b7b50/d .functor NAND 1, L_0x24b8090, L_0x24b7970, L_0x24b8390, C4<1>; -L_0x24b7b50 .delay (10000,10000,10000) L_0x24b7b50/d; -L_0x24b7c40/d .functor NAND 1, L_0x24b78c0, L_0x24b81c0, L_0x24b8430, C4<1>; -L_0x24b7c40 .delay (10000,10000,10000) L_0x24b7c40/d; -L_0x24b7d30/d .functor NAND 1, L_0x24b8090, L_0x24b81c0, L_0x24b8520, C4<1>; -L_0x24b7d30 .delay (10000,10000,10000) L_0x24b7d30/d; -L_0x24b7e10/d .functor NAND 1, L_0x24b7a10, L_0x24b7b50, L_0x24b7c40, L_0x24b7d30; -L_0x24b7e10 .delay (10000,10000,10000) L_0x24b7e10/d; -v0x23c23b0_0 .net "S0", 0 0, L_0x24b8090; 1 drivers -v0x23c47c0_0 .net "S1", 0 0, L_0x24b81c0; 1 drivers -v0x23c4860_0 .net "in0", 0 0, L_0x24b82f0; 1 drivers -v0x23c4900_0 .net "in1", 0 0, L_0x24b8390; 1 drivers -v0x23c6cc0_0 .net "in2", 0 0, L_0x24b8430; 1 drivers -v0x23c6d60_0 .net "in3", 0 0, L_0x24b8520; 1 drivers -v0x23c6e00_0 .net "nS0", 0 0, L_0x24b78c0; 1 drivers -v0x23c91e0_0 .net "nS1", 0 0, L_0x24b7970; 1 drivers -v0x23c9260_0 .net "out", 0 0, L_0x24b7e10; 1 drivers -v0x23c9300_0 .net "out0", 0 0, L_0x24b7a10; 1 drivers -v0x23cb6f0_0 .net "out1", 0 0, L_0x24b7b50; 1 drivers -v0x23cb790_0 .net "out2", 0 0, L_0x24b7c40; 1 drivers -v0x23cb830_0 .net "out3", 0 0, L_0x24b7d30; 1 drivers -S_0x23bb3c0 .scope module, "TwoMux0case" "TwoInMux" 2 285, 2 8, S_0x22690e0; - .timescale -9 -12; -L_0x24b8610/d .functor NOT 1, L_0x249f290, C4<0>, C4<0>, C4<0>; -L_0x24b8610 .delay (10000,10000,10000) L_0x24b8610/d; -L_0x24b86c0/d .functor AND 1, L_0x249f330, L_0x24b8610, C4<1>, C4<1>; -L_0x24b86c0 .delay (20000,20000,20000) L_0x24b86c0/d; -L_0x249f000/d .functor AND 1, L_0x249f420, L_0x249f290, C4<1>, C4<1>; -L_0x249f000 .delay (20000,20000,20000) L_0x249f000/d; -L_0x249f0b0/d .functor OR 1, L_0x24b86c0, L_0x249f000, C4<0>, C4<0>; -L_0x249f0b0 .delay (20000,20000,20000) L_0x249f0b0/d; -v0x23bb4b0_0 .net "S", 0 0, L_0x249f290; 1 drivers -v0x23bd8c0_0 .net "in0", 0 0, L_0x249f330; 1 drivers -v0x23bd960_0 .net "in1", 0 0, L_0x249f420; 1 drivers -v0x23bda00_0 .net "nS", 0 0, L_0x24b8610; 1 drivers -v0x23bfdc0_0 .net "out0", 0 0, L_0x24b86c0; 1 drivers -v0x23bfe60_0 .net "out1", 0 0, L_0x249f000; 1 drivers -v0x23bff00_0 .net "outfinal", 0 0, L_0x249f0b0; 1 drivers -S_0x239ad50 .scope generate, "muxbits[1]" "muxbits[1]" 2 290, 2 290, S_0x22690e0; - .timescale -9 -12; -P_0x22934a8 .param/l "i" 2 290, +C4<01>; -L_0x246b7c0/d .functor OR 1, L_0x246bcf0, L_0x246bad0, C4<0>, C4<0>; -L_0x246b7c0 .delay (20000,20000,20000) L_0x246b7c0/d; -v0x23b8f60_0 .net *"_s15", 0 0, L_0x246bcf0; 1 drivers -v0x23b9020_0 .net *"_s16", 0 0, L_0x246bad0; 1 drivers -S_0x23ad630 .scope module, "ZeroMux" "FourInMux" 2 292, 2 24, S_0x239ad50; - .timescale -9 -12; -L_0x2467a80/d .functor NOT 1, L_0x2469d30, C4<0>, C4<0>, C4<0>; -L_0x2467a80 .delay (10000,10000,10000) L_0x2467a80/d; -L_0x24693d0/d .functor NOT 1, L_0x2469e60, C4<0>, C4<0>, C4<0>; -L_0x24693d0 .delay (10000,10000,10000) L_0x24693d0/d; -L_0x24694d0/d .functor NAND 1, L_0x2467a80, L_0x24693d0, L_0x2469f90, C4<1>; -L_0x24694d0 .delay (10000,10000,10000) L_0x24694d0/d; -L_0x2469670/d .functor NAND 1, L_0x2469d30, L_0x24693d0, L_0x246a030, C4<1>; -L_0x2469670 .delay (10000,10000,10000) L_0x2469670/d; -L_0x24697c0/d .functor NAND 1, L_0x2467a80, L_0x2469e60, L_0x246a120, C4<1>; -L_0x24697c0 .delay (10000,10000,10000) L_0x24697c0/d; -L_0x2469910/d .functor NAND 1, L_0x2469d30, L_0x2469e60, L_0x246a2a0, C4<1>; -L_0x2469910 .delay (10000,10000,10000) L_0x2469910/d; -L_0x2469a80/d .functor NAND 1, L_0x24694d0, L_0x2469670, L_0x24697c0, L_0x2469910; -L_0x2469a80 .delay (10000,10000,10000) L_0x2469a80/d; -v0x23afaa0_0 .net "S0", 0 0, L_0x2469d30; 1 drivers -v0x23afb60_0 .net "S1", 0 0, L_0x2469e60; 1 drivers -v0x23afc00_0 .net "in0", 0 0, L_0x2469f90; 1 drivers -v0x23b1fb0_0 .net "in1", 0 0, L_0x246a030; 1 drivers -v0x23b2030_0 .net "in2", 0 0, L_0x246a120; 1 drivers -v0x23b20d0_0 .net "in3", 0 0, L_0x246a2a0; 1 drivers -v0x23b44c0_0 .net "nS0", 0 0, L_0x2467a80; 1 drivers -v0x23b4560_0 .net "nS1", 0 0, L_0x24693d0; 1 drivers -v0x23b4600_0 .net "out", 0 0, L_0x2469a80; 1 drivers -v0x23b69d0_0 .net "out0", 0 0, L_0x24694d0; 1 drivers -v0x23b6a50_0 .net "out1", 0 0, L_0x2469670; 1 drivers -v0x23b6af0_0 .net "out2", 0 0, L_0x24697c0; 1 drivers -v0x23b8ec0_0 .net "out3", 0 0, L_0x2469910; 1 drivers -S_0x23a1cf0 .scope module, "OneMux" "FourInMux" 2 293, 2 24, S_0x239ad50; - .timescale -9 -12; -L_0x246a420/d .functor NOT 1, L_0x246acf0, C4<0>, C4<0>, C4<0>; -L_0x246a420 .delay (10000,10000,10000) L_0x246a420/d; -L_0x246a4c0/d .functor NOT 1, L_0x246ae20, C4<0>, C4<0>, C4<0>; -L_0x246a4c0 .delay (10000,10000,10000) L_0x246a4c0/d; -L_0x246a560/d .functor NAND 1, L_0x246a420, L_0x246a4c0, L_0x246afb0, C4<1>; -L_0x246a560 .delay (10000,10000,10000) L_0x246a560/d; -L_0x246a6a0/d .functor NAND 1, L_0x246acf0, L_0x246a4c0, L_0x246b050, C4<1>; -L_0x246a6a0 .delay (10000,10000,10000) L_0x246a6a0/d; -L_0x246a790/d .functor NAND 1, L_0x246a420, L_0x246ae20, L_0x246b0f0, C4<1>; -L_0x246a790 .delay (10000,10000,10000) L_0x246a790/d; -L_0x246a880/d .functor NAND 1, L_0x246acf0, L_0x246ae20, L_0x246b1e0, C4<1>; -L_0x246a880 .delay (10000,10000,10000) L_0x246a880/d; -L_0x246a9f0/d .functor NAND 1, L_0x246a560, L_0x246a6a0, L_0x246a790, L_0x246a880; -L_0x246a9f0 .delay (10000,10000,10000) L_0x246a9f0/d; -v0x23a4150_0 .net "S0", 0 0, L_0x246acf0; 1 drivers -v0x23a4210_0 .net "S1", 0 0, L_0x246ae20; 1 drivers -v0x23a42b0_0 .net "in0", 0 0, L_0x246afb0; 1 drivers -v0x23a6650_0 .net "in1", 0 0, L_0x246b050; 1 drivers -v0x23a66d0_0 .net "in2", 0 0, L_0x246b0f0; 1 drivers -v0x23a6770_0 .net "in3", 0 0, L_0x246b1e0; 1 drivers -v0x23a8b70_0 .net "nS0", 0 0, L_0x246a420; 1 drivers -v0x23a8c10_0 .net "nS1", 0 0, L_0x246a4c0; 1 drivers -v0x23a8cb0_0 .net "out", 0 0, L_0x246a9f0; 1 drivers -v0x23ab080_0 .net "out0", 0 0, L_0x246a560; 1 drivers -v0x23ab100_0 .net "out1", 0 0, L_0x246a6a0; 1 drivers -v0x23ab1a0_0 .net "out2", 0 0, L_0x246a790; 1 drivers -v0x23ad590_0 .net "out3", 0 0, L_0x246a880; 1 drivers -S_0x239d250 .scope module, "TwoMux" "TwoInMux" 2 294, 2 8, S_0x239ad50; - .timescale -9 -12; -L_0x246af50/d .functor NOT 1, L_0x246b720, C4<0>, C4<0>, C4<0>; -L_0x246af50 .delay (10000,10000,10000) L_0x246af50/d; -L_0x246b360/d .functor AND 1, L_0x246b850, L_0x246af50, C4<1>, C4<1>; -L_0x246b360 .delay (20000,20000,20000) L_0x246b360/d; -L_0x246b450/d .functor AND 1, L_0x246b990, L_0x246b720, C4<1>, C4<1>; -L_0x246b450 .delay (20000,20000,20000) L_0x246b450/d; -L_0x246b540/d .functor OR 1, L_0x246b360, L_0x246b450, C4<0>, C4<0>; -L_0x246b540 .delay (20000,20000,20000) L_0x246b540/d; -v0x239d340_0 .net "S", 0 0, L_0x246b720; 1 drivers -v0x23988e0_0 .net "in0", 0 0, L_0x246b850; 1 drivers -v0x239ae80_0 .net "in1", 0 0, L_0x246b990; 1 drivers -v0x239f750_0 .net "nS", 0 0, L_0x246af50; 1 drivers -v0x239f7d0_0 .net "out0", 0 0, L_0x246b360; 1 drivers -v0x239f870_0 .net "out1", 0 0, L_0x246b450; 1 drivers -v0x23a1c50_0 .net "outfinal", 0 0, L_0x246b540; 1 drivers -S_0x236d7a0 .scope generate, "muxbits[2]" "muxbits[2]" 2 290, 2 290, S_0x22690e0; - .timescale -9 -12; -P_0x22d4e38 .param/l "i" 2 290, +C4<010>; -L_0x246e3f0/d .functor OR 1, L_0x246e720, L_0x246e850, C4<0>, C4<0>; -L_0x246e3f0 .delay (20000,20000,20000) L_0x246e3f0/d; -v0x23987a0_0 .net *"_s15", 0 0, L_0x246e720; 1 drivers -v0x2398840_0 .net *"_s16", 0 0, L_0x246e850; 1 drivers -S_0x2381dc0 .scope module, "ZeroMux" "FourInMux" 2 292, 2 24, S_0x236d7a0; - .timescale -9 -12; -L_0x246bf30/d .functor NOT 1, L_0x246bde0, C4<0>, C4<0>, C4<0>; -L_0x246bf30 .delay (10000,10000,10000) L_0x246bf30/d; -L_0x246c020/d .functor NOT 1, L_0x246c920, C4<0>, C4<0>, C4<0>; -L_0x246c020 .delay (10000,10000,10000) L_0x246c020/d; -L_0x246c0c0/d .functor NAND 1, L_0x246bf30, L_0x246c020, L_0x246c7d0, C4<1>; -L_0x246c0c0 .delay (10000,10000,10000) L_0x246c0c0/d; -L_0x246c200/d .functor NAND 1, L_0x246bde0, L_0x246c020, L_0x246cb20, C4<1>; -L_0x246c200 .delay (10000,10000,10000) L_0x246c200/d; -L_0x246c2f0/d .functor NAND 1, L_0x246bf30, L_0x246c920, L_0x246ca50, C4<1>; -L_0x246c2f0 .delay (10000,10000,10000) L_0x246c2f0/d; -L_0x246c3e0/d .functor NAND 1, L_0x246bde0, L_0x246c920, L_0x246ccf0, C4<1>; -L_0x246c3e0 .delay (10000,10000,10000) L_0x246c3e0/d; -L_0x246c520/d .functor NAND 1, L_0x246c0c0, L_0x246c200, L_0x246c2f0, L_0x246c3e0; -L_0x246c520 .delay (10000,10000,10000) L_0x246c520/d; -v0x2381eb0_0 .net "S0", 0 0, L_0x246bde0; 1 drivers -v0x23832c0_0 .net "S1", 0 0, L_0x246c920; 1 drivers -v0x2383360_0 .net "in0", 0 0, L_0x246c7d0; 1 drivers -v0x2383400_0 .net "in1", 0 0, L_0x246cb20; 1 drivers -v0x23848c0_0 .net "in2", 0 0, L_0x246ca50; 1 drivers -v0x2384960_0 .net "in3", 0 0, L_0x246ccf0; 1 drivers -v0x2384a00_0 .net "nS0", 0 0, L_0x246bf30; 1 drivers -v0x2385e40_0 .net "nS1", 0 0, L_0x246c020; 1 drivers -v0x2385ec0_0 .net "out", 0 0, L_0x246c520; 1 drivers -v0x2385f60_0 .net "out0", 0 0, L_0x246c0c0; 1 drivers -v0x23e0440_0 .net "out1", 0 0, L_0x246c200; 1 drivers -v0x23e04e0_0 .net "out2", 0 0, L_0x246c2f0; 1 drivers -v0x23e0580_0 .net "out3", 0 0, L_0x246c3e0; 1 drivers -S_0x237b0e0 .scope module, "OneMux" "FourInMux" 2 293, 2 24, S_0x236d7a0; - .timescale -9 -12; -L_0x246cbc0/d .functor NOT 1, L_0x246d6c0, C4<0>, C4<0>, C4<0>; -L_0x246cbc0 .delay (10000,10000,10000) L_0x246cbc0/d; -L_0x246cf20/d .functor NOT 1, L_0x246cde0, C4<0>, C4<0>, C4<0>; -L_0x246cf20 .delay (10000,10000,10000) L_0x246cf20/d; -L_0x246cf80/d .functor NAND 1, L_0x246cbc0, L_0x246cf20, L_0x246d980, C4<1>; -L_0x246cf80 .delay (10000,10000,10000) L_0x246cf80/d; -L_0x246d0c0/d .functor NAND 1, L_0x246d6c0, L_0x246cf20, L_0x246d7f0, C4<1>; -L_0x246d0c0 .delay (10000,10000,10000) L_0x246d0c0/d; -L_0x246d1b0/d .functor NAND 1, L_0x246cbc0, L_0x246cde0, L_0x246dbc0, C4<1>; -L_0x246d1b0 .delay (10000,10000,10000) L_0x246d1b0/d; -L_0x246d2a0/d .functor NAND 1, L_0x246d6c0, L_0x246cde0, L_0x246dab0, C4<1>; -L_0x246d2a0 .delay (10000,10000,10000) L_0x246d2a0/d; -L_0x246d410/d .functor NAND 1, L_0x246cf80, L_0x246d0c0, L_0x246d1b0, L_0x246d2a0; -L_0x246d410 .delay (10000,10000,10000) L_0x246d410/d; -v0x237c640_0 .net "S0", 0 0, L_0x246d6c0; 1 drivers -v0x237c700_0 .net "S1", 0 0, L_0x246cde0; 1 drivers -v0x237c7a0_0 .net "in0", 0 0, L_0x246d980; 1 drivers -v0x237dbc0_0 .net "in1", 0 0, L_0x246d7f0; 1 drivers -v0x237dc40_0 .net "in2", 0 0, L_0x246dbc0; 1 drivers -v0x237dce0_0 .net "in3", 0 0, L_0x246dab0; 1 drivers -v0x237f1c0_0 .net "nS0", 0 0, L_0x246cbc0; 1 drivers -v0x237f260_0 .net "nS1", 0 0, L_0x246cf20; 1 drivers -v0x237f300_0 .net "out", 0 0, L_0x246d410; 1 drivers -v0x2380740_0 .net "out0", 0 0, L_0x246cf80; 1 drivers -v0x23807e0_0 .net "out1", 0 0, L_0x246d0c0; 1 drivers -v0x2380880_0 .net "out2", 0 0, L_0x246d1b0; 1 drivers -v0x2381d40_0 .net "out3", 0 0, L_0x246d2a0; 1 drivers -S_0x23784c0 .scope module, "TwoMux" "TwoInMux" 2 294, 2 8, S_0x236d7a0; - .timescale -9 -12; -L_0x246d890/d .functor NOT 1, L_0x246dc60, C4<0>, C4<0>, C4<0>; -L_0x246d890 .delay (10000,10000,10000) L_0x246d890/d; -L_0x246ddd0/d .functor AND 1, L_0x246e2c0, L_0x246d890, C4<1>, C4<1>; -L_0x246ddd0 .delay (20000,20000,20000) L_0x246ddd0/d; -L_0x246dec0/d .functor AND 1, L_0x246e190, L_0x246dc60, C4<1>, C4<1>; -L_0x246dec0 .delay (20000,20000,20000) L_0x246dec0/d; -L_0x246dfb0/d .functor OR 1, L_0x246ddd0, L_0x246dec0, C4<0>, C4<0>; -L_0x246dfb0 .delay (20000,20000,20000) L_0x246dfb0/d; -v0x23785b0_0 .net "S", 0 0, L_0x246dc60; 1 drivers -v0x236c2b0_0 .net "in0", 0 0, L_0x246e2c0; 1 drivers -v0x236d8d0_0 .net "in1", 0 0, L_0x246e190; 1 drivers -v0x2379ac0_0 .net "nS", 0 0, L_0x246d890; 1 drivers -v0x2379b40_0 .net "out0", 0 0, L_0x246ddd0; 1 drivers -v0x2379be0_0 .net "out1", 0 0, L_0x246dec0; 1 drivers -v0x237b040_0 .net "outfinal", 0 0, L_0x246dfb0; 1 drivers -S_0x22c6fe0 .scope generate, "muxbits[3]" "muxbits[3]" 2 290, 2 290, S_0x22690e0; - .timescale -9 -12; -P_0x226d278 .param/l "i" 2 290, +C4<011>; -L_0x2470d20/d .functor OR 1, L_0x24710a0, L_0x2470eb0, C4<0>, C4<0>; -L_0x2470d20 .delay (20000,20000,20000) L_0x2470d20/d; -v0x236c150_0 .net *"_s15", 0 0, L_0x24710a0; 1 drivers -v0x236c210_0 .net *"_s16", 0 0, L_0x2470eb0; 1 drivers -S_0x2270ca0 .scope module, "ZeroMux" "FourInMux" 2 292, 2 24, S_0x22c6fe0; - .timescale -9 -12; -L_0x246e5d0/d .functor NOT 1, L_0x246f170, C4<0>, C4<0>, C4<0>; -L_0x246e5d0 .delay (10000,10000,10000) L_0x246e5d0/d; -L_0x246e670/d .functor NOT 1, L_0x246e980, C4<0>, C4<0>, C4<0>; -L_0x246e670 .delay (10000,10000,10000) L_0x246e670/d; -L_0x246eae0/d .functor NAND 1, L_0x246e5d0, L_0x246e670, L_0x246f410, C4<1>; +S_0x23b34d0 .scope module, "test32Adder" "test32Adder" 2 126; + .timescale -9 -12; +P_0x23412f8 .param/l "size" 2 127, +C4<0100>; +v0x245e5f0_0 .var "A", 3 0; +RS_0x7f3880bf1098/0/0 .resolv tri, L_0x24608b0, L_0x24625c0, L_0x24641e0, L_0x2466260; +RS_0x7f3880bf1098/0/4 .resolv tri, L_0x2478450, L_0x2479fc0, L_0x247b9e0, L_0x247d920; +RS_0x7f3880bf1098 .resolv tri, RS_0x7f3880bf1098/0/0, RS_0x7f3880bf1098/0/4, C4, C4; +v0x245e670_0 .net8 "AddSubSLTSum", 3 0, RS_0x7f3880bf1098; 8 drivers +v0x245e6f0_0 .net "AllZeros", 0 0, L_0x2488c80; 1 drivers +RS_0x7f3880befe38/0/0 .resolv tri, L_0x2467c20, L_0x24686d0, L_0x2469140, L_0x2469ba0; +RS_0x7f3880befe38/0/4 .resolv tri, L_0x247f1f0, L_0x247fc60, L_0x24806d0, L_0x2481230; +RS_0x7f3880befe38 .resolv tri, RS_0x7f3880befe38/0/0, RS_0x7f3880befe38/0/4, C4, C4; +v0x245e770_0 .net8 "AndNandOut", 3 0, RS_0x7f3880befe38; 8 drivers +v0x245e7f0_0 .var "B", 3 0; +v0x245e870_0 .var "Command", 2 0; +RS_0x7f3880bf1578 .resolv tri, L_0x2470cd0, L_0x2473950, L_0x24765b0, L_0x24880f0; +v0x245e8f0_0 .net8 "OneBitFinalOut", 3 0, RS_0x7f3880bf1578; 4 drivers +RS_0x7f3880bef748/0/0 .resolv tri, L_0x246aef0, L_0x246c450, L_0x246d750, L_0x246ea40; +RS_0x7f3880bef748/0/4 .resolv tri, L_0x24825f0, L_0x24838f0, L_0x2484bf0, L_0x2485ee0; +RS_0x7f3880bef748 .resolv tri, RS_0x7f3880bef748/0/0, RS_0x7f3880bef748/0/4, C4, C4; +v0x245e970_0 .net8 "OrNorXorOut", 3 0, RS_0x7f3880bef748; 8 drivers +RS_0x7f3880bf1188 .resolv tri, L_0x24672e0, L_0x247e8f0, C4, C4; +v0x245ea40_0 .net8 "SLTflag", 0 0, RS_0x7f3880bf1188; 2 drivers +RS_0x7f3880bf15a8 .resolv tri, L_0x2471180, L_0x2473e20, L_0x24766f0, L_0x24883b0; +v0x245eac0_0 .net8 "ZeroFlag", 3 0, RS_0x7f3880bf15a8; 4 drivers +v0x245eb40_0 .var "carryin", 3 0; +RS_0x7f3880bf13c8 .resolv tri, L_0x2466530, L_0x247dbf0, C4, C4; +v0x245ebc0_0 .net8 "carryout", 0 0, RS_0x7f3880bf13c8; 2 drivers +RS_0x7f3880bf1488 .resolv tri, L_0x2466300, L_0x247da20, C4, C4; +v0x245ec40_0 .net8 "overflow", 0 0, RS_0x7f3880bf1488; 2 drivers +RS_0x7f3880bf14b8/0/0 .resolv tri, L_0x2460020, L_0x2461dd0, L_0x2463b30, L_0x2465af0; +RS_0x7f3880bf14b8/0/4 .resolv tri, L_0x2477d30, L_0x2479830, L_0x247b370, L_0x247d220; +RS_0x7f3880bf14b8 .resolv tri, RS_0x7f3880bf14b8/0/0, RS_0x7f3880bf14b8/0/4, C4, C4; +v0x245ecc0_0 .net8 "subtract", 3 0, RS_0x7f3880bf14b8; 8 drivers +S_0x24576a0 .scope module, "trial" "AddSubSLT32" 2 145, 3 205, S_0x23b34d0; + .timescale -9 -12; +P_0x2457798 .param/l "size" 3 242, +C4<0100>; +L_0x2464440/d .functor NOT 1, L_0x2464530, C4<0>, C4<0>, C4<0>; +L_0x2464440 .delay (10000,10000,10000) L_0x2464440/d; +L_0x24645d0/d .functor AND 1, L_0x2464710, L_0x2464370, L_0x2464440, C4<1>; +L_0x24645d0 .delay (20000,20000,20000) L_0x24645d0/d; +L_0x2466530/d .functor OR 1, L_0x2466660, C4<0>, C4<0>, C4<0>; +L_0x2466530 .delay (20000,20000,20000) L_0x2466530/d; +L_0x2466300/d .functor XOR 1, RS_0x7f3880bf13c8, L_0x2466980, C4<0>, C4<0>; +L_0x2466300 .delay (40000,40000,40000) L_0x2466300/d; +L_0x2466a20/d .functor NOT 1, RS_0x7f3880bf1488, C4<0>, C4<0>, C4<0>; +L_0x2466a20 .delay (10000,10000,10000) L_0x2466a20/d; +L_0x2466b10/d .functor NOT 1, L_0x2466bf0, C4<0>, C4<0>, C4<0>; +L_0x2466b10 .delay (10000,10000,10000) L_0x2466b10/d; +L_0x2460950/d .functor AND 1, L_0x2466a20, L_0x2466ee0, C4<1>, C4<1>; +L_0x2460950 .delay (20000,20000,20000) L_0x2460950/d; +L_0x2466f80/d .functor AND 1, RS_0x7f3880bf1488, L_0x2466b10, C4<1>, C4<1>; +L_0x2466f80 .delay (20000,20000,20000) L_0x2466f80/d; +L_0x2467070/d .functor AND 1, L_0x2460950, L_0x24645d0, C4<1>, C4<1>; +L_0x2467070 .delay (20000,20000,20000) L_0x2467070/d; +L_0x2467170/d .functor AND 1, L_0x2466f80, L_0x24645d0, C4<1>, C4<1>; +L_0x2467170 .delay (20000,20000,20000) L_0x2467170/d; +L_0x24672e0/d .functor OR 1, L_0x2467070, L_0x2467170, C4<0>, C4<0>; +L_0x24672e0 .delay (20000,20000,20000) L_0x24672e0/d; +v0x245d340_0 .net "A", 3 0, v0x245e5f0_0; 1 drivers +v0x245d3e0_0 .alias "AddSubSLTSum", 3 0, v0x245e670_0; +v0x245d460_0 .net "B", 3 0, v0x245e7f0_0; 1 drivers +RS_0x7f3880bf3d08 .resolv tri, L_0x245ff30, L_0x2461c80, L_0x24639a0, L_0x24647b0; +v0x245d4e0_0 .net8 "CarryoutWire", 3 0, RS_0x7f3880bf3d08; 4 drivers +v0x245d560_0 .net "Command", 2 0, v0x245e870_0; 1 drivers +RS_0x7f3880bf3d38 .resolv tri, L_0x245fe40, L_0x2461b90, L_0x24638b0, L_0x24658c0; +v0x245d5e0_0 .net8 "NewVal", 3 0, RS_0x7f3880bf3d38; 4 drivers +v0x245d680_0 .net "Res0OF1", 0 0, L_0x2466f80; 1 drivers +v0x245d720_0 .net "Res1OF0", 0 0, L_0x2460950; 1 drivers +v0x245d810_0 .alias "SLTflag", 0 0, v0x245ea40_0; +v0x245d8e0_0 .net "SLTflag0", 0 0, L_0x2467070; 1 drivers +v0x245d980_0 .net "SLTflag1", 0 0, L_0x2467170; 1 drivers +v0x245da20_0 .net "SLTon", 0 0, L_0x24645d0; 1 drivers +v0x245db30_0 .net *"_s37", 0 0, L_0x2464530; 1 drivers +v0x245dbd0_0 .net *"_s39", 0 0, L_0x2464710; 1 drivers +v0x245dcf0_0 .net *"_s41", 0 0, L_0x2464370; 1 drivers +v0x245dd90_0 .net *"_s61", 0 0, L_0x2466660; 1 drivers +v0x245dc50_0 .net/s *"_s62", 0 0, C4<0>; 1 drivers +v0x245dee0_0 .net *"_s65", 0 0, L_0x2466980; 1 drivers +v0x245e000_0 .net *"_s67", 0 0, L_0x2466bf0; 1 drivers +v0x245e080_0 .net *"_s69", 0 0, L_0x2466ee0; 1 drivers +v0x245df60_0 .net "carryin", 3 0, v0x245eb40_0; 1 drivers +v0x245e1b0_0 .alias "carryout", 0 0, v0x245ebc0_0; +v0x245e100_0 .net "nAddSubSLTSum", 0 0, L_0x2466b10; 1 drivers +v0x245e2f0_0 .net "nCmd2", 0 0, L_0x2464440; 1 drivers +v0x245e230_0 .net "nOF", 0 0, L_0x2466a20; 1 drivers +v0x245e440_0 .alias "overflow", 0 0, v0x245ec40_0; +v0x245e3c0_0 .alias "subtract", 3 0, v0x245ecc0_0; +L_0x245fe40 .part/pv L_0x245f960, 1, 1, 4; +L_0x245ff30 .part/pv L_0x245fce0, 1, 1, 4; +L_0x2460020 .part/pv L_0x2450740, 1, 1, 4; +L_0x2460150 .part v0x245e5f0_0, 1, 1; +L_0x2460300 .part v0x245e7f0_0, 1, 1; +L_0x24604b0 .part RS_0x7f3880bf3d08, 0, 1; +L_0x24608b0 .part/pv L_0x2460770, 1, 1, 4; +L_0x24609e0 .part RS_0x7f3880bf3d38, 1, 1; +L_0x2461b90 .part/pv L_0x24616e0, 2, 1, 4; +L_0x2461c80 .part/pv L_0x2461a30, 2, 1, 4; +L_0x2461dd0 .part/pv L_0x2461410, 2, 1, 4; +L_0x2461e70 .part v0x245e5f0_0, 2, 1; +L_0x2461f80 .part v0x245e7f0_0, 2, 1; +L_0x24620b0 .part RS_0x7f3880bf3d08, 1, 1; +L_0x24625c0 .part/pv L_0x24624d0, 2, 1, 4; +L_0x2462660 .part RS_0x7f3880bf3d38, 2, 1; +L_0x24638b0 .part/pv L_0x2463400, 3, 1, 4; +L_0x24639a0 .part/pv L_0x2463750, 3, 1, 4; +L_0x2463b30 .part/pv L_0x2463130, 3, 1, 4; +L_0x2463bd0 .part v0x245e5f0_0, 3, 1; +L_0x2463a90 .part v0x245e7f0_0, 3, 1; +L_0x2463db0 .part RS_0x7f3880bf3d08, 2, 1; +L_0x24641e0 .part/pv L_0x24640a0, 3, 1, 4; +L_0x2464280 .part RS_0x7f3880bf3d38, 3, 1; +L_0x2464530 .part v0x245e870_0, 2, 1; +L_0x2464710 .part v0x245e870_0, 0, 1; +L_0x2464370 .part v0x245e870_0, 1, 1; +L_0x24658c0 .part/pv L_0x2465410, 0, 1, 4; +L_0x24647b0 .part/pv L_0x2465760, 0, 1, 4; +L_0x2465af0 .part/pv L_0x2465140, 0, 1, 4; +L_0x24659b0 .part v0x245e5f0_0, 0, 1; +L_0x2465ce0 .part v0x245e7f0_0, 0, 1; +L_0x2465be0 .part RS_0x7f3880bf14b8, 0, 1; +L_0x2466260 .part/pv L_0x2466120, 0, 1, 4; +L_0x2465e10 .part RS_0x7f3880bf3d38, 0, 1; +L_0x2466660 .part RS_0x7f3880bf3d08, 3, 1; +L_0x2466980 .part RS_0x7f3880bf3d08, 2, 1; +L_0x2466bf0 .part RS_0x7f3880bf1098, 3, 1; +L_0x2466ee0 .part RS_0x7f3880bf1098, 3, 1; +S_0x245c320 .scope module, "attempt2" "MiddleAddSubSLT" 3 235, 3 89, S_0x24576a0; + .timescale -9 -12; +L_0x24648e0/d .functor NOT 1, L_0x2465ce0, C4<0>, C4<0>, C4<0>; +L_0x24648e0 .delay (10000,10000,10000) L_0x24648e0/d; +L_0x2464fe0/d .functor NOT 1, L_0x24650a0, C4<0>, C4<0>, C4<0>; +L_0x2464fe0 .delay (10000,10000,10000) L_0x2464fe0/d; +L_0x2465140/d .functor AND 1, L_0x2465280, L_0x2464fe0, C4<1>, C4<1>; +L_0x2465140 .delay (20000,20000,20000) L_0x2465140/d; +L_0x2465320/d .functor XOR 1, L_0x24659b0, L_0x2464d70, C4<0>, C4<0>; +L_0x2465320 .delay (40000,40000,40000) L_0x2465320/d; +L_0x2465410/d .functor XOR 1, L_0x2465320, L_0x2465be0, C4<0>, C4<0>; +L_0x2465410 .delay (40000,40000,40000) L_0x2465410/d; +L_0x2465500/d .functor AND 1, L_0x24659b0, L_0x2464d70, C4<1>, C4<1>; +L_0x2465500 .delay (20000,20000,20000) L_0x2465500/d; +L_0x2465670/d .functor AND 1, L_0x2465320, L_0x2465be0, C4<1>, C4<1>; +L_0x2465670 .delay (20000,20000,20000) L_0x2465670/d; +L_0x2465760/d .functor OR 1, L_0x2465500, L_0x2465670, C4<0>, C4<0>; +L_0x2465760 .delay (20000,20000,20000) L_0x2465760/d; +v0x245c9a0_0 .net "A", 0 0, L_0x24659b0; 1 drivers +v0x245ca60_0 .net "AandB", 0 0, L_0x2465500; 1 drivers +v0x245cb00_0 .net "AddSubSLTSum", 0 0, L_0x2465410; 1 drivers +v0x245cba0_0 .net "AxorB", 0 0, L_0x2465320; 1 drivers +v0x245cc20_0 .net "B", 0 0, L_0x2465ce0; 1 drivers +v0x245ccd0_0 .net "BornB", 0 0, L_0x2464d70; 1 drivers +v0x245cd90_0 .net "CINandAxorB", 0 0, L_0x2465670; 1 drivers +v0x245ce10_0 .alias "Command", 2 0, v0x245d560_0; +v0x245ce90_0 .net *"_s3", 0 0, L_0x24650a0; 1 drivers +v0x245cf10_0 .net *"_s5", 0 0, L_0x2465280; 1 drivers +v0x245cfb0_0 .net "carryin", 0 0, L_0x2465be0; 1 drivers +v0x245d050_0 .net "carryout", 0 0, L_0x2465760; 1 drivers +v0x245d0f0_0 .net "nB", 0 0, L_0x24648e0; 1 drivers +v0x245d1a0_0 .net "nCmd2", 0 0, L_0x2464fe0; 1 drivers +v0x245d2a0_0 .net "subtract", 0 0, L_0x2465140; 1 drivers +L_0x2464f40 .part v0x245e870_0, 0, 1; +L_0x24650a0 .part v0x245e870_0, 2, 1; +L_0x2465280 .part v0x245e870_0, 0, 1; +S_0x245c410 .scope module, "mux0" "TwoInMux" 3 105, 3 8, S_0x245c320; + .timescale -9 -12; +L_0x2464a90/d .functor NOT 1, L_0x2464f40, C4<0>, C4<0>, C4<0>; +L_0x2464a90 .delay (10000,10000,10000) L_0x2464a90/d; +L_0x2464b50/d .functor AND 1, L_0x2465ce0, L_0x2464a90, C4<1>, C4<1>; +L_0x2464b50 .delay (20000,20000,20000) L_0x2464b50/d; +L_0x2464c60/d .functor AND 1, L_0x24648e0, L_0x2464f40, C4<1>, C4<1>; +L_0x2464c60 .delay (20000,20000,20000) L_0x2464c60/d; +L_0x2464d70/d .functor OR 1, L_0x2464b50, L_0x2464c60, C4<0>, C4<0>; +L_0x2464d70 .delay (20000,20000,20000) L_0x2464d70/d; +v0x245c500_0 .net "S", 0 0, L_0x2464f40; 1 drivers +v0x245c5c0_0 .alias "in0", 0 0, v0x245cc20_0; +v0x245c660_0 .alias "in1", 0 0, v0x245d0f0_0; +v0x245c700_0 .net "nS", 0 0, L_0x2464a90; 1 drivers +v0x245c780_0 .net "out0", 0 0, L_0x2464b50; 1 drivers +v0x245c820_0 .net "out1", 0 0, L_0x2464c60; 1 drivers +v0x245c900_0 .alias "outfinal", 0 0, v0x245ccd0_0; +S_0x245bdc0 .scope module, "setSLTres" "TwoInMux" 3 236, 3 8, S_0x24576a0; + .timescale -9 -12; +L_0x2465c80/d .functor NOT 1, L_0x24645d0, C4<0>, C4<0>, C4<0>; +L_0x2465c80 .delay (10000,10000,10000) L_0x2465c80/d; +L_0x24600c0/d .functor AND 1, L_0x2465e10, L_0x2465c80, C4<1>, C4<1>; +L_0x24600c0 .delay (20000,20000,20000) L_0x24600c0/d; +L_0x2466080/d .functor AND 1, C4<0>, L_0x24645d0, C4<1>, C4<1>; +L_0x2466080 .delay (20000,20000,20000) L_0x2466080/d; +L_0x2466120/d .functor OR 1, L_0x24600c0, L_0x2466080, C4<0>, C4<0>; +L_0x2466120 .delay (20000,20000,20000) L_0x2466120/d; +v0x245beb0_0 .alias "S", 0 0, v0x245da20_0; +v0x245bf50_0 .net "in0", 0 0, L_0x2465e10; 1 drivers +v0x245bff0_0 .net "in1", 0 0, C4<0>; 1 drivers +v0x245c090_0 .net "nS", 0 0, L_0x2465c80; 1 drivers +v0x245c140_0 .net "out0", 0 0, L_0x24600c0; 1 drivers +v0x245c1e0_0 .net "out1", 0 0, L_0x2466080; 1 drivers +v0x245c280_0 .net "outfinal", 0 0, L_0x2466120; 1 drivers +S_0x245a600 .scope generate, "addbits[1]" "addbits[1]" 3 244, 3 244, S_0x24576a0; + .timescale -9 -12; +P_0x245a6f8 .param/l "i" 3 244, +C4<01>; +S_0x245ad50 .scope module, "attempt" "MiddleAddSubSLT" 3 246, 3 89, S_0x245a600; + .timescale -9 -12; +L_0x2458b60/d .functor NOT 1, L_0x2460300, C4<0>, C4<0>, C4<0>; +L_0x2458b60 .delay (10000,10000,10000) L_0x2458b60/d; +L_0x245a370/d .functor NOT 1, L_0x24506a0, C4<0>, C4<0>, C4<0>; +L_0x245a370 .delay (10000,10000,10000) L_0x245a370/d; +L_0x2450740/d .functor AND 1, L_0x245f7d0, L_0x245a370, C4<1>, C4<1>; +L_0x2450740 .delay (20000,20000,20000) L_0x2450740/d; +L_0x245f870/d .functor XOR 1, L_0x2460150, L_0x245f100, C4<0>, C4<0>; +L_0x245f870 .delay (40000,40000,40000) L_0x245f870/d; +L_0x245f960/d .functor XOR 1, L_0x245f870, L_0x24604b0, C4<0>, C4<0>; +L_0x245f960 .delay (40000,40000,40000) L_0x245f960/d; +L_0x245fa50/d .functor AND 1, L_0x2460150, L_0x245f100, C4<1>, C4<1>; +L_0x245fa50 .delay (20000,20000,20000) L_0x245fa50/d; +L_0x245fbf0/d .functor AND 1, L_0x245f870, L_0x24604b0, C4<1>, C4<1>; +L_0x245fbf0 .delay (20000,20000,20000) L_0x245fbf0/d; +L_0x245fce0/d .functor OR 1, L_0x245fa50, L_0x245fbf0, C4<0>, C4<0>; +L_0x245fce0 .delay (20000,20000,20000) L_0x245fce0/d; +v0x245b3d0_0 .net "A", 0 0, L_0x2460150; 1 drivers +v0x245b490_0 .net "AandB", 0 0, L_0x245fa50; 1 drivers +v0x245b530_0 .net "AddSubSLTSum", 0 0, L_0x245f960; 1 drivers +v0x245b5d0_0 .net "AxorB", 0 0, L_0x245f870; 1 drivers +v0x245b650_0 .net "B", 0 0, L_0x2460300; 1 drivers +v0x245b700_0 .net "BornB", 0 0, L_0x245f100; 1 drivers +v0x245b7c0_0 .net "CINandAxorB", 0 0, L_0x245fbf0; 1 drivers +v0x245b840_0 .alias "Command", 2 0, v0x245d560_0; +v0x245b910_0 .net *"_s3", 0 0, L_0x24506a0; 1 drivers +v0x245b990_0 .net *"_s5", 0 0, L_0x245f7d0; 1 drivers +v0x245ba30_0 .net "carryin", 0 0, L_0x24604b0; 1 drivers +v0x245bad0_0 .net "carryout", 0 0, L_0x245fce0; 1 drivers +v0x245bb70_0 .net "nB", 0 0, L_0x2458b60; 1 drivers +v0x245bc20_0 .net "nCmd2", 0 0, L_0x245a370; 1 drivers +v0x245bd20_0 .net "subtract", 0 0, L_0x2450740; 1 drivers +L_0x245f2d0 .part v0x245e870_0, 0, 1; +L_0x24506a0 .part v0x245e870_0, 2, 1; +L_0x245f7d0 .part v0x245e870_0, 0, 1; +S_0x245ae40 .scope module, "mux0" "TwoInMux" 3 105, 3 8, S_0x245ad50; + .timescale -9 -12; +L_0x245ee60/d .functor NOT 1, L_0x245f2d0, C4<0>, C4<0>, C4<0>; +L_0x245ee60 .delay (10000,10000,10000) L_0x245ee60/d; +L_0x245eee0/d .functor AND 1, L_0x2460300, L_0x245ee60, C4<1>, C4<1>; +L_0x245eee0 .delay (20000,20000,20000) L_0x245eee0/d; +L_0x245eff0/d .functor AND 1, L_0x2458b60, L_0x245f2d0, C4<1>, C4<1>; +L_0x245eff0 .delay (20000,20000,20000) L_0x245eff0/d; +L_0x245f100/d .functor OR 1, L_0x245eee0, L_0x245eff0, C4<0>, C4<0>; +L_0x245f100 .delay (20000,20000,20000) L_0x245f100/d; +v0x245af30_0 .net "S", 0 0, L_0x245f2d0; 1 drivers +v0x245aff0_0 .alias "in0", 0 0, v0x245b650_0; +v0x245b090_0 .alias "in1", 0 0, v0x245bb70_0; +v0x245b130_0 .net "nS", 0 0, L_0x245ee60; 1 drivers +v0x245b1b0_0 .net "out0", 0 0, L_0x245eee0; 1 drivers +v0x245b250_0 .net "out1", 0 0, L_0x245eff0; 1 drivers +v0x245b330_0 .alias "outfinal", 0 0, v0x245b700_0; +S_0x245a7b0 .scope module, "setSLTres" "TwoInMux" 3 247, 3 8, S_0x245a600; + .timescale -9 -12; +L_0x2454450/d .functor NOT 1, L_0x24645d0, C4<0>, C4<0>, C4<0>; +L_0x2454450 .delay (10000,10000,10000) L_0x2454450/d; +L_0x24605e0/d .functor AND 1, L_0x24609e0, L_0x2454450, C4<1>, C4<1>; +L_0x24605e0 .delay (20000,20000,20000) L_0x24605e0/d; +L_0x24606d0/d .functor AND 1, C4<0>, L_0x24645d0, C4<1>, C4<1>; +L_0x24606d0 .delay (20000,20000,20000) L_0x24606d0/d; +L_0x2460770/d .functor OR 1, L_0x24605e0, L_0x24606d0, C4<0>, C4<0>; +L_0x2460770 .delay (20000,20000,20000) L_0x2460770/d; +v0x245a8a0_0 .alias "S", 0 0, v0x245da20_0; +v0x245a970_0 .net "in0", 0 0, L_0x24609e0; 1 drivers +v0x245aa10_0 .net "in1", 0 0, C4<0>; 1 drivers +v0x245aab0_0 .net "nS", 0 0, L_0x2454450; 1 drivers +v0x245ab30_0 .net "out0", 0 0, L_0x24605e0; 1 drivers +v0x245abd0_0 .net "out1", 0 0, L_0x24606d0; 1 drivers +v0x245acb0_0 .net "outfinal", 0 0, L_0x2460770; 1 drivers +S_0x2458f70 .scope generate, "addbits[2]" "addbits[2]" 3 244, 3 244, S_0x24576a0; + .timescale -9 -12; +P_0x2458928 .param/l "i" 3 244, +C4<010>; +S_0x2459670 .scope module, "attempt" "MiddleAddSubSLT" 3 246, 3 89, S_0x2458f70; + .timescale -9 -12; +L_0x2460b70/d .functor NOT 1, L_0x2461f80, C4<0>, C4<0>, C4<0>; +L_0x2460b70 .delay (10000,10000,10000) L_0x2460b70/d; +L_0x24612b0/d .functor NOT 1, L_0x2461370, C4<0>, C4<0>, C4<0>; +L_0x24612b0 .delay (10000,10000,10000) L_0x24612b0/d; +L_0x2461410/d .functor AND 1, L_0x2461550, L_0x24612b0, C4<1>, C4<1>; +L_0x2461410 .delay (20000,20000,20000) L_0x2461410/d; +L_0x24615f0/d .functor XOR 1, L_0x2461e70, L_0x2461040, C4<0>, C4<0>; +L_0x24615f0 .delay (40000,40000,40000) L_0x24615f0/d; +L_0x24616e0/d .functor XOR 1, L_0x24615f0, L_0x24620b0, C4<0>, C4<0>; +L_0x24616e0 .delay (40000,40000,40000) L_0x24616e0/d; +L_0x24617d0/d .functor AND 1, L_0x2461e70, L_0x2461040, C4<1>, C4<1>; +L_0x24617d0 .delay (20000,20000,20000) L_0x24617d0/d; +L_0x2461940/d .functor AND 1, L_0x24615f0, L_0x24620b0, C4<1>, C4<1>; +L_0x2461940 .delay (20000,20000,20000) L_0x2461940/d; +L_0x2461a30/d .functor OR 1, L_0x24617d0, L_0x2461940, C4<0>, C4<0>; +L_0x2461a30 .delay (20000,20000,20000) L_0x2461a30/d; +v0x2459cf0_0 .net "A", 0 0, L_0x2461e70; 1 drivers +v0x2459db0_0 .net "AandB", 0 0, L_0x24617d0; 1 drivers +v0x2459e50_0 .net "AddSubSLTSum", 0 0, L_0x24616e0; 1 drivers +v0x2459ef0_0 .net "AxorB", 0 0, L_0x24615f0; 1 drivers +v0x2459f70_0 .net "B", 0 0, L_0x2461f80; 1 drivers +v0x2459ff0_0 .net "BornB", 0 0, L_0x2461040; 1 drivers +v0x245a070_0 .net "CINandAxorB", 0 0, L_0x2461940; 1 drivers +v0x245a0f0_0 .alias "Command", 2 0, v0x245d560_0; +v0x245a170_0 .net *"_s3", 0 0, L_0x2461370; 1 drivers +v0x245a1f0_0 .net *"_s5", 0 0, L_0x2461550; 1 drivers +v0x245a270_0 .net "carryin", 0 0, L_0x24620b0; 1 drivers +v0x245a2f0_0 .net "carryout", 0 0, L_0x2461a30; 1 drivers +v0x245a3e0_0 .net "nB", 0 0, L_0x2460b70; 1 drivers +v0x245a460_0 .net "nCmd2", 0 0, L_0x24612b0; 1 drivers +v0x245a560_0 .net "subtract", 0 0, L_0x2461410; 1 drivers +L_0x2461210 .part v0x245e870_0, 0, 1; +L_0x2461370 .part v0x245e870_0, 2, 1; +L_0x2461550 .part v0x245e870_0, 0, 1; +S_0x2459760 .scope module, "mux0" "TwoInMux" 3 105, 3 8, S_0x2459670; + .timescale -9 -12; +L_0x2460d60/d .functor NOT 1, L_0x2461210, C4<0>, C4<0>, C4<0>; +L_0x2460d60 .delay (10000,10000,10000) L_0x2460d60/d; +L_0x2460e20/d .functor AND 1, L_0x2461f80, L_0x2460d60, C4<1>, C4<1>; +L_0x2460e20 .delay (20000,20000,20000) L_0x2460e20/d; +L_0x2460f30/d .functor AND 1, L_0x2460b70, L_0x2461210, C4<1>, C4<1>; +L_0x2460f30 .delay (20000,20000,20000) L_0x2460f30/d; +L_0x2461040/d .functor OR 1, L_0x2460e20, L_0x2460f30, C4<0>, C4<0>; +L_0x2461040 .delay (20000,20000,20000) L_0x2461040/d; +v0x2459850_0 .net "S", 0 0, L_0x2461210; 1 drivers +v0x2459910_0 .alias "in0", 0 0, v0x2459f70_0; +v0x24599b0_0 .alias "in1", 0 0, v0x245a3e0_0; +v0x2459a50_0 .net "nS", 0 0, L_0x2460d60; 1 drivers +v0x2459ad0_0 .net "out0", 0 0, L_0x2460e20; 1 drivers +v0x2459b70_0 .net "out1", 0 0, L_0x2460f30; 1 drivers +v0x2459c50_0 .alias "outfinal", 0 0, v0x2459ff0_0; +S_0x24590e0 .scope module, "setSLTres" "TwoInMux" 3 247, 3 8, S_0x2458f70; + .timescale -9 -12; +L_0x2461d70/d .functor NOT 1, L_0x24645d0, C4<0>, C4<0>, C4<0>; +L_0x2461d70 .delay (10000,10000,10000) L_0x2461d70/d; +L_0x24622a0/d .functor AND 1, L_0x2462660, L_0x2461d70, C4<1>, C4<1>; +L_0x24622a0 .delay (20000,20000,20000) L_0x24622a0/d; +L_0x2462360/d .functor AND 1, C4<0>, L_0x24645d0, C4<1>, C4<1>; +L_0x2462360 .delay (20000,20000,20000) L_0x2462360/d; +L_0x24624d0/d .functor OR 1, L_0x24622a0, L_0x2462360, C4<0>, C4<0>; +L_0x24624d0 .delay (20000,20000,20000) L_0x24624d0/d; +v0x24591d0_0 .alias "S", 0 0, v0x245da20_0; +v0x2459280_0 .net "in0", 0 0, L_0x2462660; 1 drivers +v0x2459300_0 .net "in1", 0 0, C4<0>; 1 drivers +v0x24593a0_0 .net "nS", 0 0, L_0x2461d70; 1 drivers +v0x2459450_0 .net "out0", 0 0, L_0x24622a0; 1 drivers +v0x24594f0_0 .net "out1", 0 0, L_0x2462360; 1 drivers +v0x24595d0_0 .net "outfinal", 0 0, L_0x24624d0; 1 drivers +S_0x2457810 .scope generate, "addbits[3]" "addbits[3]" 3 244, 3 244, S_0x24576a0; + .timescale -9 -12; +P_0x2457908 .param/l "i" 3 244, +C4<011>; +S_0x2457ef0 .scope module, "attempt" "MiddleAddSubSLT" 3 246, 3 89, S_0x2457810; + .timescale -9 -12; +L_0x24628b0/d .functor NOT 1, L_0x2463a90, C4<0>, C4<0>, C4<0>; +L_0x24628b0 .delay (10000,10000,10000) L_0x24628b0/d; +L_0x2462fd0/d .functor NOT 1, L_0x2463090, C4<0>, C4<0>, C4<0>; +L_0x2462fd0 .delay (10000,10000,10000) L_0x2462fd0/d; +L_0x2463130/d .functor AND 1, L_0x2463270, L_0x2462fd0, C4<1>, C4<1>; +L_0x2463130 .delay (20000,20000,20000) L_0x2463130/d; +L_0x2463310/d .functor XOR 1, L_0x2463bd0, L_0x2462d60, C4<0>, C4<0>; +L_0x2463310 .delay (40000,40000,40000) L_0x2463310/d; +L_0x2463400/d .functor XOR 1, L_0x2463310, L_0x2463db0, C4<0>, C4<0>; +L_0x2463400 .delay (40000,40000,40000) L_0x2463400/d; +L_0x24634f0/d .functor AND 1, L_0x2463bd0, L_0x2462d60, C4<1>, C4<1>; +L_0x24634f0 .delay (20000,20000,20000) L_0x24634f0/d; +L_0x2463660/d .functor AND 1, L_0x2463310, L_0x2463db0, C4<1>, C4<1>; +L_0x2463660 .delay (20000,20000,20000) L_0x2463660/d; +L_0x2463750/d .functor OR 1, L_0x24634f0, L_0x2463660, C4<0>, C4<0>; +L_0x2463750 .delay (20000,20000,20000) L_0x2463750/d; +v0x2458570_0 .net "A", 0 0, L_0x2463bd0; 1 drivers +v0x2458630_0 .net "AandB", 0 0, L_0x24634f0; 1 drivers +v0x24586d0_0 .net "AddSubSLTSum", 0 0, L_0x2463400; 1 drivers +v0x2458770_0 .net "AxorB", 0 0, L_0x2463310; 1 drivers +v0x24587f0_0 .net "B", 0 0, L_0x2463a90; 1 drivers +v0x24588a0_0 .net "BornB", 0 0, L_0x2462d60; 1 drivers +v0x2458960_0 .net "CINandAxorB", 0 0, L_0x2463660; 1 drivers +v0x24589e0_0 .alias "Command", 2 0, v0x245d560_0; +v0x2458a60_0 .net *"_s3", 0 0, L_0x2463090; 1 drivers +v0x2458ae0_0 .net *"_s5", 0 0, L_0x2463270; 1 drivers +v0x2458be0_0 .net "carryin", 0 0, L_0x2463db0; 1 drivers +v0x2458c80_0 .net "carryout", 0 0, L_0x2463750; 1 drivers +v0x2458d20_0 .net "nB", 0 0, L_0x24628b0; 1 drivers +v0x2458dd0_0 .net "nCmd2", 0 0, L_0x2462fd0; 1 drivers +v0x2458ed0_0 .net "subtract", 0 0, L_0x2463130; 1 drivers +L_0x2462f30 .part v0x245e870_0, 0, 1; +L_0x2463090 .part v0x245e870_0, 2, 1; +L_0x2463270 .part v0x245e870_0, 0, 1; +S_0x2457fe0 .scope module, "mux0" "TwoInMux" 3 105, 3 8, S_0x2457ef0; + .timescale -9 -12; +L_0x2462a80/d .functor NOT 1, L_0x2462f30, C4<0>, C4<0>, C4<0>; +L_0x2462a80 .delay (10000,10000,10000) L_0x2462a80/d; +L_0x2462b40/d .functor AND 1, L_0x2463a90, L_0x2462a80, C4<1>, C4<1>; +L_0x2462b40 .delay (20000,20000,20000) L_0x2462b40/d; +L_0x2462c50/d .functor AND 1, L_0x24628b0, L_0x2462f30, C4<1>, C4<1>; +L_0x2462c50 .delay (20000,20000,20000) L_0x2462c50/d; +L_0x2462d60/d .functor OR 1, L_0x2462b40, L_0x2462c50, C4<0>, C4<0>; +L_0x2462d60 .delay (20000,20000,20000) L_0x2462d60/d; +v0x24580d0_0 .net "S", 0 0, L_0x2462f30; 1 drivers +v0x2458190_0 .alias "in0", 0 0, v0x24587f0_0; +v0x2458230_0 .alias "in1", 0 0, v0x2458d20_0; +v0x24582d0_0 .net "nS", 0 0, L_0x2462a80; 1 drivers +v0x2458350_0 .net "out0", 0 0, L_0x2462b40; 1 drivers +v0x24583f0_0 .net "out1", 0 0, L_0x2462c50; 1 drivers +v0x24584d0_0 .alias "outfinal", 0 0, v0x24588a0_0; +S_0x2457980 .scope module, "setSLTres" "TwoInMux" 3 247, 3 8, S_0x2457810; + .timescale -9 -12; +L_0x2463c70/d .functor NOT 1, L_0x24645d0, C4<0>, C4<0>, C4<0>; +L_0x2463c70 .delay (10000,10000,10000) L_0x2463c70/d; +L_0x2463f10/d .functor AND 1, L_0x2464280, L_0x2463c70, C4<1>, C4<1>; +L_0x2463f10 .delay (20000,20000,20000) L_0x2463f10/d; +L_0x2464000/d .functor AND 1, C4<0>, L_0x24645d0, C4<1>, C4<1>; +L_0x2464000 .delay (20000,20000,20000) L_0x2464000/d; +L_0x24640a0/d .functor OR 1, L_0x2463f10, L_0x2464000, C4<0>, C4<0>; +L_0x24640a0 .delay (20000,20000,20000) L_0x24640a0/d; +v0x2457a70_0 .alias "S", 0 0, v0x245da20_0; +v0x2457b10_0 .net "in0", 0 0, L_0x2464280; 1 drivers +v0x2457bb0_0 .net "in1", 0 0, C4<0>; 1 drivers +v0x2457c50_0 .net "nS", 0 0, L_0x2463c70; 1 drivers +v0x2457cd0_0 .net "out0", 0 0, L_0x2463f10; 1 drivers +v0x2457d70_0 .net "out1", 0 0, L_0x2464000; 1 drivers +v0x2457e50_0 .net "outfinal", 0 0, L_0x24640a0; 1 drivers +S_0x24545e0 .scope module, "trial1" "AndNand32" 2 147, 3 154, S_0x23b34d0; + .timescale -9 -12; +P_0x2453fd8 .param/l "size" 3 161, +C4<0100>; +v0x24574a0_0 .alias "A", 3 0, v0x245d340_0; +v0x2457520_0 .alias "AndNandOut", 3 0, v0x245e770_0; +v0x24575a0_0 .alias "B", 3 0, v0x245d460_0; +v0x2457620_0 .alias "Command", 2 0, v0x245d560_0; +L_0x2467c20 .part/pv L_0x24679b0, 1, 1, 4; +L_0x2467d70 .part v0x245e5f0_0, 1, 1; +L_0x2467e10 .part v0x245e7f0_0, 1, 1; +L_0x24686d0 .part/pv L_0x2468460, 2, 1, 4; +L_0x2468770 .part v0x245e5f0_0, 2, 1; +L_0x2468810 .part v0x245e7f0_0, 2, 1; +L_0x2469140 .part/pv L_0x2468ed0, 3, 1, 4; +L_0x24691e0 .part v0x245e5f0_0, 3, 1; +L_0x24692d0 .part v0x245e7f0_0, 3, 1; +L_0x2469ba0 .part/pv L_0x2469930, 0, 1, 4; +L_0x2469ca0 .part v0x245e5f0_0, 0, 1; +L_0x2469d40 .part v0x245e7f0_0, 0, 1; +S_0x2456a70 .scope module, "attempt2" "AndNand" 3 165, 3 48, S_0x24545e0; + .timescale -9 -12; +L_0x24693c0/d .functor NAND 1, L_0x2469ca0, L_0x2469d40, C4<1>, C4<1>; +L_0x24693c0 .delay (10000,10000,10000) L_0x24693c0/d; +L_0x24694e0/d .functor NOT 1, L_0x24693c0, C4<0>, C4<0>, C4<0>; +L_0x24694e0 .delay (10000,10000,10000) L_0x24694e0/d; +v0x2457090_0 .net "A", 0 0, L_0x2469ca0; 1 drivers +v0x2457150_0 .net "AandB", 0 0, L_0x24694e0; 1 drivers +v0x24571d0_0 .net "AnandB", 0 0, L_0x24693c0; 1 drivers +v0x2457280_0 .net "AndNandOut", 0 0, L_0x2469930; 1 drivers +v0x2457360_0 .net "B", 0 0, L_0x2469d40; 1 drivers +v0x24573e0_0 .alias "Command", 2 0, v0x245d560_0; +L_0x2469b00 .part v0x245e870_0, 0, 1; +S_0x2456b60 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0x2456a70; + .timescale -9 -12; +L_0x2469610/d .functor NOT 1, L_0x2469b00, C4<0>, C4<0>, C4<0>; +L_0x2469610 .delay (10000,10000,10000) L_0x2469610/d; +L_0x24696d0/d .functor AND 1, L_0x24694e0, L_0x2469610, C4<1>, C4<1>; +L_0x24696d0 .delay (20000,20000,20000) L_0x24696d0/d; +L_0x24697e0/d .functor AND 1, L_0x24693c0, L_0x2469b00, C4<1>, C4<1>; +L_0x24697e0 .delay (20000,20000,20000) L_0x24697e0/d; +L_0x2469930/d .functor OR 1, L_0x24696d0, L_0x24697e0, C4<0>, C4<0>; +L_0x2469930 .delay (20000,20000,20000) L_0x2469930/d; +v0x2456c50_0 .net "S", 0 0, L_0x2469b00; 1 drivers +v0x2456cd0_0 .alias "in0", 0 0, v0x2457150_0; +v0x2456d50_0 .alias "in1", 0 0, v0x24571d0_0; +v0x2456df0_0 .net "nS", 0 0, L_0x2469610; 1 drivers +v0x2456e70_0 .net "out0", 0 0, L_0x24696d0; 1 drivers +v0x2456f10_0 .net "out1", 0 0, L_0x24697e0; 1 drivers +v0x2456ff0_0 .alias "outfinal", 0 0, v0x2457280_0; +S_0x2455eb0 .scope generate, "andbits[1]" "andbits[1]" 3 169, 3 169, S_0x24545e0; + .timescale -9 -12; +P_0x2455fa8 .param/l "i" 3 169, +C4<01>; +S_0x2456020 .scope module, "attempt" "AndNand" 3 171, 3 48, S_0x2455eb0; + .timescale -9 -12; +L_0x2467450/d .functor NAND 1, L_0x2467d70, L_0x2467e10, C4<1>, C4<1>; +L_0x2467450 .delay (10000,10000,10000) L_0x2467450/d; +L_0x2467560/d .functor NOT 1, L_0x2467450, C4<0>, C4<0>, C4<0>; +L_0x2467560 .delay (10000,10000,10000) L_0x2467560/d; +v0x2456660_0 .net "A", 0 0, L_0x2467d70; 1 drivers +v0x2456720_0 .net "AandB", 0 0, L_0x2467560; 1 drivers +v0x24567a0_0 .net "AnandB", 0 0, L_0x2467450; 1 drivers +v0x2456850_0 .net "AndNandOut", 0 0, L_0x24679b0; 1 drivers +v0x2456930_0 .net "B", 0 0, L_0x2467e10; 1 drivers +v0x24569b0_0 .alias "Command", 2 0, v0x245d560_0; +L_0x2467b80 .part v0x245e870_0, 0, 1; +S_0x2456110 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0x2456020; + .timescale -9 -12; +L_0x2467690/d .functor NOT 1, L_0x2467b80, C4<0>, C4<0>, C4<0>; +L_0x2467690 .delay (10000,10000,10000) L_0x2467690/d; +L_0x2467750/d .functor AND 1, L_0x2467560, L_0x2467690, C4<1>, C4<1>; +L_0x2467750 .delay (20000,20000,20000) L_0x2467750/d; +L_0x2467860/d .functor AND 1, L_0x2467450, L_0x2467b80, C4<1>, C4<1>; +L_0x2467860 .delay (20000,20000,20000) L_0x2467860/d; +L_0x24679b0/d .functor OR 1, L_0x2467750, L_0x2467860, C4<0>, C4<0>; +L_0x24679b0 .delay (20000,20000,20000) L_0x24679b0/d; +v0x2456200_0 .net "S", 0 0, L_0x2467b80; 1 drivers +v0x2456280_0 .alias "in0", 0 0, v0x2456720_0; +v0x2456320_0 .alias "in1", 0 0, v0x24567a0_0; +v0x24563c0_0 .net "nS", 0 0, L_0x2467690; 1 drivers +v0x2456440_0 .net "out0", 0 0, L_0x2467750; 1 drivers +v0x24564e0_0 .net "out1", 0 0, L_0x2467860; 1 drivers +v0x24565c0_0 .alias "outfinal", 0 0, v0x2456850_0; +S_0x24552f0 .scope generate, "andbits[2]" "andbits[2]" 3 169, 3 169, S_0x24545e0; + .timescale -9 -12; +P_0x24553e8 .param/l "i" 3 169, +C4<010>; +S_0x2455460 .scope module, "attempt" "AndNand" 3 171, 3 48, S_0x24552f0; + .timescale -9 -12; +L_0x2467eb0/d .functor NAND 1, L_0x2468770, L_0x2468810, C4<1>, C4<1>; +L_0x2467eb0 .delay (10000,10000,10000) L_0x2467eb0/d; +L_0x2468010/d .functor NOT 1, L_0x2467eb0, C4<0>, C4<0>, C4<0>; +L_0x2468010 .delay (10000,10000,10000) L_0x2468010/d; +v0x2455aa0_0 .net "A", 0 0, L_0x2468770; 1 drivers +v0x2455b60_0 .net "AandB", 0 0, L_0x2468010; 1 drivers +v0x2455be0_0 .net "AnandB", 0 0, L_0x2467eb0; 1 drivers +v0x2455c90_0 .net "AndNandOut", 0 0, L_0x2468460; 1 drivers +v0x2455d70_0 .net "B", 0 0, L_0x2468810; 1 drivers +v0x2455df0_0 .alias "Command", 2 0, v0x245d560_0; +L_0x2468630 .part v0x245e870_0, 0, 1; +S_0x2455550 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0x2455460; + .timescale -9 -12; +L_0x2468140/d .functor NOT 1, L_0x2468630, C4<0>, C4<0>, C4<0>; +L_0x2468140 .delay (10000,10000,10000) L_0x2468140/d; +L_0x2468200/d .functor AND 1, L_0x2468010, L_0x2468140, C4<1>, C4<1>; +L_0x2468200 .delay (20000,20000,20000) L_0x2468200/d; +L_0x2468310/d .functor AND 1, L_0x2467eb0, L_0x2468630, C4<1>, C4<1>; +L_0x2468310 .delay (20000,20000,20000) L_0x2468310/d; +L_0x2468460/d .functor OR 1, L_0x2468200, L_0x2468310, C4<0>, C4<0>; +L_0x2468460 .delay (20000,20000,20000) L_0x2468460/d; +v0x2455640_0 .net "S", 0 0, L_0x2468630; 1 drivers +v0x24556c0_0 .alias "in0", 0 0, v0x2455b60_0; +v0x2455760_0 .alias "in1", 0 0, v0x2455be0_0; +v0x2455800_0 .net "nS", 0 0, L_0x2468140; 1 drivers +v0x2455880_0 .net "out0", 0 0, L_0x2468200; 1 drivers +v0x2455920_0 .net "out1", 0 0, L_0x2468310; 1 drivers +v0x2455a00_0 .alias "outfinal", 0 0, v0x2455c90_0; +S_0x2454710 .scope generate, "andbits[3]" "andbits[3]" 3 169, 3 169, S_0x24545e0; + .timescale -9 -12; +P_0x2454808 .param/l "i" 3 169, +C4<011>; +S_0x2454880 .scope module, "attempt" "AndNand" 3 171, 3 48, S_0x2454710; + .timescale -9 -12; +L_0x2468940/d .functor NAND 1, L_0x24691e0, L_0x24692d0, C4<1>, C4<1>; +L_0x2468940 .delay (10000,10000,10000) L_0x2468940/d; +L_0x2468a80/d .functor NOT 1, L_0x2468940, C4<0>, C4<0>, C4<0>; +L_0x2468a80 .delay (10000,10000,10000) L_0x2468a80/d; +v0x2454ee0_0 .net "A", 0 0, L_0x24691e0; 1 drivers +v0x2454fa0_0 .net "AandB", 0 0, L_0x2468a80; 1 drivers +v0x2455020_0 .net "AnandB", 0 0, L_0x2468940; 1 drivers +v0x24550d0_0 .net "AndNandOut", 0 0, L_0x2468ed0; 1 drivers +v0x24551b0_0 .net "B", 0 0, L_0x24692d0; 1 drivers +v0x2455230_0 .alias "Command", 2 0, v0x245d560_0; +L_0x24690a0 .part v0x245e870_0, 0, 1; +S_0x2454970 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0x2454880; + .timescale -9 -12; +L_0x2468bb0/d .functor NOT 1, L_0x24690a0, C4<0>, C4<0>, C4<0>; +L_0x2468bb0 .delay (10000,10000,10000) L_0x2468bb0/d; +L_0x2468c70/d .functor AND 1, L_0x2468a80, L_0x2468bb0, C4<1>, C4<1>; +L_0x2468c70 .delay (20000,20000,20000) L_0x2468c70/d; +L_0x2468d80/d .functor AND 1, L_0x2468940, L_0x24690a0, C4<1>, C4<1>; +L_0x2468d80 .delay (20000,20000,20000) L_0x2468d80/d; +L_0x2468ed0/d .functor OR 1, L_0x2468c70, L_0x2468d80, C4<0>, C4<0>; +L_0x2468ed0 .delay (20000,20000,20000) L_0x2468ed0/d; +v0x2454a60_0 .net "S", 0 0, L_0x24690a0; 1 drivers +v0x2454b00_0 .alias "in0", 0 0, v0x2454fa0_0; +v0x2454ba0_0 .alias "in1", 0 0, v0x2455020_0; +v0x2454c40_0 .net "nS", 0 0, L_0x2468bb0; 1 drivers +v0x2454cc0_0 .net "out0", 0 0, L_0x2468c70; 1 drivers +v0x2454d60_0 .net "out1", 0 0, L_0x2468d80; 1 drivers +v0x2454e40_0 .alias "outfinal", 0 0, v0x24550d0_0; +S_0x244f3e0 .scope module, "trial2" "OrNorXor32" 2 149, 3 177, S_0x23b34d0; + .timescale -9 -12; +P_0x244cb98 .param/l "size" 3 184, +C4<0100>; +v0x24542c0_0 .alias "A", 3 0, v0x245d340_0; +v0x24543d0_0 .alias "B", 3 0, v0x245d460_0; +v0x24544e0_0 .alias "Command", 2 0, v0x245d560_0; +v0x2454560_0 .alias "OrNorXorOut", 3 0, v0x245e970_0; +L_0x246aef0 .part/pv L_0x246ac80, 1, 1, 4; +L_0x246b020 .part v0x245e5f0_0, 1, 1; +L_0x24601f0 .part v0x245e7f0_0, 1, 1; +L_0x246c450 .part/pv L_0x246c1e0, 2, 1, 4; +L_0x246c4f0 .part v0x245e5f0_0, 2, 1; +L_0x246c590 .part v0x245e7f0_0, 2, 1; +L_0x246d750 .part/pv L_0x246d4e0, 3, 1, 4; +L_0x246d7f0 .part v0x245e5f0_0, 3, 1; +L_0x246d890 .part v0x245e7f0_0, 3, 1; +L_0x246ea40 .part/pv L_0x246e7d0, 0, 1, 4; +L_0x246eb40 .part v0x245e5f0_0, 0, 1; +L_0x246ebe0 .part v0x245e7f0_0, 0, 1; +S_0x2453080 .scope module, "attempt2" "OrNorXor" 3 192, 3 64, S_0x244f3e0; + .timescale -9 -12; +L_0x246d930/d .functor NOR 1, L_0x246eb40, L_0x246ebe0, C4<0>, C4<0>; +L_0x246d930 .delay (10000,10000,10000) L_0x246d930/d; +L_0x246da30/d .functor NOT 1, L_0x246d930, C4<0>, C4<0>, C4<0>; +L_0x246da30 .delay (10000,10000,10000) L_0x246da30/d; +L_0x246db60/d .functor NAND 1, L_0x246eb40, L_0x246ebe0, C4<1>, C4<1>; +L_0x246db60 .delay (10000,10000,10000) L_0x246db60/d; +L_0x246dcc0/d .functor NAND 1, L_0x246db60, L_0x246da30, C4<1>, C4<1>; +L_0x246dcc0 .delay (10000,10000,10000) L_0x246dcc0/d; +L_0x246ddd0/d .functor NOT 1, L_0x246dcc0, C4<0>, C4<0>, C4<0>; +L_0x246ddd0 .delay (10000,10000,10000) L_0x246ddd0/d; +v0x2453bd0_0 .net "A", 0 0, L_0x246eb40; 1 drivers +v0x2453c70_0 .net "AnandB", 0 0, L_0x246db60; 1 drivers +v0x2453d10_0 .net "AnorB", 0 0, L_0x246d930; 1 drivers +v0x2453dc0_0 .net "AorB", 0 0, L_0x246da30; 1 drivers +v0x2453ea0_0 .net "AxorB", 0 0, L_0x246ddd0; 1 drivers +v0x2453f50_0 .net "B", 0 0, L_0x246ebe0; 1 drivers +v0x2454010_0 .alias "Command", 2 0, v0x245d560_0; +v0x2454090_0 .net "OrNorXorOut", 0 0, L_0x246e7d0; 1 drivers +v0x2454110_0 .net "XorNor", 0 0, L_0x246e250; 1 drivers +v0x24541e0_0 .net "nXor", 0 0, L_0x246dcc0; 1 drivers +L_0x246e3d0 .part v0x245e870_0, 2, 1; +L_0x246e9a0 .part v0x245e870_0, 0, 1; +S_0x2453660 .scope module, "mux0" "TwoInMux" 3 83, 3 8, S_0x2453080; + .timescale -9 -12; +L_0x246df30/d .functor NOT 1, L_0x246e3d0, C4<0>, C4<0>, C4<0>; +L_0x246df30 .delay (10000,10000,10000) L_0x246df30/d; +L_0x246dff0/d .functor AND 1, L_0x246ddd0, L_0x246df30, C4<1>, C4<1>; +L_0x246dff0 .delay (20000,20000,20000) L_0x246dff0/d; +L_0x246e100/d .functor AND 1, L_0x246d930, L_0x246e3d0, C4<1>, C4<1>; +L_0x246e100 .delay (20000,20000,20000) L_0x246e100/d; +L_0x246e250/d .functor OR 1, L_0x246dff0, L_0x246e100, C4<0>, C4<0>; +L_0x246e250 .delay (20000,20000,20000) L_0x246e250/d; +v0x2453750_0 .net "S", 0 0, L_0x246e3d0; 1 drivers +v0x2453810_0 .alias "in0", 0 0, v0x2453ea0_0; +v0x24538b0_0 .alias "in1", 0 0, v0x2453d10_0; +v0x2453950_0 .net "nS", 0 0, L_0x246df30; 1 drivers +v0x24539d0_0 .net "out0", 0 0, L_0x246dff0; 1 drivers +v0x2453a70_0 .net "out1", 0 0, L_0x246e100; 1 drivers +v0x2453b50_0 .alias "outfinal", 0 0, v0x2454110_0; +S_0x2453170 .scope module, "mux1" "TwoInMux" 3 84, 3 8, S_0x2453080; + .timescale -9 -12; +L_0x246e470/d .functor NOT 1, L_0x246e9a0, C4<0>, C4<0>, C4<0>; +L_0x246e470 .delay (10000,10000,10000) L_0x246e470/d; +L_0x246e530/d .functor AND 1, L_0x246e250, L_0x246e470, C4<1>, C4<1>; +L_0x246e530 .delay (20000,20000,20000) L_0x246e530/d; +L_0x246e680/d .functor AND 1, L_0x246da30, L_0x246e9a0, C4<1>, C4<1>; +L_0x246e680 .delay (20000,20000,20000) L_0x246e680/d; +L_0x246e7d0/d .functor OR 1, L_0x246e530, L_0x246e680, C4<0>, C4<0>; +L_0x246e7d0 .delay (20000,20000,20000) L_0x246e7d0/d; +v0x2453260_0 .net "S", 0 0, L_0x246e9a0; 1 drivers +v0x24532e0_0 .alias "in0", 0 0, v0x2454110_0; +v0x2453360_0 .alias "in1", 0 0, v0x2453dc0_0; +v0x2453400_0 .net "nS", 0 0, L_0x246e470; 1 drivers +v0x2453480_0 .net "out0", 0 0, L_0x246e530; 1 drivers +v0x2453520_0 .net "out1", 0 0, L_0x246e680; 1 drivers +v0x24535c0_0 .alias "outfinal", 0 0, v0x2454090_0; +S_0x2451cb0 .scope generate, "orbits[1]" "orbits[1]" 3 196, 3 196, S_0x244f3e0; + .timescale -9 -12; +P_0x24519c8 .param/l "i" 3 196, +C4<01>; +S_0x2451de0 .scope module, "attempt" "OrNorXor" 3 198, 3 64, S_0x2451cb0; + .timescale -9 -12; +L_0x2469c40/d .functor NOR 1, L_0x246b020, L_0x24601f0, C4<0>, C4<0>; +L_0x2469c40 .delay (10000,10000,10000) L_0x2469c40/d; +L_0x2469ee0/d .functor NOT 1, L_0x2469c40, C4<0>, C4<0>, C4<0>; +L_0x2469ee0 .delay (10000,10000,10000) L_0x2469ee0/d; +L_0x246a010/d .functor NAND 1, L_0x246b020, L_0x24601f0, C4<1>, C4<1>; +L_0x246a010 .delay (10000,10000,10000) L_0x246a010/d; +L_0x246a170/d .functor NAND 1, L_0x246a010, L_0x2469ee0, C4<1>, C4<1>; +L_0x246a170 .delay (10000,10000,10000) L_0x246a170/d; +L_0x246a280/d .functor NOT 1, L_0x246a170, C4<0>, C4<0>, C4<0>; +L_0x246a280 .delay (10000,10000,10000) L_0x246a280/d; +v0x2452990_0 .net "A", 0 0, L_0x246b020; 1 drivers +v0x2452a30_0 .net "AnandB", 0 0, L_0x246a010; 1 drivers +v0x2452ad0_0 .net "AnorB", 0 0, L_0x2469c40; 1 drivers +v0x2452b80_0 .net "AorB", 0 0, L_0x2469ee0; 1 drivers +v0x2452c60_0 .net "AxorB", 0 0, L_0x246a280; 1 drivers +v0x2452d10_0 .net "B", 0 0, L_0x24601f0; 1 drivers +v0x2452dd0_0 .alias "Command", 2 0, v0x245d560_0; +v0x2452e50_0 .net "OrNorXorOut", 0 0, L_0x246ac80; 1 drivers +v0x2452ed0_0 .net "XorNor", 0 0, L_0x246a700; 1 drivers +v0x2452fa0_0 .net "nXor", 0 0, L_0x246a170; 1 drivers +L_0x246a880 .part v0x245e870_0, 2, 1; +L_0x246ae50 .part v0x245e870_0, 0, 1; +S_0x2452420 .scope module, "mux0" "TwoInMux" 3 83, 3 8, S_0x2451de0; + .timescale -9 -12; +L_0x246a3e0/d .functor NOT 1, L_0x246a880, C4<0>, C4<0>, C4<0>; +L_0x246a3e0 .delay (10000,10000,10000) L_0x246a3e0/d; +L_0x246a4a0/d .functor AND 1, L_0x246a280, L_0x246a3e0, C4<1>, C4<1>; +L_0x246a4a0 .delay (20000,20000,20000) L_0x246a4a0/d; +L_0x246a5b0/d .functor AND 1, L_0x2469c40, L_0x246a880, C4<1>, C4<1>; +L_0x246a5b0 .delay (20000,20000,20000) L_0x246a5b0/d; +L_0x246a700/d .functor OR 1, L_0x246a4a0, L_0x246a5b0, C4<0>, C4<0>; +L_0x246a700 .delay (20000,20000,20000) L_0x246a700/d; +v0x2452510_0 .net "S", 0 0, L_0x246a880; 1 drivers +v0x24525d0_0 .alias "in0", 0 0, v0x2452c60_0; +v0x2452670_0 .alias "in1", 0 0, v0x2452ad0_0; +v0x2452710_0 .net "nS", 0 0, L_0x246a3e0; 1 drivers +v0x2452790_0 .net "out0", 0 0, L_0x246a4a0; 1 drivers +v0x2452830_0 .net "out1", 0 0, L_0x246a5b0; 1 drivers +v0x2452910_0 .alias "outfinal", 0 0, v0x2452ed0_0; +S_0x2451ed0 .scope module, "mux1" "TwoInMux" 3 84, 3 8, S_0x2451de0; + .timescale -9 -12; +L_0x246a920/d .functor NOT 1, L_0x246ae50, C4<0>, C4<0>, C4<0>; +L_0x246a920 .delay (10000,10000,10000) L_0x246a920/d; +L_0x246a9e0/d .functor AND 1, L_0x246a700, L_0x246a920, C4<1>, C4<1>; +L_0x246a9e0 .delay (20000,20000,20000) L_0x246a9e0/d; +L_0x246ab30/d .functor AND 1, L_0x2469ee0, L_0x246ae50, C4<1>, C4<1>; +L_0x246ab30 .delay (20000,20000,20000) L_0x246ab30/d; +L_0x246ac80/d .functor OR 1, L_0x246a9e0, L_0x246ab30, C4<0>, C4<0>; +L_0x246ac80 .delay (20000,20000,20000) L_0x246ac80/d; +v0x2451fc0_0 .net "S", 0 0, L_0x246ae50; 1 drivers +v0x2452040_0 .alias "in0", 0 0, v0x2452ed0_0; +v0x24520e0_0 .alias "in1", 0 0, v0x2452b80_0; +v0x2452180_0 .net "nS", 0 0, L_0x246a920; 1 drivers +v0x2452200_0 .net "out0", 0 0, L_0x246a9e0; 1 drivers +v0x24522a0_0 .net "out1", 0 0, L_0x246ab30; 1 drivers +v0x2452380_0 .alias "outfinal", 0 0, v0x2452e50_0; +S_0x24508e0 .scope generate, "orbits[2]" "orbits[2]" 3 196, 3 196, S_0x244f3e0; + .timescale -9 -12; +P_0x2450598 .param/l "i" 3 196, +C4<010>; +S_0x2450a10 .scope module, "attempt" "OrNorXor" 3 198, 3 64, S_0x24508e0; + .timescale -9 -12; +L_0x2460290/d .functor NOR 1, L_0x246c4f0, L_0x246c590, C4<0>, C4<0>; +L_0x2460290 .delay (10000,10000,10000) L_0x2460290/d; +L_0x2460400/d .functor NOT 1, L_0x2460290, C4<0>, C4<0>, C4<0>; +L_0x2460400 .delay (10000,10000,10000) L_0x2460400/d; +L_0x246b570/d .functor NAND 1, L_0x246c4f0, L_0x246c590, C4<1>, C4<1>; +L_0x246b570 .delay (10000,10000,10000) L_0x246b570/d; +L_0x246b6d0/d .functor NAND 1, L_0x246b570, L_0x2460400, C4<1>, C4<1>; +L_0x246b6d0 .delay (10000,10000,10000) L_0x246b6d0/d; +L_0x246b7e0/d .functor NOT 1, L_0x246b6d0, C4<0>, C4<0>, C4<0>; +L_0x246b7e0 .delay (10000,10000,10000) L_0x246b7e0/d; +v0x24515c0_0 .net "A", 0 0, L_0x246c4f0; 1 drivers +v0x2451660_0 .net "AnandB", 0 0, L_0x246b570; 1 drivers +v0x2451700_0 .net "AnorB", 0 0, L_0x2460290; 1 drivers +v0x24517b0_0 .net "AorB", 0 0, L_0x2460400; 1 drivers +v0x2451890_0 .net "AxorB", 0 0, L_0x246b7e0; 1 drivers +v0x2451940_0 .net "B", 0 0, L_0x246c590; 1 drivers +v0x2451a00_0 .alias "Command", 2 0, v0x245d560_0; +v0x2451a80_0 .net "OrNorXorOut", 0 0, L_0x246c1e0; 1 drivers +v0x2451b00_0 .net "XorNor", 0 0, L_0x246bc60; 1 drivers +v0x2451bd0_0 .net "nXor", 0 0, L_0x246b6d0; 1 drivers +L_0x246bde0 .part v0x245e870_0, 2, 1; +L_0x246c3b0 .part v0x245e870_0, 0, 1; +S_0x2451050 .scope module, "mux0" "TwoInMux" 3 83, 3 8, S_0x2450a10; + .timescale -9 -12; +L_0x246b940/d .functor NOT 1, L_0x246bde0, C4<0>, C4<0>, C4<0>; +L_0x246b940 .delay (10000,10000,10000) L_0x246b940/d; +L_0x246ba00/d .functor AND 1, L_0x246b7e0, L_0x246b940, C4<1>, C4<1>; +L_0x246ba00 .delay (20000,20000,20000) L_0x246ba00/d; +L_0x246bb10/d .functor AND 1, L_0x2460290, L_0x246bde0, C4<1>, C4<1>; +L_0x246bb10 .delay (20000,20000,20000) L_0x246bb10/d; +L_0x246bc60/d .functor OR 1, L_0x246ba00, L_0x246bb10, C4<0>, C4<0>; +L_0x246bc60 .delay (20000,20000,20000) L_0x246bc60/d; +v0x2451140_0 .net "S", 0 0, L_0x246bde0; 1 drivers +v0x2451200_0 .alias "in0", 0 0, v0x2451890_0; +v0x24512a0_0 .alias "in1", 0 0, v0x2451700_0; +v0x2451340_0 .net "nS", 0 0, L_0x246b940; 1 drivers +v0x24513c0_0 .net "out0", 0 0, L_0x246ba00; 1 drivers +v0x2451460_0 .net "out1", 0 0, L_0x246bb10; 1 drivers +v0x2451540_0 .alias "outfinal", 0 0, v0x2451b00_0; +S_0x2450b00 .scope module, "mux1" "TwoInMux" 3 84, 3 8, S_0x2450a10; + .timescale -9 -12; +L_0x246be80/d .functor NOT 1, L_0x246c3b0, C4<0>, C4<0>, C4<0>; +L_0x246be80 .delay (10000,10000,10000) L_0x246be80/d; +L_0x246bf40/d .functor AND 1, L_0x246bc60, L_0x246be80, C4<1>, C4<1>; +L_0x246bf40 .delay (20000,20000,20000) L_0x246bf40/d; +L_0x246c090/d .functor AND 1, L_0x2460400, L_0x246c3b0, C4<1>, C4<1>; +L_0x246c090 .delay (20000,20000,20000) L_0x246c090/d; +L_0x246c1e0/d .functor OR 1, L_0x246bf40, L_0x246c090, C4<0>, C4<0>; +L_0x246c1e0 .delay (20000,20000,20000) L_0x246c1e0/d; +v0x2450bf0_0 .net "S", 0 0, L_0x246c3b0; 1 drivers +v0x2450c70_0 .alias "in0", 0 0, v0x2451b00_0; +v0x2450d10_0 .alias "in1", 0 0, v0x24517b0_0; +v0x2450db0_0 .net "nS", 0 0, L_0x246be80; 1 drivers +v0x2450e30_0 .net "out0", 0 0, L_0x246bf40; 1 drivers +v0x2450ed0_0 .net "out1", 0 0, L_0x246c090; 1 drivers +v0x2450fb0_0 .alias "outfinal", 0 0, v0x2451a80_0; +S_0x244f4d0 .scope generate, "orbits[3]" "orbits[3]" 3 196, 3 196, S_0x244f3e0; + .timescale -9 -12; +P_0x244f218 .param/l "i" 3 196, +C4<011>; +S_0x244f5c0 .scope module, "attempt" "OrNorXor" 3 198, 3 64, S_0x244f4d0; + .timescale -9 -12; +L_0x246c670/d .functor NOR 1, L_0x246d7f0, L_0x246d890, C4<0>, C4<0>; +L_0x246c670 .delay (10000,10000,10000) L_0x246c670/d; +L_0x246c760/d .functor NOT 1, L_0x246c670, C4<0>, C4<0>, C4<0>; +L_0x246c760 .delay (10000,10000,10000) L_0x246c760/d; +L_0x246c870/d .functor NAND 1, L_0x246d7f0, L_0x246d890, C4<1>, C4<1>; +L_0x246c870 .delay (10000,10000,10000) L_0x246c870/d; +L_0x246c9d0/d .functor NAND 1, L_0x246c870, L_0x246c760, C4<1>, C4<1>; +L_0x246c9d0 .delay (10000,10000,10000) L_0x246c9d0/d; +L_0x246cae0/d .functor NOT 1, L_0x246c9d0, C4<0>, C4<0>, C4<0>; +L_0x246cae0 .delay (10000,10000,10000) L_0x246cae0/d; +v0x2450190_0 .net "A", 0 0, L_0x246d7f0; 1 drivers +v0x2450230_0 .net "AnandB", 0 0, L_0x246c870; 1 drivers +v0x24502d0_0 .net "AnorB", 0 0, L_0x246c670; 1 drivers +v0x2450380_0 .net "AorB", 0 0, L_0x246c760; 1 drivers +v0x2450460_0 .net "AxorB", 0 0, L_0x246cae0; 1 drivers +v0x2450510_0 .net "B", 0 0, L_0x246d890; 1 drivers +v0x24505d0_0 .alias "Command", 2 0, v0x245d560_0; +v0x24471c0_0 .net "OrNorXorOut", 0 0, L_0x246d4e0; 1 drivers +v0x2447240_0 .net "XorNor", 0 0, L_0x246cf60; 1 drivers +v0x2450860_0 .net "nXor", 0 0, L_0x246c9d0; 1 drivers +L_0x246d0e0 .part v0x245e870_0, 2, 1; +L_0x246d6b0 .part v0x245e870_0, 0, 1; +S_0x244fc20 .scope module, "mux0" "TwoInMux" 3 83, 3 8, S_0x244f5c0; + .timescale -9 -12; +L_0x246cc40/d .functor NOT 1, L_0x246d0e0, C4<0>, C4<0>, C4<0>; +L_0x246cc40 .delay (10000,10000,10000) L_0x246cc40/d; +L_0x246cd00/d .functor AND 1, L_0x246cae0, L_0x246cc40, C4<1>, C4<1>; +L_0x246cd00 .delay (20000,20000,20000) L_0x246cd00/d; +L_0x246ce10/d .functor AND 1, L_0x246c670, L_0x246d0e0, C4<1>, C4<1>; +L_0x246ce10 .delay (20000,20000,20000) L_0x246ce10/d; +L_0x246cf60/d .functor OR 1, L_0x246cd00, L_0x246ce10, C4<0>, C4<0>; +L_0x246cf60 .delay (20000,20000,20000) L_0x246cf60/d; +v0x244fd10_0 .net "S", 0 0, L_0x246d0e0; 1 drivers +v0x244fdd0_0 .alias "in0", 0 0, v0x2450460_0; +v0x244fe70_0 .alias "in1", 0 0, v0x24502d0_0; +v0x244ff10_0 .net "nS", 0 0, L_0x246cc40; 1 drivers +v0x244ff90_0 .net "out0", 0 0, L_0x246cd00; 1 drivers +v0x2450030_0 .net "out1", 0 0, L_0x246ce10; 1 drivers +v0x2450110_0 .alias "outfinal", 0 0, v0x2447240_0; +S_0x244f6b0 .scope module, "mux1" "TwoInMux" 3 84, 3 8, S_0x244f5c0; + .timescale -9 -12; +L_0x246d180/d .functor NOT 1, L_0x246d6b0, C4<0>, C4<0>, C4<0>; +L_0x246d180 .delay (10000,10000,10000) L_0x246d180/d; +L_0x246d240/d .functor AND 1, L_0x246cf60, L_0x246d180, C4<1>, C4<1>; +L_0x246d240 .delay (20000,20000,20000) L_0x246d240/d; +L_0x246d390/d .functor AND 1, L_0x246c760, L_0x246d6b0, C4<1>, C4<1>; +L_0x246d390 .delay (20000,20000,20000) L_0x246d390/d; +L_0x246d4e0/d .functor OR 1, L_0x246d240, L_0x246d390, C4<0>, C4<0>; +L_0x246d4e0 .delay (20000,20000,20000) L_0x246d4e0/d; +v0x244f7a0_0 .net "S", 0 0, L_0x246d6b0; 1 drivers +v0x244f840_0 .alias "in0", 0 0, v0x2447240_0; +v0x244f8e0_0 .alias "in1", 0 0, v0x2450380_0; +v0x244f980_0 .net "nS", 0 0, L_0x246d180; 1 drivers +v0x244fa00_0 .net "out0", 0 0, L_0x246d240; 1 drivers +v0x244faa0_0 .net "out1", 0 0, L_0x246d390; 1 drivers +v0x244fb80_0 .alias "outfinal", 0 0, v0x24471c0_0; +S_0x23d85b0 .scope module, "superalu" "Bitslice32" 2 151, 3 286, S_0x23b34d0; + .timescale -9 -12; +P_0x23b1ea8 .param/l "size" 3 303, +C4<0100>; +L_0x2473c50/d .functor AND 1, L_0x2488450, L_0x2488630, C4<1>, C4<1>; +L_0x2473c50 .delay (20000,20000,20000) L_0x2473c50/d; +L_0x2488720/d .functor NOT 1, L_0x24887d0, C4<0>, C4<0>, C4<0>; +L_0x2488720 .delay (10000,10000,10000) L_0x2488720/d; +L_0x2488c80/d .functor AND 1, L_0x2488720, L_0x2488720, C4<1>, C4<1>; +L_0x2488c80 .delay (20000,20000,20000) L_0x2488c80/d; +v0x244e420_0 .alias "A", 3 0, v0x245d340_0; +v0x244e4c0_0 .alias "AddSubSLTSum", 3 0, v0x245e670_0; +v0x244e540_0 .alias "AllZeros", 0 0, v0x245e6f0_0; +v0x244e5c0_0 .alias "AndNandOut", 3 0, v0x245e770_0; +v0x244e670_0 .alias "B", 3 0, v0x245d460_0; +RS_0x7f3880bf1518 .resolv tri, L_0x246f380, L_0x2471c60, L_0x24749e0, L_0x2486820; +v0x244e6f0_0 .net8 "Cmd0Start", 3 0, RS_0x7f3880bf1518; 4 drivers +RS_0x7f3880bf1548 .resolv tri, L_0x24701d0, L_0x2472ed0, L_0x24759d0, L_0x2487650; +v0x244e770_0 .net8 "Cmd1Start", 3 0, RS_0x7f3880bf1548; 4 drivers +v0x244e7f0_0 .alias "Command", 2 0, v0x245d560_0; +v0x244e870_0 .alias "OneBitFinalOut", 3 0, v0x245e8f0_0; +v0x244e910_0 .alias "OrNorXorOut", 3 0, v0x245e970_0; +v0x244e990_0 .alias "SLTflag", 0 0, v0x245ea40_0; +v0x244ea40_0 .alias "ZeroFlag", 3 0, v0x245eac0_0; +v0x244eac0_0 .net *"_s111", 0 0, L_0x2473c50; 1 drivers +v0x244eb40_0 .net *"_s114", 0 0, L_0x2488450; 1 drivers +v0x244ec60_0 .net *"_s116", 0 0, L_0x2488630; 1 drivers +v0x244ed00_0 .net *"_s118", 0 0, L_0x24887d0; 1 drivers +v0x244ebc0_0 .net *"_s21", 0 0, L_0x2471220; 1 drivers +v0x244ee50_0 .net *"_s46", 0 0, L_0x2473520; 1 drivers +v0x244ef70_0 .net *"_s71", 0 0, L_0x2476790; 1 drivers +v0x244eff0_0 .alias "carryin", 3 0, v0x245df60_0; +v0x244eed0_0 .alias "carryout", 0 0, v0x245ebc0_0; +v0x244f150_0 .alias "overflow", 0 0, v0x245ec40_0; +v0x244f070_0 .alias "subtract", 3 0, v0x245ecc0_0; +v0x244f290_0 .net "yeszero", 0 0, L_0x2488720; 1 drivers +L_0x246f380 .part/pv L_0x246f1a0, 1, 1, 4; +L_0x246f420 .part v0x245e870_0, 0, 1; +L_0x246f550 .part v0x245e870_0, 1, 1; +L_0x246f680 .part RS_0x7f3880bf1098, 1, 1; +L_0x246f720 .part RS_0x7f3880bf1098, 1, 1; +L_0x246f7c0 .part RS_0x7f3880bef748, 1, 1; +L_0x246f9c0 .part RS_0x7f3880bf1098, 1, 1; +L_0x24701d0 .part/pv L_0x246fff0, 1, 1, 4; +L_0x24702c0 .part v0x245e870_0, 0, 1; +L_0x24703f0 .part v0x245e870_0, 1, 1; +L_0x2470580 .part RS_0x7f3880befe38, 1, 1; +L_0x2470730 .part RS_0x7f3880befe38, 1, 1; +L_0x24707d0 .part RS_0x7f3880bef748, 1, 1; +L_0x2470870 .part RS_0x7f3880bef748, 1, 1; +L_0x2470cd0 .part/pv L_0x2470b90, 1, 1, 4; +L_0x2470dc0 .part v0x245e870_0, 2, 1; +L_0x2470e60 .part RS_0x7f3880bf1518, 1, 1; +L_0x2470fa0 .part RS_0x7f3880bf1548, 1, 1; +L_0x2471180 .part/pv L_0x2471220, 1, 1, 4; +L_0x2471320 .part RS_0x7f3880bf15a8, 0, 1; +L_0x24710e0 .part RS_0x7f3880bf1578, 1, 1; +L_0x2471c60 .part/pv L_0x2471a50, 2, 1, 4; +L_0x24713c0 .part v0x245e870_0, 0, 1; +L_0x245f370 .part v0x245e870_0, 1, 1; +L_0x2471d00 .part RS_0x7f3880bf1098, 2, 1; +L_0x245f570 .part RS_0x7f3880bf1098, 2, 1; +L_0x245f4a0 .part RS_0x7f3880bef748, 2, 1; +L_0x2472660 .part RS_0x7f3880bf1098, 2, 1; +L_0x2472ed0 .part/pv L_0x2472cc0, 2, 1, 4; +L_0x2472f70 .part v0x245e870_0, 0, 1; +L_0x2472700 .part v0x245e870_0, 1, 1; +L_0x2473230 .part RS_0x7f3880befe38, 2, 1; +L_0x24730a0 .part RS_0x7f3880befe38, 2, 1; +L_0x24733e0 .part RS_0x7f3880bef748, 2, 1; +L_0x24732d0 .part RS_0x7f3880bef748, 2, 1; +L_0x2473950 .part/pv L_0x2473810, 2, 1, 4; +L_0x2473480 .part v0x245e870_0, 2, 1; +L_0x2473bb0 .part RS_0x7f3880bf1518, 2, 1; +L_0x2473a80 .part RS_0x7f3880bf1548, 2, 1; +L_0x2473e20 .part/pv L_0x2473520, 2, 1, 4; +L_0x2473d20 .part RS_0x7f3880bf15a8, 1, 1; +L_0x24740a0 .part RS_0x7f3880bf1578, 2, 1; +L_0x24749e0 .part/pv L_0x24747d0, 3, 1, 4; +L_0x2474a80 .part v0x245e870_0, 0, 1; +L_0x2474140 .part v0x245e870_0, 1, 1; +L_0x2474d20 .part RS_0x7f3880bf1098, 3, 1; +L_0x2466c90 .part RS_0x7f3880bf1098, 3, 1; +L_0x2474bb0 .part RS_0x7f3880bef748, 3, 1; +L_0x2475160 .part RS_0x7f3880bf1098, 3, 1; +L_0x24759d0 .part/pv L_0x24757c0, 3, 1, 4; +L_0x2474fd0 .part v0x245e870_0, 0, 1; +L_0x2475c10 .part v0x245e870_0, 1, 1; +L_0x2475a70 .part RS_0x7f3880befe38, 3, 1; +L_0x2475b10 .part RS_0x7f3880befe38, 3, 1; +L_0x2475f00 .part RS_0x7f3880bef748, 3, 1; +L_0x2475fa0 .part RS_0x7f3880bef748, 3, 1; +L_0x24765b0 .part/pv L_0x2476470, 3, 1, 4; +L_0x2476650 .part v0x245e870_0, 2, 1; +L_0x2476250 .part RS_0x7f3880bf1518, 3, 1; +L_0x2476340 .part RS_0x7f3880bf1548, 3, 1; +L_0x24766f0 .part/pv L_0x2476790, 3, 1, 4; +L_0x2476b10 .part RS_0x7f3880bf15a8, 2, 1; +L_0x2476920 .part RS_0x7f3880bf1578, 3, 1; +L_0x2486820 .part/pv L_0x2486640, 0, 1, 4; +L_0x2476bb0 .part v0x245e870_0, 0, 1; +L_0x2476ce0 .part v0x245e870_0, 1, 1; +L_0x24868c0 .part RS_0x7f3880bf1098, 0, 1; +L_0x2486960 .part RS_0x7f3880bf1098, 0, 1; +L_0x2486a00 .part RS_0x7f3880bef748, 0, 1; +L_0x2486de0 .part RS_0x7f3880bf1098, 0, 1; +L_0x2487650 .part/pv L_0x2487470, 0, 1, 4; +L_0x24876f0 .part v0x245e870_0, 0, 1; +L_0x2486ed0 .part v0x245e870_0, 1, 1; +L_0x2487000 .part RS_0x7f3880befe38, 0, 1; +L_0x2487a80 .part RS_0x7f3880befe38, 0, 1; +L_0x2487b20 .part RS_0x7f3880bef748, 0, 1; +L_0x2487820 .part RS_0x7f3880bef748, 0, 1; +L_0x24880f0 .part/pv L_0x2487fb0, 0, 1, 4; +L_0x2487bc0 .part v0x245e870_0, 2, 1; +L_0x2487c60 .part RS_0x7f3880bf1518, 0, 1; +L_0x2487d50 .part RS_0x7f3880bf1548, 0, 1; +L_0x24883b0 .part/pv L_0x2473c50, 0, 1, 4; +L_0x2488450 .part RS_0x7f3880bf1578, 0, 1; +L_0x2488630 .part RS_0x7f3880bf1578, 0, 1; +L_0x24887d0 .part RS_0x7f3880bf15a8, 3, 1; +S_0x24474b0 .scope module, "trial" "AddSubSLT32" 3 311, 3 205, S_0x23d85b0; + .timescale -9 -12; +P_0x24475a8 .param/l "size" 3 242, +C4<0100>; +L_0x247bc90/d .functor NOT 1, L_0x247bd40, C4<0>, C4<0>, C4<0>; +L_0x247bc90 .delay (10000,10000,10000) L_0x247bc90/d; +L_0x247bde0/d .functor AND 1, L_0x247bf20, L_0x247bb70, L_0x247bc90, C4<1>; +L_0x247bde0 .delay (20000,20000,20000) L_0x247bde0/d; +L_0x247dbf0/d .functor OR 1, L_0x247dce0, C4<0>, C4<0>, C4<0>; +L_0x247dbf0 .delay (20000,20000,20000) L_0x247dbf0/d; +L_0x247da20/d .functor XOR 1, RS_0x7f3880bf13c8, L_0x247dfc0, C4<0>, C4<0>; +L_0x247da20 .delay (40000,40000,40000) L_0x247da20/d; +L_0x247e060/d .functor NOT 1, RS_0x7f3880bf1488, C4<0>, C4<0>, C4<0>; +L_0x247e060 .delay (10000,10000,10000) L_0x247e060/d; +L_0x247e1d0/d .functor NOT 1, L_0x247e2b0, C4<0>, C4<0>, C4<0>; +L_0x247e1d0 .delay (10000,10000,10000) L_0x247e1d0/d; +L_0x247de90/d .functor AND 1, L_0x247e060, L_0x247e4e0, C4<1>, C4<1>; +L_0x247de90 .delay (20000,20000,20000) L_0x247de90/d; +L_0x247e580/d .functor AND 1, RS_0x7f3880bf1488, L_0x247e1d0, C4<1>, C4<1>; +L_0x247e580 .delay (20000,20000,20000) L_0x247e580/d; +L_0x247e680/d .functor AND 1, L_0x247de90, L_0x247bde0, C4<1>, C4<1>; +L_0x247e680 .delay (20000,20000,20000) L_0x247e680/d; +L_0x247e780/d .functor AND 1, L_0x247e580, L_0x247bde0, C4<1>, C4<1>; +L_0x247e780 .delay (20000,20000,20000) L_0x247e780/d; +L_0x247e8f0/d .functor OR 1, L_0x247e680, L_0x247e780, C4<0>, C4<0>; +L_0x247e8f0 .delay (20000,20000,20000) L_0x247e8f0/d; +v0x244d180_0 .alias "A", 3 0, v0x245d340_0; +v0x244d220_0 .alias "AddSubSLTSum", 3 0, v0x245e670_0; +v0x244d2c0_0 .alias "B", 3 0, v0x245d460_0; +RS_0x7f3880bf10c8 .resolv tri, L_0x2477c40, L_0x24796e0, L_0x247b1e0, L_0x247bfc0; +v0x244d390_0 .net8 "CarryoutWire", 3 0, RS_0x7f3880bf10c8; 4 drivers +v0x244d410_0 .alias "Command", 2 0, v0x245d560_0; +RS_0x7f3880bf10f8 .resolv tri, L_0x2477b50, L_0x24795f0, L_0x247b0f0, L_0x247cff0; +v0x244d490_0 .net8 "NewVal", 3 0, RS_0x7f3880bf10f8; 4 drivers +v0x244d530_0 .net "Res0OF1", 0 0, L_0x247e580; 1 drivers +v0x244d5d0_0 .net "Res1OF0", 0 0, L_0x247de90; 1 drivers +v0x244d6c0_0 .alias "SLTflag", 0 0, v0x245ea40_0; +v0x244d760_0 .net "SLTflag0", 0 0, L_0x247e680; 1 drivers +v0x244d800_0 .net "SLTflag1", 0 0, L_0x247e780; 1 drivers +v0x244d8a0_0 .net "SLTon", 0 0, L_0x247bde0; 1 drivers +v0x244d9b0_0 .net *"_s37", 0 0, L_0x247bd40; 1 drivers +v0x244da50_0 .net *"_s39", 0 0, L_0x247bf20; 1 drivers +v0x244db70_0 .net *"_s41", 0 0, L_0x247bb70; 1 drivers +v0x244dc10_0 .net *"_s61", 0 0, L_0x247dce0; 1 drivers +v0x244dad0_0 .net/s *"_s62", 0 0, C4<0>; 1 drivers +v0x244dd60_0 .net *"_s65", 0 0, L_0x247dfc0; 1 drivers +v0x244de80_0 .net *"_s67", 0 0, L_0x247e2b0; 1 drivers +v0x244df00_0 .net *"_s69", 0 0, L_0x247e4e0; 1 drivers +v0x244dde0_0 .alias "carryin", 3 0, v0x245df60_0; +v0x244e030_0 .alias "carryout", 0 0, v0x245ebc0_0; +v0x244df80_0 .net "nAddSubSLTSum", 0 0, L_0x247e1d0; 1 drivers +v0x244e170_0 .net "nCmd2", 0 0, L_0x247bc90; 1 drivers +v0x244e0d0_0 .net "nOF", 0 0, L_0x247e060; 1 drivers +v0x244e2c0_0 .alias "overflow", 0 0, v0x245ec40_0; +v0x244e210_0 .alias "subtract", 3 0, v0x245ecc0_0; +L_0x2477b50 .part/pv L_0x24776c0, 1, 1, 4; +L_0x2477c40 .part/pv L_0x2477a10, 1, 1, 4; +L_0x2477d30 .part/pv L_0x24773f0, 1, 1, 4; +L_0x2477e20 .part v0x245e5f0_0, 1, 1; +L_0x2477ec0 .part v0x245e7f0_0, 1, 1; +L_0x2477ff0 .part RS_0x7f3880bf10c8, 0, 1; +L_0x2478450 .part/pv L_0x2478310, 1, 1, 4; +L_0x24784f0 .part RS_0x7f3880bf10f8, 1, 1; +L_0x24795f0 .part/pv L_0x2479160, 2, 1, 4; +L_0x24796e0 .part/pv L_0x24794b0, 2, 1, 4; +L_0x2479830 .part/pv L_0x2478e90, 2, 1, 4; +L_0x24798d0 .part v0x245e5f0_0, 2, 1; +L_0x24799e0 .part v0x245e7f0_0, 2, 1; +L_0x2479b10 .part RS_0x7f3880bf10c8, 1, 1; +L_0x2479fc0 .part/pv L_0x2479ed0, 2, 1, 4; +L_0x247a060 .part RS_0x7f3880bf10f8, 2, 1; +L_0x247b0f0 .part/pv L_0x247ad00, 3, 1, 4; +L_0x247b1e0 .part/pv L_0x2479c40, 3, 1, 4; +L_0x247b370 .part/pv L_0x247aa30, 3, 1, 4; +L_0x247b410 .part v0x245e5f0_0, 3, 1; +L_0x247b2d0 .part v0x245e7f0_0, 3, 1; +L_0x247b5f0 .part RS_0x7f3880bf10c8, 2, 1; +L_0x247b9e0 .part/pv L_0x247b8a0, 3, 1, 4; +L_0x247ba80 .part RS_0x7f3880bf10f8, 3, 1; +L_0x247bd40 .part v0x245e870_0, 2, 1; +L_0x247bf20 .part v0x245e870_0, 0, 1; +L_0x247bb70 .part v0x245e870_0, 1, 1; +L_0x247cff0 .part/pv L_0x247cb40, 0, 1, 4; +L_0x247bfc0 .part/pv L_0x247ce90, 0, 1, 4; +L_0x247d220 .part/pv L_0x247c870, 0, 1, 4; +L_0x247d0e0 .part v0x245e5f0_0, 0, 1; +L_0x247d410 .part v0x245e7f0_0, 0, 1; +L_0x247d310 .part RS_0x7f3880bf14b8, 0, 1; +L_0x247d920 .part/pv L_0x247d7e0, 0, 1, 4; +L_0x247d540 .part RS_0x7f3880bf10f8, 0, 1; +L_0x247dce0 .part RS_0x7f3880bf10c8, 3, 1; +L_0x247dfc0 .part RS_0x7f3880bf10c8, 2, 1; +L_0x247e2b0 .part RS_0x7f3880bf1098, 3, 1; +L_0x247e4e0 .part RS_0x7f3880bf1098, 3, 1; +S_0x244c160 .scope module, "attempt2" "MiddleAddSubSLT" 3 235, 3 89, S_0x24474b0; + .timescale -9 -12; +L_0x247c0f0/d .functor NOT 1, L_0x247d410, C4<0>, C4<0>, C4<0>; +L_0x247c0f0 .delay (10000,10000,10000) L_0x247c0f0/d; +L_0x247c730/d .functor NOT 1, L_0x247c7d0, C4<0>, C4<0>, C4<0>; +L_0x247c730 .delay (10000,10000,10000) L_0x247c730/d; +L_0x247c870/d .functor AND 1, L_0x247c9b0, L_0x247c730, C4<1>, C4<1>; +L_0x247c870 .delay (20000,20000,20000) L_0x247c870/d; +L_0x247ca50/d .functor XOR 1, L_0x247d0e0, L_0x247c500, C4<0>, C4<0>; +L_0x247ca50 .delay (40000,40000,40000) L_0x247ca50/d; +L_0x247cb40/d .functor XOR 1, L_0x247ca50, L_0x247d310, C4<0>, C4<0>; +L_0x247cb40 .delay (40000,40000,40000) L_0x247cb40/d; +L_0x247cc30/d .functor AND 1, L_0x247d0e0, L_0x247c500, C4<1>, C4<1>; +L_0x247cc30 .delay (20000,20000,20000) L_0x247cc30/d; +L_0x247cda0/d .functor AND 1, L_0x247ca50, L_0x247d310, C4<1>, C4<1>; +L_0x247cda0 .delay (20000,20000,20000) L_0x247cda0/d; +L_0x247ce90/d .functor OR 1, L_0x247cc30, L_0x247cda0, C4<0>, C4<0>; +L_0x247ce90 .delay (20000,20000,20000) L_0x247ce90/d; +v0x244c7e0_0 .net "A", 0 0, L_0x247d0e0; 1 drivers +v0x244c8a0_0 .net "AandB", 0 0, L_0x247cc30; 1 drivers +v0x244c940_0 .net "AddSubSLTSum", 0 0, L_0x247cb40; 1 drivers +v0x244c9e0_0 .net "AxorB", 0 0, L_0x247ca50; 1 drivers +v0x244ca60_0 .net "B", 0 0, L_0x247d410; 1 drivers +v0x244cb10_0 .net "BornB", 0 0, L_0x247c500; 1 drivers +v0x244cbd0_0 .net "CINandAxorB", 0 0, L_0x247cda0; 1 drivers +v0x244cc50_0 .alias "Command", 2 0, v0x245d560_0; +v0x244ccd0_0 .net *"_s3", 0 0, L_0x247c7d0; 1 drivers +v0x244cd50_0 .net *"_s5", 0 0, L_0x247c9b0; 1 drivers +v0x244cdf0_0 .net "carryin", 0 0, L_0x247d310; 1 drivers +v0x244ce90_0 .net "carryout", 0 0, L_0x247ce90; 1 drivers +v0x244cf30_0 .net "nB", 0 0, L_0x247c0f0; 1 drivers +v0x244cfe0_0 .net "nCmd2", 0 0, L_0x247c730; 1 drivers +v0x244d0e0_0 .net "subtract", 0 0, L_0x247c870; 1 drivers +L_0x247c690 .part v0x245e870_0, 0, 1; +L_0x247c7d0 .part v0x245e870_0, 2, 1; +L_0x247c9b0 .part v0x245e870_0, 0, 1; +S_0x244c250 .scope module, "mux0" "TwoInMux" 3 105, 3 8, S_0x244c160; + .timescale -9 -12; +L_0x247c280/d .functor NOT 1, L_0x247c690, C4<0>, C4<0>, C4<0>; +L_0x247c280 .delay (10000,10000,10000) L_0x247c280/d; +L_0x247c320/d .functor AND 1, L_0x247d410, L_0x247c280, C4<1>, C4<1>; +L_0x247c320 .delay (20000,20000,20000) L_0x247c320/d; +L_0x247c410/d .functor AND 1, L_0x247c0f0, L_0x247c690, C4<1>, C4<1>; +L_0x247c410 .delay (20000,20000,20000) L_0x247c410/d; +L_0x247c500/d .functor OR 1, L_0x247c320, L_0x247c410, C4<0>, C4<0>; +L_0x247c500 .delay (20000,20000,20000) L_0x247c500/d; +v0x244c340_0 .net "S", 0 0, L_0x247c690; 1 drivers +v0x244c400_0 .alias "in0", 0 0, v0x244ca60_0; +v0x244c4a0_0 .alias "in1", 0 0, v0x244cf30_0; +v0x244c540_0 .net "nS", 0 0, L_0x247c280; 1 drivers +v0x244c5c0_0 .net "out0", 0 0, L_0x247c320; 1 drivers +v0x244c660_0 .net "out1", 0 0, L_0x247c410; 1 drivers +v0x244c740_0 .alias "outfinal", 0 0, v0x244cb10_0; +S_0x244bc00 .scope module, "setSLTres" "TwoInMux" 3 236, 3 8, S_0x24474b0; + .timescale -9 -12; +L_0x247d3b0/d .functor NOT 1, L_0x247bde0, C4<0>, C4<0>, C4<0>; +L_0x247d3b0 .delay (10000,10000,10000) L_0x247d3b0/d; +L_0x247d650/d .functor AND 1, L_0x247d540, L_0x247d3b0, C4<1>, C4<1>; +L_0x247d650 .delay (20000,20000,20000) L_0x247d650/d; +L_0x247d740/d .functor AND 1, C4<0>, L_0x247bde0, C4<1>, C4<1>; +L_0x247d740 .delay (20000,20000,20000) L_0x247d740/d; +L_0x247d7e0/d .functor OR 1, L_0x247d650, L_0x247d740, C4<0>, C4<0>; +L_0x247d7e0 .delay (20000,20000,20000) L_0x247d7e0/d; +v0x244bcf0_0 .alias "S", 0 0, v0x244d8a0_0; +v0x244bd90_0 .net "in0", 0 0, L_0x247d540; 1 drivers +v0x244be30_0 .net "in1", 0 0, C4<0>; 1 drivers +v0x244bed0_0 .net "nS", 0 0, L_0x247d3b0; 1 drivers +v0x244bf80_0 .net "out0", 0 0, L_0x247d650; 1 drivers +v0x244c020_0 .net "out1", 0 0, L_0x247d740; 1 drivers +v0x244c0c0_0 .net "outfinal", 0 0, L_0x247d7e0; 1 drivers +S_0x244a520 .scope generate, "addbits[1]" "addbits[1]" 3 244, 3 244, S_0x24474b0; + .timescale -9 -12; +P_0x2449f38 .param/l "i" 3 244, +C4<01>; +S_0x244abe0 .scope module, "attempt" "MiddleAddSubSLT" 3 246, 3 89, S_0x244a520; + .timescale -9 -12; +L_0x2476a10/d .functor NOT 1, L_0x2477ec0, C4<0>, C4<0>, C4<0>; +L_0x2476a10 .delay (10000,10000,10000) L_0x2476a10/d; +L_0x24772b0/d .functor NOT 1, L_0x2477350, C4<0>, C4<0>, C4<0>; +L_0x24772b0 .delay (10000,10000,10000) L_0x24772b0/d; +L_0x24773f0/d .functor AND 1, L_0x2477530, L_0x24772b0, C4<1>, C4<1>; +L_0x24773f0 .delay (20000,20000,20000) L_0x24773f0/d; +L_0x24775d0/d .functor XOR 1, L_0x2477e20, L_0x2477080, C4<0>, C4<0>; +L_0x24775d0 .delay (40000,40000,40000) L_0x24775d0/d; +L_0x24776c0/d .functor XOR 1, L_0x24775d0, L_0x2477ff0, C4<0>, C4<0>; +L_0x24776c0 .delay (40000,40000,40000) L_0x24776c0/d; +L_0x24777b0/d .functor AND 1, L_0x2477e20, L_0x2477080, C4<1>, C4<1>; +L_0x24777b0 .delay (20000,20000,20000) L_0x24777b0/d; +L_0x2477920/d .functor AND 1, L_0x24775d0, L_0x2477ff0, C4<1>, C4<1>; +L_0x2477920 .delay (20000,20000,20000) L_0x2477920/d; +L_0x2477a10/d .functor OR 1, L_0x24777b0, L_0x2477920, C4<0>, C4<0>; +L_0x2477a10 .delay (20000,20000,20000) L_0x2477a10/d; +v0x244b260_0 .net "A", 0 0, L_0x2477e20; 1 drivers +v0x244b320_0 .net "AandB", 0 0, L_0x24777b0; 1 drivers +v0x244b3c0_0 .net "AddSubSLTSum", 0 0, L_0x24776c0; 1 drivers +v0x244b460_0 .net "AxorB", 0 0, L_0x24775d0; 1 drivers +v0x244b4e0_0 .net "B", 0 0, L_0x2477ec0; 1 drivers +v0x244b590_0 .net "BornB", 0 0, L_0x2477080; 1 drivers +v0x244b650_0 .net "CINandAxorB", 0 0, L_0x2477920; 1 drivers +v0x244b6d0_0 .alias "Command", 2 0, v0x245d560_0; +v0x244b750_0 .net *"_s3", 0 0, L_0x2477350; 1 drivers +v0x244b7d0_0 .net *"_s5", 0 0, L_0x2477530; 1 drivers +v0x244b870_0 .net "carryin", 0 0, L_0x2477ff0; 1 drivers +v0x244b910_0 .net "carryout", 0 0, L_0x2477a10; 1 drivers +v0x244b9b0_0 .net "nB", 0 0, L_0x2476a10; 1 drivers +v0x244ba60_0 .net "nCmd2", 0 0, L_0x24772b0; 1 drivers +v0x244bb60_0 .net "subtract", 0 0, L_0x24773f0; 1 drivers +L_0x2477210 .part v0x245e870_0, 0, 1; +L_0x2477350 .part v0x245e870_0, 2, 1; +L_0x2477530 .part v0x245e870_0, 0, 1; +S_0x244acd0 .scope module, "mux0" "TwoInMux" 3 105, 3 8, S_0x244abe0; + .timescale -9 -12; +L_0x2476e00/d .functor NOT 1, L_0x2477210, C4<0>, C4<0>, C4<0>; +L_0x2476e00 .delay (10000,10000,10000) L_0x2476e00/d; +L_0x2476ea0/d .functor AND 1, L_0x2477ec0, L_0x2476e00, C4<1>, C4<1>; +L_0x2476ea0 .delay (20000,20000,20000) L_0x2476ea0/d; +L_0x2476f90/d .functor AND 1, L_0x2476a10, L_0x2477210, C4<1>, C4<1>; +L_0x2476f90 .delay (20000,20000,20000) L_0x2476f90/d; +L_0x2477080/d .functor OR 1, L_0x2476ea0, L_0x2476f90, C4<0>, C4<0>; +L_0x2477080 .delay (20000,20000,20000) L_0x2477080/d; +v0x244adc0_0 .net "S", 0 0, L_0x2477210; 1 drivers +v0x244ae80_0 .alias "in0", 0 0, v0x244b4e0_0; +v0x244af20_0 .alias "in1", 0 0, v0x244b9b0_0; +v0x244afc0_0 .net "nS", 0 0, L_0x2476e00; 1 drivers +v0x244b040_0 .net "out0", 0 0, L_0x2476ea0; 1 drivers +v0x244b0e0_0 .net "out1", 0 0, L_0x2476f90; 1 drivers +v0x244b1c0_0 .alias "outfinal", 0 0, v0x244b590_0; +S_0x244a690 .scope module, "setSLTres" "TwoInMux" 3 247, 3 8, S_0x244a520; + .timescale -9 -12; +L_0x2478090/d .functor NOT 1, L_0x247bde0, C4<0>, C4<0>, C4<0>; +L_0x2478090 .delay (10000,10000,10000) L_0x2478090/d; +L_0x2478180/d .functor AND 1, L_0x24784f0, L_0x2478090, C4<1>, C4<1>; +L_0x2478180 .delay (20000,20000,20000) L_0x2478180/d; +L_0x2478270/d .functor AND 1, C4<0>, L_0x247bde0, C4<1>, C4<1>; +L_0x2478270 .delay (20000,20000,20000) L_0x2478270/d; +L_0x2478310/d .functor OR 1, L_0x2478180, L_0x2478270, C4<0>, C4<0>; +L_0x2478310 .delay (20000,20000,20000) L_0x2478310/d; +v0x244a780_0 .alias "S", 0 0, v0x244d8a0_0; +v0x244a800_0 .net "in0", 0 0, L_0x24784f0; 1 drivers +v0x244a8a0_0 .net "in1", 0 0, C4<0>; 1 drivers +v0x244a940_0 .net "nS", 0 0, L_0x2478090; 1 drivers +v0x244a9c0_0 .net "out0", 0 0, L_0x2478180; 1 drivers +v0x244aa60_0 .net "out1", 0 0, L_0x2478270; 1 drivers +v0x244ab40_0 .net "outfinal", 0 0, L_0x2478310; 1 drivers +S_0x2448e00 .scope generate, "addbits[2]" "addbits[2]" 3 244, 3 244, S_0x24474b0; + .timescale -9 -12; +P_0x2448748 .param/l "i" 3 244, +C4<010>; +S_0x2449500 .scope module, "attempt" "MiddleAddSubSLT" 3 246, 3 89, S_0x2448e00; + .timescale -9 -12; +L_0x2478710/d .functor NOT 1, L_0x24799e0, C4<0>, C4<0>, C4<0>; +L_0x2478710 .delay (10000,10000,10000) L_0x2478710/d; +L_0x2478d50/d .functor NOT 1, L_0x2478df0, C4<0>, C4<0>, C4<0>; +L_0x2478d50 .delay (10000,10000,10000) L_0x2478d50/d; +L_0x2478e90/d .functor AND 1, L_0x2478fd0, L_0x2478d50, C4<1>, C4<1>; +L_0x2478e90 .delay (20000,20000,20000) L_0x2478e90/d; +L_0x2479070/d .functor XOR 1, L_0x24798d0, L_0x2478b20, C4<0>, C4<0>; +L_0x2479070 .delay (40000,40000,40000) L_0x2479070/d; +L_0x2479160/d .functor XOR 1, L_0x2479070, L_0x2479b10, C4<0>, C4<0>; +L_0x2479160 .delay (40000,40000,40000) L_0x2479160/d; +L_0x2479250/d .functor AND 1, L_0x24798d0, L_0x2478b20, C4<1>, C4<1>; +L_0x2479250 .delay (20000,20000,20000) L_0x2479250/d; +L_0x24793c0/d .functor AND 1, L_0x2479070, L_0x2479b10, C4<1>, C4<1>; +L_0x24793c0 .delay (20000,20000,20000) L_0x24793c0/d; +L_0x24794b0/d .functor OR 1, L_0x2479250, L_0x24793c0, C4<0>, C4<0>; +L_0x24794b0 .delay (20000,20000,20000) L_0x24794b0/d; +v0x2449b80_0 .net "A", 0 0, L_0x24798d0; 1 drivers +v0x2449c40_0 .net "AandB", 0 0, L_0x2479250; 1 drivers +v0x2449ce0_0 .net "AddSubSLTSum", 0 0, L_0x2479160; 1 drivers +v0x2449d80_0 .net "AxorB", 0 0, L_0x2479070; 1 drivers +v0x2449e00_0 .net "B", 0 0, L_0x24799e0; 1 drivers +v0x2449eb0_0 .net "BornB", 0 0, L_0x2478b20; 1 drivers +v0x2449f70_0 .net "CINandAxorB", 0 0, L_0x24793c0; 1 drivers +v0x2449ff0_0 .alias "Command", 2 0, v0x245d560_0; +v0x244a070_0 .net *"_s3", 0 0, L_0x2478df0; 1 drivers +v0x244a0f0_0 .net *"_s5", 0 0, L_0x2478fd0; 1 drivers +v0x244a190_0 .net "carryin", 0 0, L_0x2479b10; 1 drivers +v0x244a230_0 .net "carryout", 0 0, L_0x24794b0; 1 drivers +v0x244a2d0_0 .net "nB", 0 0, L_0x2478710; 1 drivers +v0x244a380_0 .net "nCmd2", 0 0, L_0x2478d50; 1 drivers +v0x244a480_0 .net "subtract", 0 0, L_0x2478e90; 1 drivers +L_0x2478cb0 .part v0x245e870_0, 0, 1; +L_0x2478df0 .part v0x245e870_0, 2, 1; +L_0x2478fd0 .part v0x245e870_0, 0, 1; +S_0x24495f0 .scope module, "mux0" "TwoInMux" 3 105, 3 8, S_0x2449500; + .timescale -9 -12; +L_0x24788a0/d .functor NOT 1, L_0x2478cb0, C4<0>, C4<0>, C4<0>; +L_0x24788a0 .delay (10000,10000,10000) L_0x24788a0/d; +L_0x2478940/d .functor AND 1, L_0x24799e0, L_0x24788a0, C4<1>, C4<1>; +L_0x2478940 .delay (20000,20000,20000) L_0x2478940/d; +L_0x2478a30/d .functor AND 1, L_0x2478710, L_0x2478cb0, C4<1>, C4<1>; +L_0x2478a30 .delay (20000,20000,20000) L_0x2478a30/d; +L_0x2478b20/d .functor OR 1, L_0x2478940, L_0x2478a30, C4<0>, C4<0>; +L_0x2478b20 .delay (20000,20000,20000) L_0x2478b20/d; +v0x24496e0_0 .net "S", 0 0, L_0x2478cb0; 1 drivers +v0x24497a0_0 .alias "in0", 0 0, v0x2449e00_0; +v0x2449840_0 .alias "in1", 0 0, v0x244a2d0_0; +v0x24498e0_0 .net "nS", 0 0, L_0x24788a0; 1 drivers +v0x2449960_0 .net "out0", 0 0, L_0x2478940; 1 drivers +v0x2449a00_0 .net "out1", 0 0, L_0x2478a30; 1 drivers +v0x2449ae0_0 .alias "outfinal", 0 0, v0x2449eb0_0; +S_0x2448f70 .scope module, "setSLTres" "TwoInMux" 3 247, 3 8, S_0x2448e00; + .timescale -9 -12; +L_0x24797d0/d .functor NOT 1, L_0x247bde0, C4<0>, C4<0>, C4<0>; +L_0x24797d0 .delay (10000,10000,10000) L_0x24797d0/d; +L_0x2479cc0/d .functor AND 1, L_0x247a060, L_0x24797d0, C4<1>, C4<1>; +L_0x2479cc0 .delay (20000,20000,20000) L_0x2479cc0/d; +L_0x2479d60/d .functor AND 1, C4<0>, L_0x247bde0, C4<1>, C4<1>; +L_0x2479d60 .delay (20000,20000,20000) L_0x2479d60/d; +L_0x2479ed0/d .functor OR 1, L_0x2479cc0, L_0x2479d60, C4<0>, C4<0>; +L_0x2479ed0 .delay (20000,20000,20000) L_0x2479ed0/d; +v0x2449060_0 .alias "S", 0 0, v0x244d8a0_0; +v0x2449110_0 .net "in0", 0 0, L_0x247a060; 1 drivers +v0x2449190_0 .net "in1", 0 0, C4<0>; 1 drivers +v0x2449230_0 .net "nS", 0 0, L_0x24797d0; 1 drivers +v0x24492e0_0 .net "out0", 0 0, L_0x2479cc0; 1 drivers +v0x2449380_0 .net "out1", 0 0, L_0x2479d60; 1 drivers +v0x2449460_0 .net "outfinal", 0 0, L_0x2479ed0; 1 drivers +S_0x2447620 .scope generate, "addbits[3]" "addbits[3]" 3 244, 3 244, S_0x24474b0; + .timescale -9 -12; +P_0x2447718 .param/l "i" 3 244, +C4<011>; +S_0x2447d10 .scope module, "attempt" "MiddleAddSubSLT" 3 246, 3 89, S_0x2447620; + .timescale -9 -12; +L_0x247a2b0/d .functor NOT 1, L_0x247b2d0, C4<0>, C4<0>, C4<0>; +L_0x247a2b0 .delay (10000,10000,10000) L_0x247a2b0/d; +L_0x247a8f0/d .functor NOT 1, L_0x247a990, C4<0>, C4<0>, C4<0>; +L_0x247a8f0 .delay (10000,10000,10000) L_0x247a8f0/d; +L_0x247aa30/d .functor AND 1, L_0x247ab70, L_0x247a8f0, C4<1>, C4<1>; +L_0x247aa30 .delay (20000,20000,20000) L_0x247aa30/d; +L_0x247ac10/d .functor XOR 1, L_0x247b410, L_0x247a6c0, C4<0>, C4<0>; +L_0x247ac10 .delay (40000,40000,40000) L_0x247ac10/d; +L_0x247ad00/d .functor XOR 1, L_0x247ac10, L_0x247b5f0, C4<0>, C4<0>; +L_0x247ad00 .delay (40000,40000,40000) L_0x247ad00/d; +L_0x247adf0/d .functor AND 1, L_0x247b410, L_0x247a6c0, C4<1>, C4<1>; +L_0x247adf0 .delay (20000,20000,20000) L_0x247adf0/d; +L_0x247af60/d .functor AND 1, L_0x247ac10, L_0x247b5f0, C4<1>, C4<1>; +L_0x247af60 .delay (20000,20000,20000) L_0x247af60/d; +L_0x2479c40/d .functor OR 1, L_0x247adf0, L_0x247af60, C4<0>, C4<0>; +L_0x2479c40 .delay (20000,20000,20000) L_0x2479c40/d; +v0x2448390_0 .net "A", 0 0, L_0x247b410; 1 drivers +v0x2448450_0 .net "AandB", 0 0, L_0x247adf0; 1 drivers +v0x24484f0_0 .net "AddSubSLTSum", 0 0, L_0x247ad00; 1 drivers +v0x2448590_0 .net "AxorB", 0 0, L_0x247ac10; 1 drivers +v0x2448610_0 .net "B", 0 0, L_0x247b2d0; 1 drivers +v0x24486c0_0 .net "BornB", 0 0, L_0x247a6c0; 1 drivers +v0x2448780_0 .net "CINandAxorB", 0 0, L_0x247af60; 1 drivers +v0x2448800_0 .alias "Command", 2 0, v0x245d560_0; +v0x2448880_0 .net *"_s3", 0 0, L_0x247a990; 1 drivers +v0x2448900_0 .net *"_s5", 0 0, L_0x247ab70; 1 drivers +v0x2448a00_0 .net "carryin", 0 0, L_0x247b5f0; 1 drivers +v0x2448aa0_0 .net "carryout", 0 0, L_0x2479c40; 1 drivers +v0x2448bb0_0 .net "nB", 0 0, L_0x247a2b0; 1 drivers +v0x2448c60_0 .net "nCmd2", 0 0, L_0x247a8f0; 1 drivers +v0x2448d60_0 .net "subtract", 0 0, L_0x247aa30; 1 drivers +L_0x247a850 .part v0x245e870_0, 0, 1; +L_0x247a990 .part v0x245e870_0, 2, 1; +L_0x247ab70 .part v0x245e870_0, 0, 1; +S_0x2447e00 .scope module, "mux0" "TwoInMux" 3 105, 3 8, S_0x2447d10; + .timescale -9 -12; +L_0x247a440/d .functor NOT 1, L_0x247a850, C4<0>, C4<0>, C4<0>; +L_0x247a440 .delay (10000,10000,10000) L_0x247a440/d; +L_0x247a4e0/d .functor AND 1, L_0x247b2d0, L_0x247a440, C4<1>, C4<1>; +L_0x247a4e0 .delay (20000,20000,20000) L_0x247a4e0/d; +L_0x247a5d0/d .functor AND 1, L_0x247a2b0, L_0x247a850, C4<1>, C4<1>; +L_0x247a5d0 .delay (20000,20000,20000) L_0x247a5d0/d; +L_0x247a6c0/d .functor OR 1, L_0x247a4e0, L_0x247a5d0, C4<0>, C4<0>; +L_0x247a6c0 .delay (20000,20000,20000) L_0x247a6c0/d; +v0x2447ef0_0 .net "S", 0 0, L_0x247a850; 1 drivers +v0x2447fb0_0 .alias "in0", 0 0, v0x2448610_0; +v0x2448050_0 .alias "in1", 0 0, v0x2448bb0_0; +v0x24480f0_0 .net "nS", 0 0, L_0x247a440; 1 drivers +v0x2448170_0 .net "out0", 0 0, L_0x247a4e0; 1 drivers +v0x2448210_0 .net "out1", 0 0, L_0x247a5d0; 1 drivers +v0x24482f0_0 .alias "outfinal", 0 0, v0x24486c0_0; +S_0x2447790 .scope module, "setSLTres" "TwoInMux" 3 247, 3 8, S_0x2447620; + .timescale -9 -12; +L_0x247b4b0/d .functor NOT 1, L_0x247bde0, C4<0>, C4<0>, C4<0>; +L_0x247b4b0 .delay (10000,10000,10000) L_0x247b4b0/d; +L_0x247b750/d .functor AND 1, L_0x247ba80, L_0x247b4b0, C4<1>, C4<1>; +L_0x247b750 .delay (20000,20000,20000) L_0x247b750/d; +L_0x247b800/d .functor AND 1, C4<0>, L_0x247bde0, C4<1>, C4<1>; +L_0x247b800 .delay (20000,20000,20000) L_0x247b800/d; +L_0x247b8a0/d .functor OR 1, L_0x247b750, L_0x247b800, C4<0>, C4<0>; +L_0x247b8a0 .delay (20000,20000,20000) L_0x247b8a0/d; +v0x2447880_0 .alias "S", 0 0, v0x244d8a0_0; +v0x2447900_0 .net "in0", 0 0, L_0x247ba80; 1 drivers +v0x24479a0_0 .net "in1", 0 0, C4<0>; 1 drivers +v0x2447a40_0 .net "nS", 0 0, L_0x247b4b0; 1 drivers +v0x2447af0_0 .net "out0", 0 0, L_0x247b750; 1 drivers +v0x2447b90_0 .net "out1", 0 0, L_0x247b800; 1 drivers +v0x2447c70_0 .net "outfinal", 0 0, L_0x247b8a0; 1 drivers +S_0x2444270 .scope module, "trial1" "AndNand32" 3 312, 3 154, S_0x23d85b0; + .timescale -9 -12; +P_0x2443cf8 .param/l "size" 3 161, +C4<0100>; +v0x2444160_0 .alias "A", 3 0, v0x245d340_0; +v0x24472d0_0 .alias "AndNandOut", 3 0, v0x245e770_0; +v0x2447350_0 .alias "B", 3 0, v0x245d460_0; +v0x2447400_0 .alias "Command", 2 0, v0x245d560_0; +L_0x247f1f0 .part/pv L_0x247ef80, 1, 1, 4; +L_0x247f2b0 .part v0x245e5f0_0, 1, 1; +L_0x247f350 .part v0x245e7f0_0, 1, 1; +L_0x247fc60 .part/pv L_0x247f9f0, 2, 1, 4; +L_0x247fd00 .part v0x245e5f0_0, 2, 1; +L_0x247fda0 .part v0x245e7f0_0, 2, 1; +L_0x24806d0 .part/pv L_0x2480460, 3, 1, 4; +L_0x2470620 .part v0x245e5f0_0, 3, 1; +L_0x2480980 .part v0x245e7f0_0, 3, 1; +L_0x2481230 .part/pv L_0x2480fc0, 0, 1, 4; +L_0x2481330 .part v0x245e5f0_0, 0, 1; +L_0x24813d0 .part v0x245e7f0_0, 0, 1; +S_0x2446790 .scope module, "attempt2" "AndNand" 3 165, 3 48, S_0x2444270; + .timescale -9 -12; +L_0x2480a70/d .functor NAND 1, L_0x2481330, L_0x24813d0, C4<1>, C4<1>; +L_0x2480a70 .delay (10000,10000,10000) L_0x2480a70/d; +L_0x2480b70/d .functor NOT 1, L_0x2480a70, C4<0>, C4<0>, C4<0>; +L_0x2480b70 .delay (10000,10000,10000) L_0x2480b70/d; +v0x2446db0_0 .net "A", 0 0, L_0x2481330; 1 drivers +v0x2446e70_0 .net "AandB", 0 0, L_0x2480b70; 1 drivers +v0x2446ef0_0 .net "AnandB", 0 0, L_0x2480a70; 1 drivers +v0x2446fa0_0 .net "AndNandOut", 0 0, L_0x2480fc0; 1 drivers +v0x2447080_0 .net "B", 0 0, L_0x24813d0; 1 drivers +v0x2447100_0 .alias "Command", 2 0, v0x245d560_0; +L_0x2481190 .part v0x245e870_0, 0, 1; +S_0x2446880 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0x2446790; + .timescale -9 -12; +L_0x2480ca0/d .functor NOT 1, L_0x2481190, C4<0>, C4<0>, C4<0>; +L_0x2480ca0 .delay (10000,10000,10000) L_0x2480ca0/d; +L_0x2480d60/d .functor AND 1, L_0x2480b70, L_0x2480ca0, C4<1>, C4<1>; +L_0x2480d60 .delay (20000,20000,20000) L_0x2480d60/d; +L_0x2480e70/d .functor AND 1, L_0x2480a70, L_0x2481190, C4<1>, C4<1>; +L_0x2480e70 .delay (20000,20000,20000) L_0x2480e70/d; +L_0x2480fc0/d .functor OR 1, L_0x2480d60, L_0x2480e70, C4<0>, C4<0>; +L_0x2480fc0 .delay (20000,20000,20000) L_0x2480fc0/d; +v0x2446970_0 .net "S", 0 0, L_0x2481190; 1 drivers +v0x24469f0_0 .alias "in0", 0 0, v0x2446e70_0; +v0x2446a70_0 .alias "in1", 0 0, v0x2446ef0_0; +v0x2446b10_0 .net "nS", 0 0, L_0x2480ca0; 1 drivers +v0x2446b90_0 .net "out0", 0 0, L_0x2480d60; 1 drivers +v0x2446c30_0 .net "out1", 0 0, L_0x2480e70; 1 drivers +v0x2446d10_0 .alias "outfinal", 0 0, v0x2446fa0_0; +S_0x2445bd0 .scope generate, "andbits[1]" "andbits[1]" 3 169, 3 169, S_0x2444270; + .timescale -9 -12; +P_0x2445cc8 .param/l "i" 3 169, +C4<01>; +S_0x2445d40 .scope module, "attempt" "AndNand" 3 171, 3 48, S_0x2445bd0; + .timescale -9 -12; +L_0x247ea20/d .functor NAND 1, L_0x247f2b0, L_0x247f350, C4<1>, C4<1>; +L_0x247ea20 .delay (10000,10000,10000) L_0x247ea20/d; +L_0x247eb30/d .functor NOT 1, L_0x247ea20, C4<0>, C4<0>, C4<0>; +L_0x247eb30 .delay (10000,10000,10000) L_0x247eb30/d; +v0x2446380_0 .net "A", 0 0, L_0x247f2b0; 1 drivers +v0x2446440_0 .net "AandB", 0 0, L_0x247eb30; 1 drivers +v0x24464c0_0 .net "AnandB", 0 0, L_0x247ea20; 1 drivers +v0x2446570_0 .net "AndNandOut", 0 0, L_0x247ef80; 1 drivers +v0x2446650_0 .net "B", 0 0, L_0x247f350; 1 drivers +v0x24466d0_0 .alias "Command", 2 0, v0x245d560_0; +L_0x247f150 .part v0x245e870_0, 0, 1; +S_0x2445e30 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0x2445d40; + .timescale -9 -12; +L_0x247ec60/d .functor NOT 1, L_0x247f150, C4<0>, C4<0>, C4<0>; +L_0x247ec60 .delay (10000,10000,10000) L_0x247ec60/d; +L_0x247ed20/d .functor AND 1, L_0x247eb30, L_0x247ec60, C4<1>, C4<1>; +L_0x247ed20 .delay (20000,20000,20000) L_0x247ed20/d; +L_0x247ee30/d .functor AND 1, L_0x247ea20, L_0x247f150, C4<1>, C4<1>; +L_0x247ee30 .delay (20000,20000,20000) L_0x247ee30/d; +L_0x247ef80/d .functor OR 1, L_0x247ed20, L_0x247ee30, C4<0>, C4<0>; +L_0x247ef80 .delay (20000,20000,20000) L_0x247ef80/d; +v0x2445f20_0 .net "S", 0 0, L_0x247f150; 1 drivers +v0x2445fa0_0 .alias "in0", 0 0, v0x2446440_0; +v0x2446040_0 .alias "in1", 0 0, v0x24464c0_0; +v0x24460e0_0 .net "nS", 0 0, L_0x247ec60; 1 drivers +v0x2446160_0 .net "out0", 0 0, L_0x247ed20; 1 drivers +v0x2446200_0 .net "out1", 0 0, L_0x247ee30; 1 drivers +v0x24462e0_0 .alias "outfinal", 0 0, v0x2446570_0; +S_0x2445010 .scope generate, "andbits[2]" "andbits[2]" 3 169, 3 169, S_0x2444270; + .timescale -9 -12; +P_0x2445108 .param/l "i" 3 169, +C4<010>; +S_0x2445180 .scope module, "attempt" "AndNand" 3 171, 3 48, S_0x2445010; + .timescale -9 -12; +L_0x247f440/d .functor NAND 1, L_0x247fd00, L_0x247fda0, C4<1>, C4<1>; +L_0x247f440 .delay (10000,10000,10000) L_0x247f440/d; +L_0x247f5a0/d .functor NOT 1, L_0x247f440, C4<0>, C4<0>, C4<0>; +L_0x247f5a0 .delay (10000,10000,10000) L_0x247f5a0/d; +v0x24457c0_0 .net "A", 0 0, L_0x247fd00; 1 drivers +v0x2445880_0 .net "AandB", 0 0, L_0x247f5a0; 1 drivers +v0x2445900_0 .net "AnandB", 0 0, L_0x247f440; 1 drivers +v0x24459b0_0 .net "AndNandOut", 0 0, L_0x247f9f0; 1 drivers +v0x2445a90_0 .net "B", 0 0, L_0x247fda0; 1 drivers +v0x2445b10_0 .alias "Command", 2 0, v0x245d560_0; +L_0x247fbc0 .part v0x245e870_0, 0, 1; +S_0x2445270 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0x2445180; + .timescale -9 -12; +L_0x247f6d0/d .functor NOT 1, L_0x247fbc0, C4<0>, C4<0>, C4<0>; +L_0x247f6d0 .delay (10000,10000,10000) L_0x247f6d0/d; +L_0x247f790/d .functor AND 1, L_0x247f5a0, L_0x247f6d0, C4<1>, C4<1>; +L_0x247f790 .delay (20000,20000,20000) L_0x247f790/d; +L_0x247f8a0/d .functor AND 1, L_0x247f440, L_0x247fbc0, C4<1>, C4<1>; +L_0x247f8a0 .delay (20000,20000,20000) L_0x247f8a0/d; +L_0x247f9f0/d .functor OR 1, L_0x247f790, L_0x247f8a0, C4<0>, C4<0>; +L_0x247f9f0 .delay (20000,20000,20000) L_0x247f9f0/d; +v0x2445360_0 .net "S", 0 0, L_0x247fbc0; 1 drivers +v0x24453e0_0 .alias "in0", 0 0, v0x2445880_0; +v0x2445480_0 .alias "in1", 0 0, v0x2445900_0; +v0x2445520_0 .net "nS", 0 0, L_0x247f6d0; 1 drivers +v0x24455a0_0 .net "out0", 0 0, L_0x247f790; 1 drivers +v0x2445640_0 .net "out1", 0 0, L_0x247f8a0; 1 drivers +v0x2445720_0 .alias "outfinal", 0 0, v0x24459b0_0; +S_0x24443e0 .scope generate, "andbits[3]" "andbits[3]" 3 169, 3 169, S_0x2444270; + .timescale -9 -12; +P_0x24444d8 .param/l "i" 3 169, +C4<011>; +S_0x2444570 .scope module, "attempt" "AndNand" 3 171, 3 48, S_0x24443e0; + .timescale -9 -12; +L_0x247fed0/d .functor NAND 1, L_0x2470620, L_0x2480980, C4<1>, C4<1>; +L_0x247fed0 .delay (10000,10000,10000) L_0x247fed0/d; +L_0x2480010/d .functor NOT 1, L_0x247fed0, C4<0>, C4<0>, C4<0>; +L_0x2480010 .delay (10000,10000,10000) L_0x2480010/d; +v0x2444c00_0 .net "A", 0 0, L_0x2470620; 1 drivers +v0x2444cc0_0 .net "AandB", 0 0, L_0x2480010; 1 drivers +v0x2444d40_0 .net "AnandB", 0 0, L_0x247fed0; 1 drivers +v0x2444df0_0 .net "AndNandOut", 0 0, L_0x2480460; 1 drivers +v0x2444ed0_0 .net "B", 0 0, L_0x2480980; 1 drivers +v0x2444f50_0 .alias "Command", 2 0, v0x245d560_0; +L_0x2480630 .part v0x245e870_0, 0, 1; +S_0x2444660 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0x2444570; + .timescale -9 -12; +L_0x2480140/d .functor NOT 1, L_0x2480630, C4<0>, C4<0>, C4<0>; +L_0x2480140 .delay (10000,10000,10000) L_0x2480140/d; +L_0x2480200/d .functor AND 1, L_0x2480010, L_0x2480140, C4<1>, C4<1>; +L_0x2480200 .delay (20000,20000,20000) L_0x2480200/d; +L_0x2480310/d .functor AND 1, L_0x247fed0, L_0x2480630, C4<1>, C4<1>; +L_0x2480310 .delay (20000,20000,20000) L_0x2480310/d; +L_0x2480460/d .functor OR 1, L_0x2480200, L_0x2480310, C4<0>, C4<0>; +L_0x2480460 .delay (20000,20000,20000) L_0x2480460/d; +v0x2444750_0 .net "S", 0 0, L_0x2480630; 1 drivers +v0x24447f0_0 .alias "in0", 0 0, v0x2444cc0_0; +v0x2444890_0 .alias "in1", 0 0, v0x2444d40_0; +v0x2444930_0 .net "nS", 0 0, L_0x2480140; 1 drivers +v0x24449e0_0 .net "out0", 0 0, L_0x2480200; 1 drivers +v0x2444a80_0 .net "out1", 0 0, L_0x2480310; 1 drivers +v0x2444b60_0 .alias "outfinal", 0 0, v0x2444df0_0; +S_0x243f050 .scope module, "trial2" "OrNorXor32" 3 313, 3 177, S_0x23d85b0; + .timescale -9 -12; +P_0x243e1a8 .param/l "size" 3 184, +C4<0100>; +v0x2443fe0_0 .alias "A", 3 0, v0x245d340_0; +v0x2444060_0 .alias "B", 3 0, v0x245d460_0; +v0x24440e0_0 .alias "Command", 2 0, v0x245d560_0; +v0x24441f0_0 .alias "OrNorXorOut", 3 0, v0x245e970_0; +L_0x24825f0 .part/pv L_0x2482380, 1, 1, 4; +L_0x2482690 .part v0x245e5f0_0, 1, 1; +L_0x2482730 .part v0x245e7f0_0, 1, 1; +L_0x24838f0 .part/pv L_0x2483680, 2, 1, 4; +L_0x2483990 .part v0x245e5f0_0, 2, 1; +L_0x2483a30 .part v0x245e7f0_0, 2, 1; +L_0x2484bf0 .part/pv L_0x2484980, 3, 1, 4; +L_0x2484c90 .part v0x245e5f0_0, 3, 1; +L_0x2484d30 .part v0x245e7f0_0, 3, 1; +L_0x2485ee0 .part/pv L_0x2485c70, 0, 1, 4; +L_0x2485fe0 .part v0x245e5f0_0, 0, 1; +L_0x2486080 .part v0x245e7f0_0, 0, 1; +S_0x2442dd0 .scope module, "attempt2" "OrNorXor" 3 192, 3 64, S_0x243f050; + .timescale -9 -12; +L_0x2484dd0/d .functor NOR 1, L_0x2485fe0, L_0x2486080, C4<0>, C4<0>; +L_0x2484dd0 .delay (10000,10000,10000) L_0x2484dd0/d; +L_0x2484ed0/d .functor NOT 1, L_0x2484dd0, C4<0>, C4<0>, C4<0>; +L_0x2484ed0 .delay (10000,10000,10000) L_0x2484ed0/d; +L_0x2485000/d .functor NAND 1, L_0x2485fe0, L_0x2486080, C4<1>, C4<1>; +L_0x2485000 .delay (10000,10000,10000) L_0x2485000/d; +L_0x2485160/d .functor NAND 1, L_0x2485000, L_0x2484ed0, C4<1>, C4<1>; +L_0x2485160 .delay (10000,10000,10000) L_0x2485160/d; +L_0x2485270/d .functor NOT 1, L_0x2485160, C4<0>, C4<0>, C4<0>; +L_0x2485270 .delay (10000,10000,10000) L_0x2485270/d; +v0x2443920_0 .net "A", 0 0, L_0x2485fe0; 1 drivers +v0x24439c0_0 .net "AnandB", 0 0, L_0x2485000; 1 drivers +v0x2443a60_0 .net "AnorB", 0 0, L_0x2484dd0; 1 drivers +v0x2443ae0_0 .net "AorB", 0 0, L_0x2484ed0; 1 drivers +v0x2443bc0_0 .net "AxorB", 0 0, L_0x2485270; 1 drivers +v0x2443c70_0 .net "B", 0 0, L_0x2486080; 1 drivers +v0x2443d30_0 .alias "Command", 2 0, v0x245d560_0; +v0x2443db0_0 .net "OrNorXorOut", 0 0, L_0x2485c70; 1 drivers +v0x2443e30_0 .net "XorNor", 0 0, L_0x24856f0; 1 drivers +v0x2443f00_0 .net "nXor", 0 0, L_0x2485160; 1 drivers +L_0x2485870 .part v0x245e870_0, 2, 1; +L_0x2485e40 .part v0x245e870_0, 0, 1; +S_0x24433b0 .scope module, "mux0" "TwoInMux" 3 83, 3 8, S_0x2442dd0; + .timescale -9 -12; +L_0x24853d0/d .functor NOT 1, L_0x2485870, C4<0>, C4<0>, C4<0>; +L_0x24853d0 .delay (10000,10000,10000) L_0x24853d0/d; +L_0x2485490/d .functor AND 1, L_0x2485270, L_0x24853d0, C4<1>, C4<1>; +L_0x2485490 .delay (20000,20000,20000) L_0x2485490/d; +L_0x24855a0/d .functor AND 1, L_0x2484dd0, L_0x2485870, C4<1>, C4<1>; +L_0x24855a0 .delay (20000,20000,20000) L_0x24855a0/d; +L_0x24856f0/d .functor OR 1, L_0x2485490, L_0x24855a0, C4<0>, C4<0>; +L_0x24856f0 .delay (20000,20000,20000) L_0x24856f0/d; +v0x24434a0_0 .net "S", 0 0, L_0x2485870; 1 drivers +v0x2443560_0 .alias "in0", 0 0, v0x2443bc0_0; +v0x2443600_0 .alias "in1", 0 0, v0x2443a60_0; +v0x24436a0_0 .net "nS", 0 0, L_0x24853d0; 1 drivers +v0x2443720_0 .net "out0", 0 0, L_0x2485490; 1 drivers +v0x24437c0_0 .net "out1", 0 0, L_0x24855a0; 1 drivers +v0x24438a0_0 .alias "outfinal", 0 0, v0x2443e30_0; +S_0x2442ec0 .scope module, "mux1" "TwoInMux" 3 84, 3 8, S_0x2442dd0; + .timescale -9 -12; +L_0x2485910/d .functor NOT 1, L_0x2485e40, C4<0>, C4<0>, C4<0>; +L_0x2485910 .delay (10000,10000,10000) L_0x2485910/d; +L_0x24859d0/d .functor AND 1, L_0x24856f0, L_0x2485910, C4<1>, C4<1>; +L_0x24859d0 .delay (20000,20000,20000) L_0x24859d0/d; +L_0x2485b20/d .functor AND 1, L_0x2484ed0, L_0x2485e40, C4<1>, C4<1>; +L_0x2485b20 .delay (20000,20000,20000) L_0x2485b20/d; +L_0x2485c70/d .functor OR 1, L_0x24859d0, L_0x2485b20, C4<0>, C4<0>; +L_0x2485c70 .delay (20000,20000,20000) L_0x2485c70/d; +v0x2442fb0_0 .net "S", 0 0, L_0x2485e40; 1 drivers +v0x2443030_0 .alias "in0", 0 0, v0x2443e30_0; +v0x24430b0_0 .alias "in1", 0 0, v0x2443ae0_0; +v0x2443150_0 .net "nS", 0 0, L_0x2485910; 1 drivers +v0x24431d0_0 .net "out0", 0 0, L_0x24859d0; 1 drivers +v0x2443270_0 .net "out1", 0 0, L_0x2485b20; 1 drivers +v0x2443310_0 .alias "outfinal", 0 0, v0x2443db0_0; +S_0x24419d0 .scope generate, "orbits[1]" "orbits[1]" 3 196, 3 196, S_0x243f050; + .timescale -9 -12; +P_0x24416b8 .param/l "i" 3 196, +C4<01>; +S_0x2441b00 .scope module, "attempt" "OrNorXor" 3 198, 3 64, S_0x24419d0; + .timescale -9 -12; +L_0x24812d0/d .functor NOR 1, L_0x2482690, L_0x2482730, C4<0>, C4<0>; +L_0x24812d0 .delay (10000,10000,10000) L_0x24812d0/d; +L_0x24815e0/d .functor NOT 1, L_0x24812d0, C4<0>, C4<0>, C4<0>; +L_0x24815e0 .delay (10000,10000,10000) L_0x24815e0/d; +L_0x2481710/d .functor NAND 1, L_0x2482690, L_0x2482730, C4<1>, C4<1>; +L_0x2481710 .delay (10000,10000,10000) L_0x2481710/d; +L_0x2481870/d .functor NAND 1, L_0x2481710, L_0x24815e0, C4<1>, C4<1>; +L_0x2481870 .delay (10000,10000,10000) L_0x2481870/d; +L_0x2481980/d .functor NOT 1, L_0x2481870, C4<0>, C4<0>, C4<0>; +L_0x2481980 .delay (10000,10000,10000) L_0x2481980/d; +v0x2442690_0 .net "A", 0 0, L_0x2482690; 1 drivers +v0x2442730_0 .net "AnandB", 0 0, L_0x2481710; 1 drivers +v0x24427d0_0 .net "AnorB", 0 0, L_0x24812d0; 1 drivers +v0x2442880_0 .net "AorB", 0 0, L_0x24815e0; 1 drivers +v0x2442960_0 .net "AxorB", 0 0, L_0x2481980; 1 drivers +v0x2442a10_0 .net "B", 0 0, L_0x2482730; 1 drivers +v0x2442ad0_0 .alias "Command", 2 0, v0x245d560_0; +v0x2442b50_0 .net "OrNorXorOut", 0 0, L_0x2482380; 1 drivers +v0x2442c20_0 .net "XorNor", 0 0, L_0x2481e00; 1 drivers +v0x2442cf0_0 .net "nXor", 0 0, L_0x2481870; 1 drivers +L_0x2481f80 .part v0x245e870_0, 2, 1; +L_0x2482550 .part v0x245e870_0, 0, 1; +S_0x2442120 .scope module, "mux0" "TwoInMux" 3 83, 3 8, S_0x2441b00; + .timescale -9 -12; +L_0x2481ae0/d .functor NOT 1, L_0x2481f80, C4<0>, C4<0>, C4<0>; +L_0x2481ae0 .delay (10000,10000,10000) L_0x2481ae0/d; +L_0x2481ba0/d .functor AND 1, L_0x2481980, L_0x2481ae0, C4<1>, C4<1>; +L_0x2481ba0 .delay (20000,20000,20000) L_0x2481ba0/d; +L_0x2481cb0/d .functor AND 1, L_0x24812d0, L_0x2481f80, C4<1>, C4<1>; +L_0x2481cb0 .delay (20000,20000,20000) L_0x2481cb0/d; +L_0x2481e00/d .functor OR 1, L_0x2481ba0, L_0x2481cb0, C4<0>, C4<0>; +L_0x2481e00 .delay (20000,20000,20000) L_0x2481e00/d; +v0x2442210_0 .net "S", 0 0, L_0x2481f80; 1 drivers +v0x24422d0_0 .alias "in0", 0 0, v0x2442960_0; +v0x2442370_0 .alias "in1", 0 0, v0x24427d0_0; +v0x2442410_0 .net "nS", 0 0, L_0x2481ae0; 1 drivers +v0x2442490_0 .net "out0", 0 0, L_0x2481ba0; 1 drivers +v0x2442530_0 .net "out1", 0 0, L_0x2481cb0; 1 drivers +v0x2442610_0 .alias "outfinal", 0 0, v0x2442c20_0; +S_0x2441bf0 .scope module, "mux1" "TwoInMux" 3 84, 3 8, S_0x2441b00; + .timescale -9 -12; +L_0x2482020/d .functor NOT 1, L_0x2482550, C4<0>, C4<0>, C4<0>; +L_0x2482020 .delay (10000,10000,10000) L_0x2482020/d; +L_0x24820e0/d .functor AND 1, L_0x2481e00, L_0x2482020, C4<1>, C4<1>; +L_0x24820e0 .delay (20000,20000,20000) L_0x24820e0/d; +L_0x2482230/d .functor AND 1, L_0x24815e0, L_0x2482550, C4<1>, C4<1>; +L_0x2482230 .delay (20000,20000,20000) L_0x2482230/d; +L_0x2482380/d .functor OR 1, L_0x24820e0, L_0x2482230, C4<0>, C4<0>; +L_0x2482380 .delay (20000,20000,20000) L_0x2482380/d; +v0x2441ce0_0 .net "S", 0 0, L_0x2482550; 1 drivers +v0x2441d60_0 .alias "in0", 0 0, v0x2442c20_0; +v0x2441de0_0 .alias "in1", 0 0, v0x2442880_0; +v0x2441e80_0 .net "nS", 0 0, L_0x2482020; 1 drivers +v0x2441f00_0 .net "out0", 0 0, L_0x24820e0; 1 drivers +v0x2441fa0_0 .net "out1", 0 0, L_0x2482230; 1 drivers +v0x2442080_0 .alias "outfinal", 0 0, v0x2442b50_0; +S_0x24405b0 .scope generate, "orbits[2]" "orbits[2]" 3 196, 3 196, S_0x243f050; + .timescale -9 -12; +P_0x2440328 .param/l "i" 3 196, +C4<010>; +S_0x24406e0 .scope module, "attempt" "OrNorXor" 3 198, 3 64, S_0x24405b0; + .timescale -9 -12; +L_0x24827d0/d .functor NOR 1, L_0x2483990, L_0x2483a30, C4<0>, C4<0>; +L_0x24827d0 .delay (10000,10000,10000) L_0x24827d0/d; +L_0x24828e0/d .functor NOT 1, L_0x24827d0, C4<0>, C4<0>, C4<0>; +L_0x24828e0 .delay (10000,10000,10000) L_0x24828e0/d; +L_0x2482a10/d .functor NAND 1, L_0x2483990, L_0x2483a30, C4<1>, C4<1>; +L_0x2482a10 .delay (10000,10000,10000) L_0x2482a10/d; +L_0x2482b70/d .functor NAND 1, L_0x2482a10, L_0x24828e0, C4<1>, C4<1>; +L_0x2482b70 .delay (10000,10000,10000) L_0x2482b70/d; +L_0x2482c80/d .functor NOT 1, L_0x2482b70, C4<0>, C4<0>, C4<0>; +L_0x2482c80 .delay (10000,10000,10000) L_0x2482c80/d; +v0x24412b0_0 .net "A", 0 0, L_0x2483990; 1 drivers +v0x2441350_0 .net "AnandB", 0 0, L_0x2482a10; 1 drivers +v0x24413f0_0 .net "AnorB", 0 0, L_0x24827d0; 1 drivers +v0x24414a0_0 .net "AorB", 0 0, L_0x24828e0; 1 drivers +v0x2441580_0 .net "AxorB", 0 0, L_0x2482c80; 1 drivers +v0x2441630_0 .net "B", 0 0, L_0x2483a30; 1 drivers +v0x24416f0_0 .alias "Command", 2 0, v0x245d560_0; +v0x2441770_0 .net "OrNorXorOut", 0 0, L_0x2483680; 1 drivers +v0x2441820_0 .net "XorNor", 0 0, L_0x2483100; 1 drivers +v0x24418f0_0 .net "nXor", 0 0, L_0x2482b70; 1 drivers +L_0x2483280 .part v0x245e870_0, 2, 1; +L_0x2483850 .part v0x245e870_0, 0, 1; +S_0x2440d40 .scope module, "mux0" "TwoInMux" 3 83, 3 8, S_0x24406e0; + .timescale -9 -12; +L_0x2482de0/d .functor NOT 1, L_0x2483280, C4<0>, C4<0>, C4<0>; +L_0x2482de0 .delay (10000,10000,10000) L_0x2482de0/d; +L_0x2482ea0/d .functor AND 1, L_0x2482c80, L_0x2482de0, C4<1>, C4<1>; +L_0x2482ea0 .delay (20000,20000,20000) L_0x2482ea0/d; +L_0x2482fb0/d .functor AND 1, L_0x24827d0, L_0x2483280, C4<1>, C4<1>; +L_0x2482fb0 .delay (20000,20000,20000) L_0x2482fb0/d; +L_0x2483100/d .functor OR 1, L_0x2482ea0, L_0x2482fb0, C4<0>, C4<0>; +L_0x2483100 .delay (20000,20000,20000) L_0x2483100/d; +v0x2440e30_0 .net "S", 0 0, L_0x2483280; 1 drivers +v0x2440ef0_0 .alias "in0", 0 0, v0x2441580_0; +v0x2440f90_0 .alias "in1", 0 0, v0x24413f0_0; +v0x2441030_0 .net "nS", 0 0, L_0x2482de0; 1 drivers +v0x24410b0_0 .net "out0", 0 0, L_0x2482ea0; 1 drivers +v0x2441150_0 .net "out1", 0 0, L_0x2482fb0; 1 drivers +v0x2441230_0 .alias "outfinal", 0 0, v0x2441820_0; +S_0x24407d0 .scope module, "mux1" "TwoInMux" 3 84, 3 8, S_0x24406e0; + .timescale -9 -12; +L_0x2483320/d .functor NOT 1, L_0x2483850, C4<0>, C4<0>, C4<0>; +L_0x2483320 .delay (10000,10000,10000) L_0x2483320/d; +L_0x24833e0/d .functor AND 1, L_0x2483100, L_0x2483320, C4<1>, C4<1>; +L_0x24833e0 .delay (20000,20000,20000) L_0x24833e0/d; +L_0x2483530/d .functor AND 1, L_0x24828e0, L_0x2483850, C4<1>, C4<1>; +L_0x2483530 .delay (20000,20000,20000) L_0x2483530/d; +L_0x2483680/d .functor OR 1, L_0x24833e0, L_0x2483530, C4<0>, C4<0>; +L_0x2483680 .delay (20000,20000,20000) L_0x2483680/d; +v0x24408c0_0 .net "S", 0 0, L_0x2483850; 1 drivers +v0x2440960_0 .alias "in0", 0 0, v0x2441820_0; +v0x2440a00_0 .alias "in1", 0 0, v0x24414a0_0; +v0x2440aa0_0 .net "nS", 0 0, L_0x2483320; 1 drivers +v0x2440b20_0 .net "out0", 0 0, L_0x24833e0; 1 drivers +v0x2440bc0_0 .net "out1", 0 0, L_0x2483530; 1 drivers +v0x2440ca0_0 .alias "outfinal", 0 0, v0x2441770_0; +S_0x243f1c0 .scope generate, "orbits[3]" "orbits[3]" 3 196, 3 196, S_0x243f050; + .timescale -9 -12; +P_0x243f2b8 .param/l "i" 3 196, +C4<011>; +S_0x243f350 .scope module, "attempt" "OrNorXor" 3 198, 3 64, S_0x243f1c0; + .timescale -9 -12; +L_0x2483b10/d .functor NOR 1, L_0x2484c90, L_0x2484d30, C4<0>, C4<0>; +L_0x2483b10 .delay (10000,10000,10000) L_0x2483b10/d; +L_0x2483c00/d .functor NOT 1, L_0x2483b10, C4<0>, C4<0>, C4<0>; +L_0x2483c00 .delay (10000,10000,10000) L_0x2483c00/d; +L_0x2483d10/d .functor NAND 1, L_0x2484c90, L_0x2484d30, C4<1>, C4<1>; +L_0x2483d10 .delay (10000,10000,10000) L_0x2483d10/d; +L_0x2483e70/d .functor NAND 1, L_0x2483d10, L_0x2483c00, C4<1>, C4<1>; +L_0x2483e70 .delay (10000,10000,10000) L_0x2483e70/d; +L_0x2483f80/d .functor NOT 1, L_0x2483e70, C4<0>, C4<0>, C4<0>; +L_0x2483f80 .delay (10000,10000,10000) L_0x2483f80/d; +v0x243ff20_0 .net "A", 0 0, L_0x2484c90; 1 drivers +v0x243ffc0_0 .net "AnandB", 0 0, L_0x2483d10; 1 drivers +v0x2440060_0 .net "AnorB", 0 0, L_0x2483b10; 1 drivers +v0x2440110_0 .net "AorB", 0 0, L_0x2483c00; 1 drivers +v0x24401f0_0 .net "AxorB", 0 0, L_0x2483f80; 1 drivers +v0x24402a0_0 .net "B", 0 0, L_0x2484d30; 1 drivers +v0x2440360_0 .alias "Command", 2 0, v0x245d560_0; +v0x24403e0_0 .net "OrNorXorOut", 0 0, L_0x2484980; 1 drivers +v0x2440460_0 .net "XorNor", 0 0, L_0x2484400; 1 drivers +v0x2440530_0 .net "nXor", 0 0, L_0x2483e70; 1 drivers +L_0x2484580 .part v0x245e870_0, 2, 1; +L_0x2484b50 .part v0x245e870_0, 0, 1; +S_0x243f9b0 .scope module, "mux0" "TwoInMux" 3 83, 3 8, S_0x243f350; + .timescale -9 -12; +L_0x24840e0/d .functor NOT 1, L_0x2484580, C4<0>, C4<0>, C4<0>; +L_0x24840e0 .delay (10000,10000,10000) L_0x24840e0/d; +L_0x24841a0/d .functor AND 1, L_0x2483f80, L_0x24840e0, C4<1>, C4<1>; +L_0x24841a0 .delay (20000,20000,20000) L_0x24841a0/d; +L_0x24842b0/d .functor AND 1, L_0x2483b10, L_0x2484580, C4<1>, C4<1>; +L_0x24842b0 .delay (20000,20000,20000) L_0x24842b0/d; +L_0x2484400/d .functor OR 1, L_0x24841a0, L_0x24842b0, C4<0>, C4<0>; +L_0x2484400 .delay (20000,20000,20000) L_0x2484400/d; +v0x243faa0_0 .net "S", 0 0, L_0x2484580; 1 drivers +v0x243fb60_0 .alias "in0", 0 0, v0x24401f0_0; +v0x243fc00_0 .alias "in1", 0 0, v0x2440060_0; +v0x243fca0_0 .net "nS", 0 0, L_0x24840e0; 1 drivers +v0x243fd20_0 .net "out0", 0 0, L_0x24841a0; 1 drivers +v0x243fdc0_0 .net "out1", 0 0, L_0x24842b0; 1 drivers +v0x243fea0_0 .alias "outfinal", 0 0, v0x2440460_0; +S_0x243f440 .scope module, "mux1" "TwoInMux" 3 84, 3 8, S_0x243f350; + .timescale -9 -12; +L_0x2484620/d .functor NOT 1, L_0x2484b50, C4<0>, C4<0>, C4<0>; +L_0x2484620 .delay (10000,10000,10000) L_0x2484620/d; +L_0x24846e0/d .functor AND 1, L_0x2484400, L_0x2484620, C4<1>, C4<1>; +L_0x24846e0 .delay (20000,20000,20000) L_0x24846e0/d; +L_0x2484830/d .functor AND 1, L_0x2483c00, L_0x2484b50, C4<1>, C4<1>; +L_0x2484830 .delay (20000,20000,20000) L_0x2484830/d; +L_0x2484980/d .functor OR 1, L_0x24846e0, L_0x2484830, C4<0>, C4<0>; +L_0x2484980 .delay (20000,20000,20000) L_0x2484980/d; +v0x243f530_0 .net "S", 0 0, L_0x2484b50; 1 drivers +v0x243f5d0_0 .alias "in0", 0 0, v0x2440460_0; +v0x243f670_0 .alias "in1", 0 0, v0x2440110_0; +v0x243f710_0 .net "nS", 0 0, L_0x2484620; 1 drivers +v0x243f790_0 .net "out0", 0 0, L_0x24846e0; 1 drivers +v0x243f830_0 .net "out1", 0 0, L_0x2484830; 1 drivers +v0x243f910_0 .alias "outfinal", 0 0, v0x24403e0_0; +S_0x243e6d0 .scope module, "ZeroMux0case" "FourInMux" 3 315, 3 24, S_0x23d85b0; + .timescale -9 -12; +L_0x2485f80/d .functor NOT 1, L_0x2476bb0, C4<0>, C4<0>, C4<0>; +L_0x2485f80 .delay (10000,10000,10000) L_0x2485f80/d; +L_0x24861d0/d .functor NOT 1, L_0x2476ce0, C4<0>, C4<0>, C4<0>; +L_0x24861d0 .delay (10000,10000,10000) L_0x24861d0/d; +L_0x2486290/d .functor NAND 1, L_0x2485f80, L_0x24861d0, L_0x24868c0, C4<1>; +L_0x2486290 .delay (10000,10000,10000) L_0x2486290/d; +L_0x2486380/d .functor NAND 1, L_0x2476bb0, L_0x24861d0, L_0x2486960, C4<1>; +L_0x2486380 .delay (10000,10000,10000) L_0x2486380/d; +L_0x2486470/d .functor NAND 1, L_0x2485f80, L_0x2476ce0, L_0x2486a00, C4<1>; +L_0x2486470 .delay (10000,10000,10000) L_0x2486470/d; +L_0x2486560/d .functor NAND 1, L_0x2476bb0, L_0x2476ce0, L_0x2486de0, C4<1>; +L_0x2486560 .delay (10000,10000,10000) L_0x2486560/d; +L_0x2486640/d .functor NAND 1, L_0x2486290, L_0x2486380, L_0x2486470, L_0x2486560; +L_0x2486640 .delay (10000,10000,10000) L_0x2486640/d; +v0x243e7c0_0 .net "S0", 0 0, L_0x2476bb0; 1 drivers +v0x243e880_0 .net "S1", 0 0, L_0x2476ce0; 1 drivers +v0x243e920_0 .net "in0", 0 0, L_0x24868c0; 1 drivers +v0x243e9c0_0 .net "in1", 0 0, L_0x2486960; 1 drivers +v0x243ea40_0 .net "in2", 0 0, L_0x2486a00; 1 drivers +v0x243eae0_0 .net "in3", 0 0, L_0x2486de0; 1 drivers +v0x243eb80_0 .net "nS0", 0 0, L_0x2485f80; 1 drivers +v0x243ec20_0 .net "nS1", 0 0, L_0x24861d0; 1 drivers +v0x243ecc0_0 .net "out", 0 0, L_0x2486640; 1 drivers +v0x243ed60_0 .net "out0", 0 0, L_0x2486290; 1 drivers +v0x243ee00_0 .net "out1", 0 0, L_0x2486380; 1 drivers +v0x243eea0_0 .net "out2", 0 0, L_0x2486470; 1 drivers +v0x243efb0_0 .net "out3", 0 0, L_0x2486560; 1 drivers +S_0x243dd10 .scope module, "OneMux0case" "FourInMux" 3 316, 3 24, S_0x23d85b0; + .timescale -9 -12; +L_0x2486b60/d .functor NOT 1, L_0x24876f0, C4<0>, C4<0>, C4<0>; +L_0x2486b60 .delay (10000,10000,10000) L_0x2486b60/d; +L_0x2486c50/d .functor NOT 1, L_0x2486ed0, C4<0>, C4<0>, C4<0>; +L_0x2486c50 .delay (10000,10000,10000) L_0x2486c50/d; +L_0x2486cf0/d .functor NAND 1, L_0x2486b60, L_0x2486c50, L_0x2487000, C4<1>; +L_0x2486cf0 .delay (10000,10000,10000) L_0x2486cf0/d; +L_0x24871b0/d .functor NAND 1, L_0x24876f0, L_0x2486c50, L_0x2487a80, C4<1>; +L_0x24871b0 .delay (10000,10000,10000) L_0x24871b0/d; +L_0x24872a0/d .functor NAND 1, L_0x2486b60, L_0x2486ed0, L_0x2487b20, C4<1>; +L_0x24872a0 .delay (10000,10000,10000) L_0x24872a0/d; +L_0x2487390/d .functor NAND 1, L_0x24876f0, L_0x2486ed0, L_0x2487820, C4<1>; +L_0x2487390 .delay (10000,10000,10000) L_0x2487390/d; +L_0x2487470/d .functor NAND 1, L_0x2486cf0, L_0x24871b0, L_0x24872a0, L_0x2487390; +L_0x2487470 .delay (10000,10000,10000) L_0x2487470/d; +v0x243de00_0 .net "S0", 0 0, L_0x24876f0; 1 drivers +v0x243dec0_0 .net "S1", 0 0, L_0x2486ed0; 1 drivers +v0x243df60_0 .net "in0", 0 0, L_0x2487000; 1 drivers +v0x243e000_0 .net "in1", 0 0, L_0x2487a80; 1 drivers +v0x243e080_0 .net "in2", 0 0, L_0x2487b20; 1 drivers +v0x243e120_0 .net "in3", 0 0, L_0x2487820; 1 drivers +v0x243e200_0 .net "nS0", 0 0, L_0x2486b60; 1 drivers +v0x243e2a0_0 .net "nS1", 0 0, L_0x2486c50; 1 drivers +v0x243e340_0 .net "out", 0 0, L_0x2487470; 1 drivers +v0x243e3e0_0 .net "out0", 0 0, L_0x2486cf0; 1 drivers +v0x243e480_0 .net "out1", 0 0, L_0x24871b0; 1 drivers +v0x243e520_0 .net "out2", 0 0, L_0x24872a0; 1 drivers +v0x243e630_0 .net "out3", 0 0, L_0x2487390; 1 drivers +S_0x243d7c0 .scope module, "TwoMux0case" "TwoInMux" 3 317, 3 8, S_0x23d85b0; + .timescale -9 -12; +L_0x2487910/d .functor NOT 1, L_0x2487bc0, C4<0>, C4<0>, C4<0>; +L_0x2487910 .delay (10000,10000,10000) L_0x2487910/d; +L_0x2487a00/d .functor AND 1, L_0x2487c60, L_0x2487910, C4<1>, C4<1>; +L_0x2487a00 .delay (20000,20000,20000) L_0x2487a00/d; +L_0x2487ec0/d .functor AND 1, L_0x2487d50, L_0x2487bc0, C4<1>, C4<1>; +L_0x2487ec0 .delay (20000,20000,20000) L_0x2487ec0/d; +L_0x2487fb0/d .functor OR 1, L_0x2487a00, L_0x2487ec0, C4<0>, C4<0>; +L_0x2487fb0 .delay (20000,20000,20000) L_0x2487fb0/d; +v0x243d8b0_0 .net "S", 0 0, L_0x2487bc0; 1 drivers +v0x243d970_0 .net "in0", 0 0, L_0x2487c60; 1 drivers +v0x243da10_0 .net "in1", 0 0, L_0x2487d50; 1 drivers +v0x243dab0_0 .net "nS", 0 0, L_0x2487910; 1 drivers +v0x243db30_0 .net "out0", 0 0, L_0x2487a00; 1 drivers +v0x243dbd0_0 .net "out1", 0 0, L_0x2487ec0; 1 drivers +v0x243dc70_0 .net "outfinal", 0 0, L_0x2487fb0; 1 drivers +S_0x243bc40 .scope generate, "muxbits[1]" "muxbits[1]" 3 322, 3 322, S_0x23d85b0; + .timescale -9 -12; +P_0x243ac38 .param/l "i" 3 322, +C4<01>; +L_0x2471220/d .functor OR 1, L_0x2471320, L_0x24710e0, C4<0>, C4<0>; +L_0x2471220 .delay (20000,20000,20000) L_0x2471220/d; +v0x243d660_0 .net *"_s15", 0 0, L_0x2471320; 1 drivers +v0x243d720_0 .net *"_s16", 0 0, L_0x24710e0; 1 drivers +S_0x243cce0 .scope module, "ZeroMux" "FourInMux" 3 324, 3 24, S_0x243bc40; + .timescale -9 -12; +L_0x246eae0/d .functor NOT 1, L_0x246f420, C4<0>, C4<0>, C4<0>; L_0x246eae0 .delay (10000,10000,10000) L_0x246eae0/d; -L_0x246ebd0/d .functor NAND 1, L_0x246f170, L_0x246e670, L_0x246f2a0, C4<1>; -L_0x246ebd0 .delay (10000,10000,10000) L_0x246ebd0/d; -L_0x246ecc0/d .functor NAND 1, L_0x246e5d0, L_0x246e980, L_0x246f340, C4<1>; -L_0x246ecc0 .delay (10000,10000,10000) L_0x246ecc0/d; -L_0x246edb0/d .functor NAND 1, L_0x246f170, L_0x246e980, L_0x246f5c0, C4<1>; -L_0x246edb0 .delay (10000,10000,10000) L_0x246edb0/d; -L_0x246eec0/d .functor NAND 1, L_0x246eae0, L_0x246ebd0, L_0x246ecc0, L_0x246edb0; -L_0x246eec0 .delay (10000,10000,10000) L_0x246eec0/d; -v0x2270d90_0 .net "S0", 0 0, L_0x246f170; 1 drivers -v0x22a4d80_0 .net "S1", 0 0, L_0x246e980; 1 drivers -v0x22a4e20_0 .net "in0", 0 0, L_0x246f410; 1 drivers -v0x22e6db0_0 .net "in1", 0 0, L_0x246f2a0; 1 drivers -v0x22e6e30_0 .net "in2", 0 0, L_0x246f340; 1 drivers -v0x2210090_0 .net "in3", 0 0, L_0x246f5c0; 1 drivers -v0x2210130_0 .net "nS0", 0 0, L_0x246e5d0; 1 drivers -v0x22101d0_0 .net "nS1", 0 0, L_0x246e670; 1 drivers -v0x21ecd40_0 .net "out", 0 0, L_0x246eec0; 1 drivers -v0x21ecdc0_0 .net "out0", 0 0, L_0x246eae0; 1 drivers -v0x21ece60_0 .net "out1", 0 0, L_0x246ebd0; 1 drivers -v0x2376fb0_0 .net "out2", 0 0, L_0x246ecc0; 1 drivers -v0x23770c0_0 .net "out3", 0 0, L_0x246edb0; 1 drivers -S_0x22a6850 .scope module, "OneMux" "FourInMux" 2 293, 2 24, S_0x22c6fe0; - .timescale -9 -12; -L_0x246f6b0/d .functor NOT 1, L_0x246f850, C4<0>, C4<0>, C4<0>; -L_0x246f6b0 .delay (10000,10000,10000) L_0x246f6b0/d; -L_0x246f9e0/d .functor NOT 1, L_0x24702c0, C4<0>, C4<0>, C4<0>; -L_0x246f9e0 .delay (10000,10000,10000) L_0x246f9e0/d; -L_0x246fa40/d .functor NAND 1, L_0x246f6b0, L_0x246f9e0, L_0x2470120, C4<1>; -L_0x246fa40 .delay (10000,10000,10000) L_0x246fa40/d; -L_0x246fb80/d .functor NAND 1, L_0x246f850, L_0x246f9e0, L_0x24701c0, C4<1>; -L_0x246fb80 .delay (10000,10000,10000) L_0x246fb80/d; -L_0x246fc70/d .functor NAND 1, L_0x246f6b0, L_0x24702c0, L_0x24705b0, C4<1>; -L_0x246fc70 .delay (10000,10000,10000) L_0x246fc70/d; -L_0x246fd60/d .functor NAND 1, L_0x246f850, L_0x24702c0, L_0x2470650, C4<1>; -L_0x246fd60 .delay (10000,10000,10000) L_0x246fd60/d; -L_0x246fe70/d .functor NAND 1, L_0x246fa40, L_0x246fb80, L_0x246fc70, L_0x246fd60; -L_0x246fe70 .delay (10000,10000,10000) L_0x246fe70/d; -v0x22a6940_0 .net "S0", 0 0, L_0x246f850; 1 drivers -v0x2293360_0 .net "S1", 0 0, L_0x24702c0; 1 drivers -v0x2293400_0 .net "in0", 0 0, L_0x2470120; 1 drivers -v0x228f7f0_0 .net "in1", 0 0, L_0x24701c0; 1 drivers -v0x228f870_0 .net "in2", 0 0, L_0x24705b0; 1 drivers -v0x228d800_0 .net "in3", 0 0, L_0x2470650; 1 drivers -v0x228d8a0_0 .net "nS0", 0 0, L_0x246f6b0; 1 drivers -v0x2289c90_0 .net "nS1", 0 0, L_0x246f9e0; 1 drivers -v0x2289d30_0 .net "out", 0 0, L_0x246fe70; 1 drivers -v0x2287ca0_0 .net "out0", 0 0, L_0x246fa40; 1 drivers -v0x2287d40_0 .net "out1", 0 0, L_0x246fb80; 1 drivers -v0x2272c90_0 .net "out2", 0 0, L_0x246fc70; 1 drivers -v0x2272d30_0 .net "out3", 0 0, L_0x246fd60; 1 drivers -S_0x22b1f10 .scope module, "TwoMux" "TwoInMux" 2 294, 2 8, S_0x22c6fe0; - .timescale -9 -12; -L_0x24703f0/d .functor NOT 1, L_0x2470be0, C4<0>, C4<0>, C4<0>; -L_0x24703f0 .delay (10000,10000,10000) L_0x24703f0/d; -L_0x24704e0/d .functor AND 1, L_0x24706f0, L_0x24703f0, C4<1>, C4<1>; -L_0x24704e0 .delay (20000,20000,20000) L_0x24704e0/d; -L_0x2470910/d .functor AND 1, L_0x24707e0, L_0x2470be0, C4<1>, C4<1>; -L_0x2470910 .delay (20000,20000,20000) L_0x2470910/d; -L_0x2470a00/d .functor OR 1, L_0x24704e0, L_0x2470910, C4<0>, C4<0>; -L_0x2470a00 .delay (20000,20000,20000) L_0x2470a00/d; -v0x22b2000_0 .net "S", 0 0, L_0x2470be0; 1 drivers -v0x22aff20_0 .net "in0", 0 0, L_0x24706f0; 1 drivers -v0x22affa0_0 .net "in1", 0 0, L_0x24707e0; 1 drivers -v0x22ac3b0_0 .net "nS", 0 0, L_0x24703f0; 1 drivers -v0x22ac430_0 .net "out0", 0 0, L_0x24704e0; 1 drivers -v0x22aa3c0_0 .net "out1", 0 0, L_0x2470910; 1 drivers -v0x22aa460_0 .net "outfinal", 0 0, L_0x2470a00; 1 drivers -S_0x2308aa0 .scope generate, "muxbits[4]" "muxbits[4]" 2 290, 2 290, S_0x22690e0; - .timescale -9 -12; -P_0x22f0f38 .param/l "i" 2 290, +C4<0100>; -L_0x24736d0/d .functor OR 1, L_0x2473b50, L_0x2473d00, C4<0>, C4<0>; -L_0x24736d0 .delay (20000,20000,20000) L_0x24736d0/d; -v0x22c90b0_0 .net *"_s15", 0 0, L_0x2473b50; 1 drivers -v0x22c9170_0 .net *"_s16", 0 0, L_0x2473d00; 1 drivers -S_0x22ea580 .scope module, "ZeroMux" "FourInMux" 2 292, 2 24, S_0x2308aa0; - .timescale -9 -12; -L_0x2470fa0/d .functor NOT 1, L_0x2471140, C4<0>, C4<0>, C4<0>; -L_0x2470fa0 .delay (10000,10000,10000) L_0x2470fa0/d; -L_0x2471340/d .functor NOT 1, L_0x2471270, C4<0>, C4<0>, C4<0>; -L_0x2471340 .delay (10000,10000,10000) L_0x2471340/d; -L_0x24713a0/d .functor NAND 1, L_0x2470fa0, L_0x2471340, L_0x2471b10, C4<1>; -L_0x24713a0 .delay (10000,10000,10000) L_0x24713a0/d; -L_0x24714e0/d .functor NAND 1, L_0x2471140, L_0x2471340, L_0x2471bb0, C4<1>; -L_0x24714e0 .delay (10000,10000,10000) L_0x24714e0/d; -L_0x24715d0/d .functor NAND 1, L_0x2470fa0, L_0x2471270, L_0x2471c50, C4<1>; -L_0x24715d0 .delay (10000,10000,10000) L_0x24715d0/d; -L_0x24716f0/d .functor NAND 1, L_0x2471140, L_0x2471270, L_0x2472030, C4<1>; -L_0x24716f0 .delay (10000,10000,10000) L_0x24716f0/d; -L_0x2471860/d .functor NAND 1, L_0x24713a0, L_0x24714e0, L_0x24715d0, L_0x24716f0; -L_0x2471860 .delay (10000,10000,10000) L_0x2471860/d; -v0x22ea670_0 .net "S0", 0 0, L_0x2471140; 1 drivers -v0x22ec6d0_0 .net "S1", 0 0, L_0x2471270; 1 drivers -v0x22675d0_0 .net "in0", 0 0, L_0x2471b10; 1 drivers -v0x2267670_0 .net "in1", 0 0, L_0x2471bb0; 1 drivers -v0x22d4cf0_0 .net "in2", 0 0, L_0x2471c50; 1 drivers -v0x22d4d90_0 .net "in3", 0 0, L_0x2472030; 1 drivers -v0x22d2c40_0 .net "nS0", 0 0, L_0x2470fa0; 1 drivers -v0x22d2ce0_0 .net "nS1", 0 0, L_0x2471340; 1 drivers -v0x22ceed0_0 .net "out", 0 0, L_0x2471860; 1 drivers -v0x22cef70_0 .net "out0", 0 0, L_0x24713a0; 1 drivers -v0x22cce20_0 .net "out1", 0 0, L_0x24714e0; 1 drivers -v0x22ccec0_0 .net "out2", 0 0, L_0x24715d0; 1 drivers -v0x2265670_0 .net "out3", 0 0, L_0x24716f0; 1 drivers -S_0x2309d90 .scope module, "OneMux" "FourInMux" 2 293, 2 24, S_0x2308aa0; - .timescale -9 -12; -L_0x2471db0/d .functor NOT 1, L_0x24729d0, C4<0>, C4<0>, C4<0>; -L_0x2471db0 .delay (10000,10000,10000) L_0x2471db0/d; -L_0x2471ea0/d .functor NOT 1, L_0x2472120, C4<0>, C4<0>, C4<0>; -L_0x2471ea0 .delay (10000,10000,10000) L_0x2471ea0/d; -L_0x2471f40/d .functor NAND 1, L_0x2471db0, L_0x2471ea0, L_0x2472250, C4<1>; -L_0x2471f40 .delay (10000,10000,10000) L_0x2471f40/d; -L_0x2472400/d .functor NAND 1, L_0x24729d0, L_0x2471ea0, L_0x2472b00, C4<1>; -L_0x2472400 .delay (10000,10000,10000) L_0x2472400/d; -L_0x24724f0/d .functor NAND 1, L_0x2471db0, L_0x2472120, L_0x2472ba0, C4<1>; -L_0x24724f0 .delay (10000,10000,10000) L_0x24724f0/d; -L_0x24725e0/d .functor NAND 1, L_0x24729d0, L_0x2472120, L_0x2472c90, C4<1>; -L_0x24725e0 .delay (10000,10000,10000) L_0x24725e0/d; -L_0x2472720/d .functor NAND 1, L_0x2471f40, L_0x2472400, L_0x24724f0, L_0x24725e0; -L_0x2472720 .delay (10000,10000,10000) L_0x2472720/d; -v0x2309e80_0 .net "S0", 0 0, L_0x24729d0; 1 drivers -v0x226d1d0_0 .net "S1", 0 0, L_0x2472120; 1 drivers -v0x2307cc0_0 .net "in0", 0 0, L_0x2472250; 1 drivers -v0x2307d60_0 .net "in1", 0 0, L_0x2472b00; 1 drivers -v0x226b140_0 .net "in2", 0 0, L_0x2472ba0; 1 drivers -v0x226b1e0_0 .net "in3", 0 0, L_0x2472c90; 1 drivers -v0x22f61c0_0 .net "nS0", 0 0, L_0x2471db0; 1 drivers -v0x22f6260_0 .net "nS1", 0 0, L_0x2471ea0; 1 drivers -v0x22f2450_0 .net "out", 0 0, L_0x2472720; 1 drivers -v0x22f24f0_0 .net "out0", 0 0, L_0x2471f40; 1 drivers -v0x22f03a0_0 .net "out1", 0 0, L_0x2472400; 1 drivers -v0x22f0440_0 .net "out2", 0 0, L_0x24724f0; 1 drivers -v0x22ec630_0 .net "out3", 0 0, L_0x24725e0; 1 drivers -S_0x23087f0 .scope module, "TwoMux" "TwoInMux" 2 294, 2 8, S_0x2308aa0; - .timescale -9 -12; -L_0x246da20/d .functor NOT 1, L_0x2472e60, C4<0>, C4<0>, C4<0>; -L_0x246da20 .delay (10000,10000,10000) L_0x246da20/d; -L_0x2473160/d .functor AND 1, L_0x2472f00, L_0x246da20, C4<1>, C4<1>; -L_0x2473160 .delay (20000,20000,20000) L_0x2473160/d; -L_0x2473250/d .functor AND 1, L_0x2472ff0, L_0x2472e60, C4<1>, C4<1>; -L_0x2473250 .delay (20000,20000,20000) L_0x2473250/d; -L_0x2473340/d .functor OR 1, L_0x2473160, L_0x2473250, C4<0>, C4<0>; -L_0x2473340 .delay (20000,20000,20000) L_0x2473340/d; -v0x230a410_0 .net "S", 0 0, L_0x2472e60; 1 drivers -v0x230bdb0_0 .net "in0", 0 0, L_0x2472f00; 1 drivers -v0x230be50_0 .net "in1", 0 0, L_0x2472ff0; 1 drivers -v0x2308540_0 .net "nS", 0 0, L_0x246da20; 1 drivers -v0x23085c0_0 .net "out0", 0 0, L_0x2473160; 1 drivers -v0x23082a0_0 .net "out1", 0 0, L_0x2473250; 1 drivers -v0x226d130_0 .net "outfinal", 0 0, L_0x2473340; 1 drivers -S_0x22eb090 .scope generate, "muxbits[5]" "muxbits[5]" 2 290, 2 290, S_0x22690e0; - .timescale -9 -12; -P_0x22d9088 .param/l "i" 2 290, +C4<0101>; -L_0x2475e70/d .functor OR 1, L_0x2475fb0, L_0x2476050, C4<0>, C4<0>; -L_0x2475e70 .delay (20000,20000,20000) L_0x2475e70/d; -v0x230a6d0_0 .net *"_s15", 0 0, L_0x2475fb0; 1 drivers -v0x230a390_0 .net *"_s16", 0 0, L_0x2476050; 1 drivers -S_0x22f6780 .scope module, "ZeroMux" "FourInMux" 2 292, 2 24, S_0x22eb090; - .timescale -9 -12; -L_0x246e8f0/d .functor NOT 1, L_0x24745b0, C4<0>, C4<0>, C4<0>; -L_0x246e8f0 .delay (10000,10000,10000) L_0x246e8f0/d; -L_0x2473900/d .functor NOT 1, L_0x2473eb0, C4<0>, C4<0>, C4<0>; -L_0x2473900 .delay (10000,10000,10000) L_0x2473900/d; -L_0x2473960/d .functor NAND 1, L_0x246e8f0, L_0x2473900, L_0x2473fe0, C4<1>; -L_0x2473960 .delay (10000,10000,10000) L_0x2473960/d; -L_0x2473a60/d .functor NAND 1, L_0x24745b0, L_0x2473900, L_0x2474080, C4<1>; -L_0x2473a60 .delay (10000,10000,10000) L_0x2473a60/d; -L_0x2474160/d .functor NAND 1, L_0x246e8f0, L_0x2473eb0, L_0x24749b0, C4<1>; -L_0x2474160 .delay (10000,10000,10000) L_0x2474160/d; -L_0x2474250/d .functor NAND 1, L_0x24745b0, L_0x2473eb0, L_0x24746e0, C4<1>; -L_0x2474250 .delay (10000,10000,10000) L_0x2474250/d; -L_0x2474330/d .functor NAND 1, L_0x2473960, L_0x2473a60, L_0x2474160, L_0x2474250; -L_0x2474330 .delay (10000,10000,10000) L_0x2474330/d; -v0x22f88b0_0 .net "S0", 0 0, L_0x24745b0; 1 drivers -v0x22fe670_0 .net "S1", 0 0, L_0x2473eb0; 1 drivers -v0x22fe710_0 .net "in0", 0 0, L_0x2473fe0; 1 drivers -v0x22fc580_0 .net "in1", 0 0, L_0x2474080; 1 drivers -v0x22fc620_0 .net "in2", 0 0, L_0x24749b0; 1 drivers -v0x23044d0_0 .net "in3", 0 0, L_0x24746e0; 1 drivers -v0x2304570_0 .net "nS0", 0 0, L_0x246e8f0; 1 drivers -v0x23023e0_0 .net "nS1", 0 0, L_0x2473900; 1 drivers -v0x2302480_0 .net "out", 0 0, L_0x2474330; 1 drivers -v0x230ab90_0 .net "out0", 0 0, L_0x2473960; 1 drivers -v0x230ac30_0 .net "out1", 0 0, L_0x2473a60; 1 drivers -v0x230a8e0_0 .net "out2", 0 0, L_0x2474160; 1 drivers -v0x230a630_0 .net "out3", 0 0, L_0x2474250; 1 drivers -S_0x22f2cf0 .scope module, "OneMux" "FourInMux" 2 293, 2 24, S_0x22eb090; - .timescale -9 -12; -L_0x246f4b0/d .functor NOT 1, L_0x2474aa0, C4<0>, C4<0>, C4<0>; -L_0x246f4b0 .delay (10000,10000,10000) L_0x246f4b0/d; -L_0x246f560/d .functor NOT 1, L_0x2474bd0, C4<0>, C4<0>, C4<0>; -L_0x246f560 .delay (10000,10000,10000) L_0x246f560/d; -L_0x2474810/d .functor NAND 1, L_0x246f4b0, L_0x246f560, L_0x2475770, C4<1>; -L_0x2474810 .delay (10000,10000,10000) L_0x2474810/d; -L_0x2474950/d .functor NAND 1, L_0x2474aa0, L_0x246f560, L_0x2475810, C4<1>; -L_0x2474950 .delay (10000,10000,10000) L_0x2474950/d; -L_0x2475020/d .functor NAND 1, L_0x246f4b0, L_0x2474bd0, L_0x2475470, C4<1>; -L_0x2475020 .delay (10000,10000,10000) L_0x2475020/d; -L_0x2475110/d .functor NAND 1, L_0x2474aa0, L_0x2474bd0, L_0x2475560, C4<1>; -L_0x2475110 .delay (10000,10000,10000) L_0x2475110/d; -L_0x24751f0/d .functor NAND 1, L_0x2474810, L_0x2474950, L_0x2475020, L_0x2475110; -L_0x24751f0 .delay (10000,10000,10000) L_0x24751f0/d; -v0x22f3040_0 .net "S0", 0 0, L_0x2474aa0; 1 drivers -v0x22f2a50_0 .net "S1", 0 0, L_0x2474bd0; 1 drivers -v0x22f2af0_0 .net "in0", 0 0, L_0x2475770; 1 drivers -v0x22f1160_0 .net "in1", 0 0, L_0x2475810; 1 drivers -v0x22f1200_0 .net "in2", 0 0, L_0x2475470; 1 drivers -v0x22f0eb0_0 .net "in3", 0 0, L_0x2475560; 1 drivers -v0x22f4470_0 .net "nS0", 0 0, L_0x246f4b0; 1 drivers -v0x22f4510_0 .net "nS1", 0 0, L_0x246f560; 1 drivers -v0x22f0c00_0 .net "out", 0 0, L_0x24751f0; 1 drivers -v0x22f0ca0_0 .net "out0", 0 0, L_0x2474810; 1 drivers -v0x22f0960_0 .net "out1", 0 0, L_0x2474950; 1 drivers -v0x22f0a00_0 .net "out2", 0 0, L_0x2475020; 1 drivers -v0x22f8810_0 .net "out3", 0 0, L_0x2475110; 1 drivers -S_0x22ee650 .scope module, "TwoMux" "TwoInMux" 2 294, 2 8, S_0x22eb090; - .timescale -9 -12; -L_0x2474d00/d .functor NOT 1, L_0x2475b20, C4<0>, C4<0>, C4<0>; -L_0x2474d00 .delay (10000,10000,10000) L_0x2474d00/d; -L_0x246f7d0/d .functor AND 1, L_0x2476100, L_0x2474d00, C4<1>, C4<1>; -L_0x246f7d0 .delay (20000,20000,20000) L_0x246f7d0/d; -L_0x24756e0/d .functor AND 1, L_0x24761f0, L_0x2475b20, C4<1>, C4<1>; -L_0x24756e0 .delay (20000,20000,20000) L_0x24756e0/d; -L_0x2475940/d .functor OR 1, L_0x246f7d0, L_0x24756e0, C4<0>, C4<0>; -L_0x2475940 .delay (20000,20000,20000) L_0x2475940/d; -v0x22eade0_0 .net "S", 0 0, L_0x2475b20; 1 drivers -v0x22eae80_0 .net "in0", 0 0, L_0x2476100; 1 drivers -v0x22eab40_0 .net "in1", 0 0, L_0x24761f0; 1 drivers -v0x22eabe0_0 .net "nS", 0 0, L_0x2474d00; 1 drivers -v0x22f3250_0 .net "out0", 0 0, L_0x246f7d0; 1 drivers -v0x22f32f0_0 .net "out1", 0 0, L_0x24756e0; 1 drivers -v0x22f2fa0_0 .net "outfinal", 0 0, L_0x2475940; 1 drivers -S_0x22cd3e0 .scope generate, "muxbits[6]" "muxbits[6]" 2 290, 2 290, S_0x22690e0; - .timescale -9 -12; -P_0x22c9738 .param/l "i" 2 290, +C4<0110>; -L_0x243e4e0/d .functor OR 1, L_0x243e5e0, L_0x243e680, C4<0>, C4<0>; -L_0x243e4e0 .delay (20000,20000,20000) L_0x243e4e0/d; -v0x22eb340_0 .net *"_s15", 0 0, L_0x243e5e0; 1 drivers -v0x22eb400_0 .net *"_s16", 0 0, L_0x243e680; 1 drivers -S_0x22e70b0 .scope module, "ZeroMux" "FourInMux" 2 292, 2 24, S_0x22cd3e0; - .timescale -9 -12; -L_0x2476680/d .functor NOT 1, L_0x24762e0, C4<0>, C4<0>, C4<0>; -L_0x2476680 .delay (10000,10000,10000) L_0x2476680/d; -L_0x2476770/d .functor NOT 1, L_0x2476410, C4<0>, C4<0>, C4<0>; -L_0x2476770 .delay (10000,10000,10000) L_0x2476770/d; -L_0x2476810/d .functor NAND 1, L_0x2476680, L_0x2476770, L_0x2476540, C4<1>; -L_0x2476810 .delay (10000,10000,10000) L_0x2476810/d; -L_0x2476950/d .functor NAND 1, L_0x24762e0, L_0x2476770, L_0x2477200, C4<1>; -L_0x2476950 .delay (10000,10000,10000) L_0x2476950/d; -L_0x2476a40/d .functor NAND 1, L_0x2476680, L_0x2476410, L_0x2476e90, C4<1>; -L_0x2476a40 .delay (10000,10000,10000) L_0x2476a40/d; -L_0x2476b30/d .functor NAND 1, L_0x24762e0, L_0x2476410, L_0x2476f30, C4<1>; -L_0x2476b30 .delay (10000,10000,10000) L_0x2476b30/d; -L_0x2476c10/d .functor NAND 1, L_0x2476810, L_0x2476950, L_0x2476a40, L_0x2476b30; -L_0x2476c10 .delay (10000,10000,10000) L_0x2476c10/d; -v0x22e7400_0 .net "S0", 0 0, L_0x24762e0; 1 drivers -v0x22e8830_0 .net "S1", 0 0, L_0x2476410; 1 drivers -v0x22e88d0_0 .net "in0", 0 0, L_0x2476540; 1 drivers -v0x22e4cc0_0 .net "in1", 0 0, L_0x2477200; 1 drivers -v0x22e4d60_0 .net "in2", 0 0, L_0x2476e90; 1 drivers -v0x22ed430_0 .net "in3", 0 0, L_0x2476f30; 1 drivers -v0x22ed4d0_0 .net "nS0", 0 0, L_0x2476680; 1 drivers -v0x22ed180_0 .net "nS1", 0 0, L_0x2476770; 1 drivers -v0x22ed220_0 .net "out", 0 0, L_0x2476c10; 1 drivers -v0x22eced0_0 .net "out0", 0 0, L_0x2476810; 1 drivers -v0x22ecf70_0 .net "out1", 0 0, L_0x2476950; 1 drivers -v0x22ecc30_0 .net "out2", 0 0, L_0x2476a40; 1 drivers -v0x22eccd0_0 .net "out3", 0 0, L_0x2476b30; 1 drivers -S_0x22d34a0 .scope module, "OneMux" "FourInMux" 2 293, 2 24, S_0x22cd3e0; - .timescale -9 -12; -L_0x2477020/d .functor NOT 1, L_0x2477c60, C4<0>, C4<0>, C4<0>; -L_0x2477020 .delay (10000,10000,10000) L_0x2477020/d; -L_0x2477110/d .functor NOT 1, L_0x24772a0, C4<0>, C4<0>, C4<0>; -L_0x2477110 .delay (10000,10000,10000) L_0x2477110/d; -L_0x2477630/d .functor NAND 1, L_0x2477020, L_0x2477110, L_0x24773d0, C4<1>; -L_0x2477630 .delay (10000,10000,10000) L_0x2477630/d; -L_0x2477720/d .functor NAND 1, L_0x2477c60, L_0x2477110, L_0x2477470, C4<1>; -L_0x2477720 .delay (10000,10000,10000) L_0x2477720/d; -L_0x2477810/d .functor NAND 1, L_0x2477020, L_0x24772a0, L_0x2477510, C4<1>; -L_0x2477810 .delay (10000,10000,10000) L_0x2477810/d; -L_0x2477900/d .functor NAND 1, L_0x2477c60, L_0x24772a0, L_0x2477d90, C4<1>; -L_0x2477900 .delay (10000,10000,10000) L_0x2477900/d; -L_0x24779e0/d .functor NAND 1, L_0x2477630, L_0x2477720, L_0x2477810, L_0x2477900; -L_0x24779e0 .delay (10000,10000,10000) L_0x24779e0/d; -v0x22d37f0_0 .net "S0", 0 0, L_0x2477c60; 1 drivers -v0x22d3200_0 .net "S1", 0 0, L_0x24772a0; 1 drivers -v0x22d32a0_0 .net "in0", 0 0, L_0x24773d0; 1 drivers -v0x22db0f0_0 .net "in1", 0 0, L_0x2477470; 1 drivers -v0x22db190_0 .net "in2", 0 0, L_0x2477510; 1 drivers -v0x22d9000_0 .net "in3", 0 0, L_0x2477d90; 1 drivers -v0x22e0f50_0 .net "nS0", 0 0, L_0x2477020; 1 drivers -v0x22e0ff0_0 .net "nS1", 0 0, L_0x2477110; 1 drivers -v0x22dee60_0 .net "out", 0 0, L_0x24779e0; 1 drivers -v0x22def00_0 .net "out0", 0 0, L_0x2477630; 1 drivers -v0x22e7610_0 .net "out1", 0 0, L_0x2477720; 1 drivers -v0x22e76b0_0 .net "out2", 0 0, L_0x2477810; 1 drivers -v0x22e7360_0 .net "out3", 0 0, L_0x2477900; 1 drivers -S_0x22d5840 .scope module, "TwoMux" "TwoInMux" 2 294, 2 8, S_0x22cd3e0; - .timescale -9 -12; -L_0x2477e80/d .functor NOT 1, L_0x243e990, C4<0>, C4<0>, C4<0>; -L_0x2477e80 .delay (10000,10000,10000) L_0x2477e80/d; -L_0x2477f30/d .functor AND 1, L_0x243ea30, L_0x2477e80, C4<1>, C4<1>; -L_0x2477f30 .delay (20000,20000,20000) L_0x2477f30/d; -L_0x2477fe0/d .functor AND 1, L_0x243eb20, L_0x243e990, C4<1>, C4<1>; -L_0x2477fe0 .delay (20000,20000,20000) L_0x2477fe0/d; -L_0x24780d0/d .functor OR 1, L_0x2477f30, L_0x2477fe0, C4<0>, C4<0>; -L_0x24780d0 .delay (20000,20000,20000) L_0x24780d0/d; -v0x22cd700_0 .net "S", 0 0, L_0x243e990; 1 drivers -v0x22d5590_0 .net "in0", 0 0, L_0x243ea30; 1 drivers -v0x22d5630_0 .net "in1", 0 0, L_0x243eb20; 1 drivers -v0x22d52f0_0 .net "nS", 0 0, L_0x2477e80; 1 drivers -v0x22d5370_0 .net "out0", 0 0, L_0x2477f30; 1 drivers -v0x22d3a00_0 .net "out1", 0 0, L_0x2477fe0; 1 drivers -v0x22d3750_0 .net "outfinal", 0 0, L_0x24780d0; 1 drivers -S_0x22b24b0 .scope generate, "muxbits[7]" "muxbits[7]" 2 290, 2 290, S_0x22690e0; - .timescale -9 -12; -P_0x22a5108 .param/l "i" 2 290, +C4<0111>; -L_0x247b230/d .functor OR 1, L_0x247b370, L_0x247ba00, C4<0>, C4<0>; -L_0x247b230 .delay (20000,20000,20000) L_0x247b230/d; -v0x22d0f90_0 .net *"_s15", 0 0, L_0x247b370; 1 drivers -v0x22cd680_0 .net *"_s16", 0 0, L_0x247ba00; 1 drivers -S_0x22c75c0 .scope module, "ZeroMux" "FourInMux" 2 292, 2 24, S_0x22b24b0; - .timescale -9 -12; -L_0x243e770/d .functor NOT 1, L_0x2479c00, C4<0>, C4<0>, C4<0>; -L_0x243e770 .delay (10000,10000,10000) L_0x243e770/d; -L_0x243e820/d .functor NOT 1, L_0x2479140, C4<0>, C4<0>, C4<0>; -L_0x243e820 .delay (10000,10000,10000) L_0x243e820/d; -L_0x2479580/d .functor NAND 1, L_0x243e770, L_0x243e820, L_0x2479270, C4<1>; -L_0x2479580 .delay (10000,10000,10000) L_0x2479580/d; -L_0x24796c0/d .functor NAND 1, L_0x2479c00, L_0x243e820, L_0x2479310, C4<1>; -L_0x24796c0 .delay (10000,10000,10000) L_0x24796c0/d; -L_0x24797b0/d .functor NAND 1, L_0x243e770, L_0x2479140, L_0x24793b0, C4<1>; -L_0x24797b0 .delay (10000,10000,10000) L_0x24797b0/d; -L_0x24798a0/d .functor NAND 1, L_0x2479c00, L_0x2479140, L_0x24794a0, C4<1>; -L_0x24798a0 .delay (10000,10000,10000) L_0x24798a0/d; -L_0x2479980/d .functor NAND 1, L_0x2479580, L_0x24796c0, L_0x24797b0, L_0x24798a0; -L_0x2479980 .delay (10000,10000,10000) L_0x2479980/d; -v0x22c7900_0 .net "S0", 0 0, L_0x2479c00; 1 drivers -v0x22cfcd0_0 .net "S1", 0 0, L_0x2479140; 1 drivers -v0x22cfd70_0 .net "in0", 0 0, L_0x2479270; 1 drivers -v0x22cfa20_0 .net "in1", 0 0, L_0x2479310; 1 drivers -v0x22cfac0_0 .net "in2", 0 0, L_0x24793b0; 1 drivers -v0x22cf770_0 .net "in3", 0 0, L_0x24794a0; 1 drivers -v0x22cf810_0 .net "nS0", 0 0, L_0x243e770; 1 drivers -v0x22cf4d0_0 .net "nS1", 0 0, L_0x243e820; 1 drivers -v0x22cf570_0 .net "out", 0 0, L_0x2479980; 1 drivers -v0x22cdbe0_0 .net "out0", 0 0, L_0x2479580; 1 drivers -v0x22cdc80_0 .net "out1", 0 0, L_0x24796c0; 1 drivers -v0x22cd930_0 .net "out2", 0 0, L_0x24797b0; 1 drivers -v0x22d0ef0_0 .net "out3", 0 0, L_0x24798a0; 1 drivers -S_0x22c9eb0 .scope module, "OneMux" "FourInMux" 2 293, 2 24, S_0x22b24b0; - .timescale -9 -12; -L_0x247a1b0/d .functor NOT 1, L_0x2479d30, C4<0>, C4<0>, C4<0>; -L_0x247a1b0 .delay (10000,10000,10000) L_0x247a1b0/d; -L_0x247a2a0/d .functor NOT 1, L_0x2479e60, C4<0>, C4<0>, C4<0>; -L_0x247a2a0 .delay (10000,10000,10000) L_0x247a2a0/d; -L_0x247a340/d .functor NAND 1, L_0x247a1b0, L_0x247a2a0, L_0x2479f90, C4<1>; -L_0x247a340 .delay (10000,10000,10000) L_0x247a340/d; -L_0x247a480/d .functor NAND 1, L_0x2479d30, L_0x247a2a0, L_0x247a030, C4<1>; -L_0x247a480 .delay (10000,10000,10000) L_0x247a480/d; -L_0x247a570/d .functor NAND 1, L_0x247a1b0, L_0x2479e60, L_0x247ae20, C4<1>; -L_0x247a570 .delay (10000,10000,10000) L_0x247a570/d; -L_0x247a660/d .functor NAND 1, L_0x2479d30, L_0x2479e60, L_0x247aec0, C4<1>; -L_0x247a660 .delay (10000,10000,10000) L_0x247a660/d; -L_0x247a740/d .functor NAND 1, L_0x247a340, L_0x247a480, L_0x247a570, L_0x247a660; -L_0x247a740 .delay (10000,10000,10000) L_0x247a740/d; -v0x22b0560_0 .net "S0", 0 0, L_0x2479d30; 1 drivers -v0x22c9c00_0 .net "S1", 0 0, L_0x2479e60; 1 drivers -v0x22c9ca0_0 .net "in0", 0 0, L_0x2479f90; 1 drivers -v0x22c9950_0 .net "in1", 0 0, L_0x247a030; 1 drivers -v0x22c99f0_0 .net "in2", 0 0, L_0x247ae20; 1 drivers -v0x22c96b0_0 .net "in3", 0 0, L_0x247aec0; 1 drivers -v0x22c7dc0_0 .net "nS0", 0 0, L_0x247a1b0; 1 drivers -v0x22c7e60_0 .net "nS1", 0 0, L_0x247a2a0; 1 drivers -v0x22c7b10_0 .net "out", 0 0, L_0x247a740; 1 drivers -v0x22c7bb0_0 .net "out0", 0 0, L_0x247a340; 1 drivers -v0x22cb0d0_0 .net "out1", 0 0, L_0x247a480; 1 drivers -v0x22cb170_0 .net "out2", 0 0, L_0x247a570; 1 drivers -v0x22c7860_0 .net "out3", 0 0, L_0x247a660; 1 drivers -S_0x22b0c60 .scope module, "TwoMux" "TwoInMux" 2 294, 2 8, S_0x22b24b0; - .timescale -9 -12; -L_0x247a9c0/d .functor NOT 1, L_0x247b4c0, C4<0>, C4<0>, C4<0>; -L_0x247a9c0 .delay (10000,10000,10000) L_0x247a9c0/d; -L_0x247aa70/d .functor AND 1, L_0x247afb0, L_0x247a9c0, C4<1>, C4<1>; -L_0x247aa70 .delay (20000,20000,20000) L_0x247aa70/d; -L_0x247ab60/d .functor AND 1, L_0x247b0a0, L_0x247b4c0, C4<1>, C4<1>; -L_0x247ab60 .delay (20000,20000,20000) L_0x247ab60/d; -L_0x247ac50/d .functor OR 1, L_0x247aa70, L_0x247ab60, C4<0>, C4<0>; -L_0x247ac50 .delay (20000,20000,20000) L_0x247ac50/d; -v0x22b09d0_0 .net "S", 0 0, L_0x247b4c0; 1 drivers -v0x22b0a70_0 .net "in0", 0 0, L_0x247afb0; 1 drivers -v0x22b3df0_0 .net "in1", 0 0, L_0x247b0a0; 1 drivers -v0x22b3e90_0 .net "nS", 0 0, L_0x247a9c0; 1 drivers -v0x22b0740_0 .net "out0", 0 0, L_0x247aa70; 1 drivers -v0x22b07e0_0 .net "out1", 0 0, L_0x247ab60; 1 drivers -v0x22b04c0_0 .net "outfinal", 0 0, L_0x247ac50; 1 drivers -S_0x2293b80 .scope generate, "muxbits[8]" "muxbits[8]" 2 290, 2 290, S_0x22690e0; - .timescale -9 -12; -P_0x228bbf8 .param/l "i" 2 290, +C4<01000>; -L_0x24735c0/d .functor OR 1, L_0x247dc00, L_0x2473bf0, C4<0>, C4<0>; -L_0x24735c0 .delay (20000,20000,20000) L_0x24735c0/d; -v0x22b2730_0 .net *"_s15", 0 0, L_0x247dc00; 1 drivers -v0x22b27f0_0 .net *"_s16", 0 0, L_0x2473bf0; 1 drivers -S_0x22ab100 .scope module, "ZeroMux" "FourInMux" 2 292, 2 24, S_0x2293b80; - .timescale -9 -12; -L_0x247baa0/d .functor NOT 1, L_0x247b560, C4<0>, C4<0>, C4<0>; -L_0x247baa0 .delay (10000,10000,10000) L_0x247baa0/d; -L_0x247bb50/d .functor NOT 1, L_0x247b690, C4<0>, C4<0>, C4<0>; -L_0x247bb50 .delay (10000,10000,10000) L_0x247bb50/d; -L_0x247bbf0/d .functor NAND 1, L_0x247baa0, L_0x247bb50, L_0x247b7c0, C4<1>; -L_0x247bbf0 .delay (10000,10000,10000) L_0x247bbf0/d; -L_0x247bd30/d .functor NAND 1, L_0x247b560, L_0x247bb50, L_0x247b860, C4<1>; -L_0x247bd30 .delay (10000,10000,10000) L_0x247bd30/d; -L_0x247be20/d .functor NAND 1, L_0x247baa0, L_0x247b690, L_0x247b900, C4<1>; -L_0x247be20 .delay (10000,10000,10000) L_0x247be20/d; -L_0x247bf10/d .functor NAND 1, L_0x247b560, L_0x247b690, L_0x247c740, C4<1>; -L_0x247bf10 .delay (10000,10000,10000) L_0x247bf10/d; -L_0x247bff0/d .functor NAND 1, L_0x247bbf0, L_0x247bd30, L_0x247be20, L_0x247bf10; -L_0x247bff0 .delay (10000,10000,10000) L_0x247bff0/d; -v0x22ac9f0_0 .net "S0", 0 0, L_0x247b560; 1 drivers -v0x22aae70_0 .net "S1", 0 0, L_0x247b690; 1 drivers -v0x22aaf10_0 .net "in0", 0 0, L_0x247b7c0; 1 drivers -v0x22ae290_0 .net "in1", 0 0, L_0x247b860; 1 drivers -v0x22ae330_0 .net "in2", 0 0, L_0x247b900; 1 drivers -v0x22aabe0_0 .net "in3", 0 0, L_0x247c740; 1 drivers -v0x22aac80_0 .net "nS0", 0 0, L_0x247baa0; 1 drivers -v0x22aa960_0 .net "nS1", 0 0, L_0x247bb50; 1 drivers -v0x22aaa00_0 .net "out", 0 0, L_0x247bff0; 1 drivers -v0x22b2c50_0 .net "out0", 0 0, L_0x247bbf0; 1 drivers -v0x22b2cf0_0 .net "out1", 0 0, L_0x247bd30; 1 drivers -v0x22b29c0_0 .net "out2", 0 0, L_0x247be20; 1 drivers -v0x22b2a60_0 .net "out3", 0 0, L_0x247bf10; 1 drivers -S_0x22a55a0 .scope module, "OneMux" "FourInMux" 2 293, 2 24, S_0x2293b80; - .timescale -9 -12; -L_0x247c270/d .functor NOT 1, L_0x247d070, C4<0>, C4<0>, C4<0>; -L_0x247c270 .delay (10000,10000,10000) L_0x247c270/d; -L_0x247c360/d .functor NOT 1, L_0x247c830, C4<0>, C4<0>, C4<0>; -L_0x247c360 .delay (10000,10000,10000) L_0x247c360/d; -L_0x247c400/d .functor NAND 1, L_0x247c270, L_0x247c360, L_0x247c960, C4<1>; -L_0x247c400 .delay (10000,10000,10000) L_0x247c400/d; -L_0x247c540/d .functor NAND 1, L_0x247d070, L_0x247c360, L_0x247cc10, C4<1>; -L_0x247c540 .delay (10000,10000,10000) L_0x247c540/d; -L_0x247c630/d .functor NAND 1, L_0x247c270, L_0x247c830, L_0x2472d50, C4<1>; -L_0x247c630 .delay (10000,10000,10000) L_0x247c630/d; -L_0x247cd10/d .functor NAND 1, L_0x247d070, L_0x247c830, L_0x247d6b0, C4<1>; -L_0x247cd10 .delay (10000,10000,10000) L_0x247cd10/d; -L_0x247cdf0/d .functor NAND 1, L_0x247c400, L_0x247c540, L_0x247c630, L_0x247cd10; -L_0x247cdf0 .delay (10000,10000,10000) L_0x247cdf0/d; -v0x22a6e90_0 .net "S0", 0 0, L_0x247d070; 1 drivers -v0x22a5310_0 .net "S1", 0 0, L_0x247c830; 1 drivers -v0x22a53b0_0 .net "in0", 0 0, L_0x247c960; 1 drivers -v0x22a8730_0 .net "in1", 0 0, L_0x247cc10; 1 drivers -v0x22a87d0_0 .net "in2", 0 0, L_0x2472d50; 1 drivers -v0x22a5080_0 .net "in3", 0 0, L_0x247d6b0; 1 drivers -v0x22ad0f0_0 .net "nS0", 0 0, L_0x247c270; 1 drivers -v0x22ad190_0 .net "nS1", 0 0, L_0x247c360; 1 drivers -v0x22ace60_0 .net "out", 0 0, L_0x247cdf0; 1 drivers -v0x22acf00_0 .net "out0", 0 0, L_0x247c400; 1 drivers -v0x22acbd0_0 .net "out1", 0 0, L_0x247c540; 1 drivers -v0x22acc70_0 .net "out2", 0 0, L_0x247c630; 1 drivers -v0x22ac950_0 .net "out3", 0 0, L_0x247cd10; 1 drivers -S_0x2293900 .scope module, "TwoMux" "TwoInMux" 2 294, 2 8, S_0x2293b80; - .timescale -9 -12; -L_0x247d750/d .functor NOT 1, L_0x247d1a0, C4<0>, C4<0>, C4<0>; -L_0x247d750 .delay (10000,10000,10000) L_0x247d750/d; -L_0x247d840/d .functor AND 1, L_0x247d240, L_0x247d750, C4<1>, C4<1>; -L_0x247d840 .delay (20000,20000,20000) L_0x247d840/d; -L_0x247d930/d .functor AND 1, L_0x24737a0, L_0x247d1a0, C4<1>, C4<1>; -L_0x247d930 .delay (20000,20000,20000) L_0x247d930/d; -L_0x247da20/d .functor OR 1, L_0x247d840, L_0x247d930, C4<0>, C4<0>; -L_0x247da20 .delay (20000,20000,20000) L_0x247da20/d; -v0x2293e90_0 .net "S", 0 0, L_0x247d1a0; 1 drivers -v0x22a7590_0 .net "in0", 0 0, L_0x247d240; 1 drivers -v0x22a7630_0 .net "in1", 0 0, L_0x24737a0; 1 drivers -v0x22a7300_0 .net "nS", 0 0, L_0x247d750; 1 drivers -v0x22a7380_0 .net "out0", 0 0, L_0x247d840; 1 drivers -v0x22a7070_0 .net "out1", 0 0, L_0x247d930; 1 drivers -v0x22a6df0_0 .net "outfinal", 0 0, L_0x247da20; 1 drivers -S_0x2271240 .scope generate, "muxbits[9]" "muxbits[9]" 2 290, 2 290, S_0x22690e0; - .timescale -9 -12; -P_0x226d758 .param/l "i" 2 290, +C4<01001>; -L_0x247fef0/d .functor OR 1, L_0x2480030, L_0x24800d0, C4<0>, C4<0>; -L_0x247fef0 .delay (20000,20000,20000) L_0x247fef0/d; -v0x2294140_0 .net *"_s15", 0 0, L_0x2480030; 1 drivers -v0x2293e10_0 .net *"_s16", 0 0, L_0x24800d0; 1 drivers -S_0x2290010 .scope module, "ZeroMux" "FourInMux" 2 292, 2 24, S_0x2271240; - .timescale -9 -12; -L_0x247e0c0/d .functor NOT 1, L_0x247eeb0, C4<0>, C4<0>, C4<0>; -L_0x247e0c0 .delay (10000,10000,10000) L_0x247e0c0/d; -L_0x2473da0/d .functor NOT 1, L_0x247e340, C4<0>, C4<0>, C4<0>; -L_0x2473da0 .delay (10000,10000,10000) L_0x2473da0/d; -L_0x2473e40/d .functor NAND 1, L_0x247e0c0, L_0x2473da0, L_0x247e470, C4<1>; -L_0x2473e40 .delay (10000,10000,10000) L_0x2473e40/d; -L_0x247e970/d .functor NAND 1, L_0x247eeb0, L_0x2473da0, L_0x247e510, C4<1>; -L_0x247e970 .delay (10000,10000,10000) L_0x247e970/d; -L_0x247ea60/d .functor NAND 1, L_0x247e0c0, L_0x247e340, L_0x247e5b0, C4<1>; -L_0x247ea60 .delay (10000,10000,10000) L_0x247ea60/d; -L_0x247eb50/d .functor NAND 1, L_0x247eeb0, L_0x247e340, L_0x247e6a0, C4<1>; -L_0x247eb50 .delay (10000,10000,10000) L_0x247eb50/d; -L_0x247ec30/d .functor NAND 1, L_0x2473e40, L_0x247e970, L_0x247ea60, L_0x247eb50; -L_0x247ec30 .delay (10000,10000,10000) L_0x247ec30/d; -v0x2290340_0 .net "S0", 0 0, L_0x247eeb0; 1 drivers -v0x228fd90_0 .net "S1", 0 0, L_0x247e340; 1 drivers -v0x228fe30_0 .net "in0", 0 0, L_0x247e470; 1 drivers -v0x228e540_0 .net "in1", 0 0, L_0x247e510; 1 drivers -v0x228e5e0_0 .net "in2", 0 0, L_0x247e5b0; 1 drivers -v0x228e2b0_0 .net "in3", 0 0, L_0x247e6a0; 1 drivers -v0x228e350_0 .net "nS0", 0 0, L_0x247e0c0; 1 drivers -v0x22916d0_0 .net "nS1", 0 0, L_0x2473da0; 1 drivers -v0x2291770_0 .net "out", 0 0, L_0x247ec30; 1 drivers -v0x228e020_0 .net "out0", 0 0, L_0x2473e40; 1 drivers -v0x228e0c0_0 .net "out1", 0 0, L_0x247e970; 1 drivers -v0x228dda0_0 .net "out2", 0 0, L_0x247ea60; 1 drivers -v0x22940a0_0 .net "out3", 0 0, L_0x247eb50; 1 drivers -S_0x228a230 .scope module, "OneMux" "FourInMux" 2 293, 2 24, S_0x2271240; - .timescale -9 -12; -L_0x247e790/d .functor NOT 1, L_0x247efe0, C4<0>, C4<0>, C4<0>; -L_0x247e790 .delay (10000,10000,10000) L_0x247e790/d; -L_0x247e830/d .functor NOT 1, L_0x247f110, C4<0>, C4<0>, C4<0>; -L_0x247e830 .delay (10000,10000,10000) L_0x247e830/d; -L_0x247f5f0/d .functor NAND 1, L_0x247e790, L_0x247e830, L_0x247f240, C4<1>; -L_0x247f5f0 .delay (10000,10000,10000) L_0x247f5f0/d; -L_0x247f730/d .functor NAND 1, L_0x247efe0, L_0x247e830, L_0x247f2e0, C4<1>; -L_0x247f730 .delay (10000,10000,10000) L_0x247f730/d; -L_0x247f820/d .functor NAND 1, L_0x247e790, L_0x247f110, L_0x247f380, C4<1>; -L_0x247f820 .delay (10000,10000,10000) L_0x247f820/d; -L_0x247f910/d .functor NAND 1, L_0x247efe0, L_0x247f110, L_0x247f470, C4<1>; -L_0x247f910 .delay (10000,10000,10000) L_0x247f910/d; -L_0x247f9f0/d .functor NAND 1, L_0x247f5f0, L_0x247f730, L_0x247f820, L_0x247f910; -L_0x247f9f0 .delay (10000,10000,10000) L_0x247f9f0/d; -v0x228a550_0 .net "S0", 0 0, L_0x247efe0; 1 drivers -v0x22889e0_0 .net "S1", 0 0, L_0x247f110; 1 drivers -v0x2288a80_0 .net "in0", 0 0, L_0x247f240; 1 drivers -v0x2288750_0 .net "in1", 0 0, L_0x247f2e0; 1 drivers -v0x22887f0_0 .net "in2", 0 0, L_0x247f380; 1 drivers -v0x228bb70_0 .net "in3", 0 0, L_0x247f470; 1 drivers -v0x22884c0_0 .net "nS0", 0 0, L_0x247e790; 1 drivers -v0x2288560_0 .net "nS1", 0 0, L_0x247e830; 1 drivers -v0x2288240_0 .net "out", 0 0, L_0x247f9f0; 1 drivers -v0x22882e0_0 .net "out0", 0 0, L_0x247f5f0; 1 drivers -v0x2290530_0 .net "out1", 0 0, L_0x247f730; 1 drivers -v0x22905d0_0 .net "out2", 0 0, L_0x247f820; 1 drivers -v0x22902a0_0 .net "out3", 0 0, L_0x247f910; 1 drivers -S_0x2284e70 .scope module, "TwoMux" "TwoInMux" 2 294, 2 8, S_0x2271240; - .timescale -9 -12; -L_0x2480230/d .functor NOT 1, L_0x24806e0, C4<0>, C4<0>, C4<0>; -L_0x2480230 .delay (10000,10000,10000) L_0x2480230/d; -L_0x2480320/d .functor AND 1, L_0x247fc70, L_0x2480230, C4<1>, C4<1>; -L_0x2480320 .delay (20000,20000,20000) L_0x2480320/d; -L_0x2480410/d .functor AND 1, L_0x247fd60, L_0x24806e0, C4<1>, C4<1>; -L_0x2480410 .delay (20000,20000,20000) L_0x2480410/d; -L_0x2480500/d .functor OR 1, L_0x2480320, L_0x2480410, C4<0>, C4<0>; -L_0x2480500 .delay (20000,20000,20000) L_0x2480500/d; -v0x2286010_0 .net "S", 0 0, L_0x24806e0; 1 drivers -v0x22860b0_0 .net "in0", 0 0, L_0x247fc70; 1 drivers -v0x228a9d0_0 .net "in1", 0 0, L_0x247fd60; 1 drivers -v0x228aa70_0 .net "nS", 0 0, L_0x2480230; 1 drivers -v0x228a740_0 .net "out0", 0 0, L_0x2480320; 1 drivers -v0x228a7e0_0 .net "out1", 0 0, L_0x2480410; 1 drivers -v0x228a4b0_0 .net "outfinal", 0 0, L_0x2480500; 1 drivers -S_0x2267b70 .scope generate, "muxbits[10]" "muxbits[10]" 2 290, 2 290, S_0x22690e0; - .timescale -9 -12; -P_0x2353df8 .param/l "i" 2 290, +C4<01010>; -L_0x2482750/d .functor OR 1, L_0x2482890, L_0x2482930, C4<0>, C4<0>; -L_0x2482750 .delay (20000,20000,20000) L_0x2482750/d; -v0x22714c0_0 .net *"_s15", 0 0, L_0x2482890; 1 drivers -v0x2271580_0 .net *"_s16", 0 0, L_0x2482930; 1 drivers -S_0x226b6e0 .scope module, "ZeroMux" "FourInMux" 2 292, 2 24, S_0x2267b70; - .timescale -9 -12; -L_0x24801c0/d .functor NOT 1, L_0x2480780, C4<0>, C4<0>, C4<0>; -L_0x24801c0 .delay (10000,10000,10000) L_0x24801c0/d; -L_0x2480e00/d .functor NOT 1, L_0x24808b0, C4<0>, C4<0>, C4<0>; -L_0x2480e00 .delay (10000,10000,10000) L_0x2480e00/d; -L_0x2480ea0/d .functor NAND 1, L_0x24801c0, L_0x2480e00, L_0x24809e0, C4<1>; -L_0x2480ea0 .delay (10000,10000,10000) L_0x2480ea0/d; -L_0x2480fe0/d .functor NAND 1, L_0x2480780, L_0x2480e00, L_0x2480a80, C4<1>; -L_0x2480fe0 .delay (10000,10000,10000) L_0x2480fe0/d; -L_0x24810d0/d .functor NAND 1, L_0x24801c0, L_0x24808b0, L_0x2480b20, C4<1>; -L_0x24810d0 .delay (10000,10000,10000) L_0x24810d0/d; -L_0x24811c0/d .functor NAND 1, L_0x2480780, L_0x24808b0, L_0x2480c10, C4<1>; -L_0x24811c0 .delay (10000,10000,10000) L_0x24811c0/d; -L_0x24812a0/d .functor NAND 1, L_0x2480ea0, L_0x2480fe0, L_0x24810d0, L_0x24811c0; -L_0x24812a0 .delay (10000,10000,10000) L_0x24812a0/d; -v0x226ba00_0 .net "S0", 0 0, L_0x2480780; 1 drivers -v0x22739d0_0 .net "S1", 0 0, L_0x24808b0; 1 drivers -v0x2273a70_0 .net "in0", 0 0, L_0x24809e0; 1 drivers -v0x2273740_0 .net "in1", 0 0, L_0x2480a80; 1 drivers -v0x22737e0_0 .net "in2", 0 0, L_0x2480b20; 1 drivers -v0x22734b0_0 .net "in3", 0 0, L_0x2480c10; 1 drivers -v0x2273550_0 .net "nS0", 0 0, L_0x24801c0; 1 drivers -v0x2273230_0 .net "nS1", 0 0, L_0x2480e00; 1 drivers -v0x22732d0_0 .net "out", 0 0, L_0x24812a0; 1 drivers -v0x22719e0_0 .net "out0", 0 0, L_0x2480ea0; 1 drivers -v0x2271a80_0 .net "out1", 0 0, L_0x2480fe0; 1 drivers -v0x2271750_0 .net "out2", 0 0, L_0x24810d0; 1 drivers -v0x22717f0_0 .net "out3", 0 0, L_0x24811c0; 1 drivers -S_0x226de70 .scope module, "OneMux" "FourInMux" 2 293, 2 24, S_0x2267b70; - .timescale -9 -12; -L_0x2480d00/d .functor NOT 1, L_0x2482300, C4<0>, C4<0>, C4<0>; -L_0x2480d00 .delay (10000,10000,10000) L_0x2480d00/d; -L_0x2481be0/d .functor NOT 1, L_0x2481520, C4<0>, C4<0>, C4<0>; -L_0x2481be0 .delay (10000,10000,10000) L_0x2481be0/d; -L_0x2481c80/d .functor NAND 1, L_0x2480d00, L_0x2481be0, L_0x2481650, C4<1>; -L_0x2481c80 .delay (10000,10000,10000) L_0x2481c80/d; -L_0x2481dc0/d .functor NAND 1, L_0x2482300, L_0x2481be0, L_0x24816f0, C4<1>; -L_0x2481dc0 .delay (10000,10000,10000) L_0x2481dc0/d; -L_0x2481eb0/d .functor NAND 1, L_0x2480d00, L_0x2481520, L_0x2481790, C4<1>; -L_0x2481eb0 .delay (10000,10000,10000) L_0x2481eb0/d; -L_0x2481fa0/d .functor NAND 1, L_0x2482300, L_0x2481520, L_0x2481880, C4<1>; -L_0x2481fa0 .delay (10000,10000,10000) L_0x2481fa0/d; -L_0x2482080/d .functor NAND 1, L_0x2481c80, L_0x2481dc0, L_0x2481eb0, L_0x2481fa0; -L_0x2482080 .delay (10000,10000,10000) L_0x2482080/d; -v0x2265c20_0 .net "S0", 0 0, L_0x2482300; 1 drivers -v0x226dbe0_0 .net "S1", 0 0, L_0x2481520; 1 drivers -v0x226dc80_0 .net "in0", 0 0, L_0x2481650; 1 drivers -v0x226d950_0 .net "in1", 0 0, L_0x24816f0; 1 drivers -v0x226d9f0_0 .net "in2", 0 0, L_0x2481790; 1 drivers -v0x226d6d0_0 .net "in3", 0 0, L_0x2481880; 1 drivers -v0x226be80_0 .net "nS0", 0 0, L_0x2480d00; 1 drivers -v0x226bf20_0 .net "nS1", 0 0, L_0x2481be0; 1 drivers -v0x226bbf0_0 .net "out", 0 0, L_0x2482080; 1 drivers -v0x226bc90_0 .net "out0", 0 0, L_0x2481c80; 1 drivers -v0x226f010_0 .net "out1", 0 0, L_0x2481dc0; 1 drivers -v0x226f0b0_0 .net "out2", 0 0, L_0x2481eb0; 1 drivers -v0x226b960_0 .net "out3", 0 0, L_0x2481fa0; 1 drivers -S_0x2266320 .scope module, "TwoMux" "TwoInMux" 2 294, 2 8, S_0x2267b70; - .timescale -9 -12; -L_0x2481970/d .functor NOT 1, L_0x2482430, C4<0>, C4<0>, C4<0>; -L_0x2481970 .delay (10000,10000,10000) L_0x2481970/d; -L_0x2481a60/d .functor AND 1, L_0x24824d0, L_0x2481970, C4<1>, C4<1>; -L_0x2481a60 .delay (20000,20000,20000) L_0x2481a60/d; -L_0x2482a90/d .functor AND 1, L_0x24825c0, L_0x2482430, C4<1>, C4<1>; -L_0x2482a90 .delay (20000,20000,20000) L_0x2482a90/d; -L_0x2482b80/d .functor OR 1, L_0x2481a60, L_0x2482a90, C4<0>, C4<0>; -L_0x2482b80 .delay (20000,20000,20000) L_0x2482b80/d; -v0x2267e70_0 .net "S", 0 0, L_0x2482430; 1 drivers -v0x2266090_0 .net "in0", 0 0, L_0x24824d0; 1 drivers -v0x2266130_0 .net "in1", 0 0, L_0x24825c0; 1 drivers -v0x22694b0_0 .net "nS", 0 0, L_0x2481970; 1 drivers -v0x2269530_0 .net "out0", 0 0, L_0x2481a60; 1 drivers -v0x2265e00_0 .net "out1", 0 0, L_0x2482a90; 1 drivers -v0x2265b80_0 .net "outfinal", 0 0, L_0x2482b80; 1 drivers -S_0x2278880 .scope generate, "muxbits[11]" "muxbits[11]" 2 290, 2 290, S_0x22690e0; - .timescale -9 -12; -P_0x23e1ea8 .param/l "i" 2 290, +C4<01011>; -L_0x24852d0/d .functor OR 1, L_0x2485410, L_0x24854b0, C4<0>, C4<0>; -L_0x24852d0 .delay (20000,20000,20000) L_0x24852d0/d; -v0x2268120_0 .net *"_s15", 0 0, L_0x2485410; 1 drivers -v0x2267df0_0 .net *"_s16", 0 0, L_0x24854b0; 1 drivers -S_0x23149a0 .scope module, "ZeroMux" "FourInMux" 2 292, 2 24, S_0x2278880; - .timescale -9 -12; -L_0x2482a20/d .functor NOT 1, L_0x2483bb0, C4<0>, C4<0>, C4<0>; -L_0x2482a20 .delay (10000,10000,10000) L_0x2482a20/d; -L_0x2483490/d .functor NOT 1, L_0x2482d60, C4<0>, C4<0>, C4<0>; -L_0x2483490 .delay (10000,10000,10000) L_0x2483490/d; -L_0x2483530/d .functor NAND 1, L_0x2482a20, L_0x2483490, L_0x2482e90, C4<1>; -L_0x2483530 .delay (10000,10000,10000) L_0x2483530/d; -L_0x2483670/d .functor NAND 1, L_0x2483bb0, L_0x2483490, L_0x2483340, C4<1>; -L_0x2483670 .delay (10000,10000,10000) L_0x2483670/d; -L_0x2483760/d .functor NAND 1, L_0x2482a20, L_0x2482d60, L_0x2474d80, C4<1>; -L_0x2483760 .delay (10000,10000,10000) L_0x2483760/d; -L_0x2483850/d .functor NAND 1, L_0x2483bb0, L_0x2482d60, L_0x2474e70, C4<1>; -L_0x2483850 .delay (10000,10000,10000) L_0x2483850/d; -L_0x2483930/d .functor NAND 1, L_0x2483530, L_0x2483670, L_0x2483760, L_0x2483850; -L_0x2483930 .delay (10000,10000,10000) L_0x2483930/d; -v0x2348510_0 .net "S0", 0 0, L_0x2483bb0; 1 drivers -v0x23370b0_0 .net "S1", 0 0, L_0x2482d60; 1 drivers -v0x2337150_0 .net "in0", 0 0, L_0x2482e90; 1 drivers -v0x2334380_0 .net "in1", 0 0, L_0x2483340; 1 drivers -v0x2334420_0 .net "in2", 0 0, L_0x2474d80; 1 drivers -v0x2331540_0 .net "in3", 0 0, L_0x2474e70; 1 drivers -v0x23315e0_0 .net "nS0", 0 0, L_0x2482a20; 1 drivers -v0x230fa00_0 .net "nS1", 0 0, L_0x2483490; 1 drivers -v0x230faa0_0 .net "out", 0 0, L_0x2483930; 1 drivers -v0x236c8e0_0 .net "out0", 0 0, L_0x2483530; 1 drivers -v0x236c980_0 .net "out1", 0 0, L_0x2483670; 1 drivers -v0x2268310_0 .net "out2", 0 0, L_0x2483760; 1 drivers -v0x2268080_0 .net "out3", 0 0, L_0x2483850; 1 drivers -S_0x2328aa0 .scope module, "OneMux" "FourInMux" 2 293, 2 24, S_0x2278880; - .timescale -9 -12; -L_0x2475bc0/d .functor NOT 1, L_0x2484300, C4<0>, C4<0>, C4<0>; -L_0x2475bc0 .delay (10000,10000,10000) L_0x2475bc0/d; -L_0x2475cb0/d .functor NOT 1, L_0x2484f20, C4<0>, C4<0>, C4<0>; -L_0x2475cb0 .delay (10000,10000,10000) L_0x2475cb0/d; -L_0x2475d50/d .functor NAND 1, L_0x2475bc0, L_0x2475cb0, L_0x24847b0, C4<1>; -L_0x2475d50 .delay (10000,10000,10000) L_0x2475d50/d; -L_0x2483dc0/d .functor NAND 1, L_0x2484300, L_0x2475cb0, L_0x2484850, C4<1>; -L_0x2483dc0 .delay (10000,10000,10000) L_0x2483dc0/d; -L_0x2483eb0/d .functor NAND 1, L_0x2475bc0, L_0x2484f20, L_0x24848f0, C4<1>; -L_0x2483eb0 .delay (10000,10000,10000) L_0x2483eb0/d; -L_0x2483fa0/d .functor NAND 1, L_0x2484300, L_0x2484f20, L_0x24849e0, C4<1>; -L_0x2483fa0 .delay (10000,10000,10000) L_0x2483fa0/d; -L_0x2484080/d .functor NAND 1, L_0x2475d50, L_0x2483dc0, L_0x2483eb0, L_0x2483fa0; -L_0x2484080 .delay (10000,10000,10000) L_0x2484080/d; -v0x2311c00_0 .net "S0", 0 0, L_0x2484300; 1 drivers -v0x2367de0_0 .net "S1", 0 0, L_0x2484f20; 1 drivers -v0x2367e80_0 .net "in0", 0 0, L_0x24847b0; 1 drivers -v0x2317690_0 .net "in1", 0 0, L_0x2484850; 1 drivers -v0x2317730_0 .net "in2", 0 0, L_0x24848f0; 1 drivers -v0x2353d70_0 .net "in3", 0 0, L_0x24849e0; 1 drivers -v0x2350f30_0 .net "nS0", 0 0, L_0x2475bc0; 1 drivers -v0x2350fd0_0 .net "nS1", 0 0, L_0x2475cb0; 1 drivers -v0x234e0f0_0 .net "out", 0 0, L_0x2484080; 1 drivers -v0x234e190_0 .net "out0", 0 0, L_0x2475d50; 1 drivers -v0x234b2b0_0 .net "out1", 0 0, L_0x2483dc0; 1 drivers -v0x234b350_0 .net "out2", 0 0, L_0x2483eb0; 1 drivers -v0x2348470_0 .net "out3", 0 0, L_0x2483fa0; 1 drivers -S_0x2276840 .scope module, "TwoMux" "TwoInMux" 2 294, 2 8, S_0x2278880; - .timescale -9 -12; -L_0x2484ad0/d .functor NOT 1, L_0x2485850, C4<0>, C4<0>, C4<0>; -L_0x2484ad0 .delay (10000,10000,10000) L_0x2484ad0/d; -L_0x2484bc0/d .functor AND 1, L_0x2485050, L_0x2484ad0, C4<1>, C4<1>; -L_0x2484bc0 .delay (20000,20000,20000) L_0x2484bc0/d; -L_0x2484cb0/d .functor AND 1, L_0x2485140, L_0x2485850, C4<1>, C4<1>; -L_0x2484cb0 .delay (20000,20000,20000) L_0x2484cb0/d; -L_0x2484da0/d .functor OR 1, L_0x2484bc0, L_0x2484cb0, C4<0>, C4<0>; -L_0x2484da0 .delay (20000,20000,20000) L_0x2484da0/d; -v0x2259bc0_0 .net "S", 0 0, L_0x2485850; 1 drivers -v0x2259c60_0 .net "in0", 0 0, L_0x2485050; 1 drivers -v0x232e700_0 .net "in1", 0 0, L_0x2485140; 1 drivers -v0x232e7a0_0 .net "nS", 0 0, L_0x2484ad0; 1 drivers -v0x232b8c0_0 .net "out0", 0 0, L_0x2484bc0; 1 drivers -v0x232b960_0 .net "out1", 0 0, L_0x2484cb0; 1 drivers -v0x2311b60_0 .net "outfinal", 0 0, L_0x2484da0; 1 drivers -S_0x22e09f0 .scope generate, "muxbits[12]" "muxbits[12]" 2 290, 2 290, S_0x22690e0; - .timescale -9 -12; -P_0x23e3978 .param/l "i" 2 290, +C4<01100>; -L_0x2487900/d .functor OR 1, L_0x2487a40, L_0x2487ae0, C4<0>, C4<0>; -L_0x2487900 .delay (20000,20000,20000) L_0x2487900/d; -v0x227c490_0 .net *"_s15", 0 0, L_0x2487a40; 1 drivers -v0x227c550_0 .net *"_s16", 0 0, L_0x2487ae0; 1 drivers -S_0x229ebf0 .scope module, "ZeroMux" "FourInMux" 2 292, 2 24, S_0x22e09f0; - .timescale -9 -12; -L_0x24855a0/d .functor NOT 1, L_0x24858f0, C4<0>, C4<0>, C4<0>; -L_0x24855a0 .delay (10000,10000,10000) L_0x24855a0/d; -L_0x2485690/d .functor NOT 1, L_0x2485a20, C4<0>, C4<0>, C4<0>; -L_0x2485690 .delay (10000,10000,10000) L_0x2485690/d; -L_0x2486030/d .functor NAND 1, L_0x24855a0, L_0x2485690, L_0x2485b50, C4<1>; -L_0x2486030 .delay (10000,10000,10000) L_0x2486030/d; -L_0x2486170/d .functor NAND 1, L_0x24858f0, L_0x2485690, L_0x2485bf0, C4<1>; -L_0x2486170 .delay (10000,10000,10000) L_0x2486170/d; -L_0x2486260/d .functor NAND 1, L_0x24855a0, L_0x2485a20, L_0x2485c90, C4<1>; -L_0x2486260 .delay (10000,10000,10000) L_0x2486260/d; -L_0x2486350/d .functor NAND 1, L_0x24858f0, L_0x2485a20, L_0x2485d80, C4<1>; -L_0x2486350 .delay (10000,10000,10000) L_0x2486350/d; -L_0x2486430/d .functor NAND 1, L_0x2486030, L_0x2486170, L_0x2486260, L_0x2486350; -L_0x2486430 .delay (10000,10000,10000) L_0x2486430/d; -v0x229afe0_0 .net "S0", 0 0, L_0x24858f0; 1 drivers -v0x229b0a0_0 .net "S1", 0 0, L_0x2485a20; 1 drivers -v0x2298fa0_0 .net "in0", 0 0, L_0x2485b50; 1 drivers -v0x2299040_0 .net "in1", 0 0, L_0x2485bf0; 1 drivers -v0x2295390_0 .net "in2", 0 0, L_0x2485c90; 1 drivers -v0x2295430_0 .net "in3", 0 0, L_0x2485d80; 1 drivers -v0x225f9d0_0 .net "nS0", 0 0, L_0x24855a0; 1 drivers -v0x225fa70_0 .net "nS1", 0 0, L_0x2485690; 1 drivers -v0x2284120_0 .net "out", 0 0, L_0x2486430; 1 drivers -v0x22841c0_0 .net "out0", 0 0, L_0x2486030; 1 drivers -v0x22820e0_0 .net "out1", 0 0, L_0x2486170; 1 drivers -v0x2282180_0 .net "out2", 0 0, L_0x2486260; 1 drivers -v0x227e560_0 .net "out3", 0 0, L_0x2486350; 1 drivers -S_0x22c1360 .scope module, "OneMux" "FourInMux" 2 293, 2 24, S_0x22e09f0; - .timescale -9 -12; -L_0x2485e70/d .functor NOT 1, L_0x24874b0, C4<0>, C4<0>, C4<0>; -L_0x2485e70 .delay (10000,10000,10000) L_0x2485e70/d; -L_0x2485f60/d .functor NOT 1, L_0x24866b0, C4<0>, C4<0>, C4<0>; -L_0x2485f60 .delay (10000,10000,10000) L_0x2485f60/d; -L_0x2486e30/d .functor NAND 1, L_0x2485e70, L_0x2485f60, L_0x24867e0, C4<1>; -L_0x2486e30 .delay (10000,10000,10000) L_0x2486e30/d; -L_0x2486f70/d .functor NAND 1, L_0x24874b0, L_0x2485f60, L_0x2486880, C4<1>; -L_0x2486f70 .delay (10000,10000,10000) L_0x2486f70/d; -L_0x2487060/d .functor NAND 1, L_0x2485e70, L_0x24866b0, L_0x2486920, C4<1>; -L_0x2487060 .delay (10000,10000,10000) L_0x2487060/d; -L_0x2487150/d .functor NAND 1, L_0x24874b0, L_0x24866b0, L_0x2486a10, C4<1>; -L_0x2487150 .delay (10000,10000,10000) L_0x2487150/d; -L_0x2487230/d .functor NAND 1, L_0x2486e30, L_0x2486f70, L_0x2487060, L_0x2487150; -L_0x2487230 .delay (10000,10000,10000) L_0x2487230/d; -v0x22bd750_0 .net "S0", 0 0, L_0x24874b0; 1 drivers -v0x22bd810_0 .net "S1", 0 0, L_0x24866b0; 1 drivers -v0x22bb710_0 .net "in0", 0 0, L_0x24867e0; 1 drivers -v0x22bb7b0_0 .net "in1", 0 0, L_0x2486880; 1 drivers -v0x22b7b00_0 .net "in2", 0 0, L_0x2486920; 1 drivers -v0x22b7ba0_0 .net "in3", 0 0, L_0x2486a10; 1 drivers -v0x22b5ac0_0 .net "nS0", 0 0, L_0x2485e70; 1 drivers -v0x22b5b60_0 .net "nS1", 0 0, L_0x2485f60; 1 drivers -v0x2261a10_0 .net "out", 0 0, L_0x2487230; 1 drivers -v0x2261ab0_0 .net "out0", 0 0, L_0x2486e30; 1 drivers -v0x22a4840_0 .net "out1", 0 0, L_0x2486f70; 1 drivers -v0x22a48e0_0 .net "out2", 0 0, L_0x2487060; 1 drivers -v0x22a0cc0_0 .net "out3", 0 0, L_0x2487150; 1 drivers -S_0x22de920 .scope module, "TwoMux" "TwoInMux" 2 294, 2 8, S_0x22e09f0; - .timescale -9 -12; -L_0x2486b00/d .functor NOT 1, L_0x24875e0, C4<0>, C4<0>, C4<0>; -L_0x2486b00 .delay (10000,10000,10000) L_0x2486b00/d; -L_0x2486bf0/d .functor AND 1, L_0x2487680, L_0x2486b00, C4<1>, C4<1>; -L_0x2486bf0 .delay (20000,20000,20000) L_0x2486bf0/d; -L_0x2486ce0/d .functor AND 1, L_0x2487770, L_0x24875e0, C4<1>, C4<1>; -L_0x2486ce0 .delay (20000,20000,20000) L_0x2486ce0/d; -L_0x2486dd0/d .functor OR 1, L_0x2486bf0, L_0x2486ce0, C4<0>, C4<0>; -L_0x2486dd0 .delay (20000,20000,20000) L_0x2486dd0/d; -v0x22e4800_0 .net "S", 0 0, L_0x24875e0; 1 drivers -v0x22dab90_0 .net "in0", 0 0, L_0x2487680; 1 drivers -v0x22dac30_0 .net "in1", 0 0, L_0x2487770; 1 drivers -v0x22d8ac0_0 .net "nS", 0 0, L_0x2486b00; 1 drivers -v0x22d8b40_0 .net "out0", 0 0, L_0x2486bf0; 1 drivers -v0x22c33a0_0 .net "out1", 0 0, L_0x2486ce0; 1 drivers -v0x22c3440_0 .net "outfinal", 0 0, L_0x2486dd0; 1 drivers -S_0x2111ab0 .scope generate, "muxbits[13]" "muxbits[13]" 2 290, 2 290, S_0x22690e0; - .timescale -9 -12; -P_0x23031a8 .param/l "i" 2 290, +C4<01101>; -L_0x2489e70/d .functor OR 1, L_0x2489fb0, L_0x248a050, C4<0>, C4<0>; -L_0x2489e70 .delay (20000,20000,20000) L_0x2489e70/d; -v0x22e68f0_0 .net *"_s15", 0 0, L_0x2489fb0; 1 drivers -v0x22e4780_0 .net *"_s16", 0 0, L_0x248a050; 1 drivers -S_0x23e1db0 .scope module, "ZeroMux" "FourInMux" 2 292, 2 24, S_0x2111ab0; - .timescale -9 -12; -L_0x2487bd0/d .functor NOT 1, L_0x2488dc0, C4<0>, C4<0>, C4<0>; -L_0x2487bd0 .delay (10000,10000,10000) L_0x2487bd0/d; -L_0x2487d20/d .functor NOT 1, L_0x2487f10, C4<0>, C4<0>, C4<0>; -L_0x2487d20 .delay (10000,10000,10000) L_0x2487d20/d; -L_0x2488740/d .functor NAND 1, L_0x2487bd0, L_0x2487d20, L_0x2488040, C4<1>; -L_0x2488740 .delay (10000,10000,10000) L_0x2488740/d; -L_0x2488880/d .functor NAND 1, L_0x2488dc0, L_0x2487d20, L_0x24880e0, C4<1>; -L_0x2488880 .delay (10000,10000,10000) L_0x2488880/d; -L_0x2488970/d .functor NAND 1, L_0x2487bd0, L_0x2487f10, L_0x2488180, C4<1>; -L_0x2488970 .delay (10000,10000,10000) L_0x2488970/d; -L_0x2488a60/d .functor NAND 1, L_0x2488dc0, L_0x2487f10, L_0x2488270, C4<1>; -L_0x2488a60 .delay (10000,10000,10000) L_0x2488a60/d; -L_0x2488b40/d .functor NAND 1, L_0x2488740, L_0x2488880, L_0x2488970, L_0x2488a60; -L_0x2488b40 .delay (10000,10000,10000) L_0x2488b40/d; -v0x23e2150_0 .net "S0", 0 0, L_0x2488dc0; 1 drivers -v0x23e1830_0 .net "S1", 0 0, L_0x2487f10; 1 drivers -v0x23e18d0_0 .net "in0", 0 0, L_0x2488040; 1 drivers -v0x2303f70_0 .net "in1", 0 0, L_0x24880e0; 1 drivers -v0x2304010_0 .net "in2", 0 0, L_0x2488180; 1 drivers -v0x2301ea0_0 .net "in3", 0 0, L_0x2488270; 1 drivers -v0x2301f40_0 .net "nS0", 0 0, L_0x2487bd0; 1 drivers -v0x22fe110_0 .net "nS1", 0 0, L_0x2487d20; 1 drivers -v0x22fe1b0_0 .net "out", 0 0, L_0x2488b40; 1 drivers -v0x22fc040_0 .net "out0", 0 0, L_0x2488740; 1 drivers -v0x22fc0e0_0 .net "out1", 0 0, L_0x2488880; 1 drivers -v0x22f82b0_0 .net "out2", 0 0, L_0x2488970; 1 drivers -v0x22e6850_0 .net "out3", 0 0, L_0x2488a60; 1 drivers -S_0x23e4410 .scope module, "OneMux" "FourInMux" 2 293, 2 24, S_0x2111ab0; - .timescale -9 -12; -L_0x2488360/d .functor NOT 1, L_0x2488ef0, C4<0>, C4<0>, C4<0>; -L_0x2488360 .delay (10000,10000,10000) L_0x2488360/d; -L_0x2488450/d .functor NOT 1, L_0x2489020, C4<0>, C4<0>, C4<0>; -L_0x2488450 .delay (10000,10000,10000) L_0x2488450/d; -L_0x2488510/d .functor NAND 1, L_0x2488360, L_0x2488450, L_0x2489150, C4<1>; -L_0x2488510 .delay (10000,10000,10000) L_0x2488510/d; -L_0x2488670/d .functor NAND 1, L_0x2488ef0, L_0x2488450, L_0x24891f0, C4<1>; -L_0x2488670 .delay (10000,10000,10000) L_0x2488670/d; -L_0x24897a0/d .functor NAND 1, L_0x2488360, L_0x2489020, L_0x2489290, C4<1>; -L_0x24897a0 .delay (10000,10000,10000) L_0x24897a0/d; -L_0x2489890/d .functor NAND 1, L_0x2488ef0, L_0x2489020, L_0x2489380, C4<1>; -L_0x2489890 .delay (10000,10000,10000) L_0x2489890/d; -L_0x2489970/d .functor NAND 1, L_0x2488510, L_0x2488670, L_0x24897a0, L_0x2489890; -L_0x2489970 .delay (10000,10000,10000) L_0x2489970/d; -v0x23e4750_0 .net "S0", 0 0, L_0x2488ef0; 1 drivers -v0x23e4170_0 .net "S1", 0 0, L_0x2489020; 1 drivers -v0x23e4210_0 .net "in0", 0 0, L_0x2489150; 1 drivers -v0x23e3e70_0 .net "in1", 0 0, L_0x24891f0; 1 drivers -v0x23e3f10_0 .net "in2", 0 0, L_0x2489290; 1 drivers -v0x23e38f0_0 .net "in3", 0 0, L_0x2489380; 1 drivers -v0x23e2890_0 .net "nS0", 0 0, L_0x2488360; 1 drivers -v0x23e2930_0 .net "nS1", 0 0, L_0x2488450; 1 drivers -v0x23e25f0_0 .net "out", 0 0, L_0x2489970; 1 drivers -v0x23e2690_0 .net "out0", 0 0, L_0x2488510; 1 drivers -v0x23e2350_0 .net "out1", 0 0, L_0x2488670; 1 drivers -v0x23e23f0_0 .net "out2", 0 0, L_0x24897a0; 1 drivers -v0x23e20b0_0 .net "out3", 0 0, L_0x2489890; 1 drivers -S_0x23e5b60 .scope module, "TwoMux" "TwoInMux" 2 294, 2 8, S_0x2111ab0; - .timescale -9 -12; -L_0x2489470/d .functor NOT 1, L_0x248a680, C4<0>, C4<0>, C4<0>; -L_0x2489470 .delay (10000,10000,10000) L_0x2489470/d; -L_0x2489560/d .functor AND 1, L_0x2489bf0, L_0x2489470, C4<1>, C4<1>; -L_0x2489560 .delay (20000,20000,20000) L_0x2489560/d; -L_0x2489650/d .functor AND 1, L_0x2489ce0, L_0x248a680, C4<1>, C4<1>; -L_0x2489650 .delay (20000,20000,20000) L_0x2489650/d; -L_0x248a4a0/d .functor OR 1, L_0x2489560, L_0x2489650, C4<0>, C4<0>; -L_0x248a4a0 .delay (20000,20000,20000) L_0x248a4a0/d; -v0x23e58c0_0 .net "S", 0 0, L_0x248a680; 1 drivers -v0x23e5960_0 .net "in0", 0 0, L_0x2489bf0; 1 drivers -v0x23e4950_0 .net "in1", 0 0, L_0x2489ce0; 1 drivers -v0x23e49f0_0 .net "nS", 0 0, L_0x2489470; 1 drivers -v0x225bcd0_0 .net "out0", 0 0, L_0x2489560; 1 drivers -v0x225bd70_0 .net "out1", 0 0, L_0x2489650; 1 drivers -v0x23e46b0_0 .net "outfinal", 0 0, L_0x248a4a0; 1 drivers -S_0x22fcde0 .scope generate, "muxbits[14]" "muxbits[14]" 2 290, 2 290, S_0x22690e0; - .timescale -9 -12; -P_0x22f4ab8 .param/l "i" 2 290, +C4<01110>; -L_0x248c710/d .functor OR 1, L_0x248c850, L_0x248c8f0, C4<0>, C4<0>; -L_0x248c710 .delay (20000,20000,20000) L_0x248c710/d; -v0x230b190_0 .net *"_s15", 0 0, L_0x248c850; 1 drivers -v0x230ae40_0 .net *"_s16", 0 0, L_0x248c8f0; 1 drivers -S_0x2306220 .scope module, "ZeroMux" "FourInMux" 2 292, 2 24, S_0x22fcde0; - .timescale -9 -12; -L_0x248a140/d .functor NOT 1, L_0x248a720, C4<0>, C4<0>, C4<0>; -L_0x248a140 .delay (10000,10000,10000) L_0x248a140/d; -L_0x248a250/d .functor NOT 1, L_0x248a850, C4<0>, C4<0>, C4<0>; -L_0x248a250 .delay (10000,10000,10000) L_0x248a250/d; -L_0x248a310/d .functor NAND 1, L_0x248a140, L_0x248a250, L_0x248a980, C4<1>; -L_0x248a310 .delay (10000,10000,10000) L_0x248a310/d; -L_0x248afb0/d .functor NAND 1, L_0x248a720, L_0x248a250, L_0x248aa20, C4<1>; -L_0x248afb0 .delay (10000,10000,10000) L_0x248afb0/d; -L_0x248b0a0/d .functor NAND 1, L_0x248a140, L_0x248a850, L_0x248aac0, C4<1>; -L_0x248b0a0 .delay (10000,10000,10000) L_0x248b0a0/d; -L_0x248b190/d .functor NAND 1, L_0x248a720, L_0x248a850, L_0x248abb0, C4<1>; -L_0x248b190 .delay (10000,10000,10000) L_0x248b190/d; -L_0x248b270/d .functor NAND 1, L_0x248a310, L_0x248afb0, L_0x248b0a0, L_0x248b190; -L_0x248b270 .delay (10000,10000,10000) L_0x248b270/d; -v0x2305290_0 .net "S0", 0 0, L_0x248a720; 1 drivers -v0x2304fe0_0 .net "S1", 0 0, L_0x248a850; 1 drivers -v0x2305080_0 .net "in0", 0 0, L_0x248a980; 1 drivers -v0x23026e0_0 .net "in1", 0 0, L_0x248aa20; 1 drivers -v0x2302760_0 .net "in2", 0 0, L_0x248aac0; 1 drivers -v0x2309000_0 .net "in3", 0 0, L_0x248abb0; 1 drivers -v0x23090a0_0 .net "nS0", 0 0, L_0x248a140; 1 drivers -v0x2308d50_0 .net "nS1", 0 0, L_0x248a250; 1 drivers -v0x2308df0_0 .net "out", 0 0, L_0x248b270; 1 drivers -v0x230c310_0 .net "out0", 0 0, L_0x248a310; 1 drivers -v0x230c390_0 .net "out1", 0 0, L_0x248afb0; 1 drivers -v0x230c060_0 .net "out2", 0 0, L_0x248b0a0; 1 drivers -v0x230b0f0_0 .net "out3", 0 0, L_0x248b190; 1 drivers -S_0x22fc880 .scope module, "OneMux" "FourInMux" 2 293, 2 24, S_0x22fcde0; - .timescale -9 -12; -L_0x248aca0/d .functor NOT 1, L_0x248c2c0, C4<0>, C4<0>, C4<0>; -L_0x248aca0 .delay (10000,10000,10000) L_0x248aca0/d; -L_0x248ad90/d .functor NOT 1, L_0x248b4f0, C4<0>, C4<0>, C4<0>; -L_0x248ad90 .delay (10000,10000,10000) L_0x248ad90/d; -L_0x248ae30/d .functor NAND 1, L_0x248aca0, L_0x248ad90, L_0x248b620, C4<1>; -L_0x248ae30 .delay (10000,10000,10000) L_0x248ae30/d; -L_0x248bdc0/d .functor NAND 1, L_0x248c2c0, L_0x248ad90, L_0x248b6c0, C4<1>; -L_0x248bdc0 .delay (10000,10000,10000) L_0x248bdc0/d; -L_0x248be70/d .functor NAND 1, L_0x248aca0, L_0x248b4f0, L_0x248b760, C4<1>; -L_0x248be70 .delay (10000,10000,10000) L_0x248be70/d; -L_0x248bf60/d .functor NAND 1, L_0x248c2c0, L_0x248b4f0, L_0x248b850, C4<1>; -L_0x248bf60 .delay (10000,10000,10000) L_0x248bf60/d; -L_0x248c040/d .functor NAND 1, L_0x248ae30, L_0x248bdc0, L_0x248be70, L_0x248bf60; -L_0x248c040 .delay (10000,10000,10000) L_0x248c040/d; -v0x2304d30_0 .net "S0", 0 0, L_0x248c2c0; 1 drivers -v0x2304dd0_0 .net "S1", 0 0, L_0x248b4f0; 1 drivers -v0x2304a80_0 .net "in0", 0 0, L_0x248b620; 1 drivers -v0x2304b20_0 .net "in1", 0 0, L_0x248b6c0; 1 drivers -v0x23047d0_0 .net "in2", 0 0, L_0x248b760; 1 drivers -v0x2304870_0 .net "in3", 0 0, L_0x248b850; 1 drivers -v0x2303200_0 .net "nS0", 0 0, L_0x248aca0; 1 drivers -v0x2302ef0_0 .net "nS1", 0 0, L_0x248ad90; 1 drivers -v0x2302f70_0 .net "out", 0 0, L_0x248c040; 1 drivers -v0x2302c40_0 .net "out0", 0 0, L_0x248ae30; 1 drivers -v0x2302ce0_0 .net "out1", 0 0, L_0x248bdc0; 1 drivers -v0x23029b0_0 .net "out2", 0 0, L_0x248be70; 1 drivers -v0x23064f0_0 .net "out3", 0 0, L_0x248bf60; 1 drivers -S_0x22fcb30 .scope module, "TwoMux" "TwoInMux" 2 294, 2 8, S_0x22fcde0; - .timescale -9 -12; -L_0x248b940/d .functor NOT 1, L_0x248c3f0, C4<0>, C4<0>, C4<0>; -L_0x248b940 .delay (10000,10000,10000) L_0x248b940/d; -L_0x248ba30/d .functor AND 1, L_0x248c490, L_0x248b940, C4<1>, C4<1>; -L_0x248ba30 .delay (20000,20000,20000) L_0x248ba30/d; -L_0x248bb20/d .functor AND 1, L_0x248c580, L_0x248c3f0, C4<1>, C4<1>; -L_0x248bb20 .delay (20000,20000,20000) L_0x248bb20/d; -L_0x248bc10/d .functor OR 1, L_0x248ba30, L_0x248bb20, C4<0>, C4<0>; -L_0x248bc10 .delay (20000,20000,20000) L_0x248bc10/d; -v0x2300670_0 .net "S", 0 0, L_0x248c3f0; 1 drivers -v0x2300710_0 .net "in0", 0 0, L_0x248c490; 1 drivers -v0x23003c0_0 .net "in1", 0 0, L_0x248c580; 1 drivers -v0x2300460_0 .net "nS", 0 0, L_0x248b940; 1 drivers -v0x22ff430_0 .net "out0", 0 0, L_0x248ba30; 1 drivers -v0x22ff4d0_0 .net "out1", 0 0, L_0x248bb20; 1 drivers -v0x22ff1e0_0 .net "outfinal", 0 0, L_0x248bc10; 1 drivers -S_0x22ed990 .scope generate, "muxbits[15]" "muxbits[15]" 2 290, 2 290, S_0x22690e0; - .timescale -9 -12; -P_0x22e1a68 .param/l "i" 2 290, +C4<01111>; -L_0x248eb90/d .functor OR 1, L_0x248ec90, L_0x248ed30, C4<0>, C4<0>; -L_0x248eb90 .delay (20000,20000,20000) L_0x248eb90/d; -v0x22fd3e0_0 .net *"_s15", 0 0, L_0x248ec90; 1 drivers -v0x22fd0b0_0 .net *"_s16", 0 0, L_0x248ed30; 1 drivers -S_0x22fa810 .scope module, "ZeroMux" "FourInMux" 2 292, 2 24, S_0x22ed990; - .timescale -9 -12; -L_0x248c9e0/d .functor NOT 1, L_0x248db70, C4<0>, C4<0>, C4<0>; -L_0x248c9e0 .delay (10000,10000,10000) L_0x248c9e0/d; -L_0x248cad0/d .functor NOT 1, L_0x248cd90, C4<0>, C4<0>, C4<0>; -L_0x248cad0 .delay (10000,10000,10000) L_0x248cad0/d; -L_0x248cb70/d .functor NAND 1, L_0x248c9e0, L_0x248cad0, L_0x248cec0, C4<1>; -L_0x248cb70 .delay (10000,10000,10000) L_0x248cb70/d; -L_0x248bd50/d .functor NAND 1, L_0x248db70, L_0x248cad0, L_0x248cf60, C4<1>; -L_0x248bd50 .delay (10000,10000,10000) L_0x248bd50/d; -L_0x248d720/d .functor NAND 1, L_0x248c9e0, L_0x248cd90, L_0x248d000, C4<1>; -L_0x248d720 .delay (10000,10000,10000) L_0x248d720/d; -L_0x248d810/d .functor NAND 1, L_0x248db70, L_0x248cd90, L_0x248d0f0, C4<1>; -L_0x248d810 .delay (10000,10000,10000) L_0x248d810/d; -L_0x248d8f0/d .functor NAND 1, L_0x248cb70, L_0x248bd50, L_0x248d720, L_0x248d810; -L_0x248d8f0 .delay (10000,10000,10000) L_0x248d8f0/d; -v0x22fa560_0 .net "S0", 0 0, L_0x248db70; 1 drivers -v0x22fa600_0 .net "S1", 0 0, L_0x248cd90; 1 drivers -v0x22f95d0_0 .net "in0", 0 0, L_0x248cec0; 1 drivers -v0x22f9670_0 .net "in1", 0 0, L_0x248cf60; 1 drivers -v0x22f9320_0 .net "in2", 0 0, L_0x248d000; 1 drivers -v0x22f93c0_0 .net "in3", 0 0, L_0x248d0f0; 1 drivers -v0x22f6a40_0 .net "nS0", 0 0, L_0x248c9e0; 1 drivers -v0x22feed0_0 .net "nS1", 0 0, L_0x248cad0; 1 drivers -v0x22fef70_0 .net "out", 0 0, L_0x248d8f0; 1 drivers -v0x22fec20_0 .net "out0", 0 0, L_0x248cb70; 1 drivers -v0x22fecc0_0 .net "out1", 0 0, L_0x248bd50; 1 drivers -v0x22fe970_0 .net "out2", 0 0, L_0x248d720; 1 drivers -v0x22fd340_0 .net "out3", 0 0, L_0x248d810; 1 drivers -S_0x22f3500 .scope module, "OneMux" "FourInMux" 2 293, 2 24, S_0x22ed990; - .timescale -9 -12; -L_0x248d1e0/d .functor NOT 1, L_0x248dca0, C4<0>, C4<0>, C4<0>; -L_0x248d1e0 .delay (10000,10000,10000) L_0x248d1e0/d; -L_0x248d290/d .functor NOT 1, L_0x248ddd0, C4<0>, C4<0>, C4<0>; -L_0x248d290 .delay (10000,10000,10000) L_0x248d290/d; -L_0x248d330/d .functor NAND 1, L_0x248d1e0, L_0x248d290, L_0x248df00, C4<1>; -L_0x248d330 .delay (10000,10000,10000) L_0x248d330/d; -L_0x248d470/d .functor NAND 1, L_0x248dca0, L_0x248d290, L_0x248dfa0, C4<1>; -L_0x248d470 .delay (10000,10000,10000) L_0x248d470/d; -L_0x248d560/d .functor NAND 1, L_0x248d1e0, L_0x248ddd0, L_0x248e040, C4<1>; -L_0x248d560 .delay (10000,10000,10000) L_0x248d560/d; -L_0x248d650/d .functor NAND 1, L_0x248dca0, L_0x248ddd0, L_0x248e130, C4<1>; -L_0x248d650 .delay (10000,10000,10000) L_0x248d650/d; -L_0x248e690/d .functor NAND 1, L_0x248d330, L_0x248d470, L_0x248d560, L_0x248d650; -L_0x248e690 .delay (10000,10000,10000) L_0x248e690/d; -v0x22f3850_0 .net "S0", 0 0, L_0x248dca0; 1 drivers -v0x22f9070_0 .net "S1", 0 0, L_0x248ddd0; 1 drivers -v0x22f90f0_0 .net "in0", 0 0, L_0x248df00; 1 drivers -v0x22f8dc0_0 .net "in1", 0 0, L_0x248dfa0; 1 drivers -v0x22f8e60_0 .net "in2", 0 0, L_0x248e040; 1 drivers -v0x22f8b10_0 .net "in3", 0 0, L_0x248e130; 1 drivers -v0x22f8bb0_0 .net "nS0", 0 0, L_0x248d1e0; 1 drivers -v0x22f7500_0 .net "nS1", 0 0, L_0x248d290; 1 drivers -v0x22f7230_0 .net "out", 0 0, L_0x248e690; 1 drivers -v0x22f72d0_0 .net "out0", 0 0, L_0x248d330; 1 drivers -v0x22f6f80_0 .net "out1", 0 0, L_0x248d470; 1 drivers -v0x22f7020_0 .net "out2", 0 0, L_0x248d560; 1 drivers -v0x22f6d60_0 .net "out3", 0 0, L_0x248d650; 1 drivers -S_0x22ed6e0 .scope module, "TwoMux" "TwoInMux" 2 294, 2 8, S_0x22ed990; - .timescale -9 -12; -L_0x22f7580/d .functor NOT 1, L_0x248f360, C4<0>, C4<0>, C4<0>; -L_0x22f7580 .delay (10000,10000,10000) L_0x22f7580/d; -L_0x248e2b0/d .functor AND 1, L_0x248e910, L_0x22f7580, C4<1>, C4<1>; -L_0x248e2b0 .delay (20000,20000,20000) L_0x248e2b0/d; -L_0x248e3a0/d .functor AND 1, L_0x248ea00, L_0x248f360, C4<1>, C4<1>; -L_0x248e3a0 .delay (20000,20000,20000) L_0x248e3a0/d; -L_0x248e490/d .functor OR 1, L_0x248e2b0, L_0x248e3a0, C4<0>, C4<0>; -L_0x248e490 .delay (20000,20000,20000) L_0x248e490/d; -v0x22f16c0_0 .net "S", 0 0, L_0x248f360; 1 drivers -v0x22f1760_0 .net "in0", 0 0, L_0x248e910; 1 drivers -v0x22f1410_0 .net "in1", 0 0, L_0x248ea00; 1 drivers -v0x22f14b0_0 .net "nS", 0 0, L_0x22f7580; 1 drivers -v0x22f49f0_0 .net "out0", 0 0, L_0x248e2b0; 1 drivers -v0x22f4720_0 .net "out1", 0 0, L_0x248e3a0; 1 drivers -v0x22f37b0_0 .net "outfinal", 0 0, L_0x248e490; 1 drivers -S_0x22e17b0 .scope generate, "muxbits[16]" "muxbits[16]" 2 290, 2 290, S_0x22690e0; - .timescale -9 -12; -P_0x22d0318 .param/l "i" 2 290, +C4<010000>; -L_0x247d420/d .functor OR 1, L_0x247e130, L_0x247e1d0, C4<0>, C4<0>; -L_0x247d420 .delay (20000,20000,20000) L_0x247d420/d; -v0x22eec50_0 .net *"_s15", 0 0, L_0x247e130; 1 drivers -v0x22ee900_0 .net *"_s16", 0 0, L_0x247e1d0; 1 drivers -S_0x22e5270 .scope module, "ZeroMux" "FourInMux" 2 292, 2 24, S_0x22e17b0; - .timescale -9 -12; -L_0x248ee20/d .functor NOT 1, L_0x248f400, C4<0>, C4<0>, C4<0>; -L_0x248ee20 .delay (10000,10000,10000) L_0x248ee20/d; -L_0x248ef10/d .functor NOT 1, L_0x248f530, C4<0>, C4<0>, C4<0>; -L_0x248ef10 .delay (10000,10000,10000) L_0x248ef10/d; -L_0x248efb0/d .functor NAND 1, L_0x248ee20, L_0x248ef10, L_0x248f660, C4<1>; -L_0x248efb0 .delay (10000,10000,10000) L_0x248efb0/d; -L_0x248f0f0/d .functor NAND 1, L_0x248f400, L_0x248ef10, L_0x248f700, C4<1>; -L_0x248f0f0 .delay (10000,10000,10000) L_0x248f0f0/d; -L_0x248f1e0/d .functor NAND 1, L_0x248ee20, L_0x248f530, L_0x248f7a0, C4<1>; -L_0x248f1e0 .delay (10000,10000,10000) L_0x248f1e0/d; -L_0x248fe30/d .functor NAND 1, L_0x248f400, L_0x248f530, L_0x248f890, C4<1>; -L_0x248fe30 .delay (10000,10000,10000) L_0x248fe30/d; -L_0x248fed0/d .functor NAND 1, L_0x248efb0, L_0x248f0f0, L_0x248f1e0, L_0x248fe30; -L_0x248fed0 .delay (10000,10000,10000) L_0x248fed0/d; -v0x22e8d90_0 .net "S0", 0 0, L_0x248f400; 1 drivers -v0x22e8ae0_0 .net "S1", 0 0, L_0x248f530; 1 drivers -v0x22e8b80_0 .net "in0", 0 0, L_0x248f660; 1 drivers -v0x22e7b70_0 .net "in1", 0 0, L_0x248f700; 1 drivers -v0x22e7bf0_0 .net "in2", 0 0, L_0x248f7a0; 1 drivers -v0x22e78c0_0 .net "in3", 0 0, L_0x248f890; 1 drivers -v0x22e7960_0 .net "nS0", 0 0, L_0x248ee20; 1 drivers -v0x22e4fc0_0 .net "nS1", 0 0, L_0x248ef10; 1 drivers -v0x22e5060_0 .net "out", 0 0, L_0x248fed0; 1 drivers -v0x22eb8a0_0 .net "out0", 0 0, L_0x248efb0; 1 drivers -v0x22eb920_0 .net "out1", 0 0, L_0x248f0f0; 1 drivers -v0x22eb5f0_0 .net "out2", 0 0, L_0x248f1e0; 1 drivers -v0x22eebb0_0 .net "out3", 0 0, L_0x248fe30; 1 drivers -S_0x22df410 .scope module, "OneMux" "FourInMux" 2 293, 2 24, S_0x22e17b0; - .timescale -9 -12; -L_0x248f980/d .functor NOT 1, L_0x2490f20, C4<0>, C4<0>, C4<0>; -L_0x248f980 .delay (10000,10000,10000) L_0x248f980/d; -L_0x248fa70/d .functor NOT 1, L_0x2490150, C4<0>, C4<0>, C4<0>; -L_0x248fa70 .delay (10000,10000,10000) L_0x248fa70/d; -L_0x248fb10/d .functor NAND 1, L_0x248f980, L_0x248fa70, L_0x2490280, C4<1>; -L_0x248fb10 .delay (10000,10000,10000) L_0x248fb10/d; -L_0x248fc50/d .functor NAND 1, L_0x2490f20, L_0x248fa70, L_0x247ca00, C4<1>; -L_0x248fc50 .delay (10000,10000,10000) L_0x248fc50/d; -L_0x248fd40/d .functor NAND 1, L_0x248f980, L_0x2490150, L_0x247caa0, C4<1>; -L_0x248fd40 .delay (10000,10000,10000) L_0x248fd40/d; -L_0x2490bc0/d .functor NAND 1, L_0x2490f20, L_0x2490150, L_0x2490730, C4<1>; -L_0x2490bc0 .delay (10000,10000,10000) L_0x2490bc0/d; -L_0x2490ca0/d .functor NAND 1, L_0x248fb10, L_0x248fc50, L_0x248fd40, L_0x2490bc0; -L_0x2490ca0 .delay (10000,10000,10000) L_0x2490ca0/d; -v0x22e2f50_0 .net "S0", 0 0, L_0x2490f20; 1 drivers -v0x22e2ff0_0 .net "S1", 0 0, L_0x2490150; 1 drivers -v0x22e2ca0_0 .net "in0", 0 0, L_0x2490280; 1 drivers -v0x22e2d40_0 .net "in1", 0 0, L_0x247ca00; 1 drivers -v0x22e1d10_0 .net "in2", 0 0, L_0x247caa0; 1 drivers -v0x22e1db0_0 .net "in3", 0 0, L_0x2490730; 1 drivers -v0x22e1ac0_0 .net "nS0", 0 0, L_0x248f980; 1 drivers -v0x22df160_0 .net "nS1", 0 0, L_0x248fa70; 1 drivers -v0x22df1e0_0 .net "out", 0 0, L_0x2490ca0; 1 drivers -v0x22e5a80_0 .net "out0", 0 0, L_0x248fb10; 1 drivers -v0x22e5b20_0 .net "out1", 0 0, L_0x248fc50; 1 drivers -v0x22e57f0_0 .net "out2", 0 0, L_0x248fd40; 1 drivers -v0x22e5540_0 .net "out3", 0 0, L_0x2490bc0; 1 drivers -S_0x22e1500 .scope module, "TwoMux" "TwoInMux" 2 294, 2 8, S_0x22e17b0; - .timescale -9 -12; -L_0x2490820/d .functor NOT 1, L_0x2491050, C4<0>, C4<0>, C4<0>; -L_0x2490820 .delay (10000,10000,10000) L_0x2490820/d; -L_0x24908d0/d .functor AND 1, L_0x24910f0, L_0x2490820, C4<1>, C4<1>; -L_0x24908d0 .delay (20000,20000,20000) L_0x24908d0/d; -L_0x24909c0/d .functor AND 1, L_0x247d330, L_0x2491050, C4<1>, C4<1>; -L_0x24909c0 .delay (20000,20000,20000) L_0x24909c0/d; -L_0x2490ab0/d .functor OR 1, L_0x24908d0, L_0x24909c0, C4<0>, C4<0>; -L_0x2490ab0 .delay (20000,20000,20000) L_0x2490ab0/d; -v0x22e1250_0 .net "S", 0 0, L_0x2491050; 1 drivers -v0x22e12f0_0 .net "in0", 0 0, L_0x24910f0; 1 drivers -v0x22dfc20_0 .net "in1", 0 0, L_0x247d330; 1 drivers -v0x22dfcc0_0 .net "nS", 0 0, L_0x2490820; 1 drivers -v0x22df970_0 .net "out0", 0 0, L_0x24908d0; 1 drivers -v0x22dfa10_0 .net "out1", 0 0, L_0x24909c0; 1 drivers -v0x22df720_0 .net "outfinal", 0 0, L_0x2490ab0; 1 drivers -S_0x22ce140 .scope generate, "muxbits[17]" "muxbits[17]" 2 290, 2 290, S_0x22690e0; - .timescale -9 -12; -P_0x22c2348 .param/l "i" 2 290, +C4<010001>; -L_0x24940b0/d .functor OR 1, L_0x24941f0, L_0x2494290, C4<0>, C4<0>; -L_0x24940b0 .delay (20000,20000,20000) L_0x24940b0/d; -v0x22dbca0_0 .net *"_s15", 0 0, L_0x24941f0; 1 drivers -v0x22d9320_0 .net *"_s16", 0 0, L_0x2494290; 1 drivers -S_0x22db3f0 .scope module, "ZeroMux" "FourInMux" 2 292, 2 24, S_0x22ce140; - .timescale -9 -12; -L_0x247e2c0/d .functor NOT 1, L_0x2491f40, C4<0>, C4<0>, C4<0>; -L_0x247e2c0 .delay (10000,10000,10000) L_0x247e2c0/d; -L_0x247dd30/d .functor NOT 1, L_0x2492070, C4<0>, C4<0>, C4<0>; -L_0x247dd30 .delay (10000,10000,10000) L_0x247dd30/d; -L_0x247ddd0/d .functor NAND 1, L_0x247e2c0, L_0x247dd30, L_0x24921a0, C4<1>; -L_0x247ddd0 .delay (10000,10000,10000) L_0x247ddd0/d; -L_0x247df10/d .functor NAND 1, L_0x2491f40, L_0x247dd30, L_0x2492240, C4<1>; -L_0x247df10 .delay (10000,10000,10000) L_0x247df10/d; -L_0x247e000/d .functor NAND 1, L_0x247e2c0, L_0x2492070, L_0x24922e0, C4<1>; -L_0x247e000 .delay (10000,10000,10000) L_0x247e000/d; -L_0x2491be0/d .functor NAND 1, L_0x2491f40, L_0x2492070, L_0x24923d0, C4<1>; -L_0x2491be0 .delay (10000,10000,10000) L_0x2491be0/d; -L_0x2491cc0/d .functor NAND 1, L_0x247ddd0, L_0x247df10, L_0x247e000, L_0x2491be0; -L_0x2491cc0 .delay (10000,10000,10000) L_0x2491cc0/d; -v0x22d9dc0_0 .net "S0", 0 0, L_0x2491f40; 1 drivers -v0x22d9e60_0 .net "S1", 0 0, L_0x2492070; 1 drivers -v0x22d9b10_0 .net "in0", 0 0, L_0x24921a0; 1 drivers -v0x22d9bb0_0 .net "in1", 0 0, L_0x2492240; 1 drivers -v0x22d9860_0 .net "in2", 0 0, L_0x24922e0; 1 drivers -v0x22d9900_0 .net "in3", 0 0, L_0x24923d0; 1 drivers -v0x22d95d0_0 .net "nS0", 0 0, L_0x247e2c0; 1 drivers -v0x22dd0f0_0 .net "nS1", 0 0, L_0x247dd30; 1 drivers -v0x22dd190_0 .net "out", 0 0, L_0x2491cc0; 1 drivers -v0x22dce40_0 .net "out0", 0 0, L_0x247ddd0; 1 drivers -v0x22dcee0_0 .net "out1", 0 0, L_0x247df10; 1 drivers -v0x22dbeb0_0 .net "out2", 0 0, L_0x247e000; 1 drivers -v0x22dbc00_0 .net "out3", 0 0, L_0x2491be0; 1 drivers -S_0x22d3f60 .scope module, "OneMux" "FourInMux" 2 293, 2 24, S_0x22ce140; - .timescale -9 -12; -L_0x24924c0/d .functor NOT 1, L_0x2492e30, C4<0>, C4<0>, C4<0>; -L_0x24924c0 .delay (10000,10000,10000) L_0x24924c0/d; -L_0x24925b0/d .functor NOT 1, L_0x2492f60, C4<0>, C4<0>, C4<0>; -L_0x24925b0 .delay (10000,10000,10000) L_0x24925b0/d; -L_0x2493930/d .functor NAND 1, L_0x24924c0, L_0x24925b0, L_0x2493090, C4<1>; -L_0x2493930 .delay (10000,10000,10000) L_0x2493930/d; -L_0x2493a70/d .functor NAND 1, L_0x2492e30, L_0x24925b0, L_0x2493130, C4<1>; -L_0x2493a70 .delay (10000,10000,10000) L_0x2493a70/d; -L_0x2493b60/d .functor NAND 1, L_0x24924c0, L_0x2492f60, L_0x24931d0, C4<1>; -L_0x2493b60 .delay (10000,10000,10000) L_0x2493b60/d; -L_0x2493c50/d .functor NAND 1, L_0x2492e30, L_0x2492f60, L_0x24932c0, C4<1>; -L_0x2493c50 .delay (10000,10000,10000) L_0x2493c50/d; -L_0x2493d60/d .functor NAND 1, L_0x2493930, L_0x2493a70, L_0x2493b60, L_0x2493c50; -L_0x2493d60 .delay (10000,10000,10000) L_0x2493d60/d; -v0x22d5b90_0 .net "S0", 0 0, L_0x2492e30; 1 drivers -v0x22d3cb0_0 .net "S1", 0 0, L_0x2492f60; 1 drivers -v0x22d3d30_0 .net "in0", 0 0, L_0x2493090; 1 drivers -v0x22d7290_0 .net "in1", 0 0, L_0x2493130; 1 drivers -v0x22d7330_0 .net "in2", 0 0, L_0x24931d0; 1 drivers -v0x22d6fe0_0 .net "in3", 0 0, L_0x24932c0; 1 drivers -v0x22d7080_0 .net "nS0", 0 0, L_0x24924c0; 1 drivers -v0x22d6070_0 .net "nS1", 0 0, L_0x24925b0; 1 drivers -v0x22d5da0_0 .net "out", 0 0, L_0x2493d60; 1 drivers -v0x22d5e40_0 .net "out0", 0 0, L_0x2493930; 1 drivers -v0x22db950_0 .net "out1", 0 0, L_0x2493a70; 1 drivers -v0x22db9f0_0 .net "out2", 0 0, L_0x2493b60; 1 drivers -v0x22db730_0 .net "out3", 0 0, L_0x2493c50; 1 drivers -S_0x22cde90 .scope module, "TwoMux" "TwoInMux" 2 294, 2 8, S_0x22ce140; - .timescale -9 -12; -L_0x22d60f0/d .functor NOT 1, L_0x2493800, C4<0>, C4<0>, C4<0>; -L_0x22d60f0 .delay (10000,10000,10000) L_0x22d60f0/d; -L_0x2493440/d .functor AND 1, L_0x2494b20, L_0x22d60f0, C4<1>, C4<1>; -L_0x2493440 .delay (20000,20000,20000) L_0x2493440/d; -L_0x2493530/d .functor AND 1, L_0x2494bc0, L_0x2493800, C4<1>, C4<1>; -L_0x2493530 .delay (20000,20000,20000) L_0x2493530/d; -L_0x2493620/d .functor OR 1, L_0x2493440, L_0x2493530, C4<0>, C4<0>; -L_0x2493620 .delay (20000,20000,20000) L_0x2493620/d; -v0x22d1450_0 .net "S", 0 0, L_0x2493800; 1 drivers -v0x22d14f0_0 .net "in0", 0 0, L_0x2494b20; 1 drivers -v0x22d11a0_0 .net "in1", 0 0, L_0x2494bc0; 1 drivers -v0x22d1240_0 .net "nS", 0 0, L_0x22d60f0; 1 drivers -v0x22d0250_0 .net "out0", 0 0, L_0x2493440; 1 drivers -v0x22cff80_0 .net "out1", 0 0, L_0x2493530; 1 drivers -v0x22d5af0_0 .net "outfinal", 0 0, L_0x2493620; 1 drivers -S_0x22bfbb0 .scope generate, "muxbits[18]" "muxbits[18]" 2 290, 2 290, S_0x22690e0; - .timescale -9 -12; -P_0x22b2fc8 .param/l "i" 2 290, +C4<010010>; -L_0x24968a0/d .functor OR 1, L_0x24969e0, L_0x2496a80, C4<0>, C4<0>; -L_0x24968a0 .delay (20000,20000,20000) L_0x24968a0/d; -v0x22ca4b0_0 .net *"_s15", 0 0, L_0x24969e0; 1 drivers -v0x22ca160_0 .net *"_s16", 0 0, L_0x2496a80; 1 drivers -S_0x22c52b0 .scope module, "ZeroMux" "FourInMux" 2 292, 2 24, S_0x22bfbb0; - .timescale -9 -12; -L_0x2494380/d .functor NOT 1, L_0x2494cb0, C4<0>, C4<0>, C4<0>; -L_0x2494380 .delay (10000,10000,10000) L_0x2494380/d; -L_0x2494470/d .functor NOT 1, L_0x2494de0, C4<0>, C4<0>, C4<0>; -L_0x2494470 .delay (10000,10000,10000) L_0x2494470/d; -L_0x2494510/d .functor NAND 1, L_0x2494380, L_0x2494470, L_0x2494f10, C4<1>; -L_0x2494510 .delay (10000,10000,10000) L_0x2494510/d; -L_0x2494650/d .functor NAND 1, L_0x2494cb0, L_0x2494470, L_0x2494fb0, C4<1>; -L_0x2494650 .delay (10000,10000,10000) L_0x2494650/d; -L_0x2494740/d .functor NAND 1, L_0x2494380, L_0x2494de0, L_0x2495050, C4<1>; -L_0x2494740 .delay (10000,10000,10000) L_0x2494740/d; -L_0x2494830/d .functor NAND 1, L_0x2494cb0, L_0x2494de0, L_0x2495140, C4<1>; -L_0x2494830 .delay (10000,10000,10000) L_0x2494830/d; -L_0x2494970/d .functor NAND 1, L_0x2494510, L_0x2494650, L_0x2494740, L_0x2494830; -L_0x2494970 .delay (10000,10000,10000) L_0x2494970/d; -v0x22c4610_0 .net "S0", 0 0, L_0x2494cb0; 1 drivers -v0x22c4380_0 .net "S1", 0 0, L_0x2494de0; 1 drivers -v0x22c4420_0 .net "in0", 0 0, L_0x2494f10; 1 drivers -v0x22c18a0_0 .net "in1", 0 0, L_0x2494fb0; 1 drivers -v0x22c1920_0 .net "in2", 0 0, L_0x2495050; 1 drivers -v0x22c8320_0 .net "in3", 0 0, L_0x2495140; 1 drivers -v0x22c83c0_0 .net "nS0", 0 0, L_0x2494380; 1 drivers -v0x22c8070_0 .net "nS1", 0 0, L_0x2494470; 1 drivers -v0x22c8110_0 .net "out", 0 0, L_0x2494970; 1 drivers -v0x22cb630_0 .net "out0", 0 0, L_0x2494510; 1 drivers -v0x22cb6b0_0 .net "out1", 0 0, L_0x2494650; 1 drivers -v0x22cb380_0 .net "out2", 0 0, L_0x2494740; 1 drivers -v0x22ca410_0 .net "out3", 0 0, L_0x2494830; 1 drivers -S_0x22c40f0 .scope module, "OneMux" "FourInMux" 2 293, 2 24, S_0x22bfbb0; - .timescale -9 -12; -L_0x2495230/d .functor NOT 1, L_0x2496770, C4<0>, C4<0>, C4<0>; -L_0x2495230 .delay (10000,10000,10000) L_0x2495230/d; -L_0x2495320/d .functor NOT 1, L_0x2495910, C4<0>, C4<0>, C4<0>; -L_0x2495320 .delay (10000,10000,10000) L_0x2495320/d; -L_0x24953c0/d .functor NAND 1, L_0x2495230, L_0x2495320, L_0x2495a40, C4<1>; -L_0x24953c0 .delay (10000,10000,10000) L_0x24953c0/d; -L_0x2495500/d .functor NAND 1, L_0x2496770, L_0x2495320, L_0x2495ae0, C4<1>; -L_0x2495500 .delay (10000,10000,10000) L_0x2495500/d; -L_0x24955f0/d .functor NAND 1, L_0x2495230, L_0x2495910, L_0x2495b80, C4<1>; -L_0x24955f0 .delay (10000,10000,10000) L_0x24955f0/d; -L_0x24956e0/d .functor NAND 1, L_0x2496770, L_0x2495910, L_0x2495c70, C4<1>; -L_0x24956e0 .delay (10000,10000,10000) L_0x24956e0/d; -L_0x24964c0/d .functor NAND 1, L_0x24953c0, L_0x2495500, L_0x24955f0, L_0x24956e0; -L_0x24964c0 .delay (10000,10000,10000) L_0x24964c0/d; -v0x22c3e60_0 .net "S0", 0 0, L_0x2496770; 1 drivers -v0x22c3f00_0 .net "S1", 0 0, L_0x2495910; 1 drivers -v0x22c38e0_0 .net "in0", 0 0, L_0x2495a40; 1 drivers -v0x22c3980_0 .net "in1", 0 0, L_0x2495ae0; 1 drivers -v0x22c25d0_0 .net "in2", 0 0, L_0x2495b80; 1 drivers -v0x22c2670_0 .net "in3", 0 0, L_0x2495c70; 1 drivers -v0x22c23a0_0 .net "nS0", 0 0, L_0x2495230; 1 drivers -v0x22c20b0_0 .net "nS1", 0 0, L_0x2495320; 1 drivers -v0x22c2130_0 .net "out", 0 0, L_0x24964c0; 1 drivers -v0x22c1e20_0 .net "out0", 0 0, L_0x24953c0; 1 drivers -v0x22c1ec0_0 .net "out1", 0 0, L_0x2495500; 1 drivers -v0x22c5820_0 .net "out2", 0 0, L_0x24955f0; 1 drivers -v0x22c5590_0 .net "out3", 0 0, L_0x24956e0; 1 drivers -S_0x22bf920 .scope module, "TwoMux" "TwoInMux" 2 294, 2 8, S_0x22bfbb0; - .timescale -9 -12; -L_0x2495d60/d .functor NOT 1, L_0x24961d0, C4<0>, C4<0>, C4<0>; -L_0x2495d60 .delay (10000,10000,10000) L_0x2495d60/d; -L_0x2495e10/d .functor AND 1, L_0x2496270, L_0x2495d60, C4<1>, C4<1>; -L_0x2495e10 .delay (20000,20000,20000) L_0x2495e10/d; -L_0x2495f00/d .functor AND 1, L_0x2496360, L_0x24961d0, C4<1>, C4<1>; -L_0x2495f00 .delay (20000,20000,20000) L_0x2495f00/d; -L_0x2495ff0/d .functor OR 1, L_0x2495e10, L_0x2495f00, C4<0>, C4<0>; -L_0x2495ff0 .delay (20000,20000,20000) L_0x2495ff0/d; -v0x22bf660_0 .net "S", 0 0, L_0x24961d0; 1 drivers -v0x22bf700_0 .net "in0", 0 0, L_0x2496270; 1 drivers -v0x22be9c0_0 .net "in1", 0 0, L_0x2496360; 1 drivers -v0x22bea60_0 .net "nS", 0 0, L_0x2495d60; 1 drivers -v0x22be730_0 .net "out0", 0 0, L_0x2495e10; 1 drivers -v0x22be7d0_0 .net "out1", 0 0, L_0x2495f00; 1 drivers -v0x22bbcb0_0 .net "outfinal", 0 0, L_0x2495ff0; 1 drivers -S_0x22b0ef0 .scope generate, "muxbits[19]" "muxbits[19]" 2 290, 2 290, S_0x22690e0; - .timescale -9 -12; -P_0x22a1c18 .param/l "i" 2 290, +C4<010011>; -L_0x2499c20/d .functor OR 1, L_0x2499d60, L_0x2498f10, C4<0>, C4<0>; -L_0x2499c20 .delay (20000,20000,20000) L_0x2499c20/d; -v0x22bc500_0 .net *"_s15", 0 0, L_0x2499d60; 1 drivers -v0x22bc1f0_0 .net *"_s16", 0 0, L_0x2498f10; 1 drivers -S_0x22b8d70 .scope module, "ZeroMux" "FourInMux" 2 292, 2 24, S_0x22b0ef0; - .timescale -9 -12; -L_0x2496b70/d .functor NOT 1, L_0x24980e0, C4<0>, C4<0>, C4<0>; -L_0x2496b70 .delay (10000,10000,10000) L_0x2496b70/d; -L_0x2496c60/d .functor NOT 1, L_0x2497500, C4<0>, C4<0>, C4<0>; -L_0x2496c60 .delay (10000,10000,10000) L_0x2496c60/d; -L_0x2496d00/d .functor NAND 1, L_0x2496b70, L_0x2496c60, L_0x2497630, C4<1>; -L_0x2496d00 .delay (10000,10000,10000) L_0x2496d00/d; -L_0x2496e40/d .functor NAND 1, L_0x24980e0, L_0x2496c60, L_0x24976d0, C4<1>; -L_0x2496e40 .delay (10000,10000,10000) L_0x2496e40/d; -L_0x2496f30/d .functor NAND 1, L_0x2496b70, L_0x2497500, L_0x2497770, C4<1>; -L_0x2496f30 .delay (10000,10000,10000) L_0x2496f30/d; -L_0x2497020/d .functor NAND 1, L_0x24980e0, L_0x2497500, L_0x2497860, C4<1>; -L_0x2497020 .delay (10000,10000,10000) L_0x2497020/d; -L_0x2497130/d .functor NAND 1, L_0x2496d00, L_0x2496e40, L_0x2496f30, L_0x2497020; -L_0x2497130 .delay (10000,10000,10000) L_0x2497130/d; -v0x22b8ae0_0 .net "S0", 0 0, L_0x24980e0; 1 drivers -v0x22b8b80_0 .net "S1", 0 0, L_0x2497500; 1 drivers -v0x22b6000_0 .net "in0", 0 0, L_0x2497630; 1 drivers -v0x22b60a0_0 .net "in1", 0 0, L_0x24976d0; 1 drivers -v0x22be4a0_0 .net "in2", 0 0, L_0x2497770; 1 drivers -v0x22be540_0 .net "in3", 0 0, L_0x2497860; 1 drivers -v0x22be230_0 .net "nS0", 0 0, L_0x2496b70; 1 drivers -v0x22bdc90_0 .net "nS1", 0 0, L_0x2496c60; 1 drivers -v0x22bdd30_0 .net "out", 0 0, L_0x2497130; 1 drivers -v0x22bc980_0 .net "out0", 0 0, L_0x2496d00; 1 drivers -v0x22bca20_0 .net "out1", 0 0, L_0x2496e40; 1 drivers -v0x22bc6f0_0 .net "out2", 0 0, L_0x2496f30; 1 drivers -v0x22bc460_0 .net "out3", 0 0, L_0x2497020; 1 drivers -S_0x22b8040 .scope module, "OneMux" "FourInMux" 2 293, 2 24, S_0x22b0ef0; - .timescale -9 -12; -L_0x2497950/d .functor NOT 1, L_0x2498210, C4<0>, C4<0>, C4<0>; -L_0x2497950 .delay (10000,10000,10000) L_0x2497950/d; -L_0x2497a00/d .functor NOT 1, L_0x2498340, C4<0>, C4<0>, C4<0>; -L_0x2497a00 .delay (10000,10000,10000) L_0x2497a00/d; -L_0x2497aa0/d .functor NAND 1, L_0x2497950, L_0x2497a00, L_0x2498470, C4<1>; -L_0x2497aa0 .delay (10000,10000,10000) L_0x2497aa0/d; -L_0x2497be0/d .functor NAND 1, L_0x2498210, L_0x2497a00, L_0x2498510, C4<1>; -L_0x2497be0 .delay (10000,10000,10000) L_0x2497be0/d; -L_0x2497cd0/d .functor NAND 1, L_0x2497950, L_0x2498340, L_0x24985b0, C4<1>; -L_0x2497cd0 .delay (10000,10000,10000) L_0x2497cd0/d; -L_0x2497df0/d .functor NAND 1, L_0x2498210, L_0x2498340, L_0x24986a0, C4<1>; -L_0x2497df0 .delay (10000,10000,10000) L_0x2497df0/d; -L_0x2497f60/d .functor NAND 1, L_0x2497aa0, L_0x2497be0, L_0x2497cd0, L_0x2497df0; -L_0x2497f60 .delay (10000,10000,10000) L_0x2497f60/d; -v0x22b8660_0 .net "S0", 0 0, L_0x2498210; 1 drivers -v0x22b6d30_0 .net "S1", 0 0, L_0x2498340; 1 drivers -v0x22b6db0_0 .net "in0", 0 0, L_0x2498470; 1 drivers -v0x22b6aa0_0 .net "in1", 0 0, L_0x2498510; 1 drivers -v0x22b6b40_0 .net "in2", 0 0, L_0x24985b0; 1 drivers -v0x22b6810_0 .net "in3", 0 0, L_0x24986a0; 1 drivers -v0x22b68b0_0 .net "nS0", 0 0, L_0x2497950; 1 drivers -v0x22b65a0_0 .net "nS1", 0 0, L_0x2497a00; 1 drivers -v0x22b9f60_0 .net "out", 0 0, L_0x2497f60; 1 drivers -v0x22ba000_0 .net "out0", 0 0, L_0x2497aa0; 1 drivers -v0x22b9cd0_0 .net "out1", 0 0, L_0x2497be0; 1 drivers -v0x22b9d70_0 .net "out2", 0 0, L_0x2497cd0; 1 drivers -v0x22b9aa0_0 .net "out3", 0 0, L_0x2497df0; 1 drivers -S_0x22b4310 .scope module, "TwoMux" "TwoInMux" 2 294, 2 8, S_0x22b0ef0; - .timescale -9 -12; -L_0x22b6620/d .functor NOT 1, L_0x2498ba0, C4<0>, C4<0>, C4<0>; -L_0x22b6620 .delay (10000,10000,10000) L_0x22b6620/d; -L_0x24987e0/d .functor AND 1, L_0x2498c40, L_0x22b6620, C4<1>, C4<1>; -L_0x24987e0 .delay (20000,20000,20000) L_0x24987e0/d; -L_0x24988d0/d .functor AND 1, L_0x2498d30, L_0x2498ba0, C4<1>, C4<1>; -L_0x24988d0 .delay (20000,20000,20000) L_0x24988d0/d; -L_0x24989c0/d .functor OR 1, L_0x24987e0, L_0x24988d0, C4<0>, C4<0>; -L_0x24989c0 .delay (20000,20000,20000) L_0x24989c0/d; -v0x22b4080_0 .net "S", 0 0, L_0x2498ba0; 1 drivers -v0x22b4120_0 .net "in0", 0 0, L_0x2498c40; 1 drivers -v0x22b3170_0 .net "in1", 0 0, L_0x2498d30; 1 drivers -v0x22b3210_0 .net "nS", 0 0, L_0x22b6620; 1 drivers -v0x22b2f00_0 .net "out0", 0 0, L_0x24987e0; 1 drivers -v0x22b8850_0 .net "out1", 0 0, L_0x24988d0; 1 drivers -v0x22b85c0_0 .net "outfinal", 0 0, L_0x24989c0; 1 drivers -S_0x22a16f0 .scope generate, "muxbits[20]" "muxbits[20]" 2 290, 2 290, S_0x22690e0; - .timescale -9 -12; -P_0x22946a8 .param/l "i" 2 290, +C4<010100>; -L_0x249b5f0/d .functor OR 1, L_0x249b730, L_0x249b7d0, C4<0>, C4<0>; -L_0x249b5f0 .delay (20000,20000,20000) L_0x249b5f0/d; -v0x22ad420_0 .net *"_s15", 0 0, L_0x249b730; 1 drivers -v0x22b1180_0 .net *"_s16", 0 0, L_0x249b7d0; 1 drivers -S_0x22a89c0 .scope module, "ZeroMux" "FourInMux" 2 292, 2 24, S_0x22a16f0; - .timescale -9 -12; -L_0x2499000/d .functor NOT 1, L_0x24998a0, C4<0>, C4<0>, C4<0>; -L_0x2499000 .delay (10000,10000,10000) L_0x2499000/d; -L_0x24990f0/d .functor NOT 1, L_0x24999d0, C4<0>, C4<0>, C4<0>; -L_0x24990f0 .delay (10000,10000,10000) L_0x24990f0/d; -L_0x2499190/d .functor NAND 1, L_0x2499000, L_0x24990f0, L_0x249aaa0, C4<1>; -L_0x2499190 .delay (10000,10000,10000) L_0x2499190/d; -L_0x24992d0/d .functor NAND 1, L_0x24998a0, L_0x24990f0, L_0x249ab40, C4<1>; -L_0x24992d0 .delay (10000,10000,10000) L_0x24992d0/d; -L_0x24993c0/d .functor NAND 1, L_0x2499000, L_0x24999d0, L_0x2499e00, C4<1>; -L_0x24993c0 .delay (10000,10000,10000) L_0x24993c0/d; -L_0x24994b0/d .functor NAND 1, L_0x24998a0, L_0x24999d0, L_0x2499ef0, C4<1>; -L_0x24994b0 .delay (10000,10000,10000) L_0x24994b0/d; -L_0x24995f0/d .functor NAND 1, L_0x2499190, L_0x24992d0, L_0x24993c0, L_0x24994b0; -L_0x24995f0 .delay (10000,10000,10000) L_0x24995f0/d; -v0x22a7ab0_0 .net "S0", 0 0, L_0x24998a0; 1 drivers -v0x22a7820_0 .net "S1", 0 0, L_0x24999d0; 1 drivers -v0x22a78c0_0 .net "in0", 0 0, L_0x249aaa0; 1 drivers -v0x22ab620_0 .net "in1", 0 0, L_0x249ab40; 1 drivers -v0x22ab6a0_0 .net "in2", 0 0, L_0x2499e00; 1 drivers -v0x22ab390_0 .net "in3", 0 0, L_0x2499ef0; 1 drivers -v0x22ab430_0 .net "nS0", 0 0, L_0x2499000; 1 drivers -v0x22ae7b0_0 .net "nS1", 0 0, L_0x24990f0; 1 drivers -v0x22ae850_0 .net "out", 0 0, L_0x24995f0; 1 drivers -v0x22ae520_0 .net "out0", 0 0, L_0x2499190; 1 drivers -v0x22ae5a0_0 .net "out1", 0 0, L_0x24992d0; 1 drivers -v0x22ad610_0 .net "out2", 0 0, L_0x24993c0; 1 drivers -v0x22ad380_0 .net "out3", 0 0, L_0x24994b0; 1 drivers -S_0x22a3090 .scope module, "OneMux" "FourInMux" 2 293, 2 24, S_0x22a16f0; - .timescale -9 -12; -L_0x2499fe0/d .functor NOT 1, L_0x249a8b0, C4<0>, C4<0>, C4<0>; -L_0x2499fe0 .delay (10000,10000,10000) L_0x2499fe0/d; -L_0x249a0d0/d .functor NOT 1, L_0x249a9e0, C4<0>, C4<0>, C4<0>; -L_0x249a0d0 .delay (10000,10000,10000) L_0x249a0d0/d; -L_0x249a170/d .functor NAND 1, L_0x2499fe0, L_0x249a0d0, L_0x249b940, C4<1>; -L_0x249a170 .delay (10000,10000,10000) L_0x249a170/d; -L_0x249a2b0/d .functor NAND 1, L_0x249a8b0, L_0x249a0d0, L_0x249abe0, C4<1>; -L_0x249a2b0 .delay (10000,10000,10000) L_0x249a2b0/d; -L_0x249a3a0/d .functor NAND 1, L_0x2499fe0, L_0x249a9e0, L_0x249ac80, C4<1>; -L_0x249a3a0 .delay (10000,10000,10000) L_0x249a3a0/d; -L_0x249a490/d .functor NAND 1, L_0x249a8b0, L_0x249a9e0, L_0x249ad70, C4<1>; -L_0x249a490 .delay (10000,10000,10000) L_0x249a490/d; -L_0x249a600/d .functor NAND 1, L_0x249a170, L_0x249a2b0, L_0x249a3a0, L_0x249a490; -L_0x249a600 .delay (10000,10000,10000) L_0x249a600/d; -v0x22a2e00_0 .net "S0", 0 0, L_0x249a8b0; 1 drivers -v0x22a2ea0_0 .net "S1", 0 0, L_0x249a9e0; 1 drivers -v0x22a2b40_0 .net "in0", 0 0, L_0x249b940; 1 drivers -v0x22a2be0_0 .net "in1", 0 0, L_0x249abe0; 1 drivers -v0x22a1ea0_0 .net "in2", 0 0, L_0x249ac80; 1 drivers -v0x22a1f40_0 .net "in3", 0 0, L_0x249ad70; 1 drivers -v0x22a1c70_0 .net "nS0", 0 0, L_0x2499fe0; 1 drivers -v0x229f130_0 .net "nS1", 0 0, L_0x249a0d0; 1 drivers -v0x229f1b0_0 .net "out", 0 0, L_0x249a600; 1 drivers -v0x22a5ac0_0 .net "out0", 0 0, L_0x249a170; 1 drivers -v0x22a5b60_0 .net "out1", 0 0, L_0x249a2b0; 1 drivers -v0x22a5850_0 .net "out2", 0 0, L_0x249a3a0; 1 drivers -v0x22a8c70_0 .net "out3", 0 0, L_0x249a490; 1 drivers -S_0x22a1170 .scope module, "TwoMux" "TwoInMux" 2 294, 2 8, S_0x22a16f0; - .timescale -9 -12; -L_0x249ae60/d .functor NOT 1, L_0x249b2d0, C4<0>, C4<0>, C4<0>; -L_0x249ae60 .delay (10000,10000,10000) L_0x249ae60/d; -L_0x249af10/d .functor AND 1, L_0x249b370, L_0x249ae60, C4<1>, C4<1>; -L_0x249af10 .delay (20000,20000,20000) L_0x249af10/d; -L_0x249b000/d .functor AND 1, L_0x249b460, L_0x249b2d0, C4<1>, C4<1>; -L_0x249b000 .delay (20000,20000,20000) L_0x249b000/d; -L_0x249b0f0/d .functor OR 1, L_0x249af10, L_0x249b000, C4<0>, C4<0>; -L_0x249b0f0 .delay (20000,20000,20000) L_0x249b0f0/d; -v0x229fe60_0 .net "S", 0 0, L_0x249b2d0; 1 drivers -v0x229ff00_0 .net "in0", 0 0, L_0x249b370; 1 drivers -v0x229fbd0_0 .net "in1", 0 0, L_0x249b460; 1 drivers -v0x229fc70_0 .net "nS", 0 0, L_0x249ae60; 1 drivers -v0x229f940_0 .net "out0", 0 0, L_0x249af10; 1 drivers -v0x229f9e0_0 .net "out1", 0 0, L_0x249b000; 1 drivers -v0x229f710_0 .net "outfinal", 0 0, L_0x249b0f0; 1 drivers -S_0x22907c0 .scope generate, "muxbits[21]" "muxbits[21]" 2 290, 2 290, S_0x22690e0; - .timescale -9 -12; -P_0x22862a8 .param/l "i" 2 290, +C4<010101>; -L_0x249d940/d .functor OR 1, L_0x249da80, L_0x249db20, C4<0>, C4<0>; -L_0x249d940 .delay (20000,20000,20000) L_0x249d940/d; -v0x2299580_0 .net *"_s15", 0 0, L_0x249da80; 1 drivers -v0x22a19a0_0 .net *"_s16", 0 0, L_0x249db20; 1 drivers -S_0x2299f80 .scope module, "ZeroMux" "FourInMux" 2 292, 2 24, S_0x22907c0; - .timescale -9 -12; -L_0x249c710/d .functor NOT 1, L_0x249cf70, C4<0>, C4<0>, C4<0>; -L_0x249c710 .delay (10000,10000,10000) L_0x249c710/d; -L_0x249c7c0/d .functor NOT 1, L_0x249b9e0, C4<0>, C4<0>, C4<0>; -L_0x249c7c0 .delay (10000,10000,10000) L_0x249c7c0/d; -L_0x249c860/d .functor NAND 1, L_0x249c710, L_0x249c7c0, L_0x249bb10, C4<1>; -L_0x249c860 .delay (10000,10000,10000) L_0x249c860/d; -L_0x249c9a0/d .functor NAND 1, L_0x249cf70, L_0x249c7c0, L_0x249bbb0, C4<1>; -L_0x249c9a0 .delay (10000,10000,10000) L_0x249c9a0/d; -L_0x249ca90/d .functor NAND 1, L_0x249c710, L_0x249b9e0, L_0x249bc50, C4<1>; -L_0x249ca90 .delay (10000,10000,10000) L_0x249ca90/d; -L_0x249cb80/d .functor NAND 1, L_0x249cf70, L_0x249b9e0, L_0x249bd40, C4<1>; -L_0x249cb80 .delay (10000,10000,10000) L_0x249cb80/d; -L_0x249ccc0/d .functor NAND 1, L_0x249c860, L_0x249c9a0, L_0x249ca90, L_0x249cb80; -L_0x249ccc0 .delay (10000,10000,10000) L_0x249ccc0/d; -v0x2299cf0_0 .net "S0", 0 0, L_0x249cf70; 1 drivers -v0x2299d90_0 .net "S1", 0 0, L_0x249b9e0; 1 drivers -v0x2299a60_0 .net "in0", 0 0, L_0x249bb10; 1 drivers -v0x2299b00_0 .net "in1", 0 0, L_0x249bbb0; 1 drivers -v0x229d440_0 .net "in2", 0 0, L_0x249bc50; 1 drivers -v0x229d4e0_0 .net "in3", 0 0, L_0x249bd40; 1 drivers -v0x229d1d0_0 .net "nS0", 0 0, L_0x249c710; 1 drivers -v0x229cef0_0 .net "nS1", 0 0, L_0x249c7c0; 1 drivers -v0x229cf90_0 .net "out", 0 0, L_0x249ccc0; 1 drivers -v0x229c250_0 .net "out0", 0 0, L_0x249c860; 1 drivers -v0x229c2f0_0 .net "out1", 0 0, L_0x249c9a0; 1 drivers -v0x229bfc0_0 .net "out2", 0 0, L_0x249ca90; 1 drivers -v0x22994e0_0 .net "out3", 0 0, L_0x249cb80; 1 drivers -S_0x2297560 .scope module, "OneMux" "FourInMux" 2 293, 2 24, S_0x22907c0; - .timescale -9 -12; -L_0x249cbe0/d .functor NOT 1, L_0x249d0a0, C4<0>, C4<0>, C4<0>; -L_0x249cbe0 .delay (10000,10000,10000) L_0x249cbe0/d; -L_0x249c690/d .functor NOT 1, L_0x249d1d0, C4<0>, C4<0>, C4<0>; -L_0x249c690 .delay (10000,10000,10000) L_0x249c690/d; -L_0x2482f70/d .functor NAND 1, L_0x249cbe0, L_0x249c690, L_0x249d300, C4<1>; -L_0x2482f70 .delay (10000,10000,10000) L_0x2482f70/d; -L_0x24830b0/d .functor NAND 1, L_0x249d0a0, L_0x249c690, L_0x249d3a0, C4<1>; -L_0x24830b0 .delay (10000,10000,10000) L_0x24830b0/d; -L_0x24831d0/d .functor NAND 1, L_0x249cbe0, L_0x249d1d0, L_0x249d440, C4<1>; -L_0x24831d0 .delay (10000,10000,10000) L_0x24831d0/d; -L_0x249de00/d .functor NAND 1, L_0x249d0a0, L_0x249d1d0, L_0x249d530, C4<1>; -L_0x249de00 .delay (10000,10000,10000) L_0x249de00/d; -L_0x249df70/d .functor NAND 1, L_0x2482f70, L_0x24830b0, L_0x24831d0, L_0x249de00; -L_0x249df70 .delay (10000,10000,10000) L_0x249df70/d; -v0x2297890_0 .net "S0", 0 0, L_0x249d0a0; 1 drivers -v0x22972a0_0 .net "S1", 0 0, L_0x249d1d0; 1 drivers -v0x2297320_0 .net "in0", 0 0, L_0x249d300; 1 drivers -v0x2296600_0 .net "in1", 0 0, L_0x249d3a0; 1 drivers -v0x22966a0_0 .net "in2", 0 0, L_0x249d440; 1 drivers -v0x2296370_0 .net "in3", 0 0, L_0x249d530; 1 drivers -v0x2296410_0 .net "nS0", 0 0, L_0x249cbe0; 1 drivers -v0x229bd50_0 .net "nS1", 0 0, L_0x249c690; 1 drivers -v0x229baa0_0 .net "out", 0 0, L_0x249df70; 1 drivers -v0x229bb40_0 .net "out0", 0 0, L_0x2482f70; 1 drivers -v0x229b520_0 .net "out1", 0 0, L_0x24830b0; 1 drivers -v0x229b5c0_0 .net "out2", 0 0, L_0x24831d0; 1 drivers -v0x229a2a0_0 .net "out3", 0 0, L_0x249de00; 1 drivers -S_0x22960e0 .scope module, "TwoMux" "TwoInMux" 2 294, 2 8, S_0x22907c0; - .timescale -9 -12; -L_0x229bdd0/d .functor NOT 1, L_0x249d620, C4<0>, C4<0>, C4<0>; -L_0x229bdd0 .delay (10000,10000,10000) L_0x229bdd0/d; -L_0x24843f0/d .functor AND 1, L_0x249d6c0, L_0x229bdd0, C4<1>, C4<1>; -L_0x24843f0 .delay (20000,20000,20000) L_0x24843f0/d; -L_0x24844e0/d .functor AND 1, L_0x249d7b0, L_0x249d620, C4<1>, C4<1>; -L_0x24844e0 .delay (20000,20000,20000) L_0x24844e0/d; -L_0x24845d0/d .functor OR 1, L_0x24843f0, L_0x24844e0, C4<0>, C4<0>; -L_0x24845d0 .delay (20000,20000,20000) L_0x24845d0/d; -v0x2295e50_0 .net "S", 0 0, L_0x249d620; 1 drivers -v0x2295ef0_0 .net "in0", 0 0, L_0x249d6c0; 1 drivers -v0x22958d0_0 .net "in1", 0 0, L_0x249d7b0; 1 drivers -v0x2295970_0 .net "nS", 0 0, L_0x229bdd0; 1 drivers -v0x22945e0_0 .net "out0", 0 0, L_0x24843f0; 1 drivers -v0x2294330_0 .net "out1", 0 0, L_0x24844e0; 1 drivers -v0x22977f0_0 .net "outfinal", 0 0, L_0x24845d0; 1 drivers -S_0x227f740 .scope generate, "muxbits[22]" "muxbits[22]" 2 290, 2 290, S_0x22690e0; - .timescale -9 -12; -P_0x2278ea8 .param/l "i" 2 290, +C4<010110>; -L_0x24a03e0/d .functor OR 1, L_0x24a0520, L_0x24a1d40, C4<0>, C4<0>; -L_0x24a03e0 .delay (20000,20000,20000) L_0x24a03e0/d; -v0x2291a00_0 .net *"_s15", 0 0, L_0x24a0520; 1 drivers -v0x2290a50_0 .net *"_s16", 0 0, L_0x24a1d40; 1 drivers -S_0x2288c70 .scope module, "ZeroMux" "FourInMux" 2 292, 2 24, S_0x227f740; - .timescale -9 -12; -L_0x249dc10/d .functor NOT 1, L_0x249e930, C4<0>, C4<0>, C4<0>; -L_0x249dc10 .delay (10000,10000,10000) L_0x249dc10/d; -L_0x249dd00/d .functor NOT 1, L_0x249ea60, C4<0>, C4<0>, C4<0>; -L_0x249dd00 .delay (10000,10000,10000) L_0x249dd00/d; -L_0x249dda0/d .functor NAND 1, L_0x249dc10, L_0x249dd00, L_0x249eb90, C4<1>; -L_0x249dda0 .delay (10000,10000,10000) L_0x249dda0/d; -L_0x249e300/d .functor NAND 1, L_0x249e930, L_0x249dd00, L_0x249ec30, C4<1>; -L_0x249e300 .delay (10000,10000,10000) L_0x249e300/d; -L_0x249e3f0/d .functor NAND 1, L_0x249dc10, L_0x249ea60, L_0x249ecd0, C4<1>; -L_0x249e3f0 .delay (10000,10000,10000) L_0x249e3f0/d; -L_0x249e540/d .functor NAND 1, L_0x249e930, L_0x249ea60, L_0x249edc0, C4<1>; -L_0x249e540 .delay (10000,10000,10000) L_0x249e540/d; -L_0x249e680/d .functor NAND 1, L_0x249dda0, L_0x249e300, L_0x249e3f0, L_0x249e540; -L_0x249e680 .delay (10000,10000,10000) L_0x249e680/d; -v0x228c090_0 .net "S0", 0 0, L_0x249e930; 1 drivers -v0x228be00_0 .net "S1", 0 0, L_0x249ea60; 1 drivers -v0x228bea0_0 .net "in0", 0 0, L_0x249eb90; 1 drivers -v0x228aef0_0 .net "in1", 0 0, L_0x249ec30; 1 drivers -v0x228af70_0 .net "in2", 0 0, L_0x249ecd0; 1 drivers -v0x228ac60_0 .net "in3", 0 0, L_0x249edc0; 1 drivers -v0x228ad00_0 .net "nS0", 0 0, L_0x249dc10; 1 drivers -v0x228ea60_0 .net "nS1", 0 0, L_0x249dd00; 1 drivers -v0x228eb00_0 .net "out", 0 0, L_0x249e680; 1 drivers -v0x228e7d0_0 .net "out0", 0 0, L_0x249dda0; 1 drivers -v0x228e850_0 .net "out1", 0 0, L_0x249e300; 1 drivers -v0x2291bf0_0 .net "out2", 0 0, L_0x249e3f0; 1 drivers -v0x2291960_0 .net "out3", 0 0, L_0x249e540; 1 drivers -S_0x22830c0 .scope module, "OneMux" "FourInMux" 2 293, 2 24, S_0x227f740; - .timescale -9 -12; -L_0x249eeb0/d .functor NOT 1, L_0x24a0da0, C4<0>, C4<0>, C4<0>; -L_0x249eeb0 .delay (10000,10000,10000) L_0x249eeb0/d; -L_0x249ef50/d .functor NOT 1, L_0x249f7c0, C4<0>, C4<0>, C4<0>; -L_0x249ef50 .delay (10000,10000,10000) L_0x249ef50/d; -L_0x24a0660/d .functor NAND 1, L_0x249eeb0, L_0x249ef50, L_0x249f8f0, C4<1>; -L_0x24a0660 .delay (10000,10000,10000) L_0x24a0660/d; -L_0x24a07a0/d .functor NAND 1, L_0x24a0da0, L_0x249ef50, L_0x249f990, C4<1>; -L_0x24a07a0 .delay (10000,10000,10000) L_0x24a07a0/d; -L_0x24a0890/d .functor NAND 1, L_0x249eeb0, L_0x249f7c0, L_0x249fa30, C4<1>; -L_0x24a0890 .delay (10000,10000,10000) L_0x24a0890/d; -L_0x24a0980/d .functor NAND 1, L_0x24a0da0, L_0x249f7c0, L_0x249fb20, C4<1>; -L_0x24a0980 .delay (10000,10000,10000) L_0x24a0980/d; -L_0x24a0af0/d .functor NAND 1, L_0x24a0660, L_0x24a07a0, L_0x24a0890, L_0x24a0980; -L_0x24a0af0 .delay (10000,10000,10000) L_0x24a0af0/d; -v0x2282e30_0 .net "S0", 0 0, L_0x24a0da0; 1 drivers -v0x2282ed0_0 .net "S1", 0 0, L_0x249f7c0; 1 drivers -v0x2282ba0_0 .net "in0", 0 0, L_0x249f8f0; 1 drivers -v0x2282c40_0 .net "in1", 0 0, L_0x249f990; 1 drivers -v0x2286530_0 .net "in2", 0 0, L_0x249fa30; 1 drivers -v0x22865d0_0 .net "in3", 0 0, L_0x249fb20; 1 drivers -v0x2286300_0 .net "nS0", 0 0, L_0x249eeb0; 1 drivers -v0x2285390_0 .net "nS1", 0 0, L_0x249ef50; 1 drivers -v0x2285410_0 .net "out", 0 0, L_0x24a0af0; 1 drivers -v0x2285100_0 .net "out0", 0 0, L_0x24a0660; 1 drivers -v0x22851a0_0 .net "out1", 0 0, L_0x24a07a0; 1 drivers -v0x2282640_0 .net "out2", 0 0, L_0x24a0890; 1 drivers -v0x2288f20_0 .net "out3", 0 0, L_0x24a0980; 1 drivers -S_0x227f4b0 .scope module, "TwoMux" "TwoInMux" 2 294, 2 8, S_0x227f740; - .timescale -9 -12; -L_0x249fc10/d .functor NOT 1, L_0x24a00c0, C4<0>, C4<0>, C4<0>; -L_0x249fc10 .delay (10000,10000,10000) L_0x249fc10/d; -L_0x249fd00/d .functor AND 1, L_0x24a0160, L_0x249fc10, C4<1>, C4<1>; -L_0x249fd00 .delay (20000,20000,20000) L_0x249fd00/d; -L_0x249fdf0/d .functor AND 1, L_0x24a0250, L_0x24a00c0, C4<1>, C4<1>; -L_0x249fdf0 .delay (20000,20000,20000) L_0x249fdf0/d; -L_0x249fee0/d .functor OR 1, L_0x249fd00, L_0x249fdf0, C4<0>, C4<0>; -L_0x249fee0 .delay (20000,20000,20000) L_0x249fee0/d; -v0x227c9d0_0 .net "S", 0 0, L_0x24a00c0; 1 drivers -v0x227ca70_0 .net "in0", 0 0, L_0x24a0160; 1 drivers -v0x2284be0_0 .net "in1", 0 0, L_0x24a0250; 1 drivers -v0x2284c80_0 .net "nS", 0 0, L_0x249fc10; 1 drivers -v0x2284660_0 .net "out0", 0 0, L_0x249fd00; 1 drivers -v0x2284700_0 .net "out1", 0 0, L_0x249fdf0; 1 drivers -v0x22833b0_0 .net "outfinal", 0 0, L_0x249fee0; 1 drivers -S_0x2273ef0 .scope generate, "muxbits[23]" "muxbits[23]" 2 290, 2 290, S_0x22690e0; - .timescale -9 -12; -P_0x22699d8 .param/l "i" 2 290, +C4<010111>; -L_0x24a2b20/d .functor OR 1, L_0x24a44f0, L_0x24a35e0, C4<0>, C4<0>; -L_0x24a2b20 .delay (20000,20000,20000) L_0x24a2b20/d; -v0x2280740_0 .net *"_s15", 0 0, L_0x24a44f0; 1 drivers -v0x2280400_0 .net *"_s16", 0 0, L_0x24a35e0; 1 drivers -S_0x227f220 .scope module, "ZeroMux" "FourInMux" 2 292, 2 24, S_0x2273ef0; - .timescale -9 -12; -L_0x24a0ed0/d .functor NOT 1, L_0x24a17a0, C4<0>, C4<0>, C4<0>; -L_0x24a0ed0 .delay (10000,10000,10000) L_0x24a0ed0/d; -L_0x24a0fc0/d .functor NOT 1, L_0x24a18d0, C4<0>, C4<0>, C4<0>; -L_0x24a0fc0 .delay (10000,10000,10000) L_0x24a0fc0/d; -L_0x24a1060/d .functor NAND 1, L_0x24a0ed0, L_0x24a0fc0, L_0x24a1a00, C4<1>; -L_0x24a1060 .delay (10000,10000,10000) L_0x24a1060/d; -L_0x24a11a0/d .functor NAND 1, L_0x24a17a0, L_0x24a0fc0, L_0x24a1aa0, C4<1>; -L_0x24a11a0 .delay (10000,10000,10000) L_0x24a11a0/d; -L_0x24a1290/d .functor NAND 1, L_0x24a0ed0, L_0x24a18d0, L_0x24a1b40, C4<1>; -L_0x24a1290 .delay (10000,10000,10000) L_0x24a1290/d; -L_0x24a1380/d .functor NAND 1, L_0x24a17a0, L_0x24a18d0, L_0x24a1c30, C4<1>; -L_0x24a1380 .delay (10000,10000,10000) L_0x24a1380/d; -L_0x24a14f0/d .functor NAND 1, L_0x24a1060, L_0x24a11a0, L_0x24a1290, L_0x24a1380; -L_0x24a14f0 .delay (10000,10000,10000) L_0x24a14f0/d; -v0x227ef90_0 .net "S0", 0 0, L_0x24a17a0; 1 drivers -v0x227f030_0 .net "S1", 0 0, L_0x24a18d0; 1 drivers -v0x227ea10_0 .net "in0", 0 0, L_0x24a1a00; 1 drivers -v0x227eab0_0 .net "in1", 0 0, L_0x24a1aa0; 1 drivers -v0x227d700_0 .net "in2", 0 0, L_0x24a1b40; 1 drivers -v0x227d7a0_0 .net "in3", 0 0, L_0x24a1c30; 1 drivers -v0x227d490_0 .net "nS0", 0 0, L_0x24a0ed0; 1 drivers -v0x227d1e0_0 .net "nS1", 0 0, L_0x24a0fc0; 1 drivers -v0x227d280_0 .net "out", 0 0, L_0x24a14f0; 1 drivers -v0x227cf50_0 .net "out0", 0 0, L_0x24a1060; 1 drivers -v0x227cff0_0 .net "out1", 0 0, L_0x24a11a0; 1 drivers -v0x2280930_0 .net "out2", 0 0, L_0x24a1290; 1 drivers -v0x22806a0_0 .net "out3", 0 0, L_0x24a1380; 1 drivers -S_0x2277590 .scope module, "OneMux" "FourInMux" 2 293, 2 24, S_0x2273ef0; - .timescale -9 -12; -L_0x24a2ce0/d .functor NOT 1, L_0x24a1e30, C4<0>, C4<0>, C4<0>; -L_0x24a2ce0 .delay (10000,10000,10000) L_0x24a2ce0/d; -L_0x24a2dd0/d .functor NOT 1, L_0x24a1f60, C4<0>, C4<0>, C4<0>; -L_0x24a2dd0 .delay (10000,10000,10000) L_0x24a2dd0/d; -L_0x24a2e70/d .functor NAND 1, L_0x24a2ce0, L_0x24a2dd0, L_0x24a2090, C4<1>; -L_0x24a2e70 .delay (10000,10000,10000) L_0x24a2e70/d; -L_0x24a2fb0/d .functor NAND 1, L_0x24a1e30, L_0x24a2dd0, L_0x24a2130, C4<1>; -L_0x24a2fb0 .delay (10000,10000,10000) L_0x24a2fb0/d; -L_0x24a30a0/d .functor NAND 1, L_0x24a2ce0, L_0x24a1f60, L_0x24a21d0, C4<1>; -L_0x24a30a0 .delay (10000,10000,10000) L_0x24a30a0/d; -L_0x24a31c0/d .functor NAND 1, L_0x24a1e30, L_0x24a1f60, L_0x24a22c0, C4<1>; -L_0x24a31c0 .delay (10000,10000,10000) L_0x24a31c0/d; -L_0x24a3330/d .functor NAND 1, L_0x24a2e70, L_0x24a2fb0, L_0x24a30a0, L_0x24a31c0; -L_0x24a3330 .delay (10000,10000,10000) L_0x24a3330/d; -v0x22778c0_0 .net "S0", 0 0, L_0x24a1e30; 1 drivers -v0x2277300_0 .net "S1", 0 0, L_0x24a1f60; 1 drivers -v0x2277380_0 .net "in0", 0 0, L_0x24a2090; 1 drivers -v0x227ace0_0 .net "in1", 0 0, L_0x24a2130; 1 drivers -v0x227ad80_0 .net "in2", 0 0, L_0x24a21d0; 1 drivers -v0x227aa50_0 .net "in3", 0 0, L_0x24a22c0; 1 drivers -v0x227aaf0_0 .net "nS0", 0 0, L_0x24a2ce0; 1 drivers -v0x227a7b0_0 .net "nS1", 0 0, L_0x24a2dd0; 1 drivers -v0x2279af0_0 .net "out", 0 0, L_0x24a3330; 1 drivers -v0x2279b90_0 .net "out0", 0 0, L_0x24a2e70; 1 drivers -v0x2279860_0 .net "out1", 0 0, L_0x24a2fb0; 1 drivers -v0x2279900_0 .net "out2", 0 0, L_0x24a30a0; 1 drivers -v0x2276e10_0 .net "out3", 0 0, L_0x24a31c0; 1 drivers -S_0x2273c60 .scope module, "TwoMux" "TwoInMux" 2 294, 2 8, S_0x2273ef0; - .timescale -9 -12; -L_0x227a830/d .functor NOT 1, L_0x24a2800, C4<0>, C4<0>, C4<0>; -L_0x227a830 .delay (10000,10000,10000) L_0x227a830/d; -L_0x24a2440/d .functor AND 1, L_0x24a28a0, L_0x227a830, C4<1>, C4<1>; -L_0x24a2440 .delay (20000,20000,20000) L_0x24a2440/d; -L_0x24a2530/d .functor AND 1, L_0x24a2990, L_0x24a2800, C4<1>, C4<1>; -L_0x24a2530 .delay (20000,20000,20000) L_0x24a2530/d; -L_0x24a2620/d .functor OR 1, L_0x24a2440, L_0x24a2530, C4<0>, C4<0>; -L_0x24a2620 .delay (20000,20000,20000) L_0x24a2620/d; -v0x22795d0_0 .net "S", 0 0, L_0x24a2800; 1 drivers -v0x2279670_0 .net "in0", 0 0, L_0x24a28a0; 1 drivers -v0x2279340_0 .net "in1", 0 0, L_0x24a2990; 1 drivers -v0x22793e0_0 .net "nS", 0 0, L_0x227a830; 1 drivers -v0x2278de0_0 .net "out0", 0 0, L_0x24a2440; 1 drivers -v0x2277ab0_0 .net "out1", 0 0, L_0x24a2530; 1 drivers -v0x2277820_0 .net "outfinal", 0 0, L_0x24a2620; 1 drivers -S_0x2260720 .scope generate, "muxbits[24]" "muxbits[24]" 2 290, 2 290, S_0x22690e0; - .timescale -9 -12; -P_0x23db138 .param/l "i" 2 290, +C4<011000>; -L_0x24a51b0/d .functor OR 1, L_0x24a52f0, L_0x24a5390, C4<0>, C4<0>; -L_0x24a51b0 .delay (20000,20000,20000) L_0x24a51b0/d; -v0x2274ea0_0 .net *"_s15", 0 0, L_0x24a52f0; 1 drivers -v0x2274b70_0 .net *"_s16", 0 0, L_0x24a5390; 1 drivers -S_0x226c110 .scope module, "ZeroMux" "FourInMux" 2 292, 2 24, S_0x2260720; - .timescale -9 -12; -L_0x24a36d0/d .functor NOT 1, L_0x24a3f70, C4<0>, C4<0>, C4<0>; -L_0x24a36d0 .delay (10000,10000,10000) L_0x24a36d0/d; -L_0x24a37c0/d .functor NOT 1, L_0x24a40a0, C4<0>, C4<0>, C4<0>; -L_0x24a37c0 .delay (10000,10000,10000) L_0x24a37c0/d; -L_0x24a3860/d .functor NAND 1, L_0x24a36d0, L_0x24a37c0, L_0x24a41d0, C4<1>; -L_0x24a3860 .delay (10000,10000,10000) L_0x24a3860/d; -L_0x24a39a0/d .functor NAND 1, L_0x24a3f70, L_0x24a37c0, L_0x24a4270, C4<1>; -L_0x24a39a0 .delay (10000,10000,10000) L_0x24a39a0/d; -L_0x24a3a90/d .functor NAND 1, L_0x24a36d0, L_0x24a40a0, L_0x24a4310, C4<1>; -L_0x24a3a90 .delay (10000,10000,10000) L_0x24a3a90/d; -L_0x24a3b80/d .functor NAND 1, L_0x24a3f70, L_0x24a40a0, L_0x24a4400, C4<1>; -L_0x24a3b80 .delay (10000,10000,10000) L_0x24a3b80/d; -L_0x24a3cc0/d .functor NAND 1, L_0x24a3860, L_0x24a39a0, L_0x24a3a90, L_0x24a3b80; -L_0x24a3cc0 .delay (10000,10000,10000) L_0x24a3cc0/d; -v0x226f530_0 .net "S0", 0 0, L_0x24a3f70; 1 drivers -v0x226f2a0_0 .net "S1", 0 0, L_0x24a40a0; 1 drivers -v0x226f340_0 .net "in0", 0 0, L_0x24a41d0; 1 drivers -v0x226e390_0 .net "in1", 0 0, L_0x24a4270; 1 drivers -v0x226e410_0 .net "in2", 0 0, L_0x24a4310; 1 drivers -v0x226e100_0 .net "in3", 0 0, L_0x24a4400; 1 drivers -v0x226e1a0_0 .net "nS0", 0 0, L_0x24a36d0; 1 drivers -v0x2271f00_0 .net "nS1", 0 0, L_0x24a37c0; 1 drivers -v0x2271fa0_0 .net "out", 0 0, L_0x24a3cc0; 1 drivers -v0x2271c70_0 .net "out0", 0 0, L_0x24a3860; 1 drivers -v0x2271cf0_0 .net "out1", 0 0, L_0x24a39a0; 1 drivers -v0x2275090_0 .net "out2", 0 0, L_0x24a3a90; 1 drivers -v0x2274e00_0 .net "out3", 0 0, L_0x24a3b80; 1 drivers -S_0x22629f0 .scope module, "OneMux" "FourInMux" 2 293, 2 24, S_0x2260720; - .timescale -9 -12; -L_0x24a2c60/d .functor NOT 1, L_0x24a5d60, C4<0>, C4<0>, C4<0>; -L_0x24a2c60 .delay (10000,10000,10000) L_0x24a2c60/d; -L_0x24a5580/d .functor NOT 1, L_0x24a4590, C4<0>, C4<0>, C4<0>; -L_0x24a5580 .delay (10000,10000,10000) L_0x24a5580/d; -L_0x24a5620/d .functor NAND 1, L_0x24a2c60, L_0x24a5580, L_0x24a46c0, C4<1>; -L_0x24a5620 .delay (10000,10000,10000) L_0x24a5620/d; -L_0x24a5760/d .functor NAND 1, L_0x24a5d60, L_0x24a5580, L_0x24a4760, C4<1>; -L_0x24a5760 .delay (10000,10000,10000) L_0x24a5760/d; -L_0x24a5850/d .functor NAND 1, L_0x24a2c60, L_0x24a4590, L_0x24a4800, C4<1>; -L_0x24a5850 .delay (10000,10000,10000) L_0x24a5850/d; -L_0x24a5940/d .functor NAND 1, L_0x24a5d60, L_0x24a4590, L_0x24a48f0, C4<1>; -L_0x24a5940 .delay (10000,10000,10000) L_0x24a5940/d; -L_0x24a5ab0/d .functor NAND 1, L_0x24a5620, L_0x24a5760, L_0x24a5850, L_0x24a5940; -L_0x24a5ab0 .delay (10000,10000,10000) L_0x24a5ab0/d; -v0x225ff10_0 .net "S0", 0 0, L_0x24a5d60; 1 drivers -v0x225ffb0_0 .net "S1", 0 0, L_0x24a4590; 1 drivers -v0x2266840_0 .net "in0", 0 0, L_0x24a46c0; 1 drivers -v0x22668e0_0 .net "in1", 0 0, L_0x24a4760; 1 drivers -v0x22665b0_0 .net "in2", 0 0, L_0x24a4800; 1 drivers -v0x2266650_0 .net "in3", 0 0, L_0x24a48f0; 1 drivers -v0x2269a30_0 .net "nS0", 0 0, L_0x24a2c60; 1 drivers -v0x2269740_0 .net "nS1", 0 0, L_0x24a5580; 1 drivers -v0x22697c0_0 .net "out", 0 0, L_0x24a5ab0; 1 drivers -v0x2268830_0 .net "out0", 0 0, L_0x24a5620; 1 drivers -v0x22688d0_0 .net "out1", 0 0, L_0x24a5760; 1 drivers -v0x22685c0_0 .net "out2", 0 0, L_0x24a5850; 1 drivers -v0x226c3c0_0 .net "out3", 0 0, L_0x24a5940; 1 drivers -S_0x2260490 .scope module, "TwoMux" "TwoInMux" 2 294, 2 8, S_0x2260720; - .timescale -9 -12; -L_0x24a49e0/d .functor NOT 1, L_0x24a4e90, C4<0>, C4<0>, C4<0>; -L_0x24a49e0 .delay (10000,10000,10000) L_0x24a49e0/d; -L_0x24a4ad0/d .functor AND 1, L_0x24a4f30, L_0x24a49e0, C4<1>, C4<1>; -L_0x24a4ad0 .delay (20000,20000,20000) L_0x24a4ad0/d; -L_0x24a4bc0/d .functor AND 1, L_0x24a5020, L_0x24a4e90, C4<1>, C4<1>; -L_0x24a4bc0 .delay (20000,20000,20000) L_0x24a4bc0/d; -L_0x24a4cb0/d .functor OR 1, L_0x24a4ad0, L_0x24a4bc0, C4<0>, C4<0>; -L_0x24a4cb0 .delay (20000,20000,20000) L_0x24a4cb0/d; -v0x2263e70_0 .net "S", 0 0, L_0x24a4e90; 1 drivers -v0x2263f10_0 .net "in0", 0 0, L_0x24a4f30; 1 drivers -v0x2263be0_0 .net "in1", 0 0, L_0x24a5020; 1 drivers -v0x2263c80_0 .net "nS", 0 0, L_0x24a49e0; 1 drivers -v0x2263920_0 .net "out0", 0 0, L_0x24a4ad0; 1 drivers -v0x22639c0_0 .net "out1", 0 0, L_0x24a4bc0; 1 drivers -v0x2262ce0_0 .net "outfinal", 0 0, L_0x24a4cb0; 1 drivers -S_0x23d9a20 .scope generate, "muxbits[25]" "muxbits[25]" 2 290, 2 290, S_0x22690e0; - .timescale -9 -12; -P_0x23ce0d8 .param/l "i" 2 290, +C4<011001>; -L_0x24a80c0/d .functor OR 1, L_0x24a8200, L_0x24a82a0, C4<0>, C4<0>; -L_0x24a80c0 .delay (20000,20000,20000) L_0x24a80c0/d; -v0x2260ce0_0 .net *"_s15", 0 0, L_0x24a8200; 1 drivers -v0x22609d0_0 .net *"_s16", 0 0, L_0x24a82a0; 1 drivers -S_0x225e1e0 .scope module, "ZeroMux" "FourInMux" 2 292, 2 24, S_0x23d9a20; - .timescale -9 -12; -L_0x24a5480/d .functor NOT 1, L_0x24a76a0, C4<0>, C4<0>, C4<0>; -L_0x24a5480 .delay (10000,10000,10000) L_0x24a5480/d; -L_0x24a6ef0/d .functor NOT 1, L_0x24a5e90, C4<0>, C4<0>, C4<0>; -L_0x24a6ef0 .delay (10000,10000,10000) L_0x24a6ef0/d; -L_0x24a6f90/d .functor NAND 1, L_0x24a5480, L_0x24a6ef0, L_0x24a5fc0, C4<1>; -L_0x24a6f90 .delay (10000,10000,10000) L_0x24a6f90/d; -L_0x24a70d0/d .functor NAND 1, L_0x24a76a0, L_0x24a6ef0, L_0x24a6060, C4<1>; -L_0x24a70d0 .delay (10000,10000,10000) L_0x24a70d0/d; -L_0x24a71c0/d .functor NAND 1, L_0x24a5480, L_0x24a5e90, L_0x24a6100, C4<1>; -L_0x24a71c0 .delay (10000,10000,10000) L_0x24a71c0/d; -L_0x24a72b0/d .functor NAND 1, L_0x24a76a0, L_0x24a5e90, L_0x24a61f0, C4<1>; -L_0x24a72b0 .delay (10000,10000,10000) L_0x24a72b0/d; -L_0x24a73f0/d .functor NAND 1, L_0x24a6f90, L_0x24a70d0, L_0x24a71c0, L_0x24a72b0; -L_0x24a73f0 .delay (10000,10000,10000) L_0x24a73f0/d; -v0x225df50_0 .net "S0", 0 0, L_0x24a76a0; 1 drivers -v0x225dff0_0 .net "S1", 0 0, L_0x24a5e90; 1 drivers -v0x225cfb0_0 .net "in0", 0 0, L_0x24a5fc0; 1 drivers -v0x225d050_0 .net "in1", 0 0, L_0x24a6060; 1 drivers -v0x225cd20_0 .net "in2", 0 0, L_0x24a6100; 1 drivers -v0x225cdc0_0 .net "in3", 0 0, L_0x24a61f0; 1 drivers -v0x225a190_0 .net "nS0", 0 0, L_0x24a5480; 1 drivers -v0x2262760_0 .net "nS1", 0 0, L_0x24a6ef0; 1 drivers -v0x2262800_0 .net "out", 0 0, L_0x24a73f0; 1 drivers -v0x22624d0_0 .net "out0", 0 0, L_0x24a6f90; 1 drivers -v0x2262570_0 .net "out1", 0 0, L_0x24a70d0; 1 drivers -v0x2261f50_0 .net "out2", 0 0, L_0x24a71c0; 1 drivers -v0x2260c40_0 .net "out3", 0 0, L_0x24a72b0; 1 drivers -S_0x23dd550 .scope module, "OneMux" "FourInMux" 2 293, 2 24, S_0x23d9a20; - .timescale -9 -12; -L_0x24a62e0/d .functor NOT 1, L_0x24a6ba0, C4<0>, C4<0>, C4<0>; -L_0x24a62e0 .delay (10000,10000,10000) L_0x24a62e0/d; -L_0x24a6390/d .functor NOT 1, L_0x24a6cd0, C4<0>, C4<0>, C4<0>; -L_0x24a6390 .delay (10000,10000,10000) L_0x24a6390/d; -L_0x24a6430/d .functor NAND 1, L_0x24a62e0, L_0x24a6390, L_0x24a87f0, C4<1>; -L_0x24a6430 .delay (10000,10000,10000) L_0x24a6430/d; -L_0x24a6570/d .functor NAND 1, L_0x24a6ba0, L_0x24a6390, L_0x24a8890, C4<1>; -L_0x24a6570 .delay (10000,10000,10000) L_0x24a6570/d; -L_0x24a6660/d .functor NAND 1, L_0x24a62e0, L_0x24a6cd0, L_0x24a77d0, C4<1>; -L_0x24a6660 .delay (10000,10000,10000) L_0x24a6660/d; -L_0x24a6780/d .functor NAND 1, L_0x24a6ba0, L_0x24a6cd0, L_0x24a78c0, C4<1>; -L_0x24a6780 .delay (10000,10000,10000) L_0x24a6780/d; -L_0x24a68f0/d .functor NAND 1, L_0x24a6430, L_0x24a6570, L_0x24a6660, L_0x24a6780; -L_0x24a68f0 .delay (10000,10000,10000) L_0x24a68f0/d; -v0x23de4c0_0 .net "S0", 0 0, L_0x24a6ba0; 1 drivers -v0x225ca90_0 .net "S1", 0 0, L_0x24a6cd0; 1 drivers -v0x225cb10_0 .net "in0", 0 0, L_0x24a87f0; 1 drivers -v0x225c7d0_0 .net "in1", 0 0, L_0x24a8890; 1 drivers -v0x225c870_0 .net "in2", 0 0, L_0x24a77d0; 1 drivers -v0x225c250_0 .net "in3", 0 0, L_0x24a78c0; 1 drivers -v0x225c2f0_0 .net "nS0", 0 0, L_0x24a62e0; 1 drivers -v0x225af20_0 .net "nS1", 0 0, L_0x24a6390; 1 drivers -v0x225ac40_0 .net "out", 0 0, L_0x24a68f0; 1 drivers -v0x225ace0_0 .net "out0", 0 0, L_0x24a6430; 1 drivers -v0x225a9b0_0 .net "out1", 0 0, L_0x24a6570; 1 drivers -v0x225aa50_0 .net "out2", 0 0, L_0x24a6660; 1 drivers -v0x225a780_0 .net "out3", 0 0, L_0x24a6780; 1 drivers -S_0x23d8b50 .scope module, "TwoMux" "TwoInMux" 2 294, 2 8, S_0x23d9a20; - .timescale -9 -12; -L_0x24a6e00/d .functor NOT 1, L_0x24a7da0, C4<0>, C4<0>, C4<0>; -L_0x24a6e00 .delay (10000,10000,10000) L_0x24a6e00/d; -L_0x225afa0/d .functor AND 1, L_0x24a7e40, L_0x24a6e00, C4<1>, C4<1>; -L_0x225afa0 .delay (20000,20000,20000) L_0x225afa0/d; -L_0x24a7ad0/d .functor AND 1, L_0x24a7f30, L_0x24a7da0, C4<1>, C4<1>; -L_0x24a7ad0 .delay (20000,20000,20000) L_0x24a7ad0/d; -L_0x24a7bc0/d .functor OR 1, L_0x225afa0, L_0x24a7ad0, C4<0>, C4<0>; -L_0x24a7bc0 .delay (20000,20000,20000) L_0x24a7bc0/d; -v0x23dc1a0_0 .net "S", 0 0, L_0x24a7da0; 1 drivers -v0x23dc240_0 .net "in0", 0 0, L_0x24a7e40; 1 drivers -v0x23dbf20_0 .net "in1", 0 0, L_0x24a7f30; 1 drivers -v0x23dbfc0_0 .net "nS", 0 0, L_0x24a6e00; 1 drivers -v0x23db070_0 .net "out0", 0 0, L_0x225afa0; 1 drivers -v0x23de6a0_0 .net "out1", 0 0, L_0x24a7ad0; 1 drivers -v0x23de420_0 .net "outfinal", 0 0, L_0x24a7bc0; 1 drivers -S_0x23c7420 .scope generate, "muxbits[26]" "muxbits[26]" 2 290, 2 290, S_0x22690e0; - .timescale -9 -12; -P_0x23b7208 .param/l "i" 2 290, +C4<011010>; -L_0x24aa7a0/d .functor OR 1, L_0x24aa8e0, L_0x24aa980, C4<0>, C4<0>; -L_0x24aa7a0 .delay (20000,20000,20000) L_0x24aa7a0/d; -v0x23d66c0_0 .net *"_s15", 0 0, L_0x24aa8e0; 1 drivers -v0x23d9ca0_0 .net *"_s16", 0 0, L_0x24aa980; 1 drivers -S_0x23d2d70 .scope module, "ZeroMux" "FourInMux" 2 292, 2 24, S_0x23c7420; - .timescale -9 -12; -L_0x24a8390/d .functor NOT 1, L_0x24a8930, C4<0>, C4<0>, C4<0>; -L_0x24a8390 .delay (10000,10000,10000) L_0x24a8390/d; -L_0x24a8480/d .functor NOT 1, L_0x24a8a60, C4<0>, C4<0>, C4<0>; -L_0x24a8480 .delay (10000,10000,10000) L_0x24a8480/d; -L_0x24a8520/d .functor NAND 1, L_0x24a8390, L_0x24a8480, L_0x24a8b90, C4<1>; -L_0x24a8520 .delay (10000,10000,10000) L_0x24a8520/d; -L_0x24a8660/d .functor NAND 1, L_0x24a8930, L_0x24a8480, L_0x24a8c30, C4<1>; -L_0x24a8660 .delay (10000,10000,10000) L_0x24a8660/d; -L_0x24a8750/d .functor NAND 1, L_0x24a8390, L_0x24a8a60, L_0x24a8cd0, C4<1>; -L_0x24a8750 .delay (10000,10000,10000) L_0x24a8750/d; -L_0x24a99f0/d .functor NAND 1, L_0x24a8930, L_0x24a8a60, L_0x24a8dc0, C4<1>; -L_0x24a99f0 .delay (10000,10000,10000) L_0x24a99f0/d; -L_0x24a9b30/d .functor NAND 1, L_0x24a8520, L_0x24a8660, L_0x24a8750, L_0x24a99f0; -L_0x24a9b30 .delay (10000,10000,10000) L_0x24a9b30/d; -v0x23d2af0_0 .net "S0", 0 0, L_0x24a8930; 1 drivers -v0x23d1c00_0 .net "S1", 0 0, L_0x24a8a60; 1 drivers -v0x23d1ca0_0 .net "in0", 0 0, L_0x24a8b90; 1 drivers -v0x23d5280_0 .net "in1", 0 0, L_0x24a8c30; 1 drivers -v0x23d5300_0 .net "in2", 0 0, L_0x24a8cd0; 1 drivers -v0x23d5000_0 .net "in3", 0 0, L_0x24a8dc0; 1 drivers -v0x23d50a0_0 .net "nS0", 0 0, L_0x24a8390; 1 drivers -v0x23d4110_0 .net "nS1", 0 0, L_0x24a8480; 1 drivers -v0x23d41b0_0 .net "out", 0 0, L_0x24a9b30; 1 drivers -v0x23d77a0_0 .net "out0", 0 0, L_0x24a8520; 1 drivers -v0x23d7820_0 .net "out1", 0 0, L_0x24a8660; 1 drivers -v0x23d7520_0 .net "out2", 0 0, L_0x24a8750; 1 drivers -v0x23d6620_0 .net "out3", 0 0, L_0x24a99f0; 1 drivers -S_0x23cbe40 .scope module, "OneMux" "FourInMux" 2 293, 2 24, S_0x23c7420; - .timescale -9 -12; -L_0x24a8eb0/d .functor NOT 1, L_0x24a9780, C4<0>, C4<0>, C4<0>; -L_0x24a8eb0 .delay (10000,10000,10000) L_0x24a8eb0/d; -L_0x24a8fa0/d .functor NOT 1, L_0x24a98b0, C4<0>, C4<0>, C4<0>; -L_0x24a8fa0 .delay (10000,10000,10000) L_0x24a8fa0/d; -L_0x24a9040/d .functor NAND 1, L_0x24a8eb0, L_0x24a8fa0, L_0x24aaf30, C4<1>; -L_0x24a9040 .delay (10000,10000,10000) L_0x24a9040/d; -L_0x24a9180/d .functor NAND 1, L_0x24a9780, L_0x24a8fa0, L_0x24a9de0, C4<1>; -L_0x24a9180 .delay (10000,10000,10000) L_0x24a9180/d; -L_0x24a9270/d .functor NAND 1, L_0x24a8eb0, L_0x24a98b0, L_0x24a9e80, C4<1>; -L_0x24a9270 .delay (10000,10000,10000) L_0x24a9270/d; -L_0x24a9360/d .functor NAND 1, L_0x24a9780, L_0x24a98b0, L_0x24a9f20, C4<1>; -L_0x24a9360 .delay (10000,10000,10000) L_0x24a9360/d; -L_0x24a94d0/d .functor NAND 1, L_0x24a9040, L_0x24a9180, L_0x24a9270, L_0x24a9360; -L_0x24a94d0 .delay (10000,10000,10000) L_0x24a94d0/d; -v0x23cbbc0_0 .net "S0", 0 0, L_0x24a9780; 1 drivers -v0x23cbc60_0 .net "S1", 0 0, L_0x24a98b0; 1 drivers -v0x23cacd0_0 .net "in0", 0 0, L_0x24aaf30; 1 drivers -v0x23cad70_0 .net "in1", 0 0, L_0x24a9de0; 1 drivers -v0x23ce350_0 .net "in2", 0 0, L_0x24a9e80; 1 drivers -v0x23ce3f0_0 .net "in3", 0 0, L_0x24a9f20; 1 drivers -v0x23ce130_0 .net "nS0", 0 0, L_0x24a8eb0; 1 drivers -v0x23cd1e0_0 .net "nS1", 0 0, L_0x24a8fa0; 1 drivers -v0x23cd260_0 .net "out", 0 0, L_0x24a94d0; 1 drivers -v0x23d0860_0 .net "out0", 0 0, L_0x24a9040; 1 drivers -v0x23d0900_0 .net "out1", 0 0, L_0x24a9180; 1 drivers -v0x23d0600_0 .net "out2", 0 0, L_0x24a9270; 1 drivers -v0x23cf710_0 .net "out3", 0 0, L_0x24a9360; 1 drivers -S_0x23c71a0 .scope module, "TwoMux" "TwoInMux" 2 294, 2 8, S_0x23c7420; - .timescale -9 -12; -L_0x24aa010/d .functor NOT 1, L_0x24aa480, C4<0>, C4<0>, C4<0>; -L_0x24aa010 .delay (10000,10000,10000) L_0x24aa010/d; -L_0x24aa0c0/d .functor AND 1, L_0x24aa520, L_0x24aa010, C4<1>, C4<1>; -L_0x24aa0c0 .delay (20000,20000,20000) L_0x24aa0c0/d; -L_0x24aa1b0/d .functor AND 1, L_0x24aa610, L_0x24aa480, C4<1>, C4<1>; -L_0x24aa1b0 .delay (20000,20000,20000) L_0x24aa1b0/d; -L_0x24aa2a0/d .functor OR 1, L_0x24aa0c0, L_0x24aa1b0, C4<0>, C4<0>; -L_0x24aa2a0 .delay (20000,20000,20000) L_0x24aa2a0/d; -v0x23c62d0_0 .net "S", 0 0, L_0x24aa480; 1 drivers -v0x23c6370_0 .net "in0", 0 0, L_0x24aa520; 1 drivers -v0x23c9930_0 .net "in1", 0 0, L_0x24aa610; 1 drivers -v0x23c99d0_0 .net "nS", 0 0, L_0x24aa010; 1 drivers -v0x23c96b0_0 .net "out0", 0 0, L_0x24aa0c0; 1 drivers -v0x23c9750_0 .net "out1", 0 0, L_0x24aa1b0; 1 drivers -v0x23c8820_0 .net "outfinal", 0 0, L_0x24aa2a0; 1 drivers -S_0x23b1590 .scope generate, "muxbits[27]" "muxbits[27]" 2 290, 2 290, S_0x22690e0; - .timescale -9 -12; -P_0x23a5c68 .param/l "i" 2 290, +C4<011011>; -L_0x24ace00/d .functor OR 1, L_0x24acf40, L_0x24acfe0, C4<0>, C4<0>; -L_0x24ace00 .delay (20000,20000,20000) L_0x24ace00/d; -v0x23c4d40_0 .net *"_s15", 0 0, L_0x24acf40; 1 drivers -v0x23c3df0_0 .net *"_s16", 0 0, L_0x24acfe0; 1 drivers -S_0x23bced0 .scope module, "ZeroMux" "FourInMux" 2 292, 2 24, S_0x23b1590; - .timescale -9 -12; -L_0x24aaa70/d .functor NOT 1, L_0x24ac5a0, C4<0>, C4<0>, C4<0>; -L_0x24aaa70 .delay (10000,10000,10000) L_0x24aaa70/d; -L_0x24aab60/d .functor NOT 1, L_0x24aafd0, C4<0>, C4<0>, C4<0>; -L_0x24aab60 .delay (10000,10000,10000) L_0x24aab60/d; -L_0x24aac00/d .functor NAND 1, L_0x24aaa70, L_0x24aab60, L_0x24ab100, C4<1>; -L_0x24aac00 .delay (10000,10000,10000) L_0x24aac00/d; -L_0x24aad40/d .functor NAND 1, L_0x24ac5a0, L_0x24aab60, L_0x24ab1a0, C4<1>; -L_0x24aad40 .delay (10000,10000,10000) L_0x24aad40/d; -L_0x24aae30/d .functor NAND 1, L_0x24aaa70, L_0x24aafd0, L_0x24ab240, C4<1>; -L_0x24aae30 .delay (10000,10000,10000) L_0x24aae30/d; -L_0x24ac180/d .functor NAND 1, L_0x24ac5a0, L_0x24aafd0, L_0x24ab330, C4<1>; -L_0x24ac180 .delay (10000,10000,10000) L_0x24ac180/d; -L_0x24ac2f0/d .functor NAND 1, L_0x24aac00, L_0x24aad40, L_0x24aae30, L_0x24ac180; -L_0x24ac2f0 .delay (10000,10000,10000) L_0x24ac2f0/d; -v0x23c0520_0 .net "S0", 0 0, L_0x24ac5a0; 1 drivers -v0x23c05c0_0 .net "S1", 0 0, L_0x24aafd0; 1 drivers -v0x23c02a0_0 .net "in0", 0 0, L_0x24ab100; 1 drivers -v0x23c0340_0 .net "in1", 0 0, L_0x24ab1a0; 1 drivers -v0x23bf3d0_0 .net "in2", 0 0, L_0x24ab240; 1 drivers -v0x23bf470_0 .net "in3", 0 0, L_0x24ab330; 1 drivers -v0x23c2a40_0 .net "nS0", 0 0, L_0x24aaa70; 1 drivers -v0x23c27a0_0 .net "nS1", 0 0, L_0x24aab60; 1 drivers -v0x23c2840_0 .net "out", 0 0, L_0x24ac2f0; 1 drivers -v0x23c18d0_0 .net "out0", 0 0, L_0x24aac00; 1 drivers -v0x23c1970_0 .net "out1", 0 0, L_0x24aad40; 1 drivers -v0x23c4f20_0 .net "out2", 0 0, L_0x24aae30; 1 drivers -v0x23c4ca0_0 .net "out3", 0 0, L_0x24ac180; 1 drivers -S_0x23b9620 .scope module, "OneMux" "FourInMux" 2 293, 2 24, S_0x23b1590; - .timescale -9 -12; -L_0x24ab420/d .functor NOT 1, L_0x24abce0, C4<0>, C4<0>, C4<0>; -L_0x24ab420 .delay (10000,10000,10000) L_0x24ab420/d; -L_0x24ab4d0/d .functor NOT 1, L_0x24abe10, C4<0>, C4<0>, C4<0>; -L_0x24ab4d0 .delay (10000,10000,10000) L_0x24ab4d0/d; -L_0x24ab570/d .functor NAND 1, L_0x24ab420, L_0x24ab4d0, L_0x24abf40, C4<1>; -L_0x24ab570 .delay (10000,10000,10000) L_0x24ab570/d; -L_0x24ab6b0/d .functor NAND 1, L_0x24abce0, L_0x24ab4d0, L_0x24abfe0, C4<1>; -L_0x24ab6b0 .delay (10000,10000,10000) L_0x24ab6b0/d; -L_0x24ab7a0/d .functor NAND 1, L_0x24ab420, L_0x24abe10, L_0x24ad850, C4<1>; -L_0x24ab7a0 .delay (10000,10000,10000) L_0x24ab7a0/d; -L_0x24ab8c0/d .functor NAND 1, L_0x24abce0, L_0x24abe10, L_0x24ad8f0, C4<1>; -L_0x24ab8c0 .delay (10000,10000,10000) L_0x24ab8c0/d; -L_0x24aba30/d .functor NAND 1, L_0x24ab570, L_0x24ab6b0, L_0x24ab7a0, L_0x24ab8c0; -L_0x24aba30 .delay (10000,10000,10000) L_0x24aba30/d; -v0x23b6050_0 .net "S0", 0 0, L_0x24abce0; 1 drivers -v0x23b93a0_0 .net "S1", 0 0, L_0x24abe10; 1 drivers -v0x23b9420_0 .net "in0", 0 0, L_0x24abf40; 1 drivers -v0x23b84d0_0 .net "in1", 0 0, L_0x24abfe0; 1 drivers -v0x23b8570_0 .net "in2", 0 0, L_0x24ad850; 1 drivers -v0x23bbb20_0 .net "in3", 0 0, L_0x24ad8f0; 1 drivers -v0x23bbbc0_0 .net "nS0", 0 0, L_0x24ab420; 1 drivers -v0x23bb8c0_0 .net "nS1", 0 0, L_0x24ab4d0; 1 drivers -v0x23ba9d0_0 .net "out", 0 0, L_0x24aba30; 1 drivers -v0x23baa70_0 .net "out0", 0 0, L_0x24ab570; 1 drivers -v0x23be020_0 .net "out1", 0 0, L_0x24ab6b0; 1 drivers -v0x23be0c0_0 .net "out2", 0 0, L_0x24ab7a0; 1 drivers -v0x23bde30_0 .net "out3", 0 0, L_0x24ab8c0; 1 drivers -S_0x23b4c10 .scope module, "TwoMux" "TwoInMux" 2 294, 2 8, S_0x23b1590; - .timescale -9 -12; -L_0x23bb940/d .functor NOT 1, L_0x24acae0, C4<0>, C4<0>, C4<0>; -L_0x23bb940 .delay (10000,10000,10000) L_0x23bb940/d; -L_0x24ac720/d .functor AND 1, L_0x24acb80, L_0x23bb940, C4<1>, C4<1>; -L_0x24ac720 .delay (20000,20000,20000) L_0x24ac720/d; -L_0x24ac810/d .functor AND 1, L_0x24acc70, L_0x24acae0, C4<1>, C4<1>; -L_0x24ac810 .delay (20000,20000,20000) L_0x24ac810/d; -L_0x24ac900/d .functor OR 1, L_0x24ac720, L_0x24ac810, C4<0>, C4<0>; -L_0x24ac900 .delay (20000,20000,20000) L_0x24ac900/d; -v0x23b4990_0 .net "S", 0 0, L_0x24acae0; 1 drivers -v0x23b4a30_0 .net "in0", 0 0, L_0x24acb80; 1 drivers -v0x23b3aa0_0 .net "in1", 0 0, L_0x24acc70; 1 drivers -v0x23b3b40_0 .net "nS", 0 0, L_0x23bb940; 1 drivers -v0x23b7140_0 .net "out0", 0 0, L_0x24ac720; 1 drivers -v0x23b6ea0_0 .net "out1", 0 0, L_0x24ac810; 1 drivers -v0x23b5fb0_0 .net "outfinal", 0 0, L_0x24ac900; 1 drivers -S_0x239fc30 .scope generate, "muxbits[28]" "muxbits[28]" 2 290, 2 290, S_0x22690e0; - .timescale -9 -12; -P_0x23927e8 .param/l "i" 2 290, +C4<011100>; -L_0x24af5a0/d .functor OR 1, L_0x24af6e0, L_0x24af780, C4<0>, C4<0>; -L_0x24af5a0 .delay (20000,20000,20000) L_0x24af5a0/d; -v0x23b27a0_0 .net *"_s15", 0 0, L_0x24af6e0; 1 drivers -v0x23b2480_0 .net *"_s16", 0 0, L_0x24af780; 1 drivers -S_0x23ab550 .scope module, "ZeroMux" "FourInMux" 2 292, 2 24, S_0x239fc30; - .timescale -9 -12; -L_0x24ad0d0/d .functor NOT 1, L_0x24ad9e0, C4<0>, C4<0>, C4<0>; -L_0x24ad0d0 .delay (10000,10000,10000) L_0x24ad0d0/d; -L_0x24ad1c0/d .functor NOT 1, L_0x24adb10, C4<0>, C4<0>, C4<0>; -L_0x24ad1c0 .delay (10000,10000,10000) L_0x24ad1c0/d; -L_0x24ad260/d .functor NAND 1, L_0x24ad0d0, L_0x24ad1c0, L_0x24adc40, C4<1>; -L_0x24ad260 .delay (10000,10000,10000) L_0x24ad260/d; -L_0x24ad3a0/d .functor NAND 1, L_0x24ad9e0, L_0x24ad1c0, L_0x24adce0, C4<1>; -L_0x24ad3a0 .delay (10000,10000,10000) L_0x24ad3a0/d; -L_0x24ad490/d .functor NAND 1, L_0x24ad0d0, L_0x24adb10, L_0x24add80, C4<1>; -L_0x24ad490 .delay (10000,10000,10000) L_0x24ad490/d; -L_0x24ad5e0/d .functor NAND 1, L_0x24ad9e0, L_0x24adb10, L_0x24ade70, C4<1>; -L_0x24ad5e0 .delay (10000,10000,10000) L_0x24ad5e0/d; -L_0x24ad720/d .functor NAND 1, L_0x24ad260, L_0x24ad3a0, L_0x24ad490, L_0x24ad5e0; -L_0x24ad720 .delay (10000,10000,10000) L_0x24ad720/d; -v0x23aa660_0 .net "S0", 0 0, L_0x24ad9e0; 1 drivers -v0x23adce0_0 .net "S1", 0 0, L_0x24adb10; 1 drivers -v0x23add80_0 .net "in0", 0 0, L_0x24adc40; 1 drivers -v0x23ada60_0 .net "in1", 0 0, L_0x24adce0; 1 drivers -v0x23adae0_0 .net "in2", 0 0, L_0x24add80; 1 drivers -v0x23acb70_0 .net "in3", 0 0, L_0x24ade70; 1 drivers -v0x23acc10_0 .net "nS0", 0 0, L_0x24ad0d0; 1 drivers -v0x23b01f0_0 .net "nS1", 0 0, L_0x24ad1c0; 1 drivers -v0x23b0290_0 .net "out", 0 0, L_0x24ad720; 1 drivers -v0x23aff70_0 .net "out0", 0 0, L_0x24ad260; 1 drivers -v0x23afff0_0 .net "out1", 0 0, L_0x24ad3a0; 1 drivers -v0x23af080_0 .net "out2", 0 0, L_0x24ad490; 1 drivers -v0x23b2700_0 .net "out3", 0 0, L_0x24ad5e0; 1 drivers -S_0x23a4630 .scope module, "OneMux" "FourInMux" 2 293, 2 24, S_0x239fc30; - .timescale -9 -12; -L_0x24adf60/d .functor NOT 1, L_0x24ae830, C4<0>, C4<0>, C4<0>; -L_0x24adf60 .delay (10000,10000,10000) L_0x24adf60/d; -L_0x24ae050/d .functor NOT 1, L_0x24ae960, C4<0>, C4<0>, C4<0>; -L_0x24ae050 .delay (10000,10000,10000) L_0x24ae050/d; -L_0x24ae0f0/d .functor NAND 1, L_0x24adf60, L_0x24ae050, L_0x24aea90, C4<1>; -L_0x24ae0f0 .delay (10000,10000,10000) L_0x24ae0f0/d; -L_0x24ae230/d .functor NAND 1, L_0x24ae830, L_0x24ae050, L_0x24aff40, C4<1>; -L_0x24ae230 .delay (10000,10000,10000) L_0x24ae230/d; -L_0x24ae320/d .functor NAND 1, L_0x24adf60, L_0x24ae960, L_0x24affe0, C4<1>; -L_0x24ae320 .delay (10000,10000,10000) L_0x24ae320/d; -L_0x24ae410/d .functor NAND 1, L_0x24ae830, L_0x24ae960, L_0x24aed20, C4<1>; -L_0x24ae410 .delay (10000,10000,10000) L_0x24ae410/d; -L_0x24ae580/d .functor NAND 1, L_0x24ae0f0, L_0x24ae230, L_0x24ae320, L_0x24ae410; -L_0x24ae580 .delay (10000,10000,10000) L_0x24ae580/d; -v0x23a3760_0 .net "S0", 0 0, L_0x24ae830; 1 drivers -v0x23a3800_0 .net "S1", 0 0, L_0x24ae960; 1 drivers -v0x23a6db0_0 .net "in0", 0 0, L_0x24aea90; 1 drivers -v0x23a6e50_0 .net "in1", 0 0, L_0x24aff40; 1 drivers -v0x23a6b30_0 .net "in2", 0 0, L_0x24affe0; 1 drivers -v0x23a6bd0_0 .net "in3", 0 0, L_0x24aed20; 1 drivers -v0x23a5cc0_0 .net "nS0", 0 0, L_0x24adf60; 1 drivers -v0x23a92c0_0 .net "nS1", 0 0, L_0x24ae050; 1 drivers -v0x23a9340_0 .net "out", 0 0, L_0x24ae580; 1 drivers -v0x23a9040_0 .net "out0", 0 0, L_0x24ae0f0; 1 drivers -v0x23a90e0_0 .net "out1", 0 0, L_0x24ae230; 1 drivers -v0x23a8170_0 .net "out2", 0 0, L_0x24ae320; 1 drivers -v0x23ab7f0_0 .net "out3", 0 0, L_0x24ae410; 1 drivers -S_0x239ed60 .scope module, "TwoMux" "TwoInMux" 2 294, 2 8, S_0x239fc30; - .timescale -9 -12; -L_0x24aee10/d .functor NOT 1, L_0x24af280, C4<0>, C4<0>, C4<0>; -L_0x24aee10 .delay (10000,10000,10000) L_0x24aee10/d; -L_0x24aeec0/d .functor AND 1, L_0x24af320, L_0x24aee10, C4<1>, C4<1>; -L_0x24aeec0 .delay (20000,20000,20000) L_0x24aeec0/d; -L_0x24aefb0/d .functor AND 1, L_0x24af410, L_0x24af280, C4<1>, C4<1>; -L_0x24aefb0 .delay (20000,20000,20000) L_0x24aefb0/d; -L_0x24af0a0/d .functor OR 1, L_0x24aeec0, L_0x24aefb0, C4<0>, C4<0>; -L_0x24af0a0 .delay (20000,20000,20000) L_0x24af0a0/d; -v0x23a23b0_0 .net "S", 0 0, L_0x24af280; 1 drivers -v0x23a2450_0 .net "in0", 0 0, L_0x24af320; 1 drivers -v0x23a2130_0 .net "in1", 0 0, L_0x24af410; 1 drivers -v0x23a21d0_0 .net "nS", 0 0, L_0x24aee10; 1 drivers -v0x23a1260_0 .net "out0", 0 0, L_0x24aeec0; 1 drivers -v0x23a1300_0 .net "out1", 0 0, L_0x24aefb0; 1 drivers -v0x23a4910_0 .net "outfinal", 0 0, L_0x24af0a0; 1 drivers -S_0x23913c0 .scope generate, "muxbits[29]" "muxbits[29]" 2 290, 2 290, S_0x22690e0; - .timescale -9 -12; -P_0x23838a8 .param/l "i" 2 290, +C4<011101>; -L_0x24b18c0/d .functor OR 1, L_0x24b19c0, L_0x24b1a60, C4<0>, C4<0>; -L_0x24b18c0 .delay (20000,20000,20000) L_0x24b18c0/d; -v0x239c900_0 .net *"_s15", 0 0, L_0x24b19c0; 1 drivers -v0x239fed0_0 .net *"_s16", 0 0, L_0x24b1a60; 1 drivers -S_0x2398f40 .scope module, "ZeroMux" "FourInMux" 2 292, 2 24, S_0x23913c0; - .timescale -9 -12; -L_0x24af870/d .functor NOT 1, L_0x24b1510, C4<0>, C4<0>, C4<0>; -L_0x24af870 .delay (10000,10000,10000) L_0x24af870/d; -L_0x24af960/d .functor NOT 1, L_0x24b0080, C4<0>, C4<0>, C4<0>; -L_0x24af960 .delay (10000,10000,10000) L_0x24af960/d; -L_0x24afa00/d .functor NAND 1, L_0x24af870, L_0x24af960, L_0x24b01b0, C4<1>; -L_0x24afa00 .delay (10000,10000,10000) L_0x24afa00/d; -L_0x24afb40/d .functor NAND 1, L_0x24b1510, L_0x24af960, L_0x24b0250, C4<1>; -L_0x24afb40 .delay (10000,10000,10000) L_0x24afb40/d; -L_0x24afc30/d .functor NAND 1, L_0x24af870, L_0x24b0080, L_0x24b02f0, C4<1>; -L_0x24afc30 .delay (10000,10000,10000) L_0x24afc30/d; -L_0x24afd20/d .functor NAND 1, L_0x24b1510, L_0x24b0080, L_0x24b0390, C4<1>; -L_0x24afd20 .delay (10000,10000,10000) L_0x24afd20/d; -L_0x24afe90/d .functor NAND 1, L_0x24afa00, L_0x24afb40, L_0x24afc30, L_0x24afd20; -L_0x24afe90 .delay (10000,10000,10000) L_0x24afe90/d; -v0x2398c60_0 .net "S0", 0 0, L_0x24b1510; 1 drivers -v0x2398d00_0 .net "S1", 0 0, L_0x24b0080; 1 drivers -v0x2397db0_0 .net "in0", 0 0, L_0x24b01b0; 1 drivers -v0x2397e50_0 .net "in1", 0 0, L_0x24b0250; 1 drivers -v0x239b4b0_0 .net "in2", 0 0, L_0x24b02f0; 1 drivers -v0x239b550_0 .net "in3", 0 0, L_0x24b0390; 1 drivers -v0x239b250_0 .net "nS0", 0 0, L_0x24af870; 1 drivers -v0x239a330_0 .net "nS1", 0 0, L_0x24af960; 1 drivers -v0x239a3d0_0 .net "out", 0 0, L_0x24afe90; 1 drivers -v0x239d9b0_0 .net "out0", 0 0, L_0x24afa00; 1 drivers -v0x239da50_0 .net "out1", 0 0, L_0x24afb40; 1 drivers -v0x239d730_0 .net "out2", 0 0, L_0x24afc30; 1 drivers -v0x239c860_0 .net "out3", 0 0, L_0x24afd20; 1 drivers -S_0x2393cc0 .scope module, "OneMux" "FourInMux" 2 293, 2 24, S_0x23913c0; - .timescale -9 -12; -L_0x24b0480/d .functor NOT 1, L_0x24b0d70, C4<0>, C4<0>, C4<0>; -L_0x24b0480 .delay (10000,10000,10000) L_0x24b0480/d; -L_0x24b0530/d .functor NOT 1, L_0x24b0ea0, C4<0>, C4<0>, C4<0>; -L_0x24b0530 .delay (10000,10000,10000) L_0x24b0530/d; -L_0x24b05d0/d .functor NAND 1, L_0x24b0480, L_0x24b0530, L_0x24b0fd0, C4<1>; -L_0x24b05d0 .delay (10000,10000,10000) L_0x24b05d0/d; -L_0x24b0710/d .functor NAND 1, L_0x24b0d70, L_0x24b0530, L_0x24b1070, C4<1>; -L_0x24b0710 .delay (10000,10000,10000) L_0x24b0710/d; -L_0x24b0800/d .functor NAND 1, L_0x24b0480, L_0x24b0ea0, L_0x24b1110, C4<1>; -L_0x24b0800 .delay (10000,10000,10000) L_0x24b0800/d; -L_0x24b0950/d .functor NAND 1, L_0x24b0d70, L_0x24b0ea0, L_0x24b1200, C4<1>; -L_0x24b0950 .delay (10000,10000,10000) L_0x24b0950/d; -L_0x24b0ac0/d .functor NAND 1, L_0x24b05d0, L_0x24b0710, L_0x24b0800, L_0x24b0950; -L_0x24b0ac0 .delay (10000,10000,10000) L_0x24b0ac0/d; -v0x2393fe0_0 .net "S0", 0 0, L_0x24b0d70; 1 drivers -v0x23937c0_0 .net "S1", 0 0, L_0x24b0ea0; 1 drivers -v0x2393840_0 .net "in0", 0 0, L_0x24b0fd0; 1 drivers -v0x2395500_0 .net "in1", 0 0, L_0x24b1070; 1 drivers -v0x23955a0_0 .net "in2", 0 0, L_0x24b1110; 1 drivers -v0x2395280_0 .net "in3", 0 0, L_0x24b1200; 1 drivers -v0x2395320_0 .net "nS0", 0 0, L_0x24b0480; 1 drivers -v0x2394da0_0 .net "nS1", 0 0, L_0x24b0530; 1 drivers -v0x23e0b80_0 .net "out", 0 0, L_0x24b0ac0; 1 drivers -v0x23e0c20_0 .net "out0", 0 0, L_0x24b05d0; 1 drivers -v0x23e0910_0 .net "out1", 0 0, L_0x24b0710; 1 drivers -v0x23e09b0_0 .net "out2", 0 0, L_0x24b0800; 1 drivers -v0x23dfae0_0 .net "out3", 0 0, L_0x24b0950; 1 drivers -S_0x2391140 .scope module, "TwoMux" "TwoInMux" 2 294, 2 8, S_0x23913c0; - .timescale -9 -12; -L_0x24b2920/d .functor NOT 1, L_0x24b2dd0, C4<0>, C4<0>, C4<0>; -L_0x24b2920 .delay (10000,10000,10000) L_0x24b2920/d; -L_0x24b2a10/d .functor AND 1, L_0x24b1640, L_0x24b2920, C4<1>, C4<1>; -L_0x24b2a10 .delay (20000,20000,20000) L_0x24b2a10/d; -L_0x24b2b00/d .functor AND 1, L_0x24b1730, L_0x24b2dd0, C4<1>, C4<1>; -L_0x24b2b00 .delay (20000,20000,20000) L_0x24b2b00/d; -L_0x24b2bf0/d .functor OR 1, L_0x24b2a10, L_0x24b2b00, C4<0>, C4<0>; -L_0x24b2bf0 .delay (20000,20000,20000) L_0x24b2bf0/d; -v0x2390c40_0 .net "S", 0 0, L_0x24b2dd0; 1 drivers -v0x2390ce0_0 .net "in0", 0 0, L_0x24b1640; 1 drivers -v0x2392980_0 .net "in1", 0 0, L_0x24b1730; 1 drivers -v0x2392a20_0 .net "nS", 0 0, L_0x24b2920; 1 drivers -v0x2392720_0 .net "out0", 0 0, L_0x24b2a10; 1 drivers -v0x2392200_0 .net "out1", 0 0, L_0x24b2b00; 1 drivers -v0x2393f40_0 .net "outfinal", 0 0, L_0x24b2bf0; 1 drivers -S_0x2385000 .scope generate, "muxbits[30]" "muxbits[30]" 2 290, 2 290, S_0x22690e0; - .timescale -9 -12; -P_0x237a288 .param/l "i" 2 290, +C4<011110>; -L_0x24b43e0/d .functor OR 1, L_0x24b44e0, L_0x24b4580, C4<0>, C4<0>; -L_0x24b43e0 .delay (20000,20000,20000) L_0x24b43e0/d; -v0x238fc20_0 .net *"_s15", 0 0, L_0x24b44e0; 1 drivers -v0x238f680_0 .net *"_s16", 0 0, L_0x24b4580; 1 drivers -S_0x238b540 .scope module, "ZeroMux" "FourInMux" 2 292, 2 24, S_0x2385000; - .timescale -9 -12; -L_0x24b1b50/d .functor NOT 1, L_0x24b2420, C4<0>, C4<0>, C4<0>; -L_0x24b1b50 .delay (10000,10000,10000) L_0x24b1b50/d; -L_0x24b1c40/d .functor NOT 1, L_0x24b2550, C4<0>, C4<0>, C4<0>; -L_0x24b1c40 .delay (10000,10000,10000) L_0x24b1c40/d; -L_0x24b1ce0/d .functor NAND 1, L_0x24b1b50, L_0x24b1c40, L_0x24b2680, C4<1>; -L_0x24b1ce0 .delay (10000,10000,10000) L_0x24b1ce0/d; -L_0x24b1e20/d .functor NAND 1, L_0x24b2420, L_0x24b1c40, L_0x24b2720, C4<1>; -L_0x24b1e20 .delay (10000,10000,10000) L_0x24b1e20/d; -L_0x24b1f10/d .functor NAND 1, L_0x24b1b50, L_0x24b2550, L_0x24b27c0, C4<1>; -L_0x24b1f10 .delay (10000,10000,10000) L_0x24b1f10/d; -L_0x24b2030/d .functor NAND 1, L_0x24b2420, L_0x24b2550, L_0x24b41b0, C4<1>; -L_0x24b2030 .delay (10000,10000,10000) L_0x24b2030/d; -L_0x24b2170/d .functor NAND 1, L_0x24b1ce0, L_0x24b1e20, L_0x24b1f10, L_0x24b2030; -L_0x24b2170 .delay (10000,10000,10000) L_0x24b2170/d; -v0x238bae0_0 .net "S0", 0 0, L_0x24b2420; 1 drivers -v0x238d2a0_0 .net "S1", 0 0, L_0x24b2550; 1 drivers -v0x238d000_0 .net "in0", 0 0, L_0x24b2680; 1 drivers -v0x238d0a0_0 .net "in1", 0 0, L_0x24b2720; 1 drivers -v0x238cb00_0 .net "in2", 0 0, L_0x24b27c0; 1 drivers -v0x238cba0_0 .net "in3", 0 0, L_0x24b41b0; 1 drivers -v0x238e840_0 .net "nS0", 0 0, L_0x24b1b50; 1 drivers -v0x238e8c0_0 .net "nS1", 0 0, L_0x24b1c40; 1 drivers -v0x238e5c0_0 .net "out", 0 0, L_0x24b2170; 1 drivers -v0x238e660_0 .net "out0", 0 0, L_0x24b1ce0; 1 drivers -v0x238e0e0_0 .net "out1", 0 0, L_0x24b1e20; 1 drivers -v0x238fe00_0 .net "out2", 0 0, L_0x24b1f10; 1 drivers -v0x238fb80_0 .net "out3", 0 0, L_0x24b2030; 1 drivers -S_0x2389140 .scope module, "OneMux" "FourInMux" 2 293, 2 24, S_0x2385000; - .timescale -9 -12; -L_0x24b2090/d .functor NOT 1, L_0x24b3740, C4<0>, C4<0>, C4<0>; -L_0x24b2090 .delay (10000,10000,10000) L_0x24b2090/d; -L_0x24b2f00/d .functor NOT 1, L_0x24b3870, C4<0>, C4<0>, C4<0>; -L_0x24b2f00 .delay (10000,10000,10000) L_0x24b2f00/d; -L_0x24b2fa0/d .functor NAND 1, L_0x24b2090, L_0x24b2f00, L_0x24b39a0, C4<1>; -L_0x24b2fa0 .delay (10000,10000,10000) L_0x24b2fa0/d; -L_0x24b30e0/d .functor NAND 1, L_0x24b3740, L_0x24b2f00, L_0x24b3a40, C4<1>; -L_0x24b30e0 .delay (10000,10000,10000) L_0x24b30e0/d; -L_0x24b3200/d .functor NAND 1, L_0x24b2090, L_0x24b3870, L_0x24b3ae0, C4<1>; -L_0x24b3200 .delay (10000,10000,10000) L_0x24b3200/d; -L_0x24b3350/d .functor NAND 1, L_0x24b3740, L_0x24b3870, L_0x24b3bd0, C4<1>; -L_0x24b3350 .delay (10000,10000,10000) L_0x24b3350/d; -L_0x24b3490/d .functor NAND 1, L_0x24b2fa0, L_0x24b30e0, L_0x24b3200, L_0x24b3350; -L_0x24b3490 .delay (10000,10000,10000) L_0x24b3490/d; -v0x23874a0_0 .net "S0", 0 0, L_0x24b3740; 1 drivers -v0x2388ec0_0 .net "S1", 0 0, L_0x24b3870; 1 drivers -v0x2388f40_0 .net "in0", 0 0, L_0x24b39a0; 1 drivers -v0x23889c0_0 .net "in1", 0 0, L_0x24b3a40; 1 drivers -v0x2388a60_0 .net "in2", 0 0, L_0x24b3ae0; 1 drivers -v0x238a700_0 .net "in3", 0 0, L_0x24b3bd0; 1 drivers -v0x238a7a0_0 .net "nS0", 0 0, L_0x24b2090; 1 drivers -v0x238a480_0 .net "nS1", 0 0, L_0x24b2f00; 1 drivers -v0x238a520_0 .net "out", 0 0, L_0x24b3490; 1 drivers -v0x2389f80_0 .net "out0", 0 0, L_0x24b2fa0; 1 drivers -v0x238a000_0 .net "out1", 0 0, L_0x24b30e0; 1 drivers -v0x238bcc0_0 .net "out2", 0 0, L_0x24b3200; 1 drivers -v0x238ba40_0 .net "out3", 0 0, L_0x24b3350; 1 drivers -S_0x2384d60 .scope module, "TwoMux" "TwoInMux" 2 294, 2 8, S_0x2385000; - .timescale -9 -12; -L_0x24b3cc0/d .functor NOT 1, L_0x24b55e0, C4<0>, C4<0>, C4<0>; -L_0x24b3cc0 .delay (10000,10000,10000) L_0x24b3cc0/d; -L_0x24b3db0/d .functor AND 1, L_0x24b5680, L_0x24b3cc0, C4<1>, C4<1>; -L_0x24b3db0 .delay (20000,20000,20000) L_0x24b3db0/d; -L_0x24b3ea0/d .functor AND 1, L_0x24b4250, L_0x24b55e0, C4<1>, C4<1>; -L_0x24b3ea0 .delay (20000,20000,20000) L_0x24b3ea0/d; -L_0x24b3f90/d .functor OR 1, L_0x24b3db0, L_0x24b3ea0, C4<0>, C4<0>; -L_0x24b3f90 .delay (20000,20000,20000) L_0x24b3f90/d; -v0x23865c0_0 .net "S", 0 0, L_0x24b55e0; 1 drivers -v0x2386340_0 .net "in0", 0 0, L_0x24b5680; 1 drivers -v0x23863e0_0 .net "in1", 0 0, L_0x24b4250; 1 drivers -v0x2387b80_0 .net "nS", 0 0, L_0x24b3cc0; 1 drivers -v0x2387c00_0 .net "out0", 0 0, L_0x24b3db0; 1 drivers -v0x2387900_0 .net "out1", 0 0, L_0x24b3ea0; 1 drivers -v0x2387400_0 .net "outfinal", 0 0, L_0x24b3f90; 1 drivers -S_0x22747a0 .scope generate, "muxbits[31]" "muxbits[31]" 2 290, 2 290, S_0x22690e0; - .timescale -9 -12; -P_0x2165518 .param/l "i" 2 290, +C4<011111>; -L_0x24b6480/d .functor OR 1, L_0x24b65c0, L_0x24b6660, C4<0>, C4<0>; -L_0x24b6480 .delay (20000,20000,20000) L_0x24b6480/d; -v0x2383a60_0 .net *"_s15", 0 0, L_0x24b65c0; 1 drivers -v0x23837c0_0 .net *"_s16", 0 0, L_0x24b6660; 1 drivers -S_0x237e340 .scope module, "ZeroMux" "FourInMux" 2 292, 2 24, S_0x22747a0; - .timescale -9 -12; -L_0x24b4670/d .functor NOT 1, L_0x24b4f40, C4<0>, C4<0>, C4<0>; -L_0x24b4670 .delay (10000,10000,10000) L_0x24b4670/d; -L_0x24b4760/d .functor NOT 1, L_0x24b5070, C4<0>, C4<0>, C4<0>; -L_0x24b4760 .delay (10000,10000,10000) L_0x24b4760/d; -L_0x24b4800/d .functor NAND 1, L_0x24b4670, L_0x24b4760, L_0x24b51a0, C4<1>; -L_0x24b4800 .delay (10000,10000,10000) L_0x24b4800/d; -L_0x24b4940/d .functor NAND 1, L_0x24b4f40, L_0x24b4760, L_0x24b5240, C4<1>; -L_0x24b4940 .delay (10000,10000,10000) L_0x24b4940/d; -L_0x24b4a30/d .functor NAND 1, L_0x24b4670, L_0x24b5070, L_0x24b52e0, C4<1>; -L_0x24b4a30 .delay (10000,10000,10000) L_0x24b4a30/d; -L_0x24b4b20/d .functor NAND 1, L_0x24b4f40, L_0x24b5070, L_0x24b53d0, C4<1>; -L_0x24b4b20 .delay (10000,10000,10000) L_0x24b4b20/d; -L_0x24b4c90/d .functor NAND 1, L_0x24b4800, L_0x24b4940, L_0x24b4a30, L_0x24b4b20; -L_0x24b4c90 .delay (10000,10000,10000) L_0x24b4c90/d; -v0x237cb80_0 .net "S0", 0 0, L_0x24b4f40; 1 drivers -v0x237e0c0_0 .net "S1", 0 0, L_0x24b5070; 1 drivers -v0x237e160_0 .net "in0", 0 0, L_0x24b51a0; 1 drivers -v0x237f920_0 .net "in1", 0 0, L_0x24b5240; 1 drivers -v0x237f660_0 .net "in2", 0 0, L_0x24b52e0; 1 drivers -v0x237f700_0 .net "in3", 0 0, L_0x24b53d0; 1 drivers -v0x2380ec0_0 .net "nS0", 0 0, L_0x24b4670; 1 drivers -v0x2380f60_0 .net "nS1", 0 0, L_0x24b4760; 1 drivers -v0x2380c40_0 .net "out", 0 0, L_0x24b4c90; 1 drivers -v0x2380cc0_0 .net "out0", 0 0, L_0x24b4800; 1 drivers -v0x2382480_0 .net "out1", 0 0, L_0x24b4940; 1 drivers -v0x2382520_0 .net "out2", 0 0, L_0x24b4a30; 1 drivers -v0x2382270_0 .net "out3", 0 0, L_0x24b4b20; 1 drivers -S_0x23773d0 .scope module, "OneMux" "FourInMux" 2 293, 2 24, S_0x22747a0; - .timescale -9 -12; -L_0x24b54c0/d .functor NOT 1, L_0x24b5770, C4<0>, C4<0>, C4<0>; -L_0x24b54c0 .delay (10000,10000,10000) L_0x24b54c0/d; -L_0x24b6b60/d .functor NOT 1, L_0x24b58a0, C4<0>, C4<0>, C4<0>; -L_0x24b6b60 .delay (10000,10000,10000) L_0x24b6b60/d; -L_0x24b6c00/d .functor NAND 1, L_0x24b54c0, L_0x24b6b60, L_0x24b59d0, C4<1>; -L_0x24b6c00 .delay (10000,10000,10000) L_0x24b6c00/d; -L_0x24b6d40/d .functor NAND 1, L_0x24b5770, L_0x24b6b60, L_0x24b5a70, C4<1>; -L_0x24b6d40 .delay (10000,10000,10000) L_0x24b6d40/d; -L_0x24b6e30/d .functor NAND 1, L_0x24b54c0, L_0x24b58a0, L_0x24b5b10, C4<1>; -L_0x24b6e30 .delay (10000,10000,10000) L_0x24b6e30/d; -L_0x24b6f20/d .functor NAND 1, L_0x24b5770, L_0x24b58a0, L_0x24b5c00, C4<1>; -L_0x24b6f20 .delay (10000,10000,10000) L_0x24b6f20/d; -L_0x24b7090/d .functor NAND 1, L_0x24b6c00, L_0x24b6d40, L_0x24b6e30, L_0x24b6f20; -L_0x24b7090 .delay (10000,10000,10000) L_0x24b7090/d; -v0x2377720_0 .net "S0", 0 0, L_0x24b5770; 1 drivers -v0x2378c40_0 .net "S1", 0 0, L_0x24b58a0; 1 drivers -v0x2378cc0_0 .net "in0", 0 0, L_0x24b59d0; 1 drivers -v0x23789c0_0 .net "in1", 0 0, L_0x24b5a70; 1 drivers -v0x2378a60_0 .net "in2", 0 0, L_0x24b5b10; 1 drivers -v0x237a200_0 .net "in3", 0 0, L_0x24b5c00; 1 drivers -v0x2379f60_0 .net "nS0", 0 0, L_0x24b54c0; 1 drivers -v0x237a000_0 .net "nS1", 0 0, L_0x24b6b60; 1 drivers -v0x237b7c0_0 .net "out", 0 0, L_0x24b7090; 1 drivers -v0x237b840_0 .net "out0", 0 0, L_0x24b6c00; 1 drivers -v0x237b5a0_0 .net "out1", 0 0, L_0x24b6d40; 1 drivers -v0x237cd80_0 .net "out2", 0 0, L_0x24b6e30; 1 drivers -v0x237cae0_0 .net "out3", 0 0, L_0x24b6f20; 1 drivers -S_0x2285c40 .scope module, "TwoMux" "TwoInMux" 2 294, 2 8, S_0x22747a0; - .timescale -9 -12; -L_0x24b5cf0/d .functor NOT 1, L_0x24b6160, C4<0>, C4<0>, C4<0>; -L_0x24b5cf0 .delay (10000,10000,10000) L_0x24b5cf0/d; -L_0x24b5da0/d .functor AND 1, L_0x24b6200, L_0x24b5cf0, C4<1>, C4<1>; -L_0x24b5da0 .delay (20000,20000,20000) L_0x24b5da0/d; -L_0x24b5e90/d .functor AND 1, L_0x24b62f0, L_0x24b6160, C4<1>, C4<1>; -L_0x24b5e90 .delay (20000,20000,20000) L_0x24b5e90/d; -L_0x24b5f80/d .functor OR 1, L_0x24b5da0, L_0x24b5e90, C4<0>, C4<0>; -L_0x24b5f80 .delay (20000,20000,20000) L_0x24b5f80/d; -v0x2117b80_0 .net "S", 0 0, L_0x24b6160; 1 drivers -v0x2374490_0 .net "in0", 0 0, L_0x24b6200; 1 drivers -v0x2376170_0 .net "in1", 0 0, L_0x24b62f0; 1 drivers -v0x23761f0_0 .net "nS", 0 0, L_0x24b5cf0; 1 drivers -v0x2375f20_0 .net "out0", 0 0, L_0x24b5da0; 1 drivers -v0x23759f0_0 .net "out1", 0 0, L_0x24b5e90; 1 drivers -v0x2377680_0 .net "outfinal", 0 0, L_0x24b5f80; 1 drivers -S_0x226ec40 .scope module, "testBasicFunctions" "testBasicFunctions" 3 6; - .timescale -9 -12; -v0x2468770_0 .var "A", 0 0; -v0x2468810_0 .net "AddSubSLTSum", 0 0, L_0x2525bc0; 1 drivers -v0x2468890_0 .net "AndNandOut", 0 0, L_0x25265f0; 1 drivers -v0x2468910_0 .var "B", 0 0; -v0x2468a20_0 .var "Command", 2 0; -v0x2468aa0_0 .net "OrNorXorOut", 0 0, L_0x2527800; 1 drivers -v0x2468b20_0 .var "S0", 0 0; -v0x2468ba0_0 .var "S1", 0 0; -v0x2468c70_0 .var "carryin", 0 0; -v0x2468d20_0 .net "carryout", 0 0, L_0x2525f60; 1 drivers -v0x2468dd0_0 .var "in0", 0 0; -v0x2468e80_0 .var "in1", 0 0; -v0x2468fa0_0 .var "in2", 0 0; -v0x2469050_0 .var "in3", 0 0; -v0x2469180_0 .net "muxout", 0 0, L_0x2522210; 1 drivers -v0x2469230_0 .net "subtract", 0 0, L_0x25258b0; 1 drivers -S_0x2467e60 .scope module, "testmux" "FourInMux" 3 20, 2 24, S_0x226ec40; - .timescale -9 -12; -L_0x2492610/d .functor NOT 1, v0x2468b20_0, C4<0>, C4<0>, C4<0>; -L_0x2492610 .delay (10000,10000,10000) L_0x2492610/d; -L_0x24926b0/d .functor NOT 1, v0x2468ba0_0, C4<0>, C4<0>, C4<0>; -L_0x24926b0 .delay (10000,10000,10000) L_0x24926b0/d; -L_0x24927a0/d .functor NAND 1, L_0x2492610, L_0x24926b0, v0x2468dd0_0, C4<1>; -L_0x24927a0 .delay (10000,10000,10000) L_0x24927a0/d; -L_0x2492930/d .functor NAND 1, v0x2468b20_0, L_0x24926b0, v0x2468e80_0, C4<1>; -L_0x2492930 .delay (10000,10000,10000) L_0x2492930/d; -L_0x2521f20/d .functor NAND 1, L_0x2492610, v0x2468ba0_0, v0x2468fa0_0, C4<1>; -L_0x2521f20 .delay (10000,10000,10000) L_0x2521f20/d; -L_0x2522010/d .functor NAND 1, v0x2468b20_0, v0x2468ba0_0, v0x2469050_0, C4<1>; -L_0x2522010 .delay (10000,10000,10000) L_0x2522010/d; -L_0x2522210/d .functor NAND 1, L_0x24927a0, L_0x2492930, L_0x2521f20, L_0x2522010; -L_0x2522210 .delay (10000,10000,10000) L_0x2522210/d; -v0x2467f50_0 .net "S0", 0 0, v0x2468b20_0; 1 drivers -v0x2468010_0 .net "S1", 0 0, v0x2468ba0_0; 1 drivers -v0x24680b0_0 .net "in0", 0 0, v0x2468dd0_0; 1 drivers -v0x2468150_0 .net "in1", 0 0, v0x2468e80_0; 1 drivers -v0x24681d0_0 .net "in2", 0 0, v0x2468fa0_0; 1 drivers -v0x2468270_0 .net "in3", 0 0, v0x2469050_0; 1 drivers -v0x2468310_0 .net "nS0", 0 0, L_0x2492610; 1 drivers -v0x24683b0_0 .net "nS1", 0 0, L_0x24926b0; 1 drivers -v0x2468450_0 .alias "out", 0 0, v0x2469180_0; -v0x24684f0_0 .net "out0", 0 0, L_0x24927a0; 1 drivers -v0x2468590_0 .net "out1", 0 0, L_0x2492930; 1 drivers -v0x2468630_0 .net "out2", 0 0, L_0x2521f20; 1 drivers -v0x24686d0_0 .net "out3", 0 0, L_0x2522010; 1 drivers -S_0x2466e50 .scope module, "testadd" "MiddleAddSubSLT" 3 22, 2 89, S_0x226ec40; - .timescale -9 -12; -L_0x2525140/d .functor NOT 1, v0x2468910_0, C4<0>, C4<0>, C4<0>; -L_0x2525140 .delay (10000,10000,10000) L_0x2525140/d; -L_0x2525770/d .functor NOT 1, L_0x2525810, C4<0>, C4<0>, C4<0>; -L_0x2525770 .delay (10000,10000,10000) L_0x2525770/d; -L_0x25258b0/d .functor AND 1, L_0x25259f0, L_0x2525770, C4<1>, C4<1>; -L_0x25258b0 .delay (20000,20000,20000) L_0x25258b0/d; -L_0x2525a90/d .functor XOR 1, v0x2468770_0, L_0x25254b0, C4<0>, C4<0>; -L_0x2525a90 .delay (40000,40000,40000) L_0x2525a90/d; -L_0x2525bc0/d .functor XOR 1, L_0x2525a90, v0x2468c70_0, C4<0>, C4<0>; -L_0x2525bc0 .delay (40000,40000,40000) L_0x2525bc0/d; -L_0x2525d50/d .functor AND 1, v0x2468770_0, L_0x25254b0, C4<1>, C4<1>; -L_0x2525d50 .delay (20000,20000,20000) L_0x2525d50/d; -L_0x2525ec0/d .functor AND 1, L_0x2525a90, v0x2468c70_0, C4<1>, C4<1>; -L_0x2525ec0 .delay (20000,20000,20000) L_0x2525ec0/d; -L_0x2525f60/d .functor OR 1, L_0x2525d50, L_0x2525ec0, C4<0>, C4<0>; -L_0x2525f60 .delay (20000,20000,20000) L_0x2525f60/d; -v0x24673f0_0 .net "A", 0 0, v0x2468770_0; 1 drivers -v0x24674c0_0 .net "AandB", 0 0, L_0x2525d50; 1 drivers -v0x2467560_0 .alias "AddSubSLTSum", 0 0, v0x2468810_0; -v0x2467600_0 .net "AxorB", 0 0, L_0x2525a90; 1 drivers -v0x2467680_0 .net "B", 0 0, v0x2468910_0; 1 drivers -v0x2467700_0 .net "BornB", 0 0, L_0x25254b0; 1 drivers -v0x24677c0_0 .net "CINandAxorB", 0 0, L_0x2525ec0; 1 drivers -v0x2467840_0 .net "Command", 2 0, v0x2468a20_0; 1 drivers -v0x2467960_0 .net *"_s3", 0 0, L_0x2525810; 1 drivers -v0x2467a00_0 .net *"_s5", 0 0, L_0x25259f0; 1 drivers -v0x2467b00_0 .net "carryin", 0 0, v0x2468c70_0; 1 drivers -v0x2467ba0_0 .alias "carryout", 0 0, v0x2468d20_0; -v0x2467c40_0 .net "nB", 0 0, L_0x2525140; 1 drivers -v0x2467cc0_0 .net "nCmd2", 0 0, L_0x2525770; 1 drivers -v0x2467dc0_0 .alias "subtract", 0 0, v0x2469230_0; -L_0x2525640 .part v0x2468a20_0, 0, 1; -L_0x2525810 .part v0x2468a20_0, 2, 1; -L_0x25259f0 .part v0x2468a20_0, 0, 1; -S_0x2466f40 .scope module, "mux0" "TwoInMux" 2 105, 2 8, S_0x2466e50; - .timescale -9 -12; -L_0x2525230/d .functor NOT 1, L_0x2525640, C4<0>, C4<0>, C4<0>; -L_0x2525230 .delay (10000,10000,10000) L_0x2525230/d; -L_0x25252d0/d .functor AND 1, v0x2468910_0, L_0x2525230, C4<1>, C4<1>; -L_0x25252d0 .delay (20000,20000,20000) L_0x25252d0/d; -L_0x25253c0/d .functor AND 1, L_0x2525140, L_0x2525640, C4<1>, C4<1>; -L_0x25253c0 .delay (20000,20000,20000) L_0x25253c0/d; -L_0x25254b0/d .functor OR 1, L_0x25252d0, L_0x25253c0, C4<0>, C4<0>; -L_0x25254b0 .delay (20000,20000,20000) L_0x25254b0/d; -v0x2467030_0 .net "S", 0 0, L_0x2525640; 1 drivers -v0x24670b0_0 .alias "in0", 0 0, v0x2467680_0; -v0x2467130_0 .alias "in1", 0 0, v0x2467c40_0; -v0x24671b0_0 .net "nS", 0 0, L_0x2525230; 1 drivers -v0x2467230_0 .net "out0", 0 0, L_0x25252d0; 1 drivers -v0x24672b0_0 .net "out1", 0 0, L_0x25253c0; 1 drivers -v0x2467370_0 .alias "outfinal", 0 0, v0x2467700_0; -S_0x24663e0 .scope module, "testand" "AndNand" 3 24, 2 48, S_0x226ec40; - .timescale -9 -12; -L_0x25260a0/d .functor NAND 1, v0x2468770_0, v0x2468910_0, C4<1>, C4<1>; -L_0x25260a0 .delay (10000,10000,10000) L_0x25260a0/d; -L_0x25261a0/d .functor NOT 1, L_0x25260a0, C4<0>, C4<0>, C4<0>; -L_0x25261a0 .delay (10000,10000,10000) L_0x25261a0/d; -v0x2466a00_0 .alias "A", 0 0, v0x24673f0_0; -v0x2466aa0_0 .net "AandB", 0 0, L_0x25261a0; 1 drivers -v0x2466b50_0 .net "AnandB", 0 0, L_0x25260a0; 1 drivers -v0x2466c00_0 .alias "AndNandOut", 0 0, v0x2468890_0; -v0x2466ce0_0 .alias "B", 0 0, v0x2467680_0; -v0x2466d90_0 .alias "Command", 2 0, v0x2467840_0; -L_0x2526770 .part v0x2468a20_0, 0, 1; -S_0x24664d0 .scope module, "potato" "TwoInMux" 2 60, 2 8, S_0x24663e0; - .timescale -9 -12; -L_0x25262d0/d .functor NOT 1, L_0x2526770, C4<0>, C4<0>, C4<0>; -L_0x25262d0 .delay (10000,10000,10000) L_0x25262d0/d; -L_0x2526390/d .functor AND 1, L_0x25261a0, L_0x25262d0, C4<1>, C4<1>; -L_0x2526390 .delay (20000,20000,20000) L_0x2526390/d; -L_0x25264a0/d .functor AND 1, L_0x25260a0, L_0x2526770, C4<1>, C4<1>; -L_0x25264a0 .delay (20000,20000,20000) L_0x25264a0/d; -L_0x25265f0/d .functor OR 1, L_0x2526390, L_0x25264a0, C4<0>, C4<0>; -L_0x25265f0 .delay (20000,20000,20000) L_0x25265f0/d; -v0x24665c0_0 .net "S", 0 0, L_0x2526770; 1 drivers -v0x2466660_0 .alias "in0", 0 0, v0x2466aa0_0; -v0x2466700_0 .alias "in1", 0 0, v0x2466b50_0; -v0x24667a0_0 .net "nS", 0 0, L_0x25262d0; 1 drivers -v0x2466820_0 .net "out0", 0 0, L_0x2526390; 1 drivers -v0x24668c0_0 .net "out1", 0 0, L_0x25264a0; 1 drivers -v0x2466960_0 .alias "outfinal", 0 0, v0x2468890_0; -S_0x2464f10 .scope module, "testor" "OrNorXor" 3 26, 2 64, S_0x226ec40; - .timescale -9 -12; -L_0x2526810/d .functor NOR 1, v0x2468770_0, v0x2468910_0, C4<0>, C4<0>; -L_0x2526810 .delay (10000,10000,10000) L_0x2526810/d; -L_0x25269e0/d .functor NOT 1, L_0x2526810, C4<0>, C4<0>, C4<0>; -L_0x25269e0 .delay (10000,10000,10000) L_0x25269e0/d; -L_0x2526b10/d .functor NAND 1, v0x2468770_0, v0x2468910_0, C4<1>, C4<1>; -L_0x2526b10 .delay (10000,10000,10000) L_0x2526b10/d; -L_0x2526ca0/d .functor NAND 1, L_0x2526b10, L_0x25269e0, C4<1>, C4<1>; -L_0x2526ca0 .delay (10000,10000,10000) L_0x2526ca0/d; -L_0x2526d90/d .functor NOT 1, L_0x2526ca0, C4<0>, C4<0>, C4<0>; -L_0x2526d90 .delay (10000,10000,10000) L_0x2526d90/d; -v0x2465d80_0 .alias "A", 0 0, v0x24673f0_0; -v0x2465e20_0 .net "AnandB", 0 0, L_0x2526b10; 1 drivers -v0x2465ec0_0 .net "AnorB", 0 0, L_0x2526810; 1 drivers -v0x2465f70_0 .net "AorB", 0 0, L_0x25269e0; 1 drivers -v0x2466050_0 .net "AxorB", 0 0, L_0x2526d90; 1 drivers -v0x24660d0_0 .alias "B", 0 0, v0x2467680_0; -v0x2466190_0 .alias "Command", 2 0, v0x2467840_0; -v0x2466210_0 .alias "OrNorXorOut", 0 0, v0x2468aa0_0; -v0x2466290_0 .net "XorNor", 0 0, L_0x25271f0; 1 drivers -v0x2466360_0 .net "nXor", 0 0, L_0x2526ca0; 1 drivers -L_0x2527370 .part v0x2468a20_0, 2, 1; -L_0x2527980 .part v0x2468a20_0, 0, 1; -S_0x2465810 .scope module, "mux0" "TwoInMux" 2 83, 2 8, S_0x2464f10; - .timescale -9 -12; -L_0x2526ed0/d .functor NOT 1, L_0x2527370, C4<0>, C4<0>, C4<0>; -L_0x2526ed0 .delay (10000,10000,10000) L_0x2526ed0/d; -L_0x2526f90/d .functor AND 1, L_0x2526d90, L_0x2526ed0, C4<1>, C4<1>; -L_0x2526f90 .delay (20000,20000,20000) L_0x2526f90/d; -L_0x25270a0/d .functor AND 1, L_0x2526810, L_0x2527370, C4<1>, C4<1>; -L_0x25270a0 .delay (20000,20000,20000) L_0x25270a0/d; -L_0x25271f0/d .functor OR 1, L_0x2526f90, L_0x25270a0, C4<0>, C4<0>; -L_0x25271f0 .delay (20000,20000,20000) L_0x25271f0/d; -v0x2465900_0 .net "S", 0 0, L_0x2527370; 1 drivers -v0x24659c0_0 .alias "in0", 0 0, v0x2466050_0; -v0x2465a60_0 .alias "in1", 0 0, v0x2465ec0_0; -v0x2465b00_0 .net "nS", 0 0, L_0x2526ed0; 1 drivers -v0x2465b80_0 .net "out0", 0 0, L_0x2526f90; 1 drivers -v0x2465c20_0 .net "out1", 0 0, L_0x25270a0; 1 drivers -v0x2465d00_0 .alias "outfinal", 0 0, v0x2466290_0; -S_0x2465390 .scope module, "mux1" "TwoInMux" 2 84, 2 8, S_0x2464f10; - .timescale -9 -12; -L_0x25256e0/d .functor NOT 1, L_0x2527980, C4<0>, C4<0>, C4<0>; -L_0x25256e0 .delay (10000,10000,10000) L_0x25256e0/d; -L_0x2527560/d .functor AND 1, L_0x25271f0, L_0x25256e0, C4<1>, C4<1>; -L_0x2527560 .delay (20000,20000,20000) L_0x2527560/d; -L_0x25276b0/d .functor AND 1, L_0x25269e0, L_0x2527980, C4<1>, C4<1>; -L_0x25276b0 .delay (20000,20000,20000) L_0x25276b0/d; -L_0x2527800/d .functor OR 1, L_0x2527560, L_0x25276b0, C4<0>, C4<0>; -L_0x2527800 .delay (20000,20000,20000) L_0x2527800/d; -v0x2465000_0 .net "S", 0 0, L_0x2527980; 1 drivers -v0x2465480_0 .alias "in0", 0 0, v0x2466290_0; -v0x2465500_0 .alias "in1", 0 0, v0x2465f70_0; -v0x2465580_0 .net "nS", 0 0, L_0x25256e0; 1 drivers -v0x2465630_0 .net "out0", 0 0, L_0x2527560; 1 drivers -v0x24656d0_0 .net "out1", 0 0, L_0x25276b0; 1 drivers -v0x2465770_0 .alias "outfinal", 0 0, v0x2468aa0_0; - .scope S_0x226ec40; +L_0x246ed30/d .functor NOT 1, L_0x246f550, C4<0>, C4<0>, C4<0>; +L_0x246ed30 .delay (10000,10000,10000) L_0x246ed30/d; +L_0x246edf0/d .functor NAND 1, L_0x246eae0, L_0x246ed30, L_0x246f680, C4<1>; +L_0x246edf0 .delay (10000,10000,10000) L_0x246edf0/d; +L_0x246eee0/d .functor NAND 1, L_0x246f420, L_0x246ed30, L_0x246f720, C4<1>; +L_0x246eee0 .delay (10000,10000,10000) L_0x246eee0/d; +L_0x246efd0/d .functor NAND 1, L_0x246eae0, L_0x246f550, L_0x246f7c0, C4<1>; +L_0x246efd0 .delay (10000,10000,10000) L_0x246efd0/d; +L_0x246f0c0/d .functor NAND 1, L_0x246f420, L_0x246f550, L_0x246f9c0, C4<1>; +L_0x246f0c0 .delay (10000,10000,10000) L_0x246f0c0/d; +L_0x246f1a0/d .functor NAND 1, L_0x246edf0, L_0x246eee0, L_0x246efd0, L_0x246f0c0; +L_0x246f1a0 .delay (10000,10000,10000) L_0x246f1a0/d; +v0x243cdd0_0 .net "S0", 0 0, L_0x246f420; 1 drivers +v0x243ce90_0 .net "S1", 0 0, L_0x246f550; 1 drivers +v0x243cf30_0 .net "in0", 0 0, L_0x246f680; 1 drivers +v0x243cfd0_0 .net "in1", 0 0, L_0x246f720; 1 drivers +v0x243d050_0 .net "in2", 0 0, L_0x246f7c0; 1 drivers +v0x243d0f0_0 .net "in3", 0 0, L_0x246f9c0; 1 drivers +v0x243d190_0 .net "nS0", 0 0, L_0x246eae0; 1 drivers +v0x243d230_0 .net "nS1", 0 0, L_0x246ed30; 1 drivers +v0x243d2d0_0 .net "out", 0 0, L_0x246f1a0; 1 drivers +v0x243d370_0 .net "out0", 0 0, L_0x246edf0; 1 drivers +v0x243d410_0 .net "out1", 0 0, L_0x246eee0; 1 drivers +v0x243d4b0_0 .net "out2", 0 0, L_0x246efd0; 1 drivers +v0x243d5c0_0 .net "out3", 0 0, L_0x246f0c0; 1 drivers +S_0x243c320 .scope module, "OneMux" "FourInMux" 3 325, 3 24, S_0x243bc40; + .timescale -9 -12; +L_0x246fa60/d .functor NOT 1, L_0x24702c0, C4<0>, C4<0>, C4<0>; +L_0x246fa60 .delay (10000,10000,10000) L_0x246fa60/d; +L_0x246fb50/d .functor NOT 1, L_0x24703f0, C4<0>, C4<0>, C4<0>; +L_0x246fb50 .delay (10000,10000,10000) L_0x246fb50/d; +L_0x246fbf0/d .functor NAND 1, L_0x246fa60, L_0x246fb50, L_0x2470580, C4<1>; +L_0x246fbf0 .delay (10000,10000,10000) L_0x246fbf0/d; +L_0x246fd30/d .functor NAND 1, L_0x24702c0, L_0x246fb50, L_0x2470730, C4<1>; +L_0x246fd30 .delay (10000,10000,10000) L_0x246fd30/d; +L_0x246fe20/d .functor NAND 1, L_0x246fa60, L_0x24703f0, L_0x24707d0, C4<1>; +L_0x246fe20 .delay (10000,10000,10000) L_0x246fe20/d; +L_0x246ff10/d .functor NAND 1, L_0x24702c0, L_0x24703f0, L_0x2470870, C4<1>; +L_0x246ff10 .delay (10000,10000,10000) L_0x246ff10/d; +L_0x246fff0/d .functor NAND 1, L_0x246fbf0, L_0x246fd30, L_0x246fe20, L_0x246ff10; +L_0x246fff0 .delay (10000,10000,10000) L_0x246fff0/d; +v0x243c410_0 .net "S0", 0 0, L_0x24702c0; 1 drivers +v0x243c4d0_0 .net "S1", 0 0, L_0x24703f0; 1 drivers +v0x243c570_0 .net "in0", 0 0, L_0x2470580; 1 drivers +v0x243c610_0 .net "in1", 0 0, L_0x2470730; 1 drivers +v0x243c690_0 .net "in2", 0 0, L_0x24707d0; 1 drivers +v0x243c730_0 .net "in3", 0 0, L_0x2470870; 1 drivers +v0x243c810_0 .net "nS0", 0 0, L_0x246fa60; 1 drivers +v0x243c8b0_0 .net "nS1", 0 0, L_0x246fb50; 1 drivers +v0x243c950_0 .net "out", 0 0, L_0x246fff0; 1 drivers +v0x243c9f0_0 .net "out0", 0 0, L_0x246fbf0; 1 drivers +v0x243ca90_0 .net "out1", 0 0, L_0x246fd30; 1 drivers +v0x243cb30_0 .net "out2", 0 0, L_0x246fe20; 1 drivers +v0x243cc40_0 .net "out3", 0 0, L_0x246ff10; 1 drivers +S_0x243bdb0 .scope module, "TwoMux" "TwoInMux" 3 326, 3 8, S_0x243bc40; + .timescale -9 -12; +L_0x2470520/d .functor NOT 1, L_0x2470dc0, C4<0>, C4<0>, C4<0>; +L_0x2470520 .delay (10000,10000,10000) L_0x2470520/d; +L_0x24709b0/d .functor AND 1, L_0x2470e60, L_0x2470520, C4<1>, C4<1>; +L_0x24709b0 .delay (20000,20000,20000) L_0x24709b0/d; +L_0x2470aa0/d .functor AND 1, L_0x2470fa0, L_0x2470dc0, C4<1>, C4<1>; +L_0x2470aa0 .delay (20000,20000,20000) L_0x2470aa0/d; +L_0x2470b90/d .functor OR 1, L_0x24709b0, L_0x2470aa0, C4<0>, C4<0>; +L_0x2470b90 .delay (20000,20000,20000) L_0x2470b90/d; +v0x243bea0_0 .net "S", 0 0, L_0x2470dc0; 1 drivers +v0x243bf40_0 .net "in0", 0 0, L_0x2470e60; 1 drivers +v0x243bfe0_0 .net "in1", 0 0, L_0x2470fa0; 1 drivers +v0x243c080_0 .net "nS", 0 0, L_0x2470520; 1 drivers +v0x243c100_0 .net "out0", 0 0, L_0x24709b0; 1 drivers +v0x243c1a0_0 .net "out1", 0 0, L_0x2470aa0; 1 drivers +v0x243c280_0 .net "outfinal", 0 0, L_0x2470b90; 1 drivers +S_0x243a0c0 .scope generate, "muxbits[2]" "muxbits[2]" 3 322, 3 322, S_0x23d85b0; + .timescale -9 -12; +P_0x2439008 .param/l "i" 3 322, +C4<010>; +L_0x2473520/d .functor OR 1, L_0x2473d20, L_0x24740a0, C4<0>, C4<0>; +L_0x2473520 .delay (20000,20000,20000) L_0x2473520/d; +v0x243bae0_0 .net *"_s15", 0 0, L_0x2473d20; 1 drivers +v0x243bba0_0 .net *"_s16", 0 0, L_0x24740a0; 1 drivers +S_0x243b160 .scope module, "ZeroMux" "FourInMux" 3 324, 3 24, S_0x243a0c0; + .timescale -9 -12; +L_0x24714c0/d .functor NOT 1, L_0x24713c0, C4<0>, C4<0>, C4<0>; +L_0x24714c0 .delay (10000,10000,10000) L_0x24714c0/d; +L_0x24715b0/d .functor NOT 1, L_0x245f370, C4<0>, C4<0>, C4<0>; +L_0x24715b0 .delay (10000,10000,10000) L_0x24715b0/d; +L_0x2471650/d .functor NAND 1, L_0x24714c0, L_0x24715b0, L_0x2471d00, C4<1>; +L_0x2471650 .delay (10000,10000,10000) L_0x2471650/d; +L_0x2471790/d .functor NAND 1, L_0x24713c0, L_0x24715b0, L_0x245f570, C4<1>; +L_0x2471790 .delay (10000,10000,10000) L_0x2471790/d; +L_0x2471880/d .functor NAND 1, L_0x24714c0, L_0x245f370, L_0x245f4a0, C4<1>; +L_0x2471880 .delay (10000,10000,10000) L_0x2471880/d; +L_0x2471970/d .functor NAND 1, L_0x24713c0, L_0x245f370, L_0x2472660, C4<1>; +L_0x2471970 .delay (10000,10000,10000) L_0x2471970/d; +L_0x2471a50/d .functor NAND 1, L_0x2471650, L_0x2471790, L_0x2471880, L_0x2471970; +L_0x2471a50 .delay (10000,10000,10000) L_0x2471a50/d; +v0x243b250_0 .net "S0", 0 0, L_0x24713c0; 1 drivers +v0x243b310_0 .net "S1", 0 0, L_0x245f370; 1 drivers +v0x243b3b0_0 .net "in0", 0 0, L_0x2471d00; 1 drivers +v0x243b450_0 .net "in1", 0 0, L_0x245f570; 1 drivers +v0x243b4d0_0 .net "in2", 0 0, L_0x245f4a0; 1 drivers +v0x243b570_0 .net "in3", 0 0, L_0x2472660; 1 drivers +v0x243b610_0 .net "nS0", 0 0, L_0x24714c0; 1 drivers +v0x243b6b0_0 .net "nS1", 0 0, L_0x24715b0; 1 drivers +v0x243b750_0 .net "out", 0 0, L_0x2471a50; 1 drivers +v0x243b7f0_0 .net "out0", 0 0, L_0x2471650; 1 drivers +v0x243b890_0 .net "out1", 0 0, L_0x2471790; 1 drivers +v0x243b930_0 .net "out2", 0 0, L_0x2471880; 1 drivers +v0x243ba40_0 .net "out3", 0 0, L_0x2471970; 1 drivers +S_0x243a7a0 .scope module, "OneMux" "FourInMux" 3 325, 3 24, S_0x243a0c0; + .timescale -9 -12; +L_0x245f610/d .functor NOT 1, L_0x2472f70, C4<0>, C4<0>, C4<0>; +L_0x245f610 .delay (10000,10000,10000) L_0x245f610/d; +L_0x24727f0/d .functor NOT 1, L_0x2472700, C4<0>, C4<0>, C4<0>; +L_0x24727f0 .delay (10000,10000,10000) L_0x24727f0/d; +L_0x2472890/d .functor NAND 1, L_0x245f610, L_0x24727f0, L_0x2473230, C4<1>; +L_0x2472890 .delay (10000,10000,10000) L_0x2472890/d; +L_0x24729d0/d .functor NAND 1, L_0x2472f70, L_0x24727f0, L_0x24730a0, C4<1>; +L_0x24729d0 .delay (10000,10000,10000) L_0x24729d0/d; +L_0x2472ac0/d .functor NAND 1, L_0x245f610, L_0x2472700, L_0x24733e0, C4<1>; +L_0x2472ac0 .delay (10000,10000,10000) L_0x2472ac0/d; +L_0x2472bb0/d .functor NAND 1, L_0x2472f70, L_0x2472700, L_0x24732d0, C4<1>; +L_0x2472bb0 .delay (10000,10000,10000) L_0x2472bb0/d; +L_0x2472cc0/d .functor NAND 1, L_0x2472890, L_0x24729d0, L_0x2472ac0, L_0x2472bb0; +L_0x2472cc0 .delay (10000,10000,10000) L_0x2472cc0/d; +v0x243a890_0 .net "S0", 0 0, L_0x2472f70; 1 drivers +v0x243a950_0 .net "S1", 0 0, L_0x2472700; 1 drivers +v0x243a9f0_0 .net "in0", 0 0, L_0x2473230; 1 drivers +v0x243aa90_0 .net "in1", 0 0, L_0x24730a0; 1 drivers +v0x243ab10_0 .net "in2", 0 0, L_0x24733e0; 1 drivers +v0x243abb0_0 .net "in3", 0 0, L_0x24732d0; 1 drivers +v0x243ac90_0 .net "nS0", 0 0, L_0x245f610; 1 drivers +v0x243ad30_0 .net "nS1", 0 0, L_0x24727f0; 1 drivers +v0x243add0_0 .net "out", 0 0, L_0x2472cc0; 1 drivers +v0x243ae70_0 .net "out0", 0 0, L_0x2472890; 1 drivers +v0x243af10_0 .net "out1", 0 0, L_0x24729d0; 1 drivers +v0x243afb0_0 .net "out2", 0 0, L_0x2472ac0; 1 drivers +v0x243b0c0_0 .net "out3", 0 0, L_0x2472bb0; 1 drivers +S_0x243a230 .scope module, "TwoMux" "TwoInMux" 3 326, 3 8, S_0x243a0c0; + .timescale -9 -12; +L_0x2473370/d .functor NOT 1, L_0x2473480, C4<0>, C4<0>, C4<0>; +L_0x2473370 .delay (10000,10000,10000) L_0x2473370/d; +L_0x2473630/d .functor AND 1, L_0x2473bb0, L_0x2473370, C4<1>, C4<1>; +L_0x2473630 .delay (20000,20000,20000) L_0x2473630/d; +L_0x2473720/d .functor AND 1, L_0x2473a80, L_0x2473480, C4<1>, C4<1>; +L_0x2473720 .delay (20000,20000,20000) L_0x2473720/d; +L_0x2473810/d .functor OR 1, L_0x2473630, L_0x2473720, C4<0>, C4<0>; +L_0x2473810 .delay (20000,20000,20000) L_0x2473810/d; +v0x243a320_0 .net "S", 0 0, L_0x2473480; 1 drivers +v0x243a3c0_0 .net "in0", 0 0, L_0x2473bb0; 1 drivers +v0x243a460_0 .net "in1", 0 0, L_0x2473a80; 1 drivers +v0x243a500_0 .net "nS", 0 0, L_0x2473370; 1 drivers +v0x243a580_0 .net "out0", 0 0, L_0x2473630; 1 drivers +v0x243a620_0 .net "out1", 0 0, L_0x2473720; 1 drivers +v0x243a700_0 .net "outfinal", 0 0, L_0x2473810; 1 drivers +S_0x2389b20 .scope generate, "muxbits[3]" "muxbits[3]" 3 322, 3 322, S_0x23d85b0; + .timescale -9 -12; +P_0x23a5c28 .param/l "i" 3 322, +C4<011>; +L_0x2476790/d .functor OR 1, L_0x2476b10, L_0x2476920, C4<0>, C4<0>; +L_0x2476790 .delay (20000,20000,20000) L_0x2476790/d; +v0x2439f60_0 .net *"_s15", 0 0, L_0x2476b10; 1 drivers +v0x243a020_0 .net *"_s16", 0 0, L_0x2476920; 1 drivers +S_0x24395e0 .scope module, "ZeroMux" "FourInMux" 3 324, 3 24, S_0x2389b20; + .timescale -9 -12; +L_0x2473f50/d .functor NOT 1, L_0x2474a80, C4<0>, C4<0>, C4<0>; +L_0x2473f50 .delay (10000,10000,10000) L_0x2473f50/d; +L_0x2474040/d .functor NOT 1, L_0x2474140, C4<0>, C4<0>, C4<0>; +L_0x2474040 .delay (10000,10000,10000) L_0x2474040/d; +L_0x24742e0/d .functor NAND 1, L_0x2473f50, L_0x2474040, L_0x2474d20, C4<1>; +L_0x24742e0 .delay (10000,10000,10000) L_0x24742e0/d; +L_0x2474420/d .functor NAND 1, L_0x2474a80, L_0x2474040, L_0x2466c90, C4<1>; +L_0x2474420 .delay (10000,10000,10000) L_0x2474420/d; +L_0x2474510/d .functor NAND 1, L_0x2473f50, L_0x2474140, L_0x2474bb0, C4<1>; +L_0x2474510 .delay (10000,10000,10000) L_0x2474510/d; +L_0x2474660/d .functor NAND 1, L_0x2474a80, L_0x2474140, L_0x2475160, C4<1>; +L_0x2474660 .delay (10000,10000,10000) L_0x2474660/d; +L_0x24747d0/d .functor NAND 1, L_0x24742e0, L_0x2474420, L_0x2474510, L_0x2474660; +L_0x24747d0 .delay (10000,10000,10000) L_0x24747d0/d; +v0x24396d0_0 .net "S0", 0 0, L_0x2474a80; 1 drivers +v0x2439790_0 .net "S1", 0 0, L_0x2474140; 1 drivers +v0x2439830_0 .net "in0", 0 0, L_0x2474d20; 1 drivers +v0x24398d0_0 .net "in1", 0 0, L_0x2466c90; 1 drivers +v0x2439950_0 .net "in2", 0 0, L_0x2474bb0; 1 drivers +v0x24399f0_0 .net "in3", 0 0, L_0x2475160; 1 drivers +v0x2439a90_0 .net "nS0", 0 0, L_0x2473f50; 1 drivers +v0x2439b30_0 .net "nS1", 0 0, L_0x2474040; 1 drivers +v0x2439bd0_0 .net "out", 0 0, L_0x24747d0; 1 drivers +v0x2439c70_0 .net "out0", 0 0, L_0x24742e0; 1 drivers +v0x2439d10_0 .net "out1", 0 0, L_0x2474420; 1 drivers +v0x2439db0_0 .net "out2", 0 0, L_0x2474510; 1 drivers +v0x2439ec0_0 .net "out3", 0 0, L_0x2474660; 1 drivers +S_0x2438b70 .scope module, "OneMux" "FourInMux" 3 325, 3 24, S_0x2389b20; + .timescale -9 -12; +L_0x2474ca0/d .functor NOT 1, L_0x2474fd0, C4<0>, C4<0>, C4<0>; +L_0x2474ca0 .delay (10000,10000,10000) L_0x2474ca0/d; +L_0x2475290/d .functor NOT 1, L_0x2475c10, C4<0>, C4<0>, C4<0>; +L_0x2475290 .delay (10000,10000,10000) L_0x2475290/d; +L_0x2475330/d .functor NAND 1, L_0x2474ca0, L_0x2475290, L_0x2475a70, C4<1>; +L_0x2475330 .delay (10000,10000,10000) L_0x2475330/d; +L_0x2475470/d .functor NAND 1, L_0x2474fd0, L_0x2475290, L_0x2475b10, C4<1>; +L_0x2475470 .delay (10000,10000,10000) L_0x2475470/d; +L_0x2475560/d .functor NAND 1, L_0x2474ca0, L_0x2475c10, L_0x2475f00, C4<1>; +L_0x2475560 .delay (10000,10000,10000) L_0x2475560/d; +L_0x2475650/d .functor NAND 1, L_0x2474fd0, L_0x2475c10, L_0x2475fa0, C4<1>; +L_0x2475650 .delay (10000,10000,10000) L_0x2475650/d; +L_0x24757c0/d .functor NAND 1, L_0x2475330, L_0x2475470, L_0x2475560, L_0x2475650; +L_0x24757c0 .delay (10000,10000,10000) L_0x24757c0/d; +v0x2438c60_0 .net "S0", 0 0, L_0x2474fd0; 1 drivers +v0x2438d20_0 .net "S1", 0 0, L_0x2475c10; 1 drivers +v0x2438dc0_0 .net "in0", 0 0, L_0x2475a70; 1 drivers +v0x2438e60_0 .net "in1", 0 0, L_0x2475b10; 1 drivers +v0x2438ee0_0 .net "in2", 0 0, L_0x2475f00; 1 drivers +v0x2438f80_0 .net "in3", 0 0, L_0x2475fa0; 1 drivers +v0x2439060_0 .net "nS0", 0 0, L_0x2474ca0; 1 drivers +v0x2439100_0 .net "nS1", 0 0, L_0x2475290; 1 drivers +v0x24391f0_0 .net "out", 0 0, L_0x24757c0; 1 drivers +v0x2439290_0 .net "out0", 0 0, L_0x2475330; 1 drivers +v0x2439390_0 .net "out1", 0 0, L_0x2475470; 1 drivers +v0x2439430_0 .net "out2", 0 0, L_0x2475560; 1 drivers +v0x2439540_0 .net "out3", 0 0, L_0x2475650; 1 drivers +S_0x23cef60 .scope module, "TwoMux" "TwoInMux" 3 326, 3 8, S_0x2389b20; + .timescale -9 -12; +L_0x246f8b0/d .functor NOT 1, L_0x2476650, C4<0>, C4<0>, C4<0>; +L_0x246f8b0 .delay (10000,10000,10000) L_0x246f8b0/d; +L_0x2475d40/d .functor AND 1, L_0x2476250, L_0x246f8b0, C4<1>, C4<1>; +L_0x2475d40 .delay (20000,20000,20000) L_0x2475d40/d; +L_0x2475e30/d .functor AND 1, L_0x2476340, L_0x2476650, C4<1>, C4<1>; +L_0x2475e30 .delay (20000,20000,20000) L_0x2475e30/d; +L_0x2476470/d .functor OR 1, L_0x2475d40, L_0x2475e30, C4<0>, C4<0>; +L_0x2476470 .delay (20000,20000,20000) L_0x2476470/d; +v0x232ba40_0 .net "S", 0 0, L_0x2476650; 1 drivers +v0x2438760_0 .net "in0", 0 0, L_0x2476250; 1 drivers +v0x2438800_0 .net "in1", 0 0, L_0x2476340; 1 drivers +v0x24388a0_0 .net "nS", 0 0, L_0x246f8b0; 1 drivers +v0x2438950_0 .net "out0", 0 0, L_0x2475d40; 1 drivers +v0x24389f0_0 .net "out1", 0 0, L_0x2475e30; 1 drivers +v0x2438ad0_0 .net "outfinal", 0 0, L_0x2476470; 1 drivers + .scope S_0x23b34d0; T_0 ; - %vpi_call 3 28 "$dumpfile", "SmallALU.vcd"; - %vpi_call 3 29 "$dumpvars"; - %vpi_call 3 44 "$display", "Adder/Subtractor"; - %vpi_call 3 45 "$display", "A B | Command |Out|ExpectOut|Carryout-Add"; - %set/v v0x2468770_0, 1, 1; - %set/v v0x2468910_0, 1, 1; - %set/v v0x2468a20_0, 0, 3; - %set/v v0x2468c70_0, 0, 1; + %vpi_call 2 154 "$dumpfile", "FullALU.vcd"; + %vpi_call 2 155 "$dumpvars"; + %vpi_call 2 157 "$display", "Test 4 Bit Adder Functionality"; + %vpi_call 2 159 "$display", " A | B |Command| Out|ExpectedOut|Cout|OF"; + %movi 8, 2, 4; + %set/v v0x245e5f0_0, 8, 4; + %movi 8, 4, 4; + %set/v v0x245e7f0_0, 8, 4; + %set/v v0x245e870_0, 0, 3; %delay 1000000, 0; - %vpi_call 3 48 "$display", "%b %b | %b | %b | 0 | %b", v0x2468770_0, v0x2468910_0, v0x2468a20_0, v0x2468810_0, v0x2468d20_0; - %set/v v0x2468770_0, 1, 1; - %set/v v0x2468910_0, 0, 1; - %set/v v0x2468a20_0, 0, 3; - %set/v v0x2468c70_0, 0, 1; + %vpi_call 2 163 "$display", "%b | %b | %b | %b | Expect 0110| %b | %b ", v0x245e5f0_0, v0x245e7f0_0, v0x245e870_0, v0x245e670_0, v0x245ebc0_0, v0x245ec40_0; + %movi 8, 1, 4; + %set/v v0x245e5f0_0, 8, 4; + %movi 8, 6, 4; + %set/v v0x245e7f0_0, 8, 4; + %set/v v0x245e870_0, 0, 3; %delay 1000000, 0; - %vpi_call 3 50 "$display", "%b %b | %b | %b | 1 | %b", v0x2468770_0, v0x2468910_0, v0x2468a20_0, v0x2468810_0, v0x2468d20_0; - %set/v v0x2468770_0, 0, 1; - %set/v v0x2468910_0, 1, 1; - %set/v v0x2468a20_0, 0, 3; - %set/v v0x2468c70_0, 0, 1; + %vpi_call 2 167 "$display", "%b | %b | %b | %b | Expect 0111| %b | %b ", v0x245e5f0_0, v0x245e7f0_0, v0x245e870_0, v0x245e670_0, v0x245ebc0_0, v0x245ec40_0; + %movi 8, 5, 4; + %set/v v0x245e5f0_0, 8, 4; + %movi 8, 13, 4; + %set/v v0x245e7f0_0, 8, 4; + %set/v v0x245e870_0, 0, 3; %delay 1000000, 0; - %vpi_call 3 52 "$display", "%b %b | %b | %b | 1 | %b", v0x2468770_0, v0x2468910_0, v0x2468a20_0, v0x2468810_0, v0x2468d20_0; - %set/v v0x2468770_0, 0, 1; - %set/v v0x2468910_0, 0, 1; - %set/v v0x2468a20_0, 0, 3; - %set/v v0x2468c70_0, 0, 1; + %vpi_call 2 171 "$display", "%b | %b | %b | %b | Expect 0010| %b | %b ", v0x245e5f0_0, v0x245e7f0_0, v0x245e870_0, v0x245e670_0, v0x245ebc0_0, v0x245ec40_0; + %movi 8, 2, 4; + %set/v v0x245e5f0_0, 8, 4; + %set/v v0x245e7f0_0, 1, 4; + %set/v v0x245e870_0, 0, 3; %delay 1000000, 0; - %vpi_call 3 54 "$display", "%b %b | %b | %b | 0 | %b", v0x2468770_0, v0x2468910_0, v0x2468a20_0, v0x2468810_0, v0x2468d20_0; - %vpi_call 3 56 "$display", "A B | Command |Out|ExpectOut|Carryout-Sub"; - %set/v v0x2468770_0, 1, 1; - %set/v v0x2468910_0, 1, 1; - %movi 8, 1, 3; - %set/v v0x2468a20_0, 8, 3; - %set/v v0x2468c70_0, 1, 1; + %vpi_call 2 175 "$display", "%b | %b | %b | %b | Expect 0001| %b | %b ", v0x245e5f0_0, v0x245e7f0_0, v0x245e870_0, v0x245e670_0, v0x245ebc0_0, v0x245ec40_0; + %movi 8, 8, 4; + %set/v v0x245e5f0_0, 8, 4; + %movi 8, 3, 4; + %set/v v0x245e7f0_0, 8, 4; + %set/v v0x245e870_0, 0, 3; %delay 1000000, 0; - %vpi_call 3 58 "$display", "%b %b | %b | %b | 0 | %b", v0x2468770_0, v0x2468910_0, v0x2468a20_0, v0x2468810_0, v0x2468d20_0; - %set/v v0x2468770_0, 1, 1; - %set/v v0x2468910_0, 0, 1; - %movi 8, 1, 3; - %set/v v0x2468a20_0, 8, 3; - %set/v v0x2468c70_0, 1, 1; + %vpi_call 2 179 "$display", "%b | %b | %b | %b | Expect 1011| %b | %b ", v0x245e5f0_0, v0x245e7f0_0, v0x245e870_0, v0x245e670_0, v0x245ebc0_0, v0x245ec40_0; + %movi 8, 12, 4; + %set/v v0x245e5f0_0, 8, 4; + %movi 8, 2, 4; + %set/v v0x245e7f0_0, 8, 4; + %set/v v0x245e870_0, 0, 3; %delay 1000000, 0; - %vpi_call 3 60 "$display", "%b %b | %b | %b | 1 | %b", v0x2468770_0, v0x2468910_0, v0x2468a20_0, v0x2468810_0, v0x2468d20_0; - %set/v v0x2468770_0, 0, 1; - %set/v v0x2468910_0, 1, 1; - %movi 8, 1, 3; - %set/v v0x2468a20_0, 8, 3; - %set/v v0x2468c70_0, 1, 1; + %vpi_call 2 183 "$display", "%b | %b | %b | %b | Expect 1110| %b | %b ", v0x245e5f0_0, v0x245e7f0_0, v0x245e870_0, v0x245e670_0, v0x245ebc0_0, v0x245ec40_0; + %movi 8, 11, 4; + %set/v v0x245e5f0_0, 8, 4; + %movi 8, 5, 4; + %set/v v0x245e7f0_0, 8, 4; + %set/v v0x245e870_0, 0, 3; %delay 1000000, 0; - %vpi_call 3 62 "$display", "%b %b | %b | %b | 1 | %b", v0x2468770_0, v0x2468910_0, v0x2468a20_0, v0x2468810_0, v0x2468d20_0; - %set/v v0x2468770_0, 0, 1; - %set/v v0x2468910_0, 0, 1; - %movi 8, 1, 3; - %set/v v0x2468a20_0, 8, 3; - %set/v v0x2468c70_0, 1, 1; + %vpi_call 2 187 "$display", "%b | %b | %b | %b | Expect 0000| %b | %b ", v0x245e5f0_0, v0x245e7f0_0, v0x245e870_0, v0x245e670_0, v0x245ebc0_0, v0x245ec40_0; + %movi 8, 7, 4; + %set/v v0x245e5f0_0, 8, 4; + %movi 8, 9, 4; + %set/v v0x245e7f0_0, 8, 4; + %set/v v0x245e870_0, 0, 3; + %delay 1000000, 0; + %vpi_call 2 191 "$display", "%b | %b | %b | %b | Expect 0000| %b | %b ", v0x245e5f0_0, v0x245e7f0_0, v0x245e870_0, v0x245e670_0, v0x245ebc0_0, v0x245ec40_0; + %movi 8, 13, 4; + %set/v v0x245e5f0_0, 8, 4; + %movi 8, 12, 4; + %set/v v0x245e7f0_0, 8, 4; + %set/v v0x245e870_0, 0, 3; + %delay 1000000, 0; + %vpi_call 2 195 "$display", "%b | %b | %b | %b | Expect 1001| %b | %b ", v0x245e5f0_0, v0x245e7f0_0, v0x245e870_0, v0x245e670_0, v0x245ebc0_0, v0x245ec40_0; + %movi 8, 14, 4; + %set/v v0x245e5f0_0, 8, 4; + %movi 8, 10, 4; + %set/v v0x245e7f0_0, 8, 4; + %set/v v0x245e870_0, 0, 3; + %delay 1000000, 0; + %vpi_call 2 199 "$display", "%b | %b | %b | %b | Expect 1000| %b | %b ", v0x245e5f0_0, v0x245e7f0_0, v0x245e870_0, v0x245e670_0, v0x245ebc0_0, v0x245ec40_0; + %movi 8, 5, 4; + %set/v v0x245e5f0_0, 8, 4; + %movi 8, 6, 4; + %set/v v0x245e7f0_0, 8, 4; + %set/v v0x245e870_0, 0, 3; + %delay 1000000, 0; + %vpi_call 2 203 "$display", "%b | %b | %b | %b | Expect XXXX| %b | %b ", v0x245e5f0_0, v0x245e7f0_0, v0x245e870_0, v0x245e670_0, v0x245ebc0_0, v0x245ec40_0; + %movi 8, 2, 4; + %set/v v0x245e5f0_0, 8, 4; + %movi 8, 7, 4; + %set/v v0x245e7f0_0, 8, 4; + %set/v v0x245e870_0, 0, 3; %delay 1000000, 0; - %vpi_call 3 64 "$display", "%b %b | %b | %b | 0 | %b", v0x2468770_0, v0x2468910_0, v0x2468a20_0, v0x2468810_0, v0x2468d20_0; - %vpi_call 3 66 "$display", "A B | Command |Out|ExpectOut|Carryout-SLT"; - %set/v v0x2468770_0, 1, 1; - %set/v v0x2468910_0, 1, 1; + %vpi_call 2 207 "$display", "%b | %b | %b | %b | Expect XXXX| %b | %b ", v0x245e5f0_0, v0x245e7f0_0, v0x245e870_0, v0x245e670_0, v0x245ebc0_0, v0x245ec40_0; + %movi 8, 7, 4; + %set/v v0x245e5f0_0, 8, 4; + %movi 8, 7, 4; + %set/v v0x245e7f0_0, 8, 4; + %set/v v0x245e870_0, 0, 3; + %delay 1000000, 0; + %vpi_call 2 211 "$display", "%b | %b | %b | %b | Expect XXXX| %b | %b ", v0x245e5f0_0, v0x245e7f0_0, v0x245e870_0, v0x245e670_0, v0x245ebc0_0, v0x245ec40_0; + %movi 8, 8, 4; + %set/v v0x245e5f0_0, 8, 4; + %set/v v0x245e7f0_0, 1, 4; + %set/v v0x245e870_0, 0, 3; + %delay 1000000, 0; + %vpi_call 2 215 "$display", "%b | %b | %b | %b | Expect XXXX| %b | %b ", v0x245e5f0_0, v0x245e7f0_0, v0x245e870_0, v0x245e670_0, v0x245ebc0_0, v0x245ec40_0; + %movi 8, 8, 4; + %set/v v0x245e5f0_0, 8, 4; + %movi 8, 13, 4; + %set/v v0x245e7f0_0, 8, 4; + %set/v v0x245e870_0, 0, 3; + %delay 1000000, 0; + %vpi_call 2 219 "$display", "%b | %b | %b | %b | Expect XXXX| %b | %b ", v0x245e5f0_0, v0x245e7f0_0, v0x245e870_0, v0x245e670_0, v0x245ebc0_0, v0x245ec40_0; + %movi 8, 11, 4; + %set/v v0x245e5f0_0, 8, 4; + %movi 8, 12, 4; + %set/v v0x245e7f0_0, 8, 4; + %set/v v0x245e870_0, 0, 3; + %delay 1000000, 0; + %vpi_call 2 223 "$display", "%b | %b | %b | %b | Expect XXXX| %b | %b ", v0x245e5f0_0, v0x245e7f0_0, v0x245e870_0, v0x245e670_0, v0x245ebc0_0, v0x245ec40_0; + %vpi_call 2 225 "$display", "Test 4 Bit SLT Functionality"; + %vpi_call 2 227 "$display", " A | B |Command| Out|ExpectedOut|Cout|OF |SLTflag"; + %movi 8, 2, 4; + %set/v v0x245e5f0_0, 8, 4; + %movi 8, 4, 4; + %set/v v0x245e7f0_0, 8, 4; + %movi 8, 3, 3; + %set/v v0x245e870_0, 8, 3; + %delay 1000000, 0; + %vpi_call 2 231 "$display", "%b | %b | %b | %b | Expect 1110| %b | %b | %b", v0x245e5f0_0, v0x245e7f0_0, v0x245e870_0, v0x245e670_0, v0x245ebc0_0, v0x245ec40_0, v0x245ea40_0; + %movi 8, 4, 4; + %set/v v0x245e5f0_0, 8, 4; + %movi 8, 2, 4; + %set/v v0x245e7f0_0, 8, 4; + %movi 8, 3, 3; + %set/v v0x245e870_0, 8, 3; + %delay 1000000, 0; + %vpi_call 2 235 "$display", "%b | %b | %b | %b | Expect 0010| %b | %b | %b", v0x245e5f0_0, v0x245e7f0_0, v0x245e870_0, v0x245e670_0, v0x245ebc0_0, v0x245ec40_0, v0x245ea40_0; + %movi 8, 14, 4; + %set/v v0x245e5f0_0, 8, 4; + %movi 8, 4, 4; + %set/v v0x245e7f0_0, 8, 4; %movi 8, 3, 3; - %set/v v0x2468a20_0, 8, 3; - %set/v v0x2468c70_0, 1, 1; + %set/v v0x245e870_0, 8, 3; %delay 1000000, 0; - %vpi_call 3 68 "$display", "%b %b | %b | %b | 0 | %b", v0x2468770_0, v0x2468910_0, v0x2468a20_0, v0x2468810_0, v0x2468d20_0; - %set/v v0x2468770_0, 1, 1; - %set/v v0x2468910_0, 0, 1; + %vpi_call 2 239 "$display", "%b | %b | %b | %b | Expect 1010| %b | %b | %b", v0x245e5f0_0, v0x245e7f0_0, v0x245e870_0, v0x245e670_0, v0x245ebc0_0, v0x245ec40_0, v0x245ea40_0; + %movi 8, 4, 4; + %set/v v0x245e5f0_0, 8, 4; + %movi 8, 14, 4; + %set/v v0x245e7f0_0, 8, 4; %movi 8, 3, 3; - %set/v v0x2468a20_0, 8, 3; - %set/v v0x2468c70_0, 1, 1; + %set/v v0x245e870_0, 8, 3; %delay 1000000, 0; - %vpi_call 3 70 "$display", "%b %b | %b | %b | 1 | %b", v0x2468770_0, v0x2468910_0, v0x2468a20_0, v0x2468810_0, v0x2468d20_0; - %set/v v0x2468770_0, 0, 1; - %set/v v0x2468910_0, 1, 1; + %vpi_call 2 243 "$display", "%b | %b | %b | %b | Expect 0110| %b | %b | %b", v0x245e5f0_0, v0x245e7f0_0, v0x245e870_0, v0x245e670_0, v0x245ebc0_0, v0x245ec40_0, v0x245ea40_0; + %movi 8, 14, 4; + %set/v v0x245e5f0_0, 8, 4; + %set/v v0x245e7f0_0, 1, 4; %movi 8, 3, 3; - %set/v v0x2468a20_0, 8, 3; - %set/v v0x2468c70_0, 1, 1; + %set/v v0x245e870_0, 8, 3; %delay 1000000, 0; - %vpi_call 3 72 "$display", "%b %b | %b | %b | 1 | %b", v0x2468770_0, v0x2468910_0, v0x2468a20_0, v0x2468810_0, v0x2468d20_0; - %set/v v0x2468770_0, 0, 1; - %set/v v0x2468910_0, 0, 1; + %vpi_call 2 247 "$display", "%b | %b | %b | %b | Expect 1111| %b | %b | %b", v0x245e5f0_0, v0x245e7f0_0, v0x245e870_0, v0x245e670_0, v0x245ebc0_0, v0x245ec40_0, v0x245ea40_0; + %set/v v0x245e5f0_0, 1, 4; + %movi 8, 14, 4; + %set/v v0x245e7f0_0, 8, 4; %movi 8, 3, 3; - %set/v v0x2468a20_0, 8, 3; - %set/v v0x2468c70_0, 1, 1; + %set/v v0x245e870_0, 8, 3; %delay 1000000, 0; - %vpi_call 3 74 "$display", "%b %b | %b | %b | 0 | %b", v0x2468770_0, v0x2468910_0, v0x2468a20_0, v0x2468810_0, v0x2468d20_0; - %vpi_call 3 76 "$display", "A B |Command|Out|ExpectOut-AND"; - %set/v v0x2468770_0, 0, 1; - %set/v v0x2468910_0, 0, 1; + %vpi_call 2 251 "$display", "%b | %b | %b | %b | Expect 0001| %b | %b | %b", v0x245e5f0_0, v0x245e7f0_0, v0x245e870_0, v0x245e670_0, v0x245ebc0_0, v0x245ec40_0, v0x245ea40_0; + %movi 8, 13, 4; + %set/v v0x245e5f0_0, 8, 4; + %movi 8, 13, 4; + %set/v v0x245e7f0_0, 8, 4; + %movi 8, 3, 3; + %set/v v0x245e870_0, 8, 3; + %delay 1000000, 0; + %vpi_call 2 255 "$display", "%b | %b | %b | %b | Expect 0000| %b | %b | %b", v0x245e5f0_0, v0x245e7f0_0, v0x245e870_0, v0x245e670_0, v0x245ebc0_0, v0x245ec40_0, v0x245ea40_0; + %movi 8, 5, 4; + %set/v v0x245e5f0_0, 8, 4; + %movi 8, 5, 4; + %set/v v0x245e7f0_0, 8, 4; + %movi 8, 3, 3; + %set/v v0x245e870_0, 8, 3; + %delay 1000000, 0; + %vpi_call 2 259 "$display", "%b | %b | %b | %b | Expect 0000| %b | %b | %b", v0x245e5f0_0, v0x245e7f0_0, v0x245e870_0, v0x245e670_0, v0x245ebc0_0, v0x245ec40_0, v0x245ea40_0; + %movi 8, 9, 4; + %set/v v0x245e5f0_0, 8, 4; + %movi 8, 5, 4; + %set/v v0x245e7f0_0, 8, 4; + %movi 8, 3, 3; + %set/v v0x245e870_0, 8, 3; + %delay 1000000, 0; + %vpi_call 2 263 "$display", "%b | %b | %b | %b | Expect XXXX| %b | %b | %b", v0x245e5f0_0, v0x245e7f0_0, v0x245e870_0, v0x245e670_0, v0x245ebc0_0, v0x245ec40_0, v0x245ea40_0; + %vpi_call 2 265 "$display", "Test 4 Bit AND/NAND Functionality"; + %vpi_call 2 267 "$display", " A | B |Command| Out |ExpectedOut-AND"; + %set/v v0x245e5f0_0, 1, 4; + %set/v v0x245e7f0_0, 1, 4; %movi 8, 4, 3; - %set/v v0x2468a20_0, 8, 3; + %set/v v0x245e870_0, 8, 3; %delay 1000000, 0; - %vpi_call 3 78 "$display", "%b %b | %b | %b | 0", v0x2468770_0, v0x2468910_0, v0x2468a20_0, v0x2468890_0; - %set/v v0x2468770_0, 0, 1; - %set/v v0x2468910_0, 1, 1; + %vpi_call 2 271 "$display", "%b | %b | %b | %b | 1111", v0x245e5f0_0, v0x245e7f0_0, v0x245e870_0, v0x245e770_0; + %set/v v0x245e5f0_0, 1, 4; + %movi 8, 10, 4; + %set/v v0x245e7f0_0, 8, 4; %movi 8, 4, 3; - %set/v v0x2468a20_0, 8, 3; + %set/v v0x245e870_0, 8, 3; %delay 1000000, 0; - %vpi_call 3 80 "$display", "%b %b | %b | %b | 0", v0x2468770_0, v0x2468910_0, v0x2468a20_0, v0x2468890_0; - %set/v v0x2468770_0, 1, 1; - %set/v v0x2468910_0, 0, 1; + %vpi_call 2 275 "$display", "%b | %b | %b | %b | 1010", v0x245e5f0_0, v0x245e7f0_0, v0x245e870_0, v0x245e770_0; + %set/v v0x245e5f0_0, 1, 4; + %movi 8, 5, 4; + %set/v v0x245e7f0_0, 8, 4; %movi 8, 4, 3; - %set/v v0x2468a20_0, 8, 3; + %set/v v0x245e870_0, 8, 3; %delay 1000000, 0; - %vpi_call 3 82 "$display", "%b %b | %b | %b | 0", v0x2468770_0, v0x2468910_0, v0x2468a20_0, v0x2468890_0; - %set/v v0x2468770_0, 1, 1; - %set/v v0x2468910_0, 1, 1; + %vpi_call 2 279 "$display", "%b | %b | %b | %b | 0101", v0x245e5f0_0, v0x245e7f0_0, v0x245e870_0, v0x245e770_0; + %set/v v0x245e5f0_0, 1, 4; + %set/v v0x245e7f0_0, 0, 4; %movi 8, 4, 3; - %set/v v0x2468a20_0, 8, 3; + %set/v v0x245e870_0, 8, 3; %delay 1000000, 0; - %vpi_call 3 84 "$display", "%b %b | %b | %b | 1", v0x2468770_0, v0x2468910_0, v0x2468a20_0, v0x2468890_0; - %vpi_call 3 85 "$display", "A B |Command|Out|ExpectOut-NAND"; - %set/v v0x2468770_0, 0, 1; - %set/v v0x2468910_0, 0, 1; + %vpi_call 2 283 "$display", "%b | %b | %b | %b | 0000", v0x245e5f0_0, v0x245e7f0_0, v0x245e870_0, v0x245e770_0; + %vpi_call 2 286 "$display", " A | B |Command| Out |ExpectedOut-NAND"; + %set/v v0x245e5f0_0, 1, 4; + %set/v v0x245e7f0_0, 1, 4; %movi 8, 5, 3; - %set/v v0x2468a20_0, 8, 3; + %set/v v0x245e870_0, 8, 3; %delay 1000000, 0; - %vpi_call 3 87 "$display", "%b %b | %b | %b | 1", v0x2468770_0, v0x2468910_0, v0x2468a20_0, v0x2468890_0; - %set/v v0x2468770_0, 0, 1; - %set/v v0x2468910_0, 1, 1; + %vpi_call 2 290 "$display", "%b | %b | %b | %b | 0000", v0x245e5f0_0, v0x245e7f0_0, v0x245e870_0, v0x245e770_0; + %set/v v0x245e5f0_0, 1, 4; + %movi 8, 10, 4; + %set/v v0x245e7f0_0, 8, 4; %movi 8, 5, 3; - %set/v v0x2468a20_0, 8, 3; + %set/v v0x245e870_0, 8, 3; %delay 1000000, 0; - %vpi_call 3 89 "$display", "%b %b | %b | %b | 1", v0x2468770_0, v0x2468910_0, v0x2468a20_0, v0x2468890_0; - %set/v v0x2468770_0, 1, 1; - %set/v v0x2468910_0, 0, 1; + %vpi_call 2 294 "$display", "%b | %b | %b | %b | 0101", v0x245e5f0_0, v0x245e7f0_0, v0x245e870_0, v0x245e770_0; + %set/v v0x245e5f0_0, 1, 4; + %movi 8, 5, 4; + %set/v v0x245e7f0_0, 8, 4; %movi 8, 5, 3; - %set/v v0x2468a20_0, 8, 3; + %set/v v0x245e870_0, 8, 3; %delay 1000000, 0; - %vpi_call 3 91 "$display", "%b %b | %b | %b | 1", v0x2468770_0, v0x2468910_0, v0x2468a20_0, v0x2468890_0; - %set/v v0x2468770_0, 1, 1; - %set/v v0x2468910_0, 1, 1; + %vpi_call 2 298 "$display", "%b | %b | %b | %b | 1010", v0x245e5f0_0, v0x245e7f0_0, v0x245e870_0, v0x245e770_0; + %set/v v0x245e5f0_0, 1, 4; + %set/v v0x245e7f0_0, 0, 4; %movi 8, 5, 3; - %set/v v0x2468a20_0, 8, 3; + %set/v v0x245e870_0, 8, 3; %delay 1000000, 0; - %vpi_call 3 93 "$display", "%b %b | %b | %b | 0", v0x2468770_0, v0x2468910_0, v0x2468a20_0, v0x2468890_0; - %vpi_call 3 95 "$display", "A B |Command|Out|ExpectOut-OR"; - %set/v v0x2468770_0, 1, 1; - %set/v v0x2468910_0, 1, 1; - %set/v v0x2468a20_0, 1, 3; + %vpi_call 2 302 "$display", "%b | %b | %b | %b | 1111", v0x245e5f0_0, v0x245e7f0_0, v0x245e870_0, v0x245e770_0; + %vpi_call 2 304 "$display", "Test 4 Bit OR/NOR/XOR Functionality"; + %vpi_call 2 306 "$display", " A | B |Command | Out |ExpectedOut-OR"; + %movi 8, 10, 4; + %set/v v0x245e5f0_0, 8, 4; + %movi 8, 5, 4; + %set/v v0x245e7f0_0, 8, 4; + %set/v v0x245e870_0, 1, 3; %delay 1000000, 0; - %vpi_call 3 97 "$display", "%b %b | %b | %b | 1", v0x2468770_0, v0x2468910_0, v0x2468a20_0, v0x2468aa0_0; - %set/v v0x2468770_0, 1, 1; - %set/v v0x2468910_0, 0, 1; - %set/v v0x2468a20_0, 1, 3; + %vpi_call 2 310 "$display", "%b | %b | %b | %b | 1111", v0x245e5f0_0, v0x245e7f0_0, v0x245e870_0, v0x245e970_0; + %set/v v0x245e5f0_0, 1, 4; + %movi 8, 5, 4; + %set/v v0x245e7f0_0, 8, 4; + %set/v v0x245e870_0, 1, 3; %delay 1000000, 0; - %vpi_call 3 99 "$display", "%b %b | %b | %b | 1", v0x2468770_0, v0x2468910_0, v0x2468a20_0, v0x2468aa0_0; - %set/v v0x2468770_0, 0, 1; - %set/v v0x2468910_0, 1, 1; - %set/v v0x2468a20_0, 1, 3; + %vpi_call 2 314 "$display", "%b | %b | %b | %b | 1111", v0x245e5f0_0, v0x245e7f0_0, v0x245e870_0, v0x245e970_0; + %movi 8, 11, 4; + %set/v v0x245e5f0_0, 8, 4; + %set/v v0x245e7f0_0, 0, 4; + %set/v v0x245e870_0, 1, 3; %delay 1000000, 0; - %vpi_call 3 101 "$display", "%b %b | %b | %b | 1", v0x2468770_0, v0x2468910_0, v0x2468a20_0, v0x2468aa0_0; - %set/v v0x2468770_0, 0, 1; - %set/v v0x2468910_0, 0, 1; - %set/v v0x2468a20_0, 1, 3; - %delay 1000000, 0; - %vpi_call 3 103 "$display", "%b %b | %b | %b | 0", v0x2468770_0, v0x2468910_0, v0x2468a20_0, v0x2468aa0_0; - %vpi_call 3 104 "$display", "A B |Command|Out|ExpectOut-NOR"; - %set/v v0x2468770_0, 1, 1; - %set/v v0x2468910_0, 1, 1; + %vpi_call 2 318 "$display", "%b | %b | %b | %b | 1011", v0x245e5f0_0, v0x245e7f0_0, v0x245e870_0, v0x245e970_0; + %vpi_call 2 320 "$display", " A | B |Command | Out |ExpectedOut-NOR"; + %movi 8, 10, 4; + %set/v v0x245e5f0_0, 8, 4; + %movi 8, 5, 4; + %set/v v0x245e7f0_0, 8, 4; %movi 8, 6, 3; - %set/v v0x2468a20_0, 8, 3; + %set/v v0x245e870_0, 8, 3; %delay 1000000, 0; - %vpi_call 3 106 "$display", "%b %b | %b | %b | 0", v0x2468770_0, v0x2468910_0, v0x2468a20_0, v0x2468aa0_0; - %set/v v0x2468770_0, 1, 1; - %set/v v0x2468910_0, 0, 1; + %vpi_call 2 324 "$display", "%b | %b | %b | %b | 0000", v0x245e5f0_0, v0x245e7f0_0, v0x245e870_0, v0x245e970_0; + %set/v v0x245e5f0_0, 1, 4; + %movi 8, 5, 4; + %set/v v0x245e7f0_0, 8, 4; %movi 8, 6, 3; - %set/v v0x2468a20_0, 8, 3; + %set/v v0x245e870_0, 8, 3; %delay 1000000, 0; - %vpi_call 3 108 "$display", "%b %b | %b | %b | 0", v0x2468770_0, v0x2468910_0, v0x2468a20_0, v0x2468aa0_0; - %set/v v0x2468770_0, 0, 1; - %set/v v0x2468910_0, 1, 1; + %vpi_call 2 328 "$display", "%b | %b | %b | %b | 0000", v0x245e5f0_0, v0x245e7f0_0, v0x245e870_0, v0x245e970_0; + %movi 8, 11, 4; + %set/v v0x245e5f0_0, 8, 4; + %set/v v0x245e7f0_0, 0, 4; %movi 8, 6, 3; - %set/v v0x2468a20_0, 8, 3; + %set/v v0x245e870_0, 8, 3; %delay 1000000, 0; - %vpi_call 3 110 "$display", "%b %b | %b | %b | 0", v0x2468770_0, v0x2468910_0, v0x2468a20_0, v0x2468aa0_0; - %set/v v0x2468770_0, 0, 1; - %set/v v0x2468910_0, 0, 1; - %movi 8, 6, 3; - %set/v v0x2468a20_0, 8, 3; + %vpi_call 2 332 "$display", "%b | %b | %b | %b | 0100", v0x245e5f0_0, v0x245e7f0_0, v0x245e870_0, v0x245e970_0; + %vpi_call 2 334 "$display", " A | B |Command | Out |ExpectedOut-XOR"; + %movi 8, 10, 4; + %set/v v0x245e5f0_0, 8, 4; + %movi 8, 5, 4; + %set/v v0x245e7f0_0, 8, 4; + %movi 8, 2, 3; + %set/v v0x245e870_0, 8, 3; %delay 1000000, 0; - %vpi_call 3 112 "$display", "%b %b | %b | %b | 1", v0x2468770_0, v0x2468910_0, v0x2468a20_0, v0x2468aa0_0; - %vpi_call 3 113 "$display", "A B |Command|Out|ExpectOut-XOR"; - %set/v v0x2468770_0, 1, 1; - %set/v v0x2468910_0, 1, 1; + %vpi_call 2 338 "$display", "%b | %b | %b | %b | 1111", v0x245e5f0_0, v0x245e7f0_0, v0x245e870_0, v0x245e970_0; + %set/v v0x245e5f0_0, 1, 4; + %movi 8, 5, 4; + %set/v v0x245e7f0_0, 8, 4; %movi 8, 2, 3; - %set/v v0x2468a20_0, 8, 3; + %set/v v0x245e870_0, 8, 3; %delay 1000000, 0; - %vpi_call 3 115 "$display", "%b %b | %b | %b | 0", v0x2468770_0, v0x2468910_0, v0x2468a20_0, v0x2468aa0_0; - %set/v v0x2468770_0, 1, 1; - %set/v v0x2468910_0, 0, 1; + %vpi_call 2 342 "$display", "%b | %b | %b | %b | 1010", v0x245e5f0_0, v0x245e7f0_0, v0x245e870_0, v0x245e970_0; + %movi 8, 11, 4; + %set/v v0x245e5f0_0, 8, 4; + %set/v v0x245e7f0_0, 0, 4; %movi 8, 2, 3; - %set/v v0x2468a20_0, 8, 3; + %set/v v0x245e870_0, 8, 3; + %delay 1000000, 0; + %vpi_call 2 346 "$display", "%b | %b | %b | %b | 1011", v0x245e5f0_0, v0x245e7f0_0, v0x245e870_0, v0x245e970_0; + %vpi_call 2 348 "$display", "Test 4 Bit ALU Functionality"; + %vpi_call 2 350 "$display", " A | B |Command | Out |ExpectedOut | COut | OF |SLT|Zero"; + %set/v v0x245e5f0_0, 1, 4; + %set/v v0x245e7f0_0, 1, 4; + %movi 8, 4, 3; + %set/v v0x245e870_0, 8, 3; + %delay 1000000, 0; + %vpi_call 2 355 "$display", "%b | %b | %b - AND | %b | 1111 | %b | %b | %b | %b", v0x245e5f0_0, v0x245e7f0_0, v0x245e870_0, v0x245e8f0_0, v0x245ebc0_0, v0x245ec40_0, v0x245ea40_0, v0x245e6f0_0; + %set/v v0x245e5f0_0, 1, 4; + %set/v v0x245e7f0_0, 0, 4; + %movi 8, 5, 3; + %set/v v0x245e870_0, 8, 3; + %delay 1000000, 0; + %vpi_call 2 360 "$display", "%b | %b | %b - NAND | %b | 1111 | %b | %b | %b | %b", v0x245e5f0_0, v0x245e7f0_0, v0x245e870_0, v0x245e8f0_0, v0x245ebc0_0, v0x245ec40_0, v0x245ea40_0, v0x245e6f0_0; + %set/v v0x245e5f0_0, 1, 4; + %movi 8, 5, 4; + %set/v v0x245e7f0_0, 8, 4; + %set/v v0x245e870_0, 1, 3; + %delay 1000000, 0; + %vpi_call 2 365 "$display", "%b | %b | %b - OR | %b | 1111 | %b | %b | %b | %b", v0x245e5f0_0, v0x245e7f0_0, v0x245e870_0, v0x245e8f0_0, v0x245ebc0_0, v0x245ec40_0, v0x245ea40_0, v0x245e6f0_0; + %movi 8, 11, 4; + %set/v v0x245e5f0_0, 8, 4; + %set/v v0x245e7f0_0, 0, 4; + %movi 8, 6, 3; + %set/v v0x245e870_0, 8, 3; %delay 1000000, 0; - %vpi_call 3 117 "$display", "%b %b | %b | %b | 1", v0x2468770_0, v0x2468910_0, v0x2468a20_0, v0x2468aa0_0; - %set/v v0x2468770_0, 0, 1; - %set/v v0x2468910_0, 1, 1; + %vpi_call 2 370 "$display", "%b | %b | %b - NOR | %b | 0100 | %b | %b | %b | %b", v0x245e5f0_0, v0x245e7f0_0, v0x245e870_0, v0x245e8f0_0, v0x245ebc0_0, v0x245ec40_0, v0x245ea40_0, v0x245e6f0_0; + %movi 8, 11, 4; + %set/v v0x245e5f0_0, 8, 4; + %set/v v0x245e7f0_0, 0, 4; %movi 8, 2, 3; - %set/v v0x2468a20_0, 8, 3; + %set/v v0x245e870_0, 8, 3; + %delay 1000000, 0; + %vpi_call 2 375 "$display", "%b | %b | %b - XOR | %b | 1011 | %b | %b | %b | %b", v0x245e5f0_0, v0x245e7f0_0, v0x245e870_0, v0x245e8f0_0, v0x245ebc0_0, v0x245ec40_0, v0x245ea40_0, v0x245e6f0_0; + %movi 8, 2, 4; + %set/v v0x245e5f0_0, 8, 4; + %movi 8, 4, 4; + %set/v v0x245e7f0_0, 8, 4; + %set/v v0x245e870_0, 0, 3; + %delay 1000000, 0; + %vpi_call 2 380 "$display", "%b | %b | %b - ADD | %b | 0110 | %b | %b | %b | %b", v0x245e5f0_0, v0x245e7f0_0, v0x245e870_0, v0x245e8f0_0, v0x245ebc0_0, v0x245ec40_0, v0x245ea40_0, v0x245e6f0_0; + %movi 8, 11, 4; + %set/v v0x245e5f0_0, 8, 4; + %movi 8, 12, 4; + %set/v v0x245e7f0_0, 8, 4; + %set/v v0x245e870_0, 0, 3; + %delay 1000000, 0; + %vpi_call 2 384 "$display", "%b | %b | %b - ADD | %b | XXXX | %b | %b | %b | %b", v0x245e5f0_0, v0x245e7f0_0, v0x245e870_0, v0x245e8f0_0, v0x245ebc0_0, v0x245ec40_0, v0x245ea40_0, v0x245e6f0_0; + %movi 8, 2, 4; + %set/v v0x245e5f0_0, 8, 4; + %movi 8, 4, 4; + %set/v v0x245e7f0_0, 8, 4; + %movi 8, 1, 3; + %set/v v0x245e870_0, 8, 3; + %delay 1000000, 0; + %vpi_call 2 389 "$display", "%b | %b | %b - SUB | %b | 1110 | %b | %b | %b | %b", v0x245e5f0_0, v0x245e7f0_0, v0x245e870_0, v0x245e8f0_0, v0x245ebc0_0, v0x245ec40_0, v0x245ea40_0, v0x245e6f0_0; + %movi 8, 9, 4; + %set/v v0x245e5f0_0, 8, 4; + %movi 8, 3, 4; + %set/v v0x245e7f0_0, 8, 4; + %movi 8, 1, 3; + %set/v v0x245e870_0, 8, 3; + %delay 1000000, 0; + %vpi_call 2 393 "$display", "%b | %b | %b - SUB | %b | XXXX | %b | %b | %b | %b", v0x245e5f0_0, v0x245e7f0_0, v0x245e870_0, v0x245e8f0_0, v0x245ebc0_0, v0x245ec40_0, v0x245ea40_0, v0x245e6f0_0; + %movi 8, 4, 4; + %set/v v0x245e5f0_0, 8, 4; + %movi 8, 2, 4; + %set/v v0x245e7f0_0, 8, 4; + %movi 8, 3, 3; + %set/v v0x245e870_0, 8, 3; %delay 1000000, 0; - %vpi_call 3 119 "$display", "%b %b | %b | %b | 1 ", v0x2468770_0, v0x2468910_0, v0x2468a20_0, v0x2468aa0_0; - %set/v v0x2468770_0, 0, 1; - %set/v v0x2468910_0, 0, 1; + %vpi_call 2 399 "$display", "%b | %b | %b - SLT | %b | 0010 | %b | %b | %b | %b", v0x245e5f0_0, v0x245e7f0_0, v0x245e870_0, v0x245e8f0_0, v0x245ebc0_0, v0x245ec40_0, v0x245ea40_0, v0x245e6f0_0; + %movi 8, 9, 4; + %set/v v0x245e5f0_0, 8, 4; + %movi 8, 5, 4; + %set/v v0x245e7f0_0, 8, 4; + %movi 8, 3, 3; + %set/v v0x245e870_0, 8, 3; + %delay 1000000, 0; + %vpi_call 2 403 "$display", "%b | %b | %b - SLT | %b | XXXX | %b | %b | %b | %b", v0x245e5f0_0, v0x245e7f0_0, v0x245e870_0, v0x245e8f0_0, v0x245ebc0_0, v0x245ec40_0, v0x245ea40_0, v0x245e6f0_0; + %set/v v0x245e5f0_0, 0, 4; + %set/v v0x245e7f0_0, 1, 4; + %movi 8, 4, 3; + %set/v v0x245e870_0, 8, 3; + %delay 1000000, 0; + %vpi_call 2 409 "$display", "%b | %b | %b - AND | %b | 0000 | %b | %b | %b | %b", v0x245e5f0_0, v0x245e7f0_0, v0x245e870_0, v0x245e8f0_0, v0x245ebc0_0, v0x245ec40_0, v0x245ea40_0, v0x245e6f0_0; + %set/v v0x245e5f0_0, 1, 4; + %set/v v0x245e7f0_0, 1, 4; + %movi 8, 5, 3; + %set/v v0x245e870_0, 8, 3; + %delay 1000000, 0; + %vpi_call 2 412 "$display", "%b | %b | %b - NAND | %b | 0000 | %b | %b | %b | %b", v0x245e5f0_0, v0x245e7f0_0, v0x245e870_0, v0x245e8f0_0, v0x245ebc0_0, v0x245ec40_0, v0x245ea40_0, v0x245e6f0_0; + %set/v v0x245e5f0_0, 0, 4; + %set/v v0x245e7f0_0, 0, 4; + %set/v v0x245e870_0, 1, 3; + %delay 1000000, 0; + %vpi_call 2 415 "$display", "%b | %b | %b - OR | %b | 0000 | %b | %b | %b | %b", v0x245e5f0_0, v0x245e7f0_0, v0x245e870_0, v0x245e8f0_0, v0x245ebc0_0, v0x245ec40_0, v0x245ea40_0, v0x245e6f0_0; + %movi 8, 11, 4; + %set/v v0x245e5f0_0, 8, 4; + %movi 8, 4, 4; + %set/v v0x245e7f0_0, 8, 4; + %movi 8, 6, 3; + %set/v v0x245e870_0, 8, 3; + %delay 1000000, 0; + %vpi_call 2 417 "$display", "%b | %b | %b - NOR | %b | 0000 | %b | %b | %b | %b", v0x245e5f0_0, v0x245e7f0_0, v0x245e870_0, v0x245e8f0_0, v0x245ebc0_0, v0x245ec40_0, v0x245ea40_0, v0x245e6f0_0; + %movi 8, 11, 4; + %set/v v0x245e5f0_0, 8, 4; + %movi 8, 11, 4; + %set/v v0x245e7f0_0, 8, 4; %movi 8, 2, 3; - %set/v v0x2468a20_0, 8, 3; + %set/v v0x245e870_0, 8, 3; + %delay 1000000, 0; + %vpi_call 2 420 "$display", "%b | %b | %b - XOR | %b | 0000 | %b | %b | %b | %b", v0x245e5f0_0, v0x245e7f0_0, v0x245e870_0, v0x245e8f0_0, v0x245ebc0_0, v0x245ec40_0, v0x245ea40_0, v0x245e6f0_0; + %movi 8, 2, 4; + %set/v v0x245e5f0_0, 8, 4; + %movi 8, 14, 4; + %set/v v0x245e7f0_0, 8, 4; + %set/v v0x245e870_0, 0, 3; + %delay 1000000, 0; + %vpi_call 2 423 "$display", "%b | %b | %b - ADD | %b | 0000 | %b | %b | %b | %b", v0x245e5f0_0, v0x245e7f0_0, v0x245e870_0, v0x245e8f0_0, v0x245ebc0_0, v0x245ec40_0, v0x245ea40_0, v0x245e6f0_0; + %movi 8, 2, 4; + %set/v v0x245e5f0_0, 8, 4; + %movi 8, 2, 4; + %set/v v0x245e7f0_0, 8, 4; + %movi 8, 1, 3; + %set/v v0x245e870_0, 8, 3; %delay 1000000, 0; - %vpi_call 3 121 "$display", "%b %b | %b | %b | 0", v0x2468770_0, v0x2468910_0, v0x2468a20_0, v0x2468aa0_0; + %vpi_call 2 426 "$display", "%b | %b | %b - SUB | %b | 0000 | %b | %b | %b | %b", v0x245e5f0_0, v0x245e7f0_0, v0x245e870_0, v0x245e8f0_0, v0x245ebc0_0, v0x245ec40_0, v0x245ea40_0, v0x245e6f0_0; + %set/v v0x245e5f0_0, 0, 4; + %set/v v0x245e7f0_0, 0, 4; + %movi 8, 3, 3; + %set/v v0x245e870_0, 8, 3; + %delay 1000000, 0; + %vpi_call 2 430 "$display", "%b | %b | %b - SLT | %b | 0000 | %b | %b | %b | %b", v0x245e5f0_0, v0x245e7f0_0, v0x245e870_0, v0x245e8f0_0, v0x245ebc0_0, v0x245ec40_0, v0x245ea40_0, v0x245e6f0_0; %end; .thread T_0; # The file index is used to find the file name in the following table. :file_names 4; "N/A"; ""; - "./alu.v"; "testing.t.v"; + "./alu.v"; diff --git a/testing.t.v b/testing.t.v index d2c43b6..1fb0369 100644 --- a/testing.t.v +++ b/testing.t.v @@ -2,7 +2,7 @@ `timescale 1 ns / 1 ps `include "alu.v" - +/* module testBasicFunctions(); // we begin by testing the basic AND/NAND, OR/NOR/XOR, and ADD/SUB/SLT modules wire AndNandOut; @@ -30,7 +30,7 @@ initial begin // test mux - /*$display("Four Input Multiplexer"); + $display("Four Input Multiplexer"); $display("S0 S1 |in0 in1 in2 in3| Output"); S0 = 0; S1 = 0; in0 = 1'bx; in1 = 0; in2 = 0; in3 = 0; #1000 $display(" %b %b | %b %b %b %b | %b", S0, S1, in0, in1, in2, in3, muxout); @@ -39,7 +39,7 @@ initial begin S0 = 0; S1 = 1; in0 = 0; in1 = 0; in2 = 1'bx; in3 = 0; #1000 $display(" %b %b | %b %b %b %b | %b", S0, S1, in0, in1, in2, in3, muxout); S0 = 1; S1 = 1; in0 = 0; in1 = 0; in2 = 0; in3 = 1'bx; #1000 - $display(" %b %b | %b %b %b %b | %b", S0, S1, in0, in1, in2, in3, muxout);*/ + $display(" %b %b | %b %b %b %b | %b", S0, S1, in0, in1, in2, in3, muxout); // just the adder - proper behavior $display("Adder/Subtractor"); $display("A B | Command |Out|ExpectOut|Carryout-Add"); @@ -121,11 +121,10 @@ initial begin $display("%b %b | %b | %b | 0", A, B, Command, OrNorXorOut); end endmodule +*/ - -/* module test32Adder(); -parameter size = 32; +parameter size = 4; output [size-1:0] OneBitFinalOut; output [size-1:0] OrNorXorOut; output [size-1:0] AndNandOut; @@ -185,7 +184,7 @@ $display("%b | %b | %b | %b | Expect 1110| %b | %b ", A, B, Command, AddSubSLTSu //Pos + Neg = 0 | -5 + 5 = 0 | -5 = 1101 | 5 = 0101 | 0 = 0000 | NO OVERFLOW A = 4'b1011; B = 4'b0101; Command =3'b000; #1000 -$display("%b | %b | %b | %b | Expect 0110| %b | %b ", A, B, Command, AddSubSLTSum, carryout, overflow); +$display("%b | %b | %b | %b | Expect 0000| %b | %b ", A, B, Command, AddSubSLTSum, carryout, overflow); //Pos + Neg = 0 | -7 + 7 = 0 | -7 = 1001 | 7 = 0111 | 0 = 0000 | NO OVERFLOW A = 4'b0111; B = 4'b1001; Command =3'b000; #1000 @@ -433,7 +432,5 @@ A = 4'b0000; B = 4'b0000; Command =3'b011; #1000 end endmodule -*/ - From dc52e1d457dc651c34d8df8eac642034d75d01d0 Mon Sep 17 00:00:00 2001 From: mjakus Date: Tue, 10 Oct 2017 18:27:02 -0400 Subject: [PATCH 24/28] actually got slt working --- FullALU.vcd | 46918 +++++++++++++++++++++++++++++++------------------- alu.v | 120 +- test | 5563 +++--- testing.t.v | 5 +- 4 files changed, 32174 insertions(+), 20432 deletions(-) diff --git a/FullALU.vcd b/FullALU.vcd index 42feeac..ee1d5b2 100644 --- a/FullALU.vcd +++ b/FullALU.vcd @@ -1,5 +1,5 @@ $date - Tue Oct 10 17:34:37 2017 + Tue Oct 10 18:24:46 2017 $end $version Icarus Verilog @@ -13,935 +13,1329 @@ $var wire 1 " AllZeros $end $var wire 4 # AndNandOut [3:0] $end $var wire 4 $ OneBitFinalOut [3:0] $end $var wire 4 % OrNorXorOut [3:0] $end -$var wire 1 & SLTflag $end -$var wire 4 ' ZeroFlag [3:0] $end -$var wire 1 ( carryout $end -$var wire 1 ) overflow $end -$var wire 4 * subtract [3:0] $end -$var reg 4 + A [3:0] $end -$var reg 4 , B [3:0] $end -$var reg 3 - Command [2:0] $end -$var reg 4 . carryin [3:0] $end +$var wire 4 & SLTSum [3:0] $end +$var wire 1 ' SLTflag $end +$var wire 4 ( ZeroFlag [3:0] $end +$var wire 1 ) carryout $end +$var wire 1 * overflow $end +$var wire 4 + subtract [3:0] $end +$var reg 4 , A [3:0] $end +$var reg 4 - B [3:0] $end +$var reg 3 . Command [2:0] $end +$var reg 4 / carryin [3:0] $end $scope module trial $end -$var wire 4 / A [3:0] $end -$var wire 4 0 AddSubSLTSum [3:0] $end -$var wire 4 1 B [3:0] $end -$var wire 4 2 CarryoutWire [3:0] $end -$var wire 3 3 Command [2:0] $end -$var wire 4 4 NewVal [3:0] $end -$var wire 1 5 Res0OF1 $end -$var wire 1 6 Res1OF0 $end -$var wire 1 & SLTflag $end -$var wire 1 7 SLTflag0 $end -$var wire 1 8 SLTflag1 $end -$var wire 1 9 SLTon $end -$var wire 4 : carryin [3:0] $end -$var wire 1 ( carryout $end -$var wire 1 ; nAddSubSLTSum $end -$var wire 1 < nCmd2 $end -$var wire 1 = nOF $end -$var wire 1 ) overflow $end -$var wire 4 > subtract [3:0] $end +$var wire 4 0 A [3:0] $end +$var wire 4 1 AddSubSLTSum [3:0] $end +$var wire 4 2 B [3:0] $end +$var wire 4 3 CarryoutWire [3:0] $end +$var wire 3 4 Command [2:0] $end +$var wire 4 5 NewVal [3:0] $end +$var wire 1 6 Res0OF1 $end +$var wire 1 7 Res1OF0 $end +$var wire 1 ' SLTflag $end +$var wire 1 8 SLTflag0 $end +$var wire 1 9 SLTflag1 $end +$var wire 1 : SLTon $end +$var wire 4 ; carryin [3:0] $end +$var wire 1 ) carryout $end +$var wire 1 < nAddSubSLTSum $end +$var wire 1 = nCmd2 $end +$var wire 1 > nOF $end +$var wire 1 * overflow $end +$var wire 4 ? subtract [3:0] $end $scope module attempt2 $end -$var wire 1 ? A $end -$var wire 1 @ AandB $end -$var wire 1 A AddSubSLTSum $end -$var wire 1 B AxorB $end -$var wire 1 C B $end -$var wire 1 D BornB $end -$var wire 1 E CINandAxorB $end -$var wire 3 F Command [2:0] $end -$var wire 1 G carryin $end -$var wire 1 H carryout $end -$var wire 1 I nB $end -$var wire 1 J nCmd2 $end -$var wire 1 K subtract $end +$var wire 1 @ A $end +$var wire 1 A AandB $end +$var wire 1 B AddSubSLTSum $end +$var wire 1 C AxorB $end +$var wire 1 D B $end +$var wire 1 E BornB $end +$var wire 1 F CINandAxorB $end +$var wire 3 G Command [2:0] $end +$var wire 1 H carryin $end +$var wire 1 I carryout $end +$var wire 1 J nB $end +$var wire 1 K nCmd2 $end +$var wire 1 L subtract $end $scope module mux0 $end -$var wire 1 L S $end -$var wire 1 C in0 $end -$var wire 1 I in1 $end -$var wire 1 M nS $end -$var wire 1 N out0 $end -$var wire 1 O out1 $end -$var wire 1 D outfinal $end +$var wire 1 M S $end +$var wire 1 D in0 $end +$var wire 1 J in1 $end +$var wire 1 N nS $end +$var wire 1 O out0 $end +$var wire 1 P out1 $end +$var wire 1 E outfinal $end $upscope $end $upscope $end $scope module setSLTres $end -$var wire 1 9 S $end -$var wire 1 P in0 $end -$var wire 1 Q in1 $end -$var wire 1 R nS $end -$var wire 1 S out0 $end -$var wire 1 T out1 $end -$var wire 1 U outfinal $end +$var wire 1 : S $end +$var wire 1 Q in0 $end +$var wire 1 R in1 $end +$var wire 1 S nS $end +$var wire 1 T out0 $end +$var wire 1 U out1 $end +$var wire 1 V outfinal $end $upscope $end $scope begin addbits[1] $end $scope module attempt $end -$var wire 1 V A $end -$var wire 1 W AandB $end -$var wire 1 X AddSubSLTSum $end -$var wire 1 Y AxorB $end -$var wire 1 Z B $end -$var wire 1 [ BornB $end -$var wire 1 \ CINandAxorB $end -$var wire 3 ] Command [2:0] $end -$var wire 1 ^ carryin $end -$var wire 1 _ carryout $end -$var wire 1 ` nB $end -$var wire 1 a nCmd2 $end -$var wire 1 b subtract $end +$var wire 1 W A $end +$var wire 1 X AandB $end +$var wire 1 Y AddSubSLTSum $end +$var wire 1 Z AxorB $end +$var wire 1 [ B $end +$var wire 1 \ BornB $end +$var wire 1 ] CINandAxorB $end +$var wire 3 ^ Command [2:0] $end +$var wire 1 _ carryin $end +$var wire 1 ` carryout $end +$var wire 1 a nB $end +$var wire 1 b nCmd2 $end +$var wire 1 c subtract $end $scope module mux0 $end -$var wire 1 c S $end -$var wire 1 Z in0 $end -$var wire 1 ` in1 $end -$var wire 1 d nS $end -$var wire 1 e out0 $end -$var wire 1 f out1 $end -$var wire 1 [ outfinal $end +$var wire 1 d S $end +$var wire 1 [ in0 $end +$var wire 1 a in1 $end +$var wire 1 e nS $end +$var wire 1 f out0 $end +$var wire 1 g out1 $end +$var wire 1 \ outfinal $end $upscope $end $upscope $end $scope module setSLTres $end -$var wire 1 9 S $end -$var wire 1 g in0 $end -$var wire 1 h in1 $end -$var wire 1 i nS $end -$var wire 1 j out0 $end -$var wire 1 k out1 $end -$var wire 1 l outfinal $end +$var wire 1 : S $end +$var wire 1 h in0 $end +$var wire 1 i in1 $end +$var wire 1 j nS $end +$var wire 1 k out0 $end +$var wire 1 l out1 $end +$var wire 1 m outfinal $end $upscope $end $upscope $end $scope begin addbits[2] $end $scope module attempt $end -$var wire 1 m A $end -$var wire 1 n AandB $end -$var wire 1 o AddSubSLTSum $end -$var wire 1 p AxorB $end -$var wire 1 q B $end -$var wire 1 r BornB $end -$var wire 1 s CINandAxorB $end -$var wire 3 t Command [2:0] $end -$var wire 1 u carryin $end -$var wire 1 v carryout $end -$var wire 1 w nB $end -$var wire 1 x nCmd2 $end -$var wire 1 y subtract $end +$var wire 1 n A $end +$var wire 1 o AandB $end +$var wire 1 p AddSubSLTSum $end +$var wire 1 q AxorB $end +$var wire 1 r B $end +$var wire 1 s BornB $end +$var wire 1 t CINandAxorB $end +$var wire 3 u Command [2:0] $end +$var wire 1 v carryin $end +$var wire 1 w carryout $end +$var wire 1 x nB $end +$var wire 1 y nCmd2 $end +$var wire 1 z subtract $end $scope module mux0 $end -$var wire 1 z S $end -$var wire 1 q in0 $end -$var wire 1 w in1 $end -$var wire 1 { nS $end -$var wire 1 | out0 $end -$var wire 1 } out1 $end -$var wire 1 r outfinal $end +$var wire 1 { S $end +$var wire 1 r in0 $end +$var wire 1 x in1 $end +$var wire 1 | nS $end +$var wire 1 } out0 $end +$var wire 1 ~ out1 $end +$var wire 1 s outfinal $end $upscope $end $upscope $end $scope module setSLTres $end -$var wire 1 9 S $end -$var wire 1 ~ in0 $end -$var wire 1 !" in1 $end -$var wire 1 "" nS $end -$var wire 1 #" out0 $end -$var wire 1 $" out1 $end -$var wire 1 %" outfinal $end +$var wire 1 : S $end +$var wire 1 !" in0 $end +$var wire 1 "" in1 $end +$var wire 1 #" nS $end +$var wire 1 $" out0 $end +$var wire 1 %" out1 $end +$var wire 1 &" outfinal $end $upscope $end $upscope $end $scope begin addbits[3] $end $scope module attempt $end -$var wire 1 &" A $end -$var wire 1 '" AandB $end -$var wire 1 (" AddSubSLTSum $end -$var wire 1 )" AxorB $end -$var wire 1 *" B $end -$var wire 1 +" BornB $end -$var wire 1 ," CINandAxorB $end -$var wire 3 -" Command [2:0] $end -$var wire 1 ." carryin $end -$var wire 1 /" carryout $end -$var wire 1 0" nB $end -$var wire 1 1" nCmd2 $end -$var wire 1 2" subtract $end +$var wire 1 '" A $end +$var wire 1 (" AandB $end +$var wire 1 )" AddSubSLTSum $end +$var wire 1 *" AxorB $end +$var wire 1 +" B $end +$var wire 1 ," BornB $end +$var wire 1 -" CINandAxorB $end +$var wire 3 ." Command [2:0] $end +$var wire 1 /" carryin $end +$var wire 1 0" carryout $end +$var wire 1 1" nB $end +$var wire 1 2" nCmd2 $end +$var wire 1 3" subtract $end $scope module mux0 $end -$var wire 1 3" S $end -$var wire 1 *" in0 $end -$var wire 1 0" in1 $end -$var wire 1 4" nS $end -$var wire 1 5" out0 $end -$var wire 1 6" out1 $end -$var wire 1 +" outfinal $end +$var wire 1 4" S $end +$var wire 1 +" in0 $end +$var wire 1 1" in1 $end +$var wire 1 5" nS $end +$var wire 1 6" out0 $end +$var wire 1 7" out1 $end +$var wire 1 ," outfinal $end $upscope $end $upscope $end $scope module setSLTres $end -$var wire 1 9 S $end -$var wire 1 7" in0 $end -$var wire 1 8" in1 $end -$var wire 1 9" nS $end -$var wire 1 :" out0 $end -$var wire 1 ;" out1 $end -$var wire 1 <" outfinal $end +$var wire 1 : S $end +$var wire 1 8" in0 $end +$var wire 1 9" in1 $end +$var wire 1 :" nS $end +$var wire 1 ;" out0 $end +$var wire 1 <" out1 $end +$var wire 1 =" outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope module test $end +$var wire 4 >" A [3:0] $end +$var wire 4 ?" AddSubSLTSum [3:0] $end +$var wire 4 @" B [3:0] $end +$var wire 4 A" CarryoutWire [3:0] $end +$var wire 3 B" Command [2:0] $end +$var wire 4 C" NewVal [3:0] $end +$var wire 1 D" Res0OF1 $end +$var wire 1 E" Res1OF0 $end +$var wire 4 F" SLTSum [3:0] $end +$var wire 1 ' SLTflag $end +$var wire 1 G" SLTflag0 $end +$var wire 1 H" SLTflag1 $end +$var wire 1 I" SLTon $end +$var wire 4 J" carryin [3:0] $end +$var wire 1 ) carryout $end +$var wire 1 K" nAddSubSLTSum $end +$var wire 1 L" nCmd2 $end +$var wire 1 M" nOF $end +$var wire 1 * overflow $end +$var wire 4 N" subtract [3:0] $end +$scope module attempt2 $end +$var wire 1 O" A $end +$var wire 1 P" AandB $end +$var wire 1 Q" AddSubSLTSum $end +$var wire 1 R" AxorB $end +$var wire 1 S" B $end +$var wire 1 T" BornB $end +$var wire 1 U" CINandAxorB $end +$var wire 3 V" Command [2:0] $end +$var wire 1 W" carryin $end +$var wire 1 X" carryout $end +$var wire 1 Y" nB $end +$var wire 1 Z" nCmd2 $end +$var wire 1 [" subtract $end +$scope module mux0 $end +$var wire 1 \" S $end +$var wire 1 S" in0 $end +$var wire 1 Y" in1 $end +$var wire 1 ]" nS $end +$var wire 1 ^" out0 $end +$var wire 1 _" out1 $end +$var wire 1 T" outfinal $end +$upscope $end +$upscope $end +$scope module setSLTres $end +$var wire 1 I" S $end +$var wire 1 `" in0 $end +$var wire 1 a" in1 $end +$var wire 1 b" nS $end +$var wire 1 c" out0 $end +$var wire 1 d" out1 $end +$var wire 1 e" outfinal $end +$upscope $end +$scope module FinalSLT $end +$var wire 1 ' S $end +$var wire 1 f" in0 $end +$var wire 1 ' in1 $end +$var wire 1 g" nS $end +$var wire 1 h" out0 $end +$var wire 1 i" out1 $end +$var wire 1 j" outfinal $end +$upscope $end +$scope begin addbits[1] $end +$scope module attempt $end +$var wire 1 k" A $end +$var wire 1 l" AandB $end +$var wire 1 m" AddSubSLTSum $end +$var wire 1 n" AxorB $end +$var wire 1 o" B $end +$var wire 1 p" BornB $end +$var wire 1 q" CINandAxorB $end +$var wire 3 r" Command [2:0] $end +$var wire 1 s" carryin $end +$var wire 1 t" carryout $end +$var wire 1 u" nB $end +$var wire 1 v" nCmd2 $end +$var wire 1 w" subtract $end +$scope module mux0 $end +$var wire 1 x" S $end +$var wire 1 o" in0 $end +$var wire 1 u" in1 $end +$var wire 1 y" nS $end +$var wire 1 z" out0 $end +$var wire 1 {" out1 $end +$var wire 1 p" outfinal $end +$upscope $end +$upscope $end +$scope module setSLTres2 $end +$var wire 1 I" S $end +$var wire 1 |" in0 $end +$var wire 1 }" in1 $end +$var wire 1 ~" nS $end +$var wire 1 !# out0 $end +$var wire 1 "# out1 $end +$var wire 1 ## outfinal $end +$upscope $end +$scope module setSLTres3 $end +$var wire 1 I" S $end +$var wire 1 $# in0 $end +$var wire 1 %# in1 $end +$var wire 1 &# nS $end +$var wire 1 '# out0 $end +$var wire 1 (# out1 $end +$var wire 1 )# outfinal $end +$upscope $end +$upscope $end +$scope begin addbits[2] $end +$scope module attempt $end +$var wire 1 *# A $end +$var wire 1 +# AandB $end +$var wire 1 ,# AddSubSLTSum $end +$var wire 1 -# AxorB $end +$var wire 1 .# B $end +$var wire 1 /# BornB $end +$var wire 1 0# CINandAxorB $end +$var wire 3 1# Command [2:0] $end +$var wire 1 2# carryin $end +$var wire 1 3# carryout $end +$var wire 1 4# nB $end +$var wire 1 5# nCmd2 $end +$var wire 1 6# subtract $end +$scope module mux0 $end +$var wire 1 7# S $end +$var wire 1 .# in0 $end +$var wire 1 4# in1 $end +$var wire 1 8# nS $end +$var wire 1 9# out0 $end +$var wire 1 :# out1 $end +$var wire 1 /# outfinal $end +$upscope $end +$upscope $end +$scope module setSLTres2 $end +$var wire 1 I" S $end +$var wire 1 ;# in0 $end +$var wire 1 <# in1 $end +$var wire 1 =# nS $end +$var wire 1 ># out0 $end +$var wire 1 ?# out1 $end +$var wire 1 @# outfinal $end +$upscope $end +$scope module setSLTres3 $end +$var wire 1 I" S $end +$var wire 1 A# in0 $end +$var wire 1 B# in1 $end +$var wire 1 C# nS $end +$var wire 1 D# out0 $end +$var wire 1 E# out1 $end +$var wire 1 F# outfinal $end +$upscope $end +$upscope $end +$scope begin addbits[3] $end +$scope module attempt $end +$var wire 1 G# A $end +$var wire 1 H# AandB $end +$var wire 1 I# AddSubSLTSum $end +$var wire 1 J# AxorB $end +$var wire 1 K# B $end +$var wire 1 L# BornB $end +$var wire 1 M# CINandAxorB $end +$var wire 3 N# Command [2:0] $end +$var wire 1 O# carryin $end +$var wire 1 P# carryout $end +$var wire 1 Q# nB $end +$var wire 1 R# nCmd2 $end +$var wire 1 S# subtract $end +$scope module mux0 $end +$var wire 1 T# S $end +$var wire 1 K# in0 $end +$var wire 1 Q# in1 $end +$var wire 1 U# nS $end +$var wire 1 V# out0 $end +$var wire 1 W# out1 $end +$var wire 1 L# outfinal $end +$upscope $end +$upscope $end +$scope module setSLTres2 $end +$var wire 1 I" S $end +$var wire 1 X# in0 $end +$var wire 1 Y# in1 $end +$var wire 1 Z# nS $end +$var wire 1 [# out0 $end +$var wire 1 \# out1 $end +$var wire 1 ]# outfinal $end +$upscope $end +$scope module setSLTres3 $end +$var wire 1 I" S $end +$var wire 1 ^# in0 $end +$var wire 1 _# in1 $end +$var wire 1 `# nS $end +$var wire 1 a# out0 $end +$var wire 1 b# out1 $end +$var wire 1 c# outfinal $end $upscope $end $upscope $end $upscope $end $scope module trial1 $end -$var wire 4 =" A [3:0] $end -$var wire 4 >" AndNandOut [3:0] $end -$var wire 4 ?" B [3:0] $end -$var wire 3 @" Command [2:0] $end +$var wire 4 d# A [3:0] $end +$var wire 4 e# AndNandOut [3:0] $end +$var wire 4 f# B [3:0] $end +$var wire 3 g# Command [2:0] $end $scope module attempt2 $end -$var wire 1 A" A $end -$var wire 1 B" AandB $end -$var wire 1 C" AnandB $end -$var wire 1 D" AndNandOut $end -$var wire 1 E" B $end -$var wire 3 F" Command [2:0] $end +$var wire 1 h# A $end +$var wire 1 i# AandB $end +$var wire 1 j# AnandB $end +$var wire 1 k# AndNandOut $end +$var wire 1 l# B $end +$var wire 3 m# Command [2:0] $end $scope module potato $end -$var wire 1 G" S $end -$var wire 1 B" in0 $end -$var wire 1 C" in1 $end -$var wire 1 H" nS $end -$var wire 1 I" out0 $end -$var wire 1 J" out1 $end -$var wire 1 D" outfinal $end +$var wire 1 n# S $end +$var wire 1 i# in0 $end +$var wire 1 j# in1 $end +$var wire 1 o# nS $end +$var wire 1 p# out0 $end +$var wire 1 q# out1 $end +$var wire 1 k# outfinal $end $upscope $end $upscope $end $scope begin andbits[1] $end $scope module attempt $end -$var wire 1 K" A $end -$var wire 1 L" AandB $end -$var wire 1 M" AnandB $end -$var wire 1 N" AndNandOut $end -$var wire 1 O" B $end -$var wire 3 P" Command [2:0] $end +$var wire 1 r# A $end +$var wire 1 s# AandB $end +$var wire 1 t# AnandB $end +$var wire 1 u# AndNandOut $end +$var wire 1 v# B $end +$var wire 3 w# Command [2:0] $end $scope module potato $end -$var wire 1 Q" S $end -$var wire 1 L" in0 $end -$var wire 1 M" in1 $end -$var wire 1 R" nS $end -$var wire 1 S" out0 $end -$var wire 1 T" out1 $end -$var wire 1 N" outfinal $end +$var wire 1 x# S $end +$var wire 1 s# in0 $end +$var wire 1 t# in1 $end +$var wire 1 y# nS $end +$var wire 1 z# out0 $end +$var wire 1 {# out1 $end +$var wire 1 u# outfinal $end $upscope $end $upscope $end $upscope $end $scope begin andbits[2] $end $scope module attempt $end -$var wire 1 U" A $end -$var wire 1 V" AandB $end -$var wire 1 W" AnandB $end -$var wire 1 X" AndNandOut $end -$var wire 1 Y" B $end -$var wire 3 Z" Command [2:0] $end +$var wire 1 |# A $end +$var wire 1 }# AandB $end +$var wire 1 ~# AnandB $end +$var wire 1 !$ AndNandOut $end +$var wire 1 "$ B $end +$var wire 3 #$ Command [2:0] $end $scope module potato $end -$var wire 1 [" S $end -$var wire 1 V" in0 $end -$var wire 1 W" in1 $end -$var wire 1 \" nS $end -$var wire 1 ]" out0 $end -$var wire 1 ^" out1 $end -$var wire 1 X" outfinal $end +$var wire 1 $$ S $end +$var wire 1 }# in0 $end +$var wire 1 ~# in1 $end +$var wire 1 %$ nS $end +$var wire 1 &$ out0 $end +$var wire 1 '$ out1 $end +$var wire 1 !$ outfinal $end $upscope $end $upscope $end $upscope $end $scope begin andbits[3] $end $scope module attempt $end -$var wire 1 _" A $end -$var wire 1 `" AandB $end -$var wire 1 a" AnandB $end -$var wire 1 b" AndNandOut $end -$var wire 1 c" B $end -$var wire 3 d" Command [2:0] $end +$var wire 1 ($ A $end +$var wire 1 )$ AandB $end +$var wire 1 *$ AnandB $end +$var wire 1 +$ AndNandOut $end +$var wire 1 ,$ B $end +$var wire 3 -$ Command [2:0] $end $scope module potato $end -$var wire 1 e" S $end -$var wire 1 `" in0 $end -$var wire 1 a" in1 $end -$var wire 1 f" nS $end -$var wire 1 g" out0 $end -$var wire 1 h" out1 $end -$var wire 1 b" outfinal $end +$var wire 1 .$ S $end +$var wire 1 )$ in0 $end +$var wire 1 *$ in1 $end +$var wire 1 /$ nS $end +$var wire 1 0$ out0 $end +$var wire 1 1$ out1 $end +$var wire 1 +$ outfinal $end $upscope $end $upscope $end $upscope $end $upscope $end $scope module trial2 $end -$var wire 4 i" A [3:0] $end -$var wire 4 j" B [3:0] $end -$var wire 3 k" Command [2:0] $end -$var wire 4 l" OrNorXorOut [3:0] $end +$var wire 4 2$ A [3:0] $end +$var wire 4 3$ B [3:0] $end +$var wire 3 4$ Command [2:0] $end +$var wire 4 5$ OrNorXorOut [3:0] $end $scope module attempt2 $end -$var wire 1 m" A $end -$var wire 1 n" AnandB $end -$var wire 1 o" AnorB $end -$var wire 1 p" AorB $end -$var wire 1 q" AxorB $end -$var wire 1 r" B $end -$var wire 3 s" Command [2:0] $end -$var wire 1 t" OrNorXorOut $end -$var wire 1 u" XorNor $end -$var wire 1 v" nXor $end +$var wire 1 6$ A $end +$var wire 1 7$ AnandB $end +$var wire 1 8$ AnorB $end +$var wire 1 9$ AorB $end +$var wire 1 :$ AxorB $end +$var wire 1 ;$ B $end +$var wire 3 <$ Command [2:0] $end +$var wire 1 =$ OrNorXorOut $end +$var wire 1 >$ XorNor $end +$var wire 1 ?$ nXor $end $scope module mux0 $end -$var wire 1 w" S $end -$var wire 1 q" in0 $end -$var wire 1 o" in1 $end -$var wire 1 x" nS $end -$var wire 1 y" out0 $end -$var wire 1 z" out1 $end -$var wire 1 u" outfinal $end +$var wire 1 @$ S $end +$var wire 1 :$ in0 $end +$var wire 1 8$ in1 $end +$var wire 1 A$ nS $end +$var wire 1 B$ out0 $end +$var wire 1 C$ out1 $end +$var wire 1 >$ outfinal $end $upscope $end $scope module mux1 $end -$var wire 1 {" S $end -$var wire 1 u" in0 $end -$var wire 1 p" in1 $end -$var wire 1 |" nS $end -$var wire 1 }" out0 $end -$var wire 1 ~" out1 $end -$var wire 1 t" outfinal $end +$var wire 1 D$ S $end +$var wire 1 >$ in0 $end +$var wire 1 9$ in1 $end +$var wire 1 E$ nS $end +$var wire 1 F$ out0 $end +$var wire 1 G$ out1 $end +$var wire 1 =$ outfinal $end $upscope $end $upscope $end $scope begin orbits[1] $end $scope module attempt $end -$var wire 1 !# A $end -$var wire 1 "# AnandB $end -$var wire 1 ## AnorB $end -$var wire 1 $# AorB $end -$var wire 1 %# AxorB $end -$var wire 1 &# B $end -$var wire 3 '# Command [2:0] $end -$var wire 1 (# OrNorXorOut $end -$var wire 1 )# XorNor $end -$var wire 1 *# nXor $end +$var wire 1 H$ A $end +$var wire 1 I$ AnandB $end +$var wire 1 J$ AnorB $end +$var wire 1 K$ AorB $end +$var wire 1 L$ AxorB $end +$var wire 1 M$ B $end +$var wire 3 N$ Command [2:0] $end +$var wire 1 O$ OrNorXorOut $end +$var wire 1 P$ XorNor $end +$var wire 1 Q$ nXor $end $scope module mux0 $end -$var wire 1 +# S $end -$var wire 1 %# in0 $end -$var wire 1 ## in1 $end -$var wire 1 ,# nS $end -$var wire 1 -# out0 $end -$var wire 1 .# out1 $end -$var wire 1 )# outfinal $end +$var wire 1 R$ S $end +$var wire 1 L$ in0 $end +$var wire 1 J$ in1 $end +$var wire 1 S$ nS $end +$var wire 1 T$ out0 $end +$var wire 1 U$ out1 $end +$var wire 1 P$ outfinal $end $upscope $end $scope module mux1 $end -$var wire 1 /# S $end -$var wire 1 )# in0 $end -$var wire 1 $# in1 $end -$var wire 1 0# nS $end -$var wire 1 1# out0 $end -$var wire 1 2# out1 $end -$var wire 1 (# outfinal $end +$var wire 1 V$ S $end +$var wire 1 P$ in0 $end +$var wire 1 K$ in1 $end +$var wire 1 W$ nS $end +$var wire 1 X$ out0 $end +$var wire 1 Y$ out1 $end +$var wire 1 O$ outfinal $end $upscope $end $upscope $end $upscope $end $scope begin orbits[2] $end $scope module attempt $end -$var wire 1 3# A $end -$var wire 1 4# AnandB $end -$var wire 1 5# AnorB $end -$var wire 1 6# AorB $end -$var wire 1 7# AxorB $end -$var wire 1 8# B $end -$var wire 3 9# Command [2:0] $end -$var wire 1 :# OrNorXorOut $end -$var wire 1 ;# XorNor $end -$var wire 1 <# nXor $end +$var wire 1 Z$ A $end +$var wire 1 [$ AnandB $end +$var wire 1 \$ AnorB $end +$var wire 1 ]$ AorB $end +$var wire 1 ^$ AxorB $end +$var wire 1 _$ B $end +$var wire 3 `$ Command [2:0] $end +$var wire 1 a$ OrNorXorOut $end +$var wire 1 b$ XorNor $end +$var wire 1 c$ nXor $end $scope module mux0 $end -$var wire 1 =# S $end -$var wire 1 7# in0 $end -$var wire 1 5# in1 $end -$var wire 1 ># nS $end -$var wire 1 ?# out0 $end -$var wire 1 @# out1 $end -$var wire 1 ;# outfinal $end +$var wire 1 d$ S $end +$var wire 1 ^$ in0 $end +$var wire 1 \$ in1 $end +$var wire 1 e$ nS $end +$var wire 1 f$ out0 $end +$var wire 1 g$ out1 $end +$var wire 1 b$ outfinal $end $upscope $end $scope module mux1 $end -$var wire 1 A# S $end -$var wire 1 ;# in0 $end -$var wire 1 6# in1 $end -$var wire 1 B# nS $end -$var wire 1 C# out0 $end -$var wire 1 D# out1 $end -$var wire 1 :# outfinal $end +$var wire 1 h$ S $end +$var wire 1 b$ in0 $end +$var wire 1 ]$ in1 $end +$var wire 1 i$ nS $end +$var wire 1 j$ out0 $end +$var wire 1 k$ out1 $end +$var wire 1 a$ outfinal $end $upscope $end $upscope $end $upscope $end $scope begin orbits[3] $end $scope module attempt $end -$var wire 1 E# A $end -$var wire 1 F# AnandB $end -$var wire 1 G# AnorB $end -$var wire 1 H# AorB $end -$var wire 1 I# AxorB $end -$var wire 1 J# B $end -$var wire 3 K# Command [2:0] $end -$var wire 1 L# OrNorXorOut $end -$var wire 1 M# XorNor $end -$var wire 1 N# nXor $end +$var wire 1 l$ A $end +$var wire 1 m$ AnandB $end +$var wire 1 n$ AnorB $end +$var wire 1 o$ AorB $end +$var wire 1 p$ AxorB $end +$var wire 1 q$ B $end +$var wire 3 r$ Command [2:0] $end +$var wire 1 s$ OrNorXorOut $end +$var wire 1 t$ XorNor $end +$var wire 1 u$ nXor $end $scope module mux0 $end -$var wire 1 O# S $end -$var wire 1 I# in0 $end -$var wire 1 G# in1 $end -$var wire 1 P# nS $end -$var wire 1 Q# out0 $end -$var wire 1 R# out1 $end -$var wire 1 M# outfinal $end +$var wire 1 v$ S $end +$var wire 1 p$ in0 $end +$var wire 1 n$ in1 $end +$var wire 1 w$ nS $end +$var wire 1 x$ out0 $end +$var wire 1 y$ out1 $end +$var wire 1 t$ outfinal $end $upscope $end $scope module mux1 $end -$var wire 1 S# S $end -$var wire 1 M# in0 $end -$var wire 1 H# in1 $end -$var wire 1 T# nS $end -$var wire 1 U# out0 $end -$var wire 1 V# out1 $end -$var wire 1 L# outfinal $end +$var wire 1 z$ S $end +$var wire 1 t$ in0 $end +$var wire 1 o$ in1 $end +$var wire 1 {$ nS $end +$var wire 1 |$ out0 $end +$var wire 1 }$ out1 $end +$var wire 1 s$ outfinal $end $upscope $end $upscope $end $upscope $end $upscope $end $scope module superalu $end -$var wire 4 W# A [3:0] $end -$var wire 4 X# AddSubSLTSum [3:0] $end +$var wire 4 ~$ A [3:0] $end +$var wire 4 !% AddSubSLTSum [3:0] $end $var wire 1 " AllZeros $end -$var wire 4 Y# AndNandOut [3:0] $end -$var wire 4 Z# B [3:0] $end -$var wire 4 [# Cmd0Start [3:0] $end -$var wire 4 \# Cmd1Start [3:0] $end -$var wire 3 ]# Command [2:0] $end -$var wire 4 ^# OneBitFinalOut [3:0] $end -$var wire 4 _# OrNorXorOut [3:0] $end -$var wire 1 & SLTflag $end -$var wire 4 `# ZeroFlag [3:0] $end -$var wire 4 a# carryin [3:0] $end -$var wire 1 ( carryout $end -$var wire 1 ) overflow $end -$var wire 4 b# subtract [3:0] $end -$var wire 1 c# yeszero $end +$var wire 4 "% AndNandOut [3:0] $end +$var wire 4 #% B [3:0] $end +$var wire 4 $% Cmd0Start [3:0] $end +$var wire 4 %% Cmd1Start [3:0] $end +$var wire 3 &% Command [2:0] $end +$var wire 4 '% OneBitFinalOut [3:0] $end +$var wire 4 (% OrNorXorOut [3:0] $end +$var wire 4 )% SLTSum [3:0] $end +$var wire 1 ' SLTflag $end +$var wire 4 *% ZeroFlag [3:0] $end +$var wire 4 +% carryin [3:0] $end +$var wire 1 ) carryout $end +$var wire 1 * overflow $end +$var wire 4 ,% subtract [3:0] $end +$var wire 1 -% yeszero $end +$scope module test $end +$var wire 4 .% A [3:0] $end +$var wire 4 /% AddSubSLTSum [3:0] $end +$var wire 4 0% B [3:0] $end +$var wire 4 1% CarryoutWire [3:0] $end +$var wire 3 2% Command [2:0] $end +$var wire 4 3% NewVal [3:0] $end +$var wire 1 4% Res0OF1 $end +$var wire 1 5% Res1OF0 $end +$var wire 4 6% SLTSum [3:0] $end +$var wire 1 ' SLTflag $end +$var wire 1 7% SLTflag0 $end +$var wire 1 8% SLTflag1 $end +$var wire 1 9% SLTon $end +$var wire 4 :% carryin [3:0] $end +$var wire 1 ) carryout $end +$var wire 1 ;% nAddSubSLTSum $end +$var wire 1 <% nCmd2 $end +$var wire 1 =% nOF $end +$var wire 1 * overflow $end +$var wire 4 >% subtract [3:0] $end +$scope module attempt2 $end +$var wire 1 ?% A $end +$var wire 1 @% AandB $end +$var wire 1 A% AddSubSLTSum $end +$var wire 1 B% AxorB $end +$var wire 1 C% B $end +$var wire 1 D% BornB $end +$var wire 1 E% CINandAxorB $end +$var wire 3 F% Command [2:0] $end +$var wire 1 G% carryin $end +$var wire 1 H% carryout $end +$var wire 1 I% nB $end +$var wire 1 J% nCmd2 $end +$var wire 1 K% subtract $end +$scope module mux0 $end +$var wire 1 L% S $end +$var wire 1 C% in0 $end +$var wire 1 I% in1 $end +$var wire 1 M% nS $end +$var wire 1 N% out0 $end +$var wire 1 O% out1 $end +$var wire 1 D% outfinal $end +$upscope $end +$upscope $end +$scope module setSLTres $end +$var wire 1 9% S $end +$var wire 1 P% in0 $end +$var wire 1 Q% in1 $end +$var wire 1 R% nS $end +$var wire 1 S% out0 $end +$var wire 1 T% out1 $end +$var wire 1 U% outfinal $end +$upscope $end +$scope module FinalSLT $end +$var wire 1 ' S $end +$var wire 1 V% in0 $end +$var wire 1 ' in1 $end +$var wire 1 W% nS $end +$var wire 1 X% out0 $end +$var wire 1 Y% out1 $end +$var wire 1 Z% outfinal $end +$upscope $end +$scope begin addbits[1] $end +$scope module attempt $end +$var wire 1 [% A $end +$var wire 1 \% AandB $end +$var wire 1 ]% AddSubSLTSum $end +$var wire 1 ^% AxorB $end +$var wire 1 _% B $end +$var wire 1 `% BornB $end +$var wire 1 a% CINandAxorB $end +$var wire 3 b% Command [2:0] $end +$var wire 1 c% carryin $end +$var wire 1 d% carryout $end +$var wire 1 e% nB $end +$var wire 1 f% nCmd2 $end +$var wire 1 g% subtract $end +$scope module mux0 $end +$var wire 1 h% S $end +$var wire 1 _% in0 $end +$var wire 1 e% in1 $end +$var wire 1 i% nS $end +$var wire 1 j% out0 $end +$var wire 1 k% out1 $end +$var wire 1 `% outfinal $end +$upscope $end +$upscope $end +$scope module setSLTres2 $end +$var wire 1 9% S $end +$var wire 1 l% in0 $end +$var wire 1 m% in1 $end +$var wire 1 n% nS $end +$var wire 1 o% out0 $end +$var wire 1 p% out1 $end +$var wire 1 q% outfinal $end +$upscope $end +$scope module setSLTres3 $end +$var wire 1 9% S $end +$var wire 1 r% in0 $end +$var wire 1 s% in1 $end +$var wire 1 t% nS $end +$var wire 1 u% out0 $end +$var wire 1 v% out1 $end +$var wire 1 w% outfinal $end +$upscope $end +$upscope $end +$scope begin addbits[2] $end +$scope module attempt $end +$var wire 1 x% A $end +$var wire 1 y% AandB $end +$var wire 1 z% AddSubSLTSum $end +$var wire 1 {% AxorB $end +$var wire 1 |% B $end +$var wire 1 }% BornB $end +$var wire 1 ~% CINandAxorB $end +$var wire 3 !& Command [2:0] $end +$var wire 1 "& carryin $end +$var wire 1 #& carryout $end +$var wire 1 $& nB $end +$var wire 1 %& nCmd2 $end +$var wire 1 && subtract $end +$scope module mux0 $end +$var wire 1 '& S $end +$var wire 1 |% in0 $end +$var wire 1 $& in1 $end +$var wire 1 (& nS $end +$var wire 1 )& out0 $end +$var wire 1 *& out1 $end +$var wire 1 }% outfinal $end +$upscope $end +$upscope $end +$scope module setSLTres2 $end +$var wire 1 9% S $end +$var wire 1 +& in0 $end +$var wire 1 ,& in1 $end +$var wire 1 -& nS $end +$var wire 1 .& out0 $end +$var wire 1 /& out1 $end +$var wire 1 0& outfinal $end +$upscope $end +$scope module setSLTres3 $end +$var wire 1 9% S $end +$var wire 1 1& in0 $end +$var wire 1 2& in1 $end +$var wire 1 3& nS $end +$var wire 1 4& out0 $end +$var wire 1 5& out1 $end +$var wire 1 6& outfinal $end +$upscope $end +$upscope $end +$scope begin addbits[3] $end +$scope module attempt $end +$var wire 1 7& A $end +$var wire 1 8& AandB $end +$var wire 1 9& AddSubSLTSum $end +$var wire 1 :& AxorB $end +$var wire 1 ;& B $end +$var wire 1 <& BornB $end +$var wire 1 =& CINandAxorB $end +$var wire 3 >& Command [2:0] $end +$var wire 1 ?& carryin $end +$var wire 1 @& carryout $end +$var wire 1 A& nB $end +$var wire 1 B& nCmd2 $end +$var wire 1 C& subtract $end +$scope module mux0 $end +$var wire 1 D& S $end +$var wire 1 ;& in0 $end +$var wire 1 A& in1 $end +$var wire 1 E& nS $end +$var wire 1 F& out0 $end +$var wire 1 G& out1 $end +$var wire 1 <& outfinal $end +$upscope $end +$upscope $end +$scope module setSLTres2 $end +$var wire 1 9% S $end +$var wire 1 H& in0 $end +$var wire 1 I& in1 $end +$var wire 1 J& nS $end +$var wire 1 K& out0 $end +$var wire 1 L& out1 $end +$var wire 1 M& outfinal $end +$upscope $end +$scope module setSLTres3 $end +$var wire 1 9% S $end +$var wire 1 N& in0 $end +$var wire 1 O& in1 $end +$var wire 1 P& nS $end +$var wire 1 Q& out0 $end +$var wire 1 R& out1 $end +$var wire 1 S& outfinal $end +$upscope $end +$upscope $end +$upscope $end $scope module trial $end -$var wire 4 d# A [3:0] $end -$var wire 4 e# AddSubSLTSum [3:0] $end -$var wire 4 f# B [3:0] $end -$var wire 4 g# CarryoutWire [3:0] $end -$var wire 3 h# Command [2:0] $end -$var wire 4 i# NewVal [3:0] $end -$var wire 1 j# Res0OF1 $end -$var wire 1 k# Res1OF0 $end -$var wire 1 & SLTflag $end -$var wire 1 l# SLTflag0 $end -$var wire 1 m# SLTflag1 $end -$var wire 1 n# SLTon $end -$var wire 4 o# carryin [3:0] $end -$var wire 1 ( carryout $end -$var wire 1 p# nAddSubSLTSum $end -$var wire 1 q# nCmd2 $end -$var wire 1 r# nOF $end -$var wire 1 ) overflow $end -$var wire 4 s# subtract [3:0] $end +$var wire 4 T& A [3:0] $end +$var wire 4 U& AddSubSLTSum [3:0] $end +$var wire 4 V& B [3:0] $end +$var wire 4 W& CarryoutWire [3:0] $end +$var wire 3 X& Command [2:0] $end +$var wire 4 Y& NewVal [3:0] $end +$var wire 1 Z& Res0OF1 $end +$var wire 1 [& Res1OF0 $end +$var wire 1 ' SLTflag $end +$var wire 1 \& SLTflag0 $end +$var wire 1 ]& SLTflag1 $end +$var wire 1 ^& SLTon $end +$var wire 4 _& carryin [3:0] $end +$var wire 1 ) carryout $end +$var wire 1 `& nAddSubSLTSum $end +$var wire 1 a& nCmd2 $end +$var wire 1 b& nOF $end +$var wire 1 * overflow $end +$var wire 4 c& subtract [3:0] $end $scope module attempt2 $end -$var wire 1 t# A $end -$var wire 1 u# AandB $end -$var wire 1 v# AddSubSLTSum $end -$var wire 1 w# AxorB $end -$var wire 1 x# B $end -$var wire 1 y# BornB $end -$var wire 1 z# CINandAxorB $end -$var wire 3 {# Command [2:0] $end -$var wire 1 |# carryin $end -$var wire 1 }# carryout $end -$var wire 1 ~# nB $end -$var wire 1 !$ nCmd2 $end -$var wire 1 "$ subtract $end +$var wire 1 d& A $end +$var wire 1 e& AandB $end +$var wire 1 f& AddSubSLTSum $end +$var wire 1 g& AxorB $end +$var wire 1 h& B $end +$var wire 1 i& BornB $end +$var wire 1 j& CINandAxorB $end +$var wire 3 k& Command [2:0] $end +$var wire 1 l& carryin $end +$var wire 1 m& carryout $end +$var wire 1 n& nB $end +$var wire 1 o& nCmd2 $end +$var wire 1 p& subtract $end $scope module mux0 $end -$var wire 1 #$ S $end -$var wire 1 x# in0 $end -$var wire 1 ~# in1 $end -$var wire 1 $$ nS $end -$var wire 1 %$ out0 $end -$var wire 1 &$ out1 $end -$var wire 1 y# outfinal $end +$var wire 1 q& S $end +$var wire 1 h& in0 $end +$var wire 1 n& in1 $end +$var wire 1 r& nS $end +$var wire 1 s& out0 $end +$var wire 1 t& out1 $end +$var wire 1 i& outfinal $end $upscope $end $upscope $end $scope module setSLTres $end -$var wire 1 n# S $end -$var wire 1 '$ in0 $end -$var wire 1 ($ in1 $end -$var wire 1 )$ nS $end -$var wire 1 *$ out0 $end -$var wire 1 +$ out1 $end -$var wire 1 ,$ outfinal $end +$var wire 1 ^& S $end +$var wire 1 u& in0 $end +$var wire 1 v& in1 $end +$var wire 1 w& nS $end +$var wire 1 x& out0 $end +$var wire 1 y& out1 $end +$var wire 1 z& outfinal $end $upscope $end $scope begin addbits[1] $end $scope module attempt $end -$var wire 1 -$ A $end -$var wire 1 .$ AandB $end -$var wire 1 /$ AddSubSLTSum $end -$var wire 1 0$ AxorB $end -$var wire 1 1$ B $end -$var wire 1 2$ BornB $end -$var wire 1 3$ CINandAxorB $end -$var wire 3 4$ Command [2:0] $end -$var wire 1 5$ carryin $end -$var wire 1 6$ carryout $end -$var wire 1 7$ nB $end -$var wire 1 8$ nCmd2 $end -$var wire 1 9$ subtract $end +$var wire 1 {& A $end +$var wire 1 |& AandB $end +$var wire 1 }& AddSubSLTSum $end +$var wire 1 ~& AxorB $end +$var wire 1 !' B $end +$var wire 1 "' BornB $end +$var wire 1 #' CINandAxorB $end +$var wire 3 $' Command [2:0] $end +$var wire 1 %' carryin $end +$var wire 1 &' carryout $end +$var wire 1 '' nB $end +$var wire 1 (' nCmd2 $end +$var wire 1 )' subtract $end $scope module mux0 $end -$var wire 1 :$ S $end -$var wire 1 1$ in0 $end -$var wire 1 7$ in1 $end -$var wire 1 ;$ nS $end -$var wire 1 <$ out0 $end -$var wire 1 =$ out1 $end -$var wire 1 2$ outfinal $end +$var wire 1 *' S $end +$var wire 1 !' in0 $end +$var wire 1 '' in1 $end +$var wire 1 +' nS $end +$var wire 1 ,' out0 $end +$var wire 1 -' out1 $end +$var wire 1 "' outfinal $end $upscope $end $upscope $end $scope module setSLTres $end -$var wire 1 n# S $end -$var wire 1 >$ in0 $end -$var wire 1 ?$ in1 $end -$var wire 1 @$ nS $end -$var wire 1 A$ out0 $end -$var wire 1 B$ out1 $end -$var wire 1 C$ outfinal $end +$var wire 1 ^& S $end +$var wire 1 .' in0 $end +$var wire 1 /' in1 $end +$var wire 1 0' nS $end +$var wire 1 1' out0 $end +$var wire 1 2' out1 $end +$var wire 1 3' outfinal $end $upscope $end $upscope $end $scope begin addbits[2] $end $scope module attempt $end -$var wire 1 D$ A $end -$var wire 1 E$ AandB $end -$var wire 1 F$ AddSubSLTSum $end -$var wire 1 G$ AxorB $end -$var wire 1 H$ B $end -$var wire 1 I$ BornB $end -$var wire 1 J$ CINandAxorB $end -$var wire 3 K$ Command [2:0] $end -$var wire 1 L$ carryin $end -$var wire 1 M$ carryout $end -$var wire 1 N$ nB $end -$var wire 1 O$ nCmd2 $end -$var wire 1 P$ subtract $end +$var wire 1 4' A $end +$var wire 1 5' AandB $end +$var wire 1 6' AddSubSLTSum $end +$var wire 1 7' AxorB $end +$var wire 1 8' B $end +$var wire 1 9' BornB $end +$var wire 1 :' CINandAxorB $end +$var wire 3 ;' Command [2:0] $end +$var wire 1 <' carryin $end +$var wire 1 =' carryout $end +$var wire 1 >' nB $end +$var wire 1 ?' nCmd2 $end +$var wire 1 @' subtract $end $scope module mux0 $end -$var wire 1 Q$ S $end -$var wire 1 H$ in0 $end -$var wire 1 N$ in1 $end -$var wire 1 R$ nS $end -$var wire 1 S$ out0 $end -$var wire 1 T$ out1 $end -$var wire 1 I$ outfinal $end +$var wire 1 A' S $end +$var wire 1 8' in0 $end +$var wire 1 >' in1 $end +$var wire 1 B' nS $end +$var wire 1 C' out0 $end +$var wire 1 D' out1 $end +$var wire 1 9' outfinal $end $upscope $end $upscope $end $scope module setSLTres $end -$var wire 1 n# S $end -$var wire 1 U$ in0 $end -$var wire 1 V$ in1 $end -$var wire 1 W$ nS $end -$var wire 1 X$ out0 $end -$var wire 1 Y$ out1 $end -$var wire 1 Z$ outfinal $end +$var wire 1 ^& S $end +$var wire 1 E' in0 $end +$var wire 1 F' in1 $end +$var wire 1 G' nS $end +$var wire 1 H' out0 $end +$var wire 1 I' out1 $end +$var wire 1 J' outfinal $end $upscope $end $upscope $end $scope begin addbits[3] $end $scope module attempt $end -$var wire 1 [$ A $end -$var wire 1 \$ AandB $end -$var wire 1 ]$ AddSubSLTSum $end -$var wire 1 ^$ AxorB $end -$var wire 1 _$ B $end -$var wire 1 `$ BornB $end -$var wire 1 a$ CINandAxorB $end -$var wire 3 b$ Command [2:0] $end -$var wire 1 c$ carryin $end -$var wire 1 d$ carryout $end -$var wire 1 e$ nB $end -$var wire 1 f$ nCmd2 $end -$var wire 1 g$ subtract $end +$var wire 1 K' A $end +$var wire 1 L' AandB $end +$var wire 1 M' AddSubSLTSum $end +$var wire 1 N' AxorB $end +$var wire 1 O' B $end +$var wire 1 P' BornB $end +$var wire 1 Q' CINandAxorB $end +$var wire 3 R' Command [2:0] $end +$var wire 1 S' carryin $end +$var wire 1 T' carryout $end +$var wire 1 U' nB $end +$var wire 1 V' nCmd2 $end +$var wire 1 W' subtract $end $scope module mux0 $end -$var wire 1 h$ S $end -$var wire 1 _$ in0 $end -$var wire 1 e$ in1 $end -$var wire 1 i$ nS $end -$var wire 1 j$ out0 $end -$var wire 1 k$ out1 $end -$var wire 1 `$ outfinal $end +$var wire 1 X' S $end +$var wire 1 O' in0 $end +$var wire 1 U' in1 $end +$var wire 1 Y' nS $end +$var wire 1 Z' out0 $end +$var wire 1 [' out1 $end +$var wire 1 P' outfinal $end $upscope $end $upscope $end $scope module setSLTres $end -$var wire 1 n# S $end -$var wire 1 l$ in0 $end -$var wire 1 m$ in1 $end -$var wire 1 n$ nS $end -$var wire 1 o$ out0 $end -$var wire 1 p$ out1 $end -$var wire 1 q$ outfinal $end +$var wire 1 ^& S $end +$var wire 1 \' in0 $end +$var wire 1 ]' in1 $end +$var wire 1 ^' nS $end +$var wire 1 _' out0 $end +$var wire 1 `' out1 $end +$var wire 1 a' outfinal $end $upscope $end $upscope $end $upscope $end $scope module trial1 $end -$var wire 4 r$ A [3:0] $end -$var wire 4 s$ AndNandOut [3:0] $end -$var wire 4 t$ B [3:0] $end -$var wire 3 u$ Command [2:0] $end +$var wire 4 b' A [3:0] $end +$var wire 4 c' AndNandOut [3:0] $end +$var wire 4 d' B [3:0] $end +$var wire 3 e' Command [2:0] $end $scope module attempt2 $end -$var wire 1 v$ A $end -$var wire 1 w$ AandB $end -$var wire 1 x$ AnandB $end -$var wire 1 y$ AndNandOut $end -$var wire 1 z$ B $end -$var wire 3 {$ Command [2:0] $end +$var wire 1 f' A $end +$var wire 1 g' AandB $end +$var wire 1 h' AnandB $end +$var wire 1 i' AndNandOut $end +$var wire 1 j' B $end +$var wire 3 k' Command [2:0] $end $scope module potato $end -$var wire 1 |$ S $end -$var wire 1 w$ in0 $end -$var wire 1 x$ in1 $end -$var wire 1 }$ nS $end -$var wire 1 ~$ out0 $end -$var wire 1 !% out1 $end -$var wire 1 y$ outfinal $end +$var wire 1 l' S $end +$var wire 1 g' in0 $end +$var wire 1 h' in1 $end +$var wire 1 m' nS $end +$var wire 1 n' out0 $end +$var wire 1 o' out1 $end +$var wire 1 i' outfinal $end $upscope $end $upscope $end $scope begin andbits[1] $end $scope module attempt $end -$var wire 1 "% A $end -$var wire 1 #% AandB $end -$var wire 1 $% AnandB $end -$var wire 1 %% AndNandOut $end -$var wire 1 &% B $end -$var wire 3 '% Command [2:0] $end +$var wire 1 p' A $end +$var wire 1 q' AandB $end +$var wire 1 r' AnandB $end +$var wire 1 s' AndNandOut $end +$var wire 1 t' B $end +$var wire 3 u' Command [2:0] $end $scope module potato $end -$var wire 1 (% S $end -$var wire 1 #% in0 $end -$var wire 1 $% in1 $end -$var wire 1 )% nS $end -$var wire 1 *% out0 $end -$var wire 1 +% out1 $end -$var wire 1 %% outfinal $end +$var wire 1 v' S $end +$var wire 1 q' in0 $end +$var wire 1 r' in1 $end +$var wire 1 w' nS $end +$var wire 1 x' out0 $end +$var wire 1 y' out1 $end +$var wire 1 s' outfinal $end $upscope $end $upscope $end $upscope $end $scope begin andbits[2] $end $scope module attempt $end -$var wire 1 ,% A $end -$var wire 1 -% AandB $end -$var wire 1 .% AnandB $end -$var wire 1 /% AndNandOut $end -$var wire 1 0% B $end -$var wire 3 1% Command [2:0] $end +$var wire 1 z' A $end +$var wire 1 {' AandB $end +$var wire 1 |' AnandB $end +$var wire 1 }' AndNandOut $end +$var wire 1 ~' B $end +$var wire 3 !( Command [2:0] $end $scope module potato $end -$var wire 1 2% S $end -$var wire 1 -% in0 $end -$var wire 1 .% in1 $end -$var wire 1 3% nS $end -$var wire 1 4% out0 $end -$var wire 1 5% out1 $end -$var wire 1 /% outfinal $end +$var wire 1 "( S $end +$var wire 1 {' in0 $end +$var wire 1 |' in1 $end +$var wire 1 #( nS $end +$var wire 1 $( out0 $end +$var wire 1 %( out1 $end +$var wire 1 }' outfinal $end $upscope $end $upscope $end $upscope $end $scope begin andbits[3] $end $scope module attempt $end -$var wire 1 6% A $end -$var wire 1 7% AandB $end -$var wire 1 8% AnandB $end -$var wire 1 9% AndNandOut $end -$var wire 1 :% B $end -$var wire 3 ;% Command [2:0] $end +$var wire 1 &( A $end +$var wire 1 '( AandB $end +$var wire 1 (( AnandB $end +$var wire 1 )( AndNandOut $end +$var wire 1 *( B $end +$var wire 3 +( Command [2:0] $end $scope module potato $end -$var wire 1 <% S $end -$var wire 1 7% in0 $end -$var wire 1 8% in1 $end -$var wire 1 =% nS $end -$var wire 1 >% out0 $end -$var wire 1 ?% out1 $end -$var wire 1 9% outfinal $end +$var wire 1 ,( S $end +$var wire 1 '( in0 $end +$var wire 1 (( in1 $end +$var wire 1 -( nS $end +$var wire 1 .( out0 $end +$var wire 1 /( out1 $end +$var wire 1 )( outfinal $end $upscope $end $upscope $end $upscope $end $upscope $end $scope module trial2 $end -$var wire 4 @% A [3:0] $end -$var wire 4 A% B [3:0] $end -$var wire 3 B% Command [2:0] $end -$var wire 4 C% OrNorXorOut [3:0] $end +$var wire 4 0( A [3:0] $end +$var wire 4 1( B [3:0] $end +$var wire 3 2( Command [2:0] $end +$var wire 4 3( OrNorXorOut [3:0] $end $scope module attempt2 $end -$var wire 1 D% A $end -$var wire 1 E% AnandB $end -$var wire 1 F% AnorB $end -$var wire 1 G% AorB $end -$var wire 1 H% AxorB $end -$var wire 1 I% B $end -$var wire 3 J% Command [2:0] $end -$var wire 1 K% OrNorXorOut $end -$var wire 1 L% XorNor $end -$var wire 1 M% nXor $end +$var wire 1 4( A $end +$var wire 1 5( AnandB $end +$var wire 1 6( AnorB $end +$var wire 1 7( AorB $end +$var wire 1 8( AxorB $end +$var wire 1 9( B $end +$var wire 3 :( Command [2:0] $end +$var wire 1 ;( OrNorXorOut $end +$var wire 1 <( XorNor $end +$var wire 1 =( nXor $end $scope module mux0 $end -$var wire 1 N% S $end -$var wire 1 H% in0 $end -$var wire 1 F% in1 $end -$var wire 1 O% nS $end -$var wire 1 P% out0 $end -$var wire 1 Q% out1 $end -$var wire 1 L% outfinal $end +$var wire 1 >( S $end +$var wire 1 8( in0 $end +$var wire 1 6( in1 $end +$var wire 1 ?( nS $end +$var wire 1 @( out0 $end +$var wire 1 A( out1 $end +$var wire 1 <( outfinal $end $upscope $end $scope module mux1 $end -$var wire 1 R% S $end -$var wire 1 L% in0 $end -$var wire 1 G% in1 $end -$var wire 1 S% nS $end -$var wire 1 T% out0 $end -$var wire 1 U% out1 $end -$var wire 1 K% outfinal $end +$var wire 1 B( S $end +$var wire 1 <( in0 $end +$var wire 1 7( in1 $end +$var wire 1 C( nS $end +$var wire 1 D( out0 $end +$var wire 1 E( out1 $end +$var wire 1 ;( outfinal $end $upscope $end $upscope $end $scope begin orbits[1] $end $scope module attempt $end -$var wire 1 V% A $end -$var wire 1 W% AnandB $end -$var wire 1 X% AnorB $end -$var wire 1 Y% AorB $end -$var wire 1 Z% AxorB $end -$var wire 1 [% B $end -$var wire 3 \% Command [2:0] $end -$var wire 1 ]% OrNorXorOut $end -$var wire 1 ^% XorNor $end -$var wire 1 _% nXor $end +$var wire 1 F( A $end +$var wire 1 G( AnandB $end +$var wire 1 H( AnorB $end +$var wire 1 I( AorB $end +$var wire 1 J( AxorB $end +$var wire 1 K( B $end +$var wire 3 L( Command [2:0] $end +$var wire 1 M( OrNorXorOut $end +$var wire 1 N( XorNor $end +$var wire 1 O( nXor $end $scope module mux0 $end -$var wire 1 `% S $end -$var wire 1 Z% in0 $end -$var wire 1 X% in1 $end -$var wire 1 a% nS $end -$var wire 1 b% out0 $end -$var wire 1 c% out1 $end -$var wire 1 ^% outfinal $end +$var wire 1 P( S $end +$var wire 1 J( in0 $end +$var wire 1 H( in1 $end +$var wire 1 Q( nS $end +$var wire 1 R( out0 $end +$var wire 1 S( out1 $end +$var wire 1 N( outfinal $end $upscope $end $scope module mux1 $end -$var wire 1 d% S $end -$var wire 1 ^% in0 $end -$var wire 1 Y% in1 $end -$var wire 1 e% nS $end -$var wire 1 f% out0 $end -$var wire 1 g% out1 $end -$var wire 1 ]% outfinal $end +$var wire 1 T( S $end +$var wire 1 N( in0 $end +$var wire 1 I( in1 $end +$var wire 1 U( nS $end +$var wire 1 V( out0 $end +$var wire 1 W( out1 $end +$var wire 1 M( outfinal $end $upscope $end $upscope $end $upscope $end $scope begin orbits[2] $end $scope module attempt $end -$var wire 1 h% A $end -$var wire 1 i% AnandB $end -$var wire 1 j% AnorB $end -$var wire 1 k% AorB $end -$var wire 1 l% AxorB $end -$var wire 1 m% B $end -$var wire 3 n% Command [2:0] $end -$var wire 1 o% OrNorXorOut $end -$var wire 1 p% XorNor $end -$var wire 1 q% nXor $end +$var wire 1 X( A $end +$var wire 1 Y( AnandB $end +$var wire 1 Z( AnorB $end +$var wire 1 [( AorB $end +$var wire 1 \( AxorB $end +$var wire 1 ]( B $end +$var wire 3 ^( Command [2:0] $end +$var wire 1 _( OrNorXorOut $end +$var wire 1 `( XorNor $end +$var wire 1 a( nXor $end $scope module mux0 $end -$var wire 1 r% S $end -$var wire 1 l% in0 $end -$var wire 1 j% in1 $end -$var wire 1 s% nS $end -$var wire 1 t% out0 $end -$var wire 1 u% out1 $end -$var wire 1 p% outfinal $end +$var wire 1 b( S $end +$var wire 1 \( in0 $end +$var wire 1 Z( in1 $end +$var wire 1 c( nS $end +$var wire 1 d( out0 $end +$var wire 1 e( out1 $end +$var wire 1 `( outfinal $end $upscope $end $scope module mux1 $end -$var wire 1 v% S $end -$var wire 1 p% in0 $end -$var wire 1 k% in1 $end -$var wire 1 w% nS $end -$var wire 1 x% out0 $end -$var wire 1 y% out1 $end -$var wire 1 o% outfinal $end +$var wire 1 f( S $end +$var wire 1 `( in0 $end +$var wire 1 [( in1 $end +$var wire 1 g( nS $end +$var wire 1 h( out0 $end +$var wire 1 i( out1 $end +$var wire 1 _( outfinal $end $upscope $end $upscope $end $upscope $end $scope begin orbits[3] $end $scope module attempt $end -$var wire 1 z% A $end -$var wire 1 {% AnandB $end -$var wire 1 |% AnorB $end -$var wire 1 }% AorB $end -$var wire 1 ~% AxorB $end -$var wire 1 !& B $end -$var wire 3 "& Command [2:0] $end -$var wire 1 #& OrNorXorOut $end -$var wire 1 $& XorNor $end -$var wire 1 %& nXor $end +$var wire 1 j( A $end +$var wire 1 k( AnandB $end +$var wire 1 l( AnorB $end +$var wire 1 m( AorB $end +$var wire 1 n( AxorB $end +$var wire 1 o( B $end +$var wire 3 p( Command [2:0] $end +$var wire 1 q( OrNorXorOut $end +$var wire 1 r( XorNor $end +$var wire 1 s( nXor $end $scope module mux0 $end -$var wire 1 && S $end -$var wire 1 ~% in0 $end -$var wire 1 |% in1 $end -$var wire 1 '& nS $end -$var wire 1 (& out0 $end -$var wire 1 )& out1 $end -$var wire 1 $& outfinal $end +$var wire 1 t( S $end +$var wire 1 n( in0 $end +$var wire 1 l( in1 $end +$var wire 1 u( nS $end +$var wire 1 v( out0 $end +$var wire 1 w( out1 $end +$var wire 1 r( outfinal $end $upscope $end $scope module mux1 $end -$var wire 1 *& S $end -$var wire 1 $& in0 $end -$var wire 1 }% in1 $end -$var wire 1 +& nS $end -$var wire 1 ,& out0 $end -$var wire 1 -& out1 $end -$var wire 1 #& outfinal $end +$var wire 1 x( S $end +$var wire 1 r( in0 $end +$var wire 1 m( in1 $end +$var wire 1 y( nS $end +$var wire 1 z( out0 $end +$var wire 1 {( out1 $end +$var wire 1 q( outfinal $end $upscope $end $upscope $end $upscope $end $upscope $end $scope module ZeroMux0case $end -$var wire 1 .& S0 $end -$var wire 1 /& S1 $end -$var wire 1 0& in0 $end -$var wire 1 1& in1 $end -$var wire 1 2& in2 $end -$var wire 1 3& in3 $end -$var wire 1 4& nS0 $end -$var wire 1 5& nS1 $end -$var wire 1 6& out $end -$var wire 1 7& out0 $end -$var wire 1 8& out1 $end -$var wire 1 9& out2 $end -$var wire 1 :& out3 $end +$var wire 1 |( S0 $end +$var wire 1 }( S1 $end +$var wire 1 ~( in0 $end +$var wire 1 !) in1 $end +$var wire 1 ") in2 $end +$var wire 1 #) in3 $end +$var wire 1 $) nS0 $end +$var wire 1 %) nS1 $end +$var wire 1 &) out $end +$var wire 1 ') out0 $end +$var wire 1 () out1 $end +$var wire 1 )) out2 $end +$var wire 1 *) out3 $end $upscope $end $scope module OneMux0case $end -$var wire 1 ;& S0 $end -$var wire 1 <& S1 $end -$var wire 1 =& in0 $end -$var wire 1 >& in1 $end -$var wire 1 ?& in2 $end -$var wire 1 @& in3 $end -$var wire 1 A& nS0 $end -$var wire 1 B& nS1 $end -$var wire 1 C& out $end -$var wire 1 D& out0 $end -$var wire 1 E& out1 $end -$var wire 1 F& out2 $end -$var wire 1 G& out3 $end +$var wire 1 +) S0 $end +$var wire 1 ,) S1 $end +$var wire 1 -) in0 $end +$var wire 1 .) in1 $end +$var wire 1 /) in2 $end +$var wire 1 0) in3 $end +$var wire 1 1) nS0 $end +$var wire 1 2) nS1 $end +$var wire 1 3) out $end +$var wire 1 4) out0 $end +$var wire 1 5) out1 $end +$var wire 1 6) out2 $end +$var wire 1 7) out3 $end $upscope $end $scope module TwoMux0case $end -$var wire 1 H& S $end -$var wire 1 I& in0 $end -$var wire 1 J& in1 $end -$var wire 1 K& nS $end -$var wire 1 L& out0 $end -$var wire 1 M& out1 $end -$var wire 1 N& outfinal $end +$var wire 1 8) S $end +$var wire 1 9) in0 $end +$var wire 1 :) in1 $end +$var wire 1 ;) nS $end +$var wire 1 <) out0 $end +$var wire 1 =) out1 $end +$var wire 1 >) outfinal $end $upscope $end $scope begin muxbits[1] $end $scope module ZeroMux $end -$var wire 1 O& S0 $end -$var wire 1 P& S1 $end -$var wire 1 Q& in0 $end -$var wire 1 R& in1 $end -$var wire 1 S& in2 $end -$var wire 1 T& in3 $end -$var wire 1 U& nS0 $end -$var wire 1 V& nS1 $end -$var wire 1 W& out $end -$var wire 1 X& out0 $end -$var wire 1 Y& out1 $end -$var wire 1 Z& out2 $end -$var wire 1 [& out3 $end +$var wire 1 ?) S0 $end +$var wire 1 @) S1 $end +$var wire 1 A) in0 $end +$var wire 1 B) in1 $end +$var wire 1 C) in2 $end +$var wire 1 D) in3 $end +$var wire 1 E) nS0 $end +$var wire 1 F) nS1 $end +$var wire 1 G) out $end +$var wire 1 H) out0 $end +$var wire 1 I) out1 $end +$var wire 1 J) out2 $end +$var wire 1 K) out3 $end $upscope $end $scope module OneMux $end -$var wire 1 \& S0 $end -$var wire 1 ]& S1 $end -$var wire 1 ^& in0 $end -$var wire 1 _& in1 $end -$var wire 1 `& in2 $end -$var wire 1 a& in3 $end -$var wire 1 b& nS0 $end -$var wire 1 c& nS1 $end -$var wire 1 d& out $end -$var wire 1 e& out0 $end -$var wire 1 f& out1 $end -$var wire 1 g& out2 $end -$var wire 1 h& out3 $end +$var wire 1 L) S0 $end +$var wire 1 M) S1 $end +$var wire 1 N) in0 $end +$var wire 1 O) in1 $end +$var wire 1 P) in2 $end +$var wire 1 Q) in3 $end +$var wire 1 R) nS0 $end +$var wire 1 S) nS1 $end +$var wire 1 T) out $end +$var wire 1 U) out0 $end +$var wire 1 V) out1 $end +$var wire 1 W) out2 $end +$var wire 1 X) out3 $end $upscope $end $scope module TwoMux $end -$var wire 1 i& S $end -$var wire 1 j& in0 $end -$var wire 1 k& in1 $end -$var wire 1 l& nS $end -$var wire 1 m& out0 $end -$var wire 1 n& out1 $end -$var wire 1 o& outfinal $end +$var wire 1 Y) S $end +$var wire 1 Z) in0 $end +$var wire 1 [) in1 $end +$var wire 1 \) nS $end +$var wire 1 ]) out0 $end +$var wire 1 ^) out1 $end +$var wire 1 _) outfinal $end $upscope $end $upscope $end $scope begin muxbits[2] $end $scope module ZeroMux $end -$var wire 1 p& S0 $end -$var wire 1 q& S1 $end -$var wire 1 r& in0 $end -$var wire 1 s& in1 $end -$var wire 1 t& in2 $end -$var wire 1 u& in3 $end -$var wire 1 v& nS0 $end -$var wire 1 w& nS1 $end -$var wire 1 x& out $end -$var wire 1 y& out0 $end -$var wire 1 z& out1 $end -$var wire 1 {& out2 $end -$var wire 1 |& out3 $end +$var wire 1 `) S0 $end +$var wire 1 a) S1 $end +$var wire 1 b) in0 $end +$var wire 1 c) in1 $end +$var wire 1 d) in2 $end +$var wire 1 e) in3 $end +$var wire 1 f) nS0 $end +$var wire 1 g) nS1 $end +$var wire 1 h) out $end +$var wire 1 i) out0 $end +$var wire 1 j) out1 $end +$var wire 1 k) out2 $end +$var wire 1 l) out3 $end $upscope $end $scope module OneMux $end -$var wire 1 }& S0 $end -$var wire 1 ~& S1 $end -$var wire 1 !' in0 $end -$var wire 1 "' in1 $end -$var wire 1 #' in2 $end -$var wire 1 $' in3 $end -$var wire 1 %' nS0 $end -$var wire 1 &' nS1 $end -$var wire 1 '' out $end -$var wire 1 (' out0 $end -$var wire 1 )' out1 $end -$var wire 1 *' out2 $end -$var wire 1 +' out3 $end +$var wire 1 m) S0 $end +$var wire 1 n) S1 $end +$var wire 1 o) in0 $end +$var wire 1 p) in1 $end +$var wire 1 q) in2 $end +$var wire 1 r) in3 $end +$var wire 1 s) nS0 $end +$var wire 1 t) nS1 $end +$var wire 1 u) out $end +$var wire 1 v) out0 $end +$var wire 1 w) out1 $end +$var wire 1 x) out2 $end +$var wire 1 y) out3 $end $upscope $end $scope module TwoMux $end -$var wire 1 ,' S $end -$var wire 1 -' in0 $end -$var wire 1 .' in1 $end -$var wire 1 /' nS $end -$var wire 1 0' out0 $end -$var wire 1 1' out1 $end -$var wire 1 2' outfinal $end +$var wire 1 z) S $end +$var wire 1 {) in0 $end +$var wire 1 |) in1 $end +$var wire 1 }) nS $end +$var wire 1 ~) out0 $end +$var wire 1 !* out1 $end +$var wire 1 "* outfinal $end $upscope $end $upscope $end $scope begin muxbits[3] $end $scope module ZeroMux $end -$var wire 1 3' S0 $end -$var wire 1 4' S1 $end -$var wire 1 5' in0 $end -$var wire 1 6' in1 $end -$var wire 1 7' in2 $end -$var wire 1 8' in3 $end -$var wire 1 9' nS0 $end -$var wire 1 :' nS1 $end -$var wire 1 ;' out $end -$var wire 1 <' out0 $end -$var wire 1 =' out1 $end -$var wire 1 >' out2 $end -$var wire 1 ?' out3 $end +$var wire 1 #* S0 $end +$var wire 1 $* S1 $end +$var wire 1 %* in0 $end +$var wire 1 &* in1 $end +$var wire 1 '* in2 $end +$var wire 1 (* in3 $end +$var wire 1 )* nS0 $end +$var wire 1 ** nS1 $end +$var wire 1 +* out $end +$var wire 1 ,* out0 $end +$var wire 1 -* out1 $end +$var wire 1 .* out2 $end +$var wire 1 /* out3 $end $upscope $end $scope module OneMux $end -$var wire 1 @' S0 $end -$var wire 1 A' S1 $end -$var wire 1 B' in0 $end -$var wire 1 C' in1 $end -$var wire 1 D' in2 $end -$var wire 1 E' in3 $end -$var wire 1 F' nS0 $end -$var wire 1 G' nS1 $end -$var wire 1 H' out $end -$var wire 1 I' out0 $end -$var wire 1 J' out1 $end -$var wire 1 K' out2 $end -$var wire 1 L' out3 $end +$var wire 1 0* S0 $end +$var wire 1 1* S1 $end +$var wire 1 2* in0 $end +$var wire 1 3* in1 $end +$var wire 1 4* in2 $end +$var wire 1 5* in3 $end +$var wire 1 6* nS0 $end +$var wire 1 7* nS1 $end +$var wire 1 8* out $end +$var wire 1 9* out0 $end +$var wire 1 :* out1 $end +$var wire 1 ;* out2 $end +$var wire 1 <* out3 $end $upscope $end $scope module TwoMux $end -$var wire 1 M' S $end -$var wire 1 N' in0 $end -$var wire 1 O' in1 $end -$var wire 1 P' nS $end -$var wire 1 Q' out0 $end -$var wire 1 R' out1 $end -$var wire 1 S' outfinal $end +$var wire 1 =* S $end +$var wire 1 >* in0 $end +$var wire 1 ?* in1 $end +$var wire 1 @* nS $end +$var wire 1 A* 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+0^' +1g +1{" +1k% +1-' +1{# +1y' #60040000 -0%# -0Z% -02# -0g% -0Y -00$ +0L$ +0J( +0Y$ +0W( +0Z +0n" +0^% +0~& #60050000 -1^& -1_& -1[ -12$ -1N" -1%% +1N) +1O) +1\ +1p" +1`% +1"' +1u# +1s' b1111 # -b1111 >" -b1111 Y# -b1111 s$ +b1111 e# +b1111 "% +b1111 c' #60060000 -0S& -0`& -0a& -0(# -0]% +0C) +0P) +0Q) +0O$ +0M( b0 % -b0 l" -b0 _# -b0 C% -0\ -03$ +b0 5$ +b0 (% +b0 3( +0] +0q" +0a% +0#' #60070000 -1h& +1X) #60080000 -0k& -0u -0L$ -1g -1>$ -0d& -b0 \# -0_ -b1101 2 -06$ -b1101 g# -1X -b10 4 -1/$ -b10 i# -#60090000 +0[) +0v +02# +0"& +0<' +1h +1|" +1l% +1.' +0T) +b0 %% +0` +b1101 3 +0t" +b1101 A" +0d% +b1101 1% +0&' +b1101 W& 1Y -10$ +b10 5 +1m" +b10 C" +1]% +b10 3% +1}& +b10 Y& +#60090000 +1Z +1n" +1^% +1~& #60100000 -0s -0J$ +0t +00# +0~% +0:' #60110000 -1\ -13$ +1] +1q" +1a% +1#' #60120000 -0." -0c$ -1~ -1U$ -0v -b1001 2 -0M$ -b1001 g# -1o -b110 4 -1F$ -b110 i# +0/" +0O# +0?& +0S' +1!" +1;# +1+& +1E' +0w +b1001 3 +03# +b1001 A" +0#& +b1001 1% +0=' +b1001 W& +1p +b110 5 +1,# +b110 C" +1z% +b110 3% +16' +b110 Y& #60130000 -1u -1L$ -0g -0>$ -1_ -b1011 2 -16$ -b1011 g# -0X -b100 4 -0/$ -b100 i# +1v +12# +1"& +1<' +0h +0|" +0l% +0.' +1` +b1011 3 +1t" +b1011 A" +1d% +b1011 1% +1&' +b1011 W& +0Y +b100 5 +0m" +b100 C" +0]% +b100 3% +0}& +b100 Y& #60140000 -0," -0a$ +0-" +0M# +0=& +0Q' #60150000 -1s -1J$ +1t +10# +1~% +1:' #60160000 -17" -1l$ -0/" -b11 2 -0d$ -b11 g# -1(" -b1100 4 -1]$ -b1100 i# -1) +18" +1X# +1H& +1\' +00" +b11 3 +0P# +b11 A" +0@& +b11 1% +0T' +b11 W& +1)" +b1100 5 +1I# +b1100 C" +19& +b1100 3% +1M' +b1100 Y& +1* #60170000 -1." -1c$ -0~ -0U$ -0= -0r# -1v -b111 2 -1M$ -b111 g# -0o -b1000 4 -0F$ -b1000 i# +1/" +1O# +1?& +1S' +0!" +0;# +0+& +0E' +0> +0M" +0=% +0b& +1w +b111 3 +13# +b111 A" +1#& +b111 1% +1=' +b111 W& +0p +b1000 5 +0,# +b1000 C" +0z% +b1000 3% +06' +b1000 Y& #60180000 -0( -15 -1j# +0) +16 +1D" +14% +1Z& #60190000 -1," -1a$ +1-" +1M# +1=& +1Q' #60200000 -18 -1m# +19 +1H" +18% +1]& #60210000 -07" -0l$ -1/" -b1111 2 -1d$ -b1111 g# -0(" -b0 4 -0]$ -b0 i# +08" +0X# +0H& +0\' +10" +b1111 3 +1P# +b1111 A" +1@& +b1111 1% +1T' +b1111 W& +0)" +b0 5 +0I# +b0 C" +09& +b0 3% +0M' +b0 Y& #60220000 -1& +1' #60230000 -1( +0g" +0W% +1) +#60240000 +1i" +1Y% +#60260000 +1#) +1j" +1Z% +b1 & +b1 F" +b1 )% +b1 6% #60270000 -0) +0*) +0* #60280000 -1= -1r# +19) +1&) +b1 $% +1> +1M" +1=% +1b& #60290000 -05 -0j# +06 +0D" +04% +0Z& +#60300000 +1<) #60310000 -08 -0m# +09 +0H" +08% +0]& +#60320000 +1>) +b1 $ +b1 '% #60330000 -0& +0' +#60340000 +1g" +1W% +b1 ( +b1 *% +#60350000 +0i" +0Y% +#60360000 +b11 ( +b11 *% +#60370000 +0#) +0j" +0Z% +b0 & +b0 F" +b0 )% +b0 6% +#60380000 +1*) +b111 ( +b111 *% +#60390000 +09) +0&) +b0 $% +#60400000 +b1111 ( +b1111 *% +#60410000 +0-% +0<) +#60430000 +0" +0>) +b0 $ +b0 '% +#60450000 +b1110 ( +b1110 *% +#60470000 +b1100 ( +b1100 *% +#60490000 +b1000 ( +b1000 *% +#60510000 +b0 ( +b0 *% +#60520000 +1-% +#60540000 +1" #61000000 diff --git a/alu.v b/alu.v index 415432c..8d2acb0 100644 --- a/alu.v +++ b/alu.v @@ -224,9 +224,7 @@ input [size-1:0]carryin // we think this doesn't do anything but don't want to wire SLTflag0; wire SLTflag1; wire nCmd2; - - - + `NOT n0(nCmd2, Command[2]); //`AND subtractchoose(subtract, Command[0], nCmd2); @@ -234,10 +232,7 @@ input [size-1:0]carryin // we think this doesn't do anything but don't want to `AND sltcheck0(SLTon, Command[0], Command[1], nCmd2); MiddleAddSubSLT attempt2(NewVal[0], CarryoutWire[0], subtract[0], A[0], B[0], Command, subtract[0]); TwoInMux setSLTres(AddSubSLTSum[0], SLTon, NewVal[0], 0); - - - - + genvar i; parameter size = 4; generate @@ -249,13 +244,6 @@ input [size-1:0]carryin // we think this doesn't do anything but don't want to end endgenerate - /*genvar j; - generate - for (j=1; j; -v0x245e5f0_0 .var "A", 3 0; -RS_0x7f3880bf1098/0/0 .resolv tri, L_0x24608b0, L_0x24625c0, L_0x24641e0, L_0x2466260; -RS_0x7f3880bf1098/0/4 .resolv tri, L_0x2478450, L_0x2479fc0, L_0x247b9e0, L_0x247d920; -RS_0x7f3880bf1098 .resolv tri, RS_0x7f3880bf1098/0/0, RS_0x7f3880bf1098/0/4, C4, C4; -v0x245e670_0 .net8 "AddSubSLTSum", 3 0, RS_0x7f3880bf1098; 8 drivers -v0x245e6f0_0 .net "AllZeros", 0 0, L_0x2488c80; 1 drivers -RS_0x7f3880befe38/0/0 .resolv tri, L_0x2467c20, L_0x24686d0, L_0x2469140, L_0x2469ba0; -RS_0x7f3880befe38/0/4 .resolv tri, L_0x247f1f0, L_0x247fc60, L_0x24806d0, L_0x2481230; -RS_0x7f3880befe38 .resolv tri, RS_0x7f3880befe38/0/0, RS_0x7f3880befe38/0/4, C4, C4; -v0x245e770_0 .net8 "AndNandOut", 3 0, RS_0x7f3880befe38; 8 drivers -v0x245e7f0_0 .var "B", 3 0; -v0x245e870_0 .var "Command", 2 0; -RS_0x7f3880bf1578 .resolv tri, L_0x2470cd0, L_0x2473950, L_0x24765b0, L_0x24880f0; -v0x245e8f0_0 .net8 "OneBitFinalOut", 3 0, RS_0x7f3880bf1578; 4 drivers -RS_0x7f3880bef748/0/0 .resolv tri, L_0x246aef0, L_0x246c450, L_0x246d750, L_0x246ea40; -RS_0x7f3880bef748/0/4 .resolv tri, L_0x24825f0, L_0x24838f0, L_0x2484bf0, L_0x2485ee0; -RS_0x7f3880bef748 .resolv tri, RS_0x7f3880bef748/0/0, RS_0x7f3880bef748/0/4, C4, C4; -v0x245e970_0 .net8 "OrNorXorOut", 3 0, RS_0x7f3880bef748; 8 drivers -RS_0x7f3880bf1188 .resolv tri, L_0x24672e0, L_0x247e8f0, C4, C4; -v0x245ea40_0 .net8 "SLTflag", 0 0, RS_0x7f3880bf1188; 2 drivers -RS_0x7f3880bf15a8 .resolv tri, L_0x2471180, L_0x2473e20, L_0x24766f0, L_0x24883b0; -v0x245eac0_0 .net8 "ZeroFlag", 3 0, RS_0x7f3880bf15a8; 4 drivers -v0x245eb40_0 .var "carryin", 3 0; -RS_0x7f3880bf13c8 .resolv tri, L_0x2466530, L_0x247dbf0, C4, C4; -v0x245ebc0_0 .net8 "carryout", 0 0, RS_0x7f3880bf13c8; 2 drivers -RS_0x7f3880bf1488 .resolv tri, L_0x2466300, L_0x247da20, C4, C4; -v0x245ec40_0 .net8 "overflow", 0 0, RS_0x7f3880bf1488; 2 drivers -RS_0x7f3880bf14b8/0/0 .resolv tri, L_0x2460020, L_0x2461dd0, L_0x2463b30, L_0x2465af0; -RS_0x7f3880bf14b8/0/4 .resolv tri, L_0x2477d30, L_0x2479830, L_0x247b370, L_0x247d220; -RS_0x7f3880bf14b8 .resolv tri, RS_0x7f3880bf14b8/0/0, RS_0x7f3880bf14b8/0/4, C4, C4; -v0x245ecc0_0 .net8 "subtract", 3 0, RS_0x7f3880bf14b8; 8 drivers -S_0x24576a0 .scope module, "trial" "AddSubSLT32" 2 145, 3 205, S_0x23b34d0; - .timescale -9 -12; -P_0x2457798 .param/l "size" 3 242, +C4<0100>; -L_0x2464440/d .functor NOT 1, L_0x2464530, C4<0>, C4<0>, C4<0>; -L_0x2464440 .delay (10000,10000,10000) L_0x2464440/d; -L_0x24645d0/d .functor AND 1, L_0x2464710, L_0x2464370, L_0x2464440, C4<1>; -L_0x24645d0 .delay (20000,20000,20000) L_0x24645d0/d; -L_0x2466530/d .functor OR 1, L_0x2466660, C4<0>, C4<0>, C4<0>; -L_0x2466530 .delay (20000,20000,20000) L_0x2466530/d; -L_0x2466300/d .functor XOR 1, RS_0x7f3880bf13c8, L_0x2466980, C4<0>, C4<0>; -L_0x2466300 .delay (40000,40000,40000) L_0x2466300/d; -L_0x2466a20/d .functor NOT 1, RS_0x7f3880bf1488, C4<0>, C4<0>, C4<0>; -L_0x2466a20 .delay (10000,10000,10000) L_0x2466a20/d; -L_0x2466b10/d .functor NOT 1, L_0x2466bf0, C4<0>, C4<0>, C4<0>; -L_0x2466b10 .delay (10000,10000,10000) L_0x2466b10/d; -L_0x2460950/d .functor AND 1, L_0x2466a20, L_0x2466ee0, C4<1>, C4<1>; -L_0x2460950 .delay (20000,20000,20000) L_0x2460950/d; -L_0x2466f80/d .functor AND 1, RS_0x7f3880bf1488, L_0x2466b10, C4<1>, C4<1>; -L_0x2466f80 .delay (20000,20000,20000) L_0x2466f80/d; -L_0x2467070/d .functor AND 1, L_0x2460950, L_0x24645d0, C4<1>, C4<1>; -L_0x2467070 .delay (20000,20000,20000) L_0x2467070/d; -L_0x2467170/d .functor AND 1, L_0x2466f80, L_0x24645d0, C4<1>, C4<1>; -L_0x2467170 .delay (20000,20000,20000) L_0x2467170/d; -L_0x24672e0/d .functor OR 1, L_0x2467070, L_0x2467170, C4<0>, C4<0>; -L_0x24672e0 .delay (20000,20000,20000) L_0x24672e0/d; -v0x245d340_0 .net "A", 3 0, v0x245e5f0_0; 1 drivers -v0x245d3e0_0 .alias "AddSubSLTSum", 3 0, v0x245e670_0; -v0x245d460_0 .net "B", 3 0, v0x245e7f0_0; 1 drivers -RS_0x7f3880bf3d08 .resolv tri, L_0x245ff30, L_0x2461c80, L_0x24639a0, L_0x24647b0; -v0x245d4e0_0 .net8 "CarryoutWire", 3 0, RS_0x7f3880bf3d08; 4 drivers -v0x245d560_0 .net "Command", 2 0, v0x245e870_0; 1 drivers -RS_0x7f3880bf3d38 .resolv tri, L_0x245fe40, L_0x2461b90, L_0x24638b0, L_0x24658c0; -v0x245d5e0_0 .net8 "NewVal", 3 0, RS_0x7f3880bf3d38; 4 drivers -v0x245d680_0 .net "Res0OF1", 0 0, L_0x2466f80; 1 drivers -v0x245d720_0 .net "Res1OF0", 0 0, L_0x2460950; 1 drivers -v0x245d810_0 .alias "SLTflag", 0 0, v0x245ea40_0; -v0x245d8e0_0 .net "SLTflag0", 0 0, L_0x2467070; 1 drivers -v0x245d980_0 .net "SLTflag1", 0 0, L_0x2467170; 1 drivers -v0x245da20_0 .net "SLTon", 0 0, L_0x24645d0; 1 drivers -v0x245db30_0 .net *"_s37", 0 0, L_0x2464530; 1 drivers -v0x245dbd0_0 .net *"_s39", 0 0, L_0x2464710; 1 drivers -v0x245dcf0_0 .net *"_s41", 0 0, L_0x2464370; 1 drivers -v0x245dd90_0 .net *"_s61", 0 0, L_0x2466660; 1 drivers -v0x245dc50_0 .net/s *"_s62", 0 0, C4<0>; 1 drivers -v0x245dee0_0 .net *"_s65", 0 0, L_0x2466980; 1 drivers -v0x245e000_0 .net *"_s67", 0 0, L_0x2466bf0; 1 drivers -v0x245e080_0 .net *"_s69", 0 0, L_0x2466ee0; 1 drivers -v0x245df60_0 .net "carryin", 3 0, v0x245eb40_0; 1 drivers -v0x245e1b0_0 .alias "carryout", 0 0, v0x245ebc0_0; -v0x245e100_0 .net "nAddSubSLTSum", 0 0, L_0x2466b10; 1 drivers -v0x245e2f0_0 .net "nCmd2", 0 0, L_0x2464440; 1 drivers -v0x245e230_0 .net "nOF", 0 0, L_0x2466a20; 1 drivers -v0x245e440_0 .alias "overflow", 0 0, v0x245ec40_0; -v0x245e3c0_0 .alias "subtract", 3 0, v0x245ecc0_0; -L_0x245fe40 .part/pv L_0x245f960, 1, 1, 4; -L_0x245ff30 .part/pv L_0x245fce0, 1, 1, 4; -L_0x2460020 .part/pv L_0x2450740, 1, 1, 4; -L_0x2460150 .part v0x245e5f0_0, 1, 1; -L_0x2460300 .part v0x245e7f0_0, 1, 1; -L_0x24604b0 .part RS_0x7f3880bf3d08, 0, 1; -L_0x24608b0 .part/pv L_0x2460770, 1, 1, 4; -L_0x24609e0 .part RS_0x7f3880bf3d38, 1, 1; -L_0x2461b90 .part/pv L_0x24616e0, 2, 1, 4; -L_0x2461c80 .part/pv L_0x2461a30, 2, 1, 4; -L_0x2461dd0 .part/pv L_0x2461410, 2, 1, 4; -L_0x2461e70 .part v0x245e5f0_0, 2, 1; -L_0x2461f80 .part v0x245e7f0_0, 2, 1; -L_0x24620b0 .part RS_0x7f3880bf3d08, 1, 1; -L_0x24625c0 .part/pv L_0x24624d0, 2, 1, 4; -L_0x2462660 .part RS_0x7f3880bf3d38, 2, 1; -L_0x24638b0 .part/pv L_0x2463400, 3, 1, 4; -L_0x24639a0 .part/pv L_0x2463750, 3, 1, 4; -L_0x2463b30 .part/pv L_0x2463130, 3, 1, 4; -L_0x2463bd0 .part v0x245e5f0_0, 3, 1; -L_0x2463a90 .part v0x245e7f0_0, 3, 1; -L_0x2463db0 .part RS_0x7f3880bf3d08, 2, 1; -L_0x24641e0 .part/pv L_0x24640a0, 3, 1, 4; -L_0x2464280 .part RS_0x7f3880bf3d38, 3, 1; -L_0x2464530 .part v0x245e870_0, 2, 1; -L_0x2464710 .part v0x245e870_0, 0, 1; -L_0x2464370 .part v0x245e870_0, 1, 1; -L_0x24658c0 .part/pv L_0x2465410, 0, 1, 4; -L_0x24647b0 .part/pv L_0x2465760, 0, 1, 4; -L_0x2465af0 .part/pv L_0x2465140, 0, 1, 4; -L_0x24659b0 .part v0x245e5f0_0, 0, 1; -L_0x2465ce0 .part v0x245e7f0_0, 0, 1; -L_0x2465be0 .part RS_0x7f3880bf14b8, 0, 1; -L_0x2466260 .part/pv L_0x2466120, 0, 1, 4; -L_0x2465e10 .part RS_0x7f3880bf3d38, 0, 1; -L_0x2466660 .part RS_0x7f3880bf3d08, 3, 1; -L_0x2466980 .part RS_0x7f3880bf3d08, 2, 1; -L_0x2466bf0 .part RS_0x7f3880bf1098, 3, 1; -L_0x2466ee0 .part RS_0x7f3880bf1098, 3, 1; -S_0x245c320 .scope module, "attempt2" "MiddleAddSubSLT" 3 235, 3 89, S_0x24576a0; - .timescale -9 -12; -L_0x24648e0/d .functor NOT 1, L_0x2465ce0, C4<0>, C4<0>, C4<0>; -L_0x24648e0 .delay (10000,10000,10000) L_0x24648e0/d; -L_0x2464fe0/d .functor NOT 1, L_0x24650a0, C4<0>, C4<0>, C4<0>; -L_0x2464fe0 .delay (10000,10000,10000) L_0x2464fe0/d; -L_0x2465140/d .functor AND 1, L_0x2465280, L_0x2464fe0, C4<1>, C4<1>; -L_0x2465140 .delay (20000,20000,20000) L_0x2465140/d; -L_0x2465320/d .functor XOR 1, L_0x24659b0, L_0x2464d70, C4<0>, C4<0>; -L_0x2465320 .delay (40000,40000,40000) L_0x2465320/d; -L_0x2465410/d .functor XOR 1, L_0x2465320, L_0x2465be0, C4<0>, C4<0>; -L_0x2465410 .delay (40000,40000,40000) L_0x2465410/d; -L_0x2465500/d .functor AND 1, L_0x24659b0, L_0x2464d70, C4<1>, C4<1>; -L_0x2465500 .delay (20000,20000,20000) L_0x2465500/d; -L_0x2465670/d .functor AND 1, L_0x2465320, L_0x2465be0, C4<1>, C4<1>; -L_0x2465670 .delay (20000,20000,20000) L_0x2465670/d; -L_0x2465760/d .functor OR 1, L_0x2465500, L_0x2465670, C4<0>, C4<0>; -L_0x2465760 .delay (20000,20000,20000) L_0x2465760/d; -v0x245c9a0_0 .net "A", 0 0, L_0x24659b0; 1 drivers -v0x245ca60_0 .net "AandB", 0 0, L_0x2465500; 1 drivers -v0x245cb00_0 .net "AddSubSLTSum", 0 0, L_0x2465410; 1 drivers -v0x245cba0_0 .net "AxorB", 0 0, L_0x2465320; 1 drivers -v0x245cc20_0 .net "B", 0 0, L_0x2465ce0; 1 drivers -v0x245ccd0_0 .net "BornB", 0 0, L_0x2464d70; 1 drivers -v0x245cd90_0 .net "CINandAxorB", 0 0, L_0x2465670; 1 drivers -v0x245ce10_0 .alias "Command", 2 0, v0x245d560_0; -v0x245ce90_0 .net *"_s3", 0 0, L_0x24650a0; 1 drivers -v0x245cf10_0 .net *"_s5", 0 0, L_0x2465280; 1 drivers -v0x245cfb0_0 .net "carryin", 0 0, L_0x2465be0; 1 drivers -v0x245d050_0 .net "carryout", 0 0, L_0x2465760; 1 drivers -v0x245d0f0_0 .net "nB", 0 0, L_0x24648e0; 1 drivers -v0x245d1a0_0 .net "nCmd2", 0 0, L_0x2464fe0; 1 drivers -v0x245d2a0_0 .net "subtract", 0 0, L_0x2465140; 1 drivers -L_0x2464f40 .part v0x245e870_0, 0, 1; -L_0x24650a0 .part v0x245e870_0, 2, 1; -L_0x2465280 .part v0x245e870_0, 0, 1; -S_0x245c410 .scope module, "mux0" "TwoInMux" 3 105, 3 8, S_0x245c320; - .timescale -9 -12; -L_0x2464a90/d .functor NOT 1, L_0x2464f40, C4<0>, C4<0>, C4<0>; -L_0x2464a90 .delay (10000,10000,10000) L_0x2464a90/d; -L_0x2464b50/d .functor AND 1, L_0x2465ce0, L_0x2464a90, C4<1>, C4<1>; -L_0x2464b50 .delay (20000,20000,20000) L_0x2464b50/d; -L_0x2464c60/d .functor AND 1, L_0x24648e0, L_0x2464f40, C4<1>, C4<1>; -L_0x2464c60 .delay (20000,20000,20000) L_0x2464c60/d; -L_0x2464d70/d .functor OR 1, L_0x2464b50, L_0x2464c60, C4<0>, C4<0>; -L_0x2464d70 .delay (20000,20000,20000) L_0x2464d70/d; -v0x245c500_0 .net "S", 0 0, L_0x2464f40; 1 drivers -v0x245c5c0_0 .alias "in0", 0 0, v0x245cc20_0; -v0x245c660_0 .alias "in1", 0 0, v0x245d0f0_0; -v0x245c700_0 .net "nS", 0 0, L_0x2464a90; 1 drivers -v0x245c780_0 .net "out0", 0 0, L_0x2464b50; 1 drivers -v0x245c820_0 .net "out1", 0 0, L_0x2464c60; 1 drivers -v0x245c900_0 .alias "outfinal", 0 0, v0x245ccd0_0; -S_0x245bdc0 .scope module, "setSLTres" "TwoInMux" 3 236, 3 8, S_0x24576a0; - .timescale -9 -12; -L_0x2465c80/d .functor NOT 1, L_0x24645d0, C4<0>, C4<0>, C4<0>; -L_0x2465c80 .delay (10000,10000,10000) L_0x2465c80/d; -L_0x24600c0/d .functor AND 1, L_0x2465e10, L_0x2465c80, C4<1>, C4<1>; -L_0x24600c0 .delay (20000,20000,20000) L_0x24600c0/d; -L_0x2466080/d .functor AND 1, C4<0>, L_0x24645d0, C4<1>, C4<1>; -L_0x2466080 .delay (20000,20000,20000) L_0x2466080/d; -L_0x2466120/d .functor OR 1, L_0x24600c0, L_0x2466080, C4<0>, C4<0>; -L_0x2466120 .delay (20000,20000,20000) L_0x2466120/d; -v0x245beb0_0 .alias "S", 0 0, v0x245da20_0; -v0x245bf50_0 .net "in0", 0 0, L_0x2465e10; 1 drivers -v0x245bff0_0 .net "in1", 0 0, C4<0>; 1 drivers -v0x245c090_0 .net "nS", 0 0, L_0x2465c80; 1 drivers -v0x245c140_0 .net "out0", 0 0, L_0x24600c0; 1 drivers -v0x245c1e0_0 .net "out1", 0 0, L_0x2466080; 1 drivers -v0x245c280_0 .net "outfinal", 0 0, L_0x2466120; 1 drivers -S_0x245a600 .scope generate, "addbits[1]" "addbits[1]" 3 244, 3 244, S_0x24576a0; - .timescale -9 -12; -P_0x245a6f8 .param/l "i" 3 244, +C4<01>; -S_0x245ad50 .scope module, "attempt" "MiddleAddSubSLT" 3 246, 3 89, S_0x245a600; - .timescale -9 -12; -L_0x2458b60/d .functor NOT 1, L_0x2460300, C4<0>, C4<0>, C4<0>; -L_0x2458b60 .delay (10000,10000,10000) L_0x2458b60/d; -L_0x245a370/d .functor NOT 1, L_0x24506a0, C4<0>, C4<0>, C4<0>; -L_0x245a370 .delay (10000,10000,10000) L_0x245a370/d; -L_0x2450740/d .functor AND 1, L_0x245f7d0, L_0x245a370, C4<1>, C4<1>; -L_0x2450740 .delay (20000,20000,20000) L_0x2450740/d; -L_0x245f870/d .functor XOR 1, L_0x2460150, L_0x245f100, C4<0>, C4<0>; -L_0x245f870 .delay (40000,40000,40000) L_0x245f870/d; -L_0x245f960/d .functor XOR 1, L_0x245f870, L_0x24604b0, C4<0>, C4<0>; -L_0x245f960 .delay (40000,40000,40000) L_0x245f960/d; -L_0x245fa50/d .functor AND 1, L_0x2460150, L_0x245f100, C4<1>, C4<1>; -L_0x245fa50 .delay (20000,20000,20000) L_0x245fa50/d; -L_0x245fbf0/d .functor AND 1, L_0x245f870, L_0x24604b0, C4<1>, C4<1>; -L_0x245fbf0 .delay (20000,20000,20000) L_0x245fbf0/d; -L_0x245fce0/d .functor OR 1, L_0x245fa50, L_0x245fbf0, C4<0>, C4<0>; -L_0x245fce0 .delay (20000,20000,20000) L_0x245fce0/d; -v0x245b3d0_0 .net "A", 0 0, L_0x2460150; 1 drivers -v0x245b490_0 .net "AandB", 0 0, L_0x245fa50; 1 drivers -v0x245b530_0 .net "AddSubSLTSum", 0 0, L_0x245f960; 1 drivers -v0x245b5d0_0 .net "AxorB", 0 0, L_0x245f870; 1 drivers -v0x245b650_0 .net "B", 0 0, L_0x2460300; 1 drivers -v0x245b700_0 .net "BornB", 0 0, L_0x245f100; 1 drivers -v0x245b7c0_0 .net "CINandAxorB", 0 0, L_0x245fbf0; 1 drivers -v0x245b840_0 .alias "Command", 2 0, v0x245d560_0; -v0x245b910_0 .net *"_s3", 0 0, L_0x24506a0; 1 drivers -v0x245b990_0 .net *"_s5", 0 0, L_0x245f7d0; 1 drivers -v0x245ba30_0 .net "carryin", 0 0, L_0x24604b0; 1 drivers -v0x245bad0_0 .net "carryout", 0 0, L_0x245fce0; 1 drivers -v0x245bb70_0 .net "nB", 0 0, L_0x2458b60; 1 drivers -v0x245bc20_0 .net "nCmd2", 0 0, L_0x245a370; 1 drivers -v0x245bd20_0 .net "subtract", 0 0, L_0x2450740; 1 drivers -L_0x245f2d0 .part v0x245e870_0, 0, 1; -L_0x24506a0 .part v0x245e870_0, 2, 1; -L_0x245f7d0 .part v0x245e870_0, 0, 1; -S_0x245ae40 .scope module, "mux0" "TwoInMux" 3 105, 3 8, S_0x245ad50; - .timescale -9 -12; -L_0x245ee60/d .functor NOT 1, L_0x245f2d0, C4<0>, C4<0>, C4<0>; -L_0x245ee60 .delay (10000,10000,10000) L_0x245ee60/d; -L_0x245eee0/d .functor AND 1, L_0x2460300, L_0x245ee60, C4<1>, C4<1>; -L_0x245eee0 .delay (20000,20000,20000) L_0x245eee0/d; -L_0x245eff0/d .functor AND 1, L_0x2458b60, L_0x245f2d0, C4<1>, C4<1>; -L_0x245eff0 .delay (20000,20000,20000) L_0x245eff0/d; -L_0x245f100/d .functor OR 1, L_0x245eee0, L_0x245eff0, C4<0>, C4<0>; -L_0x245f100 .delay (20000,20000,20000) L_0x245f100/d; -v0x245af30_0 .net "S", 0 0, L_0x245f2d0; 1 drivers -v0x245aff0_0 .alias "in0", 0 0, v0x245b650_0; -v0x245b090_0 .alias "in1", 0 0, v0x245bb70_0; -v0x245b130_0 .net "nS", 0 0, L_0x245ee60; 1 drivers -v0x245b1b0_0 .net "out0", 0 0, L_0x245eee0; 1 drivers -v0x245b250_0 .net "out1", 0 0, L_0x245eff0; 1 drivers -v0x245b330_0 .alias "outfinal", 0 0, v0x245b700_0; -S_0x245a7b0 .scope module, "setSLTres" "TwoInMux" 3 247, 3 8, S_0x245a600; - .timescale -9 -12; -L_0x2454450/d .functor NOT 1, L_0x24645d0, C4<0>, C4<0>, C4<0>; -L_0x2454450 .delay (10000,10000,10000) L_0x2454450/d; -L_0x24605e0/d .functor AND 1, L_0x24609e0, L_0x2454450, C4<1>, C4<1>; -L_0x24605e0 .delay (20000,20000,20000) L_0x24605e0/d; -L_0x24606d0/d .functor AND 1, C4<0>, L_0x24645d0, C4<1>, C4<1>; -L_0x24606d0 .delay (20000,20000,20000) L_0x24606d0/d; -L_0x2460770/d .functor OR 1, L_0x24605e0, L_0x24606d0, C4<0>, C4<0>; -L_0x2460770 .delay (20000,20000,20000) L_0x2460770/d; -v0x245a8a0_0 .alias "S", 0 0, v0x245da20_0; -v0x245a970_0 .net "in0", 0 0, L_0x24609e0; 1 drivers -v0x245aa10_0 .net "in1", 0 0, C4<0>; 1 drivers -v0x245aab0_0 .net "nS", 0 0, L_0x2454450; 1 drivers -v0x245ab30_0 .net "out0", 0 0, L_0x24605e0; 1 drivers -v0x245abd0_0 .net "out1", 0 0, L_0x24606d0; 1 drivers -v0x245acb0_0 .net "outfinal", 0 0, L_0x2460770; 1 drivers -S_0x2458f70 .scope generate, "addbits[2]" "addbits[2]" 3 244, 3 244, S_0x24576a0; - .timescale -9 -12; -P_0x2458928 .param/l "i" 3 244, +C4<010>; -S_0x2459670 .scope module, "attempt" "MiddleAddSubSLT" 3 246, 3 89, S_0x2458f70; - .timescale -9 -12; -L_0x2460b70/d .functor NOT 1, L_0x2461f80, C4<0>, C4<0>, C4<0>; -L_0x2460b70 .delay (10000,10000,10000) L_0x2460b70/d; -L_0x24612b0/d .functor NOT 1, L_0x2461370, C4<0>, C4<0>, C4<0>; -L_0x24612b0 .delay (10000,10000,10000) L_0x24612b0/d; -L_0x2461410/d .functor AND 1, L_0x2461550, L_0x24612b0, C4<1>, C4<1>; -L_0x2461410 .delay (20000,20000,20000) L_0x2461410/d; -L_0x24615f0/d .functor XOR 1, L_0x2461e70, L_0x2461040, C4<0>, C4<0>; -L_0x24615f0 .delay (40000,40000,40000) L_0x24615f0/d; -L_0x24616e0/d .functor XOR 1, L_0x24615f0, L_0x24620b0, C4<0>, C4<0>; -L_0x24616e0 .delay (40000,40000,40000) L_0x24616e0/d; -L_0x24617d0/d .functor AND 1, L_0x2461e70, L_0x2461040, C4<1>, C4<1>; -L_0x24617d0 .delay (20000,20000,20000) L_0x24617d0/d; -L_0x2461940/d .functor AND 1, L_0x24615f0, L_0x24620b0, C4<1>, C4<1>; -L_0x2461940 .delay (20000,20000,20000) L_0x2461940/d; -L_0x2461a30/d .functor OR 1, L_0x24617d0, L_0x2461940, C4<0>, C4<0>; -L_0x2461a30 .delay (20000,20000,20000) L_0x2461a30/d; -v0x2459cf0_0 .net "A", 0 0, L_0x2461e70; 1 drivers -v0x2459db0_0 .net "AandB", 0 0, L_0x24617d0; 1 drivers -v0x2459e50_0 .net "AddSubSLTSum", 0 0, L_0x24616e0; 1 drivers -v0x2459ef0_0 .net "AxorB", 0 0, L_0x24615f0; 1 drivers -v0x2459f70_0 .net "B", 0 0, L_0x2461f80; 1 drivers -v0x2459ff0_0 .net "BornB", 0 0, L_0x2461040; 1 drivers -v0x245a070_0 .net "CINandAxorB", 0 0, L_0x2461940; 1 drivers -v0x245a0f0_0 .alias "Command", 2 0, v0x245d560_0; -v0x245a170_0 .net *"_s3", 0 0, L_0x2461370; 1 drivers -v0x245a1f0_0 .net *"_s5", 0 0, L_0x2461550; 1 drivers -v0x245a270_0 .net "carryin", 0 0, L_0x24620b0; 1 drivers -v0x245a2f0_0 .net "carryout", 0 0, L_0x2461a30; 1 drivers -v0x245a3e0_0 .net "nB", 0 0, L_0x2460b70; 1 drivers -v0x245a460_0 .net "nCmd2", 0 0, L_0x24612b0; 1 drivers -v0x245a560_0 .net "subtract", 0 0, L_0x2461410; 1 drivers -L_0x2461210 .part v0x245e870_0, 0, 1; -L_0x2461370 .part v0x245e870_0, 2, 1; -L_0x2461550 .part v0x245e870_0, 0, 1; -S_0x2459760 .scope module, "mux0" "TwoInMux" 3 105, 3 8, S_0x2459670; - .timescale -9 -12; -L_0x2460d60/d .functor NOT 1, L_0x2461210, C4<0>, C4<0>, C4<0>; -L_0x2460d60 .delay (10000,10000,10000) L_0x2460d60/d; -L_0x2460e20/d .functor AND 1, L_0x2461f80, L_0x2460d60, C4<1>, C4<1>; -L_0x2460e20 .delay (20000,20000,20000) L_0x2460e20/d; -L_0x2460f30/d .functor AND 1, L_0x2460b70, L_0x2461210, C4<1>, C4<1>; -L_0x2460f30 .delay (20000,20000,20000) L_0x2460f30/d; -L_0x2461040/d .functor OR 1, L_0x2460e20, L_0x2460f30, C4<0>, C4<0>; -L_0x2461040 .delay (20000,20000,20000) L_0x2461040/d; -v0x2459850_0 .net "S", 0 0, L_0x2461210; 1 drivers -v0x2459910_0 .alias "in0", 0 0, v0x2459f70_0; -v0x24599b0_0 .alias "in1", 0 0, v0x245a3e0_0; -v0x2459a50_0 .net "nS", 0 0, L_0x2460d60; 1 drivers -v0x2459ad0_0 .net "out0", 0 0, L_0x2460e20; 1 drivers -v0x2459b70_0 .net "out1", 0 0, L_0x2460f30; 1 drivers -v0x2459c50_0 .alias "outfinal", 0 0, v0x2459ff0_0; -S_0x24590e0 .scope module, "setSLTres" "TwoInMux" 3 247, 3 8, S_0x2458f70; - .timescale -9 -12; -L_0x2461d70/d .functor NOT 1, L_0x24645d0, C4<0>, C4<0>, C4<0>; -L_0x2461d70 .delay (10000,10000,10000) L_0x2461d70/d; -L_0x24622a0/d .functor AND 1, L_0x2462660, L_0x2461d70, C4<1>, C4<1>; -L_0x24622a0 .delay (20000,20000,20000) L_0x24622a0/d; -L_0x2462360/d .functor AND 1, C4<0>, L_0x24645d0, C4<1>, C4<1>; -L_0x2462360 .delay (20000,20000,20000) L_0x2462360/d; -L_0x24624d0/d .functor OR 1, L_0x24622a0, L_0x2462360, C4<0>, C4<0>; -L_0x24624d0 .delay (20000,20000,20000) L_0x24624d0/d; -v0x24591d0_0 .alias "S", 0 0, v0x245da20_0; -v0x2459280_0 .net "in0", 0 0, L_0x2462660; 1 drivers -v0x2459300_0 .net "in1", 0 0, C4<0>; 1 drivers -v0x24593a0_0 .net "nS", 0 0, L_0x2461d70; 1 drivers -v0x2459450_0 .net "out0", 0 0, L_0x24622a0; 1 drivers -v0x24594f0_0 .net "out1", 0 0, L_0x2462360; 1 drivers -v0x24595d0_0 .net "outfinal", 0 0, L_0x24624d0; 1 drivers -S_0x2457810 .scope generate, "addbits[3]" "addbits[3]" 3 244, 3 244, S_0x24576a0; - .timescale -9 -12; -P_0x2457908 .param/l "i" 3 244, +C4<011>; -S_0x2457ef0 .scope module, "attempt" "MiddleAddSubSLT" 3 246, 3 89, S_0x2457810; - .timescale -9 -12; -L_0x24628b0/d .functor NOT 1, L_0x2463a90, C4<0>, C4<0>, C4<0>; -L_0x24628b0 .delay (10000,10000,10000) L_0x24628b0/d; -L_0x2462fd0/d .functor NOT 1, L_0x2463090, C4<0>, C4<0>, C4<0>; -L_0x2462fd0 .delay (10000,10000,10000) L_0x2462fd0/d; -L_0x2463130/d .functor AND 1, L_0x2463270, L_0x2462fd0, C4<1>, C4<1>; -L_0x2463130 .delay (20000,20000,20000) L_0x2463130/d; -L_0x2463310/d .functor XOR 1, L_0x2463bd0, L_0x2462d60, C4<0>, C4<0>; -L_0x2463310 .delay (40000,40000,40000) L_0x2463310/d; -L_0x2463400/d .functor XOR 1, L_0x2463310, L_0x2463db0, C4<0>, C4<0>; -L_0x2463400 .delay (40000,40000,40000) L_0x2463400/d; -L_0x24634f0/d .functor AND 1, L_0x2463bd0, L_0x2462d60, C4<1>, C4<1>; -L_0x24634f0 .delay (20000,20000,20000) L_0x24634f0/d; -L_0x2463660/d .functor AND 1, L_0x2463310, L_0x2463db0, C4<1>, C4<1>; -L_0x2463660 .delay (20000,20000,20000) L_0x2463660/d; -L_0x2463750/d .functor OR 1, L_0x24634f0, L_0x2463660, C4<0>, C4<0>; -L_0x2463750 .delay (20000,20000,20000) L_0x2463750/d; -v0x2458570_0 .net "A", 0 0, L_0x2463bd0; 1 drivers -v0x2458630_0 .net "AandB", 0 0, L_0x24634f0; 1 drivers -v0x24586d0_0 .net "AddSubSLTSum", 0 0, L_0x2463400; 1 drivers -v0x2458770_0 .net "AxorB", 0 0, L_0x2463310; 1 drivers -v0x24587f0_0 .net "B", 0 0, L_0x2463a90; 1 drivers -v0x24588a0_0 .net "BornB", 0 0, L_0x2462d60; 1 drivers -v0x2458960_0 .net "CINandAxorB", 0 0, L_0x2463660; 1 drivers -v0x24589e0_0 .alias "Command", 2 0, v0x245d560_0; -v0x2458a60_0 .net *"_s3", 0 0, L_0x2463090; 1 drivers -v0x2458ae0_0 .net *"_s5", 0 0, L_0x2463270; 1 drivers -v0x2458be0_0 .net "carryin", 0 0, L_0x2463db0; 1 drivers -v0x2458c80_0 .net "carryout", 0 0, L_0x2463750; 1 drivers -v0x2458d20_0 .net "nB", 0 0, L_0x24628b0; 1 drivers -v0x2458dd0_0 .net "nCmd2", 0 0, L_0x2462fd0; 1 drivers -v0x2458ed0_0 .net "subtract", 0 0, L_0x2463130; 1 drivers -L_0x2462f30 .part v0x245e870_0, 0, 1; -L_0x2463090 .part v0x245e870_0, 2, 1; -L_0x2463270 .part v0x245e870_0, 0, 1; -S_0x2457fe0 .scope module, "mux0" "TwoInMux" 3 105, 3 8, S_0x2457ef0; - .timescale -9 -12; -L_0x2462a80/d .functor NOT 1, L_0x2462f30, C4<0>, C4<0>, C4<0>; -L_0x2462a80 .delay (10000,10000,10000) L_0x2462a80/d; -L_0x2462b40/d .functor AND 1, L_0x2463a90, L_0x2462a80, C4<1>, C4<1>; -L_0x2462b40 .delay (20000,20000,20000) L_0x2462b40/d; -L_0x2462c50/d .functor AND 1, L_0x24628b0, L_0x2462f30, C4<1>, C4<1>; -L_0x2462c50 .delay (20000,20000,20000) L_0x2462c50/d; -L_0x2462d60/d .functor OR 1, L_0x2462b40, L_0x2462c50, C4<0>, C4<0>; -L_0x2462d60 .delay (20000,20000,20000) L_0x2462d60/d; -v0x24580d0_0 .net "S", 0 0, L_0x2462f30; 1 drivers -v0x2458190_0 .alias "in0", 0 0, v0x24587f0_0; -v0x2458230_0 .alias "in1", 0 0, v0x2458d20_0; -v0x24582d0_0 .net "nS", 0 0, L_0x2462a80; 1 drivers -v0x2458350_0 .net "out0", 0 0, L_0x2462b40; 1 drivers -v0x24583f0_0 .net "out1", 0 0, L_0x2462c50; 1 drivers -v0x24584d0_0 .alias "outfinal", 0 0, v0x24588a0_0; -S_0x2457980 .scope module, "setSLTres" "TwoInMux" 3 247, 3 8, S_0x2457810; - .timescale -9 -12; -L_0x2463c70/d .functor NOT 1, L_0x24645d0, C4<0>, C4<0>, C4<0>; -L_0x2463c70 .delay (10000,10000,10000) L_0x2463c70/d; -L_0x2463f10/d .functor AND 1, L_0x2464280, L_0x2463c70, C4<1>, C4<1>; -L_0x2463f10 .delay (20000,20000,20000) L_0x2463f10/d; -L_0x2464000/d .functor AND 1, C4<0>, L_0x24645d0, C4<1>, C4<1>; -L_0x2464000 .delay (20000,20000,20000) L_0x2464000/d; -L_0x24640a0/d .functor OR 1, L_0x2463f10, L_0x2464000, C4<0>, C4<0>; -L_0x24640a0 .delay (20000,20000,20000) L_0x24640a0/d; -v0x2457a70_0 .alias "S", 0 0, v0x245da20_0; -v0x2457b10_0 .net "in0", 0 0, L_0x2464280; 1 drivers -v0x2457bb0_0 .net "in1", 0 0, C4<0>; 1 drivers -v0x2457c50_0 .net "nS", 0 0, L_0x2463c70; 1 drivers -v0x2457cd0_0 .net "out0", 0 0, L_0x2463f10; 1 drivers -v0x2457d70_0 .net "out1", 0 0, L_0x2464000; 1 drivers -v0x2457e50_0 .net "outfinal", 0 0, L_0x24640a0; 1 drivers -S_0x24545e0 .scope module, "trial1" "AndNand32" 2 147, 3 154, S_0x23b34d0; - .timescale -9 -12; -P_0x2453fd8 .param/l "size" 3 161, +C4<0100>; -v0x24574a0_0 .alias "A", 3 0, v0x245d340_0; -v0x2457520_0 .alias "AndNandOut", 3 0, v0x245e770_0; -v0x24575a0_0 .alias "B", 3 0, v0x245d460_0; -v0x2457620_0 .alias "Command", 2 0, v0x245d560_0; -L_0x2467c20 .part/pv L_0x24679b0, 1, 1, 4; -L_0x2467d70 .part v0x245e5f0_0, 1, 1; -L_0x2467e10 .part v0x245e7f0_0, 1, 1; -L_0x24686d0 .part/pv L_0x2468460, 2, 1, 4; -L_0x2468770 .part v0x245e5f0_0, 2, 1; -L_0x2468810 .part v0x245e7f0_0, 2, 1; -L_0x2469140 .part/pv L_0x2468ed0, 3, 1, 4; -L_0x24691e0 .part v0x245e5f0_0, 3, 1; -L_0x24692d0 .part v0x245e7f0_0, 3, 1; -L_0x2469ba0 .part/pv L_0x2469930, 0, 1, 4; -L_0x2469ca0 .part v0x245e5f0_0, 0, 1; -L_0x2469d40 .part v0x245e7f0_0, 0, 1; -S_0x2456a70 .scope module, "attempt2" "AndNand" 3 165, 3 48, S_0x24545e0; - .timescale -9 -12; -L_0x24693c0/d .functor NAND 1, L_0x2469ca0, L_0x2469d40, C4<1>, C4<1>; -L_0x24693c0 .delay (10000,10000,10000) L_0x24693c0/d; -L_0x24694e0/d .functor NOT 1, L_0x24693c0, C4<0>, C4<0>, C4<0>; -L_0x24694e0 .delay (10000,10000,10000) L_0x24694e0/d; -v0x2457090_0 .net "A", 0 0, L_0x2469ca0; 1 drivers -v0x2457150_0 .net "AandB", 0 0, L_0x24694e0; 1 drivers -v0x24571d0_0 .net "AnandB", 0 0, L_0x24693c0; 1 drivers -v0x2457280_0 .net "AndNandOut", 0 0, L_0x2469930; 1 drivers -v0x2457360_0 .net "B", 0 0, L_0x2469d40; 1 drivers -v0x24573e0_0 .alias "Command", 2 0, v0x245d560_0; -L_0x2469b00 .part v0x245e870_0, 0, 1; -S_0x2456b60 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0x2456a70; - .timescale -9 -12; -L_0x2469610/d .functor NOT 1, L_0x2469b00, C4<0>, C4<0>, C4<0>; -L_0x2469610 .delay (10000,10000,10000) L_0x2469610/d; -L_0x24696d0/d .functor AND 1, L_0x24694e0, L_0x2469610, C4<1>, C4<1>; -L_0x24696d0 .delay (20000,20000,20000) L_0x24696d0/d; -L_0x24697e0/d .functor AND 1, L_0x24693c0, L_0x2469b00, C4<1>, C4<1>; -L_0x24697e0 .delay (20000,20000,20000) L_0x24697e0/d; -L_0x2469930/d .functor OR 1, L_0x24696d0, L_0x24697e0, C4<0>, C4<0>; -L_0x2469930 .delay (20000,20000,20000) L_0x2469930/d; -v0x2456c50_0 .net "S", 0 0, L_0x2469b00; 1 drivers -v0x2456cd0_0 .alias "in0", 0 0, v0x2457150_0; -v0x2456d50_0 .alias "in1", 0 0, v0x24571d0_0; -v0x2456df0_0 .net "nS", 0 0, L_0x2469610; 1 drivers -v0x2456e70_0 .net "out0", 0 0, L_0x24696d0; 1 drivers -v0x2456f10_0 .net "out1", 0 0, L_0x24697e0; 1 drivers -v0x2456ff0_0 .alias "outfinal", 0 0, v0x2457280_0; -S_0x2455eb0 .scope generate, "andbits[1]" "andbits[1]" 3 169, 3 169, S_0x24545e0; - .timescale -9 -12; -P_0x2455fa8 .param/l "i" 3 169, +C4<01>; -S_0x2456020 .scope module, "attempt" "AndNand" 3 171, 3 48, S_0x2455eb0; - .timescale -9 -12; -L_0x2467450/d .functor NAND 1, L_0x2467d70, L_0x2467e10, C4<1>, C4<1>; -L_0x2467450 .delay (10000,10000,10000) L_0x2467450/d; -L_0x2467560/d .functor NOT 1, L_0x2467450, C4<0>, C4<0>, C4<0>; -L_0x2467560 .delay (10000,10000,10000) L_0x2467560/d; -v0x2456660_0 .net "A", 0 0, L_0x2467d70; 1 drivers -v0x2456720_0 .net "AandB", 0 0, L_0x2467560; 1 drivers -v0x24567a0_0 .net "AnandB", 0 0, L_0x2467450; 1 drivers -v0x2456850_0 .net "AndNandOut", 0 0, L_0x24679b0; 1 drivers -v0x2456930_0 .net "B", 0 0, L_0x2467e10; 1 drivers -v0x24569b0_0 .alias "Command", 2 0, v0x245d560_0; -L_0x2467b80 .part v0x245e870_0, 0, 1; -S_0x2456110 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0x2456020; - .timescale -9 -12; -L_0x2467690/d .functor NOT 1, L_0x2467b80, C4<0>, C4<0>, C4<0>; -L_0x2467690 .delay (10000,10000,10000) L_0x2467690/d; -L_0x2467750/d .functor AND 1, L_0x2467560, L_0x2467690, C4<1>, C4<1>; -L_0x2467750 .delay (20000,20000,20000) L_0x2467750/d; -L_0x2467860/d .functor AND 1, L_0x2467450, L_0x2467b80, C4<1>, C4<1>; -L_0x2467860 .delay (20000,20000,20000) L_0x2467860/d; -L_0x24679b0/d .functor OR 1, L_0x2467750, L_0x2467860, C4<0>, C4<0>; -L_0x24679b0 .delay (20000,20000,20000) L_0x24679b0/d; -v0x2456200_0 .net "S", 0 0, L_0x2467b80; 1 drivers -v0x2456280_0 .alias "in0", 0 0, v0x2456720_0; -v0x2456320_0 .alias "in1", 0 0, v0x24567a0_0; -v0x24563c0_0 .net "nS", 0 0, L_0x2467690; 1 drivers -v0x2456440_0 .net "out0", 0 0, L_0x2467750; 1 drivers -v0x24564e0_0 .net "out1", 0 0, L_0x2467860; 1 drivers -v0x24565c0_0 .alias "outfinal", 0 0, v0x2456850_0; -S_0x24552f0 .scope generate, "andbits[2]" "andbits[2]" 3 169, 3 169, S_0x24545e0; - .timescale -9 -12; -P_0x24553e8 .param/l "i" 3 169, +C4<010>; -S_0x2455460 .scope module, "attempt" "AndNand" 3 171, 3 48, S_0x24552f0; - .timescale -9 -12; -L_0x2467eb0/d .functor NAND 1, L_0x2468770, L_0x2468810, C4<1>, C4<1>; -L_0x2467eb0 .delay (10000,10000,10000) L_0x2467eb0/d; -L_0x2468010/d .functor NOT 1, L_0x2467eb0, C4<0>, C4<0>, C4<0>; -L_0x2468010 .delay (10000,10000,10000) L_0x2468010/d; -v0x2455aa0_0 .net "A", 0 0, L_0x2468770; 1 drivers -v0x2455b60_0 .net "AandB", 0 0, L_0x2468010; 1 drivers -v0x2455be0_0 .net "AnandB", 0 0, L_0x2467eb0; 1 drivers -v0x2455c90_0 .net "AndNandOut", 0 0, L_0x2468460; 1 drivers -v0x2455d70_0 .net "B", 0 0, L_0x2468810; 1 drivers -v0x2455df0_0 .alias "Command", 2 0, v0x245d560_0; -L_0x2468630 .part v0x245e870_0, 0, 1; -S_0x2455550 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0x2455460; - .timescale -9 -12; -L_0x2468140/d .functor NOT 1, L_0x2468630, C4<0>, C4<0>, C4<0>; -L_0x2468140 .delay (10000,10000,10000) L_0x2468140/d; -L_0x2468200/d .functor AND 1, L_0x2468010, L_0x2468140, C4<1>, C4<1>; -L_0x2468200 .delay (20000,20000,20000) L_0x2468200/d; -L_0x2468310/d .functor AND 1, L_0x2467eb0, L_0x2468630, C4<1>, C4<1>; -L_0x2468310 .delay (20000,20000,20000) L_0x2468310/d; -L_0x2468460/d .functor OR 1, L_0x2468200, L_0x2468310, C4<0>, C4<0>; -L_0x2468460 .delay (20000,20000,20000) L_0x2468460/d; -v0x2455640_0 .net "S", 0 0, L_0x2468630; 1 drivers -v0x24556c0_0 .alias "in0", 0 0, v0x2455b60_0; -v0x2455760_0 .alias "in1", 0 0, v0x2455be0_0; -v0x2455800_0 .net "nS", 0 0, L_0x2468140; 1 drivers -v0x2455880_0 .net "out0", 0 0, L_0x2468200; 1 drivers -v0x2455920_0 .net "out1", 0 0, L_0x2468310; 1 drivers -v0x2455a00_0 .alias "outfinal", 0 0, v0x2455c90_0; -S_0x2454710 .scope generate, "andbits[3]" "andbits[3]" 3 169, 3 169, S_0x24545e0; - .timescale -9 -12; -P_0x2454808 .param/l "i" 3 169, +C4<011>; -S_0x2454880 .scope module, "attempt" "AndNand" 3 171, 3 48, S_0x2454710; - .timescale -9 -12; -L_0x2468940/d .functor NAND 1, L_0x24691e0, L_0x24692d0, C4<1>, C4<1>; -L_0x2468940 .delay (10000,10000,10000) L_0x2468940/d; -L_0x2468a80/d .functor NOT 1, L_0x2468940, C4<0>, C4<0>, C4<0>; -L_0x2468a80 .delay (10000,10000,10000) L_0x2468a80/d; -v0x2454ee0_0 .net "A", 0 0, L_0x24691e0; 1 drivers -v0x2454fa0_0 .net "AandB", 0 0, L_0x2468a80; 1 drivers -v0x2455020_0 .net "AnandB", 0 0, L_0x2468940; 1 drivers -v0x24550d0_0 .net "AndNandOut", 0 0, L_0x2468ed0; 1 drivers -v0x24551b0_0 .net "B", 0 0, L_0x24692d0; 1 drivers -v0x2455230_0 .alias "Command", 2 0, v0x245d560_0; -L_0x24690a0 .part v0x245e870_0, 0, 1; -S_0x2454970 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0x2454880; - .timescale -9 -12; -L_0x2468bb0/d .functor NOT 1, L_0x24690a0, C4<0>, C4<0>, C4<0>; -L_0x2468bb0 .delay (10000,10000,10000) L_0x2468bb0/d; -L_0x2468c70/d .functor AND 1, L_0x2468a80, L_0x2468bb0, C4<1>, C4<1>; -L_0x2468c70 .delay (20000,20000,20000) L_0x2468c70/d; -L_0x2468d80/d .functor AND 1, L_0x2468940, L_0x24690a0, C4<1>, C4<1>; -L_0x2468d80 .delay (20000,20000,20000) L_0x2468d80/d; -L_0x2468ed0/d .functor OR 1, L_0x2468c70, L_0x2468d80, C4<0>, C4<0>; -L_0x2468ed0 .delay (20000,20000,20000) L_0x2468ed0/d; -v0x2454a60_0 .net "S", 0 0, L_0x24690a0; 1 drivers -v0x2454b00_0 .alias "in0", 0 0, v0x2454fa0_0; -v0x2454ba0_0 .alias "in1", 0 0, v0x2455020_0; -v0x2454c40_0 .net "nS", 0 0, L_0x2468bb0; 1 drivers -v0x2454cc0_0 .net "out0", 0 0, L_0x2468c70; 1 drivers -v0x2454d60_0 .net "out1", 0 0, L_0x2468d80; 1 drivers -v0x2454e40_0 .alias "outfinal", 0 0, v0x24550d0_0; -S_0x244f3e0 .scope module, "trial2" "OrNorXor32" 2 149, 3 177, S_0x23b34d0; - .timescale -9 -12; -P_0x244cb98 .param/l "size" 3 184, +C4<0100>; -v0x24542c0_0 .alias "A", 3 0, v0x245d340_0; -v0x24543d0_0 .alias "B", 3 0, v0x245d460_0; -v0x24544e0_0 .alias "Command", 2 0, v0x245d560_0; -v0x2454560_0 .alias "OrNorXorOut", 3 0, v0x245e970_0; -L_0x246aef0 .part/pv L_0x246ac80, 1, 1, 4; -L_0x246b020 .part v0x245e5f0_0, 1, 1; -L_0x24601f0 .part v0x245e7f0_0, 1, 1; -L_0x246c450 .part/pv L_0x246c1e0, 2, 1, 4; -L_0x246c4f0 .part v0x245e5f0_0, 2, 1; -L_0x246c590 .part v0x245e7f0_0, 2, 1; -L_0x246d750 .part/pv L_0x246d4e0, 3, 1, 4; -L_0x246d7f0 .part v0x245e5f0_0, 3, 1; -L_0x246d890 .part v0x245e7f0_0, 3, 1; -L_0x246ea40 .part/pv L_0x246e7d0, 0, 1, 4; -L_0x246eb40 .part v0x245e5f0_0, 0, 1; -L_0x246ebe0 .part v0x245e7f0_0, 0, 1; -S_0x2453080 .scope module, "attempt2" "OrNorXor" 3 192, 3 64, S_0x244f3e0; - .timescale -9 -12; -L_0x246d930/d .functor NOR 1, L_0x246eb40, L_0x246ebe0, C4<0>, C4<0>; -L_0x246d930 .delay (10000,10000,10000) L_0x246d930/d; -L_0x246da30/d .functor NOT 1, L_0x246d930, C4<0>, C4<0>, C4<0>; -L_0x246da30 .delay (10000,10000,10000) L_0x246da30/d; -L_0x246db60/d .functor NAND 1, L_0x246eb40, L_0x246ebe0, C4<1>, C4<1>; -L_0x246db60 .delay (10000,10000,10000) L_0x246db60/d; -L_0x246dcc0/d .functor NAND 1, L_0x246db60, L_0x246da30, C4<1>, C4<1>; -L_0x246dcc0 .delay (10000,10000,10000) L_0x246dcc0/d; -L_0x246ddd0/d .functor NOT 1, L_0x246dcc0, C4<0>, C4<0>, C4<0>; -L_0x246ddd0 .delay (10000,10000,10000) L_0x246ddd0/d; -v0x2453bd0_0 .net "A", 0 0, L_0x246eb40; 1 drivers -v0x2453c70_0 .net "AnandB", 0 0, L_0x246db60; 1 drivers -v0x2453d10_0 .net "AnorB", 0 0, L_0x246d930; 1 drivers -v0x2453dc0_0 .net "AorB", 0 0, L_0x246da30; 1 drivers -v0x2453ea0_0 .net "AxorB", 0 0, L_0x246ddd0; 1 drivers -v0x2453f50_0 .net "B", 0 0, L_0x246ebe0; 1 drivers -v0x2454010_0 .alias "Command", 2 0, v0x245d560_0; -v0x2454090_0 .net "OrNorXorOut", 0 0, L_0x246e7d0; 1 drivers -v0x2454110_0 .net "XorNor", 0 0, L_0x246e250; 1 drivers -v0x24541e0_0 .net "nXor", 0 0, L_0x246dcc0; 1 drivers -L_0x246e3d0 .part v0x245e870_0, 2, 1; -L_0x246e9a0 .part v0x245e870_0, 0, 1; -S_0x2453660 .scope module, "mux0" "TwoInMux" 3 83, 3 8, S_0x2453080; - .timescale -9 -12; -L_0x246df30/d .functor NOT 1, L_0x246e3d0, C4<0>, C4<0>, C4<0>; -L_0x246df30 .delay (10000,10000,10000) L_0x246df30/d; -L_0x246dff0/d .functor AND 1, L_0x246ddd0, L_0x246df30, C4<1>, C4<1>; -L_0x246dff0 .delay (20000,20000,20000) L_0x246dff0/d; -L_0x246e100/d .functor AND 1, L_0x246d930, L_0x246e3d0, C4<1>, C4<1>; -L_0x246e100 .delay (20000,20000,20000) L_0x246e100/d; -L_0x246e250/d .functor OR 1, L_0x246dff0, L_0x246e100, C4<0>, C4<0>; -L_0x246e250 .delay (20000,20000,20000) L_0x246e250/d; -v0x2453750_0 .net "S", 0 0, L_0x246e3d0; 1 drivers -v0x2453810_0 .alias "in0", 0 0, v0x2453ea0_0; -v0x24538b0_0 .alias "in1", 0 0, v0x2453d10_0; -v0x2453950_0 .net "nS", 0 0, L_0x246df30; 1 drivers -v0x24539d0_0 .net "out0", 0 0, L_0x246dff0; 1 drivers -v0x2453a70_0 .net "out1", 0 0, L_0x246e100; 1 drivers -v0x2453b50_0 .alias "outfinal", 0 0, v0x2454110_0; -S_0x2453170 .scope module, "mux1" "TwoInMux" 3 84, 3 8, S_0x2453080; - .timescale -9 -12; -L_0x246e470/d .functor NOT 1, L_0x246e9a0, C4<0>, C4<0>, C4<0>; -L_0x246e470 .delay (10000,10000,10000) L_0x246e470/d; -L_0x246e530/d .functor AND 1, L_0x246e250, L_0x246e470, C4<1>, C4<1>; -L_0x246e530 .delay (20000,20000,20000) L_0x246e530/d; -L_0x246e680/d .functor AND 1, L_0x246da30, L_0x246e9a0, C4<1>, C4<1>; -L_0x246e680 .delay (20000,20000,20000) L_0x246e680/d; -L_0x246e7d0/d .functor OR 1, L_0x246e530, L_0x246e680, C4<0>, C4<0>; -L_0x246e7d0 .delay (20000,20000,20000) L_0x246e7d0/d; -v0x2453260_0 .net "S", 0 0, L_0x246e9a0; 1 drivers -v0x24532e0_0 .alias "in0", 0 0, v0x2454110_0; -v0x2453360_0 .alias "in1", 0 0, v0x2453dc0_0; -v0x2453400_0 .net "nS", 0 0, L_0x246e470; 1 drivers -v0x2453480_0 .net "out0", 0 0, L_0x246e530; 1 drivers -v0x2453520_0 .net "out1", 0 0, L_0x246e680; 1 drivers -v0x24535c0_0 .alias "outfinal", 0 0, v0x2454090_0; -S_0x2451cb0 .scope generate, "orbits[1]" "orbits[1]" 3 196, 3 196, S_0x244f3e0; - .timescale -9 -12; -P_0x24519c8 .param/l "i" 3 196, +C4<01>; -S_0x2451de0 .scope module, "attempt" "OrNorXor" 3 198, 3 64, S_0x2451cb0; - .timescale -9 -12; -L_0x2469c40/d .functor NOR 1, L_0x246b020, L_0x24601f0, C4<0>, C4<0>; -L_0x2469c40 .delay (10000,10000,10000) L_0x2469c40/d; -L_0x2469ee0/d .functor NOT 1, L_0x2469c40, C4<0>, C4<0>, C4<0>; -L_0x2469ee0 .delay (10000,10000,10000) L_0x2469ee0/d; -L_0x246a010/d .functor NAND 1, L_0x246b020, L_0x24601f0, C4<1>, C4<1>; -L_0x246a010 .delay (10000,10000,10000) L_0x246a010/d; -L_0x246a170/d .functor NAND 1, L_0x246a010, L_0x2469ee0, C4<1>, C4<1>; -L_0x246a170 .delay (10000,10000,10000) L_0x246a170/d; -L_0x246a280/d .functor NOT 1, L_0x246a170, C4<0>, C4<0>, C4<0>; -L_0x246a280 .delay (10000,10000,10000) L_0x246a280/d; -v0x2452990_0 .net "A", 0 0, L_0x246b020; 1 drivers -v0x2452a30_0 .net "AnandB", 0 0, L_0x246a010; 1 drivers -v0x2452ad0_0 .net "AnorB", 0 0, L_0x2469c40; 1 drivers -v0x2452b80_0 .net "AorB", 0 0, L_0x2469ee0; 1 drivers -v0x2452c60_0 .net "AxorB", 0 0, L_0x246a280; 1 drivers -v0x2452d10_0 .net "B", 0 0, L_0x24601f0; 1 drivers -v0x2452dd0_0 .alias "Command", 2 0, v0x245d560_0; -v0x2452e50_0 .net "OrNorXorOut", 0 0, L_0x246ac80; 1 drivers -v0x2452ed0_0 .net "XorNor", 0 0, L_0x246a700; 1 drivers -v0x2452fa0_0 .net "nXor", 0 0, L_0x246a170; 1 drivers -L_0x246a880 .part v0x245e870_0, 2, 1; -L_0x246ae50 .part v0x245e870_0, 0, 1; -S_0x2452420 .scope module, "mux0" "TwoInMux" 3 83, 3 8, S_0x2451de0; - .timescale -9 -12; -L_0x246a3e0/d .functor NOT 1, L_0x246a880, C4<0>, C4<0>, C4<0>; -L_0x246a3e0 .delay (10000,10000,10000) L_0x246a3e0/d; -L_0x246a4a0/d .functor AND 1, L_0x246a280, L_0x246a3e0, C4<1>, C4<1>; -L_0x246a4a0 .delay (20000,20000,20000) L_0x246a4a0/d; -L_0x246a5b0/d .functor AND 1, L_0x2469c40, L_0x246a880, C4<1>, C4<1>; -L_0x246a5b0 .delay (20000,20000,20000) L_0x246a5b0/d; -L_0x246a700/d .functor OR 1, L_0x246a4a0, L_0x246a5b0, C4<0>, C4<0>; -L_0x246a700 .delay (20000,20000,20000) L_0x246a700/d; -v0x2452510_0 .net "S", 0 0, L_0x246a880; 1 drivers -v0x24525d0_0 .alias "in0", 0 0, v0x2452c60_0; -v0x2452670_0 .alias "in1", 0 0, v0x2452ad0_0; -v0x2452710_0 .net "nS", 0 0, L_0x246a3e0; 1 drivers -v0x2452790_0 .net "out0", 0 0, L_0x246a4a0; 1 drivers -v0x2452830_0 .net "out1", 0 0, L_0x246a5b0; 1 drivers -v0x2452910_0 .alias "outfinal", 0 0, v0x2452ed0_0; -S_0x2451ed0 .scope module, "mux1" "TwoInMux" 3 84, 3 8, S_0x2451de0; - .timescale -9 -12; -L_0x246a920/d .functor NOT 1, L_0x246ae50, C4<0>, C4<0>, C4<0>; -L_0x246a920 .delay (10000,10000,10000) L_0x246a920/d; -L_0x246a9e0/d .functor AND 1, L_0x246a700, L_0x246a920, C4<1>, C4<1>; -L_0x246a9e0 .delay (20000,20000,20000) L_0x246a9e0/d; -L_0x246ab30/d .functor AND 1, L_0x2469ee0, L_0x246ae50, C4<1>, C4<1>; -L_0x246ab30 .delay (20000,20000,20000) L_0x246ab30/d; -L_0x246ac80/d .functor OR 1, L_0x246a9e0, L_0x246ab30, C4<0>, C4<0>; -L_0x246ac80 .delay (20000,20000,20000) L_0x246ac80/d; -v0x2451fc0_0 .net "S", 0 0, L_0x246ae50; 1 drivers -v0x2452040_0 .alias "in0", 0 0, v0x2452ed0_0; -v0x24520e0_0 .alias "in1", 0 0, v0x2452b80_0; -v0x2452180_0 .net "nS", 0 0, L_0x246a920; 1 drivers -v0x2452200_0 .net "out0", 0 0, L_0x246a9e0; 1 drivers -v0x24522a0_0 .net "out1", 0 0, L_0x246ab30; 1 drivers -v0x2452380_0 .alias "outfinal", 0 0, v0x2452e50_0; -S_0x24508e0 .scope generate, "orbits[2]" "orbits[2]" 3 196, 3 196, S_0x244f3e0; - .timescale -9 -12; -P_0x2450598 .param/l "i" 3 196, +C4<010>; -S_0x2450a10 .scope module, "attempt" "OrNorXor" 3 198, 3 64, S_0x24508e0; - .timescale -9 -12; -L_0x2460290/d .functor NOR 1, L_0x246c4f0, L_0x246c590, C4<0>, C4<0>; -L_0x2460290 .delay (10000,10000,10000) L_0x2460290/d; -L_0x2460400/d .functor NOT 1, L_0x2460290, C4<0>, C4<0>, C4<0>; -L_0x2460400 .delay (10000,10000,10000) L_0x2460400/d; -L_0x246b570/d .functor NAND 1, L_0x246c4f0, L_0x246c590, C4<1>, C4<1>; -L_0x246b570 .delay (10000,10000,10000) L_0x246b570/d; -L_0x246b6d0/d .functor NAND 1, L_0x246b570, L_0x2460400, C4<1>, C4<1>; -L_0x246b6d0 .delay (10000,10000,10000) L_0x246b6d0/d; -L_0x246b7e0/d .functor NOT 1, L_0x246b6d0, C4<0>, C4<0>, C4<0>; -L_0x246b7e0 .delay (10000,10000,10000) L_0x246b7e0/d; -v0x24515c0_0 .net "A", 0 0, L_0x246c4f0; 1 drivers -v0x2451660_0 .net "AnandB", 0 0, L_0x246b570; 1 drivers -v0x2451700_0 .net "AnorB", 0 0, L_0x2460290; 1 drivers -v0x24517b0_0 .net "AorB", 0 0, L_0x2460400; 1 drivers -v0x2451890_0 .net "AxorB", 0 0, L_0x246b7e0; 1 drivers -v0x2451940_0 .net "B", 0 0, L_0x246c590; 1 drivers -v0x2451a00_0 .alias "Command", 2 0, v0x245d560_0; -v0x2451a80_0 .net "OrNorXorOut", 0 0, L_0x246c1e0; 1 drivers -v0x2451b00_0 .net "XorNor", 0 0, L_0x246bc60; 1 drivers -v0x2451bd0_0 .net "nXor", 0 0, L_0x246b6d0; 1 drivers -L_0x246bde0 .part v0x245e870_0, 2, 1; -L_0x246c3b0 .part v0x245e870_0, 0, 1; -S_0x2451050 .scope module, "mux0" "TwoInMux" 3 83, 3 8, S_0x2450a10; - .timescale -9 -12; -L_0x246b940/d .functor NOT 1, L_0x246bde0, C4<0>, C4<0>, C4<0>; -L_0x246b940 .delay (10000,10000,10000) L_0x246b940/d; -L_0x246ba00/d .functor AND 1, L_0x246b7e0, L_0x246b940, C4<1>, C4<1>; -L_0x246ba00 .delay (20000,20000,20000) L_0x246ba00/d; -L_0x246bb10/d .functor AND 1, L_0x2460290, L_0x246bde0, C4<1>, C4<1>; -L_0x246bb10 .delay (20000,20000,20000) L_0x246bb10/d; -L_0x246bc60/d .functor OR 1, L_0x246ba00, L_0x246bb10, C4<0>, C4<0>; -L_0x246bc60 .delay (20000,20000,20000) L_0x246bc60/d; -v0x2451140_0 .net "S", 0 0, L_0x246bde0; 1 drivers -v0x2451200_0 .alias "in0", 0 0, v0x2451890_0; -v0x24512a0_0 .alias "in1", 0 0, v0x2451700_0; -v0x2451340_0 .net "nS", 0 0, L_0x246b940; 1 drivers -v0x24513c0_0 .net "out0", 0 0, L_0x246ba00; 1 drivers -v0x2451460_0 .net "out1", 0 0, L_0x246bb10; 1 drivers -v0x2451540_0 .alias "outfinal", 0 0, v0x2451b00_0; -S_0x2450b00 .scope module, "mux1" "TwoInMux" 3 84, 3 8, S_0x2450a10; - .timescale -9 -12; -L_0x246be80/d .functor NOT 1, L_0x246c3b0, C4<0>, C4<0>, C4<0>; -L_0x246be80 .delay (10000,10000,10000) L_0x246be80/d; -L_0x246bf40/d .functor AND 1, L_0x246bc60, L_0x246be80, C4<1>, C4<1>; -L_0x246bf40 .delay (20000,20000,20000) L_0x246bf40/d; -L_0x246c090/d .functor AND 1, L_0x2460400, L_0x246c3b0, C4<1>, C4<1>; -L_0x246c090 .delay (20000,20000,20000) L_0x246c090/d; -L_0x246c1e0/d .functor OR 1, L_0x246bf40, L_0x246c090, C4<0>, C4<0>; -L_0x246c1e0 .delay (20000,20000,20000) L_0x246c1e0/d; -v0x2450bf0_0 .net "S", 0 0, L_0x246c3b0; 1 drivers -v0x2450c70_0 .alias "in0", 0 0, v0x2451b00_0; -v0x2450d10_0 .alias "in1", 0 0, v0x24517b0_0; -v0x2450db0_0 .net "nS", 0 0, L_0x246be80; 1 drivers -v0x2450e30_0 .net "out0", 0 0, L_0x246bf40; 1 drivers -v0x2450ed0_0 .net "out1", 0 0, L_0x246c090; 1 drivers -v0x2450fb0_0 .alias "outfinal", 0 0, v0x2451a80_0; -S_0x244f4d0 .scope generate, "orbits[3]" "orbits[3]" 3 196, 3 196, S_0x244f3e0; - .timescale -9 -12; -P_0x244f218 .param/l "i" 3 196, +C4<011>; -S_0x244f5c0 .scope module, "attempt" "OrNorXor" 3 198, 3 64, S_0x244f4d0; - .timescale -9 -12; -L_0x246c670/d .functor NOR 1, L_0x246d7f0, L_0x246d890, C4<0>, C4<0>; -L_0x246c670 .delay (10000,10000,10000) L_0x246c670/d; -L_0x246c760/d .functor NOT 1, L_0x246c670, C4<0>, C4<0>, C4<0>; -L_0x246c760 .delay (10000,10000,10000) L_0x246c760/d; -L_0x246c870/d .functor NAND 1, L_0x246d7f0, L_0x246d890, C4<1>, C4<1>; -L_0x246c870 .delay (10000,10000,10000) L_0x246c870/d; -L_0x246c9d0/d .functor NAND 1, L_0x246c870, L_0x246c760, C4<1>, C4<1>; -L_0x246c9d0 .delay (10000,10000,10000) L_0x246c9d0/d; -L_0x246cae0/d .functor NOT 1, L_0x246c9d0, C4<0>, C4<0>, C4<0>; -L_0x246cae0 .delay (10000,10000,10000) L_0x246cae0/d; -v0x2450190_0 .net "A", 0 0, L_0x246d7f0; 1 drivers -v0x2450230_0 .net "AnandB", 0 0, L_0x246c870; 1 drivers -v0x24502d0_0 .net "AnorB", 0 0, L_0x246c670; 1 drivers -v0x2450380_0 .net "AorB", 0 0, L_0x246c760; 1 drivers -v0x2450460_0 .net "AxorB", 0 0, L_0x246cae0; 1 drivers -v0x2450510_0 .net "B", 0 0, L_0x246d890; 1 drivers -v0x24505d0_0 .alias "Command", 2 0, v0x245d560_0; -v0x24471c0_0 .net "OrNorXorOut", 0 0, L_0x246d4e0; 1 drivers -v0x2447240_0 .net "XorNor", 0 0, L_0x246cf60; 1 drivers -v0x2450860_0 .net "nXor", 0 0, L_0x246c9d0; 1 drivers -L_0x246d0e0 .part v0x245e870_0, 2, 1; -L_0x246d6b0 .part v0x245e870_0, 0, 1; -S_0x244fc20 .scope module, "mux0" "TwoInMux" 3 83, 3 8, S_0x244f5c0; - .timescale -9 -12; -L_0x246cc40/d .functor NOT 1, L_0x246d0e0, C4<0>, C4<0>, C4<0>; -L_0x246cc40 .delay (10000,10000,10000) L_0x246cc40/d; -L_0x246cd00/d .functor AND 1, L_0x246cae0, L_0x246cc40, C4<1>, C4<1>; -L_0x246cd00 .delay (20000,20000,20000) L_0x246cd00/d; -L_0x246ce10/d .functor AND 1, L_0x246c670, L_0x246d0e0, C4<1>, C4<1>; -L_0x246ce10 .delay (20000,20000,20000) L_0x246ce10/d; -L_0x246cf60/d .functor OR 1, L_0x246cd00, L_0x246ce10, C4<0>, C4<0>; -L_0x246cf60 .delay (20000,20000,20000) L_0x246cf60/d; -v0x244fd10_0 .net "S", 0 0, L_0x246d0e0; 1 drivers -v0x244fdd0_0 .alias "in0", 0 0, v0x2450460_0; -v0x244fe70_0 .alias "in1", 0 0, v0x24502d0_0; -v0x244ff10_0 .net "nS", 0 0, L_0x246cc40; 1 drivers -v0x244ff90_0 .net "out0", 0 0, L_0x246cd00; 1 drivers -v0x2450030_0 .net "out1", 0 0, L_0x246ce10; 1 drivers -v0x2450110_0 .alias "outfinal", 0 0, v0x2447240_0; -S_0x244f6b0 .scope module, "mux1" "TwoInMux" 3 84, 3 8, S_0x244f5c0; - .timescale -9 -12; -L_0x246d180/d .functor NOT 1, L_0x246d6b0, C4<0>, C4<0>, C4<0>; -L_0x246d180 .delay (10000,10000,10000) L_0x246d180/d; -L_0x246d240/d .functor AND 1, L_0x246cf60, L_0x246d180, C4<1>, C4<1>; -L_0x246d240 .delay (20000,20000,20000) L_0x246d240/d; -L_0x246d390/d .functor AND 1, L_0x246c760, L_0x246d6b0, C4<1>, C4<1>; -L_0x246d390 .delay (20000,20000,20000) L_0x246d390/d; -L_0x246d4e0/d .functor OR 1, L_0x246d240, L_0x246d390, C4<0>, C4<0>; -L_0x246d4e0 .delay (20000,20000,20000) L_0x246d4e0/d; -v0x244f7a0_0 .net "S", 0 0, L_0x246d6b0; 1 drivers -v0x244f840_0 .alias "in0", 0 0, v0x2447240_0; -v0x244f8e0_0 .alias "in1", 0 0, v0x2450380_0; -v0x244f980_0 .net "nS", 0 0, L_0x246d180; 1 drivers -v0x244fa00_0 .net "out0", 0 0, L_0x246d240; 1 drivers -v0x244faa0_0 .net "out1", 0 0, L_0x246d390; 1 drivers -v0x244fb80_0 .alias "outfinal", 0 0, v0x24471c0_0; -S_0x23d85b0 .scope module, "superalu" "Bitslice32" 2 151, 3 286, S_0x23b34d0; - .timescale -9 -12; -P_0x23b1ea8 .param/l "size" 3 303, +C4<0100>; -L_0x2473c50/d .functor AND 1, L_0x2488450, L_0x2488630, C4<1>, C4<1>; -L_0x2473c50 .delay (20000,20000,20000) L_0x2473c50/d; -L_0x2488720/d .functor NOT 1, L_0x24887d0, C4<0>, C4<0>, C4<0>; -L_0x2488720 .delay (10000,10000,10000) L_0x2488720/d; -L_0x2488c80/d .functor AND 1, L_0x2488720, L_0x2488720, C4<1>, C4<1>; -L_0x2488c80 .delay (20000,20000,20000) L_0x2488c80/d; -v0x244e420_0 .alias "A", 3 0, v0x245d340_0; -v0x244e4c0_0 .alias "AddSubSLTSum", 3 0, v0x245e670_0; -v0x244e540_0 .alias "AllZeros", 0 0, v0x245e6f0_0; -v0x244e5c0_0 .alias "AndNandOut", 3 0, v0x245e770_0; -v0x244e670_0 .alias "B", 3 0, v0x245d460_0; -RS_0x7f3880bf1518 .resolv tri, L_0x246f380, L_0x2471c60, L_0x24749e0, L_0x2486820; -v0x244e6f0_0 .net8 "Cmd0Start", 3 0, RS_0x7f3880bf1518; 4 drivers -RS_0x7f3880bf1548 .resolv tri, L_0x24701d0, L_0x2472ed0, L_0x24759d0, L_0x2487650; -v0x244e770_0 .net8 "Cmd1Start", 3 0, RS_0x7f3880bf1548; 4 drivers -v0x244e7f0_0 .alias "Command", 2 0, v0x245d560_0; -v0x244e870_0 .alias "OneBitFinalOut", 3 0, v0x245e8f0_0; -v0x244e910_0 .alias "OrNorXorOut", 3 0, v0x245e970_0; -v0x244e990_0 .alias "SLTflag", 0 0, v0x245ea40_0; -v0x244ea40_0 .alias "ZeroFlag", 3 0, v0x245eac0_0; -v0x244eac0_0 .net *"_s111", 0 0, L_0x2473c50; 1 drivers -v0x244eb40_0 .net *"_s114", 0 0, L_0x2488450; 1 drivers -v0x244ec60_0 .net *"_s116", 0 0, L_0x2488630; 1 drivers -v0x244ed00_0 .net *"_s118", 0 0, L_0x24887d0; 1 drivers -v0x244ebc0_0 .net *"_s21", 0 0, L_0x2471220; 1 drivers -v0x244ee50_0 .net *"_s46", 0 0, L_0x2473520; 1 drivers -v0x244ef70_0 .net *"_s71", 0 0, L_0x2476790; 1 drivers -v0x244eff0_0 .alias "carryin", 3 0, v0x245df60_0; -v0x244eed0_0 .alias "carryout", 0 0, v0x245ebc0_0; -v0x244f150_0 .alias "overflow", 0 0, v0x245ec40_0; -v0x244f070_0 .alias "subtract", 3 0, v0x245ecc0_0; -v0x244f290_0 .net "yeszero", 0 0, L_0x2488720; 1 drivers -L_0x246f380 .part/pv L_0x246f1a0, 1, 1, 4; -L_0x246f420 .part v0x245e870_0, 0, 1; -L_0x246f550 .part v0x245e870_0, 1, 1; -L_0x246f680 .part RS_0x7f3880bf1098, 1, 1; -L_0x246f720 .part RS_0x7f3880bf1098, 1, 1; -L_0x246f7c0 .part RS_0x7f3880bef748, 1, 1; -L_0x246f9c0 .part RS_0x7f3880bf1098, 1, 1; -L_0x24701d0 .part/pv L_0x246fff0, 1, 1, 4; -L_0x24702c0 .part v0x245e870_0, 0, 1; -L_0x24703f0 .part v0x245e870_0, 1, 1; -L_0x2470580 .part RS_0x7f3880befe38, 1, 1; -L_0x2470730 .part RS_0x7f3880befe38, 1, 1; -L_0x24707d0 .part RS_0x7f3880bef748, 1, 1; -L_0x2470870 .part RS_0x7f3880bef748, 1, 1; -L_0x2470cd0 .part/pv L_0x2470b90, 1, 1, 4; -L_0x2470dc0 .part v0x245e870_0, 2, 1; -L_0x2470e60 .part RS_0x7f3880bf1518, 1, 1; -L_0x2470fa0 .part RS_0x7f3880bf1548, 1, 1; -L_0x2471180 .part/pv L_0x2471220, 1, 1, 4; -L_0x2471320 .part RS_0x7f3880bf15a8, 0, 1; -L_0x24710e0 .part RS_0x7f3880bf1578, 1, 1; -L_0x2471c60 .part/pv L_0x2471a50, 2, 1, 4; -L_0x24713c0 .part v0x245e870_0, 0, 1; -L_0x245f370 .part v0x245e870_0, 1, 1; -L_0x2471d00 .part RS_0x7f3880bf1098, 2, 1; -L_0x245f570 .part RS_0x7f3880bf1098, 2, 1; -L_0x245f4a0 .part RS_0x7f3880bef748, 2, 1; -L_0x2472660 .part RS_0x7f3880bf1098, 2, 1; -L_0x2472ed0 .part/pv L_0x2472cc0, 2, 1, 4; -L_0x2472f70 .part v0x245e870_0, 0, 1; -L_0x2472700 .part v0x245e870_0, 1, 1; -L_0x2473230 .part RS_0x7f3880befe38, 2, 1; -L_0x24730a0 .part RS_0x7f3880befe38, 2, 1; -L_0x24733e0 .part RS_0x7f3880bef748, 2, 1; -L_0x24732d0 .part RS_0x7f3880bef748, 2, 1; -L_0x2473950 .part/pv L_0x2473810, 2, 1, 4; -L_0x2473480 .part v0x245e870_0, 2, 1; -L_0x2473bb0 .part RS_0x7f3880bf1518, 2, 1; -L_0x2473a80 .part RS_0x7f3880bf1548, 2, 1; -L_0x2473e20 .part/pv L_0x2473520, 2, 1, 4; -L_0x2473d20 .part RS_0x7f3880bf15a8, 1, 1; -L_0x24740a0 .part RS_0x7f3880bf1578, 2, 1; -L_0x24749e0 .part/pv L_0x24747d0, 3, 1, 4; -L_0x2474a80 .part v0x245e870_0, 0, 1; -L_0x2474140 .part v0x245e870_0, 1, 1; -L_0x2474d20 .part RS_0x7f3880bf1098, 3, 1; -L_0x2466c90 .part RS_0x7f3880bf1098, 3, 1; -L_0x2474bb0 .part RS_0x7f3880bef748, 3, 1; -L_0x2475160 .part RS_0x7f3880bf1098, 3, 1; -L_0x24759d0 .part/pv L_0x24757c0, 3, 1, 4; -L_0x2474fd0 .part v0x245e870_0, 0, 1; -L_0x2475c10 .part v0x245e870_0, 1, 1; -L_0x2475a70 .part RS_0x7f3880befe38, 3, 1; -L_0x2475b10 .part RS_0x7f3880befe38, 3, 1; -L_0x2475f00 .part RS_0x7f3880bef748, 3, 1; -L_0x2475fa0 .part RS_0x7f3880bef748, 3, 1; -L_0x24765b0 .part/pv L_0x2476470, 3, 1, 4; -L_0x2476650 .part v0x245e870_0, 2, 1; -L_0x2476250 .part RS_0x7f3880bf1518, 3, 1; -L_0x2476340 .part RS_0x7f3880bf1548, 3, 1; -L_0x24766f0 .part/pv L_0x2476790, 3, 1, 4; -L_0x2476b10 .part RS_0x7f3880bf15a8, 2, 1; -L_0x2476920 .part RS_0x7f3880bf1578, 3, 1; -L_0x2486820 .part/pv L_0x2486640, 0, 1, 4; -L_0x2476bb0 .part v0x245e870_0, 0, 1; -L_0x2476ce0 .part v0x245e870_0, 1, 1; -L_0x24868c0 .part RS_0x7f3880bf1098, 0, 1; -L_0x2486960 .part RS_0x7f3880bf1098, 0, 1; -L_0x2486a00 .part RS_0x7f3880bef748, 0, 1; -L_0x2486de0 .part RS_0x7f3880bf1098, 0, 1; -L_0x2487650 .part/pv L_0x2487470, 0, 1, 4; -L_0x24876f0 .part v0x245e870_0, 0, 1; -L_0x2486ed0 .part v0x245e870_0, 1, 1; -L_0x2487000 .part RS_0x7f3880befe38, 0, 1; -L_0x2487a80 .part RS_0x7f3880befe38, 0, 1; -L_0x2487b20 .part RS_0x7f3880bef748, 0, 1; -L_0x2487820 .part RS_0x7f3880bef748, 0, 1; -L_0x24880f0 .part/pv L_0x2487fb0, 0, 1, 4; -L_0x2487bc0 .part v0x245e870_0, 2, 1; -L_0x2487c60 .part RS_0x7f3880bf1518, 0, 1; -L_0x2487d50 .part RS_0x7f3880bf1548, 0, 1; -L_0x24883b0 .part/pv L_0x2473c50, 0, 1, 4; -L_0x2488450 .part RS_0x7f3880bf1578, 0, 1; -L_0x2488630 .part RS_0x7f3880bf1578, 0, 1; -L_0x24887d0 .part RS_0x7f3880bf15a8, 3, 1; -S_0x24474b0 .scope module, "trial" "AddSubSLT32" 3 311, 3 205, S_0x23d85b0; - .timescale -9 -12; -P_0x24475a8 .param/l "size" 3 242, +C4<0100>; -L_0x247bc90/d .functor NOT 1, L_0x247bd40, C4<0>, C4<0>, C4<0>; -L_0x247bc90 .delay (10000,10000,10000) L_0x247bc90/d; -L_0x247bde0/d .functor AND 1, L_0x247bf20, L_0x247bb70, L_0x247bc90, C4<1>; -L_0x247bde0 .delay (20000,20000,20000) L_0x247bde0/d; -L_0x247dbf0/d .functor OR 1, L_0x247dce0, C4<0>, C4<0>, C4<0>; -L_0x247dbf0 .delay (20000,20000,20000) L_0x247dbf0/d; -L_0x247da20/d .functor XOR 1, RS_0x7f3880bf13c8, L_0x247dfc0, C4<0>, C4<0>; -L_0x247da20 .delay (40000,40000,40000) L_0x247da20/d; -L_0x247e060/d .functor NOT 1, RS_0x7f3880bf1488, C4<0>, C4<0>, C4<0>; -L_0x247e060 .delay (10000,10000,10000) L_0x247e060/d; -L_0x247e1d0/d .functor NOT 1, L_0x247e2b0, C4<0>, C4<0>, C4<0>; -L_0x247e1d0 .delay (10000,10000,10000) L_0x247e1d0/d; -L_0x247de90/d .functor AND 1, L_0x247e060, L_0x247e4e0, C4<1>, C4<1>; -L_0x247de90 .delay (20000,20000,20000) L_0x247de90/d; -L_0x247e580/d .functor AND 1, RS_0x7f3880bf1488, L_0x247e1d0, C4<1>, C4<1>; -L_0x247e580 .delay (20000,20000,20000) L_0x247e580/d; -L_0x247e680/d .functor AND 1, L_0x247de90, L_0x247bde0, C4<1>, C4<1>; -L_0x247e680 .delay (20000,20000,20000) L_0x247e680/d; -L_0x247e780/d .functor AND 1, L_0x247e580, L_0x247bde0, C4<1>, C4<1>; -L_0x247e780 .delay (20000,20000,20000) L_0x247e780/d; -L_0x247e8f0/d .functor OR 1, L_0x247e680, L_0x247e780, C4<0>, C4<0>; -L_0x247e8f0 .delay (20000,20000,20000) L_0x247e8f0/d; -v0x244d180_0 .alias "A", 3 0, v0x245d340_0; -v0x244d220_0 .alias "AddSubSLTSum", 3 0, v0x245e670_0; -v0x244d2c0_0 .alias "B", 3 0, v0x245d460_0; -RS_0x7f3880bf10c8 .resolv tri, L_0x2477c40, L_0x24796e0, L_0x247b1e0, L_0x247bfc0; -v0x244d390_0 .net8 "CarryoutWire", 3 0, RS_0x7f3880bf10c8; 4 drivers -v0x244d410_0 .alias "Command", 2 0, v0x245d560_0; -RS_0x7f3880bf10f8 .resolv tri, L_0x2477b50, L_0x24795f0, L_0x247b0f0, L_0x247cff0; -v0x244d490_0 .net8 "NewVal", 3 0, RS_0x7f3880bf10f8; 4 drivers -v0x244d530_0 .net "Res0OF1", 0 0, L_0x247e580; 1 drivers -v0x244d5d0_0 .net "Res1OF0", 0 0, L_0x247de90; 1 drivers -v0x244d6c0_0 .alias "SLTflag", 0 0, v0x245ea40_0; -v0x244d760_0 .net "SLTflag0", 0 0, L_0x247e680; 1 drivers -v0x244d800_0 .net "SLTflag1", 0 0, L_0x247e780; 1 drivers -v0x244d8a0_0 .net "SLTon", 0 0, L_0x247bde0; 1 drivers -v0x244d9b0_0 .net *"_s37", 0 0, L_0x247bd40; 1 drivers -v0x244da50_0 .net *"_s39", 0 0, L_0x247bf20; 1 drivers -v0x244db70_0 .net *"_s41", 0 0, L_0x247bb70; 1 drivers -v0x244dc10_0 .net *"_s61", 0 0, L_0x247dce0; 1 drivers -v0x244dad0_0 .net/s *"_s62", 0 0, C4<0>; 1 drivers -v0x244dd60_0 .net *"_s65", 0 0, L_0x247dfc0; 1 drivers -v0x244de80_0 .net *"_s67", 0 0, L_0x247e2b0; 1 drivers -v0x244df00_0 .net *"_s69", 0 0, L_0x247e4e0; 1 drivers -v0x244dde0_0 .alias "carryin", 3 0, v0x245df60_0; -v0x244e030_0 .alias "carryout", 0 0, v0x245ebc0_0; -v0x244df80_0 .net "nAddSubSLTSum", 0 0, L_0x247e1d0; 1 drivers -v0x244e170_0 .net "nCmd2", 0 0, L_0x247bc90; 1 drivers -v0x244e0d0_0 .net "nOF", 0 0, L_0x247e060; 1 drivers -v0x244e2c0_0 .alias "overflow", 0 0, v0x245ec40_0; -v0x244e210_0 .alias "subtract", 3 0, v0x245ecc0_0; -L_0x2477b50 .part/pv L_0x24776c0, 1, 1, 4; -L_0x2477c40 .part/pv L_0x2477a10, 1, 1, 4; -L_0x2477d30 .part/pv L_0x24773f0, 1, 1, 4; -L_0x2477e20 .part v0x245e5f0_0, 1, 1; -L_0x2477ec0 .part v0x245e7f0_0, 1, 1; -L_0x2477ff0 .part RS_0x7f3880bf10c8, 0, 1; -L_0x2478450 .part/pv L_0x2478310, 1, 1, 4; -L_0x24784f0 .part RS_0x7f3880bf10f8, 1, 1; -L_0x24795f0 .part/pv L_0x2479160, 2, 1, 4; -L_0x24796e0 .part/pv L_0x24794b0, 2, 1, 4; -L_0x2479830 .part/pv L_0x2478e90, 2, 1, 4; -L_0x24798d0 .part v0x245e5f0_0, 2, 1; -L_0x24799e0 .part v0x245e7f0_0, 2, 1; -L_0x2479b10 .part RS_0x7f3880bf10c8, 1, 1; -L_0x2479fc0 .part/pv L_0x2479ed0, 2, 1, 4; -L_0x247a060 .part RS_0x7f3880bf10f8, 2, 1; -L_0x247b0f0 .part/pv L_0x247ad00, 3, 1, 4; -L_0x247b1e0 .part/pv L_0x2479c40, 3, 1, 4; -L_0x247b370 .part/pv L_0x247aa30, 3, 1, 4; -L_0x247b410 .part v0x245e5f0_0, 3, 1; -L_0x247b2d0 .part v0x245e7f0_0, 3, 1; -L_0x247b5f0 .part RS_0x7f3880bf10c8, 2, 1; -L_0x247b9e0 .part/pv L_0x247b8a0, 3, 1, 4; -L_0x247ba80 .part RS_0x7f3880bf10f8, 3, 1; -L_0x247bd40 .part v0x245e870_0, 2, 1; -L_0x247bf20 .part v0x245e870_0, 0, 1; -L_0x247bb70 .part v0x245e870_0, 1, 1; -L_0x247cff0 .part/pv L_0x247cb40, 0, 1, 4; -L_0x247bfc0 .part/pv L_0x247ce90, 0, 1, 4; -L_0x247d220 .part/pv L_0x247c870, 0, 1, 4; -L_0x247d0e0 .part v0x245e5f0_0, 0, 1; -L_0x247d410 .part v0x245e7f0_0, 0, 1; -L_0x247d310 .part RS_0x7f3880bf14b8, 0, 1; -L_0x247d920 .part/pv L_0x247d7e0, 0, 1, 4; -L_0x247d540 .part RS_0x7f3880bf10f8, 0, 1; -L_0x247dce0 .part RS_0x7f3880bf10c8, 3, 1; -L_0x247dfc0 .part RS_0x7f3880bf10c8, 2, 1; -L_0x247e2b0 .part RS_0x7f3880bf1098, 3, 1; -L_0x247e4e0 .part RS_0x7f3880bf1098, 3, 1; -S_0x244c160 .scope module, "attempt2" "MiddleAddSubSLT" 3 235, 3 89, S_0x24474b0; - .timescale -9 -12; -L_0x247c0f0/d .functor NOT 1, L_0x247d410, C4<0>, C4<0>, C4<0>; -L_0x247c0f0 .delay (10000,10000,10000) L_0x247c0f0/d; -L_0x247c730/d .functor NOT 1, L_0x247c7d0, C4<0>, C4<0>, C4<0>; -L_0x247c730 .delay (10000,10000,10000) L_0x247c730/d; -L_0x247c870/d .functor AND 1, L_0x247c9b0, L_0x247c730, C4<1>, C4<1>; -L_0x247c870 .delay (20000,20000,20000) L_0x247c870/d; -L_0x247ca50/d .functor XOR 1, L_0x247d0e0, L_0x247c500, C4<0>, C4<0>; -L_0x247ca50 .delay (40000,40000,40000) L_0x247ca50/d; -L_0x247cb40/d .functor XOR 1, L_0x247ca50, L_0x247d310, C4<0>, C4<0>; -L_0x247cb40 .delay (40000,40000,40000) L_0x247cb40/d; -L_0x247cc30/d .functor AND 1, L_0x247d0e0, L_0x247c500, C4<1>, C4<1>; -L_0x247cc30 .delay (20000,20000,20000) L_0x247cc30/d; -L_0x247cda0/d .functor AND 1, L_0x247ca50, L_0x247d310, C4<1>, C4<1>; -L_0x247cda0 .delay (20000,20000,20000) L_0x247cda0/d; -L_0x247ce90/d .functor OR 1, L_0x247cc30, L_0x247cda0, C4<0>, C4<0>; -L_0x247ce90 .delay (20000,20000,20000) L_0x247ce90/d; -v0x244c7e0_0 .net "A", 0 0, L_0x247d0e0; 1 drivers -v0x244c8a0_0 .net "AandB", 0 0, L_0x247cc30; 1 drivers -v0x244c940_0 .net "AddSubSLTSum", 0 0, L_0x247cb40; 1 drivers -v0x244c9e0_0 .net "AxorB", 0 0, L_0x247ca50; 1 drivers -v0x244ca60_0 .net "B", 0 0, L_0x247d410; 1 drivers -v0x244cb10_0 .net "BornB", 0 0, L_0x247c500; 1 drivers -v0x244cbd0_0 .net "CINandAxorB", 0 0, L_0x247cda0; 1 drivers -v0x244cc50_0 .alias "Command", 2 0, v0x245d560_0; -v0x244ccd0_0 .net *"_s3", 0 0, L_0x247c7d0; 1 drivers -v0x244cd50_0 .net *"_s5", 0 0, L_0x247c9b0; 1 drivers -v0x244cdf0_0 .net "carryin", 0 0, L_0x247d310; 1 drivers -v0x244ce90_0 .net "carryout", 0 0, L_0x247ce90; 1 drivers -v0x244cf30_0 .net "nB", 0 0, L_0x247c0f0; 1 drivers -v0x244cfe0_0 .net "nCmd2", 0 0, L_0x247c730; 1 drivers -v0x244d0e0_0 .net "subtract", 0 0, L_0x247c870; 1 drivers -L_0x247c690 .part v0x245e870_0, 0, 1; -L_0x247c7d0 .part v0x245e870_0, 2, 1; -L_0x247c9b0 .part v0x245e870_0, 0, 1; -S_0x244c250 .scope module, "mux0" "TwoInMux" 3 105, 3 8, S_0x244c160; - .timescale -9 -12; -L_0x247c280/d .functor NOT 1, L_0x247c690, C4<0>, C4<0>, C4<0>; -L_0x247c280 .delay (10000,10000,10000) L_0x247c280/d; -L_0x247c320/d .functor AND 1, L_0x247d410, L_0x247c280, C4<1>, C4<1>; -L_0x247c320 .delay (20000,20000,20000) L_0x247c320/d; -L_0x247c410/d .functor AND 1, L_0x247c0f0, L_0x247c690, C4<1>, C4<1>; -L_0x247c410 .delay (20000,20000,20000) L_0x247c410/d; -L_0x247c500/d .functor OR 1, L_0x247c320, L_0x247c410, C4<0>, C4<0>; -L_0x247c500 .delay (20000,20000,20000) L_0x247c500/d; -v0x244c340_0 .net "S", 0 0, L_0x247c690; 1 drivers -v0x244c400_0 .alias "in0", 0 0, v0x244ca60_0; -v0x244c4a0_0 .alias "in1", 0 0, v0x244cf30_0; -v0x244c540_0 .net "nS", 0 0, L_0x247c280; 1 drivers -v0x244c5c0_0 .net "out0", 0 0, L_0x247c320; 1 drivers -v0x244c660_0 .net "out1", 0 0, L_0x247c410; 1 drivers -v0x244c740_0 .alias "outfinal", 0 0, v0x244cb10_0; -S_0x244bc00 .scope module, "setSLTres" "TwoInMux" 3 236, 3 8, S_0x24474b0; - .timescale -9 -12; -L_0x247d3b0/d .functor NOT 1, L_0x247bde0, C4<0>, C4<0>, C4<0>; -L_0x247d3b0 .delay (10000,10000,10000) L_0x247d3b0/d; -L_0x247d650/d .functor AND 1, L_0x247d540, L_0x247d3b0, C4<1>, C4<1>; -L_0x247d650 .delay (20000,20000,20000) L_0x247d650/d; -L_0x247d740/d .functor AND 1, C4<0>, L_0x247bde0, C4<1>, C4<1>; -L_0x247d740 .delay (20000,20000,20000) L_0x247d740/d; -L_0x247d7e0/d .functor OR 1, L_0x247d650, L_0x247d740, C4<0>, C4<0>; -L_0x247d7e0 .delay (20000,20000,20000) L_0x247d7e0/d; -v0x244bcf0_0 .alias "S", 0 0, v0x244d8a0_0; -v0x244bd90_0 .net "in0", 0 0, L_0x247d540; 1 drivers -v0x244be30_0 .net "in1", 0 0, C4<0>; 1 drivers -v0x244bed0_0 .net "nS", 0 0, L_0x247d3b0; 1 drivers -v0x244bf80_0 .net "out0", 0 0, L_0x247d650; 1 drivers -v0x244c020_0 .net "out1", 0 0, L_0x247d740; 1 drivers -v0x244c0c0_0 .net "outfinal", 0 0, L_0x247d7e0; 1 drivers -S_0x244a520 .scope generate, "addbits[1]" "addbits[1]" 3 244, 3 244, S_0x24474b0; - .timescale -9 -12; -P_0x2449f38 .param/l "i" 3 244, +C4<01>; -S_0x244abe0 .scope module, "attempt" "MiddleAddSubSLT" 3 246, 3 89, S_0x244a520; - .timescale -9 -12; -L_0x2476a10/d .functor NOT 1, L_0x2477ec0, C4<0>, C4<0>, C4<0>; -L_0x2476a10 .delay (10000,10000,10000) L_0x2476a10/d; -L_0x24772b0/d .functor NOT 1, L_0x2477350, C4<0>, C4<0>, C4<0>; -L_0x24772b0 .delay (10000,10000,10000) L_0x24772b0/d; -L_0x24773f0/d .functor AND 1, L_0x2477530, L_0x24772b0, C4<1>, C4<1>; -L_0x24773f0 .delay (20000,20000,20000) L_0x24773f0/d; -L_0x24775d0/d .functor XOR 1, L_0x2477e20, L_0x2477080, C4<0>, C4<0>; -L_0x24775d0 .delay (40000,40000,40000) L_0x24775d0/d; -L_0x24776c0/d .functor XOR 1, L_0x24775d0, L_0x2477ff0, C4<0>, C4<0>; -L_0x24776c0 .delay (40000,40000,40000) L_0x24776c0/d; -L_0x24777b0/d .functor AND 1, L_0x2477e20, L_0x2477080, C4<1>, C4<1>; -L_0x24777b0 .delay (20000,20000,20000) L_0x24777b0/d; -L_0x2477920/d .functor AND 1, L_0x24775d0, L_0x2477ff0, C4<1>, C4<1>; -L_0x2477920 .delay (20000,20000,20000) L_0x2477920/d; -L_0x2477a10/d .functor OR 1, L_0x24777b0, L_0x2477920, C4<0>, C4<0>; -L_0x2477a10 .delay (20000,20000,20000) L_0x2477a10/d; -v0x244b260_0 .net "A", 0 0, L_0x2477e20; 1 drivers -v0x244b320_0 .net "AandB", 0 0, L_0x24777b0; 1 drivers -v0x244b3c0_0 .net "AddSubSLTSum", 0 0, L_0x24776c0; 1 drivers -v0x244b460_0 .net "AxorB", 0 0, L_0x24775d0; 1 drivers -v0x244b4e0_0 .net "B", 0 0, L_0x2477ec0; 1 drivers -v0x244b590_0 .net "BornB", 0 0, L_0x2477080; 1 drivers -v0x244b650_0 .net "CINandAxorB", 0 0, L_0x2477920; 1 drivers -v0x244b6d0_0 .alias "Command", 2 0, v0x245d560_0; -v0x244b750_0 .net *"_s3", 0 0, L_0x2477350; 1 drivers -v0x244b7d0_0 .net *"_s5", 0 0, L_0x2477530; 1 drivers -v0x244b870_0 .net "carryin", 0 0, L_0x2477ff0; 1 drivers -v0x244b910_0 .net "carryout", 0 0, L_0x2477a10; 1 drivers -v0x244b9b0_0 .net "nB", 0 0, L_0x2476a10; 1 drivers -v0x244ba60_0 .net "nCmd2", 0 0, L_0x24772b0; 1 drivers -v0x244bb60_0 .net "subtract", 0 0, L_0x24773f0; 1 drivers -L_0x2477210 .part v0x245e870_0, 0, 1; -L_0x2477350 .part v0x245e870_0, 2, 1; -L_0x2477530 .part v0x245e870_0, 0, 1; -S_0x244acd0 .scope module, "mux0" "TwoInMux" 3 105, 3 8, S_0x244abe0; - .timescale -9 -12; -L_0x2476e00/d .functor NOT 1, L_0x2477210, C4<0>, C4<0>, C4<0>; -L_0x2476e00 .delay (10000,10000,10000) L_0x2476e00/d; -L_0x2476ea0/d .functor AND 1, L_0x2477ec0, L_0x2476e00, C4<1>, C4<1>; -L_0x2476ea0 .delay (20000,20000,20000) L_0x2476ea0/d; -L_0x2476f90/d .functor AND 1, L_0x2476a10, L_0x2477210, C4<1>, C4<1>; -L_0x2476f90 .delay (20000,20000,20000) L_0x2476f90/d; -L_0x2477080/d .functor OR 1, L_0x2476ea0, L_0x2476f90, C4<0>, C4<0>; -L_0x2477080 .delay (20000,20000,20000) L_0x2477080/d; -v0x244adc0_0 .net "S", 0 0, L_0x2477210; 1 drivers -v0x244ae80_0 .alias "in0", 0 0, v0x244b4e0_0; -v0x244af20_0 .alias "in1", 0 0, v0x244b9b0_0; -v0x244afc0_0 .net "nS", 0 0, L_0x2476e00; 1 drivers -v0x244b040_0 .net "out0", 0 0, L_0x2476ea0; 1 drivers -v0x244b0e0_0 .net "out1", 0 0, L_0x2476f90; 1 drivers -v0x244b1c0_0 .alias "outfinal", 0 0, v0x244b590_0; -S_0x244a690 .scope module, "setSLTres" "TwoInMux" 3 247, 3 8, S_0x244a520; - .timescale -9 -12; -L_0x2478090/d .functor NOT 1, L_0x247bde0, C4<0>, C4<0>, C4<0>; -L_0x2478090 .delay (10000,10000,10000) L_0x2478090/d; -L_0x2478180/d .functor AND 1, L_0x24784f0, L_0x2478090, C4<1>, C4<1>; -L_0x2478180 .delay (20000,20000,20000) L_0x2478180/d; -L_0x2478270/d .functor AND 1, C4<0>, L_0x247bde0, C4<1>, C4<1>; -L_0x2478270 .delay (20000,20000,20000) L_0x2478270/d; -L_0x2478310/d .functor OR 1, L_0x2478180, L_0x2478270, C4<0>, C4<0>; -L_0x2478310 .delay (20000,20000,20000) L_0x2478310/d; -v0x244a780_0 .alias "S", 0 0, v0x244d8a0_0; -v0x244a800_0 .net "in0", 0 0, L_0x24784f0; 1 drivers -v0x244a8a0_0 .net "in1", 0 0, C4<0>; 1 drivers -v0x244a940_0 .net "nS", 0 0, L_0x2478090; 1 drivers -v0x244a9c0_0 .net "out0", 0 0, L_0x2478180; 1 drivers -v0x244aa60_0 .net "out1", 0 0, L_0x2478270; 1 drivers -v0x244ab40_0 .net "outfinal", 0 0, L_0x2478310; 1 drivers -S_0x2448e00 .scope generate, "addbits[2]" "addbits[2]" 3 244, 3 244, S_0x24474b0; - .timescale -9 -12; -P_0x2448748 .param/l "i" 3 244, +C4<010>; -S_0x2449500 .scope module, "attempt" "MiddleAddSubSLT" 3 246, 3 89, S_0x2448e00; - .timescale -9 -12; -L_0x2478710/d .functor NOT 1, L_0x24799e0, C4<0>, C4<0>, C4<0>; -L_0x2478710 .delay (10000,10000,10000) L_0x2478710/d; -L_0x2478d50/d .functor NOT 1, L_0x2478df0, C4<0>, C4<0>, C4<0>; -L_0x2478d50 .delay (10000,10000,10000) L_0x2478d50/d; -L_0x2478e90/d .functor AND 1, L_0x2478fd0, L_0x2478d50, C4<1>, C4<1>; -L_0x2478e90 .delay (20000,20000,20000) L_0x2478e90/d; -L_0x2479070/d .functor XOR 1, L_0x24798d0, L_0x2478b20, C4<0>, C4<0>; -L_0x2479070 .delay (40000,40000,40000) L_0x2479070/d; -L_0x2479160/d .functor XOR 1, L_0x2479070, L_0x2479b10, C4<0>, C4<0>; -L_0x2479160 .delay (40000,40000,40000) L_0x2479160/d; -L_0x2479250/d .functor AND 1, L_0x24798d0, L_0x2478b20, C4<1>, C4<1>; -L_0x2479250 .delay (20000,20000,20000) L_0x2479250/d; -L_0x24793c0/d .functor AND 1, L_0x2479070, L_0x2479b10, C4<1>, C4<1>; -L_0x24793c0 .delay (20000,20000,20000) L_0x24793c0/d; -L_0x24794b0/d .functor OR 1, L_0x2479250, L_0x24793c0, C4<0>, C4<0>; -L_0x24794b0 .delay (20000,20000,20000) L_0x24794b0/d; -v0x2449b80_0 .net "A", 0 0, L_0x24798d0; 1 drivers -v0x2449c40_0 .net "AandB", 0 0, L_0x2479250; 1 drivers -v0x2449ce0_0 .net "AddSubSLTSum", 0 0, L_0x2479160; 1 drivers -v0x2449d80_0 .net "AxorB", 0 0, L_0x2479070; 1 drivers -v0x2449e00_0 .net "B", 0 0, L_0x24799e0; 1 drivers -v0x2449eb0_0 .net "BornB", 0 0, L_0x2478b20; 1 drivers -v0x2449f70_0 .net "CINandAxorB", 0 0, L_0x24793c0; 1 drivers -v0x2449ff0_0 .alias "Command", 2 0, v0x245d560_0; -v0x244a070_0 .net *"_s3", 0 0, L_0x2478df0; 1 drivers -v0x244a0f0_0 .net *"_s5", 0 0, L_0x2478fd0; 1 drivers -v0x244a190_0 .net "carryin", 0 0, L_0x2479b10; 1 drivers -v0x244a230_0 .net "carryout", 0 0, L_0x24794b0; 1 drivers -v0x244a2d0_0 .net "nB", 0 0, L_0x2478710; 1 drivers -v0x244a380_0 .net "nCmd2", 0 0, L_0x2478d50; 1 drivers -v0x244a480_0 .net "subtract", 0 0, L_0x2478e90; 1 drivers -L_0x2478cb0 .part v0x245e870_0, 0, 1; -L_0x2478df0 .part v0x245e870_0, 2, 1; -L_0x2478fd0 .part v0x245e870_0, 0, 1; -S_0x24495f0 .scope module, "mux0" "TwoInMux" 3 105, 3 8, S_0x2449500; - .timescale -9 -12; -L_0x24788a0/d .functor NOT 1, L_0x2478cb0, C4<0>, C4<0>, C4<0>; -L_0x24788a0 .delay (10000,10000,10000) L_0x24788a0/d; -L_0x2478940/d .functor AND 1, L_0x24799e0, L_0x24788a0, C4<1>, C4<1>; -L_0x2478940 .delay (20000,20000,20000) L_0x2478940/d; -L_0x2478a30/d .functor AND 1, L_0x2478710, L_0x2478cb0, C4<1>, C4<1>; -L_0x2478a30 .delay (20000,20000,20000) L_0x2478a30/d; -L_0x2478b20/d .functor OR 1, L_0x2478940, L_0x2478a30, C4<0>, C4<0>; -L_0x2478b20 .delay (20000,20000,20000) L_0x2478b20/d; -v0x24496e0_0 .net "S", 0 0, L_0x2478cb0; 1 drivers -v0x24497a0_0 .alias "in0", 0 0, v0x2449e00_0; -v0x2449840_0 .alias "in1", 0 0, v0x244a2d0_0; -v0x24498e0_0 .net "nS", 0 0, L_0x24788a0; 1 drivers -v0x2449960_0 .net "out0", 0 0, L_0x2478940; 1 drivers -v0x2449a00_0 .net "out1", 0 0, L_0x2478a30; 1 drivers -v0x2449ae0_0 .alias "outfinal", 0 0, v0x2449eb0_0; -S_0x2448f70 .scope module, "setSLTres" "TwoInMux" 3 247, 3 8, S_0x2448e00; - .timescale -9 -12; -L_0x24797d0/d .functor NOT 1, L_0x247bde0, C4<0>, C4<0>, C4<0>; -L_0x24797d0 .delay (10000,10000,10000) L_0x24797d0/d; -L_0x2479cc0/d .functor AND 1, L_0x247a060, L_0x24797d0, C4<1>, C4<1>; -L_0x2479cc0 .delay (20000,20000,20000) L_0x2479cc0/d; -L_0x2479d60/d .functor AND 1, C4<0>, L_0x247bde0, C4<1>, C4<1>; -L_0x2479d60 .delay (20000,20000,20000) L_0x2479d60/d; -L_0x2479ed0/d .functor OR 1, L_0x2479cc0, L_0x2479d60, C4<0>, C4<0>; -L_0x2479ed0 .delay (20000,20000,20000) L_0x2479ed0/d; -v0x2449060_0 .alias "S", 0 0, v0x244d8a0_0; -v0x2449110_0 .net "in0", 0 0, L_0x247a060; 1 drivers -v0x2449190_0 .net "in1", 0 0, C4<0>; 1 drivers -v0x2449230_0 .net "nS", 0 0, L_0x24797d0; 1 drivers -v0x24492e0_0 .net "out0", 0 0, L_0x2479cc0; 1 drivers -v0x2449380_0 .net "out1", 0 0, L_0x2479d60; 1 drivers -v0x2449460_0 .net "outfinal", 0 0, L_0x2479ed0; 1 drivers -S_0x2447620 .scope generate, "addbits[3]" "addbits[3]" 3 244, 3 244, S_0x24474b0; - .timescale -9 -12; -P_0x2447718 .param/l "i" 3 244, +C4<011>; -S_0x2447d10 .scope module, "attempt" "MiddleAddSubSLT" 3 246, 3 89, S_0x2447620; - .timescale -9 -12; -L_0x247a2b0/d .functor NOT 1, L_0x247b2d0, C4<0>, C4<0>, C4<0>; -L_0x247a2b0 .delay (10000,10000,10000) L_0x247a2b0/d; -L_0x247a8f0/d .functor NOT 1, L_0x247a990, C4<0>, C4<0>, C4<0>; -L_0x247a8f0 .delay (10000,10000,10000) L_0x247a8f0/d; -L_0x247aa30/d .functor AND 1, L_0x247ab70, L_0x247a8f0, C4<1>, C4<1>; -L_0x247aa30 .delay (20000,20000,20000) L_0x247aa30/d; -L_0x247ac10/d .functor XOR 1, L_0x247b410, L_0x247a6c0, C4<0>, C4<0>; -L_0x247ac10 .delay (40000,40000,40000) L_0x247ac10/d; -L_0x247ad00/d .functor XOR 1, L_0x247ac10, L_0x247b5f0, C4<0>, C4<0>; -L_0x247ad00 .delay (40000,40000,40000) L_0x247ad00/d; -L_0x247adf0/d .functor AND 1, L_0x247b410, L_0x247a6c0, C4<1>, C4<1>; -L_0x247adf0 .delay (20000,20000,20000) L_0x247adf0/d; -L_0x247af60/d .functor AND 1, L_0x247ac10, L_0x247b5f0, C4<1>, C4<1>; -L_0x247af60 .delay (20000,20000,20000) L_0x247af60/d; -L_0x2479c40/d .functor OR 1, L_0x247adf0, L_0x247af60, C4<0>, C4<0>; -L_0x2479c40 .delay (20000,20000,20000) L_0x2479c40/d; -v0x2448390_0 .net "A", 0 0, L_0x247b410; 1 drivers -v0x2448450_0 .net "AandB", 0 0, L_0x247adf0; 1 drivers -v0x24484f0_0 .net "AddSubSLTSum", 0 0, L_0x247ad00; 1 drivers -v0x2448590_0 .net "AxorB", 0 0, L_0x247ac10; 1 drivers -v0x2448610_0 .net "B", 0 0, L_0x247b2d0; 1 drivers -v0x24486c0_0 .net "BornB", 0 0, L_0x247a6c0; 1 drivers -v0x2448780_0 .net "CINandAxorB", 0 0, L_0x247af60; 1 drivers -v0x2448800_0 .alias "Command", 2 0, v0x245d560_0; -v0x2448880_0 .net *"_s3", 0 0, L_0x247a990; 1 drivers -v0x2448900_0 .net *"_s5", 0 0, L_0x247ab70; 1 drivers -v0x2448a00_0 .net "carryin", 0 0, L_0x247b5f0; 1 drivers -v0x2448aa0_0 .net "carryout", 0 0, L_0x2479c40; 1 drivers -v0x2448bb0_0 .net "nB", 0 0, L_0x247a2b0; 1 drivers -v0x2448c60_0 .net "nCmd2", 0 0, L_0x247a8f0; 1 drivers -v0x2448d60_0 .net "subtract", 0 0, L_0x247aa30; 1 drivers -L_0x247a850 .part v0x245e870_0, 0, 1; -L_0x247a990 .part v0x245e870_0, 2, 1; -L_0x247ab70 .part v0x245e870_0, 0, 1; -S_0x2447e00 .scope module, "mux0" "TwoInMux" 3 105, 3 8, S_0x2447d10; - .timescale -9 -12; -L_0x247a440/d .functor NOT 1, L_0x247a850, C4<0>, C4<0>, C4<0>; -L_0x247a440 .delay (10000,10000,10000) L_0x247a440/d; -L_0x247a4e0/d .functor AND 1, L_0x247b2d0, L_0x247a440, C4<1>, C4<1>; -L_0x247a4e0 .delay (20000,20000,20000) L_0x247a4e0/d; -L_0x247a5d0/d .functor AND 1, L_0x247a2b0, L_0x247a850, C4<1>, C4<1>; -L_0x247a5d0 .delay (20000,20000,20000) L_0x247a5d0/d; -L_0x247a6c0/d .functor OR 1, L_0x247a4e0, L_0x247a5d0, C4<0>, C4<0>; -L_0x247a6c0 .delay (20000,20000,20000) L_0x247a6c0/d; -v0x2447ef0_0 .net "S", 0 0, L_0x247a850; 1 drivers -v0x2447fb0_0 .alias "in0", 0 0, v0x2448610_0; -v0x2448050_0 .alias "in1", 0 0, v0x2448bb0_0; -v0x24480f0_0 .net "nS", 0 0, L_0x247a440; 1 drivers -v0x2448170_0 .net "out0", 0 0, L_0x247a4e0; 1 drivers -v0x2448210_0 .net "out1", 0 0, L_0x247a5d0; 1 drivers -v0x24482f0_0 .alias "outfinal", 0 0, v0x24486c0_0; -S_0x2447790 .scope module, "setSLTres" "TwoInMux" 3 247, 3 8, S_0x2447620; - .timescale -9 -12; -L_0x247b4b0/d .functor NOT 1, L_0x247bde0, C4<0>, C4<0>, C4<0>; -L_0x247b4b0 .delay (10000,10000,10000) L_0x247b4b0/d; -L_0x247b750/d .functor AND 1, L_0x247ba80, L_0x247b4b0, C4<1>, C4<1>; -L_0x247b750 .delay (20000,20000,20000) L_0x247b750/d; -L_0x247b800/d .functor AND 1, C4<0>, L_0x247bde0, C4<1>, C4<1>; -L_0x247b800 .delay (20000,20000,20000) L_0x247b800/d; -L_0x247b8a0/d .functor OR 1, L_0x247b750, L_0x247b800, C4<0>, C4<0>; -L_0x247b8a0 .delay (20000,20000,20000) L_0x247b8a0/d; -v0x2447880_0 .alias "S", 0 0, v0x244d8a0_0; -v0x2447900_0 .net "in0", 0 0, L_0x247ba80; 1 drivers -v0x24479a0_0 .net "in1", 0 0, C4<0>; 1 drivers -v0x2447a40_0 .net "nS", 0 0, L_0x247b4b0; 1 drivers -v0x2447af0_0 .net "out0", 0 0, L_0x247b750; 1 drivers -v0x2447b90_0 .net "out1", 0 0, L_0x247b800; 1 drivers -v0x2447c70_0 .net "outfinal", 0 0, L_0x247b8a0; 1 drivers -S_0x2444270 .scope module, "trial1" "AndNand32" 3 312, 3 154, S_0x23d85b0; - .timescale -9 -12; -P_0x2443cf8 .param/l "size" 3 161, +C4<0100>; -v0x2444160_0 .alias "A", 3 0, v0x245d340_0; -v0x24472d0_0 .alias "AndNandOut", 3 0, v0x245e770_0; -v0x2447350_0 .alias "B", 3 0, v0x245d460_0; -v0x2447400_0 .alias "Command", 2 0, v0x245d560_0; -L_0x247f1f0 .part/pv L_0x247ef80, 1, 1, 4; -L_0x247f2b0 .part v0x245e5f0_0, 1, 1; -L_0x247f350 .part v0x245e7f0_0, 1, 1; -L_0x247fc60 .part/pv L_0x247f9f0, 2, 1, 4; -L_0x247fd00 .part v0x245e5f0_0, 2, 1; -L_0x247fda0 .part v0x245e7f0_0, 2, 1; -L_0x24806d0 .part/pv L_0x2480460, 3, 1, 4; -L_0x2470620 .part v0x245e5f0_0, 3, 1; -L_0x2480980 .part v0x245e7f0_0, 3, 1; -L_0x2481230 .part/pv L_0x2480fc0, 0, 1, 4; -L_0x2481330 .part v0x245e5f0_0, 0, 1; -L_0x24813d0 .part v0x245e7f0_0, 0, 1; -S_0x2446790 .scope module, "attempt2" "AndNand" 3 165, 3 48, S_0x2444270; - .timescale -9 -12; -L_0x2480a70/d .functor NAND 1, L_0x2481330, L_0x24813d0, C4<1>, C4<1>; -L_0x2480a70 .delay (10000,10000,10000) L_0x2480a70/d; -L_0x2480b70/d .functor NOT 1, L_0x2480a70, C4<0>, C4<0>, C4<0>; -L_0x2480b70 .delay (10000,10000,10000) L_0x2480b70/d; -v0x2446db0_0 .net "A", 0 0, L_0x2481330; 1 drivers -v0x2446e70_0 .net "AandB", 0 0, L_0x2480b70; 1 drivers -v0x2446ef0_0 .net "AnandB", 0 0, L_0x2480a70; 1 drivers -v0x2446fa0_0 .net "AndNandOut", 0 0, L_0x2480fc0; 1 drivers -v0x2447080_0 .net "B", 0 0, L_0x24813d0; 1 drivers -v0x2447100_0 .alias "Command", 2 0, v0x245d560_0; -L_0x2481190 .part v0x245e870_0, 0, 1; -S_0x2446880 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0x2446790; - .timescale -9 -12; -L_0x2480ca0/d .functor NOT 1, L_0x2481190, C4<0>, C4<0>, C4<0>; -L_0x2480ca0 .delay (10000,10000,10000) L_0x2480ca0/d; -L_0x2480d60/d .functor AND 1, L_0x2480b70, L_0x2480ca0, C4<1>, C4<1>; -L_0x2480d60 .delay (20000,20000,20000) L_0x2480d60/d; -L_0x2480e70/d .functor AND 1, L_0x2480a70, L_0x2481190, C4<1>, C4<1>; -L_0x2480e70 .delay (20000,20000,20000) L_0x2480e70/d; -L_0x2480fc0/d .functor OR 1, L_0x2480d60, L_0x2480e70, C4<0>, C4<0>; -L_0x2480fc0 .delay (20000,20000,20000) L_0x2480fc0/d; -v0x2446970_0 .net "S", 0 0, L_0x2481190; 1 drivers -v0x24469f0_0 .alias "in0", 0 0, v0x2446e70_0; -v0x2446a70_0 .alias "in1", 0 0, v0x2446ef0_0; -v0x2446b10_0 .net "nS", 0 0, L_0x2480ca0; 1 drivers -v0x2446b90_0 .net "out0", 0 0, L_0x2480d60; 1 drivers -v0x2446c30_0 .net "out1", 0 0, L_0x2480e70; 1 drivers -v0x2446d10_0 .alias "outfinal", 0 0, v0x2446fa0_0; -S_0x2445bd0 .scope generate, "andbits[1]" "andbits[1]" 3 169, 3 169, S_0x2444270; - .timescale -9 -12; -P_0x2445cc8 .param/l "i" 3 169, +C4<01>; -S_0x2445d40 .scope module, "attempt" "AndNand" 3 171, 3 48, S_0x2445bd0; - .timescale -9 -12; -L_0x247ea20/d .functor NAND 1, L_0x247f2b0, L_0x247f350, C4<1>, C4<1>; -L_0x247ea20 .delay (10000,10000,10000) L_0x247ea20/d; -L_0x247eb30/d .functor NOT 1, L_0x247ea20, C4<0>, C4<0>, C4<0>; -L_0x247eb30 .delay (10000,10000,10000) L_0x247eb30/d; -v0x2446380_0 .net "A", 0 0, L_0x247f2b0; 1 drivers -v0x2446440_0 .net "AandB", 0 0, L_0x247eb30; 1 drivers -v0x24464c0_0 .net "AnandB", 0 0, L_0x247ea20; 1 drivers -v0x2446570_0 .net "AndNandOut", 0 0, L_0x247ef80; 1 drivers -v0x2446650_0 .net "B", 0 0, L_0x247f350; 1 drivers -v0x24466d0_0 .alias "Command", 2 0, v0x245d560_0; -L_0x247f150 .part v0x245e870_0, 0, 1; -S_0x2445e30 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0x2445d40; - .timescale -9 -12; -L_0x247ec60/d .functor NOT 1, L_0x247f150, C4<0>, C4<0>, C4<0>; -L_0x247ec60 .delay (10000,10000,10000) L_0x247ec60/d; -L_0x247ed20/d .functor AND 1, L_0x247eb30, L_0x247ec60, C4<1>, C4<1>; -L_0x247ed20 .delay (20000,20000,20000) L_0x247ed20/d; -L_0x247ee30/d .functor AND 1, L_0x247ea20, L_0x247f150, C4<1>, C4<1>; -L_0x247ee30 .delay (20000,20000,20000) L_0x247ee30/d; -L_0x247ef80/d .functor OR 1, L_0x247ed20, L_0x247ee30, C4<0>, C4<0>; -L_0x247ef80 .delay (20000,20000,20000) L_0x247ef80/d; -v0x2445f20_0 .net "S", 0 0, L_0x247f150; 1 drivers -v0x2445fa0_0 .alias "in0", 0 0, v0x2446440_0; -v0x2446040_0 .alias "in1", 0 0, v0x24464c0_0; -v0x24460e0_0 .net "nS", 0 0, L_0x247ec60; 1 drivers -v0x2446160_0 .net "out0", 0 0, L_0x247ed20; 1 drivers -v0x2446200_0 .net "out1", 0 0, L_0x247ee30; 1 drivers -v0x24462e0_0 .alias "outfinal", 0 0, v0x2446570_0; -S_0x2445010 .scope generate, "andbits[2]" "andbits[2]" 3 169, 3 169, S_0x2444270; - .timescale -9 -12; -P_0x2445108 .param/l "i" 3 169, +C4<010>; -S_0x2445180 .scope module, "attempt" "AndNand" 3 171, 3 48, S_0x2445010; - .timescale -9 -12; -L_0x247f440/d .functor NAND 1, L_0x247fd00, L_0x247fda0, C4<1>, C4<1>; -L_0x247f440 .delay (10000,10000,10000) L_0x247f440/d; -L_0x247f5a0/d .functor NOT 1, L_0x247f440, C4<0>, C4<0>, C4<0>; -L_0x247f5a0 .delay (10000,10000,10000) L_0x247f5a0/d; -v0x24457c0_0 .net "A", 0 0, L_0x247fd00; 1 drivers -v0x2445880_0 .net "AandB", 0 0, L_0x247f5a0; 1 drivers -v0x2445900_0 .net "AnandB", 0 0, L_0x247f440; 1 drivers -v0x24459b0_0 .net "AndNandOut", 0 0, L_0x247f9f0; 1 drivers -v0x2445a90_0 .net "B", 0 0, L_0x247fda0; 1 drivers -v0x2445b10_0 .alias "Command", 2 0, v0x245d560_0; -L_0x247fbc0 .part v0x245e870_0, 0, 1; -S_0x2445270 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0x2445180; - .timescale -9 -12; -L_0x247f6d0/d .functor NOT 1, L_0x247fbc0, C4<0>, C4<0>, C4<0>; -L_0x247f6d0 .delay (10000,10000,10000) L_0x247f6d0/d; -L_0x247f790/d .functor AND 1, L_0x247f5a0, L_0x247f6d0, C4<1>, C4<1>; -L_0x247f790 .delay (20000,20000,20000) L_0x247f790/d; -L_0x247f8a0/d .functor AND 1, L_0x247f440, L_0x247fbc0, C4<1>, C4<1>; -L_0x247f8a0 .delay (20000,20000,20000) L_0x247f8a0/d; -L_0x247f9f0/d .functor OR 1, L_0x247f790, L_0x247f8a0, C4<0>, C4<0>; -L_0x247f9f0 .delay (20000,20000,20000) L_0x247f9f0/d; -v0x2445360_0 .net "S", 0 0, L_0x247fbc0; 1 drivers -v0x24453e0_0 .alias "in0", 0 0, v0x2445880_0; -v0x2445480_0 .alias "in1", 0 0, v0x2445900_0; -v0x2445520_0 .net "nS", 0 0, L_0x247f6d0; 1 drivers -v0x24455a0_0 .net "out0", 0 0, L_0x247f790; 1 drivers -v0x2445640_0 .net "out1", 0 0, L_0x247f8a0; 1 drivers -v0x2445720_0 .alias "outfinal", 0 0, v0x24459b0_0; -S_0x24443e0 .scope generate, "andbits[3]" "andbits[3]" 3 169, 3 169, S_0x2444270; - .timescale -9 -12; -P_0x24444d8 .param/l "i" 3 169, +C4<011>; -S_0x2444570 .scope module, "attempt" "AndNand" 3 171, 3 48, S_0x24443e0; - .timescale -9 -12; -L_0x247fed0/d .functor NAND 1, L_0x2470620, L_0x2480980, C4<1>, C4<1>; -L_0x247fed0 .delay (10000,10000,10000) L_0x247fed0/d; -L_0x2480010/d .functor NOT 1, L_0x247fed0, C4<0>, C4<0>, C4<0>; -L_0x2480010 .delay (10000,10000,10000) L_0x2480010/d; -v0x2444c00_0 .net "A", 0 0, L_0x2470620; 1 drivers -v0x2444cc0_0 .net "AandB", 0 0, L_0x2480010; 1 drivers -v0x2444d40_0 .net "AnandB", 0 0, L_0x247fed0; 1 drivers -v0x2444df0_0 .net "AndNandOut", 0 0, L_0x2480460; 1 drivers -v0x2444ed0_0 .net "B", 0 0, L_0x2480980; 1 drivers -v0x2444f50_0 .alias "Command", 2 0, v0x245d560_0; -L_0x2480630 .part v0x245e870_0, 0, 1; -S_0x2444660 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0x2444570; - .timescale -9 -12; -L_0x2480140/d .functor NOT 1, L_0x2480630, C4<0>, C4<0>, C4<0>; -L_0x2480140 .delay (10000,10000,10000) L_0x2480140/d; -L_0x2480200/d .functor AND 1, L_0x2480010, L_0x2480140, C4<1>, C4<1>; -L_0x2480200 .delay (20000,20000,20000) L_0x2480200/d; -L_0x2480310/d .functor AND 1, L_0x247fed0, L_0x2480630, C4<1>, C4<1>; -L_0x2480310 .delay (20000,20000,20000) L_0x2480310/d; -L_0x2480460/d .functor OR 1, L_0x2480200, L_0x2480310, C4<0>, C4<0>; -L_0x2480460 .delay (20000,20000,20000) L_0x2480460/d; -v0x2444750_0 .net "S", 0 0, L_0x2480630; 1 drivers -v0x24447f0_0 .alias "in0", 0 0, v0x2444cc0_0; -v0x2444890_0 .alias "in1", 0 0, v0x2444d40_0; -v0x2444930_0 .net "nS", 0 0, L_0x2480140; 1 drivers -v0x24449e0_0 .net "out0", 0 0, L_0x2480200; 1 drivers -v0x2444a80_0 .net "out1", 0 0, L_0x2480310; 1 drivers -v0x2444b60_0 .alias "outfinal", 0 0, v0x2444df0_0; -S_0x243f050 .scope module, "trial2" "OrNorXor32" 3 313, 3 177, S_0x23d85b0; - .timescale -9 -12; -P_0x243e1a8 .param/l "size" 3 184, +C4<0100>; -v0x2443fe0_0 .alias "A", 3 0, v0x245d340_0; -v0x2444060_0 .alias "B", 3 0, v0x245d460_0; -v0x24440e0_0 .alias "Command", 2 0, v0x245d560_0; -v0x24441f0_0 .alias "OrNorXorOut", 3 0, v0x245e970_0; -L_0x24825f0 .part/pv L_0x2482380, 1, 1, 4; -L_0x2482690 .part v0x245e5f0_0, 1, 1; -L_0x2482730 .part v0x245e7f0_0, 1, 1; -L_0x24838f0 .part/pv L_0x2483680, 2, 1, 4; -L_0x2483990 .part v0x245e5f0_0, 2, 1; -L_0x2483a30 .part v0x245e7f0_0, 2, 1; -L_0x2484bf0 .part/pv L_0x2484980, 3, 1, 4; -L_0x2484c90 .part v0x245e5f0_0, 3, 1; -L_0x2484d30 .part v0x245e7f0_0, 3, 1; -L_0x2485ee0 .part/pv L_0x2485c70, 0, 1, 4; -L_0x2485fe0 .part v0x245e5f0_0, 0, 1; -L_0x2486080 .part v0x245e7f0_0, 0, 1; -S_0x2442dd0 .scope module, "attempt2" "OrNorXor" 3 192, 3 64, S_0x243f050; - .timescale -9 -12; -L_0x2484dd0/d .functor NOR 1, L_0x2485fe0, L_0x2486080, C4<0>, C4<0>; -L_0x2484dd0 .delay (10000,10000,10000) L_0x2484dd0/d; -L_0x2484ed0/d .functor NOT 1, L_0x2484dd0, C4<0>, C4<0>, C4<0>; -L_0x2484ed0 .delay (10000,10000,10000) L_0x2484ed0/d; -L_0x2485000/d .functor NAND 1, L_0x2485fe0, L_0x2486080, C4<1>, C4<1>; -L_0x2485000 .delay (10000,10000,10000) L_0x2485000/d; -L_0x2485160/d .functor NAND 1, L_0x2485000, L_0x2484ed0, C4<1>, C4<1>; -L_0x2485160 .delay (10000,10000,10000) L_0x2485160/d; -L_0x2485270/d .functor NOT 1, L_0x2485160, C4<0>, C4<0>, C4<0>; -L_0x2485270 .delay (10000,10000,10000) L_0x2485270/d; -v0x2443920_0 .net "A", 0 0, L_0x2485fe0; 1 drivers -v0x24439c0_0 .net "AnandB", 0 0, L_0x2485000; 1 drivers -v0x2443a60_0 .net "AnorB", 0 0, L_0x2484dd0; 1 drivers -v0x2443ae0_0 .net "AorB", 0 0, L_0x2484ed0; 1 drivers -v0x2443bc0_0 .net "AxorB", 0 0, L_0x2485270; 1 drivers -v0x2443c70_0 .net "B", 0 0, L_0x2486080; 1 drivers -v0x2443d30_0 .alias "Command", 2 0, v0x245d560_0; -v0x2443db0_0 .net "OrNorXorOut", 0 0, L_0x2485c70; 1 drivers -v0x2443e30_0 .net "XorNor", 0 0, L_0x24856f0; 1 drivers -v0x2443f00_0 .net "nXor", 0 0, L_0x2485160; 1 drivers -L_0x2485870 .part v0x245e870_0, 2, 1; -L_0x2485e40 .part v0x245e870_0, 0, 1; -S_0x24433b0 .scope module, "mux0" "TwoInMux" 3 83, 3 8, S_0x2442dd0; - .timescale -9 -12; -L_0x24853d0/d .functor NOT 1, L_0x2485870, C4<0>, C4<0>, C4<0>; -L_0x24853d0 .delay (10000,10000,10000) L_0x24853d0/d; -L_0x2485490/d .functor AND 1, L_0x2485270, L_0x24853d0, C4<1>, C4<1>; -L_0x2485490 .delay (20000,20000,20000) L_0x2485490/d; -L_0x24855a0/d .functor AND 1, L_0x2484dd0, L_0x2485870, C4<1>, C4<1>; -L_0x24855a0 .delay (20000,20000,20000) L_0x24855a0/d; -L_0x24856f0/d .functor OR 1, L_0x2485490, L_0x24855a0, C4<0>, C4<0>; -L_0x24856f0 .delay (20000,20000,20000) L_0x24856f0/d; -v0x24434a0_0 .net "S", 0 0, L_0x2485870; 1 drivers -v0x2443560_0 .alias "in0", 0 0, v0x2443bc0_0; -v0x2443600_0 .alias "in1", 0 0, v0x2443a60_0; -v0x24436a0_0 .net "nS", 0 0, L_0x24853d0; 1 drivers -v0x2443720_0 .net "out0", 0 0, L_0x2485490; 1 drivers -v0x24437c0_0 .net "out1", 0 0, L_0x24855a0; 1 drivers -v0x24438a0_0 .alias "outfinal", 0 0, v0x2443e30_0; -S_0x2442ec0 .scope module, "mux1" "TwoInMux" 3 84, 3 8, S_0x2442dd0; - .timescale -9 -12; -L_0x2485910/d .functor NOT 1, L_0x2485e40, C4<0>, C4<0>, C4<0>; -L_0x2485910 .delay (10000,10000,10000) L_0x2485910/d; -L_0x24859d0/d .functor AND 1, L_0x24856f0, L_0x2485910, C4<1>, C4<1>; -L_0x24859d0 .delay (20000,20000,20000) L_0x24859d0/d; -L_0x2485b20/d .functor AND 1, L_0x2484ed0, L_0x2485e40, C4<1>, C4<1>; -L_0x2485b20 .delay (20000,20000,20000) L_0x2485b20/d; -L_0x2485c70/d .functor OR 1, L_0x24859d0, L_0x2485b20, C4<0>, C4<0>; -L_0x2485c70 .delay (20000,20000,20000) L_0x2485c70/d; -v0x2442fb0_0 .net "S", 0 0, L_0x2485e40; 1 drivers -v0x2443030_0 .alias "in0", 0 0, v0x2443e30_0; -v0x24430b0_0 .alias "in1", 0 0, v0x2443ae0_0; -v0x2443150_0 .net "nS", 0 0, L_0x2485910; 1 drivers -v0x24431d0_0 .net "out0", 0 0, L_0x24859d0; 1 drivers -v0x2443270_0 .net "out1", 0 0, L_0x2485b20; 1 drivers -v0x2443310_0 .alias "outfinal", 0 0, v0x2443db0_0; -S_0x24419d0 .scope generate, "orbits[1]" "orbits[1]" 3 196, 3 196, S_0x243f050; - .timescale -9 -12; -P_0x24416b8 .param/l "i" 3 196, +C4<01>; -S_0x2441b00 .scope module, "attempt" "OrNorXor" 3 198, 3 64, S_0x24419d0; - .timescale -9 -12; -L_0x24812d0/d .functor NOR 1, L_0x2482690, L_0x2482730, C4<0>, C4<0>; -L_0x24812d0 .delay (10000,10000,10000) L_0x24812d0/d; -L_0x24815e0/d .functor NOT 1, L_0x24812d0, C4<0>, C4<0>, C4<0>; -L_0x24815e0 .delay (10000,10000,10000) L_0x24815e0/d; -L_0x2481710/d .functor NAND 1, L_0x2482690, L_0x2482730, C4<1>, C4<1>; -L_0x2481710 .delay (10000,10000,10000) L_0x2481710/d; -L_0x2481870/d .functor NAND 1, L_0x2481710, L_0x24815e0, C4<1>, C4<1>; -L_0x2481870 .delay (10000,10000,10000) L_0x2481870/d; -L_0x2481980/d .functor NOT 1, L_0x2481870, C4<0>, C4<0>, C4<0>; -L_0x2481980 .delay (10000,10000,10000) L_0x2481980/d; -v0x2442690_0 .net "A", 0 0, L_0x2482690; 1 drivers -v0x2442730_0 .net "AnandB", 0 0, L_0x2481710; 1 drivers -v0x24427d0_0 .net "AnorB", 0 0, L_0x24812d0; 1 drivers -v0x2442880_0 .net "AorB", 0 0, L_0x24815e0; 1 drivers -v0x2442960_0 .net "AxorB", 0 0, L_0x2481980; 1 drivers -v0x2442a10_0 .net "B", 0 0, L_0x2482730; 1 drivers -v0x2442ad0_0 .alias "Command", 2 0, v0x245d560_0; -v0x2442b50_0 .net "OrNorXorOut", 0 0, L_0x2482380; 1 drivers -v0x2442c20_0 .net "XorNor", 0 0, L_0x2481e00; 1 drivers -v0x2442cf0_0 .net "nXor", 0 0, L_0x2481870; 1 drivers -L_0x2481f80 .part v0x245e870_0, 2, 1; -L_0x2482550 .part v0x245e870_0, 0, 1; -S_0x2442120 .scope module, "mux0" "TwoInMux" 3 83, 3 8, S_0x2441b00; - .timescale -9 -12; -L_0x2481ae0/d .functor NOT 1, L_0x2481f80, C4<0>, C4<0>, C4<0>; -L_0x2481ae0 .delay (10000,10000,10000) L_0x2481ae0/d; -L_0x2481ba0/d .functor AND 1, L_0x2481980, L_0x2481ae0, C4<1>, C4<1>; -L_0x2481ba0 .delay (20000,20000,20000) L_0x2481ba0/d; -L_0x2481cb0/d .functor AND 1, L_0x24812d0, L_0x2481f80, C4<1>, C4<1>; -L_0x2481cb0 .delay (20000,20000,20000) L_0x2481cb0/d; -L_0x2481e00/d .functor OR 1, L_0x2481ba0, L_0x2481cb0, C4<0>, C4<0>; -L_0x2481e00 .delay (20000,20000,20000) L_0x2481e00/d; -v0x2442210_0 .net "S", 0 0, L_0x2481f80; 1 drivers -v0x24422d0_0 .alias "in0", 0 0, v0x2442960_0; -v0x2442370_0 .alias "in1", 0 0, v0x24427d0_0; -v0x2442410_0 .net "nS", 0 0, L_0x2481ae0; 1 drivers -v0x2442490_0 .net "out0", 0 0, L_0x2481ba0; 1 drivers -v0x2442530_0 .net "out1", 0 0, L_0x2481cb0; 1 drivers -v0x2442610_0 .alias "outfinal", 0 0, v0x2442c20_0; -S_0x2441bf0 .scope module, "mux1" "TwoInMux" 3 84, 3 8, S_0x2441b00; - .timescale -9 -12; -L_0x2482020/d .functor NOT 1, L_0x2482550, C4<0>, C4<0>, C4<0>; -L_0x2482020 .delay (10000,10000,10000) L_0x2482020/d; -L_0x24820e0/d .functor AND 1, L_0x2481e00, L_0x2482020, C4<1>, C4<1>; -L_0x24820e0 .delay (20000,20000,20000) L_0x24820e0/d; -L_0x2482230/d .functor AND 1, L_0x24815e0, L_0x2482550, C4<1>, C4<1>; -L_0x2482230 .delay (20000,20000,20000) L_0x2482230/d; -L_0x2482380/d .functor OR 1, L_0x24820e0, L_0x2482230, C4<0>, C4<0>; -L_0x2482380 .delay (20000,20000,20000) L_0x2482380/d; -v0x2441ce0_0 .net "S", 0 0, L_0x2482550; 1 drivers -v0x2441d60_0 .alias "in0", 0 0, v0x2442c20_0; -v0x2441de0_0 .alias "in1", 0 0, v0x2442880_0; -v0x2441e80_0 .net "nS", 0 0, L_0x2482020; 1 drivers -v0x2441f00_0 .net "out0", 0 0, L_0x24820e0; 1 drivers -v0x2441fa0_0 .net "out1", 0 0, L_0x2482230; 1 drivers -v0x2442080_0 .alias "outfinal", 0 0, v0x2442b50_0; -S_0x24405b0 .scope generate, "orbits[2]" "orbits[2]" 3 196, 3 196, S_0x243f050; - .timescale -9 -12; -P_0x2440328 .param/l "i" 3 196, +C4<010>; -S_0x24406e0 .scope module, "attempt" "OrNorXor" 3 198, 3 64, S_0x24405b0; - .timescale -9 -12; -L_0x24827d0/d .functor NOR 1, L_0x2483990, L_0x2483a30, C4<0>, C4<0>; -L_0x24827d0 .delay (10000,10000,10000) L_0x24827d0/d; -L_0x24828e0/d .functor NOT 1, L_0x24827d0, C4<0>, C4<0>, C4<0>; -L_0x24828e0 .delay (10000,10000,10000) L_0x24828e0/d; -L_0x2482a10/d .functor NAND 1, L_0x2483990, L_0x2483a30, C4<1>, C4<1>; -L_0x2482a10 .delay (10000,10000,10000) L_0x2482a10/d; -L_0x2482b70/d .functor NAND 1, L_0x2482a10, L_0x24828e0, C4<1>, C4<1>; -L_0x2482b70 .delay (10000,10000,10000) L_0x2482b70/d; -L_0x2482c80/d .functor NOT 1, L_0x2482b70, C4<0>, C4<0>, C4<0>; -L_0x2482c80 .delay (10000,10000,10000) L_0x2482c80/d; -v0x24412b0_0 .net "A", 0 0, L_0x2483990; 1 drivers -v0x2441350_0 .net "AnandB", 0 0, L_0x2482a10; 1 drivers -v0x24413f0_0 .net "AnorB", 0 0, L_0x24827d0; 1 drivers -v0x24414a0_0 .net "AorB", 0 0, L_0x24828e0; 1 drivers -v0x2441580_0 .net "AxorB", 0 0, L_0x2482c80; 1 drivers -v0x2441630_0 .net "B", 0 0, L_0x2483a30; 1 drivers -v0x24416f0_0 .alias "Command", 2 0, v0x245d560_0; -v0x2441770_0 .net "OrNorXorOut", 0 0, L_0x2483680; 1 drivers -v0x2441820_0 .net "XorNor", 0 0, L_0x2483100; 1 drivers -v0x24418f0_0 .net "nXor", 0 0, L_0x2482b70; 1 drivers -L_0x2483280 .part v0x245e870_0, 2, 1; -L_0x2483850 .part v0x245e870_0, 0, 1; -S_0x2440d40 .scope module, "mux0" "TwoInMux" 3 83, 3 8, S_0x24406e0; - .timescale -9 -12; -L_0x2482de0/d .functor NOT 1, L_0x2483280, C4<0>, C4<0>, C4<0>; -L_0x2482de0 .delay (10000,10000,10000) L_0x2482de0/d; -L_0x2482ea0/d .functor AND 1, L_0x2482c80, L_0x2482de0, C4<1>, C4<1>; -L_0x2482ea0 .delay (20000,20000,20000) L_0x2482ea0/d; -L_0x2482fb0/d .functor AND 1, L_0x24827d0, L_0x2483280, C4<1>, C4<1>; -L_0x2482fb0 .delay (20000,20000,20000) L_0x2482fb0/d; -L_0x2483100/d .functor OR 1, L_0x2482ea0, L_0x2482fb0, C4<0>, C4<0>; -L_0x2483100 .delay (20000,20000,20000) L_0x2483100/d; -v0x2440e30_0 .net "S", 0 0, L_0x2483280; 1 drivers -v0x2440ef0_0 .alias "in0", 0 0, v0x2441580_0; -v0x2440f90_0 .alias "in1", 0 0, v0x24413f0_0; -v0x2441030_0 .net "nS", 0 0, L_0x2482de0; 1 drivers -v0x24410b0_0 .net "out0", 0 0, L_0x2482ea0; 1 drivers -v0x2441150_0 .net "out1", 0 0, L_0x2482fb0; 1 drivers -v0x2441230_0 .alias "outfinal", 0 0, v0x2441820_0; -S_0x24407d0 .scope module, "mux1" "TwoInMux" 3 84, 3 8, S_0x24406e0; - .timescale -9 -12; -L_0x2483320/d .functor NOT 1, L_0x2483850, C4<0>, C4<0>, C4<0>; -L_0x2483320 .delay (10000,10000,10000) L_0x2483320/d; -L_0x24833e0/d .functor AND 1, L_0x2483100, L_0x2483320, C4<1>, C4<1>; -L_0x24833e0 .delay (20000,20000,20000) L_0x24833e0/d; -L_0x2483530/d .functor AND 1, L_0x24828e0, L_0x2483850, C4<1>, C4<1>; -L_0x2483530 .delay (20000,20000,20000) L_0x2483530/d; -L_0x2483680/d .functor OR 1, L_0x24833e0, L_0x2483530, C4<0>, C4<0>; -L_0x2483680 .delay (20000,20000,20000) L_0x2483680/d; -v0x24408c0_0 .net "S", 0 0, L_0x2483850; 1 drivers -v0x2440960_0 .alias "in0", 0 0, v0x2441820_0; -v0x2440a00_0 .alias "in1", 0 0, v0x24414a0_0; -v0x2440aa0_0 .net "nS", 0 0, L_0x2483320; 1 drivers -v0x2440b20_0 .net "out0", 0 0, L_0x24833e0; 1 drivers -v0x2440bc0_0 .net "out1", 0 0, L_0x2483530; 1 drivers -v0x2440ca0_0 .alias "outfinal", 0 0, v0x2441770_0; -S_0x243f1c0 .scope generate, "orbits[3]" "orbits[3]" 3 196, 3 196, S_0x243f050; - .timescale -9 -12; -P_0x243f2b8 .param/l "i" 3 196, +C4<011>; -S_0x243f350 .scope module, "attempt" "OrNorXor" 3 198, 3 64, S_0x243f1c0; - .timescale -9 -12; -L_0x2483b10/d .functor NOR 1, L_0x2484c90, L_0x2484d30, C4<0>, C4<0>; -L_0x2483b10 .delay (10000,10000,10000) L_0x2483b10/d; -L_0x2483c00/d .functor NOT 1, L_0x2483b10, C4<0>, C4<0>, C4<0>; -L_0x2483c00 .delay (10000,10000,10000) L_0x2483c00/d; -L_0x2483d10/d .functor NAND 1, L_0x2484c90, L_0x2484d30, C4<1>, C4<1>; -L_0x2483d10 .delay (10000,10000,10000) L_0x2483d10/d; -L_0x2483e70/d .functor NAND 1, L_0x2483d10, L_0x2483c00, C4<1>, C4<1>; -L_0x2483e70 .delay (10000,10000,10000) L_0x2483e70/d; -L_0x2483f80/d .functor NOT 1, L_0x2483e70, C4<0>, C4<0>, C4<0>; -L_0x2483f80 .delay (10000,10000,10000) L_0x2483f80/d; -v0x243ff20_0 .net "A", 0 0, L_0x2484c90; 1 drivers -v0x243ffc0_0 .net "AnandB", 0 0, L_0x2483d10; 1 drivers -v0x2440060_0 .net "AnorB", 0 0, L_0x2483b10; 1 drivers -v0x2440110_0 .net "AorB", 0 0, L_0x2483c00; 1 drivers -v0x24401f0_0 .net "AxorB", 0 0, L_0x2483f80; 1 drivers -v0x24402a0_0 .net "B", 0 0, L_0x2484d30; 1 drivers -v0x2440360_0 .alias "Command", 2 0, v0x245d560_0; -v0x24403e0_0 .net "OrNorXorOut", 0 0, L_0x2484980; 1 drivers -v0x2440460_0 .net "XorNor", 0 0, L_0x2484400; 1 drivers -v0x2440530_0 .net "nXor", 0 0, L_0x2483e70; 1 drivers -L_0x2484580 .part v0x245e870_0, 2, 1; -L_0x2484b50 .part v0x245e870_0, 0, 1; -S_0x243f9b0 .scope module, "mux0" "TwoInMux" 3 83, 3 8, S_0x243f350; - .timescale -9 -12; -L_0x24840e0/d .functor NOT 1, L_0x2484580, C4<0>, C4<0>, C4<0>; -L_0x24840e0 .delay (10000,10000,10000) L_0x24840e0/d; -L_0x24841a0/d .functor AND 1, L_0x2483f80, L_0x24840e0, C4<1>, C4<1>; -L_0x24841a0 .delay (20000,20000,20000) L_0x24841a0/d; -L_0x24842b0/d .functor AND 1, L_0x2483b10, L_0x2484580, C4<1>, C4<1>; -L_0x24842b0 .delay (20000,20000,20000) L_0x24842b0/d; -L_0x2484400/d .functor OR 1, L_0x24841a0, L_0x24842b0, C4<0>, C4<0>; -L_0x2484400 .delay (20000,20000,20000) L_0x2484400/d; -v0x243faa0_0 .net "S", 0 0, L_0x2484580; 1 drivers -v0x243fb60_0 .alias "in0", 0 0, v0x24401f0_0; -v0x243fc00_0 .alias "in1", 0 0, v0x2440060_0; -v0x243fca0_0 .net "nS", 0 0, L_0x24840e0; 1 drivers -v0x243fd20_0 .net "out0", 0 0, L_0x24841a0; 1 drivers -v0x243fdc0_0 .net "out1", 0 0, L_0x24842b0; 1 drivers -v0x243fea0_0 .alias "outfinal", 0 0, v0x2440460_0; -S_0x243f440 .scope module, "mux1" "TwoInMux" 3 84, 3 8, S_0x243f350; - .timescale -9 -12; -L_0x2484620/d .functor NOT 1, L_0x2484b50, C4<0>, C4<0>, C4<0>; -L_0x2484620 .delay (10000,10000,10000) L_0x2484620/d; -L_0x24846e0/d .functor AND 1, L_0x2484400, L_0x2484620, C4<1>, C4<1>; -L_0x24846e0 .delay (20000,20000,20000) L_0x24846e0/d; -L_0x2484830/d .functor AND 1, L_0x2483c00, L_0x2484b50, C4<1>, C4<1>; -L_0x2484830 .delay (20000,20000,20000) L_0x2484830/d; -L_0x2484980/d .functor OR 1, L_0x24846e0, L_0x2484830, C4<0>, C4<0>; -L_0x2484980 .delay (20000,20000,20000) L_0x2484980/d; -v0x243f530_0 .net "S", 0 0, L_0x2484b50; 1 drivers -v0x243f5d0_0 .alias "in0", 0 0, v0x2440460_0; -v0x243f670_0 .alias "in1", 0 0, v0x2440110_0; -v0x243f710_0 .net "nS", 0 0, L_0x2484620; 1 drivers -v0x243f790_0 .net "out0", 0 0, L_0x24846e0; 1 drivers -v0x243f830_0 .net "out1", 0 0, L_0x2484830; 1 drivers -v0x243f910_0 .alias "outfinal", 0 0, v0x24403e0_0; -S_0x243e6d0 .scope module, "ZeroMux0case" "FourInMux" 3 315, 3 24, S_0x23d85b0; - .timescale -9 -12; -L_0x2485f80/d .functor NOT 1, L_0x2476bb0, C4<0>, C4<0>, C4<0>; -L_0x2485f80 .delay (10000,10000,10000) L_0x2485f80/d; -L_0x24861d0/d .functor NOT 1, L_0x2476ce0, C4<0>, C4<0>, C4<0>; -L_0x24861d0 .delay (10000,10000,10000) L_0x24861d0/d; -L_0x2486290/d .functor NAND 1, L_0x2485f80, L_0x24861d0, L_0x24868c0, C4<1>; -L_0x2486290 .delay (10000,10000,10000) L_0x2486290/d; -L_0x2486380/d .functor NAND 1, L_0x2476bb0, L_0x24861d0, L_0x2486960, C4<1>; -L_0x2486380 .delay (10000,10000,10000) L_0x2486380/d; -L_0x2486470/d .functor NAND 1, L_0x2485f80, L_0x2476ce0, L_0x2486a00, C4<1>; -L_0x2486470 .delay (10000,10000,10000) L_0x2486470/d; -L_0x2486560/d .functor NAND 1, L_0x2476bb0, L_0x2476ce0, L_0x2486de0, C4<1>; -L_0x2486560 .delay (10000,10000,10000) L_0x2486560/d; -L_0x2486640/d .functor NAND 1, L_0x2486290, L_0x2486380, L_0x2486470, L_0x2486560; -L_0x2486640 .delay (10000,10000,10000) L_0x2486640/d; -v0x243e7c0_0 .net "S0", 0 0, L_0x2476bb0; 1 drivers -v0x243e880_0 .net "S1", 0 0, L_0x2476ce0; 1 drivers -v0x243e920_0 .net "in0", 0 0, L_0x24868c0; 1 drivers -v0x243e9c0_0 .net "in1", 0 0, L_0x2486960; 1 drivers -v0x243ea40_0 .net "in2", 0 0, L_0x2486a00; 1 drivers -v0x243eae0_0 .net "in3", 0 0, L_0x2486de0; 1 drivers -v0x243eb80_0 .net "nS0", 0 0, L_0x2485f80; 1 drivers -v0x243ec20_0 .net "nS1", 0 0, L_0x24861d0; 1 drivers -v0x243ecc0_0 .net "out", 0 0, L_0x2486640; 1 drivers -v0x243ed60_0 .net "out0", 0 0, L_0x2486290; 1 drivers -v0x243ee00_0 .net "out1", 0 0, L_0x2486380; 1 drivers -v0x243eea0_0 .net "out2", 0 0, L_0x2486470; 1 drivers -v0x243efb0_0 .net "out3", 0 0, L_0x2486560; 1 drivers -S_0x243dd10 .scope module, "OneMux0case" "FourInMux" 3 316, 3 24, S_0x23d85b0; - .timescale -9 -12; -L_0x2486b60/d .functor NOT 1, L_0x24876f0, C4<0>, C4<0>, C4<0>; -L_0x2486b60 .delay (10000,10000,10000) L_0x2486b60/d; -L_0x2486c50/d .functor NOT 1, L_0x2486ed0, C4<0>, C4<0>, C4<0>; -L_0x2486c50 .delay (10000,10000,10000) L_0x2486c50/d; -L_0x2486cf0/d .functor NAND 1, L_0x2486b60, L_0x2486c50, L_0x2487000, C4<1>; -L_0x2486cf0 .delay (10000,10000,10000) L_0x2486cf0/d; -L_0x24871b0/d .functor NAND 1, L_0x24876f0, L_0x2486c50, L_0x2487a80, C4<1>; -L_0x24871b0 .delay (10000,10000,10000) L_0x24871b0/d; -L_0x24872a0/d .functor NAND 1, L_0x2486b60, L_0x2486ed0, L_0x2487b20, C4<1>; -L_0x24872a0 .delay (10000,10000,10000) L_0x24872a0/d; -L_0x2487390/d .functor NAND 1, L_0x24876f0, L_0x2486ed0, L_0x2487820, C4<1>; -L_0x2487390 .delay (10000,10000,10000) L_0x2487390/d; -L_0x2487470/d .functor NAND 1, L_0x2486cf0, L_0x24871b0, L_0x24872a0, L_0x2487390; -L_0x2487470 .delay (10000,10000,10000) L_0x2487470/d; -v0x243de00_0 .net "S0", 0 0, L_0x24876f0; 1 drivers -v0x243dec0_0 .net "S1", 0 0, L_0x2486ed0; 1 drivers -v0x243df60_0 .net "in0", 0 0, L_0x2487000; 1 drivers -v0x243e000_0 .net "in1", 0 0, L_0x2487a80; 1 drivers -v0x243e080_0 .net "in2", 0 0, L_0x2487b20; 1 drivers -v0x243e120_0 .net "in3", 0 0, L_0x2487820; 1 drivers -v0x243e200_0 .net "nS0", 0 0, L_0x2486b60; 1 drivers -v0x243e2a0_0 .net "nS1", 0 0, L_0x2486c50; 1 drivers -v0x243e340_0 .net "out", 0 0, L_0x2487470; 1 drivers -v0x243e3e0_0 .net "out0", 0 0, L_0x2486cf0; 1 drivers -v0x243e480_0 .net "out1", 0 0, L_0x24871b0; 1 drivers -v0x243e520_0 .net "out2", 0 0, L_0x24872a0; 1 drivers -v0x243e630_0 .net "out3", 0 0, L_0x2487390; 1 drivers -S_0x243d7c0 .scope module, "TwoMux0case" "TwoInMux" 3 317, 3 8, S_0x23d85b0; - .timescale -9 -12; -L_0x2487910/d .functor NOT 1, L_0x2487bc0, C4<0>, C4<0>, C4<0>; -L_0x2487910 .delay (10000,10000,10000) L_0x2487910/d; -L_0x2487a00/d .functor AND 1, L_0x2487c60, L_0x2487910, C4<1>, C4<1>; -L_0x2487a00 .delay (20000,20000,20000) L_0x2487a00/d; -L_0x2487ec0/d .functor AND 1, L_0x2487d50, L_0x2487bc0, C4<1>, C4<1>; -L_0x2487ec0 .delay (20000,20000,20000) L_0x2487ec0/d; -L_0x2487fb0/d .functor OR 1, L_0x2487a00, L_0x2487ec0, C4<0>, C4<0>; -L_0x2487fb0 .delay (20000,20000,20000) L_0x2487fb0/d; -v0x243d8b0_0 .net "S", 0 0, L_0x2487bc0; 1 drivers -v0x243d970_0 .net "in0", 0 0, L_0x2487c60; 1 drivers -v0x243da10_0 .net "in1", 0 0, L_0x2487d50; 1 drivers -v0x243dab0_0 .net "nS", 0 0, L_0x2487910; 1 drivers -v0x243db30_0 .net "out0", 0 0, L_0x2487a00; 1 drivers -v0x243dbd0_0 .net "out1", 0 0, L_0x2487ec0; 1 drivers -v0x243dc70_0 .net "outfinal", 0 0, L_0x2487fb0; 1 drivers -S_0x243bc40 .scope generate, "muxbits[1]" "muxbits[1]" 3 322, 3 322, S_0x23d85b0; - .timescale -9 -12; -P_0x243ac38 .param/l "i" 3 322, +C4<01>; -L_0x2471220/d .functor OR 1, L_0x2471320, L_0x24710e0, C4<0>, C4<0>; -L_0x2471220 .delay (20000,20000,20000) L_0x2471220/d; -v0x243d660_0 .net *"_s15", 0 0, L_0x2471320; 1 drivers -v0x243d720_0 .net *"_s16", 0 0, L_0x24710e0; 1 drivers -S_0x243cce0 .scope module, "ZeroMux" "FourInMux" 3 324, 3 24, S_0x243bc40; - .timescale -9 -12; -L_0x246eae0/d .functor NOT 1, L_0x246f420, C4<0>, C4<0>, C4<0>; -L_0x246eae0 .delay (10000,10000,10000) L_0x246eae0/d; -L_0x246ed30/d .functor NOT 1, L_0x246f550, C4<0>, C4<0>, C4<0>; -L_0x246ed30 .delay (10000,10000,10000) L_0x246ed30/d; -L_0x246edf0/d .functor NAND 1, L_0x246eae0, L_0x246ed30, L_0x246f680, C4<1>; -L_0x246edf0 .delay (10000,10000,10000) L_0x246edf0/d; -L_0x246eee0/d .functor NAND 1, L_0x246f420, L_0x246ed30, L_0x246f720, C4<1>; -L_0x246eee0 .delay (10000,10000,10000) L_0x246eee0/d; -L_0x246efd0/d .functor NAND 1, L_0x246eae0, L_0x246f550, L_0x246f7c0, C4<1>; -L_0x246efd0 .delay (10000,10000,10000) L_0x246efd0/d; -L_0x246f0c0/d .functor NAND 1, L_0x246f420, L_0x246f550, L_0x246f9c0, C4<1>; -L_0x246f0c0 .delay (10000,10000,10000) L_0x246f0c0/d; -L_0x246f1a0/d .functor NAND 1, L_0x246edf0, L_0x246eee0, L_0x246efd0, L_0x246f0c0; -L_0x246f1a0 .delay (10000,10000,10000) L_0x246f1a0/d; -v0x243cdd0_0 .net "S0", 0 0, L_0x246f420; 1 drivers -v0x243ce90_0 .net "S1", 0 0, L_0x246f550; 1 drivers -v0x243cf30_0 .net "in0", 0 0, L_0x246f680; 1 drivers -v0x243cfd0_0 .net "in1", 0 0, L_0x246f720; 1 drivers -v0x243d050_0 .net "in2", 0 0, L_0x246f7c0; 1 drivers -v0x243d0f0_0 .net "in3", 0 0, L_0x246f9c0; 1 drivers -v0x243d190_0 .net "nS0", 0 0, L_0x246eae0; 1 drivers -v0x243d230_0 .net "nS1", 0 0, L_0x246ed30; 1 drivers -v0x243d2d0_0 .net "out", 0 0, L_0x246f1a0; 1 drivers -v0x243d370_0 .net "out0", 0 0, L_0x246edf0; 1 drivers -v0x243d410_0 .net "out1", 0 0, L_0x246eee0; 1 drivers -v0x243d4b0_0 .net "out2", 0 0, L_0x246efd0; 1 drivers -v0x243d5c0_0 .net "out3", 0 0, L_0x246f0c0; 1 drivers -S_0x243c320 .scope module, "OneMux" "FourInMux" 3 325, 3 24, S_0x243bc40; - .timescale -9 -12; -L_0x246fa60/d .functor NOT 1, L_0x24702c0, C4<0>, C4<0>, C4<0>; -L_0x246fa60 .delay (10000,10000,10000) L_0x246fa60/d; -L_0x246fb50/d .functor NOT 1, L_0x24703f0, C4<0>, C4<0>, C4<0>; -L_0x246fb50 .delay (10000,10000,10000) L_0x246fb50/d; -L_0x246fbf0/d .functor NAND 1, L_0x246fa60, L_0x246fb50, L_0x2470580, C4<1>; -L_0x246fbf0 .delay (10000,10000,10000) L_0x246fbf0/d; -L_0x246fd30/d .functor NAND 1, L_0x24702c0, L_0x246fb50, L_0x2470730, C4<1>; -L_0x246fd30 .delay (10000,10000,10000) L_0x246fd30/d; -L_0x246fe20/d .functor NAND 1, L_0x246fa60, L_0x24703f0, L_0x24707d0, C4<1>; -L_0x246fe20 .delay (10000,10000,10000) L_0x246fe20/d; -L_0x246ff10/d .functor NAND 1, L_0x24702c0, L_0x24703f0, L_0x2470870, C4<1>; -L_0x246ff10 .delay (10000,10000,10000) L_0x246ff10/d; -L_0x246fff0/d .functor NAND 1, L_0x246fbf0, L_0x246fd30, L_0x246fe20, L_0x246ff10; -L_0x246fff0 .delay (10000,10000,10000) L_0x246fff0/d; -v0x243c410_0 .net "S0", 0 0, L_0x24702c0; 1 drivers -v0x243c4d0_0 .net "S1", 0 0, L_0x24703f0; 1 drivers -v0x243c570_0 .net "in0", 0 0, L_0x2470580; 1 drivers -v0x243c610_0 .net "in1", 0 0, L_0x2470730; 1 drivers -v0x243c690_0 .net "in2", 0 0, L_0x24707d0; 1 drivers -v0x243c730_0 .net "in3", 0 0, L_0x2470870; 1 drivers -v0x243c810_0 .net "nS0", 0 0, L_0x246fa60; 1 drivers -v0x243c8b0_0 .net "nS1", 0 0, L_0x246fb50; 1 drivers -v0x243c950_0 .net "out", 0 0, L_0x246fff0; 1 drivers -v0x243c9f0_0 .net "out0", 0 0, L_0x246fbf0; 1 drivers -v0x243ca90_0 .net "out1", 0 0, L_0x246fd30; 1 drivers -v0x243cb30_0 .net "out2", 0 0, L_0x246fe20; 1 drivers -v0x243cc40_0 .net "out3", 0 0, L_0x246ff10; 1 drivers -S_0x243bdb0 .scope module, "TwoMux" "TwoInMux" 3 326, 3 8, S_0x243bc40; - .timescale -9 -12; -L_0x2470520/d .functor NOT 1, L_0x2470dc0, C4<0>, C4<0>, C4<0>; -L_0x2470520 .delay (10000,10000,10000) L_0x2470520/d; -L_0x24709b0/d .functor AND 1, L_0x2470e60, L_0x2470520, C4<1>, C4<1>; -L_0x24709b0 .delay (20000,20000,20000) L_0x24709b0/d; -L_0x2470aa0/d .functor AND 1, L_0x2470fa0, L_0x2470dc0, C4<1>, C4<1>; -L_0x2470aa0 .delay (20000,20000,20000) L_0x2470aa0/d; -L_0x2470b90/d .functor OR 1, L_0x24709b0, L_0x2470aa0, C4<0>, C4<0>; -L_0x2470b90 .delay (20000,20000,20000) L_0x2470b90/d; -v0x243bea0_0 .net "S", 0 0, L_0x2470dc0; 1 drivers -v0x243bf40_0 .net "in0", 0 0, L_0x2470e60; 1 drivers -v0x243bfe0_0 .net "in1", 0 0, L_0x2470fa0; 1 drivers -v0x243c080_0 .net "nS", 0 0, L_0x2470520; 1 drivers -v0x243c100_0 .net "out0", 0 0, L_0x24709b0; 1 drivers -v0x243c1a0_0 .net "out1", 0 0, L_0x2470aa0; 1 drivers -v0x243c280_0 .net "outfinal", 0 0, L_0x2470b90; 1 drivers -S_0x243a0c0 .scope generate, "muxbits[2]" "muxbits[2]" 3 322, 3 322, S_0x23d85b0; - .timescale -9 -12; -P_0x2439008 .param/l "i" 3 322, +C4<010>; -L_0x2473520/d .functor OR 1, L_0x2473d20, L_0x24740a0, C4<0>, C4<0>; -L_0x2473520 .delay (20000,20000,20000) L_0x2473520/d; -v0x243bae0_0 .net *"_s15", 0 0, L_0x2473d20; 1 drivers -v0x243bba0_0 .net *"_s16", 0 0, L_0x24740a0; 1 drivers -S_0x243b160 .scope module, "ZeroMux" "FourInMux" 3 324, 3 24, S_0x243a0c0; - .timescale -9 -12; -L_0x24714c0/d .functor NOT 1, L_0x24713c0, C4<0>, C4<0>, C4<0>; -L_0x24714c0 .delay (10000,10000,10000) L_0x24714c0/d; -L_0x24715b0/d .functor NOT 1, L_0x245f370, C4<0>, C4<0>, C4<0>; -L_0x24715b0 .delay (10000,10000,10000) L_0x24715b0/d; -L_0x2471650/d .functor NAND 1, L_0x24714c0, L_0x24715b0, L_0x2471d00, C4<1>; -L_0x2471650 .delay (10000,10000,10000) L_0x2471650/d; -L_0x2471790/d .functor NAND 1, L_0x24713c0, L_0x24715b0, L_0x245f570, C4<1>; -L_0x2471790 .delay (10000,10000,10000) L_0x2471790/d; -L_0x2471880/d .functor NAND 1, L_0x24714c0, L_0x245f370, L_0x245f4a0, C4<1>; -L_0x2471880 .delay (10000,10000,10000) L_0x2471880/d; -L_0x2471970/d .functor NAND 1, L_0x24713c0, L_0x245f370, L_0x2472660, C4<1>; -L_0x2471970 .delay (10000,10000,10000) L_0x2471970/d; -L_0x2471a50/d .functor NAND 1, L_0x2471650, L_0x2471790, L_0x2471880, L_0x2471970; -L_0x2471a50 .delay (10000,10000,10000) L_0x2471a50/d; -v0x243b250_0 .net "S0", 0 0, L_0x24713c0; 1 drivers -v0x243b310_0 .net "S1", 0 0, L_0x245f370; 1 drivers -v0x243b3b0_0 .net "in0", 0 0, L_0x2471d00; 1 drivers -v0x243b450_0 .net "in1", 0 0, L_0x245f570; 1 drivers -v0x243b4d0_0 .net "in2", 0 0, L_0x245f4a0; 1 drivers -v0x243b570_0 .net "in3", 0 0, L_0x2472660; 1 drivers -v0x243b610_0 .net "nS0", 0 0, L_0x24714c0; 1 drivers -v0x243b6b0_0 .net "nS1", 0 0, L_0x24715b0; 1 drivers -v0x243b750_0 .net "out", 0 0, L_0x2471a50; 1 drivers -v0x243b7f0_0 .net "out0", 0 0, L_0x2471650; 1 drivers -v0x243b890_0 .net "out1", 0 0, L_0x2471790; 1 drivers -v0x243b930_0 .net "out2", 0 0, L_0x2471880; 1 drivers -v0x243ba40_0 .net "out3", 0 0, L_0x2471970; 1 drivers -S_0x243a7a0 .scope module, "OneMux" "FourInMux" 3 325, 3 24, S_0x243a0c0; - .timescale -9 -12; -L_0x245f610/d .functor NOT 1, L_0x2472f70, C4<0>, C4<0>, C4<0>; -L_0x245f610 .delay (10000,10000,10000) L_0x245f610/d; -L_0x24727f0/d .functor NOT 1, L_0x2472700, C4<0>, C4<0>, C4<0>; -L_0x24727f0 .delay (10000,10000,10000) L_0x24727f0/d; -L_0x2472890/d .functor NAND 1, L_0x245f610, L_0x24727f0, L_0x2473230, C4<1>; -L_0x2472890 .delay (10000,10000,10000) L_0x2472890/d; -L_0x24729d0/d .functor NAND 1, L_0x2472f70, L_0x24727f0, L_0x24730a0, C4<1>; -L_0x24729d0 .delay (10000,10000,10000) L_0x24729d0/d; -L_0x2472ac0/d .functor NAND 1, L_0x245f610, L_0x2472700, L_0x24733e0, C4<1>; -L_0x2472ac0 .delay (10000,10000,10000) L_0x2472ac0/d; -L_0x2472bb0/d .functor NAND 1, L_0x2472f70, L_0x2472700, L_0x24732d0, C4<1>; -L_0x2472bb0 .delay (10000,10000,10000) L_0x2472bb0/d; -L_0x2472cc0/d .functor NAND 1, L_0x2472890, L_0x24729d0, L_0x2472ac0, L_0x2472bb0; -L_0x2472cc0 .delay (10000,10000,10000) L_0x2472cc0/d; -v0x243a890_0 .net "S0", 0 0, L_0x2472f70; 1 drivers -v0x243a950_0 .net "S1", 0 0, L_0x2472700; 1 drivers -v0x243a9f0_0 .net "in0", 0 0, L_0x2473230; 1 drivers -v0x243aa90_0 .net "in1", 0 0, L_0x24730a0; 1 drivers -v0x243ab10_0 .net "in2", 0 0, L_0x24733e0; 1 drivers -v0x243abb0_0 .net "in3", 0 0, L_0x24732d0; 1 drivers -v0x243ac90_0 .net "nS0", 0 0, L_0x245f610; 1 drivers -v0x243ad30_0 .net "nS1", 0 0, L_0x24727f0; 1 drivers -v0x243add0_0 .net "out", 0 0, L_0x2472cc0; 1 drivers -v0x243ae70_0 .net "out0", 0 0, L_0x2472890; 1 drivers -v0x243af10_0 .net "out1", 0 0, L_0x24729d0; 1 drivers -v0x243afb0_0 .net "out2", 0 0, L_0x2472ac0; 1 drivers -v0x243b0c0_0 .net "out3", 0 0, L_0x2472bb0; 1 drivers -S_0x243a230 .scope module, "TwoMux" "TwoInMux" 3 326, 3 8, S_0x243a0c0; - .timescale -9 -12; -L_0x2473370/d .functor NOT 1, L_0x2473480, C4<0>, C4<0>, C4<0>; -L_0x2473370 .delay (10000,10000,10000) L_0x2473370/d; -L_0x2473630/d .functor AND 1, L_0x2473bb0, L_0x2473370, C4<1>, C4<1>; -L_0x2473630 .delay (20000,20000,20000) L_0x2473630/d; -L_0x2473720/d .functor AND 1, L_0x2473a80, L_0x2473480, C4<1>, C4<1>; -L_0x2473720 .delay (20000,20000,20000) L_0x2473720/d; -L_0x2473810/d .functor OR 1, L_0x2473630, L_0x2473720, C4<0>, C4<0>; -L_0x2473810 .delay (20000,20000,20000) L_0x2473810/d; -v0x243a320_0 .net "S", 0 0, L_0x2473480; 1 drivers -v0x243a3c0_0 .net "in0", 0 0, L_0x2473bb0; 1 drivers -v0x243a460_0 .net "in1", 0 0, L_0x2473a80; 1 drivers -v0x243a500_0 .net "nS", 0 0, L_0x2473370; 1 drivers -v0x243a580_0 .net "out0", 0 0, L_0x2473630; 1 drivers -v0x243a620_0 .net "out1", 0 0, L_0x2473720; 1 drivers -v0x243a700_0 .net "outfinal", 0 0, L_0x2473810; 1 drivers -S_0x2389b20 .scope generate, "muxbits[3]" "muxbits[3]" 3 322, 3 322, S_0x23d85b0; - .timescale -9 -12; -P_0x23a5c28 .param/l "i" 3 322, +C4<011>; -L_0x2476790/d .functor OR 1, L_0x2476b10, L_0x2476920, C4<0>, C4<0>; -L_0x2476790 .delay (20000,20000,20000) L_0x2476790/d; -v0x2439f60_0 .net *"_s15", 0 0, L_0x2476b10; 1 drivers -v0x243a020_0 .net *"_s16", 0 0, L_0x2476920; 1 drivers -S_0x24395e0 .scope module, "ZeroMux" "FourInMux" 3 324, 3 24, S_0x2389b20; - .timescale -9 -12; -L_0x2473f50/d .functor NOT 1, L_0x2474a80, C4<0>, C4<0>, C4<0>; -L_0x2473f50 .delay (10000,10000,10000) L_0x2473f50/d; -L_0x2474040/d .functor NOT 1, L_0x2474140, C4<0>, C4<0>, C4<0>; -L_0x2474040 .delay (10000,10000,10000) L_0x2474040/d; -L_0x24742e0/d .functor NAND 1, L_0x2473f50, L_0x2474040, L_0x2474d20, C4<1>; -L_0x24742e0 .delay (10000,10000,10000) L_0x24742e0/d; -L_0x2474420/d .functor NAND 1, L_0x2474a80, L_0x2474040, L_0x2466c90, C4<1>; -L_0x2474420 .delay (10000,10000,10000) L_0x2474420/d; -L_0x2474510/d .functor NAND 1, L_0x2473f50, L_0x2474140, L_0x2474bb0, C4<1>; -L_0x2474510 .delay (10000,10000,10000) L_0x2474510/d; -L_0x2474660/d .functor NAND 1, L_0x2474a80, L_0x2474140, L_0x2475160, C4<1>; -L_0x2474660 .delay (10000,10000,10000) L_0x2474660/d; -L_0x24747d0/d .functor NAND 1, L_0x24742e0, L_0x2474420, L_0x2474510, L_0x2474660; -L_0x24747d0 .delay (10000,10000,10000) L_0x24747d0/d; -v0x24396d0_0 .net "S0", 0 0, L_0x2474a80; 1 drivers -v0x2439790_0 .net "S1", 0 0, L_0x2474140; 1 drivers -v0x2439830_0 .net "in0", 0 0, L_0x2474d20; 1 drivers -v0x24398d0_0 .net "in1", 0 0, L_0x2466c90; 1 drivers -v0x2439950_0 .net "in2", 0 0, L_0x2474bb0; 1 drivers -v0x24399f0_0 .net "in3", 0 0, L_0x2475160; 1 drivers -v0x2439a90_0 .net "nS0", 0 0, L_0x2473f50; 1 drivers -v0x2439b30_0 .net "nS1", 0 0, L_0x2474040; 1 drivers -v0x2439bd0_0 .net "out", 0 0, L_0x24747d0; 1 drivers -v0x2439c70_0 .net "out0", 0 0, L_0x24742e0; 1 drivers -v0x2439d10_0 .net "out1", 0 0, L_0x2474420; 1 drivers -v0x2439db0_0 .net "out2", 0 0, L_0x2474510; 1 drivers -v0x2439ec0_0 .net "out3", 0 0, L_0x2474660; 1 drivers -S_0x2438b70 .scope module, "OneMux" "FourInMux" 3 325, 3 24, S_0x2389b20; - .timescale -9 -12; -L_0x2474ca0/d .functor NOT 1, L_0x2474fd0, C4<0>, C4<0>, C4<0>; -L_0x2474ca0 .delay (10000,10000,10000) L_0x2474ca0/d; -L_0x2475290/d .functor NOT 1, L_0x2475c10, C4<0>, C4<0>, C4<0>; -L_0x2475290 .delay (10000,10000,10000) L_0x2475290/d; -L_0x2475330/d .functor NAND 1, L_0x2474ca0, L_0x2475290, L_0x2475a70, C4<1>; -L_0x2475330 .delay (10000,10000,10000) L_0x2475330/d; -L_0x2475470/d .functor NAND 1, L_0x2474fd0, L_0x2475290, L_0x2475b10, C4<1>; -L_0x2475470 .delay (10000,10000,10000) L_0x2475470/d; -L_0x2475560/d .functor NAND 1, L_0x2474ca0, L_0x2475c10, L_0x2475f00, C4<1>; -L_0x2475560 .delay (10000,10000,10000) L_0x2475560/d; -L_0x2475650/d .functor NAND 1, L_0x2474fd0, L_0x2475c10, L_0x2475fa0, C4<1>; -L_0x2475650 .delay (10000,10000,10000) L_0x2475650/d; -L_0x24757c0/d .functor NAND 1, L_0x2475330, L_0x2475470, L_0x2475560, L_0x2475650; -L_0x24757c0 .delay (10000,10000,10000) L_0x24757c0/d; -v0x2438c60_0 .net "S0", 0 0, L_0x2474fd0; 1 drivers -v0x2438d20_0 .net "S1", 0 0, L_0x2475c10; 1 drivers -v0x2438dc0_0 .net "in0", 0 0, L_0x2475a70; 1 drivers -v0x2438e60_0 .net "in1", 0 0, L_0x2475b10; 1 drivers -v0x2438ee0_0 .net "in2", 0 0, L_0x2475f00; 1 drivers -v0x2438f80_0 .net "in3", 0 0, L_0x2475fa0; 1 drivers -v0x2439060_0 .net "nS0", 0 0, L_0x2474ca0; 1 drivers -v0x2439100_0 .net "nS1", 0 0, L_0x2475290; 1 drivers -v0x24391f0_0 .net "out", 0 0, L_0x24757c0; 1 drivers -v0x2439290_0 .net "out0", 0 0, L_0x2475330; 1 drivers -v0x2439390_0 .net "out1", 0 0, L_0x2475470; 1 drivers -v0x2439430_0 .net "out2", 0 0, L_0x2475560; 1 drivers -v0x2439540_0 .net "out3", 0 0, L_0x2475650; 1 drivers -S_0x23cef60 .scope module, "TwoMux" "TwoInMux" 3 326, 3 8, S_0x2389b20; - .timescale -9 -12; -L_0x246f8b0/d .functor NOT 1, L_0x2476650, C4<0>, C4<0>, C4<0>; -L_0x246f8b0 .delay (10000,10000,10000) L_0x246f8b0/d; -L_0x2475d40/d .functor AND 1, L_0x2476250, L_0x246f8b0, C4<1>, C4<1>; -L_0x2475d40 .delay (20000,20000,20000) L_0x2475d40/d; -L_0x2475e30/d .functor AND 1, L_0x2476340, L_0x2476650, C4<1>, C4<1>; -L_0x2475e30 .delay (20000,20000,20000) L_0x2475e30/d; -L_0x2476470/d .functor OR 1, L_0x2475d40, L_0x2475e30, C4<0>, C4<0>; -L_0x2476470 .delay (20000,20000,20000) L_0x2476470/d; -v0x232ba40_0 .net "S", 0 0, L_0x2476650; 1 drivers -v0x2438760_0 .net "in0", 0 0, L_0x2476250; 1 drivers -v0x2438800_0 .net "in1", 0 0, L_0x2476340; 1 drivers -v0x24388a0_0 .net "nS", 0 0, L_0x246f8b0; 1 drivers -v0x2438950_0 .net "out0", 0 0, L_0x2475d40; 1 drivers -v0x24389f0_0 .net "out1", 0 0, L_0x2475e30; 1 drivers -v0x2438ad0_0 .net "outfinal", 0 0, L_0x2476470; 1 drivers - .scope S_0x23b34d0; +S_0x96f1c0 .scope module, "test32Adder" "test32Adder" 2 126; + .timescale -9 -12; +P_0x8a8438 .param/l "size" 2 127, +C4<0100>; +v0xa38650_0 .var "A", 3 0; +RS_0x7ffb33a70098/0/0 .resolv tri, L_0xa3a560, L_0xa3c1f0, L_0xa3de90, L_0xa3fea0; +RS_0x7ffb33a70098/0/4 .resolv tri, L_0xa65ad0, L_0xa67820, L_0xa69740, L_0xa6be60; +RS_0x7ffb33a70098 .resolv tri, RS_0x7ffb33a70098/0/0, RS_0x7ffb33a70098/0/4, C4, C4; +v0xa386d0_0 .net8 "AddSubSLTSum", 3 0, RS_0x7ffb33a70098; 8 drivers +v0xa38750_0 .net "AllZeros", 0 0, L_0xa77250; 1 drivers +RS_0x7ffb33a6ee38/0/0 .resolv tri, L_0xa4bac0, L_0xa4c570, L_0xa4cfe0, L_0xa4da40; +RS_0x7ffb33a6ee38/0/4 .resolv tri, L_0xa6d7c0, L_0xa6e230, L_0xa6eca0, L_0xa6f800; +RS_0x7ffb33a6ee38 .resolv tri, RS_0x7ffb33a6ee38/0/0, RS_0x7ffb33a6ee38/0/4, C4, C4; +v0xa387d0_0 .net8 "AndNandOut", 3 0, RS_0x7ffb33a6ee38; 8 drivers +v0xa38850_0 .var "B", 3 0; +v0xa388d0_0 .var "Command", 2 0; +RS_0x7ffb33a71f88 .resolv tri, L_0xa54a70, L_0xa573c0, L_0xa59ee0, L_0xa766c0; +v0xa38950_0 .net8 "OneBitFinalOut", 3 0, RS_0x7ffb33a71f88; 4 drivers +RS_0x7ffb33a6e748/0/0 .resolv tri, L_0xa4ee00, L_0xa50140, L_0xa51440, L_0xa52730; +RS_0x7ffb33a6e748/0/4 .resolv tri, L_0xa70bc0, L_0xa71ec0, L_0xa731c0, L_0xa744b0; +RS_0x7ffb33a6e748 .resolv tri, RS_0x7ffb33a6e748/0/0, RS_0x7ffb33a6e748/0/4, C4, C4; +v0xa389d0_0 .net8 "OrNorXorOut", 3 0, RS_0x7ffb33a6e748; 8 drivers +RS_0x7ffb33a71c58/0/0 .resolv tri, L_0xa43020, L_0xa45330, L_0xa47b60, L_0xa4b110; +RS_0x7ffb33a71c58/0/4 .resolv tri, L_0xa5c560, L_0xa5e700, L_0xa60980, L_0xa64010; +RS_0x7ffb33a71c58 .resolv tri, RS_0x7ffb33a71c58/0/0, RS_0x7ffb33a71c58/0/4, C4, C4; +v0xa38a50_0 .net8 "SLTSum", 3 0, RS_0x7ffb33a71c58; 8 drivers +RS_0x7ffb33a70188 .resolv tri, L_0xa40f00, L_0xa4abf0, L_0xa63a00, L_0xa6cee0; +v0xa38ad0_0 .net8 "SLTflag", 0 0, RS_0x7ffb33a70188; 4 drivers +RS_0x7ffb33a71fb8 .resolv tri, L_0xa54f20, L_0xa57890, L_0xa5a020, L_0xa76980; +v0xa38b50_0 .net8 "ZeroFlag", 3 0, RS_0x7ffb33a71fb8; 4 drivers +v0xa38c00_0 .var "carryin", 3 0; +RS_0x7ffb33a703c8 .resolv tri, L_0xa40170, L_0xa371a0, L_0xa62700, L_0xa6c130; +v0xa38c80_0 .net8 "carryout", 0 0, RS_0x7ffb33a703c8; 4 drivers +RS_0x7ffb33a70488 .resolv tri, L_0xa3ff40, L_0xa4a230, L_0xa63050, L_0xa6bfb0; +v0xa38d00_0 .net8 "overflow", 0 0, RS_0x7ffb33a70488; 4 drivers +RS_0x7ffb33a704b8/0/0 .resolv tri, L_0xa39e20, L_0xa3ba20, L_0xa3d760, L_0xa3f7a0; +RS_0x7ffb33a704b8/0/4 .resolv tri, L_0xa421c0, L_0xa44520, L_0xa455c0, L_0xa48340; +RS_0x7ffb33a704b8/0/8 .resolv tri, L_0xa5b660, L_0xa5d970, L_0xa5e990, L_0xa61160; +RS_0x7ffb33a704b8/0/12 .resolv tri, L_0xa65390, L_0xa67120, L_0xa68d90, L_0xa6b7f0; +RS_0x7ffb33a704b8 .resolv tri, RS_0x7ffb33a704b8/0/0, RS_0x7ffb33a704b8/0/4, RS_0x7ffb33a704b8/0/8, RS_0x7ffb33a704b8/0/12; +v0xa38e00_0 .net8 "subtract", 3 0, RS_0x7ffb33a704b8; 16 drivers +S_0xa31580 .scope module, "trial" "AddSubSLT32" 2 146, 3 205, S_0x96f1c0; + .timescale -9 -12; +P_0xa2fcc8 .param/l "size" 3 237, +C4<0100>; +L_0xa3e0f0/d .functor NOT 1, L_0xa3e1e0, C4<0>, C4<0>, C4<0>; +L_0xa3e0f0 .delay (10000,10000,10000) L_0xa3e0f0/d; +L_0xa3e280/d .functor AND 1, L_0xa3e3c0, L_0xa3e020, L_0xa3e0f0, C4<1>; +L_0xa3e280 .delay (20000,20000,20000) L_0xa3e280/d; +L_0xa40170/d .functor OR 1, L_0xa40260, C4<0>, C4<0>, C4<0>; +L_0xa40170 .delay (20000,20000,20000) L_0xa40170/d; +L_0xa3ff40/d .functor XOR 1, RS_0x7ffb33a703c8, L_0xa40540, C4<0>, C4<0>; +L_0xa3ff40 .delay (40000,40000,40000) L_0xa3ff40/d; +L_0xa405e0/d .functor NOT 1, RS_0x7ffb33a70488, C4<0>, C4<0>, C4<0>; +L_0xa405e0 .delay (10000,10000,10000) L_0xa405e0/d; +L_0xa406d0/d .functor NOT 1, L_0xa407b0, C4<0>, C4<0>, C4<0>; +L_0xa406d0 .delay (10000,10000,10000) L_0xa406d0/d; +L_0xa3a600/d .functor AND 1, L_0xa405e0, L_0xa40aa0, C4<1>, C4<1>; +L_0xa3a600 .delay (20000,20000,20000) L_0xa3a600/d; +L_0xa40b40/d .functor AND 1, RS_0x7ffb33a70488, L_0xa406d0, C4<1>, C4<1>; +L_0xa40b40 .delay (20000,20000,20000) L_0xa40b40/d; +L_0xa40cb0/d .functor AND 1, L_0xa3a600, L_0xa3e280, C4<1>, C4<1>; +L_0xa40cb0 .delay (20000,20000,20000) L_0xa40cb0/d; +L_0xa40db0/d .functor AND 1, L_0xa40b40, L_0xa3e280, C4<1>, C4<1>; +L_0xa40db0 .delay (20000,20000,20000) L_0xa40db0/d; +L_0xa40f00/d .functor OR 1, L_0xa40cb0, L_0xa40db0, C4<0>, C4<0>; +L_0xa40f00 .delay (20000,20000,20000) L_0xa40f00/d; +v0xa37070_0 .net "A", 3 0, v0xa38650_0; 1 drivers +v0xa1fc00_0 .alias "AddSubSLTSum", 3 0, v0xa386d0_0; +v0xa37220_0 .net "B", 3 0, v0xa38850_0; 1 drivers +RS_0x7ffb33a760f8 .resolv tri, L_0xa39d30, L_0xa3b8d0, L_0xa3d5d0, L_0xa3e460; +v0xa1fe90_0 .net8 "CarryoutWire", 3 0, RS_0x7ffb33a760f8; 4 drivers +v0xa373b0_0 .net "Command", 2 0, v0xa388d0_0; 1 drivers +RS_0x7ffb33a76128 .resolv tri, L_0xa39c40, L_0xa3b7e0, L_0xa3d4e0, L_0xa3f570; +v0xa37430_0 .net8 "NewVal", 3 0, RS_0x7ffb33a76128; 4 drivers +v0xa374d0_0 .net "Res0OF1", 0 0, L_0xa40b40; 1 drivers +v0xa37570_0 .net "Res1OF0", 0 0, L_0xa3a600; 1 drivers +v0xa37660_0 .alias "SLTflag", 0 0, v0xa38ad0_0; +v0xa202d0_0 .net "SLTflag0", 0 0, L_0xa40cb0; 1 drivers +v0xa37810_0 .net "SLTflag1", 0 0, L_0xa40db0; 1 drivers +v0xa378b0_0 .net "SLTon", 0 0, L_0xa3e280; 1 drivers +v0xa379c0_0 .net *"_s37", 0 0, L_0xa3e1e0; 1 drivers +v0xa37a60_0 .net *"_s39", 0 0, L_0xa3e3c0; 1 drivers +v0xa37b80_0 .net *"_s41", 0 0, L_0xa3e020; 1 drivers +v0xa37c20_0 .net *"_s61", 0 0, L_0xa40260; 1 drivers +v0xa37ae0_0 .net/s *"_s62", 0 0, C4<0>; 1 drivers +v0xa37d70_0 .net *"_s65", 0 0, L_0xa40540; 1 drivers +v0xa37e90_0 .net *"_s67", 0 0, L_0xa407b0; 1 drivers +v0xa37f10_0 .net *"_s69", 0 0, L_0xa40aa0; 1 drivers +v0xa37df0_0 .net "carryin", 3 0, v0xa38c00_0; 1 drivers +v0xa380d0_0 .alias "carryout", 0 0, v0xa38c80_0; +v0xa38210_0 .net "nAddSubSLTSum", 0 0, L_0xa406d0; 1 drivers +v0xa38290_0 .net "nCmd2", 0 0, L_0xa3e0f0; 1 drivers +v0xa38150_0 .net "nOF", 0 0, L_0xa405e0; 1 drivers +v0xa383e0_0 .alias "overflow", 0 0, v0xa38d00_0; +v0xa38540_0 .alias "subtract", 3 0, v0xa38e00_0; +L_0xa39c40 .part/pv L_0xa39730, 1, 1, 4; +L_0xa39d30 .part/pv L_0xa39ae0, 1, 1, 4; +L_0xa39e20 .part/pv L_0xa39430, 1, 1, 4; +L_0xa39f10 .part v0xa38650_0, 1, 1; +L_0xa39fb0 .part v0xa38850_0, 1, 1; +L_0xa3a0e0 .part RS_0x7ffb33a760f8, 0, 1; +L_0xa3a560 .part/pv L_0xa3a420, 1, 1, 4; +L_0xa3a690 .part RS_0x7ffb33a76128, 1, 1; +L_0xa3b7e0 .part/pv L_0xa3b350, 2, 1, 4; +L_0xa3b8d0 .part/pv L_0xa3b6a0, 2, 1, 4; +L_0xa3ba20 .part/pv L_0xa3b080, 2, 1, 4; +L_0xa3bac0 .part v0xa38650_0, 2, 1; +L_0xa3bbd0 .part v0xa38850_0, 2, 1; +L_0xa3bd00 .part RS_0x7ffb33a760f8, 1, 1; +L_0xa3c1f0 .part/pv L_0xa3c100, 2, 1, 4; +L_0xa3c290 .part RS_0x7ffb33a76128, 2, 1; +L_0xa3d4e0 .part/pv L_0xa3d030, 3, 1, 4; +L_0xa3d5d0 .part/pv L_0xa3d380, 3, 1, 4; +L_0xa3d760 .part/pv L_0xa3cd60, 3, 1, 4; +L_0xa3d910 .part v0xa38650_0, 3, 1; +L_0xa3d6c0 .part v0xa38850_0, 3, 1; +L_0xa3da60 .part RS_0x7ffb33a760f8, 2, 1; +L_0xa3de90 .part/pv L_0xa3dd50, 3, 1, 4; +L_0xa3df30 .part RS_0x7ffb33a76128, 3, 1; +L_0xa3e1e0 .part v0xa388d0_0, 2, 1; +L_0xa3e3c0 .part v0xa388d0_0, 0, 1; +L_0xa3e020 .part v0xa388d0_0, 1, 1; +L_0xa3f570 .part/pv L_0xa3f0a0, 0, 1, 4; +L_0xa3e460 .part/pv L_0xa3f410, 0, 1, 4; +L_0xa3f7a0 .part/pv L_0xa3edd0, 0, 1, 4; +L_0xa3f660 .part v0xa38650_0, 0, 1; +L_0xa3f990 .part v0xa38850_0, 0, 1; +L_0xa3f890 .part RS_0x7ffb33a704b8, 0, 1; +L_0xa3fea0 .part/pv L_0xa3fd60, 0, 1, 4; +L_0xa3fac0 .part RS_0x7ffb33a76128, 0, 1; +L_0xa40260 .part RS_0x7ffb33a760f8, 3, 1; +L_0xa40540 .part RS_0x7ffb33a760f8, 2, 1; +L_0xa407b0 .part RS_0x7ffb33a70098, 3, 1; +L_0xa40aa0 .part RS_0x7ffb33a70098, 3, 1; +S_0xa36050 .scope module, "attempt2" "MiddleAddSubSLT" 3 233, 3 89, S_0xa31580; + .timescale -9 -12; +L_0xa3e590/d .functor NOT 1, L_0xa3f990, C4<0>, C4<0>, C4<0>; +L_0xa3e590 .delay (10000,10000,10000) L_0xa3e590/d; +L_0xa3ec70/d .functor NOT 1, L_0xa3ed30, C4<0>, C4<0>, C4<0>; +L_0xa3ec70 .delay (10000,10000,10000) L_0xa3ec70/d; +L_0xa3edd0/d .functor AND 1, L_0xa3ef10, L_0xa3ec70, C4<1>, C4<1>; +L_0xa3edd0 .delay (20000,20000,20000) L_0xa3edd0/d; +L_0xa3efb0/d .functor XOR 1, L_0xa3f660, L_0xa3ea00, C4<0>, C4<0>; +L_0xa3efb0 .delay (40000,40000,40000) L_0xa3efb0/d; +L_0xa3f0a0/d .functor XOR 1, L_0xa3efb0, L_0xa3f890, C4<0>, C4<0>; +L_0xa3f0a0 .delay (40000,40000,40000) L_0xa3f0a0/d; +L_0xa3f190/d .functor AND 1, L_0xa3f660, L_0xa3ea00, C4<1>, C4<1>; +L_0xa3f190 .delay (20000,20000,20000) L_0xa3f190/d; +L_0xa3f300/d .functor AND 1, L_0xa3efb0, L_0xa3f890, C4<1>, C4<1>; +L_0xa3f300 .delay (20000,20000,20000) L_0xa3f300/d; +L_0xa3f410/d .functor OR 1, L_0xa3f190, L_0xa3f300, C4<0>, C4<0>; +L_0xa3f410 .delay (20000,20000,20000) L_0xa3f410/d; +v0xa366d0_0 .net "A", 0 0, L_0xa3f660; 1 drivers +v0xa36790_0 .net "AandB", 0 0, L_0xa3f190; 1 drivers +v0xa36830_0 .net "AddSubSLTSum", 0 0, L_0xa3f0a0; 1 drivers +v0xa368d0_0 .net "AxorB", 0 0, L_0xa3efb0; 1 drivers +v0xa36950_0 .net "B", 0 0, L_0xa3f990; 1 drivers +v0xa36a00_0 .net "BornB", 0 0, L_0xa3ea00; 1 drivers +v0xa36ac0_0 .net "CINandAxorB", 0 0, L_0xa3f300; 1 drivers +v0xa36b40_0 .alias "Command", 2 0, v0xa373b0_0; +v0xa36bc0_0 .net *"_s3", 0 0, L_0xa3ed30; 1 drivers +v0xa36c40_0 .net *"_s5", 0 0, L_0xa3ef10; 1 drivers +v0xa36ce0_0 .net "carryin", 0 0, L_0xa3f890; 1 drivers +v0xa36d80_0 .net "carryout", 0 0, L_0xa3f410; 1 drivers +v0xa36e20_0 .net "nB", 0 0, L_0xa3e590; 1 drivers +v0xa36ed0_0 .net "nCmd2", 0 0, L_0xa3ec70; 1 drivers +v0xa36fd0_0 .net "subtract", 0 0, L_0xa3edd0; 1 drivers +L_0xa3ebd0 .part v0xa388d0_0, 0, 1; +L_0xa3ed30 .part v0xa388d0_0, 2, 1; +L_0xa3ef10 .part v0xa388d0_0, 0, 1; +S_0xa36140 .scope module, "mux0" "TwoInMux" 3 105, 3 8, S_0xa36050; + .timescale -9 -12; +L_0xa3e720/d .functor NOT 1, L_0xa3ebd0, C4<0>, C4<0>, C4<0>; +L_0xa3e720 .delay (10000,10000,10000) L_0xa3e720/d; +L_0xa3e7e0/d .functor AND 1, L_0xa3f990, L_0xa3e720, C4<1>, C4<1>; +L_0xa3e7e0 .delay (20000,20000,20000) L_0xa3e7e0/d; +L_0xa3e8f0/d .functor AND 1, L_0xa3e590, L_0xa3ebd0, C4<1>, C4<1>; +L_0xa3e8f0 .delay (20000,20000,20000) L_0xa3e8f0/d; +L_0xa3ea00/d .functor OR 1, L_0xa3e7e0, L_0xa3e8f0, C4<0>, C4<0>; +L_0xa3ea00 .delay (20000,20000,20000) L_0xa3ea00/d; +v0xa36230_0 .net "S", 0 0, L_0xa3ebd0; 1 drivers +v0xa362f0_0 .alias "in0", 0 0, v0xa36950_0; +v0xa36390_0 .alias "in1", 0 0, v0xa36e20_0; +v0xa36430_0 .net "nS", 0 0, L_0xa3e720; 1 drivers +v0xa364b0_0 .net "out0", 0 0, L_0xa3e7e0; 1 drivers +v0xa36550_0 .net "out1", 0 0, L_0xa3e8f0; 1 drivers +v0xa36630_0 .alias "outfinal", 0 0, v0xa36a00_0; +S_0xa35af0 .scope module, "setSLTres" "TwoInMux" 3 234, 3 8, S_0xa31580; + .timescale -9 -12; +L_0xa3f930/d .functor NOT 1, L_0xa3e280, C4<0>, C4<0>, C4<0>; +L_0xa3f930 .delay (10000,10000,10000) L_0xa3f930/d; +L_0xa3fbd0/d .functor AND 1, L_0xa3fac0, L_0xa3f930, C4<1>, C4<1>; +L_0xa3fbd0 .delay (20000,20000,20000) L_0xa3fbd0/d; +L_0xa3fcc0/d .functor AND 1, C4<0>, L_0xa3e280, C4<1>, C4<1>; +L_0xa3fcc0 .delay (20000,20000,20000) L_0xa3fcc0/d; +L_0xa3fd60/d .functor OR 1, L_0xa3fbd0, L_0xa3fcc0, C4<0>, C4<0>; +L_0xa3fd60 .delay (20000,20000,20000) L_0xa3fd60/d; +v0xa35be0_0 .alias "S", 0 0, v0xa378b0_0; +v0xa35c80_0 .net "in0", 0 0, L_0xa3fac0; 1 drivers +v0xa35d20_0 .net "in1", 0 0, C4<0>; 1 drivers +v0xa35dc0_0 .net "nS", 0 0, L_0xa3f930; 1 drivers +v0xa35e70_0 .net "out0", 0 0, L_0xa3fbd0; 1 drivers +v0xa35f10_0 .net "out1", 0 0, L_0xa3fcc0; 1 drivers +v0xa35fb0_0 .net "outfinal", 0 0, L_0xa3fd60; 1 drivers +S_0xa343c0 .scope generate, "addbits[1]" "addbits[1]" 3 239, 3 239, S_0xa31580; + .timescale -9 -12; +P_0xa33dd8 .param/l "i" 3 239, +C4<01>; +S_0xa34a80 .scope module, "attempt" "MiddleAddSubSLT" 3 241, 3 89, S_0xa343c0; + .timescale -9 -12; +L_0xa2a820/d .functor NOT 1, L_0xa39fb0, C4<0>, C4<0>, C4<0>; +L_0xa2a820 .delay (10000,10000,10000) L_0xa2a820/d; +L_0xa392d0/d .functor NOT 1, L_0xa39390, C4<0>, C4<0>, C4<0>; +L_0xa392d0 .delay (10000,10000,10000) L_0xa392d0/d; +L_0xa39430/d .functor AND 1, L_0xa39570, L_0xa392d0, C4<1>, C4<1>; +L_0xa39430 .delay (20000,20000,20000) L_0xa39430/d; +L_0xa39610/d .functor XOR 1, L_0xa39f10, L_0xa390b0, C4<0>, C4<0>; +L_0xa39610 .delay (40000,40000,40000) L_0xa39610/d; +L_0xa39730/d .functor XOR 1, L_0xa39610, L_0xa3a0e0, C4<0>, C4<0>; +L_0xa39730 .delay (40000,40000,40000) L_0xa39730/d; +L_0xa39850/d .functor AND 1, L_0xa39f10, L_0xa390b0, C4<1>, C4<1>; +L_0xa39850 .delay (20000,20000,20000) L_0xa39850/d; +L_0xa399f0/d .functor AND 1, L_0xa39610, L_0xa3a0e0, C4<1>, C4<1>; +L_0xa399f0 .delay (20000,20000,20000) L_0xa399f0/d; +L_0xa39ae0/d .functor OR 1, L_0xa39850, L_0xa399f0, C4<0>, C4<0>; +L_0xa39ae0 .delay (20000,20000,20000) L_0xa39ae0/d; +v0xa35100_0 .net "A", 0 0, L_0xa39f10; 1 drivers +v0xa351c0_0 .net "AandB", 0 0, L_0xa39850; 1 drivers +v0xa35260_0 .net "AddSubSLTSum", 0 0, L_0xa39730; 1 drivers +v0xa35300_0 .net "AxorB", 0 0, L_0xa39610; 1 drivers +v0xa35380_0 .net "B", 0 0, L_0xa39fb0; 1 drivers +v0xa35430_0 .net "BornB", 0 0, L_0xa390b0; 1 drivers +v0xa354f0_0 .net "CINandAxorB", 0 0, L_0xa399f0; 1 drivers +v0xa35570_0 .alias "Command", 2 0, v0xa373b0_0; +v0xa35640_0 .net *"_s3", 0 0, L_0xa39390; 1 drivers +v0xa356c0_0 .net *"_s5", 0 0, L_0xa39570; 1 drivers +v0xa35760_0 .net "carryin", 0 0, L_0xa3a0e0; 1 drivers +v0xa35800_0 .net "carryout", 0 0, L_0xa39ae0; 1 drivers +v0xa358a0_0 .net "nB", 0 0, L_0xa2a820; 1 drivers +v0xa35950_0 .net "nCmd2", 0 0, L_0xa392d0; 1 drivers +v0xa35a50_0 .net "subtract", 0 0, L_0xa39430; 1 drivers +L_0xa39230 .part v0xa388d0_0, 0, 1; +L_0xa39390 .part v0xa388d0_0, 2, 1; +L_0xa39570 .part v0xa388d0_0, 0, 1; +S_0xa34b70 .scope module, "mux0" "TwoInMux" 3 105, 3 8, S_0xa34a80; + .timescale -9 -12; +L_0xa38e80/d .functor NOT 1, L_0xa39230, C4<0>, C4<0>, C4<0>; +L_0xa38e80 .delay (10000,10000,10000) L_0xa38e80/d; +L_0xa38f00/d .functor AND 1, L_0xa39fb0, L_0xa38e80, C4<1>, C4<1>; +L_0xa38f00 .delay (20000,20000,20000) L_0xa38f00/d; +L_0xa38ff0/d .functor AND 1, L_0xa2a820, L_0xa39230, C4<1>, C4<1>; +L_0xa38ff0 .delay (20000,20000,20000) L_0xa38ff0/d; +L_0xa390b0/d .functor OR 1, L_0xa38f00, L_0xa38ff0, C4<0>, C4<0>; +L_0xa390b0 .delay (20000,20000,20000) L_0xa390b0/d; +v0xa34c60_0 .net "S", 0 0, L_0xa39230; 1 drivers +v0xa34d20_0 .alias "in0", 0 0, v0xa35380_0; +v0xa34dc0_0 .alias "in1", 0 0, v0xa358a0_0; +v0xa34e60_0 .net "nS", 0 0, L_0xa38e80; 1 drivers +v0xa34ee0_0 .net "out0", 0 0, L_0xa38f00; 1 drivers +v0xa34f80_0 .net "out1", 0 0, L_0xa38ff0; 1 drivers +v0xa35060_0 .alias "outfinal", 0 0, v0xa35430_0; +S_0xa34530 .scope module, "setSLTres" "TwoInMux" 3 242, 3 8, S_0xa343c0; + .timescale -9 -12; +L_0xa3a180/d .functor NOT 1, L_0xa3e280, C4<0>, C4<0>, C4<0>; +L_0xa3a180 .delay (10000,10000,10000) L_0xa3a180/d; +L_0xa3a270/d .functor AND 1, L_0xa3a690, L_0xa3a180, C4<1>, C4<1>; +L_0xa3a270 .delay (20000,20000,20000) L_0xa3a270/d; +L_0xa3a380/d .functor AND 1, C4<0>, L_0xa3e280, C4<1>, C4<1>; +L_0xa3a380 .delay (20000,20000,20000) L_0xa3a380/d; +L_0xa3a420/d .functor OR 1, L_0xa3a270, L_0xa3a380, C4<0>, C4<0>; +L_0xa3a420 .delay (20000,20000,20000) L_0xa3a420/d; +v0xa34620_0 .alias "S", 0 0, v0xa378b0_0; +v0xa346a0_0 .net "in0", 0 0, L_0xa3a690; 1 drivers +v0xa34740_0 .net "in1", 0 0, C4<0>; 1 drivers +v0xa347e0_0 .net "nS", 0 0, L_0xa3a180; 1 drivers +v0xa34860_0 .net "out0", 0 0, L_0xa3a270; 1 drivers +v0xa34900_0 .net "out1", 0 0, L_0xa3a380; 1 drivers +v0xa349e0_0 .net "outfinal", 0 0, L_0xa3a420; 1 drivers +S_0xa32ca0 .scope generate, "addbits[2]" "addbits[2]" 3 239, 3 239, S_0xa31580; + .timescale -9 -12; +P_0xa326b8 .param/l "i" 3 239, +C4<010>; +S_0xa333a0 .scope module, "attempt" "MiddleAddSubSLT" 3 241, 3 89, S_0xa32ca0; + .timescale -9 -12; +L_0xa3a820/d .functor NOT 1, L_0xa3bbd0, C4<0>, C4<0>, C4<0>; +L_0xa3a820 .delay (10000,10000,10000) L_0xa3a820/d; +L_0xa3af60/d .functor NOT 1, L_0xa3afe0, C4<0>, C4<0>, C4<0>; +L_0xa3af60 .delay (10000,10000,10000) L_0xa3af60/d; +L_0xa3b080/d .functor AND 1, L_0xa3b1c0, L_0xa3af60, C4<1>, C4<1>; +L_0xa3b080 .delay (20000,20000,20000) L_0xa3b080/d; +L_0xa3b260/d .functor XOR 1, L_0xa3bac0, L_0xa3acf0, C4<0>, C4<0>; +L_0xa3b260 .delay (40000,40000,40000) L_0xa3b260/d; +L_0xa3b350/d .functor XOR 1, L_0xa3b260, L_0xa3bd00, C4<0>, C4<0>; +L_0xa3b350 .delay (40000,40000,40000) L_0xa3b350/d; +L_0xa3b440/d .functor AND 1, L_0xa3bac0, L_0xa3acf0, C4<1>, C4<1>; +L_0xa3b440 .delay (20000,20000,20000) L_0xa3b440/d; +L_0xa3b5b0/d .functor AND 1, L_0xa3b260, L_0xa3bd00, C4<1>, C4<1>; +L_0xa3b5b0 .delay (20000,20000,20000) L_0xa3b5b0/d; +L_0xa3b6a0/d .functor OR 1, L_0xa3b440, L_0xa3b5b0, C4<0>, C4<0>; +L_0xa3b6a0 .delay (20000,20000,20000) L_0xa3b6a0/d; +v0xa33a20_0 .net "A", 0 0, L_0xa3bac0; 1 drivers +v0xa33ae0_0 .net "AandB", 0 0, L_0xa3b440; 1 drivers +v0xa33b80_0 .net "AddSubSLTSum", 0 0, L_0xa3b350; 1 drivers +v0xa33c20_0 .net "AxorB", 0 0, L_0xa3b260; 1 drivers +v0xa33ca0_0 .net "B", 0 0, L_0xa3bbd0; 1 drivers +v0xa33d50_0 .net "BornB", 0 0, L_0xa3acf0; 1 drivers +v0xa33e10_0 .net "CINandAxorB", 0 0, L_0xa3b5b0; 1 drivers +v0xa33e90_0 .alias "Command", 2 0, v0xa373b0_0; +v0xa33f10_0 .net *"_s3", 0 0, L_0xa3afe0; 1 drivers +v0xa33f90_0 .net *"_s5", 0 0, L_0xa3b1c0; 1 drivers +v0xa34030_0 .net "carryin", 0 0, L_0xa3bd00; 1 drivers +v0xa340d0_0 .net "carryout", 0 0, L_0xa3b6a0; 1 drivers +v0xa34170_0 .net "nB", 0 0, L_0xa3a820; 1 drivers +v0xa34220_0 .net "nCmd2", 0 0, L_0xa3af60; 1 drivers +v0xa34320_0 .net "subtract", 0 0, L_0xa3b080; 1 drivers +L_0xa3aec0 .part v0xa388d0_0, 0, 1; +L_0xa3afe0 .part v0xa388d0_0, 2, 1; +L_0xa3b1c0 .part v0xa388d0_0, 0, 1; +S_0xa33490 .scope module, "mux0" "TwoInMux" 3 105, 3 8, S_0xa333a0; + .timescale -9 -12; +L_0xa3aa10/d .functor NOT 1, L_0xa3aec0, C4<0>, C4<0>, C4<0>; +L_0xa3aa10 .delay (10000,10000,10000) L_0xa3aa10/d; +L_0xa3aad0/d .functor AND 1, L_0xa3bbd0, L_0xa3aa10, C4<1>, C4<1>; +L_0xa3aad0 .delay (20000,20000,20000) L_0xa3aad0/d; +L_0xa3abe0/d .functor AND 1, L_0xa3a820, L_0xa3aec0, C4<1>, C4<1>; +L_0xa3abe0 .delay (20000,20000,20000) L_0xa3abe0/d; +L_0xa3acf0/d .functor OR 1, L_0xa3aad0, L_0xa3abe0, C4<0>, C4<0>; +L_0xa3acf0 .delay (20000,20000,20000) L_0xa3acf0/d; +v0xa33580_0 .net "S", 0 0, L_0xa3aec0; 1 drivers +v0xa33640_0 .alias "in0", 0 0, v0xa33ca0_0; +v0xa336e0_0 .alias "in1", 0 0, v0xa34170_0; +v0xa33780_0 .net "nS", 0 0, L_0xa3aa10; 1 drivers +v0xa33800_0 .net "out0", 0 0, L_0xa3aad0; 1 drivers +v0xa338a0_0 .net "out1", 0 0, L_0xa3abe0; 1 drivers +v0xa33980_0 .alias "outfinal", 0 0, v0xa33d50_0; +S_0xa32e10 .scope module, "setSLTres" "TwoInMux" 3 242, 3 8, S_0xa32ca0; + .timescale -9 -12; +L_0xa3b9c0/d .functor NOT 1, L_0xa3e280, C4<0>, C4<0>, C4<0>; +L_0xa3b9c0 .delay (10000,10000,10000) L_0xa3b9c0/d; +L_0xa3bed0/d .functor AND 1, L_0xa3c290, L_0xa3b9c0, C4<1>, C4<1>; +L_0xa3bed0 .delay (20000,20000,20000) L_0xa3bed0/d; +L_0xa3bf90/d .functor AND 1, C4<0>, L_0xa3e280, C4<1>, C4<1>; +L_0xa3bf90 .delay (20000,20000,20000) L_0xa3bf90/d; +L_0xa3c100/d .functor OR 1, L_0xa3bed0, L_0xa3bf90, C4<0>, C4<0>; +L_0xa3c100 .delay (20000,20000,20000) L_0xa3c100/d; +v0xa32f00_0 .alias "S", 0 0, v0xa378b0_0; +v0xa32fb0_0 .net "in0", 0 0, L_0xa3c290; 1 drivers +v0xa33030_0 .net "in1", 0 0, C4<0>; 1 drivers +v0xa330d0_0 .net "nS", 0 0, L_0xa3b9c0; 1 drivers +v0xa33180_0 .net "out0", 0 0, L_0xa3bed0; 1 drivers +v0xa33220_0 .net "out1", 0 0, L_0xa3bf90; 1 drivers +v0xa33300_0 .net "outfinal", 0 0, L_0xa3c100; 1 drivers +S_0xa31670 .scope generate, "addbits[3]" "addbits[3]" 3 239, 3 239, S_0xa31580; + .timescale -9 -12; +P_0xa31358 .param/l "i" 3 239, +C4<011>; +S_0xa31cb0 .scope module, "attempt" "MiddleAddSubSLT" 3 241, 3 89, S_0xa31670; + .timescale -9 -12; +L_0xa3c4e0/d .functor NOT 1, L_0xa3d6c0, C4<0>, C4<0>, C4<0>; +L_0xa3c4e0 .delay (10000,10000,10000) L_0xa3c4e0/d; +L_0xa3cc00/d .functor NOT 1, L_0xa3ccc0, C4<0>, C4<0>, C4<0>; +L_0xa3cc00 .delay (10000,10000,10000) L_0xa3cc00/d; +L_0xa3cd60/d .functor AND 1, L_0xa3cea0, L_0xa3cc00, C4<1>, C4<1>; +L_0xa3cd60 .delay (20000,20000,20000) L_0xa3cd60/d; +L_0xa3cf40/d .functor XOR 1, L_0xa3d910, L_0xa3c990, C4<0>, C4<0>; +L_0xa3cf40 .delay (40000,40000,40000) L_0xa3cf40/d; +L_0xa3d030/d .functor XOR 1, L_0xa3cf40, L_0xa3da60, C4<0>, C4<0>; +L_0xa3d030 .delay (40000,40000,40000) L_0xa3d030/d; +L_0xa3d120/d .functor AND 1, L_0xa3d910, L_0xa3c990, C4<1>, C4<1>; +L_0xa3d120 .delay (20000,20000,20000) L_0xa3d120/d; +L_0xa3d290/d .functor AND 1, L_0xa3cf40, L_0xa3da60, C4<1>, C4<1>; +L_0xa3d290 .delay (20000,20000,20000) L_0xa3d290/d; +L_0xa3d380/d .functor OR 1, L_0xa3d120, L_0xa3d290, C4<0>, C4<0>; +L_0xa3d380 .delay (20000,20000,20000) L_0xa3d380/d; +v0xa32330_0 .net "A", 0 0, L_0xa3d910; 1 drivers +v0xa323f0_0 .net "AandB", 0 0, L_0xa3d120; 1 drivers +v0xa32490_0 .net "AddSubSLTSum", 0 0, L_0xa3d030; 1 drivers +v0xa32530_0 .net "AxorB", 0 0, L_0xa3cf40; 1 drivers +v0xa325b0_0 .net "B", 0 0, L_0xa3d6c0; 1 drivers +v0xa32630_0 .net "BornB", 0 0, L_0xa3c990; 1 drivers +v0xa326f0_0 .net "CINandAxorB", 0 0, L_0xa3d290; 1 drivers +v0xa32770_0 .alias "Command", 2 0, v0xa373b0_0; +v0xa327f0_0 .net *"_s3", 0 0, L_0xa3ccc0; 1 drivers +v0xa32870_0 .net *"_s5", 0 0, L_0xa3cea0; 1 drivers +v0xa32910_0 .net "carryin", 0 0, L_0xa3da60; 1 drivers +v0xa329b0_0 .net "carryout", 0 0, L_0xa3d380; 1 drivers +v0xa32a50_0 .net "nB", 0 0, L_0xa3c4e0; 1 drivers +v0xa32b00_0 .net "nCmd2", 0 0, L_0xa3cc00; 1 drivers +v0xa32c00_0 .net "subtract", 0 0, L_0xa3cd60; 1 drivers +L_0xa3cb60 .part v0xa388d0_0, 0, 1; +L_0xa3ccc0 .part v0xa388d0_0, 2, 1; +L_0xa3cea0 .part v0xa388d0_0, 0, 1; +S_0xa31da0 .scope module, "mux0" "TwoInMux" 3 105, 3 8, S_0xa31cb0; + .timescale -9 -12; +L_0xa3c6b0/d .functor NOT 1, L_0xa3cb60, C4<0>, C4<0>, C4<0>; +L_0xa3c6b0 .delay (10000,10000,10000) L_0xa3c6b0/d; +L_0xa3c770/d .functor AND 1, L_0xa3d6c0, L_0xa3c6b0, C4<1>, C4<1>; +L_0xa3c770 .delay (20000,20000,20000) L_0xa3c770/d; +L_0xa3c880/d .functor AND 1, L_0xa3c4e0, L_0xa3cb60, C4<1>, C4<1>; +L_0xa3c880 .delay (20000,20000,20000) L_0xa3c880/d; +L_0xa3c990/d .functor OR 1, L_0xa3c770, L_0xa3c880, C4<0>, C4<0>; +L_0xa3c990 .delay (20000,20000,20000) L_0xa3c990/d; +v0xa31e90_0 .net "S", 0 0, L_0xa3cb60; 1 drivers +v0xa31f50_0 .alias "in0", 0 0, v0xa325b0_0; +v0xa31ff0_0 .alias "in1", 0 0, v0xa32a50_0; +v0xa32090_0 .net "nS", 0 0, L_0xa3c6b0; 1 drivers +v0xa32110_0 .net "out0", 0 0, L_0xa3c770; 1 drivers +v0xa321b0_0 .net "out1", 0 0, L_0xa3c880; 1 drivers +v0xa32290_0 .alias "outfinal", 0 0, v0xa32630_0; +S_0xa31760 .scope module, "setSLTres" "TwoInMux" 3 242, 3 8, S_0xa31670; + .timescale -9 -12; +L_0xa3d9b0/d .functor NOT 1, L_0xa3e280, C4<0>, C4<0>, C4<0>; +L_0xa3d9b0 .delay (10000,10000,10000) L_0xa3d9b0/d; +L_0xa3dbc0/d .functor AND 1, L_0xa3df30, L_0xa3d9b0, C4<1>, C4<1>; +L_0xa3dbc0 .delay (20000,20000,20000) L_0xa3dbc0/d; +L_0xa3dcb0/d .functor AND 1, C4<0>, L_0xa3e280, C4<1>, C4<1>; +L_0xa3dcb0 .delay (20000,20000,20000) L_0xa3dcb0/d; +L_0xa3dd50/d .functor OR 1, L_0xa3dbc0, L_0xa3dcb0, C4<0>, C4<0>; +L_0xa3dd50 .delay (20000,20000,20000) L_0xa3dd50/d; +v0xa31850_0 .alias "S", 0 0, v0xa378b0_0; +v0xa318d0_0 .net "in0", 0 0, L_0xa3df30; 1 drivers +v0xa31970_0 .net "in1", 0 0, C4<0>; 1 drivers +v0xa31a10_0 .net "nS", 0 0, L_0xa3d9b0; 1 drivers +v0xa31a90_0 .net "out0", 0 0, L_0xa3dbc0; 1 drivers +v0xa31b30_0 .net "out1", 0 0, L_0xa3dcb0; 1 drivers +v0xa31c10_0 .net "outfinal", 0 0, L_0xa3dd50; 1 drivers +S_0xa28d90 .scope module, "test" "SLT32" 2 148, 3 273, S_0x96f1c0; + .timescale -9 -12; +P_0xa28e88 .param/l "size" 3 305, +C4<0100>; +L_0xa44d20/d .functor NOT 1, L_0xa47fa0, C4<0>, C4<0>, C4<0>; +L_0xa44d20 .delay (10000,10000,10000) L_0xa44d20/d; +L_0xa47e00/d .functor AND 1, L_0xa481b0, L_0xa48250, L_0xa44d20, C4<1>; +L_0xa47e00 .delay (20000,20000,20000) L_0xa47e00/d; +L_0xa371a0/d .functor OR 1, L_0xa4a020, C4<0>, C4<0>, C4<0>; +L_0xa371a0 .delay (20000,20000,20000) L_0xa371a0/d; +L_0xa4a230/d .functor XOR 1, RS_0x7ffb33a703c8, L_0xa4a2d0, C4<0>, C4<0>; +L_0xa4a230 .delay (40000,40000,40000) L_0xa4a230/d; +L_0xa49eb0/d .functor NOT 1, RS_0x7ffb33a70488, C4<0>, C4<0>, C4<0>; +L_0xa49eb0 .delay (10000,10000,10000) L_0xa49eb0/d; +L_0xa49fc0/d .functor NOT 1, L_0xa4a570, C4<0>, C4<0>, C4<0>; +L_0xa49fc0 .delay (10000,10000,10000) L_0xa49fc0/d; +L_0xa4a610/d .functor AND 1, L_0xa49eb0, L_0xa4a770, C4<1>, C4<1>; +L_0xa4a610 .delay (20000,20000,20000) L_0xa4a610/d; +L_0xa4a370/d .functor AND 1, RS_0x7ffb33a70488, L_0xa49fc0, C4<1>, C4<1>; +L_0xa4a370 .delay (20000,20000,20000) L_0xa4a370/d; +L_0xa4a9a0/d .functor AND 1, L_0xa4a610, L_0xa47e00, C4<1>, C4<1>; +L_0xa4a9a0 .delay (20000,20000,20000) L_0xa4a9a0/d; +L_0xa4aaa0/d .functor AND 1, L_0xa4a370, L_0xa47e00, C4<1>, C4<1>; +L_0xa4aaa0 .delay (20000,20000,20000) L_0xa4aaa0/d; +L_0xa4abf0/d .functor OR 1, L_0xa4a9a0, L_0xa4aaa0, C4<0>, C4<0>; +L_0xa4abf0 .delay (20000,20000,20000) L_0xa4abf0/d; +v0xa302b0_0 .alias "A", 3 0, v0xa37070_0; +RS_0x7ffb33a74b68 .resolv tri, L_0xa42980, L_0xa44c80, L_0xa47550, L_0xa49c10; +v0xa30350_0 .net8 "AddSubSLTSum", 3 0, RS_0x7ffb33a74b68; 4 drivers +v0xa303f0_0 .alias "B", 3 0, v0xa37220_0; +RS_0x7ffb33a74b98 .resolv tri, L_0xa420d0, L_0xa44430, L_0xa46a00, L_0xa493c0; +v0xa30470_0 .net8 "CarryoutWire", 3 0, RS_0x7ffb33a74b98; 4 drivers +v0xa30520_0 .alias "Command", 2 0, v0xa373b0_0; +RS_0x7ffb33a74bc8 .resolv tri, L_0xa41fe0, L_0xa44340, L_0xa46910, L_0xa492d0; +v0xa305a0_0 .net8 "NewVal", 3 0, RS_0x7ffb33a74bc8; 4 drivers +v0xa30640_0 .net "Res0OF1", 0 0, L_0xa4a370; 1 drivers +v0xa306e0_0 .net "Res1OF0", 0 0, L_0xa4a610; 1 drivers +v0xa30780_0 .alias "SLTSum", 3 0, v0xa38a50_0; +v0xa30800_0 .alias "SLTflag", 0 0, v0xa38ad0_0; +v0xa30880_0 .net "SLTflag0", 0 0, L_0xa4a9a0; 1 drivers +v0xa30920_0 .net "SLTflag1", 0 0, L_0xa4aaa0; 1 drivers +v0xa309c0_0 .net "SLTon", 0 0, L_0xa47e00; 1 drivers +v0xa30a40_0 .net *"_s49", 0 0, L_0xa47fa0; 1 drivers +v0xa30b60_0 .net *"_s51", 0 0, L_0xa481b0; 1 drivers +v0xa30c00_0 .net *"_s53", 0 0, L_0xa48250; 1 drivers +v0xa30ac0_0 .net *"_s73", 0 0, L_0xa4a020; 1 drivers +v0xa30d50_0 .net/s *"_s74", 0 0, C4<0>; 1 drivers +v0xa30e70_0 .net *"_s77", 0 0, L_0xa4a2d0; 1 drivers +v0xa30ef0_0 .net *"_s79", 0 0, L_0xa4a570; 1 drivers +v0xa30dd0_0 .net *"_s81", 0 0, L_0xa4a770; 1 drivers +v0xa31020_0 .alias "carryin", 3 0, v0xa37df0_0; +v0xa30f70_0 .alias "carryout", 0 0, v0xa38c80_0; +v0xa31160_0 .net "nAddSubSLTSum", 0 0, L_0xa49fc0; 1 drivers +v0xa310a0_0 .net "nCmd2", 0 0, L_0xa44d20; 1 drivers +v0xa312b0_0 .net "nOF", 0 0, L_0xa49eb0; 1 drivers +v0xa311e0_0 .alias "overflow", 0 0, v0xa38d00_0; +v0xa31410_0 .alias "subtract", 3 0, v0xa38e00_0; +L_0xa41fe0 .part/pv L_0xa41b30, 1, 1, 4; +L_0xa420d0 .part/pv L_0xa41e80, 1, 1, 4; +L_0xa421c0 .part/pv L_0xa41860, 1, 1, 4; +L_0xa422b0 .part v0xa38650_0, 1, 1; +L_0xa42350 .part v0xa38850_0, 1, 1; +L_0xa42480 .part RS_0x7ffb33a74b98, 0, 1; +L_0xa42980 .part/pv L_0xa42840, 1, 1, 4; +L_0xa42a20 .part RS_0x7ffb33a74bc8, 1, 1; +L_0xa43020 .part/pv L_0xa42ee0, 1, 1, 4; +L_0xa43150 .part RS_0x7ffb33a74b68, 1, 1; +L_0xa432a0 .part RS_0x7ffb33a74b68, 1, 1; +L_0xa44340 .part/pv L_0xa43e90, 2, 1, 4; +L_0xa44430 .part/pv L_0xa441e0, 2, 1, 4; +L_0xa44520 .part/pv L_0xa43bc0, 2, 1, 4; +L_0xa44610 .part v0xa38650_0, 2, 1; +L_0xa446b0 .part v0xa38850_0, 2, 1; +L_0xa44870 .part RS_0x7ffb33a74b98, 1, 1; +L_0xa44c80 .part/pv L_0xa44b40, 2, 1, 4; +L_0xa44e50 .part RS_0x7ffb33a74bc8, 2, 1; +L_0xa45330 .part/pv L_0xa451f0, 2, 1, 4; +L_0xa44db0 .part RS_0x7ffb33a74b68, 2, 1; +L_0xa454d0 .part RS_0x7ffb33a74b68, 2, 1; +L_0xa46910 .part/pv L_0xa2c640, 3, 1, 4; +L_0xa46a00 .part/pv L_0xa467d0, 3, 1, 4; +L_0xa455c0 .part/pv L_0xa3bb60, 3, 1, 4; +L_0xa46c10 .part v0xa38650_0, 3, 1; +L_0xa46af0 .part v0xa38850_0, 3, 1; +L_0xa372a0 .part RS_0x7ffb33a74b98, 2, 1; +L_0xa47550 .part/pv L_0xa47410, 3, 1, 4; +L_0xa475f0 .part RS_0x7ffb33a74bc8, 3, 1; +L_0xa47b60 .part/pv L_0xa47a20, 3, 1, 4; +L_0xa47c00 .part RS_0x7ffb33a74b68, 3, 1; +L_0xa476e0 .part RS_0x7ffb33a74b68, 3, 1; +L_0xa47fa0 .part v0xa388d0_0, 2, 1; +L_0xa481b0 .part v0xa388d0_0, 0, 1; +L_0xa48250 .part v0xa388d0_0, 1, 1; +L_0xa492d0 .part/pv L_0xa48e20, 0, 1, 4; +L_0xa493c0 .part/pv L_0xa49170, 0, 1, 4; +L_0xa48340 .part/pv L_0xa48b50, 0, 1, 4; +L_0xa495f0 .part v0xa38650_0, 0, 1; +L_0xa494b0 .part v0xa38850_0, 0, 1; +L_0xa497e0 .part RS_0x7ffb33a704b8, 0, 1; +L_0xa49c10 .part/pv L_0xa49ad0, 0, 1, 4; +L_0xa49cb0 .part RS_0x7ffb33a74bc8, 0, 1; +L_0xa4a020 .part RS_0x7ffb33a74b98, 3, 1; +L_0xa4a2d0 .part RS_0x7ffb33a74b98, 2, 1; +L_0xa4a570 .part RS_0x7ffb33a74b68, 3, 1; +L_0xa4a770 .part RS_0x7ffb33a74b68, 3, 1; +L_0xa4b110 .part/pv L_0xa4afb0, 0, 1, 4; +L_0xa4b1b0 .part RS_0x7ffb33a74b68, 0, 1; +S_0xa2f290 .scope module, "attempt2" "MiddleAddSubSLT" 3 300, 3 89, S_0xa28d90; + .timescale -9 -12; +L_0xa48040/d .functor NOT 1, L_0xa494b0, C4<0>, C4<0>, C4<0>; +L_0xa48040 .delay (10000,10000,10000) L_0xa48040/d; +L_0xa489f0/d .functor NOT 1, L_0xa48ab0, C4<0>, C4<0>, C4<0>; +L_0xa489f0 .delay (10000,10000,10000) L_0xa489f0/d; +L_0xa48b50/d .functor AND 1, L_0xa48c90, L_0xa489f0, C4<1>, C4<1>; +L_0xa48b50 .delay (20000,20000,20000) L_0xa48b50/d; +L_0xa48d30/d .functor XOR 1, L_0xa495f0, L_0xa48780, C4<0>, C4<0>; +L_0xa48d30 .delay (40000,40000,40000) L_0xa48d30/d; +L_0xa48e20/d .functor XOR 1, L_0xa48d30, L_0xa497e0, C4<0>, C4<0>; +L_0xa48e20 .delay (40000,40000,40000) L_0xa48e20/d; +L_0xa48f10/d .functor AND 1, L_0xa495f0, L_0xa48780, C4<1>, C4<1>; +L_0xa48f10 .delay (20000,20000,20000) L_0xa48f10/d; +L_0xa49080/d .functor AND 1, L_0xa48d30, L_0xa497e0, C4<1>, C4<1>; +L_0xa49080 .delay (20000,20000,20000) L_0xa49080/d; +L_0xa49170/d .functor OR 1, L_0xa48f10, L_0xa49080, C4<0>, C4<0>; +L_0xa49170 .delay (20000,20000,20000) L_0xa49170/d; +v0xa2f910_0 .net "A", 0 0, L_0xa495f0; 1 drivers +v0xa2f9d0_0 .net "AandB", 0 0, L_0xa48f10; 1 drivers +v0xa2fa70_0 .net "AddSubSLTSum", 0 0, L_0xa48e20; 1 drivers +v0xa2fb10_0 .net "AxorB", 0 0, L_0xa48d30; 1 drivers +v0xa2fb90_0 .net "B", 0 0, L_0xa494b0; 1 drivers +v0xa2fc40_0 .net "BornB", 0 0, L_0xa48780; 1 drivers +v0xa2fd00_0 .net "CINandAxorB", 0 0, L_0xa49080; 1 drivers +v0xa2fd80_0 .alias "Command", 2 0, v0xa373b0_0; +v0xa2fe00_0 .net *"_s3", 0 0, L_0xa48ab0; 1 drivers +v0xa2fe80_0 .net *"_s5", 0 0, L_0xa48c90; 1 drivers +v0xa2ff20_0 .net "carryin", 0 0, L_0xa497e0; 1 drivers +v0xa2ffc0_0 .net "carryout", 0 0, L_0xa49170; 1 drivers +v0xa30060_0 .net "nB", 0 0, L_0xa48040; 1 drivers +v0xa30110_0 .net "nCmd2", 0 0, L_0xa489f0; 1 drivers +v0xa30210_0 .net "subtract", 0 0, L_0xa48b50; 1 drivers +L_0xa48950 .part v0xa388d0_0, 0, 1; +L_0xa48ab0 .part v0xa388d0_0, 2, 1; +L_0xa48c90 .part v0xa388d0_0, 0, 1; +S_0xa2f380 .scope module, "mux0" "TwoInMux" 3 105, 3 8, S_0xa2f290; + .timescale -9 -12; +L_0xa48500/d .functor NOT 1, L_0xa48950, C4<0>, C4<0>, C4<0>; +L_0xa48500 .delay (10000,10000,10000) L_0xa48500/d; +L_0xa485a0/d .functor AND 1, L_0xa494b0, L_0xa48500, C4<1>, C4<1>; +L_0xa485a0 .delay (20000,20000,20000) L_0xa485a0/d; +L_0xa48690/d .functor AND 1, L_0xa48040, L_0xa48950, C4<1>, C4<1>; +L_0xa48690 .delay (20000,20000,20000) L_0xa48690/d; +L_0xa48780/d .functor OR 1, L_0xa485a0, L_0xa48690, C4<0>, C4<0>; +L_0xa48780 .delay (20000,20000,20000) L_0xa48780/d; +v0xa2f470_0 .net "S", 0 0, L_0xa48950; 1 drivers +v0xa2f530_0 .alias "in0", 0 0, v0xa2fb90_0; +v0xa2f5d0_0 .alias "in1", 0 0, v0xa30060_0; +v0xa2f670_0 .net "nS", 0 0, L_0xa48500; 1 drivers +v0xa2f6f0_0 .net "out0", 0 0, L_0xa485a0; 1 drivers +v0xa2f790_0 .net "out1", 0 0, L_0xa48690; 1 drivers +v0xa2f870_0 .alias "outfinal", 0 0, v0xa2fc40_0; +S_0xa2ed20 .scope module, "setSLTres" "TwoInMux" 3 301, 3 8, S_0xa28d90; + .timescale -9 -12; +L_0xa49690/d .functor NOT 1, L_0xa47e00, C4<0>, C4<0>, C4<0>; +L_0xa49690 .delay (10000,10000,10000) L_0xa49690/d; +L_0xa49730/d .functor AND 1, L_0xa49cb0, L_0xa49690, C4<1>, C4<1>; +L_0xa49730 .delay (20000,20000,20000) L_0xa49730/d; +L_0xa49a30/d .functor AND 1, C4<0>, L_0xa47e00, C4<1>, C4<1>; +L_0xa49a30 .delay (20000,20000,20000) L_0xa49a30/d; +L_0xa49ad0/d .functor OR 1, L_0xa49730, L_0xa49a30, C4<0>, C4<0>; +L_0xa49ad0 .delay (20000,20000,20000) L_0xa49ad0/d; +v0xa2ee10_0 .alias "S", 0 0, v0xa309c0_0; +v0xa2eeb0_0 .net "in0", 0 0, L_0xa49cb0; 1 drivers +v0xa2ef50_0 .net "in1", 0 0, C4<0>; 1 drivers +v0xa2eff0_0 .net "nS", 0 0, L_0xa49690; 1 drivers +v0xa2f070_0 .net "out0", 0 0, L_0xa49730; 1 drivers +v0xa2f110_0 .net "out1", 0 0, L_0xa49a30; 1 drivers +v0xa2f1f0_0 .net "outfinal", 0 0, L_0xa49ad0; 1 drivers +S_0xa2e7e0 .scope module, "FinalSLT" "TwoInMux" 3 328, 3 8, S_0xa28d90; + .timescale -9 -12; +L_0xa4ad20/d .functor NOT 1, RS_0x7ffb33a70188, C4<0>, C4<0>, C4<0>; +L_0xa4ad20 .delay (10000,10000,10000) L_0xa4ad20/d; +L_0xa4ae00/d .functor AND 1, L_0xa4b1b0, L_0xa4ad20, C4<1>, C4<1>; +L_0xa4ae00 .delay (20000,20000,20000) L_0xa4ae00/d; +L_0xa4af10/d .functor AND 1, RS_0x7ffb33a70188, RS_0x7ffb33a70188, C4<1>, C4<1>; +L_0xa4af10 .delay (20000,20000,20000) L_0xa4af10/d; +L_0xa4afb0/d .functor OR 1, L_0xa4ae00, L_0xa4af10, C4<0>, C4<0>; +L_0xa4afb0 .delay (20000,20000,20000) L_0xa4afb0/d; +v0xa2e8d0_0 .alias "S", 0 0, v0xa38ad0_0; +v0xa2e970_0 .net "in0", 0 0, L_0xa4b1b0; 1 drivers +v0xa2ea10_0 .alias "in1", 0 0, v0xa38ad0_0; +v0xa2ea90_0 .net "nS", 0 0, L_0xa4ad20; 1 drivers +v0xa2eb40_0 .net "out0", 0 0, L_0xa4ae00; 1 drivers +v0xa2ebe0_0 .net "out1", 0 0, L_0xa4af10; 1 drivers +v0xa2ec80_0 .net "outfinal", 0 0, L_0xa4afb0; 1 drivers +S_0xa2cab0 .scope generate, "addbits[1]" "addbits[1]" 3 307, 3 307, S_0xa28d90; + .timescale -9 -12; +P_0xa2cba8 .param/l "i" 3 307, +C4<01>; +S_0xa2d7c0 .scope module, "attempt" "MiddleAddSubSLT" 3 309, 3 89, S_0xa2cab0; + .timescale -9 -12; +L_0xa41010/d .functor NOT 1, L_0xa42350, C4<0>, C4<0>, C4<0>; +L_0xa41010 .delay (10000,10000,10000) L_0xa41010/d; +L_0xa41700/d .functor NOT 1, L_0xa417c0, C4<0>, C4<0>, C4<0>; +L_0xa41700 .delay (10000,10000,10000) L_0xa41700/d; +L_0xa41860/d .functor AND 1, L_0xa419a0, L_0xa41700, C4<1>, C4<1>; +L_0xa41860 .delay (20000,20000,20000) L_0xa41860/d; +L_0xa41a40/d .functor XOR 1, L_0xa422b0, L_0xa41490, C4<0>, C4<0>; +L_0xa41a40 .delay (40000,40000,40000) L_0xa41a40/d; +L_0xa41b30/d .functor XOR 1, L_0xa41a40, L_0xa42480, C4<0>, C4<0>; +L_0xa41b30 .delay (40000,40000,40000) L_0xa41b30/d; +L_0xa41c20/d .functor AND 1, L_0xa422b0, L_0xa41490, C4<1>, C4<1>; +L_0xa41c20 .delay (20000,20000,20000) L_0xa41c20/d; +L_0xa41d90/d .functor AND 1, L_0xa41a40, L_0xa42480, C4<1>, C4<1>; +L_0xa41d90 .delay (20000,20000,20000) L_0xa41d90/d; +L_0xa41e80/d .functor OR 1, L_0xa41c20, L_0xa41d90, C4<0>, C4<0>; +L_0xa41e80 .delay (20000,20000,20000) L_0xa41e80/d; +v0xa2de40_0 .net "A", 0 0, L_0xa422b0; 1 drivers +v0xa2df00_0 .net "AandB", 0 0, L_0xa41c20; 1 drivers +v0xa2dfa0_0 .net "AddSubSLTSum", 0 0, L_0xa41b30; 1 drivers +v0xa2e040_0 .net "AxorB", 0 0, L_0xa41a40; 1 drivers +v0xa2e0c0_0 .net "B", 0 0, L_0xa42350; 1 drivers +v0xa2e170_0 .net "BornB", 0 0, L_0xa41490; 1 drivers +v0xa2e230_0 .net "CINandAxorB", 0 0, L_0xa41d90; 1 drivers +v0xa2e2b0_0 .alias "Command", 2 0, v0xa373b0_0; +v0xa2e330_0 .net *"_s3", 0 0, L_0xa417c0; 1 drivers +v0xa2e3b0_0 .net *"_s5", 0 0, L_0xa419a0; 1 drivers +v0xa2e450_0 .net "carryin", 0 0, L_0xa42480; 1 drivers +v0xa2e4f0_0 .net "carryout", 0 0, L_0xa41e80; 1 drivers +v0xa2e590_0 .net "nB", 0 0, L_0xa41010; 1 drivers +v0xa2e640_0 .net "nCmd2", 0 0, L_0xa41700; 1 drivers +v0xa2e740_0 .net "subtract", 0 0, L_0xa41860; 1 drivers +L_0xa41660 .part v0xa388d0_0, 0, 1; +L_0xa417c0 .part v0xa388d0_0, 2, 1; +L_0xa419a0 .part v0xa388d0_0, 0, 1; +S_0xa2d8b0 .scope module, "mux0" "TwoInMux" 3 105, 3 8, S_0xa2d7c0; + .timescale -9 -12; +L_0xa411b0/d .functor NOT 1, L_0xa41660, C4<0>, C4<0>, C4<0>; +L_0xa411b0 .delay (10000,10000,10000) L_0xa411b0/d; +L_0xa41270/d .functor AND 1, L_0xa42350, L_0xa411b0, C4<1>, C4<1>; +L_0xa41270 .delay (20000,20000,20000) L_0xa41270/d; +L_0xa41380/d .functor AND 1, L_0xa41010, L_0xa41660, C4<1>, C4<1>; +L_0xa41380 .delay (20000,20000,20000) L_0xa41380/d; +L_0xa41490/d .functor OR 1, L_0xa41270, L_0xa41380, C4<0>, C4<0>; +L_0xa41490 .delay (20000,20000,20000) L_0xa41490/d; +v0xa2d9a0_0 .net "S", 0 0, L_0xa41660; 1 drivers +v0xa2da60_0 .alias "in0", 0 0, v0xa2e0c0_0; +v0xa2db00_0 .alias "in1", 0 0, v0xa2e590_0; +v0xa2dba0_0 .net "nS", 0 0, L_0xa411b0; 1 drivers +v0xa2dc20_0 .net "out0", 0 0, L_0xa41270; 1 drivers +v0xa2dcc0_0 .net "out1", 0 0, L_0xa41380; 1 drivers +v0xa2dda0_0 .alias "outfinal", 0 0, v0xa2e170_0; +S_0xa2d250 .scope module, "setSLTres2" "TwoInMux" 3 310, 3 8, S_0xa2cab0; + .timescale -9 -12; +L_0xa42520/d .functor NOT 1, L_0xa47e00, C4<0>, C4<0>, C4<0>; +L_0xa42520 .delay (10000,10000,10000) L_0xa42520/d; +L_0xa42690/d .functor AND 1, L_0xa42a20, L_0xa42520, C4<1>, C4<1>; +L_0xa42690 .delay (20000,20000,20000) L_0xa42690/d; +L_0xa427a0/d .functor AND 1, C4<0>, L_0xa47e00, C4<1>, C4<1>; +L_0xa427a0 .delay (20000,20000,20000) L_0xa427a0/d; +L_0xa42840/d .functor OR 1, L_0xa42690, L_0xa427a0, C4<0>, C4<0>; +L_0xa42840 .delay (20000,20000,20000) L_0xa42840/d; +v0xa2d340_0 .alias "S", 0 0, v0xa309c0_0; +v0xa2d3e0_0 .net "in0", 0 0, L_0xa42a20; 1 drivers +v0xa2d480_0 .net "in1", 0 0, C4<0>; 1 drivers +v0xa2d520_0 .net "nS", 0 0, L_0xa42520; 1 drivers +v0xa2d5a0_0 .net "out0", 0 0, L_0xa42690; 1 drivers +v0xa2d640_0 .net "out1", 0 0, L_0xa427a0; 1 drivers +v0xa2d720_0 .net "outfinal", 0 0, L_0xa42840; 1 drivers +S_0xa2cc40 .scope module, "setSLTres3" "TwoInMux" 3 311, 3 8, S_0xa2cab0; + .timescale -9 -12; +L_0xa42c40/d .functor NOT 1, L_0xa47e00, C4<0>, C4<0>, C4<0>; +L_0xa42c40 .delay (10000,10000,10000) L_0xa42c40/d; +L_0xa42d30/d .functor AND 1, L_0xa43150, L_0xa42c40, C4<1>, C4<1>; +L_0xa42d30 .delay (20000,20000,20000) L_0xa42d30/d; +L_0xa42e40/d .functor AND 1, L_0xa432a0, L_0xa47e00, C4<1>, C4<1>; +L_0xa42e40 .delay (20000,20000,20000) L_0xa42e40/d; +L_0xa42ee0/d .functor OR 1, L_0xa42d30, L_0xa42e40, C4<0>, C4<0>; +L_0xa42ee0 .delay (20000,20000,20000) L_0xa42ee0/d; +v0xa2cd30_0 .alias "S", 0 0, v0xa309c0_0; +v0xa2ce40_0 .net "in0", 0 0, L_0xa43150; 1 drivers +v0xa2cee0_0 .net "in1", 0 0, L_0xa432a0; 1 drivers +v0xa2cf80_0 .net "nS", 0 0, L_0xa42c40; 1 drivers +v0xa2d030_0 .net "out0", 0 0, L_0xa42d30; 1 drivers +v0xa2d0d0_0 .net "out1", 0 0, L_0xa42e40; 1 drivers +v0xa2d1b0_0 .net "outfinal", 0 0, L_0xa42ee0; 1 drivers +S_0xa2ac30 .scope generate, "addbits[2]" "addbits[2]" 3 307, 3 307, S_0xa28d90; + .timescale -9 -12; +P_0xa2a598 .param/l "i" 3 307, +C4<010>; +S_0xa2b860 .scope module, "attempt" "MiddleAddSubSLT" 3 309, 3 89, S_0xa2ac30; + .timescale -9 -12; +L_0xa43340/d .functor NOT 1, L_0xa446b0, C4<0>, C4<0>, C4<0>; +L_0xa43340 .delay (10000,10000,10000) L_0xa43340/d; +L_0xa43a60/d .functor NOT 1, L_0xa43b20, C4<0>, C4<0>, C4<0>; +L_0xa43a60 .delay (10000,10000,10000) L_0xa43a60/d; +L_0xa43bc0/d .functor AND 1, L_0xa43d00, L_0xa43a60, C4<1>, C4<1>; +L_0xa43bc0 .delay (20000,20000,20000) L_0xa43bc0/d; +L_0xa43da0/d .functor XOR 1, L_0xa44610, L_0xa437f0, C4<0>, C4<0>; +L_0xa43da0 .delay (40000,40000,40000) L_0xa43da0/d; +L_0xa43e90/d .functor XOR 1, L_0xa43da0, L_0xa44870, C4<0>, C4<0>; +L_0xa43e90 .delay (40000,40000,40000) L_0xa43e90/d; +L_0xa43f80/d .functor AND 1, L_0xa44610, L_0xa437f0, C4<1>, C4<1>; +L_0xa43f80 .delay (20000,20000,20000) L_0xa43f80/d; +L_0xa440f0/d .functor AND 1, L_0xa43da0, L_0xa44870, C4<1>, C4<1>; +L_0xa440f0 .delay (20000,20000,20000) L_0xa440f0/d; +L_0xa441e0/d .functor OR 1, L_0xa43f80, L_0xa440f0, C4<0>, C4<0>; +L_0xa441e0 .delay (20000,20000,20000) L_0xa441e0/d; +v0xa2bee0_0 .net "A", 0 0, L_0xa44610; 1 drivers +v0xa2bfa0_0 .net "AandB", 0 0, L_0xa43f80; 1 drivers +v0xa2c040_0 .net "AddSubSLTSum", 0 0, L_0xa43e90; 1 drivers +v0xa2c0e0_0 .net "AxorB", 0 0, L_0xa43da0; 1 drivers +v0xa2c160_0 .net "B", 0 0, L_0xa446b0; 1 drivers +v0xa2c210_0 .net "BornB", 0 0, L_0xa437f0; 1 drivers +v0xa2c2d0_0 .net "CINandAxorB", 0 0, L_0xa440f0; 1 drivers +v0xa2c350_0 .alias "Command", 2 0, v0xa373b0_0; +v0xa1aac0_0 .net *"_s3", 0 0, L_0xa43b20; 1 drivers +v0xa1ab40_0 .net *"_s5", 0 0, L_0xa43d00; 1 drivers +v0xa1abe0_0 .net "carryin", 0 0, L_0xa44870; 1 drivers +v0xa2c830_0 .net "carryout", 0 0, L_0xa441e0; 1 drivers +v0xa2c8b0_0 .net "nB", 0 0, L_0xa43340; 1 drivers +v0xa2c930_0 .net "nCmd2", 0 0, L_0xa43a60; 1 drivers +v0xa2ca30_0 .net "subtract", 0 0, L_0xa43bc0; 1 drivers +L_0xa439c0 .part v0xa388d0_0, 0, 1; +L_0xa43b20 .part v0xa388d0_0, 2, 1; +L_0xa43d00 .part v0xa388d0_0, 0, 1; +S_0xa2b950 .scope module, "mux0" "TwoInMux" 3 105, 3 8, S_0xa2b860; + .timescale -9 -12; +L_0xa43510/d .functor NOT 1, L_0xa439c0, C4<0>, C4<0>, C4<0>; +L_0xa43510 .delay (10000,10000,10000) L_0xa43510/d; +L_0xa435d0/d .functor AND 1, L_0xa446b0, L_0xa43510, C4<1>, C4<1>; +L_0xa435d0 .delay (20000,20000,20000) L_0xa435d0/d; +L_0xa436e0/d .functor AND 1, L_0xa43340, L_0xa439c0, C4<1>, C4<1>; +L_0xa436e0 .delay (20000,20000,20000) L_0xa436e0/d; +L_0xa437f0/d .functor OR 1, L_0xa435d0, L_0xa436e0, C4<0>, C4<0>; +L_0xa437f0 .delay (20000,20000,20000) L_0xa437f0/d; +v0xa2ba40_0 .net "S", 0 0, L_0xa439c0; 1 drivers +v0xa2bb00_0 .alias "in0", 0 0, v0xa2c160_0; +v0xa2bba0_0 .alias "in1", 0 0, v0xa2c8b0_0; +v0xa2bc40_0 .net "nS", 0 0, L_0xa43510; 1 drivers +v0xa2bcc0_0 .net "out0", 0 0, L_0xa435d0; 1 drivers +v0xa2bd60_0 .net "out1", 0 0, L_0xa436e0; 1 drivers +v0xa2be40_0 .alias "outfinal", 0 0, v0xa2c210_0; +S_0xa2b2f0 .scope module, "setSLTres2" "TwoInMux" 3 310, 3 8, S_0xa2ac30; + .timescale -9 -12; +L_0xa43240/d .functor NOT 1, L_0xa47e00, C4<0>, C4<0>, C4<0>; +L_0xa43240 .delay (10000,10000,10000) L_0xa43240/d; +L_0xa449e0/d .functor AND 1, L_0xa44e50, L_0xa43240, C4<1>, C4<1>; +L_0xa449e0 .delay (20000,20000,20000) L_0xa449e0/d; +L_0xa44aa0/d .functor AND 1, C4<0>, L_0xa47e00, C4<1>, C4<1>; +L_0xa44aa0 .delay (20000,20000,20000) L_0xa44aa0/d; +L_0xa44b40/d .functor OR 1, L_0xa449e0, L_0xa44aa0, C4<0>, C4<0>; +L_0xa44b40 .delay (20000,20000,20000) L_0xa44b40/d; +v0xa2b3e0_0 .alias "S", 0 0, v0xa309c0_0; +v0xa2b480_0 .net "in0", 0 0, L_0xa44e50; 1 drivers +v0xa2b520_0 .net "in1", 0 0, C4<0>; 1 drivers +v0xa2b5c0_0 .net "nS", 0 0, L_0xa43240; 1 drivers +v0xa2b640_0 .net "out0", 0 0, L_0xa449e0; 1 drivers +v0xa2b6e0_0 .net "out1", 0 0, L_0xa44aa0; 1 drivers +v0xa2b7c0_0 .net "outfinal", 0 0, L_0xa44b40; 1 drivers +S_0xa2ada0 .scope module, "setSLTres3" "TwoInMux" 3 311, 3 8, S_0xa2ac30; + .timescale -9 -12; +L_0xa44f30/d .functor NOT 1, L_0xa47e00, C4<0>, C4<0>, C4<0>; +L_0xa44f30 .delay (10000,10000,10000) L_0xa44f30/d; +L_0xa45040/d .functor AND 1, L_0xa44db0, L_0xa44f30, C4<1>, C4<1>; +L_0xa45040 .delay (20000,20000,20000) L_0xa45040/d; +L_0xa45150/d .functor AND 1, L_0xa454d0, L_0xa47e00, C4<1>, C4<1>; +L_0xa45150 .delay (20000,20000,20000) L_0xa45150/d; +L_0xa451f0/d .functor OR 1, L_0xa45040, L_0xa45150, C4<0>, C4<0>; +L_0xa451f0 .delay (20000,20000,20000) L_0xa451f0/d; +v0xa2ae90_0 .alias "S", 0 0, v0xa309c0_0; +v0xa2af10_0 .net "in0", 0 0, L_0xa44db0; 1 drivers +v0xa2afb0_0 .net "in1", 0 0, L_0xa454d0; 1 drivers +v0xa2b050_0 .net "nS", 0 0, L_0xa44f30; 1 drivers +v0xa2b0d0_0 .net "out0", 0 0, L_0xa45040; 1 drivers +v0xa2b170_0 .net "out1", 0 0, L_0xa45150; 1 drivers +v0xa2b250_0 .net "outfinal", 0 0, L_0xa451f0; 1 drivers +S_0xa28f00 .scope generate, "addbits[3]" "addbits[3]" 3 307, 3 307, S_0xa28d90; + .timescale -9 -12; +P_0xa28ff8 .param/l "i" 3 307, +C4<011>; +S_0xa29b60 .scope module, "attempt" "MiddleAddSubSLT" 3 309, 3 89, S_0xa28f00; + .timescale -9 -12; +L_0xa453d0/d .functor NOT 1, L_0xa46af0, C4<0>, C4<0>, C4<0>; +L_0xa453d0 .delay (10000,10000,10000) L_0xa453d0/d; +L_0xa45cf0/d .functor NOT 1, L_0xa45db0, C4<0>, C4<0>, C4<0>; +L_0xa45cf0 .delay (10000,10000,10000) L_0xa45cf0/d; +L_0xa3bb60/d .functor AND 1, L_0xa2c4b0, L_0xa45cf0, C4<1>, C4<1>; +L_0xa3bb60 .delay (20000,20000,20000) L_0xa3bb60/d; +L_0xa2c550/d .functor XOR 1, L_0xa46c10, L_0xa45a80, C4<0>, C4<0>; +L_0xa2c550 .delay (40000,40000,40000) L_0xa2c550/d; +L_0xa2c640/d .functor XOR 1, L_0xa2c550, L_0xa372a0, C4<0>, C4<0>; +L_0xa2c640 .delay (40000,40000,40000) L_0xa2c640/d; +L_0xa2c730/d .functor AND 1, L_0xa46c10, L_0xa45a80, C4<1>, C4<1>; +L_0xa2c730 .delay (20000,20000,20000) L_0xa2c730/d; +L_0xa466e0/d .functor AND 1, L_0xa2c550, L_0xa372a0, C4<1>, C4<1>; +L_0xa466e0 .delay (20000,20000,20000) L_0xa466e0/d; +L_0xa467d0/d .functor OR 1, L_0xa2c730, L_0xa466e0, C4<0>, C4<0>; +L_0xa467d0 .delay (20000,20000,20000) L_0xa467d0/d; +v0xa2a1e0_0 .net "A", 0 0, L_0xa46c10; 1 drivers +v0xa2a2a0_0 .net "AandB", 0 0, L_0xa2c730; 1 drivers +v0xa2a340_0 .net "AddSubSLTSum", 0 0, L_0xa2c640; 1 drivers +v0xa2a3e0_0 .net "AxorB", 0 0, L_0xa2c550; 1 drivers +v0xa2a460_0 .net "B", 0 0, L_0xa46af0; 1 drivers +v0xa2a510_0 .net "BornB", 0 0, L_0xa45a80; 1 drivers +v0xa2a5d0_0 .net "CINandAxorB", 0 0, L_0xa466e0; 1 drivers +v0xa2a650_0 .alias "Command", 2 0, v0xa373b0_0; +v0xa2a720_0 .net *"_s3", 0 0, L_0xa45db0; 1 drivers +v0xa2a7a0_0 .net *"_s5", 0 0, L_0xa2c4b0; 1 drivers +v0xa2a8a0_0 .net "carryin", 0 0, L_0xa372a0; 1 drivers +v0xa2a940_0 .net "carryout", 0 0, L_0xa467d0; 1 drivers +v0xa2a9e0_0 .net "nB", 0 0, L_0xa453d0; 1 drivers +v0xa2aa90_0 .net "nCmd2", 0 0, L_0xa45cf0; 1 drivers +v0xa2ab90_0 .net "subtract", 0 0, L_0xa3bb60; 1 drivers +L_0xa45c50 .part v0xa388d0_0, 0, 1; +L_0xa45db0 .part v0xa388d0_0, 2, 1; +L_0xa2c4b0 .part v0xa388d0_0, 0, 1; +S_0xa29c50 .scope module, "mux0" "TwoInMux" 3 105, 3 8, S_0xa29b60; + .timescale -9 -12; +L_0xa457a0/d .functor NOT 1, L_0xa45c50, C4<0>, C4<0>, C4<0>; +L_0xa457a0 .delay (10000,10000,10000) L_0xa457a0/d; +L_0xa45860/d .functor AND 1, L_0xa46af0, L_0xa457a0, C4<1>, C4<1>; +L_0xa45860 .delay (20000,20000,20000) L_0xa45860/d; +L_0xa45970/d .functor AND 1, L_0xa453d0, L_0xa45c50, C4<1>, C4<1>; +L_0xa45970 .delay (20000,20000,20000) L_0xa45970/d; +L_0xa45a80/d .functor OR 1, L_0xa45860, L_0xa45970, C4<0>, C4<0>; +L_0xa45a80 .delay (20000,20000,20000) L_0xa45a80/d; +v0xa29d40_0 .net "S", 0 0, L_0xa45c50; 1 drivers +v0xa29e00_0 .alias "in0", 0 0, v0xa2a460_0; +v0xa29ea0_0 .alias "in1", 0 0, v0xa2a9e0_0; +v0xa29f40_0 .net "nS", 0 0, L_0xa457a0; 1 drivers +v0xa29fc0_0 .net "out0", 0 0, L_0xa45860; 1 drivers +v0xa2a060_0 .net "out1", 0 0, L_0xa45970; 1 drivers +v0xa2a140_0 .alias "outfinal", 0 0, v0xa2a510_0; +S_0xa295e0 .scope module, "setSLTres2" "TwoInMux" 3 310, 3 8, S_0xa28f00; + .timescale -9 -12; +L_0xa37340/d .functor NOT 1, L_0xa47e00, C4<0>, C4<0>, C4<0>; +L_0xa37340 .delay (10000,10000,10000) L_0xa37340/d; +L_0xa42580/d .functor AND 1, L_0xa475f0, L_0xa37340, C4<1>, C4<1>; +L_0xa42580 .delay (20000,20000,20000) L_0xa42580/d; +L_0xa47370/d .functor AND 1, C4<0>, L_0xa47e00, C4<1>, C4<1>; +L_0xa47370 .delay (20000,20000,20000) L_0xa47370/d; +L_0xa47410/d .functor OR 1, L_0xa42580, L_0xa47370, C4<0>, C4<0>; +L_0xa47410 .delay (20000,20000,20000) L_0xa47410/d; +v0xa296d0_0 .alias "S", 0 0, v0xa309c0_0; +v0xa29770_0 .net "in0", 0 0, L_0xa475f0; 1 drivers +v0xa297f0_0 .net "in1", 0 0, C4<0>; 1 drivers +v0xa29890_0 .net "nS", 0 0, L_0xa37340; 1 drivers +v0xa29940_0 .net "out0", 0 0, L_0xa42580; 1 drivers +v0xa299e0_0 .net "out1", 0 0, L_0xa47370; 1 drivers +v0xa29ac0_0 .net "outfinal", 0 0, L_0xa47410; 1 drivers +S_0xa29070 .scope module, "setSLTres3" "TwoInMux" 3 311, 3 8, S_0xa28f00; + .timescale -9 -12; +L_0xa477e0/d .functor NOT 1, L_0xa47e00, C4<0>, C4<0>, C4<0>; +L_0xa477e0 .delay (10000,10000,10000) L_0xa477e0/d; +L_0xa47890/d .functor AND 1, L_0xa47c00, L_0xa477e0, C4<1>, C4<1>; +L_0xa47890 .delay (20000,20000,20000) L_0xa47890/d; +L_0xa47980/d .functor AND 1, L_0xa476e0, L_0xa47e00, C4<1>, C4<1>; +L_0xa47980 .delay (20000,20000,20000) L_0xa47980/d; +L_0xa47a20/d .functor OR 1, L_0xa47890, L_0xa47980, C4<0>, C4<0>; +L_0xa47a20 .delay (20000,20000,20000) L_0xa47a20/d; +v0xa29160_0 .alias "S", 0 0, v0xa309c0_0; +v0xa29200_0 .net "in0", 0 0, L_0xa47c00; 1 drivers +v0xa292a0_0 .net "in1", 0 0, L_0xa476e0; 1 drivers +v0xa29340_0 .net "nS", 0 0, L_0xa477e0; 1 drivers +v0xa293c0_0 .net "out0", 0 0, L_0xa47890; 1 drivers +v0xa29460_0 .net "out1", 0 0, L_0xa47980; 1 drivers +v0xa29540_0 .net "outfinal", 0 0, L_0xa47a20; 1 drivers +S_0xa25c80 .scope module, "trial1" "AndNand32" 2 150, 3 154, S_0x96f1c0; + .timescale -9 -12; +P_0xa25798 .param/l "size" 3 161, +C4<0100>; +v0xa28b40_0 .alias "A", 3 0, v0xa37070_0; +v0xa28bc0_0 .alias "AndNandOut", 3 0, v0xa387d0_0; +v0xa28c90_0 .alias "B", 3 0, v0xa37220_0; +v0xa28d10_0 .alias "Command", 2 0, v0xa373b0_0; +L_0xa4bac0 .part/pv L_0xa4b850, 1, 1, 4; +L_0xa4bc10 .part v0xa38650_0, 1, 1; +L_0xa4bcb0 .part v0xa38850_0, 1, 1; +L_0xa4c570 .part/pv L_0xa4c300, 2, 1, 4; +L_0xa4c610 .part v0xa38650_0, 2, 1; +L_0xa4c6b0 .part v0xa38850_0, 2, 1; +L_0xa4cfe0 .part/pv L_0xa4cd70, 3, 1, 4; +L_0xa4d080 .part v0xa38650_0, 3, 1; +L_0xa4d170 .part v0xa38850_0, 3, 1; +L_0xa4da40 .part/pv L_0xa4d7d0, 0, 1, 4; +L_0xa4db40 .part v0xa38650_0, 0, 1; +L_0xa4dbe0 .part v0xa38850_0, 0, 1; +S_0xa28110 .scope module, "attempt2" "AndNand" 3 165, 3 48, S_0xa25c80; + .timescale -9 -12; +L_0xa4d260/d .functor NAND 1, L_0xa4db40, L_0xa4dbe0, C4<1>, C4<1>; +L_0xa4d260 .delay (10000,10000,10000) L_0xa4d260/d; +L_0xa4d380/d .functor NOT 1, L_0xa4d260, C4<0>, C4<0>, C4<0>; +L_0xa4d380 .delay (10000,10000,10000) L_0xa4d380/d; +v0xa28730_0 .net "A", 0 0, L_0xa4db40; 1 drivers +v0xa287f0_0 .net "AandB", 0 0, L_0xa4d380; 1 drivers +v0xa28870_0 .net "AnandB", 0 0, L_0xa4d260; 1 drivers +v0xa28920_0 .net "AndNandOut", 0 0, L_0xa4d7d0; 1 drivers +v0xa28a00_0 .net "B", 0 0, L_0xa4dbe0; 1 drivers +v0xa28a80_0 .alias "Command", 2 0, v0xa373b0_0; +L_0xa4d9a0 .part v0xa388d0_0, 0, 1; +S_0xa28200 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0xa28110; + .timescale -9 -12; +L_0xa4d4b0/d .functor NOT 1, L_0xa4d9a0, C4<0>, C4<0>, C4<0>; +L_0xa4d4b0 .delay (10000,10000,10000) L_0xa4d4b0/d; +L_0xa4d570/d .functor AND 1, L_0xa4d380, L_0xa4d4b0, C4<1>, C4<1>; +L_0xa4d570 .delay (20000,20000,20000) L_0xa4d570/d; +L_0xa4d680/d .functor AND 1, L_0xa4d260, L_0xa4d9a0, C4<1>, C4<1>; +L_0xa4d680 .delay (20000,20000,20000) L_0xa4d680/d; +L_0xa4d7d0/d .functor OR 1, L_0xa4d570, L_0xa4d680, C4<0>, C4<0>; +L_0xa4d7d0 .delay (20000,20000,20000) L_0xa4d7d0/d; +v0xa282f0_0 .net "S", 0 0, L_0xa4d9a0; 1 drivers +v0xa28370_0 .alias "in0", 0 0, v0xa287f0_0; +v0xa283f0_0 .alias "in1", 0 0, v0xa28870_0; +v0xa28490_0 .net "nS", 0 0, L_0xa4d4b0; 1 drivers +v0xa28510_0 .net "out0", 0 0, L_0xa4d570; 1 drivers +v0xa285b0_0 .net "out1", 0 0, L_0xa4d680; 1 drivers +v0xa28690_0 .alias "outfinal", 0 0, v0xa28920_0; +S_0xa27550 .scope generate, "andbits[1]" "andbits[1]" 3 169, 3 169, S_0xa25c80; + .timescale -9 -12; +P_0xa27648 .param/l "i" 3 169, +C4<01>; +S_0xa276c0 .scope module, "attempt" "AndNand" 3 171, 3 48, S_0xa27550; + .timescale -9 -12; +L_0xa4a810/d .functor NAND 1, L_0xa4bc10, L_0xa4bcb0, C4<1>, C4<1>; +L_0xa4a810 .delay (10000,10000,10000) L_0xa4a810/d; +L_0xa4b440/d .functor NOT 1, L_0xa4a810, C4<0>, C4<0>, C4<0>; +L_0xa4b440 .delay (10000,10000,10000) L_0xa4b440/d; +v0xa27d00_0 .net "A", 0 0, L_0xa4bc10; 1 drivers +v0xa27dc0_0 .net "AandB", 0 0, L_0xa4b440; 1 drivers +v0xa27e40_0 .net "AnandB", 0 0, L_0xa4a810; 1 drivers +v0xa27ef0_0 .net "AndNandOut", 0 0, L_0xa4b850; 1 drivers +v0xa27fd0_0 .net "B", 0 0, L_0xa4bcb0; 1 drivers +v0xa28050_0 .alias "Command", 2 0, v0xa373b0_0; +L_0xa4ba20 .part v0xa388d0_0, 0, 1; +S_0xa277b0 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0xa276c0; + .timescale -9 -12; +L_0xa4b530/d .functor NOT 1, L_0xa4ba20, C4<0>, C4<0>, C4<0>; +L_0xa4b530 .delay (10000,10000,10000) L_0xa4b530/d; +L_0xa4b5f0/d .functor AND 1, L_0xa4b440, L_0xa4b530, C4<1>, C4<1>; +L_0xa4b5f0 .delay (20000,20000,20000) L_0xa4b5f0/d; +L_0xa4b700/d .functor AND 1, L_0xa4a810, L_0xa4ba20, C4<1>, C4<1>; +L_0xa4b700 .delay (20000,20000,20000) L_0xa4b700/d; +L_0xa4b850/d .functor OR 1, L_0xa4b5f0, L_0xa4b700, C4<0>, C4<0>; +L_0xa4b850 .delay (20000,20000,20000) L_0xa4b850/d; +v0xa278a0_0 .net "S", 0 0, L_0xa4ba20; 1 drivers +v0xa27920_0 .alias "in0", 0 0, v0xa27dc0_0; +v0xa279c0_0 .alias "in1", 0 0, v0xa27e40_0; +v0xa27a60_0 .net "nS", 0 0, L_0xa4b530; 1 drivers +v0xa27ae0_0 .net "out0", 0 0, L_0xa4b5f0; 1 drivers +v0xa27b80_0 .net "out1", 0 0, L_0xa4b700; 1 drivers +v0xa27c60_0 .alias "outfinal", 0 0, v0xa27ef0_0; +S_0xa26990 .scope generate, "andbits[2]" "andbits[2]" 3 169, 3 169, S_0xa25c80; + .timescale -9 -12; +P_0xa26a88 .param/l "i" 3 169, +C4<010>; +S_0xa26b00 .scope module, "attempt" "AndNand" 3 171, 3 48, S_0xa26990; + .timescale -9 -12; +L_0xa4bd50/d .functor NAND 1, L_0xa4c610, L_0xa4c6b0, C4<1>, C4<1>; +L_0xa4bd50 .delay (10000,10000,10000) L_0xa4bd50/d; +L_0xa4beb0/d .functor NOT 1, L_0xa4bd50, C4<0>, C4<0>, C4<0>; +L_0xa4beb0 .delay (10000,10000,10000) L_0xa4beb0/d; +v0xa27140_0 .net "A", 0 0, L_0xa4c610; 1 drivers +v0xa27200_0 .net "AandB", 0 0, L_0xa4beb0; 1 drivers +v0xa27280_0 .net "AnandB", 0 0, L_0xa4bd50; 1 drivers +v0xa27330_0 .net "AndNandOut", 0 0, L_0xa4c300; 1 drivers +v0xa27410_0 .net "B", 0 0, L_0xa4c6b0; 1 drivers +v0xa27490_0 .alias "Command", 2 0, v0xa373b0_0; +L_0xa4c4d0 .part v0xa388d0_0, 0, 1; +S_0xa26bf0 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0xa26b00; + .timescale -9 -12; +L_0xa4bfe0/d .functor NOT 1, L_0xa4c4d0, C4<0>, C4<0>, C4<0>; +L_0xa4bfe0 .delay (10000,10000,10000) L_0xa4bfe0/d; +L_0xa4c0a0/d .functor AND 1, L_0xa4beb0, L_0xa4bfe0, C4<1>, C4<1>; +L_0xa4c0a0 .delay (20000,20000,20000) L_0xa4c0a0/d; +L_0xa4c1b0/d .functor AND 1, L_0xa4bd50, L_0xa4c4d0, C4<1>, C4<1>; +L_0xa4c1b0 .delay (20000,20000,20000) L_0xa4c1b0/d; +L_0xa4c300/d .functor OR 1, L_0xa4c0a0, L_0xa4c1b0, C4<0>, C4<0>; +L_0xa4c300 .delay (20000,20000,20000) L_0xa4c300/d; +v0xa26ce0_0 .net "S", 0 0, L_0xa4c4d0; 1 drivers +v0xa26d60_0 .alias "in0", 0 0, v0xa27200_0; +v0xa26e00_0 .alias "in1", 0 0, v0xa27280_0; +v0xa26ea0_0 .net "nS", 0 0, L_0xa4bfe0; 1 drivers +v0xa26f20_0 .net "out0", 0 0, L_0xa4c0a0; 1 drivers +v0xa26fc0_0 .net "out1", 0 0, L_0xa4c1b0; 1 drivers +v0xa270a0_0 .alias "outfinal", 0 0, v0xa27330_0; +S_0xa25db0 .scope generate, "andbits[3]" "andbits[3]" 3 169, 3 169, S_0xa25c80; + .timescale -9 -12; +P_0xa25ea8 .param/l "i" 3 169, +C4<011>; +S_0xa25f20 .scope module, "attempt" "AndNand" 3 171, 3 48, S_0xa25db0; + .timescale -9 -12; +L_0xa4c7e0/d .functor NAND 1, L_0xa4d080, L_0xa4d170, C4<1>, C4<1>; +L_0xa4c7e0 .delay (10000,10000,10000) L_0xa4c7e0/d; +L_0xa4c920/d .functor NOT 1, L_0xa4c7e0, C4<0>, C4<0>, C4<0>; +L_0xa4c920 .delay (10000,10000,10000) L_0xa4c920/d; +v0xa26580_0 .net "A", 0 0, L_0xa4d080; 1 drivers +v0xa26640_0 .net "AandB", 0 0, L_0xa4c920; 1 drivers +v0xa266c0_0 .net "AnandB", 0 0, L_0xa4c7e0; 1 drivers +v0xa26770_0 .net "AndNandOut", 0 0, L_0xa4cd70; 1 drivers +v0xa26850_0 .net "B", 0 0, L_0xa4d170; 1 drivers +v0xa268d0_0 .alias "Command", 2 0, v0xa373b0_0; +L_0xa4cf40 .part v0xa388d0_0, 0, 1; +S_0xa26010 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0xa25f20; + .timescale -9 -12; +L_0xa4ca50/d .functor NOT 1, L_0xa4cf40, C4<0>, C4<0>, C4<0>; +L_0xa4ca50 .delay (10000,10000,10000) L_0xa4ca50/d; +L_0xa4cb10/d .functor AND 1, L_0xa4c920, L_0xa4ca50, C4<1>, C4<1>; +L_0xa4cb10 .delay (20000,20000,20000) L_0xa4cb10/d; +L_0xa4cc20/d .functor AND 1, L_0xa4c7e0, L_0xa4cf40, C4<1>, C4<1>; +L_0xa4cc20 .delay (20000,20000,20000) L_0xa4cc20/d; +L_0xa4cd70/d .functor OR 1, L_0xa4cb10, L_0xa4cc20, C4<0>, C4<0>; +L_0xa4cd70 .delay (20000,20000,20000) L_0xa4cd70/d; +v0xa26100_0 .net "S", 0 0, L_0xa4cf40; 1 drivers +v0xa261a0_0 .alias "in0", 0 0, v0xa26640_0; +v0xa26240_0 .alias "in1", 0 0, v0xa266c0_0; +v0xa262e0_0 .net "nS", 0 0, L_0xa4ca50; 1 drivers +v0xa26360_0 .net "out0", 0 0, L_0xa4cb10; 1 drivers +v0xa26400_0 .net "out1", 0 0, L_0xa4cc20; 1 drivers +v0xa264e0_0 .alias "outfinal", 0 0, v0xa26770_0; +S_0xa20c10 .scope module, "trial2" "OrNorXor32" 2 152, 3 177, S_0x96f1c0; + .timescale -9 -12; +P_0xa1e328 .param/l "size" 3 184, +C4<0100>; +v0xa25a80_0 .alias "A", 3 0, v0xa37070_0; +v0xa25b00_0 .alias "B", 3 0, v0xa37220_0; +v0xa25b80_0 .alias "Command", 2 0, v0xa373b0_0; +v0xa25c00_0 .alias "OrNorXorOut", 3 0, v0xa389d0_0; +L_0xa4ee00 .part/pv L_0xa4eb90, 1, 1, 4; +L_0xa4ef30 .part v0xa38650_0, 1, 1; +L_0xa4efd0 .part v0xa38850_0, 1, 1; +L_0xa50140 .part/pv L_0xa4fed0, 2, 1, 4; +L_0xa501e0 .part v0xa38650_0, 2, 1; +L_0xa50280 .part v0xa38850_0, 2, 1; +L_0xa51440 .part/pv L_0xa511d0, 3, 1, 4; +L_0xa514e0 .part v0xa38650_0, 3, 1; +L_0xa51580 .part v0xa38850_0, 3, 1; +L_0xa52730 .part/pv L_0xa524c0, 0, 1, 4; +L_0xa52830 .part v0xa38650_0, 0, 1; +L_0xa528d0 .part v0xa38850_0, 0, 1; +S_0xa24840 .scope module, "attempt2" "OrNorXor" 3 192, 3 64, S_0xa20c10; + .timescale -9 -12; +L_0xa51620/d .functor NOR 1, L_0xa52830, L_0xa528d0, C4<0>, C4<0>; +L_0xa51620 .delay (10000,10000,10000) L_0xa51620/d; +L_0xa51720/d .functor NOT 1, L_0xa51620, C4<0>, C4<0>, C4<0>; +L_0xa51720 .delay (10000,10000,10000) L_0xa51720/d; +L_0xa51850/d .functor NAND 1, L_0xa52830, L_0xa528d0, C4<1>, C4<1>; +L_0xa51850 .delay (10000,10000,10000) L_0xa51850/d; +L_0xa519b0/d .functor NAND 1, L_0xa51850, L_0xa51720, C4<1>, C4<1>; +L_0xa519b0 .delay (10000,10000,10000) L_0xa519b0/d; +L_0xa51ac0/d .functor NOT 1, L_0xa519b0, C4<0>, C4<0>, C4<0>; +L_0xa51ac0 .delay (10000,10000,10000) L_0xa51ac0/d; +v0xa25390_0 .net "A", 0 0, L_0xa52830; 1 drivers +v0xa25430_0 .net "AnandB", 0 0, L_0xa51850; 1 drivers +v0xa254d0_0 .net "AnorB", 0 0, L_0xa51620; 1 drivers +v0xa25580_0 .net "AorB", 0 0, L_0xa51720; 1 drivers +v0xa25660_0 .net "AxorB", 0 0, L_0xa51ac0; 1 drivers +v0xa25710_0 .net "B", 0 0, L_0xa528d0; 1 drivers +v0xa257d0_0 .alias "Command", 2 0, v0xa373b0_0; +v0xa25850_0 .net "OrNorXorOut", 0 0, L_0xa524c0; 1 drivers +v0xa258d0_0 .net "XorNor", 0 0, L_0xa51f40; 1 drivers +v0xa259a0_0 .net "nXor", 0 0, L_0xa519b0; 1 drivers +L_0xa520c0 .part v0xa388d0_0, 2, 1; +L_0xa52690 .part v0xa388d0_0, 0, 1; +S_0xa24e20 .scope module, "mux0" "TwoInMux" 3 83, 3 8, S_0xa24840; + .timescale -9 -12; +L_0xa51c20/d .functor NOT 1, L_0xa520c0, C4<0>, C4<0>, C4<0>; +L_0xa51c20 .delay (10000,10000,10000) L_0xa51c20/d; +L_0xa51ce0/d .functor AND 1, L_0xa51ac0, L_0xa51c20, C4<1>, C4<1>; +L_0xa51ce0 .delay (20000,20000,20000) L_0xa51ce0/d; +L_0xa51df0/d .functor AND 1, L_0xa51620, L_0xa520c0, C4<1>, C4<1>; +L_0xa51df0 .delay (20000,20000,20000) L_0xa51df0/d; +L_0xa51f40/d .functor OR 1, L_0xa51ce0, L_0xa51df0, C4<0>, C4<0>; +L_0xa51f40 .delay (20000,20000,20000) L_0xa51f40/d; +v0xa24f10_0 .net "S", 0 0, L_0xa520c0; 1 drivers +v0xa24fd0_0 .alias "in0", 0 0, v0xa25660_0; +v0xa25070_0 .alias "in1", 0 0, v0xa254d0_0; +v0xa25110_0 .net "nS", 0 0, L_0xa51c20; 1 drivers +v0xa25190_0 .net "out0", 0 0, L_0xa51ce0; 1 drivers +v0xa25230_0 .net "out1", 0 0, L_0xa51df0; 1 drivers +v0xa25310_0 .alias "outfinal", 0 0, v0xa258d0_0; +S_0xa24930 .scope module, "mux1" "TwoInMux" 3 84, 3 8, S_0xa24840; + .timescale -9 -12; +L_0xa52160/d .functor NOT 1, L_0xa52690, C4<0>, C4<0>, C4<0>; +L_0xa52160 .delay (10000,10000,10000) L_0xa52160/d; +L_0xa52220/d .functor AND 1, L_0xa51f40, L_0xa52160, C4<1>, C4<1>; +L_0xa52220 .delay (20000,20000,20000) L_0xa52220/d; +L_0xa52370/d .functor AND 1, L_0xa51720, L_0xa52690, C4<1>, C4<1>; +L_0xa52370 .delay (20000,20000,20000) L_0xa52370/d; +L_0xa524c0/d .functor OR 1, L_0xa52220, L_0xa52370, C4<0>, C4<0>; +L_0xa524c0 .delay (20000,20000,20000) L_0xa524c0/d; +v0xa24a20_0 .net "S", 0 0, L_0xa52690; 1 drivers +v0xa24aa0_0 .alias "in0", 0 0, v0xa258d0_0; +v0xa24b20_0 .alias "in1", 0 0, v0xa25580_0; +v0xa24bc0_0 .net "nS", 0 0, L_0xa52160; 1 drivers +v0xa24c40_0 .net "out0", 0 0, L_0xa52220; 1 drivers +v0xa24ce0_0 .net "out1", 0 0, L_0xa52370; 1 drivers +v0xa24d80_0 .alias "outfinal", 0 0, v0xa25850_0; +S_0xa23470 .scope generate, "orbits[1]" "orbits[1]" 3 196, 3 196, S_0xa20c10; + .timescale -9 -12; +P_0xa23188 .param/l "i" 3 196, +C4<01>; +S_0xa235a0 .scope module, "attempt" "OrNorXor" 3 198, 3 64, S_0xa23470; + .timescale -9 -12; +L_0xa4dae0/d .functor NOR 1, L_0xa4ef30, L_0xa4efd0, C4<0>, C4<0>; +L_0xa4dae0 .delay (10000,10000,10000) L_0xa4dae0/d; +L_0xa4ddf0/d .functor NOT 1, L_0xa4dae0, C4<0>, C4<0>, C4<0>; +L_0xa4ddf0 .delay (10000,10000,10000) L_0xa4ddf0/d; +L_0xa4df20/d .functor NAND 1, L_0xa4ef30, L_0xa4efd0, C4<1>, C4<1>; +L_0xa4df20 .delay (10000,10000,10000) L_0xa4df20/d; +L_0xa4e080/d .functor NAND 1, L_0xa4df20, L_0xa4ddf0, C4<1>, C4<1>; +L_0xa4e080 .delay (10000,10000,10000) L_0xa4e080/d; +L_0xa4e190/d .functor NOT 1, L_0xa4e080, C4<0>, C4<0>, C4<0>; +L_0xa4e190 .delay (10000,10000,10000) L_0xa4e190/d; +v0xa24150_0 .net "A", 0 0, L_0xa4ef30; 1 drivers +v0xa241f0_0 .net "AnandB", 0 0, L_0xa4df20; 1 drivers +v0xa24290_0 .net "AnorB", 0 0, L_0xa4dae0; 1 drivers +v0xa24340_0 .net "AorB", 0 0, L_0xa4ddf0; 1 drivers +v0xa24420_0 .net "AxorB", 0 0, L_0xa4e190; 1 drivers +v0xa244d0_0 .net "B", 0 0, L_0xa4efd0; 1 drivers +v0xa24590_0 .alias "Command", 2 0, v0xa373b0_0; +v0xa24610_0 .net "OrNorXorOut", 0 0, L_0xa4eb90; 1 drivers +v0xa24690_0 .net "XorNor", 0 0, L_0xa4e610; 1 drivers +v0xa24760_0 .net "nXor", 0 0, L_0xa4e080; 1 drivers +L_0xa4e790 .part v0xa388d0_0, 2, 1; +L_0xa4ed60 .part v0xa388d0_0, 0, 1; +S_0xa23be0 .scope module, "mux0" "TwoInMux" 3 83, 3 8, S_0xa235a0; + .timescale -9 -12; +L_0xa4e2f0/d .functor NOT 1, L_0xa4e790, C4<0>, C4<0>, C4<0>; +L_0xa4e2f0 .delay (10000,10000,10000) L_0xa4e2f0/d; +L_0xa4e3b0/d .functor AND 1, L_0xa4e190, L_0xa4e2f0, C4<1>, C4<1>; +L_0xa4e3b0 .delay (20000,20000,20000) L_0xa4e3b0/d; +L_0xa4e4c0/d .functor AND 1, L_0xa4dae0, L_0xa4e790, C4<1>, C4<1>; +L_0xa4e4c0 .delay (20000,20000,20000) L_0xa4e4c0/d; +L_0xa4e610/d .functor OR 1, L_0xa4e3b0, L_0xa4e4c0, C4<0>, C4<0>; +L_0xa4e610 .delay (20000,20000,20000) L_0xa4e610/d; +v0xa23cd0_0 .net "S", 0 0, L_0xa4e790; 1 drivers +v0xa23d90_0 .alias "in0", 0 0, v0xa24420_0; +v0xa23e30_0 .alias "in1", 0 0, v0xa24290_0; +v0xa23ed0_0 .net "nS", 0 0, L_0xa4e2f0; 1 drivers +v0xa23f50_0 .net "out0", 0 0, L_0xa4e3b0; 1 drivers +v0xa23ff0_0 .net "out1", 0 0, L_0xa4e4c0; 1 drivers +v0xa240d0_0 .alias "outfinal", 0 0, v0xa24690_0; +S_0xa23690 .scope module, "mux1" "TwoInMux" 3 84, 3 8, S_0xa235a0; + .timescale -9 -12; +L_0xa4e830/d .functor NOT 1, L_0xa4ed60, C4<0>, C4<0>, C4<0>; +L_0xa4e830 .delay (10000,10000,10000) L_0xa4e830/d; +L_0xa4e8f0/d .functor AND 1, L_0xa4e610, L_0xa4e830, C4<1>, C4<1>; +L_0xa4e8f0 .delay (20000,20000,20000) L_0xa4e8f0/d; +L_0xa4ea40/d .functor AND 1, L_0xa4ddf0, L_0xa4ed60, C4<1>, C4<1>; +L_0xa4ea40 .delay (20000,20000,20000) L_0xa4ea40/d; +L_0xa4eb90/d .functor OR 1, L_0xa4e8f0, L_0xa4ea40, C4<0>, C4<0>; +L_0xa4eb90 .delay (20000,20000,20000) L_0xa4eb90/d; +v0xa23780_0 .net "S", 0 0, L_0xa4ed60; 1 drivers +v0xa23800_0 .alias "in0", 0 0, v0xa24690_0; +v0xa238a0_0 .alias "in1", 0 0, v0xa24340_0; +v0xa23940_0 .net "nS", 0 0, L_0xa4e830; 1 drivers +v0xa239c0_0 .net "out0", 0 0, L_0xa4e8f0; 1 drivers +v0xa23a60_0 .net "out1", 0 0, L_0xa4ea40; 1 drivers +v0xa23b40_0 .alias "outfinal", 0 0, v0xa24610_0; +S_0xa220a0 .scope generate, "orbits[2]" "orbits[2]" 3 196, 3 196, S_0xa20c10; + .timescale -9 -12; +P_0xa21dc8 .param/l "i" 3 196, +C4<010>; +S_0xa221d0 .scope module, "attempt" "OrNorXor" 3 198, 3 64, S_0xa220a0; + .timescale -9 -12; +L_0xa4f070/d .functor NOR 1, L_0xa501e0, L_0xa50280, C4<0>, C4<0>; +L_0xa4f070 .delay (10000,10000,10000) L_0xa4f070/d; +L_0xa4f130/d .functor NOT 1, L_0xa4f070, C4<0>, C4<0>, C4<0>; +L_0xa4f130 .delay (10000,10000,10000) L_0xa4f130/d; +L_0xa4f260/d .functor NAND 1, L_0xa501e0, L_0xa50280, C4<1>, C4<1>; +L_0xa4f260 .delay (10000,10000,10000) L_0xa4f260/d; +L_0xa4f3c0/d .functor NAND 1, L_0xa4f260, L_0xa4f130, C4<1>, C4<1>; +L_0xa4f3c0 .delay (10000,10000,10000) L_0xa4f3c0/d; +L_0xa4f4d0/d .functor NOT 1, L_0xa4f3c0, C4<0>, C4<0>, C4<0>; +L_0xa4f4d0 .delay (10000,10000,10000) L_0xa4f4d0/d; +v0xa22d80_0 .net "A", 0 0, L_0xa501e0; 1 drivers +v0xa22e20_0 .net "AnandB", 0 0, L_0xa4f260; 1 drivers +v0xa22ec0_0 .net "AnorB", 0 0, L_0xa4f070; 1 drivers +v0xa22f70_0 .net "AorB", 0 0, L_0xa4f130; 1 drivers +v0xa23050_0 .net "AxorB", 0 0, L_0xa4f4d0; 1 drivers +v0xa23100_0 .net "B", 0 0, L_0xa50280; 1 drivers +v0xa231c0_0 .alias "Command", 2 0, v0xa373b0_0; +v0xa23240_0 .net "OrNorXorOut", 0 0, L_0xa4fed0; 1 drivers +v0xa232c0_0 .net "XorNor", 0 0, L_0xa4f950; 1 drivers +v0xa23390_0 .net "nXor", 0 0, L_0xa4f3c0; 1 drivers +L_0xa4fad0 .part v0xa388d0_0, 2, 1; +L_0xa500a0 .part v0xa388d0_0, 0, 1; +S_0xa22810 .scope module, "mux0" "TwoInMux" 3 83, 3 8, S_0xa221d0; + .timescale -9 -12; +L_0xa4f630/d .functor NOT 1, L_0xa4fad0, C4<0>, C4<0>, C4<0>; +L_0xa4f630 .delay (10000,10000,10000) L_0xa4f630/d; +L_0xa4f6f0/d .functor AND 1, L_0xa4f4d0, L_0xa4f630, C4<1>, C4<1>; +L_0xa4f6f0 .delay (20000,20000,20000) L_0xa4f6f0/d; +L_0xa4f800/d .functor AND 1, L_0xa4f070, L_0xa4fad0, C4<1>, C4<1>; +L_0xa4f800 .delay (20000,20000,20000) L_0xa4f800/d; +L_0xa4f950/d .functor OR 1, L_0xa4f6f0, L_0xa4f800, C4<0>, C4<0>; +L_0xa4f950 .delay (20000,20000,20000) L_0xa4f950/d; +v0xa22900_0 .net "S", 0 0, L_0xa4fad0; 1 drivers +v0xa229c0_0 .alias "in0", 0 0, v0xa23050_0; +v0xa22a60_0 .alias "in1", 0 0, v0xa22ec0_0; +v0xa22b00_0 .net "nS", 0 0, L_0xa4f630; 1 drivers +v0xa22b80_0 .net "out0", 0 0, L_0xa4f6f0; 1 drivers +v0xa22c20_0 .net "out1", 0 0, L_0xa4f800; 1 drivers +v0xa22d00_0 .alias "outfinal", 0 0, v0xa232c0_0; +S_0xa222c0 .scope module, "mux1" "TwoInMux" 3 84, 3 8, S_0xa221d0; + .timescale -9 -12; +L_0xa4fb70/d .functor NOT 1, L_0xa500a0, C4<0>, C4<0>, C4<0>; +L_0xa4fb70 .delay (10000,10000,10000) L_0xa4fb70/d; +L_0xa4fc30/d .functor AND 1, L_0xa4f950, L_0xa4fb70, C4<1>, C4<1>; +L_0xa4fc30 .delay (20000,20000,20000) L_0xa4fc30/d; +L_0xa4fd80/d .functor AND 1, L_0xa4f130, L_0xa500a0, C4<1>, C4<1>; +L_0xa4fd80 .delay (20000,20000,20000) L_0xa4fd80/d; +L_0xa4fed0/d .functor OR 1, L_0xa4fc30, L_0xa4fd80, C4<0>, C4<0>; +L_0xa4fed0 .delay (20000,20000,20000) L_0xa4fed0/d; +v0xa223b0_0 .net "S", 0 0, L_0xa500a0; 1 drivers +v0xa22430_0 .alias "in0", 0 0, v0xa232c0_0; +v0xa224d0_0 .alias "in1", 0 0, v0xa22f70_0; +v0xa22570_0 .net "nS", 0 0, L_0xa4fb70; 1 drivers +v0xa225f0_0 .net "out0", 0 0, L_0xa4fc30; 1 drivers +v0xa22690_0 .net "out1", 0 0, L_0xa4fd80; 1 drivers +v0xa22770_0 .alias "outfinal", 0 0, v0xa23240_0; +S_0xa20d00 .scope generate, "orbits[3]" "orbits[3]" 3 196, 3 196, S_0xa20c10; + .timescale -9 -12; +P_0xa20df8 .param/l "i" 3 196, +C4<011>; +S_0xa20eb0 .scope module, "attempt" "OrNorXor" 3 198, 3 64, S_0xa20d00; + .timescale -9 -12; +L_0xa50360/d .functor NOR 1, L_0xa514e0, L_0xa51580, C4<0>, C4<0>; +L_0xa50360 .delay (10000,10000,10000) L_0xa50360/d; +L_0xa50450/d .functor NOT 1, L_0xa50360, C4<0>, C4<0>, C4<0>; +L_0xa50450 .delay (10000,10000,10000) L_0xa50450/d; +L_0xa50560/d .functor NAND 1, L_0xa514e0, L_0xa51580, C4<1>, C4<1>; +L_0xa50560 .delay (10000,10000,10000) L_0xa50560/d; +L_0xa506c0/d .functor NAND 1, L_0xa50560, L_0xa50450, C4<1>, C4<1>; +L_0xa506c0 .delay (10000,10000,10000) L_0xa506c0/d; +L_0xa507d0/d .functor NOT 1, L_0xa506c0, C4<0>, C4<0>, C4<0>; +L_0xa507d0 .delay (10000,10000,10000) L_0xa507d0/d; +v0xa21a80_0 .net "A", 0 0, L_0xa514e0; 1 drivers +v0xa21b20_0 .net "AnandB", 0 0, L_0xa50560; 1 drivers +v0xa21bc0_0 .net "AnorB", 0 0, L_0xa50360; 1 drivers +v0xa21c40_0 .net "AorB", 0 0, L_0xa50450; 1 drivers +v0xa21cc0_0 .net "AxorB", 0 0, L_0xa507d0; 1 drivers +v0xa21d40_0 .net "B", 0 0, L_0xa51580; 1 drivers +v0xa21e00_0 .alias "Command", 2 0, v0xa373b0_0; +v0xa21e80_0 .net "OrNorXorOut", 0 0, L_0xa511d0; 1 drivers +v0xa21f50_0 .net "XorNor", 0 0, L_0xa50c50; 1 drivers +v0xa22020_0 .net "nXor", 0 0, L_0xa506c0; 1 drivers +L_0xa50dd0 .part v0xa388d0_0, 2, 1; +L_0xa513a0 .part v0xa388d0_0, 0, 1; +S_0xa21510 .scope module, "mux0" "TwoInMux" 3 83, 3 8, S_0xa20eb0; + .timescale -9 -12; +L_0xa50930/d .functor NOT 1, L_0xa50dd0, C4<0>, C4<0>, C4<0>; +L_0xa50930 .delay (10000,10000,10000) L_0xa50930/d; +L_0xa509f0/d .functor AND 1, L_0xa507d0, L_0xa50930, C4<1>, C4<1>; +L_0xa509f0 .delay (20000,20000,20000) L_0xa509f0/d; +L_0xa50b00/d .functor AND 1, L_0xa50360, L_0xa50dd0, C4<1>, C4<1>; +L_0xa50b00 .delay (20000,20000,20000) L_0xa50b00/d; +L_0xa50c50/d .functor OR 1, L_0xa509f0, L_0xa50b00, C4<0>, C4<0>; +L_0xa50c50 .delay (20000,20000,20000) L_0xa50c50/d; +v0xa21600_0 .net "S", 0 0, L_0xa50dd0; 1 drivers +v0xa216c0_0 .alias "in0", 0 0, v0xa21cc0_0; +v0xa21760_0 .alias "in1", 0 0, v0xa21bc0_0; +v0xa21800_0 .net "nS", 0 0, L_0xa50930; 1 drivers +v0xa21880_0 .net "out0", 0 0, L_0xa509f0; 1 drivers +v0xa21920_0 .net "out1", 0 0, L_0xa50b00; 1 drivers +v0xa21a00_0 .alias "outfinal", 0 0, v0xa21f50_0; +S_0xa20fa0 .scope module, "mux1" "TwoInMux" 3 84, 3 8, S_0xa20eb0; + .timescale -9 -12; +L_0xa50e70/d .functor NOT 1, L_0xa513a0, C4<0>, C4<0>, C4<0>; +L_0xa50e70 .delay (10000,10000,10000) L_0xa50e70/d; +L_0xa50f30/d .functor AND 1, L_0xa50c50, L_0xa50e70, C4<1>, C4<1>; +L_0xa50f30 .delay (20000,20000,20000) L_0xa50f30/d; +L_0xa51080/d .functor AND 1, L_0xa50450, L_0xa513a0, C4<1>, C4<1>; +L_0xa51080 .delay (20000,20000,20000) L_0xa51080/d; +L_0xa511d0/d .functor OR 1, L_0xa50f30, L_0xa51080, C4<0>, C4<0>; +L_0xa511d0 .delay (20000,20000,20000) L_0xa511d0/d; +v0xa21090_0 .net "S", 0 0, L_0xa513a0; 1 drivers +v0xa21130_0 .alias "in0", 0 0, v0xa21f50_0; +v0xa211d0_0 .alias "in1", 0 0, v0xa21c40_0; +v0xa21270_0 .net "nS", 0 0, L_0xa50e70; 1 drivers +v0xa212f0_0 .net "out0", 0 0, L_0xa50f30; 1 drivers +v0xa21390_0 .net "out1", 0 0, L_0xa51080; 1 drivers +v0xa21470_0 .alias "outfinal", 0 0, v0xa21e80_0; +S_0x9cd4a0 .scope module, "superalu" "Bitslice32" 2 154, 3 368, S_0x96f1c0; + .timescale -9 -12; +P_0x8c2938 .param/l "size" 3 386, +C4<0100>; +L_0xa576c0/d .functor AND 1, L_0xa76a20, L_0xa76c00, C4<1>, C4<1>; +L_0xa576c0 .delay (20000,20000,20000) L_0xa576c0/d; +L_0xa76cf0/d .functor NOT 1, L_0xa76da0, C4<0>, C4<0>, C4<0>; +L_0xa76cf0 .delay (10000,10000,10000) L_0xa76cf0/d; +L_0xa77250/d .functor AND 1, L_0xa76cf0, L_0xa76cf0, C4<1>, C4<1>; +L_0xa77250 .delay (20000,20000,20000) L_0xa77250/d; +v0xa1f9b0_0 .alias "A", 3 0, v0xa37070_0; +v0xa1fc90_0 .alias "AddSubSLTSum", 3 0, v0xa386d0_0; +v0xa1fd10_0 .alias "AllZeros", 0 0, v0xa38750_0; +v0xa1fd90_0 .alias "AndNandOut", 3 0, v0xa387d0_0; +v0xa1fe10_0 .alias "B", 3 0, v0xa37220_0; +RS_0x7ffb33a71f28 .resolv tri, L_0xa53070, L_0xa55a50, L_0xa58450, L_0xa74df0; +v0xa1ff20_0 .net8 "Cmd0Start", 3 0, RS_0x7ffb33a71f28; 4 drivers +RS_0x7ffb33a71f58 .resolv tri, L_0xa53f70, L_0xa56940, L_0xa59300, L_0xa75c20; +v0xa1ffa0_0 .net8 "Cmd1Start", 3 0, RS_0x7ffb33a71f58; 4 drivers +v0xa20020_0 .alias "Command", 2 0, v0xa373b0_0; +v0xa200a0_0 .alias "OneBitFinalOut", 3 0, v0xa38950_0; +v0xa20120_0 .alias "OrNorXorOut", 3 0, v0xa389d0_0; +v0xa201a0_0 .alias "SLTSum", 3 0, v0xa38a50_0; +v0xa20250_0 .alias "SLTflag", 0 0, v0xa38ad0_0; +v0xa20360_0 .alias "ZeroFlag", 3 0, v0xa38b50_0; +v0xa203e0_0 .net *"_s111", 0 0, L_0xa576c0; 1 drivers +v0xa204e0_0 .net *"_s114", 0 0, L_0xa76a20; 1 drivers +v0xa20560_0 .net *"_s116", 0 0, L_0xa76c00; 1 drivers +v0xa20460_0 .net *"_s118", 0 0, L_0xa76da0; 1 drivers +v0xa206b0_0 .net *"_s21", 0 0, L_0xa54fc0; 1 drivers +v0xa207d0_0 .net *"_s46", 0 0, L_0xa56f90; 1 drivers +v0xa20850_0 .net *"_s71", 0 0, L_0xa5a0c0; 1 drivers +v0xa20730_0 .alias "carryin", 3 0, v0xa37df0_0; +v0xa20980_0 .alias "carryout", 0 0, v0xa38c80_0; +v0xa208d0_0 .alias "overflow", 0 0, v0xa38d00_0; +v0xa20ac0_0 .alias "subtract", 3 0, v0xa38e00_0; +v0xa20a00_0 .net "yeszero", 0 0, L_0xa76cf0; 1 drivers +L_0xa53070 .part/pv L_0xa52e90, 1, 1, 4; +L_0xa53110 .part v0xa388d0_0, 0, 1; +L_0xa53240 .part v0xa388d0_0, 1, 1; +L_0xa53370 .part RS_0x7ffb33a70098, 1, 1; +L_0xa53410 .part RS_0x7ffb33a70098, 1, 1; +L_0xa534b0 .part RS_0x7ffb33a6e748, 1, 1; +L_0xa536b0 .part RS_0x7ffb33a71c58, 1, 1; +L_0xa53f70 .part/pv L_0xa53d90, 1, 1, 4; +L_0xa54060 .part v0xa388d0_0, 0, 1; +L_0xa54190 .part v0xa388d0_0, 1, 1; +L_0xa54320 .part RS_0x7ffb33a6ee38, 1, 1; +L_0xa544d0 .part RS_0x7ffb33a6ee38, 1, 1; +L_0xa54570 .part RS_0x7ffb33a6e748, 1, 1; +L_0xa54610 .part RS_0x7ffb33a6e748, 1, 1; +L_0xa54a70 .part/pv L_0xa54930, 1, 1, 4; +L_0xa54b60 .part v0xa388d0_0, 2, 1; +L_0xa54c00 .part RS_0x7ffb33a71f28, 1, 1; +L_0xa54d40 .part RS_0x7ffb33a71f58, 1, 1; +L_0xa54f20 .part/pv L_0xa54fc0, 1, 1, 4; +L_0xa550c0 .part RS_0x7ffb33a71fb8, 0, 1; +L_0xa54e80 .part RS_0x7ffb33a71f88, 1, 1; +L_0xa55a50 .part/pv L_0xa55840, 2, 1, 4; +L_0xa55160 .part v0xa388d0_0, 0, 1; +L_0xa55c40 .part v0xa388d0_0, 1, 1; +L_0xa55af0 .part RS_0x7ffb33a70098, 2, 1; +L_0xa55e40 .part RS_0x7ffb33a70098, 2, 1; +L_0xa55d70 .part RS_0x7ffb33a6e748, 2, 1; +L_0xa56010 .part RS_0x7ffb33a71c58, 2, 1; +L_0xa56940 .part/pv L_0xa56730, 2, 1, 4; +L_0xa569e0 .part v0xa388d0_0, 0, 1; +L_0xa56100 .part v0xa388d0_0, 1, 1; +L_0xa56ca0 .part RS_0x7ffb33a6ee38, 2, 1; +L_0xa56b10 .part RS_0x7ffb33a6ee38, 2, 1; +L_0xa56e50 .part RS_0x7ffb33a6e748, 2, 1; +L_0xa56d40 .part RS_0x7ffb33a6e748, 2, 1; +L_0xa573c0 .part/pv L_0xa57280, 2, 1, 4; +L_0xa56ef0 .part v0xa388d0_0, 2, 1; +L_0xa57620 .part RS_0x7ffb33a71f28, 2, 1; +L_0xa574f0 .part RS_0x7ffb33a71f58, 2, 1; +L_0xa57890 .part/pv L_0xa56f90, 2, 1, 4; +L_0xa57790 .part RS_0x7ffb33a71fb8, 1, 1; +L_0xa57b10 .part RS_0x7ffb33a71f88, 2, 1; +L_0xa58450 .part/pv L_0xa58240, 3, 1, 4; +L_0xa584f0 .part v0xa388d0_0, 0, 1; +L_0xa57bb0 .part v0xa388d0_0, 1, 1; +L_0xa58790 .part RS_0x7ffb33a70098, 3, 1; +L_0xa58620 .part RS_0x7ffb33a70098, 3, 1; +L_0xa586c0 .part RS_0x7ffb33a6e748, 3, 1; +L_0xa58830 .part RS_0x7ffb33a71c58, 3, 1; +L_0xa59300 .part/pv L_0xa590f0, 3, 1, 4; +L_0xa58a00 .part v0xa388d0_0, 0, 1; +L_0xa59540 .part v0xa388d0_0, 1, 1; +L_0xa593a0 .part RS_0x7ffb33a6ee38, 3, 1; +L_0xa59440 .part RS_0x7ffb33a6ee38, 3, 1; +L_0xa59830 .part RS_0x7ffb33a6e748, 3, 1; +L_0xa598d0 .part RS_0x7ffb33a6e748, 3, 1; +L_0xa59ee0 .part/pv L_0xa59da0, 3, 1, 4; +L_0xa59f80 .part v0xa388d0_0, 2, 1; +L_0xa59b80 .part RS_0x7ffb33a71f28, 3, 1; +L_0xa59c70 .part RS_0x7ffb33a71f58, 3, 1; +L_0xa5a020 .part/pv L_0xa5a0c0, 3, 1, 4; +L_0xa5a440 .part RS_0x7ffb33a71fb8, 2, 1; +L_0xa5a250 .part RS_0x7ffb33a71f88, 3, 1; +L_0xa74df0 .part/pv L_0xa74c10, 0, 1, 4; +L_0xa5a4e0 .part v0xa388d0_0, 0, 1; +L_0xa5a610 .part v0xa388d0_0, 1, 1; +L_0xa74e90 .part RS_0x7ffb33a70098, 0, 1; +L_0xa74f30 .part RS_0x7ffb33a70098, 0, 1; +L_0xa74fd0 .part RS_0x7ffb33a6e748, 0, 1; +L_0xa753b0 .part RS_0x7ffb33a71c58, 0, 1; +L_0xa75c20 .part/pv L_0xa75a40, 0, 1, 4; +L_0xa75cc0 .part v0xa388d0_0, 0, 1; +L_0xa754a0 .part v0xa388d0_0, 1, 1; +L_0xa755d0 .part RS_0x7ffb33a6ee38, 0, 1; +L_0xa76050 .part RS_0x7ffb33a6ee38, 0, 1; +L_0xa760f0 .part RS_0x7ffb33a6e748, 0, 1; +L_0xa75df0 .part RS_0x7ffb33a6e748, 0, 1; +L_0xa766c0 .part/pv L_0xa76580, 0, 1, 4; +L_0xa76190 .part v0xa388d0_0, 2, 1; +L_0xa76230 .part RS_0x7ffb33a71f28, 0, 1; +L_0xa76320 .part RS_0x7ffb33a71f58, 0, 1; +L_0xa76980 .part/pv L_0xa576c0, 0, 1, 4; +L_0xa76a20 .part RS_0x7ffb33a71f88, 0, 1; +L_0xa76c00 .part RS_0x7ffb33a71f88, 0, 1; +L_0xa76da0 .part RS_0x7ffb33a71fb8, 3, 1; +S_0xa175f0 .scope module, "test" "SLT32" 3 393, 3 273, S_0x9cd4a0; + .timescale -9 -12; +P_0xa15d68 .param/l "size" 3 305, +C4<0100>; +L_0xa5e190/d .functor NOT 1, L_0xa60dc0, C4<0>, C4<0>, C4<0>; +L_0xa5e190 .delay (10000,10000,10000) L_0xa5e190/d; +L_0xa60c20/d .functor AND 1, L_0xa60fd0, L_0xa61070, L_0xa5e190, C4<1>; +L_0xa60c20 .delay (20000,20000,20000) L_0xa60c20/d; +L_0xa62700/d .functor OR 1, L_0xa62ea0, C4<0>, C4<0>, C4<0>; +L_0xa62700 .delay (20000,20000,20000) L_0xa62700/d; +L_0xa63050/d .functor XOR 1, RS_0x7ffb33a703c8, L_0xa63100, C4<0>, C4<0>; +L_0xa63050 .delay (40000,40000,40000) L_0xa63050/d; +L_0xa62d30/d .functor NOT 1, RS_0x7ffb33a70488, C4<0>, C4<0>, C4<0>; +L_0xa62d30 .delay (10000,10000,10000) L_0xa62d30/d; +L_0xa62e40/d .functor NOT 1, L_0xa633a0, C4<0>, C4<0>, C4<0>; +L_0xa62e40 .delay (10000,10000,10000) L_0xa62e40/d; +L_0xa63440/d .functor AND 1, L_0xa62d30, L_0xa63580, C4<1>, C4<1>; +L_0xa63440 .delay (20000,20000,20000) L_0xa63440/d; +L_0xa631a0/d .functor AND 1, RS_0x7ffb33a70488, L_0xa62e40, C4<1>, C4<1>; +L_0xa631a0 .delay (20000,20000,20000) L_0xa631a0/d; +L_0xa637b0/d .functor AND 1, L_0xa63440, L_0xa60c20, C4<1>, C4<1>; +L_0xa637b0 .delay (20000,20000,20000) L_0xa637b0/d; +L_0xa638b0/d .functor AND 1, L_0xa631a0, L_0xa60c20, C4<1>, C4<1>; +L_0xa638b0 .delay (20000,20000,20000) L_0xa638b0/d; +L_0xa63a00/d .functor OR 1, L_0xa637b0, L_0xa638b0, C4<0>, C4<0>; +L_0xa63a00 .delay (20000,20000,20000) L_0xa63a00/d; +v0xa1e910_0 .alias "A", 3 0, v0xa37070_0; +RS_0x7ffb33a71b68 .resolv tri, L_0xa5bf20, L_0xa5e0f0, L_0xa60350, L_0xa62a90; +v0xa1e9b0_0 .net8 "AddSubSLTSum", 3 0, RS_0x7ffb33a71b68; 4 drivers +v0xa1ea50_0 .alias "B", 3 0, v0xa37220_0; +RS_0x7ffb33a71b98 .resolv tri, L_0xa5b570, L_0xa5d880, L_0xa5fa10, L_0xa62240; +v0xa1ead0_0 .net8 "CarryoutWire", 3 0, RS_0x7ffb33a71b98; 4 drivers +v0xa1eb80_0 .alias "Command", 2 0, v0xa373b0_0; +RS_0x7ffb33a71bc8 .resolv tri, L_0xa5b480, L_0xa5d720, L_0xa5f920, L_0xa62150; +v0xa1ec00_0 .net8 "NewVal", 3 0, RS_0x7ffb33a71bc8; 4 drivers +v0xa1eca0_0 .net "Res0OF1", 0 0, L_0xa631a0; 1 drivers +v0xa1ed40_0 .net "Res1OF0", 0 0, L_0xa63440; 1 drivers +v0xa1ede0_0 .alias "SLTSum", 3 0, v0xa38a50_0; +v0xa1ee80_0 .alias "SLTflag", 0 0, v0xa38ad0_0; +v0xa1ef00_0 .net "SLTflag0", 0 0, L_0xa637b0; 1 drivers +v0xa1efa0_0 .net "SLTflag1", 0 0, L_0xa638b0; 1 drivers +v0xa1f040_0 .net "SLTon", 0 0, L_0xa60c20; 1 drivers +v0xa1f0c0_0 .net *"_s49", 0 0, L_0xa60dc0; 1 drivers +v0xa1f1e0_0 .net *"_s51", 0 0, L_0xa60fd0; 1 drivers +v0xa1f280_0 .net *"_s53", 0 0, L_0xa61070; 1 drivers +v0xa1f140_0 .net *"_s73", 0 0, L_0xa62ea0; 1 drivers +v0xa1f3d0_0 .net/s *"_s74", 0 0, C4<0>; 1 drivers +v0xa1f4f0_0 .net *"_s77", 0 0, L_0xa63100; 1 drivers +v0xa1f570_0 .net *"_s79", 0 0, L_0xa633a0; 1 drivers +v0xa1f450_0 .net *"_s81", 0 0, L_0xa63580; 1 drivers +v0xa1f6a0_0 .alias "carryin", 3 0, v0xa37df0_0; +v0xa1f5f0_0 .alias "carryout", 0 0, v0xa38c80_0; +v0xa1f7e0_0 .net "nAddSubSLTSum", 0 0, L_0xa62e40; 1 drivers +v0xa1f720_0 .net "nCmd2", 0 0, L_0xa5e190; 1 drivers +v0xa1f930_0 .net "nOF", 0 0, L_0xa62d30; 1 drivers +v0xa1f860_0 .alias "overflow", 0 0, v0xa38d00_0; +v0xa1fa90_0 .alias "subtract", 3 0, v0xa38e00_0; +L_0xa5b480 .part/pv L_0xa5aff0, 1, 1, 4; +L_0xa5b570 .part/pv L_0xa5b340, 1, 1, 4; +L_0xa5b660 .part/pv L_0xa5ad20, 1, 1, 4; +L_0xa3d850 .part v0xa38650_0, 1, 1; +L_0xa5b910 .part v0xa38850_0, 1, 1; +L_0xa5ba40 .part RS_0x7ffb33a71b98, 0, 1; +L_0xa5bf20 .part/pv L_0xa5bde0, 1, 1, 4; +L_0xa5bfc0 .part RS_0x7ffb33a71bc8, 1, 1; +L_0xa5c560 .part/pv L_0xa5c420, 1, 1, 4; +L_0xa5c600 .part RS_0x7ffb33a71b68, 1, 1; +L_0xa5c7a0 .part RS_0x7ffb33a71b68, 1, 1; +L_0xa5d720 .part/pv L_0xa5d290, 2, 1, 4; +L_0xa5d880 .part/pv L_0xa5d5e0, 2, 1, 4; +L_0xa5d970 .part/pv L_0xa5cfc0, 2, 1, 4; +L_0xa5dae0 .part v0xa38650_0, 2, 1; +L_0xa5db80 .part v0xa38850_0, 2, 1; +L_0xa5dd40 .part RS_0x7ffb33a71b98, 1, 1; +L_0xa5e0f0 .part/pv L_0xa5dfb0, 2, 1, 4; +L_0xa5e2c0 .part RS_0x7ffb33a71bc8, 2, 1; +L_0xa5e700 .part/pv L_0xa5e5c0, 2, 1, 4; +L_0xa5e220 .part RS_0x7ffb33a71b68, 2, 1; +L_0xa5e8a0 .part RS_0x7ffb33a71b68, 2, 1; +L_0xa5f920 .part/pv L_0xa5f450, 3, 1, 4; +L_0xa5fa10 .part/pv L_0xa5f7c0, 3, 1, 4; +L_0xa5e990 .part/pv L_0xa5f180, 3, 1, 4; +L_0xa5fc20 .part v0xa38650_0, 3, 1; +L_0xa5fb00 .part v0xa38850_0, 3, 1; +L_0xa5fe30 .part RS_0x7ffb33a71b98, 2, 1; +L_0xa60350 .part/pv L_0xa60210, 3, 1, 4; +L_0xa603f0 .part RS_0x7ffb33a71bc8, 3, 1; +L_0xa60980 .part/pv L_0xa60840, 3, 1, 4; +L_0xa60a20 .part RS_0x7ffb33a71b68, 3, 1; +L_0xa604e0 .part RS_0x7ffb33a71b68, 3, 1; +L_0xa60dc0 .part v0xa388d0_0, 2, 1; +L_0xa60fd0 .part v0xa388d0_0, 0, 1; +L_0xa61070 .part v0xa388d0_0, 1, 1; +L_0xa62150 .part/pv L_0xa61ca0, 0, 1, 4; +L_0xa62240 .part/pv L_0xa61ff0, 0, 1, 4; +L_0xa61160 .part/pv L_0xa619d0, 0, 1, 4; +L_0xa62470 .part v0xa38650_0, 0, 1; +L_0xa62330 .part v0xa38850_0, 0, 1; +L_0xa62660 .part RS_0x7ffb33a704b8, 0, 1; +L_0xa62a90 .part/pv L_0xa62950, 0, 1, 4; +L_0xa62b30 .part RS_0x7ffb33a71bc8, 0, 1; +L_0xa62ea0 .part RS_0x7ffb33a71b98, 3, 1; +L_0xa63100 .part RS_0x7ffb33a71b98, 2, 1; +L_0xa633a0 .part RS_0x7ffb33a71b68, 3, 1; +L_0xa63580 .part RS_0x7ffb33a71b68, 3, 1; +L_0xa64010 .part/pv L_0xa63ed0, 0, 1, 4; +L_0xa640b0 .part RS_0x7ffb33a71b68, 0, 1; +S_0xa1d8f0 .scope module, "attempt2" "MiddleAddSubSLT" 3 300, 3 89, S_0xa175f0; + .timescale -9 -12; +L_0xa60e60/d .functor NOT 1, L_0xa62330, C4<0>, C4<0>, C4<0>; +L_0xa60e60 .delay (10000,10000,10000) L_0xa60e60/d; +L_0xa61870/d .functor NOT 1, L_0xa61930, C4<0>, C4<0>, C4<0>; +L_0xa61870 .delay (10000,10000,10000) L_0xa61870/d; +L_0xa619d0/d .functor AND 1, L_0xa61b10, L_0xa61870, C4<1>, C4<1>; +L_0xa619d0 .delay (20000,20000,20000) L_0xa619d0/d; +L_0xa61bb0/d .functor XOR 1, L_0xa62470, L_0xa61600, C4<0>, C4<0>; +L_0xa61bb0 .delay (40000,40000,40000) L_0xa61bb0/d; +L_0xa61ca0/d .functor XOR 1, L_0xa61bb0, L_0xa62660, C4<0>, C4<0>; +L_0xa61ca0 .delay (40000,40000,40000) L_0xa61ca0/d; +L_0xa61d90/d .functor AND 1, L_0xa62470, L_0xa61600, C4<1>, C4<1>; +L_0xa61d90 .delay (20000,20000,20000) L_0xa61d90/d; +L_0xa61f00/d .functor AND 1, L_0xa61bb0, L_0xa62660, C4<1>, C4<1>; +L_0xa61f00 .delay (20000,20000,20000) L_0xa61f00/d; +L_0xa61ff0/d .functor OR 1, L_0xa61d90, L_0xa61f00, C4<0>, C4<0>; +L_0xa61ff0 .delay (20000,20000,20000) L_0xa61ff0/d; +v0xa1df70_0 .net "A", 0 0, L_0xa62470; 1 drivers +v0xa1e030_0 .net "AandB", 0 0, L_0xa61d90; 1 drivers +v0xa1e0d0_0 .net "AddSubSLTSum", 0 0, L_0xa61ca0; 1 drivers +v0xa1e170_0 .net "AxorB", 0 0, L_0xa61bb0; 1 drivers +v0xa1e1f0_0 .net "B", 0 0, L_0xa62330; 1 drivers +v0xa1e2a0_0 .net "BornB", 0 0, L_0xa61600; 1 drivers +v0xa1e360_0 .net "CINandAxorB", 0 0, L_0xa61f00; 1 drivers +v0xa1e3e0_0 .alias "Command", 2 0, v0xa373b0_0; +v0xa1e460_0 .net *"_s3", 0 0, L_0xa61930; 1 drivers +v0xa1e4e0_0 .net *"_s5", 0 0, L_0xa61b10; 1 drivers +v0xa1e580_0 .net "carryin", 0 0, L_0xa62660; 1 drivers +v0xa1e620_0 .net "carryout", 0 0, L_0xa61ff0; 1 drivers +v0xa1e6c0_0 .net "nB", 0 0, L_0xa60e60; 1 drivers +v0xa1e770_0 .net "nCmd2", 0 0, L_0xa61870; 1 drivers +v0xa1e870_0 .net "subtract", 0 0, L_0xa619d0; 1 drivers +L_0xa617d0 .part v0xa388d0_0, 0, 1; +L_0xa61930 .part v0xa388d0_0, 2, 1; +L_0xa61b10 .part v0xa388d0_0, 0, 1; +S_0xa1d9e0 .scope module, "mux0" "TwoInMux" 3 105, 3 8, S_0xa1d8f0; + .timescale -9 -12; +L_0xa61320/d .functor NOT 1, L_0xa617d0, C4<0>, C4<0>, C4<0>; +L_0xa61320 .delay (10000,10000,10000) L_0xa61320/d; +L_0xa613e0/d .functor AND 1, L_0xa62330, L_0xa61320, C4<1>, C4<1>; +L_0xa613e0 .delay (20000,20000,20000) L_0xa613e0/d; +L_0xa614f0/d .functor AND 1, L_0xa60e60, L_0xa617d0, C4<1>, C4<1>; +L_0xa614f0 .delay (20000,20000,20000) L_0xa614f0/d; +L_0xa61600/d .functor OR 1, L_0xa613e0, L_0xa614f0, C4<0>, C4<0>; +L_0xa61600 .delay (20000,20000,20000) L_0xa61600/d; +v0xa1dad0_0 .net "S", 0 0, L_0xa617d0; 1 drivers +v0xa1db90_0 .alias "in0", 0 0, v0xa1e1f0_0; +v0xa1dc30_0 .alias "in1", 0 0, v0xa1e6c0_0; +v0xa1dcd0_0 .net "nS", 0 0, L_0xa61320; 1 drivers +v0xa1dd50_0 .net "out0", 0 0, L_0xa613e0; 1 drivers +v0xa1ddf0_0 .net "out1", 0 0, L_0xa614f0; 1 drivers +v0xa1ded0_0 .alias "outfinal", 0 0, v0xa1e2a0_0; +S_0xa1d380 .scope module, "setSLTres" "TwoInMux" 3 301, 3 8, S_0xa175f0; + .timescale -9 -12; +L_0xa62510/d .functor NOT 1, L_0xa60c20, C4<0>, C4<0>, C4<0>; +L_0xa62510 .delay (10000,10000,10000) L_0xa62510/d; +L_0xa625b0/d .functor AND 1, L_0xa62b30, L_0xa62510, C4<1>, C4<1>; +L_0xa625b0 .delay (20000,20000,20000) L_0xa625b0/d; +L_0xa628b0/d .functor AND 1, C4<0>, L_0xa60c20, C4<1>, C4<1>; +L_0xa628b0 .delay (20000,20000,20000) L_0xa628b0/d; +L_0xa62950/d .functor OR 1, L_0xa625b0, L_0xa628b0, C4<0>, C4<0>; +L_0xa62950 .delay (20000,20000,20000) L_0xa62950/d; +v0xa1d470_0 .alias "S", 0 0, v0xa1f040_0; +v0xa1d510_0 .net "in0", 0 0, L_0xa62b30; 1 drivers +v0xa1d5b0_0 .net "in1", 0 0, C4<0>; 1 drivers +v0xa1d650_0 .net "nS", 0 0, L_0xa62510; 1 drivers +v0xa1d6d0_0 .net "out0", 0 0, L_0xa625b0; 1 drivers +v0xa1d770_0 .net "out1", 0 0, L_0xa628b0; 1 drivers +v0xa1d850_0 .net "outfinal", 0 0, L_0xa62950; 1 drivers +S_0xa1ce60 .scope module, "FinalSLT" "TwoInMux" 3 328, 3 8, S_0xa175f0; + .timescale -9 -12; +L_0xa63b10/d .functor NOT 1, RS_0x7ffb33a70188, C4<0>, C4<0>, C4<0>; +L_0xa63b10 .delay (10000,10000,10000) L_0xa63b10/d; +L_0xa37740/d .functor AND 1, L_0xa640b0, L_0xa63b10, C4<1>, C4<1>; +L_0xa37740 .delay (20000,20000,20000) L_0xa37740/d; +L_0xa63e30/d .functor AND 1, RS_0x7ffb33a70188, RS_0x7ffb33a70188, C4<1>, C4<1>; +L_0xa63e30 .delay (20000,20000,20000) L_0xa63e30/d; +L_0xa63ed0/d .functor OR 1, L_0xa37740, L_0xa63e30, C4<0>, C4<0>; +L_0xa63ed0 .delay (20000,20000,20000) L_0xa63ed0/d; +v0xa1cf50_0 .alias "S", 0 0, v0xa38ad0_0; +v0xa1d020_0 .net "in0", 0 0, L_0xa640b0; 1 drivers +v0xa1d0a0_0 .alias "in1", 0 0, v0xa38ad0_0; +v0xa1d120_0 .net "nS", 0 0, L_0xa63b10; 1 drivers +v0xa1d1a0_0 .net "out0", 0 0, L_0xa37740; 1 drivers +v0xa1d240_0 .net "out1", 0 0, L_0xa63e30; 1 drivers +v0xa1d2e0_0 .net "outfinal", 0 0, L_0xa63ed0; 1 drivers +S_0xa1b150 .scope generate, "addbits[1]" "addbits[1]" 3 307, 3 307, S_0xa175f0; + .timescale -9 -12; +P_0xa1a938 .param/l "i" 3 307, +C4<01>; +S_0xa1be40 .scope module, "attempt" "MiddleAddSubSLT" 3 309, 3 89, S_0xa1b150; + .timescale -9 -12; +L_0xa5a340/d .functor NOT 1, L_0xa5b910, C4<0>, C4<0>, C4<0>; +L_0xa5a340 .delay (10000,10000,10000) L_0xa5a340/d; +L_0xa5abe0/d .functor NOT 1, L_0xa5ac80, C4<0>, C4<0>, C4<0>; +L_0xa5abe0 .delay (10000,10000,10000) L_0xa5abe0/d; +L_0xa5ad20/d .functor AND 1, L_0xa5ae60, L_0xa5abe0, C4<1>, C4<1>; +L_0xa5ad20 .delay (20000,20000,20000) L_0xa5ad20/d; +L_0xa5af00/d .functor XOR 1, L_0xa3d850, L_0xa5a9b0, C4<0>, C4<0>; +L_0xa5af00 .delay (40000,40000,40000) L_0xa5af00/d; +L_0xa5aff0/d .functor XOR 1, L_0xa5af00, L_0xa5ba40, C4<0>, C4<0>; +L_0xa5aff0 .delay (40000,40000,40000) L_0xa5aff0/d; +L_0xa5b0e0/d .functor AND 1, L_0xa3d850, L_0xa5a9b0, C4<1>, C4<1>; +L_0xa5b0e0 .delay (20000,20000,20000) L_0xa5b0e0/d; +L_0xa5b250/d .functor AND 1, L_0xa5af00, L_0xa5ba40, C4<1>, C4<1>; +L_0xa5b250 .delay (20000,20000,20000) L_0xa5b250/d; +L_0xa5b340/d .functor OR 1, L_0xa5b0e0, L_0xa5b250, C4<0>, C4<0>; +L_0xa5b340 .delay (20000,20000,20000) L_0xa5b340/d; +v0xa1c4c0_0 .net "A", 0 0, L_0xa3d850; 1 drivers +v0xa1c580_0 .net "AandB", 0 0, L_0xa5b0e0; 1 drivers +v0xa1c620_0 .net "AddSubSLTSum", 0 0, L_0xa5aff0; 1 drivers +v0xa1c6c0_0 .net "AxorB", 0 0, L_0xa5af00; 1 drivers +v0xa1c740_0 .net "B", 0 0, L_0xa5b910; 1 drivers +v0xa1c7f0_0 .net "BornB", 0 0, L_0xa5a9b0; 1 drivers +v0xa1c8b0_0 .net "CINandAxorB", 0 0, L_0xa5b250; 1 drivers +v0xa1c930_0 .alias "Command", 2 0, v0xa373b0_0; +v0xa1c9b0_0 .net *"_s3", 0 0, L_0xa5ac80; 1 drivers +v0xa1ca30_0 .net *"_s5", 0 0, L_0xa5ae60; 1 drivers +v0xa1cad0_0 .net "carryin", 0 0, L_0xa5ba40; 1 drivers +v0xa1cb70_0 .net "carryout", 0 0, L_0xa5b340; 1 drivers +v0xa1cc10_0 .net "nB", 0 0, L_0xa5a340; 1 drivers +v0xa1ccc0_0 .net "nCmd2", 0 0, L_0xa5abe0; 1 drivers +v0xa1cdc0_0 .net "subtract", 0 0, L_0xa5ad20; 1 drivers +L_0xa5ab40 .part v0xa388d0_0, 0, 1; +L_0xa5ac80 .part v0xa388d0_0, 2, 1; +L_0xa5ae60 .part v0xa388d0_0, 0, 1; +S_0xa1bf30 .scope module, "mux0" "TwoInMux" 3 105, 3 8, S_0xa1be40; + .timescale -9 -12; +L_0xa5a730/d .functor NOT 1, L_0xa5ab40, C4<0>, C4<0>, C4<0>; +L_0xa5a730 .delay (10000,10000,10000) L_0xa5a730/d; +L_0xa5a7d0/d .functor AND 1, L_0xa5b910, L_0xa5a730, C4<1>, C4<1>; +L_0xa5a7d0 .delay (20000,20000,20000) L_0xa5a7d0/d; +L_0xa5a8c0/d .functor AND 1, L_0xa5a340, L_0xa5ab40, C4<1>, C4<1>; +L_0xa5a8c0 .delay (20000,20000,20000) L_0xa5a8c0/d; +L_0xa5a9b0/d .functor OR 1, L_0xa5a7d0, L_0xa5a8c0, C4<0>, C4<0>; +L_0xa5a9b0 .delay (20000,20000,20000) L_0xa5a9b0/d; +v0xa1c020_0 .net "S", 0 0, L_0xa5ab40; 1 drivers +v0xa1c0e0_0 .alias "in0", 0 0, v0xa1c740_0; +v0xa1c180_0 .alias "in1", 0 0, v0xa1cc10_0; +v0xa1c220_0 .net "nS", 0 0, L_0xa5a730; 1 drivers +v0xa1c2a0_0 .net "out0", 0 0, L_0xa5a7d0; 1 drivers +v0xa1c340_0 .net "out1", 0 0, L_0xa5a8c0; 1 drivers +v0xa1c420_0 .alias "outfinal", 0 0, v0xa1c7f0_0; +S_0xa1b8d0 .scope module, "setSLTres2" "TwoInMux" 3 310, 3 8, S_0xa1b150; + .timescale -9 -12; +L_0xa5bae0/d .functor NOT 1, L_0xa60c20, C4<0>, C4<0>, C4<0>; +L_0xa5bae0 .delay (10000,10000,10000) L_0xa5bae0/d; +L_0xa5bc50/d .functor AND 1, L_0xa5bfc0, L_0xa5bae0, C4<1>, C4<1>; +L_0xa5bc50 .delay (20000,20000,20000) L_0xa5bc50/d; +L_0xa5bd40/d .functor AND 1, C4<0>, L_0xa60c20, C4<1>, C4<1>; +L_0xa5bd40 .delay (20000,20000,20000) L_0xa5bd40/d; +L_0xa5bde0/d .functor OR 1, L_0xa5bc50, L_0xa5bd40, C4<0>, C4<0>; +L_0xa5bde0 .delay (20000,20000,20000) L_0xa5bde0/d; +v0xa1b9c0_0 .alias "S", 0 0, v0xa1f040_0; +v0xa1ba60_0 .net "in0", 0 0, L_0xa5bfc0; 1 drivers +v0xa1bb00_0 .net "in1", 0 0, C4<0>; 1 drivers +v0xa1bba0_0 .net "nS", 0 0, L_0xa5bae0; 1 drivers +v0xa1bc20_0 .net "out0", 0 0, L_0xa5bc50; 1 drivers +v0xa1bcc0_0 .net "out1", 0 0, L_0xa5bd40; 1 drivers +v0xa1bda0_0 .net "outfinal", 0 0, L_0xa5bde0; 1 drivers +S_0xa1b2c0 .scope module, "setSLTres3" "TwoInMux" 3 311, 3 8, S_0xa1b150; + .timescale -9 -12; +L_0xa5c1a0/d .functor NOT 1, L_0xa60c20, C4<0>, C4<0>, C4<0>; +L_0xa5c1a0 .delay (10000,10000,10000) L_0xa5c1a0/d; +L_0xa5c290/d .functor AND 1, L_0xa5c600, L_0xa5c1a0, C4<1>, C4<1>; +L_0xa5c290 .delay (20000,20000,20000) L_0xa5c290/d; +L_0xa5c380/d .functor AND 1, L_0xa5c7a0, L_0xa60c20, C4<1>, C4<1>; +L_0xa5c380 .delay (20000,20000,20000) L_0xa5c380/d; +L_0xa5c420/d .functor OR 1, L_0xa5c290, L_0xa5c380, C4<0>, C4<0>; +L_0xa5c420 .delay (20000,20000,20000) L_0xa5c420/d; +v0xa1b3b0_0 .alias "S", 0 0, v0xa1f040_0; +v0xa1b4c0_0 .net "in0", 0 0, L_0xa5c600; 1 drivers +v0xa1b560_0 .net "in1", 0 0, L_0xa5c7a0; 1 drivers +v0xa1b600_0 .net "nS", 0 0, L_0xa5c1a0; 1 drivers +v0xa1b6b0_0 .net "out0", 0 0, L_0xa5c290; 1 drivers +v0xa1b750_0 .net "out1", 0 0, L_0xa5c380; 1 drivers +v0xa1b830_0 .net "outfinal", 0 0, L_0xa5c420; 1 drivers +S_0xa193d0 .scope generate, "addbits[2]" "addbits[2]" 3 307, 3 307, S_0xa175f0; + .timescale -9 -12; +P_0xa18de8 .param/l "i" 3 307, +C4<010>; +S_0xa19fe0 .scope module, "attempt" "MiddleAddSubSLT" 3 309, 3 89, S_0xa193d0; + .timescale -9 -12; +L_0xa5c840/d .functor NOT 1, L_0xa5db80, C4<0>, C4<0>, C4<0>; +L_0xa5c840 .delay (10000,10000,10000) L_0xa5c840/d; +L_0xa5ce80/d .functor NOT 1, L_0xa5cf20, C4<0>, C4<0>, C4<0>; +L_0xa5ce80 .delay (10000,10000,10000) L_0xa5ce80/d; +L_0xa5cfc0/d .functor AND 1, L_0xa5d100, L_0xa5ce80, C4<1>, C4<1>; +L_0xa5cfc0 .delay (20000,20000,20000) L_0xa5cfc0/d; +L_0xa5d1a0/d .functor XOR 1, L_0xa5dae0, L_0xa5cc50, C4<0>, C4<0>; +L_0xa5d1a0 .delay (40000,40000,40000) L_0xa5d1a0/d; +L_0xa5d290/d .functor XOR 1, L_0xa5d1a0, L_0xa5dd40, C4<0>, C4<0>; +L_0xa5d290 .delay (40000,40000,40000) L_0xa5d290/d; +L_0xa5d380/d .functor AND 1, L_0xa5dae0, L_0xa5cc50, C4<1>, C4<1>; +L_0xa5d380 .delay (20000,20000,20000) L_0xa5d380/d; +L_0xa5d4f0/d .functor AND 1, L_0xa5d1a0, L_0xa5dd40, C4<1>, C4<1>; +L_0xa5d4f0 .delay (20000,20000,20000) L_0xa5d4f0/d; +L_0xa5d5e0/d .functor OR 1, L_0xa5d380, L_0xa5d4f0, C4<0>, C4<0>; +L_0xa5d5e0 .delay (20000,20000,20000) L_0xa5d5e0/d; +v0xa1a580_0 .net "A", 0 0, L_0xa5dae0; 1 drivers +v0xa1a640_0 .net "AandB", 0 0, L_0xa5d380; 1 drivers +v0xa1a6e0_0 .net "AddSubSLTSum", 0 0, L_0xa5d290; 1 drivers +v0xa1a780_0 .net "AxorB", 0 0, L_0xa5d1a0; 1 drivers +v0xa1a800_0 .net "B", 0 0, L_0xa5db80; 1 drivers +v0xa1a8b0_0 .net "BornB", 0 0, L_0xa5cc50; 1 drivers +v0xa1a970_0 .net "CINandAxorB", 0 0, L_0xa5d4f0; 1 drivers +v0xa1a9f0_0 .alias "Command", 2 0, v0xa373b0_0; +v0xa10390_0 .net *"_s3", 0 0, L_0xa5cf20; 1 drivers +v0xa10410_0 .net *"_s5", 0 0, L_0xa5d100; 1 drivers +v0xa1ad50_0 .net "carryin", 0 0, L_0xa5dd40; 1 drivers +v0xa1adf0_0 .net "carryout", 0 0, L_0xa5d5e0; 1 drivers +v0xa1af00_0 .net "nB", 0 0, L_0xa5c840; 1 drivers +v0xa1afb0_0 .net "nCmd2", 0 0, L_0xa5ce80; 1 drivers +v0xa1b0b0_0 .net "subtract", 0 0, L_0xa5cfc0; 1 drivers +L_0xa5cde0 .part v0xa388d0_0, 0, 1; +L_0xa5cf20 .part v0xa388d0_0, 2, 1; +L_0xa5d100 .part v0xa388d0_0, 0, 1; +S_0xa1a0d0 .scope module, "mux0" "TwoInMux" 3 105, 3 8, S_0xa19fe0; + .timescale -9 -12; +L_0xa5c9d0/d .functor NOT 1, L_0xa5cde0, C4<0>, C4<0>, C4<0>; +L_0xa5c9d0 .delay (10000,10000,10000) L_0xa5c9d0/d; +L_0xa5ca70/d .functor AND 1, L_0xa5db80, L_0xa5c9d0, C4<1>, C4<1>; +L_0xa5ca70 .delay (20000,20000,20000) L_0xa5ca70/d; +L_0xa5cb60/d .functor AND 1, L_0xa5c840, L_0xa5cde0, C4<1>, C4<1>; +L_0xa5cb60 .delay (20000,20000,20000) L_0xa5cb60/d; +L_0xa5cc50/d .functor OR 1, L_0xa5ca70, L_0xa5cb60, C4<0>, C4<0>; +L_0xa5cc50 .delay (20000,20000,20000) L_0xa5cc50/d; +v0xa1a1c0_0 .net "S", 0 0, L_0xa5cde0; 1 drivers +v0xa1a240_0 .alias "in0", 0 0, v0xa1a800_0; +v0xa1a2c0_0 .alias "in1", 0 0, v0xa1af00_0; +v0xa1a340_0 .net "nS", 0 0, L_0xa5c9d0; 1 drivers +v0xa1a3c0_0 .net "out0", 0 0, L_0xa5ca70; 1 drivers +v0xa1a440_0 .net "out1", 0 0, L_0xa5cb60; 1 drivers +v0xa1a4e0_0 .alias "outfinal", 0 0, v0xa1a8b0_0; +S_0xa19a90 .scope module, "setSLTres2" "TwoInMux" 3 310, 3 8, S_0xa193d0; + .timescale -9 -12; +L_0xa5c740/d .functor NOT 1, L_0xa60c20, C4<0>, C4<0>, C4<0>; +L_0xa5c740 .delay (10000,10000,10000) L_0xa5c740/d; +L_0xa5de70/d .functor AND 1, L_0xa5e2c0, L_0xa5c740, C4<1>, C4<1>; +L_0xa5de70 .delay (20000,20000,20000) L_0xa5de70/d; +L_0xa5df10/d .functor AND 1, C4<0>, L_0xa60c20, C4<1>, C4<1>; +L_0xa5df10 .delay (20000,20000,20000) L_0xa5df10/d; +L_0xa5dfb0/d .functor OR 1, L_0xa5de70, L_0xa5df10, C4<0>, C4<0>; +L_0xa5dfb0 .delay (20000,20000,20000) L_0xa5dfb0/d; +v0xa19b80_0 .alias "S", 0 0, v0xa1f040_0; +v0xa19c20_0 .net "in0", 0 0, L_0xa5e2c0; 1 drivers +v0xa19cc0_0 .net "in1", 0 0, C4<0>; 1 drivers +v0xa19d60_0 .net "nS", 0 0, L_0xa5c740; 1 drivers +v0xa19de0_0 .net "out0", 0 0, L_0xa5de70; 1 drivers +v0xa19e80_0 .net "out1", 0 0, L_0xa5df10; 1 drivers +v0xa19f60_0 .net "outfinal", 0 0, L_0xa5dfb0; 1 drivers +S_0xa19540 .scope module, "setSLTres3" "TwoInMux" 3 311, 3 8, S_0xa193d0; + .timescale -9 -12; +L_0xa4a1d0/d .functor NOT 1, L_0xa60c20, C4<0>, C4<0>, C4<0>; +L_0xa4a1d0 .delay (10000,10000,10000) L_0xa4a1d0/d; +L_0xa5e430/d .functor AND 1, L_0xa5e220, L_0xa4a1d0, C4<1>, C4<1>; +L_0xa5e430 .delay (20000,20000,20000) L_0xa5e430/d; +L_0xa5e520/d .functor AND 1, L_0xa5e8a0, L_0xa60c20, C4<1>, C4<1>; +L_0xa5e520 .delay (20000,20000,20000) L_0xa5e520/d; +L_0xa5e5c0/d .functor OR 1, L_0xa5e430, L_0xa5e520, C4<0>, C4<0>; +L_0xa5e5c0 .delay (20000,20000,20000) L_0xa5e5c0/d; +v0xa19630_0 .alias "S", 0 0, v0xa1f040_0; +v0xa196b0_0 .net "in0", 0 0, L_0xa5e220; 1 drivers +v0xa19750_0 .net "in1", 0 0, L_0xa5e8a0; 1 drivers +v0xa197f0_0 .net "nS", 0 0, L_0xa4a1d0; 1 drivers +v0xa19870_0 .net "out0", 0 0, L_0xa5e430; 1 drivers +v0xa19910_0 .net "out1", 0 0, L_0xa5e520; 1 drivers +v0xa199f0_0 .net "outfinal", 0 0, L_0xa5e5c0; 1 drivers +S_0xa17760 .scope generate, "addbits[3]" "addbits[3]" 3 307, 3 307, S_0xa175f0; + .timescale -9 -12; +P_0xa17858 .param/l "i" 3 307, +C4<011>; +S_0xa183b0 .scope module, "attempt" "MiddleAddSubSLT" 3 309, 3 89, S_0xa17760; + .timescale -9 -12; +L_0xa5e7a0/d .functor NOT 1, L_0xa5fb00, C4<0>, C4<0>, C4<0>; +L_0xa5e7a0 .delay (10000,10000,10000) L_0xa5e7a0/d; +L_0xa5f020/d .functor NOT 1, L_0xa5f0e0, C4<0>, C4<0>, C4<0>; +L_0xa5f020 .delay (10000,10000,10000) L_0xa5f020/d; +L_0xa5f180/d .functor AND 1, L_0xa5f2c0, L_0xa5f020, C4<1>, C4<1>; +L_0xa5f180 .delay (20000,20000,20000) L_0xa5f180/d; +L_0xa5f360/d .functor XOR 1, L_0xa5fc20, L_0xa5edb0, C4<0>, C4<0>; +L_0xa5f360 .delay (40000,40000,40000) L_0xa5f360/d; +L_0xa5f450/d .functor XOR 1, L_0xa5f360, L_0xa5fe30, C4<0>, C4<0>; +L_0xa5f450 .delay (40000,40000,40000) L_0xa5f450/d; +L_0xa5f540/d .functor AND 1, L_0xa5fc20, L_0xa5edb0, C4<1>, C4<1>; +L_0xa5f540 .delay (20000,20000,20000) L_0xa5f540/d; +L_0xa5f6b0/d .functor AND 1, L_0xa5f360, L_0xa5fe30, C4<1>, C4<1>; +L_0xa5f6b0 .delay (20000,20000,20000) L_0xa5f6b0/d; +L_0xa5f7c0/d .functor OR 1, L_0xa5f540, L_0xa5f6b0, C4<0>, C4<0>; +L_0xa5f7c0 .delay (20000,20000,20000) L_0xa5f7c0/d; +v0xa18a30_0 .net "A", 0 0, L_0xa5fc20; 1 drivers +v0xa18af0_0 .net "AandB", 0 0, L_0xa5f540; 1 drivers +v0xa18b90_0 .net "AddSubSLTSum", 0 0, L_0xa5f450; 1 drivers +v0xa18c30_0 .net "AxorB", 0 0, L_0xa5f360; 1 drivers +v0xa18cb0_0 .net "B", 0 0, L_0xa5fb00; 1 drivers +v0xa18d60_0 .net "BornB", 0 0, L_0xa5edb0; 1 drivers +v0xa18e20_0 .net "CINandAxorB", 0 0, L_0xa5f6b0; 1 drivers +v0xa18ea0_0 .alias "Command", 2 0, v0xa373b0_0; +v0xa18f20_0 .net *"_s3", 0 0, L_0xa5f0e0; 1 drivers +v0xa18fa0_0 .net *"_s5", 0 0, L_0xa5f2c0; 1 drivers +v0xa19040_0 .net "carryin", 0 0, L_0xa5fe30; 1 drivers +v0xa190e0_0 .net "carryout", 0 0, L_0xa5f7c0; 1 drivers +v0xa19180_0 .net "nB", 0 0, L_0xa5e7a0; 1 drivers +v0xa19230_0 .net "nCmd2", 0 0, L_0xa5f020; 1 drivers +v0xa19330_0 .net "subtract", 0 0, L_0xa5f180; 1 drivers +L_0xa5ef80 .part v0xa388d0_0, 0, 1; +L_0xa5f0e0 .part v0xa388d0_0, 2, 1; +L_0xa5f2c0 .part v0xa388d0_0, 0, 1; +S_0xa184a0 .scope module, "mux0" "TwoInMux" 3 105, 3 8, S_0xa183b0; + .timescale -9 -12; +L_0xa5eb30/d .functor NOT 1, L_0xa5ef80, C4<0>, C4<0>, C4<0>; +L_0xa5eb30 .delay (10000,10000,10000) L_0xa5eb30/d; +L_0xa5ebd0/d .functor AND 1, L_0xa5fb00, L_0xa5eb30, C4<1>, C4<1>; +L_0xa5ebd0 .delay (20000,20000,20000) L_0xa5ebd0/d; +L_0xa5ecc0/d .functor AND 1, L_0xa5e7a0, L_0xa5ef80, C4<1>, C4<1>; +L_0xa5ecc0 .delay (20000,20000,20000) L_0xa5ecc0/d; +L_0xa5edb0/d .functor OR 1, L_0xa5ebd0, L_0xa5ecc0, C4<0>, C4<0>; +L_0xa5edb0 .delay (20000,20000,20000) L_0xa5edb0/d; +v0xa18590_0 .net "S", 0 0, L_0xa5ef80; 1 drivers +v0xa18650_0 .alias "in0", 0 0, v0xa18cb0_0; +v0xa186f0_0 .alias "in1", 0 0, v0xa19180_0; +v0xa18790_0 .net "nS", 0 0, L_0xa5eb30; 1 drivers +v0xa18810_0 .net "out0", 0 0, L_0xa5ebd0; 1 drivers +v0xa188b0_0 .net "out1", 0 0, L_0xa5ecc0; 1 drivers +v0xa18990_0 .alias "outfinal", 0 0, v0xa18d60_0; +S_0xa17e60 .scope module, "setSLTres2" "TwoInMux" 3 310, 3 8, S_0xa17760; + .timescale -9 -12; +L_0xa5fcc0/d .functor NOT 1, L_0xa60c20, C4<0>, C4<0>, C4<0>; +L_0xa5fcc0 .delay (10000,10000,10000) L_0xa5fcc0/d; +L_0xa5fd20/d .functor AND 1, L_0xa603f0, L_0xa5fcc0, C4<1>, C4<1>; +L_0xa5fd20 .delay (20000,20000,20000) L_0xa5fd20/d; +L_0xa5bbd0/d .functor AND 1, C4<0>, L_0xa60c20, C4<1>, C4<1>; +L_0xa5bbd0 .delay (20000,20000,20000) L_0xa5bbd0/d; +L_0xa60210/d .functor OR 1, L_0xa5fd20, L_0xa5bbd0, C4<0>, C4<0>; +L_0xa60210 .delay (20000,20000,20000) L_0xa60210/d; +v0xa17f50_0 .alias "S", 0 0, v0xa1f040_0; +v0xa17ff0_0 .net "in0", 0 0, L_0xa603f0; 1 drivers +v0xa18070_0 .net "in1", 0 0, C4<0>; 1 drivers +v0xa18110_0 .net "nS", 0 0, L_0xa5fcc0; 1 drivers +v0xa18190_0 .net "out0", 0 0, L_0xa5fd20; 1 drivers +v0xa18230_0 .net "out1", 0 0, L_0xa5bbd0; 1 drivers +v0xa18310_0 .net "outfinal", 0 0, L_0xa60210; 1 drivers +S_0xa178f0 .scope module, "setSLTres3" "TwoInMux" 3 311, 3 8, S_0xa17760; + .timescale -9 -12; +L_0xa5ff60/d .functor NOT 1, L_0xa60c20, C4<0>, C4<0>, C4<0>; +L_0xa5ff60 .delay (10000,10000,10000) L_0xa5ff60/d; +L_0xa60690/d .functor AND 1, L_0xa60a20, L_0xa5ff60, C4<1>, C4<1>; +L_0xa60690 .delay (20000,20000,20000) L_0xa60690/d; +L_0xa607a0/d .functor AND 1, L_0xa604e0, L_0xa60c20, C4<1>, C4<1>; +L_0xa607a0 .delay (20000,20000,20000) L_0xa607a0/d; +L_0xa60840/d .functor OR 1, L_0xa60690, L_0xa607a0, C4<0>, C4<0>; +L_0xa60840 .delay (20000,20000,20000) L_0xa60840/d; +v0xa179e0_0 .alias "S", 0 0, v0xa1f040_0; +v0xa17a80_0 .net "in0", 0 0, L_0xa60a20; 1 drivers +v0xa17b20_0 .net "in1", 0 0, L_0xa604e0; 1 drivers +v0xa17bc0_0 .net "nS", 0 0, L_0xa5ff60; 1 drivers +v0xa17c40_0 .net "out0", 0 0, L_0xa60690; 1 drivers +v0xa17ce0_0 .net "out1", 0 0, L_0xa607a0; 1 drivers +v0xa17dc0_0 .net "outfinal", 0 0, L_0xa60840; 1 drivers +S_0xa10680 .scope module, "trial" "AddSubSLT32" 3 394, 3 205, S_0x9cd4a0; + .timescale -9 -12; +P_0xa10778 .param/l "size" 3 237, +C4<0100>; +L_0xa65e70/d .functor NOT 1, L_0xa69ad0, C4<0>, C4<0>, C4<0>; +L_0xa65e70 .delay (10000,10000,10000) L_0xa65e70/d; +L_0xa69b70/d .functor AND 1, L_0xa69cb0, L_0xa698d0, L_0xa65e70, C4<1>; +L_0xa69b70 .delay (20000,20000,20000) L_0xa69b70/d; +L_0xa6c130/d .functor OR 1, L_0xa6c220, C4<0>, C4<0>, C4<0>; +L_0xa6c130 .delay (20000,20000,20000) L_0xa6c130/d; +L_0xa6bfb0/d .functor XOR 1, RS_0x7ffb33a703c8, L_0xa6c500, C4<0>, C4<0>; +L_0xa6bfb0 .delay (40000,40000,40000) L_0xa6bfb0/d; +L_0xa699e0/d .functor NOT 1, RS_0x7ffb33a70488, C4<0>, C4<0>, C4<0>; +L_0xa699e0 .delay (10000,10000,10000) L_0xa699e0/d; +L_0xa40c30/d .functor NOT 1, L_0xa6c880, C4<0>, C4<0>, C4<0>; +L_0xa40c30 .delay (10000,10000,10000) L_0xa40c30/d; +L_0xa6c3d0/d .functor AND 1, L_0xa699e0, L_0xa6cab0, C4<1>, C4<1>; +L_0xa6c3d0 .delay (20000,20000,20000) L_0xa6c3d0/d; +L_0xa6cb50/d .functor AND 1, RS_0x7ffb33a70488, L_0xa40c30, C4<1>, C4<1>; +L_0xa6cb50 .delay (20000,20000,20000) L_0xa6cb50/d; +L_0xa6cc90/d .functor AND 1, L_0xa6c3d0, L_0xa69b70, C4<1>, C4<1>; +L_0xa6cc90 .delay (20000,20000,20000) L_0xa6cc90/d; +L_0xa6cd90/d .functor AND 1, L_0xa6cb50, L_0xa69b70, C4<1>, C4<1>; +L_0xa6cd90 .delay (20000,20000,20000) L_0xa6cd90/d; +L_0xa6cee0/d .functor OR 1, L_0xa6cc90, L_0xa6cd90, C4<0>, C4<0>; +L_0xa6cee0 .delay (20000,20000,20000) L_0xa6cee0/d; +v0xa16350_0 .alias "A", 3 0, v0xa37070_0; +v0xa163f0_0 .alias "AddSubSLTSum", 3 0, v0xa386d0_0; +v0xa16490_0 .alias "B", 3 0, v0xa37220_0; +RS_0x7ffb33a700c8 .resolv tri, L_0xa652a0, L_0xa66fd0, L_0xa68c00, L_0xa69d50; +v0xa16560_0 .net8 "CarryoutWire", 3 0, RS_0x7ffb33a700c8; 4 drivers +v0xa165e0_0 .alias "Command", 2 0, v0xa373b0_0; +RS_0x7ffb33a700f8 .resolv tri, L_0xa651b0, L_0xa66ee0, L_0xa68b10, L_0xa46410; +v0xa16660_0 .net8 "NewVal", 3 0, RS_0x7ffb33a700f8; 4 drivers +v0xa16700_0 .net "Res0OF1", 0 0, L_0xa6cb50; 1 drivers +v0xa167a0_0 .net "Res1OF0", 0 0, L_0xa6c3d0; 1 drivers +v0xa16890_0 .alias "SLTflag", 0 0, v0xa38ad0_0; +v0xa16930_0 .net "SLTflag0", 0 0, L_0xa6cc90; 1 drivers +v0xa169d0_0 .net "SLTflag1", 0 0, L_0xa6cd90; 1 drivers +v0xa16a70_0 .net "SLTon", 0 0, L_0xa69b70; 1 drivers +v0xa16b80_0 .net *"_s37", 0 0, L_0xa69ad0; 1 drivers +v0xa16c20_0 .net *"_s39", 0 0, L_0xa69cb0; 1 drivers +v0xa16d40_0 .net *"_s41", 0 0, L_0xa698d0; 1 drivers +v0xa16de0_0 .net *"_s61", 0 0, L_0xa6c220; 1 drivers +v0xa16ca0_0 .net/s *"_s62", 0 0, C4<0>; 1 drivers +v0xa16f30_0 .net *"_s65", 0 0, L_0xa6c500; 1 drivers +v0xa17050_0 .net *"_s67", 0 0, L_0xa6c880; 1 drivers +v0xa170d0_0 .net *"_s69", 0 0, L_0xa6cab0; 1 drivers +v0xa16fb0_0 .alias "carryin", 3 0, v0xa37df0_0; +v0xa17200_0 .alias "carryout", 0 0, v0xa38c80_0; +v0xa17150_0 .net "nAddSubSLTSum", 0 0, L_0xa40c30; 1 drivers +v0xa17340_0 .net "nCmd2", 0 0, L_0xa65e70; 1 drivers +v0xa172a0_0 .net "nOF", 0 0, L_0xa699e0; 1 drivers +v0xa17490_0 .alias "overflow", 0 0, v0xa38d00_0; +v0xa173e0_0 .alias "subtract", 3 0, v0xa38e00_0; +L_0xa651b0 .part/pv L_0xa64d00, 1, 1, 4; +L_0xa652a0 .part/pv L_0xa65050, 1, 1, 4; +L_0xa65390 .part/pv L_0xa64a30, 1, 1, 4; +L_0xa65480 .part v0xa38650_0, 1, 1; +L_0xa65520 .part v0xa38850_0, 1, 1; +L_0xa65650 .part RS_0x7ffb33a700c8, 0, 1; +L_0xa65ad0 .part/pv L_0xa65990, 1, 1, 4; +L_0xa40850 .part RS_0x7ffb33a700f8, 1, 1; +L_0xa66ee0 .part/pv L_0xa66a30, 2, 1, 4; +L_0xa66fd0 .part/pv L_0xa66d80, 2, 1, 4; +L_0xa67120 .part/pv L_0xa66760, 2, 1, 4; +L_0xa671c0 .part v0xa38650_0, 2, 1; +L_0xa67260 .part v0xa38850_0, 2, 1; +L_0xa67390 .part RS_0x7ffb33a700c8, 1, 1; +L_0xa67820 .part/pv L_0xa67730, 2, 1, 4; +L_0xa678c0 .part RS_0x7ffb33a700f8, 2, 1; +L_0xa68b10 .part/pv L_0xa68660, 3, 1, 4; +L_0xa68c00 .part/pv L_0xa689b0, 3, 1, 4; +L_0xa68d90 .part/pv L_0xa68390, 3, 1, 4; +L_0xa68e30 .part v0xa38650_0, 3, 1; +L_0xa68cf0 .part v0xa38850_0, 3, 1; +L_0xa46df0 .part RS_0x7ffb33a700c8, 2, 1; +L_0xa69740 .part/pv L_0xa47050, 3, 1, 4; +L_0xa697e0 .part RS_0x7ffb33a700f8, 3, 1; +L_0xa69ad0 .part v0xa388d0_0, 2, 1; +L_0xa69cb0 .part v0xa388d0_0, 0, 1; +L_0xa698d0 .part v0xa388d0_0, 1, 1; +L_0xa46410 .part/pv L_0xa45f40, 0, 1, 4; +L_0xa69d50 .part/pv L_0xa462b0, 0, 1, 4; +L_0xa6b7f0 .part/pv L_0xa6a600, 0, 1, 4; +L_0xa46500 .part v0xa38650_0, 0, 1; +L_0xa6b9e0 .part v0xa38850_0, 0, 1; +L_0xa6b8e0 .part RS_0x7ffb33a704b8, 0, 1; +L_0xa6be60 .part/pv L_0xa6bd20, 0, 1, 4; +L_0xa6bb10 .part RS_0x7ffb33a700f8, 0, 1; +L_0xa6c220 .part RS_0x7ffb33a700c8, 3, 1; +L_0xa6c500 .part RS_0x7ffb33a700c8, 2, 1; +L_0xa6c880 .part RS_0x7ffb33a70098, 3, 1; +L_0xa6cab0 .part RS_0x7ffb33a70098, 3, 1; +S_0xa15330 .scope module, "attempt2" "MiddleAddSubSLT" 3 233, 3 89, S_0xa10680; + .timescale -9 -12; +L_0xa69e80/d .functor NOT 1, L_0xa6b9e0, C4<0>, C4<0>, C4<0>; +L_0xa69e80 .delay (10000,10000,10000) L_0xa69e80/d; +L_0xa6a4c0/d .functor NOT 1, L_0xa6a560, C4<0>, C4<0>, C4<0>; +L_0xa6a4c0 .delay (10000,10000,10000) L_0xa6a4c0/d; +L_0xa6a600/d .functor AND 1, L_0xa6a740, L_0xa6a4c0, C4<1>, C4<1>; +L_0xa6a600 .delay (20000,20000,20000) L_0xa6a600/d; +L_0xa45e50/d .functor XOR 1, L_0xa46500, L_0xa6a290, C4<0>, C4<0>; +L_0xa45e50 .delay (40000,40000,40000) L_0xa45e50/d; +L_0xa45f40/d .functor XOR 1, L_0xa45e50, L_0xa6b8e0, C4<0>, C4<0>; +L_0xa45f40 .delay (40000,40000,40000) L_0xa45f40/d; +L_0xa46030/d .functor AND 1, L_0xa46500, L_0xa6a290, C4<1>, C4<1>; +L_0xa46030 .delay (20000,20000,20000) L_0xa46030/d; +L_0xa461a0/d .functor AND 1, L_0xa45e50, L_0xa6b8e0, C4<1>, C4<1>; +L_0xa461a0 .delay (20000,20000,20000) L_0xa461a0/d; +L_0xa462b0/d .functor OR 1, L_0xa46030, L_0xa461a0, C4<0>, C4<0>; +L_0xa462b0 .delay (20000,20000,20000) L_0xa462b0/d; +v0xa159b0_0 .net "A", 0 0, L_0xa46500; 1 drivers +v0xa15a70_0 .net "AandB", 0 0, L_0xa46030; 1 drivers +v0xa15b10_0 .net "AddSubSLTSum", 0 0, L_0xa45f40; 1 drivers +v0xa15bb0_0 .net "AxorB", 0 0, L_0xa45e50; 1 drivers +v0xa15c30_0 .net "B", 0 0, L_0xa6b9e0; 1 drivers +v0xa15ce0_0 .net "BornB", 0 0, L_0xa6a290; 1 drivers +v0xa15da0_0 .net "CINandAxorB", 0 0, L_0xa461a0; 1 drivers +v0xa15e20_0 .alias "Command", 2 0, v0xa373b0_0; +v0xa15ea0_0 .net *"_s3", 0 0, L_0xa6a560; 1 drivers +v0xa15f20_0 .net *"_s5", 0 0, L_0xa6a740; 1 drivers +v0xa15fc0_0 .net "carryin", 0 0, L_0xa6b8e0; 1 drivers +v0xa16060_0 .net "carryout", 0 0, L_0xa462b0; 1 drivers +v0xa16100_0 .net "nB", 0 0, L_0xa69e80; 1 drivers +v0xa161b0_0 .net "nCmd2", 0 0, L_0xa6a4c0; 1 drivers +v0xa162b0_0 .net "subtract", 0 0, L_0xa6a600; 1 drivers +L_0xa6a420 .part v0xa388d0_0, 0, 1; +L_0xa6a560 .part v0xa388d0_0, 2, 1; +L_0xa6a740 .part v0xa388d0_0, 0, 1; +S_0xa15420 .scope module, "mux0" "TwoInMux" 3 105, 3 8, S_0xa15330; + .timescale -9 -12; +L_0xa6a010/d .functor NOT 1, L_0xa6a420, C4<0>, C4<0>, C4<0>; +L_0xa6a010 .delay (10000,10000,10000) L_0xa6a010/d; +L_0xa6a0b0/d .functor AND 1, L_0xa6b9e0, L_0xa6a010, C4<1>, C4<1>; +L_0xa6a0b0 .delay (20000,20000,20000) L_0xa6a0b0/d; +L_0xa6a1a0/d .functor AND 1, L_0xa69e80, L_0xa6a420, C4<1>, C4<1>; +L_0xa6a1a0 .delay (20000,20000,20000) L_0xa6a1a0/d; +L_0xa6a290/d .functor OR 1, L_0xa6a0b0, L_0xa6a1a0, C4<0>, C4<0>; +L_0xa6a290 .delay (20000,20000,20000) L_0xa6a290/d; +v0xa15510_0 .net "S", 0 0, L_0xa6a420; 1 drivers +v0xa155d0_0 .alias "in0", 0 0, v0xa15c30_0; +v0xa15670_0 .alias "in1", 0 0, v0xa16100_0; +v0xa15710_0 .net "nS", 0 0, L_0xa6a010; 1 drivers +v0xa15790_0 .net "out0", 0 0, L_0xa6a0b0; 1 drivers +v0xa15830_0 .net "out1", 0 0, L_0xa6a1a0; 1 drivers +v0xa15910_0 .alias "outfinal", 0 0, v0xa15ce0_0; +S_0xa14dd0 .scope module, "setSLTres" "TwoInMux" 3 234, 3 8, S_0xa10680; + .timescale -9 -12; +L_0xa6b980/d .functor NOT 1, L_0xa69b70, C4<0>, C4<0>, C4<0>; +L_0xa6b980 .delay (10000,10000,10000) L_0xa6b980/d; +L_0xa6bc20/d .functor AND 1, L_0xa6bb10, L_0xa6b980, C4<1>, C4<1>; +L_0xa6bc20 .delay (20000,20000,20000) L_0xa6bc20/d; +L_0xa6bc80/d .functor AND 1, C4<0>, L_0xa69b70, C4<1>, C4<1>; +L_0xa6bc80 .delay (20000,20000,20000) L_0xa6bc80/d; +L_0xa6bd20/d .functor OR 1, L_0xa6bc20, L_0xa6bc80, C4<0>, C4<0>; +L_0xa6bd20 .delay (20000,20000,20000) L_0xa6bd20/d; +v0xa14ec0_0 .alias "S", 0 0, v0xa16a70_0; +v0xa14f60_0 .net "in0", 0 0, L_0xa6bb10; 1 drivers +v0xa15000_0 .net "in1", 0 0, C4<0>; 1 drivers +v0xa150a0_0 .net "nS", 0 0, L_0xa6b980; 1 drivers +v0xa15150_0 .net "out0", 0 0, L_0xa6bc20; 1 drivers +v0xa151f0_0 .net "out1", 0 0, L_0xa6bc80; 1 drivers +v0xa15290_0 .net "outfinal", 0 0, L_0xa6bd20; 1 drivers +S_0xa136f0 .scope generate, "addbits[1]" "addbits[1]" 3 239, 3 239, S_0xa10680; + .timescale -9 -12; +P_0xa13108 .param/l "i" 3 239, +C4<01>; +S_0xa13db0 .scope module, "attempt" "MiddleAddSubSLT" 3 241, 3 89, S_0xa136f0; + .timescale -9 -12; +L_0xa63620/d .functor NOT 1, L_0xa65520, C4<0>, C4<0>, C4<0>; +L_0xa63620 .delay (10000,10000,10000) L_0xa63620/d; +L_0xa648d0/d .functor NOT 1, L_0xa64990, C4<0>, C4<0>, C4<0>; +L_0xa648d0 .delay (10000,10000,10000) L_0xa648d0/d; +L_0xa64a30/d .functor AND 1, L_0xa64b70, L_0xa648d0, C4<1>, C4<1>; +L_0xa64a30 .delay (20000,20000,20000) L_0xa64a30/d; +L_0xa64c10/d .functor XOR 1, L_0xa65480, L_0xa64660, C4<0>, C4<0>; +L_0xa64c10 .delay (40000,40000,40000) L_0xa64c10/d; +L_0xa64d00/d .functor XOR 1, L_0xa64c10, L_0xa65650, C4<0>, C4<0>; +L_0xa64d00 .delay (40000,40000,40000) L_0xa64d00/d; +L_0xa64df0/d .functor AND 1, L_0xa65480, L_0xa64660, C4<1>, C4<1>; +L_0xa64df0 .delay (20000,20000,20000) L_0xa64df0/d; +L_0xa64f60/d .functor AND 1, L_0xa64c10, L_0xa65650, C4<1>, C4<1>; +L_0xa64f60 .delay (20000,20000,20000) L_0xa64f60/d; +L_0xa65050/d .functor OR 1, L_0xa64df0, L_0xa64f60, C4<0>, C4<0>; +L_0xa65050 .delay (20000,20000,20000) L_0xa65050/d; +v0xa14430_0 .net "A", 0 0, L_0xa65480; 1 drivers +v0xa144f0_0 .net "AandB", 0 0, L_0xa64df0; 1 drivers +v0xa14590_0 .net "AddSubSLTSum", 0 0, L_0xa64d00; 1 drivers +v0xa14630_0 .net "AxorB", 0 0, L_0xa64c10; 1 drivers +v0xa146b0_0 .net "B", 0 0, L_0xa65520; 1 drivers +v0xa14760_0 .net "BornB", 0 0, L_0xa64660; 1 drivers +v0xa14820_0 .net "CINandAxorB", 0 0, L_0xa64f60; 1 drivers +v0xa148a0_0 .alias "Command", 2 0, v0xa373b0_0; +v0xa14920_0 .net *"_s3", 0 0, L_0xa64990; 1 drivers +v0xa149a0_0 .net *"_s5", 0 0, L_0xa64b70; 1 drivers +v0xa14a40_0 .net "carryin", 0 0, L_0xa65650; 1 drivers +v0xa14ae0_0 .net "carryout", 0 0, L_0xa65050; 1 drivers +v0xa14b80_0 .net "nB", 0 0, L_0xa63620; 1 drivers +v0xa14c30_0 .net "nCmd2", 0 0, L_0xa648d0; 1 drivers +v0xa14d30_0 .net "subtract", 0 0, L_0xa64a30; 1 drivers +L_0xa64830 .part v0xa388d0_0, 0, 1; +L_0xa64990 .part v0xa388d0_0, 2, 1; +L_0xa64b70 .part v0xa388d0_0, 0, 1; +S_0xa13ea0 .scope module, "mux0" "TwoInMux" 3 105, 3 8, S_0xa13db0; + .timescale -9 -12; +L_0xa64380/d .functor NOT 1, L_0xa64830, C4<0>, C4<0>, C4<0>; +L_0xa64380 .delay (10000,10000,10000) L_0xa64380/d; +L_0xa64440/d .functor AND 1, L_0xa65520, L_0xa64380, C4<1>, C4<1>; +L_0xa64440 .delay (20000,20000,20000) L_0xa64440/d; +L_0xa64550/d .functor AND 1, L_0xa63620, L_0xa64830, C4<1>, C4<1>; +L_0xa64550 .delay (20000,20000,20000) L_0xa64550/d; +L_0xa64660/d .functor OR 1, L_0xa64440, L_0xa64550, C4<0>, C4<0>; +L_0xa64660 .delay (20000,20000,20000) L_0xa64660/d; +v0xa13f90_0 .net "S", 0 0, L_0xa64830; 1 drivers +v0xa14050_0 .alias "in0", 0 0, v0xa146b0_0; +v0xa140f0_0 .alias "in1", 0 0, v0xa14b80_0; +v0xa14190_0 .net "nS", 0 0, L_0xa64380; 1 drivers +v0xa14210_0 .net "out0", 0 0, L_0xa64440; 1 drivers +v0xa142b0_0 .net "out1", 0 0, L_0xa64550; 1 drivers +v0xa14390_0 .alias "outfinal", 0 0, v0xa14760_0; +S_0xa13860 .scope module, "setSLTres" "TwoInMux" 3 242, 3 8, S_0xa136f0; + .timescale -9 -12; +L_0xa656f0/d .functor NOT 1, L_0xa69b70, C4<0>, C4<0>, C4<0>; +L_0xa656f0 .delay (10000,10000,10000) L_0xa656f0/d; +L_0xa657e0/d .functor AND 1, L_0xa40850, L_0xa656f0, C4<1>, C4<1>; +L_0xa657e0 .delay (20000,20000,20000) L_0xa657e0/d; +L_0xa658f0/d .functor AND 1, C4<0>, L_0xa69b70, C4<1>, C4<1>; +L_0xa658f0 .delay (20000,20000,20000) L_0xa658f0/d; +L_0xa65990/d .functor OR 1, L_0xa657e0, L_0xa658f0, C4<0>, C4<0>; +L_0xa65990 .delay (20000,20000,20000) L_0xa65990/d; +v0xa13950_0 .alias "S", 0 0, v0xa16a70_0; +v0xa139d0_0 .net "in0", 0 0, L_0xa40850; 1 drivers +v0xa13a70_0 .net "in1", 0 0, C4<0>; 1 drivers +v0xa13b10_0 .net "nS", 0 0, L_0xa656f0; 1 drivers +v0xa13b90_0 .net "out0", 0 0, L_0xa657e0; 1 drivers +v0xa13c30_0 .net "out1", 0 0, L_0xa658f0; 1 drivers +v0xa13d10_0 .net "outfinal", 0 0, L_0xa65990; 1 drivers +S_0xa11fd0 .scope generate, "addbits[2]" "addbits[2]" 3 239, 3 239, S_0xa10680; + .timescale -9 -12; +P_0xa11918 .param/l "i" 3 239, +C4<010>; +S_0xa126d0 .scope module, "attempt" "MiddleAddSubSLT" 3 241, 3 89, S_0xa11fd0; + .timescale -9 -12; +L_0xa65f00/d .functor NOT 1, L_0xa67260, C4<0>, C4<0>, C4<0>; +L_0xa65f00 .delay (10000,10000,10000) L_0xa65f00/d; +L_0xa66600/d .functor NOT 1, L_0xa666c0, C4<0>, C4<0>, C4<0>; +L_0xa66600 .delay (10000,10000,10000) L_0xa66600/d; +L_0xa66760/d .functor AND 1, L_0xa668a0, L_0xa66600, C4<1>, C4<1>; +L_0xa66760 .delay (20000,20000,20000) L_0xa66760/d; +L_0xa66940/d .functor XOR 1, L_0xa671c0, L_0xa66390, C4<0>, C4<0>; +L_0xa66940 .delay (40000,40000,40000) L_0xa66940/d; +L_0xa66a30/d .functor XOR 1, L_0xa66940, L_0xa67390, C4<0>, C4<0>; +L_0xa66a30 .delay (40000,40000,40000) L_0xa66a30/d; +L_0xa66b20/d .functor AND 1, L_0xa671c0, L_0xa66390, C4<1>, C4<1>; +L_0xa66b20 .delay (20000,20000,20000) L_0xa66b20/d; +L_0xa66c90/d .functor AND 1, L_0xa66940, L_0xa67390, C4<1>, C4<1>; +L_0xa66c90 .delay (20000,20000,20000) L_0xa66c90/d; +L_0xa66d80/d .functor OR 1, L_0xa66b20, L_0xa66c90, C4<0>, C4<0>; +L_0xa66d80 .delay (20000,20000,20000) L_0xa66d80/d; +v0xa12d50_0 .net "A", 0 0, L_0xa671c0; 1 drivers +v0xa12e10_0 .net "AandB", 0 0, L_0xa66b20; 1 drivers +v0xa12eb0_0 .net "AddSubSLTSum", 0 0, L_0xa66a30; 1 drivers +v0xa12f50_0 .net "AxorB", 0 0, L_0xa66940; 1 drivers +v0xa12fd0_0 .net "B", 0 0, L_0xa67260; 1 drivers +v0xa13080_0 .net "BornB", 0 0, L_0xa66390; 1 drivers +v0xa13140_0 .net "CINandAxorB", 0 0, L_0xa66c90; 1 drivers +v0xa131c0_0 .alias "Command", 2 0, v0xa373b0_0; +v0xa13240_0 .net *"_s3", 0 0, L_0xa666c0; 1 drivers +v0xa132c0_0 .net *"_s5", 0 0, L_0xa668a0; 1 drivers +v0xa13360_0 .net "carryin", 0 0, L_0xa67390; 1 drivers +v0xa13400_0 .net "carryout", 0 0, L_0xa66d80; 1 drivers +v0xa134a0_0 .net "nB", 0 0, L_0xa65f00; 1 drivers +v0xa13550_0 .net "nCmd2", 0 0, L_0xa66600; 1 drivers +v0xa13650_0 .net "subtract", 0 0, L_0xa66760; 1 drivers +L_0xa66560 .part v0xa388d0_0, 0, 1; +L_0xa666c0 .part v0xa388d0_0, 2, 1; +L_0xa668a0 .part v0xa388d0_0, 0, 1; +S_0xa127c0 .scope module, "mux0" "TwoInMux" 3 105, 3 8, S_0xa126d0; + .timescale -9 -12; +L_0xa660b0/d .functor NOT 1, L_0xa66560, C4<0>, C4<0>, C4<0>; +L_0xa660b0 .delay (10000,10000,10000) L_0xa660b0/d; +L_0xa66170/d .functor AND 1, L_0xa67260, L_0xa660b0, C4<1>, C4<1>; +L_0xa66170 .delay (20000,20000,20000) L_0xa66170/d; +L_0xa66280/d .functor AND 1, L_0xa65f00, L_0xa66560, C4<1>, C4<1>; +L_0xa66280 .delay (20000,20000,20000) L_0xa66280/d; +L_0xa66390/d .functor OR 1, L_0xa66170, L_0xa66280, C4<0>, C4<0>; +L_0xa66390 .delay (20000,20000,20000) L_0xa66390/d; +v0xa128b0_0 .net "S", 0 0, L_0xa66560; 1 drivers +v0xa12970_0 .alias "in0", 0 0, v0xa12fd0_0; +v0xa12a10_0 .alias "in1", 0 0, v0xa134a0_0; +v0xa12ab0_0 .net "nS", 0 0, L_0xa660b0; 1 drivers +v0xa12b30_0 .net "out0", 0 0, L_0xa66170; 1 drivers +v0xa12bd0_0 .net "out1", 0 0, L_0xa66280; 1 drivers +v0xa12cb0_0 .alias "outfinal", 0 0, v0xa13080_0; +S_0xa12140 .scope module, "setSLTres" "TwoInMux" 3 242, 3 8, S_0xa11fd0; + .timescale -9 -12; +L_0xa670c0/d .functor NOT 1, L_0xa69b70, C4<0>, C4<0>, C4<0>; +L_0xa670c0 .delay (10000,10000,10000) L_0xa670c0/d; +L_0xa67500/d .functor AND 1, L_0xa678c0, L_0xa670c0, C4<1>, C4<1>; +L_0xa67500 .delay (20000,20000,20000) L_0xa67500/d; +L_0xa675c0/d .functor AND 1, C4<0>, L_0xa69b70, C4<1>, C4<1>; +L_0xa675c0 .delay (20000,20000,20000) L_0xa675c0/d; +L_0xa67730/d .functor OR 1, L_0xa67500, L_0xa675c0, C4<0>, C4<0>; +L_0xa67730 .delay (20000,20000,20000) L_0xa67730/d; +v0xa12230_0 .alias "S", 0 0, v0xa16a70_0; +v0xa122e0_0 .net "in0", 0 0, L_0xa678c0; 1 drivers +v0xa12360_0 .net "in1", 0 0, C4<0>; 1 drivers +v0xa12400_0 .net "nS", 0 0, L_0xa670c0; 1 drivers +v0xa124b0_0 .net "out0", 0 0, L_0xa67500; 1 drivers +v0xa12550_0 .net "out1", 0 0, L_0xa675c0; 1 drivers +v0xa12630_0 .net "outfinal", 0 0, L_0xa67730; 1 drivers +S_0xa107f0 .scope generate, "addbits[3]" "addbits[3]" 3 239, 3 239, S_0xa10680; + .timescale -9 -12; +P_0xa108e8 .param/l "i" 3 239, +C4<011>; +S_0xa10ee0 .scope module, "attempt" "MiddleAddSubSLT" 3 241, 3 89, S_0xa107f0; + .timescale -9 -12; +L_0xa67b10/d .functor NOT 1, L_0xa68cf0, C4<0>, C4<0>, C4<0>; +L_0xa67b10 .delay (10000,10000,10000) L_0xa67b10/d; +L_0xa68230/d .functor NOT 1, L_0xa682f0, C4<0>, C4<0>, C4<0>; +L_0xa68230 .delay (10000,10000,10000) L_0xa68230/d; +L_0xa68390/d .functor AND 1, L_0xa684d0, L_0xa68230, C4<1>, C4<1>; +L_0xa68390 .delay (20000,20000,20000) L_0xa68390/d; +L_0xa68570/d .functor XOR 1, L_0xa68e30, L_0xa67fc0, C4<0>, C4<0>; +L_0xa68570 .delay (40000,40000,40000) L_0xa68570/d; +L_0xa68660/d .functor XOR 1, L_0xa68570, L_0xa46df0, C4<0>, C4<0>; +L_0xa68660 .delay (40000,40000,40000) L_0xa68660/d; +L_0xa68750/d .functor AND 1, L_0xa68e30, L_0xa67fc0, C4<1>, C4<1>; +L_0xa68750 .delay (20000,20000,20000) L_0xa68750/d; +L_0xa688c0/d .functor AND 1, L_0xa68570, L_0xa46df0, C4<1>, C4<1>; +L_0xa688c0 .delay (20000,20000,20000) L_0xa688c0/d; +L_0xa689b0/d .functor OR 1, L_0xa68750, L_0xa688c0, C4<0>, C4<0>; +L_0xa689b0 .delay (20000,20000,20000) L_0xa689b0/d; +v0xa11560_0 .net "A", 0 0, L_0xa68e30; 1 drivers +v0xa11620_0 .net "AandB", 0 0, L_0xa68750; 1 drivers +v0xa116c0_0 .net "AddSubSLTSum", 0 0, L_0xa68660; 1 drivers +v0xa11760_0 .net "AxorB", 0 0, L_0xa68570; 1 drivers +v0xa117e0_0 .net "B", 0 0, L_0xa68cf0; 1 drivers +v0xa11890_0 .net "BornB", 0 0, L_0xa67fc0; 1 drivers +v0xa11950_0 .net "CINandAxorB", 0 0, L_0xa688c0; 1 drivers +v0xa119d0_0 .alias "Command", 2 0, v0xa373b0_0; +v0xa11a50_0 .net *"_s3", 0 0, L_0xa682f0; 1 drivers +v0xa11ad0_0 .net *"_s5", 0 0, L_0xa684d0; 1 drivers +v0xa11bd0_0 .net "carryin", 0 0, L_0xa46df0; 1 drivers +v0xa11c70_0 .net "carryout", 0 0, L_0xa689b0; 1 drivers +v0xa11d80_0 .net "nB", 0 0, L_0xa67b10; 1 drivers +v0xa11e30_0 .net "nCmd2", 0 0, L_0xa68230; 1 drivers +v0xa11f30_0 .net "subtract", 0 0, L_0xa68390; 1 drivers +L_0xa68190 .part v0xa388d0_0, 0, 1; +L_0xa682f0 .part v0xa388d0_0, 2, 1; +L_0xa684d0 .part v0xa388d0_0, 0, 1; +S_0xa10fd0 .scope module, "mux0" "TwoInMux" 3 105, 3 8, S_0xa10ee0; + .timescale -9 -12; +L_0xa67ce0/d .functor NOT 1, L_0xa68190, C4<0>, C4<0>, C4<0>; +L_0xa67ce0 .delay (10000,10000,10000) L_0xa67ce0/d; +L_0xa67da0/d .functor AND 1, L_0xa68cf0, L_0xa67ce0, C4<1>, C4<1>; +L_0xa67da0 .delay (20000,20000,20000) L_0xa67da0/d; +L_0xa67eb0/d .functor AND 1, L_0xa67b10, L_0xa68190, C4<1>, C4<1>; +L_0xa67eb0 .delay (20000,20000,20000) L_0xa67eb0/d; +L_0xa67fc0/d .functor OR 1, L_0xa67da0, L_0xa67eb0, C4<0>, C4<0>; +L_0xa67fc0 .delay (20000,20000,20000) L_0xa67fc0/d; +v0xa110c0_0 .net "S", 0 0, L_0xa68190; 1 drivers +v0xa11180_0 .alias "in0", 0 0, v0xa117e0_0; +v0xa11220_0 .alias "in1", 0 0, v0xa11d80_0; +v0xa112c0_0 .net "nS", 0 0, L_0xa67ce0; 1 drivers +v0xa11340_0 .net "out0", 0 0, L_0xa67da0; 1 drivers +v0xa113e0_0 .net "out1", 0 0, L_0xa67eb0; 1 drivers +v0xa114c0_0 .alias "outfinal", 0 0, v0xa11890_0; +S_0xa10960 .scope module, "setSLTres" "TwoInMux" 3 242, 3 8, S_0xa107f0; + .timescale -9 -12; +L_0xa5d810/d .functor NOT 1, L_0xa69b70, C4<0>, C4<0>, C4<0>; +L_0xa5d810 .delay (10000,10000,10000) L_0xa5d810/d; +L_0xa5da60/d .functor AND 1, L_0xa697e0, L_0xa5d810, C4<1>, C4<1>; +L_0xa5da60 .delay (20000,20000,20000) L_0xa5da60/d; +L_0xa46d00/d .functor AND 1, C4<0>, L_0xa69b70, C4<1>, C4<1>; +L_0xa46d00 .delay (20000,20000,20000) L_0xa46d00/d; +L_0xa47050/d .functor OR 1, L_0xa5da60, L_0xa46d00, C4<0>, C4<0>; +L_0xa47050 .delay (20000,20000,20000) L_0xa47050/d; +v0xa10a50_0 .alias "S", 0 0, v0xa16a70_0; +v0xa10ad0_0 .net "in0", 0 0, L_0xa697e0; 1 drivers +v0xa10b70_0 .net "in1", 0 0, C4<0>; 1 drivers +v0xa10c10_0 .net "nS", 0 0, L_0xa5d810; 1 drivers +v0xa10cc0_0 .net "out0", 0 0, L_0xa5da60; 1 drivers +v0xa10d60_0 .net "out1", 0 0, L_0xa46d00; 1 drivers +v0xa10e40_0 .net "outfinal", 0 0, L_0xa47050; 1 drivers +S_0xa0d440 .scope module, "trial1" "AndNand32" 3 395, 3 154, S_0x9cd4a0; + .timescale -9 -12; +P_0xa0cec8 .param/l "size" 3 161, +C4<0100>; +v0xa0d330_0 .alias "A", 3 0, v0xa37070_0; +v0xa104a0_0 .alias "AndNandOut", 3 0, v0xa387d0_0; +v0xa10520_0 .alias "B", 3 0, v0xa37220_0; +v0xa105d0_0 .alias "Command", 2 0, v0xa373b0_0; +L_0xa6d7c0 .part/pv L_0xa6d550, 1, 1, 4; +L_0xa6d880 .part v0xa38650_0, 1, 1; +L_0xa6d920 .part v0xa38850_0, 1, 1; +L_0xa6e230 .part/pv L_0xa6dfc0, 2, 1, 4; +L_0xa6e2d0 .part v0xa38650_0, 2, 1; +L_0xa6e370 .part v0xa38850_0, 2, 1; +L_0xa6eca0 .part/pv L_0xa6ea30, 3, 1, 4; +L_0xa543c0 .part v0xa38650_0, 3, 1; +L_0xa6ef50 .part v0xa38850_0, 3, 1; +L_0xa6f800 .part/pv L_0xa6f590, 0, 1, 4; +L_0xa6f900 .part v0xa38650_0, 0, 1; +L_0xa6f9a0 .part v0xa38850_0, 0, 1; +S_0xa0f960 .scope module, "attempt2" "AndNand" 3 165, 3 48, S_0xa0d440; + .timescale -9 -12; +L_0xa6f040/d .functor NAND 1, L_0xa6f900, L_0xa6f9a0, C4<1>, C4<1>; +L_0xa6f040 .delay (10000,10000,10000) L_0xa6f040/d; +L_0xa6f140/d .functor NOT 1, L_0xa6f040, C4<0>, C4<0>, C4<0>; +L_0xa6f140 .delay (10000,10000,10000) L_0xa6f140/d; +v0xa0ff80_0 .net "A", 0 0, L_0xa6f900; 1 drivers +v0xa10040_0 .net "AandB", 0 0, L_0xa6f140; 1 drivers +v0xa100c0_0 .net "AnandB", 0 0, L_0xa6f040; 1 drivers +v0xa10170_0 .net "AndNandOut", 0 0, L_0xa6f590; 1 drivers +v0xa10250_0 .net "B", 0 0, L_0xa6f9a0; 1 drivers +v0xa102d0_0 .alias "Command", 2 0, v0xa373b0_0; +L_0xa6f760 .part v0xa388d0_0, 0, 1; +S_0xa0fa50 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0xa0f960; + .timescale -9 -12; +L_0xa6f270/d .functor NOT 1, L_0xa6f760, C4<0>, C4<0>, C4<0>; +L_0xa6f270 .delay (10000,10000,10000) L_0xa6f270/d; +L_0xa6f330/d .functor AND 1, L_0xa6f140, L_0xa6f270, C4<1>, C4<1>; +L_0xa6f330 .delay (20000,20000,20000) L_0xa6f330/d; +L_0xa6f440/d .functor AND 1, L_0xa6f040, L_0xa6f760, C4<1>, C4<1>; +L_0xa6f440 .delay (20000,20000,20000) L_0xa6f440/d; +L_0xa6f590/d .functor OR 1, L_0xa6f330, L_0xa6f440, C4<0>, C4<0>; +L_0xa6f590 .delay (20000,20000,20000) L_0xa6f590/d; +v0xa0fb40_0 .net "S", 0 0, L_0xa6f760; 1 drivers +v0xa0fbc0_0 .alias "in0", 0 0, v0xa10040_0; +v0xa0fc40_0 .alias "in1", 0 0, v0xa100c0_0; +v0xa0fce0_0 .net "nS", 0 0, L_0xa6f270; 1 drivers +v0xa0fd60_0 .net "out0", 0 0, L_0xa6f330; 1 drivers +v0xa0fe00_0 .net "out1", 0 0, L_0xa6f440; 1 drivers +v0xa0fee0_0 .alias "outfinal", 0 0, v0xa10170_0; +S_0xa0eda0 .scope generate, "andbits[1]" "andbits[1]" 3 169, 3 169, S_0xa0d440; + .timescale -9 -12; +P_0xa0ee98 .param/l "i" 3 169, +C4<01>; +S_0xa0ef10 .scope module, "attempt" "AndNand" 3 171, 3 48, S_0xa0eda0; + .timescale -9 -12; +L_0xa6cff0/d .functor NAND 1, L_0xa6d880, L_0xa6d920, C4<1>, C4<1>; +L_0xa6cff0 .delay (10000,10000,10000) L_0xa6cff0/d; +L_0xa6d100/d .functor NOT 1, L_0xa6cff0, C4<0>, C4<0>, C4<0>; +L_0xa6d100 .delay (10000,10000,10000) L_0xa6d100/d; +v0xa0f550_0 .net "A", 0 0, L_0xa6d880; 1 drivers +v0xa0f610_0 .net "AandB", 0 0, L_0xa6d100; 1 drivers +v0xa0f690_0 .net "AnandB", 0 0, L_0xa6cff0; 1 drivers +v0xa0f740_0 .net "AndNandOut", 0 0, L_0xa6d550; 1 drivers +v0xa0f820_0 .net "B", 0 0, L_0xa6d920; 1 drivers +v0xa0f8a0_0 .alias "Command", 2 0, v0xa373b0_0; +L_0xa6d720 .part v0xa388d0_0, 0, 1; +S_0xa0f000 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0xa0ef10; + .timescale -9 -12; +L_0xa6d230/d .functor NOT 1, L_0xa6d720, C4<0>, C4<0>, C4<0>; +L_0xa6d230 .delay (10000,10000,10000) L_0xa6d230/d; +L_0xa6d2f0/d .functor AND 1, L_0xa6d100, L_0xa6d230, C4<1>, C4<1>; +L_0xa6d2f0 .delay (20000,20000,20000) L_0xa6d2f0/d; +L_0xa6d400/d .functor AND 1, L_0xa6cff0, L_0xa6d720, C4<1>, C4<1>; +L_0xa6d400 .delay (20000,20000,20000) L_0xa6d400/d; +L_0xa6d550/d .functor OR 1, L_0xa6d2f0, L_0xa6d400, C4<0>, C4<0>; +L_0xa6d550 .delay (20000,20000,20000) L_0xa6d550/d; +v0xa0f0f0_0 .net "S", 0 0, L_0xa6d720; 1 drivers +v0xa0f170_0 .alias "in0", 0 0, v0xa0f610_0; +v0xa0f210_0 .alias "in1", 0 0, v0xa0f690_0; +v0xa0f2b0_0 .net "nS", 0 0, L_0xa6d230; 1 drivers +v0xa0f330_0 .net "out0", 0 0, L_0xa6d2f0; 1 drivers +v0xa0f3d0_0 .net "out1", 0 0, L_0xa6d400; 1 drivers +v0xa0f4b0_0 .alias "outfinal", 0 0, v0xa0f740_0; +S_0xa0e1e0 .scope generate, "andbits[2]" "andbits[2]" 3 169, 3 169, S_0xa0d440; + .timescale -9 -12; +P_0xa0e2d8 .param/l "i" 3 169, +C4<010>; +S_0xa0e350 .scope module, "attempt" "AndNand" 3 171, 3 48, S_0xa0e1e0; + .timescale -9 -12; +L_0xa6da10/d .functor NAND 1, L_0xa6e2d0, L_0xa6e370, C4<1>, C4<1>; +L_0xa6da10 .delay (10000,10000,10000) L_0xa6da10/d; +L_0xa6db70/d .functor NOT 1, L_0xa6da10, C4<0>, C4<0>, C4<0>; +L_0xa6db70 .delay (10000,10000,10000) L_0xa6db70/d; +v0xa0e990_0 .net "A", 0 0, L_0xa6e2d0; 1 drivers +v0xa0ea50_0 .net "AandB", 0 0, L_0xa6db70; 1 drivers +v0xa0ead0_0 .net "AnandB", 0 0, L_0xa6da10; 1 drivers +v0xa0eb80_0 .net "AndNandOut", 0 0, L_0xa6dfc0; 1 drivers +v0xa0ec60_0 .net "B", 0 0, L_0xa6e370; 1 drivers +v0xa0ece0_0 .alias "Command", 2 0, v0xa373b0_0; +L_0xa6e190 .part v0xa388d0_0, 0, 1; +S_0xa0e440 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0xa0e350; + .timescale -9 -12; +L_0xa6dca0/d .functor NOT 1, L_0xa6e190, C4<0>, C4<0>, C4<0>; +L_0xa6dca0 .delay (10000,10000,10000) L_0xa6dca0/d; +L_0xa6dd60/d .functor AND 1, L_0xa6db70, L_0xa6dca0, C4<1>, C4<1>; +L_0xa6dd60 .delay (20000,20000,20000) L_0xa6dd60/d; +L_0xa6de70/d .functor AND 1, L_0xa6da10, L_0xa6e190, C4<1>, C4<1>; +L_0xa6de70 .delay (20000,20000,20000) L_0xa6de70/d; +L_0xa6dfc0/d .functor OR 1, L_0xa6dd60, L_0xa6de70, C4<0>, C4<0>; +L_0xa6dfc0 .delay (20000,20000,20000) L_0xa6dfc0/d; +v0xa0e530_0 .net "S", 0 0, L_0xa6e190; 1 drivers +v0xa0e5b0_0 .alias "in0", 0 0, v0xa0ea50_0; +v0xa0e650_0 .alias "in1", 0 0, v0xa0ead0_0; +v0xa0e6f0_0 .net "nS", 0 0, L_0xa6dca0; 1 drivers +v0xa0e770_0 .net "out0", 0 0, L_0xa6dd60; 1 drivers +v0xa0e810_0 .net "out1", 0 0, L_0xa6de70; 1 drivers +v0xa0e8f0_0 .alias "outfinal", 0 0, v0xa0eb80_0; +S_0xa0d5b0 .scope generate, "andbits[3]" "andbits[3]" 3 169, 3 169, S_0xa0d440; + .timescale -9 -12; +P_0xa0d6a8 .param/l "i" 3 169, +C4<011>; +S_0xa0d740 .scope module, "attempt" "AndNand" 3 171, 3 48, S_0xa0d5b0; + .timescale -9 -12; +L_0xa6e4a0/d .functor NAND 1, L_0xa543c0, L_0xa6ef50, C4<1>, C4<1>; +L_0xa6e4a0 .delay (10000,10000,10000) L_0xa6e4a0/d; +L_0xa6e5e0/d .functor NOT 1, L_0xa6e4a0, C4<0>, C4<0>, C4<0>; +L_0xa6e5e0 .delay (10000,10000,10000) L_0xa6e5e0/d; +v0xa0ddd0_0 .net "A", 0 0, L_0xa543c0; 1 drivers +v0xa0de90_0 .net "AandB", 0 0, L_0xa6e5e0; 1 drivers +v0xa0df10_0 .net "AnandB", 0 0, L_0xa6e4a0; 1 drivers +v0xa0dfc0_0 .net "AndNandOut", 0 0, L_0xa6ea30; 1 drivers +v0xa0e0a0_0 .net "B", 0 0, L_0xa6ef50; 1 drivers +v0xa0e120_0 .alias "Command", 2 0, v0xa373b0_0; +L_0xa6ec00 .part v0xa388d0_0, 0, 1; +S_0xa0d830 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0xa0d740; + .timescale -9 -12; +L_0xa6e710/d .functor NOT 1, L_0xa6ec00, C4<0>, C4<0>, C4<0>; +L_0xa6e710 .delay (10000,10000,10000) L_0xa6e710/d; +L_0xa6e7d0/d .functor AND 1, L_0xa6e5e0, L_0xa6e710, C4<1>, C4<1>; +L_0xa6e7d0 .delay (20000,20000,20000) L_0xa6e7d0/d; +L_0xa6e8e0/d .functor AND 1, L_0xa6e4a0, L_0xa6ec00, C4<1>, C4<1>; +L_0xa6e8e0 .delay (20000,20000,20000) L_0xa6e8e0/d; +L_0xa6ea30/d .functor OR 1, L_0xa6e7d0, L_0xa6e8e0, C4<0>, C4<0>; +L_0xa6ea30 .delay (20000,20000,20000) L_0xa6ea30/d; +v0xa0d920_0 .net "S", 0 0, L_0xa6ec00; 1 drivers +v0xa0d9c0_0 .alias "in0", 0 0, v0xa0de90_0; +v0xa0da60_0 .alias "in1", 0 0, v0xa0df10_0; +v0xa0db00_0 .net "nS", 0 0, L_0xa6e710; 1 drivers +v0xa0dbb0_0 .net "out0", 0 0, L_0xa6e7d0; 1 drivers +v0xa0dc50_0 .net "out1", 0 0, L_0xa6e8e0; 1 drivers +v0xa0dd30_0 .alias "outfinal", 0 0, v0xa0dfc0_0; +S_0xa08220 .scope module, "trial2" "OrNorXor32" 3 396, 3 177, S_0x9cd4a0; + .timescale -9 -12; +P_0xa07378 .param/l "size" 3 184, +C4<0100>; +v0xa0d1b0_0 .alias "A", 3 0, v0xa37070_0; +v0xa0d230_0 .alias "B", 3 0, v0xa37220_0; +v0xa0d2b0_0 .alias "Command", 2 0, v0xa373b0_0; +v0xa0d3c0_0 .alias "OrNorXorOut", 3 0, v0xa389d0_0; +L_0xa70bc0 .part/pv L_0xa70950, 1, 1, 4; +L_0xa70c60 .part v0xa38650_0, 1, 1; +L_0xa70d00 .part v0xa38850_0, 1, 1; +L_0xa71ec0 .part/pv L_0xa71c50, 2, 1, 4; +L_0xa71f60 .part v0xa38650_0, 2, 1; +L_0xa72000 .part v0xa38850_0, 2, 1; +L_0xa731c0 .part/pv L_0xa72f50, 3, 1, 4; +L_0xa73260 .part v0xa38650_0, 3, 1; +L_0xa73300 .part v0xa38850_0, 3, 1; +L_0xa744b0 .part/pv L_0xa74240, 0, 1, 4; +L_0xa745b0 .part v0xa38650_0, 0, 1; +L_0xa74650 .part v0xa38850_0, 0, 1; +S_0xa0bfa0 .scope module, "attempt2" "OrNorXor" 3 192, 3 64, S_0xa08220; + .timescale -9 -12; +L_0xa733a0/d .functor NOR 1, L_0xa745b0, L_0xa74650, C4<0>, C4<0>; +L_0xa733a0 .delay (10000,10000,10000) L_0xa733a0/d; +L_0xa734a0/d .functor NOT 1, L_0xa733a0, C4<0>, C4<0>, C4<0>; +L_0xa734a0 .delay (10000,10000,10000) L_0xa734a0/d; +L_0xa735d0/d .functor NAND 1, L_0xa745b0, L_0xa74650, C4<1>, C4<1>; +L_0xa735d0 .delay (10000,10000,10000) L_0xa735d0/d; +L_0xa73730/d .functor NAND 1, L_0xa735d0, L_0xa734a0, C4<1>, C4<1>; +L_0xa73730 .delay (10000,10000,10000) L_0xa73730/d; +L_0xa73840/d .functor NOT 1, L_0xa73730, C4<0>, C4<0>, C4<0>; +L_0xa73840 .delay (10000,10000,10000) L_0xa73840/d; +v0xa0caf0_0 .net "A", 0 0, L_0xa745b0; 1 drivers +v0xa0cb90_0 .net "AnandB", 0 0, L_0xa735d0; 1 drivers +v0xa0cc30_0 .net "AnorB", 0 0, L_0xa733a0; 1 drivers +v0xa0ccb0_0 .net "AorB", 0 0, L_0xa734a0; 1 drivers +v0xa0cd90_0 .net "AxorB", 0 0, L_0xa73840; 1 drivers +v0xa0ce40_0 .net "B", 0 0, L_0xa74650; 1 drivers +v0xa0cf00_0 .alias "Command", 2 0, v0xa373b0_0; +v0xa0cf80_0 .net "OrNorXorOut", 0 0, L_0xa74240; 1 drivers +v0xa0d000_0 .net "XorNor", 0 0, L_0xa73cc0; 1 drivers +v0xa0d0d0_0 .net "nXor", 0 0, L_0xa73730; 1 drivers +L_0xa73e40 .part v0xa388d0_0, 2, 1; +L_0xa74410 .part v0xa388d0_0, 0, 1; +S_0xa0c580 .scope module, "mux0" "TwoInMux" 3 83, 3 8, S_0xa0bfa0; + .timescale -9 -12; +L_0xa739a0/d .functor NOT 1, L_0xa73e40, C4<0>, C4<0>, C4<0>; +L_0xa739a0 .delay (10000,10000,10000) L_0xa739a0/d; +L_0xa73a60/d .functor AND 1, L_0xa73840, L_0xa739a0, C4<1>, C4<1>; +L_0xa73a60 .delay (20000,20000,20000) L_0xa73a60/d; +L_0xa73b70/d .functor AND 1, L_0xa733a0, L_0xa73e40, C4<1>, C4<1>; +L_0xa73b70 .delay (20000,20000,20000) L_0xa73b70/d; +L_0xa73cc0/d .functor OR 1, L_0xa73a60, L_0xa73b70, C4<0>, C4<0>; +L_0xa73cc0 .delay (20000,20000,20000) L_0xa73cc0/d; +v0xa0c670_0 .net "S", 0 0, L_0xa73e40; 1 drivers +v0xa0c730_0 .alias "in0", 0 0, v0xa0cd90_0; +v0xa0c7d0_0 .alias "in1", 0 0, v0xa0cc30_0; +v0xa0c870_0 .net "nS", 0 0, L_0xa739a0; 1 drivers +v0xa0c8f0_0 .net "out0", 0 0, L_0xa73a60; 1 drivers +v0xa0c990_0 .net "out1", 0 0, L_0xa73b70; 1 drivers +v0xa0ca70_0 .alias "outfinal", 0 0, v0xa0d000_0; +S_0xa0c090 .scope module, "mux1" "TwoInMux" 3 84, 3 8, S_0xa0bfa0; + .timescale -9 -12; +L_0xa73ee0/d .functor NOT 1, L_0xa74410, C4<0>, C4<0>, C4<0>; +L_0xa73ee0 .delay (10000,10000,10000) L_0xa73ee0/d; +L_0xa73fa0/d .functor AND 1, L_0xa73cc0, L_0xa73ee0, C4<1>, C4<1>; +L_0xa73fa0 .delay (20000,20000,20000) L_0xa73fa0/d; +L_0xa740f0/d .functor AND 1, L_0xa734a0, L_0xa74410, C4<1>, C4<1>; +L_0xa740f0 .delay (20000,20000,20000) L_0xa740f0/d; +L_0xa74240/d .functor OR 1, L_0xa73fa0, L_0xa740f0, C4<0>, C4<0>; +L_0xa74240 .delay (20000,20000,20000) L_0xa74240/d; +v0xa0c180_0 .net "S", 0 0, L_0xa74410; 1 drivers +v0xa0c200_0 .alias "in0", 0 0, v0xa0d000_0; +v0xa0c280_0 .alias "in1", 0 0, v0xa0ccb0_0; +v0xa0c320_0 .net "nS", 0 0, L_0xa73ee0; 1 drivers +v0xa0c3a0_0 .net "out0", 0 0, L_0xa73fa0; 1 drivers +v0xa0c440_0 .net "out1", 0 0, L_0xa740f0; 1 drivers +v0xa0c4e0_0 .alias "outfinal", 0 0, v0xa0cf80_0; +S_0xa0aba0 .scope generate, "orbits[1]" "orbits[1]" 3 196, 3 196, S_0xa08220; + .timescale -9 -12; +P_0xa0a888 .param/l "i" 3 196, +C4<01>; +S_0xa0acd0 .scope module, "attempt" "OrNorXor" 3 198, 3 64, S_0xa0aba0; + .timescale -9 -12; +L_0xa6f8a0/d .functor NOR 1, L_0xa70c60, L_0xa70d00, C4<0>, C4<0>; +L_0xa6f8a0 .delay (10000,10000,10000) L_0xa6f8a0/d; +L_0xa6fbb0/d .functor NOT 1, L_0xa6f8a0, C4<0>, C4<0>, C4<0>; +L_0xa6fbb0 .delay (10000,10000,10000) L_0xa6fbb0/d; +L_0xa6fce0/d .functor NAND 1, L_0xa70c60, L_0xa70d00, C4<1>, C4<1>; +L_0xa6fce0 .delay (10000,10000,10000) L_0xa6fce0/d; +L_0xa6fe40/d .functor NAND 1, L_0xa6fce0, L_0xa6fbb0, C4<1>, C4<1>; +L_0xa6fe40 .delay (10000,10000,10000) L_0xa6fe40/d; +L_0xa6ff50/d .functor NOT 1, L_0xa6fe40, C4<0>, C4<0>, C4<0>; +L_0xa6ff50 .delay (10000,10000,10000) L_0xa6ff50/d; +v0xa0b860_0 .net "A", 0 0, L_0xa70c60; 1 drivers +v0xa0b900_0 .net "AnandB", 0 0, L_0xa6fce0; 1 drivers +v0xa0b9a0_0 .net "AnorB", 0 0, L_0xa6f8a0; 1 drivers +v0xa0ba50_0 .net "AorB", 0 0, L_0xa6fbb0; 1 drivers +v0xa0bb30_0 .net "AxorB", 0 0, L_0xa6ff50; 1 drivers +v0xa0bbe0_0 .net "B", 0 0, L_0xa70d00; 1 drivers +v0xa0bca0_0 .alias "Command", 2 0, v0xa373b0_0; +v0xa0bd20_0 .net "OrNorXorOut", 0 0, L_0xa70950; 1 drivers +v0xa0bdf0_0 .net "XorNor", 0 0, L_0xa703d0; 1 drivers +v0xa0bec0_0 .net "nXor", 0 0, L_0xa6fe40; 1 drivers +L_0xa70550 .part v0xa388d0_0, 2, 1; +L_0xa70b20 .part v0xa388d0_0, 0, 1; +S_0xa0b2f0 .scope module, "mux0" "TwoInMux" 3 83, 3 8, S_0xa0acd0; + .timescale -9 -12; +L_0xa700b0/d .functor NOT 1, L_0xa70550, C4<0>, C4<0>, C4<0>; +L_0xa700b0 .delay (10000,10000,10000) L_0xa700b0/d; +L_0xa70170/d .functor AND 1, L_0xa6ff50, L_0xa700b0, C4<1>, C4<1>; +L_0xa70170 .delay (20000,20000,20000) L_0xa70170/d; +L_0xa70280/d .functor AND 1, L_0xa6f8a0, L_0xa70550, C4<1>, C4<1>; +L_0xa70280 .delay (20000,20000,20000) L_0xa70280/d; +L_0xa703d0/d .functor OR 1, L_0xa70170, L_0xa70280, C4<0>, C4<0>; +L_0xa703d0 .delay (20000,20000,20000) L_0xa703d0/d; +v0xa0b3e0_0 .net "S", 0 0, L_0xa70550; 1 drivers +v0xa0b4a0_0 .alias "in0", 0 0, v0xa0bb30_0; +v0xa0b540_0 .alias "in1", 0 0, v0xa0b9a0_0; +v0xa0b5e0_0 .net "nS", 0 0, L_0xa700b0; 1 drivers +v0xa0b660_0 .net "out0", 0 0, L_0xa70170; 1 drivers +v0xa0b700_0 .net "out1", 0 0, L_0xa70280; 1 drivers +v0xa0b7e0_0 .alias "outfinal", 0 0, v0xa0bdf0_0; +S_0xa0adc0 .scope module, "mux1" "TwoInMux" 3 84, 3 8, S_0xa0acd0; + .timescale -9 -12; +L_0xa705f0/d .functor NOT 1, L_0xa70b20, C4<0>, C4<0>, C4<0>; +L_0xa705f0 .delay (10000,10000,10000) L_0xa705f0/d; +L_0xa706b0/d .functor AND 1, L_0xa703d0, L_0xa705f0, C4<1>, C4<1>; +L_0xa706b0 .delay (20000,20000,20000) L_0xa706b0/d; +L_0xa70800/d .functor AND 1, L_0xa6fbb0, L_0xa70b20, C4<1>, C4<1>; +L_0xa70800 .delay (20000,20000,20000) L_0xa70800/d; +L_0xa70950/d .functor OR 1, L_0xa706b0, L_0xa70800, C4<0>, C4<0>; +L_0xa70950 .delay (20000,20000,20000) L_0xa70950/d; +v0xa0aeb0_0 .net "S", 0 0, L_0xa70b20; 1 drivers +v0xa0af30_0 .alias "in0", 0 0, v0xa0bdf0_0; +v0xa0afb0_0 .alias "in1", 0 0, v0xa0ba50_0; +v0xa0b050_0 .net "nS", 0 0, L_0xa705f0; 1 drivers +v0xa0b0d0_0 .net "out0", 0 0, L_0xa706b0; 1 drivers +v0xa0b170_0 .net "out1", 0 0, L_0xa70800; 1 drivers +v0xa0b250_0 .alias "outfinal", 0 0, v0xa0bd20_0; +S_0xa09780 .scope generate, "orbits[2]" "orbits[2]" 3 196, 3 196, S_0xa08220; + .timescale -9 -12; +P_0xa094f8 .param/l "i" 3 196, +C4<010>; +S_0xa098b0 .scope module, "attempt" "OrNorXor" 3 198, 3 64, S_0xa09780; + .timescale -9 -12; +L_0xa70da0/d .functor NOR 1, L_0xa71f60, L_0xa72000, C4<0>, C4<0>; +L_0xa70da0 .delay (10000,10000,10000) L_0xa70da0/d; +L_0xa70eb0/d .functor NOT 1, L_0xa70da0, C4<0>, C4<0>, C4<0>; +L_0xa70eb0 .delay (10000,10000,10000) L_0xa70eb0/d; +L_0xa70fe0/d .functor NAND 1, L_0xa71f60, L_0xa72000, C4<1>, C4<1>; +L_0xa70fe0 .delay (10000,10000,10000) L_0xa70fe0/d; +L_0xa71140/d .functor NAND 1, L_0xa70fe0, L_0xa70eb0, C4<1>, C4<1>; +L_0xa71140 .delay (10000,10000,10000) L_0xa71140/d; +L_0xa71250/d .functor NOT 1, L_0xa71140, C4<0>, C4<0>, C4<0>; +L_0xa71250 .delay (10000,10000,10000) L_0xa71250/d; +v0xa0a480_0 .net "A", 0 0, L_0xa71f60; 1 drivers +v0xa0a520_0 .net "AnandB", 0 0, L_0xa70fe0; 1 drivers +v0xa0a5c0_0 .net "AnorB", 0 0, L_0xa70da0; 1 drivers +v0xa0a670_0 .net "AorB", 0 0, L_0xa70eb0; 1 drivers +v0xa0a750_0 .net "AxorB", 0 0, L_0xa71250; 1 drivers +v0xa0a800_0 .net "B", 0 0, L_0xa72000; 1 drivers +v0xa0a8c0_0 .alias "Command", 2 0, v0xa373b0_0; +v0xa0a940_0 .net "OrNorXorOut", 0 0, L_0xa71c50; 1 drivers +v0xa0a9f0_0 .net "XorNor", 0 0, L_0xa716d0; 1 drivers +v0xa0aac0_0 .net "nXor", 0 0, L_0xa71140; 1 drivers +L_0xa71850 .part v0xa388d0_0, 2, 1; +L_0xa71e20 .part v0xa388d0_0, 0, 1; +S_0xa09f10 .scope module, "mux0" "TwoInMux" 3 83, 3 8, S_0xa098b0; + .timescale -9 -12; +L_0xa713b0/d .functor NOT 1, L_0xa71850, C4<0>, C4<0>, C4<0>; +L_0xa713b0 .delay (10000,10000,10000) L_0xa713b0/d; +L_0xa71470/d .functor AND 1, L_0xa71250, L_0xa713b0, C4<1>, C4<1>; +L_0xa71470 .delay (20000,20000,20000) L_0xa71470/d; +L_0xa71580/d .functor AND 1, L_0xa70da0, L_0xa71850, C4<1>, C4<1>; +L_0xa71580 .delay (20000,20000,20000) L_0xa71580/d; +L_0xa716d0/d .functor OR 1, L_0xa71470, L_0xa71580, C4<0>, C4<0>; +L_0xa716d0 .delay (20000,20000,20000) L_0xa716d0/d; +v0xa0a000_0 .net "S", 0 0, L_0xa71850; 1 drivers +v0xa0a0c0_0 .alias "in0", 0 0, v0xa0a750_0; +v0xa0a160_0 .alias "in1", 0 0, v0xa0a5c0_0; +v0xa0a200_0 .net "nS", 0 0, L_0xa713b0; 1 drivers +v0xa0a280_0 .net "out0", 0 0, L_0xa71470; 1 drivers +v0xa0a320_0 .net "out1", 0 0, L_0xa71580; 1 drivers +v0xa0a400_0 .alias "outfinal", 0 0, v0xa0a9f0_0; +S_0xa099a0 .scope module, "mux1" "TwoInMux" 3 84, 3 8, S_0xa098b0; + .timescale -9 -12; +L_0xa718f0/d .functor NOT 1, L_0xa71e20, C4<0>, C4<0>, C4<0>; +L_0xa718f0 .delay (10000,10000,10000) L_0xa718f0/d; +L_0xa719b0/d .functor AND 1, L_0xa716d0, L_0xa718f0, C4<1>, C4<1>; +L_0xa719b0 .delay (20000,20000,20000) L_0xa719b0/d; +L_0xa71b00/d .functor AND 1, L_0xa70eb0, L_0xa71e20, C4<1>, C4<1>; +L_0xa71b00 .delay (20000,20000,20000) L_0xa71b00/d; +L_0xa71c50/d .functor OR 1, L_0xa719b0, L_0xa71b00, C4<0>, C4<0>; +L_0xa71c50 .delay (20000,20000,20000) L_0xa71c50/d; +v0xa09a90_0 .net "S", 0 0, L_0xa71e20; 1 drivers +v0xa09b30_0 .alias "in0", 0 0, v0xa0a9f0_0; +v0xa09bd0_0 .alias "in1", 0 0, v0xa0a670_0; +v0xa09c70_0 .net "nS", 0 0, L_0xa718f0; 1 drivers +v0xa09cf0_0 .net "out0", 0 0, L_0xa719b0; 1 drivers +v0xa09d90_0 .net "out1", 0 0, L_0xa71b00; 1 drivers +v0xa09e70_0 .alias "outfinal", 0 0, v0xa0a940_0; +S_0xa08390 .scope generate, "orbits[3]" "orbits[3]" 3 196, 3 196, S_0xa08220; + .timescale -9 -12; +P_0xa08488 .param/l "i" 3 196, +C4<011>; +S_0xa08520 .scope module, "attempt" "OrNorXor" 3 198, 3 64, S_0xa08390; + .timescale -9 -12; +L_0xa720e0/d .functor NOR 1, L_0xa73260, L_0xa73300, C4<0>, C4<0>; +L_0xa720e0 .delay (10000,10000,10000) L_0xa720e0/d; +L_0xa721d0/d .functor NOT 1, L_0xa720e0, C4<0>, C4<0>, C4<0>; +L_0xa721d0 .delay (10000,10000,10000) L_0xa721d0/d; +L_0xa722e0/d .functor NAND 1, L_0xa73260, L_0xa73300, C4<1>, C4<1>; +L_0xa722e0 .delay (10000,10000,10000) L_0xa722e0/d; +L_0xa72440/d .functor NAND 1, L_0xa722e0, L_0xa721d0, C4<1>, C4<1>; +L_0xa72440 .delay (10000,10000,10000) L_0xa72440/d; +L_0xa72550/d .functor NOT 1, L_0xa72440, C4<0>, C4<0>, C4<0>; +L_0xa72550 .delay (10000,10000,10000) L_0xa72550/d; +v0xa090f0_0 .net "A", 0 0, L_0xa73260; 1 drivers +v0xa09190_0 .net "AnandB", 0 0, L_0xa722e0; 1 drivers +v0xa09230_0 .net "AnorB", 0 0, L_0xa720e0; 1 drivers +v0xa092e0_0 .net "AorB", 0 0, L_0xa721d0; 1 drivers +v0xa093c0_0 .net "AxorB", 0 0, L_0xa72550; 1 drivers +v0xa09470_0 .net "B", 0 0, L_0xa73300; 1 drivers +v0xa09530_0 .alias "Command", 2 0, v0xa373b0_0; +v0xa095b0_0 .net "OrNorXorOut", 0 0, L_0xa72f50; 1 drivers +v0xa09630_0 .net "XorNor", 0 0, L_0xa729d0; 1 drivers +v0xa09700_0 .net "nXor", 0 0, L_0xa72440; 1 drivers +L_0xa72b50 .part v0xa388d0_0, 2, 1; +L_0xa73120 .part v0xa388d0_0, 0, 1; +S_0xa08b80 .scope module, "mux0" "TwoInMux" 3 83, 3 8, S_0xa08520; + .timescale -9 -12; +L_0xa726b0/d .functor NOT 1, L_0xa72b50, C4<0>, C4<0>, C4<0>; +L_0xa726b0 .delay (10000,10000,10000) L_0xa726b0/d; +L_0xa72770/d .functor AND 1, L_0xa72550, L_0xa726b0, C4<1>, C4<1>; +L_0xa72770 .delay (20000,20000,20000) L_0xa72770/d; +L_0xa72880/d .functor AND 1, L_0xa720e0, L_0xa72b50, C4<1>, C4<1>; +L_0xa72880 .delay (20000,20000,20000) L_0xa72880/d; +L_0xa729d0/d .functor OR 1, L_0xa72770, L_0xa72880, C4<0>, C4<0>; +L_0xa729d0 .delay (20000,20000,20000) L_0xa729d0/d; +v0xa08c70_0 .net "S", 0 0, L_0xa72b50; 1 drivers +v0xa08d30_0 .alias "in0", 0 0, v0xa093c0_0; +v0xa08dd0_0 .alias "in1", 0 0, v0xa09230_0; +v0xa08e70_0 .net "nS", 0 0, L_0xa726b0; 1 drivers +v0xa08ef0_0 .net "out0", 0 0, L_0xa72770; 1 drivers +v0xa08f90_0 .net "out1", 0 0, L_0xa72880; 1 drivers +v0xa09070_0 .alias "outfinal", 0 0, v0xa09630_0; +S_0xa08610 .scope module, "mux1" "TwoInMux" 3 84, 3 8, S_0xa08520; + .timescale -9 -12; +L_0xa72bf0/d .functor NOT 1, L_0xa73120, C4<0>, C4<0>, C4<0>; +L_0xa72bf0 .delay (10000,10000,10000) L_0xa72bf0/d; +L_0xa72cb0/d .functor AND 1, L_0xa729d0, L_0xa72bf0, C4<1>, C4<1>; +L_0xa72cb0 .delay (20000,20000,20000) L_0xa72cb0/d; +L_0xa72e00/d .functor AND 1, L_0xa721d0, L_0xa73120, C4<1>, C4<1>; +L_0xa72e00 .delay (20000,20000,20000) L_0xa72e00/d; +L_0xa72f50/d .functor OR 1, L_0xa72cb0, L_0xa72e00, C4<0>, C4<0>; +L_0xa72f50 .delay (20000,20000,20000) L_0xa72f50/d; +v0xa08700_0 .net "S", 0 0, L_0xa73120; 1 drivers +v0xa087a0_0 .alias "in0", 0 0, v0xa09630_0; +v0xa08840_0 .alias "in1", 0 0, v0xa092e0_0; +v0xa088e0_0 .net "nS", 0 0, L_0xa72bf0; 1 drivers +v0xa08960_0 .net "out0", 0 0, L_0xa72cb0; 1 drivers +v0xa08a00_0 .net "out1", 0 0, L_0xa72e00; 1 drivers +v0xa08ae0_0 .alias "outfinal", 0 0, v0xa095b0_0; +S_0xa078a0 .scope module, "ZeroMux0case" "FourInMux" 3 398, 3 24, S_0x9cd4a0; + .timescale -9 -12; +L_0xa74550/d .functor NOT 1, L_0xa5a4e0, C4<0>, C4<0>, C4<0>; +L_0xa74550 .delay (10000,10000,10000) L_0xa74550/d; +L_0xa747a0/d .functor NOT 1, L_0xa5a610, C4<0>, C4<0>, C4<0>; +L_0xa747a0 .delay (10000,10000,10000) L_0xa747a0/d; +L_0xa74860/d .functor NAND 1, L_0xa74550, L_0xa747a0, L_0xa74e90, C4<1>; +L_0xa74860 .delay (10000,10000,10000) L_0xa74860/d; +L_0xa74950/d .functor NAND 1, L_0xa5a4e0, L_0xa747a0, L_0xa74f30, C4<1>; +L_0xa74950 .delay (10000,10000,10000) L_0xa74950/d; +L_0xa74a40/d .functor NAND 1, L_0xa74550, L_0xa5a610, L_0xa74fd0, C4<1>; +L_0xa74a40 .delay (10000,10000,10000) L_0xa74a40/d; +L_0xa74b30/d .functor NAND 1, L_0xa5a4e0, L_0xa5a610, L_0xa753b0, C4<1>; +L_0xa74b30 .delay (10000,10000,10000) L_0xa74b30/d; +L_0xa74c10/d .functor NAND 1, L_0xa74860, L_0xa74950, L_0xa74a40, L_0xa74b30; +L_0xa74c10 .delay (10000,10000,10000) L_0xa74c10/d; +v0xa07990_0 .net "S0", 0 0, L_0xa5a4e0; 1 drivers +v0xa07a50_0 .net "S1", 0 0, L_0xa5a610; 1 drivers +v0xa07af0_0 .net "in0", 0 0, L_0xa74e90; 1 drivers +v0xa07b90_0 .net "in1", 0 0, L_0xa74f30; 1 drivers +v0xa07c10_0 .net "in2", 0 0, L_0xa74fd0; 1 drivers +v0xa07cb0_0 .net "in3", 0 0, L_0xa753b0; 1 drivers +v0xa07d50_0 .net "nS0", 0 0, L_0xa74550; 1 drivers +v0xa07df0_0 .net "nS1", 0 0, L_0xa747a0; 1 drivers +v0xa07e90_0 .net "out", 0 0, L_0xa74c10; 1 drivers +v0xa07f30_0 .net "out0", 0 0, L_0xa74860; 1 drivers +v0xa07fd0_0 .net "out1", 0 0, L_0xa74950; 1 drivers +v0xa08070_0 .net "out2", 0 0, L_0xa74a40; 1 drivers +v0xa08180_0 .net "out3", 0 0, L_0xa74b30; 1 drivers +S_0xa06ee0 .scope module, "OneMux0case" "FourInMux" 3 399, 3 24, S_0x9cd4a0; + .timescale -9 -12; +L_0xa75130/d .functor NOT 1, L_0xa75cc0, C4<0>, C4<0>, C4<0>; +L_0xa75130 .delay (10000,10000,10000) L_0xa75130/d; +L_0xa75220/d .functor NOT 1, L_0xa754a0, C4<0>, C4<0>, C4<0>; +L_0xa75220 .delay (10000,10000,10000) L_0xa75220/d; +L_0xa752c0/d .functor NAND 1, L_0xa75130, L_0xa75220, L_0xa755d0, C4<1>; +L_0xa752c0 .delay (10000,10000,10000) L_0xa752c0/d; +L_0xa75780/d .functor NAND 1, L_0xa75cc0, L_0xa75220, L_0xa76050, C4<1>; +L_0xa75780 .delay (10000,10000,10000) L_0xa75780/d; +L_0xa75870/d .functor NAND 1, L_0xa75130, L_0xa754a0, L_0xa760f0, C4<1>; +L_0xa75870 .delay (10000,10000,10000) L_0xa75870/d; +L_0xa75960/d .functor NAND 1, L_0xa75cc0, L_0xa754a0, L_0xa75df0, C4<1>; +L_0xa75960 .delay (10000,10000,10000) L_0xa75960/d; +L_0xa75a40/d .functor NAND 1, L_0xa752c0, L_0xa75780, L_0xa75870, L_0xa75960; +L_0xa75a40 .delay (10000,10000,10000) L_0xa75a40/d; +v0xa06fd0_0 .net "S0", 0 0, L_0xa75cc0; 1 drivers +v0xa07090_0 .net "S1", 0 0, L_0xa754a0; 1 drivers +v0xa07130_0 .net "in0", 0 0, L_0xa755d0; 1 drivers +v0xa071d0_0 .net "in1", 0 0, L_0xa76050; 1 drivers +v0xa07250_0 .net "in2", 0 0, L_0xa760f0; 1 drivers +v0xa072f0_0 .net "in3", 0 0, L_0xa75df0; 1 drivers +v0xa073d0_0 .net "nS0", 0 0, L_0xa75130; 1 drivers +v0xa07470_0 .net "nS1", 0 0, L_0xa75220; 1 drivers +v0xa07510_0 .net "out", 0 0, L_0xa75a40; 1 drivers +v0xa075b0_0 .net "out0", 0 0, L_0xa752c0; 1 drivers +v0xa07650_0 .net "out1", 0 0, L_0xa75780; 1 drivers +v0xa076f0_0 .net "out2", 0 0, L_0xa75870; 1 drivers +v0xa07800_0 .net "out3", 0 0, L_0xa75960; 1 drivers +S_0xa06990 .scope module, "TwoMux0case" "TwoInMux" 3 400, 3 8, S_0x9cd4a0; + .timescale -9 -12; +L_0xa75ee0/d .functor NOT 1, L_0xa76190, C4<0>, C4<0>, C4<0>; +L_0xa75ee0 .delay (10000,10000,10000) L_0xa75ee0/d; +L_0xa75fd0/d .functor AND 1, L_0xa76230, L_0xa75ee0, C4<1>, C4<1>; +L_0xa75fd0 .delay (20000,20000,20000) L_0xa75fd0/d; +L_0xa76490/d .functor AND 1, L_0xa76320, L_0xa76190, C4<1>, C4<1>; +L_0xa76490 .delay (20000,20000,20000) L_0xa76490/d; +L_0xa76580/d .functor OR 1, L_0xa75fd0, L_0xa76490, C4<0>, C4<0>; +L_0xa76580 .delay (20000,20000,20000) L_0xa76580/d; +v0xa06a80_0 .net "S", 0 0, L_0xa76190; 1 drivers +v0xa06b40_0 .net "in0", 0 0, L_0xa76230; 1 drivers +v0xa06be0_0 .net "in1", 0 0, L_0xa76320; 1 drivers +v0xa06c80_0 .net "nS", 0 0, L_0xa75ee0; 1 drivers +v0xa06d00_0 .net "out0", 0 0, L_0xa75fd0; 1 drivers +v0xa06da0_0 .net "out1", 0 0, L_0xa76490; 1 drivers +v0xa06e40_0 .net "outfinal", 0 0, L_0xa76580; 1 drivers +S_0xa04e10 .scope generate, "muxbits[1]" "muxbits[1]" 3 405, 3 405, S_0x9cd4a0; + .timescale -9 -12; +P_0xa03e08 .param/l "i" 3 405, +C4<01>; +L_0xa54fc0/d .functor OR 1, L_0xa550c0, L_0xa54e80, C4<0>, C4<0>; +L_0xa54fc0 .delay (20000,20000,20000) L_0xa54fc0/d; +v0xa06830_0 .net *"_s15", 0 0, L_0xa550c0; 1 drivers +v0xa068f0_0 .net *"_s16", 0 0, L_0xa54e80; 1 drivers +S_0xa05eb0 .scope module, "ZeroMux" "FourInMux" 3 407, 3 24, S_0xa04e10; + .timescale -9 -12; +L_0xa527d0/d .functor NOT 1, L_0xa53110, C4<0>, C4<0>, C4<0>; +L_0xa527d0 .delay (10000,10000,10000) L_0xa527d0/d; +L_0xa52a20/d .functor NOT 1, L_0xa53240, C4<0>, C4<0>, C4<0>; +L_0xa52a20 .delay (10000,10000,10000) L_0xa52a20/d; +L_0xa52ae0/d .functor NAND 1, L_0xa527d0, L_0xa52a20, L_0xa53370, C4<1>; +L_0xa52ae0 .delay (10000,10000,10000) L_0xa52ae0/d; +L_0xa52bd0/d .functor NAND 1, L_0xa53110, L_0xa52a20, L_0xa53410, C4<1>; +L_0xa52bd0 .delay (10000,10000,10000) L_0xa52bd0/d; +L_0xa52cc0/d .functor NAND 1, L_0xa527d0, L_0xa53240, L_0xa534b0, C4<1>; +L_0xa52cc0 .delay (10000,10000,10000) L_0xa52cc0/d; +L_0xa52db0/d .functor NAND 1, L_0xa53110, L_0xa53240, L_0xa536b0, C4<1>; +L_0xa52db0 .delay (10000,10000,10000) L_0xa52db0/d; +L_0xa52e90/d .functor NAND 1, L_0xa52ae0, L_0xa52bd0, L_0xa52cc0, L_0xa52db0; +L_0xa52e90 .delay (10000,10000,10000) L_0xa52e90/d; +v0xa05fa0_0 .net "S0", 0 0, L_0xa53110; 1 drivers +v0xa06060_0 .net "S1", 0 0, L_0xa53240; 1 drivers +v0xa06100_0 .net "in0", 0 0, L_0xa53370; 1 drivers +v0xa061a0_0 .net "in1", 0 0, L_0xa53410; 1 drivers +v0xa06220_0 .net "in2", 0 0, L_0xa534b0; 1 drivers +v0xa062c0_0 .net "in3", 0 0, L_0xa536b0; 1 drivers +v0xa06360_0 .net "nS0", 0 0, L_0xa527d0; 1 drivers +v0xa06400_0 .net "nS1", 0 0, L_0xa52a20; 1 drivers +v0xa064a0_0 .net "out", 0 0, L_0xa52e90; 1 drivers +v0xa06540_0 .net "out0", 0 0, L_0xa52ae0; 1 drivers +v0xa065e0_0 .net "out1", 0 0, L_0xa52bd0; 1 drivers +v0xa06680_0 .net "out2", 0 0, L_0xa52cc0; 1 drivers +v0xa06790_0 .net "out3", 0 0, L_0xa52db0; 1 drivers +S_0xa054f0 .scope module, "OneMux" "FourInMux" 3 408, 3 24, S_0xa04e10; + .timescale -9 -12; +L_0xa430c0/d .functor NOT 1, L_0xa54060, C4<0>, C4<0>, C4<0>; +L_0xa430c0 .delay (10000,10000,10000) L_0xa430c0/d; +L_0xa538f0/d .functor NOT 1, L_0xa54190, C4<0>, C4<0>, C4<0>; +L_0xa538f0 .delay (10000,10000,10000) L_0xa538f0/d; +L_0xa53990/d .functor NAND 1, L_0xa430c0, L_0xa538f0, L_0xa54320, C4<1>; +L_0xa53990 .delay (10000,10000,10000) L_0xa53990/d; +L_0xa53ad0/d .functor NAND 1, L_0xa54060, L_0xa538f0, L_0xa544d0, C4<1>; +L_0xa53ad0 .delay (10000,10000,10000) L_0xa53ad0/d; +L_0xa53bc0/d .functor NAND 1, L_0xa430c0, L_0xa54190, L_0xa54570, C4<1>; +L_0xa53bc0 .delay (10000,10000,10000) L_0xa53bc0/d; +L_0xa53cb0/d .functor NAND 1, L_0xa54060, L_0xa54190, L_0xa54610, C4<1>; +L_0xa53cb0 .delay (10000,10000,10000) L_0xa53cb0/d; +L_0xa53d90/d .functor NAND 1, L_0xa53990, L_0xa53ad0, L_0xa53bc0, L_0xa53cb0; +L_0xa53d90 .delay (10000,10000,10000) L_0xa53d90/d; +v0xa055e0_0 .net "S0", 0 0, L_0xa54060; 1 drivers +v0xa056a0_0 .net "S1", 0 0, L_0xa54190; 1 drivers +v0xa05740_0 .net "in0", 0 0, L_0xa54320; 1 drivers +v0xa057e0_0 .net "in1", 0 0, L_0xa544d0; 1 drivers +v0xa05860_0 .net "in2", 0 0, L_0xa54570; 1 drivers +v0xa05900_0 .net "in3", 0 0, L_0xa54610; 1 drivers +v0xa059e0_0 .net "nS0", 0 0, L_0xa430c0; 1 drivers +v0xa05a80_0 .net "nS1", 0 0, L_0xa538f0; 1 drivers +v0xa05b20_0 .net "out", 0 0, L_0xa53d90; 1 drivers +v0xa05bc0_0 .net "out0", 0 0, L_0xa53990; 1 drivers +v0xa05c60_0 .net "out1", 0 0, L_0xa53ad0; 1 drivers +v0xa05d00_0 .net "out2", 0 0, L_0xa53bc0; 1 drivers +v0xa05e10_0 .net "out3", 0 0, L_0xa53cb0; 1 drivers +S_0xa04f80 .scope module, "TwoMux" "TwoInMux" 3 409, 3 8, S_0xa04e10; + .timescale -9 -12; +L_0xa542c0/d .functor NOT 1, L_0xa54b60, C4<0>, C4<0>, C4<0>; +L_0xa542c0 .delay (10000,10000,10000) L_0xa542c0/d; +L_0xa54750/d .functor AND 1, L_0xa54c00, L_0xa542c0, C4<1>, C4<1>; +L_0xa54750 .delay (20000,20000,20000) L_0xa54750/d; +L_0xa54840/d .functor AND 1, L_0xa54d40, L_0xa54b60, C4<1>, C4<1>; +L_0xa54840 .delay (20000,20000,20000) L_0xa54840/d; +L_0xa54930/d .functor OR 1, L_0xa54750, L_0xa54840, C4<0>, C4<0>; +L_0xa54930 .delay (20000,20000,20000) L_0xa54930/d; +v0xa05070_0 .net "S", 0 0, L_0xa54b60; 1 drivers +v0xa05110_0 .net "in0", 0 0, L_0xa54c00; 1 drivers +v0xa051b0_0 .net "in1", 0 0, L_0xa54d40; 1 drivers +v0xa05250_0 .net "nS", 0 0, L_0xa542c0; 1 drivers +v0xa052d0_0 .net "out0", 0 0, L_0xa54750; 1 drivers +v0xa05370_0 .net "out1", 0 0, L_0xa54840; 1 drivers +v0xa05450_0 .net "outfinal", 0 0, L_0xa54930; 1 drivers +S_0xa03290 .scope generate, "muxbits[2]" "muxbits[2]" 3 405, 3 405, S_0x9cd4a0; + .timescale -9 -12; +P_0xa021d8 .param/l "i" 3 405, +C4<010>; +L_0xa56f90/d .functor OR 1, L_0xa57790, L_0xa57b10, C4<0>, C4<0>; +L_0xa56f90 .delay (20000,20000,20000) L_0xa56f90/d; +v0xa04cb0_0 .net *"_s15", 0 0, L_0xa57790; 1 drivers +v0xa04d70_0 .net *"_s16", 0 0, L_0xa57b10; 1 drivers +S_0xa04330 .scope module, "ZeroMux" "FourInMux" 3 407, 3 24, S_0xa03290; + .timescale -9 -12; +L_0xa55260/d .functor NOT 1, L_0xa55160, C4<0>, C4<0>, C4<0>; +L_0xa55260 .delay (10000,10000,10000) L_0xa55260/d; +L_0xa55310/d .functor NOT 1, L_0xa55c40, C4<0>, C4<0>, C4<0>; +L_0xa55310 .delay (10000,10000,10000) L_0xa55310/d; +L_0xa553b0/d .functor NAND 1, L_0xa55260, L_0xa55310, L_0xa55af0, C4<1>; +L_0xa553b0 .delay (10000,10000,10000) L_0xa553b0/d; +L_0xa554f0/d .functor NAND 1, L_0xa55160, L_0xa55310, L_0xa55e40, C4<1>; +L_0xa554f0 .delay (10000,10000,10000) L_0xa554f0/d; +L_0xa555e0/d .functor NAND 1, L_0xa55260, L_0xa55c40, L_0xa55d70, C4<1>; +L_0xa555e0 .delay (10000,10000,10000) L_0xa555e0/d; +L_0xa556d0/d .functor NAND 1, L_0xa55160, L_0xa55c40, L_0xa56010, C4<1>; +L_0xa556d0 .delay (10000,10000,10000) L_0xa556d0/d; +L_0xa55840/d .functor NAND 1, L_0xa553b0, L_0xa554f0, L_0xa555e0, L_0xa556d0; +L_0xa55840 .delay (10000,10000,10000) L_0xa55840/d; +v0xa04420_0 .net "S0", 0 0, L_0xa55160; 1 drivers +v0xa044e0_0 .net "S1", 0 0, L_0xa55c40; 1 drivers +v0xa04580_0 .net "in0", 0 0, L_0xa55af0; 1 drivers +v0xa04620_0 .net "in1", 0 0, L_0xa55e40; 1 drivers +v0xa046a0_0 .net "in2", 0 0, L_0xa55d70; 1 drivers +v0xa04740_0 .net "in3", 0 0, L_0xa56010; 1 drivers +v0xa047e0_0 .net "nS0", 0 0, L_0xa55260; 1 drivers +v0xa04880_0 .net "nS1", 0 0, L_0xa55310; 1 drivers +v0xa04920_0 .net "out", 0 0, L_0xa55840; 1 drivers +v0xa049c0_0 .net "out0", 0 0, L_0xa553b0; 1 drivers +v0xa04a60_0 .net "out1", 0 0, L_0xa554f0; 1 drivers +v0xa04b00_0 .net "out2", 0 0, L_0xa555e0; 1 drivers +v0xa04c10_0 .net "out3", 0 0, L_0xa556d0; 1 drivers +S_0xa03970 .scope module, "OneMux" "FourInMux" 3 408, 3 24, S_0xa03290; + .timescale -9 -12; +L_0xa55ee0/d .functor NOT 1, L_0xa569e0, C4<0>, C4<0>, C4<0>; +L_0xa55ee0 .delay (10000,10000,10000) L_0xa55ee0/d; +L_0xa56240/d .functor NOT 1, L_0xa56100, C4<0>, C4<0>, C4<0>; +L_0xa56240 .delay (10000,10000,10000) L_0xa56240/d; +L_0xa562a0/d .functor NAND 1, L_0xa55ee0, L_0xa56240, L_0xa56ca0, C4<1>; +L_0xa562a0 .delay (10000,10000,10000) L_0xa562a0/d; +L_0xa563e0/d .functor NAND 1, L_0xa569e0, L_0xa56240, L_0xa56b10, C4<1>; +L_0xa563e0 .delay (10000,10000,10000) L_0xa563e0/d; +L_0xa564d0/d .functor NAND 1, L_0xa55ee0, L_0xa56100, L_0xa56e50, C4<1>; +L_0xa564d0 .delay (10000,10000,10000) L_0xa564d0/d; +L_0xa565c0/d .functor NAND 1, L_0xa569e0, L_0xa56100, L_0xa56d40, C4<1>; +L_0xa565c0 .delay (10000,10000,10000) L_0xa565c0/d; +L_0xa56730/d .functor NAND 1, L_0xa562a0, L_0xa563e0, L_0xa564d0, L_0xa565c0; +L_0xa56730 .delay (10000,10000,10000) L_0xa56730/d; +v0xa03a60_0 .net "S0", 0 0, L_0xa569e0; 1 drivers +v0xa03b20_0 .net "S1", 0 0, L_0xa56100; 1 drivers +v0xa03bc0_0 .net "in0", 0 0, L_0xa56ca0; 1 drivers +v0xa03c60_0 .net "in1", 0 0, L_0xa56b10; 1 drivers +v0xa03ce0_0 .net "in2", 0 0, L_0xa56e50; 1 drivers +v0xa03d80_0 .net "in3", 0 0, L_0xa56d40; 1 drivers +v0xa03e60_0 .net "nS0", 0 0, L_0xa55ee0; 1 drivers +v0xa03f00_0 .net "nS1", 0 0, L_0xa56240; 1 drivers +v0xa03fa0_0 .net "out", 0 0, L_0xa56730; 1 drivers +v0xa04040_0 .net "out0", 0 0, L_0xa562a0; 1 drivers +v0xa040e0_0 .net "out1", 0 0, L_0xa563e0; 1 drivers +v0xa04180_0 .net "out2", 0 0, L_0xa564d0; 1 drivers +v0xa04290_0 .net "out3", 0 0, L_0xa565c0; 1 drivers +S_0xa03400 .scope module, "TwoMux" "TwoInMux" 3 409, 3 8, S_0xa03290; + .timescale -9 -12; +L_0xa56de0/d .functor NOT 1, L_0xa56ef0, C4<0>, C4<0>, C4<0>; +L_0xa56de0 .delay (10000,10000,10000) L_0xa56de0/d; +L_0xa570a0/d .functor AND 1, L_0xa57620, L_0xa56de0, C4<1>, C4<1>; +L_0xa570a0 .delay (20000,20000,20000) L_0xa570a0/d; +L_0xa57190/d .functor AND 1, L_0xa574f0, L_0xa56ef0, C4<1>, C4<1>; +L_0xa57190 .delay (20000,20000,20000) L_0xa57190/d; +L_0xa57280/d .functor OR 1, L_0xa570a0, L_0xa57190, C4<0>, C4<0>; +L_0xa57280 .delay (20000,20000,20000) L_0xa57280/d; +v0xa034f0_0 .net "S", 0 0, L_0xa56ef0; 1 drivers +v0xa03590_0 .net "in0", 0 0, L_0xa57620; 1 drivers +v0xa03630_0 .net "in1", 0 0, L_0xa574f0; 1 drivers +v0xa036d0_0 .net "nS", 0 0, L_0xa56de0; 1 drivers +v0xa03750_0 .net "out0", 0 0, L_0xa570a0; 1 drivers +v0xa037f0_0 .net "out1", 0 0, L_0xa57190; 1 drivers +v0xa038d0_0 .net "outfinal", 0 0, L_0xa57280; 1 drivers +S_0x9308d0 .scope generate, "muxbits[3]" "muxbits[3]" 3 405, 3 405, S_0x9cd4a0; + .timescale -9 -12; +P_0x89e2c8 .param/l "i" 3 405, +C4<011>; +L_0xa5a0c0/d .functor OR 1, L_0xa5a440, L_0xa5a250, C4<0>, C4<0>; +L_0xa5a0c0 .delay (20000,20000,20000) L_0xa5a0c0/d; +v0xa03130_0 .net *"_s15", 0 0, L_0xa5a440; 1 drivers +v0xa031f0_0 .net *"_s16", 0 0, L_0xa5a250; 1 drivers +S_0xa027b0 .scope module, "ZeroMux" "FourInMux" 3 407, 3 24, S_0x9308d0; + .timescale -9 -12; +L_0xa579c0/d .functor NOT 1, L_0xa584f0, C4<0>, C4<0>, C4<0>; +L_0xa579c0 .delay (10000,10000,10000) L_0xa579c0/d; +L_0xa57ab0/d .functor NOT 1, L_0xa57bb0, C4<0>, C4<0>, C4<0>; +L_0xa57ab0 .delay (10000,10000,10000) L_0xa57ab0/d; +L_0xa57d50/d .functor NAND 1, L_0xa579c0, L_0xa57ab0, L_0xa58790, C4<1>; +L_0xa57d50 .delay (10000,10000,10000) L_0xa57d50/d; +L_0xa57e90/d .functor NAND 1, L_0xa584f0, L_0xa57ab0, L_0xa58620, C4<1>; +L_0xa57e90 .delay (10000,10000,10000) L_0xa57e90/d; +L_0xa57f80/d .functor NAND 1, L_0xa579c0, L_0xa57bb0, L_0xa586c0, C4<1>; +L_0xa57f80 .delay (10000,10000,10000) L_0xa57f80/d; +L_0xa580d0/d .functor NAND 1, L_0xa584f0, L_0xa57bb0, L_0xa58830, C4<1>; +L_0xa580d0 .delay (10000,10000,10000) L_0xa580d0/d; +L_0xa58240/d .functor NAND 1, L_0xa57d50, L_0xa57e90, L_0xa57f80, L_0xa580d0; +L_0xa58240 .delay (10000,10000,10000) L_0xa58240/d; +v0xa028a0_0 .net "S0", 0 0, L_0xa584f0; 1 drivers +v0xa02960_0 .net "S1", 0 0, L_0xa57bb0; 1 drivers +v0xa02a00_0 .net "in0", 0 0, L_0xa58790; 1 drivers +v0xa02aa0_0 .net "in1", 0 0, L_0xa58620; 1 drivers +v0xa02b20_0 .net "in2", 0 0, L_0xa586c0; 1 drivers +v0xa02bc0_0 .net "in3", 0 0, L_0xa58830; 1 drivers +v0xa02c60_0 .net "nS0", 0 0, L_0xa579c0; 1 drivers +v0xa02d00_0 .net "nS1", 0 0, L_0xa57ab0; 1 drivers +v0xa02da0_0 .net "out", 0 0, L_0xa58240; 1 drivers +v0xa02e40_0 .net "out0", 0 0, L_0xa57d50; 1 drivers +v0xa02ee0_0 .net "out1", 0 0, L_0xa57e90; 1 drivers +v0xa02f80_0 .net "out2", 0 0, L_0xa57f80; 1 drivers +v0xa03090_0 .net "out3", 0 0, L_0xa580d0; 1 drivers +S_0xa01d40 .scope module, "OneMux" "FourInMux" 3 408, 3 24, S_0x9308d0; + .timescale -9 -12; +L_0xa58920/d .functor NOT 1, L_0xa58a00, C4<0>, C4<0>, C4<0>; +L_0xa58920 .delay (10000,10000,10000) L_0xa58920/d; +L_0xa58c20/d .functor NOT 1, L_0xa59540, C4<0>, C4<0>, C4<0>; +L_0xa58c20 .delay (10000,10000,10000) L_0xa58c20/d; +L_0xa58cc0/d .functor NAND 1, L_0xa58920, L_0xa58c20, L_0xa593a0, C4<1>; +L_0xa58cc0 .delay (10000,10000,10000) L_0xa58cc0/d; +L_0xa58e00/d .functor NAND 1, L_0xa58a00, L_0xa58c20, L_0xa59440, C4<1>; +L_0xa58e00 .delay (10000,10000,10000) L_0xa58e00/d; +L_0xa58ef0/d .functor NAND 1, L_0xa58920, L_0xa59540, L_0xa59830, C4<1>; +L_0xa58ef0 .delay (10000,10000,10000) L_0xa58ef0/d; +L_0xa58fe0/d .functor NAND 1, L_0xa58a00, L_0xa59540, L_0xa598d0, C4<1>; +L_0xa58fe0 .delay (10000,10000,10000) L_0xa58fe0/d; +L_0xa590f0/d .functor NAND 1, L_0xa58cc0, L_0xa58e00, L_0xa58ef0, L_0xa58fe0; +L_0xa590f0 .delay (10000,10000,10000) L_0xa590f0/d; +v0xa01e30_0 .net "S0", 0 0, L_0xa58a00; 1 drivers +v0xa01ef0_0 .net "S1", 0 0, L_0xa59540; 1 drivers +v0xa01f90_0 .net "in0", 0 0, L_0xa593a0; 1 drivers +v0xa02030_0 .net "in1", 0 0, L_0xa59440; 1 drivers +v0xa020b0_0 .net "in2", 0 0, L_0xa59830; 1 drivers +v0xa02150_0 .net "in3", 0 0, L_0xa598d0; 1 drivers +v0xa02230_0 .net "nS0", 0 0, L_0xa58920; 1 drivers +v0xa022d0_0 .net "nS1", 0 0, L_0xa58c20; 1 drivers +v0xa023c0_0 .net "out", 0 0, L_0xa590f0; 1 drivers +v0xa02460_0 .net "out0", 0 0, L_0xa58cc0; 1 drivers +v0xa02560_0 .net "out1", 0 0, L_0xa58e00; 1 drivers +v0xa02600_0 .net "out2", 0 0, L_0xa58ef0; 1 drivers +v0xa02710_0 .net "out3", 0 0, L_0xa58fe0; 1 drivers +S_0x98b6e0 .scope module, "TwoMux" "TwoInMux" 3 409, 3 8, S_0x9308d0; + .timescale -9 -12; +L_0xa535a0/d .functor NOT 1, L_0xa59f80, C4<0>, C4<0>, C4<0>; +L_0xa535a0 .delay (10000,10000,10000) L_0xa535a0/d; +L_0xa59670/d .functor AND 1, L_0xa59b80, L_0xa535a0, C4<1>, C4<1>; +L_0xa59670 .delay (20000,20000,20000) L_0xa59670/d; +L_0xa59760/d .functor AND 1, L_0xa59c70, L_0xa59f80, C4<1>, C4<1>; +L_0xa59760 .delay (20000,20000,20000) L_0xa59760/d; +L_0xa59da0/d .functor OR 1, L_0xa59670, L_0xa59760, C4<0>, C4<0>; +L_0xa59da0 .delay (20000,20000,20000) L_0xa59da0/d; +v0x90c030_0 .net "S", 0 0, L_0xa59f80; 1 drivers +v0x910ec0_0 .net "in0", 0 0, L_0xa59b80; 1 drivers +v0x910f60_0 .net "in1", 0 0, L_0xa59c70; 1 drivers +v0x911000_0 .net "nS", 0 0, L_0xa535a0; 1 drivers +v0x9110b0_0 .net "out0", 0 0, L_0xa59670; 1 drivers +v0x911150_0 .net "out1", 0 0, L_0xa59760; 1 drivers +v0x911230_0 .net "outfinal", 0 0, L_0xa59da0; 1 drivers + .scope S_0x96f1c0; T_0 ; - %vpi_call 2 154 "$dumpfile", "FullALU.vcd"; - %vpi_call 2 155 "$dumpvars"; - %vpi_call 2 157 "$display", "Test 4 Bit Adder Functionality"; - %vpi_call 2 159 "$display", " A | B |Command| Out|ExpectedOut|Cout|OF"; + %vpi_call 2 157 "$dumpfile", "FullALU.vcd"; + %vpi_call 2 158 "$dumpvars"; + %vpi_call 2 160 "$display", "Test 4 Bit Adder Functionality"; + %vpi_call 2 162 "$display", " A | B |Command| Out|ExpectedOut|Cout|OF"; %movi 8, 2, 4; - %set/v v0x245e5f0_0, 8, 4; + %set/v v0xa38650_0, 8, 4; %movi 8, 4, 4; - %set/v v0x245e7f0_0, 8, 4; - %set/v v0x245e870_0, 0, 3; + %set/v v0xa38850_0, 8, 4; + %set/v v0xa388d0_0, 0, 3; %delay 1000000, 0; - %vpi_call 2 163 "$display", "%b | %b | %b | %b | Expect 0110| %b | %b ", v0x245e5f0_0, v0x245e7f0_0, v0x245e870_0, v0x245e670_0, v0x245ebc0_0, v0x245ec40_0; + %vpi_call 2 166 "$display", "%b | %b | %b | %b | Expect 0110| %b | %b ", v0xa38650_0, v0xa38850_0, v0xa388d0_0, v0xa386d0_0, v0xa38c80_0, v0xa38d00_0; %movi 8, 1, 4; - %set/v v0x245e5f0_0, 8, 4; + %set/v v0xa38650_0, 8, 4; %movi 8, 6, 4; - %set/v v0x245e7f0_0, 8, 4; - %set/v v0x245e870_0, 0, 3; + %set/v v0xa38850_0, 8, 4; + %set/v v0xa388d0_0, 0, 3; %delay 1000000, 0; - %vpi_call 2 167 "$display", "%b | %b | %b | %b | Expect 0111| %b | %b ", v0x245e5f0_0, v0x245e7f0_0, v0x245e870_0, v0x245e670_0, v0x245ebc0_0, v0x245ec40_0; + %vpi_call 2 170 "$display", "%b | %b | %b | %b | Expect 0111| %b | %b ", v0xa38650_0, v0xa38850_0, v0xa388d0_0, v0xa386d0_0, v0xa38c80_0, v0xa38d00_0; %movi 8, 5, 4; - %set/v v0x245e5f0_0, 8, 4; + %set/v v0xa38650_0, 8, 4; %movi 8, 13, 4; - %set/v v0x245e7f0_0, 8, 4; - %set/v v0x245e870_0, 0, 3; + %set/v v0xa38850_0, 8, 4; + %set/v v0xa388d0_0, 0, 3; %delay 1000000, 0; - %vpi_call 2 171 "$display", "%b | %b | %b | %b | Expect 0010| %b | %b ", v0x245e5f0_0, v0x245e7f0_0, v0x245e870_0, v0x245e670_0, v0x245ebc0_0, v0x245ec40_0; + %vpi_call 2 174 "$display", "%b | %b | %b | %b | Expect 0010| %b | %b ", v0xa38650_0, v0xa38850_0, v0xa388d0_0, v0xa386d0_0, v0xa38c80_0, v0xa38d00_0; %movi 8, 2, 4; - %set/v v0x245e5f0_0, 8, 4; - %set/v v0x245e7f0_0, 1, 4; - %set/v v0x245e870_0, 0, 3; + %set/v v0xa38650_0, 8, 4; + %set/v v0xa38850_0, 1, 4; + %set/v v0xa388d0_0, 0, 3; %delay 1000000, 0; - %vpi_call 2 175 "$display", "%b | %b | %b | %b | Expect 0001| %b | %b ", v0x245e5f0_0, v0x245e7f0_0, v0x245e870_0, v0x245e670_0, v0x245ebc0_0, v0x245ec40_0; + %vpi_call 2 178 "$display", "%b | %b | %b | %b | Expect 0001| %b | %b ", v0xa38650_0, v0xa38850_0, v0xa388d0_0, v0xa386d0_0, v0xa38c80_0, v0xa38d00_0; %movi 8, 8, 4; - %set/v v0x245e5f0_0, 8, 4; + %set/v v0xa38650_0, 8, 4; %movi 8, 3, 4; - %set/v v0x245e7f0_0, 8, 4; - %set/v v0x245e870_0, 0, 3; + %set/v v0xa38850_0, 8, 4; + %set/v v0xa388d0_0, 0, 3; %delay 1000000, 0; - %vpi_call 2 179 "$display", "%b | %b | %b | %b | Expect 1011| %b | %b ", v0x245e5f0_0, v0x245e7f0_0, v0x245e870_0, v0x245e670_0, v0x245ebc0_0, v0x245ec40_0; + %vpi_call 2 182 "$display", "%b | %b | %b | %b | Expect 1011| %b | %b ", v0xa38650_0, v0xa38850_0, v0xa388d0_0, v0xa386d0_0, v0xa38c80_0, v0xa38d00_0; %movi 8, 12, 4; - %set/v v0x245e5f0_0, 8, 4; + %set/v v0xa38650_0, 8, 4; %movi 8, 2, 4; - %set/v v0x245e7f0_0, 8, 4; - %set/v v0x245e870_0, 0, 3; + %set/v v0xa38850_0, 8, 4; + %set/v v0xa388d0_0, 0, 3; %delay 1000000, 0; - %vpi_call 2 183 "$display", "%b | %b | %b | %b | Expect 1110| %b | %b ", v0x245e5f0_0, v0x245e7f0_0, v0x245e870_0, v0x245e670_0, v0x245ebc0_0, v0x245ec40_0; + %vpi_call 2 186 "$display", "%b | %b | %b | %b | Expect 1110| %b | %b ", v0xa38650_0, v0xa38850_0, v0xa388d0_0, v0xa386d0_0, v0xa38c80_0, v0xa38d00_0; %movi 8, 11, 4; - %set/v v0x245e5f0_0, 8, 4; + %set/v v0xa38650_0, 8, 4; %movi 8, 5, 4; - %set/v v0x245e7f0_0, 8, 4; - %set/v v0x245e870_0, 0, 3; + %set/v v0xa38850_0, 8, 4; + %set/v v0xa388d0_0, 0, 3; %delay 1000000, 0; - %vpi_call 2 187 "$display", "%b | %b | %b | %b | Expect 0000| %b | %b ", v0x245e5f0_0, v0x245e7f0_0, v0x245e870_0, v0x245e670_0, v0x245ebc0_0, v0x245ec40_0; + %vpi_call 2 190 "$display", "%b | %b | %b | %b | Expect 0000| %b | %b ", v0xa38650_0, v0xa38850_0, v0xa388d0_0, v0xa386d0_0, v0xa38c80_0, v0xa38d00_0; %movi 8, 7, 4; - %set/v v0x245e5f0_0, 8, 4; + %set/v v0xa38650_0, 8, 4; %movi 8, 9, 4; - %set/v v0x245e7f0_0, 8, 4; - %set/v v0x245e870_0, 0, 3; + %set/v v0xa38850_0, 8, 4; + %set/v v0xa388d0_0, 0, 3; %delay 1000000, 0; - %vpi_call 2 191 "$display", "%b | %b | %b | %b | Expect 0000| %b | %b ", v0x245e5f0_0, v0x245e7f0_0, v0x245e870_0, v0x245e670_0, v0x245ebc0_0, v0x245ec40_0; + %vpi_call 2 194 "$display", "%b | %b | %b | %b | Expect 0000| %b | %b ", v0xa38650_0, v0xa38850_0, v0xa388d0_0, v0xa386d0_0, v0xa38c80_0, v0xa38d00_0; %movi 8, 13, 4; - %set/v v0x245e5f0_0, 8, 4; + %set/v v0xa38650_0, 8, 4; %movi 8, 12, 4; - %set/v v0x245e7f0_0, 8, 4; - %set/v v0x245e870_0, 0, 3; + %set/v v0xa38850_0, 8, 4; + %set/v v0xa388d0_0, 0, 3; %delay 1000000, 0; - %vpi_call 2 195 "$display", "%b | %b | %b | %b | Expect 1001| %b | %b ", v0x245e5f0_0, v0x245e7f0_0, v0x245e870_0, v0x245e670_0, v0x245ebc0_0, v0x245ec40_0; + %vpi_call 2 198 "$display", "%b | %b | %b | %b | Expect 1001| %b | %b ", v0xa38650_0, v0xa38850_0, v0xa388d0_0, v0xa386d0_0, v0xa38c80_0, v0xa38d00_0; %movi 8, 14, 4; - %set/v v0x245e5f0_0, 8, 4; + %set/v v0xa38650_0, 8, 4; %movi 8, 10, 4; - %set/v v0x245e7f0_0, 8, 4; - %set/v v0x245e870_0, 0, 3; + %set/v v0xa38850_0, 8, 4; + %set/v v0xa388d0_0, 0, 3; %delay 1000000, 0; - %vpi_call 2 199 "$display", "%b | %b | %b | %b | Expect 1000| %b | %b ", v0x245e5f0_0, v0x245e7f0_0, v0x245e870_0, v0x245e670_0, v0x245ebc0_0, v0x245ec40_0; + %vpi_call 2 202 "$display", "%b | %b | %b | %b | Expect 1000| %b | %b ", v0xa38650_0, v0xa38850_0, v0xa388d0_0, v0xa386d0_0, v0xa38c80_0, v0xa38d00_0; %movi 8, 5, 4; - %set/v v0x245e5f0_0, 8, 4; + %set/v v0xa38650_0, 8, 4; %movi 8, 6, 4; - %set/v v0x245e7f0_0, 8, 4; - %set/v v0x245e870_0, 0, 3; + %set/v v0xa38850_0, 8, 4; + %set/v v0xa388d0_0, 0, 3; %delay 1000000, 0; - %vpi_call 2 203 "$display", "%b | %b | %b | %b | Expect XXXX| %b | %b ", v0x245e5f0_0, v0x245e7f0_0, v0x245e870_0, v0x245e670_0, v0x245ebc0_0, v0x245ec40_0; + %vpi_call 2 206 "$display", "%b | %b | %b | %b | Expect XXXX| %b | %b ", v0xa38650_0, v0xa38850_0, v0xa388d0_0, v0xa386d0_0, v0xa38c80_0, v0xa38d00_0; %movi 8, 2, 4; - %set/v v0x245e5f0_0, 8, 4; + %set/v v0xa38650_0, 8, 4; %movi 8, 7, 4; - %set/v v0x245e7f0_0, 8, 4; - %set/v v0x245e870_0, 0, 3; + %set/v v0xa38850_0, 8, 4; + %set/v v0xa388d0_0, 0, 3; %delay 1000000, 0; - %vpi_call 2 207 "$display", "%b | %b | %b | %b | Expect XXXX| %b | %b ", v0x245e5f0_0, v0x245e7f0_0, v0x245e870_0, v0x245e670_0, v0x245ebc0_0, v0x245ec40_0; + %vpi_call 2 210 "$display", "%b | %b | %b | %b | Expect XXXX| %b | %b ", v0xa38650_0, v0xa38850_0, v0xa388d0_0, v0xa386d0_0, v0xa38c80_0, v0xa38d00_0; %movi 8, 7, 4; - %set/v v0x245e5f0_0, 8, 4; + %set/v v0xa38650_0, 8, 4; %movi 8, 7, 4; - %set/v v0x245e7f0_0, 8, 4; - %set/v v0x245e870_0, 0, 3; + %set/v v0xa38850_0, 8, 4; + %set/v v0xa388d0_0, 0, 3; %delay 1000000, 0; - %vpi_call 2 211 "$display", "%b | %b | %b | %b | Expect XXXX| %b | %b ", v0x245e5f0_0, v0x245e7f0_0, v0x245e870_0, v0x245e670_0, v0x245ebc0_0, v0x245ec40_0; + %vpi_call 2 214 "$display", "%b | %b | %b | %b | Expect XXXX| %b | %b ", v0xa38650_0, v0xa38850_0, v0xa388d0_0, v0xa386d0_0, v0xa38c80_0, v0xa38d00_0; %movi 8, 8, 4; - %set/v v0x245e5f0_0, 8, 4; - %set/v v0x245e7f0_0, 1, 4; - %set/v v0x245e870_0, 0, 3; + %set/v v0xa38650_0, 8, 4; + %set/v v0xa38850_0, 1, 4; + %set/v v0xa388d0_0, 0, 3; %delay 1000000, 0; - %vpi_call 2 215 "$display", "%b | %b | %b | %b | Expect XXXX| %b | %b ", v0x245e5f0_0, v0x245e7f0_0, v0x245e870_0, v0x245e670_0, v0x245ebc0_0, v0x245ec40_0; + %vpi_call 2 218 "$display", "%b | %b | %b | %b | Expect XXXX| %b | %b ", v0xa38650_0, v0xa38850_0, v0xa388d0_0, v0xa386d0_0, v0xa38c80_0, v0xa38d00_0; %movi 8, 8, 4; - %set/v v0x245e5f0_0, 8, 4; + %set/v v0xa38650_0, 8, 4; %movi 8, 13, 4; - %set/v v0x245e7f0_0, 8, 4; - %set/v v0x245e870_0, 0, 3; + %set/v v0xa38850_0, 8, 4; + %set/v v0xa388d0_0, 0, 3; %delay 1000000, 0; - %vpi_call 2 219 "$display", "%b | %b | %b | %b | Expect XXXX| %b | %b ", v0x245e5f0_0, v0x245e7f0_0, v0x245e870_0, v0x245e670_0, v0x245ebc0_0, v0x245ec40_0; + %vpi_call 2 222 "$display", "%b | %b | %b | %b | Expect XXXX| %b | %b ", v0xa38650_0, v0xa38850_0, v0xa388d0_0, v0xa386d0_0, v0xa38c80_0, v0xa38d00_0; %movi 8, 11, 4; - %set/v v0x245e5f0_0, 8, 4; + %set/v v0xa38650_0, 8, 4; %movi 8, 12, 4; - %set/v v0x245e7f0_0, 8, 4; - %set/v v0x245e870_0, 0, 3; + %set/v v0xa38850_0, 8, 4; + %set/v v0xa388d0_0, 0, 3; %delay 1000000, 0; - %vpi_call 2 223 "$display", "%b | %b | %b | %b | Expect XXXX| %b | %b ", v0x245e5f0_0, v0x245e7f0_0, v0x245e870_0, v0x245e670_0, v0x245ebc0_0, v0x245ec40_0; - %vpi_call 2 225 "$display", "Test 4 Bit SLT Functionality"; - %vpi_call 2 227 "$display", " A | B |Command| Out|ExpectedOut|Cout|OF |SLTflag"; + %vpi_call 2 226 "$display", "%b | %b | %b | %b | Expect XXXX| %b | %b ", v0xa38650_0, v0xa38850_0, v0xa388d0_0, v0xa386d0_0, v0xa38c80_0, v0xa38d00_0; + %vpi_call 2 228 "$display", "Test 4 Bit SLT Functionality"; + %vpi_call 2 230 "$display", " A | B |Command| Out|ExpectedOut|Cout|OF |SLTflag"; %movi 8, 2, 4; - %set/v v0x245e5f0_0, 8, 4; + %set/v v0xa38650_0, 8, 4; %movi 8, 4, 4; - %set/v v0x245e7f0_0, 8, 4; + %set/v v0xa38850_0, 8, 4; %movi 8, 3, 3; - %set/v v0x245e870_0, 8, 3; + %set/v v0xa388d0_0, 8, 3; %delay 1000000, 0; - %vpi_call 2 231 "$display", "%b | %b | %b | %b | Expect 1110| %b | %b | %b", v0x245e5f0_0, v0x245e7f0_0, v0x245e870_0, v0x245e670_0, v0x245ebc0_0, v0x245ec40_0, v0x245ea40_0; + %vpi_call 2 234 "$display", "%b | %b | %b | %b | Expect 1110| %b | %b | %b", v0xa38650_0, v0xa38850_0, v0xa388d0_0, v0xa386d0_0, v0xa38c80_0, v0xa38d00_0, v0xa38ad0_0; %movi 8, 4, 4; - %set/v v0x245e5f0_0, 8, 4; + %set/v v0xa38650_0, 8, 4; %movi 8, 2, 4; - %set/v v0x245e7f0_0, 8, 4; + %set/v v0xa38850_0, 8, 4; %movi 8, 3, 3; - %set/v v0x245e870_0, 8, 3; + %set/v v0xa388d0_0, 8, 3; %delay 1000000, 0; - %vpi_call 2 235 "$display", "%b | %b | %b | %b | Expect 0010| %b | %b | %b", v0x245e5f0_0, v0x245e7f0_0, v0x245e870_0, v0x245e670_0, v0x245ebc0_0, v0x245ec40_0, v0x245ea40_0; + %vpi_call 2 238 "$display", "%b | %b | %b | %b | Expect 0010| %b | %b | %b", v0xa38650_0, v0xa38850_0, v0xa388d0_0, v0xa386d0_0, v0xa38c80_0, v0xa38d00_0, v0xa38ad0_0; %movi 8, 14, 4; - %set/v v0x245e5f0_0, 8, 4; + %set/v v0xa38650_0, 8, 4; %movi 8, 4, 4; - %set/v v0x245e7f0_0, 8, 4; + %set/v v0xa38850_0, 8, 4; %movi 8, 3, 3; - %set/v v0x245e870_0, 8, 3; + %set/v v0xa388d0_0, 8, 3; %delay 1000000, 0; - %vpi_call 2 239 "$display", "%b | %b | %b | %b | Expect 1010| %b | %b | %b", v0x245e5f0_0, v0x245e7f0_0, v0x245e870_0, v0x245e670_0, v0x245ebc0_0, v0x245ec40_0, v0x245ea40_0; + %vpi_call 2 242 "$display", "%b | %b | %b | %b | Expect 1010| %b | %b | %b", v0xa38650_0, v0xa38850_0, v0xa388d0_0, v0xa386d0_0, v0xa38c80_0, v0xa38d00_0, v0xa38ad0_0; %movi 8, 4, 4; - %set/v v0x245e5f0_0, 8, 4; + %set/v v0xa38650_0, 8, 4; %movi 8, 14, 4; - %set/v v0x245e7f0_0, 8, 4; + %set/v v0xa38850_0, 8, 4; %movi 8, 3, 3; - %set/v v0x245e870_0, 8, 3; + %set/v v0xa388d0_0, 8, 3; %delay 1000000, 0; - %vpi_call 2 243 "$display", "%b | %b | %b | %b | Expect 0110| %b | %b | %b", v0x245e5f0_0, v0x245e7f0_0, v0x245e870_0, v0x245e670_0, v0x245ebc0_0, v0x245ec40_0, v0x245ea40_0; + %vpi_call 2 246 "$display", "%b | %b | %b | %b | Expect 0110| %b | %b | %b", v0xa38650_0, v0xa38850_0, v0xa388d0_0, v0xa386d0_0, v0xa38c80_0, v0xa38d00_0, v0xa38ad0_0; %movi 8, 14, 4; - %set/v v0x245e5f0_0, 8, 4; - %set/v v0x245e7f0_0, 1, 4; + %set/v v0xa38650_0, 8, 4; + %set/v v0xa38850_0, 1, 4; %movi 8, 3, 3; - %set/v v0x245e870_0, 8, 3; + %set/v v0xa388d0_0, 8, 3; %delay 1000000, 0; - %vpi_call 2 247 "$display", "%b | %b | %b | %b | Expect 1111| %b | %b | %b", v0x245e5f0_0, v0x245e7f0_0, v0x245e870_0, v0x245e670_0, v0x245ebc0_0, v0x245ec40_0, v0x245ea40_0; - %set/v v0x245e5f0_0, 1, 4; + %vpi_call 2 250 "$display", "%b | %b | %b | %b | Expect 1111| %b | %b | %b", v0xa38650_0, v0xa38850_0, v0xa388d0_0, v0xa386d0_0, v0xa38c80_0, v0xa38d00_0, v0xa38ad0_0; + %set/v v0xa38650_0, 1, 4; %movi 8, 14, 4; - %set/v v0x245e7f0_0, 8, 4; + %set/v v0xa38850_0, 8, 4; %movi 8, 3, 3; - %set/v v0x245e870_0, 8, 3; + %set/v v0xa388d0_0, 8, 3; %delay 1000000, 0; - %vpi_call 2 251 "$display", "%b | %b | %b | %b | Expect 0001| %b | %b | %b", v0x245e5f0_0, v0x245e7f0_0, v0x245e870_0, v0x245e670_0, v0x245ebc0_0, v0x245ec40_0, v0x245ea40_0; + %vpi_call 2 254 "$display", "%b | %b | %b | %b | Expect 0001| %b | %b | %b", v0xa38650_0, v0xa38850_0, v0xa388d0_0, v0xa386d0_0, v0xa38c80_0, v0xa38d00_0, v0xa38ad0_0; %movi 8, 13, 4; - %set/v v0x245e5f0_0, 8, 4; + %set/v v0xa38650_0, 8, 4; %movi 8, 13, 4; - %set/v v0x245e7f0_0, 8, 4; + %set/v v0xa38850_0, 8, 4; %movi 8, 3, 3; - %set/v v0x245e870_0, 8, 3; + %set/v v0xa388d0_0, 8, 3; %delay 1000000, 0; - %vpi_call 2 255 "$display", "%b | %b | %b | %b | Expect 0000| %b | %b | %b", v0x245e5f0_0, v0x245e7f0_0, v0x245e870_0, v0x245e670_0, v0x245ebc0_0, v0x245ec40_0, v0x245ea40_0; + %vpi_call 2 258 "$display", "%b | %b | %b | %b | Expect 0000| %b | %b | %b", v0xa38650_0, v0xa38850_0, v0xa388d0_0, v0xa386d0_0, v0xa38c80_0, v0xa38d00_0, v0xa38ad0_0; %movi 8, 5, 4; - %set/v v0x245e5f0_0, 8, 4; + %set/v v0xa38650_0, 8, 4; %movi 8, 5, 4; - %set/v v0x245e7f0_0, 8, 4; + %set/v v0xa38850_0, 8, 4; %movi 8, 3, 3; - %set/v v0x245e870_0, 8, 3; + %set/v v0xa388d0_0, 8, 3; %delay 1000000, 0; - %vpi_call 2 259 "$display", "%b | %b | %b | %b | Expect 0000| %b | %b | %b", v0x245e5f0_0, v0x245e7f0_0, v0x245e870_0, v0x245e670_0, v0x245ebc0_0, v0x245ec40_0, v0x245ea40_0; + %vpi_call 2 262 "$display", "%b | %b | %b | %b | Expect 0000| %b | %b | %b", v0xa38650_0, v0xa38850_0, v0xa388d0_0, v0xa386d0_0, v0xa38c80_0, v0xa38d00_0, v0xa38ad0_0; %movi 8, 9, 4; - %set/v v0x245e5f0_0, 8, 4; + %set/v v0xa38650_0, 8, 4; %movi 8, 5, 4; - %set/v v0x245e7f0_0, 8, 4; + %set/v v0xa38850_0, 8, 4; %movi 8, 3, 3; - %set/v v0x245e870_0, 8, 3; + %set/v v0xa388d0_0, 8, 3; %delay 1000000, 0; - %vpi_call 2 263 "$display", "%b | %b | %b | %b | Expect XXXX| %b | %b | %b", v0x245e5f0_0, v0x245e7f0_0, v0x245e870_0, v0x245e670_0, v0x245ebc0_0, v0x245ec40_0, v0x245ea40_0; - %vpi_call 2 265 "$display", "Test 4 Bit AND/NAND Functionality"; - %vpi_call 2 267 "$display", " A | B |Command| Out |ExpectedOut-AND"; - %set/v v0x245e5f0_0, 1, 4; - %set/v v0x245e7f0_0, 1, 4; + %vpi_call 2 266 "$display", "%b | %b | %b | %b | Expect XXXX| %b | %b | %b", v0xa38650_0, v0xa38850_0, v0xa388d0_0, v0xa386d0_0, v0xa38c80_0, v0xa38d00_0, v0xa38ad0_0; + %vpi_call 2 268 "$display", "Test 4 Bit AND/NAND Functionality"; + %vpi_call 2 270 "$display", " A | B |Command| Out |ExpectedOut-AND"; + %set/v v0xa38650_0, 1, 4; + %set/v v0xa38850_0, 1, 4; %movi 8, 4, 3; - %set/v v0x245e870_0, 8, 3; + %set/v v0xa388d0_0, 8, 3; %delay 1000000, 0; - %vpi_call 2 271 "$display", "%b | %b | %b | %b | 1111", v0x245e5f0_0, v0x245e7f0_0, v0x245e870_0, v0x245e770_0; - %set/v v0x245e5f0_0, 1, 4; + %vpi_call 2 274 "$display", "%b | %b | %b | %b | 1111", v0xa38650_0, v0xa38850_0, v0xa388d0_0, v0xa387d0_0; + %set/v v0xa38650_0, 1, 4; %movi 8, 10, 4; - %set/v v0x245e7f0_0, 8, 4; + %set/v v0xa38850_0, 8, 4; %movi 8, 4, 3; - %set/v v0x245e870_0, 8, 3; + %set/v v0xa388d0_0, 8, 3; %delay 1000000, 0; - %vpi_call 2 275 "$display", "%b | %b | %b | %b | 1010", v0x245e5f0_0, v0x245e7f0_0, v0x245e870_0, v0x245e770_0; - %set/v v0x245e5f0_0, 1, 4; + %vpi_call 2 278 "$display", "%b | %b | %b | %b | 1010", v0xa38650_0, v0xa38850_0, v0xa388d0_0, v0xa387d0_0; + %set/v v0xa38650_0, 1, 4; %movi 8, 5, 4; - %set/v v0x245e7f0_0, 8, 4; + %set/v v0xa38850_0, 8, 4; %movi 8, 4, 3; - %set/v v0x245e870_0, 8, 3; + %set/v v0xa388d0_0, 8, 3; %delay 1000000, 0; - %vpi_call 2 279 "$display", "%b | %b | %b | %b | 0101", v0x245e5f0_0, v0x245e7f0_0, v0x245e870_0, v0x245e770_0; - %set/v v0x245e5f0_0, 1, 4; - %set/v v0x245e7f0_0, 0, 4; + %vpi_call 2 282 "$display", "%b | %b | %b | %b | 0101", v0xa38650_0, v0xa38850_0, v0xa388d0_0, v0xa387d0_0; + %set/v v0xa38650_0, 1, 4; + %set/v v0xa38850_0, 0, 4; %movi 8, 4, 3; - %set/v v0x245e870_0, 8, 3; + %set/v v0xa388d0_0, 8, 3; %delay 1000000, 0; - %vpi_call 2 283 "$display", "%b | %b | %b | %b | 0000", v0x245e5f0_0, v0x245e7f0_0, v0x245e870_0, v0x245e770_0; - %vpi_call 2 286 "$display", " A | B |Command| Out |ExpectedOut-NAND"; - %set/v v0x245e5f0_0, 1, 4; - %set/v v0x245e7f0_0, 1, 4; + %vpi_call 2 286 "$display", "%b | %b | %b | %b | 0000", v0xa38650_0, v0xa38850_0, v0xa388d0_0, v0xa387d0_0; + %vpi_call 2 289 "$display", " A | B |Command| Out |ExpectedOut-NAND"; + %set/v v0xa38650_0, 1, 4; + %set/v v0xa38850_0, 1, 4; %movi 8, 5, 3; - %set/v v0x245e870_0, 8, 3; + %set/v v0xa388d0_0, 8, 3; %delay 1000000, 0; - %vpi_call 2 290 "$display", "%b | %b | %b | %b | 0000", v0x245e5f0_0, v0x245e7f0_0, v0x245e870_0, v0x245e770_0; - %set/v v0x245e5f0_0, 1, 4; + %vpi_call 2 293 "$display", "%b | %b | %b | %b | 0000", v0xa38650_0, v0xa38850_0, v0xa388d0_0, v0xa387d0_0; + %set/v v0xa38650_0, 1, 4; %movi 8, 10, 4; - %set/v v0x245e7f0_0, 8, 4; + %set/v v0xa38850_0, 8, 4; %movi 8, 5, 3; - %set/v v0x245e870_0, 8, 3; + %set/v v0xa388d0_0, 8, 3; %delay 1000000, 0; - %vpi_call 2 294 "$display", "%b | %b | %b | %b | 0101", v0x245e5f0_0, v0x245e7f0_0, v0x245e870_0, v0x245e770_0; - %set/v v0x245e5f0_0, 1, 4; + %vpi_call 2 297 "$display", "%b | %b | %b | %b | 0101", v0xa38650_0, v0xa38850_0, v0xa388d0_0, v0xa387d0_0; + %set/v v0xa38650_0, 1, 4; %movi 8, 5, 4; - %set/v v0x245e7f0_0, 8, 4; + %set/v v0xa38850_0, 8, 4; %movi 8, 5, 3; - %set/v v0x245e870_0, 8, 3; + %set/v v0xa388d0_0, 8, 3; %delay 1000000, 0; - %vpi_call 2 298 "$display", "%b | %b | %b | %b | 1010", v0x245e5f0_0, v0x245e7f0_0, v0x245e870_0, v0x245e770_0; - %set/v v0x245e5f0_0, 1, 4; - %set/v v0x245e7f0_0, 0, 4; + %vpi_call 2 301 "$display", "%b | %b | %b | %b | 1010", v0xa38650_0, v0xa38850_0, v0xa388d0_0, v0xa387d0_0; + %set/v v0xa38650_0, 1, 4; + %set/v v0xa38850_0, 0, 4; %movi 8, 5, 3; - %set/v v0x245e870_0, 8, 3; + %set/v v0xa388d0_0, 8, 3; %delay 1000000, 0; - %vpi_call 2 302 "$display", "%b | %b | %b | %b | 1111", v0x245e5f0_0, v0x245e7f0_0, v0x245e870_0, v0x245e770_0; - %vpi_call 2 304 "$display", "Test 4 Bit OR/NOR/XOR Functionality"; - %vpi_call 2 306 "$display", " A | B |Command | Out |ExpectedOut-OR"; + %vpi_call 2 305 "$display", "%b | %b | %b | %b | 1111", v0xa38650_0, v0xa38850_0, v0xa388d0_0, v0xa387d0_0; + %vpi_call 2 307 "$display", "Test 4 Bit OR/NOR/XOR Functionality"; + %vpi_call 2 309 "$display", " A | B |Command | Out |ExpectedOut-OR"; %movi 8, 10, 4; - %set/v v0x245e5f0_0, 8, 4; + %set/v v0xa38650_0, 8, 4; %movi 8, 5, 4; - %set/v v0x245e7f0_0, 8, 4; - %set/v v0x245e870_0, 1, 3; + %set/v v0xa38850_0, 8, 4; + %set/v v0xa388d0_0, 1, 3; %delay 1000000, 0; - %vpi_call 2 310 "$display", "%b | %b | %b | %b | 1111", v0x245e5f0_0, v0x245e7f0_0, v0x245e870_0, v0x245e970_0; - %set/v v0x245e5f0_0, 1, 4; + %vpi_call 2 313 "$display", "%b | %b | %b | %b | 1111", v0xa38650_0, v0xa38850_0, v0xa388d0_0, v0xa389d0_0; + %set/v v0xa38650_0, 1, 4; %movi 8, 5, 4; - %set/v v0x245e7f0_0, 8, 4; - %set/v v0x245e870_0, 1, 3; + %set/v v0xa38850_0, 8, 4; + %set/v v0xa388d0_0, 1, 3; %delay 1000000, 0; - %vpi_call 2 314 "$display", "%b | %b | %b | %b | 1111", v0x245e5f0_0, v0x245e7f0_0, v0x245e870_0, v0x245e970_0; + %vpi_call 2 317 "$display", "%b | %b | %b | %b | 1111", v0xa38650_0, v0xa38850_0, v0xa388d0_0, v0xa389d0_0; %movi 8, 11, 4; - %set/v v0x245e5f0_0, 8, 4; - %set/v v0x245e7f0_0, 0, 4; - %set/v v0x245e870_0, 1, 3; + %set/v v0xa38650_0, 8, 4; + %set/v v0xa38850_0, 0, 4; + %set/v v0xa388d0_0, 1, 3; %delay 1000000, 0; - %vpi_call 2 318 "$display", "%b | %b | %b | %b | 1011", v0x245e5f0_0, v0x245e7f0_0, v0x245e870_0, v0x245e970_0; - %vpi_call 2 320 "$display", " A | B |Command | Out |ExpectedOut-NOR"; + %vpi_call 2 321 "$display", "%b | %b | %b | %b | 1011", v0xa38650_0, v0xa38850_0, v0xa388d0_0, v0xa389d0_0; + %vpi_call 2 323 "$display", " A | B |Command | Out |ExpectedOut-NOR"; %movi 8, 10, 4; - %set/v v0x245e5f0_0, 8, 4; + %set/v v0xa38650_0, 8, 4; %movi 8, 5, 4; - %set/v v0x245e7f0_0, 8, 4; + %set/v v0xa38850_0, 8, 4; %movi 8, 6, 3; - %set/v v0x245e870_0, 8, 3; + %set/v v0xa388d0_0, 8, 3; %delay 1000000, 0; - %vpi_call 2 324 "$display", "%b | %b | %b | %b | 0000", v0x245e5f0_0, v0x245e7f0_0, v0x245e870_0, v0x245e970_0; - %set/v v0x245e5f0_0, 1, 4; + %vpi_call 2 327 "$display", "%b | %b | %b | %b | 0000", v0xa38650_0, v0xa38850_0, v0xa388d0_0, v0xa389d0_0; + %set/v v0xa38650_0, 1, 4; %movi 8, 5, 4; - %set/v v0x245e7f0_0, 8, 4; + %set/v v0xa38850_0, 8, 4; %movi 8, 6, 3; - %set/v v0x245e870_0, 8, 3; + %set/v v0xa388d0_0, 8, 3; %delay 1000000, 0; - %vpi_call 2 328 "$display", "%b | %b | %b | %b | 0000", v0x245e5f0_0, v0x245e7f0_0, v0x245e870_0, v0x245e970_0; + %vpi_call 2 331 "$display", "%b | %b | %b | %b | 0000", v0xa38650_0, v0xa38850_0, v0xa388d0_0, v0xa389d0_0; %movi 8, 11, 4; - %set/v v0x245e5f0_0, 8, 4; - %set/v v0x245e7f0_0, 0, 4; + %set/v v0xa38650_0, 8, 4; + %set/v v0xa38850_0, 0, 4; %movi 8, 6, 3; - %set/v v0x245e870_0, 8, 3; + %set/v v0xa388d0_0, 8, 3; %delay 1000000, 0; - %vpi_call 2 332 "$display", "%b | %b | %b | %b | 0100", v0x245e5f0_0, v0x245e7f0_0, v0x245e870_0, v0x245e970_0; - %vpi_call 2 334 "$display", " A | B |Command | Out |ExpectedOut-XOR"; + %vpi_call 2 335 "$display", "%b | %b | %b | %b | 0100", v0xa38650_0, v0xa38850_0, v0xa388d0_0, v0xa389d0_0; + %vpi_call 2 337 "$display", " A | B |Command | Out |ExpectedOut-XOR"; %movi 8, 10, 4; - %set/v v0x245e5f0_0, 8, 4; + %set/v v0xa38650_0, 8, 4; %movi 8, 5, 4; - %set/v v0x245e7f0_0, 8, 4; + %set/v v0xa38850_0, 8, 4; %movi 8, 2, 3; - %set/v v0x245e870_0, 8, 3; + %set/v v0xa388d0_0, 8, 3; %delay 1000000, 0; - %vpi_call 2 338 "$display", "%b | %b | %b | %b | 1111", v0x245e5f0_0, v0x245e7f0_0, v0x245e870_0, v0x245e970_0; - %set/v v0x245e5f0_0, 1, 4; + %vpi_call 2 341 "$display", "%b | %b | %b | %b | 1111", v0xa38650_0, v0xa38850_0, v0xa388d0_0, v0xa389d0_0; + %set/v v0xa38650_0, 1, 4; %movi 8, 5, 4; - %set/v v0x245e7f0_0, 8, 4; + %set/v v0xa38850_0, 8, 4; %movi 8, 2, 3; - %set/v v0x245e870_0, 8, 3; + %set/v v0xa388d0_0, 8, 3; %delay 1000000, 0; - %vpi_call 2 342 "$display", "%b | %b | %b | %b | 1010", v0x245e5f0_0, v0x245e7f0_0, v0x245e870_0, v0x245e970_0; + %vpi_call 2 345 "$display", "%b | %b | %b | %b | 1010", v0xa38650_0, v0xa38850_0, v0xa388d0_0, v0xa389d0_0; %movi 8, 11, 4; - %set/v v0x245e5f0_0, 8, 4; - %set/v v0x245e7f0_0, 0, 4; + %set/v v0xa38650_0, 8, 4; + %set/v v0xa38850_0, 0, 4; %movi 8, 2, 3; - %set/v v0x245e870_0, 8, 3; + %set/v v0xa388d0_0, 8, 3; %delay 1000000, 0; - %vpi_call 2 346 "$display", "%b | %b | %b | %b | 1011", v0x245e5f0_0, v0x245e7f0_0, v0x245e870_0, v0x245e970_0; - %vpi_call 2 348 "$display", "Test 4 Bit ALU Functionality"; - %vpi_call 2 350 "$display", " A | B |Command | Out |ExpectedOut | COut | OF |SLT|Zero"; - %set/v v0x245e5f0_0, 1, 4; - %set/v v0x245e7f0_0, 1, 4; + %vpi_call 2 349 "$display", "%b | %b | %b | %b | 1011", v0xa38650_0, v0xa38850_0, v0xa388d0_0, v0xa389d0_0; + %vpi_call 2 351 "$display", "Test 4 Bit ALU Functionality"; + %vpi_call 2 353 "$display", " A | B |Command | Out |ExpectedOut | COut | OF |SLT|Zero"; + %set/v v0xa38650_0, 1, 4; + %set/v v0xa38850_0, 1, 4; %movi 8, 4, 3; - %set/v v0x245e870_0, 8, 3; + %set/v v0xa388d0_0, 8, 3; %delay 1000000, 0; - %vpi_call 2 355 "$display", "%b | %b | %b - AND | %b | 1111 | %b | %b | %b | %b", v0x245e5f0_0, v0x245e7f0_0, v0x245e870_0, v0x245e8f0_0, v0x245ebc0_0, v0x245ec40_0, v0x245ea40_0, v0x245e6f0_0; - %set/v v0x245e5f0_0, 1, 4; - %set/v v0x245e7f0_0, 0, 4; + %vpi_call 2 358 "$display", "%b | %b | %b - AND | %b | 1111 | %b | %b | %b | %b", v0xa38650_0, v0xa38850_0, v0xa388d0_0, v0xa38950_0, v0xa38c80_0, v0xa38d00_0, v0xa38ad0_0, v0xa38750_0; + %set/v v0xa38650_0, 1, 4; + %set/v v0xa38850_0, 0, 4; %movi 8, 5, 3; - %set/v v0x245e870_0, 8, 3; + %set/v v0xa388d0_0, 8, 3; %delay 1000000, 0; - %vpi_call 2 360 "$display", "%b | %b | %b - NAND | %b | 1111 | %b | %b | %b | %b", v0x245e5f0_0, v0x245e7f0_0, v0x245e870_0, v0x245e8f0_0, v0x245ebc0_0, v0x245ec40_0, v0x245ea40_0, v0x245e6f0_0; - %set/v v0x245e5f0_0, 1, 4; + %vpi_call 2 363 "$display", "%b | %b | %b - NAND | %b | 1111 | %b | %b | %b | %b", v0xa38650_0, v0xa38850_0, v0xa388d0_0, v0xa38950_0, v0xa38c80_0, v0xa38d00_0, v0xa38ad0_0, v0xa38750_0; + %set/v v0xa38650_0, 1, 4; %movi 8, 5, 4; - %set/v v0x245e7f0_0, 8, 4; - %set/v v0x245e870_0, 1, 3; + %set/v v0xa38850_0, 8, 4; + %set/v v0xa388d0_0, 1, 3; %delay 1000000, 0; - %vpi_call 2 365 "$display", "%b | %b | %b - OR | %b | 1111 | %b | %b | %b | %b", v0x245e5f0_0, v0x245e7f0_0, v0x245e870_0, v0x245e8f0_0, v0x245ebc0_0, v0x245ec40_0, v0x245ea40_0, v0x245e6f0_0; + %vpi_call 2 368 "$display", "%b | %b | %b - OR | %b | 1111 | %b | %b | %b | %b", v0xa38650_0, v0xa38850_0, v0xa388d0_0, v0xa38950_0, v0xa38c80_0, v0xa38d00_0, v0xa38ad0_0, v0xa38750_0; %movi 8, 11, 4; - %set/v v0x245e5f0_0, 8, 4; - %set/v v0x245e7f0_0, 0, 4; + %set/v v0xa38650_0, 8, 4; + %set/v v0xa38850_0, 0, 4; %movi 8, 6, 3; - %set/v v0x245e870_0, 8, 3; + %set/v v0xa388d0_0, 8, 3; %delay 1000000, 0; - %vpi_call 2 370 "$display", "%b | %b | %b - NOR | %b | 0100 | %b | %b | %b | %b", v0x245e5f0_0, v0x245e7f0_0, v0x245e870_0, v0x245e8f0_0, v0x245ebc0_0, v0x245ec40_0, v0x245ea40_0, v0x245e6f0_0; + %vpi_call 2 373 "$display", "%b | %b | %b - NOR | %b | 0100 | %b | %b | %b | %b", v0xa38650_0, v0xa38850_0, v0xa388d0_0, v0xa38950_0, v0xa38c80_0, v0xa38d00_0, v0xa38ad0_0, v0xa38750_0; %movi 8, 11, 4; - %set/v v0x245e5f0_0, 8, 4; - %set/v v0x245e7f0_0, 0, 4; + %set/v v0xa38650_0, 8, 4; + %set/v v0xa38850_0, 0, 4; %movi 8, 2, 3; - %set/v v0x245e870_0, 8, 3; + %set/v v0xa388d0_0, 8, 3; %delay 1000000, 0; - %vpi_call 2 375 "$display", "%b | %b | %b - XOR | %b | 1011 | %b | %b | %b | %b", v0x245e5f0_0, v0x245e7f0_0, v0x245e870_0, v0x245e8f0_0, v0x245ebc0_0, v0x245ec40_0, v0x245ea40_0, v0x245e6f0_0; + %vpi_call 2 378 "$display", "%b | %b | %b - XOR | %b | 1011 | %b | %b | %b | %b", v0xa38650_0, v0xa38850_0, v0xa388d0_0, v0xa38950_0, v0xa38c80_0, v0xa38d00_0, v0xa38ad0_0, v0xa38750_0; %movi 8, 2, 4; - %set/v v0x245e5f0_0, 8, 4; + %set/v v0xa38650_0, 8, 4; %movi 8, 4, 4; - %set/v v0x245e7f0_0, 8, 4; - %set/v v0x245e870_0, 0, 3; + %set/v v0xa38850_0, 8, 4; + %set/v v0xa388d0_0, 0, 3; %delay 1000000, 0; - %vpi_call 2 380 "$display", "%b | %b | %b - ADD | %b | 0110 | %b | %b | %b | %b", v0x245e5f0_0, v0x245e7f0_0, v0x245e870_0, v0x245e8f0_0, v0x245ebc0_0, v0x245ec40_0, v0x245ea40_0, v0x245e6f0_0; + %vpi_call 2 383 "$display", "%b | %b | %b - ADD | %b | 0110 | %b | %b | %b | %b", v0xa38650_0, v0xa38850_0, v0xa388d0_0, v0xa38950_0, v0xa38c80_0, v0xa38d00_0, v0xa38ad0_0, v0xa38750_0; %movi 8, 11, 4; - %set/v v0x245e5f0_0, 8, 4; + %set/v v0xa38650_0, 8, 4; %movi 8, 12, 4; - %set/v v0x245e7f0_0, 8, 4; - %set/v v0x245e870_0, 0, 3; + %set/v v0xa38850_0, 8, 4; + %set/v v0xa388d0_0, 0, 3; %delay 1000000, 0; - %vpi_call 2 384 "$display", "%b | %b | %b - ADD | %b | XXXX | %b | %b | %b | %b", v0x245e5f0_0, v0x245e7f0_0, v0x245e870_0, v0x245e8f0_0, v0x245ebc0_0, v0x245ec40_0, v0x245ea40_0, v0x245e6f0_0; + %vpi_call 2 387 "$display", "%b | %b | %b - ADD | %b | XXXX | %b | %b | %b | %b", v0xa38650_0, v0xa38850_0, v0xa388d0_0, v0xa38950_0, v0xa38c80_0, v0xa38d00_0, v0xa38ad0_0, v0xa38750_0; %movi 8, 2, 4; - %set/v v0x245e5f0_0, 8, 4; + %set/v v0xa38650_0, 8, 4; %movi 8, 4, 4; - %set/v v0x245e7f0_0, 8, 4; + %set/v v0xa38850_0, 8, 4; %movi 8, 1, 3; - %set/v v0x245e870_0, 8, 3; + %set/v v0xa388d0_0, 8, 3; %delay 1000000, 0; - %vpi_call 2 389 "$display", "%b | %b | %b - SUB | %b | 1110 | %b | %b | %b | %b", v0x245e5f0_0, v0x245e7f0_0, v0x245e870_0, v0x245e8f0_0, v0x245ebc0_0, v0x245ec40_0, v0x245ea40_0, v0x245e6f0_0; + %vpi_call 2 392 "$display", "%b | %b | %b - SUB | %b | 1110 | %b | %b | %b | %b", v0xa38650_0, v0xa38850_0, v0xa388d0_0, v0xa38950_0, v0xa38c80_0, v0xa38d00_0, v0xa38ad0_0, v0xa38750_0; %movi 8, 9, 4; - %set/v v0x245e5f0_0, 8, 4; + %set/v v0xa38650_0, 8, 4; %movi 8, 3, 4; - %set/v v0x245e7f0_0, 8, 4; + %set/v v0xa38850_0, 8, 4; %movi 8, 1, 3; - %set/v v0x245e870_0, 8, 3; + %set/v v0xa388d0_0, 8, 3; %delay 1000000, 0; - %vpi_call 2 393 "$display", "%b | %b | %b - SUB | %b | XXXX | %b | %b | %b | %b", v0x245e5f0_0, v0x245e7f0_0, v0x245e870_0, v0x245e8f0_0, v0x245ebc0_0, v0x245ec40_0, v0x245ea40_0, v0x245e6f0_0; + %vpi_call 2 396 "$display", "%b | %b | %b - SUB | %b | XXXX | %b | %b | %b | %b", v0xa38650_0, v0xa38850_0, v0xa388d0_0, v0xa38950_0, v0xa38c80_0, v0xa38d00_0, v0xa38ad0_0, v0xa38750_0; %movi 8, 4, 4; - %set/v v0x245e5f0_0, 8, 4; + %set/v v0xa38650_0, 8, 4; %movi 8, 2, 4; - %set/v v0x245e7f0_0, 8, 4; + %set/v v0xa38850_0, 8, 4; %movi 8, 3, 3; - %set/v v0x245e870_0, 8, 3; + %set/v v0xa388d0_0, 8, 3; %delay 1000000, 0; - %vpi_call 2 399 "$display", "%b | %b | %b - SLT | %b | 0010 | %b | %b | %b | %b", v0x245e5f0_0, v0x245e7f0_0, v0x245e870_0, v0x245e8f0_0, v0x245ebc0_0, v0x245ec40_0, v0x245ea40_0, v0x245e6f0_0; + %vpi_call 2 402 "$display", "%b | %b | %b - SLT | %b | 0010 | %b | %b | %b | %b", v0xa38650_0, v0xa38850_0, v0xa388d0_0, v0xa38950_0, v0xa38c80_0, v0xa38d00_0, v0xa38ad0_0, v0xa38750_0; %movi 8, 9, 4; - %set/v v0x245e5f0_0, 8, 4; + %set/v v0xa38650_0, 8, 4; %movi 8, 5, 4; - %set/v v0x245e7f0_0, 8, 4; + %set/v v0xa38850_0, 8, 4; %movi 8, 3, 3; - %set/v v0x245e870_0, 8, 3; + %set/v v0xa388d0_0, 8, 3; %delay 1000000, 0; - %vpi_call 2 403 "$display", "%b | %b | %b - SLT | %b | XXXX | %b | %b | %b | %b", v0x245e5f0_0, v0x245e7f0_0, v0x245e870_0, v0x245e8f0_0, v0x245ebc0_0, v0x245ec40_0, v0x245ea40_0, v0x245e6f0_0; - %set/v v0x245e5f0_0, 0, 4; - %set/v v0x245e7f0_0, 1, 4; + %vpi_call 2 406 "$display", "%b | %b | %b - SLT | %b | XXXX | %b | %b | %b | %b", v0xa38650_0, v0xa38850_0, v0xa388d0_0, v0xa38950_0, v0xa38c80_0, v0xa38d00_0, v0xa38ad0_0, v0xa38750_0; + %set/v v0xa38650_0, 0, 4; + %set/v v0xa38850_0, 1, 4; %movi 8, 4, 3; - %set/v v0x245e870_0, 8, 3; + %set/v v0xa388d0_0, 8, 3; %delay 1000000, 0; - %vpi_call 2 409 "$display", "%b | %b | %b - AND | %b | 0000 | %b | %b | %b | %b", v0x245e5f0_0, v0x245e7f0_0, v0x245e870_0, v0x245e8f0_0, v0x245ebc0_0, v0x245ec40_0, v0x245ea40_0, v0x245e6f0_0; - %set/v v0x245e5f0_0, 1, 4; - %set/v v0x245e7f0_0, 1, 4; + %vpi_call 2 412 "$display", "%b | %b | %b - AND | %b | 0000 | %b | %b | %b | %b", v0xa38650_0, v0xa38850_0, v0xa388d0_0, v0xa38950_0, v0xa38c80_0, v0xa38d00_0, v0xa38ad0_0, v0xa38750_0; + %set/v v0xa38650_0, 1, 4; + %set/v v0xa38850_0, 1, 4; %movi 8, 5, 3; - %set/v v0x245e870_0, 8, 3; + %set/v v0xa388d0_0, 8, 3; %delay 1000000, 0; - %vpi_call 2 412 "$display", "%b | %b | %b - NAND | %b | 0000 | %b | %b | %b | %b", v0x245e5f0_0, v0x245e7f0_0, v0x245e870_0, v0x245e8f0_0, v0x245ebc0_0, v0x245ec40_0, v0x245ea40_0, v0x245e6f0_0; - %set/v v0x245e5f0_0, 0, 4; - %set/v v0x245e7f0_0, 0, 4; - %set/v v0x245e870_0, 1, 3; + %vpi_call 2 415 "$display", "%b | %b | %b - NAND | %b | 0000 | %b | %b | %b | %b", v0xa38650_0, v0xa38850_0, v0xa388d0_0, v0xa38950_0, v0xa38c80_0, v0xa38d00_0, v0xa38ad0_0, v0xa38750_0; + %set/v v0xa38650_0, 0, 4; + %set/v v0xa38850_0, 0, 4; + %set/v v0xa388d0_0, 1, 3; %delay 1000000, 0; - %vpi_call 2 415 "$display", "%b | %b | %b - OR | %b | 0000 | %b | %b | %b | %b", v0x245e5f0_0, v0x245e7f0_0, v0x245e870_0, v0x245e8f0_0, v0x245ebc0_0, v0x245ec40_0, v0x245ea40_0, v0x245e6f0_0; + %vpi_call 2 418 "$display", "%b | %b | %b - OR | %b | 0000 | %b | %b | %b | %b", v0xa38650_0, v0xa38850_0, v0xa388d0_0, v0xa38950_0, v0xa38c80_0, v0xa38d00_0, v0xa38ad0_0, v0xa38750_0; %movi 8, 11, 4; - %set/v v0x245e5f0_0, 8, 4; + %set/v v0xa38650_0, 8, 4; %movi 8, 4, 4; - %set/v v0x245e7f0_0, 8, 4; + %set/v v0xa38850_0, 8, 4; %movi 8, 6, 3; - %set/v v0x245e870_0, 8, 3; + %set/v v0xa388d0_0, 8, 3; %delay 1000000, 0; - %vpi_call 2 417 "$display", "%b | %b | %b - NOR | %b | 0000 | %b | %b | %b | %b", v0x245e5f0_0, v0x245e7f0_0, v0x245e870_0, v0x245e8f0_0, v0x245ebc0_0, v0x245ec40_0, v0x245ea40_0, v0x245e6f0_0; + %vpi_call 2 420 "$display", "%b | %b | %b - NOR | %b | 0000 | %b | %b | %b | %b", v0xa38650_0, v0xa38850_0, v0xa388d0_0, v0xa38950_0, v0xa38c80_0, v0xa38d00_0, v0xa38ad0_0, v0xa38750_0; %movi 8, 11, 4; - %set/v v0x245e5f0_0, 8, 4; + %set/v v0xa38650_0, 8, 4; %movi 8, 11, 4; - %set/v v0x245e7f0_0, 8, 4; + %set/v v0xa38850_0, 8, 4; %movi 8, 2, 3; - %set/v v0x245e870_0, 8, 3; + %set/v v0xa388d0_0, 8, 3; %delay 1000000, 0; - %vpi_call 2 420 "$display", "%b | %b | %b - XOR | %b | 0000 | %b | %b | %b | %b", v0x245e5f0_0, v0x245e7f0_0, v0x245e870_0, v0x245e8f0_0, v0x245ebc0_0, v0x245ec40_0, v0x245ea40_0, v0x245e6f0_0; + %vpi_call 2 423 "$display", "%b | %b | %b - XOR | %b | 0000 | %b | %b | %b | %b", v0xa38650_0, v0xa38850_0, v0xa388d0_0, v0xa38950_0, v0xa38c80_0, v0xa38d00_0, v0xa38ad0_0, v0xa38750_0; %movi 8, 2, 4; - %set/v v0x245e5f0_0, 8, 4; + %set/v v0xa38650_0, 8, 4; %movi 8, 14, 4; - %set/v v0x245e7f0_0, 8, 4; - %set/v v0x245e870_0, 0, 3; + %set/v v0xa38850_0, 8, 4; + %set/v v0xa388d0_0, 0, 3; %delay 1000000, 0; - %vpi_call 2 423 "$display", "%b | %b | %b - ADD | %b | 0000 | %b | %b | %b | %b", v0x245e5f0_0, v0x245e7f0_0, v0x245e870_0, v0x245e8f0_0, v0x245ebc0_0, v0x245ec40_0, v0x245ea40_0, v0x245e6f0_0; + %vpi_call 2 426 "$display", "%b | %b | %b - ADD | %b | 0000 | %b | %b | %b | %b", v0xa38650_0, v0xa38850_0, v0xa388d0_0, v0xa38950_0, v0xa38c80_0, v0xa38d00_0, v0xa38ad0_0, v0xa38750_0; %movi 8, 2, 4; - %set/v v0x245e5f0_0, 8, 4; + %set/v v0xa38650_0, 8, 4; %movi 8, 2, 4; - %set/v v0x245e7f0_0, 8, 4; + %set/v v0xa38850_0, 8, 4; %movi 8, 1, 3; - %set/v v0x245e870_0, 8, 3; + %set/v v0xa388d0_0, 8, 3; %delay 1000000, 0; - %vpi_call 2 426 "$display", "%b | %b | %b - SUB | %b | 0000 | %b | %b | %b | %b", v0x245e5f0_0, v0x245e7f0_0, v0x245e870_0, v0x245e8f0_0, v0x245ebc0_0, v0x245ec40_0, v0x245ea40_0, v0x245e6f0_0; - %set/v v0x245e5f0_0, 0, 4; - %set/v v0x245e7f0_0, 0, 4; + %vpi_call 2 429 "$display", "%b | %b | %b - SUB | %b | 0000 | %b | %b | %b | %b", v0xa38650_0, v0xa38850_0, v0xa388d0_0, v0xa38950_0, v0xa38c80_0, v0xa38d00_0, v0xa38ad0_0, v0xa38750_0; + %set/v v0xa38650_0, 0, 4; + %set/v v0xa38850_0, 0, 4; %movi 8, 3, 3; - %set/v v0x245e870_0, 8, 3; + %set/v v0xa388d0_0, 8, 3; %delay 1000000, 0; - %vpi_call 2 430 "$display", "%b | %b | %b - SLT | %b | 0000 | %b | %b | %b | %b", v0x245e5f0_0, v0x245e7f0_0, v0x245e870_0, v0x245e8f0_0, v0x245ebc0_0, v0x245ec40_0, v0x245ea40_0, v0x245e6f0_0; + %vpi_call 2 433 "$display", "%b | %b | %b - SLT | %b | 0000 | %b | %b | %b | %b", v0xa38650_0, v0xa38850_0, v0xa388d0_0, v0xa38950_0, v0xa38c80_0, v0xa38d00_0, v0xa38ad0_0, v0xa38750_0; %end; .thread T_0; # The file index is used to find the file name in the following table. diff --git a/testing.t.v b/testing.t.v index 1fb0369..cf46736 100644 --- a/testing.t.v +++ b/testing.t.v @@ -129,6 +129,7 @@ output [size-1:0] OneBitFinalOut; output [size-1:0] OrNorXorOut; output [size-1:0] AndNandOut; wire [size-1:0] AddSubSLTSum; +wire [size-1:0] SLTSum; wire carryout; wire overflow; wire SLTflag; @@ -144,11 +145,13 @@ wire [size-1:0] CarryoutWire; AddSubSLT32 trial(AddSubSLTSum, carryout, overflow, SLTflag, subtract, A, B, Command, carryin); +SLT32 test(SLTSum, carryout, overflow, SLTflag, subtract, A, B, Command, carryin); + AndNand32 trial1(AndNandOut, A, B, Command); OrNorXor32 trial2(OrNorXorOut, A, B, Command); -Bitslice32 superalu(OneBitFinalOut, AddSubSLTSum, carryout, overflow, SLTflag, OrNorXorOut, AndNandOut, subtract, ZeroFlag, AllZeros, A, B, Command, carryin); +Bitslice32 superalu(OneBitFinalOut, AddSubSLTSum, SLTSum, carryout, overflow, SLTflag, OrNorXorOut, AndNandOut, subtract, ZeroFlag, AllZeros, A, B, Command, carryin); initial begin $dumpfile("FullALU.vcd"); From a20b472b7b3d964a4ff4c3cfb70ea59e329194bc Mon Sep 17 00:00:00 2001 From: mjakus Date: Tue, 10 Oct 2017 21:04:54 -0400 Subject: [PATCH 25/28] Maybe all that still needs to be done is commenting --- FullALU.vcd | 55841 ++++++++++++++++++++++++-------------------------- alu.v | 142 +- test | 6274 +++--- testing.t.v | 39 +- 4 files changed, 30047 insertions(+), 32249 deletions(-) diff --git a/FullALU.vcd b/FullALU.vcd index ee1d5b2..bb76593 100644 --- a/FullALU.vcd +++ b/FullALU.vcd @@ -1,5 +1,5 @@ $date - Tue Oct 10 18:24:46 2017 + Tue Oct 10 20:57:35 2017 $end $version Icarus Verilog @@ -15,1327 +15,1236 @@ $var wire 4 $ OneBitFinalOut [3:0] $end $var wire 4 % OrNorXorOut [3:0] $end $var wire 4 & SLTSum [3:0] $end $var wire 1 ' SLTflag $end -$var wire 4 ( ZeroFlag [3:0] $end -$var wire 1 ) carryout $end -$var wire 1 * overflow $end -$var wire 4 + subtract [3:0] $end -$var reg 4 , A [3:0] $end -$var reg 4 - B [3:0] $end -$var reg 3 . Command [2:0] $end -$var reg 4 / carryin [3:0] $end +$var wire 1 ( SLTflag1 $end +$var wire 4 ) ZeroFlag [3:0] $end +$var wire 1 * carryout $end +$var wire 1 + overflow $end +$var wire 4 , subtract [3:0] $end +$var reg 4 - A [3:0] $end +$var reg 4 . B [3:0] $end +$var reg 3 / Command [2:0] $end +$var reg 4 0 carryin [3:0] $end $scope module trial $end -$var wire 4 0 A [3:0] $end -$var wire 4 1 AddSubSLTSum [3:0] $end -$var wire 4 2 B [3:0] $end -$var wire 4 3 CarryoutWire [3:0] $end -$var wire 3 4 Command [2:0] $end -$var wire 4 5 NewVal [3:0] $end -$var wire 1 6 Res0OF1 $end -$var wire 1 7 Res1OF0 $end -$var wire 1 ' SLTflag $end -$var wire 1 8 SLTflag0 $end -$var wire 1 9 SLTflag1 $end -$var wire 1 : SLTon $end -$var wire 4 ; carryin [3:0] $end -$var wire 1 ) carryout $end -$var wire 1 < nAddSubSLTSum $end -$var wire 1 = nCmd2 $end -$var wire 1 > nOF $end -$var wire 1 * overflow $end -$var wire 4 ? subtract [3:0] $end +$var wire 4 1 A [3:0] $end +$var wire 4 2 AddSubSLTSum [3:0] $end +$var wire 4 3 B [3:0] $end +$var wire 4 4 CarryoutWire [3:0] $end +$var wire 3 5 Command [2:0] $end +$var wire 4 6 carryin [3:0] $end +$var wire 1 * carryout $end +$var wire 1 + overflow $end +$var wire 4 7 subtract [3:0] $end $scope module attempt2 $end -$var wire 1 @ A $end -$var wire 1 A AandB $end -$var wire 1 B AddSubSLTSum $end -$var wire 1 C AxorB $end -$var wire 1 D B $end -$var wire 1 E BornB $end -$var wire 1 F CINandAxorB $end -$var wire 3 G Command [2:0] $end -$var wire 1 H carryin $end -$var wire 1 I carryout $end -$var wire 1 J nB $end -$var wire 1 K nCmd2 $end -$var wire 1 L subtract $end +$var wire 1 8 A $end +$var wire 1 9 AandB $end +$var wire 1 : AddSubSLTSum $end +$var wire 1 ; AxorB $end +$var wire 1 < B $end +$var wire 1 = BornB $end +$var wire 1 > CINandAxorB $end +$var wire 3 ? Command [2:0] $end +$var wire 1 @ carryin $end +$var wire 1 A carryout $end +$var wire 1 B nB $end +$var wire 1 C nCmd2 $end +$var wire 1 D subtract $end $scope module mux0 $end -$var wire 1 M S $end -$var wire 1 D in0 $end -$var wire 1 J in1 $end -$var wire 1 N nS $end -$var wire 1 O out0 $end -$var wire 1 P out1 $end -$var wire 1 E outfinal $end -$upscope $end +$var wire 1 E S $end +$var wire 1 < in0 $end +$var wire 1 B in1 $end +$var wire 1 F nS $end +$var wire 1 G out0 $end +$var wire 1 H out1 $end +$var wire 1 = outfinal $end $upscope $end -$scope module setSLTres $end -$var wire 1 : S $end -$var wire 1 Q in0 $end -$var wire 1 R in1 $end -$var wire 1 S nS $end -$var wire 1 T out0 $end -$var wire 1 U out1 $end -$var wire 1 V outfinal $end $upscope $end $scope begin addbits[1] $end $scope module attempt $end -$var wire 1 W A $end -$var wire 1 X AandB $end -$var wire 1 Y AddSubSLTSum $end -$var wire 1 Z AxorB $end -$var wire 1 [ B $end -$var wire 1 \ BornB $end -$var wire 1 ] CINandAxorB $end -$var wire 3 ^ Command [2:0] $end -$var wire 1 _ carryin $end -$var wire 1 ` carryout $end -$var wire 1 a nB $end -$var wire 1 b nCmd2 $end -$var wire 1 c subtract $end +$var wire 1 I A $end +$var wire 1 J AandB $end +$var wire 1 K AddSubSLTSum $end +$var wire 1 L AxorB $end +$var wire 1 M B $end +$var wire 1 N BornB $end +$var wire 1 O CINandAxorB $end +$var wire 3 P Command [2:0] $end +$var wire 1 Q carryin $end +$var wire 1 R carryout $end +$var wire 1 S nB $end +$var wire 1 T nCmd2 $end +$var wire 1 U subtract $end $scope module mux0 $end -$var wire 1 d S $end -$var wire 1 [ in0 $end -$var wire 1 a in1 $end -$var wire 1 e nS $end -$var wire 1 f out0 $end -$var wire 1 g out1 $end -$var wire 1 \ outfinal $end +$var wire 1 V S $end +$var wire 1 M in0 $end +$var wire 1 S in1 $end +$var wire 1 W nS $end +$var wire 1 X out0 $end +$var wire 1 Y out1 $end +$var wire 1 N outfinal $end $upscope $end $upscope $end -$scope module setSLTres $end -$var wire 1 : S $end -$var wire 1 h in0 $end -$var wire 1 i in1 $end -$var wire 1 j nS $end -$var wire 1 k out0 $end -$var wire 1 l out1 $end -$var wire 1 m outfinal $end -$upscope $end $upscope $end $scope begin addbits[2] $end $scope module attempt $end -$var wire 1 n A $end -$var wire 1 o AandB $end -$var wire 1 p AddSubSLTSum $end -$var wire 1 q AxorB $end -$var wire 1 r B $end -$var wire 1 s BornB $end -$var wire 1 t CINandAxorB $end -$var wire 3 u Command [2:0] $end -$var wire 1 v carryin $end -$var wire 1 w carryout $end -$var wire 1 x nB $end -$var wire 1 y nCmd2 $end -$var wire 1 z subtract $end +$var wire 1 Z A $end +$var wire 1 [ AandB $end +$var wire 1 \ AddSubSLTSum $end +$var wire 1 ] AxorB $end +$var wire 1 ^ B $end +$var wire 1 _ BornB $end +$var wire 1 ` CINandAxorB $end +$var wire 3 a Command [2:0] $end +$var wire 1 b carryin $end +$var wire 1 c carryout $end +$var wire 1 d nB $end +$var wire 1 e nCmd2 $end +$var wire 1 f subtract $end $scope module mux0 $end -$var wire 1 { S $end -$var wire 1 r in0 $end -$var wire 1 x in1 $end -$var wire 1 | nS $end -$var wire 1 } out0 $end -$var wire 1 ~ out1 $end -$var wire 1 s outfinal $end -$upscope $end +$var wire 1 g S $end +$var wire 1 ^ in0 $end +$var wire 1 d in1 $end +$var wire 1 h nS $end +$var wire 1 i out0 $end +$var wire 1 j out1 $end +$var wire 1 _ outfinal $end $upscope $end -$scope module setSLTres $end -$var wire 1 : S $end -$var wire 1 !" in0 $end -$var wire 1 "" in1 $end -$var wire 1 #" nS $end -$var wire 1 $" out0 $end -$var wire 1 %" out1 $end -$var wire 1 &" outfinal $end $upscope $end $upscope $end $scope begin addbits[3] $end $scope module attempt $end -$var wire 1 '" A $end -$var wire 1 (" AandB $end -$var wire 1 )" AddSubSLTSum $end -$var wire 1 *" AxorB $end -$var wire 1 +" B $end -$var wire 1 ," BornB $end -$var wire 1 -" CINandAxorB $end -$var wire 3 ." Command [2:0] $end -$var wire 1 /" carryin $end -$var wire 1 0" carryout $end -$var wire 1 1" nB $end -$var wire 1 2" nCmd2 $end -$var wire 1 3" subtract $end +$var wire 1 k A $end +$var wire 1 l AandB $end +$var wire 1 m AddSubSLTSum $end +$var wire 1 n AxorB $end +$var wire 1 o B $end +$var wire 1 p BornB $end +$var wire 1 q CINandAxorB $end +$var wire 3 r Command [2:0] $end +$var wire 1 s carryin $end +$var wire 1 t carryout $end +$var wire 1 u nB $end +$var wire 1 v nCmd2 $end +$var wire 1 w subtract $end $scope module mux0 $end -$var wire 1 4" S $end -$var wire 1 +" in0 $end -$var wire 1 1" in1 $end -$var wire 1 5" nS $end -$var wire 1 6" out0 $end -$var wire 1 7" out1 $end -$var wire 1 ," outfinal $end +$var wire 1 x S $end +$var wire 1 o in0 $end +$var wire 1 u in1 $end +$var wire 1 y nS $end +$var wire 1 z out0 $end +$var wire 1 { out1 $end +$var wire 1 p outfinal $end $upscope $end $upscope $end -$scope module setSLTres $end -$var wire 1 : S $end -$var wire 1 8" in0 $end -$var wire 1 9" in1 $end -$var wire 1 :" nS $end -$var wire 1 ;" out0 $end -$var wire 1 <" out1 $end -$var wire 1 =" outfinal $end -$upscope $end $upscope $end $upscope $end -$scope module test $end -$var wire 4 >" A [3:0] $end -$var wire 4 ?" AddSubSLTSum [3:0] $end -$var wire 4 @" B [3:0] $end -$var wire 4 A" CarryoutWire [3:0] $end -$var wire 3 B" Command [2:0] $end -$var wire 4 C" NewVal [3:0] $end -$var wire 1 D" Res0OF1 $end -$var wire 1 E" Res1OF0 $end -$var wire 4 F" SLTSum [3:0] $end -$var wire 1 ' SLTflag $end -$var wire 1 G" SLTflag0 $end -$var wire 1 H" SLTflag1 $end -$var wire 1 I" SLTon $end -$var wire 4 J" carryin [3:0] $end -$var wire 1 ) carryout $end -$var wire 1 K" nAddSubSLTSum $end -$var wire 1 L" nCmd2 $end -$var wire 1 M" nOF $end -$var wire 1 * overflow $end -$var wire 4 N" subtract [3:0] $end +$scope module test2 $end +$var wire 4 | A [3:0] $end +$var wire 4 } AddSubSLTSum [3:0] $end +$var wire 4 ~ B [3:0] $end +$var wire 4 !" CarryoutWire [3:0] $end +$var wire 3 "" Command [2:0] $end +$var wire 4 #" NewVal [3:0] $end +$var wire 1 $" Res0OF1 $end +$var wire 1 %" Res1OF0 $end +$var wire 4 &" SLTSum [3:0] $end +$var wire 1 ( SLTflag $end +$var wire 1 '" SLTflag0 $end +$var wire 1 (" SLTflag1 $end +$var wire 1 )" SLTon $end +$var wire 4 *" carryin [3:0] $end +$var wire 1 * carryout $end +$var wire 1 +" nAddSubSLTSum $end +$var wire 1 ," nCmd2 $end +$var wire 1 -" nOF $end +$var wire 1 + overflow $end +$var wire 4 ." subtract [3:0] $end $scope module attempt2 $end -$var wire 1 O" A $end -$var wire 1 P" AandB $end -$var wire 1 Q" AddSubSLTSum $end -$var wire 1 R" AxorB $end -$var wire 1 S" B $end -$var wire 1 T" BornB $end -$var wire 1 U" CINandAxorB $end -$var wire 3 V" Command [2:0] $end -$var wire 1 W" carryin $end -$var wire 1 X" carryout $end -$var wire 1 Y" nB $end -$var wire 1 Z" nCmd2 $end -$var wire 1 [" subtract $end +$var wire 1 /" A $end +$var wire 1 0" AandB $end +$var wire 1 1" AddSubSLTSum $end +$var wire 1 2" AxorB $end +$var wire 1 3" B $end +$var wire 1 4" BornB $end +$var wire 1 5" CINandAxorB $end +$var wire 3 6" Command [2:0] $end +$var wire 1 7" carryin $end +$var wire 1 8" carryout $end +$var wire 1 9" nB $end +$var wire 1 :" nCmd2 $end +$var wire 1 ;" subtract $end $scope module mux0 $end -$var wire 1 \" S $end -$var wire 1 S" in0 $end -$var wire 1 Y" in1 $end -$var wire 1 ]" nS $end -$var wire 1 ^" out0 $end -$var wire 1 _" out1 $end -$var wire 1 T" outfinal $end +$var wire 1 <" S $end +$var wire 1 3" in0 $end +$var wire 1 9" in1 $end +$var wire 1 =" nS $end +$var wire 1 >" out0 $end +$var wire 1 ?" out1 $end +$var wire 1 4" outfinal $end $upscope $end $upscope $end -$scope module setSLTres $end -$var wire 1 I" S $end -$var wire 1 `" in0 $end -$var wire 1 a" in1 $end -$var wire 1 b" nS $end -$var wire 1 c" out0 $end -$var wire 1 d" out1 $end -$var wire 1 e" outfinal $end +$scope module setSLTresult $end +$var wire 1 )" S $end +$var wire 1 @" in0 $end +$var wire 1 A" in1 $end +$var wire 1 B" nS $end +$var wire 1 C" out0 $end +$var wire 1 D" out1 $end +$var wire 1 E" outfinal $end $upscope $end $scope module FinalSLT $end -$var wire 1 ' S $end -$var wire 1 f" in0 $end -$var wire 1 ' in1 $end -$var wire 1 g" nS $end -$var wire 1 h" out0 $end -$var wire 1 i" out1 $end -$var wire 1 j" outfinal $end +$var wire 1 ( S $end +$var wire 1 F" in0 $end +$var wire 1 ( in1 $end +$var wire 1 G" nS $end +$var wire 1 H" out0 $end +$var wire 1 I" out1 $end +$var wire 1 J" outfinal $end $upscope $end -$scope begin addbits[1] $end +$scope begin sltbits[1] $end $scope module attempt $end -$var wire 1 k" A $end -$var wire 1 l" AandB $end -$var wire 1 m" AddSubSLTSum $end -$var wire 1 n" AxorB $end -$var wire 1 o" B $end -$var wire 1 p" BornB $end -$var wire 1 q" CINandAxorB $end -$var wire 3 r" Command [2:0] $end -$var wire 1 s" carryin $end -$var wire 1 t" carryout $end -$var wire 1 u" nB $end -$var wire 1 v" nCmd2 $end -$var wire 1 w" subtract $end +$var wire 1 K" A $end +$var wire 1 L" AandB $end +$var wire 1 M" AddSubSLTSum $end +$var wire 1 N" AxorB $end +$var wire 1 O" B $end +$var wire 1 P" BornB $end +$var wire 1 Q" CINandAxorB $end +$var wire 3 R" Command [2:0] $end +$var wire 1 S" carryin $end +$var wire 1 T" carryout $end +$var wire 1 U" nB $end +$var wire 1 V" nCmd2 $end +$var wire 1 W" subtract $end $scope module mux0 $end -$var wire 1 x" S $end -$var wire 1 o" in0 $end -$var wire 1 u" in1 $end -$var wire 1 y" nS $end -$var wire 1 z" out0 $end -$var wire 1 {" out1 $end -$var wire 1 p" outfinal $end +$var wire 1 X" S $end +$var wire 1 O" in0 $end +$var wire 1 U" in1 $end +$var wire 1 Y" nS $end +$var wire 1 Z" out0 $end +$var wire 1 [" out1 $end +$var wire 1 P" outfinal $end $upscope $end $upscope $end $scope module setSLTres2 $end -$var wire 1 I" S $end -$var wire 1 |" in0 $end -$var wire 1 }" in1 $end -$var wire 1 ~" nS $end -$var wire 1 !# out0 $end -$var wire 1 "# out1 $end -$var wire 1 ## outfinal $end +$var wire 1 )" S $end +$var wire 1 \" in0 $end +$var wire 1 ]" in1 $end +$var wire 1 ^" nS $end +$var wire 1 _" out0 $end +$var wire 1 `" out1 $end +$var wire 1 a" outfinal $end $upscope $end $scope module setSLTres3 $end -$var wire 1 I" S $end -$var wire 1 $# in0 $end -$var wire 1 %# in1 $end -$var wire 1 &# nS $end -$var wire 1 '# out0 $end -$var wire 1 (# out1 $end -$var wire 1 )# outfinal $end +$var wire 1 )" S $end +$var wire 1 b" in0 $end +$var wire 1 c" in1 $end +$var wire 1 d" nS $end +$var wire 1 e" out0 $end +$var wire 1 f" out1 $end +$var wire 1 g" outfinal $end $upscope $end $upscope $end -$scope begin addbits[2] $end +$scope begin sltbits[2] $end $scope module attempt $end -$var wire 1 *# A $end -$var wire 1 +# AandB $end -$var wire 1 ,# AddSubSLTSum $end -$var wire 1 -# AxorB $end -$var wire 1 .# B $end -$var wire 1 /# BornB $end -$var wire 1 0# CINandAxorB $end -$var wire 3 1# Command [2:0] $end -$var wire 1 2# carryin $end -$var wire 1 3# carryout $end -$var wire 1 4# nB $end -$var wire 1 5# nCmd2 $end -$var wire 1 6# subtract $end +$var wire 1 h" A $end +$var wire 1 i" AandB $end +$var wire 1 j" AddSubSLTSum $end +$var wire 1 k" AxorB $end +$var wire 1 l" B $end +$var wire 1 m" BornB $end +$var wire 1 n" CINandAxorB $end +$var wire 3 o" Command [2:0] $end +$var wire 1 p" carryin $end +$var wire 1 q" carryout $end +$var wire 1 r" nB $end +$var wire 1 s" nCmd2 $end +$var wire 1 t" subtract $end $scope module mux0 $end -$var wire 1 7# S $end -$var wire 1 .# in0 $end -$var wire 1 4# in1 $end -$var wire 1 8# nS $end -$var wire 1 9# out0 $end -$var wire 1 :# out1 $end -$var wire 1 /# outfinal $end +$var wire 1 u" S $end +$var wire 1 l" in0 $end +$var wire 1 r" in1 $end +$var wire 1 v" nS $end +$var wire 1 w" out0 $end +$var wire 1 x" out1 $end +$var wire 1 m" outfinal $end $upscope $end $upscope $end $scope module setSLTres2 $end -$var wire 1 I" S $end -$var wire 1 ;# in0 $end -$var wire 1 <# in1 $end -$var wire 1 =# nS $end -$var wire 1 ># out0 $end -$var wire 1 ?# out1 $end -$var wire 1 @# outfinal $end +$var wire 1 )" S $end +$var wire 1 y" in0 $end +$var wire 1 z" in1 $end +$var wire 1 {" nS $end +$var wire 1 |" out0 $end +$var wire 1 }" out1 $end +$var wire 1 ~" outfinal $end $upscope $end $scope module setSLTres3 $end -$var wire 1 I" S $end -$var wire 1 A# in0 $end -$var wire 1 B# in1 $end -$var wire 1 C# nS $end -$var wire 1 D# out0 $end -$var wire 1 E# out1 $end -$var wire 1 F# outfinal $end +$var wire 1 )" S $end +$var wire 1 !# in0 $end +$var wire 1 "# in1 $end +$var wire 1 ## nS $end +$var wire 1 $# out0 $end +$var wire 1 %# out1 $end +$var wire 1 &# outfinal $end $upscope $end $upscope $end -$scope begin addbits[3] $end +$scope begin sltbits[3] $end $scope module attempt $end -$var wire 1 G# A $end -$var wire 1 H# AandB $end -$var wire 1 I# AddSubSLTSum $end -$var wire 1 J# AxorB $end -$var wire 1 K# B $end -$var wire 1 L# BornB $end -$var wire 1 M# CINandAxorB $end -$var wire 3 N# Command [2:0] $end -$var wire 1 O# carryin $end -$var wire 1 P# carryout $end -$var wire 1 Q# nB $end -$var wire 1 R# nCmd2 $end -$var wire 1 S# subtract $end +$var wire 1 '# A $end +$var wire 1 (# AandB $end +$var wire 1 )# AddSubSLTSum $end +$var wire 1 *# AxorB $end +$var wire 1 +# B $end +$var wire 1 ,# BornB $end +$var wire 1 -# CINandAxorB $end +$var wire 3 .# Command [2:0] $end +$var wire 1 /# carryin $end +$var wire 1 0# carryout $end +$var wire 1 1# nB $end +$var wire 1 2# nCmd2 $end +$var wire 1 3# subtract $end $scope module mux0 $end -$var wire 1 T# S $end -$var wire 1 K# in0 $end -$var wire 1 Q# in1 $end -$var wire 1 U# nS $end -$var wire 1 V# out0 $end -$var wire 1 W# out1 $end -$var wire 1 L# outfinal $end +$var wire 1 4# S $end +$var wire 1 +# in0 $end +$var wire 1 1# in1 $end +$var wire 1 5# nS $end +$var wire 1 6# out0 $end +$var wire 1 7# out1 $end +$var wire 1 ,# outfinal $end $upscope $end $upscope $end $scope module setSLTres2 $end -$var wire 1 I" S $end -$var wire 1 X# in0 $end -$var wire 1 Y# in1 $end -$var wire 1 Z# nS $end -$var wire 1 [# out0 $end -$var wire 1 \# out1 $end -$var wire 1 ]# outfinal $end +$var wire 1 )" S $end +$var wire 1 8# in0 $end +$var wire 1 9# in1 $end +$var wire 1 :# nS $end +$var wire 1 ;# out0 $end +$var wire 1 <# out1 $end +$var wire 1 =# outfinal $end $upscope $end $scope module setSLTres3 $end -$var wire 1 I" S $end -$var wire 1 ^# in0 $end -$var wire 1 _# in1 $end -$var wire 1 `# nS $end -$var wire 1 a# out0 $end -$var wire 1 b# out1 $end -$var wire 1 c# outfinal $end +$var wire 1 )" S $end +$var wire 1 ># in0 $end +$var wire 1 ?# in1 $end +$var wire 1 @# nS $end +$var wire 1 A# out0 $end +$var wire 1 B# out1 $end +$var wire 1 C# outfinal $end $upscope $end $upscope $end $upscope $end $scope module trial1 $end -$var wire 4 d# A [3:0] $end -$var wire 4 e# AndNandOut [3:0] $end -$var wire 4 f# B [3:0] $end -$var wire 3 g# Command [2:0] $end +$var wire 4 D# A [3:0] $end +$var wire 4 E# AndNandOut [3:0] $end +$var wire 4 F# B [3:0] $end +$var wire 3 G# Command [2:0] $end $scope module attempt2 $end -$var wire 1 h# A $end -$var wire 1 i# AandB $end -$var wire 1 j# AnandB $end -$var wire 1 k# AndNandOut $end -$var wire 1 l# B $end -$var wire 3 m# Command [2:0] $end +$var wire 1 H# A $end +$var wire 1 I# AandB $end +$var wire 1 J# AnandB $end +$var wire 1 K# AndNandOut $end +$var wire 1 L# B $end +$var wire 3 M# Command [2:0] $end $scope module potato $end -$var wire 1 n# S $end -$var wire 1 i# in0 $end -$var wire 1 j# in1 $end -$var wire 1 o# nS $end -$var wire 1 p# out0 $end -$var wire 1 q# out1 $end -$var wire 1 k# outfinal $end +$var wire 1 N# S $end +$var wire 1 I# in0 $end +$var wire 1 J# in1 $end +$var wire 1 O# nS $end +$var wire 1 P# out0 $end +$var wire 1 Q# out1 $end +$var wire 1 K# outfinal $end $upscope $end $upscope $end $scope begin andbits[1] $end $scope module attempt $end -$var wire 1 r# A $end -$var wire 1 s# AandB $end -$var wire 1 t# AnandB $end -$var wire 1 u# AndNandOut $end -$var wire 1 v# B $end -$var wire 3 w# Command [2:0] $end +$var wire 1 R# A $end +$var wire 1 S# AandB $end +$var wire 1 T# AnandB $end +$var wire 1 U# AndNandOut $end +$var wire 1 V# B $end +$var wire 3 W# Command [2:0] $end $scope module potato $end -$var wire 1 x# S $end -$var wire 1 s# in0 $end -$var wire 1 t# in1 $end -$var wire 1 y# nS $end -$var wire 1 z# out0 $end -$var wire 1 {# out1 $end -$var wire 1 u# outfinal $end +$var wire 1 X# S $end +$var wire 1 S# in0 $end +$var wire 1 T# in1 $end +$var wire 1 Y# nS $end +$var wire 1 Z# out0 $end +$var wire 1 [# out1 $end +$var wire 1 U# outfinal $end $upscope $end $upscope $end $upscope $end $scope begin andbits[2] $end $scope module attempt $end -$var wire 1 |# A $end -$var wire 1 }# AandB $end -$var wire 1 ~# AnandB $end -$var wire 1 !$ AndNandOut $end -$var wire 1 "$ B $end -$var wire 3 #$ Command [2:0] $end +$var wire 1 \# A $end +$var wire 1 ]# AandB $end +$var wire 1 ^# AnandB $end +$var wire 1 _# AndNandOut $end +$var wire 1 `# B $end +$var wire 3 a# Command [2:0] $end $scope module potato $end -$var wire 1 $$ S $end -$var wire 1 }# in0 $end -$var wire 1 ~# in1 $end -$var wire 1 %$ nS $end -$var wire 1 &$ out0 $end -$var wire 1 '$ out1 $end -$var wire 1 !$ outfinal $end +$var wire 1 b# S $end +$var wire 1 ]# in0 $end +$var wire 1 ^# in1 $end +$var wire 1 c# nS $end +$var wire 1 d# out0 $end +$var wire 1 e# out1 $end +$var wire 1 _# outfinal $end $upscope $end $upscope $end $upscope $end $scope begin andbits[3] $end $scope module attempt $end -$var wire 1 ($ A $end -$var wire 1 )$ AandB $end -$var wire 1 *$ AnandB $end -$var wire 1 +$ AndNandOut $end -$var wire 1 ,$ B $end -$var wire 3 -$ Command [2:0] $end +$var wire 1 f# A $end +$var wire 1 g# AandB $end +$var wire 1 h# AnandB $end +$var wire 1 i# AndNandOut $end +$var wire 1 j# B $end +$var wire 3 k# Command [2:0] $end $scope module potato $end -$var wire 1 .$ S $end -$var wire 1 )$ in0 $end -$var wire 1 *$ in1 $end -$var wire 1 /$ nS $end -$var wire 1 0$ out0 $end -$var wire 1 1$ out1 $end -$var wire 1 +$ outfinal $end +$var wire 1 l# S $end +$var wire 1 g# in0 $end +$var wire 1 h# in1 $end +$var wire 1 m# nS $end +$var wire 1 n# out0 $end +$var wire 1 o# out1 $end +$var wire 1 i# outfinal $end $upscope $end $upscope $end $upscope $end $upscope $end $scope module trial2 $end -$var wire 4 2$ A [3:0] $end -$var wire 4 3$ B [3:0] $end -$var wire 3 4$ Command [2:0] $end -$var wire 4 5$ OrNorXorOut [3:0] $end +$var wire 4 p# A [3:0] $end +$var wire 4 q# B [3:0] $end +$var wire 3 r# Command [2:0] $end +$var wire 4 s# OrNorXorOut [3:0] $end $scope module attempt2 $end -$var wire 1 6$ A $end -$var wire 1 7$ AnandB $end -$var wire 1 8$ AnorB $end -$var wire 1 9$ AorB $end -$var wire 1 :$ AxorB $end -$var wire 1 ;$ B $end -$var wire 3 <$ Command [2:0] $end -$var wire 1 =$ OrNorXorOut $end -$var wire 1 >$ XorNor $end -$var wire 1 ?$ nXor $end +$var wire 1 t# A $end +$var wire 1 u# AnandB $end +$var wire 1 v# AnorB $end +$var wire 1 w# AorB $end +$var wire 1 x# AxorB $end +$var wire 1 y# B $end +$var wire 3 z# Command [2:0] $end +$var wire 1 {# OrNorXorOut $end +$var wire 1 |# XorNor $end +$var wire 1 }# nXor $end $scope module mux0 $end -$var wire 1 @$ S $end -$var wire 1 :$ in0 $end -$var wire 1 8$ in1 $end -$var wire 1 A$ nS $end -$var wire 1 B$ out0 $end -$var wire 1 C$ out1 $end -$var wire 1 >$ outfinal $end +$var wire 1 ~# S $end +$var wire 1 x# in0 $end +$var wire 1 v# in1 $end +$var wire 1 !$ nS $end +$var wire 1 "$ out0 $end +$var wire 1 #$ out1 $end +$var wire 1 |# outfinal $end $upscope $end $scope module mux1 $end -$var wire 1 D$ S $end -$var wire 1 >$ in0 $end -$var wire 1 9$ in1 $end -$var wire 1 E$ nS $end -$var wire 1 F$ out0 $end -$var wire 1 G$ out1 $end -$var wire 1 =$ outfinal $end +$var wire 1 $$ S $end +$var wire 1 |# in0 $end +$var wire 1 w# in1 $end +$var wire 1 %$ nS $end +$var wire 1 &$ out0 $end +$var wire 1 '$ out1 $end +$var wire 1 {# outfinal $end $upscope $end $upscope $end $scope begin orbits[1] $end $scope module attempt $end -$var wire 1 H$ A $end -$var wire 1 I$ AnandB $end -$var wire 1 J$ AnorB $end -$var wire 1 K$ AorB $end -$var wire 1 L$ AxorB $end -$var wire 1 M$ B $end -$var wire 3 N$ Command [2:0] $end -$var wire 1 O$ OrNorXorOut $end -$var wire 1 P$ XorNor $end -$var wire 1 Q$ nXor $end +$var wire 1 ($ A $end +$var wire 1 )$ AnandB $end +$var wire 1 *$ AnorB $end +$var wire 1 +$ AorB $end +$var wire 1 ,$ AxorB $end +$var wire 1 -$ B $end +$var wire 3 .$ Command [2:0] $end +$var wire 1 /$ OrNorXorOut $end +$var wire 1 0$ XorNor $end +$var wire 1 1$ nXor $end $scope module mux0 $end -$var wire 1 R$ S $end -$var wire 1 L$ in0 $end -$var wire 1 J$ in1 $end -$var wire 1 S$ nS $end -$var wire 1 T$ out0 $end -$var wire 1 U$ out1 $end -$var wire 1 P$ outfinal $end +$var wire 1 2$ S $end +$var wire 1 ,$ in0 $end +$var wire 1 *$ in1 $end +$var wire 1 3$ nS $end +$var wire 1 4$ out0 $end +$var wire 1 5$ out1 $end +$var wire 1 0$ outfinal $end $upscope $end $scope module mux1 $end -$var wire 1 V$ S $end -$var wire 1 P$ in0 $end -$var wire 1 K$ in1 $end -$var wire 1 W$ nS $end -$var wire 1 X$ out0 $end -$var wire 1 Y$ out1 $end -$var wire 1 O$ outfinal $end +$var wire 1 6$ S $end +$var wire 1 0$ in0 $end +$var wire 1 +$ in1 $end +$var wire 1 7$ nS $end +$var wire 1 8$ out0 $end +$var wire 1 9$ out1 $end +$var wire 1 /$ outfinal $end $upscope $end $upscope $end $upscope $end $scope begin orbits[2] $end $scope module attempt $end -$var wire 1 Z$ A $end -$var wire 1 [$ AnandB $end -$var wire 1 \$ AnorB $end -$var wire 1 ]$ AorB $end -$var wire 1 ^$ AxorB $end -$var wire 1 _$ B $end -$var wire 3 `$ Command [2:0] $end -$var wire 1 a$ OrNorXorOut $end -$var wire 1 b$ XorNor $end -$var wire 1 c$ nXor $end +$var wire 1 :$ A $end +$var wire 1 ;$ AnandB $end +$var wire 1 <$ AnorB $end +$var wire 1 =$ AorB $end +$var wire 1 >$ AxorB $end +$var wire 1 ?$ B $end +$var wire 3 @$ Command [2:0] $end +$var wire 1 A$ OrNorXorOut $end +$var wire 1 B$ XorNor $end +$var wire 1 C$ nXor $end $scope module mux0 $end -$var wire 1 d$ S $end -$var wire 1 ^$ in0 $end -$var wire 1 \$ in1 $end -$var wire 1 e$ nS $end -$var wire 1 f$ out0 $end -$var wire 1 g$ out1 $end -$var wire 1 b$ outfinal $end +$var wire 1 D$ S $end +$var wire 1 >$ in0 $end +$var wire 1 <$ in1 $end +$var wire 1 E$ nS $end +$var wire 1 F$ out0 $end +$var wire 1 G$ out1 $end +$var wire 1 B$ outfinal $end $upscope $end $scope module mux1 $end -$var wire 1 h$ S $end -$var wire 1 b$ in0 $end -$var wire 1 ]$ in1 $end -$var wire 1 i$ nS $end -$var wire 1 j$ out0 $end -$var wire 1 k$ out1 $end -$var wire 1 a$ outfinal $end +$var wire 1 H$ S $end +$var wire 1 B$ in0 $end +$var wire 1 =$ in1 $end +$var wire 1 I$ nS $end +$var wire 1 J$ out0 $end +$var wire 1 K$ out1 $end +$var wire 1 A$ outfinal $end $upscope $end $upscope $end $upscope $end $scope begin orbits[3] $end $scope module attempt $end -$var wire 1 l$ A $end -$var wire 1 m$ AnandB $end -$var wire 1 n$ AnorB $end -$var wire 1 o$ AorB $end -$var wire 1 p$ AxorB $end -$var wire 1 q$ B $end -$var wire 3 r$ Command [2:0] $end -$var wire 1 s$ OrNorXorOut $end -$var wire 1 t$ XorNor $end -$var wire 1 u$ nXor $end +$var wire 1 L$ A $end +$var wire 1 M$ AnandB $end +$var wire 1 N$ AnorB $end +$var wire 1 O$ AorB $end +$var wire 1 P$ AxorB $end +$var wire 1 Q$ B $end +$var wire 3 R$ Command [2:0] $end +$var wire 1 S$ OrNorXorOut $end +$var wire 1 T$ XorNor $end +$var wire 1 U$ nXor $end $scope module mux0 $end -$var wire 1 v$ S $end -$var wire 1 p$ in0 $end -$var wire 1 n$ in1 $end -$var wire 1 w$ nS $end -$var wire 1 x$ out0 $end -$var wire 1 y$ out1 $end -$var wire 1 t$ outfinal $end +$var wire 1 V$ S $end +$var wire 1 P$ in0 $end +$var wire 1 N$ in1 $end +$var wire 1 W$ nS $end +$var wire 1 X$ out0 $end +$var wire 1 Y$ out1 $end +$var wire 1 T$ outfinal $end $upscope $end $scope module mux1 $end -$var wire 1 z$ S $end -$var wire 1 t$ in0 $end -$var wire 1 o$ in1 $end -$var wire 1 {$ nS $end -$var wire 1 |$ out0 $end -$var wire 1 }$ out1 $end -$var wire 1 s$ outfinal $end +$var wire 1 Z$ S $end +$var wire 1 T$ in0 $end +$var wire 1 O$ in1 $end +$var wire 1 [$ nS $end +$var wire 1 \$ out0 $end +$var wire 1 ]$ out1 $end +$var wire 1 S$ outfinal $end $upscope $end $upscope $end $upscope $end $upscope $end $scope module superalu $end -$var wire 4 ~$ A [3:0] $end -$var wire 4 !% AddSubSLTSum [3:0] $end +$var wire 4 ^$ A [3:0] $end +$var wire 4 _$ AddSubSLTSum [3:0] $end $var wire 1 " AllZeros $end -$var wire 4 "% AndNandOut [3:0] $end -$var wire 4 #% B [3:0] $end -$var wire 4 $% Cmd0Start [3:0] $end -$var wire 4 %% Cmd1Start [3:0] $end -$var wire 3 &% Command [2:0] $end -$var wire 4 '% OneBitFinalOut [3:0] $end -$var wire 4 (% OrNorXorOut [3:0] $end -$var wire 4 )% SLTSum [3:0] $end +$var wire 4 `$ AndNandOut [3:0] $end +$var wire 4 a$ B [3:0] $end +$var wire 4 b$ Cmd0Start [3:0] $end +$var wire 4 c$ Cmd1Start [3:0] $end +$var wire 3 d$ Command [2:0] $end +$var wire 4 e$ OneBitFinalOut [3:0] $end +$var wire 4 f$ OrNorXorOut [3:0] $end +$var wire 4 g$ SLTSum [3:0] $end $var wire 1 ' SLTflag $end -$var wire 4 *% ZeroFlag [3:0] $end -$var wire 4 +% carryin [3:0] $end -$var wire 1 ) carryout $end -$var wire 1 * overflow $end -$var wire 4 ,% subtract [3:0] $end -$var wire 1 -% yeszero $end +$var wire 4 h$ ZeroFlag [3:0] $end +$var wire 4 i$ carryin [3:0] $end +$var wire 1 * carryout $end +$var wire 1 + overflow $end +$var wire 4 j$ subtract [3:0] $end +$var wire 1 k$ yeszero $end $scope module test $end -$var wire 4 .% A [3:0] $end -$var wire 4 /% AddSubSLTSum [3:0] $end -$var wire 4 0% B [3:0] $end -$var wire 4 1% CarryoutWire [3:0] $end -$var wire 3 2% Command [2:0] $end -$var wire 4 3% NewVal [3:0] $end -$var wire 1 4% Res0OF1 $end -$var wire 1 5% Res1OF0 $end -$var wire 4 6% SLTSum [3:0] $end +$var wire 4 l$ A [3:0] $end +$var wire 4 m$ AddSubSLTSum [3:0] $end +$var wire 4 n$ B [3:0] $end +$var wire 4 o$ CarryoutWire [3:0] $end +$var wire 3 p$ Command [2:0] $end +$var wire 4 q$ NewVal [3:0] $end +$var wire 1 r$ Res0OF1 $end +$var wire 1 s$ Res1OF0 $end +$var wire 4 t$ SLTSum [3:0] $end $var wire 1 ' SLTflag $end -$var wire 1 7% SLTflag0 $end -$var wire 1 8% SLTflag1 $end -$var wire 1 9% SLTon $end -$var wire 4 :% carryin [3:0] $end -$var wire 1 ) carryout $end -$var wire 1 ;% nAddSubSLTSum $end -$var wire 1 <% nCmd2 $end -$var wire 1 =% nOF $end -$var wire 1 * overflow $end -$var wire 4 >% subtract [3:0] $end +$var wire 1 u$ SLTflag0 $end +$var wire 1 v$ SLTflag1 $end +$var wire 1 w$ SLTon $end +$var wire 4 x$ carryin [3:0] $end +$var wire 1 * carryout $end +$var wire 1 y$ nAddSubSLTSum $end +$var wire 1 z$ nCmd2 $end +$var wire 1 {$ nOF $end +$var wire 1 + overflow $end +$var wire 4 |$ subtract [3:0] $end $scope module attempt2 $end -$var wire 1 ?% A $end -$var wire 1 @% AandB $end -$var wire 1 A% AddSubSLTSum $end -$var wire 1 B% AxorB $end -$var wire 1 C% B $end -$var wire 1 D% BornB $end -$var wire 1 E% CINandAxorB $end -$var wire 3 F% Command [2:0] $end -$var wire 1 G% carryin $end -$var wire 1 H% carryout $end -$var wire 1 I% nB $end -$var wire 1 J% nCmd2 $end -$var wire 1 K% subtract $end +$var wire 1 }$ A $end +$var wire 1 ~$ AandB $end +$var wire 1 !% AddSubSLTSum $end +$var wire 1 "% AxorB $end +$var wire 1 #% B $end +$var wire 1 $% BornB $end +$var wire 1 %% CINandAxorB $end +$var wire 3 &% Command [2:0] $end +$var wire 1 '% carryin $end +$var wire 1 (% carryout $end +$var wire 1 )% nB $end +$var wire 1 *% nCmd2 $end +$var wire 1 +% subtract $end $scope module mux0 $end -$var wire 1 L% S $end -$var wire 1 C% in0 $end -$var wire 1 I% in1 $end -$var wire 1 M% nS $end -$var wire 1 N% out0 $end -$var wire 1 O% out1 $end -$var wire 1 D% outfinal $end +$var wire 1 ,% S $end +$var wire 1 #% in0 $end +$var wire 1 )% in1 $end +$var wire 1 -% nS $end +$var wire 1 .% out0 $end +$var wire 1 /% out1 $end +$var wire 1 $% outfinal $end $upscope $end $upscope $end -$scope module setSLTres $end -$var wire 1 9% S $end -$var wire 1 P% in0 $end -$var wire 1 Q% in1 $end -$var wire 1 R% nS $end -$var wire 1 S% out0 $end -$var wire 1 T% out1 $end -$var wire 1 U% outfinal $end +$scope module setSLTresult $end +$var wire 1 w$ S $end +$var wire 1 0% in0 $end +$var wire 1 1% in1 $end +$var wire 1 2% nS $end +$var wire 1 3% out0 $end +$var wire 1 4% out1 $end +$var wire 1 5% outfinal $end $upscope $end $scope module FinalSLT $end $var wire 1 ' S $end -$var wire 1 V% in0 $end +$var wire 1 6% in0 $end $var wire 1 ' in1 $end -$var wire 1 W% nS $end -$var wire 1 X% out0 $end -$var wire 1 Y% out1 $end -$var wire 1 Z% outfinal $end +$var wire 1 7% nS $end +$var wire 1 8% out0 $end +$var wire 1 9% out1 $end +$var wire 1 :% outfinal $end $upscope $end -$scope begin addbits[1] $end +$scope begin sltbits[1] $end $scope module attempt $end -$var wire 1 [% A $end -$var wire 1 \% AandB $end -$var wire 1 ]% AddSubSLTSum $end -$var wire 1 ^% AxorB $end -$var wire 1 _% B $end -$var wire 1 `% BornB $end -$var wire 1 a% CINandAxorB $end -$var wire 3 b% Command [2:0] $end -$var wire 1 c% carryin $end -$var wire 1 d% carryout $end -$var wire 1 e% nB $end -$var wire 1 f% nCmd2 $end -$var wire 1 g% subtract $end +$var wire 1 ;% A $end +$var wire 1 <% AandB $end +$var wire 1 =% AddSubSLTSum $end +$var wire 1 >% AxorB $end +$var wire 1 ?% B $end +$var wire 1 @% BornB $end +$var wire 1 A% CINandAxorB $end +$var wire 3 B% Command [2:0] $end +$var wire 1 C% carryin $end +$var wire 1 D% carryout $end +$var wire 1 E% nB $end +$var wire 1 F% nCmd2 $end +$var wire 1 G% subtract $end $scope module mux0 $end -$var wire 1 h% S $end -$var wire 1 _% in0 $end -$var wire 1 e% in1 $end -$var wire 1 i% nS $end -$var wire 1 j% out0 $end -$var wire 1 k% out1 $end -$var wire 1 `% outfinal $end +$var wire 1 H% S $end +$var wire 1 ?% in0 $end +$var wire 1 E% in1 $end +$var wire 1 I% nS $end +$var wire 1 J% out0 $end +$var wire 1 K% out1 $end +$var wire 1 @% outfinal $end $upscope $end $upscope $end $scope module setSLTres2 $end -$var wire 1 9% S $end -$var wire 1 l% in0 $end -$var wire 1 m% in1 $end -$var wire 1 n% nS $end -$var wire 1 o% out0 $end -$var wire 1 p% out1 $end -$var wire 1 q% outfinal $end +$var wire 1 w$ S $end +$var wire 1 L% in0 $end +$var wire 1 M% in1 $end +$var wire 1 N% nS $end +$var wire 1 O% out0 $end +$var wire 1 P% out1 $end +$var wire 1 Q% outfinal $end $upscope $end $scope module setSLTres3 $end -$var wire 1 9% S $end -$var wire 1 r% in0 $end -$var wire 1 s% in1 $end -$var wire 1 t% nS $end -$var wire 1 u% out0 $end -$var wire 1 v% out1 $end -$var wire 1 w% outfinal $end +$var wire 1 w$ S $end +$var wire 1 R% in0 $end +$var wire 1 S% in1 $end +$var wire 1 T% nS $end +$var wire 1 U% out0 $end +$var wire 1 V% out1 $end +$var wire 1 W% outfinal $end $upscope $end $upscope $end -$scope begin addbits[2] $end +$scope begin sltbits[2] $end $scope module attempt $end -$var wire 1 x% A $end -$var wire 1 y% AandB $end -$var wire 1 z% AddSubSLTSum $end -$var wire 1 {% AxorB $end -$var wire 1 |% B $end -$var wire 1 }% BornB $end -$var wire 1 ~% CINandAxorB $end -$var wire 3 !& Command [2:0] $end -$var wire 1 "& carryin $end -$var wire 1 #& carryout $end -$var wire 1 $& nB $end -$var wire 1 %& nCmd2 $end -$var wire 1 && subtract $end +$var wire 1 X% A $end +$var wire 1 Y% AandB $end +$var wire 1 Z% AddSubSLTSum $end +$var wire 1 [% AxorB $end +$var wire 1 \% B $end +$var wire 1 ]% BornB $end +$var wire 1 ^% CINandAxorB $end +$var wire 3 _% Command [2:0] $end +$var wire 1 `% carryin $end +$var wire 1 a% carryout $end +$var wire 1 b% nB $end +$var wire 1 c% nCmd2 $end +$var wire 1 d% subtract $end $scope module mux0 $end -$var wire 1 '& S $end -$var wire 1 |% in0 $end -$var wire 1 $& in1 $end -$var wire 1 (& nS $end -$var wire 1 )& out0 $end -$var wire 1 *& out1 $end -$var wire 1 }% outfinal $end +$var wire 1 e% S $end +$var wire 1 \% in0 $end +$var wire 1 b% in1 $end +$var wire 1 f% nS $end +$var wire 1 g% out0 $end +$var wire 1 h% out1 $end +$var wire 1 ]% outfinal $end $upscope $end $upscope $end $scope module setSLTres2 $end -$var wire 1 9% S $end -$var wire 1 +& in0 $end -$var wire 1 ,& in1 $end -$var wire 1 -& nS $end -$var wire 1 .& out0 $end -$var wire 1 /& out1 $end -$var wire 1 0& outfinal $end +$var wire 1 w$ S $end +$var wire 1 i% in0 $end +$var wire 1 j% in1 $end +$var wire 1 k% nS $end +$var wire 1 l% out0 $end +$var wire 1 m% out1 $end +$var wire 1 n% outfinal $end $upscope $end $scope module setSLTres3 $end -$var wire 1 9% S $end -$var wire 1 1& in0 $end -$var wire 1 2& in1 $end -$var wire 1 3& nS $end -$var wire 1 4& out0 $end -$var wire 1 5& out1 $end -$var wire 1 6& outfinal $end +$var wire 1 w$ S $end +$var wire 1 o% in0 $end +$var wire 1 p% in1 $end +$var wire 1 q% nS $end +$var wire 1 r% out0 $end +$var wire 1 s% out1 $end +$var wire 1 t% outfinal $end $upscope $end $upscope $end -$scope begin addbits[3] $end +$scope begin sltbits[3] $end $scope module attempt $end -$var wire 1 7& A $end -$var wire 1 8& AandB $end -$var wire 1 9& AddSubSLTSum $end -$var wire 1 :& AxorB $end -$var wire 1 ;& B $end -$var wire 1 <& BornB $end -$var wire 1 =& CINandAxorB $end -$var wire 3 >& Command [2:0] $end -$var wire 1 ?& carryin $end -$var wire 1 @& carryout $end -$var wire 1 A& nB $end -$var wire 1 B& nCmd2 $end -$var wire 1 C& subtract $end +$var wire 1 u% A $end +$var wire 1 v% AandB $end +$var wire 1 w% AddSubSLTSum $end +$var wire 1 x% AxorB $end +$var wire 1 y% B $end +$var wire 1 z% BornB $end +$var wire 1 {% CINandAxorB $end +$var wire 3 |% Command [2:0] $end +$var wire 1 }% carryin $end +$var wire 1 ~% carryout $end +$var wire 1 !& nB $end +$var wire 1 "& nCmd2 $end +$var wire 1 #& subtract $end $scope module mux0 $end -$var wire 1 D& S $end -$var wire 1 ;& in0 $end -$var wire 1 A& in1 $end -$var wire 1 E& nS $end -$var wire 1 F& out0 $end -$var wire 1 G& out1 $end -$var wire 1 <& outfinal $end +$var wire 1 $& S $end +$var wire 1 y% in0 $end +$var wire 1 !& in1 $end +$var wire 1 %& nS $end +$var wire 1 && out0 $end +$var wire 1 '& out1 $end +$var wire 1 z% outfinal $end $upscope $end $upscope $end $scope module setSLTres2 $end -$var wire 1 9% S $end -$var wire 1 H& in0 $end -$var wire 1 I& in1 $end -$var wire 1 J& nS $end -$var wire 1 K& out0 $end -$var wire 1 L& out1 $end -$var wire 1 M& outfinal $end +$var wire 1 w$ S $end +$var wire 1 (& in0 $end +$var wire 1 )& in1 $end +$var wire 1 *& nS $end +$var wire 1 +& out0 $end +$var wire 1 ,& out1 $end +$var wire 1 -& outfinal $end $upscope $end $scope module setSLTres3 $end -$var wire 1 9% S $end -$var wire 1 N& in0 $end -$var wire 1 O& in1 $end -$var wire 1 P& nS $end -$var wire 1 Q& out0 $end -$var wire 1 R& out1 $end -$var wire 1 S& outfinal $end +$var wire 1 w$ S $end +$var wire 1 .& in0 $end +$var wire 1 /& in1 $end +$var wire 1 0& nS $end +$var wire 1 1& out0 $end +$var wire 1 2& out1 $end +$var wire 1 3& outfinal $end $upscope $end $upscope $end $upscope $end $scope module trial $end -$var wire 4 T& A [3:0] $end -$var wire 4 U& AddSubSLTSum [3:0] $end -$var wire 4 V& B [3:0] $end -$var wire 4 W& CarryoutWire [3:0] $end -$var wire 3 X& Command [2:0] $end -$var wire 4 Y& NewVal [3:0] $end -$var wire 1 Z& Res0OF1 $end -$var wire 1 [& Res1OF0 $end -$var wire 1 ' SLTflag $end -$var wire 1 \& SLTflag0 $end -$var wire 1 ]& SLTflag1 $end -$var wire 1 ^& SLTon $end -$var wire 4 _& carryin [3:0] $end -$var wire 1 ) carryout $end -$var wire 1 `& nAddSubSLTSum $end -$var wire 1 a& nCmd2 $end -$var wire 1 b& nOF $end -$var wire 1 * overflow $end -$var wire 4 c& subtract [3:0] $end +$var wire 4 4& A [3:0] $end +$var wire 4 5& AddSubSLTSum [3:0] $end +$var wire 4 6& B [3:0] $end +$var wire 4 7& CarryoutWire [3:0] $end +$var wire 3 8& Command [2:0] $end +$var wire 4 9& carryin [3:0] $end +$var wire 1 * carryout $end +$var wire 1 + overflow $end +$var wire 4 :& subtract [3:0] $end $scope module attempt2 $end -$var wire 1 d& A $end -$var wire 1 e& AandB $end -$var wire 1 f& AddSubSLTSum $end -$var wire 1 g& AxorB $end -$var wire 1 h& B $end -$var wire 1 i& BornB $end -$var wire 1 j& CINandAxorB $end -$var wire 3 k& Command [2:0] $end -$var wire 1 l& carryin $end -$var wire 1 m& carryout $end -$var wire 1 n& nB $end -$var wire 1 o& nCmd2 $end -$var wire 1 p& subtract $end +$var wire 1 ;& A $end +$var wire 1 <& AandB $end +$var wire 1 =& AddSubSLTSum $end +$var wire 1 >& AxorB $end +$var wire 1 ?& B $end +$var wire 1 @& BornB $end +$var wire 1 A& CINandAxorB $end +$var wire 3 B& Command [2:0] $end +$var wire 1 C& carryin $end +$var wire 1 D& carryout $end +$var wire 1 E& nB $end +$var wire 1 F& nCmd2 $end +$var wire 1 G& subtract $end $scope module mux0 $end -$var wire 1 q& S $end -$var wire 1 h& in0 $end -$var wire 1 n& in1 $end -$var wire 1 r& nS $end -$var wire 1 s& out0 $end -$var wire 1 t& out1 $end -$var wire 1 i& outfinal $end +$var wire 1 H& S $end +$var wire 1 ?& in0 $end +$var wire 1 E& in1 $end +$var wire 1 I& nS $end +$var wire 1 J& out0 $end +$var wire 1 K& out1 $end +$var wire 1 @& outfinal $end $upscope $end $upscope $end -$scope module setSLTres $end -$var wire 1 ^& S $end -$var wire 1 u& in0 $end -$var wire 1 v& in1 $end -$var wire 1 w& nS $end -$var wire 1 x& out0 $end -$var wire 1 y& out1 $end -$var wire 1 z& outfinal $end -$upscope $end $scope begin addbits[1] $end $scope module attempt $end -$var wire 1 {& A $end -$var wire 1 |& AandB $end -$var wire 1 }& AddSubSLTSum $end -$var wire 1 ~& AxorB $end -$var wire 1 !' B $end -$var wire 1 "' BornB $end -$var wire 1 #' CINandAxorB $end -$var wire 3 $' Command [2:0] $end -$var wire 1 %' carryin $end -$var wire 1 &' carryout $end -$var wire 1 '' nB $end -$var wire 1 (' nCmd2 $end -$var wire 1 )' subtract $end +$var wire 1 L& A $end +$var wire 1 M& AandB $end +$var wire 1 N& AddSubSLTSum $end +$var wire 1 O& AxorB $end +$var wire 1 P& B $end +$var wire 1 Q& BornB $end +$var wire 1 R& CINandAxorB $end +$var wire 3 S& Command [2:0] $end +$var wire 1 T& carryin $end +$var wire 1 U& carryout $end +$var wire 1 V& nB $end +$var wire 1 W& nCmd2 $end +$var wire 1 X& subtract $end $scope module mux0 $end -$var wire 1 *' S $end -$var wire 1 !' in0 $end -$var wire 1 '' in1 $end -$var wire 1 +' nS $end -$var wire 1 ,' out0 $end -$var wire 1 -' out1 $end -$var wire 1 "' outfinal $end -$upscope $end +$var wire 1 Y& S $end +$var wire 1 P& in0 $end +$var wire 1 V& in1 $end +$var wire 1 Z& nS $end +$var wire 1 [& out0 $end +$var wire 1 \& out1 $end +$var wire 1 Q& outfinal $end $upscope $end -$scope module setSLTres $end -$var wire 1 ^& S $end -$var wire 1 .' in0 $end -$var wire 1 /' in1 $end -$var wire 1 0' nS $end -$var wire 1 1' out0 $end -$var wire 1 2' out1 $end -$var wire 1 3' outfinal $end $upscope $end $upscope $end $scope begin addbits[2] $end $scope module attempt $end -$var wire 1 4' A $end -$var wire 1 5' AandB $end -$var wire 1 6' AddSubSLTSum $end -$var wire 1 7' AxorB $end -$var wire 1 8' B $end -$var wire 1 9' BornB $end -$var wire 1 :' CINandAxorB $end -$var wire 3 ;' Command [2:0] $end -$var wire 1 <' carryin $end -$var wire 1 =' carryout $end -$var wire 1 >' nB $end -$var wire 1 ?' nCmd2 $end -$var wire 1 @' subtract $end +$var wire 1 ]& A $end +$var wire 1 ^& AandB $end +$var wire 1 _& AddSubSLTSum $end +$var wire 1 `& AxorB $end +$var wire 1 a& B $end +$var wire 1 b& BornB $end +$var wire 1 c& CINandAxorB $end +$var wire 3 d& Command [2:0] $end +$var wire 1 e& carryin $end +$var wire 1 f& carryout $end +$var wire 1 g& nB $end +$var wire 1 h& nCmd2 $end +$var wire 1 i& subtract $end $scope module mux0 $end -$var wire 1 A' S $end -$var wire 1 8' in0 $end -$var wire 1 >' in1 $end -$var wire 1 B' nS $end -$var wire 1 C' out0 $end -$var wire 1 D' out1 $end -$var wire 1 9' outfinal $end +$var wire 1 j& S $end +$var wire 1 a& in0 $end +$var wire 1 g& in1 $end +$var wire 1 k& nS $end +$var wire 1 l& out0 $end +$var wire 1 m& out1 $end +$var wire 1 b& outfinal $end $upscope $end $upscope $end -$scope module setSLTres $end -$var wire 1 ^& S $end -$var wire 1 E' in0 $end -$var wire 1 F' in1 $end -$var wire 1 G' nS $end -$var wire 1 H' out0 $end -$var wire 1 I' out1 $end -$var wire 1 J' outfinal $end -$upscope $end $upscope $end $scope begin addbits[3] $end $scope module attempt $end -$var wire 1 K' A $end -$var wire 1 L' AandB $end -$var wire 1 M' AddSubSLTSum $end -$var wire 1 N' AxorB $end -$var wire 1 O' B $end -$var wire 1 P' BornB $end -$var wire 1 Q' CINandAxorB $end -$var wire 3 R' Command [2:0] $end -$var wire 1 S' carryin $end -$var wire 1 T' carryout $end -$var wire 1 U' nB $end -$var wire 1 V' nCmd2 $end -$var wire 1 W' subtract $end +$var wire 1 n& A $end +$var wire 1 o& AandB $end +$var wire 1 p& AddSubSLTSum $end +$var wire 1 q& AxorB $end +$var wire 1 r& B $end +$var wire 1 s& BornB $end +$var wire 1 t& CINandAxorB $end +$var wire 3 u& Command [2:0] $end +$var wire 1 v& carryin $end +$var wire 1 w& carryout $end +$var wire 1 x& nB $end +$var wire 1 y& nCmd2 $end +$var wire 1 z& subtract $end $scope module mux0 $end -$var wire 1 X' S $end -$var wire 1 O' in0 $end -$var wire 1 U' in1 $end -$var wire 1 Y' nS $end -$var wire 1 Z' out0 $end -$var wire 1 [' out1 $end -$var wire 1 P' outfinal $end -$upscope $end +$var wire 1 {& S $end +$var wire 1 r& in0 $end +$var wire 1 x& in1 $end +$var wire 1 |& nS $end +$var wire 1 }& out0 $end +$var wire 1 ~& out1 $end +$var wire 1 s& outfinal $end $upscope $end -$scope module setSLTres $end -$var wire 1 ^& S $end -$var wire 1 \' in0 $end -$var wire 1 ]' in1 $end -$var wire 1 ^' nS $end -$var wire 1 _' out0 $end -$var wire 1 `' out1 $end -$var wire 1 a' outfinal $end $upscope $end $upscope $end $upscope $end $scope module trial1 $end -$var wire 4 b' A [3:0] $end -$var wire 4 c' AndNandOut [3:0] $end -$var wire 4 d' B [3:0] $end -$var wire 3 e' Command [2:0] $end +$var wire 4 !' A [3:0] $end +$var wire 4 "' AndNandOut [3:0] $end +$var wire 4 #' B [3:0] $end +$var wire 3 $' Command [2:0] $end $scope module attempt2 $end -$var wire 1 f' A $end -$var wire 1 g' AandB $end -$var wire 1 h' AnandB $end -$var wire 1 i' AndNandOut $end -$var wire 1 j' B $end -$var wire 3 k' Command [2:0] $end +$var wire 1 %' A $end +$var wire 1 &' AandB $end +$var wire 1 '' AnandB $end +$var wire 1 (' AndNandOut $end +$var wire 1 )' B $end +$var wire 3 *' Command [2:0] $end $scope module potato $end -$var wire 1 l' S $end -$var wire 1 g' in0 $end -$var wire 1 h' in1 $end -$var wire 1 m' nS $end -$var wire 1 n' out0 $end -$var wire 1 o' out1 $end -$var wire 1 i' outfinal $end +$var wire 1 +' S $end +$var wire 1 &' in0 $end +$var wire 1 '' in1 $end +$var wire 1 ,' nS $end +$var wire 1 -' out0 $end +$var wire 1 .' out1 $end +$var wire 1 (' outfinal $end $upscope $end $upscope $end $scope begin andbits[1] $end $scope module attempt $end -$var wire 1 p' A $end -$var wire 1 q' AandB $end -$var wire 1 r' AnandB $end -$var wire 1 s' AndNandOut $end -$var wire 1 t' B $end -$var wire 3 u' Command [2:0] $end +$var wire 1 /' A $end +$var wire 1 0' AandB $end +$var wire 1 1' AnandB $end +$var wire 1 2' AndNandOut $end +$var wire 1 3' B $end +$var wire 3 4' Command [2:0] $end $scope module potato $end -$var wire 1 v' S $end -$var wire 1 q' in0 $end -$var wire 1 r' in1 $end -$var wire 1 w' nS $end -$var wire 1 x' out0 $end -$var wire 1 y' out1 $end -$var wire 1 s' outfinal $end +$var wire 1 5' S $end +$var wire 1 0' in0 $end +$var wire 1 1' in1 $end +$var wire 1 6' nS $end +$var wire 1 7' out0 $end +$var wire 1 8' out1 $end +$var wire 1 2' outfinal $end $upscope $end $upscope $end $upscope $end $scope begin andbits[2] $end $scope module attempt $end -$var wire 1 z' A $end -$var wire 1 {' AandB $end -$var wire 1 |' AnandB $end -$var wire 1 }' AndNandOut $end -$var wire 1 ~' B $end -$var wire 3 !( Command [2:0] $end +$var wire 1 9' A $end +$var wire 1 :' AandB $end +$var wire 1 ;' AnandB $end +$var wire 1 <' AndNandOut $end +$var wire 1 =' B $end +$var wire 3 >' Command [2:0] $end $scope module potato $end -$var wire 1 "( S $end -$var wire 1 {' in0 $end -$var wire 1 |' in1 $end -$var wire 1 #( nS $end -$var wire 1 $( out0 $end -$var wire 1 %( out1 $end -$var wire 1 }' outfinal $end +$var wire 1 ?' S $end +$var wire 1 :' in0 $end +$var wire 1 ;' in1 $end +$var wire 1 @' nS $end +$var wire 1 A' out0 $end +$var wire 1 B' out1 $end +$var wire 1 <' outfinal $end $upscope $end $upscope $end $upscope $end $scope begin andbits[3] $end $scope module attempt $end -$var wire 1 &( A $end -$var wire 1 '( AandB $end -$var wire 1 (( AnandB $end -$var wire 1 )( AndNandOut $end -$var wire 1 *( B $end -$var wire 3 +( Command [2:0] $end +$var wire 1 C' A $end +$var wire 1 D' AandB $end +$var wire 1 E' AnandB $end +$var wire 1 F' AndNandOut $end +$var wire 1 G' B $end +$var wire 3 H' Command [2:0] $end $scope module potato $end -$var wire 1 ,( S $end -$var wire 1 '( in0 $end -$var wire 1 (( in1 $end -$var wire 1 -( nS $end -$var wire 1 .( out0 $end -$var wire 1 /( out1 $end -$var wire 1 )( outfinal $end +$var wire 1 I' S $end +$var wire 1 D' in0 $end +$var wire 1 E' in1 $end +$var wire 1 J' nS $end +$var wire 1 K' out0 $end +$var wire 1 L' out1 $end +$var wire 1 F' outfinal $end $upscope $end $upscope $end $upscope $end $upscope $end $scope module trial2 $end -$var wire 4 0( A [3:0] $end -$var wire 4 1( B [3:0] $end -$var wire 3 2( Command [2:0] $end -$var wire 4 3( OrNorXorOut [3:0] $end +$var wire 4 M' A [3:0] $end +$var wire 4 N' B [3:0] $end +$var wire 3 O' Command [2:0] $end +$var wire 4 P' OrNorXorOut [3:0] $end $scope module attempt2 $end -$var wire 1 4( A $end -$var wire 1 5( AnandB $end -$var wire 1 6( AnorB $end -$var wire 1 7( AorB $end -$var wire 1 8( AxorB $end -$var wire 1 9( B $end -$var wire 3 :( Command [2:0] $end -$var wire 1 ;( OrNorXorOut $end -$var wire 1 <( XorNor $end -$var wire 1 =( nXor $end +$var wire 1 Q' A $end +$var wire 1 R' AnandB $end +$var wire 1 S' AnorB $end +$var wire 1 T' AorB $end +$var wire 1 U' AxorB $end +$var wire 1 V' B $end +$var wire 3 W' Command [2:0] $end +$var wire 1 X' OrNorXorOut $end +$var wire 1 Y' XorNor $end +$var wire 1 Z' nXor $end $scope module mux0 $end -$var wire 1 >( S $end -$var wire 1 8( in0 $end -$var wire 1 6( in1 $end -$var wire 1 ?( nS $end -$var wire 1 @( out0 $end -$var wire 1 A( out1 $end -$var wire 1 <( outfinal $end +$var wire 1 [' S $end +$var wire 1 U' in0 $end +$var wire 1 S' in1 $end +$var wire 1 \' nS $end +$var wire 1 ]' out0 $end +$var wire 1 ^' out1 $end +$var wire 1 Y' outfinal $end $upscope $end $scope module mux1 $end -$var wire 1 B( S $end -$var wire 1 <( in0 $end -$var wire 1 7( in1 $end -$var wire 1 C( nS $end -$var wire 1 D( out0 $end -$var wire 1 E( out1 $end -$var wire 1 ;( outfinal $end +$var wire 1 _' S $end +$var wire 1 Y' in0 $end +$var wire 1 T' in1 $end +$var wire 1 `' nS $end +$var wire 1 a' out0 $end +$var wire 1 b' out1 $end +$var wire 1 X' outfinal $end $upscope $end $upscope $end $scope begin orbits[1] $end $scope module attempt $end -$var wire 1 F( A $end -$var wire 1 G( AnandB $end -$var wire 1 H( AnorB $end -$var wire 1 I( AorB $end -$var wire 1 J( AxorB $end -$var wire 1 K( B $end -$var wire 3 L( Command [2:0] $end -$var wire 1 M( OrNorXorOut $end -$var wire 1 N( XorNor $end -$var wire 1 O( nXor $end +$var wire 1 c' A $end +$var wire 1 d' AnandB $end +$var wire 1 e' AnorB $end +$var wire 1 f' AorB $end +$var wire 1 g' AxorB $end +$var wire 1 h' B $end +$var wire 3 i' Command [2:0] $end +$var wire 1 j' OrNorXorOut $end +$var wire 1 k' XorNor $end +$var wire 1 l' nXor $end $scope module mux0 $end -$var wire 1 P( S $end -$var wire 1 J( in0 $end -$var wire 1 H( in1 $end -$var wire 1 Q( nS $end -$var wire 1 R( out0 $end -$var wire 1 S( out1 $end -$var wire 1 N( outfinal $end +$var wire 1 m' S $end +$var wire 1 g' in0 $end +$var wire 1 e' in1 $end +$var wire 1 n' nS $end +$var wire 1 o' out0 $end +$var wire 1 p' out1 $end +$var wire 1 k' outfinal $end $upscope $end $scope module mux1 $end -$var wire 1 T( S $end -$var wire 1 N( in0 $end -$var wire 1 I( in1 $end -$var wire 1 U( nS $end -$var wire 1 V( out0 $end -$var wire 1 W( out1 $end -$var wire 1 M( outfinal $end +$var wire 1 q' S $end +$var wire 1 k' in0 $end +$var wire 1 f' in1 $end +$var wire 1 r' nS $end +$var wire 1 s' out0 $end +$var wire 1 t' out1 $end +$var wire 1 j' outfinal $end $upscope $end $upscope $end $upscope $end $scope begin orbits[2] $end $scope module attempt $end -$var wire 1 X( A $end -$var wire 1 Y( AnandB $end -$var wire 1 Z( AnorB $end -$var wire 1 [( AorB $end -$var wire 1 \( AxorB $end -$var wire 1 ]( B $end -$var wire 3 ^( Command [2:0] $end -$var wire 1 _( OrNorXorOut $end -$var wire 1 `( XorNor $end -$var wire 1 a( nXor $end +$var wire 1 u' A $end +$var wire 1 v' AnandB $end +$var wire 1 w' AnorB $end +$var wire 1 x' AorB $end +$var wire 1 y' AxorB $end +$var wire 1 z' B $end +$var wire 3 {' Command [2:0] $end +$var wire 1 |' OrNorXorOut $end +$var wire 1 }' XorNor $end +$var wire 1 ~' nXor $end $scope module mux0 $end -$var wire 1 b( S $end -$var wire 1 \( in0 $end -$var wire 1 Z( in1 $end -$var wire 1 c( nS $end -$var wire 1 d( out0 $end -$var wire 1 e( out1 $end -$var wire 1 `( outfinal $end +$var wire 1 !( S $end +$var wire 1 y' in0 $end +$var wire 1 w' in1 $end +$var wire 1 "( nS $end +$var wire 1 #( out0 $end +$var wire 1 $( out1 $end +$var wire 1 }' outfinal $end $upscope $end $scope module mux1 $end -$var wire 1 f( S $end -$var wire 1 `( in0 $end -$var wire 1 [( in1 $end -$var wire 1 g( nS $end -$var wire 1 h( out0 $end -$var wire 1 i( out1 $end -$var wire 1 _( outfinal $end +$var wire 1 %( S $end +$var wire 1 }' in0 $end +$var wire 1 x' in1 $end +$var wire 1 &( nS $end +$var wire 1 '( out0 $end +$var wire 1 (( out1 $end +$var wire 1 |' outfinal $end $upscope $end $upscope $end $upscope $end $scope begin orbits[3] $end $scope module attempt $end -$var wire 1 j( A $end -$var wire 1 k( AnandB $end -$var wire 1 l( AnorB $end -$var wire 1 m( AorB $end -$var wire 1 n( AxorB $end -$var wire 1 o( B $end -$var wire 3 p( Command [2:0] $end -$var wire 1 q( OrNorXorOut $end -$var wire 1 r( XorNor $end -$var wire 1 s( nXor $end +$var wire 1 )( A $end +$var wire 1 *( AnandB $end +$var wire 1 +( AnorB $end +$var wire 1 ,( AorB $end +$var wire 1 -( AxorB $end +$var wire 1 .( B $end +$var wire 3 /( Command [2:0] $end +$var wire 1 0( OrNorXorOut $end +$var wire 1 1( XorNor $end +$var wire 1 2( nXor $end $scope module mux0 $end -$var wire 1 t( S $end -$var wire 1 n( in0 $end -$var wire 1 l( in1 $end -$var wire 1 u( nS $end -$var wire 1 v( out0 $end -$var wire 1 w( out1 $end -$var wire 1 r( outfinal $end +$var wire 1 3( S $end +$var wire 1 -( in0 $end +$var wire 1 +( in1 $end +$var wire 1 4( nS $end +$var wire 1 5( out0 $end +$var wire 1 6( out1 $end +$var wire 1 1( outfinal $end $upscope $end $scope module mux1 $end -$var wire 1 x( S $end -$var wire 1 r( in0 $end -$var wire 1 m( in1 $end -$var wire 1 y( nS $end -$var wire 1 z( out0 $end -$var wire 1 {( out1 $end -$var wire 1 q( outfinal $end +$var wire 1 7( S $end +$var wire 1 1( in0 $end +$var wire 1 ,( in1 $end +$var wire 1 8( nS $end +$var wire 1 9( out0 $end +$var wire 1 :( out1 $end +$var wire 1 0( outfinal $end $upscope $end $upscope $end $upscope $end $upscope $end $scope module ZeroMux0case $end -$var wire 1 |( S0 $end -$var wire 1 }( S1 $end -$var wire 1 ~( in0 $end -$var wire 1 !) in1 $end -$var wire 1 ") in2 $end -$var wire 1 #) in3 $end -$var wire 1 $) nS0 $end -$var wire 1 %) nS1 $end -$var wire 1 &) out $end -$var wire 1 ') out0 $end -$var wire 1 () out1 $end -$var wire 1 )) out2 $end -$var wire 1 *) out3 $end +$var wire 1 ;( S0 $end +$var wire 1 <( S1 $end +$var wire 1 =( in0 $end +$var wire 1 >( in1 $end +$var wire 1 ?( in2 $end +$var wire 1 @( in3 $end +$var wire 1 A( nS0 $end +$var wire 1 B( nS1 $end +$var wire 1 C( out $end +$var wire 1 D( out0 $end +$var wire 1 E( out1 $end +$var wire 1 F( out2 $end +$var wire 1 G( out3 $end $upscope $end $scope module OneMux0case $end -$var wire 1 +) S0 $end -$var wire 1 ,) S1 $end -$var wire 1 -) in0 $end -$var wire 1 .) in1 $end -$var wire 1 /) in2 $end -$var wire 1 0) in3 $end -$var wire 1 1) nS0 $end -$var wire 1 2) nS1 $end -$var wire 1 3) out $end -$var wire 1 4) out0 $end -$var wire 1 5) out1 $end -$var wire 1 6) out2 $end -$var wire 1 7) out3 $end +$var wire 1 H( S0 $end +$var wire 1 I( S1 $end +$var wire 1 J( in0 $end +$var wire 1 K( in1 $end +$var wire 1 L( in2 $end +$var wire 1 M( in3 $end +$var wire 1 N( nS0 $end +$var wire 1 O( nS1 $end +$var wire 1 P( out $end +$var wire 1 Q( out0 $end +$var wire 1 R( out1 $end +$var wire 1 S( out2 $end +$var wire 1 T( out3 $end $upscope $end $scope module TwoMux0case $end -$var wire 1 8) S $end -$var wire 1 9) in0 $end -$var wire 1 :) in1 $end -$var wire 1 ;) nS $end -$var wire 1 <) out0 $end -$var wire 1 =) out1 $end -$var wire 1 >) outfinal $end +$var wire 1 U( S $end +$var wire 1 V( in0 $end +$var wire 1 W( in1 $end +$var wire 1 X( nS $end +$var wire 1 Y( out0 $end +$var wire 1 Z( out1 $end +$var wire 1 [( outfinal $end $upscope $end $scope begin muxbits[1] $end $scope module ZeroMux $end -$var wire 1 ?) S0 $end -$var wire 1 @) S1 $end -$var wire 1 A) in0 $end -$var wire 1 B) in1 $end -$var wire 1 C) in2 $end -$var wire 1 D) in3 $end -$var wire 1 E) nS0 $end -$var wire 1 F) nS1 $end -$var wire 1 G) out $end -$var wire 1 H) out0 $end -$var wire 1 I) out1 $end -$var wire 1 J) out2 $end -$var wire 1 K) out3 $end +$var wire 1 \( S0 $end +$var wire 1 ]( S1 $end +$var wire 1 ^( in0 $end +$var wire 1 _( in1 $end +$var wire 1 `( in2 $end +$var wire 1 a( in3 $end +$var wire 1 b( nS0 $end +$var wire 1 c( nS1 $end +$var wire 1 d( out $end +$var wire 1 e( out0 $end +$var wire 1 f( out1 $end +$var wire 1 g( out2 $end +$var wire 1 h( out3 $end $upscope $end $scope module OneMux $end -$var wire 1 L) S0 $end -$var wire 1 M) S1 $end -$var wire 1 N) in0 $end -$var wire 1 O) in1 $end -$var wire 1 P) in2 $end -$var wire 1 Q) in3 $end -$var wire 1 R) nS0 $end -$var wire 1 S) nS1 $end -$var wire 1 T) out $end -$var wire 1 U) out0 $end -$var wire 1 V) out1 $end -$var wire 1 W) out2 $end -$var wire 1 X) out3 $end +$var wire 1 i( S0 $end +$var wire 1 j( S1 $end +$var wire 1 k( in0 $end +$var wire 1 l( in1 $end +$var wire 1 m( in2 $end +$var wire 1 n( in3 $end +$var wire 1 o( nS0 $end +$var wire 1 p( nS1 $end +$var wire 1 q( out $end +$var wire 1 r( out0 $end +$var wire 1 s( out1 $end +$var wire 1 t( out2 $end +$var wire 1 u( out3 $end $upscope $end $scope module TwoMux $end -$var wire 1 Y) S $end -$var wire 1 Z) in0 $end -$var wire 1 [) in1 $end -$var wire 1 \) nS $end -$var wire 1 ]) out0 $end -$var wire 1 ^) out1 $end -$var wire 1 _) outfinal $end +$var wire 1 v( S $end +$var wire 1 w( in0 $end +$var wire 1 x( in1 $end +$var wire 1 y( nS $end +$var wire 1 z( out0 $end +$var wire 1 {( out1 $end +$var wire 1 |( outfinal $end $upscope $end $upscope $end $scope begin muxbits[2] $end $scope module ZeroMux $end -$var wire 1 `) S0 $end -$var wire 1 a) S1 $end -$var wire 1 b) in0 $end -$var wire 1 c) in1 $end -$var wire 1 d) in2 $end -$var wire 1 e) in3 $end -$var wire 1 f) nS0 $end -$var wire 1 g) nS1 $end -$var wire 1 h) out $end -$var wire 1 i) out0 $end -$var wire 1 j) out1 $end -$var wire 1 k) out2 $end -$var wire 1 l) out3 $end +$var wire 1 }( S0 $end +$var wire 1 ~( S1 $end +$var wire 1 !) in0 $end +$var wire 1 ") in1 $end +$var wire 1 #) in2 $end +$var wire 1 $) in3 $end +$var wire 1 %) nS0 $end +$var wire 1 &) nS1 $end +$var wire 1 ') out $end +$var wire 1 () out0 $end +$var wire 1 )) out1 $end +$var wire 1 *) out2 $end +$var wire 1 +) out3 $end $upscope $end $scope module OneMux $end -$var wire 1 m) S0 $end -$var wire 1 n) S1 $end -$var wire 1 o) in0 $end -$var wire 1 p) in1 $end -$var wire 1 q) in2 $end -$var wire 1 r) in3 $end -$var wire 1 s) nS0 $end -$var wire 1 t) nS1 $end -$var wire 1 u) out $end -$var wire 1 v) out0 $end -$var wire 1 w) out1 $end -$var wire 1 x) out2 $end -$var wire 1 y) out3 $end +$var wire 1 ,) S0 $end +$var wire 1 -) S1 $end +$var wire 1 .) in0 $end +$var wire 1 /) in1 $end +$var wire 1 0) in2 $end +$var wire 1 1) in3 $end +$var wire 1 2) nS0 $end +$var wire 1 3) nS1 $end +$var wire 1 4) out $end +$var wire 1 5) out0 $end +$var wire 1 6) out1 $end +$var wire 1 7) out2 $end +$var wire 1 8) out3 $end $upscope $end $scope module TwoMux $end -$var wire 1 z) S $end -$var wire 1 {) in0 $end -$var wire 1 |) in1 $end -$var wire 1 }) nS $end -$var wire 1 ~) out0 $end -$var wire 1 !* out1 $end -$var wire 1 "* outfinal $end +$var wire 1 9) S $end +$var wire 1 :) in0 $end +$var wire 1 ;) in1 $end +$var wire 1 <) nS $end +$var wire 1 =) out0 $end +$var wire 1 >) out1 $end +$var wire 1 ?) outfinal $end $upscope $end $upscope $end $scope begin muxbits[3] $end $scope module ZeroMux $end -$var wire 1 #* S0 $end -$var wire 1 $* S1 $end -$var wire 1 %* in0 $end -$var wire 1 &* in1 $end -$var wire 1 '* in2 $end -$var wire 1 (* in3 $end -$var wire 1 )* nS0 $end -$var wire 1 ** nS1 $end -$var wire 1 +* out $end -$var wire 1 ,* out0 $end -$var wire 1 -* out1 $end -$var wire 1 .* out2 $end -$var wire 1 /* out3 $end +$var wire 1 @) S0 $end +$var wire 1 A) S1 $end +$var wire 1 B) in0 $end +$var wire 1 C) in1 $end +$var wire 1 D) in2 $end +$var wire 1 E) in3 $end +$var wire 1 F) nS0 $end +$var wire 1 G) nS1 $end +$var wire 1 H) out $end +$var wire 1 I) out0 $end +$var wire 1 J) out1 $end +$var wire 1 K) out2 $end +$var wire 1 L) out3 $end $upscope $end $scope module OneMux $end -$var wire 1 0* S0 $end -$var wire 1 1* S1 $end -$var wire 1 2* in0 $end -$var wire 1 3* in1 $end -$var wire 1 4* in2 $end -$var wire 1 5* in3 $end -$var wire 1 6* nS0 $end -$var wire 1 7* nS1 $end -$var wire 1 8* out $end -$var wire 1 9* out0 $end -$var wire 1 :* out1 $end -$var wire 1 ;* out2 $end -$var wire 1 <* out3 $end +$var wire 1 M) S0 $end +$var wire 1 N) S1 $end +$var wire 1 O) in0 $end +$var wire 1 P) in1 $end +$var wire 1 Q) in2 $end +$var wire 1 R) in3 $end +$var wire 1 S) nS0 $end +$var wire 1 T) nS1 $end +$var wire 1 U) out $end +$var wire 1 V) out0 $end +$var wire 1 W) out1 $end +$var wire 1 X) out2 $end +$var wire 1 Y) out3 $end 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g$ +b1 t$ +#61270000 +0G( +0+ +#61280000 +1V( +1C( +b1 b$ +1-" +1{$ +#61290000 +0$" +0r$ +#61300000 +1Y( +#61310000 +0(" +0v$ +#61320000 +1[( b1 $ -b1 '% -#60330000 +b1 e$ +#61330000 +0( 0' -#60340000 -1g" -1W% -b1 ( -b1 *% -#60350000 -0i" -0Y% -#60360000 -b11 ( -b11 *% -#60370000 -0#) -0j" -0Z% +#61340000 +1G" +17% +b1 ) +b1 h$ +#61350000 +0I" +09% +#61360000 +b11 ) +b11 h$ +#61370000 +0@( +0J" +0:% b0 & -b0 F" -b0 )% -b0 6% -#60380000 -1*) -b111 ( -b111 *% -#60390000 -09) -0&) -b0 $% -#60400000 -b1111 ( -b1111 *% -#60410000 -0-% -0<) -#60430000 +b0 &" +b0 g$ +b0 t$ +#61380000 +1G( +b111 ) +b111 h$ +#61390000 +0V( +0C( +b0 b$ +#61400000 +b1111 ) +b1111 h$ +#61410000 +0k$ +0Y( +#61430000 0" -0>) +0[( b0 $ -b0 '% -#60450000 -b1110 ( -b1110 *% -#60470000 -b1100 ( -b1100 *% -#60490000 -b1000 ( -b1000 *% -#60510000 -b0 ( -b0 *% -#60520000 -1-% -#60540000 +b0 e$ +#61450000 +b1110 ) +b1110 h$ +#61470000 +b1100 ) +b1100 h$ +#61490000 +b1000 ) +b1000 h$ +#61510000 +b0 ) +b0 h$ +#61520000 +1k$ +#61540000 1" -#61000000 +#62000000 diff --git a/alu.v b/alu.v index 8d2acb0..4f4e1fc 100644 --- a/alu.v +++ b/alu.v @@ -84,7 +84,6 @@ input[2:0] Command TwoInMux mux1(OrNorXorOut, Command[0], XorNor, AorB); endmodule - // this module calculates addition, subtraction, and SLT based on which command is selected. SLT happens when A; -v0xa38650_0 .var "A", 3 0; -RS_0x7ffb33a70098/0/0 .resolv tri, L_0xa3a560, L_0xa3c1f0, L_0xa3de90, L_0xa3fea0; -RS_0x7ffb33a70098/0/4 .resolv tri, L_0xa65ad0, L_0xa67820, L_0xa69740, L_0xa6be60; -RS_0x7ffb33a70098 .resolv tri, RS_0x7ffb33a70098/0/0, RS_0x7ffb33a70098/0/4, C4, C4; -v0xa386d0_0 .net8 "AddSubSLTSum", 3 0, RS_0x7ffb33a70098; 8 drivers -v0xa38750_0 .net "AllZeros", 0 0, L_0xa77250; 1 drivers -RS_0x7ffb33a6ee38/0/0 .resolv tri, L_0xa4bac0, L_0xa4c570, L_0xa4cfe0, L_0xa4da40; -RS_0x7ffb33a6ee38/0/4 .resolv tri, L_0xa6d7c0, L_0xa6e230, L_0xa6eca0, L_0xa6f800; -RS_0x7ffb33a6ee38 .resolv tri, RS_0x7ffb33a6ee38/0/0, RS_0x7ffb33a6ee38/0/4, C4, C4; -v0xa387d0_0 .net8 "AndNandOut", 3 0, RS_0x7ffb33a6ee38; 8 drivers -v0xa38850_0 .var "B", 3 0; -v0xa388d0_0 .var "Command", 2 0; -RS_0x7ffb33a71f88 .resolv tri, L_0xa54a70, L_0xa573c0, L_0xa59ee0, L_0xa766c0; -v0xa38950_0 .net8 "OneBitFinalOut", 3 0, RS_0x7ffb33a71f88; 4 drivers -RS_0x7ffb33a6e748/0/0 .resolv tri, L_0xa4ee00, L_0xa50140, L_0xa51440, L_0xa52730; -RS_0x7ffb33a6e748/0/4 .resolv tri, L_0xa70bc0, L_0xa71ec0, L_0xa731c0, L_0xa744b0; -RS_0x7ffb33a6e748 .resolv tri, RS_0x7ffb33a6e748/0/0, RS_0x7ffb33a6e748/0/4, C4, C4; -v0xa389d0_0 .net8 "OrNorXorOut", 3 0, RS_0x7ffb33a6e748; 8 drivers -RS_0x7ffb33a71c58/0/0 .resolv tri, L_0xa43020, L_0xa45330, L_0xa47b60, L_0xa4b110; -RS_0x7ffb33a71c58/0/4 .resolv tri, L_0xa5c560, L_0xa5e700, L_0xa60980, L_0xa64010; -RS_0x7ffb33a71c58 .resolv tri, RS_0x7ffb33a71c58/0/0, RS_0x7ffb33a71c58/0/4, C4, C4; -v0xa38a50_0 .net8 "SLTSum", 3 0, RS_0x7ffb33a71c58; 8 drivers -RS_0x7ffb33a70188 .resolv tri, L_0xa40f00, L_0xa4abf0, L_0xa63a00, L_0xa6cee0; -v0xa38ad0_0 .net8 "SLTflag", 0 0, RS_0x7ffb33a70188; 4 drivers -RS_0x7ffb33a71fb8 .resolv tri, L_0xa54f20, L_0xa57890, L_0xa5a020, L_0xa76980; -v0xa38b50_0 .net8 "ZeroFlag", 3 0, RS_0x7ffb33a71fb8; 4 drivers -v0xa38c00_0 .var "carryin", 3 0; -RS_0x7ffb33a703c8 .resolv tri, L_0xa40170, L_0xa371a0, L_0xa62700, L_0xa6c130; -v0xa38c80_0 .net8 "carryout", 0 0, RS_0x7ffb33a703c8; 4 drivers -RS_0x7ffb33a70488 .resolv tri, L_0xa3ff40, L_0xa4a230, L_0xa63050, L_0xa6bfb0; -v0xa38d00_0 .net8 "overflow", 0 0, RS_0x7ffb33a70488; 4 drivers -RS_0x7ffb33a704b8/0/0 .resolv tri, L_0xa39e20, L_0xa3ba20, L_0xa3d760, L_0xa3f7a0; -RS_0x7ffb33a704b8/0/4 .resolv tri, L_0xa421c0, L_0xa44520, L_0xa455c0, L_0xa48340; -RS_0x7ffb33a704b8/0/8 .resolv tri, L_0xa5b660, L_0xa5d970, L_0xa5e990, L_0xa61160; -RS_0x7ffb33a704b8/0/12 .resolv tri, L_0xa65390, L_0xa67120, L_0xa68d90, L_0xa6b7f0; -RS_0x7ffb33a704b8 .resolv tri, RS_0x7ffb33a704b8/0/0, RS_0x7ffb33a704b8/0/4, RS_0x7ffb33a704b8/0/8, RS_0x7ffb33a704b8/0/12; -v0xa38e00_0 .net8 "subtract", 3 0, RS_0x7ffb33a704b8; 16 drivers -S_0xa31580 .scope module, "trial" "AddSubSLT32" 2 146, 3 205, S_0x96f1c0; - .timescale -9 -12; -P_0xa2fcc8 .param/l "size" 3 237, +C4<0100>; -L_0xa3e0f0/d .functor NOT 1, L_0xa3e1e0, C4<0>, C4<0>, C4<0>; -L_0xa3e0f0 .delay (10000,10000,10000) L_0xa3e0f0/d; -L_0xa3e280/d .functor AND 1, L_0xa3e3c0, L_0xa3e020, L_0xa3e0f0, C4<1>; -L_0xa3e280 .delay (20000,20000,20000) L_0xa3e280/d; -L_0xa40170/d .functor OR 1, L_0xa40260, C4<0>, C4<0>, C4<0>; -L_0xa40170 .delay (20000,20000,20000) L_0xa40170/d; -L_0xa3ff40/d .functor XOR 1, RS_0x7ffb33a703c8, L_0xa40540, C4<0>, C4<0>; -L_0xa3ff40 .delay (40000,40000,40000) L_0xa3ff40/d; -L_0xa405e0/d .functor NOT 1, RS_0x7ffb33a70488, C4<0>, C4<0>, C4<0>; -L_0xa405e0 .delay (10000,10000,10000) L_0xa405e0/d; -L_0xa406d0/d .functor NOT 1, L_0xa407b0, C4<0>, C4<0>, C4<0>; -L_0xa406d0 .delay (10000,10000,10000) L_0xa406d0/d; -L_0xa3a600/d .functor AND 1, L_0xa405e0, L_0xa40aa0, C4<1>, C4<1>; -L_0xa3a600 .delay (20000,20000,20000) L_0xa3a600/d; -L_0xa40b40/d .functor AND 1, RS_0x7ffb33a70488, L_0xa406d0, C4<1>, C4<1>; -L_0xa40b40 .delay (20000,20000,20000) L_0xa40b40/d; -L_0xa40cb0/d .functor AND 1, L_0xa3a600, L_0xa3e280, C4<1>, C4<1>; -L_0xa40cb0 .delay (20000,20000,20000) L_0xa40cb0/d; -L_0xa40db0/d .functor AND 1, L_0xa40b40, L_0xa3e280, C4<1>, C4<1>; -L_0xa40db0 .delay (20000,20000,20000) L_0xa40db0/d; -L_0xa40f00/d .functor OR 1, L_0xa40cb0, L_0xa40db0, C4<0>, C4<0>; -L_0xa40f00 .delay (20000,20000,20000) L_0xa40f00/d; -v0xa37070_0 .net "A", 3 0, v0xa38650_0; 1 drivers -v0xa1fc00_0 .alias "AddSubSLTSum", 3 0, v0xa386d0_0; -v0xa37220_0 .net "B", 3 0, v0xa38850_0; 1 drivers -RS_0x7ffb33a760f8 .resolv tri, L_0xa39d30, L_0xa3b8d0, L_0xa3d5d0, L_0xa3e460; -v0xa1fe90_0 .net8 "CarryoutWire", 3 0, RS_0x7ffb33a760f8; 4 drivers -v0xa373b0_0 .net "Command", 2 0, v0xa388d0_0; 1 drivers -RS_0x7ffb33a76128 .resolv tri, L_0xa39c40, L_0xa3b7e0, L_0xa3d4e0, L_0xa3f570; -v0xa37430_0 .net8 "NewVal", 3 0, RS_0x7ffb33a76128; 4 drivers -v0xa374d0_0 .net "Res0OF1", 0 0, L_0xa40b40; 1 drivers -v0xa37570_0 .net "Res1OF0", 0 0, L_0xa3a600; 1 drivers -v0xa37660_0 .alias "SLTflag", 0 0, v0xa38ad0_0; -v0xa202d0_0 .net "SLTflag0", 0 0, L_0xa40cb0; 1 drivers -v0xa37810_0 .net "SLTflag1", 0 0, L_0xa40db0; 1 drivers -v0xa378b0_0 .net "SLTon", 0 0, L_0xa3e280; 1 drivers -v0xa379c0_0 .net *"_s37", 0 0, L_0xa3e1e0; 1 drivers -v0xa37a60_0 .net *"_s39", 0 0, L_0xa3e3c0; 1 drivers -v0xa37b80_0 .net *"_s41", 0 0, L_0xa3e020; 1 drivers -v0xa37c20_0 .net *"_s61", 0 0, L_0xa40260; 1 drivers -v0xa37ae0_0 .net/s *"_s62", 0 0, C4<0>; 1 drivers -v0xa37d70_0 .net *"_s65", 0 0, L_0xa40540; 1 drivers -v0xa37e90_0 .net *"_s67", 0 0, L_0xa407b0; 1 drivers -v0xa37f10_0 .net *"_s69", 0 0, L_0xa40aa0; 1 drivers -v0xa37df0_0 .net "carryin", 3 0, v0xa38c00_0; 1 drivers -v0xa380d0_0 .alias "carryout", 0 0, v0xa38c80_0; -v0xa38210_0 .net "nAddSubSLTSum", 0 0, L_0xa406d0; 1 drivers -v0xa38290_0 .net "nCmd2", 0 0, L_0xa3e0f0; 1 drivers -v0xa38150_0 .net "nOF", 0 0, L_0xa405e0; 1 drivers -v0xa383e0_0 .alias "overflow", 0 0, v0xa38d00_0; -v0xa38540_0 .alias "subtract", 3 0, v0xa38e00_0; -L_0xa39c40 .part/pv L_0xa39730, 1, 1, 4; -L_0xa39d30 .part/pv L_0xa39ae0, 1, 1, 4; -L_0xa39e20 .part/pv L_0xa39430, 1, 1, 4; -L_0xa39f10 .part v0xa38650_0, 1, 1; -L_0xa39fb0 .part v0xa38850_0, 1, 1; -L_0xa3a0e0 .part RS_0x7ffb33a760f8, 0, 1; -L_0xa3a560 .part/pv L_0xa3a420, 1, 1, 4; -L_0xa3a690 .part RS_0x7ffb33a76128, 1, 1; -L_0xa3b7e0 .part/pv L_0xa3b350, 2, 1, 4; -L_0xa3b8d0 .part/pv L_0xa3b6a0, 2, 1, 4; -L_0xa3ba20 .part/pv L_0xa3b080, 2, 1, 4; -L_0xa3bac0 .part v0xa38650_0, 2, 1; -L_0xa3bbd0 .part v0xa38850_0, 2, 1; -L_0xa3bd00 .part RS_0x7ffb33a760f8, 1, 1; -L_0xa3c1f0 .part/pv L_0xa3c100, 2, 1, 4; -L_0xa3c290 .part RS_0x7ffb33a76128, 2, 1; -L_0xa3d4e0 .part/pv L_0xa3d030, 3, 1, 4; -L_0xa3d5d0 .part/pv L_0xa3d380, 3, 1, 4; -L_0xa3d760 .part/pv L_0xa3cd60, 3, 1, 4; -L_0xa3d910 .part v0xa38650_0, 3, 1; -L_0xa3d6c0 .part v0xa38850_0, 3, 1; -L_0xa3da60 .part RS_0x7ffb33a760f8, 2, 1; -L_0xa3de90 .part/pv L_0xa3dd50, 3, 1, 4; -L_0xa3df30 .part RS_0x7ffb33a76128, 3, 1; -L_0xa3e1e0 .part v0xa388d0_0, 2, 1; -L_0xa3e3c0 .part v0xa388d0_0, 0, 1; -L_0xa3e020 .part v0xa388d0_0, 1, 1; -L_0xa3f570 .part/pv L_0xa3f0a0, 0, 1, 4; -L_0xa3e460 .part/pv L_0xa3f410, 0, 1, 4; -L_0xa3f7a0 .part/pv L_0xa3edd0, 0, 1, 4; -L_0xa3f660 .part v0xa38650_0, 0, 1; -L_0xa3f990 .part v0xa38850_0, 0, 1; -L_0xa3f890 .part RS_0x7ffb33a704b8, 0, 1; -L_0xa3fea0 .part/pv L_0xa3fd60, 0, 1, 4; -L_0xa3fac0 .part RS_0x7ffb33a76128, 0, 1; -L_0xa40260 .part RS_0x7ffb33a760f8, 3, 1; -L_0xa40540 .part RS_0x7ffb33a760f8, 2, 1; -L_0xa407b0 .part RS_0x7ffb33a70098, 3, 1; -L_0xa40aa0 .part RS_0x7ffb33a70098, 3, 1; -S_0xa36050 .scope module, "attempt2" "MiddleAddSubSLT" 3 233, 3 89, S_0xa31580; - .timescale -9 -12; -L_0xa3e590/d .functor NOT 1, L_0xa3f990, C4<0>, C4<0>, C4<0>; -L_0xa3e590 .delay (10000,10000,10000) L_0xa3e590/d; -L_0xa3ec70/d .functor NOT 1, L_0xa3ed30, C4<0>, C4<0>, C4<0>; -L_0xa3ec70 .delay (10000,10000,10000) L_0xa3ec70/d; -L_0xa3edd0/d .functor AND 1, L_0xa3ef10, L_0xa3ec70, C4<1>, C4<1>; -L_0xa3edd0 .delay (20000,20000,20000) L_0xa3edd0/d; -L_0xa3efb0/d .functor XOR 1, L_0xa3f660, L_0xa3ea00, C4<0>, C4<0>; -L_0xa3efb0 .delay (40000,40000,40000) L_0xa3efb0/d; -L_0xa3f0a0/d .functor XOR 1, L_0xa3efb0, L_0xa3f890, C4<0>, C4<0>; -L_0xa3f0a0 .delay (40000,40000,40000) L_0xa3f0a0/d; -L_0xa3f190/d .functor AND 1, L_0xa3f660, L_0xa3ea00, C4<1>, C4<1>; -L_0xa3f190 .delay (20000,20000,20000) L_0xa3f190/d; -L_0xa3f300/d .functor AND 1, L_0xa3efb0, L_0xa3f890, C4<1>, C4<1>; -L_0xa3f300 .delay (20000,20000,20000) L_0xa3f300/d; -L_0xa3f410/d .functor OR 1, L_0xa3f190, L_0xa3f300, C4<0>, C4<0>; -L_0xa3f410 .delay (20000,20000,20000) L_0xa3f410/d; -v0xa366d0_0 .net "A", 0 0, L_0xa3f660; 1 drivers -v0xa36790_0 .net "AandB", 0 0, L_0xa3f190; 1 drivers -v0xa36830_0 .net "AddSubSLTSum", 0 0, L_0xa3f0a0; 1 drivers -v0xa368d0_0 .net "AxorB", 0 0, L_0xa3efb0; 1 drivers -v0xa36950_0 .net "B", 0 0, L_0xa3f990; 1 drivers -v0xa36a00_0 .net "BornB", 0 0, L_0xa3ea00; 1 drivers -v0xa36ac0_0 .net "CINandAxorB", 0 0, L_0xa3f300; 1 drivers -v0xa36b40_0 .alias "Command", 2 0, v0xa373b0_0; -v0xa36bc0_0 .net *"_s3", 0 0, L_0xa3ed30; 1 drivers -v0xa36c40_0 .net *"_s5", 0 0, L_0xa3ef10; 1 drivers -v0xa36ce0_0 .net "carryin", 0 0, L_0xa3f890; 1 drivers -v0xa36d80_0 .net "carryout", 0 0, L_0xa3f410; 1 drivers -v0xa36e20_0 .net "nB", 0 0, L_0xa3e590; 1 drivers -v0xa36ed0_0 .net "nCmd2", 0 0, L_0xa3ec70; 1 drivers -v0xa36fd0_0 .net "subtract", 0 0, L_0xa3edd0; 1 drivers -L_0xa3ebd0 .part v0xa388d0_0, 0, 1; -L_0xa3ed30 .part v0xa388d0_0, 2, 1; -L_0xa3ef10 .part v0xa388d0_0, 0, 1; -S_0xa36140 .scope module, "mux0" "TwoInMux" 3 105, 3 8, S_0xa36050; - .timescale -9 -12; -L_0xa3e720/d .functor NOT 1, L_0xa3ebd0, C4<0>, C4<0>, C4<0>; -L_0xa3e720 .delay (10000,10000,10000) L_0xa3e720/d; -L_0xa3e7e0/d .functor AND 1, L_0xa3f990, L_0xa3e720, C4<1>, C4<1>; -L_0xa3e7e0 .delay (20000,20000,20000) L_0xa3e7e0/d; -L_0xa3e8f0/d .functor AND 1, L_0xa3e590, L_0xa3ebd0, C4<1>, C4<1>; -L_0xa3e8f0 .delay (20000,20000,20000) L_0xa3e8f0/d; -L_0xa3ea00/d .functor OR 1, L_0xa3e7e0, L_0xa3e8f0, C4<0>, C4<0>; -L_0xa3ea00 .delay (20000,20000,20000) L_0xa3ea00/d; -v0xa36230_0 .net "S", 0 0, L_0xa3ebd0; 1 drivers -v0xa362f0_0 .alias "in0", 0 0, v0xa36950_0; -v0xa36390_0 .alias "in1", 0 0, v0xa36e20_0; -v0xa36430_0 .net "nS", 0 0, L_0xa3e720; 1 drivers -v0xa364b0_0 .net "out0", 0 0, L_0xa3e7e0; 1 drivers -v0xa36550_0 .net "out1", 0 0, L_0xa3e8f0; 1 drivers -v0xa36630_0 .alias "outfinal", 0 0, v0xa36a00_0; -S_0xa35af0 .scope module, "setSLTres" "TwoInMux" 3 234, 3 8, S_0xa31580; - .timescale -9 -12; -L_0xa3f930/d .functor NOT 1, L_0xa3e280, C4<0>, C4<0>, C4<0>; -L_0xa3f930 .delay (10000,10000,10000) L_0xa3f930/d; -L_0xa3fbd0/d .functor AND 1, L_0xa3fac0, L_0xa3f930, C4<1>, C4<1>; -L_0xa3fbd0 .delay (20000,20000,20000) L_0xa3fbd0/d; -L_0xa3fcc0/d .functor AND 1, C4<0>, L_0xa3e280, C4<1>, C4<1>; -L_0xa3fcc0 .delay (20000,20000,20000) L_0xa3fcc0/d; -L_0xa3fd60/d .functor OR 1, L_0xa3fbd0, L_0xa3fcc0, C4<0>, C4<0>; -L_0xa3fd60 .delay (20000,20000,20000) L_0xa3fd60/d; -v0xa35be0_0 .alias "S", 0 0, v0xa378b0_0; -v0xa35c80_0 .net "in0", 0 0, L_0xa3fac0; 1 drivers -v0xa35d20_0 .net "in1", 0 0, C4<0>; 1 drivers -v0xa35dc0_0 .net "nS", 0 0, L_0xa3f930; 1 drivers -v0xa35e70_0 .net "out0", 0 0, L_0xa3fbd0; 1 drivers -v0xa35f10_0 .net "out1", 0 0, L_0xa3fcc0; 1 drivers -v0xa35fb0_0 .net "outfinal", 0 0, L_0xa3fd60; 1 drivers -S_0xa343c0 .scope generate, "addbits[1]" "addbits[1]" 3 239, 3 239, S_0xa31580; - .timescale -9 -12; -P_0xa33dd8 .param/l "i" 3 239, +C4<01>; -S_0xa34a80 .scope module, "attempt" "MiddleAddSubSLT" 3 241, 3 89, S_0xa343c0; - .timescale -9 -12; -L_0xa2a820/d .functor NOT 1, L_0xa39fb0, C4<0>, C4<0>, C4<0>; -L_0xa2a820 .delay (10000,10000,10000) L_0xa2a820/d; -L_0xa392d0/d .functor NOT 1, L_0xa39390, C4<0>, C4<0>, C4<0>; -L_0xa392d0 .delay (10000,10000,10000) L_0xa392d0/d; -L_0xa39430/d .functor AND 1, L_0xa39570, L_0xa392d0, C4<1>, C4<1>; -L_0xa39430 .delay (20000,20000,20000) L_0xa39430/d; -L_0xa39610/d .functor XOR 1, L_0xa39f10, L_0xa390b0, C4<0>, C4<0>; -L_0xa39610 .delay (40000,40000,40000) L_0xa39610/d; -L_0xa39730/d .functor XOR 1, L_0xa39610, L_0xa3a0e0, C4<0>, C4<0>; -L_0xa39730 .delay (40000,40000,40000) L_0xa39730/d; -L_0xa39850/d .functor AND 1, L_0xa39f10, L_0xa390b0, C4<1>, C4<1>; -L_0xa39850 .delay (20000,20000,20000) L_0xa39850/d; -L_0xa399f0/d .functor AND 1, L_0xa39610, L_0xa3a0e0, C4<1>, C4<1>; -L_0xa399f0 .delay (20000,20000,20000) L_0xa399f0/d; -L_0xa39ae0/d .functor OR 1, L_0xa39850, L_0xa399f0, C4<0>, C4<0>; -L_0xa39ae0 .delay (20000,20000,20000) L_0xa39ae0/d; -v0xa35100_0 .net "A", 0 0, L_0xa39f10; 1 drivers -v0xa351c0_0 .net "AandB", 0 0, L_0xa39850; 1 drivers -v0xa35260_0 .net "AddSubSLTSum", 0 0, L_0xa39730; 1 drivers -v0xa35300_0 .net "AxorB", 0 0, L_0xa39610; 1 drivers -v0xa35380_0 .net "B", 0 0, L_0xa39fb0; 1 drivers -v0xa35430_0 .net "BornB", 0 0, L_0xa390b0; 1 drivers -v0xa354f0_0 .net "CINandAxorB", 0 0, L_0xa399f0; 1 drivers -v0xa35570_0 .alias "Command", 2 0, v0xa373b0_0; -v0xa35640_0 .net *"_s3", 0 0, L_0xa39390; 1 drivers -v0xa356c0_0 .net *"_s5", 0 0, L_0xa39570; 1 drivers -v0xa35760_0 .net "carryin", 0 0, L_0xa3a0e0; 1 drivers -v0xa35800_0 .net "carryout", 0 0, L_0xa39ae0; 1 drivers -v0xa358a0_0 .net "nB", 0 0, L_0xa2a820; 1 drivers -v0xa35950_0 .net "nCmd2", 0 0, L_0xa392d0; 1 drivers -v0xa35a50_0 .net "subtract", 0 0, L_0xa39430; 1 drivers -L_0xa39230 .part v0xa388d0_0, 0, 1; -L_0xa39390 .part v0xa388d0_0, 2, 1; -L_0xa39570 .part v0xa388d0_0, 0, 1; -S_0xa34b70 .scope module, "mux0" "TwoInMux" 3 105, 3 8, S_0xa34a80; - .timescale -9 -12; -L_0xa38e80/d .functor NOT 1, L_0xa39230, C4<0>, C4<0>, C4<0>; -L_0xa38e80 .delay (10000,10000,10000) L_0xa38e80/d; -L_0xa38f00/d .functor AND 1, L_0xa39fb0, L_0xa38e80, C4<1>, C4<1>; -L_0xa38f00 .delay (20000,20000,20000) L_0xa38f00/d; -L_0xa38ff0/d .functor AND 1, L_0xa2a820, L_0xa39230, C4<1>, C4<1>; -L_0xa38ff0 .delay (20000,20000,20000) L_0xa38ff0/d; -L_0xa390b0/d .functor OR 1, L_0xa38f00, L_0xa38ff0, C4<0>, C4<0>; -L_0xa390b0 .delay (20000,20000,20000) L_0xa390b0/d; -v0xa34c60_0 .net "S", 0 0, L_0xa39230; 1 drivers -v0xa34d20_0 .alias "in0", 0 0, v0xa35380_0; -v0xa34dc0_0 .alias "in1", 0 0, v0xa358a0_0; -v0xa34e60_0 .net "nS", 0 0, L_0xa38e80; 1 drivers -v0xa34ee0_0 .net "out0", 0 0, L_0xa38f00; 1 drivers -v0xa34f80_0 .net "out1", 0 0, L_0xa38ff0; 1 drivers -v0xa35060_0 .alias "outfinal", 0 0, v0xa35430_0; -S_0xa34530 .scope module, "setSLTres" "TwoInMux" 3 242, 3 8, S_0xa343c0; - .timescale -9 -12; -L_0xa3a180/d .functor NOT 1, L_0xa3e280, C4<0>, C4<0>, C4<0>; -L_0xa3a180 .delay (10000,10000,10000) L_0xa3a180/d; -L_0xa3a270/d .functor AND 1, L_0xa3a690, L_0xa3a180, C4<1>, C4<1>; -L_0xa3a270 .delay (20000,20000,20000) L_0xa3a270/d; -L_0xa3a380/d .functor AND 1, C4<0>, L_0xa3e280, C4<1>, C4<1>; -L_0xa3a380 .delay (20000,20000,20000) L_0xa3a380/d; -L_0xa3a420/d .functor OR 1, L_0xa3a270, L_0xa3a380, C4<0>, C4<0>; -L_0xa3a420 .delay (20000,20000,20000) L_0xa3a420/d; -v0xa34620_0 .alias "S", 0 0, v0xa378b0_0; -v0xa346a0_0 .net "in0", 0 0, L_0xa3a690; 1 drivers -v0xa34740_0 .net "in1", 0 0, C4<0>; 1 drivers -v0xa347e0_0 .net "nS", 0 0, L_0xa3a180; 1 drivers -v0xa34860_0 .net "out0", 0 0, L_0xa3a270; 1 drivers -v0xa34900_0 .net "out1", 0 0, L_0xa3a380; 1 drivers -v0xa349e0_0 .net "outfinal", 0 0, L_0xa3a420; 1 drivers -S_0xa32ca0 .scope generate, "addbits[2]" "addbits[2]" 3 239, 3 239, S_0xa31580; - .timescale -9 -12; -P_0xa326b8 .param/l "i" 3 239, +C4<010>; -S_0xa333a0 .scope module, "attempt" "MiddleAddSubSLT" 3 241, 3 89, S_0xa32ca0; - .timescale -9 -12; -L_0xa3a820/d .functor NOT 1, L_0xa3bbd0, C4<0>, C4<0>, C4<0>; -L_0xa3a820 .delay (10000,10000,10000) L_0xa3a820/d; -L_0xa3af60/d .functor NOT 1, L_0xa3afe0, C4<0>, C4<0>, C4<0>; -L_0xa3af60 .delay (10000,10000,10000) L_0xa3af60/d; -L_0xa3b080/d .functor AND 1, L_0xa3b1c0, L_0xa3af60, C4<1>, C4<1>; -L_0xa3b080 .delay (20000,20000,20000) L_0xa3b080/d; -L_0xa3b260/d .functor XOR 1, L_0xa3bac0, L_0xa3acf0, C4<0>, C4<0>; -L_0xa3b260 .delay (40000,40000,40000) L_0xa3b260/d; -L_0xa3b350/d .functor XOR 1, L_0xa3b260, L_0xa3bd00, C4<0>, C4<0>; -L_0xa3b350 .delay (40000,40000,40000) L_0xa3b350/d; -L_0xa3b440/d .functor AND 1, L_0xa3bac0, L_0xa3acf0, C4<1>, C4<1>; -L_0xa3b440 .delay (20000,20000,20000) L_0xa3b440/d; -L_0xa3b5b0/d .functor AND 1, L_0xa3b260, L_0xa3bd00, C4<1>, C4<1>; -L_0xa3b5b0 .delay (20000,20000,20000) L_0xa3b5b0/d; -L_0xa3b6a0/d .functor OR 1, L_0xa3b440, L_0xa3b5b0, C4<0>, C4<0>; -L_0xa3b6a0 .delay (20000,20000,20000) L_0xa3b6a0/d; -v0xa33a20_0 .net "A", 0 0, L_0xa3bac0; 1 drivers -v0xa33ae0_0 .net "AandB", 0 0, L_0xa3b440; 1 drivers -v0xa33b80_0 .net "AddSubSLTSum", 0 0, L_0xa3b350; 1 drivers -v0xa33c20_0 .net "AxorB", 0 0, L_0xa3b260; 1 drivers -v0xa33ca0_0 .net "B", 0 0, L_0xa3bbd0; 1 drivers -v0xa33d50_0 .net "BornB", 0 0, L_0xa3acf0; 1 drivers -v0xa33e10_0 .net "CINandAxorB", 0 0, L_0xa3b5b0; 1 drivers -v0xa33e90_0 .alias "Command", 2 0, v0xa373b0_0; -v0xa33f10_0 .net *"_s3", 0 0, L_0xa3afe0; 1 drivers -v0xa33f90_0 .net *"_s5", 0 0, L_0xa3b1c0; 1 drivers -v0xa34030_0 .net "carryin", 0 0, L_0xa3bd00; 1 drivers -v0xa340d0_0 .net "carryout", 0 0, L_0xa3b6a0; 1 drivers -v0xa34170_0 .net "nB", 0 0, L_0xa3a820; 1 drivers -v0xa34220_0 .net "nCmd2", 0 0, L_0xa3af60; 1 drivers -v0xa34320_0 .net "subtract", 0 0, L_0xa3b080; 1 drivers -L_0xa3aec0 .part v0xa388d0_0, 0, 1; -L_0xa3afe0 .part v0xa388d0_0, 2, 1; -L_0xa3b1c0 .part v0xa388d0_0, 0, 1; -S_0xa33490 .scope module, "mux0" "TwoInMux" 3 105, 3 8, S_0xa333a0; - .timescale -9 -12; -L_0xa3aa10/d .functor NOT 1, L_0xa3aec0, C4<0>, C4<0>, C4<0>; -L_0xa3aa10 .delay (10000,10000,10000) L_0xa3aa10/d; -L_0xa3aad0/d .functor AND 1, L_0xa3bbd0, L_0xa3aa10, C4<1>, C4<1>; -L_0xa3aad0 .delay (20000,20000,20000) L_0xa3aad0/d; -L_0xa3abe0/d .functor AND 1, L_0xa3a820, L_0xa3aec0, C4<1>, C4<1>; -L_0xa3abe0 .delay (20000,20000,20000) L_0xa3abe0/d; -L_0xa3acf0/d .functor OR 1, L_0xa3aad0, L_0xa3abe0, C4<0>, C4<0>; -L_0xa3acf0 .delay (20000,20000,20000) L_0xa3acf0/d; -v0xa33580_0 .net "S", 0 0, L_0xa3aec0; 1 drivers -v0xa33640_0 .alias "in0", 0 0, v0xa33ca0_0; -v0xa336e0_0 .alias "in1", 0 0, v0xa34170_0; -v0xa33780_0 .net "nS", 0 0, L_0xa3aa10; 1 drivers -v0xa33800_0 .net "out0", 0 0, L_0xa3aad0; 1 drivers -v0xa338a0_0 .net "out1", 0 0, L_0xa3abe0; 1 drivers -v0xa33980_0 .alias "outfinal", 0 0, v0xa33d50_0; -S_0xa32e10 .scope module, "setSLTres" "TwoInMux" 3 242, 3 8, S_0xa32ca0; - .timescale -9 -12; -L_0xa3b9c0/d .functor NOT 1, L_0xa3e280, C4<0>, C4<0>, C4<0>; -L_0xa3b9c0 .delay (10000,10000,10000) L_0xa3b9c0/d; -L_0xa3bed0/d .functor AND 1, L_0xa3c290, L_0xa3b9c0, C4<1>, C4<1>; -L_0xa3bed0 .delay (20000,20000,20000) L_0xa3bed0/d; -L_0xa3bf90/d .functor AND 1, C4<0>, L_0xa3e280, C4<1>, C4<1>; -L_0xa3bf90 .delay (20000,20000,20000) L_0xa3bf90/d; -L_0xa3c100/d .functor OR 1, L_0xa3bed0, L_0xa3bf90, C4<0>, C4<0>; -L_0xa3c100 .delay (20000,20000,20000) L_0xa3c100/d; -v0xa32f00_0 .alias "S", 0 0, v0xa378b0_0; -v0xa32fb0_0 .net "in0", 0 0, L_0xa3c290; 1 drivers -v0xa33030_0 .net "in1", 0 0, C4<0>; 1 drivers -v0xa330d0_0 .net "nS", 0 0, L_0xa3b9c0; 1 drivers -v0xa33180_0 .net "out0", 0 0, L_0xa3bed0; 1 drivers -v0xa33220_0 .net "out1", 0 0, L_0xa3bf90; 1 drivers -v0xa33300_0 .net "outfinal", 0 0, L_0xa3c100; 1 drivers -S_0xa31670 .scope generate, "addbits[3]" "addbits[3]" 3 239, 3 239, S_0xa31580; - .timescale -9 -12; -P_0xa31358 .param/l "i" 3 239, +C4<011>; -S_0xa31cb0 .scope module, "attempt" "MiddleAddSubSLT" 3 241, 3 89, S_0xa31670; - .timescale -9 -12; -L_0xa3c4e0/d .functor NOT 1, L_0xa3d6c0, C4<0>, C4<0>, C4<0>; -L_0xa3c4e0 .delay (10000,10000,10000) L_0xa3c4e0/d; -L_0xa3cc00/d .functor NOT 1, L_0xa3ccc0, C4<0>, C4<0>, C4<0>; -L_0xa3cc00 .delay (10000,10000,10000) L_0xa3cc00/d; -L_0xa3cd60/d .functor AND 1, L_0xa3cea0, L_0xa3cc00, C4<1>, C4<1>; -L_0xa3cd60 .delay (20000,20000,20000) L_0xa3cd60/d; -L_0xa3cf40/d .functor XOR 1, L_0xa3d910, L_0xa3c990, C4<0>, C4<0>; -L_0xa3cf40 .delay (40000,40000,40000) L_0xa3cf40/d; -L_0xa3d030/d .functor XOR 1, L_0xa3cf40, L_0xa3da60, C4<0>, C4<0>; -L_0xa3d030 .delay (40000,40000,40000) L_0xa3d030/d; -L_0xa3d120/d .functor AND 1, L_0xa3d910, L_0xa3c990, C4<1>, C4<1>; -L_0xa3d120 .delay (20000,20000,20000) L_0xa3d120/d; -L_0xa3d290/d .functor AND 1, L_0xa3cf40, L_0xa3da60, C4<1>, C4<1>; -L_0xa3d290 .delay (20000,20000,20000) L_0xa3d290/d; -L_0xa3d380/d .functor OR 1, L_0xa3d120, L_0xa3d290, C4<0>, C4<0>; -L_0xa3d380 .delay (20000,20000,20000) L_0xa3d380/d; -v0xa32330_0 .net "A", 0 0, L_0xa3d910; 1 drivers -v0xa323f0_0 .net "AandB", 0 0, L_0xa3d120; 1 drivers -v0xa32490_0 .net "AddSubSLTSum", 0 0, L_0xa3d030; 1 drivers -v0xa32530_0 .net "AxorB", 0 0, L_0xa3cf40; 1 drivers -v0xa325b0_0 .net "B", 0 0, L_0xa3d6c0; 1 drivers -v0xa32630_0 .net "BornB", 0 0, L_0xa3c990; 1 drivers -v0xa326f0_0 .net "CINandAxorB", 0 0, L_0xa3d290; 1 drivers -v0xa32770_0 .alias "Command", 2 0, v0xa373b0_0; -v0xa327f0_0 .net *"_s3", 0 0, L_0xa3ccc0; 1 drivers -v0xa32870_0 .net *"_s5", 0 0, L_0xa3cea0; 1 drivers -v0xa32910_0 .net "carryin", 0 0, L_0xa3da60; 1 drivers -v0xa329b0_0 .net "carryout", 0 0, L_0xa3d380; 1 drivers -v0xa32a50_0 .net "nB", 0 0, L_0xa3c4e0; 1 drivers -v0xa32b00_0 .net "nCmd2", 0 0, L_0xa3cc00; 1 drivers -v0xa32c00_0 .net "subtract", 0 0, L_0xa3cd60; 1 drivers -L_0xa3cb60 .part v0xa388d0_0, 0, 1; -L_0xa3ccc0 .part v0xa388d0_0, 2, 1; -L_0xa3cea0 .part v0xa388d0_0, 0, 1; -S_0xa31da0 .scope module, "mux0" "TwoInMux" 3 105, 3 8, S_0xa31cb0; - .timescale -9 -12; -L_0xa3c6b0/d .functor NOT 1, L_0xa3cb60, C4<0>, C4<0>, C4<0>; -L_0xa3c6b0 .delay (10000,10000,10000) L_0xa3c6b0/d; -L_0xa3c770/d .functor AND 1, L_0xa3d6c0, L_0xa3c6b0, C4<1>, C4<1>; -L_0xa3c770 .delay (20000,20000,20000) L_0xa3c770/d; -L_0xa3c880/d .functor AND 1, L_0xa3c4e0, L_0xa3cb60, C4<1>, C4<1>; -L_0xa3c880 .delay (20000,20000,20000) L_0xa3c880/d; -L_0xa3c990/d .functor OR 1, L_0xa3c770, L_0xa3c880, C4<0>, C4<0>; -L_0xa3c990 .delay (20000,20000,20000) L_0xa3c990/d; -v0xa31e90_0 .net "S", 0 0, L_0xa3cb60; 1 drivers -v0xa31f50_0 .alias "in0", 0 0, v0xa325b0_0; -v0xa31ff0_0 .alias "in1", 0 0, v0xa32a50_0; -v0xa32090_0 .net "nS", 0 0, L_0xa3c6b0; 1 drivers -v0xa32110_0 .net "out0", 0 0, L_0xa3c770; 1 drivers -v0xa321b0_0 .net "out1", 0 0, L_0xa3c880; 1 drivers -v0xa32290_0 .alias "outfinal", 0 0, v0xa32630_0; -S_0xa31760 .scope module, "setSLTres" "TwoInMux" 3 242, 3 8, S_0xa31670; - .timescale -9 -12; -L_0xa3d9b0/d .functor NOT 1, L_0xa3e280, C4<0>, C4<0>, C4<0>; -L_0xa3d9b0 .delay (10000,10000,10000) L_0xa3d9b0/d; -L_0xa3dbc0/d .functor AND 1, L_0xa3df30, L_0xa3d9b0, C4<1>, C4<1>; -L_0xa3dbc0 .delay (20000,20000,20000) L_0xa3dbc0/d; -L_0xa3dcb0/d .functor AND 1, C4<0>, L_0xa3e280, C4<1>, C4<1>; -L_0xa3dcb0 .delay (20000,20000,20000) L_0xa3dcb0/d; -L_0xa3dd50/d .functor OR 1, L_0xa3dbc0, L_0xa3dcb0, C4<0>, C4<0>; -L_0xa3dd50 .delay (20000,20000,20000) L_0xa3dd50/d; -v0xa31850_0 .alias "S", 0 0, v0xa378b0_0; -v0xa318d0_0 .net "in0", 0 0, L_0xa3df30; 1 drivers -v0xa31970_0 .net "in1", 0 0, C4<0>; 1 drivers -v0xa31a10_0 .net "nS", 0 0, L_0xa3d9b0; 1 drivers -v0xa31a90_0 .net "out0", 0 0, L_0xa3dbc0; 1 drivers -v0xa31b30_0 .net "out1", 0 0, L_0xa3dcb0; 1 drivers -v0xa31c10_0 .net "outfinal", 0 0, L_0xa3dd50; 1 drivers -S_0xa28d90 .scope module, "test" "SLT32" 2 148, 3 273, S_0x96f1c0; - .timescale -9 -12; -P_0xa28e88 .param/l "size" 3 305, +C4<0100>; -L_0xa44d20/d .functor NOT 1, L_0xa47fa0, C4<0>, C4<0>, C4<0>; -L_0xa44d20 .delay (10000,10000,10000) L_0xa44d20/d; -L_0xa47e00/d .functor AND 1, L_0xa481b0, L_0xa48250, L_0xa44d20, C4<1>; -L_0xa47e00 .delay (20000,20000,20000) L_0xa47e00/d; -L_0xa371a0/d .functor OR 1, L_0xa4a020, C4<0>, C4<0>, C4<0>; -L_0xa371a0 .delay (20000,20000,20000) L_0xa371a0/d; -L_0xa4a230/d .functor XOR 1, RS_0x7ffb33a703c8, L_0xa4a2d0, C4<0>, C4<0>; -L_0xa4a230 .delay (40000,40000,40000) L_0xa4a230/d; -L_0xa49eb0/d .functor NOT 1, RS_0x7ffb33a70488, C4<0>, C4<0>, C4<0>; -L_0xa49eb0 .delay (10000,10000,10000) L_0xa49eb0/d; -L_0xa49fc0/d .functor NOT 1, L_0xa4a570, C4<0>, C4<0>, C4<0>; -L_0xa49fc0 .delay (10000,10000,10000) L_0xa49fc0/d; -L_0xa4a610/d .functor AND 1, L_0xa49eb0, L_0xa4a770, C4<1>, C4<1>; -L_0xa4a610 .delay (20000,20000,20000) L_0xa4a610/d; -L_0xa4a370/d .functor AND 1, RS_0x7ffb33a70488, L_0xa49fc0, C4<1>, C4<1>; -L_0xa4a370 .delay (20000,20000,20000) L_0xa4a370/d; -L_0xa4a9a0/d .functor AND 1, L_0xa4a610, L_0xa47e00, C4<1>, C4<1>; -L_0xa4a9a0 .delay (20000,20000,20000) L_0xa4a9a0/d; -L_0xa4aaa0/d .functor AND 1, L_0xa4a370, L_0xa47e00, C4<1>, C4<1>; -L_0xa4aaa0 .delay (20000,20000,20000) L_0xa4aaa0/d; -L_0xa4abf0/d .functor OR 1, L_0xa4a9a0, L_0xa4aaa0, C4<0>, C4<0>; -L_0xa4abf0 .delay (20000,20000,20000) L_0xa4abf0/d; -v0xa302b0_0 .alias "A", 3 0, v0xa37070_0; -RS_0x7ffb33a74b68 .resolv tri, L_0xa42980, L_0xa44c80, L_0xa47550, L_0xa49c10; -v0xa30350_0 .net8 "AddSubSLTSum", 3 0, RS_0x7ffb33a74b68; 4 drivers -v0xa303f0_0 .alias "B", 3 0, v0xa37220_0; -RS_0x7ffb33a74b98 .resolv tri, L_0xa420d0, L_0xa44430, L_0xa46a00, L_0xa493c0; -v0xa30470_0 .net8 "CarryoutWire", 3 0, RS_0x7ffb33a74b98; 4 drivers -v0xa30520_0 .alias "Command", 2 0, v0xa373b0_0; -RS_0x7ffb33a74bc8 .resolv tri, L_0xa41fe0, L_0xa44340, L_0xa46910, L_0xa492d0; -v0xa305a0_0 .net8 "NewVal", 3 0, RS_0x7ffb33a74bc8; 4 drivers -v0xa30640_0 .net "Res0OF1", 0 0, L_0xa4a370; 1 drivers -v0xa306e0_0 .net "Res1OF0", 0 0, L_0xa4a610; 1 drivers -v0xa30780_0 .alias "SLTSum", 3 0, v0xa38a50_0; -v0xa30800_0 .alias "SLTflag", 0 0, v0xa38ad0_0; -v0xa30880_0 .net "SLTflag0", 0 0, L_0xa4a9a0; 1 drivers -v0xa30920_0 .net "SLTflag1", 0 0, L_0xa4aaa0; 1 drivers -v0xa309c0_0 .net "SLTon", 0 0, L_0xa47e00; 1 drivers -v0xa30a40_0 .net *"_s49", 0 0, L_0xa47fa0; 1 drivers -v0xa30b60_0 .net *"_s51", 0 0, L_0xa481b0; 1 drivers -v0xa30c00_0 .net *"_s53", 0 0, L_0xa48250; 1 drivers -v0xa30ac0_0 .net *"_s73", 0 0, L_0xa4a020; 1 drivers -v0xa30d50_0 .net/s *"_s74", 0 0, C4<0>; 1 drivers -v0xa30e70_0 .net *"_s77", 0 0, L_0xa4a2d0; 1 drivers -v0xa30ef0_0 .net *"_s79", 0 0, L_0xa4a570; 1 drivers -v0xa30dd0_0 .net *"_s81", 0 0, L_0xa4a770; 1 drivers -v0xa31020_0 .alias "carryin", 3 0, v0xa37df0_0; -v0xa30f70_0 .alias "carryout", 0 0, v0xa38c80_0; -v0xa31160_0 .net "nAddSubSLTSum", 0 0, L_0xa49fc0; 1 drivers -v0xa310a0_0 .net "nCmd2", 0 0, L_0xa44d20; 1 drivers -v0xa312b0_0 .net "nOF", 0 0, L_0xa49eb0; 1 drivers -v0xa311e0_0 .alias "overflow", 0 0, v0xa38d00_0; -v0xa31410_0 .alias "subtract", 3 0, v0xa38e00_0; -L_0xa41fe0 .part/pv L_0xa41b30, 1, 1, 4; -L_0xa420d0 .part/pv L_0xa41e80, 1, 1, 4; -L_0xa421c0 .part/pv L_0xa41860, 1, 1, 4; -L_0xa422b0 .part v0xa38650_0, 1, 1; -L_0xa42350 .part v0xa38850_0, 1, 1; -L_0xa42480 .part RS_0x7ffb33a74b98, 0, 1; -L_0xa42980 .part/pv L_0xa42840, 1, 1, 4; -L_0xa42a20 .part RS_0x7ffb33a74bc8, 1, 1; -L_0xa43020 .part/pv L_0xa42ee0, 1, 1, 4; -L_0xa43150 .part RS_0x7ffb33a74b68, 1, 1; -L_0xa432a0 .part RS_0x7ffb33a74b68, 1, 1; -L_0xa44340 .part/pv L_0xa43e90, 2, 1, 4; -L_0xa44430 .part/pv L_0xa441e0, 2, 1, 4; -L_0xa44520 .part/pv L_0xa43bc0, 2, 1, 4; -L_0xa44610 .part v0xa38650_0, 2, 1; -L_0xa446b0 .part v0xa38850_0, 2, 1; -L_0xa44870 .part RS_0x7ffb33a74b98, 1, 1; -L_0xa44c80 .part/pv L_0xa44b40, 2, 1, 4; -L_0xa44e50 .part RS_0x7ffb33a74bc8, 2, 1; -L_0xa45330 .part/pv L_0xa451f0, 2, 1, 4; -L_0xa44db0 .part RS_0x7ffb33a74b68, 2, 1; -L_0xa454d0 .part RS_0x7ffb33a74b68, 2, 1; -L_0xa46910 .part/pv L_0xa2c640, 3, 1, 4; -L_0xa46a00 .part/pv L_0xa467d0, 3, 1, 4; -L_0xa455c0 .part/pv L_0xa3bb60, 3, 1, 4; -L_0xa46c10 .part v0xa38650_0, 3, 1; -L_0xa46af0 .part v0xa38850_0, 3, 1; -L_0xa372a0 .part RS_0x7ffb33a74b98, 2, 1; -L_0xa47550 .part/pv L_0xa47410, 3, 1, 4; -L_0xa475f0 .part RS_0x7ffb33a74bc8, 3, 1; -L_0xa47b60 .part/pv L_0xa47a20, 3, 1, 4; -L_0xa47c00 .part RS_0x7ffb33a74b68, 3, 1; -L_0xa476e0 .part RS_0x7ffb33a74b68, 3, 1; -L_0xa47fa0 .part v0xa388d0_0, 2, 1; -L_0xa481b0 .part v0xa388d0_0, 0, 1; -L_0xa48250 .part v0xa388d0_0, 1, 1; -L_0xa492d0 .part/pv L_0xa48e20, 0, 1, 4; -L_0xa493c0 .part/pv L_0xa49170, 0, 1, 4; -L_0xa48340 .part/pv L_0xa48b50, 0, 1, 4; -L_0xa495f0 .part v0xa38650_0, 0, 1; -L_0xa494b0 .part v0xa38850_0, 0, 1; -L_0xa497e0 .part RS_0x7ffb33a704b8, 0, 1; -L_0xa49c10 .part/pv L_0xa49ad0, 0, 1, 4; -L_0xa49cb0 .part RS_0x7ffb33a74bc8, 0, 1; -L_0xa4a020 .part RS_0x7ffb33a74b98, 3, 1; -L_0xa4a2d0 .part RS_0x7ffb33a74b98, 2, 1; -L_0xa4a570 .part RS_0x7ffb33a74b68, 3, 1; -L_0xa4a770 .part RS_0x7ffb33a74b68, 3, 1; -L_0xa4b110 .part/pv L_0xa4afb0, 0, 1, 4; -L_0xa4b1b0 .part RS_0x7ffb33a74b68, 0, 1; -S_0xa2f290 .scope module, "attempt2" "MiddleAddSubSLT" 3 300, 3 89, S_0xa28d90; - .timescale -9 -12; -L_0xa48040/d .functor NOT 1, L_0xa494b0, C4<0>, C4<0>, C4<0>; -L_0xa48040 .delay (10000,10000,10000) L_0xa48040/d; -L_0xa489f0/d .functor NOT 1, L_0xa48ab0, C4<0>, C4<0>, C4<0>; -L_0xa489f0 .delay (10000,10000,10000) L_0xa489f0/d; -L_0xa48b50/d .functor AND 1, L_0xa48c90, L_0xa489f0, C4<1>, C4<1>; -L_0xa48b50 .delay (20000,20000,20000) L_0xa48b50/d; -L_0xa48d30/d .functor XOR 1, L_0xa495f0, L_0xa48780, C4<0>, C4<0>; -L_0xa48d30 .delay (40000,40000,40000) L_0xa48d30/d; -L_0xa48e20/d .functor XOR 1, L_0xa48d30, L_0xa497e0, C4<0>, C4<0>; -L_0xa48e20 .delay (40000,40000,40000) L_0xa48e20/d; -L_0xa48f10/d .functor AND 1, L_0xa495f0, L_0xa48780, C4<1>, C4<1>; -L_0xa48f10 .delay (20000,20000,20000) L_0xa48f10/d; -L_0xa49080/d .functor AND 1, L_0xa48d30, L_0xa497e0, C4<1>, C4<1>; -L_0xa49080 .delay (20000,20000,20000) L_0xa49080/d; -L_0xa49170/d .functor OR 1, L_0xa48f10, L_0xa49080, C4<0>, C4<0>; -L_0xa49170 .delay (20000,20000,20000) L_0xa49170/d; -v0xa2f910_0 .net "A", 0 0, L_0xa495f0; 1 drivers -v0xa2f9d0_0 .net "AandB", 0 0, L_0xa48f10; 1 drivers -v0xa2fa70_0 .net "AddSubSLTSum", 0 0, L_0xa48e20; 1 drivers -v0xa2fb10_0 .net "AxorB", 0 0, L_0xa48d30; 1 drivers -v0xa2fb90_0 .net "B", 0 0, L_0xa494b0; 1 drivers -v0xa2fc40_0 .net "BornB", 0 0, L_0xa48780; 1 drivers -v0xa2fd00_0 .net "CINandAxorB", 0 0, L_0xa49080; 1 drivers -v0xa2fd80_0 .alias "Command", 2 0, v0xa373b0_0; -v0xa2fe00_0 .net *"_s3", 0 0, L_0xa48ab0; 1 drivers -v0xa2fe80_0 .net *"_s5", 0 0, L_0xa48c90; 1 drivers -v0xa2ff20_0 .net "carryin", 0 0, L_0xa497e0; 1 drivers -v0xa2ffc0_0 .net "carryout", 0 0, L_0xa49170; 1 drivers -v0xa30060_0 .net "nB", 0 0, L_0xa48040; 1 drivers -v0xa30110_0 .net "nCmd2", 0 0, L_0xa489f0; 1 drivers -v0xa30210_0 .net "subtract", 0 0, L_0xa48b50; 1 drivers -L_0xa48950 .part v0xa388d0_0, 0, 1; -L_0xa48ab0 .part v0xa388d0_0, 2, 1; -L_0xa48c90 .part v0xa388d0_0, 0, 1; -S_0xa2f380 .scope module, "mux0" "TwoInMux" 3 105, 3 8, S_0xa2f290; - .timescale -9 -12; -L_0xa48500/d .functor NOT 1, L_0xa48950, C4<0>, C4<0>, C4<0>; -L_0xa48500 .delay (10000,10000,10000) L_0xa48500/d; -L_0xa485a0/d .functor AND 1, L_0xa494b0, L_0xa48500, C4<1>, C4<1>; -L_0xa485a0 .delay (20000,20000,20000) L_0xa485a0/d; -L_0xa48690/d .functor AND 1, L_0xa48040, L_0xa48950, C4<1>, C4<1>; -L_0xa48690 .delay (20000,20000,20000) L_0xa48690/d; -L_0xa48780/d .functor OR 1, L_0xa485a0, L_0xa48690, C4<0>, C4<0>; -L_0xa48780 .delay (20000,20000,20000) L_0xa48780/d; -v0xa2f470_0 .net "S", 0 0, L_0xa48950; 1 drivers -v0xa2f530_0 .alias "in0", 0 0, v0xa2fb90_0; -v0xa2f5d0_0 .alias "in1", 0 0, v0xa30060_0; -v0xa2f670_0 .net "nS", 0 0, L_0xa48500; 1 drivers -v0xa2f6f0_0 .net "out0", 0 0, L_0xa485a0; 1 drivers -v0xa2f790_0 .net "out1", 0 0, L_0xa48690; 1 drivers -v0xa2f870_0 .alias "outfinal", 0 0, v0xa2fc40_0; -S_0xa2ed20 .scope module, "setSLTres" "TwoInMux" 3 301, 3 8, S_0xa28d90; - .timescale -9 -12; -L_0xa49690/d .functor NOT 1, L_0xa47e00, C4<0>, C4<0>, C4<0>; -L_0xa49690 .delay (10000,10000,10000) L_0xa49690/d; -L_0xa49730/d .functor AND 1, L_0xa49cb0, L_0xa49690, C4<1>, C4<1>; -L_0xa49730 .delay (20000,20000,20000) L_0xa49730/d; -L_0xa49a30/d .functor AND 1, C4<0>, L_0xa47e00, C4<1>, C4<1>; -L_0xa49a30 .delay (20000,20000,20000) L_0xa49a30/d; -L_0xa49ad0/d .functor OR 1, L_0xa49730, L_0xa49a30, C4<0>, C4<0>; -L_0xa49ad0 .delay (20000,20000,20000) L_0xa49ad0/d; -v0xa2ee10_0 .alias "S", 0 0, v0xa309c0_0; -v0xa2eeb0_0 .net "in0", 0 0, L_0xa49cb0; 1 drivers -v0xa2ef50_0 .net "in1", 0 0, C4<0>; 1 drivers -v0xa2eff0_0 .net "nS", 0 0, L_0xa49690; 1 drivers -v0xa2f070_0 .net "out0", 0 0, L_0xa49730; 1 drivers -v0xa2f110_0 .net "out1", 0 0, L_0xa49a30; 1 drivers -v0xa2f1f0_0 .net "outfinal", 0 0, L_0xa49ad0; 1 drivers -S_0xa2e7e0 .scope module, "FinalSLT" "TwoInMux" 3 328, 3 8, S_0xa28d90; - .timescale -9 -12; -L_0xa4ad20/d .functor NOT 1, RS_0x7ffb33a70188, C4<0>, C4<0>, C4<0>; -L_0xa4ad20 .delay (10000,10000,10000) L_0xa4ad20/d; -L_0xa4ae00/d .functor AND 1, L_0xa4b1b0, L_0xa4ad20, C4<1>, C4<1>; -L_0xa4ae00 .delay (20000,20000,20000) L_0xa4ae00/d; -L_0xa4af10/d .functor AND 1, RS_0x7ffb33a70188, RS_0x7ffb33a70188, C4<1>, C4<1>; -L_0xa4af10 .delay (20000,20000,20000) L_0xa4af10/d; -L_0xa4afb0/d .functor OR 1, L_0xa4ae00, L_0xa4af10, C4<0>, C4<0>; -L_0xa4afb0 .delay (20000,20000,20000) L_0xa4afb0/d; -v0xa2e8d0_0 .alias "S", 0 0, v0xa38ad0_0; -v0xa2e970_0 .net "in0", 0 0, L_0xa4b1b0; 1 drivers -v0xa2ea10_0 .alias "in1", 0 0, v0xa38ad0_0; -v0xa2ea90_0 .net "nS", 0 0, L_0xa4ad20; 1 drivers -v0xa2eb40_0 .net "out0", 0 0, L_0xa4ae00; 1 drivers -v0xa2ebe0_0 .net "out1", 0 0, L_0xa4af10; 1 drivers -v0xa2ec80_0 .net "outfinal", 0 0, L_0xa4afb0; 1 drivers -S_0xa2cab0 .scope generate, "addbits[1]" "addbits[1]" 3 307, 3 307, S_0xa28d90; - .timescale -9 -12; -P_0xa2cba8 .param/l "i" 3 307, +C4<01>; -S_0xa2d7c0 .scope module, "attempt" "MiddleAddSubSLT" 3 309, 3 89, S_0xa2cab0; - .timescale -9 -12; -L_0xa41010/d .functor NOT 1, L_0xa42350, C4<0>, C4<0>, C4<0>; -L_0xa41010 .delay (10000,10000,10000) L_0xa41010/d; -L_0xa41700/d .functor NOT 1, L_0xa417c0, C4<0>, C4<0>, C4<0>; -L_0xa41700 .delay (10000,10000,10000) L_0xa41700/d; -L_0xa41860/d .functor AND 1, L_0xa419a0, L_0xa41700, C4<1>, C4<1>; -L_0xa41860 .delay (20000,20000,20000) L_0xa41860/d; -L_0xa41a40/d .functor XOR 1, L_0xa422b0, L_0xa41490, C4<0>, C4<0>; -L_0xa41a40 .delay (40000,40000,40000) L_0xa41a40/d; -L_0xa41b30/d .functor XOR 1, L_0xa41a40, L_0xa42480, C4<0>, C4<0>; -L_0xa41b30 .delay (40000,40000,40000) L_0xa41b30/d; -L_0xa41c20/d .functor AND 1, L_0xa422b0, L_0xa41490, C4<1>, C4<1>; -L_0xa41c20 .delay (20000,20000,20000) L_0xa41c20/d; -L_0xa41d90/d .functor AND 1, L_0xa41a40, L_0xa42480, C4<1>, C4<1>; -L_0xa41d90 .delay (20000,20000,20000) L_0xa41d90/d; -L_0xa41e80/d .functor OR 1, L_0xa41c20, L_0xa41d90, C4<0>, C4<0>; -L_0xa41e80 .delay (20000,20000,20000) L_0xa41e80/d; -v0xa2de40_0 .net "A", 0 0, L_0xa422b0; 1 drivers -v0xa2df00_0 .net "AandB", 0 0, L_0xa41c20; 1 drivers -v0xa2dfa0_0 .net "AddSubSLTSum", 0 0, L_0xa41b30; 1 drivers -v0xa2e040_0 .net "AxorB", 0 0, L_0xa41a40; 1 drivers -v0xa2e0c0_0 .net "B", 0 0, L_0xa42350; 1 drivers -v0xa2e170_0 .net "BornB", 0 0, L_0xa41490; 1 drivers -v0xa2e230_0 .net "CINandAxorB", 0 0, L_0xa41d90; 1 drivers -v0xa2e2b0_0 .alias "Command", 2 0, v0xa373b0_0; -v0xa2e330_0 .net *"_s3", 0 0, L_0xa417c0; 1 drivers -v0xa2e3b0_0 .net *"_s5", 0 0, L_0xa419a0; 1 drivers -v0xa2e450_0 .net "carryin", 0 0, L_0xa42480; 1 drivers -v0xa2e4f0_0 .net "carryout", 0 0, L_0xa41e80; 1 drivers -v0xa2e590_0 .net "nB", 0 0, L_0xa41010; 1 drivers -v0xa2e640_0 .net "nCmd2", 0 0, L_0xa41700; 1 drivers -v0xa2e740_0 .net "subtract", 0 0, L_0xa41860; 1 drivers -L_0xa41660 .part v0xa388d0_0, 0, 1; -L_0xa417c0 .part v0xa388d0_0, 2, 1; -L_0xa419a0 .part v0xa388d0_0, 0, 1; -S_0xa2d8b0 .scope module, "mux0" "TwoInMux" 3 105, 3 8, S_0xa2d7c0; - .timescale -9 -12; -L_0xa411b0/d .functor NOT 1, L_0xa41660, C4<0>, C4<0>, C4<0>; -L_0xa411b0 .delay (10000,10000,10000) L_0xa411b0/d; -L_0xa41270/d .functor AND 1, L_0xa42350, L_0xa411b0, C4<1>, C4<1>; -L_0xa41270 .delay (20000,20000,20000) L_0xa41270/d; -L_0xa41380/d .functor AND 1, L_0xa41010, L_0xa41660, C4<1>, C4<1>; -L_0xa41380 .delay (20000,20000,20000) L_0xa41380/d; -L_0xa41490/d .functor OR 1, L_0xa41270, L_0xa41380, C4<0>, C4<0>; -L_0xa41490 .delay (20000,20000,20000) L_0xa41490/d; -v0xa2d9a0_0 .net "S", 0 0, L_0xa41660; 1 drivers -v0xa2da60_0 .alias "in0", 0 0, v0xa2e0c0_0; -v0xa2db00_0 .alias "in1", 0 0, v0xa2e590_0; -v0xa2dba0_0 .net "nS", 0 0, L_0xa411b0; 1 drivers -v0xa2dc20_0 .net "out0", 0 0, L_0xa41270; 1 drivers -v0xa2dcc0_0 .net "out1", 0 0, L_0xa41380; 1 drivers -v0xa2dda0_0 .alias "outfinal", 0 0, v0xa2e170_0; -S_0xa2d250 .scope module, "setSLTres2" "TwoInMux" 3 310, 3 8, S_0xa2cab0; - .timescale -9 -12; -L_0xa42520/d .functor NOT 1, L_0xa47e00, C4<0>, C4<0>, C4<0>; -L_0xa42520 .delay (10000,10000,10000) L_0xa42520/d; -L_0xa42690/d .functor AND 1, L_0xa42a20, L_0xa42520, C4<1>, C4<1>; -L_0xa42690 .delay (20000,20000,20000) L_0xa42690/d; -L_0xa427a0/d .functor AND 1, C4<0>, L_0xa47e00, C4<1>, C4<1>; -L_0xa427a0 .delay (20000,20000,20000) L_0xa427a0/d; -L_0xa42840/d .functor OR 1, L_0xa42690, L_0xa427a0, C4<0>, C4<0>; -L_0xa42840 .delay (20000,20000,20000) L_0xa42840/d; -v0xa2d340_0 .alias "S", 0 0, v0xa309c0_0; -v0xa2d3e0_0 .net "in0", 0 0, L_0xa42a20; 1 drivers -v0xa2d480_0 .net "in1", 0 0, C4<0>; 1 drivers -v0xa2d520_0 .net "nS", 0 0, L_0xa42520; 1 drivers -v0xa2d5a0_0 .net "out0", 0 0, L_0xa42690; 1 drivers -v0xa2d640_0 .net "out1", 0 0, L_0xa427a0; 1 drivers -v0xa2d720_0 .net "outfinal", 0 0, L_0xa42840; 1 drivers -S_0xa2cc40 .scope module, "setSLTres3" "TwoInMux" 3 311, 3 8, S_0xa2cab0; - .timescale -9 -12; -L_0xa42c40/d .functor NOT 1, L_0xa47e00, C4<0>, C4<0>, C4<0>; -L_0xa42c40 .delay (10000,10000,10000) L_0xa42c40/d; -L_0xa42d30/d .functor AND 1, L_0xa43150, L_0xa42c40, C4<1>, C4<1>; -L_0xa42d30 .delay (20000,20000,20000) L_0xa42d30/d; -L_0xa42e40/d .functor AND 1, L_0xa432a0, L_0xa47e00, C4<1>, C4<1>; -L_0xa42e40 .delay (20000,20000,20000) L_0xa42e40/d; -L_0xa42ee0/d .functor OR 1, L_0xa42d30, L_0xa42e40, C4<0>, C4<0>; -L_0xa42ee0 .delay (20000,20000,20000) L_0xa42ee0/d; -v0xa2cd30_0 .alias "S", 0 0, v0xa309c0_0; -v0xa2ce40_0 .net "in0", 0 0, L_0xa43150; 1 drivers -v0xa2cee0_0 .net "in1", 0 0, L_0xa432a0; 1 drivers -v0xa2cf80_0 .net "nS", 0 0, L_0xa42c40; 1 drivers -v0xa2d030_0 .net "out0", 0 0, L_0xa42d30; 1 drivers -v0xa2d0d0_0 .net "out1", 0 0, L_0xa42e40; 1 drivers -v0xa2d1b0_0 .net "outfinal", 0 0, L_0xa42ee0; 1 drivers -S_0xa2ac30 .scope generate, "addbits[2]" "addbits[2]" 3 307, 3 307, S_0xa28d90; - .timescale -9 -12; -P_0xa2a598 .param/l "i" 3 307, +C4<010>; -S_0xa2b860 .scope module, "attempt" "MiddleAddSubSLT" 3 309, 3 89, S_0xa2ac30; - .timescale -9 -12; -L_0xa43340/d .functor NOT 1, L_0xa446b0, C4<0>, C4<0>, C4<0>; -L_0xa43340 .delay (10000,10000,10000) L_0xa43340/d; -L_0xa43a60/d .functor NOT 1, L_0xa43b20, C4<0>, C4<0>, C4<0>; -L_0xa43a60 .delay (10000,10000,10000) L_0xa43a60/d; -L_0xa43bc0/d .functor AND 1, L_0xa43d00, L_0xa43a60, C4<1>, C4<1>; -L_0xa43bc0 .delay (20000,20000,20000) L_0xa43bc0/d; -L_0xa43da0/d .functor XOR 1, L_0xa44610, L_0xa437f0, C4<0>, C4<0>; -L_0xa43da0 .delay (40000,40000,40000) L_0xa43da0/d; -L_0xa43e90/d .functor XOR 1, L_0xa43da0, L_0xa44870, C4<0>, C4<0>; -L_0xa43e90 .delay (40000,40000,40000) L_0xa43e90/d; -L_0xa43f80/d .functor AND 1, L_0xa44610, L_0xa437f0, C4<1>, C4<1>; -L_0xa43f80 .delay (20000,20000,20000) L_0xa43f80/d; -L_0xa440f0/d .functor AND 1, L_0xa43da0, L_0xa44870, C4<1>, C4<1>; -L_0xa440f0 .delay (20000,20000,20000) L_0xa440f0/d; -L_0xa441e0/d .functor OR 1, L_0xa43f80, L_0xa440f0, C4<0>, C4<0>; -L_0xa441e0 .delay (20000,20000,20000) L_0xa441e0/d; -v0xa2bee0_0 .net "A", 0 0, L_0xa44610; 1 drivers -v0xa2bfa0_0 .net "AandB", 0 0, L_0xa43f80; 1 drivers -v0xa2c040_0 .net "AddSubSLTSum", 0 0, L_0xa43e90; 1 drivers -v0xa2c0e0_0 .net "AxorB", 0 0, L_0xa43da0; 1 drivers -v0xa2c160_0 .net "B", 0 0, L_0xa446b0; 1 drivers -v0xa2c210_0 .net "BornB", 0 0, L_0xa437f0; 1 drivers -v0xa2c2d0_0 .net "CINandAxorB", 0 0, L_0xa440f0; 1 drivers -v0xa2c350_0 .alias "Command", 2 0, v0xa373b0_0; -v0xa1aac0_0 .net *"_s3", 0 0, L_0xa43b20; 1 drivers -v0xa1ab40_0 .net *"_s5", 0 0, L_0xa43d00; 1 drivers -v0xa1abe0_0 .net "carryin", 0 0, L_0xa44870; 1 drivers -v0xa2c830_0 .net "carryout", 0 0, L_0xa441e0; 1 drivers -v0xa2c8b0_0 .net "nB", 0 0, L_0xa43340; 1 drivers -v0xa2c930_0 .net "nCmd2", 0 0, L_0xa43a60; 1 drivers -v0xa2ca30_0 .net "subtract", 0 0, L_0xa43bc0; 1 drivers -L_0xa439c0 .part v0xa388d0_0, 0, 1; -L_0xa43b20 .part v0xa388d0_0, 2, 1; -L_0xa43d00 .part v0xa388d0_0, 0, 1; -S_0xa2b950 .scope module, "mux0" "TwoInMux" 3 105, 3 8, S_0xa2b860; - .timescale -9 -12; -L_0xa43510/d .functor NOT 1, L_0xa439c0, C4<0>, C4<0>, C4<0>; -L_0xa43510 .delay (10000,10000,10000) L_0xa43510/d; -L_0xa435d0/d .functor AND 1, L_0xa446b0, L_0xa43510, C4<1>, C4<1>; -L_0xa435d0 .delay (20000,20000,20000) L_0xa435d0/d; -L_0xa436e0/d .functor AND 1, L_0xa43340, L_0xa439c0, C4<1>, C4<1>; -L_0xa436e0 .delay (20000,20000,20000) L_0xa436e0/d; -L_0xa437f0/d .functor OR 1, L_0xa435d0, L_0xa436e0, C4<0>, C4<0>; -L_0xa437f0 .delay (20000,20000,20000) L_0xa437f0/d; -v0xa2ba40_0 .net "S", 0 0, L_0xa439c0; 1 drivers -v0xa2bb00_0 .alias "in0", 0 0, v0xa2c160_0; -v0xa2bba0_0 .alias "in1", 0 0, v0xa2c8b0_0; -v0xa2bc40_0 .net "nS", 0 0, L_0xa43510; 1 drivers -v0xa2bcc0_0 .net "out0", 0 0, L_0xa435d0; 1 drivers -v0xa2bd60_0 .net "out1", 0 0, L_0xa436e0; 1 drivers -v0xa2be40_0 .alias "outfinal", 0 0, v0xa2c210_0; -S_0xa2b2f0 .scope module, "setSLTres2" "TwoInMux" 3 310, 3 8, S_0xa2ac30; - .timescale -9 -12; -L_0xa43240/d .functor NOT 1, L_0xa47e00, C4<0>, C4<0>, C4<0>; -L_0xa43240 .delay (10000,10000,10000) L_0xa43240/d; -L_0xa449e0/d .functor AND 1, L_0xa44e50, L_0xa43240, C4<1>, C4<1>; -L_0xa449e0 .delay (20000,20000,20000) L_0xa449e0/d; -L_0xa44aa0/d .functor AND 1, C4<0>, L_0xa47e00, C4<1>, C4<1>; -L_0xa44aa0 .delay (20000,20000,20000) L_0xa44aa0/d; -L_0xa44b40/d .functor OR 1, L_0xa449e0, L_0xa44aa0, C4<0>, C4<0>; -L_0xa44b40 .delay (20000,20000,20000) L_0xa44b40/d; -v0xa2b3e0_0 .alias "S", 0 0, v0xa309c0_0; -v0xa2b480_0 .net "in0", 0 0, L_0xa44e50; 1 drivers -v0xa2b520_0 .net "in1", 0 0, C4<0>; 1 drivers -v0xa2b5c0_0 .net "nS", 0 0, L_0xa43240; 1 drivers -v0xa2b640_0 .net "out0", 0 0, L_0xa449e0; 1 drivers -v0xa2b6e0_0 .net "out1", 0 0, L_0xa44aa0; 1 drivers -v0xa2b7c0_0 .net "outfinal", 0 0, L_0xa44b40; 1 drivers -S_0xa2ada0 .scope module, "setSLTres3" "TwoInMux" 3 311, 3 8, S_0xa2ac30; - .timescale -9 -12; -L_0xa44f30/d .functor NOT 1, L_0xa47e00, C4<0>, C4<0>, C4<0>; -L_0xa44f30 .delay (10000,10000,10000) L_0xa44f30/d; -L_0xa45040/d .functor AND 1, L_0xa44db0, L_0xa44f30, C4<1>, C4<1>; -L_0xa45040 .delay (20000,20000,20000) L_0xa45040/d; -L_0xa45150/d .functor AND 1, L_0xa454d0, L_0xa47e00, C4<1>, C4<1>; -L_0xa45150 .delay (20000,20000,20000) L_0xa45150/d; -L_0xa451f0/d .functor OR 1, L_0xa45040, L_0xa45150, C4<0>, C4<0>; -L_0xa451f0 .delay (20000,20000,20000) L_0xa451f0/d; -v0xa2ae90_0 .alias "S", 0 0, v0xa309c0_0; -v0xa2af10_0 .net "in0", 0 0, L_0xa44db0; 1 drivers -v0xa2afb0_0 .net "in1", 0 0, L_0xa454d0; 1 drivers -v0xa2b050_0 .net "nS", 0 0, L_0xa44f30; 1 drivers -v0xa2b0d0_0 .net "out0", 0 0, L_0xa45040; 1 drivers -v0xa2b170_0 .net "out1", 0 0, L_0xa45150; 1 drivers -v0xa2b250_0 .net "outfinal", 0 0, L_0xa451f0; 1 drivers -S_0xa28f00 .scope generate, "addbits[3]" "addbits[3]" 3 307, 3 307, S_0xa28d90; - .timescale -9 -12; -P_0xa28ff8 .param/l "i" 3 307, +C4<011>; -S_0xa29b60 .scope module, "attempt" "MiddleAddSubSLT" 3 309, 3 89, S_0xa28f00; - .timescale -9 -12; -L_0xa453d0/d .functor NOT 1, L_0xa46af0, C4<0>, C4<0>, C4<0>; -L_0xa453d0 .delay (10000,10000,10000) L_0xa453d0/d; -L_0xa45cf0/d .functor NOT 1, L_0xa45db0, C4<0>, C4<0>, C4<0>; -L_0xa45cf0 .delay (10000,10000,10000) L_0xa45cf0/d; -L_0xa3bb60/d .functor AND 1, L_0xa2c4b0, L_0xa45cf0, C4<1>, C4<1>; -L_0xa3bb60 .delay (20000,20000,20000) L_0xa3bb60/d; -L_0xa2c550/d .functor XOR 1, L_0xa46c10, L_0xa45a80, C4<0>, C4<0>; -L_0xa2c550 .delay (40000,40000,40000) L_0xa2c550/d; -L_0xa2c640/d .functor XOR 1, L_0xa2c550, L_0xa372a0, C4<0>, C4<0>; -L_0xa2c640 .delay (40000,40000,40000) L_0xa2c640/d; -L_0xa2c730/d .functor AND 1, L_0xa46c10, L_0xa45a80, C4<1>, C4<1>; -L_0xa2c730 .delay (20000,20000,20000) L_0xa2c730/d; -L_0xa466e0/d .functor AND 1, L_0xa2c550, L_0xa372a0, C4<1>, C4<1>; -L_0xa466e0 .delay (20000,20000,20000) L_0xa466e0/d; -L_0xa467d0/d .functor OR 1, L_0xa2c730, L_0xa466e0, C4<0>, C4<0>; -L_0xa467d0 .delay (20000,20000,20000) L_0xa467d0/d; -v0xa2a1e0_0 .net "A", 0 0, L_0xa46c10; 1 drivers -v0xa2a2a0_0 .net "AandB", 0 0, L_0xa2c730; 1 drivers -v0xa2a340_0 .net "AddSubSLTSum", 0 0, L_0xa2c640; 1 drivers -v0xa2a3e0_0 .net "AxorB", 0 0, L_0xa2c550; 1 drivers -v0xa2a460_0 .net "B", 0 0, L_0xa46af0; 1 drivers -v0xa2a510_0 .net "BornB", 0 0, L_0xa45a80; 1 drivers -v0xa2a5d0_0 .net "CINandAxorB", 0 0, L_0xa466e0; 1 drivers -v0xa2a650_0 .alias "Command", 2 0, v0xa373b0_0; -v0xa2a720_0 .net *"_s3", 0 0, L_0xa45db0; 1 drivers -v0xa2a7a0_0 .net *"_s5", 0 0, L_0xa2c4b0; 1 drivers -v0xa2a8a0_0 .net "carryin", 0 0, L_0xa372a0; 1 drivers -v0xa2a940_0 .net "carryout", 0 0, L_0xa467d0; 1 drivers -v0xa2a9e0_0 .net "nB", 0 0, L_0xa453d0; 1 drivers -v0xa2aa90_0 .net "nCmd2", 0 0, L_0xa45cf0; 1 drivers -v0xa2ab90_0 .net "subtract", 0 0, L_0xa3bb60; 1 drivers -L_0xa45c50 .part v0xa388d0_0, 0, 1; -L_0xa45db0 .part v0xa388d0_0, 2, 1; -L_0xa2c4b0 .part v0xa388d0_0, 0, 1; -S_0xa29c50 .scope module, "mux0" "TwoInMux" 3 105, 3 8, S_0xa29b60; - .timescale -9 -12; -L_0xa457a0/d .functor NOT 1, L_0xa45c50, C4<0>, C4<0>, C4<0>; -L_0xa457a0 .delay (10000,10000,10000) L_0xa457a0/d; -L_0xa45860/d .functor AND 1, L_0xa46af0, L_0xa457a0, C4<1>, C4<1>; -L_0xa45860 .delay (20000,20000,20000) L_0xa45860/d; -L_0xa45970/d .functor AND 1, L_0xa453d0, L_0xa45c50, C4<1>, C4<1>; -L_0xa45970 .delay (20000,20000,20000) L_0xa45970/d; -L_0xa45a80/d .functor OR 1, L_0xa45860, L_0xa45970, C4<0>, C4<0>; -L_0xa45a80 .delay (20000,20000,20000) L_0xa45a80/d; -v0xa29d40_0 .net "S", 0 0, L_0xa45c50; 1 drivers -v0xa29e00_0 .alias "in0", 0 0, v0xa2a460_0; -v0xa29ea0_0 .alias "in1", 0 0, v0xa2a9e0_0; -v0xa29f40_0 .net "nS", 0 0, L_0xa457a0; 1 drivers -v0xa29fc0_0 .net "out0", 0 0, L_0xa45860; 1 drivers -v0xa2a060_0 .net "out1", 0 0, L_0xa45970; 1 drivers -v0xa2a140_0 .alias "outfinal", 0 0, v0xa2a510_0; -S_0xa295e0 .scope module, "setSLTres2" "TwoInMux" 3 310, 3 8, S_0xa28f00; - .timescale -9 -12; -L_0xa37340/d .functor NOT 1, L_0xa47e00, C4<0>, C4<0>, C4<0>; -L_0xa37340 .delay (10000,10000,10000) L_0xa37340/d; -L_0xa42580/d .functor AND 1, L_0xa475f0, L_0xa37340, C4<1>, C4<1>; -L_0xa42580 .delay (20000,20000,20000) L_0xa42580/d; -L_0xa47370/d .functor AND 1, C4<0>, L_0xa47e00, C4<1>, C4<1>; -L_0xa47370 .delay (20000,20000,20000) L_0xa47370/d; -L_0xa47410/d .functor OR 1, L_0xa42580, L_0xa47370, C4<0>, C4<0>; -L_0xa47410 .delay (20000,20000,20000) L_0xa47410/d; -v0xa296d0_0 .alias "S", 0 0, v0xa309c0_0; -v0xa29770_0 .net "in0", 0 0, L_0xa475f0; 1 drivers -v0xa297f0_0 .net "in1", 0 0, C4<0>; 1 drivers -v0xa29890_0 .net "nS", 0 0, L_0xa37340; 1 drivers -v0xa29940_0 .net "out0", 0 0, L_0xa42580; 1 drivers -v0xa299e0_0 .net "out1", 0 0, L_0xa47370; 1 drivers -v0xa29ac0_0 .net "outfinal", 0 0, L_0xa47410; 1 drivers -S_0xa29070 .scope module, "setSLTres3" "TwoInMux" 3 311, 3 8, S_0xa28f00; - .timescale -9 -12; -L_0xa477e0/d .functor NOT 1, L_0xa47e00, C4<0>, C4<0>, C4<0>; -L_0xa477e0 .delay (10000,10000,10000) L_0xa477e0/d; -L_0xa47890/d .functor AND 1, L_0xa47c00, L_0xa477e0, C4<1>, C4<1>; -L_0xa47890 .delay (20000,20000,20000) L_0xa47890/d; -L_0xa47980/d .functor AND 1, L_0xa476e0, L_0xa47e00, C4<1>, C4<1>; -L_0xa47980 .delay (20000,20000,20000) L_0xa47980/d; -L_0xa47a20/d .functor OR 1, L_0xa47890, L_0xa47980, C4<0>, C4<0>; -L_0xa47a20 .delay (20000,20000,20000) L_0xa47a20/d; -v0xa29160_0 .alias "S", 0 0, v0xa309c0_0; -v0xa29200_0 .net "in0", 0 0, L_0xa47c00; 1 drivers -v0xa292a0_0 .net "in1", 0 0, L_0xa476e0; 1 drivers -v0xa29340_0 .net "nS", 0 0, L_0xa477e0; 1 drivers -v0xa293c0_0 .net "out0", 0 0, L_0xa47890; 1 drivers -v0xa29460_0 .net "out1", 0 0, L_0xa47980; 1 drivers -v0xa29540_0 .net "outfinal", 0 0, L_0xa47a20; 1 drivers -S_0xa25c80 .scope module, "trial1" "AndNand32" 2 150, 3 154, S_0x96f1c0; - .timescale -9 -12; -P_0xa25798 .param/l "size" 3 161, +C4<0100>; -v0xa28b40_0 .alias "A", 3 0, v0xa37070_0; -v0xa28bc0_0 .alias "AndNandOut", 3 0, v0xa387d0_0; -v0xa28c90_0 .alias "B", 3 0, v0xa37220_0; -v0xa28d10_0 .alias "Command", 2 0, v0xa373b0_0; -L_0xa4bac0 .part/pv L_0xa4b850, 1, 1, 4; -L_0xa4bc10 .part v0xa38650_0, 1, 1; -L_0xa4bcb0 .part v0xa38850_0, 1, 1; -L_0xa4c570 .part/pv L_0xa4c300, 2, 1, 4; -L_0xa4c610 .part v0xa38650_0, 2, 1; -L_0xa4c6b0 .part v0xa38850_0, 2, 1; -L_0xa4cfe0 .part/pv L_0xa4cd70, 3, 1, 4; -L_0xa4d080 .part v0xa38650_0, 3, 1; -L_0xa4d170 .part v0xa38850_0, 3, 1; -L_0xa4da40 .part/pv L_0xa4d7d0, 0, 1, 4; -L_0xa4db40 .part v0xa38650_0, 0, 1; -L_0xa4dbe0 .part v0xa38850_0, 0, 1; -S_0xa28110 .scope module, "attempt2" "AndNand" 3 165, 3 48, S_0xa25c80; - .timescale -9 -12; -L_0xa4d260/d .functor NAND 1, L_0xa4db40, L_0xa4dbe0, C4<1>, C4<1>; -L_0xa4d260 .delay (10000,10000,10000) L_0xa4d260/d; -L_0xa4d380/d .functor NOT 1, L_0xa4d260, C4<0>, C4<0>, C4<0>; -L_0xa4d380 .delay (10000,10000,10000) L_0xa4d380/d; -v0xa28730_0 .net "A", 0 0, L_0xa4db40; 1 drivers -v0xa287f0_0 .net "AandB", 0 0, L_0xa4d380; 1 drivers -v0xa28870_0 .net "AnandB", 0 0, L_0xa4d260; 1 drivers -v0xa28920_0 .net "AndNandOut", 0 0, L_0xa4d7d0; 1 drivers -v0xa28a00_0 .net "B", 0 0, L_0xa4dbe0; 1 drivers -v0xa28a80_0 .alias "Command", 2 0, v0xa373b0_0; -L_0xa4d9a0 .part v0xa388d0_0, 0, 1; -S_0xa28200 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0xa28110; - .timescale -9 -12; -L_0xa4d4b0/d .functor NOT 1, L_0xa4d9a0, C4<0>, C4<0>, C4<0>; -L_0xa4d4b0 .delay (10000,10000,10000) L_0xa4d4b0/d; -L_0xa4d570/d .functor AND 1, L_0xa4d380, L_0xa4d4b0, C4<1>, C4<1>; -L_0xa4d570 .delay (20000,20000,20000) L_0xa4d570/d; -L_0xa4d680/d .functor AND 1, L_0xa4d260, L_0xa4d9a0, C4<1>, C4<1>; -L_0xa4d680 .delay (20000,20000,20000) L_0xa4d680/d; -L_0xa4d7d0/d .functor OR 1, L_0xa4d570, L_0xa4d680, C4<0>, C4<0>; -L_0xa4d7d0 .delay (20000,20000,20000) L_0xa4d7d0/d; -v0xa282f0_0 .net "S", 0 0, L_0xa4d9a0; 1 drivers -v0xa28370_0 .alias "in0", 0 0, v0xa287f0_0; -v0xa283f0_0 .alias "in1", 0 0, v0xa28870_0; -v0xa28490_0 .net "nS", 0 0, L_0xa4d4b0; 1 drivers -v0xa28510_0 .net "out0", 0 0, L_0xa4d570; 1 drivers -v0xa285b0_0 .net "out1", 0 0, L_0xa4d680; 1 drivers -v0xa28690_0 .alias "outfinal", 0 0, v0xa28920_0; -S_0xa27550 .scope generate, "andbits[1]" "andbits[1]" 3 169, 3 169, S_0xa25c80; - .timescale -9 -12; -P_0xa27648 .param/l "i" 3 169, +C4<01>; -S_0xa276c0 .scope module, "attempt" "AndNand" 3 171, 3 48, S_0xa27550; - .timescale -9 -12; -L_0xa4a810/d .functor NAND 1, L_0xa4bc10, L_0xa4bcb0, C4<1>, C4<1>; -L_0xa4a810 .delay (10000,10000,10000) L_0xa4a810/d; -L_0xa4b440/d .functor NOT 1, L_0xa4a810, C4<0>, C4<0>, C4<0>; -L_0xa4b440 .delay (10000,10000,10000) L_0xa4b440/d; -v0xa27d00_0 .net "A", 0 0, L_0xa4bc10; 1 drivers -v0xa27dc0_0 .net "AandB", 0 0, L_0xa4b440; 1 drivers -v0xa27e40_0 .net "AnandB", 0 0, L_0xa4a810; 1 drivers -v0xa27ef0_0 .net "AndNandOut", 0 0, L_0xa4b850; 1 drivers -v0xa27fd0_0 .net "B", 0 0, L_0xa4bcb0; 1 drivers -v0xa28050_0 .alias "Command", 2 0, v0xa373b0_0; -L_0xa4ba20 .part v0xa388d0_0, 0, 1; -S_0xa277b0 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0xa276c0; - .timescale -9 -12; -L_0xa4b530/d .functor NOT 1, L_0xa4ba20, C4<0>, C4<0>, C4<0>; -L_0xa4b530 .delay (10000,10000,10000) L_0xa4b530/d; -L_0xa4b5f0/d .functor AND 1, L_0xa4b440, L_0xa4b530, C4<1>, C4<1>; -L_0xa4b5f0 .delay (20000,20000,20000) L_0xa4b5f0/d; -L_0xa4b700/d .functor AND 1, L_0xa4a810, L_0xa4ba20, C4<1>, C4<1>; -L_0xa4b700 .delay (20000,20000,20000) L_0xa4b700/d; -L_0xa4b850/d .functor OR 1, L_0xa4b5f0, L_0xa4b700, C4<0>, C4<0>; -L_0xa4b850 .delay (20000,20000,20000) L_0xa4b850/d; -v0xa278a0_0 .net "S", 0 0, L_0xa4ba20; 1 drivers -v0xa27920_0 .alias "in0", 0 0, v0xa27dc0_0; -v0xa279c0_0 .alias "in1", 0 0, v0xa27e40_0; -v0xa27a60_0 .net "nS", 0 0, L_0xa4b530; 1 drivers -v0xa27ae0_0 .net "out0", 0 0, L_0xa4b5f0; 1 drivers -v0xa27b80_0 .net "out1", 0 0, L_0xa4b700; 1 drivers -v0xa27c60_0 .alias "outfinal", 0 0, v0xa27ef0_0; -S_0xa26990 .scope generate, "andbits[2]" "andbits[2]" 3 169, 3 169, S_0xa25c80; - .timescale -9 -12; -P_0xa26a88 .param/l "i" 3 169, +C4<010>; -S_0xa26b00 .scope module, "attempt" "AndNand" 3 171, 3 48, S_0xa26990; - .timescale -9 -12; -L_0xa4bd50/d .functor NAND 1, L_0xa4c610, L_0xa4c6b0, C4<1>, C4<1>; -L_0xa4bd50 .delay (10000,10000,10000) L_0xa4bd50/d; -L_0xa4beb0/d .functor NOT 1, L_0xa4bd50, C4<0>, C4<0>, C4<0>; -L_0xa4beb0 .delay (10000,10000,10000) L_0xa4beb0/d; -v0xa27140_0 .net "A", 0 0, L_0xa4c610; 1 drivers -v0xa27200_0 .net "AandB", 0 0, L_0xa4beb0; 1 drivers -v0xa27280_0 .net "AnandB", 0 0, L_0xa4bd50; 1 drivers -v0xa27330_0 .net "AndNandOut", 0 0, L_0xa4c300; 1 drivers -v0xa27410_0 .net "B", 0 0, L_0xa4c6b0; 1 drivers -v0xa27490_0 .alias "Command", 2 0, v0xa373b0_0; -L_0xa4c4d0 .part v0xa388d0_0, 0, 1; -S_0xa26bf0 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0xa26b00; - .timescale -9 -12; -L_0xa4bfe0/d .functor NOT 1, L_0xa4c4d0, C4<0>, C4<0>, C4<0>; -L_0xa4bfe0 .delay (10000,10000,10000) L_0xa4bfe0/d; -L_0xa4c0a0/d .functor AND 1, L_0xa4beb0, L_0xa4bfe0, C4<1>, C4<1>; -L_0xa4c0a0 .delay (20000,20000,20000) L_0xa4c0a0/d; -L_0xa4c1b0/d .functor AND 1, L_0xa4bd50, L_0xa4c4d0, C4<1>, C4<1>; -L_0xa4c1b0 .delay (20000,20000,20000) L_0xa4c1b0/d; -L_0xa4c300/d .functor OR 1, L_0xa4c0a0, L_0xa4c1b0, C4<0>, C4<0>; -L_0xa4c300 .delay (20000,20000,20000) L_0xa4c300/d; -v0xa26ce0_0 .net "S", 0 0, L_0xa4c4d0; 1 drivers -v0xa26d60_0 .alias "in0", 0 0, v0xa27200_0; -v0xa26e00_0 .alias "in1", 0 0, v0xa27280_0; -v0xa26ea0_0 .net "nS", 0 0, L_0xa4bfe0; 1 drivers -v0xa26f20_0 .net "out0", 0 0, L_0xa4c0a0; 1 drivers -v0xa26fc0_0 .net "out1", 0 0, L_0xa4c1b0; 1 drivers -v0xa270a0_0 .alias "outfinal", 0 0, v0xa27330_0; -S_0xa25db0 .scope generate, "andbits[3]" "andbits[3]" 3 169, 3 169, S_0xa25c80; - .timescale -9 -12; -P_0xa25ea8 .param/l "i" 3 169, +C4<011>; -S_0xa25f20 .scope module, "attempt" "AndNand" 3 171, 3 48, S_0xa25db0; - .timescale -9 -12; -L_0xa4c7e0/d .functor NAND 1, L_0xa4d080, L_0xa4d170, C4<1>, C4<1>; -L_0xa4c7e0 .delay (10000,10000,10000) L_0xa4c7e0/d; -L_0xa4c920/d .functor NOT 1, L_0xa4c7e0, C4<0>, C4<0>, C4<0>; -L_0xa4c920 .delay (10000,10000,10000) L_0xa4c920/d; -v0xa26580_0 .net "A", 0 0, L_0xa4d080; 1 drivers -v0xa26640_0 .net "AandB", 0 0, L_0xa4c920; 1 drivers -v0xa266c0_0 .net "AnandB", 0 0, L_0xa4c7e0; 1 drivers -v0xa26770_0 .net "AndNandOut", 0 0, L_0xa4cd70; 1 drivers -v0xa26850_0 .net "B", 0 0, L_0xa4d170; 1 drivers -v0xa268d0_0 .alias "Command", 2 0, v0xa373b0_0; -L_0xa4cf40 .part v0xa388d0_0, 0, 1; -S_0xa26010 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0xa25f20; - .timescale -9 -12; -L_0xa4ca50/d .functor NOT 1, L_0xa4cf40, C4<0>, C4<0>, C4<0>; -L_0xa4ca50 .delay (10000,10000,10000) L_0xa4ca50/d; -L_0xa4cb10/d .functor AND 1, L_0xa4c920, L_0xa4ca50, C4<1>, C4<1>; -L_0xa4cb10 .delay (20000,20000,20000) L_0xa4cb10/d; -L_0xa4cc20/d .functor AND 1, L_0xa4c7e0, L_0xa4cf40, C4<1>, C4<1>; -L_0xa4cc20 .delay (20000,20000,20000) L_0xa4cc20/d; -L_0xa4cd70/d .functor OR 1, L_0xa4cb10, L_0xa4cc20, C4<0>, C4<0>; -L_0xa4cd70 .delay (20000,20000,20000) L_0xa4cd70/d; -v0xa26100_0 .net "S", 0 0, L_0xa4cf40; 1 drivers -v0xa261a0_0 .alias "in0", 0 0, v0xa26640_0; -v0xa26240_0 .alias "in1", 0 0, v0xa266c0_0; -v0xa262e0_0 .net "nS", 0 0, L_0xa4ca50; 1 drivers -v0xa26360_0 .net "out0", 0 0, L_0xa4cb10; 1 drivers -v0xa26400_0 .net "out1", 0 0, L_0xa4cc20; 1 drivers -v0xa264e0_0 .alias "outfinal", 0 0, v0xa26770_0; -S_0xa20c10 .scope module, "trial2" "OrNorXor32" 2 152, 3 177, S_0x96f1c0; - .timescale -9 -12; -P_0xa1e328 .param/l "size" 3 184, +C4<0100>; -v0xa25a80_0 .alias "A", 3 0, v0xa37070_0; -v0xa25b00_0 .alias "B", 3 0, v0xa37220_0; -v0xa25b80_0 .alias "Command", 2 0, v0xa373b0_0; -v0xa25c00_0 .alias "OrNorXorOut", 3 0, v0xa389d0_0; -L_0xa4ee00 .part/pv L_0xa4eb90, 1, 1, 4; -L_0xa4ef30 .part v0xa38650_0, 1, 1; -L_0xa4efd0 .part v0xa38850_0, 1, 1; -L_0xa50140 .part/pv L_0xa4fed0, 2, 1, 4; -L_0xa501e0 .part v0xa38650_0, 2, 1; -L_0xa50280 .part v0xa38850_0, 2, 1; -L_0xa51440 .part/pv L_0xa511d0, 3, 1, 4; -L_0xa514e0 .part v0xa38650_0, 3, 1; -L_0xa51580 .part v0xa38850_0, 3, 1; -L_0xa52730 .part/pv L_0xa524c0, 0, 1, 4; -L_0xa52830 .part v0xa38650_0, 0, 1; -L_0xa528d0 .part v0xa38850_0, 0, 1; -S_0xa24840 .scope module, "attempt2" "OrNorXor" 3 192, 3 64, S_0xa20c10; - .timescale -9 -12; -L_0xa51620/d .functor NOR 1, L_0xa52830, L_0xa528d0, C4<0>, C4<0>; -L_0xa51620 .delay (10000,10000,10000) L_0xa51620/d; -L_0xa51720/d .functor NOT 1, L_0xa51620, C4<0>, C4<0>, C4<0>; -L_0xa51720 .delay (10000,10000,10000) L_0xa51720/d; -L_0xa51850/d .functor NAND 1, L_0xa52830, L_0xa528d0, C4<1>, C4<1>; -L_0xa51850 .delay (10000,10000,10000) L_0xa51850/d; -L_0xa519b0/d .functor NAND 1, L_0xa51850, L_0xa51720, C4<1>, C4<1>; -L_0xa519b0 .delay (10000,10000,10000) L_0xa519b0/d; -L_0xa51ac0/d .functor NOT 1, L_0xa519b0, C4<0>, C4<0>, C4<0>; -L_0xa51ac0 .delay (10000,10000,10000) L_0xa51ac0/d; -v0xa25390_0 .net "A", 0 0, L_0xa52830; 1 drivers -v0xa25430_0 .net "AnandB", 0 0, L_0xa51850; 1 drivers -v0xa254d0_0 .net "AnorB", 0 0, L_0xa51620; 1 drivers -v0xa25580_0 .net "AorB", 0 0, L_0xa51720; 1 drivers -v0xa25660_0 .net "AxorB", 0 0, L_0xa51ac0; 1 drivers -v0xa25710_0 .net "B", 0 0, L_0xa528d0; 1 drivers -v0xa257d0_0 .alias "Command", 2 0, v0xa373b0_0; -v0xa25850_0 .net "OrNorXorOut", 0 0, L_0xa524c0; 1 drivers -v0xa258d0_0 .net "XorNor", 0 0, L_0xa51f40; 1 drivers -v0xa259a0_0 .net "nXor", 0 0, L_0xa519b0; 1 drivers -L_0xa520c0 .part v0xa388d0_0, 2, 1; -L_0xa52690 .part v0xa388d0_0, 0, 1; -S_0xa24e20 .scope module, "mux0" "TwoInMux" 3 83, 3 8, S_0xa24840; - .timescale -9 -12; -L_0xa51c20/d .functor NOT 1, L_0xa520c0, C4<0>, C4<0>, C4<0>; -L_0xa51c20 .delay (10000,10000,10000) L_0xa51c20/d; -L_0xa51ce0/d .functor AND 1, L_0xa51ac0, L_0xa51c20, C4<1>, C4<1>; -L_0xa51ce0 .delay (20000,20000,20000) L_0xa51ce0/d; -L_0xa51df0/d .functor AND 1, L_0xa51620, L_0xa520c0, C4<1>, C4<1>; -L_0xa51df0 .delay (20000,20000,20000) L_0xa51df0/d; -L_0xa51f40/d .functor OR 1, L_0xa51ce0, L_0xa51df0, C4<0>, C4<0>; -L_0xa51f40 .delay (20000,20000,20000) L_0xa51f40/d; -v0xa24f10_0 .net "S", 0 0, L_0xa520c0; 1 drivers -v0xa24fd0_0 .alias "in0", 0 0, v0xa25660_0; -v0xa25070_0 .alias "in1", 0 0, v0xa254d0_0; -v0xa25110_0 .net "nS", 0 0, L_0xa51c20; 1 drivers -v0xa25190_0 .net "out0", 0 0, L_0xa51ce0; 1 drivers -v0xa25230_0 .net "out1", 0 0, L_0xa51df0; 1 drivers -v0xa25310_0 .alias "outfinal", 0 0, v0xa258d0_0; -S_0xa24930 .scope module, "mux1" "TwoInMux" 3 84, 3 8, S_0xa24840; - .timescale -9 -12; -L_0xa52160/d .functor NOT 1, L_0xa52690, C4<0>, C4<0>, C4<0>; -L_0xa52160 .delay (10000,10000,10000) L_0xa52160/d; -L_0xa52220/d .functor AND 1, L_0xa51f40, L_0xa52160, C4<1>, C4<1>; -L_0xa52220 .delay (20000,20000,20000) L_0xa52220/d; -L_0xa52370/d .functor AND 1, L_0xa51720, L_0xa52690, C4<1>, C4<1>; -L_0xa52370 .delay (20000,20000,20000) L_0xa52370/d; -L_0xa524c0/d .functor OR 1, L_0xa52220, L_0xa52370, C4<0>, C4<0>; -L_0xa524c0 .delay (20000,20000,20000) L_0xa524c0/d; -v0xa24a20_0 .net "S", 0 0, L_0xa52690; 1 drivers -v0xa24aa0_0 .alias "in0", 0 0, v0xa258d0_0; -v0xa24b20_0 .alias "in1", 0 0, v0xa25580_0; -v0xa24bc0_0 .net "nS", 0 0, L_0xa52160; 1 drivers -v0xa24c40_0 .net "out0", 0 0, L_0xa52220; 1 drivers -v0xa24ce0_0 .net "out1", 0 0, L_0xa52370; 1 drivers -v0xa24d80_0 .alias "outfinal", 0 0, v0xa25850_0; -S_0xa23470 .scope generate, "orbits[1]" "orbits[1]" 3 196, 3 196, S_0xa20c10; - .timescale -9 -12; -P_0xa23188 .param/l "i" 3 196, +C4<01>; -S_0xa235a0 .scope module, "attempt" "OrNorXor" 3 198, 3 64, S_0xa23470; - .timescale -9 -12; -L_0xa4dae0/d .functor NOR 1, L_0xa4ef30, L_0xa4efd0, C4<0>, C4<0>; -L_0xa4dae0 .delay (10000,10000,10000) L_0xa4dae0/d; -L_0xa4ddf0/d .functor NOT 1, L_0xa4dae0, C4<0>, C4<0>, C4<0>; -L_0xa4ddf0 .delay (10000,10000,10000) L_0xa4ddf0/d; -L_0xa4df20/d .functor NAND 1, L_0xa4ef30, L_0xa4efd0, C4<1>, C4<1>; -L_0xa4df20 .delay (10000,10000,10000) L_0xa4df20/d; -L_0xa4e080/d .functor NAND 1, L_0xa4df20, L_0xa4ddf0, C4<1>, C4<1>; -L_0xa4e080 .delay (10000,10000,10000) L_0xa4e080/d; -L_0xa4e190/d .functor NOT 1, L_0xa4e080, C4<0>, C4<0>, C4<0>; -L_0xa4e190 .delay (10000,10000,10000) L_0xa4e190/d; -v0xa24150_0 .net "A", 0 0, L_0xa4ef30; 1 drivers -v0xa241f0_0 .net "AnandB", 0 0, L_0xa4df20; 1 drivers -v0xa24290_0 .net "AnorB", 0 0, L_0xa4dae0; 1 drivers -v0xa24340_0 .net "AorB", 0 0, L_0xa4ddf0; 1 drivers -v0xa24420_0 .net "AxorB", 0 0, L_0xa4e190; 1 drivers -v0xa244d0_0 .net "B", 0 0, L_0xa4efd0; 1 drivers -v0xa24590_0 .alias "Command", 2 0, v0xa373b0_0; -v0xa24610_0 .net "OrNorXorOut", 0 0, L_0xa4eb90; 1 drivers -v0xa24690_0 .net "XorNor", 0 0, L_0xa4e610; 1 drivers -v0xa24760_0 .net "nXor", 0 0, L_0xa4e080; 1 drivers -L_0xa4e790 .part v0xa388d0_0, 2, 1; -L_0xa4ed60 .part v0xa388d0_0, 0, 1; -S_0xa23be0 .scope module, "mux0" "TwoInMux" 3 83, 3 8, S_0xa235a0; - .timescale -9 -12; -L_0xa4e2f0/d .functor NOT 1, L_0xa4e790, C4<0>, C4<0>, C4<0>; -L_0xa4e2f0 .delay (10000,10000,10000) L_0xa4e2f0/d; -L_0xa4e3b0/d .functor AND 1, L_0xa4e190, L_0xa4e2f0, C4<1>, C4<1>; -L_0xa4e3b0 .delay (20000,20000,20000) L_0xa4e3b0/d; -L_0xa4e4c0/d .functor AND 1, L_0xa4dae0, L_0xa4e790, C4<1>, C4<1>; -L_0xa4e4c0 .delay (20000,20000,20000) L_0xa4e4c0/d; -L_0xa4e610/d .functor OR 1, L_0xa4e3b0, L_0xa4e4c0, C4<0>, C4<0>; -L_0xa4e610 .delay (20000,20000,20000) L_0xa4e610/d; -v0xa23cd0_0 .net "S", 0 0, L_0xa4e790; 1 drivers -v0xa23d90_0 .alias "in0", 0 0, v0xa24420_0; -v0xa23e30_0 .alias "in1", 0 0, v0xa24290_0; -v0xa23ed0_0 .net "nS", 0 0, L_0xa4e2f0; 1 drivers -v0xa23f50_0 .net "out0", 0 0, L_0xa4e3b0; 1 drivers -v0xa23ff0_0 .net "out1", 0 0, L_0xa4e4c0; 1 drivers -v0xa240d0_0 .alias "outfinal", 0 0, v0xa24690_0; -S_0xa23690 .scope module, "mux1" "TwoInMux" 3 84, 3 8, S_0xa235a0; - .timescale -9 -12; -L_0xa4e830/d .functor NOT 1, L_0xa4ed60, C4<0>, C4<0>, C4<0>; -L_0xa4e830 .delay (10000,10000,10000) L_0xa4e830/d; -L_0xa4e8f0/d .functor AND 1, L_0xa4e610, L_0xa4e830, C4<1>, C4<1>; -L_0xa4e8f0 .delay (20000,20000,20000) L_0xa4e8f0/d; -L_0xa4ea40/d .functor AND 1, L_0xa4ddf0, L_0xa4ed60, C4<1>, C4<1>; -L_0xa4ea40 .delay (20000,20000,20000) L_0xa4ea40/d; -L_0xa4eb90/d .functor OR 1, L_0xa4e8f0, L_0xa4ea40, C4<0>, C4<0>; -L_0xa4eb90 .delay (20000,20000,20000) L_0xa4eb90/d; -v0xa23780_0 .net "S", 0 0, L_0xa4ed60; 1 drivers -v0xa23800_0 .alias "in0", 0 0, v0xa24690_0; -v0xa238a0_0 .alias "in1", 0 0, v0xa24340_0; -v0xa23940_0 .net "nS", 0 0, L_0xa4e830; 1 drivers -v0xa239c0_0 .net "out0", 0 0, L_0xa4e8f0; 1 drivers -v0xa23a60_0 .net "out1", 0 0, L_0xa4ea40; 1 drivers -v0xa23b40_0 .alias "outfinal", 0 0, v0xa24610_0; -S_0xa220a0 .scope generate, "orbits[2]" "orbits[2]" 3 196, 3 196, S_0xa20c10; - .timescale -9 -12; -P_0xa21dc8 .param/l "i" 3 196, +C4<010>; -S_0xa221d0 .scope module, "attempt" "OrNorXor" 3 198, 3 64, S_0xa220a0; - .timescale -9 -12; -L_0xa4f070/d .functor NOR 1, L_0xa501e0, L_0xa50280, C4<0>, C4<0>; -L_0xa4f070 .delay (10000,10000,10000) L_0xa4f070/d; -L_0xa4f130/d .functor NOT 1, L_0xa4f070, C4<0>, C4<0>, C4<0>; -L_0xa4f130 .delay (10000,10000,10000) L_0xa4f130/d; -L_0xa4f260/d .functor NAND 1, L_0xa501e0, L_0xa50280, C4<1>, C4<1>; -L_0xa4f260 .delay (10000,10000,10000) L_0xa4f260/d; -L_0xa4f3c0/d .functor NAND 1, L_0xa4f260, L_0xa4f130, C4<1>, C4<1>; -L_0xa4f3c0 .delay (10000,10000,10000) L_0xa4f3c0/d; -L_0xa4f4d0/d .functor NOT 1, L_0xa4f3c0, C4<0>, C4<0>, C4<0>; -L_0xa4f4d0 .delay (10000,10000,10000) L_0xa4f4d0/d; -v0xa22d80_0 .net "A", 0 0, L_0xa501e0; 1 drivers -v0xa22e20_0 .net "AnandB", 0 0, L_0xa4f260; 1 drivers -v0xa22ec0_0 .net "AnorB", 0 0, L_0xa4f070; 1 drivers -v0xa22f70_0 .net "AorB", 0 0, L_0xa4f130; 1 drivers -v0xa23050_0 .net "AxorB", 0 0, L_0xa4f4d0; 1 drivers -v0xa23100_0 .net "B", 0 0, L_0xa50280; 1 drivers -v0xa231c0_0 .alias "Command", 2 0, v0xa373b0_0; -v0xa23240_0 .net "OrNorXorOut", 0 0, L_0xa4fed0; 1 drivers -v0xa232c0_0 .net "XorNor", 0 0, L_0xa4f950; 1 drivers -v0xa23390_0 .net "nXor", 0 0, L_0xa4f3c0; 1 drivers -L_0xa4fad0 .part v0xa388d0_0, 2, 1; -L_0xa500a0 .part v0xa388d0_0, 0, 1; -S_0xa22810 .scope module, "mux0" "TwoInMux" 3 83, 3 8, S_0xa221d0; - .timescale -9 -12; -L_0xa4f630/d .functor NOT 1, L_0xa4fad0, C4<0>, C4<0>, C4<0>; -L_0xa4f630 .delay (10000,10000,10000) L_0xa4f630/d; -L_0xa4f6f0/d .functor AND 1, L_0xa4f4d0, L_0xa4f630, C4<1>, C4<1>; -L_0xa4f6f0 .delay (20000,20000,20000) L_0xa4f6f0/d; -L_0xa4f800/d .functor AND 1, L_0xa4f070, L_0xa4fad0, C4<1>, C4<1>; -L_0xa4f800 .delay (20000,20000,20000) L_0xa4f800/d; -L_0xa4f950/d .functor OR 1, L_0xa4f6f0, L_0xa4f800, C4<0>, C4<0>; -L_0xa4f950 .delay (20000,20000,20000) L_0xa4f950/d; -v0xa22900_0 .net "S", 0 0, L_0xa4fad0; 1 drivers -v0xa229c0_0 .alias "in0", 0 0, v0xa23050_0; -v0xa22a60_0 .alias "in1", 0 0, v0xa22ec0_0; -v0xa22b00_0 .net "nS", 0 0, L_0xa4f630; 1 drivers -v0xa22b80_0 .net "out0", 0 0, L_0xa4f6f0; 1 drivers -v0xa22c20_0 .net "out1", 0 0, L_0xa4f800; 1 drivers -v0xa22d00_0 .alias "outfinal", 0 0, v0xa232c0_0; -S_0xa222c0 .scope module, "mux1" "TwoInMux" 3 84, 3 8, S_0xa221d0; - .timescale -9 -12; -L_0xa4fb70/d .functor NOT 1, L_0xa500a0, C4<0>, C4<0>, C4<0>; -L_0xa4fb70 .delay (10000,10000,10000) L_0xa4fb70/d; -L_0xa4fc30/d .functor AND 1, L_0xa4f950, L_0xa4fb70, C4<1>, C4<1>; -L_0xa4fc30 .delay (20000,20000,20000) L_0xa4fc30/d; -L_0xa4fd80/d .functor AND 1, L_0xa4f130, L_0xa500a0, C4<1>, C4<1>; -L_0xa4fd80 .delay (20000,20000,20000) L_0xa4fd80/d; -L_0xa4fed0/d .functor OR 1, L_0xa4fc30, L_0xa4fd80, C4<0>, C4<0>; -L_0xa4fed0 .delay (20000,20000,20000) L_0xa4fed0/d; -v0xa223b0_0 .net "S", 0 0, L_0xa500a0; 1 drivers -v0xa22430_0 .alias "in0", 0 0, v0xa232c0_0; -v0xa224d0_0 .alias "in1", 0 0, v0xa22f70_0; -v0xa22570_0 .net "nS", 0 0, L_0xa4fb70; 1 drivers -v0xa225f0_0 .net "out0", 0 0, L_0xa4fc30; 1 drivers -v0xa22690_0 .net "out1", 0 0, L_0xa4fd80; 1 drivers -v0xa22770_0 .alias "outfinal", 0 0, v0xa23240_0; -S_0xa20d00 .scope generate, "orbits[3]" "orbits[3]" 3 196, 3 196, S_0xa20c10; - .timescale -9 -12; -P_0xa20df8 .param/l "i" 3 196, +C4<011>; -S_0xa20eb0 .scope module, "attempt" "OrNorXor" 3 198, 3 64, S_0xa20d00; - .timescale -9 -12; -L_0xa50360/d .functor NOR 1, L_0xa514e0, L_0xa51580, C4<0>, C4<0>; -L_0xa50360 .delay (10000,10000,10000) L_0xa50360/d; -L_0xa50450/d .functor NOT 1, L_0xa50360, C4<0>, C4<0>, C4<0>; -L_0xa50450 .delay (10000,10000,10000) L_0xa50450/d; -L_0xa50560/d .functor NAND 1, L_0xa514e0, L_0xa51580, C4<1>, C4<1>; -L_0xa50560 .delay (10000,10000,10000) L_0xa50560/d; -L_0xa506c0/d .functor NAND 1, L_0xa50560, L_0xa50450, C4<1>, C4<1>; -L_0xa506c0 .delay (10000,10000,10000) L_0xa506c0/d; -L_0xa507d0/d .functor NOT 1, L_0xa506c0, C4<0>, C4<0>, C4<0>; -L_0xa507d0 .delay (10000,10000,10000) L_0xa507d0/d; -v0xa21a80_0 .net "A", 0 0, L_0xa514e0; 1 drivers -v0xa21b20_0 .net "AnandB", 0 0, L_0xa50560; 1 drivers -v0xa21bc0_0 .net "AnorB", 0 0, L_0xa50360; 1 drivers -v0xa21c40_0 .net "AorB", 0 0, L_0xa50450; 1 drivers -v0xa21cc0_0 .net "AxorB", 0 0, L_0xa507d0; 1 drivers -v0xa21d40_0 .net "B", 0 0, L_0xa51580; 1 drivers -v0xa21e00_0 .alias "Command", 2 0, v0xa373b0_0; -v0xa21e80_0 .net "OrNorXorOut", 0 0, L_0xa511d0; 1 drivers -v0xa21f50_0 .net "XorNor", 0 0, L_0xa50c50; 1 drivers -v0xa22020_0 .net "nXor", 0 0, L_0xa506c0; 1 drivers -L_0xa50dd0 .part v0xa388d0_0, 2, 1; -L_0xa513a0 .part v0xa388d0_0, 0, 1; -S_0xa21510 .scope module, "mux0" "TwoInMux" 3 83, 3 8, S_0xa20eb0; - .timescale -9 -12; -L_0xa50930/d .functor NOT 1, L_0xa50dd0, C4<0>, C4<0>, C4<0>; -L_0xa50930 .delay (10000,10000,10000) L_0xa50930/d; -L_0xa509f0/d .functor AND 1, L_0xa507d0, L_0xa50930, C4<1>, C4<1>; -L_0xa509f0 .delay (20000,20000,20000) L_0xa509f0/d; -L_0xa50b00/d .functor AND 1, L_0xa50360, L_0xa50dd0, C4<1>, C4<1>; -L_0xa50b00 .delay (20000,20000,20000) L_0xa50b00/d; -L_0xa50c50/d .functor OR 1, L_0xa509f0, L_0xa50b00, C4<0>, C4<0>; -L_0xa50c50 .delay (20000,20000,20000) L_0xa50c50/d; -v0xa21600_0 .net "S", 0 0, L_0xa50dd0; 1 drivers -v0xa216c0_0 .alias "in0", 0 0, v0xa21cc0_0; -v0xa21760_0 .alias "in1", 0 0, v0xa21bc0_0; -v0xa21800_0 .net "nS", 0 0, L_0xa50930; 1 drivers -v0xa21880_0 .net "out0", 0 0, L_0xa509f0; 1 drivers -v0xa21920_0 .net "out1", 0 0, L_0xa50b00; 1 drivers -v0xa21a00_0 .alias "outfinal", 0 0, v0xa21f50_0; -S_0xa20fa0 .scope module, "mux1" "TwoInMux" 3 84, 3 8, S_0xa20eb0; - .timescale -9 -12; -L_0xa50e70/d .functor NOT 1, L_0xa513a0, C4<0>, C4<0>, C4<0>; -L_0xa50e70 .delay (10000,10000,10000) L_0xa50e70/d; -L_0xa50f30/d .functor AND 1, L_0xa50c50, L_0xa50e70, C4<1>, C4<1>; -L_0xa50f30 .delay (20000,20000,20000) L_0xa50f30/d; -L_0xa51080/d .functor AND 1, L_0xa50450, L_0xa513a0, C4<1>, C4<1>; -L_0xa51080 .delay (20000,20000,20000) L_0xa51080/d; -L_0xa511d0/d .functor OR 1, L_0xa50f30, L_0xa51080, C4<0>, C4<0>; -L_0xa511d0 .delay (20000,20000,20000) L_0xa511d0/d; -v0xa21090_0 .net "S", 0 0, L_0xa513a0; 1 drivers -v0xa21130_0 .alias "in0", 0 0, v0xa21f50_0; -v0xa211d0_0 .alias "in1", 0 0, v0xa21c40_0; -v0xa21270_0 .net "nS", 0 0, L_0xa50e70; 1 drivers -v0xa212f0_0 .net "out0", 0 0, L_0xa50f30; 1 drivers -v0xa21390_0 .net "out1", 0 0, L_0xa51080; 1 drivers -v0xa21470_0 .alias "outfinal", 0 0, v0xa21e80_0; -S_0x9cd4a0 .scope module, "superalu" "Bitslice32" 2 154, 3 368, S_0x96f1c0; - .timescale -9 -12; -P_0x8c2938 .param/l "size" 3 386, +C4<0100>; -L_0xa576c0/d .functor AND 1, L_0xa76a20, L_0xa76c00, C4<1>, C4<1>; -L_0xa576c0 .delay (20000,20000,20000) L_0xa576c0/d; -L_0xa76cf0/d .functor NOT 1, L_0xa76da0, C4<0>, C4<0>, C4<0>; -L_0xa76cf0 .delay (10000,10000,10000) L_0xa76cf0/d; -L_0xa77250/d .functor AND 1, L_0xa76cf0, L_0xa76cf0, C4<1>, C4<1>; -L_0xa77250 .delay (20000,20000,20000) L_0xa77250/d; -v0xa1f9b0_0 .alias "A", 3 0, v0xa37070_0; -v0xa1fc90_0 .alias "AddSubSLTSum", 3 0, v0xa386d0_0; -v0xa1fd10_0 .alias "AllZeros", 0 0, v0xa38750_0; -v0xa1fd90_0 .alias "AndNandOut", 3 0, v0xa387d0_0; -v0xa1fe10_0 .alias "B", 3 0, v0xa37220_0; -RS_0x7ffb33a71f28 .resolv tri, L_0xa53070, L_0xa55a50, L_0xa58450, L_0xa74df0; -v0xa1ff20_0 .net8 "Cmd0Start", 3 0, RS_0x7ffb33a71f28; 4 drivers -RS_0x7ffb33a71f58 .resolv tri, L_0xa53f70, L_0xa56940, L_0xa59300, L_0xa75c20; -v0xa1ffa0_0 .net8 "Cmd1Start", 3 0, RS_0x7ffb33a71f58; 4 drivers -v0xa20020_0 .alias "Command", 2 0, v0xa373b0_0; -v0xa200a0_0 .alias "OneBitFinalOut", 3 0, v0xa38950_0; -v0xa20120_0 .alias "OrNorXorOut", 3 0, v0xa389d0_0; -v0xa201a0_0 .alias "SLTSum", 3 0, v0xa38a50_0; -v0xa20250_0 .alias "SLTflag", 0 0, v0xa38ad0_0; -v0xa20360_0 .alias "ZeroFlag", 3 0, v0xa38b50_0; -v0xa203e0_0 .net *"_s111", 0 0, L_0xa576c0; 1 drivers -v0xa204e0_0 .net *"_s114", 0 0, L_0xa76a20; 1 drivers -v0xa20560_0 .net *"_s116", 0 0, L_0xa76c00; 1 drivers -v0xa20460_0 .net *"_s118", 0 0, L_0xa76da0; 1 drivers -v0xa206b0_0 .net *"_s21", 0 0, L_0xa54fc0; 1 drivers -v0xa207d0_0 .net *"_s46", 0 0, L_0xa56f90; 1 drivers -v0xa20850_0 .net *"_s71", 0 0, L_0xa5a0c0; 1 drivers -v0xa20730_0 .alias "carryin", 3 0, v0xa37df0_0; -v0xa20980_0 .alias "carryout", 0 0, v0xa38c80_0; -v0xa208d0_0 .alias "overflow", 0 0, v0xa38d00_0; -v0xa20ac0_0 .alias "subtract", 3 0, v0xa38e00_0; -v0xa20a00_0 .net "yeszero", 0 0, L_0xa76cf0; 1 drivers -L_0xa53070 .part/pv L_0xa52e90, 1, 1, 4; -L_0xa53110 .part v0xa388d0_0, 0, 1; -L_0xa53240 .part v0xa388d0_0, 1, 1; -L_0xa53370 .part RS_0x7ffb33a70098, 1, 1; -L_0xa53410 .part RS_0x7ffb33a70098, 1, 1; -L_0xa534b0 .part RS_0x7ffb33a6e748, 1, 1; -L_0xa536b0 .part RS_0x7ffb33a71c58, 1, 1; -L_0xa53f70 .part/pv L_0xa53d90, 1, 1, 4; -L_0xa54060 .part v0xa388d0_0, 0, 1; -L_0xa54190 .part v0xa388d0_0, 1, 1; -L_0xa54320 .part RS_0x7ffb33a6ee38, 1, 1; -L_0xa544d0 .part RS_0x7ffb33a6ee38, 1, 1; -L_0xa54570 .part RS_0x7ffb33a6e748, 1, 1; -L_0xa54610 .part RS_0x7ffb33a6e748, 1, 1; -L_0xa54a70 .part/pv L_0xa54930, 1, 1, 4; -L_0xa54b60 .part v0xa388d0_0, 2, 1; -L_0xa54c00 .part RS_0x7ffb33a71f28, 1, 1; -L_0xa54d40 .part RS_0x7ffb33a71f58, 1, 1; -L_0xa54f20 .part/pv L_0xa54fc0, 1, 1, 4; -L_0xa550c0 .part RS_0x7ffb33a71fb8, 0, 1; -L_0xa54e80 .part RS_0x7ffb33a71f88, 1, 1; -L_0xa55a50 .part/pv L_0xa55840, 2, 1, 4; -L_0xa55160 .part v0xa388d0_0, 0, 1; -L_0xa55c40 .part v0xa388d0_0, 1, 1; -L_0xa55af0 .part RS_0x7ffb33a70098, 2, 1; -L_0xa55e40 .part RS_0x7ffb33a70098, 2, 1; -L_0xa55d70 .part RS_0x7ffb33a6e748, 2, 1; -L_0xa56010 .part RS_0x7ffb33a71c58, 2, 1; -L_0xa56940 .part/pv L_0xa56730, 2, 1, 4; -L_0xa569e0 .part v0xa388d0_0, 0, 1; -L_0xa56100 .part v0xa388d0_0, 1, 1; -L_0xa56ca0 .part RS_0x7ffb33a6ee38, 2, 1; -L_0xa56b10 .part RS_0x7ffb33a6ee38, 2, 1; -L_0xa56e50 .part RS_0x7ffb33a6e748, 2, 1; -L_0xa56d40 .part RS_0x7ffb33a6e748, 2, 1; -L_0xa573c0 .part/pv L_0xa57280, 2, 1, 4; -L_0xa56ef0 .part v0xa388d0_0, 2, 1; -L_0xa57620 .part RS_0x7ffb33a71f28, 2, 1; -L_0xa574f0 .part RS_0x7ffb33a71f58, 2, 1; -L_0xa57890 .part/pv L_0xa56f90, 2, 1, 4; -L_0xa57790 .part RS_0x7ffb33a71fb8, 1, 1; -L_0xa57b10 .part RS_0x7ffb33a71f88, 2, 1; -L_0xa58450 .part/pv L_0xa58240, 3, 1, 4; -L_0xa584f0 .part v0xa388d0_0, 0, 1; -L_0xa57bb0 .part v0xa388d0_0, 1, 1; -L_0xa58790 .part RS_0x7ffb33a70098, 3, 1; -L_0xa58620 .part RS_0x7ffb33a70098, 3, 1; -L_0xa586c0 .part RS_0x7ffb33a6e748, 3, 1; -L_0xa58830 .part RS_0x7ffb33a71c58, 3, 1; -L_0xa59300 .part/pv L_0xa590f0, 3, 1, 4; -L_0xa58a00 .part v0xa388d0_0, 0, 1; -L_0xa59540 .part v0xa388d0_0, 1, 1; -L_0xa593a0 .part RS_0x7ffb33a6ee38, 3, 1; -L_0xa59440 .part RS_0x7ffb33a6ee38, 3, 1; -L_0xa59830 .part RS_0x7ffb33a6e748, 3, 1; -L_0xa598d0 .part RS_0x7ffb33a6e748, 3, 1; -L_0xa59ee0 .part/pv L_0xa59da0, 3, 1, 4; -L_0xa59f80 .part v0xa388d0_0, 2, 1; -L_0xa59b80 .part RS_0x7ffb33a71f28, 3, 1; -L_0xa59c70 .part RS_0x7ffb33a71f58, 3, 1; -L_0xa5a020 .part/pv L_0xa5a0c0, 3, 1, 4; -L_0xa5a440 .part RS_0x7ffb33a71fb8, 2, 1; -L_0xa5a250 .part RS_0x7ffb33a71f88, 3, 1; -L_0xa74df0 .part/pv L_0xa74c10, 0, 1, 4; -L_0xa5a4e0 .part v0xa388d0_0, 0, 1; -L_0xa5a610 .part v0xa388d0_0, 1, 1; -L_0xa74e90 .part RS_0x7ffb33a70098, 0, 1; -L_0xa74f30 .part RS_0x7ffb33a70098, 0, 1; -L_0xa74fd0 .part RS_0x7ffb33a6e748, 0, 1; -L_0xa753b0 .part RS_0x7ffb33a71c58, 0, 1; -L_0xa75c20 .part/pv L_0xa75a40, 0, 1, 4; -L_0xa75cc0 .part v0xa388d0_0, 0, 1; -L_0xa754a0 .part v0xa388d0_0, 1, 1; -L_0xa755d0 .part RS_0x7ffb33a6ee38, 0, 1; -L_0xa76050 .part RS_0x7ffb33a6ee38, 0, 1; -L_0xa760f0 .part RS_0x7ffb33a6e748, 0, 1; -L_0xa75df0 .part RS_0x7ffb33a6e748, 0, 1; -L_0xa766c0 .part/pv L_0xa76580, 0, 1, 4; -L_0xa76190 .part v0xa388d0_0, 2, 1; -L_0xa76230 .part RS_0x7ffb33a71f28, 0, 1; -L_0xa76320 .part RS_0x7ffb33a71f58, 0, 1; -L_0xa76980 .part/pv L_0xa576c0, 0, 1, 4; -L_0xa76a20 .part RS_0x7ffb33a71f88, 0, 1; -L_0xa76c00 .part RS_0x7ffb33a71f88, 0, 1; -L_0xa76da0 .part RS_0x7ffb33a71fb8, 3, 1; -S_0xa175f0 .scope module, "test" "SLT32" 3 393, 3 273, S_0x9cd4a0; - .timescale -9 -12; -P_0xa15d68 .param/l "size" 3 305, +C4<0100>; -L_0xa5e190/d .functor NOT 1, L_0xa60dc0, C4<0>, C4<0>, C4<0>; -L_0xa5e190 .delay (10000,10000,10000) L_0xa5e190/d; -L_0xa60c20/d .functor AND 1, L_0xa60fd0, L_0xa61070, L_0xa5e190, C4<1>; -L_0xa60c20 .delay (20000,20000,20000) L_0xa60c20/d; -L_0xa62700/d .functor OR 1, L_0xa62ea0, C4<0>, C4<0>, C4<0>; -L_0xa62700 .delay (20000,20000,20000) L_0xa62700/d; -L_0xa63050/d .functor XOR 1, RS_0x7ffb33a703c8, L_0xa63100, C4<0>, C4<0>; -L_0xa63050 .delay (40000,40000,40000) L_0xa63050/d; -L_0xa62d30/d .functor NOT 1, RS_0x7ffb33a70488, C4<0>, C4<0>, C4<0>; -L_0xa62d30 .delay (10000,10000,10000) L_0xa62d30/d; -L_0xa62e40/d .functor NOT 1, L_0xa633a0, C4<0>, C4<0>, C4<0>; -L_0xa62e40 .delay (10000,10000,10000) L_0xa62e40/d; -L_0xa63440/d .functor AND 1, L_0xa62d30, L_0xa63580, C4<1>, C4<1>; -L_0xa63440 .delay (20000,20000,20000) L_0xa63440/d; -L_0xa631a0/d .functor AND 1, RS_0x7ffb33a70488, L_0xa62e40, C4<1>, C4<1>; -L_0xa631a0 .delay (20000,20000,20000) L_0xa631a0/d; -L_0xa637b0/d .functor AND 1, L_0xa63440, L_0xa60c20, C4<1>, C4<1>; -L_0xa637b0 .delay (20000,20000,20000) L_0xa637b0/d; -L_0xa638b0/d .functor AND 1, L_0xa631a0, L_0xa60c20, C4<1>, C4<1>; -L_0xa638b0 .delay (20000,20000,20000) L_0xa638b0/d; -L_0xa63a00/d .functor OR 1, L_0xa637b0, L_0xa638b0, C4<0>, C4<0>; -L_0xa63a00 .delay (20000,20000,20000) L_0xa63a00/d; -v0xa1e910_0 .alias "A", 3 0, v0xa37070_0; -RS_0x7ffb33a71b68 .resolv tri, L_0xa5bf20, L_0xa5e0f0, L_0xa60350, L_0xa62a90; -v0xa1e9b0_0 .net8 "AddSubSLTSum", 3 0, RS_0x7ffb33a71b68; 4 drivers -v0xa1ea50_0 .alias "B", 3 0, v0xa37220_0; -RS_0x7ffb33a71b98 .resolv tri, L_0xa5b570, L_0xa5d880, L_0xa5fa10, L_0xa62240; -v0xa1ead0_0 .net8 "CarryoutWire", 3 0, RS_0x7ffb33a71b98; 4 drivers -v0xa1eb80_0 .alias "Command", 2 0, v0xa373b0_0; -RS_0x7ffb33a71bc8 .resolv tri, L_0xa5b480, L_0xa5d720, L_0xa5f920, L_0xa62150; -v0xa1ec00_0 .net8 "NewVal", 3 0, RS_0x7ffb33a71bc8; 4 drivers -v0xa1eca0_0 .net "Res0OF1", 0 0, L_0xa631a0; 1 drivers -v0xa1ed40_0 .net "Res1OF0", 0 0, L_0xa63440; 1 drivers -v0xa1ede0_0 .alias "SLTSum", 3 0, v0xa38a50_0; -v0xa1ee80_0 .alias "SLTflag", 0 0, v0xa38ad0_0; -v0xa1ef00_0 .net "SLTflag0", 0 0, L_0xa637b0; 1 drivers -v0xa1efa0_0 .net "SLTflag1", 0 0, L_0xa638b0; 1 drivers -v0xa1f040_0 .net "SLTon", 0 0, L_0xa60c20; 1 drivers -v0xa1f0c0_0 .net *"_s49", 0 0, L_0xa60dc0; 1 drivers -v0xa1f1e0_0 .net *"_s51", 0 0, L_0xa60fd0; 1 drivers -v0xa1f280_0 .net *"_s53", 0 0, L_0xa61070; 1 drivers -v0xa1f140_0 .net *"_s73", 0 0, L_0xa62ea0; 1 drivers -v0xa1f3d0_0 .net/s *"_s74", 0 0, C4<0>; 1 drivers -v0xa1f4f0_0 .net *"_s77", 0 0, L_0xa63100; 1 drivers -v0xa1f570_0 .net *"_s79", 0 0, L_0xa633a0; 1 drivers -v0xa1f450_0 .net *"_s81", 0 0, L_0xa63580; 1 drivers -v0xa1f6a0_0 .alias "carryin", 3 0, v0xa37df0_0; -v0xa1f5f0_0 .alias "carryout", 0 0, v0xa38c80_0; -v0xa1f7e0_0 .net "nAddSubSLTSum", 0 0, L_0xa62e40; 1 drivers -v0xa1f720_0 .net "nCmd2", 0 0, L_0xa5e190; 1 drivers -v0xa1f930_0 .net "nOF", 0 0, L_0xa62d30; 1 drivers -v0xa1f860_0 .alias "overflow", 0 0, v0xa38d00_0; -v0xa1fa90_0 .alias "subtract", 3 0, v0xa38e00_0; -L_0xa5b480 .part/pv L_0xa5aff0, 1, 1, 4; -L_0xa5b570 .part/pv L_0xa5b340, 1, 1, 4; -L_0xa5b660 .part/pv L_0xa5ad20, 1, 1, 4; -L_0xa3d850 .part v0xa38650_0, 1, 1; -L_0xa5b910 .part v0xa38850_0, 1, 1; -L_0xa5ba40 .part RS_0x7ffb33a71b98, 0, 1; -L_0xa5bf20 .part/pv L_0xa5bde0, 1, 1, 4; -L_0xa5bfc0 .part RS_0x7ffb33a71bc8, 1, 1; -L_0xa5c560 .part/pv L_0xa5c420, 1, 1, 4; -L_0xa5c600 .part RS_0x7ffb33a71b68, 1, 1; -L_0xa5c7a0 .part RS_0x7ffb33a71b68, 1, 1; -L_0xa5d720 .part/pv L_0xa5d290, 2, 1, 4; -L_0xa5d880 .part/pv L_0xa5d5e0, 2, 1, 4; -L_0xa5d970 .part/pv L_0xa5cfc0, 2, 1, 4; -L_0xa5dae0 .part v0xa38650_0, 2, 1; -L_0xa5db80 .part v0xa38850_0, 2, 1; -L_0xa5dd40 .part RS_0x7ffb33a71b98, 1, 1; -L_0xa5e0f0 .part/pv L_0xa5dfb0, 2, 1, 4; -L_0xa5e2c0 .part RS_0x7ffb33a71bc8, 2, 1; -L_0xa5e700 .part/pv L_0xa5e5c0, 2, 1, 4; -L_0xa5e220 .part RS_0x7ffb33a71b68, 2, 1; -L_0xa5e8a0 .part RS_0x7ffb33a71b68, 2, 1; -L_0xa5f920 .part/pv L_0xa5f450, 3, 1, 4; -L_0xa5fa10 .part/pv L_0xa5f7c0, 3, 1, 4; -L_0xa5e990 .part/pv L_0xa5f180, 3, 1, 4; -L_0xa5fc20 .part v0xa38650_0, 3, 1; -L_0xa5fb00 .part v0xa38850_0, 3, 1; -L_0xa5fe30 .part RS_0x7ffb33a71b98, 2, 1; -L_0xa60350 .part/pv L_0xa60210, 3, 1, 4; -L_0xa603f0 .part RS_0x7ffb33a71bc8, 3, 1; -L_0xa60980 .part/pv L_0xa60840, 3, 1, 4; -L_0xa60a20 .part RS_0x7ffb33a71b68, 3, 1; -L_0xa604e0 .part RS_0x7ffb33a71b68, 3, 1; -L_0xa60dc0 .part v0xa388d0_0, 2, 1; -L_0xa60fd0 .part v0xa388d0_0, 0, 1; -L_0xa61070 .part v0xa388d0_0, 1, 1; -L_0xa62150 .part/pv L_0xa61ca0, 0, 1, 4; -L_0xa62240 .part/pv L_0xa61ff0, 0, 1, 4; -L_0xa61160 .part/pv L_0xa619d0, 0, 1, 4; -L_0xa62470 .part v0xa38650_0, 0, 1; -L_0xa62330 .part v0xa38850_0, 0, 1; -L_0xa62660 .part RS_0x7ffb33a704b8, 0, 1; -L_0xa62a90 .part/pv L_0xa62950, 0, 1, 4; -L_0xa62b30 .part RS_0x7ffb33a71bc8, 0, 1; -L_0xa62ea0 .part RS_0x7ffb33a71b98, 3, 1; -L_0xa63100 .part RS_0x7ffb33a71b98, 2, 1; -L_0xa633a0 .part RS_0x7ffb33a71b68, 3, 1; -L_0xa63580 .part RS_0x7ffb33a71b68, 3, 1; -L_0xa64010 .part/pv L_0xa63ed0, 0, 1, 4; -L_0xa640b0 .part RS_0x7ffb33a71b68, 0, 1; -S_0xa1d8f0 .scope module, "attempt2" "MiddleAddSubSLT" 3 300, 3 89, S_0xa175f0; - .timescale -9 -12; -L_0xa60e60/d .functor NOT 1, L_0xa62330, C4<0>, C4<0>, C4<0>; -L_0xa60e60 .delay (10000,10000,10000) L_0xa60e60/d; -L_0xa61870/d .functor NOT 1, L_0xa61930, C4<0>, C4<0>, C4<0>; -L_0xa61870 .delay (10000,10000,10000) L_0xa61870/d; -L_0xa619d0/d .functor AND 1, L_0xa61b10, L_0xa61870, C4<1>, C4<1>; -L_0xa619d0 .delay (20000,20000,20000) L_0xa619d0/d; -L_0xa61bb0/d .functor XOR 1, L_0xa62470, L_0xa61600, C4<0>, C4<0>; -L_0xa61bb0 .delay (40000,40000,40000) L_0xa61bb0/d; -L_0xa61ca0/d .functor XOR 1, L_0xa61bb0, L_0xa62660, C4<0>, C4<0>; -L_0xa61ca0 .delay (40000,40000,40000) L_0xa61ca0/d; -L_0xa61d90/d .functor AND 1, L_0xa62470, L_0xa61600, C4<1>, C4<1>; -L_0xa61d90 .delay (20000,20000,20000) L_0xa61d90/d; -L_0xa61f00/d .functor AND 1, L_0xa61bb0, L_0xa62660, C4<1>, C4<1>; -L_0xa61f00 .delay (20000,20000,20000) L_0xa61f00/d; -L_0xa61ff0/d .functor OR 1, L_0xa61d90, L_0xa61f00, C4<0>, C4<0>; -L_0xa61ff0 .delay (20000,20000,20000) L_0xa61ff0/d; -v0xa1df70_0 .net "A", 0 0, L_0xa62470; 1 drivers -v0xa1e030_0 .net "AandB", 0 0, L_0xa61d90; 1 drivers -v0xa1e0d0_0 .net "AddSubSLTSum", 0 0, L_0xa61ca0; 1 drivers -v0xa1e170_0 .net "AxorB", 0 0, L_0xa61bb0; 1 drivers -v0xa1e1f0_0 .net "B", 0 0, L_0xa62330; 1 drivers -v0xa1e2a0_0 .net "BornB", 0 0, L_0xa61600; 1 drivers -v0xa1e360_0 .net "CINandAxorB", 0 0, L_0xa61f00; 1 drivers -v0xa1e3e0_0 .alias "Command", 2 0, v0xa373b0_0; -v0xa1e460_0 .net *"_s3", 0 0, L_0xa61930; 1 drivers -v0xa1e4e0_0 .net *"_s5", 0 0, L_0xa61b10; 1 drivers -v0xa1e580_0 .net "carryin", 0 0, L_0xa62660; 1 drivers -v0xa1e620_0 .net "carryout", 0 0, L_0xa61ff0; 1 drivers -v0xa1e6c0_0 .net "nB", 0 0, L_0xa60e60; 1 drivers -v0xa1e770_0 .net "nCmd2", 0 0, L_0xa61870; 1 drivers -v0xa1e870_0 .net "subtract", 0 0, L_0xa619d0; 1 drivers -L_0xa617d0 .part v0xa388d0_0, 0, 1; -L_0xa61930 .part v0xa388d0_0, 2, 1; -L_0xa61b10 .part v0xa388d0_0, 0, 1; -S_0xa1d9e0 .scope module, "mux0" "TwoInMux" 3 105, 3 8, S_0xa1d8f0; - .timescale -9 -12; -L_0xa61320/d .functor NOT 1, L_0xa617d0, C4<0>, C4<0>, C4<0>; -L_0xa61320 .delay (10000,10000,10000) L_0xa61320/d; -L_0xa613e0/d .functor AND 1, L_0xa62330, L_0xa61320, C4<1>, C4<1>; -L_0xa613e0 .delay (20000,20000,20000) L_0xa613e0/d; -L_0xa614f0/d .functor AND 1, L_0xa60e60, L_0xa617d0, C4<1>, C4<1>; -L_0xa614f0 .delay (20000,20000,20000) L_0xa614f0/d; -L_0xa61600/d .functor OR 1, L_0xa613e0, L_0xa614f0, C4<0>, C4<0>; -L_0xa61600 .delay (20000,20000,20000) L_0xa61600/d; -v0xa1dad0_0 .net "S", 0 0, L_0xa617d0; 1 drivers -v0xa1db90_0 .alias "in0", 0 0, v0xa1e1f0_0; -v0xa1dc30_0 .alias "in1", 0 0, v0xa1e6c0_0; -v0xa1dcd0_0 .net "nS", 0 0, L_0xa61320; 1 drivers -v0xa1dd50_0 .net "out0", 0 0, L_0xa613e0; 1 drivers -v0xa1ddf0_0 .net "out1", 0 0, L_0xa614f0; 1 drivers -v0xa1ded0_0 .alias "outfinal", 0 0, v0xa1e2a0_0; -S_0xa1d380 .scope module, "setSLTres" "TwoInMux" 3 301, 3 8, S_0xa175f0; - .timescale -9 -12; -L_0xa62510/d .functor NOT 1, L_0xa60c20, C4<0>, C4<0>, C4<0>; -L_0xa62510 .delay (10000,10000,10000) L_0xa62510/d; -L_0xa625b0/d .functor AND 1, L_0xa62b30, L_0xa62510, C4<1>, C4<1>; -L_0xa625b0 .delay (20000,20000,20000) L_0xa625b0/d; -L_0xa628b0/d .functor AND 1, C4<0>, L_0xa60c20, C4<1>, C4<1>; -L_0xa628b0 .delay (20000,20000,20000) L_0xa628b0/d; -L_0xa62950/d .functor OR 1, L_0xa625b0, L_0xa628b0, C4<0>, C4<0>; -L_0xa62950 .delay (20000,20000,20000) L_0xa62950/d; -v0xa1d470_0 .alias "S", 0 0, v0xa1f040_0; -v0xa1d510_0 .net "in0", 0 0, L_0xa62b30; 1 drivers -v0xa1d5b0_0 .net "in1", 0 0, C4<0>; 1 drivers -v0xa1d650_0 .net "nS", 0 0, L_0xa62510; 1 drivers -v0xa1d6d0_0 .net "out0", 0 0, L_0xa625b0; 1 drivers -v0xa1d770_0 .net "out1", 0 0, L_0xa628b0; 1 drivers -v0xa1d850_0 .net "outfinal", 0 0, L_0xa62950; 1 drivers -S_0xa1ce60 .scope module, "FinalSLT" "TwoInMux" 3 328, 3 8, S_0xa175f0; - .timescale -9 -12; -L_0xa63b10/d .functor NOT 1, RS_0x7ffb33a70188, C4<0>, C4<0>, C4<0>; -L_0xa63b10 .delay (10000,10000,10000) L_0xa63b10/d; -L_0xa37740/d .functor AND 1, L_0xa640b0, L_0xa63b10, C4<1>, C4<1>; -L_0xa37740 .delay (20000,20000,20000) L_0xa37740/d; -L_0xa63e30/d .functor AND 1, RS_0x7ffb33a70188, RS_0x7ffb33a70188, C4<1>, C4<1>; -L_0xa63e30 .delay (20000,20000,20000) L_0xa63e30/d; -L_0xa63ed0/d .functor OR 1, L_0xa37740, L_0xa63e30, C4<0>, C4<0>; -L_0xa63ed0 .delay (20000,20000,20000) L_0xa63ed0/d; -v0xa1cf50_0 .alias "S", 0 0, v0xa38ad0_0; -v0xa1d020_0 .net "in0", 0 0, L_0xa640b0; 1 drivers -v0xa1d0a0_0 .alias "in1", 0 0, v0xa38ad0_0; -v0xa1d120_0 .net "nS", 0 0, L_0xa63b10; 1 drivers -v0xa1d1a0_0 .net "out0", 0 0, L_0xa37740; 1 drivers -v0xa1d240_0 .net "out1", 0 0, L_0xa63e30; 1 drivers -v0xa1d2e0_0 .net "outfinal", 0 0, L_0xa63ed0; 1 drivers -S_0xa1b150 .scope generate, "addbits[1]" "addbits[1]" 3 307, 3 307, S_0xa175f0; - .timescale -9 -12; -P_0xa1a938 .param/l "i" 3 307, +C4<01>; -S_0xa1be40 .scope module, "attempt" "MiddleAddSubSLT" 3 309, 3 89, S_0xa1b150; - .timescale -9 -12; -L_0xa5a340/d .functor NOT 1, L_0xa5b910, C4<0>, C4<0>, C4<0>; -L_0xa5a340 .delay (10000,10000,10000) L_0xa5a340/d; -L_0xa5abe0/d .functor NOT 1, L_0xa5ac80, C4<0>, C4<0>, C4<0>; -L_0xa5abe0 .delay (10000,10000,10000) L_0xa5abe0/d; -L_0xa5ad20/d .functor AND 1, L_0xa5ae60, L_0xa5abe0, C4<1>, C4<1>; -L_0xa5ad20 .delay (20000,20000,20000) L_0xa5ad20/d; -L_0xa5af00/d .functor XOR 1, L_0xa3d850, L_0xa5a9b0, C4<0>, C4<0>; -L_0xa5af00 .delay (40000,40000,40000) L_0xa5af00/d; -L_0xa5aff0/d .functor XOR 1, L_0xa5af00, L_0xa5ba40, C4<0>, C4<0>; -L_0xa5aff0 .delay (40000,40000,40000) L_0xa5aff0/d; -L_0xa5b0e0/d .functor AND 1, L_0xa3d850, L_0xa5a9b0, C4<1>, C4<1>; -L_0xa5b0e0 .delay (20000,20000,20000) L_0xa5b0e0/d; -L_0xa5b250/d .functor AND 1, L_0xa5af00, L_0xa5ba40, C4<1>, C4<1>; -L_0xa5b250 .delay (20000,20000,20000) L_0xa5b250/d; -L_0xa5b340/d .functor OR 1, L_0xa5b0e0, L_0xa5b250, C4<0>, C4<0>; -L_0xa5b340 .delay (20000,20000,20000) L_0xa5b340/d; -v0xa1c4c0_0 .net "A", 0 0, L_0xa3d850; 1 drivers -v0xa1c580_0 .net "AandB", 0 0, L_0xa5b0e0; 1 drivers -v0xa1c620_0 .net "AddSubSLTSum", 0 0, L_0xa5aff0; 1 drivers -v0xa1c6c0_0 .net "AxorB", 0 0, L_0xa5af00; 1 drivers -v0xa1c740_0 .net "B", 0 0, L_0xa5b910; 1 drivers -v0xa1c7f0_0 .net "BornB", 0 0, L_0xa5a9b0; 1 drivers -v0xa1c8b0_0 .net "CINandAxorB", 0 0, L_0xa5b250; 1 drivers -v0xa1c930_0 .alias "Command", 2 0, v0xa373b0_0; -v0xa1c9b0_0 .net *"_s3", 0 0, L_0xa5ac80; 1 drivers -v0xa1ca30_0 .net *"_s5", 0 0, L_0xa5ae60; 1 drivers -v0xa1cad0_0 .net "carryin", 0 0, L_0xa5ba40; 1 drivers -v0xa1cb70_0 .net "carryout", 0 0, L_0xa5b340; 1 drivers -v0xa1cc10_0 .net "nB", 0 0, L_0xa5a340; 1 drivers -v0xa1ccc0_0 .net "nCmd2", 0 0, L_0xa5abe0; 1 drivers -v0xa1cdc0_0 .net "subtract", 0 0, L_0xa5ad20; 1 drivers -L_0xa5ab40 .part v0xa388d0_0, 0, 1; -L_0xa5ac80 .part v0xa388d0_0, 2, 1; -L_0xa5ae60 .part v0xa388d0_0, 0, 1; -S_0xa1bf30 .scope module, "mux0" "TwoInMux" 3 105, 3 8, S_0xa1be40; - .timescale -9 -12; -L_0xa5a730/d .functor NOT 1, L_0xa5ab40, C4<0>, C4<0>, C4<0>; -L_0xa5a730 .delay (10000,10000,10000) L_0xa5a730/d; -L_0xa5a7d0/d .functor AND 1, L_0xa5b910, L_0xa5a730, C4<1>, C4<1>; -L_0xa5a7d0 .delay (20000,20000,20000) L_0xa5a7d0/d; -L_0xa5a8c0/d .functor AND 1, L_0xa5a340, L_0xa5ab40, C4<1>, C4<1>; -L_0xa5a8c0 .delay (20000,20000,20000) L_0xa5a8c0/d; -L_0xa5a9b0/d .functor OR 1, L_0xa5a7d0, L_0xa5a8c0, C4<0>, C4<0>; -L_0xa5a9b0 .delay (20000,20000,20000) L_0xa5a9b0/d; -v0xa1c020_0 .net "S", 0 0, L_0xa5ab40; 1 drivers -v0xa1c0e0_0 .alias "in0", 0 0, v0xa1c740_0; -v0xa1c180_0 .alias "in1", 0 0, v0xa1cc10_0; -v0xa1c220_0 .net "nS", 0 0, L_0xa5a730; 1 drivers -v0xa1c2a0_0 .net "out0", 0 0, L_0xa5a7d0; 1 drivers -v0xa1c340_0 .net "out1", 0 0, L_0xa5a8c0; 1 drivers -v0xa1c420_0 .alias "outfinal", 0 0, v0xa1c7f0_0; -S_0xa1b8d0 .scope module, "setSLTres2" "TwoInMux" 3 310, 3 8, S_0xa1b150; - .timescale -9 -12; -L_0xa5bae0/d .functor NOT 1, L_0xa60c20, C4<0>, C4<0>, C4<0>; -L_0xa5bae0 .delay (10000,10000,10000) L_0xa5bae0/d; -L_0xa5bc50/d .functor AND 1, L_0xa5bfc0, L_0xa5bae0, C4<1>, C4<1>; -L_0xa5bc50 .delay (20000,20000,20000) L_0xa5bc50/d; -L_0xa5bd40/d .functor AND 1, C4<0>, L_0xa60c20, C4<1>, C4<1>; -L_0xa5bd40 .delay (20000,20000,20000) L_0xa5bd40/d; -L_0xa5bde0/d .functor OR 1, L_0xa5bc50, L_0xa5bd40, C4<0>, C4<0>; -L_0xa5bde0 .delay (20000,20000,20000) L_0xa5bde0/d; -v0xa1b9c0_0 .alias "S", 0 0, v0xa1f040_0; -v0xa1ba60_0 .net "in0", 0 0, L_0xa5bfc0; 1 drivers -v0xa1bb00_0 .net "in1", 0 0, C4<0>; 1 drivers -v0xa1bba0_0 .net "nS", 0 0, L_0xa5bae0; 1 drivers -v0xa1bc20_0 .net "out0", 0 0, L_0xa5bc50; 1 drivers -v0xa1bcc0_0 .net "out1", 0 0, L_0xa5bd40; 1 drivers -v0xa1bda0_0 .net "outfinal", 0 0, L_0xa5bde0; 1 drivers -S_0xa1b2c0 .scope module, "setSLTres3" "TwoInMux" 3 311, 3 8, S_0xa1b150; - .timescale -9 -12; -L_0xa5c1a0/d .functor NOT 1, L_0xa60c20, C4<0>, C4<0>, C4<0>; -L_0xa5c1a0 .delay (10000,10000,10000) L_0xa5c1a0/d; -L_0xa5c290/d .functor AND 1, L_0xa5c600, L_0xa5c1a0, C4<1>, C4<1>; -L_0xa5c290 .delay (20000,20000,20000) L_0xa5c290/d; -L_0xa5c380/d .functor AND 1, L_0xa5c7a0, L_0xa60c20, C4<1>, C4<1>; -L_0xa5c380 .delay (20000,20000,20000) L_0xa5c380/d; -L_0xa5c420/d .functor OR 1, L_0xa5c290, L_0xa5c380, C4<0>, C4<0>; -L_0xa5c420 .delay (20000,20000,20000) L_0xa5c420/d; -v0xa1b3b0_0 .alias "S", 0 0, v0xa1f040_0; -v0xa1b4c0_0 .net "in0", 0 0, L_0xa5c600; 1 drivers -v0xa1b560_0 .net "in1", 0 0, L_0xa5c7a0; 1 drivers -v0xa1b600_0 .net "nS", 0 0, L_0xa5c1a0; 1 drivers -v0xa1b6b0_0 .net "out0", 0 0, L_0xa5c290; 1 drivers -v0xa1b750_0 .net "out1", 0 0, L_0xa5c380; 1 drivers -v0xa1b830_0 .net "outfinal", 0 0, L_0xa5c420; 1 drivers -S_0xa193d0 .scope generate, "addbits[2]" "addbits[2]" 3 307, 3 307, S_0xa175f0; - .timescale -9 -12; -P_0xa18de8 .param/l "i" 3 307, +C4<010>; -S_0xa19fe0 .scope module, "attempt" "MiddleAddSubSLT" 3 309, 3 89, S_0xa193d0; - .timescale -9 -12; -L_0xa5c840/d .functor NOT 1, L_0xa5db80, C4<0>, C4<0>, C4<0>; -L_0xa5c840 .delay (10000,10000,10000) L_0xa5c840/d; -L_0xa5ce80/d .functor NOT 1, L_0xa5cf20, C4<0>, C4<0>, C4<0>; -L_0xa5ce80 .delay (10000,10000,10000) L_0xa5ce80/d; -L_0xa5cfc0/d .functor AND 1, L_0xa5d100, L_0xa5ce80, C4<1>, C4<1>; -L_0xa5cfc0 .delay (20000,20000,20000) L_0xa5cfc0/d; -L_0xa5d1a0/d .functor XOR 1, L_0xa5dae0, L_0xa5cc50, C4<0>, C4<0>; -L_0xa5d1a0 .delay (40000,40000,40000) L_0xa5d1a0/d; -L_0xa5d290/d .functor XOR 1, L_0xa5d1a0, L_0xa5dd40, C4<0>, C4<0>; -L_0xa5d290 .delay (40000,40000,40000) L_0xa5d290/d; -L_0xa5d380/d .functor AND 1, L_0xa5dae0, L_0xa5cc50, C4<1>, C4<1>; -L_0xa5d380 .delay (20000,20000,20000) L_0xa5d380/d; -L_0xa5d4f0/d .functor AND 1, L_0xa5d1a0, L_0xa5dd40, C4<1>, C4<1>; -L_0xa5d4f0 .delay (20000,20000,20000) L_0xa5d4f0/d; -L_0xa5d5e0/d .functor OR 1, L_0xa5d380, L_0xa5d4f0, C4<0>, C4<0>; -L_0xa5d5e0 .delay (20000,20000,20000) L_0xa5d5e0/d; -v0xa1a580_0 .net "A", 0 0, L_0xa5dae0; 1 drivers -v0xa1a640_0 .net "AandB", 0 0, L_0xa5d380; 1 drivers -v0xa1a6e0_0 .net "AddSubSLTSum", 0 0, L_0xa5d290; 1 drivers -v0xa1a780_0 .net "AxorB", 0 0, L_0xa5d1a0; 1 drivers -v0xa1a800_0 .net "B", 0 0, L_0xa5db80; 1 drivers -v0xa1a8b0_0 .net "BornB", 0 0, L_0xa5cc50; 1 drivers -v0xa1a970_0 .net "CINandAxorB", 0 0, L_0xa5d4f0; 1 drivers -v0xa1a9f0_0 .alias "Command", 2 0, v0xa373b0_0; -v0xa10390_0 .net *"_s3", 0 0, L_0xa5cf20; 1 drivers -v0xa10410_0 .net *"_s5", 0 0, L_0xa5d100; 1 drivers -v0xa1ad50_0 .net "carryin", 0 0, L_0xa5dd40; 1 drivers -v0xa1adf0_0 .net "carryout", 0 0, L_0xa5d5e0; 1 drivers -v0xa1af00_0 .net "nB", 0 0, L_0xa5c840; 1 drivers -v0xa1afb0_0 .net "nCmd2", 0 0, L_0xa5ce80; 1 drivers -v0xa1b0b0_0 .net "subtract", 0 0, L_0xa5cfc0; 1 drivers -L_0xa5cde0 .part v0xa388d0_0, 0, 1; -L_0xa5cf20 .part v0xa388d0_0, 2, 1; -L_0xa5d100 .part v0xa388d0_0, 0, 1; -S_0xa1a0d0 .scope module, "mux0" "TwoInMux" 3 105, 3 8, S_0xa19fe0; - .timescale -9 -12; -L_0xa5c9d0/d .functor NOT 1, L_0xa5cde0, C4<0>, C4<0>, C4<0>; -L_0xa5c9d0 .delay (10000,10000,10000) L_0xa5c9d0/d; -L_0xa5ca70/d .functor AND 1, L_0xa5db80, L_0xa5c9d0, C4<1>, C4<1>; -L_0xa5ca70 .delay (20000,20000,20000) L_0xa5ca70/d; -L_0xa5cb60/d .functor AND 1, L_0xa5c840, L_0xa5cde0, C4<1>, C4<1>; -L_0xa5cb60 .delay (20000,20000,20000) L_0xa5cb60/d; -L_0xa5cc50/d .functor OR 1, L_0xa5ca70, L_0xa5cb60, C4<0>, C4<0>; -L_0xa5cc50 .delay (20000,20000,20000) L_0xa5cc50/d; -v0xa1a1c0_0 .net "S", 0 0, L_0xa5cde0; 1 drivers -v0xa1a240_0 .alias "in0", 0 0, v0xa1a800_0; -v0xa1a2c0_0 .alias "in1", 0 0, v0xa1af00_0; -v0xa1a340_0 .net "nS", 0 0, L_0xa5c9d0; 1 drivers -v0xa1a3c0_0 .net "out0", 0 0, L_0xa5ca70; 1 drivers -v0xa1a440_0 .net "out1", 0 0, L_0xa5cb60; 1 drivers -v0xa1a4e0_0 .alias "outfinal", 0 0, v0xa1a8b0_0; -S_0xa19a90 .scope module, "setSLTres2" "TwoInMux" 3 310, 3 8, S_0xa193d0; - .timescale -9 -12; -L_0xa5c740/d .functor NOT 1, L_0xa60c20, C4<0>, C4<0>, C4<0>; -L_0xa5c740 .delay (10000,10000,10000) L_0xa5c740/d; -L_0xa5de70/d .functor AND 1, L_0xa5e2c0, L_0xa5c740, C4<1>, C4<1>; -L_0xa5de70 .delay (20000,20000,20000) L_0xa5de70/d; -L_0xa5df10/d .functor AND 1, C4<0>, L_0xa60c20, C4<1>, C4<1>; -L_0xa5df10 .delay (20000,20000,20000) L_0xa5df10/d; -L_0xa5dfb0/d .functor OR 1, L_0xa5de70, L_0xa5df10, C4<0>, C4<0>; -L_0xa5dfb0 .delay (20000,20000,20000) L_0xa5dfb0/d; -v0xa19b80_0 .alias "S", 0 0, v0xa1f040_0; -v0xa19c20_0 .net "in0", 0 0, L_0xa5e2c0; 1 drivers -v0xa19cc0_0 .net "in1", 0 0, C4<0>; 1 drivers -v0xa19d60_0 .net "nS", 0 0, L_0xa5c740; 1 drivers -v0xa19de0_0 .net "out0", 0 0, L_0xa5de70; 1 drivers -v0xa19e80_0 .net "out1", 0 0, L_0xa5df10; 1 drivers -v0xa19f60_0 .net "outfinal", 0 0, L_0xa5dfb0; 1 drivers -S_0xa19540 .scope module, "setSLTres3" "TwoInMux" 3 311, 3 8, S_0xa193d0; - .timescale -9 -12; -L_0xa4a1d0/d .functor NOT 1, L_0xa60c20, C4<0>, C4<0>, C4<0>; -L_0xa4a1d0 .delay (10000,10000,10000) L_0xa4a1d0/d; -L_0xa5e430/d .functor AND 1, L_0xa5e220, L_0xa4a1d0, C4<1>, C4<1>; -L_0xa5e430 .delay (20000,20000,20000) L_0xa5e430/d; -L_0xa5e520/d .functor AND 1, L_0xa5e8a0, L_0xa60c20, C4<1>, C4<1>; -L_0xa5e520 .delay (20000,20000,20000) L_0xa5e520/d; -L_0xa5e5c0/d .functor OR 1, L_0xa5e430, L_0xa5e520, C4<0>, C4<0>; -L_0xa5e5c0 .delay (20000,20000,20000) L_0xa5e5c0/d; -v0xa19630_0 .alias "S", 0 0, v0xa1f040_0; -v0xa196b0_0 .net "in0", 0 0, L_0xa5e220; 1 drivers -v0xa19750_0 .net "in1", 0 0, L_0xa5e8a0; 1 drivers -v0xa197f0_0 .net "nS", 0 0, L_0xa4a1d0; 1 drivers -v0xa19870_0 .net "out0", 0 0, L_0xa5e430; 1 drivers -v0xa19910_0 .net "out1", 0 0, L_0xa5e520; 1 drivers -v0xa199f0_0 .net "outfinal", 0 0, L_0xa5e5c0; 1 drivers -S_0xa17760 .scope generate, "addbits[3]" "addbits[3]" 3 307, 3 307, S_0xa175f0; - .timescale -9 -12; -P_0xa17858 .param/l "i" 3 307, +C4<011>; -S_0xa183b0 .scope module, "attempt" "MiddleAddSubSLT" 3 309, 3 89, S_0xa17760; - .timescale -9 -12; -L_0xa5e7a0/d .functor NOT 1, L_0xa5fb00, C4<0>, C4<0>, C4<0>; -L_0xa5e7a0 .delay (10000,10000,10000) L_0xa5e7a0/d; -L_0xa5f020/d .functor NOT 1, L_0xa5f0e0, C4<0>, C4<0>, C4<0>; -L_0xa5f020 .delay (10000,10000,10000) L_0xa5f020/d; -L_0xa5f180/d .functor AND 1, L_0xa5f2c0, L_0xa5f020, C4<1>, C4<1>; -L_0xa5f180 .delay (20000,20000,20000) L_0xa5f180/d; -L_0xa5f360/d .functor XOR 1, L_0xa5fc20, L_0xa5edb0, C4<0>, C4<0>; -L_0xa5f360 .delay (40000,40000,40000) L_0xa5f360/d; -L_0xa5f450/d .functor XOR 1, L_0xa5f360, L_0xa5fe30, C4<0>, C4<0>; -L_0xa5f450 .delay (40000,40000,40000) L_0xa5f450/d; -L_0xa5f540/d .functor AND 1, L_0xa5fc20, L_0xa5edb0, C4<1>, C4<1>; -L_0xa5f540 .delay (20000,20000,20000) L_0xa5f540/d; -L_0xa5f6b0/d .functor AND 1, L_0xa5f360, L_0xa5fe30, C4<1>, C4<1>; -L_0xa5f6b0 .delay (20000,20000,20000) L_0xa5f6b0/d; -L_0xa5f7c0/d .functor OR 1, L_0xa5f540, L_0xa5f6b0, C4<0>, C4<0>; -L_0xa5f7c0 .delay (20000,20000,20000) L_0xa5f7c0/d; -v0xa18a30_0 .net "A", 0 0, L_0xa5fc20; 1 drivers -v0xa18af0_0 .net "AandB", 0 0, L_0xa5f540; 1 drivers -v0xa18b90_0 .net "AddSubSLTSum", 0 0, L_0xa5f450; 1 drivers -v0xa18c30_0 .net "AxorB", 0 0, L_0xa5f360; 1 drivers -v0xa18cb0_0 .net "B", 0 0, L_0xa5fb00; 1 drivers -v0xa18d60_0 .net "BornB", 0 0, L_0xa5edb0; 1 drivers -v0xa18e20_0 .net "CINandAxorB", 0 0, L_0xa5f6b0; 1 drivers -v0xa18ea0_0 .alias "Command", 2 0, v0xa373b0_0; -v0xa18f20_0 .net *"_s3", 0 0, L_0xa5f0e0; 1 drivers -v0xa18fa0_0 .net *"_s5", 0 0, L_0xa5f2c0; 1 drivers -v0xa19040_0 .net "carryin", 0 0, L_0xa5fe30; 1 drivers -v0xa190e0_0 .net "carryout", 0 0, L_0xa5f7c0; 1 drivers -v0xa19180_0 .net "nB", 0 0, L_0xa5e7a0; 1 drivers -v0xa19230_0 .net "nCmd2", 0 0, L_0xa5f020; 1 drivers -v0xa19330_0 .net "subtract", 0 0, L_0xa5f180; 1 drivers -L_0xa5ef80 .part v0xa388d0_0, 0, 1; -L_0xa5f0e0 .part v0xa388d0_0, 2, 1; -L_0xa5f2c0 .part v0xa388d0_0, 0, 1; -S_0xa184a0 .scope module, "mux0" "TwoInMux" 3 105, 3 8, S_0xa183b0; - .timescale -9 -12; -L_0xa5eb30/d .functor NOT 1, L_0xa5ef80, C4<0>, C4<0>, C4<0>; -L_0xa5eb30 .delay (10000,10000,10000) L_0xa5eb30/d; -L_0xa5ebd0/d .functor AND 1, L_0xa5fb00, L_0xa5eb30, C4<1>, C4<1>; -L_0xa5ebd0 .delay (20000,20000,20000) L_0xa5ebd0/d; -L_0xa5ecc0/d .functor AND 1, L_0xa5e7a0, L_0xa5ef80, C4<1>, C4<1>; -L_0xa5ecc0 .delay (20000,20000,20000) L_0xa5ecc0/d; -L_0xa5edb0/d .functor OR 1, L_0xa5ebd0, L_0xa5ecc0, C4<0>, C4<0>; -L_0xa5edb0 .delay (20000,20000,20000) L_0xa5edb0/d; -v0xa18590_0 .net "S", 0 0, L_0xa5ef80; 1 drivers -v0xa18650_0 .alias "in0", 0 0, v0xa18cb0_0; -v0xa186f0_0 .alias "in1", 0 0, v0xa19180_0; -v0xa18790_0 .net "nS", 0 0, L_0xa5eb30; 1 drivers -v0xa18810_0 .net "out0", 0 0, L_0xa5ebd0; 1 drivers -v0xa188b0_0 .net "out1", 0 0, L_0xa5ecc0; 1 drivers -v0xa18990_0 .alias "outfinal", 0 0, v0xa18d60_0; -S_0xa17e60 .scope module, "setSLTres2" "TwoInMux" 3 310, 3 8, S_0xa17760; - .timescale -9 -12; -L_0xa5fcc0/d .functor NOT 1, L_0xa60c20, C4<0>, C4<0>, C4<0>; -L_0xa5fcc0 .delay (10000,10000,10000) L_0xa5fcc0/d; -L_0xa5fd20/d .functor AND 1, L_0xa603f0, L_0xa5fcc0, C4<1>, C4<1>; -L_0xa5fd20 .delay (20000,20000,20000) L_0xa5fd20/d; -L_0xa5bbd0/d .functor AND 1, C4<0>, L_0xa60c20, C4<1>, C4<1>; -L_0xa5bbd0 .delay (20000,20000,20000) L_0xa5bbd0/d; -L_0xa60210/d .functor OR 1, L_0xa5fd20, L_0xa5bbd0, C4<0>, C4<0>; -L_0xa60210 .delay (20000,20000,20000) L_0xa60210/d; -v0xa17f50_0 .alias "S", 0 0, v0xa1f040_0; -v0xa17ff0_0 .net "in0", 0 0, L_0xa603f0; 1 drivers -v0xa18070_0 .net "in1", 0 0, C4<0>; 1 drivers -v0xa18110_0 .net "nS", 0 0, L_0xa5fcc0; 1 drivers -v0xa18190_0 .net "out0", 0 0, L_0xa5fd20; 1 drivers -v0xa18230_0 .net "out1", 0 0, L_0xa5bbd0; 1 drivers -v0xa18310_0 .net "outfinal", 0 0, L_0xa60210; 1 drivers -S_0xa178f0 .scope module, "setSLTres3" "TwoInMux" 3 311, 3 8, S_0xa17760; - .timescale -9 -12; -L_0xa5ff60/d .functor NOT 1, L_0xa60c20, C4<0>, C4<0>, C4<0>; -L_0xa5ff60 .delay (10000,10000,10000) L_0xa5ff60/d; -L_0xa60690/d .functor AND 1, L_0xa60a20, L_0xa5ff60, C4<1>, C4<1>; -L_0xa60690 .delay (20000,20000,20000) L_0xa60690/d; -L_0xa607a0/d .functor AND 1, L_0xa604e0, L_0xa60c20, C4<1>, C4<1>; -L_0xa607a0 .delay (20000,20000,20000) L_0xa607a0/d; -L_0xa60840/d .functor OR 1, L_0xa60690, L_0xa607a0, C4<0>, C4<0>; -L_0xa60840 .delay (20000,20000,20000) L_0xa60840/d; -v0xa179e0_0 .alias "S", 0 0, v0xa1f040_0; -v0xa17a80_0 .net "in0", 0 0, L_0xa60a20; 1 drivers -v0xa17b20_0 .net "in1", 0 0, L_0xa604e0; 1 drivers -v0xa17bc0_0 .net "nS", 0 0, L_0xa5ff60; 1 drivers -v0xa17c40_0 .net "out0", 0 0, L_0xa60690; 1 drivers -v0xa17ce0_0 .net "out1", 0 0, L_0xa607a0; 1 drivers -v0xa17dc0_0 .net "outfinal", 0 0, L_0xa60840; 1 drivers -S_0xa10680 .scope module, "trial" "AddSubSLT32" 3 394, 3 205, S_0x9cd4a0; - .timescale -9 -12; -P_0xa10778 .param/l "size" 3 237, +C4<0100>; -L_0xa65e70/d .functor NOT 1, L_0xa69ad0, C4<0>, C4<0>, C4<0>; -L_0xa65e70 .delay (10000,10000,10000) L_0xa65e70/d; -L_0xa69b70/d .functor AND 1, L_0xa69cb0, L_0xa698d0, L_0xa65e70, C4<1>; -L_0xa69b70 .delay (20000,20000,20000) L_0xa69b70/d; -L_0xa6c130/d .functor OR 1, L_0xa6c220, C4<0>, C4<0>, C4<0>; -L_0xa6c130 .delay (20000,20000,20000) L_0xa6c130/d; -L_0xa6bfb0/d .functor XOR 1, RS_0x7ffb33a703c8, L_0xa6c500, C4<0>, C4<0>; -L_0xa6bfb0 .delay (40000,40000,40000) L_0xa6bfb0/d; -L_0xa699e0/d .functor NOT 1, RS_0x7ffb33a70488, C4<0>, C4<0>, C4<0>; -L_0xa699e0 .delay (10000,10000,10000) L_0xa699e0/d; -L_0xa40c30/d .functor NOT 1, L_0xa6c880, C4<0>, C4<0>, C4<0>; -L_0xa40c30 .delay (10000,10000,10000) L_0xa40c30/d; -L_0xa6c3d0/d .functor AND 1, L_0xa699e0, L_0xa6cab0, C4<1>, C4<1>; -L_0xa6c3d0 .delay (20000,20000,20000) L_0xa6c3d0/d; -L_0xa6cb50/d .functor AND 1, RS_0x7ffb33a70488, L_0xa40c30, C4<1>, C4<1>; -L_0xa6cb50 .delay (20000,20000,20000) L_0xa6cb50/d; -L_0xa6cc90/d .functor AND 1, L_0xa6c3d0, L_0xa69b70, C4<1>, C4<1>; -L_0xa6cc90 .delay (20000,20000,20000) L_0xa6cc90/d; -L_0xa6cd90/d .functor AND 1, L_0xa6cb50, L_0xa69b70, C4<1>, C4<1>; -L_0xa6cd90 .delay (20000,20000,20000) L_0xa6cd90/d; -L_0xa6cee0/d .functor OR 1, L_0xa6cc90, L_0xa6cd90, C4<0>, C4<0>; -L_0xa6cee0 .delay (20000,20000,20000) L_0xa6cee0/d; -v0xa16350_0 .alias "A", 3 0, v0xa37070_0; -v0xa163f0_0 .alias "AddSubSLTSum", 3 0, v0xa386d0_0; -v0xa16490_0 .alias "B", 3 0, v0xa37220_0; -RS_0x7ffb33a700c8 .resolv tri, L_0xa652a0, L_0xa66fd0, L_0xa68c00, L_0xa69d50; -v0xa16560_0 .net8 "CarryoutWire", 3 0, RS_0x7ffb33a700c8; 4 drivers -v0xa165e0_0 .alias "Command", 2 0, v0xa373b0_0; -RS_0x7ffb33a700f8 .resolv tri, L_0xa651b0, L_0xa66ee0, L_0xa68b10, L_0xa46410; -v0xa16660_0 .net8 "NewVal", 3 0, RS_0x7ffb33a700f8; 4 drivers -v0xa16700_0 .net "Res0OF1", 0 0, L_0xa6cb50; 1 drivers -v0xa167a0_0 .net "Res1OF0", 0 0, L_0xa6c3d0; 1 drivers -v0xa16890_0 .alias "SLTflag", 0 0, v0xa38ad0_0; -v0xa16930_0 .net "SLTflag0", 0 0, L_0xa6cc90; 1 drivers -v0xa169d0_0 .net "SLTflag1", 0 0, L_0xa6cd90; 1 drivers -v0xa16a70_0 .net "SLTon", 0 0, L_0xa69b70; 1 drivers -v0xa16b80_0 .net *"_s37", 0 0, L_0xa69ad0; 1 drivers -v0xa16c20_0 .net *"_s39", 0 0, L_0xa69cb0; 1 drivers -v0xa16d40_0 .net *"_s41", 0 0, L_0xa698d0; 1 drivers -v0xa16de0_0 .net *"_s61", 0 0, L_0xa6c220; 1 drivers -v0xa16ca0_0 .net/s *"_s62", 0 0, C4<0>; 1 drivers -v0xa16f30_0 .net *"_s65", 0 0, L_0xa6c500; 1 drivers -v0xa17050_0 .net *"_s67", 0 0, L_0xa6c880; 1 drivers -v0xa170d0_0 .net *"_s69", 0 0, L_0xa6cab0; 1 drivers -v0xa16fb0_0 .alias "carryin", 3 0, v0xa37df0_0; -v0xa17200_0 .alias "carryout", 0 0, v0xa38c80_0; -v0xa17150_0 .net "nAddSubSLTSum", 0 0, L_0xa40c30; 1 drivers -v0xa17340_0 .net "nCmd2", 0 0, L_0xa65e70; 1 drivers -v0xa172a0_0 .net "nOF", 0 0, L_0xa699e0; 1 drivers -v0xa17490_0 .alias "overflow", 0 0, v0xa38d00_0; -v0xa173e0_0 .alias "subtract", 3 0, v0xa38e00_0; -L_0xa651b0 .part/pv L_0xa64d00, 1, 1, 4; -L_0xa652a0 .part/pv L_0xa65050, 1, 1, 4; -L_0xa65390 .part/pv L_0xa64a30, 1, 1, 4; -L_0xa65480 .part v0xa38650_0, 1, 1; -L_0xa65520 .part v0xa38850_0, 1, 1; -L_0xa65650 .part RS_0x7ffb33a700c8, 0, 1; -L_0xa65ad0 .part/pv L_0xa65990, 1, 1, 4; -L_0xa40850 .part RS_0x7ffb33a700f8, 1, 1; -L_0xa66ee0 .part/pv L_0xa66a30, 2, 1, 4; -L_0xa66fd0 .part/pv L_0xa66d80, 2, 1, 4; -L_0xa67120 .part/pv L_0xa66760, 2, 1, 4; -L_0xa671c0 .part v0xa38650_0, 2, 1; -L_0xa67260 .part v0xa38850_0, 2, 1; -L_0xa67390 .part RS_0x7ffb33a700c8, 1, 1; -L_0xa67820 .part/pv L_0xa67730, 2, 1, 4; -L_0xa678c0 .part RS_0x7ffb33a700f8, 2, 1; -L_0xa68b10 .part/pv L_0xa68660, 3, 1, 4; -L_0xa68c00 .part/pv L_0xa689b0, 3, 1, 4; -L_0xa68d90 .part/pv L_0xa68390, 3, 1, 4; -L_0xa68e30 .part v0xa38650_0, 3, 1; -L_0xa68cf0 .part v0xa38850_0, 3, 1; -L_0xa46df0 .part RS_0x7ffb33a700c8, 2, 1; -L_0xa69740 .part/pv L_0xa47050, 3, 1, 4; -L_0xa697e0 .part RS_0x7ffb33a700f8, 3, 1; -L_0xa69ad0 .part v0xa388d0_0, 2, 1; -L_0xa69cb0 .part v0xa388d0_0, 0, 1; -L_0xa698d0 .part v0xa388d0_0, 1, 1; -L_0xa46410 .part/pv L_0xa45f40, 0, 1, 4; -L_0xa69d50 .part/pv L_0xa462b0, 0, 1, 4; -L_0xa6b7f0 .part/pv L_0xa6a600, 0, 1, 4; -L_0xa46500 .part v0xa38650_0, 0, 1; -L_0xa6b9e0 .part v0xa38850_0, 0, 1; -L_0xa6b8e0 .part RS_0x7ffb33a704b8, 0, 1; -L_0xa6be60 .part/pv L_0xa6bd20, 0, 1, 4; -L_0xa6bb10 .part RS_0x7ffb33a700f8, 0, 1; -L_0xa6c220 .part RS_0x7ffb33a700c8, 3, 1; -L_0xa6c500 .part RS_0x7ffb33a700c8, 2, 1; -L_0xa6c880 .part RS_0x7ffb33a70098, 3, 1; -L_0xa6cab0 .part RS_0x7ffb33a70098, 3, 1; -S_0xa15330 .scope module, "attempt2" "MiddleAddSubSLT" 3 233, 3 89, S_0xa10680; - .timescale -9 -12; -L_0xa69e80/d .functor NOT 1, L_0xa6b9e0, C4<0>, C4<0>, C4<0>; -L_0xa69e80 .delay (10000,10000,10000) L_0xa69e80/d; -L_0xa6a4c0/d .functor NOT 1, L_0xa6a560, C4<0>, C4<0>, C4<0>; -L_0xa6a4c0 .delay (10000,10000,10000) L_0xa6a4c0/d; -L_0xa6a600/d .functor AND 1, L_0xa6a740, L_0xa6a4c0, C4<1>, C4<1>; -L_0xa6a600 .delay (20000,20000,20000) L_0xa6a600/d; -L_0xa45e50/d .functor XOR 1, L_0xa46500, L_0xa6a290, C4<0>, C4<0>; -L_0xa45e50 .delay (40000,40000,40000) L_0xa45e50/d; -L_0xa45f40/d .functor XOR 1, L_0xa45e50, L_0xa6b8e0, C4<0>, C4<0>; -L_0xa45f40 .delay (40000,40000,40000) L_0xa45f40/d; -L_0xa46030/d .functor AND 1, L_0xa46500, L_0xa6a290, C4<1>, C4<1>; -L_0xa46030 .delay (20000,20000,20000) L_0xa46030/d; -L_0xa461a0/d .functor AND 1, L_0xa45e50, L_0xa6b8e0, C4<1>, C4<1>; -L_0xa461a0 .delay (20000,20000,20000) L_0xa461a0/d; -L_0xa462b0/d .functor OR 1, L_0xa46030, L_0xa461a0, C4<0>, C4<0>; -L_0xa462b0 .delay (20000,20000,20000) L_0xa462b0/d; -v0xa159b0_0 .net "A", 0 0, L_0xa46500; 1 drivers -v0xa15a70_0 .net "AandB", 0 0, L_0xa46030; 1 drivers -v0xa15b10_0 .net "AddSubSLTSum", 0 0, L_0xa45f40; 1 drivers -v0xa15bb0_0 .net "AxorB", 0 0, L_0xa45e50; 1 drivers -v0xa15c30_0 .net "B", 0 0, L_0xa6b9e0; 1 drivers -v0xa15ce0_0 .net "BornB", 0 0, L_0xa6a290; 1 drivers -v0xa15da0_0 .net "CINandAxorB", 0 0, L_0xa461a0; 1 drivers -v0xa15e20_0 .alias "Command", 2 0, v0xa373b0_0; -v0xa15ea0_0 .net *"_s3", 0 0, L_0xa6a560; 1 drivers -v0xa15f20_0 .net *"_s5", 0 0, L_0xa6a740; 1 drivers -v0xa15fc0_0 .net "carryin", 0 0, L_0xa6b8e0; 1 drivers -v0xa16060_0 .net "carryout", 0 0, L_0xa462b0; 1 drivers -v0xa16100_0 .net "nB", 0 0, L_0xa69e80; 1 drivers -v0xa161b0_0 .net "nCmd2", 0 0, L_0xa6a4c0; 1 drivers -v0xa162b0_0 .net "subtract", 0 0, L_0xa6a600; 1 drivers -L_0xa6a420 .part v0xa388d0_0, 0, 1; -L_0xa6a560 .part v0xa388d0_0, 2, 1; -L_0xa6a740 .part v0xa388d0_0, 0, 1; -S_0xa15420 .scope module, "mux0" "TwoInMux" 3 105, 3 8, S_0xa15330; - .timescale -9 -12; -L_0xa6a010/d .functor NOT 1, L_0xa6a420, C4<0>, C4<0>, C4<0>; -L_0xa6a010 .delay (10000,10000,10000) L_0xa6a010/d; -L_0xa6a0b0/d .functor AND 1, L_0xa6b9e0, L_0xa6a010, C4<1>, C4<1>; -L_0xa6a0b0 .delay (20000,20000,20000) L_0xa6a0b0/d; -L_0xa6a1a0/d .functor AND 1, L_0xa69e80, L_0xa6a420, C4<1>, C4<1>; -L_0xa6a1a0 .delay (20000,20000,20000) L_0xa6a1a0/d; -L_0xa6a290/d .functor OR 1, L_0xa6a0b0, L_0xa6a1a0, C4<0>, C4<0>; -L_0xa6a290 .delay (20000,20000,20000) L_0xa6a290/d; -v0xa15510_0 .net "S", 0 0, L_0xa6a420; 1 drivers -v0xa155d0_0 .alias "in0", 0 0, v0xa15c30_0; -v0xa15670_0 .alias "in1", 0 0, v0xa16100_0; -v0xa15710_0 .net "nS", 0 0, L_0xa6a010; 1 drivers -v0xa15790_0 .net "out0", 0 0, L_0xa6a0b0; 1 drivers -v0xa15830_0 .net "out1", 0 0, L_0xa6a1a0; 1 drivers -v0xa15910_0 .alias "outfinal", 0 0, v0xa15ce0_0; -S_0xa14dd0 .scope module, "setSLTres" "TwoInMux" 3 234, 3 8, S_0xa10680; - .timescale -9 -12; -L_0xa6b980/d .functor NOT 1, L_0xa69b70, C4<0>, C4<0>, C4<0>; -L_0xa6b980 .delay (10000,10000,10000) L_0xa6b980/d; -L_0xa6bc20/d .functor AND 1, L_0xa6bb10, L_0xa6b980, C4<1>, C4<1>; -L_0xa6bc20 .delay (20000,20000,20000) L_0xa6bc20/d; -L_0xa6bc80/d .functor AND 1, C4<0>, L_0xa69b70, C4<1>, C4<1>; -L_0xa6bc80 .delay (20000,20000,20000) L_0xa6bc80/d; -L_0xa6bd20/d .functor OR 1, L_0xa6bc20, L_0xa6bc80, C4<0>, C4<0>; -L_0xa6bd20 .delay (20000,20000,20000) L_0xa6bd20/d; -v0xa14ec0_0 .alias "S", 0 0, v0xa16a70_0; -v0xa14f60_0 .net "in0", 0 0, L_0xa6bb10; 1 drivers -v0xa15000_0 .net "in1", 0 0, C4<0>; 1 drivers -v0xa150a0_0 .net "nS", 0 0, L_0xa6b980; 1 drivers -v0xa15150_0 .net "out0", 0 0, L_0xa6bc20; 1 drivers -v0xa151f0_0 .net "out1", 0 0, L_0xa6bc80; 1 drivers -v0xa15290_0 .net "outfinal", 0 0, L_0xa6bd20; 1 drivers -S_0xa136f0 .scope generate, "addbits[1]" "addbits[1]" 3 239, 3 239, S_0xa10680; - .timescale -9 -12; -P_0xa13108 .param/l "i" 3 239, +C4<01>; -S_0xa13db0 .scope module, "attempt" "MiddleAddSubSLT" 3 241, 3 89, S_0xa136f0; - .timescale -9 -12; -L_0xa63620/d .functor NOT 1, L_0xa65520, C4<0>, C4<0>, C4<0>; -L_0xa63620 .delay (10000,10000,10000) L_0xa63620/d; -L_0xa648d0/d .functor NOT 1, L_0xa64990, C4<0>, C4<0>, C4<0>; -L_0xa648d0 .delay (10000,10000,10000) L_0xa648d0/d; -L_0xa64a30/d .functor AND 1, L_0xa64b70, L_0xa648d0, C4<1>, C4<1>; -L_0xa64a30 .delay (20000,20000,20000) L_0xa64a30/d; -L_0xa64c10/d .functor XOR 1, L_0xa65480, L_0xa64660, C4<0>, C4<0>; -L_0xa64c10 .delay (40000,40000,40000) L_0xa64c10/d; -L_0xa64d00/d .functor XOR 1, L_0xa64c10, L_0xa65650, C4<0>, C4<0>; -L_0xa64d00 .delay (40000,40000,40000) L_0xa64d00/d; -L_0xa64df0/d .functor AND 1, L_0xa65480, L_0xa64660, C4<1>, C4<1>; -L_0xa64df0 .delay (20000,20000,20000) L_0xa64df0/d; -L_0xa64f60/d .functor AND 1, L_0xa64c10, L_0xa65650, C4<1>, C4<1>; -L_0xa64f60 .delay (20000,20000,20000) L_0xa64f60/d; -L_0xa65050/d .functor OR 1, L_0xa64df0, L_0xa64f60, C4<0>, C4<0>; -L_0xa65050 .delay (20000,20000,20000) L_0xa65050/d; -v0xa14430_0 .net "A", 0 0, L_0xa65480; 1 drivers -v0xa144f0_0 .net "AandB", 0 0, L_0xa64df0; 1 drivers -v0xa14590_0 .net "AddSubSLTSum", 0 0, L_0xa64d00; 1 drivers -v0xa14630_0 .net "AxorB", 0 0, L_0xa64c10; 1 drivers -v0xa146b0_0 .net "B", 0 0, L_0xa65520; 1 drivers -v0xa14760_0 .net "BornB", 0 0, L_0xa64660; 1 drivers -v0xa14820_0 .net "CINandAxorB", 0 0, L_0xa64f60; 1 drivers -v0xa148a0_0 .alias "Command", 2 0, v0xa373b0_0; -v0xa14920_0 .net *"_s3", 0 0, L_0xa64990; 1 drivers -v0xa149a0_0 .net *"_s5", 0 0, L_0xa64b70; 1 drivers -v0xa14a40_0 .net "carryin", 0 0, L_0xa65650; 1 drivers -v0xa14ae0_0 .net "carryout", 0 0, L_0xa65050; 1 drivers -v0xa14b80_0 .net "nB", 0 0, L_0xa63620; 1 drivers -v0xa14c30_0 .net "nCmd2", 0 0, L_0xa648d0; 1 drivers -v0xa14d30_0 .net "subtract", 0 0, L_0xa64a30; 1 drivers -L_0xa64830 .part v0xa388d0_0, 0, 1; -L_0xa64990 .part v0xa388d0_0, 2, 1; -L_0xa64b70 .part v0xa388d0_0, 0, 1; -S_0xa13ea0 .scope module, "mux0" "TwoInMux" 3 105, 3 8, S_0xa13db0; - .timescale -9 -12; -L_0xa64380/d .functor NOT 1, L_0xa64830, C4<0>, C4<0>, C4<0>; -L_0xa64380 .delay (10000,10000,10000) L_0xa64380/d; -L_0xa64440/d .functor AND 1, L_0xa65520, L_0xa64380, C4<1>, C4<1>; -L_0xa64440 .delay (20000,20000,20000) L_0xa64440/d; -L_0xa64550/d .functor AND 1, L_0xa63620, L_0xa64830, C4<1>, C4<1>; -L_0xa64550 .delay (20000,20000,20000) L_0xa64550/d; -L_0xa64660/d .functor OR 1, L_0xa64440, L_0xa64550, C4<0>, C4<0>; -L_0xa64660 .delay (20000,20000,20000) L_0xa64660/d; -v0xa13f90_0 .net "S", 0 0, L_0xa64830; 1 drivers -v0xa14050_0 .alias "in0", 0 0, v0xa146b0_0; -v0xa140f0_0 .alias "in1", 0 0, v0xa14b80_0; -v0xa14190_0 .net "nS", 0 0, L_0xa64380; 1 drivers -v0xa14210_0 .net "out0", 0 0, L_0xa64440; 1 drivers -v0xa142b0_0 .net "out1", 0 0, L_0xa64550; 1 drivers -v0xa14390_0 .alias "outfinal", 0 0, v0xa14760_0; -S_0xa13860 .scope module, "setSLTres" "TwoInMux" 3 242, 3 8, S_0xa136f0; - .timescale -9 -12; -L_0xa656f0/d .functor NOT 1, L_0xa69b70, C4<0>, C4<0>, C4<0>; -L_0xa656f0 .delay (10000,10000,10000) L_0xa656f0/d; -L_0xa657e0/d .functor AND 1, L_0xa40850, L_0xa656f0, C4<1>, C4<1>; -L_0xa657e0 .delay (20000,20000,20000) L_0xa657e0/d; -L_0xa658f0/d .functor AND 1, C4<0>, L_0xa69b70, C4<1>, C4<1>; -L_0xa658f0 .delay (20000,20000,20000) L_0xa658f0/d; -L_0xa65990/d .functor OR 1, L_0xa657e0, L_0xa658f0, C4<0>, C4<0>; -L_0xa65990 .delay (20000,20000,20000) L_0xa65990/d; -v0xa13950_0 .alias "S", 0 0, v0xa16a70_0; -v0xa139d0_0 .net "in0", 0 0, L_0xa40850; 1 drivers -v0xa13a70_0 .net "in1", 0 0, C4<0>; 1 drivers -v0xa13b10_0 .net "nS", 0 0, L_0xa656f0; 1 drivers -v0xa13b90_0 .net "out0", 0 0, L_0xa657e0; 1 drivers -v0xa13c30_0 .net "out1", 0 0, L_0xa658f0; 1 drivers -v0xa13d10_0 .net "outfinal", 0 0, L_0xa65990; 1 drivers -S_0xa11fd0 .scope generate, "addbits[2]" "addbits[2]" 3 239, 3 239, S_0xa10680; - .timescale -9 -12; -P_0xa11918 .param/l "i" 3 239, +C4<010>; -S_0xa126d0 .scope module, "attempt" "MiddleAddSubSLT" 3 241, 3 89, S_0xa11fd0; - .timescale -9 -12; -L_0xa65f00/d .functor NOT 1, L_0xa67260, C4<0>, C4<0>, C4<0>; -L_0xa65f00 .delay (10000,10000,10000) L_0xa65f00/d; -L_0xa66600/d .functor NOT 1, L_0xa666c0, C4<0>, C4<0>, C4<0>; -L_0xa66600 .delay (10000,10000,10000) L_0xa66600/d; -L_0xa66760/d .functor AND 1, L_0xa668a0, L_0xa66600, C4<1>, C4<1>; -L_0xa66760 .delay (20000,20000,20000) L_0xa66760/d; -L_0xa66940/d .functor XOR 1, L_0xa671c0, L_0xa66390, C4<0>, C4<0>; -L_0xa66940 .delay (40000,40000,40000) L_0xa66940/d; -L_0xa66a30/d .functor XOR 1, L_0xa66940, L_0xa67390, C4<0>, C4<0>; -L_0xa66a30 .delay (40000,40000,40000) L_0xa66a30/d; -L_0xa66b20/d .functor AND 1, L_0xa671c0, L_0xa66390, C4<1>, C4<1>; -L_0xa66b20 .delay (20000,20000,20000) L_0xa66b20/d; -L_0xa66c90/d .functor AND 1, L_0xa66940, L_0xa67390, C4<1>, C4<1>; -L_0xa66c90 .delay (20000,20000,20000) L_0xa66c90/d; -L_0xa66d80/d .functor OR 1, L_0xa66b20, L_0xa66c90, C4<0>, C4<0>; -L_0xa66d80 .delay (20000,20000,20000) L_0xa66d80/d; -v0xa12d50_0 .net "A", 0 0, L_0xa671c0; 1 drivers -v0xa12e10_0 .net "AandB", 0 0, L_0xa66b20; 1 drivers -v0xa12eb0_0 .net "AddSubSLTSum", 0 0, L_0xa66a30; 1 drivers -v0xa12f50_0 .net "AxorB", 0 0, L_0xa66940; 1 drivers -v0xa12fd0_0 .net "B", 0 0, L_0xa67260; 1 drivers -v0xa13080_0 .net "BornB", 0 0, L_0xa66390; 1 drivers -v0xa13140_0 .net "CINandAxorB", 0 0, L_0xa66c90; 1 drivers -v0xa131c0_0 .alias "Command", 2 0, v0xa373b0_0; -v0xa13240_0 .net *"_s3", 0 0, L_0xa666c0; 1 drivers -v0xa132c0_0 .net *"_s5", 0 0, L_0xa668a0; 1 drivers -v0xa13360_0 .net "carryin", 0 0, L_0xa67390; 1 drivers -v0xa13400_0 .net "carryout", 0 0, L_0xa66d80; 1 drivers -v0xa134a0_0 .net "nB", 0 0, L_0xa65f00; 1 drivers -v0xa13550_0 .net "nCmd2", 0 0, L_0xa66600; 1 drivers -v0xa13650_0 .net "subtract", 0 0, L_0xa66760; 1 drivers -L_0xa66560 .part v0xa388d0_0, 0, 1; -L_0xa666c0 .part v0xa388d0_0, 2, 1; -L_0xa668a0 .part v0xa388d0_0, 0, 1; -S_0xa127c0 .scope module, "mux0" "TwoInMux" 3 105, 3 8, S_0xa126d0; - .timescale -9 -12; -L_0xa660b0/d .functor NOT 1, L_0xa66560, C4<0>, C4<0>, C4<0>; -L_0xa660b0 .delay (10000,10000,10000) L_0xa660b0/d; -L_0xa66170/d .functor AND 1, L_0xa67260, L_0xa660b0, C4<1>, C4<1>; -L_0xa66170 .delay (20000,20000,20000) L_0xa66170/d; -L_0xa66280/d .functor AND 1, L_0xa65f00, L_0xa66560, C4<1>, C4<1>; -L_0xa66280 .delay (20000,20000,20000) L_0xa66280/d; -L_0xa66390/d .functor OR 1, L_0xa66170, L_0xa66280, C4<0>, C4<0>; -L_0xa66390 .delay (20000,20000,20000) L_0xa66390/d; -v0xa128b0_0 .net "S", 0 0, L_0xa66560; 1 drivers -v0xa12970_0 .alias "in0", 0 0, v0xa12fd0_0; -v0xa12a10_0 .alias "in1", 0 0, v0xa134a0_0; -v0xa12ab0_0 .net "nS", 0 0, L_0xa660b0; 1 drivers -v0xa12b30_0 .net "out0", 0 0, L_0xa66170; 1 drivers -v0xa12bd0_0 .net "out1", 0 0, L_0xa66280; 1 drivers -v0xa12cb0_0 .alias "outfinal", 0 0, v0xa13080_0; -S_0xa12140 .scope module, "setSLTres" "TwoInMux" 3 242, 3 8, S_0xa11fd0; - .timescale -9 -12; -L_0xa670c0/d .functor NOT 1, L_0xa69b70, C4<0>, C4<0>, C4<0>; -L_0xa670c0 .delay (10000,10000,10000) L_0xa670c0/d; -L_0xa67500/d .functor AND 1, L_0xa678c0, L_0xa670c0, C4<1>, C4<1>; -L_0xa67500 .delay (20000,20000,20000) L_0xa67500/d; -L_0xa675c0/d .functor AND 1, C4<0>, L_0xa69b70, C4<1>, C4<1>; -L_0xa675c0 .delay (20000,20000,20000) L_0xa675c0/d; -L_0xa67730/d .functor OR 1, L_0xa67500, L_0xa675c0, C4<0>, C4<0>; -L_0xa67730 .delay (20000,20000,20000) L_0xa67730/d; -v0xa12230_0 .alias "S", 0 0, v0xa16a70_0; -v0xa122e0_0 .net "in0", 0 0, L_0xa678c0; 1 drivers -v0xa12360_0 .net "in1", 0 0, C4<0>; 1 drivers -v0xa12400_0 .net "nS", 0 0, L_0xa670c0; 1 drivers -v0xa124b0_0 .net "out0", 0 0, L_0xa67500; 1 drivers -v0xa12550_0 .net "out1", 0 0, L_0xa675c0; 1 drivers -v0xa12630_0 .net "outfinal", 0 0, L_0xa67730; 1 drivers -S_0xa107f0 .scope generate, "addbits[3]" "addbits[3]" 3 239, 3 239, S_0xa10680; - .timescale -9 -12; -P_0xa108e8 .param/l "i" 3 239, +C4<011>; -S_0xa10ee0 .scope module, "attempt" "MiddleAddSubSLT" 3 241, 3 89, S_0xa107f0; - .timescale -9 -12; -L_0xa67b10/d .functor NOT 1, L_0xa68cf0, C4<0>, C4<0>, C4<0>; -L_0xa67b10 .delay (10000,10000,10000) L_0xa67b10/d; -L_0xa68230/d .functor NOT 1, L_0xa682f0, C4<0>, C4<0>, C4<0>; -L_0xa68230 .delay (10000,10000,10000) L_0xa68230/d; -L_0xa68390/d .functor AND 1, L_0xa684d0, L_0xa68230, C4<1>, C4<1>; -L_0xa68390 .delay (20000,20000,20000) L_0xa68390/d; -L_0xa68570/d .functor XOR 1, L_0xa68e30, L_0xa67fc0, C4<0>, C4<0>; -L_0xa68570 .delay (40000,40000,40000) L_0xa68570/d; -L_0xa68660/d .functor XOR 1, L_0xa68570, L_0xa46df0, C4<0>, C4<0>; -L_0xa68660 .delay (40000,40000,40000) L_0xa68660/d; -L_0xa68750/d .functor AND 1, L_0xa68e30, L_0xa67fc0, C4<1>, C4<1>; -L_0xa68750 .delay (20000,20000,20000) L_0xa68750/d; -L_0xa688c0/d .functor AND 1, L_0xa68570, L_0xa46df0, C4<1>, C4<1>; -L_0xa688c0 .delay (20000,20000,20000) L_0xa688c0/d; -L_0xa689b0/d .functor OR 1, L_0xa68750, L_0xa688c0, C4<0>, C4<0>; -L_0xa689b0 .delay (20000,20000,20000) L_0xa689b0/d; -v0xa11560_0 .net "A", 0 0, L_0xa68e30; 1 drivers -v0xa11620_0 .net "AandB", 0 0, L_0xa68750; 1 drivers -v0xa116c0_0 .net "AddSubSLTSum", 0 0, L_0xa68660; 1 drivers -v0xa11760_0 .net "AxorB", 0 0, L_0xa68570; 1 drivers -v0xa117e0_0 .net "B", 0 0, L_0xa68cf0; 1 drivers -v0xa11890_0 .net "BornB", 0 0, L_0xa67fc0; 1 drivers -v0xa11950_0 .net "CINandAxorB", 0 0, L_0xa688c0; 1 drivers -v0xa119d0_0 .alias "Command", 2 0, v0xa373b0_0; -v0xa11a50_0 .net *"_s3", 0 0, L_0xa682f0; 1 drivers -v0xa11ad0_0 .net *"_s5", 0 0, L_0xa684d0; 1 drivers -v0xa11bd0_0 .net "carryin", 0 0, L_0xa46df0; 1 drivers -v0xa11c70_0 .net "carryout", 0 0, L_0xa689b0; 1 drivers -v0xa11d80_0 .net "nB", 0 0, L_0xa67b10; 1 drivers -v0xa11e30_0 .net "nCmd2", 0 0, L_0xa68230; 1 drivers -v0xa11f30_0 .net "subtract", 0 0, L_0xa68390; 1 drivers -L_0xa68190 .part v0xa388d0_0, 0, 1; -L_0xa682f0 .part v0xa388d0_0, 2, 1; -L_0xa684d0 .part v0xa388d0_0, 0, 1; -S_0xa10fd0 .scope module, "mux0" "TwoInMux" 3 105, 3 8, S_0xa10ee0; - .timescale -9 -12; -L_0xa67ce0/d .functor NOT 1, L_0xa68190, C4<0>, C4<0>, C4<0>; -L_0xa67ce0 .delay (10000,10000,10000) L_0xa67ce0/d; -L_0xa67da0/d .functor AND 1, L_0xa68cf0, L_0xa67ce0, C4<1>, C4<1>; -L_0xa67da0 .delay (20000,20000,20000) L_0xa67da0/d; -L_0xa67eb0/d .functor AND 1, L_0xa67b10, L_0xa68190, C4<1>, C4<1>; -L_0xa67eb0 .delay (20000,20000,20000) L_0xa67eb0/d; -L_0xa67fc0/d .functor OR 1, L_0xa67da0, L_0xa67eb0, C4<0>, C4<0>; -L_0xa67fc0 .delay (20000,20000,20000) L_0xa67fc0/d; -v0xa110c0_0 .net "S", 0 0, L_0xa68190; 1 drivers -v0xa11180_0 .alias "in0", 0 0, v0xa117e0_0; -v0xa11220_0 .alias "in1", 0 0, v0xa11d80_0; -v0xa112c0_0 .net "nS", 0 0, L_0xa67ce0; 1 drivers -v0xa11340_0 .net "out0", 0 0, L_0xa67da0; 1 drivers -v0xa113e0_0 .net "out1", 0 0, L_0xa67eb0; 1 drivers -v0xa114c0_0 .alias "outfinal", 0 0, v0xa11890_0; -S_0xa10960 .scope module, "setSLTres" "TwoInMux" 3 242, 3 8, S_0xa107f0; - .timescale -9 -12; -L_0xa5d810/d .functor NOT 1, L_0xa69b70, C4<0>, C4<0>, C4<0>; -L_0xa5d810 .delay (10000,10000,10000) L_0xa5d810/d; -L_0xa5da60/d .functor AND 1, L_0xa697e0, L_0xa5d810, C4<1>, C4<1>; -L_0xa5da60 .delay (20000,20000,20000) L_0xa5da60/d; -L_0xa46d00/d .functor AND 1, C4<0>, L_0xa69b70, C4<1>, C4<1>; -L_0xa46d00 .delay (20000,20000,20000) L_0xa46d00/d; -L_0xa47050/d .functor OR 1, L_0xa5da60, L_0xa46d00, C4<0>, C4<0>; -L_0xa47050 .delay (20000,20000,20000) L_0xa47050/d; -v0xa10a50_0 .alias "S", 0 0, v0xa16a70_0; -v0xa10ad0_0 .net "in0", 0 0, L_0xa697e0; 1 drivers -v0xa10b70_0 .net "in1", 0 0, C4<0>; 1 drivers -v0xa10c10_0 .net "nS", 0 0, L_0xa5d810; 1 drivers -v0xa10cc0_0 .net "out0", 0 0, L_0xa5da60; 1 drivers -v0xa10d60_0 .net "out1", 0 0, L_0xa46d00; 1 drivers -v0xa10e40_0 .net "outfinal", 0 0, L_0xa47050; 1 drivers -S_0xa0d440 .scope module, "trial1" "AndNand32" 3 395, 3 154, S_0x9cd4a0; - .timescale -9 -12; -P_0xa0cec8 .param/l "size" 3 161, +C4<0100>; -v0xa0d330_0 .alias "A", 3 0, v0xa37070_0; -v0xa104a0_0 .alias "AndNandOut", 3 0, v0xa387d0_0; -v0xa10520_0 .alias "B", 3 0, v0xa37220_0; -v0xa105d0_0 .alias "Command", 2 0, v0xa373b0_0; -L_0xa6d7c0 .part/pv L_0xa6d550, 1, 1, 4; -L_0xa6d880 .part v0xa38650_0, 1, 1; -L_0xa6d920 .part v0xa38850_0, 1, 1; -L_0xa6e230 .part/pv L_0xa6dfc0, 2, 1, 4; -L_0xa6e2d0 .part v0xa38650_0, 2, 1; -L_0xa6e370 .part v0xa38850_0, 2, 1; -L_0xa6eca0 .part/pv L_0xa6ea30, 3, 1, 4; -L_0xa543c0 .part v0xa38650_0, 3, 1; -L_0xa6ef50 .part v0xa38850_0, 3, 1; -L_0xa6f800 .part/pv L_0xa6f590, 0, 1, 4; -L_0xa6f900 .part v0xa38650_0, 0, 1; -L_0xa6f9a0 .part v0xa38850_0, 0, 1; -S_0xa0f960 .scope module, "attempt2" "AndNand" 3 165, 3 48, S_0xa0d440; - .timescale -9 -12; -L_0xa6f040/d .functor NAND 1, L_0xa6f900, L_0xa6f9a0, C4<1>, C4<1>; -L_0xa6f040 .delay (10000,10000,10000) L_0xa6f040/d; -L_0xa6f140/d .functor NOT 1, L_0xa6f040, C4<0>, C4<0>, C4<0>; -L_0xa6f140 .delay (10000,10000,10000) L_0xa6f140/d; -v0xa0ff80_0 .net "A", 0 0, L_0xa6f900; 1 drivers -v0xa10040_0 .net "AandB", 0 0, L_0xa6f140; 1 drivers -v0xa100c0_0 .net "AnandB", 0 0, L_0xa6f040; 1 drivers -v0xa10170_0 .net "AndNandOut", 0 0, L_0xa6f590; 1 drivers -v0xa10250_0 .net "B", 0 0, L_0xa6f9a0; 1 drivers -v0xa102d0_0 .alias "Command", 2 0, v0xa373b0_0; -L_0xa6f760 .part v0xa388d0_0, 0, 1; -S_0xa0fa50 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0xa0f960; - .timescale -9 -12; -L_0xa6f270/d .functor NOT 1, L_0xa6f760, C4<0>, C4<0>, C4<0>; -L_0xa6f270 .delay (10000,10000,10000) L_0xa6f270/d; -L_0xa6f330/d .functor AND 1, L_0xa6f140, L_0xa6f270, C4<1>, C4<1>; -L_0xa6f330 .delay (20000,20000,20000) L_0xa6f330/d; -L_0xa6f440/d .functor AND 1, L_0xa6f040, L_0xa6f760, C4<1>, C4<1>; -L_0xa6f440 .delay (20000,20000,20000) L_0xa6f440/d; -L_0xa6f590/d .functor OR 1, L_0xa6f330, L_0xa6f440, C4<0>, C4<0>; -L_0xa6f590 .delay (20000,20000,20000) L_0xa6f590/d; -v0xa0fb40_0 .net "S", 0 0, L_0xa6f760; 1 drivers -v0xa0fbc0_0 .alias "in0", 0 0, v0xa10040_0; -v0xa0fc40_0 .alias "in1", 0 0, v0xa100c0_0; -v0xa0fce0_0 .net "nS", 0 0, L_0xa6f270; 1 drivers -v0xa0fd60_0 .net "out0", 0 0, L_0xa6f330; 1 drivers -v0xa0fe00_0 .net "out1", 0 0, L_0xa6f440; 1 drivers -v0xa0fee0_0 .alias "outfinal", 0 0, v0xa10170_0; -S_0xa0eda0 .scope generate, "andbits[1]" "andbits[1]" 3 169, 3 169, S_0xa0d440; - .timescale -9 -12; -P_0xa0ee98 .param/l "i" 3 169, +C4<01>; -S_0xa0ef10 .scope module, "attempt" "AndNand" 3 171, 3 48, S_0xa0eda0; - .timescale -9 -12; -L_0xa6cff0/d .functor NAND 1, L_0xa6d880, L_0xa6d920, C4<1>, C4<1>; -L_0xa6cff0 .delay (10000,10000,10000) L_0xa6cff0/d; -L_0xa6d100/d .functor NOT 1, L_0xa6cff0, C4<0>, C4<0>, C4<0>; -L_0xa6d100 .delay (10000,10000,10000) L_0xa6d100/d; -v0xa0f550_0 .net "A", 0 0, L_0xa6d880; 1 drivers -v0xa0f610_0 .net "AandB", 0 0, L_0xa6d100; 1 drivers -v0xa0f690_0 .net "AnandB", 0 0, L_0xa6cff0; 1 drivers -v0xa0f740_0 .net "AndNandOut", 0 0, L_0xa6d550; 1 drivers -v0xa0f820_0 .net "B", 0 0, L_0xa6d920; 1 drivers -v0xa0f8a0_0 .alias "Command", 2 0, v0xa373b0_0; -L_0xa6d720 .part v0xa388d0_0, 0, 1; -S_0xa0f000 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0xa0ef10; - .timescale -9 -12; -L_0xa6d230/d .functor NOT 1, L_0xa6d720, C4<0>, C4<0>, C4<0>; -L_0xa6d230 .delay (10000,10000,10000) L_0xa6d230/d; -L_0xa6d2f0/d .functor AND 1, L_0xa6d100, L_0xa6d230, C4<1>, C4<1>; -L_0xa6d2f0 .delay (20000,20000,20000) L_0xa6d2f0/d; -L_0xa6d400/d .functor AND 1, L_0xa6cff0, L_0xa6d720, C4<1>, C4<1>; -L_0xa6d400 .delay (20000,20000,20000) L_0xa6d400/d; -L_0xa6d550/d .functor OR 1, L_0xa6d2f0, L_0xa6d400, C4<0>, C4<0>; -L_0xa6d550 .delay (20000,20000,20000) L_0xa6d550/d; -v0xa0f0f0_0 .net "S", 0 0, L_0xa6d720; 1 drivers -v0xa0f170_0 .alias "in0", 0 0, v0xa0f610_0; -v0xa0f210_0 .alias "in1", 0 0, v0xa0f690_0; -v0xa0f2b0_0 .net "nS", 0 0, L_0xa6d230; 1 drivers -v0xa0f330_0 .net "out0", 0 0, L_0xa6d2f0; 1 drivers -v0xa0f3d0_0 .net "out1", 0 0, L_0xa6d400; 1 drivers -v0xa0f4b0_0 .alias "outfinal", 0 0, v0xa0f740_0; -S_0xa0e1e0 .scope generate, "andbits[2]" "andbits[2]" 3 169, 3 169, S_0xa0d440; - .timescale -9 -12; -P_0xa0e2d8 .param/l "i" 3 169, +C4<010>; -S_0xa0e350 .scope module, "attempt" "AndNand" 3 171, 3 48, S_0xa0e1e0; - .timescale -9 -12; -L_0xa6da10/d .functor NAND 1, L_0xa6e2d0, L_0xa6e370, C4<1>, C4<1>; -L_0xa6da10 .delay (10000,10000,10000) L_0xa6da10/d; -L_0xa6db70/d .functor NOT 1, L_0xa6da10, C4<0>, C4<0>, C4<0>; -L_0xa6db70 .delay (10000,10000,10000) L_0xa6db70/d; -v0xa0e990_0 .net "A", 0 0, L_0xa6e2d0; 1 drivers -v0xa0ea50_0 .net "AandB", 0 0, L_0xa6db70; 1 drivers -v0xa0ead0_0 .net "AnandB", 0 0, L_0xa6da10; 1 drivers -v0xa0eb80_0 .net "AndNandOut", 0 0, L_0xa6dfc0; 1 drivers -v0xa0ec60_0 .net "B", 0 0, L_0xa6e370; 1 drivers -v0xa0ece0_0 .alias "Command", 2 0, v0xa373b0_0; -L_0xa6e190 .part v0xa388d0_0, 0, 1; -S_0xa0e440 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0xa0e350; - .timescale -9 -12; -L_0xa6dca0/d .functor NOT 1, L_0xa6e190, C4<0>, C4<0>, C4<0>; -L_0xa6dca0 .delay (10000,10000,10000) L_0xa6dca0/d; -L_0xa6dd60/d .functor AND 1, L_0xa6db70, L_0xa6dca0, C4<1>, C4<1>; -L_0xa6dd60 .delay (20000,20000,20000) L_0xa6dd60/d; -L_0xa6de70/d .functor AND 1, L_0xa6da10, L_0xa6e190, C4<1>, C4<1>; -L_0xa6de70 .delay (20000,20000,20000) L_0xa6de70/d; -L_0xa6dfc0/d .functor OR 1, L_0xa6dd60, L_0xa6de70, C4<0>, C4<0>; -L_0xa6dfc0 .delay (20000,20000,20000) L_0xa6dfc0/d; -v0xa0e530_0 .net "S", 0 0, L_0xa6e190; 1 drivers -v0xa0e5b0_0 .alias "in0", 0 0, v0xa0ea50_0; -v0xa0e650_0 .alias "in1", 0 0, v0xa0ead0_0; -v0xa0e6f0_0 .net "nS", 0 0, L_0xa6dca0; 1 drivers -v0xa0e770_0 .net "out0", 0 0, L_0xa6dd60; 1 drivers -v0xa0e810_0 .net "out1", 0 0, L_0xa6de70; 1 drivers -v0xa0e8f0_0 .alias "outfinal", 0 0, v0xa0eb80_0; -S_0xa0d5b0 .scope generate, "andbits[3]" "andbits[3]" 3 169, 3 169, S_0xa0d440; - .timescale -9 -12; -P_0xa0d6a8 .param/l "i" 3 169, +C4<011>; -S_0xa0d740 .scope module, "attempt" "AndNand" 3 171, 3 48, S_0xa0d5b0; - .timescale -9 -12; -L_0xa6e4a0/d .functor NAND 1, L_0xa543c0, L_0xa6ef50, C4<1>, C4<1>; -L_0xa6e4a0 .delay (10000,10000,10000) L_0xa6e4a0/d; -L_0xa6e5e0/d .functor NOT 1, L_0xa6e4a0, C4<0>, C4<0>, C4<0>; -L_0xa6e5e0 .delay (10000,10000,10000) L_0xa6e5e0/d; -v0xa0ddd0_0 .net "A", 0 0, L_0xa543c0; 1 drivers -v0xa0de90_0 .net "AandB", 0 0, L_0xa6e5e0; 1 drivers -v0xa0df10_0 .net "AnandB", 0 0, L_0xa6e4a0; 1 drivers -v0xa0dfc0_0 .net "AndNandOut", 0 0, L_0xa6ea30; 1 drivers -v0xa0e0a0_0 .net "B", 0 0, L_0xa6ef50; 1 drivers -v0xa0e120_0 .alias "Command", 2 0, v0xa373b0_0; -L_0xa6ec00 .part v0xa388d0_0, 0, 1; -S_0xa0d830 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0xa0d740; - .timescale -9 -12; -L_0xa6e710/d .functor NOT 1, L_0xa6ec00, C4<0>, C4<0>, C4<0>; -L_0xa6e710 .delay (10000,10000,10000) L_0xa6e710/d; -L_0xa6e7d0/d .functor AND 1, L_0xa6e5e0, L_0xa6e710, C4<1>, C4<1>; -L_0xa6e7d0 .delay (20000,20000,20000) L_0xa6e7d0/d; -L_0xa6e8e0/d .functor AND 1, L_0xa6e4a0, L_0xa6ec00, C4<1>, C4<1>; -L_0xa6e8e0 .delay (20000,20000,20000) L_0xa6e8e0/d; -L_0xa6ea30/d .functor OR 1, L_0xa6e7d0, L_0xa6e8e0, C4<0>, C4<0>; -L_0xa6ea30 .delay (20000,20000,20000) L_0xa6ea30/d; -v0xa0d920_0 .net "S", 0 0, L_0xa6ec00; 1 drivers -v0xa0d9c0_0 .alias "in0", 0 0, v0xa0de90_0; -v0xa0da60_0 .alias "in1", 0 0, v0xa0df10_0; -v0xa0db00_0 .net "nS", 0 0, L_0xa6e710; 1 drivers -v0xa0dbb0_0 .net "out0", 0 0, L_0xa6e7d0; 1 drivers -v0xa0dc50_0 .net "out1", 0 0, L_0xa6e8e0; 1 drivers -v0xa0dd30_0 .alias "outfinal", 0 0, v0xa0dfc0_0; -S_0xa08220 .scope module, "trial2" "OrNorXor32" 3 396, 3 177, S_0x9cd4a0; - .timescale -9 -12; -P_0xa07378 .param/l "size" 3 184, +C4<0100>; -v0xa0d1b0_0 .alias "A", 3 0, v0xa37070_0; -v0xa0d230_0 .alias "B", 3 0, v0xa37220_0; -v0xa0d2b0_0 .alias "Command", 2 0, v0xa373b0_0; -v0xa0d3c0_0 .alias "OrNorXorOut", 3 0, v0xa389d0_0; -L_0xa70bc0 .part/pv L_0xa70950, 1, 1, 4; -L_0xa70c60 .part v0xa38650_0, 1, 1; -L_0xa70d00 .part v0xa38850_0, 1, 1; -L_0xa71ec0 .part/pv L_0xa71c50, 2, 1, 4; -L_0xa71f60 .part v0xa38650_0, 2, 1; -L_0xa72000 .part v0xa38850_0, 2, 1; -L_0xa731c0 .part/pv L_0xa72f50, 3, 1, 4; -L_0xa73260 .part v0xa38650_0, 3, 1; -L_0xa73300 .part v0xa38850_0, 3, 1; -L_0xa744b0 .part/pv L_0xa74240, 0, 1, 4; -L_0xa745b0 .part v0xa38650_0, 0, 1; -L_0xa74650 .part v0xa38850_0, 0, 1; -S_0xa0bfa0 .scope module, "attempt2" "OrNorXor" 3 192, 3 64, S_0xa08220; - .timescale -9 -12; -L_0xa733a0/d .functor NOR 1, L_0xa745b0, L_0xa74650, C4<0>, C4<0>; -L_0xa733a0 .delay (10000,10000,10000) L_0xa733a0/d; -L_0xa734a0/d .functor NOT 1, L_0xa733a0, C4<0>, C4<0>, C4<0>; -L_0xa734a0 .delay (10000,10000,10000) L_0xa734a0/d; -L_0xa735d0/d .functor NAND 1, L_0xa745b0, L_0xa74650, C4<1>, C4<1>; -L_0xa735d0 .delay (10000,10000,10000) L_0xa735d0/d; -L_0xa73730/d .functor NAND 1, L_0xa735d0, L_0xa734a0, C4<1>, C4<1>; -L_0xa73730 .delay (10000,10000,10000) L_0xa73730/d; -L_0xa73840/d .functor NOT 1, L_0xa73730, C4<0>, C4<0>, C4<0>; -L_0xa73840 .delay (10000,10000,10000) L_0xa73840/d; -v0xa0caf0_0 .net "A", 0 0, L_0xa745b0; 1 drivers -v0xa0cb90_0 .net "AnandB", 0 0, L_0xa735d0; 1 drivers -v0xa0cc30_0 .net "AnorB", 0 0, L_0xa733a0; 1 drivers -v0xa0ccb0_0 .net "AorB", 0 0, L_0xa734a0; 1 drivers -v0xa0cd90_0 .net "AxorB", 0 0, L_0xa73840; 1 drivers -v0xa0ce40_0 .net "B", 0 0, L_0xa74650; 1 drivers -v0xa0cf00_0 .alias "Command", 2 0, v0xa373b0_0; -v0xa0cf80_0 .net "OrNorXorOut", 0 0, L_0xa74240; 1 drivers -v0xa0d000_0 .net "XorNor", 0 0, L_0xa73cc0; 1 drivers -v0xa0d0d0_0 .net "nXor", 0 0, L_0xa73730; 1 drivers -L_0xa73e40 .part v0xa388d0_0, 2, 1; -L_0xa74410 .part v0xa388d0_0, 0, 1; -S_0xa0c580 .scope module, "mux0" "TwoInMux" 3 83, 3 8, S_0xa0bfa0; - .timescale -9 -12; -L_0xa739a0/d .functor NOT 1, L_0xa73e40, C4<0>, C4<0>, C4<0>; -L_0xa739a0 .delay (10000,10000,10000) L_0xa739a0/d; -L_0xa73a60/d .functor AND 1, L_0xa73840, L_0xa739a0, C4<1>, C4<1>; -L_0xa73a60 .delay (20000,20000,20000) L_0xa73a60/d; -L_0xa73b70/d .functor AND 1, L_0xa733a0, L_0xa73e40, C4<1>, C4<1>; -L_0xa73b70 .delay (20000,20000,20000) L_0xa73b70/d; -L_0xa73cc0/d .functor OR 1, L_0xa73a60, L_0xa73b70, C4<0>, C4<0>; -L_0xa73cc0 .delay (20000,20000,20000) L_0xa73cc0/d; -v0xa0c670_0 .net "S", 0 0, L_0xa73e40; 1 drivers -v0xa0c730_0 .alias "in0", 0 0, v0xa0cd90_0; -v0xa0c7d0_0 .alias "in1", 0 0, v0xa0cc30_0; -v0xa0c870_0 .net "nS", 0 0, L_0xa739a0; 1 drivers -v0xa0c8f0_0 .net "out0", 0 0, L_0xa73a60; 1 drivers -v0xa0c990_0 .net "out1", 0 0, L_0xa73b70; 1 drivers -v0xa0ca70_0 .alias "outfinal", 0 0, v0xa0d000_0; -S_0xa0c090 .scope module, "mux1" "TwoInMux" 3 84, 3 8, S_0xa0bfa0; - .timescale -9 -12; -L_0xa73ee0/d .functor NOT 1, L_0xa74410, C4<0>, C4<0>, C4<0>; -L_0xa73ee0 .delay (10000,10000,10000) L_0xa73ee0/d; -L_0xa73fa0/d .functor AND 1, L_0xa73cc0, L_0xa73ee0, C4<1>, C4<1>; -L_0xa73fa0 .delay (20000,20000,20000) L_0xa73fa0/d; -L_0xa740f0/d .functor AND 1, L_0xa734a0, L_0xa74410, C4<1>, C4<1>; -L_0xa740f0 .delay (20000,20000,20000) L_0xa740f0/d; -L_0xa74240/d .functor OR 1, L_0xa73fa0, L_0xa740f0, C4<0>, C4<0>; -L_0xa74240 .delay (20000,20000,20000) L_0xa74240/d; -v0xa0c180_0 .net "S", 0 0, L_0xa74410; 1 drivers -v0xa0c200_0 .alias "in0", 0 0, v0xa0d000_0; -v0xa0c280_0 .alias "in1", 0 0, v0xa0ccb0_0; -v0xa0c320_0 .net "nS", 0 0, L_0xa73ee0; 1 drivers -v0xa0c3a0_0 .net "out0", 0 0, L_0xa73fa0; 1 drivers -v0xa0c440_0 .net "out1", 0 0, L_0xa740f0; 1 drivers -v0xa0c4e0_0 .alias "outfinal", 0 0, v0xa0cf80_0; -S_0xa0aba0 .scope generate, "orbits[1]" "orbits[1]" 3 196, 3 196, S_0xa08220; - .timescale -9 -12; -P_0xa0a888 .param/l "i" 3 196, +C4<01>; -S_0xa0acd0 .scope module, "attempt" "OrNorXor" 3 198, 3 64, S_0xa0aba0; - .timescale -9 -12; -L_0xa6f8a0/d .functor NOR 1, L_0xa70c60, L_0xa70d00, C4<0>, C4<0>; -L_0xa6f8a0 .delay (10000,10000,10000) L_0xa6f8a0/d; -L_0xa6fbb0/d .functor NOT 1, L_0xa6f8a0, C4<0>, C4<0>, C4<0>; -L_0xa6fbb0 .delay (10000,10000,10000) L_0xa6fbb0/d; -L_0xa6fce0/d .functor NAND 1, L_0xa70c60, L_0xa70d00, C4<1>, C4<1>; -L_0xa6fce0 .delay (10000,10000,10000) L_0xa6fce0/d; -L_0xa6fe40/d .functor NAND 1, L_0xa6fce0, L_0xa6fbb0, C4<1>, C4<1>; -L_0xa6fe40 .delay (10000,10000,10000) L_0xa6fe40/d; -L_0xa6ff50/d .functor NOT 1, L_0xa6fe40, C4<0>, C4<0>, C4<0>; -L_0xa6ff50 .delay (10000,10000,10000) L_0xa6ff50/d; -v0xa0b860_0 .net "A", 0 0, L_0xa70c60; 1 drivers -v0xa0b900_0 .net "AnandB", 0 0, L_0xa6fce0; 1 drivers -v0xa0b9a0_0 .net "AnorB", 0 0, L_0xa6f8a0; 1 drivers -v0xa0ba50_0 .net "AorB", 0 0, L_0xa6fbb0; 1 drivers -v0xa0bb30_0 .net "AxorB", 0 0, L_0xa6ff50; 1 drivers -v0xa0bbe0_0 .net "B", 0 0, L_0xa70d00; 1 drivers -v0xa0bca0_0 .alias "Command", 2 0, v0xa373b0_0; -v0xa0bd20_0 .net "OrNorXorOut", 0 0, L_0xa70950; 1 drivers -v0xa0bdf0_0 .net "XorNor", 0 0, L_0xa703d0; 1 drivers -v0xa0bec0_0 .net "nXor", 0 0, L_0xa6fe40; 1 drivers -L_0xa70550 .part v0xa388d0_0, 2, 1; -L_0xa70b20 .part v0xa388d0_0, 0, 1; -S_0xa0b2f0 .scope module, "mux0" "TwoInMux" 3 83, 3 8, S_0xa0acd0; - .timescale -9 -12; -L_0xa700b0/d .functor NOT 1, L_0xa70550, C4<0>, C4<0>, C4<0>; -L_0xa700b0 .delay (10000,10000,10000) L_0xa700b0/d; -L_0xa70170/d .functor AND 1, L_0xa6ff50, L_0xa700b0, C4<1>, C4<1>; -L_0xa70170 .delay (20000,20000,20000) L_0xa70170/d; -L_0xa70280/d .functor AND 1, L_0xa6f8a0, L_0xa70550, C4<1>, C4<1>; -L_0xa70280 .delay (20000,20000,20000) L_0xa70280/d; -L_0xa703d0/d .functor OR 1, L_0xa70170, L_0xa70280, C4<0>, C4<0>; -L_0xa703d0 .delay (20000,20000,20000) L_0xa703d0/d; -v0xa0b3e0_0 .net "S", 0 0, L_0xa70550; 1 drivers -v0xa0b4a0_0 .alias "in0", 0 0, v0xa0bb30_0; -v0xa0b540_0 .alias "in1", 0 0, v0xa0b9a0_0; -v0xa0b5e0_0 .net "nS", 0 0, L_0xa700b0; 1 drivers -v0xa0b660_0 .net "out0", 0 0, L_0xa70170; 1 drivers -v0xa0b700_0 .net "out1", 0 0, L_0xa70280; 1 drivers -v0xa0b7e0_0 .alias "outfinal", 0 0, v0xa0bdf0_0; -S_0xa0adc0 .scope module, "mux1" "TwoInMux" 3 84, 3 8, S_0xa0acd0; - .timescale -9 -12; -L_0xa705f0/d .functor NOT 1, L_0xa70b20, C4<0>, C4<0>, C4<0>; -L_0xa705f0 .delay (10000,10000,10000) L_0xa705f0/d; -L_0xa706b0/d .functor AND 1, L_0xa703d0, L_0xa705f0, C4<1>, C4<1>; -L_0xa706b0 .delay (20000,20000,20000) L_0xa706b0/d; -L_0xa70800/d .functor AND 1, L_0xa6fbb0, L_0xa70b20, C4<1>, C4<1>; -L_0xa70800 .delay (20000,20000,20000) L_0xa70800/d; -L_0xa70950/d .functor OR 1, L_0xa706b0, L_0xa70800, C4<0>, C4<0>; -L_0xa70950 .delay (20000,20000,20000) L_0xa70950/d; -v0xa0aeb0_0 .net "S", 0 0, L_0xa70b20; 1 drivers -v0xa0af30_0 .alias "in0", 0 0, v0xa0bdf0_0; -v0xa0afb0_0 .alias "in1", 0 0, v0xa0ba50_0; -v0xa0b050_0 .net "nS", 0 0, L_0xa705f0; 1 drivers -v0xa0b0d0_0 .net "out0", 0 0, L_0xa706b0; 1 drivers -v0xa0b170_0 .net "out1", 0 0, L_0xa70800; 1 drivers -v0xa0b250_0 .alias "outfinal", 0 0, v0xa0bd20_0; -S_0xa09780 .scope generate, "orbits[2]" "orbits[2]" 3 196, 3 196, S_0xa08220; - .timescale -9 -12; -P_0xa094f8 .param/l "i" 3 196, +C4<010>; -S_0xa098b0 .scope module, "attempt" "OrNorXor" 3 198, 3 64, S_0xa09780; - .timescale -9 -12; -L_0xa70da0/d .functor NOR 1, L_0xa71f60, L_0xa72000, C4<0>, C4<0>; -L_0xa70da0 .delay (10000,10000,10000) L_0xa70da0/d; -L_0xa70eb0/d .functor NOT 1, L_0xa70da0, C4<0>, C4<0>, C4<0>; -L_0xa70eb0 .delay (10000,10000,10000) L_0xa70eb0/d; -L_0xa70fe0/d .functor NAND 1, L_0xa71f60, L_0xa72000, C4<1>, C4<1>; -L_0xa70fe0 .delay (10000,10000,10000) L_0xa70fe0/d; -L_0xa71140/d .functor NAND 1, L_0xa70fe0, L_0xa70eb0, C4<1>, C4<1>; -L_0xa71140 .delay (10000,10000,10000) L_0xa71140/d; -L_0xa71250/d .functor NOT 1, L_0xa71140, C4<0>, C4<0>, C4<0>; -L_0xa71250 .delay (10000,10000,10000) L_0xa71250/d; -v0xa0a480_0 .net "A", 0 0, L_0xa71f60; 1 drivers -v0xa0a520_0 .net "AnandB", 0 0, L_0xa70fe0; 1 drivers -v0xa0a5c0_0 .net "AnorB", 0 0, L_0xa70da0; 1 drivers -v0xa0a670_0 .net "AorB", 0 0, L_0xa70eb0; 1 drivers -v0xa0a750_0 .net "AxorB", 0 0, L_0xa71250; 1 drivers -v0xa0a800_0 .net "B", 0 0, L_0xa72000; 1 drivers -v0xa0a8c0_0 .alias "Command", 2 0, v0xa373b0_0; -v0xa0a940_0 .net "OrNorXorOut", 0 0, L_0xa71c50; 1 drivers -v0xa0a9f0_0 .net "XorNor", 0 0, L_0xa716d0; 1 drivers -v0xa0aac0_0 .net "nXor", 0 0, L_0xa71140; 1 drivers -L_0xa71850 .part v0xa388d0_0, 2, 1; -L_0xa71e20 .part v0xa388d0_0, 0, 1; -S_0xa09f10 .scope module, "mux0" "TwoInMux" 3 83, 3 8, S_0xa098b0; - .timescale -9 -12; -L_0xa713b0/d .functor NOT 1, L_0xa71850, C4<0>, C4<0>, C4<0>; -L_0xa713b0 .delay (10000,10000,10000) L_0xa713b0/d; -L_0xa71470/d .functor AND 1, L_0xa71250, L_0xa713b0, C4<1>, C4<1>; -L_0xa71470 .delay (20000,20000,20000) L_0xa71470/d; -L_0xa71580/d .functor AND 1, L_0xa70da0, L_0xa71850, C4<1>, C4<1>; -L_0xa71580 .delay (20000,20000,20000) L_0xa71580/d; -L_0xa716d0/d .functor OR 1, L_0xa71470, L_0xa71580, C4<0>, C4<0>; -L_0xa716d0 .delay (20000,20000,20000) L_0xa716d0/d; -v0xa0a000_0 .net "S", 0 0, L_0xa71850; 1 drivers -v0xa0a0c0_0 .alias "in0", 0 0, v0xa0a750_0; -v0xa0a160_0 .alias "in1", 0 0, v0xa0a5c0_0; -v0xa0a200_0 .net "nS", 0 0, L_0xa713b0; 1 drivers -v0xa0a280_0 .net "out0", 0 0, L_0xa71470; 1 drivers -v0xa0a320_0 .net "out1", 0 0, L_0xa71580; 1 drivers -v0xa0a400_0 .alias "outfinal", 0 0, v0xa0a9f0_0; -S_0xa099a0 .scope module, "mux1" "TwoInMux" 3 84, 3 8, S_0xa098b0; - .timescale -9 -12; -L_0xa718f0/d .functor NOT 1, L_0xa71e20, C4<0>, C4<0>, C4<0>; -L_0xa718f0 .delay (10000,10000,10000) L_0xa718f0/d; -L_0xa719b0/d .functor AND 1, L_0xa716d0, L_0xa718f0, C4<1>, C4<1>; -L_0xa719b0 .delay (20000,20000,20000) L_0xa719b0/d; -L_0xa71b00/d .functor AND 1, L_0xa70eb0, L_0xa71e20, C4<1>, C4<1>; -L_0xa71b00 .delay (20000,20000,20000) L_0xa71b00/d; -L_0xa71c50/d .functor OR 1, L_0xa719b0, L_0xa71b00, C4<0>, C4<0>; -L_0xa71c50 .delay (20000,20000,20000) L_0xa71c50/d; -v0xa09a90_0 .net "S", 0 0, L_0xa71e20; 1 drivers -v0xa09b30_0 .alias "in0", 0 0, v0xa0a9f0_0; -v0xa09bd0_0 .alias "in1", 0 0, v0xa0a670_0; -v0xa09c70_0 .net "nS", 0 0, L_0xa718f0; 1 drivers -v0xa09cf0_0 .net "out0", 0 0, L_0xa719b0; 1 drivers -v0xa09d90_0 .net "out1", 0 0, L_0xa71b00; 1 drivers -v0xa09e70_0 .alias "outfinal", 0 0, v0xa0a940_0; -S_0xa08390 .scope generate, "orbits[3]" "orbits[3]" 3 196, 3 196, S_0xa08220; - .timescale -9 -12; -P_0xa08488 .param/l "i" 3 196, +C4<011>; -S_0xa08520 .scope module, "attempt" "OrNorXor" 3 198, 3 64, S_0xa08390; - .timescale -9 -12; -L_0xa720e0/d .functor NOR 1, L_0xa73260, L_0xa73300, C4<0>, C4<0>; -L_0xa720e0 .delay (10000,10000,10000) L_0xa720e0/d; -L_0xa721d0/d .functor NOT 1, L_0xa720e0, C4<0>, C4<0>, C4<0>; -L_0xa721d0 .delay (10000,10000,10000) L_0xa721d0/d; -L_0xa722e0/d .functor NAND 1, L_0xa73260, L_0xa73300, C4<1>, C4<1>; -L_0xa722e0 .delay (10000,10000,10000) L_0xa722e0/d; -L_0xa72440/d .functor NAND 1, L_0xa722e0, L_0xa721d0, C4<1>, C4<1>; -L_0xa72440 .delay (10000,10000,10000) L_0xa72440/d; -L_0xa72550/d .functor NOT 1, L_0xa72440, C4<0>, C4<0>, C4<0>; -L_0xa72550 .delay (10000,10000,10000) L_0xa72550/d; -v0xa090f0_0 .net "A", 0 0, L_0xa73260; 1 drivers -v0xa09190_0 .net "AnandB", 0 0, L_0xa722e0; 1 drivers -v0xa09230_0 .net "AnorB", 0 0, L_0xa720e0; 1 drivers -v0xa092e0_0 .net "AorB", 0 0, L_0xa721d0; 1 drivers -v0xa093c0_0 .net "AxorB", 0 0, L_0xa72550; 1 drivers -v0xa09470_0 .net "B", 0 0, L_0xa73300; 1 drivers -v0xa09530_0 .alias "Command", 2 0, v0xa373b0_0; -v0xa095b0_0 .net "OrNorXorOut", 0 0, L_0xa72f50; 1 drivers -v0xa09630_0 .net "XorNor", 0 0, L_0xa729d0; 1 drivers -v0xa09700_0 .net "nXor", 0 0, L_0xa72440; 1 drivers -L_0xa72b50 .part v0xa388d0_0, 2, 1; -L_0xa73120 .part v0xa388d0_0, 0, 1; -S_0xa08b80 .scope module, "mux0" "TwoInMux" 3 83, 3 8, S_0xa08520; - .timescale -9 -12; -L_0xa726b0/d .functor NOT 1, L_0xa72b50, C4<0>, C4<0>, C4<0>; -L_0xa726b0 .delay (10000,10000,10000) L_0xa726b0/d; -L_0xa72770/d .functor AND 1, L_0xa72550, L_0xa726b0, C4<1>, C4<1>; -L_0xa72770 .delay (20000,20000,20000) L_0xa72770/d; -L_0xa72880/d .functor AND 1, L_0xa720e0, L_0xa72b50, C4<1>, C4<1>; -L_0xa72880 .delay (20000,20000,20000) L_0xa72880/d; -L_0xa729d0/d .functor OR 1, L_0xa72770, L_0xa72880, C4<0>, C4<0>; -L_0xa729d0 .delay (20000,20000,20000) L_0xa729d0/d; -v0xa08c70_0 .net "S", 0 0, L_0xa72b50; 1 drivers -v0xa08d30_0 .alias "in0", 0 0, v0xa093c0_0; -v0xa08dd0_0 .alias "in1", 0 0, v0xa09230_0; -v0xa08e70_0 .net "nS", 0 0, L_0xa726b0; 1 drivers -v0xa08ef0_0 .net "out0", 0 0, L_0xa72770; 1 drivers -v0xa08f90_0 .net "out1", 0 0, L_0xa72880; 1 drivers -v0xa09070_0 .alias "outfinal", 0 0, v0xa09630_0; -S_0xa08610 .scope module, "mux1" "TwoInMux" 3 84, 3 8, S_0xa08520; - .timescale -9 -12; -L_0xa72bf0/d .functor NOT 1, L_0xa73120, C4<0>, C4<0>, C4<0>; -L_0xa72bf0 .delay (10000,10000,10000) L_0xa72bf0/d; -L_0xa72cb0/d .functor AND 1, L_0xa729d0, L_0xa72bf0, C4<1>, C4<1>; -L_0xa72cb0 .delay (20000,20000,20000) L_0xa72cb0/d; -L_0xa72e00/d .functor AND 1, L_0xa721d0, L_0xa73120, C4<1>, C4<1>; -L_0xa72e00 .delay (20000,20000,20000) L_0xa72e00/d; -L_0xa72f50/d .functor OR 1, L_0xa72cb0, L_0xa72e00, C4<0>, C4<0>; -L_0xa72f50 .delay (20000,20000,20000) L_0xa72f50/d; -v0xa08700_0 .net "S", 0 0, L_0xa73120; 1 drivers -v0xa087a0_0 .alias "in0", 0 0, v0xa09630_0; -v0xa08840_0 .alias "in1", 0 0, v0xa092e0_0; -v0xa088e0_0 .net "nS", 0 0, L_0xa72bf0; 1 drivers -v0xa08960_0 .net "out0", 0 0, L_0xa72cb0; 1 drivers -v0xa08a00_0 .net "out1", 0 0, L_0xa72e00; 1 drivers -v0xa08ae0_0 .alias "outfinal", 0 0, v0xa095b0_0; -S_0xa078a0 .scope module, "ZeroMux0case" "FourInMux" 3 398, 3 24, S_0x9cd4a0; - .timescale -9 -12; -L_0xa74550/d .functor NOT 1, L_0xa5a4e0, C4<0>, C4<0>, C4<0>; -L_0xa74550 .delay (10000,10000,10000) L_0xa74550/d; -L_0xa747a0/d .functor NOT 1, L_0xa5a610, C4<0>, C4<0>, C4<0>; -L_0xa747a0 .delay (10000,10000,10000) L_0xa747a0/d; -L_0xa74860/d .functor NAND 1, L_0xa74550, L_0xa747a0, L_0xa74e90, C4<1>; -L_0xa74860 .delay (10000,10000,10000) L_0xa74860/d; -L_0xa74950/d .functor NAND 1, L_0xa5a4e0, L_0xa747a0, L_0xa74f30, C4<1>; -L_0xa74950 .delay (10000,10000,10000) L_0xa74950/d; -L_0xa74a40/d .functor NAND 1, L_0xa74550, L_0xa5a610, L_0xa74fd0, C4<1>; -L_0xa74a40 .delay (10000,10000,10000) L_0xa74a40/d; -L_0xa74b30/d .functor NAND 1, L_0xa5a4e0, L_0xa5a610, L_0xa753b0, C4<1>; -L_0xa74b30 .delay (10000,10000,10000) L_0xa74b30/d; -L_0xa74c10/d .functor NAND 1, L_0xa74860, L_0xa74950, L_0xa74a40, L_0xa74b30; -L_0xa74c10 .delay (10000,10000,10000) L_0xa74c10/d; -v0xa07990_0 .net "S0", 0 0, L_0xa5a4e0; 1 drivers -v0xa07a50_0 .net "S1", 0 0, L_0xa5a610; 1 drivers -v0xa07af0_0 .net "in0", 0 0, L_0xa74e90; 1 drivers -v0xa07b90_0 .net "in1", 0 0, L_0xa74f30; 1 drivers -v0xa07c10_0 .net "in2", 0 0, L_0xa74fd0; 1 drivers -v0xa07cb0_0 .net "in3", 0 0, L_0xa753b0; 1 drivers -v0xa07d50_0 .net "nS0", 0 0, L_0xa74550; 1 drivers -v0xa07df0_0 .net "nS1", 0 0, L_0xa747a0; 1 drivers -v0xa07e90_0 .net "out", 0 0, L_0xa74c10; 1 drivers -v0xa07f30_0 .net "out0", 0 0, L_0xa74860; 1 drivers -v0xa07fd0_0 .net "out1", 0 0, L_0xa74950; 1 drivers -v0xa08070_0 .net "out2", 0 0, L_0xa74a40; 1 drivers -v0xa08180_0 .net "out3", 0 0, L_0xa74b30; 1 drivers -S_0xa06ee0 .scope module, "OneMux0case" "FourInMux" 3 399, 3 24, S_0x9cd4a0; - .timescale -9 -12; -L_0xa75130/d .functor NOT 1, L_0xa75cc0, C4<0>, C4<0>, C4<0>; -L_0xa75130 .delay (10000,10000,10000) L_0xa75130/d; -L_0xa75220/d .functor NOT 1, L_0xa754a0, C4<0>, C4<0>, C4<0>; -L_0xa75220 .delay (10000,10000,10000) L_0xa75220/d; -L_0xa752c0/d .functor NAND 1, L_0xa75130, L_0xa75220, L_0xa755d0, C4<1>; -L_0xa752c0 .delay (10000,10000,10000) L_0xa752c0/d; -L_0xa75780/d .functor NAND 1, L_0xa75cc0, L_0xa75220, L_0xa76050, C4<1>; -L_0xa75780 .delay (10000,10000,10000) L_0xa75780/d; -L_0xa75870/d .functor NAND 1, L_0xa75130, L_0xa754a0, L_0xa760f0, C4<1>; -L_0xa75870 .delay (10000,10000,10000) L_0xa75870/d; -L_0xa75960/d .functor NAND 1, L_0xa75cc0, L_0xa754a0, L_0xa75df0, C4<1>; -L_0xa75960 .delay (10000,10000,10000) L_0xa75960/d; -L_0xa75a40/d .functor NAND 1, L_0xa752c0, L_0xa75780, L_0xa75870, L_0xa75960; -L_0xa75a40 .delay (10000,10000,10000) L_0xa75a40/d; -v0xa06fd0_0 .net "S0", 0 0, L_0xa75cc0; 1 drivers -v0xa07090_0 .net "S1", 0 0, L_0xa754a0; 1 drivers -v0xa07130_0 .net "in0", 0 0, L_0xa755d0; 1 drivers -v0xa071d0_0 .net "in1", 0 0, L_0xa76050; 1 drivers -v0xa07250_0 .net "in2", 0 0, L_0xa760f0; 1 drivers -v0xa072f0_0 .net "in3", 0 0, L_0xa75df0; 1 drivers -v0xa073d0_0 .net "nS0", 0 0, L_0xa75130; 1 drivers -v0xa07470_0 .net "nS1", 0 0, L_0xa75220; 1 drivers -v0xa07510_0 .net "out", 0 0, L_0xa75a40; 1 drivers -v0xa075b0_0 .net "out0", 0 0, L_0xa752c0; 1 drivers -v0xa07650_0 .net "out1", 0 0, L_0xa75780; 1 drivers -v0xa076f0_0 .net "out2", 0 0, L_0xa75870; 1 drivers -v0xa07800_0 .net "out3", 0 0, L_0xa75960; 1 drivers -S_0xa06990 .scope module, "TwoMux0case" "TwoInMux" 3 400, 3 8, S_0x9cd4a0; - .timescale -9 -12; -L_0xa75ee0/d .functor NOT 1, L_0xa76190, C4<0>, C4<0>, C4<0>; -L_0xa75ee0 .delay (10000,10000,10000) L_0xa75ee0/d; -L_0xa75fd0/d .functor AND 1, L_0xa76230, L_0xa75ee0, C4<1>, C4<1>; -L_0xa75fd0 .delay (20000,20000,20000) L_0xa75fd0/d; -L_0xa76490/d .functor AND 1, L_0xa76320, L_0xa76190, C4<1>, C4<1>; -L_0xa76490 .delay (20000,20000,20000) L_0xa76490/d; -L_0xa76580/d .functor OR 1, L_0xa75fd0, L_0xa76490, C4<0>, C4<0>; -L_0xa76580 .delay (20000,20000,20000) L_0xa76580/d; -v0xa06a80_0 .net "S", 0 0, L_0xa76190; 1 drivers -v0xa06b40_0 .net "in0", 0 0, L_0xa76230; 1 drivers -v0xa06be0_0 .net "in1", 0 0, L_0xa76320; 1 drivers -v0xa06c80_0 .net "nS", 0 0, L_0xa75ee0; 1 drivers -v0xa06d00_0 .net "out0", 0 0, L_0xa75fd0; 1 drivers -v0xa06da0_0 .net "out1", 0 0, L_0xa76490; 1 drivers -v0xa06e40_0 .net "outfinal", 0 0, L_0xa76580; 1 drivers -S_0xa04e10 .scope generate, "muxbits[1]" "muxbits[1]" 3 405, 3 405, S_0x9cd4a0; - .timescale -9 -12; -P_0xa03e08 .param/l "i" 3 405, +C4<01>; -L_0xa54fc0/d .functor OR 1, L_0xa550c0, L_0xa54e80, C4<0>, C4<0>; -L_0xa54fc0 .delay (20000,20000,20000) L_0xa54fc0/d; -v0xa06830_0 .net *"_s15", 0 0, L_0xa550c0; 1 drivers -v0xa068f0_0 .net *"_s16", 0 0, L_0xa54e80; 1 drivers -S_0xa05eb0 .scope module, "ZeroMux" "FourInMux" 3 407, 3 24, S_0xa04e10; - .timescale -9 -12; -L_0xa527d0/d .functor NOT 1, L_0xa53110, C4<0>, C4<0>, C4<0>; -L_0xa527d0 .delay (10000,10000,10000) L_0xa527d0/d; -L_0xa52a20/d .functor NOT 1, L_0xa53240, C4<0>, C4<0>, C4<0>; -L_0xa52a20 .delay (10000,10000,10000) L_0xa52a20/d; -L_0xa52ae0/d .functor NAND 1, L_0xa527d0, L_0xa52a20, L_0xa53370, C4<1>; -L_0xa52ae0 .delay (10000,10000,10000) L_0xa52ae0/d; -L_0xa52bd0/d .functor NAND 1, L_0xa53110, L_0xa52a20, L_0xa53410, C4<1>; -L_0xa52bd0 .delay (10000,10000,10000) L_0xa52bd0/d; -L_0xa52cc0/d .functor NAND 1, L_0xa527d0, L_0xa53240, L_0xa534b0, C4<1>; -L_0xa52cc0 .delay (10000,10000,10000) L_0xa52cc0/d; -L_0xa52db0/d .functor NAND 1, L_0xa53110, L_0xa53240, L_0xa536b0, C4<1>; -L_0xa52db0 .delay (10000,10000,10000) L_0xa52db0/d; -L_0xa52e90/d .functor NAND 1, L_0xa52ae0, L_0xa52bd0, L_0xa52cc0, L_0xa52db0; -L_0xa52e90 .delay (10000,10000,10000) L_0xa52e90/d; -v0xa05fa0_0 .net "S0", 0 0, L_0xa53110; 1 drivers -v0xa06060_0 .net "S1", 0 0, L_0xa53240; 1 drivers -v0xa06100_0 .net "in0", 0 0, L_0xa53370; 1 drivers -v0xa061a0_0 .net "in1", 0 0, L_0xa53410; 1 drivers -v0xa06220_0 .net "in2", 0 0, L_0xa534b0; 1 drivers -v0xa062c0_0 .net "in3", 0 0, L_0xa536b0; 1 drivers -v0xa06360_0 .net "nS0", 0 0, L_0xa527d0; 1 drivers -v0xa06400_0 .net "nS1", 0 0, L_0xa52a20; 1 drivers -v0xa064a0_0 .net "out", 0 0, L_0xa52e90; 1 drivers -v0xa06540_0 .net "out0", 0 0, L_0xa52ae0; 1 drivers -v0xa065e0_0 .net "out1", 0 0, L_0xa52bd0; 1 drivers -v0xa06680_0 .net "out2", 0 0, L_0xa52cc0; 1 drivers -v0xa06790_0 .net "out3", 0 0, L_0xa52db0; 1 drivers -S_0xa054f0 .scope module, "OneMux" "FourInMux" 3 408, 3 24, S_0xa04e10; - .timescale -9 -12; -L_0xa430c0/d .functor NOT 1, L_0xa54060, C4<0>, C4<0>, C4<0>; -L_0xa430c0 .delay (10000,10000,10000) L_0xa430c0/d; -L_0xa538f0/d .functor NOT 1, L_0xa54190, C4<0>, C4<0>, C4<0>; -L_0xa538f0 .delay (10000,10000,10000) L_0xa538f0/d; -L_0xa53990/d .functor NAND 1, L_0xa430c0, L_0xa538f0, L_0xa54320, C4<1>; -L_0xa53990 .delay (10000,10000,10000) L_0xa53990/d; -L_0xa53ad0/d .functor NAND 1, L_0xa54060, L_0xa538f0, L_0xa544d0, C4<1>; -L_0xa53ad0 .delay (10000,10000,10000) L_0xa53ad0/d; -L_0xa53bc0/d .functor NAND 1, L_0xa430c0, L_0xa54190, L_0xa54570, C4<1>; -L_0xa53bc0 .delay (10000,10000,10000) L_0xa53bc0/d; -L_0xa53cb0/d .functor NAND 1, L_0xa54060, L_0xa54190, L_0xa54610, C4<1>; -L_0xa53cb0 .delay (10000,10000,10000) L_0xa53cb0/d; -L_0xa53d90/d .functor NAND 1, L_0xa53990, L_0xa53ad0, L_0xa53bc0, L_0xa53cb0; -L_0xa53d90 .delay (10000,10000,10000) L_0xa53d90/d; -v0xa055e0_0 .net "S0", 0 0, L_0xa54060; 1 drivers -v0xa056a0_0 .net "S1", 0 0, L_0xa54190; 1 drivers -v0xa05740_0 .net "in0", 0 0, L_0xa54320; 1 drivers -v0xa057e0_0 .net "in1", 0 0, L_0xa544d0; 1 drivers -v0xa05860_0 .net "in2", 0 0, L_0xa54570; 1 drivers -v0xa05900_0 .net "in3", 0 0, L_0xa54610; 1 drivers -v0xa059e0_0 .net "nS0", 0 0, L_0xa430c0; 1 drivers -v0xa05a80_0 .net "nS1", 0 0, L_0xa538f0; 1 drivers -v0xa05b20_0 .net "out", 0 0, L_0xa53d90; 1 drivers -v0xa05bc0_0 .net "out0", 0 0, L_0xa53990; 1 drivers -v0xa05c60_0 .net "out1", 0 0, L_0xa53ad0; 1 drivers -v0xa05d00_0 .net "out2", 0 0, L_0xa53bc0; 1 drivers -v0xa05e10_0 .net "out3", 0 0, L_0xa53cb0; 1 drivers -S_0xa04f80 .scope module, "TwoMux" "TwoInMux" 3 409, 3 8, S_0xa04e10; - .timescale -9 -12; -L_0xa542c0/d .functor NOT 1, L_0xa54b60, C4<0>, C4<0>, C4<0>; -L_0xa542c0 .delay (10000,10000,10000) L_0xa542c0/d; -L_0xa54750/d .functor AND 1, L_0xa54c00, L_0xa542c0, C4<1>, C4<1>; -L_0xa54750 .delay (20000,20000,20000) L_0xa54750/d; -L_0xa54840/d .functor AND 1, L_0xa54d40, L_0xa54b60, C4<1>, C4<1>; -L_0xa54840 .delay (20000,20000,20000) L_0xa54840/d; -L_0xa54930/d .functor OR 1, L_0xa54750, L_0xa54840, C4<0>, C4<0>; -L_0xa54930 .delay (20000,20000,20000) L_0xa54930/d; -v0xa05070_0 .net "S", 0 0, L_0xa54b60; 1 drivers -v0xa05110_0 .net "in0", 0 0, L_0xa54c00; 1 drivers -v0xa051b0_0 .net "in1", 0 0, L_0xa54d40; 1 drivers -v0xa05250_0 .net "nS", 0 0, L_0xa542c0; 1 drivers -v0xa052d0_0 .net "out0", 0 0, L_0xa54750; 1 drivers -v0xa05370_0 .net "out1", 0 0, L_0xa54840; 1 drivers -v0xa05450_0 .net "outfinal", 0 0, L_0xa54930; 1 drivers -S_0xa03290 .scope generate, "muxbits[2]" "muxbits[2]" 3 405, 3 405, S_0x9cd4a0; - .timescale -9 -12; -P_0xa021d8 .param/l "i" 3 405, +C4<010>; -L_0xa56f90/d .functor OR 1, L_0xa57790, L_0xa57b10, C4<0>, C4<0>; -L_0xa56f90 .delay (20000,20000,20000) L_0xa56f90/d; -v0xa04cb0_0 .net *"_s15", 0 0, L_0xa57790; 1 drivers -v0xa04d70_0 .net *"_s16", 0 0, L_0xa57b10; 1 drivers -S_0xa04330 .scope module, "ZeroMux" "FourInMux" 3 407, 3 24, S_0xa03290; - .timescale -9 -12; -L_0xa55260/d .functor NOT 1, L_0xa55160, C4<0>, C4<0>, C4<0>; -L_0xa55260 .delay (10000,10000,10000) L_0xa55260/d; -L_0xa55310/d .functor NOT 1, L_0xa55c40, C4<0>, C4<0>, C4<0>; -L_0xa55310 .delay (10000,10000,10000) L_0xa55310/d; -L_0xa553b0/d .functor NAND 1, L_0xa55260, L_0xa55310, L_0xa55af0, C4<1>; -L_0xa553b0 .delay (10000,10000,10000) L_0xa553b0/d; -L_0xa554f0/d .functor NAND 1, L_0xa55160, L_0xa55310, L_0xa55e40, C4<1>; -L_0xa554f0 .delay (10000,10000,10000) L_0xa554f0/d; -L_0xa555e0/d .functor NAND 1, L_0xa55260, L_0xa55c40, L_0xa55d70, C4<1>; -L_0xa555e0 .delay (10000,10000,10000) L_0xa555e0/d; -L_0xa556d0/d .functor NAND 1, L_0xa55160, L_0xa55c40, L_0xa56010, C4<1>; -L_0xa556d0 .delay (10000,10000,10000) L_0xa556d0/d; -L_0xa55840/d .functor NAND 1, L_0xa553b0, L_0xa554f0, L_0xa555e0, L_0xa556d0; -L_0xa55840 .delay (10000,10000,10000) L_0xa55840/d; -v0xa04420_0 .net "S0", 0 0, L_0xa55160; 1 drivers -v0xa044e0_0 .net "S1", 0 0, L_0xa55c40; 1 drivers -v0xa04580_0 .net "in0", 0 0, L_0xa55af0; 1 drivers -v0xa04620_0 .net "in1", 0 0, L_0xa55e40; 1 drivers -v0xa046a0_0 .net "in2", 0 0, L_0xa55d70; 1 drivers -v0xa04740_0 .net "in3", 0 0, L_0xa56010; 1 drivers -v0xa047e0_0 .net "nS0", 0 0, L_0xa55260; 1 drivers -v0xa04880_0 .net "nS1", 0 0, L_0xa55310; 1 drivers -v0xa04920_0 .net "out", 0 0, L_0xa55840; 1 drivers -v0xa049c0_0 .net "out0", 0 0, L_0xa553b0; 1 drivers -v0xa04a60_0 .net "out1", 0 0, L_0xa554f0; 1 drivers -v0xa04b00_0 .net "out2", 0 0, L_0xa555e0; 1 drivers -v0xa04c10_0 .net "out3", 0 0, L_0xa556d0; 1 drivers -S_0xa03970 .scope module, "OneMux" "FourInMux" 3 408, 3 24, S_0xa03290; - .timescale -9 -12; -L_0xa55ee0/d .functor NOT 1, L_0xa569e0, C4<0>, C4<0>, C4<0>; -L_0xa55ee0 .delay (10000,10000,10000) L_0xa55ee0/d; -L_0xa56240/d .functor NOT 1, L_0xa56100, C4<0>, C4<0>, C4<0>; -L_0xa56240 .delay (10000,10000,10000) L_0xa56240/d; -L_0xa562a0/d .functor NAND 1, L_0xa55ee0, L_0xa56240, L_0xa56ca0, C4<1>; -L_0xa562a0 .delay (10000,10000,10000) L_0xa562a0/d; -L_0xa563e0/d .functor NAND 1, L_0xa569e0, L_0xa56240, L_0xa56b10, C4<1>; -L_0xa563e0 .delay (10000,10000,10000) L_0xa563e0/d; -L_0xa564d0/d .functor NAND 1, L_0xa55ee0, L_0xa56100, L_0xa56e50, C4<1>; -L_0xa564d0 .delay (10000,10000,10000) L_0xa564d0/d; -L_0xa565c0/d .functor NAND 1, L_0xa569e0, L_0xa56100, L_0xa56d40, C4<1>; -L_0xa565c0 .delay (10000,10000,10000) L_0xa565c0/d; -L_0xa56730/d .functor NAND 1, L_0xa562a0, L_0xa563e0, L_0xa564d0, L_0xa565c0; -L_0xa56730 .delay (10000,10000,10000) L_0xa56730/d; -v0xa03a60_0 .net "S0", 0 0, L_0xa569e0; 1 drivers -v0xa03b20_0 .net "S1", 0 0, L_0xa56100; 1 drivers -v0xa03bc0_0 .net "in0", 0 0, L_0xa56ca0; 1 drivers -v0xa03c60_0 .net "in1", 0 0, L_0xa56b10; 1 drivers -v0xa03ce0_0 .net "in2", 0 0, L_0xa56e50; 1 drivers -v0xa03d80_0 .net "in3", 0 0, L_0xa56d40; 1 drivers -v0xa03e60_0 .net "nS0", 0 0, L_0xa55ee0; 1 drivers -v0xa03f00_0 .net "nS1", 0 0, L_0xa56240; 1 drivers -v0xa03fa0_0 .net "out", 0 0, L_0xa56730; 1 drivers -v0xa04040_0 .net "out0", 0 0, L_0xa562a0; 1 drivers -v0xa040e0_0 .net "out1", 0 0, L_0xa563e0; 1 drivers -v0xa04180_0 .net "out2", 0 0, L_0xa564d0; 1 drivers -v0xa04290_0 .net "out3", 0 0, L_0xa565c0; 1 drivers -S_0xa03400 .scope module, "TwoMux" "TwoInMux" 3 409, 3 8, S_0xa03290; - .timescale -9 -12; -L_0xa56de0/d .functor NOT 1, L_0xa56ef0, C4<0>, C4<0>, C4<0>; -L_0xa56de0 .delay (10000,10000,10000) L_0xa56de0/d; -L_0xa570a0/d .functor AND 1, L_0xa57620, L_0xa56de0, C4<1>, C4<1>; -L_0xa570a0 .delay (20000,20000,20000) L_0xa570a0/d; -L_0xa57190/d .functor AND 1, L_0xa574f0, L_0xa56ef0, C4<1>, C4<1>; -L_0xa57190 .delay (20000,20000,20000) L_0xa57190/d; -L_0xa57280/d .functor OR 1, L_0xa570a0, L_0xa57190, C4<0>, C4<0>; -L_0xa57280 .delay (20000,20000,20000) L_0xa57280/d; -v0xa034f0_0 .net "S", 0 0, L_0xa56ef0; 1 drivers -v0xa03590_0 .net "in0", 0 0, L_0xa57620; 1 drivers -v0xa03630_0 .net "in1", 0 0, L_0xa574f0; 1 drivers -v0xa036d0_0 .net "nS", 0 0, L_0xa56de0; 1 drivers -v0xa03750_0 .net "out0", 0 0, L_0xa570a0; 1 drivers -v0xa037f0_0 .net "out1", 0 0, L_0xa57190; 1 drivers -v0xa038d0_0 .net "outfinal", 0 0, L_0xa57280; 1 drivers -S_0x9308d0 .scope generate, "muxbits[3]" "muxbits[3]" 3 405, 3 405, S_0x9cd4a0; - .timescale -9 -12; -P_0x89e2c8 .param/l "i" 3 405, +C4<011>; -L_0xa5a0c0/d .functor OR 1, L_0xa5a440, L_0xa5a250, C4<0>, C4<0>; -L_0xa5a0c0 .delay (20000,20000,20000) L_0xa5a0c0/d; -v0xa03130_0 .net *"_s15", 0 0, L_0xa5a440; 1 drivers -v0xa031f0_0 .net *"_s16", 0 0, L_0xa5a250; 1 drivers -S_0xa027b0 .scope module, "ZeroMux" "FourInMux" 3 407, 3 24, S_0x9308d0; - .timescale -9 -12; -L_0xa579c0/d .functor NOT 1, L_0xa584f0, C4<0>, C4<0>, C4<0>; -L_0xa579c0 .delay (10000,10000,10000) L_0xa579c0/d; -L_0xa57ab0/d .functor NOT 1, L_0xa57bb0, C4<0>, C4<0>, C4<0>; -L_0xa57ab0 .delay (10000,10000,10000) L_0xa57ab0/d; -L_0xa57d50/d .functor NAND 1, L_0xa579c0, L_0xa57ab0, L_0xa58790, C4<1>; -L_0xa57d50 .delay (10000,10000,10000) L_0xa57d50/d; -L_0xa57e90/d .functor NAND 1, L_0xa584f0, L_0xa57ab0, L_0xa58620, C4<1>; -L_0xa57e90 .delay (10000,10000,10000) L_0xa57e90/d; -L_0xa57f80/d .functor NAND 1, L_0xa579c0, L_0xa57bb0, L_0xa586c0, C4<1>; -L_0xa57f80 .delay (10000,10000,10000) L_0xa57f80/d; -L_0xa580d0/d .functor NAND 1, L_0xa584f0, L_0xa57bb0, L_0xa58830, C4<1>; -L_0xa580d0 .delay (10000,10000,10000) L_0xa580d0/d; -L_0xa58240/d .functor NAND 1, L_0xa57d50, L_0xa57e90, L_0xa57f80, L_0xa580d0; -L_0xa58240 .delay (10000,10000,10000) L_0xa58240/d; -v0xa028a0_0 .net "S0", 0 0, L_0xa584f0; 1 drivers -v0xa02960_0 .net "S1", 0 0, L_0xa57bb0; 1 drivers -v0xa02a00_0 .net "in0", 0 0, L_0xa58790; 1 drivers -v0xa02aa0_0 .net "in1", 0 0, L_0xa58620; 1 drivers -v0xa02b20_0 .net "in2", 0 0, L_0xa586c0; 1 drivers -v0xa02bc0_0 .net "in3", 0 0, L_0xa58830; 1 drivers -v0xa02c60_0 .net "nS0", 0 0, L_0xa579c0; 1 drivers -v0xa02d00_0 .net "nS1", 0 0, L_0xa57ab0; 1 drivers -v0xa02da0_0 .net "out", 0 0, L_0xa58240; 1 drivers -v0xa02e40_0 .net "out0", 0 0, L_0xa57d50; 1 drivers -v0xa02ee0_0 .net "out1", 0 0, L_0xa57e90; 1 drivers -v0xa02f80_0 .net "out2", 0 0, L_0xa57f80; 1 drivers -v0xa03090_0 .net "out3", 0 0, L_0xa580d0; 1 drivers -S_0xa01d40 .scope module, "OneMux" "FourInMux" 3 408, 3 24, S_0x9308d0; - .timescale -9 -12; -L_0xa58920/d .functor NOT 1, L_0xa58a00, C4<0>, C4<0>, C4<0>; -L_0xa58920 .delay (10000,10000,10000) L_0xa58920/d; -L_0xa58c20/d .functor NOT 1, L_0xa59540, C4<0>, C4<0>, C4<0>; -L_0xa58c20 .delay (10000,10000,10000) L_0xa58c20/d; -L_0xa58cc0/d .functor NAND 1, L_0xa58920, L_0xa58c20, L_0xa593a0, C4<1>; -L_0xa58cc0 .delay (10000,10000,10000) L_0xa58cc0/d; -L_0xa58e00/d .functor NAND 1, L_0xa58a00, L_0xa58c20, L_0xa59440, C4<1>; -L_0xa58e00 .delay (10000,10000,10000) L_0xa58e00/d; -L_0xa58ef0/d .functor NAND 1, L_0xa58920, L_0xa59540, L_0xa59830, C4<1>; -L_0xa58ef0 .delay (10000,10000,10000) L_0xa58ef0/d; -L_0xa58fe0/d .functor NAND 1, L_0xa58a00, L_0xa59540, L_0xa598d0, C4<1>; -L_0xa58fe0 .delay (10000,10000,10000) L_0xa58fe0/d; -L_0xa590f0/d .functor NAND 1, L_0xa58cc0, L_0xa58e00, L_0xa58ef0, L_0xa58fe0; -L_0xa590f0 .delay (10000,10000,10000) L_0xa590f0/d; -v0xa01e30_0 .net "S0", 0 0, L_0xa58a00; 1 drivers -v0xa01ef0_0 .net "S1", 0 0, L_0xa59540; 1 drivers -v0xa01f90_0 .net "in0", 0 0, L_0xa593a0; 1 drivers -v0xa02030_0 .net "in1", 0 0, L_0xa59440; 1 drivers -v0xa020b0_0 .net "in2", 0 0, L_0xa59830; 1 drivers -v0xa02150_0 .net "in3", 0 0, L_0xa598d0; 1 drivers -v0xa02230_0 .net "nS0", 0 0, L_0xa58920; 1 drivers -v0xa022d0_0 .net "nS1", 0 0, L_0xa58c20; 1 drivers -v0xa023c0_0 .net "out", 0 0, L_0xa590f0; 1 drivers -v0xa02460_0 .net "out0", 0 0, L_0xa58cc0; 1 drivers -v0xa02560_0 .net "out1", 0 0, L_0xa58e00; 1 drivers -v0xa02600_0 .net "out2", 0 0, L_0xa58ef0; 1 drivers -v0xa02710_0 .net "out3", 0 0, L_0xa58fe0; 1 drivers -S_0x98b6e0 .scope module, "TwoMux" "TwoInMux" 3 409, 3 8, S_0x9308d0; - .timescale -9 -12; -L_0xa535a0/d .functor NOT 1, L_0xa59f80, C4<0>, C4<0>, C4<0>; -L_0xa535a0 .delay (10000,10000,10000) L_0xa535a0/d; -L_0xa59670/d .functor AND 1, L_0xa59b80, L_0xa535a0, C4<1>, C4<1>; -L_0xa59670 .delay (20000,20000,20000) L_0xa59670/d; -L_0xa59760/d .functor AND 1, L_0xa59c70, L_0xa59f80, C4<1>, C4<1>; -L_0xa59760 .delay (20000,20000,20000) L_0xa59760/d; -L_0xa59da0/d .functor OR 1, L_0xa59670, L_0xa59760, C4<0>, C4<0>; -L_0xa59da0 .delay (20000,20000,20000) L_0xa59da0/d; -v0x90c030_0 .net "S", 0 0, L_0xa59f80; 1 drivers -v0x910ec0_0 .net "in0", 0 0, L_0xa59b80; 1 drivers -v0x910f60_0 .net "in1", 0 0, L_0xa59c70; 1 drivers -v0x911000_0 .net "nS", 0 0, L_0xa535a0; 1 drivers -v0x9110b0_0 .net "out0", 0 0, L_0xa59670; 1 drivers -v0x911150_0 .net "out1", 0 0, L_0xa59760; 1 drivers -v0x911230_0 .net "outfinal", 0 0, L_0xa59da0; 1 drivers - .scope S_0x96f1c0; +S_0xeed190 .scope module, "test32Adder" "test32Adder" 2 126; + .timescale -9 -12; +P_0xe82438 .param/l "size" 2 127, +C4<0100>; +v0xffc310_0 .var "A", 3 0; +RS_0x7f9963cefbe8/0/0 .resolv tri, L_0xffdb80, L_0xfff100, L_0x10005d0, L_0x1001bd0; +RS_0x7f9963cefbe8/0/4 .resolv tri, L_0x10267e0, L_0x1027d20, L_0x10291f0, L_0x102aaf0; +RS_0x7f9963cefbe8 .resolv tri, RS_0x7f9963cefbe8/0/0, RS_0x7f9963cefbe8/0/4, C4, C4; +v0xffc3b0_0 .net8 "AddSubSLTSum", 3 0, RS_0x7f9963cefbe8; 8 drivers +v0xffc430_0 .net "AllZeros", 0 0, L_0x1035f20; 1 drivers +RS_0x7f9963ceee38/0/0 .resolv tri, L_0x100d070, L_0x100db20, L_0x100e590, L_0x100eff0; +RS_0x7f9963ceee38/0/4 .resolv tri, L_0x102bbf0, L_0x102c660, L_0x102d0d0, L_0x102dc30; +RS_0x7f9963ceee38 .resolv tri, RS_0x7f9963ceee38/0/0, RS_0x7f9963ceee38/0/4, C4, C4; +v0xffc4b0_0 .net8 "AndNandOut", 3 0, RS_0x7f9963ceee38; 8 drivers +v0xffc560_0 .var "B", 3 0; +v0xffc5e0_0 .var "Command", 2 0; +RS_0x7f9963cf1868 .resolv tri, L_0x10160c0, L_0x1018a20, L_0x101b540, L_0x1035390; +v0xffc660_0 .net8 "OneBitFinalOut", 3 0, RS_0x7f9963cf1868; 4 drivers +RS_0x7f9963cee748/0/0 .resolv tri, L_0x10103b0, L_0x10116f0, L_0x10129f0, L_0x1013ce0; +RS_0x7f9963cee748/0/4 .resolv tri, L_0x1009490, L_0x1030990, L_0x1031c50, L_0x1032f40; +RS_0x7f9963cee748 .resolv tri, RS_0x7f9963cee748/0/0, RS_0x7f9963cee748/0/4, C4, C4; +v0xffc6e0_0 .net8 "OrNorXorOut", 3 0, RS_0x7f9963cee748; 8 drivers +RS_0x7f9963cf1538/0/0 .resolv tri, L_0x10045c0, L_0x10068d0, L_0x1008da0, L_0x100c6c0; +RS_0x7f9963cf1538/0/4 .resolv tri, L_0x101dbc0, L_0x101fdd0, L_0x1022050, L_0x1025660; +RS_0x7f9963cf1538 .resolv tri, RS_0x7f9963cf1538/0/0, RS_0x7f9963cf1538/0/4, C4, C4; +v0xffc760_0 .net8 "SLTSum", 3 0, RS_0x7f9963cf1538; 8 drivers +v0xffc7e0_0 .net "SLTflag", 0 0, L_0x10250b0; 1 drivers +v0xffc8f0_0 .net "SLTflag1", 0 0, L_0x100c180; 1 drivers +RS_0x7f9963cf1898 .resolv tri, L_0x1016570, L_0x1018ef0, L_0x101b680, L_0x1035650; +v0xffc970_0 .net8 "ZeroFlag", 3 0, RS_0x7f9963cf1898; 4 drivers +v0xffca90_0 .var "carryin", 3 0; +RS_0x7f9963cefd08 .resolv tri, L_0x1001f50, L_0x100adb0, L_0x1023e10, L_0x102ae70; +v0xffcb10_0 .net8 "carryout", 0 0, RS_0x7f9963cefd08; 4 drivers +RS_0x7f9963cefd38 .resolv tri, L_0x10023c0, L_0x100b770, L_0x1024700, L_0x1023db0; +v0xffcc10_0 .net8 "overflow", 0 0, RS_0x7f9963cefd38; 4 drivers +RS_0x7f9963cefd68/0/0 .resolv tri, L_0xffddc0, L_0xfff330, L_0x10007b0, L_0x1000c60; +RS_0x7f9963cefd68/0/4 .resolv tri, L_0x1003760, L_0x1005ac0, L_0x1006b60, L_0xff2320; +RS_0x7f9963cefd68/0/8 .resolv tri, L_0x101ccc0, L_0x101efd0, L_0x1020060, L_0x1022830; +RS_0x7f9963cefd68/0/12 .resolv tri, L_0x10269e0, L_0x1027f50, L_0x10294f0, L_0x1008250; +RS_0x7f9963cefd68 .resolv tri, RS_0x7f9963cefd68/0/0, RS_0x7f9963cefd68/0/4, RS_0x7f9963cefd68/0/8, RS_0x7f9963cefd68/0/12; +v0xffcc90_0 .net8 "subtract", 3 0, RS_0x7f9963cefd68; 16 drivers +S_0xff73e0 .scope module, "trial" "AddSubSLT32" 2 147, 3 166, S_0xeed190; + .timescale -9 -12; +P_0xff5ad8 .param/l "size" 3 180, +C4<0100>; +L_0x1001f50/d .functor OR 1, L_0x1002210, C4<0>, C4<0>, C4<0>; +L_0x1001f50 .delay (20000,20000,20000) L_0x1001f50/d; +L_0x10023c0/d .functor XOR 1, RS_0x7f9963cefd08, L_0x10024b0, C4<0>, C4<0>; +L_0x10023c0 .delay (40000,40000,40000) L_0x10023c0/d; +v0xffb8e0_0 .net "A", 3 0, v0xffc310_0; 1 drivers +v0xfe5a60_0 .alias "AddSubSLTSum", 3 0, v0xffc3b0_0; +v0xffba90_0 .net "B", 3 0, v0xffc560_0; 1 drivers +RS_0x7f9963cf5558 .resolv tri, L_0xffdcd0, L_0xfff1f0, L_0x10006c0, L_0x1001cc0; +v0xfe5cf0_0 .net8 "CarryoutWire", 3 0, RS_0x7f9963cf5558; 4 drivers +v0xffbc20_0 .net "Command", 2 0, v0xffc5e0_0; 1 drivers +v0xffbca0_0 .net *"_s40", 0 0, L_0x1002210; 1 drivers +v0xffbd40_0 .net/s *"_s41", 0 0, C4<0>; 1 drivers +v0xffbde0_0 .net *"_s44", 0 0, L_0x10024b0; 1 drivers +v0xffbed0_0 .net "carryin", 3 0, v0xffca90_0; 1 drivers +v0xffbfe0_0 .alias "carryout", 0 0, v0xffcb10_0; +v0xffc0f0_0 .alias "overflow", 0 0, v0xffcc10_0; +v0xffc200_0 .alias "subtract", 3 0, v0xffcc90_0; +L_0xffdb80 .part/pv L_0xffd670, 1, 1, 4; +L_0xffdcd0 .part/pv L_0xffda20, 1, 1, 4; +L_0xffddc0 .part/pv L_0xffd370, 1, 1, 4; +L_0xffdeb0 .part v0xffc310_0, 1, 1; +L_0xffdf50 .part v0xffc560_0, 1, 1; +L_0xffe080 .part RS_0x7f9963cf5558, 0, 1; +L_0xfff100 .part/pv L_0xffec50, 2, 1, 4; +L_0xfff1f0 .part/pv L_0xffefa0, 2, 1, 4; +L_0xfff330 .part/pv L_0xffe980, 2, 1, 4; +L_0xfff420 .part v0xffc310_0, 2, 1; +L_0xfff520 .part v0xffc560_0, 2, 1; +L_0xfff650 .part RS_0x7f9963cf5558, 1, 1; +L_0x10005d0 .part/pv L_0x1000120, 3, 1, 4; +L_0x10006c0 .part/pv L_0x1000470, 3, 1, 4; +L_0x10007b0 .part/pv L_0xfffe50, 3, 1, 4; +L_0x1000960 .part v0xffc310_0, 3, 1; +L_0x1000a90 .part v0xffc560_0, 3, 1; +L_0x1000bc0 .part RS_0x7f9963cf5558, 2, 1; +L_0x1001bd0 .part/pv L_0x1001720, 0, 1, 4; +L_0x1001cc0 .part/pv L_0x1001a70, 0, 1, 4; +L_0x1000c60 .part/pv L_0x1001450, 0, 1, 4; +L_0x1001eb0 .part v0xffc310_0, 0, 1; +L_0x1001db0 .part v0xffc560_0, 0, 1; +L_0x10020a0 .part RS_0x7f9963cefd68, 0, 1; +L_0x1002210 .part RS_0x7f9963cf5558, 3, 1; +L_0x10024b0 .part RS_0x7f9963cf5558, 2, 1; +S_0xffa8d0 .scope module, "attempt2" "MiddleAddSubSLT" 3 177, 3 88, S_0xff73e0; + .timescale -9 -12; +L_0x1000a00/d .functor NOT 1, L_0x1001db0, C4<0>, C4<0>, C4<0>; +L_0x1000a00 .delay (10000,10000,10000) L_0x1000a00/d; +L_0x10012f0/d .functor NOT 1, L_0x10013b0, C4<0>, C4<0>, C4<0>; +L_0x10012f0 .delay (10000,10000,10000) L_0x10012f0/d; +L_0x1001450/d .functor AND 1, L_0x1001590, L_0x10012f0, C4<1>, C4<1>; +L_0x1001450 .delay (20000,20000,20000) L_0x1001450/d; +L_0x1001630/d .functor XOR 1, L_0x1001eb0, L_0x1001080, C4<0>, C4<0>; +L_0x1001630 .delay (40000,40000,40000) L_0x1001630/d; +L_0x1001720/d .functor XOR 1, L_0x1001630, L_0x10020a0, C4<0>, C4<0>; +L_0x1001720 .delay (40000,40000,40000) L_0x1001720/d; +L_0x1001810/d .functor AND 1, L_0x1001eb0, L_0x1001080, C4<1>, C4<1>; +L_0x1001810 .delay (20000,20000,20000) L_0x1001810/d; +L_0x1001980/d .functor AND 1, L_0x1001630, L_0x10020a0, C4<1>, C4<1>; +L_0x1001980 .delay (20000,20000,20000) L_0x1001980/d; +L_0x1001a70/d .functor OR 1, L_0x1001810, L_0x1001980, C4<0>, C4<0>; +L_0x1001a70 .delay (20000,20000,20000) L_0x1001a70/d; +v0xffaf40_0 .net "A", 0 0, L_0x1001eb0; 1 drivers +v0xffb000_0 .net "AandB", 0 0, L_0x1001810; 1 drivers +v0xffb0a0_0 .net "AddSubSLTSum", 0 0, L_0x1001720; 1 drivers +v0xffb140_0 .net "AxorB", 0 0, L_0x1001630; 1 drivers +v0xffb1c0_0 .net "B", 0 0, L_0x1001db0; 1 drivers +v0xffb270_0 .net "BornB", 0 0, L_0x1001080; 1 drivers +v0xffb330_0 .net "CINandAxorB", 0 0, L_0x1001980; 1 drivers +v0xffb3b0_0 .alias "Command", 2 0, v0xffbc20_0; +v0xffb430_0 .net *"_s3", 0 0, L_0x10013b0; 1 drivers +v0xffb4b0_0 .net *"_s5", 0 0, L_0x1001590; 1 drivers +v0xffb550_0 .net "carryin", 0 0, L_0x10020a0; 1 drivers +v0xffb5f0_0 .net "carryout", 0 0, L_0x1001a70; 1 drivers +v0xffb690_0 .net "nB", 0 0, L_0x1000a00; 1 drivers +v0xffb740_0 .net "nCmd2", 0 0, L_0x10012f0; 1 drivers +v0xffb840_0 .net "subtract", 0 0, L_0x1001450; 1 drivers +L_0x1001250 .part v0xffc5e0_0, 0, 1; +L_0x10013b0 .part v0xffc5e0_0, 2, 1; +L_0x1001590 .part v0xffc5e0_0, 0, 1; +S_0xffa9c0 .scope module, "mux0" "TwoInMux" 3 104, 3 8, S_0xffa8d0; + .timescale -9 -12; +L_0x1000da0/d .functor NOT 1, L_0x1001250, C4<0>, C4<0>, C4<0>; +L_0x1000da0 .delay (10000,10000,10000) L_0x1000da0/d; +L_0x1000e60/d .functor AND 1, L_0x1001db0, L_0x1000da0, C4<1>, C4<1>; +L_0x1000e60 .delay (20000,20000,20000) L_0x1000e60/d; +L_0x1000f70/d .functor AND 1, L_0x1000a00, L_0x1001250, C4<1>, C4<1>; +L_0x1000f70 .delay (20000,20000,20000) L_0x1000f70/d; +L_0x1001080/d .functor OR 1, L_0x1000e60, L_0x1000f70, C4<0>, C4<0>; +L_0x1001080 .delay (20000,20000,20000) L_0x1001080/d; +v0xffaab0_0 .net "S", 0 0, L_0x1001250; 1 drivers +v0xffab70_0 .alias "in0", 0 0, v0xffb1c0_0; +v0xffac10_0 .alias "in1", 0 0, v0xffb690_0; +v0xffacb0_0 .net "nS", 0 0, L_0x1000da0; 1 drivers +v0xffad60_0 .net "out0", 0 0, L_0x1000e60; 1 drivers +v0xffae00_0 .net "out1", 0 0, L_0x1000f70; 1 drivers +v0xffaea0_0 .alias "outfinal", 0 0, v0xffb270_0; +S_0xff9730 .scope generate, "addbits[1]" "addbits[1]" 3 182, 3 182, S_0xff73e0; + .timescale -9 -12; +P_0xff9148 .param/l "i" 3 182, +C4<01>; +S_0xff98a0 .scope module, "attempt" "MiddleAddSubSLT" 3 184, 3 88, S_0xff9730; + .timescale -9 -12; +L_0xff4140/d .functor NOT 1, L_0xffdf50, C4<0>, C4<0>, C4<0>; +L_0xff4140 .delay (10000,10000,10000) L_0xff4140/d; +L_0xffd210/d .functor NOT 1, L_0xffd2d0, C4<0>, C4<0>, C4<0>; +L_0xffd210 .delay (10000,10000,10000) L_0xffd210/d; +L_0xffd370/d .functor AND 1, L_0xffd4b0, L_0xffd210, C4<1>, C4<1>; +L_0xffd370 .delay (20000,20000,20000) L_0xffd370/d; +L_0xffd550/d .functor XOR 1, L_0xffdeb0, L_0xffcff0, C4<0>, C4<0>; +L_0xffd550 .delay (40000,40000,40000) L_0xffd550/d; +L_0xffd670/d .functor XOR 1, L_0xffd550, L_0xffe080, C4<0>, C4<0>; +L_0xffd670 .delay (40000,40000,40000) L_0xffd670/d; +L_0xffd790/d .functor AND 1, L_0xffdeb0, L_0xffcff0, C4<1>, C4<1>; +L_0xffd790 .delay (20000,20000,20000) L_0xffd790/d; +L_0xffd930/d .functor AND 1, L_0xffd550, L_0xffe080, C4<1>, C4<1>; +L_0xffd930 .delay (20000,20000,20000) L_0xffd930/d; +L_0xffda20/d .functor OR 1, L_0xffd790, L_0xffd930, C4<0>, C4<0>; +L_0xffda20 .delay (20000,20000,20000) L_0xffda20/d; +v0xff9f30_0 .net "A", 0 0, L_0xffdeb0; 1 drivers +v0xff9ff0_0 .net "AandB", 0 0, L_0xffd790; 1 drivers +v0xffa090_0 .net "AddSubSLTSum", 0 0, L_0xffd670; 1 drivers +v0xffa130_0 .net "AxorB", 0 0, L_0xffd550; 1 drivers +v0xffa1b0_0 .net "B", 0 0, L_0xffdf50; 1 drivers +v0xffa260_0 .net "BornB", 0 0, L_0xffcff0; 1 drivers +v0xffa320_0 .net "CINandAxorB", 0 0, L_0xffd930; 1 drivers +v0xffa3a0_0 .alias "Command", 2 0, v0xffbc20_0; +v0xffa420_0 .net *"_s3", 0 0, L_0xffd2d0; 1 drivers +v0xffa4a0_0 .net *"_s5", 0 0, L_0xffd4b0; 1 drivers +v0xffa540_0 .net "carryin", 0 0, L_0xffe080; 1 drivers +v0xffa5e0_0 .net "carryout", 0 0, L_0xffda20; 1 drivers +v0xffa680_0 .net "nB", 0 0, L_0xff4140; 1 drivers +v0xffa730_0 .net "nCmd2", 0 0, L_0xffd210; 1 drivers +v0xffa830_0 .net "subtract", 0 0, L_0xffd370; 1 drivers +L_0xffd170 .part v0xffc5e0_0, 0, 1; +L_0xffd2d0 .part v0xffc5e0_0, 2, 1; +L_0xffd4b0 .part v0xffc5e0_0, 0, 1; +S_0xff9990 .scope module, "mux0" "TwoInMux" 3 104, 3 8, S_0xff98a0; + .timescale -9 -12; +L_0xffcda0/d .functor NOT 1, L_0xffd170, C4<0>, C4<0>, C4<0>; +L_0xffcda0 .delay (10000,10000,10000) L_0xffcda0/d; +L_0xffce40/d .functor AND 1, L_0xffdf50, L_0xffcda0, C4<1>, C4<1>; +L_0xffce40 .delay (20000,20000,20000) L_0xffce40/d; +L_0xffcf30/d .functor AND 1, L_0xff4140, L_0xffd170, C4<1>, C4<1>; +L_0xffcf30 .delay (20000,20000,20000) L_0xffcf30/d; +L_0xffcff0/d .functor OR 1, L_0xffce40, L_0xffcf30, C4<0>, C4<0>; +L_0xffcff0 .delay (20000,20000,20000) L_0xffcff0/d; +v0xff9a80_0 .net "S", 0 0, L_0xffd170; 1 drivers +v0xff9b20_0 .alias "in0", 0 0, v0xffa1b0_0; +v0xff9bc0_0 .alias "in1", 0 0, v0xffa680_0; +v0xff9c60_0 .net "nS", 0 0, L_0xffcda0; 1 drivers +v0xff9d10_0 .net "out0", 0 0, L_0xffce40; 1 drivers +v0xff9db0_0 .net "out1", 0 0, L_0xffcf30; 1 drivers +v0xff9e90_0 .alias "outfinal", 0 0, v0xffa260_0; +S_0xff8590 .scope generate, "addbits[2]" "addbits[2]" 3 182, 3 182, S_0xff73e0; + .timescale -9 -12; +P_0xff7f88 .param/l "i" 3 182, +C4<010>; +S_0xff8700 .scope module, "attempt" "MiddleAddSubSLT" 3 184, 3 88, S_0xff8590; + .timescale -9 -12; +L_0xffe120/d .functor NOT 1, L_0xfff520, C4<0>, C4<0>, C4<0>; +L_0xffe120 .delay (10000,10000,10000) L_0xffe120/d; +L_0xffe820/d .functor NOT 1, L_0xffe8e0, C4<0>, C4<0>, C4<0>; +L_0xffe820 .delay (10000,10000,10000) L_0xffe820/d; +L_0xffe980/d .functor AND 1, L_0xffeac0, L_0xffe820, C4<1>, C4<1>; +L_0xffe980 .delay (20000,20000,20000) L_0xffe980/d; +L_0xffeb60/d .functor XOR 1, L_0xfff420, L_0xffe5b0, C4<0>, C4<0>; +L_0xffeb60 .delay (40000,40000,40000) L_0xffeb60/d; +L_0xffec50/d .functor XOR 1, L_0xffeb60, L_0xfff650, C4<0>, C4<0>; +L_0xffec50 .delay (40000,40000,40000) L_0xffec50/d; +L_0xffed40/d .functor AND 1, L_0xfff420, L_0xffe5b0, C4<1>, C4<1>; +L_0xffed40 .delay (20000,20000,20000) L_0xffed40/d; +L_0xffeeb0/d .functor AND 1, L_0xffeb60, L_0xfff650, C4<1>, C4<1>; +L_0xffeeb0 .delay (20000,20000,20000) L_0xffeeb0/d; +L_0xffefa0/d .functor OR 1, L_0xffed40, L_0xffeeb0, C4<0>, C4<0>; +L_0xffefa0 .delay (20000,20000,20000) L_0xffefa0/d; +v0xff8d90_0 .net "A", 0 0, L_0xfff420; 1 drivers +v0xff8e50_0 .net "AandB", 0 0, L_0xffed40; 1 drivers +v0xff8ef0_0 .net "AddSubSLTSum", 0 0, L_0xffec50; 1 drivers +v0xff8f90_0 .net "AxorB", 0 0, L_0xffeb60; 1 drivers +v0xff9010_0 .net "B", 0 0, L_0xfff520; 1 drivers +v0xff90c0_0 .net "BornB", 0 0, L_0xffe5b0; 1 drivers +v0xff9180_0 .net "CINandAxorB", 0 0, L_0xffeeb0; 1 drivers +v0xff9200_0 .alias "Command", 2 0, v0xffbc20_0; +v0xff9280_0 .net *"_s3", 0 0, L_0xffe8e0; 1 drivers +v0xff9300_0 .net *"_s5", 0 0, L_0xffeac0; 1 drivers +v0xff93a0_0 .net "carryin", 0 0, L_0xfff650; 1 drivers +v0xff9440_0 .net "carryout", 0 0, L_0xffefa0; 1 drivers +v0xff94e0_0 .net "nB", 0 0, L_0xffe120; 1 drivers +v0xff9590_0 .net "nCmd2", 0 0, L_0xffe820; 1 drivers +v0xff9690_0 .net "subtract", 0 0, L_0xffe980; 1 drivers +L_0xffe780 .part v0xffc5e0_0, 0, 1; +L_0xffe8e0 .part v0xffc5e0_0, 2, 1; +L_0xffeac0 .part v0xffc5e0_0, 0, 1; +S_0xff87f0 .scope module, "mux0" "TwoInMux" 3 104, 3 8, S_0xff8700; + .timescale -9 -12; +L_0xffe2d0/d .functor NOT 1, L_0xffe780, C4<0>, C4<0>, C4<0>; +L_0xffe2d0 .delay (10000,10000,10000) L_0xffe2d0/d; +L_0xffe390/d .functor AND 1, L_0xfff520, L_0xffe2d0, C4<1>, C4<1>; +L_0xffe390 .delay (20000,20000,20000) L_0xffe390/d; +L_0xffe4a0/d .functor AND 1, L_0xffe120, L_0xffe780, C4<1>, C4<1>; +L_0xffe4a0 .delay (20000,20000,20000) L_0xffe4a0/d; +L_0xffe5b0/d .functor OR 1, L_0xffe390, L_0xffe4a0, C4<0>, C4<0>; +L_0xffe5b0 .delay (20000,20000,20000) L_0xffe5b0/d; +v0xff88e0_0 .net "S", 0 0, L_0xffe780; 1 drivers +v0xff8980_0 .alias "in0", 0 0, v0xff9010_0; +v0xff8a20_0 .alias "in1", 0 0, v0xff94e0_0; +v0xff8ac0_0 .net "nS", 0 0, L_0xffe2d0; 1 drivers +v0xff8b70_0 .net "out0", 0 0, L_0xffe390; 1 drivers +v0xff8c10_0 .net "out1", 0 0, L_0xffe4a0; 1 drivers +v0xff8cf0_0 .alias "outfinal", 0 0, v0xff90c0_0; +S_0xff74d0 .scope generate, "addbits[3]" "addbits[3]" 3 182, 3 182, S_0xff73e0; + .timescale -9 -12; +P_0xff71b8 .param/l "i" 3 182, +C4<011>; +S_0xff75c0 .scope module, "attempt" "MiddleAddSubSLT" 3 184, 3 88, S_0xff74d0; + .timescale -9 -12; +L_0xfff4c0/d .functor NOT 1, L_0x1000a90, C4<0>, C4<0>, C4<0>; +L_0xfff4c0 .delay (10000,10000,10000) L_0xfff4c0/d; +L_0xfffcf0/d .functor NOT 1, L_0xfffdb0, C4<0>, C4<0>, C4<0>; +L_0xfffcf0 .delay (10000,10000,10000) L_0xfffcf0/d; +L_0xfffe50/d .functor AND 1, L_0xffff90, L_0xfffcf0, C4<1>, C4<1>; +L_0xfffe50 .delay (20000,20000,20000) L_0xfffe50/d; +L_0x1000030/d .functor XOR 1, L_0x1000960, L_0xfffa80, C4<0>, C4<0>; +L_0x1000030 .delay (40000,40000,40000) L_0x1000030/d; +L_0x1000120/d .functor XOR 1, L_0x1000030, L_0x1000bc0, C4<0>, C4<0>; +L_0x1000120 .delay (40000,40000,40000) L_0x1000120/d; +L_0x1000210/d .functor AND 1, L_0x1000960, L_0xfffa80, C4<1>, C4<1>; +L_0x1000210 .delay (20000,20000,20000) L_0x1000210/d; +L_0x1000380/d .functor AND 1, L_0x1000030, L_0x1000bc0, C4<1>, C4<1>; +L_0x1000380 .delay (20000,20000,20000) L_0x1000380/d; +L_0x1000470/d .functor OR 1, L_0x1000210, L_0x1000380, C4<0>, C4<0>; +L_0x1000470 .delay (20000,20000,20000) L_0x1000470/d; +v0xff7c00_0 .net "A", 0 0, L_0x1000960; 1 drivers +v0xff7cc0_0 .net "AandB", 0 0, L_0x1000210; 1 drivers +v0xff7d60_0 .net "AddSubSLTSum", 0 0, L_0x1000120; 1 drivers +v0xff7e00_0 .net "AxorB", 0 0, L_0x1000030; 1 drivers +v0xff7e80_0 .net "B", 0 0, L_0x1000a90; 1 drivers +v0xff7f00_0 .net "BornB", 0 0, L_0xfffa80; 1 drivers +v0xff7fc0_0 .net "CINandAxorB", 0 0, L_0x1000380; 1 drivers +v0xff8040_0 .alias "Command", 2 0, v0xffbc20_0; +v0xff8110_0 .net *"_s3", 0 0, L_0xfffdb0; 1 drivers +v0xff8190_0 .net *"_s5", 0 0, L_0xffff90; 1 drivers +v0xff8230_0 .net "carryin", 0 0, L_0x1000bc0; 1 drivers +v0xff82d0_0 .net "carryout", 0 0, L_0x1000470; 1 drivers +v0xff8370_0 .net "nB", 0 0, L_0xfff4c0; 1 drivers +v0xff83f0_0 .net "nCmd2", 0 0, L_0xfffcf0; 1 drivers +v0xff84f0_0 .net "subtract", 0 0, L_0xfffe50; 1 drivers +L_0xfffc50 .part v0xffc5e0_0, 0, 1; +L_0xfffdb0 .part v0xffc5e0_0, 2, 1; +L_0xffff90 .part v0xffc5e0_0, 0, 1; +S_0xff76b0 .scope module, "mux0" "TwoInMux" 3 104, 3 8, S_0xff75c0; + .timescale -9 -12; +L_0xfff7e0/d .functor NOT 1, L_0xfffc50, C4<0>, C4<0>, C4<0>; +L_0xfff7e0 .delay (10000,10000,10000) L_0xfff7e0/d; +L_0xfff860/d .functor AND 1, L_0x1000a90, L_0xfff7e0, C4<1>, C4<1>; +L_0xfff860 .delay (20000,20000,20000) L_0xfff860/d; +L_0xfff970/d .functor AND 1, L_0xfff4c0, L_0xfffc50, C4<1>, C4<1>; +L_0xfff970 .delay (20000,20000,20000) L_0xfff970/d; +L_0xfffa80/d .functor OR 1, L_0xfff860, L_0xfff970, C4<0>, C4<0>; +L_0xfffa80 .delay (20000,20000,20000) L_0xfffa80/d; +v0xff77a0_0 .net "S", 0 0, L_0xfffc50; 1 drivers +v0xff7820_0 .alias "in0", 0 0, v0xff7e80_0; +v0xff78c0_0 .alias "in1", 0 0, v0xff8370_0; +v0xff7960_0 .net "nS", 0 0, L_0xfff7e0; 1 drivers +v0xff79e0_0 .net "out0", 0 0, L_0xfff860; 1 drivers +v0xff7a80_0 .net "out1", 0 0, L_0xfff970; 1 drivers +v0xff7b60_0 .alias "outfinal", 0 0, v0xff7f00_0; +S_0xfeeba0 .scope module, "test2" "SLT32" 2 149, 3 208, S_0xeed190; + .timescale -9 -12; +P_0xfeec98 .param/l "size" 3 238, +C4<0100>; +L_0x10062c0/d .functor NOT 1, L_0x10091e0, C4<0>, C4<0>, C4<0>; +L_0x10062c0 .delay (10000,10000,10000) L_0x10062c0/d; +L_0x1009040/d .functor AND 1, L_0x10093f0, L_0xff2230, L_0x10062c0, C4<1>; +L_0x1009040 .delay (20000,20000,20000) L_0x1009040/d; +L_0x100adb0/d .functor OR 1, L_0x100ae10, C4<0>, C4<0>, C4<0>; +L_0x100adb0 .delay (20000,20000,20000) L_0x100adb0/d; +L_0x100b770/d .functor XOR 1, RS_0x7f9963cefd08, L_0x100b860, C4<0>, C4<0>; +L_0x100b770 .delay (40000,40000,40000) L_0x100b770/d; +L_0x100b3e0/d .functor NOT 1, RS_0x7f9963cefd38, C4<0>, C4<0>, C4<0>; +L_0x100b3e0 .delay (10000,10000,10000) L_0x100b3e0/d; +L_0x100ba80/d .functor NOT 1, L_0x100bb60, C4<0>, C4<0>, C4<0>; +L_0x100ba80 .delay (10000,10000,10000) L_0x100ba80/d; +L_0x100bc00/d .functor AND 1, L_0x100b3e0, L_0x100bd40, C4<1>, C4<1>; +L_0x100bc00 .delay (20000,20000,20000) L_0x100bc00/d; +L_0x100b900/d .functor AND 1, RS_0x7f9963cefd38, L_0x100ba80, C4<1>, C4<1>; +L_0x100b900 .delay (20000,20000,20000) L_0x100b900/d; +L_0x100bf70/d .functor AND 1, L_0x100bc00, L_0x1009040, C4<1>, C4<1>; +L_0x100bf70 .delay (20000,20000,20000) L_0x100bf70/d; +L_0x100c070/d .functor AND 1, L_0x100b900, L_0x1009040, C4<1>, C4<1>; +L_0x100c070 .delay (20000,20000,20000) L_0x100c070/d; +L_0x100c180/d .functor OR 1, L_0x100bf70, L_0x100c070, C4<0>, C4<0>; +L_0x100c180 .delay (20000,20000,20000) L_0x100c180/d; +v0xff60c0_0 .alias "A", 3 0, v0xffb8e0_0; +RS_0x7f9963cf4478 .resolv tri, L_0x1003f40, L_0x1006220, L_0x10087b0, L_0x100b140; +v0xff6160_0 .net8 "AddSubSLTSum", 3 0, RS_0x7f9963cf4478; 4 drivers +v0xff6200_0 .alias "B", 3 0, v0xffba90_0; +RS_0x7f9963cf44a8 .resolv tri, L_0x1003670, L_0x10059d0, L_0x1007c60, L_0x100a8f0; +v0xff6280_0 .net8 "CarryoutWire", 3 0, RS_0x7f9963cf44a8; 4 drivers +v0xff6330_0 .alias "Command", 2 0, v0xffbc20_0; +RS_0x7f9963cf44d8 .resolv tri, L_0x1003580, L_0x10058e0, L_0x1007b70, L_0x100a800; +v0xff63b0_0 .net8 "NewVal", 3 0, RS_0x7f9963cf44d8; 4 drivers +v0xff6450_0 .net "Res0OF1", 0 0, L_0x100b900; 1 drivers +v0xff64f0_0 .net "Res1OF0", 0 0, L_0x100bc00; 1 drivers +v0xff6590_0 .alias "SLTSum", 3 0, v0xffc760_0; +v0xff6660_0 .alias "SLTflag", 0 0, v0xffc8f0_0; +v0xff66e0_0 .net "SLTflag0", 0 0, L_0x100bf70; 1 drivers +v0xff6780_0 .net "SLTflag1", 0 0, L_0x100c070; 1 drivers +v0xff6820_0 .net "SLTon", 0 0, L_0x1009040; 1 drivers +v0xff68a0_0 .net *"_s49", 0 0, L_0x10091e0; 1 drivers +v0xff69c0_0 .net *"_s51", 0 0, L_0x10093f0; 1 drivers +v0xff6a60_0 .net *"_s53", 0 0, L_0xff2230; 1 drivers +v0xff6920_0 .net *"_s73", 0 0, L_0x100ae10; 1 drivers +v0xff6bb0_0 .net/s *"_s74", 0 0, C4<0>; 1 drivers +v0xff6cd0_0 .net *"_s77", 0 0, L_0x100b860; 1 drivers +v0xff6d50_0 .net *"_s79", 0 0, L_0x100bb60; 1 drivers +v0xff6c30_0 .net *"_s81", 0 0, L_0x100bd40; 1 drivers +v0xff6e80_0 .alias "carryin", 3 0, v0xffbed0_0; +v0xff6dd0_0 .alias "carryout", 0 0, v0xffcb10_0; +v0xff6fc0_0 .net "nAddSubSLTSum", 0 0, L_0x100ba80; 1 drivers +v0xff6f00_0 .net "nCmd2", 0 0, L_0x10062c0; 1 drivers +v0xff7110_0 .net "nOF", 0 0, L_0x100b3e0; 1 drivers +v0xff7040_0 .alias "overflow", 0 0, v0xffcc10_0; +v0xff7270_0 .alias "subtract", 3 0, v0xffcc90_0; +L_0x1003580 .part/pv L_0x10030d0, 1, 1, 4; +L_0x1003670 .part/pv L_0x1003420, 1, 1, 4; +L_0x1003760 .part/pv L_0x1002e00, 1, 1, 4; +L_0x1003850 .part v0xffc310_0, 1, 1; +L_0x10038f0 .part v0xffc560_0, 1, 1; +L_0x1003a20 .part RS_0x7f9963cf44a8, 0, 1; +L_0x1003f40 .part/pv L_0x1003e00, 1, 1, 4; +L_0x1003fe0 .part RS_0x7f9963cf44d8, 1, 1; +L_0x10045c0 .part/pv L_0x1004460, 1, 1, 4; +L_0x10046f0 .part RS_0x7f9963cf4478, 1, 1; +L_0x1004840 .part RS_0x7f9963cf4478, 1, 1; +L_0x10058e0 .part/pv L_0x1005430, 2, 1, 4; +L_0x10059d0 .part/pv L_0x1005780, 2, 1, 4; +L_0x1005ac0 .part/pv L_0x1005160, 2, 1, 4; +L_0x1005bb0 .part v0xffc310_0, 2, 1; +L_0x1005c50 .part v0xffc560_0, 2, 1; +L_0x1005e10 .part RS_0x7f9963cf44a8, 1, 1; +L_0x1006220 .part/pv L_0x10060e0, 2, 1, 4; +L_0x10063f0 .part RS_0x7f9963cf44d8, 2, 1; +L_0x10068d0 .part/pv L_0x1006790, 2, 1, 4; +L_0x1006350 .part RS_0x7f9963cf4478, 2, 1; +L_0x1006a70 .part RS_0x7f9963cf4478, 2, 1; +L_0x1007b70 .part/pv L_0x10076c0, 3, 1, 4; +L_0x1007c60 .part/pv L_0x1007a10, 3, 1, 4; +L_0x1006b60 .part/pv L_0x10073f0, 3, 1, 4; +L_0x1007e70 .part v0xffc310_0, 3, 1; +L_0x1007d50 .part v0xffc560_0, 3, 1; +L_0xffbb10 .part RS_0x7f9963cf44a8, 2, 1; +L_0x10087b0 .part/pv L_0x1008670, 3, 1, 4; +L_0x1008850 .part RS_0x7f9963cf44d8, 3, 1; +L_0x1008da0 .part/pv L_0x1008c60, 3, 1, 4; +L_0x1008e40 .part RS_0x7f9963cf4478, 3, 1; +L_0x1008940 .part RS_0x7f9963cf4478, 3, 1; +L_0x10091e0 .part v0xffc5e0_0, 2, 1; +L_0x10093f0 .part v0xffc5e0_0, 0, 1; +L_0xff2230 .part v0xffc5e0_0, 1, 1; +L_0x100a800 .part/pv L_0x100a370, 0, 1, 4; +L_0x100a8f0 .part/pv L_0x100a6c0, 0, 1, 4; +L_0xff2320 .part/pv L_0x100a0a0, 0, 1, 4; +L_0x100ab20 .part v0xffc310_0, 0, 1; +L_0x100a9e0 .part v0xffc560_0, 0, 1; +L_0x100ad10 .part RS_0x7f9963cefd68, 0, 1; +L_0x100b140 .part/pv L_0x100b000, 0, 1, 4; +L_0x100b1e0 .part RS_0x7f9963cf44d8, 0, 1; +L_0x100ae10 .part RS_0x7f9963cf44a8, 3, 1; +L_0x100b860 .part RS_0x7f9963cf44a8, 2, 1; +L_0x100bb60 .part RS_0x7f9963cf4478, 3, 1; +L_0x100bd40 .part RS_0x7f9963cf44d8, 3, 1; +L_0x100c6c0 .part/pv L_0x100c560, 0, 1, 4; +L_0x100c760 .part RS_0x7f9963cf4478, 0, 1; +S_0xff50a0 .scope module, "attempt2" "MiddleAddSubSLT" 3 234, 3 88, S_0xfeeba0; + .timescale -9 -12; +L_0xffc9f0/d .functor NOT 1, L_0x100a9e0, C4<0>, C4<0>, C4<0>; +L_0xffc9f0 .delay (10000,10000,10000) L_0xffc9f0/d; +L_0x1009f60/d .functor NOT 1, L_0x100a000, C4<0>, C4<0>, C4<0>; +L_0x1009f60 .delay (10000,10000,10000) L_0x1009f60/d; +L_0x100a0a0/d .functor AND 1, L_0x100a1e0, L_0x1009f60, C4<1>, C4<1>; +L_0x100a0a0 .delay (20000,20000,20000) L_0x100a0a0/d; +L_0x100a280/d .functor XOR 1, L_0x100ab20, L_0x1009d30, C4<0>, C4<0>; +L_0x100a280 .delay (40000,40000,40000) L_0x100a280/d; +L_0x100a370/d .functor XOR 1, L_0x100a280, L_0x100ad10, C4<0>, C4<0>; +L_0x100a370 .delay (40000,40000,40000) L_0x100a370/d; +L_0x100a460/d .functor AND 1, L_0x100ab20, L_0x1009d30, C4<1>, C4<1>; +L_0x100a460 .delay (20000,20000,20000) L_0x100a460/d; +L_0x100a5d0/d .functor AND 1, L_0x100a280, L_0x100ad10, C4<1>, C4<1>; +L_0x100a5d0 .delay (20000,20000,20000) L_0x100a5d0/d; +L_0x100a6c0/d .functor OR 1, L_0x100a460, L_0x100a5d0, C4<0>, C4<0>; +L_0x100a6c0 .delay (20000,20000,20000) L_0x100a6c0/d; +v0xff5720_0 .net "A", 0 0, L_0x100ab20; 1 drivers +v0xff57e0_0 .net "AandB", 0 0, L_0x100a460; 1 drivers +v0xff5880_0 .net "AddSubSLTSum", 0 0, L_0x100a370; 1 drivers +v0xff5920_0 .net "AxorB", 0 0, L_0x100a280; 1 drivers +v0xff59a0_0 .net "B", 0 0, L_0x100a9e0; 1 drivers +v0xff5a50_0 .net "BornB", 0 0, L_0x1009d30; 1 drivers +v0xff5b10_0 .net "CINandAxorB", 0 0, L_0x100a5d0; 1 drivers +v0xff5b90_0 .alias "Command", 2 0, v0xffbc20_0; +v0xff5c10_0 .net *"_s3", 0 0, L_0x100a000; 1 drivers +v0xff5c90_0 .net *"_s5", 0 0, L_0x100a1e0; 1 drivers +v0xff5d30_0 .net "carryin", 0 0, L_0x100ad10; 1 drivers +v0xff5dd0_0 .net "carryout", 0 0, L_0x100a6c0; 1 drivers +v0xff5e70_0 .net "nB", 0 0, L_0xffc9f0; 1 drivers +v0xff5f20_0 .net "nCmd2", 0 0, L_0x1009f60; 1 drivers +v0xff6020_0 .net "subtract", 0 0, L_0x100a0a0; 1 drivers +L_0x1009ec0 .part v0xffc5e0_0, 0, 1; +L_0x100a000 .part v0xffc5e0_0, 2, 1; +L_0x100a1e0 .part v0xffc5e0_0, 0, 1; +S_0xff5190 .scope module, "mux0" "TwoInMux" 3 104, 3 8, S_0xff50a0; + .timescale -9 -12; +L_0xff2450/d .functor NOT 1, L_0x1009ec0, C4<0>, C4<0>, C4<0>; +L_0xff2450 .delay (10000,10000,10000) L_0xff2450/d; +L_0xff24d0/d .functor AND 1, L_0x100a9e0, L_0xff2450, C4<1>, C4<1>; +L_0xff24d0 .delay (20000,20000,20000) L_0xff24d0/d; +L_0xff25e0/d .functor AND 1, L_0xffc9f0, L_0x1009ec0, C4<1>, C4<1>; +L_0xff25e0 .delay (20000,20000,20000) L_0xff25e0/d; +L_0x1009d30/d .functor OR 1, L_0xff24d0, L_0xff25e0, C4<0>, C4<0>; +L_0x1009d30 .delay (20000,20000,20000) L_0x1009d30/d; +v0xff5280_0 .net "S", 0 0, L_0x1009ec0; 1 drivers +v0xff5340_0 .alias "in0", 0 0, v0xff59a0_0; +v0xff53e0_0 .alias "in1", 0 0, v0xff5e70_0; +v0xff5480_0 .net "nS", 0 0, L_0xff2450; 1 drivers +v0xff5500_0 .net "out0", 0 0, L_0xff24d0; 1 drivers +v0xff55a0_0 .net "out1", 0 0, L_0xff25e0; 1 drivers +v0xff5680_0 .alias "outfinal", 0 0, v0xff5a50_0; +S_0xff4b30 .scope module, "setSLTresult" "TwoInMux" 3 235, 3 8, S_0xfeeba0; + .timescale -9 -12; +L_0x100abc0/d .functor NOT 1, L_0x1009040, C4<0>, C4<0>, C4<0>; +L_0x100abc0 .delay (10000,10000,10000) L_0x100abc0/d; +L_0x100ac60/d .functor AND 1, L_0x100b1e0, L_0x100abc0, C4<1>, C4<1>; +L_0x100ac60 .delay (20000,20000,20000) L_0x100ac60/d; +L_0x100af60/d .functor AND 1, C4<0>, L_0x1009040, C4<1>, C4<1>; +L_0x100af60 .delay (20000,20000,20000) L_0x100af60/d; +L_0x100b000/d .functor OR 1, L_0x100ac60, L_0x100af60, C4<0>, C4<0>; +L_0x100b000 .delay (20000,20000,20000) L_0x100b000/d; +v0xff4c20_0 .alias "S", 0 0, v0xff6820_0; +v0xff4cc0_0 .net "in0", 0 0, L_0x100b1e0; 1 drivers +v0xff4d60_0 .net "in1", 0 0, C4<0>; 1 drivers +v0xff4e00_0 .net "nS", 0 0, L_0x100abc0; 1 drivers +v0xff4e80_0 .net "out0", 0 0, L_0x100ac60; 1 drivers +v0xff4f20_0 .net "out1", 0 0, L_0x100af60; 1 drivers +v0xff5000_0 .net "outfinal", 0 0, L_0x100b000; 1 drivers +S_0xff45c0 .scope module, "FinalSLT" "TwoInMux" 3 261, 3 8, S_0xfeeba0; + .timescale -9 -12; +L_0x100c2d0/d .functor NOT 1, L_0x100c180, C4<0>, C4<0>, C4<0>; +L_0x100c2d0 .delay (10000,10000,10000) L_0x100c2d0/d; +L_0x100c3b0/d .functor AND 1, L_0x100c760, L_0x100c2d0, C4<1>, C4<1>; +L_0x100c3b0 .delay (20000,20000,20000) L_0x100c3b0/d; +L_0x100c4c0/d .functor AND 1, L_0x100c180, L_0x100c180, C4<1>, C4<1>; +L_0x100c4c0 .delay (20000,20000,20000) L_0x100c4c0/d; +L_0x100c560/d .functor OR 1, L_0x100c3b0, L_0x100c4c0, C4<0>, C4<0>; +L_0x100c560 .delay (20000,20000,20000) L_0x100c560/d; +v0xff46b0_0 .alias "S", 0 0, v0xffc8f0_0; +v0xff4770_0 .net "in0", 0 0, L_0x100c760; 1 drivers +v0xff4810_0 .alias "in1", 0 0, v0xffc8f0_0; +v0xff48c0_0 .net "nS", 0 0, L_0x100c2d0; 1 drivers +v0xff4970_0 .net "out0", 0 0, L_0x100c3b0; 1 drivers +v0xff49f0_0 .net "out1", 0 0, L_0x100c4c0; 1 drivers +v0xff4a90_0 .net "outfinal", 0 0, L_0x100c560; 1 drivers +S_0xff28c0 .scope generate, "sltbits[1]" "sltbits[1]" 3 240, 3 240, S_0xfeeba0; + .timescale -9 -12; +P_0xff29b8 .param/l "i" 3 240, +C4<01>; +S_0xff34b0 .scope module, "attempt" "MiddleAddSubSLT" 3 242, 3 88, S_0xff28c0; + .timescale -9 -12; +L_0x1002140/d .functor NOT 1, L_0x10038f0, C4<0>, C4<0>, C4<0>; +L_0x1002140 .delay (10000,10000,10000) L_0x1002140/d; +L_0x1002ca0/d .functor NOT 1, L_0x1002d60, C4<0>, C4<0>, C4<0>; +L_0x1002ca0 .delay (10000,10000,10000) L_0x1002ca0/d; +L_0x1002e00/d .functor AND 1, L_0x1002f40, L_0x1002ca0, C4<1>, C4<1>; +L_0x1002e00 .delay (20000,20000,20000) L_0x1002e00/d; +L_0x1002fe0/d .functor XOR 1, L_0x1003850, L_0x1002a30, C4<0>, C4<0>; +L_0x1002fe0 .delay (40000,40000,40000) L_0x1002fe0/d; +L_0x10030d0/d .functor XOR 1, L_0x1002fe0, L_0x1003a20, C4<0>, C4<0>; +L_0x10030d0 .delay (40000,40000,40000) L_0x10030d0/d; +L_0x10031c0/d .functor AND 1, L_0x1003850, L_0x1002a30, C4<1>, C4<1>; +L_0x10031c0 .delay (20000,20000,20000) L_0x10031c0/d; +L_0x1003330/d .functor AND 1, L_0x1002fe0, L_0x1003a20, C4<1>, C4<1>; +L_0x1003330 .delay (20000,20000,20000) L_0x1003330/d; +L_0x1003420/d .functor OR 1, L_0x10031c0, L_0x1003330, C4<0>, C4<0>; +L_0x1003420 .delay (20000,20000,20000) L_0x1003420/d; +v0xff3b30_0 .net "A", 0 0, L_0x1003850; 1 drivers +v0xff3bf0_0 .net "AandB", 0 0, L_0x10031c0; 1 drivers +v0xff3c90_0 .net "AddSubSLTSum", 0 0, L_0x10030d0; 1 drivers +v0xff3d30_0 .net "AxorB", 0 0, L_0x1002fe0; 1 drivers +v0xff3db0_0 .net "B", 0 0, L_0x10038f0; 1 drivers +v0xff3e30_0 .net "BornB", 0 0, L_0x1002a30; 1 drivers +v0xff3ef0_0 .net "CINandAxorB", 0 0, L_0x1003330; 1 drivers +v0xff3f70_0 .alias "Command", 2 0, v0xffbc20_0; +v0xff4040_0 .net *"_s3", 0 0, L_0x1002d60; 1 drivers +v0xff40c0_0 .net *"_s5", 0 0, L_0x1002f40; 1 drivers +v0xff41c0_0 .net "carryin", 0 0, L_0x1003a20; 1 drivers +v0xff4260_0 .net "carryout", 0 0, L_0x1003420; 1 drivers +v0xff4370_0 .net "nB", 0 0, L_0x1002140; 1 drivers +v0xff4420_0 .net "nCmd2", 0 0, L_0x1002ca0; 1 drivers +v0xff4520_0 .net "subtract", 0 0, L_0x1002e00; 1 drivers +L_0x1002c00 .part v0xffc5e0_0, 0, 1; +L_0x1002d60 .part v0xffc5e0_0, 2, 1; +L_0x1002f40 .part v0xffc5e0_0, 0, 1; +S_0xff35a0 .scope module, "mux0" "TwoInMux" 3 104, 3 8, S_0xff34b0; + .timescale -9 -12; +L_0x1002750/d .functor NOT 1, L_0x1002c00, C4<0>, C4<0>, C4<0>; +L_0x1002750 .delay (10000,10000,10000) L_0x1002750/d; +L_0x1002810/d .functor AND 1, L_0x10038f0, L_0x1002750, C4<1>, C4<1>; +L_0x1002810 .delay (20000,20000,20000) L_0x1002810/d; +L_0x1002920/d .functor AND 1, L_0x1002140, L_0x1002c00, C4<1>, C4<1>; +L_0x1002920 .delay (20000,20000,20000) L_0x1002920/d; +L_0x1002a30/d .functor OR 1, L_0x1002810, L_0x1002920, C4<0>, C4<0>; +L_0x1002a30 .delay (20000,20000,20000) L_0x1002a30/d; +v0xff3690_0 .net "S", 0 0, L_0x1002c00; 1 drivers +v0xff3730_0 .alias "in0", 0 0, v0xff3db0_0; +v0xff37d0_0 .alias "in1", 0 0, v0xff4370_0; +v0xff3870_0 .net "nS", 0 0, L_0x1002750; 1 drivers +v0xff3910_0 .net "out0", 0 0, L_0x1002810; 1 drivers +v0xff39b0_0 .net "out1", 0 0, L_0x1002920; 1 drivers +v0xff3a90_0 .alias "outfinal", 0 0, v0xff3e30_0; +S_0xff3040 .scope module, "setSLTres2" "TwoInMux" 3 243, 3 8, S_0xff28c0; + .timescale -9 -12; +L_0x1003ac0/d .functor NOT 1, L_0x1009040, C4<0>, C4<0>, C4<0>; +L_0x1003ac0 .delay (10000,10000,10000) L_0x1003ac0/d; +L_0x1003c30/d .functor AND 1, L_0x1003fe0, L_0x1003ac0, C4<1>, C4<1>; +L_0x1003c30 .delay (20000,20000,20000) L_0x1003c30/d; +L_0x1003d40/d .functor AND 1, C4<0>, L_0x1009040, C4<1>, C4<1>; +L_0x1003d40 .delay (20000,20000,20000) L_0x1003d40/d; +L_0x1003e00/d .functor OR 1, L_0x1003c30, L_0x1003d40, C4<0>, C4<0>; +L_0x1003e00 .delay (20000,20000,20000) L_0x1003e00/d; +v0xff3130_0 .alias "S", 0 0, v0xff6820_0; +v0xff31b0_0 .net "in0", 0 0, L_0x1003fe0; 1 drivers +v0xff3230_0 .net "in1", 0 0, C4<0>; 1 drivers +v0xff32b0_0 .net "nS", 0 0, L_0x1003ac0; 1 drivers +v0xff3330_0 .net "out0", 0 0, L_0x1003c30; 1 drivers +v0xff33b0_0 .net "out1", 0 0, L_0x1003d40; 1 drivers +v0xff3430_0 .net "outfinal", 0 0, L_0x1003e00; 1 drivers +S_0xff2a50 .scope module, "setSLTres3" "TwoInMux" 3 244, 3 8, S_0xff28c0; + .timescale -9 -12; +L_0x10041c0/d .functor NOT 1, L_0x1009040, C4<0>, C4<0>, C4<0>; +L_0x10041c0 .delay (10000,10000,10000) L_0x10041c0/d; +L_0x10042b0/d .functor AND 1, L_0x10046f0, L_0x10041c0, C4<1>, C4<1>; +L_0x10042b0 .delay (20000,20000,20000) L_0x10042b0/d; +L_0x10043c0/d .functor AND 1, L_0x1004840, L_0x1009040, C4<1>, C4<1>; +L_0x10043c0 .delay (20000,20000,20000) L_0x10043c0/d; +L_0x1004460/d .functor OR 1, L_0x10042b0, L_0x10043c0, C4<0>, C4<0>; +L_0x1004460 .delay (20000,20000,20000) L_0x1004460/d; +v0xff2b40_0 .alias "S", 0 0, v0xff6820_0; +v0xff2c50_0 .net "in0", 0 0, L_0x10046f0; 1 drivers +v0xff2cf0_0 .net "in1", 0 0, L_0x1004840; 1 drivers +v0xff2d90_0 .net "nS", 0 0, L_0x10041c0; 1 drivers +v0xff2e40_0 .net "out0", 0 0, L_0x10042b0; 1 drivers +v0xff2ee0_0 .net "out1", 0 0, L_0x10043c0; 1 drivers +v0xff2fc0_0 .net "outfinal", 0 0, L_0x1004460; 1 drivers +S_0xff0a40 .scope generate, "sltbits[2]" "sltbits[2]" 3 240, 3 240, S_0xfeeba0; + .timescale -9 -12; +P_0xff03a8 .param/l "i" 3 240, +C4<010>; +S_0xff1670 .scope module, "attempt" "MiddleAddSubSLT" 3 242, 3 88, S_0xff0a40; + .timescale -9 -12; +L_0x10048e0/d .functor NOT 1, L_0x1005c50, C4<0>, C4<0>, C4<0>; +L_0x10048e0 .delay (10000,10000,10000) L_0x10048e0/d; +L_0x1005000/d .functor NOT 1, L_0x10050c0, C4<0>, C4<0>, C4<0>; +L_0x1005000 .delay (10000,10000,10000) L_0x1005000/d; +L_0x1005160/d .functor AND 1, L_0x10052a0, L_0x1005000, C4<1>, C4<1>; +L_0x1005160 .delay (20000,20000,20000) L_0x1005160/d; +L_0x1005340/d .functor XOR 1, L_0x1005bb0, L_0x1004d90, C4<0>, C4<0>; +L_0x1005340 .delay (40000,40000,40000) L_0x1005340/d; +L_0x1005430/d .functor XOR 1, L_0x1005340, L_0x1005e10, C4<0>, C4<0>; +L_0x1005430 .delay (40000,40000,40000) L_0x1005430/d; +L_0x1005520/d .functor AND 1, L_0x1005bb0, L_0x1004d90, C4<1>, C4<1>; +L_0x1005520 .delay (20000,20000,20000) L_0x1005520/d; +L_0x1005690/d .functor AND 1, L_0x1005340, L_0x1005e10, C4<1>, C4<1>; +L_0x1005690 .delay (20000,20000,20000) L_0x1005690/d; +L_0x1005780/d .functor OR 1, L_0x1005520, L_0x1005690, C4<0>, C4<0>; +L_0x1005780 .delay (20000,20000,20000) L_0x1005780/d; +v0xff1cf0_0 .net "A", 0 0, L_0x1005bb0; 1 drivers +v0xff1db0_0 .net "AandB", 0 0, L_0x1005520; 1 drivers +v0xff1e50_0 .net "AddSubSLTSum", 0 0, L_0x1005430; 1 drivers +v0xff1ef0_0 .net "AxorB", 0 0, L_0x1005340; 1 drivers +v0xff1f70_0 .net "B", 0 0, L_0x1005c50; 1 drivers +v0xff2020_0 .net "BornB", 0 0, L_0x1004d90; 1 drivers +v0xff20e0_0 .net "CINandAxorB", 0 0, L_0x1005690; 1 drivers +v0xff2160_0 .alias "Command", 2 0, v0xffbc20_0; +v0xfe09a0_0 .net *"_s3", 0 0, L_0x10050c0; 1 drivers +v0xfe0a20_0 .net *"_s5", 0 0, L_0x10052a0; 1 drivers +v0xfe0ac0_0 .net "carryin", 0 0, L_0x1005e10; 1 drivers +v0xff2640_0 .net "carryout", 0 0, L_0x1005780; 1 drivers +v0xff26c0_0 .net "nB", 0 0, L_0x10048e0; 1 drivers +v0xff2740_0 .net "nCmd2", 0 0, L_0x1005000; 1 drivers +v0xff2840_0 .net "subtract", 0 0, L_0x1005160; 1 drivers +L_0x1004f60 .part v0xffc5e0_0, 0, 1; +L_0x10050c0 .part v0xffc5e0_0, 2, 1; +L_0x10052a0 .part v0xffc5e0_0, 0, 1; +S_0xff1760 .scope module, "mux0" "TwoInMux" 3 104, 3 8, S_0xff1670; + .timescale -9 -12; +L_0x1004ab0/d .functor NOT 1, L_0x1004f60, C4<0>, C4<0>, C4<0>; +L_0x1004ab0 .delay (10000,10000,10000) L_0x1004ab0/d; +L_0x1004b70/d .functor AND 1, L_0x1005c50, L_0x1004ab0, C4<1>, C4<1>; +L_0x1004b70 .delay (20000,20000,20000) L_0x1004b70/d; +L_0x1004c80/d .functor AND 1, L_0x10048e0, L_0x1004f60, C4<1>, C4<1>; +L_0x1004c80 .delay (20000,20000,20000) L_0x1004c80/d; +L_0x1004d90/d .functor OR 1, L_0x1004b70, L_0x1004c80, C4<0>, C4<0>; +L_0x1004d90 .delay (20000,20000,20000) L_0x1004d90/d; +v0xff1850_0 .net "S", 0 0, L_0x1004f60; 1 drivers +v0xff1910_0 .alias "in0", 0 0, v0xff1f70_0; +v0xff19b0_0 .alias "in1", 0 0, v0xff26c0_0; +v0xff1a50_0 .net "nS", 0 0, L_0x1004ab0; 1 drivers +v0xff1ad0_0 .net "out0", 0 0, L_0x1004b70; 1 drivers +v0xff1b70_0 .net "out1", 0 0, L_0x1004c80; 1 drivers +v0xff1c50_0 .alias "outfinal", 0 0, v0xff2020_0; +S_0xff1100 .scope module, "setSLTres2" "TwoInMux" 3 243, 3 8, S_0xff0a40; + .timescale -9 -12; +L_0x10047e0/d .functor NOT 1, L_0x1009040, C4<0>, C4<0>, C4<0>; +L_0x10047e0 .delay (10000,10000,10000) L_0x10047e0/d; +L_0x1005f80/d .functor AND 1, L_0x10063f0, L_0x10047e0, C4<1>, C4<1>; +L_0x1005f80 .delay (20000,20000,20000) L_0x1005f80/d; +L_0x1006040/d .functor AND 1, C4<0>, L_0x1009040, C4<1>, C4<1>; +L_0x1006040 .delay (20000,20000,20000) L_0x1006040/d; +L_0x10060e0/d .functor OR 1, L_0x1005f80, L_0x1006040, C4<0>, C4<0>; +L_0x10060e0 .delay (20000,20000,20000) L_0x10060e0/d; +v0xff11f0_0 .alias "S", 0 0, v0xff6820_0; +v0xff1290_0 .net "in0", 0 0, L_0x10063f0; 1 drivers +v0xff1330_0 .net "in1", 0 0, C4<0>; 1 drivers +v0xff13d0_0 .net "nS", 0 0, L_0x10047e0; 1 drivers +v0xff1450_0 .net "out0", 0 0, L_0x1005f80; 1 drivers +v0xff14f0_0 .net "out1", 0 0, L_0x1006040; 1 drivers +v0xff15d0_0 .net "outfinal", 0 0, L_0x10060e0; 1 drivers +S_0xff0bb0 .scope module, "setSLTres3" "TwoInMux" 3 244, 3 8, S_0xff0a40; + .timescale -9 -12; +L_0x10064d0/d .functor NOT 1, L_0x1009040, C4<0>, C4<0>, C4<0>; +L_0x10064d0 .delay (10000,10000,10000) L_0x10064d0/d; +L_0x10065e0/d .functor AND 1, L_0x1006350, L_0x10064d0, C4<1>, C4<1>; +L_0x10065e0 .delay (20000,20000,20000) L_0x10065e0/d; +L_0x10066f0/d .functor AND 1, L_0x1006a70, L_0x1009040, C4<1>, C4<1>; +L_0x10066f0 .delay (20000,20000,20000) L_0x10066f0/d; +L_0x1006790/d .functor OR 1, L_0x10065e0, L_0x10066f0, C4<0>, C4<0>; +L_0x1006790 .delay (20000,20000,20000) L_0x1006790/d; +v0xff0ca0_0 .alias "S", 0 0, v0xff6820_0; +v0xff0d20_0 .net "in0", 0 0, L_0x1006350; 1 drivers +v0xff0dc0_0 .net "in1", 0 0, L_0x1006a70; 1 drivers +v0xff0e60_0 .net "nS", 0 0, L_0x10064d0; 1 drivers +v0xff0ee0_0 .net "out0", 0 0, L_0x10065e0; 1 drivers +v0xff0f80_0 .net "out1", 0 0, L_0x10066f0; 1 drivers +v0xff1060_0 .net "outfinal", 0 0, L_0x1006790; 1 drivers +S_0xfeed10 .scope generate, "sltbits[3]" "sltbits[3]" 3 240, 3 240, S_0xfeeba0; + .timescale -9 -12; +P_0xfeee08 .param/l "i" 3 240, +C4<011>; +S_0xfef970 .scope module, "attempt" "MiddleAddSubSLT" 3 242, 3 88, S_0xfeed10; + .timescale -9 -12; +L_0x1006970/d .functor NOT 1, L_0x1007d50, C4<0>, C4<0>, C4<0>; +L_0x1006970 .delay (10000,10000,10000) L_0x1006970/d; +L_0x1007290/d .functor NOT 1, L_0x1007350, C4<0>, C4<0>, C4<0>; +L_0x1007290 .delay (10000,10000,10000) L_0x1007290/d; +L_0x10073f0/d .functor AND 1, L_0x1007530, L_0x1007290, C4<1>, C4<1>; +L_0x10073f0 .delay (20000,20000,20000) L_0x10073f0/d; +L_0x10075d0/d .functor XOR 1, L_0x1007e70, L_0x1007020, C4<0>, C4<0>; +L_0x10075d0 .delay (40000,40000,40000) L_0x10075d0/d; +L_0x10076c0/d .functor XOR 1, L_0x10075d0, L_0xffbb10, C4<0>, C4<0>; +L_0x10076c0 .delay (40000,40000,40000) L_0x10076c0/d; +L_0x10077b0/d .functor AND 1, L_0x1007e70, L_0x1007020, C4<1>, C4<1>; +L_0x10077b0 .delay (20000,20000,20000) L_0x10077b0/d; +L_0x1007920/d .functor AND 1, L_0x10075d0, L_0xffbb10, C4<1>, C4<1>; +L_0x1007920 .delay (20000,20000,20000) L_0x1007920/d; +L_0x1007a10/d .functor OR 1, L_0x10077b0, L_0x1007920, C4<0>, C4<0>; +L_0x1007a10 .delay (20000,20000,20000) L_0x1007a10/d; +v0xfefff0_0 .net "A", 0 0, L_0x1007e70; 1 drivers +v0xff00b0_0 .net "AandB", 0 0, L_0x10077b0; 1 drivers +v0xff0150_0 .net "AddSubSLTSum", 0 0, L_0x10076c0; 1 drivers +v0xff01f0_0 .net "AxorB", 0 0, L_0x10075d0; 1 drivers +v0xff0270_0 .net "B", 0 0, L_0x1007d50; 1 drivers +v0xff0320_0 .net "BornB", 0 0, L_0x1007020; 1 drivers +v0xff03e0_0 .net "CINandAxorB", 0 0, L_0x1007920; 1 drivers +v0xff0460_0 .alias "Command", 2 0, v0xffbc20_0; +v0xff0530_0 .net *"_s3", 0 0, L_0x1007350; 1 drivers +v0xff05b0_0 .net *"_s5", 0 0, L_0x1007530; 1 drivers +v0xff06b0_0 .net "carryin", 0 0, L_0xffbb10; 1 drivers +v0xff0750_0 .net "carryout", 0 0, L_0x1007a10; 1 drivers +v0xff07f0_0 .net "nB", 0 0, L_0x1006970; 1 drivers +v0xff08a0_0 .net "nCmd2", 0 0, L_0x1007290; 1 drivers +v0xff09a0_0 .net "subtract", 0 0, L_0x10073f0; 1 drivers +L_0x10071f0 .part v0xffc5e0_0, 0, 1; +L_0x1007350 .part v0xffc5e0_0, 2, 1; +L_0x1007530 .part v0xffc5e0_0, 0, 1; +S_0xfefa60 .scope module, "mux0" "TwoInMux" 3 104, 3 8, S_0xfef970; + .timescale -9 -12; +L_0x1006d40/d .functor NOT 1, L_0x10071f0, C4<0>, C4<0>, C4<0>; +L_0x1006d40 .delay (10000,10000,10000) L_0x1006d40/d; +L_0x1006e00/d .functor AND 1, L_0x1007d50, L_0x1006d40, C4<1>, C4<1>; +L_0x1006e00 .delay (20000,20000,20000) L_0x1006e00/d; +L_0x1006f10/d .functor AND 1, L_0x1006970, L_0x10071f0, C4<1>, C4<1>; +L_0x1006f10 .delay (20000,20000,20000) L_0x1006f10/d; +L_0x1007020/d .functor OR 1, L_0x1006e00, L_0x1006f10, C4<0>, C4<0>; +L_0x1007020 .delay (20000,20000,20000) L_0x1007020/d; +v0xfefb50_0 .net "S", 0 0, L_0x10071f0; 1 drivers +v0xfefc10_0 .alias "in0", 0 0, v0xff0270_0; +v0xfefcb0_0 .alias "in1", 0 0, v0xff07f0_0; +v0xfefd50_0 .net "nS", 0 0, L_0x1006d40; 1 drivers +v0xfefdd0_0 .net "out0", 0 0, L_0x1006e00; 1 drivers +v0xfefe70_0 .net "out1", 0 0, L_0x1006f10; 1 drivers +v0xfeff50_0 .alias "outfinal", 0 0, v0xff0320_0; +S_0xfef3f0 .scope module, "setSLTres2" "TwoInMux" 3 243, 3 8, S_0xfeed10; + .timescale -9 -12; +L_0xffbbb0/d .functor NOT 1, L_0x1009040, C4<0>, C4<0>, C4<0>; +L_0xffbbb0 .delay (10000,10000,10000) L_0xffbbb0/d; +L_0x1003b20/d .functor AND 1, L_0x1008850, L_0xffbbb0, C4<1>, C4<1>; +L_0x1003b20 .delay (20000,20000,20000) L_0x1003b20/d; +L_0x10085d0/d .functor AND 1, C4<0>, L_0x1009040, C4<1>, C4<1>; +L_0x10085d0 .delay (20000,20000,20000) L_0x10085d0/d; +L_0x1008670/d .functor OR 1, L_0x1003b20, L_0x10085d0, C4<0>, C4<0>; +L_0x1008670 .delay (20000,20000,20000) L_0x1008670/d; +v0xfef4e0_0 .alias "S", 0 0, v0xff6820_0; +v0xfef580_0 .net "in0", 0 0, L_0x1008850; 1 drivers +v0xfef600_0 .net "in1", 0 0, C4<0>; 1 drivers +v0xfef6a0_0 .net "nS", 0 0, L_0xffbbb0; 1 drivers +v0xfef750_0 .net "out0", 0 0, L_0x1003b20; 1 drivers +v0xfef7f0_0 .net "out1", 0 0, L_0x10085d0; 1 drivers +v0xfef8d0_0 .net "outfinal", 0 0, L_0x1008670; 1 drivers +S_0xfeee80 .scope module, "setSLTres3" "TwoInMux" 3 244, 3 8, S_0xfeed10; + .timescale -9 -12; +L_0xffba10/d .functor NOT 1, L_0x1009040, C4<0>, C4<0>, C4<0>; +L_0xffba10 .delay (10000,10000,10000) L_0xffba10/d; +L_0x1008ad0/d .functor AND 1, L_0x1008e40, L_0xffba10, C4<1>, C4<1>; +L_0x1008ad0 .delay (20000,20000,20000) L_0x1008ad0/d; +L_0x1008bc0/d .functor AND 1, L_0x1008940, L_0x1009040, C4<1>, C4<1>; +L_0x1008bc0 .delay (20000,20000,20000) L_0x1008bc0/d; +L_0x1008c60/d .functor OR 1, L_0x1008ad0, L_0x1008bc0, C4<0>, C4<0>; +L_0x1008c60 .delay (20000,20000,20000) L_0x1008c60/d; +v0xfeef70_0 .alias "S", 0 0, v0xff6820_0; +v0xfef010_0 .net "in0", 0 0, L_0x1008e40; 1 drivers +v0xfef0b0_0 .net "in1", 0 0, L_0x1008940; 1 drivers +v0xfef150_0 .net "nS", 0 0, L_0xffba10; 1 drivers +v0xfef1d0_0 .net "out0", 0 0, L_0x1008ad0; 1 drivers +v0xfef270_0 .net "out1", 0 0, L_0x1008bc0; 1 drivers +v0xfef350_0 .net "outfinal", 0 0, L_0x1008c60; 1 drivers +S_0xfeba90 .scope module, "trial1" "AndNand32" 2 151, 3 115, S_0xeed190; + .timescale -9 -12; +P_0xfeb5a8 .param/l "size" 3 122, +C4<0100>; +v0xfee950_0 .alias "A", 3 0, v0xffb8e0_0; +v0xfee9d0_0 .alias "AndNandOut", 3 0, v0xffc4b0_0; +v0xfeeaa0_0 .alias "B", 3 0, v0xffba90_0; +v0xfeeb20_0 .alias "Command", 2 0, v0xffbc20_0; +L_0x100d070 .part/pv L_0x100ce00, 1, 1, 4; +L_0x100d1c0 .part v0xffc310_0, 1, 1; +L_0x100d260 .part v0xffc560_0, 1, 1; +L_0x100db20 .part/pv L_0x100d8b0, 2, 1, 4; +L_0x100dbc0 .part v0xffc310_0, 2, 1; +L_0x100dc60 .part v0xffc560_0, 2, 1; +L_0x100e590 .part/pv L_0x100e320, 3, 1, 4; +L_0x100e630 .part v0xffc310_0, 3, 1; +L_0x100e720 .part v0xffc560_0, 3, 1; +L_0x100eff0 .part/pv L_0x100ed80, 0, 1, 4; +L_0x100f0f0 .part v0xffc310_0, 0, 1; +L_0x100f190 .part v0xffc560_0, 0, 1; +S_0xfedf20 .scope module, "attempt2" "AndNand" 3 126, 3 48, S_0xfeba90; + .timescale -9 -12; +L_0x100e810/d .functor NAND 1, L_0x100f0f0, L_0x100f190, C4<1>, C4<1>; +L_0x100e810 .delay (10000,10000,10000) L_0x100e810/d; +L_0x100e930/d .functor NOT 1, L_0x100e810, C4<0>, C4<0>, C4<0>; +L_0x100e930 .delay (10000,10000,10000) L_0x100e930/d; +v0xfee540_0 .net "A", 0 0, L_0x100f0f0; 1 drivers +v0xfee600_0 .net "AandB", 0 0, L_0x100e930; 1 drivers +v0xfee680_0 .net "AnandB", 0 0, L_0x100e810; 1 drivers +v0xfee730_0 .net "AndNandOut", 0 0, L_0x100ed80; 1 drivers +v0xfee810_0 .net "B", 0 0, L_0x100f190; 1 drivers +v0xfee890_0 .alias "Command", 2 0, v0xffbc20_0; +L_0x100ef50 .part v0xffc5e0_0, 0, 1; +S_0xfee010 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0xfedf20; + .timescale -9 -12; +L_0x100ea60/d .functor NOT 1, L_0x100ef50, C4<0>, C4<0>, C4<0>; +L_0x100ea60 .delay (10000,10000,10000) L_0x100ea60/d; +L_0x100eb20/d .functor AND 1, L_0x100e930, L_0x100ea60, C4<1>, C4<1>; +L_0x100eb20 .delay (20000,20000,20000) L_0x100eb20/d; +L_0x100ec30/d .functor AND 1, L_0x100e810, L_0x100ef50, C4<1>, C4<1>; +L_0x100ec30 .delay (20000,20000,20000) L_0x100ec30/d; +L_0x100ed80/d .functor OR 1, L_0x100eb20, L_0x100ec30, C4<0>, C4<0>; +L_0x100ed80 .delay (20000,20000,20000) L_0x100ed80/d; +v0xfee100_0 .net "S", 0 0, L_0x100ef50; 1 drivers +v0xfee180_0 .alias "in0", 0 0, v0xfee600_0; +v0xfee200_0 .alias "in1", 0 0, v0xfee680_0; +v0xfee2a0_0 .net "nS", 0 0, L_0x100ea60; 1 drivers +v0xfee320_0 .net "out0", 0 0, L_0x100eb20; 1 drivers +v0xfee3c0_0 .net "out1", 0 0, L_0x100ec30; 1 drivers +v0xfee4a0_0 .alias "outfinal", 0 0, v0xfee730_0; +S_0xfed360 .scope generate, "andbits[1]" "andbits[1]" 3 130, 3 130, S_0xfeba90; + .timescale -9 -12; +P_0xfed458 .param/l "i" 3 130, +C4<01>; +S_0xfed4d0 .scope module, "attempt" "AndNand" 3 132, 3 48, S_0xfed360; + .timescale -9 -12; +L_0x100bde0/d .functor NAND 1, L_0x100d1c0, L_0x100d260, C4<1>, C4<1>; +L_0x100bde0 .delay (10000,10000,10000) L_0x100bde0/d; +L_0x100c9f0/d .functor NOT 1, L_0x100bde0, C4<0>, C4<0>, C4<0>; +L_0x100c9f0 .delay (10000,10000,10000) L_0x100c9f0/d; +v0xfedb10_0 .net "A", 0 0, L_0x100d1c0; 1 drivers +v0xfedbd0_0 .net "AandB", 0 0, L_0x100c9f0; 1 drivers +v0xfedc50_0 .net "AnandB", 0 0, L_0x100bde0; 1 drivers +v0xfedd00_0 .net "AndNandOut", 0 0, L_0x100ce00; 1 drivers +v0xfedde0_0 .net "B", 0 0, L_0x100d260; 1 drivers +v0xfede60_0 .alias "Command", 2 0, v0xffbc20_0; +L_0x100cfd0 .part v0xffc5e0_0, 0, 1; +S_0xfed5c0 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0xfed4d0; + .timescale -9 -12; +L_0x100cae0/d .functor NOT 1, L_0x100cfd0, C4<0>, C4<0>, C4<0>; +L_0x100cae0 .delay (10000,10000,10000) L_0x100cae0/d; +L_0x100cba0/d .functor AND 1, L_0x100c9f0, L_0x100cae0, C4<1>, C4<1>; +L_0x100cba0 .delay (20000,20000,20000) L_0x100cba0/d; +L_0x100ccb0/d .functor AND 1, L_0x100bde0, L_0x100cfd0, C4<1>, C4<1>; +L_0x100ccb0 .delay (20000,20000,20000) L_0x100ccb0/d; +L_0x100ce00/d .functor OR 1, L_0x100cba0, L_0x100ccb0, C4<0>, C4<0>; +L_0x100ce00 .delay (20000,20000,20000) L_0x100ce00/d; +v0xfed6b0_0 .net "S", 0 0, L_0x100cfd0; 1 drivers +v0xfed730_0 .alias "in0", 0 0, v0xfedbd0_0; +v0xfed7d0_0 .alias "in1", 0 0, v0xfedc50_0; +v0xfed870_0 .net "nS", 0 0, L_0x100cae0; 1 drivers +v0xfed8f0_0 .net "out0", 0 0, L_0x100cba0; 1 drivers +v0xfed990_0 .net "out1", 0 0, L_0x100ccb0; 1 drivers +v0xfeda70_0 .alias "outfinal", 0 0, v0xfedd00_0; +S_0xfec7a0 .scope generate, "andbits[2]" "andbits[2]" 3 130, 3 130, S_0xfeba90; + .timescale -9 -12; +P_0xfec898 .param/l "i" 3 130, +C4<010>; +S_0xfec910 .scope module, "attempt" "AndNand" 3 132, 3 48, S_0xfec7a0; + .timescale -9 -12; +L_0x100d300/d .functor NAND 1, L_0x100dbc0, L_0x100dc60, C4<1>, C4<1>; +L_0x100d300 .delay (10000,10000,10000) L_0x100d300/d; +L_0x100d460/d .functor NOT 1, L_0x100d300, C4<0>, C4<0>, C4<0>; +L_0x100d460 .delay (10000,10000,10000) L_0x100d460/d; +v0xfecf50_0 .net "A", 0 0, L_0x100dbc0; 1 drivers +v0xfed010_0 .net "AandB", 0 0, L_0x100d460; 1 drivers +v0xfed090_0 .net "AnandB", 0 0, L_0x100d300; 1 drivers +v0xfed140_0 .net "AndNandOut", 0 0, L_0x100d8b0; 1 drivers +v0xfed220_0 .net "B", 0 0, L_0x100dc60; 1 drivers +v0xfed2a0_0 .alias "Command", 2 0, v0xffbc20_0; +L_0x100da80 .part v0xffc5e0_0, 0, 1; +S_0xfeca00 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0xfec910; + .timescale -9 -12; +L_0x100d590/d .functor NOT 1, L_0x100da80, C4<0>, C4<0>, C4<0>; +L_0x100d590 .delay (10000,10000,10000) L_0x100d590/d; +L_0x100d650/d .functor AND 1, L_0x100d460, L_0x100d590, C4<1>, C4<1>; +L_0x100d650 .delay (20000,20000,20000) L_0x100d650/d; +L_0x100d760/d .functor AND 1, L_0x100d300, L_0x100da80, C4<1>, C4<1>; +L_0x100d760 .delay (20000,20000,20000) L_0x100d760/d; +L_0x100d8b0/d .functor OR 1, L_0x100d650, L_0x100d760, C4<0>, C4<0>; +L_0x100d8b0 .delay (20000,20000,20000) L_0x100d8b0/d; +v0xfecaf0_0 .net "S", 0 0, L_0x100da80; 1 drivers +v0xfecb70_0 .alias "in0", 0 0, v0xfed010_0; +v0xfecc10_0 .alias "in1", 0 0, v0xfed090_0; +v0xfeccb0_0 .net "nS", 0 0, L_0x100d590; 1 drivers +v0xfecd30_0 .net "out0", 0 0, L_0x100d650; 1 drivers +v0xfecdd0_0 .net "out1", 0 0, L_0x100d760; 1 drivers +v0xfeceb0_0 .alias "outfinal", 0 0, v0xfed140_0; +S_0xfebbc0 .scope generate, "andbits[3]" "andbits[3]" 3 130, 3 130, S_0xfeba90; + .timescale -9 -12; +P_0xfebcb8 .param/l "i" 3 130, +C4<011>; +S_0xfebd30 .scope module, "attempt" "AndNand" 3 132, 3 48, S_0xfebbc0; + .timescale -9 -12; +L_0x100dd90/d .functor NAND 1, L_0x100e630, L_0x100e720, C4<1>, C4<1>; +L_0x100dd90 .delay (10000,10000,10000) L_0x100dd90/d; +L_0x100ded0/d .functor NOT 1, L_0x100dd90, C4<0>, C4<0>, C4<0>; +L_0x100ded0 .delay (10000,10000,10000) L_0x100ded0/d; +v0xfec390_0 .net "A", 0 0, L_0x100e630; 1 drivers +v0xfec450_0 .net "AandB", 0 0, L_0x100ded0; 1 drivers +v0xfec4d0_0 .net "AnandB", 0 0, L_0x100dd90; 1 drivers +v0xfec580_0 .net "AndNandOut", 0 0, L_0x100e320; 1 drivers +v0xfec660_0 .net "B", 0 0, L_0x100e720; 1 drivers +v0xfec6e0_0 .alias "Command", 2 0, v0xffbc20_0; +L_0x100e4f0 .part v0xffc5e0_0, 0, 1; +S_0xfebe20 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0xfebd30; + .timescale -9 -12; +L_0x100e000/d .functor NOT 1, L_0x100e4f0, C4<0>, C4<0>, C4<0>; +L_0x100e000 .delay (10000,10000,10000) L_0x100e000/d; +L_0x100e0c0/d .functor AND 1, L_0x100ded0, L_0x100e000, C4<1>, C4<1>; +L_0x100e0c0 .delay (20000,20000,20000) L_0x100e0c0/d; +L_0x100e1d0/d .functor AND 1, L_0x100dd90, L_0x100e4f0, C4<1>, C4<1>; +L_0x100e1d0 .delay (20000,20000,20000) L_0x100e1d0/d; +L_0x100e320/d .functor OR 1, L_0x100e0c0, L_0x100e1d0, C4<0>, C4<0>; +L_0x100e320 .delay (20000,20000,20000) L_0x100e320/d; +v0xfebf10_0 .net "S", 0 0, L_0x100e4f0; 1 drivers +v0xfebfb0_0 .alias "in0", 0 0, v0xfec450_0; +v0xfec050_0 .alias "in1", 0 0, v0xfec4d0_0; +v0xfec0f0_0 .net "nS", 0 0, L_0x100e000; 1 drivers +v0xfec170_0 .net "out0", 0 0, L_0x100e0c0; 1 drivers +v0xfec210_0 .net "out1", 0 0, L_0x100e1d0; 1 drivers +v0xfec2f0_0 .alias "outfinal", 0 0, v0xfec580_0; +S_0xfe6a60 .scope module, "trial2" "OrNorXor32" 2 153, 3 138, S_0xeed190; + .timescale -9 -12; +P_0xfe5608 .param/l "size" 3 145, +C4<0100>; +v0xfeb890_0 .alias "A", 3 0, v0xffb8e0_0; +v0xfeb910_0 .alias "B", 3 0, v0xffba90_0; +v0xfeb990_0 .alias "Command", 2 0, v0xffbc20_0; +v0xfeba10_0 .alias "OrNorXorOut", 3 0, v0xffc6e0_0; +L_0x10103b0 .part/pv L_0x1010140, 1, 1, 4; +L_0x10104e0 .part v0xffc310_0, 1, 1; +L_0x1010580 .part v0xffc560_0, 1, 1; +L_0x10116f0 .part/pv L_0x1011480, 2, 1, 4; +L_0x1011790 .part v0xffc310_0, 2, 1; +L_0x1011830 .part v0xffc560_0, 2, 1; +L_0x10129f0 .part/pv L_0x1012780, 3, 1, 4; +L_0x1012a90 .part v0xffc310_0, 3, 1; +L_0x1012b30 .part v0xffc560_0, 3, 1; +L_0x1013ce0 .part/pv L_0x1013a70, 0, 1, 4; +L_0x1013de0 .part v0xffc310_0, 0, 1; +L_0x1013e80 .part v0xffc560_0, 0, 1; +S_0xfea650 .scope module, "attempt2" "OrNorXor" 3 153, 3 64, S_0xfe6a60; + .timescale -9 -12; +L_0x1012bd0/d .functor NOR 1, L_0x1013de0, L_0x1013e80, C4<0>, C4<0>; +L_0x1012bd0 .delay (10000,10000,10000) L_0x1012bd0/d; +L_0x1012cd0/d .functor NOT 1, L_0x1012bd0, C4<0>, C4<0>, C4<0>; +L_0x1012cd0 .delay (10000,10000,10000) L_0x1012cd0/d; +L_0x1012e00/d .functor NAND 1, L_0x1013de0, L_0x1013e80, C4<1>, C4<1>; +L_0x1012e00 .delay (10000,10000,10000) L_0x1012e00/d; +L_0x1012f60/d .functor NAND 1, L_0x1012e00, L_0x1012cd0, C4<1>, C4<1>; +L_0x1012f60 .delay (10000,10000,10000) L_0x1012f60/d; +L_0x1013070/d .functor NOT 1, L_0x1012f60, C4<0>, C4<0>, C4<0>; +L_0x1013070 .delay (10000,10000,10000) L_0x1013070/d; +v0xfeb1a0_0 .net "A", 0 0, L_0x1013de0; 1 drivers +v0xfeb240_0 .net "AnandB", 0 0, L_0x1012e00; 1 drivers +v0xfeb2e0_0 .net "AnorB", 0 0, L_0x1012bd0; 1 drivers +v0xfeb390_0 .net "AorB", 0 0, L_0x1012cd0; 1 drivers +v0xfeb470_0 .net "AxorB", 0 0, L_0x1013070; 1 drivers +v0xfeb520_0 .net "B", 0 0, L_0x1013e80; 1 drivers +v0xfeb5e0_0 .alias "Command", 2 0, v0xffbc20_0; +v0xfeb660_0 .net "OrNorXorOut", 0 0, L_0x1013a70; 1 drivers +v0xfeb6e0_0 .net "XorNor", 0 0, L_0x10134f0; 1 drivers +v0xfeb7b0_0 .net "nXor", 0 0, L_0x1012f60; 1 drivers +L_0x1013670 .part v0xffc5e0_0, 2, 1; +L_0x1013c40 .part v0xffc5e0_0, 0, 1; +S_0xfeac30 .scope module, "mux0" "TwoInMux" 3 83, 3 8, S_0xfea650; + .timescale -9 -12; +L_0x10131d0/d .functor NOT 1, L_0x1013670, C4<0>, C4<0>, C4<0>; +L_0x10131d0 .delay (10000,10000,10000) L_0x10131d0/d; +L_0x1013290/d .functor AND 1, L_0x1013070, L_0x10131d0, C4<1>, C4<1>; +L_0x1013290 .delay (20000,20000,20000) L_0x1013290/d; +L_0x10133a0/d .functor AND 1, L_0x1012bd0, L_0x1013670, C4<1>, C4<1>; +L_0x10133a0 .delay (20000,20000,20000) L_0x10133a0/d; +L_0x10134f0/d .functor OR 1, L_0x1013290, L_0x10133a0, C4<0>, C4<0>; +L_0x10134f0 .delay (20000,20000,20000) L_0x10134f0/d; +v0xfead20_0 .net "S", 0 0, L_0x1013670; 1 drivers +v0xfeade0_0 .alias "in0", 0 0, v0xfeb470_0; +v0xfeae80_0 .alias "in1", 0 0, v0xfeb2e0_0; +v0xfeaf20_0 .net "nS", 0 0, L_0x10131d0; 1 drivers +v0xfeafa0_0 .net "out0", 0 0, L_0x1013290; 1 drivers +v0xfeb040_0 .net "out1", 0 0, L_0x10133a0; 1 drivers +v0xfeb120_0 .alias "outfinal", 0 0, v0xfeb6e0_0; +S_0xfea740 .scope module, "mux1" "TwoInMux" 3 84, 3 8, S_0xfea650; + .timescale -9 -12; +L_0x1013710/d .functor NOT 1, L_0x1013c40, C4<0>, C4<0>, C4<0>; +L_0x1013710 .delay (10000,10000,10000) L_0x1013710/d; +L_0x10137d0/d .functor AND 1, L_0x10134f0, L_0x1013710, C4<1>, C4<1>; +L_0x10137d0 .delay (20000,20000,20000) L_0x10137d0/d; +L_0x1013920/d .functor AND 1, L_0x1012cd0, L_0x1013c40, C4<1>, C4<1>; +L_0x1013920 .delay (20000,20000,20000) L_0x1013920/d; +L_0x1013a70/d .functor OR 1, L_0x10137d0, L_0x1013920, C4<0>, C4<0>; +L_0x1013a70 .delay (20000,20000,20000) L_0x1013a70/d; +v0xfea830_0 .net "S", 0 0, L_0x1013c40; 1 drivers +v0xfea8b0_0 .alias "in0", 0 0, v0xfeb6e0_0; +v0xfea930_0 .alias "in1", 0 0, v0xfeb390_0; +v0xfea9d0_0 .net "nS", 0 0, L_0x1013710; 1 drivers +v0xfeaa50_0 .net "out0", 0 0, L_0x10137d0; 1 drivers +v0xfeaaf0_0 .net "out1", 0 0, L_0x1013920; 1 drivers +v0xfeab90_0 .alias "outfinal", 0 0, v0xfeb660_0; +S_0xfe9280 .scope generate, "orbits[1]" "orbits[1]" 3 157, 3 157, S_0xfe6a60; + .timescale -9 -12; +P_0xfe8f98 .param/l "i" 3 157, +C4<01>; +S_0xfe93b0 .scope module, "attempt" "OrNorXor" 3 159, 3 64, S_0xfe9280; + .timescale -9 -12; +L_0x100f090/d .functor NOR 1, L_0x10104e0, L_0x1010580, C4<0>, C4<0>; +L_0x100f090 .delay (10000,10000,10000) L_0x100f090/d; +L_0x100f3a0/d .functor NOT 1, L_0x100f090, C4<0>, C4<0>, C4<0>; +L_0x100f3a0 .delay (10000,10000,10000) L_0x100f3a0/d; +L_0x100f4d0/d .functor NAND 1, L_0x10104e0, L_0x1010580, C4<1>, C4<1>; +L_0x100f4d0 .delay (10000,10000,10000) L_0x100f4d0/d; +L_0x100f630/d .functor NAND 1, L_0x100f4d0, L_0x100f3a0, C4<1>, C4<1>; +L_0x100f630 .delay (10000,10000,10000) L_0x100f630/d; +L_0x100f740/d .functor NOT 1, L_0x100f630, C4<0>, C4<0>, C4<0>; +L_0x100f740 .delay (10000,10000,10000) L_0x100f740/d; +v0xfe9f60_0 .net "A", 0 0, L_0x10104e0; 1 drivers +v0xfea000_0 .net "AnandB", 0 0, L_0x100f4d0; 1 drivers +v0xfea0a0_0 .net "AnorB", 0 0, L_0x100f090; 1 drivers +v0xfea150_0 .net "AorB", 0 0, L_0x100f3a0; 1 drivers +v0xfea230_0 .net "AxorB", 0 0, L_0x100f740; 1 drivers +v0xfea2e0_0 .net "B", 0 0, L_0x1010580; 1 drivers +v0xfea3a0_0 .alias "Command", 2 0, v0xffbc20_0; +v0xfea420_0 .net "OrNorXorOut", 0 0, L_0x1010140; 1 drivers +v0xfea4a0_0 .net "XorNor", 0 0, L_0x100fbc0; 1 drivers +v0xfea570_0 .net "nXor", 0 0, L_0x100f630; 1 drivers +L_0x100fd40 .part v0xffc5e0_0, 2, 1; +L_0x1010310 .part v0xffc5e0_0, 0, 1; +S_0xfe99f0 .scope module, "mux0" "TwoInMux" 3 83, 3 8, S_0xfe93b0; + .timescale -9 -12; +L_0x100f8a0/d .functor NOT 1, L_0x100fd40, C4<0>, C4<0>, C4<0>; +L_0x100f8a0 .delay (10000,10000,10000) L_0x100f8a0/d; +L_0x100f960/d .functor AND 1, L_0x100f740, L_0x100f8a0, C4<1>, C4<1>; +L_0x100f960 .delay (20000,20000,20000) L_0x100f960/d; +L_0x100fa70/d .functor AND 1, L_0x100f090, L_0x100fd40, C4<1>, C4<1>; +L_0x100fa70 .delay (20000,20000,20000) L_0x100fa70/d; +L_0x100fbc0/d .functor OR 1, L_0x100f960, L_0x100fa70, C4<0>, C4<0>; +L_0x100fbc0 .delay (20000,20000,20000) L_0x100fbc0/d; +v0xfe9ae0_0 .net "S", 0 0, L_0x100fd40; 1 drivers +v0xfe9ba0_0 .alias "in0", 0 0, v0xfea230_0; +v0xfe9c40_0 .alias "in1", 0 0, v0xfea0a0_0; +v0xfe9ce0_0 .net "nS", 0 0, L_0x100f8a0; 1 drivers +v0xfe9d60_0 .net "out0", 0 0, L_0x100f960; 1 drivers +v0xfe9e00_0 .net "out1", 0 0, L_0x100fa70; 1 drivers +v0xfe9ee0_0 .alias "outfinal", 0 0, v0xfea4a0_0; +S_0xfe94a0 .scope module, "mux1" "TwoInMux" 3 84, 3 8, S_0xfe93b0; + .timescale -9 -12; +L_0x100fde0/d .functor NOT 1, L_0x1010310, C4<0>, C4<0>, C4<0>; +L_0x100fde0 .delay (10000,10000,10000) L_0x100fde0/d; +L_0x100fea0/d .functor AND 1, L_0x100fbc0, L_0x100fde0, C4<1>, C4<1>; +L_0x100fea0 .delay (20000,20000,20000) L_0x100fea0/d; +L_0x100fff0/d .functor AND 1, L_0x100f3a0, L_0x1010310, C4<1>, C4<1>; +L_0x100fff0 .delay (20000,20000,20000) L_0x100fff0/d; +L_0x1010140/d .functor OR 1, L_0x100fea0, L_0x100fff0, C4<0>, C4<0>; +L_0x1010140 .delay (20000,20000,20000) L_0x1010140/d; +v0xfe9590_0 .net "S", 0 0, L_0x1010310; 1 drivers +v0xfe9610_0 .alias "in0", 0 0, v0xfea4a0_0; +v0xfe96b0_0 .alias "in1", 0 0, v0xfea150_0; +v0xfe9750_0 .net "nS", 0 0, L_0x100fde0; 1 drivers +v0xfe97d0_0 .net "out0", 0 0, L_0x100fea0; 1 drivers +v0xfe9870_0 .net "out1", 0 0, L_0x100fff0; 1 drivers +v0xfe9950_0 .alias "outfinal", 0 0, v0xfea420_0; +S_0xfe7eb0 .scope generate, "orbits[2]" "orbits[2]" 3 157, 3 157, S_0xfe6a60; + .timescale -9 -12; +P_0xfe7bd8 .param/l "i" 3 157, +C4<010>; +S_0xfe7fe0 .scope module, "attempt" "OrNorXor" 3 159, 3 64, S_0xfe7eb0; + .timescale -9 -12; +L_0x1010620/d .functor NOR 1, L_0x1011790, L_0x1011830, C4<0>, C4<0>; +L_0x1010620 .delay (10000,10000,10000) L_0x1010620/d; +L_0x10106e0/d .functor NOT 1, L_0x1010620, C4<0>, C4<0>, C4<0>; +L_0x10106e0 .delay (10000,10000,10000) L_0x10106e0/d; +L_0x1010810/d .functor NAND 1, L_0x1011790, L_0x1011830, C4<1>, C4<1>; +L_0x1010810 .delay (10000,10000,10000) L_0x1010810/d; +L_0x1010970/d .functor NAND 1, L_0x1010810, L_0x10106e0, C4<1>, C4<1>; +L_0x1010970 .delay (10000,10000,10000) L_0x1010970/d; +L_0x1010a80/d .functor NOT 1, L_0x1010970, C4<0>, C4<0>, C4<0>; +L_0x1010a80 .delay (10000,10000,10000) L_0x1010a80/d; +v0xfe8b90_0 .net "A", 0 0, L_0x1011790; 1 drivers +v0xfe8c30_0 .net "AnandB", 0 0, L_0x1010810; 1 drivers +v0xfe8cd0_0 .net "AnorB", 0 0, L_0x1010620; 1 drivers +v0xfe8d80_0 .net "AorB", 0 0, L_0x10106e0; 1 drivers +v0xfe8e60_0 .net "AxorB", 0 0, L_0x1010a80; 1 drivers +v0xfe8f10_0 .net "B", 0 0, L_0x1011830; 1 drivers +v0xfe8fd0_0 .alias "Command", 2 0, v0xffbc20_0; +v0xfe9050_0 .net "OrNorXorOut", 0 0, L_0x1011480; 1 drivers +v0xfe90d0_0 .net "XorNor", 0 0, L_0x1010f00; 1 drivers +v0xfe91a0_0 .net "nXor", 0 0, L_0x1010970; 1 drivers +L_0x1011080 .part v0xffc5e0_0, 2, 1; +L_0x1011650 .part v0xffc5e0_0, 0, 1; +S_0xfe8620 .scope module, "mux0" "TwoInMux" 3 83, 3 8, S_0xfe7fe0; + .timescale -9 -12; +L_0x1010be0/d .functor NOT 1, L_0x1011080, C4<0>, C4<0>, C4<0>; +L_0x1010be0 .delay (10000,10000,10000) L_0x1010be0/d; +L_0x1010ca0/d .functor AND 1, L_0x1010a80, L_0x1010be0, C4<1>, C4<1>; +L_0x1010ca0 .delay (20000,20000,20000) L_0x1010ca0/d; +L_0x1010db0/d .functor AND 1, L_0x1010620, L_0x1011080, C4<1>, C4<1>; +L_0x1010db0 .delay (20000,20000,20000) L_0x1010db0/d; +L_0x1010f00/d .functor OR 1, L_0x1010ca0, L_0x1010db0, C4<0>, C4<0>; +L_0x1010f00 .delay (20000,20000,20000) L_0x1010f00/d; +v0xfe8710_0 .net "S", 0 0, L_0x1011080; 1 drivers +v0xfe87d0_0 .alias "in0", 0 0, v0xfe8e60_0; +v0xfe8870_0 .alias "in1", 0 0, v0xfe8cd0_0; +v0xfe8910_0 .net "nS", 0 0, L_0x1010be0; 1 drivers +v0xfe8990_0 .net "out0", 0 0, L_0x1010ca0; 1 drivers +v0xfe8a30_0 .net "out1", 0 0, L_0x1010db0; 1 drivers +v0xfe8b10_0 .alias "outfinal", 0 0, v0xfe90d0_0; +S_0xfe80d0 .scope module, "mux1" "TwoInMux" 3 84, 3 8, S_0xfe7fe0; + .timescale -9 -12; +L_0x1011120/d .functor NOT 1, L_0x1011650, C4<0>, C4<0>, C4<0>; +L_0x1011120 .delay (10000,10000,10000) L_0x1011120/d; +L_0x10111e0/d .functor AND 1, L_0x1010f00, L_0x1011120, C4<1>, C4<1>; +L_0x10111e0 .delay (20000,20000,20000) L_0x10111e0/d; +L_0x1011330/d .functor AND 1, L_0x10106e0, L_0x1011650, C4<1>, C4<1>; +L_0x1011330 .delay (20000,20000,20000) L_0x1011330/d; +L_0x1011480/d .functor OR 1, L_0x10111e0, L_0x1011330, C4<0>, C4<0>; +L_0x1011480 .delay (20000,20000,20000) L_0x1011480/d; +v0xfe81c0_0 .net "S", 0 0, L_0x1011650; 1 drivers +v0xfe8240_0 .alias "in0", 0 0, v0xfe90d0_0; +v0xfe82e0_0 .alias "in1", 0 0, v0xfe8d80_0; +v0xfe8380_0 .net "nS", 0 0, L_0x1011120; 1 drivers +v0xfe8400_0 .net "out0", 0 0, L_0x10111e0; 1 drivers +v0xfe84a0_0 .net "out1", 0 0, L_0x1011330; 1 drivers +v0xfe8580_0 .alias "outfinal", 0 0, v0xfe9050_0; +S_0xfe6b50 .scope generate, "orbits[3]" "orbits[3]" 3 157, 3 157, S_0xfe6a60; + .timescale -9 -12; +P_0xfe6828 .param/l "i" 3 157, +C4<011>; +S_0xfe6ca0 .scope module, "attempt" "OrNorXor" 3 159, 3 64, S_0xfe6b50; + .timescale -9 -12; +L_0x1011910/d .functor NOR 1, L_0x1012a90, L_0x1012b30, C4<0>, C4<0>; +L_0x1011910 .delay (10000,10000,10000) L_0x1011910/d; +L_0x1011a00/d .functor NOT 1, L_0x1011910, C4<0>, C4<0>, C4<0>; +L_0x1011a00 .delay (10000,10000,10000) L_0x1011a00/d; +L_0x1011b10/d .functor NAND 1, L_0x1012a90, L_0x1012b30, C4<1>, C4<1>; +L_0x1011b10 .delay (10000,10000,10000) L_0x1011b10/d; +L_0x1011c70/d .functor NAND 1, L_0x1011b10, L_0x1011a00, C4<1>, C4<1>; +L_0x1011c70 .delay (10000,10000,10000) L_0x1011c70/d; +L_0x1011d80/d .functor NOT 1, L_0x1011c70, C4<0>, C4<0>, C4<0>; +L_0x1011d80 .delay (10000,10000,10000) L_0x1011d80/d; +v0xfe7890_0 .net "A", 0 0, L_0x1012a90; 1 drivers +v0xfe7930_0 .net "AnandB", 0 0, L_0x1011b10; 1 drivers +v0xfe79d0_0 .net "AnorB", 0 0, L_0x1011910; 1 drivers +v0xfe7a50_0 .net "AorB", 0 0, L_0x1011a00; 1 drivers +v0xfe7ad0_0 .net "AxorB", 0 0, L_0x1011d80; 1 drivers +v0xfe7b50_0 .net "B", 0 0, L_0x1012b30; 1 drivers +v0xfe7c10_0 .alias "Command", 2 0, v0xffbc20_0; +v0xfe7c90_0 .net "OrNorXorOut", 0 0, L_0x1012780; 1 drivers +v0xfe7d60_0 .net "XorNor", 0 0, L_0x1012200; 1 drivers +v0xfe7e30_0 .net "nXor", 0 0, L_0x1011c70; 1 drivers +L_0x1012380 .part v0xffc5e0_0, 2, 1; +L_0x1012950 .part v0xffc5e0_0, 0, 1; +S_0xfe7320 .scope module, "mux0" "TwoInMux" 3 83, 3 8, S_0xfe6ca0; + .timescale -9 -12; +L_0x1011ee0/d .functor NOT 1, L_0x1012380, C4<0>, C4<0>, C4<0>; +L_0x1011ee0 .delay (10000,10000,10000) L_0x1011ee0/d; +L_0x1011fa0/d .functor AND 1, L_0x1011d80, L_0x1011ee0, C4<1>, C4<1>; +L_0x1011fa0 .delay (20000,20000,20000) L_0x1011fa0/d; +L_0x10120b0/d .functor AND 1, L_0x1011910, L_0x1012380, C4<1>, C4<1>; +L_0x10120b0 .delay (20000,20000,20000) L_0x10120b0/d; +L_0x1012200/d .functor OR 1, L_0x1011fa0, L_0x10120b0, C4<0>, C4<0>; +L_0x1012200 .delay (20000,20000,20000) L_0x1012200/d; +v0xfe7410_0 .net "S", 0 0, L_0x1012380; 1 drivers +v0xfe74d0_0 .alias "in0", 0 0, v0xfe7ad0_0; +v0xfe7570_0 .alias "in1", 0 0, v0xfe79d0_0; +v0xfe7610_0 .net "nS", 0 0, L_0x1011ee0; 1 drivers +v0xfe7690_0 .net "out0", 0 0, L_0x1011fa0; 1 drivers +v0xfe7730_0 .net "out1", 0 0, L_0x10120b0; 1 drivers +v0xfe7810_0 .alias "outfinal", 0 0, v0xfe7d60_0; +S_0xfe6d90 .scope module, "mux1" "TwoInMux" 3 84, 3 8, S_0xfe6ca0; + .timescale -9 -12; +L_0x1012420/d .functor NOT 1, L_0x1012950, C4<0>, C4<0>, C4<0>; +L_0x1012420 .delay (10000,10000,10000) L_0x1012420/d; +L_0x10124e0/d .functor AND 1, L_0x1012200, L_0x1012420, C4<1>, C4<1>; +L_0x10124e0 .delay (20000,20000,20000) L_0x10124e0/d; +L_0x1012630/d .functor AND 1, L_0x1011a00, L_0x1012950, C4<1>, C4<1>; +L_0x1012630 .delay (20000,20000,20000) L_0x1012630/d; +L_0x1012780/d .functor OR 1, L_0x10124e0, L_0x1012630, C4<0>, C4<0>; +L_0x1012780 .delay (20000,20000,20000) L_0x1012780/d; +v0xfe6e80_0 .net "S", 0 0, L_0x1012950; 1 drivers +v0xfe6f40_0 .alias "in0", 0 0, v0xfe7d60_0; +v0xfe6fe0_0 .alias "in1", 0 0, v0xfe7a50_0; +v0xfe7080_0 .net "nS", 0 0, L_0x1012420; 1 drivers +v0xfe7100_0 .net "out0", 0 0, L_0x10124e0; 1 drivers +v0xfe71a0_0 .net "out1", 0 0, L_0x1012630; 1 drivers +v0xfe7280_0 .alias "outfinal", 0 0, v0xfe7c90_0; +S_0xf6f800 .scope module, "superalu" "Bitslice32" 2 155, 3 302, S_0xeed190; + .timescale -9 -12; +P_0xe99568 .param/l "size" 3 320, +C4<0100>; +L_0x1018d20/d .functor AND 1, L_0x10356f0, L_0x10358d0, C4<1>, C4<1>; +L_0x1018d20 .delay (20000,20000,20000) L_0x1018d20/d; +L_0x10359c0/d .functor NOT 1, L_0x1035a70, C4<0>, C4<0>, C4<0>; +L_0x10359c0 .delay (10000,10000,10000) L_0x10359c0/d; +L_0x1035f20/d .functor AND 1, L_0x10359c0, L_0x10359c0, C4<1>, C4<1>; +L_0x1035f20 .delay (20000,20000,20000) L_0x1035f20/d; +v0xfe5810_0 .alias "A", 3 0, v0xffb8e0_0; +v0xfe5af0_0 .alias "AddSubSLTSum", 3 0, v0xffc3b0_0; +v0xfe5b70_0 .alias "AllZeros", 0 0, v0xffc430_0; +v0xfe5bf0_0 .alias "AndNandOut", 3 0, v0xffc4b0_0; +v0xfe5c70_0 .alias "B", 3 0, v0xffba90_0; +RS_0x7f9963cf1808 .resolv tri, L_0x1014610, L_0x10170b0, L_0x1019ab0, L_0x1033a30; +v0xfe5d80_0 .net8 "Cmd0Start", 3 0, RS_0x7f9963cf1808; 4 drivers +RS_0x7f9963cf1838 .resolv tri, L_0x10155c0, L_0x1017fa0, L_0x101a960, L_0x10348f0; +v0xfe5e00_0 .net8 "Cmd1Start", 3 0, RS_0x7f9963cf1838; 4 drivers +v0xfe5e80_0 .alias "Command", 2 0, v0xffbc20_0; +v0xfe5f00_0 .alias "OneBitFinalOut", 3 0, v0xffc660_0; +v0xfe5f80_0 .alias "OrNorXorOut", 3 0, v0xffc6e0_0; +v0xfe6000_0 .alias "SLTSum", 3 0, v0xffc760_0; +v0xfe60b0_0 .alias "SLTflag", 0 0, v0xffc7e0_0; +v0xfe6130_0 .alias "ZeroFlag", 3 0, v0xffc970_0; +v0xfe61b0_0 .net *"_s111", 0 0, L_0x1018d20; 1 drivers +v0xfe62b0_0 .net *"_s114", 0 0, L_0x10356f0; 1 drivers +v0xfe6330_0 .net *"_s116", 0 0, L_0x10358d0; 1 drivers +v0xfe6230_0 .net *"_s118", 0 0, L_0x1035a70; 1 drivers +v0xfe6480_0 .net *"_s21", 0 0, L_0x1016610; 1 drivers +v0xfe65a0_0 .net *"_s46", 0 0, L_0x10185f0; 1 drivers +v0xfe6620_0 .net *"_s71", 0 0, L_0x101b720; 1 drivers +v0xfe6500_0 .alias "carryin", 3 0, v0xffbed0_0; +v0xfe6750_0 .alias "carryout", 0 0, v0xffcb10_0; +v0xfe66a0_0 .alias "overflow", 0 0, v0xffcc10_0; +v0xfe6890_0 .alias "subtract", 3 0, v0xffcc90_0; +v0xfe69e0_0 .net "yeszero", 0 0, L_0x10359c0; 1 drivers +L_0x1014610 .part/pv L_0x1014430, 1, 1, 4; +L_0x10146b0 .part v0xffc5e0_0, 0, 1; +L_0x10147e0 .part v0xffc5e0_0, 1, 1; +L_0x1014910 .part RS_0x7f9963cefbe8, 1, 1; +L_0x1014ac0 .part RS_0x7f9963cefbe8, 1, 1; +L_0x1014b60 .part RS_0x7f9963cee748, 1, 1; +L_0x1014d10 .part RS_0x7f9963cf1538, 1, 1; +L_0x10155c0 .part/pv L_0x10153b0, 1, 1, 4; +L_0x10156b0 .part v0xffc5e0_0, 0, 1; +L_0x10157e0 .part v0xffc5e0_0, 1, 1; +L_0x1015970 .part RS_0x7f9963ceee38, 1, 1; +L_0x1015b20 .part RS_0x7f9963ceee38, 1, 1; +L_0x1015bc0 .part RS_0x7f9963cee748, 1, 1; +L_0x1015c60 .part RS_0x7f9963cee748, 1, 1; +L_0x10160c0 .part/pv L_0x1015f80, 1, 1, 4; +L_0x10161b0 .part v0xffc5e0_0, 2, 1; +L_0x1016250 .part RS_0x7f9963cf1808, 1, 1; +L_0x1016390 .part RS_0x7f9963cf1838, 1, 1; +L_0x1016570 .part/pv L_0x1016610, 1, 1, 4; +L_0x1016710 .part RS_0x7f9963cf1898, 0, 1; +L_0x10164d0 .part RS_0x7f9963cf1868, 1, 1; +L_0x10170b0 .part/pv L_0x1016ea0, 2, 1, 4; +L_0x10167b0 .part v0xffc5e0_0, 0, 1; +L_0x10172a0 .part v0xffc5e0_0, 1, 1; +L_0x1017150 .part RS_0x7f9963cefbe8, 2, 1; +L_0x10174a0 .part RS_0x7f9963cefbe8, 2, 1; +L_0x10173d0 .part RS_0x7f9963cee748, 2, 1; +L_0x1017670 .part RS_0x7f9963cf1538, 2, 1; +L_0x1017fa0 .part/pv L_0x1017d90, 2, 1, 4; +L_0x1018040 .part v0xffc5e0_0, 0, 1; +L_0x1017760 .part v0xffc5e0_0, 1, 1; +L_0x1018300 .part RS_0x7f9963ceee38, 2, 1; +L_0x1018170 .part RS_0x7f9963ceee38, 2, 1; +L_0x10184b0 .part RS_0x7f9963cee748, 2, 1; +L_0x10183a0 .part RS_0x7f9963cee748, 2, 1; +L_0x1018a20 .part/pv L_0x10188e0, 2, 1, 4; +L_0x1018550 .part v0xffc5e0_0, 2, 1; +L_0x1018c80 .part RS_0x7f9963cf1808, 2, 1; +L_0x1018b50 .part RS_0x7f9963cf1838, 2, 1; +L_0x1018ef0 .part/pv L_0x10185f0, 2, 1, 4; +L_0x1018df0 .part RS_0x7f9963cf1898, 1, 1; +L_0x1019170 .part RS_0x7f9963cf1868, 2, 1; +L_0x1019ab0 .part/pv L_0x10198a0, 3, 1, 4; +L_0x1019b50 .part v0xffc5e0_0, 0, 1; +L_0x1019210 .part v0xffc5e0_0, 1, 1; +L_0x1019df0 .part RS_0x7f9963cefbe8, 3, 1; +L_0x1019c80 .part RS_0x7f9963cefbe8, 3, 1; +L_0x1019d20 .part RS_0x7f9963cee748, 3, 1; +L_0x1019e90 .part RS_0x7f9963cf1538, 3, 1; +L_0x101a960 .part/pv L_0x101a750, 3, 1, 4; +L_0x101a060 .part v0xffc5e0_0, 0, 1; +L_0x101aba0 .part v0xffc5e0_0, 1, 1; +L_0x101aa00 .part RS_0x7f9963ceee38, 3, 1; +L_0x101aaa0 .part RS_0x7f9963ceee38, 3, 1; +L_0x101ae90 .part RS_0x7f9963cee748, 3, 1; +L_0x101af30 .part RS_0x7f9963cee748, 3, 1; +L_0x101b540 .part/pv L_0x101b400, 3, 1, 4; +L_0x101b5e0 .part v0xffc5e0_0, 2, 1; +L_0x101b1e0 .part RS_0x7f9963cf1808, 3, 1; +L_0x101b2d0 .part RS_0x7f9963cf1838, 3, 1; +L_0x101b680 .part/pv L_0x101b720, 3, 1, 4; +L_0x101baa0 .part RS_0x7f9963cf1898, 2, 1; +L_0x101b8b0 .part RS_0x7f9963cf1868, 3, 1; +L_0x1033a30 .part/pv L_0x1033820, 0, 1, 4; +L_0x101bb40 .part v0xffc5e0_0, 0, 1; +L_0x101bc70 .part v0xffc5e0_0, 1, 1; +L_0x1033ad0 .part RS_0x7f9963cefbe8, 0, 1; +L_0x1033b70 .part RS_0x7f9963cefbe8, 0, 1; +L_0x1033c10 .part RS_0x7f9963cee748, 0, 1; +L_0x1033ff0 .part RS_0x7f9963cf1538, 0, 1; +L_0x10348f0 .part/pv L_0x10346e0, 0, 1, 4; +L_0x1034990 .part v0xffc5e0_0, 0, 1; +L_0x10340e0 .part v0xffc5e0_0, 1, 1; +L_0x1034210 .part RS_0x7f9963ceee38, 0, 1; +L_0x1034d20 .part RS_0x7f9963ceee38, 0, 1; +L_0x1034dc0 .part RS_0x7f9963cee748, 0, 1; +L_0x1034ac0 .part RS_0x7f9963cee748, 0, 1; +L_0x1035390 .part/pv L_0x1035250, 0, 1, 4; +L_0x1034e60 .part v0xffc5e0_0, 2, 1; +L_0x1034f00 .part RS_0x7f9963cf1808, 0, 1; +L_0x1034ff0 .part RS_0x7f9963cf1838, 0, 1; +L_0x1035650 .part/pv L_0x1018d20, 0, 1, 4; +L_0x10356f0 .part RS_0x7f9963cf1868, 0, 1; +L_0x10358d0 .part RS_0x7f9963cf1868, 0, 1; +L_0x1035a70 .part RS_0x7f9963cf1898, 3, 1; +S_0xfdd360 .scope module, "test" "SLT32" 3 327, 3 208, S_0xf6f800; + .timescale -9 -12; +P_0xfdc608 .param/l "size" 3 238, +C4<0100>; +L_0x101f7f0/d .functor NOT 1, L_0x1022490, C4<0>, C4<0>, C4<0>; +L_0x101f7f0 .delay (10000,10000,10000) L_0x101f7f0/d; +L_0x10222f0/d .functor AND 1, L_0x10226a0, L_0x1022740, L_0x101f7f0, C4<1>; +L_0x10222f0 .delay (20000,20000,20000) L_0x10222f0/d; +L_0x1023e10/d .functor OR 1, L_0x1024550, C4<0>, C4<0>, C4<0>; +L_0x1023e10 .delay (20000,20000,20000) L_0x1023e10/d; +L_0x1024700/d .functor XOR 1, RS_0x7f9963cefd08, L_0x10247b0, C4<0>, C4<0>; +L_0x1024700 .delay (40000,40000,40000) L_0x1024700/d; +L_0x10243e0/d .functor NOT 1, RS_0x7f9963cefd38, C4<0>, C4<0>, C4<0>; +L_0x10243e0 .delay (10000,10000,10000) L_0x10243e0/d; +L_0x10244d0/d .functor NOT 1, L_0x1024a50, C4<0>, C4<0>, C4<0>; +L_0x10244d0 .delay (10000,10000,10000) L_0x10244d0/d; +L_0x1024af0/d .functor AND 1, L_0x10243e0, L_0x1024c30, C4<1>, C4<1>; +L_0x1024af0 .delay (20000,20000,20000) L_0x1024af0/d; +L_0x1024850/d .functor AND 1, RS_0x7f9963cefd38, L_0x10244d0, C4<1>, C4<1>; +L_0x1024850 .delay (20000,20000,20000) L_0x1024850/d; +L_0x1024e60/d .functor AND 1, L_0x1024af0, L_0x10222f0, C4<1>, C4<1>; +L_0x1024e60 .delay (20000,20000,20000) L_0x1024e60/d; +L_0x1024f60/d .functor AND 1, L_0x1024850, L_0x10222f0, C4<1>, C4<1>; +L_0x1024f60 .delay (20000,20000,20000) L_0x1024f60/d; +L_0x10250b0/d .functor OR 1, L_0x1024e60, L_0x1024f60, C4<0>, C4<0>; +L_0x10250b0 .delay (20000,20000,20000) L_0x10250b0/d; +v0xfe4770_0 .alias "A", 3 0, v0xffb8e0_0; +RS_0x7f9963cf1448 .resolv tri, L_0x101d580, L_0x101f750, L_0x1021a20, L_0x1024140; +v0xfe4810_0 .net8 "AddSubSLTSum", 3 0, RS_0x7f9963cf1448; 4 drivers +v0xfe48b0_0 .alias "B", 3 0, v0xffba90_0; +RS_0x7f9963cf1478 .resolv tri, L_0x101cbd0, L_0x101eee0, L_0x10210e0, L_0x10238f0; +v0xfe4930_0 .net8 "CarryoutWire", 3 0, RS_0x7f9963cf1478; 4 drivers +v0xfe49e0_0 .alias "Command", 2 0, v0xffbc20_0; +RS_0x7f9963cf14a8 .resolv tri, L_0x101cae0, L_0x101ed80, L_0x1020ff0, L_0x1023800; +v0xfe4a60_0 .net8 "NewVal", 3 0, RS_0x7f9963cf14a8; 4 drivers +v0xfe4b00_0 .net "Res0OF1", 0 0, L_0x1024850; 1 drivers +v0xfe4ba0_0 .net "Res1OF0", 0 0, L_0x1024af0; 1 drivers +v0xfe4c40_0 .alias "SLTSum", 3 0, v0xffc760_0; +v0xfe4ce0_0 .alias "SLTflag", 0 0, v0xffc7e0_0; +v0xfe4d60_0 .net "SLTflag0", 0 0, L_0x1024e60; 1 drivers +v0xfe4e00_0 .net "SLTflag1", 0 0, L_0x1024f60; 1 drivers +v0xfe4ea0_0 .net "SLTon", 0 0, L_0x10222f0; 1 drivers +v0xfe4f20_0 .net *"_s49", 0 0, L_0x1022490; 1 drivers +v0xfe5040_0 .net *"_s51", 0 0, L_0x10226a0; 1 drivers +v0xfe50e0_0 .net *"_s53", 0 0, L_0x1022740; 1 drivers +v0xfe4fa0_0 .net *"_s73", 0 0, L_0x1024550; 1 drivers +v0xfe5230_0 .net/s *"_s74", 0 0, C4<0>; 1 drivers +v0xfe5350_0 .net *"_s77", 0 0, L_0x10247b0; 1 drivers +v0xfe53d0_0 .net *"_s79", 0 0, L_0x1024a50; 1 drivers +v0xfe52b0_0 .net *"_s81", 0 0, L_0x1024c30; 1 drivers +v0xfe5500_0 .alias "carryin", 3 0, v0xffbed0_0; +v0xfe5450_0 .alias "carryout", 0 0, v0xffcb10_0; +v0xfe5640_0 .net "nAddSubSLTSum", 0 0, L_0x10244d0; 1 drivers +v0xfe5580_0 .net "nCmd2", 0 0, L_0x101f7f0; 1 drivers +v0xfe5790_0 .net "nOF", 0 0, L_0x10243e0; 1 drivers +v0xfe56c0_0 .alias "overflow", 0 0, v0xffcc10_0; +v0xfe58f0_0 .alias "subtract", 3 0, v0xffcc90_0; +L_0x101cae0 .part/pv L_0x101c650, 1, 1, 4; +L_0x101cbd0 .part/pv L_0x101c9a0, 1, 1, 4; +L_0x101ccc0 .part/pv L_0x101c380, 1, 1, 4; +L_0x10008a0 .part v0xffc310_0, 1, 1; +L_0x101cf70 .part v0xffc560_0, 1, 1; +L_0x101d0a0 .part RS_0x7f9963cf1478, 0, 1; +L_0x101d580 .part/pv L_0x101d440, 1, 1, 4; +L_0x101d620 .part RS_0x7f9963cf14a8, 1, 1; +L_0x101dbc0 .part/pv L_0x101da80, 1, 1, 4; +L_0x101dc60 .part RS_0x7f9963cf1448, 1, 1; +L_0x101de00 .part RS_0x7f9963cf1448, 1, 1; +L_0x101ed80 .part/pv L_0x101e8f0, 2, 1, 4; +L_0x101eee0 .part/pv L_0x101ec40, 2, 1, 4; +L_0x101efd0 .part/pv L_0x101e620, 2, 1, 4; +L_0x101f140 .part v0xffc310_0, 2, 1; +L_0x101f1e0 .part v0xffc560_0, 2, 1; +L_0x101f3a0 .part RS_0x7f9963cf1478, 1, 1; +L_0x101f750 .part/pv L_0x101f610, 2, 1, 4; +L_0x101f920 .part RS_0x7f9963cf14a8, 2, 1; +L_0x101fdd0 .part/pv L_0x101fc90, 2, 1, 4; +L_0x101f880 .part RS_0x7f9963cf1448, 2, 1; +L_0x101ff70 .part RS_0x7f9963cf1448, 2, 1; +L_0x1020ff0 .part/pv L_0x1020b40, 3, 1, 4; +L_0x10210e0 .part/pv L_0x1020e90, 3, 1, 4; +L_0x1020060 .part/pv L_0x1020870, 3, 1, 4; +L_0x10212f0 .part v0xffc310_0, 3, 1; +L_0x10211d0 .part v0xffc560_0, 3, 1; +L_0x1021500 .part RS_0x7f9963cf1478, 2, 1; +L_0x1021a20 .part/pv L_0x10218e0, 3, 1, 4; +L_0x1021ac0 .part RS_0x7f9963cf14a8, 3, 1; +L_0x1022050 .part/pv L_0x1021f10, 3, 1, 4; +L_0x10220f0 .part RS_0x7f9963cf1448, 3, 1; +L_0x1021bb0 .part RS_0x7f9963cf1448, 3, 1; +L_0x1022490 .part v0xffc5e0_0, 2, 1; +L_0x10226a0 .part v0xffc5e0_0, 0, 1; +L_0x1022740 .part v0xffc5e0_0, 1, 1; +L_0x1023800 .part/pv L_0x1023350, 0, 1, 4; +L_0x10238f0 .part/pv L_0x10236a0, 0, 1, 4; +L_0x1022830 .part/pv L_0x1023080, 0, 1, 4; +L_0x1023b20 .part v0xffc310_0, 0, 1; +L_0x10239e0 .part v0xffc560_0, 0, 1; +L_0x1023d10 .part RS_0x7f9963cefd68, 0, 1; +L_0x1024140 .part/pv L_0x1024000, 0, 1, 4; +L_0x10241e0 .part RS_0x7f9963cf14a8, 0, 1; +L_0x1024550 .part RS_0x7f9963cf1478, 3, 1; +L_0x10247b0 .part RS_0x7f9963cf1478, 2, 1; +L_0x1024a50 .part RS_0x7f9963cf1448, 3, 1; +L_0x1024c30 .part RS_0x7f9963cf14a8, 3, 1; +L_0x1025660 .part/pv L_0x1025520, 0, 1, 4; +L_0x1025700 .part RS_0x7f9963cf1448, 0, 1; +S_0xfe3750 .scope module, "attempt2" "MiddleAddSubSLT" 3 234, 3 88, S_0xfdd360; + .timescale -9 -12; +L_0x1022530/d .functor NOT 1, L_0x10239e0, C4<0>, C4<0>, C4<0>; +L_0x1022530 .delay (10000,10000,10000) L_0x1022530/d; +L_0x1022f20/d .functor NOT 1, L_0x1022fe0, C4<0>, C4<0>, C4<0>; +L_0x1022f20 .delay (10000,10000,10000) L_0x1022f20/d; +L_0x1023080/d .functor AND 1, L_0x10231c0, L_0x1022f20, C4<1>, C4<1>; +L_0x1023080 .delay (20000,20000,20000) L_0x1023080/d; +L_0x1023260/d .functor XOR 1, L_0x1023b20, L_0x1022cb0, C4<0>, C4<0>; +L_0x1023260 .delay (40000,40000,40000) L_0x1023260/d; +L_0x1023350/d .functor XOR 1, L_0x1023260, L_0x1023d10, C4<0>, C4<0>; +L_0x1023350 .delay (40000,40000,40000) L_0x1023350/d; +L_0x1023440/d .functor AND 1, L_0x1023b20, L_0x1022cb0, C4<1>, C4<1>; +L_0x1023440 .delay (20000,20000,20000) L_0x1023440/d; +L_0x10235b0/d .functor AND 1, L_0x1023260, L_0x1023d10, C4<1>, C4<1>; +L_0x10235b0 .delay (20000,20000,20000) L_0x10235b0/d; +L_0x10236a0/d .functor OR 1, L_0x1023440, L_0x10235b0, C4<0>, C4<0>; +L_0x10236a0 .delay (20000,20000,20000) L_0x10236a0/d; +v0xfe3dd0_0 .net "A", 0 0, L_0x1023b20; 1 drivers +v0xfe3e90_0 .net "AandB", 0 0, L_0x1023440; 1 drivers +v0xfe3f30_0 .net "AddSubSLTSum", 0 0, L_0x1023350; 1 drivers +v0xfe3fd0_0 .net "AxorB", 0 0, L_0x1023260; 1 drivers +v0xfe4050_0 .net "B", 0 0, L_0x10239e0; 1 drivers +v0xfe4100_0 .net "BornB", 0 0, L_0x1022cb0; 1 drivers +v0xfe41c0_0 .net "CINandAxorB", 0 0, L_0x10235b0; 1 drivers +v0xfe4240_0 .alias "Command", 2 0, v0xffbc20_0; +v0xfe42c0_0 .net *"_s3", 0 0, L_0x1022fe0; 1 drivers +v0xfe4340_0 .net *"_s5", 0 0, L_0x10231c0; 1 drivers +v0xfe43e0_0 .net "carryin", 0 0, L_0x1023d10; 1 drivers +v0xfe4480_0 .net "carryout", 0 0, L_0x10236a0; 1 drivers +v0xfe4520_0 .net "nB", 0 0, L_0x1022530; 1 drivers +v0xfe45d0_0 .net "nCmd2", 0 0, L_0x1022f20; 1 drivers +v0xfe46d0_0 .net "subtract", 0 0, L_0x1023080; 1 drivers +L_0x1022e80 .part v0xffc5e0_0, 0, 1; +L_0x1022fe0 .part v0xffc5e0_0, 2, 1; +L_0x10231c0 .part v0xffc5e0_0, 0, 1; +S_0xfe3840 .scope module, "mux0" "TwoInMux" 3 104, 3 8, S_0xfe3750; + .timescale -9 -12; +L_0x10229f0/d .functor NOT 1, L_0x1022e80, C4<0>, C4<0>, C4<0>; +L_0x10229f0 .delay (10000,10000,10000) L_0x10229f0/d; +L_0x1022a90/d .functor AND 1, L_0x10239e0, L_0x10229f0, C4<1>, C4<1>; +L_0x1022a90 .delay (20000,20000,20000) L_0x1022a90/d; +L_0x1022ba0/d .functor AND 1, L_0x1022530, L_0x1022e80, C4<1>, C4<1>; +L_0x1022ba0 .delay (20000,20000,20000) L_0x1022ba0/d; +L_0x1022cb0/d .functor OR 1, L_0x1022a90, L_0x1022ba0, C4<0>, C4<0>; +L_0x1022cb0 .delay (20000,20000,20000) L_0x1022cb0/d; +v0xfe3930_0 .net "S", 0 0, L_0x1022e80; 1 drivers +v0xfe39f0_0 .alias "in0", 0 0, v0xfe4050_0; +v0xfe3a90_0 .alias "in1", 0 0, v0xfe4520_0; +v0xfe3b30_0 .net "nS", 0 0, L_0x10229f0; 1 drivers +v0xfe3bb0_0 .net "out0", 0 0, L_0x1022a90; 1 drivers +v0xfe3c50_0 .net "out1", 0 0, L_0x1022ba0; 1 drivers +v0xfe3d30_0 .alias "outfinal", 0 0, v0xfe4100_0; +S_0xfe31e0 .scope module, "setSLTresult" "TwoInMux" 3 235, 3 8, S_0xfdd360; + .timescale -9 -12; +L_0x1023bc0/d .functor NOT 1, L_0x10222f0, C4<0>, C4<0>, C4<0>; +L_0x1023bc0 .delay (10000,10000,10000) L_0x1023bc0/d; +L_0x1023c60/d .functor AND 1, L_0x10241e0, L_0x1023bc0, C4<1>, C4<1>; +L_0x1023c60 .delay (20000,20000,20000) L_0x1023c60/d; +L_0x1023f60/d .functor AND 1, C4<0>, L_0x10222f0, C4<1>, C4<1>; +L_0x1023f60 .delay (20000,20000,20000) L_0x1023f60/d; +L_0x1024000/d .functor OR 1, L_0x1023c60, L_0x1023f60, C4<0>, C4<0>; +L_0x1024000 .delay (20000,20000,20000) L_0x1024000/d; +v0xfe32d0_0 .alias "S", 0 0, v0xfe4ea0_0; +v0xfe3370_0 .net "in0", 0 0, L_0x10241e0; 1 drivers +v0xfe3410_0 .net "in1", 0 0, C4<0>; 1 drivers +v0xfe34b0_0 .net "nS", 0 0, L_0x1023bc0; 1 drivers +v0xfe3530_0 .net "out0", 0 0, L_0x1023c60; 1 drivers +v0xfe35d0_0 .net "out1", 0 0, L_0x1023f60; 1 drivers +v0xfe36b0_0 .net "outfinal", 0 0, L_0x1024000; 1 drivers +S_0xfe2c70 .scope module, "FinalSLT" "TwoInMux" 3 261, 3 8, S_0xfdd360; + .timescale -9 -12; +L_0x10251c0/d .functor NOT 1, L_0x10250b0, C4<0>, C4<0>, C4<0>; +L_0x10251c0 .delay (10000,10000,10000) L_0x10251c0/d; +L_0x10252a0/d .functor AND 1, L_0x1025700, L_0x10251c0, C4<1>, C4<1>; +L_0x10252a0 .delay (20000,20000,20000) L_0x10252a0/d; +L_0x10253b0/d .functor AND 1, L_0x10250b0, L_0x10250b0, C4<1>, C4<1>; +L_0x10253b0 .delay (20000,20000,20000) L_0x10253b0/d; +L_0x1025520/d .functor OR 1, L_0x10252a0, L_0x10253b0, C4<0>, C4<0>; +L_0x1025520 .delay (20000,20000,20000) L_0x1025520/d; +v0xfe2d60_0 .alias "S", 0 0, v0xffc7e0_0; +v0xfe2e20_0 .net "in0", 0 0, L_0x1025700; 1 drivers +v0xfe2ec0_0 .alias "in1", 0 0, v0xffc7e0_0; +v0xfe2f70_0 .net "nS", 0 0, L_0x10251c0; 1 drivers +v0xfe3020_0 .net "out0", 0 0, L_0x10252a0; 1 drivers +v0xfe30a0_0 .net "out1", 0 0, L_0x10253b0; 1 drivers +v0xfe3140_0 .net "outfinal", 0 0, L_0x1025520; 1 drivers +S_0xfe0f60 .scope generate, "sltbits[1]" "sltbits[1]" 3 240, 3 240, S_0xfdd360; + .timescale -9 -12; +P_0xfe0818 .param/l "i" 3 240, +C4<01>; +S_0xfe1c50 .scope module, "attempt" "MiddleAddSubSLT" 3 242, 3 88, S_0xfe0f60; + .timescale -9 -12; +L_0x101b9a0/d .functor NOT 1, L_0x101cf70, C4<0>, C4<0>, C4<0>; +L_0x101b9a0 .delay (10000,10000,10000) L_0x101b9a0/d; +L_0x101c240/d .functor NOT 1, L_0x101c2e0, C4<0>, C4<0>, C4<0>; +L_0x101c240 .delay (10000,10000,10000) L_0x101c240/d; +L_0x101c380/d .functor AND 1, L_0x101c4c0, L_0x101c240, C4<1>, C4<1>; +L_0x101c380 .delay (20000,20000,20000) L_0x101c380/d; +L_0x101c560/d .functor XOR 1, L_0x10008a0, L_0x101c010, C4<0>, C4<0>; +L_0x101c560 .delay (40000,40000,40000) L_0x101c560/d; +L_0x101c650/d .functor XOR 1, L_0x101c560, L_0x101d0a0, C4<0>, C4<0>; +L_0x101c650 .delay (40000,40000,40000) L_0x101c650/d; +L_0x101c740/d .functor AND 1, L_0x10008a0, L_0x101c010, C4<1>, C4<1>; +L_0x101c740 .delay (20000,20000,20000) L_0x101c740/d; +L_0x101c8b0/d .functor AND 1, L_0x101c560, L_0x101d0a0, C4<1>, C4<1>; +L_0x101c8b0 .delay (20000,20000,20000) L_0x101c8b0/d; +L_0x101c9a0/d .functor OR 1, L_0x101c740, L_0x101c8b0, C4<0>, C4<0>; +L_0x101c9a0 .delay (20000,20000,20000) L_0x101c9a0/d; +v0xfe22d0_0 .net "A", 0 0, L_0x10008a0; 1 drivers +v0xfe2390_0 .net "AandB", 0 0, L_0x101c740; 1 drivers +v0xfe2430_0 .net "AddSubSLTSum", 0 0, L_0x101c650; 1 drivers +v0xfe24d0_0 .net "AxorB", 0 0, L_0x101c560; 1 drivers +v0xfe2550_0 .net "B", 0 0, L_0x101cf70; 1 drivers +v0xfe2600_0 .net "BornB", 0 0, L_0x101c010; 1 drivers +v0xfe26c0_0 .net "CINandAxorB", 0 0, L_0x101c8b0; 1 drivers +v0xfe2740_0 .alias "Command", 2 0, v0xffbc20_0; +v0xfe27c0_0 .net *"_s3", 0 0, L_0x101c2e0; 1 drivers +v0xfe2840_0 .net *"_s5", 0 0, L_0x101c4c0; 1 drivers +v0xfe28e0_0 .net "carryin", 0 0, L_0x101d0a0; 1 drivers +v0xfe2980_0 .net "carryout", 0 0, L_0x101c9a0; 1 drivers +v0xfe2a20_0 .net "nB", 0 0, L_0x101b9a0; 1 drivers +v0xfe2ad0_0 .net "nCmd2", 0 0, L_0x101c240; 1 drivers +v0xfe2bd0_0 .net "subtract", 0 0, L_0x101c380; 1 drivers +L_0x101c1a0 .part v0xffc5e0_0, 0, 1; +L_0x101c2e0 .part v0xffc5e0_0, 2, 1; +L_0x101c4c0 .part v0xffc5e0_0, 0, 1; +S_0xfe1d40 .scope module, "mux0" "TwoInMux" 3 104, 3 8, S_0xfe1c50; + .timescale -9 -12; +L_0x101bd90/d .functor NOT 1, L_0x101c1a0, C4<0>, C4<0>, C4<0>; +L_0x101bd90 .delay (10000,10000,10000) L_0x101bd90/d; +L_0x101be30/d .functor AND 1, L_0x101cf70, L_0x101bd90, C4<1>, C4<1>; +L_0x101be30 .delay (20000,20000,20000) L_0x101be30/d; +L_0x101bf20/d .functor AND 1, L_0x101b9a0, L_0x101c1a0, C4<1>, C4<1>; +L_0x101bf20 .delay (20000,20000,20000) L_0x101bf20/d; +L_0x101c010/d .functor OR 1, L_0x101be30, L_0x101bf20, C4<0>, C4<0>; +L_0x101c010 .delay (20000,20000,20000) L_0x101c010/d; +v0xfe1e30_0 .net "S", 0 0, L_0x101c1a0; 1 drivers +v0xfe1ef0_0 .alias "in0", 0 0, v0xfe2550_0; +v0xfe1f90_0 .alias "in1", 0 0, v0xfe2a20_0; +v0xfe2030_0 .net "nS", 0 0, L_0x101bd90; 1 drivers +v0xfe20b0_0 .net "out0", 0 0, L_0x101be30; 1 drivers +v0xfe2150_0 .net "out1", 0 0, L_0x101bf20; 1 drivers +v0xfe2230_0 .alias "outfinal", 0 0, v0xfe2600_0; +S_0xfe16e0 .scope module, "setSLTres2" "TwoInMux" 3 243, 3 8, S_0xfe0f60; + .timescale -9 -12; +L_0x101d140/d .functor NOT 1, L_0x10222f0, C4<0>, C4<0>, C4<0>; +L_0x101d140 .delay (10000,10000,10000) L_0x101d140/d; +L_0x101d2b0/d .functor AND 1, L_0x101d620, L_0x101d140, C4<1>, C4<1>; +L_0x101d2b0 .delay (20000,20000,20000) L_0x101d2b0/d; +L_0x101d3a0/d .functor AND 1, C4<0>, L_0x10222f0, C4<1>, C4<1>; +L_0x101d3a0 .delay (20000,20000,20000) L_0x101d3a0/d; +L_0x101d440/d .functor OR 1, L_0x101d2b0, L_0x101d3a0, C4<0>, C4<0>; +L_0x101d440 .delay (20000,20000,20000) L_0x101d440/d; +v0xfe17d0_0 .alias "S", 0 0, v0xfe4ea0_0; +v0xfe1870_0 .net "in0", 0 0, L_0x101d620; 1 drivers +v0xfe1910_0 .net "in1", 0 0, C4<0>; 1 drivers +v0xfe19b0_0 .net "nS", 0 0, L_0x101d140; 1 drivers +v0xfe1a30_0 .net "out0", 0 0, L_0x101d2b0; 1 drivers +v0xfe1ad0_0 .net "out1", 0 0, L_0x101d3a0; 1 drivers +v0xfe1bb0_0 .net "outfinal", 0 0, L_0x101d440; 1 drivers +S_0xfe10d0 .scope module, "setSLTres3" "TwoInMux" 3 244, 3 8, S_0xfe0f60; + .timescale -9 -12; +L_0x101d800/d .functor NOT 1, L_0x10222f0, C4<0>, C4<0>, C4<0>; +L_0x101d800 .delay (10000,10000,10000) L_0x101d800/d; +L_0x101d8f0/d .functor AND 1, L_0x101dc60, L_0x101d800, C4<1>, C4<1>; +L_0x101d8f0 .delay (20000,20000,20000) L_0x101d8f0/d; +L_0x101d9e0/d .functor AND 1, L_0x101de00, L_0x10222f0, C4<1>, C4<1>; +L_0x101d9e0 .delay (20000,20000,20000) L_0x101d9e0/d; +L_0x101da80/d .functor OR 1, L_0x101d8f0, L_0x101d9e0, C4<0>, C4<0>; +L_0x101da80 .delay (20000,20000,20000) L_0x101da80/d; +v0xfe11c0_0 .alias "S", 0 0, v0xfe4ea0_0; +v0xfe12d0_0 .net "in0", 0 0, L_0x101dc60; 1 drivers +v0xfe1370_0 .net "in1", 0 0, L_0x101de00; 1 drivers +v0xfe1410_0 .net "nS", 0 0, L_0x101d800; 1 drivers +v0xfe14c0_0 .net "out0", 0 0, L_0x101d8f0; 1 drivers +v0xfe1560_0 .net "out1", 0 0, L_0x101d9e0; 1 drivers +v0xfe1640_0 .net "outfinal", 0 0, L_0x101da80; 1 drivers +S_0xfdf1b0 .scope generate, "sltbits[2]" "sltbits[2]" 3 240, 3 240, S_0xfdd360; + .timescale -9 -12; +P_0xfdeb58 .param/l "i" 3 240, +C4<010>; +S_0xfdfde0 .scope module, "attempt" "MiddleAddSubSLT" 3 242, 3 88, S_0xfdf1b0; + .timescale -9 -12; +L_0x101dea0/d .functor NOT 1, L_0x101f1e0, C4<0>, C4<0>, C4<0>; +L_0x101dea0 .delay (10000,10000,10000) L_0x101dea0/d; +L_0x101e4e0/d .functor NOT 1, L_0x101e580, C4<0>, C4<0>, C4<0>; +L_0x101e4e0 .delay (10000,10000,10000) L_0x101e4e0/d; +L_0x101e620/d .functor AND 1, L_0x101e760, L_0x101e4e0, C4<1>, C4<1>; +L_0x101e620 .delay (20000,20000,20000) L_0x101e620/d; +L_0x101e800/d .functor XOR 1, L_0x101f140, L_0x101e2b0, C4<0>, C4<0>; +L_0x101e800 .delay (40000,40000,40000) L_0x101e800/d; +L_0x101e8f0/d .functor XOR 1, L_0x101e800, L_0x101f3a0, C4<0>, C4<0>; +L_0x101e8f0 .delay (40000,40000,40000) L_0x101e8f0/d; +L_0x101e9e0/d .functor AND 1, L_0x101f140, L_0x101e2b0, C4<1>, C4<1>; +L_0x101e9e0 .delay (20000,20000,20000) L_0x101e9e0/d; +L_0x101eb50/d .functor AND 1, L_0x101e800, L_0x101f3a0, C4<1>, C4<1>; +L_0x101eb50 .delay (20000,20000,20000) L_0x101eb50/d; +L_0x101ec40/d .functor OR 1, L_0x101e9e0, L_0x101eb50, C4<0>, C4<0>; +L_0x101ec40 .delay (20000,20000,20000) L_0x101ec40/d; +v0xfe0460_0 .net "A", 0 0, L_0x101f140; 1 drivers +v0xfe0520_0 .net "AandB", 0 0, L_0x101e9e0; 1 drivers +v0xfe05c0_0 .net "AddSubSLTSum", 0 0, L_0x101e8f0; 1 drivers +v0xfe0660_0 .net "AxorB", 0 0, L_0x101e800; 1 drivers +v0xfe06e0_0 .net "B", 0 0, L_0x101f1e0; 1 drivers +v0xfe0790_0 .net "BornB", 0 0, L_0x101e2b0; 1 drivers +v0xfe0850_0 .net "CINandAxorB", 0 0, L_0x101eb50; 1 drivers +v0xfe08d0_0 .alias "Command", 2 0, v0xffbc20_0; +v0xfd81f0_0 .net *"_s3", 0 0, L_0x101e580; 1 drivers +v0xfd8270_0 .net *"_s5", 0 0, L_0x101e760; 1 drivers +v0xfe0bd0_0 .net "carryin", 0 0, L_0x101f3a0; 1 drivers +v0xfe0c70_0 .net "carryout", 0 0, L_0x101ec40; 1 drivers +v0xfe0d10_0 .net "nB", 0 0, L_0x101dea0; 1 drivers +v0xfe0dc0_0 .net "nCmd2", 0 0, L_0x101e4e0; 1 drivers +v0xfe0ec0_0 .net "subtract", 0 0, L_0x101e620; 1 drivers +L_0x101e440 .part v0xffc5e0_0, 0, 1; +L_0x101e580 .part v0xffc5e0_0, 2, 1; +L_0x101e760 .part v0xffc5e0_0, 0, 1; +S_0xfdfed0 .scope module, "mux0" "TwoInMux" 3 104, 3 8, S_0xfdfde0; + .timescale -9 -12; +L_0x101e030/d .functor NOT 1, L_0x101e440, C4<0>, C4<0>, C4<0>; +L_0x101e030 .delay (10000,10000,10000) L_0x101e030/d; +L_0x101e0d0/d .functor AND 1, L_0x101f1e0, L_0x101e030, C4<1>, C4<1>; +L_0x101e0d0 .delay (20000,20000,20000) L_0x101e0d0/d; +L_0x101e1c0/d .functor AND 1, L_0x101dea0, L_0x101e440, C4<1>, C4<1>; +L_0x101e1c0 .delay (20000,20000,20000) L_0x101e1c0/d; +L_0x101e2b0/d .functor OR 1, L_0x101e0d0, L_0x101e1c0, C4<0>, C4<0>; +L_0x101e2b0 .delay (20000,20000,20000) L_0x101e2b0/d; +v0xfdffc0_0 .net "S", 0 0, L_0x101e440; 1 drivers +v0xfe0080_0 .alias "in0", 0 0, v0xfe06e0_0; +v0xfe0120_0 .alias "in1", 0 0, v0xfe0d10_0; +v0xfe01c0_0 .net "nS", 0 0, L_0x101e030; 1 drivers +v0xfe0240_0 .net "out0", 0 0, L_0x101e0d0; 1 drivers +v0xfe02e0_0 .net "out1", 0 0, L_0x101e1c0; 1 drivers +v0xfe03c0_0 .alias "outfinal", 0 0, v0xfe0790_0; +S_0xfdf870 .scope module, "setSLTres2" "TwoInMux" 3 243, 3 8, S_0xfdf1b0; + .timescale -9 -12; +L_0x101dda0/d .functor NOT 1, L_0x10222f0, C4<0>, C4<0>, C4<0>; +L_0x101dda0 .delay (10000,10000,10000) L_0x101dda0/d; +L_0x101f4d0/d .functor AND 1, L_0x101f920, L_0x101dda0, C4<1>, C4<1>; +L_0x101f4d0 .delay (20000,20000,20000) L_0x101f4d0/d; +L_0x101f570/d .functor AND 1, C4<0>, L_0x10222f0, C4<1>, C4<1>; +L_0x101f570 .delay (20000,20000,20000) L_0x101f570/d; +L_0x101f610/d .functor OR 1, L_0x101f4d0, L_0x101f570, C4<0>, C4<0>; +L_0x101f610 .delay (20000,20000,20000) L_0x101f610/d; +v0xfdf960_0 .alias "S", 0 0, v0xfe4ea0_0; +v0xfdfa00_0 .net "in0", 0 0, L_0x101f920; 1 drivers +v0xfdfaa0_0 .net "in1", 0 0, C4<0>; 1 drivers +v0xfdfb40_0 .net "nS", 0 0, L_0x101dda0; 1 drivers +v0xfdfbc0_0 .net "out0", 0 0, L_0x101f4d0; 1 drivers +v0xfdfc60_0 .net "out1", 0 0, L_0x101f570; 1 drivers +v0xfdfd40_0 .net "outfinal", 0 0, L_0x101f610; 1 drivers +S_0xfdf320 .scope module, "setSLTres3" "TwoInMux" 3 244, 3 8, S_0xfdf1b0; + .timescale -9 -12; +L_0x101fa50/d .functor NOT 1, L_0x10222f0, C4<0>, C4<0>, C4<0>; +L_0x101fa50 .delay (10000,10000,10000) L_0x101fa50/d; +L_0x101fb00/d .functor AND 1, L_0x101f880, L_0x101fa50, C4<1>, C4<1>; +L_0x101fb00 .delay (20000,20000,20000) L_0x101fb00/d; +L_0x101fbf0/d .functor AND 1, L_0x101ff70, L_0x10222f0, C4<1>, C4<1>; +L_0x101fbf0 .delay (20000,20000,20000) L_0x101fbf0/d; +L_0x101fc90/d .functor OR 1, L_0x101fb00, L_0x101fbf0, C4<0>, C4<0>; +L_0x101fc90 .delay (20000,20000,20000) L_0x101fc90/d; +v0xfdf410_0 .alias "S", 0 0, v0xfe4ea0_0; +v0xfdf490_0 .net "in0", 0 0, L_0x101f880; 1 drivers +v0xfdf530_0 .net "in1", 0 0, L_0x101ff70; 1 drivers +v0xfdf5d0_0 .net "nS", 0 0, L_0x101fa50; 1 drivers +v0xfdf650_0 .net "out0", 0 0, L_0x101fb00; 1 drivers +v0xfdf6f0_0 .net "out1", 0 0, L_0x101fbf0; 1 drivers +v0xfdf7d0_0 .net "outfinal", 0 0, L_0x101fc90; 1 drivers +S_0xfdd4d0 .scope generate, "sltbits[3]" "sltbits[3]" 3 240, 3 240, S_0xfdd360; + .timescale -9 -12; +P_0xfdd5c8 .param/l "i" 3 240, +C4<011>; +S_0xfde120 .scope module, "attempt" "MiddleAddSubSLT" 3 242, 3 88, S_0xfdd4d0; + .timescale -9 -12; +L_0x101fe70/d .functor NOT 1, L_0x10211d0, C4<0>, C4<0>, C4<0>; +L_0x101fe70 .delay (10000,10000,10000) L_0x101fe70/d; +L_0x1020710/d .functor NOT 1, L_0x10207d0, C4<0>, C4<0>, C4<0>; +L_0x1020710 .delay (10000,10000,10000) L_0x1020710/d; +L_0x1020870/d .functor AND 1, L_0x10209b0, L_0x1020710, C4<1>, C4<1>; +L_0x1020870 .delay (20000,20000,20000) L_0x1020870/d; +L_0x1020a50/d .functor XOR 1, L_0x10212f0, L_0x10204a0, C4<0>, C4<0>; +L_0x1020a50 .delay (40000,40000,40000) L_0x1020a50/d; +L_0x1020b40/d .functor XOR 1, L_0x1020a50, L_0x1021500, C4<0>, C4<0>; +L_0x1020b40 .delay (40000,40000,40000) L_0x1020b40/d; +L_0x1020c30/d .functor AND 1, L_0x10212f0, L_0x10204a0, C4<1>, C4<1>; +L_0x1020c30 .delay (20000,20000,20000) L_0x1020c30/d; +L_0x1020da0/d .functor AND 1, L_0x1020a50, L_0x1021500, C4<1>, C4<1>; +L_0x1020da0 .delay (20000,20000,20000) L_0x1020da0/d; +L_0x1020e90/d .functor OR 1, L_0x1020c30, L_0x1020da0, C4<0>, C4<0>; +L_0x1020e90 .delay (20000,20000,20000) L_0x1020e90/d; +v0xfde7a0_0 .net "A", 0 0, L_0x10212f0; 1 drivers +v0xfde860_0 .net "AandB", 0 0, L_0x1020c30; 1 drivers +v0xfde900_0 .net "AddSubSLTSum", 0 0, L_0x1020b40; 1 drivers +v0xfde9a0_0 .net "AxorB", 0 0, L_0x1020a50; 1 drivers +v0xfdea20_0 .net "B", 0 0, L_0x10211d0; 1 drivers +v0xfdead0_0 .net "BornB", 0 0, L_0x10204a0; 1 drivers +v0xfdeb90_0 .net "CINandAxorB", 0 0, L_0x1020da0; 1 drivers +v0xfdec10_0 .alias "Command", 2 0, v0xffbc20_0; +v0xfdec90_0 .net *"_s3", 0 0, L_0x10207d0; 1 drivers +v0xfded10_0 .net *"_s5", 0 0, L_0x10209b0; 1 drivers +v0xfdedb0_0 .net "carryin", 0 0, L_0x1021500; 1 drivers +v0xfdee50_0 .net "carryout", 0 0, L_0x1020e90; 1 drivers +v0xfdef60_0 .net "nB", 0 0, L_0x101fe70; 1 drivers +v0xfdf010_0 .net "nCmd2", 0 0, L_0x1020710; 1 drivers +v0xfdf110_0 .net "subtract", 0 0, L_0x1020870; 1 drivers +L_0x1020670 .part v0xffc5e0_0, 0, 1; +L_0x10207d0 .part v0xffc5e0_0, 2, 1; +L_0x10209b0 .part v0xffc5e0_0, 0, 1; +S_0xfde210 .scope module, "mux0" "TwoInMux" 3 104, 3 8, S_0xfde120; + .timescale -9 -12; +L_0x1020200/d .functor NOT 1, L_0x1020670, C4<0>, C4<0>, C4<0>; +L_0x1020200 .delay (10000,10000,10000) L_0x1020200/d; +L_0x10202a0/d .functor AND 1, L_0x10211d0, L_0x1020200, C4<1>, C4<1>; +L_0x10202a0 .delay (20000,20000,20000) L_0x10202a0/d; +L_0x1020390/d .functor AND 1, L_0x101fe70, L_0x1020670, C4<1>, C4<1>; +L_0x1020390 .delay (20000,20000,20000) L_0x1020390/d; +L_0x10204a0/d .functor OR 1, L_0x10202a0, L_0x1020390, C4<0>, C4<0>; +L_0x10204a0 .delay (20000,20000,20000) L_0x10204a0/d; +v0xfde300_0 .net "S", 0 0, L_0x1020670; 1 drivers +v0xfde3c0_0 .alias "in0", 0 0, v0xfdea20_0; +v0xfde460_0 .alias "in1", 0 0, v0xfdef60_0; +v0xfde500_0 .net "nS", 0 0, L_0x1020200; 1 drivers +v0xfde580_0 .net "out0", 0 0, L_0x10202a0; 1 drivers +v0xfde620_0 .net "out1", 0 0, L_0x1020390; 1 drivers +v0xfde700_0 .alias "outfinal", 0 0, v0xfdead0_0; +S_0xfddbd0 .scope module, "setSLTres2" "TwoInMux" 3 243, 3 8, S_0xfdd4d0; + .timescale -9 -12; +L_0x1021390/d .functor NOT 1, L_0x10222f0, C4<0>, C4<0>, C4<0>; +L_0x1021390 .delay (10000,10000,10000) L_0x1021390/d; +L_0x10213f0/d .functor AND 1, L_0x1021ac0, L_0x1021390, C4<1>, C4<1>; +L_0x10213f0 .delay (20000,20000,20000) L_0x10213f0/d; +L_0x101d230/d .functor AND 1, C4<0>, L_0x10222f0, C4<1>, C4<1>; +L_0x101d230 .delay (20000,20000,20000) L_0x101d230/d; +L_0x10218e0/d .functor OR 1, L_0x10213f0, L_0x101d230, C4<0>, C4<0>; +L_0x10218e0 .delay (20000,20000,20000) L_0x10218e0/d; +v0xfddcc0_0 .alias "S", 0 0, v0xfe4ea0_0; +v0xfddd60_0 .net "in0", 0 0, L_0x1021ac0; 1 drivers +v0xfddde0_0 .net "in1", 0 0, C4<0>; 1 drivers +v0xfdde80_0 .net "nS", 0 0, L_0x1021390; 1 drivers +v0xfddf00_0 .net "out0", 0 0, L_0x10213f0; 1 drivers +v0xfddfa0_0 .net "out1", 0 0, L_0x101d230; 1 drivers +v0xfde080_0 .net "outfinal", 0 0, L_0x10218e0; 1 drivers +S_0xfdd660 .scope module, "setSLTres3" "TwoInMux" 3 244, 3 8, S_0xfdd4d0; + .timescale -9 -12; +L_0x1021630/d .functor NOT 1, L_0x10222f0, C4<0>, C4<0>, C4<0>; +L_0x1021630 .delay (10000,10000,10000) L_0x1021630/d; +L_0x1021d60/d .functor AND 1, L_0x10220f0, L_0x1021630, C4<1>, C4<1>; +L_0x1021d60 .delay (20000,20000,20000) L_0x1021d60/d; +L_0x1021e70/d .functor AND 1, L_0x1021bb0, L_0x10222f0, C4<1>, C4<1>; +L_0x1021e70 .delay (20000,20000,20000) L_0x1021e70/d; +L_0x1021f10/d .functor OR 1, L_0x1021d60, L_0x1021e70, C4<0>, C4<0>; +L_0x1021f10 .delay (20000,20000,20000) L_0x1021f10/d; +v0xfdd750_0 .alias "S", 0 0, v0xfe4ea0_0; +v0xfdd7f0_0 .net "in0", 0 0, L_0x10220f0; 1 drivers +v0xfdd890_0 .net "in1", 0 0, L_0x1021bb0; 1 drivers +v0xfdd930_0 .net "nS", 0 0, L_0x1021630; 1 drivers +v0xfdd9b0_0 .net "out0", 0 0, L_0x1021d60; 1 drivers +v0xfdda50_0 .net "out1", 0 0, L_0x1021e70; 1 drivers +v0xfddb30_0 .net "outfinal", 0 0, L_0x1021f10; 1 drivers +S_0xfd84e0 .scope module, "trial" "AddSubSLT32" 3 328, 3 166, S_0xf6f800; + .timescale -9 -12; +P_0xfd85d8 .param/l "size" 3 180, +C4<0100>; +L_0x102ae70/d .functor OR 1, L_0x102b130, C4<0>, C4<0>, C4<0>; +L_0x102ae70 .delay (20000,20000,20000) L_0x102ae70/d; +L_0x1023db0/d .functor XOR 1, RS_0x7f9963cefd08, L_0x102b3a0, C4<0>, C4<0>; +L_0x1023db0 .delay (40000,40000,40000) L_0x1023db0/d; +v0xfdcbf0_0 .alias "A", 3 0, v0xffb8e0_0; +v0xfdcc90_0 .alias "AddSubSLTSum", 3 0, v0xffc3b0_0; +v0xfdcd30_0 .alias "B", 3 0, v0xffba90_0; +RS_0x7f9963cefc18 .resolv tri, L_0x10268f0, L_0x1027e10, L_0x1014a00, L_0x102abe0; +v0xfdcdb0_0 .net8 "CarryoutWire", 3 0, RS_0x7f9963cefc18; 4 drivers +v0xfdce30_0 .alias "Command", 2 0, v0xffbc20_0; +v0xfdceb0_0 .net *"_s40", 0 0, L_0x102b130; 1 drivers +v0xfdcf50_0 .net/s *"_s41", 0 0, C4<0>; 1 drivers +v0xfdcff0_0 .net *"_s44", 0 0, L_0x102b3a0; 1 drivers +v0xfdd0e0_0 .alias "carryin", 3 0, v0xffbed0_0; +v0xfdd180_0 .alias "carryout", 0 0, v0xffcb10_0; +v0xfdd220_0 .alias "overflow", 0 0, v0xffcc10_0; +v0xfdd2c0_0 .alias "subtract", 3 0, v0xffcc90_0; +L_0x10267e0 .part/pv L_0x1026330, 1, 1, 4; +L_0x10268f0 .part/pv L_0x1026680, 1, 1, 4; +L_0x10269e0 .part/pv L_0x1026060, 1, 1, 4; +L_0x1026ad0 .part v0xffc310_0, 1, 1; +L_0x1026b70 .part v0xffc560_0, 1, 1; +L_0x1026ca0 .part RS_0x7f9963cefc18, 0, 1; +L_0x1027d20 .part/pv L_0x1027870, 2, 1, 4; +L_0x1027e10 .part/pv L_0x1027bc0, 2, 1, 4; +L_0x1027f50 .part/pv L_0x10275a0, 2, 1, 4; +L_0x1028040 .part v0xffc310_0, 2, 1; +L_0x1028140 .part v0xffc560_0, 2, 1; +L_0x1028270 .part RS_0x7f9963cefc18, 1, 1; +L_0x10291f0 .part/pv L_0x1028d40, 3, 1, 4; +L_0x1014a00 .part/pv L_0x1029090, 3, 1, 4; +L_0x10294f0 .part/pv L_0x1028a70, 3, 1, 4; +L_0x10295e0 .part v0xffc310_0, 3, 1; +L_0x1007fa0 .part v0xffc560_0, 3, 1; +L_0x10081b0 .part RS_0x7f9963cefc18, 2, 1; +L_0x102aaf0 .part/pv L_0x102a660, 0, 1, 4; +L_0x102abe0 .part/pv L_0x102a9b0, 0, 1, 4; +L_0x1008250 .part/pv L_0x102a390, 0, 1, 4; +L_0x102add0 .part v0xffc310_0, 0, 1; +L_0x102acd0 .part v0xffc560_0, 0, 1; +L_0x102afc0 .part RS_0x7f9963cefd68, 0, 1; +L_0x102b130 .part RS_0x7f9963cefc18, 3, 1; +L_0x102b3a0 .part RS_0x7f9963cefc18, 2, 1; +S_0xfdbbe0 .scope module, "attempt2" "MiddleAddSubSLT" 3 177, 3 88, S_0xfd84e0; + .timescale -9 -12; +L_0x101ee70/d .functor NOT 1, L_0x102acd0, C4<0>, C4<0>, C4<0>; +L_0x101ee70 .delay (10000,10000,10000) L_0x101ee70/d; +L_0x102a250/d .functor NOT 1, L_0x102a2f0, C4<0>, C4<0>, C4<0>; +L_0x102a250 .delay (10000,10000,10000) L_0x102a250/d; +L_0x102a390/d .functor AND 1, L_0x102a4d0, L_0x102a250, C4<1>, C4<1>; +L_0x102a390 .delay (20000,20000,20000) L_0x102a390/d; +L_0x102a570/d .functor XOR 1, L_0x102add0, L_0x102a020, C4<0>, C4<0>; +L_0x102a570 .delay (40000,40000,40000) L_0x102a570/d; +L_0x102a660/d .functor XOR 1, L_0x102a570, L_0x102afc0, C4<0>, C4<0>; +L_0x102a660 .delay (40000,40000,40000) L_0x102a660/d; +L_0x102a750/d .functor AND 1, L_0x102add0, L_0x102a020, C4<1>, C4<1>; +L_0x102a750 .delay (20000,20000,20000) L_0x102a750/d; +L_0x102a8c0/d .functor AND 1, L_0x102a570, L_0x102afc0, C4<1>, C4<1>; +L_0x102a8c0 .delay (20000,20000,20000) L_0x102a8c0/d; +L_0x102a9b0/d .functor OR 1, L_0x102a750, L_0x102a8c0, C4<0>, C4<0>; +L_0x102a9b0 .delay (20000,20000,20000) L_0x102a9b0/d; +v0xfdc250_0 .net "A", 0 0, L_0x102add0; 1 drivers +v0xfdc310_0 .net "AandB", 0 0, L_0x102a750; 1 drivers +v0xfdc3b0_0 .net "AddSubSLTSum", 0 0, L_0x102a660; 1 drivers +v0xfdc450_0 .net "AxorB", 0 0, L_0x102a570; 1 drivers +v0xfdc4d0_0 .net "B", 0 0, L_0x102acd0; 1 drivers +v0xfdc580_0 .net "BornB", 0 0, L_0x102a020; 1 drivers +v0xfdc640_0 .net "CINandAxorB", 0 0, L_0x102a8c0; 1 drivers +v0xfdc6c0_0 .alias "Command", 2 0, v0xffbc20_0; +v0xfdc740_0 .net *"_s3", 0 0, L_0x102a2f0; 1 drivers +v0xfdc7c0_0 .net *"_s5", 0 0, L_0x102a4d0; 1 drivers +v0xfdc860_0 .net "carryin", 0 0, L_0x102afc0; 1 drivers +v0xfdc900_0 .net "carryout", 0 0, L_0x102a9b0; 1 drivers +v0xfdc9a0_0 .net "nB", 0 0, L_0x101ee70; 1 drivers +v0xfdca50_0 .net "nCmd2", 0 0, L_0x102a250; 1 drivers +v0xfdcb50_0 .net "subtract", 0 0, L_0x102a390; 1 drivers +L_0x102a1b0 .part v0xffc5e0_0, 0, 1; +L_0x102a2f0 .part v0xffc5e0_0, 2, 1; +L_0x102a4d0 .part v0xffc5e0_0, 0, 1; +S_0xfdbcd0 .scope module, "mux0" "TwoInMux" 3 104, 3 8, S_0xfdbbe0; + .timescale -9 -12; +L_0x1007f10/d .functor NOT 1, L_0x102a1b0, C4<0>, C4<0>, C4<0>; +L_0x1007f10 .delay (10000,10000,10000) L_0x1007f10/d; +L_0x1008330/d .functor AND 1, L_0x102acd0, L_0x1007f10, C4<1>, C4<1>; +L_0x1008330 .delay (20000,20000,20000) L_0x1008330/d; +L_0x1029f30/d .functor AND 1, L_0x101ee70, L_0x102a1b0, C4<1>, C4<1>; +L_0x1029f30 .delay (20000,20000,20000) L_0x1029f30/d; +L_0x102a020/d .functor OR 1, L_0x1008330, L_0x1029f30, C4<0>, C4<0>; +L_0x102a020 .delay (20000,20000,20000) L_0x102a020/d; +v0xfdbdc0_0 .net "S", 0 0, L_0x102a1b0; 1 drivers +v0xfdbe80_0 .alias "in0", 0 0, v0xfdc4d0_0; +v0xfdbf20_0 .alias "in1", 0 0, v0xfdc9a0_0; +v0xfdbfc0_0 .net "nS", 0 0, L_0x1007f10; 1 drivers +v0xfdc070_0 .net "out0", 0 0, L_0x1008330; 1 drivers +v0xfdc110_0 .net "out1", 0 0, L_0x1029f30; 1 drivers +v0xfdc1b0_0 .alias "outfinal", 0 0, v0xfdc580_0; +S_0xfdaa40 .scope generate, "addbits[1]" "addbits[1]" 3 182, 3 182, S_0xfd84e0; + .timescale -9 -12; +P_0xfda458 .param/l "i" 3 182, +C4<01>; +S_0xfdabb0 .scope module, "attempt" "MiddleAddSubSLT" 3 184, 3 88, S_0xfdaa40; + .timescale -9 -12; +L_0x1024cd0/d .functor NOT 1, L_0x1026b70, C4<0>, C4<0>, C4<0>; +L_0x1024cd0 .delay (10000,10000,10000) L_0x1024cd0/d; +L_0x1025f00/d .functor NOT 1, L_0x1025fc0, C4<0>, C4<0>, C4<0>; +L_0x1025f00 .delay (10000,10000,10000) L_0x1025f00/d; +L_0x1026060/d .functor AND 1, L_0x10261a0, L_0x1025f00, C4<1>, C4<1>; +L_0x1026060 .delay (20000,20000,20000) L_0x1026060/d; +L_0x1026240/d .functor XOR 1, L_0x1026ad0, L_0x1025c90, C4<0>, C4<0>; +L_0x1026240 .delay (40000,40000,40000) L_0x1026240/d; +L_0x1026330/d .functor XOR 1, L_0x1026240, L_0x1026ca0, C4<0>, C4<0>; +L_0x1026330 .delay (40000,40000,40000) L_0x1026330/d; +L_0x1026420/d .functor AND 1, L_0x1026ad0, L_0x1025c90, C4<1>, C4<1>; +L_0x1026420 .delay (20000,20000,20000) L_0x1026420/d; +L_0x1026590/d .functor AND 1, L_0x1026240, L_0x1026ca0, C4<1>, C4<1>; +L_0x1026590 .delay (20000,20000,20000) L_0x1026590/d; +L_0x1026680/d .functor OR 1, L_0x1026420, L_0x1026590, C4<0>, C4<0>; +L_0x1026680 .delay (20000,20000,20000) L_0x1026680/d; +v0xfdb240_0 .net "A", 0 0, L_0x1026ad0; 1 drivers +v0xfdb300_0 .net "AandB", 0 0, L_0x1026420; 1 drivers +v0xfdb3a0_0 .net "AddSubSLTSum", 0 0, L_0x1026330; 1 drivers +v0xfdb440_0 .net "AxorB", 0 0, L_0x1026240; 1 drivers +v0xfdb4c0_0 .net "B", 0 0, L_0x1026b70; 1 drivers +v0xfdb570_0 .net "BornB", 0 0, L_0x1025c90; 1 drivers +v0xfdb630_0 .net "CINandAxorB", 0 0, L_0x1026590; 1 drivers +v0xfdb6b0_0 .alias "Command", 2 0, v0xffbc20_0; +v0xfdb730_0 .net *"_s3", 0 0, L_0x1025fc0; 1 drivers +v0xfdb7b0_0 .net *"_s5", 0 0, L_0x10261a0; 1 drivers +v0xfdb850_0 .net "carryin", 0 0, L_0x1026ca0; 1 drivers +v0xfdb8f0_0 .net "carryout", 0 0, L_0x1026680; 1 drivers +v0xfdb990_0 .net "nB", 0 0, L_0x1024cd0; 1 drivers +v0xfdba40_0 .net "nCmd2", 0 0, L_0x1025f00; 1 drivers +v0xfdbb40_0 .net "subtract", 0 0, L_0x1026060; 1 drivers +L_0x1025e60 .part v0xffc5e0_0, 0, 1; +L_0x1025fc0 .part v0xffc5e0_0, 2, 1; +L_0x10261a0 .part v0xffc5e0_0, 0, 1; +S_0xfdaca0 .scope module, "mux0" "TwoInMux" 3 104, 3 8, S_0xfdabb0; + .timescale -9 -12; +L_0x10259b0/d .functor NOT 1, L_0x1025e60, C4<0>, C4<0>, C4<0>; +L_0x10259b0 .delay (10000,10000,10000) L_0x10259b0/d; +L_0x1025a70/d .functor AND 1, L_0x1026b70, L_0x10259b0, C4<1>, C4<1>; +L_0x1025a70 .delay (20000,20000,20000) L_0x1025a70/d; +L_0x1025b80/d .functor AND 1, L_0x1024cd0, L_0x1025e60, C4<1>, C4<1>; +L_0x1025b80 .delay (20000,20000,20000) L_0x1025b80/d; +L_0x1025c90/d .functor OR 1, L_0x1025a70, L_0x1025b80, C4<0>, C4<0>; +L_0x1025c90 .delay (20000,20000,20000) L_0x1025c90/d; +v0xfdad90_0 .net "S", 0 0, L_0x1025e60; 1 drivers +v0xfdae30_0 .alias "in0", 0 0, v0xfdb4c0_0; +v0xfdaed0_0 .alias "in1", 0 0, v0xfdb990_0; +v0xfdaf70_0 .net "nS", 0 0, L_0x10259b0; 1 drivers +v0xfdb020_0 .net "out0", 0 0, L_0x1025a70; 1 drivers +v0xfdb0c0_0 .net "out1", 0 0, L_0x1025b80; 1 drivers +v0xfdb1a0_0 .alias "outfinal", 0 0, v0xfdb570_0; +S_0xfd98a0 .scope generate, "addbits[2]" "addbits[2]" 3 182, 3 182, S_0xfd84e0; + .timescale -9 -12; +P_0xfd91e8 .param/l "i" 3 182, +C4<010>; +S_0xfd9a10 .scope module, "attempt" "MiddleAddSubSLT" 3 184, 3 88, S_0xfd98a0; + .timescale -9 -12; +L_0x1026d40/d .functor NOT 1, L_0x1028140, C4<0>, C4<0>, C4<0>; +L_0x1026d40 .delay (10000,10000,10000) L_0x1026d40/d; +L_0x1027440/d .functor NOT 1, L_0x1027500, C4<0>, C4<0>, C4<0>; +L_0x1027440 .delay (10000,10000,10000) L_0x1027440/d; +L_0x10275a0/d .functor AND 1, L_0x10276e0, L_0x1027440, C4<1>, C4<1>; +L_0x10275a0 .delay (20000,20000,20000) L_0x10275a0/d; +L_0x1027780/d .functor XOR 1, L_0x1028040, L_0x10271d0, C4<0>, C4<0>; +L_0x1027780 .delay (40000,40000,40000) L_0x1027780/d; +L_0x1027870/d .functor XOR 1, L_0x1027780, L_0x1028270, C4<0>, C4<0>; +L_0x1027870 .delay (40000,40000,40000) L_0x1027870/d; +L_0x1027960/d .functor AND 1, L_0x1028040, L_0x10271d0, C4<1>, C4<1>; +L_0x1027960 .delay (20000,20000,20000) L_0x1027960/d; +L_0x1027ad0/d .functor AND 1, L_0x1027780, L_0x1028270, C4<1>, C4<1>; +L_0x1027ad0 .delay (20000,20000,20000) L_0x1027ad0/d; +L_0x1027bc0/d .functor OR 1, L_0x1027960, L_0x1027ad0, C4<0>, C4<0>; +L_0x1027bc0 .delay (20000,20000,20000) L_0x1027bc0/d; +v0xfda0a0_0 .net "A", 0 0, L_0x1028040; 1 drivers +v0xfda160_0 .net "AandB", 0 0, L_0x1027960; 1 drivers +v0xfda200_0 .net "AddSubSLTSum", 0 0, L_0x1027870; 1 drivers +v0xfda2a0_0 .net "AxorB", 0 0, L_0x1027780; 1 drivers +v0xfda320_0 .net "B", 0 0, L_0x1028140; 1 drivers +v0xfda3d0_0 .net "BornB", 0 0, L_0x10271d0; 1 drivers +v0xfda490_0 .net "CINandAxorB", 0 0, L_0x1027ad0; 1 drivers +v0xfda510_0 .alias "Command", 2 0, v0xffbc20_0; +v0xfda590_0 .net *"_s3", 0 0, L_0x1027500; 1 drivers +v0xfda610_0 .net *"_s5", 0 0, L_0x10276e0; 1 drivers +v0xfda6b0_0 .net "carryin", 0 0, L_0x1028270; 1 drivers +v0xfda750_0 .net "carryout", 0 0, L_0x1027bc0; 1 drivers +v0xfda7f0_0 .net "nB", 0 0, L_0x1026d40; 1 drivers +v0xfda8a0_0 .net "nCmd2", 0 0, L_0x1027440; 1 drivers +v0xfda9a0_0 .net "subtract", 0 0, L_0x10275a0; 1 drivers +L_0x10273a0 .part v0xffc5e0_0, 0, 1; +L_0x1027500 .part v0xffc5e0_0, 2, 1; +L_0x10276e0 .part v0xffc5e0_0, 0, 1; +S_0xfd9b00 .scope module, "mux0" "TwoInMux" 3 104, 3 8, S_0xfd9a10; + .timescale -9 -12; +L_0x1026ef0/d .functor NOT 1, L_0x10273a0, C4<0>, C4<0>, C4<0>; +L_0x1026ef0 .delay (10000,10000,10000) L_0x1026ef0/d; +L_0x1026fb0/d .functor AND 1, L_0x1028140, L_0x1026ef0, C4<1>, C4<1>; +L_0x1026fb0 .delay (20000,20000,20000) L_0x1026fb0/d; +L_0x10270c0/d .functor AND 1, L_0x1026d40, L_0x10273a0, C4<1>, C4<1>; +L_0x10270c0 .delay (20000,20000,20000) L_0x10270c0/d; +L_0x10271d0/d .functor OR 1, L_0x1026fb0, L_0x10270c0, C4<0>, C4<0>; +L_0x10271d0 .delay (20000,20000,20000) L_0x10271d0/d; +v0xfd9bf0_0 .net "S", 0 0, L_0x10273a0; 1 drivers +v0xfd9c90_0 .alias "in0", 0 0, v0xfda320_0; +v0xfd9d30_0 .alias "in1", 0 0, v0xfda7f0_0; +v0xfd9dd0_0 .net "nS", 0 0, L_0x1026ef0; 1 drivers +v0xfd9e80_0 .net "out0", 0 0, L_0x1026fb0; 1 drivers +v0xfd9f20_0 .net "out1", 0 0, L_0x10270c0; 1 drivers +v0xfda000_0 .alias "outfinal", 0 0, v0xfda3d0_0; +S_0xfd8650 .scope generate, "addbits[3]" "addbits[3]" 3 182, 3 182, S_0xfd84e0; + .timescale -9 -12; +P_0xfd8748 .param/l "i" 3 182, +C4<011>; +S_0xfd87c0 .scope module, "attempt" "MiddleAddSubSLT" 3 184, 3 88, S_0xfd8650; + .timescale -9 -12; +L_0x10280e0/d .functor NOT 1, L_0x1007fa0, C4<0>, C4<0>, C4<0>; +L_0x10280e0 .delay (10000,10000,10000) L_0x10280e0/d; +L_0x1028910/d .functor NOT 1, L_0x10289d0, C4<0>, C4<0>, C4<0>; +L_0x1028910 .delay (10000,10000,10000) L_0x1028910/d; +L_0x1028a70/d .functor AND 1, L_0x1028bb0, L_0x1028910, C4<1>, C4<1>; +L_0x1028a70 .delay (20000,20000,20000) L_0x1028a70/d; +L_0x1028c50/d .functor XOR 1, L_0x10295e0, L_0x10286a0, C4<0>, C4<0>; +L_0x1028c50 .delay (40000,40000,40000) L_0x1028c50/d; +L_0x1028d40/d .functor XOR 1, L_0x1028c50, L_0x10081b0, C4<0>, C4<0>; +L_0x1028d40 .delay (40000,40000,40000) L_0x1028d40/d; +L_0x1028e30/d .functor AND 1, L_0x10295e0, L_0x10286a0, C4<1>, C4<1>; +L_0x1028e30 .delay (20000,20000,20000) L_0x1028e30/d; +L_0x1028fa0/d .functor AND 1, L_0x1028c50, L_0x10081b0, C4<1>, C4<1>; +L_0x1028fa0 .delay (20000,20000,20000) L_0x1028fa0/d; +L_0x1029090/d .functor OR 1, L_0x1028e30, L_0x1028fa0, C4<0>, C4<0>; +L_0x1029090 .delay (20000,20000,20000) L_0x1029090/d; +v0xfd8e30_0 .net "A", 0 0, L_0x10295e0; 1 drivers +v0xfd8ef0_0 .net "AandB", 0 0, L_0x1028e30; 1 drivers +v0xfd8f90_0 .net "AddSubSLTSum", 0 0, L_0x1028d40; 1 drivers +v0xfd9030_0 .net "AxorB", 0 0, L_0x1028c50; 1 drivers +v0xfd90b0_0 .net "B", 0 0, L_0x1007fa0; 1 drivers +v0xfd9160_0 .net "BornB", 0 0, L_0x10286a0; 1 drivers +v0xfd9220_0 .net "CINandAxorB", 0 0, L_0x1028fa0; 1 drivers +v0xfd92a0_0 .alias "Command", 2 0, v0xffbc20_0; +v0xfd9320_0 .net *"_s3", 0 0, L_0x10289d0; 1 drivers +v0xfd93a0_0 .net *"_s5", 0 0, L_0x1028bb0; 1 drivers +v0xfd94a0_0 .net "carryin", 0 0, L_0x10081b0; 1 drivers +v0xfd9540_0 .net "carryout", 0 0, L_0x1029090; 1 drivers +v0xfd9650_0 .net "nB", 0 0, L_0x10280e0; 1 drivers +v0xfd9700_0 .net "nCmd2", 0 0, L_0x1028910; 1 drivers +v0xfd9800_0 .net "subtract", 0 0, L_0x1028a70; 1 drivers +L_0x1028870 .part v0xffc5e0_0, 0, 1; +L_0x10289d0 .part v0xffc5e0_0, 2, 1; +L_0x1028bb0 .part v0xffc5e0_0, 0, 1; +S_0xfd88b0 .scope module, "mux0" "TwoInMux" 3 104, 3 8, S_0xfd87c0; + .timescale -9 -12; +L_0x1028400/d .functor NOT 1, L_0x1028870, C4<0>, C4<0>, C4<0>; +L_0x1028400 .delay (10000,10000,10000) L_0x1028400/d; +L_0x1028480/d .functor AND 1, L_0x1007fa0, L_0x1028400, C4<1>, C4<1>; +L_0x1028480 .delay (20000,20000,20000) L_0x1028480/d; +L_0x1028590/d .functor AND 1, L_0x10280e0, L_0x1028870, C4<1>, C4<1>; +L_0x1028590 .delay (20000,20000,20000) L_0x1028590/d; +L_0x10286a0/d .functor OR 1, L_0x1028480, L_0x1028590, C4<0>, C4<0>; +L_0x10286a0 .delay (20000,20000,20000) L_0x10286a0/d; +v0xfd89a0_0 .net "S", 0 0, L_0x1028870; 1 drivers +v0xfd8a20_0 .alias "in0", 0 0, v0xfd90b0_0; +v0xfd8ac0_0 .alias "in1", 0 0, v0xfd9650_0; +v0xfd8b60_0 .net "nS", 0 0, L_0x1028400; 1 drivers +v0xfd8c10_0 .net "out0", 0 0, L_0x1028480; 1 drivers +v0xfd8cb0_0 .net "out1", 0 0, L_0x1028590; 1 drivers +v0xfd8d90_0 .alias "outfinal", 0 0, v0xfd9160_0; +S_0xfd52a0 .scope module, "trial1" "AndNand32" 3 329, 3 115, S_0xf6f800; + .timescale -9 -12; +P_0xfd4d28 .param/l "size" 3 122, +C4<0100>; +v0xfd5190_0 .alias "A", 3 0, v0xffb8e0_0; +v0xfd8300_0 .alias "AndNandOut", 3 0, v0xffc4b0_0; +v0xfd8380_0 .alias "B", 3 0, v0xffba90_0; +v0xfd8430_0 .alias "Command", 2 0, v0xffbc20_0; +L_0x102bbf0 .part/pv L_0x102b980, 1, 1, 4; +L_0x102bcb0 .part v0xffc310_0, 1, 1; +L_0x102bd50 .part v0xffc560_0, 1, 1; +L_0x102c660 .part/pv L_0x102c3f0, 2, 1, 4; +L_0x102c700 .part v0xffc310_0, 2, 1; +L_0x102c7a0 .part v0xffc560_0, 2, 1; +L_0x102d0d0 .part/pv L_0x102ce60, 3, 1, 4; +L_0x1015a10 .part v0xffc310_0, 3, 1; +L_0x102d380 .part v0xffc560_0, 3, 1; +L_0x102dc30 .part/pv L_0x102d9c0, 0, 1, 4; +L_0x102dd30 .part v0xffc310_0, 0, 1; +L_0x102ddd0 .part v0xffc560_0, 0, 1; +S_0xfd77c0 .scope module, "attempt2" "AndNand" 3 126, 3 48, S_0xfd52a0; + .timescale -9 -12; +L_0x102d470/d .functor NAND 1, L_0x102dd30, L_0x102ddd0, C4<1>, C4<1>; +L_0x102d470 .delay (10000,10000,10000) L_0x102d470/d; +L_0x102d570/d .functor NOT 1, L_0x102d470, C4<0>, C4<0>, C4<0>; +L_0x102d570 .delay (10000,10000,10000) L_0x102d570/d; +v0xfd7de0_0 .net "A", 0 0, L_0x102dd30; 1 drivers +v0xfd7ea0_0 .net "AandB", 0 0, L_0x102d570; 1 drivers +v0xfd7f20_0 .net "AnandB", 0 0, L_0x102d470; 1 drivers +v0xfd7fd0_0 .net "AndNandOut", 0 0, L_0x102d9c0; 1 drivers +v0xfd80b0_0 .net "B", 0 0, L_0x102ddd0; 1 drivers +v0xfd8130_0 .alias "Command", 2 0, v0xffbc20_0; +L_0x102db90 .part v0xffc5e0_0, 0, 1; +S_0xfd78b0 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0xfd77c0; + .timescale -9 -12; +L_0x102d6a0/d .functor NOT 1, L_0x102db90, C4<0>, C4<0>, C4<0>; +L_0x102d6a0 .delay (10000,10000,10000) L_0x102d6a0/d; +L_0x102d760/d .functor AND 1, L_0x102d570, L_0x102d6a0, C4<1>, C4<1>; +L_0x102d760 .delay (20000,20000,20000) L_0x102d760/d; +L_0x102d870/d .functor AND 1, L_0x102d470, L_0x102db90, C4<1>, C4<1>; +L_0x102d870 .delay (20000,20000,20000) L_0x102d870/d; +L_0x102d9c0/d .functor OR 1, L_0x102d760, L_0x102d870, C4<0>, C4<0>; +L_0x102d9c0 .delay (20000,20000,20000) L_0x102d9c0/d; +v0xfd79a0_0 .net "S", 0 0, L_0x102db90; 1 drivers +v0xfd7a20_0 .alias "in0", 0 0, v0xfd7ea0_0; +v0xfd7aa0_0 .alias "in1", 0 0, v0xfd7f20_0; +v0xfd7b40_0 .net "nS", 0 0, L_0x102d6a0; 1 drivers +v0xfd7bc0_0 .net "out0", 0 0, L_0x102d760; 1 drivers +v0xfd7c60_0 .net "out1", 0 0, L_0x102d870; 1 drivers +v0xfd7d40_0 .alias "outfinal", 0 0, v0xfd7fd0_0; +S_0xfd6c00 .scope generate, "andbits[1]" "andbits[1]" 3 130, 3 130, S_0xfd52a0; + .timescale -9 -12; +P_0xfd6cf8 .param/l "i" 3 130, +C4<01>; +S_0xfd6d70 .scope module, "attempt" "AndNand" 3 132, 3 48, S_0xfd6c00; + .timescale -9 -12; +L_0x102b060/d .functor NAND 1, L_0x102bcb0, L_0x102bd50, C4<1>, C4<1>; +L_0x102b060 .delay (10000,10000,10000) L_0x102b060/d; +L_0x102b5b0/d .functor NOT 1, L_0x102b060, C4<0>, C4<0>, C4<0>; +L_0x102b5b0 .delay (10000,10000,10000) L_0x102b5b0/d; +v0xfd73b0_0 .net "A", 0 0, L_0x102bcb0; 1 drivers +v0xfd7470_0 .net "AandB", 0 0, L_0x102b5b0; 1 drivers +v0xfd74f0_0 .net "AnandB", 0 0, L_0x102b060; 1 drivers +v0xfd75a0_0 .net "AndNandOut", 0 0, L_0x102b980; 1 drivers +v0xfd7680_0 .net "B", 0 0, L_0x102bd50; 1 drivers +v0xfd7700_0 .alias "Command", 2 0, v0xffbc20_0; +L_0x102bb50 .part v0xffc5e0_0, 0, 1; +S_0xfd6e60 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0xfd6d70; + .timescale -9 -12; +L_0x102b6a0/d .functor NOT 1, L_0x102bb50, C4<0>, C4<0>, C4<0>; +L_0x102b6a0 .delay (10000,10000,10000) L_0x102b6a0/d; +L_0x102b740/d .functor AND 1, L_0x102b5b0, L_0x102b6a0, C4<1>, C4<1>; +L_0x102b740 .delay (20000,20000,20000) L_0x102b740/d; +L_0x102b830/d .functor AND 1, L_0x102b060, L_0x102bb50, C4<1>, C4<1>; +L_0x102b830 .delay (20000,20000,20000) L_0x102b830/d; +L_0x102b980/d .functor OR 1, L_0x102b740, L_0x102b830, C4<0>, C4<0>; +L_0x102b980 .delay (20000,20000,20000) L_0x102b980/d; +v0xfd6f50_0 .net "S", 0 0, L_0x102bb50; 1 drivers +v0xfd6fd0_0 .alias "in0", 0 0, v0xfd7470_0; +v0xfd7070_0 .alias "in1", 0 0, v0xfd74f0_0; +v0xfd7110_0 .net "nS", 0 0, L_0x102b6a0; 1 drivers +v0xfd7190_0 .net "out0", 0 0, L_0x102b740; 1 drivers +v0xfd7230_0 .net "out1", 0 0, L_0x102b830; 1 drivers +v0xfd7310_0 .alias "outfinal", 0 0, v0xfd75a0_0; +S_0xfd6040 .scope generate, "andbits[2]" "andbits[2]" 3 130, 3 130, S_0xfd52a0; + .timescale -9 -12; +P_0xfd6138 .param/l "i" 3 130, +C4<010>; +S_0xfd61b0 .scope module, "attempt" "AndNand" 3 132, 3 48, S_0xfd6040; + .timescale -9 -12; +L_0x102be40/d .functor NAND 1, L_0x102c700, L_0x102c7a0, C4<1>, C4<1>; +L_0x102be40 .delay (10000,10000,10000) L_0x102be40/d; +L_0x102bfa0/d .functor NOT 1, L_0x102be40, C4<0>, C4<0>, C4<0>; +L_0x102bfa0 .delay (10000,10000,10000) L_0x102bfa0/d; +v0xfd67f0_0 .net "A", 0 0, L_0x102c700; 1 drivers +v0xfd68b0_0 .net "AandB", 0 0, L_0x102bfa0; 1 drivers +v0xfd6930_0 .net "AnandB", 0 0, L_0x102be40; 1 drivers +v0xfd69e0_0 .net "AndNandOut", 0 0, L_0x102c3f0; 1 drivers +v0xfd6ac0_0 .net "B", 0 0, L_0x102c7a0; 1 drivers +v0xfd6b40_0 .alias "Command", 2 0, v0xffbc20_0; +L_0x102c5c0 .part v0xffc5e0_0, 0, 1; +S_0xfd62a0 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0xfd61b0; + .timescale -9 -12; +L_0x102c0d0/d .functor NOT 1, L_0x102c5c0, C4<0>, C4<0>, C4<0>; +L_0x102c0d0 .delay (10000,10000,10000) L_0x102c0d0/d; +L_0x102c190/d .functor AND 1, L_0x102bfa0, L_0x102c0d0, C4<1>, C4<1>; +L_0x102c190 .delay (20000,20000,20000) L_0x102c190/d; +L_0x102c2a0/d .functor AND 1, L_0x102be40, L_0x102c5c0, C4<1>, C4<1>; +L_0x102c2a0 .delay (20000,20000,20000) L_0x102c2a0/d; +L_0x102c3f0/d .functor OR 1, L_0x102c190, L_0x102c2a0, C4<0>, C4<0>; +L_0x102c3f0 .delay (20000,20000,20000) L_0x102c3f0/d; +v0xfd6390_0 .net "S", 0 0, L_0x102c5c0; 1 drivers +v0xfd6410_0 .alias "in0", 0 0, v0xfd68b0_0; +v0xfd64b0_0 .alias "in1", 0 0, v0xfd6930_0; +v0xfd6550_0 .net "nS", 0 0, L_0x102c0d0; 1 drivers +v0xfd65d0_0 .net "out0", 0 0, L_0x102c190; 1 drivers +v0xfd6670_0 .net "out1", 0 0, L_0x102c2a0; 1 drivers +v0xfd6750_0 .alias "outfinal", 0 0, v0xfd69e0_0; +S_0xfd5410 .scope generate, "andbits[3]" "andbits[3]" 3 130, 3 130, S_0xfd52a0; + .timescale -9 -12; +P_0xfd5508 .param/l "i" 3 130, +C4<011>; +S_0xfd55a0 .scope module, "attempt" "AndNand" 3 132, 3 48, S_0xfd5410; + .timescale -9 -12; +L_0x102c8d0/d .functor NAND 1, L_0x1015a10, L_0x102d380, C4<1>, C4<1>; +L_0x102c8d0 .delay (10000,10000,10000) L_0x102c8d0/d; +L_0x102ca10/d .functor NOT 1, L_0x102c8d0, C4<0>, C4<0>, C4<0>; +L_0x102ca10 .delay (10000,10000,10000) L_0x102ca10/d; +v0xfd5c30_0 .net "A", 0 0, L_0x1015a10; 1 drivers +v0xfd5cf0_0 .net "AandB", 0 0, L_0x102ca10; 1 drivers +v0xfd5d70_0 .net "AnandB", 0 0, L_0x102c8d0; 1 drivers +v0xfd5e20_0 .net "AndNandOut", 0 0, L_0x102ce60; 1 drivers +v0xfd5f00_0 .net "B", 0 0, L_0x102d380; 1 drivers +v0xfd5f80_0 .alias "Command", 2 0, v0xffbc20_0; +L_0x102d030 .part v0xffc5e0_0, 0, 1; +S_0xfd5690 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0xfd55a0; + .timescale -9 -12; +L_0x102cb40/d .functor NOT 1, L_0x102d030, C4<0>, C4<0>, C4<0>; +L_0x102cb40 .delay (10000,10000,10000) L_0x102cb40/d; +L_0x102cc00/d .functor AND 1, L_0x102ca10, L_0x102cb40, C4<1>, C4<1>; +L_0x102cc00 .delay (20000,20000,20000) L_0x102cc00/d; +L_0x102cd10/d .functor AND 1, L_0x102c8d0, L_0x102d030, C4<1>, C4<1>; +L_0x102cd10 .delay (20000,20000,20000) L_0x102cd10/d; +L_0x102ce60/d .functor OR 1, L_0x102cc00, L_0x102cd10, C4<0>, C4<0>; +L_0x102ce60 .delay (20000,20000,20000) L_0x102ce60/d; +v0xfd5780_0 .net "S", 0 0, L_0x102d030; 1 drivers +v0xfd5820_0 .alias "in0", 0 0, v0xfd5cf0_0; +v0xfd58c0_0 .alias "in1", 0 0, v0xfd5d70_0; +v0xfd5960_0 .net "nS", 0 0, L_0x102cb40; 1 drivers +v0xfd5a10_0 .net "out0", 0 0, L_0x102cc00; 1 drivers +v0xfd5ab0_0 .net "out1", 0 0, L_0x102cd10; 1 drivers +v0xfd5b90_0 .alias "outfinal", 0 0, v0xfd5e20_0; +S_0xfd0080 .scope module, "trial2" "OrNorXor32" 3 330, 3 138, S_0xf6f800; + .timescale -9 -12; +P_0xfcf1d8 .param/l "size" 3 145, +C4<0100>; +v0xfd5010_0 .alias "A", 3 0, v0xffb8e0_0; +v0xfd5090_0 .alias "B", 3 0, v0xffba90_0; +v0xfd5110_0 .alias "Command", 2 0, v0xffbc20_0; +v0xfd5220_0 .alias "OrNorXorOut", 3 0, v0xffc6e0_0; +L_0x1009490 .part/pv L_0x102ed80, 1, 1, 4; +L_0x1009530 .part v0xffc310_0, 1, 1; +L_0x10095d0 .part v0xffc560_0, 1, 1; +L_0x1030990 .part/pv L_0x1030760, 2, 1, 4; +L_0x1030a30 .part v0xffc310_0, 2, 1; +L_0x1030ad0 .part v0xffc560_0, 2, 1; +L_0x1031c50 .part/pv L_0x10319e0, 3, 1, 4; +L_0x1031cf0 .part v0xffc310_0, 3, 1; +L_0x1031d90 .part v0xffc560_0, 3, 1; +L_0x1032f40 .part/pv L_0x1032cd0, 0, 1, 4; +L_0x1033040 .part v0xffc310_0, 0, 1; +L_0x10330e0 .part v0xffc560_0, 0, 1; +S_0xfd3e00 .scope module, "attempt2" "OrNorXor" 3 153, 3 64, S_0xfd0080; + .timescale -9 -12; +L_0x1031e30/d .functor NOR 1, L_0x1033040, L_0x10330e0, C4<0>, C4<0>; +L_0x1031e30 .delay (10000,10000,10000) L_0x1031e30/d; +L_0x1031f30/d .functor NOT 1, L_0x1031e30, C4<0>, C4<0>, C4<0>; +L_0x1031f30 .delay (10000,10000,10000) L_0x1031f30/d; +L_0x1032060/d .functor NAND 1, L_0x1033040, L_0x10330e0, C4<1>, C4<1>; +L_0x1032060 .delay (10000,10000,10000) L_0x1032060/d; +L_0x10321c0/d .functor NAND 1, L_0x1032060, L_0x1031f30, C4<1>, C4<1>; +L_0x10321c0 .delay (10000,10000,10000) L_0x10321c0/d; +L_0x10322d0/d .functor NOT 1, L_0x10321c0, C4<0>, C4<0>, C4<0>; +L_0x10322d0 .delay (10000,10000,10000) L_0x10322d0/d; +v0xfd4950_0 .net "A", 0 0, L_0x1033040; 1 drivers +v0xfd49f0_0 .net "AnandB", 0 0, L_0x1032060; 1 drivers +v0xfd4a90_0 .net "AnorB", 0 0, L_0x1031e30; 1 drivers +v0xfd4b10_0 .net "AorB", 0 0, L_0x1031f30; 1 drivers +v0xfd4bf0_0 .net "AxorB", 0 0, L_0x10322d0; 1 drivers +v0xfd4ca0_0 .net "B", 0 0, L_0x10330e0; 1 drivers +v0xfd4d60_0 .alias "Command", 2 0, v0xffbc20_0; +v0xfd4de0_0 .net "OrNorXorOut", 0 0, L_0x1032cd0; 1 drivers +v0xfd4e60_0 .net "XorNor", 0 0, L_0x1032750; 1 drivers +v0xfd4f30_0 .net "nXor", 0 0, L_0x10321c0; 1 drivers +L_0x10328d0 .part v0xffc5e0_0, 2, 1; +L_0x1032ea0 .part v0xffc5e0_0, 0, 1; +S_0xfd43e0 .scope module, "mux0" "TwoInMux" 3 83, 3 8, S_0xfd3e00; + .timescale -9 -12; +L_0x1032430/d .functor NOT 1, L_0x10328d0, C4<0>, C4<0>, C4<0>; +L_0x1032430 .delay (10000,10000,10000) L_0x1032430/d; +L_0x10324f0/d .functor AND 1, L_0x10322d0, L_0x1032430, C4<1>, C4<1>; +L_0x10324f0 .delay (20000,20000,20000) L_0x10324f0/d; +L_0x1032600/d .functor AND 1, L_0x1031e30, L_0x10328d0, C4<1>, C4<1>; +L_0x1032600 .delay (20000,20000,20000) L_0x1032600/d; +L_0x1032750/d .functor OR 1, L_0x10324f0, L_0x1032600, C4<0>, C4<0>; +L_0x1032750 .delay (20000,20000,20000) L_0x1032750/d; +v0xfd44d0_0 .net "S", 0 0, L_0x10328d0; 1 drivers +v0xfd4590_0 .alias "in0", 0 0, v0xfd4bf0_0; +v0xfd4630_0 .alias "in1", 0 0, v0xfd4a90_0; +v0xfd46d0_0 .net "nS", 0 0, L_0x1032430; 1 drivers +v0xfd4750_0 .net "out0", 0 0, L_0x10324f0; 1 drivers +v0xfd47f0_0 .net "out1", 0 0, L_0x1032600; 1 drivers +v0xfd48d0_0 .alias "outfinal", 0 0, v0xfd4e60_0; +S_0xfd3ef0 .scope module, "mux1" "TwoInMux" 3 84, 3 8, S_0xfd3e00; + .timescale -9 -12; +L_0x1032970/d .functor NOT 1, L_0x1032ea0, C4<0>, C4<0>, C4<0>; +L_0x1032970 .delay (10000,10000,10000) L_0x1032970/d; +L_0x1032a30/d .functor AND 1, L_0x1032750, L_0x1032970, C4<1>, C4<1>; +L_0x1032a30 .delay (20000,20000,20000) L_0x1032a30/d; +L_0x1032b80/d .functor AND 1, L_0x1031f30, L_0x1032ea0, C4<1>, C4<1>; +L_0x1032b80 .delay (20000,20000,20000) L_0x1032b80/d; +L_0x1032cd0/d .functor OR 1, L_0x1032a30, L_0x1032b80, C4<0>, C4<0>; +L_0x1032cd0 .delay (20000,20000,20000) L_0x1032cd0/d; +v0xfd3fe0_0 .net "S", 0 0, L_0x1032ea0; 1 drivers +v0xfd4060_0 .alias "in0", 0 0, v0xfd4e60_0; +v0xfd40e0_0 .alias "in1", 0 0, v0xfd4b10_0; +v0xfd4180_0 .net "nS", 0 0, L_0x1032970; 1 drivers +v0xfd4200_0 .net "out0", 0 0, L_0x1032a30; 1 drivers +v0xfd42a0_0 .net "out1", 0 0, L_0x1032b80; 1 drivers +v0xfd4340_0 .alias "outfinal", 0 0, v0xfd4de0_0; +S_0xfd29e0 .scope generate, "orbits[1]" "orbits[1]" 3 157, 3 157, S_0xfd0080; + .timescale -9 -12; +P_0xfd2678 .param/l "i" 3 157, +C4<01>; +S_0xfd2b10 .scope module, "attempt" "OrNorXor" 3 159, 3 64, S_0xfd29e0; + .timescale -9 -12; +L_0x102dcd0/d .functor NOR 1, L_0x1009530, L_0x10095d0, C4<0>, C4<0>; +L_0x102dcd0 .delay (10000,10000,10000) L_0x102dcd0/d; +L_0x102dfe0/d .functor NOT 1, L_0x102dcd0, C4<0>, C4<0>, C4<0>; +L_0x102dfe0 .delay (10000,10000,10000) L_0x102dfe0/d; +L_0x102e110/d .functor NAND 1, L_0x1009530, L_0x10095d0, C4<1>, C4<1>; +L_0x102e110 .delay (10000,10000,10000) L_0x102e110/d; +L_0x102e270/d .functor NAND 1, L_0x102e110, L_0x102dfe0, C4<1>, C4<1>; +L_0x102e270 .delay (10000,10000,10000) L_0x102e270/d; +L_0x102e380/d .functor NOT 1, L_0x102e270, C4<0>, C4<0>, C4<0>; +L_0x102e380 .delay (10000,10000,10000) L_0x102e380/d; +v0xfd36c0_0 .net "A", 0 0, L_0x1009530; 1 drivers +v0xfd3760_0 .net "AnandB", 0 0, L_0x102e110; 1 drivers +v0xfd3800_0 .net "AnorB", 0 0, L_0x102dcd0; 1 drivers +v0xfd38b0_0 .net "AorB", 0 0, L_0x102dfe0; 1 drivers +v0xfd3990_0 .net "AxorB", 0 0, L_0x102e380; 1 drivers +v0xfd3a40_0 .net "B", 0 0, L_0x10095d0; 1 drivers +v0xfd3b00_0 .alias "Command", 2 0, v0xffbc20_0; +v0xfd3b80_0 .net "OrNorXorOut", 0 0, L_0x102ed80; 1 drivers +v0xfd3c50_0 .net "XorNor", 0 0, L_0x102e800; 1 drivers +v0xfd3d20_0 .net "nXor", 0 0, L_0x102e270; 1 drivers +L_0x102e980 .part v0xffc5e0_0, 2, 1; +L_0x102ef50 .part v0xffc5e0_0, 0, 1; +S_0xfd3150 .scope module, "mux0" "TwoInMux" 3 83, 3 8, S_0xfd2b10; + .timescale -9 -12; +L_0x102e4e0/d .functor NOT 1, L_0x102e980, C4<0>, C4<0>, C4<0>; +L_0x102e4e0 .delay (10000,10000,10000) L_0x102e4e0/d; +L_0x102e5a0/d .functor AND 1, L_0x102e380, L_0x102e4e0, C4<1>, C4<1>; +L_0x102e5a0 .delay (20000,20000,20000) L_0x102e5a0/d; +L_0x102e6b0/d .functor AND 1, L_0x102dcd0, L_0x102e980, C4<1>, C4<1>; +L_0x102e6b0 .delay (20000,20000,20000) L_0x102e6b0/d; +L_0x102e800/d .functor OR 1, L_0x102e5a0, L_0x102e6b0, C4<0>, C4<0>; +L_0x102e800 .delay (20000,20000,20000) L_0x102e800/d; +v0xfd3240_0 .net "S", 0 0, L_0x102e980; 1 drivers +v0xfd3300_0 .alias "in0", 0 0, v0xfd3990_0; +v0xfd33a0_0 .alias "in1", 0 0, v0xfd3800_0; +v0xfd3440_0 .net "nS", 0 0, L_0x102e4e0; 1 drivers +v0xfd34c0_0 .net "out0", 0 0, L_0x102e5a0; 1 drivers +v0xfd3560_0 .net "out1", 0 0, L_0x102e6b0; 1 drivers +v0xfd3640_0 .alias "outfinal", 0 0, v0xfd3c50_0; +S_0xfd2c00 .scope module, "mux1" "TwoInMux" 3 84, 3 8, S_0xfd2b10; + .timescale -9 -12; +L_0x102ea20/d .functor NOT 1, L_0x102ef50, C4<0>, C4<0>, C4<0>; +L_0x102ea20 .delay (10000,10000,10000) L_0x102ea20/d; +L_0x102eae0/d .functor AND 1, L_0x102e800, L_0x102ea20, C4<1>, C4<1>; +L_0x102eae0 .delay (20000,20000,20000) L_0x102eae0/d; +L_0x102ec30/d .functor AND 1, L_0x102dfe0, L_0x102ef50, C4<1>, C4<1>; +L_0x102ec30 .delay (20000,20000,20000) L_0x102ec30/d; +L_0x102ed80/d .functor OR 1, L_0x102eae0, L_0x102ec30, C4<0>, C4<0>; +L_0x102ed80 .delay (20000,20000,20000) L_0x102ed80/d; +v0xfd2cf0_0 .net "S", 0 0, L_0x102ef50; 1 drivers +v0xfd2d70_0 .alias "in0", 0 0, v0xfd3c50_0; +v0xfd2e10_0 .alias "in1", 0 0, v0xfd38b0_0; +v0xfd2eb0_0 .net "nS", 0 0, L_0x102ea20; 1 drivers +v0xfd2f30_0 .net "out0", 0 0, L_0x102eae0; 1 drivers +v0xfd2fd0_0 .net "out1", 0 0, L_0x102ec30; 1 drivers +v0xfd30b0_0 .alias "outfinal", 0 0, v0xfd3b80_0; +S_0xfd15e0 .scope generate, "orbits[2]" "orbits[2]" 3 157, 3 157, S_0xfd0080; + .timescale -9 -12; +P_0xfd1358 .param/l "i" 3 157, +C4<010>; +S_0xfd1710 .scope module, "attempt" "OrNorXor" 3 159, 3 64, S_0xfd15e0; + .timescale -9 -12; +L_0x1009670/d .functor NOR 1, L_0x1030a30, L_0x1030ad0, C4<0>, C4<0>; +L_0x1009670 .delay (10000,10000,10000) L_0x1009670/d; +L_0x1009780/d .functor NOT 1, L_0x1009670, C4<0>, C4<0>, C4<0>; +L_0x1009780 .delay (10000,10000,10000) L_0x1009780/d; +L_0x10098b0/d .functor NAND 1, L_0x1030a30, L_0x1030ad0, C4<1>, C4<1>; +L_0x10098b0 .delay (10000,10000,10000) L_0x10098b0/d; +L_0x1009a10/d .functor NAND 1, L_0x10098b0, L_0x1009780, C4<1>, C4<1>; +L_0x1009a10 .delay (10000,10000,10000) L_0x1009a10/d; +L_0x1009b20/d .functor NOT 1, L_0x1009a10, C4<0>, C4<0>, C4<0>; +L_0x1009b20 .delay (10000,10000,10000) L_0x1009b20/d; +v0xfd22a0_0 .net "A", 0 0, L_0x1030a30; 1 drivers +v0xfd2340_0 .net "AnandB", 0 0, L_0x10098b0; 1 drivers +v0xfd23e0_0 .net "AnorB", 0 0, L_0x1009670; 1 drivers +v0xfd2490_0 .net "AorB", 0 0, L_0x1009780; 1 drivers +v0xfd2540_0 .net "AxorB", 0 0, L_0x1009b20; 1 drivers +v0xfd25f0_0 .net "B", 0 0, L_0x1030ad0; 1 drivers +v0xfd26b0_0 .alias "Command", 2 0, v0xffbc20_0; +v0xfd2730_0 .net "OrNorXorOut", 0 0, L_0x1030760; 1 drivers +v0xfd2830_0 .net "XorNor", 0 0, L_0x1030280; 1 drivers +v0xfd2900_0 .net "nXor", 0 0, L_0x1009a10; 1 drivers +L_0x10303c0 .part v0xffc5e0_0, 2, 1; +L_0x10308f0 .part v0xffc5e0_0, 0, 1; +S_0xfd1d70 .scope module, "mux0" "TwoInMux" 3 83, 3 8, S_0xfd1710; + .timescale -9 -12; +L_0x1030000/d .functor NOT 1, L_0x10303c0, C4<0>, C4<0>, C4<0>; +L_0x1030000 .delay (10000,10000,10000) L_0x1030000/d; +L_0x1030060/d .functor AND 1, L_0x1009b20, L_0x1030000, C4<1>, C4<1>; +L_0x1030060 .delay (20000,20000,20000) L_0x1030060/d; +L_0x1030150/d .functor AND 1, L_0x1009670, L_0x10303c0, C4<1>, C4<1>; +L_0x1030150 .delay (20000,20000,20000) L_0x1030150/d; +L_0x1030280/d .functor OR 1, L_0x1030060, L_0x1030150, C4<0>, C4<0>; +L_0x1030280 .delay (20000,20000,20000) L_0x1030280/d; +v0xfd1e60_0 .net "S", 0 0, L_0x10303c0; 1 drivers +v0xfd1f20_0 .alias "in0", 0 0, v0xfd2540_0; +v0xfd1fc0_0 .alias "in1", 0 0, v0xfd23e0_0; +v0xfd2040_0 .net "nS", 0 0, L_0x1030000; 1 drivers +v0xfd20c0_0 .net "out0", 0 0, L_0x1030060; 1 drivers +v0xfd2140_0 .net "out1", 0 0, L_0x1030150; 1 drivers +v0xfd2220_0 .alias "outfinal", 0 0, v0xfd2830_0; +S_0xfd1800 .scope module, "mux1" "TwoInMux" 3 84, 3 8, S_0xfd1710; + .timescale -9 -12; +L_0x1030460/d .functor NOT 1, L_0x10308f0, C4<0>, C4<0>, C4<0>; +L_0x1030460 .delay (10000,10000,10000) L_0x1030460/d; +L_0x1030500/d .functor AND 1, L_0x1030280, L_0x1030460, C4<1>, C4<1>; +L_0x1030500 .delay (20000,20000,20000) L_0x1030500/d; +L_0x1030630/d .functor AND 1, L_0x1009780, L_0x10308f0, C4<1>, C4<1>; +L_0x1030630 .delay (20000,20000,20000) L_0x1030630/d; +L_0x1030760/d .functor OR 1, L_0x1030500, L_0x1030630, C4<0>, C4<0>; +L_0x1030760 .delay (20000,20000,20000) L_0x1030760/d; +v0xfd18f0_0 .net "S", 0 0, L_0x10308f0; 1 drivers +v0xfd1990_0 .alias "in0", 0 0, v0xfd2830_0; +v0xfd1a30_0 .alias "in1", 0 0, v0xfd2490_0; +v0xfd1ad0_0 .net "nS", 0 0, L_0x1030460; 1 drivers +v0xfd1b50_0 .net "out0", 0 0, L_0x1030500; 1 drivers +v0xfd1bf0_0 .net "out1", 0 0, L_0x1030630; 1 drivers +v0xfd1cd0_0 .alias "outfinal", 0 0, v0xfd2730_0; +S_0xfd01f0 .scope generate, "orbits[3]" "orbits[3]" 3 157, 3 157, S_0xfd0080; + .timescale -9 -12; +P_0xfd02e8 .param/l "i" 3 157, +C4<011>; +S_0xfd0380 .scope module, "attempt" "OrNorXor" 3 159, 3 64, S_0xfd01f0; + .timescale -9 -12; +L_0x1030bb0/d .functor NOR 1, L_0x1031cf0, L_0x1031d90, C4<0>, C4<0>; +L_0x1030bb0 .delay (10000,10000,10000) L_0x1030bb0/d; +L_0x1030ca0/d .functor NOT 1, L_0x1030bb0, C4<0>, C4<0>, C4<0>; +L_0x1030ca0 .delay (10000,10000,10000) L_0x1030ca0/d; +L_0x1030d90/d .functor NAND 1, L_0x1031cf0, L_0x1031d90, C4<1>, C4<1>; +L_0x1030d90 .delay (10000,10000,10000) L_0x1030d90/d; +L_0x1030ed0/d .functor NAND 1, L_0x1030d90, L_0x1030ca0, C4<1>, C4<1>; +L_0x1030ed0 .delay (10000,10000,10000) L_0x1030ed0/d; +L_0x1030fe0/d .functor NOT 1, L_0x1030ed0, C4<0>, C4<0>, C4<0>; +L_0x1030fe0 .delay (10000,10000,10000) L_0x1030fe0/d; +v0xfd0f50_0 .net "A", 0 0, L_0x1031cf0; 1 drivers +v0xfd0ff0_0 .net "AnandB", 0 0, L_0x1030d90; 1 drivers +v0xfd1090_0 .net "AnorB", 0 0, L_0x1030bb0; 1 drivers +v0xfd1140_0 .net "AorB", 0 0, L_0x1030ca0; 1 drivers +v0xfd1220_0 .net "AxorB", 0 0, L_0x1030fe0; 1 drivers +v0xfd12d0_0 .net "B", 0 0, L_0x1031d90; 1 drivers +v0xfd1390_0 .alias "Command", 2 0, v0xffbc20_0; +v0xfd1410_0 .net "OrNorXorOut", 0 0, L_0x10319e0; 1 drivers +v0xfd1490_0 .net "XorNor", 0 0, L_0x1031460; 1 drivers +v0xfd1560_0 .net "nXor", 0 0, L_0x1030ed0; 1 drivers +L_0x10315e0 .part v0xffc5e0_0, 2, 1; +L_0x1031bb0 .part v0xffc5e0_0, 0, 1; +S_0xfd09e0 .scope module, "mux0" "TwoInMux" 3 83, 3 8, S_0xfd0380; + .timescale -9 -12; +L_0x1031140/d .functor NOT 1, L_0x10315e0, C4<0>, C4<0>, C4<0>; +L_0x1031140 .delay (10000,10000,10000) L_0x1031140/d; +L_0x1031200/d .functor AND 1, L_0x1030fe0, L_0x1031140, C4<1>, C4<1>; +L_0x1031200 .delay (20000,20000,20000) L_0x1031200/d; +L_0x1031310/d .functor AND 1, L_0x1030bb0, L_0x10315e0, C4<1>, C4<1>; +L_0x1031310 .delay (20000,20000,20000) L_0x1031310/d; +L_0x1031460/d .functor OR 1, L_0x1031200, L_0x1031310, C4<0>, C4<0>; +L_0x1031460 .delay (20000,20000,20000) L_0x1031460/d; +v0xfd0ad0_0 .net "S", 0 0, L_0x10315e0; 1 drivers +v0xfd0b90_0 .alias "in0", 0 0, v0xfd1220_0; +v0xfd0c30_0 .alias "in1", 0 0, v0xfd1090_0; +v0xfd0cd0_0 .net "nS", 0 0, L_0x1031140; 1 drivers +v0xfd0d50_0 .net "out0", 0 0, L_0x1031200; 1 drivers +v0xfd0df0_0 .net "out1", 0 0, L_0x1031310; 1 drivers +v0xfd0ed0_0 .alias "outfinal", 0 0, v0xfd1490_0; +S_0xfd0470 .scope module, "mux1" "TwoInMux" 3 84, 3 8, S_0xfd0380; + .timescale -9 -12; +L_0x1031680/d .functor NOT 1, L_0x1031bb0, C4<0>, C4<0>, C4<0>; +L_0x1031680 .delay (10000,10000,10000) L_0x1031680/d; +L_0x1031740/d .functor AND 1, L_0x1031460, L_0x1031680, C4<1>, C4<1>; +L_0x1031740 .delay (20000,20000,20000) L_0x1031740/d; +L_0x1031890/d .functor AND 1, L_0x1030ca0, L_0x1031bb0, C4<1>, C4<1>; +L_0x1031890 .delay (20000,20000,20000) L_0x1031890/d; +L_0x10319e0/d .functor OR 1, L_0x1031740, L_0x1031890, C4<0>, C4<0>; +L_0x10319e0 .delay (20000,20000,20000) L_0x10319e0/d; +v0xfd0560_0 .net "S", 0 0, L_0x1031bb0; 1 drivers +v0xfd0600_0 .alias "in0", 0 0, v0xfd1490_0; +v0xfd06a0_0 .alias "in1", 0 0, v0xfd1140_0; +v0xfd0740_0 .net "nS", 0 0, L_0x1031680; 1 drivers +v0xfd07c0_0 .net "out0", 0 0, L_0x1031740; 1 drivers +v0xfd0860_0 .net "out1", 0 0, L_0x1031890; 1 drivers +v0xfd0940_0 .alias "outfinal", 0 0, v0xfd1410_0; +S_0xfcf700 .scope module, "ZeroMux0case" "FourInMux" 3 332, 3 24, S_0xf6f800; + .timescale -9 -12; +L_0x1032fe0/d .functor NOT 1, L_0x101bb40, C4<0>, C4<0>, C4<0>; +L_0x1032fe0 .delay (10000,10000,10000) L_0x1032fe0/d; +L_0x1033230/d .functor NOT 1, L_0x101bc70, C4<0>, C4<0>, C4<0>; +L_0x1033230 .delay (10000,10000,10000) L_0x1033230/d; +L_0x10332f0/d .functor NAND 1, L_0x1032fe0, L_0x1033230, L_0x1033ad0, C4<1>; +L_0x10332f0 .delay (10000,10000,10000) L_0x10332f0/d; +L_0x1033410/d .functor NAND 1, L_0x101bb40, L_0x1033230, L_0x1033b70, C4<1>; +L_0x1033410 .delay (10000,10000,10000) L_0x1033410/d; +L_0x1033560/d .functor NAND 1, L_0x1032fe0, L_0x101bc70, L_0x1033c10, C4<1>; +L_0x1033560 .delay (10000,10000,10000) L_0x1033560/d; +L_0x10336b0/d .functor NAND 1, L_0x101bb40, L_0x101bc70, L_0x1033ff0, C4<1>; +L_0x10336b0 .delay (10000,10000,10000) L_0x10336b0/d; +L_0x1033820/d .functor NAND 1, L_0x10332f0, L_0x1033410, L_0x1033560, L_0x10336b0; +L_0x1033820 .delay (10000,10000,10000) L_0x1033820/d; +v0xfcf7f0_0 .net "S0", 0 0, L_0x101bb40; 1 drivers +v0xfcf8b0_0 .net "S1", 0 0, L_0x101bc70; 1 drivers +v0xfcf950_0 .net "in0", 0 0, L_0x1033ad0; 1 drivers +v0xfcf9f0_0 .net "in1", 0 0, L_0x1033b70; 1 drivers +v0xfcfa70_0 .net "in2", 0 0, L_0x1033c10; 1 drivers +v0xfcfb10_0 .net "in3", 0 0, L_0x1033ff0; 1 drivers +v0xfcfbb0_0 .net "nS0", 0 0, L_0x1032fe0; 1 drivers +v0xfcfc50_0 .net "nS1", 0 0, L_0x1033230; 1 drivers +v0xfcfcf0_0 .net "out", 0 0, L_0x1033820; 1 drivers +v0xfcfd90_0 .net "out0", 0 0, L_0x10332f0; 1 drivers +v0xfcfe30_0 .net "out1", 0 0, L_0x1033410; 1 drivers +v0xfcfed0_0 .net "out2", 0 0, L_0x1033560; 1 drivers +v0xfcffe0_0 .net "out3", 0 0, L_0x10336b0; 1 drivers +S_0xfced40 .scope module, "OneMux0case" "FourInMux" 3 333, 3 24, S_0xf6f800; + .timescale -9 -12; +L_0x1033d70/d .functor NOT 1, L_0x1034990, C4<0>, C4<0>, C4<0>; +L_0x1033d70 .delay (10000,10000,10000) L_0x1033d70/d; +L_0x1033e60/d .functor NOT 1, L_0x10340e0, C4<0>, C4<0>, C4<0>; +L_0x1033e60 .delay (10000,10000,10000) L_0x1033e60/d; +L_0x1033f00/d .functor NAND 1, L_0x1033d70, L_0x1033e60, L_0x1034210, C4<1>; +L_0x1033f00 .delay (10000,10000,10000) L_0x1033f00/d; +L_0x10343c0/d .functor NAND 1, L_0x1034990, L_0x1033e60, L_0x1034d20, C4<1>; +L_0x10343c0 .delay (10000,10000,10000) L_0x10343c0/d; +L_0x10344b0/d .functor NAND 1, L_0x1033d70, L_0x10340e0, L_0x1034dc0, C4<1>; +L_0x10344b0 .delay (10000,10000,10000) L_0x10344b0/d; +L_0x10345a0/d .functor NAND 1, L_0x1034990, L_0x10340e0, L_0x1034ac0, C4<1>; +L_0x10345a0 .delay (10000,10000,10000) L_0x10345a0/d; +L_0x10346e0/d .functor NAND 1, L_0x1033f00, L_0x10343c0, L_0x10344b0, L_0x10345a0; +L_0x10346e0 .delay (10000,10000,10000) L_0x10346e0/d; +v0xfcee30_0 .net "S0", 0 0, L_0x1034990; 1 drivers +v0xfceef0_0 .net "S1", 0 0, L_0x10340e0; 1 drivers +v0xfcef90_0 .net "in0", 0 0, L_0x1034210; 1 drivers +v0xfcf030_0 .net "in1", 0 0, L_0x1034d20; 1 drivers +v0xfcf0b0_0 .net "in2", 0 0, L_0x1034dc0; 1 drivers +v0xfcf150_0 .net "in3", 0 0, L_0x1034ac0; 1 drivers +v0xfcf230_0 .net "nS0", 0 0, L_0x1033d70; 1 drivers +v0xfcf2d0_0 .net "nS1", 0 0, L_0x1033e60; 1 drivers +v0xfcf370_0 .net "out", 0 0, L_0x10346e0; 1 drivers +v0xfcf410_0 .net "out0", 0 0, L_0x1033f00; 1 drivers +v0xfcf4b0_0 .net "out1", 0 0, L_0x10343c0; 1 drivers +v0xfcf550_0 .net "out2", 0 0, L_0x10344b0; 1 drivers +v0xfcf660_0 .net "out3", 0 0, L_0x10345a0; 1 drivers +S_0xfce7f0 .scope module, "TwoMux0case" "TwoInMux" 3 334, 3 8, S_0xf6f800; + .timescale -9 -12; +L_0x1034bb0/d .functor NOT 1, L_0x1034e60, C4<0>, C4<0>, C4<0>; +L_0x1034bb0 .delay (10000,10000,10000) L_0x1034bb0/d; +L_0x1034ca0/d .functor AND 1, L_0x1034f00, L_0x1034bb0, C4<1>, C4<1>; +L_0x1034ca0 .delay (20000,20000,20000) L_0x1034ca0/d; +L_0x1035160/d .functor AND 1, L_0x1034ff0, L_0x1034e60, C4<1>, C4<1>; +L_0x1035160 .delay (20000,20000,20000) L_0x1035160/d; +L_0x1035250/d .functor OR 1, L_0x1034ca0, L_0x1035160, C4<0>, C4<0>; +L_0x1035250 .delay (20000,20000,20000) L_0x1035250/d; +v0xfce8e0_0 .net "S", 0 0, L_0x1034e60; 1 drivers +v0xfce9a0_0 .net "in0", 0 0, L_0x1034f00; 1 drivers +v0xfcea40_0 .net "in1", 0 0, L_0x1034ff0; 1 drivers +v0xfceae0_0 .net "nS", 0 0, L_0x1034bb0; 1 drivers +v0xfceb60_0 .net "out0", 0 0, L_0x1034ca0; 1 drivers +v0xfcec00_0 .net "out1", 0 0, L_0x1035160; 1 drivers +v0xfceca0_0 .net "outfinal", 0 0, L_0x1035250; 1 drivers +S_0xfccc70 .scope generate, "muxbits[1]" "muxbits[1]" 3 339, 3 339, S_0xf6f800; + .timescale -9 -12; +P_0xfcbc68 .param/l "i" 3 339, +C4<01>; +L_0x1016610/d .functor OR 1, L_0x1016710, L_0x10164d0, C4<0>, C4<0>; +L_0x1016610 .delay (20000,20000,20000) L_0x1016610/d; +v0xfce690_0 .net *"_s15", 0 0, L_0x1016710; 1 drivers +v0xfce750_0 .net *"_s16", 0 0, L_0x10164d0; 1 drivers +S_0xfcdd10 .scope module, "ZeroMux" "FourInMux" 3 341, 3 24, S_0xfccc70; + .timescale -9 -12; +L_0x1013d80/d .functor NOT 1, L_0x10146b0, C4<0>, C4<0>, C4<0>; +L_0x1013d80 .delay (10000,10000,10000) L_0x1013d80/d; +L_0x1013fd0/d .functor NOT 1, L_0x10147e0, C4<0>, C4<0>, C4<0>; +L_0x1013fd0 .delay (10000,10000,10000) L_0x1013fd0/d; +L_0x1014030/d .functor NAND 1, L_0x1013d80, L_0x1013fd0, L_0x1014910, C4<1>; +L_0x1014030 .delay (10000,10000,10000) L_0x1014030/d; +L_0x1014170/d .functor NAND 1, L_0x10146b0, L_0x1013fd0, L_0x1014ac0, C4<1>; +L_0x1014170 .delay (10000,10000,10000) L_0x1014170/d; +L_0x1014260/d .functor NAND 1, L_0x1013d80, L_0x10147e0, L_0x1014b60, C4<1>; +L_0x1014260 .delay (10000,10000,10000) L_0x1014260/d; +L_0x1014350/d .functor NAND 1, L_0x10146b0, L_0x10147e0, L_0x1014d10, C4<1>; +L_0x1014350 .delay (10000,10000,10000) L_0x1014350/d; +L_0x1014430/d .functor NAND 1, L_0x1014030, L_0x1014170, L_0x1014260, L_0x1014350; +L_0x1014430 .delay (10000,10000,10000) L_0x1014430/d; +v0xfcde00_0 .net "S0", 0 0, L_0x10146b0; 1 drivers +v0xfcdec0_0 .net "S1", 0 0, L_0x10147e0; 1 drivers +v0xfcdf60_0 .net "in0", 0 0, L_0x1014910; 1 drivers +v0xfce000_0 .net "in1", 0 0, L_0x1014ac0; 1 drivers +v0xfce080_0 .net "in2", 0 0, L_0x1014b60; 1 drivers +v0xfce120_0 .net "in3", 0 0, L_0x1014d10; 1 drivers +v0xfce1c0_0 .net "nS0", 0 0, L_0x1013d80; 1 drivers +v0xfce260_0 .net "nS1", 0 0, L_0x1013fd0; 1 drivers +v0xfce300_0 .net "out", 0 0, L_0x1014430; 1 drivers +v0xfce3a0_0 .net "out0", 0 0, L_0x1014030; 1 drivers +v0xfce440_0 .net "out1", 0 0, L_0x1014170; 1 drivers +v0xfce4e0_0 .net "out2", 0 0, L_0x1014260; 1 drivers +v0xfce5f0_0 .net "out3", 0 0, L_0x1014350; 1 drivers +S_0xfcd350 .scope module, "OneMux" "FourInMux" 3 342, 3 24, S_0xfccc70; + .timescale -9 -12; +L_0x1004660/d .functor NOT 1, L_0x10156b0, C4<0>, C4<0>, C4<0>; +L_0x1004660 .delay (10000,10000,10000) L_0x1004660/d; +L_0x1014f10/d .functor NOT 1, L_0x10157e0, C4<0>, C4<0>, C4<0>; +L_0x1014f10 .delay (10000,10000,10000) L_0x1014f10/d; +L_0x1014fb0/d .functor NAND 1, L_0x1004660, L_0x1014f10, L_0x1015970, C4<1>; +L_0x1014fb0 .delay (10000,10000,10000) L_0x1014fb0/d; +L_0x10150f0/d .functor NAND 1, L_0x10156b0, L_0x1014f10, L_0x1015b20, C4<1>; +L_0x10150f0 .delay (10000,10000,10000) L_0x10150f0/d; +L_0x10151e0/d .functor NAND 1, L_0x1004660, L_0x10157e0, L_0x1015bc0, C4<1>; +L_0x10151e0 .delay (10000,10000,10000) L_0x10151e0/d; +L_0x10152d0/d .functor NAND 1, L_0x10156b0, L_0x10157e0, L_0x1015c60, C4<1>; +L_0x10152d0 .delay (10000,10000,10000) L_0x10152d0/d; +L_0x10153b0/d .functor NAND 1, L_0x1014fb0, L_0x10150f0, L_0x10151e0, L_0x10152d0; +L_0x10153b0 .delay (10000,10000,10000) L_0x10153b0/d; +v0xfcd440_0 .net "S0", 0 0, L_0x10156b0; 1 drivers +v0xfcd500_0 .net "S1", 0 0, L_0x10157e0; 1 drivers +v0xfcd5a0_0 .net "in0", 0 0, L_0x1015970; 1 drivers +v0xfcd640_0 .net "in1", 0 0, L_0x1015b20; 1 drivers +v0xfcd6c0_0 .net "in2", 0 0, L_0x1015bc0; 1 drivers +v0xfcd760_0 .net "in3", 0 0, L_0x1015c60; 1 drivers +v0xfcd840_0 .net "nS0", 0 0, L_0x1004660; 1 drivers +v0xfcd8e0_0 .net "nS1", 0 0, L_0x1014f10; 1 drivers +v0xfcd980_0 .net "out", 0 0, L_0x10153b0; 1 drivers +v0xfcda20_0 .net "out0", 0 0, L_0x1014fb0; 1 drivers +v0xfcdac0_0 .net "out1", 0 0, L_0x10150f0; 1 drivers +v0xfcdb60_0 .net "out2", 0 0, L_0x10151e0; 1 drivers +v0xfcdc70_0 .net "out3", 0 0, L_0x10152d0; 1 drivers +S_0xfccde0 .scope module, "TwoMux" "TwoInMux" 3 343, 3 8, S_0xfccc70; + .timescale -9 -12; +L_0x1015910/d .functor NOT 1, L_0x10161b0, C4<0>, C4<0>, C4<0>; +L_0x1015910 .delay (10000,10000,10000) L_0x1015910/d; +L_0x1015da0/d .functor AND 1, L_0x1016250, L_0x1015910, C4<1>, C4<1>; +L_0x1015da0 .delay (20000,20000,20000) L_0x1015da0/d; +L_0x1015e90/d .functor AND 1, L_0x1016390, L_0x10161b0, C4<1>, C4<1>; +L_0x1015e90 .delay (20000,20000,20000) L_0x1015e90/d; +L_0x1015f80/d .functor OR 1, L_0x1015da0, L_0x1015e90, C4<0>, C4<0>; +L_0x1015f80 .delay (20000,20000,20000) L_0x1015f80/d; +v0xfcced0_0 .net "S", 0 0, L_0x10161b0; 1 drivers +v0xfccf70_0 .net "in0", 0 0, L_0x1016250; 1 drivers +v0xfcd010_0 .net "in1", 0 0, L_0x1016390; 1 drivers +v0xfcd0b0_0 .net "nS", 0 0, L_0x1015910; 1 drivers +v0xfcd130_0 .net "out0", 0 0, L_0x1015da0; 1 drivers +v0xfcd1d0_0 .net "out1", 0 0, L_0x1015e90; 1 drivers +v0xfcd2b0_0 .net "outfinal", 0 0, L_0x1015f80; 1 drivers +S_0xfcb0f0 .scope generate, "muxbits[2]" "muxbits[2]" 3 339, 3 339, S_0xf6f800; + .timescale -9 -12; +P_0xfca038 .param/l "i" 3 339, +C4<010>; +L_0x10185f0/d .functor OR 1, L_0x1018df0, L_0x1019170, C4<0>, C4<0>; +L_0x10185f0 .delay (20000,20000,20000) L_0x10185f0/d; +v0xfccb10_0 .net *"_s15", 0 0, L_0x1018df0; 1 drivers +v0xfccbd0_0 .net *"_s16", 0 0, L_0x1019170; 1 drivers +S_0xfcc190 .scope module, "ZeroMux" "FourInMux" 3 341, 3 24, S_0xfcb0f0; + .timescale -9 -12; +L_0x10168b0/d .functor NOT 1, L_0x10167b0, C4<0>, C4<0>, C4<0>; +L_0x10168b0 .delay (10000,10000,10000) L_0x10168b0/d; +L_0x10169a0/d .functor NOT 1, L_0x10172a0, C4<0>, C4<0>, C4<0>; +L_0x10169a0 .delay (10000,10000,10000) L_0x10169a0/d; +L_0x1016a40/d .functor NAND 1, L_0x10168b0, L_0x10169a0, L_0x1017150, C4<1>; +L_0x1016a40 .delay (10000,10000,10000) L_0x1016a40/d; +L_0x1016b80/d .functor NAND 1, L_0x10167b0, L_0x10169a0, L_0x10174a0, C4<1>; +L_0x1016b80 .delay (10000,10000,10000) L_0x1016b80/d; +L_0x1016c70/d .functor NAND 1, L_0x10168b0, L_0x10172a0, L_0x10173d0, C4<1>; +L_0x1016c70 .delay (10000,10000,10000) L_0x1016c70/d; +L_0x1016d60/d .functor NAND 1, L_0x10167b0, L_0x10172a0, L_0x1017670, C4<1>; +L_0x1016d60 .delay (10000,10000,10000) L_0x1016d60/d; +L_0x1016ea0/d .functor NAND 1, L_0x1016a40, L_0x1016b80, L_0x1016c70, L_0x1016d60; +L_0x1016ea0 .delay (10000,10000,10000) L_0x1016ea0/d; +v0xfcc280_0 .net "S0", 0 0, L_0x10167b0; 1 drivers +v0xfcc340_0 .net "S1", 0 0, L_0x10172a0; 1 drivers +v0xfcc3e0_0 .net "in0", 0 0, L_0x1017150; 1 drivers +v0xfcc480_0 .net "in1", 0 0, L_0x10174a0; 1 drivers +v0xfcc500_0 .net "in2", 0 0, L_0x10173d0; 1 drivers +v0xfcc5a0_0 .net "in3", 0 0, L_0x1017670; 1 drivers +v0xfcc640_0 .net "nS0", 0 0, L_0x10168b0; 1 drivers +v0xfcc6e0_0 .net "nS1", 0 0, L_0x10169a0; 1 drivers +v0xfcc780_0 .net "out", 0 0, L_0x1016ea0; 1 drivers +v0xfcc820_0 .net "out0", 0 0, L_0x1016a40; 1 drivers +v0xfcc8c0_0 .net "out1", 0 0, L_0x1016b80; 1 drivers +v0xfcc960_0 .net "out2", 0 0, L_0x1016c70; 1 drivers +v0xfcca70_0 .net "out3", 0 0, L_0x1016d60; 1 drivers +S_0xfcb7d0 .scope module, "OneMux" "FourInMux" 3 342, 3 24, S_0xfcb0f0; + .timescale -9 -12; +L_0x1017540/d .functor NOT 1, L_0x1018040, C4<0>, C4<0>, C4<0>; +L_0x1017540 .delay (10000,10000,10000) L_0x1017540/d; +L_0x10178a0/d .functor NOT 1, L_0x1017760, C4<0>, C4<0>, C4<0>; +L_0x10178a0 .delay (10000,10000,10000) L_0x10178a0/d; +L_0x1017900/d .functor NAND 1, L_0x1017540, L_0x10178a0, L_0x1018300, C4<1>; +L_0x1017900 .delay (10000,10000,10000) L_0x1017900/d; +L_0x1017a40/d .functor NAND 1, L_0x1018040, L_0x10178a0, L_0x1018170, C4<1>; +L_0x1017a40 .delay (10000,10000,10000) L_0x1017a40/d; +L_0x1017b30/d .functor NAND 1, L_0x1017540, L_0x1017760, L_0x10184b0, C4<1>; +L_0x1017b30 .delay (10000,10000,10000) L_0x1017b30/d; +L_0x1017c20/d .functor NAND 1, L_0x1018040, L_0x1017760, L_0x10183a0, C4<1>; +L_0x1017c20 .delay (10000,10000,10000) L_0x1017c20/d; +L_0x1017d90/d .functor NAND 1, L_0x1017900, L_0x1017a40, L_0x1017b30, L_0x1017c20; +L_0x1017d90 .delay (10000,10000,10000) L_0x1017d90/d; +v0xfcb8c0_0 .net "S0", 0 0, L_0x1018040; 1 drivers +v0xfcb980_0 .net "S1", 0 0, L_0x1017760; 1 drivers +v0xfcba20_0 .net "in0", 0 0, L_0x1018300; 1 drivers +v0xfcbac0_0 .net "in1", 0 0, L_0x1018170; 1 drivers +v0xfcbb40_0 .net "in2", 0 0, L_0x10184b0; 1 drivers +v0xfcbbe0_0 .net "in3", 0 0, L_0x10183a0; 1 drivers +v0xfcbcc0_0 .net "nS0", 0 0, L_0x1017540; 1 drivers +v0xfcbd60_0 .net "nS1", 0 0, L_0x10178a0; 1 drivers +v0xfcbe00_0 .net "out", 0 0, L_0x1017d90; 1 drivers +v0xfcbea0_0 .net "out0", 0 0, L_0x1017900; 1 drivers +v0xfcbf40_0 .net "out1", 0 0, L_0x1017a40; 1 drivers +v0xfcbfe0_0 .net "out2", 0 0, L_0x1017b30; 1 drivers +v0xfcc0f0_0 .net "out3", 0 0, L_0x1017c20; 1 drivers +S_0xfcb260 .scope module, "TwoMux" "TwoInMux" 3 343, 3 8, S_0xfcb0f0; + .timescale -9 -12; +L_0x1018440/d .functor NOT 1, L_0x1018550, C4<0>, C4<0>, C4<0>; +L_0x1018440 .delay (10000,10000,10000) L_0x1018440/d; +L_0x1018700/d .functor AND 1, L_0x1018c80, L_0x1018440, C4<1>, C4<1>; +L_0x1018700 .delay (20000,20000,20000) L_0x1018700/d; +L_0x10187f0/d .functor AND 1, L_0x1018b50, L_0x1018550, C4<1>, C4<1>; +L_0x10187f0 .delay (20000,20000,20000) L_0x10187f0/d; +L_0x10188e0/d .functor OR 1, L_0x1018700, L_0x10187f0, C4<0>, C4<0>; +L_0x10188e0 .delay (20000,20000,20000) L_0x10188e0/d; +v0xfcb350_0 .net "S", 0 0, L_0x1018550; 1 drivers +v0xfcb3f0_0 .net "in0", 0 0, L_0x1018c80; 1 drivers +v0xfcb490_0 .net "in1", 0 0, L_0x1018b50; 1 drivers +v0xfcb530_0 .net "nS", 0 0, L_0x1018440; 1 drivers +v0xfcb5b0_0 .net "out0", 0 0, L_0x1018700; 1 drivers +v0xfcb650_0 .net "out1", 0 0, L_0x10187f0; 1 drivers +v0xfcb730_0 .net "outfinal", 0 0, L_0x10188e0; 1 drivers +S_0xf5f220 .scope generate, "muxbits[3]" "muxbits[3]" 3 339, 3 339, S_0xf6f800; + .timescale -9 -12; +P_0xf1f968 .param/l "i" 3 339, +C4<011>; +L_0x101b720/d .functor OR 1, L_0x101baa0, L_0x101b8b0, C4<0>, C4<0>; +L_0x101b720 .delay (20000,20000,20000) L_0x101b720/d; +v0xfcaf90_0 .net *"_s15", 0 0, L_0x101baa0; 1 drivers +v0xfcb050_0 .net *"_s16", 0 0, L_0x101b8b0; 1 drivers +S_0xfca610 .scope module, "ZeroMux" "FourInMux" 3 341, 3 24, S_0xf5f220; + .timescale -9 -12; +L_0x1019020/d .functor NOT 1, L_0x1019b50, C4<0>, C4<0>, C4<0>; +L_0x1019020 .delay (10000,10000,10000) L_0x1019020/d; +L_0x1019110/d .functor NOT 1, L_0x1019210, C4<0>, C4<0>, C4<0>; +L_0x1019110 .delay (10000,10000,10000) L_0x1019110/d; +L_0x10193b0/d .functor NAND 1, L_0x1019020, L_0x1019110, L_0x1019df0, C4<1>; +L_0x10193b0 .delay (10000,10000,10000) L_0x10193b0/d; +L_0x10194f0/d .functor NAND 1, L_0x1019b50, L_0x1019110, L_0x1019c80, C4<1>; +L_0x10194f0 .delay (10000,10000,10000) L_0x10194f0/d; +L_0x10195e0/d .functor NAND 1, L_0x1019020, L_0x1019210, L_0x1019d20, C4<1>; +L_0x10195e0 .delay (10000,10000,10000) L_0x10195e0/d; +L_0x1019730/d .functor NAND 1, L_0x1019b50, L_0x1019210, L_0x1019e90, C4<1>; +L_0x1019730 .delay (10000,10000,10000) L_0x1019730/d; +L_0x10198a0/d .functor NAND 1, L_0x10193b0, L_0x10194f0, L_0x10195e0, L_0x1019730; +L_0x10198a0 .delay (10000,10000,10000) L_0x10198a0/d; +v0xfca700_0 .net "S0", 0 0, L_0x1019b50; 1 drivers +v0xfca7c0_0 .net "S1", 0 0, L_0x1019210; 1 drivers +v0xfca860_0 .net "in0", 0 0, L_0x1019df0; 1 drivers +v0xfca900_0 .net "in1", 0 0, L_0x1019c80; 1 drivers +v0xfca980_0 .net "in2", 0 0, L_0x1019d20; 1 drivers +v0xfcaa20_0 .net "in3", 0 0, L_0x1019e90; 1 drivers +v0xfcaac0_0 .net "nS0", 0 0, L_0x1019020; 1 drivers +v0xfcab60_0 .net "nS1", 0 0, L_0x1019110; 1 drivers +v0xfcac00_0 .net "out", 0 0, L_0x10198a0; 1 drivers +v0xfcaca0_0 .net "out0", 0 0, L_0x10193b0; 1 drivers +v0xfcad40_0 .net "out1", 0 0, L_0x10194f0; 1 drivers +v0xfcade0_0 .net "out2", 0 0, L_0x10195e0; 1 drivers +v0xfcaef0_0 .net "out3", 0 0, L_0x1019730; 1 drivers +S_0xfc9ba0 .scope module, "OneMux" "FourInMux" 3 342, 3 24, S_0xf5f220; + .timescale -9 -12; +L_0x1019f80/d .functor NOT 1, L_0x101a060, C4<0>, C4<0>, C4<0>; +L_0x1019f80 .delay (10000,10000,10000) L_0x1019f80/d; +L_0x101a280/d .functor NOT 1, L_0x101aba0, C4<0>, C4<0>, C4<0>; +L_0x101a280 .delay (10000,10000,10000) L_0x101a280/d; +L_0x101a320/d .functor NAND 1, L_0x1019f80, L_0x101a280, L_0x101aa00, C4<1>; +L_0x101a320 .delay (10000,10000,10000) L_0x101a320/d; +L_0x101a460/d .functor NAND 1, L_0x101a060, L_0x101a280, L_0x101aaa0, C4<1>; +L_0x101a460 .delay (10000,10000,10000) L_0x101a460/d; +L_0x101a550/d .functor NAND 1, L_0x1019f80, L_0x101aba0, L_0x101ae90, C4<1>; +L_0x101a550 .delay (10000,10000,10000) L_0x101a550/d; +L_0x101a640/d .functor NAND 1, L_0x101a060, L_0x101aba0, L_0x101af30, C4<1>; +L_0x101a640 .delay (10000,10000,10000) L_0x101a640/d; +L_0x101a750/d .functor NAND 1, L_0x101a320, L_0x101a460, L_0x101a550, L_0x101a640; +L_0x101a750 .delay (10000,10000,10000) L_0x101a750/d; +v0xfc9c90_0 .net "S0", 0 0, L_0x101a060; 1 drivers +v0xfc9d50_0 .net "S1", 0 0, L_0x101aba0; 1 drivers +v0xfc9df0_0 .net "in0", 0 0, L_0x101aa00; 1 drivers +v0xfc9e90_0 .net "in1", 0 0, L_0x101aaa0; 1 drivers +v0xfc9f10_0 .net "in2", 0 0, L_0x101ae90; 1 drivers +v0xfc9fb0_0 .net "in3", 0 0, L_0x101af30; 1 drivers +v0xfca090_0 .net "nS0", 0 0, L_0x1019f80; 1 drivers +v0xfca130_0 .net "nS1", 0 0, L_0x101a280; 1 drivers +v0xfca220_0 .net "out", 0 0, L_0x101a750; 1 drivers +v0xfca2c0_0 .net "out0", 0 0, L_0x101a320; 1 drivers +v0xfca3c0_0 .net "out1", 0 0, L_0x101a460; 1 drivers +v0xfca460_0 .net "out2", 0 0, L_0x101a550; 1 drivers +v0xfca570_0 .net "out3", 0 0, L_0x101a640; 1 drivers +S_0xf25ff0 .scope module, "TwoMux" "TwoInMux" 3 343, 3 8, S_0xf5f220; + .timescale -9 -12; +L_0x1014c00/d .functor NOT 1, L_0x101b5e0, C4<0>, C4<0>, C4<0>; +L_0x1014c00 .delay (10000,10000,10000) L_0x1014c00/d; +L_0x101acd0/d .functor AND 1, L_0x101b1e0, L_0x1014c00, C4<1>, C4<1>; +L_0x101acd0 .delay (20000,20000,20000) L_0x101acd0/d; +L_0x101adc0/d .functor AND 1, L_0x101b2d0, L_0x101b5e0, C4<1>, C4<1>; +L_0x101adc0 .delay (20000,20000,20000) L_0x101adc0/d; +L_0x101b400/d .functor OR 1, L_0x101acd0, L_0x101adc0, C4<0>, C4<0>; +L_0x101b400 .delay (20000,20000,20000) L_0x101b400/d; +v0xedf330_0 .net "S", 0 0, L_0x101b5e0; 1 drivers +v0xfc9790_0 .net "in0", 0 0, L_0x101b1e0; 1 drivers +v0xfc9830_0 .net "in1", 0 0, L_0x101b2d0; 1 drivers +v0xfc98d0_0 .net "nS", 0 0, L_0x1014c00; 1 drivers +v0xfc9980_0 .net "out0", 0 0, L_0x101acd0; 1 drivers +v0xfc9a20_0 .net "out1", 0 0, L_0x101adc0; 1 drivers +v0xfc9b00_0 .net "outfinal", 0 0, L_0x101b400; 1 drivers + .scope S_0xeed190; T_0 ; - %vpi_call 2 157 "$dumpfile", "FullALU.vcd"; - %vpi_call 2 158 "$dumpvars"; - %vpi_call 2 160 "$display", "Test 4 Bit Adder Functionality"; - %vpi_call 2 162 "$display", " A | B |Command| Out|ExpectedOut|Cout|OF"; + %vpi_call 2 158 "$dumpfile", "FullALU.vcd"; + %vpi_call 2 159 "$dumpvars"; + %vpi_call 2 161 "$display", "Test 4 Bit Adder Functionality"; + %vpi_call 2 163 "$display", " A | B |Command| Out|ExpectedOut|Cout|OF"; %movi 8, 2, 4; - %set/v v0xa38650_0, 8, 4; + %set/v v0xffc310_0, 8, 4; %movi 8, 4, 4; - %set/v v0xa38850_0, 8, 4; - %set/v v0xa388d0_0, 0, 3; + %set/v v0xffc560_0, 8, 4; + %set/v v0xffc5e0_0, 0, 3; %delay 1000000, 0; - %vpi_call 2 166 "$display", "%b | %b | %b | %b | Expect 0110| %b | %b ", v0xa38650_0, v0xa38850_0, v0xa388d0_0, v0xa386d0_0, v0xa38c80_0, v0xa38d00_0; + %vpi_call 2 167 "$display", "%b | %b | %b | %b | Expect 0110| %b | %b ", v0xffc310_0, v0xffc560_0, v0xffc5e0_0, v0xffc3b0_0, v0xffcb10_0, v0xffcc10_0; %movi 8, 1, 4; - %set/v v0xa38650_0, 8, 4; + %set/v v0xffc310_0, 8, 4; %movi 8, 6, 4; - %set/v v0xa38850_0, 8, 4; - %set/v v0xa388d0_0, 0, 3; + %set/v v0xffc560_0, 8, 4; + %set/v v0xffc5e0_0, 0, 3; %delay 1000000, 0; - %vpi_call 2 170 "$display", "%b | %b | %b | %b | Expect 0111| %b | %b ", v0xa38650_0, v0xa38850_0, v0xa388d0_0, v0xa386d0_0, v0xa38c80_0, v0xa38d00_0; + %vpi_call 2 171 "$display", "%b | %b | %b | %b | Expect 0111| %b | %b ", v0xffc310_0, v0xffc560_0, v0xffc5e0_0, v0xffc3b0_0, v0xffcb10_0, v0xffcc10_0; %movi 8, 5, 4; - %set/v v0xa38650_0, 8, 4; + %set/v v0xffc310_0, 8, 4; %movi 8, 13, 4; - %set/v v0xa38850_0, 8, 4; - %set/v v0xa388d0_0, 0, 3; + %set/v v0xffc560_0, 8, 4; + %set/v v0xffc5e0_0, 0, 3; %delay 1000000, 0; - %vpi_call 2 174 "$display", "%b | %b | %b | %b | Expect 0010| %b | %b ", v0xa38650_0, v0xa38850_0, v0xa388d0_0, v0xa386d0_0, v0xa38c80_0, v0xa38d00_0; + %vpi_call 2 175 "$display", "%b | %b | %b | %b | Expect 0010| %b | %b ", v0xffc310_0, v0xffc560_0, v0xffc5e0_0, v0xffc3b0_0, v0xffcb10_0, v0xffcc10_0; %movi 8, 2, 4; - %set/v v0xa38650_0, 8, 4; - %set/v v0xa38850_0, 1, 4; - %set/v v0xa388d0_0, 0, 3; + %set/v v0xffc310_0, 8, 4; + %set/v v0xffc560_0, 1, 4; + %set/v v0xffc5e0_0, 0, 3; %delay 1000000, 0; - %vpi_call 2 178 "$display", "%b | %b | %b | %b | Expect 0001| %b | %b ", v0xa38650_0, v0xa38850_0, v0xa388d0_0, v0xa386d0_0, v0xa38c80_0, v0xa38d00_0; + %vpi_call 2 179 "$display", "%b | %b | %b | %b | Expect 0001| %b | %b ", v0xffc310_0, v0xffc560_0, v0xffc5e0_0, v0xffc3b0_0, v0xffcb10_0, v0xffcc10_0; %movi 8, 8, 4; - %set/v v0xa38650_0, 8, 4; + %set/v v0xffc310_0, 8, 4; %movi 8, 3, 4; - %set/v v0xa38850_0, 8, 4; - %set/v v0xa388d0_0, 0, 3; + %set/v v0xffc560_0, 8, 4; + %set/v v0xffc5e0_0, 0, 3; %delay 1000000, 0; - %vpi_call 2 182 "$display", "%b | %b | %b | %b | Expect 1011| %b | %b ", v0xa38650_0, v0xa38850_0, v0xa388d0_0, v0xa386d0_0, v0xa38c80_0, v0xa38d00_0; + %vpi_call 2 183 "$display", "%b | %b | %b | %b | Expect 1011| %b | %b ", v0xffc310_0, v0xffc560_0, v0xffc5e0_0, v0xffc3b0_0, v0xffcb10_0, v0xffcc10_0; %movi 8, 12, 4; - %set/v v0xa38650_0, 8, 4; + %set/v v0xffc310_0, 8, 4; %movi 8, 2, 4; - %set/v v0xa38850_0, 8, 4; - %set/v v0xa388d0_0, 0, 3; + %set/v v0xffc560_0, 8, 4; + %set/v v0xffc5e0_0, 0, 3; %delay 1000000, 0; - %vpi_call 2 186 "$display", "%b | %b | %b | %b | Expect 1110| %b | %b ", v0xa38650_0, v0xa38850_0, v0xa388d0_0, v0xa386d0_0, v0xa38c80_0, v0xa38d00_0; + %vpi_call 2 187 "$display", "%b | %b | %b | %b | Expect 1110| %b | %b ", v0xffc310_0, v0xffc560_0, v0xffc5e0_0, v0xffc3b0_0, v0xffcb10_0, v0xffcc10_0; %movi 8, 11, 4; - %set/v v0xa38650_0, 8, 4; + %set/v v0xffc310_0, 8, 4; %movi 8, 5, 4; - %set/v v0xa38850_0, 8, 4; - %set/v v0xa388d0_0, 0, 3; + %set/v v0xffc560_0, 8, 4; + %set/v v0xffc5e0_0, 0, 3; %delay 1000000, 0; - %vpi_call 2 190 "$display", "%b | %b | %b | %b | Expect 0000| %b | %b ", v0xa38650_0, v0xa38850_0, v0xa388d0_0, v0xa386d0_0, v0xa38c80_0, v0xa38d00_0; + %vpi_call 2 191 "$display", "%b | %b | %b | %b | Expect 0000| %b | %b ", v0xffc310_0, v0xffc560_0, v0xffc5e0_0, v0xffc3b0_0, v0xffcb10_0, v0xffcc10_0; %movi 8, 7, 4; - %set/v v0xa38650_0, 8, 4; + %set/v v0xffc310_0, 8, 4; %movi 8, 9, 4; - %set/v v0xa38850_0, 8, 4; - %set/v v0xa388d0_0, 0, 3; + %set/v v0xffc560_0, 8, 4; + %set/v v0xffc5e0_0, 0, 3; %delay 1000000, 0; - %vpi_call 2 194 "$display", "%b | %b | %b | %b | Expect 0000| %b | %b ", v0xa38650_0, v0xa38850_0, v0xa388d0_0, v0xa386d0_0, v0xa38c80_0, v0xa38d00_0; + %vpi_call 2 195 "$display", "%b | %b | %b | %b | Expect 0000| %b | %b ", v0xffc310_0, v0xffc560_0, v0xffc5e0_0, v0xffc3b0_0, v0xffcb10_0, v0xffcc10_0; %movi 8, 13, 4; - %set/v v0xa38650_0, 8, 4; + %set/v v0xffc310_0, 8, 4; %movi 8, 12, 4; - %set/v v0xa38850_0, 8, 4; - %set/v v0xa388d0_0, 0, 3; + %set/v v0xffc560_0, 8, 4; + %set/v v0xffc5e0_0, 0, 3; %delay 1000000, 0; - %vpi_call 2 198 "$display", "%b | %b | %b | %b | Expect 1001| %b | %b ", v0xa38650_0, v0xa38850_0, v0xa388d0_0, v0xa386d0_0, v0xa38c80_0, v0xa38d00_0; + %vpi_call 2 199 "$display", "%b | %b | %b | %b | Expect 1001| %b | %b ", v0xffc310_0, v0xffc560_0, v0xffc5e0_0, v0xffc3b0_0, v0xffcb10_0, v0xffcc10_0; %movi 8, 14, 4; - %set/v v0xa38650_0, 8, 4; + %set/v v0xffc310_0, 8, 4; %movi 8, 10, 4; - %set/v v0xa38850_0, 8, 4; - %set/v v0xa388d0_0, 0, 3; + %set/v v0xffc560_0, 8, 4; + %set/v v0xffc5e0_0, 0, 3; %delay 1000000, 0; - %vpi_call 2 202 "$display", "%b | %b | %b | %b | Expect 1000| %b | %b ", v0xa38650_0, v0xa38850_0, v0xa388d0_0, v0xa386d0_0, v0xa38c80_0, v0xa38d00_0; + %vpi_call 2 203 "$display", "%b | %b | %b | %b | Expect 1000| %b | %b ", v0xffc310_0, v0xffc560_0, v0xffc5e0_0, v0xffc3b0_0, v0xffcb10_0, v0xffcc10_0; %movi 8, 5, 4; - %set/v v0xa38650_0, 8, 4; + %set/v v0xffc310_0, 8, 4; %movi 8, 6, 4; - %set/v v0xa38850_0, 8, 4; - %set/v v0xa388d0_0, 0, 3; + %set/v v0xffc560_0, 8, 4; + %set/v v0xffc5e0_0, 0, 3; %delay 1000000, 0; - %vpi_call 2 206 "$display", "%b | %b | %b | %b | Expect XXXX| %b | %b ", v0xa38650_0, v0xa38850_0, v0xa388d0_0, v0xa386d0_0, v0xa38c80_0, v0xa38d00_0; + %vpi_call 2 207 "$display", "%b | %b | %b | %b | Expect XXXX| %b | %b ", v0xffc310_0, v0xffc560_0, v0xffc5e0_0, v0xffc3b0_0, v0xffcb10_0, v0xffcc10_0; %movi 8, 2, 4; - %set/v v0xa38650_0, 8, 4; + %set/v v0xffc310_0, 8, 4; %movi 8, 7, 4; - %set/v v0xa38850_0, 8, 4; - %set/v v0xa388d0_0, 0, 3; + %set/v v0xffc560_0, 8, 4; + %set/v v0xffc5e0_0, 0, 3; %delay 1000000, 0; - %vpi_call 2 210 "$display", "%b | %b | %b | %b | Expect XXXX| %b | %b ", v0xa38650_0, v0xa38850_0, v0xa388d0_0, v0xa386d0_0, v0xa38c80_0, v0xa38d00_0; + %vpi_call 2 211 "$display", "%b | %b | %b | %b | Expect XXXX| %b | %b ", v0xffc310_0, v0xffc560_0, v0xffc5e0_0, v0xffc3b0_0, v0xffcb10_0, v0xffcc10_0; %movi 8, 7, 4; - %set/v v0xa38650_0, 8, 4; + %set/v v0xffc310_0, 8, 4; %movi 8, 7, 4; - %set/v v0xa38850_0, 8, 4; - %set/v v0xa388d0_0, 0, 3; + %set/v v0xffc560_0, 8, 4; + %set/v v0xffc5e0_0, 0, 3; %delay 1000000, 0; - %vpi_call 2 214 "$display", "%b | %b | %b | %b | Expect XXXX| %b | %b ", v0xa38650_0, v0xa38850_0, v0xa388d0_0, v0xa386d0_0, v0xa38c80_0, v0xa38d00_0; + %vpi_call 2 215 "$display", "%b | %b | %b | %b | Expect XXXX| %b | %b ", v0xffc310_0, v0xffc560_0, v0xffc5e0_0, v0xffc3b0_0, v0xffcb10_0, v0xffcc10_0; %movi 8, 8, 4; - %set/v v0xa38650_0, 8, 4; - %set/v v0xa38850_0, 1, 4; - %set/v v0xa388d0_0, 0, 3; + %set/v v0xffc310_0, 8, 4; + %set/v v0xffc560_0, 1, 4; + %set/v v0xffc5e0_0, 0, 3; %delay 1000000, 0; - %vpi_call 2 218 "$display", "%b | %b | %b | %b | Expect XXXX| %b | %b ", v0xa38650_0, v0xa38850_0, v0xa388d0_0, v0xa386d0_0, v0xa38c80_0, v0xa38d00_0; + %vpi_call 2 219 "$display", "%b | %b | %b | %b | Expect XXXX| %b | %b ", v0xffc310_0, v0xffc560_0, v0xffc5e0_0, v0xffc3b0_0, v0xffcb10_0, v0xffcc10_0; %movi 8, 8, 4; - %set/v v0xa38650_0, 8, 4; + %set/v v0xffc310_0, 8, 4; %movi 8, 13, 4; - %set/v v0xa38850_0, 8, 4; - %set/v v0xa388d0_0, 0, 3; + %set/v v0xffc560_0, 8, 4; + %set/v v0xffc5e0_0, 0, 3; %delay 1000000, 0; - %vpi_call 2 222 "$display", "%b | %b | %b | %b | Expect XXXX| %b | %b ", v0xa38650_0, v0xa38850_0, v0xa388d0_0, v0xa386d0_0, v0xa38c80_0, v0xa38d00_0; + %vpi_call 2 223 "$display", "%b | %b | %b | %b | Expect XXXX| %b | %b ", v0xffc310_0, v0xffc560_0, v0xffc5e0_0, v0xffc3b0_0, v0xffcb10_0, v0xffcc10_0; %movi 8, 11, 4; - %set/v v0xa38650_0, 8, 4; + %set/v v0xffc310_0, 8, 4; %movi 8, 12, 4; - %set/v v0xa38850_0, 8, 4; - %set/v v0xa388d0_0, 0, 3; + %set/v v0xffc560_0, 8, 4; + %set/v v0xffc5e0_0, 0, 3; %delay 1000000, 0; - %vpi_call 2 226 "$display", "%b | %b | %b | %b | Expect XXXX| %b | %b ", v0xa38650_0, v0xa38850_0, v0xa388d0_0, v0xa386d0_0, v0xa38c80_0, v0xa38d00_0; - %vpi_call 2 228 "$display", "Test 4 Bit SLT Functionality"; - %vpi_call 2 230 "$display", " A | B |Command| Out|ExpectedOut|Cout|OF |SLTflag"; + %vpi_call 2 227 "$display", "%b | %b | %b | %b | Expect XXXX| %b | %b ", v0xffc310_0, v0xffc560_0, v0xffc5e0_0, v0xffc3b0_0, v0xffcb10_0, v0xffcc10_0; + %vpi_call 2 229 "$display", "Test 4 Bit SLT Functionality"; + %vpi_call 2 231 "$display", " A | B |Command| Out|ExpectedOut|Cout|OF |SLTflag"; %movi 8, 2, 4; - %set/v v0xa38650_0, 8, 4; + %set/v v0xffc310_0, 8, 4; %movi 8, 4, 4; - %set/v v0xa38850_0, 8, 4; + %set/v v0xffc560_0, 8, 4; %movi 8, 3, 3; - %set/v v0xa388d0_0, 8, 3; + %set/v v0xffc5e0_0, 8, 3; %delay 1000000, 0; - %vpi_call 2 234 "$display", "%b | %b | %b | %b | Expect 1110| %b | %b | %b", v0xa38650_0, v0xa38850_0, v0xa388d0_0, v0xa386d0_0, v0xa38c80_0, v0xa38d00_0, v0xa38ad0_0; + %vpi_call 2 235 "$display", "%b | %b | %b | %b | Expect 0001| %b | %b | %b", v0xffc310_0, v0xffc560_0, v0xffc5e0_0, v0xffc760_0, v0xffcb10_0, v0xffcc10_0, v0xffc8f0_0; %movi 8, 4, 4; - %set/v v0xa38650_0, 8, 4; + %set/v v0xffc310_0, 8, 4; %movi 8, 2, 4; - %set/v v0xa38850_0, 8, 4; + %set/v v0xffc560_0, 8, 4; %movi 8, 3, 3; - %set/v v0xa388d0_0, 8, 3; + %set/v v0xffc5e0_0, 8, 3; %delay 1000000, 0; - %vpi_call 2 238 "$display", "%b | %b | %b | %b | Expect 0010| %b | %b | %b", v0xa38650_0, v0xa38850_0, v0xa388d0_0, v0xa386d0_0, v0xa38c80_0, v0xa38d00_0, v0xa38ad0_0; + %vpi_call 2 239 "$display", "%b | %b | %b | %b | Expect 0000| %b | %b | %b", v0xffc310_0, v0xffc560_0, v0xffc5e0_0, v0xffc760_0, v0xffcb10_0, v0xffcc10_0, v0xffc8f0_0; %movi 8, 14, 4; - %set/v v0xa38650_0, 8, 4; + %set/v v0xffc310_0, 8, 4; %movi 8, 4, 4; - %set/v v0xa38850_0, 8, 4; + %set/v v0xffc560_0, 8, 4; %movi 8, 3, 3; - %set/v v0xa388d0_0, 8, 3; + %set/v v0xffc5e0_0, 8, 3; %delay 1000000, 0; - %vpi_call 2 242 "$display", "%b | %b | %b | %b | Expect 1010| %b | %b | %b", v0xa38650_0, v0xa38850_0, v0xa388d0_0, v0xa386d0_0, v0xa38c80_0, v0xa38d00_0, v0xa38ad0_0; + %vpi_call 2 243 "$display", "%b | %b | %b | %b | Expect 0001| %b | %b | %b", v0xffc310_0, v0xffc560_0, v0xffc5e0_0, v0xffc760_0, v0xffcb10_0, v0xffcc10_0, v0xffc8f0_0; %movi 8, 4, 4; - %set/v v0xa38650_0, 8, 4; + %set/v v0xffc310_0, 8, 4; %movi 8, 14, 4; - %set/v v0xa38850_0, 8, 4; + %set/v v0xffc560_0, 8, 4; %movi 8, 3, 3; - %set/v v0xa388d0_0, 8, 3; + %set/v v0xffc5e0_0, 8, 3; %delay 1000000, 0; - %vpi_call 2 246 "$display", "%b | %b | %b | %b | Expect 0110| %b | %b | %b", v0xa38650_0, v0xa38850_0, v0xa388d0_0, v0xa386d0_0, v0xa38c80_0, v0xa38d00_0, v0xa38ad0_0; + %vpi_call 2 247 "$display", "%b | %b | %b | %b | Expect 0000| %b | %b | %b", v0xffc310_0, v0xffc560_0, v0xffc5e0_0, v0xffc760_0, v0xffcb10_0, v0xffcc10_0, v0xffc8f0_0; %movi 8, 14, 4; - %set/v v0xa38650_0, 8, 4; - %set/v v0xa38850_0, 1, 4; + %set/v v0xffc310_0, 8, 4; + %set/v v0xffc560_0, 1, 4; %movi 8, 3, 3; - %set/v v0xa388d0_0, 8, 3; + %set/v v0xffc5e0_0, 8, 3; %delay 1000000, 0; - %vpi_call 2 250 "$display", "%b | %b | %b | %b | Expect 1111| %b | %b | %b", v0xa38650_0, v0xa38850_0, v0xa388d0_0, v0xa386d0_0, v0xa38c80_0, v0xa38d00_0, v0xa38ad0_0; - %set/v v0xa38650_0, 1, 4; + %vpi_call 2 251 "$display", "%b | %b | %b | %b | Expect 0001| %b | %b | %b", v0xffc310_0, v0xffc560_0, v0xffc5e0_0, v0xffc760_0, v0xffcb10_0, v0xffcc10_0, v0xffc8f0_0; + %set/v v0xffc310_0, 1, 4; %movi 8, 14, 4; - %set/v v0xa38850_0, 8, 4; + %set/v v0xffc560_0, 8, 4; %movi 8, 3, 3; - %set/v v0xa388d0_0, 8, 3; + %set/v v0xffc5e0_0, 8, 3; %delay 1000000, 0; - %vpi_call 2 254 "$display", "%b | %b | %b | %b | Expect 0001| %b | %b | %b", v0xa38650_0, v0xa38850_0, v0xa388d0_0, v0xa386d0_0, v0xa38c80_0, v0xa38d00_0, v0xa38ad0_0; + %vpi_call 2 255 "$display", "%b | %b | %b | %b | Expect 0000| %b | %b | %b", v0xffc310_0, v0xffc560_0, v0xffc5e0_0, v0xffc760_0, v0xffcb10_0, v0xffcc10_0, v0xffc8f0_0; %movi 8, 13, 4; - %set/v v0xa38650_0, 8, 4; + %set/v v0xffc310_0, 8, 4; %movi 8, 13, 4; - %set/v v0xa38850_0, 8, 4; + %set/v v0xffc560_0, 8, 4; %movi 8, 3, 3; - %set/v v0xa388d0_0, 8, 3; + %set/v v0xffc5e0_0, 8, 3; %delay 1000000, 0; - %vpi_call 2 258 "$display", "%b | %b | %b | %b | Expect 0000| %b | %b | %b", v0xa38650_0, v0xa38850_0, v0xa388d0_0, v0xa386d0_0, v0xa38c80_0, v0xa38d00_0, v0xa38ad0_0; + %vpi_call 2 259 "$display", "%b | %b | %b | %b | Expect 0000| %b | %b | %b", v0xffc310_0, v0xffc560_0, v0xffc5e0_0, v0xffc760_0, v0xffcb10_0, v0xffcc10_0, v0xffc8f0_0; %movi 8, 5, 4; - %set/v v0xa38650_0, 8, 4; + %set/v v0xffc310_0, 8, 4; %movi 8, 5, 4; - %set/v v0xa38850_0, 8, 4; + %set/v v0xffc560_0, 8, 4; %movi 8, 3, 3; - %set/v v0xa388d0_0, 8, 3; + %set/v v0xffc5e0_0, 8, 3; %delay 1000000, 0; - %vpi_call 2 262 "$display", "%b | %b | %b | %b | Expect 0000| %b | %b | %b", v0xa38650_0, v0xa38850_0, v0xa388d0_0, v0xa386d0_0, v0xa38c80_0, v0xa38d00_0, v0xa38ad0_0; + %vpi_call 2 263 "$display", "%b | %b | %b | %b | Expect 0000| %b | %b | %b", v0xffc310_0, v0xffc560_0, v0xffc5e0_0, v0xffc760_0, v0xffcb10_0, v0xffcc10_0, v0xffc8f0_0; %movi 8, 9, 4; - %set/v v0xa38650_0, 8, 4; + %set/v v0xffc310_0, 8, 4; %movi 8, 5, 4; - %set/v v0xa38850_0, 8, 4; + %set/v v0xffc560_0, 8, 4; %movi 8, 3, 3; - %set/v v0xa388d0_0, 8, 3; + %set/v v0xffc5e0_0, 8, 3; %delay 1000000, 0; - %vpi_call 2 266 "$display", "%b | %b | %b | %b | Expect XXXX| %b | %b | %b", v0xa38650_0, v0xa38850_0, v0xa388d0_0, v0xa386d0_0, v0xa38c80_0, v0xa38d00_0, v0xa38ad0_0; - %vpi_call 2 268 "$display", "Test 4 Bit AND/NAND Functionality"; - %vpi_call 2 270 "$display", " A | B |Command| Out |ExpectedOut-AND"; - %set/v v0xa38650_0, 1, 4; - %set/v v0xa38850_0, 1, 4; + %vpi_call 2 267 "$display", "%b | %b | %b | %b | Expect 0001| %b | %b | %b", v0xffc310_0, v0xffc560_0, v0xffc5e0_0, v0xffc760_0, v0xffcb10_0, v0xffcc10_0, v0xffc8f0_0; + %vpi_call 2 269 "$display", "Test 4 Bit AND/NAND Functionality"; + %vpi_call 2 271 "$display", " A | B |Command| Out |ExpectedOut-AND"; + %set/v v0xffc310_0, 1, 4; + %set/v v0xffc560_0, 1, 4; %movi 8, 4, 3; - %set/v v0xa388d0_0, 8, 3; + %set/v v0xffc5e0_0, 8, 3; %delay 1000000, 0; - %vpi_call 2 274 "$display", "%b | %b | %b | %b | 1111", v0xa38650_0, v0xa38850_0, v0xa388d0_0, v0xa387d0_0; - %set/v v0xa38650_0, 1, 4; + %vpi_call 2 275 "$display", "%b | %b | %b | %b | 1111", v0xffc310_0, v0xffc560_0, v0xffc5e0_0, v0xffc4b0_0; + %set/v v0xffc310_0, 1, 4; %movi 8, 10, 4; - %set/v v0xa38850_0, 8, 4; + %set/v v0xffc560_0, 8, 4; %movi 8, 4, 3; - %set/v v0xa388d0_0, 8, 3; + %set/v v0xffc5e0_0, 8, 3; %delay 1000000, 0; - %vpi_call 2 278 "$display", "%b | %b | %b | %b | 1010", v0xa38650_0, v0xa38850_0, v0xa388d0_0, v0xa387d0_0; - %set/v v0xa38650_0, 1, 4; + %vpi_call 2 279 "$display", "%b | %b | %b | %b | 1010", v0xffc310_0, v0xffc560_0, v0xffc5e0_0, v0xffc4b0_0; + %set/v v0xffc310_0, 1, 4; %movi 8, 5, 4; - %set/v v0xa38850_0, 8, 4; + %set/v v0xffc560_0, 8, 4; %movi 8, 4, 3; - %set/v v0xa388d0_0, 8, 3; + %set/v v0xffc5e0_0, 8, 3; %delay 1000000, 0; - %vpi_call 2 282 "$display", "%b | %b | %b | %b | 0101", v0xa38650_0, v0xa38850_0, v0xa388d0_0, v0xa387d0_0; - %set/v v0xa38650_0, 1, 4; - %set/v v0xa38850_0, 0, 4; + %vpi_call 2 283 "$display", "%b | %b | %b | %b | 0101", v0xffc310_0, v0xffc560_0, v0xffc5e0_0, v0xffc4b0_0; + %set/v v0xffc310_0, 1, 4; + %set/v v0xffc560_0, 0, 4; %movi 8, 4, 3; - %set/v v0xa388d0_0, 8, 3; + %set/v v0xffc5e0_0, 8, 3; %delay 1000000, 0; - %vpi_call 2 286 "$display", "%b | %b | %b | %b | 0000", v0xa38650_0, v0xa38850_0, v0xa388d0_0, v0xa387d0_0; - %vpi_call 2 289 "$display", " A | B |Command| Out |ExpectedOut-NAND"; - %set/v v0xa38650_0, 1, 4; - %set/v v0xa38850_0, 1, 4; + %vpi_call 2 287 "$display", "%b | %b | %b | %b | 0000", v0xffc310_0, v0xffc560_0, v0xffc5e0_0, v0xffc4b0_0; + %vpi_call 2 290 "$display", " A | B |Command| Out |ExpectedOut-NAND"; + %set/v v0xffc310_0, 1, 4; + %set/v v0xffc560_0, 1, 4; %movi 8, 5, 3; - %set/v v0xa388d0_0, 8, 3; + %set/v v0xffc5e0_0, 8, 3; %delay 1000000, 0; - %vpi_call 2 293 "$display", "%b | %b | %b | %b | 0000", v0xa38650_0, v0xa38850_0, v0xa388d0_0, v0xa387d0_0; - %set/v v0xa38650_0, 1, 4; + %vpi_call 2 294 "$display", "%b | %b | %b | %b | 0000", v0xffc310_0, v0xffc560_0, v0xffc5e0_0, v0xffc4b0_0; + %set/v v0xffc310_0, 1, 4; %movi 8, 10, 4; - %set/v v0xa38850_0, 8, 4; + %set/v v0xffc560_0, 8, 4; %movi 8, 5, 3; - %set/v v0xa388d0_0, 8, 3; + %set/v v0xffc5e0_0, 8, 3; %delay 1000000, 0; - %vpi_call 2 297 "$display", "%b | %b | %b | %b | 0101", v0xa38650_0, v0xa38850_0, v0xa388d0_0, v0xa387d0_0; - %set/v v0xa38650_0, 1, 4; + %vpi_call 2 298 "$display", "%b | %b | %b | %b | 0101", v0xffc310_0, v0xffc560_0, v0xffc5e0_0, v0xffc4b0_0; + %set/v v0xffc310_0, 1, 4; %movi 8, 5, 4; - %set/v v0xa38850_0, 8, 4; + %set/v v0xffc560_0, 8, 4; %movi 8, 5, 3; - %set/v v0xa388d0_0, 8, 3; + %set/v v0xffc5e0_0, 8, 3; %delay 1000000, 0; - %vpi_call 2 301 "$display", "%b | %b | %b | %b | 1010", v0xa38650_0, v0xa38850_0, v0xa388d0_0, v0xa387d0_0; - %set/v v0xa38650_0, 1, 4; - %set/v v0xa38850_0, 0, 4; + %vpi_call 2 302 "$display", "%b | %b | %b | %b | 1010", v0xffc310_0, v0xffc560_0, v0xffc5e0_0, v0xffc4b0_0; + %set/v v0xffc310_0, 1, 4; + %set/v v0xffc560_0, 0, 4; %movi 8, 5, 3; - %set/v v0xa388d0_0, 8, 3; + %set/v v0xffc5e0_0, 8, 3; %delay 1000000, 0; - %vpi_call 2 305 "$display", "%b | %b | %b | %b | 1111", v0xa38650_0, v0xa38850_0, v0xa388d0_0, v0xa387d0_0; - %vpi_call 2 307 "$display", "Test 4 Bit OR/NOR/XOR Functionality"; - %vpi_call 2 309 "$display", " A | B |Command | Out |ExpectedOut-OR"; + %vpi_call 2 306 "$display", "%b | %b | %b | %b | 1111", v0xffc310_0, v0xffc560_0, v0xffc5e0_0, v0xffc4b0_0; + %vpi_call 2 308 "$display", "Test 4 Bit OR/NOR/XOR Functionality"; + %vpi_call 2 310 "$display", " A | B |Command | Out |ExpectedOut-OR"; %movi 8, 10, 4; - %set/v v0xa38650_0, 8, 4; + %set/v v0xffc310_0, 8, 4; %movi 8, 5, 4; - %set/v v0xa38850_0, 8, 4; - %set/v v0xa388d0_0, 1, 3; + %set/v v0xffc560_0, 8, 4; + %set/v v0xffc5e0_0, 1, 3; %delay 1000000, 0; - %vpi_call 2 313 "$display", "%b | %b | %b | %b | 1111", v0xa38650_0, v0xa38850_0, v0xa388d0_0, v0xa389d0_0; - %set/v v0xa38650_0, 1, 4; + %vpi_call 2 314 "$display", "%b | %b | %b | %b | 1111", v0xffc310_0, v0xffc560_0, v0xffc5e0_0, v0xffc6e0_0; + %set/v v0xffc310_0, 1, 4; %movi 8, 5, 4; - %set/v v0xa38850_0, 8, 4; - %set/v v0xa388d0_0, 1, 3; + %set/v v0xffc560_0, 8, 4; + %set/v v0xffc5e0_0, 1, 3; %delay 1000000, 0; - %vpi_call 2 317 "$display", "%b | %b | %b | %b | 1111", v0xa38650_0, v0xa38850_0, v0xa388d0_0, v0xa389d0_0; + %vpi_call 2 318 "$display", "%b | %b | %b | %b | 1111", v0xffc310_0, v0xffc560_0, v0xffc5e0_0, v0xffc6e0_0; %movi 8, 11, 4; - %set/v v0xa38650_0, 8, 4; - %set/v v0xa38850_0, 0, 4; - %set/v v0xa388d0_0, 1, 3; + %set/v v0xffc310_0, 8, 4; + %set/v v0xffc560_0, 0, 4; + %set/v v0xffc5e0_0, 1, 3; %delay 1000000, 0; - %vpi_call 2 321 "$display", "%b | %b | %b | %b | 1011", v0xa38650_0, v0xa38850_0, v0xa388d0_0, v0xa389d0_0; - %vpi_call 2 323 "$display", " A | B |Command | Out |ExpectedOut-NOR"; + %vpi_call 2 322 "$display", "%b | %b | %b | %b | 1011", v0xffc310_0, v0xffc560_0, v0xffc5e0_0, v0xffc6e0_0; + %vpi_call 2 324 "$display", " A | B |Command | Out |ExpectedOut-NOR"; %movi 8, 10, 4; - %set/v v0xa38650_0, 8, 4; + %set/v v0xffc310_0, 8, 4; %movi 8, 5, 4; - %set/v v0xa38850_0, 8, 4; + %set/v v0xffc560_0, 8, 4; %movi 8, 6, 3; - %set/v v0xa388d0_0, 8, 3; + %set/v v0xffc5e0_0, 8, 3; %delay 1000000, 0; - %vpi_call 2 327 "$display", "%b | %b | %b | %b | 0000", v0xa38650_0, v0xa38850_0, v0xa388d0_0, v0xa389d0_0; - %set/v v0xa38650_0, 1, 4; + %vpi_call 2 328 "$display", "%b | %b | %b | %b | 0000", v0xffc310_0, v0xffc560_0, v0xffc5e0_0, v0xffc6e0_0; + %set/v v0xffc310_0, 1, 4; %movi 8, 5, 4; - %set/v v0xa38850_0, 8, 4; + %set/v v0xffc560_0, 8, 4; %movi 8, 6, 3; - %set/v v0xa388d0_0, 8, 3; + %set/v v0xffc5e0_0, 8, 3; %delay 1000000, 0; - %vpi_call 2 331 "$display", "%b | %b | %b | %b | 0000", v0xa38650_0, v0xa38850_0, v0xa388d0_0, v0xa389d0_0; + %vpi_call 2 332 "$display", "%b | %b | %b | %b | 0000", v0xffc310_0, v0xffc560_0, v0xffc5e0_0, v0xffc6e0_0; %movi 8, 11, 4; - %set/v v0xa38650_0, 8, 4; - %set/v v0xa38850_0, 0, 4; + %set/v v0xffc310_0, 8, 4; + %set/v v0xffc560_0, 0, 4; %movi 8, 6, 3; - %set/v v0xa388d0_0, 8, 3; + %set/v v0xffc5e0_0, 8, 3; %delay 1000000, 0; - %vpi_call 2 335 "$display", "%b | %b | %b | %b | 0100", v0xa38650_0, v0xa38850_0, v0xa388d0_0, v0xa389d0_0; - %vpi_call 2 337 "$display", " A | B |Command | Out |ExpectedOut-XOR"; + %vpi_call 2 336 "$display", "%b | %b | %b | %b | 0100", v0xffc310_0, v0xffc560_0, v0xffc5e0_0, v0xffc6e0_0; + %vpi_call 2 338 "$display", " A | B |Command | Out |ExpectedOut-XOR"; %movi 8, 10, 4; - %set/v v0xa38650_0, 8, 4; + %set/v v0xffc310_0, 8, 4; %movi 8, 5, 4; - %set/v v0xa38850_0, 8, 4; + %set/v v0xffc560_0, 8, 4; %movi 8, 2, 3; - %set/v v0xa388d0_0, 8, 3; + %set/v v0xffc5e0_0, 8, 3; %delay 1000000, 0; - %vpi_call 2 341 "$display", "%b | %b | %b | %b | 1111", v0xa38650_0, v0xa38850_0, v0xa388d0_0, v0xa389d0_0; - %set/v v0xa38650_0, 1, 4; + %vpi_call 2 342 "$display", "%b | %b | %b | %b | 1111", v0xffc310_0, v0xffc560_0, v0xffc5e0_0, v0xffc6e0_0; + %set/v v0xffc310_0, 1, 4; %movi 8, 5, 4; - %set/v v0xa38850_0, 8, 4; + %set/v v0xffc560_0, 8, 4; %movi 8, 2, 3; - %set/v v0xa388d0_0, 8, 3; + %set/v v0xffc5e0_0, 8, 3; %delay 1000000, 0; - %vpi_call 2 345 "$display", "%b | %b | %b | %b | 1010", v0xa38650_0, v0xa38850_0, v0xa388d0_0, v0xa389d0_0; + %vpi_call 2 346 "$display", "%b | %b | %b | %b | 1010", v0xffc310_0, v0xffc560_0, v0xffc5e0_0, v0xffc6e0_0; %movi 8, 11, 4; - %set/v v0xa38650_0, 8, 4; - %set/v v0xa38850_0, 0, 4; + %set/v v0xffc310_0, 8, 4; + %set/v v0xffc560_0, 0, 4; %movi 8, 2, 3; - %set/v v0xa388d0_0, 8, 3; + %set/v v0xffc5e0_0, 8, 3; %delay 1000000, 0; - %vpi_call 2 349 "$display", "%b | %b | %b | %b | 1011", v0xa38650_0, v0xa38850_0, v0xa388d0_0, v0xa389d0_0; - %vpi_call 2 351 "$display", "Test 4 Bit ALU Functionality"; - %vpi_call 2 353 "$display", " A | B |Command | Out |ExpectedOut | COut | OF |SLT|Zero"; - %set/v v0xa38650_0, 1, 4; - %set/v v0xa38850_0, 1, 4; + %vpi_call 2 350 "$display", "%b | %b | %b | %b | 1011", v0xffc310_0, v0xffc560_0, v0xffc5e0_0, v0xffc6e0_0; + %vpi_call 2 352 "$display", "Test 4 Bit ALU Functionality"; + %vpi_call 2 354 "$display", " A | B |Command | Out |ExpectedOut | COut | OF |SLT|Zero"; + %set/v v0xffc310_0, 1, 4; + %set/v v0xffc560_0, 1, 4; %movi 8, 4, 3; - %set/v v0xa388d0_0, 8, 3; + %set/v v0xffc5e0_0, 8, 3; %delay 1000000, 0; - %vpi_call 2 358 "$display", "%b | %b | %b - AND | %b | 1111 | %b | %b | %b | %b", v0xa38650_0, v0xa38850_0, v0xa388d0_0, v0xa38950_0, v0xa38c80_0, v0xa38d00_0, v0xa38ad0_0, v0xa38750_0; - %set/v v0xa38650_0, 1, 4; - %set/v v0xa38850_0, 0, 4; + %vpi_call 2 359 "$display", "%b | %b | %b - AND | %b | 1111 | %b | %b | %b | %b", v0xffc310_0, v0xffc560_0, v0xffc5e0_0, v0xffc660_0, v0xffcb10_0, v0xffcc10_0, v0xffc7e0_0, v0xffc430_0; + %set/v v0xffc310_0, 1, 4; + %set/v v0xffc560_0, 0, 4; %movi 8, 5, 3; - %set/v v0xa388d0_0, 8, 3; + %set/v v0xffc5e0_0, 8, 3; %delay 1000000, 0; - %vpi_call 2 363 "$display", "%b | %b | %b - NAND | %b | 1111 | %b | %b | %b | %b", v0xa38650_0, v0xa38850_0, v0xa388d0_0, v0xa38950_0, v0xa38c80_0, v0xa38d00_0, v0xa38ad0_0, v0xa38750_0; - %set/v v0xa38650_0, 1, 4; + %vpi_call 2 364 "$display", "%b | %b | %b - NAND | %b | 1111 | %b | %b | %b | %b", v0xffc310_0, v0xffc560_0, v0xffc5e0_0, v0xffc660_0, v0xffcb10_0, v0xffcc10_0, v0xffc7e0_0, v0xffc430_0; + %set/v v0xffc310_0, 1, 4; %movi 8, 5, 4; - %set/v v0xa38850_0, 8, 4; - %set/v v0xa388d0_0, 1, 3; + %set/v v0xffc560_0, 8, 4; + %set/v v0xffc5e0_0, 1, 3; %delay 1000000, 0; - %vpi_call 2 368 "$display", "%b | %b | %b - OR | %b | 1111 | %b | %b | %b | %b", v0xa38650_0, v0xa38850_0, v0xa388d0_0, v0xa38950_0, v0xa38c80_0, v0xa38d00_0, v0xa38ad0_0, v0xa38750_0; + %vpi_call 2 369 "$display", "%b | %b | %b - OR | %b | 1111 | %b | %b | %b | %b", v0xffc310_0, v0xffc560_0, v0xffc5e0_0, v0xffc660_0, v0xffcb10_0, v0xffcc10_0, v0xffc7e0_0, v0xffc430_0; %movi 8, 11, 4; - %set/v v0xa38650_0, 8, 4; - %set/v v0xa38850_0, 0, 4; + %set/v v0xffc310_0, 8, 4; + %set/v v0xffc560_0, 0, 4; %movi 8, 6, 3; - %set/v v0xa388d0_0, 8, 3; + %set/v v0xffc5e0_0, 8, 3; %delay 1000000, 0; - %vpi_call 2 373 "$display", "%b | %b | %b - NOR | %b | 0100 | %b | %b | %b | %b", v0xa38650_0, v0xa38850_0, v0xa388d0_0, v0xa38950_0, v0xa38c80_0, v0xa38d00_0, v0xa38ad0_0, v0xa38750_0; + %vpi_call 2 374 "$display", "%b | %b | %b - NOR | %b | 0100 | %b | %b | %b | %b", v0xffc310_0, v0xffc560_0, v0xffc5e0_0, v0xffc660_0, v0xffcb10_0, v0xffcc10_0, v0xffc7e0_0, v0xffc430_0; %movi 8, 11, 4; - %set/v v0xa38650_0, 8, 4; - %set/v v0xa38850_0, 0, 4; + %set/v v0xffc310_0, 8, 4; + %set/v v0xffc560_0, 0, 4; %movi 8, 2, 3; - %set/v v0xa388d0_0, 8, 3; + %set/v v0xffc5e0_0, 8, 3; %delay 1000000, 0; - %vpi_call 2 378 "$display", "%b | %b | %b - XOR | %b | 1011 | %b | %b | %b | %b", v0xa38650_0, v0xa38850_0, v0xa388d0_0, v0xa38950_0, v0xa38c80_0, v0xa38d00_0, v0xa38ad0_0, v0xa38750_0; + %vpi_call 2 379 "$display", "%b | %b | %b - XOR | %b | 1011 | %b | %b | %b | %b", v0xffc310_0, v0xffc560_0, v0xffc5e0_0, v0xffc660_0, v0xffcb10_0, v0xffcc10_0, v0xffc7e0_0, v0xffc430_0; %movi 8, 2, 4; - %set/v v0xa38650_0, 8, 4; + %set/v v0xffc310_0, 8, 4; %movi 8, 4, 4; - %set/v v0xa38850_0, 8, 4; - %set/v v0xa388d0_0, 0, 3; + %set/v v0xffc560_0, 8, 4; + %set/v v0xffc5e0_0, 0, 3; %delay 1000000, 0; - %vpi_call 2 383 "$display", "%b | %b | %b - ADD | %b | 0110 | %b | %b | %b | %b", v0xa38650_0, v0xa38850_0, v0xa388d0_0, v0xa38950_0, v0xa38c80_0, v0xa38d00_0, v0xa38ad0_0, v0xa38750_0; + %vpi_call 2 384 "$display", "%b | %b | %b - ADD | %b | 0110 | %b | %b | %b | %b", v0xffc310_0, v0xffc560_0, v0xffc5e0_0, v0xffc660_0, v0xffcb10_0, v0xffcc10_0, v0xffc7e0_0, v0xffc430_0; %movi 8, 11, 4; - %set/v v0xa38650_0, 8, 4; + %set/v v0xffc310_0, 8, 4; %movi 8, 12, 4; - %set/v v0xa38850_0, 8, 4; - %set/v v0xa388d0_0, 0, 3; + %set/v v0xffc560_0, 8, 4; + %set/v v0xffc5e0_0, 0, 3; %delay 1000000, 0; - %vpi_call 2 387 "$display", "%b | %b | %b - ADD | %b | XXXX | %b | %b | %b | %b", v0xa38650_0, v0xa38850_0, v0xa388d0_0, v0xa38950_0, v0xa38c80_0, v0xa38d00_0, v0xa38ad0_0, v0xa38750_0; + %vpi_call 2 388 "$display", "%b | %b | %b - ADD | %b | XXXX | %b | %b | %b | %b", v0xffc310_0, v0xffc560_0, v0xffc5e0_0, v0xffc660_0, v0xffcb10_0, v0xffcc10_0, v0xffc7e0_0, v0xffc430_0; %movi 8, 2, 4; - %set/v v0xa38650_0, 8, 4; + %set/v v0xffc310_0, 8, 4; %movi 8, 4, 4; - %set/v v0xa38850_0, 8, 4; + %set/v v0xffc560_0, 8, 4; %movi 8, 1, 3; - %set/v v0xa388d0_0, 8, 3; + %set/v v0xffc5e0_0, 8, 3; %delay 1000000, 0; - %vpi_call 2 392 "$display", "%b | %b | %b - SUB | %b | 1110 | %b | %b | %b | %b", v0xa38650_0, v0xa38850_0, v0xa388d0_0, v0xa38950_0, v0xa38c80_0, v0xa38d00_0, v0xa38ad0_0, v0xa38750_0; + %vpi_call 2 393 "$display", "%b | %b | %b - SUB | %b | 1110 | %b | %b | %b | %b", v0xffc310_0, v0xffc560_0, v0xffc5e0_0, v0xffc660_0, v0xffcb10_0, v0xffcc10_0, v0xffc7e0_0, v0xffc430_0; %movi 8, 9, 4; - %set/v v0xa38650_0, 8, 4; + %set/v v0xffc310_0, 8, 4; %movi 8, 3, 4; - %set/v v0xa38850_0, 8, 4; + %set/v v0xffc560_0, 8, 4; %movi 8, 1, 3; - %set/v v0xa388d0_0, 8, 3; + %set/v v0xffc5e0_0, 8, 3; %delay 1000000, 0; - %vpi_call 2 396 "$display", "%b | %b | %b - SUB | %b | XXXX | %b | %b | %b | %b", v0xa38650_0, v0xa38850_0, v0xa388d0_0, v0xa38950_0, v0xa38c80_0, v0xa38d00_0, v0xa38ad0_0, v0xa38750_0; + %vpi_call 2 397 "$display", "%b | %b | %b - SUB | %b | XXXX | %b | %b | %b | %b", v0xffc310_0, v0xffc560_0, v0xffc5e0_0, v0xffc660_0, v0xffcb10_0, v0xffcc10_0, v0xffc7e0_0, v0xffc430_0; %movi 8, 4, 4; - %set/v v0xa38650_0, 8, 4; + %set/v v0xffc310_0, 8, 4; %movi 8, 2, 4; - %set/v v0xa38850_0, 8, 4; + %set/v v0xffc560_0, 8, 4; %movi 8, 3, 3; - %set/v v0xa388d0_0, 8, 3; + %set/v v0xffc5e0_0, 8, 3; %delay 1000000, 0; - %vpi_call 2 402 "$display", "%b | %b | %b - SLT | %b | 0010 | %b | %b | %b | %b", v0xa38650_0, v0xa38850_0, v0xa388d0_0, v0xa38950_0, v0xa38c80_0, v0xa38d00_0, v0xa38ad0_0, v0xa38750_0; + %vpi_call 2 403 "$display", "%b | %b | %b - SLT | %b | 0010 | %b | %b | %b | %b", v0xffc310_0, v0xffc560_0, v0xffc5e0_0, v0xffc660_0, v0xffcb10_0, v0xffcc10_0, v0xffc8f0_0, v0xffc430_0; %movi 8, 9, 4; - %set/v v0xa38650_0, 8, 4; + %set/v v0xffc310_0, 8, 4; %movi 8, 5, 4; - %set/v v0xa38850_0, 8, 4; + %set/v v0xffc560_0, 8, 4; %movi 8, 3, 3; - %set/v v0xa388d0_0, 8, 3; + %set/v v0xffc5e0_0, 8, 3; %delay 1000000, 0; - %vpi_call 2 406 "$display", "%b | %b | %b - SLT | %b | XXXX | %b | %b | %b | %b", v0xa38650_0, v0xa38850_0, v0xa388d0_0, v0xa38950_0, v0xa38c80_0, v0xa38d00_0, v0xa38ad0_0, v0xa38750_0; - %set/v v0xa38650_0, 0, 4; - %set/v v0xa38850_0, 1, 4; + %vpi_call 2 407 "$display", "%b | %b | %b - SLT | %b | XXXX | %b | %b | %b | %b", v0xffc310_0, v0xffc560_0, v0xffc5e0_0, v0xffc660_0, v0xffcb10_0, v0xffcc10_0, v0xffc8f0_0, v0xffc430_0; + %movi 8, 2, 4; + %set/v v0xffc310_0, 8, 4; + %movi 8, 4, 4; + %set/v v0xffc560_0, 8, 4; + %movi 8, 3, 3; + %set/v v0xffc5e0_0, 8, 3; + %delay 1000000, 0; + %vpi_call 2 411 "$display", "%b | %b | %b - SLT | %b | XXXX | %b | %b | %b | %b", v0xffc310_0, v0xffc560_0, v0xffc5e0_0, v0xffc660_0, v0xffcb10_0, v0xffcc10_0, v0xffc8f0_0, v0xffc430_0; + %set/v v0xffc310_0, 0, 4; + %set/v v0xffc560_0, 1, 4; %movi 8, 4, 3; - %set/v v0xa388d0_0, 8, 3; + %set/v v0xffc5e0_0, 8, 3; %delay 1000000, 0; - %vpi_call 2 412 "$display", "%b | %b | %b - AND | %b | 0000 | %b | %b | %b | %b", v0xa38650_0, v0xa38850_0, v0xa388d0_0, v0xa38950_0, v0xa38c80_0, v0xa38d00_0, v0xa38ad0_0, v0xa38750_0; - %set/v v0xa38650_0, 1, 4; - %set/v v0xa38850_0, 1, 4; + %vpi_call 2 419 "$display", "%b | %b | %b - AND | %b | 0000 | %b | %b | %b | %b", v0xffc310_0, v0xffc560_0, v0xffc5e0_0, v0xffc660_0, v0xffcb10_0, v0xffcc10_0, v0xffc7e0_0, v0xffc430_0; + %set/v v0xffc310_0, 1, 4; + %set/v v0xffc560_0, 1, 4; %movi 8, 5, 3; - %set/v v0xa388d0_0, 8, 3; + %set/v v0xffc5e0_0, 8, 3; %delay 1000000, 0; - %vpi_call 2 415 "$display", "%b | %b | %b - NAND | %b | 0000 | %b | %b | %b | %b", v0xa38650_0, v0xa38850_0, v0xa388d0_0, v0xa38950_0, v0xa38c80_0, v0xa38d00_0, v0xa38ad0_0, v0xa38750_0; - %set/v v0xa38650_0, 0, 4; - %set/v v0xa38850_0, 0, 4; - %set/v v0xa388d0_0, 1, 3; + %vpi_call 2 422 "$display", "%b | %b | %b - NAND | %b | 0000 | %b | %b | %b | %b", v0xffc310_0, v0xffc560_0, v0xffc5e0_0, v0xffc660_0, v0xffcb10_0, v0xffcc10_0, v0xffc7e0_0, v0xffc430_0; + %set/v v0xffc310_0, 0, 4; + %set/v v0xffc560_0, 0, 4; + %set/v v0xffc5e0_0, 1, 3; %delay 1000000, 0; - %vpi_call 2 418 "$display", "%b | %b | %b - OR | %b | 0000 | %b | %b | %b | %b", v0xa38650_0, v0xa38850_0, v0xa388d0_0, v0xa38950_0, v0xa38c80_0, v0xa38d00_0, v0xa38ad0_0, v0xa38750_0; + %vpi_call 2 425 "$display", "%b | %b | %b - OR | %b | 0000 | %b | %b | %b | %b", v0xffc310_0, v0xffc560_0, v0xffc5e0_0, v0xffc660_0, v0xffcb10_0, v0xffcc10_0, v0xffc7e0_0, v0xffc430_0; %movi 8, 11, 4; - %set/v v0xa38650_0, 8, 4; + %set/v v0xffc310_0, 8, 4; %movi 8, 4, 4; - %set/v v0xa38850_0, 8, 4; + %set/v v0xffc560_0, 8, 4; %movi 8, 6, 3; - %set/v v0xa388d0_0, 8, 3; + %set/v v0xffc5e0_0, 8, 3; %delay 1000000, 0; - %vpi_call 2 420 "$display", "%b | %b | %b - NOR | %b | 0000 | %b | %b | %b | %b", v0xa38650_0, v0xa38850_0, v0xa388d0_0, v0xa38950_0, v0xa38c80_0, v0xa38d00_0, v0xa38ad0_0, v0xa38750_0; + %vpi_call 2 427 "$display", "%b | %b | %b - NOR | %b | 0000 | %b | %b | %b | %b", v0xffc310_0, v0xffc560_0, v0xffc5e0_0, v0xffc660_0, v0xffcb10_0, v0xffcc10_0, v0xffc7e0_0, v0xffc430_0; %movi 8, 11, 4; - %set/v v0xa38650_0, 8, 4; + %set/v v0xffc310_0, 8, 4; %movi 8, 11, 4; - %set/v v0xa38850_0, 8, 4; + %set/v v0xffc560_0, 8, 4; %movi 8, 2, 3; - %set/v v0xa388d0_0, 8, 3; + %set/v v0xffc5e0_0, 8, 3; %delay 1000000, 0; - %vpi_call 2 423 "$display", "%b | %b | %b - XOR | %b | 0000 | %b | %b | %b | %b", v0xa38650_0, v0xa38850_0, v0xa388d0_0, v0xa38950_0, v0xa38c80_0, v0xa38d00_0, v0xa38ad0_0, v0xa38750_0; + %vpi_call 2 430 "$display", "%b | %b | %b - XOR | %b | 0000 | %b | %b | %b | %b", v0xffc310_0, v0xffc560_0, v0xffc5e0_0, v0xffc660_0, v0xffcb10_0, v0xffcc10_0, v0xffc7e0_0, v0xffc430_0; %movi 8, 2, 4; - %set/v v0xa38650_0, 8, 4; + %set/v v0xffc310_0, 8, 4; %movi 8, 14, 4; - %set/v v0xa38850_0, 8, 4; - %set/v v0xa388d0_0, 0, 3; + %set/v v0xffc560_0, 8, 4; + %set/v v0xffc5e0_0, 0, 3; %delay 1000000, 0; - %vpi_call 2 426 "$display", "%b | %b | %b - ADD | %b | 0000 | %b | %b | %b | %b", v0xa38650_0, v0xa38850_0, v0xa388d0_0, v0xa38950_0, v0xa38c80_0, v0xa38d00_0, v0xa38ad0_0, v0xa38750_0; + %vpi_call 2 433 "$display", "%b | %b | %b - ADD | %b | 0000 | %b | %b | %b | %b", v0xffc310_0, v0xffc560_0, v0xffc5e0_0, v0xffc660_0, v0xffcb10_0, v0xffcc10_0, v0xffc7e0_0, v0xffc430_0; %movi 8, 2, 4; - %set/v v0xa38650_0, 8, 4; + %set/v v0xffc310_0, 8, 4; %movi 8, 2, 4; - %set/v v0xa38850_0, 8, 4; + %set/v v0xffc560_0, 8, 4; %movi 8, 1, 3; - %set/v v0xa388d0_0, 8, 3; + %set/v v0xffc5e0_0, 8, 3; %delay 1000000, 0; - %vpi_call 2 429 "$display", "%b | %b | %b - SUB | %b | 0000 | %b | %b | %b | %b", v0xa38650_0, v0xa38850_0, v0xa388d0_0, v0xa38950_0, v0xa38c80_0, v0xa38d00_0, v0xa38ad0_0, v0xa38750_0; - %set/v v0xa38650_0, 0, 4; - %set/v v0xa38850_0, 0, 4; + %vpi_call 2 436 "$display", "%b | %b | %b - SUB | %b | 0000 | %b | %b | %b | %b", v0xffc310_0, v0xffc560_0, v0xffc5e0_0, v0xffc660_0, v0xffcb10_0, v0xffcc10_0, v0xffc7e0_0, v0xffc430_0; + %set/v v0xffc310_0, 0, 4; + %set/v v0xffc560_0, 0, 4; %movi 8, 3, 3; - %set/v v0xa388d0_0, 8, 3; + %set/v v0xffc5e0_0, 8, 3; %delay 1000000, 0; - %vpi_call 2 433 "$display", "%b | %b | %b - SLT | %b | 0000 | %b | %b | %b | %b", v0xa38650_0, v0xa38850_0, v0xa388d0_0, v0xa38950_0, v0xa38c80_0, v0xa38d00_0, v0xa38ad0_0, v0xa38750_0; + %vpi_call 2 440 "$display", "%b | %b | %b - SLT | %b | 0000 | %b | %b | %b | %b", v0xffc310_0, v0xffc560_0, v0xffc5e0_0, v0xffc660_0, v0xffcb10_0, v0xffcc10_0, v0xffc7e0_0, v0xffc430_0; %end; .thread T_0; # The file index is used to find the file name in the following table. diff --git a/testing.t.v b/testing.t.v index cf46736..88a9987 100644 --- a/testing.t.v +++ b/testing.t.v @@ -125,14 +125,15 @@ endmodule module test32Adder(); parameter size = 4; -output [size-1:0] OneBitFinalOut; -output [size-1:0] OrNorXorOut; -output [size-1:0] AndNandOut; +wire [size-1:0] OneBitFinalOut; +wire [size-1:0] OrNorXorOut; +wire [size-1:0] AndNandOut; wire [size-1:0] AddSubSLTSum; wire [size-1:0] SLTSum; wire carryout; wire overflow; wire SLTflag; +wire SLTflag1; wire [size-1:0]ZeroFlag; wire AllZeros; wire [size-1:0] subtract; @@ -143,9 +144,9 @@ wire Cmd0Start [size-1:0]; wire Cmd1Start [size-1:0]; wire [size-1:0] CarryoutWire; -AddSubSLT32 trial(AddSubSLTSum, carryout, overflow, SLTflag, subtract, A, B, Command, carryin); +AddSubSLT32 trial(AddSubSLTSum, carryout, overflow, subtract, A, B, Command, carryin); -SLT32 test(SLTSum, carryout, overflow, SLTflag, subtract, A, B, Command, carryin); +SLT32 test2(SLTSum, carryout, overflow, SLTflag1, subtract, A, B, Command, carryin); AndNand32 trial1(AndNandOut, A, B, Command); @@ -231,39 +232,39 @@ $display(" A | B |Command| Out|ExpectedOut|Cout|OF |SLTflag"); // A < B, A > 0 | B > 0 | No Overflow | A = 2 = 0010 | B = 4 = 0100 A = 4'b0010; B = 4'b0100; Command =3'b011; #1000 -$display("%b | %b | %b | %b | Expect 1110| %b | %b | %b", A, B, Command, AddSubSLTSum, carryout, overflow, SLTflag); +$display("%b | %b | %b | %b | Expect 0001| %b | %b | %b", A, B, Command, SLTSum, carryout, overflow, SLTflag1); // A > B, A > 0 | B > 0 | No Overflow | A = 4 = 0100 | B = 2 = 0010 A = 4'b0100; B = 4'b0010; Command =3'b011; #1000 -$display("%b | %b | %b | %b | Expect 0010| %b | %b | %b", A, B, Command, AddSubSLTSum, carryout, overflow, SLTflag); +$display("%b | %b | %b | %b | Expect 0000| %b | %b | %b", A, B, Command, SLTSum, carryout, overflow, SLTflag1); // A < B, A < 0 | B > 0 | No Overflow | A = -2 = 1110 | B = 4 = 0100 A = 4'b1110; B = 4'b0100; Command =3'b011; #1000 -$display("%b | %b | %b | %b | Expect 1010| %b | %b | %b", A, B, Command, AddSubSLTSum, carryout, overflow, SLTflag); +$display("%b | %b | %b | %b | Expect 0001| %b | %b | %b", A, B, Command, SLTSum, carryout, overflow, SLTflag1); // A > B, A > 0 | B < 0 | No Overflow | A = 4 = 0100| B = -2 = 1110 A = 4'b0100; B = 4'b1110; Command =3'b011; #1000 -$display("%b | %b | %b | %b | Expect 0110| %b | %b | %b", A, B, Command, AddSubSLTSum, carryout, overflow, SLTflag); +$display("%b | %b | %b | %b | Expect 0000| %b | %b | %b", A, B, Command, SLTSum, carryout, overflow, SLTflag1); // A < B, A < 0 | B < 0 | No Overflow | A = -2 = 1110 | B = -1 = 1111 A = 4'b1110; B = 4'b1111; Command =3'b011; #1000 -$display("%b | %b | %b | %b | Expect 1111| %b | %b | %b", A, B, Command, AddSubSLTSum, carryout, overflow, SLTflag); +$display("%b | %b | %b | %b | Expect 0001| %b | %b | %b", A, B, Command, SLTSum, carryout, overflow, SLTflag1); // A > B, A < 0 | B < 0 | No Overflow | A = -1 = 1111 | B = -2 = 1110 A = 4'b1111; B = 4'b1110; Command =3'b011; #1000 -$display("%b | %b | %b | %b | Expect 0001| %b | %b | %b", A, B, Command, AddSubSLTSum, carryout, overflow, SLTflag); +$display("%b | %b | %b | %b | Expect 0000| %b | %b | %b", A, B, Command, SLTSum, carryout, overflow, SLTflag1); // A = B, A < 0 | B < 0 | No Overflow | A = -3 = 1101 | B = -3 = 1101 A = 4'b1101; B = 4'b1101; Command =3'b011; #1000 -$display("%b | %b | %b | %b | Expect 0000| %b | %b | %b", A, B, Command, AddSubSLTSum, carryout, overflow, SLTflag); +$display("%b | %b | %b | %b | Expect 0000| %b | %b | %b", A, B, Command, SLTSum, carryout, overflow, SLTflag1); // A = B, A > 0 | B > 0 | No Overflow | A = 5 = 0101 | B = 5 = 0101 A = 4'b0101; B = 4'b0101; Command =3'b011; #1000 -$display("%b | %b | %b | %b | Expect 0000| %b | %b | %b", A, B, Command, AddSubSLTSum, carryout, overflow, SLTflag); +$display("%b | %b | %b | %b | Expect 0000| %b | %b | %b", A, B, Command, SLTSum, carryout, overflow, SLTflag1); // A < B, A < 0 | B > 0 | Overflow | A = -7 = 1001 | B = 5 = 0101 A = 4'b1001; B = 4'b0101; Command =3'b011; #1000 -$display("%b | %b | %b | %b | Expect XXXX| %b | %b | %b", A, B, Command, AddSubSLTSum, carryout, overflow, SLTflag); +$display("%b | %b | %b | %b | Expect 0001| %b | %b | %b", A, B, Command, SLTSum, carryout, overflow, SLTflag1); $display("Test 4 Bit AND/NAND Functionality"); // there are too many possibilities even for just a four bit AND/NAND, which means we need to choose our test cases strategically. @@ -399,11 +400,17 @@ A = 4'b1001; B = 4'b0011; Command =3'b001; #1000 // A > B, A > 0 | B > 0 | No Overflow | A = 4 = 0100 | B = 2 = 0010 A = 4'b0100; B = 4'b0010; Command =3'b011; #1000 - $display("%b | %b | %b - SLT | %b | 0010 | %b | %b | %b | %b", A, B, Command, OneBitFinalOut, carryout, overflow, SLTflag, AllZeros); + $display("%b | %b | %b - SLT | %b | 0010 | %b | %b | %b | %b", A, B, Command, OneBitFinalOut, carryout, overflow, SLTflag1, AllZeros); // A < B, A < 0 | B > 0 | Overflow | A = -7 = 1001 | B = 5 = 0101 A = 4'b1001; B = 4'b0101; Command =3'b011; #1000 - $display("%b | %b | %b - SLT | %b | XXXX | %b | %b | %b | %b", A, B, Command, OneBitFinalOut, carryout, overflow, SLTflag, AllZeros); + $display("%b | %b | %b - SLT | %b | XXXX | %b | %b | %b | %b", A, B, Command, OneBitFinalOut, carryout, overflow, SLTflag1, AllZeros); + +// A < B, A < 0 | B > 0 | Overflow | A = 2 = 0010 | B = 4 = 0100 +A = 4'b0010; B = 4'b0100; Command =3'b011; #1000 + $display("%b | %b | %b - SLT | %b | XXXX | %b | %b | %b | %b", A, B, Command, OneBitFinalOut, carryout, overflow, SLTflag1, AllZeros); + + // Test Zero From daba44deb279553bfb7c55dadfd1d3bbd1bdcf87 Mon Sep 17 00:00:00 2001 From: mjakus Date: Tue, 10 Oct 2017 22:46:43 -0400 Subject: [PATCH 26/28] done with everything but cleanup/comments --- FullALU.vcd | 202534 ++++++++++++++++++++++++++++++++++++++++++------- alu.v | 113 +- test | 36129 ++++++++- testing.t.v | 20 +- 4 files changed, 207184 insertions(+), 31612 deletions(-) diff --git a/FullALU.vcd b/FullALU.vcd index bb76593..8f91102 100644 --- a/FullALU.vcd +++ b/FullALU.vcd @@ -1,5 +1,5 @@ $date - Tue Oct 10 20:57:35 2017 + Tue Oct 10 22:34:16 2017 $end $version Icarus Verilog @@ -8,29205 +8,174749 @@ $timescale 1ps $end $scope module test32Adder $end -$var wire 4 ! AddSubSLTSum [3:0] $end +$var wire 32 ! AddSubSLTSum [31:0] $end $var wire 1 " AllZeros $end -$var wire 4 # AndNandOut [3:0] $end -$var wire 4 $ OneBitFinalOut [3:0] $end -$var wire 4 % OrNorXorOut [3:0] $end -$var wire 4 & SLTSum [3:0] $end -$var wire 1 ' SLTflag $end -$var wire 1 ( SLTflag1 $end -$var wire 4 ) ZeroFlag [3:0] $end -$var wire 1 * carryout $end -$var wire 1 + overflow $end -$var wire 4 , subtract [3:0] $end -$var reg 4 - A [3:0] $end -$var reg 4 . B [3:0] $end -$var reg 3 / Command [2:0] $end -$var reg 4 0 carryin [3:0] $end +$var wire 1 # AllZeros2 $end +$var wire 32 $ AndNandOut [31:0] $end +$var wire 32 % OneBitFinalOut [31:0] $end +$var wire 32 & OneBitFinalOut2 [31:0] $end +$var wire 32 ' OrNorXorOut [31:0] $end +$var wire 32 ( SLTSum [31:0] $end +$var wire 1 ) SLTflag $end +$var wire 1 * SLTflag1 $end +$var wire 32 + ZeroFlag [31:0] $end +$var wire 1 , carryout $end +$var wire 1 - carryout2 $end +$var wire 1 . overflow $end +$var wire 1 / overflow2 $end +$var wire 32 0 subtract [31:0] $end +$var reg 32 1 A [31:0] $end +$var reg 32 2 B [31:0] $end +$var reg 3 3 Command [2:0] $end +$var reg 32 4 carryin [31:0] $end $scope module trial $end -$var wire 4 1 A [3:0] $end -$var wire 4 2 AddSubSLTSum [3:0] $end -$var wire 4 3 B [3:0] $end -$var wire 4 4 CarryoutWire [3:0] $end -$var wire 3 5 Command [2:0] $end -$var wire 4 6 carryin [3:0] $end -$var wire 1 * carryout $end -$var wire 1 + overflow $end -$var wire 4 7 subtract [3:0] $end +$var wire 32 5 A [31:0] $end +$var wire 32 6 AddSubSLTSum [31:0] $end +$var wire 32 7 B [31:0] $end +$var wire 32 8 CarryoutWire [31:0] $end +$var wire 3 9 Command [2:0] $end +$var wire 32 : carryin [31:0] $end +$var wire 1 , carryout $end +$var wire 1 . overflow $end +$var wire 32 ; subtract [31:0] $end $scope module attempt2 $end -$var wire 1 8 A $end -$var wire 1 9 AandB $end -$var wire 1 : AddSubSLTSum $end -$var wire 1 ; AxorB $end -$var wire 1 < B $end -$var wire 1 = BornB $end -$var wire 1 > CINandAxorB $end -$var wire 3 ? Command [2:0] $end -$var wire 1 @ carryin $end -$var wire 1 A carryout $end -$var wire 1 B nB $end -$var wire 1 C nCmd2 $end -$var wire 1 D subtract $end -$scope module mux0 $end -$var wire 1 E S $end -$var wire 1 < in0 $end -$var wire 1 B in1 $end -$var wire 1 F nS $end -$var wire 1 G out0 $end -$var wire 1 H out1 $end -$var wire 1 = outfinal $end +$var wire 1 < A $end +$var wire 1 = AandB $end +$var wire 1 > AddSubSLTSum $end +$var wire 1 ? AxorB $end +$var wire 1 @ B $end +$var wire 1 A BornB $end +$var wire 1 B CINandAxorB $end +$var wire 3 C Command [2:0] $end +$var wire 1 D carryin $end +$var wire 1 E carryout $end +$var wire 1 F nB $end +$var wire 1 G nCmd2 $end +$var wire 1 H subtract $end +$scope module mux0 $end +$var wire 1 I S $end +$var wire 1 @ in0 $end +$var wire 1 F in1 $end +$var wire 1 J nS $end +$var wire 1 K out0 $end +$var wire 1 L out1 $end +$var wire 1 A outfinal $end $upscope $end $upscope $end $scope begin addbits[1] $end $scope module attempt $end -$var wire 1 I A $end -$var wire 1 J AandB $end -$var wire 1 K AddSubSLTSum $end -$var wire 1 L AxorB $end -$var wire 1 M B $end -$var wire 1 N BornB $end -$var wire 1 O CINandAxorB $end -$var wire 3 P Command [2:0] $end -$var wire 1 Q carryin $end -$var wire 1 R carryout $end -$var wire 1 S nB $end -$var wire 1 T nCmd2 $end -$var wire 1 U subtract $end -$scope module mux0 $end -$var wire 1 V S $end -$var wire 1 M in0 $end -$var wire 1 S in1 $end -$var wire 1 W nS $end -$var wire 1 X out0 $end -$var wire 1 Y out1 $end -$var wire 1 N outfinal $end +$var wire 1 M A $end +$var wire 1 N AandB $end +$var wire 1 O AddSubSLTSum $end +$var wire 1 P AxorB $end +$var wire 1 Q B $end +$var wire 1 R BornB $end +$var wire 1 S CINandAxorB $end +$var wire 3 T Command [2:0] $end +$var wire 1 U carryin $end +$var wire 1 V carryout $end +$var wire 1 W nB $end +$var wire 1 X nCmd2 $end +$var wire 1 Y subtract $end +$scope module mux0 $end +$var wire 1 Z S $end +$var wire 1 Q in0 $end +$var wire 1 W in1 $end +$var wire 1 [ nS $end +$var wire 1 \ out0 $end +$var wire 1 ] out1 $end +$var wire 1 R outfinal $end $upscope $end $upscope $end $upscope $end $scope begin addbits[2] $end $scope module attempt $end -$var wire 1 Z A $end -$var wire 1 [ AandB $end -$var wire 1 \ AddSubSLTSum $end -$var wire 1 ] AxorB $end -$var wire 1 ^ B $end -$var wire 1 _ BornB $end -$var wire 1 ` CINandAxorB $end -$var wire 3 a Command [2:0] $end -$var wire 1 b carryin $end -$var wire 1 c carryout $end -$var wire 1 d nB $end -$var wire 1 e nCmd2 $end -$var wire 1 f subtract $end -$scope module mux0 $end -$var wire 1 g S $end -$var wire 1 ^ in0 $end -$var wire 1 d in1 $end -$var wire 1 h nS $end -$var wire 1 i out0 $end -$var wire 1 j out1 $end -$var wire 1 _ outfinal $end +$var wire 1 ^ A $end +$var wire 1 _ AandB $end +$var wire 1 ` AddSubSLTSum $end +$var wire 1 a AxorB $end +$var wire 1 b B $end +$var wire 1 c BornB $end +$var wire 1 d CINandAxorB $end +$var wire 3 e Command [2:0] $end +$var wire 1 f carryin $end +$var wire 1 g carryout $end +$var wire 1 h nB $end +$var wire 1 i nCmd2 $end +$var wire 1 j subtract $end +$scope module mux0 $end +$var wire 1 k S $end +$var wire 1 b in0 $end +$var wire 1 h in1 $end +$var wire 1 l nS $end +$var wire 1 m out0 $end +$var wire 1 n out1 $end +$var wire 1 c outfinal $end $upscope $end $upscope $end $upscope $end $scope begin addbits[3] $end $scope module attempt $end -$var wire 1 k A $end -$var wire 1 l AandB $end -$var wire 1 m AddSubSLTSum $end -$var wire 1 n AxorB $end -$var wire 1 o B $end -$var wire 1 p BornB $end -$var wire 1 q CINandAxorB $end -$var wire 3 r Command [2:0] $end -$var wire 1 s carryin $end -$var wire 1 t carryout $end -$var wire 1 u nB $end -$var wire 1 v nCmd2 $end -$var wire 1 w subtract $end +$var wire 1 o A $end +$var wire 1 p AandB $end +$var wire 1 q AddSubSLTSum $end +$var wire 1 r AxorB $end +$var wire 1 s B $end +$var wire 1 t BornB $end +$var wire 1 u CINandAxorB $end +$var wire 3 v Command [2:0] $end +$var wire 1 w carryin $end +$var wire 1 x carryout $end +$var wire 1 y nB $end +$var wire 1 z nCmd2 $end +$var wire 1 { subtract $end $scope module mux0 $end -$var wire 1 x S $end -$var wire 1 o in0 $end -$var wire 1 u in1 $end -$var wire 1 y nS $end -$var wire 1 z out0 $end -$var wire 1 { out1 $end -$var wire 1 p outfinal $end -$upscope $end +$var wire 1 | S $end +$var wire 1 s in0 $end +$var wire 1 y in1 $end +$var wire 1 } nS $end +$var wire 1 ~ out0 $end +$var wire 1 !" out1 $end +$var wire 1 t outfinal $end $upscope $end $upscope $end $upscope $end -$scope module test2 $end -$var wire 4 | A [3:0] $end -$var wire 4 } AddSubSLTSum [3:0] $end -$var wire 4 ~ B [3:0] $end -$var wire 4 !" CarryoutWire [3:0] $end -$var wire 3 "" Command [2:0] $end -$var wire 4 #" NewVal [3:0] $end -$var wire 1 $" Res0OF1 $end -$var wire 1 %" Res1OF0 $end -$var wire 4 &" SLTSum [3:0] $end -$var wire 1 ( SLTflag $end -$var wire 1 '" SLTflag0 $end -$var wire 1 (" SLTflag1 $end -$var wire 1 )" SLTon $end -$var wire 4 *" carryin [3:0] $end -$var wire 1 * carryout $end -$var wire 1 +" nAddSubSLTSum $end -$var wire 1 ," nCmd2 $end -$var wire 1 -" nOF $end -$var wire 1 + overflow $end -$var wire 4 ." subtract [3:0] $end -$scope module attempt2 $end -$var wire 1 /" A $end -$var wire 1 0" AandB $end -$var wire 1 1" AddSubSLTSum $end -$var wire 1 2" AxorB $end -$var wire 1 3" B $end -$var wire 1 4" BornB $end -$var wire 1 5" CINandAxorB $end -$var wire 3 6" Command [2:0] $end -$var wire 1 7" carryin $end -$var wire 1 8" carryout $end -$var wire 1 9" nB $end -$var wire 1 :" nCmd2 $end -$var wire 1 ;" subtract $end -$scope module mux0 $end -$var wire 1 <" S $end -$var wire 1 3" in0 $end -$var wire 1 9" in1 $end -$var wire 1 =" nS $end -$var wire 1 >" out0 $end -$var wire 1 ?" out1 $end -$var wire 1 4" outfinal $end -$upscope $end +$scope begin addbits[4] $end +$scope module attempt $end +$var wire 1 "" A $end +$var wire 1 #" AandB $end +$var wire 1 $" AddSubSLTSum $end +$var wire 1 %" AxorB $end +$var wire 1 &" B $end +$var wire 1 '" BornB $end +$var wire 1 (" CINandAxorB $end +$var wire 3 )" Command [2:0] $end +$var wire 1 *" carryin $end +$var wire 1 +" carryout $end +$var wire 1 ," nB $end +$var wire 1 -" nCmd2 $end +$var wire 1 ." subtract $end +$scope module mux0 $end +$var wire 1 /" S $end +$var wire 1 &" in0 $end +$var wire 1 ," in1 $end +$var wire 1 0" nS $end +$var wire 1 1" out0 $end +$var wire 1 2" out1 $end +$var wire 1 '" outfinal $end $upscope $end -$scope module setSLTresult $end -$var wire 1 )" S $end -$var wire 1 @" in0 $end -$var wire 1 A" in1 $end -$var wire 1 B" nS $end -$var wire 1 C" out0 $end -$var wire 1 D" out1 $end -$var wire 1 E" outfinal $end $upscope $end -$scope module FinalSLT $end -$var wire 1 ( S $end -$var wire 1 F" in0 $end -$var wire 1 ( in1 $end -$var wire 1 G" nS $end -$var wire 1 H" out0 $end -$var wire 1 I" out1 $end -$var wire 1 J" outfinal $end $upscope $end -$scope begin sltbits[1] $end +$scope begin addbits[5] $end $scope module attempt $end -$var wire 1 K" A $end -$var wire 1 L" AandB $end -$var wire 1 M" AddSubSLTSum $end -$var wire 1 N" AxorB $end -$var wire 1 O" B $end -$var wire 1 P" BornB $end -$var wire 1 Q" CINandAxorB $end -$var wire 3 R" Command [2:0] $end -$var wire 1 S" carryin $end -$var wire 1 T" carryout $end -$var wire 1 U" nB $end -$var wire 1 V" nCmd2 $end -$var wire 1 W" subtract $end -$scope module mux0 $end -$var wire 1 X" S $end -$var wire 1 O" in0 $end -$var wire 1 U" in1 $end -$var wire 1 Y" nS $end -$var wire 1 Z" out0 $end -$var wire 1 [" out1 $end -$var wire 1 P" outfinal $end -$upscope $end -$upscope $end -$scope module setSLTres2 $end -$var wire 1 )" S $end -$var wire 1 \" in0 $end -$var wire 1 ]" in1 $end -$var wire 1 ^" nS $end -$var wire 1 _" out0 $end -$var wire 1 `" out1 $end -$var wire 1 a" outfinal $end +$var wire 1 3" A $end +$var wire 1 4" AandB $end +$var wire 1 5" AddSubSLTSum $end +$var wire 1 6" AxorB $end +$var wire 1 7" B $end +$var wire 1 8" BornB $end +$var wire 1 9" CINandAxorB $end +$var wire 3 :" Command [2:0] $end +$var wire 1 ;" carryin $end +$var wire 1 <" carryout $end +$var wire 1 =" nB $end +$var wire 1 >" nCmd2 $end +$var wire 1 ?" subtract $end +$scope module mux0 $end +$var wire 1 @" S $end +$var wire 1 7" in0 $end +$var wire 1 =" in1 $end +$var wire 1 A" nS $end +$var wire 1 B" out0 $end +$var wire 1 C" out1 $end +$var wire 1 8" outfinal $end $upscope $end -$scope module setSLTres3 $end -$var wire 1 )" S $end -$var wire 1 b" in0 $end -$var wire 1 c" in1 $end -$var wire 1 d" nS $end -$var wire 1 e" out0 $end -$var wire 1 f" out1 $end -$var wire 1 g" outfinal $end $upscope $end $upscope $end -$scope begin sltbits[2] $end +$scope begin addbits[6] $end $scope module attempt $end -$var wire 1 h" A $end -$var wire 1 i" AandB $end -$var wire 1 j" AddSubSLTSum $end -$var wire 1 k" AxorB $end -$var wire 1 l" B $end -$var wire 1 m" BornB $end -$var wire 1 n" CINandAxorB $end -$var wire 3 o" Command [2:0] $end -$var wire 1 p" carryin $end -$var wire 1 q" carryout $end -$var wire 1 r" nB $end -$var wire 1 s" nCmd2 $end -$var wire 1 t" subtract $end -$scope module mux0 $end -$var wire 1 u" S $end -$var wire 1 l" in0 $end -$var wire 1 r" in1 $end -$var wire 1 v" nS $end -$var wire 1 w" out0 $end -$var wire 1 x" out1 $end -$var wire 1 m" outfinal $end +$var wire 1 D" A $end +$var wire 1 E" AandB $end +$var wire 1 F" AddSubSLTSum $end +$var wire 1 G" AxorB $end +$var wire 1 H" B $end +$var wire 1 I" BornB $end +$var wire 1 J" CINandAxorB $end +$var wire 3 K" Command [2:0] $end +$var wire 1 L" carryin $end +$var wire 1 M" carryout $end +$var wire 1 N" nB $end +$var wire 1 O" nCmd2 $end +$var wire 1 P" subtract $end +$scope module mux0 $end +$var wire 1 Q" S $end +$var wire 1 H" in0 $end +$var wire 1 N" in1 $end +$var wire 1 R" nS $end +$var wire 1 S" out0 $end +$var wire 1 T" out1 $end +$var wire 1 I" outfinal $end $upscope $end $upscope $end -$scope module setSLTres2 $end -$var wire 1 )" S $end -$var wire 1 y" in0 $end -$var wire 1 z" in1 $end -$var wire 1 {" nS $end -$var wire 1 |" out0 $end -$var wire 1 }" out1 $end -$var wire 1 ~" outfinal $end $upscope $end -$scope module setSLTres3 $end -$var wire 1 )" S $end -$var wire 1 !# in0 $end -$var wire 1 "# in1 $end -$var wire 1 ## nS $end -$var wire 1 $# out0 $end -$var wire 1 %# out1 $end -$var wire 1 &# outfinal $end +$scope begin addbits[7] $end +$scope module attempt $end +$var wire 1 U" A $end +$var wire 1 V" AandB $end +$var wire 1 W" AddSubSLTSum $end +$var wire 1 X" AxorB $end +$var wire 1 Y" B $end +$var wire 1 Z" BornB $end +$var wire 1 [" CINandAxorB $end +$var wire 3 \" Command [2:0] $end +$var wire 1 ]" carryin $end +$var wire 1 ^" carryout $end +$var wire 1 _" nB $end +$var wire 1 `" nCmd2 $end +$var wire 1 a" subtract $end +$scope module mux0 $end +$var wire 1 b" S $end +$var wire 1 Y" in0 $end +$var wire 1 _" in1 $end +$var wire 1 c" nS $end +$var wire 1 d" out0 $end +$var wire 1 e" out1 $end +$var wire 1 Z" outfinal $end $upscope $end $upscope $end -$scope begin sltbits[3] $end +$upscope $end +$scope begin addbits[8] $end $scope module attempt $end -$var wire 1 '# A $end -$var wire 1 (# AandB $end -$var wire 1 )# AddSubSLTSum $end -$var wire 1 *# AxorB $end -$var wire 1 +# B $end -$var wire 1 ,# BornB $end -$var wire 1 -# CINandAxorB $end -$var wire 3 .# Command [2:0] $end -$var wire 1 /# carryin $end -$var wire 1 0# carryout $end -$var wire 1 1# nB $end -$var wire 1 2# nCmd2 $end -$var wire 1 3# subtract $end -$scope module mux0 $end -$var wire 1 4# S $end -$var wire 1 +# in0 $end -$var wire 1 1# in1 $end -$var wire 1 5# nS $end -$var wire 1 6# out0 $end -$var wire 1 7# out1 $end -$var wire 1 ,# outfinal $end +$var wire 1 f" A $end +$var wire 1 g" AandB $end +$var wire 1 h" AddSubSLTSum $end +$var wire 1 i" AxorB $end +$var wire 1 j" B $end +$var wire 1 k" BornB $end +$var wire 1 l" CINandAxorB $end +$var wire 3 m" Command [2:0] $end +$var wire 1 n" carryin $end +$var wire 1 o" carryout $end +$var wire 1 p" nB $end +$var wire 1 q" nCmd2 $end +$var wire 1 r" subtract $end +$scope module mux0 $end +$var wire 1 s" S $end +$var wire 1 j" in0 $end +$var wire 1 p" in1 $end +$var wire 1 t" nS $end +$var wire 1 u" out0 $end +$var wire 1 v" out1 $end +$var wire 1 k" outfinal $end $upscope $end $upscope $end -$scope module setSLTres2 $end -$var wire 1 )" S $end -$var wire 1 8# in0 $end -$var wire 1 9# in1 $end -$var wire 1 :# nS $end -$var wire 1 ;# out0 $end -$var wire 1 <# out1 $end -$var wire 1 =# outfinal $end $upscope $end -$scope module setSLTres3 $end -$var wire 1 )" S $end -$var wire 1 ># in0 $end -$var wire 1 ?# in1 $end -$var wire 1 @# nS $end -$var wire 1 A# out0 $end -$var wire 1 B# out1 $end -$var wire 1 C# outfinal $end +$scope begin addbits[9] $end +$scope module attempt $end +$var wire 1 w" A $end +$var wire 1 x" AandB $end +$var wire 1 y" AddSubSLTSum $end +$var wire 1 z" AxorB $end +$var wire 1 {" B $end +$var wire 1 |" BornB $end +$var wire 1 }" CINandAxorB $end +$var wire 3 ~" Command [2:0] $end +$var wire 1 !# carryin $end +$var wire 1 "# carryout $end +$var wire 1 ## nB $end +$var wire 1 $# nCmd2 $end +$var wire 1 %# subtract $end +$scope module mux0 $end +$var wire 1 &# S $end +$var wire 1 {" in0 $end +$var wire 1 ## in1 $end +$var wire 1 '# nS $end +$var wire 1 (# out0 $end +$var wire 1 )# out1 $end +$var wire 1 |" outfinal $end $upscope $end $upscope $end $upscope $end -$scope module trial1 $end -$var wire 4 D# A [3:0] $end -$var wire 4 E# AndNandOut [3:0] $end -$var wire 4 F# B [3:0] $end -$var wire 3 G# Command [2:0] $end -$scope module attempt2 $end -$var wire 1 H# A $end -$var wire 1 I# AandB $end -$var wire 1 J# AnandB $end -$var wire 1 K# AndNandOut $end -$var wire 1 L# B $end -$var wire 3 M# Command [2:0] $end -$scope module potato $end -$var wire 1 N# S $end -$var wire 1 I# in0 $end -$var wire 1 J# in1 $end -$var wire 1 O# nS $end -$var wire 1 P# out0 $end -$var wire 1 Q# out1 $end -$var wire 1 K# outfinal $end +$scope begin addbits[10] $end +$scope module attempt $end +$var wire 1 *# A $end +$var wire 1 +# AandB $end +$var wire 1 ,# AddSubSLTSum $end +$var wire 1 -# AxorB $end +$var wire 1 .# B $end +$var wire 1 /# BornB $end +$var wire 1 0# CINandAxorB $end +$var wire 3 1# Command [2:0] $end +$var wire 1 2# carryin $end +$var wire 1 3# carryout $end +$var wire 1 4# nB $end +$var wire 1 5# nCmd2 $end +$var wire 1 6# subtract $end +$scope module mux0 $end +$var wire 1 7# S $end +$var wire 1 .# in0 $end +$var wire 1 4# in1 $end +$var wire 1 8# nS $end +$var wire 1 9# out0 $end +$var wire 1 :# out1 $end +$var wire 1 /# outfinal $end $upscope $end $upscope $end -$scope begin andbits[1] $end +$upscope $end +$scope begin addbits[11] $end $scope module attempt $end -$var wire 1 R# A $end -$var wire 1 S# AandB $end -$var wire 1 T# AnandB $end -$var wire 1 U# AndNandOut $end -$var wire 1 V# B $end -$var wire 3 W# Command [2:0] $end -$scope module potato $end -$var wire 1 X# S $end -$var wire 1 S# in0 $end -$var wire 1 T# in1 $end -$var wire 1 Y# nS $end -$var wire 1 Z# out0 $end -$var wire 1 [# out1 $end -$var wire 1 U# outfinal $end +$var wire 1 ;# A $end +$var wire 1 <# AandB $end +$var wire 1 =# AddSubSLTSum $end +$var wire 1 ># AxorB $end +$var wire 1 ?# B $end +$var wire 1 @# BornB $end +$var wire 1 A# CINandAxorB $end +$var wire 3 B# Command [2:0] $end +$var wire 1 C# carryin $end +$var wire 1 D# carryout $end +$var wire 1 E# nB $end +$var wire 1 F# nCmd2 $end +$var wire 1 G# subtract $end +$scope module mux0 $end +$var wire 1 H# S $end +$var wire 1 ?# in0 $end +$var wire 1 E# in1 $end +$var wire 1 I# nS $end +$var wire 1 J# out0 $end +$var wire 1 K# out1 $end +$var wire 1 @# outfinal $end $upscope $end $upscope $end $upscope $end -$scope begin andbits[2] $end +$scope begin addbits[12] $end $scope module attempt $end -$var wire 1 \# A $end -$var wire 1 ]# AandB $end -$var wire 1 ^# AnandB $end -$var wire 1 _# AndNandOut $end -$var wire 1 `# B $end -$var wire 3 a# Command [2:0] $end -$scope module potato $end -$var wire 1 b# S $end -$var wire 1 ]# in0 $end -$var wire 1 ^# in1 $end -$var wire 1 c# nS $end -$var wire 1 d# out0 $end -$var wire 1 e# out1 $end -$var wire 1 _# outfinal $end +$var wire 1 L# A $end +$var wire 1 M# AandB $end +$var wire 1 N# AddSubSLTSum $end +$var wire 1 O# AxorB $end +$var wire 1 P# B $end +$var wire 1 Q# BornB $end +$var wire 1 R# CINandAxorB $end +$var wire 3 S# Command [2:0] $end +$var wire 1 T# carryin $end +$var wire 1 U# carryout $end +$var wire 1 V# nB $end +$var wire 1 W# nCmd2 $end +$var wire 1 X# subtract $end +$scope module mux0 $end +$var wire 1 Y# S $end +$var wire 1 P# in0 $end +$var wire 1 V# in1 $end +$var wire 1 Z# nS $end +$var wire 1 [# out0 $end +$var wire 1 \# out1 $end +$var wire 1 Q# outfinal $end $upscope $end $upscope $end $upscope $end -$scope begin andbits[3] $end +$scope begin addbits[13] $end $scope module attempt $end -$var wire 1 f# A $end -$var wire 1 g# AandB $end -$var wire 1 h# AnandB $end -$var wire 1 i# AndNandOut $end -$var wire 1 j# B $end -$var wire 3 k# Command [2:0] $end -$scope module potato $end -$var wire 1 l# S $end -$var wire 1 g# in0 $end -$var wire 1 h# in1 $end -$var wire 1 m# nS $end -$var wire 1 n# out0 $end -$var wire 1 o# out1 $end -$var wire 1 i# outfinal $end -$upscope $end +$var wire 1 ]# A $end +$var wire 1 ^# AandB $end +$var wire 1 _# AddSubSLTSum $end +$var wire 1 `# AxorB $end +$var wire 1 a# B $end +$var wire 1 b# BornB $end +$var wire 1 c# CINandAxorB $end +$var wire 3 d# Command [2:0] $end +$var wire 1 e# carryin $end +$var wire 1 f# carryout $end +$var wire 1 g# nB $end +$var wire 1 h# nCmd2 $end +$var wire 1 i# subtract $end +$scope module mux0 $end +$var wire 1 j# S $end +$var wire 1 a# in0 $end +$var wire 1 g# in1 $end +$var wire 1 k# nS $end +$var wire 1 l# out0 $end +$var wire 1 m# out1 $end +$var wire 1 b# outfinal $end $upscope $end $upscope $end $upscope $end -$scope module trial2 $end -$var wire 4 p# A [3:0] $end -$var wire 4 q# B [3:0] $end -$var wire 3 r# Command [2:0] $end -$var wire 4 s# OrNorXorOut [3:0] $end -$scope module attempt2 $end -$var wire 1 t# A $end -$var wire 1 u# AnandB $end -$var wire 1 v# AnorB $end -$var wire 1 w# AorB $end -$var wire 1 x# AxorB $end -$var wire 1 y# B $end -$var wire 3 z# Command [2:0] $end -$var wire 1 {# OrNorXorOut $end -$var wire 1 |# XorNor $end -$var wire 1 }# nXor $end -$scope module mux0 $end -$var wire 1 ~# S $end -$var wire 1 x# in0 $end -$var wire 1 v# in1 $end -$var wire 1 !$ nS $end -$var wire 1 "$ out0 $end -$var wire 1 #$ out1 $end -$var wire 1 |# outfinal $end +$scope begin addbits[14] $end +$scope module attempt $end +$var wire 1 n# A $end +$var wire 1 o# AandB $end +$var wire 1 p# AddSubSLTSum $end +$var wire 1 q# AxorB $end +$var wire 1 r# B $end +$var wire 1 s# BornB $end +$var wire 1 t# CINandAxorB $end +$var wire 3 u# Command [2:0] $end +$var wire 1 v# carryin $end +$var wire 1 w# carryout $end +$var wire 1 x# nB $end +$var wire 1 y# nCmd2 $end +$var wire 1 z# subtract $end +$scope module mux0 $end +$var wire 1 {# S $end +$var wire 1 r# in0 $end +$var wire 1 x# in1 $end +$var wire 1 |# nS $end +$var wire 1 }# out0 $end +$var wire 1 ~# out1 $end +$var wire 1 s# outfinal $end $upscope $end -$scope module mux1 $end -$var wire 1 $$ S $end -$var wire 1 |# in0 $end -$var wire 1 w# in1 $end -$var wire 1 %$ nS $end -$var wire 1 &$ out0 $end -$var wire 1 '$ out1 $end -$var wire 1 {# outfinal $end $upscope $end $upscope $end -$scope begin orbits[1] $end +$scope begin addbits[15] $end $scope module attempt $end -$var wire 1 ($ A $end -$var wire 1 )$ AnandB $end -$var wire 1 *$ AnorB $end -$var wire 1 +$ AorB $end -$var wire 1 ,$ AxorB $end -$var wire 1 -$ B $end -$var wire 3 .$ Command [2:0] $end -$var wire 1 /$ OrNorXorOut $end -$var wire 1 0$ XorNor $end -$var wire 1 1$ nXor $end -$scope module mux0 $end -$var wire 1 2$ S $end -$var wire 1 ,$ in0 $end -$var wire 1 *$ in1 $end -$var wire 1 3$ nS $end -$var wire 1 4$ out0 $end -$var wire 1 5$ out1 $end -$var wire 1 0$ outfinal $end -$upscope $end -$scope module mux1 $end -$var wire 1 6$ S $end -$var wire 1 0$ in0 $end +$var wire 1 !$ A $end +$var wire 1 "$ AandB $end +$var wire 1 #$ AddSubSLTSum $end +$var wire 1 $$ AxorB $end +$var wire 1 %$ B $end +$var wire 1 &$ BornB $end +$var wire 1 '$ CINandAxorB $end +$var wire 3 ($ Command [2:0] $end +$var wire 1 )$ carryin $end +$var wire 1 *$ carryout $end +$var wire 1 +$ nB $end +$var wire 1 ,$ nCmd2 $end +$var wire 1 -$ subtract $end +$scope module mux0 $end +$var wire 1 .$ S $end +$var wire 1 %$ in0 $end $var wire 1 +$ in1 $end -$var wire 1 7$ nS $end -$var wire 1 8$ out0 $end -$var wire 1 9$ out1 $end -$var wire 1 /$ outfinal $end +$var wire 1 /$ nS $end +$var wire 1 0$ out0 $end +$var wire 1 1$ out1 $end +$var wire 1 &$ outfinal $end $upscope $end $upscope $end $upscope $end -$scope begin orbits[2] $end +$scope begin addbits[16] $end $scope module attempt $end -$var wire 1 :$ A $end -$var wire 1 ;$ AnandB $end -$var wire 1 <$ AnorB $end -$var wire 1 =$ AorB $end -$var wire 1 >$ AxorB $end -$var wire 1 ?$ B $end -$var wire 3 @$ Command [2:0] $end -$var wire 1 A$ OrNorXorOut $end -$var wire 1 B$ XorNor $end -$var wire 1 C$ nXor $end -$scope module mux0 $end -$var wire 1 D$ S $end -$var wire 1 >$ in0 $end +$var wire 1 2$ A $end +$var wire 1 3$ AandB $end +$var wire 1 4$ AddSubSLTSum $end +$var wire 1 5$ AxorB $end +$var wire 1 6$ B $end +$var wire 1 7$ BornB $end +$var wire 1 8$ CINandAxorB $end +$var wire 3 9$ Command [2:0] $end +$var wire 1 :$ carryin $end +$var wire 1 ;$ carryout $end +$var wire 1 <$ nB $end +$var wire 1 =$ nCmd2 $end +$var wire 1 >$ subtract $end +$scope module mux0 $end +$var wire 1 ?$ S $end +$var wire 1 6$ in0 $end $var wire 1 <$ in1 $end -$var wire 1 E$ nS $end -$var wire 1 F$ out0 $end -$var wire 1 G$ out1 $end -$var wire 1 B$ outfinal $end +$var wire 1 @$ nS $end +$var wire 1 A$ out0 $end +$var wire 1 B$ out1 $end +$var wire 1 7$ outfinal $end $upscope $end -$scope module mux1 $end -$var wire 1 H$ S $end -$var wire 1 B$ in0 $end -$var wire 1 =$ in1 $end -$var wire 1 I$ nS $end -$var wire 1 J$ out0 $end -$var wire 1 K$ out1 $end -$var wire 1 A$ outfinal $end +$upscope $end +$upscope $end +$scope begin addbits[17] $end +$scope module attempt $end +$var wire 1 C$ A $end +$var wire 1 D$ AandB $end +$var wire 1 E$ AddSubSLTSum $end +$var wire 1 F$ AxorB $end +$var wire 1 G$ B $end +$var wire 1 H$ BornB $end +$var wire 1 I$ CINandAxorB $end +$var wire 3 J$ Command [2:0] $end +$var wire 1 K$ carryin $end +$var wire 1 L$ carryout $end +$var wire 1 M$ nB $end +$var wire 1 N$ nCmd2 $end +$var wire 1 O$ subtract $end +$scope module mux0 $end +$var wire 1 P$ S $end +$var wire 1 G$ in0 $end +$var wire 1 M$ in1 $end +$var wire 1 Q$ nS $end +$var wire 1 R$ out0 $end +$var wire 1 S$ out1 $end +$var wire 1 H$ outfinal $end $upscope $end $upscope $end $upscope $end -$scope begin orbits[3] $end +$scope begin addbits[18] $end $scope module attempt $end -$var wire 1 L$ A $end -$var wire 1 M$ AnandB $end -$var wire 1 N$ AnorB $end -$var wire 1 O$ AorB $end -$var wire 1 P$ AxorB $end -$var wire 1 Q$ B $end -$var wire 3 R$ Command [2:0] $end -$var wire 1 S$ OrNorXorOut $end -$var wire 1 T$ XorNor $end -$var wire 1 U$ nXor $end -$scope module mux0 $end -$var wire 1 V$ S $end -$var wire 1 P$ in0 $end -$var wire 1 N$ in1 $end -$var wire 1 W$ nS $end -$var wire 1 X$ out0 $end -$var wire 1 Y$ out1 $end -$var wire 1 T$ outfinal $end +$var wire 1 T$ A $end +$var wire 1 U$ AandB $end +$var wire 1 V$ AddSubSLTSum $end +$var wire 1 W$ AxorB $end +$var wire 1 X$ B $end +$var wire 1 Y$ BornB $end +$var wire 1 Z$ CINandAxorB $end +$var wire 3 [$ Command [2:0] $end +$var wire 1 \$ carryin $end +$var wire 1 ]$ carryout $end +$var wire 1 ^$ nB $end +$var wire 1 _$ nCmd2 $end +$var wire 1 `$ subtract $end +$scope module mux0 $end +$var wire 1 a$ S $end +$var wire 1 X$ in0 $end +$var wire 1 ^$ in1 $end +$var wire 1 b$ nS $end +$var wire 1 c$ out0 $end +$var wire 1 d$ out1 $end +$var wire 1 Y$ outfinal $end $upscope $end -$scope module mux1 $end -$var wire 1 Z$ S $end -$var wire 1 T$ in0 $end -$var wire 1 O$ in1 $end -$var wire 1 [$ nS $end -$var wire 1 \$ out0 $end -$var wire 1 ]$ out1 $end -$var wire 1 S$ outfinal $end $upscope $end $upscope $end +$scope begin addbits[19] $end +$scope module attempt $end +$var wire 1 e$ A $end +$var wire 1 f$ AandB $end +$var wire 1 g$ AddSubSLTSum $end +$var wire 1 h$ AxorB $end +$var wire 1 i$ B $end +$var wire 1 j$ BornB $end +$var wire 1 k$ CINandAxorB $end +$var wire 3 l$ Command [2:0] $end +$var wire 1 m$ carryin $end +$var wire 1 n$ carryout $end +$var wire 1 o$ nB $end +$var wire 1 p$ nCmd2 $end +$var wire 1 q$ subtract $end +$scope module mux0 $end +$var wire 1 r$ S $end +$var wire 1 i$ in0 $end +$var wire 1 o$ in1 $end +$var wire 1 s$ nS $end +$var wire 1 t$ out0 $end +$var wire 1 u$ out1 $end +$var wire 1 j$ outfinal $end $upscope $end $upscope $end -$scope module superalu $end -$var wire 4 ^$ A [3:0] $end -$var wire 4 _$ AddSubSLTSum [3:0] $end -$var wire 1 " AllZeros $end -$var wire 4 `$ AndNandOut [3:0] $end -$var wire 4 a$ B [3:0] $end -$var wire 4 b$ Cmd0Start [3:0] $end -$var wire 4 c$ Cmd1Start [3:0] $end -$var wire 3 d$ Command [2:0] $end -$var wire 4 e$ OneBitFinalOut [3:0] $end -$var wire 4 f$ OrNorXorOut [3:0] $end -$var wire 4 g$ SLTSum [3:0] $end -$var wire 1 ' SLTflag $end -$var wire 4 h$ ZeroFlag [3:0] $end -$var wire 4 i$ carryin [3:0] $end -$var wire 1 * carryout $end -$var wire 1 + overflow $end -$var wire 4 j$ subtract [3:0] $end -$var wire 1 k$ yeszero $end -$scope module test $end -$var wire 4 l$ A [3:0] $end -$var wire 4 m$ AddSubSLTSum [3:0] $end -$var wire 4 n$ B [3:0] $end -$var wire 4 o$ CarryoutWire [3:0] $end -$var wire 3 p$ Command [2:0] $end -$var wire 4 q$ NewVal [3:0] $end -$var wire 1 r$ Res0OF1 $end -$var wire 1 s$ Res1OF0 $end -$var wire 4 t$ SLTSum [3:0] $end -$var wire 1 ' SLTflag $end -$var wire 1 u$ SLTflag0 $end -$var wire 1 v$ SLTflag1 $end -$var wire 1 w$ SLTon $end -$var wire 4 x$ carryin [3:0] $end -$var wire 1 * carryout $end -$var wire 1 y$ nAddSubSLTSum $end -$var wire 1 z$ nCmd2 $end -$var wire 1 {$ nOF $end -$var wire 1 + overflow $end -$var wire 4 |$ subtract [3:0] $end -$scope module attempt2 $end -$var wire 1 }$ A $end -$var wire 1 ~$ AandB $end -$var wire 1 !% AddSubSLTSum $end -$var wire 1 "% AxorB $end -$var wire 1 #% B $end -$var wire 1 $% BornB $end -$var wire 1 %% CINandAxorB $end -$var wire 3 &% Command [2:0] $end -$var wire 1 '% carryin $end -$var wire 1 (% carryout $end -$var wire 1 )% nB $end -$var wire 1 *% nCmd2 $end -$var wire 1 +% subtract $end -$scope module mux0 $end -$var wire 1 ,% S $end -$var wire 1 #% in0 $end -$var wire 1 )% in1 $end -$var wire 1 -% nS $end -$var wire 1 .% out0 $end -$var wire 1 /% out1 $end -$var wire 1 $% outfinal $end +$upscope $end +$scope begin addbits[20] $end +$scope module attempt $end +$var wire 1 v$ A $end +$var wire 1 w$ AandB $end +$var wire 1 x$ AddSubSLTSum $end +$var wire 1 y$ AxorB $end +$var wire 1 z$ B $end +$var wire 1 {$ BornB $end +$var wire 1 |$ CINandAxorB $end +$var wire 3 }$ Command [2:0] $end +$var wire 1 ~$ carryin $end +$var wire 1 !% carryout $end +$var wire 1 "% nB $end +$var wire 1 #% nCmd2 $end +$var wire 1 $% subtract $end +$scope module mux0 $end +$var wire 1 %% S $end +$var wire 1 z$ in0 $end +$var wire 1 "% in1 $end +$var wire 1 &% nS $end +$var wire 1 '% out0 $end +$var wire 1 (% out1 $end +$var wire 1 {$ outfinal $end $upscope $end $upscope $end -$scope module setSLTresult $end -$var wire 1 w$ S $end -$var wire 1 0% in0 $end -$var wire 1 1% in1 $end -$var wire 1 2% nS $end -$var wire 1 3% out0 $end -$var wire 1 4% out1 $end -$var wire 1 5% outfinal $end $upscope $end -$scope module FinalSLT $end -$var wire 1 ' S $end -$var wire 1 6% in0 $end -$var wire 1 ' in1 $end +$scope begin addbits[21] $end +$scope module attempt $end +$var wire 1 )% A $end +$var wire 1 *% AandB $end +$var wire 1 +% AddSubSLTSum $end +$var wire 1 ,% AxorB $end +$var wire 1 -% B $end +$var wire 1 .% BornB $end +$var wire 1 /% CINandAxorB $end +$var wire 3 0% Command [2:0] $end +$var wire 1 1% carryin $end +$var wire 1 2% carryout $end +$var wire 1 3% nB $end +$var wire 1 4% nCmd2 $end +$var wire 1 5% subtract $end +$scope module mux0 $end +$var wire 1 6% S $end +$var wire 1 -% in0 $end +$var wire 1 3% in1 $end $var wire 1 7% nS $end $var wire 1 8% out0 $end $var wire 1 9% out1 $end -$var wire 1 :% outfinal $end +$var wire 1 .% outfinal $end $upscope $end -$scope begin sltbits[1] $end -$scope module attempt $end -$var wire 1 ;% A $end -$var wire 1 <% AandB $end -$var wire 1 =% AddSubSLTSum $end -$var wire 1 >% AxorB $end -$var wire 1 ?% B $end -$var wire 1 @% BornB $end -$var wire 1 A% CINandAxorB $end -$var wire 3 B% Command [2:0] $end -$var wire 1 C% carryin $end -$var wire 1 D% carryout $end -$var wire 1 E% nB $end -$var wire 1 F% nCmd2 $end -$var wire 1 G% subtract $end -$scope module mux0 $end -$var wire 1 H% S $end -$var wire 1 ?% in0 $end -$var wire 1 E% in1 $end -$var wire 1 I% nS $end -$var wire 1 J% out0 $end -$var wire 1 K% out1 $end -$var wire 1 @% outfinal $end $upscope $end $upscope $end -$scope module setSLTres2 $end -$var wire 1 w$ S $end -$var wire 1 L% in0 $end -$var wire 1 M% in1 $end -$var wire 1 N% nS $end -$var wire 1 O% out0 $end -$var wire 1 P% out1 $end -$var wire 1 Q% outfinal $end +$scope begin addbits[22] $end +$scope module attempt $end +$var wire 1 :% A $end +$var wire 1 ;% AandB $end +$var wire 1 <% AddSubSLTSum $end +$var wire 1 =% AxorB $end +$var wire 1 >% B $end +$var wire 1 ?% BornB $end +$var wire 1 @% CINandAxorB $end +$var wire 3 A% Command [2:0] $end +$var wire 1 B% carryin $end +$var wire 1 C% carryout $end +$var wire 1 D% nB $end +$var wire 1 E% nCmd2 $end +$var wire 1 F% subtract $end +$scope module mux0 $end +$var wire 1 G% S $end +$var wire 1 >% in0 $end +$var wire 1 D% in1 $end +$var wire 1 H% nS $end +$var wire 1 I% out0 $end +$var wire 1 J% out1 $end +$var wire 1 ?% outfinal $end $upscope $end -$scope module setSLTres3 $end -$var wire 1 w$ S $end -$var wire 1 R% in0 $end -$var wire 1 S% in1 $end -$var wire 1 T% nS $end -$var wire 1 U% out0 $end -$var wire 1 V% out1 $end -$var wire 1 W% outfinal $end $upscope $end $upscope $end -$scope begin sltbits[2] $end +$scope begin addbits[23] $end $scope module attempt $end -$var wire 1 X% A $end -$var wire 1 Y% AandB $end -$var wire 1 Z% AddSubSLTSum $end -$var wire 1 [% AxorB $end -$var wire 1 \% B $end -$var wire 1 ]% BornB $end -$var wire 1 ^% CINandAxorB $end -$var wire 3 _% Command [2:0] $end -$var wire 1 `% carryin $end -$var wire 1 a% carryout $end -$var wire 1 b% nB $end -$var wire 1 c% nCmd2 $end -$var wire 1 d% subtract $end -$scope module mux0 $end -$var wire 1 e% S $end -$var wire 1 \% in0 $end -$var wire 1 b% in1 $end -$var wire 1 f% nS $end -$var wire 1 g% out0 $end -$var wire 1 h% out1 $end -$var wire 1 ]% outfinal $end -$upscope $end -$upscope $end -$scope module setSLTres2 $end -$var wire 1 w$ S $end -$var wire 1 i% in0 $end -$var wire 1 j% in1 $end -$var wire 1 k% nS $end -$var wire 1 l% out0 $end -$var wire 1 m% out1 $end -$var wire 1 n% outfinal $end +$var wire 1 K% A $end +$var wire 1 L% AandB $end +$var wire 1 M% AddSubSLTSum $end +$var wire 1 N% AxorB $end +$var wire 1 O% B $end +$var wire 1 P% BornB $end +$var wire 1 Q% CINandAxorB $end +$var wire 3 R% Command [2:0] $end +$var wire 1 S% carryin $end +$var wire 1 T% carryout $end +$var wire 1 U% nB $end +$var wire 1 V% nCmd2 $end +$var wire 1 W% subtract $end +$scope module mux0 $end +$var wire 1 X% S $end +$var wire 1 O% in0 $end +$var wire 1 U% in1 $end +$var wire 1 Y% nS $end +$var wire 1 Z% out0 $end +$var wire 1 [% out1 $end +$var wire 1 P% outfinal $end $upscope $end -$scope module setSLTres3 $end -$var wire 1 w$ S $end -$var wire 1 o% in0 $end -$var wire 1 p% in1 $end -$var wire 1 q% nS $end -$var wire 1 r% out0 $end -$var wire 1 s% out1 $end -$var wire 1 t% outfinal $end $upscope $end $upscope $end -$scope begin sltbits[3] $end +$scope begin addbits[24] $end $scope module attempt $end -$var wire 1 u% A $end -$var wire 1 v% AandB $end -$var wire 1 w% AddSubSLTSum $end -$var wire 1 x% AxorB $end -$var wire 1 y% B $end -$var wire 1 z% BornB $end -$var wire 1 {% CINandAxorB $end -$var wire 3 |% Command [2:0] $end -$var wire 1 }% carryin $end -$var wire 1 ~% carryout $end -$var wire 1 !& nB $end -$var wire 1 "& nCmd2 $end -$var wire 1 #& subtract $end -$scope module mux0 $end -$var wire 1 $& S $end -$var wire 1 y% in0 $end -$var wire 1 !& in1 $end -$var wire 1 %& nS $end -$var wire 1 && out0 $end -$var wire 1 '& out1 $end -$var wire 1 z% outfinal $end -$upscope $end -$upscope $end -$scope module setSLTres2 $end -$var wire 1 w$ S $end -$var wire 1 (& in0 $end -$var wire 1 )& in1 $end -$var wire 1 *& nS $end -$var wire 1 +& out0 $end -$var wire 1 ,& out1 $end -$var wire 1 -& outfinal $end +$var wire 1 \% A $end +$var wire 1 ]% AandB $end +$var wire 1 ^% AddSubSLTSum $end +$var wire 1 _% AxorB $end +$var wire 1 `% B $end +$var wire 1 a% BornB $end +$var wire 1 b% CINandAxorB $end +$var wire 3 c% Command [2:0] $end +$var wire 1 d% carryin $end +$var wire 1 e% carryout $end +$var wire 1 f% nB $end +$var wire 1 g% nCmd2 $end +$var wire 1 h% subtract $end +$scope module mux0 $end +$var wire 1 i% S $end +$var wire 1 `% in0 $end +$var wire 1 f% in1 $end +$var wire 1 j% nS $end +$var wire 1 k% out0 $end +$var wire 1 l% out1 $end +$var wire 1 a% outfinal $end $upscope $end -$scope module setSLTres3 $end -$var wire 1 w$ S $end -$var wire 1 .& in0 $end -$var wire 1 /& in1 $end -$var wire 1 0& nS $end -$var wire 1 1& out0 $end -$var wire 1 2& out1 $end -$var wire 1 3& outfinal $end $upscope $end $upscope $end +$scope begin addbits[25] $end +$scope module attempt $end +$var wire 1 m% A $end +$var wire 1 n% AandB $end +$var wire 1 o% AddSubSLTSum $end +$var wire 1 p% AxorB $end +$var wire 1 q% B $end +$var wire 1 r% BornB $end +$var wire 1 s% CINandAxorB $end +$var wire 3 t% Command [2:0] $end +$var wire 1 u% carryin $end +$var wire 1 v% carryout $end +$var wire 1 w% nB $end +$var wire 1 x% nCmd2 $end +$var wire 1 y% subtract $end +$scope module mux0 $end +$var wire 1 z% S $end +$var wire 1 q% in0 $end +$var wire 1 w% in1 $end +$var wire 1 {% nS $end +$var wire 1 |% out0 $end +$var wire 1 }% out1 $end +$var wire 1 r% outfinal $end $upscope $end -$scope module trial $end -$var wire 4 4& A [3:0] $end -$var wire 4 5& AddSubSLTSum [3:0] $end -$var wire 4 6& B [3:0] $end -$var wire 4 7& CarryoutWire [3:0] $end -$var wire 3 8& Command [2:0] $end -$var wire 4 9& carryin [3:0] $end -$var wire 1 * carryout $end -$var wire 1 + overflow $end -$var wire 4 :& subtract [3:0] $end -$scope module attempt2 $end -$var wire 1 ;& A $end -$var wire 1 <& AandB $end -$var wire 1 =& AddSubSLTSum $end -$var wire 1 >& AxorB $end -$var wire 1 ?& B $end -$var wire 1 @& BornB $end -$var wire 1 A& CINandAxorB $end -$var wire 3 B& Command [2:0] $end -$var wire 1 C& carryin $end -$var wire 1 D& carryout $end -$var wire 1 E& nB $end -$var wire 1 F& nCmd2 $end -$var wire 1 G& subtract $end -$scope module mux0 $end -$var wire 1 H& S $end -$var wire 1 ?& in0 $end -$var wire 1 E& in1 $end -$var wire 1 I& nS $end -$var wire 1 J& out0 $end -$var wire 1 K& out1 $end -$var wire 1 @& outfinal $end $upscope $end $upscope $end -$scope begin addbits[1] $end +$scope begin addbits[26] $end $scope module attempt $end -$var wire 1 L& A $end -$var wire 1 M& AandB $end -$var wire 1 N& AddSubSLTSum $end -$var wire 1 O& AxorB $end -$var wire 1 P& B $end -$var wire 1 Q& BornB $end -$var wire 1 R& CINandAxorB $end -$var wire 3 S& Command [2:0] $end -$var wire 1 T& carryin $end -$var wire 1 U& carryout $end -$var wire 1 V& nB $end -$var wire 1 W& nCmd2 $end -$var wire 1 X& subtract $end -$scope module mux0 $end -$var wire 1 Y& S $end -$var wire 1 P& in0 $end -$var wire 1 V& in1 $end -$var wire 1 Z& nS $end -$var wire 1 [& out0 $end -$var wire 1 \& out1 $end -$var wire 1 Q& outfinal $end +$var wire 1 ~% A $end +$var wire 1 !& AandB $end +$var wire 1 "& AddSubSLTSum $end +$var wire 1 #& AxorB $end +$var wire 1 $& B $end +$var wire 1 %& BornB $end +$var wire 1 && CINandAxorB $end +$var wire 3 '& Command [2:0] $end +$var wire 1 (& carryin $end +$var wire 1 )& carryout $end +$var wire 1 *& nB $end +$var wire 1 +& nCmd2 $end +$var wire 1 ,& subtract $end +$scope module mux0 $end +$var wire 1 -& S $end +$var wire 1 $& in0 $end +$var wire 1 *& in1 $end +$var wire 1 .& nS $end +$var wire 1 /& out0 $end +$var wire 1 0& out1 $end +$var wire 1 %& outfinal $end $upscope $end $upscope $end $upscope $end -$scope begin addbits[2] $end +$scope begin addbits[27] $end $scope module attempt $end -$var wire 1 ]& A $end -$var wire 1 ^& AandB $end -$var wire 1 _& AddSubSLTSum $end -$var wire 1 `& AxorB $end -$var wire 1 a& B $end -$var wire 1 b& BornB $end -$var wire 1 c& CINandAxorB $end -$var wire 3 d& Command [2:0] $end -$var wire 1 e& carryin $end -$var wire 1 f& carryout $end -$var wire 1 g& nB $end -$var wire 1 h& nCmd2 $end -$var wire 1 i& subtract $end -$scope module mux0 $end -$var wire 1 j& S $end -$var wire 1 a& in0 $end -$var wire 1 g& in1 $end -$var wire 1 k& nS $end -$var wire 1 l& out0 $end -$var wire 1 m& out1 $end -$var wire 1 b& outfinal $end +$var wire 1 1& A $end +$var wire 1 2& AandB $end +$var wire 1 3& AddSubSLTSum $end +$var wire 1 4& AxorB $end +$var wire 1 5& B $end +$var wire 1 6& BornB $end +$var wire 1 7& CINandAxorB $end +$var wire 3 8& Command [2:0] $end +$var wire 1 9& carryin $end +$var wire 1 :& carryout $end +$var wire 1 ;& nB $end +$var wire 1 <& nCmd2 $end +$var wire 1 =& subtract $end +$scope module mux0 $end +$var wire 1 >& S $end +$var wire 1 5& in0 $end +$var wire 1 ;& in1 $end +$var wire 1 ?& nS $end +$var wire 1 @& out0 $end +$var wire 1 A& out1 $end +$var wire 1 6& outfinal $end $upscope $end $upscope $end $upscope $end -$scope begin addbits[3] $end +$scope begin addbits[28] $end $scope module attempt $end -$var wire 1 n& A $end -$var wire 1 o& AandB $end -$var wire 1 p& AddSubSLTSum $end -$var wire 1 q& AxorB $end -$var wire 1 r& B $end -$var wire 1 s& BornB $end -$var wire 1 t& CINandAxorB $end -$var wire 3 u& Command [2:0] $end -$var wire 1 v& carryin $end -$var wire 1 w& carryout $end -$var wire 1 x& nB $end -$var wire 1 y& nCmd2 $end -$var wire 1 z& subtract $end +$var wire 1 B& A $end +$var wire 1 C& AandB $end +$var wire 1 D& AddSubSLTSum $end +$var wire 1 E& AxorB $end +$var wire 1 F& B $end +$var wire 1 G& BornB $end +$var wire 1 H& CINandAxorB $end +$var wire 3 I& Command [2:0] $end +$var wire 1 J& carryin $end +$var wire 1 K& carryout $end +$var wire 1 L& nB $end +$var wire 1 M& nCmd2 $end +$var wire 1 N& subtract $end $scope module mux0 $end -$var wire 1 {& S $end -$var wire 1 r& in0 $end -$var wire 1 x& in1 $end -$var wire 1 |& nS $end -$var wire 1 }& out0 $end -$var wire 1 ~& out1 $end -$var wire 1 s& outfinal $end +$var wire 1 O& S $end +$var wire 1 F& in0 $end +$var wire 1 L& in1 $end +$var wire 1 P& nS $end +$var wire 1 Q& out0 $end +$var wire 1 R& out1 $end +$var wire 1 G& outfinal $end $upscope $end $upscope $end $upscope $end +$scope begin addbits[29] $end +$scope module attempt $end +$var wire 1 S& A $end +$var wire 1 T& AandB $end +$var wire 1 U& AddSubSLTSum $end +$var wire 1 V& AxorB $end +$var wire 1 W& B $end +$var wire 1 X& BornB $end +$var wire 1 Y& CINandAxorB $end +$var wire 3 Z& Command [2:0] $end +$var wire 1 [& carryin $end +$var wire 1 \& carryout $end +$var wire 1 ]& nB $end +$var wire 1 ^& nCmd2 $end +$var wire 1 _& subtract $end +$scope module mux0 $end +$var wire 1 `& S $end +$var wire 1 W& in0 $end +$var wire 1 ]& in1 $end +$var wire 1 a& nS $end +$var wire 1 b& out0 $end +$var wire 1 c& out1 $end +$var wire 1 X& outfinal $end $upscope $end -$scope module trial1 $end -$var wire 4 !' A [3:0] $end -$var wire 4 "' AndNandOut [3:0] $end -$var wire 4 #' B [3:0] $end -$var wire 3 $' Command [2:0] $end -$scope module attempt2 $end -$var wire 1 %' A $end -$var wire 1 &' AandB $end -$var wire 1 '' AnandB $end -$var wire 1 (' AndNandOut $end -$var wire 1 )' B $end -$var wire 3 *' Command [2:0] $end -$scope module potato $end -$var wire 1 +' S $end -$var wire 1 &' in0 $end -$var wire 1 '' in1 $end -$var wire 1 ,' nS $end -$var wire 1 -' out0 $end -$var wire 1 .' out1 $end -$var wire 1 (' outfinal $end $upscope $end $upscope $end -$scope begin andbits[1] $end +$scope begin addbits[30] $end $scope module attempt $end -$var wire 1 /' A $end -$var wire 1 0' AandB $end -$var wire 1 1' AnandB $end -$var wire 1 2' AndNandOut $end -$var wire 1 3' B $end -$var wire 3 4' Command [2:0] $end -$scope module potato $end -$var wire 1 5' S $end -$var wire 1 0' in0 $end -$var wire 1 1' in1 $end -$var wire 1 6' nS $end -$var wire 1 7' out0 $end -$var wire 1 8' out1 $end -$var wire 1 2' outfinal $end +$var wire 1 d& A $end +$var wire 1 e& AandB $end +$var wire 1 f& AddSubSLTSum $end +$var wire 1 g& AxorB $end +$var wire 1 h& B $end +$var wire 1 i& BornB $end +$var wire 1 j& CINandAxorB $end +$var wire 3 k& Command [2:0] $end +$var wire 1 l& carryin $end +$var wire 1 m& carryout $end +$var wire 1 n& nB $end +$var wire 1 o& nCmd2 $end +$var wire 1 p& subtract $end +$scope module mux0 $end +$var wire 1 q& S $end +$var wire 1 h& in0 $end +$var wire 1 n& in1 $end +$var wire 1 r& nS $end +$var wire 1 s& out0 $end +$var wire 1 t& out1 $end +$var wire 1 i& outfinal $end $upscope $end $upscope $end $upscope $end -$scope begin andbits[2] $end +$scope begin addbits[31] $end $scope module attempt $end -$var wire 1 9' A $end -$var wire 1 :' AandB $end -$var wire 1 ;' AnandB $end -$var wire 1 <' AndNandOut $end -$var wire 1 =' B $end -$var wire 3 >' Command [2:0] $end -$scope module potato $end -$var wire 1 ?' S $end -$var wire 1 :' in0 $end -$var wire 1 ;' in1 $end -$var wire 1 @' nS $end -$var wire 1 A' out0 $end -$var wire 1 B' out1 $end -$var wire 1 <' outfinal $end +$var wire 1 u& A $end +$var wire 1 v& AandB $end +$var wire 1 w& AddSubSLTSum $end +$var wire 1 x& AxorB $end +$var wire 1 y& B $end +$var wire 1 z& BornB $end +$var wire 1 {& CINandAxorB $end +$var wire 3 |& Command [2:0] $end +$var wire 1 }& carryin $end +$var wire 1 ~& carryout $end +$var wire 1 !' nB $end +$var wire 1 "' nCmd2 $end +$var wire 1 #' subtract $end +$scope module mux0 $end +$var wire 1 $' S $end +$var wire 1 y& in0 $end +$var wire 1 !' in1 $end +$var wire 1 %' nS $end +$var wire 1 &' out0 $end +$var wire 1 '' out1 $end +$var wire 1 z& outfinal $end $upscope $end $upscope $end $upscope $end -$scope begin andbits[3] $end -$scope module attempt $end -$var wire 1 C' A $end -$var wire 1 D' AandB $end -$var wire 1 E' AnandB $end -$var wire 1 F' AndNandOut $end -$var wire 1 G' B $end -$var wire 3 H' Command [2:0] $end -$scope module potato $end -$var wire 1 I' S $end -$var wire 1 D' in0 $end -$var wire 1 E' in1 $end -$var wire 1 J' nS $end -$var wire 1 K' out0 $end -$var wire 1 L' out1 $end -$var wire 1 F' outfinal $end $upscope $end +$scope module test2 $end +$var wire 32 (' A [31:0] $end +$var wire 32 )' AddSubSLTSum [31:0] $end +$var wire 32 *' B [31:0] $end +$var wire 32 +' CarryoutWire [31:0] $end +$var wire 3 ,' Command [2:0] $end +$var wire 32 -' NewVal [31:0] $end +$var wire 1 .' Res0OF1 $end +$var wire 1 /' Res1OF0 $end +$var wire 32 0' SLTSum [31:0] $end +$var wire 1 * SLTflag $end +$var wire 1 1' SLTflag0 $end +$var wire 1 2' SLTflag1 $end +$var wire 1 3' SLTon $end +$var wire 32 4' carryin [31:0] $end +$var wire 1 , carryout $end +$var wire 1 5' nAddSubSLTSum $end +$var wire 1 6' nCmd2 $end +$var wire 1 7' nOF $end +$var wire 1 . overflow $end +$var wire 32 8' subtract [31:0] $end +$scope module attempt2 $end +$var wire 1 9' A $end +$var wire 1 :' AandB $end +$var wire 1 ;' AddSubSLTSum $end +$var wire 1 <' AxorB $end +$var wire 1 =' B $end +$var wire 1 >' BornB $end +$var wire 1 ?' CINandAxorB $end +$var wire 3 @' Command [2:0] $end +$var wire 1 A' carryin $end +$var wire 1 B' carryout $end +$var wire 1 C' nB $end +$var wire 1 D' nCmd2 $end +$var wire 1 E' subtract $end +$scope module mux0 $end +$var wire 1 F' S $end +$var wire 1 =' in0 $end +$var wire 1 C' in1 $end +$var wire 1 G' nS $end +$var wire 1 H' out0 $end +$var wire 1 I' out1 $end +$var wire 1 >' outfinal $end $upscope $end $upscope $end +$scope module setSLTresult $end +$var wire 1 3' S $end +$var wire 1 J' in0 $end +$var wire 1 K' in1 $end +$var wire 1 L' nS $end +$var wire 1 M' out0 $end +$var wire 1 N' out1 $end +$var wire 1 O' outfinal $end $upscope $end -$scope module trial2 $end -$var wire 4 M' A [3:0] $end -$var wire 4 N' B [3:0] $end -$var wire 3 O' Command [2:0] $end -$var wire 4 P' OrNorXorOut [3:0] $end -$scope module attempt2 $end -$var wire 1 Q' A $end -$var wire 1 R' AnandB $end -$var wire 1 S' AnorB $end -$var wire 1 T' AorB $end -$var wire 1 U' AxorB $end -$var wire 1 V' B $end -$var wire 3 W' Command [2:0] $end -$var wire 1 X' OrNorXorOut $end -$var wire 1 Y' XorNor $end -$var wire 1 Z' nXor $end -$scope module mux0 $end -$var wire 1 [' S $end -$var wire 1 U' in0 $end -$var wire 1 S' in1 $end -$var wire 1 \' nS $end -$var wire 1 ]' out0 $end -$var wire 1 ^' out1 $end -$var wire 1 Y' outfinal $end +$scope module FinalSLT $end +$var wire 1 * S $end +$var wire 1 P' in0 $end +$var wire 1 * in1 $end +$var wire 1 Q' nS $end +$var wire 1 R' out0 $end +$var wire 1 S' out1 $end +$var wire 1 T' outfinal $end $upscope $end -$scope module mux1 $end -$var wire 1 _' S $end +$scope begin sltbits[1] $end +$scope module attempt $end +$var wire 1 U' A $end +$var wire 1 V' AandB $end +$var wire 1 W' AddSubSLTSum $end +$var wire 1 X' AxorB $end +$var wire 1 Y' B $end +$var wire 1 Z' BornB $end +$var wire 1 [' CINandAxorB $end +$var wire 3 \' Command [2:0] $end +$var wire 1 ]' carryin $end +$var wire 1 ^' carryout $end +$var wire 1 _' nB $end +$var wire 1 `' nCmd2 $end +$var wire 1 a' subtract $end +$scope module mux0 $end +$var wire 1 b' S $end $var wire 1 Y' in0 $end -$var wire 1 T' in1 $end -$var wire 1 `' nS $end -$var wire 1 a' out0 $end -$var wire 1 b' out1 $end -$var wire 1 X' outfinal $end +$var wire 1 _' in1 $end +$var wire 1 c' nS $end +$var wire 1 d' out0 $end +$var wire 1 e' out1 $end +$var wire 1 Z' outfinal $end $upscope $end $upscope $end -$scope begin orbits[1] $end -$scope module attempt $end -$var wire 1 c' A $end -$var wire 1 d' AnandB $end -$var wire 1 e' AnorB $end -$var wire 1 f' AorB $end -$var wire 1 g' AxorB $end -$var wire 1 h' B $end -$var wire 3 i' Command [2:0] $end -$var wire 1 j' OrNorXorOut $end -$var wire 1 k' XorNor $end -$var wire 1 l' nXor $end -$scope module mux0 $end -$var wire 1 m' S $end -$var wire 1 g' in0 $end -$var wire 1 e' in1 $end +$scope module setSLTres2 $end +$var wire 1 3' S $end +$var wire 1 f' in0 $end +$var wire 1 g' in1 $end +$var wire 1 h' nS $end +$var wire 1 i' out0 $end +$var wire 1 j' out1 $end +$var wire 1 k' outfinal $end +$upscope $end +$scope module setSLTres3 $end +$var wire 1 3' S $end +$var wire 1 l' in0 $end +$var wire 1 m' in1 $end $var wire 1 n' nS $end $var wire 1 o' out0 $end $var wire 1 p' out1 $end -$var wire 1 k' outfinal $end -$upscope $end -$scope module mux1 $end -$var wire 1 q' S $end -$var wire 1 k' in0 $end -$var wire 1 f' in1 $end -$var wire 1 r' nS $end -$var wire 1 s' out0 $end -$var wire 1 t' out1 $end -$var wire 1 j' outfinal $end -$upscope $end +$var wire 1 q' outfinal $end $upscope $end $upscope $end -$scope begin orbits[2] $end +$scope begin sltbits[2] $end $scope module attempt $end -$var wire 1 u' A $end -$var wire 1 v' AnandB $end -$var wire 1 w' AnorB $end -$var wire 1 x' AorB $end -$var wire 1 y' AxorB $end -$var wire 1 z' B $end -$var wire 3 {' Command [2:0] $end -$var wire 1 |' OrNorXorOut $end -$var wire 1 }' XorNor $end -$var wire 1 ~' nXor $end +$var wire 1 r' A $end +$var wire 1 s' AandB $end +$var wire 1 t' AddSubSLTSum $end +$var wire 1 u' AxorB $end +$var wire 1 v' B $end +$var wire 1 w' BornB $end +$var wire 1 x' CINandAxorB $end +$var wire 3 y' Command [2:0] $end +$var wire 1 z' carryin $end +$var wire 1 {' carryout $end +$var wire 1 |' nB $end +$var wire 1 }' nCmd2 $end +$var wire 1 ~' subtract $end $scope module mux0 $end $var wire 1 !( S $end -$var wire 1 y' in0 $end -$var wire 1 w' in1 $end +$var wire 1 v' in0 $end +$var wire 1 |' in1 $end $var wire 1 "( nS $end $var wire 1 #( out0 $end $var wire 1 $( out1 $end -$var wire 1 }' outfinal $end +$var wire 1 w' outfinal $end $upscope $end -$scope module mux1 $end -$var wire 1 %( S $end -$var wire 1 }' in0 $end -$var wire 1 x' in1 $end -$var wire 1 &( nS $end -$var wire 1 '( out0 $end -$var wire 1 (( out1 $end -$var wire 1 |' outfinal $end $upscope $end +$scope module setSLTres2 $end +$var wire 1 3' S $end +$var wire 1 %( in0 $end +$var wire 1 &( in1 $end +$var wire 1 '( nS $end +$var wire 1 (( out0 $end +$var wire 1 )( out1 $end +$var wire 1 *( outfinal $end +$upscope $end +$scope module setSLTres3 $end +$var wire 1 3' S $end +$var wire 1 +( in0 $end +$var wire 1 ,( in1 $end +$var wire 1 -( nS $end +$var wire 1 .( out0 $end +$var wire 1 /( out1 $end +$var wire 1 0( outfinal $end $upscope $end $upscope $end -$scope begin orbits[3] $end +$scope begin sltbits[3] $end $scope module attempt $end -$var wire 1 )( A $end -$var wire 1 *( AnandB $end -$var wire 1 +( AnorB $end -$var wire 1 ,( AorB $end -$var wire 1 -( AxorB $end -$var wire 1 .( B $end -$var wire 3 /( Command [2:0] $end -$var wire 1 0( OrNorXorOut $end -$var wire 1 1( XorNor $end -$var wire 1 2( nXor $end -$scope module mux0 $end -$var wire 1 3( S $end -$var wire 1 -( in0 $end -$var wire 1 +( in1 $end -$var wire 1 4( nS $end -$var wire 1 5( out0 $end -$var wire 1 6( out1 $end -$var wire 1 1( outfinal $end +$var wire 1 1( A $end +$var wire 1 2( AandB $end +$var wire 1 3( AddSubSLTSum $end +$var wire 1 4( AxorB $end +$var wire 1 5( B $end +$var wire 1 6( BornB $end +$var wire 1 7( CINandAxorB $end +$var wire 3 8( Command [2:0] $end +$var wire 1 9( carryin $end +$var wire 1 :( carryout $end +$var wire 1 ;( nB $end +$var wire 1 <( nCmd2 $end +$var wire 1 =( subtract $end +$scope module mux0 $end +$var wire 1 >( S $end +$var wire 1 5( in0 $end +$var wire 1 ;( in1 $end +$var wire 1 ?( nS $end +$var wire 1 @( out0 $end +$var wire 1 A( out1 $end +$var wire 1 6( outfinal $end $upscope $end -$scope module mux1 $end -$var wire 1 7( S $end -$var wire 1 1( in0 $end -$var wire 1 ,( in1 $end -$var wire 1 8( nS $end -$var wire 1 9( out0 $end -$var wire 1 :( out1 $end -$var wire 1 0( outfinal $end $upscope $end +$scope module setSLTres2 $end +$var wire 1 3' S $end +$var wire 1 B( in0 $end +$var wire 1 C( in1 $end +$var wire 1 D( nS $end +$var wire 1 E( out0 $end +$var wire 1 F( out1 $end +$var wire 1 G( outfinal $end $upscope $end +$scope module setSLTres3 $end +$var wire 1 3' S $end +$var wire 1 H( in0 $end +$var wire 1 I( in1 $end +$var wire 1 J( nS $end +$var wire 1 K( out0 $end +$var wire 1 L( out1 $end +$var wire 1 M( outfinal $end $upscope $end $upscope $end -$scope module ZeroMux0case $end -$var wire 1 ;( S0 $end -$var wire 1 <( S1 $end -$var wire 1 =( in0 $end -$var wire 1 >( in1 $end -$var wire 1 ?( in2 $end -$var wire 1 @( in3 $end -$var wire 1 A( nS0 $end -$var wire 1 B( nS1 $end -$var wire 1 C( out $end -$var wire 1 D( out0 $end -$var wire 1 E( out1 $end -$var wire 1 F( out2 $end -$var wire 1 G( out3 $end +$scope begin sltbits[4] $end +$scope module attempt $end +$var wire 1 N( A $end +$var wire 1 O( AandB $end +$var wire 1 P( AddSubSLTSum $end +$var wire 1 Q( AxorB $end +$var wire 1 R( B $end +$var wire 1 S( BornB $end +$var wire 1 T( CINandAxorB $end +$var wire 3 U( Command [2:0] $end +$var wire 1 V( carryin $end +$var wire 1 W( carryout $end +$var wire 1 X( nB $end +$var wire 1 Y( nCmd2 $end +$var wire 1 Z( subtract $end +$scope module mux0 $end +$var wire 1 [( S $end +$var wire 1 R( in0 $end +$var wire 1 X( in1 $end +$var wire 1 \( nS $end +$var wire 1 ]( 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-b1001 #" -1w% -b1001 q$ -1p& -b1001 ! -b1001 2 -b1001 _$ -b1001 5& -0+ -#34130000 -1-" -1{$ -#34140000 -0$# -1H" -0r% -18% -1;# -1+& -0$" -0r$ -#34150000 -1%" -1s$ -#34160000 -0$) -1@( -1># -1?# -1.& -1/& -0&# -1J" -0t% -1:% -b1 & -b1 &" -b1 g$ -b1 t$ -1=# -b1001 } -1-& -b1001 m$ -#34170000 -1+) -0G( -0+" -0y$ -#34180000 -0:) -1V( -0') -1C( -b1 b$ -1A# -11& -#34200000 -1E) -1C# -13& -b1001 & -b1001 &" -b1001 g$ -b1001 t$ -#34210000 -0L) -#34220000 -1[) -1H) -b1001 b$ -#35000000 -0^ -0< -0l" -03" -0`# -0L# -0?$ -0y# -0\% -0#% -0a& -0?& -0=' -0)' -0z' -0V' -0Z -0h" -0\# -0:$ -0X% -0]& -09' -0u' -b0 . -b0 3 -b0 ~ -b0 F# -b0 q# -b0 a$ -b0 n$ -b0 6& -b0 #' -b0 N' -b1011 - -b1011 1 -b1011 | -b1011 D# -b1011 p# -b1011 ^$ -b1011 l$ -b1011 4& -b1011 !' -b1011 M' -#35010000 -1d -1B -1r" -19" -1J# -1u# -1b% -1)% -1g& -1E& -1'' -1R' -1^# -1<$ -1;$ -1;' -1w' -1v' -#35020000 -0I# -0}# -0&' -0Z' -0]# -0=$ -0C$ -0:' -0x' -0~' -#35030000 -1x# -1U' -1C$ -1>$ -1~' -1y' -1j -1H -1x" -1?" -1Q# -1h% -1/% -1m& -1K& -1.' -1e# -1G$ -1B' -1$( -#35040000 -0>$ -0y' -0K$ -0(( -0] -0k" -0[% -0`& -#35050000 -1J( -1K( -1.) -1/) -1_ -1= -1m" -14" -1K# -1]% -1$% -1b& -1@& -1(' -1_# -1B$ -1<' -b1111 # -b1111 E# -b1111 `$ -b1111 "' -1}' -#35060000 -0#) -00) -01) -0A$ -0|' -b1011 % -b1011 s# -b1011 f$ -b1011 P' -0` -0n" -0^% -0c& -#35070000 -18) -19 -10" -1~$ -1<& -#35080000 -0;) -0s -0/# -0}% -0v& -1y" -1i% -1!) -1") -04) -b1011 c$ -0c -b1010 4 -0q" -b1010 !" -0a% -b1010 o$ -0f& -b1010 7& -1\ -1j" -b1101 #" -1Z% -b1101 q$ -1_& -b1101 ! -b1101 2 -b1101 _$ -b1101 5& -#35090000 -1Q -1S" -1C% -1T& -1A -b1011 4 -18" -b1011 !" -1(% -b1011 o$ -1D& -b1011 7& -1] -0; -1k" -02" -1[% -0"% -1`& -0>& -#35100000 -0>) -1|" -1l% -#35110000 -1` -1n" -1^% -1c& -#35120000 -1!# -1"# -1o% -1p% -08# -0(& -0B) -0C) -0?) -b1011 $ -b1011 e$ -1~" -b1101 } -1n% -b1101 m$ -0m -0)# -b101 #" -0w% -b101 q$ -0p& -b101 ! -b101 2 -b101 _$ -b101 5& -1+ -#35130000 -1s -1/# -1}% -1v& -1\" -1L% -1^( -1_( -0y" -0@" -0i% -00% -0!) -0") -0=( -0>( -0-" -0{$ -1c -b1111 4 -1q" -b1111 !" -1a% -b1111 o$ -1f& -b1111 7& -1K -1M" -1=% -1N& -0\ -0: -0j" -01" -b10 #" -0Z% -0!% -b10 q$ -0_& -0=& -b10 ! -b10 2 -b10 _$ -b10 5& -#35140000 -1$# -1r% -0;# -0%" -0+& -0s$ -#35150000 -1_" -1O% -0|" -0C" -0l% -03% -#35160000 -1$) -0># -0?# -0.& -0/& -1&# -1t% -b1101 & -b1101 &" -b1101 g$ -b1101 t$ -0=# -b101 } -0-& -b101 m$ -#35170000 -1b" -1c" -1R% -1S% -0!# -0"# -0F" -0o% -0p% -06% -18# -1(& -1B) -1C) -0+) -1+" -1y$ -1a" -1Q% -0~" -0E" -b10 } -0n% -05% -b10 m$ -1m -1)# -b1010 #" -1w% -b1010 q$ -1p& -b1010 ! -b1010 2 -b1010 _$ -b1010 5& -0+ -#35180000 -1:) -1') -b1101 b$ -1-" -1{$ -0A# -01& -#35190000 -1e" -1U% -0$# -0H" -0r% -08% -1;# -1+& -#35200000 -0E) -1%" -1s$ -0C# -03& -b101 & -b101 &" -b101 g$ -b101 t$ -#35210000 -1a( -0$) -0@( -1># -1?# -1.& -1/& -1L) -1g" -1W% -0&# -0J" -0t% -0:% -b10 & -b10 &" -b10 g$ -b10 t$ -1=# -b1010 } -1-& -b1010 m$ -#35220000 -0[) -0h( -1+) -1G( -0+" -0y$ -0H) -b101 b$ -#35230000 -1w( -0:) -0V( -1d( -0') -0C( -b10 b$ -1A# -11& -#35250000 -1E) -1C# -13& -b1010 & -b1010 &" -b1010 g$ -b1010 t$ -#35260000 -0L) -#35270000 -1[) -1H) -b1010 b$ -#36000000 -0E -0V -0g -0x -0<" -0X" -0u" -04# -0N# -0X# -0b# -0l# -0$$ -06$ -0H$ -0Z$ -0\( -0i( +$scope begin sltbits[8] $end +$scope module attempt $end +$var wire 1 d) A $end +$var wire 1 e) AandB $end +$var wire 1 f) AddSubSLTSum $end +$var wire 1 g) AxorB $end +$var wire 1 h) B $end +$var wire 1 i) BornB $end +$var wire 1 j) CINandAxorB $end +$var wire 3 k) Command [2:0] $end +$var wire 1 l) carryin $end +$var wire 1 m) carryout $end +$var wire 1 n) nB $end +$var wire 1 o) nCmd2 $end +$var wire 1 p) subtract $end +$scope module mux0 $end +$var wire 1 q) S $end +$var wire 1 h) in0 $end +$var wire 1 n) in1 $end +$var wire 1 r) nS $end +$var wire 1 s) out0 $end +$var wire 1 t) out1 $end +$var wire 1 i) outfinal $end +$upscope $end +$upscope $end +$scope module setSLTres2 $end +$var wire 1 3' S $end +$var wire 1 u) in0 $end +$var wire 1 v) in1 $end +$var wire 1 w) nS $end +$var wire 1 x) out0 $end +$var wire 1 y) out1 $end +$var wire 1 z) outfinal $end +$upscope $end +$scope module setSLTres3 $end +$var wire 1 3' S $end +$var wire 1 {) in0 $end +$var wire 1 |) in1 $end +$var wire 1 }) nS $end +$var wire 1 ~) out0 $end +$var wire 1 !* out1 $end +$var wire 1 "* outfinal $end +$upscope $end +$upscope $end +$scope begin sltbits[9] $end +$scope module attempt $end +$var wire 1 #* A $end +$var wire 1 $* AandB $end +$var wire 1 %* AddSubSLTSum $end +$var wire 1 &* AxorB $end +$var wire 1 '* B $end +$var wire 1 (* BornB $end +$var wire 1 )* CINandAxorB $end +$var wire 3 ** Command [2:0] $end +$var wire 1 +* carryin $end +$var wire 1 ,* carryout $end +$var wire 1 -* nB $end +$var wire 1 .* nCmd2 $end +$var wire 1 /* subtract $end +$scope module mux0 $end +$var wire 1 0* S $end +$var wire 1 '* in0 $end +$var wire 1 -* in1 $end +$var wire 1 1* nS $end +$var wire 1 2* out0 $end +$var wire 1 3* out1 $end +$var wire 1 (* outfinal $end +$upscope $end +$upscope $end +$scope module setSLTres2 $end +$var wire 1 3' S $end +$var wire 1 4* in0 $end +$var wire 1 5* in1 $end +$var wire 1 6* nS $end +$var wire 1 7* out0 $end +$var wire 1 8* out1 $end +$var wire 1 9* outfinal $end +$upscope $end +$scope module setSLTres3 $end +$var wire 1 3' S $end +$var wire 1 :* in0 $end +$var wire 1 ;* in1 $end +$var wire 1 <* nS $end +$var wire 1 =* out0 $end +$var wire 1 >* out1 $end +$var wire 1 ?* outfinal $end +$upscope $end +$upscope $end +$scope begin sltbits[10] $end +$scope module attempt $end +$var wire 1 @* A $end +$var wire 1 A* AandB $end +$var wire 1 B* AddSubSLTSum $end +$var wire 1 C* AxorB $end +$var wire 1 D* B $end +$var wire 1 E* BornB $end +$var wire 1 F* CINandAxorB $end +$var wire 3 G* Command [2:0] $end +$var wire 1 H* carryin $end +$var wire 1 I* carryout $end +$var wire 1 J* nB $end +$var wire 1 K* nCmd2 $end +$var wire 1 L* subtract $end +$scope module mux0 $end +$var wire 1 M* S $end +$var wire 1 D* in0 $end +$var wire 1 J* in1 $end +$var wire 1 N* nS $end +$var wire 1 O* out0 $end +$var wire 1 P* out1 $end +$var wire 1 E* outfinal $end +$upscope $end +$upscope $end +$scope module setSLTres2 $end +$var wire 1 3' S $end +$var wire 1 Q* in0 $end +$var wire 1 R* in1 $end +$var wire 1 S* nS $end +$var wire 1 T* out0 $end +$var wire 1 U* out1 $end +$var wire 1 V* outfinal $end +$upscope $end +$scope module setSLTres3 $end +$var wire 1 3' S $end +$var wire 1 W* in0 $end +$var wire 1 X* in1 $end +$var wire 1 Y* nS $end +$var wire 1 Z* out0 $end +$var wire 1 [* out1 $end +$var wire 1 \* outfinal $end +$upscope $end +$upscope $end +$scope begin sltbits[11] $end +$scope module attempt $end +$var wire 1 ]* A $end +$var wire 1 ^* AandB $end +$var wire 1 _* AddSubSLTSum $end +$var wire 1 `* AxorB $end +$var wire 1 a* B $end +$var wire 1 b* BornB $end +$var wire 1 c* CINandAxorB $end +$var wire 3 d* Command [2:0] $end +$var wire 1 e* carryin $end +$var wire 1 f* carryout $end +$var wire 1 g* nB $end +$var wire 1 h* nCmd2 $end +$var wire 1 i* subtract $end +$scope module mux0 $end +$var wire 1 j* S $end +$var wire 1 a* in0 $end +$var wire 1 g* in1 $end +$var wire 1 k* nS $end +$var wire 1 l* out0 $end +$var wire 1 m* out1 $end +$var wire 1 b* outfinal $end +$upscope $end +$upscope $end +$scope module setSLTres2 $end +$var wire 1 3' S $end +$var wire 1 n* in0 $end +$var wire 1 o* in1 $end +$var wire 1 p* nS $end +$var wire 1 q* out0 $end +$var wire 1 r* out1 $end +$var wire 1 s* outfinal $end +$upscope $end +$scope module setSLTres3 $end +$var wire 1 3' S $end +$var wire 1 t* in0 $end +$var wire 1 u* in1 $end +$var wire 1 v* nS $end +$var wire 1 w* out0 $end +$var wire 1 x* out1 $end +$var wire 1 y* outfinal $end +$upscope $end +$upscope $end +$scope begin sltbits[12] $end +$scope module attempt $end +$var wire 1 z* A $end +$var wire 1 {* AandB $end +$var wire 1 |* AddSubSLTSum $end +$var wire 1 }* AxorB $end +$var wire 1 ~* B $end +$var wire 1 !+ BornB $end +$var wire 1 "+ CINandAxorB $end +$var wire 3 #+ Command [2:0] $end +$var wire 1 $+ carryin $end +$var wire 1 %+ carryout $end +$var wire 1 &+ nB $end +$var wire 1 '+ nCmd2 $end +$var wire 1 (+ subtract $end +$scope module mux0 $end +$var wire 1 )+ S $end +$var wire 1 ~* in0 $end +$var wire 1 &+ in1 $end +$var wire 1 *+ nS $end +$var wire 1 ++ out0 $end +$var wire 1 ,+ out1 $end +$var wire 1 !+ outfinal $end +$upscope $end +$upscope $end +$scope module setSLTres2 $end +$var wire 1 3' S $end +$var wire 1 -+ in0 $end +$var wire 1 .+ in1 $end +$var wire 1 /+ nS $end +$var wire 1 0+ out0 $end +$var wire 1 1+ out1 $end +$var wire 1 2+ outfinal $end +$upscope $end +$scope module setSLTres3 $end +$var wire 1 3' S $end +$var wire 1 3+ in0 $end +$var wire 1 4+ in1 $end +$var wire 1 5+ nS $end +$var wire 1 6+ out0 $end +$var wire 1 7+ out1 $end +$var wire 1 8+ outfinal $end +$upscope $end +$upscope $end +$scope begin sltbits[13] $end +$scope module attempt $end +$var wire 1 9+ A $end +$var wire 1 :+ AandB $end +$var wire 1 ;+ AddSubSLTSum $end +$var wire 1 <+ AxorB $end +$var wire 1 =+ B $end +$var wire 1 >+ BornB $end +$var wire 1 ?+ CINandAxorB $end +$var wire 3 @+ Command [2:0] $end +$var wire 1 A+ carryin $end +$var wire 1 B+ carryout $end +$var wire 1 C+ nB $end +$var wire 1 D+ nCmd2 $end +$var wire 1 E+ subtract $end +$scope module mux0 $end +$var wire 1 F+ S $end +$var wire 1 =+ in0 $end +$var wire 1 C+ in1 $end +$var wire 1 G+ nS $end +$var wire 1 H+ out0 $end +$var wire 1 I+ out1 $end +$var wire 1 >+ outfinal $end +$upscope $end +$upscope $end +$scope module setSLTres2 $end +$var wire 1 3' S $end +$var wire 1 J+ in0 $end +$var wire 1 K+ in1 $end +$var wire 1 L+ nS $end +$var wire 1 M+ out0 $end +$var wire 1 N+ out1 $end +$var wire 1 O+ outfinal $end +$upscope $end +$scope module setSLTres3 $end +$var wire 1 3' S $end +$var wire 1 P+ in0 $end +$var wire 1 Q+ in1 $end +$var wire 1 R+ nS $end +$var wire 1 S+ out0 $end +$var wire 1 T+ out1 $end +$var wire 1 U+ outfinal $end +$upscope $end +$upscope $end +$scope begin sltbits[14] $end +$scope module attempt $end +$var wire 1 V+ A $end +$var wire 1 W+ AandB $end +$var wire 1 X+ AddSubSLTSum $end +$var wire 1 Y+ AxorB $end +$var wire 1 Z+ B $end +$var wire 1 [+ BornB $end +$var wire 1 \+ CINandAxorB $end +$var wire 3 ]+ Command [2:0] $end +$var wire 1 ^+ carryin $end +$var wire 1 _+ carryout $end +$var wire 1 `+ nB $end +$var wire 1 a+ nCmd2 $end +$var wire 1 b+ subtract $end +$scope module mux0 $end +$var wire 1 c+ S $end +$var wire 1 Z+ in0 $end +$var wire 1 `+ in1 $end +$var wire 1 d+ nS $end +$var wire 1 e+ out0 $end +$var wire 1 f+ out1 $end +$var wire 1 [+ outfinal $end +$upscope $end +$upscope $end +$scope module setSLTres2 $end +$var wire 1 3' S $end +$var wire 1 g+ in0 $end +$var wire 1 h+ in1 $end +$var wire 1 i+ nS $end +$var wire 1 j+ out0 $end +$var wire 1 k+ out1 $end +$var wire 1 l+ outfinal $end +$upscope $end +$scope module setSLTres3 $end +$var wire 1 3' S $end +$var wire 1 m+ in0 $end +$var wire 1 n+ in1 $end +$var wire 1 o+ nS $end +$var wire 1 p+ out0 $end +$var wire 1 q+ out1 $end +$var wire 1 r+ outfinal $end +$upscope $end +$upscope $end +$scope begin sltbits[15] $end +$scope module attempt $end +$var wire 1 s+ A $end +$var wire 1 t+ AandB $end +$var wire 1 u+ AddSubSLTSum $end +$var wire 1 v+ AxorB $end +$var wire 1 w+ B $end +$var wire 1 x+ BornB $end +$var wire 1 y+ CINandAxorB $end +$var wire 3 z+ Command [2:0] $end +$var wire 1 {+ carryin $end +$var wire 1 |+ carryout $end +$var wire 1 }+ nB $end +$var wire 1 ~+ nCmd2 $end +$var wire 1 !, subtract $end +$scope module mux0 $end +$var wire 1 ", S $end +$var wire 1 w+ in0 $end +$var wire 1 }+ in1 $end +$var wire 1 #, nS $end +$var wire 1 $, out0 $end +$var wire 1 %, out1 $end +$var wire 1 x+ outfinal $end +$upscope $end +$upscope $end +$scope module setSLTres2 $end +$var wire 1 3' S $end +$var wire 1 &, in0 $end +$var wire 1 ', in1 $end +$var wire 1 (, nS $end +$var wire 1 ), out0 $end +$var wire 1 *, out1 $end +$var wire 1 +, outfinal $end +$upscope $end +$scope module setSLTres3 $end +$var wire 1 3' S $end +$var wire 1 ,, in0 $end +$var wire 1 -, in1 $end +$var wire 1 ., nS $end +$var wire 1 /, out0 $end +$var wire 1 0, out1 $end +$var wire 1 1, outfinal $end +$upscope $end +$upscope $end +$scope begin sltbits[16] $end +$scope module attempt $end +$var wire 1 2, A $end +$var wire 1 3, AandB $end +$var wire 1 4, AddSubSLTSum $end +$var wire 1 5, AxorB $end +$var wire 1 6, B $end +$var wire 1 7, BornB $end +$var wire 1 8, CINandAxorB $end +$var wire 3 9, Command [2:0] $end +$var wire 1 :, carryin $end +$var wire 1 ;, carryout $end +$var wire 1 <, nB $end +$var wire 1 =, nCmd2 $end +$var wire 1 >, subtract $end +$scope module mux0 $end +$var wire 1 ?, S $end +$var wire 1 6, in0 $end +$var wire 1 <, in1 $end +$var wire 1 @, nS $end +$var wire 1 A, out0 $end +$var wire 1 B, out1 $end +$var wire 1 7, outfinal $end +$upscope $end +$upscope $end +$scope module setSLTres2 $end +$var wire 1 3' S $end +$var wire 1 C, in0 $end +$var wire 1 D, in1 $end +$var wire 1 E, nS $end +$var wire 1 F, out0 $end +$var wire 1 G, out1 $end +$var wire 1 H, outfinal $end +$upscope $end +$scope module setSLTres3 $end +$var wire 1 3' S $end +$var wire 1 I, in0 $end +$var wire 1 J, in1 $end +$var wire 1 K, nS $end +$var wire 1 L, out0 $end +$var wire 1 M, out1 $end +$var wire 1 N, outfinal $end +$upscope $end +$upscope $end +$scope begin sltbits[17] $end +$scope module attempt $end +$var wire 1 O, A $end +$var wire 1 P, AandB $end +$var wire 1 Q, AddSubSLTSum $end +$var wire 1 R, AxorB $end +$var wire 1 S, B $end +$var wire 1 T, BornB $end +$var wire 1 U, CINandAxorB $end +$var wire 3 V, Command [2:0] $end +$var wire 1 W, carryin $end +$var wire 1 X, carryout $end +$var wire 1 Y, nB $end +$var wire 1 Z, nCmd2 $end +$var wire 1 [, subtract $end +$scope module mux0 $end +$var wire 1 \, S $end +$var wire 1 S, in0 $end +$var wire 1 Y, in1 $end +$var wire 1 ], nS $end +$var wire 1 ^, out0 $end +$var wire 1 _, out1 $end +$var wire 1 T, outfinal $end +$upscope $end +$upscope $end +$scope module setSLTres2 $end +$var wire 1 3' S $end +$var wire 1 `, in0 $end +$var wire 1 a, in1 $end +$var wire 1 b, nS $end +$var wire 1 c, out0 $end +$var wire 1 d, out1 $end +$var wire 1 e, outfinal $end +$upscope $end +$scope module setSLTres3 $end +$var wire 1 3' S $end +$var wire 1 f, in0 $end +$var wire 1 g, in1 $end +$var wire 1 h, nS $end +$var wire 1 i, out0 $end +$var wire 1 j, out1 $end +$var wire 1 k, outfinal $end +$upscope $end +$upscope $end +$scope begin sltbits[18] $end +$scope module attempt $end +$var wire 1 l, A $end +$var wire 1 m, AandB $end +$var wire 1 n, AddSubSLTSum $end +$var wire 1 o, AxorB $end +$var wire 1 p, B $end +$var wire 1 q, BornB $end +$var wire 1 r, CINandAxorB $end +$var wire 3 s, Command [2:0] $end +$var wire 1 t, carryin $end +$var wire 1 u, carryout $end +$var wire 1 v, nB $end +$var wire 1 w, nCmd2 $end +$var wire 1 x, subtract $end +$scope module mux0 $end +$var wire 1 y, S $end +$var wire 1 p, in0 $end +$var wire 1 v, in1 $end +$var wire 1 z, nS $end +$var wire 1 {, out0 $end +$var wire 1 |, out1 $end +$var wire 1 q, outfinal $end +$upscope $end +$upscope $end +$scope module setSLTres2 $end +$var wire 1 3' S $end +$var wire 1 }, in0 $end +$var wire 1 ~, in1 $end +$var wire 1 !- nS $end +$var wire 1 "- out0 $end +$var wire 1 #- out1 $end +$var wire 1 $- outfinal $end +$upscope $end +$scope module setSLTres3 $end +$var wire 1 3' S $end +$var wire 1 %- in0 $end +$var wire 1 &- in1 $end +$var wire 1 '- nS $end +$var wire 1 (- out0 $end +$var wire 1 )- out1 $end +$var wire 1 *- outfinal $end +$upscope $end +$upscope $end +$scope begin sltbits[19] $end +$scope module attempt $end +$var wire 1 +- A $end +$var wire 1 ,- AandB $end +$var wire 1 -- AddSubSLTSum $end +$var wire 1 .- AxorB $end +$var wire 1 /- B $end +$var wire 1 0- BornB $end +$var wire 1 1- CINandAxorB $end +$var wire 3 2- Command [2:0] $end +$var wire 1 3- carryin $end +$var wire 1 4- carryout $end +$var wire 1 5- nB $end +$var wire 1 6- nCmd2 $end +$var wire 1 7- subtract $end +$scope module mux0 $end +$var wire 1 8- S $end +$var wire 1 /- in0 $end +$var wire 1 5- in1 $end +$var wire 1 9- nS $end +$var wire 1 :- out0 $end +$var wire 1 ;- out1 $end +$var wire 1 0- outfinal $end +$upscope $end +$upscope $end +$scope module setSLTres2 $end +$var wire 1 3' S $end +$var wire 1 <- in0 $end +$var wire 1 =- in1 $end +$var wire 1 >- nS $end +$var wire 1 ?- out0 $end +$var wire 1 @- out1 $end +$var wire 1 A- outfinal $end +$upscope $end +$scope module setSLTres3 $end +$var wire 1 3' S $end +$var wire 1 B- in0 $end +$var wire 1 C- in1 $end +$var wire 1 D- nS $end +$var wire 1 E- out0 $end +$var wire 1 F- out1 $end +$var wire 1 G- outfinal $end +$upscope $end +$upscope $end +$scope begin sltbits[20] $end +$scope module attempt $end +$var wire 1 H- A $end +$var wire 1 I- AandB $end +$var wire 1 J- AddSubSLTSum $end +$var wire 1 K- AxorB $end +$var wire 1 L- B $end +$var wire 1 M- BornB $end +$var wire 1 N- CINandAxorB $end +$var wire 3 O- Command [2:0] $end +$var wire 1 P- carryin $end +$var wire 1 Q- carryout $end +$var wire 1 R- nB $end +$var wire 1 S- nCmd2 $end +$var wire 1 T- subtract $end +$scope module mux0 $end +$var wire 1 U- S $end +$var wire 1 L- in0 $end +$var wire 1 R- in1 $end +$var wire 1 V- nS $end +$var wire 1 W- out0 $end +$var wire 1 X- out1 $end +$var wire 1 M- outfinal $end +$upscope $end +$upscope $end +$scope module setSLTres2 $end +$var wire 1 3' S $end +$var wire 1 Y- in0 $end +$var wire 1 Z- in1 $end +$var wire 1 [- nS $end +$var wire 1 \- out0 $end +$var wire 1 ]- out1 $end +$var wire 1 ^- outfinal $end +$upscope $end +$scope module setSLTres3 $end +$var wire 1 3' S $end +$var wire 1 _- in0 $end +$var wire 1 `- in1 $end +$var wire 1 a- nS $end +$var wire 1 b- out0 $end +$var wire 1 c- out1 $end +$var wire 1 d- outfinal $end +$upscope $end +$upscope $end +$scope begin sltbits[21] $end +$scope module attempt $end +$var wire 1 e- A $end +$var wire 1 f- AandB $end +$var wire 1 g- AddSubSLTSum $end +$var wire 1 h- AxorB $end +$var wire 1 i- B $end +$var wire 1 j- BornB $end +$var wire 1 k- CINandAxorB $end +$var wire 3 l- Command [2:0] $end +$var wire 1 m- carryin $end +$var wire 1 n- carryout $end +$var wire 1 o- nB $end +$var wire 1 p- nCmd2 $end +$var wire 1 q- subtract $end +$scope module mux0 $end +$var wire 1 r- S $end +$var wire 1 i- in0 $end +$var wire 1 o- in1 $end +$var wire 1 s- nS $end +$var wire 1 t- out0 $end +$var wire 1 u- out1 $end +$var wire 1 j- outfinal $end +$upscope $end +$upscope $end +$scope module setSLTres2 $end +$var wire 1 3' S $end +$var wire 1 v- in0 $end +$var wire 1 w- in1 $end +$var wire 1 x- nS $end +$var wire 1 y- out0 $end +$var wire 1 z- out1 $end +$var wire 1 {- outfinal $end +$upscope $end +$scope module setSLTres3 $end +$var wire 1 3' S $end +$var wire 1 |- in0 $end +$var wire 1 }- in1 $end +$var wire 1 ~- nS $end +$var wire 1 !. out0 $end +$var wire 1 ". out1 $end +$var wire 1 #. outfinal $end +$upscope $end +$upscope $end +$scope begin sltbits[22] $end +$scope module attempt $end +$var wire 1 $. A $end +$var wire 1 %. AandB $end +$var wire 1 &. AddSubSLTSum $end +$var wire 1 '. AxorB $end +$var wire 1 (. B $end +$var wire 1 ). BornB $end +$var wire 1 *. CINandAxorB $end +$var wire 3 +. Command [2:0] $end +$var wire 1 ,. carryin $end +$var wire 1 -. carryout $end +$var wire 1 .. nB $end +$var wire 1 /. nCmd2 $end +$var wire 1 0. subtract $end +$scope module mux0 $end +$var wire 1 1. S $end +$var wire 1 (. in0 $end +$var wire 1 .. in1 $end +$var wire 1 2. nS $end +$var wire 1 3. out0 $end +$var wire 1 4. out1 $end +$var wire 1 ). outfinal $end +$upscope $end +$upscope $end +$scope module setSLTres2 $end +$var wire 1 3' S $end +$var wire 1 5. in0 $end +$var wire 1 6. in1 $end +$var wire 1 7. nS $end +$var wire 1 8. out0 $end +$var wire 1 9. out1 $end +$var wire 1 :. outfinal $end +$upscope $end +$scope module setSLTres3 $end +$var wire 1 3' S $end +$var wire 1 ;. in0 $end +$var wire 1 <. in1 $end +$var wire 1 =. nS $end +$var wire 1 >. out0 $end +$var wire 1 ?. out1 $end +$var wire 1 @. outfinal $end +$upscope $end +$upscope $end +$scope begin sltbits[23] $end +$scope module attempt $end +$var wire 1 A. A $end +$var wire 1 B. AandB $end +$var wire 1 C. AddSubSLTSum $end +$var wire 1 D. AxorB $end +$var wire 1 E. B $end +$var wire 1 F. BornB $end +$var wire 1 G. CINandAxorB $end +$var wire 3 H. Command [2:0] $end +$var wire 1 I. carryin $end +$var wire 1 J. carryout $end +$var wire 1 K. nB $end +$var wire 1 L. nCmd2 $end +$var wire 1 M. subtract $end +$scope module mux0 $end +$var wire 1 N. S $end +$var wire 1 E. in0 $end +$var wire 1 K. in1 $end +$var wire 1 O. nS $end +$var wire 1 P. out0 $end +$var wire 1 Q. out1 $end +$var wire 1 F. outfinal $end +$upscope $end +$upscope $end +$scope module setSLTres2 $end +$var wire 1 3' S $end +$var wire 1 R. in0 $end +$var wire 1 S. in1 $end +$var wire 1 T. nS $end +$var wire 1 U. out0 $end +$var wire 1 V. out1 $end +$var wire 1 W. outfinal $end +$upscope $end +$scope module setSLTres3 $end +$var wire 1 3' S $end +$var wire 1 X. in0 $end +$var wire 1 Y. in1 $end +$var wire 1 Z. nS $end +$var wire 1 [. out0 $end +$var wire 1 \. out1 $end +$var wire 1 ]. outfinal $end +$upscope $end +$upscope $end +$scope begin sltbits[24] $end +$scope module attempt $end +$var wire 1 ^. A $end +$var wire 1 _. AandB $end +$var wire 1 `. AddSubSLTSum $end +$var wire 1 a. AxorB $end +$var wire 1 b. B $end +$var wire 1 c. BornB $end +$var wire 1 d. CINandAxorB $end +$var wire 3 e. Command [2:0] $end +$var wire 1 f. carryin $end +$var wire 1 g. carryout $end +$var wire 1 h. nB $end +$var wire 1 i. nCmd2 $end +$var wire 1 j. subtract $end +$scope module mux0 $end +$var wire 1 k. S $end +$var wire 1 b. in0 $end +$var wire 1 h. in1 $end +$var wire 1 l. nS $end +$var wire 1 m. out0 $end +$var wire 1 n. out1 $end +$var wire 1 c. outfinal $end +$upscope $end +$upscope $end +$scope module setSLTres2 $end +$var wire 1 3' S $end +$var wire 1 o. in0 $end +$var wire 1 p. in1 $end +$var wire 1 q. nS $end +$var wire 1 r. out0 $end +$var wire 1 s. out1 $end +$var wire 1 t. outfinal $end +$upscope $end +$scope module setSLTres3 $end +$var wire 1 3' S $end +$var wire 1 u. in0 $end +$var wire 1 v. in1 $end +$var wire 1 w. nS $end +$var wire 1 x. out0 $end +$var wire 1 y. out1 $end +$var wire 1 z. outfinal $end +$upscope $end +$upscope $end +$scope begin sltbits[25] $end +$scope module attempt $end +$var wire 1 {. A $end +$var wire 1 |. AandB $end +$var wire 1 }. AddSubSLTSum $end +$var wire 1 ~. AxorB $end +$var wire 1 !/ B $end +$var wire 1 "/ BornB $end +$var wire 1 #/ CINandAxorB $end +$var wire 3 $/ Command [2:0] $end +$var wire 1 %/ carryin $end +$var wire 1 &/ carryout $end +$var wire 1 '/ nB $end +$var wire 1 (/ nCmd2 $end +$var wire 1 )/ subtract $end +$scope module mux0 $end +$var wire 1 */ S $end +$var wire 1 !/ in0 $end +$var wire 1 '/ in1 $end +$var wire 1 +/ nS $end +$var wire 1 ,/ out0 $end +$var wire 1 -/ out1 $end +$var wire 1 "/ outfinal $end +$upscope $end +$upscope $end +$scope module setSLTres2 $end +$var wire 1 3' S $end +$var wire 1 ./ in0 $end +$var wire 1 // in1 $end +$var wire 1 0/ nS $end +$var wire 1 1/ out0 $end +$var wire 1 2/ out1 $end +$var wire 1 3/ outfinal $end +$upscope $end +$scope module setSLTres3 $end +$var wire 1 3' S $end +$var wire 1 4/ in0 $end +$var wire 1 5/ in1 $end +$var wire 1 6/ nS $end +$var wire 1 7/ out0 $end +$var wire 1 8/ out1 $end +$var wire 1 9/ outfinal $end +$upscope $end +$upscope $end +$scope begin sltbits[26] $end +$scope module attempt $end +$var wire 1 :/ A $end +$var wire 1 ;/ AandB $end +$var wire 1 / B $end +$var wire 1 ?/ BornB $end +$var wire 1 @/ CINandAxorB $end +$var wire 3 A/ Command [2:0] $end +$var wire 1 B/ carryin $end +$var wire 1 C/ carryout $end +$var wire 1 D/ nB $end +$var wire 1 E/ nCmd2 $end +$var wire 1 F/ subtract $end +$scope module mux0 $end +$var wire 1 G/ S $end +$var wire 1 >/ in0 $end +$var wire 1 D/ in1 $end +$var wire 1 H/ nS $end +$var wire 1 I/ out0 $end +$var wire 1 J/ out1 $end +$var wire 1 ?/ outfinal $end +$upscope $end +$upscope $end +$scope module setSLTres2 $end +$var wire 1 3' S $end +$var wire 1 K/ in0 $end +$var wire 1 L/ in1 $end +$var wire 1 M/ nS $end +$var wire 1 N/ out0 $end +$var wire 1 O/ out1 $end +$var wire 1 P/ outfinal $end +$upscope $end +$scope module setSLTres3 $end +$var wire 1 3' S $end +$var wire 1 Q/ in0 $end +$var wire 1 R/ in1 $end +$var wire 1 S/ nS $end +$var wire 1 T/ out0 $end +$var wire 1 U/ out1 $end +$var wire 1 V/ outfinal $end +$upscope $end +$upscope $end +$scope begin sltbits[27] $end +$scope module attempt $end +$var wire 1 W/ A $end +$var wire 1 X/ AandB $end +$var wire 1 Y/ AddSubSLTSum $end +$var wire 1 Z/ AxorB $end +$var wire 1 [/ B $end +$var wire 1 \/ BornB $end +$var wire 1 ]/ CINandAxorB $end +$var wire 3 ^/ Command [2:0] $end +$var wire 1 _/ carryin $end +$var wire 1 `/ carryout $end +$var wire 1 a/ nB $end +$var wire 1 b/ nCmd2 $end +$var wire 1 c/ subtract $end +$scope module mux0 $end +$var wire 1 d/ S $end +$var wire 1 [/ in0 $end +$var wire 1 a/ in1 $end +$var wire 1 e/ nS $end +$var wire 1 f/ out0 $end +$var wire 1 g/ out1 $end +$var wire 1 \/ outfinal $end +$upscope $end +$upscope $end +$scope module setSLTres2 $end +$var wire 1 3' S $end +$var wire 1 h/ in0 $end +$var wire 1 i/ in1 $end +$var wire 1 j/ nS $end +$var wire 1 k/ out0 $end +$var wire 1 l/ out1 $end +$var wire 1 m/ outfinal $end +$upscope $end +$scope module setSLTres3 $end +$var wire 1 3' S $end +$var wire 1 n/ in0 $end +$var wire 1 o/ in1 $end +$var wire 1 p/ nS $end +$var wire 1 q/ out0 $end +$var wire 1 r/ out1 $end +$var wire 1 s/ outfinal $end +$upscope $end +$upscope $end +$scope begin sltbits[28] $end +$scope module attempt $end +$var wire 1 t/ A $end +$var wire 1 u/ AandB $end +$var wire 1 v/ AddSubSLTSum $end +$var wire 1 w/ AxorB $end +$var wire 1 x/ B $end +$var wire 1 y/ BornB $end +$var wire 1 z/ CINandAxorB $end +$var wire 3 {/ Command [2:0] $end +$var wire 1 |/ carryin $end +$var wire 1 }/ carryout $end +$var wire 1 ~/ nB $end +$var wire 1 !0 nCmd2 $end +$var wire 1 "0 subtract $end +$scope module mux0 $end +$var wire 1 #0 S $end +$var wire 1 x/ in0 $end +$var wire 1 ~/ in1 $end +$var wire 1 $0 nS $end +$var wire 1 %0 out0 $end +$var wire 1 &0 out1 $end +$var wire 1 y/ outfinal $end +$upscope $end +$upscope $end +$scope module setSLTres2 $end +$var wire 1 3' S $end +$var wire 1 '0 in0 $end +$var wire 1 (0 in1 $end +$var wire 1 )0 nS $end +$var wire 1 *0 out0 $end +$var wire 1 +0 out1 $end +$var wire 1 ,0 outfinal $end +$upscope $end +$scope module setSLTres3 $end +$var wire 1 3' S $end +$var wire 1 -0 in0 $end +$var wire 1 .0 in1 $end +$var wire 1 /0 nS $end +$var wire 1 00 out0 $end +$var wire 1 10 out1 $end +$var wire 1 20 outfinal $end +$upscope $end +$upscope $end +$scope begin sltbits[29] $end +$scope module attempt $end +$var wire 1 30 A $end +$var wire 1 40 AandB $end +$var wire 1 50 AddSubSLTSum $end +$var wire 1 60 AxorB $end +$var wire 1 70 B $end +$var wire 1 80 BornB $end +$var wire 1 90 CINandAxorB $end +$var wire 3 :0 Command [2:0] $end +$var wire 1 ;0 carryin $end +$var wire 1 <0 carryout $end +$var wire 1 =0 nB $end +$var wire 1 >0 nCmd2 $end +$var wire 1 ?0 subtract $end +$scope module mux0 $end +$var wire 1 @0 S $end +$var wire 1 70 in0 $end +$var wire 1 =0 in1 $end +$var wire 1 A0 nS $end +$var wire 1 B0 out0 $end +$var wire 1 C0 out1 $end +$var wire 1 80 outfinal $end +$upscope $end +$upscope $end +$scope module setSLTres2 $end +$var wire 1 3' S $end +$var wire 1 D0 in0 $end +$var wire 1 E0 in1 $end +$var wire 1 F0 nS $end +$var wire 1 G0 out0 $end +$var wire 1 H0 out1 $end +$var wire 1 I0 outfinal $end +$upscope $end +$scope module setSLTres3 $end +$var wire 1 3' S $end +$var wire 1 J0 in0 $end +$var wire 1 K0 in1 $end +$var wire 1 L0 nS $end +$var wire 1 M0 out0 $end +$var wire 1 N0 out1 $end +$var wire 1 O0 outfinal $end +$upscope $end +$upscope $end +$scope begin sltbits[30] $end +$scope module attempt $end +$var wire 1 P0 A $end +$var wire 1 Q0 AandB $end +$var wire 1 R0 AddSubSLTSum $end +$var wire 1 S0 AxorB $end +$var wire 1 T0 B $end +$var wire 1 U0 BornB $end +$var wire 1 V0 CINandAxorB $end +$var wire 3 W0 Command [2:0] $end +$var wire 1 X0 carryin $end +$var wire 1 Y0 carryout $end +$var wire 1 Z0 nB $end +$var wire 1 [0 nCmd2 $end +$var wire 1 \0 subtract $end +$scope module mux0 $end +$var wire 1 ]0 S $end +$var wire 1 T0 in0 $end +$var wire 1 Z0 in1 $end +$var wire 1 ^0 nS $end +$var wire 1 _0 out0 $end +$var wire 1 `0 out1 $end +$var wire 1 U0 outfinal $end +$upscope $end +$upscope $end +$scope module setSLTres2 $end +$var wire 1 3' S $end +$var wire 1 a0 in0 $end +$var wire 1 b0 in1 $end +$var wire 1 c0 nS $end +$var wire 1 d0 out0 $end +$var wire 1 e0 out1 $end +$var wire 1 f0 outfinal $end +$upscope $end +$scope module setSLTres3 $end +$var wire 1 3' S $end +$var wire 1 g0 in0 $end +$var wire 1 h0 in1 $end +$var wire 1 i0 nS $end +$var wire 1 j0 out0 $end +$var wire 1 k0 out1 $end +$var wire 1 l0 outfinal $end +$upscope $end +$upscope $end +$scope begin sltbits[31] $end +$scope module attempt $end +$var wire 1 m0 A $end +$var wire 1 n0 AandB $end +$var wire 1 o0 AddSubSLTSum $end +$var wire 1 p0 AxorB $end +$var wire 1 q0 B $end +$var wire 1 r0 BornB $end +$var wire 1 s0 CINandAxorB $end +$var wire 3 t0 Command [2:0] $end +$var wire 1 u0 carryin $end +$var wire 1 v0 carryout $end +$var wire 1 w0 nB $end +$var wire 1 x0 nCmd2 $end +$var wire 1 y0 subtract $end +$scope module mux0 $end +$var wire 1 z0 S $end +$var wire 1 q0 in0 $end +$var wire 1 w0 in1 $end +$var wire 1 {0 nS $end +$var wire 1 |0 out0 $end +$var wire 1 }0 out1 $end +$var wire 1 r0 outfinal $end +$upscope $end +$upscope $end +$scope module setSLTres2 $end +$var wire 1 3' S $end +$var wire 1 ~0 in0 $end +$var wire 1 !1 in1 $end +$var wire 1 "1 nS $end +$var wire 1 #1 out0 $end +$var wire 1 $1 out1 $end +$var wire 1 %1 outfinal $end +$upscope $end +$scope module setSLTres3 $end +$var wire 1 3' S $end +$var wire 1 &1 in0 $end +$var wire 1 '1 in1 $end +$var wire 1 (1 nS $end +$var wire 1 )1 out0 $end +$var wire 1 *1 out1 $end +$var wire 1 +1 outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope module trial1 $end +$var wire 32 ,1 A [31:0] $end +$var wire 32 -1 AndNandOut [31:0] $end +$var wire 32 .1 B [31:0] $end +$var wire 3 /1 Command [2:0] $end +$scope module attempt2 $end +$var wire 1 01 A $end +$var wire 1 11 AandB $end +$var wire 1 21 AnandB $end +$var wire 1 31 AndNandOut $end +$var wire 1 41 B $end +$var wire 3 51 Command [2:0] $end +$scope module potato $end +$var wire 1 61 S $end +$var wire 1 11 in0 $end +$var wire 1 21 in1 $end +$var wire 1 71 nS $end +$var wire 1 81 out0 $end +$var wire 1 91 out1 $end +$var wire 1 31 outfinal $end +$upscope $end +$upscope $end +$scope begin andbits[1] $end +$scope module attempt $end +$var wire 1 :1 A $end +$var wire 1 ;1 AandB $end +$var wire 1 <1 AnandB $end +$var wire 1 =1 AndNandOut $end +$var wire 1 >1 B $end +$var wire 3 ?1 Command [2:0] $end +$scope module potato $end +$var wire 1 @1 S $end +$var wire 1 ;1 in0 $end +$var wire 1 <1 in1 $end +$var wire 1 A1 nS $end +$var wire 1 B1 out0 $end +$var wire 1 C1 out1 $end +$var wire 1 =1 outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin andbits[2] $end +$scope module attempt $end +$var wire 1 D1 A $end +$var wire 1 E1 AandB $end +$var wire 1 F1 AnandB $end +$var wire 1 G1 AndNandOut $end +$var wire 1 H1 B $end +$var wire 3 I1 Command [2:0] $end +$scope module potato $end +$var wire 1 J1 S $end +$var wire 1 E1 in0 $end +$var wire 1 F1 in1 $end +$var wire 1 K1 nS $end +$var wire 1 L1 out0 $end +$var wire 1 M1 out1 $end +$var wire 1 G1 outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin andbits[3] $end +$scope module attempt $end +$var wire 1 N1 A $end +$var wire 1 O1 AandB $end +$var wire 1 P1 AnandB $end +$var wire 1 Q1 AndNandOut $end +$var wire 1 R1 B $end +$var wire 3 S1 Command [2:0] $end +$scope module potato $end +$var wire 1 T1 S $end +$var wire 1 O1 in0 $end +$var wire 1 P1 in1 $end +$var wire 1 U1 nS $end +$var wire 1 V1 out0 $end +$var wire 1 W1 out1 $end +$var wire 1 Q1 outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin andbits[4] $end +$scope module attempt $end +$var wire 1 X1 A $end +$var wire 1 Y1 AandB $end +$var wire 1 Z1 AnandB $end +$var wire 1 [1 AndNandOut $end +$var wire 1 \1 B $end +$var wire 3 ]1 Command [2:0] $end +$scope module potato $end +$var wire 1 ^1 S $end +$var wire 1 Y1 in0 $end +$var wire 1 Z1 in1 $end +$var wire 1 _1 nS $end +$var wire 1 `1 out0 $end +$var wire 1 a1 out1 $end +$var wire 1 [1 outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin andbits[5] $end +$scope module attempt $end +$var wire 1 b1 A $end +$var wire 1 c1 AandB $end +$var wire 1 d1 AnandB $end +$var wire 1 e1 AndNandOut $end +$var wire 1 f1 B $end +$var wire 3 g1 Command [2:0] $end +$scope module potato $end +$var wire 1 h1 S $end +$var wire 1 c1 in0 $end +$var wire 1 d1 in1 $end +$var wire 1 i1 nS $end +$var wire 1 j1 out0 $end +$var wire 1 k1 out1 $end +$var wire 1 e1 outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin andbits[6] $end +$scope module attempt $end +$var wire 1 l1 A $end +$var wire 1 m1 AandB $end +$var wire 1 n1 AnandB $end +$var wire 1 o1 AndNandOut $end +$var wire 1 p1 B $end +$var wire 3 q1 Command [2:0] $end +$scope module potato $end +$var wire 1 r1 S $end +$var wire 1 m1 in0 $end +$var wire 1 n1 in1 $end +$var wire 1 s1 nS $end +$var wire 1 t1 out0 $end +$var wire 1 u1 out1 $end +$var wire 1 o1 outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin andbits[7] $end +$scope module attempt $end +$var wire 1 v1 A $end +$var wire 1 w1 AandB $end +$var wire 1 x1 AnandB $end +$var wire 1 y1 AndNandOut $end +$var wire 1 z1 B $end +$var wire 3 {1 Command [2:0] $end +$scope module potato $end +$var wire 1 |1 S $end +$var wire 1 w1 in0 $end +$var wire 1 x1 in1 $end +$var wire 1 }1 nS $end +$var wire 1 ~1 out0 $end +$var wire 1 !2 out1 $end +$var wire 1 y1 outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin andbits[8] $end +$scope module attempt $end +$var wire 1 "2 A $end +$var wire 1 #2 AandB $end +$var wire 1 $2 AnandB $end +$var wire 1 %2 AndNandOut $end +$var wire 1 &2 B $end +$var wire 3 '2 Command [2:0] $end +$scope module potato $end +$var wire 1 (2 S $end +$var wire 1 #2 in0 $end +$var wire 1 $2 in1 $end +$var wire 1 )2 nS $end +$var wire 1 *2 out0 $end +$var wire 1 +2 out1 $end +$var wire 1 %2 outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin andbits[9] $end +$scope module attempt $end +$var wire 1 ,2 A $end +$var wire 1 -2 AandB $end +$var wire 1 .2 AnandB $end +$var wire 1 /2 AndNandOut $end +$var wire 1 02 B $end +$var wire 3 12 Command [2:0] $end +$scope module potato $end +$var wire 1 22 S $end +$var wire 1 -2 in0 $end +$var wire 1 .2 in1 $end +$var wire 1 32 nS $end +$var wire 1 42 out0 $end +$var wire 1 52 out1 $end +$var wire 1 /2 outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin andbits[10] $end +$scope module attempt $end +$var wire 1 62 A $end +$var wire 1 72 AandB $end +$var wire 1 82 AnandB $end +$var wire 1 92 AndNandOut $end +$var wire 1 :2 B $end +$var wire 3 ;2 Command [2:0] $end +$scope module potato $end +$var wire 1 <2 S $end +$var wire 1 72 in0 $end +$var wire 1 82 in1 $end +$var wire 1 =2 nS $end +$var wire 1 >2 out0 $end +$var wire 1 ?2 out1 $end +$var wire 1 92 outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin andbits[11] $end +$scope module attempt $end +$var wire 1 @2 A $end +$var wire 1 A2 AandB $end +$var wire 1 B2 AnandB $end +$var wire 1 C2 AndNandOut $end +$var wire 1 D2 B $end +$var wire 3 E2 Command [2:0] $end +$scope module potato $end +$var wire 1 F2 S $end +$var wire 1 A2 in0 $end +$var wire 1 B2 in1 $end +$var wire 1 G2 nS $end +$var wire 1 H2 out0 $end +$var wire 1 I2 out1 $end +$var wire 1 C2 outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin andbits[12] $end +$scope module attempt $end +$var wire 1 J2 A $end +$var wire 1 K2 AandB $end +$var wire 1 L2 AnandB $end +$var wire 1 M2 AndNandOut $end +$var wire 1 N2 B $end +$var wire 3 O2 Command [2:0] $end +$scope module potato $end +$var wire 1 P2 S $end +$var wire 1 K2 in0 $end +$var wire 1 L2 in1 $end +$var wire 1 Q2 nS $end +$var wire 1 R2 out0 $end +$var wire 1 S2 out1 $end +$var wire 1 M2 outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin andbits[13] $end +$scope module attempt $end +$var wire 1 T2 A $end +$var wire 1 U2 AandB $end +$var wire 1 V2 AnandB $end +$var wire 1 W2 AndNandOut $end +$var wire 1 X2 B $end +$var wire 3 Y2 Command [2:0] $end +$scope module potato $end +$var wire 1 Z2 S $end +$var wire 1 U2 in0 $end +$var wire 1 V2 in1 $end +$var wire 1 [2 nS $end +$var wire 1 \2 out0 $end +$var wire 1 ]2 out1 $end +$var wire 1 W2 outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin andbits[14] $end +$scope module attempt $end +$var wire 1 ^2 A $end +$var wire 1 _2 AandB $end +$var wire 1 `2 AnandB $end +$var wire 1 a2 AndNandOut $end +$var wire 1 b2 B $end +$var wire 3 c2 Command [2:0] $end +$scope module potato $end +$var wire 1 d2 S $end +$var wire 1 _2 in0 $end +$var wire 1 `2 in1 $end +$var wire 1 e2 nS $end +$var wire 1 f2 out0 $end +$var wire 1 g2 out1 $end +$var wire 1 a2 outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin andbits[15] $end +$scope module attempt $end +$var wire 1 h2 A $end +$var wire 1 i2 AandB $end +$var wire 1 j2 AnandB $end +$var wire 1 k2 AndNandOut $end +$var wire 1 l2 B $end +$var wire 3 m2 Command [2:0] $end +$scope module potato $end +$var wire 1 n2 S $end +$var wire 1 i2 in0 $end +$var wire 1 j2 in1 $end +$var wire 1 o2 nS $end +$var wire 1 p2 out0 $end +$var wire 1 q2 out1 $end +$var wire 1 k2 outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin andbits[16] $end +$scope module attempt $end +$var wire 1 r2 A $end +$var wire 1 s2 AandB $end +$var wire 1 t2 AnandB $end +$var wire 1 u2 AndNandOut $end +$var wire 1 v2 B $end +$var wire 3 w2 Command [2:0] $end +$scope module potato $end +$var wire 1 x2 S $end +$var wire 1 s2 in0 $end +$var wire 1 t2 in1 $end +$var wire 1 y2 nS $end +$var wire 1 z2 out0 $end +$var wire 1 {2 out1 $end +$var wire 1 u2 outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin andbits[17] $end +$scope module attempt $end +$var wire 1 |2 A $end +$var wire 1 }2 AandB $end +$var wire 1 ~2 AnandB $end +$var wire 1 !3 AndNandOut $end +$var wire 1 "3 B $end +$var wire 3 #3 Command [2:0] $end +$scope module potato $end +$var wire 1 $3 S $end +$var wire 1 }2 in0 $end +$var wire 1 ~2 in1 $end +$var wire 1 %3 nS $end +$var wire 1 &3 out0 $end +$var wire 1 '3 out1 $end +$var wire 1 !3 outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin andbits[18] $end +$scope module attempt $end +$var wire 1 (3 A $end +$var wire 1 )3 AandB $end +$var wire 1 *3 AnandB $end +$var wire 1 +3 AndNandOut $end +$var wire 1 ,3 B $end +$var wire 3 -3 Command [2:0] $end +$scope module potato $end +$var wire 1 .3 S $end +$var wire 1 )3 in0 $end +$var wire 1 *3 in1 $end +$var wire 1 /3 nS $end +$var wire 1 03 out0 $end +$var wire 1 13 out1 $end +$var wire 1 +3 outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin andbits[19] $end +$scope module attempt $end +$var wire 1 23 A $end +$var wire 1 33 AandB $end +$var wire 1 43 AnandB $end +$var wire 1 53 AndNandOut $end +$var wire 1 63 B $end +$var wire 3 73 Command [2:0] $end +$scope module potato $end +$var wire 1 83 S $end +$var wire 1 33 in0 $end +$var wire 1 43 in1 $end +$var wire 1 93 nS $end +$var wire 1 :3 out0 $end +$var wire 1 ;3 out1 $end +$var wire 1 53 outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin andbits[20] $end +$scope module attempt $end +$var wire 1 <3 A $end +$var wire 1 =3 AandB $end +$var wire 1 >3 AnandB $end +$var wire 1 ?3 AndNandOut $end +$var wire 1 @3 B $end +$var wire 3 A3 Command [2:0] $end +$scope module potato $end +$var wire 1 B3 S $end +$var wire 1 =3 in0 $end +$var wire 1 >3 in1 $end +$var wire 1 C3 nS $end +$var wire 1 D3 out0 $end +$var wire 1 E3 out1 $end +$var wire 1 ?3 outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin andbits[21] $end +$scope module attempt $end +$var wire 1 F3 A $end +$var wire 1 G3 AandB $end +$var wire 1 H3 AnandB $end +$var wire 1 I3 AndNandOut $end +$var wire 1 J3 B $end +$var wire 3 K3 Command [2:0] $end +$scope module potato $end +$var wire 1 L3 S $end +$var wire 1 G3 in0 $end +$var wire 1 H3 in1 $end +$var wire 1 M3 nS $end +$var wire 1 N3 out0 $end +$var wire 1 O3 out1 $end +$var wire 1 I3 outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin andbits[22] $end +$scope module attempt $end +$var wire 1 P3 A $end +$var wire 1 Q3 AandB $end +$var wire 1 R3 AnandB $end +$var wire 1 S3 AndNandOut $end +$var wire 1 T3 B $end +$var wire 3 U3 Command [2:0] $end +$scope module potato $end +$var wire 1 V3 S $end +$var wire 1 Q3 in0 $end +$var wire 1 R3 in1 $end +$var wire 1 W3 nS $end +$var wire 1 X3 out0 $end +$var wire 1 Y3 out1 $end +$var wire 1 S3 outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin andbits[23] $end +$scope module attempt $end +$var wire 1 Z3 A $end +$var wire 1 [3 AandB $end +$var wire 1 \3 AnandB $end +$var wire 1 ]3 AndNandOut $end +$var wire 1 ^3 B $end +$var wire 3 _3 Command [2:0] $end +$scope module potato $end +$var wire 1 `3 S $end +$var wire 1 [3 in0 $end +$var wire 1 \3 in1 $end +$var wire 1 a3 nS $end +$var wire 1 b3 out0 $end +$var wire 1 c3 out1 $end +$var wire 1 ]3 outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin andbits[24] $end +$scope module attempt $end +$var wire 1 d3 A $end +$var wire 1 e3 AandB $end +$var wire 1 f3 AnandB $end +$var wire 1 g3 AndNandOut $end +$var wire 1 h3 B $end +$var wire 3 i3 Command [2:0] $end +$scope module potato $end +$var wire 1 j3 S $end +$var wire 1 e3 in0 $end +$var wire 1 f3 in1 $end +$var wire 1 k3 nS $end +$var wire 1 l3 out0 $end +$var wire 1 m3 out1 $end +$var wire 1 g3 outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin andbits[25] $end +$scope module attempt $end +$var wire 1 n3 A $end +$var wire 1 o3 AandB $end +$var wire 1 p3 AnandB $end +$var wire 1 q3 AndNandOut $end +$var wire 1 r3 B $end +$var wire 3 s3 Command [2:0] $end +$scope module potato $end +$var wire 1 t3 S $end +$var wire 1 o3 in0 $end +$var wire 1 p3 in1 $end +$var wire 1 u3 nS $end +$var wire 1 v3 out0 $end +$var wire 1 w3 out1 $end +$var wire 1 q3 outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin andbits[26] $end +$scope module attempt $end +$var wire 1 x3 A $end +$var wire 1 y3 AandB $end +$var wire 1 z3 AnandB $end +$var wire 1 {3 AndNandOut $end +$var wire 1 |3 B $end +$var wire 3 }3 Command [2:0] $end +$scope module potato $end +$var wire 1 ~3 S $end +$var wire 1 y3 in0 $end +$var wire 1 z3 in1 $end +$var wire 1 !4 nS $end +$var wire 1 "4 out0 $end +$var wire 1 #4 out1 $end +$var wire 1 {3 outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin andbits[27] $end +$scope module attempt $end +$var wire 1 $4 A $end +$var wire 1 %4 AandB $end +$var wire 1 &4 AnandB $end +$var wire 1 '4 AndNandOut $end +$var wire 1 (4 B $end +$var wire 3 )4 Command [2:0] $end +$scope module potato $end +$var wire 1 *4 S $end +$var wire 1 %4 in0 $end +$var wire 1 &4 in1 $end +$var wire 1 +4 nS $end +$var wire 1 ,4 out0 $end +$var wire 1 -4 out1 $end +$var wire 1 '4 outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin andbits[28] $end +$scope module attempt $end +$var wire 1 .4 A $end +$var wire 1 /4 AandB $end +$var wire 1 04 AnandB $end +$var wire 1 14 AndNandOut $end +$var wire 1 24 B $end +$var wire 3 34 Command [2:0] $end +$scope module potato $end +$var wire 1 44 S $end +$var wire 1 /4 in0 $end +$var wire 1 04 in1 $end +$var wire 1 54 nS $end +$var wire 1 64 out0 $end +$var wire 1 74 out1 $end +$var wire 1 14 outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin andbits[29] $end +$scope module attempt $end +$var wire 1 84 A $end +$var wire 1 94 AandB $end +$var wire 1 :4 AnandB $end +$var wire 1 ;4 AndNandOut $end +$var wire 1 <4 B $end +$var wire 3 =4 Command [2:0] $end +$scope module potato $end +$var wire 1 >4 S $end +$var wire 1 94 in0 $end +$var wire 1 :4 in1 $end +$var wire 1 ?4 nS $end +$var wire 1 @4 out0 $end +$var wire 1 A4 out1 $end +$var wire 1 ;4 outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin andbits[30] $end +$scope module attempt $end +$var wire 1 B4 A $end +$var wire 1 C4 AandB $end +$var wire 1 D4 AnandB $end +$var wire 1 E4 AndNandOut $end +$var wire 1 F4 B $end +$var wire 3 G4 Command [2:0] $end +$scope module potato $end +$var wire 1 H4 S $end +$var wire 1 C4 in0 $end +$var wire 1 D4 in1 $end +$var wire 1 I4 nS $end +$var wire 1 J4 out0 $end +$var wire 1 K4 out1 $end +$var wire 1 E4 outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin andbits[31] $end +$scope module attempt $end +$var wire 1 L4 A $end +$var wire 1 M4 AandB $end +$var wire 1 N4 AnandB $end +$var wire 1 O4 AndNandOut $end +$var wire 1 P4 B $end +$var wire 3 Q4 Command [2:0] $end +$scope module potato $end +$var wire 1 R4 S $end +$var wire 1 M4 in0 $end +$var wire 1 N4 in1 $end +$var wire 1 S4 nS $end +$var wire 1 T4 out0 $end +$var wire 1 U4 out1 $end +$var wire 1 O4 outfinal $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope module trial2 $end +$var wire 32 V4 A [31:0] $end +$var wire 32 W4 B [31:0] $end +$var wire 3 X4 Command [2:0] $end +$var wire 32 Y4 OrNorXorOut [31:0] $end +$scope module attempt2 $end +$var wire 1 Z4 A $end +$var wire 1 [4 AnandB $end +$var wire 1 \4 AnorB $end +$var wire 1 ]4 AorB $end +$var wire 1 ^4 AxorB $end +$var wire 1 _4 B $end +$var wire 3 `4 Command [2:0] $end +$var wire 1 a4 OrNorXorOut $end +$var wire 1 b4 XorNor $end +$var wire 1 c4 nXor $end +$scope module mux0 $end +$var wire 1 d4 S $end +$var wire 1 ^4 in0 $end +$var wire 1 \4 in1 $end +$var wire 1 e4 nS $end +$var wire 1 f4 out0 $end +$var wire 1 g4 out1 $end +$var wire 1 b4 outfinal $end +$upscope $end +$scope module mux1 $end +$var wire 1 h4 S $end +$var wire 1 b4 in0 $end +$var wire 1 ]4 in1 $end +$var wire 1 i4 nS $end +$var wire 1 j4 out0 $end +$var wire 1 k4 out1 $end +$var wire 1 a4 outfinal $end +$upscope $end +$upscope $end +$scope begin orbits[1] $end +$scope module attempt $end +$var wire 1 l4 A $end +$var wire 1 m4 AnandB $end +$var wire 1 n4 AnorB $end +$var wire 1 o4 AorB $end +$var wire 1 p4 AxorB $end +$var wire 1 q4 B $end +$var wire 3 r4 Command [2:0] $end +$var wire 1 s4 OrNorXorOut $end +$var wire 1 t4 XorNor $end +$var wire 1 u4 nXor $end +$scope module mux0 $end +$var wire 1 v4 S $end +$var wire 1 p4 in0 $end +$var wire 1 n4 in1 $end +$var wire 1 w4 nS $end +$var wire 1 x4 out0 $end +$var wire 1 y4 out1 $end +$var wire 1 t4 outfinal $end +$upscope $end +$scope module mux1 $end +$var wire 1 z4 S $end +$var wire 1 t4 in0 $end +$var wire 1 o4 in1 $end +$var wire 1 {4 nS $end +$var wire 1 |4 out0 $end +$var wire 1 }4 out1 $end +$var wire 1 s4 outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin orbits[2] $end +$scope module attempt $end +$var wire 1 ~4 A $end +$var wire 1 !5 AnandB $end +$var wire 1 "5 AnorB $end +$var wire 1 #5 AorB $end +$var wire 1 $5 AxorB $end +$var wire 1 %5 B $end +$var wire 3 &5 Command [2:0] $end +$var wire 1 '5 OrNorXorOut $end +$var wire 1 (5 XorNor $end +$var wire 1 )5 nXor $end +$scope module mux0 $end +$var wire 1 *5 S $end +$var wire 1 $5 in0 $end +$var wire 1 "5 in1 $end +$var wire 1 +5 nS $end +$var wire 1 ,5 out0 $end +$var wire 1 -5 out1 $end +$var wire 1 (5 outfinal $end +$upscope $end +$scope module mux1 $end +$var wire 1 .5 S $end +$var wire 1 (5 in0 $end +$var wire 1 #5 in1 $end +$var wire 1 /5 nS $end +$var wire 1 05 out0 $end +$var wire 1 15 out1 $end +$var wire 1 '5 outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin orbits[3] $end +$scope module attempt $end +$var wire 1 25 A $end +$var wire 1 35 AnandB $end +$var wire 1 45 AnorB $end +$var wire 1 55 AorB $end +$var wire 1 65 AxorB $end +$var wire 1 75 B $end +$var wire 3 85 Command [2:0] $end +$var wire 1 95 OrNorXorOut $end +$var wire 1 :5 XorNor $end +$var wire 1 ;5 nXor $end +$scope module mux0 $end +$var wire 1 <5 S $end +$var wire 1 65 in0 $end +$var wire 1 45 in1 $end +$var wire 1 =5 nS $end +$var wire 1 >5 out0 $end +$var wire 1 ?5 out1 $end +$var wire 1 :5 outfinal $end +$upscope $end +$scope module mux1 $end +$var wire 1 @5 S $end +$var wire 1 :5 in0 $end +$var wire 1 55 in1 $end +$var wire 1 A5 nS $end +$var wire 1 B5 out0 $end +$var wire 1 C5 out1 $end +$var wire 1 95 outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin orbits[4] $end +$scope module attempt $end +$var wire 1 D5 A $end +$var wire 1 E5 AnandB $end +$var wire 1 F5 AnorB $end +$var wire 1 G5 AorB $end +$var wire 1 H5 AxorB $end +$var wire 1 I5 B $end +$var wire 3 J5 Command [2:0] $end +$var wire 1 K5 OrNorXorOut $end +$var wire 1 L5 XorNor $end +$var wire 1 M5 nXor $end +$scope module mux0 $end +$var wire 1 N5 S $end +$var wire 1 H5 in0 $end +$var wire 1 F5 in1 $end +$var wire 1 O5 nS $end +$var wire 1 P5 out0 $end +$var wire 1 Q5 out1 $end +$var wire 1 L5 outfinal $end +$upscope $end +$scope module mux1 $end +$var wire 1 R5 S $end +$var wire 1 L5 in0 $end +$var wire 1 G5 in1 $end +$var wire 1 S5 nS $end +$var wire 1 T5 out0 $end +$var wire 1 U5 out1 $end +$var wire 1 K5 outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin orbits[5] $end +$scope module attempt $end +$var wire 1 V5 A $end +$var wire 1 W5 AnandB $end +$var wire 1 X5 AnorB $end +$var wire 1 Y5 AorB $end +$var wire 1 Z5 AxorB $end +$var wire 1 [5 B $end +$var wire 3 \5 Command [2:0] $end +$var wire 1 ]5 OrNorXorOut $end +$var wire 1 ^5 XorNor $end +$var wire 1 _5 nXor $end +$scope module mux0 $end +$var wire 1 `5 S $end +$var wire 1 Z5 in0 $end +$var wire 1 X5 in1 $end +$var wire 1 a5 nS $end +$var wire 1 b5 out0 $end +$var wire 1 c5 out1 $end +$var wire 1 ^5 outfinal $end +$upscope $end +$scope module mux1 $end +$var wire 1 d5 S $end +$var wire 1 ^5 in0 $end +$var wire 1 Y5 in1 $end +$var wire 1 e5 nS $end +$var wire 1 f5 out0 $end +$var wire 1 g5 out1 $end +$var wire 1 ]5 outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin orbits[6] $end +$scope module attempt $end +$var wire 1 h5 A $end +$var wire 1 i5 AnandB $end +$var wire 1 j5 AnorB $end +$var wire 1 k5 AorB $end +$var wire 1 l5 AxorB $end +$var wire 1 m5 B $end +$var wire 3 n5 Command [2:0] $end +$var wire 1 o5 OrNorXorOut $end +$var wire 1 p5 XorNor $end +$var wire 1 q5 nXor $end +$scope module mux0 $end +$var wire 1 r5 S $end +$var wire 1 l5 in0 $end +$var wire 1 j5 in1 $end +$var wire 1 s5 nS $end +$var wire 1 t5 out0 $end +$var wire 1 u5 out1 $end +$var wire 1 p5 outfinal $end +$upscope $end +$scope module mux1 $end +$var wire 1 v5 S $end +$var wire 1 p5 in0 $end +$var wire 1 k5 in1 $end +$var wire 1 w5 nS $end +$var wire 1 x5 out0 $end +$var wire 1 y5 out1 $end +$var wire 1 o5 outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin orbits[7] $end +$scope module attempt $end +$var wire 1 z5 A $end +$var wire 1 {5 AnandB $end +$var wire 1 |5 AnorB $end +$var wire 1 }5 AorB $end +$var wire 1 ~5 AxorB $end +$var wire 1 !6 B $end +$var wire 3 "6 Command [2:0] $end +$var wire 1 #6 OrNorXorOut $end +$var wire 1 $6 XorNor $end +$var wire 1 %6 nXor $end +$scope module mux0 $end +$var wire 1 &6 S $end +$var wire 1 ~5 in0 $end +$var wire 1 |5 in1 $end +$var wire 1 '6 nS $end +$var wire 1 (6 out0 $end +$var wire 1 )6 out1 $end +$var wire 1 $6 outfinal $end +$upscope $end +$scope module mux1 $end +$var wire 1 *6 S $end +$var wire 1 $6 in0 $end +$var wire 1 }5 in1 $end +$var wire 1 +6 nS $end +$var wire 1 ,6 out0 $end +$var wire 1 -6 out1 $end +$var wire 1 #6 outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin orbits[8] $end +$scope module attempt $end +$var wire 1 .6 A $end +$var wire 1 /6 AnandB $end +$var wire 1 06 AnorB $end +$var wire 1 16 AorB $end +$var wire 1 26 AxorB $end +$var wire 1 36 B $end +$var wire 3 46 Command [2:0] $end +$var wire 1 56 OrNorXorOut $end +$var wire 1 66 XorNor $end +$var wire 1 76 nXor $end +$scope module mux0 $end +$var wire 1 86 S $end +$var wire 1 26 in0 $end +$var wire 1 06 in1 $end +$var wire 1 96 nS $end +$var wire 1 :6 out0 $end +$var wire 1 ;6 out1 $end +$var wire 1 66 outfinal $end +$upscope $end +$scope module mux1 $end +$var wire 1 <6 S $end +$var wire 1 66 in0 $end +$var wire 1 16 in1 $end +$var wire 1 =6 nS $end +$var wire 1 >6 out0 $end +$var wire 1 ?6 out1 $end +$var wire 1 56 outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin orbits[9] $end +$scope module attempt $end +$var wire 1 @6 A $end +$var wire 1 A6 AnandB $end +$var wire 1 B6 AnorB $end +$var wire 1 C6 AorB $end +$var wire 1 D6 AxorB $end +$var wire 1 E6 B $end +$var wire 3 F6 Command [2:0] $end +$var wire 1 G6 OrNorXorOut $end +$var wire 1 H6 XorNor $end +$var wire 1 I6 nXor $end +$scope module mux0 $end +$var wire 1 J6 S $end +$var wire 1 D6 in0 $end +$var wire 1 B6 in1 $end +$var wire 1 K6 nS $end +$var wire 1 L6 out0 $end +$var wire 1 M6 out1 $end +$var wire 1 H6 outfinal $end +$upscope $end +$scope module mux1 $end +$var wire 1 N6 S $end +$var wire 1 H6 in0 $end +$var wire 1 C6 in1 $end +$var wire 1 O6 nS $end +$var wire 1 P6 out0 $end +$var wire 1 Q6 out1 $end +$var wire 1 G6 outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin orbits[10] $end +$scope module attempt $end +$var wire 1 R6 A $end +$var wire 1 S6 AnandB $end +$var wire 1 T6 AnorB $end +$var wire 1 U6 AorB $end +$var wire 1 V6 AxorB $end +$var wire 1 W6 B $end +$var wire 3 X6 Command [2:0] $end +$var wire 1 Y6 OrNorXorOut $end +$var wire 1 Z6 XorNor $end +$var wire 1 [6 nXor $end +$scope module mux0 $end +$var wire 1 \6 S $end +$var wire 1 V6 in0 $end +$var wire 1 T6 in1 $end +$var wire 1 ]6 nS $end +$var wire 1 ^6 out0 $end +$var wire 1 _6 out1 $end +$var wire 1 Z6 outfinal $end +$upscope $end +$scope module mux1 $end +$var wire 1 `6 S $end +$var wire 1 Z6 in0 $end +$var wire 1 U6 in1 $end +$var wire 1 a6 nS $end +$var wire 1 b6 out0 $end +$var wire 1 c6 out1 $end +$var wire 1 Y6 outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin orbits[11] $end +$scope module attempt $end +$var wire 1 d6 A $end +$var wire 1 e6 AnandB $end +$var wire 1 f6 AnorB $end +$var wire 1 g6 AorB $end +$var wire 1 h6 AxorB $end +$var wire 1 i6 B $end +$var wire 3 j6 Command [2:0] $end +$var wire 1 k6 OrNorXorOut $end +$var wire 1 l6 XorNor $end +$var wire 1 m6 nXor $end +$scope module mux0 $end +$var wire 1 n6 S $end +$var wire 1 h6 in0 $end +$var wire 1 f6 in1 $end +$var wire 1 o6 nS $end +$var wire 1 p6 out0 $end +$var wire 1 q6 out1 $end +$var wire 1 l6 outfinal $end +$upscope $end +$scope module mux1 $end +$var wire 1 r6 S $end +$var wire 1 l6 in0 $end +$var wire 1 g6 in1 $end +$var wire 1 s6 nS $end +$var wire 1 t6 out0 $end +$var wire 1 u6 out1 $end +$var wire 1 k6 outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin orbits[12] $end +$scope module attempt $end +$var wire 1 v6 A $end +$var wire 1 w6 AnandB $end +$var wire 1 x6 AnorB $end +$var wire 1 y6 AorB $end +$var wire 1 z6 AxorB $end +$var wire 1 {6 B $end +$var wire 3 |6 Command [2:0] $end +$var wire 1 }6 OrNorXorOut $end +$var wire 1 ~6 XorNor $end +$var wire 1 !7 nXor $end +$scope module mux0 $end +$var wire 1 "7 S $end +$var wire 1 z6 in0 $end +$var wire 1 x6 in1 $end +$var wire 1 #7 nS $end +$var wire 1 $7 out0 $end +$var wire 1 %7 out1 $end +$var wire 1 ~6 outfinal $end +$upscope $end +$scope module mux1 $end +$var wire 1 &7 S $end +$var wire 1 ~6 in0 $end +$var wire 1 y6 in1 $end +$var wire 1 '7 nS $end +$var wire 1 (7 out0 $end +$var wire 1 )7 out1 $end +$var wire 1 }6 outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin orbits[13] $end +$scope module attempt $end +$var wire 1 *7 A $end +$var wire 1 +7 AnandB $end +$var wire 1 ,7 AnorB $end +$var wire 1 -7 AorB $end +$var wire 1 .7 AxorB $end +$var wire 1 /7 B $end +$var wire 3 07 Command [2:0] $end +$var wire 1 17 OrNorXorOut $end +$var wire 1 27 XorNor $end +$var wire 1 37 nXor $end +$scope module mux0 $end +$var wire 1 47 S $end +$var wire 1 .7 in0 $end +$var wire 1 ,7 in1 $end +$var wire 1 57 nS $end +$var wire 1 67 out0 $end +$var wire 1 77 out1 $end +$var wire 1 27 outfinal $end +$upscope $end +$scope module mux1 $end +$var wire 1 87 S $end +$var wire 1 27 in0 $end +$var wire 1 -7 in1 $end +$var wire 1 97 nS $end +$var wire 1 :7 out0 $end +$var wire 1 ;7 out1 $end +$var wire 1 17 outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin orbits[14] $end +$scope module attempt $end +$var wire 1 <7 A $end +$var wire 1 =7 AnandB $end +$var wire 1 >7 AnorB $end +$var wire 1 ?7 AorB $end +$var wire 1 @7 AxorB $end +$var wire 1 A7 B $end +$var wire 3 B7 Command [2:0] $end +$var wire 1 C7 OrNorXorOut $end +$var wire 1 D7 XorNor $end +$var wire 1 E7 nXor $end +$scope module mux0 $end +$var wire 1 F7 S $end +$var wire 1 @7 in0 $end +$var wire 1 >7 in1 $end +$var wire 1 G7 nS $end +$var wire 1 H7 out0 $end +$var wire 1 I7 out1 $end +$var wire 1 D7 outfinal $end +$upscope $end +$scope module mux1 $end +$var wire 1 J7 S $end +$var wire 1 D7 in0 $end +$var wire 1 ?7 in1 $end +$var wire 1 K7 nS $end +$var wire 1 L7 out0 $end +$var wire 1 M7 out1 $end +$var wire 1 C7 outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin orbits[15] $end +$scope module attempt $end +$var wire 1 N7 A $end +$var wire 1 O7 AnandB $end +$var wire 1 P7 AnorB $end +$var wire 1 Q7 AorB $end +$var wire 1 R7 AxorB $end +$var wire 1 S7 B $end +$var wire 3 T7 Command [2:0] $end +$var wire 1 U7 OrNorXorOut $end +$var wire 1 V7 XorNor $end +$var wire 1 W7 nXor $end +$scope module mux0 $end +$var wire 1 X7 S $end +$var wire 1 R7 in0 $end +$var wire 1 P7 in1 $end +$var wire 1 Y7 nS $end +$var wire 1 Z7 out0 $end +$var wire 1 [7 out1 $end +$var wire 1 V7 outfinal $end +$upscope $end +$scope module mux1 $end +$var wire 1 \7 S $end +$var wire 1 V7 in0 $end +$var wire 1 Q7 in1 $end +$var wire 1 ]7 nS $end +$var wire 1 ^7 out0 $end +$var wire 1 _7 out1 $end +$var wire 1 U7 outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin orbits[16] $end +$scope module attempt $end +$var wire 1 `7 A $end +$var wire 1 a7 AnandB $end +$var wire 1 b7 AnorB $end +$var wire 1 c7 AorB $end +$var wire 1 d7 AxorB $end +$var wire 1 e7 B $end +$var wire 3 f7 Command [2:0] $end +$var wire 1 g7 OrNorXorOut $end +$var wire 1 h7 XorNor $end +$var wire 1 i7 nXor $end +$scope module mux0 $end +$var wire 1 j7 S $end +$var wire 1 d7 in0 $end +$var wire 1 b7 in1 $end +$var wire 1 k7 nS $end +$var wire 1 l7 out0 $end +$var wire 1 m7 out1 $end +$var wire 1 h7 outfinal $end +$upscope $end +$scope module mux1 $end +$var wire 1 n7 S $end +$var wire 1 h7 in0 $end +$var wire 1 c7 in1 $end +$var wire 1 o7 nS $end +$var wire 1 p7 out0 $end +$var wire 1 q7 out1 $end +$var wire 1 g7 outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin orbits[17] $end +$scope module attempt $end +$var wire 1 r7 A $end +$var wire 1 s7 AnandB $end +$var wire 1 t7 AnorB $end +$var wire 1 u7 AorB $end +$var wire 1 v7 AxorB $end +$var wire 1 w7 B $end +$var wire 3 x7 Command [2:0] $end +$var wire 1 y7 OrNorXorOut $end +$var wire 1 z7 XorNor $end +$var wire 1 {7 nXor $end +$scope module mux0 $end +$var wire 1 |7 S $end +$var wire 1 v7 in0 $end +$var wire 1 t7 in1 $end +$var wire 1 }7 nS $end +$var wire 1 ~7 out0 $end +$var wire 1 !8 out1 $end +$var wire 1 z7 outfinal $end +$upscope $end +$scope module mux1 $end +$var wire 1 "8 S $end +$var wire 1 z7 in0 $end +$var wire 1 u7 in1 $end +$var wire 1 #8 nS $end +$var wire 1 $8 out0 $end +$var wire 1 %8 out1 $end +$var wire 1 y7 outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin orbits[18] $end +$scope module attempt $end +$var wire 1 &8 A $end +$var wire 1 '8 AnandB $end +$var wire 1 (8 AnorB $end +$var wire 1 )8 AorB $end +$var wire 1 *8 AxorB $end +$var wire 1 +8 B $end +$var wire 3 ,8 Command [2:0] $end +$var wire 1 -8 OrNorXorOut $end +$var wire 1 .8 XorNor $end +$var wire 1 /8 nXor $end +$scope module mux0 $end +$var wire 1 08 S $end +$var wire 1 *8 in0 $end +$var wire 1 (8 in1 $end +$var wire 1 18 nS $end +$var wire 1 28 out0 $end +$var wire 1 38 out1 $end +$var wire 1 .8 outfinal $end +$upscope $end +$scope module mux1 $end +$var wire 1 48 S $end +$var wire 1 .8 in0 $end +$var wire 1 )8 in1 $end +$var wire 1 58 nS $end +$var wire 1 68 out0 $end +$var wire 1 78 out1 $end +$var wire 1 -8 outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin orbits[19] $end +$scope module attempt $end +$var wire 1 88 A $end +$var wire 1 98 AnandB $end +$var wire 1 :8 AnorB $end +$var wire 1 ;8 AorB $end +$var wire 1 <8 AxorB $end +$var wire 1 =8 B $end +$var wire 3 >8 Command [2:0] $end +$var wire 1 ?8 OrNorXorOut $end +$var wire 1 @8 XorNor $end +$var wire 1 A8 nXor $end +$scope module mux0 $end +$var wire 1 B8 S $end +$var wire 1 <8 in0 $end +$var wire 1 :8 in1 $end +$var wire 1 C8 nS $end +$var wire 1 D8 out0 $end +$var wire 1 E8 out1 $end +$var wire 1 @8 outfinal $end +$upscope $end +$scope module mux1 $end +$var wire 1 F8 S $end +$var wire 1 @8 in0 $end +$var wire 1 ;8 in1 $end +$var wire 1 G8 nS $end +$var wire 1 H8 out0 $end +$var wire 1 I8 out1 $end +$var wire 1 ?8 outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin orbits[20] $end +$scope module attempt $end +$var wire 1 J8 A $end +$var wire 1 K8 AnandB $end +$var wire 1 L8 AnorB $end +$var wire 1 M8 AorB $end +$var wire 1 N8 AxorB $end +$var wire 1 O8 B $end +$var wire 3 P8 Command [2:0] $end +$var wire 1 Q8 OrNorXorOut $end +$var wire 1 R8 XorNor $end +$var wire 1 S8 nXor $end +$scope module mux0 $end +$var wire 1 T8 S $end +$var wire 1 N8 in0 $end +$var wire 1 L8 in1 $end +$var wire 1 U8 nS $end +$var wire 1 V8 out0 $end +$var wire 1 W8 out1 $end +$var wire 1 R8 outfinal $end +$upscope $end +$scope module mux1 $end +$var wire 1 X8 S $end +$var wire 1 R8 in0 $end +$var wire 1 M8 in1 $end +$var wire 1 Y8 nS $end +$var wire 1 Z8 out0 $end +$var wire 1 [8 out1 $end +$var wire 1 Q8 outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin orbits[21] $end +$scope module attempt $end +$var wire 1 \8 A $end +$var wire 1 ]8 AnandB $end +$var wire 1 ^8 AnorB $end +$var wire 1 _8 AorB $end +$var wire 1 `8 AxorB $end +$var wire 1 a8 B $end +$var wire 3 b8 Command [2:0] $end +$var wire 1 c8 OrNorXorOut $end +$var wire 1 d8 XorNor $end +$var wire 1 e8 nXor $end +$scope module mux0 $end +$var wire 1 f8 S $end +$var wire 1 `8 in0 $end +$var wire 1 ^8 in1 $end +$var wire 1 g8 nS $end +$var wire 1 h8 out0 $end +$var wire 1 i8 out1 $end +$var wire 1 d8 outfinal $end +$upscope $end +$scope module mux1 $end +$var wire 1 j8 S $end +$var wire 1 d8 in0 $end +$var wire 1 _8 in1 $end +$var wire 1 k8 nS $end +$var wire 1 l8 out0 $end +$var wire 1 m8 out1 $end +$var wire 1 c8 outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin orbits[22] $end +$scope module attempt $end +$var wire 1 n8 A $end +$var wire 1 o8 AnandB $end +$var wire 1 p8 AnorB $end +$var wire 1 q8 AorB $end +$var wire 1 r8 AxorB $end +$var wire 1 s8 B $end +$var wire 3 t8 Command [2:0] $end +$var wire 1 u8 OrNorXorOut $end +$var wire 1 v8 XorNor $end +$var wire 1 w8 nXor $end +$scope module mux0 $end +$var wire 1 x8 S $end +$var wire 1 r8 in0 $end +$var wire 1 p8 in1 $end +$var wire 1 y8 nS $end +$var wire 1 z8 out0 $end +$var wire 1 {8 out1 $end +$var wire 1 v8 outfinal $end +$upscope $end +$scope module mux1 $end +$var wire 1 |8 S $end +$var wire 1 v8 in0 $end +$var wire 1 q8 in1 $end +$var wire 1 }8 nS $end +$var wire 1 ~8 out0 $end +$var wire 1 !9 out1 $end +$var wire 1 u8 outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin orbits[23] $end +$scope module attempt $end +$var wire 1 "9 A $end +$var wire 1 #9 AnandB $end +$var wire 1 $9 AnorB $end +$var wire 1 %9 AorB $end +$var wire 1 &9 AxorB $end +$var wire 1 '9 B $end +$var wire 3 (9 Command [2:0] $end +$var wire 1 )9 OrNorXorOut $end +$var wire 1 *9 XorNor $end +$var wire 1 +9 nXor $end +$scope module mux0 $end +$var wire 1 ,9 S $end +$var wire 1 &9 in0 $end +$var wire 1 $9 in1 $end +$var wire 1 -9 nS $end +$var wire 1 .9 out0 $end +$var wire 1 /9 out1 $end +$var wire 1 *9 outfinal $end +$upscope $end +$scope module mux1 $end +$var wire 1 09 S $end +$var wire 1 *9 in0 $end +$var wire 1 %9 in1 $end +$var wire 1 19 nS $end +$var wire 1 29 out0 $end +$var wire 1 39 out1 $end +$var wire 1 )9 outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin orbits[24] $end +$scope module attempt $end +$var wire 1 49 A $end +$var wire 1 59 AnandB $end +$var wire 1 69 AnorB $end +$var wire 1 79 AorB $end +$var wire 1 89 AxorB $end +$var wire 1 99 B $end +$var wire 3 :9 Command [2:0] $end +$var wire 1 ;9 OrNorXorOut $end +$var wire 1 <9 XorNor $end +$var wire 1 =9 nXor $end +$scope module mux0 $end +$var wire 1 >9 S $end +$var wire 1 89 in0 $end +$var wire 1 69 in1 $end +$var wire 1 ?9 nS $end +$var wire 1 @9 out0 $end +$var wire 1 A9 out1 $end +$var wire 1 <9 outfinal $end +$upscope $end +$scope module mux1 $end +$var wire 1 B9 S $end +$var wire 1 <9 in0 $end +$var wire 1 79 in1 $end +$var wire 1 C9 nS $end +$var wire 1 D9 out0 $end +$var wire 1 E9 out1 $end +$var wire 1 ;9 outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin orbits[25] $end +$scope module attempt $end +$var wire 1 F9 A $end +$var wire 1 G9 AnandB $end +$var wire 1 H9 AnorB $end +$var wire 1 I9 AorB $end +$var wire 1 J9 AxorB $end +$var wire 1 K9 B $end +$var wire 3 L9 Command [2:0] $end +$var wire 1 M9 OrNorXorOut $end +$var wire 1 N9 XorNor $end +$var wire 1 O9 nXor $end +$scope module mux0 $end +$var wire 1 P9 S $end +$var wire 1 J9 in0 $end +$var wire 1 H9 in1 $end +$var wire 1 Q9 nS $end +$var wire 1 R9 out0 $end +$var wire 1 S9 out1 $end +$var wire 1 N9 outfinal $end +$upscope $end +$scope module mux1 $end +$var wire 1 T9 S $end +$var wire 1 N9 in0 $end +$var wire 1 I9 in1 $end +$var wire 1 U9 nS $end +$var wire 1 V9 out0 $end +$var wire 1 W9 out1 $end +$var wire 1 M9 outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin orbits[26] $end +$scope module attempt $end +$var wire 1 X9 A $end +$var wire 1 Y9 AnandB $end +$var wire 1 Z9 AnorB $end +$var wire 1 [9 AorB $end +$var wire 1 \9 AxorB $end +$var wire 1 ]9 B $end +$var wire 3 ^9 Command [2:0] $end +$var wire 1 _9 OrNorXorOut $end +$var wire 1 `9 XorNor $end +$var wire 1 a9 nXor $end +$scope module mux0 $end +$var wire 1 b9 S $end +$var wire 1 \9 in0 $end +$var wire 1 Z9 in1 $end +$var wire 1 c9 nS $end +$var wire 1 d9 out0 $end +$var wire 1 e9 out1 $end +$var wire 1 `9 outfinal $end +$upscope $end +$scope module mux1 $end +$var wire 1 f9 S $end +$var wire 1 `9 in0 $end +$var wire 1 [9 in1 $end +$var wire 1 g9 nS $end +$var wire 1 h9 out0 $end +$var wire 1 i9 out1 $end +$var wire 1 _9 outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin orbits[27] $end +$scope module attempt $end +$var wire 1 j9 A $end +$var wire 1 k9 AnandB $end +$var wire 1 l9 AnorB $end +$var wire 1 m9 AorB $end +$var wire 1 n9 AxorB $end +$var wire 1 o9 B $end +$var wire 3 p9 Command [2:0] $end +$var wire 1 q9 OrNorXorOut $end +$var wire 1 r9 XorNor $end +$var wire 1 s9 nXor $end +$scope module mux0 $end +$var wire 1 t9 S $end +$var wire 1 n9 in0 $end +$var wire 1 l9 in1 $end +$var wire 1 u9 nS $end +$var wire 1 v9 out0 $end +$var wire 1 w9 out1 $end +$var wire 1 r9 outfinal $end +$upscope $end +$scope module mux1 $end +$var wire 1 x9 S $end +$var wire 1 r9 in0 $end +$var wire 1 m9 in1 $end +$var wire 1 y9 nS $end +$var wire 1 z9 out0 $end +$var wire 1 {9 out1 $end +$var wire 1 q9 outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin orbits[28] $end +$scope module attempt $end +$var wire 1 |9 A $end +$var wire 1 }9 AnandB $end +$var wire 1 ~9 AnorB $end +$var wire 1 !: AorB $end +$var wire 1 ": AxorB $end +$var wire 1 #: B $end +$var wire 3 $: Command [2:0] $end +$var wire 1 %: OrNorXorOut $end +$var wire 1 &: XorNor $end +$var wire 1 ': nXor $end +$scope module mux0 $end +$var wire 1 (: S $end +$var wire 1 ": in0 $end +$var wire 1 ~9 in1 $end +$var wire 1 ): nS $end +$var wire 1 *: out0 $end +$var wire 1 +: out1 $end +$var wire 1 &: outfinal $end +$upscope $end +$scope module mux1 $end +$var wire 1 ,: S $end +$var wire 1 &: in0 $end +$var wire 1 !: in1 $end +$var wire 1 -: nS $end +$var wire 1 .: out0 $end +$var wire 1 /: out1 $end +$var wire 1 %: outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin orbits[29] $end +$scope module attempt $end +$var wire 1 0: A $end +$var wire 1 1: AnandB $end +$var wire 1 2: AnorB $end +$var wire 1 3: AorB $end +$var wire 1 4: AxorB $end +$var wire 1 5: B $end +$var wire 3 6: Command [2:0] $end +$var wire 1 7: OrNorXorOut $end +$var wire 1 8: XorNor $end +$var wire 1 9: nXor $end +$scope module mux0 $end +$var wire 1 :: S $end +$var wire 1 4: in0 $end +$var wire 1 2: in1 $end +$var wire 1 ;: nS $end +$var wire 1 <: out0 $end +$var wire 1 =: out1 $end +$var wire 1 8: outfinal $end +$upscope $end +$scope module mux1 $end +$var wire 1 >: S $end +$var wire 1 8: in0 $end +$var wire 1 3: in1 $end +$var wire 1 ?: nS $end +$var wire 1 @: out0 $end +$var wire 1 A: out1 $end +$var wire 1 7: outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin orbits[30] $end +$scope module attempt $end +$var wire 1 B: A $end +$var wire 1 C: AnandB $end +$var wire 1 D: AnorB $end +$var wire 1 E: AorB $end +$var wire 1 F: AxorB $end +$var wire 1 G: B $end +$var wire 3 H: Command [2:0] $end +$var wire 1 I: OrNorXorOut $end +$var wire 1 J: XorNor $end +$var wire 1 K: nXor $end +$scope module mux0 $end +$var wire 1 L: S $end +$var wire 1 F: in0 $end +$var wire 1 D: in1 $end +$var wire 1 M: nS $end +$var wire 1 N: out0 $end +$var wire 1 O: out1 $end +$var wire 1 J: outfinal $end +$upscope $end +$scope module mux1 $end +$var wire 1 P: S $end +$var wire 1 J: in0 $end +$var wire 1 E: in1 $end +$var wire 1 Q: nS $end +$var wire 1 R: out0 $end +$var wire 1 S: out1 $end +$var wire 1 I: outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin orbits[31] $end +$scope module attempt $end +$var wire 1 T: A $end +$var wire 1 U: AnandB $end +$var wire 1 V: AnorB $end +$var wire 1 W: AorB $end +$var wire 1 X: AxorB $end +$var wire 1 Y: B $end +$var wire 3 Z: Command [2:0] $end +$var wire 1 [: OrNorXorOut $end +$var wire 1 \: XorNor $end +$var wire 1 ]: nXor $end +$scope module mux0 $end +$var wire 1 ^: S $end +$var wire 1 X: in0 $end +$var wire 1 V: in1 $end +$var wire 1 _: nS $end +$var wire 1 `: out0 $end +$var wire 1 a: out1 $end +$var wire 1 \: outfinal $end +$upscope $end +$scope module mux1 $end +$var wire 1 b: S $end +$var wire 1 \: in0 $end +$var wire 1 W: in1 $end +$var wire 1 c: nS $end +$var wire 1 d: out0 $end +$var wire 1 e: out1 $end +$var wire 1 [: outfinal $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope module superalu $end +$var wire 32 f: A [31:0] $end +$var wire 32 g: AddSubSLTSum [31:0] $end +$var wire 1 " AllZeros $end +$var wire 32 h: AndNandOut [31:0] $end +$var wire 32 i: B [31:0] $end +$var wire 32 j: Cmd0Start [31:0] $end +$var wire 32 k: Cmd1Start [31:0] $end +$var wire 3 l: Command [2:0] $end +$var wire 32 m: OneBitFinalOut [31:0] $end +$var wire 32 n: OrNorXorOut [31:0] $end +$var wire 32 o: SLTSum [31:0] $end +$var wire 1 ) SLTflag $end +$var wire 32 p: ZeroFlag [31:0] $end +$var wire 32 q: carryin [31:0] $end +$var wire 1 , carryout $end +$var wire 1 . overflow $end +$var wire 32 r: subtract [31:0] $end +$var wire 1 s: yeszero $end +$scope module test $end +$var wire 32 t: A [31:0] $end +$var wire 32 u: AddSubSLTSum [31:0] $end +$var wire 32 v: B [31:0] $end +$var wire 32 w: CarryoutWire [31:0] $end +$var wire 3 x: Command [2:0] $end +$var wire 32 y: NewVal [31:0] $end +$var wire 1 z: Res0OF1 $end +$var wire 1 {: Res1OF0 $end +$var wire 32 |: SLTSum [31:0] $end +$var wire 1 ) SLTflag $end +$var wire 1 }: SLTflag0 $end +$var wire 1 ~: SLTflag1 $end +$var wire 1 !; SLTon $end +$var wire 32 "; carryin [31:0] $end +$var wire 1 , carryout $end +$var wire 1 #; nAddSubSLTSum $end +$var wire 1 $; nCmd2 $end +$var wire 1 %; nOF $end +$var wire 1 . overflow $end +$var wire 32 &; subtract [31:0] $end +$scope module attempt2 $end +$var wire 1 '; A $end +$var wire 1 (; AandB $end +$var wire 1 ); AddSubSLTSum $end +$var wire 1 *; AxorB $end +$var wire 1 +; B $end +$var wire 1 ,; BornB $end +$var wire 1 -; CINandAxorB $end +$var wire 3 .; Command [2:0] $end +$var wire 1 /; carryin $end +$var wire 1 0; carryout $end +$var wire 1 1; nB $end +$var wire 1 2; nCmd2 $end +$var wire 1 3; subtract $end +$scope module mux0 $end +$var wire 1 4; S $end +$var wire 1 +; in0 $end +$var wire 1 1; in1 $end +$var wire 1 5; nS $end +$var wire 1 6; out0 $end +$var wire 1 7; out1 $end +$var wire 1 ,; outfinal $end +$upscope $end +$upscope $end +$scope module setSLTresult $end +$var wire 1 !; S $end +$var wire 1 8; in0 $end +$var wire 1 9; in1 $end +$var wire 1 :; nS $end +$var wire 1 ;; out0 $end +$var wire 1 <; out1 $end +$var wire 1 =; outfinal $end +$upscope $end +$scope module FinalSLT $end +$var wire 1 ) S $end +$var wire 1 >; in0 $end +$var wire 1 ) in1 $end +$var wire 1 ?; nS $end +$var wire 1 @; out0 $end +$var wire 1 A; out1 $end +$var wire 1 B; outfinal $end +$upscope $end +$scope begin sltbits[1] $end +$scope module attempt $end +$var wire 1 C; A $end +$var wire 1 D; AandB $end +$var wire 1 E; AddSubSLTSum $end +$var wire 1 F; AxorB $end +$var wire 1 G; B $end +$var wire 1 H; BornB $end +$var wire 1 I; CINandAxorB $end +$var wire 3 J; Command [2:0] $end +$var wire 1 K; carryin $end +$var wire 1 L; carryout $end +$var wire 1 M; nB $end +$var wire 1 N; nCmd2 $end +$var wire 1 O; subtract $end +$scope module mux0 $end +$var wire 1 P; S $end +$var wire 1 G; in0 $end +$var wire 1 M; in1 $end +$var wire 1 Q; nS $end +$var wire 1 R; out0 $end +$var wire 1 S; out1 $end +$var wire 1 H; outfinal $end +$upscope $end +$upscope $end +$scope module setSLTres2 $end +$var wire 1 !; S $end +$var wire 1 T; in0 $end +$var wire 1 U; in1 $end +$var wire 1 V; nS $end +$var wire 1 W; out0 $end +$var wire 1 X; out1 $end +$var wire 1 Y; outfinal $end +$upscope $end +$scope module setSLTres3 $end +$var wire 1 !; S $end +$var wire 1 Z; in0 $end +$var wire 1 [; in1 $end +$var wire 1 \; nS $end +$var wire 1 ]; out0 $end +$var wire 1 ^; out1 $end +$var wire 1 _; outfinal $end +$upscope $end +$upscope $end +$scope begin sltbits[2] $end +$scope module attempt $end +$var wire 1 `; A $end +$var wire 1 a; AandB $end +$var wire 1 b; AddSubSLTSum $end +$var wire 1 c; AxorB $end +$var wire 1 d; B $end +$var wire 1 e; BornB $end +$var wire 1 f; CINandAxorB $end +$var wire 3 g; Command [2:0] $end +$var wire 1 h; carryin $end +$var wire 1 i; carryout $end +$var wire 1 j; nB $end +$var wire 1 k; nCmd2 $end +$var wire 1 l; subtract $end +$scope module mux0 $end +$var wire 1 m; S $end +$var wire 1 d; in0 $end +$var wire 1 j; in1 $end +$var wire 1 n; nS $end +$var wire 1 o; out0 $end +$var wire 1 p; out1 $end +$var wire 1 e; outfinal $end +$upscope $end +$upscope $end +$scope module setSLTres2 $end +$var wire 1 !; S $end +$var wire 1 q; in0 $end +$var wire 1 r; in1 $end +$var wire 1 s; nS $end +$var wire 1 t; out0 $end +$var wire 1 u; out1 $end +$var wire 1 v; outfinal $end +$upscope $end +$scope module setSLTres3 $end +$var wire 1 !; S $end +$var wire 1 w; in0 $end +$var wire 1 x; in1 $end +$var wire 1 y; nS $end +$var wire 1 z; out0 $end +$var wire 1 {; out1 $end +$var wire 1 |; outfinal $end +$upscope $end +$upscope $end +$scope begin sltbits[3] $end +$scope module attempt $end +$var wire 1 }; A $end +$var wire 1 ~; AandB $end +$var wire 1 !< AddSubSLTSum $end +$var wire 1 "< AxorB $end +$var wire 1 #< B $end +$var wire 1 $< BornB $end +$var wire 1 %< CINandAxorB $end +$var wire 3 &< Command [2:0] $end +$var wire 1 '< carryin $end +$var wire 1 (< carryout $end +$var wire 1 )< nB $end +$var wire 1 *< nCmd2 $end +$var wire 1 +< subtract $end +$scope module mux0 $end +$var wire 1 ,< S $end +$var wire 1 #< in0 $end +$var wire 1 )< in1 $end +$var wire 1 -< nS $end +$var wire 1 .< out0 $end +$var wire 1 /< out1 $end +$var wire 1 $< outfinal $end +$upscope $end +$upscope $end +$scope module setSLTres2 $end +$var wire 1 !; S $end +$var wire 1 0< in0 $end +$var wire 1 1< in1 $end +$var wire 1 2< nS $end +$var wire 1 3< out0 $end +$var wire 1 4< out1 $end +$var wire 1 5< outfinal $end +$upscope $end +$scope module setSLTres3 $end +$var wire 1 !; S $end +$var wire 1 6< in0 $end +$var wire 1 7< in1 $end +$var wire 1 8< nS $end +$var wire 1 9< out0 $end +$var wire 1 :< out1 $end +$var wire 1 ;< outfinal $end +$upscope $end +$upscope $end +$scope begin sltbits[4] $end +$scope module attempt $end +$var wire 1 << A $end +$var wire 1 =< AandB $end +$var wire 1 >< AddSubSLTSum $end +$var wire 1 ?< AxorB $end +$var wire 1 @< B $end +$var wire 1 A< BornB $end +$var wire 1 B< CINandAxorB $end +$var wire 3 C< Command [2:0] $end +$var wire 1 D< carryin $end +$var wire 1 E< carryout $end +$var wire 1 F< nB $end +$var wire 1 G< nCmd2 $end +$var wire 1 H< subtract $end +$scope module mux0 $end +$var wire 1 I< S $end +$var wire 1 @< in0 $end +$var wire 1 F< in1 $end +$var wire 1 J< nS $end +$var wire 1 K< out0 $end +$var wire 1 L< out1 $end +$var wire 1 A< outfinal $end +$upscope $end +$upscope $end +$scope module setSLTres2 $end +$var wire 1 !; S $end +$var wire 1 M< in0 $end +$var wire 1 N< in1 $end +$var wire 1 O< nS $end +$var wire 1 P< out0 $end +$var wire 1 Q< out1 $end +$var wire 1 R< outfinal $end +$upscope $end +$scope module setSLTres3 $end +$var wire 1 !; S $end +$var wire 1 S< in0 $end +$var wire 1 T< in1 $end +$var wire 1 U< nS $end +$var wire 1 V< out0 $end +$var wire 1 W< out1 $end +$var wire 1 X< outfinal $end +$upscope $end +$upscope $end +$scope begin sltbits[5] $end +$scope module attempt $end +$var wire 1 Y< A $end +$var wire 1 Z< AandB $end +$var wire 1 [< AddSubSLTSum $end +$var wire 1 \< AxorB $end +$var wire 1 ]< B $end +$var wire 1 ^< BornB $end +$var wire 1 _< CINandAxorB $end +$var wire 3 `< Command [2:0] $end +$var wire 1 a< carryin $end +$var wire 1 b< carryout $end +$var wire 1 c< nB $end +$var wire 1 d< nCmd2 $end +$var wire 1 e< subtract $end +$scope module mux0 $end +$var wire 1 f< S $end +$var wire 1 ]< in0 $end +$var wire 1 c< in1 $end +$var wire 1 g< nS $end +$var wire 1 h< out0 $end +$var wire 1 i< out1 $end +$var wire 1 ^< outfinal $end +$upscope $end +$upscope $end +$scope module setSLTres2 $end +$var wire 1 !; S $end +$var wire 1 j< in0 $end +$var wire 1 k< in1 $end +$var wire 1 l< nS $end +$var wire 1 m< out0 $end +$var wire 1 n< out1 $end +$var wire 1 o< outfinal $end +$upscope $end +$scope module setSLTres3 $end +$var wire 1 !; S $end +$var wire 1 p< in0 $end +$var wire 1 q< in1 $end +$var wire 1 r< nS $end +$var wire 1 s< out0 $end +$var wire 1 t< out1 $end +$var wire 1 u< outfinal $end +$upscope $end +$upscope $end +$scope begin sltbits[6] $end +$scope module attempt $end +$var wire 1 v< A $end +$var wire 1 w< AandB $end +$var wire 1 x< AddSubSLTSum $end +$var wire 1 y< AxorB $end +$var wire 1 z< B $end +$var wire 1 {< BornB $end +$var wire 1 |< CINandAxorB $end +$var wire 3 }< Command [2:0] $end +$var wire 1 ~< carryin $end +$var wire 1 != carryout $end +$var wire 1 "= nB $end +$var wire 1 #= nCmd2 $end +$var wire 1 $= subtract $end +$scope module mux0 $end +$var wire 1 %= S $end +$var wire 1 z< in0 $end +$var wire 1 "= in1 $end +$var wire 1 &= nS $end +$var wire 1 '= out0 $end +$var wire 1 (= out1 $end +$var wire 1 {< outfinal $end +$upscope $end +$upscope $end +$scope module setSLTres2 $end +$var wire 1 !; S $end +$var wire 1 )= in0 $end +$var wire 1 *= in1 $end +$var wire 1 += nS $end +$var wire 1 ,= out0 $end +$var wire 1 -= out1 $end +$var wire 1 .= outfinal $end +$upscope $end +$scope module setSLTres3 $end +$var wire 1 !; S $end +$var wire 1 /= in0 $end +$var wire 1 0= in1 $end +$var wire 1 1= nS $end +$var wire 1 2= out0 $end +$var wire 1 3= out1 $end +$var wire 1 4= outfinal $end +$upscope $end +$upscope $end +$scope begin sltbits[7] $end +$scope module attempt $end +$var wire 1 5= A $end +$var wire 1 6= AandB $end +$var wire 1 7= AddSubSLTSum $end +$var wire 1 8= AxorB $end +$var wire 1 9= B $end +$var wire 1 := BornB $end +$var wire 1 ;= CINandAxorB $end +$var wire 3 <= Command [2:0] $end +$var wire 1 == carryin $end +$var wire 1 >= carryout $end +$var wire 1 ?= nB $end +$var wire 1 @= nCmd2 $end +$var wire 1 A= subtract $end +$scope module mux0 $end +$var wire 1 B= S $end +$var wire 1 9= in0 $end +$var wire 1 ?= in1 $end +$var wire 1 C= nS $end +$var wire 1 D= out0 $end +$var wire 1 E= out1 $end +$var wire 1 := outfinal $end +$upscope $end +$upscope $end +$scope module setSLTres2 $end +$var wire 1 !; S $end +$var wire 1 F= in0 $end +$var wire 1 G= in1 $end +$var wire 1 H= nS $end +$var wire 1 I= out0 $end +$var wire 1 J= out1 $end +$var wire 1 K= outfinal $end +$upscope $end +$scope module setSLTres3 $end +$var wire 1 !; S $end +$var wire 1 L= in0 $end +$var wire 1 M= in1 $end +$var wire 1 N= nS $end +$var wire 1 O= out0 $end +$var wire 1 P= out1 $end +$var wire 1 Q= outfinal $end +$upscope $end +$upscope $end +$scope begin sltbits[8] $end +$scope module attempt $end +$var wire 1 R= A $end +$var wire 1 S= AandB $end +$var wire 1 T= AddSubSLTSum $end +$var wire 1 U= AxorB $end +$var wire 1 V= B $end +$var wire 1 W= BornB $end +$var wire 1 X= CINandAxorB $end +$var wire 3 Y= Command [2:0] $end +$var wire 1 Z= carryin $end +$var wire 1 [= carryout $end +$var wire 1 \= nB $end +$var wire 1 ]= nCmd2 $end +$var wire 1 ^= subtract $end +$scope module mux0 $end +$var wire 1 _= S $end +$var wire 1 V= in0 $end +$var wire 1 \= in1 $end +$var wire 1 `= nS $end +$var wire 1 a= out0 $end +$var wire 1 b= out1 $end +$var wire 1 W= outfinal $end +$upscope $end +$upscope $end +$scope module setSLTres2 $end +$var wire 1 !; S $end +$var wire 1 c= in0 $end +$var wire 1 d= in1 $end +$var wire 1 e= nS $end +$var wire 1 f= out0 $end +$var wire 1 g= out1 $end +$var wire 1 h= outfinal $end +$upscope $end +$scope module setSLTres3 $end +$var wire 1 !; S $end +$var wire 1 i= in0 $end +$var wire 1 j= in1 $end +$var wire 1 k= nS $end +$var wire 1 l= out0 $end +$var wire 1 m= out1 $end +$var wire 1 n= outfinal $end +$upscope $end +$upscope $end +$scope begin sltbits[9] $end +$scope module attempt $end +$var wire 1 o= A $end +$var wire 1 p= AandB $end +$var wire 1 q= AddSubSLTSum $end +$var wire 1 r= AxorB $end +$var wire 1 s= B $end +$var wire 1 t= BornB $end +$var wire 1 u= CINandAxorB $end +$var wire 3 v= Command [2:0] $end +$var wire 1 w= carryin $end +$var wire 1 x= carryout $end +$var wire 1 y= nB $end +$var wire 1 z= nCmd2 $end +$var wire 1 {= subtract $end +$scope module mux0 $end +$var wire 1 |= S $end +$var wire 1 s= in0 $end +$var wire 1 y= in1 $end +$var wire 1 }= nS $end +$var wire 1 ~= out0 $end +$var wire 1 !> out1 $end +$var wire 1 t= outfinal $end +$upscope $end +$upscope $end +$scope module setSLTres2 $end +$var wire 1 !; S $end +$var wire 1 "> in0 $end +$var wire 1 #> in1 $end +$var wire 1 $> nS $end +$var wire 1 %> out0 $end +$var wire 1 &> out1 $end +$var wire 1 '> outfinal $end +$upscope $end +$scope module setSLTres3 $end +$var wire 1 !; S $end +$var wire 1 (> in0 $end +$var wire 1 )> in1 $end +$var wire 1 *> nS $end +$var wire 1 +> out0 $end +$var wire 1 ,> out1 $end +$var wire 1 -> outfinal $end +$upscope $end +$upscope $end +$scope begin sltbits[10] $end +$scope module attempt $end +$var wire 1 .> A $end +$var wire 1 /> AandB $end +$var wire 1 0> AddSubSLTSum $end +$var wire 1 1> AxorB $end +$var wire 1 2> B $end +$var wire 1 3> BornB $end +$var wire 1 4> CINandAxorB $end +$var wire 3 5> Command [2:0] $end +$var wire 1 6> carryin $end +$var wire 1 7> carryout $end +$var wire 1 8> nB $end +$var wire 1 9> nCmd2 $end +$var wire 1 :> subtract $end +$scope module mux0 $end +$var wire 1 ;> S $end +$var wire 1 2> in0 $end +$var wire 1 8> in1 $end +$var wire 1 <> nS $end +$var wire 1 => out0 $end +$var wire 1 >> out1 $end +$var wire 1 3> outfinal $end +$upscope $end +$upscope $end +$scope module setSLTres2 $end +$var wire 1 !; S $end +$var wire 1 ?> in0 $end +$var wire 1 @> in1 $end +$var wire 1 A> nS $end +$var wire 1 B> out0 $end +$var wire 1 C> out1 $end +$var wire 1 D> outfinal $end +$upscope $end +$scope module setSLTres3 $end +$var wire 1 !; S $end +$var wire 1 E> in0 $end +$var wire 1 F> in1 $end +$var wire 1 G> nS $end +$var wire 1 H> out0 $end +$var wire 1 I> out1 $end +$var wire 1 J> outfinal $end +$upscope $end +$upscope $end +$scope begin sltbits[11] $end +$scope module attempt $end +$var wire 1 K> A $end +$var wire 1 L> AandB $end +$var wire 1 M> AddSubSLTSum $end +$var wire 1 N> AxorB $end +$var wire 1 O> B $end +$var wire 1 P> BornB $end +$var wire 1 Q> CINandAxorB $end +$var wire 3 R> Command [2:0] $end +$var wire 1 S> carryin $end +$var wire 1 T> carryout $end +$var wire 1 U> nB $end +$var wire 1 V> nCmd2 $end +$var wire 1 W> subtract $end +$scope module mux0 $end +$var wire 1 X> S $end +$var wire 1 O> in0 $end +$var wire 1 U> in1 $end +$var wire 1 Y> nS $end +$var wire 1 Z> out0 $end +$var wire 1 [> out1 $end +$var wire 1 P> outfinal $end +$upscope $end +$upscope $end +$scope module setSLTres2 $end +$var wire 1 !; S $end +$var wire 1 \> in0 $end +$var wire 1 ]> in1 $end +$var wire 1 ^> nS $end +$var wire 1 _> out0 $end +$var wire 1 `> out1 $end +$var wire 1 a> outfinal $end +$upscope $end +$scope module setSLTres3 $end +$var wire 1 !; S $end +$var wire 1 b> in0 $end +$var wire 1 c> in1 $end +$var wire 1 d> nS $end +$var wire 1 e> out0 $end +$var wire 1 f> out1 $end +$var wire 1 g> outfinal $end +$upscope $end +$upscope $end +$scope begin sltbits[12] $end +$scope module attempt $end +$var wire 1 h> A $end +$var wire 1 i> AandB $end +$var wire 1 j> AddSubSLTSum $end +$var wire 1 k> AxorB $end +$var wire 1 l> B $end +$var wire 1 m> BornB $end +$var wire 1 n> CINandAxorB $end +$var wire 3 o> Command [2:0] $end +$var wire 1 p> carryin $end +$var wire 1 q> carryout $end +$var wire 1 r> nB $end +$var wire 1 s> nCmd2 $end +$var wire 1 t> subtract $end +$scope module mux0 $end +$var wire 1 u> S $end +$var wire 1 l> in0 $end +$var wire 1 r> in1 $end +$var wire 1 v> nS $end +$var wire 1 w> out0 $end +$var wire 1 x> out1 $end +$var wire 1 m> outfinal $end +$upscope $end +$upscope $end +$scope module setSLTres2 $end +$var wire 1 !; S $end +$var wire 1 y> in0 $end +$var wire 1 z> in1 $end +$var wire 1 {> nS $end +$var wire 1 |> out0 $end +$var wire 1 }> out1 $end +$var wire 1 ~> outfinal $end +$upscope $end +$scope module setSLTres3 $end +$var wire 1 !; S $end +$var wire 1 !? in0 $end +$var wire 1 "? in1 $end +$var wire 1 #? nS $end +$var wire 1 $? out0 $end +$var wire 1 %? out1 $end +$var wire 1 &? outfinal $end +$upscope $end +$upscope $end +$scope begin sltbits[13] $end +$scope module attempt $end +$var wire 1 '? A $end +$var wire 1 (? AandB $end +$var wire 1 )? AddSubSLTSum $end +$var wire 1 *? AxorB $end +$var wire 1 +? B $end +$var wire 1 ,? BornB $end +$var wire 1 -? CINandAxorB $end +$var wire 3 .? Command [2:0] $end +$var wire 1 /? carryin $end +$var wire 1 0? carryout $end +$var wire 1 1? nB $end +$var wire 1 2? nCmd2 $end +$var wire 1 3? subtract $end +$scope module mux0 $end +$var wire 1 4? S $end +$var wire 1 +? in0 $end +$var wire 1 1? in1 $end +$var wire 1 5? nS $end +$var wire 1 6? out0 $end +$var wire 1 7? out1 $end +$var wire 1 ,? outfinal $end +$upscope $end +$upscope $end +$scope module setSLTres2 $end +$var wire 1 !; S $end +$var wire 1 8? in0 $end +$var wire 1 9? in1 $end +$var wire 1 :? nS $end +$var wire 1 ;? out0 $end +$var wire 1 ? in0 $end +$var wire 1 ?? in1 $end +$var wire 1 @? nS $end +$var wire 1 A? out0 $end +$var wire 1 B? out1 $end +$var wire 1 C? outfinal $end +$upscope $end +$upscope $end +$scope begin sltbits[14] $end +$scope module attempt $end +$var wire 1 D? A $end +$var wire 1 E? AandB $end +$var wire 1 F? AddSubSLTSum $end +$var wire 1 G? AxorB $end +$var wire 1 H? B $end +$var wire 1 I? BornB $end +$var wire 1 J? CINandAxorB $end +$var wire 3 K? Command [2:0] $end +$var wire 1 L? carryin $end +$var wire 1 M? carryout $end +$var wire 1 N? nB $end +$var wire 1 O? nCmd2 $end +$var wire 1 P? subtract $end +$scope module mux0 $end +$var wire 1 Q? S $end +$var wire 1 H? in0 $end +$var wire 1 N? in1 $end +$var wire 1 R? nS $end +$var wire 1 S? out0 $end +$var wire 1 T? out1 $end +$var wire 1 I? outfinal $end +$upscope $end +$upscope $end +$scope module setSLTres2 $end +$var wire 1 !; S $end +$var wire 1 U? in0 $end +$var wire 1 V? in1 $end +$var wire 1 W? nS $end +$var wire 1 X? out0 $end +$var wire 1 Y? out1 $end +$var wire 1 Z? outfinal $end +$upscope $end +$scope module setSLTres3 $end +$var wire 1 !; S $end +$var wire 1 [? in0 $end +$var wire 1 \? in1 $end +$var wire 1 ]? nS $end +$var wire 1 ^? out0 $end +$var wire 1 _? out1 $end +$var wire 1 `? outfinal $end +$upscope $end +$upscope $end +$scope begin sltbits[15] $end +$scope module attempt $end +$var wire 1 a? A $end +$var wire 1 b? AandB $end +$var wire 1 c? AddSubSLTSum $end +$var wire 1 d? AxorB $end +$var wire 1 e? B $end +$var wire 1 f? BornB $end +$var wire 1 g? CINandAxorB $end +$var wire 3 h? Command [2:0] $end +$var wire 1 i? carryin $end +$var wire 1 j? carryout $end +$var wire 1 k? nB $end +$var wire 1 l? nCmd2 $end +$var wire 1 m? subtract $end +$scope module mux0 $end +$var wire 1 n? S $end +$var wire 1 e? in0 $end +$var wire 1 k? in1 $end +$var wire 1 o? nS $end +$var wire 1 p? out0 $end +$var wire 1 q? out1 $end +$var wire 1 f? outfinal $end +$upscope $end +$upscope $end +$scope module setSLTres2 $end +$var wire 1 !; S $end +$var wire 1 r? in0 $end +$var wire 1 s? in1 $end +$var wire 1 t? nS $end +$var wire 1 u? out0 $end +$var wire 1 v? out1 $end +$var wire 1 w? outfinal $end +$upscope $end +$scope module setSLTres3 $end +$var wire 1 !; S $end +$var wire 1 x? in0 $end +$var wire 1 y? in1 $end +$var wire 1 z? nS $end +$var wire 1 {? out0 $end +$var wire 1 |? out1 $end +$var wire 1 }? outfinal $end +$upscope $end +$upscope $end +$scope begin sltbits[16] $end +$scope module attempt $end +$var wire 1 ~? A $end +$var wire 1 !@ AandB $end +$var wire 1 "@ AddSubSLTSum $end +$var wire 1 #@ AxorB $end +$var wire 1 $@ B $end +$var wire 1 %@ BornB $end +$var wire 1 &@ CINandAxorB $end +$var wire 3 '@ Command [2:0] $end +$var wire 1 (@ carryin $end +$var wire 1 )@ carryout $end +$var wire 1 *@ nB $end +$var wire 1 +@ nCmd2 $end +$var wire 1 ,@ subtract $end +$scope module mux0 $end +$var wire 1 -@ S $end +$var wire 1 $@ in0 $end +$var wire 1 *@ in1 $end +$var wire 1 .@ nS $end +$var wire 1 /@ out0 $end +$var wire 1 0@ out1 $end +$var wire 1 %@ outfinal $end +$upscope $end +$upscope $end +$scope module setSLTres2 $end +$var wire 1 !; S $end +$var wire 1 1@ in0 $end +$var wire 1 2@ in1 $end +$var wire 1 3@ nS $end +$var wire 1 4@ out0 $end +$var wire 1 5@ out1 $end +$var wire 1 6@ outfinal $end +$upscope $end +$scope module setSLTres3 $end +$var wire 1 !; S $end +$var wire 1 7@ in0 $end +$var wire 1 8@ in1 $end +$var wire 1 9@ nS $end +$var wire 1 :@ out0 $end +$var wire 1 ;@ out1 $end +$var wire 1 <@ outfinal $end +$upscope $end +$upscope $end +$scope begin sltbits[17] $end +$scope module attempt $end +$var wire 1 =@ A $end +$var wire 1 >@ AandB $end +$var wire 1 ?@ AddSubSLTSum $end +$var wire 1 @@ AxorB $end +$var wire 1 A@ B $end +$var wire 1 B@ BornB $end +$var wire 1 C@ CINandAxorB $end +$var wire 3 D@ Command [2:0] $end +$var wire 1 E@ carryin $end +$var wire 1 F@ carryout $end +$var wire 1 G@ nB $end +$var wire 1 H@ nCmd2 $end +$var wire 1 I@ subtract $end +$scope module mux0 $end +$var wire 1 J@ S $end +$var wire 1 A@ in0 $end +$var wire 1 G@ in1 $end +$var wire 1 K@ nS $end +$var wire 1 L@ out0 $end +$var wire 1 M@ out1 $end +$var wire 1 B@ outfinal $end +$upscope $end +$upscope $end +$scope module setSLTres2 $end +$var wire 1 !; S $end +$var wire 1 N@ in0 $end +$var wire 1 O@ in1 $end +$var wire 1 P@ nS $end +$var wire 1 Q@ out0 $end +$var wire 1 R@ out1 $end +$var wire 1 S@ outfinal $end +$upscope $end +$scope module setSLTres3 $end +$var wire 1 !; S $end +$var wire 1 T@ in0 $end +$var wire 1 U@ in1 $end +$var wire 1 V@ nS $end +$var wire 1 W@ out0 $end +$var wire 1 X@ out1 $end +$var wire 1 Y@ outfinal $end +$upscope $end +$upscope $end +$scope begin sltbits[18] $end +$scope module attempt $end +$var wire 1 Z@ A $end +$var wire 1 [@ AandB $end +$var wire 1 \@ AddSubSLTSum $end +$var wire 1 ]@ AxorB $end +$var wire 1 ^@ B $end +$var wire 1 _@ BornB $end +$var wire 1 `@ CINandAxorB $end +$var wire 3 a@ Command [2:0] $end +$var wire 1 b@ carryin $end +$var wire 1 c@ carryout $end +$var wire 1 d@ nB $end +$var wire 1 e@ nCmd2 $end +$var wire 1 f@ subtract $end +$scope module mux0 $end +$var wire 1 g@ S $end +$var wire 1 ^@ in0 $end +$var wire 1 d@ in1 $end +$var wire 1 h@ nS $end +$var wire 1 i@ out0 $end +$var wire 1 j@ out1 $end +$var wire 1 _@ outfinal $end +$upscope $end +$upscope $end +$scope module setSLTres2 $end +$var wire 1 !; S $end +$var wire 1 k@ in0 $end +$var wire 1 l@ in1 $end +$var wire 1 m@ nS $end +$var wire 1 n@ out0 $end +$var wire 1 o@ out1 $end +$var wire 1 p@ outfinal $end +$upscope $end +$scope module setSLTres3 $end +$var wire 1 !; S $end +$var wire 1 q@ in0 $end +$var wire 1 r@ in1 $end +$var wire 1 s@ nS $end +$var wire 1 t@ out0 $end +$var wire 1 u@ out1 $end +$var wire 1 v@ outfinal $end +$upscope $end +$upscope $end +$scope begin sltbits[19] $end +$scope module attempt $end +$var wire 1 w@ A $end +$var wire 1 x@ AandB $end +$var wire 1 y@ AddSubSLTSum $end +$var wire 1 z@ AxorB $end +$var wire 1 {@ B $end +$var wire 1 |@ BornB $end +$var wire 1 }@ CINandAxorB $end +$var wire 3 ~@ Command [2:0] $end +$var wire 1 !A carryin $end +$var wire 1 "A carryout $end +$var wire 1 #A nB $end +$var wire 1 $A nCmd2 $end +$var wire 1 %A subtract $end +$scope module mux0 $end +$var wire 1 &A S $end +$var wire 1 {@ in0 $end +$var wire 1 #A in1 $end +$var wire 1 'A nS $end +$var wire 1 (A out0 $end +$var wire 1 )A out1 $end +$var wire 1 |@ outfinal $end +$upscope $end +$upscope $end +$scope module setSLTres2 $end +$var wire 1 !; S $end +$var wire 1 *A in0 $end +$var wire 1 +A in1 $end +$var wire 1 ,A nS $end +$var wire 1 -A out0 $end +$var wire 1 .A out1 $end +$var wire 1 /A outfinal $end +$upscope $end +$scope module setSLTres3 $end +$var wire 1 !; S $end +$var wire 1 0A in0 $end +$var wire 1 1A in1 $end +$var wire 1 2A nS $end +$var wire 1 3A out0 $end +$var wire 1 4A out1 $end +$var wire 1 5A outfinal $end +$upscope $end +$upscope $end +$scope begin sltbits[20] $end +$scope module attempt $end +$var wire 1 6A A $end +$var wire 1 7A AandB $end +$var wire 1 8A AddSubSLTSum $end +$var wire 1 9A AxorB $end +$var wire 1 :A B $end +$var wire 1 ;A BornB $end +$var wire 1 A carryin $end +$var wire 1 ?A carryout $end +$var wire 1 @A nB $end +$var wire 1 AA nCmd2 $end +$var wire 1 BA subtract $end +$scope module mux0 $end +$var wire 1 CA S $end +$var wire 1 :A in0 $end +$var wire 1 @A in1 $end +$var wire 1 DA nS $end +$var wire 1 EA out0 $end +$var wire 1 FA out1 $end +$var wire 1 ;A outfinal $end +$upscope $end +$upscope $end +$scope module setSLTres2 $end +$var wire 1 !; S $end +$var wire 1 GA in0 $end +$var wire 1 HA in1 $end +$var wire 1 IA nS $end +$var wire 1 JA out0 $end +$var wire 1 KA out1 $end +$var wire 1 LA outfinal $end +$upscope $end +$scope module setSLTres3 $end +$var wire 1 !; S $end +$var wire 1 MA in0 $end +$var wire 1 NA in1 $end +$var wire 1 OA nS $end +$var wire 1 PA out0 $end +$var wire 1 QA out1 $end +$var wire 1 RA outfinal $end +$upscope $end +$upscope $end +$scope begin sltbits[21] $end +$scope module attempt $end +$var wire 1 SA A $end +$var wire 1 TA AandB $end +$var wire 1 UA AddSubSLTSum $end +$var wire 1 VA AxorB $end +$var wire 1 WA B $end +$var wire 1 XA BornB $end +$var wire 1 YA CINandAxorB $end +$var wire 3 ZA Command [2:0] $end +$var wire 1 [A carryin $end +$var wire 1 \A carryout $end +$var wire 1 ]A nB $end +$var wire 1 ^A nCmd2 $end +$var wire 1 _A subtract $end +$scope module mux0 $end +$var wire 1 `A S $end +$var wire 1 WA in0 $end +$var wire 1 ]A in1 $end +$var wire 1 aA nS $end +$var wire 1 bA out0 $end +$var wire 1 cA out1 $end +$var wire 1 XA outfinal $end +$upscope $end +$upscope $end +$scope module setSLTres2 $end +$var wire 1 !; S $end +$var wire 1 dA in0 $end +$var wire 1 eA in1 $end +$var wire 1 fA nS $end +$var wire 1 gA out0 $end +$var wire 1 hA out1 $end +$var wire 1 iA outfinal $end +$upscope $end +$scope module setSLTres3 $end +$var wire 1 !; S $end +$var wire 1 jA in0 $end +$var wire 1 kA in1 $end +$var wire 1 lA nS $end +$var wire 1 mA out0 $end +$var wire 1 nA out1 $end +$var wire 1 oA outfinal $end +$upscope $end +$upscope $end +$scope begin sltbits[22] $end +$scope module attempt $end +$var wire 1 pA A $end +$var wire 1 qA AandB $end +$var wire 1 rA AddSubSLTSum $end +$var wire 1 sA AxorB $end +$var wire 1 tA B $end +$var wire 1 uA BornB $end +$var wire 1 vA CINandAxorB $end +$var wire 3 wA Command [2:0] $end +$var wire 1 xA carryin $end +$var wire 1 yA carryout $end +$var wire 1 zA nB $end +$var wire 1 {A nCmd2 $end +$var wire 1 |A subtract $end +$scope module mux0 $end +$var wire 1 }A S $end +$var wire 1 tA in0 $end +$var wire 1 zA in1 $end +$var wire 1 ~A nS $end +$var wire 1 !B out0 $end +$var wire 1 "B out1 $end +$var wire 1 uA outfinal $end +$upscope $end +$upscope $end +$scope module setSLTres2 $end +$var wire 1 !; S $end +$var wire 1 #B in0 $end +$var wire 1 $B in1 $end +$var wire 1 %B nS $end +$var wire 1 &B out0 $end +$var wire 1 'B out1 $end +$var wire 1 (B outfinal $end +$upscope $end +$scope module setSLTres3 $end +$var wire 1 !; S $end +$var wire 1 )B in0 $end +$var wire 1 *B in1 $end +$var wire 1 +B nS $end +$var wire 1 ,B out0 $end +$var wire 1 -B out1 $end +$var wire 1 .B outfinal $end +$upscope $end +$upscope $end +$scope begin sltbits[23] $end +$scope module attempt $end +$var wire 1 /B A $end +$var wire 1 0B AandB $end +$var wire 1 1B AddSubSLTSum $end +$var wire 1 2B AxorB $end +$var wire 1 3B B $end +$var wire 1 4B BornB $end +$var wire 1 5B CINandAxorB $end +$var wire 3 6B Command [2:0] $end +$var wire 1 7B carryin $end +$var wire 1 8B carryout $end +$var wire 1 9B nB $end +$var wire 1 :B nCmd2 $end +$var wire 1 ;B subtract $end +$scope module mux0 $end +$var wire 1 B out0 $end +$var wire 1 ?B out1 $end +$var wire 1 4B outfinal $end +$upscope $end +$upscope $end +$scope module setSLTres2 $end +$var wire 1 !; S $end +$var wire 1 @B in0 $end +$var wire 1 AB in1 $end +$var wire 1 BB nS $end +$var wire 1 CB out0 $end +$var wire 1 DB out1 $end +$var wire 1 EB outfinal $end +$upscope $end +$scope module setSLTres3 $end +$var wire 1 !; S $end +$var wire 1 FB in0 $end +$var wire 1 GB in1 $end +$var wire 1 HB nS $end +$var wire 1 IB out0 $end +$var wire 1 JB out1 $end +$var wire 1 KB outfinal $end +$upscope $end +$upscope $end +$scope begin sltbits[24] $end +$scope module attempt $end +$var wire 1 LB A $end +$var wire 1 MB AandB $end +$var wire 1 NB AddSubSLTSum $end +$var wire 1 OB AxorB $end +$var wire 1 PB B $end +$var wire 1 QB BornB $end +$var wire 1 RB CINandAxorB $end +$var wire 3 SB Command [2:0] $end +$var wire 1 TB carryin $end +$var wire 1 UB carryout $end +$var wire 1 VB nB $end +$var wire 1 WB nCmd2 $end +$var wire 1 XB subtract $end +$scope module mux0 $end +$var wire 1 YB S $end +$var wire 1 PB in0 $end +$var wire 1 VB in1 $end +$var wire 1 ZB nS $end +$var wire 1 [B out0 $end +$var wire 1 \B out1 $end +$var wire 1 QB outfinal $end +$upscope $end +$upscope $end +$scope module setSLTres2 $end +$var wire 1 !; S $end +$var wire 1 ]B in0 $end +$var wire 1 ^B in1 $end +$var wire 1 _B nS $end +$var wire 1 `B out0 $end +$var wire 1 aB out1 $end +$var wire 1 bB outfinal $end +$upscope $end +$scope module setSLTres3 $end +$var wire 1 !; S $end +$var wire 1 cB in0 $end +$var wire 1 dB in1 $end +$var wire 1 eB nS $end +$var wire 1 fB out0 $end +$var wire 1 gB out1 $end +$var wire 1 hB outfinal $end +$upscope $end +$upscope $end +$scope begin sltbits[25] $end +$scope module attempt $end +$var wire 1 iB A $end +$var wire 1 jB AandB $end +$var wire 1 kB AddSubSLTSum $end +$var wire 1 lB AxorB $end +$var wire 1 mB B $end +$var wire 1 nB BornB $end +$var wire 1 oB CINandAxorB $end +$var wire 3 pB Command [2:0] $end +$var wire 1 qB carryin $end +$var wire 1 rB carryout $end +$var wire 1 sB nB $end +$var wire 1 tB nCmd2 $end +$var wire 1 uB subtract $end +$scope module mux0 $end +$var wire 1 vB S $end +$var wire 1 mB in0 $end +$var wire 1 sB in1 $end +$var wire 1 wB nS $end +$var wire 1 xB out0 $end +$var wire 1 yB out1 $end +$var wire 1 nB outfinal $end +$upscope $end +$upscope $end +$scope module setSLTres2 $end +$var wire 1 !; S $end +$var wire 1 zB in0 $end +$var wire 1 {B in1 $end +$var wire 1 |B nS $end +$var wire 1 }B out0 $end +$var wire 1 ~B out1 $end +$var wire 1 !C outfinal $end +$upscope $end +$scope module setSLTres3 $end +$var wire 1 !; S $end +$var wire 1 "C in0 $end +$var wire 1 #C in1 $end +$var wire 1 $C nS $end +$var wire 1 %C out0 $end +$var wire 1 &C out1 $end +$var wire 1 'C outfinal $end +$upscope $end +$upscope $end +$scope begin sltbits[26] $end +$scope module attempt $end +$var wire 1 (C A $end +$var wire 1 )C AandB $end +$var wire 1 *C AddSubSLTSum $end +$var wire 1 +C AxorB $end +$var wire 1 ,C B $end +$var wire 1 -C BornB $end +$var wire 1 .C CINandAxorB $end +$var wire 3 /C Command [2:0] $end +$var wire 1 0C carryin $end +$var wire 1 1C carryout $end +$var wire 1 2C nB $end +$var wire 1 3C nCmd2 $end +$var wire 1 4C subtract $end +$scope module mux0 $end +$var wire 1 5C S $end +$var wire 1 ,C in0 $end +$var wire 1 2C in1 $end +$var wire 1 6C nS $end +$var wire 1 7C out0 $end +$var wire 1 8C out1 $end +$var wire 1 -C outfinal $end +$upscope $end +$upscope $end +$scope module setSLTres2 $end +$var wire 1 !; S $end +$var wire 1 9C in0 $end +$var wire 1 :C in1 $end +$var wire 1 ;C nS $end +$var wire 1 C outfinal $end +$upscope $end +$scope module setSLTres3 $end +$var wire 1 !; S $end +$var wire 1 ?C in0 $end +$var wire 1 @C in1 $end +$var wire 1 AC nS $end +$var wire 1 BC out0 $end +$var wire 1 CC out1 $end +$var wire 1 DC outfinal $end +$upscope $end +$upscope $end +$scope begin sltbits[27] $end +$scope module attempt $end +$var wire 1 EC A $end +$var wire 1 FC AandB $end +$var wire 1 GC AddSubSLTSum $end +$var wire 1 HC AxorB $end +$var wire 1 IC B $end +$var wire 1 JC BornB $end +$var wire 1 KC CINandAxorB $end +$var wire 3 LC Command [2:0] $end +$var wire 1 MC carryin $end +$var wire 1 NC carryout $end +$var wire 1 OC nB $end +$var wire 1 PC nCmd2 $end +$var wire 1 QC subtract $end +$scope module mux0 $end +$var wire 1 RC S $end +$var wire 1 IC in0 $end +$var wire 1 OC in1 $end +$var wire 1 SC nS $end +$var wire 1 TC out0 $end +$var wire 1 UC out1 $end +$var wire 1 JC outfinal $end +$upscope $end +$upscope $end +$scope module setSLTres2 $end +$var wire 1 !; S $end +$var wire 1 VC in0 $end +$var wire 1 WC in1 $end +$var wire 1 XC nS $end +$var wire 1 YC out0 $end +$var wire 1 ZC out1 $end +$var wire 1 [C outfinal $end +$upscope $end +$scope module setSLTres3 $end +$var wire 1 !; S $end +$var wire 1 \C in0 $end +$var wire 1 ]C in1 $end +$var wire 1 ^C nS $end +$var wire 1 _C out0 $end +$var wire 1 `C out1 $end +$var wire 1 aC outfinal $end +$upscope $end +$upscope $end +$scope begin sltbits[28] $end +$scope module attempt $end +$var wire 1 bC A $end +$var wire 1 cC AandB $end +$var wire 1 dC AddSubSLTSum $end +$var wire 1 eC AxorB $end +$var wire 1 fC B $end +$var wire 1 gC BornB $end +$var wire 1 hC CINandAxorB $end +$var wire 3 iC Command [2:0] $end +$var wire 1 jC carryin $end +$var wire 1 kC carryout $end +$var wire 1 lC nB $end +$var wire 1 mC nCmd2 $end +$var wire 1 nC subtract $end +$scope module mux0 $end +$var wire 1 oC S $end +$var wire 1 fC in0 $end +$var wire 1 lC in1 $end +$var wire 1 pC nS $end +$var wire 1 qC out0 $end +$var wire 1 rC out1 $end +$var wire 1 gC outfinal $end +$upscope $end +$upscope $end +$scope module setSLTres2 $end +$var wire 1 !; S $end +$var wire 1 sC in0 $end +$var wire 1 tC in1 $end +$var wire 1 uC nS $end +$var wire 1 vC out0 $end +$var wire 1 wC out1 $end +$var wire 1 xC outfinal $end +$upscope $end +$scope module setSLTres3 $end +$var wire 1 !; S $end +$var wire 1 yC in0 $end +$var wire 1 zC in1 $end +$var wire 1 {C nS $end +$var wire 1 |C out0 $end +$var wire 1 }C out1 $end +$var wire 1 ~C outfinal $end +$upscope $end +$upscope $end +$scope begin sltbits[29] $end +$scope module attempt $end +$var wire 1 !D A $end +$var wire 1 "D AandB $end +$var wire 1 #D AddSubSLTSum $end +$var wire 1 $D AxorB $end +$var wire 1 %D B $end +$var wire 1 &D BornB $end +$var wire 1 'D CINandAxorB $end +$var wire 3 (D Command [2:0] $end +$var wire 1 )D carryin $end +$var wire 1 *D carryout $end +$var wire 1 +D nB $end +$var wire 1 ,D nCmd2 $end +$var wire 1 -D subtract $end +$scope module mux0 $end +$var wire 1 .D S $end +$var wire 1 %D in0 $end +$var wire 1 +D in1 $end +$var wire 1 /D nS $end +$var wire 1 0D out0 $end +$var wire 1 1D out1 $end +$var wire 1 &D outfinal $end +$upscope $end +$upscope $end +$scope module setSLTres2 $end +$var wire 1 !; S $end +$var wire 1 2D in0 $end +$var wire 1 3D in1 $end +$var wire 1 4D nS $end +$var wire 1 5D out0 $end +$var wire 1 6D out1 $end +$var wire 1 7D outfinal $end +$upscope $end +$scope module setSLTres3 $end +$var wire 1 !; S $end +$var wire 1 8D in0 $end +$var wire 1 9D in1 $end +$var wire 1 :D nS $end +$var wire 1 ;D out0 $end +$var wire 1 D A $end +$var wire 1 ?D AandB $end +$var wire 1 @D AddSubSLTSum $end +$var wire 1 AD AxorB $end +$var wire 1 BD B $end +$var wire 1 CD BornB $end +$var wire 1 DD CINandAxorB $end +$var wire 3 ED Command [2:0] $end +$var wire 1 FD carryin $end +$var wire 1 GD carryout $end +$var wire 1 HD nB $end +$var wire 1 ID nCmd2 $end +$var wire 1 JD subtract $end +$scope module mux0 $end +$var wire 1 KD S $end +$var wire 1 BD in0 $end +$var wire 1 HD in1 $end +$var wire 1 LD nS $end +$var wire 1 MD out0 $end +$var wire 1 ND out1 $end +$var wire 1 CD outfinal $end +$upscope $end +$upscope $end +$scope module setSLTres2 $end +$var wire 1 !; S $end +$var wire 1 OD in0 $end +$var wire 1 PD in1 $end +$var wire 1 QD nS $end +$var wire 1 RD out0 $end +$var wire 1 SD out1 $end +$var wire 1 TD outfinal $end +$upscope $end +$scope module setSLTres3 $end +$var wire 1 !; S $end +$var wire 1 UD in0 $end +$var wire 1 VD in1 $end +$var wire 1 WD nS $end +$var wire 1 XD out0 $end +$var wire 1 YD out1 $end +$var wire 1 ZD outfinal $end +$upscope $end +$upscope $end +$scope begin sltbits[31] $end +$scope module attempt $end +$var wire 1 [D A $end +$var wire 1 \D AandB $end +$var wire 1 ]D AddSubSLTSum $end +$var wire 1 ^D AxorB $end +$var wire 1 _D B $end +$var wire 1 `D BornB $end +$var wire 1 aD CINandAxorB $end +$var wire 3 bD Command [2:0] $end +$var wire 1 cD carryin $end +$var wire 1 dD carryout $end +$var wire 1 eD nB $end +$var wire 1 fD nCmd2 $end +$var wire 1 gD subtract $end +$scope module mux0 $end +$var wire 1 hD S $end +$var wire 1 _D in0 $end +$var wire 1 eD in1 $end +$var wire 1 iD nS $end +$var wire 1 jD out0 $end +$var wire 1 kD out1 $end +$var wire 1 `D outfinal $end +$upscope $end +$upscope $end +$scope module setSLTres2 $end +$var wire 1 !; S $end +$var wire 1 lD in0 $end +$var wire 1 mD in1 $end +$var wire 1 nD nS $end +$var wire 1 oD out0 $end +$var wire 1 pD out1 $end +$var wire 1 qD outfinal $end +$upscope $end +$scope module setSLTres3 $end +$var wire 1 !; S $end +$var wire 1 rD in0 $end +$var wire 1 sD in1 $end +$var wire 1 tD nS $end +$var wire 1 uD out0 $end +$var wire 1 vD out1 $end +$var wire 1 wD outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope module trial $end +$var wire 32 xD A [31:0] $end +$var wire 32 yD AddSubSLTSum [31:0] $end +$var wire 32 zD B [31:0] $end +$var wire 32 {D CarryoutWire [31:0] $end +$var wire 3 |D Command [2:0] $end +$var wire 32 }D carryin [31:0] $end +$var wire 1 , carryout $end +$var wire 1 . overflow $end +$var wire 32 ~D subtract [31:0] $end +$scope module attempt2 $end +$var wire 1 !E A $end +$var wire 1 "E AandB $end +$var wire 1 #E AddSubSLTSum $end +$var wire 1 $E AxorB $end +$var wire 1 %E B $end +$var wire 1 &E BornB $end +$var wire 1 'E CINandAxorB $end +$var wire 3 (E Command [2:0] $end +$var wire 1 )E carryin $end +$var wire 1 *E carryout $end +$var wire 1 +E nB $end +$var wire 1 ,E nCmd2 $end +$var wire 1 -E subtract $end +$scope module mux0 $end +$var wire 1 .E S $end +$var wire 1 %E in0 $end +$var wire 1 +E in1 $end +$var wire 1 /E nS $end +$var wire 1 0E out0 $end +$var wire 1 1E out1 $end +$var wire 1 &E outfinal $end +$upscope $end +$upscope $end +$scope begin addbits[1] $end +$scope module attempt $end +$var wire 1 2E A $end +$var wire 1 3E AandB $end +$var wire 1 4E AddSubSLTSum $end +$var wire 1 5E AxorB $end +$var wire 1 6E B $end +$var wire 1 7E BornB $end +$var wire 1 8E CINandAxorB $end +$var wire 3 9E Command [2:0] $end +$var wire 1 :E carryin $end +$var wire 1 ;E carryout $end +$var wire 1 E subtract $end +$scope module mux0 $end +$var wire 1 ?E S $end +$var wire 1 6E in0 $end +$var wire 1 F B $end +$var wire 1 ?F BornB $end +$var wire 1 @F CINandAxorB $end +$var wire 3 AF Command [2:0] $end +$var wire 1 BF carryin $end +$var wire 1 CF carryout $end +$var wire 1 DF nB $end +$var wire 1 EF nCmd2 $end +$var wire 1 FF subtract $end +$scope module mux0 $end +$var wire 1 GF S $end +$var wire 1 >F in0 $end +$var wire 1 DF in1 $end +$var wire 1 HF nS $end +$var wire 1 IF out0 $end +$var wire 1 JF out1 $end +$var wire 1 ?F outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin addbits[8] $end +$scope module attempt $end +$var wire 1 KF A $end +$var wire 1 LF AandB $end +$var wire 1 MF AddSubSLTSum $end +$var wire 1 NF AxorB $end +$var wire 1 OF B $end +$var wire 1 PF BornB $end +$var wire 1 QF CINandAxorB $end +$var wire 3 RF Command [2:0] $end +$var wire 1 SF carryin $end +$var wire 1 TF carryout $end +$var wire 1 UF nB $end +$var wire 1 VF nCmd2 $end +$var wire 1 WF subtract $end +$scope module mux0 $end +$var wire 1 XF S $end +$var wire 1 OF in0 $end +$var wire 1 UF in1 $end +$var wire 1 YF nS $end +$var wire 1 ZF out0 $end +$var wire 1 [F out1 $end +$var wire 1 PF outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin addbits[9] $end +$scope module attempt $end +$var wire 1 \F A $end +$var wire 1 ]F AandB $end +$var wire 1 ^F AddSubSLTSum $end +$var wire 1 _F AxorB $end +$var wire 1 `F B $end +$var wire 1 aF BornB $end +$var wire 1 bF CINandAxorB $end +$var wire 3 cF Command [2:0] $end +$var wire 1 dF carryin $end +$var wire 1 eF carryout $end +$var wire 1 fF nB $end +$var wire 1 gF nCmd2 $end +$var wire 1 hF subtract $end +$scope module mux0 $end +$var wire 1 iF S $end +$var wire 1 `F in0 $end +$var wire 1 fF in1 $end +$var wire 1 jF nS $end +$var wire 1 kF out0 $end +$var wire 1 lF out1 $end +$var wire 1 aF outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin addbits[10] $end +$scope module attempt $end +$var wire 1 mF A $end +$var wire 1 nF AandB $end +$var wire 1 oF AddSubSLTSum $end +$var wire 1 pF AxorB $end +$var wire 1 qF B $end +$var wire 1 rF BornB $end +$var wire 1 sF CINandAxorB $end +$var wire 3 tF Command [2:0] $end +$var wire 1 uF carryin $end +$var wire 1 vF carryout $end +$var wire 1 wF nB $end +$var wire 1 xF nCmd2 $end +$var wire 1 yF subtract $end +$scope module mux0 $end +$var wire 1 zF S $end +$var wire 1 qF in0 $end +$var wire 1 wF in1 $end +$var wire 1 {F nS $end +$var wire 1 |F out0 $end +$var wire 1 }F out1 $end +$var wire 1 rF outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin addbits[11] $end +$scope module attempt $end +$var wire 1 ~F A $end +$var wire 1 !G AandB $end +$var wire 1 "G AddSubSLTSum $end +$var wire 1 #G AxorB $end +$var wire 1 $G B $end +$var wire 1 %G BornB $end +$var wire 1 &G CINandAxorB $end +$var wire 3 'G Command [2:0] $end +$var wire 1 (G carryin $end +$var wire 1 )G carryout $end +$var wire 1 *G nB $end +$var wire 1 +G nCmd2 $end +$var wire 1 ,G subtract $end +$scope module mux0 $end +$var wire 1 -G S $end +$var wire 1 $G in0 $end +$var wire 1 *G in1 $end +$var wire 1 .G nS $end +$var wire 1 /G out0 $end +$var wire 1 0G out1 $end +$var wire 1 %G outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin addbits[12] $end +$scope module attempt $end +$var wire 1 1G A $end +$var wire 1 2G AandB $end +$var wire 1 3G AddSubSLTSum $end +$var wire 1 4G AxorB $end +$var wire 1 5G B $end +$var wire 1 6G BornB $end +$var wire 1 7G CINandAxorB $end +$var wire 3 8G Command [2:0] $end +$var wire 1 9G carryin $end +$var wire 1 :G carryout $end +$var wire 1 ;G nB $end +$var wire 1 G S $end +$var wire 1 5G in0 $end +$var wire 1 ;G in1 $end +$var wire 1 ?G nS $end +$var wire 1 @G out0 $end +$var wire 1 AG out1 $end +$var wire 1 6G outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin addbits[13] $end +$scope module attempt $end +$var wire 1 BG A $end +$var wire 1 CG AandB $end +$var wire 1 DG AddSubSLTSum $end +$var wire 1 EG AxorB $end +$var wire 1 FG B $end +$var wire 1 GG BornB $end +$var wire 1 HG CINandAxorB $end +$var wire 3 IG Command [2:0] $end +$var wire 1 JG carryin $end +$var wire 1 KG carryout $end +$var wire 1 LG nB $end +$var wire 1 MG nCmd2 $end +$var wire 1 NG subtract $end +$scope module mux0 $end +$var wire 1 OG S $end +$var wire 1 FG in0 $end +$var wire 1 LG in1 $end +$var wire 1 PG nS $end +$var wire 1 QG out0 $end +$var wire 1 RG out1 $end +$var wire 1 GG outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin addbits[14] $end +$scope module attempt $end +$var wire 1 SG A $end +$var wire 1 TG AandB $end +$var wire 1 UG AddSubSLTSum $end +$var wire 1 VG AxorB $end +$var wire 1 WG B $end +$var wire 1 XG BornB $end +$var wire 1 YG CINandAxorB $end +$var wire 3 ZG Command [2:0] $end +$var wire 1 [G carryin $end +$var wire 1 \G carryout $end +$var wire 1 ]G nB $end +$var wire 1 ^G nCmd2 $end +$var wire 1 _G subtract $end +$scope module mux0 $end +$var wire 1 `G S $end +$var wire 1 WG in0 $end +$var wire 1 ]G in1 $end +$var wire 1 aG nS $end +$var wire 1 bG out0 $end +$var wire 1 cG out1 $end +$var wire 1 XG outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin addbits[15] $end +$scope module attempt $end +$var wire 1 dG A $end +$var wire 1 eG AandB $end +$var wire 1 fG AddSubSLTSum $end +$var wire 1 gG AxorB $end +$var wire 1 hG B $end +$var wire 1 iG BornB $end +$var wire 1 jG CINandAxorB $end +$var wire 3 kG Command [2:0] $end +$var wire 1 lG carryin $end +$var wire 1 mG carryout $end +$var wire 1 nG nB $end +$var wire 1 oG nCmd2 $end +$var wire 1 pG subtract $end +$scope module mux0 $end +$var wire 1 qG S $end +$var wire 1 hG in0 $end +$var wire 1 nG in1 $end +$var wire 1 rG nS $end +$var wire 1 sG out0 $end +$var wire 1 tG out1 $end +$var wire 1 iG outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin addbits[16] $end +$scope module attempt $end +$var wire 1 uG A $end +$var wire 1 vG AandB $end +$var wire 1 wG AddSubSLTSum $end +$var wire 1 xG AxorB $end +$var wire 1 yG B $end +$var wire 1 zG BornB $end +$var wire 1 {G CINandAxorB $end +$var wire 3 |G Command [2:0] $end +$var wire 1 }G carryin $end +$var wire 1 ~G carryout $end +$var wire 1 !H nB $end +$var wire 1 "H nCmd2 $end +$var wire 1 #H subtract $end +$scope module mux0 $end +$var wire 1 $H S $end +$var wire 1 yG in0 $end +$var wire 1 !H in1 $end +$var wire 1 %H nS $end +$var wire 1 &H out0 $end +$var wire 1 'H out1 $end +$var wire 1 zG outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin addbits[17] $end +$scope module attempt $end +$var wire 1 (H A $end +$var wire 1 )H AandB $end +$var wire 1 *H AddSubSLTSum $end +$var wire 1 +H AxorB $end +$var wire 1 ,H B $end +$var wire 1 -H BornB $end +$var wire 1 .H CINandAxorB $end +$var wire 3 /H Command [2:0] $end +$var wire 1 0H carryin $end +$var wire 1 1H carryout $end +$var wire 1 2H nB $end +$var wire 1 3H nCmd2 $end +$var wire 1 4H subtract $end +$scope module mux0 $end +$var wire 1 5H S $end +$var wire 1 ,H in0 $end +$var wire 1 2H in1 $end +$var wire 1 6H nS $end +$var wire 1 7H out0 $end +$var wire 1 8H out1 $end +$var wire 1 -H outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin addbits[18] $end +$scope module attempt $end +$var wire 1 9H A $end +$var wire 1 :H AandB $end +$var wire 1 ;H AddSubSLTSum $end +$var wire 1 H BornB $end +$var wire 1 ?H CINandAxorB $end +$var wire 3 @H Command [2:0] $end +$var wire 1 AH carryin $end +$var wire 1 BH carryout $end +$var wire 1 CH nB $end +$var wire 1 DH nCmd2 $end +$var wire 1 EH subtract $end +$scope module mux0 $end +$var wire 1 FH S $end +$var wire 1 =H in0 $end +$var wire 1 CH in1 $end +$var wire 1 GH nS $end +$var wire 1 HH out0 $end +$var wire 1 IH out1 $end +$var wire 1 >H outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin addbits[19] $end +$scope module attempt $end +$var wire 1 JH A $end +$var wire 1 KH AandB $end +$var wire 1 LH AddSubSLTSum $end +$var wire 1 MH AxorB $end +$var wire 1 NH B $end +$var wire 1 OH BornB $end +$var wire 1 PH CINandAxorB $end +$var wire 3 QH Command [2:0] $end +$var wire 1 RH carryin $end +$var wire 1 SH carryout $end +$var wire 1 TH nB $end +$var wire 1 UH nCmd2 $end +$var wire 1 VH subtract $end +$scope module mux0 $end +$var wire 1 WH S $end +$var wire 1 NH in0 $end +$var wire 1 TH in1 $end +$var wire 1 XH nS $end +$var wire 1 YH out0 $end +$var wire 1 ZH out1 $end +$var wire 1 OH outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin addbits[20] $end +$scope module attempt $end +$var wire 1 [H A $end +$var wire 1 \H AandB $end +$var wire 1 ]H AddSubSLTSum $end +$var wire 1 ^H AxorB $end +$var wire 1 _H B $end +$var wire 1 `H BornB $end +$var wire 1 aH CINandAxorB $end +$var wire 3 bH Command [2:0] $end +$var wire 1 cH carryin $end +$var wire 1 dH carryout $end +$var wire 1 eH nB $end +$var wire 1 fH nCmd2 $end +$var wire 1 gH subtract $end +$scope module mux0 $end +$var wire 1 hH S $end +$var wire 1 _H in0 $end +$var wire 1 eH in1 $end +$var wire 1 iH nS $end +$var wire 1 jH out0 $end +$var wire 1 kH out1 $end +$var wire 1 `H outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin addbits[21] $end +$scope module attempt $end +$var wire 1 lH A $end +$var wire 1 mH AandB $end +$var wire 1 nH AddSubSLTSum $end +$var wire 1 oH AxorB $end +$var wire 1 pH B $end +$var wire 1 qH BornB $end +$var wire 1 rH CINandAxorB $end +$var wire 3 sH Command [2:0] $end +$var wire 1 tH carryin $end +$var wire 1 uH carryout $end +$var wire 1 vH nB $end +$var wire 1 wH nCmd2 $end +$var wire 1 xH subtract $end +$scope module mux0 $end +$var wire 1 yH S $end +$var wire 1 pH in0 $end +$var wire 1 vH in1 $end +$var wire 1 zH nS $end +$var wire 1 {H out0 $end +$var wire 1 |H out1 $end +$var wire 1 qH outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin addbits[22] $end +$scope module attempt $end +$var wire 1 }H A $end +$var wire 1 ~H AandB $end +$var wire 1 !I AddSubSLTSum $end +$var wire 1 "I AxorB $end +$var wire 1 #I B $end +$var wire 1 $I BornB $end +$var wire 1 %I CINandAxorB $end +$var wire 3 &I Command [2:0] $end +$var wire 1 'I carryin $end +$var wire 1 (I carryout $end +$var wire 1 )I nB $end +$var wire 1 *I nCmd2 $end +$var wire 1 +I subtract $end +$scope module mux0 $end +$var wire 1 ,I S $end +$var wire 1 #I in0 $end +$var wire 1 )I in1 $end +$var wire 1 -I nS $end +$var wire 1 .I out0 $end +$var wire 1 /I out1 $end +$var wire 1 $I outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin addbits[23] $end +$scope module attempt $end +$var wire 1 0I A $end +$var wire 1 1I AandB $end +$var wire 1 2I AddSubSLTSum $end +$var wire 1 3I AxorB $end +$var wire 1 4I B $end +$var wire 1 5I BornB $end +$var wire 1 6I CINandAxorB $end +$var wire 3 7I Command [2:0] $end +$var wire 1 8I carryin $end +$var wire 1 9I carryout $end +$var wire 1 :I nB $end +$var wire 1 ;I nCmd2 $end +$var wire 1 I nS $end +$var wire 1 ?I out0 $end +$var wire 1 @I out1 $end +$var wire 1 5I outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin addbits[24] $end +$scope module attempt $end +$var wire 1 AI A $end +$var wire 1 BI AandB $end +$var wire 1 CI AddSubSLTSum $end +$var wire 1 DI AxorB $end +$var wire 1 EI B $end +$var wire 1 FI BornB $end +$var wire 1 GI CINandAxorB $end +$var wire 3 HI Command [2:0] $end +$var wire 1 II carryin $end +$var wire 1 JI carryout $end +$var wire 1 KI nB $end +$var wire 1 LI nCmd2 $end +$var wire 1 MI subtract $end +$scope module mux0 $end +$var wire 1 NI S $end +$var wire 1 EI in0 $end +$var wire 1 KI in1 $end +$var wire 1 OI nS $end +$var wire 1 PI out0 $end +$var wire 1 QI out1 $end +$var wire 1 FI outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin addbits[25] $end +$scope module attempt $end +$var wire 1 RI A $end +$var wire 1 SI AandB $end +$var wire 1 TI AddSubSLTSum $end +$var wire 1 UI AxorB $end +$var wire 1 VI B $end +$var wire 1 WI BornB $end +$var wire 1 XI CINandAxorB $end +$var wire 3 YI Command [2:0] $end +$var wire 1 ZI carryin $end +$var wire 1 [I carryout $end +$var wire 1 \I nB $end +$var wire 1 ]I nCmd2 $end +$var wire 1 ^I subtract $end +$scope module mux0 $end +$var wire 1 _I S $end +$var wire 1 VI in0 $end +$var wire 1 \I in1 $end +$var wire 1 `I nS $end +$var wire 1 aI out0 $end +$var wire 1 bI out1 $end +$var wire 1 WI outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin addbits[26] $end +$scope module attempt $end +$var wire 1 cI A $end +$var wire 1 dI AandB $end +$var wire 1 eI AddSubSLTSum $end +$var wire 1 fI AxorB $end +$var wire 1 gI B $end +$var wire 1 hI BornB $end +$var wire 1 iI CINandAxorB $end +$var wire 3 jI Command [2:0] $end +$var wire 1 kI carryin $end +$var wire 1 lI carryout $end +$var wire 1 mI nB $end +$var wire 1 nI nCmd2 $end +$var wire 1 oI subtract $end +$scope module mux0 $end +$var wire 1 pI S $end +$var wire 1 gI in0 $end +$var wire 1 mI in1 $end +$var wire 1 qI nS $end +$var wire 1 rI out0 $end +$var wire 1 sI out1 $end +$var wire 1 hI outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin addbits[27] $end +$scope module attempt $end +$var wire 1 tI A $end +$var wire 1 uI AandB $end +$var wire 1 vI AddSubSLTSum $end +$var wire 1 wI AxorB $end +$var wire 1 xI B $end +$var wire 1 yI BornB $end +$var wire 1 zI CINandAxorB $end +$var wire 3 {I Command [2:0] $end +$var wire 1 |I carryin $end +$var wire 1 }I carryout $end +$var wire 1 ~I nB $end +$var wire 1 !J nCmd2 $end +$var wire 1 "J subtract $end +$scope module mux0 $end +$var wire 1 #J S $end +$var wire 1 xI in0 $end +$var wire 1 ~I in1 $end +$var wire 1 $J nS $end +$var wire 1 %J out0 $end +$var wire 1 &J out1 $end +$var wire 1 yI outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin addbits[28] $end +$scope module attempt $end +$var wire 1 'J A $end +$var wire 1 (J AandB $end +$var wire 1 )J AddSubSLTSum $end +$var wire 1 *J AxorB $end +$var wire 1 +J B $end +$var wire 1 ,J BornB $end +$var wire 1 -J CINandAxorB $end +$var wire 3 .J Command [2:0] $end +$var wire 1 /J carryin $end +$var wire 1 0J carryout $end +$var wire 1 1J nB $end +$var wire 1 2J nCmd2 $end +$var wire 1 3J subtract $end +$scope module mux0 $end +$var wire 1 4J S $end +$var wire 1 +J in0 $end +$var wire 1 1J in1 $end +$var wire 1 5J nS $end +$var wire 1 6J out0 $end +$var wire 1 7J out1 $end +$var wire 1 ,J outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin addbits[29] $end +$scope module attempt $end +$var wire 1 8J A $end +$var wire 1 9J AandB $end +$var wire 1 :J AddSubSLTSum $end +$var wire 1 ;J AxorB $end +$var wire 1 J CINandAxorB $end +$var wire 3 ?J Command [2:0] $end +$var wire 1 @J carryin $end +$var wire 1 AJ carryout $end +$var wire 1 BJ nB $end +$var wire 1 CJ nCmd2 $end +$var wire 1 DJ subtract $end +$scope module mux0 $end +$var wire 1 EJ S $end +$var wire 1 K Command [2:0] $end +$scope module potato $end +$var wire 1 ?K S $end +$var wire 1 :K in0 $end +$var wire 1 ;K in1 $end +$var wire 1 @K nS $end +$var wire 1 AK out0 $end +$var wire 1 BK out1 $end +$var wire 1 L out1 $end +$var wire 1 8L outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin andbits[14] $end +$scope module attempt $end +$var wire 1 ?L A $end +$var wire 1 @L AandB $end +$var wire 1 AL AnandB $end +$var wire 1 BL AndNandOut $end +$var wire 1 CL B $end +$var wire 3 DL Command [2:0] $end +$scope module potato $end +$var wire 1 EL S $end +$var wire 1 @L in0 $end +$var wire 1 AL in1 $end +$var wire 1 FL nS $end +$var wire 1 GL out0 $end +$var wire 1 HL out1 $end +$var wire 1 BL outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin andbits[15] $end +$scope module attempt $end +$var wire 1 IL A $end +$var wire 1 JL AandB $end +$var wire 1 KL AnandB $end +$var wire 1 LL AndNandOut $end +$var wire 1 ML B $end +$var wire 3 NL Command [2:0] $end +$scope module potato $end +$var wire 1 OL S $end +$var wire 1 JL in0 $end +$var wire 1 KL in1 $end +$var wire 1 PL nS $end +$var wire 1 QL out0 $end +$var wire 1 RL out1 $end +$var wire 1 LL outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin andbits[16] $end +$scope module attempt $end +$var wire 1 SL A $end +$var wire 1 TL AandB $end +$var wire 1 UL AnandB $end +$var wire 1 VL AndNandOut $end +$var wire 1 WL B $end +$var wire 3 XL Command [2:0] $end +$scope module potato $end +$var wire 1 YL S $end +$var wire 1 TL in0 $end +$var wire 1 UL in1 $end +$var wire 1 ZL nS $end +$var wire 1 [L out0 $end +$var wire 1 \L out1 $end +$var wire 1 VL outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin andbits[17] $end +$scope module attempt $end +$var wire 1 ]L A $end +$var wire 1 ^L AandB $end +$var wire 1 _L AnandB $end +$var wire 1 `L AndNandOut $end +$var wire 1 aL B $end +$var wire 3 bL Command [2:0] $end +$scope module potato $end +$var wire 1 cL S $end +$var wire 1 ^L in0 $end +$var wire 1 _L in1 $end +$var wire 1 dL nS $end +$var wire 1 eL out0 $end +$var wire 1 fL out1 $end +$var wire 1 `L outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin andbits[18] $end +$scope module attempt $end +$var wire 1 gL A $end +$var wire 1 hL AandB $end +$var wire 1 iL AnandB $end +$var wire 1 jL AndNandOut $end +$var wire 1 kL B $end +$var wire 3 lL Command [2:0] $end +$scope module potato $end +$var wire 1 mL S $end +$var wire 1 hL in0 $end +$var wire 1 iL in1 $end +$var wire 1 nL nS $end +$var wire 1 oL out0 $end +$var wire 1 pL out1 $end +$var wire 1 jL outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin andbits[19] $end +$scope module attempt $end +$var wire 1 qL A $end +$var wire 1 rL AandB $end +$var wire 1 sL AnandB $end +$var wire 1 tL AndNandOut $end +$var wire 1 uL B $end +$var wire 3 vL Command [2:0] $end +$scope module potato $end +$var wire 1 wL S $end +$var wire 1 rL in0 $end +$var wire 1 sL in1 $end +$var wire 1 xL nS $end +$var wire 1 yL out0 $end +$var wire 1 zL out1 $end +$var wire 1 tL outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin andbits[20] $end +$scope module attempt $end +$var wire 1 {L A $end +$var wire 1 |L AandB $end +$var wire 1 }L AnandB $end +$var wire 1 ~L AndNandOut $end +$var wire 1 !M B $end +$var wire 3 "M Command [2:0] $end +$scope module potato $end +$var wire 1 #M S $end +$var wire 1 |L in0 $end +$var wire 1 }L in1 $end +$var wire 1 $M nS $end +$var wire 1 %M out0 $end +$var wire 1 &M out1 $end +$var wire 1 ~L outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin andbits[21] $end +$scope module attempt $end +$var wire 1 'M A $end +$var wire 1 (M AandB $end +$var wire 1 )M AnandB $end +$var wire 1 *M AndNandOut $end +$var wire 1 +M B $end +$var wire 3 ,M Command [2:0] $end +$scope module potato $end +$var wire 1 -M S $end +$var wire 1 (M in0 $end +$var wire 1 )M in1 $end +$var wire 1 .M nS $end +$var wire 1 /M out0 $end +$var wire 1 0M out1 $end +$var wire 1 *M outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin andbits[22] $end +$scope module attempt $end +$var wire 1 1M A $end +$var wire 1 2M AandB $end +$var wire 1 3M AnandB $end +$var wire 1 4M AndNandOut $end +$var wire 1 5M B $end +$var wire 3 6M Command [2:0] $end +$scope module potato $end +$var wire 1 7M S $end +$var wire 1 2M in0 $end +$var wire 1 3M in1 $end +$var wire 1 8M nS $end +$var wire 1 9M out0 $end +$var wire 1 :M out1 $end +$var wire 1 4M outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin andbits[23] $end +$scope module attempt $end +$var wire 1 ;M A $end +$var wire 1 M AndNandOut $end +$var wire 1 ?M B $end +$var wire 3 @M Command [2:0] $end +$scope module potato $end +$var wire 1 AM S $end +$var wire 1 M outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin andbits[24] $end +$scope module attempt $end +$var wire 1 EM A $end +$var wire 1 FM AandB $end +$var wire 1 GM AnandB $end +$var wire 1 HM AndNandOut $end +$var wire 1 IM B $end +$var wire 3 JM Command [2:0] $end +$scope module potato $end +$var wire 1 KM S $end +$var wire 1 FM in0 $end +$var wire 1 GM in1 $end +$var wire 1 LM nS $end +$var wire 1 MM out0 $end +$var wire 1 NM out1 $end +$var wire 1 HM outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin andbits[25] $end +$scope module attempt $end +$var wire 1 OM A $end +$var wire 1 PM AandB $end +$var wire 1 QM AnandB $end +$var wire 1 RM AndNandOut $end +$var wire 1 SM B $end +$var wire 3 TM Command [2:0] $end +$scope module potato $end +$var wire 1 UM S $end +$var wire 1 PM in0 $end +$var wire 1 QM in1 $end +$var wire 1 VM nS $end +$var wire 1 WM out0 $end +$var wire 1 XM out1 $end +$var wire 1 RM outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin andbits[26] $end +$scope module attempt $end +$var wire 1 YM A $end +$var wire 1 ZM AandB $end +$var wire 1 [M AnandB $end +$var wire 1 \M AndNandOut $end +$var wire 1 ]M B $end +$var wire 3 ^M Command [2:0] $end +$scope module potato $end +$var wire 1 _M S $end +$var wire 1 ZM in0 $end +$var wire 1 [M in1 $end +$var wire 1 `M nS $end +$var wire 1 aM out0 $end +$var wire 1 bM out1 $end +$var wire 1 \M outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin andbits[27] $end +$scope module attempt $end +$var wire 1 cM A $end +$var wire 1 dM AandB $end +$var wire 1 eM AnandB $end +$var wire 1 fM AndNandOut $end +$var wire 1 gM B $end +$var wire 3 hM Command [2:0] $end +$scope module potato $end +$var wire 1 iM S $end +$var wire 1 dM in0 $end +$var wire 1 eM in1 $end +$var wire 1 jM nS $end +$var wire 1 kM out0 $end +$var wire 1 lM out1 $end +$var wire 1 fM outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin andbits[28] $end +$scope module attempt $end +$var wire 1 mM A $end +$var wire 1 nM AandB $end +$var wire 1 oM AnandB $end +$var wire 1 pM AndNandOut $end +$var wire 1 qM B $end +$var wire 3 rM Command [2:0] $end +$scope module potato $end +$var wire 1 sM S $end +$var wire 1 nM in0 $end +$var wire 1 oM in1 $end +$var wire 1 tM nS $end +$var wire 1 uM out0 $end +$var wire 1 vM out1 $end +$var wire 1 pM outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin andbits[29] $end +$scope module attempt $end +$var wire 1 wM A $end +$var wire 1 xM AandB $end +$var wire 1 yM AnandB $end +$var wire 1 zM AndNandOut $end +$var wire 1 {M B $end +$var wire 3 |M Command [2:0] $end +$scope module potato $end +$var wire 1 }M S $end +$var wire 1 xM in0 $end +$var wire 1 yM in1 $end +$var wire 1 ~M nS $end +$var wire 1 !N out0 $end +$var wire 1 "N out1 $end +$var wire 1 zM outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin andbits[30] $end +$scope module attempt $end +$var wire 1 #N A $end +$var wire 1 $N AandB $end +$var wire 1 %N AnandB $end +$var wire 1 &N AndNandOut $end +$var wire 1 'N B $end +$var wire 3 (N Command [2:0] $end +$scope module potato $end +$var wire 1 )N S $end +$var wire 1 $N in0 $end +$var wire 1 %N in1 $end +$var wire 1 *N nS $end +$var wire 1 +N out0 $end +$var wire 1 ,N out1 $end +$var wire 1 &N outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin andbits[31] $end +$scope module attempt $end +$var wire 1 -N A $end +$var wire 1 .N AandB $end +$var wire 1 /N AnandB $end +$var wire 1 0N AndNandOut $end +$var wire 1 1N B $end +$var wire 3 2N Command [2:0] $end +$scope module potato $end +$var wire 1 3N S $end +$var wire 1 .N in0 $end +$var wire 1 /N in1 $end +$var wire 1 4N nS $end +$var wire 1 5N out0 $end +$var wire 1 6N out1 $end +$var wire 1 0N outfinal $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope module trial2 $end +$var wire 32 7N A [31:0] $end +$var wire 32 8N B [31:0] $end +$var wire 3 9N Command [2:0] $end +$var wire 32 :N OrNorXorOut [31:0] $end +$scope module attempt2 $end +$var wire 1 ;N A $end +$var wire 1 N AorB $end +$var wire 1 ?N AxorB $end +$var wire 1 @N B $end +$var wire 3 AN Command [2:0] $end +$var wire 1 BN OrNorXorOut $end +$var wire 1 CN XorNor $end +$var wire 1 DN nXor $end +$scope module mux0 $end +$var wire 1 EN S $end +$var wire 1 ?N in0 $end +$var wire 1 =N in1 $end +$var wire 1 FN nS $end +$var wire 1 GN out0 $end +$var wire 1 HN out1 $end +$var wire 1 CN outfinal $end +$upscope $end +$scope module mux1 $end +$var wire 1 IN S $end +$var wire 1 CN in0 $end +$var wire 1 >N in1 $end +$var wire 1 JN nS $end +$var wire 1 KN out0 $end +$var wire 1 LN out1 $end +$var wire 1 BN outfinal $end +$upscope $end +$upscope $end +$scope begin orbits[1] $end +$scope module attempt $end +$var wire 1 MN A $end +$var wire 1 NN AnandB $end +$var wire 1 ON AnorB $end +$var wire 1 PN AorB $end +$var wire 1 QN AxorB $end +$var wire 1 RN B $end +$var wire 3 SN Command [2:0] $end +$var wire 1 TN OrNorXorOut $end +$var wire 1 UN XorNor $end +$var wire 1 VN nXor $end +$scope module mux0 $end +$var wire 1 WN S $end +$var wire 1 QN in0 $end +$var wire 1 ON in1 $end +$var wire 1 XN nS $end +$var wire 1 YN out0 $end +$var wire 1 ZN out1 $end +$var wire 1 UN outfinal $end +$upscope $end +$scope module mux1 $end +$var wire 1 [N S $end +$var wire 1 UN in0 $end +$var wire 1 PN in1 $end +$var wire 1 \N nS $end +$var wire 1 ]N out0 $end +$var wire 1 ^N out1 $end +$var wire 1 TN outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin orbits[2] $end +$scope module attempt $end +$var wire 1 _N A $end +$var wire 1 `N AnandB $end +$var wire 1 aN AnorB $end +$var wire 1 bN AorB $end +$var wire 1 cN AxorB $end +$var wire 1 dN B $end +$var wire 3 eN Command [2:0] $end +$var wire 1 fN OrNorXorOut $end +$var wire 1 gN XorNor $end +$var wire 1 hN nXor $end +$scope module mux0 $end +$var wire 1 iN S $end +$var wire 1 cN in0 $end +$var wire 1 aN in1 $end +$var wire 1 jN nS $end +$var wire 1 kN out0 $end +$var wire 1 lN out1 $end +$var wire 1 gN outfinal $end +$upscope $end +$scope module mux1 $end +$var wire 1 mN S $end +$var wire 1 gN in0 $end +$var wire 1 bN in1 $end +$var wire 1 nN nS $end +$var wire 1 oN out0 $end +$var wire 1 pN out1 $end +$var wire 1 fN outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin orbits[3] $end +$scope module attempt $end +$var wire 1 qN A $end +$var wire 1 rN AnandB $end +$var wire 1 sN AnorB $end +$var wire 1 tN AorB $end +$var wire 1 uN AxorB $end +$var wire 1 vN B $end +$var wire 3 wN Command [2:0] $end +$var wire 1 xN OrNorXorOut $end +$var wire 1 yN XorNor $end +$var wire 1 zN nXor $end +$scope module mux0 $end +$var wire 1 {N S $end +$var wire 1 uN in0 $end +$var wire 1 sN in1 $end +$var wire 1 |N nS $end +$var wire 1 }N out0 $end +$var wire 1 ~N out1 $end +$var wire 1 yN outfinal $end +$upscope $end +$scope module mux1 $end +$var wire 1 !O S $end +$var wire 1 yN in0 $end +$var wire 1 tN in1 $end +$var wire 1 "O nS $end +$var wire 1 #O out0 $end +$var wire 1 $O out1 $end +$var wire 1 xN outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin orbits[4] $end +$scope module attempt $end +$var wire 1 %O A $end +$var wire 1 &O AnandB $end +$var wire 1 'O AnorB $end +$var wire 1 (O AorB $end +$var wire 1 )O AxorB $end +$var wire 1 *O B $end +$var wire 3 +O Command [2:0] $end +$var wire 1 ,O OrNorXorOut $end +$var wire 1 -O XorNor $end +$var wire 1 .O nXor $end +$scope module mux0 $end +$var wire 1 /O S $end +$var wire 1 )O in0 $end +$var wire 1 'O in1 $end +$var wire 1 0O nS $end +$var wire 1 1O out0 $end +$var wire 1 2O out1 $end +$var wire 1 -O outfinal $end +$upscope $end +$scope module mux1 $end +$var wire 1 3O S $end +$var wire 1 -O in0 $end +$var wire 1 (O in1 $end +$var wire 1 4O nS $end +$var wire 1 5O out0 $end +$var wire 1 6O out1 $end +$var wire 1 ,O outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin orbits[5] $end +$scope module attempt $end +$var wire 1 7O A $end +$var wire 1 8O AnandB $end +$var wire 1 9O AnorB $end +$var wire 1 :O AorB $end +$var wire 1 ;O AxorB $end +$var wire 1 O OrNorXorOut $end +$var wire 1 ?O XorNor $end +$var wire 1 @O nXor $end +$scope module mux0 $end +$var wire 1 AO S $end +$var wire 1 ;O in0 $end +$var wire 1 9O in1 $end +$var wire 1 BO nS $end +$var wire 1 CO out0 $end +$var wire 1 DO out1 $end +$var wire 1 ?O outfinal $end +$upscope $end +$scope module mux1 $end +$var wire 1 EO S $end +$var wire 1 ?O in0 $end +$var wire 1 :O in1 $end +$var wire 1 FO nS $end +$var wire 1 GO out0 $end +$var wire 1 HO out1 $end +$var wire 1 >O outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin orbits[6] $end +$scope module attempt $end +$var wire 1 IO A $end +$var wire 1 JO AnandB $end +$var wire 1 KO AnorB $end +$var wire 1 LO AorB $end +$var wire 1 MO AxorB $end +$var wire 1 NO B $end +$var wire 3 OO Command [2:0] $end +$var wire 1 PO OrNorXorOut $end +$var wire 1 QO XorNor $end +$var wire 1 RO nXor $end +$scope module mux0 $end +$var wire 1 SO S $end +$var wire 1 MO in0 $end +$var wire 1 KO in1 $end +$var wire 1 TO nS $end +$var wire 1 UO out0 $end +$var wire 1 VO out1 $end +$var wire 1 QO outfinal $end +$upscope $end +$scope module mux1 $end +$var wire 1 WO S $end +$var wire 1 QO in0 $end +$var wire 1 LO in1 $end +$var wire 1 XO nS $end +$var wire 1 YO out0 $end +$var wire 1 ZO out1 $end +$var wire 1 PO outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin orbits[7] $end +$scope module attempt $end +$var wire 1 [O A $end +$var wire 1 \O AnandB $end +$var wire 1 ]O AnorB $end +$var wire 1 ^O AorB $end +$var wire 1 _O AxorB $end +$var wire 1 `O B $end +$var wire 3 aO Command [2:0] $end +$var wire 1 bO OrNorXorOut $end +$var wire 1 cO XorNor $end +$var wire 1 dO nXor $end +$scope module mux0 $end +$var wire 1 eO S $end +$var wire 1 _O in0 $end +$var wire 1 ]O in1 $end +$var wire 1 fO nS $end +$var wire 1 gO out0 $end +$var wire 1 hO out1 $end +$var wire 1 cO outfinal $end +$upscope $end +$scope module mux1 $end +$var wire 1 iO S $end +$var wire 1 cO in0 $end +$var wire 1 ^O in1 $end +$var wire 1 jO nS $end +$var wire 1 kO out0 $end +$var wire 1 lO out1 $end +$var wire 1 bO outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin orbits[8] $end +$scope module attempt $end +$var wire 1 mO A $end +$var wire 1 nO AnandB $end +$var wire 1 oO AnorB $end +$var wire 1 pO AorB $end +$var wire 1 qO AxorB $end +$var wire 1 rO B $end +$var wire 3 sO Command [2:0] $end +$var wire 1 tO OrNorXorOut $end +$var wire 1 uO XorNor $end +$var wire 1 vO nXor $end +$scope module mux0 $end +$var wire 1 wO S $end +$var wire 1 qO in0 $end +$var wire 1 oO in1 $end +$var wire 1 xO nS $end +$var wire 1 yO out0 $end +$var wire 1 zO out1 $end +$var wire 1 uO outfinal $end +$upscope $end +$scope module mux1 $end +$var wire 1 {O S $end +$var wire 1 uO in0 $end +$var wire 1 pO in1 $end +$var wire 1 |O nS $end +$var wire 1 }O out0 $end +$var wire 1 ~O out1 $end +$var wire 1 tO outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin orbits[9] $end +$scope module attempt $end +$var wire 1 !P A $end +$var wire 1 "P AnandB $end +$var wire 1 #P AnorB $end +$var wire 1 $P AorB $end +$var wire 1 %P AxorB $end +$var wire 1 &P B $end +$var wire 3 'P Command [2:0] $end +$var wire 1 (P OrNorXorOut $end +$var wire 1 )P XorNor $end +$var wire 1 *P nXor $end +$scope module mux0 $end +$var wire 1 +P S $end +$var wire 1 %P in0 $end +$var wire 1 #P in1 $end +$var wire 1 ,P nS $end +$var wire 1 -P out0 $end +$var wire 1 .P out1 $end +$var wire 1 )P outfinal $end +$upscope $end +$scope module mux1 $end +$var wire 1 /P S $end +$var wire 1 )P in0 $end +$var wire 1 $P in1 $end +$var wire 1 0P nS $end +$var wire 1 1P out0 $end +$var wire 1 2P out1 $end +$var wire 1 (P outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin orbits[10] $end +$scope module attempt $end +$var wire 1 3P A $end +$var wire 1 4P AnandB $end +$var wire 1 5P AnorB $end +$var wire 1 6P AorB $end +$var wire 1 7P AxorB $end +$var wire 1 8P B $end +$var wire 3 9P Command [2:0] $end +$var wire 1 :P OrNorXorOut $end +$var wire 1 ;P XorNor $end +$var wire 1

p AndNandOut $end +$var wire 1 ?p B $end +$var wire 3 @p Command [2:0] $end +$scope module potato $end +$var wire 1 Ap S $end +$var wire 1

p outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin andbits[6] $end +$scope module attempt $end +$var wire 1 Ep A $end +$var wire 1 Fp AandB $end +$var wire 1 Gp AnandB $end +$var wire 1 Hp AndNandOut $end +$var wire 1 Ip B $end +$var wire 3 Jp Command [2:0] $end +$scope module potato $end +$var wire 1 Kp S $end +$var wire 1 Fp in0 $end +$var wire 1 Gp in1 $end +$var wire 1 Lp nS $end +$var wire 1 Mp out0 $end +$var wire 1 Np out1 $end +$var wire 1 Hp outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin andbits[7] $end +$scope module attempt $end +$var wire 1 Op A $end +$var wire 1 Pp AandB $end +$var wire 1 Qp AnandB $end +$var wire 1 Rp AndNandOut $end +$var wire 1 Sp B $end +$var wire 3 Tp Command [2:0] $end +$scope module potato $end +$var wire 1 Up S $end +$var wire 1 Pp in0 $end +$var wire 1 Qp in1 $end +$var wire 1 Vp nS $end +$var wire 1 Wp out0 $end +$var wire 1 Xp out1 $end +$var wire 1 Rp outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin andbits[8] $end +$scope module attempt $end +$var wire 1 Yp A $end +$var wire 1 Zp AandB $end +$var wire 1 [p AnandB $end +$var wire 1 \p AndNandOut $end +$var wire 1 ]p B $end +$var wire 3 ^p Command [2:0] $end +$scope module potato $end +$var wire 1 _p S $end +$var wire 1 Zp in0 $end +$var wire 1 [p in1 $end +$var wire 1 `p nS $end +$var wire 1 ap out0 $end +$var wire 1 bp out1 $end +$var wire 1 \p outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin andbits[9] $end +$scope module attempt $end +$var wire 1 cp A $end +$var wire 1 dp AandB $end +$var wire 1 ep AnandB $end +$var wire 1 fp AndNandOut $end +$var wire 1 gp B $end +$var wire 3 hp Command [2:0] $end +$scope module potato $end +$var wire 1 ip S $end +$var wire 1 dp in0 $end +$var wire 1 ep in1 $end +$var wire 1 jp nS $end +$var wire 1 kp out0 $end +$var wire 1 lp out1 $end +$var wire 1 fp outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin andbits[10] $end +$scope module attempt $end +$var wire 1 mp A $end +$var wire 1 np AandB $end +$var wire 1 op AnandB $end +$var wire 1 pp AndNandOut $end +$var wire 1 qp B $end +$var wire 3 rp Command [2:0] $end +$scope module potato $end +$var wire 1 sp S $end +$var wire 1 np in0 $end +$var wire 1 op in1 $end +$var wire 1 tp nS $end +$var wire 1 up out0 $end +$var wire 1 vp out1 $end +$var wire 1 pp outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin andbits[11] $end +$scope module attempt $end +$var wire 1 wp A $end +$var wire 1 xp AandB $end +$var wire 1 yp AnandB $end +$var wire 1 zp AndNandOut $end +$var wire 1 {p B $end +$var wire 3 |p Command [2:0] $end +$scope module potato $end +$var wire 1 }p S $end +$var wire 1 xp in0 $end +$var wire 1 yp in1 $end +$var wire 1 ~p nS $end +$var wire 1 !q out0 $end +$var wire 1 "q out1 $end +$var wire 1 zp outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin andbits[12] $end +$scope module attempt $end +$var wire 1 #q A $end +$var wire 1 $q AandB $end +$var wire 1 %q AnandB $end +$var wire 1 &q AndNandOut $end +$var wire 1 'q B $end +$var wire 3 (q Command [2:0] $end +$scope module potato $end +$var wire 1 )q S $end +$var wire 1 $q in0 $end +$var wire 1 %q in1 $end +$var wire 1 *q nS $end +$var wire 1 +q out0 $end +$var wire 1 ,q out1 $end +$var wire 1 &q outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin andbits[13] $end +$scope module attempt $end +$var wire 1 -q A $end +$var wire 1 .q AandB $end +$var wire 1 /q AnandB $end +$var wire 1 0q AndNandOut $end +$var wire 1 1q B $end +$var wire 3 2q Command [2:0] $end +$scope module potato $end +$var wire 1 3q S $end +$var wire 1 .q in0 $end +$var wire 1 /q in1 $end +$var wire 1 4q nS $end +$var wire 1 5q out0 $end +$var wire 1 6q out1 $end +$var wire 1 0q outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin andbits[14] $end +$scope module attempt $end +$var wire 1 7q A $end +$var wire 1 8q AandB $end +$var wire 1 9q AnandB $end +$var wire 1 :q AndNandOut $end +$var wire 1 ;q B $end +$var wire 3 q nS $end +$var wire 1 ?q out0 $end +$var wire 1 @q out1 $end +$var wire 1 :q outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin andbits[15] $end +$scope module attempt $end +$var wire 1 Aq A $end +$var wire 1 Bq AandB $end +$var wire 1 Cq AnandB $end +$var wire 1 Dq AndNandOut $end +$var wire 1 Eq B $end +$var wire 3 Fq Command [2:0] $end +$scope module potato $end +$var wire 1 Gq S $end +$var wire 1 Bq in0 $end +$var wire 1 Cq in1 $end +$var wire 1 Hq nS $end +$var wire 1 Iq out0 $end +$var wire 1 Jq out1 $end +$var wire 1 Dq outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin andbits[16] $end +$scope module attempt $end +$var wire 1 Kq A $end +$var wire 1 Lq AandB $end +$var wire 1 Mq AnandB $end +$var wire 1 Nq AndNandOut $end +$var wire 1 Oq B $end +$var wire 3 Pq Command [2:0] $end +$scope module potato $end +$var wire 1 Qq S $end +$var wire 1 Lq in0 $end +$var wire 1 Mq in1 $end +$var wire 1 Rq nS $end +$var wire 1 Sq out0 $end +$var wire 1 Tq out1 $end +$var wire 1 Nq outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin andbits[17] $end +$scope module attempt $end +$var wire 1 Uq A $end +$var wire 1 Vq AandB $end +$var wire 1 Wq AnandB $end +$var wire 1 Xq AndNandOut $end +$var wire 1 Yq B $end +$var wire 3 Zq Command [2:0] $end +$scope module potato $end +$var wire 1 [q S $end +$var wire 1 Vq in0 $end +$var wire 1 Wq in1 $end +$var wire 1 \q nS $end +$var wire 1 ]q out0 $end +$var wire 1 ^q out1 $end +$var wire 1 Xq outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin andbits[18] $end +$scope module attempt $end +$var wire 1 _q A $end +$var wire 1 `q AandB $end +$var wire 1 aq AnandB $end +$var wire 1 bq AndNandOut $end +$var wire 1 cq B $end +$var wire 3 dq Command [2:0] $end +$scope module potato $end +$var wire 1 eq S $end +$var wire 1 `q in0 $end +$var wire 1 aq in1 $end +$var wire 1 fq nS $end +$var wire 1 gq out0 $end +$var wire 1 hq out1 $end +$var wire 1 bq outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin andbits[19] $end +$scope module attempt $end +$var wire 1 iq A $end +$var wire 1 jq AandB $end +$var wire 1 kq AnandB $end +$var wire 1 lq AndNandOut $end +$var wire 1 mq B $end +$var wire 3 nq Command [2:0] $end +$scope module potato $end +$var wire 1 oq S $end +$var wire 1 jq in0 $end +$var wire 1 kq in1 $end +$var wire 1 pq nS $end +$var wire 1 qq out0 $end +$var wire 1 rq out1 $end +$var wire 1 lq outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin andbits[20] $end +$scope module attempt $end +$var wire 1 sq A $end +$var wire 1 tq AandB $end +$var wire 1 uq AnandB $end +$var wire 1 vq AndNandOut $end +$var wire 1 wq B $end +$var wire 3 xq Command [2:0] $end +$scope module potato $end +$var wire 1 yq S $end +$var wire 1 tq in0 $end +$var wire 1 uq in1 $end +$var wire 1 zq nS $end +$var wire 1 {q out0 $end +$var wire 1 |q out1 $end +$var wire 1 vq outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin andbits[21] $end +$scope module attempt $end +$var wire 1 }q A $end +$var wire 1 ~q AandB $end +$var wire 1 !r AnandB $end +$var wire 1 "r AndNandOut $end +$var wire 1 #r B $end +$var wire 3 $r Command [2:0] $end +$scope module potato $end +$var wire 1 %r S $end +$var wire 1 ~q in0 $end +$var wire 1 !r in1 $end +$var wire 1 &r nS $end +$var wire 1 'r out0 $end +$var wire 1 (r out1 $end +$var wire 1 "r outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin andbits[22] $end +$scope module attempt $end +$var wire 1 )r A $end +$var wire 1 *r AandB $end +$var wire 1 +r AnandB $end +$var wire 1 ,r AndNandOut $end +$var wire 1 -r B $end +$var wire 3 .r Command [2:0] $end +$scope module potato $end +$var wire 1 /r S $end +$var wire 1 *r in0 $end +$var wire 1 +r in1 $end +$var wire 1 0r nS $end +$var wire 1 1r out0 $end +$var wire 1 2r out1 $end +$var wire 1 ,r outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin andbits[23] $end +$scope module attempt $end +$var wire 1 3r A $end +$var wire 1 4r AandB $end +$var wire 1 5r AnandB $end +$var wire 1 6r AndNandOut $end +$var wire 1 7r B $end +$var wire 3 8r Command [2:0] $end +$scope module potato $end +$var wire 1 9r S $end +$var wire 1 4r in0 $end +$var wire 1 5r in1 $end +$var wire 1 :r nS $end +$var wire 1 ;r out0 $end +$var wire 1 r AandB $end +$var wire 1 ?r AnandB $end +$var wire 1 @r AndNandOut $end +$var wire 1 Ar B $end +$var wire 3 Br Command [2:0] $end +$scope module potato $end +$var wire 1 Cr S $end +$var wire 1 >r in0 $end +$var wire 1 ?r in1 $end +$var wire 1 Dr nS $end +$var wire 1 Er out0 $end +$var wire 1 Fr out1 $end +$var wire 1 @r outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin andbits[25] $end +$scope module attempt $end +$var wire 1 Gr A $end +$var wire 1 Hr AandB $end +$var wire 1 Ir AnandB $end +$var wire 1 Jr AndNandOut $end +$var wire 1 Kr B $end +$var wire 3 Lr Command [2:0] $end +$scope module potato $end +$var wire 1 Mr S $end +$var wire 1 Hr in0 $end +$var wire 1 Ir in1 $end +$var wire 1 Nr nS $end +$var wire 1 Or out0 $end +$var wire 1 Pr out1 $end +$var wire 1 Jr outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin andbits[26] $end +$scope module attempt $end +$var wire 1 Qr A $end +$var wire 1 Rr AandB $end +$var wire 1 Sr AnandB $end +$var wire 1 Tr AndNandOut $end +$var wire 1 Ur B $end +$var wire 3 Vr Command [2:0] $end +$scope module potato $end +$var wire 1 Wr S $end +$var wire 1 Rr in0 $end +$var wire 1 Sr in1 $end +$var wire 1 Xr nS $end +$var wire 1 Yr out0 $end +$var wire 1 Zr out1 $end +$var wire 1 Tr outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin andbits[27] $end +$scope module attempt $end +$var wire 1 [r A $end +$var wire 1 \r AandB $end +$var wire 1 ]r AnandB $end +$var wire 1 ^r AndNandOut $end +$var wire 1 _r B $end +$var wire 3 `r Command [2:0] $end +$scope module potato $end +$var wire 1 ar S $end +$var wire 1 \r in0 $end +$var wire 1 ]r in1 $end +$var wire 1 br nS $end +$var wire 1 cr out0 $end +$var wire 1 dr out1 $end +$var wire 1 ^r outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin andbits[28] $end +$scope module attempt $end +$var wire 1 er A $end +$var wire 1 fr AandB $end +$var wire 1 gr AnandB $end +$var wire 1 hr AndNandOut $end +$var wire 1 ir B $end +$var wire 3 jr Command [2:0] $end +$scope module potato $end +$var wire 1 kr S $end +$var wire 1 fr in0 $end +$var wire 1 gr in1 $end +$var wire 1 lr nS $end +$var wire 1 mr out0 $end +$var wire 1 nr out1 $end +$var wire 1 hr outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin andbits[29] $end +$scope module attempt $end +$var wire 1 or A $end +$var wire 1 pr AandB $end +$var wire 1 qr AnandB $end +$var wire 1 rr AndNandOut $end +$var wire 1 sr B $end +$var wire 3 tr Command [2:0] $end +$scope module potato $end +$var wire 1 ur S $end +$var wire 1 pr in0 $end +$var wire 1 qr in1 $end +$var wire 1 vr nS $end +$var wire 1 wr out0 $end +$var wire 1 xr out1 $end +$var wire 1 rr outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin andbits[30] $end +$scope module attempt $end +$var wire 1 yr A $end +$var wire 1 zr AandB $end +$var wire 1 {r AnandB $end +$var wire 1 |r AndNandOut $end +$var wire 1 }r B $end +$var wire 3 ~r Command [2:0] $end +$scope module potato $end +$var wire 1 !s S $end +$var wire 1 zr in0 $end +$var wire 1 {r in1 $end +$var wire 1 "s nS $end +$var wire 1 #s out0 $end +$var wire 1 $s out1 $end +$var wire 1 |r outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin andbits[31] $end +$scope module attempt $end +$var wire 1 %s A $end +$var wire 1 &s AandB $end +$var wire 1 's AnandB $end +$var wire 1 (s AndNandOut $end +$var wire 1 )s B $end +$var wire 3 *s Command [2:0] $end +$scope module potato $end +$var wire 1 +s S $end +$var wire 1 &s in0 $end +$var wire 1 's in1 $end +$var wire 1 ,s nS $end +$var wire 1 -s out0 $end +$var wire 1 .s out1 $end +$var wire 1 (s outfinal $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope module trial2 $end +$var wire 32 /s A [31:0] $end +$var wire 32 0s B [31:0] $end +$var wire 3 1s Command [2:0] $end +$var wire 32 2s OrNorXorOut [31:0] $end +$scope module attempt2 $end +$var wire 1 3s A $end +$var wire 1 4s AnandB $end +$var wire 1 5s AnorB $end +$var wire 1 6s AorB $end +$var wire 1 7s AxorB $end +$var wire 1 8s B $end +$var wire 3 9s Command [2:0] $end +$var wire 1 :s OrNorXorOut $end +$var wire 1 ;s XorNor $end +$var wire 1 s nS $end +$var wire 1 ?s out0 $end +$var wire 1 @s out1 $end +$var wire 1 ;s outfinal $end +$upscope $end +$scope module mux1 $end +$var wire 1 As S $end +$var wire 1 ;s in0 $end +$var wire 1 6s in1 $end +$var wire 1 Bs nS $end +$var wire 1 Cs out0 $end +$var wire 1 Ds out1 $end +$var wire 1 :s outfinal $end +$upscope $end +$upscope $end +$scope begin orbits[1] $end +$scope module attempt $end +$var wire 1 Es A $end +$var wire 1 Fs AnandB $end +$var wire 1 Gs AnorB $end +$var wire 1 Hs AorB $end +$var wire 1 Is AxorB $end +$var wire 1 Js B $end +$var wire 3 Ks Command [2:0] $end +$var wire 1 Ls OrNorXorOut $end +$var wire 1 Ms XorNor $end +$var wire 1 Ns nXor $end +$scope module mux0 $end +$var wire 1 Os S $end +$var wire 1 Is in0 $end +$var wire 1 Gs in1 $end +$var wire 1 Ps nS $end +$var wire 1 Qs out0 $end +$var wire 1 Rs out1 $end +$var wire 1 Ms outfinal $end +$upscope $end +$scope module mux1 $end +$var wire 1 Ss S $end +$var wire 1 Ms in0 $end +$var wire 1 Hs in1 $end +$var wire 1 Ts nS $end +$var wire 1 Us out0 $end +$var wire 1 Vs out1 $end +$var wire 1 Ls outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin orbits[2] $end +$scope module attempt $end +$var wire 1 Ws A $end +$var wire 1 Xs AnandB $end +$var wire 1 Ys AnorB $end +$var wire 1 Zs AorB $end +$var wire 1 [s AxorB $end +$var wire 1 \s B $end +$var wire 3 ]s Command [2:0] $end +$var wire 1 ^s OrNorXorOut $end +$var wire 1 _s XorNor $end +$var wire 1 `s nXor $end +$scope module mux0 $end +$var wire 1 as S $end +$var wire 1 [s in0 $end +$var wire 1 Ys in1 $end +$var wire 1 bs nS $end +$var wire 1 cs out0 $end +$var wire 1 ds out1 $end +$var wire 1 _s outfinal $end +$upscope $end +$scope module mux1 $end +$var wire 1 es S $end +$var wire 1 _s in0 $end +$var wire 1 Zs in1 $end +$var wire 1 fs nS $end +$var wire 1 gs out0 $end +$var wire 1 hs out1 $end +$var wire 1 ^s outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin orbits[3] $end +$scope module attempt $end +$var wire 1 is A $end +$var wire 1 js AnandB $end +$var wire 1 ks AnorB $end +$var wire 1 ls AorB $end +$var wire 1 ms AxorB $end +$var wire 1 ns B $end +$var wire 3 os Command [2:0] $end +$var wire 1 ps OrNorXorOut $end +$var wire 1 qs XorNor $end +$var wire 1 rs nXor $end +$scope module mux0 $end +$var wire 1 ss S $end +$var wire 1 ms in0 $end +$var wire 1 ks in1 $end +$var wire 1 ts nS $end +$var wire 1 us out0 $end +$var wire 1 vs out1 $end +$var wire 1 qs outfinal $end +$upscope $end +$scope module mux1 $end +$var wire 1 ws S $end +$var wire 1 qs in0 $end +$var wire 1 ls in1 $end +$var wire 1 xs nS $end +$var wire 1 ys out0 $end +$var wire 1 zs out1 $end +$var wire 1 ps outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin orbits[4] $end +$scope module attempt $end +$var wire 1 {s A $end +$var wire 1 |s AnandB $end +$var wire 1 }s AnorB $end +$var wire 1 ~s AorB $end +$var wire 1 !t AxorB $end +$var wire 1 "t B $end +$var wire 3 #t Command [2:0] $end +$var wire 1 $t OrNorXorOut $end +$var wire 1 %t XorNor $end +$var wire 1 &t nXor $end +$scope module mux0 $end +$var wire 1 't S $end +$var wire 1 !t in0 $end +$var wire 1 }s in1 $end +$var wire 1 (t nS $end +$var wire 1 )t out0 $end +$var wire 1 *t out1 $end +$var wire 1 %t outfinal $end +$upscope $end +$scope module mux1 $end +$var wire 1 +t S $end +$var wire 1 %t in0 $end +$var wire 1 ~s in1 $end +$var wire 1 ,t nS $end +$var wire 1 -t out0 $end +$var wire 1 .t out1 $end +$var wire 1 $t outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin orbits[5] $end +$scope module attempt $end +$var wire 1 /t A $end +$var wire 1 0t AnandB $end +$var wire 1 1t AnorB $end +$var wire 1 2t AorB $end +$var wire 1 3t AxorB $end +$var wire 1 4t B $end +$var wire 3 5t Command [2:0] $end +$var wire 1 6t OrNorXorOut $end +$var wire 1 7t XorNor $end +$var wire 1 8t nXor $end +$scope module mux0 $end +$var wire 1 9t S $end +$var wire 1 3t in0 $end +$var wire 1 1t in1 $end +$var wire 1 :t nS $end +$var wire 1 ;t out0 $end +$var wire 1 t nS $end +$var wire 1 ?t out0 $end +$var wire 1 @t out1 $end +$var wire 1 6t outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin orbits[6] $end +$scope module attempt $end +$var wire 1 At A $end +$var wire 1 Bt AnandB $end +$var wire 1 Ct AnorB $end +$var wire 1 Dt AorB $end +$var wire 1 Et AxorB $end +$var wire 1 Ft B $end +$var wire 3 Gt Command [2:0] $end +$var wire 1 Ht OrNorXorOut $end +$var wire 1 It XorNor $end +$var wire 1 Jt nXor $end +$scope module mux0 $end +$var wire 1 Kt S $end +$var wire 1 Et in0 $end +$var wire 1 Ct in1 $end +$var wire 1 Lt nS $end +$var wire 1 Mt out0 $end +$var wire 1 Nt out1 $end +$var wire 1 It outfinal $end +$upscope $end +$scope module mux1 $end +$var wire 1 Ot S $end +$var wire 1 It in0 $end +$var wire 1 Dt in1 $end +$var wire 1 Pt nS $end +$var wire 1 Qt out0 $end +$var wire 1 Rt out1 $end +$var wire 1 Ht outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin orbits[7] $end +$scope module attempt $end +$var wire 1 St A $end +$var wire 1 Tt AnandB $end +$var wire 1 Ut AnorB $end +$var wire 1 Vt AorB $end +$var wire 1 Wt AxorB $end +$var wire 1 Xt B $end +$var wire 3 Yt Command [2:0] $end +$var wire 1 Zt OrNorXorOut $end +$var wire 1 [t XorNor $end +$var wire 1 \t nXor $end +$scope module mux0 $end +$var wire 1 ]t S $end +$var wire 1 Wt in0 $end +$var wire 1 Ut in1 $end +$var wire 1 ^t nS $end +$var wire 1 _t out0 $end +$var wire 1 `t out1 $end +$var wire 1 [t outfinal $end +$upscope $end +$scope module mux1 $end +$var wire 1 at S $end +$var wire 1 [t in0 $end +$var wire 1 Vt in1 $end +$var wire 1 bt nS $end +$var wire 1 ct out0 $end +$var wire 1 dt out1 $end +$var wire 1 Zt outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin orbits[8] $end +$scope module attempt $end +$var wire 1 et A $end +$var wire 1 ft AnandB $end +$var wire 1 gt AnorB $end +$var wire 1 ht AorB $end +$var wire 1 it AxorB $end +$var wire 1 jt B $end +$var wire 3 kt Command [2:0] $end +$var wire 1 lt OrNorXorOut $end +$var wire 1 mt XorNor $end +$var wire 1 nt nXor $end +$scope module mux0 $end +$var wire 1 ot S $end +$var wire 1 it in0 $end +$var wire 1 gt in1 $end +$var wire 1 pt nS $end +$var wire 1 qt out0 $end +$var wire 1 rt out1 $end +$var wire 1 mt outfinal $end +$upscope $end +$scope module mux1 $end +$var wire 1 st S $end +$var wire 1 mt in0 $end +$var wire 1 ht in1 $end +$var wire 1 tt nS $end +$var wire 1 ut out0 $end +$var wire 1 vt out1 $end +$var wire 1 lt outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin orbits[9] $end +$scope module attempt $end +$var wire 1 wt A $end +$var wire 1 xt AnandB $end +$var wire 1 yt AnorB $end +$var wire 1 zt AorB $end +$var wire 1 {t AxorB $end +$var wire 1 |t B $end +$var wire 3 }t Command [2:0] $end +$var wire 1 ~t OrNorXorOut $end +$var wire 1 !u XorNor $end +$var wire 1 "u nXor $end +$scope module mux0 $end +$var wire 1 #u S $end +$var wire 1 {t in0 $end +$var wire 1 yt in1 $end +$var wire 1 $u nS $end +$var wire 1 %u out0 $end +$var wire 1 &u out1 $end +$var wire 1 !u outfinal $end +$upscope $end +$scope module mux1 $end +$var wire 1 'u S $end +$var wire 1 !u in0 $end +$var wire 1 zt in1 $end +$var wire 1 (u nS $end +$var wire 1 )u out0 $end +$var wire 1 *u out1 $end +$var wire 1 ~t outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin orbits[10] $end +$scope module attempt $end +$var wire 1 +u A $end +$var wire 1 ,u AnandB $end +$var wire 1 -u AnorB $end +$var wire 1 .u AorB $end +$var wire 1 /u AxorB $end +$var wire 1 0u B $end +$var wire 3 1u Command [2:0] $end +$var wire 1 2u OrNorXorOut $end +$var wire 1 3u XorNor $end +$var wire 1 4u nXor $end +$scope module mux0 $end +$var wire 1 5u S $end +$var wire 1 /u in0 $end +$var wire 1 -u in1 $end +$var wire 1 6u nS $end +$var wire 1 7u out0 $end +$var wire 1 8u out1 $end +$var wire 1 3u outfinal $end +$upscope $end +$scope module mux1 $end +$var wire 1 9u S $end +$var wire 1 3u in0 $end +$var wire 1 .u in1 $end +$var wire 1 :u nS $end +$var wire 1 ;u out0 $end +$var wire 1 u AnandB $end +$var wire 1 ?u AnorB $end +$var wire 1 @u AorB $end +$var wire 1 Au AxorB $end +$var wire 1 Bu B $end +$var wire 3 Cu Command [2:0] $end +$var wire 1 Du OrNorXorOut $end +$var wire 1 Eu XorNor $end +$var wire 1 Fu nXor $end +$scope module mux0 $end +$var wire 1 Gu S $end +$var wire 1 Au in0 $end +$var wire 1 ?u in1 $end +$var wire 1 Hu nS $end +$var wire 1 Iu out0 $end +$var wire 1 Ju out1 $end +$var wire 1 Eu outfinal $end +$upscope $end +$scope module mux1 $end +$var wire 1 Ku S $end +$var wire 1 Eu in0 $end +$var wire 1 @u in1 $end +$var wire 1 Lu nS $end +$var wire 1 Mu out0 $end +$var wire 1 Nu out1 $end +$var wire 1 Du outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin orbits[12] $end +$scope module attempt $end +$var wire 1 Ou A $end +$var wire 1 Pu AnandB $end +$var wire 1 Qu AnorB $end +$var wire 1 Ru AorB $end +$var wire 1 Su AxorB $end +$var wire 1 Tu B $end +$var wire 3 Uu Command [2:0] $end +$var wire 1 Vu OrNorXorOut $end +$var wire 1 Wu XorNor $end +$var wire 1 Xu nXor $end +$scope module mux0 $end +$var wire 1 Yu S $end +$var wire 1 Su in0 $end +$var wire 1 Qu in1 $end +$var wire 1 Zu nS $end +$var wire 1 [u out0 $end +$var wire 1 \u out1 $end +$var wire 1 Wu outfinal $end +$upscope $end +$scope module mux1 $end +$var wire 1 ]u S $end +$var wire 1 Wu in0 $end +$var wire 1 Ru in1 $end +$var wire 1 ^u nS $end +$var wire 1 _u out0 $end +$var wire 1 `u out1 $end +$var wire 1 Vu outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin orbits[13] $end +$scope module attempt $end +$var wire 1 au A $end +$var wire 1 bu AnandB $end +$var wire 1 cu AnorB $end +$var wire 1 du AorB $end +$var wire 1 eu AxorB $end +$var wire 1 fu B $end +$var wire 3 gu Command [2:0] $end +$var wire 1 hu OrNorXorOut $end +$var wire 1 iu XorNor $end +$var wire 1 ju nXor $end +$scope module mux0 $end +$var wire 1 ku S $end +$var wire 1 eu in0 $end +$var wire 1 cu in1 $end +$var wire 1 lu nS $end +$var wire 1 mu out0 $end +$var wire 1 nu out1 $end +$var wire 1 iu outfinal $end +$upscope $end +$scope module mux1 $end +$var wire 1 ou S $end +$var wire 1 iu in0 $end +$var wire 1 du in1 $end +$var wire 1 pu nS $end +$var wire 1 qu out0 $end +$var wire 1 ru out1 $end +$var wire 1 hu outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin orbits[14] $end +$scope module attempt $end +$var wire 1 su A $end +$var wire 1 tu AnandB $end +$var wire 1 uu AnorB $end +$var wire 1 vu AorB $end +$var wire 1 wu AxorB $end +$var wire 1 xu B $end +$var wire 3 yu Command [2:0] $end +$var wire 1 zu OrNorXorOut $end +$var wire 1 {u XorNor $end +$var wire 1 |u nXor $end +$scope module mux0 $end +$var wire 1 }u S $end +$var wire 1 wu in0 $end +$var wire 1 uu in1 $end +$var wire 1 ~u nS $end +$var wire 1 !v out0 $end +$var wire 1 "v out1 $end +$var wire 1 {u outfinal $end +$upscope $end +$scope module mux1 $end +$var wire 1 #v S $end +$var wire 1 {u in0 $end +$var wire 1 vu in1 $end +$var wire 1 $v nS $end +$var wire 1 %v out0 $end +$var wire 1 &v out1 $end +$var wire 1 zu outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin orbits[15] $end +$scope module attempt $end +$var wire 1 'v A $end +$var wire 1 (v AnandB $end +$var wire 1 )v AnorB $end +$var wire 1 *v AorB $end +$var wire 1 +v AxorB $end +$var wire 1 ,v B $end +$var wire 3 -v Command [2:0] $end +$var wire 1 .v OrNorXorOut $end +$var wire 1 /v XorNor $end +$var wire 1 0v nXor $end +$scope module mux0 $end +$var wire 1 1v S $end +$var wire 1 +v in0 $end +$var wire 1 )v in1 $end +$var wire 1 2v nS $end +$var wire 1 3v out0 $end +$var wire 1 4v out1 $end +$var wire 1 /v outfinal $end +$upscope $end +$scope module mux1 $end +$var wire 1 5v S $end +$var wire 1 /v in0 $end +$var wire 1 *v in1 $end +$var wire 1 6v nS $end +$var wire 1 7v out0 $end +$var wire 1 8v out1 $end +$var wire 1 .v outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin orbits[16] $end +$scope module attempt $end +$var wire 1 9v A $end +$var wire 1 :v AnandB $end +$var wire 1 ;v AnorB $end +$var wire 1 v B $end +$var wire 3 ?v Command [2:0] $end +$var wire 1 @v OrNorXorOut $end +$var wire 1 Av XorNor $end +$var wire 1 Bv nXor $end +$scope module mux0 $end +$var wire 1 Cv S $end +$var wire 1 =v in0 $end +$var wire 1 ;v in1 $end +$var wire 1 Dv nS $end +$var wire 1 Ev out0 $end +$var wire 1 Fv out1 $end +$var wire 1 Av outfinal $end +$upscope $end +$scope module mux1 $end +$var wire 1 Gv S $end +$var wire 1 Av in0 $end +$var wire 1 w nXor $end +$scope module mux0 $end +$var wire 1 ?w S $end +$var wire 1 9w in0 $end +$var wire 1 7w in1 $end +$var wire 1 @w nS $end +$var wire 1 Aw out0 $end +$var wire 1 Bw out1 $end +$var wire 1 =w outfinal $end +$upscope $end +$scope module mux1 $end +$var wire 1 Cw S $end +$var wire 1 =w in0 $end +$var wire 1 8w in1 $end +$var wire 1 Dw nS $end +$var wire 1 Ew out0 $end +$var wire 1 Fw out1 $end +$var wire 1 x out1 $end +$var wire 1 9x outfinal $end +$upscope $end +$scope module mux1 $end +$var wire 1 ?x S $end +$var wire 1 9x in0 $end +$var wire 1 4x in1 $end +$var wire 1 @x nS $end +$var wire 1 Ax out0 $end +$var wire 1 Bx out1 $end +$var wire 1 8x outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin orbits[27] $end +$scope module attempt $end +$var wire 1 Cx A $end +$var wire 1 Dx AnandB $end +$var wire 1 Ex AnorB $end +$var wire 1 Fx AorB $end +$var wire 1 Gx AxorB $end +$var wire 1 Hx B $end +$var wire 3 Ix Command [2:0] $end +$var wire 1 Jx OrNorXorOut $end +$var wire 1 Kx XorNor $end +$var wire 1 Lx nXor $end +$scope module mux0 $end +$var wire 1 Mx S $end +$var wire 1 Gx in0 $end +$var wire 1 Ex in1 $end +$var wire 1 Nx nS $end +$var wire 1 Ox out0 $end +$var wire 1 Px out1 $end +$var wire 1 Kx outfinal $end +$upscope $end +$scope module mux1 $end +$var wire 1 Qx S $end +$var wire 1 Kx in0 $end +$var wire 1 Fx in1 $end +$var wire 1 Rx nS $end +$var wire 1 Sx out0 $end +$var wire 1 Tx out1 $end +$var wire 1 Jx outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin orbits[28] $end +$scope module attempt $end +$var wire 1 Ux A $end +$var wire 1 Vx AnandB $end +$var wire 1 Wx AnorB $end +$var wire 1 Xx AorB $end +$var wire 1 Yx AxorB $end +$var wire 1 Zx B $end +$var wire 3 [x Command [2:0] $end +$var wire 1 \x OrNorXorOut $end +$var wire 1 ]x XorNor $end +$var wire 1 ^x nXor $end +$scope module mux0 $end +$var wire 1 _x S $end +$var wire 1 Yx in0 $end +$var wire 1 Wx in1 $end +$var wire 1 `x nS $end +$var wire 1 ax out0 $end +$var wire 1 bx out1 $end +$var wire 1 ]x outfinal $end +$upscope $end +$scope module mux1 $end +$var wire 1 cx S $end +$var wire 1 ]x in0 $end +$var wire 1 Xx in1 $end +$var wire 1 dx nS $end +$var wire 1 ex out0 $end +$var wire 1 fx out1 $end +$var wire 1 \x outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin orbits[29] $end +$scope module attempt $end +$var wire 1 gx A $end +$var wire 1 hx AnandB $end +$var wire 1 ix AnorB $end +$var wire 1 jx AorB $end +$var wire 1 kx AxorB $end +$var wire 1 lx B $end +$var wire 3 mx Command [2:0] $end +$var wire 1 nx OrNorXorOut $end +$var wire 1 ox XorNor $end +$var wire 1 px nXor $end +$scope module mux0 $end +$var wire 1 qx S $end +$var wire 1 kx in0 $end +$var wire 1 ix in1 $end +$var wire 1 rx nS $end +$var wire 1 sx out0 $end +$var wire 1 tx out1 $end +$var wire 1 ox outfinal $end +$upscope $end +$scope module mux1 $end +$var wire 1 ux S $end +$var wire 1 ox in0 $end +$var wire 1 jx in1 $end +$var wire 1 vx nS $end +$var wire 1 wx out0 $end +$var wire 1 xx out1 $end +$var wire 1 nx outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin orbits[30] $end +$scope module attempt $end +$var wire 1 yx A $end +$var wire 1 zx AnandB $end +$var wire 1 {x AnorB $end +$var wire 1 |x AorB $end +$var wire 1 }x AxorB $end +$var wire 1 ~x B $end +$var wire 3 !y Command [2:0] $end +$var wire 1 "y OrNorXorOut $end +$var wire 1 #y XorNor $end +$var wire 1 $y nXor $end +$scope module mux0 $end +$var wire 1 %y S $end +$var wire 1 }x in0 $end +$var wire 1 {x in1 $end +$var wire 1 &y nS $end +$var wire 1 'y out0 $end +$var wire 1 (y out1 $end +$var wire 1 #y outfinal $end +$upscope $end +$scope module mux1 $end +$var wire 1 )y S $end +$var wire 1 #y in0 $end +$var wire 1 |x in1 $end +$var wire 1 *y nS $end +$var wire 1 +y out0 $end +$var wire 1 ,y out1 $end +$var wire 1 "y outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin orbits[31] $end +$scope module attempt $end +$var wire 1 -y A $end +$var wire 1 .y AnandB $end +$var wire 1 /y AnorB $end +$var wire 1 0y AorB $end +$var wire 1 1y AxorB $end +$var wire 1 2y B $end +$var wire 3 3y Command [2:0] $end +$var wire 1 4y OrNorXorOut $end +$var wire 1 5y XorNor $end +$var wire 1 6y nXor $end +$scope module mux0 $end +$var wire 1 7y S $end +$var wire 1 1y in0 $end +$var wire 1 /y in1 $end +$var wire 1 8y nS $end +$var wire 1 9y out0 $end +$var wire 1 :y out1 $end +$var wire 1 5y outfinal $end +$upscope $end +$scope module mux1 $end +$var wire 1 ;y S $end +$var wire 1 5y in0 $end +$var wire 1 0y in1 $end +$var wire 1 y out1 $end +$var wire 1 4y outfinal $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope module ZeroMux0case $end +$var wire 1 ?y S0 $end +$var wire 1 @y S1 $end +$var wire 1 Ay in0 $end +$var wire 1 By in1 $end +$var wire 1 Cy in2 $end +$var wire 1 Dy in3 $end +$var wire 1 Ey nS0 $end +$var wire 1 Fy nS1 $end +$var wire 1 Gy out $end +$var wire 1 Hy out0 $end +$var wire 1 Iy out1 $end +$var wire 1 Jy out2 $end +$var wire 1 Ky out3 $end +$upscope $end +$scope module OneMux0case $end +$var wire 1 Ly S0 $end +$var wire 1 My S1 $end +$var wire 1 Ny in0 $end +$var wire 1 Oy in1 $end +$var wire 1 Py in2 $end +$var wire 1 Qy in3 $end +$var wire 1 Ry nS0 $end +$var wire 1 Sy nS1 $end +$var wire 1 Ty out $end +$var wire 1 Uy out0 $end +$var wire 1 Vy out1 $end +$var wire 1 Wy out2 $end +$var wire 1 Xy out3 $end +$upscope $end +$scope module TwoMux0case $end +$var wire 1 Yy S $end +$var wire 1 Zy in0 $end +$var wire 1 [y in1 $end +$var wire 1 \y nS $end +$var wire 1 ]y out0 $end +$var wire 1 ^y out1 $end +$var wire 1 _y outfinal $end +$upscope $end +$scope begin muxbits[1] $end +$scope module ZeroMux $end +$var wire 1 `y S0 $end +$var wire 1 ay S1 $end +$var wire 1 by in0 $end +$var wire 1 cy in1 $end +$var wire 1 dy in2 $end +$var wire 1 ey in3 $end +$var wire 1 fy nS0 $end +$var wire 1 gy nS1 $end +$var wire 1 hy out $end +$var wire 1 iy out0 $end +$var wire 1 jy out1 $end +$var wire 1 ky out2 $end +$var wire 1 ly out3 $end +$upscope $end +$scope module OneMux $end +$var wire 1 my S0 $end +$var wire 1 ny S1 $end +$var wire 1 oy in0 $end +$var wire 1 py in1 $end +$var wire 1 qy in2 $end +$var wire 1 ry in3 $end +$var wire 1 sy nS0 $end +$var wire 1 ty nS1 $end +$var wire 1 uy out $end +$var wire 1 vy out0 $end +$var wire 1 wy out1 $end +$var wire 1 xy out2 $end +$var wire 1 yy out3 $end +$upscope $end +$scope module TwoMux $end +$var wire 1 zy S $end +$var wire 1 {y in0 $end +$var wire 1 |y in1 $end +$var wire 1 }y nS $end +$var wire 1 ~y out0 $end +$var wire 1 !z out1 $end +$var wire 1 "z outfinal $end +$upscope $end +$upscope $end +$scope begin muxbits[2] $end +$scope module ZeroMux $end +$var wire 1 #z S0 $end +$var wire 1 $z S1 $end +$var wire 1 %z in0 $end +$var wire 1 &z in1 $end +$var wire 1 'z in2 $end +$var wire 1 (z in3 $end +$var wire 1 )z nS0 $end +$var wire 1 *z nS1 $end +$var wire 1 +z out $end +$var wire 1 ,z out0 $end +$var wire 1 -z out1 $end +$var wire 1 .z out2 $end +$var wire 1 /z out3 $end +$upscope $end +$scope module OneMux $end +$var wire 1 0z S0 $end +$var wire 1 1z S1 $end +$var wire 1 2z in0 $end +$var wire 1 3z in1 $end +$var wire 1 4z in2 $end +$var wire 1 5z in3 $end +$var wire 1 6z nS0 $end +$var wire 1 7z nS1 $end +$var wire 1 8z out $end +$var wire 1 9z out0 $end +$var wire 1 :z out1 $end +$var wire 1 ;z out2 $end +$var wire 1 z in0 $end +$var wire 1 ?z in1 $end +$var wire 1 @z nS $end +$var wire 1 Az out0 $end +$var wire 1 Bz out1 $end +$var wire 1 Cz outfinal $end +$upscope $end +$upscope $end +$scope begin muxbits[3] $end +$scope module ZeroMux $end +$var wire 1 Dz S0 $end +$var wire 1 Ez S1 $end +$var wire 1 Fz in0 $end +$var wire 1 Gz in1 $end +$var wire 1 Hz in2 $end +$var wire 1 Iz in3 $end +$var wire 1 Jz nS0 $end +$var wire 1 Kz nS1 $end +$var wire 1 Lz out $end +$var wire 1 Mz out0 $end +$var wire 1 Nz out1 $end +$var wire 1 Oz out2 $end +$var wire 1 Pz out3 $end +$upscope $end +$scope module OneMux $end +$var wire 1 Qz S0 $end +$var wire 1 Rz S1 $end +$var wire 1 Sz in0 $end +$var wire 1 Tz in1 $end +$var wire 1 Uz in2 $end +$var wire 1 Vz in3 $end +$var wire 1 Wz nS0 $end +$var wire 1 Xz nS1 $end +$var wire 1 Yz out $end +$var wire 1 Zz out0 $end +$var wire 1 [z out1 $end +$var wire 1 \z out2 $end +$var wire 1 ]z out3 $end +$upscope $end +$scope module TwoMux $end +$var wire 1 ^z S $end +$var wire 1 _z in0 $end +$var wire 1 `z in1 $end +$var wire 1 az nS $end +$var wire 1 bz out0 $end +$var wire 1 cz out1 $end +$var wire 1 dz outfinal $end +$upscope $end +$upscope $end +$scope begin muxbits[4] $end +$scope module ZeroMux $end +$var wire 1 ez S0 $end +$var wire 1 fz S1 $end +$var wire 1 gz in0 $end +$var wire 1 hz in1 $end +$var wire 1 iz in2 $end +$var wire 1 jz in3 $end +$var wire 1 kz nS0 $end +$var wire 1 lz nS1 $end +$var wire 1 mz out $end +$var wire 1 nz out0 $end +$var wire 1 oz out1 $end +$var wire 1 pz out2 $end +$var wire 1 qz out3 $end +$upscope $end +$scope module OneMux $end +$var wire 1 rz S0 $end +$var wire 1 sz S1 $end +$var wire 1 tz in0 $end +$var wire 1 uz in1 $end +$var wire 1 vz in2 $end +$var wire 1 wz in3 $end +$var wire 1 xz nS0 $end +$var wire 1 yz nS1 $end +$var wire 1 zz out $end +$var wire 1 {z out0 $end +$var wire 1 |z out1 $end +$var wire 1 }z out2 $end +$var wire 1 ~z out3 $end +$upscope $end +$scope module TwoMux $end +$var wire 1 !{ S $end +$var wire 1 "{ in0 $end +$var wire 1 #{ in1 $end +$var wire 1 ${ nS $end +$var wire 1 %{ out0 $end +$var wire 1 &{ out1 $end +$var wire 1 '{ outfinal $end +$upscope $end +$upscope $end +$scope begin muxbits[5] $end +$scope module ZeroMux $end +$var wire 1 ({ S0 $end +$var wire 1 ){ S1 $end +$var wire 1 *{ in0 $end +$var wire 1 +{ in1 $end +$var wire 1 ,{ in2 $end +$var wire 1 -{ in3 $end +$var wire 1 .{ nS0 $end +$var wire 1 /{ nS1 $end +$var wire 1 0{ out $end +$var wire 1 1{ out0 $end +$var wire 1 2{ out1 $end +$var wire 1 3{ out2 $end +$var wire 1 4{ out3 $end +$upscope $end +$scope module OneMux $end +$var wire 1 5{ S0 $end +$var wire 1 6{ S1 $end +$var wire 1 7{ in0 $end +$var wire 1 8{ in1 $end +$var wire 1 9{ in2 $end +$var wire 1 :{ in3 $end +$var wire 1 ;{ nS0 $end +$var wire 1 <{ nS1 $end +$var wire 1 ={ out $end +$var wire 1 >{ out0 $end +$var wire 1 ?{ out1 $end +$var wire 1 @{ out2 $end +$var wire 1 A{ out3 $end +$upscope $end +$scope module TwoMux $end +$var wire 1 B{ S $end +$var wire 1 C{ in0 $end +$var wire 1 D{ in1 $end +$var wire 1 E{ nS $end +$var wire 1 F{ out0 $end +$var wire 1 G{ out1 $end +$var wire 1 H{ outfinal $end +$upscope $end +$upscope $end +$scope begin muxbits[6] $end +$scope module ZeroMux $end +$var wire 1 I{ S0 $end +$var wire 1 J{ S1 $end +$var wire 1 K{ in0 $end +$var wire 1 L{ in1 $end +$var wire 1 M{ in2 $end +$var wire 1 N{ in3 $end +$var wire 1 O{ nS0 $end +$var wire 1 P{ nS1 $end +$var wire 1 Q{ out $end +$var wire 1 R{ out0 $end +$var wire 1 S{ out1 $end +$var wire 1 T{ out2 $end +$var wire 1 U{ out3 $end +$upscope $end +$scope module OneMux $end +$var wire 1 V{ S0 $end +$var wire 1 W{ S1 $end +$var wire 1 X{ in0 $end +$var wire 1 Y{ in1 $end +$var wire 1 Z{ in2 $end +$var wire 1 [{ in3 $end +$var wire 1 \{ nS0 $end +$var wire 1 ]{ nS1 $end +$var wire 1 ^{ out $end +$var wire 1 _{ out0 $end +$var wire 1 `{ out1 $end +$var wire 1 a{ out2 $end +$var wire 1 b{ out3 $end +$upscope $end +$scope module TwoMux $end +$var wire 1 c{ S $end +$var wire 1 d{ in0 $end +$var wire 1 e{ in1 $end +$var wire 1 f{ nS $end +$var wire 1 g{ out0 $end +$var wire 1 h{ out1 $end +$var wire 1 i{ outfinal $end +$upscope $end +$upscope $end +$scope begin muxbits[7] $end +$scope module ZeroMux $end +$var wire 1 j{ S0 $end +$var wire 1 k{ S1 $end +$var wire 1 l{ in0 $end +$var wire 1 m{ in1 $end +$var wire 1 n{ in2 $end +$var wire 1 o{ in3 $end +$var wire 1 p{ nS0 $end +$var wire 1 q{ nS1 $end +$var wire 1 r{ out $end +$var wire 1 s{ out0 $end +$var wire 1 t{ out1 $end +$var wire 1 u{ out2 $end +$var wire 1 v{ out3 $end +$upscope $end +$scope module OneMux $end +$var wire 1 w{ S0 $end +$var wire 1 x{ S1 $end +$var wire 1 y{ in0 $end +$var wire 1 z{ in1 $end +$var wire 1 {{ in2 $end +$var wire 1 |{ in3 $end +$var wire 1 }{ nS0 $end +$var wire 1 ~{ nS1 $end +$var wire 1 !| out $end +$var wire 1 "| out0 $end +$var wire 1 #| out1 $end +$var wire 1 $| out2 $end +$var wire 1 %| out3 $end +$upscope $end +$scope module TwoMux $end +$var wire 1 &| S $end +$var wire 1 '| in0 $end +$var wire 1 (| in1 $end +$var wire 1 )| nS $end +$var wire 1 *| out0 $end +$var wire 1 +| out1 $end +$var wire 1 ,| outfinal $end +$upscope $end +$upscope $end +$scope begin muxbits[8] $end +$scope module ZeroMux $end +$var wire 1 -| S0 $end +$var wire 1 .| S1 $end +$var wire 1 /| in0 $end +$var wire 1 0| in1 $end +$var wire 1 1| in2 $end +$var wire 1 2| in3 $end +$var wire 1 3| nS0 $end +$var wire 1 4| nS1 $end +$var wire 1 5| out $end +$var wire 1 6| out0 $end +$var wire 1 7| out1 $end +$var wire 1 8| out2 $end +$var wire 1 9| out3 $end +$upscope $end +$scope module OneMux $end +$var wire 1 :| S0 $end +$var wire 1 ;| S1 $end +$var wire 1 <| in0 $end +$var wire 1 =| in1 $end +$var wire 1 >| in2 $end +$var wire 1 ?| in3 $end +$var wire 1 @| nS0 $end +$var wire 1 A| nS1 $end +$var wire 1 B| out $end +$var wire 1 C| out0 $end +$var wire 1 D| out1 $end +$var wire 1 E| out2 $end +$var wire 1 F| out3 $end +$upscope $end +$scope module TwoMux $end +$var wire 1 G| S $end +$var wire 1 H| in0 $end +$var wire 1 I| in1 $end +$var wire 1 J| nS $end +$var wire 1 K| out0 $end +$var wire 1 L| out1 $end +$var wire 1 M| outfinal $end +$upscope $end +$upscope $end +$scope begin muxbits[9] $end +$scope module ZeroMux $end +$var wire 1 N| S0 $end +$var wire 1 O| S1 $end +$var wire 1 P| in0 $end +$var wire 1 Q| in1 $end +$var wire 1 R| in2 $end +$var wire 1 S| in3 $end +$var wire 1 T| nS0 $end +$var wire 1 U| nS1 $end +$var wire 1 V| out $end +$var wire 1 W| out0 $end +$var wire 1 X| out1 $end +$var wire 1 Y| out2 $end +$var wire 1 Z| out3 $end +$upscope $end +$scope module OneMux $end +$var wire 1 [| S0 $end +$var wire 1 \| S1 $end +$var wire 1 ]| in0 $end +$var wire 1 ^| in1 $end +$var wire 1 _| in2 $end +$var wire 1 `| in3 $end +$var wire 1 a| nS0 $end +$var wire 1 b| nS1 $end +$var wire 1 c| out $end +$var wire 1 d| out0 $end +$var wire 1 e| out1 $end +$var wire 1 f| out2 $end +$var wire 1 g| out3 $end +$upscope $end +$scope module TwoMux $end +$var wire 1 h| S $end +$var wire 1 i| in0 $end +$var wire 1 j| in1 $end +$var wire 1 k| nS $end +$var wire 1 l| out0 $end +$var wire 1 m| out1 $end +$var wire 1 n| outfinal $end +$upscope $end +$upscope $end +$scope begin muxbits[10] $end +$scope module ZeroMux $end +$var wire 1 o| S0 $end +$var wire 1 p| S1 $end +$var wire 1 q| in0 $end +$var wire 1 r| in1 $end +$var wire 1 s| in2 $end +$var wire 1 t| in3 $end +$var wire 1 u| nS0 $end +$var wire 1 v| nS1 $end +$var wire 1 w| out $end +$var wire 1 x| out0 $end +$var wire 1 y| out1 $end +$var wire 1 z| out2 $end +$var wire 1 {| out3 $end +$upscope $end +$scope module OneMux $end +$var wire 1 || S0 $end +$var wire 1 }| S1 $end +$var wire 1 ~| in0 $end +$var wire 1 !} in1 $end +$var wire 1 "} in2 $end +$var wire 1 #} in3 $end +$var wire 1 $} nS0 $end +$var wire 1 %} nS1 $end +$var wire 1 &} out $end +$var wire 1 '} out0 $end +$var wire 1 (} out1 $end +$var wire 1 )} out2 $end +$var wire 1 *} out3 $end +$upscope $end +$scope module TwoMux $end +$var wire 1 +} S $end +$var wire 1 ,} in0 $end +$var wire 1 -} in1 $end +$var wire 1 .} nS $end +$var wire 1 /} out0 $end +$var wire 1 0} out1 $end +$var wire 1 1} outfinal $end +$upscope $end +$upscope $end +$scope begin muxbits[11] $end +$scope module ZeroMux $end +$var wire 1 2} S0 $end +$var wire 1 3} S1 $end +$var wire 1 4} in0 $end +$var wire 1 5} in1 $end +$var wire 1 6} in2 $end +$var wire 1 7} in3 $end +$var wire 1 8} nS0 $end +$var wire 1 9} nS1 $end +$var wire 1 :} out $end +$var wire 1 ;} out0 $end +$var wire 1 <} out1 $end +$var wire 1 =} out2 $end +$var wire 1 >} out3 $end +$upscope $end +$scope module OneMux $end +$var wire 1 ?} S0 $end +$var wire 1 @} S1 $end +$var wire 1 A} in0 $end +$var wire 1 B} in1 $end +$var wire 1 C} in2 $end +$var wire 1 D} in3 $end +$var wire 1 E} nS0 $end +$var wire 1 F} nS1 $end +$var wire 1 G} out $end +$var wire 1 H} out0 $end +$var wire 1 I} out1 $end +$var wire 1 J} out2 $end +$var wire 1 K} out3 $end +$upscope $end +$scope module TwoMux $end +$var wire 1 L} S $end +$var wire 1 M} in0 $end +$var wire 1 N} in1 $end +$var wire 1 O} nS $end +$var wire 1 P} out0 $end +$var wire 1 Q} out1 $end +$var wire 1 R} outfinal $end +$upscope $end +$upscope $end +$scope begin muxbits[12] $end +$scope module ZeroMux $end +$var wire 1 S} S0 $end +$var wire 1 T} S1 $end +$var wire 1 U} in0 $end +$var wire 1 V} in1 $end +$var wire 1 W} in2 $end +$var wire 1 X} in3 $end +$var wire 1 Y} nS0 $end +$var wire 1 Z} nS1 $end +$var wire 1 [} out $end +$var wire 1 \} out0 $end +$var wire 1 ]} out1 $end +$var wire 1 ^} out2 $end +$var wire 1 _} out3 $end +$upscope $end +$scope module OneMux $end +$var wire 1 `} S0 $end +$var wire 1 a} S1 $end +$var wire 1 b} in0 $end +$var wire 1 c} in1 $end +$var wire 1 d} in2 $end +$var wire 1 e} in3 $end +$var wire 1 f} nS0 $end +$var wire 1 g} nS1 $end +$var wire 1 h} out $end +$var wire 1 i} out0 $end +$var wire 1 j} out1 $end +$var wire 1 k} out2 $end +$var wire 1 l} out3 $end +$upscope $end +$scope module TwoMux $end +$var wire 1 m} S $end +$var wire 1 n} in0 $end +$var wire 1 o} in1 $end +$var wire 1 p} nS $end +$var wire 1 q} out0 $end +$var wire 1 r} out1 $end +$var wire 1 s} outfinal $end +$upscope $end +$upscope $end +$scope begin muxbits[13] $end +$scope module ZeroMux $end +$var wire 1 t} S0 $end +$var wire 1 u} S1 $end +$var wire 1 v} in0 $end +$var wire 1 w} in1 $end +$var wire 1 x} in2 $end +$var wire 1 y} in3 $end +$var wire 1 z} nS0 $end +$var wire 1 {} nS1 $end +$var wire 1 |} out $end +$var wire 1 }} out0 $end +$var wire 1 ~} out1 $end +$var wire 1 !~ out2 $end +$var wire 1 "~ out3 $end +$upscope $end +$scope module OneMux $end +$var wire 1 #~ S0 $end +$var wire 1 $~ S1 $end +$var wire 1 %~ in0 $end +$var wire 1 &~ in1 $end +$var wire 1 '~ in2 $end +$var wire 1 (~ in3 $end +$var wire 1 )~ nS0 $end +$var wire 1 *~ nS1 $end +$var wire 1 +~ out $end +$var wire 1 ,~ out0 $end +$var wire 1 -~ out1 $end +$var wire 1 .~ out2 $end +$var wire 1 /~ out3 $end +$upscope $end +$scope module TwoMux $end +$var wire 1 0~ S $end +$var wire 1 1~ in0 $end +$var wire 1 2~ in1 $end +$var wire 1 3~ nS $end +$var wire 1 4~ out0 $end +$var wire 1 5~ out1 $end +$var wire 1 6~ outfinal $end +$upscope $end +$upscope $end +$scope begin muxbits[14] $end +$scope module ZeroMux $end +$var wire 1 7~ S0 $end +$var wire 1 8~ S1 $end +$var wire 1 9~ in0 $end +$var wire 1 :~ in1 $end +$var wire 1 ;~ in2 $end +$var wire 1 <~ in3 $end +$var wire 1 =~ nS0 $end +$var wire 1 >~ nS1 $end +$var wire 1 ?~ out $end +$var wire 1 @~ out0 $end +$var wire 1 A~ out1 $end +$var wire 1 B~ out2 $end +$var wire 1 C~ out3 $end +$upscope $end +$scope module OneMux $end +$var wire 1 D~ S0 $end +$var wire 1 E~ S1 $end +$var wire 1 F~ in0 $end +$var wire 1 G~ in1 $end +$var wire 1 H~ in2 $end +$var wire 1 I~ in3 $end +$var wire 1 J~ nS0 $end +$var wire 1 K~ nS1 $end +$var wire 1 L~ out $end +$var wire 1 M~ out0 $end +$var wire 1 N~ out1 $end +$var wire 1 O~ out2 $end +$var wire 1 P~ out3 $end +$upscope $end +$scope module TwoMux $end +$var wire 1 Q~ S $end +$var wire 1 R~ in0 $end +$var wire 1 S~ in1 $end +$var wire 1 T~ nS $end +$var wire 1 U~ out0 $end +$var wire 1 V~ out1 $end +$var wire 1 W~ outfinal $end +$upscope $end +$upscope $end +$scope begin muxbits[15] $end +$scope module ZeroMux $end +$var wire 1 X~ S0 $end +$var wire 1 Y~ S1 $end +$var wire 1 Z~ in0 $end +$var wire 1 [~ in1 $end +$var wire 1 \~ in2 $end +$var wire 1 ]~ in3 $end +$var wire 1 ^~ nS0 $end +$var wire 1 _~ nS1 $end +$var wire 1 `~ out $end +$var wire 1 a~ out0 $end +$var wire 1 b~ out1 $end +$var wire 1 c~ out2 $end +$var wire 1 d~ out3 $end +$upscope $end +$scope module OneMux $end +$var wire 1 e~ S0 $end +$var wire 1 f~ S1 $end +$var wire 1 g~ in0 $end +$var wire 1 h~ in1 $end +$var wire 1 i~ in2 $end +$var wire 1 j~ in3 $end +$var wire 1 k~ nS0 $end +$var wire 1 l~ nS1 $end +$var wire 1 m~ out $end +$var wire 1 n~ out0 $end +$var wire 1 o~ out1 $end +$var wire 1 p~ out2 $end +$var wire 1 q~ out3 $end +$upscope $end +$scope module TwoMux $end +$var wire 1 r~ S $end +$var wire 1 s~ in0 $end +$var wire 1 t~ in1 $end +$var wire 1 u~ nS $end +$var wire 1 v~ out0 $end +$var wire 1 w~ out1 $end +$var wire 1 x~ outfinal $end +$upscope $end +$upscope $end +$scope begin muxbits[16] $end +$scope module ZeroMux $end +$var wire 1 y~ S0 $end +$var wire 1 z~ S1 $end +$var wire 1 {~ in0 $end +$var wire 1 |~ in1 $end +$var wire 1 }~ in2 $end +$var wire 1 ~~ in3 $end +$var wire 1 !!" nS0 $end +$var wire 1 "!" nS1 $end +$var wire 1 #!" out $end +$var wire 1 $!" out0 $end +$var wire 1 %!" out1 $end +$var wire 1 &!" out2 $end +$var wire 1 '!" out3 $end +$upscope $end +$scope module OneMux $end +$var wire 1 (!" S0 $end +$var wire 1 )!" S1 $end +$var wire 1 *!" in0 $end +$var wire 1 +!" in1 $end +$var wire 1 ,!" in2 $end +$var wire 1 -!" in3 $end +$var wire 1 .!" nS0 $end +$var wire 1 /!" nS1 $end +$var wire 1 0!" out $end +$var wire 1 1!" out0 $end +$var wire 1 2!" out1 $end +$var wire 1 3!" out2 $end +$var wire 1 4!" out3 $end +$upscope $end +$scope module TwoMux $end +$var wire 1 5!" S $end +$var wire 1 6!" in0 $end +$var wire 1 7!" in1 $end +$var wire 1 8!" nS $end +$var wire 1 9!" out0 $end +$var wire 1 :!" out1 $end +$var wire 1 ;!" outfinal $end +$upscope $end +$upscope $end +$scope begin muxbits[17] $end +$scope module ZeroMux $end +$var wire 1 !" in0 $end +$var wire 1 ?!" in1 $end +$var wire 1 @!" in2 $end +$var wire 1 A!" in3 $end +$var wire 1 B!" nS0 $end +$var wire 1 C!" nS1 $end +$var wire 1 D!" out $end +$var wire 1 E!" out0 $end +$var wire 1 F!" out1 $end +$var wire 1 G!" out2 $end +$var wire 1 H!" out3 $end +$upscope $end +$scope module OneMux $end +$var wire 1 I!" S0 $end +$var wire 1 J!" S1 $end +$var wire 1 K!" in0 $end +$var wire 1 L!" in1 $end +$var wire 1 M!" in2 $end +$var wire 1 N!" in3 $end +$var wire 1 O!" nS0 $end +$var wire 1 P!" nS1 $end +$var wire 1 Q!" out $end +$var wire 1 R!" out0 $end +$var wire 1 S!" out1 $end +$var wire 1 T!" out2 $end +$var wire 1 U!" out3 $end +$upscope $end +$scope module TwoMux $end +$var wire 1 V!" S $end +$var wire 1 W!" in0 $end +$var wire 1 X!" in1 $end +$var wire 1 Y!" nS $end +$var wire 1 Z!" out0 $end +$var wire 1 [!" out1 $end +$var wire 1 \!" outfinal $end +$upscope $end +$upscope $end +$scope begin muxbits[18] $end +$scope module ZeroMux $end +$var wire 1 ]!" S0 $end +$var wire 1 ^!" S1 $end +$var wire 1 _!" in0 $end +$var wire 1 `!" in1 $end +$var wire 1 a!" in2 $end +$var wire 1 b!" in3 $end +$var wire 1 c!" nS0 $end +$var wire 1 d!" nS1 $end +$var wire 1 e!" out $end +$var wire 1 f!" out0 $end +$var wire 1 g!" out1 $end +$var wire 1 h!" out2 $end +$var wire 1 i!" out3 $end +$upscope $end +$scope module OneMux $end +$var wire 1 j!" S0 $end +$var wire 1 k!" S1 $end +$var wire 1 l!" in0 $end +$var wire 1 m!" in1 $end +$var wire 1 n!" in2 $end +$var wire 1 o!" in3 $end +$var wire 1 p!" nS0 $end +$var wire 1 q!" nS1 $end +$var wire 1 r!" out $end +$var wire 1 s!" out0 $end +$var wire 1 t!" out1 $end +$var wire 1 u!" out2 $end +$var wire 1 v!" out3 $end +$upscope $end +$scope module TwoMux $end +$var wire 1 w!" S $end +$var wire 1 x!" in0 $end +$var wire 1 y!" in1 $end +$var wire 1 z!" nS $end +$var wire 1 {!" out0 $end +$var wire 1 |!" out1 $end +$var wire 1 }!" outfinal $end +$upscope $end +$upscope $end +$scope begin muxbits[19] $end +$scope module ZeroMux $end +$var wire 1 ~!" S0 $end +$var wire 1 !"" S1 $end +$var wire 1 """ in0 $end +$var wire 1 #"" in1 $end +$var wire 1 $"" in2 $end +$var wire 1 %"" in3 $end +$var wire 1 &"" nS0 $end +$var wire 1 '"" nS1 $end +$var wire 1 ("" out $end +$var wire 1 )"" out0 $end +$var wire 1 *"" out1 $end +$var wire 1 +"" out2 $end +$var wire 1 ,"" out3 $end +$upscope $end +$scope module OneMux $end +$var wire 1 -"" S0 $end +$var wire 1 ."" S1 $end +$var wire 1 /"" in0 $end +$var wire 1 0"" in1 $end +$var wire 1 1"" in2 $end +$var wire 1 2"" in3 $end +$var wire 1 3"" nS0 $end +$var wire 1 4"" nS1 $end +$var wire 1 5"" out $end +$var wire 1 6"" out0 $end +$var wire 1 7"" out1 $end +$var wire 1 8"" out2 $end +$var wire 1 9"" out3 $end +$upscope $end +$scope module TwoMux $end +$var wire 1 :"" S $end +$var wire 1 ;"" in0 $end +$var wire 1 <"" in1 $end +$var wire 1 ="" nS $end +$var wire 1 >"" out0 $end +$var wire 1 ?"" out1 $end +$var wire 1 @"" outfinal $end +$upscope $end +$upscope $end +$scope begin muxbits[20] $end +$scope module ZeroMux $end +$var wire 1 A"" S0 $end +$var wire 1 B"" S1 $end +$var wire 1 C"" in0 $end +$var wire 1 D"" in1 $end +$var wire 1 E"" in2 $end +$var wire 1 F"" in3 $end +$var wire 1 G"" nS0 $end +$var wire 1 H"" nS1 $end +$var wire 1 I"" out $end +$var wire 1 J"" out0 $end +$var wire 1 K"" out1 $end +$var wire 1 L"" out2 $end +$var wire 1 M"" out3 $end +$upscope $end +$scope module OneMux $end +$var wire 1 N"" S0 $end +$var wire 1 O"" S1 $end +$var wire 1 P"" in0 $end +$var wire 1 Q"" in1 $end +$var wire 1 R"" in2 $end +$var wire 1 S"" in3 $end +$var wire 1 T"" nS0 $end +$var wire 1 U"" nS1 $end +$var wire 1 V"" out $end +$var wire 1 W"" out0 $end +$var wire 1 X"" out1 $end +$var wire 1 Y"" out2 $end +$var wire 1 Z"" out3 $end +$upscope $end +$scope module TwoMux $end +$var wire 1 ["" S $end +$var wire 1 \"" in0 $end +$var wire 1 ]"" in1 $end +$var wire 1 ^"" nS $end +$var wire 1 _"" out0 $end +$var wire 1 `"" out1 $end +$var wire 1 a"" outfinal $end +$upscope $end +$upscope $end +$scope begin muxbits[21] $end +$scope module ZeroMux $end +$var wire 1 b"" S0 $end +$var wire 1 c"" S1 $end +$var wire 1 d"" in0 $end +$var wire 1 e"" in1 $end +$var wire 1 f"" in2 $end +$var wire 1 g"" in3 $end +$var wire 1 h"" nS0 $end +$var wire 1 i"" nS1 $end +$var wire 1 j"" out $end +$var wire 1 k"" out0 $end +$var wire 1 l"" out1 $end +$var wire 1 m"" out2 $end +$var wire 1 n"" out3 $end +$upscope $end +$scope module OneMux $end +$var wire 1 o"" S0 $end +$var wire 1 p"" S1 $end +$var wire 1 q"" in0 $end +$var wire 1 r"" in1 $end +$var wire 1 s"" in2 $end +$var wire 1 t"" in3 $end +$var wire 1 u"" nS0 $end +$var wire 1 v"" nS1 $end +$var wire 1 w"" out $end +$var wire 1 x"" out0 $end +$var wire 1 y"" out1 $end +$var wire 1 z"" out2 $end +$var wire 1 {"" out3 $end +$upscope $end +$scope module TwoMux $end +$var wire 1 |"" S $end +$var wire 1 }"" in0 $end +$var wire 1 ~"" in1 $end +$var wire 1 !#" nS $end +$var wire 1 "#" out0 $end +$var wire 1 ##" out1 $end +$var wire 1 $#" outfinal $end +$upscope $end +$upscope $end +$scope begin muxbits[22] $end +$scope module ZeroMux $end +$var wire 1 %#" S0 $end +$var wire 1 &#" S1 $end +$var wire 1 '#" in0 $end +$var wire 1 (#" in1 $end +$var wire 1 )#" in2 $end +$var wire 1 *#" in3 $end +$var wire 1 +#" nS0 $end +$var wire 1 ,#" nS1 $end +$var wire 1 -#" out $end +$var wire 1 .#" out0 $end +$var wire 1 /#" out1 $end +$var wire 1 0#" out2 $end +$var wire 1 1#" out3 $end +$upscope $end +$scope module OneMux $end +$var wire 1 2#" S0 $end +$var wire 1 3#" S1 $end +$var wire 1 4#" in0 $end +$var wire 1 5#" in1 $end +$var wire 1 6#" in2 $end +$var wire 1 7#" in3 $end +$var wire 1 8#" nS0 $end +$var wire 1 9#" nS1 $end +$var wire 1 :#" out $end +$var wire 1 ;#" out0 $end +$var wire 1 <#" out1 $end +$var wire 1 =#" out2 $end +$var wire 1 >#" out3 $end +$upscope $end +$scope module TwoMux $end +$var wire 1 ?#" S $end +$var wire 1 @#" in0 $end +$var wire 1 A#" in1 $end +$var wire 1 B#" nS $end +$var wire 1 C#" out0 $end +$var wire 1 D#" out1 $end +$var wire 1 E#" outfinal $end +$upscope $end +$upscope $end +$scope begin muxbits[23] $end +$scope module ZeroMux $end +$var wire 1 F#" S0 $end +$var wire 1 G#" S1 $end +$var wire 1 H#" in0 $end +$var wire 1 I#" in1 $end +$var wire 1 J#" in2 $end +$var wire 1 K#" in3 $end +$var wire 1 L#" nS0 $end +$var wire 1 M#" nS1 $end +$var wire 1 N#" out $end +$var wire 1 O#" out0 $end +$var wire 1 P#" out1 $end +$var wire 1 Q#" out2 $end +$var wire 1 R#" out3 $end +$upscope $end +$scope module OneMux $end +$var wire 1 S#" S0 $end +$var wire 1 T#" S1 $end +$var wire 1 U#" in0 $end +$var wire 1 V#" in1 $end +$var wire 1 W#" in2 $end +$var wire 1 X#" in3 $end +$var wire 1 Y#" nS0 $end +$var wire 1 Z#" nS1 $end +$var wire 1 [#" out $end +$var wire 1 \#" out0 $end +$var wire 1 ]#" out1 $end +$var wire 1 ^#" out2 $end +$var wire 1 _#" out3 $end +$upscope $end +$scope module TwoMux $end +$var wire 1 `#" S $end +$var wire 1 a#" in0 $end +$var wire 1 b#" in1 $end +$var wire 1 c#" nS $end +$var wire 1 d#" out0 $end +$var wire 1 e#" out1 $end +$var wire 1 f#" outfinal $end +$upscope $end +$upscope $end +$scope begin muxbits[24] $end +$scope module ZeroMux $end +$var wire 1 g#" S0 $end +$var wire 1 h#" S1 $end +$var wire 1 i#" in0 $end +$var wire 1 j#" in1 $end +$var wire 1 k#" in2 $end +$var wire 1 l#" in3 $end +$var wire 1 m#" nS0 $end +$var wire 1 n#" nS1 $end +$var wire 1 o#" out $end +$var wire 1 p#" out0 $end +$var wire 1 q#" out1 $end +$var wire 1 r#" out2 $end +$var wire 1 s#" out3 $end +$upscope $end +$scope module OneMux $end +$var wire 1 t#" S0 $end +$var wire 1 u#" S1 $end +$var wire 1 v#" in0 $end +$var wire 1 w#" in1 $end +$var wire 1 x#" in2 $end +$var wire 1 y#" in3 $end +$var wire 1 z#" nS0 $end +$var wire 1 {#" nS1 $end +$var wire 1 |#" out $end +$var wire 1 }#" out0 $end +$var wire 1 ~#" out1 $end +$var wire 1 !$" out2 $end +$var wire 1 "$" out3 $end +$upscope $end +$scope module TwoMux $end +$var wire 1 #$" S $end +$var wire 1 $$" in0 $end +$var wire 1 %$" in1 $end +$var wire 1 &$" nS $end +$var wire 1 '$" out0 $end +$var wire 1 ($" out1 $end +$var wire 1 )$" outfinal $end +$upscope $end +$upscope $end +$scope begin muxbits[25] $end +$scope module ZeroMux $end +$var wire 1 *$" S0 $end +$var wire 1 +$" S1 $end +$var wire 1 ,$" in0 $end +$var wire 1 -$" in1 $end +$var wire 1 .$" in2 $end +$var wire 1 /$" in3 $end +$var wire 1 0$" nS0 $end +$var wire 1 1$" nS1 $end +$var wire 1 2$" out $end +$var wire 1 3$" out0 $end +$var wire 1 4$" out1 $end +$var wire 1 5$" out2 $end +$var wire 1 6$" out3 $end +$upscope $end +$scope module OneMux $end +$var wire 1 7$" S0 $end +$var wire 1 8$" S1 $end +$var wire 1 9$" in0 $end +$var wire 1 :$" in1 $end +$var wire 1 ;$" in2 $end +$var wire 1 <$" in3 $end +$var wire 1 =$" nS0 $end +$var wire 1 >$" nS1 $end +$var wire 1 ?$" out $end +$var wire 1 @$" out0 $end +$var wire 1 A$" out1 $end +$var wire 1 B$" out2 $end +$var wire 1 C$" out3 $end +$upscope $end +$scope module TwoMux $end +$var wire 1 D$" S $end +$var wire 1 E$" in0 $end +$var wire 1 F$" in1 $end +$var wire 1 G$" nS $end +$var wire 1 H$" out0 $end +$var wire 1 I$" out1 $end +$var wire 1 J$" outfinal $end +$upscope $end +$upscope $end +$scope begin muxbits[26] $end +$scope module ZeroMux $end +$var wire 1 K$" S0 $end +$var wire 1 L$" S1 $end +$var wire 1 M$" in0 $end +$var wire 1 N$" in1 $end +$var wire 1 O$" in2 $end +$var wire 1 P$" in3 $end +$var wire 1 Q$" nS0 $end +$var wire 1 R$" nS1 $end +$var wire 1 S$" out $end +$var wire 1 T$" out0 $end +$var wire 1 U$" out1 $end +$var wire 1 V$" out2 $end +$var wire 1 W$" out3 $end +$upscope $end +$scope module OneMux $end +$var wire 1 X$" S0 $end +$var wire 1 Y$" S1 $end +$var wire 1 Z$" in0 $end +$var wire 1 [$" in1 $end +$var wire 1 \$" in2 $end +$var wire 1 ]$" in3 $end +$var wire 1 ^$" nS0 $end +$var wire 1 _$" nS1 $end +$var wire 1 `$" out $end +$var wire 1 a$" out0 $end +$var wire 1 b$" out1 $end +$var wire 1 c$" out2 $end +$var wire 1 d$" out3 $end +$upscope $end +$scope module TwoMux $end +$var wire 1 e$" S $end +$var wire 1 f$" in0 $end +$var wire 1 g$" in1 $end +$var wire 1 h$" nS $end +$var wire 1 i$" out0 $end +$var wire 1 j$" out1 $end +$var wire 1 k$" outfinal $end +$upscope $end +$upscope $end +$scope begin muxbits[27] $end +$scope module ZeroMux $end +$var wire 1 l$" S0 $end +$var wire 1 m$" S1 $end +$var wire 1 n$" in0 $end +$var wire 1 o$" in1 $end +$var wire 1 p$" in2 $end +$var wire 1 q$" in3 $end +$var wire 1 r$" nS0 $end +$var wire 1 s$" nS1 $end +$var wire 1 t$" out $end +$var wire 1 u$" out0 $end +$var wire 1 v$" out1 $end +$var wire 1 w$" out2 $end +$var wire 1 x$" out3 $end +$upscope $end +$scope module OneMux $end +$var wire 1 y$" S0 $end +$var wire 1 z$" S1 $end +$var wire 1 {$" in0 $end +$var wire 1 |$" in1 $end +$var wire 1 }$" in2 $end +$var wire 1 ~$" in3 $end +$var wire 1 !%" nS0 $end +$var wire 1 "%" nS1 $end +$var wire 1 #%" out $end +$var wire 1 $%" out0 $end +$var wire 1 %%" out1 $end +$var wire 1 &%" out2 $end +$var wire 1 '%" out3 $end +$upscope $end +$scope module TwoMux $end +$var wire 1 (%" S $end +$var wire 1 )%" in0 $end +$var wire 1 *%" in1 $end +$var wire 1 +%" nS $end +$var wire 1 ,%" out0 $end +$var wire 1 -%" out1 $end +$var wire 1 .%" outfinal $end +$upscope $end +$upscope $end +$scope begin muxbits[28] $end +$scope module ZeroMux $end +$var wire 1 /%" S0 $end +$var wire 1 0%" S1 $end +$var wire 1 1%" in0 $end +$var wire 1 2%" in1 $end +$var wire 1 3%" in2 $end +$var wire 1 4%" in3 $end +$var wire 1 5%" nS0 $end +$var wire 1 6%" nS1 $end +$var wire 1 7%" out $end +$var wire 1 8%" out0 $end +$var wire 1 9%" out1 $end +$var wire 1 :%" out2 $end +$var wire 1 ;%" out3 $end +$upscope $end +$scope module OneMux $end +$var wire 1 <%" S0 $end +$var wire 1 =%" S1 $end +$var wire 1 >%" in0 $end +$var wire 1 ?%" in1 $end +$var wire 1 @%" in2 $end +$var wire 1 A%" in3 $end +$var wire 1 B%" nS0 $end +$var wire 1 C%" nS1 $end +$var wire 1 D%" out $end +$var wire 1 E%" out0 $end +$var wire 1 F%" out1 $end +$var wire 1 G%" out2 $end +$var wire 1 H%" out3 $end +$upscope $end +$scope module TwoMux $end +$var wire 1 I%" S $end +$var wire 1 J%" in0 $end +$var wire 1 K%" in1 $end +$var wire 1 L%" nS $end +$var wire 1 M%" out0 $end +$var wire 1 N%" out1 $end +$var wire 1 O%" outfinal $end +$upscope $end +$upscope $end +$scope begin muxbits[29] $end +$scope module ZeroMux $end +$var wire 1 P%" S0 $end +$var wire 1 Q%" S1 $end +$var wire 1 R%" in0 $end +$var wire 1 S%" in1 $end +$var wire 1 T%" in2 $end +$var wire 1 U%" in3 $end +$var wire 1 V%" nS0 $end +$var wire 1 W%" nS1 $end +$var wire 1 X%" out $end +$var wire 1 Y%" out0 $end +$var wire 1 Z%" out1 $end +$var wire 1 [%" out2 $end +$var wire 1 \%" out3 $end +$upscope $end +$scope module OneMux $end +$var wire 1 ]%" S0 $end +$var wire 1 ^%" S1 $end +$var wire 1 _%" in0 $end +$var wire 1 `%" in1 $end +$var wire 1 a%" in2 $end +$var wire 1 b%" in3 $end +$var wire 1 c%" nS0 $end +$var wire 1 d%" nS1 $end +$var wire 1 e%" out $end +$var wire 1 f%" out0 $end +$var wire 1 g%" out1 $end +$var wire 1 h%" out2 $end +$var wire 1 i%" out3 $end +$upscope $end +$scope module TwoMux $end +$var wire 1 j%" S $end +$var wire 1 k%" in0 $end +$var wire 1 l%" in1 $end +$var wire 1 m%" nS $end +$var wire 1 n%" out0 $end +$var wire 1 o%" out1 $end +$var wire 1 p%" outfinal $end +$upscope $end +$upscope $end +$scope begin muxbits[30] $end +$scope module ZeroMux $end +$var wire 1 q%" S0 $end +$var wire 1 r%" S1 $end +$var wire 1 s%" in0 $end +$var wire 1 t%" in1 $end +$var wire 1 u%" in2 $end +$var wire 1 v%" in3 $end +$var wire 1 w%" nS0 $end +$var wire 1 x%" nS1 $end +$var wire 1 y%" out $end +$var wire 1 z%" out0 $end +$var wire 1 {%" out1 $end +$var wire 1 |%" out2 $end +$var wire 1 }%" out3 $end +$upscope $end +$scope module OneMux $end +$var wire 1 ~%" S0 $end +$var wire 1 !&" S1 $end +$var wire 1 "&" in0 $end +$var wire 1 #&" in1 $end +$var wire 1 $&" in2 $end +$var wire 1 %&" in3 $end +$var wire 1 &&" nS0 $end +$var wire 1 '&" nS1 $end +$var wire 1 (&" out $end +$var wire 1 )&" out0 $end +$var wire 1 *&" out1 $end +$var wire 1 +&" out2 $end +$var wire 1 ,&" out3 $end +$upscope $end +$scope module TwoMux $end +$var wire 1 -&" S $end +$var wire 1 .&" in0 $end +$var wire 1 /&" in1 $end +$var wire 1 0&" nS $end +$var wire 1 1&" out0 $end +$var wire 1 2&" out1 $end +$var wire 1 3&" outfinal $end +$upscope $end +$upscope $end +$scope begin muxbits[31] $end +$scope module ZeroMux $end +$var wire 1 4&" S0 $end +$var wire 1 5&" S1 $end +$var wire 1 6&" in0 $end +$var wire 1 7&" in1 $end +$var wire 1 8&" in2 $end +$var wire 1 9&" in3 $end +$var wire 1 :&" nS0 $end +$var wire 1 ;&" nS1 $end +$var wire 1 <&" out $end +$var wire 1 =&" out0 $end +$var wire 1 >&" out1 $end +$var wire 1 ?&" out2 $end +$var wire 1 @&" out3 $end +$upscope $end +$scope module OneMux $end +$var wire 1 A&" S0 $end +$var wire 1 B&" S1 $end +$var wire 1 C&" in0 $end +$var wire 1 D&" in1 $end +$var wire 1 E&" in2 $end +$var wire 1 F&" in3 $end +$var wire 1 G&" nS0 $end +$var wire 1 H&" nS1 $end +$var wire 1 I&" out $end +$var wire 1 J&" out0 $end +$var wire 1 K&" out1 $end +$var wire 1 L&" out2 $end +$var wire 1 M&" out3 $end +$upscope $end +$scope module TwoMux $end +$var wire 1 N&" S $end +$var wire 1 O&" in0 $end +$var wire 1 P&" in1 $end +$var wire 1 Q&" nS $end +$var wire 1 R&" out0 $end +$var wire 1 S&" out1 $end +$var wire 1 T&" outfinal $end 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+#64150000 +b11000000000000000000000000000000 + +b11000000000000000000000000000000 p: +b11000000000000000000000000000000 d_ +#64170000 +b10000000000000000000000000000000 + +b10000000000000000000000000000000 p: +b10000000000000000000000000000000 d_ +#64190000 +b0 + +b0 p: +b0 d_ +#64200000 +1s: +1k_ +#64220000 1" -#62000000 +1# diff --git a/alu.v b/alu.v index 4f4e1fc..2eb50df 100644 --- a/alu.v +++ b/alu.v @@ -4,6 +4,107 @@ `define OR or #20 // nor with not is 20 `define NOR nor #10 // base is 10 `define XOR xor #40 // and with or is 40 + +module ALU +( +output[31:0] result, // OneBitFinalOut +output carryout, +output zero, //AllZeros +output overflow, +input[31:0] operandA, // A +input[31:0] operandB, // B +input[2:0] command //Command +); + // Your code here +/* +output [size-1:0] OneBitFinalOut, +output [size-1:0]AddSubSLTSum, +output [size-1:0]SLTSum, +output carryout, +output overflow, +output SLTflag, +output [size-1:0] OrNorXorOut, +output [size-1:0] AndNandOut, +output [size-1:0] subtract, +output [size-1:0] ZeroFlag, +output AllZeros, +input [size-1:0] A, +input [size-1:0] B, +input[2:0] Command, +input [size-1:0]carryin // don't think this does anything but don't want to break it! +); +*/ + parameter size = 32; + wire [size-1:0] Cmd0Start; + wire [size-1:0] Cmd1Start; + wire [size-1:0] CarryoutWire; + wire yeszero; + wire [size-1:0] NewVal; + wire [size-1:0] SLTSum; + wire [size-1:0] ZeroFlag; + wire [size-1:0] carryin; + wire [size-1:0] subtract; + wire SLTflag; + wire [size-1:0] AndNandOut; + wire [size-1:0] OrNorXorOut; + wire [size-1:0] AddSubSLTSum; + + SLT32 test(SLTSum, carryout, overflow, SLTflag, subtract, operandA, operandB, command, carryin); + AddSubSLT32 trial(AddSubSLTSum, carryout, overflow, subtract, operandA, operandB, command, carryin); + AndNand32 trial1(AndNandOut, operandA, operandB, command); + OrNorXor32 trial2(OrNorXorOut, operandA, operandB, command); + + FourInMux ZeroMux0case(Cmd0Start[0], command[0], command[1], AddSubSLTSum[0], AddSubSLTSum[0], OrNorXorOut[0], SLTSum[0]); + FourInMux OneMux0case(Cmd1Start[0], command[0], command[1], AndNandOut[0], AndNandOut[0], OrNorXorOut[0], OrNorXorOut[0]); + TwoInMux TwoMux0case(result[0], command[2], Cmd0Start[0], Cmd1Start[0]); + `AND setZerothZero(ZeroFlag[0], result[0], result[0]); + + genvar i; + generate + for (i=1; i; -v0xffc310_0 .var "A", 3 0; -RS_0x7f9963cefbe8/0/0 .resolv tri, L_0xffdb80, L_0xfff100, L_0x10005d0, L_0x1001bd0; -RS_0x7f9963cefbe8/0/4 .resolv tri, L_0x10267e0, L_0x1027d20, L_0x10291f0, L_0x102aaf0; -RS_0x7f9963cefbe8 .resolv tri, RS_0x7f9963cefbe8/0/0, RS_0x7f9963cefbe8/0/4, C4, C4; -v0xffc3b0_0 .net8 "AddSubSLTSum", 3 0, RS_0x7f9963cefbe8; 8 drivers -v0xffc430_0 .net "AllZeros", 0 0, L_0x1035f20; 1 drivers -RS_0x7f9963ceee38/0/0 .resolv tri, L_0x100d070, L_0x100db20, L_0x100e590, L_0x100eff0; -RS_0x7f9963ceee38/0/4 .resolv tri, L_0x102bbf0, L_0x102c660, L_0x102d0d0, L_0x102dc30; -RS_0x7f9963ceee38 .resolv tri, RS_0x7f9963ceee38/0/0, RS_0x7f9963ceee38/0/4, C4, C4; -v0xffc4b0_0 .net8 "AndNandOut", 3 0, RS_0x7f9963ceee38; 8 drivers -v0xffc560_0 .var "B", 3 0; -v0xffc5e0_0 .var "Command", 2 0; -RS_0x7f9963cf1868 .resolv tri, L_0x10160c0, L_0x1018a20, L_0x101b540, L_0x1035390; -v0xffc660_0 .net8 "OneBitFinalOut", 3 0, RS_0x7f9963cf1868; 4 drivers -RS_0x7f9963cee748/0/0 .resolv tri, L_0x10103b0, L_0x10116f0, L_0x10129f0, L_0x1013ce0; -RS_0x7f9963cee748/0/4 .resolv tri, L_0x1009490, L_0x1030990, L_0x1031c50, L_0x1032f40; -RS_0x7f9963cee748 .resolv tri, RS_0x7f9963cee748/0/0, RS_0x7f9963cee748/0/4, C4, C4; -v0xffc6e0_0 .net8 "OrNorXorOut", 3 0, RS_0x7f9963cee748; 8 drivers -RS_0x7f9963cf1538/0/0 .resolv tri, L_0x10045c0, L_0x10068d0, L_0x1008da0, L_0x100c6c0; -RS_0x7f9963cf1538/0/4 .resolv tri, L_0x101dbc0, L_0x101fdd0, L_0x1022050, L_0x1025660; -RS_0x7f9963cf1538 .resolv tri, RS_0x7f9963cf1538/0/0, RS_0x7f9963cf1538/0/4, C4, C4; -v0xffc760_0 .net8 "SLTSum", 3 0, RS_0x7f9963cf1538; 8 drivers -v0xffc7e0_0 .net "SLTflag", 0 0, L_0x10250b0; 1 drivers -v0xffc8f0_0 .net "SLTflag1", 0 0, L_0x100c180; 1 drivers -RS_0x7f9963cf1898 .resolv tri, L_0x1016570, L_0x1018ef0, L_0x101b680, L_0x1035650; -v0xffc970_0 .net8 "ZeroFlag", 3 0, RS_0x7f9963cf1898; 4 drivers -v0xffca90_0 .var "carryin", 3 0; -RS_0x7f9963cefd08 .resolv tri, L_0x1001f50, L_0x100adb0, L_0x1023e10, L_0x102ae70; -v0xffcb10_0 .net8 "carryout", 0 0, RS_0x7f9963cefd08; 4 drivers -RS_0x7f9963cefd38 .resolv tri, L_0x10023c0, L_0x100b770, L_0x1024700, L_0x1023db0; -v0xffcc10_0 .net8 "overflow", 0 0, RS_0x7f9963cefd38; 4 drivers -RS_0x7f9963cefd68/0/0 .resolv tri, L_0xffddc0, L_0xfff330, L_0x10007b0, L_0x1000c60; -RS_0x7f9963cefd68/0/4 .resolv tri, L_0x1003760, L_0x1005ac0, L_0x1006b60, L_0xff2320; -RS_0x7f9963cefd68/0/8 .resolv tri, L_0x101ccc0, L_0x101efd0, L_0x1020060, L_0x1022830; -RS_0x7f9963cefd68/0/12 .resolv tri, L_0x10269e0, L_0x1027f50, L_0x10294f0, L_0x1008250; -RS_0x7f9963cefd68 .resolv tri, RS_0x7f9963cefd68/0/0, RS_0x7f9963cefd68/0/4, RS_0x7f9963cefd68/0/8, RS_0x7f9963cefd68/0/12; -v0xffcc90_0 .net8 "subtract", 3 0, RS_0x7f9963cefd68; 16 drivers -S_0xff73e0 .scope module, "trial" "AddSubSLT32" 2 147, 3 166, S_0xeed190; - .timescale -9 -12; -P_0xff5ad8 .param/l "size" 3 180, +C4<0100>; -L_0x1001f50/d .functor OR 1, L_0x1002210, C4<0>, C4<0>, C4<0>; -L_0x1001f50 .delay (20000,20000,20000) L_0x1001f50/d; -L_0x10023c0/d .functor XOR 1, RS_0x7f9963cefd08, L_0x10024b0, C4<0>, C4<0>; -L_0x10023c0 .delay (40000,40000,40000) L_0x10023c0/d; -v0xffb8e0_0 .net "A", 3 0, v0xffc310_0; 1 drivers -v0xfe5a60_0 .alias "AddSubSLTSum", 3 0, v0xffc3b0_0; -v0xffba90_0 .net "B", 3 0, v0xffc560_0; 1 drivers -RS_0x7f9963cf5558 .resolv tri, L_0xffdcd0, L_0xfff1f0, L_0x10006c0, L_0x1001cc0; -v0xfe5cf0_0 .net8 "CarryoutWire", 3 0, RS_0x7f9963cf5558; 4 drivers -v0xffbc20_0 .net "Command", 2 0, v0xffc5e0_0; 1 drivers -v0xffbca0_0 .net *"_s40", 0 0, L_0x1002210; 1 drivers -v0xffbd40_0 .net/s *"_s41", 0 0, C4<0>; 1 drivers -v0xffbde0_0 .net *"_s44", 0 0, L_0x10024b0; 1 drivers -v0xffbed0_0 .net "carryin", 3 0, v0xffca90_0; 1 drivers -v0xffbfe0_0 .alias "carryout", 0 0, v0xffcb10_0; -v0xffc0f0_0 .alias "overflow", 0 0, v0xffcc10_0; -v0xffc200_0 .alias "subtract", 3 0, v0xffcc90_0; -L_0xffdb80 .part/pv L_0xffd670, 1, 1, 4; -L_0xffdcd0 .part/pv L_0xffda20, 1, 1, 4; -L_0xffddc0 .part/pv L_0xffd370, 1, 1, 4; -L_0xffdeb0 .part v0xffc310_0, 1, 1; -L_0xffdf50 .part v0xffc560_0, 1, 1; -L_0xffe080 .part RS_0x7f9963cf5558, 0, 1; -L_0xfff100 .part/pv L_0xffec50, 2, 1, 4; -L_0xfff1f0 .part/pv L_0xffefa0, 2, 1, 4; -L_0xfff330 .part/pv L_0xffe980, 2, 1, 4; -L_0xfff420 .part v0xffc310_0, 2, 1; -L_0xfff520 .part v0xffc560_0, 2, 1; -L_0xfff650 .part RS_0x7f9963cf5558, 1, 1; -L_0x10005d0 .part/pv L_0x1000120, 3, 1, 4; -L_0x10006c0 .part/pv L_0x1000470, 3, 1, 4; -L_0x10007b0 .part/pv L_0xfffe50, 3, 1, 4; -L_0x1000960 .part v0xffc310_0, 3, 1; -L_0x1000a90 .part v0xffc560_0, 3, 1; -L_0x1000bc0 .part RS_0x7f9963cf5558, 2, 1; -L_0x1001bd0 .part/pv L_0x1001720, 0, 1, 4; -L_0x1001cc0 .part/pv L_0x1001a70, 0, 1, 4; -L_0x1000c60 .part/pv L_0x1001450, 0, 1, 4; -L_0x1001eb0 .part v0xffc310_0, 0, 1; -L_0x1001db0 .part v0xffc560_0, 0, 1; -L_0x10020a0 .part RS_0x7f9963cefd68, 0, 1; -L_0x1002210 .part RS_0x7f9963cf5558, 3, 1; -L_0x10024b0 .part RS_0x7f9963cf5558, 2, 1; -S_0xffa8d0 .scope module, "attempt2" "MiddleAddSubSLT" 3 177, 3 88, S_0xff73e0; - .timescale -9 -12; -L_0x1000a00/d .functor NOT 1, L_0x1001db0, C4<0>, C4<0>, C4<0>; -L_0x1000a00 .delay (10000,10000,10000) L_0x1000a00/d; -L_0x10012f0/d .functor NOT 1, L_0x10013b0, C4<0>, C4<0>, C4<0>; -L_0x10012f0 .delay (10000,10000,10000) L_0x10012f0/d; -L_0x1001450/d .functor AND 1, L_0x1001590, L_0x10012f0, C4<1>, C4<1>; -L_0x1001450 .delay (20000,20000,20000) L_0x1001450/d; -L_0x1001630/d .functor XOR 1, L_0x1001eb0, L_0x1001080, C4<0>, C4<0>; -L_0x1001630 .delay (40000,40000,40000) L_0x1001630/d; -L_0x1001720/d .functor XOR 1, L_0x1001630, L_0x10020a0, C4<0>, C4<0>; -L_0x1001720 .delay (40000,40000,40000) L_0x1001720/d; -L_0x1001810/d .functor AND 1, L_0x1001eb0, L_0x1001080, C4<1>, C4<1>; -L_0x1001810 .delay (20000,20000,20000) L_0x1001810/d; -L_0x1001980/d .functor AND 1, L_0x1001630, L_0x10020a0, C4<1>, C4<1>; -L_0x1001980 .delay (20000,20000,20000) L_0x1001980/d; -L_0x1001a70/d .functor OR 1, L_0x1001810, L_0x1001980, C4<0>, C4<0>; -L_0x1001a70 .delay (20000,20000,20000) L_0x1001a70/d; -v0xffaf40_0 .net "A", 0 0, L_0x1001eb0; 1 drivers -v0xffb000_0 .net "AandB", 0 0, L_0x1001810; 1 drivers -v0xffb0a0_0 .net "AddSubSLTSum", 0 0, L_0x1001720; 1 drivers -v0xffb140_0 .net "AxorB", 0 0, L_0x1001630; 1 drivers -v0xffb1c0_0 .net "B", 0 0, L_0x1001db0; 1 drivers -v0xffb270_0 .net "BornB", 0 0, L_0x1001080; 1 drivers -v0xffb330_0 .net "CINandAxorB", 0 0, L_0x1001980; 1 drivers -v0xffb3b0_0 .alias "Command", 2 0, v0xffbc20_0; -v0xffb430_0 .net *"_s3", 0 0, L_0x10013b0; 1 drivers -v0xffb4b0_0 .net *"_s5", 0 0, L_0x1001590; 1 drivers -v0xffb550_0 .net "carryin", 0 0, L_0x10020a0; 1 drivers -v0xffb5f0_0 .net "carryout", 0 0, L_0x1001a70; 1 drivers -v0xffb690_0 .net "nB", 0 0, L_0x1000a00; 1 drivers -v0xffb740_0 .net "nCmd2", 0 0, L_0x10012f0; 1 drivers -v0xffb840_0 .net "subtract", 0 0, L_0x1001450; 1 drivers -L_0x1001250 .part v0xffc5e0_0, 0, 1; -L_0x10013b0 .part v0xffc5e0_0, 2, 1; -L_0x1001590 .part v0xffc5e0_0, 0, 1; -S_0xffa9c0 .scope module, "mux0" "TwoInMux" 3 104, 3 8, S_0xffa8d0; - .timescale -9 -12; -L_0x1000da0/d .functor NOT 1, L_0x1001250, C4<0>, C4<0>, C4<0>; -L_0x1000da0 .delay (10000,10000,10000) L_0x1000da0/d; -L_0x1000e60/d .functor AND 1, L_0x1001db0, L_0x1000da0, C4<1>, C4<1>; -L_0x1000e60 .delay (20000,20000,20000) L_0x1000e60/d; -L_0x1000f70/d .functor AND 1, L_0x1000a00, L_0x1001250, C4<1>, C4<1>; -L_0x1000f70 .delay (20000,20000,20000) L_0x1000f70/d; -L_0x1001080/d .functor OR 1, L_0x1000e60, L_0x1000f70, C4<0>, C4<0>; -L_0x1001080 .delay (20000,20000,20000) L_0x1001080/d; -v0xffaab0_0 .net "S", 0 0, L_0x1001250; 1 drivers -v0xffab70_0 .alias "in0", 0 0, v0xffb1c0_0; -v0xffac10_0 .alias "in1", 0 0, v0xffb690_0; -v0xffacb0_0 .net "nS", 0 0, L_0x1000da0; 1 drivers -v0xffad60_0 .net "out0", 0 0, L_0x1000e60; 1 drivers -v0xffae00_0 .net "out1", 0 0, L_0x1000f70; 1 drivers -v0xffaea0_0 .alias "outfinal", 0 0, v0xffb270_0; -S_0xff9730 .scope generate, "addbits[1]" "addbits[1]" 3 182, 3 182, S_0xff73e0; - .timescale -9 -12; -P_0xff9148 .param/l "i" 3 182, +C4<01>; -S_0xff98a0 .scope module, "attempt" "MiddleAddSubSLT" 3 184, 3 88, S_0xff9730; - .timescale -9 -12; -L_0xff4140/d .functor NOT 1, L_0xffdf50, C4<0>, C4<0>, C4<0>; -L_0xff4140 .delay (10000,10000,10000) L_0xff4140/d; -L_0xffd210/d .functor NOT 1, L_0xffd2d0, C4<0>, C4<0>, C4<0>; -L_0xffd210 .delay (10000,10000,10000) L_0xffd210/d; -L_0xffd370/d .functor AND 1, L_0xffd4b0, L_0xffd210, C4<1>, C4<1>; -L_0xffd370 .delay (20000,20000,20000) L_0xffd370/d; -L_0xffd550/d .functor XOR 1, L_0xffdeb0, L_0xffcff0, C4<0>, C4<0>; -L_0xffd550 .delay (40000,40000,40000) L_0xffd550/d; -L_0xffd670/d .functor XOR 1, L_0xffd550, L_0xffe080, C4<0>, C4<0>; -L_0xffd670 .delay (40000,40000,40000) L_0xffd670/d; -L_0xffd790/d .functor AND 1, L_0xffdeb0, L_0xffcff0, C4<1>, C4<1>; -L_0xffd790 .delay (20000,20000,20000) L_0xffd790/d; -L_0xffd930/d .functor AND 1, L_0xffd550, L_0xffe080, C4<1>, C4<1>; -L_0xffd930 .delay (20000,20000,20000) L_0xffd930/d; -L_0xffda20/d .functor OR 1, L_0xffd790, L_0xffd930, C4<0>, C4<0>; -L_0xffda20 .delay (20000,20000,20000) L_0xffda20/d; -v0xff9f30_0 .net "A", 0 0, L_0xffdeb0; 1 drivers -v0xff9ff0_0 .net "AandB", 0 0, L_0xffd790; 1 drivers -v0xffa090_0 .net "AddSubSLTSum", 0 0, L_0xffd670; 1 drivers -v0xffa130_0 .net "AxorB", 0 0, L_0xffd550; 1 drivers -v0xffa1b0_0 .net "B", 0 0, L_0xffdf50; 1 drivers -v0xffa260_0 .net "BornB", 0 0, L_0xffcff0; 1 drivers -v0xffa320_0 .net "CINandAxorB", 0 0, L_0xffd930; 1 drivers -v0xffa3a0_0 .alias "Command", 2 0, v0xffbc20_0; -v0xffa420_0 .net *"_s3", 0 0, L_0xffd2d0; 1 drivers -v0xffa4a0_0 .net *"_s5", 0 0, L_0xffd4b0; 1 drivers -v0xffa540_0 .net "carryin", 0 0, L_0xffe080; 1 drivers -v0xffa5e0_0 .net "carryout", 0 0, L_0xffda20; 1 drivers -v0xffa680_0 .net "nB", 0 0, L_0xff4140; 1 drivers -v0xffa730_0 .net "nCmd2", 0 0, L_0xffd210; 1 drivers -v0xffa830_0 .net "subtract", 0 0, L_0xffd370; 1 drivers -L_0xffd170 .part v0xffc5e0_0, 0, 1; -L_0xffd2d0 .part v0xffc5e0_0, 2, 1; -L_0xffd4b0 .part v0xffc5e0_0, 0, 1; -S_0xff9990 .scope module, "mux0" "TwoInMux" 3 104, 3 8, S_0xff98a0; - .timescale -9 -12; -L_0xffcda0/d .functor NOT 1, L_0xffd170, C4<0>, C4<0>, C4<0>; -L_0xffcda0 .delay (10000,10000,10000) L_0xffcda0/d; -L_0xffce40/d .functor AND 1, L_0xffdf50, L_0xffcda0, C4<1>, C4<1>; -L_0xffce40 .delay (20000,20000,20000) L_0xffce40/d; -L_0xffcf30/d .functor AND 1, L_0xff4140, L_0xffd170, C4<1>, C4<1>; -L_0xffcf30 .delay (20000,20000,20000) L_0xffcf30/d; -L_0xffcff0/d .functor OR 1, L_0xffce40, L_0xffcf30, C4<0>, C4<0>; -L_0xffcff0 .delay (20000,20000,20000) L_0xffcff0/d; -v0xff9a80_0 .net "S", 0 0, L_0xffd170; 1 drivers -v0xff9b20_0 .alias "in0", 0 0, v0xffa1b0_0; -v0xff9bc0_0 .alias "in1", 0 0, v0xffa680_0; -v0xff9c60_0 .net "nS", 0 0, L_0xffcda0; 1 drivers -v0xff9d10_0 .net "out0", 0 0, L_0xffce40; 1 drivers -v0xff9db0_0 .net "out1", 0 0, L_0xffcf30; 1 drivers -v0xff9e90_0 .alias "outfinal", 0 0, v0xffa260_0; -S_0xff8590 .scope generate, "addbits[2]" "addbits[2]" 3 182, 3 182, S_0xff73e0; - .timescale -9 -12; -P_0xff7f88 .param/l "i" 3 182, +C4<010>; -S_0xff8700 .scope module, "attempt" "MiddleAddSubSLT" 3 184, 3 88, S_0xff8590; - .timescale -9 -12; -L_0xffe120/d .functor NOT 1, L_0xfff520, C4<0>, C4<0>, C4<0>; -L_0xffe120 .delay (10000,10000,10000) L_0xffe120/d; -L_0xffe820/d .functor NOT 1, L_0xffe8e0, C4<0>, C4<0>, C4<0>; -L_0xffe820 .delay (10000,10000,10000) L_0xffe820/d; -L_0xffe980/d .functor AND 1, L_0xffeac0, L_0xffe820, C4<1>, C4<1>; -L_0xffe980 .delay (20000,20000,20000) L_0xffe980/d; -L_0xffeb60/d .functor XOR 1, L_0xfff420, L_0xffe5b0, C4<0>, C4<0>; -L_0xffeb60 .delay (40000,40000,40000) L_0xffeb60/d; -L_0xffec50/d .functor XOR 1, L_0xffeb60, L_0xfff650, C4<0>, C4<0>; -L_0xffec50 .delay (40000,40000,40000) L_0xffec50/d; -L_0xffed40/d .functor AND 1, L_0xfff420, L_0xffe5b0, C4<1>, C4<1>; -L_0xffed40 .delay (20000,20000,20000) L_0xffed40/d; -L_0xffeeb0/d .functor AND 1, L_0xffeb60, L_0xfff650, C4<1>, C4<1>; -L_0xffeeb0 .delay (20000,20000,20000) L_0xffeeb0/d; -L_0xffefa0/d .functor OR 1, L_0xffed40, L_0xffeeb0, C4<0>, C4<0>; -L_0xffefa0 .delay (20000,20000,20000) L_0xffefa0/d; -v0xff8d90_0 .net "A", 0 0, L_0xfff420; 1 drivers -v0xff8e50_0 .net "AandB", 0 0, L_0xffed40; 1 drivers -v0xff8ef0_0 .net "AddSubSLTSum", 0 0, L_0xffec50; 1 drivers -v0xff8f90_0 .net "AxorB", 0 0, L_0xffeb60; 1 drivers -v0xff9010_0 .net "B", 0 0, L_0xfff520; 1 drivers -v0xff90c0_0 .net "BornB", 0 0, L_0xffe5b0; 1 drivers -v0xff9180_0 .net "CINandAxorB", 0 0, L_0xffeeb0; 1 drivers -v0xff9200_0 .alias "Command", 2 0, v0xffbc20_0; -v0xff9280_0 .net *"_s3", 0 0, L_0xffe8e0; 1 drivers -v0xff9300_0 .net *"_s5", 0 0, L_0xffeac0; 1 drivers -v0xff93a0_0 .net "carryin", 0 0, L_0xfff650; 1 drivers -v0xff9440_0 .net "carryout", 0 0, L_0xffefa0; 1 drivers -v0xff94e0_0 .net "nB", 0 0, L_0xffe120; 1 drivers -v0xff9590_0 .net "nCmd2", 0 0, L_0xffe820; 1 drivers -v0xff9690_0 .net "subtract", 0 0, L_0xffe980; 1 drivers -L_0xffe780 .part v0xffc5e0_0, 0, 1; -L_0xffe8e0 .part v0xffc5e0_0, 2, 1; -L_0xffeac0 .part v0xffc5e0_0, 0, 1; -S_0xff87f0 .scope module, "mux0" "TwoInMux" 3 104, 3 8, S_0xff8700; - .timescale -9 -12; -L_0xffe2d0/d .functor NOT 1, L_0xffe780, C4<0>, C4<0>, C4<0>; -L_0xffe2d0 .delay (10000,10000,10000) L_0xffe2d0/d; -L_0xffe390/d .functor AND 1, L_0xfff520, L_0xffe2d0, C4<1>, C4<1>; -L_0xffe390 .delay (20000,20000,20000) L_0xffe390/d; -L_0xffe4a0/d .functor AND 1, L_0xffe120, L_0xffe780, C4<1>, C4<1>; -L_0xffe4a0 .delay (20000,20000,20000) L_0xffe4a0/d; -L_0xffe5b0/d .functor OR 1, L_0xffe390, L_0xffe4a0, C4<0>, C4<0>; -L_0xffe5b0 .delay (20000,20000,20000) L_0xffe5b0/d; -v0xff88e0_0 .net "S", 0 0, L_0xffe780; 1 drivers -v0xff8980_0 .alias "in0", 0 0, v0xff9010_0; -v0xff8a20_0 .alias "in1", 0 0, v0xff94e0_0; -v0xff8ac0_0 .net "nS", 0 0, L_0xffe2d0; 1 drivers -v0xff8b70_0 .net "out0", 0 0, L_0xffe390; 1 drivers -v0xff8c10_0 .net "out1", 0 0, L_0xffe4a0; 1 drivers -v0xff8cf0_0 .alias "outfinal", 0 0, v0xff90c0_0; -S_0xff74d0 .scope generate, "addbits[3]" "addbits[3]" 3 182, 3 182, S_0xff73e0; - .timescale -9 -12; -P_0xff71b8 .param/l "i" 3 182, +C4<011>; -S_0xff75c0 .scope module, "attempt" "MiddleAddSubSLT" 3 184, 3 88, S_0xff74d0; - .timescale -9 -12; -L_0xfff4c0/d .functor NOT 1, L_0x1000a90, C4<0>, C4<0>, C4<0>; -L_0xfff4c0 .delay (10000,10000,10000) L_0xfff4c0/d; -L_0xfffcf0/d .functor NOT 1, L_0xfffdb0, C4<0>, C4<0>, C4<0>; -L_0xfffcf0 .delay (10000,10000,10000) L_0xfffcf0/d; -L_0xfffe50/d .functor AND 1, L_0xffff90, L_0xfffcf0, C4<1>, C4<1>; -L_0xfffe50 .delay (20000,20000,20000) L_0xfffe50/d; -L_0x1000030/d .functor XOR 1, L_0x1000960, L_0xfffa80, C4<0>, C4<0>; -L_0x1000030 .delay (40000,40000,40000) L_0x1000030/d; -L_0x1000120/d .functor XOR 1, L_0x1000030, L_0x1000bc0, C4<0>, C4<0>; -L_0x1000120 .delay (40000,40000,40000) L_0x1000120/d; -L_0x1000210/d .functor AND 1, L_0x1000960, L_0xfffa80, C4<1>, C4<1>; -L_0x1000210 .delay (20000,20000,20000) L_0x1000210/d; -L_0x1000380/d .functor AND 1, L_0x1000030, L_0x1000bc0, C4<1>, C4<1>; -L_0x1000380 .delay (20000,20000,20000) L_0x1000380/d; -L_0x1000470/d .functor OR 1, L_0x1000210, L_0x1000380, C4<0>, C4<0>; -L_0x1000470 .delay (20000,20000,20000) L_0x1000470/d; -v0xff7c00_0 .net "A", 0 0, L_0x1000960; 1 drivers -v0xff7cc0_0 .net "AandB", 0 0, L_0x1000210; 1 drivers -v0xff7d60_0 .net "AddSubSLTSum", 0 0, L_0x1000120; 1 drivers -v0xff7e00_0 .net "AxorB", 0 0, L_0x1000030; 1 drivers -v0xff7e80_0 .net "B", 0 0, L_0x1000a90; 1 drivers -v0xff7f00_0 .net "BornB", 0 0, L_0xfffa80; 1 drivers -v0xff7fc0_0 .net "CINandAxorB", 0 0, L_0x1000380; 1 drivers -v0xff8040_0 .alias "Command", 2 0, v0xffbc20_0; -v0xff8110_0 .net *"_s3", 0 0, L_0xfffdb0; 1 drivers -v0xff8190_0 .net *"_s5", 0 0, L_0xffff90; 1 drivers -v0xff8230_0 .net "carryin", 0 0, L_0x1000bc0; 1 drivers -v0xff82d0_0 .net "carryout", 0 0, L_0x1000470; 1 drivers -v0xff8370_0 .net "nB", 0 0, L_0xfff4c0; 1 drivers -v0xff83f0_0 .net "nCmd2", 0 0, L_0xfffcf0; 1 drivers -v0xff84f0_0 .net "subtract", 0 0, L_0xfffe50; 1 drivers -L_0xfffc50 .part v0xffc5e0_0, 0, 1; -L_0xfffdb0 .part v0xffc5e0_0, 2, 1; -L_0xffff90 .part v0xffc5e0_0, 0, 1; -S_0xff76b0 .scope module, "mux0" "TwoInMux" 3 104, 3 8, S_0xff75c0; - .timescale -9 -12; -L_0xfff7e0/d .functor NOT 1, L_0xfffc50, C4<0>, C4<0>, C4<0>; -L_0xfff7e0 .delay (10000,10000,10000) L_0xfff7e0/d; -L_0xfff860/d .functor AND 1, L_0x1000a90, L_0xfff7e0, C4<1>, C4<1>; -L_0xfff860 .delay (20000,20000,20000) L_0xfff860/d; -L_0xfff970/d .functor AND 1, L_0xfff4c0, L_0xfffc50, C4<1>, C4<1>; -L_0xfff970 .delay (20000,20000,20000) L_0xfff970/d; -L_0xfffa80/d .functor OR 1, L_0xfff860, L_0xfff970, C4<0>, C4<0>; -L_0xfffa80 .delay (20000,20000,20000) L_0xfffa80/d; -v0xff77a0_0 .net "S", 0 0, L_0xfffc50; 1 drivers -v0xff7820_0 .alias "in0", 0 0, v0xff7e80_0; -v0xff78c0_0 .alias "in1", 0 0, v0xff8370_0; -v0xff7960_0 .net "nS", 0 0, L_0xfff7e0; 1 drivers -v0xff79e0_0 .net "out0", 0 0, L_0xfff860; 1 drivers -v0xff7a80_0 .net "out1", 0 0, L_0xfff970; 1 drivers -v0xff7b60_0 .alias "outfinal", 0 0, v0xff7f00_0; -S_0xfeeba0 .scope module, "test2" "SLT32" 2 149, 3 208, S_0xeed190; - .timescale -9 -12; -P_0xfeec98 .param/l "size" 3 238, +C4<0100>; -L_0x10062c0/d .functor NOT 1, L_0x10091e0, C4<0>, C4<0>, C4<0>; -L_0x10062c0 .delay (10000,10000,10000) L_0x10062c0/d; -L_0x1009040/d .functor AND 1, L_0x10093f0, L_0xff2230, L_0x10062c0, C4<1>; -L_0x1009040 .delay (20000,20000,20000) L_0x1009040/d; -L_0x100adb0/d .functor OR 1, L_0x100ae10, C4<0>, C4<0>, C4<0>; -L_0x100adb0 .delay (20000,20000,20000) L_0x100adb0/d; -L_0x100b770/d .functor XOR 1, RS_0x7f9963cefd08, L_0x100b860, C4<0>, C4<0>; -L_0x100b770 .delay (40000,40000,40000) L_0x100b770/d; -L_0x100b3e0/d .functor NOT 1, RS_0x7f9963cefd38, C4<0>, C4<0>, C4<0>; -L_0x100b3e0 .delay (10000,10000,10000) L_0x100b3e0/d; -L_0x100ba80/d .functor NOT 1, L_0x100bb60, C4<0>, C4<0>, C4<0>; -L_0x100ba80 .delay (10000,10000,10000) L_0x100ba80/d; -L_0x100bc00/d .functor AND 1, L_0x100b3e0, L_0x100bd40, C4<1>, C4<1>; -L_0x100bc00 .delay (20000,20000,20000) L_0x100bc00/d; -L_0x100b900/d .functor AND 1, RS_0x7f9963cefd38, L_0x100ba80, C4<1>, C4<1>; -L_0x100b900 .delay (20000,20000,20000) L_0x100b900/d; -L_0x100bf70/d .functor AND 1, L_0x100bc00, L_0x1009040, C4<1>, C4<1>; -L_0x100bf70 .delay (20000,20000,20000) L_0x100bf70/d; -L_0x100c070/d .functor AND 1, L_0x100b900, L_0x1009040, C4<1>, C4<1>; -L_0x100c070 .delay (20000,20000,20000) L_0x100c070/d; -L_0x100c180/d .functor OR 1, L_0x100bf70, L_0x100c070, C4<0>, C4<0>; -L_0x100c180 .delay (20000,20000,20000) L_0x100c180/d; -v0xff60c0_0 .alias "A", 3 0, v0xffb8e0_0; -RS_0x7f9963cf4478 .resolv tri, L_0x1003f40, L_0x1006220, L_0x10087b0, L_0x100b140; -v0xff6160_0 .net8 "AddSubSLTSum", 3 0, RS_0x7f9963cf4478; 4 drivers -v0xff6200_0 .alias "B", 3 0, v0xffba90_0; -RS_0x7f9963cf44a8 .resolv tri, L_0x1003670, L_0x10059d0, L_0x1007c60, L_0x100a8f0; -v0xff6280_0 .net8 "CarryoutWire", 3 0, RS_0x7f9963cf44a8; 4 drivers -v0xff6330_0 .alias "Command", 2 0, v0xffbc20_0; -RS_0x7f9963cf44d8 .resolv tri, L_0x1003580, L_0x10058e0, L_0x1007b70, L_0x100a800; -v0xff63b0_0 .net8 "NewVal", 3 0, RS_0x7f9963cf44d8; 4 drivers -v0xff6450_0 .net "Res0OF1", 0 0, L_0x100b900; 1 drivers -v0xff64f0_0 .net "Res1OF0", 0 0, L_0x100bc00; 1 drivers -v0xff6590_0 .alias "SLTSum", 3 0, v0xffc760_0; -v0xff6660_0 .alias "SLTflag", 0 0, v0xffc8f0_0; -v0xff66e0_0 .net "SLTflag0", 0 0, L_0x100bf70; 1 drivers -v0xff6780_0 .net "SLTflag1", 0 0, L_0x100c070; 1 drivers -v0xff6820_0 .net "SLTon", 0 0, L_0x1009040; 1 drivers -v0xff68a0_0 .net *"_s49", 0 0, L_0x10091e0; 1 drivers -v0xff69c0_0 .net *"_s51", 0 0, L_0x10093f0; 1 drivers -v0xff6a60_0 .net *"_s53", 0 0, L_0xff2230; 1 drivers -v0xff6920_0 .net *"_s73", 0 0, L_0x100ae10; 1 drivers -v0xff6bb0_0 .net/s *"_s74", 0 0, C4<0>; 1 drivers -v0xff6cd0_0 .net *"_s77", 0 0, L_0x100b860; 1 drivers -v0xff6d50_0 .net *"_s79", 0 0, L_0x100bb60; 1 drivers -v0xff6c30_0 .net *"_s81", 0 0, L_0x100bd40; 1 drivers -v0xff6e80_0 .alias "carryin", 3 0, v0xffbed0_0; -v0xff6dd0_0 .alias "carryout", 0 0, v0xffcb10_0; -v0xff6fc0_0 .net "nAddSubSLTSum", 0 0, L_0x100ba80; 1 drivers -v0xff6f00_0 .net "nCmd2", 0 0, L_0x10062c0; 1 drivers -v0xff7110_0 .net "nOF", 0 0, L_0x100b3e0; 1 drivers -v0xff7040_0 .alias "overflow", 0 0, v0xffcc10_0; -v0xff7270_0 .alias "subtract", 3 0, v0xffcc90_0; -L_0x1003580 .part/pv L_0x10030d0, 1, 1, 4; -L_0x1003670 .part/pv L_0x1003420, 1, 1, 4; -L_0x1003760 .part/pv L_0x1002e00, 1, 1, 4; -L_0x1003850 .part v0xffc310_0, 1, 1; -L_0x10038f0 .part v0xffc560_0, 1, 1; -L_0x1003a20 .part RS_0x7f9963cf44a8, 0, 1; -L_0x1003f40 .part/pv L_0x1003e00, 1, 1, 4; -L_0x1003fe0 .part RS_0x7f9963cf44d8, 1, 1; -L_0x10045c0 .part/pv L_0x1004460, 1, 1, 4; -L_0x10046f0 .part RS_0x7f9963cf4478, 1, 1; -L_0x1004840 .part RS_0x7f9963cf4478, 1, 1; -L_0x10058e0 .part/pv L_0x1005430, 2, 1, 4; -L_0x10059d0 .part/pv L_0x1005780, 2, 1, 4; -L_0x1005ac0 .part/pv L_0x1005160, 2, 1, 4; -L_0x1005bb0 .part v0xffc310_0, 2, 1; -L_0x1005c50 .part v0xffc560_0, 2, 1; -L_0x1005e10 .part RS_0x7f9963cf44a8, 1, 1; -L_0x1006220 .part/pv L_0x10060e0, 2, 1, 4; -L_0x10063f0 .part RS_0x7f9963cf44d8, 2, 1; -L_0x10068d0 .part/pv L_0x1006790, 2, 1, 4; -L_0x1006350 .part RS_0x7f9963cf4478, 2, 1; -L_0x1006a70 .part RS_0x7f9963cf4478, 2, 1; -L_0x1007b70 .part/pv L_0x10076c0, 3, 1, 4; -L_0x1007c60 .part/pv L_0x1007a10, 3, 1, 4; -L_0x1006b60 .part/pv L_0x10073f0, 3, 1, 4; -L_0x1007e70 .part v0xffc310_0, 3, 1; -L_0x1007d50 .part v0xffc560_0, 3, 1; -L_0xffbb10 .part RS_0x7f9963cf44a8, 2, 1; -L_0x10087b0 .part/pv L_0x1008670, 3, 1, 4; -L_0x1008850 .part RS_0x7f9963cf44d8, 3, 1; -L_0x1008da0 .part/pv L_0x1008c60, 3, 1, 4; -L_0x1008e40 .part RS_0x7f9963cf4478, 3, 1; -L_0x1008940 .part RS_0x7f9963cf4478, 3, 1; -L_0x10091e0 .part v0xffc5e0_0, 2, 1; -L_0x10093f0 .part v0xffc5e0_0, 0, 1; -L_0xff2230 .part v0xffc5e0_0, 1, 1; -L_0x100a800 .part/pv L_0x100a370, 0, 1, 4; -L_0x100a8f0 .part/pv L_0x100a6c0, 0, 1, 4; -L_0xff2320 .part/pv L_0x100a0a0, 0, 1, 4; -L_0x100ab20 .part v0xffc310_0, 0, 1; -L_0x100a9e0 .part v0xffc560_0, 0, 1; -L_0x100ad10 .part RS_0x7f9963cefd68, 0, 1; -L_0x100b140 .part/pv L_0x100b000, 0, 1, 4; -L_0x100b1e0 .part RS_0x7f9963cf44d8, 0, 1; -L_0x100ae10 .part RS_0x7f9963cf44a8, 3, 1; -L_0x100b860 .part RS_0x7f9963cf44a8, 2, 1; -L_0x100bb60 .part RS_0x7f9963cf4478, 3, 1; -L_0x100bd40 .part RS_0x7f9963cf44d8, 3, 1; -L_0x100c6c0 .part/pv L_0x100c560, 0, 1, 4; -L_0x100c760 .part RS_0x7f9963cf4478, 0, 1; -S_0xff50a0 .scope module, "attempt2" "MiddleAddSubSLT" 3 234, 3 88, S_0xfeeba0; - .timescale -9 -12; -L_0xffc9f0/d .functor NOT 1, L_0x100a9e0, C4<0>, C4<0>, C4<0>; -L_0xffc9f0 .delay (10000,10000,10000) L_0xffc9f0/d; -L_0x1009f60/d .functor NOT 1, L_0x100a000, C4<0>, C4<0>, C4<0>; -L_0x1009f60 .delay (10000,10000,10000) L_0x1009f60/d; -L_0x100a0a0/d .functor AND 1, L_0x100a1e0, L_0x1009f60, C4<1>, C4<1>; -L_0x100a0a0 .delay (20000,20000,20000) L_0x100a0a0/d; -L_0x100a280/d .functor XOR 1, L_0x100ab20, L_0x1009d30, C4<0>, C4<0>; -L_0x100a280 .delay (40000,40000,40000) L_0x100a280/d; -L_0x100a370/d .functor XOR 1, L_0x100a280, L_0x100ad10, C4<0>, C4<0>; -L_0x100a370 .delay (40000,40000,40000) L_0x100a370/d; -L_0x100a460/d .functor AND 1, L_0x100ab20, L_0x1009d30, C4<1>, C4<1>; -L_0x100a460 .delay (20000,20000,20000) L_0x100a460/d; -L_0x100a5d0/d .functor AND 1, L_0x100a280, L_0x100ad10, C4<1>, C4<1>; -L_0x100a5d0 .delay (20000,20000,20000) L_0x100a5d0/d; -L_0x100a6c0/d .functor OR 1, L_0x100a460, L_0x100a5d0, C4<0>, C4<0>; -L_0x100a6c0 .delay (20000,20000,20000) L_0x100a6c0/d; -v0xff5720_0 .net "A", 0 0, L_0x100ab20; 1 drivers -v0xff57e0_0 .net "AandB", 0 0, L_0x100a460; 1 drivers -v0xff5880_0 .net "AddSubSLTSum", 0 0, L_0x100a370; 1 drivers -v0xff5920_0 .net "AxorB", 0 0, L_0x100a280; 1 drivers -v0xff59a0_0 .net "B", 0 0, L_0x100a9e0; 1 drivers -v0xff5a50_0 .net "BornB", 0 0, L_0x1009d30; 1 drivers -v0xff5b10_0 .net "CINandAxorB", 0 0, L_0x100a5d0; 1 drivers -v0xff5b90_0 .alias "Command", 2 0, v0xffbc20_0; -v0xff5c10_0 .net *"_s3", 0 0, L_0x100a000; 1 drivers -v0xff5c90_0 .net *"_s5", 0 0, L_0x100a1e0; 1 drivers -v0xff5d30_0 .net "carryin", 0 0, L_0x100ad10; 1 drivers -v0xff5dd0_0 .net "carryout", 0 0, L_0x100a6c0; 1 drivers -v0xff5e70_0 .net "nB", 0 0, L_0xffc9f0; 1 drivers -v0xff5f20_0 .net "nCmd2", 0 0, L_0x1009f60; 1 drivers -v0xff6020_0 .net "subtract", 0 0, L_0x100a0a0; 1 drivers -L_0x1009ec0 .part v0xffc5e0_0, 0, 1; -L_0x100a000 .part v0xffc5e0_0, 2, 1; -L_0x100a1e0 .part v0xffc5e0_0, 0, 1; -S_0xff5190 .scope module, "mux0" "TwoInMux" 3 104, 3 8, S_0xff50a0; - .timescale -9 -12; -L_0xff2450/d .functor NOT 1, L_0x1009ec0, C4<0>, C4<0>, C4<0>; -L_0xff2450 .delay (10000,10000,10000) L_0xff2450/d; -L_0xff24d0/d .functor AND 1, L_0x100a9e0, L_0xff2450, C4<1>, C4<1>; -L_0xff24d0 .delay (20000,20000,20000) L_0xff24d0/d; -L_0xff25e0/d .functor AND 1, L_0xffc9f0, L_0x1009ec0, C4<1>, C4<1>; -L_0xff25e0 .delay (20000,20000,20000) L_0xff25e0/d; -L_0x1009d30/d .functor OR 1, L_0xff24d0, L_0xff25e0, C4<0>, C4<0>; -L_0x1009d30 .delay (20000,20000,20000) L_0x1009d30/d; -v0xff5280_0 .net "S", 0 0, L_0x1009ec0; 1 drivers -v0xff5340_0 .alias "in0", 0 0, v0xff59a0_0; -v0xff53e0_0 .alias "in1", 0 0, v0xff5e70_0; -v0xff5480_0 .net "nS", 0 0, L_0xff2450; 1 drivers -v0xff5500_0 .net "out0", 0 0, L_0xff24d0; 1 drivers -v0xff55a0_0 .net "out1", 0 0, L_0xff25e0; 1 drivers -v0xff5680_0 .alias "outfinal", 0 0, v0xff5a50_0; -S_0xff4b30 .scope module, "setSLTresult" "TwoInMux" 3 235, 3 8, S_0xfeeba0; - .timescale -9 -12; -L_0x100abc0/d .functor NOT 1, L_0x1009040, C4<0>, C4<0>, C4<0>; -L_0x100abc0 .delay (10000,10000,10000) L_0x100abc0/d; -L_0x100ac60/d .functor AND 1, L_0x100b1e0, L_0x100abc0, C4<1>, C4<1>; -L_0x100ac60 .delay (20000,20000,20000) L_0x100ac60/d; -L_0x100af60/d .functor AND 1, C4<0>, L_0x1009040, C4<1>, C4<1>; -L_0x100af60 .delay (20000,20000,20000) L_0x100af60/d; -L_0x100b000/d .functor OR 1, L_0x100ac60, L_0x100af60, C4<0>, C4<0>; -L_0x100b000 .delay (20000,20000,20000) L_0x100b000/d; -v0xff4c20_0 .alias "S", 0 0, v0xff6820_0; -v0xff4cc0_0 .net "in0", 0 0, L_0x100b1e0; 1 drivers -v0xff4d60_0 .net "in1", 0 0, C4<0>; 1 drivers -v0xff4e00_0 .net "nS", 0 0, L_0x100abc0; 1 drivers -v0xff4e80_0 .net "out0", 0 0, L_0x100ac60; 1 drivers -v0xff4f20_0 .net "out1", 0 0, L_0x100af60; 1 drivers -v0xff5000_0 .net "outfinal", 0 0, L_0x100b000; 1 drivers -S_0xff45c0 .scope module, "FinalSLT" "TwoInMux" 3 261, 3 8, S_0xfeeba0; - .timescale -9 -12; -L_0x100c2d0/d .functor NOT 1, L_0x100c180, C4<0>, C4<0>, C4<0>; -L_0x100c2d0 .delay (10000,10000,10000) L_0x100c2d0/d; -L_0x100c3b0/d .functor AND 1, L_0x100c760, L_0x100c2d0, C4<1>, C4<1>; -L_0x100c3b0 .delay (20000,20000,20000) L_0x100c3b0/d; -L_0x100c4c0/d .functor AND 1, L_0x100c180, L_0x100c180, C4<1>, C4<1>; -L_0x100c4c0 .delay (20000,20000,20000) L_0x100c4c0/d; -L_0x100c560/d .functor OR 1, L_0x100c3b0, L_0x100c4c0, C4<0>, C4<0>; -L_0x100c560 .delay (20000,20000,20000) L_0x100c560/d; -v0xff46b0_0 .alias "S", 0 0, v0xffc8f0_0; -v0xff4770_0 .net "in0", 0 0, L_0x100c760; 1 drivers -v0xff4810_0 .alias "in1", 0 0, v0xffc8f0_0; -v0xff48c0_0 .net "nS", 0 0, L_0x100c2d0; 1 drivers -v0xff4970_0 .net "out0", 0 0, L_0x100c3b0; 1 drivers -v0xff49f0_0 .net "out1", 0 0, L_0x100c4c0; 1 drivers -v0xff4a90_0 .net "outfinal", 0 0, L_0x100c560; 1 drivers -S_0xff28c0 .scope generate, "sltbits[1]" "sltbits[1]" 3 240, 3 240, S_0xfeeba0; - .timescale -9 -12; -P_0xff29b8 .param/l "i" 3 240, +C4<01>; -S_0xff34b0 .scope module, "attempt" "MiddleAddSubSLT" 3 242, 3 88, S_0xff28c0; - .timescale -9 -12; -L_0x1002140/d .functor NOT 1, L_0x10038f0, C4<0>, C4<0>, C4<0>; -L_0x1002140 .delay (10000,10000,10000) L_0x1002140/d; -L_0x1002ca0/d .functor NOT 1, L_0x1002d60, C4<0>, C4<0>, C4<0>; -L_0x1002ca0 .delay (10000,10000,10000) L_0x1002ca0/d; -L_0x1002e00/d .functor AND 1, L_0x1002f40, L_0x1002ca0, C4<1>, C4<1>; -L_0x1002e00 .delay (20000,20000,20000) L_0x1002e00/d; -L_0x1002fe0/d .functor XOR 1, L_0x1003850, L_0x1002a30, C4<0>, C4<0>; -L_0x1002fe0 .delay (40000,40000,40000) L_0x1002fe0/d; -L_0x10030d0/d .functor XOR 1, L_0x1002fe0, L_0x1003a20, C4<0>, C4<0>; -L_0x10030d0 .delay (40000,40000,40000) L_0x10030d0/d; -L_0x10031c0/d .functor AND 1, L_0x1003850, L_0x1002a30, C4<1>, C4<1>; -L_0x10031c0 .delay (20000,20000,20000) L_0x10031c0/d; -L_0x1003330/d .functor AND 1, L_0x1002fe0, L_0x1003a20, C4<1>, C4<1>; -L_0x1003330 .delay (20000,20000,20000) L_0x1003330/d; -L_0x1003420/d .functor OR 1, L_0x10031c0, L_0x1003330, C4<0>, C4<0>; -L_0x1003420 .delay (20000,20000,20000) L_0x1003420/d; -v0xff3b30_0 .net "A", 0 0, L_0x1003850; 1 drivers -v0xff3bf0_0 .net "AandB", 0 0, L_0x10031c0; 1 drivers -v0xff3c90_0 .net "AddSubSLTSum", 0 0, L_0x10030d0; 1 drivers -v0xff3d30_0 .net "AxorB", 0 0, L_0x1002fe0; 1 drivers -v0xff3db0_0 .net "B", 0 0, L_0x10038f0; 1 drivers -v0xff3e30_0 .net "BornB", 0 0, L_0x1002a30; 1 drivers -v0xff3ef0_0 .net "CINandAxorB", 0 0, L_0x1003330; 1 drivers -v0xff3f70_0 .alias "Command", 2 0, v0xffbc20_0; -v0xff4040_0 .net *"_s3", 0 0, L_0x1002d60; 1 drivers -v0xff40c0_0 .net *"_s5", 0 0, L_0x1002f40; 1 drivers -v0xff41c0_0 .net "carryin", 0 0, L_0x1003a20; 1 drivers -v0xff4260_0 .net "carryout", 0 0, L_0x1003420; 1 drivers -v0xff4370_0 .net "nB", 0 0, L_0x1002140; 1 drivers -v0xff4420_0 .net "nCmd2", 0 0, L_0x1002ca0; 1 drivers -v0xff4520_0 .net "subtract", 0 0, L_0x1002e00; 1 drivers -L_0x1002c00 .part v0xffc5e0_0, 0, 1; -L_0x1002d60 .part v0xffc5e0_0, 2, 1; -L_0x1002f40 .part v0xffc5e0_0, 0, 1; -S_0xff35a0 .scope module, "mux0" "TwoInMux" 3 104, 3 8, S_0xff34b0; - .timescale -9 -12; -L_0x1002750/d .functor NOT 1, L_0x1002c00, C4<0>, C4<0>, C4<0>; -L_0x1002750 .delay (10000,10000,10000) L_0x1002750/d; -L_0x1002810/d .functor AND 1, L_0x10038f0, L_0x1002750, C4<1>, C4<1>; -L_0x1002810 .delay (20000,20000,20000) L_0x1002810/d; -L_0x1002920/d .functor AND 1, L_0x1002140, L_0x1002c00, C4<1>, C4<1>; -L_0x1002920 .delay (20000,20000,20000) L_0x1002920/d; -L_0x1002a30/d .functor OR 1, L_0x1002810, L_0x1002920, C4<0>, C4<0>; -L_0x1002a30 .delay (20000,20000,20000) L_0x1002a30/d; -v0xff3690_0 .net "S", 0 0, L_0x1002c00; 1 drivers -v0xff3730_0 .alias "in0", 0 0, v0xff3db0_0; -v0xff37d0_0 .alias "in1", 0 0, v0xff4370_0; -v0xff3870_0 .net "nS", 0 0, L_0x1002750; 1 drivers -v0xff3910_0 .net "out0", 0 0, L_0x1002810; 1 drivers -v0xff39b0_0 .net "out1", 0 0, L_0x1002920; 1 drivers -v0xff3a90_0 .alias "outfinal", 0 0, v0xff3e30_0; -S_0xff3040 .scope module, "setSLTres2" "TwoInMux" 3 243, 3 8, S_0xff28c0; - .timescale -9 -12; -L_0x1003ac0/d .functor NOT 1, L_0x1009040, C4<0>, C4<0>, C4<0>; -L_0x1003ac0 .delay (10000,10000,10000) L_0x1003ac0/d; -L_0x1003c30/d .functor AND 1, L_0x1003fe0, L_0x1003ac0, C4<1>, C4<1>; -L_0x1003c30 .delay (20000,20000,20000) L_0x1003c30/d; -L_0x1003d40/d .functor AND 1, C4<0>, L_0x1009040, C4<1>, C4<1>; -L_0x1003d40 .delay (20000,20000,20000) L_0x1003d40/d; -L_0x1003e00/d .functor OR 1, L_0x1003c30, L_0x1003d40, C4<0>, C4<0>; -L_0x1003e00 .delay (20000,20000,20000) L_0x1003e00/d; -v0xff3130_0 .alias "S", 0 0, v0xff6820_0; -v0xff31b0_0 .net "in0", 0 0, L_0x1003fe0; 1 drivers -v0xff3230_0 .net "in1", 0 0, C4<0>; 1 drivers -v0xff32b0_0 .net "nS", 0 0, L_0x1003ac0; 1 drivers -v0xff3330_0 .net "out0", 0 0, L_0x1003c30; 1 drivers -v0xff33b0_0 .net "out1", 0 0, L_0x1003d40; 1 drivers -v0xff3430_0 .net "outfinal", 0 0, L_0x1003e00; 1 drivers -S_0xff2a50 .scope module, "setSLTres3" "TwoInMux" 3 244, 3 8, S_0xff28c0; - .timescale -9 -12; -L_0x10041c0/d .functor NOT 1, L_0x1009040, C4<0>, C4<0>, C4<0>; -L_0x10041c0 .delay (10000,10000,10000) L_0x10041c0/d; -L_0x10042b0/d .functor AND 1, L_0x10046f0, L_0x10041c0, C4<1>, C4<1>; -L_0x10042b0 .delay (20000,20000,20000) L_0x10042b0/d; -L_0x10043c0/d .functor AND 1, L_0x1004840, L_0x1009040, C4<1>, C4<1>; -L_0x10043c0 .delay (20000,20000,20000) L_0x10043c0/d; -L_0x1004460/d .functor OR 1, L_0x10042b0, L_0x10043c0, C4<0>, C4<0>; -L_0x1004460 .delay (20000,20000,20000) L_0x1004460/d; -v0xff2b40_0 .alias "S", 0 0, v0xff6820_0; -v0xff2c50_0 .net "in0", 0 0, L_0x10046f0; 1 drivers -v0xff2cf0_0 .net "in1", 0 0, L_0x1004840; 1 drivers -v0xff2d90_0 .net "nS", 0 0, L_0x10041c0; 1 drivers -v0xff2e40_0 .net "out0", 0 0, L_0x10042b0; 1 drivers -v0xff2ee0_0 .net "out1", 0 0, L_0x10043c0; 1 drivers -v0xff2fc0_0 .net "outfinal", 0 0, L_0x1004460; 1 drivers -S_0xff0a40 .scope generate, "sltbits[2]" "sltbits[2]" 3 240, 3 240, S_0xfeeba0; - .timescale -9 -12; -P_0xff03a8 .param/l "i" 3 240, +C4<010>; -S_0xff1670 .scope module, "attempt" "MiddleAddSubSLT" 3 242, 3 88, S_0xff0a40; - .timescale -9 -12; -L_0x10048e0/d .functor NOT 1, L_0x1005c50, C4<0>, C4<0>, C4<0>; -L_0x10048e0 .delay (10000,10000,10000) L_0x10048e0/d; -L_0x1005000/d .functor NOT 1, L_0x10050c0, C4<0>, C4<0>, C4<0>; -L_0x1005000 .delay (10000,10000,10000) L_0x1005000/d; -L_0x1005160/d .functor AND 1, L_0x10052a0, L_0x1005000, C4<1>, C4<1>; -L_0x1005160 .delay (20000,20000,20000) L_0x1005160/d; -L_0x1005340/d .functor XOR 1, L_0x1005bb0, L_0x1004d90, C4<0>, C4<0>; -L_0x1005340 .delay (40000,40000,40000) L_0x1005340/d; -L_0x1005430/d .functor XOR 1, L_0x1005340, L_0x1005e10, C4<0>, C4<0>; -L_0x1005430 .delay (40000,40000,40000) L_0x1005430/d; -L_0x1005520/d .functor AND 1, L_0x1005bb0, L_0x1004d90, C4<1>, C4<1>; -L_0x1005520 .delay (20000,20000,20000) L_0x1005520/d; -L_0x1005690/d .functor AND 1, L_0x1005340, L_0x1005e10, C4<1>, C4<1>; -L_0x1005690 .delay (20000,20000,20000) L_0x1005690/d; -L_0x1005780/d .functor OR 1, L_0x1005520, L_0x1005690, C4<0>, C4<0>; -L_0x1005780 .delay (20000,20000,20000) L_0x1005780/d; -v0xff1cf0_0 .net "A", 0 0, L_0x1005bb0; 1 drivers -v0xff1db0_0 .net "AandB", 0 0, L_0x1005520; 1 drivers -v0xff1e50_0 .net "AddSubSLTSum", 0 0, L_0x1005430; 1 drivers -v0xff1ef0_0 .net "AxorB", 0 0, L_0x1005340; 1 drivers -v0xff1f70_0 .net "B", 0 0, L_0x1005c50; 1 drivers -v0xff2020_0 .net "BornB", 0 0, L_0x1004d90; 1 drivers -v0xff20e0_0 .net "CINandAxorB", 0 0, L_0x1005690; 1 drivers -v0xff2160_0 .alias "Command", 2 0, v0xffbc20_0; -v0xfe09a0_0 .net *"_s3", 0 0, L_0x10050c0; 1 drivers -v0xfe0a20_0 .net *"_s5", 0 0, L_0x10052a0; 1 drivers -v0xfe0ac0_0 .net "carryin", 0 0, L_0x1005e10; 1 drivers -v0xff2640_0 .net "carryout", 0 0, L_0x1005780; 1 drivers -v0xff26c0_0 .net "nB", 0 0, L_0x10048e0; 1 drivers -v0xff2740_0 .net "nCmd2", 0 0, L_0x1005000; 1 drivers -v0xff2840_0 .net "subtract", 0 0, L_0x1005160; 1 drivers -L_0x1004f60 .part v0xffc5e0_0, 0, 1; -L_0x10050c0 .part v0xffc5e0_0, 2, 1; -L_0x10052a0 .part v0xffc5e0_0, 0, 1; -S_0xff1760 .scope module, "mux0" "TwoInMux" 3 104, 3 8, S_0xff1670; - .timescale -9 -12; -L_0x1004ab0/d .functor NOT 1, L_0x1004f60, C4<0>, C4<0>, C4<0>; -L_0x1004ab0 .delay (10000,10000,10000) L_0x1004ab0/d; -L_0x1004b70/d .functor AND 1, L_0x1005c50, L_0x1004ab0, C4<1>, C4<1>; -L_0x1004b70 .delay (20000,20000,20000) L_0x1004b70/d; -L_0x1004c80/d .functor AND 1, L_0x10048e0, L_0x1004f60, C4<1>, C4<1>; -L_0x1004c80 .delay (20000,20000,20000) L_0x1004c80/d; -L_0x1004d90/d .functor OR 1, L_0x1004b70, L_0x1004c80, C4<0>, C4<0>; -L_0x1004d90 .delay (20000,20000,20000) L_0x1004d90/d; -v0xff1850_0 .net "S", 0 0, L_0x1004f60; 1 drivers -v0xff1910_0 .alias "in0", 0 0, v0xff1f70_0; -v0xff19b0_0 .alias "in1", 0 0, v0xff26c0_0; -v0xff1a50_0 .net "nS", 0 0, L_0x1004ab0; 1 drivers -v0xff1ad0_0 .net "out0", 0 0, L_0x1004b70; 1 drivers -v0xff1b70_0 .net "out1", 0 0, L_0x1004c80; 1 drivers -v0xff1c50_0 .alias "outfinal", 0 0, v0xff2020_0; -S_0xff1100 .scope module, "setSLTres2" "TwoInMux" 3 243, 3 8, S_0xff0a40; - .timescale -9 -12; -L_0x10047e0/d .functor NOT 1, L_0x1009040, C4<0>, C4<0>, C4<0>; -L_0x10047e0 .delay (10000,10000,10000) L_0x10047e0/d; -L_0x1005f80/d .functor AND 1, L_0x10063f0, L_0x10047e0, C4<1>, C4<1>; -L_0x1005f80 .delay (20000,20000,20000) L_0x1005f80/d; -L_0x1006040/d .functor AND 1, C4<0>, L_0x1009040, C4<1>, C4<1>; -L_0x1006040 .delay (20000,20000,20000) L_0x1006040/d; -L_0x10060e0/d .functor OR 1, L_0x1005f80, L_0x1006040, C4<0>, C4<0>; -L_0x10060e0 .delay (20000,20000,20000) L_0x10060e0/d; -v0xff11f0_0 .alias "S", 0 0, v0xff6820_0; -v0xff1290_0 .net "in0", 0 0, L_0x10063f0; 1 drivers -v0xff1330_0 .net "in1", 0 0, C4<0>; 1 drivers -v0xff13d0_0 .net "nS", 0 0, L_0x10047e0; 1 drivers -v0xff1450_0 .net "out0", 0 0, L_0x1005f80; 1 drivers -v0xff14f0_0 .net "out1", 0 0, L_0x1006040; 1 drivers -v0xff15d0_0 .net "outfinal", 0 0, L_0x10060e0; 1 drivers -S_0xff0bb0 .scope module, "setSLTres3" "TwoInMux" 3 244, 3 8, S_0xff0a40; - .timescale -9 -12; -L_0x10064d0/d .functor NOT 1, L_0x1009040, C4<0>, C4<0>, C4<0>; -L_0x10064d0 .delay (10000,10000,10000) L_0x10064d0/d; -L_0x10065e0/d .functor AND 1, L_0x1006350, L_0x10064d0, C4<1>, C4<1>; -L_0x10065e0 .delay (20000,20000,20000) L_0x10065e0/d; -L_0x10066f0/d .functor AND 1, L_0x1006a70, L_0x1009040, C4<1>, C4<1>; -L_0x10066f0 .delay (20000,20000,20000) L_0x10066f0/d; -L_0x1006790/d .functor OR 1, L_0x10065e0, L_0x10066f0, C4<0>, C4<0>; -L_0x1006790 .delay (20000,20000,20000) L_0x1006790/d; -v0xff0ca0_0 .alias "S", 0 0, v0xff6820_0; -v0xff0d20_0 .net "in0", 0 0, L_0x1006350; 1 drivers -v0xff0dc0_0 .net "in1", 0 0, L_0x1006a70; 1 drivers -v0xff0e60_0 .net "nS", 0 0, L_0x10064d0; 1 drivers -v0xff0ee0_0 .net "out0", 0 0, L_0x10065e0; 1 drivers -v0xff0f80_0 .net "out1", 0 0, L_0x10066f0; 1 drivers -v0xff1060_0 .net "outfinal", 0 0, L_0x1006790; 1 drivers -S_0xfeed10 .scope generate, "sltbits[3]" "sltbits[3]" 3 240, 3 240, S_0xfeeba0; - .timescale -9 -12; -P_0xfeee08 .param/l "i" 3 240, +C4<011>; -S_0xfef970 .scope module, "attempt" "MiddleAddSubSLT" 3 242, 3 88, S_0xfeed10; - .timescale -9 -12; -L_0x1006970/d .functor NOT 1, L_0x1007d50, C4<0>, C4<0>, C4<0>; -L_0x1006970 .delay (10000,10000,10000) L_0x1006970/d; -L_0x1007290/d .functor NOT 1, L_0x1007350, C4<0>, C4<0>, C4<0>; -L_0x1007290 .delay (10000,10000,10000) L_0x1007290/d; -L_0x10073f0/d .functor AND 1, L_0x1007530, L_0x1007290, C4<1>, C4<1>; -L_0x10073f0 .delay (20000,20000,20000) L_0x10073f0/d; -L_0x10075d0/d .functor XOR 1, L_0x1007e70, L_0x1007020, C4<0>, C4<0>; -L_0x10075d0 .delay (40000,40000,40000) L_0x10075d0/d; -L_0x10076c0/d .functor XOR 1, L_0x10075d0, L_0xffbb10, C4<0>, C4<0>; -L_0x10076c0 .delay (40000,40000,40000) L_0x10076c0/d; -L_0x10077b0/d .functor AND 1, L_0x1007e70, L_0x1007020, C4<1>, C4<1>; -L_0x10077b0 .delay (20000,20000,20000) L_0x10077b0/d; -L_0x1007920/d .functor AND 1, L_0x10075d0, L_0xffbb10, C4<1>, C4<1>; -L_0x1007920 .delay (20000,20000,20000) L_0x1007920/d; -L_0x1007a10/d .functor OR 1, L_0x10077b0, L_0x1007920, C4<0>, C4<0>; -L_0x1007a10 .delay (20000,20000,20000) L_0x1007a10/d; -v0xfefff0_0 .net "A", 0 0, L_0x1007e70; 1 drivers -v0xff00b0_0 .net "AandB", 0 0, L_0x10077b0; 1 drivers -v0xff0150_0 .net "AddSubSLTSum", 0 0, L_0x10076c0; 1 drivers -v0xff01f0_0 .net "AxorB", 0 0, L_0x10075d0; 1 drivers -v0xff0270_0 .net "B", 0 0, L_0x1007d50; 1 drivers -v0xff0320_0 .net "BornB", 0 0, L_0x1007020; 1 drivers -v0xff03e0_0 .net "CINandAxorB", 0 0, L_0x1007920; 1 drivers -v0xff0460_0 .alias "Command", 2 0, v0xffbc20_0; -v0xff0530_0 .net *"_s3", 0 0, L_0x1007350; 1 drivers -v0xff05b0_0 .net *"_s5", 0 0, L_0x1007530; 1 drivers -v0xff06b0_0 .net "carryin", 0 0, L_0xffbb10; 1 drivers -v0xff0750_0 .net "carryout", 0 0, L_0x1007a10; 1 drivers -v0xff07f0_0 .net "nB", 0 0, L_0x1006970; 1 drivers -v0xff08a0_0 .net "nCmd2", 0 0, L_0x1007290; 1 drivers -v0xff09a0_0 .net "subtract", 0 0, L_0x10073f0; 1 drivers -L_0x10071f0 .part v0xffc5e0_0, 0, 1; -L_0x1007350 .part v0xffc5e0_0, 2, 1; -L_0x1007530 .part v0xffc5e0_0, 0, 1; -S_0xfefa60 .scope module, "mux0" "TwoInMux" 3 104, 3 8, S_0xfef970; - .timescale -9 -12; -L_0x1006d40/d .functor NOT 1, L_0x10071f0, C4<0>, C4<0>, C4<0>; -L_0x1006d40 .delay (10000,10000,10000) L_0x1006d40/d; -L_0x1006e00/d .functor AND 1, L_0x1007d50, L_0x1006d40, C4<1>, C4<1>; -L_0x1006e00 .delay (20000,20000,20000) L_0x1006e00/d; -L_0x1006f10/d .functor AND 1, L_0x1006970, L_0x10071f0, C4<1>, C4<1>; -L_0x1006f10 .delay (20000,20000,20000) L_0x1006f10/d; -L_0x1007020/d .functor OR 1, L_0x1006e00, L_0x1006f10, C4<0>, C4<0>; -L_0x1007020 .delay (20000,20000,20000) L_0x1007020/d; -v0xfefb50_0 .net "S", 0 0, L_0x10071f0; 1 drivers -v0xfefc10_0 .alias "in0", 0 0, v0xff0270_0; -v0xfefcb0_0 .alias "in1", 0 0, v0xff07f0_0; -v0xfefd50_0 .net "nS", 0 0, L_0x1006d40; 1 drivers -v0xfefdd0_0 .net "out0", 0 0, L_0x1006e00; 1 drivers -v0xfefe70_0 .net "out1", 0 0, L_0x1006f10; 1 drivers -v0xfeff50_0 .alias "outfinal", 0 0, v0xff0320_0; -S_0xfef3f0 .scope module, "setSLTres2" "TwoInMux" 3 243, 3 8, S_0xfeed10; - .timescale -9 -12; -L_0xffbbb0/d .functor NOT 1, L_0x1009040, C4<0>, C4<0>, C4<0>; -L_0xffbbb0 .delay (10000,10000,10000) L_0xffbbb0/d; -L_0x1003b20/d .functor AND 1, L_0x1008850, L_0xffbbb0, C4<1>, C4<1>; -L_0x1003b20 .delay (20000,20000,20000) L_0x1003b20/d; -L_0x10085d0/d .functor AND 1, C4<0>, L_0x1009040, C4<1>, C4<1>; -L_0x10085d0 .delay (20000,20000,20000) L_0x10085d0/d; -L_0x1008670/d .functor OR 1, L_0x1003b20, L_0x10085d0, C4<0>, C4<0>; -L_0x1008670 .delay (20000,20000,20000) L_0x1008670/d; -v0xfef4e0_0 .alias "S", 0 0, v0xff6820_0; -v0xfef580_0 .net "in0", 0 0, L_0x1008850; 1 drivers -v0xfef600_0 .net "in1", 0 0, C4<0>; 1 drivers -v0xfef6a0_0 .net "nS", 0 0, L_0xffbbb0; 1 drivers -v0xfef750_0 .net "out0", 0 0, L_0x1003b20; 1 drivers -v0xfef7f0_0 .net "out1", 0 0, L_0x10085d0; 1 drivers -v0xfef8d0_0 .net "outfinal", 0 0, L_0x1008670; 1 drivers -S_0xfeee80 .scope module, "setSLTres3" "TwoInMux" 3 244, 3 8, S_0xfeed10; - .timescale -9 -12; -L_0xffba10/d .functor NOT 1, L_0x1009040, C4<0>, C4<0>, C4<0>; -L_0xffba10 .delay (10000,10000,10000) L_0xffba10/d; -L_0x1008ad0/d .functor AND 1, L_0x1008e40, L_0xffba10, C4<1>, C4<1>; -L_0x1008ad0 .delay (20000,20000,20000) L_0x1008ad0/d; -L_0x1008bc0/d .functor AND 1, L_0x1008940, L_0x1009040, C4<1>, C4<1>; -L_0x1008bc0 .delay (20000,20000,20000) L_0x1008bc0/d; -L_0x1008c60/d .functor OR 1, L_0x1008ad0, L_0x1008bc0, C4<0>, C4<0>; -L_0x1008c60 .delay (20000,20000,20000) L_0x1008c60/d; -v0xfeef70_0 .alias "S", 0 0, v0xff6820_0; -v0xfef010_0 .net "in0", 0 0, L_0x1008e40; 1 drivers -v0xfef0b0_0 .net "in1", 0 0, L_0x1008940; 1 drivers -v0xfef150_0 .net "nS", 0 0, L_0xffba10; 1 drivers -v0xfef1d0_0 .net "out0", 0 0, L_0x1008ad0; 1 drivers -v0xfef270_0 .net "out1", 0 0, L_0x1008bc0; 1 drivers -v0xfef350_0 .net "outfinal", 0 0, L_0x1008c60; 1 drivers -S_0xfeba90 .scope module, "trial1" "AndNand32" 2 151, 3 115, S_0xeed190; - .timescale -9 -12; -P_0xfeb5a8 .param/l "size" 3 122, +C4<0100>; -v0xfee950_0 .alias "A", 3 0, v0xffb8e0_0; -v0xfee9d0_0 .alias "AndNandOut", 3 0, v0xffc4b0_0; -v0xfeeaa0_0 .alias "B", 3 0, v0xffba90_0; -v0xfeeb20_0 .alias "Command", 2 0, v0xffbc20_0; -L_0x100d070 .part/pv L_0x100ce00, 1, 1, 4; -L_0x100d1c0 .part v0xffc310_0, 1, 1; -L_0x100d260 .part v0xffc560_0, 1, 1; -L_0x100db20 .part/pv L_0x100d8b0, 2, 1, 4; -L_0x100dbc0 .part v0xffc310_0, 2, 1; -L_0x100dc60 .part v0xffc560_0, 2, 1; -L_0x100e590 .part/pv L_0x100e320, 3, 1, 4; -L_0x100e630 .part v0xffc310_0, 3, 1; -L_0x100e720 .part v0xffc560_0, 3, 1; -L_0x100eff0 .part/pv L_0x100ed80, 0, 1, 4; -L_0x100f0f0 .part v0xffc310_0, 0, 1; -L_0x100f190 .part v0xffc560_0, 0, 1; -S_0xfedf20 .scope module, "attempt2" "AndNand" 3 126, 3 48, S_0xfeba90; - .timescale -9 -12; -L_0x100e810/d .functor NAND 1, L_0x100f0f0, L_0x100f190, C4<1>, C4<1>; -L_0x100e810 .delay (10000,10000,10000) L_0x100e810/d; -L_0x100e930/d .functor NOT 1, L_0x100e810, C4<0>, C4<0>, C4<0>; -L_0x100e930 .delay (10000,10000,10000) L_0x100e930/d; -v0xfee540_0 .net "A", 0 0, L_0x100f0f0; 1 drivers -v0xfee600_0 .net "AandB", 0 0, L_0x100e930; 1 drivers -v0xfee680_0 .net "AnandB", 0 0, L_0x100e810; 1 drivers -v0xfee730_0 .net "AndNandOut", 0 0, L_0x100ed80; 1 drivers -v0xfee810_0 .net "B", 0 0, L_0x100f190; 1 drivers -v0xfee890_0 .alias "Command", 2 0, v0xffbc20_0; -L_0x100ef50 .part v0xffc5e0_0, 0, 1; -S_0xfee010 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0xfedf20; - .timescale -9 -12; -L_0x100ea60/d .functor NOT 1, L_0x100ef50, C4<0>, C4<0>, C4<0>; -L_0x100ea60 .delay (10000,10000,10000) L_0x100ea60/d; -L_0x100eb20/d .functor AND 1, L_0x100e930, L_0x100ea60, C4<1>, C4<1>; -L_0x100eb20 .delay (20000,20000,20000) L_0x100eb20/d; -L_0x100ec30/d .functor AND 1, L_0x100e810, L_0x100ef50, C4<1>, C4<1>; -L_0x100ec30 .delay (20000,20000,20000) L_0x100ec30/d; -L_0x100ed80/d .functor OR 1, L_0x100eb20, L_0x100ec30, C4<0>, C4<0>; -L_0x100ed80 .delay (20000,20000,20000) L_0x100ed80/d; -v0xfee100_0 .net "S", 0 0, L_0x100ef50; 1 drivers -v0xfee180_0 .alias "in0", 0 0, v0xfee600_0; -v0xfee200_0 .alias "in1", 0 0, v0xfee680_0; -v0xfee2a0_0 .net "nS", 0 0, L_0x100ea60; 1 drivers -v0xfee320_0 .net "out0", 0 0, L_0x100eb20; 1 drivers -v0xfee3c0_0 .net "out1", 0 0, L_0x100ec30; 1 drivers -v0xfee4a0_0 .alias "outfinal", 0 0, v0xfee730_0; -S_0xfed360 .scope generate, "andbits[1]" "andbits[1]" 3 130, 3 130, S_0xfeba90; - .timescale -9 -12; -P_0xfed458 .param/l "i" 3 130, +C4<01>; -S_0xfed4d0 .scope module, "attempt" "AndNand" 3 132, 3 48, S_0xfed360; - .timescale -9 -12; -L_0x100bde0/d .functor NAND 1, L_0x100d1c0, L_0x100d260, C4<1>, C4<1>; -L_0x100bde0 .delay (10000,10000,10000) L_0x100bde0/d; -L_0x100c9f0/d .functor NOT 1, L_0x100bde0, C4<0>, C4<0>, C4<0>; -L_0x100c9f0 .delay (10000,10000,10000) L_0x100c9f0/d; -v0xfedb10_0 .net "A", 0 0, L_0x100d1c0; 1 drivers -v0xfedbd0_0 .net "AandB", 0 0, L_0x100c9f0; 1 drivers -v0xfedc50_0 .net "AnandB", 0 0, L_0x100bde0; 1 drivers -v0xfedd00_0 .net "AndNandOut", 0 0, L_0x100ce00; 1 drivers -v0xfedde0_0 .net "B", 0 0, L_0x100d260; 1 drivers -v0xfede60_0 .alias "Command", 2 0, v0xffbc20_0; -L_0x100cfd0 .part v0xffc5e0_0, 0, 1; -S_0xfed5c0 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0xfed4d0; - .timescale -9 -12; -L_0x100cae0/d .functor NOT 1, L_0x100cfd0, C4<0>, C4<0>, C4<0>; -L_0x100cae0 .delay (10000,10000,10000) L_0x100cae0/d; -L_0x100cba0/d .functor AND 1, L_0x100c9f0, L_0x100cae0, C4<1>, C4<1>; -L_0x100cba0 .delay (20000,20000,20000) L_0x100cba0/d; -L_0x100ccb0/d .functor AND 1, L_0x100bde0, L_0x100cfd0, C4<1>, C4<1>; -L_0x100ccb0 .delay (20000,20000,20000) L_0x100ccb0/d; -L_0x100ce00/d .functor OR 1, L_0x100cba0, L_0x100ccb0, C4<0>, C4<0>; -L_0x100ce00 .delay (20000,20000,20000) L_0x100ce00/d; -v0xfed6b0_0 .net "S", 0 0, L_0x100cfd0; 1 drivers -v0xfed730_0 .alias "in0", 0 0, v0xfedbd0_0; -v0xfed7d0_0 .alias "in1", 0 0, v0xfedc50_0; -v0xfed870_0 .net "nS", 0 0, L_0x100cae0; 1 drivers -v0xfed8f0_0 .net "out0", 0 0, L_0x100cba0; 1 drivers -v0xfed990_0 .net "out1", 0 0, L_0x100ccb0; 1 drivers -v0xfeda70_0 .alias "outfinal", 0 0, v0xfedd00_0; -S_0xfec7a0 .scope generate, "andbits[2]" "andbits[2]" 3 130, 3 130, S_0xfeba90; - .timescale -9 -12; -P_0xfec898 .param/l "i" 3 130, +C4<010>; -S_0xfec910 .scope module, "attempt" "AndNand" 3 132, 3 48, S_0xfec7a0; - .timescale -9 -12; -L_0x100d300/d .functor NAND 1, L_0x100dbc0, L_0x100dc60, C4<1>, C4<1>; -L_0x100d300 .delay (10000,10000,10000) L_0x100d300/d; -L_0x100d460/d .functor NOT 1, L_0x100d300, C4<0>, C4<0>, C4<0>; -L_0x100d460 .delay (10000,10000,10000) L_0x100d460/d; -v0xfecf50_0 .net "A", 0 0, L_0x100dbc0; 1 drivers -v0xfed010_0 .net "AandB", 0 0, L_0x100d460; 1 drivers -v0xfed090_0 .net "AnandB", 0 0, L_0x100d300; 1 drivers -v0xfed140_0 .net "AndNandOut", 0 0, L_0x100d8b0; 1 drivers -v0xfed220_0 .net "B", 0 0, L_0x100dc60; 1 drivers -v0xfed2a0_0 .alias "Command", 2 0, v0xffbc20_0; -L_0x100da80 .part v0xffc5e0_0, 0, 1; -S_0xfeca00 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0xfec910; - .timescale -9 -12; -L_0x100d590/d .functor NOT 1, L_0x100da80, C4<0>, C4<0>, C4<0>; -L_0x100d590 .delay (10000,10000,10000) L_0x100d590/d; -L_0x100d650/d .functor AND 1, L_0x100d460, L_0x100d590, C4<1>, C4<1>; -L_0x100d650 .delay (20000,20000,20000) L_0x100d650/d; -L_0x100d760/d .functor AND 1, L_0x100d300, L_0x100da80, C4<1>, C4<1>; -L_0x100d760 .delay (20000,20000,20000) L_0x100d760/d; -L_0x100d8b0/d .functor OR 1, L_0x100d650, L_0x100d760, C4<0>, C4<0>; -L_0x100d8b0 .delay (20000,20000,20000) L_0x100d8b0/d; -v0xfecaf0_0 .net "S", 0 0, L_0x100da80; 1 drivers -v0xfecb70_0 .alias "in0", 0 0, v0xfed010_0; -v0xfecc10_0 .alias "in1", 0 0, v0xfed090_0; -v0xfeccb0_0 .net "nS", 0 0, L_0x100d590; 1 drivers -v0xfecd30_0 .net "out0", 0 0, L_0x100d650; 1 drivers -v0xfecdd0_0 .net "out1", 0 0, L_0x100d760; 1 drivers -v0xfeceb0_0 .alias "outfinal", 0 0, v0xfed140_0; -S_0xfebbc0 .scope generate, "andbits[3]" "andbits[3]" 3 130, 3 130, S_0xfeba90; - .timescale -9 -12; -P_0xfebcb8 .param/l "i" 3 130, +C4<011>; -S_0xfebd30 .scope module, "attempt" "AndNand" 3 132, 3 48, S_0xfebbc0; - .timescale -9 -12; -L_0x100dd90/d .functor NAND 1, L_0x100e630, L_0x100e720, C4<1>, C4<1>; -L_0x100dd90 .delay (10000,10000,10000) L_0x100dd90/d; -L_0x100ded0/d .functor NOT 1, L_0x100dd90, C4<0>, C4<0>, C4<0>; -L_0x100ded0 .delay (10000,10000,10000) L_0x100ded0/d; -v0xfec390_0 .net "A", 0 0, L_0x100e630; 1 drivers -v0xfec450_0 .net "AandB", 0 0, L_0x100ded0; 1 drivers -v0xfec4d0_0 .net "AnandB", 0 0, L_0x100dd90; 1 drivers -v0xfec580_0 .net "AndNandOut", 0 0, L_0x100e320; 1 drivers -v0xfec660_0 .net "B", 0 0, L_0x100e720; 1 drivers -v0xfec6e0_0 .alias "Command", 2 0, v0xffbc20_0; -L_0x100e4f0 .part v0xffc5e0_0, 0, 1; -S_0xfebe20 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0xfebd30; - .timescale -9 -12; -L_0x100e000/d .functor NOT 1, L_0x100e4f0, C4<0>, C4<0>, C4<0>; -L_0x100e000 .delay (10000,10000,10000) L_0x100e000/d; -L_0x100e0c0/d .functor AND 1, L_0x100ded0, L_0x100e000, C4<1>, C4<1>; -L_0x100e0c0 .delay (20000,20000,20000) L_0x100e0c0/d; -L_0x100e1d0/d .functor AND 1, L_0x100dd90, L_0x100e4f0, C4<1>, C4<1>; -L_0x100e1d0 .delay (20000,20000,20000) L_0x100e1d0/d; -L_0x100e320/d .functor OR 1, L_0x100e0c0, L_0x100e1d0, C4<0>, C4<0>; -L_0x100e320 .delay (20000,20000,20000) L_0x100e320/d; -v0xfebf10_0 .net "S", 0 0, L_0x100e4f0; 1 drivers -v0xfebfb0_0 .alias "in0", 0 0, v0xfec450_0; -v0xfec050_0 .alias "in1", 0 0, v0xfec4d0_0; -v0xfec0f0_0 .net "nS", 0 0, L_0x100e000; 1 drivers -v0xfec170_0 .net "out0", 0 0, L_0x100e0c0; 1 drivers -v0xfec210_0 .net "out1", 0 0, L_0x100e1d0; 1 drivers -v0xfec2f0_0 .alias "outfinal", 0 0, v0xfec580_0; -S_0xfe6a60 .scope module, "trial2" "OrNorXor32" 2 153, 3 138, S_0xeed190; - .timescale -9 -12; -P_0xfe5608 .param/l "size" 3 145, +C4<0100>; -v0xfeb890_0 .alias "A", 3 0, v0xffb8e0_0; -v0xfeb910_0 .alias "B", 3 0, v0xffba90_0; -v0xfeb990_0 .alias "Command", 2 0, v0xffbc20_0; -v0xfeba10_0 .alias "OrNorXorOut", 3 0, v0xffc6e0_0; -L_0x10103b0 .part/pv L_0x1010140, 1, 1, 4; -L_0x10104e0 .part v0xffc310_0, 1, 1; -L_0x1010580 .part v0xffc560_0, 1, 1; -L_0x10116f0 .part/pv L_0x1011480, 2, 1, 4; -L_0x1011790 .part v0xffc310_0, 2, 1; -L_0x1011830 .part v0xffc560_0, 2, 1; -L_0x10129f0 .part/pv L_0x1012780, 3, 1, 4; -L_0x1012a90 .part v0xffc310_0, 3, 1; -L_0x1012b30 .part v0xffc560_0, 3, 1; -L_0x1013ce0 .part/pv L_0x1013a70, 0, 1, 4; -L_0x1013de0 .part v0xffc310_0, 0, 1; -L_0x1013e80 .part v0xffc560_0, 0, 1; -S_0xfea650 .scope module, "attempt2" "OrNorXor" 3 153, 3 64, S_0xfe6a60; - .timescale -9 -12; -L_0x1012bd0/d .functor NOR 1, L_0x1013de0, L_0x1013e80, C4<0>, C4<0>; -L_0x1012bd0 .delay (10000,10000,10000) L_0x1012bd0/d; -L_0x1012cd0/d .functor NOT 1, L_0x1012bd0, C4<0>, C4<0>, C4<0>; -L_0x1012cd0 .delay (10000,10000,10000) L_0x1012cd0/d; -L_0x1012e00/d .functor NAND 1, L_0x1013de0, L_0x1013e80, C4<1>, C4<1>; -L_0x1012e00 .delay (10000,10000,10000) L_0x1012e00/d; -L_0x1012f60/d .functor NAND 1, L_0x1012e00, L_0x1012cd0, C4<1>, C4<1>; -L_0x1012f60 .delay (10000,10000,10000) L_0x1012f60/d; -L_0x1013070/d .functor NOT 1, L_0x1012f60, C4<0>, C4<0>, C4<0>; -L_0x1013070 .delay (10000,10000,10000) L_0x1013070/d; -v0xfeb1a0_0 .net "A", 0 0, L_0x1013de0; 1 drivers -v0xfeb240_0 .net "AnandB", 0 0, L_0x1012e00; 1 drivers -v0xfeb2e0_0 .net "AnorB", 0 0, L_0x1012bd0; 1 drivers -v0xfeb390_0 .net "AorB", 0 0, L_0x1012cd0; 1 drivers -v0xfeb470_0 .net "AxorB", 0 0, L_0x1013070; 1 drivers -v0xfeb520_0 .net "B", 0 0, L_0x1013e80; 1 drivers -v0xfeb5e0_0 .alias "Command", 2 0, v0xffbc20_0; -v0xfeb660_0 .net "OrNorXorOut", 0 0, L_0x1013a70; 1 drivers -v0xfeb6e0_0 .net "XorNor", 0 0, L_0x10134f0; 1 drivers -v0xfeb7b0_0 .net "nXor", 0 0, L_0x1012f60; 1 drivers -L_0x1013670 .part v0xffc5e0_0, 2, 1; -L_0x1013c40 .part v0xffc5e0_0, 0, 1; -S_0xfeac30 .scope module, "mux0" "TwoInMux" 3 83, 3 8, S_0xfea650; - .timescale -9 -12; -L_0x10131d0/d .functor NOT 1, L_0x1013670, C4<0>, C4<0>, C4<0>; -L_0x10131d0 .delay (10000,10000,10000) L_0x10131d0/d; -L_0x1013290/d .functor AND 1, L_0x1013070, L_0x10131d0, C4<1>, C4<1>; -L_0x1013290 .delay (20000,20000,20000) L_0x1013290/d; -L_0x10133a0/d .functor AND 1, L_0x1012bd0, L_0x1013670, C4<1>, C4<1>; -L_0x10133a0 .delay (20000,20000,20000) L_0x10133a0/d; -L_0x10134f0/d .functor OR 1, L_0x1013290, L_0x10133a0, C4<0>, C4<0>; -L_0x10134f0 .delay (20000,20000,20000) L_0x10134f0/d; -v0xfead20_0 .net "S", 0 0, L_0x1013670; 1 drivers -v0xfeade0_0 .alias "in0", 0 0, v0xfeb470_0; -v0xfeae80_0 .alias "in1", 0 0, v0xfeb2e0_0; -v0xfeaf20_0 .net "nS", 0 0, L_0x10131d0; 1 drivers -v0xfeafa0_0 .net "out0", 0 0, L_0x1013290; 1 drivers -v0xfeb040_0 .net "out1", 0 0, L_0x10133a0; 1 drivers -v0xfeb120_0 .alias "outfinal", 0 0, v0xfeb6e0_0; -S_0xfea740 .scope module, "mux1" "TwoInMux" 3 84, 3 8, S_0xfea650; - .timescale -9 -12; -L_0x1013710/d .functor NOT 1, L_0x1013c40, C4<0>, C4<0>, C4<0>; -L_0x1013710 .delay (10000,10000,10000) L_0x1013710/d; -L_0x10137d0/d .functor AND 1, L_0x10134f0, L_0x1013710, C4<1>, C4<1>; -L_0x10137d0 .delay (20000,20000,20000) L_0x10137d0/d; -L_0x1013920/d .functor AND 1, L_0x1012cd0, L_0x1013c40, C4<1>, C4<1>; -L_0x1013920 .delay (20000,20000,20000) L_0x1013920/d; -L_0x1013a70/d .functor OR 1, L_0x10137d0, L_0x1013920, C4<0>, C4<0>; -L_0x1013a70 .delay (20000,20000,20000) L_0x1013a70/d; -v0xfea830_0 .net "S", 0 0, L_0x1013c40; 1 drivers -v0xfea8b0_0 .alias "in0", 0 0, v0xfeb6e0_0; -v0xfea930_0 .alias "in1", 0 0, v0xfeb390_0; -v0xfea9d0_0 .net "nS", 0 0, L_0x1013710; 1 drivers -v0xfeaa50_0 .net "out0", 0 0, L_0x10137d0; 1 drivers -v0xfeaaf0_0 .net "out1", 0 0, L_0x1013920; 1 drivers -v0xfeab90_0 .alias "outfinal", 0 0, v0xfeb660_0; -S_0xfe9280 .scope generate, "orbits[1]" "orbits[1]" 3 157, 3 157, S_0xfe6a60; - .timescale -9 -12; -P_0xfe8f98 .param/l "i" 3 157, +C4<01>; -S_0xfe93b0 .scope module, "attempt" "OrNorXor" 3 159, 3 64, S_0xfe9280; - .timescale -9 -12; -L_0x100f090/d .functor NOR 1, L_0x10104e0, L_0x1010580, C4<0>, C4<0>; -L_0x100f090 .delay (10000,10000,10000) L_0x100f090/d; -L_0x100f3a0/d .functor NOT 1, L_0x100f090, C4<0>, C4<0>, C4<0>; -L_0x100f3a0 .delay (10000,10000,10000) L_0x100f3a0/d; -L_0x100f4d0/d .functor NAND 1, L_0x10104e0, L_0x1010580, C4<1>, C4<1>; -L_0x100f4d0 .delay (10000,10000,10000) L_0x100f4d0/d; -L_0x100f630/d .functor NAND 1, L_0x100f4d0, L_0x100f3a0, C4<1>, C4<1>; -L_0x100f630 .delay (10000,10000,10000) L_0x100f630/d; -L_0x100f740/d .functor NOT 1, L_0x100f630, C4<0>, C4<0>, C4<0>; -L_0x100f740 .delay (10000,10000,10000) L_0x100f740/d; -v0xfe9f60_0 .net "A", 0 0, L_0x10104e0; 1 drivers -v0xfea000_0 .net "AnandB", 0 0, L_0x100f4d0; 1 drivers -v0xfea0a0_0 .net "AnorB", 0 0, L_0x100f090; 1 drivers -v0xfea150_0 .net "AorB", 0 0, L_0x100f3a0; 1 drivers -v0xfea230_0 .net "AxorB", 0 0, L_0x100f740; 1 drivers -v0xfea2e0_0 .net "B", 0 0, L_0x1010580; 1 drivers -v0xfea3a0_0 .alias "Command", 2 0, v0xffbc20_0; -v0xfea420_0 .net "OrNorXorOut", 0 0, L_0x1010140; 1 drivers -v0xfea4a0_0 .net "XorNor", 0 0, L_0x100fbc0; 1 drivers -v0xfea570_0 .net "nXor", 0 0, L_0x100f630; 1 drivers -L_0x100fd40 .part v0xffc5e0_0, 2, 1; -L_0x1010310 .part v0xffc5e0_0, 0, 1; -S_0xfe99f0 .scope module, "mux0" "TwoInMux" 3 83, 3 8, S_0xfe93b0; - .timescale -9 -12; -L_0x100f8a0/d .functor NOT 1, L_0x100fd40, C4<0>, C4<0>, C4<0>; -L_0x100f8a0 .delay (10000,10000,10000) L_0x100f8a0/d; -L_0x100f960/d .functor AND 1, L_0x100f740, L_0x100f8a0, C4<1>, C4<1>; -L_0x100f960 .delay (20000,20000,20000) L_0x100f960/d; -L_0x100fa70/d .functor AND 1, L_0x100f090, L_0x100fd40, C4<1>, C4<1>; -L_0x100fa70 .delay (20000,20000,20000) L_0x100fa70/d; -L_0x100fbc0/d .functor OR 1, L_0x100f960, L_0x100fa70, C4<0>, C4<0>; -L_0x100fbc0 .delay (20000,20000,20000) L_0x100fbc0/d; -v0xfe9ae0_0 .net "S", 0 0, L_0x100fd40; 1 drivers -v0xfe9ba0_0 .alias "in0", 0 0, v0xfea230_0; -v0xfe9c40_0 .alias "in1", 0 0, v0xfea0a0_0; -v0xfe9ce0_0 .net "nS", 0 0, L_0x100f8a0; 1 drivers -v0xfe9d60_0 .net "out0", 0 0, L_0x100f960; 1 drivers -v0xfe9e00_0 .net "out1", 0 0, L_0x100fa70; 1 drivers -v0xfe9ee0_0 .alias "outfinal", 0 0, v0xfea4a0_0; -S_0xfe94a0 .scope module, "mux1" "TwoInMux" 3 84, 3 8, S_0xfe93b0; - .timescale -9 -12; -L_0x100fde0/d .functor NOT 1, L_0x1010310, C4<0>, C4<0>, C4<0>; -L_0x100fde0 .delay (10000,10000,10000) L_0x100fde0/d; -L_0x100fea0/d .functor AND 1, L_0x100fbc0, L_0x100fde0, C4<1>, C4<1>; -L_0x100fea0 .delay (20000,20000,20000) L_0x100fea0/d; -L_0x100fff0/d .functor AND 1, L_0x100f3a0, L_0x1010310, C4<1>, C4<1>; -L_0x100fff0 .delay (20000,20000,20000) L_0x100fff0/d; -L_0x1010140/d .functor OR 1, L_0x100fea0, L_0x100fff0, C4<0>, C4<0>; -L_0x1010140 .delay (20000,20000,20000) L_0x1010140/d; -v0xfe9590_0 .net "S", 0 0, L_0x1010310; 1 drivers -v0xfe9610_0 .alias "in0", 0 0, v0xfea4a0_0; -v0xfe96b0_0 .alias "in1", 0 0, v0xfea150_0; -v0xfe9750_0 .net "nS", 0 0, L_0x100fde0; 1 drivers -v0xfe97d0_0 .net "out0", 0 0, L_0x100fea0; 1 drivers -v0xfe9870_0 .net "out1", 0 0, L_0x100fff0; 1 drivers -v0xfe9950_0 .alias "outfinal", 0 0, v0xfea420_0; -S_0xfe7eb0 .scope generate, "orbits[2]" "orbits[2]" 3 157, 3 157, S_0xfe6a60; - .timescale -9 -12; -P_0xfe7bd8 .param/l "i" 3 157, +C4<010>; -S_0xfe7fe0 .scope module, "attempt" "OrNorXor" 3 159, 3 64, S_0xfe7eb0; - .timescale -9 -12; -L_0x1010620/d .functor NOR 1, L_0x1011790, L_0x1011830, C4<0>, C4<0>; -L_0x1010620 .delay (10000,10000,10000) L_0x1010620/d; -L_0x10106e0/d .functor NOT 1, L_0x1010620, C4<0>, C4<0>, C4<0>; -L_0x10106e0 .delay (10000,10000,10000) L_0x10106e0/d; -L_0x1010810/d .functor NAND 1, L_0x1011790, L_0x1011830, C4<1>, C4<1>; -L_0x1010810 .delay (10000,10000,10000) L_0x1010810/d; -L_0x1010970/d .functor NAND 1, L_0x1010810, L_0x10106e0, C4<1>, C4<1>; -L_0x1010970 .delay (10000,10000,10000) L_0x1010970/d; -L_0x1010a80/d .functor NOT 1, L_0x1010970, C4<0>, C4<0>, C4<0>; -L_0x1010a80 .delay (10000,10000,10000) L_0x1010a80/d; -v0xfe8b90_0 .net "A", 0 0, L_0x1011790; 1 drivers -v0xfe8c30_0 .net "AnandB", 0 0, L_0x1010810; 1 drivers -v0xfe8cd0_0 .net "AnorB", 0 0, L_0x1010620; 1 drivers -v0xfe8d80_0 .net "AorB", 0 0, L_0x10106e0; 1 drivers -v0xfe8e60_0 .net "AxorB", 0 0, L_0x1010a80; 1 drivers -v0xfe8f10_0 .net "B", 0 0, L_0x1011830; 1 drivers -v0xfe8fd0_0 .alias "Command", 2 0, v0xffbc20_0; -v0xfe9050_0 .net "OrNorXorOut", 0 0, L_0x1011480; 1 drivers -v0xfe90d0_0 .net "XorNor", 0 0, L_0x1010f00; 1 drivers -v0xfe91a0_0 .net "nXor", 0 0, L_0x1010970; 1 drivers -L_0x1011080 .part v0xffc5e0_0, 2, 1; -L_0x1011650 .part v0xffc5e0_0, 0, 1; -S_0xfe8620 .scope module, "mux0" "TwoInMux" 3 83, 3 8, S_0xfe7fe0; - .timescale -9 -12; -L_0x1010be0/d .functor NOT 1, L_0x1011080, C4<0>, C4<0>, C4<0>; -L_0x1010be0 .delay (10000,10000,10000) L_0x1010be0/d; -L_0x1010ca0/d .functor AND 1, L_0x1010a80, L_0x1010be0, C4<1>, C4<1>; -L_0x1010ca0 .delay (20000,20000,20000) L_0x1010ca0/d; -L_0x1010db0/d .functor AND 1, L_0x1010620, L_0x1011080, C4<1>, C4<1>; -L_0x1010db0 .delay (20000,20000,20000) L_0x1010db0/d; -L_0x1010f00/d .functor OR 1, L_0x1010ca0, L_0x1010db0, C4<0>, C4<0>; -L_0x1010f00 .delay (20000,20000,20000) L_0x1010f00/d; -v0xfe8710_0 .net "S", 0 0, L_0x1011080; 1 drivers -v0xfe87d0_0 .alias "in0", 0 0, v0xfe8e60_0; -v0xfe8870_0 .alias "in1", 0 0, v0xfe8cd0_0; -v0xfe8910_0 .net "nS", 0 0, L_0x1010be0; 1 drivers -v0xfe8990_0 .net "out0", 0 0, L_0x1010ca0; 1 drivers -v0xfe8a30_0 .net "out1", 0 0, L_0x1010db0; 1 drivers -v0xfe8b10_0 .alias "outfinal", 0 0, v0xfe90d0_0; -S_0xfe80d0 .scope module, "mux1" "TwoInMux" 3 84, 3 8, S_0xfe7fe0; - .timescale -9 -12; -L_0x1011120/d .functor NOT 1, L_0x1011650, C4<0>, C4<0>, C4<0>; -L_0x1011120 .delay (10000,10000,10000) L_0x1011120/d; -L_0x10111e0/d .functor AND 1, L_0x1010f00, L_0x1011120, C4<1>, C4<1>; -L_0x10111e0 .delay (20000,20000,20000) L_0x10111e0/d; -L_0x1011330/d .functor AND 1, L_0x10106e0, L_0x1011650, C4<1>, C4<1>; -L_0x1011330 .delay (20000,20000,20000) L_0x1011330/d; -L_0x1011480/d .functor OR 1, L_0x10111e0, L_0x1011330, C4<0>, C4<0>; -L_0x1011480 .delay (20000,20000,20000) L_0x1011480/d; -v0xfe81c0_0 .net "S", 0 0, L_0x1011650; 1 drivers -v0xfe8240_0 .alias "in0", 0 0, v0xfe90d0_0; -v0xfe82e0_0 .alias "in1", 0 0, v0xfe8d80_0; -v0xfe8380_0 .net "nS", 0 0, L_0x1011120; 1 drivers -v0xfe8400_0 .net "out0", 0 0, L_0x10111e0; 1 drivers -v0xfe84a0_0 .net "out1", 0 0, L_0x1011330; 1 drivers -v0xfe8580_0 .alias "outfinal", 0 0, v0xfe9050_0; -S_0xfe6b50 .scope generate, "orbits[3]" "orbits[3]" 3 157, 3 157, S_0xfe6a60; - .timescale -9 -12; -P_0xfe6828 .param/l "i" 3 157, +C4<011>; -S_0xfe6ca0 .scope module, "attempt" "OrNorXor" 3 159, 3 64, S_0xfe6b50; - .timescale -9 -12; -L_0x1011910/d .functor NOR 1, L_0x1012a90, L_0x1012b30, C4<0>, C4<0>; -L_0x1011910 .delay (10000,10000,10000) L_0x1011910/d; -L_0x1011a00/d .functor NOT 1, L_0x1011910, C4<0>, C4<0>, C4<0>; -L_0x1011a00 .delay (10000,10000,10000) L_0x1011a00/d; -L_0x1011b10/d .functor NAND 1, L_0x1012a90, L_0x1012b30, C4<1>, C4<1>; -L_0x1011b10 .delay (10000,10000,10000) L_0x1011b10/d; -L_0x1011c70/d .functor NAND 1, L_0x1011b10, L_0x1011a00, C4<1>, C4<1>; -L_0x1011c70 .delay (10000,10000,10000) L_0x1011c70/d; -L_0x1011d80/d .functor NOT 1, L_0x1011c70, C4<0>, C4<0>, C4<0>; -L_0x1011d80 .delay (10000,10000,10000) L_0x1011d80/d; -v0xfe7890_0 .net "A", 0 0, L_0x1012a90; 1 drivers -v0xfe7930_0 .net "AnandB", 0 0, L_0x1011b10; 1 drivers -v0xfe79d0_0 .net "AnorB", 0 0, L_0x1011910; 1 drivers -v0xfe7a50_0 .net "AorB", 0 0, L_0x1011a00; 1 drivers -v0xfe7ad0_0 .net "AxorB", 0 0, L_0x1011d80; 1 drivers -v0xfe7b50_0 .net "B", 0 0, L_0x1012b30; 1 drivers -v0xfe7c10_0 .alias "Command", 2 0, v0xffbc20_0; -v0xfe7c90_0 .net "OrNorXorOut", 0 0, L_0x1012780; 1 drivers -v0xfe7d60_0 .net "XorNor", 0 0, L_0x1012200; 1 drivers -v0xfe7e30_0 .net "nXor", 0 0, L_0x1011c70; 1 drivers -L_0x1012380 .part v0xffc5e0_0, 2, 1; -L_0x1012950 .part v0xffc5e0_0, 0, 1; -S_0xfe7320 .scope module, "mux0" "TwoInMux" 3 83, 3 8, S_0xfe6ca0; - .timescale -9 -12; -L_0x1011ee0/d .functor NOT 1, L_0x1012380, C4<0>, C4<0>, C4<0>; -L_0x1011ee0 .delay (10000,10000,10000) L_0x1011ee0/d; -L_0x1011fa0/d .functor AND 1, L_0x1011d80, L_0x1011ee0, C4<1>, C4<1>; -L_0x1011fa0 .delay (20000,20000,20000) L_0x1011fa0/d; -L_0x10120b0/d .functor AND 1, L_0x1011910, L_0x1012380, C4<1>, C4<1>; -L_0x10120b0 .delay (20000,20000,20000) L_0x10120b0/d; -L_0x1012200/d .functor OR 1, L_0x1011fa0, L_0x10120b0, C4<0>, C4<0>; -L_0x1012200 .delay (20000,20000,20000) L_0x1012200/d; -v0xfe7410_0 .net "S", 0 0, L_0x1012380; 1 drivers -v0xfe74d0_0 .alias "in0", 0 0, v0xfe7ad0_0; -v0xfe7570_0 .alias "in1", 0 0, v0xfe79d0_0; -v0xfe7610_0 .net "nS", 0 0, L_0x1011ee0; 1 drivers -v0xfe7690_0 .net "out0", 0 0, L_0x1011fa0; 1 drivers -v0xfe7730_0 .net "out1", 0 0, L_0x10120b0; 1 drivers -v0xfe7810_0 .alias "outfinal", 0 0, v0xfe7d60_0; -S_0xfe6d90 .scope module, "mux1" "TwoInMux" 3 84, 3 8, S_0xfe6ca0; - .timescale -9 -12; -L_0x1012420/d .functor NOT 1, L_0x1012950, C4<0>, C4<0>, C4<0>; -L_0x1012420 .delay (10000,10000,10000) L_0x1012420/d; -L_0x10124e0/d .functor AND 1, L_0x1012200, L_0x1012420, C4<1>, C4<1>; -L_0x10124e0 .delay (20000,20000,20000) L_0x10124e0/d; -L_0x1012630/d .functor AND 1, L_0x1011a00, L_0x1012950, C4<1>, C4<1>; -L_0x1012630 .delay (20000,20000,20000) L_0x1012630/d; -L_0x1012780/d .functor OR 1, L_0x10124e0, L_0x1012630, C4<0>, C4<0>; -L_0x1012780 .delay (20000,20000,20000) L_0x1012780/d; -v0xfe6e80_0 .net "S", 0 0, L_0x1012950; 1 drivers -v0xfe6f40_0 .alias "in0", 0 0, v0xfe7d60_0; -v0xfe6fe0_0 .alias "in1", 0 0, v0xfe7a50_0; -v0xfe7080_0 .net "nS", 0 0, L_0x1012420; 1 drivers -v0xfe7100_0 .net "out0", 0 0, L_0x10124e0; 1 drivers -v0xfe71a0_0 .net "out1", 0 0, L_0x1012630; 1 drivers -v0xfe7280_0 .alias "outfinal", 0 0, v0xfe7c90_0; -S_0xf6f800 .scope module, "superalu" "Bitslice32" 2 155, 3 302, S_0xeed190; - .timescale -9 -12; -P_0xe99568 .param/l "size" 3 320, +C4<0100>; -L_0x1018d20/d .functor AND 1, L_0x10356f0, L_0x10358d0, C4<1>, C4<1>; -L_0x1018d20 .delay (20000,20000,20000) L_0x1018d20/d; -L_0x10359c0/d .functor NOT 1, L_0x1035a70, C4<0>, C4<0>, C4<0>; -L_0x10359c0 .delay (10000,10000,10000) L_0x10359c0/d; -L_0x1035f20/d .functor AND 1, L_0x10359c0, L_0x10359c0, C4<1>, C4<1>; -L_0x1035f20 .delay (20000,20000,20000) L_0x1035f20/d; -v0xfe5810_0 .alias "A", 3 0, v0xffb8e0_0; -v0xfe5af0_0 .alias "AddSubSLTSum", 3 0, v0xffc3b0_0; -v0xfe5b70_0 .alias "AllZeros", 0 0, v0xffc430_0; -v0xfe5bf0_0 .alias "AndNandOut", 3 0, v0xffc4b0_0; -v0xfe5c70_0 .alias "B", 3 0, v0xffba90_0; -RS_0x7f9963cf1808 .resolv tri, L_0x1014610, L_0x10170b0, L_0x1019ab0, L_0x1033a30; -v0xfe5d80_0 .net8 "Cmd0Start", 3 0, RS_0x7f9963cf1808; 4 drivers -RS_0x7f9963cf1838 .resolv tri, L_0x10155c0, L_0x1017fa0, L_0x101a960, L_0x10348f0; -v0xfe5e00_0 .net8 "Cmd1Start", 3 0, RS_0x7f9963cf1838; 4 drivers -v0xfe5e80_0 .alias "Command", 2 0, v0xffbc20_0; -v0xfe5f00_0 .alias "OneBitFinalOut", 3 0, v0xffc660_0; -v0xfe5f80_0 .alias "OrNorXorOut", 3 0, v0xffc6e0_0; -v0xfe6000_0 .alias "SLTSum", 3 0, v0xffc760_0; -v0xfe60b0_0 .alias "SLTflag", 0 0, v0xffc7e0_0; -v0xfe6130_0 .alias "ZeroFlag", 3 0, v0xffc970_0; -v0xfe61b0_0 .net *"_s111", 0 0, L_0x1018d20; 1 drivers -v0xfe62b0_0 .net *"_s114", 0 0, L_0x10356f0; 1 drivers -v0xfe6330_0 .net *"_s116", 0 0, L_0x10358d0; 1 drivers -v0xfe6230_0 .net *"_s118", 0 0, L_0x1035a70; 1 drivers -v0xfe6480_0 .net *"_s21", 0 0, L_0x1016610; 1 drivers -v0xfe65a0_0 .net *"_s46", 0 0, L_0x10185f0; 1 drivers -v0xfe6620_0 .net *"_s71", 0 0, L_0x101b720; 1 drivers -v0xfe6500_0 .alias "carryin", 3 0, v0xffbed0_0; -v0xfe6750_0 .alias "carryout", 0 0, v0xffcb10_0; -v0xfe66a0_0 .alias "overflow", 0 0, v0xffcc10_0; -v0xfe6890_0 .alias "subtract", 3 0, v0xffcc90_0; -v0xfe69e0_0 .net "yeszero", 0 0, L_0x10359c0; 1 drivers -L_0x1014610 .part/pv L_0x1014430, 1, 1, 4; -L_0x10146b0 .part v0xffc5e0_0, 0, 1; -L_0x10147e0 .part v0xffc5e0_0, 1, 1; -L_0x1014910 .part RS_0x7f9963cefbe8, 1, 1; -L_0x1014ac0 .part RS_0x7f9963cefbe8, 1, 1; -L_0x1014b60 .part RS_0x7f9963cee748, 1, 1; -L_0x1014d10 .part RS_0x7f9963cf1538, 1, 1; -L_0x10155c0 .part/pv L_0x10153b0, 1, 1, 4; -L_0x10156b0 .part v0xffc5e0_0, 0, 1; -L_0x10157e0 .part v0xffc5e0_0, 1, 1; -L_0x1015970 .part RS_0x7f9963ceee38, 1, 1; -L_0x1015b20 .part RS_0x7f9963ceee38, 1, 1; -L_0x1015bc0 .part RS_0x7f9963cee748, 1, 1; -L_0x1015c60 .part RS_0x7f9963cee748, 1, 1; -L_0x10160c0 .part/pv L_0x1015f80, 1, 1, 4; -L_0x10161b0 .part v0xffc5e0_0, 2, 1; -L_0x1016250 .part RS_0x7f9963cf1808, 1, 1; -L_0x1016390 .part RS_0x7f9963cf1838, 1, 1; -L_0x1016570 .part/pv L_0x1016610, 1, 1, 4; -L_0x1016710 .part RS_0x7f9963cf1898, 0, 1; -L_0x10164d0 .part RS_0x7f9963cf1868, 1, 1; -L_0x10170b0 .part/pv L_0x1016ea0, 2, 1, 4; -L_0x10167b0 .part v0xffc5e0_0, 0, 1; -L_0x10172a0 .part v0xffc5e0_0, 1, 1; -L_0x1017150 .part RS_0x7f9963cefbe8, 2, 1; -L_0x10174a0 .part RS_0x7f9963cefbe8, 2, 1; -L_0x10173d0 .part RS_0x7f9963cee748, 2, 1; -L_0x1017670 .part RS_0x7f9963cf1538, 2, 1; -L_0x1017fa0 .part/pv L_0x1017d90, 2, 1, 4; -L_0x1018040 .part v0xffc5e0_0, 0, 1; -L_0x1017760 .part v0xffc5e0_0, 1, 1; -L_0x1018300 .part RS_0x7f9963ceee38, 2, 1; -L_0x1018170 .part RS_0x7f9963ceee38, 2, 1; -L_0x10184b0 .part RS_0x7f9963cee748, 2, 1; -L_0x10183a0 .part RS_0x7f9963cee748, 2, 1; -L_0x1018a20 .part/pv L_0x10188e0, 2, 1, 4; -L_0x1018550 .part v0xffc5e0_0, 2, 1; -L_0x1018c80 .part RS_0x7f9963cf1808, 2, 1; -L_0x1018b50 .part RS_0x7f9963cf1838, 2, 1; -L_0x1018ef0 .part/pv L_0x10185f0, 2, 1, 4; -L_0x1018df0 .part RS_0x7f9963cf1898, 1, 1; -L_0x1019170 .part RS_0x7f9963cf1868, 2, 1; -L_0x1019ab0 .part/pv L_0x10198a0, 3, 1, 4; -L_0x1019b50 .part v0xffc5e0_0, 0, 1; -L_0x1019210 .part v0xffc5e0_0, 1, 1; -L_0x1019df0 .part RS_0x7f9963cefbe8, 3, 1; -L_0x1019c80 .part RS_0x7f9963cefbe8, 3, 1; -L_0x1019d20 .part RS_0x7f9963cee748, 3, 1; -L_0x1019e90 .part RS_0x7f9963cf1538, 3, 1; -L_0x101a960 .part/pv L_0x101a750, 3, 1, 4; -L_0x101a060 .part v0xffc5e0_0, 0, 1; -L_0x101aba0 .part v0xffc5e0_0, 1, 1; -L_0x101aa00 .part RS_0x7f9963ceee38, 3, 1; -L_0x101aaa0 .part RS_0x7f9963ceee38, 3, 1; -L_0x101ae90 .part RS_0x7f9963cee748, 3, 1; -L_0x101af30 .part RS_0x7f9963cee748, 3, 1; -L_0x101b540 .part/pv L_0x101b400, 3, 1, 4; -L_0x101b5e0 .part v0xffc5e0_0, 2, 1; -L_0x101b1e0 .part RS_0x7f9963cf1808, 3, 1; -L_0x101b2d0 .part RS_0x7f9963cf1838, 3, 1; -L_0x101b680 .part/pv L_0x101b720, 3, 1, 4; -L_0x101baa0 .part RS_0x7f9963cf1898, 2, 1; -L_0x101b8b0 .part RS_0x7f9963cf1868, 3, 1; -L_0x1033a30 .part/pv L_0x1033820, 0, 1, 4; -L_0x101bb40 .part v0xffc5e0_0, 0, 1; -L_0x101bc70 .part v0xffc5e0_0, 1, 1; -L_0x1033ad0 .part RS_0x7f9963cefbe8, 0, 1; -L_0x1033b70 .part RS_0x7f9963cefbe8, 0, 1; -L_0x1033c10 .part RS_0x7f9963cee748, 0, 1; -L_0x1033ff0 .part RS_0x7f9963cf1538, 0, 1; -L_0x10348f0 .part/pv L_0x10346e0, 0, 1, 4; -L_0x1034990 .part v0xffc5e0_0, 0, 1; -L_0x10340e0 .part v0xffc5e0_0, 1, 1; -L_0x1034210 .part RS_0x7f9963ceee38, 0, 1; -L_0x1034d20 .part RS_0x7f9963ceee38, 0, 1; -L_0x1034dc0 .part RS_0x7f9963cee748, 0, 1; -L_0x1034ac0 .part RS_0x7f9963cee748, 0, 1; -L_0x1035390 .part/pv L_0x1035250, 0, 1, 4; -L_0x1034e60 .part v0xffc5e0_0, 2, 1; -L_0x1034f00 .part RS_0x7f9963cf1808, 0, 1; -L_0x1034ff0 .part RS_0x7f9963cf1838, 0, 1; -L_0x1035650 .part/pv L_0x1018d20, 0, 1, 4; -L_0x10356f0 .part RS_0x7f9963cf1868, 0, 1; -L_0x10358d0 .part RS_0x7f9963cf1868, 0, 1; -L_0x1035a70 .part RS_0x7f9963cf1898, 3, 1; -S_0xfdd360 .scope module, "test" "SLT32" 3 327, 3 208, S_0xf6f800; - .timescale -9 -12; -P_0xfdc608 .param/l "size" 3 238, +C4<0100>; -L_0x101f7f0/d .functor NOT 1, L_0x1022490, C4<0>, C4<0>, C4<0>; -L_0x101f7f0 .delay (10000,10000,10000) L_0x101f7f0/d; -L_0x10222f0/d .functor AND 1, L_0x10226a0, L_0x1022740, L_0x101f7f0, C4<1>; -L_0x10222f0 .delay (20000,20000,20000) L_0x10222f0/d; -L_0x1023e10/d .functor OR 1, L_0x1024550, C4<0>, C4<0>, C4<0>; -L_0x1023e10 .delay (20000,20000,20000) L_0x1023e10/d; -L_0x1024700/d .functor XOR 1, RS_0x7f9963cefd08, L_0x10247b0, C4<0>, C4<0>; -L_0x1024700 .delay (40000,40000,40000) L_0x1024700/d; -L_0x10243e0/d .functor NOT 1, RS_0x7f9963cefd38, C4<0>, C4<0>, C4<0>; -L_0x10243e0 .delay (10000,10000,10000) L_0x10243e0/d; -L_0x10244d0/d .functor NOT 1, L_0x1024a50, C4<0>, C4<0>, C4<0>; -L_0x10244d0 .delay (10000,10000,10000) L_0x10244d0/d; -L_0x1024af0/d .functor AND 1, L_0x10243e0, L_0x1024c30, C4<1>, C4<1>; -L_0x1024af0 .delay (20000,20000,20000) L_0x1024af0/d; -L_0x1024850/d .functor AND 1, RS_0x7f9963cefd38, L_0x10244d0, C4<1>, C4<1>; -L_0x1024850 .delay (20000,20000,20000) L_0x1024850/d; -L_0x1024e60/d .functor AND 1, L_0x1024af0, L_0x10222f0, C4<1>, C4<1>; -L_0x1024e60 .delay (20000,20000,20000) L_0x1024e60/d; -L_0x1024f60/d .functor AND 1, L_0x1024850, L_0x10222f0, C4<1>, C4<1>; -L_0x1024f60 .delay (20000,20000,20000) L_0x1024f60/d; -L_0x10250b0/d .functor OR 1, L_0x1024e60, L_0x1024f60, C4<0>, C4<0>; -L_0x10250b0 .delay (20000,20000,20000) L_0x10250b0/d; -v0xfe4770_0 .alias "A", 3 0, v0xffb8e0_0; -RS_0x7f9963cf1448 .resolv tri, L_0x101d580, L_0x101f750, L_0x1021a20, L_0x1024140; -v0xfe4810_0 .net8 "AddSubSLTSum", 3 0, RS_0x7f9963cf1448; 4 drivers -v0xfe48b0_0 .alias "B", 3 0, v0xffba90_0; -RS_0x7f9963cf1478 .resolv tri, L_0x101cbd0, L_0x101eee0, L_0x10210e0, L_0x10238f0; -v0xfe4930_0 .net8 "CarryoutWire", 3 0, RS_0x7f9963cf1478; 4 drivers -v0xfe49e0_0 .alias "Command", 2 0, v0xffbc20_0; -RS_0x7f9963cf14a8 .resolv tri, L_0x101cae0, L_0x101ed80, L_0x1020ff0, L_0x1023800; -v0xfe4a60_0 .net8 "NewVal", 3 0, RS_0x7f9963cf14a8; 4 drivers -v0xfe4b00_0 .net "Res0OF1", 0 0, L_0x1024850; 1 drivers -v0xfe4ba0_0 .net "Res1OF0", 0 0, L_0x1024af0; 1 drivers -v0xfe4c40_0 .alias "SLTSum", 3 0, v0xffc760_0; -v0xfe4ce0_0 .alias "SLTflag", 0 0, v0xffc7e0_0; -v0xfe4d60_0 .net "SLTflag0", 0 0, L_0x1024e60; 1 drivers -v0xfe4e00_0 .net "SLTflag1", 0 0, L_0x1024f60; 1 drivers -v0xfe4ea0_0 .net "SLTon", 0 0, L_0x10222f0; 1 drivers -v0xfe4f20_0 .net *"_s49", 0 0, L_0x1022490; 1 drivers -v0xfe5040_0 .net *"_s51", 0 0, L_0x10226a0; 1 drivers -v0xfe50e0_0 .net *"_s53", 0 0, L_0x1022740; 1 drivers -v0xfe4fa0_0 .net *"_s73", 0 0, L_0x1024550; 1 drivers -v0xfe5230_0 .net/s *"_s74", 0 0, C4<0>; 1 drivers -v0xfe5350_0 .net *"_s77", 0 0, L_0x10247b0; 1 drivers -v0xfe53d0_0 .net *"_s79", 0 0, L_0x1024a50; 1 drivers -v0xfe52b0_0 .net *"_s81", 0 0, L_0x1024c30; 1 drivers -v0xfe5500_0 .alias "carryin", 3 0, v0xffbed0_0; -v0xfe5450_0 .alias "carryout", 0 0, v0xffcb10_0; -v0xfe5640_0 .net "nAddSubSLTSum", 0 0, L_0x10244d0; 1 drivers -v0xfe5580_0 .net "nCmd2", 0 0, L_0x101f7f0; 1 drivers -v0xfe5790_0 .net "nOF", 0 0, L_0x10243e0; 1 drivers -v0xfe56c0_0 .alias "overflow", 0 0, v0xffcc10_0; -v0xfe58f0_0 .alias "subtract", 3 0, v0xffcc90_0; -L_0x101cae0 .part/pv L_0x101c650, 1, 1, 4; -L_0x101cbd0 .part/pv L_0x101c9a0, 1, 1, 4; -L_0x101ccc0 .part/pv L_0x101c380, 1, 1, 4; -L_0x10008a0 .part v0xffc310_0, 1, 1; -L_0x101cf70 .part v0xffc560_0, 1, 1; -L_0x101d0a0 .part RS_0x7f9963cf1478, 0, 1; -L_0x101d580 .part/pv L_0x101d440, 1, 1, 4; -L_0x101d620 .part RS_0x7f9963cf14a8, 1, 1; -L_0x101dbc0 .part/pv L_0x101da80, 1, 1, 4; -L_0x101dc60 .part RS_0x7f9963cf1448, 1, 1; -L_0x101de00 .part RS_0x7f9963cf1448, 1, 1; -L_0x101ed80 .part/pv L_0x101e8f0, 2, 1, 4; -L_0x101eee0 .part/pv L_0x101ec40, 2, 1, 4; -L_0x101efd0 .part/pv L_0x101e620, 2, 1, 4; -L_0x101f140 .part v0xffc310_0, 2, 1; -L_0x101f1e0 .part v0xffc560_0, 2, 1; -L_0x101f3a0 .part RS_0x7f9963cf1478, 1, 1; -L_0x101f750 .part/pv L_0x101f610, 2, 1, 4; -L_0x101f920 .part RS_0x7f9963cf14a8, 2, 1; -L_0x101fdd0 .part/pv L_0x101fc90, 2, 1, 4; -L_0x101f880 .part RS_0x7f9963cf1448, 2, 1; -L_0x101ff70 .part RS_0x7f9963cf1448, 2, 1; -L_0x1020ff0 .part/pv L_0x1020b40, 3, 1, 4; -L_0x10210e0 .part/pv L_0x1020e90, 3, 1, 4; -L_0x1020060 .part/pv L_0x1020870, 3, 1, 4; -L_0x10212f0 .part v0xffc310_0, 3, 1; -L_0x10211d0 .part v0xffc560_0, 3, 1; -L_0x1021500 .part RS_0x7f9963cf1478, 2, 1; -L_0x1021a20 .part/pv L_0x10218e0, 3, 1, 4; -L_0x1021ac0 .part RS_0x7f9963cf14a8, 3, 1; -L_0x1022050 .part/pv L_0x1021f10, 3, 1, 4; -L_0x10220f0 .part RS_0x7f9963cf1448, 3, 1; -L_0x1021bb0 .part RS_0x7f9963cf1448, 3, 1; -L_0x1022490 .part v0xffc5e0_0, 2, 1; -L_0x10226a0 .part v0xffc5e0_0, 0, 1; -L_0x1022740 .part v0xffc5e0_0, 1, 1; -L_0x1023800 .part/pv L_0x1023350, 0, 1, 4; -L_0x10238f0 .part/pv L_0x10236a0, 0, 1, 4; -L_0x1022830 .part/pv L_0x1023080, 0, 1, 4; -L_0x1023b20 .part v0xffc310_0, 0, 1; -L_0x10239e0 .part v0xffc560_0, 0, 1; -L_0x1023d10 .part RS_0x7f9963cefd68, 0, 1; -L_0x1024140 .part/pv L_0x1024000, 0, 1, 4; -L_0x10241e0 .part RS_0x7f9963cf14a8, 0, 1; -L_0x1024550 .part RS_0x7f9963cf1478, 3, 1; -L_0x10247b0 .part RS_0x7f9963cf1478, 2, 1; -L_0x1024a50 .part RS_0x7f9963cf1448, 3, 1; -L_0x1024c30 .part RS_0x7f9963cf14a8, 3, 1; -L_0x1025660 .part/pv L_0x1025520, 0, 1, 4; -L_0x1025700 .part RS_0x7f9963cf1448, 0, 1; -S_0xfe3750 .scope module, "attempt2" "MiddleAddSubSLT" 3 234, 3 88, S_0xfdd360; - .timescale -9 -12; -L_0x1022530/d .functor NOT 1, L_0x10239e0, C4<0>, C4<0>, C4<0>; -L_0x1022530 .delay (10000,10000,10000) L_0x1022530/d; -L_0x1022f20/d .functor NOT 1, L_0x1022fe0, C4<0>, C4<0>, C4<0>; -L_0x1022f20 .delay (10000,10000,10000) L_0x1022f20/d; -L_0x1023080/d .functor AND 1, L_0x10231c0, L_0x1022f20, C4<1>, C4<1>; -L_0x1023080 .delay (20000,20000,20000) L_0x1023080/d; -L_0x1023260/d .functor XOR 1, L_0x1023b20, L_0x1022cb0, C4<0>, C4<0>; -L_0x1023260 .delay (40000,40000,40000) L_0x1023260/d; -L_0x1023350/d .functor XOR 1, L_0x1023260, L_0x1023d10, C4<0>, C4<0>; -L_0x1023350 .delay (40000,40000,40000) L_0x1023350/d; -L_0x1023440/d .functor AND 1, L_0x1023b20, L_0x1022cb0, C4<1>, C4<1>; -L_0x1023440 .delay (20000,20000,20000) L_0x1023440/d; -L_0x10235b0/d .functor AND 1, L_0x1023260, L_0x1023d10, C4<1>, C4<1>; -L_0x10235b0 .delay (20000,20000,20000) L_0x10235b0/d; -L_0x10236a0/d .functor OR 1, L_0x1023440, L_0x10235b0, C4<0>, C4<0>; -L_0x10236a0 .delay (20000,20000,20000) L_0x10236a0/d; -v0xfe3dd0_0 .net "A", 0 0, L_0x1023b20; 1 drivers -v0xfe3e90_0 .net "AandB", 0 0, L_0x1023440; 1 drivers -v0xfe3f30_0 .net "AddSubSLTSum", 0 0, L_0x1023350; 1 drivers -v0xfe3fd0_0 .net "AxorB", 0 0, L_0x1023260; 1 drivers -v0xfe4050_0 .net "B", 0 0, L_0x10239e0; 1 drivers -v0xfe4100_0 .net "BornB", 0 0, L_0x1022cb0; 1 drivers -v0xfe41c0_0 .net "CINandAxorB", 0 0, L_0x10235b0; 1 drivers -v0xfe4240_0 .alias "Command", 2 0, v0xffbc20_0; -v0xfe42c0_0 .net *"_s3", 0 0, L_0x1022fe0; 1 drivers -v0xfe4340_0 .net *"_s5", 0 0, L_0x10231c0; 1 drivers -v0xfe43e0_0 .net "carryin", 0 0, L_0x1023d10; 1 drivers -v0xfe4480_0 .net "carryout", 0 0, L_0x10236a0; 1 drivers -v0xfe4520_0 .net "nB", 0 0, L_0x1022530; 1 drivers -v0xfe45d0_0 .net "nCmd2", 0 0, L_0x1022f20; 1 drivers -v0xfe46d0_0 .net "subtract", 0 0, L_0x1023080; 1 drivers -L_0x1022e80 .part v0xffc5e0_0, 0, 1; -L_0x1022fe0 .part v0xffc5e0_0, 2, 1; -L_0x10231c0 .part v0xffc5e0_0, 0, 1; -S_0xfe3840 .scope module, "mux0" "TwoInMux" 3 104, 3 8, S_0xfe3750; - .timescale -9 -12; -L_0x10229f0/d .functor NOT 1, L_0x1022e80, C4<0>, C4<0>, C4<0>; -L_0x10229f0 .delay (10000,10000,10000) L_0x10229f0/d; -L_0x1022a90/d .functor AND 1, L_0x10239e0, L_0x10229f0, C4<1>, C4<1>; -L_0x1022a90 .delay (20000,20000,20000) L_0x1022a90/d; -L_0x1022ba0/d .functor AND 1, L_0x1022530, L_0x1022e80, C4<1>, C4<1>; -L_0x1022ba0 .delay (20000,20000,20000) L_0x1022ba0/d; -L_0x1022cb0/d .functor OR 1, L_0x1022a90, L_0x1022ba0, C4<0>, C4<0>; -L_0x1022cb0 .delay (20000,20000,20000) L_0x1022cb0/d; -v0xfe3930_0 .net "S", 0 0, L_0x1022e80; 1 drivers -v0xfe39f0_0 .alias "in0", 0 0, v0xfe4050_0; -v0xfe3a90_0 .alias "in1", 0 0, v0xfe4520_0; -v0xfe3b30_0 .net "nS", 0 0, L_0x10229f0; 1 drivers -v0xfe3bb0_0 .net "out0", 0 0, L_0x1022a90; 1 drivers -v0xfe3c50_0 .net "out1", 0 0, L_0x1022ba0; 1 drivers -v0xfe3d30_0 .alias "outfinal", 0 0, v0xfe4100_0; -S_0xfe31e0 .scope module, "setSLTresult" "TwoInMux" 3 235, 3 8, S_0xfdd360; - .timescale -9 -12; -L_0x1023bc0/d .functor NOT 1, L_0x10222f0, C4<0>, C4<0>, C4<0>; -L_0x1023bc0 .delay (10000,10000,10000) L_0x1023bc0/d; -L_0x1023c60/d .functor AND 1, L_0x10241e0, L_0x1023bc0, C4<1>, C4<1>; -L_0x1023c60 .delay (20000,20000,20000) L_0x1023c60/d; -L_0x1023f60/d .functor AND 1, C4<0>, L_0x10222f0, C4<1>, C4<1>; -L_0x1023f60 .delay (20000,20000,20000) L_0x1023f60/d; -L_0x1024000/d .functor OR 1, L_0x1023c60, L_0x1023f60, C4<0>, C4<0>; -L_0x1024000 .delay (20000,20000,20000) L_0x1024000/d; -v0xfe32d0_0 .alias "S", 0 0, v0xfe4ea0_0; -v0xfe3370_0 .net "in0", 0 0, L_0x10241e0; 1 drivers -v0xfe3410_0 .net "in1", 0 0, C4<0>; 1 drivers -v0xfe34b0_0 .net "nS", 0 0, L_0x1023bc0; 1 drivers -v0xfe3530_0 .net "out0", 0 0, L_0x1023c60; 1 drivers -v0xfe35d0_0 .net "out1", 0 0, L_0x1023f60; 1 drivers -v0xfe36b0_0 .net "outfinal", 0 0, L_0x1024000; 1 drivers -S_0xfe2c70 .scope module, "FinalSLT" "TwoInMux" 3 261, 3 8, S_0xfdd360; - .timescale -9 -12; -L_0x10251c0/d .functor NOT 1, L_0x10250b0, C4<0>, C4<0>, C4<0>; -L_0x10251c0 .delay (10000,10000,10000) L_0x10251c0/d; -L_0x10252a0/d .functor AND 1, L_0x1025700, L_0x10251c0, C4<1>, C4<1>; -L_0x10252a0 .delay (20000,20000,20000) L_0x10252a0/d; -L_0x10253b0/d .functor AND 1, L_0x10250b0, L_0x10250b0, C4<1>, C4<1>; -L_0x10253b0 .delay (20000,20000,20000) L_0x10253b0/d; -L_0x1025520/d .functor OR 1, L_0x10252a0, L_0x10253b0, C4<0>, C4<0>; -L_0x1025520 .delay (20000,20000,20000) L_0x1025520/d; -v0xfe2d60_0 .alias "S", 0 0, v0xffc7e0_0; -v0xfe2e20_0 .net "in0", 0 0, L_0x1025700; 1 drivers -v0xfe2ec0_0 .alias "in1", 0 0, v0xffc7e0_0; -v0xfe2f70_0 .net "nS", 0 0, L_0x10251c0; 1 drivers -v0xfe3020_0 .net "out0", 0 0, L_0x10252a0; 1 drivers -v0xfe30a0_0 .net "out1", 0 0, L_0x10253b0; 1 drivers -v0xfe3140_0 .net "outfinal", 0 0, L_0x1025520; 1 drivers -S_0xfe0f60 .scope generate, "sltbits[1]" "sltbits[1]" 3 240, 3 240, S_0xfdd360; - .timescale -9 -12; -P_0xfe0818 .param/l "i" 3 240, +C4<01>; -S_0xfe1c50 .scope module, "attempt" "MiddleAddSubSLT" 3 242, 3 88, S_0xfe0f60; - .timescale -9 -12; -L_0x101b9a0/d .functor NOT 1, L_0x101cf70, C4<0>, C4<0>, C4<0>; -L_0x101b9a0 .delay (10000,10000,10000) L_0x101b9a0/d; -L_0x101c240/d .functor NOT 1, L_0x101c2e0, C4<0>, C4<0>, C4<0>; -L_0x101c240 .delay (10000,10000,10000) L_0x101c240/d; -L_0x101c380/d .functor AND 1, L_0x101c4c0, L_0x101c240, C4<1>, C4<1>; -L_0x101c380 .delay (20000,20000,20000) L_0x101c380/d; -L_0x101c560/d .functor XOR 1, L_0x10008a0, L_0x101c010, C4<0>, C4<0>; -L_0x101c560 .delay (40000,40000,40000) L_0x101c560/d; -L_0x101c650/d .functor XOR 1, L_0x101c560, L_0x101d0a0, C4<0>, C4<0>; -L_0x101c650 .delay (40000,40000,40000) L_0x101c650/d; -L_0x101c740/d .functor AND 1, L_0x10008a0, L_0x101c010, C4<1>, C4<1>; -L_0x101c740 .delay (20000,20000,20000) L_0x101c740/d; -L_0x101c8b0/d .functor AND 1, L_0x101c560, L_0x101d0a0, C4<1>, C4<1>; -L_0x101c8b0 .delay (20000,20000,20000) L_0x101c8b0/d; -L_0x101c9a0/d .functor OR 1, L_0x101c740, L_0x101c8b0, C4<0>, C4<0>; -L_0x101c9a0 .delay (20000,20000,20000) L_0x101c9a0/d; -v0xfe22d0_0 .net "A", 0 0, L_0x10008a0; 1 drivers -v0xfe2390_0 .net "AandB", 0 0, L_0x101c740; 1 drivers -v0xfe2430_0 .net "AddSubSLTSum", 0 0, L_0x101c650; 1 drivers -v0xfe24d0_0 .net "AxorB", 0 0, L_0x101c560; 1 drivers -v0xfe2550_0 .net "B", 0 0, L_0x101cf70; 1 drivers -v0xfe2600_0 .net "BornB", 0 0, L_0x101c010; 1 drivers -v0xfe26c0_0 .net "CINandAxorB", 0 0, L_0x101c8b0; 1 drivers -v0xfe2740_0 .alias "Command", 2 0, v0xffbc20_0; -v0xfe27c0_0 .net *"_s3", 0 0, L_0x101c2e0; 1 drivers -v0xfe2840_0 .net *"_s5", 0 0, L_0x101c4c0; 1 drivers -v0xfe28e0_0 .net "carryin", 0 0, L_0x101d0a0; 1 drivers -v0xfe2980_0 .net "carryout", 0 0, L_0x101c9a0; 1 drivers -v0xfe2a20_0 .net "nB", 0 0, L_0x101b9a0; 1 drivers -v0xfe2ad0_0 .net "nCmd2", 0 0, L_0x101c240; 1 drivers -v0xfe2bd0_0 .net "subtract", 0 0, L_0x101c380; 1 drivers -L_0x101c1a0 .part v0xffc5e0_0, 0, 1; -L_0x101c2e0 .part v0xffc5e0_0, 2, 1; -L_0x101c4c0 .part v0xffc5e0_0, 0, 1; -S_0xfe1d40 .scope module, "mux0" "TwoInMux" 3 104, 3 8, S_0xfe1c50; - .timescale -9 -12; -L_0x101bd90/d .functor NOT 1, L_0x101c1a0, C4<0>, C4<0>, C4<0>; -L_0x101bd90 .delay (10000,10000,10000) L_0x101bd90/d; -L_0x101be30/d .functor AND 1, L_0x101cf70, L_0x101bd90, C4<1>, C4<1>; -L_0x101be30 .delay (20000,20000,20000) L_0x101be30/d; -L_0x101bf20/d .functor AND 1, L_0x101b9a0, L_0x101c1a0, C4<1>, C4<1>; -L_0x101bf20 .delay (20000,20000,20000) L_0x101bf20/d; -L_0x101c010/d .functor OR 1, L_0x101be30, L_0x101bf20, C4<0>, C4<0>; -L_0x101c010 .delay (20000,20000,20000) L_0x101c010/d; -v0xfe1e30_0 .net "S", 0 0, L_0x101c1a0; 1 drivers -v0xfe1ef0_0 .alias "in0", 0 0, v0xfe2550_0; -v0xfe1f90_0 .alias "in1", 0 0, v0xfe2a20_0; -v0xfe2030_0 .net "nS", 0 0, L_0x101bd90; 1 drivers -v0xfe20b0_0 .net "out0", 0 0, L_0x101be30; 1 drivers -v0xfe2150_0 .net "out1", 0 0, L_0x101bf20; 1 drivers -v0xfe2230_0 .alias "outfinal", 0 0, v0xfe2600_0; -S_0xfe16e0 .scope module, "setSLTres2" "TwoInMux" 3 243, 3 8, S_0xfe0f60; - .timescale -9 -12; -L_0x101d140/d .functor NOT 1, L_0x10222f0, C4<0>, C4<0>, C4<0>; -L_0x101d140 .delay (10000,10000,10000) L_0x101d140/d; -L_0x101d2b0/d .functor AND 1, L_0x101d620, L_0x101d140, C4<1>, C4<1>; -L_0x101d2b0 .delay (20000,20000,20000) L_0x101d2b0/d; -L_0x101d3a0/d .functor AND 1, C4<0>, L_0x10222f0, C4<1>, C4<1>; -L_0x101d3a0 .delay (20000,20000,20000) L_0x101d3a0/d; -L_0x101d440/d .functor OR 1, L_0x101d2b0, L_0x101d3a0, C4<0>, C4<0>; -L_0x101d440 .delay (20000,20000,20000) L_0x101d440/d; -v0xfe17d0_0 .alias "S", 0 0, v0xfe4ea0_0; -v0xfe1870_0 .net "in0", 0 0, L_0x101d620; 1 drivers -v0xfe1910_0 .net "in1", 0 0, C4<0>; 1 drivers -v0xfe19b0_0 .net "nS", 0 0, L_0x101d140; 1 drivers -v0xfe1a30_0 .net "out0", 0 0, L_0x101d2b0; 1 drivers -v0xfe1ad0_0 .net "out1", 0 0, L_0x101d3a0; 1 drivers -v0xfe1bb0_0 .net "outfinal", 0 0, L_0x101d440; 1 drivers -S_0xfe10d0 .scope module, "setSLTres3" "TwoInMux" 3 244, 3 8, S_0xfe0f60; - .timescale -9 -12; -L_0x101d800/d .functor NOT 1, L_0x10222f0, C4<0>, C4<0>, C4<0>; -L_0x101d800 .delay (10000,10000,10000) L_0x101d800/d; -L_0x101d8f0/d .functor AND 1, L_0x101dc60, L_0x101d800, C4<1>, C4<1>; -L_0x101d8f0 .delay (20000,20000,20000) L_0x101d8f0/d; -L_0x101d9e0/d .functor AND 1, L_0x101de00, L_0x10222f0, C4<1>, C4<1>; -L_0x101d9e0 .delay (20000,20000,20000) L_0x101d9e0/d; -L_0x101da80/d .functor OR 1, L_0x101d8f0, L_0x101d9e0, C4<0>, C4<0>; -L_0x101da80 .delay (20000,20000,20000) L_0x101da80/d; -v0xfe11c0_0 .alias "S", 0 0, v0xfe4ea0_0; -v0xfe12d0_0 .net "in0", 0 0, L_0x101dc60; 1 drivers -v0xfe1370_0 .net "in1", 0 0, L_0x101de00; 1 drivers -v0xfe1410_0 .net "nS", 0 0, L_0x101d800; 1 drivers -v0xfe14c0_0 .net "out0", 0 0, L_0x101d8f0; 1 drivers -v0xfe1560_0 .net "out1", 0 0, L_0x101d9e0; 1 drivers -v0xfe1640_0 .net "outfinal", 0 0, L_0x101da80; 1 drivers -S_0xfdf1b0 .scope generate, "sltbits[2]" "sltbits[2]" 3 240, 3 240, S_0xfdd360; - .timescale -9 -12; -P_0xfdeb58 .param/l "i" 3 240, +C4<010>; -S_0xfdfde0 .scope module, "attempt" "MiddleAddSubSLT" 3 242, 3 88, S_0xfdf1b0; - .timescale -9 -12; -L_0x101dea0/d .functor NOT 1, L_0x101f1e0, C4<0>, C4<0>, C4<0>; -L_0x101dea0 .delay (10000,10000,10000) L_0x101dea0/d; -L_0x101e4e0/d .functor NOT 1, L_0x101e580, C4<0>, C4<0>, C4<0>; -L_0x101e4e0 .delay (10000,10000,10000) L_0x101e4e0/d; -L_0x101e620/d .functor AND 1, L_0x101e760, L_0x101e4e0, C4<1>, C4<1>; -L_0x101e620 .delay (20000,20000,20000) L_0x101e620/d; -L_0x101e800/d .functor XOR 1, L_0x101f140, L_0x101e2b0, C4<0>, C4<0>; -L_0x101e800 .delay (40000,40000,40000) L_0x101e800/d; -L_0x101e8f0/d .functor XOR 1, L_0x101e800, L_0x101f3a0, C4<0>, C4<0>; -L_0x101e8f0 .delay (40000,40000,40000) L_0x101e8f0/d; -L_0x101e9e0/d .functor AND 1, L_0x101f140, L_0x101e2b0, C4<1>, C4<1>; -L_0x101e9e0 .delay (20000,20000,20000) L_0x101e9e0/d; -L_0x101eb50/d .functor AND 1, L_0x101e800, L_0x101f3a0, C4<1>, C4<1>; -L_0x101eb50 .delay (20000,20000,20000) L_0x101eb50/d; -L_0x101ec40/d .functor OR 1, L_0x101e9e0, L_0x101eb50, C4<0>, C4<0>; -L_0x101ec40 .delay (20000,20000,20000) L_0x101ec40/d; -v0xfe0460_0 .net "A", 0 0, L_0x101f140; 1 drivers -v0xfe0520_0 .net "AandB", 0 0, L_0x101e9e0; 1 drivers -v0xfe05c0_0 .net "AddSubSLTSum", 0 0, L_0x101e8f0; 1 drivers -v0xfe0660_0 .net "AxorB", 0 0, L_0x101e800; 1 drivers -v0xfe06e0_0 .net "B", 0 0, L_0x101f1e0; 1 drivers -v0xfe0790_0 .net "BornB", 0 0, L_0x101e2b0; 1 drivers -v0xfe0850_0 .net "CINandAxorB", 0 0, L_0x101eb50; 1 drivers -v0xfe08d0_0 .alias "Command", 2 0, v0xffbc20_0; -v0xfd81f0_0 .net *"_s3", 0 0, L_0x101e580; 1 drivers -v0xfd8270_0 .net *"_s5", 0 0, L_0x101e760; 1 drivers -v0xfe0bd0_0 .net "carryin", 0 0, L_0x101f3a0; 1 drivers -v0xfe0c70_0 .net "carryout", 0 0, L_0x101ec40; 1 drivers -v0xfe0d10_0 .net "nB", 0 0, L_0x101dea0; 1 drivers -v0xfe0dc0_0 .net "nCmd2", 0 0, L_0x101e4e0; 1 drivers -v0xfe0ec0_0 .net "subtract", 0 0, L_0x101e620; 1 drivers -L_0x101e440 .part v0xffc5e0_0, 0, 1; -L_0x101e580 .part v0xffc5e0_0, 2, 1; -L_0x101e760 .part v0xffc5e0_0, 0, 1; -S_0xfdfed0 .scope module, "mux0" "TwoInMux" 3 104, 3 8, S_0xfdfde0; - .timescale -9 -12; -L_0x101e030/d .functor NOT 1, L_0x101e440, C4<0>, C4<0>, C4<0>; -L_0x101e030 .delay (10000,10000,10000) L_0x101e030/d; -L_0x101e0d0/d .functor AND 1, L_0x101f1e0, L_0x101e030, C4<1>, C4<1>; -L_0x101e0d0 .delay (20000,20000,20000) L_0x101e0d0/d; -L_0x101e1c0/d .functor AND 1, L_0x101dea0, L_0x101e440, C4<1>, C4<1>; -L_0x101e1c0 .delay (20000,20000,20000) L_0x101e1c0/d; -L_0x101e2b0/d .functor OR 1, L_0x101e0d0, L_0x101e1c0, C4<0>, C4<0>; -L_0x101e2b0 .delay (20000,20000,20000) L_0x101e2b0/d; -v0xfdffc0_0 .net "S", 0 0, L_0x101e440; 1 drivers -v0xfe0080_0 .alias "in0", 0 0, v0xfe06e0_0; -v0xfe0120_0 .alias "in1", 0 0, v0xfe0d10_0; -v0xfe01c0_0 .net "nS", 0 0, L_0x101e030; 1 drivers -v0xfe0240_0 .net "out0", 0 0, L_0x101e0d0; 1 drivers -v0xfe02e0_0 .net "out1", 0 0, L_0x101e1c0; 1 drivers -v0xfe03c0_0 .alias "outfinal", 0 0, v0xfe0790_0; -S_0xfdf870 .scope module, "setSLTres2" "TwoInMux" 3 243, 3 8, S_0xfdf1b0; - .timescale -9 -12; -L_0x101dda0/d .functor NOT 1, L_0x10222f0, C4<0>, C4<0>, C4<0>; -L_0x101dda0 .delay (10000,10000,10000) L_0x101dda0/d; -L_0x101f4d0/d .functor AND 1, L_0x101f920, L_0x101dda0, C4<1>, C4<1>; -L_0x101f4d0 .delay (20000,20000,20000) L_0x101f4d0/d; -L_0x101f570/d .functor AND 1, C4<0>, L_0x10222f0, C4<1>, C4<1>; -L_0x101f570 .delay (20000,20000,20000) L_0x101f570/d; -L_0x101f610/d .functor OR 1, L_0x101f4d0, L_0x101f570, C4<0>, C4<0>; -L_0x101f610 .delay (20000,20000,20000) L_0x101f610/d; -v0xfdf960_0 .alias "S", 0 0, v0xfe4ea0_0; -v0xfdfa00_0 .net "in0", 0 0, L_0x101f920; 1 drivers -v0xfdfaa0_0 .net "in1", 0 0, C4<0>; 1 drivers -v0xfdfb40_0 .net "nS", 0 0, L_0x101dda0; 1 drivers -v0xfdfbc0_0 .net "out0", 0 0, L_0x101f4d0; 1 drivers -v0xfdfc60_0 .net "out1", 0 0, L_0x101f570; 1 drivers -v0xfdfd40_0 .net "outfinal", 0 0, L_0x101f610; 1 drivers -S_0xfdf320 .scope module, "setSLTres3" "TwoInMux" 3 244, 3 8, S_0xfdf1b0; - .timescale -9 -12; -L_0x101fa50/d .functor NOT 1, L_0x10222f0, C4<0>, C4<0>, C4<0>; -L_0x101fa50 .delay (10000,10000,10000) L_0x101fa50/d; -L_0x101fb00/d .functor AND 1, L_0x101f880, L_0x101fa50, C4<1>, C4<1>; -L_0x101fb00 .delay (20000,20000,20000) L_0x101fb00/d; -L_0x101fbf0/d .functor AND 1, L_0x101ff70, L_0x10222f0, C4<1>, C4<1>; -L_0x101fbf0 .delay (20000,20000,20000) L_0x101fbf0/d; -L_0x101fc90/d .functor OR 1, L_0x101fb00, L_0x101fbf0, C4<0>, C4<0>; -L_0x101fc90 .delay (20000,20000,20000) L_0x101fc90/d; -v0xfdf410_0 .alias "S", 0 0, v0xfe4ea0_0; -v0xfdf490_0 .net "in0", 0 0, L_0x101f880; 1 drivers -v0xfdf530_0 .net "in1", 0 0, L_0x101ff70; 1 drivers -v0xfdf5d0_0 .net "nS", 0 0, L_0x101fa50; 1 drivers -v0xfdf650_0 .net "out0", 0 0, L_0x101fb00; 1 drivers -v0xfdf6f0_0 .net "out1", 0 0, L_0x101fbf0; 1 drivers -v0xfdf7d0_0 .net "outfinal", 0 0, L_0x101fc90; 1 drivers -S_0xfdd4d0 .scope generate, "sltbits[3]" "sltbits[3]" 3 240, 3 240, S_0xfdd360; - .timescale -9 -12; -P_0xfdd5c8 .param/l "i" 3 240, +C4<011>; -S_0xfde120 .scope module, "attempt" "MiddleAddSubSLT" 3 242, 3 88, S_0xfdd4d0; - .timescale -9 -12; -L_0x101fe70/d .functor NOT 1, L_0x10211d0, C4<0>, C4<0>, C4<0>; -L_0x101fe70 .delay (10000,10000,10000) L_0x101fe70/d; -L_0x1020710/d .functor NOT 1, L_0x10207d0, C4<0>, C4<0>, C4<0>; -L_0x1020710 .delay (10000,10000,10000) L_0x1020710/d; -L_0x1020870/d .functor AND 1, L_0x10209b0, L_0x1020710, C4<1>, C4<1>; -L_0x1020870 .delay (20000,20000,20000) L_0x1020870/d; -L_0x1020a50/d .functor XOR 1, L_0x10212f0, L_0x10204a0, C4<0>, C4<0>; -L_0x1020a50 .delay (40000,40000,40000) L_0x1020a50/d; -L_0x1020b40/d .functor XOR 1, L_0x1020a50, L_0x1021500, C4<0>, C4<0>; -L_0x1020b40 .delay (40000,40000,40000) L_0x1020b40/d; -L_0x1020c30/d .functor AND 1, L_0x10212f0, L_0x10204a0, C4<1>, C4<1>; -L_0x1020c30 .delay (20000,20000,20000) L_0x1020c30/d; -L_0x1020da0/d .functor AND 1, L_0x1020a50, L_0x1021500, C4<1>, C4<1>; -L_0x1020da0 .delay (20000,20000,20000) L_0x1020da0/d; -L_0x1020e90/d .functor OR 1, L_0x1020c30, L_0x1020da0, C4<0>, C4<0>; -L_0x1020e90 .delay (20000,20000,20000) L_0x1020e90/d; -v0xfde7a0_0 .net "A", 0 0, L_0x10212f0; 1 drivers -v0xfde860_0 .net "AandB", 0 0, L_0x1020c30; 1 drivers -v0xfde900_0 .net "AddSubSLTSum", 0 0, L_0x1020b40; 1 drivers -v0xfde9a0_0 .net "AxorB", 0 0, L_0x1020a50; 1 drivers -v0xfdea20_0 .net "B", 0 0, L_0x10211d0; 1 drivers -v0xfdead0_0 .net "BornB", 0 0, L_0x10204a0; 1 drivers -v0xfdeb90_0 .net "CINandAxorB", 0 0, L_0x1020da0; 1 drivers -v0xfdec10_0 .alias "Command", 2 0, v0xffbc20_0; -v0xfdec90_0 .net *"_s3", 0 0, L_0x10207d0; 1 drivers -v0xfded10_0 .net *"_s5", 0 0, L_0x10209b0; 1 drivers -v0xfdedb0_0 .net "carryin", 0 0, L_0x1021500; 1 drivers -v0xfdee50_0 .net "carryout", 0 0, L_0x1020e90; 1 drivers -v0xfdef60_0 .net "nB", 0 0, L_0x101fe70; 1 drivers -v0xfdf010_0 .net "nCmd2", 0 0, L_0x1020710; 1 drivers -v0xfdf110_0 .net "subtract", 0 0, L_0x1020870; 1 drivers -L_0x1020670 .part v0xffc5e0_0, 0, 1; -L_0x10207d0 .part v0xffc5e0_0, 2, 1; -L_0x10209b0 .part v0xffc5e0_0, 0, 1; -S_0xfde210 .scope module, "mux0" "TwoInMux" 3 104, 3 8, S_0xfde120; - .timescale -9 -12; -L_0x1020200/d .functor NOT 1, L_0x1020670, C4<0>, C4<0>, C4<0>; -L_0x1020200 .delay (10000,10000,10000) L_0x1020200/d; -L_0x10202a0/d .functor AND 1, L_0x10211d0, L_0x1020200, C4<1>, C4<1>; -L_0x10202a0 .delay (20000,20000,20000) L_0x10202a0/d; -L_0x1020390/d .functor AND 1, L_0x101fe70, L_0x1020670, C4<1>, C4<1>; -L_0x1020390 .delay (20000,20000,20000) L_0x1020390/d; -L_0x10204a0/d .functor OR 1, L_0x10202a0, L_0x1020390, C4<0>, C4<0>; -L_0x10204a0 .delay (20000,20000,20000) L_0x10204a0/d; -v0xfde300_0 .net "S", 0 0, L_0x1020670; 1 drivers -v0xfde3c0_0 .alias "in0", 0 0, v0xfdea20_0; -v0xfde460_0 .alias "in1", 0 0, v0xfdef60_0; -v0xfde500_0 .net "nS", 0 0, L_0x1020200; 1 drivers -v0xfde580_0 .net "out0", 0 0, L_0x10202a0; 1 drivers -v0xfde620_0 .net "out1", 0 0, L_0x1020390; 1 drivers -v0xfde700_0 .alias "outfinal", 0 0, v0xfdead0_0; -S_0xfddbd0 .scope module, "setSLTres2" "TwoInMux" 3 243, 3 8, S_0xfdd4d0; - .timescale -9 -12; -L_0x1021390/d .functor NOT 1, L_0x10222f0, C4<0>, C4<0>, C4<0>; -L_0x1021390 .delay (10000,10000,10000) L_0x1021390/d; -L_0x10213f0/d .functor AND 1, L_0x1021ac0, L_0x1021390, C4<1>, C4<1>; -L_0x10213f0 .delay (20000,20000,20000) L_0x10213f0/d; -L_0x101d230/d .functor AND 1, C4<0>, L_0x10222f0, C4<1>, C4<1>; -L_0x101d230 .delay (20000,20000,20000) L_0x101d230/d; -L_0x10218e0/d .functor OR 1, L_0x10213f0, L_0x101d230, C4<0>, C4<0>; -L_0x10218e0 .delay (20000,20000,20000) L_0x10218e0/d; -v0xfddcc0_0 .alias "S", 0 0, v0xfe4ea0_0; -v0xfddd60_0 .net "in0", 0 0, L_0x1021ac0; 1 drivers -v0xfddde0_0 .net "in1", 0 0, C4<0>; 1 drivers -v0xfdde80_0 .net "nS", 0 0, L_0x1021390; 1 drivers -v0xfddf00_0 .net "out0", 0 0, L_0x10213f0; 1 drivers -v0xfddfa0_0 .net "out1", 0 0, L_0x101d230; 1 drivers -v0xfde080_0 .net "outfinal", 0 0, L_0x10218e0; 1 drivers -S_0xfdd660 .scope module, "setSLTres3" "TwoInMux" 3 244, 3 8, S_0xfdd4d0; - .timescale -9 -12; -L_0x1021630/d .functor NOT 1, L_0x10222f0, C4<0>, C4<0>, C4<0>; -L_0x1021630 .delay (10000,10000,10000) L_0x1021630/d; -L_0x1021d60/d .functor AND 1, L_0x10220f0, L_0x1021630, C4<1>, C4<1>; -L_0x1021d60 .delay (20000,20000,20000) L_0x1021d60/d; -L_0x1021e70/d .functor AND 1, L_0x1021bb0, L_0x10222f0, C4<1>, C4<1>; -L_0x1021e70 .delay (20000,20000,20000) L_0x1021e70/d; -L_0x1021f10/d .functor OR 1, L_0x1021d60, L_0x1021e70, C4<0>, C4<0>; -L_0x1021f10 .delay (20000,20000,20000) L_0x1021f10/d; -v0xfdd750_0 .alias "S", 0 0, v0xfe4ea0_0; -v0xfdd7f0_0 .net "in0", 0 0, L_0x10220f0; 1 drivers -v0xfdd890_0 .net "in1", 0 0, L_0x1021bb0; 1 drivers -v0xfdd930_0 .net "nS", 0 0, L_0x1021630; 1 drivers -v0xfdd9b0_0 .net "out0", 0 0, L_0x1021d60; 1 drivers -v0xfdda50_0 .net "out1", 0 0, L_0x1021e70; 1 drivers -v0xfddb30_0 .net "outfinal", 0 0, L_0x1021f10; 1 drivers -S_0xfd84e0 .scope module, "trial" "AddSubSLT32" 3 328, 3 166, S_0xf6f800; - .timescale -9 -12; -P_0xfd85d8 .param/l "size" 3 180, +C4<0100>; -L_0x102ae70/d .functor OR 1, L_0x102b130, C4<0>, C4<0>, C4<0>; -L_0x102ae70 .delay (20000,20000,20000) L_0x102ae70/d; -L_0x1023db0/d .functor XOR 1, RS_0x7f9963cefd08, L_0x102b3a0, C4<0>, C4<0>; -L_0x1023db0 .delay (40000,40000,40000) L_0x1023db0/d; -v0xfdcbf0_0 .alias "A", 3 0, v0xffb8e0_0; -v0xfdcc90_0 .alias "AddSubSLTSum", 3 0, v0xffc3b0_0; -v0xfdcd30_0 .alias "B", 3 0, v0xffba90_0; -RS_0x7f9963cefc18 .resolv tri, L_0x10268f0, L_0x1027e10, L_0x1014a00, L_0x102abe0; -v0xfdcdb0_0 .net8 "CarryoutWire", 3 0, RS_0x7f9963cefc18; 4 drivers -v0xfdce30_0 .alias "Command", 2 0, v0xffbc20_0; -v0xfdceb0_0 .net *"_s40", 0 0, L_0x102b130; 1 drivers -v0xfdcf50_0 .net/s *"_s41", 0 0, C4<0>; 1 drivers -v0xfdcff0_0 .net *"_s44", 0 0, L_0x102b3a0; 1 drivers -v0xfdd0e0_0 .alias "carryin", 3 0, v0xffbed0_0; -v0xfdd180_0 .alias "carryout", 0 0, v0xffcb10_0; -v0xfdd220_0 .alias "overflow", 0 0, v0xffcc10_0; -v0xfdd2c0_0 .alias "subtract", 3 0, v0xffcc90_0; -L_0x10267e0 .part/pv L_0x1026330, 1, 1, 4; -L_0x10268f0 .part/pv L_0x1026680, 1, 1, 4; -L_0x10269e0 .part/pv L_0x1026060, 1, 1, 4; -L_0x1026ad0 .part v0xffc310_0, 1, 1; -L_0x1026b70 .part v0xffc560_0, 1, 1; -L_0x1026ca0 .part RS_0x7f9963cefc18, 0, 1; -L_0x1027d20 .part/pv L_0x1027870, 2, 1, 4; -L_0x1027e10 .part/pv L_0x1027bc0, 2, 1, 4; -L_0x1027f50 .part/pv L_0x10275a0, 2, 1, 4; -L_0x1028040 .part v0xffc310_0, 2, 1; -L_0x1028140 .part v0xffc560_0, 2, 1; -L_0x1028270 .part RS_0x7f9963cefc18, 1, 1; -L_0x10291f0 .part/pv L_0x1028d40, 3, 1, 4; -L_0x1014a00 .part/pv L_0x1029090, 3, 1, 4; -L_0x10294f0 .part/pv L_0x1028a70, 3, 1, 4; -L_0x10295e0 .part v0xffc310_0, 3, 1; -L_0x1007fa0 .part v0xffc560_0, 3, 1; -L_0x10081b0 .part RS_0x7f9963cefc18, 2, 1; -L_0x102aaf0 .part/pv L_0x102a660, 0, 1, 4; -L_0x102abe0 .part/pv L_0x102a9b0, 0, 1, 4; -L_0x1008250 .part/pv L_0x102a390, 0, 1, 4; -L_0x102add0 .part v0xffc310_0, 0, 1; -L_0x102acd0 .part v0xffc560_0, 0, 1; -L_0x102afc0 .part RS_0x7f9963cefd68, 0, 1; -L_0x102b130 .part RS_0x7f9963cefc18, 3, 1; -L_0x102b3a0 .part RS_0x7f9963cefc18, 2, 1; -S_0xfdbbe0 .scope module, "attempt2" "MiddleAddSubSLT" 3 177, 3 88, S_0xfd84e0; - .timescale -9 -12; -L_0x101ee70/d .functor NOT 1, L_0x102acd0, C4<0>, C4<0>, C4<0>; -L_0x101ee70 .delay (10000,10000,10000) L_0x101ee70/d; -L_0x102a250/d .functor NOT 1, L_0x102a2f0, C4<0>, C4<0>, C4<0>; -L_0x102a250 .delay (10000,10000,10000) L_0x102a250/d; -L_0x102a390/d .functor AND 1, L_0x102a4d0, L_0x102a250, C4<1>, C4<1>; -L_0x102a390 .delay (20000,20000,20000) L_0x102a390/d; -L_0x102a570/d .functor XOR 1, L_0x102add0, L_0x102a020, C4<0>, C4<0>; -L_0x102a570 .delay (40000,40000,40000) L_0x102a570/d; -L_0x102a660/d .functor XOR 1, L_0x102a570, L_0x102afc0, C4<0>, C4<0>; -L_0x102a660 .delay (40000,40000,40000) L_0x102a660/d; -L_0x102a750/d .functor AND 1, L_0x102add0, L_0x102a020, C4<1>, C4<1>; -L_0x102a750 .delay (20000,20000,20000) L_0x102a750/d; -L_0x102a8c0/d .functor AND 1, L_0x102a570, L_0x102afc0, C4<1>, C4<1>; -L_0x102a8c0 .delay (20000,20000,20000) L_0x102a8c0/d; -L_0x102a9b0/d .functor OR 1, L_0x102a750, L_0x102a8c0, C4<0>, C4<0>; -L_0x102a9b0 .delay (20000,20000,20000) L_0x102a9b0/d; -v0xfdc250_0 .net "A", 0 0, L_0x102add0; 1 drivers -v0xfdc310_0 .net "AandB", 0 0, L_0x102a750; 1 drivers -v0xfdc3b0_0 .net "AddSubSLTSum", 0 0, L_0x102a660; 1 drivers -v0xfdc450_0 .net "AxorB", 0 0, L_0x102a570; 1 drivers -v0xfdc4d0_0 .net "B", 0 0, L_0x102acd0; 1 drivers -v0xfdc580_0 .net "BornB", 0 0, L_0x102a020; 1 drivers -v0xfdc640_0 .net "CINandAxorB", 0 0, L_0x102a8c0; 1 drivers -v0xfdc6c0_0 .alias "Command", 2 0, v0xffbc20_0; -v0xfdc740_0 .net *"_s3", 0 0, L_0x102a2f0; 1 drivers -v0xfdc7c0_0 .net *"_s5", 0 0, L_0x102a4d0; 1 drivers -v0xfdc860_0 .net "carryin", 0 0, L_0x102afc0; 1 drivers -v0xfdc900_0 .net "carryout", 0 0, L_0x102a9b0; 1 drivers -v0xfdc9a0_0 .net "nB", 0 0, L_0x101ee70; 1 drivers -v0xfdca50_0 .net "nCmd2", 0 0, L_0x102a250; 1 drivers -v0xfdcb50_0 .net "subtract", 0 0, L_0x102a390; 1 drivers -L_0x102a1b0 .part v0xffc5e0_0, 0, 1; -L_0x102a2f0 .part v0xffc5e0_0, 2, 1; -L_0x102a4d0 .part v0xffc5e0_0, 0, 1; -S_0xfdbcd0 .scope module, "mux0" "TwoInMux" 3 104, 3 8, S_0xfdbbe0; - .timescale -9 -12; -L_0x1007f10/d .functor NOT 1, L_0x102a1b0, C4<0>, C4<0>, C4<0>; -L_0x1007f10 .delay (10000,10000,10000) L_0x1007f10/d; -L_0x1008330/d .functor AND 1, L_0x102acd0, L_0x1007f10, C4<1>, C4<1>; -L_0x1008330 .delay (20000,20000,20000) L_0x1008330/d; -L_0x1029f30/d .functor AND 1, L_0x101ee70, L_0x102a1b0, C4<1>, C4<1>; -L_0x1029f30 .delay (20000,20000,20000) L_0x1029f30/d; -L_0x102a020/d .functor OR 1, L_0x1008330, L_0x1029f30, C4<0>, C4<0>; -L_0x102a020 .delay (20000,20000,20000) L_0x102a020/d; -v0xfdbdc0_0 .net "S", 0 0, L_0x102a1b0; 1 drivers -v0xfdbe80_0 .alias "in0", 0 0, v0xfdc4d0_0; -v0xfdbf20_0 .alias "in1", 0 0, v0xfdc9a0_0; -v0xfdbfc0_0 .net "nS", 0 0, L_0x1007f10; 1 drivers -v0xfdc070_0 .net "out0", 0 0, L_0x1008330; 1 drivers -v0xfdc110_0 .net "out1", 0 0, L_0x1029f30; 1 drivers -v0xfdc1b0_0 .alias "outfinal", 0 0, v0xfdc580_0; -S_0xfdaa40 .scope generate, "addbits[1]" "addbits[1]" 3 182, 3 182, S_0xfd84e0; - .timescale -9 -12; -P_0xfda458 .param/l "i" 3 182, +C4<01>; -S_0xfdabb0 .scope module, "attempt" "MiddleAddSubSLT" 3 184, 3 88, S_0xfdaa40; - .timescale -9 -12; -L_0x1024cd0/d .functor NOT 1, L_0x1026b70, C4<0>, C4<0>, C4<0>; -L_0x1024cd0 .delay (10000,10000,10000) L_0x1024cd0/d; -L_0x1025f00/d .functor NOT 1, L_0x1025fc0, C4<0>, C4<0>, C4<0>; -L_0x1025f00 .delay (10000,10000,10000) L_0x1025f00/d; -L_0x1026060/d .functor AND 1, L_0x10261a0, L_0x1025f00, C4<1>, C4<1>; -L_0x1026060 .delay (20000,20000,20000) L_0x1026060/d; -L_0x1026240/d .functor XOR 1, L_0x1026ad0, L_0x1025c90, C4<0>, C4<0>; -L_0x1026240 .delay (40000,40000,40000) L_0x1026240/d; -L_0x1026330/d .functor XOR 1, L_0x1026240, L_0x1026ca0, C4<0>, C4<0>; -L_0x1026330 .delay (40000,40000,40000) L_0x1026330/d; -L_0x1026420/d .functor AND 1, L_0x1026ad0, L_0x1025c90, C4<1>, C4<1>; -L_0x1026420 .delay (20000,20000,20000) L_0x1026420/d; -L_0x1026590/d .functor AND 1, L_0x1026240, L_0x1026ca0, C4<1>, C4<1>; -L_0x1026590 .delay (20000,20000,20000) L_0x1026590/d; -L_0x1026680/d .functor OR 1, L_0x1026420, L_0x1026590, C4<0>, C4<0>; -L_0x1026680 .delay (20000,20000,20000) L_0x1026680/d; -v0xfdb240_0 .net "A", 0 0, L_0x1026ad0; 1 drivers -v0xfdb300_0 .net "AandB", 0 0, L_0x1026420; 1 drivers -v0xfdb3a0_0 .net "AddSubSLTSum", 0 0, L_0x1026330; 1 drivers -v0xfdb440_0 .net "AxorB", 0 0, L_0x1026240; 1 drivers -v0xfdb4c0_0 .net "B", 0 0, L_0x1026b70; 1 drivers -v0xfdb570_0 .net "BornB", 0 0, L_0x1025c90; 1 drivers -v0xfdb630_0 .net "CINandAxorB", 0 0, L_0x1026590; 1 drivers -v0xfdb6b0_0 .alias "Command", 2 0, v0xffbc20_0; -v0xfdb730_0 .net *"_s3", 0 0, L_0x1025fc0; 1 drivers -v0xfdb7b0_0 .net *"_s5", 0 0, L_0x10261a0; 1 drivers -v0xfdb850_0 .net "carryin", 0 0, L_0x1026ca0; 1 drivers -v0xfdb8f0_0 .net "carryout", 0 0, L_0x1026680; 1 drivers -v0xfdb990_0 .net "nB", 0 0, L_0x1024cd0; 1 drivers -v0xfdba40_0 .net "nCmd2", 0 0, L_0x1025f00; 1 drivers -v0xfdbb40_0 .net "subtract", 0 0, L_0x1026060; 1 drivers -L_0x1025e60 .part v0xffc5e0_0, 0, 1; -L_0x1025fc0 .part v0xffc5e0_0, 2, 1; -L_0x10261a0 .part v0xffc5e0_0, 0, 1; -S_0xfdaca0 .scope module, "mux0" "TwoInMux" 3 104, 3 8, S_0xfdabb0; - .timescale -9 -12; -L_0x10259b0/d .functor NOT 1, L_0x1025e60, C4<0>, C4<0>, C4<0>; -L_0x10259b0 .delay (10000,10000,10000) L_0x10259b0/d; -L_0x1025a70/d .functor AND 1, L_0x1026b70, L_0x10259b0, C4<1>, C4<1>; -L_0x1025a70 .delay (20000,20000,20000) L_0x1025a70/d; -L_0x1025b80/d .functor AND 1, L_0x1024cd0, L_0x1025e60, C4<1>, C4<1>; -L_0x1025b80 .delay (20000,20000,20000) L_0x1025b80/d; -L_0x1025c90/d .functor OR 1, L_0x1025a70, L_0x1025b80, C4<0>, C4<0>; -L_0x1025c90 .delay (20000,20000,20000) L_0x1025c90/d; -v0xfdad90_0 .net "S", 0 0, L_0x1025e60; 1 drivers -v0xfdae30_0 .alias "in0", 0 0, v0xfdb4c0_0; -v0xfdaed0_0 .alias "in1", 0 0, v0xfdb990_0; -v0xfdaf70_0 .net "nS", 0 0, L_0x10259b0; 1 drivers -v0xfdb020_0 .net "out0", 0 0, L_0x1025a70; 1 drivers -v0xfdb0c0_0 .net "out1", 0 0, L_0x1025b80; 1 drivers -v0xfdb1a0_0 .alias "outfinal", 0 0, v0xfdb570_0; -S_0xfd98a0 .scope generate, "addbits[2]" "addbits[2]" 3 182, 3 182, S_0xfd84e0; - .timescale -9 -12; -P_0xfd91e8 .param/l "i" 3 182, +C4<010>; -S_0xfd9a10 .scope module, "attempt" "MiddleAddSubSLT" 3 184, 3 88, S_0xfd98a0; - .timescale -9 -12; -L_0x1026d40/d .functor NOT 1, L_0x1028140, C4<0>, C4<0>, C4<0>; -L_0x1026d40 .delay (10000,10000,10000) L_0x1026d40/d; -L_0x1027440/d .functor NOT 1, L_0x1027500, C4<0>, C4<0>, C4<0>; -L_0x1027440 .delay (10000,10000,10000) L_0x1027440/d; -L_0x10275a0/d .functor AND 1, L_0x10276e0, L_0x1027440, C4<1>, C4<1>; -L_0x10275a0 .delay (20000,20000,20000) L_0x10275a0/d; -L_0x1027780/d .functor XOR 1, L_0x1028040, L_0x10271d0, C4<0>, C4<0>; -L_0x1027780 .delay (40000,40000,40000) L_0x1027780/d; -L_0x1027870/d .functor XOR 1, L_0x1027780, L_0x1028270, C4<0>, C4<0>; -L_0x1027870 .delay (40000,40000,40000) L_0x1027870/d; -L_0x1027960/d .functor AND 1, L_0x1028040, L_0x10271d0, C4<1>, C4<1>; -L_0x1027960 .delay (20000,20000,20000) L_0x1027960/d; -L_0x1027ad0/d .functor AND 1, L_0x1027780, L_0x1028270, C4<1>, C4<1>; -L_0x1027ad0 .delay (20000,20000,20000) L_0x1027ad0/d; -L_0x1027bc0/d .functor OR 1, L_0x1027960, L_0x1027ad0, C4<0>, C4<0>; -L_0x1027bc0 .delay (20000,20000,20000) L_0x1027bc0/d; -v0xfda0a0_0 .net "A", 0 0, L_0x1028040; 1 drivers -v0xfda160_0 .net "AandB", 0 0, L_0x1027960; 1 drivers -v0xfda200_0 .net "AddSubSLTSum", 0 0, L_0x1027870; 1 drivers -v0xfda2a0_0 .net "AxorB", 0 0, L_0x1027780; 1 drivers -v0xfda320_0 .net "B", 0 0, L_0x1028140; 1 drivers -v0xfda3d0_0 .net "BornB", 0 0, L_0x10271d0; 1 drivers -v0xfda490_0 .net "CINandAxorB", 0 0, L_0x1027ad0; 1 drivers -v0xfda510_0 .alias "Command", 2 0, v0xffbc20_0; -v0xfda590_0 .net *"_s3", 0 0, L_0x1027500; 1 drivers -v0xfda610_0 .net *"_s5", 0 0, L_0x10276e0; 1 drivers -v0xfda6b0_0 .net "carryin", 0 0, L_0x1028270; 1 drivers -v0xfda750_0 .net "carryout", 0 0, L_0x1027bc0; 1 drivers -v0xfda7f0_0 .net "nB", 0 0, L_0x1026d40; 1 drivers -v0xfda8a0_0 .net "nCmd2", 0 0, L_0x1027440; 1 drivers -v0xfda9a0_0 .net "subtract", 0 0, L_0x10275a0; 1 drivers -L_0x10273a0 .part v0xffc5e0_0, 0, 1; -L_0x1027500 .part v0xffc5e0_0, 2, 1; -L_0x10276e0 .part v0xffc5e0_0, 0, 1; -S_0xfd9b00 .scope module, "mux0" "TwoInMux" 3 104, 3 8, S_0xfd9a10; - .timescale -9 -12; -L_0x1026ef0/d .functor NOT 1, L_0x10273a0, C4<0>, C4<0>, C4<0>; -L_0x1026ef0 .delay (10000,10000,10000) L_0x1026ef0/d; -L_0x1026fb0/d .functor AND 1, L_0x1028140, L_0x1026ef0, C4<1>, C4<1>; -L_0x1026fb0 .delay (20000,20000,20000) L_0x1026fb0/d; -L_0x10270c0/d .functor AND 1, L_0x1026d40, L_0x10273a0, C4<1>, C4<1>; -L_0x10270c0 .delay (20000,20000,20000) L_0x10270c0/d; -L_0x10271d0/d .functor OR 1, L_0x1026fb0, L_0x10270c0, C4<0>, C4<0>; -L_0x10271d0 .delay (20000,20000,20000) L_0x10271d0/d; -v0xfd9bf0_0 .net "S", 0 0, L_0x10273a0; 1 drivers -v0xfd9c90_0 .alias "in0", 0 0, v0xfda320_0; -v0xfd9d30_0 .alias "in1", 0 0, v0xfda7f0_0; -v0xfd9dd0_0 .net "nS", 0 0, L_0x1026ef0; 1 drivers -v0xfd9e80_0 .net "out0", 0 0, L_0x1026fb0; 1 drivers -v0xfd9f20_0 .net "out1", 0 0, L_0x10270c0; 1 drivers -v0xfda000_0 .alias "outfinal", 0 0, v0xfda3d0_0; -S_0xfd8650 .scope generate, "addbits[3]" "addbits[3]" 3 182, 3 182, S_0xfd84e0; - .timescale -9 -12; -P_0xfd8748 .param/l "i" 3 182, +C4<011>; -S_0xfd87c0 .scope module, "attempt" "MiddleAddSubSLT" 3 184, 3 88, S_0xfd8650; - .timescale -9 -12; -L_0x10280e0/d .functor NOT 1, L_0x1007fa0, C4<0>, C4<0>, C4<0>; -L_0x10280e0 .delay (10000,10000,10000) L_0x10280e0/d; -L_0x1028910/d .functor NOT 1, L_0x10289d0, C4<0>, C4<0>, C4<0>; -L_0x1028910 .delay (10000,10000,10000) L_0x1028910/d; -L_0x1028a70/d .functor AND 1, L_0x1028bb0, L_0x1028910, C4<1>, C4<1>; -L_0x1028a70 .delay (20000,20000,20000) L_0x1028a70/d; -L_0x1028c50/d .functor XOR 1, L_0x10295e0, L_0x10286a0, C4<0>, C4<0>; -L_0x1028c50 .delay (40000,40000,40000) L_0x1028c50/d; -L_0x1028d40/d .functor XOR 1, L_0x1028c50, L_0x10081b0, C4<0>, C4<0>; -L_0x1028d40 .delay (40000,40000,40000) L_0x1028d40/d; -L_0x1028e30/d .functor AND 1, L_0x10295e0, L_0x10286a0, C4<1>, C4<1>; -L_0x1028e30 .delay (20000,20000,20000) L_0x1028e30/d; -L_0x1028fa0/d .functor AND 1, L_0x1028c50, L_0x10081b0, C4<1>, C4<1>; -L_0x1028fa0 .delay (20000,20000,20000) L_0x1028fa0/d; -L_0x1029090/d .functor OR 1, L_0x1028e30, L_0x1028fa0, C4<0>, C4<0>; -L_0x1029090 .delay (20000,20000,20000) L_0x1029090/d; -v0xfd8e30_0 .net "A", 0 0, L_0x10295e0; 1 drivers -v0xfd8ef0_0 .net "AandB", 0 0, L_0x1028e30; 1 drivers -v0xfd8f90_0 .net "AddSubSLTSum", 0 0, L_0x1028d40; 1 drivers -v0xfd9030_0 .net "AxorB", 0 0, L_0x1028c50; 1 drivers -v0xfd90b0_0 .net "B", 0 0, L_0x1007fa0; 1 drivers -v0xfd9160_0 .net "BornB", 0 0, L_0x10286a0; 1 drivers -v0xfd9220_0 .net "CINandAxorB", 0 0, L_0x1028fa0; 1 drivers -v0xfd92a0_0 .alias "Command", 2 0, v0xffbc20_0; -v0xfd9320_0 .net *"_s3", 0 0, L_0x10289d0; 1 drivers -v0xfd93a0_0 .net *"_s5", 0 0, L_0x1028bb0; 1 drivers -v0xfd94a0_0 .net "carryin", 0 0, L_0x10081b0; 1 drivers -v0xfd9540_0 .net "carryout", 0 0, L_0x1029090; 1 drivers -v0xfd9650_0 .net "nB", 0 0, L_0x10280e0; 1 drivers -v0xfd9700_0 .net "nCmd2", 0 0, L_0x1028910; 1 drivers -v0xfd9800_0 .net "subtract", 0 0, L_0x1028a70; 1 drivers -L_0x1028870 .part v0xffc5e0_0, 0, 1; -L_0x10289d0 .part v0xffc5e0_0, 2, 1; -L_0x1028bb0 .part v0xffc5e0_0, 0, 1; -S_0xfd88b0 .scope module, "mux0" "TwoInMux" 3 104, 3 8, S_0xfd87c0; - .timescale -9 -12; -L_0x1028400/d .functor NOT 1, L_0x1028870, C4<0>, C4<0>, C4<0>; -L_0x1028400 .delay (10000,10000,10000) L_0x1028400/d; -L_0x1028480/d .functor AND 1, L_0x1007fa0, L_0x1028400, C4<1>, C4<1>; -L_0x1028480 .delay (20000,20000,20000) L_0x1028480/d; -L_0x1028590/d .functor AND 1, L_0x10280e0, L_0x1028870, C4<1>, C4<1>; -L_0x1028590 .delay (20000,20000,20000) L_0x1028590/d; -L_0x10286a0/d .functor OR 1, L_0x1028480, L_0x1028590, C4<0>, C4<0>; -L_0x10286a0 .delay (20000,20000,20000) L_0x10286a0/d; -v0xfd89a0_0 .net "S", 0 0, L_0x1028870; 1 drivers -v0xfd8a20_0 .alias "in0", 0 0, v0xfd90b0_0; -v0xfd8ac0_0 .alias "in1", 0 0, v0xfd9650_0; -v0xfd8b60_0 .net "nS", 0 0, L_0x1028400; 1 drivers -v0xfd8c10_0 .net "out0", 0 0, L_0x1028480; 1 drivers -v0xfd8cb0_0 .net "out1", 0 0, L_0x1028590; 1 drivers -v0xfd8d90_0 .alias "outfinal", 0 0, v0xfd9160_0; -S_0xfd52a0 .scope module, "trial1" "AndNand32" 3 329, 3 115, S_0xf6f800; - .timescale -9 -12; -P_0xfd4d28 .param/l "size" 3 122, +C4<0100>; -v0xfd5190_0 .alias "A", 3 0, v0xffb8e0_0; -v0xfd8300_0 .alias "AndNandOut", 3 0, v0xffc4b0_0; -v0xfd8380_0 .alias "B", 3 0, v0xffba90_0; -v0xfd8430_0 .alias "Command", 2 0, v0xffbc20_0; -L_0x102bbf0 .part/pv L_0x102b980, 1, 1, 4; -L_0x102bcb0 .part v0xffc310_0, 1, 1; -L_0x102bd50 .part v0xffc560_0, 1, 1; -L_0x102c660 .part/pv L_0x102c3f0, 2, 1, 4; -L_0x102c700 .part v0xffc310_0, 2, 1; -L_0x102c7a0 .part v0xffc560_0, 2, 1; -L_0x102d0d0 .part/pv L_0x102ce60, 3, 1, 4; -L_0x1015a10 .part v0xffc310_0, 3, 1; -L_0x102d380 .part v0xffc560_0, 3, 1; -L_0x102dc30 .part/pv L_0x102d9c0, 0, 1, 4; -L_0x102dd30 .part v0xffc310_0, 0, 1; -L_0x102ddd0 .part v0xffc560_0, 0, 1; -S_0xfd77c0 .scope module, "attempt2" "AndNand" 3 126, 3 48, S_0xfd52a0; - .timescale -9 -12; -L_0x102d470/d .functor NAND 1, L_0x102dd30, L_0x102ddd0, C4<1>, C4<1>; -L_0x102d470 .delay (10000,10000,10000) L_0x102d470/d; -L_0x102d570/d .functor NOT 1, L_0x102d470, C4<0>, C4<0>, C4<0>; -L_0x102d570 .delay (10000,10000,10000) L_0x102d570/d; -v0xfd7de0_0 .net "A", 0 0, L_0x102dd30; 1 drivers -v0xfd7ea0_0 .net "AandB", 0 0, L_0x102d570; 1 drivers -v0xfd7f20_0 .net "AnandB", 0 0, L_0x102d470; 1 drivers -v0xfd7fd0_0 .net "AndNandOut", 0 0, L_0x102d9c0; 1 drivers -v0xfd80b0_0 .net "B", 0 0, L_0x102ddd0; 1 drivers -v0xfd8130_0 .alias "Command", 2 0, v0xffbc20_0; -L_0x102db90 .part v0xffc5e0_0, 0, 1; -S_0xfd78b0 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0xfd77c0; - .timescale -9 -12; -L_0x102d6a0/d .functor NOT 1, L_0x102db90, C4<0>, C4<0>, C4<0>; -L_0x102d6a0 .delay (10000,10000,10000) L_0x102d6a0/d; -L_0x102d760/d .functor AND 1, L_0x102d570, L_0x102d6a0, C4<1>, C4<1>; -L_0x102d760 .delay (20000,20000,20000) L_0x102d760/d; -L_0x102d870/d .functor AND 1, L_0x102d470, L_0x102db90, C4<1>, C4<1>; -L_0x102d870 .delay (20000,20000,20000) L_0x102d870/d; -L_0x102d9c0/d .functor OR 1, L_0x102d760, L_0x102d870, C4<0>, C4<0>; -L_0x102d9c0 .delay (20000,20000,20000) L_0x102d9c0/d; -v0xfd79a0_0 .net "S", 0 0, L_0x102db90; 1 drivers -v0xfd7a20_0 .alias "in0", 0 0, v0xfd7ea0_0; -v0xfd7aa0_0 .alias "in1", 0 0, v0xfd7f20_0; -v0xfd7b40_0 .net "nS", 0 0, L_0x102d6a0; 1 drivers -v0xfd7bc0_0 .net "out0", 0 0, L_0x102d760; 1 drivers -v0xfd7c60_0 .net "out1", 0 0, L_0x102d870; 1 drivers -v0xfd7d40_0 .alias "outfinal", 0 0, v0xfd7fd0_0; -S_0xfd6c00 .scope generate, "andbits[1]" "andbits[1]" 3 130, 3 130, S_0xfd52a0; - .timescale -9 -12; -P_0xfd6cf8 .param/l "i" 3 130, +C4<01>; -S_0xfd6d70 .scope module, "attempt" "AndNand" 3 132, 3 48, S_0xfd6c00; - .timescale -9 -12; -L_0x102b060/d .functor NAND 1, L_0x102bcb0, L_0x102bd50, C4<1>, C4<1>; -L_0x102b060 .delay (10000,10000,10000) L_0x102b060/d; -L_0x102b5b0/d .functor NOT 1, L_0x102b060, C4<0>, C4<0>, C4<0>; -L_0x102b5b0 .delay (10000,10000,10000) L_0x102b5b0/d; -v0xfd73b0_0 .net "A", 0 0, L_0x102bcb0; 1 drivers -v0xfd7470_0 .net "AandB", 0 0, L_0x102b5b0; 1 drivers -v0xfd74f0_0 .net "AnandB", 0 0, L_0x102b060; 1 drivers -v0xfd75a0_0 .net "AndNandOut", 0 0, L_0x102b980; 1 drivers -v0xfd7680_0 .net "B", 0 0, L_0x102bd50; 1 drivers -v0xfd7700_0 .alias "Command", 2 0, v0xffbc20_0; -L_0x102bb50 .part v0xffc5e0_0, 0, 1; -S_0xfd6e60 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0xfd6d70; - .timescale -9 -12; -L_0x102b6a0/d .functor NOT 1, L_0x102bb50, C4<0>, C4<0>, C4<0>; -L_0x102b6a0 .delay (10000,10000,10000) L_0x102b6a0/d; -L_0x102b740/d .functor AND 1, L_0x102b5b0, L_0x102b6a0, C4<1>, C4<1>; -L_0x102b740 .delay (20000,20000,20000) L_0x102b740/d; -L_0x102b830/d .functor AND 1, L_0x102b060, L_0x102bb50, C4<1>, C4<1>; -L_0x102b830 .delay (20000,20000,20000) L_0x102b830/d; -L_0x102b980/d .functor OR 1, L_0x102b740, L_0x102b830, C4<0>, C4<0>; -L_0x102b980 .delay (20000,20000,20000) L_0x102b980/d; -v0xfd6f50_0 .net "S", 0 0, L_0x102bb50; 1 drivers -v0xfd6fd0_0 .alias "in0", 0 0, v0xfd7470_0; -v0xfd7070_0 .alias "in1", 0 0, v0xfd74f0_0; -v0xfd7110_0 .net "nS", 0 0, L_0x102b6a0; 1 drivers -v0xfd7190_0 .net "out0", 0 0, L_0x102b740; 1 drivers -v0xfd7230_0 .net "out1", 0 0, L_0x102b830; 1 drivers -v0xfd7310_0 .alias "outfinal", 0 0, v0xfd75a0_0; -S_0xfd6040 .scope generate, "andbits[2]" "andbits[2]" 3 130, 3 130, S_0xfd52a0; - .timescale -9 -12; -P_0xfd6138 .param/l "i" 3 130, +C4<010>; -S_0xfd61b0 .scope module, "attempt" "AndNand" 3 132, 3 48, S_0xfd6040; - .timescale -9 -12; -L_0x102be40/d .functor NAND 1, L_0x102c700, L_0x102c7a0, C4<1>, C4<1>; -L_0x102be40 .delay (10000,10000,10000) L_0x102be40/d; -L_0x102bfa0/d .functor NOT 1, L_0x102be40, C4<0>, C4<0>, C4<0>; -L_0x102bfa0 .delay (10000,10000,10000) L_0x102bfa0/d; -v0xfd67f0_0 .net "A", 0 0, L_0x102c700; 1 drivers -v0xfd68b0_0 .net "AandB", 0 0, L_0x102bfa0; 1 drivers -v0xfd6930_0 .net "AnandB", 0 0, L_0x102be40; 1 drivers -v0xfd69e0_0 .net "AndNandOut", 0 0, L_0x102c3f0; 1 drivers -v0xfd6ac0_0 .net "B", 0 0, L_0x102c7a0; 1 drivers -v0xfd6b40_0 .alias "Command", 2 0, v0xffbc20_0; -L_0x102c5c0 .part v0xffc5e0_0, 0, 1; -S_0xfd62a0 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0xfd61b0; - .timescale -9 -12; -L_0x102c0d0/d .functor NOT 1, L_0x102c5c0, C4<0>, C4<0>, C4<0>; -L_0x102c0d0 .delay (10000,10000,10000) L_0x102c0d0/d; -L_0x102c190/d .functor AND 1, L_0x102bfa0, L_0x102c0d0, C4<1>, C4<1>; -L_0x102c190 .delay (20000,20000,20000) L_0x102c190/d; -L_0x102c2a0/d .functor AND 1, L_0x102be40, L_0x102c5c0, C4<1>, C4<1>; -L_0x102c2a0 .delay (20000,20000,20000) L_0x102c2a0/d; -L_0x102c3f0/d .functor OR 1, L_0x102c190, L_0x102c2a0, C4<0>, C4<0>; -L_0x102c3f0 .delay (20000,20000,20000) L_0x102c3f0/d; -v0xfd6390_0 .net "S", 0 0, L_0x102c5c0; 1 drivers -v0xfd6410_0 .alias "in0", 0 0, v0xfd68b0_0; -v0xfd64b0_0 .alias "in1", 0 0, v0xfd6930_0; -v0xfd6550_0 .net "nS", 0 0, L_0x102c0d0; 1 drivers -v0xfd65d0_0 .net "out0", 0 0, L_0x102c190; 1 drivers -v0xfd6670_0 .net "out1", 0 0, L_0x102c2a0; 1 drivers -v0xfd6750_0 .alias "outfinal", 0 0, v0xfd69e0_0; -S_0xfd5410 .scope generate, "andbits[3]" "andbits[3]" 3 130, 3 130, S_0xfd52a0; - .timescale -9 -12; -P_0xfd5508 .param/l "i" 3 130, +C4<011>; -S_0xfd55a0 .scope module, "attempt" "AndNand" 3 132, 3 48, S_0xfd5410; - .timescale -9 -12; -L_0x102c8d0/d .functor NAND 1, L_0x1015a10, L_0x102d380, C4<1>, C4<1>; -L_0x102c8d0 .delay (10000,10000,10000) L_0x102c8d0/d; -L_0x102ca10/d .functor NOT 1, L_0x102c8d0, C4<0>, C4<0>, C4<0>; -L_0x102ca10 .delay (10000,10000,10000) L_0x102ca10/d; -v0xfd5c30_0 .net "A", 0 0, L_0x1015a10; 1 drivers -v0xfd5cf0_0 .net "AandB", 0 0, L_0x102ca10; 1 drivers -v0xfd5d70_0 .net "AnandB", 0 0, L_0x102c8d0; 1 drivers -v0xfd5e20_0 .net "AndNandOut", 0 0, L_0x102ce60; 1 drivers -v0xfd5f00_0 .net "B", 0 0, L_0x102d380; 1 drivers -v0xfd5f80_0 .alias "Command", 2 0, v0xffbc20_0; -L_0x102d030 .part v0xffc5e0_0, 0, 1; -S_0xfd5690 .scope module, "potato" "TwoInMux" 3 60, 3 8, S_0xfd55a0; - .timescale -9 -12; -L_0x102cb40/d .functor NOT 1, L_0x102d030, C4<0>, C4<0>, C4<0>; -L_0x102cb40 .delay (10000,10000,10000) L_0x102cb40/d; -L_0x102cc00/d .functor AND 1, L_0x102ca10, L_0x102cb40, C4<1>, C4<1>; -L_0x102cc00 .delay (20000,20000,20000) L_0x102cc00/d; -L_0x102cd10/d .functor AND 1, L_0x102c8d0, L_0x102d030, C4<1>, C4<1>; -L_0x102cd10 .delay (20000,20000,20000) L_0x102cd10/d; -L_0x102ce60/d .functor OR 1, L_0x102cc00, L_0x102cd10, C4<0>, C4<0>; -L_0x102ce60 .delay (20000,20000,20000) L_0x102ce60/d; -v0xfd5780_0 .net "S", 0 0, L_0x102d030; 1 drivers -v0xfd5820_0 .alias "in0", 0 0, v0xfd5cf0_0; -v0xfd58c0_0 .alias "in1", 0 0, v0xfd5d70_0; -v0xfd5960_0 .net "nS", 0 0, L_0x102cb40; 1 drivers -v0xfd5a10_0 .net "out0", 0 0, L_0x102cc00; 1 drivers -v0xfd5ab0_0 .net "out1", 0 0, L_0x102cd10; 1 drivers -v0xfd5b90_0 .alias "outfinal", 0 0, v0xfd5e20_0; -S_0xfd0080 .scope module, "trial2" "OrNorXor32" 3 330, 3 138, S_0xf6f800; - .timescale -9 -12; -P_0xfcf1d8 .param/l "size" 3 145, +C4<0100>; -v0xfd5010_0 .alias "A", 3 0, v0xffb8e0_0; -v0xfd5090_0 .alias "B", 3 0, v0xffba90_0; -v0xfd5110_0 .alias "Command", 2 0, v0xffbc20_0; -v0xfd5220_0 .alias "OrNorXorOut", 3 0, v0xffc6e0_0; -L_0x1009490 .part/pv L_0x102ed80, 1, 1, 4; -L_0x1009530 .part v0xffc310_0, 1, 1; -L_0x10095d0 .part v0xffc560_0, 1, 1; -L_0x1030990 .part/pv L_0x1030760, 2, 1, 4; -L_0x1030a30 .part v0xffc310_0, 2, 1; -L_0x1030ad0 .part v0xffc560_0, 2, 1; -L_0x1031c50 .part/pv L_0x10319e0, 3, 1, 4; -L_0x1031cf0 .part v0xffc310_0, 3, 1; -L_0x1031d90 .part v0xffc560_0, 3, 1; -L_0x1032f40 .part/pv L_0x1032cd0, 0, 1, 4; -L_0x1033040 .part v0xffc310_0, 0, 1; -L_0x10330e0 .part v0xffc560_0, 0, 1; -S_0xfd3e00 .scope module, "attempt2" "OrNorXor" 3 153, 3 64, S_0xfd0080; - .timescale -9 -12; -L_0x1031e30/d .functor NOR 1, L_0x1033040, L_0x10330e0, C4<0>, C4<0>; -L_0x1031e30 .delay (10000,10000,10000) L_0x1031e30/d; -L_0x1031f30/d .functor NOT 1, L_0x1031e30, C4<0>, C4<0>, C4<0>; -L_0x1031f30 .delay (10000,10000,10000) L_0x1031f30/d; -L_0x1032060/d .functor NAND 1, L_0x1033040, L_0x10330e0, C4<1>, C4<1>; -L_0x1032060 .delay (10000,10000,10000) L_0x1032060/d; -L_0x10321c0/d .functor NAND 1, L_0x1032060, L_0x1031f30, C4<1>, C4<1>; -L_0x10321c0 .delay (10000,10000,10000) L_0x10321c0/d; -L_0x10322d0/d .functor NOT 1, L_0x10321c0, C4<0>, C4<0>, C4<0>; -L_0x10322d0 .delay (10000,10000,10000) L_0x10322d0/d; -v0xfd4950_0 .net "A", 0 0, L_0x1033040; 1 drivers -v0xfd49f0_0 .net "AnandB", 0 0, L_0x1032060; 1 drivers -v0xfd4a90_0 .net "AnorB", 0 0, L_0x1031e30; 1 drivers -v0xfd4b10_0 .net "AorB", 0 0, L_0x1031f30; 1 drivers -v0xfd4bf0_0 .net "AxorB", 0 0, L_0x10322d0; 1 drivers -v0xfd4ca0_0 .net "B", 0 0, L_0x10330e0; 1 drivers -v0xfd4d60_0 .alias "Command", 2 0, v0xffbc20_0; -v0xfd4de0_0 .net "OrNorXorOut", 0 0, L_0x1032cd0; 1 drivers -v0xfd4e60_0 .net "XorNor", 0 0, L_0x1032750; 1 drivers -v0xfd4f30_0 .net "nXor", 0 0, L_0x10321c0; 1 drivers -L_0x10328d0 .part v0xffc5e0_0, 2, 1; -L_0x1032ea0 .part v0xffc5e0_0, 0, 1; -S_0xfd43e0 .scope module, "mux0" "TwoInMux" 3 83, 3 8, S_0xfd3e00; - .timescale -9 -12; -L_0x1032430/d .functor NOT 1, L_0x10328d0, C4<0>, C4<0>, C4<0>; -L_0x1032430 .delay (10000,10000,10000) L_0x1032430/d; -L_0x10324f0/d .functor AND 1, L_0x10322d0, L_0x1032430, C4<1>, C4<1>; -L_0x10324f0 .delay (20000,20000,20000) L_0x10324f0/d; -L_0x1032600/d .functor AND 1, L_0x1031e30, L_0x10328d0, C4<1>, C4<1>; -L_0x1032600 .delay (20000,20000,20000) L_0x1032600/d; -L_0x1032750/d .functor OR 1, L_0x10324f0, L_0x1032600, C4<0>, C4<0>; -L_0x1032750 .delay (20000,20000,20000) L_0x1032750/d; -v0xfd44d0_0 .net "S", 0 0, L_0x10328d0; 1 drivers -v0xfd4590_0 .alias "in0", 0 0, v0xfd4bf0_0; -v0xfd4630_0 .alias "in1", 0 0, v0xfd4a90_0; -v0xfd46d0_0 .net "nS", 0 0, L_0x1032430; 1 drivers -v0xfd4750_0 .net "out0", 0 0, L_0x10324f0; 1 drivers -v0xfd47f0_0 .net "out1", 0 0, L_0x1032600; 1 drivers -v0xfd48d0_0 .alias "outfinal", 0 0, v0xfd4e60_0; -S_0xfd3ef0 .scope module, "mux1" "TwoInMux" 3 84, 3 8, S_0xfd3e00; - .timescale -9 -12; -L_0x1032970/d .functor NOT 1, L_0x1032ea0, C4<0>, C4<0>, C4<0>; -L_0x1032970 .delay (10000,10000,10000) L_0x1032970/d; -L_0x1032a30/d .functor AND 1, L_0x1032750, L_0x1032970, C4<1>, C4<1>; -L_0x1032a30 .delay (20000,20000,20000) L_0x1032a30/d; -L_0x1032b80/d .functor AND 1, L_0x1031f30, L_0x1032ea0, C4<1>, C4<1>; -L_0x1032b80 .delay (20000,20000,20000) L_0x1032b80/d; -L_0x1032cd0/d .functor OR 1, L_0x1032a30, L_0x1032b80, C4<0>, C4<0>; -L_0x1032cd0 .delay (20000,20000,20000) L_0x1032cd0/d; -v0xfd3fe0_0 .net "S", 0 0, L_0x1032ea0; 1 drivers -v0xfd4060_0 .alias "in0", 0 0, v0xfd4e60_0; -v0xfd40e0_0 .alias "in1", 0 0, v0xfd4b10_0; -v0xfd4180_0 .net "nS", 0 0, L_0x1032970; 1 drivers -v0xfd4200_0 .net "out0", 0 0, L_0x1032a30; 1 drivers -v0xfd42a0_0 .net "out1", 0 0, L_0x1032b80; 1 drivers -v0xfd4340_0 .alias "outfinal", 0 0, v0xfd4de0_0; -S_0xfd29e0 .scope generate, "orbits[1]" "orbits[1]" 3 157, 3 157, S_0xfd0080; - .timescale -9 -12; -P_0xfd2678 .param/l "i" 3 157, +C4<01>; -S_0xfd2b10 .scope module, "attempt" "OrNorXor" 3 159, 3 64, S_0xfd29e0; - .timescale -9 -12; -L_0x102dcd0/d .functor NOR 1, L_0x1009530, L_0x10095d0, C4<0>, C4<0>; -L_0x102dcd0 .delay (10000,10000,10000) L_0x102dcd0/d; -L_0x102dfe0/d .functor NOT 1, L_0x102dcd0, C4<0>, C4<0>, C4<0>; -L_0x102dfe0 .delay (10000,10000,10000) L_0x102dfe0/d; -L_0x102e110/d .functor NAND 1, L_0x1009530, L_0x10095d0, C4<1>, C4<1>; -L_0x102e110 .delay (10000,10000,10000) L_0x102e110/d; -L_0x102e270/d .functor NAND 1, L_0x102e110, L_0x102dfe0, C4<1>, C4<1>; -L_0x102e270 .delay (10000,10000,10000) L_0x102e270/d; -L_0x102e380/d .functor NOT 1, L_0x102e270, C4<0>, C4<0>, C4<0>; -L_0x102e380 .delay (10000,10000,10000) L_0x102e380/d; -v0xfd36c0_0 .net "A", 0 0, L_0x1009530; 1 drivers -v0xfd3760_0 .net "AnandB", 0 0, L_0x102e110; 1 drivers -v0xfd3800_0 .net "AnorB", 0 0, L_0x102dcd0; 1 drivers -v0xfd38b0_0 .net "AorB", 0 0, L_0x102dfe0; 1 drivers -v0xfd3990_0 .net "AxorB", 0 0, L_0x102e380; 1 drivers -v0xfd3a40_0 .net "B", 0 0, L_0x10095d0; 1 drivers -v0xfd3b00_0 .alias "Command", 2 0, v0xffbc20_0; -v0xfd3b80_0 .net "OrNorXorOut", 0 0, L_0x102ed80; 1 drivers -v0xfd3c50_0 .net "XorNor", 0 0, L_0x102e800; 1 drivers -v0xfd3d20_0 .net "nXor", 0 0, L_0x102e270; 1 drivers -L_0x102e980 .part v0xffc5e0_0, 2, 1; -L_0x102ef50 .part v0xffc5e0_0, 0, 1; -S_0xfd3150 .scope module, "mux0" "TwoInMux" 3 83, 3 8, S_0xfd2b10; - .timescale -9 -12; -L_0x102e4e0/d .functor NOT 1, L_0x102e980, C4<0>, C4<0>, C4<0>; -L_0x102e4e0 .delay (10000,10000,10000) L_0x102e4e0/d; -L_0x102e5a0/d .functor AND 1, L_0x102e380, L_0x102e4e0, C4<1>, C4<1>; -L_0x102e5a0 .delay (20000,20000,20000) L_0x102e5a0/d; -L_0x102e6b0/d .functor AND 1, L_0x102dcd0, L_0x102e980, C4<1>, C4<1>; -L_0x102e6b0 .delay (20000,20000,20000) L_0x102e6b0/d; -L_0x102e800/d .functor OR 1, L_0x102e5a0, L_0x102e6b0, C4<0>, C4<0>; -L_0x102e800 .delay (20000,20000,20000) L_0x102e800/d; -v0xfd3240_0 .net "S", 0 0, L_0x102e980; 1 drivers -v0xfd3300_0 .alias "in0", 0 0, v0xfd3990_0; -v0xfd33a0_0 .alias "in1", 0 0, v0xfd3800_0; -v0xfd3440_0 .net "nS", 0 0, L_0x102e4e0; 1 drivers -v0xfd34c0_0 .net "out0", 0 0, L_0x102e5a0; 1 drivers -v0xfd3560_0 .net "out1", 0 0, L_0x102e6b0; 1 drivers -v0xfd3640_0 .alias "outfinal", 0 0, v0xfd3c50_0; -S_0xfd2c00 .scope module, "mux1" "TwoInMux" 3 84, 3 8, S_0xfd2b10; - .timescale -9 -12; -L_0x102ea20/d .functor NOT 1, L_0x102ef50, C4<0>, C4<0>, C4<0>; -L_0x102ea20 .delay (10000,10000,10000) L_0x102ea20/d; -L_0x102eae0/d .functor AND 1, L_0x102e800, L_0x102ea20, C4<1>, C4<1>; -L_0x102eae0 .delay (20000,20000,20000) L_0x102eae0/d; -L_0x102ec30/d .functor AND 1, L_0x102dfe0, L_0x102ef50, C4<1>, C4<1>; -L_0x102ec30 .delay (20000,20000,20000) L_0x102ec30/d; -L_0x102ed80/d .functor OR 1, L_0x102eae0, L_0x102ec30, C4<0>, C4<0>; -L_0x102ed80 .delay (20000,20000,20000) L_0x102ed80/d; -v0xfd2cf0_0 .net "S", 0 0, L_0x102ef50; 1 drivers -v0xfd2d70_0 .alias "in0", 0 0, v0xfd3c50_0; -v0xfd2e10_0 .alias "in1", 0 0, v0xfd38b0_0; -v0xfd2eb0_0 .net "nS", 0 0, L_0x102ea20; 1 drivers -v0xfd2f30_0 .net "out0", 0 0, L_0x102eae0; 1 drivers -v0xfd2fd0_0 .net "out1", 0 0, L_0x102ec30; 1 drivers -v0xfd30b0_0 .alias "outfinal", 0 0, v0xfd3b80_0; -S_0xfd15e0 .scope generate, "orbits[2]" "orbits[2]" 3 157, 3 157, S_0xfd0080; - .timescale -9 -12; -P_0xfd1358 .param/l "i" 3 157, +C4<010>; -S_0xfd1710 .scope module, "attempt" "OrNorXor" 3 159, 3 64, S_0xfd15e0; - .timescale -9 -12; -L_0x1009670/d .functor NOR 1, L_0x1030a30, L_0x1030ad0, C4<0>, C4<0>; -L_0x1009670 .delay (10000,10000,10000) L_0x1009670/d; -L_0x1009780/d .functor NOT 1, L_0x1009670, C4<0>, C4<0>, C4<0>; -L_0x1009780 .delay (10000,10000,10000) L_0x1009780/d; -L_0x10098b0/d .functor NAND 1, L_0x1030a30, L_0x1030ad0, C4<1>, C4<1>; -L_0x10098b0 .delay (10000,10000,10000) L_0x10098b0/d; -L_0x1009a10/d .functor NAND 1, L_0x10098b0, L_0x1009780, C4<1>, C4<1>; -L_0x1009a10 .delay (10000,10000,10000) L_0x1009a10/d; -L_0x1009b20/d .functor NOT 1, L_0x1009a10, C4<0>, C4<0>, C4<0>; -L_0x1009b20 .delay (10000,10000,10000) L_0x1009b20/d; -v0xfd22a0_0 .net "A", 0 0, L_0x1030a30; 1 drivers -v0xfd2340_0 .net "AnandB", 0 0, L_0x10098b0; 1 drivers -v0xfd23e0_0 .net "AnorB", 0 0, L_0x1009670; 1 drivers -v0xfd2490_0 .net "AorB", 0 0, L_0x1009780; 1 drivers -v0xfd2540_0 .net "AxorB", 0 0, L_0x1009b20; 1 drivers -v0xfd25f0_0 .net "B", 0 0, L_0x1030ad0; 1 drivers -v0xfd26b0_0 .alias "Command", 2 0, v0xffbc20_0; -v0xfd2730_0 .net "OrNorXorOut", 0 0, L_0x1030760; 1 drivers -v0xfd2830_0 .net "XorNor", 0 0, L_0x1030280; 1 drivers -v0xfd2900_0 .net "nXor", 0 0, L_0x1009a10; 1 drivers -L_0x10303c0 .part v0xffc5e0_0, 2, 1; -L_0x10308f0 .part v0xffc5e0_0, 0, 1; -S_0xfd1d70 .scope module, "mux0" "TwoInMux" 3 83, 3 8, S_0xfd1710; - .timescale -9 -12; -L_0x1030000/d .functor NOT 1, L_0x10303c0, C4<0>, C4<0>, C4<0>; -L_0x1030000 .delay (10000,10000,10000) L_0x1030000/d; -L_0x1030060/d .functor AND 1, L_0x1009b20, L_0x1030000, C4<1>, C4<1>; -L_0x1030060 .delay (20000,20000,20000) L_0x1030060/d; -L_0x1030150/d .functor AND 1, L_0x1009670, L_0x10303c0, C4<1>, C4<1>; -L_0x1030150 .delay (20000,20000,20000) L_0x1030150/d; -L_0x1030280/d .functor OR 1, L_0x1030060, L_0x1030150, C4<0>, C4<0>; -L_0x1030280 .delay (20000,20000,20000) L_0x1030280/d; -v0xfd1e60_0 .net "S", 0 0, L_0x10303c0; 1 drivers -v0xfd1f20_0 .alias "in0", 0 0, v0xfd2540_0; -v0xfd1fc0_0 .alias "in1", 0 0, v0xfd23e0_0; -v0xfd2040_0 .net "nS", 0 0, L_0x1030000; 1 drivers -v0xfd20c0_0 .net "out0", 0 0, L_0x1030060; 1 drivers -v0xfd2140_0 .net "out1", 0 0, L_0x1030150; 1 drivers -v0xfd2220_0 .alias "outfinal", 0 0, v0xfd2830_0; -S_0xfd1800 .scope module, "mux1" "TwoInMux" 3 84, 3 8, S_0xfd1710; - .timescale -9 -12; -L_0x1030460/d .functor NOT 1, L_0x10308f0, C4<0>, C4<0>, C4<0>; -L_0x1030460 .delay (10000,10000,10000) L_0x1030460/d; -L_0x1030500/d .functor AND 1, L_0x1030280, L_0x1030460, C4<1>, C4<1>; -L_0x1030500 .delay (20000,20000,20000) L_0x1030500/d; -L_0x1030630/d .functor AND 1, L_0x1009780, L_0x10308f0, C4<1>, C4<1>; -L_0x1030630 .delay (20000,20000,20000) L_0x1030630/d; -L_0x1030760/d .functor OR 1, L_0x1030500, L_0x1030630, C4<0>, C4<0>; -L_0x1030760 .delay (20000,20000,20000) L_0x1030760/d; -v0xfd18f0_0 .net "S", 0 0, L_0x10308f0; 1 drivers -v0xfd1990_0 .alias "in0", 0 0, v0xfd2830_0; -v0xfd1a30_0 .alias "in1", 0 0, v0xfd2490_0; -v0xfd1ad0_0 .net "nS", 0 0, L_0x1030460; 1 drivers -v0xfd1b50_0 .net "out0", 0 0, L_0x1030500; 1 drivers -v0xfd1bf0_0 .net "out1", 0 0, L_0x1030630; 1 drivers -v0xfd1cd0_0 .alias "outfinal", 0 0, v0xfd2730_0; -S_0xfd01f0 .scope generate, "orbits[3]" "orbits[3]" 3 157, 3 157, S_0xfd0080; - .timescale -9 -12; -P_0xfd02e8 .param/l "i" 3 157, +C4<011>; -S_0xfd0380 .scope module, "attempt" "OrNorXor" 3 159, 3 64, S_0xfd01f0; - .timescale -9 -12; -L_0x1030bb0/d .functor NOR 1, L_0x1031cf0, L_0x1031d90, C4<0>, C4<0>; -L_0x1030bb0 .delay (10000,10000,10000) L_0x1030bb0/d; -L_0x1030ca0/d .functor NOT 1, L_0x1030bb0, C4<0>, C4<0>, C4<0>; -L_0x1030ca0 .delay (10000,10000,10000) L_0x1030ca0/d; -L_0x1030d90/d .functor NAND 1, L_0x1031cf0, L_0x1031d90, C4<1>, C4<1>; -L_0x1030d90 .delay (10000,10000,10000) L_0x1030d90/d; -L_0x1030ed0/d .functor NAND 1, L_0x1030d90, L_0x1030ca0, C4<1>, C4<1>; -L_0x1030ed0 .delay (10000,10000,10000) L_0x1030ed0/d; -L_0x1030fe0/d .functor NOT 1, L_0x1030ed0, C4<0>, C4<0>, C4<0>; -L_0x1030fe0 .delay (10000,10000,10000) L_0x1030fe0/d; -v0xfd0f50_0 .net "A", 0 0, L_0x1031cf0; 1 drivers -v0xfd0ff0_0 .net "AnandB", 0 0, L_0x1030d90; 1 drivers -v0xfd1090_0 .net "AnorB", 0 0, L_0x1030bb0; 1 drivers -v0xfd1140_0 .net "AorB", 0 0, L_0x1030ca0; 1 drivers -v0xfd1220_0 .net "AxorB", 0 0, L_0x1030fe0; 1 drivers -v0xfd12d0_0 .net "B", 0 0, L_0x1031d90; 1 drivers -v0xfd1390_0 .alias "Command", 2 0, v0xffbc20_0; -v0xfd1410_0 .net "OrNorXorOut", 0 0, L_0x10319e0; 1 drivers -v0xfd1490_0 .net "XorNor", 0 0, L_0x1031460; 1 drivers -v0xfd1560_0 .net "nXor", 0 0, L_0x1030ed0; 1 drivers -L_0x10315e0 .part v0xffc5e0_0, 2, 1; -L_0x1031bb0 .part v0xffc5e0_0, 0, 1; -S_0xfd09e0 .scope module, "mux0" "TwoInMux" 3 83, 3 8, S_0xfd0380; - .timescale -9 -12; -L_0x1031140/d .functor NOT 1, L_0x10315e0, C4<0>, C4<0>, C4<0>; -L_0x1031140 .delay (10000,10000,10000) L_0x1031140/d; -L_0x1031200/d .functor AND 1, L_0x1030fe0, L_0x1031140, C4<1>, C4<1>; -L_0x1031200 .delay (20000,20000,20000) L_0x1031200/d; -L_0x1031310/d .functor AND 1, L_0x1030bb0, L_0x10315e0, C4<1>, C4<1>; -L_0x1031310 .delay (20000,20000,20000) L_0x1031310/d; -L_0x1031460/d .functor OR 1, L_0x1031200, L_0x1031310, C4<0>, C4<0>; -L_0x1031460 .delay (20000,20000,20000) L_0x1031460/d; -v0xfd0ad0_0 .net "S", 0 0, L_0x10315e0; 1 drivers -v0xfd0b90_0 .alias "in0", 0 0, v0xfd1220_0; -v0xfd0c30_0 .alias "in1", 0 0, v0xfd1090_0; -v0xfd0cd0_0 .net "nS", 0 0, L_0x1031140; 1 drivers -v0xfd0d50_0 .net "out0", 0 0, L_0x1031200; 1 drivers -v0xfd0df0_0 .net "out1", 0 0, L_0x1031310; 1 drivers -v0xfd0ed0_0 .alias "outfinal", 0 0, v0xfd1490_0; -S_0xfd0470 .scope module, "mux1" "TwoInMux" 3 84, 3 8, S_0xfd0380; - .timescale -9 -12; -L_0x1031680/d .functor NOT 1, L_0x1031bb0, C4<0>, C4<0>, C4<0>; -L_0x1031680 .delay (10000,10000,10000) L_0x1031680/d; -L_0x1031740/d .functor AND 1, L_0x1031460, L_0x1031680, C4<1>, C4<1>; -L_0x1031740 .delay (20000,20000,20000) L_0x1031740/d; -L_0x1031890/d .functor AND 1, L_0x1030ca0, L_0x1031bb0, C4<1>, C4<1>; -L_0x1031890 .delay (20000,20000,20000) L_0x1031890/d; -L_0x10319e0/d .functor OR 1, L_0x1031740, L_0x1031890, C4<0>, C4<0>; -L_0x10319e0 .delay (20000,20000,20000) L_0x10319e0/d; -v0xfd0560_0 .net "S", 0 0, L_0x1031bb0; 1 drivers -v0xfd0600_0 .alias "in0", 0 0, v0xfd1490_0; -v0xfd06a0_0 .alias "in1", 0 0, v0xfd1140_0; -v0xfd0740_0 .net "nS", 0 0, L_0x1031680; 1 drivers -v0xfd07c0_0 .net "out0", 0 0, L_0x1031740; 1 drivers -v0xfd0860_0 .net "out1", 0 0, L_0x1031890; 1 drivers -v0xfd0940_0 .alias "outfinal", 0 0, v0xfd1410_0; -S_0xfcf700 .scope module, "ZeroMux0case" "FourInMux" 3 332, 3 24, S_0xf6f800; - .timescale -9 -12; -L_0x1032fe0/d .functor NOT 1, L_0x101bb40, C4<0>, C4<0>, C4<0>; -L_0x1032fe0 .delay (10000,10000,10000) L_0x1032fe0/d; -L_0x1033230/d .functor NOT 1, L_0x101bc70, C4<0>, C4<0>, C4<0>; -L_0x1033230 .delay (10000,10000,10000) L_0x1033230/d; -L_0x10332f0/d .functor NAND 1, L_0x1032fe0, L_0x1033230, L_0x1033ad0, C4<1>; -L_0x10332f0 .delay (10000,10000,10000) L_0x10332f0/d; -L_0x1033410/d .functor NAND 1, L_0x101bb40, L_0x1033230, L_0x1033b70, C4<1>; -L_0x1033410 .delay (10000,10000,10000) L_0x1033410/d; -L_0x1033560/d .functor NAND 1, L_0x1032fe0, L_0x101bc70, L_0x1033c10, C4<1>; -L_0x1033560 .delay (10000,10000,10000) L_0x1033560/d; -L_0x10336b0/d .functor NAND 1, L_0x101bb40, L_0x101bc70, L_0x1033ff0, C4<1>; -L_0x10336b0 .delay (10000,10000,10000) L_0x10336b0/d; -L_0x1033820/d .functor NAND 1, L_0x10332f0, L_0x1033410, L_0x1033560, L_0x10336b0; -L_0x1033820 .delay (10000,10000,10000) L_0x1033820/d; -v0xfcf7f0_0 .net "S0", 0 0, L_0x101bb40; 1 drivers -v0xfcf8b0_0 .net "S1", 0 0, L_0x101bc70; 1 drivers -v0xfcf950_0 .net "in0", 0 0, L_0x1033ad0; 1 drivers -v0xfcf9f0_0 .net "in1", 0 0, L_0x1033b70; 1 drivers -v0xfcfa70_0 .net "in2", 0 0, L_0x1033c10; 1 drivers -v0xfcfb10_0 .net "in3", 0 0, L_0x1033ff0; 1 drivers -v0xfcfbb0_0 .net "nS0", 0 0, L_0x1032fe0; 1 drivers -v0xfcfc50_0 .net "nS1", 0 0, L_0x1033230; 1 drivers -v0xfcfcf0_0 .net "out", 0 0, L_0x1033820; 1 drivers -v0xfcfd90_0 .net "out0", 0 0, L_0x10332f0; 1 drivers -v0xfcfe30_0 .net "out1", 0 0, L_0x1033410; 1 drivers -v0xfcfed0_0 .net "out2", 0 0, L_0x1033560; 1 drivers -v0xfcffe0_0 .net "out3", 0 0, L_0x10336b0; 1 drivers -S_0xfced40 .scope module, "OneMux0case" "FourInMux" 3 333, 3 24, S_0xf6f800; - .timescale -9 -12; -L_0x1033d70/d .functor NOT 1, L_0x1034990, C4<0>, C4<0>, C4<0>; -L_0x1033d70 .delay (10000,10000,10000) L_0x1033d70/d; -L_0x1033e60/d .functor NOT 1, L_0x10340e0, C4<0>, C4<0>, C4<0>; -L_0x1033e60 .delay (10000,10000,10000) L_0x1033e60/d; -L_0x1033f00/d .functor NAND 1, L_0x1033d70, L_0x1033e60, L_0x1034210, C4<1>; -L_0x1033f00 .delay (10000,10000,10000) L_0x1033f00/d; -L_0x10343c0/d .functor NAND 1, L_0x1034990, L_0x1033e60, L_0x1034d20, C4<1>; -L_0x10343c0 .delay (10000,10000,10000) L_0x10343c0/d; -L_0x10344b0/d .functor NAND 1, L_0x1033d70, L_0x10340e0, L_0x1034dc0, C4<1>; -L_0x10344b0 .delay (10000,10000,10000) L_0x10344b0/d; -L_0x10345a0/d .functor NAND 1, L_0x1034990, L_0x10340e0, L_0x1034ac0, C4<1>; -L_0x10345a0 .delay (10000,10000,10000) L_0x10345a0/d; -L_0x10346e0/d .functor NAND 1, L_0x1033f00, L_0x10343c0, L_0x10344b0, L_0x10345a0; -L_0x10346e0 .delay (10000,10000,10000) L_0x10346e0/d; -v0xfcee30_0 .net "S0", 0 0, L_0x1034990; 1 drivers -v0xfceef0_0 .net "S1", 0 0, L_0x10340e0; 1 drivers -v0xfcef90_0 .net "in0", 0 0, L_0x1034210; 1 drivers -v0xfcf030_0 .net "in1", 0 0, L_0x1034d20; 1 drivers -v0xfcf0b0_0 .net "in2", 0 0, L_0x1034dc0; 1 drivers -v0xfcf150_0 .net "in3", 0 0, L_0x1034ac0; 1 drivers -v0xfcf230_0 .net "nS0", 0 0, L_0x1033d70; 1 drivers -v0xfcf2d0_0 .net "nS1", 0 0, L_0x1033e60; 1 drivers -v0xfcf370_0 .net "out", 0 0, L_0x10346e0; 1 drivers -v0xfcf410_0 .net "out0", 0 0, L_0x1033f00; 1 drivers -v0xfcf4b0_0 .net "out1", 0 0, L_0x10343c0; 1 drivers -v0xfcf550_0 .net "out2", 0 0, L_0x10344b0; 1 drivers -v0xfcf660_0 .net "out3", 0 0, L_0x10345a0; 1 drivers -S_0xfce7f0 .scope module, "TwoMux0case" "TwoInMux" 3 334, 3 8, S_0xf6f800; - .timescale -9 -12; -L_0x1034bb0/d .functor NOT 1, L_0x1034e60, C4<0>, C4<0>, C4<0>; -L_0x1034bb0 .delay (10000,10000,10000) L_0x1034bb0/d; -L_0x1034ca0/d .functor AND 1, L_0x1034f00, L_0x1034bb0, C4<1>, C4<1>; -L_0x1034ca0 .delay (20000,20000,20000) L_0x1034ca0/d; -L_0x1035160/d .functor AND 1, L_0x1034ff0, L_0x1034e60, C4<1>, C4<1>; -L_0x1035160 .delay (20000,20000,20000) L_0x1035160/d; -L_0x1035250/d .functor OR 1, L_0x1034ca0, L_0x1035160, C4<0>, C4<0>; -L_0x1035250 .delay (20000,20000,20000) L_0x1035250/d; -v0xfce8e0_0 .net "S", 0 0, L_0x1034e60; 1 drivers -v0xfce9a0_0 .net "in0", 0 0, L_0x1034f00; 1 drivers -v0xfcea40_0 .net "in1", 0 0, L_0x1034ff0; 1 drivers -v0xfceae0_0 .net "nS", 0 0, L_0x1034bb0; 1 drivers -v0xfceb60_0 .net "out0", 0 0, L_0x1034ca0; 1 drivers -v0xfcec00_0 .net "out1", 0 0, L_0x1035160; 1 drivers -v0xfceca0_0 .net "outfinal", 0 0, L_0x1035250; 1 drivers -S_0xfccc70 .scope generate, "muxbits[1]" "muxbits[1]" 3 339, 3 339, S_0xf6f800; - .timescale -9 -12; -P_0xfcbc68 .param/l "i" 3 339, +C4<01>; -L_0x1016610/d .functor OR 1, L_0x1016710, L_0x10164d0, C4<0>, C4<0>; -L_0x1016610 .delay (20000,20000,20000) L_0x1016610/d; -v0xfce690_0 .net *"_s15", 0 0, L_0x1016710; 1 drivers -v0xfce750_0 .net *"_s16", 0 0, L_0x10164d0; 1 drivers -S_0xfcdd10 .scope module, "ZeroMux" "FourInMux" 3 341, 3 24, S_0xfccc70; - .timescale -9 -12; -L_0x1013d80/d .functor NOT 1, L_0x10146b0, C4<0>, C4<0>, C4<0>; -L_0x1013d80 .delay (10000,10000,10000) L_0x1013d80/d; -L_0x1013fd0/d .functor NOT 1, L_0x10147e0, C4<0>, C4<0>, C4<0>; -L_0x1013fd0 .delay (10000,10000,10000) L_0x1013fd0/d; -L_0x1014030/d .functor NAND 1, L_0x1013d80, L_0x1013fd0, L_0x1014910, C4<1>; -L_0x1014030 .delay (10000,10000,10000) L_0x1014030/d; -L_0x1014170/d .functor NAND 1, L_0x10146b0, L_0x1013fd0, L_0x1014ac0, C4<1>; -L_0x1014170 .delay (10000,10000,10000) L_0x1014170/d; -L_0x1014260/d .functor NAND 1, L_0x1013d80, L_0x10147e0, L_0x1014b60, C4<1>; -L_0x1014260 .delay (10000,10000,10000) L_0x1014260/d; -L_0x1014350/d .functor NAND 1, L_0x10146b0, L_0x10147e0, L_0x1014d10, C4<1>; -L_0x1014350 .delay (10000,10000,10000) L_0x1014350/d; -L_0x1014430/d .functor NAND 1, L_0x1014030, L_0x1014170, L_0x1014260, L_0x1014350; -L_0x1014430 .delay (10000,10000,10000) L_0x1014430/d; -v0xfcde00_0 .net "S0", 0 0, L_0x10146b0; 1 drivers -v0xfcdec0_0 .net "S1", 0 0, L_0x10147e0; 1 drivers -v0xfcdf60_0 .net "in0", 0 0, L_0x1014910; 1 drivers -v0xfce000_0 .net "in1", 0 0, L_0x1014ac0; 1 drivers -v0xfce080_0 .net "in2", 0 0, L_0x1014b60; 1 drivers -v0xfce120_0 .net "in3", 0 0, L_0x1014d10; 1 drivers -v0xfce1c0_0 .net "nS0", 0 0, L_0x1013d80; 1 drivers -v0xfce260_0 .net "nS1", 0 0, L_0x1013fd0; 1 drivers -v0xfce300_0 .net "out", 0 0, L_0x1014430; 1 drivers -v0xfce3a0_0 .net "out0", 0 0, L_0x1014030; 1 drivers -v0xfce440_0 .net "out1", 0 0, L_0x1014170; 1 drivers -v0xfce4e0_0 .net "out2", 0 0, L_0x1014260; 1 drivers -v0xfce5f0_0 .net "out3", 0 0, L_0x1014350; 1 drivers -S_0xfcd350 .scope module, "OneMux" "FourInMux" 3 342, 3 24, S_0xfccc70; - .timescale -9 -12; -L_0x1004660/d .functor NOT 1, L_0x10156b0, C4<0>, C4<0>, C4<0>; -L_0x1004660 .delay (10000,10000,10000) L_0x1004660/d; -L_0x1014f10/d .functor NOT 1, L_0x10157e0, C4<0>, C4<0>, C4<0>; -L_0x1014f10 .delay (10000,10000,10000) L_0x1014f10/d; -L_0x1014fb0/d .functor NAND 1, L_0x1004660, L_0x1014f10, L_0x1015970, C4<1>; -L_0x1014fb0 .delay (10000,10000,10000) L_0x1014fb0/d; -L_0x10150f0/d .functor NAND 1, L_0x10156b0, L_0x1014f10, L_0x1015b20, C4<1>; -L_0x10150f0 .delay (10000,10000,10000) L_0x10150f0/d; -L_0x10151e0/d .functor NAND 1, L_0x1004660, L_0x10157e0, L_0x1015bc0, C4<1>; -L_0x10151e0 .delay (10000,10000,10000) L_0x10151e0/d; -L_0x10152d0/d .functor NAND 1, L_0x10156b0, L_0x10157e0, L_0x1015c60, C4<1>; -L_0x10152d0 .delay (10000,10000,10000) L_0x10152d0/d; -L_0x10153b0/d .functor NAND 1, L_0x1014fb0, L_0x10150f0, L_0x10151e0, L_0x10152d0; -L_0x10153b0 .delay (10000,10000,10000) L_0x10153b0/d; -v0xfcd440_0 .net "S0", 0 0, L_0x10156b0; 1 drivers -v0xfcd500_0 .net "S1", 0 0, L_0x10157e0; 1 drivers -v0xfcd5a0_0 .net "in0", 0 0, L_0x1015970; 1 drivers -v0xfcd640_0 .net "in1", 0 0, L_0x1015b20; 1 drivers -v0xfcd6c0_0 .net "in2", 0 0, L_0x1015bc0; 1 drivers -v0xfcd760_0 .net "in3", 0 0, L_0x1015c60; 1 drivers -v0xfcd840_0 .net "nS0", 0 0, L_0x1004660; 1 drivers -v0xfcd8e0_0 .net "nS1", 0 0, L_0x1014f10; 1 drivers -v0xfcd980_0 .net "out", 0 0, L_0x10153b0; 1 drivers -v0xfcda20_0 .net "out0", 0 0, L_0x1014fb0; 1 drivers -v0xfcdac0_0 .net "out1", 0 0, L_0x10150f0; 1 drivers -v0xfcdb60_0 .net "out2", 0 0, L_0x10151e0; 1 drivers -v0xfcdc70_0 .net "out3", 0 0, L_0x10152d0; 1 drivers -S_0xfccde0 .scope module, "TwoMux" "TwoInMux" 3 343, 3 8, S_0xfccc70; - .timescale -9 -12; -L_0x1015910/d .functor NOT 1, L_0x10161b0, C4<0>, C4<0>, C4<0>; -L_0x1015910 .delay (10000,10000,10000) L_0x1015910/d; -L_0x1015da0/d .functor AND 1, L_0x1016250, L_0x1015910, C4<1>, C4<1>; -L_0x1015da0 .delay (20000,20000,20000) L_0x1015da0/d; -L_0x1015e90/d .functor AND 1, L_0x1016390, L_0x10161b0, C4<1>, C4<1>; -L_0x1015e90 .delay (20000,20000,20000) L_0x1015e90/d; -L_0x1015f80/d .functor OR 1, L_0x1015da0, L_0x1015e90, C4<0>, C4<0>; -L_0x1015f80 .delay (20000,20000,20000) L_0x1015f80/d; -v0xfcced0_0 .net "S", 0 0, L_0x10161b0; 1 drivers -v0xfccf70_0 .net "in0", 0 0, L_0x1016250; 1 drivers -v0xfcd010_0 .net "in1", 0 0, L_0x1016390; 1 drivers -v0xfcd0b0_0 .net "nS", 0 0, L_0x1015910; 1 drivers -v0xfcd130_0 .net "out0", 0 0, L_0x1015da0; 1 drivers -v0xfcd1d0_0 .net "out1", 0 0, L_0x1015e90; 1 drivers -v0xfcd2b0_0 .net "outfinal", 0 0, L_0x1015f80; 1 drivers -S_0xfcb0f0 .scope generate, "muxbits[2]" "muxbits[2]" 3 339, 3 339, S_0xf6f800; - .timescale -9 -12; -P_0xfca038 .param/l "i" 3 339, +C4<010>; -L_0x10185f0/d .functor OR 1, L_0x1018df0, L_0x1019170, C4<0>, C4<0>; -L_0x10185f0 .delay (20000,20000,20000) L_0x10185f0/d; -v0xfccb10_0 .net *"_s15", 0 0, L_0x1018df0; 1 drivers -v0xfccbd0_0 .net *"_s16", 0 0, L_0x1019170; 1 drivers -S_0xfcc190 .scope module, "ZeroMux" "FourInMux" 3 341, 3 24, S_0xfcb0f0; - .timescale -9 -12; -L_0x10168b0/d .functor NOT 1, L_0x10167b0, C4<0>, C4<0>, C4<0>; -L_0x10168b0 .delay (10000,10000,10000) L_0x10168b0/d; -L_0x10169a0/d .functor NOT 1, L_0x10172a0, C4<0>, C4<0>, C4<0>; -L_0x10169a0 .delay (10000,10000,10000) L_0x10169a0/d; -L_0x1016a40/d .functor NAND 1, L_0x10168b0, L_0x10169a0, L_0x1017150, C4<1>; -L_0x1016a40 .delay (10000,10000,10000) L_0x1016a40/d; -L_0x1016b80/d .functor NAND 1, L_0x10167b0, L_0x10169a0, L_0x10174a0, C4<1>; -L_0x1016b80 .delay (10000,10000,10000) L_0x1016b80/d; -L_0x1016c70/d .functor NAND 1, L_0x10168b0, L_0x10172a0, L_0x10173d0, C4<1>; -L_0x1016c70 .delay (10000,10000,10000) L_0x1016c70/d; -L_0x1016d60/d .functor NAND 1, L_0x10167b0, L_0x10172a0, L_0x1017670, C4<1>; -L_0x1016d60 .delay (10000,10000,10000) L_0x1016d60/d; -L_0x1016ea0/d .functor NAND 1, L_0x1016a40, L_0x1016b80, L_0x1016c70, L_0x1016d60; -L_0x1016ea0 .delay (10000,10000,10000) L_0x1016ea0/d; -v0xfcc280_0 .net "S0", 0 0, L_0x10167b0; 1 drivers -v0xfcc340_0 .net "S1", 0 0, L_0x10172a0; 1 drivers -v0xfcc3e0_0 .net "in0", 0 0, L_0x1017150; 1 drivers -v0xfcc480_0 .net "in1", 0 0, L_0x10174a0; 1 drivers -v0xfcc500_0 .net "in2", 0 0, L_0x10173d0; 1 drivers -v0xfcc5a0_0 .net "in3", 0 0, L_0x1017670; 1 drivers -v0xfcc640_0 .net "nS0", 0 0, L_0x10168b0; 1 drivers -v0xfcc6e0_0 .net "nS1", 0 0, L_0x10169a0; 1 drivers -v0xfcc780_0 .net "out", 0 0, L_0x1016ea0; 1 drivers -v0xfcc820_0 .net "out0", 0 0, L_0x1016a40; 1 drivers -v0xfcc8c0_0 .net "out1", 0 0, L_0x1016b80; 1 drivers -v0xfcc960_0 .net "out2", 0 0, L_0x1016c70; 1 drivers -v0xfcca70_0 .net "out3", 0 0, L_0x1016d60; 1 drivers -S_0xfcb7d0 .scope module, "OneMux" "FourInMux" 3 342, 3 24, S_0xfcb0f0; - .timescale -9 -12; -L_0x1017540/d .functor NOT 1, L_0x1018040, C4<0>, C4<0>, C4<0>; -L_0x1017540 .delay (10000,10000,10000) L_0x1017540/d; -L_0x10178a0/d .functor NOT 1, L_0x1017760, C4<0>, C4<0>, C4<0>; -L_0x10178a0 .delay (10000,10000,10000) L_0x10178a0/d; -L_0x1017900/d .functor NAND 1, L_0x1017540, L_0x10178a0, L_0x1018300, C4<1>; -L_0x1017900 .delay (10000,10000,10000) L_0x1017900/d; -L_0x1017a40/d .functor NAND 1, L_0x1018040, L_0x10178a0, L_0x1018170, C4<1>; -L_0x1017a40 .delay (10000,10000,10000) L_0x1017a40/d; -L_0x1017b30/d .functor NAND 1, L_0x1017540, L_0x1017760, L_0x10184b0, C4<1>; -L_0x1017b30 .delay (10000,10000,10000) L_0x1017b30/d; -L_0x1017c20/d .functor NAND 1, L_0x1018040, L_0x1017760, L_0x10183a0, C4<1>; -L_0x1017c20 .delay (10000,10000,10000) L_0x1017c20/d; -L_0x1017d90/d .functor NAND 1, L_0x1017900, L_0x1017a40, L_0x1017b30, L_0x1017c20; -L_0x1017d90 .delay (10000,10000,10000) L_0x1017d90/d; -v0xfcb8c0_0 .net "S0", 0 0, L_0x1018040; 1 drivers -v0xfcb980_0 .net "S1", 0 0, L_0x1017760; 1 drivers -v0xfcba20_0 .net "in0", 0 0, L_0x1018300; 1 drivers -v0xfcbac0_0 .net "in1", 0 0, L_0x1018170; 1 drivers -v0xfcbb40_0 .net "in2", 0 0, L_0x10184b0; 1 drivers -v0xfcbbe0_0 .net "in3", 0 0, L_0x10183a0; 1 drivers -v0xfcbcc0_0 .net "nS0", 0 0, L_0x1017540; 1 drivers -v0xfcbd60_0 .net "nS1", 0 0, L_0x10178a0; 1 drivers -v0xfcbe00_0 .net "out", 0 0, L_0x1017d90; 1 drivers -v0xfcbea0_0 .net "out0", 0 0, L_0x1017900; 1 drivers -v0xfcbf40_0 .net "out1", 0 0, L_0x1017a40; 1 drivers -v0xfcbfe0_0 .net "out2", 0 0, L_0x1017b30; 1 drivers -v0xfcc0f0_0 .net "out3", 0 0, L_0x1017c20; 1 drivers -S_0xfcb260 .scope module, "TwoMux" "TwoInMux" 3 343, 3 8, S_0xfcb0f0; - .timescale -9 -12; -L_0x1018440/d .functor NOT 1, L_0x1018550, C4<0>, C4<0>, C4<0>; -L_0x1018440 .delay (10000,10000,10000) L_0x1018440/d; -L_0x1018700/d .functor AND 1, L_0x1018c80, L_0x1018440, C4<1>, C4<1>; -L_0x1018700 .delay (20000,20000,20000) L_0x1018700/d; -L_0x10187f0/d .functor AND 1, L_0x1018b50, L_0x1018550, C4<1>, C4<1>; -L_0x10187f0 .delay (20000,20000,20000) L_0x10187f0/d; -L_0x10188e0/d .functor OR 1, L_0x1018700, L_0x10187f0, C4<0>, C4<0>; -L_0x10188e0 .delay (20000,20000,20000) L_0x10188e0/d; -v0xfcb350_0 .net "S", 0 0, L_0x1018550; 1 drivers -v0xfcb3f0_0 .net "in0", 0 0, L_0x1018c80; 1 drivers -v0xfcb490_0 .net "in1", 0 0, L_0x1018b50; 1 drivers -v0xfcb530_0 .net "nS", 0 0, L_0x1018440; 1 drivers -v0xfcb5b0_0 .net "out0", 0 0, L_0x1018700; 1 drivers -v0xfcb650_0 .net "out1", 0 0, L_0x10187f0; 1 drivers -v0xfcb730_0 .net "outfinal", 0 0, L_0x10188e0; 1 drivers -S_0xf5f220 .scope generate, "muxbits[3]" "muxbits[3]" 3 339, 3 339, S_0xf6f800; - .timescale -9 -12; -P_0xf1f968 .param/l "i" 3 339, +C4<011>; -L_0x101b720/d .functor OR 1, L_0x101baa0, L_0x101b8b0, C4<0>, C4<0>; -L_0x101b720 .delay (20000,20000,20000) L_0x101b720/d; -v0xfcaf90_0 .net *"_s15", 0 0, L_0x101baa0; 1 drivers -v0xfcb050_0 .net *"_s16", 0 0, L_0x101b8b0; 1 drivers -S_0xfca610 .scope module, "ZeroMux" "FourInMux" 3 341, 3 24, S_0xf5f220; - .timescale -9 -12; -L_0x1019020/d .functor NOT 1, L_0x1019b50, C4<0>, C4<0>, C4<0>; -L_0x1019020 .delay (10000,10000,10000) L_0x1019020/d; -L_0x1019110/d .functor NOT 1, L_0x1019210, C4<0>, C4<0>, C4<0>; -L_0x1019110 .delay (10000,10000,10000) L_0x1019110/d; -L_0x10193b0/d .functor NAND 1, L_0x1019020, L_0x1019110, L_0x1019df0, C4<1>; -L_0x10193b0 .delay (10000,10000,10000) L_0x10193b0/d; -L_0x10194f0/d .functor NAND 1, L_0x1019b50, L_0x1019110, L_0x1019c80, C4<1>; -L_0x10194f0 .delay (10000,10000,10000) L_0x10194f0/d; -L_0x10195e0/d .functor NAND 1, L_0x1019020, L_0x1019210, L_0x1019d20, C4<1>; -L_0x10195e0 .delay (10000,10000,10000) L_0x10195e0/d; -L_0x1019730/d .functor NAND 1, L_0x1019b50, L_0x1019210, L_0x1019e90, C4<1>; -L_0x1019730 .delay (10000,10000,10000) L_0x1019730/d; -L_0x10198a0/d .functor NAND 1, L_0x10193b0, L_0x10194f0, L_0x10195e0, L_0x1019730; -L_0x10198a0 .delay (10000,10000,10000) L_0x10198a0/d; -v0xfca700_0 .net "S0", 0 0, L_0x1019b50; 1 drivers -v0xfca7c0_0 .net "S1", 0 0, L_0x1019210; 1 drivers -v0xfca860_0 .net "in0", 0 0, L_0x1019df0; 1 drivers -v0xfca900_0 .net "in1", 0 0, L_0x1019c80; 1 drivers -v0xfca980_0 .net "in2", 0 0, L_0x1019d20; 1 drivers -v0xfcaa20_0 .net "in3", 0 0, L_0x1019e90; 1 drivers -v0xfcaac0_0 .net "nS0", 0 0, L_0x1019020; 1 drivers -v0xfcab60_0 .net "nS1", 0 0, L_0x1019110; 1 drivers -v0xfcac00_0 .net "out", 0 0, L_0x10198a0; 1 drivers -v0xfcaca0_0 .net "out0", 0 0, L_0x10193b0; 1 drivers -v0xfcad40_0 .net "out1", 0 0, L_0x10194f0; 1 drivers -v0xfcade0_0 .net "out2", 0 0, L_0x10195e0; 1 drivers -v0xfcaef0_0 .net "out3", 0 0, L_0x1019730; 1 drivers -S_0xfc9ba0 .scope module, "OneMux" "FourInMux" 3 342, 3 24, S_0xf5f220; - .timescale -9 -12; -L_0x1019f80/d .functor NOT 1, L_0x101a060, C4<0>, C4<0>, C4<0>; -L_0x1019f80 .delay (10000,10000,10000) L_0x1019f80/d; -L_0x101a280/d .functor NOT 1, L_0x101aba0, C4<0>, C4<0>, C4<0>; -L_0x101a280 .delay (10000,10000,10000) L_0x101a280/d; -L_0x101a320/d .functor NAND 1, L_0x1019f80, L_0x101a280, L_0x101aa00, C4<1>; -L_0x101a320 .delay (10000,10000,10000) L_0x101a320/d; -L_0x101a460/d .functor NAND 1, L_0x101a060, L_0x101a280, L_0x101aaa0, C4<1>; -L_0x101a460 .delay (10000,10000,10000) L_0x101a460/d; -L_0x101a550/d .functor NAND 1, L_0x1019f80, L_0x101aba0, L_0x101ae90, C4<1>; -L_0x101a550 .delay (10000,10000,10000) L_0x101a550/d; -L_0x101a640/d .functor NAND 1, L_0x101a060, L_0x101aba0, L_0x101af30, C4<1>; -L_0x101a640 .delay (10000,10000,10000) L_0x101a640/d; -L_0x101a750/d .functor NAND 1, L_0x101a320, L_0x101a460, L_0x101a550, L_0x101a640; -L_0x101a750 .delay (10000,10000,10000) L_0x101a750/d; -v0xfc9c90_0 .net "S0", 0 0, L_0x101a060; 1 drivers -v0xfc9d50_0 .net "S1", 0 0, L_0x101aba0; 1 drivers -v0xfc9df0_0 .net "in0", 0 0, L_0x101aa00; 1 drivers -v0xfc9e90_0 .net "in1", 0 0, L_0x101aaa0; 1 drivers -v0xfc9f10_0 .net "in2", 0 0, L_0x101ae90; 1 drivers -v0xfc9fb0_0 .net "in3", 0 0, L_0x101af30; 1 drivers -v0xfca090_0 .net "nS0", 0 0, L_0x1019f80; 1 drivers -v0xfca130_0 .net "nS1", 0 0, L_0x101a280; 1 drivers -v0xfca220_0 .net "out", 0 0, L_0x101a750; 1 drivers -v0xfca2c0_0 .net "out0", 0 0, L_0x101a320; 1 drivers -v0xfca3c0_0 .net "out1", 0 0, L_0x101a460; 1 drivers -v0xfca460_0 .net "out2", 0 0, L_0x101a550; 1 drivers -v0xfca570_0 .net "out3", 0 0, L_0x101a640; 1 drivers -S_0xf25ff0 .scope module, "TwoMux" "TwoInMux" 3 343, 3 8, S_0xf5f220; - .timescale -9 -12; -L_0x1014c00/d .functor NOT 1, L_0x101b5e0, C4<0>, C4<0>, C4<0>; -L_0x1014c00 .delay (10000,10000,10000) L_0x1014c00/d; -L_0x101acd0/d .functor AND 1, L_0x101b1e0, L_0x1014c00, C4<1>, C4<1>; -L_0x101acd0 .delay (20000,20000,20000) L_0x101acd0/d; -L_0x101adc0/d .functor AND 1, L_0x101b2d0, L_0x101b5e0, C4<1>, C4<1>; -L_0x101adc0 .delay (20000,20000,20000) L_0x101adc0/d; -L_0x101b400/d .functor OR 1, L_0x101acd0, L_0x101adc0, C4<0>, C4<0>; -L_0x101b400 .delay (20000,20000,20000) L_0x101b400/d; -v0xedf330_0 .net "S", 0 0, L_0x101b5e0; 1 drivers -v0xfc9790_0 .net "in0", 0 0, L_0x101b1e0; 1 drivers -v0xfc9830_0 .net "in1", 0 0, L_0x101b2d0; 1 drivers -v0xfc98d0_0 .net "nS", 0 0, L_0x1014c00; 1 drivers -v0xfc9980_0 .net "out0", 0 0, L_0x101acd0; 1 drivers -v0xfc9a20_0 .net "out1", 0 0, L_0x101adc0; 1 drivers -v0xfc9b00_0 .net "outfinal", 0 0, L_0x101b400; 1 drivers - .scope S_0xeed190; +S_0x22efd20 .scope module, "test32Adder" "test32Adder" 2 126; + .timescale -9 -12; +P_0x1d31a18 .param/l "size" 2 127, +C4<0100000>; +v0x295fe90_0 .var "A", 31 0; +RS_0x7f507e9ad5c8/0/0 .resolv tri, L_0x29618c0, L_0x2962e40, L_0x2964550, L_0x2965bd0; +RS_0x7f507e9ad5c8/0/4 .resolv tri, L_0x2967170, L_0x2968720, L_0x2969c40, L_0x296b160; +RS_0x7f507e9ad5c8/0/8 .resolv tri, L_0x296c770, L_0x296dc80, L_0x296f190, L_0x2970790; +RS_0x7f507e9ad5c8/0/12 .resolv tri, L_0x2971c50, L_0x2973130, L_0x29745a0, L_0x2975a20; +RS_0x7f507e9ad5c8/0/16 .resolv tri, L_0x29770e0, L_0x2978550, L_0x2979e50, L_0x297b220; +RS_0x7f507e9ad5c8/0/20 .resolv tri, L_0x297c6a0, L_0x297dbb0, L_0x297ef70, L_0x2980450; +RS_0x7f507e9ad5c8/0/24 .resolv tri, L_0x2981940, L_0x2982e20, L_0x2984300, L_0x29859d0; +RS_0x7f507e9ad5c8/0/28 .resolv tri, L_0x2986ec0, L_0x29885c0, L_0x2989ab0, L_0x298afa0; +RS_0x7f507e9ad5c8/0/32 .resolv tri, L_0x2aa88d0, L_0x2aa9e10, L_0x2aab350, L_0x2aac950; +RS_0x7f507e9ad5c8/0/36 .resolv tri, L_0x2aadef0, L_0x2aaf420, L_0x2ab0940, L_0x2ab1e60; +RS_0x7f507e9ad5c8/0/40 .resolv tri, L_0x2ab3470, L_0x2ab4980, L_0x2ab5e90, L_0x2ab73a0; +RS_0x7f507e9ad5c8/0/44 .resolv tri, L_0x2ab88a0, L_0x2ab9db0, L_0x2abb2c0, L_0x2abc6f0; +RS_0x7f507e9ad5c8/0/48 .resolv tri, L_0x2abddb0, L_0x2abf220, L_0x2ac06d0, L_0x2ac1aa0; +RS_0x7f507e9ad5c8/0/52 .resolv tri, L_0x2ac2e60, L_0x2ac4370, L_0x2ac5730, L_0x2ac6b70; +RS_0x7f507e9ad5c8/0/56 .resolv tri, L_0x2ac8830, L_0x2ac9d10, L_0x2997ec0, L_0x29993f0; +RS_0x7f507e9ad5c8/0/60 .resolv tri, L_0x299a8d0, L_0x2ad3100, L_0x2ad4540, L_0x2ad6280; +RS_0x7f507e9ad5c8/1/0 .resolv tri, RS_0x7f507e9ad5c8/0/0, RS_0x7f507e9ad5c8/0/4, RS_0x7f507e9ad5c8/0/8, RS_0x7f507e9ad5c8/0/12; +RS_0x7f507e9ad5c8/1/4 .resolv tri, RS_0x7f507e9ad5c8/0/16, RS_0x7f507e9ad5c8/0/20, RS_0x7f507e9ad5c8/0/24, RS_0x7f507e9ad5c8/0/28; +RS_0x7f507e9ad5c8/1/8 .resolv tri, RS_0x7f507e9ad5c8/0/32, RS_0x7f507e9ad5c8/0/36, RS_0x7f507e9ad5c8/0/40, RS_0x7f507e9ad5c8/0/44; +RS_0x7f507e9ad5c8/1/12 .resolv tri, RS_0x7f507e9ad5c8/0/48, RS_0x7f507e9ad5c8/0/52, RS_0x7f507e9ad5c8/0/56, RS_0x7f507e9ad5c8/0/60; +RS_0x7f507e9ad5c8 .resolv tri, RS_0x7f507e9ad5c8/1/0, RS_0x7f507e9ad5c8/1/4, RS_0x7f507e9ad5c8/1/8, RS_0x7f507e9ad5c8/1/12; +v0x295ff30_0 .net8 "AddSubSLTSum", 31 0, RS_0x7f507e9ad5c8; 64 drivers +v0x295ffb0_0 .net "AllZeros", 0 0, L_0x2a25810; 1 drivers +v0x2960030_0 .net "AllZeros2", 0 0, L_0x2c148b0; 1 drivers +RS_0x7f507e9a6998/0/0 .resolv tri, L_0x29d55b0, L_0x29d72e0, L_0x29d7d50, L_0x29d87b0; +RS_0x7f507e9a6998/0/4 .resolv tri, L_0x29d9220, L_0x29d9d80, L_0x29da7f0, L_0x29db250; +RS_0x7f507e9a6998/0/8 .resolv tri, L_0x29dbcd0, L_0x29dc740, L_0x29dd1b0, L_0x29ddc20; +RS_0x7f507e9a6998/0/12 .resolv tri, L_0x29de6a0, L_0x29df210, L_0x29dfc80, L_0x29e06f0; +RS_0x7f507e9a6998/0/16 .resolv tri, L_0x29e1170, L_0x29e1bd0, L_0x29e2650, L_0x29e30b0; +RS_0x7f507e9a6998/0/20 .resolv tri, L_0x29e3b20, L_0x29e4590, L_0x29e5010, L_0x29e5a70; +RS_0x7f507e9a6998/0/24 .resolv tri, L_0x29e64e0, L_0x29e6f40, L_0x29e79b0, L_0x29e8420; +RS_0x7f507e9a6998/0/28 .resolv tri, L_0x29e8ea0, L_0x29e9a60, L_0x29ea410, L_0x29eadc0; +RS_0x7f507e9a6998/0/32 .resolv tri, L_0x2ad6970, L_0x2ad8130, L_0x2ad8ba0, L_0x2ad9600; +RS_0x7f507e9a6998/0/36 .resolv tri, L_0x2ada070, L_0x2adab40, L_0x2adb640, L_0x2adc0a0; +RS_0x7f507e9a6998/0/40 .resolv tri, L_0x2adcb20, L_0x2add3f0, L_0x2addda0, L_0x2ade750; +RS_0x7f507e9a6998/0/44 .resolv tri, L_0x2adf1d0, L_0x2adfc30, L_0x2ae06a0, L_0x2ae1110; +RS_0x7f507e9a6998/0/48 .resolv tri, L_0x2ae1b90, L_0x2ae25f0, L_0x2ae3070, L_0x2ae3ad0; +RS_0x7f507e9a6998/0/52 .resolv tri, L_0x2ae4540, L_0x2ae4fb0, L_0x2ae5a30, L_0x2ae6490; +RS_0x7f507e9a6998/0/56 .resolv tri, L_0x2ae6f00, L_0x2ae7960, L_0x2ae83d0, L_0x2ae8e40; +RS_0x7f507e9a6998/0/60 .resolv tri, L_0x2ae98c0, L_0x2aea320, L_0x2aead90, L_0x2aec010; +RS_0x7f507e9a6998/1/0 .resolv tri, RS_0x7f507e9a6998/0/0, RS_0x7f507e9a6998/0/4, RS_0x7f507e9a6998/0/8, RS_0x7f507e9a6998/0/12; +RS_0x7f507e9a6998/1/4 .resolv tri, RS_0x7f507e9a6998/0/16, RS_0x7f507e9a6998/0/20, RS_0x7f507e9a6998/0/24, RS_0x7f507e9a6998/0/28; +RS_0x7f507e9a6998/1/8 .resolv tri, RS_0x7f507e9a6998/0/32, RS_0x7f507e9a6998/0/36, RS_0x7f507e9a6998/0/40, RS_0x7f507e9a6998/0/44; +RS_0x7f507e9a6998/1/12 .resolv tri, RS_0x7f507e9a6998/0/48, RS_0x7f507e9a6998/0/52, RS_0x7f507e9a6998/0/56, RS_0x7f507e9a6998/0/60; +RS_0x7f507e9a6998 .resolv tri, RS_0x7f507e9a6998/1/0, RS_0x7f507e9a6998/1/4, RS_0x7f507e9a6998/1/8, RS_0x7f507e9a6998/1/12; +v0x2960110_0 .net8 "AndNandOut", 31 0, RS_0x7f507e9a6998; 64 drivers +v0x2960190_0 .var "B", 31 0; +v0x2960210_0 .var "Command", 2 0; +RS_0x7f507e9b8fc8/0/0 .resolv tri, L_0x2a13d10, L_0x2a16700, L_0x2a19020, L_0x2a1b8b0; +RS_0x7f507e9b8fc8/0/4 .resolv tri, L_0x2a1e380, L_0x2a20c00, L_0x2a22df0, L_0x2a25b80; +RS_0x7f507e9b8fc8/0/8 .resolv tri, L_0x2a287f0, L_0x2a0e150, L_0x2a2dbd0, L_0x2a30380; +RS_0x7f507e9b8fc8/0/12 .resolv tri, L_0x2a32b70, L_0x2a353a0, L_0x2a369f0, L_0x2a39c30; +RS_0x7f507e9b8fc8/0/16 .resolv tri, L_0x2a3cf20, L_0x2a3f4f0, L_0x2a42060, L_0x2a44820; +RS_0x7f507e9b8fc8/0/20 .resolv tri, L_0x2a46db0, L_0x2a49350, L_0x2a4b310, L_0x2a4d770; +RS_0x7f507e9b8fc8/0/24 .resolv tri, L_0x2a505f0, L_0x2a52c10, L_0x2a55190, L_0x2a577a0; +RS_0x7f507e9b8fc8/0/28 .resolv tri, L_0x2a5a170, L_0x2a5db60, L_0x2a2b1f0, L_0x2b15ad0; +RS_0x7f507e9b8fc8/1/0 .resolv tri, RS_0x7f507e9b8fc8/0/0, RS_0x7f507e9b8fc8/0/4, RS_0x7f507e9b8fc8/0/8, RS_0x7f507e9b8fc8/0/12; +RS_0x7f507e9b8fc8/1/4 .resolv tri, RS_0x7f507e9b8fc8/0/16, RS_0x7f507e9b8fc8/0/20, RS_0x7f507e9b8fc8/0/24, RS_0x7f507e9b8fc8/0/28; +RS_0x7f507e9b8fc8 .resolv tri, RS_0x7f507e9b8fc8/1/0, RS_0x7f507e9b8fc8/1/4, C4, C4; +v0x2960290_0 .net8 "OneBitFinalOut", 31 0, RS_0x7f507e9b8fc8; 32 drivers +RS_0x7f507e9f0b38/0/0 .resolv tri, L_0x2b196d0, L_0x2b1c090, L_0x2b1ea60, L_0x2b21190; +RS_0x7f507e9f0b38/0/4 .resolv tri, L_0x2b237b0, L_0x2b264d0, L_0x2b284c0, L_0x2b2b410; +RS_0x7f507e9f0b38/0/8 .resolv tri, L_0x2b2dee0, L_0x2b305e0, L_0x2b326c0, L_0x2b35640; +RS_0x7f507e9f0b38/0/12 .resolv tri, L_0x2b37e90, L_0x2b3a6b0, L_0x2b3cf60, L_0x2b3fb50; +RS_0x7f507e9f0b38/0/16 .resolv tri, L_0x2b41820, L_0x2b44360, L_0x2b46d90, L_0x2b49550; +RS_0x7f507e9f0b38/0/20 .resolv tri, L_0x2b4b730, L_0x2b4e660, L_0x2b506d0, L_0x2b54750; +RS_0x7f507e9f0b38/0/24 .resolv tri, L_0x2b55e40, L_0x2b58640, L_0x2b5ad30, L_0x2b5d580; +RS_0x7f507e9f0b38/0/28 .resolv tri, L_0x2b5fdd0, L_0x2b63a50, L_0x2b64480, L_0x2b4c8d0; +RS_0x7f507e9f0b38/1/0 .resolv tri, RS_0x7f507e9f0b38/0/0, RS_0x7f507e9f0b38/0/4, RS_0x7f507e9f0b38/0/8, RS_0x7f507e9f0b38/0/12; +RS_0x7f507e9f0b38/1/4 .resolv tri, RS_0x7f507e9f0b38/0/16, RS_0x7f507e9f0b38/0/20, RS_0x7f507e9f0b38/0/24, RS_0x7f507e9f0b38/0/28; +RS_0x7f507e9f0b38 .resolv tri, RS_0x7f507e9f0b38/1/0, RS_0x7f507e9f0b38/1/4, C4, C4; +v0x2960310_0 .net8 "OneBitFinalOut2", 31 0, RS_0x7f507e9f0b38; 32 drivers +RS_0x7f507e9a3368/0/0 .resolv tri, L_0x29ebfa0, L_0x29ed0e0, L_0x29ee260, L_0x29ef550; +RS_0x7f507e9a3368/0/4 .resolv tri, L_0x29f0850, L_0x29f1c40, L_0x29f2f40, L_0x29f4230; +RS_0x7f507e9a3368/0/8 .resolv tri, L_0x29f5540, L_0x29f6720, L_0x29f78e0, L_0x29f8bd0; +RS_0x7f507e9a3368/0/12 .resolv tri, L_0x29f9ef0, L_0x29fb300, L_0x29fc600, L_0x29fd8f0; +RS_0x7f507e9a3368/0/16 .resolv tri, L_0x29fec00, L_0x29ffef0, L_0x2a02200, L_0x2a033c0; +RS_0x7f507e9a3368/0/20 .resolv tri, L_0x2a046d0, L_0x2a059c0, L_0x2a06cc0, L_0x2a07f80; +RS_0x7f507e9a3368/0/24 .resolv tri, L_0x2a09280, L_0x2a0a570, L_0x2a0b880, L_0x2a0cb80; +RS_0x7f507e9a3368/0/28 .resolv tri, L_0x2a0de80, L_0x2a0f240, L_0x2a10550, L_0x2a11840; +RS_0x7f507e9a3368/0/32 .resolv tri, L_0x2aed1f0, L_0x2aee2f0, L_0x2aef450, L_0x2af0740; +RS_0x7f507e9a3368/0/36 .resolv tri, L_0x2af1a40, L_0x2af2da0, L_0x2af4130, L_0x2af5420; +RS_0x7f507e9a3368/0/40 .resolv tri, L_0x2af6730, L_0x2af7a30, L_0x2af8d30, L_0x2afa020; +RS_0x7f507e9a3368/0/44 .resolv tri, L_0x2afb340, L_0x2afc640, L_0x2afd940, L_0x2afea20; +RS_0x7f507e9a3368/0/48 .resolv tri, L_0x2affc30, L_0x2b00f20, L_0x2a011b0, L_0x2b054d0; +RS_0x7f507e9a3368/0/52 .resolv tri, L_0x2b067e0, L_0x2b07ad0, L_0x2b08dd0, L_0x2b0a0d0; +RS_0x7f507e9a3368/0/56 .resolv tri, L_0x2b0b3d0, L_0x2b0c6c0, L_0x2b0d9f0, L_0x2b0ecf0; +RS_0x7f507e9a3368/0/60 .resolv tri, L_0x2b0fff0, L_0x2b112e0, L_0x2b125f0, L_0x2b13900; +RS_0x7f507e9a3368/1/0 .resolv tri, RS_0x7f507e9a3368/0/0, RS_0x7f507e9a3368/0/4, RS_0x7f507e9a3368/0/8, RS_0x7f507e9a3368/0/12; +RS_0x7f507e9a3368/1/4 .resolv tri, RS_0x7f507e9a3368/0/16, RS_0x7f507e9a3368/0/20, RS_0x7f507e9a3368/0/24, RS_0x7f507e9a3368/0/28; +RS_0x7f507e9a3368/1/8 .resolv tri, RS_0x7f507e9a3368/0/32, RS_0x7f507e9a3368/0/36, RS_0x7f507e9a3368/0/40, RS_0x7f507e9a3368/0/44; +RS_0x7f507e9a3368/1/12 .resolv tri, RS_0x7f507e9a3368/0/48, RS_0x7f507e9a3368/0/52, RS_0x7f507e9a3368/0/56, RS_0x7f507e9a3368/0/60; +RS_0x7f507e9a3368 .resolv tri, RS_0x7f507e9a3368/1/0, RS_0x7f507e9a3368/1/4, RS_0x7f507e9a3368/1/8, RS_0x7f507e9a3368/1/12; +v0x29603c0_0 .net8 "OrNorXorOut", 31 0, RS_0x7f507e9a3368; 64 drivers +RS_0x7f507e9b8c98/0/0 .resolv tri, L_0x298e080, L_0x2990460, L_0x2992620, L_0x29948c0; +RS_0x7f507e9b8c98/0/4 .resolv tri, L_0x2996b20, L_0x2892a70, L_0x299d060, L_0x299f440; +RS_0x7f507e9b8c98/0/8 .resolv tri, L_0x29a1630, L_0x29a3800, L_0x29a59e0, L_0x29a7da0; +RS_0x7f507e9b8c98/0/12 .resolv tri, L_0x29aa050, L_0x29ac2e0, L_0x29ae5d0, L_0x29b0af0; +RS_0x7f507e9b8c98/0/16 .resolv tri, L_0x29b1f90, L_0x29b48c0, L_0x298d620, L_0x29b99d0; +RS_0x7f507e9b8c98/0/20 .resolv tri, L_0x29bbc70, L_0x29bd990, L_0x29c0440, L_0x29c2500; +RS_0x7f507e9b8c98/0/24 .resolv tri, L_0x29c4810, L_0x29c6500, L_0x29c97d0, L_0x29cb9b0; +RS_0x7f507e9b8c98/0/28 .resolv tri, L_0x29cdba0, L_0x29cff90, L_0x29d2180, L_0x29d5e90; +RS_0x7f507e9b8c98/0/32 .resolv tri, L_0x2a632c0, L_0x2a65500, L_0x2a67580, L_0x2a697f0; +RS_0x7f507e9b8c98/0/36 .resolv tri, L_0x2a6b8c0, L_0x2a6daa0, L_0x2a6fbd0, L_0x2a71ef0; +RS_0x7f507e9b8c98/0/40 .resolv tri, L_0x2a740e0, L_0x2a76340, L_0x2a784f0, L_0x2a7a7e0; +RS_0x7f507e9b8c98/0/44 .resolv tri, L_0x2a7c900, L_0x2a7ea90, L_0x2a80cf0, L_0x2a83250; +RS_0x7f507e9b8c98/0/48 .resolv tri, L_0x2a846f0, L_0x2a87ed0, L_0x2a89760, L_0x2a871e0; +RS_0x7f507e9b8c98/0/52 .resolv tri, L_0x2a8db40, L_0x2a8f910, L_0x2a922f0, L_0x2a94650; +RS_0x7f507e9b8c98/0/56 .resolv tri, L_0x2a966a0, L_0x2a99180, L_0x2a9b350, L_0x2a9d570; +RS_0x7f507e9b8c98/0/60 .resolv tri, L_0x2a9f720, L_0x2aa1920, L_0x2aa3ad0, L_0x2aa7720; +RS_0x7f507e9b8c98/1/0 .resolv tri, RS_0x7f507e9b8c98/0/0, RS_0x7f507e9b8c98/0/4, RS_0x7f507e9b8c98/0/8, RS_0x7f507e9b8c98/0/12; +RS_0x7f507e9b8c98/1/4 .resolv tri, RS_0x7f507e9b8c98/0/16, RS_0x7f507e9b8c98/0/20, RS_0x7f507e9b8c98/0/24, RS_0x7f507e9b8c98/0/28; +RS_0x7f507e9b8c98/1/8 .resolv tri, RS_0x7f507e9b8c98/0/32, RS_0x7f507e9b8c98/0/36, RS_0x7f507e9b8c98/0/40, RS_0x7f507e9b8c98/0/44; +RS_0x7f507e9b8c98/1/12 .resolv tri, RS_0x7f507e9b8c98/0/48, RS_0x7f507e9b8c98/0/52, RS_0x7f507e9b8c98/0/56, RS_0x7f507e9b8c98/0/60; +RS_0x7f507e9b8c98 .resolv tri, RS_0x7f507e9b8c98/1/0, RS_0x7f507e9b8c98/1/4, RS_0x7f507e9b8c98/1/8, RS_0x7f507e9b8c98/1/12; +v0x2960440_0 .net8 "SLTSum", 31 0, RS_0x7f507e9b8c98; 64 drivers +v0x29604c0_0 .net "SLTflag", 0 0, L_0x2a828d0; 1 drivers +v0x2960640_0 .net "SLTflag1", 0 0, L_0x29d5990; 1 drivers +RS_0x7f507e9b8ff8/0/0 .resolv tri, L_0x2a14250, L_0x2a16bd0, L_0x2a19160, L_0x2a1bb70; +RS_0x7f507e9b8ff8/0/4 .resolv tri, L_0x2a1df80, L_0x2a205c0, L_0x2a23200, L_0x2a1ba40; +RS_0x7f507e9b8ff8/0/8 .resolv tri, L_0x2a28000, L_0x2a2a8d0, L_0x2a2d3e0, L_0x2a2fd70; +RS_0x7f507e9b8ff8/0/12 .resolv tri, L_0x2a32370, L_0x2a34d20, L_0x2a36d10, L_0x2a3abb0; +RS_0x7f507e9b8ff8/0/16 .resolv tri, L_0x2a3d4f0, L_0x2a40880, L_0x2a423d0, L_0x2a44b40; +RS_0x7f507e9b8ff8/0/20 .resolv tri, L_0x2a470d0, L_0x2a49670, L_0x2a4b630, L_0x2a4da90; +RS_0x7f507e9b8ff8/0/24 .resolv tri, L_0x2a50910, L_0x2a52f30, L_0x2a554b0, L_0x2a57ac0; +RS_0x7f507e9b8ff8/0/28 .resolv tri, L_0x2a5a490, L_0x2a5c650, L_0x2a2b510, L_0x2a3b060; +RS_0x7f507e9b8ff8/1/0 .resolv tri, RS_0x7f507e9b8ff8/0/0, RS_0x7f507e9b8ff8/0/4, RS_0x7f507e9b8ff8/0/8, RS_0x7f507e9b8ff8/0/12; +RS_0x7f507e9b8ff8/1/4 .resolv tri, RS_0x7f507e9b8ff8/0/16, RS_0x7f507e9b8ff8/0/20, RS_0x7f507e9b8ff8/0/24, RS_0x7f507e9b8ff8/0/28; +RS_0x7f507e9b8ff8 .resolv tri, RS_0x7f507e9b8ff8/1/0, RS_0x7f507e9b8ff8/1/4, C4, C4; +v0x29606c0_0 .net8 "ZeroFlag", 31 0, RS_0x7f507e9b8ff8; 32 drivers +v0x29607f0_0 .var "carryin", 31 0; +RS_0x7f507e9ad6e8 .resolv tri, L_0x2989ff0, L_0x29d2c20, L_0x2a82310, L_0x2ad5950; +v0x2960870_0 .net8 "carryout", 0 0, RS_0x7f507e9ad6e8; 4 drivers +RS_0x7f507e9e4bc8 .resolv tri, L_0x2b886f0, L_0x2bd6820, C4, C4; +v0x2960740_0 .net8 "carryout2", 0 0, RS_0x7f507e9e4bc8; 2 drivers +RS_0x7f507e9ad718 .resolv tri, L_0x298a1c0, L_0x29d4420, L_0x2aa45c0, L_0x2abcea0; +v0x2960980_0 .net8 "overflow", 0 0, RS_0x7f507e9ad718; 4 drivers +RS_0x7f507e9e4bf8 .resolv tri, L_0x2bab990, L_0x2bc33a0, C4, C4; +v0x29608f0_0 .net8 "overflow2", 0 0, RS_0x7f507e9e4bf8; 2 drivers +RS_0x7f507e9ad748/0/0 .resolv tri, L_0x2961b00, L_0x2963070, L_0x29647b0, L_0x2964c60; +RS_0x7f507e9ad748/0/4 .resolv tri, L_0x2966250, L_0x2967800, L_0x2968d00, L_0x296a1f0; +RS_0x7f507e9ad748/0/8 .resolv tri, L_0x296b980, L_0x296ccd0, L_0x296e210, L_0x296f780; +RS_0x7f507e9ad748/0/12 .resolv tri, L_0x2970cf0, L_0x29722f0, L_0x29736e0, L_0x2974b80; +RS_0x7f507e9ad748/0/16 .resolv tri, L_0x29763b0, L_0x2977690, L_0x2979600, L_0x297a030; +RS_0x7f507e9ad748/0/20 .resolv tri, L_0x297b400, L_0x297c880, L_0x297dd90, L_0x297f150; +RS_0x7f507e9ad748/0/24 .resolv tri, L_0x2980630, L_0x2981b20, L_0x2983000, L_0x2984b20; +RS_0x7f507e9ad748/0/28 .resolv tri, L_0x2971e30, L_0x2987370, L_0x29887a0, L_0x2989c90; +RS_0x7f507e9ad748/0/32 .resolv tri, L_0x298cf00, L_0x298f5d0, L_0x29906f0, L_0x2993a80; +RS_0x7f507e9ad748/0/36 .resolv tri, L_0x2994b60, L_0x2996e60, L_0x2892b10, L_0x299d2e0; +RS_0x7f507e9ad748/0/40 .resolv tri, L_0x299f4e0, L_0x29a18b0, L_0x29a38a0, L_0x29a6070; +RS_0x7f507e9ad748/0/44 .resolv tri, L_0x29a7e40, L_0x29aa3f0, L_0x29ac380, L_0x29ae850; +RS_0x7f507e9ad748/0/48 .resolv tri, L_0x29b0b90, L_0x29b3650, L_0x29b5e90, L_0x29b7d30; +RS_0x7f507e9ad748/0/52 .resolv tri, L_0x29ba550, L_0x29bc0c0, L_0x29be8d0, L_0x29c0890; +RS_0x7f507e9ad748/0/56 .resolv tri, L_0x29c28f0, L_0x29c4c80, L_0x29c7440, L_0x29c9a50; +RS_0x7f507e9ad748/0/60 .resolv tri, L_0x29cba50, L_0x29ce140, L_0x29d0030, L_0x29d2310; +RS_0x7f507e9ad748/0/64 .resolv tri, L_0x2a5fce0, L_0x2a646d0, L_0x2a65790, L_0x2a689c0; +RS_0x7f507e9ad748/0/68 .resolv tri, L_0x2a69a90, L_0x2a6bb40, L_0x2a6db40, L_0x2a6fe50; +RS_0x7f507e9ad748/0/72 .resolv tri, L_0x2a71f90, L_0x2a74360, L_0x2a763e0, L_0x2a78b80; +RS_0x7f507e9ad748/0/76 .resolv tri, L_0x2a7a880, L_0x2a7cb80, L_0x2a7eb30, L_0x2a80f20; +RS_0x7f507e9ad748/0/80 .resolv tri, L_0x2a832f0, L_0x2a85db0, L_0x2a87f70, L_0x2a89ca0; +RS_0x7f507e9ad748/0/84 .resolv tri, L_0x2a8c500, L_0x2a8e050, L_0x2a90850, L_0x2a92810; +RS_0x7f507e9ad748/0/88 .resolv tri, L_0x2a94860, L_0x2a96bf0, L_0x2a99220, L_0x2a9b5d0; +RS_0x7f507e9ad748/0/92 .resolv tri, L_0x2a9d610, L_0x2a9f9a0, L_0x2aa19c0, L_0x2aa3c60; +RS_0x7f507e9ad748/0/96 .resolv tri, L_0x2aa8ad0, L_0x2aaa040, L_0x2aab5b0, L_0x2aab9a0; +RS_0x7f507e9ad748/0/100 .resolv tri, L_0x2aacfd0, L_0x2aae4c0, L_0x2aafa00, L_0x2ab0ef0; +RS_0x7f507e9ad748/0/104 .resolv tri, L_0x2ab2680, L_0x2ab39d0, L_0x2ab4f10, L_0x2ab6450; +RS_0x7f507e9ad748/0/108 .resolv tri, L_0x2ab7900, L_0x2ab8e20, L_0x2aba360, L_0x2abb8a0; +RS_0x7f507e9ad748/0/112 .resolv tri, L_0x2abd080, L_0x2abe360, L_0x2abf800, L_0x2ac08b0; +RS_0x7f507e9ad748/0/116 .resolv tri, L_0x2ac1c80, L_0x2ac3040, L_0x2ac4550, L_0x2ac5910; +RS_0x7f507e9ad748/0/120 .resolv tri, L_0x29c6c30, L_0x2ac8a10, L_0x2ac9ef0, L_0x29980a0; +RS_0x7f507e9ad748/0/124 .resolv tri, L_0x29995d0, L_0x299aab0, L_0x2a374c0, L_0x2ad55f0; +RS_0x7f507e9ad748/1/0 .resolv tri, RS_0x7f507e9ad748/0/0, RS_0x7f507e9ad748/0/4, RS_0x7f507e9ad748/0/8, RS_0x7f507e9ad748/0/12; +RS_0x7f507e9ad748/1/4 .resolv tri, RS_0x7f507e9ad748/0/16, RS_0x7f507e9ad748/0/20, RS_0x7f507e9ad748/0/24, RS_0x7f507e9ad748/0/28; +RS_0x7f507e9ad748/1/8 .resolv tri, RS_0x7f507e9ad748/0/32, RS_0x7f507e9ad748/0/36, RS_0x7f507e9ad748/0/40, RS_0x7f507e9ad748/0/44; +RS_0x7f507e9ad748/1/12 .resolv tri, RS_0x7f507e9ad748/0/48, RS_0x7f507e9ad748/0/52, RS_0x7f507e9ad748/0/56, RS_0x7f507e9ad748/0/60; +RS_0x7f507e9ad748/1/16 .resolv tri, RS_0x7f507e9ad748/0/64, RS_0x7f507e9ad748/0/68, RS_0x7f507e9ad748/0/72, RS_0x7f507e9ad748/0/76; +RS_0x7f507e9ad748/1/20 .resolv tri, RS_0x7f507e9ad748/0/80, RS_0x7f507e9ad748/0/84, RS_0x7f507e9ad748/0/88, RS_0x7f507e9ad748/0/92; +RS_0x7f507e9ad748/1/24 .resolv tri, RS_0x7f507e9ad748/0/96, RS_0x7f507e9ad748/0/100, RS_0x7f507e9ad748/0/104, RS_0x7f507e9ad748/0/108; +RS_0x7f507e9ad748/1/28 .resolv tri, RS_0x7f507e9ad748/0/112, RS_0x7f507e9ad748/0/116, RS_0x7f507e9ad748/0/120, RS_0x7f507e9ad748/0/124; +RS_0x7f507e9ad748/2/0 .resolv tri, RS_0x7f507e9ad748/1/0, RS_0x7f507e9ad748/1/4, RS_0x7f507e9ad748/1/8, RS_0x7f507e9ad748/1/12; +RS_0x7f507e9ad748/2/4 .resolv tri, RS_0x7f507e9ad748/1/16, RS_0x7f507e9ad748/1/20, RS_0x7f507e9ad748/1/24, RS_0x7f507e9ad748/1/28; +RS_0x7f507e9ad748 .resolv tri, RS_0x7f507e9ad748/2/0, RS_0x7f507e9ad748/2/4, C4, C4; +v0x2960aa0_0 .net8 "subtract", 31 0, RS_0x7f507e9ad748; 128 drivers +S_0x293c2e0 .scope module, "trial" "AddSubSLT32" 2 154, 3 267, S_0x22efd20; + .timescale -9 -12; +P_0x293a9d8 .param/l "size" 3 281, +C4<0100000>; +L_0x2989ff0/d .functor OR 1, L_0x298a070, C4<0>, C4<0>, C4<0>; +L_0x2989ff0 .delay (20000,20000,20000) L_0x2989ff0/d; +L_0x298a1c0/d .functor XOR 1, RS_0x7f507e9ad6e8, L_0x2976030, C4<0>, C4<0>; +L_0x298a1c0 .delay (40000,40000,40000) L_0x298a1c0/d; +v0x295f580_0 .net "A", 31 0, v0x295fe90_0; 1 drivers +v0x295f620_0 .alias "AddSubSLTSum", 31 0, v0x295ff30_0; +v0x295f6a0_0 .net "B", 31 0, v0x2960190_0; 1 drivers +RS_0x7f507e974678/0/0 .resolv tri, L_0x2961a10, L_0x2962f30, L_0x2964640, L_0x2965cc0; +RS_0x7f507e974678/0/4 .resolv tri, L_0x2967320, L_0x2968810, L_0x2969d30, L_0x296b250; +RS_0x7f507e974678/0/8 .resolv tri, L_0x296c860, L_0x296dd70, L_0x296f280, L_0x2970880; +RS_0x7f507e974678/0/12 .resolv tri, L_0x2967260, L_0x2973220, L_0x2974690, L_0x2975b10; +RS_0x7f507e974678/0/16 .resolv tri, L_0x29771d0, L_0x2978640, L_0x2979f40, L_0x297b310; +RS_0x7f507e974678/0/20 .resolv tri, L_0x297c790, L_0x297dca0, L_0x297f060, L_0x2980540; +RS_0x7f507e974678/0/24 .resolv tri, L_0x2981a30, L_0x2982f10, L_0x29843f0, L_0x2985ac0; +RS_0x7f507e974678/0/28 .resolv tri, L_0x2971d40, L_0x29886b0, L_0x2989ba0, L_0x298b090; +RS_0x7f507e974678/1/0 .resolv tri, RS_0x7f507e974678/0/0, RS_0x7f507e974678/0/4, RS_0x7f507e974678/0/8, RS_0x7f507e974678/0/12; +RS_0x7f507e974678/1/4 .resolv tri, RS_0x7f507e974678/0/16, RS_0x7f507e974678/0/20, RS_0x7f507e974678/0/24, RS_0x7f507e974678/0/28; +RS_0x7f507e974678 .resolv tri, RS_0x7f507e974678/1/0, RS_0x7f507e974678/1/4, C4, C4; +v0x295f720_0 .net8 "CarryoutWire", 31 0, RS_0x7f507e974678; 32 drivers +v0x295f7a0_0 .net "Command", 2 0, v0x2960210_0; 1 drivers +v0x295f820_0 .net *"_s292", 0 0, L_0x298a070; 1 drivers +v0x295f8c0_0 .net/s *"_s293", 0 0, C4<0>; 1 drivers +v0x295f960_0 .net *"_s296", 0 0, L_0x2976030; 1 drivers +v0x295fa50_0 .net "carryin", 31 0, v0x29607f0_0; 1 drivers +v0x295fb60_0 .alias "carryout", 0 0, v0x2960870_0; +v0x295fc70_0 .alias "overflow", 0 0, v0x2960980_0; +v0x295fd80_0 .alias "subtract", 31 0, v0x2960aa0_0; +L_0x29618c0 .part/pv L_0x29613b0, 1, 1, 32; +L_0x2961a10 .part/pv L_0x2961760, 1, 1, 32; +L_0x2961b00 .part/pv L_0x29610b0, 1, 1, 32; +L_0x2961bf0 .part v0x295fe90_0, 1, 1; +L_0x2961c90 .part v0x2960190_0, 1, 1; +L_0x2961dc0 .part RS_0x7f507e974678, 0, 1; +L_0x2962e40 .part/pv L_0x2962990, 2, 1, 32; +L_0x2962f30 .part/pv L_0x2962ce0, 2, 1, 32; +L_0x2963070 .part/pv L_0x29626c0, 2, 1, 32; +L_0x2963160 .part v0x295fe90_0, 2, 1; +L_0x289f010 .part v0x2960190_0, 2, 1; +L_0x289f160 .part RS_0x7f507e974678, 1, 1; +L_0x2964550 .part/pv L_0x2964080, 3, 1, 32; +L_0x2964640 .part/pv L_0x29643f0, 3, 1, 32; +L_0x29647b0 .part/pv L_0x2963db0, 3, 1, 32; +L_0x2964960 .part v0x295fe90_0, 3, 1; +L_0x2964a90 .part v0x2960190_0, 3, 1; +L_0x2964bc0 .part RS_0x7f507e974678, 2, 1; +L_0x2965bd0 .part/pv L_0x2965720, 4, 1, 32; +L_0x2965cc0 .part/pv L_0x2965a70, 4, 1, 32; +L_0x2964c60 .part/pv L_0x2965450, 4, 1, 32; +L_0x2965eb0 .part v0x295fe90_0, 4, 1; +L_0x2965db0 .part v0x2960190_0, 4, 1; +L_0x29660a0 .part RS_0x7f507e974678, 3, 1; +L_0x2967170 .part/pv L_0x2966cc0, 5, 1, 32; +L_0x2967320 .part/pv L_0x2967010, 5, 1, 32; +L_0x2966250 .part/pv L_0x29669f0, 5, 1, 32; +L_0x2967540 .part v0x295fe90_0, 5, 1; +L_0x2967410 .part v0x2960190_0, 5, 1; +L_0x2967760 .part RS_0x7f507e974678, 4, 1; +L_0x2968720 .part/pv L_0x2968250, 6, 1, 32; +L_0x2968810 .part/pv L_0x29685c0, 6, 1, 32; +L_0x2967800 .part/pv L_0x2967f80, 6, 1, 32; +L_0x2968a10 .part v0x295fe90_0, 6, 1; +L_0x2968900 .part v0x2960190_0, 6, 1; +L_0x2968c60 .part RS_0x7f507e974678, 5, 1; +L_0x2969c40 .part/pv L_0x2969790, 7, 1, 32; +L_0x2969d30 .part/pv L_0x2969ae0, 7, 1, 32; +L_0x2968d00 .part/pv L_0x29694c0, 7, 1, 32; +L_0x2969f60 .part v0x295fe90_0, 7, 1; +L_0x2969e20 .part v0x2960190_0, 7, 1; +L_0x296a150 .part RS_0x7f507e974678, 6, 1; +L_0x296b160 .part/pv L_0x296acb0, 8, 1, 32; +L_0x296b250 .part/pv L_0x296b000, 8, 1, 32; +L_0x296a1f0 .part/pv L_0x296a9e0, 8, 1, 32; +L_0x296b4b0 .part v0x295fe90_0, 8, 1; +L_0x296b340 .part v0x2960190_0, 8, 1; +L_0x296b6d0 .part RS_0x7f507e974678, 7, 1; +L_0x296c770 .part/pv L_0x296c2c0, 9, 1, 32; +L_0x296c860 .part/pv L_0x296c610, 9, 1, 32; +L_0x296b980 .part/pv L_0x296bff0, 9, 1, 32; +L_0x296ba70 .part v0x295fe90_0, 9, 1; +L_0x296cb00 .part v0x2960190_0, 9, 1; +L_0x296cc30 .part RS_0x7f507e974678, 8, 1; +L_0x296dc80 .part/pv L_0x296d7d0, 10, 1, 32; +L_0x296dd70 .part/pv L_0x296db20, 10, 1, 32; +L_0x296ccd0 .part/pv L_0x296d500, 10, 1, 32; +L_0x296cdc0 .part v0x295fe90_0, 10, 1; +L_0x296e040 .part v0x2960190_0, 10, 1; +L_0x296e170 .part RS_0x7f507e974678, 9, 1; +L_0x296f190 .part/pv L_0x296ece0, 11, 1, 32; +L_0x296f280 .part/pv L_0x296f030, 11, 1, 32; +L_0x296e210 .part/pv L_0x296ea10, 11, 1, 32; +L_0x29648a0 .part v0x295fe90_0, 11, 1; +L_0x296e2b0 .part v0x2960190_0, 11, 1; +L_0x296f370 .part RS_0x7f507e974678, 10, 1; +L_0x2970790 .part/pv L_0x29702e0, 12, 1, 32; +L_0x2970880 .part/pv L_0x2970630, 12, 1, 32; +L_0x296f780 .part/pv L_0x2970010, 12, 1, 32; +L_0x296f870 .part v0x295fe90_0, 12, 1; +L_0x2970bb0 .part v0x2960190_0, 12, 1; +L_0x2970c50 .part RS_0x7f507e974678, 11, 1; +L_0x2971c50 .part/pv L_0x29717a0, 13, 1, 32; +L_0x2967260 .part/pv L_0x2971af0, 13, 1, 32; +L_0x2970cf0 .part/pv L_0x29714d0, 13, 1, 32; +L_0x2970de0 .part v0x295fe90_0, 13, 1; +L_0x2970e80 .part v0x2960190_0, 13, 1; +L_0x2972250 .part RS_0x7f507e974678, 12, 1; +L_0x2973130 .part/pv L_0x2972ca0, 14, 1, 32; +L_0x2973220 .part/pv L_0x2972ff0, 14, 1, 32; +L_0x29722f0 .part/pv L_0x29729d0, 14, 1, 32; +L_0x29723e0 .part v0x295fe90_0, 14, 1; +L_0x2972480 .part v0x2960190_0, 14, 1; +L_0x2973640 .part RS_0x7f507e974678, 13, 1; +L_0x29745a0 .part/pv L_0x2974110, 15, 1, 32; +L_0x2974690 .part/pv L_0x2974460, 15, 1, 32; +L_0x29736e0 .part/pv L_0x2973e40, 15, 1, 32; +L_0x29737d0 .part v0x295fe90_0, 15, 1; +L_0x2973870 .part v0x2960190_0, 15, 1; +L_0x2974ae0 .part RS_0x7f507e974678, 14, 1; +L_0x2975a20 .part/pv L_0x2975590, 16, 1, 32; +L_0x2975b10 .part/pv L_0x29758e0, 16, 1, 32; +L_0x2974b80 .part/pv L_0x29752c0, 16, 1, 32; +L_0x2974c70 .part v0x295fe90_0, 16, 1; +L_0x2974d10 .part v0x2960190_0, 16, 1; +L_0x2975f00 .part RS_0x7f507e974678, 15, 1; +L_0x29770e0 .part/pv L_0x2976c50, 17, 1, 32; +L_0x29771d0 .part/pv L_0x2976fa0, 17, 1, 32; +L_0x29763b0 .part/pv L_0x2976980, 17, 1, 32; +L_0x29764a0 .part v0x295fe90_0, 17, 1; +L_0x2976540 .part v0x2960190_0, 17, 1; +L_0x29775f0 .part RS_0x7f507e974678, 16, 1; +L_0x2978550 .part/pv L_0x29780c0, 18, 1, 32; +L_0x2978640 .part/pv L_0x2978410, 18, 1, 32; +L_0x2977690 .part/pv L_0x2977df0, 18, 1, 32; +L_0x2977780 .part v0x295fe90_0, 18, 1; +L_0x2977820 .part v0x2960190_0, 18, 1; +L_0x2963200 .part RS_0x7f507e974678, 17, 1; +L_0x2979e50 .part/pv L_0x29799c0, 19, 1, 32; +L_0x2979f40 .part/pv L_0x2979d10, 19, 1, 32; +L_0x2979600 .part/pv L_0x2978f70, 19, 1, 32; +L_0x29796f0 .part v0x295fe90_0, 19, 1; +L_0x2979790 .part v0x2960190_0, 19, 1; +L_0x29798c0 .part RS_0x7f507e974678, 18, 1; +L_0x297b220 .part/pv L_0x297ad90, 20, 1, 32; +L_0x297b310 .part/pv L_0x297b0e0, 20, 1, 32; +L_0x297a030 .part/pv L_0x297aac0, 20, 1, 32; +L_0x297a120 .part v0x295fe90_0, 20, 1; +L_0x297a1c0 .part v0x2960190_0, 20, 1; +L_0x297a2f0 .part RS_0x7f507e974678, 19, 1; +L_0x297c6a0 .part/pv L_0x297c1d0, 21, 1, 32; +L_0x297c790 .part/pv L_0x297c540, 21, 1, 32; +L_0x297b400 .part/pv L_0x297bf00, 21, 1, 32; +L_0x297b4f0 .part v0x295fe90_0, 21, 1; +L_0x297b590 .part v0x2960190_0, 21, 1; +L_0x297b6c0 .part RS_0x7f507e974678, 20, 1; +L_0x297dbb0 .part/pv L_0x297d700, 22, 1, 32; +L_0x297dca0 .part/pv L_0x297da50, 22, 1, 32; +L_0x297c880 .part/pv L_0x297d430, 22, 1, 32; +L_0x297c970 .part v0x295fe90_0, 22, 1; +L_0x297ca10 .part v0x2960190_0, 22, 1; +L_0x297cb40 .part RS_0x7f507e974678, 21, 1; +L_0x297ef70 .part/pv L_0x297eae0, 23, 1, 32; +L_0x297f060 .part/pv L_0x297ee30, 23, 1, 32; +L_0x297dd90 .part/pv L_0x297e810, 23, 1, 32; +L_0x297de80 .part v0x295fe90_0, 23, 1; +L_0x297df20 .part v0x2960190_0, 23, 1; +L_0x297e050 .part RS_0x7f507e974678, 22, 1; +L_0x2980450 .part/pv L_0x297ff20, 24, 1, 32; +L_0x2980540 .part/pv L_0x29802f0, 24, 1, 32; +L_0x297f150 .part/pv L_0x297fc50, 24, 1, 32; +L_0x297f240 .part v0x295fe90_0, 24, 1; +L_0x297f2e0 .part v0x2960190_0, 24, 1; +L_0x297f410 .part RS_0x7f507e974678, 23, 1; +L_0x2981940 .part/pv L_0x2981410, 25, 1, 32; +L_0x2981a30 .part/pv L_0x29817e0, 25, 1, 32; +L_0x2980630 .part/pv L_0x2981140, 25, 1, 32; +L_0x2980720 .part v0x295fe90_0, 25, 1; +L_0x29807c0 .part v0x2960190_0, 25, 1; +L_0x29808f0 .part RS_0x7f507e974678, 24, 1; +L_0x2982e20 .part/pv L_0x29828f0, 26, 1, 32; +L_0x2982f10 .part/pv L_0x2982cc0, 26, 1, 32; +L_0x2981b20 .part/pv L_0x2982620, 26, 1, 32; +L_0x2981c10 .part v0x295fe90_0, 26, 1; +L_0x2981cb0 .part v0x2960190_0, 26, 1; +L_0x2981de0 .part RS_0x7f507e974678, 25, 1; +L_0x2984300 .part/pv L_0x2983dd0, 27, 1, 32; +L_0x29843f0 .part/pv L_0x29841a0, 27, 1, 32; +L_0x2983000 .part/pv L_0x2983b00, 27, 1, 32; +L_0x296f5c0 .part v0x295fe90_0, 27, 1; +L_0x296f660 .part v0x2960190_0, 27, 1; +L_0x2984a80 .part RS_0x7f507e974678, 26, 1; +L_0x29859d0 .part/pv L_0x2985540, 28, 1, 32; +L_0x2985ac0 .part/pv L_0x2985890, 28, 1, 32; +L_0x2984b20 .part/pv L_0x2985270, 28, 1, 32; +L_0x2984c10 .part v0x295fe90_0, 28, 1; +L_0x2984cb0 .part v0x2960190_0, 28, 1; +L_0x2984de0 .part RS_0x7f507e974678, 27, 1; +L_0x2986ec0 .part/pv L_0x29869b0, 29, 1, 32; +L_0x2971d40 .part/pv L_0x2986d60, 29, 1, 32; +L_0x2971e30 .part/pv L_0x29866b0, 29, 1, 32; +L_0x2985c00 .part v0x295fe90_0, 29, 1; +L_0x2985ca0 .part v0x2960190_0, 29, 1; +L_0x2985dd0 .part RS_0x7f507e974678, 28, 1; +L_0x29885c0 .part/pv L_0x29880b0, 30, 1, 32; +L_0x29886b0 .part/pv L_0x2988460, 30, 1, 32; +L_0x2987370 .part/pv L_0x2987de0, 30, 1, 32; +L_0x2987460 .part v0x295fe90_0, 30, 1; +L_0x2987500 .part v0x2960190_0, 30, 1; +L_0x2987630 .part RS_0x7f507e974678, 29, 1; +L_0x2989ab0 .part/pv L_0x29895a0, 31, 1, 32; +L_0x2989ba0 .part/pv L_0x2989950, 31, 1, 32; +L_0x29887a0 .part/pv L_0x29892a0, 31, 1, 32; +L_0x2988890 .part v0x295fe90_0, 31, 1; +L_0x2988930 .part v0x2960190_0, 31, 1; +L_0x2988a60 .part RS_0x7f507e974678, 30, 1; +L_0x298afa0 .part/pv L_0x298aa90, 0, 1, 32; +L_0x298b090 .part/pv L_0x298ae40, 0, 1, 32; +L_0x2989c90 .part/pv L_0x298a7c0, 0, 1, 32; +L_0x2989d80 .part v0x295fe90_0, 0, 1; +L_0x2989e20 .part v0x2960190_0, 0, 1; +L_0x2989f50 .part RS_0x7f507e9ad748, 0, 1; +L_0x298a070 .part RS_0x7f507e974678, 31, 1; +L_0x2976030 .part RS_0x7f507e974678, 30, 1; +S_0x295e570 .scope module, "attempt2" "MiddleAddSubSLT" 3 278, 3 189, S_0x293c2e0; + .timescale -9 -12; +L_0x2988b00/d .functor NOT 1, L_0x2989e20, C4<0>, C4<0>, C4<0>; +L_0x2988b00 .delay (10000,10000,10000) L_0x2988b00/d; +L_0x298a680/d .functor NOT 1, L_0x298a720, C4<0>, C4<0>, C4<0>; +L_0x298a680 .delay (10000,10000,10000) L_0x298a680/d; +L_0x298a7c0/d .functor AND 1, L_0x298a900, L_0x298a680, C4<1>, C4<1>; +L_0x298a7c0 .delay (20000,20000,20000) L_0x298a7c0/d; +L_0x298a9a0/d .functor XOR 1, L_0x2989d80, L_0x298a450, C4<0>, C4<0>; +L_0x298a9a0 .delay (40000,40000,40000) L_0x298a9a0/d; +L_0x298aa90/d .functor XOR 1, L_0x298a9a0, L_0x2989f50, C4<0>, C4<0>; +L_0x298aa90 .delay (40000,40000,40000) L_0x298aa90/d; +L_0x298abb0/d .functor AND 1, L_0x2989d80, L_0x298a450, C4<1>, C4<1>; +L_0x298abb0 .delay (20000,20000,20000) L_0x298abb0/d; +L_0x298ad50/d .functor AND 1, L_0x298a9a0, L_0x2989f50, C4<1>, C4<1>; +L_0x298ad50 .delay (20000,20000,20000) L_0x298ad50/d; +L_0x298ae40/d .functor OR 1, L_0x298abb0, L_0x298ad50, C4<0>, C4<0>; +L_0x298ae40 .delay (20000,20000,20000) L_0x298ae40/d; +v0x295ebe0_0 .net "A", 0 0, L_0x2989d80; 1 drivers +v0x295eca0_0 .net "AandB", 0 0, L_0x298abb0; 1 drivers +v0x295ed40_0 .net "AddSubSLTSum", 0 0, L_0x298aa90; 1 drivers +v0x295ede0_0 .net "AxorB", 0 0, L_0x298a9a0; 1 drivers +v0x295ee60_0 .net "B", 0 0, L_0x2989e20; 1 drivers +v0x295ef10_0 .net "BornB", 0 0, L_0x298a450; 1 drivers +v0x295efd0_0 .net "CINandAxorB", 0 0, L_0x298ad50; 1 drivers +v0x295f050_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x295f0d0_0 .net *"_s3", 0 0, L_0x298a720; 1 drivers +v0x295f150_0 .net *"_s5", 0 0, L_0x298a900; 1 drivers +v0x295f1f0_0 .net "carryin", 0 0, L_0x2989f50; 1 drivers +v0x295f290_0 .net "carryout", 0 0, L_0x298ae40; 1 drivers +v0x295f330_0 .net "nB", 0 0, L_0x2988b00; 1 drivers +v0x295f3e0_0 .net "nCmd2", 0 0, L_0x298a680; 1 drivers +v0x295f4e0_0 .net "subtract", 0 0, L_0x298a7c0; 1 drivers +L_0x298a5e0 .part v0x2960210_0, 0, 1; +L_0x298a720 .part v0x2960210_0, 2, 1; +L_0x298a900 .part v0x2960210_0, 0, 1; +S_0x295e660 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x295e570; + .timescale -9 -12; +L_0x2988c60/d .functor NOT 1, L_0x298a5e0, C4<0>, C4<0>, C4<0>; +L_0x2988c60 .delay (10000,10000,10000) L_0x2988c60/d; +L_0x298a270/d .functor AND 1, L_0x2989e20, L_0x2988c60, C4<1>, C4<1>; +L_0x298a270 .delay (20000,20000,20000) L_0x298a270/d; +L_0x298a360/d .functor AND 1, L_0x2988b00, L_0x298a5e0, C4<1>, C4<1>; +L_0x298a360 .delay (20000,20000,20000) L_0x298a360/d; +L_0x298a450/d .functor OR 1, L_0x298a270, L_0x298a360, C4<0>, C4<0>; +L_0x298a450 .delay (20000,20000,20000) L_0x298a450/d; +v0x295e750_0 .net "S", 0 0, L_0x298a5e0; 1 drivers +v0x295e810_0 .alias "in0", 0 0, v0x295ee60_0; +v0x295e8b0_0 .alias "in1", 0 0, v0x295f330_0; +v0x295e950_0 .net "nS", 0 0, L_0x2988c60; 1 drivers +v0x295ea00_0 .net "out0", 0 0, L_0x298a270; 1 drivers +v0x295eaa0_0 .net "out1", 0 0, L_0x298a360; 1 drivers +v0x295eb40_0 .alias "outfinal", 0 0, v0x295ef10_0; +S_0x295d3d0 .scope generate, "addbits[1]" "addbits[1]" 3 283, 3 283, S_0x293c2e0; + .timescale -9 -12; +P_0x295cde8 .param/l "i" 3 283, +C4<01>; +S_0x295d540 .scope module, "attempt" "MiddleAddSubSLT" 3 285, 3 189, S_0x295d3d0; + .timescale -9 -12; +L_0x2951f80/d .functor NOT 1, L_0x2961c90, C4<0>, C4<0>, C4<0>; +L_0x2951f80 .delay (10000,10000,10000) L_0x2951f80/d; +L_0x2960f50/d .functor NOT 1, L_0x2961010, C4<0>, C4<0>, C4<0>; +L_0x2960f50 .delay (10000,10000,10000) L_0x2960f50/d; +L_0x29610b0/d .functor AND 1, L_0x29611f0, L_0x2960f50, C4<1>, C4<1>; +L_0x29610b0 .delay (20000,20000,20000) L_0x29610b0/d; +L_0x2961290/d .functor XOR 1, L_0x2961bf0, L_0x2960ce0, C4<0>, C4<0>; +L_0x2961290 .delay (40000,40000,40000) L_0x2961290/d; +L_0x29613b0/d .functor XOR 1, L_0x2961290, L_0x2961dc0, C4<0>, C4<0>; +L_0x29613b0 .delay (40000,40000,40000) L_0x29613b0/d; +L_0x29614d0/d .functor AND 1, L_0x2961bf0, L_0x2960ce0, C4<1>, C4<1>; +L_0x29614d0 .delay (20000,20000,20000) L_0x29614d0/d; +L_0x2961670/d .functor AND 1, L_0x2961290, L_0x2961dc0, C4<1>, C4<1>; +L_0x2961670 .delay (20000,20000,20000) L_0x2961670/d; +L_0x2961760/d .functor OR 1, L_0x29614d0, L_0x2961670, C4<0>, C4<0>; +L_0x2961760 .delay (20000,20000,20000) L_0x2961760/d; +v0x295dbd0_0 .net "A", 0 0, L_0x2961bf0; 1 drivers +v0x295dc90_0 .net "AandB", 0 0, L_0x29614d0; 1 drivers +v0x295dd30_0 .net "AddSubSLTSum", 0 0, L_0x29613b0; 1 drivers +v0x295ddd0_0 .net "AxorB", 0 0, L_0x2961290; 1 drivers +v0x295de50_0 .net "B", 0 0, L_0x2961c90; 1 drivers +v0x295df00_0 .net "BornB", 0 0, L_0x2960ce0; 1 drivers +v0x295dfc0_0 .net "CINandAxorB", 0 0, L_0x2961670; 1 drivers +v0x295e040_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x295e0c0_0 .net *"_s3", 0 0, L_0x2961010; 1 drivers +v0x295e140_0 .net *"_s5", 0 0, L_0x29611f0; 1 drivers +v0x295e1e0_0 .net "carryin", 0 0, L_0x2961dc0; 1 drivers +v0x295e280_0 .net "carryout", 0 0, L_0x2961760; 1 drivers +v0x295e320_0 .net "nB", 0 0, L_0x2951f80; 1 drivers +v0x295e3d0_0 .net "nCmd2", 0 0, L_0x2960f50; 1 drivers +v0x295e4d0_0 .net "subtract", 0 0, L_0x29610b0; 1 drivers +L_0x2960eb0 .part v0x2960210_0, 0, 1; +L_0x2961010 .part v0x2960210_0, 2, 1; +L_0x29611f0 .part v0x2960210_0, 0, 1; +S_0x295d630 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x295d540; + .timescale -9 -12; +L_0x28a1f90/d .functor NOT 1, L_0x2960eb0, C4<0>, C4<0>, C4<0>; +L_0x28a1f90 .delay (10000,10000,10000) L_0x28a1f90/d; +L_0x2960a40/d .functor AND 1, L_0x2961c90, L_0x28a1f90, C4<1>, C4<1>; +L_0x2960a40 .delay (20000,20000,20000) L_0x2960a40/d; +L_0x2960c40/d .functor AND 1, L_0x2951f80, L_0x2960eb0, C4<1>, C4<1>; +L_0x2960c40 .delay (20000,20000,20000) L_0x2960c40/d; +L_0x2960ce0/d .functor OR 1, L_0x2960a40, L_0x2960c40, C4<0>, C4<0>; +L_0x2960ce0 .delay (20000,20000,20000) L_0x2960ce0/d; +v0x295d720_0 .net "S", 0 0, L_0x2960eb0; 1 drivers +v0x295d7c0_0 .alias "in0", 0 0, v0x295de50_0; +v0x295d860_0 .alias "in1", 0 0, v0x295e320_0; +v0x295d900_0 .net "nS", 0 0, L_0x28a1f90; 1 drivers +v0x295d9b0_0 .net "out0", 0 0, L_0x2960a40; 1 drivers +v0x295da50_0 .net "out1", 0 0, L_0x2960c40; 1 drivers +v0x295db30_0 .alias "outfinal", 0 0, v0x295df00_0; +S_0x295c230 .scope generate, "addbits[2]" "addbits[2]" 3 283, 3 283, S_0x293c2e0; + .timescale -9 -12; +P_0x295bc48 .param/l "i" 3 283, +C4<010>; +S_0x295c3a0 .scope module, "attempt" "MiddleAddSubSLT" 3 285, 3 189, S_0x295c230; + .timescale -9 -12; +L_0x2961e60/d .functor NOT 1, L_0x289f010, C4<0>, C4<0>, C4<0>; +L_0x2961e60 .delay (10000,10000,10000) L_0x2961e60/d; +L_0x2962560/d .functor NOT 1, L_0x2962620, C4<0>, C4<0>, C4<0>; +L_0x2962560 .delay (10000,10000,10000) L_0x2962560/d; +L_0x29626c0/d .functor AND 1, L_0x2962800, L_0x2962560, C4<1>, C4<1>; +L_0x29626c0 .delay (20000,20000,20000) L_0x29626c0/d; +L_0x29628a0/d .functor XOR 1, L_0x2963160, L_0x29622f0, C4<0>, C4<0>; +L_0x29628a0 .delay (40000,40000,40000) L_0x29628a0/d; +L_0x2962990/d .functor XOR 1, L_0x29628a0, L_0x289f160, C4<0>, C4<0>; +L_0x2962990 .delay (40000,40000,40000) L_0x2962990/d; +L_0x2962a80/d .functor AND 1, L_0x2963160, L_0x29622f0, C4<1>, C4<1>; +L_0x2962a80 .delay (20000,20000,20000) L_0x2962a80/d; +L_0x2962bf0/d .functor AND 1, L_0x29628a0, L_0x289f160, C4<1>, C4<1>; +L_0x2962bf0 .delay (20000,20000,20000) L_0x2962bf0/d; +L_0x2962ce0/d .functor OR 1, L_0x2962a80, L_0x2962bf0, C4<0>, C4<0>; +L_0x2962ce0 .delay (20000,20000,20000) L_0x2962ce0/d; +v0x295ca30_0 .net "A", 0 0, L_0x2963160; 1 drivers +v0x295caf0_0 .net "AandB", 0 0, L_0x2962a80; 1 drivers +v0x295cb90_0 .net "AddSubSLTSum", 0 0, L_0x2962990; 1 drivers +v0x295cc30_0 .net "AxorB", 0 0, L_0x29628a0; 1 drivers +v0x295ccb0_0 .net "B", 0 0, L_0x289f010; 1 drivers +v0x295cd60_0 .net "BornB", 0 0, L_0x29622f0; 1 drivers +v0x295ce20_0 .net "CINandAxorB", 0 0, L_0x2962bf0; 1 drivers +v0x295cea0_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x295cf20_0 .net *"_s3", 0 0, L_0x2962620; 1 drivers +v0x295cfa0_0 .net *"_s5", 0 0, L_0x2962800; 1 drivers +v0x295d040_0 .net "carryin", 0 0, L_0x289f160; 1 drivers +v0x295d0e0_0 .net "carryout", 0 0, L_0x2962ce0; 1 drivers +v0x295d180_0 .net "nB", 0 0, L_0x2961e60; 1 drivers +v0x295d230_0 .net "nCmd2", 0 0, L_0x2962560; 1 drivers +v0x295d330_0 .net "subtract", 0 0, L_0x29626c0; 1 drivers +L_0x29624c0 .part v0x2960210_0, 0, 1; +L_0x2962620 .part v0x2960210_0, 2, 1; +L_0x2962800 .part v0x2960210_0, 0, 1; +S_0x295c490 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x295c3a0; + .timescale -9 -12; +L_0x2962010/d .functor NOT 1, L_0x29624c0, C4<0>, C4<0>, C4<0>; +L_0x2962010 .delay (10000,10000,10000) L_0x2962010/d; +L_0x29620d0/d .functor AND 1, L_0x289f010, L_0x2962010, C4<1>, C4<1>; +L_0x29620d0 .delay (20000,20000,20000) L_0x29620d0/d; +L_0x29621e0/d .functor AND 1, L_0x2961e60, L_0x29624c0, C4<1>, C4<1>; +L_0x29621e0 .delay (20000,20000,20000) L_0x29621e0/d; +L_0x29622f0/d .functor OR 1, L_0x29620d0, L_0x29621e0, C4<0>, C4<0>; +L_0x29622f0 .delay (20000,20000,20000) L_0x29622f0/d; +v0x295c580_0 .net "S", 0 0, L_0x29624c0; 1 drivers +v0x295c620_0 .alias "in0", 0 0, v0x295ccb0_0; +v0x295c6c0_0 .alias "in1", 0 0, v0x295d180_0; +v0x295c760_0 .net "nS", 0 0, L_0x2962010; 1 drivers +v0x295c810_0 .net "out0", 0 0, L_0x29620d0; 1 drivers +v0x295c8b0_0 .net "out1", 0 0, L_0x29621e0; 1 drivers +v0x295c990_0 .alias "outfinal", 0 0, v0x295cd60_0; +S_0x295b090 .scope generate, "addbits[3]" "addbits[3]" 3 283, 3 283, S_0x293c2e0; + .timescale -9 -12; +P_0x295aaa8 .param/l "i" 3 283, +C4<011>; +S_0x295b200 .scope module, "attempt" "MiddleAddSubSLT" 3 285, 3 189, S_0x295b090; + .timescale -9 -12; +L_0x289efb0/d .functor NOT 1, L_0x2964a90, C4<0>, C4<0>, C4<0>; +L_0x289efb0 .delay (10000,10000,10000) L_0x289efb0/d; +L_0x2963c50/d .functor NOT 1, L_0x2963d10, C4<0>, C4<0>, C4<0>; +L_0x2963c50 .delay (10000,10000,10000) L_0x2963c50/d; +L_0x2963db0/d .functor AND 1, L_0x2963ef0, L_0x2963c50, C4<1>, C4<1>; +L_0x2963db0 .delay (20000,20000,20000) L_0x2963db0/d; +L_0x2963f90/d .functor XOR 1, L_0x2964960, L_0x29639e0, C4<0>, C4<0>; +L_0x2963f90 .delay (40000,40000,40000) L_0x2963f90/d; +L_0x2964080/d .functor XOR 1, L_0x2963f90, L_0x2964bc0, C4<0>, C4<0>; +L_0x2964080 .delay (40000,40000,40000) L_0x2964080/d; +L_0x2964170/d .functor AND 1, L_0x2964960, L_0x29639e0, C4<1>, C4<1>; +L_0x2964170 .delay (20000,20000,20000) L_0x2964170/d; +L_0x29642e0/d .functor AND 1, L_0x2963f90, L_0x2964bc0, C4<1>, C4<1>; +L_0x29642e0 .delay (20000,20000,20000) L_0x29642e0/d; +L_0x29643f0/d .functor OR 1, L_0x2964170, L_0x29642e0, C4<0>, C4<0>; +L_0x29643f0 .delay (20000,20000,20000) L_0x29643f0/d; +v0x295b890_0 .net "A", 0 0, L_0x2964960; 1 drivers +v0x295b950_0 .net "AandB", 0 0, L_0x2964170; 1 drivers +v0x295b9f0_0 .net "AddSubSLTSum", 0 0, L_0x2964080; 1 drivers +v0x295ba90_0 .net "AxorB", 0 0, L_0x2963f90; 1 drivers +v0x295bb10_0 .net "B", 0 0, L_0x2964a90; 1 drivers +v0x295bbc0_0 .net "BornB", 0 0, L_0x29639e0; 1 drivers +v0x295bc80_0 .net "CINandAxorB", 0 0, L_0x29642e0; 1 drivers +v0x295bd00_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x295bd80_0 .net *"_s3", 0 0, L_0x2963d10; 1 drivers +v0x295be00_0 .net *"_s5", 0 0, L_0x2963ef0; 1 drivers +v0x295bea0_0 .net "carryin", 0 0, L_0x2964bc0; 1 drivers +v0x295bf40_0 .net "carryout", 0 0, L_0x29643f0; 1 drivers +v0x295bfe0_0 .net "nB", 0 0, L_0x289efb0; 1 drivers +v0x295c090_0 .net "nCmd2", 0 0, L_0x2963c50; 1 drivers +v0x295c190_0 .net "subtract", 0 0, L_0x2963db0; 1 drivers +L_0x2963bb0 .part v0x2960210_0, 0, 1; +L_0x2963d10 .part v0x2960210_0, 2, 1; +L_0x2963ef0 .part v0x2960210_0, 0, 1; +S_0x295b2f0 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x295b200; + .timescale -9 -12; +L_0x2963740/d .functor NOT 1, L_0x2963bb0, C4<0>, C4<0>, C4<0>; +L_0x2963740 .delay (10000,10000,10000) L_0x2963740/d; +L_0x29637c0/d .functor AND 1, L_0x2964a90, L_0x2963740, C4<1>, C4<1>; +L_0x29637c0 .delay (20000,20000,20000) L_0x29637c0/d; +L_0x29638d0/d .functor AND 1, L_0x289efb0, L_0x2963bb0, C4<1>, C4<1>; +L_0x29638d0 .delay (20000,20000,20000) L_0x29638d0/d; +L_0x29639e0/d .functor OR 1, L_0x29637c0, L_0x29638d0, C4<0>, C4<0>; +L_0x29639e0 .delay (20000,20000,20000) L_0x29639e0/d; +v0x295b3e0_0 .net "S", 0 0, L_0x2963bb0; 1 drivers +v0x295b480_0 .alias "in0", 0 0, v0x295bb10_0; +v0x295b520_0 .alias "in1", 0 0, v0x295bfe0_0; +v0x295b5c0_0 .net "nS", 0 0, L_0x2963740; 1 drivers +v0x295b670_0 .net "out0", 0 0, L_0x29637c0; 1 drivers +v0x295b710_0 .net "out1", 0 0, L_0x29638d0; 1 drivers +v0x295b7f0_0 .alias "outfinal", 0 0, v0x295bbc0_0; +S_0x2959ef0 .scope generate, "addbits[4]" "addbits[4]" 3 283, 3 283, S_0x293c2e0; + .timescale -9 -12; +P_0x2959908 .param/l "i" 3 283, +C4<0100>; +S_0x295a060 .scope module, "attempt" "MiddleAddSubSLT" 3 285, 3 189, S_0x2959ef0; + .timescale -9 -12; +L_0x2964a00/d .functor NOT 1, L_0x2965db0, C4<0>, C4<0>, C4<0>; +L_0x2964a00 .delay (10000,10000,10000) L_0x2964a00/d; +L_0x29652f0/d .functor NOT 1, L_0x29653b0, C4<0>, C4<0>, C4<0>; +L_0x29652f0 .delay (10000,10000,10000) L_0x29652f0/d; +L_0x2965450/d .functor AND 1, L_0x2965590, L_0x29652f0, C4<1>, C4<1>; +L_0x2965450 .delay (20000,20000,20000) L_0x2965450/d; +L_0x2965630/d .functor XOR 1, L_0x2965eb0, L_0x2965080, C4<0>, C4<0>; +L_0x2965630 .delay (40000,40000,40000) L_0x2965630/d; +L_0x2965720/d .functor XOR 1, L_0x2965630, L_0x29660a0, C4<0>, C4<0>; +L_0x2965720 .delay (40000,40000,40000) L_0x2965720/d; +L_0x2965810/d .functor AND 1, L_0x2965eb0, L_0x2965080, C4<1>, C4<1>; +L_0x2965810 .delay (20000,20000,20000) L_0x2965810/d; +L_0x2965980/d .functor AND 1, L_0x2965630, L_0x29660a0, C4<1>, C4<1>; +L_0x2965980 .delay (20000,20000,20000) L_0x2965980/d; +L_0x2965a70/d .functor OR 1, L_0x2965810, L_0x2965980, C4<0>, C4<0>; +L_0x2965a70 .delay (20000,20000,20000) L_0x2965a70/d; +v0x295a6f0_0 .net "A", 0 0, L_0x2965eb0; 1 drivers +v0x295a7b0_0 .net "AandB", 0 0, L_0x2965810; 1 drivers +v0x295a850_0 .net "AddSubSLTSum", 0 0, L_0x2965720; 1 drivers +v0x295a8f0_0 .net "AxorB", 0 0, L_0x2965630; 1 drivers +v0x295a970_0 .net "B", 0 0, L_0x2965db0; 1 drivers +v0x295aa20_0 .net "BornB", 0 0, L_0x2965080; 1 drivers +v0x295aae0_0 .net "CINandAxorB", 0 0, L_0x2965980; 1 drivers +v0x295ab60_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x295abe0_0 .net *"_s3", 0 0, L_0x29653b0; 1 drivers +v0x295ac60_0 .net *"_s5", 0 0, L_0x2965590; 1 drivers +v0x295ad00_0 .net "carryin", 0 0, L_0x29660a0; 1 drivers +v0x295ada0_0 .net "carryout", 0 0, L_0x2965a70; 1 drivers +v0x295ae40_0 .net "nB", 0 0, L_0x2964a00; 1 drivers +v0x295aef0_0 .net "nCmd2", 0 0, L_0x29652f0; 1 drivers +v0x295aff0_0 .net "subtract", 0 0, L_0x2965450; 1 drivers +L_0x2965250 .part v0x2960210_0, 0, 1; +L_0x29653b0 .part v0x2960210_0, 2, 1; +L_0x2965590 .part v0x2960210_0, 0, 1; +S_0x295a150 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x295a060; + .timescale -9 -12; +L_0x2964da0/d .functor NOT 1, L_0x2965250, C4<0>, C4<0>, C4<0>; +L_0x2964da0 .delay (10000,10000,10000) L_0x2964da0/d; +L_0x2964e60/d .functor AND 1, L_0x2965db0, L_0x2964da0, C4<1>, C4<1>; +L_0x2964e60 .delay (20000,20000,20000) L_0x2964e60/d; +L_0x2964f70/d .functor AND 1, L_0x2964a00, L_0x2965250, C4<1>, C4<1>; +L_0x2964f70 .delay (20000,20000,20000) L_0x2964f70/d; +L_0x2965080/d .functor OR 1, L_0x2964e60, L_0x2964f70, C4<0>, C4<0>; +L_0x2965080 .delay (20000,20000,20000) L_0x2965080/d; +v0x295a240_0 .net "S", 0 0, L_0x2965250; 1 drivers +v0x295a2e0_0 .alias "in0", 0 0, v0x295a970_0; +v0x295a380_0 .alias "in1", 0 0, v0x295ae40_0; +v0x295a420_0 .net "nS", 0 0, L_0x2964da0; 1 drivers +v0x295a4d0_0 .net "out0", 0 0, L_0x2964e60; 1 drivers +v0x295a570_0 .net "out1", 0 0, L_0x2964f70; 1 drivers +v0x295a650_0 .alias "outfinal", 0 0, v0x295aa20_0; +S_0x2958d50 .scope generate, "addbits[5]" "addbits[5]" 3 283, 3 283, S_0x293c2e0; + .timescale -9 -12; +P_0x2958768 .param/l "i" 3 283, +C4<0101>; +S_0x2958ec0 .scope module, "attempt" "MiddleAddSubSLT" 3 285, 3 189, S_0x2958d50; + .timescale -9 -12; +L_0x29636b0/d .functor NOT 1, L_0x2967410, C4<0>, C4<0>, C4<0>; +L_0x29636b0 .delay (10000,10000,10000) L_0x29636b0/d; +L_0x2966890/d .functor NOT 1, L_0x2966950, C4<0>, C4<0>, C4<0>; +L_0x2966890 .delay (10000,10000,10000) L_0x2966890/d; +L_0x29669f0/d .functor AND 1, L_0x2966b30, L_0x2966890, C4<1>, C4<1>; +L_0x29669f0 .delay (20000,20000,20000) L_0x29669f0/d; +L_0x2966bd0/d .functor XOR 1, L_0x2967540, L_0x2966620, C4<0>, C4<0>; +L_0x2966bd0 .delay (40000,40000,40000) L_0x2966bd0/d; +L_0x2966cc0/d .functor XOR 1, L_0x2966bd0, L_0x2967760, C4<0>, C4<0>; +L_0x2966cc0 .delay (40000,40000,40000) L_0x2966cc0/d; +L_0x2966db0/d .functor AND 1, L_0x2967540, L_0x2966620, C4<1>, C4<1>; +L_0x2966db0 .delay (20000,20000,20000) L_0x2966db0/d; +L_0x2966f20/d .functor AND 1, L_0x2966bd0, L_0x2967760, C4<1>, C4<1>; +L_0x2966f20 .delay (20000,20000,20000) L_0x2966f20/d; +L_0x2967010/d .functor OR 1, L_0x2966db0, L_0x2966f20, C4<0>, C4<0>; +L_0x2967010 .delay (20000,20000,20000) L_0x2967010/d; +v0x2959550_0 .net "A", 0 0, L_0x2967540; 1 drivers +v0x2959610_0 .net "AandB", 0 0, L_0x2966db0; 1 drivers +v0x29596b0_0 .net "AddSubSLTSum", 0 0, L_0x2966cc0; 1 drivers +v0x2959750_0 .net "AxorB", 0 0, L_0x2966bd0; 1 drivers +v0x29597d0_0 .net "B", 0 0, L_0x2967410; 1 drivers +v0x2959880_0 .net "BornB", 0 0, L_0x2966620; 1 drivers +v0x2959940_0 .net "CINandAxorB", 0 0, L_0x2966f20; 1 drivers +v0x29599c0_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x2959a40_0 .net *"_s3", 0 0, L_0x2966950; 1 drivers +v0x2959ac0_0 .net *"_s5", 0 0, L_0x2966b30; 1 drivers +v0x2959b60_0 .net "carryin", 0 0, L_0x2967760; 1 drivers +v0x2959c00_0 .net "carryout", 0 0, L_0x2967010; 1 drivers +v0x2959ca0_0 .net "nB", 0 0, L_0x29636b0; 1 drivers +v0x2959d50_0 .net "nCmd2", 0 0, L_0x2966890; 1 drivers +v0x2959e50_0 .net "subtract", 0 0, L_0x29669f0; 1 drivers +L_0x29667f0 .part v0x2960210_0, 0, 1; +L_0x2966950 .part v0x2960210_0, 2, 1; +L_0x2966b30 .part v0x2960210_0, 0, 1; +S_0x2958fb0 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x2958ec0; + .timescale -9 -12; +L_0x2966340/d .functor NOT 1, L_0x29667f0, C4<0>, C4<0>, C4<0>; +L_0x2966340 .delay (10000,10000,10000) L_0x2966340/d; +L_0x2966400/d .functor AND 1, L_0x2967410, L_0x2966340, C4<1>, C4<1>; +L_0x2966400 .delay (20000,20000,20000) L_0x2966400/d; +L_0x2966510/d .functor AND 1, L_0x29636b0, L_0x29667f0, C4<1>, C4<1>; +L_0x2966510 .delay (20000,20000,20000) L_0x2966510/d; +L_0x2966620/d .functor OR 1, L_0x2966400, L_0x2966510, C4<0>, C4<0>; +L_0x2966620 .delay (20000,20000,20000) L_0x2966620/d; +v0x29590a0_0 .net "S", 0 0, L_0x29667f0; 1 drivers +v0x2959140_0 .alias "in0", 0 0, v0x29597d0_0; +v0x29591e0_0 .alias "in1", 0 0, v0x2959ca0_0; +v0x2959280_0 .net "nS", 0 0, L_0x2966340; 1 drivers +v0x2959330_0 .net "out0", 0 0, L_0x2966400; 1 drivers +v0x29593d0_0 .net "out1", 0 0, L_0x2966510; 1 drivers +v0x29594b0_0 .alias "outfinal", 0 0, v0x2959880_0; +S_0x2957bb0 .scope generate, "addbits[6]" "addbits[6]" 3 283, 3 283, S_0x293c2e0; + .timescale -9 -12; +P_0x29575c8 .param/l "i" 3 283, +C4<0110>; +S_0x2957d20 .scope module, "attempt" "MiddleAddSubSLT" 3 285, 3 189, S_0x2957bb0; + .timescale -9 -12; +L_0x29675e0/d .functor NOT 1, L_0x2968900, C4<0>, C4<0>, C4<0>; +L_0x29675e0 .delay (10000,10000,10000) L_0x29675e0/d; +L_0x2967e20/d .functor NOT 1, L_0x2967ee0, C4<0>, C4<0>, C4<0>; +L_0x2967e20 .delay (10000,10000,10000) L_0x2967e20/d; +L_0x2967f80/d .functor AND 1, L_0x29680c0, L_0x2967e20, C4<1>, C4<1>; +L_0x2967f80 .delay (20000,20000,20000) L_0x2967f80/d; +L_0x2968160/d .functor XOR 1, L_0x2968a10, L_0x2967bb0, C4<0>, C4<0>; +L_0x2968160 .delay (40000,40000,40000) L_0x2968160/d; +L_0x2968250/d .functor XOR 1, L_0x2968160, L_0x2968c60, C4<0>, C4<0>; +L_0x2968250 .delay (40000,40000,40000) L_0x2968250/d; +L_0x2968340/d .functor AND 1, L_0x2968a10, L_0x2967bb0, C4<1>, C4<1>; +L_0x2968340 .delay (20000,20000,20000) L_0x2968340/d; +L_0x29684b0/d .functor AND 1, L_0x2968160, L_0x2968c60, C4<1>, C4<1>; +L_0x29684b0 .delay (20000,20000,20000) L_0x29684b0/d; +L_0x29685c0/d .functor OR 1, L_0x2968340, L_0x29684b0, C4<0>, C4<0>; +L_0x29685c0 .delay (20000,20000,20000) L_0x29685c0/d; +v0x29583b0_0 .net "A", 0 0, L_0x2968a10; 1 drivers +v0x2958470_0 .net "AandB", 0 0, L_0x2968340; 1 drivers +v0x2958510_0 .net "AddSubSLTSum", 0 0, L_0x2968250; 1 drivers +v0x29585b0_0 .net "AxorB", 0 0, L_0x2968160; 1 drivers +v0x2958630_0 .net "B", 0 0, L_0x2968900; 1 drivers +v0x29586e0_0 .net "BornB", 0 0, L_0x2967bb0; 1 drivers +v0x29587a0_0 .net "CINandAxorB", 0 0, L_0x29684b0; 1 drivers +v0x2958820_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x29588a0_0 .net *"_s3", 0 0, L_0x2967ee0; 1 drivers +v0x2958920_0 .net *"_s5", 0 0, L_0x29680c0; 1 drivers +v0x29589c0_0 .net "carryin", 0 0, L_0x2968c60; 1 drivers +v0x2958a60_0 .net "carryout", 0 0, L_0x29685c0; 1 drivers +v0x2958b00_0 .net "nB", 0 0, L_0x29675e0; 1 drivers +v0x2958bb0_0 .net "nCmd2", 0 0, L_0x2967e20; 1 drivers +v0x2958cb0_0 .net "subtract", 0 0, L_0x2967f80; 1 drivers +L_0x2967d80 .part v0x2960210_0, 0, 1; +L_0x2967ee0 .part v0x2960210_0, 2, 1; +L_0x29680c0 .part v0x2960210_0, 0, 1; +S_0x2957e10 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x2957d20; + .timescale -9 -12; +L_0x2967950/d .functor NOT 1, L_0x2967d80, C4<0>, C4<0>, C4<0>; +L_0x2967950 .delay (10000,10000,10000) L_0x2967950/d; +L_0x29679b0/d .functor AND 1, L_0x2968900, L_0x2967950, C4<1>, C4<1>; +L_0x29679b0 .delay (20000,20000,20000) L_0x29679b0/d; +L_0x2967aa0/d .functor AND 1, L_0x29675e0, L_0x2967d80, C4<1>, C4<1>; +L_0x2967aa0 .delay (20000,20000,20000) L_0x2967aa0/d; +L_0x2967bb0/d .functor OR 1, L_0x29679b0, L_0x2967aa0, C4<0>, C4<0>; +L_0x2967bb0 .delay (20000,20000,20000) L_0x2967bb0/d; +v0x2957f00_0 .net "S", 0 0, L_0x2967d80; 1 drivers +v0x2957fa0_0 .alias "in0", 0 0, v0x2958630_0; +v0x2958040_0 .alias "in1", 0 0, v0x2958b00_0; +v0x29580e0_0 .net "nS", 0 0, L_0x2967950; 1 drivers +v0x2958190_0 .net "out0", 0 0, L_0x29679b0; 1 drivers +v0x2958230_0 .net "out1", 0 0, L_0x2967aa0; 1 drivers +v0x2958310_0 .alias "outfinal", 0 0, v0x29586e0_0; +S_0x2956a10 .scope generate, "addbits[7]" "addbits[7]" 3 283, 3 283, S_0x293c2e0; + .timescale -9 -12; +P_0x2956428 .param/l "i" 3 283, +C4<0111>; +S_0x2956b80 .scope module, "attempt" "MiddleAddSubSLT" 3 285, 3 189, S_0x2956a10; + .timescale -9 -12; +L_0x29689a0/d .functor NOT 1, L_0x2969e20, C4<0>, C4<0>, C4<0>; +L_0x29689a0 .delay (10000,10000,10000) L_0x29689a0/d; +L_0x2969360/d .functor NOT 1, L_0x2969420, C4<0>, C4<0>, C4<0>; +L_0x2969360 .delay (10000,10000,10000) L_0x2969360/d; +L_0x29694c0/d .functor AND 1, L_0x2969600, L_0x2969360, C4<1>, C4<1>; +L_0x29694c0 .delay (20000,20000,20000) L_0x29694c0/d; +L_0x29696a0/d .functor XOR 1, L_0x2969f60, L_0x29690f0, C4<0>, C4<0>; +L_0x29696a0 .delay (40000,40000,40000) L_0x29696a0/d; +L_0x2969790/d .functor XOR 1, L_0x29696a0, L_0x296a150, C4<0>, C4<0>; +L_0x2969790 .delay (40000,40000,40000) L_0x2969790/d; +L_0x2969880/d .functor AND 1, L_0x2969f60, L_0x29690f0, C4<1>, C4<1>; +L_0x2969880 .delay (20000,20000,20000) L_0x2969880/d; +L_0x29699f0/d .functor AND 1, L_0x29696a0, L_0x296a150, C4<1>, C4<1>; +L_0x29699f0 .delay (20000,20000,20000) L_0x29699f0/d; +L_0x2969ae0/d .functor OR 1, L_0x2969880, L_0x29699f0, C4<0>, C4<0>; +L_0x2969ae0 .delay (20000,20000,20000) L_0x2969ae0/d; +v0x2957210_0 .net "A", 0 0, L_0x2969f60; 1 drivers +v0x29572d0_0 .net "AandB", 0 0, L_0x2969880; 1 drivers +v0x2957370_0 .net "AddSubSLTSum", 0 0, L_0x2969790; 1 drivers +v0x2957410_0 .net "AxorB", 0 0, L_0x29696a0; 1 drivers +v0x2957490_0 .net "B", 0 0, L_0x2969e20; 1 drivers +v0x2957540_0 .net "BornB", 0 0, L_0x29690f0; 1 drivers +v0x2957600_0 .net "CINandAxorB", 0 0, L_0x29699f0; 1 drivers +v0x2957680_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x2957700_0 .net *"_s3", 0 0, L_0x2969420; 1 drivers +v0x2957780_0 .net *"_s5", 0 0, L_0x2969600; 1 drivers +v0x2957820_0 .net "carryin", 0 0, L_0x296a150; 1 drivers +v0x29578c0_0 .net "carryout", 0 0, L_0x2969ae0; 1 drivers +v0x2957960_0 .net "nB", 0 0, L_0x29689a0; 1 drivers +v0x2957a10_0 .net "nCmd2", 0 0, L_0x2969360; 1 drivers +v0x2957b10_0 .net "subtract", 0 0, L_0x29694c0; 1 drivers +L_0x29692c0 .part v0x2960210_0, 0, 1; +L_0x2969420 .part v0x2960210_0, 2, 1; +L_0x2969600 .part v0x2960210_0, 0, 1; +S_0x2956c70 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x2956b80; + .timescale -9 -12; +L_0x2968e30/d .functor NOT 1, L_0x29692c0, C4<0>, C4<0>, C4<0>; +L_0x2968e30 .delay (10000,10000,10000) L_0x2968e30/d; +L_0x2968ed0/d .functor AND 1, L_0x2969e20, L_0x2968e30, C4<1>, C4<1>; +L_0x2968ed0 .delay (20000,20000,20000) L_0x2968ed0/d; +L_0x2968fe0/d .functor AND 1, L_0x29689a0, L_0x29692c0, C4<1>, C4<1>; +L_0x2968fe0 .delay (20000,20000,20000) L_0x2968fe0/d; +L_0x29690f0/d .functor OR 1, L_0x2968ed0, L_0x2968fe0, C4<0>, C4<0>; +L_0x29690f0 .delay (20000,20000,20000) L_0x29690f0/d; +v0x2956d60_0 .net "S", 0 0, L_0x29692c0; 1 drivers +v0x2956e00_0 .alias "in0", 0 0, v0x2957490_0; +v0x2956ea0_0 .alias "in1", 0 0, v0x2957960_0; +v0x2956f40_0 .net "nS", 0 0, L_0x2968e30; 1 drivers +v0x2956ff0_0 .net "out0", 0 0, L_0x2968ed0; 1 drivers +v0x2957090_0 .net "out1", 0 0, L_0x2968fe0; 1 drivers +v0x2957170_0 .alias "outfinal", 0 0, v0x2957540_0; +S_0x2955870 .scope generate, "addbits[8]" "addbits[8]" 3 283, 3 283, S_0x293c2e0; + .timescale -9 -12; +P_0x2955288 .param/l "i" 3 283, +C4<01000>; +S_0x29559e0 .scope module, "attempt" "MiddleAddSubSLT" 3 285, 3 189, S_0x2955870; + .timescale -9 -12; +L_0x296a000/d .functor NOT 1, L_0x296b340, C4<0>, C4<0>, C4<0>; +L_0x296a000 .delay (10000,10000,10000) L_0x296a000/d; +L_0x296a880/d .functor NOT 1, L_0x296a940, C4<0>, C4<0>, C4<0>; +L_0x296a880 .delay (10000,10000,10000) L_0x296a880/d; +L_0x296a9e0/d .functor AND 1, L_0x296ab20, L_0x296a880, C4<1>, C4<1>; +L_0x296a9e0 .delay (20000,20000,20000) L_0x296a9e0/d; +L_0x296abc0/d .functor XOR 1, L_0x296b4b0, L_0x296a610, C4<0>, C4<0>; +L_0x296abc0 .delay (40000,40000,40000) L_0x296abc0/d; +L_0x296acb0/d .functor XOR 1, L_0x296abc0, L_0x296b6d0, C4<0>, C4<0>; +L_0x296acb0 .delay (40000,40000,40000) L_0x296acb0/d; +L_0x296ada0/d .functor AND 1, L_0x296b4b0, L_0x296a610, C4<1>, C4<1>; +L_0x296ada0 .delay (20000,20000,20000) L_0x296ada0/d; +L_0x296af10/d .functor AND 1, L_0x296abc0, L_0x296b6d0, C4<1>, C4<1>; +L_0x296af10 .delay (20000,20000,20000) L_0x296af10/d; +L_0x296b000/d .functor OR 1, L_0x296ada0, L_0x296af10, C4<0>, C4<0>; +L_0x296b000 .delay (20000,20000,20000) L_0x296b000/d; +v0x2956070_0 .net "A", 0 0, L_0x296b4b0; 1 drivers +v0x2956130_0 .net "AandB", 0 0, L_0x296ada0; 1 drivers +v0x29561d0_0 .net "AddSubSLTSum", 0 0, L_0x296acb0; 1 drivers +v0x2956270_0 .net "AxorB", 0 0, L_0x296abc0; 1 drivers +v0x29562f0_0 .net "B", 0 0, L_0x296b340; 1 drivers +v0x29563a0_0 .net "BornB", 0 0, L_0x296a610; 1 drivers +v0x2956460_0 .net "CINandAxorB", 0 0, L_0x296af10; 1 drivers +v0x29564e0_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x2956560_0 .net *"_s3", 0 0, L_0x296a940; 1 drivers +v0x29565e0_0 .net *"_s5", 0 0, L_0x296ab20; 1 drivers +v0x2956680_0 .net "carryin", 0 0, L_0x296b6d0; 1 drivers +v0x2956720_0 .net "carryout", 0 0, L_0x296b000; 1 drivers +v0x29567c0_0 .net "nB", 0 0, L_0x296a000; 1 drivers +v0x2956870_0 .net "nCmd2", 0 0, L_0x296a880; 1 drivers +v0x2956970_0 .net "subtract", 0 0, L_0x296a9e0; 1 drivers +L_0x296a7e0 .part v0x2960210_0, 0, 1; +L_0x296a940 .part v0x2960210_0, 2, 1; +L_0x296ab20 .part v0x2960210_0, 0, 1; +S_0x2955ad0 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x29559e0; + .timescale -9 -12; +L_0x296a350/d .functor NOT 1, L_0x296a7e0, C4<0>, C4<0>, C4<0>; +L_0x296a350 .delay (10000,10000,10000) L_0x296a350/d; +L_0x296a3f0/d .functor AND 1, L_0x296b340, L_0x296a350, C4<1>, C4<1>; +L_0x296a3f0 .delay (20000,20000,20000) L_0x296a3f0/d; +L_0x296a500/d .functor AND 1, L_0x296a000, L_0x296a7e0, C4<1>, C4<1>; +L_0x296a500 .delay (20000,20000,20000) L_0x296a500/d; +L_0x296a610/d .functor OR 1, L_0x296a3f0, L_0x296a500, C4<0>, C4<0>; +L_0x296a610 .delay (20000,20000,20000) L_0x296a610/d; +v0x2955bc0_0 .net "S", 0 0, L_0x296a7e0; 1 drivers +v0x2955c60_0 .alias "in0", 0 0, v0x29562f0_0; +v0x2955d00_0 .alias "in1", 0 0, v0x29567c0_0; +v0x2955da0_0 .net "nS", 0 0, L_0x296a350; 1 drivers +v0x2955e50_0 .net "out0", 0 0, L_0x296a3f0; 1 drivers +v0x2955ef0_0 .net "out1", 0 0, L_0x296a500; 1 drivers +v0x2955fd0_0 .alias "outfinal", 0 0, v0x29563a0_0; +S_0x29546d0 .scope generate, "addbits[9]" "addbits[9]" 3 283, 3 283, S_0x293c2e0; + .timescale -9 -12; +P_0x29540e8 .param/l "i" 3 283, +C4<01001>; +S_0x2954840 .scope module, "attempt" "MiddleAddSubSLT" 3 285, 3 189, S_0x29546d0; + .timescale -9 -12; +L_0x296a2e0/d .functor NOT 1, L_0x296cb00, C4<0>, C4<0>, C4<0>; +L_0x296a2e0 .delay (10000,10000,10000) L_0x296a2e0/d; +L_0x296be90/d .functor NOT 1, L_0x296bf50, C4<0>, C4<0>, C4<0>; +L_0x296be90 .delay (10000,10000,10000) L_0x296be90/d; +L_0x296bff0/d .functor AND 1, L_0x296c130, L_0x296be90, C4<1>, C4<1>; +L_0x296bff0 .delay (20000,20000,20000) L_0x296bff0/d; +L_0x296c1d0/d .functor XOR 1, L_0x296ba70, L_0x296bc20, C4<0>, C4<0>; +L_0x296c1d0 .delay (40000,40000,40000) L_0x296c1d0/d; +L_0x296c2c0/d .functor XOR 1, L_0x296c1d0, L_0x296cc30, C4<0>, C4<0>; +L_0x296c2c0 .delay (40000,40000,40000) L_0x296c2c0/d; +L_0x296c3b0/d .functor AND 1, L_0x296ba70, L_0x296bc20, C4<1>, C4<1>; +L_0x296c3b0 .delay (20000,20000,20000) L_0x296c3b0/d; +L_0x296c520/d .functor AND 1, L_0x296c1d0, L_0x296cc30, C4<1>, C4<1>; +L_0x296c520 .delay (20000,20000,20000) L_0x296c520/d; +L_0x296c610/d .functor OR 1, L_0x296c3b0, L_0x296c520, C4<0>, C4<0>; +L_0x296c610 .delay (20000,20000,20000) L_0x296c610/d; +v0x2954ed0_0 .net "A", 0 0, L_0x296ba70; 1 drivers +v0x2954f90_0 .net "AandB", 0 0, L_0x296c3b0; 1 drivers +v0x2955030_0 .net "AddSubSLTSum", 0 0, L_0x296c2c0; 1 drivers +v0x29550d0_0 .net "AxorB", 0 0, L_0x296c1d0; 1 drivers +v0x2955150_0 .net "B", 0 0, L_0x296cb00; 1 drivers +v0x2955200_0 .net "BornB", 0 0, L_0x296bc20; 1 drivers +v0x29552c0_0 .net "CINandAxorB", 0 0, L_0x296c520; 1 drivers +v0x2955340_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x29553c0_0 .net *"_s3", 0 0, L_0x296bf50; 1 drivers +v0x2955440_0 .net *"_s5", 0 0, L_0x296c130; 1 drivers +v0x29554e0_0 .net "carryin", 0 0, L_0x296cc30; 1 drivers +v0x2955580_0 .net "carryout", 0 0, L_0x296c610; 1 drivers +v0x2955620_0 .net "nB", 0 0, L_0x296a2e0; 1 drivers +v0x29556d0_0 .net "nCmd2", 0 0, L_0x296be90; 1 drivers +v0x29557d0_0 .net "subtract", 0 0, L_0x296bff0; 1 drivers +L_0x296bdf0 .part v0x2960210_0, 0, 1; +L_0x296bf50 .part v0x2960210_0, 2, 1; +L_0x296c130 .part v0x2960210_0, 0, 1; +S_0x2954930 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x2954840; + .timescale -9 -12; +L_0x296b550/d .functor NOT 1, L_0x296bdf0, C4<0>, C4<0>, C4<0>; +L_0x296b550 .delay (10000,10000,10000) L_0x296b550/d; +L_0x296b610/d .functor AND 1, L_0x296cb00, L_0x296b550, C4<1>, C4<1>; +L_0x296b610 .delay (20000,20000,20000) L_0x296b610/d; +L_0x296bb10/d .functor AND 1, L_0x296a2e0, L_0x296bdf0, C4<1>, C4<1>; +L_0x296bb10 .delay (20000,20000,20000) L_0x296bb10/d; +L_0x296bc20/d .functor OR 1, L_0x296b610, L_0x296bb10, C4<0>, C4<0>; +L_0x296bc20 .delay (20000,20000,20000) L_0x296bc20/d; +v0x2954a20_0 .net "S", 0 0, L_0x296bdf0; 1 drivers +v0x2954ac0_0 .alias "in0", 0 0, v0x2955150_0; +v0x2954b60_0 .alias "in1", 0 0, v0x2955620_0; +v0x2954c00_0 .net "nS", 0 0, L_0x296b550; 1 drivers +v0x2954cb0_0 .net "out0", 0 0, L_0x296b610; 1 drivers +v0x2954d50_0 .net "out1", 0 0, L_0x296bb10; 1 drivers +v0x2954e30_0 .alias "outfinal", 0 0, v0x2955200_0; +S_0x2953530 .scope generate, "addbits[10]" "addbits[10]" 3 283, 3 283, S_0x293c2e0; + .timescale -9 -12; +P_0x2952f48 .param/l "i" 3 283, +C4<01010>; +S_0x29536a0 .scope module, "attempt" "MiddleAddSubSLT" 3 285, 3 189, S_0x2953530; + .timescale -9 -12; +L_0x296c950/d .functor NOT 1, L_0x296e040, C4<0>, C4<0>, C4<0>; +L_0x296c950 .delay (10000,10000,10000) L_0x296c950/d; +L_0x296d3a0/d .functor NOT 1, L_0x296d460, C4<0>, C4<0>, C4<0>; +L_0x296d3a0 .delay (10000,10000,10000) L_0x296d3a0/d; +L_0x296d500/d .functor AND 1, L_0x296d640, L_0x296d3a0, C4<1>, C4<1>; +L_0x296d500 .delay (20000,20000,20000) L_0x296d500/d; +L_0x296d6e0/d .functor XOR 1, L_0x296cdc0, L_0x296d130, C4<0>, C4<0>; +L_0x296d6e0 .delay (40000,40000,40000) L_0x296d6e0/d; +L_0x296d7d0/d .functor XOR 1, L_0x296d6e0, L_0x296e170, C4<0>, C4<0>; +L_0x296d7d0 .delay (40000,40000,40000) L_0x296d7d0/d; +L_0x296d8c0/d .functor AND 1, L_0x296cdc0, L_0x296d130, C4<1>, C4<1>; +L_0x296d8c0 .delay (20000,20000,20000) L_0x296d8c0/d; +L_0x296da30/d .functor AND 1, L_0x296d6e0, L_0x296e170, C4<1>, C4<1>; +L_0x296da30 .delay (20000,20000,20000) L_0x296da30/d; +L_0x296db20/d .functor OR 1, L_0x296d8c0, L_0x296da30, C4<0>, C4<0>; +L_0x296db20 .delay (20000,20000,20000) L_0x296db20/d; +v0x2953d30_0 .net "A", 0 0, L_0x296cdc0; 1 drivers +v0x2953df0_0 .net "AandB", 0 0, L_0x296d8c0; 1 drivers +v0x2953e90_0 .net "AddSubSLTSum", 0 0, L_0x296d7d0; 1 drivers +v0x2953f30_0 .net "AxorB", 0 0, L_0x296d6e0; 1 drivers +v0x2953fb0_0 .net "B", 0 0, L_0x296e040; 1 drivers +v0x2954060_0 .net "BornB", 0 0, L_0x296d130; 1 drivers +v0x2954120_0 .net "CINandAxorB", 0 0, L_0x296da30; 1 drivers +v0x29541a0_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x2954220_0 .net *"_s3", 0 0, L_0x296d460; 1 drivers +v0x29542a0_0 .net *"_s5", 0 0, L_0x296d640; 1 drivers +v0x2954340_0 .net "carryin", 0 0, L_0x296e170; 1 drivers +v0x29543e0_0 .net "carryout", 0 0, L_0x296db20; 1 drivers +v0x2954480_0 .net "nB", 0 0, L_0x296c950; 1 drivers +v0x2954530_0 .net "nCmd2", 0 0, L_0x296d3a0; 1 drivers +v0x2954630_0 .net "subtract", 0 0, L_0x296d500; 1 drivers +L_0x296d300 .part v0x2960210_0, 0, 1; +L_0x296d460 .part v0x2960210_0, 2, 1; +L_0x296d640 .part v0x2960210_0, 0, 1; +S_0x2953790 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x29536a0; + .timescale -9 -12; +L_0x296ce90/d .functor NOT 1, L_0x296d300, C4<0>, C4<0>, C4<0>; +L_0x296ce90 .delay (10000,10000,10000) L_0x296ce90/d; +L_0x296cf30/d .functor AND 1, L_0x296e040, L_0x296ce90, C4<1>, C4<1>; +L_0x296cf30 .delay (20000,20000,20000) L_0x296cf30/d; +L_0x296d020/d .functor AND 1, L_0x296c950, L_0x296d300, C4<1>, C4<1>; +L_0x296d020 .delay (20000,20000,20000) L_0x296d020/d; +L_0x296d130/d .functor OR 1, L_0x296cf30, L_0x296d020, C4<0>, C4<0>; +L_0x296d130 .delay (20000,20000,20000) L_0x296d130/d; +v0x2953880_0 .net "S", 0 0, L_0x296d300; 1 drivers +v0x2953920_0 .alias "in0", 0 0, v0x2953fb0_0; +v0x29539c0_0 .alias "in1", 0 0, v0x2954480_0; +v0x2953a60_0 .net "nS", 0 0, L_0x296ce90; 1 drivers +v0x2953b10_0 .net "out0", 0 0, L_0x296cf30; 1 drivers +v0x2953bb0_0 .net "out1", 0 0, L_0x296d020; 1 drivers +v0x2953c90_0 .alias "outfinal", 0 0, v0x2954060_0; +S_0x2952390 .scope generate, "addbits[11]" "addbits[11]" 3 283, 3 283, S_0x293c2e0; + .timescale -9 -12; +P_0x2951cf8 .param/l "i" 3 283, +C4<01011>; +S_0x2952500 .scope module, "attempt" "MiddleAddSubSLT" 3 285, 3 189, S_0x2952390; + .timescale -9 -12; +L_0x296de60/d .functor NOT 1, L_0x296e2b0, C4<0>, C4<0>, C4<0>; +L_0x296de60 .delay (10000,10000,10000) L_0x296de60/d; +L_0x296e8b0/d .functor NOT 1, L_0x296e970, C4<0>, C4<0>, C4<0>; +L_0x296e8b0 .delay (10000,10000,10000) L_0x296e8b0/d; +L_0x296ea10/d .functor AND 1, L_0x296eb50, L_0x296e8b0, C4<1>, C4<1>; +L_0x296ea10 .delay (20000,20000,20000) L_0x296ea10/d; +L_0x296ebf0/d .functor XOR 1, L_0x29648a0, L_0x296e640, C4<0>, C4<0>; +L_0x296ebf0 .delay (40000,40000,40000) L_0x296ebf0/d; +L_0x296ece0/d .functor XOR 1, L_0x296ebf0, L_0x296f370, C4<0>, C4<0>; +L_0x296ece0 .delay (40000,40000,40000) L_0x296ece0/d; +L_0x296edd0/d .functor AND 1, L_0x29648a0, L_0x296e640, C4<1>, C4<1>; +L_0x296edd0 .delay (20000,20000,20000) L_0x296edd0/d; +L_0x296ef40/d .functor AND 1, L_0x296ebf0, L_0x296f370, C4<1>, C4<1>; +L_0x296ef40 .delay (20000,20000,20000) L_0x296ef40/d; +L_0x296f030/d .functor OR 1, L_0x296edd0, L_0x296ef40, C4<0>, C4<0>; +L_0x296f030 .delay (20000,20000,20000) L_0x296f030/d; +v0x2952b90_0 .net "A", 0 0, L_0x29648a0; 1 drivers +v0x2952c50_0 .net "AandB", 0 0, L_0x296edd0; 1 drivers +v0x2952cf0_0 .net "AddSubSLTSum", 0 0, L_0x296ece0; 1 drivers +v0x2952d90_0 .net "AxorB", 0 0, L_0x296ebf0; 1 drivers +v0x2952e10_0 .net "B", 0 0, L_0x296e2b0; 1 drivers +v0x2952ec0_0 .net "BornB", 0 0, L_0x296e640; 1 drivers +v0x2952f80_0 .net "CINandAxorB", 0 0, L_0x296ef40; 1 drivers +v0x2953000_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x2953080_0 .net *"_s3", 0 0, L_0x296e970; 1 drivers +v0x2953100_0 .net *"_s5", 0 0, L_0x296eb50; 1 drivers +v0x29531a0_0 .net "carryin", 0 0, L_0x296f370; 1 drivers +v0x2953240_0 .net "carryout", 0 0, L_0x296f030; 1 drivers +v0x29532e0_0 .net "nB", 0 0, L_0x296de60; 1 drivers +v0x2953390_0 .net "nCmd2", 0 0, L_0x296e8b0; 1 drivers +v0x2953490_0 .net "subtract", 0 0, L_0x296ea10; 1 drivers +L_0x296e810 .part v0x2960210_0, 0, 1; +L_0x296e970 .part v0x2960210_0, 2, 1; +L_0x296eb50 .part v0x2960210_0, 0, 1; +S_0x29525f0 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x2952500; + .timescale -9 -12; +L_0x296dfc0/d .functor NOT 1, L_0x296e810, C4<0>, C4<0>, C4<0>; +L_0x296dfc0 .delay (10000,10000,10000) L_0x296dfc0/d; +L_0x296e440/d .functor AND 1, L_0x296e2b0, L_0x296dfc0, C4<1>, C4<1>; +L_0x296e440 .delay (20000,20000,20000) L_0x296e440/d; +L_0x296e530/d .functor AND 1, L_0x296de60, L_0x296e810, C4<1>, C4<1>; +L_0x296e530 .delay (20000,20000,20000) L_0x296e530/d; +L_0x296e640/d .functor OR 1, L_0x296e440, L_0x296e530, C4<0>, C4<0>; +L_0x296e640 .delay (20000,20000,20000) L_0x296e640/d; +v0x29526e0_0 .net "S", 0 0, L_0x296e810; 1 drivers +v0x2952780_0 .alias "in0", 0 0, v0x2952e10_0; +v0x2952820_0 .alias "in1", 0 0, v0x29532e0_0; +v0x29528c0_0 .net "nS", 0 0, L_0x296dfc0; 1 drivers +v0x2952970_0 .net "out0", 0 0, L_0x296e440; 1 drivers +v0x2952a10_0 .net "out1", 0 0, L_0x296e530; 1 drivers +v0x2952af0_0 .alias "outfinal", 0 0, v0x2952ec0_0; +S_0x2951180 .scope generate, "addbits[12]" "addbits[12]" 3 283, 3 283, S_0x293c2e0; + .timescale -9 -12; +P_0x2920138 .param/l "i" 3 283, +C4<01100>; +S_0x29512b0 .scope module, "attempt" "MiddleAddSubSLT" 3 285, 3 189, S_0x2951180; + .timescale -9 -12; +L_0x296f410/d .functor NOT 1, L_0x2970bb0, C4<0>, C4<0>, C4<0>; +L_0x296f410 .delay (10000,10000,10000) L_0x296f410/d; +L_0x296feb0/d .functor NOT 1, L_0x296ff70, C4<0>, C4<0>, C4<0>; +L_0x296feb0 .delay (10000,10000,10000) L_0x296feb0/d; +L_0x2970010/d .functor AND 1, L_0x2970150, L_0x296feb0, C4<1>, C4<1>; +L_0x2970010 .delay (20000,20000,20000) L_0x2970010/d; +L_0x29701f0/d .functor XOR 1, L_0x296f870, L_0x296fc40, C4<0>, C4<0>; +L_0x29701f0 .delay (40000,40000,40000) L_0x29701f0/d; +L_0x29702e0/d .functor XOR 1, L_0x29701f0, L_0x2970c50, C4<0>, C4<0>; +L_0x29702e0 .delay (40000,40000,40000) L_0x29702e0/d; +L_0x29703d0/d .functor AND 1, L_0x296f870, L_0x296fc40, C4<1>, C4<1>; +L_0x29703d0 .delay (20000,20000,20000) L_0x29703d0/d; +L_0x2970540/d .functor AND 1, L_0x29701f0, L_0x2970c50, C4<1>, C4<1>; +L_0x2970540 .delay (20000,20000,20000) L_0x2970540/d; +L_0x2970630/d .functor OR 1, L_0x29703d0, L_0x2970540, C4<0>, C4<0>; +L_0x2970630 .delay (20000,20000,20000) L_0x2970630/d; +v0x2951940_0 .net "A", 0 0, L_0x296f870; 1 drivers +v0x2951a00_0 .net "AandB", 0 0, L_0x29703d0; 1 drivers +v0x2951aa0_0 .net "AddSubSLTSum", 0 0, L_0x29702e0; 1 drivers +v0x2951b40_0 .net "AxorB", 0 0, L_0x29701f0; 1 drivers +v0x2951bc0_0 .net "B", 0 0, L_0x2970bb0; 1 drivers +v0x2951c70_0 .net "BornB", 0 0, L_0x296fc40; 1 drivers +v0x2951d30_0 .net "CINandAxorB", 0 0, L_0x2970540; 1 drivers +v0x2951db0_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x2951e80_0 .net *"_s3", 0 0, L_0x296ff70; 1 drivers +v0x2951f00_0 .net *"_s5", 0 0, L_0x2970150; 1 drivers +v0x2952000_0 .net "carryin", 0 0, L_0x2970c50; 1 drivers +v0x29520a0_0 .net "carryout", 0 0, L_0x2970630; 1 drivers +v0x2952140_0 .net "nB", 0 0, L_0x296f410; 1 drivers +v0x29521f0_0 .net "nCmd2", 0 0, L_0x296feb0; 1 drivers +v0x29522f0_0 .net "subtract", 0 0, L_0x2970010; 1 drivers +L_0x296fe10 .part v0x2960210_0, 0, 1; +L_0x296ff70 .part v0x2960210_0, 2, 1; +L_0x2970150 .part v0x2960210_0, 0, 1; +S_0x29513a0 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x29512b0; + .timescale -9 -12; +L_0x296f9a0/d .functor NOT 1, L_0x296fe10, C4<0>, C4<0>, C4<0>; +L_0x296f9a0 .delay (10000,10000,10000) L_0x296f9a0/d; +L_0x296fa40/d .functor AND 1, L_0x2970bb0, L_0x296f9a0, C4<1>, C4<1>; +L_0x296fa40 .delay (20000,20000,20000) L_0x296fa40/d; +L_0x296fb30/d .functor AND 1, L_0x296f410, L_0x296fe10, C4<1>, C4<1>; +L_0x296fb30 .delay (20000,20000,20000) L_0x296fb30/d; +L_0x296fc40/d .functor OR 1, L_0x296fa40, L_0x296fb30, C4<0>, C4<0>; +L_0x296fc40 .delay (20000,20000,20000) L_0x296fc40/d; +v0x2951490_0 .net "S", 0 0, L_0x296fe10; 1 drivers +v0x2951530_0 .alias "in0", 0 0, v0x2951bc0_0; +v0x29515d0_0 .alias "in1", 0 0, v0x2952140_0; +v0x2951670_0 .net "nS", 0 0, L_0x296f9a0; 1 drivers +v0x2951720_0 .net "out0", 0 0, L_0x296fa40; 1 drivers +v0x29517c0_0 .net "out1", 0 0, L_0x296fb30; 1 drivers +v0x29518a0_0 .alias "outfinal", 0 0, v0x2951c70_0; +S_0x2950030 .scope generate, "addbits[13]" "addbits[13]" 3 283, 3 283, S_0x293c2e0; + .timescale -9 -12; +P_0x294fa48 .param/l "i" 3 283, +C4<01101>; +S_0x29501a0 .scope module, "attempt" "MiddleAddSubSLT" 3 285, 3 189, S_0x2950030; + .timescale -9 -12; +L_0x2970970/d .functor NOT 1, L_0x2970e80, C4<0>, C4<0>, C4<0>; +L_0x2970970 .delay (10000,10000,10000) L_0x2970970/d; +L_0x2971370/d .functor NOT 1, L_0x2971430, C4<0>, C4<0>, C4<0>; +L_0x2971370 .delay (10000,10000,10000) L_0x2971370/d; +L_0x29714d0/d .functor AND 1, L_0x2971610, L_0x2971370, C4<1>, C4<1>; +L_0x29714d0 .delay (20000,20000,20000) L_0x29714d0/d; +L_0x29716b0/d .functor XOR 1, L_0x2970de0, L_0x2971100, C4<0>, C4<0>; +L_0x29716b0 .delay (40000,40000,40000) L_0x29716b0/d; +L_0x29717a0/d .functor XOR 1, L_0x29716b0, L_0x2972250, C4<0>, C4<0>; +L_0x29717a0 .delay (40000,40000,40000) L_0x29717a0/d; +L_0x2971890/d .functor AND 1, L_0x2970de0, L_0x2971100, C4<1>, C4<1>; +L_0x2971890 .delay (20000,20000,20000) L_0x2971890/d; +L_0x2971a00/d .functor AND 1, L_0x29716b0, L_0x2972250, C4<1>, C4<1>; +L_0x2971a00 .delay (20000,20000,20000) L_0x2971a00/d; +L_0x2971af0/d .functor OR 1, L_0x2971890, L_0x2971a00, C4<0>, C4<0>; +L_0x2971af0 .delay (20000,20000,20000) L_0x2971af0/d; +v0x2950830_0 .net "A", 0 0, L_0x2970de0; 1 drivers +v0x29508f0_0 .net "AandB", 0 0, L_0x2971890; 1 drivers +v0x2950990_0 .net "AddSubSLTSum", 0 0, L_0x29717a0; 1 drivers +v0x2950a30_0 .net "AxorB", 0 0, L_0x29716b0; 1 drivers +v0x2950ab0_0 .net "B", 0 0, L_0x2970e80; 1 drivers +v0x2950b60_0 .net "BornB", 0 0, L_0x2971100; 1 drivers +v0x2950c20_0 .net "CINandAxorB", 0 0, L_0x2971a00; 1 drivers +v0x2950ca0_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x2950d20_0 .net *"_s3", 0 0, L_0x2971430; 1 drivers +v0x2950da0_0 .net *"_s5", 0 0, L_0x2971610; 1 drivers +v0x2950e40_0 .net "carryin", 0 0, L_0x2972250; 1 drivers +v0x2950ee0_0 .net "carryout", 0 0, L_0x2971af0; 1 drivers +v0x2950f80_0 .net "nB", 0 0, L_0x2970970; 1 drivers +v0x2951000_0 .net "nCmd2", 0 0, L_0x2971370; 1 drivers +v0x2951100_0 .net "subtract", 0 0, L_0x29714d0; 1 drivers +L_0x29712d0 .part v0x2960210_0, 0, 1; +L_0x2971430 .part v0x2960210_0, 2, 1; +L_0x2971610 .part v0x2960210_0, 0, 1; +S_0x2950290 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x29501a0; + .timescale -9 -12; +L_0x2970ad0/d .functor NOT 1, L_0x29712d0, C4<0>, C4<0>, C4<0>; +L_0x2970ad0 .delay (10000,10000,10000) L_0x2970ad0/d; +L_0x2970b50/d .functor AND 1, L_0x2970e80, L_0x2970ad0, C4<1>, C4<1>; +L_0x2970b50 .delay (20000,20000,20000) L_0x2970b50/d; +L_0x2970ff0/d .functor AND 1, L_0x2970970, L_0x29712d0, C4<1>, C4<1>; +L_0x2970ff0 .delay (20000,20000,20000) L_0x2970ff0/d; +L_0x2971100/d .functor OR 1, L_0x2970b50, L_0x2970ff0, C4<0>, C4<0>; +L_0x2971100 .delay (20000,20000,20000) L_0x2971100/d; +v0x2950380_0 .net "S", 0 0, L_0x29712d0; 1 drivers +v0x2950420_0 .alias "in0", 0 0, v0x2950ab0_0; +v0x29504c0_0 .alias "in1", 0 0, v0x2950f80_0; +v0x2950560_0 .net "nS", 0 0, L_0x2970ad0; 1 drivers +v0x2950610_0 .net "out0", 0 0, L_0x2970b50; 1 drivers +v0x29506b0_0 .net "out1", 0 0, L_0x2970ff0; 1 drivers +v0x2950790_0 .alias "outfinal", 0 0, v0x2950b60_0; +S_0x294ee90 .scope generate, "addbits[14]" "addbits[14]" 3 283, 3 283, S_0x293c2e0; + .timescale -9 -12; +P_0x294e8a8 .param/l "i" 3 283, +C4<01110>; +S_0x294f000 .scope module, "attempt" "MiddleAddSubSLT" 3 285, 3 189, S_0x294ee90; + .timescale -9 -12; +L_0x2960540/d .functor NOT 1, L_0x2972480, C4<0>, C4<0>, C4<0>; +L_0x2960540 .delay (10000,10000,10000) L_0x2960540/d; +L_0x2972890/d .functor NOT 1, L_0x2972930, C4<0>, C4<0>, C4<0>; +L_0x2972890 .delay (10000,10000,10000) L_0x2972890/d; +L_0x29729d0/d .functor AND 1, L_0x2972b10, L_0x2972890, C4<1>, C4<1>; +L_0x29729d0 .delay (20000,20000,20000) L_0x29729d0/d; +L_0x2972bb0/d .functor XOR 1, L_0x29723e0, L_0x2972660, C4<0>, C4<0>; +L_0x2972bb0 .delay (40000,40000,40000) L_0x2972bb0/d; +L_0x2972ca0/d .functor XOR 1, L_0x2972bb0, L_0x2973640, C4<0>, C4<0>; +L_0x2972ca0 .delay (40000,40000,40000) L_0x2972ca0/d; +L_0x2972d90/d .functor AND 1, L_0x29723e0, L_0x2972660, C4<1>, C4<1>; +L_0x2972d90 .delay (20000,20000,20000) L_0x2972d90/d; +L_0x2972f00/d .functor AND 1, L_0x2972bb0, L_0x2973640, C4<1>, C4<1>; +L_0x2972f00 .delay (20000,20000,20000) L_0x2972f00/d; +L_0x2972ff0/d .functor OR 1, L_0x2972d90, L_0x2972f00, C4<0>, C4<0>; +L_0x2972ff0 .delay (20000,20000,20000) L_0x2972ff0/d; +v0x294f690_0 .net "A", 0 0, L_0x29723e0; 1 drivers +v0x294f750_0 .net "AandB", 0 0, L_0x2972d90; 1 drivers +v0x294f7f0_0 .net "AddSubSLTSum", 0 0, L_0x2972ca0; 1 drivers +v0x294f890_0 .net "AxorB", 0 0, L_0x2972bb0; 1 drivers +v0x294f910_0 .net "B", 0 0, L_0x2972480; 1 drivers +v0x294f9c0_0 .net "BornB", 0 0, L_0x2972660; 1 drivers +v0x294fa80_0 .net "CINandAxorB", 0 0, L_0x2972f00; 1 drivers +v0x294fb00_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x294fb80_0 .net *"_s3", 0 0, L_0x2972930; 1 drivers +v0x294fc00_0 .net *"_s5", 0 0, L_0x2972b10; 1 drivers +v0x294fca0_0 .net "carryin", 0 0, L_0x2973640; 1 drivers +v0x294fd40_0 .net "carryout", 0 0, L_0x2972ff0; 1 drivers +v0x294fde0_0 .net "nB", 0 0, L_0x2960540; 1 drivers +v0x294fe90_0 .net "nCmd2", 0 0, L_0x2972890; 1 drivers +v0x294ff90_0 .net "subtract", 0 0, L_0x29729d0; 1 drivers +L_0x29727f0 .part v0x2960210_0, 0, 1; +L_0x2972930 .part v0x2960210_0, 2, 1; +L_0x2972b10 .part v0x2960210_0, 0, 1; +S_0x294f0f0 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x294f000; + .timescale -9 -12; +L_0x2971fc0/d .functor NOT 1, L_0x29727f0, C4<0>, C4<0>, C4<0>; +L_0x2971fc0 .delay (10000,10000,10000) L_0x2971fc0/d; +L_0x2972080/d .functor AND 1, L_0x2972480, L_0x2971fc0, C4<1>, C4<1>; +L_0x2972080 .delay (20000,20000,20000) L_0x2972080/d; +L_0x2972570/d .functor AND 1, L_0x2960540, L_0x29727f0, C4<1>, C4<1>; +L_0x2972570 .delay (20000,20000,20000) L_0x2972570/d; +L_0x2972660/d .functor OR 1, L_0x2972080, L_0x2972570, C4<0>, C4<0>; +L_0x2972660 .delay (20000,20000,20000) L_0x2972660/d; +v0x294f1e0_0 .net "S", 0 0, L_0x29727f0; 1 drivers +v0x294f280_0 .alias "in0", 0 0, v0x294f910_0; +v0x294f320_0 .alias "in1", 0 0, v0x294fde0_0; +v0x294f3c0_0 .net "nS", 0 0, L_0x2971fc0; 1 drivers +v0x294f470_0 .net "out0", 0 0, L_0x2972080; 1 drivers +v0x294f510_0 .net "out1", 0 0, L_0x2972570; 1 drivers +v0x294f5f0_0 .alias "outfinal", 0 0, v0x294f9c0_0; +S_0x294dcf0 .scope generate, "addbits[15]" "addbits[15]" 3 283, 3 283, S_0x293c2e0; + .timescale -9 -12; +P_0x294d708 .param/l "i" 3 283, +C4<01111>; +S_0x294de60 .scope module, "attempt" "MiddleAddSubSLT" 3 285, 3 189, S_0x294dcf0; + .timescale -9 -12; +L_0x2973310/d .functor NOT 1, L_0x2973870, C4<0>, C4<0>, C4<0>; +L_0x2973310 .delay (10000,10000,10000) L_0x2973310/d; +L_0x2973d00/d .functor NOT 1, L_0x2973da0, C4<0>, C4<0>, C4<0>; +L_0x2973d00 .delay (10000,10000,10000) L_0x2973d00/d; +L_0x2973e40/d .functor AND 1, L_0x2973f80, L_0x2973d00, C4<1>, C4<1>; +L_0x2973e40 .delay (20000,20000,20000) L_0x2973e40/d; +L_0x2974020/d .functor XOR 1, L_0x29737d0, L_0x2973ad0, C4<0>, C4<0>; +L_0x2974020 .delay (40000,40000,40000) L_0x2974020/d; +L_0x2974110/d .functor XOR 1, L_0x2974020, L_0x2974ae0, C4<0>, C4<0>; +L_0x2974110 .delay (40000,40000,40000) L_0x2974110/d; +L_0x2974200/d .functor AND 1, L_0x29737d0, L_0x2973ad0, C4<1>, C4<1>; +L_0x2974200 .delay (20000,20000,20000) L_0x2974200/d; +L_0x2974370/d .functor AND 1, L_0x2974020, L_0x2974ae0, C4<1>, C4<1>; +L_0x2974370 .delay (20000,20000,20000) L_0x2974370/d; +L_0x2974460/d .functor OR 1, L_0x2974200, L_0x2974370, C4<0>, C4<0>; +L_0x2974460 .delay (20000,20000,20000) L_0x2974460/d; +v0x294e4f0_0 .net "A", 0 0, L_0x29737d0; 1 drivers +v0x294e5b0_0 .net "AandB", 0 0, L_0x2974200; 1 drivers +v0x294e650_0 .net "AddSubSLTSum", 0 0, L_0x2974110; 1 drivers +v0x294e6f0_0 .net "AxorB", 0 0, L_0x2974020; 1 drivers +v0x294e770_0 .net "B", 0 0, L_0x2973870; 1 drivers +v0x294e820_0 .net "BornB", 0 0, L_0x2973ad0; 1 drivers +v0x294e8e0_0 .net "CINandAxorB", 0 0, L_0x2974370; 1 drivers +v0x294e960_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x294e9e0_0 .net *"_s3", 0 0, L_0x2973da0; 1 drivers +v0x294ea60_0 .net *"_s5", 0 0, L_0x2973f80; 1 drivers +v0x294eb00_0 .net "carryin", 0 0, L_0x2974ae0; 1 drivers +v0x294eba0_0 .net "carryout", 0 0, L_0x2974460; 1 drivers +v0x294ec40_0 .net "nB", 0 0, L_0x2973310; 1 drivers +v0x294ecf0_0 .net "nCmd2", 0 0, L_0x2973d00; 1 drivers +v0x294edf0_0 .net "subtract", 0 0, L_0x2973e40; 1 drivers +L_0x2973c60 .part v0x2960210_0, 0, 1; +L_0x2973da0 .part v0x2960210_0, 2, 1; +L_0x2973f80 .part v0x2960210_0, 0, 1; +S_0x294df50 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x294de60; + .timescale -9 -12; +L_0x2973420/d .functor NOT 1, L_0x2973c60, C4<0>, C4<0>, C4<0>; +L_0x2973420 .delay (10000,10000,10000) L_0x2973420/d; +L_0x29734e0/d .functor AND 1, L_0x2973870, L_0x2973420, C4<1>, C4<1>; +L_0x29734e0 .delay (20000,20000,20000) L_0x29734e0/d; +L_0x29739e0/d .functor AND 1, L_0x2973310, L_0x2973c60, C4<1>, C4<1>; +L_0x29739e0 .delay (20000,20000,20000) L_0x29739e0/d; +L_0x2973ad0/d .functor OR 1, L_0x29734e0, L_0x29739e0, C4<0>, C4<0>; +L_0x2973ad0 .delay (20000,20000,20000) L_0x2973ad0/d; +v0x294e040_0 .net "S", 0 0, L_0x2973c60; 1 drivers +v0x294e0e0_0 .alias "in0", 0 0, v0x294e770_0; +v0x294e180_0 .alias "in1", 0 0, v0x294ec40_0; +v0x294e220_0 .net "nS", 0 0, L_0x2973420; 1 drivers +v0x294e2d0_0 .net "out0", 0 0, L_0x29734e0; 1 drivers +v0x294e370_0 .net "out1", 0 0, L_0x29739e0; 1 drivers +v0x294e450_0 .alias "outfinal", 0 0, v0x294e820_0; +S_0x294cb50 .scope generate, "addbits[16]" "addbits[16]" 3 283, 3 283, S_0x293c2e0; + .timescale -9 -12; +P_0x294c568 .param/l "i" 3 283, +C4<010000>; +S_0x294ccc0 .scope module, "attempt" "MiddleAddSubSLT" 3 285, 3 189, S_0x294cb50; + .timescale -9 -12; +L_0x2973910/d .functor NOT 1, L_0x2974d10, C4<0>, C4<0>, C4<0>; +L_0x2973910 .delay (10000,10000,10000) L_0x2973910/d; +L_0x2975180/d .functor NOT 1, L_0x2975220, C4<0>, C4<0>, C4<0>; +L_0x2975180 .delay (10000,10000,10000) L_0x2975180/d; +L_0x29752c0/d .functor AND 1, L_0x2975400, L_0x2975180, C4<1>, C4<1>; +L_0x29752c0 .delay (20000,20000,20000) L_0x29752c0/d; +L_0x29754a0/d .functor XOR 1, L_0x2974c70, L_0x2974f50, C4<0>, C4<0>; +L_0x29754a0 .delay (40000,40000,40000) L_0x29754a0/d; +L_0x2975590/d .functor XOR 1, L_0x29754a0, L_0x2975f00, C4<0>, C4<0>; +L_0x2975590 .delay (40000,40000,40000) L_0x2975590/d; +L_0x2975680/d .functor AND 1, L_0x2974c70, L_0x2974f50, C4<1>, C4<1>; +L_0x2975680 .delay (20000,20000,20000) L_0x2975680/d; +L_0x29757f0/d .functor AND 1, L_0x29754a0, L_0x2975f00, C4<1>, C4<1>; +L_0x29757f0 .delay (20000,20000,20000) L_0x29757f0/d; +L_0x29758e0/d .functor OR 1, L_0x2975680, L_0x29757f0, C4<0>, C4<0>; +L_0x29758e0 .delay (20000,20000,20000) L_0x29758e0/d; +v0x294d350_0 .net "A", 0 0, L_0x2974c70; 1 drivers +v0x294d410_0 .net "AandB", 0 0, L_0x2975680; 1 drivers +v0x294d4b0_0 .net "AddSubSLTSum", 0 0, L_0x2975590; 1 drivers +v0x294d550_0 .net "AxorB", 0 0, L_0x29754a0; 1 drivers +v0x294d5d0_0 .net "B", 0 0, L_0x2974d10; 1 drivers +v0x294d680_0 .net "BornB", 0 0, L_0x2974f50; 1 drivers +v0x294d740_0 .net "CINandAxorB", 0 0, L_0x29757f0; 1 drivers +v0x294d7c0_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x294d840_0 .net *"_s3", 0 0, L_0x2975220; 1 drivers +v0x294d8c0_0 .net *"_s5", 0 0, L_0x2975400; 1 drivers +v0x294d960_0 .net "carryin", 0 0, L_0x2975f00; 1 drivers +v0x294da00_0 .net "carryout", 0 0, L_0x29758e0; 1 drivers +v0x294daa0_0 .net "nB", 0 0, L_0x2973910; 1 drivers +v0x294db50_0 .net "nCmd2", 0 0, L_0x2975180; 1 drivers +v0x294dc50_0 .net "subtract", 0 0, L_0x29752c0; 1 drivers +L_0x29750e0 .part v0x2960210_0, 0, 1; +L_0x2975220 .part v0x2960210_0, 2, 1; +L_0x2975400 .part v0x2960210_0, 0, 1; +S_0x294cdb0 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x294ccc0; + .timescale -9 -12; +L_0x2974860/d .functor NOT 1, L_0x29750e0, C4<0>, C4<0>, C4<0>; +L_0x2974860 .delay (10000,10000,10000) L_0x2974860/d; +L_0x2974920/d .functor AND 1, L_0x2974d10, L_0x2974860, C4<1>, C4<1>; +L_0x2974920 .delay (20000,20000,20000) L_0x2974920/d; +L_0x2974e60/d .functor AND 1, L_0x2973910, L_0x29750e0, C4<1>, C4<1>; +L_0x2974e60 .delay (20000,20000,20000) L_0x2974e60/d; +L_0x2974f50/d .functor OR 1, L_0x2974920, L_0x2974e60, C4<0>, C4<0>; +L_0x2974f50 .delay (20000,20000,20000) L_0x2974f50/d; +v0x294cea0_0 .net "S", 0 0, L_0x29750e0; 1 drivers +v0x294cf40_0 .alias "in0", 0 0, v0x294d5d0_0; +v0x294cfe0_0 .alias "in1", 0 0, v0x294daa0_0; +v0x294d080_0 .net "nS", 0 0, L_0x2974860; 1 drivers +v0x294d130_0 .net "out0", 0 0, L_0x2974920; 1 drivers +v0x294d1d0_0 .net "out1", 0 0, L_0x2974e60; 1 drivers +v0x294d2b0_0 .alias "outfinal", 0 0, v0x294d680_0; +S_0x294b9b0 .scope generate, "addbits[17]" "addbits[17]" 3 283, 3 283, S_0x293c2e0; + .timescale -9 -12; +P_0x294b3c8 .param/l "i" 3 283, +C4<010001>; +S_0x294bb20 .scope module, "attempt" "MiddleAddSubSLT" 3 285, 3 189, S_0x294b9b0; + .timescale -9 -12; +L_0x296b770/d .functor NOT 1, L_0x2976540, C4<0>, C4<0>, C4<0>; +L_0x296b770 .delay (10000,10000,10000) L_0x296b770/d; +L_0x2976840/d .functor NOT 1, L_0x29768e0, C4<0>, C4<0>, C4<0>; +L_0x2976840 .delay (10000,10000,10000) L_0x2976840/d; +L_0x2976980/d .functor AND 1, L_0x2976ac0, L_0x2976840, C4<1>, C4<1>; +L_0x2976980 .delay (20000,20000,20000) L_0x2976980/d; +L_0x2976b60/d .functor XOR 1, L_0x29764a0, L_0x2975e20, C4<0>, C4<0>; +L_0x2976b60 .delay (40000,40000,40000) L_0x2976b60/d; +L_0x2976c50/d .functor XOR 1, L_0x2976b60, L_0x29775f0, C4<0>, C4<0>; +L_0x2976c50 .delay (40000,40000,40000) L_0x2976c50/d; +L_0x2976d40/d .functor AND 1, L_0x29764a0, L_0x2975e20, C4<1>, C4<1>; +L_0x2976d40 .delay (20000,20000,20000) L_0x2976d40/d; +L_0x2976eb0/d .functor AND 1, L_0x2976b60, L_0x29775f0, C4<1>, C4<1>; +L_0x2976eb0 .delay (20000,20000,20000) L_0x2976eb0/d; +L_0x2976fa0/d .functor OR 1, L_0x2976d40, L_0x2976eb0, C4<0>, C4<0>; +L_0x2976fa0 .delay (20000,20000,20000) L_0x2976fa0/d; +v0x294c1b0_0 .net "A", 0 0, L_0x29764a0; 1 drivers +v0x294c270_0 .net "AandB", 0 0, L_0x2976d40; 1 drivers +v0x294c310_0 .net "AddSubSLTSum", 0 0, L_0x2976c50; 1 drivers +v0x294c3b0_0 .net "AxorB", 0 0, L_0x2976b60; 1 drivers +v0x294c430_0 .net "B", 0 0, L_0x2976540; 1 drivers +v0x294c4e0_0 .net "BornB", 0 0, L_0x2975e20; 1 drivers +v0x294c5a0_0 .net "CINandAxorB", 0 0, L_0x2976eb0; 1 drivers +v0x294c620_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x294c6a0_0 .net *"_s3", 0 0, L_0x29768e0; 1 drivers +v0x294c720_0 .net *"_s5", 0 0, L_0x2976ac0; 1 drivers +v0x294c7c0_0 .net "carryin", 0 0, L_0x29775f0; 1 drivers +v0x294c860_0 .net "carryout", 0 0, L_0x2976fa0; 1 drivers +v0x294c900_0 .net "nB", 0 0, L_0x296b770; 1 drivers +v0x294c9b0_0 .net "nCmd2", 0 0, L_0x2976840; 1 drivers +v0x294cab0_0 .net "subtract", 0 0, L_0x2976980; 1 drivers +L_0x29767a0 .part v0x2960210_0, 0, 1; +L_0x29768e0 .part v0x2960210_0, 2, 1; +L_0x2976ac0 .part v0x2960210_0, 0, 1; +S_0x294bc10 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x294bb20; + .timescale -9 -12; +L_0x296b8b0/d .functor NOT 1, L_0x29767a0, C4<0>, C4<0>, C4<0>; +L_0x296b8b0 .delay (10000,10000,10000) L_0x296b8b0/d; +L_0x2975c00/d .functor AND 1, L_0x2976540, L_0x296b8b0, C4<1>, C4<1>; +L_0x2975c00 .delay (20000,20000,20000) L_0x2975c00/d; +L_0x2975d10/d .functor AND 1, L_0x296b770, L_0x29767a0, C4<1>, C4<1>; +L_0x2975d10 .delay (20000,20000,20000) L_0x2975d10/d; +L_0x2975e20/d .functor OR 1, L_0x2975c00, L_0x2975d10, C4<0>, C4<0>; +L_0x2975e20 .delay (20000,20000,20000) L_0x2975e20/d; +v0x294bd00_0 .net "S", 0 0, L_0x29767a0; 1 drivers +v0x294bda0_0 .alias "in0", 0 0, v0x294c430_0; +v0x294be40_0 .alias "in1", 0 0, v0x294c900_0; +v0x294bee0_0 .net "nS", 0 0, L_0x296b8b0; 1 drivers +v0x294bf90_0 .net "out0", 0 0, L_0x2975c00; 1 drivers +v0x294c030_0 .net "out1", 0 0, L_0x2975d10; 1 drivers +v0x294c110_0 .alias "outfinal", 0 0, v0x294c4e0_0; +S_0x294a810 .scope generate, "addbits[18]" "addbits[18]" 3 283, 3 283, S_0x293c2e0; + .timescale -9 -12; +P_0x294a228 .param/l "i" 3 283, +C4<010010>; +S_0x294a980 .scope module, "attempt" "MiddleAddSubSLT" 3 285, 3 189, S_0x294a810; + .timescale -9 -12; +L_0x29772c0/d .functor NOT 1, L_0x2977820, C4<0>, C4<0>, C4<0>; +L_0x29772c0 .delay (10000,10000,10000) L_0x29772c0/d; +L_0x2977cb0/d .functor NOT 1, L_0x2977d50, C4<0>, C4<0>, C4<0>; +L_0x2977cb0 .delay (10000,10000,10000) L_0x2977cb0/d; +L_0x2977df0/d .functor AND 1, L_0x2977f30, L_0x2977cb0, C4<1>, C4<1>; +L_0x2977df0 .delay (20000,20000,20000) L_0x2977df0/d; +L_0x2977fd0/d .functor XOR 1, L_0x2977780, L_0x2977a80, C4<0>, C4<0>; +L_0x2977fd0 .delay (40000,40000,40000) L_0x2977fd0/d; +L_0x29780c0/d .functor XOR 1, L_0x2977fd0, L_0x2963200, C4<0>, C4<0>; +L_0x29780c0 .delay (40000,40000,40000) L_0x29780c0/d; +L_0x29781b0/d .functor AND 1, L_0x2977780, L_0x2977a80, C4<1>, C4<1>; +L_0x29781b0 .delay (20000,20000,20000) L_0x29781b0/d; +L_0x2978320/d .functor AND 1, L_0x2977fd0, L_0x2963200, C4<1>, C4<1>; +L_0x2978320 .delay (20000,20000,20000) L_0x2978320/d; +L_0x2978410/d .functor OR 1, L_0x29781b0, L_0x2978320, C4<0>, C4<0>; +L_0x2978410 .delay (20000,20000,20000) L_0x2978410/d; +v0x294b010_0 .net "A", 0 0, L_0x2977780; 1 drivers +v0x294b0d0_0 .net "AandB", 0 0, L_0x29781b0; 1 drivers +v0x294b170_0 .net "AddSubSLTSum", 0 0, L_0x29780c0; 1 drivers +v0x294b210_0 .net "AxorB", 0 0, L_0x2977fd0; 1 drivers +v0x294b290_0 .net "B", 0 0, L_0x2977820; 1 drivers +v0x294b340_0 .net "BornB", 0 0, L_0x2977a80; 1 drivers +v0x294b400_0 .net "CINandAxorB", 0 0, L_0x2978320; 1 drivers +v0x294b480_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x294b500_0 .net *"_s3", 0 0, L_0x2977d50; 1 drivers +v0x294b580_0 .net *"_s5", 0 0, L_0x2977f30; 1 drivers +v0x294b620_0 .net "carryin", 0 0, L_0x2963200; 1 drivers +v0x294b6c0_0 .net "carryout", 0 0, L_0x2978410; 1 drivers +v0x294b760_0 .net "nB", 0 0, L_0x29772c0; 1 drivers +v0x294b810_0 .net "nCmd2", 0 0, L_0x2977cb0; 1 drivers +v0x294b910_0 .net "subtract", 0 0, L_0x2977df0; 1 drivers +L_0x2977c10 .part v0x2960210_0, 0, 1; +L_0x2977d50 .part v0x2960210_0, 2, 1; +L_0x2977f30 .part v0x2960210_0, 0, 1; +S_0x294aa70 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x294a980; + .timescale -9 -12; +L_0x29773d0/d .functor NOT 1, L_0x2977c10, C4<0>, C4<0>, C4<0>; +L_0x29773d0 .delay (10000,10000,10000) L_0x29773d0/d; +L_0x2977490/d .functor AND 1, L_0x2977820, L_0x29773d0, C4<1>, C4<1>; +L_0x2977490 .delay (20000,20000,20000) L_0x2977490/d; +L_0x29779d0/d .functor AND 1, L_0x29772c0, L_0x2977c10, C4<1>, C4<1>; +L_0x29779d0 .delay (20000,20000,20000) L_0x29779d0/d; +L_0x2977a80/d .functor OR 1, L_0x2977490, L_0x29779d0, C4<0>, C4<0>; +L_0x2977a80 .delay (20000,20000,20000) L_0x2977a80/d; +v0x294ab60_0 .net "S", 0 0, L_0x2977c10; 1 drivers +v0x294ac00_0 .alias "in0", 0 0, v0x294b290_0; +v0x294aca0_0 .alias "in1", 0 0, v0x294b760_0; +v0x294ad40_0 .net "nS", 0 0, L_0x29773d0; 1 drivers +v0x294adf0_0 .net "out0", 0 0, L_0x2977490; 1 drivers +v0x294ae90_0 .net "out1", 0 0, L_0x29779d0; 1 drivers +v0x294af70_0 .alias "outfinal", 0 0, v0x294b340_0; +S_0x2949670 .scope generate, "addbits[19]" "addbits[19]" 3 283, 3 283, S_0x293c2e0; + .timescale -9 -12; +P_0x2949088 .param/l "i" 3 283, +C4<010011>; +S_0x29497e0 .scope module, "attempt" "MiddleAddSubSLT" 3 285, 3 189, S_0x2949670; + .timescale -9 -12; +L_0x2977950/d .functor NOT 1, L_0x2979790, C4<0>, C4<0>, C4<0>; +L_0x2977950 .delay (10000,10000,10000) L_0x2977950/d; +L_0x29789f0/d .functor NOT 1, L_0x2978ed0, C4<0>, C4<0>, C4<0>; +L_0x29789f0 .delay (10000,10000,10000) L_0x29789f0/d; +L_0x2978f70/d .functor AND 1, L_0x29790b0, L_0x29789f0, C4<1>, C4<1>; +L_0x2978f70 .delay (20000,20000,20000) L_0x2978f70/d; +L_0x2979150/d .functor XOR 1, L_0x29796f0, L_0x2978780, C4<0>, C4<0>; +L_0x2979150 .delay (40000,40000,40000) L_0x2979150/d; +L_0x29799c0/d .functor XOR 1, L_0x2979150, L_0x29798c0, C4<0>, C4<0>; +L_0x29799c0 .delay (40000,40000,40000) L_0x29799c0/d; +L_0x2979ab0/d .functor AND 1, L_0x29796f0, L_0x2978780, C4<1>, C4<1>; +L_0x2979ab0 .delay (20000,20000,20000) L_0x2979ab0/d; +L_0x2979c20/d .functor AND 1, L_0x2979150, L_0x29798c0, C4<1>, C4<1>; +L_0x2979c20 .delay (20000,20000,20000) L_0x2979c20/d; +L_0x2979d10/d .functor OR 1, L_0x2979ab0, L_0x2979c20, C4<0>, C4<0>; +L_0x2979d10 .delay (20000,20000,20000) L_0x2979d10/d; +v0x2949e70_0 .net "A", 0 0, L_0x29796f0; 1 drivers +v0x2949f30_0 .net "AandB", 0 0, L_0x2979ab0; 1 drivers +v0x2949fd0_0 .net "AddSubSLTSum", 0 0, L_0x29799c0; 1 drivers +v0x294a070_0 .net "AxorB", 0 0, L_0x2979150; 1 drivers +v0x294a0f0_0 .net "B", 0 0, L_0x2979790; 1 drivers +v0x294a1a0_0 .net "BornB", 0 0, L_0x2978780; 1 drivers +v0x294a260_0 .net "CINandAxorB", 0 0, L_0x2979c20; 1 drivers +v0x294a2e0_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x294a360_0 .net *"_s3", 0 0, L_0x2978ed0; 1 drivers +v0x294a3e0_0 .net *"_s5", 0 0, L_0x29790b0; 1 drivers +v0x294a480_0 .net "carryin", 0 0, L_0x29798c0; 1 drivers +v0x294a520_0 .net "carryout", 0 0, L_0x2979d10; 1 drivers +v0x294a5c0_0 .net "nB", 0 0, L_0x2977950; 1 drivers +v0x294a670_0 .net "nCmd2", 0 0, L_0x29789f0; 1 drivers +v0x294a770_0 .net "subtract", 0 0, L_0x2978f70; 1 drivers +L_0x2978950 .part v0x2960210_0, 0, 1; +L_0x2978ed0 .part v0x2960210_0, 2, 1; +L_0x29790b0 .part v0x2960210_0, 0, 1; +S_0x29498d0 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x29497e0; + .timescale -9 -12; +L_0x2963380/d .functor NOT 1, L_0x2978950, C4<0>, C4<0>, C4<0>; +L_0x2963380 .delay (10000,10000,10000) L_0x2963380/d; +L_0x29634e0/d .functor AND 1, L_0x2979790, L_0x2963380, C4<1>, C4<1>; +L_0x29634e0 .delay (20000,20000,20000) L_0x29634e0/d; +L_0x29635f0/d .functor AND 1, L_0x2977950, L_0x2978950, C4<1>, C4<1>; +L_0x29635f0 .delay (20000,20000,20000) L_0x29635f0/d; +L_0x2978780/d .functor OR 1, L_0x29634e0, L_0x29635f0, C4<0>, C4<0>; +L_0x2978780 .delay (20000,20000,20000) L_0x2978780/d; +v0x29499c0_0 .net "S", 0 0, L_0x2978950; 1 drivers +v0x2949a60_0 .alias "in0", 0 0, v0x294a0f0_0; +v0x2949b00_0 .alias "in1", 0 0, v0x294a5c0_0; +v0x2949ba0_0 .net "nS", 0 0, L_0x2963380; 1 drivers +v0x2949c50_0 .net "out0", 0 0, L_0x29634e0; 1 drivers +v0x2949cf0_0 .net "out1", 0 0, L_0x29635f0; 1 drivers +v0x2949dd0_0 .alias "outfinal", 0 0, v0x294a1a0_0; +S_0x29484d0 .scope generate, "addbits[20]" "addbits[20]" 3 283, 3 283, S_0x293c2e0; + .timescale -9 -12; +P_0x2947ee8 .param/l "i" 3 283, +C4<010100>; +S_0x2948640 .scope module, "attempt" "MiddleAddSubSLT" 3 285, 3 189, S_0x29484d0; + .timescale -9 -12; +L_0x297a3d0/d .functor NOT 1, L_0x297a1c0, C4<0>, C4<0>, C4<0>; +L_0x297a3d0 .delay (10000,10000,10000) L_0x297a3d0/d; +L_0x297a980/d .functor NOT 1, L_0x297aa20, C4<0>, C4<0>, C4<0>; +L_0x297a980 .delay (10000,10000,10000) L_0x297a980/d; +L_0x297aac0/d .functor AND 1, L_0x297ac00, L_0x297a980, C4<1>, C4<1>; +L_0x297aac0 .delay (20000,20000,20000) L_0x297aac0/d; +L_0x297aca0/d .functor XOR 1, L_0x297a120, L_0x297a750, C4<0>, C4<0>; +L_0x297aca0 .delay (40000,40000,40000) L_0x297aca0/d; +L_0x297ad90/d .functor XOR 1, L_0x297aca0, L_0x297a2f0, C4<0>, C4<0>; +L_0x297ad90 .delay (40000,40000,40000) L_0x297ad90/d; +L_0x297ae80/d .functor AND 1, L_0x297a120, L_0x297a750, C4<1>, C4<1>; +L_0x297ae80 .delay (20000,20000,20000) L_0x297ae80/d; +L_0x297aff0/d .functor AND 1, L_0x297aca0, L_0x297a2f0, C4<1>, C4<1>; +L_0x297aff0 .delay (20000,20000,20000) L_0x297aff0/d; +L_0x297b0e0/d .functor OR 1, L_0x297ae80, L_0x297aff0, C4<0>, C4<0>; +L_0x297b0e0 .delay (20000,20000,20000) L_0x297b0e0/d; +v0x2948cd0_0 .net "A", 0 0, L_0x297a120; 1 drivers +v0x2948d90_0 .net "AandB", 0 0, L_0x297ae80; 1 drivers +v0x2948e30_0 .net "AddSubSLTSum", 0 0, L_0x297ad90; 1 drivers +v0x2948ed0_0 .net "AxorB", 0 0, L_0x297aca0; 1 drivers +v0x2948f50_0 .net "B", 0 0, L_0x297a1c0; 1 drivers +v0x2949000_0 .net "BornB", 0 0, L_0x297a750; 1 drivers +v0x29490c0_0 .net "CINandAxorB", 0 0, L_0x297aff0; 1 drivers +v0x2949140_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x29491c0_0 .net *"_s3", 0 0, L_0x297aa20; 1 drivers +v0x2949240_0 .net *"_s5", 0 0, L_0x297ac00; 1 drivers +v0x29492e0_0 .net "carryin", 0 0, L_0x297a2f0; 1 drivers +v0x2949380_0 .net "carryout", 0 0, L_0x297b0e0; 1 drivers +v0x2949420_0 .net "nB", 0 0, L_0x297a3d0; 1 drivers +v0x29494d0_0 .net "nCmd2", 0 0, L_0x297a980; 1 drivers +v0x29495d0_0 .net "subtract", 0 0, L_0x297aac0; 1 drivers +L_0x297a8e0 .part v0x2960210_0, 0, 1; +L_0x297aa20 .part v0x2960210_0, 2, 1; +L_0x297ac00 .part v0x2960210_0, 0, 1; +S_0x2948730 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x2948640; + .timescale -9 -12; +L_0x297a4d0/d .functor NOT 1, L_0x297a8e0, C4<0>, C4<0>, C4<0>; +L_0x297a4d0 .delay (10000,10000,10000) L_0x297a4d0/d; +L_0x297a570/d .functor AND 1, L_0x297a1c0, L_0x297a4d0, C4<1>, C4<1>; +L_0x297a570 .delay (20000,20000,20000) L_0x297a570/d; +L_0x297a660/d .functor AND 1, L_0x297a3d0, L_0x297a8e0, C4<1>, C4<1>; +L_0x297a660 .delay (20000,20000,20000) L_0x297a660/d; +L_0x297a750/d .functor OR 1, L_0x297a570, L_0x297a660, C4<0>, C4<0>; +L_0x297a750 .delay (20000,20000,20000) L_0x297a750/d; +v0x2948820_0 .net "S", 0 0, L_0x297a8e0; 1 drivers +v0x29488c0_0 .alias "in0", 0 0, v0x2948f50_0; +v0x2948960_0 .alias "in1", 0 0, v0x2949420_0; +v0x2948a00_0 .net "nS", 0 0, L_0x297a4d0; 1 drivers +v0x2948ab0_0 .net "out0", 0 0, L_0x297a570; 1 drivers +v0x2948b50_0 .net "out1", 0 0, L_0x297a660; 1 drivers +v0x2948c30_0 .alias "outfinal", 0 0, v0x2949000_0; +S_0x2947330 .scope generate, "addbits[21]" "addbits[21]" 3 283, 3 283, S_0x293c2e0; + .timescale -9 -12; +P_0x2946d48 .param/l "i" 3 283, +C4<010101>; +S_0x29474a0 .scope module, "attempt" "MiddleAddSubSLT" 3 285, 3 189, S_0x2947330; + .timescale -9 -12; +L_0x297b7d0/d .functor NOT 1, L_0x297b590, C4<0>, C4<0>, C4<0>; +L_0x297b7d0 .delay (10000,10000,10000) L_0x297b7d0/d; +L_0x297bda0/d .functor NOT 1, L_0x297be60, C4<0>, C4<0>, C4<0>; +L_0x297bda0 .delay (10000,10000,10000) L_0x297bda0/d; +L_0x297bf00/d .functor AND 1, L_0x297c040, L_0x297bda0, C4<1>, C4<1>; +L_0x297bf00 .delay (20000,20000,20000) L_0x297bf00/d; +L_0x297c0e0/d .functor XOR 1, L_0x297b4f0, L_0x297bb30, C4<0>, C4<0>; +L_0x297c0e0 .delay (40000,40000,40000) L_0x297c0e0/d; +L_0x297c1d0/d .functor XOR 1, L_0x297c0e0, L_0x297b6c0, C4<0>, C4<0>; +L_0x297c1d0 .delay (40000,40000,40000) L_0x297c1d0/d; +L_0x297c2c0/d .functor AND 1, L_0x297b4f0, L_0x297bb30, C4<1>, C4<1>; +L_0x297c2c0 .delay (20000,20000,20000) L_0x297c2c0/d; +L_0x297c430/d .functor AND 1, L_0x297c0e0, L_0x297b6c0, C4<1>, C4<1>; +L_0x297c430 .delay (20000,20000,20000) L_0x297c430/d; +L_0x297c540/d .functor OR 1, L_0x297c2c0, L_0x297c430, C4<0>, C4<0>; +L_0x297c540 .delay (20000,20000,20000) L_0x297c540/d; +v0x2947b30_0 .net "A", 0 0, L_0x297b4f0; 1 drivers +v0x2947bf0_0 .net "AandB", 0 0, L_0x297c2c0; 1 drivers +v0x2947c90_0 .net "AddSubSLTSum", 0 0, L_0x297c1d0; 1 drivers +v0x2947d30_0 .net "AxorB", 0 0, L_0x297c0e0; 1 drivers +v0x2947db0_0 .net "B", 0 0, L_0x297b590; 1 drivers +v0x2947e60_0 .net "BornB", 0 0, L_0x297bb30; 1 drivers +v0x2947f20_0 .net "CINandAxorB", 0 0, L_0x297c430; 1 drivers +v0x2947fa0_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x2948020_0 .net *"_s3", 0 0, L_0x297be60; 1 drivers +v0x29480a0_0 .net *"_s5", 0 0, L_0x297c040; 1 drivers +v0x2948140_0 .net "carryin", 0 0, L_0x297b6c0; 1 drivers +v0x29481e0_0 .net "carryout", 0 0, L_0x297c540; 1 drivers +v0x2948280_0 .net "nB", 0 0, L_0x297b7d0; 1 drivers +v0x2948330_0 .net "nCmd2", 0 0, L_0x297bda0; 1 drivers +v0x2948430_0 .net "subtract", 0 0, L_0x297bf00; 1 drivers +L_0x297bd00 .part v0x2960210_0, 0, 1; +L_0x297be60 .part v0x2960210_0, 2, 1; +L_0x297c040 .part v0x2960210_0, 0, 1; +S_0x2947590 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x29474a0; + .timescale -9 -12; +L_0x297b8d0/d .functor NOT 1, L_0x297bd00, C4<0>, C4<0>, C4<0>; +L_0x297b8d0 .delay (10000,10000,10000) L_0x297b8d0/d; +L_0x297b930/d .functor AND 1, L_0x297b590, L_0x297b8d0, C4<1>, C4<1>; +L_0x297b930 .delay (20000,20000,20000) L_0x297b930/d; +L_0x297ba20/d .functor AND 1, L_0x297b7d0, L_0x297bd00, C4<1>, C4<1>; +L_0x297ba20 .delay (20000,20000,20000) L_0x297ba20/d; +L_0x297bb30/d .functor OR 1, L_0x297b930, L_0x297ba20, C4<0>, C4<0>; +L_0x297bb30 .delay (20000,20000,20000) L_0x297bb30/d; +v0x2947680_0 .net "S", 0 0, L_0x297bd00; 1 drivers +v0x2947720_0 .alias "in0", 0 0, v0x2947db0_0; +v0x29477c0_0 .alias "in1", 0 0, v0x2948280_0; +v0x2947860_0 .net "nS", 0 0, L_0x297b8d0; 1 drivers +v0x2947910_0 .net "out0", 0 0, L_0x297b930; 1 drivers +v0x29479b0_0 .net "out1", 0 0, L_0x297ba20; 1 drivers +v0x2947a90_0 .alias "outfinal", 0 0, v0x2947e60_0; +S_0x2946190 .scope generate, "addbits[22]" "addbits[22]" 3 283, 3 283, S_0x293c2e0; + .timescale -9 -12; +P_0x2945ba8 .param/l "i" 3 283, +C4<010110>; +S_0x2946300 .scope module, "attempt" "MiddleAddSubSLT" 3 285, 3 189, S_0x2946190; + .timescale -9 -12; +L_0x297b760/d .functor NOT 1, L_0x297ca10, C4<0>, C4<0>, C4<0>; +L_0x297b760 .delay (10000,10000,10000) L_0x297b760/d; +L_0x297d2d0/d .functor NOT 1, L_0x297d390, C4<0>, C4<0>, C4<0>; +L_0x297d2d0 .delay (10000,10000,10000) L_0x297d2d0/d; +L_0x297d430/d .functor AND 1, L_0x297d570, L_0x297d2d0, C4<1>, C4<1>; +L_0x297d430 .delay (20000,20000,20000) L_0x297d430/d; +L_0x297d610/d .functor XOR 1, L_0x297c970, L_0x297d060, C4<0>, C4<0>; +L_0x297d610 .delay (40000,40000,40000) L_0x297d610/d; +L_0x297d700/d .functor XOR 1, L_0x297d610, L_0x297cb40, C4<0>, C4<0>; +L_0x297d700 .delay (40000,40000,40000) L_0x297d700/d; +L_0x297d7f0/d .functor AND 1, L_0x297c970, L_0x297d060, C4<1>, C4<1>; +L_0x297d7f0 .delay (20000,20000,20000) L_0x297d7f0/d; +L_0x297d960/d .functor AND 1, L_0x297d610, L_0x297cb40, C4<1>, C4<1>; +L_0x297d960 .delay (20000,20000,20000) L_0x297d960/d; +L_0x297da50/d .functor OR 1, L_0x297d7f0, L_0x297d960, C4<0>, C4<0>; +L_0x297da50 .delay (20000,20000,20000) L_0x297da50/d; +v0x2946990_0 .net "A", 0 0, L_0x297c970; 1 drivers +v0x2946a50_0 .net "AandB", 0 0, L_0x297d7f0; 1 drivers +v0x2946af0_0 .net "AddSubSLTSum", 0 0, L_0x297d700; 1 drivers +v0x2946b90_0 .net "AxorB", 0 0, L_0x297d610; 1 drivers +v0x2946c10_0 .net "B", 0 0, L_0x297ca10; 1 drivers +v0x2946cc0_0 .net "BornB", 0 0, L_0x297d060; 1 drivers +v0x2946d80_0 .net "CINandAxorB", 0 0, L_0x297d960; 1 drivers +v0x2946e00_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x2946e80_0 .net *"_s3", 0 0, L_0x297d390; 1 drivers +v0x2946f00_0 .net *"_s5", 0 0, L_0x297d570; 1 drivers +v0x2946fa0_0 .net "carryin", 0 0, L_0x297cb40; 1 drivers +v0x2947040_0 .net "carryout", 0 0, L_0x297da50; 1 drivers +v0x29470e0_0 .net "nB", 0 0, L_0x297b760; 1 drivers +v0x2947190_0 .net "nCmd2", 0 0, L_0x297d2d0; 1 drivers +v0x2947290_0 .net "subtract", 0 0, L_0x297d430; 1 drivers +L_0x297d230 .part v0x2960210_0, 0, 1; +L_0x297d390 .part v0x2960210_0, 2, 1; +L_0x297d570 .part v0x2960210_0, 0, 1; +S_0x29463f0 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x2946300; + .timescale -9 -12; +L_0x297cd80/d .functor NOT 1, L_0x297d230, C4<0>, C4<0>, C4<0>; +L_0x297cd80 .delay (10000,10000,10000) L_0x297cd80/d; +L_0x297ce40/d .functor AND 1, L_0x297ca10, L_0x297cd80, C4<1>, C4<1>; +L_0x297ce40 .delay (20000,20000,20000) L_0x297ce40/d; +L_0x297cf50/d .functor AND 1, L_0x297b760, L_0x297d230, C4<1>, C4<1>; +L_0x297cf50 .delay (20000,20000,20000) L_0x297cf50/d; +L_0x297d060/d .functor OR 1, L_0x297ce40, L_0x297cf50, C4<0>, C4<0>; +L_0x297d060 .delay (20000,20000,20000) L_0x297d060/d; +v0x29464e0_0 .net "S", 0 0, L_0x297d230; 1 drivers +v0x2946580_0 .alias "in0", 0 0, v0x2946c10_0; +v0x2946620_0 .alias "in1", 0 0, v0x29470e0_0; +v0x29466c0_0 .net "nS", 0 0, L_0x297cd80; 1 drivers +v0x2946770_0 .net "out0", 0 0, L_0x297ce40; 1 drivers +v0x2946810_0 .net "out1", 0 0, L_0x297cf50; 1 drivers +v0x29468f0_0 .alias "outfinal", 0 0, v0x2946cc0_0; +S_0x2944ff0 .scope generate, "addbits[23]" "addbits[23]" 3 283, 3 283, S_0x293c2e0; + .timescale -9 -12; +P_0x2944a08 .param/l "i" 3 283, +C4<010111>; +S_0x2945160 .scope module, "attempt" "MiddleAddSubSLT" 3 285, 3 189, S_0x2944ff0; + .timescale -9 -12; +L_0x297cbe0/d .functor NOT 1, L_0x297df20, C4<0>, C4<0>, C4<0>; +L_0x297cbe0 .delay (10000,10000,10000) L_0x297cbe0/d; +L_0x297e6d0/d .functor NOT 1, L_0x297e770, C4<0>, C4<0>, C4<0>; +L_0x297e6d0 .delay (10000,10000,10000) L_0x297e6d0/d; +L_0x297e810/d .functor AND 1, L_0x297e950, L_0x297e6d0, C4<1>, C4<1>; +L_0x297e810 .delay (20000,20000,20000) L_0x297e810/d; +L_0x297e9f0/d .functor XOR 1, L_0x297de80, L_0x297e4a0, C4<0>, C4<0>; +L_0x297e9f0 .delay (40000,40000,40000) L_0x297e9f0/d; +L_0x297eae0/d .functor XOR 1, L_0x297e9f0, L_0x297e050, C4<0>, C4<0>; +L_0x297eae0 .delay (40000,40000,40000) L_0x297eae0/d; +L_0x297ebd0/d .functor AND 1, L_0x297de80, L_0x297e4a0, C4<1>, C4<1>; +L_0x297ebd0 .delay (20000,20000,20000) L_0x297ebd0/d; +L_0x297ed40/d .functor AND 1, L_0x297e9f0, L_0x297e050, C4<1>, C4<1>; +L_0x297ed40 .delay (20000,20000,20000) L_0x297ed40/d; +L_0x297ee30/d .functor OR 1, L_0x297ebd0, L_0x297ed40, C4<0>, C4<0>; +L_0x297ee30 .delay (20000,20000,20000) L_0x297ee30/d; +v0x29457f0_0 .net "A", 0 0, L_0x297de80; 1 drivers +v0x29458b0_0 .net "AandB", 0 0, L_0x297ebd0; 1 drivers +v0x2945950_0 .net "AddSubSLTSum", 0 0, L_0x297eae0; 1 drivers +v0x29459f0_0 .net "AxorB", 0 0, L_0x297e9f0; 1 drivers +v0x2945a70_0 .net "B", 0 0, L_0x297df20; 1 drivers +v0x2945b20_0 .net "BornB", 0 0, L_0x297e4a0; 1 drivers +v0x2945be0_0 .net "CINandAxorB", 0 0, L_0x297ed40; 1 drivers +v0x2945c60_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x2945ce0_0 .net *"_s3", 0 0, L_0x297e770; 1 drivers +v0x2945d60_0 .net *"_s5", 0 0, L_0x297e950; 1 drivers +v0x2945e00_0 .net "carryin", 0 0, L_0x297e050; 1 drivers +v0x2945ea0_0 .net "carryout", 0 0, L_0x297ee30; 1 drivers +v0x2945f40_0 .net "nB", 0 0, L_0x297cbe0; 1 drivers +v0x2945ff0_0 .net "nCmd2", 0 0, L_0x297e6d0; 1 drivers +v0x29460f0_0 .net "subtract", 0 0, L_0x297e810; 1 drivers +L_0x297e630 .part v0x2960210_0, 0, 1; +L_0x297e770 .part v0x2960210_0, 2, 1; +L_0x297e950 .part v0x2960210_0, 0, 1; +S_0x2945250 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x2945160; + .timescale -9 -12; +L_0x297e260/d .functor NOT 1, L_0x297e630, C4<0>, C4<0>, C4<0>; +L_0x297e260 .delay (10000,10000,10000) L_0x297e260/d; +L_0x297e2c0/d .functor AND 1, L_0x297df20, L_0x297e260, C4<1>, C4<1>; +L_0x297e2c0 .delay (20000,20000,20000) L_0x297e2c0/d; +L_0x297e3b0/d .functor AND 1, L_0x297cbe0, L_0x297e630, C4<1>, C4<1>; +L_0x297e3b0 .delay (20000,20000,20000) L_0x297e3b0/d; +L_0x297e4a0/d .functor OR 1, L_0x297e2c0, L_0x297e3b0, C4<0>, C4<0>; +L_0x297e4a0 .delay (20000,20000,20000) L_0x297e4a0/d; +v0x2945340_0 .net "S", 0 0, L_0x297e630; 1 drivers +v0x29453e0_0 .alias "in0", 0 0, v0x2945a70_0; +v0x2945480_0 .alias "in1", 0 0, v0x2945f40_0; +v0x2945520_0 .net "nS", 0 0, L_0x297e260; 1 drivers +v0x29455d0_0 .net "out0", 0 0, L_0x297e2c0; 1 drivers +v0x2945670_0 .net "out1", 0 0, L_0x297e3b0; 1 drivers +v0x2945750_0 .alias "outfinal", 0 0, v0x2945b20_0; +S_0x2943e50 .scope generate, "addbits[24]" "addbits[24]" 3 283, 3 283, S_0x293c2e0; + .timescale -9 -12; +P_0x2943868 .param/l "i" 3 283, +C4<011000>; +S_0x2943fc0 .scope module, "attempt" "MiddleAddSubSLT" 3 285, 3 189, S_0x2943e50; + .timescale -9 -12; +L_0x297e0f0/d .functor NOT 1, L_0x297f2e0, C4<0>, C4<0>, C4<0>; +L_0x297e0f0 .delay (10000,10000,10000) L_0x297e0f0/d; +L_0x297faf0/d .functor NOT 1, L_0x297fbb0, C4<0>, C4<0>, C4<0>; +L_0x297faf0 .delay (10000,10000,10000) L_0x297faf0/d; +L_0x297fc50/d .functor AND 1, L_0x297fd90, L_0x297faf0, C4<1>, C4<1>; +L_0x297fc50 .delay (20000,20000,20000) L_0x297fc50/d; +L_0x297fe30/d .functor XOR 1, L_0x297f240, L_0x297f880, C4<0>, C4<0>; +L_0x297fe30 .delay (40000,40000,40000) L_0x297fe30/d; +L_0x297ff20/d .functor XOR 1, L_0x297fe30, L_0x297f410, C4<0>, C4<0>; +L_0x297ff20 .delay (40000,40000,40000) L_0x297ff20/d; +L_0x2980040/d .functor AND 1, L_0x297f240, L_0x297f880, C4<1>, C4<1>; +L_0x2980040 .delay (20000,20000,20000) L_0x2980040/d; +L_0x29801e0/d .functor AND 1, L_0x297fe30, L_0x297f410, C4<1>, C4<1>; +L_0x29801e0 .delay (20000,20000,20000) L_0x29801e0/d; +L_0x29802f0/d .functor OR 1, L_0x2980040, L_0x29801e0, C4<0>, C4<0>; +L_0x29802f0 .delay (20000,20000,20000) L_0x29802f0/d; +v0x2944650_0 .net "A", 0 0, L_0x297f240; 1 drivers +v0x2944710_0 .net "AandB", 0 0, L_0x2980040; 1 drivers +v0x29447b0_0 .net "AddSubSLTSum", 0 0, L_0x297ff20; 1 drivers +v0x2944850_0 .net "AxorB", 0 0, L_0x297fe30; 1 drivers +v0x29448d0_0 .net "B", 0 0, L_0x297f2e0; 1 drivers +v0x2944980_0 .net "BornB", 0 0, L_0x297f880; 1 drivers +v0x2944a40_0 .net "CINandAxorB", 0 0, L_0x29801e0; 1 drivers +v0x2944ac0_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x2944b40_0 .net *"_s3", 0 0, L_0x297fbb0; 1 drivers +v0x2944bc0_0 .net *"_s5", 0 0, L_0x297fd90; 1 drivers +v0x2944c60_0 .net "carryin", 0 0, L_0x297f410; 1 drivers +v0x2944d00_0 .net "carryout", 0 0, L_0x29802f0; 1 drivers +v0x2944da0_0 .net "nB", 0 0, L_0x297e0f0; 1 drivers +v0x2944e50_0 .net "nCmd2", 0 0, L_0x297faf0; 1 drivers +v0x2944f50_0 .net "subtract", 0 0, L_0x297fc50; 1 drivers +L_0x297fa50 .part v0x2960210_0, 0, 1; +L_0x297fbb0 .part v0x2960210_0, 2, 1; +L_0x297fd90 .part v0x2960210_0, 0, 1; +S_0x29440b0 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x2943fc0; + .timescale -9 -12; +L_0x297f600/d .functor NOT 1, L_0x297fa50, C4<0>, C4<0>, C4<0>; +L_0x297f600 .delay (10000,10000,10000) L_0x297f600/d; +L_0x297f6a0/d .functor AND 1, L_0x297f2e0, L_0x297f600, C4<1>, C4<1>; +L_0x297f6a0 .delay (20000,20000,20000) L_0x297f6a0/d; +L_0x297f790/d .functor AND 1, L_0x297e0f0, L_0x297fa50, C4<1>, C4<1>; +L_0x297f790 .delay (20000,20000,20000) L_0x297f790/d; +L_0x297f880/d .functor OR 1, L_0x297f6a0, L_0x297f790, C4<0>, C4<0>; +L_0x297f880 .delay (20000,20000,20000) L_0x297f880/d; +v0x29441a0_0 .net "S", 0 0, L_0x297fa50; 1 drivers +v0x2944240_0 .alias "in0", 0 0, v0x29448d0_0; +v0x29442e0_0 .alias "in1", 0 0, v0x2944da0_0; +v0x2944380_0 .net "nS", 0 0, L_0x297f600; 1 drivers +v0x2944430_0 .net "out0", 0 0, L_0x297f6a0; 1 drivers +v0x29444d0_0 .net "out1", 0 0, L_0x297f790; 1 drivers +v0x29445b0_0 .alias "outfinal", 0 0, v0x2944980_0; +S_0x2942cb0 .scope generate, "addbits[25]" "addbits[25]" 3 283, 3 283, S_0x293c2e0; + .timescale -9 -12; +P_0x29426c8 .param/l "i" 3 283, +C4<011001>; +S_0x2942e20 .scope module, "attempt" "MiddleAddSubSLT" 3 285, 3 189, S_0x2942cb0; + .timescale -9 -12; +L_0x297f4b0/d .functor NOT 1, L_0x29807c0, C4<0>, C4<0>, C4<0>; +L_0x297f4b0 .delay (10000,10000,10000) L_0x297f4b0/d; +L_0x2980fe0/d .functor NOT 1, L_0x29810a0, C4<0>, C4<0>, C4<0>; +L_0x2980fe0 .delay (10000,10000,10000) L_0x2980fe0/d; +L_0x2981140/d .functor AND 1, L_0x2981280, L_0x2980fe0, C4<1>, C4<1>; +L_0x2981140 .delay (20000,20000,20000) L_0x2981140/d; +L_0x2981320/d .functor XOR 1, L_0x2980720, L_0x2980d90, C4<0>, C4<0>; +L_0x2981320 .delay (40000,40000,40000) L_0x2981320/d; +L_0x2981410/d .functor XOR 1, L_0x2981320, L_0x29808f0, C4<0>, C4<0>; +L_0x2981410 .delay (40000,40000,40000) L_0x2981410/d; +L_0x2981530/d .functor AND 1, L_0x2980720, L_0x2980d90, C4<1>, C4<1>; +L_0x2981530 .delay (20000,20000,20000) L_0x2981530/d; +L_0x29816d0/d .functor AND 1, L_0x2981320, L_0x29808f0, C4<1>, C4<1>; +L_0x29816d0 .delay (20000,20000,20000) L_0x29816d0/d; +L_0x29817e0/d .functor OR 1, L_0x2981530, L_0x29816d0, C4<0>, C4<0>; +L_0x29817e0 .delay (20000,20000,20000) L_0x29817e0/d; +v0x29434b0_0 .net "A", 0 0, L_0x2980720; 1 drivers +v0x2943570_0 .net "AandB", 0 0, L_0x2981530; 1 drivers +v0x2943610_0 .net "AddSubSLTSum", 0 0, L_0x2981410; 1 drivers +v0x29436b0_0 .net "AxorB", 0 0, L_0x2981320; 1 drivers +v0x2943730_0 .net "B", 0 0, L_0x29807c0; 1 drivers +v0x29437e0_0 .net "BornB", 0 0, L_0x2980d90; 1 drivers +v0x29438a0_0 .net "CINandAxorB", 0 0, L_0x29816d0; 1 drivers +v0x2943920_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x29439a0_0 .net *"_s3", 0 0, L_0x29810a0; 1 drivers +v0x2943a20_0 .net *"_s5", 0 0, L_0x2981280; 1 drivers +v0x2943ac0_0 .net "carryin", 0 0, L_0x29808f0; 1 drivers +v0x2943b60_0 .net "carryout", 0 0, L_0x29817e0; 1 drivers +v0x2943c00_0 .net "nB", 0 0, L_0x297f4b0; 1 drivers +v0x2943cb0_0 .net "nCmd2", 0 0, L_0x2980fe0; 1 drivers +v0x2943db0_0 .net "subtract", 0 0, L_0x2981140; 1 drivers +L_0x2980f40 .part v0x2960210_0, 0, 1; +L_0x29810a0 .part v0x2960210_0, 2, 1; +L_0x2981280 .part v0x2960210_0, 0, 1; +S_0x2942f10 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x2942e20; + .timescale -9 -12; +L_0x2980b10/d .functor NOT 1, L_0x2980f40, C4<0>, C4<0>, C4<0>; +L_0x2980b10 .delay (10000,10000,10000) L_0x2980b10/d; +L_0x2980bb0/d .functor AND 1, L_0x29807c0, L_0x2980b10, C4<1>, C4<1>; +L_0x2980bb0 .delay (20000,20000,20000) L_0x2980bb0/d; +L_0x2980ca0/d .functor AND 1, L_0x297f4b0, L_0x2980f40, C4<1>, C4<1>; +L_0x2980ca0 .delay (20000,20000,20000) L_0x2980ca0/d; +L_0x2980d90/d .functor OR 1, L_0x2980bb0, L_0x2980ca0, C4<0>, C4<0>; +L_0x2980d90 .delay (20000,20000,20000) L_0x2980d90/d; +v0x2943000_0 .net "S", 0 0, L_0x2980f40; 1 drivers +v0x29430a0_0 .alias "in0", 0 0, v0x2943730_0; +v0x2943140_0 .alias "in1", 0 0, v0x2943c00_0; +v0x29431e0_0 .net "nS", 0 0, L_0x2980b10; 1 drivers +v0x2943290_0 .net "out0", 0 0, L_0x2980bb0; 1 drivers +v0x2943330_0 .net "out1", 0 0, L_0x2980ca0; 1 drivers +v0x2943410_0 .alias "outfinal", 0 0, v0x29437e0_0; +S_0x2941b10 .scope generate, "addbits[26]" "addbits[26]" 3 283, 3 283, S_0x293c2e0; + .timescale -9 -12; +P_0x2941528 .param/l "i" 3 283, +C4<011010>; +S_0x2941c80 .scope module, "attempt" "MiddleAddSubSLT" 3 285, 3 189, S_0x2941b10; + .timescale -9 -12; +L_0x2980990/d .functor NOT 1, L_0x2981cb0, C4<0>, C4<0>, C4<0>; +L_0x2980990 .delay (10000,10000,10000) L_0x2980990/d; +L_0x29824c0/d .functor NOT 1, L_0x2982580, C4<0>, C4<0>, C4<0>; +L_0x29824c0 .delay (10000,10000,10000) L_0x29824c0/d; +L_0x2982620/d .functor AND 1, L_0x2982760, L_0x29824c0, C4<1>, C4<1>; +L_0x2982620 .delay (20000,20000,20000) L_0x2982620/d; +L_0x2982800/d .functor XOR 1, L_0x2981c10, L_0x2982250, C4<0>, C4<0>; +L_0x2982800 .delay (40000,40000,40000) L_0x2982800/d; +L_0x29828f0/d .functor XOR 1, L_0x2982800, L_0x2981de0, C4<0>, C4<0>; +L_0x29828f0 .delay (40000,40000,40000) L_0x29828f0/d; +L_0x2982a10/d .functor AND 1, L_0x2981c10, L_0x2982250, C4<1>, C4<1>; +L_0x2982a10 .delay (20000,20000,20000) L_0x2982a10/d; +L_0x2982bb0/d .functor AND 1, L_0x2982800, L_0x2981de0, C4<1>, C4<1>; +L_0x2982bb0 .delay (20000,20000,20000) L_0x2982bb0/d; +L_0x2982cc0/d .functor OR 1, L_0x2982a10, L_0x2982bb0, C4<0>, C4<0>; +L_0x2982cc0 .delay (20000,20000,20000) L_0x2982cc0/d; +v0x2942310_0 .net "A", 0 0, L_0x2981c10; 1 drivers +v0x29423d0_0 .net "AandB", 0 0, L_0x2982a10; 1 drivers +v0x2942470_0 .net "AddSubSLTSum", 0 0, L_0x29828f0; 1 drivers +v0x2942510_0 .net "AxorB", 0 0, L_0x2982800; 1 drivers +v0x2942590_0 .net "B", 0 0, L_0x2981cb0; 1 drivers +v0x2942640_0 .net "BornB", 0 0, L_0x2982250; 1 drivers +v0x2942700_0 .net "CINandAxorB", 0 0, L_0x2982bb0; 1 drivers +v0x2942780_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x2942800_0 .net *"_s3", 0 0, L_0x2982580; 1 drivers +v0x2942880_0 .net *"_s5", 0 0, L_0x2982760; 1 drivers +v0x2942920_0 .net "carryin", 0 0, L_0x2981de0; 1 drivers +v0x29429c0_0 .net "carryout", 0 0, L_0x2982cc0; 1 drivers +v0x2942a60_0 .net "nB", 0 0, L_0x2980990; 1 drivers +v0x2942b10_0 .net "nCmd2", 0 0, L_0x29824c0; 1 drivers +v0x2942c10_0 .net "subtract", 0 0, L_0x2982620; 1 drivers +L_0x2982420 .part v0x2960210_0, 0, 1; +L_0x2982580 .part v0x2960210_0, 2, 1; +L_0x2982760 .part v0x2960210_0, 0, 1; +S_0x2941d70 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x2941c80; + .timescale -9 -12; +L_0x2980a60/d .functor NOT 1, L_0x2982420, C4<0>, C4<0>, C4<0>; +L_0x2980a60 .delay (10000,10000,10000) L_0x2980a60/d; +L_0x2982070/d .functor AND 1, L_0x2981cb0, L_0x2980a60, C4<1>, C4<1>; +L_0x2982070 .delay (20000,20000,20000) L_0x2982070/d; +L_0x2982160/d .functor AND 1, L_0x2980990, L_0x2982420, C4<1>, C4<1>; +L_0x2982160 .delay (20000,20000,20000) L_0x2982160/d; +L_0x2982250/d .functor OR 1, L_0x2982070, L_0x2982160, C4<0>, C4<0>; +L_0x2982250 .delay (20000,20000,20000) L_0x2982250/d; +v0x2941e60_0 .net "S", 0 0, L_0x2982420; 1 drivers +v0x2941f00_0 .alias "in0", 0 0, v0x2942590_0; +v0x2941fa0_0 .alias "in1", 0 0, v0x2942a60_0; +v0x2942040_0 .net "nS", 0 0, L_0x2980a60; 1 drivers +v0x29420f0_0 .net "out0", 0 0, L_0x2982070; 1 drivers +v0x2942190_0 .net "out1", 0 0, L_0x2982160; 1 drivers +v0x2942270_0 .alias "outfinal", 0 0, v0x2942640_0; +S_0x2940970 .scope generate, "addbits[27]" "addbits[27]" 3 283, 3 283, S_0x293c2e0; + .timescale -9 -12; +P_0x2940388 .param/l "i" 3 283, +C4<011011>; +S_0x2940ae0 .scope module, "attempt" "MiddleAddSubSLT" 3 285, 3 189, S_0x2940970; + .timescale -9 -12; +L_0x2981e80/d .functor NOT 1, L_0x296f660, C4<0>, C4<0>, C4<0>; +L_0x2981e80 .delay (10000,10000,10000) L_0x2981e80/d; +L_0x29839a0/d .functor NOT 1, L_0x2983a60, C4<0>, C4<0>, C4<0>; +L_0x29839a0 .delay (10000,10000,10000) L_0x29839a0/d; +L_0x2983b00/d .functor AND 1, L_0x2983c40, L_0x29839a0, C4<1>, C4<1>; +L_0x2983b00 .delay (20000,20000,20000) L_0x2983b00/d; +L_0x2983ce0/d .functor XOR 1, L_0x296f5c0, L_0x2983730, C4<0>, C4<0>; +L_0x2983ce0 .delay (40000,40000,40000) L_0x2983ce0/d; +L_0x2983dd0/d .functor XOR 1, L_0x2983ce0, L_0x2984a80, C4<0>, C4<0>; +L_0x2983dd0 .delay (40000,40000,40000) L_0x2983dd0/d; +L_0x2983ef0/d .functor AND 1, L_0x296f5c0, L_0x2983730, C4<1>, C4<1>; +L_0x2983ef0 .delay (20000,20000,20000) L_0x2983ef0/d; +L_0x2984090/d .functor AND 1, L_0x2983ce0, L_0x2984a80, C4<1>, C4<1>; +L_0x2984090 .delay (20000,20000,20000) L_0x2984090/d; +L_0x29841a0/d .functor OR 1, L_0x2983ef0, L_0x2984090, C4<0>, C4<0>; +L_0x29841a0 .delay (20000,20000,20000) L_0x29841a0/d; +v0x2941170_0 .net "A", 0 0, L_0x296f5c0; 1 drivers +v0x2941230_0 .net "AandB", 0 0, L_0x2983ef0; 1 drivers +v0x29412d0_0 .net "AddSubSLTSum", 0 0, L_0x2983dd0; 1 drivers +v0x2941370_0 .net "AxorB", 0 0, L_0x2983ce0; 1 drivers +v0x29413f0_0 .net "B", 0 0, L_0x296f660; 1 drivers +v0x29414a0_0 .net "BornB", 0 0, L_0x2983730; 1 drivers +v0x2941560_0 .net "CINandAxorB", 0 0, L_0x2984090; 1 drivers +v0x29415e0_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x2941660_0 .net *"_s3", 0 0, L_0x2983a60; 1 drivers +v0x29416e0_0 .net *"_s5", 0 0, L_0x2983c40; 1 drivers +v0x2941780_0 .net "carryin", 0 0, L_0x2984a80; 1 drivers +v0x2941820_0 .net "carryout", 0 0, L_0x29841a0; 1 drivers +v0x29418c0_0 .net "nB", 0 0, L_0x2981e80; 1 drivers +v0x2941970_0 .net "nCmd2", 0 0, L_0x29839a0; 1 drivers +v0x2941a70_0 .net "subtract", 0 0, L_0x2983b00; 1 drivers +L_0x2983900 .part v0x2960210_0, 0, 1; +L_0x2983a60 .part v0x2960210_0, 2, 1; +L_0x2983c40 .part v0x2960210_0, 0, 1; +S_0x2940bd0 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x2940ae0; + .timescale -9 -12; +L_0x29834f0/d .functor NOT 1, L_0x2983900, C4<0>, C4<0>, C4<0>; +L_0x29834f0 .delay (10000,10000,10000) L_0x29834f0/d; +L_0x2983550/d .functor AND 1, L_0x296f660, L_0x29834f0, C4<1>, C4<1>; +L_0x2983550 .delay (20000,20000,20000) L_0x2983550/d; +L_0x2983640/d .functor AND 1, L_0x2981e80, L_0x2983900, C4<1>, C4<1>; +L_0x2983640 .delay (20000,20000,20000) L_0x2983640/d; +L_0x2983730/d .functor OR 1, L_0x2983550, L_0x2983640, C4<0>, C4<0>; +L_0x2983730 .delay (20000,20000,20000) L_0x2983730/d; +v0x2940cc0_0 .net "S", 0 0, L_0x2983900; 1 drivers +v0x2940d60_0 .alias "in0", 0 0, v0x29413f0_0; +v0x2940e00_0 .alias "in1", 0 0, v0x29418c0_0; +v0x2940ea0_0 .net "nS", 0 0, L_0x29834f0; 1 drivers +v0x2940f50_0 .net "out0", 0 0, L_0x2983550; 1 drivers +v0x2940ff0_0 .net "out1", 0 0, L_0x2983640; 1 drivers +v0x29410d0_0 .alias "outfinal", 0 0, v0x29414a0_0; +S_0x293f7d0 .scope generate, "addbits[28]" "addbits[28]" 3 283, 3 283, S_0x293c2e0; + .timescale -9 -12; +P_0x293f1e8 .param/l "i" 3 283, +C4<011100>; +S_0x293f940 .scope module, "attempt" "MiddleAddSubSLT" 3 285, 3 189, S_0x293f7d0; + .timescale -9 -12; +L_0x296f700/d .functor NOT 1, L_0x2984cb0, C4<0>, C4<0>, C4<0>; +L_0x296f700 .delay (10000,10000,10000) L_0x296f700/d; +L_0x2985130/d .functor NOT 1, L_0x29851d0, C4<0>, C4<0>, C4<0>; +L_0x2985130 .delay (10000,10000,10000) L_0x2985130/d; +L_0x2985270/d .functor AND 1, L_0x29853b0, L_0x2985130, C4<1>, C4<1>; +L_0x2985270 .delay (20000,20000,20000) L_0x2985270/d; +L_0x2985450/d .functor XOR 1, L_0x2984c10, L_0x2984860, C4<0>, C4<0>; +L_0x2985450 .delay (40000,40000,40000) L_0x2985450/d; +L_0x2985540/d .functor XOR 1, L_0x2985450, L_0x2984de0, C4<0>, C4<0>; +L_0x2985540 .delay (40000,40000,40000) L_0x2985540/d; +L_0x2985630/d .functor AND 1, L_0x2984c10, L_0x2984860, C4<1>, C4<1>; +L_0x2985630 .delay (20000,20000,20000) L_0x2985630/d; +L_0x29857a0/d .functor AND 1, L_0x2985450, L_0x2984de0, C4<1>, C4<1>; +L_0x29857a0 .delay (20000,20000,20000) L_0x29857a0/d; +L_0x2985890/d .functor OR 1, L_0x2985630, L_0x29857a0, C4<0>, C4<0>; +L_0x2985890 .delay (20000,20000,20000) L_0x2985890/d; +v0x293ffd0_0 .net "A", 0 0, L_0x2984c10; 1 drivers +v0x2940090_0 .net "AandB", 0 0, L_0x2985630; 1 drivers +v0x2940130_0 .net "AddSubSLTSum", 0 0, L_0x2985540; 1 drivers +v0x29401d0_0 .net "AxorB", 0 0, L_0x2985450; 1 drivers +v0x2940250_0 .net "B", 0 0, L_0x2984cb0; 1 drivers +v0x2940300_0 .net "BornB", 0 0, L_0x2984860; 1 drivers +v0x29403c0_0 .net "CINandAxorB", 0 0, L_0x29857a0; 1 drivers +v0x2940440_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x29404c0_0 .net *"_s3", 0 0, L_0x29851d0; 1 drivers +v0x2940540_0 .net *"_s5", 0 0, L_0x29853b0; 1 drivers +v0x29405e0_0 .net "carryin", 0 0, L_0x2984de0; 1 drivers +v0x2940680_0 .net "carryout", 0 0, L_0x2985890; 1 drivers +v0x2940720_0 .net "nB", 0 0, L_0x296f700; 1 drivers +v0x29407d0_0 .net "nCmd2", 0 0, L_0x2985130; 1 drivers +v0x29408d0_0 .net "subtract", 0 0, L_0x2985270; 1 drivers +L_0x2985090 .part v0x2960210_0, 0, 1; +L_0x29851d0 .part v0x2960210_0, 2, 1; +L_0x29853b0 .part v0x2960210_0, 0, 1; +S_0x293fa30 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x293f940; + .timescale -9 -12; +L_0x29845c0/d .functor NOT 1, L_0x2985090, C4<0>, C4<0>, C4<0>; +L_0x29845c0 .delay (10000,10000,10000) L_0x29845c0/d; +L_0x2984640/d .functor AND 1, L_0x2984cb0, L_0x29845c0, C4<1>, C4<1>; +L_0x2984640 .delay (20000,20000,20000) L_0x2984640/d; +L_0x2984750/d .functor AND 1, L_0x296f700, L_0x2985090, C4<1>, C4<1>; +L_0x2984750 .delay (20000,20000,20000) L_0x2984750/d; +L_0x2984860/d .functor OR 1, L_0x2984640, L_0x2984750, C4<0>, C4<0>; +L_0x2984860 .delay (20000,20000,20000) L_0x2984860/d; +v0x293fb20_0 .net "S", 0 0, L_0x2985090; 1 drivers +v0x293fbc0_0 .alias "in0", 0 0, v0x2940250_0; +v0x293fc60_0 .alias "in1", 0 0, v0x2940720_0; +v0x293fd00_0 .net "nS", 0 0, L_0x29845c0; 1 drivers +v0x293fdb0_0 .net "out0", 0 0, L_0x2984640; 1 drivers +v0x293fe50_0 .net "out1", 0 0, L_0x2984750; 1 drivers +v0x293ff30_0 .alias "outfinal", 0 0, v0x2940300_0; +S_0x293e630 .scope generate, "addbits[29]" "addbits[29]" 3 283, 3 283, S_0x293c2e0; + .timescale -9 -12; +P_0x293e048 .param/l "i" 3 283, +C4<011101>; +S_0x293e7a0 .scope module, "attempt" "MiddleAddSubSLT" 3 285, 3 189, S_0x293e630; + .timescale -9 -12; +L_0x2984e80/d .functor NOT 1, L_0x2985ca0, C4<0>, C4<0>, C4<0>; +L_0x2984e80 .delay (10000,10000,10000) L_0x2984e80/d; +L_0x2986550/d .functor NOT 1, L_0x2986610, C4<0>, C4<0>, C4<0>; +L_0x2986550 .delay (10000,10000,10000) L_0x2986550/d; +L_0x29866b0/d .functor AND 1, L_0x29867f0, L_0x2986550, C4<1>, C4<1>; +L_0x29866b0 .delay (20000,20000,20000) L_0x29866b0/d; +L_0x2986890/d .functor XOR 1, L_0x2985c00, L_0x2986320, C4<0>, C4<0>; +L_0x2986890 .delay (40000,40000,40000) L_0x2986890/d; +L_0x29869b0/d .functor XOR 1, L_0x2986890, L_0x2985dd0, C4<0>, C4<0>; +L_0x29869b0 .delay (40000,40000,40000) L_0x29869b0/d; +L_0x2986ad0/d .functor AND 1, L_0x2985c00, L_0x2986320, C4<1>, C4<1>; +L_0x2986ad0 .delay (20000,20000,20000) L_0x2986ad0/d; +L_0x2986c70/d .functor AND 1, L_0x2986890, L_0x2985dd0, C4<1>, C4<1>; +L_0x2986c70 .delay (20000,20000,20000) L_0x2986c70/d; +L_0x2986d60/d .functor OR 1, L_0x2986ad0, L_0x2986c70, C4<0>, C4<0>; +L_0x2986d60 .delay (20000,20000,20000) L_0x2986d60/d; +v0x293ee30_0 .net "A", 0 0, L_0x2985c00; 1 drivers +v0x293eef0_0 .net "AandB", 0 0, L_0x2986ad0; 1 drivers +v0x293ef90_0 .net "AddSubSLTSum", 0 0, L_0x29869b0; 1 drivers +v0x293f030_0 .net "AxorB", 0 0, L_0x2986890; 1 drivers +v0x293f0b0_0 .net "B", 0 0, L_0x2985ca0; 1 drivers +v0x293f160_0 .net "BornB", 0 0, L_0x2986320; 1 drivers +v0x293f220_0 .net "CINandAxorB", 0 0, L_0x2986c70; 1 drivers +v0x293f2a0_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x293f320_0 .net *"_s3", 0 0, L_0x2986610; 1 drivers +v0x293f3a0_0 .net *"_s5", 0 0, L_0x29867f0; 1 drivers +v0x293f440_0 .net "carryin", 0 0, L_0x2985dd0; 1 drivers +v0x293f4e0_0 .net "carryout", 0 0, L_0x2986d60; 1 drivers +v0x293f580_0 .net "nB", 0 0, L_0x2984e80; 1 drivers +v0x293f630_0 .net "nCmd2", 0 0, L_0x2986550; 1 drivers +v0x293f730_0 .net "subtract", 0 0, L_0x29866b0; 1 drivers +L_0x29864b0 .part v0x2960210_0, 0, 1; +L_0x2986610 .part v0x2960210_0, 2, 1; +L_0x29867f0 .part v0x2960210_0, 0, 1; +S_0x293e890 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x293e7a0; + .timescale -9 -12; +L_0x2984fe0/d .functor NOT 1, L_0x29864b0, C4<0>, C4<0>, C4<0>; +L_0x2984fe0 .delay (10000,10000,10000) L_0x2984fe0/d; +L_0x2986140/d .functor AND 1, L_0x2985ca0, L_0x2984fe0, C4<1>, C4<1>; +L_0x2986140 .delay (20000,20000,20000) L_0x2986140/d; +L_0x2986230/d .functor AND 1, L_0x2984e80, L_0x29864b0, C4<1>, C4<1>; +L_0x2986230 .delay (20000,20000,20000) L_0x2986230/d; +L_0x2986320/d .functor OR 1, L_0x2986140, L_0x2986230, C4<0>, C4<0>; +L_0x2986320 .delay (20000,20000,20000) L_0x2986320/d; +v0x293e980_0 .net "S", 0 0, L_0x29864b0; 1 drivers +v0x293ea20_0 .alias "in0", 0 0, v0x293f0b0_0; +v0x293eac0_0 .alias "in1", 0 0, v0x293f580_0; +v0x293eb60_0 .net "nS", 0 0, L_0x2984fe0; 1 drivers +v0x293ec10_0 .net "out0", 0 0, L_0x2986140; 1 drivers +v0x293ecb0_0 .net "out1", 0 0, L_0x2986230; 1 drivers +v0x293ed90_0 .alias "outfinal", 0 0, v0x293f160_0; +S_0x293d490 .scope generate, "addbits[30]" "addbits[30]" 3 283, 3 283, S_0x293c2e0; + .timescale -9 -12; +P_0x293ce88 .param/l "i" 3 283, +C4<011110>; +S_0x293d600 .scope module, "attempt" "MiddleAddSubSLT" 3 285, 3 189, S_0x293d490; + .timescale -9 -12; +L_0x2985e70/d .functor NOT 1, L_0x2987500, C4<0>, C4<0>, C4<0>; +L_0x2985e70 .delay (10000,10000,10000) L_0x2985e70/d; +L_0x2987ca0/d .functor NOT 1, L_0x2987d40, C4<0>, C4<0>, C4<0>; +L_0x2987ca0 .delay (10000,10000,10000) L_0x2987ca0/d; +L_0x2987de0/d .functor AND 1, L_0x2987f20, L_0x2987ca0, C4<1>, C4<1>; +L_0x2987de0 .delay (20000,20000,20000) L_0x2987de0/d; +L_0x2987fc0/d .functor XOR 1, L_0x2987460, L_0x2987a70, C4<0>, C4<0>; +L_0x2987fc0 .delay (40000,40000,40000) L_0x2987fc0/d; +L_0x29880b0/d .functor XOR 1, L_0x2987fc0, L_0x2987630, C4<0>, C4<0>; +L_0x29880b0 .delay (40000,40000,40000) L_0x29880b0/d; +L_0x29881d0/d .functor AND 1, L_0x2987460, L_0x2987a70, C4<1>, C4<1>; +L_0x29881d0 .delay (20000,20000,20000) L_0x29881d0/d; +L_0x2988370/d .functor AND 1, L_0x2987fc0, L_0x2987630, C4<1>, C4<1>; +L_0x2988370 .delay (20000,20000,20000) L_0x2988370/d; +L_0x2988460/d .functor OR 1, L_0x29881d0, L_0x2988370, C4<0>, C4<0>; +L_0x2988460 .delay (20000,20000,20000) L_0x2988460/d; +v0x293dc90_0 .net "A", 0 0, L_0x2987460; 1 drivers +v0x293dd50_0 .net "AandB", 0 0, L_0x29881d0; 1 drivers +v0x293ddf0_0 .net "AddSubSLTSum", 0 0, L_0x29880b0; 1 drivers +v0x293de90_0 .net "AxorB", 0 0, L_0x2987fc0; 1 drivers +v0x293df10_0 .net "B", 0 0, L_0x2987500; 1 drivers +v0x293dfc0_0 .net "BornB", 0 0, L_0x2987a70; 1 drivers +v0x293e080_0 .net "CINandAxorB", 0 0, L_0x2988370; 1 drivers +v0x293e100_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x293e180_0 .net *"_s3", 0 0, L_0x2987d40; 1 drivers +v0x293e200_0 .net *"_s5", 0 0, L_0x2987f20; 1 drivers +v0x293e2a0_0 .net "carryin", 0 0, L_0x2987630; 1 drivers +v0x293e340_0 .net "carryout", 0 0, L_0x2988460; 1 drivers +v0x293e3e0_0 .net "nB", 0 0, L_0x2985e70; 1 drivers +v0x293e490_0 .net "nCmd2", 0 0, L_0x2987ca0; 1 drivers +v0x293e590_0 .net "subtract", 0 0, L_0x2987de0; 1 drivers +L_0x2987c00 .part v0x2960210_0, 0, 1; +L_0x2987d40 .part v0x2960210_0, 2, 1; +L_0x2987f20 .part v0x2960210_0, 0, 1; +S_0x293d6f0 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x293d600; + .timescale -9 -12; +L_0x2985fd0/d .functor NOT 1, L_0x2987c00, C4<0>, C4<0>, C4<0>; +L_0x2985fd0 .delay (10000,10000,10000) L_0x2985fd0/d; +L_0x2986090/d .functor AND 1, L_0x2987500, L_0x2985fd0, C4<1>, C4<1>; +L_0x2986090 .delay (20000,20000,20000) L_0x2986090/d; +L_0x2987980/d .functor AND 1, L_0x2985e70, L_0x2987c00, C4<1>, C4<1>; +L_0x2987980 .delay (20000,20000,20000) L_0x2987980/d; +L_0x2987a70/d .functor OR 1, L_0x2986090, L_0x2987980, C4<0>, C4<0>; +L_0x2987a70 .delay (20000,20000,20000) L_0x2987a70/d; +v0x293d7e0_0 .net "S", 0 0, L_0x2987c00; 1 drivers +v0x293d880_0 .alias "in0", 0 0, v0x293df10_0; +v0x293d920_0 .alias "in1", 0 0, v0x293e3e0_0; +v0x293d9c0_0 .net "nS", 0 0, L_0x2985fd0; 1 drivers +v0x293da70_0 .net "out0", 0 0, L_0x2986090; 1 drivers +v0x293db10_0 .net "out1", 0 0, L_0x2987980; 1 drivers +v0x293dbf0_0 .alias "outfinal", 0 0, v0x293dfc0_0; +S_0x293c3d0 .scope generate, "addbits[31]" "addbits[31]" 3 283, 3 283, S_0x293c2e0; + .timescale -9 -12; +P_0x293c098 .param/l "i" 3 283, +C4<011111>; +S_0x293c4c0 .scope module, "attempt" "MiddleAddSubSLT" 3 285, 3 189, S_0x293c3d0; + .timescale -9 -12; +L_0x29876d0/d .functor NOT 1, L_0x2988930, C4<0>, C4<0>, C4<0>; +L_0x29876d0 .delay (10000,10000,10000) L_0x29876d0/d; +L_0x2989160/d .functor NOT 1, L_0x2989200, C4<0>, C4<0>, C4<0>; +L_0x2989160 .delay (10000,10000,10000) L_0x2989160/d; +L_0x29892a0/d .functor AND 1, L_0x29893e0, L_0x2989160, C4<1>, C4<1>; +L_0x29892a0 .delay (20000,20000,20000) L_0x29892a0/d; +L_0x2989480/d .functor XOR 1, L_0x2988890, L_0x2988f30, C4<0>, C4<0>; +L_0x2989480 .delay (40000,40000,40000) L_0x2989480/d; +L_0x29895a0/d .functor XOR 1, L_0x2989480, L_0x2988a60, C4<0>, C4<0>; +L_0x29895a0 .delay (40000,40000,40000) L_0x29895a0/d; +L_0x29896c0/d .functor AND 1, L_0x2988890, L_0x2988f30, C4<1>, C4<1>; +L_0x29896c0 .delay (20000,20000,20000) L_0x29896c0/d; +L_0x2989860/d .functor AND 1, L_0x2989480, L_0x2988a60, C4<1>, C4<1>; +L_0x2989860 .delay (20000,20000,20000) L_0x2989860/d; +L_0x2989950/d .functor OR 1, L_0x29896c0, L_0x2989860, C4<0>, C4<0>; +L_0x2989950 .delay (20000,20000,20000) L_0x2989950/d; +v0x293cb00_0 .net "A", 0 0, L_0x2988890; 1 drivers +v0x293cbc0_0 .net "AandB", 0 0, L_0x29896c0; 1 drivers +v0x293cc60_0 .net "AddSubSLTSum", 0 0, L_0x29895a0; 1 drivers +v0x293cd00_0 .net "AxorB", 0 0, L_0x2989480; 1 drivers +v0x293cd80_0 .net "B", 0 0, L_0x2988930; 1 drivers +v0x293ce00_0 .net "BornB", 0 0, L_0x2988f30; 1 drivers +v0x293cec0_0 .net "CINandAxorB", 0 0, L_0x2989860; 1 drivers +v0x293cf40_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x293d010_0 .net *"_s3", 0 0, L_0x2989200; 1 drivers +v0x293d090_0 .net *"_s5", 0 0, L_0x29893e0; 1 drivers +v0x293d130_0 .net "carryin", 0 0, L_0x2988a60; 1 drivers +v0x293d1d0_0 .net "carryout", 0 0, L_0x2989950; 1 drivers +v0x293d270_0 .net "nB", 0 0, L_0x29876d0; 1 drivers +v0x293d2f0_0 .net "nCmd2", 0 0, L_0x2989160; 1 drivers +v0x293d3f0_0 .net "subtract", 0 0, L_0x29892a0; 1 drivers +L_0x29890c0 .part v0x2960210_0, 0, 1; +L_0x2989200 .part v0x2960210_0, 2, 1; +L_0x29893e0 .part v0x2960210_0, 0, 1; +S_0x293c5b0 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x293c4c0; + .timescale -9 -12; +L_0x2987830/d .functor NOT 1, L_0x29890c0, C4<0>, C4<0>, C4<0>; +L_0x2987830 .delay (10000,10000,10000) L_0x2987830/d; +L_0x2988d50/d .functor AND 1, L_0x2988930, L_0x2987830, C4<1>, C4<1>; +L_0x2988d50 .delay (20000,20000,20000) L_0x2988d50/d; +L_0x2988e40/d .functor AND 1, L_0x29876d0, L_0x29890c0, C4<1>, C4<1>; +L_0x2988e40 .delay (20000,20000,20000) L_0x2988e40/d; +L_0x2988f30/d .functor OR 1, L_0x2988d50, L_0x2988e40, C4<0>, C4<0>; +L_0x2988f30 .delay (20000,20000,20000) L_0x2988f30/d; +v0x293c6a0_0 .net "S", 0 0, L_0x29890c0; 1 drivers +v0x293c720_0 .alias "in0", 0 0, v0x293cd80_0; +v0x293c7c0_0 .alias "in1", 0 0, v0x293d270_0; +v0x293c860_0 .net "nS", 0 0, L_0x2987830; 1 drivers +v0x293c8e0_0 .net "out0", 0 0, L_0x2988d50; 1 drivers +v0x293c980_0 .net "out1", 0 0, L_0x2988e40; 1 drivers +v0x293ca60_0 .alias "outfinal", 0 0, v0x293ce00_0; +S_0x28e1a50 .scope module, "test2" "SLT32" 2 156, 3 298, S_0x22efd20; + .timescale -9 -12; +P_0x28e1b48 .param/l "size" 3 330, +C4<0100000>; +L_0x29d14b0/d .functor NOT 1, L_0x29d15e0, C4<0>, C4<0>, C4<0>; +L_0x29d14b0 .delay (10000,10000,10000) L_0x29d14b0/d; +L_0x29d1680/d .functor AND 1, L_0x29d17c0, L_0x29d1860, L_0x29d14b0, C4<1>; +L_0x29d1680 .delay (20000,20000,20000) L_0x29d1680/d; +L_0x29d2c20/d .functor OR 1, L_0x29af990, C4<0>, C4<0>, C4<0>; +L_0x29d2c20 .delay (20000,20000,20000) L_0x29d2c20/d; +L_0x29d4420/d .functor XOR 1, RS_0x7f507e9ad6e8, L_0x29d0940, C4<0>, C4<0>; +L_0x29d4420 .delay (40000,40000,40000) L_0x29d4420/d; +L_0x29d09e0/d .functor NOT 1, RS_0x7f507e9ad718, C4<0>, C4<0>, C4<0>; +L_0x29d09e0 .delay (10000,10000,10000) L_0x29d09e0/d; +L_0x295fcf0/d .functor NOT 1, L_0x29afbc0, C4<0>, C4<0>, C4<0>; +L_0x295fcf0 .delay (10000,10000,10000) L_0x295fcf0/d; +L_0x29afc60/d .functor AND 1, L_0x29d09e0, L_0x29afe50, C4<1>, C4<1>; +L_0x29afc60 .delay (20000,20000,20000) L_0x29afc60/d; +L_0x29afef0/d .functor AND 1, RS_0x7f507e9ad718, L_0x295fcf0, C4<1>, C4<1>; +L_0x29afef0 .delay (20000,20000,20000) L_0x29afef0/d; +L_0x29b0030/d .functor AND 1, L_0x29afc60, L_0x29d1680, C4<1>, C4<1>; +L_0x29b0030 .delay (20000,20000,20000) L_0x29b0030/d; +L_0x29b0150/d .functor AND 1, L_0x29afef0, L_0x29d1680, C4<1>, C4<1>; +L_0x29b0150 .delay (20000,20000,20000) L_0x29b0150/d; +L_0x29d5990/d .functor OR 1, L_0x29b0030, L_0x29b0150, C4<0>, C4<0>; +L_0x29d5990 .delay (20000,20000,20000) L_0x29d5990/d; +v0x293afc0_0 .alias "A", 31 0, v0x295f580_0; +RS_0x7f507e96d718/0/0 .resolv tri, L_0x298dad0, L_0x298fdb0, L_0x2992010, L_0x2994200; +RS_0x7f507e96d718/0/4 .resolv tri, L_0x29964c0, L_0x2892350, L_0x299ca40, L_0x299ed10; +RS_0x7f507e96d718/0/8 .resolv tri, L_0x29a0ff0, L_0x29a31d0, L_0x29a53a0, L_0x29a7770; +RS_0x7f507e96d718/0/12 .resolv tri, L_0x29a9970, L_0x29abc90, L_0x29aded0, L_0x29b02b0; +RS_0x7f507e96d718/0/16 .resolv tri, L_0x298d400, L_0x2979420, L_0x29b7ab0, L_0x29b9c90; +RS_0x7f507e96d718/0/20 .resolv tri, L_0x29bbe40, L_0x29be020, L_0x29befc0, L_0x29c2800; +RS_0x7f507e96d718/0/24 .resolv tri, L_0x29c2fe0, L_0x29c4f90, L_0x29c7b30, L_0x29ca140; +RS_0x7f507e96d718/0/28 .resolv tri, L_0x29cc140, L_0x29ce830, L_0x29d0720, L_0x29d2a00; +RS_0x7f507e96d718/1/0 .resolv tri, RS_0x7f507e96d718/0/0, RS_0x7f507e96d718/0/4, RS_0x7f507e96d718/0/8, RS_0x7f507e96d718/0/12; +RS_0x7f507e96d718/1/4 .resolv tri, RS_0x7f507e96d718/0/16, RS_0x7f507e96d718/0/20, RS_0x7f507e96d718/0/24, RS_0x7f507e96d718/0/28; +RS_0x7f507e96d718 .resolv tri, RS_0x7f507e96d718/1/0, RS_0x7f507e96d718/1/4, C4, C4; +v0x293b060_0 .net8 "AddSubSLTSum", 31 0, RS_0x7f507e96d718; 32 drivers +v0x293b100_0 .alias "B", 31 0, v0x295f6a0_0; +RS_0x7f507e96d748/0/0 .resolv tri, L_0x298ce10, L_0x298f4e0, L_0x29917f0, L_0x29928c0; +RS_0x7f507e96d748/0/4 .resolv tri, L_0x2995c60, L_0x2996d70, L_0x299c200, L_0x299d1f0; +RS_0x7f507e96d748/0/8 .resolv tri, L_0x29a07d0, L_0x29a17c0, L_0x29a4b90, L_0x29a5f80; +RS_0x7f507e96d748/0/12 .resolv tri, L_0x29a9150, L_0x29aa300, L_0x29ad6a0, L_0x29ae760; +RS_0x7f507e96d748/0/16 .resolv tri, L_0x29b1ea0, L_0x29b3560, L_0x29b7270, L_0x29b7c40; +RS_0x7f507e96d748/0/20 .resolv tri, L_0x29bb630, L_0x29bbfd0, L_0x29bfdf0, L_0x29c07a0; +RS_0x7f507e96d748/0/24 .resolv tri, L_0x29c41d0, L_0x29c4b90, L_0x29c8960, L_0x29c9960; +RS_0x7f507e96d748/0/28 .resolv tri, L_0x29ccd50, L_0x29ce050, L_0x29d1320, L_0x29d39b0; +RS_0x7f507e96d748/1/0 .resolv tri, RS_0x7f507e96d748/0/0, RS_0x7f507e96d748/0/4, RS_0x7f507e96d748/0/8, RS_0x7f507e96d748/0/12; +RS_0x7f507e96d748/1/4 .resolv tri, RS_0x7f507e96d748/0/16, RS_0x7f507e96d748/0/20, RS_0x7f507e96d748/0/24, RS_0x7f507e96d748/0/28; +RS_0x7f507e96d748 .resolv tri, RS_0x7f507e96d748/1/0, RS_0x7f507e96d748/1/4, C4, C4; +v0x293b180_0 .net8 "CarryoutWire", 31 0, RS_0x7f507e96d748; 32 drivers +v0x293b230_0 .alias "Command", 2 0, v0x295f7a0_0; +RS_0x7f507e96d778/0/0 .resolv tri, L_0x298cd20, L_0x298f380, L_0x2991700, L_0x2993870; +RS_0x7f507e96d778/0/4 .resolv tri, L_0x2995b70, L_0x2891a20, L_0x299c110, L_0x299e300; +RS_0x7f507e96d778/0/8 .resolv tri, L_0x29a06e0, L_0x29a28d0, L_0x29a4aa0, L_0x29a6e70; +RS_0x7f507e96d778/0/12 .resolv tri, L_0x29a9060, L_0x29ab390, L_0x29ad5b0, L_0x29af7b0; +RS_0x7f507e96d778/0/16 .resolv tri, L_0x29b1db0, L_0x29b4780, L_0x29b7180, L_0x29b9360; +RS_0x7f507e96d778/0/20 .resolv tri, L_0x29bb540, L_0x29bd720, L_0x29bfd00, L_0x29c1ef0; +RS_0x7f507e96d778/0/24 .resolv tri, L_0x29c40e0, L_0x29c6290, L_0x29c8870, L_0x29caa60; +RS_0x7f507e96d778/0/28 .resolv tri, L_0x29ccc60, L_0x29cf070, L_0x29d1230, L_0x29d38c0; +RS_0x7f507e96d778/1/0 .resolv tri, RS_0x7f507e96d778/0/0, RS_0x7f507e96d778/0/4, RS_0x7f507e96d778/0/8, RS_0x7f507e96d778/0/12; +RS_0x7f507e96d778/1/4 .resolv tri, RS_0x7f507e96d778/0/16, RS_0x7f507e96d778/0/20, RS_0x7f507e96d778/0/24, RS_0x7f507e96d778/0/28; +RS_0x7f507e96d778 .resolv tri, RS_0x7f507e96d778/1/0, RS_0x7f507e96d778/1/4, C4, C4; +v0x293b2b0_0 .net8 "NewVal", 31 0, RS_0x7f507e96d778; 32 drivers +v0x293b350_0 .net "Res0OF1", 0 0, L_0x29afef0; 1 drivers +v0x293b3f0_0 .net "Res1OF0", 0 0, L_0x29afc60; 1 drivers +v0x293b490_0 .alias "SLTSum", 31 0, v0x2960440_0; +v0x293b560_0 .alias "SLTflag", 0 0, v0x2960640_0; +v0x293b5e0_0 .net "SLTflag0", 0 0, L_0x29b0030; 1 drivers +v0x293b680_0 .net "SLTflag1", 0 0, L_0x29b0150; 1 drivers +v0x293b720_0 .net "SLTon", 0 0, L_0x29d1680; 1 drivers +v0x293b7a0_0 .net *"_s497", 0 0, L_0x29d15e0; 1 drivers +v0x293b8c0_0 .net *"_s499", 0 0, L_0x29d17c0; 1 drivers +v0x293b960_0 .net *"_s501", 0 0, L_0x29d1860; 1 drivers +v0x293b820_0 .net *"_s521", 0 0, L_0x29af990; 1 drivers +v0x293bab0_0 .net/s *"_s522", 0 0, C4<0>; 1 drivers +v0x293bbd0_0 .net *"_s525", 0 0, L_0x29d0940; 1 drivers +v0x293bc50_0 .net *"_s527", 0 0, L_0x29afbc0; 1 drivers +v0x293bb30_0 .net *"_s529", 0 0, L_0x29afe50; 1 drivers +v0x293bd80_0 .alias "carryin", 31 0, v0x295fa50_0; +v0x293bcd0_0 .alias "carryout", 0 0, v0x2960870_0; +v0x293bec0_0 .net "nAddSubSLTSum", 0 0, L_0x295fcf0; 1 drivers +v0x293be00_0 .net "nCmd2", 0 0, L_0x29d14b0; 1 drivers +v0x293c010_0 .net "nOF", 0 0, L_0x29d09e0; 1 drivers +v0x293bf40_0 .alias "overflow", 0 0, v0x2960980_0; +v0x293c170_0 .alias "subtract", 31 0, v0x2960aa0_0; +L_0x298cd20 .part/pv L_0x298c890, 1, 1, 32; +L_0x298ce10 .part/pv L_0x298cbe0, 1, 1, 32; +L_0x298cf00 .part/pv L_0x298c5c0, 1, 1, 32; +L_0x298cff0 .part v0x295fe90_0, 1, 1; +L_0x298d090 .part v0x2960190_0, 1, 1; +L_0x298d1c0 .part RS_0x7f507e96d748, 0, 1; +L_0x298dad0 .part/pv L_0x291ec30, 1, 1, 32; +L_0x298db70 .part RS_0x7f507e96d778, 1, 1; +L_0x298e080 .part/pv L_0x298df40, 1, 1, 32; +L_0x298e1b0 .part RS_0x7f507e96d718, 1, 1; +L_0x298e300 .part RS_0x7f507e96d718, 1, 1; +L_0x298f380 .part/pv L_0x298eeb0, 2, 1, 32; +L_0x298f4e0 .part/pv L_0x298f220, 2, 1, 32; +L_0x298f5d0 .part/pv L_0x298ebe0, 2, 1, 32; +L_0x298f740 .part v0x295fe90_0, 2, 1; +L_0x298f7e0 .part v0x2960190_0, 2, 1; +L_0x298f9a0 .part RS_0x7f507e96d748, 1, 1; +L_0x298fdb0 .part/pv L_0x298fc70, 2, 1, 32; +L_0x298ff80 .part RS_0x7f507e96d778, 2, 1; +L_0x2990460 .part/pv L_0x2990320, 2, 1, 32; +L_0x298fee0 .part RS_0x7f507e96d718, 2, 1; +L_0x2990600 .part RS_0x7f507e96d718, 2, 1; +L_0x2991700 .part/pv L_0x2991250, 3, 1, 32; +L_0x29917f0 .part/pv L_0x29915a0, 3, 1, 32; +L_0x29906f0 .part/pv L_0x2990f80, 3, 1, 32; +L_0x2991a00 .part v0x295fe90_0, 3, 1; +L_0x29918e0 .part v0x2960190_0, 3, 1; +L_0x2991c10 .part RS_0x7f507e96d748, 2, 1; +L_0x2992010 .part/pv L_0x2991ed0, 3, 1, 32; +L_0x29920b0 .part RS_0x7f507e96d778, 3, 1; +L_0x2992620 .part/pv L_0x29924e0, 3, 1, 32; +L_0x29926c0 .part RS_0x7f507e96d718, 3, 1; +L_0x29921a0 .part RS_0x7f507e96d718, 3, 1; +L_0x2993870 .part/pv L_0x29933e0, 4, 1, 32; +L_0x29928c0 .part/pv L_0x2993730, 4, 1, 32; +L_0x2993a80 .part/pv L_0x2993110, 4, 1, 32; +L_0x2993960 .part v0x295fe90_0, 4, 1; +L_0x2993ca0 .part v0x2960190_0, 4, 1; +L_0x2993b70 .part RS_0x7f507e96d748, 3, 1; +L_0x2994200 .part/pv L_0x29940c0, 4, 1, 32; +L_0x2993dd0 .part RS_0x7f507e96d778, 4, 1; +L_0x29948c0 .part/pv L_0x2994780, 4, 1, 32; +L_0x29942a0 .part RS_0x7f507e96d718, 4, 1; +L_0x2994ac0 .part RS_0x7f507e96d718, 4, 1; +L_0x2995b70 .part/pv L_0x29956c0, 5, 1, 32; +L_0x2995c60 .part/pv L_0x2995a10, 5, 1, 32; +L_0x2994b60 .part/pv L_0x29953f0, 5, 1, 32; +L_0x2995ed0 .part v0x295fe90_0, 5, 1; +L_0x2995d50 .part v0x2960190_0, 5, 1; +L_0x2996100 .part RS_0x7f507e96d748, 4, 1; +L_0x29964c0 .part/pv L_0x2996380, 5, 1, 32; +L_0x2996560 .part RS_0x7f507e96d778, 5, 1; +L_0x2996b20 .part/pv L_0x29969e0, 5, 1, 32; +L_0x2996cd0 .part RS_0x7f507e96d718, 5, 1; +L_0x2996650 .part RS_0x7f507e96d718, 5, 1; +L_0x2891a20 .part/pv L_0x2891550, 6, 1, 32; +L_0x2996d70 .part/pv L_0x28918a0, 6, 1, 32; +L_0x2996e60 .part/pv L_0x29976c0, 6, 1, 32; +L_0x2891b10 .part v0x295fe90_0, 6, 1; +L_0x2891bb0 .part v0x2960190_0, 6, 1; +L_0x2891f20 .part RS_0x7f507e96d748, 5, 1; +L_0x2892350 .part/pv L_0x2892210, 6, 1, 32; +L_0x29927b0 .part RS_0x7f507e96d778, 6, 1; +L_0x2892a70 .part/pv L_0x2892930, 6, 1, 32; +L_0x2892600 .part RS_0x7f507e96d718, 6, 1; +L_0x28926f0 .part RS_0x7f507e96d718, 6, 1; +L_0x299c110 .part/pv L_0x299bc80, 7, 1, 32; +L_0x299c200 .part/pv L_0x299bfd0, 7, 1, 32; +L_0x2892b10 .part/pv L_0x299b9b0, 7, 1, 32; +L_0x2892c00 .part v0x295fe90_0, 7, 1; +L_0x299c530 .part v0x2960190_0, 7, 1; +L_0x299c5d0 .part RS_0x7f507e96d748, 6, 1; +L_0x299ca40 .part/pv L_0x299c900, 7, 1, 32; +L_0x299cae0 .part RS_0x7f507e96d778, 7, 1; +L_0x299d060 .part/pv L_0x299cf20, 7, 1, 32; +L_0x299d100 .part RS_0x7f507e96d718, 7, 1; +L_0x299cbd0 .part RS_0x7f507e96d718, 7, 1; +L_0x299e300 .part/pv L_0x299de50, 8, 1, 32; +L_0x299d1f0 .part/pv L_0x299e1a0, 8, 1, 32; +L_0x299d2e0 .part/pv L_0x299db80, 8, 1, 32; +L_0x299e680 .part v0x295fe90_0, 8, 1; +L_0x299e720 .part v0x2960190_0, 8, 1; +L_0x299e3f0 .part RS_0x7f507e96d748, 7, 1; +L_0x299ed10 .part/pv L_0x299e5e0, 8, 1, 32; +L_0x299e7c0 .part RS_0x7f507e96d778, 8, 1; +L_0x299f440 .part/pv L_0x299f300, 8, 1, 32; +L_0x299edb0 .part RS_0x7f507e96d718, 8, 1; +L_0x299eea0 .part RS_0x7f507e96d718, 8, 1; +L_0x29a06e0 .part/pv L_0x29a0230, 9, 1, 32; +L_0x29a07d0 .part/pv L_0x29a0580, 9, 1, 32; +L_0x299f4e0 .part/pv L_0x299ff60, 9, 1, 32; +L_0x299f5d0 .part v0x295fe90_0, 9, 1; +L_0x299f670 .part v0x2960190_0, 9, 1; +L_0x29a0bb0 .part RS_0x7f507e96d748, 8, 1; +L_0x29a0ff0 .part/pv L_0x29a0b10, 9, 1, 32; +L_0x29a1090 .part RS_0x7f507e96d778, 9, 1; +L_0x29a1630 .part/pv L_0x29a14f0, 9, 1, 32; +L_0x29a16d0 .part RS_0x7f507e96d718, 9, 1; +L_0x29a1180 .part RS_0x7f507e96d718, 9, 1; +L_0x29a28d0 .part/pv L_0x29a2420, 10, 1, 32; +L_0x29a17c0 .part/pv L_0x29a2770, 10, 1, 32; +L_0x29a18b0 .part/pv L_0x29a2150, 10, 1, 32; +L_0x29a19a0 .part v0x295fe90_0, 10, 1; +L_0x29a1a40 .part v0x2960190_0, 10, 1; +L_0x29a29c0 .part RS_0x7f507e96d748, 9, 1; +L_0x29a31d0 .part/pv L_0x29a30e0, 10, 1, 32; +L_0x29a2d90 .part RS_0x7f507e96d778, 10, 1; +L_0x29a3800 .part/pv L_0x29a36c0, 10, 1, 32; +L_0x29a3270 .part RS_0x7f507e96d718, 10, 1; +L_0x29a3360 .part RS_0x7f507e96d718, 10, 1; +L_0x29a4aa0 .part/pv L_0x29a45f0, 11, 1, 32; +L_0x29a4b90 .part/pv L_0x29a4940, 11, 1, 32; +L_0x29a38a0 .part/pv L_0x29a4320, 11, 1, 32; +L_0x29a3990 .part v0x295fe90_0, 11, 1; +L_0x29a3a30 .part v0x2960190_0, 11, 1; +L_0x29a3b60 .part RS_0x7f507e96d748, 10, 1; +L_0x29a53a0 .part/pv L_0x29a5260, 11, 1, 32; +L_0x29a5440 .part RS_0x7f507e96d778, 11, 1; +L_0x29a59e0 .part/pv L_0x29a58f0, 11, 1, 32; +L_0x29a5a80 .part RS_0x7f507e96d718, 11, 1; +L_0x28923f0 .part RS_0x7f507e96d718, 11, 1; +L_0x29a6e70 .part/pv L_0x29a6990, 12, 1, 32; +L_0x29a5f80 .part/pv L_0x29a6d10, 12, 1, 32; +L_0x29a6070 .part/pv L_0x29a66c0, 12, 1, 32; +L_0x29a6160 .part v0x295fe90_0, 12, 1; +L_0x29a6200 .part v0x2960190_0, 12, 1; +L_0x29a7360 .part RS_0x7f507e96d748, 11, 1; +L_0x29a7770 .part/pv L_0x29a7630, 12, 1, 32; +L_0x29a6f60 .part RS_0x7f507e96d778, 12, 1; +L_0x29a7da0 .part/pv L_0x29a7c60, 12, 1, 32; +L_0x29a7810 .part RS_0x7f507e96d718, 12, 1; +L_0x29a7900 .part RS_0x7f507e96d718, 12, 1; +L_0x29a9060 .part/pv L_0x29a8b50, 13, 1, 32; +L_0x29a9150 .part/pv L_0x29a8f00, 13, 1, 32; +L_0x29a7e40 .part/pv L_0x29a8880, 13, 1, 32; +L_0x29a7f30 .part v0x295fe90_0, 13, 1; +L_0x29a7fd0 .part v0x2960190_0, 13, 1; +L_0x29a8100 .part RS_0x7f507e96d748, 12, 1; +L_0x29a9970 .part/pv L_0x29a9830, 13, 1, 32; +L_0x29a9a10 .part RS_0x7f507e96d778, 13, 1; +L_0x29aa050 .part/pv L_0x29a9610, 13, 1, 32; +L_0x2996bc0 .part RS_0x7f507e96d718, 13, 1; +L_0x29a9b00 .part RS_0x7f507e96d718, 13, 1; +L_0x29ab390 .part/pv L_0x29aae80, 14, 1, 32; +L_0x29aa300 .part/pv L_0x29ab230, 14, 1, 32; +L_0x29aa3f0 .part/pv L_0x29aab80, 14, 1, 32; +L_0x29aa4e0 .part v0x295fe90_0, 14, 1; +L_0x29aa580 .part v0x2960190_0, 14, 1; +L_0x29aa6b0 .part RS_0x7f507e96d748, 13, 1; +L_0x29abc90 .part/pv L_0x29abb20, 14, 1, 32; +L_0x29ab480 .part RS_0x7f507e96d778, 14, 1; +L_0x29ac2e0 .part/pv L_0x29ac1f0, 14, 1, 32; +L_0x29abd30 .part RS_0x7f507e96d718, 14, 1; +L_0x29abe20 .part RS_0x7f507e96d718, 14, 1; +L_0x29ad5b0 .part/pv L_0x29ad0a0, 15, 1, 32; +L_0x29ad6a0 .part/pv L_0x29ad450, 15, 1, 32; +L_0x29ac380 .part/pv L_0x29acdd0, 15, 1, 32; +L_0x29ac470 .part v0x295fe90_0, 15, 1; +L_0x29ac510 .part v0x2960190_0, 15, 1; +L_0x29ac640 .part RS_0x7f507e96d748, 14, 1; +L_0x29aded0 .part/pv L_0x29add90, 15, 1, 32; +L_0x29adf70 .part RS_0x7f507e96d778, 15, 1; +L_0x29ae5d0 .part/pv L_0x29adb70, 15, 1, 32; +L_0x29ae670 .part RS_0x7f507e96d718, 15, 1; +L_0x29ae060 .part RS_0x7f507e96d718, 15, 1; +L_0x29af7b0 .part/pv L_0x29af2d0, 16, 1, 32; +L_0x29ae760 .part/pv L_0x29af650, 16, 1, 32; +L_0x29ae850 .part/pv L_0x29af000, 16, 1, 32; +L_0x29ae940 .part v0x295fe90_0, 16, 1; +L_0x29ae9e0 .part v0x2960190_0, 16, 1; +L_0x29aeb10 .part RS_0x7f507e96d748, 15, 1; +L_0x29b02b0 .part/pv L_0x299ebd0, 16, 1, 32; +L_0x29af8a0 .part RS_0x7f507e96d778, 16, 1; +L_0x29b0af0 .part/pv L_0x29b09b0, 16, 1, 32; +L_0x29b0350 .part RS_0x7f507e96d718, 16, 1; +L_0x29b0440 .part RS_0x7f507e96d718, 16, 1; +L_0x29b1db0 .part/pv L_0x29b18a0, 17, 1, 32; +L_0x29b1ea0 .part/pv L_0x29b1c50, 17, 1, 32; +L_0x29b0b90 .part/pv L_0x29b15d0, 17, 1, 32; +L_0x29b0c80 .part v0x295fe90_0, 17, 1; +L_0x29b0d20 .part v0x2960190_0, 17, 1; +L_0x29b0e50 .part RS_0x7f507e96d748, 16, 1; +L_0x298d400 .part/pv L_0x298d2c0, 17, 1, 32; +L_0x298d4a0 .part RS_0x7f507e96d778, 17, 1; +L_0x29b1f90 .part/pv L_0x298d9a0, 17, 1, 32; +L_0x29b2030 .part RS_0x7f507e96d718, 17, 1; +L_0x29b2120 .part RS_0x7f507e96d718, 17, 1; +L_0x29b4780 .part/pv L_0x29b42d0, 18, 1, 32; +L_0x29b3560 .part/pv L_0x29b4620, 18, 1, 32; +L_0x29b3650 .part/pv L_0x29b4000, 18, 1, 32; +L_0x29b3740 .part v0x295fe90_0, 18, 1; +L_0x29b37e0 .part v0x2960190_0, 18, 1; +L_0x29b3910 .part RS_0x7f507e96d748, 17, 1; +L_0x2979420 .part/pv L_0x29792e0, 18, 1, 32; +L_0x29794c0 .part RS_0x7f507e96d778, 18, 1; +L_0x29b48c0 .part/pv L_0x2978d90, 18, 1, 32; +L_0x29b4960 .part RS_0x7f507e96d718, 18, 1; +L_0x29b4a50 .part RS_0x7f507e96d718, 18, 1; +L_0x29b7180 .part/pv L_0x29b6cd0, 19, 1, 32; +L_0x29b7270 .part/pv L_0x29b7020, 19, 1, 32; +L_0x29b5e90 .part/pv L_0x29b6a00, 19, 1, 32; +L_0x29b5f80 .part v0x295fe90_0, 19, 1; +L_0x29b6020 .part v0x2960190_0, 19, 1; +L_0x29b6150 .part RS_0x7f507e96d748, 18, 1; +L_0x29b7ab0 .part/pv L_0x29b6440, 19, 1, 32; +L_0x29b7b50 .part RS_0x7f507e96d778, 19, 1; +L_0x298d620 .part/pv L_0x29b7760, 19, 1, 32; +L_0x29b78a0 .part RS_0x7f507e96d718, 19, 1; +L_0x29b82d0 .part RS_0x7f507e96d718, 19, 1; +L_0x29b9360 .part/pv L_0x29b8eb0, 20, 1, 32; +L_0x29b7c40 .part/pv L_0x29b9200, 20, 1, 32; +L_0x29b7d30 .part/pv L_0x29b8be0, 20, 1, 32; +L_0x29b7e20 .part v0x295fe90_0, 20, 1; +L_0x29b7ec0 .part v0x2960190_0, 20, 1; +L_0x29b7ff0 .part RS_0x7f507e96d748, 19, 1; +L_0x29b9c90 .part/pv L_0x29b9b50, 20, 1, 32; +L_0x29b9450 .part RS_0x7f507e96d778, 20, 1; +L_0x29b99d0 .part/pv L_0x29b9890, 20, 1, 32; +L_0x29b9a70 .part RS_0x7f507e96d718, 20, 1; +L_0x29ba460 .part RS_0x7f507e96d718, 20, 1; +L_0x29bb540 .part/pv L_0x29bb090, 21, 1, 32; +L_0x29bb630 .part/pv L_0x29bb3e0, 21, 1, 32; +L_0x29ba550 .part/pv L_0x29badc0, 21, 1, 32; +L_0x29ba640 .part v0x295fe90_0, 21, 1; +L_0x29ba6e0 .part v0x2960190_0, 21, 1; +L_0x29ba810 .part RS_0x7f507e96d748, 20, 1; +L_0x29bbe40 .part/pv L_0x29bab00, 21, 1, 32; +L_0x29bbee0 .part RS_0x7f507e96d778, 21, 1; +L_0x29bbc70 .part/pv L_0x29bbb30, 21, 1, 32; +L_0x29bbd10 .part RS_0x7f507e96d718, 21, 1; +L_0x29b73f0 .part RS_0x7f507e96d718, 21, 1; +L_0x29bd720 .part/pv L_0x29bd270, 22, 1, 32; +L_0x29bbfd0 .part/pv L_0x29bd5c0, 22, 1, 32; +L_0x29bc0c0 .part/pv L_0x29bcfa0, 22, 1, 32; +L_0x29bc1b0 .part v0x295fe90_0, 22, 1; +L_0x29bc250 .part v0x2960190_0, 22, 1; +L_0x29bc380 .part RS_0x7f507e96d748, 21, 1; +L_0x29be020 .part/pv L_0x29bc670, 22, 1, 32; +L_0x29a5b70 .part RS_0x7f507e96d778, 22, 1; +L_0x29bd990 .part/pv L_0x29bd850, 22, 1, 32; +L_0x29bda30 .part RS_0x7f507e96d718, 22, 1; +L_0x29bdb20 .part RS_0x7f507e96d718, 22, 1; +L_0x29bfd00 .part/pv L_0x29bf850, 23, 1, 32; +L_0x29bfdf0 .part/pv L_0x29bfba0, 23, 1, 32; +L_0x29be8d0 .part/pv L_0x29bf580, 23, 1, 32; +L_0x29be9c0 .part v0x295fe90_0, 23, 1; +L_0x29bea60 .part v0x2960190_0, 23, 1; +L_0x29beb90 .part RS_0x7f507e96d748, 22, 1; +L_0x29befc0 .part/pv L_0x29bee80, 23, 1, 32; +L_0x29c06b0 .part RS_0x7f507e96d778, 23, 1; +L_0x29c0440 .part/pv L_0x29c0300, 23, 1, 32; +L_0x29c04e0 .part RS_0x7f507e96d718, 23, 1; +L_0x29c05d0 .part RS_0x7f507e96d718, 23, 1; +L_0x29c1ef0 .part/pv L_0x29c1a40, 24, 1, 32; +L_0x29c07a0 .part/pv L_0x29c1d90, 24, 1, 32; +L_0x29c0890 .part/pv L_0x29c1770, 24, 1, 32; +L_0x29c0980 .part v0x295fe90_0, 24, 1; +L_0x29c0a20 .part v0x2960190_0, 24, 1; +L_0x29c0b50 .part RS_0x7f507e96d748, 23, 1; +L_0x29c2800 .part/pv L_0x29c0e40, 24, 1, 32; +L_0x29c1fe0 .part RS_0x7f507e96d778, 24, 1; +L_0x29c2500 .part/pv L_0x29c23c0, 24, 1, 32; +L_0x29c25a0 .part RS_0x7f507e96d718, 24, 1; +L_0x29c2690 .part RS_0x7f507e96d718, 24, 1; +L_0x29c40e0 .part/pv L_0x29c3c10, 25, 1, 32; +L_0x29c41d0 .part/pv L_0x29c3f80, 25, 1, 32; +L_0x29c28f0 .part/pv L_0x29c3940, 25, 1, 32; +L_0x29c29e0 .part v0x295fe90_0, 25, 1; +L_0x29c2a80 .part v0x2960190_0, 25, 1; +L_0x29c2bb0 .part RS_0x7f507e96d748, 24, 1; +L_0x29c2fe0 .part/pv L_0x29c2ea0, 25, 1, 32; +L_0x29c3080 .part RS_0x7f507e96d778, 25, 1; +L_0x29c4810 .part/pv L_0x29c46d0, 25, 1, 32; +L_0x29c48b0 .part RS_0x7f507e96d718, 25, 1; +L_0x29c49a0 .part RS_0x7f507e96d718, 25, 1; +L_0x29c6290 .part/pv L_0x29c5de0, 26, 1, 32; +L_0x29c4b90 .part/pv L_0x29c6130, 26, 1, 32; +L_0x29c4c80 .part/pv L_0x29c5b10, 26, 1, 32; +L_0x29830f0 .part v0x295fe90_0, 26, 1; +L_0x2983190 .part v0x2960190_0, 26, 1; +L_0x29832c0 .part RS_0x7f507e96d748, 25, 1; +L_0x29c4f90 .part/pv L_0x29c4e50, 26, 1, 32; +L_0x29c5030 .part RS_0x7f507e96d778, 26, 1; +L_0x29c6500 .part/pv L_0x29c63c0, 26, 1, 32; +L_0x29c65a0 .part RS_0x7f507e96d718, 26, 1; +L_0x29c6690 .part RS_0x7f507e96d718, 26, 1; +L_0x29c8870 .part/pv L_0x29c83c0, 27, 1, 32; +L_0x29c8960 .part/pv L_0x29c8710, 27, 1, 32; +L_0x29c7440 .part/pv L_0x29c80f0, 27, 1, 32; +L_0x29c7530 .part v0x295fe90_0, 27, 1; +L_0x29c75d0 .part v0x2960190_0, 27, 1; +L_0x29c7700 .part RS_0x7f507e96d748, 26, 1; +L_0x29c7b30 .part/pv L_0x29c79f0, 27, 1, 32; +L_0x29c7bd0 .part RS_0x7f507e96d778, 27, 1; +L_0x29c97d0 .part/pv L_0x29c9660, 27, 1, 32; +L_0x29c9870 .part RS_0x7f507e96d718, 27, 1; +L_0x29c8a50 .part RS_0x7f507e96d718, 27, 1; +L_0x29caa60 .part/pv L_0x29ca5d0, 28, 1, 32; +L_0x29c9960 .part/pv L_0x29ca920, 28, 1, 32; +L_0x29c9a50 .part/pv L_0x29ca350, 28, 1, 32; +L_0x29c9b40 .part v0x295fe90_0, 28, 1; +L_0x29c9be0 .part v0x2960190_0, 28, 1; +L_0x29c9d10 .part RS_0x7f507e96d748, 27, 1; +L_0x29ca140 .part/pv L_0x29ca000, 28, 1, 32; +L_0x29ca1e0 .part RS_0x7f507e96d778, 28, 1; +L_0x29cb9b0 .part/pv L_0x29cb840, 28, 1, 32; +L_0x29cab50 .part RS_0x7f507e96d718, 28, 1; +L_0x29cac40 .part RS_0x7f507e96d718, 28, 1; +L_0x29ccc60 .part/pv L_0x29cc7b0, 29, 1, 32; +L_0x29ccd50 .part/pv L_0x29ccb00, 29, 1, 32; +L_0x29cba50 .part/pv L_0x29cc4e0, 29, 1, 32; +L_0x29cbb40 .part v0x295fe90_0, 29, 1; +L_0x29cbbe0 .part v0x2960190_0, 29, 1; +L_0x29cbd10 .part RS_0x7f507e96d748, 28, 1; +L_0x29cc140 .part/pv L_0x29cc000, 29, 1, 32; +L_0x29cc1e0 .part RS_0x7f507e96d778, 29, 1; +L_0x29cdba0 .part/pv L_0x29cda60, 29, 1, 32; +L_0x29aa0f0 .part RS_0x7f507e96d718, 29, 1; +L_0x29aa1e0 .part RS_0x7f507e96d718, 29, 1; +L_0x29cf070 .part/pv L_0x29cebe0, 30, 1, 32; +L_0x29ce050 .part/pv L_0x29cef30, 30, 1, 32; +L_0x29ce140 .part/pv L_0x29cd6c0, 30, 1, 32; +L_0x29ce230 .part v0x295fe90_0, 30, 1; +L_0x29ce2d0 .part v0x2960190_0, 30, 1; +L_0x29ce400 .part RS_0x7f507e96d748, 29, 1; +L_0x29ce830 .part/pv L_0x29ce6f0, 30, 1, 32; +L_0x29ce8d0 .part RS_0x7f507e96d778, 30, 1; +L_0x29cff90 .part/pv L_0x29cfe20, 30, 1, 32; +L_0x29cf160 .part RS_0x7f507e96d718, 30, 1; +L_0x29cf250 .part RS_0x7f507e96d718, 30, 1; +L_0x29d1230 .part/pv L_0x29d0da0, 31, 1, 32; +L_0x29d1320 .part/pv L_0x29d10f0, 31, 1, 32; +L_0x29d0030 .part/pv L_0x29cfb40, 31, 1, 32; +L_0x29d0120 .part v0x295fe90_0, 31, 1; +L_0x29d01c0 .part v0x2960190_0, 31, 1; +L_0x29d02f0 .part RS_0x7f507e96d748, 30, 1; +L_0x29d0720 .part/pv L_0x29d05e0, 31, 1, 32; +L_0x29d07c0 .part RS_0x7f507e96d778, 31, 1; +L_0x29d2180 .part/pv L_0x29d2040, 31, 1, 32; +L_0x29d2220 .part RS_0x7f507e96d718, 31, 1; +L_0x29d1410 .part RS_0x7f507e96d718, 31, 1; +L_0x29d15e0 .part v0x2960210_0, 2, 1; +L_0x29d17c0 .part v0x2960210_0, 0, 1; +L_0x29d1860 .part v0x2960210_0, 1, 1; +L_0x29d38c0 .part/pv L_0x29d33e0, 0, 1, 32; +L_0x29d39b0 .part/pv L_0x29d3760, 0, 1, 32; +L_0x29d2310 .part/pv L_0x29d3110, 0, 1, 32; +L_0x29d2400 .part v0x295fe90_0, 0, 1; +L_0x29d24a0 .part v0x2960190_0, 0, 1; +L_0x29d25d0 .part RS_0x7f507e9ad748, 0, 1; +L_0x29d2a00 .part/pv L_0x29d28c0, 0, 1, 32; +L_0x29d2aa0 .part RS_0x7f507e96d778, 0, 1; +L_0x29af990 .part RS_0x7f507e96d748, 31, 1; +L_0x29d0940 .part RS_0x7f507e96d748, 30, 1; +L_0x29afbc0 .part RS_0x7f507e96d718, 31, 1; +L_0x29afe50 .part RS_0x7f507e96d778, 31, 1; +L_0x29d5e90 .part/pv L_0x29d5d30, 0, 1, 32; +L_0x29d5f30 .part RS_0x7f507e96d718, 0, 1; +S_0x2939fa0 .scope module, "attempt2" "MiddleAddSubSLT" 3 326, 3 189, S_0x28e1a50; + .timescale -9 -12; +L_0x29d1950/d .functor NOT 1, L_0x29d24a0, C4<0>, C4<0>, C4<0>; +L_0x29d1950 .delay (10000,10000,10000) L_0x29d1950/d; +L_0x29d2fb0/d .functor NOT 1, L_0x29d3070, C4<0>, C4<0>, C4<0>; +L_0x29d2fb0 .delay (10000,10000,10000) L_0x29d2fb0/d; +L_0x29d3110/d .functor AND 1, L_0x29d3250, L_0x29d2fb0, C4<1>, C4<1>; +L_0x29d3110 .delay (20000,20000,20000) L_0x29d3110/d; +L_0x29d32f0/d .functor XOR 1, L_0x29d2400, L_0x29d1e00, C4<0>, C4<0>; +L_0x29d32f0 .delay (40000,40000,40000) L_0x29d32f0/d; +L_0x29d33e0/d .functor XOR 1, L_0x29d32f0, L_0x29d25d0, C4<0>, C4<0>; +L_0x29d33e0 .delay (40000,40000,40000) L_0x29d33e0/d; +L_0x29d34d0/d .functor AND 1, L_0x29d2400, L_0x29d1e00, C4<1>, C4<1>; +L_0x29d34d0 .delay (20000,20000,20000) L_0x29d34d0/d; +L_0x29d3670/d .functor AND 1, L_0x29d32f0, L_0x29d25d0, C4<1>, C4<1>; +L_0x29d3670 .delay (20000,20000,20000) L_0x29d3670/d; +L_0x29d3760/d .functor OR 1, L_0x29d34d0, L_0x29d3670, C4<0>, C4<0>; +L_0x29d3760 .delay (20000,20000,20000) L_0x29d3760/d; +v0x293a620_0 .net "A", 0 0, L_0x29d2400; 1 drivers +v0x293a6e0_0 .net "AandB", 0 0, L_0x29d34d0; 1 drivers +v0x293a780_0 .net "AddSubSLTSum", 0 0, L_0x29d33e0; 1 drivers +v0x293a820_0 .net "AxorB", 0 0, L_0x29d32f0; 1 drivers +v0x293a8a0_0 .net "B", 0 0, L_0x29d24a0; 1 drivers +v0x293a950_0 .net "BornB", 0 0, L_0x29d1e00; 1 drivers +v0x293aa10_0 .net "CINandAxorB", 0 0, L_0x29d3670; 1 drivers +v0x293aa90_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x293ab10_0 .net *"_s3", 0 0, L_0x29d3070; 1 drivers +v0x293ab90_0 .net *"_s5", 0 0, L_0x29d3250; 1 drivers +v0x293ac30_0 .net "carryin", 0 0, L_0x29d25d0; 1 drivers +v0x293acd0_0 .net "carryout", 0 0, L_0x29d3760; 1 drivers +v0x293ad70_0 .net "nB", 0 0, L_0x29d1950; 1 drivers +v0x293ae20_0 .net "nCmd2", 0 0, L_0x29d2fb0; 1 drivers +v0x293af20_0 .net "subtract", 0 0, L_0x29d3110; 1 drivers +L_0x29d2f10 .part v0x2960210_0, 0, 1; +L_0x29d3070 .part v0x2960210_0, 2, 1; +L_0x29d3250 .part v0x2960210_0, 0, 1; +S_0x293a090 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x2939fa0; + .timescale -9 -12; +L_0x29d1b20/d .functor NOT 1, L_0x29d2f10, C4<0>, C4<0>, C4<0>; +L_0x29d1b20 .delay (10000,10000,10000) L_0x29d1b20/d; +L_0x29d1be0/d .functor AND 1, L_0x29d24a0, L_0x29d1b20, C4<1>, C4<1>; +L_0x29d1be0 .delay (20000,20000,20000) L_0x29d1be0/d; +L_0x29d1cf0/d .functor AND 1, L_0x29d1950, L_0x29d2f10, C4<1>, C4<1>; +L_0x29d1cf0 .delay (20000,20000,20000) L_0x29d1cf0/d; +L_0x29d1e00/d .functor OR 1, L_0x29d1be0, L_0x29d1cf0, C4<0>, C4<0>; +L_0x29d1e00 .delay (20000,20000,20000) L_0x29d1e00/d; +v0x293a180_0 .net "S", 0 0, L_0x29d2f10; 1 drivers +v0x293a240_0 .alias "in0", 0 0, v0x293a8a0_0; +v0x293a2e0_0 .alias "in1", 0 0, v0x293ad70_0; +v0x293a380_0 .net "nS", 0 0, L_0x29d1b20; 1 drivers +v0x293a400_0 .net "out0", 0 0, L_0x29d1be0; 1 drivers +v0x293a4a0_0 .net "out1", 0 0, L_0x29d1cf0; 1 drivers +v0x293a580_0 .alias "outfinal", 0 0, v0x293a950_0; +S_0x2939a30 .scope module, "setSLTresult" "TwoInMux" 3 327, 3 109, S_0x28e1a50; + .timescale -9 -12; +L_0x29d2670/d .functor NOT 1, L_0x29d1680, C4<0>, C4<0>, C4<0>; +L_0x29d2670 .delay (10000,10000,10000) L_0x29d2670/d; +L_0x29d2710/d .functor AND 1, L_0x29d2aa0, L_0x29d2670, C4<1>, C4<1>; +L_0x29d2710 .delay (20000,20000,20000) L_0x29d2710/d; +L_0x29d2820/d .functor AND 1, C4<0>, L_0x29d1680, C4<1>, C4<1>; +L_0x29d2820 .delay (20000,20000,20000) L_0x29d2820/d; +L_0x29d28c0/d .functor OR 1, L_0x29d2710, L_0x29d2820, C4<0>, C4<0>; +L_0x29d28c0 .delay (20000,20000,20000) L_0x29d28c0/d; +v0x2939b20_0 .alias "S", 0 0, v0x293b720_0; +v0x2939bc0_0 .net "in0", 0 0, L_0x29d2aa0; 1 drivers +v0x2939c60_0 .net "in1", 0 0, C4<0>; 1 drivers +v0x2939d00_0 .net "nS", 0 0, L_0x29d2670; 1 drivers +v0x2939d80_0 .net "out0", 0 0, L_0x29d2710; 1 drivers +v0x2939e20_0 .net "out1", 0 0, L_0x29d2820; 1 drivers +v0x2939f00_0 .net "outfinal", 0 0, L_0x29d28c0; 1 drivers +S_0x29394c0 .scope module, "FinalSLT" "TwoInMux" 3 354, 3 109, S_0x28e1a50; + .timescale -9 -12; +L_0x29d5ac0/d .functor NOT 1, L_0x29d5990, C4<0>, C4<0>, C4<0>; +L_0x29d5ac0 .delay (10000,10000,10000) L_0x29d5ac0/d; +L_0x29d5b80/d .functor AND 1, L_0x29d5f30, L_0x29d5ac0, C4<1>, C4<1>; +L_0x29d5b80 .delay (20000,20000,20000) L_0x29d5b80/d; +L_0x29d5c90/d .functor AND 1, L_0x29d5990, L_0x29d5990, C4<1>, C4<1>; +L_0x29d5c90 .delay (20000,20000,20000) L_0x29d5c90/d; +L_0x29d5d30/d .functor OR 1, L_0x29d5b80, L_0x29d5c90, C4<0>, C4<0>; +L_0x29d5d30 .delay (20000,20000,20000) L_0x29d5d30/d; +v0x29395b0_0 .alias "S", 0 0, v0x2960640_0; +v0x2939670_0 .net "in0", 0 0, L_0x29d5f30; 1 drivers +v0x2939710_0 .alias "in1", 0 0, v0x2960640_0; +v0x29397c0_0 .net "nS", 0 0, L_0x29d5ac0; 1 drivers +v0x2939870_0 .net "out0", 0 0, L_0x29d5b80; 1 drivers +v0x29398f0_0 .net "out1", 0 0, L_0x29d5c90; 1 drivers +v0x2939990_0 .net "outfinal", 0 0, L_0x29d5d30; 1 drivers +S_0x2937840 .scope generate, "sltbits[1]" "sltbits[1]" 3 332, 3 332, S_0x28e1a50; + .timescale -9 -12; +P_0x2937258 .param/l "i" 3 332, +C4<01>; +S_0x29384a0 .scope module, "attempt" "MiddleAddSubSLT" 3 334, 3 189, S_0x2937840; + .timescale -9 -12; +L_0x29760d0/d .functor NOT 1, L_0x298d090, C4<0>, C4<0>, C4<0>; +L_0x29760d0 .delay (10000,10000,10000) L_0x29760d0/d; +L_0x298b610/d .functor NOT 1, L_0x298b6d0, C4<0>, C4<0>, C4<0>; +L_0x298b610 .delay (10000,10000,10000) L_0x298b610/d; +L_0x298c5c0/d .functor AND 1, L_0x298c700, L_0x298b610, C4<1>, C4<1>; +L_0x298c5c0 .delay (20000,20000,20000) L_0x298c5c0/d; +L_0x298c7a0/d .functor XOR 1, L_0x298cff0, L_0x298b3a0, C4<0>, C4<0>; +L_0x298c7a0 .delay (40000,40000,40000) L_0x298c7a0/d; +L_0x298c890/d .functor XOR 1, L_0x298c7a0, L_0x298d1c0, C4<0>, C4<0>; +L_0x298c890 .delay (40000,40000,40000) L_0x298c890/d; +L_0x298c980/d .functor AND 1, L_0x298cff0, L_0x298b3a0, C4<1>, C4<1>; +L_0x298c980 .delay (20000,20000,20000) L_0x298c980/d; +L_0x298caf0/d .functor AND 1, L_0x298c7a0, L_0x298d1c0, C4<1>, C4<1>; +L_0x298caf0 .delay (20000,20000,20000) L_0x298caf0/d; +L_0x298cbe0/d .functor OR 1, L_0x298c980, L_0x298caf0, C4<0>, C4<0>; +L_0x298cbe0 .delay (20000,20000,20000) L_0x298cbe0/d; +v0x2938b20_0 .net "A", 0 0, L_0x298cff0; 1 drivers +v0x2938be0_0 .net "AandB", 0 0, L_0x298c980; 1 drivers +v0x2938c80_0 .net "AddSubSLTSum", 0 0, L_0x298c890; 1 drivers +v0x2938d20_0 .net "AxorB", 0 0, L_0x298c7a0; 1 drivers +v0x2938da0_0 .net "B", 0 0, L_0x298d090; 1 drivers +v0x2938e50_0 .net "BornB", 0 0, L_0x298b3a0; 1 drivers +v0x2938f10_0 .net "CINandAxorB", 0 0, L_0x298caf0; 1 drivers +v0x2938f90_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x2939010_0 .net *"_s3", 0 0, L_0x298b6d0; 1 drivers +v0x2939090_0 .net *"_s5", 0 0, L_0x298c700; 1 drivers +v0x2939130_0 .net "carryin", 0 0, L_0x298d1c0; 1 drivers +v0x29391d0_0 .net "carryout", 0 0, L_0x298cbe0; 1 drivers +v0x2939270_0 .net "nB", 0 0, L_0x29760d0; 1 drivers +v0x2939320_0 .net "nCmd2", 0 0, L_0x298b610; 1 drivers +v0x2939420_0 .net "subtract", 0 0, L_0x298c5c0; 1 drivers +L_0x298b570 .part v0x2960210_0, 0, 1; +L_0x298b6d0 .part v0x2960210_0, 2, 1; +L_0x298c700 .part v0x2960210_0, 0, 1; +S_0x2938590 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x29384a0; + .timescale -9 -12; +L_0x29762c0/d .functor NOT 1, L_0x298b570, C4<0>, C4<0>, C4<0>; +L_0x29762c0 .delay (10000,10000,10000) L_0x29762c0/d; +L_0x298b180/d .functor AND 1, L_0x298d090, L_0x29762c0, C4<1>, C4<1>; +L_0x298b180 .delay (20000,20000,20000) L_0x298b180/d; +L_0x298b290/d .functor AND 1, L_0x29760d0, L_0x298b570, C4<1>, C4<1>; +L_0x298b290 .delay (20000,20000,20000) L_0x298b290/d; +L_0x298b3a0/d .functor OR 1, L_0x298b180, L_0x298b290, C4<0>, C4<0>; +L_0x298b3a0 .delay (20000,20000,20000) L_0x298b3a0/d; +v0x2938680_0 .net "S", 0 0, L_0x298b570; 1 drivers +v0x2938740_0 .alias "in0", 0 0, v0x2938da0_0; +v0x29387e0_0 .alias "in1", 0 0, v0x2939270_0; +v0x2938880_0 .net "nS", 0 0, L_0x29762c0; 1 drivers +v0x2938900_0 .net "out0", 0 0, L_0x298b180; 1 drivers +v0x29389a0_0 .net "out1", 0 0, L_0x298b290; 1 drivers +v0x2938a80_0 .alias "outfinal", 0 0, v0x2938e50_0; +S_0x2937f30 .scope module, "setSLTres2" "TwoInMux" 3 335, 3 109, S_0x2937840; + .timescale -9 -12; +L_0x298d260/d .functor NOT 1, L_0x29d1680, C4<0>, C4<0>, C4<0>; +L_0x298d260 .delay (10000,10000,10000) L_0x298d260/d; +L_0x291ea80/d .functor AND 1, L_0x298db70, L_0x298d260, C4<1>, C4<1>; +L_0x291ea80 .delay (20000,20000,20000) L_0x291ea80/d; +L_0x291eb90/d .functor AND 1, C4<0>, L_0x29d1680, C4<1>, C4<1>; +L_0x291eb90 .delay (20000,20000,20000) L_0x291eb90/d; +L_0x291ec30/d .functor OR 1, L_0x291ea80, L_0x291eb90, C4<0>, C4<0>; +L_0x291ec30 .delay (20000,20000,20000) L_0x291ec30/d; +v0x2938020_0 .alias "S", 0 0, v0x293b720_0; +v0x29380c0_0 .net "in0", 0 0, L_0x298db70; 1 drivers +v0x2938160_0 .net "in1", 0 0, C4<0>; 1 drivers +v0x2938200_0 .net "nS", 0 0, L_0x298d260; 1 drivers +v0x2938280_0 .net "out0", 0 0, L_0x291ea80; 1 drivers +v0x2938320_0 .net "out1", 0 0, L_0x291eb90; 1 drivers +v0x2938400_0 .net "outfinal", 0 0, L_0x291ec30; 1 drivers +S_0x29379b0 .scope module, "setSLTres3" "TwoInMux" 3 336, 3 109, S_0x2937840; + .timescale -9 -12; +L_0x298dd00/d .functor NOT 1, L_0x29d1680, C4<0>, C4<0>, C4<0>; +L_0x298dd00 .delay (10000,10000,10000) L_0x298dd00/d; +L_0x298ddb0/d .functor AND 1, L_0x298e1b0, L_0x298dd00, C4<1>, C4<1>; +L_0x298ddb0 .delay (20000,20000,20000) L_0x298ddb0/d; +L_0x298dea0/d .functor AND 1, L_0x298e300, L_0x29d1680, C4<1>, C4<1>; +L_0x298dea0 .delay (20000,20000,20000) L_0x298dea0/d; +L_0x298df40/d .functor OR 1, L_0x298ddb0, L_0x298dea0, C4<0>, C4<0>; +L_0x298df40 .delay (20000,20000,20000) L_0x298df40/d; +v0x2937aa0_0 .alias "S", 0 0, v0x293b720_0; +v0x2937b20_0 .net "in0", 0 0, L_0x298e1b0; 1 drivers +v0x2937bc0_0 .net "in1", 0 0, L_0x298e300; 1 drivers +v0x2937c60_0 .net "nS", 0 0, L_0x298dd00; 1 drivers +v0x2937d10_0 .net "out0", 0 0, L_0x298ddb0; 1 drivers +v0x2937db0_0 .net "out1", 0 0, L_0x298dea0; 1 drivers +v0x2937e90_0 .net "outfinal", 0 0, L_0x298df40; 1 drivers +S_0x2935bc0 .scope generate, "sltbits[2]" "sltbits[2]" 3 332, 3 332, S_0x28e1a50; + .timescale -9 -12; +P_0x29355d8 .param/l "i" 3 332, +C4<010>; +S_0x2936820 .scope module, "attempt" "MiddleAddSubSLT" 3 334, 3 189, S_0x2935bc0; + .timescale -9 -12; +L_0x298e3a0/d .functor NOT 1, L_0x298f7e0, C4<0>, C4<0>, C4<0>; +L_0x298e3a0 .delay (10000,10000,10000) L_0x298e3a0/d; +L_0x298ea80/d .functor NOT 1, L_0x298eb40, C4<0>, C4<0>, C4<0>; +L_0x298ea80 .delay (10000,10000,10000) L_0x298ea80/d; +L_0x298ebe0/d .functor AND 1, L_0x298ed20, L_0x298ea80, C4<1>, C4<1>; +L_0x298ebe0 .delay (20000,20000,20000) L_0x298ebe0/d; +L_0x298edc0/d .functor XOR 1, L_0x298f740, L_0x298e810, C4<0>, C4<0>; +L_0x298edc0 .delay (40000,40000,40000) L_0x298edc0/d; +L_0x298eeb0/d .functor XOR 1, L_0x298edc0, L_0x298f9a0, C4<0>, C4<0>; +L_0x298eeb0 .delay (40000,40000,40000) L_0x298eeb0/d; +L_0x298efa0/d .functor AND 1, L_0x298f740, L_0x298e810, C4<1>, C4<1>; +L_0x298efa0 .delay (20000,20000,20000) L_0x298efa0/d; +L_0x298f110/d .functor AND 1, L_0x298edc0, L_0x298f9a0, C4<1>, C4<1>; +L_0x298f110 .delay (20000,20000,20000) L_0x298f110/d; +L_0x298f220/d .functor OR 1, L_0x298efa0, L_0x298f110, C4<0>, C4<0>; +L_0x298f220 .delay (20000,20000,20000) L_0x298f220/d; +v0x2936ea0_0 .net "A", 0 0, L_0x298f740; 1 drivers +v0x2936f60_0 .net "AandB", 0 0, L_0x298efa0; 1 drivers +v0x2937000_0 .net "AddSubSLTSum", 0 0, L_0x298eeb0; 1 drivers +v0x29370a0_0 .net "AxorB", 0 0, L_0x298edc0; 1 drivers +v0x2937120_0 .net "B", 0 0, L_0x298f7e0; 1 drivers +v0x29371d0_0 .net "BornB", 0 0, L_0x298e810; 1 drivers +v0x2937290_0 .net "CINandAxorB", 0 0, L_0x298f110; 1 drivers +v0x2937310_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x2937390_0 .net *"_s3", 0 0, L_0x298eb40; 1 drivers +v0x2937410_0 .net *"_s5", 0 0, L_0x298ed20; 1 drivers +v0x29374b0_0 .net "carryin", 0 0, L_0x298f9a0; 1 drivers +v0x2937550_0 .net "carryout", 0 0, L_0x298f220; 1 drivers +v0x29375f0_0 .net "nB", 0 0, L_0x298e3a0; 1 drivers +v0x29376a0_0 .net "nCmd2", 0 0, L_0x298ea80; 1 drivers +v0x29377a0_0 .net "subtract", 0 0, L_0x298ebe0; 1 drivers +L_0x298e9e0 .part v0x2960210_0, 0, 1; +L_0x298eb40 .part v0x2960210_0, 2, 1; +L_0x298ed20 .part v0x2960210_0, 0, 1; +S_0x2936910 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x2936820; + .timescale -9 -12; +L_0x298e530/d .functor NOT 1, L_0x298e9e0, C4<0>, C4<0>, C4<0>; +L_0x298e530 .delay (10000,10000,10000) L_0x298e530/d; +L_0x298e5f0/d .functor AND 1, L_0x298f7e0, L_0x298e530, C4<1>, C4<1>; +L_0x298e5f0 .delay (20000,20000,20000) L_0x298e5f0/d; +L_0x298e700/d .functor AND 1, L_0x298e3a0, L_0x298e9e0, C4<1>, C4<1>; +L_0x298e700 .delay (20000,20000,20000) L_0x298e700/d; +L_0x298e810/d .functor OR 1, L_0x298e5f0, L_0x298e700, C4<0>, C4<0>; +L_0x298e810 .delay (20000,20000,20000) L_0x298e810/d; +v0x2936a00_0 .net "S", 0 0, L_0x298e9e0; 1 drivers +v0x2936ac0_0 .alias "in0", 0 0, v0x2937120_0; +v0x2936b60_0 .alias "in1", 0 0, v0x29375f0_0; +v0x2936c00_0 .net "nS", 0 0, L_0x298e530; 1 drivers +v0x2936c80_0 .net "out0", 0 0, L_0x298e5f0; 1 drivers +v0x2936d20_0 .net "out1", 0 0, L_0x298e700; 1 drivers +v0x2936e00_0 .alias "outfinal", 0 0, v0x29371d0_0; +S_0x29362b0 .scope module, "setSLTres2" "TwoInMux" 3 335, 3 109, S_0x2935bc0; + .timescale -9 -12; +L_0x298e2a0/d .functor NOT 1, L_0x29d1680, C4<0>, C4<0>, C4<0>; +L_0x298e2a0 .delay (10000,10000,10000) L_0x298e2a0/d; +L_0x298fb10/d .functor AND 1, L_0x298ff80, L_0x298e2a0, C4<1>, C4<1>; +L_0x298fb10 .delay (20000,20000,20000) L_0x298fb10/d; +L_0x298fbd0/d .functor AND 1, C4<0>, L_0x29d1680, C4<1>, C4<1>; +L_0x298fbd0 .delay (20000,20000,20000) L_0x298fbd0/d; +L_0x298fc70/d .functor OR 1, L_0x298fb10, L_0x298fbd0, C4<0>, C4<0>; +L_0x298fc70 .delay (20000,20000,20000) L_0x298fc70/d; +v0x29363a0_0 .alias "S", 0 0, v0x293b720_0; +v0x2936440_0 .net "in0", 0 0, L_0x298ff80; 1 drivers +v0x29364e0_0 .net "in1", 0 0, C4<0>; 1 drivers +v0x2936580_0 .net "nS", 0 0, L_0x298e2a0; 1 drivers +v0x2936600_0 .net "out0", 0 0, L_0x298fb10; 1 drivers +v0x29366a0_0 .net "out1", 0 0, L_0x298fbd0; 1 drivers +v0x2936780_0 .net "outfinal", 0 0, L_0x298fc70; 1 drivers +S_0x2935d30 .scope module, "setSLTres3" "TwoInMux" 3 336, 3 109, S_0x2935bc0; + .timescale -9 -12; +L_0x2990060/d .functor NOT 1, L_0x29d1680, C4<0>, C4<0>, C4<0>; +L_0x2990060 .delay (10000,10000,10000) L_0x2990060/d; +L_0x2990170/d .functor AND 1, L_0x298fee0, L_0x2990060, C4<1>, C4<1>; +L_0x2990170 .delay (20000,20000,20000) L_0x2990170/d; +L_0x2990280/d .functor AND 1, L_0x2990600, L_0x29d1680, C4<1>, C4<1>; +L_0x2990280 .delay (20000,20000,20000) L_0x2990280/d; +L_0x2990320/d .functor OR 1, L_0x2990170, L_0x2990280, C4<0>, C4<0>; +L_0x2990320 .delay (20000,20000,20000) L_0x2990320/d; +v0x2935e20_0 .alias "S", 0 0, v0x293b720_0; +v0x2935ea0_0 .net "in0", 0 0, L_0x298fee0; 1 drivers +v0x2935f40_0 .net "in1", 0 0, L_0x2990600; 1 drivers +v0x2935fe0_0 .net "nS", 0 0, L_0x2990060; 1 drivers +v0x2936090_0 .net "out0", 0 0, L_0x2990170; 1 drivers +v0x2936130_0 .net "out1", 0 0, L_0x2990280; 1 drivers +v0x2936210_0 .net "outfinal", 0 0, L_0x2990320; 1 drivers +S_0x2933f40 .scope generate, "sltbits[3]" "sltbits[3]" 3 332, 3 332, S_0x28e1a50; + .timescale -9 -12; +P_0x2933958 .param/l "i" 3 332, +C4<011>; +S_0x2934ba0 .scope module, "attempt" "MiddleAddSubSLT" 3 334, 3 189, S_0x2933f40; + .timescale -9 -12; +L_0x2990500/d .functor NOT 1, L_0x29918e0, C4<0>, C4<0>, C4<0>; +L_0x2990500 .delay (10000,10000,10000) L_0x2990500/d; +L_0x2990e20/d .functor NOT 1, L_0x2990ee0, C4<0>, C4<0>, C4<0>; +L_0x2990e20 .delay (10000,10000,10000) L_0x2990e20/d; +L_0x2990f80/d .functor AND 1, L_0x29910c0, L_0x2990e20, C4<1>, C4<1>; +L_0x2990f80 .delay (20000,20000,20000) L_0x2990f80/d; +L_0x2991160/d .functor XOR 1, L_0x2991a00, L_0x2990bb0, C4<0>, C4<0>; +L_0x2991160 .delay (40000,40000,40000) L_0x2991160/d; +L_0x2991250/d .functor XOR 1, L_0x2991160, L_0x2991c10, C4<0>, C4<0>; +L_0x2991250 .delay (40000,40000,40000) L_0x2991250/d; +L_0x2991340/d .functor AND 1, L_0x2991a00, L_0x2990bb0, C4<1>, C4<1>; +L_0x2991340 .delay (20000,20000,20000) L_0x2991340/d; +L_0x29914b0/d .functor AND 1, L_0x2991160, L_0x2991c10, C4<1>, C4<1>; +L_0x29914b0 .delay (20000,20000,20000) L_0x29914b0/d; +L_0x29915a0/d .functor OR 1, L_0x2991340, L_0x29914b0, C4<0>, C4<0>; +L_0x29915a0 .delay (20000,20000,20000) L_0x29915a0/d; +v0x2935220_0 .net "A", 0 0, L_0x2991a00; 1 drivers +v0x29352e0_0 .net "AandB", 0 0, L_0x2991340; 1 drivers +v0x2935380_0 .net "AddSubSLTSum", 0 0, L_0x2991250; 1 drivers +v0x2935420_0 .net "AxorB", 0 0, L_0x2991160; 1 drivers +v0x29354a0_0 .net "B", 0 0, L_0x29918e0; 1 drivers +v0x2935550_0 .net "BornB", 0 0, L_0x2990bb0; 1 drivers +v0x2935610_0 .net "CINandAxorB", 0 0, L_0x29914b0; 1 drivers +v0x2935690_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x2935710_0 .net *"_s3", 0 0, L_0x2990ee0; 1 drivers +v0x2935790_0 .net *"_s5", 0 0, L_0x29910c0; 1 drivers +v0x2935830_0 .net "carryin", 0 0, L_0x2991c10; 1 drivers +v0x29358d0_0 .net "carryout", 0 0, L_0x29915a0; 1 drivers +v0x2935970_0 .net "nB", 0 0, L_0x2990500; 1 drivers +v0x2935a20_0 .net "nCmd2", 0 0, L_0x2990e20; 1 drivers +v0x2935b20_0 .net "subtract", 0 0, L_0x2990f80; 1 drivers +L_0x2990d80 .part v0x2960210_0, 0, 1; +L_0x2990ee0 .part v0x2960210_0, 2, 1; +L_0x29910c0 .part v0x2960210_0, 0, 1; +S_0x2934c90 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x2934ba0; + .timescale -9 -12; +L_0x29908d0/d .functor NOT 1, L_0x2990d80, C4<0>, C4<0>, C4<0>; +L_0x29908d0 .delay (10000,10000,10000) L_0x29908d0/d; +L_0x2990990/d .functor AND 1, L_0x29918e0, L_0x29908d0, C4<1>, C4<1>; +L_0x2990990 .delay (20000,20000,20000) L_0x2990990/d; +L_0x2990aa0/d .functor AND 1, L_0x2990500, L_0x2990d80, C4<1>, C4<1>; +L_0x2990aa0 .delay (20000,20000,20000) L_0x2990aa0/d; +L_0x2990bb0/d .functor OR 1, L_0x2990990, L_0x2990aa0, C4<0>, C4<0>; +L_0x2990bb0 .delay (20000,20000,20000) L_0x2990bb0/d; +v0x2934d80_0 .net "S", 0 0, L_0x2990d80; 1 drivers +v0x2934e40_0 .alias "in0", 0 0, v0x29354a0_0; +v0x2934ee0_0 .alias "in1", 0 0, v0x2935970_0; +v0x2934f80_0 .net "nS", 0 0, L_0x29908d0; 1 drivers +v0x2935000_0 .net "out0", 0 0, L_0x2990990; 1 drivers +v0x29350a0_0 .net "out1", 0 0, L_0x2990aa0; 1 drivers +v0x2935180_0 .alias "outfinal", 0 0, v0x2935550_0; +S_0x2934630 .scope module, "setSLTres2" "TwoInMux" 3 335, 3 109, S_0x2933f40; + .timescale -9 -12; +L_0x2991aa0/d .functor NOT 1, L_0x29d1680, C4<0>, C4<0>, C4<0>; +L_0x2991aa0 .delay (10000,10000,10000) L_0x2991aa0/d; +L_0x2991b20/d .functor AND 1, L_0x29920b0, L_0x2991aa0, C4<1>, C4<1>; +L_0x2991b20 .delay (20000,20000,20000) L_0x2991b20/d; +L_0x2991e30/d .functor AND 1, C4<0>, L_0x29d1680, C4<1>, C4<1>; +L_0x2991e30 .delay (20000,20000,20000) L_0x2991e30/d; +L_0x2991ed0/d .functor OR 1, L_0x2991b20, L_0x2991e30, C4<0>, C4<0>; +L_0x2991ed0 .delay (20000,20000,20000) L_0x2991ed0/d; +v0x2934720_0 .alias "S", 0 0, v0x293b720_0; +v0x29347c0_0 .net "in0", 0 0, L_0x29920b0; 1 drivers +v0x2934860_0 .net "in1", 0 0, C4<0>; 1 drivers +v0x2934900_0 .net "nS", 0 0, L_0x2991aa0; 1 drivers +v0x2934980_0 .net "out0", 0 0, L_0x2991b20; 1 drivers +v0x2934a20_0 .net "out1", 0 0, L_0x2991e30; 1 drivers +v0x2934b00_0 .net "outfinal", 0 0, L_0x2991ed0; 1 drivers +S_0x29340b0 .scope module, "setSLTres3" "TwoInMux" 3 336, 3 109, S_0x2933f40; + .timescale -9 -12; +L_0x2991d40/d .functor NOT 1, L_0x29d1680, C4<0>, C4<0>, C4<0>; +L_0x2991d40 .delay (10000,10000,10000) L_0x2991d40/d; +L_0x2992330/d .functor AND 1, L_0x29926c0, L_0x2991d40, C4<1>, C4<1>; +L_0x2992330 .delay (20000,20000,20000) L_0x2992330/d; +L_0x2992440/d .functor AND 1, L_0x29921a0, L_0x29d1680, C4<1>, C4<1>; +L_0x2992440 .delay (20000,20000,20000) L_0x2992440/d; +L_0x29924e0/d .functor OR 1, L_0x2992330, L_0x2992440, C4<0>, C4<0>; +L_0x29924e0 .delay (20000,20000,20000) L_0x29924e0/d; +v0x29341a0_0 .alias "S", 0 0, v0x293b720_0; +v0x2934220_0 .net "in0", 0 0, L_0x29926c0; 1 drivers +v0x29342c0_0 .net "in1", 0 0, L_0x29921a0; 1 drivers +v0x2934360_0 .net "nS", 0 0, L_0x2991d40; 1 drivers +v0x2934410_0 .net "out0", 0 0, L_0x2992330; 1 drivers +v0x29344b0_0 .net "out1", 0 0, L_0x2992440; 1 drivers +v0x2934590_0 .net "outfinal", 0 0, L_0x29924e0; 1 drivers +S_0x29322c0 .scope generate, "sltbits[4]" "sltbits[4]" 3 332, 3 332, S_0x28e1a50; + .timescale -9 -12; +P_0x2931cd8 .param/l "i" 3 332, +C4<0100>; +S_0x2932f20 .scope module, "attempt" "MiddleAddSubSLT" 3 334, 3 189, S_0x29322c0; + .timescale -9 -12; +L_0x298fe50/d .functor NOT 1, L_0x2993ca0, C4<0>, C4<0>, C4<0>; +L_0x298fe50 .delay (10000,10000,10000) L_0x298fe50/d; +L_0x298f470/d .functor NOT 1, L_0x2993070, C4<0>, C4<0>, C4<0>; +L_0x298f470 .delay (10000,10000,10000) L_0x298f470/d; +L_0x2993110/d .functor AND 1, L_0x2993250, L_0x298f470, C4<1>, C4<1>; +L_0x2993110 .delay (20000,20000,20000) L_0x2993110/d; +L_0x29932f0/d .functor XOR 1, L_0x2993960, L_0x2992e00, C4<0>, C4<0>; +L_0x29932f0 .delay (40000,40000,40000) L_0x29932f0/d; +L_0x29933e0/d .functor XOR 1, L_0x29932f0, L_0x2993b70, C4<0>, C4<0>; +L_0x29933e0 .delay (40000,40000,40000) L_0x29933e0/d; +L_0x29934d0/d .functor AND 1, L_0x2993960, L_0x2992e00, C4<1>, C4<1>; +L_0x29934d0 .delay (20000,20000,20000) L_0x29934d0/d; +L_0x2993640/d .functor AND 1, L_0x29932f0, L_0x2993b70, C4<1>, C4<1>; +L_0x2993640 .delay (20000,20000,20000) L_0x2993640/d; +L_0x2993730/d .functor OR 1, L_0x29934d0, L_0x2993640, C4<0>, C4<0>; +L_0x2993730 .delay (20000,20000,20000) L_0x2993730/d; +v0x29335a0_0 .net "A", 0 0, L_0x2993960; 1 drivers +v0x2933660_0 .net "AandB", 0 0, L_0x29934d0; 1 drivers +v0x2933700_0 .net "AddSubSLTSum", 0 0, L_0x29933e0; 1 drivers +v0x29337a0_0 .net "AxorB", 0 0, L_0x29932f0; 1 drivers +v0x2933820_0 .net "B", 0 0, L_0x2993ca0; 1 drivers +v0x29338d0_0 .net "BornB", 0 0, L_0x2992e00; 1 drivers +v0x2933990_0 .net "CINandAxorB", 0 0, L_0x2993640; 1 drivers +v0x2933a10_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x2933a90_0 .net *"_s3", 0 0, L_0x2993070; 1 drivers +v0x2933b10_0 .net *"_s5", 0 0, L_0x2993250; 1 drivers +v0x2933bb0_0 .net "carryin", 0 0, L_0x2993b70; 1 drivers +v0x2933c50_0 .net "carryout", 0 0, L_0x2993730; 1 drivers +v0x2933cf0_0 .net "nB", 0 0, L_0x298fe50; 1 drivers +v0x2933da0_0 .net "nCmd2", 0 0, L_0x298f470; 1 drivers +v0x2933ea0_0 .net "subtract", 0 0, L_0x2993110; 1 drivers +L_0x2992fd0 .part v0x2960210_0, 0, 1; +L_0x2993070 .part v0x2960210_0, 2, 1; +L_0x2993250 .part v0x2960210_0, 0, 1; +S_0x2933010 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x2932f20; + .timescale -9 -12; +L_0x2992b20/d .functor NOT 1, L_0x2992fd0, C4<0>, C4<0>, C4<0>; +L_0x2992b20 .delay (10000,10000,10000) L_0x2992b20/d; +L_0x2992be0/d .functor AND 1, L_0x2993ca0, L_0x2992b20, C4<1>, C4<1>; +L_0x2992be0 .delay (20000,20000,20000) L_0x2992be0/d; +L_0x2992cf0/d .functor AND 1, L_0x298fe50, L_0x2992fd0, C4<1>, C4<1>; +L_0x2992cf0 .delay (20000,20000,20000) L_0x2992cf0/d; +L_0x2992e00/d .functor OR 1, L_0x2992be0, L_0x2992cf0, C4<0>, C4<0>; +L_0x2992e00 .delay (20000,20000,20000) L_0x2992e00/d; +v0x2933100_0 .net "S", 0 0, L_0x2992fd0; 1 drivers +v0x29331c0_0 .alias "in0", 0 0, v0x2933820_0; +v0x2933260_0 .alias "in1", 0 0, v0x2933cf0_0; +v0x2933300_0 .net "nS", 0 0, L_0x2992b20; 1 drivers +v0x2933380_0 .net "out0", 0 0, L_0x2992be0; 1 drivers +v0x2933420_0 .net "out1", 0 0, L_0x2992cf0; 1 drivers +v0x2933500_0 .alias "outfinal", 0 0, v0x29338d0_0; +S_0x29329b0 .scope module, "setSLTres2" "TwoInMux" 3 335, 3 109, S_0x29322c0; + .timescale -9 -12; +L_0x2993a00/d .functor NOT 1, L_0x29d1680, C4<0>, C4<0>, C4<0>; +L_0x2993a00 .delay (10000,10000,10000) L_0x2993a00/d; +L_0x2993c10/d .functor AND 1, L_0x2993dd0, L_0x2993a00, C4<1>, C4<1>; +L_0x2993c10 .delay (20000,20000,20000) L_0x2993c10/d; +L_0x2994020/d .functor AND 1, C4<0>, L_0x29d1680, C4<1>, C4<1>; +L_0x2994020 .delay (20000,20000,20000) L_0x2994020/d; +L_0x29940c0/d .functor OR 1, L_0x2993c10, L_0x2994020, C4<0>, C4<0>; +L_0x29940c0 .delay (20000,20000,20000) L_0x29940c0/d; +v0x2932aa0_0 .alias "S", 0 0, v0x293b720_0; +v0x2932b40_0 .net "in0", 0 0, L_0x2993dd0; 1 drivers +v0x2932be0_0 .net "in1", 0 0, C4<0>; 1 drivers +v0x2932c80_0 .net "nS", 0 0, L_0x2993a00; 1 drivers +v0x2932d00_0 .net "out0", 0 0, L_0x2993c10; 1 drivers +v0x2932da0_0 .net "out1", 0 0, L_0x2994020; 1 drivers +v0x2932e80_0 .net "outfinal", 0 0, L_0x29940c0; 1 drivers +S_0x2932430 .scope module, "setSLTres3" "TwoInMux" 3 336, 3 109, S_0x29322c0; + .timescale -9 -12; +L_0x2994500/d .functor NOT 1, L_0x29d1680, C4<0>, C4<0>, C4<0>; +L_0x2994500 .delay (10000,10000,10000) L_0x2994500/d; +L_0x29945d0/d .functor AND 1, L_0x29942a0, L_0x2994500, C4<1>, C4<1>; +L_0x29945d0 .delay (20000,20000,20000) L_0x29945d0/d; +L_0x29946e0/d .functor AND 1, L_0x2994ac0, L_0x29d1680, C4<1>, C4<1>; +L_0x29946e0 .delay (20000,20000,20000) L_0x29946e0/d; +L_0x2994780/d .functor OR 1, L_0x29945d0, L_0x29946e0, C4<0>, C4<0>; +L_0x2994780 .delay (20000,20000,20000) L_0x2994780/d; +v0x2932520_0 .alias "S", 0 0, v0x293b720_0; +v0x29325a0_0 .net "in0", 0 0, L_0x29942a0; 1 drivers +v0x2932640_0 .net "in1", 0 0, L_0x2994ac0; 1 drivers +v0x29326e0_0 .net "nS", 0 0, L_0x2994500; 1 drivers +v0x2932790_0 .net "out0", 0 0, L_0x29945d0; 1 drivers +v0x2932830_0 .net "out1", 0 0, L_0x29946e0; 1 drivers +v0x2932910_0 .net "outfinal", 0 0, L_0x2994780; 1 drivers +S_0x2930600 .scope generate, "sltbits[5]" "sltbits[5]" 3 332, 3 332, S_0x28e1a50; + .timescale -9 -12; +P_0x29306f8 .param/l "i" 3 332, +C4<0101>; +S_0x29312a0 .scope module, "attempt" "MiddleAddSubSLT" 3 334, 3 189, S_0x2930600; + .timescale -9 -12; +L_0x2994960/d .functor NOT 1, L_0x2995d50, C4<0>, C4<0>, C4<0>; +L_0x2994960 .delay (10000,10000,10000) L_0x2994960/d; +L_0x2995290/d .functor NOT 1, L_0x2995350, C4<0>, C4<0>, C4<0>; +L_0x2995290 .delay (10000,10000,10000) L_0x2995290/d; +L_0x29953f0/d .functor AND 1, L_0x2995530, L_0x2995290, C4<1>, C4<1>; +L_0x29953f0 .delay (20000,20000,20000) L_0x29953f0/d; +L_0x29955d0/d .functor XOR 1, L_0x2995ed0, L_0x2995020, C4<0>, C4<0>; +L_0x29955d0 .delay (40000,40000,40000) L_0x29955d0/d; +L_0x29956c0/d .functor XOR 1, L_0x29955d0, L_0x2996100, C4<0>, C4<0>; +L_0x29956c0 .delay (40000,40000,40000) L_0x29956c0/d; +L_0x29957b0/d .functor AND 1, L_0x2995ed0, L_0x2995020, C4<1>, C4<1>; +L_0x29957b0 .delay (20000,20000,20000) L_0x29957b0/d; +L_0x2995920/d .functor AND 1, L_0x29955d0, L_0x2996100, C4<1>, C4<1>; +L_0x2995920 .delay (20000,20000,20000) L_0x2995920/d; +L_0x2995a10/d .functor OR 1, L_0x29957b0, L_0x2995920, C4<0>, C4<0>; +L_0x2995a10 .delay (20000,20000,20000) L_0x2995a10/d; +v0x2931920_0 .net "A", 0 0, L_0x2995ed0; 1 drivers +v0x29319e0_0 .net "AandB", 0 0, L_0x29957b0; 1 drivers +v0x2931a80_0 .net "AddSubSLTSum", 0 0, L_0x29956c0; 1 drivers +v0x2931b20_0 .net "AxorB", 0 0, L_0x29955d0; 1 drivers +v0x2931ba0_0 .net "B", 0 0, L_0x2995d50; 1 drivers +v0x2931c50_0 .net "BornB", 0 0, L_0x2995020; 1 drivers +v0x2931d10_0 .net "CINandAxorB", 0 0, L_0x2995920; 1 drivers +v0x2931d90_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x2931e10_0 .net *"_s3", 0 0, L_0x2995350; 1 drivers +v0x2931e90_0 .net *"_s5", 0 0, L_0x2995530; 1 drivers +v0x2931f30_0 .net "carryin", 0 0, L_0x2996100; 1 drivers +v0x2931fd0_0 .net "carryout", 0 0, L_0x2995a10; 1 drivers +v0x2932070_0 .net "nB", 0 0, L_0x2994960; 1 drivers +v0x2932120_0 .net "nCmd2", 0 0, L_0x2995290; 1 drivers +v0x2932220_0 .net "subtract", 0 0, L_0x29953f0; 1 drivers +L_0x29951f0 .part v0x2960210_0, 0, 1; +L_0x2995350 .part v0x2960210_0, 2, 1; +L_0x2995530 .part v0x2960210_0, 0, 1; +S_0x2931390 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x29312a0; + .timescale -9 -12; +L_0x2994d40/d .functor NOT 1, L_0x29951f0, C4<0>, C4<0>, C4<0>; +L_0x2994d40 .delay (10000,10000,10000) L_0x2994d40/d; +L_0x2994e00/d .functor AND 1, L_0x2995d50, L_0x2994d40, C4<1>, C4<1>; +L_0x2994e00 .delay (20000,20000,20000) L_0x2994e00/d; +L_0x2994f10/d .functor AND 1, L_0x2994960, L_0x29951f0, C4<1>, C4<1>; +L_0x2994f10 .delay (20000,20000,20000) L_0x2994f10/d; +L_0x2995020/d .functor OR 1, L_0x2994e00, L_0x2994f10, C4<0>, C4<0>; +L_0x2995020 .delay (20000,20000,20000) L_0x2995020/d; +v0x2931480_0 .net "S", 0 0, L_0x29951f0; 1 drivers +v0x2931540_0 .alias "in0", 0 0, v0x2931ba0_0; +v0x29315e0_0 .alias "in1", 0 0, v0x2932070_0; +v0x2931680_0 .net "nS", 0 0, L_0x2994d40; 1 drivers +v0x2931700_0 .net "out0", 0 0, L_0x2994e00; 1 drivers +v0x29317a0_0 .net "out1", 0 0, L_0x2994f10; 1 drivers +v0x2931880_0 .alias "outfinal", 0 0, v0x2931c50_0; +S_0x2930d30 .scope module, "setSLTres2" "TwoInMux" 3 335, 3 109, S_0x2930600; + .timescale -9 -12; +L_0x2994c50/d .functor NOT 1, L_0x29d1680, C4<0>, C4<0>, C4<0>; +L_0x2994c50 .delay (10000,10000,10000) L_0x2994c50/d; +L_0x2995f70/d .functor AND 1, L_0x2996560, L_0x2994c50, C4<1>, C4<1>; +L_0x2995f70 .delay (20000,20000,20000) L_0x2995f70/d; +L_0x2996080/d .functor AND 1, C4<0>, L_0x29d1680, C4<1>, C4<1>; +L_0x2996080 .delay (20000,20000,20000) L_0x2996080/d; +L_0x2996380/d .functor OR 1, L_0x2995f70, L_0x2996080, C4<0>, C4<0>; +L_0x2996380 .delay (20000,20000,20000) L_0x2996380/d; +v0x2930e20_0 .alias "S", 0 0, v0x293b720_0; +v0x2930ec0_0 .net "in0", 0 0, L_0x2996560; 1 drivers +v0x2930f60_0 .net "in1", 0 0, C4<0>; 1 drivers +v0x2931000_0 .net "nS", 0 0, L_0x2994c50; 1 drivers +v0x2931080_0 .net "out0", 0 0, L_0x2995f70; 1 drivers +v0x2931120_0 .net "out1", 0 0, L_0x2996080; 1 drivers +v0x2931200_0 .net "outfinal", 0 0, L_0x2996380; 1 drivers +S_0x29307b0 .scope module, "setSLTres3" "TwoInMux" 3 336, 3 109, S_0x2930600; + .timescale -9 -12; +L_0x2996270/d .functor NOT 1, L_0x29d1680, C4<0>, C4<0>, C4<0>; +L_0x2996270 .delay (10000,10000,10000) L_0x2996270/d; +L_0x2996850/d .functor AND 1, L_0x2996cd0, L_0x2996270, C4<1>, C4<1>; +L_0x2996850 .delay (20000,20000,20000) L_0x2996850/d; +L_0x2996940/d .functor AND 1, L_0x2996650, L_0x29d1680, C4<1>, C4<1>; +L_0x2996940 .delay (20000,20000,20000) L_0x2996940/d; +L_0x29969e0/d .functor OR 1, L_0x2996850, L_0x2996940, C4<0>, C4<0>; +L_0x29969e0 .delay (20000,20000,20000) L_0x29969e0/d; +v0x29308a0_0 .alias "S", 0 0, v0x293b720_0; +v0x2930920_0 .net "in0", 0 0, L_0x2996cd0; 1 drivers +v0x29309c0_0 .net "in1", 0 0, L_0x2996650; 1 drivers +v0x2930a60_0 .net "nS", 0 0, L_0x2996270; 1 drivers +v0x2930b10_0 .net "out0", 0 0, L_0x2996850; 1 drivers +v0x2930bb0_0 .net "out1", 0 0, L_0x2996940; 1 drivers +v0x2930c90_0 .net "outfinal", 0 0, L_0x29969e0; 1 drivers +S_0x292e9b0 .scope generate, "sltbits[6]" "sltbits[6]" 3 332, 3 332, S_0x28e1a50; + .timescale -9 -12; +P_0x292e3c8 .param/l "i" 3 332, +C4<0110>; +S_0x292f610 .scope module, "attempt" "MiddleAddSubSLT" 3 334, 3 189, S_0x292e9b0; + .timescale -9 -12; +L_0x2996740/d .functor NOT 1, L_0x2891bb0, C4<0>, C4<0>, C4<0>; +L_0x2996740 .delay (10000,10000,10000) L_0x2996740/d; +L_0x2997560/d .functor NOT 1, L_0x2997620, C4<0>, C4<0>, C4<0>; +L_0x2997560 .delay (10000,10000,10000) L_0x2997560/d; +L_0x29976c0/d .functor AND 1, L_0x2997800, L_0x2997560, C4<1>, C4<1>; +L_0x29976c0 .delay (20000,20000,20000) L_0x29976c0/d; +L_0x2891460/d .functor XOR 1, L_0x2891b10, L_0x29972f0, C4<0>, C4<0>; +L_0x2891460 .delay (40000,40000,40000) L_0x2891460/d; +L_0x2891550/d .functor XOR 1, L_0x2891460, L_0x2891f20, C4<0>, C4<0>; +L_0x2891550 .delay (40000,40000,40000) L_0x2891550/d; +L_0x2891640/d .functor AND 1, L_0x2891b10, L_0x29972f0, C4<1>, C4<1>; +L_0x2891640 .delay (20000,20000,20000) L_0x2891640/d; +L_0x28917b0/d .functor AND 1, L_0x2891460, L_0x2891f20, C4<1>, C4<1>; +L_0x28917b0 .delay (20000,20000,20000) L_0x28917b0/d; +L_0x28918a0/d .functor OR 1, L_0x2891640, L_0x28917b0, C4<0>, C4<0>; +L_0x28918a0 .delay (20000,20000,20000) L_0x28918a0/d; +v0x292fc90_0 .net "A", 0 0, L_0x2891b10; 1 drivers +v0x292fd50_0 .net "AandB", 0 0, L_0x2891640; 1 drivers +v0x292fdf0_0 .net "AddSubSLTSum", 0 0, L_0x2891550; 1 drivers +v0x292fe90_0 .net "AxorB", 0 0, L_0x2891460; 1 drivers +v0x292ff10_0 .net "B", 0 0, L_0x2891bb0; 1 drivers +v0x292ffc0_0 .net "BornB", 0 0, L_0x29972f0; 1 drivers +v0x2930040_0 .net "CINandAxorB", 0 0, L_0x28917b0; 1 drivers +v0x29300c0_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x2930140_0 .net *"_s3", 0 0, L_0x2997620; 1 drivers +v0x29301c0_0 .net *"_s5", 0 0, L_0x2997800; 1 drivers +v0x2930240_0 .net "carryin", 0 0, L_0x2891f20; 1 drivers +v0x29302c0_0 .net "carryout", 0 0, L_0x28918a0; 1 drivers +v0x29303b0_0 .net "nB", 0 0, L_0x2996740; 1 drivers +v0x2930460_0 .net "nCmd2", 0 0, L_0x2997560; 1 drivers +v0x2930560_0 .net "subtract", 0 0, L_0x29976c0; 1 drivers +L_0x29974c0 .part v0x2960210_0, 0, 1; +L_0x2997620 .part v0x2960210_0, 2, 1; +L_0x2997800 .part v0x2960210_0, 0, 1; +S_0x292f700 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x292f610; + .timescale -9 -12; +L_0x2997010/d .functor NOT 1, L_0x29974c0, C4<0>, C4<0>, C4<0>; +L_0x2997010 .delay (10000,10000,10000) L_0x2997010/d; +L_0x29970d0/d .functor AND 1, L_0x2891bb0, L_0x2997010, C4<1>, C4<1>; +L_0x29970d0 .delay (20000,20000,20000) L_0x29970d0/d; +L_0x29971e0/d .functor AND 1, L_0x2996740, L_0x29974c0, C4<1>, C4<1>; +L_0x29971e0 .delay (20000,20000,20000) L_0x29971e0/d; +L_0x29972f0/d .functor OR 1, L_0x29970d0, L_0x29971e0, C4<0>, C4<0>; +L_0x29972f0 .delay (20000,20000,20000) L_0x29972f0/d; +v0x292f7f0_0 .net "S", 0 0, L_0x29974c0; 1 drivers +v0x292f8b0_0 .alias "in0", 0 0, v0x292ff10_0; +v0x292f950_0 .alias "in1", 0 0, v0x29303b0_0; +v0x292f9f0_0 .net "nS", 0 0, L_0x2997010; 1 drivers +v0x292fa70_0 .net "out0", 0 0, L_0x29970d0; 1 drivers +v0x292fb10_0 .net "out1", 0 0, L_0x29971e0; 1 drivers +v0x292fbf0_0 .alias "outfinal", 0 0, v0x292ffc0_0; +S_0x292f0a0 .scope module, "setSLTres2" "TwoInMux" 3 335, 3 109, S_0x292e9b0; + .timescale -9 -12; +L_0x2891fc0/d .functor NOT 1, L_0x29d1680, C4<0>, C4<0>, C4<0>; +L_0x2891fc0 .delay (10000,10000,10000) L_0x2891fc0/d; +L_0x2892060/d .functor AND 1, L_0x29927b0, L_0x2891fc0, C4<1>, C4<1>; +L_0x2892060 .delay (20000,20000,20000) L_0x2892060/d; +L_0x2892170/d .functor AND 1, C4<0>, L_0x29d1680, C4<1>, C4<1>; +L_0x2892170 .delay (20000,20000,20000) L_0x2892170/d; +L_0x2892210/d .functor OR 1, L_0x2892060, L_0x2892170, C4<0>, C4<0>; +L_0x2892210 .delay (20000,20000,20000) L_0x2892210/d; +v0x292f190_0 .alias "S", 0 0, v0x293b720_0; +v0x292f230_0 .net "in0", 0 0, L_0x29927b0; 1 drivers +v0x292f2d0_0 .net "in1", 0 0, C4<0>; 1 drivers +v0x292f370_0 .net "nS", 0 0, L_0x2891fc0; 1 drivers +v0x292f3f0_0 .net "out0", 0 0, L_0x2892060; 1 drivers +v0x292f490_0 .net "out1", 0 0, L_0x2892170; 1 drivers +v0x292f570_0 .net "outfinal", 0 0, L_0x2892210; 1 drivers +S_0x292eb20 .scope module, "setSLTres3" "TwoInMux" 3 336, 3 109, S_0x292e9b0; + .timescale -9 -12; +L_0x2891dc0/d .functor NOT 1, L_0x29d1680, C4<0>, C4<0>, C4<0>; +L_0x2891dc0 .delay (10000,10000,10000) L_0x2891dc0/d; +L_0x2891eb0/d .functor AND 1, L_0x2892600, L_0x2891dc0, C4<1>, C4<1>; +L_0x2891eb0 .delay (20000,20000,20000) L_0x2891eb0/d; +L_0x2892890/d .functor AND 1, L_0x28926f0, L_0x29d1680, C4<1>, C4<1>; +L_0x2892890 .delay (20000,20000,20000) L_0x2892890/d; +L_0x2892930/d .functor OR 1, L_0x2891eb0, L_0x2892890, C4<0>, C4<0>; +L_0x2892930 .delay (20000,20000,20000) L_0x2892930/d; +v0x292ec10_0 .alias "S", 0 0, v0x293b720_0; +v0x292ec90_0 .net "in0", 0 0, L_0x2892600; 1 drivers +v0x292ed30_0 .net "in1", 0 0, L_0x28926f0; 1 drivers +v0x292edd0_0 .net "nS", 0 0, L_0x2891dc0; 1 drivers +v0x292ee80_0 .net "out0", 0 0, L_0x2891eb0; 1 drivers +v0x292ef20_0 .net "out1", 0 0, L_0x2892890; 1 drivers +v0x292f000_0 .net "outfinal", 0 0, L_0x2892930; 1 drivers +S_0x292cd30 .scope generate, "sltbits[7]" "sltbits[7]" 3 332, 3 332, S_0x28e1a50; + .timescale -9 -12; +P_0x292c748 .param/l "i" 3 332, +C4<0111>; +S_0x292d990 .scope module, "attempt" "MiddleAddSubSLT" 3 334, 3 189, S_0x292cd30; + .timescale -9 -12; +L_0x2892d30/d .functor NOT 1, L_0x299c530, C4<0>, C4<0>, C4<0>; +L_0x2892d30 .delay (10000,10000,10000) L_0x2892d30/d; +L_0x299b8b0/d .functor NOT 1, L_0x299b910, C4<0>, C4<0>, C4<0>; +L_0x299b8b0 .delay (10000,10000,10000) L_0x299b8b0/d; +L_0x299b9b0/d .functor AND 1, L_0x299baf0, L_0x299b8b0, C4<1>, C4<1>; +L_0x299b9b0 .delay (20000,20000,20000) L_0x299b9b0/d; +L_0x299bb90/d .functor XOR 1, L_0x2892c00, L_0x28931c0, C4<0>, C4<0>; +L_0x299bb90 .delay (40000,40000,40000) L_0x299bb90/d; +L_0x299bc80/d .functor XOR 1, L_0x299bb90, L_0x299c5d0, C4<0>, C4<0>; +L_0x299bc80 .delay (40000,40000,40000) L_0x299bc80/d; +L_0x299bd70/d .functor AND 1, L_0x2892c00, L_0x28931c0, C4<1>, C4<1>; +L_0x299bd70 .delay (20000,20000,20000) L_0x299bd70/d; +L_0x299bee0/d .functor AND 1, L_0x299bb90, L_0x299c5d0, C4<1>, C4<1>; +L_0x299bee0 .delay (20000,20000,20000) L_0x299bee0/d; +L_0x299bfd0/d .functor OR 1, L_0x299bd70, L_0x299bee0, C4<0>, C4<0>; +L_0x299bfd0 .delay (20000,20000,20000) L_0x299bfd0/d; +v0x292e010_0 .net "A", 0 0, L_0x2892c00; 1 drivers +v0x292e0d0_0 .net "AandB", 0 0, L_0x299bd70; 1 drivers +v0x292e170_0 .net "AddSubSLTSum", 0 0, L_0x299bc80; 1 drivers +v0x292e210_0 .net "AxorB", 0 0, L_0x299bb90; 1 drivers +v0x292e290_0 .net "B", 0 0, L_0x299c530; 1 drivers +v0x292e340_0 .net "BornB", 0 0, L_0x28931c0; 1 drivers +v0x292e400_0 .net "CINandAxorB", 0 0, L_0x299bee0; 1 drivers +v0x292e480_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x292e500_0 .net *"_s3", 0 0, L_0x299b910; 1 drivers +v0x292e580_0 .net *"_s5", 0 0, L_0x299baf0; 1 drivers +v0x292e620_0 .net "carryin", 0 0, L_0x299c5d0; 1 drivers +v0x292e6c0_0 .net "carryout", 0 0, L_0x299bfd0; 1 drivers +v0x292e760_0 .net "nB", 0 0, L_0x2892d30; 1 drivers +v0x292e810_0 .net "nCmd2", 0 0, L_0x299b8b0; 1 drivers +v0x292e910_0 .net "subtract", 0 0, L_0x299b9b0; 1 drivers +L_0x2893390 .part v0x2960210_0, 0, 1; +L_0x299b910 .part v0x2960210_0, 2, 1; +L_0x299baf0 .part v0x2960210_0, 0, 1; +S_0x292da80 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x292d990; + .timescale -9 -12; +L_0x2892ee0/d .functor NOT 1, L_0x2893390, C4<0>, C4<0>, C4<0>; +L_0x2892ee0 .delay (10000,10000,10000) L_0x2892ee0/d; +L_0x2892fa0/d .functor AND 1, L_0x299c530, L_0x2892ee0, C4<1>, C4<1>; +L_0x2892fa0 .delay (20000,20000,20000) L_0x2892fa0/d; +L_0x28930b0/d .functor AND 1, L_0x2892d30, L_0x2893390, C4<1>, C4<1>; +L_0x28930b0 .delay (20000,20000,20000) L_0x28930b0/d; +L_0x28931c0/d .functor OR 1, L_0x2892fa0, L_0x28930b0, C4<0>, C4<0>; +L_0x28931c0 .delay (20000,20000,20000) L_0x28931c0/d; +v0x292db70_0 .net "S", 0 0, L_0x2893390; 1 drivers +v0x292dc30_0 .alias "in0", 0 0, v0x292e290_0; +v0x292dcd0_0 .alias "in1", 0 0, v0x292e760_0; +v0x292dd70_0 .net "nS", 0 0, L_0x2892ee0; 1 drivers +v0x292ddf0_0 .net "out0", 0 0, L_0x2892fa0; 1 drivers +v0x292de90_0 .net "out1", 0 0, L_0x28930b0; 1 drivers +v0x292df70_0 .alias "outfinal", 0 0, v0x292e340_0; +S_0x292d420 .scope module, "setSLTres2" "TwoInMux" 3 335, 3 109, S_0x292cd30; + .timescale -9 -12; +L_0x299c2f0/d .functor NOT 1, L_0x29d1680, C4<0>, C4<0>, C4<0>; +L_0x299c2f0 .delay (10000,10000,10000) L_0x299c2f0/d; +L_0x299c390/d .functor AND 1, L_0x299cae0, L_0x299c2f0, C4<1>, C4<1>; +L_0x299c390 .delay (20000,20000,20000) L_0x299c390/d; +L_0x299c4a0/d .functor AND 1, C4<0>, L_0x29d1680, C4<1>, C4<1>; +L_0x299c4a0 .delay (20000,20000,20000) L_0x299c4a0/d; +L_0x299c900/d .functor OR 1, L_0x299c390, L_0x299c4a0, C4<0>, C4<0>; +L_0x299c900 .delay (20000,20000,20000) L_0x299c900/d; +v0x292d510_0 .alias "S", 0 0, v0x293b720_0; +v0x292d5b0_0 .net "in0", 0 0, L_0x299cae0; 1 drivers +v0x292d650_0 .net "in1", 0 0, C4<0>; 1 drivers +v0x292d6f0_0 .net "nS", 0 0, L_0x299c2f0; 1 drivers +v0x292d770_0 .net "out0", 0 0, L_0x299c390; 1 drivers +v0x292d810_0 .net "out1", 0 0, L_0x299c4a0; 1 drivers +v0x292d8f0_0 .net "outfinal", 0 0, L_0x299c900; 1 drivers +S_0x292cea0 .scope module, "setSLTres3" "TwoInMux" 3 336, 3 109, S_0x292cd30; + .timescale -9 -12; +L_0x299c750/d .functor NOT 1, L_0x29d1680, C4<0>, C4<0>, C4<0>; +L_0x299c750 .delay (10000,10000,10000) L_0x299c750/d; +L_0x299c820/d .functor AND 1, L_0x299d100, L_0x299c750, C4<1>, C4<1>; +L_0x299c820 .delay (20000,20000,20000) L_0x299c820/d; +L_0x299ce80/d .functor AND 1, L_0x299cbd0, L_0x29d1680, C4<1>, C4<1>; +L_0x299ce80 .delay (20000,20000,20000) L_0x299ce80/d; +L_0x299cf20/d .functor OR 1, L_0x299c820, L_0x299ce80, C4<0>, C4<0>; +L_0x299cf20 .delay (20000,20000,20000) L_0x299cf20/d; +v0x292cf90_0 .alias "S", 0 0, v0x293b720_0; +v0x292d010_0 .net "in0", 0 0, L_0x299d100; 1 drivers +v0x292d0b0_0 .net "in1", 0 0, L_0x299cbd0; 1 drivers +v0x292d150_0 .net "nS", 0 0, L_0x299c750; 1 drivers +v0x292d200_0 .net "out0", 0 0, L_0x299c820; 1 drivers +v0x292d2a0_0 .net "out1", 0 0, L_0x299ce80; 1 drivers +v0x292d380_0 .net "outfinal", 0 0, L_0x299cf20; 1 drivers +S_0x292b0b0 .scope generate, "sltbits[8]" "sltbits[8]" 3 332, 3 332, S_0x28e1a50; + .timescale -9 -12; +P_0x292aac8 .param/l "i" 3 332, +C4<01000>; +S_0x292bd10 .scope module, "attempt" "MiddleAddSubSLT" 3 334, 3 189, S_0x292b0b0; + .timescale -9 -12; +L_0x299ccc0/d .functor NOT 1, L_0x299e720, C4<0>, C4<0>, C4<0>; +L_0x299ccc0 .delay (10000,10000,10000) L_0x299ccc0/d; +L_0x299da20/d .functor NOT 1, L_0x299dae0, C4<0>, C4<0>, C4<0>; +L_0x299da20 .delay (10000,10000,10000) L_0x299da20/d; +L_0x299db80/d .functor AND 1, L_0x299dcc0, L_0x299da20, C4<1>, C4<1>; +L_0x299db80 .delay (20000,20000,20000) L_0x299db80/d; +L_0x299dd60/d .functor XOR 1, L_0x299e680, L_0x299d7b0, C4<0>, C4<0>; +L_0x299dd60 .delay (40000,40000,40000) L_0x299dd60/d; +L_0x299de50/d .functor XOR 1, L_0x299dd60, L_0x299e3f0, C4<0>, C4<0>; +L_0x299de50 .delay (40000,40000,40000) L_0x299de50/d; +L_0x299df40/d .functor AND 1, L_0x299e680, L_0x299d7b0, C4<1>, C4<1>; +L_0x299df40 .delay (20000,20000,20000) L_0x299df40/d; +L_0x299e0b0/d .functor AND 1, L_0x299dd60, L_0x299e3f0, C4<1>, C4<1>; +L_0x299e0b0 .delay (20000,20000,20000) L_0x299e0b0/d; +L_0x299e1a0/d .functor OR 1, L_0x299df40, L_0x299e0b0, C4<0>, C4<0>; +L_0x299e1a0 .delay (20000,20000,20000) L_0x299e1a0/d; +v0x292c390_0 .net "A", 0 0, L_0x299e680; 1 drivers +v0x292c450_0 .net "AandB", 0 0, L_0x299df40; 1 drivers +v0x292c4f0_0 .net "AddSubSLTSum", 0 0, L_0x299de50; 1 drivers +v0x292c590_0 .net "AxorB", 0 0, L_0x299dd60; 1 drivers +v0x292c610_0 .net "B", 0 0, L_0x299e720; 1 drivers +v0x292c6c0_0 .net "BornB", 0 0, L_0x299d7b0; 1 drivers +v0x292c780_0 .net "CINandAxorB", 0 0, L_0x299e0b0; 1 drivers +v0x292c800_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x292c880_0 .net *"_s3", 0 0, L_0x299dae0; 1 drivers +v0x292c900_0 .net *"_s5", 0 0, L_0x299dcc0; 1 drivers +v0x292c9a0_0 .net "carryin", 0 0, L_0x299e3f0; 1 drivers +v0x292ca40_0 .net "carryout", 0 0, L_0x299e1a0; 1 drivers +v0x292cae0_0 .net "nB", 0 0, L_0x299ccc0; 1 drivers +v0x292cb90_0 .net "nCmd2", 0 0, L_0x299da20; 1 drivers +v0x292cc90_0 .net "subtract", 0 0, L_0x299db80; 1 drivers +L_0x299d980 .part v0x2960210_0, 0, 1; +L_0x299dae0 .part v0x2960210_0, 2, 1; +L_0x299dcc0 .part v0x2960210_0, 0, 1; +S_0x292be00 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x292bd10; + .timescale -9 -12; +L_0x299d4d0/d .functor NOT 1, L_0x299d980, C4<0>, C4<0>, C4<0>; +L_0x299d4d0 .delay (10000,10000,10000) L_0x299d4d0/d; +L_0x299d590/d .functor AND 1, L_0x299e720, L_0x299d4d0, C4<1>, C4<1>; +L_0x299d590 .delay (20000,20000,20000) L_0x299d590/d; +L_0x299d6a0/d .functor AND 1, L_0x299ccc0, L_0x299d980, C4<1>, C4<1>; +L_0x299d6a0 .delay (20000,20000,20000) L_0x299d6a0/d; +L_0x299d7b0/d .functor OR 1, L_0x299d590, L_0x299d6a0, C4<0>, C4<0>; +L_0x299d7b0 .delay (20000,20000,20000) L_0x299d7b0/d; +v0x292bef0_0 .net "S", 0 0, L_0x299d980; 1 drivers +v0x292bfb0_0 .alias "in0", 0 0, v0x292c610_0; +v0x292c050_0 .alias "in1", 0 0, v0x292cae0_0; +v0x292c0f0_0 .net "nS", 0 0, L_0x299d4d0; 1 drivers +v0x292c170_0 .net "out0", 0 0, L_0x299d590; 1 drivers +v0x292c210_0 .net "out1", 0 0, L_0x299d6a0; 1 drivers +v0x292c2f0_0 .alias "outfinal", 0 0, v0x292c6c0_0; +S_0x292b7a0 .scope module, "setSLTres2" "TwoInMux" 3 335, 3 109, S_0x292b0b0; + .timescale -9 -12; +L_0x2993f10/d .functor NOT 1, L_0x29d1680, C4<0>, C4<0>, C4<0>; +L_0x2993f10 .delay (10000,10000,10000) L_0x2993f10/d; +L_0x2993fb0/d .functor AND 1, L_0x299e7c0, L_0x2993f10, C4<1>, C4<1>; +L_0x2993fb0 .delay (20000,20000,20000) L_0x2993fb0/d; +L_0x299e540/d .functor AND 1, C4<0>, L_0x29d1680, C4<1>, C4<1>; +L_0x299e540 .delay (20000,20000,20000) L_0x299e540/d; +L_0x299e5e0/d .functor OR 1, L_0x2993fb0, L_0x299e540, C4<0>, C4<0>; +L_0x299e5e0 .delay (20000,20000,20000) L_0x299e5e0/d; +v0x292b890_0 .alias "S", 0 0, v0x293b720_0; +v0x292b930_0 .net "in0", 0 0, L_0x299e7c0; 1 drivers +v0x292b9d0_0 .net "in1", 0 0, C4<0>; 1 drivers +v0x292ba70_0 .net "nS", 0 0, L_0x2993f10; 1 drivers +v0x292baf0_0 .net "out0", 0 0, L_0x2993fb0; 1 drivers +v0x292bb90_0 .net "out1", 0 0, L_0x299e540; 1 drivers +v0x292bc70_0 .net "outfinal", 0 0, L_0x299e5e0; 1 drivers +S_0x292b220 .scope module, "setSLTres3" "TwoInMux" 3 336, 3 109, S_0x292b0b0; + .timescale -9 -12; +L_0x2994480/d .functor NOT 1, L_0x29d1680, C4<0>, C4<0>, C4<0>; +L_0x2994480 .delay (10000,10000,10000) L_0x2994480/d; +L_0x299e940/d .functor AND 1, L_0x299edb0, L_0x2994480, C4<1>, C4<1>; +L_0x299e940 .delay (20000,20000,20000) L_0x299e940/d; +L_0x299ea00/d .functor AND 1, L_0x299eea0, L_0x29d1680, C4<1>, C4<1>; +L_0x299ea00 .delay (20000,20000,20000) L_0x299ea00/d; +L_0x299f300/d .functor OR 1, L_0x299e940, L_0x299ea00, C4<0>, C4<0>; +L_0x299f300 .delay (20000,20000,20000) L_0x299f300/d; +v0x292b310_0 .alias "S", 0 0, v0x293b720_0; +v0x292b390_0 .net "in0", 0 0, L_0x299edb0; 1 drivers +v0x292b430_0 .net "in1", 0 0, L_0x299eea0; 1 drivers +v0x292b4d0_0 .net "nS", 0 0, L_0x2994480; 1 drivers +v0x292b580_0 .net "out0", 0 0, L_0x299e940; 1 drivers +v0x292b620_0 .net "out1", 0 0, L_0x299ea00; 1 drivers +v0x292b700_0 .net "outfinal", 0 0, L_0x299f300; 1 drivers +S_0x2929430 .scope generate, "sltbits[9]" "sltbits[9]" 3 332, 3 332, S_0x28e1a50; + .timescale -9 -12; +P_0x2928e48 .param/l "i" 3 332, +C4<01001>; +S_0x292a090 .scope module, "attempt" "MiddleAddSubSLT" 3 334, 3 189, S_0x2929430; + .timescale -9 -12; +L_0x299ef90/d .functor NOT 1, L_0x299f670, C4<0>, C4<0>, C4<0>; +L_0x299ef90 .delay (10000,10000,10000) L_0x299ef90/d; +L_0x299fe00/d .functor NOT 1, L_0x299fec0, C4<0>, C4<0>, C4<0>; +L_0x299fe00 .delay (10000,10000,10000) L_0x299fe00/d; +L_0x299ff60/d .functor AND 1, L_0x29a00a0, L_0x299fe00, C4<1>, C4<1>; +L_0x299ff60 .delay (20000,20000,20000) L_0x299ff60/d; +L_0x29a0140/d .functor XOR 1, L_0x299f5d0, L_0x299fb90, C4<0>, C4<0>; +L_0x29a0140 .delay (40000,40000,40000) L_0x29a0140/d; +L_0x29a0230/d .functor XOR 1, L_0x29a0140, L_0x29a0bb0, C4<0>, C4<0>; +L_0x29a0230 .delay (40000,40000,40000) L_0x29a0230/d; +L_0x29a0320/d .functor AND 1, L_0x299f5d0, L_0x299fb90, C4<1>, C4<1>; +L_0x29a0320 .delay (20000,20000,20000) L_0x29a0320/d; +L_0x29a0490/d .functor AND 1, L_0x29a0140, L_0x29a0bb0, C4<1>, C4<1>; +L_0x29a0490 .delay (20000,20000,20000) L_0x29a0490/d; +L_0x29a0580/d .functor OR 1, L_0x29a0320, L_0x29a0490, C4<0>, C4<0>; +L_0x29a0580 .delay (20000,20000,20000) L_0x29a0580/d; +v0x292a710_0 .net "A", 0 0, L_0x299f5d0; 1 drivers +v0x292a7d0_0 .net "AandB", 0 0, L_0x29a0320; 1 drivers +v0x292a870_0 .net "AddSubSLTSum", 0 0, L_0x29a0230; 1 drivers +v0x292a910_0 .net "AxorB", 0 0, L_0x29a0140; 1 drivers +v0x292a990_0 .net "B", 0 0, L_0x299f670; 1 drivers +v0x292aa40_0 .net "BornB", 0 0, L_0x299fb90; 1 drivers +v0x292ab00_0 .net "CINandAxorB", 0 0, L_0x29a0490; 1 drivers +v0x292ab80_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x292ac00_0 .net *"_s3", 0 0, L_0x299fec0; 1 drivers +v0x292ac80_0 .net *"_s5", 0 0, L_0x29a00a0; 1 drivers +v0x292ad20_0 .net "carryin", 0 0, L_0x29a0bb0; 1 drivers +v0x292adc0_0 .net "carryout", 0 0, L_0x29a0580; 1 drivers +v0x292ae60_0 .net "nB", 0 0, L_0x299ef90; 1 drivers +v0x292af10_0 .net "nCmd2", 0 0, L_0x299fe00; 1 drivers +v0x292b010_0 .net "subtract", 0 0, L_0x299ff60; 1 drivers +L_0x299fd60 .part v0x2960210_0, 0, 1; +L_0x299fec0 .part v0x2960210_0, 2, 1; +L_0x29a00a0 .part v0x2960210_0, 0, 1; +S_0x292a180 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x292a090; + .timescale -9 -12; +L_0x299f8b0/d .functor NOT 1, L_0x299fd60, C4<0>, C4<0>, C4<0>; +L_0x299f8b0 .delay (10000,10000,10000) L_0x299f8b0/d; +L_0x299f970/d .functor AND 1, L_0x299f670, L_0x299f8b0, C4<1>, C4<1>; +L_0x299f970 .delay (20000,20000,20000) L_0x299f970/d; +L_0x299fa80/d .functor AND 1, L_0x299ef90, L_0x299fd60, C4<1>, C4<1>; +L_0x299fa80 .delay (20000,20000,20000) L_0x299fa80/d; +L_0x299fb90/d .functor OR 1, L_0x299f970, L_0x299fa80, C4<0>, C4<0>; +L_0x299fb90 .delay (20000,20000,20000) L_0x299fb90/d; +v0x292a270_0 .net "S", 0 0, L_0x299fd60; 1 drivers +v0x292a330_0 .alias "in0", 0 0, v0x292a990_0; +v0x292a3d0_0 .alias "in1", 0 0, v0x292ae60_0; +v0x292a470_0 .net "nS", 0 0, L_0x299f8b0; 1 drivers +v0x292a4f0_0 .net "out0", 0 0, L_0x299f970; 1 drivers +v0x292a590_0 .net "out1", 0 0, L_0x299fa80; 1 drivers +v0x292a670_0 .alias "outfinal", 0 0, v0x292aa40_0; +S_0x2929b20 .scope module, "setSLTres2" "TwoInMux" 3 335, 3 109, S_0x2929430; + .timescale -9 -12; +L_0x29a08c0/d .functor NOT 1, L_0x29d1680, C4<0>, C4<0>, C4<0>; +L_0x29a08c0 .delay (10000,10000,10000) L_0x29a08c0/d; +L_0x29a0960/d .functor AND 1, L_0x29a1090, L_0x29a08c0, C4<1>, C4<1>; +L_0x29a0960 .delay (20000,20000,20000) L_0x29a0960/d; +L_0x29a0a70/d .functor AND 1, C4<0>, L_0x29d1680, C4<1>, C4<1>; +L_0x29a0a70 .delay (20000,20000,20000) L_0x29a0a70/d; +L_0x29a0b10/d .functor OR 1, L_0x29a0960, L_0x29a0a70, C4<0>, C4<0>; +L_0x29a0b10 .delay (20000,20000,20000) L_0x29a0b10/d; +v0x2929c10_0 .alias "S", 0 0, v0x293b720_0; +v0x2929cb0_0 .net "in0", 0 0, L_0x29a1090; 1 drivers +v0x2929d50_0 .net "in1", 0 0, C4<0>; 1 drivers +v0x2929df0_0 .net "nS", 0 0, L_0x29a08c0; 1 drivers +v0x2929e70_0 .net "out0", 0 0, L_0x29a0960; 1 drivers +v0x2929f10_0 .net "out1", 0 0, L_0x29a0a70; 1 drivers +v0x2929ff0_0 .net "outfinal", 0 0, L_0x29a0b10; 1 drivers +S_0x29295a0 .scope module, "setSLTres3" "TwoInMux" 3 336, 3 109, S_0x2929430; + .timescale -9 -12; +L_0x29a0d40/d .functor NOT 1, L_0x29d1680, C4<0>, C4<0>, C4<0>; +L_0x29a0d40 .delay (10000,10000,10000) L_0x29a0d40/d; +L_0x29a0e00/d .functor AND 1, L_0x29a16d0, L_0x29a0d40, C4<1>, C4<1>; +L_0x29a0e00 .delay (20000,20000,20000) L_0x29a0e00/d; +L_0x29a1490/d .functor AND 1, L_0x29a1180, L_0x29d1680, C4<1>, C4<1>; +L_0x29a1490 .delay (20000,20000,20000) L_0x29a1490/d; +L_0x29a14f0/d .functor OR 1, L_0x29a0e00, L_0x29a1490, C4<0>, C4<0>; +L_0x29a14f0 .delay (20000,20000,20000) L_0x29a14f0/d; +v0x2929690_0 .alias "S", 0 0, v0x293b720_0; +v0x2929710_0 .net "in0", 0 0, L_0x29a16d0; 1 drivers +v0x29297b0_0 .net "in1", 0 0, L_0x29a1180; 1 drivers +v0x2929850_0 .net "nS", 0 0, L_0x29a0d40; 1 drivers +v0x2929900_0 .net "out0", 0 0, L_0x29a0e00; 1 drivers +v0x29299a0_0 .net "out1", 0 0, L_0x29a1490; 1 drivers +v0x2929a80_0 .net "outfinal", 0 0, L_0x29a14f0; 1 drivers +S_0x29277b0 .scope generate, "sltbits[10]" "sltbits[10]" 3 332, 3 332, S_0x28e1a50; + .timescale -9 -12; +P_0x29271c8 .param/l "i" 3 332, +C4<01010>; +S_0x2928410 .scope module, "attempt" "MiddleAddSubSLT" 3 334, 3 189, S_0x29277b0; + .timescale -9 -12; +L_0x29a1270/d .functor NOT 1, L_0x29a1a40, C4<0>, C4<0>, C4<0>; +L_0x29a1270 .delay (10000,10000,10000) L_0x29a1270/d; +L_0x29a1ff0/d .functor NOT 1, L_0x29a20b0, C4<0>, C4<0>, C4<0>; +L_0x29a1ff0 .delay (10000,10000,10000) L_0x29a1ff0/d; +L_0x29a2150/d .functor AND 1, L_0x29a2290, L_0x29a1ff0, C4<1>, C4<1>; +L_0x29a2150 .delay (20000,20000,20000) L_0x29a2150/d; +L_0x29a2330/d .functor XOR 1, L_0x29a19a0, L_0x29a1d80, C4<0>, C4<0>; +L_0x29a2330 .delay (40000,40000,40000) L_0x29a2330/d; +L_0x29a2420/d .functor XOR 1, L_0x29a2330, L_0x29a29c0, C4<0>, C4<0>; +L_0x29a2420 .delay (40000,40000,40000) L_0x29a2420/d; +L_0x29a2510/d .functor AND 1, L_0x29a19a0, L_0x29a1d80, C4<1>, C4<1>; +L_0x29a2510 .delay (20000,20000,20000) L_0x29a2510/d; +L_0x29a2680/d .functor AND 1, L_0x29a2330, L_0x29a29c0, C4<1>, C4<1>; +L_0x29a2680 .delay (20000,20000,20000) L_0x29a2680/d; +L_0x29a2770/d .functor OR 1, L_0x29a2510, L_0x29a2680, C4<0>, C4<0>; +L_0x29a2770 .delay (20000,20000,20000) L_0x29a2770/d; +v0x2928a90_0 .net "A", 0 0, L_0x29a19a0; 1 drivers +v0x2928b50_0 .net "AandB", 0 0, L_0x29a2510; 1 drivers +v0x2928bf0_0 .net "AddSubSLTSum", 0 0, L_0x29a2420; 1 drivers +v0x2928c90_0 .net "AxorB", 0 0, L_0x29a2330; 1 drivers +v0x2928d10_0 .net "B", 0 0, L_0x29a1a40; 1 drivers +v0x2928dc0_0 .net "BornB", 0 0, L_0x29a1d80; 1 drivers +v0x2928e80_0 .net "CINandAxorB", 0 0, L_0x29a2680; 1 drivers +v0x2928f00_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x2928f80_0 .net *"_s3", 0 0, L_0x29a20b0; 1 drivers +v0x2929000_0 .net *"_s5", 0 0, L_0x29a2290; 1 drivers +v0x29290a0_0 .net "carryin", 0 0, L_0x29a29c0; 1 drivers +v0x2929140_0 .net "carryout", 0 0, L_0x29a2770; 1 drivers +v0x29291e0_0 .net "nB", 0 0, L_0x29a1270; 1 drivers +v0x2929290_0 .net "nCmd2", 0 0, L_0x29a1ff0; 1 drivers +v0x2929390_0 .net "subtract", 0 0, L_0x29a2150; 1 drivers +L_0x29a1f50 .part v0x2960210_0, 0, 1; +L_0x29a20b0 .part v0x2960210_0, 2, 1; +L_0x29a2290 .part v0x2960210_0, 0, 1; +S_0x2928500 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x2928410; + .timescale -9 -12; +L_0x29a1ae0/d .functor NOT 1, L_0x29a1f50, C4<0>, C4<0>, C4<0>; +L_0x29a1ae0 .delay (10000,10000,10000) L_0x29a1ae0/d; +L_0x29a1b80/d .functor AND 1, L_0x29a1a40, L_0x29a1ae0, C4<1>, C4<1>; +L_0x29a1b80 .delay (20000,20000,20000) L_0x29a1b80/d; +L_0x29a1c70/d .functor AND 1, L_0x29a1270, L_0x29a1f50, C4<1>, C4<1>; +L_0x29a1c70 .delay (20000,20000,20000) L_0x29a1c70/d; +L_0x29a1d80/d .functor OR 1, L_0x29a1b80, L_0x29a1c70, C4<0>, C4<0>; +L_0x29a1d80 .delay (20000,20000,20000) L_0x29a1d80/d; +v0x29285f0_0 .net "S", 0 0, L_0x29a1f50; 1 drivers +v0x29286b0_0 .alias "in0", 0 0, v0x2928d10_0; +v0x2928750_0 .alias "in1", 0 0, v0x29291e0_0; +v0x29287f0_0 .net "nS", 0 0, L_0x29a1ae0; 1 drivers +v0x2928870_0 .net "out0", 0 0, L_0x29a1b80; 1 drivers +v0x2928910_0 .net "out1", 0 0, L_0x29a1c70; 1 drivers +v0x29289f0_0 .alias "outfinal", 0 0, v0x2928dc0_0; +S_0x2927ea0 .scope module, "setSLTres2" "TwoInMux" 3 335, 3 109, S_0x29277b0; + .timescale -9 -12; +L_0x29a2a60/d .functor NOT 1, L_0x29d1680, C4<0>, C4<0>, C4<0>; +L_0x29a2a60 .delay (10000,10000,10000) L_0x29a2a60/d; +L_0x29a2b00/d .functor AND 1, L_0x29a2d90, L_0x29a2a60, C4<1>, C4<1>; +L_0x29a2b00 .delay (20000,20000,20000) L_0x29a2b00/d; +L_0x29a2c10/d .functor AND 1, C4<0>, L_0x29d1680, C4<1>, C4<1>; +L_0x29a2c10 .delay (20000,20000,20000) L_0x29a2c10/d; +L_0x29a30e0/d .functor OR 1, L_0x29a2b00, L_0x29a2c10, C4<0>, C4<0>; +L_0x29a30e0 .delay (20000,20000,20000) L_0x29a30e0/d; +v0x2927f90_0 .alias "S", 0 0, v0x293b720_0; +v0x2928030_0 .net "in0", 0 0, L_0x29a2d90; 1 drivers +v0x29280d0_0 .net "in1", 0 0, C4<0>; 1 drivers +v0x2928170_0 .net "nS", 0 0, L_0x29a2a60; 1 drivers +v0x29281f0_0 .net "out0", 0 0, L_0x29a2b00; 1 drivers +v0x2928290_0 .net "out1", 0 0, L_0x29a2c10; 1 drivers +v0x2928370_0 .net "outfinal", 0 0, L_0x29a30e0; 1 drivers +S_0x2927920 .scope module, "setSLTres3" "TwoInMux" 3 336, 3 109, S_0x29277b0; + .timescale -9 -12; +L_0x29a2f10/d .functor NOT 1, L_0x29d1680, C4<0>, C4<0>, C4<0>; +L_0x29a2f10 .delay (10000,10000,10000) L_0x29a2f10/d; +L_0x29a3020/d .functor AND 1, L_0x29a3270, L_0x29a2f10, C4<1>, C4<1>; +L_0x29a3020 .delay (20000,20000,20000) L_0x29a3020/d; +L_0x29a3620/d .functor AND 1, L_0x29a3360, L_0x29d1680, C4<1>, C4<1>; +L_0x29a3620 .delay (20000,20000,20000) L_0x29a3620/d; +L_0x29a36c0/d .functor OR 1, L_0x29a3020, L_0x29a3620, C4<0>, C4<0>; +L_0x29a36c0 .delay (20000,20000,20000) L_0x29a36c0/d; +v0x2927a10_0 .alias "S", 0 0, v0x293b720_0; +v0x2927a90_0 .net "in0", 0 0, L_0x29a3270; 1 drivers +v0x2927b30_0 .net "in1", 0 0, L_0x29a3360; 1 drivers +v0x2927bd0_0 .net "nS", 0 0, L_0x29a2f10; 1 drivers +v0x2927c80_0 .net "out0", 0 0, L_0x29a3020; 1 drivers +v0x2927d20_0 .net "out1", 0 0, L_0x29a3620; 1 drivers +v0x2927e00_0 .net "outfinal", 0 0, L_0x29a36c0; 1 drivers +S_0x2925b30 .scope generate, "sltbits[11]" "sltbits[11]" 3 332, 3 332, S_0x28e1a50; + .timescale -9 -12; +P_0x2925548 .param/l "i" 3 332, +C4<01011>; +S_0x2926790 .scope module, "attempt" "MiddleAddSubSLT" 3 334, 3 189, S_0x2925b30; + .timescale -9 -12; +L_0x29a3450/d .functor NOT 1, L_0x29a3a30, C4<0>, C4<0>, C4<0>; +L_0x29a3450 .delay (10000,10000,10000) L_0x29a3450/d; +L_0x29a41c0/d .functor NOT 1, L_0x29a4280, C4<0>, C4<0>, C4<0>; +L_0x29a41c0 .delay (10000,10000,10000) L_0x29a41c0/d; +L_0x29a4320/d .functor AND 1, L_0x29a4460, L_0x29a41c0, C4<1>, C4<1>; +L_0x29a4320 .delay (20000,20000,20000) L_0x29a4320/d; +L_0x29a4500/d .functor XOR 1, L_0x29a3990, L_0x29a3f50, C4<0>, C4<0>; +L_0x29a4500 .delay (40000,40000,40000) L_0x29a4500/d; +L_0x29a45f0/d .functor XOR 1, L_0x29a4500, L_0x29a3b60, C4<0>, C4<0>; +L_0x29a45f0 .delay (40000,40000,40000) L_0x29a45f0/d; +L_0x29a46e0/d .functor AND 1, L_0x29a3990, L_0x29a3f50, C4<1>, C4<1>; +L_0x29a46e0 .delay (20000,20000,20000) L_0x29a46e0/d; +L_0x29a4850/d .functor AND 1, L_0x29a4500, L_0x29a3b60, C4<1>, C4<1>; +L_0x29a4850 .delay (20000,20000,20000) L_0x29a4850/d; +L_0x29a4940/d .functor OR 1, L_0x29a46e0, L_0x29a4850, C4<0>, C4<0>; +L_0x29a4940 .delay (20000,20000,20000) L_0x29a4940/d; +v0x2926e10_0 .net "A", 0 0, L_0x29a3990; 1 drivers +v0x2926ed0_0 .net "AandB", 0 0, L_0x29a46e0; 1 drivers +v0x2926f70_0 .net "AddSubSLTSum", 0 0, L_0x29a45f0; 1 drivers +v0x2927010_0 .net "AxorB", 0 0, L_0x29a4500; 1 drivers +v0x2927090_0 .net "B", 0 0, L_0x29a3a30; 1 drivers +v0x2927140_0 .net "BornB", 0 0, L_0x29a3f50; 1 drivers +v0x2927200_0 .net "CINandAxorB", 0 0, L_0x29a4850; 1 drivers +v0x2927280_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x2927300_0 .net *"_s3", 0 0, L_0x29a4280; 1 drivers +v0x2927380_0 .net *"_s5", 0 0, L_0x29a4460; 1 drivers +v0x2927420_0 .net "carryin", 0 0, L_0x29a3b60; 1 drivers +v0x29274c0_0 .net "carryout", 0 0, L_0x29a4940; 1 drivers +v0x2927560_0 .net "nB", 0 0, L_0x29a3450; 1 drivers +v0x2927610_0 .net "nCmd2", 0 0, L_0x29a41c0; 1 drivers +v0x2927710_0 .net "subtract", 0 0, L_0x29a4320; 1 drivers +L_0x29a4120 .part v0x2960210_0, 0, 1; +L_0x29a4280 .part v0x2960210_0, 2, 1; +L_0x29a4460 .part v0x2960210_0, 0, 1; +S_0x2926880 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x2926790; + .timescale -9 -12; +L_0x29a3c70/d .functor NOT 1, L_0x29a4120, C4<0>, C4<0>, C4<0>; +L_0x29a3c70 .delay (10000,10000,10000) L_0x29a3c70/d; +L_0x29a3d30/d .functor AND 1, L_0x29a3a30, L_0x29a3c70, C4<1>, C4<1>; +L_0x29a3d30 .delay (20000,20000,20000) L_0x29a3d30/d; +L_0x29a3e40/d .functor AND 1, L_0x29a3450, L_0x29a4120, C4<1>, C4<1>; +L_0x29a3e40 .delay (20000,20000,20000) L_0x29a3e40/d; +L_0x29a3f50/d .functor OR 1, L_0x29a3d30, L_0x29a3e40, C4<0>, C4<0>; +L_0x29a3f50 .delay (20000,20000,20000) L_0x29a3f50/d; +v0x2926970_0 .net "S", 0 0, L_0x29a4120; 1 drivers +v0x2926a30_0 .alias "in0", 0 0, v0x2927090_0; +v0x2926ad0_0 .alias "in1", 0 0, v0x2927560_0; +v0x2926b70_0 .net "nS", 0 0, L_0x29a3c70; 1 drivers +v0x2926bf0_0 .net "out0", 0 0, L_0x29a3d30; 1 drivers +v0x2926c90_0 .net "out1", 0 0, L_0x29a3e40; 1 drivers +v0x2926d70_0 .alias "outfinal", 0 0, v0x2927140_0; +S_0x2926220 .scope module, "setSLTres2" "TwoInMux" 3 335, 3 109, S_0x2925b30; + .timescale -9 -12; +L_0x29a5030/d .functor NOT 1, L_0x29d1680, C4<0>, C4<0>, C4<0>; +L_0x29a5030 .delay (10000,10000,10000) L_0x29a5030/d; +L_0x29a50b0/d .functor AND 1, L_0x29a5440, L_0x29a5030, C4<1>, C4<1>; +L_0x29a50b0 .delay (20000,20000,20000) L_0x29a50b0/d; +L_0x29a51c0/d .functor AND 1, C4<0>, L_0x29d1680, C4<1>, C4<1>; +L_0x29a51c0 .delay (20000,20000,20000) L_0x29a51c0/d; +L_0x29a5260/d .functor OR 1, L_0x29a50b0, L_0x29a51c0, C4<0>, C4<0>; +L_0x29a5260 .delay (20000,20000,20000) L_0x29a5260/d; +v0x2926310_0 .alias "S", 0 0, v0x293b720_0; +v0x29263b0_0 .net "in0", 0 0, L_0x29a5440; 1 drivers +v0x2926450_0 .net "in1", 0 0, C4<0>; 1 drivers +v0x29264f0_0 .net "nS", 0 0, L_0x29a5030; 1 drivers +v0x2926570_0 .net "out0", 0 0, L_0x29a50b0; 1 drivers +v0x2926610_0 .net "out1", 0 0, L_0x29a51c0; 1 drivers +v0x29266f0_0 .net "outfinal", 0 0, L_0x29a5260; 1 drivers +S_0x2925ca0 .scope module, "setSLTres3" "TwoInMux" 3 336, 3 109, S_0x2925b30; + .timescale -9 -12; +L_0x29a0ce0/d .functor NOT 1, L_0x29d1680, C4<0>, C4<0>, C4<0>; +L_0x29a0ce0 .delay (10000,10000,10000) L_0x29a0ce0/d; +L_0x29a4e30/d .functor AND 1, L_0x29a5a80, L_0x29a0ce0, C4<1>, C4<1>; +L_0x29a4e30 .delay (20000,20000,20000) L_0x29a4e30/d; +L_0x29a4f40/d .functor AND 1, L_0x28923f0, L_0x29d1680, C4<1>, C4<1>; +L_0x29a4f40 .delay (20000,20000,20000) L_0x29a4f40/d; +L_0x29a58f0/d .functor OR 1, L_0x29a4e30, L_0x29a4f40, C4<0>, C4<0>; +L_0x29a58f0 .delay (20000,20000,20000) L_0x29a58f0/d; +v0x2925d90_0 .alias "S", 0 0, v0x293b720_0; +v0x2925e10_0 .net "in0", 0 0, L_0x29a5a80; 1 drivers +v0x2925eb0_0 .net "in1", 0 0, L_0x28923f0; 1 drivers +v0x2925f50_0 .net "nS", 0 0, L_0x29a0ce0; 1 drivers +v0x2926000_0 .net "out0", 0 0, L_0x29a4e30; 1 drivers +v0x29260a0_0 .net "out1", 0 0, L_0x29a4f40; 1 drivers +v0x2926180_0 .net "outfinal", 0 0, L_0x29a58f0; 1 drivers +S_0x2923eb0 .scope generate, "sltbits[12]" "sltbits[12]" 3 332, 3 332, S_0x28e1a50; + .timescale -9 -12; +P_0x29238c8 .param/l "i" 3 332, +C4<01100>; +S_0x2924b10 .scope module, "attempt" "MiddleAddSubSLT" 3 334, 3 189, S_0x2923eb0; + .timescale -9 -12; +L_0x28924e0/d .functor NOT 1, L_0x29a6200, C4<0>, C4<0>, C4<0>; +L_0x28924e0 .delay (10000,10000,10000) L_0x28924e0/d; +L_0x29a6580/d .functor NOT 1, L_0x29a6620, C4<0>, C4<0>, C4<0>; +L_0x29a6580 .delay (10000,10000,10000) L_0x29a6580/d; +L_0x29a66c0/d .functor AND 1, L_0x29a6800, L_0x29a6580, C4<1>, C4<1>; +L_0x29a66c0 .delay (20000,20000,20000) L_0x29a66c0/d; +L_0x29a68a0/d .functor XOR 1, L_0x29a6160, L_0x29a6350, C4<0>, C4<0>; +L_0x29a68a0 .delay (40000,40000,40000) L_0x29a68a0/d; +L_0x29a6990/d .functor XOR 1, L_0x29a68a0, L_0x29a7360, C4<0>, C4<0>; +L_0x29a6990 .delay (40000,40000,40000) L_0x29a6990/d; +L_0x29a6a80/d .functor AND 1, L_0x29a6160, L_0x29a6350, C4<1>, C4<1>; +L_0x29a6a80 .delay (20000,20000,20000) L_0x29a6a80/d; +L_0x29a6c20/d .functor AND 1, L_0x29a68a0, L_0x29a7360, C4<1>, C4<1>; +L_0x29a6c20 .delay (20000,20000,20000) L_0x29a6c20/d; +L_0x29a6d10/d .functor OR 1, L_0x29a6a80, L_0x29a6c20, C4<0>, C4<0>; +L_0x29a6d10 .delay (20000,20000,20000) L_0x29a6d10/d; +v0x2925190_0 .net "A", 0 0, L_0x29a6160; 1 drivers +v0x2925250_0 .net "AandB", 0 0, L_0x29a6a80; 1 drivers +v0x29252f0_0 .net "AddSubSLTSum", 0 0, L_0x29a6990; 1 drivers +v0x2925390_0 .net "AxorB", 0 0, L_0x29a68a0; 1 drivers +v0x2925410_0 .net "B", 0 0, L_0x29a6200; 1 drivers +v0x29254c0_0 .net "BornB", 0 0, L_0x29a6350; 1 drivers +v0x2925580_0 .net "CINandAxorB", 0 0, L_0x29a6c20; 1 drivers +v0x2925600_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x2925680_0 .net *"_s3", 0 0, L_0x29a6620; 1 drivers +v0x2925700_0 .net *"_s5", 0 0, L_0x29a6800; 1 drivers +v0x29257a0_0 .net "carryin", 0 0, L_0x29a7360; 1 drivers +v0x2925840_0 .net "carryout", 0 0, L_0x29a6d10; 1 drivers +v0x29258e0_0 .net "nB", 0 0, L_0x28924e0; 1 drivers +v0x2925990_0 .net "nCmd2", 0 0, L_0x29a6580; 1 drivers +v0x2925a90_0 .net "subtract", 0 0, L_0x29a66c0; 1 drivers +L_0x29a64e0 .part v0x2960210_0, 0, 1; +L_0x29a6620 .part v0x2960210_0, 2, 1; +L_0x29a6800 .part v0x2960210_0, 0, 1; +S_0x2924c00 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x2924b10; + .timescale -9 -12; +L_0x29a55e0/d .functor NOT 1, L_0x29a64e0, C4<0>, C4<0>, C4<0>; +L_0x29a55e0 .delay (10000,10000,10000) L_0x29a55e0/d; +L_0x29a56a0/d .functor AND 1, L_0x29a6200, L_0x29a55e0, C4<1>, C4<1>; +L_0x29a56a0 .delay (20000,20000,20000) L_0x29a56a0/d; +L_0x29a57b0/d .functor AND 1, L_0x28924e0, L_0x29a64e0, C4<1>, C4<1>; +L_0x29a57b0 .delay (20000,20000,20000) L_0x29a57b0/d; +L_0x29a6350/d .functor OR 1, L_0x29a56a0, L_0x29a57b0, C4<0>, C4<0>; +L_0x29a6350 .delay (20000,20000,20000) L_0x29a6350/d; +v0x2924cf0_0 .net "S", 0 0, L_0x29a64e0; 1 drivers +v0x2924db0_0 .alias "in0", 0 0, v0x2925410_0; +v0x2924e50_0 .alias "in1", 0 0, v0x29258e0_0; +v0x2924ef0_0 .net "nS", 0 0, L_0x29a55e0; 1 drivers +v0x2924f70_0 .net "out0", 0 0, L_0x29a56a0; 1 drivers +v0x2925010_0 .net "out1", 0 0, L_0x29a57b0; 1 drivers +v0x29250f0_0 .alias "outfinal", 0 0, v0x29254c0_0; +S_0x29245a0 .scope module, "setSLTres2" "TwoInMux" 3 335, 3 109, S_0x2923eb0; + .timescale -9 -12; +L_0x29a7400/d .functor NOT 1, L_0x29d1680, C4<0>, C4<0>, C4<0>; +L_0x29a7400 .delay (10000,10000,10000) L_0x29a7400/d; +L_0x29a7480/d .functor AND 1, L_0x29a6f60, L_0x29a7400, C4<1>, C4<1>; +L_0x29a7480 .delay (20000,20000,20000) L_0x29a7480/d; +L_0x29a7590/d .functor AND 1, C4<0>, L_0x29d1680, C4<1>, C4<1>; +L_0x29a7590 .delay (20000,20000,20000) L_0x29a7590/d; +L_0x29a7630/d .functor OR 1, L_0x29a7480, L_0x29a7590, C4<0>, C4<0>; +L_0x29a7630 .delay (20000,20000,20000) L_0x29a7630/d; +v0x2924690_0 .alias "S", 0 0, v0x293b720_0; +v0x2924730_0 .net "in0", 0 0, L_0x29a6f60; 1 drivers +v0x29247d0_0 .net "in1", 0 0, C4<0>; 1 drivers +v0x2924870_0 .net "nS", 0 0, L_0x29a7400; 1 drivers +v0x29248f0_0 .net "out0", 0 0, L_0x29a7480; 1 drivers +v0x2924990_0 .net "out1", 0 0, L_0x29a7590; 1 drivers +v0x2924a70_0 .net "outfinal", 0 0, L_0x29a7630; 1 drivers +S_0x2924020 .scope module, "setSLTres3" "TwoInMux" 3 336, 3 109, S_0x2923eb0; + .timescale -9 -12; +L_0x29a70e0/d .functor NOT 1, L_0x29d1680, C4<0>, C4<0>, C4<0>; +L_0x29a70e0 .delay (10000,10000,10000) L_0x29a70e0/d; +L_0x29a71f0/d .functor AND 1, L_0x29a7810, L_0x29a70e0, C4<1>, C4<1>; +L_0x29a71f0 .delay (20000,20000,20000) L_0x29a71f0/d; +L_0x29a7300/d .functor AND 1, L_0x29a7900, L_0x29d1680, C4<1>, C4<1>; +L_0x29a7300 .delay (20000,20000,20000) L_0x29a7300/d; +L_0x29a7c60/d .functor OR 1, L_0x29a71f0, L_0x29a7300, C4<0>, C4<0>; +L_0x29a7c60 .delay (20000,20000,20000) L_0x29a7c60/d; +v0x2924110_0 .alias "S", 0 0, v0x293b720_0; +v0x2924190_0 .net "in0", 0 0, L_0x29a7810; 1 drivers +v0x2924230_0 .net "in1", 0 0, L_0x29a7900; 1 drivers +v0x29242d0_0 .net "nS", 0 0, L_0x29a70e0; 1 drivers +v0x2924380_0 .net "out0", 0 0, L_0x29a71f0; 1 drivers +v0x2924420_0 .net "out1", 0 0, L_0x29a7300; 1 drivers +v0x2924500_0 .net "outfinal", 0 0, L_0x29a7c60; 1 drivers +S_0x2922230 .scope generate, "sltbits[13]" "sltbits[13]" 3 332, 3 332, S_0x28e1a50; + .timescale -9 -12; +P_0x2921c48 .param/l "i" 3 332, +C4<01101>; +S_0x2922e90 .scope module, "attempt" "MiddleAddSubSLT" 3 334, 3 189, S_0x2922230; + .timescale -9 -12; +L_0x29a79f0/d .functor NOT 1, L_0x29a7fd0, C4<0>, C4<0>, C4<0>; +L_0x29a79f0 .delay (10000,10000,10000) L_0x29a79f0/d; +L_0x29a8720/d .functor NOT 1, L_0x29a87e0, C4<0>, C4<0>, C4<0>; +L_0x29a8720 .delay (10000,10000,10000) L_0x29a8720/d; +L_0x29a8880/d .functor AND 1, L_0x29a89c0, L_0x29a8720, C4<1>, C4<1>; +L_0x29a8880 .delay (20000,20000,20000) L_0x29a8880/d; +L_0x29a8a60/d .functor XOR 1, L_0x29a7f30, L_0x29a84b0, C4<0>, C4<0>; +L_0x29a8a60 .delay (40000,40000,40000) L_0x29a8a60/d; +L_0x29a8b50/d .functor XOR 1, L_0x29a8a60, L_0x29a8100, C4<0>, C4<0>; +L_0x29a8b50 .delay (40000,40000,40000) L_0x29a8b50/d; +L_0x29a8c70/d .functor AND 1, L_0x29a7f30, L_0x29a84b0, C4<1>, C4<1>; +L_0x29a8c70 .delay (20000,20000,20000) L_0x29a8c70/d; +L_0x29a8e10/d .functor AND 1, L_0x29a8a60, L_0x29a8100, C4<1>, C4<1>; +L_0x29a8e10 .delay (20000,20000,20000) L_0x29a8e10/d; +L_0x29a8f00/d .functor OR 1, L_0x29a8c70, L_0x29a8e10, C4<0>, C4<0>; +L_0x29a8f00 .delay (20000,20000,20000) L_0x29a8f00/d; +v0x2923510_0 .net "A", 0 0, L_0x29a7f30; 1 drivers +v0x29235d0_0 .net "AandB", 0 0, L_0x29a8c70; 1 drivers +v0x2923670_0 .net "AddSubSLTSum", 0 0, L_0x29a8b50; 1 drivers +v0x2923710_0 .net "AxorB", 0 0, L_0x29a8a60; 1 drivers +v0x2923790_0 .net "B", 0 0, L_0x29a7fd0; 1 drivers +v0x2923840_0 .net "BornB", 0 0, L_0x29a84b0; 1 drivers +v0x2923900_0 .net "CINandAxorB", 0 0, L_0x29a8e10; 1 drivers +v0x2923980_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x2923a00_0 .net *"_s3", 0 0, L_0x29a87e0; 1 drivers +v0x2923a80_0 .net *"_s5", 0 0, L_0x29a89c0; 1 drivers +v0x2923b20_0 .net "carryin", 0 0, L_0x29a8100; 1 drivers +v0x2923bc0_0 .net "carryout", 0 0, L_0x29a8f00; 1 drivers +v0x2923c60_0 .net "nB", 0 0, L_0x29a79f0; 1 drivers +v0x2923d10_0 .net "nCmd2", 0 0, L_0x29a8720; 1 drivers +v0x2923e10_0 .net "subtract", 0 0, L_0x29a8880; 1 drivers +L_0x29a8680 .part v0x2960210_0, 0, 1; +L_0x29a87e0 .part v0x2960210_0, 2, 1; +L_0x29a89c0 .part v0x2960210_0, 0, 1; +S_0x2922f80 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x2922e90; + .timescale -9 -12; +L_0x29a7bc0/d .functor NOT 1, L_0x29a8680, C4<0>, C4<0>, C4<0>; +L_0x29a7bc0 .delay (10000,10000,10000) L_0x29a7bc0/d; +L_0x29a82b0/d .functor AND 1, L_0x29a7fd0, L_0x29a7bc0, C4<1>, C4<1>; +L_0x29a82b0 .delay (20000,20000,20000) L_0x29a82b0/d; +L_0x29a83a0/d .functor AND 1, L_0x29a79f0, L_0x29a8680, C4<1>, C4<1>; +L_0x29a83a0 .delay (20000,20000,20000) L_0x29a83a0/d; +L_0x29a84b0/d .functor OR 1, L_0x29a82b0, L_0x29a83a0, C4<0>, C4<0>; +L_0x29a84b0 .delay (20000,20000,20000) L_0x29a84b0/d; +v0x2923070_0 .net "S", 0 0, L_0x29a8680; 1 drivers +v0x2923130_0 .alias "in0", 0 0, v0x2923790_0; +v0x29231d0_0 .alias "in1", 0 0, v0x2923c60_0; +v0x2923270_0 .net "nS", 0 0, L_0x29a7bc0; 1 drivers +v0x29232f0_0 .net "out0", 0 0, L_0x29a82b0; 1 drivers +v0x2923390_0 .net "out1", 0 0, L_0x29a83a0; 1 drivers +v0x2923470_0 .alias "outfinal", 0 0, v0x2923840_0; +S_0x2922920 .scope module, "setSLTres2" "TwoInMux" 3 335, 3 109, S_0x2922230; + .timescale -9 -12; +L_0x29a81a0/d .functor NOT 1, L_0x29d1680, C4<0>, C4<0>, C4<0>; +L_0x29a81a0 .delay (10000,10000,10000) L_0x29a81a0/d; +L_0x29a96a0/d .functor AND 1, L_0x29a9a10, L_0x29a81a0, C4<1>, C4<1>; +L_0x29a96a0 .delay (20000,20000,20000) L_0x29a96a0/d; +L_0x29a9790/d .functor AND 1, C4<0>, L_0x29d1680, C4<1>, C4<1>; +L_0x29a9790 .delay (20000,20000,20000) L_0x29a9790/d; +L_0x29a9830/d .functor OR 1, L_0x29a96a0, L_0x29a9790, C4<0>, C4<0>; +L_0x29a9830 .delay (20000,20000,20000) L_0x29a9830/d; +v0x2922a10_0 .alias "S", 0 0, v0x293b720_0; +v0x2922ab0_0 .net "in0", 0 0, L_0x29a9a10; 1 drivers +v0x2922b50_0 .net "in1", 0 0, C4<0>; 1 drivers +v0x2922bf0_0 .net "nS", 0 0, L_0x29a81a0; 1 drivers +v0x2922c70_0 .net "out0", 0 0, L_0x29a96a0; 1 drivers +v0x2922d10_0 .net "out1", 0 0, L_0x29a9790; 1 drivers +v0x2922df0_0 .net "outfinal", 0 0, L_0x29a9830; 1 drivers +S_0x29223a0 .scope module, "setSLTres3" "TwoInMux" 3 336, 3 109, S_0x2922230; + .timescale -9 -12; +L_0x29a9350/d .functor NOT 1, L_0x29d1680, C4<0>, C4<0>, C4<0>; +L_0x29a9350 .delay (10000,10000,10000) L_0x29a9350/d; +L_0x29a9460/d .functor AND 1, L_0x2996bc0, L_0x29a9350, C4<1>, C4<1>; +L_0x29a9460 .delay (20000,20000,20000) L_0x29a9460/d; +L_0x29a9570/d .functor AND 1, L_0x29a9b00, L_0x29d1680, C4<1>, C4<1>; +L_0x29a9570 .delay (20000,20000,20000) L_0x29a9570/d; +L_0x29a9610/d .functor OR 1, L_0x29a9460, L_0x29a9570, C4<0>, C4<0>; +L_0x29a9610 .delay (20000,20000,20000) L_0x29a9610/d; +v0x2922490_0 .alias "S", 0 0, v0x293b720_0; +v0x2922510_0 .net "in0", 0 0, L_0x2996bc0; 1 drivers +v0x29225b0_0 .net "in1", 0 0, L_0x29a9b00; 1 drivers +v0x2922650_0 .net "nS", 0 0, L_0x29a9350; 1 drivers +v0x2922700_0 .net "out0", 0 0, L_0x29a9460; 1 drivers +v0x29227a0_0 .net "out1", 0 0, L_0x29a9570; 1 drivers +v0x2922880_0 .net "outfinal", 0 0, L_0x29a9610; 1 drivers +S_0x29205b0 .scope generate, "sltbits[14]" "sltbits[14]" 3 332, 3 332, S_0x28e1a50; + .timescale -9 -12; +P_0x291fea8 .param/l "i" 3 332, +C4<01110>; +S_0x2921210 .scope module, "attempt" "MiddleAddSubSLT" 3 334, 3 189, S_0x29205b0; + .timescale -9 -12; +L_0x29a9bf0/d .functor NOT 1, L_0x29aa580, C4<0>, C4<0>, C4<0>; +L_0x29a9bf0 .delay (10000,10000,10000) L_0x29a9bf0/d; +L_0x29aaa40/d .functor NOT 1, L_0x29aaae0, C4<0>, C4<0>, C4<0>; +L_0x29aaa40 .delay (10000,10000,10000) L_0x29aaa40/d; +L_0x29aab80/d .functor AND 1, L_0x29aacc0, L_0x29aaa40, C4<1>, C4<1>; +L_0x29aab80 .delay (20000,20000,20000) L_0x29aab80/d; +L_0x29aad60/d .functor XOR 1, L_0x29aa4e0, L_0x29aa810, C4<0>, C4<0>; +L_0x29aad60 .delay (40000,40000,40000) L_0x29aad60/d; +L_0x29aae80/d .functor XOR 1, L_0x29aad60, L_0x29aa6b0, C4<0>, C4<0>; +L_0x29aae80 .delay (40000,40000,40000) L_0x29aae80/d; +L_0x29aafa0/d .functor AND 1, L_0x29aa4e0, L_0x29aa810, C4<1>, C4<1>; +L_0x29aafa0 .delay (20000,20000,20000) L_0x29aafa0/d; +L_0x29ab140/d .functor AND 1, L_0x29aad60, L_0x29aa6b0, C4<1>, C4<1>; +L_0x29ab140 .delay (20000,20000,20000) L_0x29ab140/d; +L_0x29ab230/d .functor OR 1, L_0x29aafa0, L_0x29ab140, C4<0>, C4<0>; +L_0x29ab230 .delay (20000,20000,20000) L_0x29ab230/d; +v0x2921890_0 .net "A", 0 0, L_0x29aa4e0; 1 drivers +v0x2921950_0 .net "AandB", 0 0, L_0x29aafa0; 1 drivers +v0x29219f0_0 .net "AddSubSLTSum", 0 0, L_0x29aae80; 1 drivers +v0x2921a90_0 .net "AxorB", 0 0, L_0x29aad60; 1 drivers +v0x2921b10_0 .net "B", 0 0, L_0x29aa580; 1 drivers +v0x2921bc0_0 .net "BornB", 0 0, L_0x29aa810; 1 drivers +v0x2921c80_0 .net "CINandAxorB", 0 0, L_0x29ab140; 1 drivers +v0x2921d00_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x2921d80_0 .net *"_s3", 0 0, L_0x29aaae0; 1 drivers +v0x2921e00_0 .net *"_s5", 0 0, L_0x29aacc0; 1 drivers +v0x2921ea0_0 .net "carryin", 0 0, L_0x29aa6b0; 1 drivers +v0x2921f40_0 .net "carryout", 0 0, L_0x29ab230; 1 drivers +v0x2921fe0_0 .net "nB", 0 0, L_0x29a9bf0; 1 drivers +v0x2922090_0 .net "nCmd2", 0 0, L_0x29aaa40; 1 drivers +v0x2922190_0 .net "subtract", 0 0, L_0x29aab80; 1 drivers +L_0x29aa9a0 .part v0x2960210_0, 0, 1; +L_0x29aaae0 .part v0x2960210_0, 2, 1; +L_0x29aacc0 .part v0x2960210_0, 0, 1; +S_0x2921300 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x2921210; + .timescale -9 -12; +L_0x29a9da0/d .functor NOT 1, L_0x29aa9a0, C4<0>, C4<0>, C4<0>; +L_0x29a9da0 .delay (10000,10000,10000) L_0x29a9da0/d; +L_0x29a9e60/d .functor AND 1, L_0x29aa580, L_0x29a9da0, C4<1>, C4<1>; +L_0x29a9e60 .delay (20000,20000,20000) L_0x29a9e60/d; +L_0x29a4d10/d .functor AND 1, L_0x29a9bf0, L_0x29aa9a0, C4<1>, C4<1>; +L_0x29a4d10 .delay (20000,20000,20000) L_0x29a4d10/d; +L_0x29aa810/d .functor OR 1, L_0x29a9e60, L_0x29a4d10, C4<0>, C4<0>; +L_0x29aa810 .delay (20000,20000,20000) L_0x29aa810/d; +v0x29213f0_0 .net "S", 0 0, L_0x29aa9a0; 1 drivers +v0x29214b0_0 .alias "in0", 0 0, v0x2921b10_0; +v0x2921550_0 .alias "in1", 0 0, v0x2921fe0_0; +v0x29215f0_0 .net "nS", 0 0, L_0x29a9da0; 1 drivers +v0x2921670_0 .net "out0", 0 0, L_0x29a9e60; 1 drivers +v0x2921710_0 .net "out1", 0 0, L_0x29a4d10; 1 drivers +v0x29217f0_0 .alias "outfinal", 0 0, v0x2921bc0_0; +S_0x2920ca0 .scope module, "setSLTres2" "TwoInMux" 3 335, 3 109, S_0x29205b0; + .timescale -9 -12; +L_0x29ab930/d .functor NOT 1, L_0x29d1680, C4<0>, C4<0>, C4<0>; +L_0x29ab930 .delay (10000,10000,10000) L_0x29ab930/d; +L_0x29ab990/d .functor AND 1, L_0x29ab480, L_0x29ab930, C4<1>, C4<1>; +L_0x29ab990 .delay (20000,20000,20000) L_0x29ab990/d; +L_0x29aba80/d .functor AND 1, C4<0>, L_0x29d1680, C4<1>, C4<1>; +L_0x29aba80 .delay (20000,20000,20000) L_0x29aba80/d; +L_0x29abb20/d .functor OR 1, L_0x29ab990, L_0x29aba80, C4<0>, C4<0>; +L_0x29abb20 .delay (20000,20000,20000) L_0x29abb20/d; +v0x2920d90_0 .alias "S", 0 0, v0x293b720_0; +v0x2920e30_0 .net "in0", 0 0, L_0x29ab480; 1 drivers +v0x2920ed0_0 .net "in1", 0 0, C4<0>; 1 drivers +v0x2920f70_0 .net "nS", 0 0, L_0x29ab930; 1 drivers +v0x2920ff0_0 .net "out0", 0 0, L_0x29ab990; 1 drivers +v0x2921090_0 .net "out1", 0 0, L_0x29aba80; 1 drivers +v0x2921170_0 .net "outfinal", 0 0, L_0x29abb20; 1 drivers +S_0x2920720 .scope module, "setSLTres3" "TwoInMux" 3 336, 3 109, S_0x29205b0; + .timescale -9 -12; +L_0x29ab600/d .functor NOT 1, L_0x29d1680, C4<0>, C4<0>, C4<0>; +L_0x29ab600 .delay (10000,10000,10000) L_0x29ab600/d; +L_0x29ab730/d .functor AND 1, L_0x29abd30, L_0x29ab600, C4<1>, C4<1>; +L_0x29ab730 .delay (20000,20000,20000) L_0x29ab730/d; +L_0x29ab840/d .functor AND 1, L_0x29abe20, L_0x29d1680, C4<1>, C4<1>; +L_0x29ab840 .delay (20000,20000,20000) L_0x29ab840/d; +L_0x29ac1f0/d .functor OR 1, L_0x29ab730, L_0x29ab840, C4<0>, C4<0>; +L_0x29ac1f0 .delay (20000,20000,20000) L_0x29ac1f0/d; +v0x2920810_0 .alias "S", 0 0, v0x293b720_0; +v0x2920890_0 .net "in0", 0 0, L_0x29abd30; 1 drivers +v0x2920930_0 .net "in1", 0 0, L_0x29abe20; 1 drivers +v0x29209d0_0 .net "nS", 0 0, L_0x29ab600; 1 drivers +v0x2920a80_0 .net "out0", 0 0, L_0x29ab730; 1 drivers +v0x2920b20_0 .net "out1", 0 0, L_0x29ab840; 1 drivers +v0x2920c00_0 .net "outfinal", 0 0, L_0x29ac1f0; 1 drivers +S_0x291e710 .scope generate, "sltbits[15]" "sltbits[15]" 3 332, 3 332, S_0x28e1a50; + .timescale -9 -12; +P_0x291e128 .param/l "i" 3 332, +C4<01111>; +S_0x291f470 .scope module, "attempt" "MiddleAddSubSLT" 3 334, 3 189, S_0x291e710; + .timescale -9 -12; +L_0x29abf10/d .functor NOT 1, L_0x29ac510, C4<0>, C4<0>, C4<0>; +L_0x29abf10 .delay (10000,10000,10000) L_0x29abf10/d; +L_0x29acc70/d .functor NOT 1, L_0x29acd30, C4<0>, C4<0>, C4<0>; +L_0x29acc70 .delay (10000,10000,10000) L_0x29acc70/d; +L_0x29acdd0/d .functor AND 1, L_0x29acf10, L_0x29acc70, C4<1>, C4<1>; +L_0x29acdd0 .delay (20000,20000,20000) L_0x29acdd0/d; +L_0x29acfb0/d .functor XOR 1, L_0x29ac470, L_0x29aca00, C4<0>, C4<0>; +L_0x29acfb0 .delay (40000,40000,40000) L_0x29acfb0/d; +L_0x29ad0a0/d .functor XOR 1, L_0x29acfb0, L_0x29ac640, C4<0>, C4<0>; +L_0x29ad0a0 .delay (40000,40000,40000) L_0x29ad0a0/d; +L_0x29ad1c0/d .functor AND 1, L_0x29ac470, L_0x29aca00, C4<1>, C4<1>; +L_0x29ad1c0 .delay (20000,20000,20000) L_0x29ad1c0/d; +L_0x29ad360/d .functor AND 1, L_0x29acfb0, L_0x29ac640, C4<1>, C4<1>; +L_0x29ad360 .delay (20000,20000,20000) L_0x29ad360/d; +L_0x29ad450/d .functor OR 1, L_0x29ad1c0, L_0x29ad360, C4<0>, C4<0>; +L_0x29ad450 .delay (20000,20000,20000) L_0x29ad450/d; +v0x291faf0_0 .net "A", 0 0, L_0x29ac470; 1 drivers +v0x291fbb0_0 .net "AandB", 0 0, L_0x29ad1c0; 1 drivers +v0x291fc50_0 .net "AddSubSLTSum", 0 0, L_0x29ad0a0; 1 drivers +v0x291fcf0_0 .net "AxorB", 0 0, L_0x29acfb0; 1 drivers +v0x291fd70_0 .net "B", 0 0, L_0x29ac510; 1 drivers +v0x291fe20_0 .net "BornB", 0 0, L_0x29aca00; 1 drivers +v0x291fee0_0 .net "CINandAxorB", 0 0, L_0x29ad360; 1 drivers +v0x291ff60_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x2920030_0 .net *"_s3", 0 0, L_0x29acd30; 1 drivers +v0x29200b0_0 .net *"_s5", 0 0, L_0x29acf10; 1 drivers +v0x29201b0_0 .net "carryin", 0 0, L_0x29ac640; 1 drivers +v0x2920250_0 .net "carryout", 0 0, L_0x29ad450; 1 drivers +v0x2920360_0 .net "nB", 0 0, L_0x29abf10; 1 drivers +v0x2920410_0 .net "nCmd2", 0 0, L_0x29acc70; 1 drivers +v0x2920510_0 .net "subtract", 0 0, L_0x29acdd0; 1 drivers +L_0x29acbd0 .part v0x2960210_0, 0, 1; +L_0x29acd30 .part v0x2960210_0, 2, 1; +L_0x29acf10 .part v0x2960210_0, 0, 1; +S_0x291f560 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x291f470; + .timescale -9 -12; +L_0x29ac0e0/d .functor NOT 1, L_0x29acbd0, C4<0>, C4<0>, C4<0>; +L_0x29ac0e0 .delay (10000,10000,10000) L_0x29ac0e0/d; +L_0x29ac860/d .functor AND 1, L_0x29ac510, L_0x29ac0e0, C4<1>, C4<1>; +L_0x29ac860 .delay (20000,20000,20000) L_0x29ac860/d; +L_0x29ac910/d .functor AND 1, L_0x29abf10, L_0x29acbd0, C4<1>, C4<1>; +L_0x29ac910 .delay (20000,20000,20000) L_0x29ac910/d; +L_0x29aca00/d .functor OR 1, L_0x29ac860, L_0x29ac910, C4<0>, C4<0>; +L_0x29aca00 .delay (20000,20000,20000) L_0x29aca00/d; +v0x291f650_0 .net "S", 0 0, L_0x29acbd0; 1 drivers +v0x291f710_0 .alias "in0", 0 0, v0x291fd70_0; +v0x291f7b0_0 .alias "in1", 0 0, v0x2920360_0; +v0x291f850_0 .net "nS", 0 0, L_0x29ac0e0; 1 drivers +v0x291f8d0_0 .net "out0", 0 0, L_0x29ac860; 1 drivers +v0x291f970_0 .net "out1", 0 0, L_0x29ac910; 1 drivers +v0x291fa50_0 .alias "outfinal", 0 0, v0x291fe20_0; +S_0x291ef80 .scope module, "setSLTres2" "TwoInMux" 3 335, 3 109, S_0x291e710; + .timescale -9 -12; +L_0x29ac6e0/d .functor NOT 1, L_0x29d1680, C4<0>, C4<0>, C4<0>; +L_0x29ac6e0 .delay (10000,10000,10000) L_0x29ac6e0/d; +L_0x29ac780/d .functor AND 1, L_0x29adf70, L_0x29ac6e0, C4<1>, C4<1>; +L_0x29ac780 .delay (20000,20000,20000) L_0x29ac780/d; +L_0x29adcf0/d .functor AND 1, C4<0>, L_0x29d1680, C4<1>, C4<1>; +L_0x29adcf0 .delay (20000,20000,20000) L_0x29adcf0/d; +L_0x29add90/d .functor OR 1, L_0x29ac780, L_0x29adcf0, C4<0>, C4<0>; +L_0x29add90 .delay (20000,20000,20000) L_0x29add90/d; +v0x291f070_0 .alias "S", 0 0, v0x293b720_0; +v0x291f0f0_0 .net "in0", 0 0, L_0x29adf70; 1 drivers +v0x291f170_0 .net "in1", 0 0, C4<0>; 1 drivers +v0x291f1f0_0 .net "nS", 0 0, L_0x29ac6e0; 1 drivers +v0x291f270_0 .net "out0", 0 0, L_0x29ac780; 1 drivers +v0x291f2f0_0 .net "out1", 0 0, L_0x29adcf0; 1 drivers +v0x291f3d0_0 .net "outfinal", 0 0, L_0x29add90; 1 drivers +S_0x291e880 .scope module, "setSLTres3" "TwoInMux" 3 336, 3 109, S_0x291e710; + .timescale -9 -12; +L_0x29ad8b0/d .functor NOT 1, L_0x29d1680, C4<0>, C4<0>, C4<0>; +L_0x29ad8b0 .delay (10000,10000,10000) L_0x29ad8b0/d; +L_0x29ad9c0/d .functor AND 1, L_0x29ae670, L_0x29ad8b0, C4<1>, C4<1>; +L_0x29ad9c0 .delay (20000,20000,20000) L_0x29ad9c0/d; +L_0x29adad0/d .functor AND 1, L_0x29ae060, L_0x29d1680, C4<1>, C4<1>; +L_0x29adad0 .delay (20000,20000,20000) L_0x29adad0/d; +L_0x29adb70/d .functor OR 1, L_0x29ad9c0, L_0x29adad0, C4<0>, C4<0>; +L_0x29adb70 .delay (20000,20000,20000) L_0x29adb70/d; +v0x291e970_0 .alias "S", 0 0, v0x293b720_0; +v0x28f04c0_0 .net "in0", 0 0, L_0x29ae670; 1 drivers +v0x28f0560_0 .net "in1", 0 0, L_0x29ae060; 1 drivers +v0x28f0600_0 .net "nS", 0 0, L_0x29ad8b0; 1 drivers +v0x291ee00_0 .net "out0", 0 0, L_0x29ad9c0; 1 drivers +v0x291ee80_0 .net "out1", 0 0, L_0x29adad0; 1 drivers +v0x291ef00_0 .net "outfinal", 0 0, L_0x29adb70; 1 drivers +S_0x291ca90 .scope generate, "sltbits[16]" "sltbits[16]" 3 332, 3 332, S_0x28e1a50; + .timescale -9 -12; +P_0x291c4a8 .param/l "i" 3 332, +C4<010000>; +S_0x291d6f0 .scope module, "attempt" "MiddleAddSubSLT" 3 334, 3 189, S_0x291ca90; + .timescale -9 -12; +L_0x29ae150/d .functor NOT 1, L_0x29ae9e0, C4<0>, C4<0>, C4<0>; +L_0x29ae150 .delay (10000,10000,10000) L_0x29ae150/d; +L_0x29aeec0/d .functor NOT 1, L_0x29aef60, C4<0>, C4<0>, C4<0>; +L_0x29aeec0 .delay (10000,10000,10000) L_0x29aeec0/d; +L_0x29af000/d .functor AND 1, L_0x29af140, L_0x29aeec0, C4<1>, C4<1>; +L_0x29af000 .delay (20000,20000,20000) L_0x29af000/d; +L_0x29af1e0/d .functor XOR 1, L_0x29ae940, L_0x29aec90, C4<0>, C4<0>; +L_0x29af1e0 .delay (40000,40000,40000) L_0x29af1e0/d; +L_0x29af2d0/d .functor XOR 1, L_0x29af1e0, L_0x29aeb10, C4<0>, C4<0>; +L_0x29af2d0 .delay (40000,40000,40000) L_0x29af2d0/d; +L_0x29af3c0/d .functor AND 1, L_0x29ae940, L_0x29aec90, C4<1>, C4<1>; +L_0x29af3c0 .delay (20000,20000,20000) L_0x29af3c0/d; +L_0x29af560/d .functor AND 1, L_0x29af1e0, L_0x29aeb10, C4<1>, C4<1>; +L_0x29af560 .delay (20000,20000,20000) L_0x29af560/d; +L_0x29af650/d .functor OR 1, L_0x29af3c0, L_0x29af560, C4<0>, C4<0>; +L_0x29af650 .delay (20000,20000,20000) L_0x29af650/d; +v0x291dd70_0 .net "A", 0 0, L_0x29ae940; 1 drivers +v0x291de30_0 .net "AandB", 0 0, L_0x29af3c0; 1 drivers +v0x291ded0_0 .net "AddSubSLTSum", 0 0, L_0x29af2d0; 1 drivers +v0x291df70_0 .net "AxorB", 0 0, L_0x29af1e0; 1 drivers +v0x291dff0_0 .net "B", 0 0, L_0x29ae9e0; 1 drivers +v0x291e0a0_0 .net "BornB", 0 0, L_0x29aec90; 1 drivers +v0x291e160_0 .net "CINandAxorB", 0 0, L_0x29af560; 1 drivers +v0x291e1e0_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x291e260_0 .net *"_s3", 0 0, L_0x29aef60; 1 drivers +v0x291e2e0_0 .net *"_s5", 0 0, L_0x29af140; 1 drivers +v0x291e380_0 .net "carryin", 0 0, L_0x29aeb10; 1 drivers +v0x291e420_0 .net "carryout", 0 0, L_0x29af650; 1 drivers +v0x291e4c0_0 .net "nB", 0 0, L_0x29ae150; 1 drivers +v0x291e570_0 .net "nCmd2", 0 0, L_0x29aeec0; 1 drivers +v0x291e670_0 .net "subtract", 0 0, L_0x29af000; 1 drivers +L_0x29aee20 .part v0x2960210_0, 0, 1; +L_0x29aef60 .part v0x2960210_0, 2, 1; +L_0x29af140 .part v0x2960210_0, 0, 1; +S_0x291d7e0 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x291d6f0; + .timescale -9 -12; +L_0x29ae2e0/d .functor NOT 1, L_0x29aee20, C4<0>, C4<0>, C4<0>; +L_0x29ae2e0 .delay (10000,10000,10000) L_0x29ae2e0/d; +L_0x29ae3a0/d .functor AND 1, L_0x29ae9e0, L_0x29ae2e0, C4<1>, C4<1>; +L_0x29ae3a0 .delay (20000,20000,20000) L_0x29ae3a0/d; +L_0x29ae4b0/d .functor AND 1, L_0x29ae150, L_0x29aee20, C4<1>, C4<1>; +L_0x29ae4b0 .delay (20000,20000,20000) L_0x29ae4b0/d; +L_0x29aec90/d .functor OR 1, L_0x29ae3a0, L_0x29ae4b0, C4<0>, C4<0>; +L_0x29aec90 .delay (20000,20000,20000) L_0x29aec90/d; +v0x291d8d0_0 .net "S", 0 0, L_0x29aee20; 1 drivers +v0x291d990_0 .alias "in0", 0 0, v0x291dff0_0; +v0x291da30_0 .alias "in1", 0 0, v0x291e4c0_0; +v0x291dad0_0 .net "nS", 0 0, L_0x29ae2e0; 1 drivers +v0x291db50_0 .net "out0", 0 0, L_0x29ae3a0; 1 drivers +v0x291dbf0_0 .net "out1", 0 0, L_0x29ae4b0; 1 drivers +v0x291dcd0_0 .alias "outfinal", 0 0, v0x291e0a0_0; +S_0x291d180 .scope module, "setSLTres2" "TwoInMux" 3 335, 3 109, S_0x291ca90; + .timescale -9 -12; +L_0x29aebb0/d .functor NOT 1, L_0x29d1680, C4<0>, C4<0>, C4<0>; +L_0x29aebb0 .delay (10000,10000,10000) L_0x29aebb0/d; +L_0x299ea60/d .functor AND 1, L_0x29af8a0, L_0x29aebb0, C4<1>, C4<1>; +L_0x299ea60 .delay (20000,20000,20000) L_0x299ea60/d; +L_0x299eb30/d .functor AND 1, C4<0>, L_0x29d1680, C4<1>, C4<1>; +L_0x299eb30 .delay (20000,20000,20000) L_0x299eb30/d; +L_0x299ebd0/d .functor OR 1, L_0x299ea60, L_0x299eb30, C4<0>, C4<0>; +L_0x299ebd0 .delay (20000,20000,20000) L_0x299ebd0/d; +v0x291d270_0 .alias "S", 0 0, v0x293b720_0; +v0x291d310_0 .net "in0", 0 0, L_0x29af8a0; 1 drivers +v0x291d3b0_0 .net "in1", 0 0, C4<0>; 1 drivers +v0x291d450_0 .net "nS", 0 0, L_0x29aebb0; 1 drivers +v0x291d4d0_0 .net "out0", 0 0, L_0x299ea60; 1 drivers +v0x291d570_0 .net "out1", 0 0, L_0x299eb30; 1 drivers +v0x291d650_0 .net "outfinal", 0 0, L_0x299ebd0; 1 drivers +S_0x291cc00 .scope module, "setSLTres3" "TwoInMux" 3 336, 3 109, S_0x291ca90; + .timescale -9 -12; +L_0x299f0b0/d .functor NOT 1, L_0x29d1680, C4<0>, C4<0>, C4<0>; +L_0x299f0b0 .delay (10000,10000,10000) L_0x299f0b0/d; +L_0x299f1a0/d .functor AND 1, L_0x29b0350, L_0x299f0b0, C4<1>, C4<1>; +L_0x299f1a0 .delay (20000,20000,20000) L_0x299f1a0/d; +L_0x29b0910/d .functor AND 1, L_0x29b0440, L_0x29d1680, C4<1>, C4<1>; +L_0x29b0910 .delay (20000,20000,20000) L_0x29b0910/d; +L_0x29b09b0/d .functor OR 1, L_0x299f1a0, L_0x29b0910, C4<0>, C4<0>; +L_0x29b09b0 .delay (20000,20000,20000) L_0x29b09b0/d; +v0x291ccf0_0 .alias "S", 0 0, v0x293b720_0; +v0x291cd70_0 .net "in0", 0 0, L_0x29b0350; 1 drivers +v0x291ce10_0 .net "in1", 0 0, L_0x29b0440; 1 drivers +v0x291ceb0_0 .net "nS", 0 0, L_0x299f0b0; 1 drivers +v0x291cf60_0 .net "out0", 0 0, L_0x299f1a0; 1 drivers +v0x291d000_0 .net "out1", 0 0, L_0x29b0910; 1 drivers +v0x291d0e0_0 .net "outfinal", 0 0, L_0x29b09b0; 1 drivers +S_0x291ae10 .scope generate, "sltbits[17]" "sltbits[17]" 3 332, 3 332, S_0x28e1a50; + .timescale -9 -12; +P_0x291a828 .param/l "i" 3 332, +C4<010001>; +S_0x291ba70 .scope module, "attempt" "MiddleAddSubSLT" 3 334, 3 189, S_0x291ae10; + .timescale -9 -12; +L_0x29b0530/d .functor NOT 1, L_0x29b0d20, C4<0>, C4<0>, C4<0>; +L_0x29b0530 .delay (10000,10000,10000) L_0x29b0530/d; +L_0x29b1470/d .functor NOT 1, L_0x29b1530, C4<0>, C4<0>, C4<0>; +L_0x29b1470 .delay (10000,10000,10000) L_0x29b1470/d; +L_0x29b15d0/d .functor AND 1, L_0x29b1710, L_0x29b1470, C4<1>, C4<1>; +L_0x29b15d0 .delay (20000,20000,20000) L_0x29b15d0/d; +L_0x29b17b0/d .functor XOR 1, L_0x29b0c80, L_0x29b1220, C4<0>, C4<0>; +L_0x29b17b0 .delay (40000,40000,40000) L_0x29b17b0/d; +L_0x29b18a0/d .functor XOR 1, L_0x29b17b0, L_0x29b0e50, C4<0>, C4<0>; +L_0x29b18a0 .delay (40000,40000,40000) L_0x29b18a0/d; +L_0x29b19c0/d .functor AND 1, L_0x29b0c80, L_0x29b1220, C4<1>, C4<1>; +L_0x29b19c0 .delay (20000,20000,20000) L_0x29b19c0/d; +L_0x29b1b60/d .functor AND 1, L_0x29b17b0, L_0x29b0e50, C4<1>, C4<1>; +L_0x29b1b60 .delay (20000,20000,20000) L_0x29b1b60/d; +L_0x29b1c50/d .functor OR 1, L_0x29b19c0, L_0x29b1b60, C4<0>, C4<0>; +L_0x29b1c50 .delay (20000,20000,20000) L_0x29b1c50/d; +v0x291c0f0_0 .net "A", 0 0, L_0x29b0c80; 1 drivers +v0x291c1b0_0 .net "AandB", 0 0, L_0x29b19c0; 1 drivers +v0x291c250_0 .net "AddSubSLTSum", 0 0, L_0x29b18a0; 1 drivers +v0x291c2f0_0 .net "AxorB", 0 0, L_0x29b17b0; 1 drivers +v0x291c370_0 .net "B", 0 0, L_0x29b0d20; 1 drivers +v0x291c420_0 .net "BornB", 0 0, L_0x29b1220; 1 drivers +v0x291c4e0_0 .net "CINandAxorB", 0 0, L_0x29b1b60; 1 drivers +v0x291c560_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x291c5e0_0 .net *"_s3", 0 0, L_0x29b1530; 1 drivers +v0x291c660_0 .net *"_s5", 0 0, L_0x29b1710; 1 drivers +v0x291c700_0 .net "carryin", 0 0, L_0x29b0e50; 1 drivers +v0x291c7a0_0 .net "carryout", 0 0, L_0x29b1c50; 1 drivers +v0x291c840_0 .net "nB", 0 0, L_0x29b0530; 1 drivers +v0x291c8f0_0 .net "nCmd2", 0 0, L_0x29b1470; 1 drivers +v0x291c9f0_0 .net "subtract", 0 0, L_0x29b15d0; 1 drivers +L_0x29b13d0 .part v0x2960210_0, 0, 1; +L_0x29b1530 .part v0x2960210_0, 2, 1; +L_0x29b1710 .part v0x2960210_0, 0, 1; +S_0x291bb60 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x291ba70; + .timescale -9 -12; +L_0x29b0700/d .functor NOT 1, L_0x29b13d0, C4<0>, C4<0>, C4<0>; +L_0x29b0700 .delay (10000,10000,10000) L_0x29b0700/d; +L_0x29b07c0/d .functor AND 1, L_0x29b0d20, L_0x29b0700, C4<1>, C4<1>; +L_0x29b07c0 .delay (20000,20000,20000) L_0x29b07c0/d; +L_0x29b1170/d .functor AND 1, L_0x29b0530, L_0x29b13d0, C4<1>, C4<1>; +L_0x29b1170 .delay (20000,20000,20000) L_0x29b1170/d; +L_0x29b1220/d .functor OR 1, L_0x29b07c0, L_0x29b1170, C4<0>, C4<0>; +L_0x29b1220 .delay (20000,20000,20000) L_0x29b1220/d; +v0x291bc50_0 .net "S", 0 0, L_0x29b13d0; 1 drivers +v0x291bd10_0 .alias "in0", 0 0, v0x291c370_0; +v0x291bdb0_0 .alias "in1", 0 0, v0x291c840_0; +v0x291be50_0 .net "nS", 0 0, L_0x29b0700; 1 drivers +v0x291bed0_0 .net "out0", 0 0, L_0x29b07c0; 1 drivers +v0x291bf70_0 .net "out1", 0 0, L_0x29b1170; 1 drivers +v0x291c050_0 .alias "outfinal", 0 0, v0x291c420_0; +S_0x291b500 .scope module, "setSLTres2" "TwoInMux" 3 335, 3 109, S_0x291ae10; + .timescale -9 -12; +L_0x29b0ef0/d .functor NOT 1, L_0x29d1680, C4<0>, C4<0>, C4<0>; +L_0x29b0ef0 .delay (10000,10000,10000) L_0x29b0ef0/d; +L_0x29b0f70/d .functor AND 1, L_0x298d4a0, L_0x29b0ef0, C4<1>, C4<1>; +L_0x29b0f70 .delay (20000,20000,20000) L_0x29b0f70/d; +L_0x29b1080/d .functor AND 1, C4<0>, L_0x29d1680, C4<1>, C4<1>; +L_0x29b1080 .delay (20000,20000,20000) L_0x29b1080/d; +L_0x298d2c0/d .functor OR 1, L_0x29b0f70, L_0x29b1080, C4<0>, C4<0>; +L_0x298d2c0 .delay (20000,20000,20000) L_0x298d2c0/d; +v0x291b5f0_0 .alias "S", 0 0, v0x293b720_0; +v0x291b690_0 .net "in0", 0 0, L_0x298d4a0; 1 drivers +v0x291b730_0 .net "in1", 0 0, C4<0>; 1 drivers +v0x291b7d0_0 .net "nS", 0 0, L_0x29b0ef0; 1 drivers +v0x291b850_0 .net "out0", 0 0, L_0x29b0f70; 1 drivers +v0x291b8f0_0 .net "out1", 0 0, L_0x29b1080; 1 drivers +v0x291b9d0_0 .net "outfinal", 0 0, L_0x298d2c0; 1 drivers +S_0x291af80 .scope module, "setSLTres3" "TwoInMux" 3 336, 3 109, S_0x291ae10; + .timescale -9 -12; +L_0x298d6c0/d .functor NOT 1, L_0x29d1680, C4<0>, C4<0>, C4<0>; +L_0x298d6c0 .delay (10000,10000,10000) L_0x298d6c0/d; +L_0x298d7f0/d .functor AND 1, L_0x29b2030, L_0x298d6c0, C4<1>, C4<1>; +L_0x298d7f0 .delay (20000,20000,20000) L_0x298d7f0/d; +L_0x298d900/d .functor AND 1, L_0x29b2120, L_0x29d1680, C4<1>, C4<1>; +L_0x298d900 .delay (20000,20000,20000) L_0x298d900/d; +L_0x298d9a0/d .functor OR 1, L_0x298d7f0, L_0x298d900, C4<0>, C4<0>; +L_0x298d9a0 .delay (20000,20000,20000) L_0x298d9a0/d; +v0x291b070_0 .alias "S", 0 0, v0x293b720_0; +v0x291b0f0_0 .net "in0", 0 0, L_0x29b2030; 1 drivers +v0x291b190_0 .net "in1", 0 0, L_0x29b2120; 1 drivers +v0x291b230_0 .net "nS", 0 0, L_0x298d6c0; 1 drivers +v0x291b2e0_0 .net "out0", 0 0, L_0x298d7f0; 1 drivers +v0x291b380_0 .net "out1", 0 0, L_0x298d900; 1 drivers +v0x291b460_0 .net "outfinal", 0 0, L_0x298d9a0; 1 drivers +S_0x2919190 .scope generate, "sltbits[18]" "sltbits[18]" 3 332, 3 332, S_0x28e1a50; + .timescale -9 -12; +P_0x2918ba8 .param/l "i" 3 332, +C4<010010>; +S_0x2919df0 .scope module, "attempt" "MiddleAddSubSLT" 3 334, 3 189, S_0x2919190; + .timescale -9 -12; +L_0x29b2210/d .functor NOT 1, L_0x29b37e0, C4<0>, C4<0>, C4<0>; +L_0x29b2210 .delay (10000,10000,10000) L_0x29b2210/d; +L_0x29b3ea0/d .functor NOT 1, L_0x29b3f60, C4<0>, C4<0>, C4<0>; +L_0x29b3ea0 .delay (10000,10000,10000) L_0x29b3ea0/d; +L_0x29b4000/d .functor AND 1, L_0x29b4140, L_0x29b3ea0, C4<1>, C4<1>; +L_0x29b4000 .delay (20000,20000,20000) L_0x29b4000/d; +L_0x29b41e0/d .functor XOR 1, L_0x29b3740, L_0x29b3c30, C4<0>, C4<0>; +L_0x29b41e0 .delay (40000,40000,40000) L_0x29b41e0/d; +L_0x29b42d0/d .functor XOR 1, L_0x29b41e0, L_0x29b3910, C4<0>, C4<0>; +L_0x29b42d0 .delay (40000,40000,40000) L_0x29b42d0/d; +L_0x29b43c0/d .functor AND 1, L_0x29b3740, L_0x29b3c30, C4<1>, C4<1>; +L_0x29b43c0 .delay (20000,20000,20000) L_0x29b43c0/d; +L_0x29b4530/d .functor AND 1, L_0x29b41e0, L_0x29b3910, C4<1>, C4<1>; +L_0x29b4530 .delay (20000,20000,20000) L_0x29b4530/d; +L_0x29b4620/d .functor OR 1, L_0x29b43c0, L_0x29b4530, C4<0>, C4<0>; +L_0x29b4620 .delay (20000,20000,20000) L_0x29b4620/d; +v0x291a470_0 .net "A", 0 0, L_0x29b3740; 1 drivers +v0x291a530_0 .net "AandB", 0 0, L_0x29b43c0; 1 drivers +v0x291a5d0_0 .net "AddSubSLTSum", 0 0, L_0x29b42d0; 1 drivers +v0x291a670_0 .net "AxorB", 0 0, L_0x29b41e0; 1 drivers +v0x291a6f0_0 .net "B", 0 0, L_0x29b37e0; 1 drivers +v0x291a7a0_0 .net "BornB", 0 0, L_0x29b3c30; 1 drivers +v0x291a860_0 .net "CINandAxorB", 0 0, L_0x29b4530; 1 drivers +v0x291a8e0_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x291a960_0 .net *"_s3", 0 0, L_0x29b3f60; 1 drivers +v0x291a9e0_0 .net *"_s5", 0 0, L_0x29b4140; 1 drivers +v0x291aa80_0 .net "carryin", 0 0, L_0x29b3910; 1 drivers +v0x291ab20_0 .net "carryout", 0 0, L_0x29b4620; 1 drivers +v0x291abc0_0 .net "nB", 0 0, L_0x29b2210; 1 drivers +v0x291ac70_0 .net "nCmd2", 0 0, L_0x29b3ea0; 1 drivers +v0x291ad70_0 .net "subtract", 0 0, L_0x29b4000; 1 drivers +L_0x29b3e00 .part v0x2960210_0, 0, 1; +L_0x29b3f60 .part v0x2960210_0, 2, 1; +L_0x29b4140 .part v0x2960210_0, 0, 1; +S_0x2919ee0 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x2919df0; + .timescale -9 -12; +L_0x29b23a0/d .functor NOT 1, L_0x29b3e00, C4<0>, C4<0>, C4<0>; +L_0x29b23a0 .delay (10000,10000,10000) L_0x29b23a0/d; +L_0x29b2420/d .functor AND 1, L_0x29b37e0, L_0x29b23a0, C4<1>, C4<1>; +L_0x29b2420 .delay (20000,20000,20000) L_0x29b2420/d; +L_0x29b3b40/d .functor AND 1, L_0x29b2210, L_0x29b3e00, C4<1>, C4<1>; +L_0x29b3b40 .delay (20000,20000,20000) L_0x29b3b40/d; +L_0x29b3c30/d .functor OR 1, L_0x29b2420, L_0x29b3b40, C4<0>, C4<0>; +L_0x29b3c30 .delay (20000,20000,20000) L_0x29b3c30/d; +v0x2919fd0_0 .net "S", 0 0, L_0x29b3e00; 1 drivers +v0x291a090_0 .alias "in0", 0 0, v0x291a6f0_0; +v0x291a130_0 .alias "in1", 0 0, v0x291abc0_0; +v0x291a1d0_0 .net "nS", 0 0, L_0x29b23a0; 1 drivers +v0x291a250_0 .net "out0", 0 0, L_0x29b2420; 1 drivers +v0x291a2f0_0 .net "out1", 0 0, L_0x29b3b40; 1 drivers +v0x291a3d0_0 .alias "outfinal", 0 0, v0x291a7a0_0; +S_0x2919880 .scope module, "setSLTres2" "TwoInMux" 3 335, 3 109, S_0x2919190; + .timescale -9 -12; +L_0x29b39b0/d .functor NOT 1, L_0x29d1680, C4<0>, C4<0>, C4<0>; +L_0x29b39b0 .delay (10000,10000,10000) L_0x29b39b0/d; +L_0x29b3a50/d .functor AND 1, L_0x29794c0, L_0x29b39b0, C4<1>, C4<1>; +L_0x29b3a50 .delay (20000,20000,20000) L_0x29b3a50/d; +L_0x2979240/d .functor AND 1, C4<0>, L_0x29d1680, C4<1>, C4<1>; +L_0x2979240 .delay (20000,20000,20000) L_0x2979240/d; +L_0x29792e0/d .functor OR 1, L_0x29b3a50, L_0x2979240, C4<0>, C4<0>; +L_0x29792e0 .delay (20000,20000,20000) L_0x29792e0/d; +v0x2919970_0 .alias "S", 0 0, v0x293b720_0; +v0x2919a10_0 .net "in0", 0 0, L_0x29794c0; 1 drivers +v0x2919ab0_0 .net "in1", 0 0, C4<0>; 1 drivers +v0x2919b50_0 .net "nS", 0 0, L_0x29b39b0; 1 drivers +v0x2919bd0_0 .net "out0", 0 0, L_0x29b3a50; 1 drivers +v0x2919c70_0 .net "out1", 0 0, L_0x2979240; 1 drivers +v0x2919d50_0 .net "outfinal", 0 0, L_0x29792e0; 1 drivers +S_0x2919300 .scope module, "setSLTres3" "TwoInMux" 3 336, 3 109, S_0x2919190; + .timescale -9 -12; +L_0x2978ad0/d .functor NOT 1, L_0x29d1680, C4<0>, C4<0>, C4<0>; +L_0x2978ad0 .delay (10000,10000,10000) L_0x2978ad0/d; +L_0x2978be0/d .functor AND 1, L_0x29b4960, L_0x2978ad0, C4<1>, C4<1>; +L_0x2978be0 .delay (20000,20000,20000) L_0x2978be0/d; +L_0x2978cf0/d .functor AND 1, L_0x29b4a50, L_0x29d1680, C4<1>, C4<1>; +L_0x2978cf0 .delay (20000,20000,20000) L_0x2978cf0/d; +L_0x2978d90/d .functor OR 1, L_0x2978be0, L_0x2978cf0, C4<0>, C4<0>; +L_0x2978d90 .delay (20000,20000,20000) L_0x2978d90/d; +v0x29193f0_0 .alias "S", 0 0, v0x293b720_0; +v0x2919470_0 .net "in0", 0 0, L_0x29b4960; 1 drivers +v0x2919510_0 .net "in1", 0 0, L_0x29b4a50; 1 drivers +v0x29195b0_0 .net "nS", 0 0, L_0x2978ad0; 1 drivers +v0x2919660_0 .net "out0", 0 0, L_0x2978be0; 1 drivers +v0x2919700_0 .net "out1", 0 0, L_0x2978cf0; 1 drivers +v0x29197e0_0 .net "outfinal", 0 0, L_0x2978d90; 1 drivers +S_0x2917510 .scope generate, "sltbits[19]" "sltbits[19]" 3 332, 3 332, S_0x28e1a50; + .timescale -9 -12; +P_0x2916f28 .param/l "i" 3 332, +C4<010011>; +S_0x2918170 .scope module, "attempt" "MiddleAddSubSLT" 3 334, 3 189, S_0x2917510; + .timescale -9 -12; +L_0x29b4b40/d .functor NOT 1, L_0x29b6020, C4<0>, C4<0>, C4<0>; +L_0x29b4b40 .delay (10000,10000,10000) L_0x29b4b40/d; +L_0x29b68a0/d .functor NOT 1, L_0x29b6960, C4<0>, C4<0>, C4<0>; +L_0x29b68a0 .delay (10000,10000,10000) L_0x29b68a0/d; +L_0x29b6a00/d .functor AND 1, L_0x29b6b40, L_0x29b68a0, C4<1>, C4<1>; +L_0x29b6a00 .delay (20000,20000,20000) L_0x29b6a00/d; +L_0x29b6be0/d .functor XOR 1, L_0x29b5f80, L_0x29b6630, C4<0>, C4<0>; +L_0x29b6be0 .delay (40000,40000,40000) L_0x29b6be0/d; +L_0x29b6cd0/d .functor XOR 1, L_0x29b6be0, L_0x29b6150, C4<0>, C4<0>; +L_0x29b6cd0 .delay (40000,40000,40000) L_0x29b6cd0/d; +L_0x29b6dc0/d .functor AND 1, L_0x29b5f80, L_0x29b6630, C4<1>, C4<1>; +L_0x29b6dc0 .delay (20000,20000,20000) L_0x29b6dc0/d; +L_0x29b6f30/d .functor AND 1, L_0x29b6be0, L_0x29b6150, C4<1>, C4<1>; +L_0x29b6f30 .delay (20000,20000,20000) L_0x29b6f30/d; +L_0x29b7020/d .functor OR 1, L_0x29b6dc0, L_0x29b6f30, C4<0>, C4<0>; +L_0x29b7020 .delay (20000,20000,20000) L_0x29b7020/d; +v0x29187f0_0 .net "A", 0 0, L_0x29b5f80; 1 drivers +v0x29188b0_0 .net "AandB", 0 0, L_0x29b6dc0; 1 drivers +v0x2918950_0 .net "AddSubSLTSum", 0 0, L_0x29b6cd0; 1 drivers +v0x29189f0_0 .net "AxorB", 0 0, L_0x29b6be0; 1 drivers +v0x2918a70_0 .net "B", 0 0, L_0x29b6020; 1 drivers +v0x2918b20_0 .net "BornB", 0 0, L_0x29b6630; 1 drivers +v0x2918be0_0 .net "CINandAxorB", 0 0, L_0x29b6f30; 1 drivers +v0x2918c60_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x2918ce0_0 .net *"_s3", 0 0, L_0x29b6960; 1 drivers +v0x2918d60_0 .net *"_s5", 0 0, L_0x29b6b40; 1 drivers +v0x2918e00_0 .net "carryin", 0 0, L_0x29b6150; 1 drivers +v0x2918ea0_0 .net "carryout", 0 0, L_0x29b7020; 1 drivers +v0x2918f40_0 .net "nB", 0 0, L_0x29b4b40; 1 drivers +v0x2918ff0_0 .net "nCmd2", 0 0, L_0x29b68a0; 1 drivers +v0x29190f0_0 .net "subtract", 0 0, L_0x29b6a00; 1 drivers +L_0x29b6800 .part v0x2960210_0, 0, 1; +L_0x29b6960 .part v0x2960210_0, 2, 1; +L_0x29b6b40 .part v0x2960210_0, 0, 1; +S_0x2918260 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x2918170; + .timescale -9 -12; +L_0x29b4d10/d .functor NOT 1, L_0x29b6800, C4<0>, C4<0>, C4<0>; +L_0x29b4d10 .delay (10000,10000,10000) L_0x29b4d10/d; +L_0x29b4dd0/d .functor AND 1, L_0x29b6020, L_0x29b4d10, C4<1>, C4<1>; +L_0x29b4dd0 .delay (20000,20000,20000) L_0x29b4dd0/d; +L_0x29b6520/d .functor AND 1, L_0x29b4b40, L_0x29b6800, C4<1>, C4<1>; +L_0x29b6520 .delay (20000,20000,20000) L_0x29b6520/d; +L_0x29b6630/d .functor OR 1, L_0x29b4dd0, L_0x29b6520, C4<0>, C4<0>; +L_0x29b6630 .delay (20000,20000,20000) L_0x29b6630/d; +v0x2918350_0 .net "S", 0 0, L_0x29b6800; 1 drivers +v0x2918410_0 .alias "in0", 0 0, v0x2918a70_0; +v0x29184b0_0 .alias "in1", 0 0, v0x2918f40_0; +v0x2918550_0 .net "nS", 0 0, L_0x29b4d10; 1 drivers +v0x29185d0_0 .net "out0", 0 0, L_0x29b4dd0; 1 drivers +v0x2918670_0 .net "out1", 0 0, L_0x29b6520; 1 drivers +v0x2918750_0 .alias "outfinal", 0 0, v0x2918b20_0; +S_0x2917c00 .scope module, "setSLTres2" "TwoInMux" 3 335, 3 109, S_0x2917510; + .timescale -9 -12; +L_0x29b61f0/d .functor NOT 1, L_0x29d1680, C4<0>, C4<0>, C4<0>; +L_0x29b61f0 .delay (10000,10000,10000) L_0x29b61f0/d; +L_0x29b6290/d .functor AND 1, L_0x29b7b50, L_0x29b61f0, C4<1>, C4<1>; +L_0x29b6290 .delay (20000,20000,20000) L_0x29b6290/d; +L_0x29b63a0/d .functor AND 1, C4<0>, L_0x29d1680, C4<1>, C4<1>; +L_0x29b63a0 .delay (20000,20000,20000) L_0x29b63a0/d; +L_0x29b6440/d .functor OR 1, L_0x29b6290, L_0x29b63a0, C4<0>, C4<0>; +L_0x29b6440 .delay (20000,20000,20000) L_0x29b6440/d; +v0x2917cf0_0 .alias "S", 0 0, v0x293b720_0; +v0x2917d90_0 .net "in0", 0 0, L_0x29b7b50; 1 drivers +v0x2917e30_0 .net "in1", 0 0, C4<0>; 1 drivers +v0x2917ed0_0 .net "nS", 0 0, L_0x29b61f0; 1 drivers +v0x2917f50_0 .net "out0", 0 0, L_0x29b6290; 1 drivers +v0x2917ff0_0 .net "out1", 0 0, L_0x29b63a0; 1 drivers +v0x29180d0_0 .net "outfinal", 0 0, L_0x29b6440; 1 drivers +S_0x2917680 .scope module, "setSLTres3" "TwoInMux" 3 336, 3 109, S_0x2917510; + .timescale -9 -12; +L_0x29b74a0/d .functor NOT 1, L_0x29d1680, C4<0>, C4<0>, C4<0>; +L_0x29b74a0 .delay (10000,10000,10000) L_0x29b74a0/d; +L_0x29b75b0/d .functor AND 1, L_0x29b78a0, L_0x29b74a0, C4<1>, C4<1>; +L_0x29b75b0 .delay (20000,20000,20000) L_0x29b75b0/d; +L_0x29b76c0/d .functor AND 1, L_0x29b82d0, L_0x29d1680, C4<1>, C4<1>; +L_0x29b76c0 .delay (20000,20000,20000) L_0x29b76c0/d; +L_0x29b7760/d .functor OR 1, L_0x29b75b0, L_0x29b76c0, C4<0>, C4<0>; +L_0x29b7760 .delay (20000,20000,20000) L_0x29b7760/d; +v0x2917770_0 .alias "S", 0 0, v0x293b720_0; +v0x29177f0_0 .net "in0", 0 0, L_0x29b78a0; 1 drivers +v0x2917890_0 .net "in1", 0 0, L_0x29b82d0; 1 drivers +v0x2917930_0 .net "nS", 0 0, L_0x29b74a0; 1 drivers +v0x29179e0_0 .net "out0", 0 0, L_0x29b75b0; 1 drivers +v0x2917a80_0 .net "out1", 0 0, L_0x29b76c0; 1 drivers +v0x2917b60_0 .net "outfinal", 0 0, L_0x29b7760; 1 drivers +S_0x2915890 .scope generate, "sltbits[20]" "sltbits[20]" 3 332, 3 332, S_0x28e1a50; + .timescale -9 -12; +P_0x29152a8 .param/l "i" 3 332, +C4<010100>; +S_0x29164f0 .scope module, "attempt" "MiddleAddSubSLT" 3 334, 3 189, S_0x2915890; + .timescale -9 -12; +L_0x29b83c0/d .functor NOT 1, L_0x29b7ec0, C4<0>, C4<0>, C4<0>; +L_0x29b83c0 .delay (10000,10000,10000) L_0x29b83c0/d; +L_0x29b8a80/d .functor NOT 1, L_0x29b8b40, C4<0>, C4<0>, C4<0>; +L_0x29b8a80 .delay (10000,10000,10000) L_0x29b8a80/d; +L_0x29b8be0/d .functor AND 1, L_0x29b8d20, L_0x29b8a80, C4<1>, C4<1>; +L_0x29b8be0 .delay (20000,20000,20000) L_0x29b8be0/d; +L_0x29b8dc0/d .functor XOR 1, L_0x29b7e20, L_0x29b8810, C4<0>, C4<0>; +L_0x29b8dc0 .delay (40000,40000,40000) L_0x29b8dc0/d; +L_0x29b8eb0/d .functor XOR 1, L_0x29b8dc0, L_0x29b7ff0, C4<0>, C4<0>; +L_0x29b8eb0 .delay (40000,40000,40000) L_0x29b8eb0/d; +L_0x29b8fa0/d .functor AND 1, L_0x29b7e20, L_0x29b8810, C4<1>, C4<1>; +L_0x29b8fa0 .delay (20000,20000,20000) L_0x29b8fa0/d; +L_0x29b9110/d .functor AND 1, L_0x29b8dc0, L_0x29b7ff0, C4<1>, C4<1>; +L_0x29b9110 .delay (20000,20000,20000) L_0x29b9110/d; +L_0x29b9200/d .functor OR 1, L_0x29b8fa0, L_0x29b9110, C4<0>, C4<0>; +L_0x29b9200 .delay (20000,20000,20000) L_0x29b9200/d; +v0x2916b70_0 .net "A", 0 0, L_0x29b7e20; 1 drivers +v0x2916c30_0 .net "AandB", 0 0, L_0x29b8fa0; 1 drivers +v0x2916cd0_0 .net "AddSubSLTSum", 0 0, L_0x29b8eb0; 1 drivers +v0x2916d70_0 .net "AxorB", 0 0, L_0x29b8dc0; 1 drivers +v0x2916df0_0 .net "B", 0 0, L_0x29b7ec0; 1 drivers +v0x2916ea0_0 .net "BornB", 0 0, L_0x29b8810; 1 drivers +v0x2916f60_0 .net "CINandAxorB", 0 0, L_0x29b9110; 1 drivers +v0x2916fe0_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x2917060_0 .net *"_s3", 0 0, L_0x29b8b40; 1 drivers +v0x29170e0_0 .net *"_s5", 0 0, L_0x29b8d20; 1 drivers +v0x2917180_0 .net "carryin", 0 0, L_0x29b7ff0; 1 drivers +v0x2917220_0 .net "carryout", 0 0, L_0x29b9200; 1 drivers +v0x29172c0_0 .net "nB", 0 0, L_0x29b83c0; 1 drivers +v0x2917370_0 .net "nCmd2", 0 0, L_0x29b8a80; 1 drivers +v0x2917470_0 .net "subtract", 0 0, L_0x29b8be0; 1 drivers +L_0x29b89e0 .part v0x2960210_0, 0, 1; +L_0x29b8b40 .part v0x2960210_0, 2, 1; +L_0x29b8d20 .part v0x2960210_0, 0, 1; +S_0x29165e0 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x29164f0; + .timescale -9 -12; +L_0x29b8530/d .functor NOT 1, L_0x29b89e0, C4<0>, C4<0>, C4<0>; +L_0x29b8530 .delay (10000,10000,10000) L_0x29b8530/d; +L_0x29b85f0/d .functor AND 1, L_0x29b7ec0, L_0x29b8530, C4<1>, C4<1>; +L_0x29b85f0 .delay (20000,20000,20000) L_0x29b85f0/d; +L_0x29b8700/d .functor AND 1, L_0x29b83c0, L_0x29b89e0, C4<1>, C4<1>; +L_0x29b8700 .delay (20000,20000,20000) L_0x29b8700/d; +L_0x29b8810/d .functor OR 1, L_0x29b85f0, L_0x29b8700, C4<0>, C4<0>; +L_0x29b8810 .delay (20000,20000,20000) L_0x29b8810/d; +v0x29166d0_0 .net "S", 0 0, L_0x29b89e0; 1 drivers +v0x2916790_0 .alias "in0", 0 0, v0x2916df0_0; +v0x2916830_0 .alias "in1", 0 0, v0x29172c0_0; +v0x29168d0_0 .net "nS", 0 0, L_0x29b8530; 1 drivers +v0x2916950_0 .net "out0", 0 0, L_0x29b85f0; 1 drivers +v0x29169f0_0 .net "out1", 0 0, L_0x29b8700; 1 drivers +v0x2916ad0_0 .alias "outfinal", 0 0, v0x2916ea0_0; +S_0x2915f80 .scope module, "setSLTres2" "TwoInMux" 3 335, 3 109, S_0x2915890; + .timescale -9 -12; +L_0x29b8090/d .functor NOT 1, L_0x29d1680, C4<0>, C4<0>, C4<0>; +L_0x29b8090 .delay (10000,10000,10000) L_0x29b8090/d; +L_0x29b8130/d .functor AND 1, L_0x29b9450, L_0x29b8090, C4<1>, C4<1>; +L_0x29b8130 .delay (20000,20000,20000) L_0x29b8130/d; +L_0x29b8240/d .functor AND 1, C4<0>, L_0x29d1680, C4<1>, C4<1>; +L_0x29b8240 .delay (20000,20000,20000) L_0x29b8240/d; +L_0x29b9b50/d .functor OR 1, L_0x29b8130, L_0x29b8240, C4<0>, C4<0>; +L_0x29b9b50 .delay (20000,20000,20000) L_0x29b9b50/d; +v0x2916070_0 .alias "S", 0 0, v0x293b720_0; +v0x2916110_0 .net "in0", 0 0, L_0x29b9450; 1 drivers +v0x29161b0_0 .net "in1", 0 0, C4<0>; 1 drivers +v0x2916250_0 .net "nS", 0 0, L_0x29b8090; 1 drivers +v0x29162d0_0 .net "out0", 0 0, L_0x29b8130; 1 drivers +v0x2916370_0 .net "out1", 0 0, L_0x29b8240; 1 drivers +v0x2916450_0 .net "outfinal", 0 0, L_0x29b9b50; 1 drivers +S_0x2915a00 .scope module, "setSLTres3" "TwoInMux" 3 336, 3 109, S_0x2915890; + .timescale -9 -12; +L_0x29b95d0/d .functor NOT 1, L_0x29d1680, C4<0>, C4<0>, C4<0>; +L_0x29b95d0 .delay (10000,10000,10000) L_0x29b95d0/d; +L_0x29b96e0/d .functor AND 1, L_0x29b9a70, L_0x29b95d0, C4<1>, C4<1>; +L_0x29b96e0 .delay (20000,20000,20000) L_0x29b96e0/d; +L_0x29b97f0/d .functor AND 1, L_0x29ba460, L_0x29d1680, C4<1>, C4<1>; +L_0x29b97f0 .delay (20000,20000,20000) L_0x29b97f0/d; +L_0x29b9890/d .functor OR 1, L_0x29b96e0, L_0x29b97f0, C4<0>, C4<0>; +L_0x29b9890 .delay (20000,20000,20000) L_0x29b9890/d; +v0x2915af0_0 .alias "S", 0 0, v0x293b720_0; +v0x2915b70_0 .net "in0", 0 0, L_0x29b9a70; 1 drivers +v0x2915c10_0 .net "in1", 0 0, L_0x29ba460; 1 drivers +v0x2915cb0_0 .net "nS", 0 0, L_0x29b95d0; 1 drivers +v0x2915d60_0 .net "out0", 0 0, L_0x29b96e0; 1 drivers +v0x2915e00_0 .net "out1", 0 0, L_0x29b97f0; 1 drivers +v0x2915ee0_0 .net "outfinal", 0 0, L_0x29b9890; 1 drivers +S_0x2913c10 .scope generate, "sltbits[21]" "sltbits[21]" 3 332, 3 332, S_0x28e1a50; + .timescale -9 -12; +P_0x2913628 .param/l "i" 3 332, +C4<010101>; +S_0x2914870 .scope module, "attempt" "MiddleAddSubSLT" 3 334, 3 189, S_0x2913c10; + .timescale -9 -12; +L_0x29b9d30/d .functor NOT 1, L_0x29ba6e0, C4<0>, C4<0>, C4<0>; +L_0x29b9d30 .delay (10000,10000,10000) L_0x29b9d30/d; +L_0x29ba3b0/d .functor NOT 1, L_0x29bad20, C4<0>, C4<0>, C4<0>; +L_0x29ba3b0 .delay (10000,10000,10000) L_0x29ba3b0/d; +L_0x29badc0/d .functor AND 1, L_0x29baf00, L_0x29ba3b0, C4<1>, C4<1>; +L_0x29badc0 .delay (20000,20000,20000) L_0x29badc0/d; +L_0x29bafa0/d .functor XOR 1, L_0x29ba640, L_0x29ba1e0, C4<0>, C4<0>; +L_0x29bafa0 .delay (40000,40000,40000) L_0x29bafa0/d; +L_0x29bb090/d .functor XOR 1, L_0x29bafa0, L_0x29ba810, C4<0>, C4<0>; +L_0x29bb090 .delay (40000,40000,40000) L_0x29bb090/d; +L_0x29bb180/d .functor AND 1, L_0x29ba640, L_0x29ba1e0, C4<1>, C4<1>; +L_0x29bb180 .delay (20000,20000,20000) L_0x29bb180/d; +L_0x29bb2f0/d .functor AND 1, L_0x29bafa0, L_0x29ba810, C4<1>, C4<1>; +L_0x29bb2f0 .delay (20000,20000,20000) L_0x29bb2f0/d; +L_0x29bb3e0/d .functor OR 1, L_0x29bb180, L_0x29bb2f0, C4<0>, C4<0>; +L_0x29bb3e0 .delay (20000,20000,20000) L_0x29bb3e0/d; +v0x2914ef0_0 .net "A", 0 0, L_0x29ba640; 1 drivers +v0x2914fb0_0 .net "AandB", 0 0, L_0x29bb180; 1 drivers +v0x2915050_0 .net "AddSubSLTSum", 0 0, L_0x29bb090; 1 drivers +v0x29150f0_0 .net "AxorB", 0 0, L_0x29bafa0; 1 drivers +v0x2915170_0 .net "B", 0 0, L_0x29ba6e0; 1 drivers +v0x2915220_0 .net "BornB", 0 0, L_0x29ba1e0; 1 drivers +v0x29152e0_0 .net "CINandAxorB", 0 0, L_0x29bb2f0; 1 drivers +v0x2915360_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x29153e0_0 .net *"_s3", 0 0, L_0x29bad20; 1 drivers +v0x2915460_0 .net *"_s5", 0 0, L_0x29baf00; 1 drivers +v0x2915500_0 .net "carryin", 0 0, L_0x29ba810; 1 drivers +v0x29155a0_0 .net "carryout", 0 0, L_0x29bb3e0; 1 drivers +v0x2915640_0 .net "nB", 0 0, L_0x29b9d30; 1 drivers +v0x29156f0_0 .net "nCmd2", 0 0, L_0x29ba3b0; 1 drivers +v0x29157f0_0 .net "subtract", 0 0, L_0x29badc0; 1 drivers +L_0x29bac40 .part v0x2960210_0, 0, 1; +L_0x29bad20 .part v0x2960210_0, 2, 1; +L_0x29baf00 .part v0x2960210_0, 0, 1; +S_0x2914960 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x2914870; + .timescale -9 -12; +L_0x29b9f00/d .functor NOT 1, L_0x29bac40, C4<0>, C4<0>, C4<0>; +L_0x29b9f00 .delay (10000,10000,10000) L_0x29b9f00/d; +L_0x29b9fc0/d .functor AND 1, L_0x29ba6e0, L_0x29b9f00, C4<1>, C4<1>; +L_0x29b9fc0 .delay (20000,20000,20000) L_0x29b9fc0/d; +L_0x29ba0d0/d .functor AND 1, L_0x29b9d30, L_0x29bac40, C4<1>, C4<1>; +L_0x29ba0d0 .delay (20000,20000,20000) L_0x29ba0d0/d; +L_0x29ba1e0/d .functor OR 1, L_0x29b9fc0, L_0x29ba0d0, C4<0>, C4<0>; +L_0x29ba1e0 .delay (20000,20000,20000) L_0x29ba1e0/d; +v0x2914a50_0 .net "S", 0 0, L_0x29bac40; 1 drivers +v0x2914b10_0 .alias "in0", 0 0, v0x2915170_0; +v0x2914bb0_0 .alias "in1", 0 0, v0x2915640_0; +v0x2914c50_0 .net "nS", 0 0, L_0x29b9f00; 1 drivers +v0x2914cd0_0 .net "out0", 0 0, L_0x29b9fc0; 1 drivers +v0x2914d70_0 .net "out1", 0 0, L_0x29ba0d0; 1 drivers +v0x2914e50_0 .alias "outfinal", 0 0, v0x2915220_0; +S_0x2914300 .scope module, "setSLTres2" "TwoInMux" 3 335, 3 109, S_0x2913c10; + .timescale -9 -12; +L_0x29ba8b0/d .functor NOT 1, L_0x29d1680, C4<0>, C4<0>, C4<0>; +L_0x29ba8b0 .delay (10000,10000,10000) L_0x29ba8b0/d; +L_0x29ba950/d .functor AND 1, L_0x29bbee0, L_0x29ba8b0, C4<1>, C4<1>; +L_0x29ba950 .delay (20000,20000,20000) L_0x29ba950/d; +L_0x29baa60/d .functor AND 1, C4<0>, L_0x29d1680, C4<1>, C4<1>; +L_0x29baa60 .delay (20000,20000,20000) L_0x29baa60/d; +L_0x29bab00/d .functor OR 1, L_0x29ba950, L_0x29baa60, C4<0>, C4<0>; +L_0x29bab00 .delay (20000,20000,20000) L_0x29bab00/d; +v0x29143f0_0 .alias "S", 0 0, v0x293b720_0; +v0x2914490_0 .net "in0", 0 0, L_0x29bbee0; 1 drivers +v0x2914530_0 .net "in1", 0 0, C4<0>; 1 drivers +v0x29145d0_0 .net "nS", 0 0, L_0x29ba8b0; 1 drivers +v0x2914650_0 .net "out0", 0 0, L_0x29ba950; 1 drivers +v0x29146f0_0 .net "out1", 0 0, L_0x29baa60; 1 drivers +v0x29147d0_0 .net "outfinal", 0 0, L_0x29bab00; 1 drivers +S_0x2913d80 .scope module, "setSLTres3" "TwoInMux" 3 336, 3 109, S_0x2913c10; + .timescale -9 -12; +L_0x29bb870/d .functor NOT 1, L_0x29d1680, C4<0>, C4<0>, C4<0>; +L_0x29bb870 .delay (10000,10000,10000) L_0x29bb870/d; +L_0x29bb980/d .functor AND 1, L_0x29bbd10, L_0x29bb870, C4<1>, C4<1>; +L_0x29bb980 .delay (20000,20000,20000) L_0x29bb980/d; +L_0x29bba90/d .functor AND 1, L_0x29b73f0, L_0x29d1680, C4<1>, C4<1>; +L_0x29bba90 .delay (20000,20000,20000) L_0x29bba90/d; +L_0x29bbb30/d .functor OR 1, L_0x29bb980, L_0x29bba90, C4<0>, C4<0>; +L_0x29bbb30 .delay (20000,20000,20000) L_0x29bbb30/d; +v0x2913e70_0 .alias "S", 0 0, v0x293b720_0; +v0x2913ef0_0 .net "in0", 0 0, L_0x29bbd10; 1 drivers +v0x2913f90_0 .net "in1", 0 0, L_0x29b73f0; 1 drivers +v0x2914030_0 .net "nS", 0 0, L_0x29bb870; 1 drivers +v0x29140e0_0 .net "out0", 0 0, L_0x29bb980; 1 drivers +v0x2914180_0 .net "out1", 0 0, L_0x29bba90; 1 drivers +v0x2914260_0 .net "outfinal", 0 0, L_0x29bbb30; 1 drivers +S_0x2911f90 .scope generate, "sltbits[22]" "sltbits[22]" 3 332, 3 332, S_0x28e1a50; + .timescale -9 -12; +P_0x2911888 .param/l "i" 3 332, +C4<010110>; +S_0x2912bf0 .scope module, "attempt" "MiddleAddSubSLT" 3 334, 3 189, S_0x2911f90; + .timescale -9 -12; +L_0x29bc760/d .functor NOT 1, L_0x29bc250, C4<0>, C4<0>, C4<0>; +L_0x29bc760 .delay (10000,10000,10000) L_0x29bc760/d; +L_0x29bce40/d .functor NOT 1, L_0x29bcf00, C4<0>, C4<0>, C4<0>; +L_0x29bce40 .delay (10000,10000,10000) L_0x29bce40/d; +L_0x29bcfa0/d .functor AND 1, L_0x29bd0e0, L_0x29bce40, C4<1>, C4<1>; +L_0x29bcfa0 .delay (20000,20000,20000) L_0x29bcfa0/d; +L_0x29bd180/d .functor XOR 1, L_0x29bc1b0, L_0x29bcbd0, C4<0>, C4<0>; +L_0x29bd180 .delay (40000,40000,40000) L_0x29bd180/d; +L_0x29bd270/d .functor XOR 1, L_0x29bd180, L_0x29bc380, C4<0>, C4<0>; +L_0x29bd270 .delay (40000,40000,40000) L_0x29bd270/d; +L_0x29bd360/d .functor AND 1, L_0x29bc1b0, L_0x29bcbd0, C4<1>, C4<1>; +L_0x29bd360 .delay (20000,20000,20000) L_0x29bd360/d; +L_0x29bd4d0/d .functor AND 1, L_0x29bd180, L_0x29bc380, C4<1>, C4<1>; +L_0x29bd4d0 .delay (20000,20000,20000) L_0x29bd4d0/d; +L_0x29bd5c0/d .functor OR 1, L_0x29bd360, L_0x29bd4d0, C4<0>, C4<0>; +L_0x29bd5c0 .delay (20000,20000,20000) L_0x29bd5c0/d; +v0x2913270_0 .net "A", 0 0, L_0x29bc1b0; 1 drivers +v0x2913330_0 .net "AandB", 0 0, L_0x29bd360; 1 drivers +v0x29133d0_0 .net "AddSubSLTSum", 0 0, L_0x29bd270; 1 drivers +v0x2913470_0 .net "AxorB", 0 0, L_0x29bd180; 1 drivers +v0x29134f0_0 .net "B", 0 0, L_0x29bc250; 1 drivers +v0x29135a0_0 .net "BornB", 0 0, L_0x29bcbd0; 1 drivers +v0x2913660_0 .net "CINandAxorB", 0 0, L_0x29bd4d0; 1 drivers +v0x29136e0_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x2913760_0 .net *"_s3", 0 0, L_0x29bcf00; 1 drivers +v0x29137e0_0 .net *"_s5", 0 0, L_0x29bd0e0; 1 drivers +v0x2913880_0 .net "carryin", 0 0, L_0x29bc380; 1 drivers +v0x2913920_0 .net "carryout", 0 0, L_0x29bd5c0; 1 drivers +v0x29139c0_0 .net "nB", 0 0, L_0x29bc760; 1 drivers +v0x2913a70_0 .net "nCmd2", 0 0, L_0x29bce40; 1 drivers +v0x2913b70_0 .net "subtract", 0 0, L_0x29bcfa0; 1 drivers +L_0x29bcda0 .part v0x2960210_0, 0, 1; +L_0x29bcf00 .part v0x2960210_0, 2, 1; +L_0x29bd0e0 .part v0x2960210_0, 0, 1; +S_0x2912ce0 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x2912bf0; + .timescale -9 -12; +L_0x29bc8f0/d .functor NOT 1, L_0x29bcda0, C4<0>, C4<0>, C4<0>; +L_0x29bc8f0 .delay (10000,10000,10000) L_0x29bc8f0/d; +L_0x29bc9b0/d .functor AND 1, L_0x29bc250, L_0x29bc8f0, C4<1>, C4<1>; +L_0x29bc9b0 .delay (20000,20000,20000) L_0x29bc9b0/d; +L_0x29bcac0/d .functor AND 1, L_0x29bc760, L_0x29bcda0, C4<1>, C4<1>; +L_0x29bcac0 .delay (20000,20000,20000) L_0x29bcac0/d; +L_0x29bcbd0/d .functor OR 1, L_0x29bc9b0, L_0x29bcac0, C4<0>, C4<0>; +L_0x29bcbd0 .delay (20000,20000,20000) L_0x29bcbd0/d; +v0x2912dd0_0 .net "S", 0 0, L_0x29bcda0; 1 drivers +v0x2912e90_0 .alias "in0", 0 0, v0x29134f0_0; +v0x2912f30_0 .alias "in1", 0 0, v0x29139c0_0; +v0x2912fd0_0 .net "nS", 0 0, L_0x29bc8f0; 1 drivers +v0x2913050_0 .net "out0", 0 0, L_0x29bc9b0; 1 drivers +v0x29130f0_0 .net "out1", 0 0, L_0x29bcac0; 1 drivers +v0x29131d0_0 .alias "outfinal", 0 0, v0x29135a0_0; +S_0x2912680 .scope module, "setSLTres2" "TwoInMux" 3 335, 3 109, S_0x2911f90; + .timescale -9 -12; +L_0x29bc420/d .functor NOT 1, L_0x29d1680, C4<0>, C4<0>, C4<0>; +L_0x29bc420 .delay (10000,10000,10000) L_0x29bc420/d; +L_0x29bc4c0/d .functor AND 1, L_0x29a5b70, L_0x29bc420, C4<1>, C4<1>; +L_0x29bc4c0 .delay (20000,20000,20000) L_0x29bc4c0/d; +L_0x29bc5d0/d .functor AND 1, C4<0>, L_0x29d1680, C4<1>, C4<1>; +L_0x29bc5d0 .delay (20000,20000,20000) L_0x29bc5d0/d; +L_0x29bc670/d .functor OR 1, L_0x29bc4c0, L_0x29bc5d0, C4<0>, C4<0>; +L_0x29bc670 .delay (20000,20000,20000) L_0x29bc670/d; +v0x2912770_0 .alias "S", 0 0, v0x293b720_0; +v0x2912810_0 .net "in0", 0 0, L_0x29a5b70; 1 drivers +v0x29128b0_0 .net "in1", 0 0, C4<0>; 1 drivers +v0x2912950_0 .net "nS", 0 0, L_0x29bc420; 1 drivers +v0x29129d0_0 .net "out0", 0 0, L_0x29bc4c0; 1 drivers +v0x2912a70_0 .net "out1", 0 0, L_0x29bc5d0; 1 drivers +v0x2912b50_0 .net "outfinal", 0 0, L_0x29bc670; 1 drivers +S_0x2912100 .scope module, "setSLTres3" "TwoInMux" 3 336, 3 109, S_0x2911f90; + .timescale -9 -12; +L_0x29a5cf0/d .functor NOT 1, L_0x29d1680, C4<0>, C4<0>, C4<0>; +L_0x29a5cf0 .delay (10000,10000,10000) L_0x29a5cf0/d; +L_0x29a5e00/d .functor AND 1, L_0x29bda30, L_0x29a5cf0, C4<1>, C4<1>; +L_0x29a5e00 .delay (20000,20000,20000) L_0x29a5e00/d; +L_0x29a5f10/d .functor AND 1, L_0x29bdb20, L_0x29d1680, C4<1>, C4<1>; +L_0x29a5f10 .delay (20000,20000,20000) L_0x29a5f10/d; +L_0x29bd850/d .functor OR 1, L_0x29a5e00, L_0x29a5f10, C4<0>, C4<0>; +L_0x29bd850 .delay (20000,20000,20000) L_0x29bd850/d; +v0x29121f0_0 .alias "S", 0 0, v0x293b720_0; +v0x2912270_0 .net "in0", 0 0, L_0x29bda30; 1 drivers +v0x2912310_0 .net "in1", 0 0, L_0x29bdb20; 1 drivers +v0x29123b0_0 .net "nS", 0 0, L_0x29a5cf0; 1 drivers +v0x2912460_0 .net "out0", 0 0, L_0x29a5e00; 1 drivers +v0x2912500_0 .net "out1", 0 0, L_0x29a5f10; 1 drivers +v0x29125e0_0 .net "outfinal", 0 0, L_0x29bd850; 1 drivers +S_0x28f01e0 .scope generate, "sltbits[23]" "sltbits[23]" 3 332, 3 332, S_0x28e1a50; + .timescale -9 -12; +P_0x28efbf8 .param/l "i" 3 332, +C4<010111>; +S_0x2910e50 .scope module, "attempt" "MiddleAddSubSLT" 3 334, 3 189, S_0x28f01e0; + .timescale -9 -12; +L_0x29bdc10/d .functor NOT 1, L_0x29bea60, C4<0>, C4<0>, C4<0>; +L_0x29bdc10 .delay (10000,10000,10000) L_0x29bdc10/d; +L_0x29bf420/d .functor NOT 1, L_0x29bf4e0, C4<0>, C4<0>, C4<0>; +L_0x29bf420 .delay (10000,10000,10000) L_0x29bf420/d; +L_0x29bf580/d .functor AND 1, L_0x29bf6c0, L_0x29bf420, C4<1>, C4<1>; +L_0x29bf580 .delay (20000,20000,20000) L_0x29bf580/d; +L_0x29bf760/d .functor XOR 1, L_0x29be9c0, L_0x29bf1b0, C4<0>, C4<0>; +L_0x29bf760 .delay (40000,40000,40000) L_0x29bf760/d; +L_0x29bf850/d .functor XOR 1, L_0x29bf760, L_0x29beb90, C4<0>, C4<0>; +L_0x29bf850 .delay (40000,40000,40000) L_0x29bf850/d; +L_0x29bf940/d .functor AND 1, L_0x29be9c0, L_0x29bf1b0, C4<1>, C4<1>; +L_0x29bf940 .delay (20000,20000,20000) L_0x29bf940/d; +L_0x29bfab0/d .functor AND 1, L_0x29bf760, L_0x29beb90, C4<1>, C4<1>; +L_0x29bfab0 .delay (20000,20000,20000) L_0x29bfab0/d; +L_0x29bfba0/d .functor OR 1, L_0x29bf940, L_0x29bfab0, C4<0>, C4<0>; +L_0x29bfba0 .delay (20000,20000,20000) L_0x29bfba0/d; +v0x29114d0_0 .net "A", 0 0, L_0x29be9c0; 1 drivers +v0x2911590_0 .net "AandB", 0 0, L_0x29bf940; 1 drivers +v0x2911630_0 .net "AddSubSLTSum", 0 0, L_0x29bf850; 1 drivers +v0x29116d0_0 .net "AxorB", 0 0, L_0x29bf760; 1 drivers +v0x2911750_0 .net "B", 0 0, L_0x29bea60; 1 drivers +v0x2911800_0 .net "BornB", 0 0, L_0x29bf1b0; 1 drivers +v0x29118c0_0 .net "CINandAxorB", 0 0, L_0x29bfab0; 1 drivers +v0x2911940_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x2911a10_0 .net *"_s3", 0 0, L_0x29bf4e0; 1 drivers +v0x2911a90_0 .net *"_s5", 0 0, L_0x29bf6c0; 1 drivers +v0x2911b90_0 .net "carryin", 0 0, L_0x29beb90; 1 drivers +v0x2911c30_0 .net "carryout", 0 0, L_0x29bfba0; 1 drivers +v0x2911d40_0 .net "nB", 0 0, L_0x29bdc10; 1 drivers +v0x2911df0_0 .net "nCmd2", 0 0, L_0x29bf420; 1 drivers +v0x2911ef0_0 .net "subtract", 0 0, L_0x29bf580; 1 drivers +L_0x29bf380 .part v0x2960210_0, 0, 1; +L_0x29bf4e0 .part v0x2960210_0, 2, 1; +L_0x29bf6c0 .part v0x2960210_0, 0, 1; +S_0x2910f40 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x2910e50; + .timescale -9 -12; +L_0x29bdde0/d .functor NOT 1, L_0x29bf380, C4<0>, C4<0>, C4<0>; +L_0x29bdde0 .delay (10000,10000,10000) L_0x29bdde0/d; +L_0x29bdea0/d .functor AND 1, L_0x29bea60, L_0x29bdde0, C4<1>, C4<1>; +L_0x29bdea0 .delay (20000,20000,20000) L_0x29bdea0/d; +L_0x29bf0c0/d .functor AND 1, L_0x29bdc10, L_0x29bf380, C4<1>, C4<1>; +L_0x29bf0c0 .delay (20000,20000,20000) L_0x29bf0c0/d; +L_0x29bf1b0/d .functor OR 1, L_0x29bdea0, L_0x29bf0c0, C4<0>, C4<0>; +L_0x29bf1b0 .delay (20000,20000,20000) L_0x29bf1b0/d; +v0x2911030_0 .net "S", 0 0, L_0x29bf380; 1 drivers +v0x29110f0_0 .alias "in0", 0 0, v0x2911750_0; +v0x2911190_0 .alias "in1", 0 0, v0x2911d40_0; +v0x2911230_0 .net "nS", 0 0, L_0x29bdde0; 1 drivers +v0x29112b0_0 .net "out0", 0 0, L_0x29bdea0; 1 drivers +v0x2911350_0 .net "out1", 0 0, L_0x29bf0c0; 1 drivers +v0x2911430_0 .alias "outfinal", 0 0, v0x2911800_0; +S_0x29108e0 .scope module, "setSLTres2" "TwoInMux" 3 335, 3 109, S_0x28f01e0; + .timescale -9 -12; +L_0x29bec30/d .functor NOT 1, L_0x29d1680, C4<0>, C4<0>, C4<0>; +L_0x29bec30 .delay (10000,10000,10000) L_0x29bec30/d; +L_0x29becd0/d .functor AND 1, L_0x29c06b0, L_0x29bec30, C4<1>, C4<1>; +L_0x29becd0 .delay (20000,20000,20000) L_0x29becd0/d; +L_0x29bede0/d .functor AND 1, C4<0>, L_0x29d1680, C4<1>, C4<1>; +L_0x29bede0 .delay (20000,20000,20000) L_0x29bede0/d; +L_0x29bee80/d .functor OR 1, L_0x29becd0, L_0x29bede0, C4<0>, C4<0>; +L_0x29bee80 .delay (20000,20000,20000) L_0x29bee80/d; +v0x29109d0_0 .alias "S", 0 0, v0x293b720_0; +v0x2910a70_0 .net "in0", 0 0, L_0x29c06b0; 1 drivers +v0x2910b10_0 .net "in1", 0 0, C4<0>; 1 drivers +v0x2910bb0_0 .net "nS", 0 0, L_0x29bec30; 1 drivers +v0x2910c30_0 .net "out0", 0 0, L_0x29becd0; 1 drivers +v0x2910cd0_0 .net "out1", 0 0, L_0x29bede0; 1 drivers +v0x2910db0_0 .net "outfinal", 0 0, L_0x29bee80; 1 drivers +S_0x28f0350 .scope module, "setSLTres3" "TwoInMux" 3 336, 3 109, S_0x28f01e0; + .timescale -9 -12; +L_0x29c0040/d .functor NOT 1, L_0x29d1680, C4<0>, C4<0>, C4<0>; +L_0x29c0040 .delay (10000,10000,10000) L_0x29c0040/d; +L_0x29c0150/d .functor AND 1, L_0x29c04e0, L_0x29c0040, C4<1>, C4<1>; +L_0x29c0150 .delay (20000,20000,20000) L_0x29c0150/d; +L_0x29c0260/d .functor AND 1, L_0x29c05d0, L_0x29d1680, C4<1>, C4<1>; +L_0x29c0260 .delay (20000,20000,20000) L_0x29c0260/d; +L_0x29c0300/d .functor OR 1, L_0x29c0150, L_0x29c0260, C4<0>, C4<0>; +L_0x29c0300 .delay (20000,20000,20000) L_0x29c0300/d; +v0x28f0440_0 .alias "S", 0 0, v0x293b720_0; +v0x28e9270_0 .net "in0", 0 0, L_0x29c04e0; 1 drivers +v0x2910570_0 .net "in1", 0 0, L_0x29c05d0; 1 drivers +v0x2910610_0 .net "nS", 0 0, L_0x29c0040; 1 drivers +v0x29106c0_0 .net "out0", 0 0, L_0x29c0150; 1 drivers +v0x2910760_0 .net "out1", 0 0, L_0x29c0260; 1 drivers +v0x2910840_0 .net "outfinal", 0 0, L_0x29c0300; 1 drivers +S_0x28ee560 .scope generate, "sltbits[24]" "sltbits[24]" 3 332, 3 332, S_0x28e1a50; + .timescale -9 -12; +P_0x28edfb8 .param/l "i" 3 332, +C4<011000>; +S_0x28ef1c0 .scope module, "attempt" "MiddleAddSubSLT" 3 334, 3 189, S_0x28ee560; + .timescale -9 -12; +L_0x29bb800/d .functor NOT 1, L_0x29c0a20, C4<0>, C4<0>, C4<0>; +L_0x29bb800 .delay (10000,10000,10000) L_0x29bb800/d; +L_0x29c1610/d .functor NOT 1, L_0x29c16d0, C4<0>, C4<0>, C4<0>; +L_0x29c1610 .delay (10000,10000,10000) L_0x29c1610/d; +L_0x29c1770/d .functor AND 1, L_0x29c18b0, L_0x29c1610, C4<1>, C4<1>; +L_0x29c1770 .delay (20000,20000,20000) L_0x29c1770/d; +L_0x29c1950/d .functor XOR 1, L_0x29c0980, L_0x29c13a0, C4<0>, C4<0>; +L_0x29c1950 .delay (40000,40000,40000) L_0x29c1950/d; +L_0x29c1a40/d .functor XOR 1, L_0x29c1950, L_0x29c0b50, C4<0>, C4<0>; +L_0x29c1a40 .delay (40000,40000,40000) L_0x29c1a40/d; +L_0x29c1b30/d .functor AND 1, L_0x29c0980, L_0x29c13a0, C4<1>, C4<1>; +L_0x29c1b30 .delay (20000,20000,20000) L_0x29c1b30/d; +L_0x29c1ca0/d .functor AND 1, L_0x29c1950, L_0x29c0b50, C4<1>, C4<1>; +L_0x29c1ca0 .delay (20000,20000,20000) L_0x29c1ca0/d; +L_0x29c1d90/d .functor OR 1, L_0x29c1b30, L_0x29c1ca0, C4<0>, C4<0>; +L_0x29c1d90 .delay (20000,20000,20000) L_0x29c1d90/d; +v0x28ef840_0 .net "A", 0 0, L_0x29c0980; 1 drivers +v0x28ef900_0 .net "AandB", 0 0, L_0x29c1b30; 1 drivers +v0x28ef9a0_0 .net "AddSubSLTSum", 0 0, L_0x29c1a40; 1 drivers +v0x28efa40_0 .net "AxorB", 0 0, L_0x29c1950; 1 drivers +v0x28efac0_0 .net "B", 0 0, L_0x29c0a20; 1 drivers +v0x28efb70_0 .net "BornB", 0 0, L_0x29c13a0; 1 drivers +v0x28efc30_0 .net "CINandAxorB", 0 0, L_0x29c1ca0; 1 drivers +v0x28efcb0_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x28efd30_0 .net *"_s3", 0 0, L_0x29c16d0; 1 drivers +v0x28efdb0_0 .net *"_s5", 0 0, L_0x29c18b0; 1 drivers +v0x28efe50_0 .net "carryin", 0 0, L_0x29c0b50; 1 drivers +v0x28efef0_0 .net "carryout", 0 0, L_0x29c1d90; 1 drivers +v0x28eff90_0 .net "nB", 0 0, L_0x29bb800; 1 drivers +v0x28f0040_0 .net "nCmd2", 0 0, L_0x29c1610; 1 drivers +v0x28f0140_0 .net "subtract", 0 0, L_0x29c1770; 1 drivers +L_0x29c1570 .part v0x2960210_0, 0, 1; +L_0x29c16d0 .part v0x2960210_0, 2, 1; +L_0x29c18b0 .part v0x2960210_0, 0, 1; +S_0x28ef2b0 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x28ef1c0; + .timescale -9 -12; +L_0x29c10c0/d .functor NOT 1, L_0x29c1570, C4<0>, C4<0>, C4<0>; +L_0x29c10c0 .delay (10000,10000,10000) L_0x29c10c0/d; +L_0x29c1180/d .functor AND 1, L_0x29c0a20, L_0x29c10c0, C4<1>, C4<1>; +L_0x29c1180 .delay (20000,20000,20000) L_0x29c1180/d; +L_0x29c1290/d .functor AND 1, L_0x29bb800, L_0x29c1570, C4<1>, C4<1>; +L_0x29c1290 .delay (20000,20000,20000) L_0x29c1290/d; +L_0x29c13a0/d .functor OR 1, L_0x29c1180, L_0x29c1290, C4<0>, C4<0>; +L_0x29c13a0 .delay (20000,20000,20000) L_0x29c13a0/d; +v0x28ef3a0_0 .net "S", 0 0, L_0x29c1570; 1 drivers +v0x28ef460_0 .alias "in0", 0 0, v0x28efac0_0; +v0x28ef500_0 .alias "in1", 0 0, v0x28eff90_0; +v0x28ef5a0_0 .net "nS", 0 0, L_0x29c10c0; 1 drivers +v0x28ef620_0 .net "out0", 0 0, L_0x29c1180; 1 drivers +v0x28ef6c0_0 .net "out1", 0 0, L_0x29c1290; 1 drivers +v0x28ef7a0_0 .alias "outfinal", 0 0, v0x28efb70_0; +S_0x28eec50 .scope module, "setSLTres2" "TwoInMux" 3 335, 3 109, S_0x28ee560; + .timescale -9 -12; +L_0x29c0bf0/d .functor NOT 1, L_0x29d1680, C4<0>, C4<0>, C4<0>; +L_0x29c0bf0 .delay (10000,10000,10000) L_0x29c0bf0/d; +L_0x29c0c90/d .functor AND 1, L_0x29c1fe0, L_0x29c0bf0, C4<1>, C4<1>; +L_0x29c0c90 .delay (20000,20000,20000) L_0x29c0c90/d; +L_0x29c0da0/d .functor AND 1, C4<0>, L_0x29d1680, C4<1>, C4<1>; +L_0x29c0da0 .delay (20000,20000,20000) L_0x29c0da0/d; +L_0x29c0e40/d .functor OR 1, L_0x29c0c90, L_0x29c0da0, C4<0>, C4<0>; +L_0x29c0e40 .delay (20000,20000,20000) L_0x29c0e40/d; +v0x28eed40_0 .alias "S", 0 0, v0x293b720_0; +v0x28eede0_0 .net "in0", 0 0, L_0x29c1fe0; 1 drivers +v0x28eee80_0 .net "in1", 0 0, C4<0>; 1 drivers +v0x28eef20_0 .net "nS", 0 0, L_0x29c0bf0; 1 drivers +v0x28eefa0_0 .net "out0", 0 0, L_0x29c0c90; 1 drivers +v0x28ef040_0 .net "out1", 0 0, L_0x29c0da0; 1 drivers +v0x28ef120_0 .net "outfinal", 0 0, L_0x29c0e40; 1 drivers +S_0x28ee6d0 .scope module, "setSLTres3" "TwoInMux" 3 336, 3 109, S_0x28ee560; + .timescale -9 -12; +L_0x29c0f30/d .functor NOT 1, L_0x29d1680, C4<0>, C4<0>, C4<0>; +L_0x29c0f30 .delay (10000,10000,10000) L_0x29c0f30/d; +L_0x29c2210/d .functor AND 1, L_0x29c25a0, L_0x29c0f30, C4<1>, C4<1>; +L_0x29c2210 .delay (20000,20000,20000) L_0x29c2210/d; +L_0x29c2320/d .functor AND 1, L_0x29c2690, L_0x29d1680, C4<1>, C4<1>; +L_0x29c2320 .delay (20000,20000,20000) L_0x29c2320/d; +L_0x29c23c0/d .functor OR 1, L_0x29c2210, L_0x29c2320, C4<0>, C4<0>; +L_0x29c23c0 .delay (20000,20000,20000) L_0x29c23c0/d; +v0x28ee7c0_0 .alias "S", 0 0, v0x293b720_0; +v0x28ee840_0 .net "in0", 0 0, L_0x29c25a0; 1 drivers +v0x28ee8e0_0 .net "in1", 0 0, L_0x29c2690; 1 drivers +v0x28ee980_0 .net "nS", 0 0, L_0x29c0f30; 1 drivers +v0x28eea30_0 .net "out0", 0 0, L_0x29c2210; 1 drivers +v0x28eead0_0 .net "out1", 0 0, L_0x29c2320; 1 drivers +v0x28eebb0_0 .net "outfinal", 0 0, L_0x29c23c0; 1 drivers +S_0x28ec920 .scope generate, "sltbits[25]" "sltbits[25]" 3 332, 3 332, S_0x28e1a50; + .timescale -9 -12; +P_0x28ec338 .param/l "i" 3 332, +C4<011001>; +S_0x28ed580 .scope module, "attempt" "MiddleAddSubSLT" 3 334, 3 189, S_0x28ec920; + .timescale -9 -12; +L_0x29c2780/d .functor NOT 1, L_0x29c2a80, C4<0>, C4<0>, C4<0>; +L_0x29c2780 .delay (10000,10000,10000) L_0x29c2780/d; +L_0x29c37e0/d .functor NOT 1, L_0x29c38a0, C4<0>, C4<0>, C4<0>; +L_0x29c37e0 .delay (10000,10000,10000) L_0x29c37e0/d; +L_0x29c3940/d .functor AND 1, L_0x29c3a80, L_0x29c37e0, C4<1>, C4<1>; +L_0x29c3940 .delay (20000,20000,20000) L_0x29c3940/d; +L_0x29c3b20/d .functor XOR 1, L_0x29c29e0, L_0x29c3570, C4<0>, C4<0>; +L_0x29c3b20 .delay (40000,40000,40000) L_0x29c3b20/d; +L_0x29c3c10/d .functor XOR 1, L_0x29c3b20, L_0x29c2bb0, C4<0>, C4<0>; +L_0x29c3c10 .delay (40000,40000,40000) L_0x29c3c10/d; +L_0x29c3d00/d .functor AND 1, L_0x29c29e0, L_0x29c3570, C4<1>, C4<1>; +L_0x29c3d00 .delay (20000,20000,20000) L_0x29c3d00/d; +L_0x29c3e70/d .functor AND 1, L_0x29c3b20, L_0x29c2bb0, C4<1>, C4<1>; +L_0x29c3e70 .delay (20000,20000,20000) L_0x29c3e70/d; +L_0x29c3f80/d .functor OR 1, L_0x29c3d00, L_0x29c3e70, C4<0>, C4<0>; +L_0x29c3f80 .delay (20000,20000,20000) L_0x29c3f80/d; +v0x28edc00_0 .net "A", 0 0, L_0x29c29e0; 1 drivers +v0x28edcc0_0 .net "AandB", 0 0, L_0x29c3d00; 1 drivers +v0x28edd60_0 .net "AddSubSLTSum", 0 0, L_0x29c3c10; 1 drivers +v0x28ede00_0 .net "AxorB", 0 0, L_0x29c3b20; 1 drivers +v0x28ede80_0 .net "B", 0 0, L_0x29c2a80; 1 drivers +v0x28edf30_0 .net "BornB", 0 0, L_0x29c3570; 1 drivers +v0x28edff0_0 .net "CINandAxorB", 0 0, L_0x29c3e70; 1 drivers +v0x28ee070_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x28ee0f0_0 .net *"_s3", 0 0, L_0x29c38a0; 1 drivers +v0x28ee170_0 .net *"_s5", 0 0, L_0x29c3a80; 1 drivers +v0x28ee1f0_0 .net "carryin", 0 0, L_0x29c2bb0; 1 drivers +v0x28ee270_0 .net "carryout", 0 0, L_0x29c3f80; 1 drivers +v0x28ee310_0 .net "nB", 0 0, L_0x29c2780; 1 drivers +v0x28ee3c0_0 .net "nCmd2", 0 0, L_0x29c37e0; 1 drivers +v0x28ee4c0_0 .net "subtract", 0 0, L_0x29c3940; 1 drivers +L_0x29c3740 .part v0x2960210_0, 0, 1; +L_0x29c38a0 .part v0x2960210_0, 2, 1; +L_0x29c3a80 .part v0x2960210_0, 0, 1; +S_0x28ed670 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x28ed580; + .timescale -9 -12; +L_0x29c3290/d .functor NOT 1, L_0x29c3740, C4<0>, C4<0>, C4<0>; +L_0x29c3290 .delay (10000,10000,10000) L_0x29c3290/d; +L_0x29c3350/d .functor AND 1, L_0x29c2a80, L_0x29c3290, C4<1>, C4<1>; +L_0x29c3350 .delay (20000,20000,20000) L_0x29c3350/d; +L_0x29c3460/d .functor AND 1, L_0x29c2780, L_0x29c3740, C4<1>, C4<1>; +L_0x29c3460 .delay (20000,20000,20000) L_0x29c3460/d; +L_0x29c3570/d .functor OR 1, L_0x29c3350, L_0x29c3460, C4<0>, C4<0>; +L_0x29c3570 .delay (20000,20000,20000) L_0x29c3570/d; +v0x28ed760_0 .net "S", 0 0, L_0x29c3740; 1 drivers +v0x28ed820_0 .alias "in0", 0 0, v0x28ede80_0; +v0x28ed8c0_0 .alias "in1", 0 0, v0x28ee310_0; +v0x28ed960_0 .net "nS", 0 0, L_0x29c3290; 1 drivers +v0x28ed9e0_0 .net "out0", 0 0, L_0x29c3350; 1 drivers +v0x28eda80_0 .net "out1", 0 0, L_0x29c3460; 1 drivers +v0x28edb60_0 .alias "outfinal", 0 0, v0x28edf30_0; +S_0x28ed010 .scope module, "setSLTres2" "TwoInMux" 3 335, 3 109, S_0x28ec920; + .timescale -9 -12; +L_0x29c2c50/d .functor NOT 1, L_0x29d1680, C4<0>, C4<0>, C4<0>; +L_0x29c2c50 .delay (10000,10000,10000) L_0x29c2c50/d; +L_0x29c2cf0/d .functor AND 1, L_0x29c3080, L_0x29c2c50, C4<1>, C4<1>; +L_0x29c2cf0 .delay (20000,20000,20000) L_0x29c2cf0/d; +L_0x29c2e00/d .functor AND 1, C4<0>, L_0x29d1680, C4<1>, C4<1>; +L_0x29c2e00 .delay (20000,20000,20000) L_0x29c2e00/d; +L_0x29c2ea0/d .functor OR 1, L_0x29c2cf0, L_0x29c2e00, C4<0>, C4<0>; +L_0x29c2ea0 .delay (20000,20000,20000) L_0x29c2ea0/d; +v0x28ed100_0 .alias "S", 0 0, v0x293b720_0; +v0x28ed1a0_0 .net "in0", 0 0, L_0x29c3080; 1 drivers +v0x28ed240_0 .net "in1", 0 0, C4<0>; 1 drivers +v0x28ed2e0_0 .net "nS", 0 0, L_0x29c2c50; 1 drivers +v0x28ed360_0 .net "out0", 0 0, L_0x29c2cf0; 1 drivers +v0x28ed400_0 .net "out1", 0 0, L_0x29c2e00; 1 drivers +v0x28ed4e0_0 .net "outfinal", 0 0, L_0x29c2ea0; 1 drivers +S_0x28eca90 .scope module, "setSLTres3" "TwoInMux" 3 336, 3 109, S_0x28ec920; + .timescale -9 -12; +L_0x29c4430/d .functor NOT 1, L_0x29d1680, C4<0>, C4<0>, C4<0>; +L_0x29c4430 .delay (10000,10000,10000) L_0x29c4430/d; +L_0x29c4520/d .functor AND 1, L_0x29c48b0, L_0x29c4430, C4<1>, C4<1>; +L_0x29c4520 .delay (20000,20000,20000) L_0x29c4520/d; +L_0x29c4630/d .functor AND 1, L_0x29c49a0, L_0x29d1680, C4<1>, C4<1>; +L_0x29c4630 .delay (20000,20000,20000) L_0x29c4630/d; +L_0x29c46d0/d .functor OR 1, L_0x29c4520, L_0x29c4630, C4<0>, C4<0>; +L_0x29c46d0 .delay (20000,20000,20000) L_0x29c46d0/d; +v0x28ecb80_0 .alias "S", 0 0, v0x293b720_0; +v0x28ecc00_0 .net "in0", 0 0, L_0x29c48b0; 1 drivers +v0x28ecca0_0 .net "in1", 0 0, L_0x29c49a0; 1 drivers +v0x28ecd40_0 .net "nS", 0 0, L_0x29c4430; 1 drivers +v0x28ecdf0_0 .net "out0", 0 0, L_0x29c4520; 1 drivers +v0x28ece90_0 .net "out1", 0 0, L_0x29c4630; 1 drivers +v0x28ecf70_0 .net "outfinal", 0 0, L_0x29c46d0; 1 drivers +S_0x28eaca0 .scope generate, "sltbits[26]" "sltbits[26]" 3 332, 3 332, S_0x28e1a50; + .timescale -9 -12; +P_0x28ea6b8 .param/l "i" 3 332, +C4<011010>; +S_0x28eb900 .scope module, "attempt" "MiddleAddSubSLT" 3 334, 3 189, S_0x28eaca0; + .timescale -9 -12; +L_0x29c4a90/d .functor NOT 1, L_0x2983190, C4<0>, C4<0>, C4<0>; +L_0x29c4a90 .delay (10000,10000,10000) L_0x29c4a90/d; +L_0x29c59b0/d .functor NOT 1, L_0x29c5a70, C4<0>, C4<0>, C4<0>; +L_0x29c59b0 .delay (10000,10000,10000) L_0x29c59b0/d; +L_0x29c5b10/d .functor AND 1, L_0x29c5c50, L_0x29c59b0, C4<1>, C4<1>; +L_0x29c5b10 .delay (20000,20000,20000) L_0x29c5b10/d; +L_0x29c5cf0/d .functor XOR 1, L_0x29830f0, L_0x29c5740, C4<0>, C4<0>; +L_0x29c5cf0 .delay (40000,40000,40000) L_0x29c5cf0/d; +L_0x29c5de0/d .functor XOR 1, L_0x29c5cf0, L_0x29832c0, C4<0>, C4<0>; +L_0x29c5de0 .delay (40000,40000,40000) L_0x29c5de0/d; +L_0x29c5ed0/d .functor AND 1, L_0x29830f0, L_0x29c5740, C4<1>, C4<1>; +L_0x29c5ed0 .delay (20000,20000,20000) L_0x29c5ed0/d; +L_0x29c6040/d .functor AND 1, L_0x29c5cf0, L_0x29832c0, C4<1>, C4<1>; +L_0x29c6040 .delay (20000,20000,20000) L_0x29c6040/d; +L_0x29c6130/d .functor OR 1, L_0x29c5ed0, L_0x29c6040, C4<0>, C4<0>; +L_0x29c6130 .delay (20000,20000,20000) L_0x29c6130/d; +v0x28ebf80_0 .net "A", 0 0, L_0x29830f0; 1 drivers +v0x28ec040_0 .net "AandB", 0 0, L_0x29c5ed0; 1 drivers +v0x28ec0e0_0 .net "AddSubSLTSum", 0 0, L_0x29c5de0; 1 drivers +v0x28ec180_0 .net "AxorB", 0 0, L_0x29c5cf0; 1 drivers +v0x28ec200_0 .net "B", 0 0, L_0x2983190; 1 drivers +v0x28ec2b0_0 .net "BornB", 0 0, L_0x29c5740; 1 drivers +v0x28ec370_0 .net "CINandAxorB", 0 0, L_0x29c6040; 1 drivers +v0x28ec3f0_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x28ec470_0 .net *"_s3", 0 0, L_0x29c5a70; 1 drivers +v0x28ec4f0_0 .net *"_s5", 0 0, L_0x29c5c50; 1 drivers +v0x28ec590_0 .net "carryin", 0 0, L_0x29832c0; 1 drivers +v0x28ec630_0 .net "carryout", 0 0, L_0x29c6130; 1 drivers +v0x28ec6d0_0 .net "nB", 0 0, L_0x29c4a90; 1 drivers +v0x28ec780_0 .net "nCmd2", 0 0, L_0x29c59b0; 1 drivers +v0x28ec880_0 .net "subtract", 0 0, L_0x29c5b10; 1 drivers +L_0x29c5910 .part v0x2960210_0, 0, 1; +L_0x29c5a70 .part v0x2960210_0, 2, 1; +L_0x29c5c50 .part v0x2960210_0, 0, 1; +S_0x28eb9f0 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x28eb900; + .timescale -9 -12; +L_0x29c5480/d .functor NOT 1, L_0x29c5910, C4<0>, C4<0>, C4<0>; +L_0x29c5480 .delay (10000,10000,10000) L_0x29c5480/d; +L_0x29c5520/d .functor AND 1, L_0x2983190, L_0x29c5480, C4<1>, C4<1>; +L_0x29c5520 .delay (20000,20000,20000) L_0x29c5520/d; +L_0x29c5630/d .functor AND 1, L_0x29c4a90, L_0x29c5910, C4<1>, C4<1>; +L_0x29c5630 .delay (20000,20000,20000) L_0x29c5630/d; +L_0x29c5740/d .functor OR 1, L_0x29c5520, L_0x29c5630, C4<0>, C4<0>; +L_0x29c5740 .delay (20000,20000,20000) L_0x29c5740/d; +v0x28ebae0_0 .net "S", 0 0, L_0x29c5910; 1 drivers +v0x28ebba0_0 .alias "in0", 0 0, v0x28ec200_0; +v0x28ebc40_0 .alias "in1", 0 0, v0x28ec6d0_0; +v0x28ebce0_0 .net "nS", 0 0, L_0x29c5480; 1 drivers +v0x28ebd60_0 .net "out0", 0 0, L_0x29c5520; 1 drivers +v0x28ebe00_0 .net "out1", 0 0, L_0x29c5630; 1 drivers +v0x28ebee0_0 .alias "outfinal", 0 0, v0x28ec2b0_0; +S_0x28eb390 .scope module, "setSLTres2" "TwoInMux" 3 335, 3 109, S_0x28eaca0; + .timescale -9 -12; +L_0x2983360/d .functor NOT 1, L_0x29d1680, C4<0>, C4<0>, C4<0>; +L_0x2983360 .delay (10000,10000,10000) L_0x2983360/d; +L_0x2983400/d .functor AND 1, L_0x29c5030, L_0x2983360, C4<1>, C4<1>; +L_0x2983400 .delay (20000,20000,20000) L_0x2983400/d; +L_0x29c4db0/d .functor AND 1, C4<0>, L_0x29d1680, C4<1>, C4<1>; +L_0x29c4db0 .delay (20000,20000,20000) L_0x29c4db0/d; +L_0x29c4e50/d .functor OR 1, L_0x2983400, L_0x29c4db0, C4<0>, C4<0>; +L_0x29c4e50 .delay (20000,20000,20000) L_0x29c4e50/d; +v0x28eb480_0 .alias "S", 0 0, v0x293b720_0; +v0x28eb520_0 .net "in0", 0 0, L_0x29c5030; 1 drivers +v0x28eb5c0_0 .net "in1", 0 0, C4<0>; 1 drivers +v0x28eb660_0 .net "nS", 0 0, L_0x2983360; 1 drivers +v0x28eb6e0_0 .net "out0", 0 0, L_0x2983400; 1 drivers +v0x28eb780_0 .net "out1", 0 0, L_0x29c4db0; 1 drivers +v0x28eb860_0 .net "outfinal", 0 0, L_0x29c4e50; 1 drivers +S_0x28eae10 .scope module, "setSLTres3" "TwoInMux" 3 336, 3 109, S_0x28eaca0; + .timescale -9 -12; +L_0x29c51b0/d .functor NOT 1, L_0x29d1680, C4<0>, C4<0>, C4<0>; +L_0x29c51b0 .delay (10000,10000,10000) L_0x29c51b0/d; +L_0x29c52c0/d .functor AND 1, L_0x29c65a0, L_0x29c51b0, C4<1>, C4<1>; +L_0x29c52c0 .delay (20000,20000,20000) L_0x29c52c0/d; +L_0x29c53d0/d .functor AND 1, L_0x29c6690, L_0x29d1680, C4<1>, C4<1>; +L_0x29c53d0 .delay (20000,20000,20000) L_0x29c53d0/d; +L_0x29c63c0/d .functor OR 1, L_0x29c52c0, L_0x29c53d0, C4<0>, C4<0>; +L_0x29c63c0 .delay (20000,20000,20000) L_0x29c63c0/d; +v0x28eaf00_0 .alias "S", 0 0, v0x293b720_0; +v0x28eaf80_0 .net "in0", 0 0, L_0x29c65a0; 1 drivers +v0x28eb020_0 .net "in1", 0 0, L_0x29c6690; 1 drivers +v0x28eb0c0_0 .net "nS", 0 0, L_0x29c51b0; 1 drivers +v0x28eb170_0 .net "out0", 0 0, L_0x29c52c0; 1 drivers +v0x28eb210_0 .net "out1", 0 0, L_0x29c53d0; 1 drivers +v0x28eb2f0_0 .net "outfinal", 0 0, L_0x29c63c0; 1 drivers +S_0x28e8f90 .scope generate, "sltbits[27]" "sltbits[27]" 3 332, 3 332, S_0x28e1a50; + .timescale -9 -12; +P_0x28e89a8 .param/l "i" 3 332, +C4<011011>; +S_0x28e9c80 .scope module, "attempt" "MiddleAddSubSLT" 3 334, 3 189, S_0x28e8f90; + .timescale -9 -12; +L_0x29c6780/d .functor NOT 1, L_0x29c75d0, C4<0>, C4<0>, C4<0>; +L_0x29c6780 .delay (10000,10000,10000) L_0x29c6780/d; +L_0x29c7f90/d .functor NOT 1, L_0x29c8050, C4<0>, C4<0>, C4<0>; +L_0x29c7f90 .delay (10000,10000,10000) L_0x29c7f90/d; +L_0x29c80f0/d .functor AND 1, L_0x29c8230, L_0x29c7f90, C4<1>, C4<1>; +L_0x29c80f0 .delay (20000,20000,20000) L_0x29c80f0/d; +L_0x29c82d0/d .functor XOR 1, L_0x29c7530, L_0x29c7d40, C4<0>, C4<0>; +L_0x29c82d0 .delay (40000,40000,40000) L_0x29c82d0/d; +L_0x29c83c0/d .functor XOR 1, L_0x29c82d0, L_0x29c7700, C4<0>, C4<0>; +L_0x29c83c0 .delay (40000,40000,40000) L_0x29c83c0/d; +L_0x29c84b0/d .functor AND 1, L_0x29c7530, L_0x29c7d40, C4<1>, C4<1>; +L_0x29c84b0 .delay (20000,20000,20000) L_0x29c84b0/d; +L_0x29c8620/d .functor AND 1, L_0x29c82d0, L_0x29c7700, C4<1>, C4<1>; +L_0x29c8620 .delay (20000,20000,20000) L_0x29c8620/d; +L_0x29c8710/d .functor OR 1, L_0x29c84b0, L_0x29c8620, C4<0>, C4<0>; +L_0x29c8710 .delay (20000,20000,20000) L_0x29c8710/d; +v0x28ea300_0 .net "A", 0 0, L_0x29c7530; 1 drivers +v0x28ea3c0_0 .net "AandB", 0 0, L_0x29c84b0; 1 drivers +v0x28ea460_0 .net "AddSubSLTSum", 0 0, L_0x29c83c0; 1 drivers +v0x28ea500_0 .net "AxorB", 0 0, L_0x29c82d0; 1 drivers +v0x28ea580_0 .net "B", 0 0, L_0x29c75d0; 1 drivers +v0x28ea630_0 .net "BornB", 0 0, L_0x29c7d40; 1 drivers +v0x28ea6f0_0 .net "CINandAxorB", 0 0, L_0x29c8620; 1 drivers +v0x28ea770_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x28ea7f0_0 .net *"_s3", 0 0, L_0x29c8050; 1 drivers +v0x28ea870_0 .net *"_s5", 0 0, L_0x29c8230; 1 drivers +v0x28ea910_0 .net "carryin", 0 0, L_0x29c7700; 1 drivers +v0x28ea9b0_0 .net "carryout", 0 0, L_0x29c8710; 1 drivers +v0x28eaa50_0 .net "nB", 0 0, L_0x29c6780; 1 drivers +v0x28eab00_0 .net "nCmd2", 0 0, L_0x29c7f90; 1 drivers +v0x28eac00_0 .net "subtract", 0 0, L_0x29c80f0; 1 drivers +L_0x29c7ef0 .part v0x2960210_0, 0, 1; +L_0x29c8050 .part v0x2960210_0, 2, 1; +L_0x29c8230 .part v0x2960210_0, 0, 1; +S_0x28e9d70 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x28e9c80; + .timescale -9 -12; +L_0x29c6950/d .functor NOT 1, L_0x29c7ef0, C4<0>, C4<0>, C4<0>; +L_0x29c6950 .delay (10000,10000,10000) L_0x29c6950/d; +L_0x29c6a10/d .functor AND 1, L_0x29c75d0, L_0x29c6950, C4<1>, C4<1>; +L_0x29c6a10 .delay (20000,20000,20000) L_0x29c6a10/d; +L_0x29c6b20/d .functor AND 1, L_0x29c6780, L_0x29c7ef0, C4<1>, C4<1>; +L_0x29c6b20 .delay (20000,20000,20000) L_0x29c6b20/d; +L_0x29c7d40/d .functor OR 1, L_0x29c6a10, L_0x29c6b20, C4<0>, C4<0>; +L_0x29c7d40 .delay (20000,20000,20000) L_0x29c7d40/d; +v0x28e9e60_0 .net "S", 0 0, L_0x29c7ef0; 1 drivers +v0x28e9f20_0 .alias "in0", 0 0, v0x28ea580_0; +v0x28e9fc0_0 .alias "in1", 0 0, v0x28eaa50_0; +v0x28ea060_0 .net "nS", 0 0, L_0x29c6950; 1 drivers +v0x28ea0e0_0 .net "out0", 0 0, L_0x29c6a10; 1 drivers +v0x28ea180_0 .net "out1", 0 0, L_0x29c6b20; 1 drivers +v0x28ea260_0 .alias "outfinal", 0 0, v0x28ea630_0; +S_0x28e9710 .scope module, "setSLTres2" "TwoInMux" 3 335, 3 109, S_0x28e8f90; + .timescale -9 -12; +L_0x29c77a0/d .functor NOT 1, L_0x29d1680, C4<0>, C4<0>, C4<0>; +L_0x29c77a0 .delay (10000,10000,10000) L_0x29c77a0/d; +L_0x29c7840/d .functor AND 1, L_0x29c7bd0, L_0x29c77a0, C4<1>, C4<1>; +L_0x29c7840 .delay (20000,20000,20000) L_0x29c7840/d; +L_0x29c7950/d .functor AND 1, C4<0>, L_0x29d1680, C4<1>, C4<1>; +L_0x29c7950 .delay (20000,20000,20000) L_0x29c7950/d; +L_0x29c79f0/d .functor OR 1, L_0x29c7840, L_0x29c7950, C4<0>, C4<0>; +L_0x29c79f0 .delay (20000,20000,20000) L_0x29c79f0/d; +v0x28e9800_0 .alias "S", 0 0, v0x293b720_0; +v0x28e98a0_0 .net "in0", 0 0, L_0x29c7bd0; 1 drivers +v0x28e9940_0 .net "in1", 0 0, C4<0>; 1 drivers +v0x28e99e0_0 .net "nS", 0 0, L_0x29c77a0; 1 drivers +v0x28e9a60_0 .net "out0", 0 0, L_0x29c7840; 1 drivers +v0x28e9b00_0 .net "out1", 0 0, L_0x29c7950; 1 drivers +v0x28e9be0_0 .net "outfinal", 0 0, L_0x29c79f0; 1 drivers +S_0x28e9100 .scope module, "setSLTres3" "TwoInMux" 3 336, 3 109, S_0x28e8f90; + .timescale -9 -12; +L_0x29c4350/d .functor NOT 1, L_0x29d1680, C4<0>, C4<0>, C4<0>; +L_0x29c4350 .delay (10000,10000,10000) L_0x29c4350/d; +L_0x29c94d0/d .functor AND 1, L_0x29c9870, L_0x29c4350, C4<1>, C4<1>; +L_0x29c94d0 .delay (20000,20000,20000) L_0x29c94d0/d; +L_0x29c95c0/d .functor AND 1, L_0x29c8a50, L_0x29d1680, C4<1>, C4<1>; +L_0x29c95c0 .delay (20000,20000,20000) L_0x29c95c0/d; +L_0x29c9660/d .functor OR 1, L_0x29c94d0, L_0x29c95c0, C4<0>, C4<0>; +L_0x29c9660 .delay (20000,20000,20000) L_0x29c9660/d; +v0x28e91f0_0 .alias "S", 0 0, v0x293b720_0; +v0x28e58e0_0 .net "in0", 0 0, L_0x29c9870; 1 drivers +v0x28e93a0_0 .net "in1", 0 0, L_0x29c8a50; 1 drivers +v0x28e9440_0 .net "nS", 0 0, L_0x29c4350; 1 drivers +v0x28e94f0_0 .net "out0", 0 0, L_0x29c94d0; 1 drivers +v0x28e9590_0 .net "out1", 0 0, L_0x29c95c0; 1 drivers +v0x28e9670_0 .net "outfinal", 0 0, L_0x29c9660; 1 drivers +S_0x28e7310 .scope generate, "sltbits[28]" "sltbits[28]" 3 332, 3 332, S_0x28e1a50; + .timescale -9 -12; +P_0x28e6d28 .param/l "i" 3 332, +C4<011100>; +S_0x28e7f70 .scope module, "attempt" "MiddleAddSubSLT" 3 334, 3 189, S_0x28e7310; + .timescale -9 -12; +L_0x29c8b40/d .functor NOT 1, L_0x29c9be0, C4<0>, C4<0>, C4<0>; +L_0x29c8b40 .delay (10000,10000,10000) L_0x29c8b40/d; +L_0x29c9280/d .functor NOT 1, L_0x29ca2b0, C4<0>, C4<0>, C4<0>; +L_0x29c9280 .delay (10000,10000,10000) L_0x29c9280/d; +L_0x29ca350/d .functor AND 1, L_0x29ca440, L_0x29c9280, C4<1>, C4<1>; +L_0x29ca350 .delay (20000,20000,20000) L_0x29ca350/d; +L_0x29ca4e0/d .functor XOR 1, L_0x29c9b40, L_0x29c9010, C4<0>, C4<0>; +L_0x29ca4e0 .delay (40000,40000,40000) L_0x29ca4e0/d; +L_0x29ca5d0/d .functor XOR 1, L_0x29ca4e0, L_0x29c9d10, C4<0>, C4<0>; +L_0x29ca5d0 .delay (40000,40000,40000) L_0x29ca5d0/d; +L_0x29ca6c0/d .functor AND 1, L_0x29c9b40, L_0x29c9010, C4<1>, C4<1>; +L_0x29ca6c0 .delay (20000,20000,20000) L_0x29ca6c0/d; +L_0x29ca830/d .functor AND 1, L_0x29ca4e0, L_0x29c9d10, C4<1>, C4<1>; +L_0x29ca830 .delay (20000,20000,20000) L_0x29ca830/d; +L_0x29ca920/d .functor OR 1, L_0x29ca6c0, L_0x29ca830, C4<0>, C4<0>; +L_0x29ca920 .delay (20000,20000,20000) L_0x29ca920/d; +v0x28e85f0_0 .net "A", 0 0, L_0x29c9b40; 1 drivers +v0x28e86b0_0 .net "AandB", 0 0, L_0x29ca6c0; 1 drivers +v0x28e8750_0 .net "AddSubSLTSum", 0 0, L_0x29ca5d0; 1 drivers +v0x28e87f0_0 .net "AxorB", 0 0, L_0x29ca4e0; 1 drivers +v0x28e8870_0 .net "B", 0 0, L_0x29c9be0; 1 drivers +v0x28e8920_0 .net "BornB", 0 0, L_0x29c9010; 1 drivers +v0x28e89e0_0 .net "CINandAxorB", 0 0, L_0x29ca830; 1 drivers +v0x28e8a60_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x28e8ae0_0 .net *"_s3", 0 0, L_0x29ca2b0; 1 drivers +v0x28e8b60_0 .net *"_s5", 0 0, L_0x29ca440; 1 drivers +v0x28e8c00_0 .net "carryin", 0 0, L_0x29c9d10; 1 drivers +v0x28e8ca0_0 .net "carryout", 0 0, L_0x29ca920; 1 drivers +v0x28e8d40_0 .net "nB", 0 0, L_0x29c8b40; 1 drivers +v0x28e8df0_0 .net "nCmd2", 0 0, L_0x29c9280; 1 drivers +v0x28e8ef0_0 .net "subtract", 0 0, L_0x29ca350; 1 drivers +L_0x29c91e0 .part v0x2960210_0, 0, 1; +L_0x29ca2b0 .part v0x2960210_0, 2, 1; +L_0x29ca440 .part v0x2960210_0, 0, 1; +S_0x28e8060 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x28e7f70; + .timescale -9 -12; +L_0x29c8d30/d .functor NOT 1, L_0x29c91e0, C4<0>, C4<0>, C4<0>; +L_0x29c8d30 .delay (10000,10000,10000) L_0x29c8d30/d; +L_0x29c8df0/d .functor AND 1, L_0x29c9be0, L_0x29c8d30, C4<1>, C4<1>; +L_0x29c8df0 .delay (20000,20000,20000) L_0x29c8df0/d; +L_0x29c8f00/d .functor AND 1, L_0x29c8b40, L_0x29c91e0, C4<1>, C4<1>; +L_0x29c8f00 .delay (20000,20000,20000) L_0x29c8f00/d; +L_0x29c9010/d .functor OR 1, L_0x29c8df0, L_0x29c8f00, C4<0>, C4<0>; +L_0x29c9010 .delay (20000,20000,20000) L_0x29c9010/d; +v0x28e8150_0 .net "S", 0 0, L_0x29c91e0; 1 drivers +v0x28e8210_0 .alias "in0", 0 0, v0x28e8870_0; +v0x28e82b0_0 .alias "in1", 0 0, v0x28e8d40_0; +v0x28e8350_0 .net "nS", 0 0, L_0x29c8d30; 1 drivers +v0x28e83d0_0 .net "out0", 0 0, L_0x29c8df0; 1 drivers +v0x28e8470_0 .net "out1", 0 0, L_0x29c8f00; 1 drivers +v0x28e8550_0 .alias "outfinal", 0 0, v0x28e8920_0; +S_0x28e7a00 .scope module, "setSLTres2" "TwoInMux" 3 335, 3 109, S_0x28e7310; + .timescale -9 -12; +L_0x29c9db0/d .functor NOT 1, L_0x29d1680, C4<0>, C4<0>, C4<0>; +L_0x29c9db0 .delay (10000,10000,10000) L_0x29c9db0/d; +L_0x29c9e50/d .functor AND 1, L_0x29ca1e0, L_0x29c9db0, C4<1>, C4<1>; +L_0x29c9e50 .delay (20000,20000,20000) L_0x29c9e50/d; +L_0x29c9f60/d .functor AND 1, C4<0>, L_0x29d1680, C4<1>, C4<1>; +L_0x29c9f60 .delay (20000,20000,20000) L_0x29c9f60/d; +L_0x29ca000/d .functor OR 1, L_0x29c9e50, L_0x29c9f60, C4<0>, C4<0>; +L_0x29ca000 .delay (20000,20000,20000) L_0x29ca000/d; +v0x28e7af0_0 .alias "S", 0 0, v0x293b720_0; +v0x28e7b90_0 .net "in0", 0 0, L_0x29ca1e0; 1 drivers +v0x28e7c30_0 .net "in1", 0 0, C4<0>; 1 drivers +v0x28e7cd0_0 .net "nS", 0 0, L_0x29c9db0; 1 drivers +v0x28e7d50_0 .net "out0", 0 0, L_0x29c9e50; 1 drivers +v0x28e7df0_0 .net "out1", 0 0, L_0x29c9f60; 1 drivers +v0x28e7ed0_0 .net "outfinal", 0 0, L_0x29ca000; 1 drivers +S_0x28e7480 .scope module, "setSLTres3" "TwoInMux" 3 336, 3 109, S_0x28e7310; + .timescale -9 -12; +L_0x29cb5c0/d .functor NOT 1, L_0x29d1680, C4<0>, C4<0>, C4<0>; +L_0x29cb5c0 .delay (10000,10000,10000) L_0x29cb5c0/d; +L_0x29cb6b0/d .functor AND 1, L_0x29cab50, L_0x29cb5c0, C4<1>, C4<1>; +L_0x29cb6b0 .delay (20000,20000,20000) L_0x29cb6b0/d; +L_0x29cb7a0/d .functor AND 1, L_0x29cac40, L_0x29d1680, C4<1>, C4<1>; +L_0x29cb7a0 .delay (20000,20000,20000) L_0x29cb7a0/d; +L_0x29cb840/d .functor OR 1, L_0x29cb6b0, L_0x29cb7a0, C4<0>, C4<0>; +L_0x29cb840 .delay (20000,20000,20000) L_0x29cb840/d; +v0x28e7570_0 .alias "S", 0 0, v0x293b720_0; +v0x28e75f0_0 .net "in0", 0 0, L_0x29cab50; 1 drivers +v0x28e7690_0 .net "in1", 0 0, L_0x29cac40; 1 drivers +v0x28e7730_0 .net "nS", 0 0, L_0x29cb5c0; 1 drivers +v0x28e77e0_0 .net "out0", 0 0, L_0x29cb6b0; 1 drivers +v0x28e7880_0 .net "out1", 0 0, L_0x29cb7a0; 1 drivers +v0x28e7960_0 .net "outfinal", 0 0, L_0x29cb840; 1 drivers +S_0x28e5600 .scope generate, "sltbits[29]" "sltbits[29]" 3 332, 3 332, S_0x28e1a50; + .timescale -9 -12; +P_0x28e4fc8 .param/l "i" 3 332, +C4<011101>; +S_0x28e62f0 .scope module, "attempt" "MiddleAddSubSLT" 3 334, 3 189, S_0x28e5600; + .timescale -9 -12; +L_0x29cad30/d .functor NOT 1, L_0x29cbbe0, C4<0>, C4<0>, C4<0>; +L_0x29cad30 .delay (10000,10000,10000) L_0x29cad30/d; +L_0x29cb470/d .functor NOT 1, L_0x29cc440, C4<0>, C4<0>, C4<0>; +L_0x29cb470 .delay (10000,10000,10000) L_0x29cb470/d; +L_0x29cc4e0/d .functor AND 1, L_0x29cc620, L_0x29cb470, C4<1>, C4<1>; +L_0x29cc4e0 .delay (20000,20000,20000) L_0x29cc4e0/d; +L_0x29cc6c0/d .functor XOR 1, L_0x29cbb40, L_0x29cb200, C4<0>, C4<0>; +L_0x29cc6c0 .delay (40000,40000,40000) L_0x29cc6c0/d; +L_0x29cc7b0/d .functor XOR 1, L_0x29cc6c0, L_0x29cbd10, C4<0>, C4<0>; +L_0x29cc7b0 .delay (40000,40000,40000) L_0x29cc7b0/d; +L_0x29cc8a0/d .functor AND 1, L_0x29cbb40, L_0x29cb200, C4<1>, C4<1>; +L_0x29cc8a0 .delay (20000,20000,20000) L_0x29cc8a0/d; +L_0x29cca10/d .functor AND 1, L_0x29cc6c0, L_0x29cbd10, C4<1>, C4<1>; +L_0x29cca10 .delay (20000,20000,20000) L_0x29cca10/d; +L_0x29ccb00/d .functor OR 1, L_0x29cc8a0, L_0x29cca10, C4<0>, C4<0>; +L_0x29ccb00 .delay (20000,20000,20000) L_0x29ccb00/d; +v0x28e6970_0 .net "A", 0 0, L_0x29cbb40; 1 drivers +v0x28e6a30_0 .net "AandB", 0 0, L_0x29cc8a0; 1 drivers +v0x28e6ad0_0 .net "AddSubSLTSum", 0 0, L_0x29cc7b0; 1 drivers +v0x28e6b70_0 .net "AxorB", 0 0, L_0x29cc6c0; 1 drivers +v0x28e6bf0_0 .net "B", 0 0, L_0x29cbbe0; 1 drivers +v0x28e6ca0_0 .net "BornB", 0 0, L_0x29cb200; 1 drivers +v0x28e6d60_0 .net "CINandAxorB", 0 0, L_0x29cca10; 1 drivers +v0x28e6de0_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x28e6e60_0 .net *"_s3", 0 0, L_0x29cc440; 1 drivers +v0x28e6ee0_0 .net *"_s5", 0 0, L_0x29cc620; 1 drivers +v0x28e6f80_0 .net "carryin", 0 0, L_0x29cbd10; 1 drivers +v0x28e7020_0 .net "carryout", 0 0, L_0x29ccb00; 1 drivers +v0x28e70c0_0 .net "nB", 0 0, L_0x29cad30; 1 drivers +v0x28e7170_0 .net "nCmd2", 0 0, L_0x29cb470; 1 drivers +v0x28e7270_0 .net "subtract", 0 0, L_0x29cc4e0; 1 drivers +L_0x29cb3d0 .part v0x2960210_0, 0, 1; +L_0x29cc440 .part v0x2960210_0, 2, 1; +L_0x29cc620 .part v0x2960210_0, 0, 1; +S_0x28e63e0 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x28e62f0; + .timescale -9 -12; +L_0x29caf20/d .functor NOT 1, L_0x29cb3d0, C4<0>, C4<0>, C4<0>; +L_0x29caf20 .delay (10000,10000,10000) L_0x29caf20/d; +L_0x29cafe0/d .functor AND 1, L_0x29cbbe0, L_0x29caf20, C4<1>, C4<1>; +L_0x29cafe0 .delay (20000,20000,20000) L_0x29cafe0/d; +L_0x29cb0f0/d .functor AND 1, L_0x29cad30, L_0x29cb3d0, C4<1>, C4<1>; +L_0x29cb0f0 .delay (20000,20000,20000) L_0x29cb0f0/d; +L_0x29cb200/d .functor OR 1, L_0x29cafe0, L_0x29cb0f0, C4<0>, C4<0>; +L_0x29cb200 .delay (20000,20000,20000) L_0x29cb200/d; +v0x28e64d0_0 .net "S", 0 0, L_0x29cb3d0; 1 drivers +v0x28e6590_0 .alias "in0", 0 0, v0x28e6bf0_0; +v0x28e6630_0 .alias "in1", 0 0, v0x28e70c0_0; +v0x28e66d0_0 .net "nS", 0 0, L_0x29caf20; 1 drivers +v0x28e6750_0 .net "out0", 0 0, L_0x29cafe0; 1 drivers +v0x28e67f0_0 .net "out1", 0 0, L_0x29cb0f0; 1 drivers +v0x28e68d0_0 .alias "outfinal", 0 0, v0x28e6ca0_0; +S_0x28e5d80 .scope module, "setSLTres2" "TwoInMux" 3 335, 3 109, S_0x28e5600; + .timescale -9 -12; +L_0x29cbdb0/d .functor NOT 1, L_0x29d1680, C4<0>, C4<0>, C4<0>; +L_0x29cbdb0 .delay (10000,10000,10000) L_0x29cbdb0/d; +L_0x29cbe50/d .functor AND 1, L_0x29cc1e0, L_0x29cbdb0, C4<1>, C4<1>; +L_0x29cbe50 .delay (20000,20000,20000) L_0x29cbe50/d; +L_0x29cbf60/d .functor AND 1, C4<0>, L_0x29d1680, C4<1>, C4<1>; +L_0x29cbf60 .delay (20000,20000,20000) L_0x29cbf60/d; +L_0x29cc000/d .functor OR 1, L_0x29cbe50, L_0x29cbf60, C4<0>, C4<0>; +L_0x29cc000 .delay (20000,20000,20000) L_0x29cc000/d; +v0x28e5e70_0 .alias "S", 0 0, v0x293b720_0; +v0x28e5f10_0 .net "in0", 0 0, L_0x29cc1e0; 1 drivers +v0x28e5fb0_0 .net "in1", 0 0, C4<0>; 1 drivers +v0x28e6050_0 .net "nS", 0 0, L_0x29cbdb0; 1 drivers +v0x28e60d0_0 .net "out0", 0 0, L_0x29cbe50; 1 drivers +v0x28e6170_0 .net "out1", 0 0, L_0x29cbf60; 1 drivers +v0x28e6250_0 .net "outfinal", 0 0, L_0x29cc000; 1 drivers +S_0x28e5770 .scope module, "setSLTres3" "TwoInMux" 3 336, 3 109, S_0x28e5600; + .timescale -9 -12; +L_0x29cc360/d .functor NOT 1, L_0x29d1680, C4<0>, C4<0>, C4<0>; +L_0x29cc360 .delay (10000,10000,10000) L_0x29cc360/d; +L_0x29c9450/d .functor AND 1, L_0x29aa0f0, L_0x29cc360, C4<1>, C4<1>; +L_0x29c9450 .delay (20000,20000,20000) L_0x29c9450/d; +L_0x29cd9c0/d .functor AND 1, L_0x29aa1e0, L_0x29d1680, C4<1>, C4<1>; +L_0x29cd9c0 .delay (20000,20000,20000) L_0x29cd9c0/d; +L_0x29cda60/d .functor OR 1, L_0x29c9450, L_0x29cd9c0, C4<0>, C4<0>; +L_0x29cda60 .delay (20000,20000,20000) L_0x29cda60/d; +v0x28e5860_0 .alias "S", 0 0, v0x293b720_0; +v0x28e5970_0 .net "in0", 0 0, L_0x29aa0f0; 1 drivers +v0x28e5a10_0 .net "in1", 0 0, L_0x29aa1e0; 1 drivers +v0x28e5ab0_0 .net "nS", 0 0, L_0x29cc360; 1 drivers +v0x28e5b60_0 .net "out0", 0 0, L_0x29c9450; 1 drivers +v0x28e5c00_0 .net "out1", 0 0, L_0x29cd9c0; 1 drivers +v0x28e5ce0_0 .net "outfinal", 0 0, L_0x29cda60; 1 drivers +S_0x28e3960 .scope generate, "sltbits[30]" "sltbits[30]" 3 332, 3 332, S_0x28e1a50; + .timescale -9 -12; +P_0x28e3258 .param/l "i" 3 332, +C4<011110>; +S_0x28e4590 .scope module, "attempt" "MiddleAddSubSLT" 3 334, 3 189, S_0x28e3960; + .timescale -9 -12; +L_0x29cce40/d .functor NOT 1, L_0x29ce2d0, C4<0>, C4<0>, C4<0>; +L_0x29cce40 .delay (10000,10000,10000) L_0x29cce40/d; +L_0x29cd560/d .functor NOT 1, L_0x29cd620, C4<0>, C4<0>, C4<0>; +L_0x29cd560 .delay (10000,10000,10000) L_0x29cd560/d; +L_0x29cd6c0/d .functor AND 1, L_0x29cea50, L_0x29cd560, C4<1>, C4<1>; +L_0x29cd6c0 .delay (20000,20000,20000) L_0x29cd6c0/d; +L_0x29ceaf0/d .functor XOR 1, L_0x29ce230, L_0x29cd2f0, C4<0>, C4<0>; +L_0x29ceaf0 .delay (40000,40000,40000) L_0x29ceaf0/d; +L_0x29cebe0/d .functor XOR 1, L_0x29ceaf0, L_0x29ce400, C4<0>, C4<0>; +L_0x29cebe0 .delay (40000,40000,40000) L_0x29cebe0/d; +L_0x29cecd0/d .functor AND 1, L_0x29ce230, L_0x29cd2f0, C4<1>, C4<1>; +L_0x29cecd0 .delay (20000,20000,20000) L_0x29cecd0/d; +L_0x29cee40/d .functor AND 1, L_0x29ceaf0, L_0x29ce400, C4<1>, C4<1>; +L_0x29cee40 .delay (20000,20000,20000) L_0x29cee40/d; +L_0x29cef30/d .functor OR 1, L_0x29cecd0, L_0x29cee40, C4<0>, C4<0>; +L_0x29cef30 .delay (20000,20000,20000) L_0x29cef30/d; +v0x28e4c10_0 .net "A", 0 0, L_0x29ce230; 1 drivers +v0x28e4cd0_0 .net "AandB", 0 0, L_0x29cecd0; 1 drivers +v0x28e4d70_0 .net "AddSubSLTSum", 0 0, L_0x29cebe0; 1 drivers +v0x28e4e10_0 .net "AxorB", 0 0, L_0x29ceaf0; 1 drivers +v0x28e4e90_0 .net "B", 0 0, L_0x29ce2d0; 1 drivers +v0x28e4f40_0 .net "BornB", 0 0, L_0x29cd2f0; 1 drivers +v0x28e5000_0 .net "CINandAxorB", 0 0, L_0x29cee40; 1 drivers +v0x28e5080_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x28e5150_0 .net *"_s3", 0 0, L_0x29cd620; 1 drivers +v0x28e51d0_0 .net *"_s5", 0 0, L_0x29cea50; 1 drivers +v0x28e5270_0 .net "carryin", 0 0, L_0x29ce400; 1 drivers +v0x28e5310_0 .net "carryout", 0 0, L_0x29cef30; 1 drivers +v0x28e53b0_0 .net "nB", 0 0, L_0x29cce40; 1 drivers +v0x28e5460_0 .net "nCmd2", 0 0, L_0x29cd560; 1 drivers +v0x28e5560_0 .net "subtract", 0 0, L_0x29cd6c0; 1 drivers +L_0x29cd4c0 .part v0x2960210_0, 0, 1; +L_0x29cd620 .part v0x2960210_0, 2, 1; +L_0x29cea50 .part v0x2960210_0, 0, 1; +S_0x28e4680 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x28e4590; + .timescale -9 -12; +L_0x29cd010/d .functor NOT 1, L_0x29cd4c0, C4<0>, C4<0>, C4<0>; +L_0x29cd010 .delay (10000,10000,10000) L_0x29cd010/d; +L_0x29cd0d0/d .functor AND 1, L_0x29ce2d0, L_0x29cd010, C4<1>, C4<1>; +L_0x29cd0d0 .delay (20000,20000,20000) L_0x29cd0d0/d; +L_0x29cd1e0/d .functor AND 1, L_0x29cce40, L_0x29cd4c0, C4<1>, C4<1>; +L_0x29cd1e0 .delay (20000,20000,20000) L_0x29cd1e0/d; +L_0x29cd2f0/d .functor OR 1, L_0x29cd0d0, L_0x29cd1e0, C4<0>, C4<0>; +L_0x29cd2f0 .delay (20000,20000,20000) L_0x29cd2f0/d; +v0x28e4770_0 .net "S", 0 0, L_0x29cd4c0; 1 drivers +v0x28e4830_0 .alias "in0", 0 0, v0x28e4e90_0; +v0x28e48d0_0 .alias "in1", 0 0, v0x28e53b0_0; +v0x28e4970_0 .net "nS", 0 0, L_0x29cd010; 1 drivers +v0x28e49f0_0 .net "out0", 0 0, L_0x29cd0d0; 1 drivers +v0x28e4a90_0 .net "out1", 0 0, L_0x29cd1e0; 1 drivers +v0x28e4b70_0 .alias "outfinal", 0 0, v0x28e4f40_0; +S_0x28e4020 .scope module, "setSLTres2" "TwoInMux" 3 335, 3 109, S_0x28e3960; + .timescale -9 -12; +L_0x29ce4a0/d .functor NOT 1, L_0x29d1680, C4<0>, C4<0>, C4<0>; +L_0x29ce4a0 .delay (10000,10000,10000) L_0x29ce4a0/d; +L_0x29ce540/d .functor AND 1, L_0x29ce8d0, L_0x29ce4a0, C4<1>, C4<1>; +L_0x29ce540 .delay (20000,20000,20000) L_0x29ce540/d; +L_0x29ce650/d .functor AND 1, C4<0>, L_0x29d1680, C4<1>, C4<1>; +L_0x29ce650 .delay (20000,20000,20000) L_0x29ce650/d; +L_0x29ce6f0/d .functor OR 1, L_0x29ce540, L_0x29ce650, C4<0>, C4<0>; +L_0x29ce6f0 .delay (20000,20000,20000) L_0x29ce6f0/d; +v0x28e4110_0 .alias "S", 0 0, v0x293b720_0; +v0x28e41b0_0 .net "in0", 0 0, L_0x29ce8d0; 1 drivers +v0x28e4250_0 .net "in1", 0 0, C4<0>; 1 drivers +v0x28e42f0_0 .net "nS", 0 0, L_0x29ce4a0; 1 drivers +v0x28e4370_0 .net "out0", 0 0, L_0x29ce540; 1 drivers +v0x28e4410_0 .net "out1", 0 0, L_0x29ce650; 1 drivers +v0x28e44f0_0 .net "outfinal", 0 0, L_0x29ce6f0; 1 drivers +S_0x28e3ad0 .scope module, "setSLTres3" "TwoInMux" 3 336, 3 109, S_0x28e3960; + .timescale -9 -12; +L_0x29cfba0/d .functor NOT 1, L_0x29d1680, C4<0>, C4<0>, C4<0>; +L_0x29cfba0 .delay (10000,10000,10000) L_0x29cfba0/d; +L_0x29cfc90/d .functor AND 1, L_0x29cf160, L_0x29cfba0, C4<1>, C4<1>; +L_0x29cfc90 .delay (20000,20000,20000) L_0x29cfc90/d; +L_0x29cfd80/d .functor AND 1, L_0x29cf250, L_0x29d1680, C4<1>, C4<1>; +L_0x29cfd80 .delay (20000,20000,20000) L_0x29cfd80/d; +L_0x29cfe20/d .functor OR 1, L_0x29cfc90, L_0x29cfd80, C4<0>, C4<0>; +L_0x29cfe20 .delay (20000,20000,20000) L_0x29cfe20/d; +v0x28e3bc0_0 .alias "S", 0 0, v0x293b720_0; +v0x28e3c40_0 .net "in0", 0 0, L_0x29cf160; 1 drivers +v0x28e3ce0_0 .net "in1", 0 0, L_0x29cf250; 1 drivers +v0x28e3d80_0 .net "nS", 0 0, L_0x29cfba0; 1 drivers +v0x28e3e00_0 .net "out0", 0 0, L_0x29cfc90; 1 drivers +v0x28e3ea0_0 .net "out1", 0 0, L_0x29cfd80; 1 drivers +v0x28e3f80_0 .net "outfinal", 0 0, L_0x29cfe20; 1 drivers +S_0x28e1bc0 .scope generate, "sltbits[31]" "sltbits[31]" 3 332, 3 332, S_0x28e1a50; + .timescale -9 -12; +P_0x28e1cb8 .param/l "i" 3 332, +C4<011111>; +S_0x28e2820 .scope module, "attempt" "MiddleAddSubSLT" 3 334, 3 189, S_0x28e1bc0; + .timescale -9 -12; +L_0x29cf340/d .functor NOT 1, L_0x29d01c0, C4<0>, C4<0>, C4<0>; +L_0x29cf340 .delay (10000,10000,10000) L_0x29cf340/d; +L_0x29cfa80/d .functor NOT 1, L_0x29d0a90, C4<0>, C4<0>, C4<0>; +L_0x29cfa80 .delay (10000,10000,10000) L_0x29cfa80/d; +L_0x29cfb40/d .functor AND 1, L_0x29d0c10, L_0x29cfa80, C4<1>, C4<1>; +L_0x29cfb40 .delay (20000,20000,20000) L_0x29cfb40/d; +L_0x29d0cb0/d .functor XOR 1, L_0x29d0120, L_0x29cf810, C4<0>, C4<0>; +L_0x29d0cb0 .delay (40000,40000,40000) L_0x29d0cb0/d; +L_0x29d0da0/d .functor XOR 1, L_0x29d0cb0, L_0x29d02f0, C4<0>, C4<0>; +L_0x29d0da0 .delay (40000,40000,40000) L_0x29d0da0/d; +L_0x29d0e90/d .functor AND 1, L_0x29d0120, L_0x29cf810, C4<1>, C4<1>; +L_0x29d0e90 .delay (20000,20000,20000) L_0x29d0e90/d; +L_0x29d1000/d .functor AND 1, L_0x29d0cb0, L_0x29d02f0, C4<1>, C4<1>; +L_0x29d1000 .delay (20000,20000,20000) L_0x29d1000/d; +L_0x29d10f0/d .functor OR 1, L_0x29d0e90, L_0x29d1000, C4<0>, C4<0>; +L_0x29d10f0 .delay (20000,20000,20000) L_0x29d10f0/d; +v0x28e2ea0_0 .net "A", 0 0, L_0x29d0120; 1 drivers +v0x28e2f60_0 .net "AandB", 0 0, L_0x29d0e90; 1 drivers +v0x28e3000_0 .net "AddSubSLTSum", 0 0, L_0x29d0da0; 1 drivers +v0x28e30a0_0 .net "AxorB", 0 0, L_0x29d0cb0; 1 drivers +v0x28e3120_0 .net "B", 0 0, L_0x29d01c0; 1 drivers +v0x28e31d0_0 .net "BornB", 0 0, L_0x29cf810; 1 drivers +v0x28e3290_0 .net "CINandAxorB", 0 0, L_0x29d1000; 1 drivers +v0x28e3310_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x28e33e0_0 .net *"_s3", 0 0, L_0x29d0a90; 1 drivers +v0x28e3460_0 .net *"_s5", 0 0, L_0x29d0c10; 1 drivers +v0x28e3560_0 .net "carryin", 0 0, L_0x29d02f0; 1 drivers +v0x28e3600_0 .net "carryout", 0 0, L_0x29d10f0; 1 drivers +v0x28e3710_0 .net "nB", 0 0, L_0x29cf340; 1 drivers +v0x28e37c0_0 .net "nCmd2", 0 0, L_0x29cfa80; 1 drivers +v0x28e38c0_0 .net "subtract", 0 0, L_0x29cfb40; 1 drivers +L_0x29cf9e0 .part v0x2960210_0, 0, 1; +L_0x29d0a90 .part v0x2960210_0, 2, 1; +L_0x29d0c10 .part v0x2960210_0, 0, 1; +S_0x28e2910 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x28e2820; + .timescale -9 -12; +L_0x29cf530/d .functor NOT 1, L_0x29cf9e0, C4<0>, C4<0>, C4<0>; +L_0x29cf530 .delay (10000,10000,10000) L_0x29cf530/d; +L_0x29cf5f0/d .functor AND 1, L_0x29d01c0, L_0x29cf530, C4<1>, C4<1>; +L_0x29cf5f0 .delay (20000,20000,20000) L_0x29cf5f0/d; +L_0x29cf700/d .functor AND 1, L_0x29cf340, L_0x29cf9e0, C4<1>, C4<1>; +L_0x29cf700 .delay (20000,20000,20000) L_0x29cf700/d; +L_0x29cf810/d .functor OR 1, L_0x29cf5f0, L_0x29cf700, C4<0>, C4<0>; +L_0x29cf810 .delay (20000,20000,20000) L_0x29cf810/d; +v0x28e2a00_0 .net "S", 0 0, L_0x29cf9e0; 1 drivers +v0x28e2ac0_0 .alias "in0", 0 0, v0x28e3120_0; +v0x28e2b60_0 .alias "in1", 0 0, v0x28e3710_0; +v0x28e2c00_0 .net "nS", 0 0, L_0x29cf530; 1 drivers +v0x28e2c80_0 .net "out0", 0 0, L_0x29cf5f0; 1 drivers +v0x28e2d20_0 .net "out1", 0 0, L_0x29cf700; 1 drivers +v0x28e2e00_0 .alias "outfinal", 0 0, v0x28e31d0_0; +S_0x28e22a0 .scope module, "setSLTres2" "TwoInMux" 3 335, 3 109, S_0x28e1bc0; + .timescale -9 -12; +L_0x29d0390/d .functor NOT 1, L_0x29d1680, C4<0>, C4<0>, C4<0>; +L_0x29d0390 .delay (10000,10000,10000) L_0x29d0390/d; +L_0x29d0430/d .functor AND 1, L_0x29d07c0, L_0x29d0390, C4<1>, C4<1>; +L_0x29d0430 .delay (20000,20000,20000) L_0x29d0430/d; +L_0x29d0540/d .functor AND 1, C4<0>, L_0x29d1680, C4<1>, C4<1>; +L_0x29d0540 .delay (20000,20000,20000) L_0x29d0540/d; +L_0x29d05e0/d .functor OR 1, L_0x29d0430, L_0x29d0540, C4<0>, C4<0>; +L_0x29d05e0 .delay (20000,20000,20000) L_0x29d05e0/d; +v0x28e2390_0 .alias "S", 0 0, v0x293b720_0; +v0x28e2430_0 .net "in0", 0 0, L_0x29d07c0; 1 drivers +v0x28e24b0_0 .net "in1", 0 0, C4<0>; 1 drivers +v0x28e2550_0 .net "nS", 0 0, L_0x29d0390; 1 drivers +v0x28e2600_0 .net "out0", 0 0, L_0x29d0430; 1 drivers +v0x28e26a0_0 .net "out1", 0 0, L_0x29d0540; 1 drivers +v0x28e2780_0 .net "outfinal", 0 0, L_0x29d05e0; 1 drivers +S_0x28e1d30 .scope module, "setSLTres3" "TwoInMux" 3 336, 3 109, S_0x28e1bc0; + .timescale -9 -12; +L_0x29cd830/d .functor NOT 1, L_0x29d1680, C4<0>, C4<0>, C4<0>; +L_0x29cd830 .delay (10000,10000,10000) L_0x29cd830/d; +L_0x29d1eb0/d .functor AND 1, L_0x29d2220, L_0x29cd830, C4<1>, C4<1>; +L_0x29d1eb0 .delay (20000,20000,20000) L_0x29d1eb0/d; +L_0x29d1fa0/d .functor AND 1, L_0x29d1410, L_0x29d1680, C4<1>, C4<1>; +L_0x29d1fa0 .delay (20000,20000,20000) L_0x29d1fa0/d; +L_0x29d2040/d .functor OR 1, L_0x29d1eb0, L_0x29d1fa0, C4<0>, C4<0>; +L_0x29d2040 .delay (20000,20000,20000) L_0x29d2040/d; +v0x28e1e20_0 .alias "S", 0 0, v0x293b720_0; +v0x28e1ec0_0 .net "in0", 0 0, L_0x29d2220; 1 drivers +v0x28e1f60_0 .net "in1", 0 0, L_0x29d1410; 1 drivers +v0x28e2000_0 .net "nS", 0 0, L_0x29cd830; 1 drivers +v0x28e2080_0 .net "out0", 0 0, L_0x29d1eb0; 1 drivers +v0x28e2120_0 .net "out1", 0 0, L_0x29d1fa0; 1 drivers +v0x28e2200_0 .net "outfinal", 0 0, L_0x29d2040; 1 drivers +S_0x28ca040 .scope module, "trial1" "AndNand32" 2 158, 3 216, S_0x22efd20; + .timescale -9 -12; +P_0x28c9b58 .param/l "size" 3 223, +C4<0100000>; +v0x28e1800_0 .alias "A", 31 0, v0x295f580_0; +v0x28e1880_0 .alias "AndNandOut", 31 0, v0x2960110_0; +v0x28e1950_0 .alias "B", 31 0, v0x295f6a0_0; +v0x28e19d0_0 .alias "Command", 2 0, v0x295f7a0_0; +L_0x29d55b0 .part/pv L_0x29d5340, 1, 1, 32; +L_0x29d5700 .part v0x295fe90_0, 1, 1; +L_0x29d57a0 .part v0x2960190_0, 1, 1; +L_0x29d72e0 .part/pv L_0x29d7070, 2, 1, 32; +L_0x29d7380 .part v0x295fe90_0, 2, 1; +L_0x29d7420 .part v0x2960190_0, 2, 1; +L_0x29d7d50 .part/pv L_0x29d7ae0, 3, 1, 32; +L_0x29d7df0 .part v0x295fe90_0, 3, 1; +L_0x29d7ee0 .part v0x2960190_0, 3, 1; +L_0x29d87b0 .part/pv L_0x29d8540, 4, 1, 32; +L_0x29d88b0 .part v0x295fe90_0, 4, 1; +L_0x29d8950 .part v0x2960190_0, 4, 1; +L_0x29d9220 .part/pv L_0x29d8fb0, 5, 1, 32; +L_0x29d93d0 .part v0x295fe90_0, 5, 1; +L_0x29d9470 .part v0x2960190_0, 5, 1; +L_0x29d9d80 .part/pv L_0x29d9b10, 6, 1, 32; +L_0x29d9e20 .part v0x295fe90_0, 6, 1; +L_0x29d9ec0 .part v0x2960190_0, 6, 1; +L_0x29da7f0 .part/pv L_0x29da580, 7, 1, 32; +L_0x29da890 .part v0x295fe90_0, 7, 1; +L_0x29d9fb0 .part v0x2960190_0, 7, 1; +L_0x29db250 .part/pv L_0x29dafe0, 8, 1, 32; +L_0x29da930 .part v0x295fe90_0, 8, 1; +L_0x29db3b0 .part v0x2960190_0, 8, 1; +L_0x29dbcd0 .part/pv L_0x29dba60, 9, 1, 32; +L_0x29dbd70 .part v0x295fe90_0, 9, 1; +L_0x29db4a0 .part v0x2960190_0, 9, 1; +L_0x29dc740 .part/pv L_0x29dc4d0, 10, 1, 32; +L_0x29dbe10 .part v0x295fe90_0, 10, 1; +L_0x29dc8d0 .part v0x2960190_0, 10, 1; +L_0x29dd1b0 .part/pv L_0x29dcf40, 11, 1, 32; +L_0x29dd250 .part v0x295fe90_0, 11, 1; +L_0x29dc9c0 .part v0x2960190_0, 11, 1; +L_0x29ddc20 .part/pv L_0x29dd9b0, 12, 1, 32; +L_0x29dd2f0 .part v0x295fe90_0, 12, 1; +L_0x29ddde0 .part v0x2960190_0, 12, 1; +L_0x29de6a0 .part/pv L_0x29de430, 13, 1, 32; +L_0x29d92c0 .part v0x295fe90_0, 13, 1; +L_0x29dde80 .part v0x2960190_0, 13, 1; +L_0x29df210 .part/pv L_0x29defa0, 14, 1, 32; +L_0x29de950 .part v0x295fe90_0, 14, 1; +L_0x29de9f0 .part v0x2960190_0, 14, 1; +L_0x29dfc80 .part/pv L_0x29dfa10, 15, 1, 32; +L_0x29dfd20 .part v0x295fe90_0, 15, 1; +L_0x29df450 .part v0x2960190_0, 15, 1; +L_0x29e06f0 .part/pv L_0x29e0480, 16, 1, 32; +L_0x29dfdc0 .part v0x295fe90_0, 16, 1; +L_0x29dfe60 .part v0x2960190_0, 16, 1; +L_0x29e1170 .part/pv L_0x29e0f00, 17, 1, 32; +L_0x29e1210 .part v0x295fe90_0, 17, 1; +L_0x29e0960 .part v0x2960190_0, 17, 1; +L_0x29e1bd0 .part/pv L_0x29e1960, 18, 1, 32; +L_0x29e12b0 .part v0x295fe90_0, 18, 1; +L_0x29e1350 .part v0x2960190_0, 18, 1; +L_0x29e2650 .part/pv L_0x29e23e0, 19, 1, 32; +L_0x29e26f0 .part v0x295fe90_0, 19, 1; +L_0x29e1c70 .part v0x2960190_0, 19, 1; +L_0x29e30b0 .part/pv L_0x29e2e40, 20, 1, 32; +L_0x29e2790 .part v0x295fe90_0, 20, 1; +L_0x29e2830 .part v0x2960190_0, 20, 1; +L_0x29e3b20 .part/pv L_0x29e38b0, 21, 1, 32; +L_0x29e3bc0 .part v0x295fe90_0, 21, 1; +L_0x29e3150 .part v0x2960190_0, 21, 1; +L_0x29e4590 .part/pv L_0x29e4320, 22, 1, 32; +L_0x29e3c60 .part v0x295fe90_0, 22, 1; +L_0x29e3d00 .part v0x2960190_0, 22, 1; +L_0x29e5010 .part/pv L_0x29e4da0, 23, 1, 32; +L_0x29e50b0 .part v0x295fe90_0, 23, 1; +L_0x29e4630 .part v0x2960190_0, 23, 1; +L_0x29e5a70 .part/pv L_0x29e5800, 24, 1, 32; +L_0x29e5150 .part v0x295fe90_0, 24, 1; +L_0x29e51f0 .part v0x2960190_0, 24, 1; +L_0x29e64e0 .part/pv L_0x29e6270, 25, 1, 32; +L_0x29e6580 .part v0x295fe90_0, 25, 1; +L_0x29e5b10 .part v0x2960190_0, 25, 1; +L_0x29e6f40 .part/pv L_0x29e6cd0, 26, 1, 32; +L_0x29e6620 .part v0x295fe90_0, 26, 1; +L_0x29e66c0 .part v0x2960190_0, 26, 1; +L_0x29e79b0 .part/pv L_0x29e7740, 27, 1, 32; +L_0x29e7a50 .part v0x295fe90_0, 27, 1; +L_0x29e6fe0 .part v0x2960190_0, 27, 1; +L_0x29e8420 .part/pv L_0x29e81b0, 28, 1, 32; +L_0x29e7af0 .part v0x295fe90_0, 28, 1; +L_0x29e7b90 .part v0x2960190_0, 28, 1; +L_0x29e8ea0 .part/pv L_0x29e8c30, 29, 1, 32; +L_0x29de740 .part v0x295fe90_0, 29, 1; +L_0x29de7e0 .part v0x2960190_0, 29, 1; +L_0x29e9a60 .part/pv L_0x29e9830, 30, 1, 32; +L_0x29e9350 .part v0x295fe90_0, 30, 1; +L_0x29e93f0 .part v0x2960190_0, 30, 1; +L_0x29ea410 .part/pv L_0x29ea1e0, 31, 1, 32; +L_0x29ea4b0 .part v0x295fe90_0, 31, 1; +L_0x29e9b00 .part v0x2960190_0, 31, 1; +L_0x29eadc0 .part/pv L_0x29eab90, 0, 1, 32; +L_0x29ea550 .part v0x295fe90_0, 0, 1; +L_0x29ea5f0 .part v0x2960190_0, 0, 1; +S_0x28e0dd0 .scope module, "attempt2" "AndNand" 3 227, 3 149, S_0x28ca040; + .timescale -9 -12; +L_0x29e9bf0/d .functor NAND 1, L_0x29ea550, L_0x29ea5f0, C4<1>, C4<1>; +L_0x29e9bf0 .delay (10000,10000,10000) L_0x29e9bf0/d; +L_0x29e9d50/d .functor NOT 1, L_0x29e9bf0, C4<0>, C4<0>, C4<0>; +L_0x29e9d50 .delay (10000,10000,10000) L_0x29e9d50/d; +v0x28e13f0_0 .net "A", 0 0, L_0x29ea550; 1 drivers +v0x28e14b0_0 .net "AandB", 0 0, L_0x29e9d50; 1 drivers +v0x28e1530_0 .net "AnandB", 0 0, L_0x29e9bf0; 1 drivers +v0x28e15e0_0 .net "AndNandOut", 0 0, L_0x29eab90; 1 drivers +v0x28e16c0_0 .net "B", 0 0, L_0x29ea5f0; 1 drivers +v0x28e1740_0 .alias "Command", 2 0, v0x295f7a0_0; +L_0x29ead20 .part v0x2960210_0, 0, 1; +S_0x28e0ec0 .scope module, "potato" "TwoInMux" 3 161, 3 109, S_0x28e0dd0; + .timescale -9 -12; +L_0x29ea8d0/d .functor NOT 1, L_0x29ead20, C4<0>, C4<0>, C4<0>; +L_0x29ea8d0 .delay (10000,10000,10000) L_0x29ea8d0/d; +L_0x29ea970/d .functor AND 1, L_0x29e9d50, L_0x29ea8d0, C4<1>, C4<1>; +L_0x29ea970 .delay (20000,20000,20000) L_0x29ea970/d; +L_0x29eaa60/d .functor AND 1, L_0x29e9bf0, L_0x29ead20, C4<1>, C4<1>; +L_0x29eaa60 .delay (20000,20000,20000) L_0x29eaa60/d; +L_0x29eab90/d .functor OR 1, L_0x29ea970, L_0x29eaa60, C4<0>, C4<0>; +L_0x29eab90 .delay (20000,20000,20000) L_0x29eab90/d; +v0x28e0fb0_0 .net "S", 0 0, L_0x29ead20; 1 drivers +v0x28e1030_0 .alias "in0", 0 0, v0x28e14b0_0; +v0x28e10b0_0 .alias "in1", 0 0, v0x28e1530_0; +v0x28e1150_0 .net "nS", 0 0, L_0x29ea8d0; 1 drivers +v0x28e11d0_0 .net "out0", 0 0, L_0x29ea970; 1 drivers +v0x28e1270_0 .net "out1", 0 0, L_0x29eaa60; 1 drivers +v0x28e1350_0 .alias "outfinal", 0 0, v0x28e15e0_0; +S_0x28e0210 .scope generate, "andbits[1]" "andbits[1]" 3 231, 3 231, S_0x28ca040; + .timescale -9 -12; +P_0x28e0308 .param/l "i" 3 231, +C4<01>; +S_0x28e0380 .scope module, "attempt" "AndNand" 3 233, 3 149, S_0x28e0210; + .timescale -9 -12; +L_0x29d4db0/d .functor NAND 1, L_0x29d5700, L_0x29d57a0, C4<1>, C4<1>; +L_0x29d4db0 .delay (10000,10000,10000) L_0x29d4db0/d; +L_0x29d4ef0/d .functor NOT 1, L_0x29d4db0, C4<0>, C4<0>, C4<0>; +L_0x29d4ef0 .delay (10000,10000,10000) L_0x29d4ef0/d; +v0x28e09c0_0 .net "A", 0 0, L_0x29d5700; 1 drivers +v0x28e0a80_0 .net "AandB", 0 0, L_0x29d4ef0; 1 drivers +v0x28e0b00_0 .net "AnandB", 0 0, L_0x29d4db0; 1 drivers +v0x28e0bb0_0 .net "AndNandOut", 0 0, L_0x29d5340; 1 drivers +v0x28e0c90_0 .net "B", 0 0, L_0x29d57a0; 1 drivers +v0x28e0d10_0 .alias "Command", 2 0, v0x295f7a0_0; +L_0x29d5510 .part v0x2960210_0, 0, 1; +S_0x28e0470 .scope module, "potato" "TwoInMux" 3 161, 3 109, S_0x28e0380; + .timescale -9 -12; +L_0x29d5020/d .functor NOT 1, L_0x29d5510, C4<0>, C4<0>, C4<0>; +L_0x29d5020 .delay (10000,10000,10000) L_0x29d5020/d; +L_0x29d50e0/d .functor AND 1, L_0x29d4ef0, L_0x29d5020, C4<1>, C4<1>; +L_0x29d50e0 .delay (20000,20000,20000) L_0x29d50e0/d; +L_0x29d51f0/d .functor AND 1, L_0x29d4db0, L_0x29d5510, C4<1>, C4<1>; +L_0x29d51f0 .delay (20000,20000,20000) L_0x29d51f0/d; +L_0x29d5340/d .functor OR 1, L_0x29d50e0, L_0x29d51f0, C4<0>, C4<0>; +L_0x29d5340 .delay (20000,20000,20000) L_0x29d5340/d; +v0x28e0560_0 .net "S", 0 0, L_0x29d5510; 1 drivers +v0x28e05e0_0 .alias "in0", 0 0, v0x28e0a80_0; +v0x28e0680_0 .alias "in1", 0 0, v0x28e0b00_0; +v0x28e0720_0 .net "nS", 0 0, L_0x29d5020; 1 drivers +v0x28e07a0_0 .net "out0", 0 0, L_0x29d50e0; 1 drivers +v0x28e0840_0 .net "out1", 0 0, L_0x29d51f0; 1 drivers +v0x28e0920_0 .alias "outfinal", 0 0, v0x28e0bb0_0; +S_0x28df650 .scope generate, "andbits[2]" "andbits[2]" 3 231, 3 231, S_0x28ca040; + .timescale -9 -12; +P_0x28df748 .param/l "i" 3 231, +C4<010>; +S_0x28df7c0 .scope module, "attempt" "AndNand" 3 233, 3 149, S_0x28df650; + .timescale -9 -12; +L_0x29d5840/d .functor NAND 1, L_0x29d7380, L_0x29d7420, C4<1>, C4<1>; +L_0x29d5840 .delay (10000,10000,10000) L_0x29d5840/d; +L_0x29d6c40/d .functor NOT 1, L_0x29d5840, C4<0>, C4<0>, C4<0>; +L_0x29d6c40 .delay (10000,10000,10000) L_0x29d6c40/d; +v0x28dfe00_0 .net "A", 0 0, L_0x29d7380; 1 drivers +v0x28dfec0_0 .net "AandB", 0 0, L_0x29d6c40; 1 drivers +v0x28dff40_0 .net "AnandB", 0 0, L_0x29d5840; 1 drivers +v0x28dfff0_0 .net "AndNandOut", 0 0, L_0x29d7070; 1 drivers +v0x28e00d0_0 .net "B", 0 0, L_0x29d7420; 1 drivers +v0x28e0150_0 .alias "Command", 2 0, v0x295f7a0_0; +L_0x29d7240 .part v0x2960210_0, 0, 1; +S_0x28df8b0 .scope module, "potato" "TwoInMux" 3 161, 3 109, S_0x28df7c0; + .timescale -9 -12; +L_0x29d6d50/d .functor NOT 1, L_0x29d7240, C4<0>, C4<0>, C4<0>; +L_0x29d6d50 .delay (10000,10000,10000) L_0x29d6d50/d; +L_0x29d6e10/d .functor AND 1, L_0x29d6c40, L_0x29d6d50, C4<1>, C4<1>; +L_0x29d6e10 .delay (20000,20000,20000) L_0x29d6e10/d; +L_0x29d6f20/d .functor AND 1, L_0x29d5840, L_0x29d7240, C4<1>, C4<1>; +L_0x29d6f20 .delay (20000,20000,20000) L_0x29d6f20/d; +L_0x29d7070/d .functor OR 1, L_0x29d6e10, L_0x29d6f20, C4<0>, C4<0>; +L_0x29d7070 .delay (20000,20000,20000) L_0x29d7070/d; +v0x28df9a0_0 .net "S", 0 0, L_0x29d7240; 1 drivers +v0x28dfa20_0 .alias "in0", 0 0, v0x28dfec0_0; +v0x28dfac0_0 .alias "in1", 0 0, v0x28dff40_0; +v0x28dfb60_0 .net "nS", 0 0, L_0x29d6d50; 1 drivers +v0x28dfbe0_0 .net "out0", 0 0, L_0x29d6e10; 1 drivers +v0x28dfc80_0 .net "out1", 0 0, L_0x29d6f20; 1 drivers +v0x28dfd60_0 .alias "outfinal", 0 0, v0x28dfff0_0; +S_0x28dea90 .scope generate, "andbits[3]" "andbits[3]" 3 231, 3 231, S_0x28ca040; + .timescale -9 -12; +P_0x28deb88 .param/l "i" 3 231, +C4<011>; +S_0x28dec00 .scope module, "attempt" "AndNand" 3 233, 3 149, S_0x28dea90; + .timescale -9 -12; +L_0x29d7550/d .functor NAND 1, L_0x29d7df0, L_0x29d7ee0, C4<1>, C4<1>; +L_0x29d7550 .delay (10000,10000,10000) L_0x29d7550/d; +L_0x29d7690/d .functor NOT 1, L_0x29d7550, C4<0>, C4<0>, C4<0>; +L_0x29d7690 .delay (10000,10000,10000) L_0x29d7690/d; +v0x28df240_0 .net "A", 0 0, L_0x29d7df0; 1 drivers +v0x28df300_0 .net "AandB", 0 0, L_0x29d7690; 1 drivers +v0x28df380_0 .net "AnandB", 0 0, L_0x29d7550; 1 drivers +v0x28df430_0 .net "AndNandOut", 0 0, L_0x29d7ae0; 1 drivers +v0x28df510_0 .net "B", 0 0, L_0x29d7ee0; 1 drivers +v0x28df590_0 .alias "Command", 2 0, v0x295f7a0_0; +L_0x29d7cb0 .part v0x2960210_0, 0, 1; +S_0x28decf0 .scope module, "potato" "TwoInMux" 3 161, 3 109, S_0x28dec00; + .timescale -9 -12; +L_0x29d77c0/d .functor NOT 1, L_0x29d7cb0, C4<0>, C4<0>, C4<0>; +L_0x29d77c0 .delay (10000,10000,10000) L_0x29d77c0/d; +L_0x29d7880/d .functor AND 1, L_0x29d7690, L_0x29d77c0, C4<1>, C4<1>; +L_0x29d7880 .delay (20000,20000,20000) L_0x29d7880/d; +L_0x29d7990/d .functor AND 1, L_0x29d7550, L_0x29d7cb0, C4<1>, C4<1>; +L_0x29d7990 .delay (20000,20000,20000) L_0x29d7990/d; +L_0x29d7ae0/d .functor OR 1, L_0x29d7880, L_0x29d7990, C4<0>, C4<0>; +L_0x29d7ae0 .delay (20000,20000,20000) L_0x29d7ae0/d; +v0x28dede0_0 .net "S", 0 0, L_0x29d7cb0; 1 drivers +v0x28dee60_0 .alias "in0", 0 0, v0x28df300_0; +v0x28def00_0 .alias "in1", 0 0, v0x28df380_0; +v0x28defa0_0 .net "nS", 0 0, L_0x29d77c0; 1 drivers +v0x28df020_0 .net "out0", 0 0, L_0x29d7880; 1 drivers +v0x28df0c0_0 .net "out1", 0 0, L_0x29d7990; 1 drivers +v0x28df1a0_0 .alias "outfinal", 0 0, v0x28df430_0; +S_0x28dded0 .scope generate, "andbits[4]" "andbits[4]" 3 231, 3 231, S_0x28ca040; + .timescale -9 -12; +P_0x28ddfc8 .param/l "i" 3 231, +C4<0100>; +S_0x28de040 .scope module, "attempt" "AndNand" 3 233, 3 149, S_0x28dded0; + .timescale -9 -12; +L_0x29d7fd0/d .functor NAND 1, L_0x29d88b0, L_0x29d8950, C4<1>, C4<1>; +L_0x29d7fd0 .delay (10000,10000,10000) L_0x29d7fd0/d; +L_0x29d80f0/d .functor NOT 1, L_0x29d7fd0, C4<0>, C4<0>, C4<0>; +L_0x29d80f0 .delay (10000,10000,10000) L_0x29d80f0/d; +v0x28de680_0 .net "A", 0 0, L_0x29d88b0; 1 drivers +v0x28de740_0 .net "AandB", 0 0, L_0x29d80f0; 1 drivers +v0x28de7c0_0 .net "AnandB", 0 0, L_0x29d7fd0; 1 drivers +v0x28de870_0 .net "AndNandOut", 0 0, L_0x29d8540; 1 drivers +v0x28de950_0 .net "B", 0 0, L_0x29d8950; 1 drivers +v0x28de9d0_0 .alias "Command", 2 0, v0x295f7a0_0; +L_0x29d8710 .part v0x2960210_0, 0, 1; +S_0x28de130 .scope module, "potato" "TwoInMux" 3 161, 3 109, S_0x28de040; + .timescale -9 -12; +L_0x29d8220/d .functor NOT 1, L_0x29d8710, C4<0>, C4<0>, C4<0>; +L_0x29d8220 .delay (10000,10000,10000) L_0x29d8220/d; +L_0x29d82e0/d .functor AND 1, L_0x29d80f0, L_0x29d8220, C4<1>, C4<1>; +L_0x29d82e0 .delay (20000,20000,20000) L_0x29d82e0/d; +L_0x29d83f0/d .functor AND 1, L_0x29d7fd0, L_0x29d8710, C4<1>, C4<1>; +L_0x29d83f0 .delay (20000,20000,20000) L_0x29d83f0/d; +L_0x29d8540/d .functor OR 1, L_0x29d82e0, L_0x29d83f0, C4<0>, C4<0>; +L_0x29d8540 .delay (20000,20000,20000) L_0x29d8540/d; +v0x28de220_0 .net "S", 0 0, L_0x29d8710; 1 drivers +v0x28de2a0_0 .alias "in0", 0 0, v0x28de740_0; +v0x28de340_0 .alias "in1", 0 0, v0x28de7c0_0; +v0x28de3e0_0 .net "nS", 0 0, L_0x29d8220; 1 drivers +v0x28de460_0 .net "out0", 0 0, L_0x29d82e0; 1 drivers +v0x28de500_0 .net "out1", 0 0, L_0x29d83f0; 1 drivers +v0x28de5e0_0 .alias "outfinal", 0 0, v0x28de870_0; +S_0x28dd310 .scope generate, "andbits[5]" "andbits[5]" 3 231, 3 231, S_0x28ca040; + .timescale -9 -12; +P_0x28dd408 .param/l "i" 3 231, +C4<0101>; +S_0x28dd480 .scope module, "attempt" "AndNand" 3 233, 3 149, S_0x28dd310; + .timescale -9 -12; +L_0x29d8850/d .functor NAND 1, L_0x29d93d0, L_0x29d9470, C4<1>, C4<1>; +L_0x29d8850 .delay (10000,10000,10000) L_0x29d8850/d; +L_0x29d8b60/d .functor NOT 1, L_0x29d8850, C4<0>, C4<0>, C4<0>; +L_0x29d8b60 .delay (10000,10000,10000) L_0x29d8b60/d; +v0x28ddac0_0 .net "A", 0 0, L_0x29d93d0; 1 drivers +v0x28ddb80_0 .net "AandB", 0 0, L_0x29d8b60; 1 drivers +v0x28ddc00_0 .net "AnandB", 0 0, L_0x29d8850; 1 drivers +v0x28ddcb0_0 .net "AndNandOut", 0 0, L_0x29d8fb0; 1 drivers +v0x28ddd90_0 .net "B", 0 0, L_0x29d9470; 1 drivers +v0x28dde10_0 .alias "Command", 2 0, v0x295f7a0_0; +L_0x29d9180 .part v0x2960210_0, 0, 1; +S_0x28dd570 .scope module, "potato" "TwoInMux" 3 161, 3 109, S_0x28dd480; + .timescale -9 -12; +L_0x29d8c90/d .functor NOT 1, L_0x29d9180, C4<0>, C4<0>, C4<0>; +L_0x29d8c90 .delay (10000,10000,10000) L_0x29d8c90/d; +L_0x29d8d50/d .functor AND 1, L_0x29d8b60, L_0x29d8c90, C4<1>, C4<1>; +L_0x29d8d50 .delay (20000,20000,20000) L_0x29d8d50/d; +L_0x29d8e60/d .functor AND 1, L_0x29d8850, L_0x29d9180, C4<1>, C4<1>; +L_0x29d8e60 .delay (20000,20000,20000) L_0x29d8e60/d; +L_0x29d8fb0/d .functor OR 1, L_0x29d8d50, L_0x29d8e60, C4<0>, C4<0>; +L_0x29d8fb0 .delay (20000,20000,20000) L_0x29d8fb0/d; +v0x28dd660_0 .net "S", 0 0, L_0x29d9180; 1 drivers +v0x28dd6e0_0 .alias "in0", 0 0, v0x28ddb80_0; +v0x28dd780_0 .alias "in1", 0 0, v0x28ddc00_0; +v0x28dd820_0 .net "nS", 0 0, L_0x29d8c90; 1 drivers +v0x28dd8a0_0 .net "out0", 0 0, L_0x29d8d50; 1 drivers +v0x28dd940_0 .net "out1", 0 0, L_0x29d8e60; 1 drivers +v0x28dda20_0 .alias "outfinal", 0 0, v0x28ddcb0_0; +S_0x28dc750 .scope generate, "andbits[6]" "andbits[6]" 3 231, 3 231, S_0x28ca040; + .timescale -9 -12; +P_0x28dc848 .param/l "i" 3 231, +C4<0110>; +S_0x28dc8c0 .scope module, "attempt" "AndNand" 3 233, 3 149, S_0x28dc750; + .timescale -9 -12; +L_0x29d9560/d .functor NAND 1, L_0x29d9e20, L_0x29d9ec0, C4<1>, C4<1>; +L_0x29d9560 .delay (10000,10000,10000) L_0x29d9560/d; +L_0x29d96c0/d .functor NOT 1, L_0x29d9560, C4<0>, C4<0>, C4<0>; +L_0x29d96c0 .delay (10000,10000,10000) L_0x29d96c0/d; +v0x28dcf00_0 .net "A", 0 0, L_0x29d9e20; 1 drivers +v0x28dcfc0_0 .net "AandB", 0 0, L_0x29d96c0; 1 drivers +v0x28dd040_0 .net "AnandB", 0 0, L_0x29d9560; 1 drivers +v0x28dd0f0_0 .net "AndNandOut", 0 0, L_0x29d9b10; 1 drivers +v0x28dd1d0_0 .net "B", 0 0, L_0x29d9ec0; 1 drivers +v0x28dd250_0 .alias "Command", 2 0, v0x295f7a0_0; +L_0x29d9ce0 .part v0x2960210_0, 0, 1; +S_0x28dc9b0 .scope module, "potato" "TwoInMux" 3 161, 3 109, S_0x28dc8c0; + .timescale -9 -12; +L_0x29d97f0/d .functor NOT 1, L_0x29d9ce0, C4<0>, C4<0>, C4<0>; +L_0x29d97f0 .delay (10000,10000,10000) L_0x29d97f0/d; +L_0x29d98b0/d .functor AND 1, L_0x29d96c0, L_0x29d97f0, C4<1>, C4<1>; +L_0x29d98b0 .delay (20000,20000,20000) L_0x29d98b0/d; +L_0x29d99c0/d .functor AND 1, L_0x29d9560, L_0x29d9ce0, C4<1>, C4<1>; +L_0x29d99c0 .delay (20000,20000,20000) L_0x29d99c0/d; +L_0x29d9b10/d .functor OR 1, L_0x29d98b0, L_0x29d99c0, C4<0>, C4<0>; +L_0x29d9b10 .delay (20000,20000,20000) L_0x29d9b10/d; +v0x28dcaa0_0 .net "S", 0 0, L_0x29d9ce0; 1 drivers +v0x28dcb20_0 .alias "in0", 0 0, v0x28dcfc0_0; +v0x28dcbc0_0 .alias "in1", 0 0, v0x28dd040_0; +v0x28dcc60_0 .net "nS", 0 0, L_0x29d97f0; 1 drivers +v0x28dcce0_0 .net "out0", 0 0, L_0x29d98b0; 1 drivers +v0x28dcd80_0 .net "out1", 0 0, L_0x29d99c0; 1 drivers +v0x28dce60_0 .alias "outfinal", 0 0, v0x28dd0f0_0; +S_0x28dbb90 .scope generate, "andbits[7]" "andbits[7]" 3 231, 3 231, S_0x28ca040; + .timescale -9 -12; +P_0x28dbc88 .param/l "i" 3 231, +C4<0111>; +S_0x28dbd00 .scope module, "attempt" "AndNand" 3 233, 3 149, S_0x28dbb90; + .timescale -9 -12; +L_0x29d5650/d .functor NAND 1, L_0x29da890, L_0x29d9fb0, C4<1>, C4<1>; +L_0x29d5650 .delay (10000,10000,10000) L_0x29d5650/d; +L_0x29da130/d .functor NOT 1, L_0x29d5650, C4<0>, C4<0>, C4<0>; +L_0x29da130 .delay (10000,10000,10000) L_0x29da130/d; +v0x28dc340_0 .net "A", 0 0, L_0x29da890; 1 drivers +v0x28dc400_0 .net "AandB", 0 0, L_0x29da130; 1 drivers +v0x28dc480_0 .net "AnandB", 0 0, L_0x29d5650; 1 drivers +v0x28dc530_0 .net "AndNandOut", 0 0, L_0x29da580; 1 drivers +v0x28dc610_0 .net "B", 0 0, L_0x29d9fb0; 1 drivers +v0x28dc690_0 .alias "Command", 2 0, v0x295f7a0_0; +L_0x29da750 .part v0x2960210_0, 0, 1; +S_0x28dbdf0 .scope module, "potato" "TwoInMux" 3 161, 3 109, S_0x28dbd00; + .timescale -9 -12; +L_0x29da260/d .functor NOT 1, L_0x29da750, C4<0>, C4<0>, C4<0>; +L_0x29da260 .delay (10000,10000,10000) L_0x29da260/d; +L_0x29da320/d .functor AND 1, L_0x29da130, L_0x29da260, C4<1>, C4<1>; +L_0x29da320 .delay (20000,20000,20000) L_0x29da320/d; +L_0x29da430/d .functor AND 1, L_0x29d5650, L_0x29da750, C4<1>, C4<1>; +L_0x29da430 .delay (20000,20000,20000) L_0x29da430/d; +L_0x29da580/d .functor OR 1, L_0x29da320, L_0x29da430, C4<0>, C4<0>; +L_0x29da580 .delay (20000,20000,20000) L_0x29da580/d; +v0x28dbee0_0 .net "S", 0 0, L_0x29da750; 1 drivers +v0x28dbf60_0 .alias "in0", 0 0, v0x28dc400_0; +v0x28dc000_0 .alias "in1", 0 0, v0x28dc480_0; +v0x28dc0a0_0 .net "nS", 0 0, L_0x29da260; 1 drivers +v0x28dc120_0 .net "out0", 0 0, L_0x29da320; 1 drivers +v0x28dc1c0_0 .net "out1", 0 0, L_0x29da430; 1 drivers +v0x28dc2a0_0 .alias "outfinal", 0 0, v0x28dc530_0; +S_0x28dafd0 .scope generate, "andbits[8]" "andbits[8]" 3 231, 3 231, S_0x28ca040; + .timescale -9 -12; +P_0x28db0c8 .param/l "i" 3 231, +C4<01000>; +S_0x28db140 .scope module, "attempt" "AndNand" 3 233, 3 149, S_0x28dafd0; + .timescale -9 -12; +L_0x29daa30/d .functor NAND 1, L_0x29da930, L_0x29db3b0, C4<1>, C4<1>; +L_0x29daa30 .delay (10000,10000,10000) L_0x29daa30/d; +L_0x29dab90/d .functor NOT 1, L_0x29daa30, C4<0>, C4<0>, C4<0>; +L_0x29dab90 .delay (10000,10000,10000) L_0x29dab90/d; +v0x28db780_0 .net "A", 0 0, L_0x29da930; 1 drivers +v0x28db840_0 .net "AandB", 0 0, L_0x29dab90; 1 drivers +v0x28db8c0_0 .net "AnandB", 0 0, L_0x29daa30; 1 drivers +v0x28db970_0 .net "AndNandOut", 0 0, L_0x29dafe0; 1 drivers +v0x28dba50_0 .net "B", 0 0, L_0x29db3b0; 1 drivers +v0x28dbad0_0 .alias "Command", 2 0, v0x295f7a0_0; +L_0x29db1b0 .part v0x2960210_0, 0, 1; +S_0x28db230 .scope module, "potato" "TwoInMux" 3 161, 3 109, S_0x28db140; + .timescale -9 -12; +L_0x29dacc0/d .functor NOT 1, L_0x29db1b0, C4<0>, C4<0>, C4<0>; +L_0x29dacc0 .delay (10000,10000,10000) L_0x29dacc0/d; +L_0x29dad80/d .functor AND 1, L_0x29dab90, L_0x29dacc0, C4<1>, C4<1>; +L_0x29dad80 .delay (20000,20000,20000) L_0x29dad80/d; +L_0x29dae90/d .functor AND 1, L_0x29daa30, L_0x29db1b0, C4<1>, C4<1>; +L_0x29dae90 .delay (20000,20000,20000) L_0x29dae90/d; +L_0x29dafe0/d .functor OR 1, L_0x29dad80, L_0x29dae90, C4<0>, C4<0>; +L_0x29dafe0 .delay (20000,20000,20000) L_0x29dafe0/d; +v0x28db320_0 .net "S", 0 0, L_0x29db1b0; 1 drivers +v0x28db3a0_0 .alias "in0", 0 0, v0x28db840_0; +v0x28db440_0 .alias "in1", 0 0, v0x28db8c0_0; +v0x28db4e0_0 .net "nS", 0 0, L_0x29dacc0; 1 drivers +v0x28db560_0 .net "out0", 0 0, L_0x29dad80; 1 drivers +v0x28db600_0 .net "out1", 0 0, L_0x29dae90; 1 drivers +v0x28db6e0_0 .alias "outfinal", 0 0, v0x28db970_0; +S_0x28da410 .scope generate, "andbits[9]" "andbits[9]" 3 231, 3 231, S_0x28ca040; + .timescale -9 -12; +P_0x28da508 .param/l "i" 3 231, +C4<01001>; +S_0x28da580 .scope module, "attempt" "AndNand" 3 233, 3 149, S_0x28da410; + .timescale -9 -12; +L_0x29db2f0/d .functor NAND 1, L_0x29dbd70, L_0x29db4a0, C4<1>, C4<1>; +L_0x29db2f0 .delay (10000,10000,10000) L_0x29db2f0/d; +L_0x29db610/d .functor NOT 1, L_0x29db2f0, C4<0>, C4<0>, C4<0>; +L_0x29db610 .delay (10000,10000,10000) L_0x29db610/d; +v0x28dabc0_0 .net "A", 0 0, L_0x29dbd70; 1 drivers +v0x28dac80_0 .net "AandB", 0 0, L_0x29db610; 1 drivers +v0x28dad00_0 .net "AnandB", 0 0, L_0x29db2f0; 1 drivers +v0x28dadb0_0 .net "AndNandOut", 0 0, L_0x29dba60; 1 drivers +v0x28dae90_0 .net "B", 0 0, L_0x29db4a0; 1 drivers +v0x28daf10_0 .alias "Command", 2 0, v0x295f7a0_0; +L_0x29dbc30 .part v0x2960210_0, 0, 1; +S_0x28da670 .scope module, "potato" "TwoInMux" 3 161, 3 109, S_0x28da580; + .timescale -9 -12; +L_0x29db740/d .functor NOT 1, L_0x29dbc30, C4<0>, C4<0>, C4<0>; +L_0x29db740 .delay (10000,10000,10000) L_0x29db740/d; +L_0x29db800/d .functor AND 1, L_0x29db610, L_0x29db740, C4<1>, C4<1>; +L_0x29db800 .delay (20000,20000,20000) L_0x29db800/d; +L_0x29db910/d .functor AND 1, L_0x29db2f0, L_0x29dbc30, C4<1>, C4<1>; +L_0x29db910 .delay (20000,20000,20000) L_0x29db910/d; +L_0x29dba60/d .functor OR 1, L_0x29db800, L_0x29db910, C4<0>, C4<0>; +L_0x29dba60 .delay (20000,20000,20000) L_0x29dba60/d; +v0x28da760_0 .net "S", 0 0, L_0x29dbc30; 1 drivers +v0x28da7e0_0 .alias "in0", 0 0, v0x28dac80_0; +v0x28da880_0 .alias "in1", 0 0, v0x28dad00_0; +v0x28da920_0 .net "nS", 0 0, L_0x29db740; 1 drivers +v0x28da9a0_0 .net "out0", 0 0, L_0x29db800; 1 drivers +v0x28daa40_0 .net "out1", 0 0, L_0x29db910; 1 drivers +v0x28dab20_0 .alias "outfinal", 0 0, v0x28dadb0_0; +S_0x28d9850 .scope generate, "andbits[10]" "andbits[10]" 3 231, 3 231, S_0x28ca040; + .timescale -9 -12; +P_0x28d9948 .param/l "i" 3 231, +C4<01010>; +S_0x28d99c0 .scope module, "attempt" "AndNand" 3 233, 3 149, S_0x28d9850; + .timescale -9 -12; +L_0x29dbf40/d .functor NAND 1, L_0x29dbe10, L_0x29dc8d0, C4<1>, C4<1>; +L_0x29dbf40 .delay (10000,10000,10000) L_0x29dbf40/d; +L_0x29dc080/d .functor NOT 1, L_0x29dbf40, C4<0>, C4<0>, C4<0>; +L_0x29dc080 .delay (10000,10000,10000) L_0x29dc080/d; +v0x28da000_0 .net "A", 0 0, L_0x29dbe10; 1 drivers +v0x28da0c0_0 .net "AandB", 0 0, L_0x29dc080; 1 drivers +v0x28da140_0 .net "AnandB", 0 0, L_0x29dbf40; 1 drivers +v0x28da1f0_0 .net "AndNandOut", 0 0, L_0x29dc4d0; 1 drivers +v0x28da2d0_0 .net "B", 0 0, L_0x29dc8d0; 1 drivers +v0x28da350_0 .alias "Command", 2 0, v0x295f7a0_0; +L_0x29dc6a0 .part v0x2960210_0, 0, 1; +S_0x28d9ab0 .scope module, "potato" "TwoInMux" 3 161, 3 109, S_0x28d99c0; + .timescale -9 -12; +L_0x29dc1b0/d .functor NOT 1, L_0x29dc6a0, C4<0>, C4<0>, C4<0>; +L_0x29dc1b0 .delay (10000,10000,10000) L_0x29dc1b0/d; +L_0x29dc270/d .functor AND 1, L_0x29dc080, L_0x29dc1b0, C4<1>, C4<1>; +L_0x29dc270 .delay (20000,20000,20000) L_0x29dc270/d; +L_0x29dc380/d .functor AND 1, L_0x29dbf40, L_0x29dc6a0, C4<1>, C4<1>; +L_0x29dc380 .delay (20000,20000,20000) L_0x29dc380/d; +L_0x29dc4d0/d .functor OR 1, L_0x29dc270, L_0x29dc380, C4<0>, C4<0>; +L_0x29dc4d0 .delay (20000,20000,20000) L_0x29dc4d0/d; +v0x28d9ba0_0 .net "S", 0 0, L_0x29dc6a0; 1 drivers +v0x28d9c20_0 .alias "in0", 0 0, v0x28da0c0_0; +v0x28d9cc0_0 .alias "in1", 0 0, v0x28da140_0; +v0x28d9d60_0 .net "nS", 0 0, L_0x29dc1b0; 1 drivers +v0x28d9de0_0 .net "out0", 0 0, L_0x29dc270; 1 drivers +v0x28d9e80_0 .net "out1", 0 0, L_0x29dc380; 1 drivers +v0x28d9f60_0 .alias "outfinal", 0 0, v0x28da1f0_0; +S_0x28d8c90 .scope generate, "andbits[11]" "andbits[11]" 3 231, 3 231, S_0x28ca040; + .timescale -9 -12; +P_0x28d8d88 .param/l "i" 3 231, +C4<01011>; +S_0x28d8e00 .scope module, "attempt" "AndNand" 3 233, 3 149, S_0x28d8c90; + .timescale -9 -12; +L_0x29dc7e0/d .functor NAND 1, L_0x29dd250, L_0x29dc9c0, C4<1>, C4<1>; +L_0x29dc7e0 .delay (10000,10000,10000) L_0x29dc7e0/d; +L_0x29dcb10/d .functor NOT 1, L_0x29dc7e0, C4<0>, C4<0>, C4<0>; +L_0x29dcb10 .delay (10000,10000,10000) L_0x29dcb10/d; +v0x28d9440_0 .net "A", 0 0, L_0x29dd250; 1 drivers +v0x28d9500_0 .net "AandB", 0 0, L_0x29dcb10; 1 drivers +v0x28d9580_0 .net "AnandB", 0 0, L_0x29dc7e0; 1 drivers +v0x28d9630_0 .net "AndNandOut", 0 0, L_0x29dcf40; 1 drivers +v0x28d9710_0 .net "B", 0 0, L_0x29dc9c0; 1 drivers +v0x28d9790_0 .alias "Command", 2 0, v0x295f7a0_0; +L_0x29dd110 .part v0x2960210_0, 0, 1; +S_0x28d8ef0 .scope module, "potato" "TwoInMux" 3 161, 3 109, S_0x28d8e00; + .timescale -9 -12; +L_0x29dcc20/d .functor NOT 1, L_0x29dd110, C4<0>, C4<0>, C4<0>; +L_0x29dcc20 .delay (10000,10000,10000) L_0x29dcc20/d; +L_0x29dcce0/d .functor AND 1, L_0x29dcb10, L_0x29dcc20, C4<1>, C4<1>; +L_0x29dcce0 .delay (20000,20000,20000) L_0x29dcce0/d; +L_0x29dcdf0/d .functor AND 1, L_0x29dc7e0, L_0x29dd110, C4<1>, C4<1>; +L_0x29dcdf0 .delay (20000,20000,20000) L_0x29dcdf0/d; +L_0x29dcf40/d .functor OR 1, L_0x29dcce0, L_0x29dcdf0, C4<0>, C4<0>; +L_0x29dcf40 .delay (20000,20000,20000) L_0x29dcf40/d; +v0x28d8fe0_0 .net "S", 0 0, L_0x29dd110; 1 drivers +v0x28d9060_0 .alias "in0", 0 0, v0x28d9500_0; +v0x28d9100_0 .alias "in1", 0 0, v0x28d9580_0; +v0x28d91a0_0 .net "nS", 0 0, L_0x29dcc20; 1 drivers +v0x28d9220_0 .net "out0", 0 0, L_0x29dcce0; 1 drivers +v0x28d92c0_0 .net "out1", 0 0, L_0x29dcdf0; 1 drivers +v0x28d93a0_0 .alias "outfinal", 0 0, v0x28d9630_0; +S_0x28d80d0 .scope generate, "andbits[12]" "andbits[12]" 3 231, 3 231, S_0x28ca040; + .timescale -9 -12; +P_0x28d81c8 .param/l "i" 3 231, +C4<01100>; +S_0x28d8240 .scope module, "attempt" "AndNand" 3 233, 3 149, S_0x28d80d0; + .timescale -9 -12; +L_0x29dd400/d .functor NAND 1, L_0x29dd2f0, L_0x29ddde0, C4<1>, C4<1>; +L_0x29dd400 .delay (10000,10000,10000) L_0x29dd400/d; +L_0x29dd560/d .functor NOT 1, L_0x29dd400, C4<0>, C4<0>, C4<0>; +L_0x29dd560 .delay (10000,10000,10000) L_0x29dd560/d; +v0x28d8880_0 .net "A", 0 0, L_0x29dd2f0; 1 drivers +v0x28d8940_0 .net "AandB", 0 0, L_0x29dd560; 1 drivers +v0x28d89c0_0 .net "AnandB", 0 0, L_0x29dd400; 1 drivers +v0x28d8a70_0 .net "AndNandOut", 0 0, L_0x29dd9b0; 1 drivers +v0x28d8b50_0 .net "B", 0 0, L_0x29ddde0; 1 drivers +v0x28d8bd0_0 .alias "Command", 2 0, v0x295f7a0_0; +L_0x29ddb80 .part v0x2960210_0, 0, 1; +S_0x28d8330 .scope module, "potato" "TwoInMux" 3 161, 3 109, S_0x28d8240; + .timescale -9 -12; +L_0x29dd690/d .functor NOT 1, L_0x29ddb80, C4<0>, C4<0>, C4<0>; +L_0x29dd690 .delay (10000,10000,10000) L_0x29dd690/d; +L_0x29dd750/d .functor AND 1, L_0x29dd560, L_0x29dd690, C4<1>, C4<1>; +L_0x29dd750 .delay (20000,20000,20000) L_0x29dd750/d; +L_0x29dd860/d .functor AND 1, L_0x29dd400, L_0x29ddb80, C4<1>, C4<1>; +L_0x29dd860 .delay (20000,20000,20000) L_0x29dd860/d; +L_0x29dd9b0/d .functor OR 1, L_0x29dd750, L_0x29dd860, C4<0>, C4<0>; +L_0x29dd9b0 .delay (20000,20000,20000) L_0x29dd9b0/d; +v0x28d8420_0 .net "S", 0 0, L_0x29ddb80; 1 drivers +v0x28d84a0_0 .alias "in0", 0 0, v0x28d8940_0; +v0x28d8540_0 .alias "in1", 0 0, v0x28d89c0_0; +v0x28d85e0_0 .net "nS", 0 0, L_0x29dd690; 1 drivers +v0x28d8660_0 .net "out0", 0 0, L_0x29dd750; 1 drivers +v0x28d8700_0 .net "out1", 0 0, L_0x29dd860; 1 drivers +v0x28d87e0_0 .alias "outfinal", 0 0, v0x28d8a70_0; +S_0x28d7510 .scope generate, "andbits[13]" "andbits[13]" 3 231, 3 231, S_0x28ca040; + .timescale -9 -12; +P_0x28d7608 .param/l "i" 3 231, +C4<01101>; +S_0x28d7680 .scope module, "attempt" "AndNand" 3 233, 3 149, S_0x28d7510; + .timescale -9 -12; +L_0x29ddcc0/d .functor NAND 1, L_0x29d92c0, L_0x29dde80, C4<1>, C4<1>; +L_0x29ddcc0 .delay (10000,10000,10000) L_0x29ddcc0/d; +L_0x29de000/d .functor NOT 1, L_0x29ddcc0, C4<0>, C4<0>, C4<0>; +L_0x29de000 .delay (10000,10000,10000) L_0x29de000/d; +v0x28d7cc0_0 .net "A", 0 0, L_0x29d92c0; 1 drivers +v0x28d7d80_0 .net "AandB", 0 0, L_0x29de000; 1 drivers +v0x28d7e00_0 .net "AnandB", 0 0, L_0x29ddcc0; 1 drivers +v0x28d7eb0_0 .net "AndNandOut", 0 0, L_0x29de430; 1 drivers +v0x28d7f90_0 .net "B", 0 0, L_0x29dde80; 1 drivers +v0x28d8010_0 .alias "Command", 2 0, v0x295f7a0_0; +L_0x29de600 .part v0x2960210_0, 0, 1; +S_0x28d7770 .scope module, "potato" "TwoInMux" 3 161, 3 109, S_0x28d7680; + .timescale -9 -12; +L_0x29de110/d .functor NOT 1, L_0x29de600, C4<0>, C4<0>, C4<0>; +L_0x29de110 .delay (10000,10000,10000) L_0x29de110/d; +L_0x29de1d0/d .functor AND 1, L_0x29de000, L_0x29de110, C4<1>, C4<1>; +L_0x29de1d0 .delay (20000,20000,20000) L_0x29de1d0/d; +L_0x29de2e0/d .functor AND 1, L_0x29ddcc0, L_0x29de600, C4<1>, C4<1>; +L_0x29de2e0 .delay (20000,20000,20000) L_0x29de2e0/d; +L_0x29de430/d .functor OR 1, L_0x29de1d0, L_0x29de2e0, C4<0>, C4<0>; +L_0x29de430 .delay (20000,20000,20000) L_0x29de430/d; +v0x28d7860_0 .net "S", 0 0, L_0x29de600; 1 drivers +v0x28d78e0_0 .alias "in0", 0 0, v0x28d7d80_0; +v0x28d7980_0 .alias "in1", 0 0, v0x28d7e00_0; +v0x28d7a20_0 .net "nS", 0 0, L_0x29de110; 1 drivers +v0x28d7aa0_0 .net "out0", 0 0, L_0x29de1d0; 1 drivers +v0x28d7b40_0 .net "out1", 0 0, L_0x29de2e0; 1 drivers +v0x28d7c20_0 .alias "outfinal", 0 0, v0x28d7eb0_0; +S_0x28d6950 .scope generate, "andbits[14]" "andbits[14]" 3 231, 3 231, S_0x28ca040; + .timescale -9 -12; +P_0x28d6a48 .param/l "i" 3 231, +C4<01110>; +S_0x28d6ac0 .scope module, "attempt" "AndNand" 3 233, 3 149, S_0x28d6950; + .timescale -9 -12; +L_0x29d9360/d .functor NAND 1, L_0x29de950, L_0x29de9f0, C4<1>, C4<1>; +L_0x29d9360 .delay (10000,10000,10000) L_0x29d9360/d; +L_0x29deb70/d .functor NOT 1, L_0x29d9360, C4<0>, C4<0>, C4<0>; +L_0x29deb70 .delay (10000,10000,10000) L_0x29deb70/d; +v0x28d7100_0 .net "A", 0 0, L_0x29de950; 1 drivers +v0x28d71c0_0 .net "AandB", 0 0, L_0x29deb70; 1 drivers +v0x28d7240_0 .net "AnandB", 0 0, L_0x29d9360; 1 drivers +v0x28d72f0_0 .net "AndNandOut", 0 0, L_0x29defa0; 1 drivers +v0x28d73d0_0 .net "B", 0 0, L_0x29de9f0; 1 drivers +v0x28d7450_0 .alias "Command", 2 0, v0x295f7a0_0; +L_0x29df170 .part v0x2960210_0, 0, 1; +S_0x28d6bb0 .scope module, "potato" "TwoInMux" 3 161, 3 109, S_0x28d6ac0; + .timescale -9 -12; +L_0x29dec80/d .functor NOT 1, L_0x29df170, C4<0>, C4<0>, C4<0>; +L_0x29dec80 .delay (10000,10000,10000) L_0x29dec80/d; +L_0x29ded40/d .functor AND 1, L_0x29deb70, L_0x29dec80, C4<1>, C4<1>; +L_0x29ded40 .delay (20000,20000,20000) L_0x29ded40/d; +L_0x29dee50/d .functor AND 1, L_0x29d9360, L_0x29df170, C4<1>, C4<1>; +L_0x29dee50 .delay (20000,20000,20000) L_0x29dee50/d; +L_0x29defa0/d .functor OR 1, L_0x29ded40, L_0x29dee50, C4<0>, C4<0>; +L_0x29defa0 .delay (20000,20000,20000) L_0x29defa0/d; +v0x28d6ca0_0 .net "S", 0 0, L_0x29df170; 1 drivers +v0x28d6d20_0 .alias "in0", 0 0, v0x28d71c0_0; +v0x28d6dc0_0 .alias "in1", 0 0, v0x28d7240_0; +v0x28d6e60_0 .net "nS", 0 0, L_0x29dec80; 1 drivers +v0x28d6ee0_0 .net "out0", 0 0, L_0x29ded40; 1 drivers +v0x28d6f80_0 .net "out1", 0 0, L_0x29dee50; 1 drivers +v0x28d7060_0 .alias "outfinal", 0 0, v0x28d72f0_0; +S_0x28d5d90 .scope generate, "andbits[15]" "andbits[15]" 3 231, 3 231, S_0x28ca040; + .timescale -9 -12; +P_0x28d5e88 .param/l "i" 3 231, +C4<01111>; +S_0x28d5f00 .scope module, "attempt" "AndNand" 3 233, 3 149, S_0x28d5d90; + .timescale -9 -12; +L_0x29df2b0/d .functor NAND 1, L_0x29dfd20, L_0x29df450, C4<1>, C4<1>; +L_0x29df2b0 .delay (10000,10000,10000) L_0x29df2b0/d; +L_0x29df600/d .functor NOT 1, L_0x29df2b0, C4<0>, C4<0>, C4<0>; +L_0x29df600 .delay (10000,10000,10000) L_0x29df600/d; +v0x28d6540_0 .net "A", 0 0, L_0x29dfd20; 1 drivers +v0x28d6600_0 .net "AandB", 0 0, L_0x29df600; 1 drivers +v0x28d6680_0 .net "AnandB", 0 0, L_0x29df2b0; 1 drivers +v0x28d6730_0 .net "AndNandOut", 0 0, L_0x29dfa10; 1 drivers +v0x28d6810_0 .net "B", 0 0, L_0x29df450; 1 drivers +v0x28d6890_0 .alias "Command", 2 0, v0x295f7a0_0; +L_0x29dfbe0 .part v0x2960210_0, 0, 1; +S_0x28d5ff0 .scope module, "potato" "TwoInMux" 3 161, 3 109, S_0x28d5f00; + .timescale -9 -12; +L_0x29df6f0/d .functor NOT 1, L_0x29dfbe0, C4<0>, C4<0>, C4<0>; +L_0x29df6f0 .delay (10000,10000,10000) L_0x29df6f0/d; +L_0x29df7b0/d .functor AND 1, L_0x29df600, L_0x29df6f0, C4<1>, C4<1>; +L_0x29df7b0 .delay (20000,20000,20000) L_0x29df7b0/d; +L_0x29df8c0/d .functor AND 1, L_0x29df2b0, L_0x29dfbe0, C4<1>, C4<1>; +L_0x29df8c0 .delay (20000,20000,20000) L_0x29df8c0/d; +L_0x29dfa10/d .functor OR 1, L_0x29df7b0, L_0x29df8c0, C4<0>, C4<0>; +L_0x29dfa10 .delay (20000,20000,20000) L_0x29dfa10/d; +v0x28d60e0_0 .net "S", 0 0, L_0x29dfbe0; 1 drivers +v0x28d6160_0 .alias "in0", 0 0, v0x28d6600_0; +v0x28d6200_0 .alias "in1", 0 0, v0x28d6680_0; +v0x28d62a0_0 .net "nS", 0 0, L_0x29df6f0; 1 drivers +v0x28d6320_0 .net "out0", 0 0, L_0x29df7b0; 1 drivers +v0x28d63c0_0 .net "out1", 0 0, L_0x29df8c0; 1 drivers +v0x28d64a0_0 .alias "outfinal", 0 0, v0x28d6730_0; +S_0x28d51d0 .scope generate, "andbits[16]" "andbits[16]" 3 231, 3 231, S_0x28ca040; + .timescale -9 -12; +P_0x28d52c8 .param/l "i" 3 231, +C4<010000>; +S_0x28d5340 .scope module, "attempt" "AndNand" 3 233, 3 149, S_0x28d51d0; + .timescale -9 -12; +L_0x29df540/d .functor NAND 1, L_0x29dfdc0, L_0x29dfe60, C4<1>, C4<1>; +L_0x29df540 .delay (10000,10000,10000) L_0x29df540/d; +L_0x29e0030/d .functor NOT 1, L_0x29df540, C4<0>, C4<0>, C4<0>; +L_0x29e0030 .delay (10000,10000,10000) L_0x29e0030/d; +v0x28d5980_0 .net "A", 0 0, L_0x29dfdc0; 1 drivers +v0x28d5a40_0 .net "AandB", 0 0, L_0x29e0030; 1 drivers +v0x28d5ac0_0 .net "AnandB", 0 0, L_0x29df540; 1 drivers +v0x28d5b70_0 .net "AndNandOut", 0 0, L_0x29e0480; 1 drivers +v0x28d5c50_0 .net "B", 0 0, L_0x29dfe60; 1 drivers +v0x28d5cd0_0 .alias "Command", 2 0, v0x295f7a0_0; +L_0x29e0650 .part v0x2960210_0, 0, 1; +S_0x28d5430 .scope module, "potato" "TwoInMux" 3 161, 3 109, S_0x28d5340; + .timescale -9 -12; +L_0x29e0160/d .functor NOT 1, L_0x29e0650, C4<0>, C4<0>, C4<0>; +L_0x29e0160 .delay (10000,10000,10000) L_0x29e0160/d; +L_0x29e0220/d .functor AND 1, L_0x29e0030, L_0x29e0160, C4<1>, C4<1>; +L_0x29e0220 .delay (20000,20000,20000) L_0x29e0220/d; +L_0x29e0330/d .functor AND 1, L_0x29df540, L_0x29e0650, C4<1>, C4<1>; +L_0x29e0330 .delay (20000,20000,20000) L_0x29e0330/d; +L_0x29e0480/d .functor OR 1, L_0x29e0220, L_0x29e0330, C4<0>, C4<0>; +L_0x29e0480 .delay (20000,20000,20000) L_0x29e0480/d; +v0x28d5520_0 .net "S", 0 0, L_0x29e0650; 1 drivers +v0x28d55a0_0 .alias "in0", 0 0, v0x28d5a40_0; +v0x28d5640_0 .alias "in1", 0 0, v0x28d5ac0_0; +v0x28d56e0_0 .net "nS", 0 0, L_0x29e0160; 1 drivers +v0x28d5760_0 .net "out0", 0 0, L_0x29e0220; 1 drivers +v0x28d5800_0 .net "out1", 0 0, L_0x29e0330; 1 drivers +v0x28d58e0_0 .alias "outfinal", 0 0, v0x28d5b70_0; +S_0x28d4610 .scope generate, "andbits[17]" "andbits[17]" 3 231, 3 231, S_0x28ca040; + .timescale -9 -12; +P_0x28d4708 .param/l "i" 3 231, +C4<010001>; +S_0x28d4780 .scope module, "attempt" "AndNand" 3 233, 3 149, S_0x28d4610; + .timescale -9 -12; +L_0x29e0790/d .functor NAND 1, L_0x29e1210, L_0x29e0960, C4<1>, C4<1>; +L_0x29e0790 .delay (10000,10000,10000) L_0x29e0790/d; +L_0x29e0af0/d .functor NOT 1, L_0x29e0790, C4<0>, C4<0>, C4<0>; +L_0x29e0af0 .delay (10000,10000,10000) L_0x29e0af0/d; +v0x28d4dc0_0 .net "A", 0 0, L_0x29e1210; 1 drivers +v0x28d4e80_0 .net "AandB", 0 0, L_0x29e0af0; 1 drivers +v0x28d4f00_0 .net "AnandB", 0 0, L_0x29e0790; 1 drivers +v0x28d4fb0_0 .net "AndNandOut", 0 0, L_0x29e0f00; 1 drivers +v0x28d5090_0 .net "B", 0 0, L_0x29e0960; 1 drivers +v0x28d5110_0 .alias "Command", 2 0, v0x295f7a0_0; +L_0x29e10d0 .part v0x2960210_0, 0, 1; +S_0x28d4870 .scope module, "potato" "TwoInMux" 3 161, 3 109, S_0x28d4780; + .timescale -9 -12; +L_0x29e0be0/d .functor NOT 1, L_0x29e10d0, C4<0>, C4<0>, C4<0>; +L_0x29e0be0 .delay (10000,10000,10000) L_0x29e0be0/d; +L_0x29e0ca0/d .functor AND 1, L_0x29e0af0, L_0x29e0be0, C4<1>, C4<1>; +L_0x29e0ca0 .delay (20000,20000,20000) L_0x29e0ca0/d; +L_0x29e0db0/d .functor AND 1, L_0x29e0790, L_0x29e10d0, C4<1>, C4<1>; +L_0x29e0db0 .delay (20000,20000,20000) L_0x29e0db0/d; +L_0x29e0f00/d .functor OR 1, L_0x29e0ca0, L_0x29e0db0, C4<0>, C4<0>; +L_0x29e0f00 .delay (20000,20000,20000) L_0x29e0f00/d; +v0x28d4960_0 .net "S", 0 0, L_0x29e10d0; 1 drivers +v0x28d49e0_0 .alias "in0", 0 0, v0x28d4e80_0; +v0x28d4a80_0 .alias "in1", 0 0, v0x28d4f00_0; +v0x28d4b20_0 .net "nS", 0 0, L_0x29e0be0; 1 drivers +v0x28d4ba0_0 .net "out0", 0 0, L_0x29e0ca0; 1 drivers +v0x28d4c40_0 .net "out1", 0 0, L_0x29e0db0; 1 drivers +v0x28d4d20_0 .alias "outfinal", 0 0, v0x28d4fb0_0; +S_0x28d3a50 .scope generate, "andbits[18]" "andbits[18]" 3 231, 3 231, S_0x28ca040; + .timescale -9 -12; +P_0x28d3b48 .param/l "i" 3 231, +C4<010010>; +S_0x28d3bc0 .scope module, "attempt" "AndNand" 3 233, 3 149, S_0x28d3a50; + .timescale -9 -12; +L_0x29e0a50/d .functor NAND 1, L_0x29e12b0, L_0x29e1350, C4<1>, C4<1>; +L_0x29e0a50 .delay (10000,10000,10000) L_0x29e0a50/d; +L_0x29e1530/d .functor NOT 1, L_0x29e0a50, C4<0>, C4<0>, C4<0>; +L_0x29e1530 .delay (10000,10000,10000) L_0x29e1530/d; +v0x28d4200_0 .net "A", 0 0, L_0x29e12b0; 1 drivers +v0x28d42c0_0 .net "AandB", 0 0, L_0x29e1530; 1 drivers +v0x28d4340_0 .net "AnandB", 0 0, L_0x29e0a50; 1 drivers +v0x28d43f0_0 .net "AndNandOut", 0 0, L_0x29e1960; 1 drivers +v0x28d44d0_0 .net "B", 0 0, L_0x29e1350; 1 drivers +v0x28d4550_0 .alias "Command", 2 0, v0x295f7a0_0; +L_0x29e1b30 .part v0x2960210_0, 0, 1; +S_0x28d3cb0 .scope module, "potato" "TwoInMux" 3 161, 3 109, S_0x28d3bc0; + .timescale -9 -12; +L_0x29e1640/d .functor NOT 1, L_0x29e1b30, C4<0>, C4<0>, C4<0>; +L_0x29e1640 .delay (10000,10000,10000) L_0x29e1640/d; +L_0x29e1700/d .functor AND 1, L_0x29e1530, L_0x29e1640, C4<1>, C4<1>; +L_0x29e1700 .delay (20000,20000,20000) L_0x29e1700/d; +L_0x29e1810/d .functor AND 1, L_0x29e0a50, L_0x29e1b30, C4<1>, C4<1>; +L_0x29e1810 .delay (20000,20000,20000) L_0x29e1810/d; +L_0x29e1960/d .functor OR 1, L_0x29e1700, L_0x29e1810, C4<0>, C4<0>; +L_0x29e1960 .delay (20000,20000,20000) L_0x29e1960/d; +v0x28d3da0_0 .net "S", 0 0, L_0x29e1b30; 1 drivers +v0x28d3e20_0 .alias "in0", 0 0, v0x28d42c0_0; +v0x28d3ec0_0 .alias "in1", 0 0, v0x28d4340_0; +v0x28d3f60_0 .net "nS", 0 0, L_0x29e1640; 1 drivers +v0x28d3fe0_0 .net "out0", 0 0, L_0x29e1700; 1 drivers +v0x28d4080_0 .net "out1", 0 0, L_0x29e1810; 1 drivers +v0x28d4160_0 .alias "outfinal", 0 0, v0x28d43f0_0; +S_0x28d2e90 .scope generate, "andbits[19]" "andbits[19]" 3 231, 3 231, S_0x28ca040; + .timescale -9 -12; +P_0x28d2f88 .param/l "i" 3 231, +C4<010011>; +S_0x28d3000 .scope module, "attempt" "AndNand" 3 233, 3 149, S_0x28d2e90; + .timescale -9 -12; +L_0x29e1e30/d .functor NAND 1, L_0x29e26f0, L_0x29e1c70, C4<1>, C4<1>; +L_0x29e1e30 .delay (10000,10000,10000) L_0x29e1e30/d; +L_0x29e1f90/d .functor NOT 1, L_0x29e1e30, C4<0>, C4<0>, C4<0>; +L_0x29e1f90 .delay (10000,10000,10000) L_0x29e1f90/d; +v0x28d3640_0 .net "A", 0 0, L_0x29e26f0; 1 drivers +v0x28d3700_0 .net "AandB", 0 0, L_0x29e1f90; 1 drivers +v0x28d3780_0 .net "AnandB", 0 0, L_0x29e1e30; 1 drivers +v0x28d3830_0 .net "AndNandOut", 0 0, L_0x29e23e0; 1 drivers +v0x28d3910_0 .net "B", 0 0, L_0x29e1c70; 1 drivers +v0x28d3990_0 .alias "Command", 2 0, v0x295f7a0_0; +L_0x29e25b0 .part v0x2960210_0, 0, 1; +S_0x28d30f0 .scope module, "potato" "TwoInMux" 3 161, 3 109, S_0x28d3000; + .timescale -9 -12; +L_0x29e20c0/d .functor NOT 1, L_0x29e25b0, C4<0>, C4<0>, C4<0>; +L_0x29e20c0 .delay (10000,10000,10000) L_0x29e20c0/d; +L_0x29e2180/d .functor AND 1, L_0x29e1f90, L_0x29e20c0, C4<1>, C4<1>; +L_0x29e2180 .delay (20000,20000,20000) L_0x29e2180/d; +L_0x29e2290/d .functor AND 1, L_0x29e1e30, L_0x29e25b0, C4<1>, C4<1>; +L_0x29e2290 .delay (20000,20000,20000) L_0x29e2290/d; +L_0x29e23e0/d .functor OR 1, L_0x29e2180, L_0x29e2290, C4<0>, C4<0>; +L_0x29e23e0 .delay (20000,20000,20000) L_0x29e23e0/d; +v0x28d31e0_0 .net "S", 0 0, L_0x29e25b0; 1 drivers +v0x28d3260_0 .alias "in0", 0 0, v0x28d3700_0; +v0x28d3300_0 .alias "in1", 0 0, v0x28d3780_0; +v0x28d33a0_0 .net "nS", 0 0, L_0x29e20c0; 1 drivers +v0x28d3420_0 .net "out0", 0 0, L_0x29e2180; 1 drivers +v0x28d34c0_0 .net "out1", 0 0, L_0x29e2290; 1 drivers +v0x28d35a0_0 .alias "outfinal", 0 0, v0x28d3830_0; +S_0x28d22d0 .scope generate, "andbits[20]" "andbits[20]" 3 231, 3 231, S_0x28ca040; + .timescale -9 -12; +P_0x28d23c8 .param/l "i" 3 231, +C4<010100>; +S_0x28d2440 .scope module, "attempt" "AndNand" 3 233, 3 149, S_0x28d22d0; + .timescale -9 -12; +L_0x29e1d60/d .functor NAND 1, L_0x29e2790, L_0x29e2830, C4<1>, C4<1>; +L_0x29e1d60 .delay (10000,10000,10000) L_0x29e1d60/d; +L_0x29e29f0/d .functor NOT 1, L_0x29e1d60, C4<0>, C4<0>, C4<0>; +L_0x29e29f0 .delay (10000,10000,10000) L_0x29e29f0/d; +v0x28d2a80_0 .net "A", 0 0, L_0x29e2790; 1 drivers +v0x28d2b40_0 .net "AandB", 0 0, L_0x29e29f0; 1 drivers +v0x28d2bc0_0 .net "AnandB", 0 0, L_0x29e1d60; 1 drivers +v0x28d2c70_0 .net "AndNandOut", 0 0, L_0x29e2e40; 1 drivers +v0x28d2d50_0 .net "B", 0 0, L_0x29e2830; 1 drivers +v0x28d2dd0_0 .alias "Command", 2 0, v0x295f7a0_0; +L_0x29e3010 .part v0x2960210_0, 0, 1; +S_0x28d2530 .scope module, "potato" "TwoInMux" 3 161, 3 109, S_0x28d2440; + .timescale -9 -12; +L_0x29e2b20/d .functor NOT 1, L_0x29e3010, C4<0>, C4<0>, C4<0>; +L_0x29e2b20 .delay (10000,10000,10000) L_0x29e2b20/d; +L_0x29e2be0/d .functor AND 1, L_0x29e29f0, L_0x29e2b20, C4<1>, C4<1>; +L_0x29e2be0 .delay (20000,20000,20000) L_0x29e2be0/d; +L_0x29e2cf0/d .functor AND 1, L_0x29e1d60, L_0x29e3010, C4<1>, C4<1>; +L_0x29e2cf0 .delay (20000,20000,20000) L_0x29e2cf0/d; +L_0x29e2e40/d .functor OR 1, L_0x29e2be0, L_0x29e2cf0, C4<0>, C4<0>; +L_0x29e2e40 .delay (20000,20000,20000) L_0x29e2e40/d; +v0x28d2620_0 .net "S", 0 0, L_0x29e3010; 1 drivers +v0x28d26a0_0 .alias "in0", 0 0, v0x28d2b40_0; +v0x28d2740_0 .alias "in1", 0 0, v0x28d2bc0_0; +v0x28d27e0_0 .net "nS", 0 0, L_0x29e2b20; 1 drivers +v0x28d2860_0 .net "out0", 0 0, L_0x29e2be0; 1 drivers +v0x28d2900_0 .net "out1", 0 0, L_0x29e2cf0; 1 drivers +v0x28d29e0_0 .alias "outfinal", 0 0, v0x28d2c70_0; +S_0x28d1710 .scope generate, "andbits[21]" "andbits[21]" 3 231, 3 231, S_0x28ca040; + .timescale -9 -12; +P_0x28d1808 .param/l "i" 3 231, +C4<010101>; +S_0x28d1880 .scope module, "attempt" "AndNand" 3 233, 3 149, S_0x28d1710; + .timescale -9 -12; +L_0x29e3340/d .functor NAND 1, L_0x29e3bc0, L_0x29e3150, C4<1>, C4<1>; +L_0x29e3340 .delay (10000,10000,10000) L_0x29e3340/d; +L_0x29e3480/d .functor NOT 1, L_0x29e3340, C4<0>, C4<0>, C4<0>; +L_0x29e3480 .delay (10000,10000,10000) L_0x29e3480/d; +v0x28d1ec0_0 .net "A", 0 0, L_0x29e3bc0; 1 drivers +v0x28d1f80_0 .net "AandB", 0 0, L_0x29e3480; 1 drivers +v0x28d2000_0 .net "AnandB", 0 0, L_0x29e3340; 1 drivers +v0x28d20b0_0 .net "AndNandOut", 0 0, L_0x29e38b0; 1 drivers +v0x28d2190_0 .net "B", 0 0, L_0x29e3150; 1 drivers +v0x28d2210_0 .alias "Command", 2 0, v0x295f7a0_0; +L_0x29e3a80 .part v0x2960210_0, 0, 1; +S_0x28d1970 .scope module, "potato" "TwoInMux" 3 161, 3 109, S_0x28d1880; + .timescale -9 -12; +L_0x29e3590/d .functor NOT 1, L_0x29e3a80, C4<0>, C4<0>, C4<0>; +L_0x29e3590 .delay (10000,10000,10000) L_0x29e3590/d; +L_0x29e3650/d .functor AND 1, L_0x29e3480, L_0x29e3590, C4<1>, C4<1>; +L_0x29e3650 .delay (20000,20000,20000) L_0x29e3650/d; +L_0x29e3760/d .functor AND 1, L_0x29e3340, L_0x29e3a80, C4<1>, C4<1>; +L_0x29e3760 .delay (20000,20000,20000) L_0x29e3760/d; +L_0x29e38b0/d .functor OR 1, L_0x29e3650, L_0x29e3760, C4<0>, C4<0>; +L_0x29e38b0 .delay (20000,20000,20000) L_0x29e38b0/d; +v0x28d1a60_0 .net "S", 0 0, L_0x29e3a80; 1 drivers +v0x28d1ae0_0 .alias "in0", 0 0, v0x28d1f80_0; +v0x28d1b80_0 .alias "in1", 0 0, v0x28d2000_0; +v0x28d1c20_0 .net "nS", 0 0, L_0x29e3590; 1 drivers +v0x28d1ca0_0 .net "out0", 0 0, L_0x29e3650; 1 drivers +v0x28d1d40_0 .net "out1", 0 0, L_0x29e3760; 1 drivers +v0x28d1e20_0 .alias "outfinal", 0 0, v0x28d20b0_0; +S_0x28d0b50 .scope generate, "andbits[22]" "andbits[22]" 3 231, 3 231, S_0x28ca040; + .timescale -9 -12; +P_0x28d0c48 .param/l "i" 3 231, +C4<010110>; +S_0x28d0cc0 .scope module, "attempt" "AndNand" 3 233, 3 149, S_0x28d0b50; + .timescale -9 -12; +L_0x29e3240/d .functor NAND 1, L_0x29e3c60, L_0x29e3d00, C4<1>, C4<1>; +L_0x29e3240 .delay (10000,10000,10000) L_0x29e3240/d; +L_0x29e3ef0/d .functor NOT 1, L_0x29e3240, C4<0>, C4<0>, C4<0>; +L_0x29e3ef0 .delay (10000,10000,10000) L_0x29e3ef0/d; +v0x28d1300_0 .net "A", 0 0, L_0x29e3c60; 1 drivers +v0x28d13c0_0 .net "AandB", 0 0, L_0x29e3ef0; 1 drivers +v0x28d1440_0 .net "AnandB", 0 0, L_0x29e3240; 1 drivers +v0x28d14f0_0 .net "AndNandOut", 0 0, L_0x29e4320; 1 drivers +v0x28d15d0_0 .net "B", 0 0, L_0x29e3d00; 1 drivers +v0x28d1650_0 .alias "Command", 2 0, v0x295f7a0_0; +L_0x29e44f0 .part v0x2960210_0, 0, 1; +S_0x28d0db0 .scope module, "potato" "TwoInMux" 3 161, 3 109, S_0x28d0cc0; + .timescale -9 -12; +L_0x29e4000/d .functor NOT 1, L_0x29e44f0, C4<0>, C4<0>, C4<0>; +L_0x29e4000 .delay (10000,10000,10000) L_0x29e4000/d; +L_0x29e40c0/d .functor AND 1, L_0x29e3ef0, L_0x29e4000, C4<1>, C4<1>; +L_0x29e40c0 .delay (20000,20000,20000) L_0x29e40c0/d; +L_0x29e41d0/d .functor AND 1, L_0x29e3240, L_0x29e44f0, C4<1>, C4<1>; +L_0x29e41d0 .delay (20000,20000,20000) L_0x29e41d0/d; +L_0x29e4320/d .functor OR 1, L_0x29e40c0, L_0x29e41d0, C4<0>, C4<0>; +L_0x29e4320 .delay (20000,20000,20000) L_0x29e4320/d; +v0x28d0ea0_0 .net "S", 0 0, L_0x29e44f0; 1 drivers +v0x28d0f20_0 .alias "in0", 0 0, v0x28d13c0_0; +v0x28d0fc0_0 .alias "in1", 0 0, v0x28d1440_0; +v0x28d1060_0 .net "nS", 0 0, L_0x29e4000; 1 drivers +v0x28d10e0_0 .net "out0", 0 0, L_0x29e40c0; 1 drivers +v0x28d1180_0 .net "out1", 0 0, L_0x29e41d0; 1 drivers +v0x28d1260_0 .alias "outfinal", 0 0, v0x28d14f0_0; +S_0x28cff90 .scope generate, "andbits[23]" "andbits[23]" 3 231, 3 231, S_0x28ca040; + .timescale -9 -12; +P_0x28d0088 .param/l "i" 3 231, +C4<010111>; +S_0x28d0100 .scope module, "attempt" "AndNand" 3 233, 3 149, S_0x28cff90; + .timescale -9 -12; +L_0x29e3df0/d .functor NAND 1, L_0x29e50b0, L_0x29e4630, C4<1>, C4<1>; +L_0x29e3df0 .delay (10000,10000,10000) L_0x29e3df0/d; +L_0x29e4950/d .functor NOT 1, L_0x29e3df0, C4<0>, C4<0>, C4<0>; +L_0x29e4950 .delay (10000,10000,10000) L_0x29e4950/d; +v0x28d0740_0 .net "A", 0 0, L_0x29e50b0; 1 drivers +v0x28d0800_0 .net "AandB", 0 0, L_0x29e4950; 1 drivers +v0x28d0880_0 .net "AnandB", 0 0, L_0x29e3df0; 1 drivers +v0x28d0930_0 .net "AndNandOut", 0 0, L_0x29e4da0; 1 drivers +v0x28d0a10_0 .net "B", 0 0, L_0x29e4630; 1 drivers +v0x28d0a90_0 .alias "Command", 2 0, v0x295f7a0_0; +L_0x29e4f70 .part v0x2960210_0, 0, 1; +S_0x28d01f0 .scope module, "potato" "TwoInMux" 3 161, 3 109, S_0x28d0100; + .timescale -9 -12; +L_0x29e4a80/d .functor NOT 1, L_0x29e4f70, C4<0>, C4<0>, C4<0>; +L_0x29e4a80 .delay (10000,10000,10000) L_0x29e4a80/d; +L_0x29e4b40/d .functor AND 1, L_0x29e4950, L_0x29e4a80, C4<1>, C4<1>; +L_0x29e4b40 .delay (20000,20000,20000) L_0x29e4b40/d; +L_0x29e4c50/d .functor AND 1, L_0x29e3df0, L_0x29e4f70, C4<1>, C4<1>; +L_0x29e4c50 .delay (20000,20000,20000) L_0x29e4c50/d; +L_0x29e4da0/d .functor OR 1, L_0x29e4b40, L_0x29e4c50, C4<0>, C4<0>; +L_0x29e4da0 .delay (20000,20000,20000) L_0x29e4da0/d; +v0x28d02e0_0 .net "S", 0 0, L_0x29e4f70; 1 drivers +v0x28d0360_0 .alias "in0", 0 0, v0x28d0800_0; +v0x28d0400_0 .alias "in1", 0 0, v0x28d0880_0; +v0x28d04a0_0 .net "nS", 0 0, L_0x29e4a80; 1 drivers +v0x28d0520_0 .net "out0", 0 0, L_0x29e4b40; 1 drivers +v0x28d05c0_0 .net "out1", 0 0, L_0x29e4c50; 1 drivers +v0x28d06a0_0 .alias "outfinal", 0 0, v0x28d0930_0; +S_0x28cf3d0 .scope generate, "andbits[24]" "andbits[24]" 3 231, 3 231, S_0x28ca040; + .timescale -9 -12; +P_0x28cf4c8 .param/l "i" 3 231, +C4<011000>; +S_0x28cf540 .scope module, "attempt" "AndNand" 3 233, 3 149, S_0x28cf3d0; + .timescale -9 -12; +L_0x29e4720/d .functor NAND 1, L_0x29e5150, L_0x29e51f0, C4<1>, C4<1>; +L_0x29e4720 .delay (10000,10000,10000) L_0x29e4720/d; +L_0x29e53d0/d .functor NOT 1, L_0x29e4720, C4<0>, C4<0>, C4<0>; +L_0x29e53d0 .delay (10000,10000,10000) L_0x29e53d0/d; +v0x28cfb80_0 .net "A", 0 0, L_0x29e5150; 1 drivers +v0x28cfc40_0 .net "AandB", 0 0, L_0x29e53d0; 1 drivers +v0x28cfcc0_0 .net "AnandB", 0 0, L_0x29e4720; 1 drivers +v0x28cfd70_0 .net "AndNandOut", 0 0, L_0x29e5800; 1 drivers +v0x28cfe50_0 .net "B", 0 0, L_0x29e51f0; 1 drivers +v0x28cfed0_0 .alias "Command", 2 0, v0x295f7a0_0; +L_0x29e59d0 .part v0x2960210_0, 0, 1; +S_0x28cf630 .scope module, "potato" "TwoInMux" 3 161, 3 109, S_0x28cf540; + .timescale -9 -12; +L_0x29e54e0/d .functor NOT 1, L_0x29e59d0, C4<0>, C4<0>, C4<0>; +L_0x29e54e0 .delay (10000,10000,10000) L_0x29e54e0/d; +L_0x29e55a0/d .functor AND 1, L_0x29e53d0, L_0x29e54e0, C4<1>, C4<1>; +L_0x29e55a0 .delay (20000,20000,20000) L_0x29e55a0/d; +L_0x29e56b0/d .functor AND 1, L_0x29e4720, L_0x29e59d0, C4<1>, C4<1>; +L_0x29e56b0 .delay (20000,20000,20000) L_0x29e56b0/d; +L_0x29e5800/d .functor OR 1, L_0x29e55a0, L_0x29e56b0, C4<0>, C4<0>; +L_0x29e5800 .delay (20000,20000,20000) L_0x29e5800/d; +v0x28cf720_0 .net "S", 0 0, L_0x29e59d0; 1 drivers +v0x28cf7a0_0 .alias "in0", 0 0, v0x28cfc40_0; +v0x28cf840_0 .alias "in1", 0 0, v0x28cfcc0_0; +v0x28cf8e0_0 .net "nS", 0 0, L_0x29e54e0; 1 drivers +v0x28cf960_0 .net "out0", 0 0, L_0x29e55a0; 1 drivers +v0x28cfa00_0 .net "out1", 0 0, L_0x29e56b0; 1 drivers +v0x28cfae0_0 .alias "outfinal", 0 0, v0x28cfd70_0; +S_0x28ce810 .scope generate, "andbits[25]" "andbits[25]" 3 231, 3 231, S_0x28ca040; + .timescale -9 -12; +P_0x28ce908 .param/l "i" 3 231, +C4<011001>; +S_0x28ce980 .scope module, "attempt" "AndNand" 3 233, 3 149, S_0x28ce810; + .timescale -9 -12; +L_0x29e52e0/d .functor NAND 1, L_0x29e6580, L_0x29e5b10, C4<1>, C4<1>; +L_0x29e52e0 .delay (10000,10000,10000) L_0x29e52e0/d; +L_0x29e5e40/d .functor NOT 1, L_0x29e52e0, C4<0>, C4<0>, C4<0>; +L_0x29e5e40 .delay (10000,10000,10000) L_0x29e5e40/d; +v0x28cefc0_0 .net "A", 0 0, L_0x29e6580; 1 drivers +v0x28cf080_0 .net "AandB", 0 0, L_0x29e5e40; 1 drivers +v0x28cf100_0 .net "AnandB", 0 0, L_0x29e52e0; 1 drivers +v0x28cf1b0_0 .net "AndNandOut", 0 0, L_0x29e6270; 1 drivers +v0x28cf290_0 .net "B", 0 0, L_0x29e5b10; 1 drivers +v0x28cf310_0 .alias "Command", 2 0, v0x295f7a0_0; +L_0x29e6440 .part v0x2960210_0, 0, 1; +S_0x28cea70 .scope module, "potato" "TwoInMux" 3 161, 3 109, S_0x28ce980; + .timescale -9 -12; +L_0x29e5f50/d .functor NOT 1, L_0x29e6440, C4<0>, C4<0>, C4<0>; +L_0x29e5f50 .delay (10000,10000,10000) L_0x29e5f50/d; +L_0x29e6010/d .functor AND 1, L_0x29e5e40, L_0x29e5f50, C4<1>, C4<1>; +L_0x29e6010 .delay (20000,20000,20000) L_0x29e6010/d; +L_0x29e6120/d .functor AND 1, L_0x29e52e0, L_0x29e6440, C4<1>, C4<1>; +L_0x29e6120 .delay (20000,20000,20000) L_0x29e6120/d; +L_0x29e6270/d .functor OR 1, L_0x29e6010, L_0x29e6120, C4<0>, C4<0>; +L_0x29e6270 .delay (20000,20000,20000) L_0x29e6270/d; +v0x28ceb60_0 .net "S", 0 0, L_0x29e6440; 1 drivers +v0x28cebe0_0 .alias "in0", 0 0, v0x28cf080_0; +v0x28cec80_0 .alias "in1", 0 0, v0x28cf100_0; +v0x28ced20_0 .net "nS", 0 0, L_0x29e5f50; 1 drivers +v0x28ceda0_0 .net "out0", 0 0, L_0x29e6010; 1 drivers +v0x28cee40_0 .net "out1", 0 0, L_0x29e6120; 1 drivers +v0x28cef20_0 .alias "outfinal", 0 0, v0x28cf1b0_0; +S_0x28cdc50 .scope generate, "andbits[26]" "andbits[26]" 3 231, 3 231, S_0x28ca040; + .timescale -9 -12; +P_0x28cdd48 .param/l "i" 3 231, +C4<011010>; +S_0x28cddc0 .scope module, "attempt" "AndNand" 3 233, 3 149, S_0x28cdc50; + .timescale -9 -12; +L_0x29e5c00/d .functor NAND 1, L_0x29e6620, L_0x29e66c0, C4<1>, C4<1>; +L_0x29e5c00 .delay (10000,10000,10000) L_0x29e5c00/d; +L_0x29e6880/d .functor NOT 1, L_0x29e5c00, C4<0>, C4<0>, C4<0>; +L_0x29e6880 .delay (10000,10000,10000) L_0x29e6880/d; +v0x28ce400_0 .net "A", 0 0, L_0x29e6620; 1 drivers +v0x28ce4c0_0 .net "AandB", 0 0, L_0x29e6880; 1 drivers +v0x28ce540_0 .net "AnandB", 0 0, L_0x29e5c00; 1 drivers +v0x28ce5f0_0 .net "AndNandOut", 0 0, L_0x29e6cd0; 1 drivers +v0x28ce6d0_0 .net "B", 0 0, L_0x29e66c0; 1 drivers +v0x28ce750_0 .alias "Command", 2 0, v0x295f7a0_0; +L_0x29e6ea0 .part v0x2960210_0, 0, 1; +S_0x28cdeb0 .scope module, "potato" "TwoInMux" 3 161, 3 109, S_0x28cddc0; + .timescale -9 -12; +L_0x29e69b0/d .functor NOT 1, L_0x29e6ea0, C4<0>, C4<0>, C4<0>; +L_0x29e69b0 .delay (10000,10000,10000) L_0x29e69b0/d; +L_0x29e6a70/d .functor AND 1, L_0x29e6880, L_0x29e69b0, C4<1>, C4<1>; +L_0x29e6a70 .delay (20000,20000,20000) L_0x29e6a70/d; +L_0x29e6b80/d .functor AND 1, L_0x29e5c00, L_0x29e6ea0, C4<1>, C4<1>; +L_0x29e6b80 .delay (20000,20000,20000) L_0x29e6b80/d; +L_0x29e6cd0/d .functor OR 1, L_0x29e6a70, L_0x29e6b80, C4<0>, C4<0>; +L_0x29e6cd0 .delay (20000,20000,20000) L_0x29e6cd0/d; +v0x28cdfa0_0 .net "S", 0 0, L_0x29e6ea0; 1 drivers +v0x28ce020_0 .alias "in0", 0 0, v0x28ce4c0_0; +v0x28ce0c0_0 .alias "in1", 0 0, v0x28ce540_0; +v0x28ce160_0 .net "nS", 0 0, L_0x29e69b0; 1 drivers +v0x28ce1e0_0 .net "out0", 0 0, L_0x29e6a70; 1 drivers +v0x28ce280_0 .net "out1", 0 0, L_0x29e6b80; 1 drivers +v0x28ce360_0 .alias "outfinal", 0 0, v0x28ce5f0_0; +S_0x28cd090 .scope generate, "andbits[27]" "andbits[27]" 3 231, 3 231, S_0x28ca040; + .timescale -9 -12; +P_0x28cd188 .param/l "i" 3 231, +C4<011011>; +S_0x28cd200 .scope module, "attempt" "AndNand" 3 233, 3 149, S_0x28cd090; + .timescale -9 -12; +L_0x29e67b0/d .functor NAND 1, L_0x29e7a50, L_0x29e6fe0, C4<1>, C4<1>; +L_0x29e67b0 .delay (10000,10000,10000) L_0x29e67b0/d; +L_0x29e72f0/d .functor NOT 1, L_0x29e67b0, C4<0>, C4<0>, C4<0>; +L_0x29e72f0 .delay (10000,10000,10000) L_0x29e72f0/d; +v0x28cd840_0 .net "A", 0 0, L_0x29e7a50; 1 drivers +v0x28cd900_0 .net "AandB", 0 0, L_0x29e72f0; 1 drivers +v0x28cd980_0 .net "AnandB", 0 0, L_0x29e67b0; 1 drivers +v0x28cda30_0 .net "AndNandOut", 0 0, L_0x29e7740; 1 drivers +v0x28cdb10_0 .net "B", 0 0, L_0x29e6fe0; 1 drivers +v0x28cdb90_0 .alias "Command", 2 0, v0x295f7a0_0; +L_0x29e7910 .part v0x2960210_0, 0, 1; +S_0x28cd2f0 .scope module, "potato" "TwoInMux" 3 161, 3 109, S_0x28cd200; + .timescale -9 -12; +L_0x29e7420/d .functor NOT 1, L_0x29e7910, C4<0>, C4<0>, C4<0>; +L_0x29e7420 .delay (10000,10000,10000) L_0x29e7420/d; +L_0x29e74e0/d .functor AND 1, L_0x29e72f0, L_0x29e7420, C4<1>, C4<1>; +L_0x29e74e0 .delay (20000,20000,20000) L_0x29e74e0/d; +L_0x29e75f0/d .functor AND 1, L_0x29e67b0, L_0x29e7910, C4<1>, C4<1>; +L_0x29e75f0 .delay (20000,20000,20000) L_0x29e75f0/d; +L_0x29e7740/d .functor OR 1, L_0x29e74e0, L_0x29e75f0, C4<0>, C4<0>; +L_0x29e7740 .delay (20000,20000,20000) L_0x29e7740/d; +v0x28cd3e0_0 .net "S", 0 0, L_0x29e7910; 1 drivers +v0x28cd460_0 .alias "in0", 0 0, v0x28cd900_0; +v0x28cd500_0 .alias "in1", 0 0, v0x28cd980_0; +v0x28cd5a0_0 .net "nS", 0 0, L_0x29e7420; 1 drivers +v0x28cd620_0 .net "out0", 0 0, L_0x29e74e0; 1 drivers +v0x28cd6c0_0 .net "out1", 0 0, L_0x29e75f0; 1 drivers +v0x28cd7a0_0 .alias "outfinal", 0 0, v0x28cda30_0; +S_0x28cc4d0 .scope generate, "andbits[28]" "andbits[28]" 3 231, 3 231, S_0x28ca040; + .timescale -9 -12; +P_0x28cc5c8 .param/l "i" 3 231, +C4<011100>; +S_0x28cc640 .scope module, "attempt" "AndNand" 3 233, 3 149, S_0x28cc4d0; + .timescale -9 -12; +L_0x29e70d0/d .functor NAND 1, L_0x29e7af0, L_0x29e7b90, C4<1>, C4<1>; +L_0x29e70d0 .delay (10000,10000,10000) L_0x29e70d0/d; +L_0x29e7d80/d .functor NOT 1, L_0x29e70d0, C4<0>, C4<0>, C4<0>; +L_0x29e7d80 .delay (10000,10000,10000) L_0x29e7d80/d; +v0x28ccc80_0 .net "A", 0 0, L_0x29e7af0; 1 drivers +v0x28ccd40_0 .net "AandB", 0 0, L_0x29e7d80; 1 drivers +v0x28ccdc0_0 .net "AnandB", 0 0, L_0x29e70d0; 1 drivers +v0x28cce70_0 .net "AndNandOut", 0 0, L_0x29e81b0; 1 drivers +v0x28ccf50_0 .net "B", 0 0, L_0x29e7b90; 1 drivers +v0x28ccfd0_0 .alias "Command", 2 0, v0x295f7a0_0; +L_0x29e8380 .part v0x2960210_0, 0, 1; +S_0x28cc730 .scope module, "potato" "TwoInMux" 3 161, 3 109, S_0x28cc640; + .timescale -9 -12; +L_0x29e7e90/d .functor NOT 1, L_0x29e8380, C4<0>, C4<0>, C4<0>; +L_0x29e7e90 .delay (10000,10000,10000) L_0x29e7e90/d; +L_0x29e7f50/d .functor AND 1, L_0x29e7d80, L_0x29e7e90, C4<1>, C4<1>; +L_0x29e7f50 .delay (20000,20000,20000) L_0x29e7f50/d; +L_0x29e8060/d .functor AND 1, L_0x29e70d0, L_0x29e8380, C4<1>, C4<1>; +L_0x29e8060 .delay (20000,20000,20000) L_0x29e8060/d; +L_0x29e81b0/d .functor OR 1, L_0x29e7f50, L_0x29e8060, C4<0>, C4<0>; +L_0x29e81b0 .delay (20000,20000,20000) L_0x29e81b0/d; +v0x28cc820_0 .net "S", 0 0, L_0x29e8380; 1 drivers +v0x28cc8a0_0 .alias "in0", 0 0, v0x28ccd40_0; +v0x28cc940_0 .alias "in1", 0 0, v0x28ccdc0_0; +v0x28cc9e0_0 .net "nS", 0 0, L_0x29e7e90; 1 drivers +v0x28cca60_0 .net "out0", 0 0, L_0x29e7f50; 1 drivers +v0x28ccb00_0 .net "out1", 0 0, L_0x29e8060; 1 drivers +v0x28ccbe0_0 .alias "outfinal", 0 0, v0x28cce70_0; +S_0x28cb910 .scope generate, "andbits[29]" "andbits[29]" 3 231, 3 231, S_0x28ca040; + .timescale -9 -12; +P_0x28cba08 .param/l "i" 3 231, +C4<011101>; +S_0x28cba80 .scope module, "attempt" "AndNand" 3 233, 3 149, S_0x28cb910; + .timescale -9 -12; +L_0x29e7c80/d .functor NAND 1, L_0x29de740, L_0x29de7e0, C4<1>, C4<1>; +L_0x29e7c80 .delay (10000,10000,10000) L_0x29e7c80/d; +L_0x29e8800/d .functor NOT 1, L_0x29e7c80, C4<0>, C4<0>, C4<0>; +L_0x29e8800 .delay (10000,10000,10000) L_0x29e8800/d; +v0x28cc0c0_0 .net "A", 0 0, L_0x29de740; 1 drivers +v0x28cc180_0 .net "AandB", 0 0, L_0x29e8800; 1 drivers +v0x28cc200_0 .net "AnandB", 0 0, L_0x29e7c80; 1 drivers +v0x28cc2b0_0 .net "AndNandOut", 0 0, L_0x29e8c30; 1 drivers +v0x28cc390_0 .net "B", 0 0, L_0x29de7e0; 1 drivers +v0x28cc410_0 .alias "Command", 2 0, v0x295f7a0_0; +L_0x29e8e00 .part v0x2960210_0, 0, 1; +S_0x28cbb70 .scope module, "potato" "TwoInMux" 3 161, 3 109, S_0x28cba80; + .timescale -9 -12; +L_0x29e8910/d .functor NOT 1, L_0x29e8e00, C4<0>, C4<0>, C4<0>; +L_0x29e8910 .delay (10000,10000,10000) L_0x29e8910/d; +L_0x29e89d0/d .functor AND 1, L_0x29e8800, L_0x29e8910, C4<1>, C4<1>; +L_0x29e89d0 .delay (20000,20000,20000) L_0x29e89d0/d; +L_0x29e8ae0/d .functor AND 1, L_0x29e7c80, L_0x29e8e00, C4<1>, C4<1>; +L_0x29e8ae0 .delay (20000,20000,20000) L_0x29e8ae0/d; +L_0x29e8c30/d .functor OR 1, L_0x29e89d0, L_0x29e8ae0, C4<0>, C4<0>; +L_0x29e8c30 .delay (20000,20000,20000) L_0x29e8c30/d; +v0x28cbc60_0 .net "S", 0 0, L_0x29e8e00; 1 drivers +v0x28cbce0_0 .alias "in0", 0 0, v0x28cc180_0; +v0x28cbd80_0 .alias "in1", 0 0, v0x28cc200_0; +v0x28cbe20_0 .net "nS", 0 0, L_0x29e8910; 1 drivers +v0x28cbea0_0 .net "out0", 0 0, L_0x29e89d0; 1 drivers +v0x28cbf40_0 .net "out1", 0 0, L_0x29e8ae0; 1 drivers +v0x28cc020_0 .alias "outfinal", 0 0, v0x28cc2b0_0; +S_0x28cad50 .scope generate, "andbits[30]" "andbits[30]" 3 231, 3 231, S_0x28ca040; + .timescale -9 -12; +P_0x28cae48 .param/l "i" 3 231, +C4<011110>; +S_0x28caec0 .scope module, "attempt" "AndNand" 3 233, 3 149, S_0x28cad50; + .timescale -9 -12; +L_0x29d89f0/d .functor NAND 1, L_0x29e9350, L_0x29e93f0, C4<1>, C4<1>; +L_0x29d89f0 .delay (10000,10000,10000) L_0x29d89f0/d; +L_0x29e8550/d .functor NOT 1, L_0x29d89f0, C4<0>, C4<0>, C4<0>; +L_0x29e8550 .delay (10000,10000,10000) L_0x29e8550/d; +v0x28cb500_0 .net "A", 0 0, L_0x29e9350; 1 drivers +v0x28cb5c0_0 .net "AandB", 0 0, L_0x29e8550; 1 drivers +v0x28cb640_0 .net "AnandB", 0 0, L_0x29d89f0; 1 drivers +v0x28cb6f0_0 .net "AndNandOut", 0 0, L_0x29e9830; 1 drivers +v0x28cb7d0_0 .net "B", 0 0, L_0x29e93f0; 1 drivers +v0x28cb850_0 .alias "Command", 2 0, v0x295f7a0_0; +L_0x29e99c0 .part v0x2960210_0, 0, 1; +S_0x28cafb0 .scope module, "potato" "TwoInMux" 3 161, 3 109, S_0x28caec0; + .timescale -9 -12; +L_0x29e8680/d .functor NOT 1, L_0x29e99c0, C4<0>, C4<0>, C4<0>; +L_0x29e8680 .delay (10000,10000,10000) L_0x29e8680/d; +L_0x29e9610/d .functor AND 1, L_0x29e8550, L_0x29e8680, C4<1>, C4<1>; +L_0x29e9610 .delay (20000,20000,20000) L_0x29e9610/d; +L_0x29e9700/d .functor AND 1, L_0x29d89f0, L_0x29e99c0, C4<1>, C4<1>; +L_0x29e9700 .delay (20000,20000,20000) L_0x29e9700/d; +L_0x29e9830/d .functor OR 1, L_0x29e9610, L_0x29e9700, C4<0>, C4<0>; +L_0x29e9830 .delay (20000,20000,20000) L_0x29e9830/d; +v0x28cb0a0_0 .net "S", 0 0, L_0x29e99c0; 1 drivers +v0x28cb120_0 .alias "in0", 0 0, v0x28cb5c0_0; +v0x28cb1c0_0 .alias "in1", 0 0, v0x28cb640_0; +v0x28cb260_0 .net "nS", 0 0, L_0x29e8680; 1 drivers +v0x28cb2e0_0 .net "out0", 0 0, L_0x29e9610; 1 drivers +v0x28cb380_0 .net "out1", 0 0, L_0x29e9700; 1 drivers +v0x28cb460_0 .alias "outfinal", 0 0, v0x28cb6f0_0; +S_0x28ca170 .scope generate, "andbits[31]" "andbits[31]" 3 231, 3 231, S_0x28ca040; + .timescale -9 -12; +P_0x28ca268 .param/l "i" 3 231, +C4<011111>; +S_0x28ca2e0 .scope module, "attempt" "AndNand" 3 233, 3 149, S_0x28ca170; + .timescale -9 -12; +L_0x29e94e0/d .functor NAND 1, L_0x29ea4b0, L_0x29e9b00, C4<1>, C4<1>; +L_0x29e94e0 .delay (10000,10000,10000) L_0x29e94e0/d; +L_0x29e9e30/d .functor NOT 1, L_0x29e94e0, C4<0>, C4<0>, C4<0>; +L_0x29e9e30 .delay (10000,10000,10000) L_0x29e9e30/d; +v0x28ca940_0 .net "A", 0 0, L_0x29ea4b0; 1 drivers +v0x28caa00_0 .net "AandB", 0 0, L_0x29e9e30; 1 drivers +v0x28caa80_0 .net "AnandB", 0 0, L_0x29e94e0; 1 drivers +v0x28cab30_0 .net "AndNandOut", 0 0, L_0x29ea1e0; 1 drivers +v0x28cac10_0 .net "B", 0 0, L_0x29e9b00; 1 drivers +v0x28cac90_0 .alias "Command", 2 0, v0x295f7a0_0; +L_0x29ea370 .part v0x2960210_0, 0, 1; +S_0x28ca3d0 .scope module, "potato" "TwoInMux" 3 161, 3 109, S_0x28ca2e0; + .timescale -9 -12; +L_0x29e9f20/d .functor NOT 1, L_0x29ea370, C4<0>, C4<0>, C4<0>; +L_0x29e9f20 .delay (10000,10000,10000) L_0x29e9f20/d; +L_0x29e9fc0/d .functor AND 1, L_0x29e9e30, L_0x29e9f20, C4<1>, C4<1>; +L_0x29e9fc0 .delay (20000,20000,20000) L_0x29e9fc0/d; +L_0x29ea0b0/d .functor AND 1, L_0x29e94e0, L_0x29ea370, C4<1>, C4<1>; +L_0x29ea0b0 .delay (20000,20000,20000) L_0x29ea0b0/d; +L_0x29ea1e0/d .functor OR 1, L_0x29e9fc0, L_0x29ea0b0, C4<0>, C4<0>; +L_0x29ea1e0 .delay (20000,20000,20000) L_0x29ea1e0/d; +v0x28ca4c0_0 .net "S", 0 0, L_0x29ea370; 1 drivers +v0x28ca560_0 .alias "in0", 0 0, v0x28caa00_0; +v0x28ca600_0 .alias "in1", 0 0, v0x28caa80_0; +v0x28ca6a0_0 .net "nS", 0 0, L_0x29e9f20; 1 drivers +v0x28ca720_0 .net "out0", 0 0, L_0x29e9fc0; 1 drivers +v0x28ca7c0_0 .net "out1", 0 0, L_0x29ea0b0; 1 drivers +v0x28ca8a0_0 .alias "outfinal", 0 0, v0x28cab30_0; +S_0x28a2590 .scope module, "trial2" "OrNorXor32" 2 160, 3 239, S_0x22efd20; + .timescale -9 -12; +P_0x289fec8 .param/l "size" 3 246, +C4<0100000>; +v0x28c9e40_0 .alias "A", 31 0, v0x295f580_0; +v0x28c9ec0_0 .alias "B", 31 0, v0x295f6a0_0; +v0x28c9f40_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x28c9fc0_0 .alias "OrNorXorOut", 31 0, v0x29603c0_0; +L_0x29ebfa0 .part/pv L_0x29ebd70, 1, 1, 32; +L_0x29ec0d0 .part v0x295fe90_0, 1, 1; +L_0x29ec170 .part v0x2960190_0, 1, 1; +L_0x29ed0e0 .part/pv L_0x29eceb0, 2, 1, 32; +L_0x29ed180 .part v0x295fe90_0, 2, 1; +L_0x29ed220 .part v0x2960190_0, 2, 1; +L_0x29ee260 .part/pv L_0x29edff0, 3, 1, 32; +L_0x29ee300 .part v0x295fe90_0, 3, 1; +L_0x29ee3a0 .part v0x2960190_0, 3, 1; +L_0x29ef550 .part/pv L_0x29ef2e0, 4, 1, 32; +L_0x29ef650 .part v0x295fe90_0, 4, 1; +L_0x29ef6f0 .part v0x2960190_0, 4, 1; +L_0x29f0850 .part/pv L_0x29f05e0, 5, 1, 32; +L_0x29f0a00 .part v0x295fe90_0, 5, 1; +L_0x29f0aa0 .part v0x2960190_0, 5, 1; +L_0x29f1c40 .part/pv L_0x29f19d0, 6, 1, 32; +L_0x29f1ce0 .part v0x295fe90_0, 6, 1; +L_0x29f1d80 .part v0x2960190_0, 6, 1; +L_0x29f2f40 .part/pv L_0x29f2cd0, 7, 1, 32; +L_0x29f2fe0 .part v0x295fe90_0, 7, 1; +L_0x29f1e20 .part v0x2960190_0, 7, 1; +L_0x29f4230 .part/pv L_0x29f3fc0, 8, 1, 32; +L_0x29f3080 .part v0x295fe90_0, 8, 1; +L_0x29f4390 .part v0x2960190_0, 8, 1; +L_0x29f5540 .part/pv L_0x29f52d0, 9, 1, 32; +L_0x29f55e0 .part v0x295fe90_0, 9, 1; +L_0x29f4430 .part v0x2960190_0, 9, 1; +L_0x29f6720 .part/pv L_0x29f64f0, 10, 1, 32; +L_0x29f5680 .part v0x295fe90_0, 10, 1; +L_0x29f68b0 .part v0x2960190_0, 10, 1; +L_0x29f78e0 .part/pv L_0x29f7670, 11, 1, 32; +L_0x29f7980 .part v0x295fe90_0, 11, 1; +L_0x29f6950 .part v0x2960190_0, 11, 1; +L_0x29f8bd0 .part/pv L_0x29f8960, 12, 1, 32; +L_0x29f7a20 .part v0x295fe90_0, 12, 1; +L_0x29f8d90 .part v0x2960190_0, 12, 1; +L_0x29f9ef0 .part/pv L_0x29f9c80, 13, 1, 32; +L_0x29f08f0 .part v0x295fe90_0, 13, 1; +L_0x29f8e30 .part v0x2960190_0, 13, 1; +L_0x29fb300 .part/pv L_0x29fb090, 14, 1, 32; +L_0x29fa1a0 .part v0x295fe90_0, 14, 1; +L_0x29fa240 .part v0x2960190_0, 14, 1; +L_0x29fc600 .part/pv L_0x29fc390, 15, 1, 32; +L_0x29fc6a0 .part v0x295fe90_0, 15, 1; +L_0x29fb3a0 .part v0x2960190_0, 15, 1; +L_0x29fd8f0 .part/pv L_0x29fd680, 16, 1, 32; +L_0x29fc740 .part v0x295fe90_0, 16, 1; +L_0x29fc7e0 .part v0x2960190_0, 16, 1; +L_0x29fec00 .part/pv L_0x29fe990, 17, 1, 32; +L_0x29feca0 .part v0x295fe90_0, 17, 1; +L_0x29fd990 .part v0x2960190_0, 17, 1; +L_0x29ffef0 .part/pv L_0x29ffc80, 18, 1, 32; +L_0x29fed40 .part v0x295fe90_0, 18, 1; +L_0x29fede0 .part v0x2960190_0, 18, 1; +L_0x2a02200 .part/pv L_0x29b5c70, 19, 1, 32; +L_0x2a022a0 .part v0x295fe90_0, 19, 1; +L_0x29b4e70 .part v0x2960190_0, 19, 1; +L_0x2a033c0 .part/pv L_0x2a03150, 20, 1, 32; +L_0x2a02340 .part v0x295fe90_0, 20, 1; +L_0x2a023e0 .part v0x2960190_0, 20, 1; +L_0x2a046d0 .part/pv L_0x2a04460, 21, 1, 32; +L_0x2a04770 .part v0x295fe90_0, 21, 1; +L_0x2a03460 .part v0x2960190_0, 21, 1; +L_0x2a059c0 .part/pv L_0x2a05750, 22, 1, 32; +L_0x2a04810 .part v0x295fe90_0, 22, 1; +L_0x2a048b0 .part v0x2960190_0, 22, 1; +L_0x2a06cc0 .part/pv L_0x2a06a50, 23, 1, 32; +L_0x2a06d60 .part v0x295fe90_0, 23, 1; +L_0x2a05a60 .part v0x2960190_0, 23, 1; +L_0x2a07f80 .part/pv L_0x2a07d10, 24, 1, 32; +L_0x2a06e00 .part v0x295fe90_0, 24, 1; +L_0x2a06ea0 .part v0x2960190_0, 24, 1; +L_0x2a09280 .part/pv L_0x2a09010, 25, 1, 32; +L_0x2a09320 .part v0x295fe90_0, 25, 1; +L_0x2a08020 .part v0x2960190_0, 25, 1; +L_0x2a0a570 .part/pv L_0x2a0a300, 26, 1, 32; +L_0x2a093c0 .part v0x295fe90_0, 26, 1; +L_0x2a09460 .part v0x2960190_0, 26, 1; +L_0x2a0b880 .part/pv L_0x2a0b610, 27, 1, 32; +L_0x2a0b920 .part v0x295fe90_0, 27, 1; +L_0x2a0a610 .part v0x2960190_0, 27, 1; +L_0x2a0cb80 .part/pv L_0x2a0c910, 28, 1, 32; +L_0x2a0b9c0 .part v0x295fe90_0, 28, 1; +L_0x2a0ba60 .part v0x2960190_0, 28, 1; +L_0x2a0de80 .part/pv L_0x2a0dc10, 29, 1, 32; +L_0x29f9f90 .part v0x295fe90_0, 29, 1; +L_0x29fa030 .part v0x2960190_0, 29, 1; +L_0x2a0f240 .part/pv L_0x2a0f010, 30, 1, 32; +L_0x2a0e330 .part v0x295fe90_0, 30, 1; +L_0x2a0e3d0 .part v0x2960190_0, 30, 1; +L_0x2a10550 .part/pv L_0x2a102e0, 31, 1, 32; +L_0x2a105f0 .part v0x295fe90_0, 31, 1; +L_0x2a0f2e0 .part v0x2960190_0, 31, 1; +L_0x2a11840 .part/pv L_0x2a115d0, 0, 1, 32; +L_0x2a10690 .part v0x295fe90_0, 0, 1; +L_0x2a10730 .part v0x2960190_0, 0, 1; +S_0x28c8c00 .scope module, "attempt2" "OrNorXor" 3 254, 3 165, S_0x28a2590; + .timescale -9 -12; +L_0x2a0f380/d .functor NOR 1, L_0x2a10690, L_0x2a10730, C4<0>, C4<0>; +L_0x2a0f380 .delay (10000,10000,10000) L_0x2a0f380/d; +L_0x2a0f470/d .functor NOT 1, L_0x2a0f380, C4<0>, C4<0>, C4<0>; +L_0x2a0f470 .delay (10000,10000,10000) L_0x2a0f470/d; +L_0x2a10980/d .functor NAND 1, L_0x2a10690, L_0x2a10730, C4<1>, C4<1>; +L_0x2a10980 .delay (10000,10000,10000) L_0x2a10980/d; +L_0x2a10ac0/d .functor NAND 1, L_0x2a10980, L_0x2a0f470, C4<1>, C4<1>; +L_0x2a10ac0 .delay (10000,10000,10000) L_0x2a10ac0/d; +L_0x2a10bd0/d .functor NOT 1, L_0x2a10ac0, C4<0>, C4<0>, C4<0>; +L_0x2a10bd0 .delay (10000,10000,10000) L_0x2a10bd0/d; +v0x28c9750_0 .net "A", 0 0, L_0x2a10690; 1 drivers +v0x28c97f0_0 .net "AnandB", 0 0, L_0x2a10980; 1 drivers +v0x28c9890_0 .net "AnorB", 0 0, L_0x2a0f380; 1 drivers +v0x28c9940_0 .net "AorB", 0 0, L_0x2a0f470; 1 drivers +v0x28c9a20_0 .net "AxorB", 0 0, L_0x2a10bd0; 1 drivers +v0x28c9ad0_0 .net "B", 0 0, L_0x2a10730; 1 drivers +v0x28c9b90_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x28c9c10_0 .net "OrNorXorOut", 0 0, L_0x2a115d0; 1 drivers +v0x28c9c90_0 .net "XorNor", 0 0, L_0x2a11050; 1 drivers +v0x28c9d60_0 .net "nXor", 0 0, L_0x2a10ac0; 1 drivers +L_0x2a111d0 .part v0x2960210_0, 2, 1; +L_0x2a117a0 .part v0x2960210_0, 0, 1; +S_0x28c91e0 .scope module, "mux0" "TwoInMux" 3 184, 3 109, S_0x28c8c00; + .timescale -9 -12; +L_0x2a10d30/d .functor NOT 1, L_0x2a111d0, C4<0>, C4<0>, C4<0>; +L_0x2a10d30 .delay (10000,10000,10000) L_0x2a10d30/d; +L_0x2a10df0/d .functor AND 1, L_0x2a10bd0, L_0x2a10d30, C4<1>, C4<1>; +L_0x2a10df0 .delay (20000,20000,20000) L_0x2a10df0/d; +L_0x2a10f00/d .functor AND 1, L_0x2a0f380, L_0x2a111d0, C4<1>, C4<1>; +L_0x2a10f00 .delay (20000,20000,20000) L_0x2a10f00/d; +L_0x2a11050/d .functor OR 1, L_0x2a10df0, L_0x2a10f00, C4<0>, C4<0>; +L_0x2a11050 .delay (20000,20000,20000) L_0x2a11050/d; +v0x28c92d0_0 .net "S", 0 0, L_0x2a111d0; 1 drivers +v0x28c9390_0 .alias "in0", 0 0, v0x28c9a20_0; +v0x28c9430_0 .alias "in1", 0 0, v0x28c9890_0; +v0x28c94d0_0 .net "nS", 0 0, L_0x2a10d30; 1 drivers +v0x28c9550_0 .net "out0", 0 0, L_0x2a10df0; 1 drivers +v0x28c95f0_0 .net "out1", 0 0, L_0x2a10f00; 1 drivers +v0x28c96d0_0 .alias "outfinal", 0 0, v0x28c9c90_0; +S_0x28c8cf0 .scope module, "mux1" "TwoInMux" 3 185, 3 109, S_0x28c8c00; + .timescale -9 -12; +L_0x2a11270/d .functor NOT 1, L_0x2a117a0, C4<0>, C4<0>, C4<0>; +L_0x2a11270 .delay (10000,10000,10000) L_0x2a11270/d; +L_0x2a11330/d .functor AND 1, L_0x2a11050, L_0x2a11270, C4<1>, C4<1>; +L_0x2a11330 .delay (20000,20000,20000) L_0x2a11330/d; +L_0x2a11480/d .functor AND 1, L_0x2a0f470, L_0x2a117a0, C4<1>, C4<1>; +L_0x2a11480 .delay (20000,20000,20000) L_0x2a11480/d; +L_0x2a115d0/d .functor OR 1, L_0x2a11330, L_0x2a11480, C4<0>, C4<0>; +L_0x2a115d0 .delay (20000,20000,20000) L_0x2a115d0/d; +v0x28c8de0_0 .net "S", 0 0, L_0x2a117a0; 1 drivers +v0x28c8e60_0 .alias "in0", 0 0, v0x28c9c90_0; +v0x28c8ee0_0 .alias "in1", 0 0, v0x28c9940_0; +v0x28c8f80_0 .net "nS", 0 0, L_0x2a11270; 1 drivers +v0x28c9000_0 .net "out0", 0 0, L_0x2a11330; 1 drivers +v0x28c90a0_0 .net "out1", 0 0, L_0x2a11480; 1 drivers +v0x28c9140_0 .alias "outfinal", 0 0, v0x28c9c10_0; +S_0x28c7830 .scope generate, "orbits[1]" "orbits[1]" 3 258, 3 258, S_0x28a2590; + .timescale -9 -12; +P_0x28c7548 .param/l "i" 3 258, +C4<01>; +S_0x28c7960 .scope module, "attempt" "OrNorXor" 3 260, 3 165, S_0x28c7830; + .timescale -9 -12; +L_0x29ea6e0/d .functor NOR 1, L_0x29ec0d0, L_0x29ec170, C4<0>, C4<0>; +L_0x29ea6e0 .delay (10000,10000,10000) L_0x29ea6e0/d; +L_0x29eb170/d .functor NOT 1, L_0x29ea6e0, C4<0>, C4<0>, C4<0>; +L_0x29eb170 .delay (10000,10000,10000) L_0x29eb170/d; +L_0x29eb260/d .functor NAND 1, L_0x29ec0d0, L_0x29ec170, C4<1>, C4<1>; +L_0x29eb260 .delay (10000,10000,10000) L_0x29eb260/d; +L_0x29eb3a0/d .functor NAND 1, L_0x29eb260, L_0x29eb170, C4<1>, C4<1>; +L_0x29eb3a0 .delay (10000,10000,10000) L_0x29eb3a0/d; +L_0x29eb490/d .functor NOT 1, L_0x29eb3a0, C4<0>, C4<0>, C4<0>; +L_0x29eb490 .delay (10000,10000,10000) L_0x29eb490/d; +v0x28c8510_0 .net "A", 0 0, L_0x29ec0d0; 1 drivers +v0x28c85b0_0 .net "AnandB", 0 0, L_0x29eb260; 1 drivers +v0x28c8650_0 .net "AnorB", 0 0, L_0x29ea6e0; 1 drivers +v0x28c8700_0 .net "AorB", 0 0, L_0x29eb170; 1 drivers +v0x28c87e0_0 .net "AxorB", 0 0, L_0x29eb490; 1 drivers +v0x28c8890_0 .net "B", 0 0, L_0x29ec170; 1 drivers +v0x28c8950_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x28c89d0_0 .net "OrNorXorOut", 0 0, L_0x29ebd70; 1 drivers +v0x28c8a50_0 .net "XorNor", 0 0, L_0x29eb890; 1 drivers +v0x28c8b20_0 .net "nXor", 0 0, L_0x29eb3a0; 1 drivers +L_0x29eb9d0 .part v0x2960210_0, 2, 1; +L_0x29ebf00 .part v0x2960210_0, 0, 1; +S_0x28c7fa0 .scope module, "mux0" "TwoInMux" 3 184, 3 109, S_0x28c7960; + .timescale -9 -12; +L_0x29eb5d0/d .functor NOT 1, L_0x29eb9d0, C4<0>, C4<0>, C4<0>; +L_0x29eb5d0 .delay (10000,10000,10000) L_0x29eb5d0/d; +L_0x29eb670/d .functor AND 1, L_0x29eb490, L_0x29eb5d0, C4<1>, C4<1>; +L_0x29eb670 .delay (20000,20000,20000) L_0x29eb670/d; +L_0x29eb760/d .functor AND 1, L_0x29ea6e0, L_0x29eb9d0, C4<1>, C4<1>; +L_0x29eb760 .delay (20000,20000,20000) L_0x29eb760/d; +L_0x29eb890/d .functor OR 1, L_0x29eb670, L_0x29eb760, C4<0>, C4<0>; +L_0x29eb890 .delay (20000,20000,20000) L_0x29eb890/d; +v0x28c8090_0 .net "S", 0 0, L_0x29eb9d0; 1 drivers +v0x28c8150_0 .alias "in0", 0 0, v0x28c87e0_0; +v0x28c81f0_0 .alias "in1", 0 0, v0x28c8650_0; +v0x28c8290_0 .net "nS", 0 0, L_0x29eb5d0; 1 drivers +v0x28c8310_0 .net "out0", 0 0, L_0x29eb670; 1 drivers +v0x28c83b0_0 .net "out1", 0 0, L_0x29eb760; 1 drivers +v0x28c8490_0 .alias "outfinal", 0 0, v0x28c8a50_0; +S_0x28c7a50 .scope module, "mux1" "TwoInMux" 3 185, 3 109, S_0x28c7960; + .timescale -9 -12; +L_0x29eba70/d .functor NOT 1, L_0x29ebf00, C4<0>, C4<0>, C4<0>; +L_0x29eba70 .delay (10000,10000,10000) L_0x29eba70/d; +L_0x29ebb10/d .functor AND 1, L_0x29eb890, L_0x29eba70, C4<1>, C4<1>; +L_0x29ebb10 .delay (20000,20000,20000) L_0x29ebb10/d; +L_0x29ebc40/d .functor AND 1, L_0x29eb170, L_0x29ebf00, C4<1>, C4<1>; +L_0x29ebc40 .delay (20000,20000,20000) L_0x29ebc40/d; +L_0x29ebd70/d .functor OR 1, L_0x29ebb10, L_0x29ebc40, C4<0>, C4<0>; +L_0x29ebd70 .delay (20000,20000,20000) L_0x29ebd70/d; +v0x28c7b40_0 .net "S", 0 0, L_0x29ebf00; 1 drivers +v0x28c7bc0_0 .alias "in0", 0 0, v0x28c8a50_0; +v0x28c7c60_0 .alias "in1", 0 0, v0x28c8700_0; +v0x28c7d00_0 .net "nS", 0 0, L_0x29eba70; 1 drivers +v0x28c7d80_0 .net "out0", 0 0, L_0x29ebb10; 1 drivers +v0x28c7e20_0 .net "out1", 0 0, L_0x29ebc40; 1 drivers +v0x28c7f00_0 .alias "outfinal", 0 0, v0x28c89d0_0; +S_0x28c6460 .scope generate, "orbits[2]" "orbits[2]" 3 258, 3 258, S_0x28a2590; + .timescale -9 -12; +P_0x28c6178 .param/l "i" 3 258, +C4<010>; +S_0x28c6590 .scope module, "attempt" "OrNorXor" 3 260, 3 165, S_0x28c6460; + .timescale -9 -12; +L_0x29ec210/d .functor NOR 1, L_0x29ed180, L_0x29ed220, C4<0>, C4<0>; +L_0x29ec210 .delay (10000,10000,10000) L_0x29ec210/d; +L_0x29ec2b0/d .functor NOT 1, L_0x29ec210, C4<0>, C4<0>, C4<0>; +L_0x29ec2b0 .delay (10000,10000,10000) L_0x29ec2b0/d; +L_0x29ec3a0/d .functor NAND 1, L_0x29ed180, L_0x29ed220, C4<1>, C4<1>; +L_0x29ec3a0 .delay (10000,10000,10000) L_0x29ec3a0/d; +L_0x29ec4e0/d .functor NAND 1, L_0x29ec3a0, L_0x29ec2b0, C4<1>, C4<1>; +L_0x29ec4e0 .delay (10000,10000,10000) L_0x29ec4e0/d; +L_0x29ec5d0/d .functor NOT 1, L_0x29ec4e0, C4<0>, C4<0>, C4<0>; +L_0x29ec5d0 .delay (10000,10000,10000) L_0x29ec5d0/d; +v0x28c7140_0 .net "A", 0 0, L_0x29ed180; 1 drivers +v0x28c71e0_0 .net "AnandB", 0 0, L_0x29ec3a0; 1 drivers +v0x28c7280_0 .net "AnorB", 0 0, L_0x29ec210; 1 drivers +v0x28c7330_0 .net "AorB", 0 0, L_0x29ec2b0; 1 drivers +v0x28c7410_0 .net "AxorB", 0 0, L_0x29ec5d0; 1 drivers +v0x28c74c0_0 .net "B", 0 0, L_0x29ed220; 1 drivers +v0x28c7580_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x28c7600_0 .net "OrNorXorOut", 0 0, L_0x29eceb0; 1 drivers +v0x28c7680_0 .net "XorNor", 0 0, L_0x29ec9d0; 1 drivers +v0x28c7750_0 .net "nXor", 0 0, L_0x29ec4e0; 1 drivers +L_0x29ecb10 .part v0x2960210_0, 2, 1; +L_0x29ed040 .part v0x2960210_0, 0, 1; +S_0x28c6bd0 .scope module, "mux0" "TwoInMux" 3 184, 3 109, S_0x28c6590; + .timescale -9 -12; +L_0x29ec710/d .functor NOT 1, L_0x29ecb10, C4<0>, C4<0>, C4<0>; +L_0x29ec710 .delay (10000,10000,10000) L_0x29ec710/d; +L_0x29ec7b0/d .functor AND 1, L_0x29ec5d0, L_0x29ec710, C4<1>, C4<1>; +L_0x29ec7b0 .delay (20000,20000,20000) L_0x29ec7b0/d; +L_0x29ec8a0/d .functor AND 1, L_0x29ec210, L_0x29ecb10, C4<1>, C4<1>; +L_0x29ec8a0 .delay (20000,20000,20000) L_0x29ec8a0/d; +L_0x29ec9d0/d .functor OR 1, L_0x29ec7b0, L_0x29ec8a0, C4<0>, C4<0>; +L_0x29ec9d0 .delay (20000,20000,20000) L_0x29ec9d0/d; +v0x28c6cc0_0 .net "S", 0 0, L_0x29ecb10; 1 drivers +v0x28c6d80_0 .alias "in0", 0 0, v0x28c7410_0; +v0x28c6e20_0 .alias "in1", 0 0, v0x28c7280_0; +v0x28c6ec0_0 .net "nS", 0 0, L_0x29ec710; 1 drivers +v0x28c6f40_0 .net "out0", 0 0, L_0x29ec7b0; 1 drivers +v0x28c6fe0_0 .net "out1", 0 0, L_0x29ec8a0; 1 drivers +v0x28c70c0_0 .alias "outfinal", 0 0, v0x28c7680_0; +S_0x28c6680 .scope module, "mux1" "TwoInMux" 3 185, 3 109, S_0x28c6590; + .timescale -9 -12; +L_0x29ecbb0/d .functor NOT 1, L_0x29ed040, C4<0>, C4<0>, C4<0>; +L_0x29ecbb0 .delay (10000,10000,10000) L_0x29ecbb0/d; +L_0x29ecc50/d .functor AND 1, L_0x29ec9d0, L_0x29ecbb0, C4<1>, C4<1>; +L_0x29ecc50 .delay (20000,20000,20000) L_0x29ecc50/d; +L_0x29ecd80/d .functor AND 1, L_0x29ec2b0, L_0x29ed040, C4<1>, C4<1>; +L_0x29ecd80 .delay (20000,20000,20000) L_0x29ecd80/d; +L_0x29eceb0/d .functor OR 1, L_0x29ecc50, L_0x29ecd80, C4<0>, C4<0>; +L_0x29eceb0 .delay (20000,20000,20000) L_0x29eceb0/d; +v0x28c6770_0 .net "S", 0 0, L_0x29ed040; 1 drivers +v0x28c67f0_0 .alias "in0", 0 0, v0x28c7680_0; +v0x28c6890_0 .alias "in1", 0 0, v0x28c7330_0; +v0x28c6930_0 .net "nS", 0 0, L_0x29ecbb0; 1 drivers +v0x28c69b0_0 .net "out0", 0 0, L_0x29ecc50; 1 drivers +v0x28c6a50_0 .net "out1", 0 0, L_0x29ecd80; 1 drivers +v0x28c6b30_0 .alias "outfinal", 0 0, v0x28c7600_0; +S_0x28c5090 .scope generate, "orbits[3]" "orbits[3]" 3 258, 3 258, S_0x28a2590; + .timescale -9 -12; +P_0x28c4da8 .param/l "i" 3 258, +C4<011>; +S_0x28c51c0 .scope module, "attempt" "OrNorXor" 3 260, 3 165, S_0x28c5090; + .timescale -9 -12; +L_0x29ed300/d .functor NOR 1, L_0x29ee300, L_0x29ee3a0, C4<0>, C4<0>; +L_0x29ed300 .delay (10000,10000,10000) L_0x29ed300/d; +L_0x29ed3f0/d .functor NOT 1, L_0x29ed300, C4<0>, C4<0>, C4<0>; +L_0x29ed3f0 .delay (10000,10000,10000) L_0x29ed3f0/d; +L_0x29ed4e0/d .functor NAND 1, L_0x29ee300, L_0x29ee3a0, C4<1>, C4<1>; +L_0x29ed4e0 .delay (10000,10000,10000) L_0x29ed4e0/d; +L_0x29ed620/d .functor NAND 1, L_0x29ed4e0, L_0x29ed3f0, C4<1>, C4<1>; +L_0x29ed620 .delay (10000,10000,10000) L_0x29ed620/d; +L_0x29ed710/d .functor NOT 1, L_0x29ed620, C4<0>, C4<0>, C4<0>; +L_0x29ed710 .delay (10000,10000,10000) L_0x29ed710/d; +v0x28c5d70_0 .net "A", 0 0, L_0x29ee300; 1 drivers +v0x28c5e10_0 .net "AnandB", 0 0, L_0x29ed4e0; 1 drivers +v0x28c5eb0_0 .net "AnorB", 0 0, L_0x29ed300; 1 drivers +v0x28c5f60_0 .net "AorB", 0 0, L_0x29ed3f0; 1 drivers +v0x28c6040_0 .net "AxorB", 0 0, L_0x29ed710; 1 drivers +v0x28c60f0_0 .net "B", 0 0, L_0x29ee3a0; 1 drivers +v0x28c61b0_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x28c6230_0 .net "OrNorXorOut", 0 0, L_0x29edff0; 1 drivers +v0x28c62b0_0 .net "XorNor", 0 0, L_0x29edb10; 1 drivers +v0x28c6380_0 .net "nXor", 0 0, L_0x29ed620; 1 drivers +L_0x29edc50 .part v0x2960210_0, 2, 1; +L_0x29ee1c0 .part v0x2960210_0, 0, 1; +S_0x28c5800 .scope module, "mux0" "TwoInMux" 3 184, 3 109, S_0x28c51c0; + .timescale -9 -12; +L_0x29ed850/d .functor NOT 1, L_0x29edc50, C4<0>, C4<0>, C4<0>; +L_0x29ed850 .delay (10000,10000,10000) L_0x29ed850/d; +L_0x29ed8f0/d .functor AND 1, L_0x29ed710, L_0x29ed850, C4<1>, C4<1>; +L_0x29ed8f0 .delay (20000,20000,20000) L_0x29ed8f0/d; +L_0x29ed9e0/d .functor AND 1, L_0x29ed300, L_0x29edc50, C4<1>, C4<1>; +L_0x29ed9e0 .delay (20000,20000,20000) L_0x29ed9e0/d; +L_0x29edb10/d .functor OR 1, L_0x29ed8f0, L_0x29ed9e0, C4<0>, C4<0>; +L_0x29edb10 .delay (20000,20000,20000) L_0x29edb10/d; +v0x28c58f0_0 .net "S", 0 0, L_0x29edc50; 1 drivers +v0x28c59b0_0 .alias "in0", 0 0, v0x28c6040_0; +v0x28c5a50_0 .alias "in1", 0 0, v0x28c5eb0_0; +v0x28c5af0_0 .net "nS", 0 0, L_0x29ed850; 1 drivers +v0x28c5b70_0 .net "out0", 0 0, L_0x29ed8f0; 1 drivers +v0x28c5c10_0 .net "out1", 0 0, L_0x29ed9e0; 1 drivers +v0x28c5cf0_0 .alias "outfinal", 0 0, v0x28c62b0_0; +S_0x28c52b0 .scope module, "mux1" "TwoInMux" 3 185, 3 109, S_0x28c51c0; + .timescale -9 -12; +L_0x29edcf0/d .functor NOT 1, L_0x29ee1c0, C4<0>, C4<0>, C4<0>; +L_0x29edcf0 .delay (10000,10000,10000) L_0x29edcf0/d; +L_0x29edd90/d .functor AND 1, L_0x29edb10, L_0x29edcf0, C4<1>, C4<1>; +L_0x29edd90 .delay (20000,20000,20000) L_0x29edd90/d; +L_0x29edec0/d .functor AND 1, L_0x29ed3f0, L_0x29ee1c0, C4<1>, C4<1>; +L_0x29edec0 .delay (20000,20000,20000) L_0x29edec0/d; +L_0x29edff0/d .functor OR 1, L_0x29edd90, L_0x29edec0, C4<0>, C4<0>; +L_0x29edff0 .delay (20000,20000,20000) L_0x29edff0/d; +v0x28c53a0_0 .net "S", 0 0, L_0x29ee1c0; 1 drivers +v0x28c5420_0 .alias "in0", 0 0, v0x28c62b0_0; +v0x28c54c0_0 .alias "in1", 0 0, v0x28c5f60_0; +v0x28c5560_0 .net "nS", 0 0, L_0x29edcf0; 1 drivers +v0x28c55e0_0 .net "out0", 0 0, L_0x29edd90; 1 drivers +v0x28c5680_0 .net "out1", 0 0, L_0x29edec0; 1 drivers +v0x28c5760_0 .alias "outfinal", 0 0, v0x28c6230_0; +S_0x28c3cc0 .scope generate, "orbits[4]" "orbits[4]" 3 258, 3 258, S_0x28a2590; + .timescale -9 -12; +P_0x28c39d8 .param/l "i" 3 258, +C4<0100>; +S_0x28c3df0 .scope module, "attempt" "OrNorXor" 3 260, 3 165, S_0x28c3cc0; + .timescale -9 -12; +L_0x29ee440/d .functor NOR 1, L_0x29ef650, L_0x29ef6f0, C4<0>, C4<0>; +L_0x29ee440 .delay (10000,10000,10000) L_0x29ee440/d; +L_0x29ee540/d .functor NOT 1, L_0x29ee440, C4<0>, C4<0>, C4<0>; +L_0x29ee540 .delay (10000,10000,10000) L_0x29ee540/d; +L_0x29ee670/d .functor NAND 1, L_0x29ef650, L_0x29ef6f0, C4<1>, C4<1>; +L_0x29ee670 .delay (10000,10000,10000) L_0x29ee670/d; +L_0x29ee7d0/d .functor NAND 1, L_0x29ee670, L_0x29ee540, C4<1>, C4<1>; +L_0x29ee7d0 .delay (10000,10000,10000) L_0x29ee7d0/d; +L_0x29ee8e0/d .functor NOT 1, L_0x29ee7d0, C4<0>, C4<0>, C4<0>; +L_0x29ee8e0 .delay (10000,10000,10000) L_0x29ee8e0/d; +v0x28c49a0_0 .net "A", 0 0, L_0x29ef650; 1 drivers +v0x28c4a40_0 .net "AnandB", 0 0, L_0x29ee670; 1 drivers +v0x28c4ae0_0 .net "AnorB", 0 0, L_0x29ee440; 1 drivers +v0x28c4b90_0 .net "AorB", 0 0, L_0x29ee540; 1 drivers +v0x28c4c70_0 .net "AxorB", 0 0, L_0x29ee8e0; 1 drivers +v0x28c4d20_0 .net "B", 0 0, L_0x29ef6f0; 1 drivers +v0x28c4de0_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x28c4e60_0 .net "OrNorXorOut", 0 0, L_0x29ef2e0; 1 drivers +v0x28c4ee0_0 .net "XorNor", 0 0, L_0x29eed60; 1 drivers +v0x28c4fb0_0 .net "nXor", 0 0, L_0x29ee7d0; 1 drivers +L_0x29eeee0 .part v0x2960210_0, 2, 1; +L_0x29ef4b0 .part v0x2960210_0, 0, 1; +S_0x28c4430 .scope module, "mux0" "TwoInMux" 3 184, 3 109, S_0x28c3df0; + .timescale -9 -12; +L_0x29eea40/d .functor NOT 1, L_0x29eeee0, C4<0>, C4<0>, C4<0>; +L_0x29eea40 .delay (10000,10000,10000) L_0x29eea40/d; +L_0x29eeb00/d .functor AND 1, L_0x29ee8e0, L_0x29eea40, C4<1>, C4<1>; +L_0x29eeb00 .delay (20000,20000,20000) L_0x29eeb00/d; +L_0x29eec10/d .functor AND 1, L_0x29ee440, L_0x29eeee0, C4<1>, C4<1>; +L_0x29eec10 .delay (20000,20000,20000) L_0x29eec10/d; +L_0x29eed60/d .functor OR 1, L_0x29eeb00, L_0x29eec10, C4<0>, C4<0>; +L_0x29eed60 .delay (20000,20000,20000) L_0x29eed60/d; +v0x28c4520_0 .net "S", 0 0, L_0x29eeee0; 1 drivers +v0x28c45e0_0 .alias "in0", 0 0, v0x28c4c70_0; +v0x28c4680_0 .alias "in1", 0 0, v0x28c4ae0_0; +v0x28c4720_0 .net "nS", 0 0, L_0x29eea40; 1 drivers +v0x28c47a0_0 .net "out0", 0 0, L_0x29eeb00; 1 drivers +v0x28c4840_0 .net "out1", 0 0, L_0x29eec10; 1 drivers +v0x28c4920_0 .alias "outfinal", 0 0, v0x28c4ee0_0; +S_0x28c3ee0 .scope module, "mux1" "TwoInMux" 3 185, 3 109, S_0x28c3df0; + .timescale -9 -12; +L_0x29eef80/d .functor NOT 1, L_0x29ef4b0, C4<0>, C4<0>, C4<0>; +L_0x29eef80 .delay (10000,10000,10000) L_0x29eef80/d; +L_0x29ef040/d .functor AND 1, L_0x29eed60, L_0x29eef80, C4<1>, C4<1>; +L_0x29ef040 .delay (20000,20000,20000) L_0x29ef040/d; +L_0x29ef190/d .functor AND 1, L_0x29ee540, L_0x29ef4b0, C4<1>, C4<1>; +L_0x29ef190 .delay (20000,20000,20000) L_0x29ef190/d; +L_0x29ef2e0/d .functor OR 1, L_0x29ef040, L_0x29ef190, C4<0>, C4<0>; +L_0x29ef2e0 .delay (20000,20000,20000) L_0x29ef2e0/d; +v0x28c3fd0_0 .net "S", 0 0, L_0x29ef4b0; 1 drivers +v0x28c4050_0 .alias "in0", 0 0, v0x28c4ee0_0; +v0x28c40f0_0 .alias "in1", 0 0, v0x28c4b90_0; +v0x28c4190_0 .net "nS", 0 0, L_0x29eef80; 1 drivers +v0x28c4210_0 .net "out0", 0 0, L_0x29ef040; 1 drivers +v0x28c42b0_0 .net "out1", 0 0, L_0x29ef190; 1 drivers +v0x28c4390_0 .alias "outfinal", 0 0, v0x28c4e60_0; +S_0x28c28f0 .scope generate, "orbits[5]" "orbits[5]" 3 258, 3 258, S_0x28a2590; + .timescale -9 -12; +P_0x28c2608 .param/l "i" 3 258, +C4<0101>; +S_0x28c2a20 .scope module, "attempt" "OrNorXor" 3 260, 3 165, S_0x28c28f0; + .timescale -9 -12; +L_0x29ef5f0/d .functor NOR 1, L_0x29f0a00, L_0x29f0aa0, C4<0>, C4<0>; +L_0x29ef5f0 .delay (10000,10000,10000) L_0x29ef5f0/d; +L_0x29ef840/d .functor NOT 1, L_0x29ef5f0, C4<0>, C4<0>, C4<0>; +L_0x29ef840 .delay (10000,10000,10000) L_0x29ef840/d; +L_0x29ef970/d .functor NAND 1, L_0x29f0a00, L_0x29f0aa0, C4<1>, C4<1>; +L_0x29ef970 .delay (10000,10000,10000) L_0x29ef970/d; +L_0x29efad0/d .functor NAND 1, L_0x29ef970, L_0x29ef840, C4<1>, C4<1>; +L_0x29efad0 .delay (10000,10000,10000) L_0x29efad0/d; +L_0x29efbe0/d .functor NOT 1, L_0x29efad0, C4<0>, C4<0>, C4<0>; +L_0x29efbe0 .delay (10000,10000,10000) L_0x29efbe0/d; +v0x28c35d0_0 .net "A", 0 0, L_0x29f0a00; 1 drivers +v0x28c3670_0 .net "AnandB", 0 0, L_0x29ef970; 1 drivers +v0x28c3710_0 .net "AnorB", 0 0, L_0x29ef5f0; 1 drivers +v0x28c37c0_0 .net "AorB", 0 0, L_0x29ef840; 1 drivers +v0x28c38a0_0 .net "AxorB", 0 0, L_0x29efbe0; 1 drivers +v0x28c3950_0 .net "B", 0 0, L_0x29f0aa0; 1 drivers +v0x28c3a10_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x28c3a90_0 .net "OrNorXorOut", 0 0, L_0x29f05e0; 1 drivers +v0x28c3b10_0 .net "XorNor", 0 0, L_0x29f0060; 1 drivers +v0x28c3be0_0 .net "nXor", 0 0, L_0x29efad0; 1 drivers +L_0x29f01e0 .part v0x2960210_0, 2, 1; +L_0x29f07b0 .part v0x2960210_0, 0, 1; +S_0x28c3060 .scope module, "mux0" "TwoInMux" 3 184, 3 109, S_0x28c2a20; + .timescale -9 -12; +L_0x29efd40/d .functor NOT 1, L_0x29f01e0, C4<0>, C4<0>, C4<0>; +L_0x29efd40 .delay (10000,10000,10000) L_0x29efd40/d; +L_0x29efe00/d .functor AND 1, L_0x29efbe0, L_0x29efd40, C4<1>, C4<1>; +L_0x29efe00 .delay (20000,20000,20000) L_0x29efe00/d; +L_0x29eff10/d .functor AND 1, L_0x29ef5f0, L_0x29f01e0, C4<1>, C4<1>; +L_0x29eff10 .delay (20000,20000,20000) L_0x29eff10/d; +L_0x29f0060/d .functor OR 1, L_0x29efe00, L_0x29eff10, C4<0>, C4<0>; +L_0x29f0060 .delay (20000,20000,20000) L_0x29f0060/d; +v0x28c3150_0 .net "S", 0 0, L_0x29f01e0; 1 drivers +v0x28c3210_0 .alias "in0", 0 0, v0x28c38a0_0; +v0x28c32b0_0 .alias "in1", 0 0, v0x28c3710_0; +v0x28c3350_0 .net "nS", 0 0, L_0x29efd40; 1 drivers +v0x28c33d0_0 .net "out0", 0 0, L_0x29efe00; 1 drivers +v0x28c3470_0 .net "out1", 0 0, L_0x29eff10; 1 drivers +v0x28c3550_0 .alias "outfinal", 0 0, v0x28c3b10_0; +S_0x28c2b10 .scope module, "mux1" "TwoInMux" 3 185, 3 109, S_0x28c2a20; + .timescale -9 -12; +L_0x29f0280/d .functor NOT 1, L_0x29f07b0, C4<0>, C4<0>, C4<0>; +L_0x29f0280 .delay (10000,10000,10000) L_0x29f0280/d; +L_0x29f0340/d .functor AND 1, L_0x29f0060, L_0x29f0280, C4<1>, C4<1>; +L_0x29f0340 .delay (20000,20000,20000) L_0x29f0340/d; +L_0x29f0490/d .functor AND 1, L_0x29ef840, L_0x29f07b0, C4<1>, C4<1>; +L_0x29f0490 .delay (20000,20000,20000) L_0x29f0490/d; +L_0x29f05e0/d .functor OR 1, L_0x29f0340, L_0x29f0490, C4<0>, C4<0>; +L_0x29f05e0 .delay (20000,20000,20000) L_0x29f05e0/d; +v0x28c2c00_0 .net "S", 0 0, L_0x29f07b0; 1 drivers +v0x28c2c80_0 .alias "in0", 0 0, v0x28c3b10_0; +v0x28c2d20_0 .alias "in1", 0 0, v0x28c37c0_0; +v0x28c2dc0_0 .net "nS", 0 0, L_0x29f0280; 1 drivers +v0x28c2e40_0 .net "out0", 0 0, L_0x29f0340; 1 drivers +v0x28c2ee0_0 .net "out1", 0 0, L_0x29f0490; 1 drivers +v0x28c2fc0_0 .alias "outfinal", 0 0, v0x28c3a90_0; +S_0x28c1520 .scope generate, "orbits[6]" "orbits[6]" 3 258, 3 258, S_0x28a2590; + .timescale -9 -12; +P_0x28c1238 .param/l "i" 3 258, +C4<0110>; +S_0x28c1650 .scope module, "attempt" "OrNorXor" 3 260, 3 165, S_0x28c1520; + .timescale -9 -12; +L_0x29f0b40/d .functor NOR 1, L_0x29f1ce0, L_0x29f1d80, C4<0>, C4<0>; +L_0x29f0b40 .delay (10000,10000,10000) L_0x29f0b40/d; +L_0x29f0c30/d .functor NOT 1, L_0x29f0b40, C4<0>, C4<0>, C4<0>; +L_0x29f0c30 .delay (10000,10000,10000) L_0x29f0c30/d; +L_0x29f0d60/d .functor NAND 1, L_0x29f1ce0, L_0x29f1d80, C4<1>, C4<1>; +L_0x29f0d60 .delay (10000,10000,10000) L_0x29f0d60/d; +L_0x29f0ec0/d .functor NAND 1, L_0x29f0d60, L_0x29f0c30, C4<1>, C4<1>; +L_0x29f0ec0 .delay (10000,10000,10000) L_0x29f0ec0/d; +L_0x29f0fd0/d .functor NOT 1, L_0x29f0ec0, C4<0>, C4<0>, C4<0>; +L_0x29f0fd0 .delay (10000,10000,10000) L_0x29f0fd0/d; +v0x28c2200_0 .net "A", 0 0, L_0x29f1ce0; 1 drivers +v0x28c22a0_0 .net "AnandB", 0 0, L_0x29f0d60; 1 drivers +v0x28c2340_0 .net "AnorB", 0 0, L_0x29f0b40; 1 drivers +v0x28c23f0_0 .net "AorB", 0 0, L_0x29f0c30; 1 drivers +v0x28c24d0_0 .net "AxorB", 0 0, L_0x29f0fd0; 1 drivers +v0x28c2580_0 .net "B", 0 0, L_0x29f1d80; 1 drivers +v0x28c2640_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x28c26c0_0 .net "OrNorXorOut", 0 0, L_0x29f19d0; 1 drivers +v0x28c2740_0 .net "XorNor", 0 0, L_0x29f1450; 1 drivers +v0x28c2810_0 .net "nXor", 0 0, L_0x29f0ec0; 1 drivers +L_0x29f15d0 .part v0x2960210_0, 2, 1; +L_0x29f1ba0 .part v0x2960210_0, 0, 1; +S_0x28c1c90 .scope module, "mux0" "TwoInMux" 3 184, 3 109, S_0x28c1650; + .timescale -9 -12; +L_0x29f1130/d .functor NOT 1, L_0x29f15d0, C4<0>, C4<0>, C4<0>; +L_0x29f1130 .delay (10000,10000,10000) L_0x29f1130/d; +L_0x29f11f0/d .functor AND 1, L_0x29f0fd0, L_0x29f1130, C4<1>, C4<1>; +L_0x29f11f0 .delay (20000,20000,20000) L_0x29f11f0/d; +L_0x29f1300/d .functor AND 1, L_0x29f0b40, L_0x29f15d0, C4<1>, C4<1>; +L_0x29f1300 .delay (20000,20000,20000) L_0x29f1300/d; +L_0x29f1450/d .functor OR 1, L_0x29f11f0, L_0x29f1300, C4<0>, C4<0>; +L_0x29f1450 .delay (20000,20000,20000) L_0x29f1450/d; +v0x28c1d80_0 .net "S", 0 0, L_0x29f15d0; 1 drivers +v0x28c1e40_0 .alias "in0", 0 0, v0x28c24d0_0; +v0x28c1ee0_0 .alias "in1", 0 0, v0x28c2340_0; +v0x28c1f80_0 .net "nS", 0 0, L_0x29f1130; 1 drivers +v0x28c2000_0 .net "out0", 0 0, L_0x29f11f0; 1 drivers +v0x28c20a0_0 .net "out1", 0 0, L_0x29f1300; 1 drivers +v0x28c2180_0 .alias "outfinal", 0 0, v0x28c2740_0; +S_0x28c1740 .scope module, "mux1" "TwoInMux" 3 185, 3 109, S_0x28c1650; + .timescale -9 -12; +L_0x29f1670/d .functor NOT 1, L_0x29f1ba0, C4<0>, C4<0>, C4<0>; +L_0x29f1670 .delay (10000,10000,10000) L_0x29f1670/d; +L_0x29f1730/d .functor AND 1, L_0x29f1450, L_0x29f1670, C4<1>, C4<1>; +L_0x29f1730 .delay (20000,20000,20000) L_0x29f1730/d; +L_0x29f1880/d .functor AND 1, L_0x29f0c30, L_0x29f1ba0, C4<1>, C4<1>; +L_0x29f1880 .delay (20000,20000,20000) L_0x29f1880/d; +L_0x29f19d0/d .functor OR 1, L_0x29f1730, L_0x29f1880, C4<0>, C4<0>; +L_0x29f19d0 .delay (20000,20000,20000) L_0x29f19d0/d; +v0x28c1830_0 .net "S", 0 0, L_0x29f1ba0; 1 drivers +v0x28c18b0_0 .alias "in0", 0 0, v0x28c2740_0; +v0x28c1950_0 .alias "in1", 0 0, v0x28c23f0_0; +v0x28c19f0_0 .net "nS", 0 0, L_0x29f1670; 1 drivers +v0x28c1a70_0 .net "out0", 0 0, L_0x29f1730; 1 drivers +v0x28c1b10_0 .net "out1", 0 0, L_0x29f1880; 1 drivers +v0x28c1bf0_0 .alias "outfinal", 0 0, v0x28c26c0_0; +S_0x28c0150 .scope generate, "orbits[7]" "orbits[7]" 3 258, 3 258, S_0x28a2590; + .timescale -9 -12; +P_0x28bfe68 .param/l "i" 3 258, +C4<0111>; +S_0x28c0280 .scope module, "attempt" "OrNorXor" 3 260, 3 165, S_0x28c0150; + .timescale -9 -12; +L_0x29ec040/d .functor NOR 1, L_0x29f2fe0, L_0x29f1e20, C4<0>, C4<0>; +L_0x29ec040 .delay (10000,10000,10000) L_0x29ec040/d; +L_0x29f1f50/d .functor NOT 1, L_0x29ec040, C4<0>, C4<0>, C4<0>; +L_0x29f1f50 .delay (10000,10000,10000) L_0x29f1f50/d; +L_0x29f2060/d .functor NAND 1, L_0x29f2fe0, L_0x29f1e20, C4<1>, C4<1>; +L_0x29f2060 .delay (10000,10000,10000) L_0x29f2060/d; +L_0x29f21c0/d .functor NAND 1, L_0x29f2060, L_0x29f1f50, C4<1>, C4<1>; +L_0x29f21c0 .delay (10000,10000,10000) L_0x29f21c0/d; +L_0x29f22d0/d .functor NOT 1, L_0x29f21c0, C4<0>, C4<0>, C4<0>; +L_0x29f22d0 .delay (10000,10000,10000) L_0x29f22d0/d; +v0x28c0e30_0 .net "A", 0 0, L_0x29f2fe0; 1 drivers +v0x28c0ed0_0 .net "AnandB", 0 0, L_0x29f2060; 1 drivers +v0x28c0f70_0 .net "AnorB", 0 0, L_0x29ec040; 1 drivers +v0x28c1020_0 .net "AorB", 0 0, L_0x29f1f50; 1 drivers +v0x28c1100_0 .net "AxorB", 0 0, L_0x29f22d0; 1 drivers +v0x28c11b0_0 .net "B", 0 0, L_0x29f1e20; 1 drivers +v0x28c1270_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x28c12f0_0 .net "OrNorXorOut", 0 0, L_0x29f2cd0; 1 drivers +v0x28c1370_0 .net "XorNor", 0 0, L_0x29f2750; 1 drivers +v0x28c1440_0 .net "nXor", 0 0, L_0x29f21c0; 1 drivers +L_0x29f28d0 .part v0x2960210_0, 2, 1; +L_0x29f2ea0 .part v0x2960210_0, 0, 1; +S_0x28c08c0 .scope module, "mux0" "TwoInMux" 3 184, 3 109, S_0x28c0280; + .timescale -9 -12; +L_0x29f2430/d .functor NOT 1, L_0x29f28d0, C4<0>, C4<0>, C4<0>; +L_0x29f2430 .delay (10000,10000,10000) L_0x29f2430/d; +L_0x29f24f0/d .functor AND 1, L_0x29f22d0, L_0x29f2430, C4<1>, C4<1>; +L_0x29f24f0 .delay (20000,20000,20000) L_0x29f24f0/d; +L_0x29f2600/d .functor AND 1, L_0x29ec040, L_0x29f28d0, C4<1>, C4<1>; +L_0x29f2600 .delay (20000,20000,20000) L_0x29f2600/d; +L_0x29f2750/d .functor OR 1, L_0x29f24f0, L_0x29f2600, C4<0>, C4<0>; +L_0x29f2750 .delay (20000,20000,20000) L_0x29f2750/d; +v0x28c09b0_0 .net "S", 0 0, L_0x29f28d0; 1 drivers +v0x28c0a70_0 .alias "in0", 0 0, v0x28c1100_0; +v0x28c0b10_0 .alias "in1", 0 0, v0x28c0f70_0; +v0x28c0bb0_0 .net "nS", 0 0, L_0x29f2430; 1 drivers +v0x28c0c30_0 .net "out0", 0 0, L_0x29f24f0; 1 drivers +v0x28c0cd0_0 .net "out1", 0 0, L_0x29f2600; 1 drivers +v0x28c0db0_0 .alias "outfinal", 0 0, v0x28c1370_0; +S_0x28c0370 .scope module, "mux1" "TwoInMux" 3 185, 3 109, S_0x28c0280; + .timescale -9 -12; +L_0x29f2970/d .functor NOT 1, L_0x29f2ea0, C4<0>, C4<0>, C4<0>; +L_0x29f2970 .delay (10000,10000,10000) L_0x29f2970/d; +L_0x29f2a30/d .functor AND 1, L_0x29f2750, L_0x29f2970, C4<1>, C4<1>; +L_0x29f2a30 .delay (20000,20000,20000) L_0x29f2a30/d; +L_0x29f2b80/d .functor AND 1, L_0x29f1f50, L_0x29f2ea0, C4<1>, C4<1>; +L_0x29f2b80 .delay (20000,20000,20000) L_0x29f2b80/d; +L_0x29f2cd0/d .functor OR 1, L_0x29f2a30, L_0x29f2b80, C4<0>, C4<0>; +L_0x29f2cd0 .delay (20000,20000,20000) L_0x29f2cd0/d; +v0x28c0460_0 .net "S", 0 0, L_0x29f2ea0; 1 drivers +v0x28c04e0_0 .alias "in0", 0 0, v0x28c1370_0; +v0x28c0580_0 .alias "in1", 0 0, v0x28c1020_0; +v0x28c0620_0 .net "nS", 0 0, L_0x29f2970; 1 drivers +v0x28c06a0_0 .net "out0", 0 0, L_0x29f2a30; 1 drivers +v0x28c0740_0 .net "out1", 0 0, L_0x29f2b80; 1 drivers +v0x28c0820_0 .alias "outfinal", 0 0, v0x28c12f0_0; +S_0x28bed80 .scope generate, "orbits[8]" "orbits[8]" 3 258, 3 258, S_0x28a2590; + .timescale -9 -12; +P_0x28bea98 .param/l "i" 3 258, +C4<01000>; +S_0x28beeb0 .scope module, "attempt" "OrNorXor" 3 260, 3 165, S_0x28bed80; + .timescale -9 -12; +L_0x29f3130/d .functor NOR 1, L_0x29f3080, L_0x29f4390, C4<0>, C4<0>; +L_0x29f3130 .delay (10000,10000,10000) L_0x29f3130/d; +L_0x29f3220/d .functor NOT 1, L_0x29f3130, C4<0>, C4<0>, C4<0>; +L_0x29f3220 .delay (10000,10000,10000) L_0x29f3220/d; +L_0x29f3350/d .functor NAND 1, L_0x29f3080, L_0x29f4390, C4<1>, C4<1>; +L_0x29f3350 .delay (10000,10000,10000) L_0x29f3350/d; +L_0x29f34b0/d .functor NAND 1, L_0x29f3350, L_0x29f3220, C4<1>, C4<1>; +L_0x29f34b0 .delay (10000,10000,10000) L_0x29f34b0/d; +L_0x29f35c0/d .functor NOT 1, L_0x29f34b0, C4<0>, C4<0>, C4<0>; +L_0x29f35c0 .delay (10000,10000,10000) L_0x29f35c0/d; +v0x28bfa60_0 .net "A", 0 0, L_0x29f3080; 1 drivers +v0x28bfb00_0 .net "AnandB", 0 0, L_0x29f3350; 1 drivers +v0x28bfba0_0 .net "AnorB", 0 0, L_0x29f3130; 1 drivers +v0x28bfc50_0 .net "AorB", 0 0, L_0x29f3220; 1 drivers +v0x28bfd30_0 .net "AxorB", 0 0, L_0x29f35c0; 1 drivers +v0x28bfde0_0 .net "B", 0 0, L_0x29f4390; 1 drivers +v0x28bfea0_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x28bff20_0 .net "OrNorXorOut", 0 0, L_0x29f3fc0; 1 drivers +v0x28bffa0_0 .net "XorNor", 0 0, L_0x29f3a40; 1 drivers +v0x28c0070_0 .net "nXor", 0 0, L_0x29f34b0; 1 drivers +L_0x29f3bc0 .part v0x2960210_0, 2, 1; +L_0x29f4190 .part v0x2960210_0, 0, 1; +S_0x28bf4f0 .scope module, "mux0" "TwoInMux" 3 184, 3 109, S_0x28beeb0; + .timescale -9 -12; +L_0x29f3720/d .functor NOT 1, L_0x29f3bc0, C4<0>, C4<0>, C4<0>; +L_0x29f3720 .delay (10000,10000,10000) L_0x29f3720/d; +L_0x29f37e0/d .functor AND 1, L_0x29f35c0, L_0x29f3720, C4<1>, C4<1>; +L_0x29f37e0 .delay (20000,20000,20000) L_0x29f37e0/d; +L_0x29f38f0/d .functor AND 1, L_0x29f3130, L_0x29f3bc0, C4<1>, C4<1>; +L_0x29f38f0 .delay (20000,20000,20000) L_0x29f38f0/d; +L_0x29f3a40/d .functor OR 1, L_0x29f37e0, L_0x29f38f0, C4<0>, C4<0>; +L_0x29f3a40 .delay (20000,20000,20000) L_0x29f3a40/d; +v0x28bf5e0_0 .net "S", 0 0, L_0x29f3bc0; 1 drivers +v0x28bf6a0_0 .alias "in0", 0 0, v0x28bfd30_0; +v0x28bf740_0 .alias "in1", 0 0, v0x28bfba0_0; +v0x28bf7e0_0 .net "nS", 0 0, L_0x29f3720; 1 drivers +v0x28bf860_0 .net "out0", 0 0, L_0x29f37e0; 1 drivers +v0x28bf900_0 .net "out1", 0 0, L_0x29f38f0; 1 drivers +v0x28bf9e0_0 .alias "outfinal", 0 0, v0x28bffa0_0; +S_0x28befa0 .scope module, "mux1" "TwoInMux" 3 185, 3 109, S_0x28beeb0; + .timescale -9 -12; +L_0x29f3c60/d .functor NOT 1, L_0x29f4190, C4<0>, C4<0>, C4<0>; +L_0x29f3c60 .delay (10000,10000,10000) L_0x29f3c60/d; +L_0x29f3d20/d .functor AND 1, L_0x29f3a40, L_0x29f3c60, C4<1>, C4<1>; +L_0x29f3d20 .delay (20000,20000,20000) L_0x29f3d20/d; +L_0x29f3e70/d .functor AND 1, L_0x29f3220, L_0x29f4190, C4<1>, C4<1>; +L_0x29f3e70 .delay (20000,20000,20000) L_0x29f3e70/d; +L_0x29f3fc0/d .functor OR 1, L_0x29f3d20, L_0x29f3e70, C4<0>, C4<0>; +L_0x29f3fc0 .delay (20000,20000,20000) L_0x29f3fc0/d; +v0x28bf090_0 .net "S", 0 0, L_0x29f4190; 1 drivers +v0x28bf110_0 .alias "in0", 0 0, v0x28bffa0_0; +v0x28bf1b0_0 .alias "in1", 0 0, v0x28bfc50_0; +v0x28bf250_0 .net "nS", 0 0, L_0x29f3c60; 1 drivers +v0x28bf2d0_0 .net "out0", 0 0, L_0x29f3d20; 1 drivers +v0x28bf370_0 .net "out1", 0 0, L_0x29f3e70; 1 drivers +v0x28bf450_0 .alias "outfinal", 0 0, v0x28bff20_0; +S_0x28bd9b0 .scope generate, "orbits[9]" "orbits[9]" 3 258, 3 258, S_0x28a2590; + .timescale -9 -12; +P_0x28bd6c8 .param/l "i" 3 258, +C4<01001>; +S_0x28bdae0 .scope module, "attempt" "OrNorXor" 3 260, 3 165, S_0x28bd9b0; + .timescale -9 -12; +L_0x29f42d0/d .functor NOR 1, L_0x29f55e0, L_0x29f4430, C4<0>, C4<0>; +L_0x29f42d0 .delay (10000,10000,10000) L_0x29f42d0/d; +L_0x29f4550/d .functor NOT 1, L_0x29f42d0, C4<0>, C4<0>, C4<0>; +L_0x29f4550 .delay (10000,10000,10000) L_0x29f4550/d; +L_0x29f4660/d .functor NAND 1, L_0x29f55e0, L_0x29f4430, C4<1>, C4<1>; +L_0x29f4660 .delay (10000,10000,10000) L_0x29f4660/d; +L_0x29f47c0/d .functor NAND 1, L_0x29f4660, L_0x29f4550, C4<1>, C4<1>; +L_0x29f47c0 .delay (10000,10000,10000) L_0x29f47c0/d; +L_0x29f48d0/d .functor NOT 1, L_0x29f47c0, C4<0>, C4<0>, C4<0>; +L_0x29f48d0 .delay (10000,10000,10000) L_0x29f48d0/d; +v0x28be690_0 .net "A", 0 0, L_0x29f55e0; 1 drivers +v0x28be730_0 .net "AnandB", 0 0, L_0x29f4660; 1 drivers +v0x28be7d0_0 .net "AnorB", 0 0, L_0x29f42d0; 1 drivers +v0x28be880_0 .net "AorB", 0 0, L_0x29f4550; 1 drivers +v0x28be960_0 .net "AxorB", 0 0, L_0x29f48d0; 1 drivers +v0x28bea10_0 .net "B", 0 0, L_0x29f4430; 1 drivers +v0x28bead0_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x28beb50_0 .net "OrNorXorOut", 0 0, L_0x29f52d0; 1 drivers +v0x28bebd0_0 .net "XorNor", 0 0, L_0x29f4d50; 1 drivers +v0x28beca0_0 .net "nXor", 0 0, L_0x29f47c0; 1 drivers +L_0x29f4ed0 .part v0x2960210_0, 2, 1; +L_0x29f54a0 .part v0x2960210_0, 0, 1; +S_0x28be120 .scope module, "mux0" "TwoInMux" 3 184, 3 109, S_0x28bdae0; + .timescale -9 -12; +L_0x29f4a30/d .functor NOT 1, L_0x29f4ed0, C4<0>, C4<0>, C4<0>; +L_0x29f4a30 .delay (10000,10000,10000) L_0x29f4a30/d; +L_0x29f4af0/d .functor AND 1, L_0x29f48d0, L_0x29f4a30, C4<1>, C4<1>; +L_0x29f4af0 .delay (20000,20000,20000) L_0x29f4af0/d; +L_0x29f4c00/d .functor AND 1, L_0x29f42d0, L_0x29f4ed0, C4<1>, C4<1>; +L_0x29f4c00 .delay (20000,20000,20000) L_0x29f4c00/d; +L_0x29f4d50/d .functor OR 1, L_0x29f4af0, L_0x29f4c00, C4<0>, C4<0>; +L_0x29f4d50 .delay (20000,20000,20000) L_0x29f4d50/d; +v0x28be210_0 .net "S", 0 0, L_0x29f4ed0; 1 drivers +v0x28be2d0_0 .alias "in0", 0 0, v0x28be960_0; +v0x28be370_0 .alias "in1", 0 0, v0x28be7d0_0; +v0x28be410_0 .net "nS", 0 0, L_0x29f4a30; 1 drivers +v0x28be490_0 .net "out0", 0 0, L_0x29f4af0; 1 drivers +v0x28be530_0 .net "out1", 0 0, L_0x29f4c00; 1 drivers +v0x28be610_0 .alias "outfinal", 0 0, v0x28bebd0_0; +S_0x28bdbd0 .scope module, "mux1" "TwoInMux" 3 185, 3 109, S_0x28bdae0; + .timescale -9 -12; +L_0x29f4f70/d .functor NOT 1, L_0x29f54a0, C4<0>, C4<0>, C4<0>; +L_0x29f4f70 .delay (10000,10000,10000) L_0x29f4f70/d; +L_0x29f5030/d .functor AND 1, L_0x29f4d50, L_0x29f4f70, C4<1>, C4<1>; +L_0x29f5030 .delay (20000,20000,20000) L_0x29f5030/d; +L_0x29f5180/d .functor AND 1, L_0x29f4550, L_0x29f54a0, C4<1>, C4<1>; +L_0x29f5180 .delay (20000,20000,20000) L_0x29f5180/d; +L_0x29f52d0/d .functor OR 1, L_0x29f5030, L_0x29f5180, C4<0>, C4<0>; +L_0x29f52d0 .delay (20000,20000,20000) L_0x29f52d0/d; +v0x28bdcc0_0 .net "S", 0 0, L_0x29f54a0; 1 drivers +v0x28bdd40_0 .alias "in0", 0 0, v0x28bebd0_0; +v0x28bdde0_0 .alias "in1", 0 0, v0x28be880_0; +v0x28bde80_0 .net "nS", 0 0, L_0x29f4f70; 1 drivers +v0x28bdf00_0 .net "out0", 0 0, L_0x29f5030; 1 drivers +v0x28bdfa0_0 .net "out1", 0 0, L_0x29f5180; 1 drivers +v0x28be080_0 .alias "outfinal", 0 0, v0x28beb50_0; +S_0x28bc5e0 .scope generate, "orbits[10]" "orbits[10]" 3 258, 3 258, S_0x28a2590; + .timescale -9 -12; +P_0x28bc2f8 .param/l "i" 3 258, +C4<01010>; +S_0x28bc710 .scope module, "attempt" "OrNorXor" 3 260, 3 165, S_0x28bc5e0; + .timescale -9 -12; +L_0x29f5760/d .functor NOR 1, L_0x29f5680, L_0x29f68b0, C4<0>, C4<0>; +L_0x29f5760 .delay (10000,10000,10000) L_0x29f5760/d; +L_0x29f5850/d .functor NOT 1, L_0x29f5760, C4<0>, C4<0>, C4<0>; +L_0x29f5850 .delay (10000,10000,10000) L_0x29f5850/d; +L_0x29f5960/d .functor NAND 1, L_0x29f5680, L_0x29f68b0, C4<1>, C4<1>; +L_0x29f5960 .delay (10000,10000,10000) L_0x29f5960/d; +L_0x29f5ac0/d .functor NAND 1, L_0x29f5960, L_0x29f5850, C4<1>, C4<1>; +L_0x29f5ac0 .delay (10000,10000,10000) L_0x29f5ac0/d; +L_0x29f5bd0/d .functor NOT 1, L_0x29f5ac0, C4<0>, C4<0>, C4<0>; +L_0x29f5bd0 .delay (10000,10000,10000) L_0x29f5bd0/d; +v0x28bd2c0_0 .net "A", 0 0, L_0x29f5680; 1 drivers +v0x28bd360_0 .net "AnandB", 0 0, L_0x29f5960; 1 drivers +v0x28bd400_0 .net "AnorB", 0 0, L_0x29f5760; 1 drivers +v0x28bd4b0_0 .net "AorB", 0 0, L_0x29f5850; 1 drivers +v0x28bd590_0 .net "AxorB", 0 0, L_0x29f5bd0; 1 drivers +v0x28bd640_0 .net "B", 0 0, L_0x29f68b0; 1 drivers +v0x28bd700_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x28bd780_0 .net "OrNorXorOut", 0 0, L_0x29f64f0; 1 drivers +v0x28bd800_0 .net "XorNor", 0 0, L_0x29f6010; 1 drivers +v0x28bd8d0_0 .net "nXor", 0 0, L_0x29f5ac0; 1 drivers +L_0x29f6150 .part v0x2960210_0, 2, 1; +L_0x29f6680 .part v0x2960210_0, 0, 1; +S_0x28bcd50 .scope module, "mux0" "TwoInMux" 3 184, 3 109, S_0x28bc710; + .timescale -9 -12; +L_0x29f5d30/d .functor NOT 1, L_0x29f6150, C4<0>, C4<0>, C4<0>; +L_0x29f5d30 .delay (10000,10000,10000) L_0x29f5d30/d; +L_0x29f5df0/d .functor AND 1, L_0x29f5bd0, L_0x29f5d30, C4<1>, C4<1>; +L_0x29f5df0 .delay (20000,20000,20000) L_0x29f5df0/d; +L_0x29f5f00/d .functor AND 1, L_0x29f5760, L_0x29f6150, C4<1>, C4<1>; +L_0x29f5f00 .delay (20000,20000,20000) L_0x29f5f00/d; +L_0x29f6010/d .functor OR 1, L_0x29f5df0, L_0x29f5f00, C4<0>, C4<0>; +L_0x29f6010 .delay (20000,20000,20000) L_0x29f6010/d; +v0x28bce40_0 .net "S", 0 0, L_0x29f6150; 1 drivers +v0x28bcf00_0 .alias "in0", 0 0, v0x28bd590_0; +v0x28bcfa0_0 .alias "in1", 0 0, v0x28bd400_0; +v0x28bd040_0 .net "nS", 0 0, L_0x29f5d30; 1 drivers +v0x28bd0c0_0 .net "out0", 0 0, L_0x29f5df0; 1 drivers +v0x28bd160_0 .net "out1", 0 0, L_0x29f5f00; 1 drivers +v0x28bd240_0 .alias "outfinal", 0 0, v0x28bd800_0; +S_0x28bc800 .scope module, "mux1" "TwoInMux" 3 185, 3 109, S_0x28bc710; + .timescale -9 -12; +L_0x29f61f0/d .functor NOT 1, L_0x29f6680, C4<0>, C4<0>, C4<0>; +L_0x29f61f0 .delay (10000,10000,10000) L_0x29f61f0/d; +L_0x29f6290/d .functor AND 1, L_0x29f6010, L_0x29f61f0, C4<1>, C4<1>; +L_0x29f6290 .delay (20000,20000,20000) L_0x29f6290/d; +L_0x29f63c0/d .functor AND 1, L_0x29f5850, L_0x29f6680, C4<1>, C4<1>; +L_0x29f63c0 .delay (20000,20000,20000) L_0x29f63c0/d; +L_0x29f64f0/d .functor OR 1, L_0x29f6290, L_0x29f63c0, C4<0>, C4<0>; +L_0x29f64f0 .delay (20000,20000,20000) L_0x29f64f0/d; +v0x28bc8f0_0 .net "S", 0 0, L_0x29f6680; 1 drivers +v0x28bc970_0 .alias "in0", 0 0, v0x28bd800_0; +v0x28bca10_0 .alias "in1", 0 0, v0x28bd4b0_0; +v0x28bcab0_0 .net "nS", 0 0, L_0x29f61f0; 1 drivers +v0x28bcb30_0 .net "out0", 0 0, L_0x29f6290; 1 drivers +v0x28bcbd0_0 .net "out1", 0 0, L_0x29f63c0; 1 drivers +v0x28bccb0_0 .alias "outfinal", 0 0, v0x28bd780_0; +S_0x28bb210 .scope generate, "orbits[11]" "orbits[11]" 3 258, 3 258, S_0x28a2590; + .timescale -9 -12; +P_0x28baf28 .param/l "i" 3 258, +C4<01011>; +S_0x28bb340 .scope module, "attempt" "OrNorXor" 3 260, 3 165, S_0x28bb210; + .timescale -9 -12; +L_0x29f67c0/d .functor NOR 1, L_0x29f7980, L_0x29f6950, C4<0>, C4<0>; +L_0x29f67c0 .delay (10000,10000,10000) L_0x29f67c0/d; +L_0x29f6a50/d .functor NOT 1, L_0x29f67c0, C4<0>, C4<0>, C4<0>; +L_0x29f6a50 .delay (10000,10000,10000) L_0x29f6a50/d; +L_0x29f6b00/d .functor NAND 1, L_0x29f7980, L_0x29f6950, C4<1>, C4<1>; +L_0x29f6b00 .delay (10000,10000,10000) L_0x29f6b00/d; +L_0x29f6c40/d .functor NAND 1, L_0x29f6b00, L_0x29f6a50, C4<1>, C4<1>; +L_0x29f6c40 .delay (10000,10000,10000) L_0x29f6c40/d; +L_0x29f6d30/d .functor NOT 1, L_0x29f6c40, C4<0>, C4<0>, C4<0>; +L_0x29f6d30 .delay (10000,10000,10000) L_0x29f6d30/d; +v0x28bbef0_0 .net "A", 0 0, L_0x29f7980; 1 drivers +v0x28bbf90_0 .net "AnandB", 0 0, L_0x29f6b00; 1 drivers +v0x28bc030_0 .net "AnorB", 0 0, L_0x29f67c0; 1 drivers +v0x28bc0e0_0 .net "AorB", 0 0, L_0x29f6a50; 1 drivers +v0x28bc1c0_0 .net "AxorB", 0 0, L_0x29f6d30; 1 drivers +v0x28bc270_0 .net "B", 0 0, L_0x29f6950; 1 drivers +v0x28bc330_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x28bc3b0_0 .net "OrNorXorOut", 0 0, L_0x29f7670; 1 drivers +v0x28bc430_0 .net "XorNor", 0 0, L_0x29f7130; 1 drivers +v0x28bc500_0 .net "nXor", 0 0, L_0x29f6c40; 1 drivers +L_0x29f7270 .part v0x2960210_0, 2, 1; +L_0x29f7840 .part v0x2960210_0, 0, 1; +S_0x28bb980 .scope module, "mux0" "TwoInMux" 3 184, 3 109, S_0x28bb340; + .timescale -9 -12; +L_0x29f6e70/d .functor NOT 1, L_0x29f7270, C4<0>, C4<0>, C4<0>; +L_0x29f6e70 .delay (10000,10000,10000) L_0x29f6e70/d; +L_0x29f6f10/d .functor AND 1, L_0x29f6d30, L_0x29f6e70, C4<1>, C4<1>; +L_0x29f6f10 .delay (20000,20000,20000) L_0x29f6f10/d; +L_0x29f7000/d .functor AND 1, L_0x29f67c0, L_0x29f7270, C4<1>, C4<1>; +L_0x29f7000 .delay (20000,20000,20000) L_0x29f7000/d; +L_0x29f7130/d .functor OR 1, L_0x29f6f10, L_0x29f7000, C4<0>, C4<0>; +L_0x29f7130 .delay (20000,20000,20000) L_0x29f7130/d; +v0x28bba70_0 .net "S", 0 0, L_0x29f7270; 1 drivers +v0x28bbb30_0 .alias "in0", 0 0, v0x28bc1c0_0; +v0x28bbbd0_0 .alias "in1", 0 0, v0x28bc030_0; +v0x28bbc70_0 .net "nS", 0 0, L_0x29f6e70; 1 drivers +v0x28bbcf0_0 .net "out0", 0 0, L_0x29f6f10; 1 drivers +v0x28bbd90_0 .net "out1", 0 0, L_0x29f7000; 1 drivers +v0x28bbe70_0 .alias "outfinal", 0 0, v0x28bc430_0; +S_0x28bb430 .scope module, "mux1" "TwoInMux" 3 185, 3 109, S_0x28bb340; + .timescale -9 -12; +L_0x29f7310/d .functor NOT 1, L_0x29f7840, C4<0>, C4<0>, C4<0>; +L_0x29f7310 .delay (10000,10000,10000) L_0x29f7310/d; +L_0x29f73d0/d .functor AND 1, L_0x29f7130, L_0x29f7310, C4<1>, C4<1>; +L_0x29f73d0 .delay (20000,20000,20000) L_0x29f73d0/d; +L_0x29f7520/d .functor AND 1, L_0x29f6a50, L_0x29f7840, C4<1>, C4<1>; +L_0x29f7520 .delay (20000,20000,20000) L_0x29f7520/d; +L_0x29f7670/d .functor OR 1, L_0x29f73d0, L_0x29f7520, C4<0>, C4<0>; +L_0x29f7670 .delay (20000,20000,20000) L_0x29f7670/d; +v0x28bb520_0 .net "S", 0 0, L_0x29f7840; 1 drivers +v0x28bb5a0_0 .alias "in0", 0 0, v0x28bc430_0; +v0x28bb640_0 .alias "in1", 0 0, v0x28bc0e0_0; +v0x28bb6e0_0 .net "nS", 0 0, L_0x29f7310; 1 drivers +v0x28bb760_0 .net "out0", 0 0, L_0x29f73d0; 1 drivers +v0x28bb800_0 .net "out1", 0 0, L_0x29f7520; 1 drivers +v0x28bb8e0_0 .alias "outfinal", 0 0, v0x28bc3b0_0; +S_0x28b9e40 .scope generate, "orbits[12]" "orbits[12]" 3 258, 3 258, S_0x28a2590; + .timescale -9 -12; +P_0x28b9b58 .param/l "i" 3 258, +C4<01100>; +S_0x28b9f70 .scope module, "attempt" "OrNorXor" 3 260, 3 165, S_0x28b9e40; + .timescale -9 -12; +L_0x29f69f0/d .functor NOR 1, L_0x29f7a20, L_0x29f8d90, C4<0>, C4<0>; +L_0x29f69f0 .delay (10000,10000,10000) L_0x29f69f0/d; +L_0x29f7bc0/d .functor NOT 1, L_0x29f69f0, C4<0>, C4<0>, C4<0>; +L_0x29f7bc0 .delay (10000,10000,10000) L_0x29f7bc0/d; +L_0x29f7cf0/d .functor NAND 1, L_0x29f7a20, L_0x29f8d90, C4<1>, C4<1>; +L_0x29f7cf0 .delay (10000,10000,10000) L_0x29f7cf0/d; +L_0x29f7e50/d .functor NAND 1, L_0x29f7cf0, L_0x29f7bc0, C4<1>, C4<1>; +L_0x29f7e50 .delay (10000,10000,10000) L_0x29f7e50/d; +L_0x29f7f60/d .functor NOT 1, L_0x29f7e50, C4<0>, C4<0>, C4<0>; +L_0x29f7f60 .delay (10000,10000,10000) L_0x29f7f60/d; +v0x28bab20_0 .net "A", 0 0, L_0x29f7a20; 1 drivers +v0x28babc0_0 .net "AnandB", 0 0, L_0x29f7cf0; 1 drivers +v0x28bac60_0 .net "AnorB", 0 0, L_0x29f69f0; 1 drivers +v0x28bad10_0 .net "AorB", 0 0, L_0x29f7bc0; 1 drivers +v0x28badf0_0 .net "AxorB", 0 0, L_0x29f7f60; 1 drivers +v0x28baea0_0 .net "B", 0 0, L_0x29f8d90; 1 drivers +v0x28baf60_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x28bafe0_0 .net "OrNorXorOut", 0 0, L_0x29f8960; 1 drivers +v0x28bb060_0 .net "XorNor", 0 0, L_0x29f83e0; 1 drivers +v0x28bb130_0 .net "nXor", 0 0, L_0x29f7e50; 1 drivers +L_0x29f8560 .part v0x2960210_0, 2, 1; +L_0x29f8b30 .part v0x2960210_0, 0, 1; +S_0x28ba5b0 .scope module, "mux0" "TwoInMux" 3 184, 3 109, S_0x28b9f70; + .timescale -9 -12; +L_0x29f80c0/d .functor NOT 1, L_0x29f8560, C4<0>, C4<0>, C4<0>; +L_0x29f80c0 .delay (10000,10000,10000) L_0x29f80c0/d; +L_0x29f8180/d .functor AND 1, L_0x29f7f60, L_0x29f80c0, C4<1>, C4<1>; +L_0x29f8180 .delay (20000,20000,20000) L_0x29f8180/d; +L_0x29f8290/d .functor AND 1, L_0x29f69f0, L_0x29f8560, C4<1>, C4<1>; +L_0x29f8290 .delay (20000,20000,20000) L_0x29f8290/d; +L_0x29f83e0/d .functor OR 1, L_0x29f8180, L_0x29f8290, C4<0>, C4<0>; +L_0x29f83e0 .delay (20000,20000,20000) L_0x29f83e0/d; +v0x28ba6a0_0 .net "S", 0 0, L_0x29f8560; 1 drivers +v0x28ba760_0 .alias "in0", 0 0, v0x28badf0_0; +v0x28ba800_0 .alias "in1", 0 0, v0x28bac60_0; +v0x28ba8a0_0 .net "nS", 0 0, L_0x29f80c0; 1 drivers +v0x28ba920_0 .net "out0", 0 0, L_0x29f8180; 1 drivers +v0x28ba9c0_0 .net "out1", 0 0, L_0x29f8290; 1 drivers +v0x28baaa0_0 .alias "outfinal", 0 0, v0x28bb060_0; +S_0x28ba060 .scope module, "mux1" "TwoInMux" 3 185, 3 109, S_0x28b9f70; + .timescale -9 -12; +L_0x29f8600/d .functor NOT 1, L_0x29f8b30, C4<0>, C4<0>, C4<0>; +L_0x29f8600 .delay (10000,10000,10000) L_0x29f8600/d; +L_0x29f86c0/d .functor AND 1, L_0x29f83e0, L_0x29f8600, C4<1>, C4<1>; +L_0x29f86c0 .delay (20000,20000,20000) L_0x29f86c0/d; +L_0x29f8810/d .functor AND 1, L_0x29f7bc0, L_0x29f8b30, C4<1>, C4<1>; +L_0x29f8810 .delay (20000,20000,20000) L_0x29f8810/d; +L_0x29f8960/d .functor OR 1, L_0x29f86c0, L_0x29f8810, C4<0>, C4<0>; +L_0x29f8960 .delay (20000,20000,20000) L_0x29f8960/d; +v0x28ba150_0 .net "S", 0 0, L_0x29f8b30; 1 drivers +v0x28ba1d0_0 .alias "in0", 0 0, v0x28bb060_0; +v0x28ba270_0 .alias "in1", 0 0, v0x28bad10_0; +v0x28ba310_0 .net "nS", 0 0, L_0x29f8600; 1 drivers +v0x28ba390_0 .net "out0", 0 0, L_0x29f86c0; 1 drivers +v0x28ba430_0 .net "out1", 0 0, L_0x29f8810; 1 drivers +v0x28ba510_0 .alias "outfinal", 0 0, v0x28bafe0_0; +S_0x28b8a70 .scope generate, "orbits[13]" "orbits[13]" 3 258, 3 258, S_0x28a2590; + .timescale -9 -12; +P_0x28b8788 .param/l "i" 3 258, +C4<01101>; +S_0x28b8ba0 .scope module, "attempt" "OrNorXor" 3 260, 3 165, S_0x28b8a70; + .timescale -9 -12; +L_0x29f7ac0/d .functor NOR 1, L_0x29f08f0, L_0x29f8e30, C4<0>, C4<0>; +L_0x29f7ac0 .delay (10000,10000,10000) L_0x29f7ac0/d; +L_0x29f8d00/d .functor NOT 1, L_0x29f7ac0, C4<0>, C4<0>, C4<0>; +L_0x29f8d00 .delay (10000,10000,10000) L_0x29f8d00/d; +L_0x29f9010/d .functor NAND 1, L_0x29f08f0, L_0x29f8e30, C4<1>, C4<1>; +L_0x29f9010 .delay (10000,10000,10000) L_0x29f9010/d; +L_0x29f9170/d .functor NAND 1, L_0x29f9010, L_0x29f8d00, C4<1>, C4<1>; +L_0x29f9170 .delay (10000,10000,10000) L_0x29f9170/d; +L_0x29f9280/d .functor NOT 1, L_0x29f9170, C4<0>, C4<0>, C4<0>; +L_0x29f9280 .delay (10000,10000,10000) L_0x29f9280/d; +v0x28b9750_0 .net "A", 0 0, L_0x29f08f0; 1 drivers +v0x28b97f0_0 .net "AnandB", 0 0, L_0x29f9010; 1 drivers +v0x28b9890_0 .net "AnorB", 0 0, L_0x29f7ac0; 1 drivers +v0x28b9940_0 .net "AorB", 0 0, L_0x29f8d00; 1 drivers +v0x28b9a20_0 .net "AxorB", 0 0, L_0x29f9280; 1 drivers +v0x28b9ad0_0 .net "B", 0 0, L_0x29f8e30; 1 drivers +v0x28b9b90_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x28b9c10_0 .net "OrNorXorOut", 0 0, L_0x29f9c80; 1 drivers +v0x28b9c90_0 .net "XorNor", 0 0, L_0x29f9700; 1 drivers +v0x28b9d60_0 .net "nXor", 0 0, L_0x29f9170; 1 drivers +L_0x29f9880 .part v0x2960210_0, 2, 1; +L_0x29f9e50 .part v0x2960210_0, 0, 1; +S_0x28b91e0 .scope module, "mux0" "TwoInMux" 3 184, 3 109, S_0x28b8ba0; + .timescale -9 -12; +L_0x29f93e0/d .functor NOT 1, L_0x29f9880, C4<0>, C4<0>, C4<0>; +L_0x29f93e0 .delay (10000,10000,10000) L_0x29f93e0/d; +L_0x29f94a0/d .functor AND 1, L_0x29f9280, L_0x29f93e0, C4<1>, C4<1>; +L_0x29f94a0 .delay (20000,20000,20000) L_0x29f94a0/d; +L_0x29f95b0/d .functor AND 1, L_0x29f7ac0, L_0x29f9880, C4<1>, C4<1>; +L_0x29f95b0 .delay (20000,20000,20000) L_0x29f95b0/d; +L_0x29f9700/d .functor OR 1, L_0x29f94a0, L_0x29f95b0, C4<0>, C4<0>; +L_0x29f9700 .delay (20000,20000,20000) L_0x29f9700/d; +v0x28b92d0_0 .net "S", 0 0, L_0x29f9880; 1 drivers +v0x28b9390_0 .alias "in0", 0 0, v0x28b9a20_0; +v0x28b9430_0 .alias "in1", 0 0, v0x28b9890_0; +v0x28b94d0_0 .net "nS", 0 0, L_0x29f93e0; 1 drivers +v0x28b9550_0 .net "out0", 0 0, L_0x29f94a0; 1 drivers +v0x28b95f0_0 .net "out1", 0 0, L_0x29f95b0; 1 drivers +v0x28b96d0_0 .alias "outfinal", 0 0, v0x28b9c90_0; +S_0x28b8c90 .scope module, "mux1" "TwoInMux" 3 185, 3 109, S_0x28b8ba0; + .timescale -9 -12; +L_0x29f9920/d .functor NOT 1, L_0x29f9e50, C4<0>, C4<0>, C4<0>; +L_0x29f9920 .delay (10000,10000,10000) L_0x29f9920/d; +L_0x29f99e0/d .functor AND 1, L_0x29f9700, L_0x29f9920, C4<1>, C4<1>; +L_0x29f99e0 .delay (20000,20000,20000) L_0x29f99e0/d; +L_0x29f9b30/d .functor AND 1, L_0x29f8d00, L_0x29f9e50, C4<1>, C4<1>; +L_0x29f9b30 .delay (20000,20000,20000) L_0x29f9b30/d; +L_0x29f9c80/d .functor OR 1, L_0x29f99e0, L_0x29f9b30, C4<0>, C4<0>; +L_0x29f9c80 .delay (20000,20000,20000) L_0x29f9c80/d; +v0x28b8d80_0 .net "S", 0 0, L_0x29f9e50; 1 drivers +v0x28b8e00_0 .alias "in0", 0 0, v0x28b9c90_0; +v0x28b8ea0_0 .alias "in1", 0 0, v0x28b9940_0; +v0x28b8f40_0 .net "nS", 0 0, L_0x29f9920; 1 drivers +v0x28b8fc0_0 .net "out0", 0 0, L_0x29f99e0; 1 drivers +v0x28b9060_0 .net "out1", 0 0, L_0x29f9b30; 1 drivers +v0x28b9140_0 .alias "outfinal", 0 0, v0x28b9c10_0; +S_0x28b76a0 .scope generate, "orbits[14]" "orbits[14]" 3 258, 3 258, S_0x28a2590; + .timescale -9 -12; +P_0x28b73b8 .param/l "i" 3 258, +C4<01110>; +S_0x28b77d0 .scope module, "attempt" "OrNorXor" 3 260, 3 165, S_0x28b76a0; + .timescale -9 -12; +L_0x29f8ed0/d .functor NOR 1, L_0x29fa1a0, L_0x29fa240, C4<0>, C4<0>; +L_0x29f8ed0 .delay (10000,10000,10000) L_0x29f8ed0/d; +L_0x29fa330/d .functor NOT 1, L_0x29f8ed0, C4<0>, C4<0>, C4<0>; +L_0x29fa330 .delay (10000,10000,10000) L_0x29fa330/d; +L_0x29fa420/d .functor NAND 1, L_0x29fa1a0, L_0x29fa240, C4<1>, C4<1>; +L_0x29fa420 .delay (10000,10000,10000) L_0x29fa420/d; +L_0x29fa580/d .functor NAND 1, L_0x29fa420, L_0x29fa330, C4<1>, C4<1>; +L_0x29fa580 .delay (10000,10000,10000) L_0x29fa580/d; +L_0x29fa690/d .functor NOT 1, L_0x29fa580, C4<0>, C4<0>, C4<0>; +L_0x29fa690 .delay (10000,10000,10000) L_0x29fa690/d; +v0x28b8380_0 .net "A", 0 0, L_0x29fa1a0; 1 drivers +v0x28b8420_0 .net "AnandB", 0 0, L_0x29fa420; 1 drivers +v0x28b84c0_0 .net "AnorB", 0 0, L_0x29f8ed0; 1 drivers +v0x28b8570_0 .net "AorB", 0 0, L_0x29fa330; 1 drivers +v0x28b8650_0 .net "AxorB", 0 0, L_0x29fa690; 1 drivers +v0x28b8700_0 .net "B", 0 0, L_0x29fa240; 1 drivers +v0x28b87c0_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x28b8840_0 .net "OrNorXorOut", 0 0, L_0x29fb090; 1 drivers +v0x28b88c0_0 .net "XorNor", 0 0, L_0x29fab10; 1 drivers +v0x28b8990_0 .net "nXor", 0 0, L_0x29fa580; 1 drivers +L_0x29fac90 .part v0x2960210_0, 2, 1; +L_0x29fb260 .part v0x2960210_0, 0, 1; +S_0x28b7e10 .scope module, "mux0" "TwoInMux" 3 184, 3 109, S_0x28b77d0; + .timescale -9 -12; +L_0x29fa7f0/d .functor NOT 1, L_0x29fac90, C4<0>, C4<0>, C4<0>; +L_0x29fa7f0 .delay (10000,10000,10000) L_0x29fa7f0/d; +L_0x29fa8b0/d .functor AND 1, L_0x29fa690, L_0x29fa7f0, C4<1>, C4<1>; +L_0x29fa8b0 .delay (20000,20000,20000) L_0x29fa8b0/d; +L_0x29fa9c0/d .functor AND 1, L_0x29f8ed0, L_0x29fac90, C4<1>, C4<1>; +L_0x29fa9c0 .delay (20000,20000,20000) L_0x29fa9c0/d; +L_0x29fab10/d .functor OR 1, L_0x29fa8b0, L_0x29fa9c0, C4<0>, C4<0>; +L_0x29fab10 .delay (20000,20000,20000) L_0x29fab10/d; +v0x28b7f00_0 .net "S", 0 0, L_0x29fac90; 1 drivers +v0x28b7fc0_0 .alias "in0", 0 0, v0x28b8650_0; +v0x28b8060_0 .alias "in1", 0 0, v0x28b84c0_0; +v0x28b8100_0 .net "nS", 0 0, L_0x29fa7f0; 1 drivers +v0x28b8180_0 .net "out0", 0 0, L_0x29fa8b0; 1 drivers +v0x28b8220_0 .net "out1", 0 0, L_0x29fa9c0; 1 drivers +v0x28b8300_0 .alias "outfinal", 0 0, v0x28b88c0_0; +S_0x28b78c0 .scope module, "mux1" "TwoInMux" 3 185, 3 109, S_0x28b77d0; + .timescale -9 -12; +L_0x29fad30/d .functor NOT 1, L_0x29fb260, C4<0>, C4<0>, C4<0>; +L_0x29fad30 .delay (10000,10000,10000) L_0x29fad30/d; +L_0x29fadf0/d .functor AND 1, L_0x29fab10, L_0x29fad30, C4<1>, C4<1>; +L_0x29fadf0 .delay (20000,20000,20000) L_0x29fadf0/d; +L_0x29faf40/d .functor AND 1, L_0x29fa330, L_0x29fb260, C4<1>, C4<1>; +L_0x29faf40 .delay (20000,20000,20000) L_0x29faf40/d; +L_0x29fb090/d .functor OR 1, L_0x29fadf0, L_0x29faf40, C4<0>, C4<0>; +L_0x29fb090 .delay (20000,20000,20000) L_0x29fb090/d; +v0x28b79b0_0 .net "S", 0 0, L_0x29fb260; 1 drivers +v0x28b7a30_0 .alias "in0", 0 0, v0x28b88c0_0; +v0x28b7ad0_0 .alias "in1", 0 0, v0x28b8570_0; +v0x28b7b70_0 .net "nS", 0 0, L_0x29fad30; 1 drivers +v0x28b7bf0_0 .net "out0", 0 0, L_0x29fadf0; 1 drivers +v0x28b7c90_0 .net "out1", 0 0, L_0x29faf40; 1 drivers +v0x28b7d70_0 .alias "outfinal", 0 0, v0x28b8840_0; +S_0x28b62d0 .scope generate, "orbits[15]" "orbits[15]" 3 258, 3 258, S_0x28a2590; + .timescale -9 -12; +P_0x28b5fe8 .param/l "i" 3 258, +C4<01111>; +S_0x28b6400 .scope module, "attempt" "OrNorXor" 3 260, 3 165, S_0x28b62d0; + .timescale -9 -12; +L_0x29fb500/d .functor NOR 1, L_0x29fc6a0, L_0x29fb3a0, C4<0>, C4<0>; +L_0x29fb500 .delay (10000,10000,10000) L_0x29fb500/d; +L_0x29fb5f0/d .functor NOT 1, L_0x29fb500, C4<0>, C4<0>, C4<0>; +L_0x29fb5f0 .delay (10000,10000,10000) L_0x29fb5f0/d; +L_0x29fb720/d .functor NAND 1, L_0x29fc6a0, L_0x29fb3a0, C4<1>, C4<1>; +L_0x29fb720 .delay (10000,10000,10000) L_0x29fb720/d; +L_0x29fb880/d .functor NAND 1, L_0x29fb720, L_0x29fb5f0, C4<1>, C4<1>; +L_0x29fb880 .delay (10000,10000,10000) L_0x29fb880/d; +L_0x29fb990/d .functor NOT 1, L_0x29fb880, C4<0>, C4<0>, C4<0>; +L_0x29fb990 .delay (10000,10000,10000) L_0x29fb990/d; +v0x28b6fb0_0 .net "A", 0 0, L_0x29fc6a0; 1 drivers +v0x28b7050_0 .net "AnandB", 0 0, L_0x29fb720; 1 drivers +v0x28b70f0_0 .net "AnorB", 0 0, L_0x29fb500; 1 drivers +v0x28b71a0_0 .net "AorB", 0 0, L_0x29fb5f0; 1 drivers +v0x28b7280_0 .net "AxorB", 0 0, L_0x29fb990; 1 drivers +v0x28b7330_0 .net "B", 0 0, L_0x29fb3a0; 1 drivers +v0x28b73f0_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x28b7470_0 .net "OrNorXorOut", 0 0, L_0x29fc390; 1 drivers +v0x28b74f0_0 .net "XorNor", 0 0, L_0x29fbe10; 1 drivers +v0x28b75c0_0 .net "nXor", 0 0, L_0x29fb880; 1 drivers +L_0x29fbf90 .part v0x2960210_0, 2, 1; +L_0x29fc560 .part v0x2960210_0, 0, 1; +S_0x28b6a40 .scope module, "mux0" "TwoInMux" 3 184, 3 109, S_0x28b6400; + .timescale -9 -12; +L_0x29fbaf0/d .functor NOT 1, L_0x29fbf90, C4<0>, C4<0>, C4<0>; +L_0x29fbaf0 .delay (10000,10000,10000) L_0x29fbaf0/d; +L_0x29fbbb0/d .functor AND 1, L_0x29fb990, L_0x29fbaf0, C4<1>, C4<1>; +L_0x29fbbb0 .delay (20000,20000,20000) L_0x29fbbb0/d; +L_0x29fbcc0/d .functor AND 1, L_0x29fb500, L_0x29fbf90, C4<1>, C4<1>; +L_0x29fbcc0 .delay (20000,20000,20000) L_0x29fbcc0/d; +L_0x29fbe10/d .functor OR 1, L_0x29fbbb0, L_0x29fbcc0, C4<0>, C4<0>; +L_0x29fbe10 .delay (20000,20000,20000) L_0x29fbe10/d; +v0x28b6b30_0 .net "S", 0 0, L_0x29fbf90; 1 drivers +v0x28b6bf0_0 .alias "in0", 0 0, v0x28b7280_0; +v0x28b6c90_0 .alias "in1", 0 0, v0x28b70f0_0; +v0x28b6d30_0 .net "nS", 0 0, L_0x29fbaf0; 1 drivers +v0x28b6db0_0 .net "out0", 0 0, L_0x29fbbb0; 1 drivers +v0x28b6e50_0 .net "out1", 0 0, L_0x29fbcc0; 1 drivers +v0x28b6f30_0 .alias "outfinal", 0 0, v0x28b74f0_0; +S_0x28b64f0 .scope module, "mux1" "TwoInMux" 3 185, 3 109, S_0x28b6400; + .timescale -9 -12; +L_0x29fc030/d .functor NOT 1, L_0x29fc560, C4<0>, C4<0>, C4<0>; +L_0x29fc030 .delay (10000,10000,10000) L_0x29fc030/d; +L_0x29fc0f0/d .functor AND 1, L_0x29fbe10, L_0x29fc030, C4<1>, C4<1>; +L_0x29fc0f0 .delay (20000,20000,20000) L_0x29fc0f0/d; +L_0x29fc240/d .functor AND 1, L_0x29fb5f0, L_0x29fc560, C4<1>, C4<1>; +L_0x29fc240 .delay (20000,20000,20000) L_0x29fc240/d; +L_0x29fc390/d .functor OR 1, L_0x29fc0f0, L_0x29fc240, C4<0>, C4<0>; +L_0x29fc390 .delay (20000,20000,20000) L_0x29fc390/d; +v0x28b65e0_0 .net "S", 0 0, L_0x29fc560; 1 drivers +v0x28b6660_0 .alias "in0", 0 0, v0x28b74f0_0; +v0x28b6700_0 .alias "in1", 0 0, v0x28b71a0_0; +v0x28b67a0_0 .net "nS", 0 0, L_0x29fc030; 1 drivers +v0x28b6820_0 .net "out0", 0 0, L_0x29fc0f0; 1 drivers +v0x28b68c0_0 .net "out1", 0 0, L_0x29fc240; 1 drivers +v0x28b69a0_0 .alias "outfinal", 0 0, v0x28b7470_0; +S_0x28b4f00 .scope generate, "orbits[16]" "orbits[16]" 3 258, 3 258, S_0x28a2590; + .timescale -9 -12; +P_0x28b4c18 .param/l "i" 3 258, +C4<010000>; +S_0x28b5030 .scope module, "attempt" "OrNorXor" 3 260, 3 165, S_0x28b4f00; + .timescale -9 -12; +L_0x29fb440/d .functor NOR 1, L_0x29fc740, L_0x29fc7e0, C4<0>, C4<0>; +L_0x29fb440 .delay (10000,10000,10000) L_0x29fb440/d; +L_0x29fc900/d .functor NOT 1, L_0x29fb440, C4<0>, C4<0>, C4<0>; +L_0x29fc900 .delay (10000,10000,10000) L_0x29fc900/d; +L_0x29fca10/d .functor NAND 1, L_0x29fc740, L_0x29fc7e0, C4<1>, C4<1>; +L_0x29fca10 .delay (10000,10000,10000) L_0x29fca10/d; +L_0x29fcb70/d .functor NAND 1, L_0x29fca10, L_0x29fc900, C4<1>, C4<1>; +L_0x29fcb70 .delay (10000,10000,10000) L_0x29fcb70/d; +L_0x29fcc80/d .functor NOT 1, L_0x29fcb70, C4<0>, C4<0>, C4<0>; +L_0x29fcc80 .delay (10000,10000,10000) L_0x29fcc80/d; +v0x28b5be0_0 .net "A", 0 0, L_0x29fc740; 1 drivers +v0x28b5c80_0 .net "AnandB", 0 0, L_0x29fca10; 1 drivers +v0x28b5d20_0 .net "AnorB", 0 0, L_0x29fb440; 1 drivers +v0x28b5dd0_0 .net "AorB", 0 0, L_0x29fc900; 1 drivers +v0x28b5eb0_0 .net "AxorB", 0 0, L_0x29fcc80; 1 drivers +v0x28b5f60_0 .net "B", 0 0, L_0x29fc7e0; 1 drivers +v0x28b6020_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x28b60a0_0 .net "OrNorXorOut", 0 0, L_0x29fd680; 1 drivers +v0x28b6120_0 .net "XorNor", 0 0, L_0x29fd100; 1 drivers +v0x28b61f0_0 .net "nXor", 0 0, L_0x29fcb70; 1 drivers +L_0x29fd280 .part v0x2960210_0, 2, 1; +L_0x29fd850 .part v0x2960210_0, 0, 1; +S_0x28b5670 .scope module, "mux0" "TwoInMux" 3 184, 3 109, S_0x28b5030; + .timescale -9 -12; +L_0x29fcde0/d .functor NOT 1, L_0x29fd280, C4<0>, C4<0>, C4<0>; +L_0x29fcde0 .delay (10000,10000,10000) L_0x29fcde0/d; +L_0x29fcea0/d .functor AND 1, L_0x29fcc80, L_0x29fcde0, C4<1>, C4<1>; +L_0x29fcea0 .delay (20000,20000,20000) L_0x29fcea0/d; +L_0x29fcfb0/d .functor AND 1, L_0x29fb440, L_0x29fd280, C4<1>, C4<1>; +L_0x29fcfb0 .delay (20000,20000,20000) L_0x29fcfb0/d; +L_0x29fd100/d .functor OR 1, L_0x29fcea0, L_0x29fcfb0, C4<0>, C4<0>; +L_0x29fd100 .delay (20000,20000,20000) L_0x29fd100/d; +v0x28b5760_0 .net "S", 0 0, L_0x29fd280; 1 drivers +v0x28b5820_0 .alias "in0", 0 0, v0x28b5eb0_0; +v0x28b58c0_0 .alias "in1", 0 0, v0x28b5d20_0; +v0x28b5960_0 .net "nS", 0 0, L_0x29fcde0; 1 drivers +v0x28b59e0_0 .net "out0", 0 0, L_0x29fcea0; 1 drivers +v0x28b5a80_0 .net "out1", 0 0, L_0x29fcfb0; 1 drivers +v0x28b5b60_0 .alias "outfinal", 0 0, v0x28b6120_0; +S_0x28b5120 .scope module, "mux1" "TwoInMux" 3 185, 3 109, S_0x28b5030; + .timescale -9 -12; +L_0x29fd320/d .functor NOT 1, L_0x29fd850, C4<0>, C4<0>, C4<0>; +L_0x29fd320 .delay (10000,10000,10000) L_0x29fd320/d; +L_0x29fd3e0/d .functor AND 1, L_0x29fd100, L_0x29fd320, C4<1>, C4<1>; +L_0x29fd3e0 .delay (20000,20000,20000) L_0x29fd3e0/d; +L_0x29fd530/d .functor AND 1, L_0x29fc900, L_0x29fd850, C4<1>, C4<1>; +L_0x29fd530 .delay (20000,20000,20000) L_0x29fd530/d; +L_0x29fd680/d .functor OR 1, L_0x29fd3e0, L_0x29fd530, C4<0>, C4<0>; +L_0x29fd680 .delay (20000,20000,20000) L_0x29fd680/d; +v0x28b5210_0 .net "S", 0 0, L_0x29fd850; 1 drivers +v0x28b5290_0 .alias "in0", 0 0, v0x28b6120_0; +v0x28b5330_0 .alias "in1", 0 0, v0x28b5dd0_0; +v0x28b53d0_0 .net "nS", 0 0, L_0x29fd320; 1 drivers +v0x28b5450_0 .net "out0", 0 0, L_0x29fd3e0; 1 drivers +v0x28b54f0_0 .net "out1", 0 0, L_0x29fd530; 1 drivers +v0x28b55d0_0 .alias "outfinal", 0 0, v0x28b60a0_0; +S_0x28b3b30 .scope generate, "orbits[17]" "orbits[17]" 3 258, 3 258, S_0x28a2590; + .timescale -9 -12; +P_0x28b3848 .param/l "i" 3 258, +C4<010001>; +S_0x28b3c60 .scope module, "attempt" "OrNorXor" 3 260, 3 165, S_0x28b3b30; + .timescale -9 -12; +L_0x29fdb20/d .functor NOR 1, L_0x29feca0, L_0x29fd990, C4<0>, C4<0>; +L_0x29fdb20 .delay (10000,10000,10000) L_0x29fdb20/d; +L_0x29fdc10/d .functor NOT 1, L_0x29fdb20, C4<0>, C4<0>, C4<0>; +L_0x29fdc10 .delay (10000,10000,10000) L_0x29fdc10/d; +L_0x29fdd20/d .functor NAND 1, L_0x29feca0, L_0x29fd990, C4<1>, C4<1>; +L_0x29fdd20 .delay (10000,10000,10000) L_0x29fdd20/d; +L_0x29fde80/d .functor NAND 1, L_0x29fdd20, L_0x29fdc10, C4<1>, C4<1>; +L_0x29fde80 .delay (10000,10000,10000) L_0x29fde80/d; +L_0x29fdf90/d .functor NOT 1, L_0x29fde80, C4<0>, C4<0>, C4<0>; +L_0x29fdf90 .delay (10000,10000,10000) L_0x29fdf90/d; +v0x28b4810_0 .net "A", 0 0, L_0x29feca0; 1 drivers +v0x28b48b0_0 .net "AnandB", 0 0, L_0x29fdd20; 1 drivers +v0x28b4950_0 .net "AnorB", 0 0, L_0x29fdb20; 1 drivers +v0x28b4a00_0 .net "AorB", 0 0, L_0x29fdc10; 1 drivers +v0x28b4ae0_0 .net "AxorB", 0 0, L_0x29fdf90; 1 drivers +v0x28b4b90_0 .net "B", 0 0, L_0x29fd990; 1 drivers +v0x28b4c50_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x28b4cd0_0 .net "OrNorXorOut", 0 0, L_0x29fe990; 1 drivers +v0x28b4d50_0 .net "XorNor", 0 0, L_0x29fe410; 1 drivers +v0x28b4e20_0 .net "nXor", 0 0, L_0x29fde80; 1 drivers +L_0x29fe590 .part v0x2960210_0, 2, 1; +L_0x29feb60 .part v0x2960210_0, 0, 1; +S_0x28b42a0 .scope module, "mux0" "TwoInMux" 3 184, 3 109, S_0x28b3c60; + .timescale -9 -12; +L_0x29fe0f0/d .functor NOT 1, L_0x29fe590, C4<0>, C4<0>, C4<0>; +L_0x29fe0f0 .delay (10000,10000,10000) L_0x29fe0f0/d; +L_0x29fe1b0/d .functor AND 1, L_0x29fdf90, L_0x29fe0f0, C4<1>, C4<1>; +L_0x29fe1b0 .delay (20000,20000,20000) L_0x29fe1b0/d; +L_0x29fe2c0/d .functor AND 1, L_0x29fdb20, L_0x29fe590, C4<1>, C4<1>; +L_0x29fe2c0 .delay (20000,20000,20000) L_0x29fe2c0/d; +L_0x29fe410/d .functor OR 1, L_0x29fe1b0, L_0x29fe2c0, C4<0>, C4<0>; +L_0x29fe410 .delay (20000,20000,20000) L_0x29fe410/d; +v0x28b4390_0 .net "S", 0 0, L_0x29fe590; 1 drivers +v0x28b4450_0 .alias "in0", 0 0, v0x28b4ae0_0; +v0x28b44f0_0 .alias "in1", 0 0, v0x28b4950_0; +v0x28b4590_0 .net "nS", 0 0, L_0x29fe0f0; 1 drivers +v0x28b4610_0 .net "out0", 0 0, L_0x29fe1b0; 1 drivers +v0x28b46b0_0 .net "out1", 0 0, L_0x29fe2c0; 1 drivers +v0x28b4790_0 .alias "outfinal", 0 0, v0x28b4d50_0; +S_0x28b3d50 .scope module, "mux1" "TwoInMux" 3 185, 3 109, S_0x28b3c60; + .timescale -9 -12; +L_0x29fe630/d .functor NOT 1, L_0x29feb60, C4<0>, C4<0>, C4<0>; +L_0x29fe630 .delay (10000,10000,10000) L_0x29fe630/d; +L_0x29fe6f0/d .functor AND 1, L_0x29fe410, L_0x29fe630, C4<1>, C4<1>; +L_0x29fe6f0 .delay (20000,20000,20000) L_0x29fe6f0/d; +L_0x29fe840/d .functor AND 1, L_0x29fdc10, L_0x29feb60, C4<1>, C4<1>; +L_0x29fe840 .delay (20000,20000,20000) L_0x29fe840/d; +L_0x29fe990/d .functor OR 1, L_0x29fe6f0, L_0x29fe840, C4<0>, C4<0>; +L_0x29fe990 .delay (20000,20000,20000) L_0x29fe990/d; +v0x28b3e40_0 .net "S", 0 0, L_0x29feb60; 1 drivers +v0x28b3ec0_0 .alias "in0", 0 0, v0x28b4d50_0; +v0x28b3f60_0 .alias "in1", 0 0, v0x28b4a00_0; +v0x28b4000_0 .net "nS", 0 0, L_0x29fe630; 1 drivers +v0x28b4080_0 .net "out0", 0 0, L_0x29fe6f0; 1 drivers +v0x28b4120_0 .net "out1", 0 0, L_0x29fe840; 1 drivers +v0x28b4200_0 .alias "outfinal", 0 0, v0x28b4cd0_0; +S_0x28b2760 .scope generate, "orbits[18]" "orbits[18]" 3 258, 3 258, S_0x28a2590; + .timescale -9 -12; +P_0x28b2478 .param/l "i" 3 258, +C4<010010>; +S_0x28b2890 .scope module, "attempt" "OrNorXor" 3 260, 3 165, S_0x28b2760; + .timescale -9 -12; +L_0x29fda30/d .functor NOR 1, L_0x29fed40, L_0x29fede0, C4<0>, C4<0>; +L_0x29fda30 .delay (10000,10000,10000) L_0x29fda30/d; +L_0x29feee0/d .functor NOT 1, L_0x29fda30, C4<0>, C4<0>, C4<0>; +L_0x29feee0 .delay (10000,10000,10000) L_0x29feee0/d; +L_0x29ff010/d .functor NAND 1, L_0x29fed40, L_0x29fede0, C4<1>, C4<1>; +L_0x29ff010 .delay (10000,10000,10000) L_0x29ff010/d; +L_0x29ff170/d .functor NAND 1, L_0x29ff010, L_0x29feee0, C4<1>, C4<1>; +L_0x29ff170 .delay (10000,10000,10000) L_0x29ff170/d; +L_0x29ff280/d .functor NOT 1, L_0x29ff170, C4<0>, C4<0>, C4<0>; +L_0x29ff280 .delay (10000,10000,10000) L_0x29ff280/d; +v0x28b3440_0 .net "A", 0 0, L_0x29fed40; 1 drivers +v0x28b34e0_0 .net "AnandB", 0 0, L_0x29ff010; 1 drivers +v0x28b3580_0 .net "AnorB", 0 0, L_0x29fda30; 1 drivers +v0x28b3630_0 .net "AorB", 0 0, L_0x29feee0; 1 drivers +v0x28b3710_0 .net "AxorB", 0 0, L_0x29ff280; 1 drivers +v0x28b37c0_0 .net "B", 0 0, L_0x29fede0; 1 drivers +v0x28b3880_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x28b3900_0 .net "OrNorXorOut", 0 0, L_0x29ffc80; 1 drivers +v0x28b3980_0 .net "XorNor", 0 0, L_0x29ff700; 1 drivers +v0x28b3a50_0 .net "nXor", 0 0, L_0x29ff170; 1 drivers +L_0x29ff880 .part v0x2960210_0, 2, 1; +L_0x29ffe50 .part v0x2960210_0, 0, 1; +S_0x28b2ed0 .scope module, "mux0" "TwoInMux" 3 184, 3 109, S_0x28b2890; + .timescale -9 -12; +L_0x29ff3e0/d .functor NOT 1, L_0x29ff880, C4<0>, C4<0>, C4<0>; +L_0x29ff3e0 .delay (10000,10000,10000) L_0x29ff3e0/d; +L_0x29ff4a0/d .functor AND 1, L_0x29ff280, L_0x29ff3e0, C4<1>, C4<1>; +L_0x29ff4a0 .delay (20000,20000,20000) L_0x29ff4a0/d; +L_0x29ff5b0/d .functor AND 1, L_0x29fda30, L_0x29ff880, C4<1>, C4<1>; +L_0x29ff5b0 .delay (20000,20000,20000) L_0x29ff5b0/d; +L_0x29ff700/d .functor OR 1, L_0x29ff4a0, L_0x29ff5b0, C4<0>, C4<0>; +L_0x29ff700 .delay (20000,20000,20000) L_0x29ff700/d; +v0x28b2fc0_0 .net "S", 0 0, L_0x29ff880; 1 drivers +v0x28b3080_0 .alias "in0", 0 0, v0x28b3710_0; +v0x28b3120_0 .alias "in1", 0 0, v0x28b3580_0; +v0x28b31c0_0 .net "nS", 0 0, L_0x29ff3e0; 1 drivers +v0x28b3240_0 .net "out0", 0 0, L_0x29ff4a0; 1 drivers +v0x28b32e0_0 .net "out1", 0 0, L_0x29ff5b0; 1 drivers +v0x28b33c0_0 .alias "outfinal", 0 0, v0x28b3980_0; +S_0x28b2980 .scope module, "mux1" "TwoInMux" 3 185, 3 109, S_0x28b2890; + .timescale -9 -12; +L_0x29ff920/d .functor NOT 1, L_0x29ffe50, C4<0>, C4<0>, C4<0>; +L_0x29ff920 .delay (10000,10000,10000) L_0x29ff920/d; +L_0x29ff9e0/d .functor AND 1, L_0x29ff700, L_0x29ff920, C4<1>, C4<1>; +L_0x29ff9e0 .delay (20000,20000,20000) L_0x29ff9e0/d; +L_0x29ffb30/d .functor AND 1, L_0x29feee0, L_0x29ffe50, C4<1>, C4<1>; +L_0x29ffb30 .delay (20000,20000,20000) L_0x29ffb30/d; +L_0x29ffc80/d .functor OR 1, L_0x29ff9e0, L_0x29ffb30, C4<0>, C4<0>; +L_0x29ffc80 .delay (20000,20000,20000) L_0x29ffc80/d; +v0x28b2a70_0 .net "S", 0 0, L_0x29ffe50; 1 drivers +v0x28b2af0_0 .alias "in0", 0 0, v0x28b3980_0; +v0x28b2b90_0 .alias "in1", 0 0, v0x28b3630_0; +v0x28b2c30_0 .net "nS", 0 0, L_0x29ff920; 1 drivers +v0x28b2cb0_0 .net "out0", 0 0, L_0x29ff9e0; 1 drivers +v0x28b2d50_0 .net "out1", 0 0, L_0x29ffb30; 1 drivers +v0x28b2e30_0 .alias "outfinal", 0 0, v0x28b3900_0; +S_0x28b1390 .scope generate, "orbits[19]" "orbits[19]" 3 258, 3 258, S_0x28a2590; + .timescale -9 -12; +P_0x28b10a8 .param/l "i" 3 258, +C4<010011>; +S_0x28b14c0 .scope module, "attempt" "OrNorXor" 3 260, 3 165, S_0x28b1390; + .timescale -9 -12; +L_0x29fee80/d .functor NOR 1, L_0x2a022a0, L_0x29b4e70, C4<0>, C4<0>; +L_0x29fee80 .delay (10000,10000,10000) L_0x29fee80/d; +L_0x2a00020/d .functor NOT 1, L_0x29fee80, C4<0>, C4<0>, C4<0>; +L_0x2a00020 .delay (10000,10000,10000) L_0x2a00020/d; +L_0x2a000e0/d .functor NAND 1, L_0x2a022a0, L_0x29b4e70, C4<1>, C4<1>; +L_0x2a000e0 .delay (10000,10000,10000) L_0x2a000e0/d; +L_0x29b5160/d .functor NAND 1, L_0x2a000e0, L_0x2a00020, C4<1>, C4<1>; +L_0x29b5160 .delay (10000,10000,10000) L_0x29b5160/d; +L_0x29b5270/d .functor NOT 1, L_0x29b5160, C4<0>, C4<0>, C4<0>; +L_0x29b5270 .delay (10000,10000,10000) L_0x29b5270/d; +v0x28b2070_0 .net "A", 0 0, L_0x2a022a0; 1 drivers +v0x28b2110_0 .net "AnandB", 0 0, L_0x2a000e0; 1 drivers +v0x28b21b0_0 .net "AnorB", 0 0, L_0x29fee80; 1 drivers +v0x28b2260_0 .net "AorB", 0 0, L_0x2a00020; 1 drivers +v0x28b2340_0 .net "AxorB", 0 0, L_0x29b5270; 1 drivers +v0x28b23f0_0 .net "B", 0 0, L_0x29b4e70; 1 drivers +v0x28b24b0_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x28b2530_0 .net "OrNorXorOut", 0 0, L_0x29b5c70; 1 drivers +v0x28b25b0_0 .net "XorNor", 0 0, L_0x29b56f0; 1 drivers +v0x28b2680_0 .net "nXor", 0 0, L_0x29b5160; 1 drivers +L_0x29b5870 .part v0x2960210_0, 2, 1; +L_0x2a02160 .part v0x2960210_0, 0, 1; +S_0x28b1b00 .scope module, "mux0" "TwoInMux" 3 184, 3 109, S_0x28b14c0; + .timescale -9 -12; +L_0x29b53d0/d .functor NOT 1, L_0x29b5870, C4<0>, C4<0>, C4<0>; +L_0x29b53d0 .delay (10000,10000,10000) L_0x29b53d0/d; +L_0x29b5490/d .functor AND 1, L_0x29b5270, L_0x29b53d0, C4<1>, C4<1>; +L_0x29b5490 .delay (20000,20000,20000) L_0x29b5490/d; +L_0x29b55a0/d .functor AND 1, L_0x29fee80, L_0x29b5870, C4<1>, C4<1>; +L_0x29b55a0 .delay (20000,20000,20000) L_0x29b55a0/d; +L_0x29b56f0/d .functor OR 1, L_0x29b5490, L_0x29b55a0, C4<0>, C4<0>; +L_0x29b56f0 .delay (20000,20000,20000) L_0x29b56f0/d; +v0x28b1bf0_0 .net "S", 0 0, L_0x29b5870; 1 drivers +v0x28b1cb0_0 .alias "in0", 0 0, v0x28b2340_0; +v0x28b1d50_0 .alias "in1", 0 0, v0x28b21b0_0; +v0x28b1df0_0 .net "nS", 0 0, L_0x29b53d0; 1 drivers +v0x28b1e70_0 .net "out0", 0 0, L_0x29b5490; 1 drivers +v0x28b1f10_0 .net "out1", 0 0, L_0x29b55a0; 1 drivers +v0x28b1ff0_0 .alias "outfinal", 0 0, v0x28b25b0_0; +S_0x28b15b0 .scope module, "mux1" "TwoInMux" 3 185, 3 109, S_0x28b14c0; + .timescale -9 -12; +L_0x29b5910/d .functor NOT 1, L_0x2a02160, C4<0>, C4<0>, C4<0>; +L_0x29b5910 .delay (10000,10000,10000) L_0x29b5910/d; +L_0x29b59d0/d .functor AND 1, L_0x29b56f0, L_0x29b5910, C4<1>, C4<1>; +L_0x29b59d0 .delay (20000,20000,20000) L_0x29b59d0/d; +L_0x29b5b20/d .functor AND 1, L_0x2a00020, L_0x2a02160, C4<1>, C4<1>; +L_0x29b5b20 .delay (20000,20000,20000) L_0x29b5b20/d; +L_0x29b5c70/d .functor OR 1, L_0x29b59d0, L_0x29b5b20, C4<0>, C4<0>; +L_0x29b5c70 .delay (20000,20000,20000) L_0x29b5c70/d; +v0x28b16a0_0 .net "S", 0 0, L_0x2a02160; 1 drivers +v0x28b1720_0 .alias "in0", 0 0, v0x28b25b0_0; +v0x28b17c0_0 .alias "in1", 0 0, v0x28b2260_0; +v0x28b1860_0 .net "nS", 0 0, L_0x29b5910; 1 drivers +v0x28b18e0_0 .net "out0", 0 0, L_0x29b59d0; 1 drivers +v0x28b1980_0 .net "out1", 0 0, L_0x29b5b20; 1 drivers +v0x28b1a60_0 .alias "outfinal", 0 0, v0x28b2530_0; +S_0x28affc0 .scope generate, "orbits[20]" "orbits[20]" 3 258, 3 258, S_0x28a2590; + .timescale -9 -12; +P_0x28afcd8 .param/l "i" 3 258, +C4<010100>; +S_0x28b00f0 .scope module, "attempt" "OrNorXor" 3 260, 3 165, S_0x28affc0; + .timescale -9 -12; +L_0x29b4f10/d .functor NOR 1, L_0x2a02340, L_0x2a023e0, C4<0>, C4<0>; +L_0x29b4f10 .delay (10000,10000,10000) L_0x29b4f10/d; +L_0x29b4fb0/d .functor NOT 1, L_0x29b4f10, C4<0>, C4<0>, C4<0>; +L_0x29b4fb0 .delay (10000,10000,10000) L_0x29b4fb0/d; +L_0x2a025a0/d .functor NAND 1, L_0x2a02340, L_0x2a023e0, C4<1>, C4<1>; +L_0x2a025a0 .delay (10000,10000,10000) L_0x2a025a0/d; +L_0x2a026e0/d .functor NAND 1, L_0x2a025a0, L_0x29b4fb0, C4<1>, C4<1>; +L_0x2a026e0 .delay (10000,10000,10000) L_0x2a026e0/d; +L_0x2a027d0/d .functor NOT 1, L_0x2a026e0, C4<0>, C4<0>, C4<0>; +L_0x2a027d0 .delay (10000,10000,10000) L_0x2a027d0/d; +v0x28b0ca0_0 .net "A", 0 0, L_0x2a02340; 1 drivers +v0x28b0d40_0 .net "AnandB", 0 0, L_0x2a025a0; 1 drivers +v0x28b0de0_0 .net "AnorB", 0 0, L_0x29b4f10; 1 drivers +v0x28b0e90_0 .net "AorB", 0 0, L_0x29b4fb0; 1 drivers +v0x28b0f70_0 .net "AxorB", 0 0, L_0x2a027d0; 1 drivers +v0x28b1020_0 .net "B", 0 0, L_0x2a023e0; 1 drivers +v0x28b10e0_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x28b1160_0 .net "OrNorXorOut", 0 0, L_0x2a03150; 1 drivers +v0x28b11e0_0 .net "XorNor", 0 0, L_0x2a02bd0; 1 drivers +v0x28b12b0_0 .net "nXor", 0 0, L_0x2a026e0; 1 drivers +L_0x2a02d50 .part v0x2960210_0, 2, 1; +L_0x2a03320 .part v0x2960210_0, 0, 1; +S_0x28b0730 .scope module, "mux0" "TwoInMux" 3 184, 3 109, S_0x28b00f0; + .timescale -9 -12; +L_0x2a02910/d .functor NOT 1, L_0x2a02d50, C4<0>, C4<0>, C4<0>; +L_0x2a02910 .delay (10000,10000,10000) L_0x2a02910/d; +L_0x2a029b0/d .functor AND 1, L_0x2a027d0, L_0x2a02910, C4<1>, C4<1>; +L_0x2a029b0 .delay (20000,20000,20000) L_0x2a029b0/d; +L_0x2a02aa0/d .functor AND 1, L_0x29b4f10, L_0x2a02d50, C4<1>, C4<1>; +L_0x2a02aa0 .delay (20000,20000,20000) L_0x2a02aa0/d; +L_0x2a02bd0/d .functor OR 1, L_0x2a029b0, L_0x2a02aa0, C4<0>, C4<0>; +L_0x2a02bd0 .delay (20000,20000,20000) L_0x2a02bd0/d; +v0x28b0820_0 .net "S", 0 0, L_0x2a02d50; 1 drivers +v0x28b08e0_0 .alias "in0", 0 0, v0x28b0f70_0; +v0x28b0980_0 .alias "in1", 0 0, v0x28b0de0_0; +v0x28b0a20_0 .net "nS", 0 0, L_0x2a02910; 1 drivers +v0x28b0aa0_0 .net "out0", 0 0, L_0x2a029b0; 1 drivers +v0x28b0b40_0 .net "out1", 0 0, L_0x2a02aa0; 1 drivers +v0x28b0c20_0 .alias "outfinal", 0 0, v0x28b11e0_0; +S_0x28b01e0 .scope module, "mux1" "TwoInMux" 3 185, 3 109, S_0x28b00f0; + .timescale -9 -12; +L_0x2a02df0/d .functor NOT 1, L_0x2a03320, C4<0>, C4<0>, C4<0>; +L_0x2a02df0 .delay (10000,10000,10000) L_0x2a02df0/d; +L_0x2a02eb0/d .functor AND 1, L_0x2a02bd0, L_0x2a02df0, C4<1>, C4<1>; +L_0x2a02eb0 .delay (20000,20000,20000) L_0x2a02eb0/d; +L_0x2a03000/d .functor AND 1, L_0x29b4fb0, L_0x2a03320, C4<1>, C4<1>; +L_0x2a03000 .delay (20000,20000,20000) L_0x2a03000/d; +L_0x2a03150/d .functor OR 1, L_0x2a02eb0, L_0x2a03000, C4<0>, C4<0>; +L_0x2a03150 .delay (20000,20000,20000) L_0x2a03150/d; +v0x28b02d0_0 .net "S", 0 0, L_0x2a03320; 1 drivers +v0x28b0350_0 .alias "in0", 0 0, v0x28b11e0_0; +v0x28b03f0_0 .alias "in1", 0 0, v0x28b0e90_0; +v0x28b0490_0 .net "nS", 0 0, L_0x2a02df0; 1 drivers +v0x28b0510_0 .net "out0", 0 0, L_0x2a02eb0; 1 drivers +v0x28b05b0_0 .net "out1", 0 0, L_0x2a03000; 1 drivers +v0x28b0690_0 .alias "outfinal", 0 0, v0x28b1160_0; +S_0x28aebf0 .scope generate, "orbits[21]" "orbits[21]" 3 258, 3 258, S_0x28a2590; + .timescale -9 -12; +P_0x28ae908 .param/l "i" 3 258, +C4<010101>; +S_0x28aed20 .scope module, "attempt" "OrNorXor" 3 260, 3 165, S_0x28aebf0; + .timescale -9 -12; +L_0x2a02480/d .functor NOR 1, L_0x2a04770, L_0x2a03460, C4<0>, C4<0>; +L_0x2a02480 .delay (10000,10000,10000) L_0x2a02480/d; +L_0x2a036e0/d .functor NOT 1, L_0x2a02480, C4<0>, C4<0>, C4<0>; +L_0x2a036e0 .delay (10000,10000,10000) L_0x2a036e0/d; +L_0x2a037f0/d .functor NAND 1, L_0x2a04770, L_0x2a03460, C4<1>, C4<1>; +L_0x2a037f0 .delay (10000,10000,10000) L_0x2a037f0/d; +L_0x2a03950/d .functor NAND 1, L_0x2a037f0, L_0x2a036e0, C4<1>, C4<1>; +L_0x2a03950 .delay (10000,10000,10000) L_0x2a03950/d; +L_0x2a03a60/d .functor NOT 1, L_0x2a03950, C4<0>, C4<0>, C4<0>; +L_0x2a03a60 .delay (10000,10000,10000) L_0x2a03a60/d; +v0x28af8d0_0 .net "A", 0 0, L_0x2a04770; 1 drivers +v0x28af970_0 .net "AnandB", 0 0, L_0x2a037f0; 1 drivers +v0x28afa10_0 .net "AnorB", 0 0, L_0x2a02480; 1 drivers +v0x28afac0_0 .net "AorB", 0 0, L_0x2a036e0; 1 drivers +v0x28afba0_0 .net "AxorB", 0 0, L_0x2a03a60; 1 drivers +v0x28afc50_0 .net "B", 0 0, L_0x2a03460; 1 drivers +v0x28afd10_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x28afd90_0 .net "OrNorXorOut", 0 0, L_0x2a04460; 1 drivers +v0x28afe10_0 .net "XorNor", 0 0, L_0x2a03ee0; 1 drivers +v0x28afee0_0 .net "nXor", 0 0, L_0x2a03950; 1 drivers +L_0x2a04060 .part v0x2960210_0, 2, 1; +L_0x2a04630 .part v0x2960210_0, 0, 1; +S_0x28af360 .scope module, "mux0" "TwoInMux" 3 184, 3 109, S_0x28aed20; + .timescale -9 -12; +L_0x2a03bc0/d .functor NOT 1, L_0x2a04060, C4<0>, C4<0>, C4<0>; +L_0x2a03bc0 .delay (10000,10000,10000) L_0x2a03bc0/d; +L_0x2a03c80/d .functor AND 1, L_0x2a03a60, L_0x2a03bc0, C4<1>, C4<1>; +L_0x2a03c80 .delay (20000,20000,20000) L_0x2a03c80/d; +L_0x2a03d90/d .functor AND 1, L_0x2a02480, L_0x2a04060, C4<1>, C4<1>; +L_0x2a03d90 .delay (20000,20000,20000) L_0x2a03d90/d; +L_0x2a03ee0/d .functor OR 1, L_0x2a03c80, L_0x2a03d90, C4<0>, C4<0>; +L_0x2a03ee0 .delay (20000,20000,20000) L_0x2a03ee0/d; +v0x28af450_0 .net "S", 0 0, L_0x2a04060; 1 drivers +v0x28af510_0 .alias "in0", 0 0, v0x28afba0_0; +v0x28af5b0_0 .alias "in1", 0 0, v0x28afa10_0; +v0x28af650_0 .net "nS", 0 0, L_0x2a03bc0; 1 drivers +v0x28af6d0_0 .net "out0", 0 0, L_0x2a03c80; 1 drivers +v0x28af770_0 .net "out1", 0 0, L_0x2a03d90; 1 drivers +v0x28af850_0 .alias "outfinal", 0 0, v0x28afe10_0; +S_0x28aee10 .scope module, "mux1" "TwoInMux" 3 185, 3 109, S_0x28aed20; + .timescale -9 -12; +L_0x2a04100/d .functor NOT 1, L_0x2a04630, C4<0>, C4<0>, C4<0>; +L_0x2a04100 .delay (10000,10000,10000) L_0x2a04100/d; +L_0x2a041c0/d .functor AND 1, L_0x2a03ee0, L_0x2a04100, C4<1>, C4<1>; +L_0x2a041c0 .delay (20000,20000,20000) L_0x2a041c0/d; +L_0x2a04310/d .functor AND 1, L_0x2a036e0, L_0x2a04630, C4<1>, C4<1>; +L_0x2a04310 .delay (20000,20000,20000) L_0x2a04310/d; +L_0x2a04460/d .functor OR 1, L_0x2a041c0, L_0x2a04310, C4<0>, C4<0>; +L_0x2a04460 .delay (20000,20000,20000) L_0x2a04460/d; +v0x28aef00_0 .net "S", 0 0, L_0x2a04630; 1 drivers +v0x28aef80_0 .alias "in0", 0 0, v0x28afe10_0; +v0x28af020_0 .alias "in1", 0 0, v0x28afac0_0; +v0x28af0c0_0 .net "nS", 0 0, L_0x2a04100; 1 drivers +v0x28af140_0 .net "out0", 0 0, L_0x2a041c0; 1 drivers +v0x28af1e0_0 .net "out1", 0 0, L_0x2a04310; 1 drivers +v0x28af2c0_0 .alias "outfinal", 0 0, v0x28afd90_0; +S_0x28ad820 .scope generate, "orbits[22]" "orbits[22]" 3 258, 3 258, S_0x28a2590; + .timescale -9 -12; +P_0x28ad538 .param/l "i" 3 258, +C4<010110>; +S_0x28ad950 .scope module, "attempt" "OrNorXor" 3 260, 3 165, S_0x28ad820; + .timescale -9 -12; +L_0x2a03500/d .functor NOR 1, L_0x2a04810, L_0x2a048b0, C4<0>, C4<0>; +L_0x2a03500 .delay (10000,10000,10000) L_0x2a03500/d; +L_0x2a035f0/d .functor NOT 1, L_0x2a03500, C4<0>, C4<0>, C4<0>; +L_0x2a035f0 .delay (10000,10000,10000) L_0x2a035f0/d; +L_0x2a04ae0/d .functor NAND 1, L_0x2a04810, L_0x2a048b0, C4<1>, C4<1>; +L_0x2a04ae0 .delay (10000,10000,10000) L_0x2a04ae0/d; +L_0x2a04c40/d .functor NAND 1, L_0x2a04ae0, L_0x2a035f0, C4<1>, C4<1>; +L_0x2a04c40 .delay (10000,10000,10000) L_0x2a04c40/d; +L_0x2a04d50/d .functor NOT 1, L_0x2a04c40, C4<0>, C4<0>, C4<0>; +L_0x2a04d50 .delay (10000,10000,10000) L_0x2a04d50/d; +v0x28ae500_0 .net "A", 0 0, L_0x2a04810; 1 drivers +v0x28ae5a0_0 .net "AnandB", 0 0, L_0x2a04ae0; 1 drivers +v0x28ae640_0 .net "AnorB", 0 0, L_0x2a03500; 1 drivers +v0x28ae6f0_0 .net "AorB", 0 0, L_0x2a035f0; 1 drivers +v0x28ae7d0_0 .net "AxorB", 0 0, L_0x2a04d50; 1 drivers +v0x28ae880_0 .net "B", 0 0, L_0x2a048b0; 1 drivers +v0x28ae940_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x28ae9c0_0 .net "OrNorXorOut", 0 0, L_0x2a05750; 1 drivers +v0x28aea40_0 .net "XorNor", 0 0, L_0x2a051d0; 1 drivers +v0x28aeb10_0 .net "nXor", 0 0, L_0x2a04c40; 1 drivers +L_0x2a05350 .part v0x2960210_0, 2, 1; +L_0x2a05920 .part v0x2960210_0, 0, 1; +S_0x28adf90 .scope module, "mux0" "TwoInMux" 3 184, 3 109, S_0x28ad950; + .timescale -9 -12; +L_0x2a04eb0/d .functor NOT 1, L_0x2a05350, C4<0>, C4<0>, C4<0>; +L_0x2a04eb0 .delay (10000,10000,10000) L_0x2a04eb0/d; +L_0x2a04f70/d .functor AND 1, L_0x2a04d50, L_0x2a04eb0, C4<1>, C4<1>; +L_0x2a04f70 .delay (20000,20000,20000) L_0x2a04f70/d; +L_0x2a05080/d .functor AND 1, L_0x2a03500, L_0x2a05350, C4<1>, C4<1>; +L_0x2a05080 .delay (20000,20000,20000) L_0x2a05080/d; +L_0x2a051d0/d .functor OR 1, L_0x2a04f70, L_0x2a05080, C4<0>, C4<0>; +L_0x2a051d0 .delay (20000,20000,20000) L_0x2a051d0/d; +v0x28ae080_0 .net "S", 0 0, L_0x2a05350; 1 drivers +v0x28ae140_0 .alias "in0", 0 0, v0x28ae7d0_0; +v0x28ae1e0_0 .alias "in1", 0 0, v0x28ae640_0; +v0x28ae280_0 .net "nS", 0 0, L_0x2a04eb0; 1 drivers +v0x28ae300_0 .net "out0", 0 0, L_0x2a04f70; 1 drivers +v0x28ae3a0_0 .net "out1", 0 0, L_0x2a05080; 1 drivers +v0x28ae480_0 .alias "outfinal", 0 0, v0x28aea40_0; +S_0x28ada40 .scope module, "mux1" "TwoInMux" 3 185, 3 109, S_0x28ad950; + .timescale -9 -12; +L_0x2a053f0/d .functor NOT 1, L_0x2a05920, C4<0>, C4<0>, C4<0>; +L_0x2a053f0 .delay (10000,10000,10000) L_0x2a053f0/d; +L_0x2a054b0/d .functor AND 1, L_0x2a051d0, L_0x2a053f0, C4<1>, C4<1>; +L_0x2a054b0 .delay (20000,20000,20000) L_0x2a054b0/d; +L_0x2a05600/d .functor AND 1, L_0x2a035f0, L_0x2a05920, C4<1>, C4<1>; +L_0x2a05600 .delay (20000,20000,20000) L_0x2a05600/d; +L_0x2a05750/d .functor OR 1, L_0x2a054b0, L_0x2a05600, C4<0>, C4<0>; +L_0x2a05750 .delay (20000,20000,20000) L_0x2a05750/d; +v0x28adb30_0 .net "S", 0 0, L_0x2a05920; 1 drivers +v0x28adbb0_0 .alias "in0", 0 0, v0x28aea40_0; +v0x28adc50_0 .alias "in1", 0 0, v0x28ae6f0_0; +v0x28adcf0_0 .net "nS", 0 0, L_0x2a053f0; 1 drivers +v0x28add70_0 .net "out0", 0 0, L_0x2a054b0; 1 drivers +v0x28ade10_0 .net "out1", 0 0, L_0x2a05600; 1 drivers +v0x28adef0_0 .alias "outfinal", 0 0, v0x28ae9c0_0; +S_0x28ac410 .scope generate, "orbits[23]" "orbits[23]" 3 258, 3 258, S_0x28a2590; + .timescale -9 -12; +P_0x28ac508 .param/l "i" 3 258, +C4<010111>; +S_0x28ac580 .scope module, "attempt" "OrNorXor" 3 260, 3 165, S_0x28ac410; + .timescale -9 -12; +L_0x2a04950/d .functor NOR 1, L_0x2a06d60, L_0x2a05a60, C4<0>, C4<0>; +L_0x2a04950 .delay (10000,10000,10000) L_0x2a04950/d; +L_0x2a05cd0/d .functor NOT 1, L_0x2a04950, C4<0>, C4<0>, C4<0>; +L_0x2a05cd0 .delay (10000,10000,10000) L_0x2a05cd0/d; +L_0x2a05de0/d .functor NAND 1, L_0x2a06d60, L_0x2a05a60, C4<1>, C4<1>; +L_0x2a05de0 .delay (10000,10000,10000) L_0x2a05de0/d; +L_0x2a05f40/d .functor NAND 1, L_0x2a05de0, L_0x2a05cd0, C4<1>, C4<1>; +L_0x2a05f40 .delay (10000,10000,10000) L_0x2a05f40/d; +L_0x2a06050/d .functor NOT 1, L_0x2a05f40, C4<0>, C4<0>, C4<0>; +L_0x2a06050 .delay (10000,10000,10000) L_0x2a06050/d; +v0x28ad130_0 .net "A", 0 0, L_0x2a06d60; 1 drivers +v0x28ad1d0_0 .net "AnandB", 0 0, L_0x2a05de0; 1 drivers +v0x28ad270_0 .net "AnorB", 0 0, L_0x2a04950; 1 drivers +v0x28ad320_0 .net "AorB", 0 0, L_0x2a05cd0; 1 drivers +v0x28ad400_0 .net "AxorB", 0 0, L_0x2a06050; 1 drivers +v0x28ad4b0_0 .net "B", 0 0, L_0x2a05a60; 1 drivers +v0x28ad570_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x28ad5f0_0 .net "OrNorXorOut", 0 0, L_0x2a06a50; 1 drivers +v0x28ad670_0 .net "XorNor", 0 0, L_0x2a064d0; 1 drivers +v0x28ad740_0 .net "nXor", 0 0, L_0x2a05f40; 1 drivers +L_0x2a06650 .part v0x2960210_0, 2, 1; +L_0x2a06c20 .part v0x2960210_0, 0, 1; +S_0x28acbc0 .scope module, "mux0" "TwoInMux" 3 184, 3 109, S_0x28ac580; + .timescale -9 -12; +L_0x2a061b0/d .functor NOT 1, L_0x2a06650, C4<0>, C4<0>, C4<0>; +L_0x2a061b0 .delay (10000,10000,10000) L_0x2a061b0/d; +L_0x2a06270/d .functor AND 1, L_0x2a06050, L_0x2a061b0, C4<1>, C4<1>; +L_0x2a06270 .delay (20000,20000,20000) L_0x2a06270/d; +L_0x2a06380/d .functor AND 1, L_0x2a04950, L_0x2a06650, C4<1>, C4<1>; +L_0x2a06380 .delay (20000,20000,20000) L_0x2a06380/d; +L_0x2a064d0/d .functor OR 1, L_0x2a06270, L_0x2a06380, C4<0>, C4<0>; +L_0x2a064d0 .delay (20000,20000,20000) L_0x2a064d0/d; +v0x28accb0_0 .net "S", 0 0, L_0x2a06650; 1 drivers +v0x28acd70_0 .alias "in0", 0 0, v0x28ad400_0; +v0x28ace10_0 .alias "in1", 0 0, v0x28ad270_0; +v0x28aceb0_0 .net "nS", 0 0, L_0x2a061b0; 1 drivers +v0x28acf30_0 .net "out0", 0 0, L_0x2a06270; 1 drivers +v0x28acfd0_0 .net "out1", 0 0, L_0x2a06380; 1 drivers +v0x28ad0b0_0 .alias "outfinal", 0 0, v0x28ad670_0; +S_0x28ac670 .scope module, "mux1" "TwoInMux" 3 185, 3 109, S_0x28ac580; + .timescale -9 -12; +L_0x2a066f0/d .functor NOT 1, L_0x2a06c20, C4<0>, C4<0>, C4<0>; +L_0x2a066f0 .delay (10000,10000,10000) L_0x2a066f0/d; +L_0x2a067b0/d .functor AND 1, L_0x2a064d0, L_0x2a066f0, C4<1>, C4<1>; +L_0x2a067b0 .delay (20000,20000,20000) L_0x2a067b0/d; +L_0x2a06900/d .functor AND 1, L_0x2a05cd0, L_0x2a06c20, C4<1>, C4<1>; +L_0x2a06900 .delay (20000,20000,20000) L_0x2a06900/d; +L_0x2a06a50/d .functor OR 1, L_0x2a067b0, L_0x2a06900, C4<0>, C4<0>; +L_0x2a06a50 .delay (20000,20000,20000) L_0x2a06a50/d; +v0x28ac760_0 .net "S", 0 0, L_0x2a06c20; 1 drivers +v0x28ac7e0_0 .alias "in0", 0 0, v0x28ad670_0; +v0x28ac880_0 .alias "in1", 0 0, v0x28ad320_0; +v0x28ac920_0 .net "nS", 0 0, L_0x2a066f0; 1 drivers +v0x28ac9a0_0 .net "out0", 0 0, L_0x2a067b0; 1 drivers +v0x28aca40_0 .net "out1", 0 0, L_0x2a06900; 1 drivers +v0x28acb20_0 .alias "outfinal", 0 0, v0x28ad5f0_0; +S_0x28ab0e0 .scope generate, "orbits[24]" "orbits[24]" 3 258, 3 258, S_0x28a2590; + .timescale -9 -12; +P_0x28aadf8 .param/l "i" 3 258, +C4<011000>; +S_0x28ab210 .scope module, "attempt" "OrNorXor" 3 260, 3 165, S_0x28ab0e0; + .timescale -9 -12; +L_0x2a05b00/d .functor NOR 1, L_0x2a06e00, L_0x2a06ea0, C4<0>, C4<0>; +L_0x2a05b00 .delay (10000,10000,10000) L_0x2a05b00/d; +L_0x2a05bf0/d .functor NOT 1, L_0x2a05b00, C4<0>, C4<0>, C4<0>; +L_0x2a05bf0 .delay (10000,10000,10000) L_0x2a05bf0/d; +L_0x2a070e0/d .functor NAND 1, L_0x2a06e00, L_0x2a06ea0, C4<1>, C4<1>; +L_0x2a070e0 .delay (10000,10000,10000) L_0x2a070e0/d; +L_0x2a07240/d .functor NAND 1, L_0x2a070e0, L_0x2a05bf0, C4<1>, C4<1>; +L_0x2a07240 .delay (10000,10000,10000) L_0x2a07240/d; +L_0x2a07350/d .functor NOT 1, L_0x2a07240, C4<0>, C4<0>, C4<0>; +L_0x2a07350 .delay (10000,10000,10000) L_0x2a07350/d; +v0x28abdc0_0 .net "A", 0 0, L_0x2a06e00; 1 drivers +v0x28abe60_0 .net "AnandB", 0 0, L_0x2a070e0; 1 drivers +v0x28abf00_0 .net "AnorB", 0 0, L_0x2a05b00; 1 drivers +v0x28abfb0_0 .net "AorB", 0 0, L_0x2a05bf0; 1 drivers +v0x28ac030_0 .net "AxorB", 0 0, L_0x2a07350; 1 drivers +v0x28ac0b0_0 .net "B", 0 0, L_0x2a06ea0; 1 drivers +v0x28ac130_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x28ac1b0_0 .net "OrNorXorOut", 0 0, L_0x2a07d10; 1 drivers +v0x28ac260_0 .net "XorNor", 0 0, L_0x2a07790; 1 drivers +v0x28ac330_0 .net "nXor", 0 0, L_0x2a07240; 1 drivers +L_0x2a07910 .part v0x2960210_0, 2, 1; +L_0x2a07ee0 .part v0x2960210_0, 0, 1; +S_0x28ab850 .scope module, "mux0" "TwoInMux" 3 184, 3 109, S_0x28ab210; + .timescale -9 -12; +L_0x2a07470/d .functor NOT 1, L_0x2a07910, C4<0>, C4<0>, C4<0>; +L_0x2a07470 .delay (10000,10000,10000) L_0x2a07470/d; +L_0x2a07530/d .functor AND 1, L_0x2a07350, L_0x2a07470, C4<1>, C4<1>; +L_0x2a07530 .delay (20000,20000,20000) L_0x2a07530/d; +L_0x2a07640/d .functor AND 1, L_0x2a05b00, L_0x2a07910, C4<1>, C4<1>; +L_0x2a07640 .delay (20000,20000,20000) L_0x2a07640/d; +L_0x2a07790/d .functor OR 1, L_0x2a07530, L_0x2a07640, C4<0>, C4<0>; +L_0x2a07790 .delay (20000,20000,20000) L_0x2a07790/d; +v0x28ab940_0 .net "S", 0 0, L_0x2a07910; 1 drivers +v0x28aba00_0 .alias "in0", 0 0, v0x28ac030_0; +v0x28abaa0_0 .alias "in1", 0 0, v0x28abf00_0; +v0x28abb40_0 .net "nS", 0 0, L_0x2a07470; 1 drivers +v0x28abbc0_0 .net "out0", 0 0, L_0x2a07530; 1 drivers +v0x28abc60_0 .net "out1", 0 0, L_0x2a07640; 1 drivers +v0x28abd40_0 .alias "outfinal", 0 0, v0x28ac260_0; +S_0x28ab300 .scope module, "mux1" "TwoInMux" 3 185, 3 109, S_0x28ab210; + .timescale -9 -12; +L_0x2a079b0/d .functor NOT 1, L_0x2a07ee0, C4<0>, C4<0>, C4<0>; +L_0x2a079b0 .delay (10000,10000,10000) L_0x2a079b0/d; +L_0x2a07a70/d .functor AND 1, L_0x2a07790, L_0x2a079b0, C4<1>, C4<1>; +L_0x2a07a70 .delay (20000,20000,20000) L_0x2a07a70/d; +L_0x2a07bc0/d .functor AND 1, L_0x2a05bf0, L_0x2a07ee0, C4<1>, C4<1>; +L_0x2a07bc0 .delay (20000,20000,20000) L_0x2a07bc0/d; +L_0x2a07d10/d .functor OR 1, L_0x2a07a70, L_0x2a07bc0, C4<0>, C4<0>; +L_0x2a07d10 .delay (20000,20000,20000) L_0x2a07d10/d; +v0x28ab3f0_0 .net "S", 0 0, L_0x2a07ee0; 1 drivers +v0x28ab470_0 .alias "in0", 0 0, v0x28ac260_0; +v0x28ab510_0 .alias "in1", 0 0, v0x28abfb0_0; +v0x28ab5b0_0 .net "nS", 0 0, L_0x2a079b0; 1 drivers +v0x28ab630_0 .net "out0", 0 0, L_0x2a07a70; 1 drivers +v0x28ab6d0_0 .net "out1", 0 0, L_0x2a07bc0; 1 drivers +v0x28ab7b0_0 .alias "outfinal", 0 0, v0x28ac1b0_0; +S_0x28a9d10 .scope generate, "orbits[25]" "orbits[25]" 3 258, 3 258, S_0x28a2590; + .timescale -9 -12; +P_0x28a9a28 .param/l "i" 3 258, +C4<011001>; +S_0x28a9e40 .scope module, "attempt" "OrNorXor" 3 260, 3 165, S_0x28a9d10; + .timescale -9 -12; +L_0x2a06f40/d .functor NOR 1, L_0x2a09320, L_0x2a08020, C4<0>, C4<0>; +L_0x2a06f40 .delay (10000,10000,10000) L_0x2a06f40/d; +L_0x2a08270/d .functor NOT 1, L_0x2a06f40, C4<0>, C4<0>, C4<0>; +L_0x2a08270 .delay (10000,10000,10000) L_0x2a08270/d; +L_0x2a083a0/d .functor NAND 1, L_0x2a09320, L_0x2a08020, C4<1>, C4<1>; +L_0x2a083a0 .delay (10000,10000,10000) L_0x2a083a0/d; +L_0x2a08500/d .functor NAND 1, L_0x2a083a0, L_0x2a08270, C4<1>, C4<1>; +L_0x2a08500 .delay (10000,10000,10000) L_0x2a08500/d; +L_0x2a08610/d .functor NOT 1, L_0x2a08500, C4<0>, C4<0>, C4<0>; +L_0x2a08610 .delay (10000,10000,10000) L_0x2a08610/d; +v0x28aa9f0_0 .net "A", 0 0, L_0x2a09320; 1 drivers +v0x28aaa90_0 .net "AnandB", 0 0, L_0x2a083a0; 1 drivers +v0x28aab30_0 .net "AnorB", 0 0, L_0x2a06f40; 1 drivers +v0x28aabe0_0 .net "AorB", 0 0, L_0x2a08270; 1 drivers +v0x28aacc0_0 .net "AxorB", 0 0, L_0x2a08610; 1 drivers +v0x28aad70_0 .net "B", 0 0, L_0x2a08020; 1 drivers +v0x28aae30_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x28aaeb0_0 .net "OrNorXorOut", 0 0, L_0x2a09010; 1 drivers +v0x28aaf30_0 .net "XorNor", 0 0, L_0x2a08a90; 1 drivers +v0x28ab000_0 .net "nXor", 0 0, L_0x2a08500; 1 drivers +L_0x2a08c10 .part v0x2960210_0, 2, 1; +L_0x2a091e0 .part v0x2960210_0, 0, 1; +S_0x28aa480 .scope module, "mux0" "TwoInMux" 3 184, 3 109, S_0x28a9e40; + .timescale -9 -12; +L_0x2a08770/d .functor NOT 1, L_0x2a08c10, C4<0>, C4<0>, C4<0>; +L_0x2a08770 .delay (10000,10000,10000) L_0x2a08770/d; +L_0x2a08830/d .functor AND 1, L_0x2a08610, L_0x2a08770, C4<1>, C4<1>; +L_0x2a08830 .delay (20000,20000,20000) L_0x2a08830/d; +L_0x2a08940/d .functor AND 1, L_0x2a06f40, L_0x2a08c10, C4<1>, C4<1>; +L_0x2a08940 .delay (20000,20000,20000) L_0x2a08940/d; +L_0x2a08a90/d .functor OR 1, L_0x2a08830, L_0x2a08940, C4<0>, C4<0>; +L_0x2a08a90 .delay (20000,20000,20000) L_0x2a08a90/d; +v0x28aa570_0 .net "S", 0 0, L_0x2a08c10; 1 drivers +v0x28aa630_0 .alias "in0", 0 0, v0x28aacc0_0; +v0x28aa6d0_0 .alias "in1", 0 0, v0x28aab30_0; +v0x28aa770_0 .net "nS", 0 0, L_0x2a08770; 1 drivers +v0x28aa7f0_0 .net "out0", 0 0, L_0x2a08830; 1 drivers +v0x28aa890_0 .net "out1", 0 0, L_0x2a08940; 1 drivers +v0x28aa970_0 .alias "outfinal", 0 0, v0x28aaf30_0; +S_0x28a9f30 .scope module, "mux1" "TwoInMux" 3 185, 3 109, S_0x28a9e40; + .timescale -9 -12; +L_0x2a08cb0/d .functor NOT 1, L_0x2a091e0, C4<0>, C4<0>, C4<0>; +L_0x2a08cb0 .delay (10000,10000,10000) L_0x2a08cb0/d; +L_0x2a08d70/d .functor AND 1, L_0x2a08a90, L_0x2a08cb0, C4<1>, C4<1>; +L_0x2a08d70 .delay (20000,20000,20000) L_0x2a08d70/d; +L_0x2a08ec0/d .functor AND 1, L_0x2a08270, L_0x2a091e0, C4<1>, C4<1>; +L_0x2a08ec0 .delay (20000,20000,20000) L_0x2a08ec0/d; +L_0x2a09010/d .functor OR 1, L_0x2a08d70, L_0x2a08ec0, C4<0>, C4<0>; +L_0x2a09010 .delay (20000,20000,20000) L_0x2a09010/d; +v0x28aa020_0 .net "S", 0 0, L_0x2a091e0; 1 drivers +v0x28aa0a0_0 .alias "in0", 0 0, v0x28aaf30_0; +v0x28aa140_0 .alias "in1", 0 0, v0x28aabe0_0; +v0x28aa1e0_0 .net "nS", 0 0, L_0x2a08cb0; 1 drivers +v0x28aa260_0 .net "out0", 0 0, L_0x2a08d70; 1 drivers +v0x28aa300_0 .net "out1", 0 0, L_0x2a08ec0; 1 drivers +v0x28aa3e0_0 .alias "outfinal", 0 0, v0x28aaeb0_0; +S_0x28a8940 .scope generate, "orbits[26]" "orbits[26]" 3 258, 3 258, S_0x28a2590; + .timescale -9 -12; +P_0x28a8658 .param/l "i" 3 258, +C4<011010>; +S_0x28a8a70 .scope module, "attempt" "OrNorXor" 3 260, 3 165, S_0x28a8940; + .timescale -9 -12; +L_0x2a080c0/d .functor NOR 1, L_0x2a093c0, L_0x2a09460, C4<0>, C4<0>; +L_0x2a080c0 .delay (10000,10000,10000) L_0x2a080c0/d; +L_0x2a081b0/d .functor NOT 1, L_0x2a080c0, C4<0>, C4<0>, C4<0>; +L_0x2a081b0 .delay (10000,10000,10000) L_0x2a081b0/d; +L_0x2a09690/d .functor NAND 1, L_0x2a093c0, L_0x2a09460, C4<1>, C4<1>; +L_0x2a09690 .delay (10000,10000,10000) L_0x2a09690/d; +L_0x2a097f0/d .functor NAND 1, L_0x2a09690, L_0x2a081b0, C4<1>, C4<1>; +L_0x2a097f0 .delay (10000,10000,10000) L_0x2a097f0/d; +L_0x2a09900/d .functor NOT 1, L_0x2a097f0, C4<0>, C4<0>, C4<0>; +L_0x2a09900 .delay (10000,10000,10000) L_0x2a09900/d; +v0x28a9620_0 .net "A", 0 0, L_0x2a093c0; 1 drivers +v0x28a96c0_0 .net "AnandB", 0 0, L_0x2a09690; 1 drivers +v0x28a9760_0 .net "AnorB", 0 0, L_0x2a080c0; 1 drivers +v0x28a9810_0 .net "AorB", 0 0, L_0x2a081b0; 1 drivers +v0x28a98f0_0 .net "AxorB", 0 0, L_0x2a09900; 1 drivers +v0x28a99a0_0 .net "B", 0 0, L_0x2a09460; 1 drivers +v0x28a9a60_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x28a9ae0_0 .net "OrNorXorOut", 0 0, L_0x2a0a300; 1 drivers +v0x28a9b60_0 .net "XorNor", 0 0, L_0x2a09d80; 1 drivers +v0x28a9c30_0 .net "nXor", 0 0, L_0x2a097f0; 1 drivers +L_0x2a09f00 .part v0x2960210_0, 2, 1; +L_0x2a0a4d0 .part v0x2960210_0, 0, 1; +S_0x28a90b0 .scope module, "mux0" "TwoInMux" 3 184, 3 109, S_0x28a8a70; + .timescale -9 -12; +L_0x2a09a60/d .functor NOT 1, L_0x2a09f00, C4<0>, C4<0>, C4<0>; +L_0x2a09a60 .delay (10000,10000,10000) L_0x2a09a60/d; +L_0x2a09b20/d .functor AND 1, L_0x2a09900, L_0x2a09a60, C4<1>, C4<1>; +L_0x2a09b20 .delay (20000,20000,20000) L_0x2a09b20/d; +L_0x2a09c30/d .functor AND 1, L_0x2a080c0, L_0x2a09f00, C4<1>, C4<1>; +L_0x2a09c30 .delay (20000,20000,20000) L_0x2a09c30/d; +L_0x2a09d80/d .functor OR 1, L_0x2a09b20, L_0x2a09c30, C4<0>, C4<0>; +L_0x2a09d80 .delay (20000,20000,20000) L_0x2a09d80/d; +v0x28a91a0_0 .net "S", 0 0, L_0x2a09f00; 1 drivers +v0x28a9260_0 .alias "in0", 0 0, v0x28a98f0_0; +v0x28a9300_0 .alias "in1", 0 0, v0x28a9760_0; +v0x28a93a0_0 .net "nS", 0 0, L_0x2a09a60; 1 drivers +v0x28a9420_0 .net "out0", 0 0, L_0x2a09b20; 1 drivers +v0x28a94c0_0 .net "out1", 0 0, L_0x2a09c30; 1 drivers +v0x28a95a0_0 .alias "outfinal", 0 0, v0x28a9b60_0; +S_0x28a8b60 .scope module, "mux1" "TwoInMux" 3 185, 3 109, S_0x28a8a70; + .timescale -9 -12; +L_0x2a09fa0/d .functor NOT 1, L_0x2a0a4d0, C4<0>, C4<0>, C4<0>; +L_0x2a09fa0 .delay (10000,10000,10000) L_0x2a09fa0/d; +L_0x2a0a060/d .functor AND 1, L_0x2a09d80, L_0x2a09fa0, C4<1>, C4<1>; +L_0x2a0a060 .delay (20000,20000,20000) L_0x2a0a060/d; +L_0x2a0a1b0/d .functor AND 1, L_0x2a081b0, L_0x2a0a4d0, C4<1>, C4<1>; +L_0x2a0a1b0 .delay (20000,20000,20000) L_0x2a0a1b0/d; +L_0x2a0a300/d .functor OR 1, L_0x2a0a060, L_0x2a0a1b0, C4<0>, C4<0>; +L_0x2a0a300 .delay (20000,20000,20000) L_0x2a0a300/d; +v0x28a8c50_0 .net "S", 0 0, L_0x2a0a4d0; 1 drivers +v0x28a8cd0_0 .alias "in0", 0 0, v0x28a9b60_0; +v0x28a8d70_0 .alias "in1", 0 0, v0x28a9810_0; +v0x28a8e10_0 .net "nS", 0 0, L_0x2a09fa0; 1 drivers +v0x28a8e90_0 .net "out0", 0 0, L_0x2a0a060; 1 drivers +v0x28a8f30_0 .net "out1", 0 0, L_0x2a0a1b0; 1 drivers +v0x28a9010_0 .alias "outfinal", 0 0, v0x28a9ae0_0; +S_0x28a7570 .scope generate, "orbits[27]" "orbits[27]" 3 258, 3 258, S_0x28a2590; + .timescale -9 -12; +P_0x28a7288 .param/l "i" 3 258, +C4<011011>; +S_0x28a76a0 .scope module, "attempt" "OrNorXor" 3 260, 3 165, S_0x28a7570; + .timescale -9 -12; +L_0x2a09500/d .functor NOR 1, L_0x2a0b920, L_0x2a0a610, C4<0>, C4<0>; +L_0x2a09500 .delay (10000,10000,10000) L_0x2a09500/d; +L_0x2a0a890/d .functor NOT 1, L_0x2a09500, C4<0>, C4<0>, C4<0>; +L_0x2a0a890 .delay (10000,10000,10000) L_0x2a0a890/d; +L_0x2a0a9a0/d .functor NAND 1, L_0x2a0b920, L_0x2a0a610, C4<1>, C4<1>; +L_0x2a0a9a0 .delay (10000,10000,10000) L_0x2a0a9a0/d; +L_0x2a0ab00/d .functor NAND 1, L_0x2a0a9a0, L_0x2a0a890, C4<1>, C4<1>; +L_0x2a0ab00 .delay (10000,10000,10000) L_0x2a0ab00/d; +L_0x2a0ac10/d .functor NOT 1, L_0x2a0ab00, C4<0>, C4<0>, C4<0>; +L_0x2a0ac10 .delay (10000,10000,10000) L_0x2a0ac10/d; +v0x28a8250_0 .net "A", 0 0, L_0x2a0b920; 1 drivers +v0x28a82f0_0 .net "AnandB", 0 0, L_0x2a0a9a0; 1 drivers +v0x28a8390_0 .net "AnorB", 0 0, L_0x2a09500; 1 drivers +v0x28a8440_0 .net "AorB", 0 0, L_0x2a0a890; 1 drivers +v0x28a8520_0 .net "AxorB", 0 0, L_0x2a0ac10; 1 drivers +v0x28a85d0_0 .net "B", 0 0, L_0x2a0a610; 1 drivers +v0x28a8690_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x28a8710_0 .net "OrNorXorOut", 0 0, L_0x2a0b610; 1 drivers +v0x28a8790_0 .net "XorNor", 0 0, L_0x2a0b090; 1 drivers +v0x28a8860_0 .net "nXor", 0 0, L_0x2a0ab00; 1 drivers +L_0x2a0b210 .part v0x2960210_0, 2, 1; +L_0x2a0b7e0 .part v0x2960210_0, 0, 1; +S_0x28a7ce0 .scope module, "mux0" "TwoInMux" 3 184, 3 109, S_0x28a76a0; + .timescale -9 -12; +L_0x2a0ad70/d .functor NOT 1, L_0x2a0b210, C4<0>, C4<0>, C4<0>; +L_0x2a0ad70 .delay (10000,10000,10000) L_0x2a0ad70/d; +L_0x2a0ae30/d .functor AND 1, L_0x2a0ac10, L_0x2a0ad70, C4<1>, C4<1>; +L_0x2a0ae30 .delay (20000,20000,20000) L_0x2a0ae30/d; +L_0x2a0af40/d .functor AND 1, L_0x2a09500, L_0x2a0b210, C4<1>, C4<1>; +L_0x2a0af40 .delay (20000,20000,20000) L_0x2a0af40/d; +L_0x2a0b090/d .functor OR 1, L_0x2a0ae30, L_0x2a0af40, C4<0>, C4<0>; +L_0x2a0b090 .delay (20000,20000,20000) L_0x2a0b090/d; +v0x28a7dd0_0 .net "S", 0 0, L_0x2a0b210; 1 drivers +v0x28a7e90_0 .alias "in0", 0 0, v0x28a8520_0; +v0x28a7f30_0 .alias "in1", 0 0, v0x28a8390_0; +v0x28a7fd0_0 .net "nS", 0 0, L_0x2a0ad70; 1 drivers +v0x28a8050_0 .net "out0", 0 0, L_0x2a0ae30; 1 drivers +v0x28a80f0_0 .net "out1", 0 0, L_0x2a0af40; 1 drivers +v0x28a81d0_0 .alias "outfinal", 0 0, v0x28a8790_0; +S_0x28a7790 .scope module, "mux1" "TwoInMux" 3 185, 3 109, S_0x28a76a0; + .timescale -9 -12; +L_0x2a0b2b0/d .functor NOT 1, L_0x2a0b7e0, C4<0>, C4<0>, C4<0>; +L_0x2a0b2b0 .delay (10000,10000,10000) L_0x2a0b2b0/d; +L_0x2a0b370/d .functor AND 1, L_0x2a0b090, L_0x2a0b2b0, C4<1>, C4<1>; +L_0x2a0b370 .delay (20000,20000,20000) L_0x2a0b370/d; +L_0x2a0b4c0/d .functor AND 1, L_0x2a0a890, L_0x2a0b7e0, C4<1>, C4<1>; +L_0x2a0b4c0 .delay (20000,20000,20000) L_0x2a0b4c0/d; +L_0x2a0b610/d .functor OR 1, L_0x2a0b370, L_0x2a0b4c0, C4<0>, C4<0>; +L_0x2a0b610 .delay (20000,20000,20000) L_0x2a0b610/d; +v0x28a7880_0 .net "S", 0 0, L_0x2a0b7e0; 1 drivers +v0x28a7900_0 .alias "in0", 0 0, v0x28a8790_0; +v0x28a79a0_0 .alias "in1", 0 0, v0x28a8440_0; +v0x28a7a40_0 .net "nS", 0 0, L_0x2a0b2b0; 1 drivers +v0x28a7ac0_0 .net "out0", 0 0, L_0x2a0b370; 1 drivers +v0x28a7b60_0 .net "out1", 0 0, L_0x2a0b4c0; 1 drivers +v0x28a7c40_0 .alias "outfinal", 0 0, v0x28a8710_0; +S_0x28a61a0 .scope generate, "orbits[28]" "orbits[28]" 3 258, 3 258, S_0x28a2590; + .timescale -9 -12; +P_0x28a5eb8 .param/l "i" 3 258, +C4<011100>; +S_0x28a62d0 .scope module, "attempt" "OrNorXor" 3 260, 3 165, S_0x28a61a0; + .timescale -9 -12; +L_0x2a0a6b0/d .functor NOR 1, L_0x2a0b9c0, L_0x2a0ba60, C4<0>, C4<0>; +L_0x2a0a6b0 .delay (10000,10000,10000) L_0x2a0a6b0/d; +L_0x2a0a7a0/d .functor NOT 1, L_0x2a0a6b0, C4<0>, C4<0>, C4<0>; +L_0x2a0a7a0 .delay (10000,10000,10000) L_0x2a0a7a0/d; +L_0x2a0bca0/d .functor NAND 1, L_0x2a0b9c0, L_0x2a0ba60, C4<1>, C4<1>; +L_0x2a0bca0 .delay (10000,10000,10000) L_0x2a0bca0/d; +L_0x2a0be00/d .functor NAND 1, L_0x2a0bca0, L_0x2a0a7a0, C4<1>, C4<1>; +L_0x2a0be00 .delay (10000,10000,10000) L_0x2a0be00/d; +L_0x2a0bf10/d .functor NOT 1, L_0x2a0be00, C4<0>, C4<0>, C4<0>; +L_0x2a0bf10 .delay (10000,10000,10000) L_0x2a0bf10/d; +v0x28a6e80_0 .net "A", 0 0, L_0x2a0b9c0; 1 drivers +v0x28a6f20_0 .net "AnandB", 0 0, L_0x2a0bca0; 1 drivers +v0x28a6fc0_0 .net "AnorB", 0 0, L_0x2a0a6b0; 1 drivers +v0x28a7070_0 .net "AorB", 0 0, L_0x2a0a7a0; 1 drivers +v0x28a7150_0 .net "AxorB", 0 0, L_0x2a0bf10; 1 drivers +v0x28a7200_0 .net "B", 0 0, L_0x2a0ba60; 1 drivers +v0x28a72c0_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x28a7340_0 .net "OrNorXorOut", 0 0, L_0x2a0c910; 1 drivers +v0x28a73c0_0 .net "XorNor", 0 0, L_0x2a0c390; 1 drivers +v0x28a7490_0 .net "nXor", 0 0, L_0x2a0be00; 1 drivers +L_0x2a0c510 .part v0x2960210_0, 2, 1; +L_0x2a0cae0 .part v0x2960210_0, 0, 1; +S_0x28a6910 .scope module, "mux0" "TwoInMux" 3 184, 3 109, S_0x28a62d0; + .timescale -9 -12; +L_0x2a0c070/d .functor NOT 1, L_0x2a0c510, C4<0>, C4<0>, C4<0>; +L_0x2a0c070 .delay (10000,10000,10000) L_0x2a0c070/d; +L_0x2a0c130/d .functor AND 1, L_0x2a0bf10, L_0x2a0c070, C4<1>, C4<1>; +L_0x2a0c130 .delay (20000,20000,20000) L_0x2a0c130/d; +L_0x2a0c240/d .functor AND 1, L_0x2a0a6b0, L_0x2a0c510, C4<1>, C4<1>; +L_0x2a0c240 .delay (20000,20000,20000) L_0x2a0c240/d; +L_0x2a0c390/d .functor OR 1, L_0x2a0c130, L_0x2a0c240, C4<0>, C4<0>; +L_0x2a0c390 .delay (20000,20000,20000) L_0x2a0c390/d; +v0x28a6a00_0 .net "S", 0 0, L_0x2a0c510; 1 drivers +v0x28a6ac0_0 .alias "in0", 0 0, v0x28a7150_0; +v0x28a6b60_0 .alias "in1", 0 0, v0x28a6fc0_0; +v0x28a6c00_0 .net "nS", 0 0, L_0x2a0c070; 1 drivers +v0x28a6c80_0 .net "out0", 0 0, L_0x2a0c130; 1 drivers +v0x28a6d20_0 .net "out1", 0 0, L_0x2a0c240; 1 drivers +v0x28a6e00_0 .alias "outfinal", 0 0, v0x28a73c0_0; +S_0x28a63c0 .scope module, "mux1" "TwoInMux" 3 185, 3 109, S_0x28a62d0; + .timescale -9 -12; +L_0x2a0c5b0/d .functor NOT 1, L_0x2a0cae0, C4<0>, C4<0>, C4<0>; +L_0x2a0c5b0 .delay (10000,10000,10000) L_0x2a0c5b0/d; +L_0x2a0c670/d .functor AND 1, L_0x2a0c390, L_0x2a0c5b0, C4<1>, C4<1>; +L_0x2a0c670 .delay (20000,20000,20000) L_0x2a0c670/d; +L_0x2a0c7c0/d .functor AND 1, L_0x2a0a7a0, L_0x2a0cae0, C4<1>, C4<1>; +L_0x2a0c7c0 .delay (20000,20000,20000) L_0x2a0c7c0/d; +L_0x2a0c910/d .functor OR 1, L_0x2a0c670, L_0x2a0c7c0, C4<0>, C4<0>; +L_0x2a0c910 .delay (20000,20000,20000) L_0x2a0c910/d; +v0x28a64b0_0 .net "S", 0 0, L_0x2a0cae0; 1 drivers +v0x28a6530_0 .alias "in0", 0 0, v0x28a73c0_0; +v0x28a65d0_0 .alias "in1", 0 0, v0x28a7070_0; +v0x28a6670_0 .net "nS", 0 0, L_0x2a0c5b0; 1 drivers +v0x28a66f0_0 .net "out0", 0 0, L_0x2a0c670; 1 drivers +v0x28a6790_0 .net "out1", 0 0, L_0x2a0c7c0; 1 drivers +v0x28a6870_0 .alias "outfinal", 0 0, v0x28a7340_0; +S_0x28a4dd0 .scope generate, "orbits[29]" "orbits[29]" 3 258, 3 258, S_0x28a2590; + .timescale -9 -12; +P_0x28a4ae8 .param/l "i" 3 258, +C4<011101>; +S_0x28a4f00 .scope module, "attempt" "OrNorXor" 3 260, 3 165, S_0x28a4dd0; + .timescale -9 -12; +L_0x2a0bb00/d .functor NOR 1, L_0x29f9f90, L_0x29fa030, C4<0>, C4<0>; +L_0x2a0bb00 .delay (10000,10000,10000) L_0x2a0bb00/d; +L_0x2a0bbf0/d .functor NOT 1, L_0x2a0bb00, C4<0>, C4<0>, C4<0>; +L_0x2a0bbf0 .delay (10000,10000,10000) L_0x2a0bbf0/d; +L_0x2a0cfa0/d .functor NAND 1, L_0x29f9f90, L_0x29fa030, C4<1>, C4<1>; +L_0x2a0cfa0 .delay (10000,10000,10000) L_0x2a0cfa0/d; +L_0x2a0d100/d .functor NAND 1, L_0x2a0cfa0, L_0x2a0bbf0, C4<1>, C4<1>; +L_0x2a0d100 .delay (10000,10000,10000) L_0x2a0d100/d; +L_0x2a0d210/d .functor NOT 1, L_0x2a0d100, C4<0>, C4<0>, C4<0>; +L_0x2a0d210 .delay (10000,10000,10000) L_0x2a0d210/d; +v0x28a5ab0_0 .net "A", 0 0, L_0x29f9f90; 1 drivers +v0x28a5b50_0 .net "AnandB", 0 0, L_0x2a0cfa0; 1 drivers +v0x28a5bf0_0 .net "AnorB", 0 0, L_0x2a0bb00; 1 drivers +v0x28a5ca0_0 .net "AorB", 0 0, L_0x2a0bbf0; 1 drivers +v0x28a5d80_0 .net "AxorB", 0 0, L_0x2a0d210; 1 drivers +v0x28a5e30_0 .net "B", 0 0, L_0x29fa030; 1 drivers +v0x28a5ef0_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x28a5f70_0 .net "OrNorXorOut", 0 0, L_0x2a0dc10; 1 drivers +v0x28a5ff0_0 .net "XorNor", 0 0, L_0x2a0d690; 1 drivers +v0x28a60c0_0 .net "nXor", 0 0, L_0x2a0d100; 1 drivers +L_0x2a0d810 .part v0x2960210_0, 2, 1; +L_0x2a0dde0 .part v0x2960210_0, 0, 1; +S_0x28a5540 .scope module, "mux0" "TwoInMux" 3 184, 3 109, S_0x28a4f00; + .timescale -9 -12; +L_0x2a0d370/d .functor NOT 1, L_0x2a0d810, C4<0>, C4<0>, C4<0>; +L_0x2a0d370 .delay (10000,10000,10000) L_0x2a0d370/d; +L_0x2a0d430/d .functor AND 1, L_0x2a0d210, L_0x2a0d370, C4<1>, C4<1>; +L_0x2a0d430 .delay (20000,20000,20000) L_0x2a0d430/d; +L_0x2a0d540/d .functor AND 1, L_0x2a0bb00, L_0x2a0d810, C4<1>, C4<1>; +L_0x2a0d540 .delay (20000,20000,20000) L_0x2a0d540/d; +L_0x2a0d690/d .functor OR 1, L_0x2a0d430, L_0x2a0d540, C4<0>, C4<0>; +L_0x2a0d690 .delay (20000,20000,20000) L_0x2a0d690/d; +v0x28a5630_0 .net "S", 0 0, L_0x2a0d810; 1 drivers +v0x28a56f0_0 .alias "in0", 0 0, v0x28a5d80_0; +v0x28a5790_0 .alias "in1", 0 0, v0x28a5bf0_0; +v0x28a5830_0 .net "nS", 0 0, L_0x2a0d370; 1 drivers +v0x28a58b0_0 .net "out0", 0 0, L_0x2a0d430; 1 drivers +v0x28a5950_0 .net "out1", 0 0, L_0x2a0d540; 1 drivers +v0x28a5a30_0 .alias "outfinal", 0 0, v0x28a5ff0_0; +S_0x28a4ff0 .scope module, "mux1" "TwoInMux" 3 185, 3 109, S_0x28a4f00; + .timescale -9 -12; +L_0x2a0d8b0/d .functor NOT 1, L_0x2a0dde0, C4<0>, C4<0>, C4<0>; +L_0x2a0d8b0 .delay (10000,10000,10000) L_0x2a0d8b0/d; +L_0x2a0d970/d .functor AND 1, L_0x2a0d690, L_0x2a0d8b0, C4<1>, C4<1>; +L_0x2a0d970 .delay (20000,20000,20000) L_0x2a0d970/d; +L_0x2a0dac0/d .functor AND 1, L_0x2a0bbf0, L_0x2a0dde0, C4<1>, C4<1>; +L_0x2a0dac0 .delay (20000,20000,20000) L_0x2a0dac0/d; +L_0x2a0dc10/d .functor OR 1, L_0x2a0d970, L_0x2a0dac0, C4<0>, C4<0>; +L_0x2a0dc10 .delay (20000,20000,20000) L_0x2a0dc10/d; +v0x28a50e0_0 .net "S", 0 0, L_0x2a0dde0; 1 drivers +v0x28a5160_0 .alias "in0", 0 0, v0x28a5ff0_0; +v0x28a5200_0 .alias "in1", 0 0, v0x28a5ca0_0; +v0x28a52a0_0 .net "nS", 0 0, L_0x2a0d8b0; 1 drivers +v0x28a5320_0 .net "out0", 0 0, L_0x2a0d970; 1 drivers +v0x28a53c0_0 .net "out1", 0 0, L_0x2a0dac0; 1 drivers +v0x28a54a0_0 .alias "outfinal", 0 0, v0x28a5f70_0; +S_0x28a3a00 .scope generate, "orbits[30]" "orbits[30]" 3 258, 3 258, S_0x28a2590; + .timescale -9 -12; +P_0x28a3728 .param/l "i" 3 258, +C4<011110>; +S_0x28a3b30 .scope module, "attempt" "OrNorXor" 3 260, 3 165, S_0x28a3a00; + .timescale -9 -12; +L_0x29fa0d0/d .functor NOR 1, L_0x2a0e330, L_0x2a0e3d0, C4<0>, C4<0>; +L_0x29fa0d0 .delay (10000,10000,10000) L_0x29fa0d0/d; +L_0x2a0cc70/d .functor NOT 1, L_0x29fa0d0, C4<0>, C4<0>, C4<0>; +L_0x2a0cc70 .delay (10000,10000,10000) L_0x2a0cc70/d; +L_0x2a0cda0/d .functor NAND 1, L_0x2a0e330, L_0x2a0e3d0, C4<1>, C4<1>; +L_0x2a0cda0 .delay (10000,10000,10000) L_0x2a0cda0/d; +L_0x2a0e640/d .functor NAND 1, L_0x2a0cda0, L_0x2a0cc70, C4<1>, C4<1>; +L_0x2a0e640 .delay (10000,10000,10000) L_0x2a0e640/d; +L_0x2a0e730/d .functor NOT 1, L_0x2a0e640, C4<0>, C4<0>, C4<0>; +L_0x2a0e730 .delay (10000,10000,10000) L_0x2a0e730/d; +v0x28a46e0_0 .net "A", 0 0, L_0x2a0e330; 1 drivers +v0x28a4780_0 .net "AnandB", 0 0, L_0x2a0cda0; 1 drivers +v0x28a4820_0 .net "AnorB", 0 0, L_0x29fa0d0; 1 drivers +v0x28a48d0_0 .net "AorB", 0 0, L_0x2a0cc70; 1 drivers +v0x28a49b0_0 .net "AxorB", 0 0, L_0x2a0e730; 1 drivers +v0x28a4a60_0 .net "B", 0 0, L_0x2a0e3d0; 1 drivers +v0x28a4b20_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x28a4ba0_0 .net "OrNorXorOut", 0 0, L_0x2a0f010; 1 drivers +v0x28a4c20_0 .net "XorNor", 0 0, L_0x2a0eb30; 1 drivers +v0x28a4cf0_0 .net "nXor", 0 0, L_0x2a0e640; 1 drivers +L_0x2a0ec70 .part v0x2960210_0, 2, 1; +L_0x2a0f1a0 .part v0x2960210_0, 0, 1; +S_0x28a4170 .scope module, "mux0" "TwoInMux" 3 184, 3 109, S_0x28a3b30; + .timescale -9 -12; +L_0x2a0e870/d .functor NOT 1, L_0x2a0ec70, C4<0>, C4<0>, C4<0>; +L_0x2a0e870 .delay (10000,10000,10000) L_0x2a0e870/d; +L_0x2a0e910/d .functor AND 1, L_0x2a0e730, L_0x2a0e870, C4<1>, C4<1>; +L_0x2a0e910 .delay (20000,20000,20000) L_0x2a0e910/d; +L_0x2a0ea00/d .functor AND 1, L_0x29fa0d0, L_0x2a0ec70, C4<1>, C4<1>; +L_0x2a0ea00 .delay (20000,20000,20000) L_0x2a0ea00/d; +L_0x2a0eb30/d .functor OR 1, L_0x2a0e910, L_0x2a0ea00, C4<0>, C4<0>; +L_0x2a0eb30 .delay (20000,20000,20000) L_0x2a0eb30/d; +v0x28a4260_0 .net "S", 0 0, L_0x2a0ec70; 1 drivers +v0x28a4320_0 .alias "in0", 0 0, v0x28a49b0_0; +v0x28a43c0_0 .alias "in1", 0 0, v0x28a4820_0; +v0x28a4460_0 .net "nS", 0 0, L_0x2a0e870; 1 drivers +v0x28a44e0_0 .net "out0", 0 0, L_0x2a0e910; 1 drivers +v0x28a4580_0 .net "out1", 0 0, L_0x2a0ea00; 1 drivers +v0x28a4660_0 .alias "outfinal", 0 0, v0x28a4c20_0; +S_0x28a3c20 .scope module, "mux1" "TwoInMux" 3 185, 3 109, S_0x28a3b30; + .timescale -9 -12; +L_0x2a0ed10/d .functor NOT 1, L_0x2a0f1a0, C4<0>, C4<0>, C4<0>; +L_0x2a0ed10 .delay (10000,10000,10000) L_0x2a0ed10/d; +L_0x2a0edb0/d .functor AND 1, L_0x2a0eb30, L_0x2a0ed10, C4<1>, C4<1>; +L_0x2a0edb0 .delay (20000,20000,20000) L_0x2a0edb0/d; +L_0x2a0eee0/d .functor AND 1, L_0x2a0cc70, L_0x2a0f1a0, C4<1>, C4<1>; +L_0x2a0eee0 .delay (20000,20000,20000) L_0x2a0eee0/d; +L_0x2a0f010/d .functor OR 1, L_0x2a0edb0, L_0x2a0eee0, C4<0>, C4<0>; +L_0x2a0f010 .delay (20000,20000,20000) L_0x2a0f010/d; +v0x28a3d10_0 .net "S", 0 0, L_0x2a0f1a0; 1 drivers +v0x28a3d90_0 .alias "in0", 0 0, v0x28a4c20_0; +v0x28a3e30_0 .alias "in1", 0 0, v0x28a48d0_0; +v0x28a3ed0_0 .net "nS", 0 0, L_0x2a0ed10; 1 drivers +v0x28a3f50_0 .net "out0", 0 0, L_0x2a0edb0; 1 drivers +v0x28a3ff0_0 .net "out1", 0 0, L_0x2a0eee0; 1 drivers +v0x28a40d0_0 .alias "outfinal", 0 0, v0x28a4ba0_0; +S_0x28a2680 .scope generate, "orbits[31]" "orbits[31]" 3 258, 3 258, S_0x28a2590; + .timescale -9 -12; +P_0x28a2208 .param/l "i" 3 258, +C4<011111>; +S_0x28a27b0 .scope module, "attempt" "OrNorXor" 3 260, 3 165, S_0x28a2680; + .timescale -9 -12; +L_0x2a0e470/d .functor NOR 1, L_0x2a105f0, L_0x2a0f2e0, C4<0>, C4<0>; +L_0x2a0e470 .delay (10000,10000,10000) L_0x2a0e470/d; +L_0x2a0e560/d .functor NOT 1, L_0x2a0e470, C4<0>, C4<0>, C4<0>; +L_0x2a0e560 .delay (10000,10000,10000) L_0x2a0e560/d; +L_0x2a0f670/d .functor NAND 1, L_0x2a105f0, L_0x2a0f2e0, C4<1>, C4<1>; +L_0x2a0f670 .delay (10000,10000,10000) L_0x2a0f670/d; +L_0x2a0f7d0/d .functor NAND 1, L_0x2a0f670, L_0x2a0e560, C4<1>, C4<1>; +L_0x2a0f7d0 .delay (10000,10000,10000) L_0x2a0f7d0/d; +L_0x2a0f8e0/d .functor NOT 1, L_0x2a0f7d0, C4<0>, C4<0>, C4<0>; +L_0x2a0f8e0 .delay (10000,10000,10000) L_0x2a0f8e0/d; +v0x28a3380_0 .net "A", 0 0, L_0x2a105f0; 1 drivers +v0x28a3420_0 .net "AnandB", 0 0, L_0x2a0f670; 1 drivers +v0x28a34c0_0 .net "AnorB", 0 0, L_0x2a0e470; 1 drivers +v0x28a3540_0 .net "AorB", 0 0, L_0x2a0e560; 1 drivers +v0x28a35f0_0 .net "AxorB", 0 0, L_0x2a0f8e0; 1 drivers +v0x28a36a0_0 .net "B", 0 0, L_0x2a0f2e0; 1 drivers +v0x28a3760_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x28a37e0_0 .net "OrNorXorOut", 0 0, L_0x2a102e0; 1 drivers +v0x28a38b0_0 .net "XorNor", 0 0, L_0x2a0fd60; 1 drivers +v0x28a3980_0 .net "nXor", 0 0, L_0x2a0f7d0; 1 drivers +L_0x2a0fee0 .part v0x2960210_0, 2, 1; +L_0x2a104b0 .part v0x2960210_0, 0, 1; +S_0x28a2e10 .scope module, "mux0" "TwoInMux" 3 184, 3 109, S_0x28a27b0; + .timescale -9 -12; +L_0x2a0fa40/d .functor NOT 1, L_0x2a0fee0, C4<0>, C4<0>, C4<0>; +L_0x2a0fa40 .delay (10000,10000,10000) L_0x2a0fa40/d; +L_0x2a0fb00/d .functor AND 1, L_0x2a0f8e0, L_0x2a0fa40, C4<1>, C4<1>; +L_0x2a0fb00 .delay (20000,20000,20000) L_0x2a0fb00/d; +L_0x2a0fc10/d .functor AND 1, L_0x2a0e470, L_0x2a0fee0, C4<1>, C4<1>; +L_0x2a0fc10 .delay (20000,20000,20000) L_0x2a0fc10/d; +L_0x2a0fd60/d .functor OR 1, L_0x2a0fb00, L_0x2a0fc10, C4<0>, C4<0>; +L_0x2a0fd60 .delay (20000,20000,20000) L_0x2a0fd60/d; +v0x28a2f00_0 .net "S", 0 0, L_0x2a0fee0; 1 drivers +v0x28a2fc0_0 .alias "in0", 0 0, v0x28a35f0_0; +v0x28a3060_0 .alias "in1", 0 0, v0x28a34c0_0; +v0x28a3100_0 .net "nS", 0 0, L_0x2a0fa40; 1 drivers +v0x28a3180_0 .net "out0", 0 0, L_0x2a0fb00; 1 drivers +v0x28a3220_0 .net "out1", 0 0, L_0x2a0fc10; 1 drivers +v0x28a3300_0 .alias "outfinal", 0 0, v0x28a38b0_0; +S_0x28a28a0 .scope module, "mux1" "TwoInMux" 3 185, 3 109, S_0x28a27b0; + .timescale -9 -12; +L_0x2a0ff80/d .functor NOT 1, L_0x2a104b0, C4<0>, C4<0>, C4<0>; +L_0x2a0ff80 .delay (10000,10000,10000) L_0x2a0ff80/d; +L_0x2a10040/d .functor AND 1, L_0x2a0fd60, L_0x2a0ff80, C4<1>, C4<1>; +L_0x2a10040 .delay (20000,20000,20000) L_0x2a10040/d; +L_0x2a10190/d .functor AND 1, L_0x2a0e560, L_0x2a104b0, C4<1>, C4<1>; +L_0x2a10190 .delay (20000,20000,20000) L_0x2a10190/d; +L_0x2a102e0/d .functor OR 1, L_0x2a10040, L_0x2a10190, C4<0>, C4<0>; +L_0x2a102e0 .delay (20000,20000,20000) L_0x2a102e0/d; +v0x28a2990_0 .net "S", 0 0, L_0x2a104b0; 1 drivers +v0x28a2a30_0 .alias "in0", 0 0, v0x28a38b0_0; +v0x28a2ad0_0 .alias "in1", 0 0, v0x28a3540_0; +v0x28a2b70_0 .net "nS", 0 0, L_0x2a0ff80; 1 drivers +v0x28a2bf0_0 .net "out0", 0 0, L_0x2a10040; 1 drivers +v0x28a2c90_0 .net "out1", 0 0, L_0x2a10190; 1 drivers +v0x28a2d70_0 .alias "outfinal", 0 0, v0x28a37e0_0; +S_0x25e6a40 .scope module, "superalu" "Bitslice32" 2 162, 3 360, S_0x22efd20; + .timescale -9 -12; +P_0x262f748 .param/l "size" 3 378, +C4<0100000>; +L_0x2a3b100/d .functor AND 1, L_0x2a254f0, L_0x2a25590, C4<1>, C4<1>; +L_0x2a3b100 .delay (20000,20000,20000) L_0x2a3b100/d; +L_0x2a25680/d .functor NOT 1, L_0x2a25770, C4<0>, C4<0>, C4<0>; +L_0x2a25680 .delay (10000,10000,10000) L_0x2a25680/d; +L_0x2a25810/d .functor AND 1, L_0x2a25680, L_0x2a25680, C4<1>, C4<1>; +L_0x2a25810 .delay (20000,20000,20000) L_0x2a25810/d; +v0x28a00d0_0 .alias "A", 31 0, v0x295f580_0; +v0x28a0320_0 .alias "AddSubSLTSum", 31 0, v0x295ff30_0; +v0x28a03a0_0 .alias "AllZeros", 0 0, v0x295ffb0_0; +v0x28a0420_0 .alias "AndNandOut", 31 0, v0x2960110_0; +v0x28a04a0_0 .alias "B", 31 0, v0x295f6a0_0; +RS_0x7f507e9b8f68/0/0 .resolv tri, L_0x2a12350, L_0x2a14d90, L_0x2a176b0, L_0x2a19f50; +RS_0x7f507e9b8f68/0/4 .resolv tri, L_0x2a1ca10, L_0x2a1f2b0, L_0x2a21b30, L_0x2a243b0; +RS_0x7f507e9b8f68/0/8 .resolv tri, L_0x2a26ed0, L_0x2a29720, L_0x2a2c300, L_0x2a2ea60; +RS_0x7f507e9b8f68/0/12 .resolv tri, L_0x2a312b0, L_0x2a33a40, L_0x2a362a0, L_0x2a39330; +RS_0x7f507e9b8f68/0/16 .resolv tri, L_0x2a3c3c0, L_0x2a3ebf0, L_0x2a41500, L_0x2a42f70; +RS_0x7f507e9b8f68/0/20 .resolv tri, L_0x2a45510, L_0x2a48a90, L_0x2a4a1e0, L_0x2a4c7c0; +RS_0x7f507e9b8f68/0/24 .resolv tri, L_0x2a4fe30, L_0x2a524e0, L_0x2a54bb0, L_0x2a57240; +RS_0x7f507e9b8f68/0/28 .resolv tri, L_0x2a598b0, L_0x2a5c330, L_0x2a5d130, L_0x2b14240; +RS_0x7f507e9b8f68/1/0 .resolv tri, RS_0x7f507e9b8f68/0/0, RS_0x7f507e9b8f68/0/4, RS_0x7f507e9b8f68/0/8, RS_0x7f507e9b8f68/0/12; +RS_0x7f507e9b8f68/1/4 .resolv tri, RS_0x7f507e9b8f68/0/16, RS_0x7f507e9b8f68/0/20, RS_0x7f507e9b8f68/0/24, RS_0x7f507e9b8f68/0/28; +RS_0x7f507e9b8f68 .resolv tri, RS_0x7f507e9b8f68/1/0, RS_0x7f507e9b8f68/1/4, C4, C4; +v0x28a0520_0 .net8 "Cmd0Start", 31 0, RS_0x7f507e9b8f68; 32 drivers +RS_0x7f507e9b8f98/0/0 .resolv tri, L_0x2a13230, L_0x2a15c80, L_0x2a18560, L_0x2a1ae10; +RS_0x7f507e9b8f98/0/4 .resolv tri, L_0x2a1d8c0, L_0x2a20170, L_0x2a229e0, L_0x2a251e0; +RS_0x7f507e9b8f98/0/8 .resolv tri, L_0x2a27d80, L_0x2a2a5c0, L_0x2a2d160, L_0x2a2f920; +RS_0x7f507e9b8f98/0/12 .resolv tri, L_0x2a32140, L_0x2a348d0, L_0x2a35ce0, L_0x2a3a1c0; +RS_0x7f507e9b8f98/0/16 .resolv tri, L_0x2a3d270, L_0x2a3faf0, L_0x2a42330, L_0x2a43c20; +RS_0x7f507e9b8f98/0/20 .resolv tri, L_0x2a46480, L_0x2a48570, L_0x2a4bec0, L_0x2a4e580; +RS_0x7f507e9b8f98/0/24 .resolv tri, L_0x2a4f310, L_0x2a51db0, L_0x2a542a0, L_0x2a56ce0; +RS_0x7f507e9b8f98/0/28 .resolv tri, L_0x2a59560, L_0x2a5bab0, L_0x2a5f760, L_0x2a62950; +RS_0x7f507e9b8f98/1/0 .resolv tri, RS_0x7f507e9b8f98/0/0, RS_0x7f507e9b8f98/0/4, RS_0x7f507e9b8f98/0/8, RS_0x7f507e9b8f98/0/12; +RS_0x7f507e9b8f98/1/4 .resolv tri, RS_0x7f507e9b8f98/0/16, RS_0x7f507e9b8f98/0/20, RS_0x7f507e9b8f98/0/24, RS_0x7f507e9b8f98/0/28; +RS_0x7f507e9b8f98 .resolv tri, RS_0x7f507e9b8f98/1/0, RS_0x7f507e9b8f98/1/4, C4, C4; +v0x28a05a0_0 .net8 "Cmd1Start", 31 0, RS_0x7f507e9b8f98; 32 drivers +v0x28a0620_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x28a06f0_0 .alias "OneBitFinalOut", 31 0, v0x2960290_0; +v0x28a0770_0 .alias "OrNorXorOut", 31 0, v0x29603c0_0; +v0x28a07f0_0 .alias "SLTSum", 31 0, v0x2960440_0; +v0x28a08a0_0 .alias "SLTflag", 0 0, v0x29604c0_0; +v0x28a0920_0 .alias "ZeroFlag", 31 0, v0x29606c0_0; +v0x28a09a0_0 .net *"_s121", 0 0, L_0x2a1e020; 1 drivers +v0x28a0aa0_0 .net *"_s146", 0 0, L_0x2a20660; 1 drivers +v0x28a0b20_0 .net *"_s171", 0 0, L_0x2a232a0; 1 drivers +v0x28a0a20_0 .net *"_s196", 0 0, L_0x2a1bd80; 1 drivers +v0x28a0c70_0 .net *"_s21", 0 0, L_0x2a142f0; 1 drivers +v0x28a0d90_0 .net *"_s221", 0 0, L_0x2a280a0; 1 drivers +v0x28a0e10_0 .net *"_s246", 0 0, L_0x2a2a970; 1 drivers +v0x28a0cf0_0 .net *"_s271", 0 0, L_0x2a2d480; 1 drivers +v0x28a0f40_0 .net *"_s296", 0 0, L_0x2a2fe10; 1 drivers +v0x28a0e90_0 .net *"_s321", 0 0, L_0x2a32410; 1 drivers +v0x28a1080_0 .net *"_s346", 0 0, L_0x2a34dc0; 1 drivers +v0x28a0fe0_0 .net *"_s371", 0 0, L_0x2a375d0; 1 drivers +v0x28a11d0_0 .net *"_s396", 0 0, L_0x2a39d70; 1 drivers +v0x28a1120_0 .net *"_s421", 0 0, L_0x2a3d590; 1 drivers +v0x28a1330_0 .net *"_s446", 0 0, L_0x2a3fcc0; 1 drivers +v0x28a1270_0 .net *"_s46", 0 0, L_0x2a162d0; 1 drivers +v0x28a14a0_0 .net *"_s471", 0 0, L_0x2a42470; 1 drivers +v0x28a13b0_0 .net *"_s496", 0 0, L_0x2a44be0; 1 drivers +v0x28a1620_0 .net *"_s521", 0 0, L_0x2a47170; 1 drivers +v0x28a1520_0 .net *"_s546", 0 0, L_0x2a49710; 1 drivers +v0x28a17b0_0 .net *"_s571", 0 0, L_0x2a4b6d0; 1 drivers +v0x28a16a0_0 .net *"_s596", 0 0, L_0x2a4db30; 1 drivers +v0x28a1950_0 .net *"_s621", 0 0, L_0x2a509b0; 1 drivers +v0x28a1830_0 .net *"_s646", 0 0, L_0x2a52fd0; 1 drivers +v0x28a18d0_0 .net *"_s671", 0 0, L_0x2a55550; 1 drivers +v0x28a1b10_0 .net *"_s696", 0 0, L_0x2a57b60; 1 drivers +v0x28a1b90_0 .net *"_s71", 0 0, L_0x2a19200; 1 drivers +v0x28a19d0_0 .net *"_s721", 0 0, L_0x2a5a530; 1 drivers +v0x28a1a70_0 .net *"_s746", 0 0, L_0x2a5c6f0; 1 drivers +v0x28a1d70_0 .net *"_s771", 0 0, L_0x2a5e180; 1 drivers +v0x28a1df0_0 .net *"_s811", 0 0, L_0x2a3b100; 1 drivers +v0x28a1c10_0 .net *"_s814", 0 0, L_0x2a254f0; 1 drivers +v0x28a1cb0_0 .net *"_s816", 0 0, L_0x2a25590; 1 drivers +v0x28a1ff0_0 .net *"_s818", 0 0, L_0x2a25770; 1 drivers +v0x28a2070_0 .net *"_s96", 0 0, L_0x2a16a00; 1 drivers +v0x28a1e90_0 .alias "carryin", 31 0, v0x295fa50_0; +v0x28a1f10_0 .alias "carryout", 0 0, v0x2960870_0; +v0x28a2290_0 .alias "overflow", 0 0, v0x2960980_0; +v0x28a2360_0 .alias "subtract", 31 0, v0x2960aa0_0; +v0x28a2140_0 .net "yeszero", 0 0, L_0x2a25680; 1 drivers +L_0x2a12350 .part/pv L_0x2a12140, 1, 1, 32; +L_0x2a123f0 .part v0x2960210_0, 0, 1; +L_0x2a12520 .part v0x2960210_0, 1, 1; +L_0x2a12650 .part RS_0x7f507e9ad5c8, 1, 1; +L_0x2a126f0 .part RS_0x7f507e9ad5c8, 1, 1; +L_0x2a12790 .part RS_0x7f507e9a3368, 1, 1; +L_0x2a128c0 .part RS_0x7f507e9b8c98, 1, 1; +L_0x2a13230 .part/pv L_0x2a12ff0, 1, 1, 32; +L_0x2a13320 .part v0x2960210_0, 0, 1; +L_0x2a13450 .part v0x2960210_0, 1, 1; +L_0x2a135e0 .part RS_0x7f507e9a6998, 1, 1; +L_0x2a13680 .part RS_0x7f507e9a6998, 1, 1; +L_0x2a13790 .part RS_0x7f507e9a3368, 1, 1; +L_0x2a13830 .part RS_0x7f507e9a3368, 1, 1; +L_0x2a13d10 .part/pv L_0x2a13bd0, 1, 1, 32; +L_0x2a13e00 .part v0x2960210_0, 2, 1; +L_0x2a13f30 .part RS_0x7f507e9b8f68, 1, 1; +L_0x2a14070 .part RS_0x7f507e9b8f98, 1, 1; +L_0x2a14250 .part/pv L_0x2a142f0, 1, 1, 32; +L_0x2a143f0 .part RS_0x7f507e9b8ff8, 0, 1; +L_0x2a141b0 .part RS_0x7f507e9b8fc8, 1, 1; +L_0x2a14d90 .part/pv L_0x2a14b80, 2, 1, 32; +L_0x2a14490 .part v0x2960210_0, 0, 1; +L_0x2a14f80 .part v0x2960210_0, 1, 1; +L_0x2a14e30 .part RS_0x7f507e9ad5c8, 2, 1; +L_0x2a15180 .part RS_0x7f507e9ad5c8, 2, 1; +L_0x2a150b0 .part RS_0x7f507e9a3368, 2, 1; +L_0x2a15350 .part RS_0x7f507e9b8c98, 2, 1; +L_0x2a15c80 .part/pv L_0x2a15a70, 2, 1, 32; +L_0x2a15d20 .part v0x2960210_0, 0, 1; +L_0x2a15440 .part v0x2960210_0, 1, 1; +L_0x2a15fe0 .part RS_0x7f507e9a6998, 2, 1; +L_0x2a15e50 .part RS_0x7f507e9a6998, 2, 1; +L_0x2a16190 .part RS_0x7f507e9a3368, 2, 1; +L_0x2a16080 .part RS_0x7f507e9a3368, 2, 1; +L_0x2a16700 .part/pv L_0x2a165c0, 2, 1, 32; +L_0x2a16230 .part v0x2960210_0, 2, 1; +L_0x2a16960 .part RS_0x7f507e9b8f68, 2, 1; +L_0x2a16830 .part RS_0x7f507e9b8f98, 2, 1; +L_0x2a16bd0 .part/pv L_0x2a162d0, 2, 1, 32; +L_0x2a16ad0 .part RS_0x7f507e9b8ff8, 1, 1; +L_0x2a16e50 .part RS_0x7f507e9b8fc8, 2, 1; +L_0x2a176b0 .part/pv L_0x2a174a0, 3, 1, 32; +L_0x2a17750 .part v0x2960210_0, 0, 1; +L_0x2a16ef0 .part v0x2960210_0, 1, 1; +L_0x2a179f0 .part RS_0x7f507e9ad5c8, 3, 1; +L_0x2a17880 .part RS_0x7f507e9ad5c8, 3, 1; +L_0x2a17920 .part RS_0x7f507e9a3368, 3, 1; +L_0x2a17a90 .part RS_0x7f507e9b8c98, 3, 1; +L_0x2a18560 .part/pv L_0x2a18350, 3, 1, 32; +L_0x2a17c60 .part v0x2960210_0, 0, 1; +L_0x2a187a0 .part v0x2960210_0, 1, 1; +L_0x2a18600 .part RS_0x7f507e9a6998, 3, 1; +L_0x2a186a0 .part RS_0x7f507e9a6998, 3, 1; +L_0x2a18a90 .part RS_0x7f507e9a3368, 3, 1; +L_0x2a18b30 .part RS_0x7f507e9a3368, 3, 1; +L_0x2a19020 .part/pv L_0x2a18ee0, 3, 1, 32; +L_0x2a190c0 .part v0x2960210_0, 2, 1; +L_0x2a18bd0 .part RS_0x7f507e9b8f68, 3, 1; +L_0x2a18cc0 .part RS_0x7f507e9b8f98, 3, 1; +L_0x2a19160 .part/pv L_0x2a19200, 3, 1, 32; +L_0x2a19580 .part RS_0x7f507e9b8ff8, 2, 1; +L_0x2a19390 .part RS_0x7f507e9b8fc8, 3, 1; +L_0x2a19f50 .part/pv L_0x2a19d40, 4, 1, 32; +L_0x2a19620 .part v0x2960210_0, 0, 1; +L_0x2a19750 .part v0x2960210_0, 1, 1; +L_0x2a19ff0 .part RS_0x7f507e9ad5c8, 4, 1; +L_0x2a1a090 .part RS_0x7f507e9ad5c8, 4, 1; +L_0x2a1a130 .part RS_0x7f507e9a3368, 4, 1; +L_0x2a1a510 .part RS_0x7f507e9b8c98, 4, 1; +L_0x2a1ae10 .part/pv L_0x2a1ac00, 4, 1, 32; +L_0x2a1aeb0 .part v0x2960210_0, 0, 1; +L_0x2a1a600 .part v0x2960210_0, 1, 1; +L_0x2a1a730 .part RS_0x7f507e9a6998, 4, 1; +L_0x2a1b240 .part RS_0x7f507e9a6998, 4, 1; +L_0x2a1b2e0 .part RS_0x7f507e9a3368, 4, 1; +L_0x2a1afe0 .part RS_0x7f507e9a3368, 4, 1; +L_0x2a1b8b0 .part/pv L_0x2a1b770, 4, 1, 32; +L_0x2a1b380 .part v0x2960210_0, 2, 1; +L_0x2a1b420 .part RS_0x7f507e9b8f68, 4, 1; +L_0x2a1b510 .part RS_0x7f507e9b8f98, 4, 1; +L_0x2a1bb70 .part/pv L_0x2a16a00, 4, 1, 32; +L_0x2a1bc10 .part RS_0x7f507e9b8ff8, 3, 1; +L_0x2a1bdf0 .part RS_0x7f507e9b8fc8, 4, 1; +L_0x2a1ca10 .part/pv L_0x2a1c800, 5, 1, 32; +L_0x2a1cab0 .part v0x2960210_0, 0, 1; +L_0x2a1c190 .part v0x2960210_0, 1, 1; +L_0x2a1c2c0 .part RS_0x7f507e9ad5c8, 5, 1; +L_0x2a1c360 .part RS_0x7f507e9ad5c8, 5, 1; +L_0x2a1ceb0 .part RS_0x7f507e9a3368, 5, 1; +L_0x2a1cbe0 .part RS_0x7f507e9b8c98, 5, 1; +L_0x2a1d8c0 .part/pv L_0x2a1d6b0, 5, 1, 32; +L_0x2a1cfa0 .part v0x2960210_0, 0, 1; +L_0x2a1d0d0 .part v0x2960210_0, 1, 1; +L_0x2a1dc60 .part RS_0x7f507e9a6998, 5, 1; +L_0x2a1dd00 .part RS_0x7f507e9a6998, 5, 1; +L_0x2a1d960 .part RS_0x7f507e9a3368, 5, 1; +L_0x2a1da50 .part RS_0x7f507e9a3368, 5, 1; +L_0x2a1e380 .part/pv L_0x2a1e240, 5, 1, 32; +L_0x2a1e420 .part v0x2960210_0, 2, 1; +L_0x2a1dda0 .part RS_0x7f507e9b8f68, 5, 1; +L_0x2a1de90 .part RS_0x7f507e9b8f98, 5, 1; +L_0x2a1df80 .part/pv L_0x2a1e020, 5, 1, 32; +L_0x2a1e8a0 .part RS_0x7f507e9b8ff8, 4, 1; +L_0x2a1e4c0 .part RS_0x7f507e9b8fc8, 5, 1; +L_0x2a1f2b0 .part/pv L_0x2a1f0a0, 6, 1, 32; +L_0x2a1e940 .part v0x2960210_0, 0, 1; +L_0x2a1ea70 .part v0x2960210_0, 1, 1; +L_0x2a1eba0 .part RS_0x7f507e9ad5c8, 6, 1; +L_0x2a1f6c0 .part RS_0x7f507e9ad5c8, 6, 1; +L_0x2a1f350 .part RS_0x7f507e9a3368, 6, 1; +L_0x2a1f3f0 .part RS_0x7f507e9b8c98, 6, 1; +L_0x2a20170 .part/pv L_0x2a1ff60, 6, 1, 32; +L_0x2a20210 .part v0x2960210_0, 0, 1; +L_0x2a1f760 .part v0x2960210_0, 1, 1; +L_0x2a1f890 .part RS_0x7f507e9a6998, 6, 1; +L_0x2a1f930 .part RS_0x7f507e9a6998, 6, 1; +L_0x2a1f9d0 .part RS_0x7f507e9a3368, 6, 1; +L_0x2a20700 .part RS_0x7f507e9a3368, 6, 1; +L_0x2a20c00 .part/pv L_0x2a20ac0, 6, 1, 32; +L_0x2a20340 .part v0x2960210_0, 2, 1; +L_0x2a203e0 .part RS_0x7f507e9b8f68, 6, 1; +L_0x2a204d0 .part RS_0x7f507e9b8f98, 6, 1; +L_0x2a205c0 .part/pv L_0x2a20660, 6, 1, 32; +L_0x2a21130 .part RS_0x7f507e9b8ff8, 5, 1; +L_0x2a211d0 .part RS_0x7f507e9b8fc8, 6, 1; +L_0x2a21b30 .part/pv L_0x2a21920, 7, 1, 32; +L_0x2a21bd0 .part v0x2960210_0, 0, 1; +L_0x2a212c0 .part v0x2960210_0, 1, 1; +L_0x2a213f0 .part RS_0x7f507e9ad5c8, 7, 1; +L_0x2a21490 .part RS_0x7f507e9ad5c8, 7, 1; +L_0x2a21530 .part RS_0x7f507e9a3368, 7, 1; +L_0x2a21620 .part RS_0x7f507e9b8c98, 7, 1; +L_0x2a229e0 .part/pv L_0x2a227d0, 7, 1, 32; +L_0x2a21d00 .part v0x2960210_0, 0, 1; +L_0x2a21e30 .part v0x2960210_0, 1, 1; +L_0x2a21f60 .part RS_0x7f507e9a6998, 7, 1; +L_0x2a22000 .part RS_0x7f507e9a6998, 7, 1; +L_0x2a22ee0 .part RS_0x7f507e9a3368, 7, 1; +L_0x2a22f80 .part RS_0x7f507e9a3368, 7, 1; +L_0x2a22df0 .part/pv L_0x2a22cb0, 7, 1, 32; +L_0x2a234e0 .part v0x2960210_0, 2, 1; +L_0x2a23070 .part RS_0x7f507e9b8f68, 7, 1; +L_0x2a23110 .part RS_0x7f507e9b8f98, 7, 1; +L_0x2a23200 .part/pv L_0x2a232a0, 7, 1, 32; +L_0x2a233e0 .part RS_0x7f507e9b8ff8, 6, 1; +L_0x2a23a20 .part RS_0x7f507e9b8fc8, 7, 1; +L_0x2a243b0 .part/pv L_0x2a241a0, 8, 1, 32; +L_0x2a23580 .part v0x2960210_0, 0, 1; +L_0x2a236b0 .part v0x2960210_0, 1, 1; +L_0x2a237e0 .part RS_0x7f507e9ad5c8, 8, 1; +L_0x2a23880 .part RS_0x7f507e9ad5c8, 8, 1; +L_0x2a23920 .part RS_0x7f507e9a3368, 8, 1; +L_0x2a24920 .part RS_0x7f507e9b8c98, 8, 1; +L_0x2a251e0 .part/pv L_0x2a24fd0, 8, 1, 32; +L_0x2a25280 .part v0x2960210_0, 0, 1; +L_0x2a24a10 .part v0x2960210_0, 1, 1; +L_0x2a24b40 .part RS_0x7f507e9a6998, 8, 1; +L_0x2a24be0 .part RS_0x7f507e9a6998, 8, 1; +L_0x2a24c80 .part RS_0x7f507e9a3368, 8, 1; +L_0x2a24d70 .part RS_0x7f507e9a3368, 8, 1; +L_0x2a25b80 .part/pv L_0x2a25a40, 8, 1, 32; +L_0x2a1b950 .part v0x2960210_0, 2, 1; +L_0x2a253b0 .part RS_0x7f507e9b8f68, 8, 1; +L_0x2a1bce0 .part RS_0x7f507e9b8f98, 8, 1; +L_0x2a1ba40 .part/pv L_0x2a1bd80, 8, 1, 32; +L_0x2a1c0d0 .part RS_0x7f507e9b8ff8, 7, 1; +L_0x2a25e30 .part RS_0x7f507e9b8fc8, 8, 1; +L_0x2a26ed0 .part/pv L_0x2a26cc0, 9, 1, 32; +L_0x2a26f70 .part v0x2960210_0, 0, 1; +L_0x2a26570 .part v0x2960210_0, 1, 1; +L_0x2a266a0 .part RS_0x7f507e9ad5c8, 9, 1; +L_0x2a26740 .part RS_0x7f507e9ad5c8, 9, 1; +L_0x2a267e0 .part RS_0x7f507e9a3368, 9, 1; +L_0x2a268d0 .part RS_0x7f507e9b8c98, 9, 1; +L_0x2a27d80 .part/pv L_0x2a27b70, 9, 1, 32; +L_0x2a270a0 .part v0x2960210_0, 0, 1; +L_0x2a271d0 .part v0x2960210_0, 1, 1; +L_0x2a27300 .part RS_0x7f507e9a6998, 9, 1; +L_0x2a273a0 .part RS_0x7f507e9a6998, 9, 1; +L_0x2a27440 .part RS_0x7f507e9a3368, 9, 1; +L_0x2a27530 .part RS_0x7f507e9a3368, 9, 1; +L_0x2a287f0 .part/pv L_0x2a286b0, 9, 1, 32; +L_0x2a28890 .part v0x2960210_0, 2, 1; +L_0x2a27e20 .part RS_0x7f507e9b8f68, 9, 1; +L_0x2a27f10 .part RS_0x7f507e9b8f98, 9, 1; +L_0x2a28000 .part/pv L_0x2a280a0, 9, 1, 32; +L_0x2a281e0 .part RS_0x7f507e9b8ff8, 8, 1; +L_0x2a28280 .part RS_0x7f507e9b8fc8, 9, 1; +L_0x2a29720 .part/pv L_0x2a29510, 10, 1, 32; +L_0x2a28930 .part v0x2960210_0, 0, 1; +L_0x2a28a60 .part v0x2960210_0, 1, 1; +L_0x2a28b90 .part RS_0x7f507e9ad5c8, 10, 1; +L_0x2a28c30 .part RS_0x7f507e9ad5c8, 10, 1; +L_0x2a28cd0 .part RS_0x7f507e9a3368, 10, 1; +L_0x2a28dc0 .part RS_0x7f507e9b8c98, 10, 1; +L_0x2a2a5c0 .part/pv L_0x2a2a3b0, 10, 1, 32; +L_0x2a2a660 .part v0x2960210_0, 0, 1; +L_0x2a297c0 .part v0x2960210_0, 1, 1; +L_0x2a298f0 .part RS_0x7f507e9a6998, 10, 1; +L_0x2a29990 .part RS_0x7f507e9a6998, 10, 1; +L_0x2a29a30 .part RS_0x7f507e9a3368, 10, 1; +L_0x2a29b20 .part RS_0x7f507e9a3368, 10, 1; +L_0x2a0e150 .part/pv L_0x2a0e010, 10, 1, 32; +L_0x2a0e1f0 .part v0x2960210_0, 2, 1; +L_0x2a0e290 .part RS_0x7f507e9b8f68, 10, 1; +L_0x2a2a7e0 .part RS_0x7f507e9b8f98, 10, 1; +L_0x2a2a8d0 .part/pv L_0x2a2a970, 10, 1, 32; +L_0x2a2aab0 .part RS_0x7f507e9b8ff8, 9, 1; +L_0x2a2ab50 .part RS_0x7f507e9b8fc8, 10, 1; +L_0x2a2c300 .part/pv L_0x2a2c0f0, 11, 1, 32; +L_0x2a2c3a0 .part v0x2960210_0, 0, 1; +L_0x2a2b5f0 .part v0x2960210_0, 1, 1; +L_0x2a2b720 .part RS_0x7f507e9ad5c8, 11, 1; +L_0x2a2b7c0 .part RS_0x7f507e9ad5c8, 11, 1; +L_0x2a2b860 .part RS_0x7f507e9a3368, 11, 1; +L_0x2a2b950 .part RS_0x7f507e9b8c98, 11, 1; +L_0x2a2d160 .part/pv L_0x2a2cf50, 11, 1, 32; +L_0x2a2c4d0 .part v0x2960210_0, 0, 1; +L_0x2a2c600 .part v0x2960210_0, 1, 1; +L_0x2a2c730 .part RS_0x7f507e9a6998, 11, 1; +L_0x2a2c7d0 .part RS_0x7f507e9a6998, 11, 1; +L_0x2a2c870 .part RS_0x7f507e9a3368, 11, 1; +L_0x2a2c960 .part RS_0x7f507e9a3368, 11, 1; +L_0x2a2dbd0 .part/pv L_0x2a2da90, 11, 1, 32; +L_0x2a2dc70 .part v0x2960210_0, 2, 1; +L_0x2a2d200 .part RS_0x7f507e9b8f68, 11, 1; +L_0x2a2d2f0 .part RS_0x7f507e9b8f98, 11, 1; +L_0x2a2d3e0 .part/pv L_0x2a2d480, 11, 1, 32; +L_0x2a2d5c0 .part RS_0x7f507e9b8ff8, 10, 1; +L_0x2a2d660 .part RS_0x7f507e9b8fc8, 11, 1; +L_0x2a2ea60 .part/pv L_0x2a2e850, 12, 1, 32; +L_0x2a2dd10 .part v0x2960210_0, 0, 1; +L_0x2a2de40 .part v0x2960210_0, 1, 1; +L_0x2a2df70 .part RS_0x7f507e9ad5c8, 12, 1; +L_0x2a2e010 .part RS_0x7f507e9ad5c8, 12, 1; +L_0x2a2e0b0 .part RS_0x7f507e9a3368, 12, 1; +L_0x2a2e1a0 .part RS_0x7f507e9b8c98, 12, 1; +L_0x2a2f920 .part/pv L_0x2a2f710, 12, 1, 32; +L_0x2a2f9c0 .part v0x2960210_0, 0, 1; +L_0x2a2eb00 .part v0x2960210_0, 1, 1; +L_0x2a2ec30 .part RS_0x7f507e9a6998, 12, 1; +L_0x2a2ecd0 .part RS_0x7f507e9a6998, 12, 1; +L_0x2a2ed70 .part RS_0x7f507e9a3368, 12, 1; +L_0x2a2ee60 .part RS_0x7f507e9a3368, 12, 1; +L_0x2a30380 .part/pv L_0x2a2f220, 12, 1, 32; +L_0x2a2faf0 .part v0x2960210_0, 2, 1; +L_0x2a2fb90 .part RS_0x7f507e9b8f68, 12, 1; +L_0x2a2fc80 .part RS_0x7f507e9b8f98, 12, 1; +L_0x2a2fd70 .part/pv L_0x2a2fe10, 12, 1, 32; +L_0x2a2ff50 .part RS_0x7f507e9b8ff8, 11, 1; +L_0x2a2fff0 .part RS_0x7f507e9b8fc8, 12, 1; +L_0x2a312b0 .part/pv L_0x2a310a0, 13, 1, 32; +L_0x2a31350 .part v0x2960210_0, 0, 1; +L_0x2a30420 .part v0x2960210_0, 1, 1; +L_0x2a30550 .part RS_0x7f507e9ad5c8, 13, 1; +L_0x2a305f0 .part RS_0x7f507e9ad5c8, 13, 1; +L_0x2a30690 .part RS_0x7f507e9a3368, 13, 1; +L_0x2a30780 .part RS_0x7f507e9b8c98, 13, 1; +L_0x2a32140 .part/pv L_0x2a31f30, 13, 1, 32; +L_0x2a31480 .part v0x2960210_0, 0, 1; +L_0x2a315b0 .part v0x2960210_0, 1, 1; +L_0x2a316e0 .part RS_0x7f507e9a6998, 13, 1; +L_0x2a31780 .part RS_0x7f507e9a6998, 13, 1; +L_0x2a31820 .part RS_0x7f507e9a3368, 13, 1; +L_0x2a31910 .part RS_0x7f507e9a3368, 13, 1; +L_0x2a32b70 .part/pv L_0x2a31c40, 13, 1, 32; +L_0x2a32c10 .part v0x2960210_0, 2, 1; +L_0x2a321e0 .part RS_0x7f507e9b8f68, 13, 1; +L_0x2a32280 .part RS_0x7f507e9b8f98, 13, 1; +L_0x2a32370 .part/pv L_0x2a32410, 13, 1, 32; +L_0x2a32550 .part RS_0x7f507e9b8ff8, 12, 1; +L_0x2a325f0 .part RS_0x7f507e9b8fc8, 13, 1; +L_0x2a33a40 .part/pv L_0x2a33830, 14, 1, 32; +L_0x2a32cb0 .part v0x2960210_0, 0, 1; +L_0x2a32de0 .part v0x2960210_0, 1, 1; +L_0x2a32f10 .part RS_0x7f507e9ad5c8, 14, 1; +L_0x2a32fb0 .part RS_0x7f507e9ad5c8, 14, 1; +L_0x2a33050 .part RS_0x7f507e9a3368, 14, 1; +L_0x2a33140 .part RS_0x7f507e9b8c98, 14, 1; +L_0x2a348d0 .part/pv L_0x2a346c0, 14, 1, 32; +L_0x2a34970 .part v0x2960210_0, 0, 1; +L_0x2a33ae0 .part v0x2960210_0, 1, 1; +L_0x2a33c10 .part RS_0x7f507e9a6998, 14, 1; +L_0x2a33cb0 .part RS_0x7f507e9a6998, 14, 1; +L_0x2a33d50 .part RS_0x7f507e9a3368, 14, 1; +L_0x2a33e40 .part RS_0x7f507e9a3368, 14, 1; +L_0x2a353a0 .part/pv L_0x2a34200, 14, 1, 32; +L_0x2a34aa0 .part v0x2960210_0, 2, 1; +L_0x2a34b40 .part RS_0x7f507e9b8f68, 14, 1; +L_0x2a34c30 .part RS_0x7f507e9b8f98, 14, 1; +L_0x2a34d20 .part/pv L_0x2a34dc0, 14, 1, 32; +L_0x2a34f00 .part RS_0x7f507e9b8ff8, 13, 1; +L_0x2a34fa0 .part RS_0x7f507e9b8fc8, 14, 1; +L_0x2a362a0 .part/pv L_0x2a36090, 15, 1, 32; +L_0x2a36340 .part v0x2960210_0, 0, 1; +L_0x2a35440 .part v0x2960210_0, 1, 1; +L_0x2a35570 .part RS_0x7f507e9ad5c8, 15, 1; +L_0x2986f60 .part RS_0x7f507e9ad5c8, 15, 1; +L_0x2987000 .part RS_0x7f507e9a3368, 15, 1; +L_0x29870f0 .part RS_0x7f507e9b8c98, 15, 1; +L_0x2a35ce0 .part/pv L_0x2a35ad0, 15, 1, 32; +L_0x2a36470 .part v0x2960210_0, 0, 1; +L_0x2a365a0 .part v0x2960210_0, 1, 1; +L_0x2a366d0 .part RS_0x7f507e9a6998, 15, 1; +L_0x29e8f40 .part RS_0x7f507e9a6998, 15, 1; +L_0x29e8fe0 .part RS_0x7f507e9a3368, 15, 1; +L_0x29e90d0 .part RS_0x7f507e9a3368, 15, 1; +L_0x2a369f0 .part/pv L_0x2a368b0, 15, 1, 32; +L_0x2a36a90 .part v0x2960210_0, 2, 1; +L_0x2a36b30 .part RS_0x7f507e9b8f68, 15, 1; +L_0x2a36c20 .part RS_0x7f507e9b8f98, 15, 1; +L_0x2a36d10 .part/pv L_0x2a375d0, 15, 1, 32; +L_0x2a37710 .part RS_0x7f507e9b8ff8, 14, 1; +L_0x2a377b0 .part RS_0x7f507e9b8fc8, 15, 1; +L_0x2a39330 .part/pv L_0x2a39150, 16, 1, 32; +L_0x2a38770 .part v0x2960210_0, 0, 1; +L_0x2a388a0 .part v0x2960210_0, 1, 1; +L_0x2a389d0 .part RS_0x7f507e9ad5c8, 16, 1; +L_0x2a38a70 .part RS_0x7f507e9ad5c8, 16, 1; +L_0x2a38b10 .part RS_0x7f507e9a3368, 16, 1; +L_0x2a38c00 .part RS_0x7f507e9b8c98, 16, 1; +L_0x2a3a1c0 .part/pv L_0x2a39fb0, 16, 1, 32; +L_0x2a3a260 .part v0x2960210_0, 0, 1; +L_0x2a393d0 .part v0x2960210_0, 1, 1; +L_0x2a39500 .part RS_0x7f507e9a6998, 16, 1; +L_0x2a395a0 .part RS_0x7f507e9a6998, 16, 1; +L_0x2a39640 .part RS_0x7f507e9a3368, 16, 1; +L_0x2a39730 .part RS_0x7f507e9a3368, 16, 1; +L_0x2a39c30 .part/pv L_0x2a39af0, 16, 1, 32; +L_0x2a39cd0 .part v0x2960210_0, 2, 1; +L_0x2a25c20 .part RS_0x7f507e9b8f68, 16, 1; +L_0x2a25d10 .part RS_0x7f507e9b8f98, 16, 1; +L_0x2a3abb0 .part/pv L_0x2a39d70, 16, 1, 32; +L_0x2a3ad30 .part RS_0x7f507e9b8ff8, 15, 1; +L_0x2a26360 .part RS_0x7f507e9b8fc8, 16, 1; +L_0x2a3c3c0 .part/pv L_0x2a3c1b0, 17, 1, 32; +L_0x2a3c460 .part v0x2960210_0, 0, 1; +L_0x2a3b1f0 .part v0x2960210_0, 1, 1; +L_0x2a3b320 .part RS_0x7f507e9ad5c8, 17, 1; +L_0x2a3b3c0 .part RS_0x7f507e9ad5c8, 17, 1; +L_0x2a3b460 .part RS_0x7f507e9a3368, 17, 1; +L_0x2a3b550 .part RS_0x7f507e9b8c98, 17, 1; +L_0x2a3d270 .part/pv L_0x2a3d090, 17, 1, 32; +L_0x2a3c590 .part v0x2960210_0, 0, 1; +L_0x2a3c6c0 .part v0x2960210_0, 1, 1; +L_0x2a3c7f0 .part RS_0x7f507e9a6998, 17, 1; +L_0x2a3c890 .part RS_0x7f507e9a6998, 17, 1; +L_0x2a3c930 .part RS_0x7f507e9a3368, 17, 1; +L_0x2a3ca20 .part RS_0x7f507e9a3368, 17, 1; +L_0x2a3cf20 .part/pv L_0x2a3cde0, 17, 1, 32; +L_0x2a3de10 .part v0x2960210_0, 2, 1; +L_0x2a3d310 .part RS_0x7f507e9b8f68, 17, 1; +L_0x2a3d400 .part RS_0x7f507e9b8f98, 17, 1; +L_0x2a3d4f0 .part/pv L_0x2a3d590, 17, 1, 32; +L_0x2a3d6d0 .part RS_0x7f507e9b8ff8, 16, 1; +L_0x2a3d770 .part RS_0x7f507e9b8fc8, 17, 1; +L_0x2a3ebf0 .part/pv L_0x2a3ea20, 18, 1, 32; +L_0x2a3deb0 .part v0x2960210_0, 0, 1; +L_0x2a3dfe0 .part v0x2960210_0, 1, 1; +L_0x2a3e110 .part RS_0x7f507e9ad5c8, 18, 1; +L_0x2a3e1b0 .part RS_0x7f507e9ad5c8, 18, 1; +L_0x2a3e250 .part RS_0x7f507e9a3368, 18, 1; +L_0x2a3e340 .part RS_0x7f507e9b8c98, 18, 1; +L_0x2a3faf0 .part/pv L_0x2a3f8e0, 18, 1, 32; +L_0x2a3fb90 .part v0x2960210_0, 0, 1; +L_0x2a3ec90 .part v0x2960210_0, 1, 1; +L_0x2a3edc0 .part RS_0x7f507e9a6998, 18, 1; +L_0x2a3ee60 .part RS_0x7f507e9a6998, 18, 1; +L_0x2a3ef00 .part RS_0x7f507e9a3368, 18, 1; +L_0x2a3eff0 .part RS_0x7f507e9a3368, 18, 1; +L_0x2a3f4f0 .part/pv L_0x2a3f3b0, 18, 1, 32; +L_0x2a3f590 .part v0x2960210_0, 2, 1; +L_0x2a3f630 .part RS_0x7f507e9b8f68, 18, 1; +L_0x2a3f720 .part RS_0x7f507e9b8f98, 18, 1; +L_0x2a40880 .part/pv L_0x2a3fcc0, 18, 1, 32; +L_0x2a3fe00 .part RS_0x7f507e9b8ff8, 17, 1; +L_0x2a3fea0 .part RS_0x7f507e9b8fc8, 18, 1; +L_0x2a41500 .part/pv L_0x2a40610, 19, 1, 32; +L_0x2a415a0 .part v0x2960210_0, 0, 1; +L_0x2a40920 .part v0x2960210_0, 1, 1; +L_0x2a40a50 .part RS_0x7f507e9ad5c8, 19, 1; +L_0x2a40af0 .part RS_0x7f507e9ad5c8, 19, 1; +L_0x2a40b90 .part RS_0x7f507e9a3368, 19, 1; +L_0x2a40c80 .part RS_0x7f507e9b8c98, 19, 1; +L_0x2a42330 .part/pv L_0x2a41330, 19, 1, 32; +L_0x2a416d0 .part v0x2960210_0, 0, 1; +L_0x2a41800 .part v0x2960210_0, 1, 1; +L_0x2a41930 .part RS_0x7f507e9a6998, 19, 1; +L_0x2a419d0 .part RS_0x7f507e9a6998, 19, 1; +L_0x2a41a70 .part RS_0x7f507e9a3368, 19, 1; +L_0x2a41b60 .part RS_0x7f507e9a3368, 19, 1; +L_0x2a42060 .part/pv L_0x2a41f20, 19, 1, 32; +L_0x2a42100 .part v0x2960210_0, 2, 1; +L_0x2a421a0 .part RS_0x7f507e9b8f68, 19, 1; +L_0x2a43030 .part RS_0x7f507e9b8f98, 19, 1; +L_0x2a423d0 .part/pv L_0x2a42470, 19, 1, 32; +L_0x2a425b0 .part RS_0x7f507e9b8ff8, 18, 1; +L_0x2a42650 .part RS_0x7f507e9b8fc8, 19, 1; +L_0x2a42f70 .part/pv L_0x2a42d60, 20, 1, 32; +L_0x2a43d60 .part v0x2960210_0, 0, 1; +L_0x2a43e90 .part v0x2960210_0, 1, 1; +L_0x2a430d0 .part RS_0x7f507e9ad5c8, 20, 1; +L_0x2a43170 .part RS_0x7f507e9ad5c8, 20, 1; +L_0x2a43210 .part RS_0x7f507e9a3368, 20, 1; +L_0x2a43300 .part RS_0x7f507e9b8c98, 20, 1; +L_0x2a43c20 .part/pv L_0x2a43a10, 20, 1, 32; +L_0x2a43cc0 .part v0x2960210_0, 0, 1; +L_0x2a43fc0 .part v0x2960210_0, 1, 1; +L_0x2a440f0 .part RS_0x7f507e9a6998, 20, 1; +L_0x2a44190 .part RS_0x7f507e9a6998, 20, 1; +L_0x2a44230 .part RS_0x7f507e9a3368, 20, 1; +L_0x2a44320 .part RS_0x7f507e9a3368, 20, 1; +L_0x2a44820 .part/pv L_0x2a446e0, 20, 1, 32; +L_0x2a448c0 .part v0x2960210_0, 2, 1; +L_0x2a44960 .part RS_0x7f507e9b8f68, 20, 1; +L_0x2a44a50 .part RS_0x7f507e9b8f98, 20, 1; +L_0x2a44b40 .part/pv L_0x2a44be0, 20, 1, 32; +L_0x2a45ad0 .part RS_0x7f507e9b8ff8, 19, 1; +L_0x2a45b70 .part RS_0x7f507e9b8fc8, 20, 1; +L_0x2a45510 .part/pv L_0x2a45300, 21, 1, 32; +L_0x2a455b0 .part v0x2960210_0, 0, 1; +L_0x2a456e0 .part v0x2960210_0, 1, 1; +L_0x2a45810 .part RS_0x7f507e9ad5c8, 21, 1; +L_0x2a458b0 .part RS_0x7f507e9ad5c8, 21, 1; +L_0x2a45950 .part RS_0x7f507e9a3368, 21, 1; +L_0x2a45c60 .part RS_0x7f507e9b8c98, 21, 1; +L_0x2a46480 .part/pv L_0x2a462a0, 21, 1, 32; +L_0x2a46520 .part v0x2960210_0, 0, 1; +L_0x2a46650 .part v0x2960210_0, 1, 1; +L_0x2a46780 .part RS_0x7f507e9a6998, 21, 1; +L_0x2a46820 .part RS_0x7f507e9a6998, 21, 1; +L_0x2a468c0 .part RS_0x7f507e9a3368, 21, 1; +L_0x2a47790 .part RS_0x7f507e9a3368, 21, 1; +L_0x2a46db0 .part/pv L_0x2a46c70, 21, 1, 32; +L_0x2a46e50 .part v0x2960210_0, 2, 1; +L_0x2a46ef0 .part RS_0x7f507e9b8f68, 21, 1; +L_0x2a46fe0 .part RS_0x7f507e9b8f98, 21, 1; +L_0x2a470d0 .part/pv L_0x2a47170, 21, 1, 32; +L_0x2a472b0 .part RS_0x7f507e9b8ff8, 20, 1; +L_0x2a47350 .part RS_0x7f507e9b8fc8, 21, 1; +L_0x2a48a90 .part/pv L_0x2a488b0, 22, 1, 32; +L_0x2a47880 .part v0x2960210_0, 0, 1; +L_0x2a479b0 .part v0x2960210_0, 1, 1; +L_0x2a47ae0 .part RS_0x7f507e9ad5c8, 22, 1; +L_0x2a47b80 .part RS_0x7f507e9ad5c8, 22, 1; +L_0x2a47c20 .part RS_0x7f507e9a3368, 22, 1; +L_0x2a47d10 .part RS_0x7f507e9b8c98, 22, 1; +L_0x2a48570 .part/pv L_0x2a48390, 22, 1, 32; +L_0x2a49940 .part v0x2960210_0, 0, 1; +L_0x2a48b30 .part v0x2960210_0, 1, 1; +L_0x2a48c60 .part RS_0x7f507e9a6998, 22, 1; +L_0x2a48d00 .part RS_0x7f507e9a6998, 22, 1; +L_0x2a48da0 .part RS_0x7f507e9a3368, 22, 1; +L_0x2a48e90 .part RS_0x7f507e9a3368, 22, 1; +L_0x2a49350 .part/pv L_0x2a49210, 22, 1, 32; +L_0x2a493f0 .part v0x2960210_0, 2, 1; +L_0x2a49490 .part RS_0x7f507e9b8f68, 22, 1; +L_0x2a49580 .part RS_0x7f507e9b8f98, 22, 1; +L_0x2a49670 .part/pv L_0x2a49710, 22, 1, 32; +L_0x2a49850 .part RS_0x7f507e9b8ff8, 21, 1; +L_0x2a4a8e0 .part RS_0x7f507e9b8fc8, 22, 1; +L_0x2a4a1e0 .part/pv L_0x2a4a000, 23, 1, 32; +L_0x2a4a280 .part v0x2960210_0, 0, 1; +L_0x2a4a3b0 .part v0x2960210_0, 1, 1; +L_0x2a4a4e0 .part RS_0x7f507e9ad5c8, 23, 1; +L_0x2a4a580 .part RS_0x7f507e9ad5c8, 23, 1; +L_0x2a4a620 .part RS_0x7f507e9a3368, 23, 1; +L_0x2a4a710 .part RS_0x7f507e9b8c98, 23, 1; +L_0x2a4bec0 .part/pv L_0x2a4bce0, 23, 1, 32; +L_0x2a4a980 .part v0x2960210_0, 0, 1; +L_0x2a4aab0 .part v0x2960210_0, 1, 1; +L_0x2a4abe0 .part RS_0x7f507e9a6998, 23, 1; +L_0x2a4ac80 .part RS_0x7f507e9a6998, 23, 1; +L_0x2a4ad20 .part RS_0x7f507e9a3368, 23, 1; +L_0x2a4ae10 .part RS_0x7f507e9a3368, 23, 1; +L_0x2a4b310 .part/pv L_0x2a4b1d0, 23, 1, 32; +L_0x2a4b3b0 .part v0x2960210_0, 2, 1; +L_0x2a4b450 .part RS_0x7f507e9b8f68, 23, 1; +L_0x2a4b540 .part RS_0x7f507e9b8f98, 23, 1; +L_0x2a4b630 .part/pv L_0x2a4b6d0, 23, 1, 32; +L_0x2a4ce70 .part RS_0x7f507e9b8ff8, 22, 1; +L_0x2a4bf60 .part RS_0x7f507e9b8fc8, 23, 1; +L_0x2a4c7c0 .part/pv L_0x2a4c5e0, 24, 1, 32; +L_0x2a4c860 .part v0x2960210_0, 0, 1; +L_0x2a4c990 .part v0x2960210_0, 1, 1; +L_0x2a4cac0 .part RS_0x7f507e9ad5c8, 24, 1; +L_0x2a4cb60 .part RS_0x7f507e9ad5c8, 24, 1; +L_0x2a4cc00 .part RS_0x7f507e9a3368, 24, 1; +L_0x2a4ccf0 .part RS_0x7f507e9b8c98, 24, 1; +L_0x2a4e580 .part/pv L_0x2a4e3a0, 24, 1, 32; +L_0x2a4e620 .part v0x2960210_0, 0, 1; +L_0x2a4cf10 .part v0x2960210_0, 1, 1; +L_0x2a4d040 .part RS_0x7f507e9a6998, 24, 1; +L_0x2a4d0e0 .part RS_0x7f507e9a6998, 24, 1; +L_0x2a4d180 .part RS_0x7f507e9a3368, 24, 1; +L_0x2a4d270 .part RS_0x7f507e9a3368, 24, 1; +L_0x2a4d770 .part/pv L_0x2a4d630, 24, 1, 32; +L_0x2a4d810 .part v0x2960210_0, 2, 1; +L_0x2a4d8b0 .part RS_0x7f507e9b8f68, 24, 1; +L_0x2a4d9a0 .part RS_0x7f507e9b8f98, 24, 1; +L_0x2a4da90 .part/pv L_0x2a4db30, 24, 1, 32; +L_0x2a4dc70 .part RS_0x7f507e9b8ff8, 23, 1; +L_0x2a4dd10 .part RS_0x7f507e9b8fc8, 24, 1; +L_0x2a4fe30 .part/pv L_0x2a4fc50, 25, 1, 32; +L_0x2a4fed0 .part v0x2960210_0, 0, 1; +L_0x2a4e750 .part v0x2960210_0, 1, 1; +L_0x2a4e880 .part RS_0x7f507e9ad5c8, 25, 1; +L_0x2a4e920 .part RS_0x7f507e9ad5c8, 25, 1; +L_0x2a4e9c0 .part RS_0x7f507e9a3368, 25, 1; +L_0x2a4eab0 .part RS_0x7f507e9b8c98, 25, 1; +L_0x2a4f310 .part/pv L_0x2a4f130, 25, 1, 32; +L_0x2a4f3b0 .part v0x2960210_0, 0, 1; +L_0x2a4f4e0 .part v0x2960210_0, 1, 1; +L_0x2a4f610 .part RS_0x7f507e9a6998, 25, 1; +L_0x2a51020 .part RS_0x7f507e9a6998, 25, 1; +L_0x2a50000 .part RS_0x7f507e9a3368, 25, 1; +L_0x2a500f0 .part RS_0x7f507e9a3368, 25, 1; +L_0x2a505f0 .part/pv L_0x2a504b0, 25, 1, 32; +L_0x2a50690 .part v0x2960210_0, 2, 1; +L_0x2a50730 .part RS_0x7f507e9b8f68, 25, 1; +L_0x2a50820 .part RS_0x7f507e9b8f98, 25, 1; +L_0x2a50910 .part/pv L_0x2a509b0, 25, 1, 32; +L_0x2a50af0 .part RS_0x7f507e9b8ff8, 24, 1; +L_0x2a50b90 .part RS_0x7f507e9b8fc8, 25, 1; +L_0x2a524e0 .part/pv L_0x2a52300, 26, 1, 32; +L_0x2a510c0 .part v0x2960210_0, 0, 1; +L_0x2a511f0 .part v0x2960210_0, 1, 1; +L_0x2a51320 .part RS_0x7f507e9ad5c8, 26, 1; +L_0x2a513c0 .part RS_0x7f507e9ad5c8, 26, 1; +L_0x2a51460 .part RS_0x7f507e9a3368, 26, 1; +L_0x2a51550 .part RS_0x7f507e9b8c98, 26, 1; +L_0x2a51db0 .part/pv L_0x2a51bd0, 26, 1, 32; +L_0x2a51e50 .part v0x2960210_0, 0, 1; +L_0x2a51f80 .part v0x2960210_0, 1, 1; +L_0x2a53640 .part RS_0x7f507e9a6998, 26, 1; +L_0x2a52580 .part RS_0x7f507e9a6998, 26, 1; +L_0x2a52620 .part RS_0x7f507e9a3368, 26, 1; +L_0x2a52710 .part RS_0x7f507e9a3368, 26, 1; +L_0x2a52c10 .part/pv L_0x2a52ad0, 26, 1, 32; +L_0x2a52cb0 .part v0x2960210_0, 2, 1; +L_0x2a52d50 .part RS_0x7f507e9b8f68, 26, 1; +L_0x2a52e40 .part RS_0x7f507e9b8f98, 26, 1; +L_0x2a52f30 .part/pv L_0x2a52fd0, 26, 1, 32; +L_0x2a53110 .part RS_0x7f507e9b8ff8, 25, 1; +L_0x2a531b0 .part RS_0x7f507e9b8fc8, 26, 1; +L_0x2a54bb0 .part/pv L_0x2a549d0, 27, 1, 32; +L_0x2a54c50 .part v0x2960210_0, 0, 1; +L_0x2a536e0 .part v0x2960210_0, 1, 1; +L_0x2a53810 .part RS_0x7f507e9ad5c8, 27, 1; +L_0x2a538b0 .part RS_0x7f507e9ad5c8, 27, 1; +L_0x2a53950 .part RS_0x7f507e9a3368, 27, 1; +L_0x2a53a40 .part RS_0x7f507e9b8c98, 27, 1; +L_0x2a542a0 .part/pv L_0x2a540c0, 27, 1, 32; +L_0x2a54340 .part v0x2960210_0, 0, 1; +L_0x2a54470 .part v0x2960210_0, 1, 1; +L_0x2a545a0 .part RS_0x7f507e9a6998, 27, 1; +L_0x2a54640 .part RS_0x7f507e9a6998, 27, 1; +L_0x2a546e0 .part RS_0x7f507e9a3368, 27, 1; +L_0x2a55f00 .part RS_0x7f507e9a3368, 27, 1; +L_0x2a55190 .part/pv L_0x2a55050, 27, 1, 32; +L_0x2a55230 .part v0x2960210_0, 2, 1; +L_0x2a552d0 .part RS_0x7f507e9b8f68, 27, 1; +L_0x2a553c0 .part RS_0x7f507e9b8f98, 27, 1; +L_0x2a554b0 .part/pv L_0x2a55550, 27, 1, 32; +L_0x2a55690 .part RS_0x7f507e9b8ff8, 26, 1; +L_0x2a55730 .part RS_0x7f507e9b8fc8, 27, 1; +L_0x2a57240 .part/pv L_0x2a55db0, 28, 1, 32; +L_0x2a55ff0 .part v0x2960210_0, 0, 1; +L_0x2a56120 .part v0x2960210_0, 1, 1; +L_0x2a56250 .part RS_0x7f507e9ad5c8, 28, 1; +L_0x2a562f0 .part RS_0x7f507e9ad5c8, 28, 1; +L_0x2a56390 .part RS_0x7f507e9a3368, 28, 1; +L_0x2a56480 .part RS_0x7f507e9b8c98, 28, 1; +L_0x2a56ce0 .part/pv L_0x2a56b00, 28, 1, 32; +L_0x2a56d80 .part v0x2960210_0, 0, 1; +L_0x2a56eb0 .part v0x2960210_0, 1, 1; +L_0x2a56fe0 .part RS_0x7f507e9a6998, 28, 1; +L_0x2a57080 .part RS_0x7f507e9a6998, 28, 1; +L_0x2a58500 .part RS_0x7f507e9a3368, 28, 1; +L_0x2a572e0 .part RS_0x7f507e9a3368, 28, 1; +L_0x2a577a0 .part/pv L_0x2a57660, 28, 1, 32; +L_0x2a57840 .part v0x2960210_0, 2, 1; +L_0x2a578e0 .part RS_0x7f507e9b8f68, 28, 1; +L_0x2a579d0 .part RS_0x7f507e9b8f98, 28, 1; +L_0x2a57ac0 .part/pv L_0x2a57b60, 28, 1, 32; +L_0x2a57ca0 .part RS_0x7f507e9b8ff8, 27, 1; +L_0x2a57d40 .part RS_0x7f507e9b8fc8, 28, 1; +L_0x2a598b0 .part/pv L_0x2a583c0, 29, 1, 32; +L_0x2a59950 .part v0x2960210_0, 0, 1; +L_0x2a585a0 .part v0x2960210_0, 1, 1; +L_0x2a586d0 .part RS_0x7f507e9ad5c8, 29, 1; +L_0x2a58770 .part RS_0x7f507e9ad5c8, 29, 1; +L_0x2a58810 .part RS_0x7f507e9a3368, 29, 1; +L_0x2a58900 .part RS_0x7f507e9b8c98, 29, 1; +L_0x2a59560 .part/pv L_0x2a59380, 29, 1, 32; +L_0x2a59600 .part v0x2960210_0, 0, 1; +L_0x2a59730 .part v0x2960210_0, 1, 1; +L_0x2a59a80 .part RS_0x7f507e9a6998, 29, 1; +L_0x2a59b20 .part RS_0x7f507e9a6998, 29, 1; +L_0x2a59bc0 .part RS_0x7f507e9a3368, 29, 1; +L_0x2a59cb0 .part RS_0x7f507e9a3368, 29, 1; +L_0x2a5a170 .part/pv L_0x2a5a030, 29, 1, 32; +L_0x2a5a210 .part v0x2960210_0, 2, 1; +L_0x2a5a2b0 .part RS_0x7f507e9b8f68, 29, 1; +L_0x2a5a3a0 .part RS_0x7f507e9b8f98, 29, 1; +L_0x2a5a490 .part/pv L_0x2a5a530, 29, 1, 32; +L_0x2a5a670 .part RS_0x7f507e9b8ff8, 28, 1; +L_0x2a5a710 .part RS_0x7f507e9b8fc8, 29, 1; +L_0x2a5c330 .part/pv L_0x2a5c150, 30, 1, 32; +L_0x2a5adc0 .part v0x2960210_0, 0, 1; +L_0x2a5aef0 .part v0x2960210_0, 1, 1; +L_0x2a5b020 .part RS_0x7f507e9ad5c8, 30, 1; +L_0x2a5b0c0 .part RS_0x7f507e9ad5c8, 30, 1; +L_0x2a5b160 .part RS_0x7f507e9a3368, 30, 1; +L_0x2a5b250 .part RS_0x7f507e9b8c98, 30, 1; +L_0x2a5bab0 .part/pv L_0x2a5b8d0, 30, 1, 32; +L_0x2a5bb50 .part v0x2960210_0, 0, 1; +L_0x2a5bc80 .part v0x2960210_0, 1, 1; +L_0x2a5bdb0 .part RS_0x7f507e9a6998, 30, 1; +L_0x2a5be50 .part RS_0x7f507e9a6998, 30, 1; +L_0x2a5bef0 .part RS_0x7f507e9a3368, 30, 1; +L_0x2a5bfe0 .part RS_0x7f507e9a3368, 30, 1; +L_0x2a5db60 .part/pv L_0x2a5da20, 30, 1, 32; +L_0x2a5c3d0 .part v0x2960210_0, 2, 1; +L_0x2a5c470 .part RS_0x7f507e9b8f68, 30, 1; +L_0x2a5c560 .part RS_0x7f507e9b8f98, 30, 1; +L_0x2a5c650 .part/pv L_0x2a5c6f0, 30, 1, 32; +L_0x2a5c830 .part RS_0x7f507e9b8ff8, 29, 1; +L_0x2a5c8d0 .part RS_0x7f507e9b8fc8, 30, 1; +L_0x2a5d130 .part/pv L_0x2a5cf50, 31, 1, 32; +L_0x2a5d1d0 .part v0x2960210_0, 0, 1; +L_0x2a5d300 .part v0x2960210_0, 1, 1; +L_0x2a5d430 .part RS_0x7f507e9ad5c8, 31, 1; +L_0x2a5d4d0 .part RS_0x7f507e9ad5c8, 31, 1; +L_0x2a5d570 .part RS_0x7f507e9a3368, 31, 1; +L_0x2a5d660 .part RS_0x7f507e9b8c98, 31, 1; +L_0x2a5f760 .part/pv L_0x2a5f580, 31, 1, 32; +L_0x2a5dc00 .part v0x2960210_0, 0, 1; +L_0x2a5dd30 .part v0x2960210_0, 1, 1; +L_0x2a5de60 .part RS_0x7f507e9a6998, 31, 1; +L_0x2a5df00 .part RS_0x7f507e9a6998, 31, 1; +L_0x2a5dfa0 .part RS_0x7f507e9a3368, 31, 1; +L_0x2a5e090 .part RS_0x7f507e9a3368, 31, 1; +L_0x2a2b1f0 .part/pv L_0x2a2b0b0, 31, 1, 32; +L_0x2a2b290 .part v0x2960210_0, 2, 1; +L_0x2a2b330 .part RS_0x7f507e9b8f68, 31, 1; +L_0x2a2b420 .part RS_0x7f507e9b8f98, 31, 1; +L_0x2a2b510 .part/pv L_0x2a5e180, 31, 1, 32; +L_0x2a5e280 .part RS_0x7f507e9b8ff8, 30, 1; +L_0x2a5e320 .part RS_0x7f507e9b8fc8, 31, 1; +L_0x2b14240 .part/pv L_0x2b14060, 0, 1, 32; +L_0x2a61c30 .part v0x2960210_0, 0, 1; +L_0x2a61d60 .part v0x2960210_0, 1, 1; +L_0x2a61e90 .part RS_0x7f507e9ad5c8, 0, 1; +L_0x2a61f30 .part RS_0x7f507e9ad5c8, 0, 1; +L_0x2a61fd0 .part RS_0x7f507e9a3368, 0, 1; +L_0x2a620c0 .part RS_0x7f507e9b8c98, 0, 1; +L_0x2a62950 .part/pv L_0x2a62740, 0, 1, 32; +L_0x2a629f0 .part v0x2960210_0, 0, 1; +L_0x2a62b20 .part v0x2960210_0, 1, 1; +L_0x2a62c50 .part RS_0x7f507e9a6998, 0, 1; +L_0x2a62cf0 .part RS_0x7f507e9a6998, 0, 1; +L_0x2a62d90 .part RS_0x7f507e9a3368, 0, 1; +L_0x2a62e80 .part RS_0x7f507e9a3368, 0, 1; +L_0x2b15ad0 .part/pv L_0x2b15990, 0, 1, 32; +L_0x2a3ade0 .part v0x2960210_0, 2, 1; +L_0x2a3ae80 .part RS_0x7f507e9b8f68, 0, 1; +L_0x2a3af70 .part RS_0x7f507e9b8f98, 0, 1; +L_0x2a3b060 .part/pv L_0x2a3b100, 0, 1, 32; +L_0x2a254f0 .part RS_0x7f507e9b8fc8, 0, 1; +L_0x2a25590 .part RS_0x7f507e9b8fc8, 0, 1; +L_0x2a25770 .part RS_0x7f507e9b8ff8, 31, 1; +S_0x2864a60 .scope module, "test" "SLT32" 3 385, 3 298, S_0x25e6a40; + .timescale -9 -12; +P_0x2863d28 .param/l "size" 3 330, +C4<0100000>; +L_0x2aa2e90/d .functor NOT 1, L_0x2aa2f80, C4<0>, C4<0>, C4<0>; +L_0x2aa2e90 .delay (10000,10000,10000) L_0x2aa2e90/d; +L_0x2aa3020/d .functor AND 1, L_0x2aa3160, L_0x2aa3200, L_0x2aa2e90, C4<1>; +L_0x2aa3020 .delay (20000,20000,20000) L_0x2aa3020/d; +L_0x2a82310/d .functor OR 1, L_0x2a82400, C4<0>, C4<0>, C4<0>; +L_0x2a82310 .delay (20000,20000,20000) L_0x2a82310/d; +L_0x2aa45c0/d .functor XOR 1, RS_0x7f507e9ad6e8, L_0x2aa14e0, C4<0>, C4<0>; +L_0x2aa45c0 .delay (40000,40000,40000) L_0x2aa45c0/d; +L_0x2aa1580/d .functor NOT 1, RS_0x7f507e9ad718, C4<0>, C4<0>, C4<0>; +L_0x2aa1580 .delay (10000,10000,10000) L_0x2aa1580/d; +L_0x2aa46b0/d .functor NOT 1, L_0x2aa5c00, C4<0>, C4<0>, C4<0>; +L_0x2aa46b0 .delay (10000,10000,10000) L_0x2aa46b0/d; +L_0x2aa5ca0/d .functor AND 1, L_0x2aa1580, L_0x2aa5de0, C4<1>, C4<1>; +L_0x2aa5ca0 .delay (20000,20000,20000) L_0x2aa5ca0/d; +L_0x2aa5e80/d .functor AND 1, RS_0x7f507e9ad718, L_0x2aa46b0, C4<1>, C4<1>; +L_0x2aa5e80 .delay (20000,20000,20000) L_0x2aa5e80/d; +L_0x2a82640/d .functor AND 1, L_0x2aa5ca0, L_0x2aa3020, C4<1>, C4<1>; +L_0x2a82640 .delay (20000,20000,20000) L_0x2a82640/d; +L_0x2a82760/d .functor AND 1, L_0x2aa5e80, L_0x2aa3020, C4<1>, C4<1>; +L_0x2a82760 .delay (20000,20000,20000) L_0x2a82760/d; +L_0x2a828d0/d .functor OR 1, L_0x2a82640, L_0x2a82760, C4<0>, C4<0>; +L_0x2a828d0 .delay (20000,20000,20000) L_0x2a828d0/d; +v0x289ef10_0 .alias "A", 31 0, v0x295f580_0; +RS_0x7f507e9b8ba8/0/0 .resolv tri, L_0x2881940, L_0x2a64e50, L_0x2a66f90, L_0x2a69140; +RS_0x7f507e9b8ba8/0/4 .resolv tri, L_0x2a6b2b0, L_0x2a6d320, L_0x2a6f570, L_0x2a717c0; +RS_0x7f507e9b8ba8/0/8 .resolv tri, L_0x2a73aa0, L_0x2a75cd0, L_0x2a77ec0, L_0x2a7a150; +RS_0x7f507e9b8ba8/0/12 .resolv tri, L_0x2a7c2b0, L_0x2a7e3f0, L_0x2a80640, L_0x2a82a10; +RS_0x7f507e9b8ba8/0/16 .resolv tri, L_0x2a601e0, L_0x2a87810, L_0x2a89a20, L_0x2a8bbf0; +RS_0x7f507e9b8ba8/0/20 .resolv tri, L_0x2a8ddd0, L_0x2a8ffa0, L_0x2a90f40, L_0x2a94770; +RS_0x7f507e9b8ba8/0/24 .resolv tri, L_0x2a94f50, L_0x2a972e0, L_0x2a99910, L_0x2a9bcc0; +RS_0x7f507e9b8ba8/0/28 .resolv tri, L_0x2a9dd00, L_0x2aa0090, L_0x2aa20b0, L_0x2aa4350; +RS_0x7f507e9b8ba8/1/0 .resolv tri, RS_0x7f507e9b8ba8/0/0, RS_0x7f507e9b8ba8/0/4, RS_0x7f507e9b8ba8/0/8, RS_0x7f507e9b8ba8/0/12; +RS_0x7f507e9b8ba8/1/4 .resolv tri, RS_0x7f507e9b8ba8/0/16, RS_0x7f507e9b8ba8/0/20, RS_0x7f507e9b8ba8/0/24, RS_0x7f507e9b8ba8/0/28; +RS_0x7f507e9b8ba8 .resolv tri, RS_0x7f507e9b8ba8/1/0, RS_0x7f507e9b8ba8/1/4, C4, C4; +v0x2604180_0 .net8 "AddSubSLTSum", 31 0, RS_0x7f507e9b8ba8; 32 drivers +v0x289f0e0_0 .alias "B", 31 0, v0x295f6a0_0; +RS_0x7f507e9b8bd8/0/0 .resolv tri, L_0x2a5fbf0, L_0x2a645e0, L_0x2a66770, L_0x2a67820; +RS_0x7f507e9b8bd8/0/4 .resolv tri, L_0x2a6aa90, L_0x2a6ba50, L_0x2a6ed30, L_0x2a6fd60; +RS_0x7f507e9b8bd8/0/8 .resolv tri, L_0x2a73280, L_0x2a74270, L_0x2a776b0, L_0x2a78a90; +RS_0x7f507e9b8bd8/0/12 .resolv tri, L_0x2a7ba90, L_0x2a7ca90, L_0x2a7fe10, L_0x2a80e30; +RS_0x7f507e9b8bd8/0/16 .resolv tri, L_0x2a84600, L_0x2a85cc0, L_0x2a891e0, L_0x2a89bb0; +RS_0x7f507e9b8bd8/0/20 .resolv tri, L_0x2a8d5c0, L_0x2a8df60, L_0x2a91d70, L_0x2a92720; +RS_0x7f507e9b8bd8/0/24 .resolv tri, L_0x2a96140, L_0x2a96b00, L_0x2a9a4f0, L_0x2a9b4e0; +RS_0x7f507e9b8bd8/0/28 .resolv tri, L_0x2a9e8f0, L_0x2a9f8b0, L_0x2aa2cb0, L_0x2aa5300; +RS_0x7f507e9b8bd8/1/0 .resolv tri, RS_0x7f507e9b8bd8/0/0, RS_0x7f507e9b8bd8/0/4, RS_0x7f507e9b8bd8/0/8, RS_0x7f507e9b8bd8/0/12; +RS_0x7f507e9b8bd8/1/4 .resolv tri, RS_0x7f507e9b8bd8/0/16, RS_0x7f507e9b8bd8/0/20, RS_0x7f507e9b8bd8/0/24, RS_0x7f507e9b8bd8/0/28; +RS_0x7f507e9b8bd8 .resolv tri, RS_0x7f507e9b8bd8/1/0, RS_0x7f507e9b8bd8/1/4, C4, C4; +v0x25ee970_0 .net8 "CarryoutWire", 31 0, RS_0x7f507e9b8bd8; 32 drivers +v0x289f2a0_0 .alias "Command", 2 0, v0x295f7a0_0; +RS_0x7f507e9b8c08/0/0 .resolv tri, L_0x2a5fb00, L_0x2a64480, L_0x2a66680, L_0x2a687b0; +RS_0x7f507e9b8c08/0/4 .resolv tri, L_0x2a6a9a0, L_0x2a6ca50, L_0x2a6ec40, L_0x2a70db0; +RS_0x7f507e9b8c08/0/8 .resolv tri, L_0x2a73190, L_0x2a75380, L_0x2a775c0, L_0x2a79880; +RS_0x7f507e9b8c08/0/12 .resolv tri, L_0x2a7b9a0, L_0x2a7daf0, L_0x2a7fd20, L_0x2a81f10; +RS_0x7f507e9b8c08/0/16 .resolv tri, L_0x2a84510, L_0x2a86ee0, L_0x2a890f0, L_0x2a8b2c0; +RS_0x7f507e9b8c08/0/20 .resolv tri, L_0x2a8d4d0, L_0x2a8f6a0, L_0x2a91c80, L_0x2a93e60; +RS_0x7f507e9b8c08/0/24 .resolv tri, L_0x2a96050, L_0x2a98210, L_0x2a9a400, L_0x2a9c5e0; +RS_0x7f507e9b8c08/0/28 .resolv tri, L_0x2a9e800, L_0x2aa09b0, L_0x2aa2bc0, L_0x2aa5210; +RS_0x7f507e9b8c08/1/0 .resolv tri, RS_0x7f507e9b8c08/0/0, RS_0x7f507e9b8c08/0/4, RS_0x7f507e9b8c08/0/8, RS_0x7f507e9b8c08/0/12; +RS_0x7f507e9b8c08/1/4 .resolv tri, RS_0x7f507e9b8c08/0/16, RS_0x7f507e9b8c08/0/20, RS_0x7f507e9b8c08/0/24, RS_0x7f507e9b8c08/0/28; +RS_0x7f507e9b8c08 .resolv tri, RS_0x7f507e9b8c08/1/0, RS_0x7f507e9b8c08/1/4, C4, C4; +v0x289f320_0 .net8 "NewVal", 31 0, RS_0x7f507e9b8c08; 32 drivers +v0x289f3c0_0 .net "Res0OF1", 0 0, L_0x2aa5e80; 1 drivers +v0x289f460_0 .net "Res1OF0", 0 0, L_0x2aa5ca0; 1 drivers +v0x289f500_0 .alias "SLTSum", 31 0, v0x2960440_0; +v0x289f5a0_0 .alias "SLTflag", 0 0, v0x29604c0_0; +v0x289f620_0 .net "SLTflag0", 0 0, L_0x2a82640; 1 drivers +v0x289f6c0_0 .net "SLTflag1", 0 0, L_0x2a82760; 1 drivers +v0x289f760_0 .net "SLTon", 0 0, L_0x2aa3020; 1 drivers +v0x289f7e0_0 .net *"_s497", 0 0, L_0x2aa2f80; 1 drivers +v0x289f900_0 .net *"_s499", 0 0, L_0x2aa3160; 1 drivers +v0x289f9a0_0 .net *"_s501", 0 0, L_0x2aa3200; 1 drivers +v0x289f860_0 .net *"_s521", 0 0, L_0x2a82400; 1 drivers +v0x289faf0_0 .net/s *"_s522", 0 0, C4<0>; 1 drivers +v0x289fc10_0 .net *"_s525", 0 0, L_0x2aa14e0; 1 drivers +v0x289fc90_0 .net *"_s527", 0 0, L_0x2aa5c00; 1 drivers +v0x289fb70_0 .net *"_s529", 0 0, L_0x2aa5de0; 1 drivers +v0x289fdc0_0 .alias "carryin", 31 0, v0x295fa50_0; +v0x289fd10_0 .alias "carryout", 0 0, v0x2960870_0; +v0x289ff00_0 .net "nAddSubSLTSum", 0 0, L_0x2aa46b0; 1 drivers +v0x289fe40_0 .net "nCmd2", 0 0, L_0x2aa2e90; 1 drivers +v0x28a0050_0 .net "nOF", 0 0, L_0x2aa1580; 1 drivers +v0x289ff80_0 .alias "overflow", 0 0, v0x2960980_0; +v0x28a01b0_0 .alias "subtract", 31 0, v0x2960aa0_0; +L_0x2a5fb00 .part/pv L_0x2a5ee60, 1, 1, 32; +L_0x2a5fbf0 .part/pv L_0x2a5f9c0, 1, 1, 32; +L_0x2a5fce0 .part/pv L_0x2a5eb90, 1, 1, 32; +L_0x2a5fdd0 .part v0x295fe90_0, 1, 1; +L_0x2a5fe70 .part v0x2960190_0, 1, 1; +L_0x2a5ffa0 .part RS_0x7f507e9b8bd8, 0, 1; +L_0x2881940 .part/pv L_0x2a60ad0, 1, 1, 32; +L_0x2881a30 .part RS_0x7f507e9b8c08, 1, 1; +L_0x2a632c0 .part/pv L_0x2a63180, 1, 1, 32; +L_0x2a63360 .part RS_0x7f507e9b8ba8, 1, 1; +L_0x2a63500 .part RS_0x7f507e9b8ba8, 1, 1; +L_0x2a64480 .part/pv L_0x2a63ff0, 2, 1, 32; +L_0x2a645e0 .part/pv L_0x2a64340, 2, 1, 32; +L_0x2a646d0 .part/pv L_0x2a63d20, 2, 1, 32; +L_0x2a64840 .part v0x295fe90_0, 2, 1; +L_0x2a648e0 .part v0x2960190_0, 2, 1; +L_0x2a64aa0 .part RS_0x7f507e9b8bd8, 1, 1; +L_0x2a64e50 .part/pv L_0x2a64d10, 2, 1, 32; +L_0x2a65020 .part RS_0x7f507e9b8c08, 2, 1; +L_0x2a65500 .part/pv L_0x2a653c0, 2, 1, 32; +L_0x2a64f80 .part RS_0x7f507e9b8ba8, 2, 1; +L_0x2a656a0 .part RS_0x7f507e9b8ba8, 2, 1; +L_0x2a66680 .part/pv L_0x2a661f0, 3, 1, 32; +L_0x2a66770 .part/pv L_0x2a66540, 3, 1, 32; +L_0x2a65790 .part/pv L_0x2a65f20, 3, 1, 32; +L_0x2a66980 .part v0x295fe90_0, 3, 1; +L_0x2a66860 .part v0x2960190_0, 3, 1; +L_0x2a66b90 .part RS_0x7f507e9b8bd8, 2, 1; +L_0x2a66f90 .part/pv L_0x2a66e50, 3, 1, 32; +L_0x2a67030 .part RS_0x7f507e9b8c08, 3, 1; +L_0x2a67580 .part/pv L_0x2a67440, 3, 1, 32; +L_0x2a67620 .part RS_0x7f507e9b8ba8, 3, 1; +L_0x2a67120 .part RS_0x7f507e9b8ba8, 3, 1; +L_0x2a687b0 .part/pv L_0x2a68320, 4, 1, 32; +L_0x2a67820 .part/pv L_0x2a68670, 4, 1, 32; +L_0x2a689c0 .part/pv L_0x2a68050, 4, 1, 32; +L_0x2a688a0 .part v0x295fe90_0, 4, 1; +L_0x2a68be0 .part v0x2960190_0, 4, 1; +L_0x2a68ab0 .part RS_0x7f507e9b8bd8, 3, 1; +L_0x2a69140 .part/pv L_0x2a69000, 4, 1, 32; +L_0x2a68d10 .part RS_0x7f507e9b8c08, 4, 1; +L_0x2a697f0 .part/pv L_0x2a696b0, 4, 1, 32; +L_0x2a691e0 .part RS_0x7f507e9b8ba8, 4, 1; +L_0x2a699f0 .part RS_0x7f507e9b8ba8, 4, 1; +L_0x2a6a9a0 .part/pv L_0x2a6a510, 5, 1, 32; +L_0x2a6aa90 .part/pv L_0x2a6a860, 5, 1, 32; +L_0x2a69a90 .part/pv L_0x2a6a240, 5, 1, 32; +L_0x2a6ad00 .part v0x295fe90_0, 5, 1; +L_0x2a6ab80 .part v0x2960190_0, 5, 1; +L_0x2a6af30 .part RS_0x7f507e9b8bd8, 4, 1; +L_0x2a6b2b0 .part/pv L_0x2a6b170, 5, 1, 32; +L_0x2a6b350 .part RS_0x7f507e9b8c08, 5, 1; +L_0x2a6b8c0 .part/pv L_0x2a6b780, 5, 1, 32; +L_0x2a6b960 .part RS_0x7f507e9b8ba8, 5, 1; +L_0x2a6b440 .part RS_0x7f507e9b8ba8, 5, 1; +L_0x2a6ca50 .part/pv L_0x2a6c5c0, 6, 1, 32; +L_0x2a6ba50 .part/pv L_0x2a6c910, 6, 1, 32; +L_0x2a6bb40 .part/pv L_0x2a6c2f0, 6, 1, 32; +L_0x2a6cb40 .part v0x295fe90_0, 6, 1; +L_0x2a6cbe0 .part v0x2960190_0, 6, 1; +L_0x2a6cf50 .part RS_0x7f507e9b8bd8, 5, 1; +L_0x2a6d320 .part/pv L_0x2a6d1e0, 6, 1, 32; +L_0x2a67710 .part RS_0x7f507e9b8c08, 6, 1; +L_0x2a6daa0 .part/pv L_0x2a6d960, 6, 1, 32; +L_0x2a6d5d0 .part RS_0x7f507e9b8ba8, 6, 1; +L_0x2a6d6c0 .part RS_0x7f507e9b8ba8, 6, 1; +L_0x2a6ec40 .part/pv L_0x2a6e7b0, 7, 1, 32; +L_0x2a6ed30 .part/pv L_0x2a6eb00, 7, 1, 32; +L_0x2a6db40 .part/pv L_0x2a6e4e0, 7, 1, 32; +L_0x2a6dc30 .part v0x295fe90_0, 7, 1; +L_0x2a6f060 .part v0x2960190_0, 7, 1; +L_0x2a6f100 .part RS_0x7f507e9b8bd8, 6, 1; +L_0x2a6f570 .part/pv L_0x2a6f430, 7, 1, 32; +L_0x2a6f610 .part RS_0x7f507e9b8c08, 7, 1; +L_0x2a6fbd0 .part/pv L_0x2a6fa90, 7, 1, 32; +L_0x2a6fc70 .part RS_0x7f507e9b8ba8, 7, 1; +L_0x2a6f700 .part RS_0x7f507e9b8ba8, 7, 1; +L_0x2a70db0 .part/pv L_0x2a708e0, 8, 1, 32; +L_0x2a6fd60 .part/pv L_0x2a70c50, 8, 1, 32; +L_0x2a6fe50 .part/pv L_0x2a70610, 8, 1, 32; +L_0x2a71130 .part v0x295fe90_0, 8, 1; +L_0x2a711d0 .part v0x2960190_0, 8, 1; +L_0x2a70ea0 .part RS_0x7f507e9b8bd8, 7, 1; +L_0x2a717c0 .part/pv L_0x2a71090, 8, 1, 32; +L_0x2a71270 .part RS_0x7f507e9b8c08, 8, 1; +L_0x2a71ef0 .part/pv L_0x2a71db0, 8, 1, 32; +L_0x2a71860 .part RS_0x7f507e9b8ba8, 8, 1; +L_0x2a71950 .part RS_0x7f507e9b8ba8, 8, 1; +L_0x2a73190 .part/pv L_0x2a72ce0, 9, 1, 32; +L_0x2a73280 .part/pv L_0x2a73030, 9, 1, 32; +L_0x2a71f90 .part/pv L_0x2a72a10, 9, 1, 32; +L_0x2a72080 .part v0x295fe90_0, 9, 1; +L_0x2a72120 .part v0x2960190_0, 9, 1; +L_0x2a73660 .part RS_0x7f507e9b8bd8, 8, 1; +L_0x2a73aa0 .part/pv L_0x2a735c0, 9, 1, 32; +L_0x2a73b40 .part RS_0x7f507e9b8c08, 9, 1; +L_0x2a740e0 .part/pv L_0x2a73fa0, 9, 1, 32; +L_0x2a74180 .part RS_0x7f507e9b8ba8, 9, 1; +L_0x2a73c30 .part RS_0x7f507e9b8ba8, 9, 1; +L_0x2a75380 .part/pv L_0x2a74ed0, 10, 1, 32; +L_0x2a74270 .part/pv L_0x2a75220, 10, 1, 32; +L_0x2a74360 .part/pv L_0x2a74c00, 10, 1, 32; +L_0x2a74450 .part v0x295fe90_0, 10, 1; +L_0x2a744f0 .part v0x2960190_0, 10, 1; +L_0x2a75470 .part RS_0x7f507e9b8bd8, 9, 1; +L_0x2a75cd0 .part/pv L_0x2a75b90, 10, 1, 32; +L_0x2a75840 .part RS_0x7f507e9b8c08, 10, 1; +L_0x2a76340 .part/pv L_0x2a76200, 10, 1, 32; +L_0x2a75d70 .part RS_0x7f507e9b8ba8, 10, 1; +L_0x2a75e60 .part RS_0x7f507e9b8ba8, 10, 1; +L_0x2a775c0 .part/pv L_0x2a770f0, 11, 1, 32; +L_0x2a776b0 .part/pv L_0x2a77460, 11, 1, 32; +L_0x2a763e0 .part/pv L_0x2a76e20, 11, 1, 32; +L_0x2a764d0 .part v0x295fe90_0, 11, 1; +L_0x2a76570 .part v0x2960190_0, 11, 1; +L_0x2a766a0 .part RS_0x7f507e9b8bd8, 10, 1; +L_0x2a77ec0 .part/pv L_0x2a77d80, 11, 1, 32; +L_0x2a77f60 .part RS_0x7f507e9b8c08, 11, 1; +L_0x2a784f0 .part/pv L_0x2a77af0, 11, 1, 32; +L_0x2a78590 .part RS_0x7f507e9b8ba8, 11, 1; +L_0x2a6d3c0 .part RS_0x7f507e9b8ba8, 11, 1; +L_0x2a79880 .part/pv L_0x2a793f0, 12, 1, 32; +L_0x2a78a90 .part/pv L_0x2a79740, 12, 1, 32; +L_0x2a78b80 .part/pv L_0x2a79120, 12, 1, 32; +L_0x2a78c70 .part v0x295fe90_0, 12, 1; +L_0x2a78d10 .part v0x2960190_0, 12, 1; +L_0x2a79d70 .part RS_0x7f507e9b8bd8, 11, 1; +L_0x2a7a150 .part/pv L_0x2a7a010, 12, 1, 32; +L_0x2a79970 .part RS_0x7f507e9b8c08, 12, 1; +L_0x2a7a7e0 .part/pv L_0x2a7a6a0, 12, 1, 32; +L_0x2a7a1f0 .part RS_0x7f507e9b8ba8, 12, 1; +L_0x2a7a2e0 .part RS_0x7f507e9b8ba8, 12, 1; +L_0x2a7b9a0 .part/pv L_0x2a7b510, 13, 1, 32; +L_0x2a7ba90 .part/pv L_0x2a7b860, 13, 1, 32; +L_0x2a7a880 .part/pv L_0x2a7b240, 13, 1, 32; +L_0x2a7a970 .part v0x295fe90_0, 13, 1; +L_0x2a7aa10 .part v0x2960190_0, 13, 1; +L_0x2a7ab40 .part RS_0x7f507e9b8bd8, 12, 1; +L_0x2a7c2b0 .part/pv L_0x2a7c170, 13, 1, 32; +L_0x2a7c350 .part RS_0x7f507e9b8c08, 13, 1; +L_0x2a7c900 .part/pv L_0x2a7bed0, 13, 1, 32; +L_0x2a7c9a0 .part RS_0x7f507e9b8ba8, 13, 1; +L_0x2a7c440 .part RS_0x7f507e9b8ba8, 13, 1; +L_0x2a7daf0 .part/pv L_0x2a7d640, 14, 1, 32; +L_0x2a7ca90 .part/pv L_0x2a7d990, 14, 1, 32; +L_0x2a7cb80 .part/pv L_0x2a7d370, 14, 1, 32; +L_0x2a7cc70 .part v0x295fe90_0, 14, 1; +L_0x2a7cd10 .part v0x2960190_0, 14, 1; +L_0x2a7ce40 .part RS_0x7f507e9b8bd8, 13, 1; +L_0x2a7e3f0 .part/pv L_0x2a7e280, 14, 1, 32; +L_0x2a7dbe0 .part RS_0x7f507e9b8c08, 14, 1; +L_0x2a7ea90 .part/pv L_0x2a7e950, 14, 1, 32; +L_0x2a7e490 .part RS_0x7f507e9b8ba8, 14, 1; +L_0x2a7e530 .part RS_0x7f507e9b8ba8, 14, 1; +L_0x2a7fd20 .part/pv L_0x2a7f810, 15, 1, 32; +L_0x2a7fe10 .part/pv L_0x2a7fbc0, 15, 1, 32; +L_0x2a7eb30 .part/pv L_0x2a7f540, 15, 1, 32; +L_0x2a7ec20 .part v0x295fe90_0, 15, 1; +L_0x2a7ecc0 .part v0x2960190_0, 15, 1; +L_0x2a7edf0 .part RS_0x7f507e9b8bd8, 14, 1; +L_0x2a80640 .part/pv L_0x2a80500, 15, 1, 32; +L_0x2a806e0 .part RS_0x7f507e9b8c08, 15, 1; +L_0x2a80cf0 .part/pv L_0x2a80250, 15, 1, 32; +L_0x2a80d90 .part RS_0x7f507e9b8ba8, 15, 1; +L_0x2a807d0 .part RS_0x7f507e9b8ba8, 15, 1; +L_0x2a81f10 .part/pv L_0x2a81a30, 16, 1, 32; +L_0x2a80e30 .part/pv L_0x2a81db0, 16, 1, 32; +L_0x2a80f20 .part/pv L_0x2a81760, 16, 1, 32; +L_0x2a81010 .part v0x295fe90_0, 16, 1; +L_0x2a810b0 .part v0x2960190_0, 16, 1; +L_0x2a811e0 .part RS_0x7f507e9b8bd8, 15, 1; +L_0x2a82a10 .part/pv L_0x2a71680, 16, 1, 32; +L_0x2a82000 .part RS_0x7f507e9b8c08, 16, 1; +L_0x2a83250 .part/pv L_0x2a83110, 16, 1, 32; +L_0x2a82ab0 .part RS_0x7f507e9b8ba8, 16, 1; +L_0x2a82ba0 .part RS_0x7f507e9b8ba8, 16, 1; +L_0x2a84510 .part/pv L_0x2a84000, 17, 1, 32; +L_0x2a84600 .part/pv L_0x2a843b0, 17, 1, 32; +L_0x2a832f0 .part/pv L_0x2a83d30, 17, 1, 32; +L_0x2a833e0 .part v0x295fe90_0, 17, 1; +L_0x2a83480 .part v0x2960190_0, 17, 1; +L_0x2a835b0 .part RS_0x7f507e9b8bd8, 16, 1; +L_0x2a601e0 .part/pv L_0x2a600a0, 17, 1, 32; +L_0x2a60280 .part RS_0x7f507e9b8c08, 17, 1; +L_0x2a846f0 .part/pv L_0x2a606e0, 17, 1, 32; +L_0x2a84790 .part RS_0x7f507e9b8ba8, 17, 1; +L_0x2a84880 .part RS_0x7f507e9b8ba8, 17, 1; +L_0x2a86ee0 .part/pv L_0x2a86a30, 18, 1, 32; +L_0x2a85cc0 .part/pv L_0x2a86d80, 18, 1, 32; +L_0x2a85db0 .part/pv L_0x2a86760, 18, 1, 32; +L_0x2a85ea0 .part v0x295fe90_0, 18, 1; +L_0x2a85f40 .part v0x2960190_0, 18, 1; +L_0x2a86070 .part RS_0x7f507e9b8bd8, 17, 1; +L_0x2a87810 .part/pv L_0x2a876d0, 18, 1, 32; +L_0x2a86fd0 .part RS_0x7f507e9b8c08, 18, 1; +L_0x2a87ed0 .part/pv L_0x2a71b60, 18, 1, 32; +L_0x2a878b0 .part RS_0x7f507e9b8ba8, 18, 1; +L_0x2a879a0 .part RS_0x7f507e9b8ba8, 18, 1; +L_0x2a890f0 .part/pv L_0x2a88be0, 19, 1, 32; +L_0x2a891e0 .part/pv L_0x2a88f90, 19, 1, 32; +L_0x2a87f70 .part/pv L_0x2a88910, 19, 1, 32; +L_0x2a88060 .part v0x295fe90_0, 19, 1; +L_0x2a88100 .part v0x2960190_0, 19, 1; +L_0x2a88230 .part RS_0x7f507e9b8bd8, 18, 1; +L_0x2a89a20 .part/pv L_0x2a88520, 19, 1, 32; +L_0x2a89ac0 .part RS_0x7f507e9b8c08, 19, 1; +L_0x2a89760 .part/pv L_0x2a89620, 19, 1, 32; +L_0x2a89800 .part RS_0x7f507e9b8ba8, 19, 1; +L_0x2a8a240 .part RS_0x7f507e9b8ba8, 19, 1; +L_0x2a8b2c0 .part/pv L_0x2a8ae10, 20, 1, 32; +L_0x2a89bb0 .part/pv L_0x2a8b160, 20, 1, 32; +L_0x2a89ca0 .part/pv L_0x2a8ab40, 20, 1, 32; +L_0x2a89d90 .part v0x295fe90_0, 20, 1; +L_0x2a89e30 .part v0x2960190_0, 20, 1; +L_0x2a89f60 .part RS_0x7f507e9b8bd8, 19, 1; +L_0x2a8bbf0 .part/pv L_0x2a8bab0, 20, 1, 32; +L_0x2a8b3b0 .part RS_0x7f507e9b8c08, 20, 1; +L_0x2a871e0 .part/pv L_0x2a8b9b0, 20, 1, 32; +L_0x2a8c370 .part RS_0x7f507e9b8ba8, 20, 1; +L_0x2a8c410 .part RS_0x7f507e9b8ba8, 20, 1; +L_0x2a8d4d0 .part/pv L_0x2a8d040, 21, 1, 32; +L_0x2a8d5c0 .part/pv L_0x2a8d390, 21, 1, 32; +L_0x2a8c500 .part/pv L_0x2a8cd70, 21, 1, 32; +L_0x2a8c5f0 .part v0x295fe90_0, 21, 1; +L_0x2a8c690 .part v0x2960190_0, 21, 1; +L_0x2a8c7c0 .part RS_0x7f507e9b8bd8, 20, 1; +L_0x2a8ddd0 .part/pv L_0x2a8cab0, 21, 1, 32; +L_0x2a8de70 .part RS_0x7f507e9b8c08, 21, 1; +L_0x2a8db40 .part/pv L_0x2a8da00, 21, 1, 32; +L_0x2a8dbe0 .part RS_0x7f507e9b8ba8, 21, 1; +L_0x2a8dcd0 .part RS_0x7f507e9b8ba8, 21, 1; +L_0x2a8f6a0 .part/pv L_0x2a8f1f0, 22, 1, 32; +L_0x2a8df60 .part/pv L_0x2a8f540, 22, 1, 32; +L_0x2a8e050 .part/pv L_0x2a8ef20, 22, 1, 32; +L_0x2a8e140 .part v0x295fe90_0, 22, 1; +L_0x2a8e1e0 .part v0x2960190_0, 22, 1; +L_0x2a8e310 .part RS_0x7f507e9b8bd8, 21, 1; +L_0x2a8ffa0 .part/pv L_0x2a8e600, 22, 1, 32; +L_0x2a78680 .part RS_0x7f507e9b8c08, 22, 1; +L_0x2a8f910 .part/pv L_0x2a8f7d0, 22, 1, 32; +L_0x2a8f9b0 .part RS_0x7f507e9b8ba8, 22, 1; +L_0x2a8faa0 .part RS_0x7f507e9b8ba8, 22, 1; +L_0x2a91c80 .part/pv L_0x2a917d0, 23, 1, 32; +L_0x2a91d70 .part/pv L_0x2a91b20, 23, 1, 32; +L_0x2a90850 .part/pv L_0x2a91500, 23, 1, 32; +L_0x2a90940 .part v0x295fe90_0, 23, 1; +L_0x2a909e0 .part v0x2960190_0, 23, 1; +L_0x2a90b10 .part RS_0x7f507e9b8bd8, 22, 1; +L_0x2a90f40 .part/pv L_0x2a90e00, 23, 1, 32; +L_0x2a92630 .part RS_0x7f507e9b8c08, 23, 1; +L_0x2a922f0 .part/pv L_0x2a921b0, 23, 1, 32; +L_0x2a92390 .part RS_0x7f507e9b8ba8, 23, 1; +L_0x2a92480 .part RS_0x7f507e9b8ba8, 23, 1; +L_0x2a93e60 .part/pv L_0x2a939b0, 24, 1, 32; +L_0x2a92720 .part/pv L_0x2a93d00, 24, 1, 32; +L_0x2a92810 .part/pv L_0x2a936e0, 24, 1, 32; +L_0x2a92900 .part v0x295fe90_0, 24, 1; +L_0x2a929a0 .part v0x2960190_0, 24, 1; +L_0x2a92ad0 .part RS_0x7f507e9b8bd8, 23, 1; +L_0x2a94770 .part/pv L_0x2a92dc0, 24, 1, 32; +L_0x2a93f50 .part RS_0x7f507e9b8c08, 24, 1; +L_0x2a94650 .part/pv L_0x2a94510, 24, 1, 32; +L_0x2a78800 .part RS_0x7f507e9b8ba8, 24, 1; +L_0x2a788f0 .part RS_0x7f507e9b8ba8, 24, 1; +L_0x2a96050 .part/pv L_0x2a95ba0, 25, 1, 32; +L_0x2a96140 .part/pv L_0x2a95ef0, 25, 1, 32; +L_0x2a94860 .part/pv L_0x2a958d0, 25, 1, 32; +L_0x2a94950 .part v0x295fe90_0, 25, 1; +L_0x2a949f0 .part v0x2960190_0, 25, 1; +L_0x2a94b20 .part RS_0x7f507e9b8bd8, 24, 1; +L_0x2a94f50 .part/pv L_0x2a94e10, 25, 1, 32; +L_0x2a94ff0 .part RS_0x7f507e9b8c08, 25, 1; +L_0x2a966a0 .part/pv L_0x2a96560, 25, 1, 32; +L_0x2a96740 .part RS_0x7f507e9b8ba8, 25, 1; +L_0x2a96830 .part RS_0x7f507e9b8ba8, 25, 1; +L_0x2a98210 .part/pv L_0x2a97d60, 26, 1, 32; +L_0x2a96b00 .part/pv L_0x2a980b0, 26, 1, 32; +L_0x2a96bf0 .part/pv L_0x2a97a90, 26, 1, 32; +L_0x2a96ce0 .part v0x295fe90_0, 26, 1; +L_0x2a96d80 .part v0x2960190_0, 26, 1; +L_0x2a96eb0 .part RS_0x7f507e9b8bd8, 25, 1; +L_0x2a972e0 .part/pv L_0x2a971a0, 26, 1, 32; +L_0x2a98be0 .part RS_0x7f507e9b8c08, 26, 1; +L_0x2a99180 .part/pv L_0x2a99040, 26, 1, 32; +L_0x2a98300 .part RS_0x7f507e9b8ba8, 26, 1; +L_0x2a983f0 .part RS_0x7f507e9b8ba8, 26, 1; +L_0x2a9a400 .part/pv L_0x2a99f70, 27, 1, 32; +L_0x2a9a4f0 .part/pv L_0x2a9a2c0, 27, 1, 32; +L_0x2a99220 .part/pv L_0x2a99ca0, 27, 1, 32; +L_0x2a99310 .part v0x295fe90_0, 27, 1; +L_0x2a993b0 .part v0x2960190_0, 27, 1; +L_0x2a994e0 .part RS_0x7f507e9b8bd8, 26, 1; +L_0x2a99910 .part/pv L_0x2a997d0, 27, 1, 32; +L_0x2a999b0 .part RS_0x7f507e9b8c08, 27, 1; +L_0x2a9b350 .part/pv L_0x2a9b1e0, 27, 1, 32; +L_0x2a9b3f0 .part RS_0x7f507e9b8ba8, 27, 1; +L_0x2a9a5e0 .part RS_0x7f507e9b8ba8, 27, 1; +L_0x2a9c5e0 .part/pv L_0x2a9c150, 28, 1, 32; +L_0x2a9b4e0 .part/pv L_0x2a9c4a0, 28, 1, 32; +L_0x2a9b5d0 .part/pv L_0x2a9bed0, 28, 1, 32; +L_0x2a9b6c0 .part v0x295fe90_0, 28, 1; +L_0x2a9b760 .part v0x2960190_0, 28, 1; +L_0x2a9b890 .part RS_0x7f507e9b8bd8, 27, 1; +L_0x2a9bcc0 .part/pv L_0x2a9bb80, 28, 1, 32; +L_0x2a9bd60 .part RS_0x7f507e9b8c08, 28, 1; +L_0x2a9d570 .part/pv L_0x2a9d430, 28, 1, 32; +L_0x2a9c6d0 .part RS_0x7f507e9b8ba8, 28, 1; +L_0x2a9c7c0 .part RS_0x7f507e9b8ba8, 28, 1; +L_0x2a9e800 .part/pv L_0x2a9e370, 29, 1, 32; +L_0x2a9e8f0 .part/pv L_0x2a9e6c0, 29, 1, 32; +L_0x2a9d610 .part/pv L_0x2a9e0a0, 29, 1, 32; +L_0x2a9d700 .part v0x295fe90_0, 29, 1; +L_0x2a9d7a0 .part v0x2960190_0, 29, 1; +L_0x2a9d8d0 .part RS_0x7f507e9b8bd8, 28, 1; +L_0x2a9dd00 .part/pv L_0x2a9dbc0, 29, 1, 32; +L_0x2a9dda0 .part RS_0x7f507e9b8c08, 29, 1; +L_0x2a9f720 .part/pv L_0x2a9f5b0, 29, 1, 32; +L_0x2a9f7c0 .part RS_0x7f507e9b8ba8, 29, 1; +L_0x2a9e9e0 .part RS_0x7f507e9b8ba8, 29, 1; +L_0x2aa09b0 .part/pv L_0x2aa0520, 30, 1, 32; +L_0x2a9f8b0 .part/pv L_0x2aa0870, 30, 1, 32; +L_0x2a9f9a0 .part/pv L_0x2a9f370, 30, 1, 32; +L_0x2a9fa90 .part v0x295fe90_0, 30, 1; +L_0x2a9fb30 .part v0x2960190_0, 30, 1; +L_0x2a9fc60 .part RS_0x7f507e9b8bd8, 29, 1; +L_0x2aa0090 .part/pv L_0x2a9ff50, 30, 1, 32; +L_0x2aa0130 .part RS_0x7f507e9b8c08, 30, 1; +L_0x2aa1920 .part/pv L_0x2aa17e0, 30, 1, 32; +L_0x2aa0aa0 .part RS_0x7f507e9b8ba8, 30, 1; +L_0x2aa0b90 .part RS_0x7f507e9b8ba8, 30, 1; +L_0x2aa2bc0 .part/pv L_0x2aa2730, 31, 1, 32; +L_0x2aa2cb0 .part/pv L_0x2aa2a80, 31, 1, 32; +L_0x2aa19c0 .part/pv L_0x2aa1460, 31, 1, 32; +L_0x2aa1ab0 .part v0x295fe90_0, 31, 1; +L_0x2aa1b50 .part v0x2960190_0, 31, 1; +L_0x2aa1c80 .part RS_0x7f507e9b8bd8, 30, 1; +L_0x2aa20b0 .part/pv L_0x2aa1f70, 31, 1, 32; +L_0x2aa2150 .part RS_0x7f507e9b8c08, 31, 1; +L_0x2aa3ad0 .part/pv L_0x2aa3990, 31, 1, 32; +L_0x2aa3b70 .part RS_0x7f507e9b8ba8, 31, 1; +L_0x2aa2da0 .part RS_0x7f507e9b8ba8, 31, 1; +L_0x2aa2f80 .part v0x2960210_0, 2, 1; +L_0x2aa3160 .part v0x2960210_0, 0, 1; +L_0x2aa3200 .part v0x2960210_0, 1, 1; +L_0x2aa5210 .part/pv L_0x2aa4d30, 0, 1, 32; +L_0x2aa5300 .part/pv L_0x2aa50b0, 0, 1, 32; +L_0x2aa3c60 .part/pv L_0x2aa4a60, 0, 1, 32; +L_0x2aa3d50 .part v0x295fe90_0, 0, 1; +L_0x2aa3df0 .part v0x2960190_0, 0, 1; +L_0x2aa3f20 .part RS_0x7f507e9ad748, 0, 1; +L_0x2aa4350 .part/pv L_0x2aa4210, 0, 1, 32; +L_0x2aa43f0 .part RS_0x7f507e9b8c08, 0, 1; +L_0x2a82400 .part RS_0x7f507e9b8bd8, 31, 1; +L_0x2aa14e0 .part RS_0x7f507e9b8bd8, 30, 1; +L_0x2aa5c00 .part RS_0x7f507e9b8ba8, 31, 1; +L_0x2aa5de0 .part RS_0x7f507e9b8c08, 31, 1; +L_0x2aa7720 .part/pv L_0x2aa75e0, 0, 1, 32; +L_0x2aa77c0 .part RS_0x7f507e9b8ba8, 0, 1; +S_0x289def0 .scope module, "attempt2" "MiddleAddSubSLT" 3 326, 3 189, S_0x2864a60; + .timescale -9 -12; +L_0x2aa32f0/d .functor NOT 1, L_0x2aa3df0, C4<0>, C4<0>, C4<0>; +L_0x2aa32f0 .delay (10000,10000,10000) L_0x2aa32f0/d; +L_0x2aa4900/d .functor NOT 1, L_0x2aa49c0, C4<0>, C4<0>, C4<0>; +L_0x2aa4900 .delay (10000,10000,10000) L_0x2aa4900/d; +L_0x2aa4a60/d .functor AND 1, L_0x2aa4ba0, L_0x2aa4900, C4<1>, C4<1>; +L_0x2aa4a60 .delay (20000,20000,20000) L_0x2aa4a60/d; +L_0x2aa4c40/d .functor XOR 1, L_0x2aa3d50, L_0x2aa37a0, C4<0>, C4<0>; +L_0x2aa4c40 .delay (40000,40000,40000) L_0x2aa4c40/d; +L_0x2aa4d30/d .functor XOR 1, L_0x2aa4c40, L_0x2aa3f20, C4<0>, C4<0>; +L_0x2aa4d30 .delay (40000,40000,40000) L_0x2aa4d30/d; +L_0x2aa4e20/d .functor AND 1, L_0x2aa3d50, L_0x2aa37a0, C4<1>, C4<1>; +L_0x2aa4e20 .delay (20000,20000,20000) L_0x2aa4e20/d; +L_0x2aa4fc0/d .functor AND 1, L_0x2aa4c40, L_0x2aa3f20, C4<1>, C4<1>; +L_0x2aa4fc0 .delay (20000,20000,20000) L_0x2aa4fc0/d; +L_0x2aa50b0/d .functor OR 1, L_0x2aa4e20, L_0x2aa4fc0, C4<0>, C4<0>; +L_0x2aa50b0 .delay (20000,20000,20000) L_0x2aa50b0/d; +v0x289e570_0 .net "A", 0 0, L_0x2aa3d50; 1 drivers +v0x289e630_0 .net "AandB", 0 0, L_0x2aa4e20; 1 drivers +v0x289e6d0_0 .net "AddSubSLTSum", 0 0, L_0x2aa4d30; 1 drivers +v0x289e770_0 .net "AxorB", 0 0, L_0x2aa4c40; 1 drivers +v0x289e7f0_0 .net "B", 0 0, L_0x2aa3df0; 1 drivers +v0x289e8a0_0 .net "BornB", 0 0, L_0x2aa37a0; 1 drivers +v0x289e960_0 .net "CINandAxorB", 0 0, L_0x2aa4fc0; 1 drivers +v0x289e9e0_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x289ea60_0 .net *"_s3", 0 0, L_0x2aa49c0; 1 drivers +v0x289eae0_0 .net *"_s5", 0 0, L_0x2aa4ba0; 1 drivers +v0x289eb80_0 .net "carryin", 0 0, L_0x2aa3f20; 1 drivers +v0x289ec20_0 .net "carryout", 0 0, L_0x2aa50b0; 1 drivers +v0x289ecc0_0 .net "nB", 0 0, L_0x2aa32f0; 1 drivers +v0x289ed70_0 .net "nCmd2", 0 0, L_0x2aa4900; 1 drivers +v0x289ee70_0 .net "subtract", 0 0, L_0x2aa4a60; 1 drivers +L_0x2aa4860 .part v0x2960210_0, 0, 1; +L_0x2aa49c0 .part v0x2960210_0, 2, 1; +L_0x2aa4ba0 .part v0x2960210_0, 0, 1; +S_0x289dfe0 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x289def0; + .timescale -9 -12; +L_0x2aa34c0/d .functor NOT 1, L_0x2aa4860, C4<0>, C4<0>, C4<0>; +L_0x2aa34c0 .delay (10000,10000,10000) L_0x2aa34c0/d; +L_0x2aa3580/d .functor AND 1, L_0x2aa3df0, L_0x2aa34c0, C4<1>, C4<1>; +L_0x2aa3580 .delay (20000,20000,20000) L_0x2aa3580/d; +L_0x2aa3690/d .functor AND 1, L_0x2aa32f0, L_0x2aa4860, C4<1>, C4<1>; +L_0x2aa3690 .delay (20000,20000,20000) L_0x2aa3690/d; +L_0x2aa37a0/d .functor OR 1, L_0x2aa3580, L_0x2aa3690, C4<0>, C4<0>; +L_0x2aa37a0 .delay (20000,20000,20000) L_0x2aa37a0/d; +v0x289e0d0_0 .net "S", 0 0, L_0x2aa4860; 1 drivers +v0x289e190_0 .alias "in0", 0 0, v0x289e7f0_0; +v0x289e230_0 .alias "in1", 0 0, v0x289ecc0_0; +v0x289e2d0_0 .net "nS", 0 0, L_0x2aa34c0; 1 drivers +v0x289e350_0 .net "out0", 0 0, L_0x2aa3580; 1 drivers +v0x289e3f0_0 .net "out1", 0 0, L_0x2aa3690; 1 drivers +v0x289e4d0_0 .alias "outfinal", 0 0, v0x289e8a0_0; +S_0x289d980 .scope module, "setSLTresult" "TwoInMux" 3 327, 3 109, S_0x2864a60; + .timescale -9 -12; +L_0x2aa3fc0/d .functor NOT 1, L_0x2aa3020, C4<0>, C4<0>, C4<0>; +L_0x2aa3fc0 .delay (10000,10000,10000) L_0x2aa3fc0/d; +L_0x2aa4060/d .functor AND 1, L_0x2aa43f0, L_0x2aa3fc0, C4<1>, C4<1>; +L_0x2aa4060 .delay (20000,20000,20000) L_0x2aa4060/d; +L_0x2aa4170/d .functor AND 1, C4<0>, L_0x2aa3020, C4<1>, C4<1>; +L_0x2aa4170 .delay (20000,20000,20000) L_0x2aa4170/d; +L_0x2aa4210/d .functor OR 1, L_0x2aa4060, L_0x2aa4170, C4<0>, C4<0>; +L_0x2aa4210 .delay (20000,20000,20000) L_0x2aa4210/d; +v0x289da70_0 .alias "S", 0 0, v0x289f760_0; +v0x289db10_0 .net "in0", 0 0, L_0x2aa43f0; 1 drivers +v0x289dbb0_0 .net "in1", 0 0, C4<0>; 1 drivers +v0x289dc50_0 .net "nS", 0 0, L_0x2aa3fc0; 1 drivers +v0x289dcd0_0 .net "out0", 0 0, L_0x2aa4060; 1 drivers +v0x289dd70_0 .net "out1", 0 0, L_0x2aa4170; 1 drivers +v0x289de50_0 .net "outfinal", 0 0, L_0x2aa4210; 1 drivers +S_0x289d410 .scope module, "FinalSLT" "TwoInMux" 3 354, 3 109, S_0x2864a60; + .timescale -9 -12; +L_0x2aa7280/d .functor NOT 1, L_0x2a828d0, C4<0>, C4<0>, C4<0>; +L_0x2aa7280 .delay (10000,10000,10000) L_0x2aa7280/d; +L_0x2aa7360/d .functor AND 1, L_0x2aa77c0, L_0x2aa7280, C4<1>, C4<1>; +L_0x2aa7360 .delay (20000,20000,20000) L_0x2aa7360/d; +L_0x2aa7470/d .functor AND 1, L_0x2a828d0, L_0x2a828d0, C4<1>, C4<1>; +L_0x2aa7470 .delay (20000,20000,20000) L_0x2aa7470/d; +L_0x2aa75e0/d .functor OR 1, L_0x2aa7360, L_0x2aa7470, C4<0>, C4<0>; +L_0x2aa75e0 .delay (20000,20000,20000) L_0x2aa75e0/d; +v0x289d500_0 .alias "S", 0 0, v0x29604c0_0; +v0x289d5c0_0 .net "in0", 0 0, L_0x2aa77c0; 1 drivers +v0x289d660_0 .alias "in1", 0 0, v0x29604c0_0; +v0x289d710_0 .net "nS", 0 0, L_0x2aa7280; 1 drivers +v0x289d7c0_0 .net "out0", 0 0, L_0x2aa7360; 1 drivers +v0x289d840_0 .net "out1", 0 0, L_0x2aa7470; 1 drivers +v0x289d8e0_0 .net "outfinal", 0 0, L_0x2aa75e0; 1 drivers +S_0x289b790 .scope generate, "sltbits[1]" "sltbits[1]" 3 332, 3 332, S_0x2864a60; + .timescale -9 -12; +P_0x289b1a8 .param/l "i" 3 332, +C4<01>; +S_0x289c3f0 .scope module, "attempt" "MiddleAddSubSLT" 3 334, 3 189, S_0x289b790; + .timescale -9 -12; +L_0x2a5e410/d .functor NOT 1, L_0x2a5fe70, C4<0>, C4<0>, C4<0>; +L_0x2a5e410 .delay (10000,10000,10000) L_0x2a5e410/d; +L_0x2a5ea50/d .functor NOT 1, L_0x2a5eaf0, C4<0>, C4<0>, C4<0>; +L_0x2a5ea50 .delay (10000,10000,10000) L_0x2a5ea50/d; +L_0x2a5eb90/d .functor AND 1, L_0x2a5ecd0, L_0x2a5ea50, C4<1>, C4<1>; +L_0x2a5eb90 .delay (20000,20000,20000) L_0x2a5eb90/d; +L_0x2a5ed70/d .functor XOR 1, L_0x2a5fdd0, L_0x2a5e820, C4<0>, C4<0>; +L_0x2a5ed70 .delay (40000,40000,40000) L_0x2a5ed70/d; +L_0x2a5ee60/d .functor XOR 1, L_0x2a5ed70, L_0x2a5ffa0, C4<0>, C4<0>; +L_0x2a5ee60 .delay (40000,40000,40000) L_0x2a5ee60/d; +L_0x2a5ef50/d .functor AND 1, L_0x2a5fdd0, L_0x2a5e820, C4<1>, C4<1>; +L_0x2a5ef50 .delay (20000,20000,20000) L_0x2a5ef50/d; +L_0x2a5f8d0/d .functor AND 1, L_0x2a5ed70, L_0x2a5ffa0, C4<1>, C4<1>; +L_0x2a5f8d0 .delay (20000,20000,20000) L_0x2a5f8d0/d; +L_0x2a5f9c0/d .functor OR 1, L_0x2a5ef50, L_0x2a5f8d0, C4<0>, C4<0>; +L_0x2a5f9c0 .delay (20000,20000,20000) L_0x2a5f9c0/d; +v0x289ca70_0 .net "A", 0 0, L_0x2a5fdd0; 1 drivers +v0x289cb30_0 .net "AandB", 0 0, L_0x2a5ef50; 1 drivers +v0x289cbd0_0 .net "AddSubSLTSum", 0 0, L_0x2a5ee60; 1 drivers +v0x289cc70_0 .net "AxorB", 0 0, L_0x2a5ed70; 1 drivers +v0x289ccf0_0 .net "B", 0 0, L_0x2a5fe70; 1 drivers +v0x289cda0_0 .net "BornB", 0 0, L_0x2a5e820; 1 drivers +v0x289ce60_0 .net "CINandAxorB", 0 0, L_0x2a5f8d0; 1 drivers +v0x289cee0_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x289cf60_0 .net *"_s3", 0 0, L_0x2a5eaf0; 1 drivers +v0x289cfe0_0 .net *"_s5", 0 0, L_0x2a5ecd0; 1 drivers +v0x289d080_0 .net "carryin", 0 0, L_0x2a5ffa0; 1 drivers +v0x289d120_0 .net "carryout", 0 0, L_0x2a5f9c0; 1 drivers +v0x289d1c0_0 .net "nB", 0 0, L_0x2a5e410; 1 drivers +v0x289d270_0 .net "nCmd2", 0 0, L_0x2a5ea50; 1 drivers +v0x289d370_0 .net "subtract", 0 0, L_0x2a5eb90; 1 drivers +L_0x2a5e9b0 .part v0x2960210_0, 0, 1; +L_0x2a5eaf0 .part v0x2960210_0, 2, 1; +L_0x2a5ecd0 .part v0x2960210_0, 0, 1; +S_0x289c4e0 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x289c3f0; + .timescale -9 -12; +L_0x2a5e5a0/d .functor NOT 1, L_0x2a5e9b0, C4<0>, C4<0>, C4<0>; +L_0x2a5e5a0 .delay (10000,10000,10000) L_0x2a5e5a0/d; +L_0x2a5e640/d .functor AND 1, L_0x2a5fe70, L_0x2a5e5a0, C4<1>, C4<1>; +L_0x2a5e640 .delay (20000,20000,20000) L_0x2a5e640/d; +L_0x2a5e730/d .functor AND 1, L_0x2a5e410, L_0x2a5e9b0, C4<1>, C4<1>; +L_0x2a5e730 .delay (20000,20000,20000) L_0x2a5e730/d; +L_0x2a5e820/d .functor OR 1, L_0x2a5e640, L_0x2a5e730, C4<0>, C4<0>; +L_0x2a5e820 .delay (20000,20000,20000) L_0x2a5e820/d; +v0x289c5d0_0 .net "S", 0 0, L_0x2a5e9b0; 1 drivers +v0x289c690_0 .alias "in0", 0 0, v0x289ccf0_0; +v0x289c730_0 .alias "in1", 0 0, v0x289d1c0_0; +v0x289c7d0_0 .net "nS", 0 0, L_0x2a5e5a0; 1 drivers +v0x289c850_0 .net "out0", 0 0, L_0x2a5e640; 1 drivers +v0x289c8f0_0 .net "out1", 0 0, L_0x2a5e730; 1 drivers +v0x289c9d0_0 .alias "outfinal", 0 0, v0x289cda0_0; +S_0x289be80 .scope module, "setSLTres2" "TwoInMux" 3 335, 3 109, S_0x289b790; + .timescale -9 -12; +L_0x2a60040/d .functor NOT 1, L_0x2aa3020, C4<0>, C4<0>, C4<0>; +L_0x2a60040 .delay (10000,10000,10000) L_0x2a60040/d; +L_0x2a60940/d .functor AND 1, L_0x2881a30, L_0x2a60040, C4<1>, C4<1>; +L_0x2a60940 .delay (20000,20000,20000) L_0x2a60940/d; +L_0x2a60a30/d .functor AND 1, C4<0>, L_0x2aa3020, C4<1>, C4<1>; +L_0x2a60a30 .delay (20000,20000,20000) L_0x2a60a30/d; +L_0x2a60ad0/d .functor OR 1, L_0x2a60940, L_0x2a60a30, C4<0>, C4<0>; +L_0x2a60ad0 .delay (20000,20000,20000) L_0x2a60ad0/d; +v0x289bf70_0 .alias "S", 0 0, v0x289f760_0; +v0x289c010_0 .net "in0", 0 0, L_0x2881a30; 1 drivers +v0x289c0b0_0 .net "in1", 0 0, C4<0>; 1 drivers +v0x289c150_0 .net "nS", 0 0, L_0x2a60040; 1 drivers +v0x289c1d0_0 .net "out0", 0 0, L_0x2a60940; 1 drivers +v0x289c270_0 .net "out1", 0 0, L_0x2a60a30; 1 drivers +v0x289c350_0 .net "outfinal", 0 0, L_0x2a60ad0; 1 drivers +S_0x289b900 .scope module, "setSLTres3" "TwoInMux" 3 336, 3 109, S_0x289b790; + .timescale -9 -12; +L_0x2a60bc0/d .functor NOT 1, L_0x2aa3020, C4<0>, C4<0>, C4<0>; +L_0x2a60bc0 .delay (10000,10000,10000) L_0x2a60bc0/d; +L_0x2881ca0/d .functor AND 1, L_0x2a63360, L_0x2a60bc0, C4<1>, C4<1>; +L_0x2881ca0 .delay (20000,20000,20000) L_0x2881ca0/d; +L_0x2a630e0/d .functor AND 1, L_0x2a63500, L_0x2aa3020, C4<1>, C4<1>; +L_0x2a630e0 .delay (20000,20000,20000) L_0x2a630e0/d; +L_0x2a63180/d .functor OR 1, L_0x2881ca0, L_0x2a630e0, C4<0>, C4<0>; +L_0x2a63180 .delay (20000,20000,20000) L_0x2a63180/d; +v0x289b9f0_0 .alias "S", 0 0, v0x289f760_0; +v0x289ba70_0 .net "in0", 0 0, L_0x2a63360; 1 drivers +v0x289bb10_0 .net "in1", 0 0, L_0x2a63500; 1 drivers +v0x289bbb0_0 .net "nS", 0 0, L_0x2a60bc0; 1 drivers +v0x289bc60_0 .net "out0", 0 0, L_0x2881ca0; 1 drivers +v0x289bd00_0 .net "out1", 0 0, L_0x2a630e0; 1 drivers +v0x289bde0_0 .net "outfinal", 0 0, L_0x2a63180; 1 drivers +S_0x2899b10 .scope generate, "sltbits[2]" "sltbits[2]" 3 332, 3 332, S_0x2864a60; + .timescale -9 -12; +P_0x2899528 .param/l "i" 3 332, +C4<010>; +S_0x289a770 .scope module, "attempt" "MiddleAddSubSLT" 3 334, 3 189, S_0x2899b10; + .timescale -9 -12; +L_0x2a635a0/d .functor NOT 1, L_0x2a648e0, C4<0>, C4<0>, C4<0>; +L_0x2a635a0 .delay (10000,10000,10000) L_0x2a635a0/d; +L_0x2a63be0/d .functor NOT 1, L_0x2a63c80, C4<0>, C4<0>, C4<0>; +L_0x2a63be0 .delay (10000,10000,10000) L_0x2a63be0/d; +L_0x2a63d20/d .functor AND 1, L_0x2a63e60, L_0x2a63be0, C4<1>, C4<1>; +L_0x2a63d20 .delay (20000,20000,20000) L_0x2a63d20/d; +L_0x2a63f00/d .functor XOR 1, L_0x2a64840, L_0x2a639b0, C4<0>, C4<0>; +L_0x2a63f00 .delay (40000,40000,40000) L_0x2a63f00/d; +L_0x2a63ff0/d .functor XOR 1, L_0x2a63f00, L_0x2a64aa0, C4<0>, C4<0>; +L_0x2a63ff0 .delay (40000,40000,40000) L_0x2a63ff0/d; +L_0x2a640e0/d .functor AND 1, L_0x2a64840, L_0x2a639b0, C4<1>, C4<1>; +L_0x2a640e0 .delay (20000,20000,20000) L_0x2a640e0/d; +L_0x2a64250/d .functor AND 1, L_0x2a63f00, L_0x2a64aa0, C4<1>, C4<1>; +L_0x2a64250 .delay (20000,20000,20000) L_0x2a64250/d; +L_0x2a64340/d .functor OR 1, L_0x2a640e0, L_0x2a64250, C4<0>, C4<0>; +L_0x2a64340 .delay (20000,20000,20000) L_0x2a64340/d; +v0x289adf0_0 .net "A", 0 0, L_0x2a64840; 1 drivers +v0x289aeb0_0 .net "AandB", 0 0, L_0x2a640e0; 1 drivers +v0x289af50_0 .net "AddSubSLTSum", 0 0, L_0x2a63ff0; 1 drivers +v0x289aff0_0 .net "AxorB", 0 0, L_0x2a63f00; 1 drivers +v0x289b070_0 .net "B", 0 0, L_0x2a648e0; 1 drivers +v0x289b120_0 .net "BornB", 0 0, L_0x2a639b0; 1 drivers +v0x289b1e0_0 .net "CINandAxorB", 0 0, L_0x2a64250; 1 drivers +v0x289b260_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x289b2e0_0 .net *"_s3", 0 0, L_0x2a63c80; 1 drivers +v0x289b360_0 .net *"_s5", 0 0, L_0x2a63e60; 1 drivers +v0x289b400_0 .net "carryin", 0 0, L_0x2a64aa0; 1 drivers +v0x289b4a0_0 .net "carryout", 0 0, L_0x2a64340; 1 drivers +v0x289b540_0 .net "nB", 0 0, L_0x2a635a0; 1 drivers +v0x289b5f0_0 .net "nCmd2", 0 0, L_0x2a63be0; 1 drivers +v0x289b6f0_0 .net "subtract", 0 0, L_0x2a63d20; 1 drivers +L_0x2a63b40 .part v0x2960210_0, 0, 1; +L_0x2a63c80 .part v0x2960210_0, 2, 1; +L_0x2a63e60 .part v0x2960210_0, 0, 1; +S_0x289a860 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x289a770; + .timescale -9 -12; +L_0x2a63730/d .functor NOT 1, L_0x2a63b40, C4<0>, C4<0>, C4<0>; +L_0x2a63730 .delay (10000,10000,10000) L_0x2a63730/d; +L_0x2a637d0/d .functor AND 1, L_0x2a648e0, L_0x2a63730, C4<1>, C4<1>; +L_0x2a637d0 .delay (20000,20000,20000) L_0x2a637d0/d; +L_0x2a638c0/d .functor AND 1, L_0x2a635a0, L_0x2a63b40, C4<1>, C4<1>; +L_0x2a638c0 .delay (20000,20000,20000) L_0x2a638c0/d; +L_0x2a639b0/d .functor OR 1, L_0x2a637d0, L_0x2a638c0, C4<0>, C4<0>; +L_0x2a639b0 .delay (20000,20000,20000) L_0x2a639b0/d; +v0x289a950_0 .net "S", 0 0, L_0x2a63b40; 1 drivers +v0x289aa10_0 .alias "in0", 0 0, v0x289b070_0; +v0x289aab0_0 .alias "in1", 0 0, v0x289b540_0; +v0x289ab50_0 .net "nS", 0 0, L_0x2a63730; 1 drivers +v0x289abd0_0 .net "out0", 0 0, L_0x2a637d0; 1 drivers +v0x289ac70_0 .net "out1", 0 0, L_0x2a638c0; 1 drivers +v0x289ad50_0 .alias "outfinal", 0 0, v0x289b120_0; +S_0x289a200 .scope module, "setSLTres2" "TwoInMux" 3 335, 3 109, S_0x2899b10; + .timescale -9 -12; +L_0x2a634a0/d .functor NOT 1, L_0x2aa3020, C4<0>, C4<0>, C4<0>; +L_0x2a634a0 .delay (10000,10000,10000) L_0x2a634a0/d; +L_0x2a64bd0/d .functor AND 1, L_0x2a65020, L_0x2a634a0, C4<1>, C4<1>; +L_0x2a64bd0 .delay (20000,20000,20000) L_0x2a64bd0/d; +L_0x2a64c70/d .functor AND 1, C4<0>, L_0x2aa3020, C4<1>, C4<1>; +L_0x2a64c70 .delay (20000,20000,20000) L_0x2a64c70/d; +L_0x2a64d10/d .functor OR 1, L_0x2a64bd0, L_0x2a64c70, C4<0>, C4<0>; +L_0x2a64d10 .delay (20000,20000,20000) L_0x2a64d10/d; +v0x289a2f0_0 .alias "S", 0 0, v0x289f760_0; +v0x289a390_0 .net "in0", 0 0, L_0x2a65020; 1 drivers +v0x289a430_0 .net "in1", 0 0, C4<0>; 1 drivers +v0x289a4d0_0 .net "nS", 0 0, L_0x2a634a0; 1 drivers +v0x289a550_0 .net "out0", 0 0, L_0x2a64bd0; 1 drivers +v0x289a5f0_0 .net "out1", 0 0, L_0x2a64c70; 1 drivers +v0x289a6d0_0 .net "outfinal", 0 0, L_0x2a64d10; 1 drivers +S_0x2899c80 .scope module, "setSLTres3" "TwoInMux" 3 336, 3 109, S_0x2899b10; + .timescale -9 -12; +L_0x29d4300/d .functor NOT 1, L_0x2aa3020, C4<0>, C4<0>, C4<0>; +L_0x29d4300 .delay (10000,10000,10000) L_0x29d4300/d; +L_0x2a65230/d .functor AND 1, L_0x2a64f80, L_0x29d4300, C4<1>, C4<1>; +L_0x2a65230 .delay (20000,20000,20000) L_0x2a65230/d; +L_0x2a65320/d .functor AND 1, L_0x2a656a0, L_0x2aa3020, C4<1>, C4<1>; +L_0x2a65320 .delay (20000,20000,20000) L_0x2a65320/d; +L_0x2a653c0/d .functor OR 1, L_0x2a65230, L_0x2a65320, C4<0>, C4<0>; +L_0x2a653c0 .delay (20000,20000,20000) L_0x2a653c0/d; +v0x2899d70_0 .alias "S", 0 0, v0x289f760_0; +v0x2899df0_0 .net "in0", 0 0, L_0x2a64f80; 1 drivers +v0x2899e90_0 .net "in1", 0 0, L_0x2a656a0; 1 drivers +v0x2899f30_0 .net "nS", 0 0, L_0x29d4300; 1 drivers +v0x2899fe0_0 .net "out0", 0 0, L_0x2a65230; 1 drivers +v0x289a080_0 .net "out1", 0 0, L_0x2a65320; 1 drivers +v0x289a160_0 .net "outfinal", 0 0, L_0x2a653c0; 1 drivers +S_0x2897e90 .scope generate, "sltbits[3]" "sltbits[3]" 3 332, 3 332, S_0x2864a60; + .timescale -9 -12; +P_0x28978a8 .param/l "i" 3 332, +C4<011>; +S_0x2898af0 .scope module, "attempt" "MiddleAddSubSLT" 3 334, 3 189, S_0x2897e90; + .timescale -9 -12; +L_0x2a655a0/d .functor NOT 1, L_0x2a66860, C4<0>, C4<0>, C4<0>; +L_0x2a655a0 .delay (10000,10000,10000) L_0x2a655a0/d; +L_0x2a65de0/d .functor NOT 1, L_0x2a65e80, C4<0>, C4<0>, C4<0>; +L_0x2a65de0 .delay (10000,10000,10000) L_0x2a65de0/d; +L_0x2a65f20/d .functor AND 1, L_0x2a66060, L_0x2a65de0, C4<1>, C4<1>; +L_0x2a65f20 .delay (20000,20000,20000) L_0x2a65f20/d; +L_0x2a66100/d .functor XOR 1, L_0x2a66980, L_0x2a65bb0, C4<0>, C4<0>; +L_0x2a66100 .delay (40000,40000,40000) L_0x2a66100/d; +L_0x2a661f0/d .functor XOR 1, L_0x2a66100, L_0x2a66b90, C4<0>, C4<0>; +L_0x2a661f0 .delay (40000,40000,40000) L_0x2a661f0/d; +L_0x2a662e0/d .functor AND 1, L_0x2a66980, L_0x2a65bb0, C4<1>, C4<1>; +L_0x2a662e0 .delay (20000,20000,20000) L_0x2a662e0/d; +L_0x2a66450/d .functor AND 1, L_0x2a66100, L_0x2a66b90, C4<1>, C4<1>; +L_0x2a66450 .delay (20000,20000,20000) L_0x2a66450/d; +L_0x2a66540/d .functor OR 1, L_0x2a662e0, L_0x2a66450, C4<0>, C4<0>; +L_0x2a66540 .delay (20000,20000,20000) L_0x2a66540/d; +v0x2899170_0 .net "A", 0 0, L_0x2a66980; 1 drivers +v0x2899230_0 .net "AandB", 0 0, L_0x2a662e0; 1 drivers +v0x28992d0_0 .net "AddSubSLTSum", 0 0, L_0x2a661f0; 1 drivers +v0x2899370_0 .net "AxorB", 0 0, L_0x2a66100; 1 drivers +v0x28993f0_0 .net "B", 0 0, L_0x2a66860; 1 drivers +v0x28994a0_0 .net "BornB", 0 0, L_0x2a65bb0; 1 drivers +v0x2899560_0 .net "CINandAxorB", 0 0, L_0x2a66450; 1 drivers +v0x28995e0_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x2899660_0 .net *"_s3", 0 0, L_0x2a65e80; 1 drivers +v0x28996e0_0 .net *"_s5", 0 0, L_0x2a66060; 1 drivers +v0x2899780_0 .net "carryin", 0 0, L_0x2a66b90; 1 drivers +v0x2899820_0 .net "carryout", 0 0, L_0x2a66540; 1 drivers +v0x28998c0_0 .net "nB", 0 0, L_0x2a655a0; 1 drivers +v0x2899970_0 .net "nCmd2", 0 0, L_0x2a65de0; 1 drivers +v0x2899a70_0 .net "subtract", 0 0, L_0x2a65f20; 1 drivers +L_0x2a65d40 .part v0x2960210_0, 0, 1; +L_0x2a65e80 .part v0x2960210_0, 2, 1; +L_0x2a66060 .part v0x2960210_0, 0, 1; +S_0x2898be0 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x2898af0; + .timescale -9 -12; +L_0x2a65930/d .functor NOT 1, L_0x2a65d40, C4<0>, C4<0>, C4<0>; +L_0x2a65930 .delay (10000,10000,10000) L_0x2a65930/d; +L_0x2a659d0/d .functor AND 1, L_0x2a66860, L_0x2a65930, C4<1>, C4<1>; +L_0x2a659d0 .delay (20000,20000,20000) L_0x2a659d0/d; +L_0x2a65ac0/d .functor AND 1, L_0x2a655a0, L_0x2a65d40, C4<1>, C4<1>; +L_0x2a65ac0 .delay (20000,20000,20000) L_0x2a65ac0/d; +L_0x2a65bb0/d .functor OR 1, L_0x2a659d0, L_0x2a65ac0, C4<0>, C4<0>; +L_0x2a65bb0 .delay (20000,20000,20000) L_0x2a65bb0/d; +v0x2898cd0_0 .net "S", 0 0, L_0x2a65d40; 1 drivers +v0x2898d90_0 .alias "in0", 0 0, v0x28993f0_0; +v0x2898e30_0 .alias "in1", 0 0, v0x28998c0_0; +v0x2898ed0_0 .net "nS", 0 0, L_0x2a65930; 1 drivers +v0x2898f50_0 .net "out0", 0 0, L_0x2a659d0; 1 drivers +v0x2898ff0_0 .net "out1", 0 0, L_0x2a65ac0; 1 drivers +v0x28990d0_0 .alias "outfinal", 0 0, v0x28994a0_0; +S_0x2898580 .scope module, "setSLTres2" "TwoInMux" 3 335, 3 109, S_0x2897e90; + .timescale -9 -12; +L_0x2a66a20/d .functor NOT 1, L_0x2aa3020, C4<0>, C4<0>, C4<0>; +L_0x2a66a20 .delay (10000,10000,10000) L_0x2a66a20/d; +L_0x2a66aa0/d .functor AND 1, L_0x2a67030, L_0x2a66a20, C4<1>, C4<1>; +L_0x2a66aa0 .delay (20000,20000,20000) L_0x2a66aa0/d; +L_0x2a66db0/d .functor AND 1, C4<0>, L_0x2aa3020, C4<1>, C4<1>; +L_0x2a66db0 .delay (20000,20000,20000) L_0x2a66db0/d; +L_0x2a66e50/d .functor OR 1, L_0x2a66aa0, L_0x2a66db0, C4<0>, C4<0>; +L_0x2a66e50 .delay (20000,20000,20000) L_0x2a66e50/d; +v0x2898670_0 .alias "S", 0 0, v0x289f760_0; +v0x2898710_0 .net "in0", 0 0, L_0x2a67030; 1 drivers +v0x28987b0_0 .net "in1", 0 0, C4<0>; 1 drivers +v0x2898850_0 .net "nS", 0 0, L_0x2a66a20; 1 drivers +v0x28988d0_0 .net "out0", 0 0, L_0x2a66aa0; 1 drivers +v0x2898970_0 .net "out1", 0 0, L_0x2a66db0; 1 drivers +v0x2898a50_0 .net "outfinal", 0 0, L_0x2a66e50; 1 drivers +S_0x2898000 .scope module, "setSLTres3" "TwoInMux" 3 336, 3 109, S_0x2897e90; + .timescale -9 -12; +L_0x2a66cc0/d .functor NOT 1, L_0x2aa3020, C4<0>, C4<0>, C4<0>; +L_0x2a66cc0 .delay (10000,10000,10000) L_0x2a66cc0/d; +L_0x2a672b0/d .functor AND 1, L_0x2a67620, L_0x2a66cc0, C4<1>, C4<1>; +L_0x2a672b0 .delay (20000,20000,20000) L_0x2a672b0/d; +L_0x2a673a0/d .functor AND 1, L_0x2a67120, L_0x2aa3020, C4<1>, C4<1>; +L_0x2a673a0 .delay (20000,20000,20000) L_0x2a673a0/d; +L_0x2a67440/d .functor OR 1, L_0x2a672b0, L_0x2a673a0, C4<0>, C4<0>; +L_0x2a67440 .delay (20000,20000,20000) L_0x2a67440/d; +v0x28980f0_0 .alias "S", 0 0, v0x289f760_0; +v0x2898170_0 .net "in0", 0 0, L_0x2a67620; 1 drivers +v0x2898210_0 .net "in1", 0 0, L_0x2a67120; 1 drivers +v0x28982b0_0 .net "nS", 0 0, L_0x2a66cc0; 1 drivers +v0x2898360_0 .net "out0", 0 0, L_0x2a672b0; 1 drivers +v0x2898400_0 .net "out1", 0 0, L_0x2a673a0; 1 drivers +v0x28984e0_0 .net "outfinal", 0 0, L_0x2a67440; 1 drivers +S_0x2896210 .scope generate, "sltbits[4]" "sltbits[4]" 3 332, 3 332, S_0x2864a60; + .timescale -9 -12; +P_0x2895c28 .param/l "i" 3 332, +C4<0100>; +S_0x2896e70 .scope module, "attempt" "MiddleAddSubSLT" 3 334, 3 189, S_0x2896210; + .timescale -9 -12; +L_0x2a64ef0/d .functor NOT 1, L_0x2a68be0, C4<0>, C4<0>, C4<0>; +L_0x2a64ef0 .delay (10000,10000,10000) L_0x2a64ef0/d; +L_0x2a67f10/d .functor NOT 1, L_0x2a67fb0, C4<0>, C4<0>, C4<0>; +L_0x2a67f10 .delay (10000,10000,10000) L_0x2a67f10/d; +L_0x2a68050/d .functor AND 1, L_0x2a68190, L_0x2a67f10, C4<1>, C4<1>; +L_0x2a68050 .delay (20000,20000,20000) L_0x2a68050/d; +L_0x2a68230/d .functor XOR 1, L_0x2a688a0, L_0x2a67ce0, C4<0>, C4<0>; +L_0x2a68230 .delay (40000,40000,40000) L_0x2a68230/d; +L_0x2a68320/d .functor XOR 1, L_0x2a68230, L_0x2a68ab0, C4<0>, C4<0>; +L_0x2a68320 .delay (40000,40000,40000) L_0x2a68320/d; +L_0x2a68410/d .functor AND 1, L_0x2a688a0, L_0x2a67ce0, C4<1>, C4<1>; +L_0x2a68410 .delay (20000,20000,20000) L_0x2a68410/d; +L_0x2a68580/d .functor AND 1, L_0x2a68230, L_0x2a68ab0, C4<1>, C4<1>; +L_0x2a68580 .delay (20000,20000,20000) L_0x2a68580/d; +L_0x2a68670/d .functor OR 1, L_0x2a68410, L_0x2a68580, C4<0>, C4<0>; +L_0x2a68670 .delay (20000,20000,20000) L_0x2a68670/d; +v0x28974f0_0 .net "A", 0 0, L_0x2a688a0; 1 drivers +v0x28975b0_0 .net "AandB", 0 0, L_0x2a68410; 1 drivers +v0x2897650_0 .net "AddSubSLTSum", 0 0, L_0x2a68320; 1 drivers +v0x28976f0_0 .net "AxorB", 0 0, L_0x2a68230; 1 drivers +v0x2897770_0 .net "B", 0 0, L_0x2a68be0; 1 drivers +v0x2897820_0 .net "BornB", 0 0, L_0x2a67ce0; 1 drivers +v0x28978e0_0 .net "CINandAxorB", 0 0, L_0x2a68580; 1 drivers +v0x2897960_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x28979e0_0 .net *"_s3", 0 0, L_0x2a67fb0; 1 drivers +v0x2897a60_0 .net *"_s5", 0 0, L_0x2a68190; 1 drivers +v0x2897b00_0 .net "carryin", 0 0, L_0x2a68ab0; 1 drivers +v0x2897ba0_0 .net "carryout", 0 0, L_0x2a68670; 1 drivers +v0x2897c40_0 .net "nB", 0 0, L_0x2a64ef0; 1 drivers +v0x2897cf0_0 .net "nCmd2", 0 0, L_0x2a67f10; 1 drivers +v0x2897df0_0 .net "subtract", 0 0, L_0x2a68050; 1 drivers +L_0x2a67e70 .part v0x2960210_0, 0, 1; +L_0x2a67fb0 .part v0x2960210_0, 2, 1; +L_0x2a68190 .part v0x2960210_0, 0, 1; +S_0x2896f60 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x2896e70; + .timescale -9 -12; +L_0x2a67a60/d .functor NOT 1, L_0x2a67e70, C4<0>, C4<0>, C4<0>; +L_0x2a67a60 .delay (10000,10000,10000) L_0x2a67a60/d; +L_0x2a67b00/d .functor AND 1, L_0x2a68be0, L_0x2a67a60, C4<1>, C4<1>; +L_0x2a67b00 .delay (20000,20000,20000) L_0x2a67b00/d; +L_0x2a67bf0/d .functor AND 1, L_0x2a64ef0, L_0x2a67e70, C4<1>, C4<1>; +L_0x2a67bf0 .delay (20000,20000,20000) L_0x2a67bf0/d; +L_0x2a67ce0/d .functor OR 1, L_0x2a67b00, L_0x2a67bf0, C4<0>, C4<0>; +L_0x2a67ce0 .delay (20000,20000,20000) L_0x2a67ce0/d; +v0x2897050_0 .net "S", 0 0, L_0x2a67e70; 1 drivers +v0x2897110_0 .alias "in0", 0 0, v0x2897770_0; +v0x28971b0_0 .alias "in1", 0 0, v0x2897c40_0; +v0x2897250_0 .net "nS", 0 0, L_0x2a67a60; 1 drivers +v0x28972d0_0 .net "out0", 0 0, L_0x2a67b00; 1 drivers +v0x2897370_0 .net "out1", 0 0, L_0x2a67bf0; 1 drivers +v0x2897450_0 .alias "outfinal", 0 0, v0x2897820_0; +S_0x2896900 .scope module, "setSLTres2" "TwoInMux" 3 335, 3 109, S_0x2896210; + .timescale -9 -12; +L_0x2a68940/d .functor NOT 1, L_0x2aa3020, C4<0>, C4<0>, C4<0>; +L_0x2a68940 .delay (10000,10000,10000) L_0x2a68940/d; +L_0x2a68b50/d .functor AND 1, L_0x2a68d10, L_0x2a68940, C4<1>, C4<1>; +L_0x2a68b50 .delay (20000,20000,20000) L_0x2a68b50/d; +L_0x2a68f60/d .functor AND 1, C4<0>, L_0x2aa3020, C4<1>, C4<1>; +L_0x2a68f60 .delay (20000,20000,20000) L_0x2a68f60/d; +L_0x2a69000/d .functor OR 1, L_0x2a68b50, L_0x2a68f60, C4<0>, C4<0>; +L_0x2a69000 .delay (20000,20000,20000) L_0x2a69000/d; +v0x28969f0_0 .alias "S", 0 0, v0x289f760_0; +v0x2896a90_0 .net "in0", 0 0, L_0x2a68d10; 1 drivers +v0x2896b30_0 .net "in1", 0 0, C4<0>; 1 drivers +v0x2896bd0_0 .net "nS", 0 0, L_0x2a68940; 1 drivers +v0x2896c50_0 .net "out0", 0 0, L_0x2a68b50; 1 drivers +v0x2896cf0_0 .net "out1", 0 0, L_0x2a68f60; 1 drivers +v0x2896dd0_0 .net "outfinal", 0 0, L_0x2a69000; 1 drivers +S_0x2896380 .scope module, "setSLTres3" "TwoInMux" 3 336, 3 109, S_0x2896210; + .timescale -9 -12; +L_0x2a65100/d .functor NOT 1, L_0x2aa3020, C4<0>, C4<0>, C4<0>; +L_0x2a65100 .delay (10000,10000,10000) L_0x2a65100/d; +L_0x2a651d0/d .functor AND 1, L_0x2a691e0, L_0x2a65100, C4<1>, C4<1>; +L_0x2a651d0 .delay (20000,20000,20000) L_0x2a651d0/d; +L_0x2a69610/d .functor AND 1, L_0x2a699f0, L_0x2aa3020, C4<1>, C4<1>; +L_0x2a69610 .delay (20000,20000,20000) L_0x2a69610/d; +L_0x2a696b0/d .functor OR 1, L_0x2a651d0, L_0x2a69610, C4<0>, C4<0>; +L_0x2a696b0 .delay (20000,20000,20000) L_0x2a696b0/d; +v0x2896470_0 .alias "S", 0 0, v0x289f760_0; +v0x28964f0_0 .net "in0", 0 0, L_0x2a691e0; 1 drivers +v0x2896590_0 .net "in1", 0 0, L_0x2a699f0; 1 drivers +v0x2896630_0 .net "nS", 0 0, L_0x2a65100; 1 drivers +v0x28966e0_0 .net "out0", 0 0, L_0x2a651d0; 1 drivers +v0x2896780_0 .net "out1", 0 0, L_0x2a69610; 1 drivers +v0x2896860_0 .net "outfinal", 0 0, L_0x2a696b0; 1 drivers +S_0x2894590 .scope generate, "sltbits[5]" "sltbits[5]" 3 332, 3 332, S_0x2864a60; + .timescale -9 -12; +P_0x2893fa8 .param/l "i" 3 332, +C4<0101>; +S_0x28951f0 .scope module, "attempt" "MiddleAddSubSLT" 3 334, 3 189, S_0x2894590; + .timescale -9 -12; +L_0x2a69890/d .functor NOT 1, L_0x2a6ab80, C4<0>, C4<0>, C4<0>; +L_0x2a69890 .delay (10000,10000,10000) L_0x2a69890/d; +L_0x2a6a100/d .functor NOT 1, L_0x2a6a1a0, C4<0>, C4<0>, C4<0>; +L_0x2a6a100 .delay (10000,10000,10000) L_0x2a6a100/d; +L_0x2a6a240/d .functor AND 1, L_0x2a6a380, L_0x2a6a100, C4<1>, C4<1>; +L_0x2a6a240 .delay (20000,20000,20000) L_0x2a6a240/d; +L_0x2a6a420/d .functor XOR 1, L_0x2a6ad00, L_0x2a69ed0, C4<0>, C4<0>; +L_0x2a6a420 .delay (40000,40000,40000) L_0x2a6a420/d; +L_0x2a6a510/d .functor XOR 1, L_0x2a6a420, L_0x2a6af30, C4<0>, C4<0>; +L_0x2a6a510 .delay (40000,40000,40000) L_0x2a6a510/d; +L_0x2a6a600/d .functor AND 1, L_0x2a6ad00, L_0x2a69ed0, C4<1>, C4<1>; +L_0x2a6a600 .delay (20000,20000,20000) L_0x2a6a600/d; +L_0x2a6a770/d .functor AND 1, L_0x2a6a420, L_0x2a6af30, C4<1>, C4<1>; +L_0x2a6a770 .delay (20000,20000,20000) L_0x2a6a770/d; +L_0x2a6a860/d .functor OR 1, L_0x2a6a600, L_0x2a6a770, C4<0>, C4<0>; +L_0x2a6a860 .delay (20000,20000,20000) L_0x2a6a860/d; +v0x2895870_0 .net "A", 0 0, L_0x2a6ad00; 1 drivers +v0x2895930_0 .net "AandB", 0 0, L_0x2a6a600; 1 drivers +v0x28959d0_0 .net "AddSubSLTSum", 0 0, L_0x2a6a510; 1 drivers +v0x2895a70_0 .net "AxorB", 0 0, L_0x2a6a420; 1 drivers +v0x2895af0_0 .net "B", 0 0, L_0x2a6ab80; 1 drivers +v0x2895ba0_0 .net "BornB", 0 0, L_0x2a69ed0; 1 drivers +v0x2895c60_0 .net "CINandAxorB", 0 0, L_0x2a6a770; 1 drivers +v0x2895ce0_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x2895d60_0 .net *"_s3", 0 0, L_0x2a6a1a0; 1 drivers +v0x2895de0_0 .net *"_s5", 0 0, L_0x2a6a380; 1 drivers +v0x2895e80_0 .net "carryin", 0 0, L_0x2a6af30; 1 drivers +v0x2895f20_0 .net "carryout", 0 0, L_0x2a6a860; 1 drivers +v0x2895fc0_0 .net "nB", 0 0, L_0x2a69890; 1 drivers +v0x2896070_0 .net "nCmd2", 0 0, L_0x2a6a100; 1 drivers +v0x2896170_0 .net "subtract", 0 0, L_0x2a6a240; 1 drivers +L_0x2a6a060 .part v0x2960210_0, 0, 1; +L_0x2a6a1a0 .part v0x2960210_0, 2, 1; +L_0x2a6a380 .part v0x2960210_0, 0, 1; +S_0x28952e0 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x28951f0; + .timescale -9 -12; +L_0x2a69c50/d .functor NOT 1, L_0x2a6a060, C4<0>, C4<0>, C4<0>; +L_0x2a69c50 .delay (10000,10000,10000) L_0x2a69c50/d; +L_0x2a69cf0/d .functor AND 1, L_0x2a6ab80, L_0x2a69c50, C4<1>, C4<1>; +L_0x2a69cf0 .delay (20000,20000,20000) L_0x2a69cf0/d; +L_0x2a69de0/d .functor AND 1, L_0x2a69890, L_0x2a6a060, C4<1>, C4<1>; +L_0x2a69de0 .delay (20000,20000,20000) L_0x2a69de0/d; +L_0x2a69ed0/d .functor OR 1, L_0x2a69cf0, L_0x2a69de0, C4<0>, C4<0>; +L_0x2a69ed0 .delay (20000,20000,20000) L_0x2a69ed0/d; +v0x28953d0_0 .net "S", 0 0, L_0x2a6a060; 1 drivers +v0x2895490_0 .alias "in0", 0 0, v0x2895af0_0; +v0x2895530_0 .alias "in1", 0 0, v0x2895fc0_0; +v0x28955d0_0 .net "nS", 0 0, L_0x2a69c50; 1 drivers +v0x2895650_0 .net "out0", 0 0, L_0x2a69cf0; 1 drivers +v0x28956f0_0 .net "out1", 0 0, L_0x2a69de0; 1 drivers +v0x28957d0_0 .alias "outfinal", 0 0, v0x2895ba0_0; +S_0x2894c80 .scope module, "setSLTres2" "TwoInMux" 3 335, 3 109, S_0x2894590; + .timescale -9 -12; +L_0x2a69b80/d .functor NOT 1, L_0x2aa3020, C4<0>, C4<0>, C4<0>; +L_0x2a69b80 .delay (10000,10000,10000) L_0x2a69b80/d; +L_0x2a6ada0/d .functor AND 1, L_0x2a6b350, L_0x2a69b80, C4<1>, C4<1>; +L_0x2a6ada0 .delay (20000,20000,20000) L_0x2a6ada0/d; +L_0x2a6ae60/d .functor AND 1, C4<0>, L_0x2aa3020, C4<1>, C4<1>; +L_0x2a6ae60 .delay (20000,20000,20000) L_0x2a6ae60/d; +L_0x2a6b170/d .functor OR 1, L_0x2a6ada0, L_0x2a6ae60, C4<0>, C4<0>; +L_0x2a6b170 .delay (20000,20000,20000) L_0x2a6b170/d; +v0x2894d70_0 .alias "S", 0 0, v0x289f760_0; +v0x2894e10_0 .net "in0", 0 0, L_0x2a6b350; 1 drivers +v0x2894eb0_0 .net "in1", 0 0, C4<0>; 1 drivers +v0x2894f50_0 .net "nS", 0 0, L_0x2a69b80; 1 drivers +v0x2894fd0_0 .net "out0", 0 0, L_0x2a6ada0; 1 drivers +v0x2895070_0 .net "out1", 0 0, L_0x2a6ae60; 1 drivers +v0x2895150_0 .net "outfinal", 0 0, L_0x2a6b170; 1 drivers +S_0x2894700 .scope module, "setSLTres3" "TwoInMux" 3 336, 3 109, S_0x2894590; + .timescale -9 -12; +L_0x2a6b060/d .functor NOT 1, L_0x2aa3020, C4<0>, C4<0>, C4<0>; +L_0x2a6b060 .delay (10000,10000,10000) L_0x2a6b060/d; +L_0x2a6b5f0/d .functor AND 1, L_0x2a6b960, L_0x2a6b060, C4<1>, C4<1>; +L_0x2a6b5f0 .delay (20000,20000,20000) L_0x2a6b5f0/d; +L_0x2a6b6e0/d .functor AND 1, L_0x2a6b440, L_0x2aa3020, C4<1>, C4<1>; +L_0x2a6b6e0 .delay (20000,20000,20000) L_0x2a6b6e0/d; +L_0x2a6b780/d .functor OR 1, L_0x2a6b5f0, L_0x2a6b6e0, C4<0>, C4<0>; +L_0x2a6b780 .delay (20000,20000,20000) L_0x2a6b780/d; +v0x28947f0_0 .alias "S", 0 0, v0x289f760_0; +v0x2894870_0 .net "in0", 0 0, L_0x2a6b960; 1 drivers +v0x2894910_0 .net "in1", 0 0, L_0x2a6b440; 1 drivers +v0x28949b0_0 .net "nS", 0 0, L_0x2a6b060; 1 drivers +v0x2894a60_0 .net "out0", 0 0, L_0x2a6b5f0; 1 drivers +v0x2894b00_0 .net "out1", 0 0, L_0x2a6b6e0; 1 drivers +v0x2894be0_0 .net "outfinal", 0 0, L_0x2a6b780; 1 drivers +S_0x27f2140 .scope generate, "sltbits[6]" "sltbits[6]" 3 332, 3 332, S_0x2864a60; + .timescale -9 -12; +P_0x2891328 .param/l "i" 3 332, +C4<0110>; +S_0x2893570 .scope module, "attempt" "MiddleAddSubSLT" 3 334, 3 189, S_0x27f2140; + .timescale -9 -12; +L_0x2a6b530/d .functor NOT 1, L_0x2a6cbe0, C4<0>, C4<0>, C4<0>; +L_0x2a6b530 .delay (10000,10000,10000) L_0x2a6b530/d; +L_0x2a6c1b0/d .functor NOT 1, L_0x2a6c250, C4<0>, C4<0>, C4<0>; +L_0x2a6c1b0 .delay (10000,10000,10000) L_0x2a6c1b0/d; +L_0x2a6c2f0/d .functor AND 1, L_0x2a6c430, L_0x2a6c1b0, C4<1>, C4<1>; +L_0x2a6c2f0 .delay (20000,20000,20000) L_0x2a6c2f0/d; +L_0x2a6c4d0/d .functor XOR 1, L_0x2a6cb40, L_0x2a6bf80, C4<0>, C4<0>; +L_0x2a6c4d0 .delay (40000,40000,40000) L_0x2a6c4d0/d; +L_0x2a6c5c0/d .functor XOR 1, L_0x2a6c4d0, L_0x2a6cf50, C4<0>, C4<0>; +L_0x2a6c5c0 .delay (40000,40000,40000) L_0x2a6c5c0/d; +L_0x2a6c6b0/d .functor AND 1, L_0x2a6cb40, L_0x2a6bf80, C4<1>, C4<1>; +L_0x2a6c6b0 .delay (20000,20000,20000) L_0x2a6c6b0/d; +L_0x2a6c820/d .functor AND 1, L_0x2a6c4d0, L_0x2a6cf50, C4<1>, C4<1>; +L_0x2a6c820 .delay (20000,20000,20000) L_0x2a6c820/d; +L_0x2a6c910/d .functor OR 1, L_0x2a6c6b0, L_0x2a6c820, C4<0>, C4<0>; +L_0x2a6c910 .delay (20000,20000,20000) L_0x2a6c910/d; +v0x2893bf0_0 .net "A", 0 0, L_0x2a6cb40; 1 drivers +v0x2893cb0_0 .net "AandB", 0 0, L_0x2a6c6b0; 1 drivers +v0x2893d50_0 .net "AddSubSLTSum", 0 0, L_0x2a6c5c0; 1 drivers +v0x2893df0_0 .net "AxorB", 0 0, L_0x2a6c4d0; 1 drivers +v0x2893e70_0 .net "B", 0 0, L_0x2a6cbe0; 1 drivers +v0x2893f20_0 .net "BornB", 0 0, L_0x2a6bf80; 1 drivers +v0x2893fe0_0 .net "CINandAxorB", 0 0, L_0x2a6c820; 1 drivers +v0x2894060_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x28940e0_0 .net *"_s3", 0 0, L_0x2a6c250; 1 drivers +v0x2894160_0 .net *"_s5", 0 0, L_0x2a6c430; 1 drivers +v0x2894200_0 .net "carryin", 0 0, L_0x2a6cf50; 1 drivers +v0x28942a0_0 .net "carryout", 0 0, L_0x2a6c910; 1 drivers +v0x2894340_0 .net "nB", 0 0, L_0x2a6b530; 1 drivers +v0x28943f0_0 .net "nCmd2", 0 0, L_0x2a6c1b0; 1 drivers +v0x28944f0_0 .net "subtract", 0 0, L_0x2a6c2f0; 1 drivers +L_0x2a6c110 .part v0x2960210_0, 0, 1; +L_0x2a6c250 .part v0x2960210_0, 2, 1; +L_0x2a6c430 .part v0x2960210_0, 0, 1; +S_0x2893660 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x2893570; + .timescale -9 -12; +L_0x2a6bd00/d .functor NOT 1, L_0x2a6c110, C4<0>, C4<0>, C4<0>; +L_0x2a6bd00 .delay (10000,10000,10000) L_0x2a6bd00/d; +L_0x2a6bda0/d .functor AND 1, L_0x2a6cbe0, L_0x2a6bd00, C4<1>, C4<1>; +L_0x2a6bda0 .delay (20000,20000,20000) L_0x2a6bda0/d; +L_0x2a6be90/d .functor AND 1, L_0x2a6b530, L_0x2a6c110, C4<1>, C4<1>; +L_0x2a6be90 .delay (20000,20000,20000) L_0x2a6be90/d; +L_0x2a6bf80/d .functor OR 1, L_0x2a6bda0, L_0x2a6be90, C4<0>, C4<0>; +L_0x2a6bf80 .delay (20000,20000,20000) L_0x2a6bf80/d; +v0x2893750_0 .net "S", 0 0, L_0x2a6c110; 1 drivers +v0x2893810_0 .alias "in0", 0 0, v0x2893e70_0; +v0x28938b0_0 .alias "in1", 0 0, v0x2894340_0; +v0x2893950_0 .net "nS", 0 0, L_0x2a6bd00; 1 drivers +v0x28939d0_0 .net "out0", 0 0, L_0x2a6bda0; 1 drivers +v0x2893a70_0 .net "out1", 0 0, L_0x2a6be90; 1 drivers +v0x2893b50_0 .alias "outfinal", 0 0, v0x2893f20_0; +S_0x27f2830 .scope module, "setSLTres2" "TwoInMux" 3 335, 3 109, S_0x27f2140; + .timescale -9 -12; +L_0x2a6cff0/d .functor NOT 1, L_0x2aa3020, C4<0>, C4<0>, C4<0>; +L_0x2a6cff0 .delay (10000,10000,10000) L_0x2a6cff0/d; +L_0x2a6d050/d .functor AND 1, L_0x2a67710, L_0x2a6cff0, C4<1>, C4<1>; +L_0x2a6d050 .delay (20000,20000,20000) L_0x2a6d050/d; +L_0x2a6d140/d .functor AND 1, C4<0>, L_0x2aa3020, C4<1>, C4<1>; +L_0x2a6d140 .delay (20000,20000,20000) L_0x2a6d140/d; +L_0x2a6d1e0/d .functor OR 1, L_0x2a6d050, L_0x2a6d140, C4<0>, C4<0>; +L_0x2a6d1e0 .delay (20000,20000,20000) L_0x2a6d1e0/d; +v0x27f2920_0 .alias "S", 0 0, v0x289f760_0; +v0x27f29c0_0 .net "in0", 0 0, L_0x2a67710; 1 drivers +v0x27f2a60_0 .net "in1", 0 0, C4<0>; 1 drivers +v0x27f2b00_0 .net "nS", 0 0, L_0x2a6cff0; 1 drivers +v0x27f2b80_0 .net "out0", 0 0, L_0x2a6d050; 1 drivers +v0x27f2c20_0 .net "out1", 0 0, L_0x2a6d140; 1 drivers +v0x28934d0_0 .net "outfinal", 0 0, L_0x2a6d1e0; 1 drivers +S_0x27f22b0 .scope module, "setSLTres3" "TwoInMux" 3 336, 3 109, S_0x27f2140; + .timescale -9 -12; +L_0x2a69440/d .functor NOT 1, L_0x2aa3020, C4<0>, C4<0>, C4<0>; +L_0x2a69440 .delay (10000,10000,10000) L_0x2a69440/d; +L_0x2a6d7d0/d .functor AND 1, L_0x2a6d5d0, L_0x2a69440, C4<1>, C4<1>; +L_0x2a6d7d0 .delay (20000,20000,20000) L_0x2a6d7d0/d; +L_0x2a6d8c0/d .functor AND 1, L_0x2a6d6c0, L_0x2aa3020, C4<1>, C4<1>; +L_0x2a6d8c0 .delay (20000,20000,20000) L_0x2a6d8c0/d; +L_0x2a6d960/d .functor OR 1, L_0x2a6d7d0, L_0x2a6d8c0, C4<0>, C4<0>; +L_0x2a6d960 .delay (20000,20000,20000) L_0x2a6d960/d; +v0x27f23a0_0 .alias "S", 0 0, v0x289f760_0; +v0x27f2420_0 .net "in0", 0 0, L_0x2a6d5d0; 1 drivers +v0x27f24c0_0 .net "in1", 0 0, L_0x2a6d6c0; 1 drivers +v0x27f2560_0 .net "nS", 0 0, L_0x2a69440; 1 drivers +v0x27f2610_0 .net "out0", 0 0, L_0x2a6d7d0; 1 drivers +v0x27f26b0_0 .net "out1", 0 0, L_0x2a6d8c0; 1 drivers +v0x27f2790_0 .net "outfinal", 0 0, L_0x2a6d960; 1 drivers +S_0x288fc90 .scope generate, "sltbits[7]" "sltbits[7]" 3 332, 3 332, S_0x2864a60; + .timescale -9 -12; +P_0x288f6a8 .param/l "i" 3 332, +C4<0111>; +S_0x28908f0 .scope module, "attempt" "MiddleAddSubSLT" 3 334, 3 189, S_0x288fc90; + .timescale -9 -12; +L_0x2a6dd60/d .functor NOT 1, L_0x2a6f060, C4<0>, C4<0>, C4<0>; +L_0x2a6dd60 .delay (10000,10000,10000) L_0x2a6dd60/d; +L_0x2a6e3a0/d .functor NOT 1, L_0x2a6e440, C4<0>, C4<0>, C4<0>; +L_0x2a6e3a0 .delay (10000,10000,10000) L_0x2a6e3a0/d; +L_0x2a6e4e0/d .functor AND 1, L_0x2a6e620, L_0x2a6e3a0, C4<1>, C4<1>; +L_0x2a6e4e0 .delay (20000,20000,20000) L_0x2a6e4e0/d; +L_0x2a6e6c0/d .functor XOR 1, L_0x2a6dc30, L_0x2a6e170, C4<0>, C4<0>; +L_0x2a6e6c0 .delay (40000,40000,40000) L_0x2a6e6c0/d; +L_0x2a6e7b0/d .functor XOR 1, L_0x2a6e6c0, L_0x2a6f100, C4<0>, C4<0>; +L_0x2a6e7b0 .delay (40000,40000,40000) L_0x2a6e7b0/d; +L_0x2a6e8a0/d .functor AND 1, L_0x2a6dc30, L_0x2a6e170, C4<1>, C4<1>; +L_0x2a6e8a0 .delay (20000,20000,20000) L_0x2a6e8a0/d; +L_0x2a6ea10/d .functor AND 1, L_0x2a6e6c0, L_0x2a6f100, C4<1>, C4<1>; +L_0x2a6ea10 .delay (20000,20000,20000) L_0x2a6ea10/d; +L_0x2a6eb00/d .functor OR 1, L_0x2a6e8a0, L_0x2a6ea10, C4<0>, C4<0>; +L_0x2a6eb00 .delay (20000,20000,20000) L_0x2a6eb00/d; +v0x2890f70_0 .net "A", 0 0, L_0x2a6dc30; 1 drivers +v0x2891030_0 .net "AandB", 0 0, L_0x2a6e8a0; 1 drivers +v0x28910d0_0 .net "AddSubSLTSum", 0 0, L_0x2a6e7b0; 1 drivers +v0x2891170_0 .net "AxorB", 0 0, L_0x2a6e6c0; 1 drivers +v0x28911f0_0 .net "B", 0 0, L_0x2a6f060; 1 drivers +v0x28912a0_0 .net "BornB", 0 0, L_0x2a6e170; 1 drivers +v0x2891360_0 .net "CINandAxorB", 0 0, L_0x2a6ea10; 1 drivers +v0x28913e0_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x27f1c90_0 .net *"_s3", 0 0, L_0x2a6e440; 1 drivers +v0x27f1d10_0 .net *"_s5", 0 0, L_0x2a6e620; 1 drivers +v0x27f1db0_0 .net "carryin", 0 0, L_0x2a6f100; 1 drivers +v0x27f1e50_0 .net "carryout", 0 0, L_0x2a6eb00; 1 drivers +v0x27f1ef0_0 .net "nB", 0 0, L_0x2a6dd60; 1 drivers +v0x27f1fa0_0 .net "nCmd2", 0 0, L_0x2a6e3a0; 1 drivers +v0x27f20a0_0 .net "subtract", 0 0, L_0x2a6e4e0; 1 drivers +L_0x2a6e300 .part v0x2960210_0, 0, 1; +L_0x2a6e440 .part v0x2960210_0, 2, 1; +L_0x2a6e620 .part v0x2960210_0, 0, 1; +S_0x28909e0 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x28908f0; + .timescale -9 -12; +L_0x2a6def0/d .functor NOT 1, L_0x2a6e300, C4<0>, C4<0>, C4<0>; +L_0x2a6def0 .delay (10000,10000,10000) L_0x2a6def0/d; +L_0x2a6df90/d .functor AND 1, L_0x2a6f060, L_0x2a6def0, C4<1>, C4<1>; +L_0x2a6df90 .delay (20000,20000,20000) L_0x2a6df90/d; +L_0x2a6e080/d .functor AND 1, L_0x2a6dd60, L_0x2a6e300, C4<1>, C4<1>; +L_0x2a6e080 .delay (20000,20000,20000) L_0x2a6e080/d; +L_0x2a6e170/d .functor OR 1, L_0x2a6df90, L_0x2a6e080, C4<0>, C4<0>; +L_0x2a6e170 .delay (20000,20000,20000) L_0x2a6e170/d; +v0x2890ad0_0 .net "S", 0 0, L_0x2a6e300; 1 drivers +v0x2890b90_0 .alias "in0", 0 0, v0x28911f0_0; +v0x2890c30_0 .alias "in1", 0 0, v0x27f1ef0_0; +v0x2890cd0_0 .net "nS", 0 0, L_0x2a6def0; 1 drivers +v0x2890d50_0 .net "out0", 0 0, L_0x2a6df90; 1 drivers +v0x2890df0_0 .net "out1", 0 0, L_0x2a6e080; 1 drivers +v0x2890ed0_0 .alias "outfinal", 0 0, v0x28912a0_0; +S_0x2890380 .scope module, "setSLTres2" "TwoInMux" 3 335, 3 109, S_0x288fc90; + .timescale -9 -12; +L_0x2a6ee20/d .functor NOT 1, L_0x2aa3020, C4<0>, C4<0>, C4<0>; +L_0x2a6ee20 .delay (10000,10000,10000) L_0x2a6ee20/d; +L_0x2a6eec0/d .functor AND 1, L_0x2a6f610, L_0x2a6ee20, C4<1>, C4<1>; +L_0x2a6eec0 .delay (20000,20000,20000) L_0x2a6eec0/d; +L_0x2a6efd0/d .functor AND 1, C4<0>, L_0x2aa3020, C4<1>, C4<1>; +L_0x2a6efd0 .delay (20000,20000,20000) L_0x2a6efd0/d; +L_0x2a6f430/d .functor OR 1, L_0x2a6eec0, L_0x2a6efd0, C4<0>, C4<0>; +L_0x2a6f430 .delay (20000,20000,20000) L_0x2a6f430/d; +v0x2890470_0 .alias "S", 0 0, v0x289f760_0; +v0x2890510_0 .net "in0", 0 0, L_0x2a6f610; 1 drivers +v0x28905b0_0 .net "in1", 0 0, C4<0>; 1 drivers +v0x2890650_0 .net "nS", 0 0, L_0x2a6ee20; 1 drivers +v0x28906d0_0 .net "out0", 0 0, L_0x2a6eec0; 1 drivers +v0x2890770_0 .net "out1", 0 0, L_0x2a6efd0; 1 drivers +v0x2890850_0 .net "outfinal", 0 0, L_0x2a6f430; 1 drivers +S_0x288fe00 .scope module, "setSLTres3" "TwoInMux" 3 336, 3 109, S_0x288fc90; + .timescale -9 -12; +L_0x2a6f230/d .functor NOT 1, L_0x2aa3020, C4<0>, C4<0>, C4<0>; +L_0x2a6f230 .delay (10000,10000,10000) L_0x2a6f230/d; +L_0x2a6f340/d .functor AND 1, L_0x2a6fc70, L_0x2a6f230, C4<1>, C4<1>; +L_0x2a6f340 .delay (20000,20000,20000) L_0x2a6f340/d; +L_0x2a6f9f0/d .functor AND 1, L_0x2a6f700, L_0x2aa3020, C4<1>, C4<1>; +L_0x2a6f9f0 .delay (20000,20000,20000) L_0x2a6f9f0/d; +L_0x2a6fa90/d .functor OR 1, L_0x2a6f340, L_0x2a6f9f0, C4<0>, C4<0>; +L_0x2a6fa90 .delay (20000,20000,20000) L_0x2a6fa90/d; +v0x288fef0_0 .alias "S", 0 0, v0x289f760_0; +v0x288ff70_0 .net "in0", 0 0, L_0x2a6fc70; 1 drivers +v0x2890010_0 .net "in1", 0 0, L_0x2a6f700; 1 drivers +v0x28900b0_0 .net "nS", 0 0, L_0x2a6f230; 1 drivers +v0x2890160_0 .net "out0", 0 0, L_0x2a6f340; 1 drivers +v0x2890200_0 .net "out1", 0 0, L_0x2a6f9f0; 1 drivers +v0x28902e0_0 .net "outfinal", 0 0, L_0x2a6fa90; 1 drivers +S_0x288e010 .scope generate, "sltbits[8]" "sltbits[8]" 3 332, 3 332, S_0x2864a60; + .timescale -9 -12; +P_0x288da28 .param/l "i" 3 332, +C4<01000>; +S_0x288ec70 .scope module, "attempt" "MiddleAddSubSLT" 3 334, 3 189, S_0x288e010; + .timescale -9 -12; +L_0x2a6f7f0/d .functor NOT 1, L_0x2a711d0, C4<0>, C4<0>, C4<0>; +L_0x2a6f7f0 .delay (10000,10000,10000) L_0x2a6f7f0/d; +L_0x2a704d0/d .functor NOT 1, L_0x2a70570, C4<0>, C4<0>, C4<0>; +L_0x2a704d0 .delay (10000,10000,10000) L_0x2a704d0/d; +L_0x2a70610/d .functor AND 1, L_0x2a70750, L_0x2a704d0, C4<1>, C4<1>; +L_0x2a70610 .delay (20000,20000,20000) L_0x2a70610/d; +L_0x2a707f0/d .functor XOR 1, L_0x2a71130, L_0x2a702a0, C4<0>, C4<0>; +L_0x2a707f0 .delay (40000,40000,40000) L_0x2a707f0/d; +L_0x2a708e0/d .functor XOR 1, L_0x2a707f0, L_0x2a70ea0, C4<0>, C4<0>; +L_0x2a708e0 .delay (40000,40000,40000) L_0x2a708e0/d; +L_0x2a709d0/d .functor AND 1, L_0x2a71130, L_0x2a702a0, C4<1>, C4<1>; +L_0x2a709d0 .delay (20000,20000,20000) L_0x2a709d0/d; +L_0x2a70b40/d .functor AND 1, L_0x2a707f0, L_0x2a70ea0, C4<1>, C4<1>; +L_0x2a70b40 .delay (20000,20000,20000) L_0x2a70b40/d; +L_0x2a70c50/d .functor OR 1, L_0x2a709d0, L_0x2a70b40, C4<0>, C4<0>; +L_0x2a70c50 .delay (20000,20000,20000) L_0x2a70c50/d; +v0x288f2f0_0 .net "A", 0 0, L_0x2a71130; 1 drivers +v0x288f3b0_0 .net "AandB", 0 0, L_0x2a709d0; 1 drivers +v0x288f450_0 .net "AddSubSLTSum", 0 0, L_0x2a708e0; 1 drivers +v0x288f4f0_0 .net "AxorB", 0 0, L_0x2a707f0; 1 drivers +v0x288f570_0 .net "B", 0 0, L_0x2a711d0; 1 drivers +v0x288f620_0 .net "BornB", 0 0, L_0x2a702a0; 1 drivers +v0x288f6e0_0 .net "CINandAxorB", 0 0, L_0x2a70b40; 1 drivers +v0x288f760_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x288f7e0_0 .net *"_s3", 0 0, L_0x2a70570; 1 drivers +v0x288f860_0 .net *"_s5", 0 0, L_0x2a70750; 1 drivers +v0x288f900_0 .net "carryin", 0 0, L_0x2a70ea0; 1 drivers +v0x288f9a0_0 .net "carryout", 0 0, L_0x2a70c50; 1 drivers +v0x288fa40_0 .net "nB", 0 0, L_0x2a6f7f0; 1 drivers +v0x288faf0_0 .net "nCmd2", 0 0, L_0x2a704d0; 1 drivers +v0x288fbf0_0 .net "subtract", 0 0, L_0x2a70610; 1 drivers +L_0x2a70430 .part v0x2960210_0, 0, 1; +L_0x2a70570 .part v0x2960210_0, 2, 1; +L_0x2a70750 .part v0x2960210_0, 0, 1; +S_0x288ed60 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x288ec70; + .timescale -9 -12; +L_0x2a70020/d .functor NOT 1, L_0x2a70430, C4<0>, C4<0>, C4<0>; +L_0x2a70020 .delay (10000,10000,10000) L_0x2a70020/d; +L_0x2a700c0/d .functor AND 1, L_0x2a711d0, L_0x2a70020, C4<1>, C4<1>; +L_0x2a700c0 .delay (20000,20000,20000) L_0x2a700c0/d; +L_0x2a701b0/d .functor AND 1, L_0x2a6f7f0, L_0x2a70430, C4<1>, C4<1>; +L_0x2a701b0 .delay (20000,20000,20000) L_0x2a701b0/d; +L_0x2a702a0/d .functor OR 1, L_0x2a700c0, L_0x2a701b0, C4<0>, C4<0>; +L_0x2a702a0 .delay (20000,20000,20000) L_0x2a702a0/d; +v0x288ee50_0 .net "S", 0 0, L_0x2a70430; 1 drivers +v0x288ef10_0 .alias "in0", 0 0, v0x288f570_0; +v0x288efb0_0 .alias "in1", 0 0, v0x288fa40_0; +v0x288f050_0 .net "nS", 0 0, L_0x2a70020; 1 drivers +v0x288f0d0_0 .net "out0", 0 0, L_0x2a700c0; 1 drivers +v0x288f170_0 .net "out1", 0 0, L_0x2a701b0; 1 drivers +v0x288f250_0 .alias "outfinal", 0 0, v0x288f620_0; +S_0x288e700 .scope module, "setSLTres2" "TwoInMux" 3 335, 3 109, S_0x288e010; + .timescale -9 -12; +L_0x2a68e50/d .functor NOT 1, L_0x2aa3020, C4<0>, C4<0>, C4<0>; +L_0x2a68e50 .delay (10000,10000,10000) L_0x2a68e50/d; +L_0x2a68ef0/d .functor AND 1, L_0x2a71270, L_0x2a68e50, C4<1>, C4<1>; +L_0x2a68ef0 .delay (20000,20000,20000) L_0x2a68ef0/d; +L_0x2a70ff0/d .functor AND 1, C4<0>, L_0x2aa3020, C4<1>, C4<1>; +L_0x2a70ff0 .delay (20000,20000,20000) L_0x2a70ff0/d; +L_0x2a71090/d .functor OR 1, L_0x2a68ef0, L_0x2a70ff0, C4<0>, C4<0>; +L_0x2a71090 .delay (20000,20000,20000) L_0x2a71090/d; +v0x288e7f0_0 .alias "S", 0 0, v0x289f760_0; +v0x288e890_0 .net "in0", 0 0, L_0x2a71270; 1 drivers +v0x288e930_0 .net "in1", 0 0, C4<0>; 1 drivers +v0x288e9d0_0 .net "nS", 0 0, L_0x2a68e50; 1 drivers +v0x288ea50_0 .net "out0", 0 0, L_0x2a68ef0; 1 drivers +v0x288eaf0_0 .net "out1", 0 0, L_0x2a70ff0; 1 drivers +v0x288ebd0_0 .net "outfinal", 0 0, L_0x2a71090; 1 drivers +S_0x288e180 .scope module, "setSLTres3" "TwoInMux" 3 336, 3 109, S_0x288e010; + .timescale -9 -12; +L_0x2a693c0/d .functor NOT 1, L_0x2aa3020, C4<0>, C4<0>, C4<0>; +L_0x2a693c0 .delay (10000,10000,10000) L_0x2a693c0/d; +L_0x2a713f0/d .functor AND 1, L_0x2a71860, L_0x2a693c0, C4<1>, C4<1>; +L_0x2a713f0 .delay (20000,20000,20000) L_0x2a713f0/d; +L_0x2a714b0/d .functor AND 1, L_0x2a71950, L_0x2aa3020, C4<1>, C4<1>; +L_0x2a714b0 .delay (20000,20000,20000) L_0x2a714b0/d; +L_0x2a71db0/d .functor OR 1, L_0x2a713f0, L_0x2a714b0, C4<0>, C4<0>; +L_0x2a71db0 .delay (20000,20000,20000) L_0x2a71db0/d; +v0x288e270_0 .alias "S", 0 0, v0x289f760_0; +v0x288e2f0_0 .net "in0", 0 0, L_0x2a71860; 1 drivers +v0x288e390_0 .net "in1", 0 0, L_0x2a71950; 1 drivers +v0x288e430_0 .net "nS", 0 0, L_0x2a693c0; 1 drivers +v0x288e4e0_0 .net "out0", 0 0, L_0x2a713f0; 1 drivers +v0x288e580_0 .net "out1", 0 0, L_0x2a714b0; 1 drivers +v0x288e660_0 .net "outfinal", 0 0, L_0x2a71db0; 1 drivers +S_0x288c390 .scope generate, "sltbits[9]" "sltbits[9]" 3 332, 3 332, S_0x2864a60; + .timescale -9 -12; +P_0x288bc88 .param/l "i" 3 332, +C4<01001>; +S_0x288cff0 .scope module, "attempt" "MiddleAddSubSLT" 3 334, 3 189, S_0x288c390; + .timescale -9 -12; +L_0x2a71a40/d .functor NOT 1, L_0x2a72120, C4<0>, C4<0>, C4<0>; +L_0x2a71a40 .delay (10000,10000,10000) L_0x2a71a40/d; +L_0x2a728b0/d .functor NOT 1, L_0x2a72970, C4<0>, C4<0>, C4<0>; +L_0x2a728b0 .delay (10000,10000,10000) L_0x2a728b0/d; +L_0x2a72a10/d .functor AND 1, L_0x2a72b50, L_0x2a728b0, C4<1>, C4<1>; +L_0x2a72a10 .delay (20000,20000,20000) L_0x2a72a10/d; +L_0x2a72bf0/d .functor XOR 1, L_0x2a72080, L_0x2a72640, C4<0>, C4<0>; +L_0x2a72bf0 .delay (40000,40000,40000) L_0x2a72bf0/d; +L_0x2a72ce0/d .functor XOR 1, L_0x2a72bf0, L_0x2a73660, C4<0>, C4<0>; +L_0x2a72ce0 .delay (40000,40000,40000) L_0x2a72ce0/d; +L_0x2a72dd0/d .functor AND 1, L_0x2a72080, L_0x2a72640, C4<1>, C4<1>; +L_0x2a72dd0 .delay (20000,20000,20000) L_0x2a72dd0/d; +L_0x2a72f40/d .functor AND 1, L_0x2a72bf0, L_0x2a73660, C4<1>, C4<1>; +L_0x2a72f40 .delay (20000,20000,20000) L_0x2a72f40/d; +L_0x2a73030/d .functor OR 1, L_0x2a72dd0, L_0x2a72f40, C4<0>, C4<0>; +L_0x2a73030 .delay (20000,20000,20000) L_0x2a73030/d; +v0x288d670_0 .net "A", 0 0, L_0x2a72080; 1 drivers +v0x288d730_0 .net "AandB", 0 0, L_0x2a72dd0; 1 drivers +v0x288d7d0_0 .net "AddSubSLTSum", 0 0, L_0x2a72ce0; 1 drivers +v0x288d870_0 .net "AxorB", 0 0, L_0x2a72bf0; 1 drivers +v0x288d8f0_0 .net "B", 0 0, L_0x2a72120; 1 drivers +v0x288d9a0_0 .net "BornB", 0 0, L_0x2a72640; 1 drivers +v0x288da60_0 .net "CINandAxorB", 0 0, L_0x2a72f40; 1 drivers +v0x288dae0_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x288db60_0 .net *"_s3", 0 0, L_0x2a72970; 1 drivers +v0x288dbe0_0 .net *"_s5", 0 0, L_0x2a72b50; 1 drivers +v0x288dc80_0 .net "carryin", 0 0, L_0x2a73660; 1 drivers +v0x288dd20_0 .net "carryout", 0 0, L_0x2a73030; 1 drivers +v0x288ddc0_0 .net "nB", 0 0, L_0x2a71a40; 1 drivers +v0x288de70_0 .net "nCmd2", 0 0, L_0x2a728b0; 1 drivers +v0x288df70_0 .net "subtract", 0 0, L_0x2a72a10; 1 drivers +L_0x2a72810 .part v0x2960210_0, 0, 1; +L_0x2a72970 .part v0x2960210_0, 2, 1; +L_0x2a72b50 .part v0x2960210_0, 0, 1; +S_0x288d0e0 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x288cff0; + .timescale -9 -12; +L_0x2a72360/d .functor NOT 1, L_0x2a72810, C4<0>, C4<0>, C4<0>; +L_0x2a72360 .delay (10000,10000,10000) L_0x2a72360/d; +L_0x2a72420/d .functor AND 1, L_0x2a72120, L_0x2a72360, C4<1>, C4<1>; +L_0x2a72420 .delay (20000,20000,20000) L_0x2a72420/d; +L_0x2a72530/d .functor AND 1, L_0x2a71a40, L_0x2a72810, C4<1>, C4<1>; +L_0x2a72530 .delay (20000,20000,20000) L_0x2a72530/d; +L_0x2a72640/d .functor OR 1, L_0x2a72420, L_0x2a72530, C4<0>, C4<0>; +L_0x2a72640 .delay (20000,20000,20000) L_0x2a72640/d; +v0x288d1d0_0 .net "S", 0 0, L_0x2a72810; 1 drivers +v0x288d290_0 .alias "in0", 0 0, v0x288d8f0_0; +v0x288d330_0 .alias "in1", 0 0, v0x288ddc0_0; +v0x288d3d0_0 .net "nS", 0 0, L_0x2a72360; 1 drivers +v0x288d450_0 .net "out0", 0 0, L_0x2a72420; 1 drivers +v0x288d4f0_0 .net "out1", 0 0, L_0x2a72530; 1 drivers +v0x288d5d0_0 .alias "outfinal", 0 0, v0x288d9a0_0; +S_0x288ca80 .scope module, "setSLTres2" "TwoInMux" 3 335, 3 109, S_0x288c390; + .timescale -9 -12; +L_0x2a73370/d .functor NOT 1, L_0x2aa3020, C4<0>, C4<0>, C4<0>; +L_0x2a73370 .delay (10000,10000,10000) L_0x2a73370/d; +L_0x2a73410/d .functor AND 1, L_0x2a73b40, L_0x2a73370, C4<1>, C4<1>; +L_0x2a73410 .delay (20000,20000,20000) L_0x2a73410/d; +L_0x2a73520/d .functor AND 1, C4<0>, L_0x2aa3020, C4<1>, C4<1>; +L_0x2a73520 .delay (20000,20000,20000) L_0x2a73520/d; +L_0x2a735c0/d .functor OR 1, L_0x2a73410, L_0x2a73520, C4<0>, C4<0>; +L_0x2a735c0 .delay (20000,20000,20000) L_0x2a735c0/d; +v0x288cb70_0 .alias "S", 0 0, v0x289f760_0; +v0x288cc10_0 .net "in0", 0 0, L_0x2a73b40; 1 drivers +v0x288ccb0_0 .net "in1", 0 0, C4<0>; 1 drivers +v0x288cd50_0 .net "nS", 0 0, L_0x2a73370; 1 drivers +v0x288cdd0_0 .net "out0", 0 0, L_0x2a73410; 1 drivers +v0x288ce70_0 .net "out1", 0 0, L_0x2a73520; 1 drivers +v0x288cf50_0 .net "outfinal", 0 0, L_0x2a735c0; 1 drivers +S_0x288c500 .scope module, "setSLTres3" "TwoInMux" 3 336, 3 109, S_0x288c390; + .timescale -9 -12; +L_0x2a73790/d .functor NOT 1, L_0x2aa3020, C4<0>, C4<0>, C4<0>; +L_0x2a73790 .delay (10000,10000,10000) L_0x2a73790/d; +L_0x2a738a0/d .functor AND 1, L_0x2a74180, L_0x2a73790, C4<1>, C4<1>; +L_0x2a738a0 .delay (20000,20000,20000) L_0x2a738a0/d; +L_0x2a73f40/d .functor AND 1, L_0x2a73c30, L_0x2aa3020, C4<1>, C4<1>; +L_0x2a73f40 .delay (20000,20000,20000) L_0x2a73f40/d; +L_0x2a73fa0/d .functor OR 1, L_0x2a738a0, L_0x2a73f40, C4<0>, C4<0>; +L_0x2a73fa0 .delay (20000,20000,20000) L_0x2a73fa0/d; +v0x288c5f0_0 .alias "S", 0 0, v0x289f760_0; +v0x288c670_0 .net "in0", 0 0, L_0x2a74180; 1 drivers +v0x288c710_0 .net "in1", 0 0, L_0x2a73c30; 1 drivers +v0x288c7b0_0 .net "nS", 0 0, L_0x2a73790; 1 drivers +v0x288c860_0 .net "out0", 0 0, L_0x2a738a0; 1 drivers +v0x288c900_0 .net "out1", 0 0, L_0x2a73f40; 1 drivers +v0x288c9e0_0 .net "outfinal", 0 0, L_0x2a73fa0; 1 drivers +S_0x288a700 .scope generate, "sltbits[10]" "sltbits[10]" 3 332, 3 332, S_0x2864a60; + .timescale -9 -12; +P_0x288a118 .param/l "i" 3 332, +C4<01010>; +S_0x288b280 .scope module, "attempt" "MiddleAddSubSLT" 3 334, 3 189, S_0x288a700; + .timescale -9 -12; +L_0x2a73d20/d .functor NOT 1, L_0x2a744f0, C4<0>, C4<0>, C4<0>; +L_0x2a73d20 .delay (10000,10000,10000) L_0x2a73d20/d; +L_0x2a74aa0/d .functor NOT 1, L_0x2a74b60, C4<0>, C4<0>, C4<0>; +L_0x2a74aa0 .delay (10000,10000,10000) L_0x2a74aa0/d; +L_0x2a74c00/d .functor AND 1, L_0x2a74d40, L_0x2a74aa0, C4<1>, C4<1>; +L_0x2a74c00 .delay (20000,20000,20000) L_0x2a74c00/d; +L_0x2a74de0/d .functor XOR 1, L_0x2a74450, L_0x2a74830, C4<0>, C4<0>; +L_0x2a74de0 .delay (40000,40000,40000) L_0x2a74de0/d; +L_0x2a74ed0/d .functor XOR 1, L_0x2a74de0, L_0x2a75470, C4<0>, C4<0>; +L_0x2a74ed0 .delay (40000,40000,40000) L_0x2a74ed0/d; +L_0x2a74fc0/d .functor AND 1, L_0x2a74450, L_0x2a74830, C4<1>, C4<1>; +L_0x2a74fc0 .delay (20000,20000,20000) L_0x2a74fc0/d; +L_0x2a75130/d .functor AND 1, L_0x2a74de0, L_0x2a75470, C4<1>, C4<1>; +L_0x2a75130 .delay (20000,20000,20000) L_0x2a75130/d; +L_0x2a75220/d .functor OR 1, L_0x2a74fc0, L_0x2a75130, C4<0>, C4<0>; +L_0x2a75220 .delay (20000,20000,20000) L_0x2a75220/d; +v0x288b900_0 .net "A", 0 0, L_0x2a74450; 1 drivers +v0x288b9c0_0 .net "AandB", 0 0, L_0x2a74fc0; 1 drivers +v0x288ba60_0 .net "AddSubSLTSum", 0 0, L_0x2a74ed0; 1 drivers +v0x288bb00_0 .net "AxorB", 0 0, L_0x2a74de0; 1 drivers +v0x288bb80_0 .net "B", 0 0, L_0x2a744f0; 1 drivers +v0x288bc00_0 .net "BornB", 0 0, L_0x2a74830; 1 drivers +v0x288bcc0_0 .net "CINandAxorB", 0 0, L_0x2a75130; 1 drivers +v0x288bd40_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x288be10_0 .net *"_s3", 0 0, L_0x2a74b60; 1 drivers +v0x288be90_0 .net *"_s5", 0 0, L_0x2a74d40; 1 drivers +v0x288bf90_0 .net "carryin", 0 0, L_0x2a75470; 1 drivers +v0x288c030_0 .net "carryout", 0 0, L_0x2a75220; 1 drivers +v0x288c140_0 .net "nB", 0 0, L_0x2a73d20; 1 drivers +v0x288c1f0_0 .net "nCmd2", 0 0, L_0x2a74aa0; 1 drivers +v0x288c2f0_0 .net "subtract", 0 0, L_0x2a74c00; 1 drivers +L_0x2a74a00 .part v0x2960210_0, 0, 1; +L_0x2a74b60 .part v0x2960210_0, 2, 1; +L_0x2a74d40 .part v0x2960210_0, 0, 1; +S_0x288b370 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x288b280; + .timescale -9 -12; +L_0x2a74590/d .functor NOT 1, L_0x2a74a00, C4<0>, C4<0>, C4<0>; +L_0x2a74590 .delay (10000,10000,10000) L_0x2a74590/d; +L_0x2a74630/d .functor AND 1, L_0x2a744f0, L_0x2a74590, C4<1>, C4<1>; +L_0x2a74630 .delay (20000,20000,20000) L_0x2a74630/d; +L_0x2a74720/d .functor AND 1, L_0x2a73d20, L_0x2a74a00, C4<1>, C4<1>; +L_0x2a74720 .delay (20000,20000,20000) L_0x2a74720/d; +L_0x2a74830/d .functor OR 1, L_0x2a74630, L_0x2a74720, C4<0>, C4<0>; +L_0x2a74830 .delay (20000,20000,20000) L_0x2a74830/d; +v0x288b460_0 .net "S", 0 0, L_0x2a74a00; 1 drivers +v0x288b500_0 .alias "in0", 0 0, v0x288bb80_0; +v0x288b5a0_0 .alias "in1", 0 0, v0x288c140_0; +v0x288b640_0 .net "nS", 0 0, L_0x2a74590; 1 drivers +v0x288b6e0_0 .net "out0", 0 0, L_0x2a74630; 1 drivers +v0x288b780_0 .net "out1", 0 0, L_0x2a74720; 1 drivers +v0x288b860_0 .alias "outfinal", 0 0, v0x288bc00_0; +S_0x288adf0 .scope module, "setSLTres2" "TwoInMux" 3 335, 3 109, S_0x288a700; + .timescale -9 -12; +L_0x2a75510/d .functor NOT 1, L_0x2aa3020, C4<0>, C4<0>, C4<0>; +L_0x2a75510 .delay (10000,10000,10000) L_0x2a75510/d; +L_0x2a755b0/d .functor AND 1, L_0x2a75840, L_0x2a75510, C4<1>, C4<1>; +L_0x2a755b0 .delay (20000,20000,20000) L_0x2a755b0/d; +L_0x2a756c0/d .functor AND 1, C4<0>, L_0x2aa3020, C4<1>, C4<1>; +L_0x2a756c0 .delay (20000,20000,20000) L_0x2a756c0/d; +L_0x2a75b90/d .functor OR 1, L_0x2a755b0, L_0x2a756c0, C4<0>, C4<0>; +L_0x2a75b90 .delay (20000,20000,20000) L_0x2a75b90/d; +v0x288aee0_0 .alias "S", 0 0, v0x289f760_0; +v0x288af80_0 .net "in0", 0 0, L_0x2a75840; 1 drivers +v0x288b000_0 .net "in1", 0 0, C4<0>; 1 drivers +v0x288b080_0 .net "nS", 0 0, L_0x2a75510; 1 drivers +v0x288b100_0 .net "out0", 0 0, L_0x2a755b0; 1 drivers +v0x288b180_0 .net "out1", 0 0, L_0x2a756c0; 1 drivers +v0x288b200_0 .net "outfinal", 0 0, L_0x2a75b90; 1 drivers +S_0x288a870 .scope module, "setSLTres3" "TwoInMux" 3 336, 3 109, S_0x288a700; + .timescale -9 -12; +L_0x2a75b30/d .functor NOT 1, L_0x2aa3020, C4<0>, C4<0>, C4<0>; +L_0x2a75b30 .delay (10000,10000,10000) L_0x2a75b30/d; +L_0x2a6cea0/d .functor AND 1, L_0x2a75d70, L_0x2a75b30, C4<1>, C4<1>; +L_0x2a6cea0 .delay (20000,20000,20000) L_0x2a6cea0/d; +L_0x2a76160/d .functor AND 1, L_0x2a75e60, L_0x2aa3020, C4<1>, C4<1>; +L_0x2a76160 .delay (20000,20000,20000) L_0x2a76160/d; +L_0x2a76200/d .functor OR 1, L_0x2a6cea0, L_0x2a76160, C4<0>, C4<0>; +L_0x2a76200 .delay (20000,20000,20000) L_0x2a76200/d; +v0x288a960_0 .alias "S", 0 0, v0x289f760_0; +v0x288a9e0_0 .net "in0", 0 0, L_0x2a75d70; 1 drivers +v0x288aa80_0 .net "in1", 0 0, L_0x2a75e60; 1 drivers +v0x288ab20_0 .net "nS", 0 0, L_0x2a75b30; 1 drivers +v0x288abd0_0 .net "out0", 0 0, L_0x2a6cea0; 1 drivers +v0x288ac70_0 .net "out1", 0 0, L_0x2a76160; 1 drivers +v0x288ad50_0 .net "outfinal", 0 0, L_0x2a76200; 1 drivers +S_0x2888a80 .scope generate, "sltbits[11]" "sltbits[11]" 3 332, 3 332, S_0x2864a60; + .timescale -9 -12; +P_0x2888498 .param/l "i" 3 332, +C4<01011>; +S_0x28896e0 .scope module, "attempt" "MiddleAddSubSLT" 3 334, 3 189, S_0x2888a80; + .timescale -9 -12; +L_0x2a75f50/d .functor NOT 1, L_0x2a76570, C4<0>, C4<0>, C4<0>; +L_0x2a75f50 .delay (10000,10000,10000) L_0x2a75f50/d; +L_0x2a76cc0/d .functor NOT 1, L_0x2a76d80, C4<0>, C4<0>, C4<0>; +L_0x2a76cc0 .delay (10000,10000,10000) L_0x2a76cc0/d; +L_0x2a76e20/d .functor AND 1, L_0x2a76f60, L_0x2a76cc0, C4<1>, C4<1>; +L_0x2a76e20 .delay (20000,20000,20000) L_0x2a76e20/d; +L_0x2a77000/d .functor XOR 1, L_0x2a764d0, L_0x2a76a50, C4<0>, C4<0>; +L_0x2a77000 .delay (40000,40000,40000) L_0x2a77000/d; +L_0x2a770f0/d .functor XOR 1, L_0x2a77000, L_0x2a766a0, C4<0>, C4<0>; +L_0x2a770f0 .delay (40000,40000,40000) L_0x2a770f0/d; +L_0x2a771e0/d .functor AND 1, L_0x2a764d0, L_0x2a76a50, C4<1>, C4<1>; +L_0x2a771e0 .delay (20000,20000,20000) L_0x2a771e0/d; +L_0x2a77350/d .functor AND 1, L_0x2a77000, L_0x2a766a0, C4<1>, C4<1>; +L_0x2a77350 .delay (20000,20000,20000) L_0x2a77350/d; +L_0x2a77460/d .functor OR 1, L_0x2a771e0, L_0x2a77350, C4<0>, C4<0>; +L_0x2a77460 .delay (20000,20000,20000) L_0x2a77460/d; +v0x2889d60_0 .net "A", 0 0, L_0x2a764d0; 1 drivers +v0x2889e20_0 .net "AandB", 0 0, L_0x2a771e0; 1 drivers +v0x2889ec0_0 .net "AddSubSLTSum", 0 0, L_0x2a770f0; 1 drivers +v0x2889f60_0 .net "AxorB", 0 0, L_0x2a77000; 1 drivers +v0x2889fe0_0 .net "B", 0 0, L_0x2a76570; 1 drivers +v0x288a090_0 .net "BornB", 0 0, L_0x2a76a50; 1 drivers +v0x288a150_0 .net "CINandAxorB", 0 0, L_0x2a77350; 1 drivers +v0x288a1d0_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x288a250_0 .net *"_s3", 0 0, L_0x2a76d80; 1 drivers +v0x288a2d0_0 .net *"_s5", 0 0, L_0x2a76f60; 1 drivers +v0x288a370_0 .net "carryin", 0 0, L_0x2a766a0; 1 drivers +v0x288a410_0 .net "carryout", 0 0, L_0x2a77460; 1 drivers +v0x288a4b0_0 .net "nB", 0 0, L_0x2a75f50; 1 drivers +v0x288a560_0 .net "nCmd2", 0 0, L_0x2a76cc0; 1 drivers +v0x288a660_0 .net "subtract", 0 0, L_0x2a76e20; 1 drivers +L_0x2a76c20 .part v0x2960210_0, 0, 1; +L_0x2a76d80 .part v0x2960210_0, 2, 1; +L_0x2a76f60 .part v0x2960210_0, 0, 1; +S_0x28897d0 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x28896e0; + .timescale -9 -12; +L_0x2a767b0/d .functor NOT 1, L_0x2a76c20, C4<0>, C4<0>, C4<0>; +L_0x2a767b0 .delay (10000,10000,10000) L_0x2a767b0/d; +L_0x2a76850/d .functor AND 1, L_0x2a76570, L_0x2a767b0, C4<1>, C4<1>; +L_0x2a76850 .delay (20000,20000,20000) L_0x2a76850/d; +L_0x2a76940/d .functor AND 1, L_0x2a75f50, L_0x2a76c20, C4<1>, C4<1>; +L_0x2a76940 .delay (20000,20000,20000) L_0x2a76940/d; +L_0x2a76a50/d .functor OR 1, L_0x2a76850, L_0x2a76940, C4<0>, C4<0>; +L_0x2a76a50 .delay (20000,20000,20000) L_0x2a76a50/d; +v0x28898c0_0 .net "S", 0 0, L_0x2a76c20; 1 drivers +v0x2889980_0 .alias "in0", 0 0, v0x2889fe0_0; +v0x2889a20_0 .alias "in1", 0 0, v0x288a4b0_0; +v0x2889ac0_0 .net "nS", 0 0, L_0x2a767b0; 1 drivers +v0x2889b40_0 .net "out0", 0 0, L_0x2a76850; 1 drivers +v0x2889be0_0 .net "out1", 0 0, L_0x2a76940; 1 drivers +v0x2889cc0_0 .alias "outfinal", 0 0, v0x288a090_0; +S_0x2889170 .scope module, "setSLTres2" "TwoInMux" 3 335, 3 109, S_0x2888a80; + .timescale -9 -12; +L_0x2a77b50/d .functor NOT 1, L_0x2aa3020, C4<0>, C4<0>, C4<0>; +L_0x2a77b50 .delay (10000,10000,10000) L_0x2a77b50/d; +L_0x2a77bd0/d .functor AND 1, L_0x2a77f60, L_0x2a77b50, C4<1>, C4<1>; +L_0x2a77bd0 .delay (20000,20000,20000) L_0x2a77bd0/d; +L_0x2a77ce0/d .functor AND 1, C4<0>, L_0x2aa3020, C4<1>, C4<1>; +L_0x2a77ce0 .delay (20000,20000,20000) L_0x2a77ce0/d; +L_0x2a77d80/d .functor OR 1, L_0x2a77bd0, L_0x2a77ce0, C4<0>, C4<0>; +L_0x2a77d80 .delay (20000,20000,20000) L_0x2a77d80/d; +v0x2889260_0 .alias "S", 0 0, v0x289f760_0; +v0x2889300_0 .net "in0", 0 0, L_0x2a77f60; 1 drivers +v0x28893a0_0 .net "in1", 0 0, C4<0>; 1 drivers +v0x2889440_0 .net "nS", 0 0, L_0x2a77b50; 1 drivers +v0x28894c0_0 .net "out0", 0 0, L_0x2a77bd0; 1 drivers +v0x2889560_0 .net "out1", 0 0, L_0x2a77ce0; 1 drivers +v0x2889640_0 .net "outfinal", 0 0, L_0x2a77d80; 1 drivers +S_0x2888bf0 .scope module, "setSLTres3" "TwoInMux" 3 336, 3 109, S_0x2888a80; + .timescale -9 -12; +L_0x2a77830/d .functor NOT 1, L_0x2aa3020, C4<0>, C4<0>, C4<0>; +L_0x2a77830 .delay (10000,10000,10000) L_0x2a77830/d; +L_0x2a77940/d .functor AND 1, L_0x2a78590, L_0x2a77830, C4<1>, C4<1>; +L_0x2a77940 .delay (20000,20000,20000) L_0x2a77940/d; +L_0x2a77a50/d .functor AND 1, L_0x2a6d3c0, L_0x2aa3020, C4<1>, C4<1>; +L_0x2a77a50 .delay (20000,20000,20000) L_0x2a77a50/d; +L_0x2a77af0/d .functor OR 1, L_0x2a77940, L_0x2a77a50, C4<0>, C4<0>; +L_0x2a77af0 .delay (20000,20000,20000) L_0x2a77af0/d; +v0x2888ce0_0 .alias "S", 0 0, v0x289f760_0; +v0x2888d60_0 .net "in0", 0 0, L_0x2a78590; 1 drivers +v0x2888e00_0 .net "in1", 0 0, L_0x2a6d3c0; 1 drivers +v0x2888ea0_0 .net "nS", 0 0, L_0x2a77830; 1 drivers +v0x2888f50_0 .net "out0", 0 0, L_0x2a77940; 1 drivers +v0x2888ff0_0 .net "out1", 0 0, L_0x2a77a50; 1 drivers +v0x28890d0_0 .net "outfinal", 0 0, L_0x2a77af0; 1 drivers +S_0x2886e00 .scope generate, "sltbits[12]" "sltbits[12]" 3 332, 3 332, S_0x2864a60; + .timescale -9 -12; +P_0x2886818 .param/l "i" 3 332, +C4<01100>; +S_0x2887a60 .scope module, "attempt" "MiddleAddSubSLT" 3 334, 3 189, S_0x2886e00; + .timescale -9 -12; +L_0x2a6d4b0/d .functor NOT 1, L_0x2a78d10, C4<0>, C4<0>, C4<0>; +L_0x2a6d4b0 .delay (10000,10000,10000) L_0x2a6d4b0/d; +L_0x2a78fe0/d .functor NOT 1, L_0x2a79080, C4<0>, C4<0>, C4<0>; +L_0x2a78fe0 .delay (10000,10000,10000) L_0x2a78fe0/d; +L_0x2a79120/d .functor AND 1, L_0x2a79260, L_0x2a78fe0, C4<1>, C4<1>; +L_0x2a79120 .delay (20000,20000,20000) L_0x2a79120/d; +L_0x2a79300/d .functor XOR 1, L_0x2a78c70, L_0x2a78330, C4<0>, C4<0>; +L_0x2a79300 .delay (40000,40000,40000) L_0x2a79300/d; +L_0x2a793f0/d .functor XOR 1, L_0x2a79300, L_0x2a79d70, C4<0>, C4<0>; +L_0x2a793f0 .delay (40000,40000,40000) L_0x2a793f0/d; +L_0x2a794e0/d .functor AND 1, L_0x2a78c70, L_0x2a78330, C4<1>, C4<1>; +L_0x2a794e0 .delay (20000,20000,20000) L_0x2a794e0/d; +L_0x2a79650/d .functor AND 1, L_0x2a79300, L_0x2a79d70, C4<1>, C4<1>; +L_0x2a79650 .delay (20000,20000,20000) L_0x2a79650/d; +L_0x2a79740/d .functor OR 1, L_0x2a794e0, L_0x2a79650, C4<0>, C4<0>; +L_0x2a79740 .delay (20000,20000,20000) L_0x2a79740/d; +v0x28880e0_0 .net "A", 0 0, L_0x2a78c70; 1 drivers +v0x28881a0_0 .net "AandB", 0 0, L_0x2a794e0; 1 drivers +v0x2888240_0 .net "AddSubSLTSum", 0 0, L_0x2a793f0; 1 drivers +v0x28882e0_0 .net "AxorB", 0 0, L_0x2a79300; 1 drivers +v0x2888360_0 .net "B", 0 0, L_0x2a78d10; 1 drivers +v0x2888410_0 .net "BornB", 0 0, L_0x2a78330; 1 drivers +v0x28884d0_0 .net "CINandAxorB", 0 0, L_0x2a79650; 1 drivers +v0x2888550_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x28885d0_0 .net *"_s3", 0 0, L_0x2a79080; 1 drivers +v0x2888650_0 .net *"_s5", 0 0, L_0x2a79260; 1 drivers +v0x28886f0_0 .net "carryin", 0 0, L_0x2a79d70; 1 drivers +v0x2888790_0 .net "carryout", 0 0, L_0x2a79740; 1 drivers +v0x2888830_0 .net "nB", 0 0, L_0x2a6d4b0; 1 drivers +v0x28888e0_0 .net "nCmd2", 0 0, L_0x2a78fe0; 1 drivers +v0x28889e0_0 .net "subtract", 0 0, L_0x2a79120; 1 drivers +L_0x2a78f40 .part v0x2960210_0, 0, 1; +L_0x2a79080 .part v0x2960210_0, 2, 1; +L_0x2a79260 .part v0x2960210_0, 0, 1; +S_0x2887b50 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x2887a60; + .timescale -9 -12; +L_0x2a78050/d .functor NOT 1, L_0x2a78f40, C4<0>, C4<0>, C4<0>; +L_0x2a78050 .delay (10000,10000,10000) L_0x2a78050/d; +L_0x2a78110/d .functor AND 1, L_0x2a78d10, L_0x2a78050, C4<1>, C4<1>; +L_0x2a78110 .delay (20000,20000,20000) L_0x2a78110/d; +L_0x2a78220/d .functor AND 1, L_0x2a6d4b0, L_0x2a78f40, C4<1>, C4<1>; +L_0x2a78220 .delay (20000,20000,20000) L_0x2a78220/d; +L_0x2a78330/d .functor OR 1, L_0x2a78110, L_0x2a78220, C4<0>, C4<0>; +L_0x2a78330 .delay (20000,20000,20000) L_0x2a78330/d; +v0x2887c40_0 .net "S", 0 0, L_0x2a78f40; 1 drivers +v0x2887d00_0 .alias "in0", 0 0, v0x2888360_0; +v0x2887da0_0 .alias "in1", 0 0, v0x2888830_0; +v0x2887e40_0 .net "nS", 0 0, L_0x2a78050; 1 drivers +v0x2887ec0_0 .net "out0", 0 0, L_0x2a78110; 1 drivers +v0x2887f60_0 .net "out1", 0 0, L_0x2a78220; 1 drivers +v0x2888040_0 .alias "outfinal", 0 0, v0x2888410_0; +S_0x28874f0 .scope module, "setSLTres2" "TwoInMux" 3 335, 3 109, S_0x2886e00; + .timescale -9 -12; +L_0x2a79e10/d .functor NOT 1, L_0x2aa3020, C4<0>, C4<0>, C4<0>; +L_0x2a79e10 .delay (10000,10000,10000) L_0x2a79e10/d; +L_0x2a79e70/d .functor AND 1, L_0x2a79970, L_0x2a79e10, C4<1>, C4<1>; +L_0x2a79e70 .delay (20000,20000,20000) L_0x2a79e70/d; +L_0x2a79f60/d .functor AND 1, C4<0>, L_0x2aa3020, C4<1>, C4<1>; +L_0x2a79f60 .delay (20000,20000,20000) L_0x2a79f60/d; +L_0x2a7a010/d .functor OR 1, L_0x2a79e70, L_0x2a79f60, C4<0>, C4<0>; +L_0x2a7a010 .delay (20000,20000,20000) L_0x2a7a010/d; +v0x28875e0_0 .alias "S", 0 0, v0x289f760_0; +v0x2887680_0 .net "in0", 0 0, L_0x2a79970; 1 drivers +v0x2887720_0 .net "in1", 0 0, C4<0>; 1 drivers +v0x28877c0_0 .net "nS", 0 0, L_0x2a79e10; 1 drivers +v0x2887840_0 .net "out0", 0 0, L_0x2a79e70; 1 drivers +v0x28878e0_0 .net "out1", 0 0, L_0x2a79f60; 1 drivers +v0x28879c0_0 .net "outfinal", 0 0, L_0x2a7a010; 1 drivers +S_0x2886f70 .scope module, "setSLTres3" "TwoInMux" 3 336, 3 109, S_0x2886e00; + .timescale -9 -12; +L_0x2a79c70/d .functor NOT 1, L_0x2aa3020, C4<0>, C4<0>, C4<0>; +L_0x2a79c70 .delay (10000,10000,10000) L_0x2a79c70/d; +L_0x2a75a30/d .functor AND 1, L_0x2a7a1f0, L_0x2a79c70, C4<1>, C4<1>; +L_0x2a75a30 .delay (20000,20000,20000) L_0x2a75a30/d; +L_0x2a7a600/d .functor AND 1, L_0x2a7a2e0, L_0x2aa3020, C4<1>, C4<1>; +L_0x2a7a600 .delay (20000,20000,20000) L_0x2a7a600/d; +L_0x2a7a6a0/d .functor OR 1, L_0x2a75a30, L_0x2a7a600, C4<0>, C4<0>; +L_0x2a7a6a0 .delay (20000,20000,20000) L_0x2a7a6a0/d; +v0x2887060_0 .alias "S", 0 0, v0x289f760_0; +v0x28870e0_0 .net "in0", 0 0, L_0x2a7a1f0; 1 drivers +v0x2887180_0 .net "in1", 0 0, L_0x2a7a2e0; 1 drivers +v0x2887220_0 .net "nS", 0 0, L_0x2a79c70; 1 drivers +v0x28872d0_0 .net "out0", 0 0, L_0x2a75a30; 1 drivers +v0x2887370_0 .net "out1", 0 0, L_0x2a7a600; 1 drivers +v0x2887450_0 .net "outfinal", 0 0, L_0x2a7a6a0; 1 drivers +S_0x2885180 .scope generate, "sltbits[13]" "sltbits[13]" 3 332, 3 332, S_0x2864a60; + .timescale -9 -12; +P_0x2884b98 .param/l "i" 3 332, +C4<01101>; +S_0x2885de0 .scope module, "attempt" "MiddleAddSubSLT" 3 334, 3 189, S_0x2885180; + .timescale -9 -12; +L_0x2a7a3d0/d .functor NOT 1, L_0x2a7aa10, C4<0>, C4<0>, C4<0>; +L_0x2a7a3d0 .delay (10000,10000,10000) L_0x2a7a3d0/d; +L_0x2a7b100/d .functor NOT 1, L_0x2a7b1a0, C4<0>, C4<0>, C4<0>; +L_0x2a7b100 .delay (10000,10000,10000) L_0x2a7b100/d; +L_0x2a7b240/d .functor AND 1, L_0x2a7b380, L_0x2a7b100, C4<1>, C4<1>; +L_0x2a7b240 .delay (20000,20000,20000) L_0x2a7b240/d; +L_0x2a7b420/d .functor XOR 1, L_0x2a7a970, L_0x2a7aed0, C4<0>, C4<0>; +L_0x2a7b420 .delay (40000,40000,40000) L_0x2a7b420/d; +L_0x2a7b510/d .functor XOR 1, L_0x2a7b420, L_0x2a7ab40, C4<0>, C4<0>; +L_0x2a7b510 .delay (40000,40000,40000) L_0x2a7b510/d; +L_0x2a7b600/d .functor AND 1, L_0x2a7a970, L_0x2a7aed0, C4<1>, C4<1>; +L_0x2a7b600 .delay (20000,20000,20000) L_0x2a7b600/d; +L_0x2a7b770/d .functor AND 1, L_0x2a7b420, L_0x2a7ab40, C4<1>, C4<1>; +L_0x2a7b770 .delay (20000,20000,20000) L_0x2a7b770/d; +L_0x2a7b860/d .functor OR 1, L_0x2a7b600, L_0x2a7b770, C4<0>, C4<0>; +L_0x2a7b860 .delay (20000,20000,20000) L_0x2a7b860/d; +v0x2886460_0 .net "A", 0 0, L_0x2a7a970; 1 drivers +v0x2886520_0 .net "AandB", 0 0, L_0x2a7b600; 1 drivers +v0x28865c0_0 .net "AddSubSLTSum", 0 0, L_0x2a7b510; 1 drivers +v0x2886660_0 .net "AxorB", 0 0, L_0x2a7b420; 1 drivers +v0x28866e0_0 .net "B", 0 0, L_0x2a7aa10; 1 drivers +v0x2886790_0 .net "BornB", 0 0, L_0x2a7aed0; 1 drivers +v0x2886850_0 .net "CINandAxorB", 0 0, L_0x2a7b770; 1 drivers +v0x28868d0_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x2886950_0 .net *"_s3", 0 0, L_0x2a7b1a0; 1 drivers +v0x28869d0_0 .net *"_s5", 0 0, L_0x2a7b380; 1 drivers +v0x2886a70_0 .net "carryin", 0 0, L_0x2a7ab40; 1 drivers +v0x2886b10_0 .net "carryout", 0 0, L_0x2a7b860; 1 drivers +v0x2886bb0_0 .net "nB", 0 0, L_0x2a7a3d0; 1 drivers +v0x2886c60_0 .net "nCmd2", 0 0, L_0x2a7b100; 1 drivers +v0x2886d60_0 .net "subtract", 0 0, L_0x2a7b240; 1 drivers +L_0x2a7b060 .part v0x2960210_0, 0, 1; +L_0x2a7b1a0 .part v0x2960210_0, 2, 1; +L_0x2a7b380 .part v0x2960210_0, 0, 1; +S_0x2885ed0 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x2885de0; + .timescale -9 -12; +L_0x2a7a5a0/d .functor NOT 1, L_0x2a7b060, C4<0>, C4<0>, C4<0>; +L_0x2a7a5a0 .delay (10000,10000,10000) L_0x2a7a5a0/d; +L_0x2a7acf0/d .functor AND 1, L_0x2a7aa10, L_0x2a7a5a0, C4<1>, C4<1>; +L_0x2a7acf0 .delay (20000,20000,20000) L_0x2a7acf0/d; +L_0x2a7ade0/d .functor AND 1, L_0x2a7a3d0, L_0x2a7b060, C4<1>, C4<1>; +L_0x2a7ade0 .delay (20000,20000,20000) L_0x2a7ade0/d; +L_0x2a7aed0/d .functor OR 1, L_0x2a7acf0, L_0x2a7ade0, C4<0>, C4<0>; +L_0x2a7aed0 .delay (20000,20000,20000) L_0x2a7aed0/d; +v0x2885fc0_0 .net "S", 0 0, L_0x2a7b060; 1 drivers +v0x2886080_0 .alias "in0", 0 0, v0x28866e0_0; +v0x2886120_0 .alias "in1", 0 0, v0x2886bb0_0; +v0x28861c0_0 .net "nS", 0 0, L_0x2a7a5a0; 1 drivers +v0x2886240_0 .net "out0", 0 0, L_0x2a7acf0; 1 drivers +v0x28862e0_0 .net "out1", 0 0, L_0x2a7ade0; 1 drivers +v0x28863c0_0 .alias "outfinal", 0 0, v0x2886790_0; +S_0x2885870 .scope module, "setSLTres2" "TwoInMux" 3 335, 3 109, S_0x2885180; + .timescale -9 -12; +L_0x2a7abe0/d .functor NOT 1, L_0x2aa3020, C4<0>, C4<0>, C4<0>; +L_0x2a7abe0 .delay (10000,10000,10000) L_0x2a7abe0/d; +L_0x2a7bfe0/d .functor AND 1, L_0x2a7c350, L_0x2a7abe0, C4<1>, C4<1>; +L_0x2a7bfe0 .delay (20000,20000,20000) L_0x2a7bfe0/d; +L_0x2a7c0d0/d .functor AND 1, C4<0>, L_0x2aa3020, C4<1>, C4<1>; +L_0x2a7c0d0 .delay (20000,20000,20000) L_0x2a7c0d0/d; +L_0x2a7c170/d .functor OR 1, L_0x2a7bfe0, L_0x2a7c0d0, C4<0>, C4<0>; +L_0x2a7c170 .delay (20000,20000,20000) L_0x2a7c170/d; +v0x2885960_0 .alias "S", 0 0, v0x289f760_0; +v0x2885a00_0 .net "in0", 0 0, L_0x2a7c350; 1 drivers +v0x2885aa0_0 .net "in1", 0 0, C4<0>; 1 drivers +v0x2885b40_0 .net "nS", 0 0, L_0x2a7abe0; 1 drivers +v0x2885bc0_0 .net "out0", 0 0, L_0x2a7bfe0; 1 drivers +v0x2885c60_0 .net "out1", 0 0, L_0x2a7c0d0; 1 drivers +v0x2885d40_0 .net "outfinal", 0 0, L_0x2a7c170; 1 drivers +S_0x28852f0 .scope module, "setSLTres3" "TwoInMux" 3 336, 3 109, S_0x2885180; + .timescale -9 -12; +L_0x2a7bc10/d .functor NOT 1, L_0x2aa3020, C4<0>, C4<0>, C4<0>; +L_0x2a7bc10 .delay (10000,10000,10000) L_0x2a7bc10/d; +L_0x2a7bd20/d .functor AND 1, L_0x2a7c9a0, L_0x2a7bc10, C4<1>, C4<1>; +L_0x2a7bd20 .delay (20000,20000,20000) L_0x2a7bd20/d; +L_0x2a7be30/d .functor AND 1, L_0x2a7c440, L_0x2aa3020, C4<1>, C4<1>; +L_0x2a7be30 .delay (20000,20000,20000) L_0x2a7be30/d; +L_0x2a7bed0/d .functor OR 1, L_0x2a7bd20, L_0x2a7be30, C4<0>, C4<0>; +L_0x2a7bed0 .delay (20000,20000,20000) L_0x2a7bed0/d; +v0x28853e0_0 .alias "S", 0 0, v0x289f760_0; +v0x2885460_0 .net "in0", 0 0, L_0x2a7c9a0; 1 drivers +v0x2885500_0 .net "in1", 0 0, L_0x2a7c440; 1 drivers +v0x28855a0_0 .net "nS", 0 0, L_0x2a7bc10; 1 drivers +v0x2885650_0 .net "out0", 0 0, L_0x2a7bd20; 1 drivers +v0x28856f0_0 .net "out1", 0 0, L_0x2a7be30; 1 drivers +v0x28857d0_0 .net "outfinal", 0 0, L_0x2a7bed0; 1 drivers +S_0x2883500 .scope generate, "sltbits[14]" "sltbits[14]" 3 332, 3 332, S_0x2864a60; + .timescale -9 -12; +P_0x2882df8 .param/l "i" 3 332, +C4<01110>; +S_0x2884160 .scope module, "attempt" "MiddleAddSubSLT" 3 334, 3 189, S_0x2883500; + .timescale -9 -12; +L_0x2a7c530/d .functor NOT 1, L_0x2a7cd10, C4<0>, C4<0>, C4<0>; +L_0x2a7c530 .delay (10000,10000,10000) L_0x2a7c530/d; +L_0x2a7d230/d .functor NOT 1, L_0x2a7d2d0, C4<0>, C4<0>, C4<0>; +L_0x2a7d230 .delay (10000,10000,10000) L_0x2a7d230/d; +L_0x2a7d370/d .functor AND 1, L_0x2a7d4b0, L_0x2a7d230, C4<1>, C4<1>; +L_0x2a7d370 .delay (20000,20000,20000) L_0x2a7d370/d; +L_0x2a7d550/d .functor XOR 1, L_0x2a7cc70, L_0x2a7d000, C4<0>, C4<0>; +L_0x2a7d550 .delay (40000,40000,40000) L_0x2a7d550/d; +L_0x2a7d640/d .functor XOR 1, L_0x2a7d550, L_0x2a7ce40, C4<0>, C4<0>; +L_0x2a7d640 .delay (40000,40000,40000) L_0x2a7d640/d; +L_0x2a7d730/d .functor AND 1, L_0x2a7cc70, L_0x2a7d000, C4<1>, C4<1>; +L_0x2a7d730 .delay (20000,20000,20000) L_0x2a7d730/d; +L_0x2a7d8a0/d .functor AND 1, L_0x2a7d550, L_0x2a7ce40, C4<1>, C4<1>; +L_0x2a7d8a0 .delay (20000,20000,20000) L_0x2a7d8a0/d; +L_0x2a7d990/d .functor OR 1, L_0x2a7d730, L_0x2a7d8a0, C4<0>, C4<0>; +L_0x2a7d990 .delay (20000,20000,20000) L_0x2a7d990/d; +v0x28847e0_0 .net "A", 0 0, L_0x2a7cc70; 1 drivers +v0x28848a0_0 .net "AandB", 0 0, L_0x2a7d730; 1 drivers +v0x2884940_0 .net "AddSubSLTSum", 0 0, L_0x2a7d640; 1 drivers +v0x28849e0_0 .net "AxorB", 0 0, L_0x2a7d550; 1 drivers +v0x2884a60_0 .net "B", 0 0, L_0x2a7cd10; 1 drivers +v0x2884b10_0 .net "BornB", 0 0, L_0x2a7d000; 1 drivers +v0x2884bd0_0 .net "CINandAxorB", 0 0, L_0x2a7d8a0; 1 drivers +v0x2884c50_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x2884cd0_0 .net *"_s3", 0 0, L_0x2a7d2d0; 1 drivers +v0x2884d50_0 .net *"_s5", 0 0, L_0x2a7d4b0; 1 drivers +v0x2884df0_0 .net "carryin", 0 0, L_0x2a7ce40; 1 drivers +v0x2884e90_0 .net "carryout", 0 0, L_0x2a7d990; 1 drivers +v0x2884f30_0 .net "nB", 0 0, L_0x2a7c530; 1 drivers +v0x2884fe0_0 .net "nCmd2", 0 0, L_0x2a7d230; 1 drivers +v0x28850e0_0 .net "subtract", 0 0, L_0x2a7d370; 1 drivers +L_0x2a7d190 .part v0x2960210_0, 0, 1; +L_0x2a7d2d0 .part v0x2960210_0, 2, 1; +L_0x2a7d4b0 .part v0x2960210_0, 0, 1; +S_0x2884250 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x2884160; + .timescale -9 -12; +L_0x2a7c6e0/d .functor NOT 1, L_0x2a7d190, C4<0>, C4<0>, C4<0>; +L_0x2a7c6e0 .delay (10000,10000,10000) L_0x2a7c6e0/d; +L_0x2a7c7a0/d .functor AND 1, L_0x2a7cd10, L_0x2a7c6e0, C4<1>, C4<1>; +L_0x2a7c7a0 .delay (20000,20000,20000) L_0x2a7c7a0/d; +L_0x2a7cf10/d .functor AND 1, L_0x2a7c530, L_0x2a7d190, C4<1>, C4<1>; +L_0x2a7cf10 .delay (20000,20000,20000) L_0x2a7cf10/d; +L_0x2a7d000/d .functor OR 1, L_0x2a7c7a0, L_0x2a7cf10, C4<0>, C4<0>; +L_0x2a7d000 .delay (20000,20000,20000) L_0x2a7d000/d; +v0x2884340_0 .net "S", 0 0, L_0x2a7d190; 1 drivers +v0x2884400_0 .alias "in0", 0 0, v0x2884a60_0; +v0x28844a0_0 .alias "in1", 0 0, v0x2884f30_0; +v0x2884540_0 .net "nS", 0 0, L_0x2a7c6e0; 1 drivers +v0x28845c0_0 .net "out0", 0 0, L_0x2a7c7a0; 1 drivers +v0x2884660_0 .net "out1", 0 0, L_0x2a7cf10; 1 drivers +v0x2884740_0 .alias "outfinal", 0 0, v0x2884b10_0; +S_0x2883bf0 .scope module, "setSLTres2" "TwoInMux" 3 335, 3 109, S_0x2883500; + .timescale -9 -12; +L_0x2a7e090/d .functor NOT 1, L_0x2aa3020, C4<0>, C4<0>, C4<0>; +L_0x2a7e090 .delay (10000,10000,10000) L_0x2a7e090/d; +L_0x2a7e0f0/d .functor AND 1, L_0x2a7dbe0, L_0x2a7e090, C4<1>, C4<1>; +L_0x2a7e0f0 .delay (20000,20000,20000) L_0x2a7e0f0/d; +L_0x2a7e1e0/d .functor AND 1, C4<0>, L_0x2aa3020, C4<1>, C4<1>; +L_0x2a7e1e0 .delay (20000,20000,20000) L_0x2a7e1e0/d; +L_0x2a7e280/d .functor OR 1, L_0x2a7e0f0, L_0x2a7e1e0, C4<0>, C4<0>; +L_0x2a7e280 .delay (20000,20000,20000) L_0x2a7e280/d; +v0x2883ce0_0 .alias "S", 0 0, v0x289f760_0; +v0x2883d80_0 .net "in0", 0 0, L_0x2a7dbe0; 1 drivers +v0x2883e20_0 .net "in1", 0 0, C4<0>; 1 drivers +v0x2883ec0_0 .net "nS", 0 0, L_0x2a7e090; 1 drivers +v0x2883f40_0 .net "out0", 0 0, L_0x2a7e0f0; 1 drivers +v0x2883fe0_0 .net "out1", 0 0, L_0x2a7e1e0; 1 drivers +v0x28840c0_0 .net "outfinal", 0 0, L_0x2a7e280; 1 drivers +S_0x2883670 .scope module, "setSLTres3" "TwoInMux" 3 336, 3 109, S_0x2883500; + .timescale -9 -12; +L_0x2a7def0/d .functor NOT 1, L_0x2aa3020, C4<0>, C4<0>, C4<0>; +L_0x2a7def0 .delay (10000,10000,10000) L_0x2a7def0/d; +L_0x2a7e020/d .functor AND 1, L_0x2a7e490, L_0x2a7def0, C4<1>, C4<1>; +L_0x2a7e020 .delay (20000,20000,20000) L_0x2a7e020/d; +L_0x2a79b80/d .functor AND 1, L_0x2a7e530, L_0x2aa3020, C4<1>, C4<1>; +L_0x2a79b80 .delay (20000,20000,20000) L_0x2a79b80/d; +L_0x2a7e950/d .functor OR 1, L_0x2a7e020, L_0x2a79b80, C4<0>, C4<0>; +L_0x2a7e950 .delay (20000,20000,20000) L_0x2a7e950/d; +v0x2883760_0 .alias "S", 0 0, v0x289f760_0; +v0x28837e0_0 .net "in0", 0 0, L_0x2a7e490; 1 drivers +v0x2883880_0 .net "in1", 0 0, L_0x2a7e530; 1 drivers +v0x2883920_0 .net "nS", 0 0, L_0x2a7def0; 1 drivers +v0x28839d0_0 .net "out0", 0 0, L_0x2a7e020; 1 drivers +v0x2883a70_0 .net "out1", 0 0, L_0x2a79b80; 1 drivers +v0x2883b50_0 .net "outfinal", 0 0, L_0x2a7e950; 1 drivers +S_0x2881660 .scope generate, "sltbits[15]" "sltbits[15]" 3 332, 3 332, S_0x2864a60; + .timescale -9 -12; +P_0x2881078 .param/l "i" 3 332, +C4<01111>; +S_0x28823c0 .scope module, "attempt" "MiddleAddSubSLT" 3 334, 3 189, S_0x2881660; + .timescale -9 -12; +L_0x2a7e620/d .functor NOT 1, L_0x2a7ecc0, C4<0>, C4<0>, C4<0>; +L_0x2a7e620 .delay (10000,10000,10000) L_0x2a7e620/d; +L_0x2a7f3e0/d .functor NOT 1, L_0x2a7f4a0, C4<0>, C4<0>, C4<0>; +L_0x2a7f3e0 .delay (10000,10000,10000) L_0x2a7f3e0/d; +L_0x2a7f540/d .functor AND 1, L_0x2a7f680, L_0x2a7f3e0, C4<1>, C4<1>; +L_0x2a7f540 .delay (20000,20000,20000) L_0x2a7f540/d; +L_0x2a7f720/d .functor XOR 1, L_0x2a7ec20, L_0x2a7f170, C4<0>, C4<0>; +L_0x2a7f720 .delay (40000,40000,40000) L_0x2a7f720/d; +L_0x2a7f810/d .functor XOR 1, L_0x2a7f720, L_0x2a7edf0, C4<0>, C4<0>; +L_0x2a7f810 .delay (40000,40000,40000) L_0x2a7f810/d; +L_0x2a7f930/d .functor AND 1, L_0x2a7ec20, L_0x2a7f170, C4<1>, C4<1>; +L_0x2a7f930 .delay (20000,20000,20000) L_0x2a7f930/d; +L_0x2a7fad0/d .functor AND 1, L_0x2a7f720, L_0x2a7edf0, C4<1>, C4<1>; +L_0x2a7fad0 .delay (20000,20000,20000) L_0x2a7fad0/d; +L_0x2a7fbc0/d .functor OR 1, L_0x2a7f930, L_0x2a7fad0, C4<0>, C4<0>; +L_0x2a7fbc0 .delay (20000,20000,20000) L_0x2a7fbc0/d; +v0x2882a40_0 .net "A", 0 0, L_0x2a7ec20; 1 drivers +v0x2882b00_0 .net "AandB", 0 0, L_0x2a7f930; 1 drivers +v0x2882ba0_0 .net "AddSubSLTSum", 0 0, L_0x2a7f810; 1 drivers +v0x2882c40_0 .net "AxorB", 0 0, L_0x2a7f720; 1 drivers +v0x2882cc0_0 .net "B", 0 0, L_0x2a7ecc0; 1 drivers +v0x2882d70_0 .net "BornB", 0 0, L_0x2a7f170; 1 drivers +v0x2882e30_0 .net "CINandAxorB", 0 0, L_0x2a7fad0; 1 drivers +v0x2882eb0_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x2882f80_0 .net *"_s3", 0 0, L_0x2a7f4a0; 1 drivers +v0x2883000_0 .net *"_s5", 0 0, L_0x2a7f680; 1 drivers +v0x2883100_0 .net "carryin", 0 0, L_0x2a7edf0; 1 drivers +v0x28831a0_0 .net "carryout", 0 0, L_0x2a7fbc0; 1 drivers +v0x28832b0_0 .net "nB", 0 0, L_0x2a7e620; 1 drivers +v0x2883360_0 .net "nCmd2", 0 0, L_0x2a7f3e0; 1 drivers +v0x2883460_0 .net "subtract", 0 0, L_0x2a7f540; 1 drivers +L_0x2a7f340 .part v0x2960210_0, 0, 1; +L_0x2a7f4a0 .part v0x2960210_0, 2, 1; +L_0x2a7f680 .part v0x2960210_0, 0, 1; +S_0x28824b0 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x28823c0; + .timescale -9 -12; +L_0x2a7e7f0/d .functor NOT 1, L_0x2a7f340, C4<0>, C4<0>, C4<0>; +L_0x2a7e7f0 .delay (10000,10000,10000) L_0x2a7e7f0/d; +L_0x2a7e8b0/d .functor AND 1, L_0x2a7ecc0, L_0x2a7e7f0, C4<1>, C4<1>; +L_0x2a7e8b0 .delay (20000,20000,20000) L_0x2a7e8b0/d; +L_0x2a7f060/d .functor AND 1, L_0x2a7e620, L_0x2a7f340, C4<1>, C4<1>; +L_0x2a7f060 .delay (20000,20000,20000) L_0x2a7f060/d; +L_0x2a7f170/d .functor OR 1, L_0x2a7e8b0, L_0x2a7f060, C4<0>, C4<0>; +L_0x2a7f170 .delay (20000,20000,20000) L_0x2a7f170/d; +v0x28825a0_0 .net "S", 0 0, L_0x2a7f340; 1 drivers +v0x2882660_0 .alias "in0", 0 0, v0x2882cc0_0; +v0x2882700_0 .alias "in1", 0 0, v0x28832b0_0; +v0x28827a0_0 .net "nS", 0 0, L_0x2a7e7f0; 1 drivers +v0x2882820_0 .net "out0", 0 0, L_0x2a7e8b0; 1 drivers +v0x28828c0_0 .net "out1", 0 0, L_0x2a7f060; 1 drivers +v0x28829a0_0 .alias "outfinal", 0 0, v0x2882d70_0; +S_0x2881ed0 .scope module, "setSLTres2" "TwoInMux" 3 335, 3 109, S_0x2881660; + .timescale -9 -12; +L_0x2a7ee90/d .functor NOT 1, L_0x2aa3020, C4<0>, C4<0>, C4<0>; +L_0x2a7ee90 .delay (10000,10000,10000) L_0x2a7ee90/d; +L_0x2a7ef30/d .functor AND 1, L_0x2a806e0, L_0x2a7ee90, C4<1>, C4<1>; +L_0x2a7ef30 .delay (20000,20000,20000) L_0x2a7ef30/d; +L_0x2a80460/d .functor AND 1, C4<0>, L_0x2aa3020, C4<1>, C4<1>; +L_0x2a80460 .delay (20000,20000,20000) L_0x2a80460/d; +L_0x2a80500/d .functor OR 1, L_0x2a7ef30, L_0x2a80460, C4<0>, C4<0>; +L_0x2a80500 .delay (20000,20000,20000) L_0x2a80500/d; +v0x2881fc0_0 .alias "S", 0 0, v0x289f760_0; +v0x2882040_0 .net "in0", 0 0, L_0x2a806e0; 1 drivers +v0x28820c0_0 .net "in1", 0 0, C4<0>; 1 drivers +v0x2882140_0 .net "nS", 0 0, L_0x2a7ee90; 1 drivers +v0x28821c0_0 .net "out0", 0 0, L_0x2a7ef30; 1 drivers +v0x2882240_0 .net "out1", 0 0, L_0x2a80460; 1 drivers +v0x2882320_0 .net "outfinal", 0 0, L_0x2a80500; 1 drivers +S_0x28817d0 .scope module, "setSLTres3" "TwoInMux" 3 336, 3 109, S_0x2881660; + .timescale -9 -12; +L_0x2a7ff90/d .functor NOT 1, L_0x2aa3020, C4<0>, C4<0>, C4<0>; +L_0x2a7ff90 .delay (10000,10000,10000) L_0x2a7ff90/d; +L_0x2a800a0/d .functor AND 1, L_0x2a80d90, L_0x2a7ff90, C4<1>, C4<1>; +L_0x2a800a0 .delay (20000,20000,20000) L_0x2a800a0/d; +L_0x2a801b0/d .functor AND 1, L_0x2a807d0, L_0x2aa3020, C4<1>, C4<1>; +L_0x2a801b0 .delay (20000,20000,20000) L_0x2a801b0/d; +L_0x2a80250/d .functor OR 1, L_0x2a800a0, L_0x2a801b0, C4<0>, C4<0>; +L_0x2a80250 .delay (20000,20000,20000) L_0x2a80250/d; +v0x28818c0_0 .alias "S", 0 0, v0x289f760_0; +v0x2873440_0 .net "in0", 0 0, L_0x2a80d90; 1 drivers +v0x28734e0_0 .net "in1", 0 0, L_0x2a807d0; 1 drivers +v0x2873580_0 .net "nS", 0 0, L_0x2a7ff90; 1 drivers +v0x2881d50_0 .net "out0", 0 0, L_0x2a800a0; 1 drivers +v0x2881dd0_0 .net "out1", 0 0, L_0x2a801b0; 1 drivers +v0x2881e50_0 .net "outfinal", 0 0, L_0x2a80250; 1 drivers +S_0x287f9e0 .scope generate, "sltbits[16]" "sltbits[16]" 3 332, 3 332, S_0x2864a60; + .timescale -9 -12; +P_0x287f3f8 .param/l "i" 3 332, +C4<010000>; +S_0x2880640 .scope module, "attempt" "MiddleAddSubSLT" 3 334, 3 189, S_0x287f9e0; + .timescale -9 -12; +L_0x2a808c0/d .functor NOT 1, L_0x2a810b0, C4<0>, C4<0>, C4<0>; +L_0x2a808c0 .delay (10000,10000,10000) L_0x2a808c0/d; +L_0x2a81620/d .functor NOT 1, L_0x2a816c0, C4<0>, C4<0>, C4<0>; +L_0x2a81620 .delay (10000,10000,10000) L_0x2a81620/d; +L_0x2a81760/d .functor AND 1, L_0x2a818a0, L_0x2a81620, C4<1>, C4<1>; +L_0x2a81760 .delay (20000,20000,20000) L_0x2a81760/d; +L_0x2a81940/d .functor XOR 1, L_0x2a81010, L_0x2a813f0, C4<0>, C4<0>; +L_0x2a81940 .delay (40000,40000,40000) L_0x2a81940/d; +L_0x2a81a30/d .functor XOR 1, L_0x2a81940, L_0x2a811e0, C4<0>, C4<0>; +L_0x2a81a30 .delay (40000,40000,40000) L_0x2a81a30/d; +L_0x2a81b20/d .functor AND 1, L_0x2a81010, L_0x2a813f0, C4<1>, C4<1>; +L_0x2a81b20 .delay (20000,20000,20000) L_0x2a81b20/d; +L_0x2a81cc0/d .functor AND 1, L_0x2a81940, L_0x2a811e0, C4<1>, C4<1>; +L_0x2a81cc0 .delay (20000,20000,20000) L_0x2a81cc0/d; +L_0x2a81db0/d .functor OR 1, L_0x2a81b20, L_0x2a81cc0, C4<0>, C4<0>; +L_0x2a81db0 .delay (20000,20000,20000) L_0x2a81db0/d; +v0x2880cc0_0 .net "A", 0 0, L_0x2a81010; 1 drivers +v0x2880d80_0 .net "AandB", 0 0, L_0x2a81b20; 1 drivers +v0x2880e20_0 .net "AddSubSLTSum", 0 0, L_0x2a81a30; 1 drivers +v0x2880ec0_0 .net "AxorB", 0 0, L_0x2a81940; 1 drivers +v0x2880f40_0 .net "B", 0 0, L_0x2a810b0; 1 drivers +v0x2880ff0_0 .net "BornB", 0 0, L_0x2a813f0; 1 drivers +v0x28810b0_0 .net "CINandAxorB", 0 0, L_0x2a81cc0; 1 drivers +v0x2881130_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x28811b0_0 .net *"_s3", 0 0, L_0x2a816c0; 1 drivers +v0x2881230_0 .net *"_s5", 0 0, L_0x2a818a0; 1 drivers +v0x28812d0_0 .net "carryin", 0 0, L_0x2a811e0; 1 drivers +v0x2881370_0 .net "carryout", 0 0, L_0x2a81db0; 1 drivers +v0x2881410_0 .net "nB", 0 0, L_0x2a808c0; 1 drivers +v0x28814c0_0 .net "nCmd2", 0 0, L_0x2a81620; 1 drivers +v0x28815c0_0 .net "subtract", 0 0, L_0x2a81760; 1 drivers +L_0x2a81580 .part v0x2960210_0, 0, 1; +L_0x2a816c0 .part v0x2960210_0, 2, 1; +L_0x2a818a0 .part v0x2960210_0, 0, 1; +S_0x2880730 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x2880640; + .timescale -9 -12; +L_0x2a80a90/d .functor NOT 1, L_0x2a81580, C4<0>, C4<0>, C4<0>; +L_0x2a80a90 .delay (10000,10000,10000) L_0x2a80a90/d; +L_0x2a80b50/d .functor AND 1, L_0x2a810b0, L_0x2a80a90, C4<1>, C4<1>; +L_0x2a80b50 .delay (20000,20000,20000) L_0x2a80b50/d; +L_0x2a80c60/d .functor AND 1, L_0x2a808c0, L_0x2a81580, C4<1>, C4<1>; +L_0x2a80c60 .delay (20000,20000,20000) L_0x2a80c60/d; +L_0x2a813f0/d .functor OR 1, L_0x2a80b50, L_0x2a80c60, C4<0>, C4<0>; +L_0x2a813f0 .delay (20000,20000,20000) L_0x2a813f0/d; +v0x2880820_0 .net "S", 0 0, L_0x2a81580; 1 drivers +v0x28808e0_0 .alias "in0", 0 0, v0x2880f40_0; +v0x2880980_0 .alias "in1", 0 0, v0x2881410_0; +v0x2880a20_0 .net "nS", 0 0, L_0x2a80a90; 1 drivers +v0x2880aa0_0 .net "out0", 0 0, L_0x2a80b50; 1 drivers +v0x2880b40_0 .net "out1", 0 0, L_0x2a80c60; 1 drivers +v0x2880c20_0 .alias "outfinal", 0 0, v0x2880ff0_0; +S_0x28800d0 .scope module, "setSLTres2" "TwoInMux" 3 335, 3 109, S_0x287f9e0; + .timescale -9 -12; +L_0x2a81280/d .functor NOT 1, L_0x2aa3020, C4<0>, C4<0>, C4<0>; +L_0x2a81280 .delay (10000,10000,10000) L_0x2a81280/d; +L_0x2a71510/d .functor AND 1, L_0x2a82000, L_0x2a81280, C4<1>, C4<1>; +L_0x2a71510 .delay (20000,20000,20000) L_0x2a71510/d; +L_0x2a715e0/d .functor AND 1, C4<0>, L_0x2aa3020, C4<1>, C4<1>; +L_0x2a715e0 .delay (20000,20000,20000) L_0x2a715e0/d; +L_0x2a71680/d .functor OR 1, L_0x2a71510, L_0x2a715e0, C4<0>, C4<0>; +L_0x2a71680 .delay (20000,20000,20000) L_0x2a71680/d; +v0x28801c0_0 .alias "S", 0 0, v0x289f760_0; +v0x2880260_0 .net "in0", 0 0, L_0x2a82000; 1 drivers +v0x2880300_0 .net "in1", 0 0, C4<0>; 1 drivers +v0x28803a0_0 .net "nS", 0 0, L_0x2a81280; 1 drivers +v0x2880420_0 .net "out0", 0 0, L_0x2a71510; 1 drivers +v0x28804c0_0 .net "out1", 0 0, L_0x2a715e0; 1 drivers +v0x28805a0_0 .net "outfinal", 0 0, L_0x2a71680; 1 drivers +S_0x287fb50 .scope module, "setSLTres3" "TwoInMux" 3 336, 3 109, S_0x287f9e0; + .timescale -9 -12; +L_0x2a7dd60/d .functor NOT 1, L_0x2aa3020, C4<0>, C4<0>, C4<0>; +L_0x2a7dd60 .delay (10000,10000,10000) L_0x2a7dd60/d; +L_0x2a7de50/d .functor AND 1, L_0x2a82ab0, L_0x2a7dd60, C4<1>, C4<1>; +L_0x2a7de50 .delay (20000,20000,20000) L_0x2a7de50/d; +L_0x2a83070/d .functor AND 1, L_0x2a82ba0, L_0x2aa3020, C4<1>, C4<1>; +L_0x2a83070 .delay (20000,20000,20000) L_0x2a83070/d; +L_0x2a83110/d .functor OR 1, L_0x2a7de50, L_0x2a83070, C4<0>, C4<0>; +L_0x2a83110 .delay (20000,20000,20000) L_0x2a83110/d; +v0x287fc40_0 .alias "S", 0 0, v0x289f760_0; +v0x287fcc0_0 .net "in0", 0 0, L_0x2a82ab0; 1 drivers +v0x287fd60_0 .net "in1", 0 0, L_0x2a82ba0; 1 drivers +v0x287fe00_0 .net "nS", 0 0, L_0x2a7dd60; 1 drivers +v0x287feb0_0 .net "out0", 0 0, L_0x2a7de50; 1 drivers +v0x287ff50_0 .net "out1", 0 0, L_0x2a83070; 1 drivers +v0x2880030_0 .net "outfinal", 0 0, L_0x2a83110; 1 drivers +S_0x287dd60 .scope generate, "sltbits[17]" "sltbits[17]" 3 332, 3 332, S_0x2864a60; + .timescale -9 -12; +P_0x287d778 .param/l "i" 3 332, +C4<010001>; +S_0x287e9c0 .scope module, "attempt" "MiddleAddSubSLT" 3 334, 3 189, S_0x287dd60; + .timescale -9 -12; +L_0x2a82c90/d .functor NOT 1, L_0x2a83480, C4<0>, C4<0>, C4<0>; +L_0x2a82c90 .delay (10000,10000,10000) L_0x2a82c90/d; +L_0x2a83bd0/d .functor NOT 1, L_0x2a83c90, C4<0>, C4<0>, C4<0>; +L_0x2a83bd0 .delay (10000,10000,10000) L_0x2a83bd0/d; +L_0x2a83d30/d .functor AND 1, L_0x2a83e70, L_0x2a83bd0, C4<1>, C4<1>; +L_0x2a83d30 .delay (20000,20000,20000) L_0x2a83d30/d; +L_0x2a83f10/d .functor XOR 1, L_0x2a833e0, L_0x2a83980, C4<0>, C4<0>; +L_0x2a83f10 .delay (40000,40000,40000) L_0x2a83f10/d; +L_0x2a84000/d .functor XOR 1, L_0x2a83f10, L_0x2a835b0, C4<0>, C4<0>; +L_0x2a84000 .delay (40000,40000,40000) L_0x2a84000/d; +L_0x2a84120/d .functor AND 1, L_0x2a833e0, L_0x2a83980, C4<1>, C4<1>; +L_0x2a84120 .delay (20000,20000,20000) L_0x2a84120/d; +L_0x2a842c0/d .functor AND 1, L_0x2a83f10, L_0x2a835b0, C4<1>, C4<1>; +L_0x2a842c0 .delay (20000,20000,20000) L_0x2a842c0/d; +L_0x2a843b0/d .functor OR 1, L_0x2a84120, L_0x2a842c0, C4<0>, C4<0>; +L_0x2a843b0 .delay (20000,20000,20000) L_0x2a843b0/d; +v0x287f040_0 .net "A", 0 0, L_0x2a833e0; 1 drivers +v0x287f100_0 .net "AandB", 0 0, L_0x2a84120; 1 drivers +v0x287f1a0_0 .net "AddSubSLTSum", 0 0, L_0x2a84000; 1 drivers +v0x287f240_0 .net "AxorB", 0 0, L_0x2a83f10; 1 drivers +v0x287f2c0_0 .net "B", 0 0, L_0x2a83480; 1 drivers +v0x287f370_0 .net "BornB", 0 0, L_0x2a83980; 1 drivers +v0x287f430_0 .net "CINandAxorB", 0 0, L_0x2a842c0; 1 drivers +v0x287f4b0_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x287f530_0 .net *"_s3", 0 0, L_0x2a83c90; 1 drivers +v0x287f5b0_0 .net *"_s5", 0 0, L_0x2a83e70; 1 drivers +v0x287f650_0 .net "carryin", 0 0, L_0x2a835b0; 1 drivers +v0x287f6f0_0 .net "carryout", 0 0, L_0x2a843b0; 1 drivers +v0x287f790_0 .net "nB", 0 0, L_0x2a82c90; 1 drivers +v0x287f840_0 .net "nCmd2", 0 0, L_0x2a83bd0; 1 drivers +v0x287f940_0 .net "subtract", 0 0, L_0x2a83d30; 1 drivers +L_0x2a83b30 .part v0x2960210_0, 0, 1; +L_0x2a83c90 .part v0x2960210_0, 2, 1; +L_0x2a83e70 .part v0x2960210_0, 0, 1; +S_0x287eab0 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x287e9c0; + .timescale -9 -12; +L_0x2a82e60/d .functor NOT 1, L_0x2a83b30, C4<0>, C4<0>, C4<0>; +L_0x2a82e60 .delay (10000,10000,10000) L_0x2a82e60/d; +L_0x2a82f20/d .functor AND 1, L_0x2a83480, L_0x2a82e60, C4<1>, C4<1>; +L_0x2a82f20 .delay (20000,20000,20000) L_0x2a82f20/d; +L_0x2a838d0/d .functor AND 1, L_0x2a82c90, L_0x2a83b30, C4<1>, C4<1>; +L_0x2a838d0 .delay (20000,20000,20000) L_0x2a838d0/d; +L_0x2a83980/d .functor OR 1, L_0x2a82f20, L_0x2a838d0, C4<0>, C4<0>; +L_0x2a83980 .delay (20000,20000,20000) L_0x2a83980/d; +v0x287eba0_0 .net "S", 0 0, L_0x2a83b30; 1 drivers +v0x287ec60_0 .alias "in0", 0 0, v0x287f2c0_0; +v0x287ed00_0 .alias "in1", 0 0, v0x287f790_0; +v0x287eda0_0 .net "nS", 0 0, L_0x2a82e60; 1 drivers +v0x287ee20_0 .net "out0", 0 0, L_0x2a82f20; 1 drivers +v0x287eec0_0 .net "out1", 0 0, L_0x2a838d0; 1 drivers +v0x287efa0_0 .alias "outfinal", 0 0, v0x287f370_0; +S_0x287e450 .scope module, "setSLTres2" "TwoInMux" 3 335, 3 109, S_0x287dd60; + .timescale -9 -12; +L_0x2a83650/d .functor NOT 1, L_0x2aa3020, C4<0>, C4<0>, C4<0>; +L_0x2a83650 .delay (10000,10000,10000) L_0x2a83650/d; +L_0x2a836d0/d .functor AND 1, L_0x2a60280, L_0x2a83650, C4<1>, C4<1>; +L_0x2a836d0 .delay (20000,20000,20000) L_0x2a836d0/d; +L_0x2a837e0/d .functor AND 1, C4<0>, L_0x2aa3020, C4<1>, C4<1>; +L_0x2a837e0 .delay (20000,20000,20000) L_0x2a837e0/d; +L_0x2a600a0/d .functor OR 1, L_0x2a836d0, L_0x2a837e0, C4<0>, C4<0>; +L_0x2a600a0 .delay (20000,20000,20000) L_0x2a600a0/d; +v0x287e540_0 .alias "S", 0 0, v0x289f760_0; +v0x287e5e0_0 .net "in0", 0 0, L_0x2a60280; 1 drivers +v0x287e680_0 .net "in1", 0 0, C4<0>; 1 drivers +v0x287e720_0 .net "nS", 0 0, L_0x2a83650; 1 drivers +v0x287e7a0_0 .net "out0", 0 0, L_0x2a836d0; 1 drivers +v0x287e840_0 .net "out1", 0 0, L_0x2a837e0; 1 drivers +v0x287e920_0 .net "outfinal", 0 0, L_0x2a600a0; 1 drivers +S_0x287ded0 .scope module, "setSLTres3" "TwoInMux" 3 336, 3 109, S_0x287dd60; + .timescale -9 -12; +L_0x2a60400/d .functor NOT 1, L_0x2aa3020, C4<0>, C4<0>, C4<0>; +L_0x2a60400 .delay (10000,10000,10000) L_0x2a60400/d; +L_0x2a60530/d .functor AND 1, L_0x2a84790, L_0x2a60400, C4<1>, C4<1>; +L_0x2a60530 .delay (20000,20000,20000) L_0x2a60530/d; +L_0x2a60640/d .functor AND 1, L_0x2a84880, L_0x2aa3020, C4<1>, C4<1>; +L_0x2a60640 .delay (20000,20000,20000) L_0x2a60640/d; +L_0x2a606e0/d .functor OR 1, L_0x2a60530, L_0x2a60640, C4<0>, C4<0>; +L_0x2a606e0 .delay (20000,20000,20000) L_0x2a606e0/d; +v0x287dfc0_0 .alias "S", 0 0, v0x289f760_0; +v0x287e040_0 .net "in0", 0 0, L_0x2a84790; 1 drivers +v0x287e0e0_0 .net "in1", 0 0, L_0x2a84880; 1 drivers +v0x287e180_0 .net "nS", 0 0, L_0x2a60400; 1 drivers +v0x287e230_0 .net "out0", 0 0, L_0x2a60530; 1 drivers +v0x287e2d0_0 .net "out1", 0 0, L_0x2a60640; 1 drivers +v0x287e3b0_0 .net "outfinal", 0 0, L_0x2a606e0; 1 drivers +S_0x287c0e0 .scope generate, "sltbits[18]" "sltbits[18]" 3 332, 3 332, S_0x2864a60; + .timescale -9 -12; +P_0x287baf8 .param/l "i" 3 332, +C4<010010>; +S_0x287cd40 .scope module, "attempt" "MiddleAddSubSLT" 3 334, 3 189, S_0x287c0e0; + .timescale -9 -12; +L_0x2a84970/d .functor NOT 1, L_0x2a85f40, C4<0>, C4<0>, C4<0>; +L_0x2a84970 .delay (10000,10000,10000) L_0x2a84970/d; +L_0x2a86600/d .functor NOT 1, L_0x2a866c0, C4<0>, C4<0>, C4<0>; +L_0x2a86600 .delay (10000,10000,10000) L_0x2a86600/d; +L_0x2a86760/d .functor AND 1, L_0x2a868a0, L_0x2a86600, C4<1>, C4<1>; +L_0x2a86760 .delay (20000,20000,20000) L_0x2a86760/d; +L_0x2a86940/d .functor XOR 1, L_0x2a85ea0, L_0x2a86390, C4<0>, C4<0>; +L_0x2a86940 .delay (40000,40000,40000) L_0x2a86940/d; +L_0x2a86a30/d .functor XOR 1, L_0x2a86940, L_0x2a86070, C4<0>, C4<0>; +L_0x2a86a30 .delay (40000,40000,40000) L_0x2a86a30/d; +L_0x2a86b20/d .functor AND 1, L_0x2a85ea0, L_0x2a86390, C4<1>, C4<1>; +L_0x2a86b20 .delay (20000,20000,20000) L_0x2a86b20/d; +L_0x2a86c90/d .functor AND 1, L_0x2a86940, L_0x2a86070, C4<1>, C4<1>; +L_0x2a86c90 .delay (20000,20000,20000) L_0x2a86c90/d; +L_0x2a86d80/d .functor OR 1, L_0x2a86b20, L_0x2a86c90, C4<0>, C4<0>; +L_0x2a86d80 .delay (20000,20000,20000) L_0x2a86d80/d; +v0x287d3c0_0 .net "A", 0 0, L_0x2a85ea0; 1 drivers +v0x287d480_0 .net "AandB", 0 0, L_0x2a86b20; 1 drivers +v0x287d520_0 .net "AddSubSLTSum", 0 0, L_0x2a86a30; 1 drivers +v0x287d5c0_0 .net "AxorB", 0 0, L_0x2a86940; 1 drivers +v0x287d640_0 .net "B", 0 0, L_0x2a85f40; 1 drivers +v0x287d6f0_0 .net "BornB", 0 0, L_0x2a86390; 1 drivers +v0x287d7b0_0 .net "CINandAxorB", 0 0, L_0x2a86c90; 1 drivers +v0x287d830_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x287d8b0_0 .net *"_s3", 0 0, L_0x2a866c0; 1 drivers +v0x287d930_0 .net *"_s5", 0 0, L_0x2a868a0; 1 drivers +v0x287d9d0_0 .net "carryin", 0 0, L_0x2a86070; 1 drivers +v0x287da70_0 .net "carryout", 0 0, L_0x2a86d80; 1 drivers +v0x287db10_0 .net "nB", 0 0, L_0x2a84970; 1 drivers +v0x287dbc0_0 .net "nCmd2", 0 0, L_0x2a86600; 1 drivers +v0x287dcc0_0 .net "subtract", 0 0, L_0x2a86760; 1 drivers +L_0x2a86560 .part v0x2960210_0, 0, 1; +L_0x2a866c0 .part v0x2960210_0, 2, 1; +L_0x2a868a0 .part v0x2960210_0, 0, 1; +S_0x287ce30 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x287cd40; + .timescale -9 -12; +L_0x2a84b40/d .functor NOT 1, L_0x2a86560, C4<0>, C4<0>, C4<0>; +L_0x2a84b40 .delay (10000,10000,10000) L_0x2a84b40/d; +L_0x2a84c00/d .functor AND 1, L_0x2a85f40, L_0x2a84b40, C4<1>, C4<1>; +L_0x2a84c00 .delay (20000,20000,20000) L_0x2a84c00/d; +L_0x2a862a0/d .functor AND 1, L_0x2a84970, L_0x2a86560, C4<1>, C4<1>; +L_0x2a862a0 .delay (20000,20000,20000) L_0x2a862a0/d; +L_0x2a86390/d .functor OR 1, L_0x2a84c00, L_0x2a862a0, C4<0>, C4<0>; +L_0x2a86390 .delay (20000,20000,20000) L_0x2a86390/d; +v0x287cf20_0 .net "S", 0 0, L_0x2a86560; 1 drivers +v0x287cfe0_0 .alias "in0", 0 0, v0x287d640_0; +v0x287d080_0 .alias "in1", 0 0, v0x287db10_0; +v0x287d120_0 .net "nS", 0 0, L_0x2a84b40; 1 drivers +v0x287d1a0_0 .net "out0", 0 0, L_0x2a84c00; 1 drivers +v0x287d240_0 .net "out1", 0 0, L_0x2a862a0; 1 drivers +v0x287d320_0 .alias "outfinal", 0 0, v0x287d6f0_0; +S_0x287c7d0 .scope module, "setSLTres2" "TwoInMux" 3 335, 3 109, S_0x287c0e0; + .timescale -9 -12; +L_0x2a86110/d .functor NOT 1, L_0x2aa3020, C4<0>, C4<0>, C4<0>; +L_0x2a86110 .delay (10000,10000,10000) L_0x2a86110/d; +L_0x2a861b0/d .functor AND 1, L_0x2a86fd0, L_0x2a86110, C4<1>, C4<1>; +L_0x2a861b0 .delay (20000,20000,20000) L_0x2a861b0/d; +L_0x2a87630/d .functor AND 1, C4<0>, L_0x2aa3020, C4<1>, C4<1>; +L_0x2a87630 .delay (20000,20000,20000) L_0x2a87630/d; +L_0x2a876d0/d .functor OR 1, L_0x2a861b0, L_0x2a87630, C4<0>, C4<0>; +L_0x2a876d0 .delay (20000,20000,20000) L_0x2a876d0/d; +v0x287c8c0_0 .alias "S", 0 0, v0x289f760_0; +v0x287c960_0 .net "in0", 0 0, L_0x2a86fd0; 1 drivers +v0x287ca00_0 .net "in1", 0 0, C4<0>; 1 drivers +v0x287caa0_0 .net "nS", 0 0, L_0x2a86110; 1 drivers +v0x287cb20_0 .net "out0", 0 0, L_0x2a861b0; 1 drivers +v0x287cbc0_0 .net "out1", 0 0, L_0x2a87630; 1 drivers +v0x287cca0_0 .net "outfinal", 0 0, L_0x2a876d0; 1 drivers +S_0x287c250 .scope module, "setSLTres3" "TwoInMux" 3 336, 3 109, S_0x287c0e0; + .timescale -9 -12; +L_0x2a87300/d .functor NOT 1, L_0x2aa3020, C4<0>, C4<0>, C4<0>; +L_0x2a87300 .delay (10000,10000,10000) L_0x2a87300/d; +L_0x2a87410/d .functor AND 1, L_0x2a878b0, L_0x2a87300, C4<1>, C4<1>; +L_0x2a87410 .delay (20000,20000,20000) L_0x2a87410/d; +L_0x2a87520/d .functor AND 1, L_0x2a879a0, L_0x2aa3020, C4<1>, C4<1>; +L_0x2a87520 .delay (20000,20000,20000) L_0x2a87520/d; +L_0x2a71b60/d .functor OR 1, L_0x2a87410, L_0x2a87520, C4<0>, C4<0>; +L_0x2a71b60 .delay (20000,20000,20000) L_0x2a71b60/d; +v0x287c340_0 .alias "S", 0 0, v0x289f760_0; +v0x287c3c0_0 .net "in0", 0 0, L_0x2a878b0; 1 drivers +v0x287c460_0 .net "in1", 0 0, L_0x2a879a0; 1 drivers +v0x287c500_0 .net "nS", 0 0, L_0x2a87300; 1 drivers +v0x287c5b0_0 .net "out0", 0 0, L_0x2a87410; 1 drivers +v0x287c650_0 .net "out1", 0 0, L_0x2a87520; 1 drivers +v0x287c730_0 .net "outfinal", 0 0, L_0x2a71b60; 1 drivers +S_0x287a460 .scope generate, "sltbits[19]" "sltbits[19]" 3 332, 3 332, S_0x2864a60; + .timescale -9 -12; +P_0x2879e78 .param/l "i" 3 332, +C4<010011>; +S_0x287b0c0 .scope module, "attempt" "MiddleAddSubSLT" 3 334, 3 189, S_0x287a460; + .timescale -9 -12; +L_0x2a71ca0/d .functor NOT 1, L_0x2a88100, C4<0>, C4<0>, C4<0>; +L_0x2a71ca0 .delay (10000,10000,10000) L_0x2a71ca0/d; +L_0x2a887d0/d .functor NOT 1, L_0x2a88870, C4<0>, C4<0>, C4<0>; +L_0x2a887d0 .delay (10000,10000,10000) L_0x2a887d0/d; +L_0x2a88910/d .functor AND 1, L_0x2a88a50, L_0x2a887d0, C4<1>, C4<1>; +L_0x2a88910 .delay (20000,20000,20000) L_0x2a88910/d; +L_0x2a88af0/d .functor XOR 1, L_0x2a88060, L_0x2a87e70, C4<0>, C4<0>; +L_0x2a88af0 .delay (40000,40000,40000) L_0x2a88af0/d; +L_0x2a88be0/d .functor XOR 1, L_0x2a88af0, L_0x2a88230, C4<0>, C4<0>; +L_0x2a88be0 .delay (40000,40000,40000) L_0x2a88be0/d; +L_0x2a88d00/d .functor AND 1, L_0x2a88060, L_0x2a87e70, C4<1>, C4<1>; +L_0x2a88d00 .delay (20000,20000,20000) L_0x2a88d00/d; +L_0x2a88ea0/d .functor AND 1, L_0x2a88af0, L_0x2a88230, C4<1>, C4<1>; +L_0x2a88ea0 .delay (20000,20000,20000) L_0x2a88ea0/d; +L_0x2a88f90/d .functor OR 1, L_0x2a88d00, L_0x2a88ea0, C4<0>, C4<0>; +L_0x2a88f90 .delay (20000,20000,20000) L_0x2a88f90/d; +v0x287b740_0 .net "A", 0 0, L_0x2a88060; 1 drivers +v0x287b800_0 .net "AandB", 0 0, L_0x2a88d00; 1 drivers +v0x287b8a0_0 .net "AddSubSLTSum", 0 0, L_0x2a88be0; 1 drivers +v0x287b940_0 .net "AxorB", 0 0, L_0x2a88af0; 1 drivers +v0x287b9c0_0 .net "B", 0 0, L_0x2a88100; 1 drivers +v0x287ba70_0 .net "BornB", 0 0, L_0x2a87e70; 1 drivers +v0x287bb30_0 .net "CINandAxorB", 0 0, L_0x2a88ea0; 1 drivers +v0x287bbb0_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x287bc30_0 .net *"_s3", 0 0, L_0x2a88870; 1 drivers +v0x287bcb0_0 .net *"_s5", 0 0, L_0x2a88a50; 1 drivers +v0x287bd50_0 .net "carryin", 0 0, L_0x2a88230; 1 drivers +v0x287bdf0_0 .net "carryout", 0 0, L_0x2a88f90; 1 drivers +v0x287be90_0 .net "nB", 0 0, L_0x2a71ca0; 1 drivers +v0x287bf40_0 .net "nCmd2", 0 0, L_0x2a887d0; 1 drivers +v0x287c040_0 .net "subtract", 0 0, L_0x2a88910; 1 drivers +L_0x2a88730 .part v0x2960210_0, 0, 1; +L_0x2a88870 .part v0x2960210_0, 2, 1; +L_0x2a88a50 .part v0x2960210_0, 0, 1; +S_0x287b1b0 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x287b0c0; + .timescale -9 -12; +L_0x2a87be0/d .functor NOT 1, L_0x2a88730, C4<0>, C4<0>, C4<0>; +L_0x2a87be0 .delay (10000,10000,10000) L_0x2a87be0/d; +L_0x2a87ca0/d .functor AND 1, L_0x2a88100, L_0x2a87be0, C4<1>, C4<1>; +L_0x2a87ca0 .delay (20000,20000,20000) L_0x2a87ca0/d; +L_0x2a87db0/d .functor AND 1, L_0x2a71ca0, L_0x2a88730, C4<1>, C4<1>; +L_0x2a87db0 .delay (20000,20000,20000) L_0x2a87db0/d; +L_0x2a87e70/d .functor OR 1, L_0x2a87ca0, L_0x2a87db0, C4<0>, C4<0>; +L_0x2a87e70 .delay (20000,20000,20000) L_0x2a87e70/d; +v0x287b2a0_0 .net "S", 0 0, L_0x2a88730; 1 drivers +v0x287b360_0 .alias "in0", 0 0, v0x287b9c0_0; +v0x287b400_0 .alias "in1", 0 0, v0x287be90_0; +v0x287b4a0_0 .net "nS", 0 0, L_0x2a87be0; 1 drivers +v0x287b520_0 .net "out0", 0 0, L_0x2a87ca0; 1 drivers +v0x287b5c0_0 .net "out1", 0 0, L_0x2a87db0; 1 drivers +v0x287b6a0_0 .alias "outfinal", 0 0, v0x287ba70_0; +S_0x287ab50 .scope module, "setSLTres2" "TwoInMux" 3 335, 3 109, S_0x287a460; + .timescale -9 -12; +L_0x2a882d0/d .functor NOT 1, L_0x2aa3020, C4<0>, C4<0>, C4<0>; +L_0x2a882d0 .delay (10000,10000,10000) L_0x2a882d0/d; +L_0x2a88370/d .functor AND 1, L_0x2a89ac0, L_0x2a882d0, C4<1>, C4<1>; +L_0x2a88370 .delay (20000,20000,20000) L_0x2a88370/d; +L_0x2a88480/d .functor AND 1, C4<0>, L_0x2aa3020, C4<1>, C4<1>; +L_0x2a88480 .delay (20000,20000,20000) L_0x2a88480/d; +L_0x2a88520/d .functor OR 1, L_0x2a88370, L_0x2a88480, C4<0>, C4<0>; +L_0x2a88520 .delay (20000,20000,20000) L_0x2a88520/d; +v0x287ac40_0 .alias "S", 0 0, v0x289f760_0; +v0x287ace0_0 .net "in0", 0 0, L_0x2a89ac0; 1 drivers +v0x287ad80_0 .net "in1", 0 0, C4<0>; 1 drivers +v0x287ae20_0 .net "nS", 0 0, L_0x2a882d0; 1 drivers +v0x287aea0_0 .net "out0", 0 0, L_0x2a88370; 1 drivers +v0x287af40_0 .net "out1", 0 0, L_0x2a88480; 1 drivers +v0x287b020_0 .net "outfinal", 0 0, L_0x2a88520; 1 drivers +S_0x287a5d0 .scope module, "setSLTres3" "TwoInMux" 3 336, 3 109, S_0x287a460; + .timescale -9 -12; +L_0x2a89360/d .functor NOT 1, L_0x2aa3020, C4<0>, C4<0>, C4<0>; +L_0x2a89360 .delay (10000,10000,10000) L_0x2a89360/d; +L_0x2a89470/d .functor AND 1, L_0x2a89800, L_0x2a89360, C4<1>, C4<1>; +L_0x2a89470 .delay (20000,20000,20000) L_0x2a89470/d; +L_0x2a89580/d .functor AND 1, L_0x2a8a240, L_0x2aa3020, C4<1>, C4<1>; +L_0x2a89580 .delay (20000,20000,20000) L_0x2a89580/d; +L_0x2a89620/d .functor OR 1, L_0x2a89470, L_0x2a89580, C4<0>, C4<0>; +L_0x2a89620 .delay (20000,20000,20000) L_0x2a89620/d; +v0x287a6c0_0 .alias "S", 0 0, v0x289f760_0; +v0x287a740_0 .net "in0", 0 0, L_0x2a89800; 1 drivers +v0x287a7e0_0 .net "in1", 0 0, L_0x2a8a240; 1 drivers +v0x287a880_0 .net "nS", 0 0, L_0x2a89360; 1 drivers +v0x287a930_0 .net "out0", 0 0, L_0x2a89470; 1 drivers +v0x287a9d0_0 .net "out1", 0 0, L_0x2a89580; 1 drivers +v0x287aab0_0 .net "outfinal", 0 0, L_0x2a89620; 1 drivers +S_0x28787e0 .scope generate, "sltbits[20]" "sltbits[20]" 3 332, 3 332, S_0x2864a60; + .timescale -9 -12; +P_0x28781f8 .param/l "i" 3 332, +C4<010100>; +S_0x2879440 .scope module, "attempt" "MiddleAddSubSLT" 3 334, 3 189, S_0x28787e0; + .timescale -9 -12; +L_0x2a8a2e0/d .functor NOT 1, L_0x2a89e30, C4<0>, C4<0>, C4<0>; +L_0x2a8a2e0 .delay (10000,10000,10000) L_0x2a8a2e0/d; +L_0x2a8a9e0/d .functor NOT 1, L_0x2a8aaa0, C4<0>, C4<0>, C4<0>; +L_0x2a8a9e0 .delay (10000,10000,10000) L_0x2a8a9e0/d; +L_0x2a8ab40/d .functor AND 1, L_0x2a8ac80, L_0x2a8a9e0, C4<1>, C4<1>; +L_0x2a8ab40 .delay (20000,20000,20000) L_0x2a8ab40/d; +L_0x2a8ad20/d .functor XOR 1, L_0x2a89d90, L_0x2a8a770, C4<0>, C4<0>; +L_0x2a8ad20 .delay (40000,40000,40000) L_0x2a8ad20/d; +L_0x2a8ae10/d .functor XOR 1, L_0x2a8ad20, L_0x2a89f60, C4<0>, C4<0>; +L_0x2a8ae10 .delay (40000,40000,40000) L_0x2a8ae10/d; +L_0x2a8af00/d .functor AND 1, L_0x2a89d90, L_0x2a8a770, C4<1>, C4<1>; +L_0x2a8af00 .delay (20000,20000,20000) L_0x2a8af00/d; +L_0x2a8b070/d .functor AND 1, L_0x2a8ad20, L_0x2a89f60, C4<1>, C4<1>; +L_0x2a8b070 .delay (20000,20000,20000) L_0x2a8b070/d; +L_0x2a8b160/d .functor OR 1, L_0x2a8af00, L_0x2a8b070, C4<0>, C4<0>; +L_0x2a8b160 .delay (20000,20000,20000) L_0x2a8b160/d; +v0x2879ac0_0 .net "A", 0 0, L_0x2a89d90; 1 drivers +v0x2879b80_0 .net "AandB", 0 0, L_0x2a8af00; 1 drivers +v0x2879c20_0 .net "AddSubSLTSum", 0 0, L_0x2a8ae10; 1 drivers +v0x2879cc0_0 .net "AxorB", 0 0, L_0x2a8ad20; 1 drivers +v0x2879d40_0 .net "B", 0 0, L_0x2a89e30; 1 drivers +v0x2879df0_0 .net "BornB", 0 0, L_0x2a8a770; 1 drivers +v0x2879eb0_0 .net "CINandAxorB", 0 0, L_0x2a8b070; 1 drivers +v0x2879f30_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x2879fb0_0 .net *"_s3", 0 0, L_0x2a8aaa0; 1 drivers +v0x287a030_0 .net *"_s5", 0 0, L_0x2a8ac80; 1 drivers +v0x287a0d0_0 .net "carryin", 0 0, L_0x2a89f60; 1 drivers +v0x287a170_0 .net "carryout", 0 0, L_0x2a8b160; 1 drivers +v0x287a210_0 .net "nB", 0 0, L_0x2a8a2e0; 1 drivers +v0x287a2c0_0 .net "nCmd2", 0 0, L_0x2a8a9e0; 1 drivers +v0x287a3c0_0 .net "subtract", 0 0, L_0x2a8ab40; 1 drivers +L_0x2a8a940 .part v0x2960210_0, 0, 1; +L_0x2a8aaa0 .part v0x2960210_0, 2, 1; +L_0x2a8ac80 .part v0x2960210_0, 0, 1; +S_0x2879530 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x2879440; + .timescale -9 -12; +L_0x2a8a490/d .functor NOT 1, L_0x2a8a940, C4<0>, C4<0>, C4<0>; +L_0x2a8a490 .delay (10000,10000,10000) L_0x2a8a490/d; +L_0x2a8a550/d .functor AND 1, L_0x2a89e30, L_0x2a8a490, C4<1>, C4<1>; +L_0x2a8a550 .delay (20000,20000,20000) L_0x2a8a550/d; +L_0x2a8a660/d .functor AND 1, L_0x2a8a2e0, L_0x2a8a940, C4<1>, C4<1>; +L_0x2a8a660 .delay (20000,20000,20000) L_0x2a8a660/d; +L_0x2a8a770/d .functor OR 1, L_0x2a8a550, L_0x2a8a660, C4<0>, C4<0>; +L_0x2a8a770 .delay (20000,20000,20000) L_0x2a8a770/d; +v0x2879620_0 .net "S", 0 0, L_0x2a8a940; 1 drivers +v0x28796e0_0 .alias "in0", 0 0, v0x2879d40_0; +v0x2879780_0 .alias "in1", 0 0, v0x287a210_0; +v0x2879820_0 .net "nS", 0 0, L_0x2a8a490; 1 drivers +v0x28798a0_0 .net "out0", 0 0, L_0x2a8a550; 1 drivers +v0x2879940_0 .net "out1", 0 0, L_0x2a8a660; 1 drivers +v0x2879a20_0 .alias "outfinal", 0 0, v0x2879df0_0; +S_0x2878ed0 .scope module, "setSLTres2" "TwoInMux" 3 335, 3 109, S_0x28787e0; + .timescale -9 -12; +L_0x2a8a000/d .functor NOT 1, L_0x2aa3020, C4<0>, C4<0>, C4<0>; +L_0x2a8a000 .delay (10000,10000,10000) L_0x2a8a000/d; +L_0x2a8a0a0/d .functor AND 1, L_0x2a8b3b0, L_0x2a8a000, C4<1>, C4<1>; +L_0x2a8a0a0 .delay (20000,20000,20000) L_0x2a8a0a0/d; +L_0x2a8a1b0/d .functor AND 1, C4<0>, L_0x2aa3020, C4<1>, C4<1>; +L_0x2a8a1b0 .delay (20000,20000,20000) L_0x2a8a1b0/d; +L_0x2a8bab0/d .functor OR 1, L_0x2a8a0a0, L_0x2a8a1b0, C4<0>, C4<0>; +L_0x2a8bab0 .delay (20000,20000,20000) L_0x2a8bab0/d; +v0x2878fc0_0 .alias "S", 0 0, v0x289f760_0; +v0x2879060_0 .net "in0", 0 0, L_0x2a8b3b0; 1 drivers +v0x2879100_0 .net "in1", 0 0, C4<0>; 1 drivers +v0x28791a0_0 .net "nS", 0 0, L_0x2a8a000; 1 drivers +v0x2879220_0 .net "out0", 0 0, L_0x2a8a0a0; 1 drivers +v0x28792c0_0 .net "out1", 0 0, L_0x2a8a1b0; 1 drivers +v0x28793a0_0 .net "outfinal", 0 0, L_0x2a8bab0; 1 drivers +S_0x2878950 .scope module, "setSLTres3" "TwoInMux" 3 336, 3 109, S_0x28787e0; + .timescale -9 -12; +L_0x2a8b6f0/d .functor NOT 1, L_0x2aa3020, C4<0>, C4<0>, C4<0>; +L_0x2a8b6f0 .delay (10000,10000,10000) L_0x2a8b6f0/d; +L_0x2a8b800/d .functor AND 1, L_0x2a8c370, L_0x2a8b6f0, C4<1>, C4<1>; +L_0x2a8b800 .delay (20000,20000,20000) L_0x2a8b800/d; +L_0x2a8b910/d .functor AND 1, L_0x2a8c410, L_0x2aa3020, C4<1>, C4<1>; +L_0x2a8b910 .delay (20000,20000,20000) L_0x2a8b910/d; +L_0x2a8b9b0/d .functor OR 1, L_0x2a8b800, L_0x2a8b910, C4<0>, C4<0>; +L_0x2a8b9b0 .delay (20000,20000,20000) L_0x2a8b9b0/d; +v0x2878a40_0 .alias "S", 0 0, v0x289f760_0; +v0x2878ac0_0 .net "in0", 0 0, L_0x2a8c370; 1 drivers +v0x2878b60_0 .net "in1", 0 0, L_0x2a8c410; 1 drivers +v0x2878c00_0 .net "nS", 0 0, L_0x2a8b6f0; 1 drivers +v0x2878cb0_0 .net "out0", 0 0, L_0x2a8b800; 1 drivers +v0x2878d50_0 .net "out1", 0 0, L_0x2a8b910; 1 drivers +v0x2878e30_0 .net "outfinal", 0 0, L_0x2a8b9b0; 1 drivers +S_0x2876b60 .scope generate, "sltbits[21]" "sltbits[21]" 3 332, 3 332, S_0x2864a60; + .timescale -9 -12; +P_0x2876578 .param/l "i" 3 332, +C4<010101>; +S_0x28777c0 .scope module, "attempt" "MiddleAddSubSLT" 3 334, 3 189, S_0x2876b60; + .timescale -9 -12; +L_0x2a8bc90/d .functor NOT 1, L_0x2a8c690, C4<0>, C4<0>, C4<0>; +L_0x2a8bc90 .delay (10000,10000,10000) L_0x2a8bc90/d; +L_0x2a8c310/d .functor NOT 1, L_0x2a8ccd0, C4<0>, C4<0>, C4<0>; +L_0x2a8c310 .delay (10000,10000,10000) L_0x2a8c310/d; +L_0x2a8cd70/d .functor AND 1, L_0x2a8ceb0, L_0x2a8c310, C4<1>, C4<1>; +L_0x2a8cd70 .delay (20000,20000,20000) L_0x2a8cd70/d; +L_0x2a8cf50/d .functor XOR 1, L_0x2a8c5f0, L_0x2a8c140, C4<0>, C4<0>; +L_0x2a8cf50 .delay (40000,40000,40000) L_0x2a8cf50/d; +L_0x2a8d040/d .functor XOR 1, L_0x2a8cf50, L_0x2a8c7c0, C4<0>, C4<0>; +L_0x2a8d040 .delay (40000,40000,40000) L_0x2a8d040/d; +L_0x2a8d130/d .functor AND 1, L_0x2a8c5f0, L_0x2a8c140, C4<1>, C4<1>; +L_0x2a8d130 .delay (20000,20000,20000) L_0x2a8d130/d; +L_0x2a8d2a0/d .functor AND 1, L_0x2a8cf50, L_0x2a8c7c0, C4<1>, C4<1>; +L_0x2a8d2a0 .delay (20000,20000,20000) L_0x2a8d2a0/d; +L_0x2a8d390/d .functor OR 1, L_0x2a8d130, L_0x2a8d2a0, C4<0>, C4<0>; +L_0x2a8d390 .delay (20000,20000,20000) L_0x2a8d390/d; +v0x2877e40_0 .net "A", 0 0, L_0x2a8c5f0; 1 drivers +v0x2877f00_0 .net "AandB", 0 0, L_0x2a8d130; 1 drivers +v0x2877fa0_0 .net "AddSubSLTSum", 0 0, L_0x2a8d040; 1 drivers +v0x2878040_0 .net "AxorB", 0 0, L_0x2a8cf50; 1 drivers +v0x28780c0_0 .net "B", 0 0, L_0x2a8c690; 1 drivers +v0x2878170_0 .net "BornB", 0 0, L_0x2a8c140; 1 drivers +v0x2878230_0 .net "CINandAxorB", 0 0, L_0x2a8d2a0; 1 drivers +v0x28782b0_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x2878330_0 .net *"_s3", 0 0, L_0x2a8ccd0; 1 drivers +v0x28783b0_0 .net *"_s5", 0 0, L_0x2a8ceb0; 1 drivers +v0x2878450_0 .net "carryin", 0 0, L_0x2a8c7c0; 1 drivers +v0x28784f0_0 .net "carryout", 0 0, L_0x2a8d390; 1 drivers +v0x2878590_0 .net "nB", 0 0, L_0x2a8bc90; 1 drivers +v0x2878640_0 .net "nCmd2", 0 0, L_0x2a8c310; 1 drivers +v0x2878740_0 .net "subtract", 0 0, L_0x2a8cd70; 1 drivers +L_0x2a8cbf0 .part v0x2960210_0, 0, 1; +L_0x2a8ccd0 .part v0x2960210_0, 2, 1; +L_0x2a8ceb0 .part v0x2960210_0, 0, 1; +S_0x28778b0 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x28777c0; + .timescale -9 -12; +L_0x2a8be60/d .functor NOT 1, L_0x2a8cbf0, C4<0>, C4<0>, C4<0>; +L_0x2a8be60 .delay (10000,10000,10000) L_0x2a8be60/d; +L_0x2a8bf20/d .functor AND 1, L_0x2a8c690, L_0x2a8be60, C4<1>, C4<1>; +L_0x2a8bf20 .delay (20000,20000,20000) L_0x2a8bf20/d; +L_0x2a8c030/d .functor AND 1, L_0x2a8bc90, L_0x2a8cbf0, C4<1>, C4<1>; +L_0x2a8c030 .delay (20000,20000,20000) L_0x2a8c030/d; +L_0x2a8c140/d .functor OR 1, L_0x2a8bf20, L_0x2a8c030, C4<0>, C4<0>; +L_0x2a8c140 .delay (20000,20000,20000) L_0x2a8c140/d; +v0x28779a0_0 .net "S", 0 0, L_0x2a8cbf0; 1 drivers +v0x2877a60_0 .alias "in0", 0 0, v0x28780c0_0; +v0x2877b00_0 .alias "in1", 0 0, v0x2878590_0; +v0x2877ba0_0 .net "nS", 0 0, L_0x2a8be60; 1 drivers +v0x2877c20_0 .net "out0", 0 0, L_0x2a8bf20; 1 drivers +v0x2877cc0_0 .net "out1", 0 0, L_0x2a8c030; 1 drivers +v0x2877da0_0 .alias "outfinal", 0 0, v0x2878170_0; +S_0x2877250 .scope module, "setSLTres2" "TwoInMux" 3 335, 3 109, S_0x2876b60; + .timescale -9 -12; +L_0x2a8c860/d .functor NOT 1, L_0x2aa3020, C4<0>, C4<0>, C4<0>; +L_0x2a8c860 .delay (10000,10000,10000) L_0x2a8c860/d; +L_0x2a8c900/d .functor AND 1, L_0x2a8de70, L_0x2a8c860, C4<1>, C4<1>; +L_0x2a8c900 .delay (20000,20000,20000) L_0x2a8c900/d; +L_0x2a8ca10/d .functor AND 1, C4<0>, L_0x2aa3020, C4<1>, C4<1>; +L_0x2a8ca10 .delay (20000,20000,20000) L_0x2a8ca10/d; +L_0x2a8cab0/d .functor OR 1, L_0x2a8c900, L_0x2a8ca10, C4<0>, C4<0>; +L_0x2a8cab0 .delay (20000,20000,20000) L_0x2a8cab0/d; +v0x2877340_0 .alias "S", 0 0, v0x289f760_0; +v0x28773e0_0 .net "in0", 0 0, L_0x2a8de70; 1 drivers +v0x2877480_0 .net "in1", 0 0, C4<0>; 1 drivers +v0x2877520_0 .net "nS", 0 0, L_0x2a8c860; 1 drivers +v0x28775a0_0 .net "out0", 0 0, L_0x2a8c900; 1 drivers +v0x2877640_0 .net "out1", 0 0, L_0x2a8ca10; 1 drivers +v0x2877720_0 .net "outfinal", 0 0, L_0x2a8cab0; 1 drivers +S_0x2876cd0 .scope module, "setSLTres3" "TwoInMux" 3 336, 3 109, S_0x2876b60; + .timescale -9 -12; +L_0x2a8d740/d .functor NOT 1, L_0x2aa3020, C4<0>, C4<0>, C4<0>; +L_0x2a8d740 .delay (10000,10000,10000) L_0x2a8d740/d; +L_0x2a8d850/d .functor AND 1, L_0x2a8dbe0, L_0x2a8d740, C4<1>, C4<1>; +L_0x2a8d850 .delay (20000,20000,20000) L_0x2a8d850/d; +L_0x2a8d960/d .functor AND 1, L_0x2a8dcd0, L_0x2aa3020, C4<1>, C4<1>; +L_0x2a8d960 .delay (20000,20000,20000) L_0x2a8d960/d; +L_0x2a8da00/d .functor OR 1, L_0x2a8d850, L_0x2a8d960, C4<0>, C4<0>; +L_0x2a8da00 .delay (20000,20000,20000) L_0x2a8da00/d; +v0x2876dc0_0 .alias "S", 0 0, v0x289f760_0; +v0x2876e40_0 .net "in0", 0 0, L_0x2a8dbe0; 1 drivers +v0x2876ee0_0 .net "in1", 0 0, L_0x2a8dcd0; 1 drivers +v0x2876f80_0 .net "nS", 0 0, L_0x2a8d740; 1 drivers +v0x2877030_0 .net "out0", 0 0, L_0x2a8d850; 1 drivers +v0x28770d0_0 .net "out1", 0 0, L_0x2a8d960; 1 drivers +v0x28771b0_0 .net "outfinal", 0 0, L_0x2a8da00; 1 drivers +S_0x2874ee0 .scope generate, "sltbits[22]" "sltbits[22]" 3 332, 3 332, S_0x2864a60; + .timescale -9 -12; +P_0x28748f8 .param/l "i" 3 332, +C4<010110>; +S_0x2875b40 .scope module, "attempt" "MiddleAddSubSLT" 3 334, 3 189, S_0x2874ee0; + .timescale -9 -12; +L_0x2a8e6a0/d .functor NOT 1, L_0x2a8e1e0, C4<0>, C4<0>, C4<0>; +L_0x2a8e6a0 .delay (10000,10000,10000) L_0x2a8e6a0/d; +L_0x2a8edc0/d .functor NOT 1, L_0x2a8ee80, C4<0>, C4<0>, C4<0>; +L_0x2a8edc0 .delay (10000,10000,10000) L_0x2a8edc0/d; +L_0x2a8ef20/d .functor AND 1, L_0x2a8f060, L_0x2a8edc0, C4<1>, C4<1>; +L_0x2a8ef20 .delay (20000,20000,20000) L_0x2a8ef20/d; +L_0x2a8f100/d .functor XOR 1, L_0x2a8e140, L_0x2a8eb50, C4<0>, C4<0>; +L_0x2a8f100 .delay (40000,40000,40000) L_0x2a8f100/d; +L_0x2a8f1f0/d .functor XOR 1, L_0x2a8f100, L_0x2a8e310, C4<0>, C4<0>; +L_0x2a8f1f0 .delay (40000,40000,40000) L_0x2a8f1f0/d; +L_0x2a8f2e0/d .functor AND 1, L_0x2a8e140, L_0x2a8eb50, C4<1>, C4<1>; +L_0x2a8f2e0 .delay (20000,20000,20000) L_0x2a8f2e0/d; +L_0x2a8f450/d .functor AND 1, L_0x2a8f100, L_0x2a8e310, C4<1>, C4<1>; +L_0x2a8f450 .delay (20000,20000,20000) L_0x2a8f450/d; +L_0x2a8f540/d .functor OR 1, L_0x2a8f2e0, L_0x2a8f450, C4<0>, C4<0>; +L_0x2a8f540 .delay (20000,20000,20000) L_0x2a8f540/d; +v0x28761c0_0 .net "A", 0 0, L_0x2a8e140; 1 drivers +v0x2876280_0 .net "AandB", 0 0, L_0x2a8f2e0; 1 drivers +v0x2876320_0 .net "AddSubSLTSum", 0 0, L_0x2a8f1f0; 1 drivers +v0x28763c0_0 .net "AxorB", 0 0, L_0x2a8f100; 1 drivers +v0x2876440_0 .net "B", 0 0, L_0x2a8e1e0; 1 drivers +v0x28764f0_0 .net "BornB", 0 0, L_0x2a8eb50; 1 drivers +v0x28765b0_0 .net "CINandAxorB", 0 0, L_0x2a8f450; 1 drivers +v0x2876630_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x28766b0_0 .net *"_s3", 0 0, L_0x2a8ee80; 1 drivers +v0x2876730_0 .net *"_s5", 0 0, L_0x2a8f060; 1 drivers +v0x28767d0_0 .net "carryin", 0 0, L_0x2a8e310; 1 drivers +v0x2876870_0 .net "carryout", 0 0, L_0x2a8f540; 1 drivers +v0x2876910_0 .net "nB", 0 0, L_0x2a8e6a0; 1 drivers +v0x28769c0_0 .net "nCmd2", 0 0, L_0x2a8edc0; 1 drivers +v0x2876ac0_0 .net "subtract", 0 0, L_0x2a8ef20; 1 drivers +L_0x2a8ed20 .part v0x2960210_0, 0, 1; +L_0x2a8ee80 .part v0x2960210_0, 2, 1; +L_0x2a8f060 .part v0x2960210_0, 0, 1; +S_0x2875c30 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x2875b40; + .timescale -9 -12; +L_0x2a8e870/d .functor NOT 1, L_0x2a8ed20, C4<0>, C4<0>, C4<0>; +L_0x2a8e870 .delay (10000,10000,10000) L_0x2a8e870/d; +L_0x2a8e930/d .functor AND 1, L_0x2a8e1e0, L_0x2a8e870, C4<1>, C4<1>; +L_0x2a8e930 .delay (20000,20000,20000) L_0x2a8e930/d; +L_0x2a8ea40/d .functor AND 1, L_0x2a8e6a0, L_0x2a8ed20, C4<1>, C4<1>; +L_0x2a8ea40 .delay (20000,20000,20000) L_0x2a8ea40/d; +L_0x2a8eb50/d .functor OR 1, L_0x2a8e930, L_0x2a8ea40, C4<0>, C4<0>; +L_0x2a8eb50 .delay (20000,20000,20000) L_0x2a8eb50/d; +v0x2875d20_0 .net "S", 0 0, L_0x2a8ed20; 1 drivers +v0x2875de0_0 .alias "in0", 0 0, v0x2876440_0; +v0x2875e80_0 .alias "in1", 0 0, v0x2876910_0; +v0x2875f20_0 .net "nS", 0 0, L_0x2a8e870; 1 drivers +v0x2875fa0_0 .net "out0", 0 0, L_0x2a8e930; 1 drivers +v0x2876040_0 .net "out1", 0 0, L_0x2a8ea40; 1 drivers +v0x2876120_0 .alias "outfinal", 0 0, v0x28764f0_0; +S_0x28755d0 .scope module, "setSLTres2" "TwoInMux" 3 335, 3 109, S_0x2874ee0; + .timescale -9 -12; +L_0x2a8e3b0/d .functor NOT 1, L_0x2aa3020, C4<0>, C4<0>, C4<0>; +L_0x2a8e3b0 .delay (10000,10000,10000) L_0x2a8e3b0/d; +L_0x2a8e450/d .functor AND 1, L_0x2a78680, L_0x2a8e3b0, C4<1>, C4<1>; +L_0x2a8e450 .delay (20000,20000,20000) L_0x2a8e450/d; +L_0x2a8e560/d .functor AND 1, C4<0>, L_0x2aa3020, C4<1>, C4<1>; +L_0x2a8e560 .delay (20000,20000,20000) L_0x2a8e560/d; +L_0x2a8e600/d .functor OR 1, L_0x2a8e450, L_0x2a8e560, C4<0>, C4<0>; +L_0x2a8e600 .delay (20000,20000,20000) L_0x2a8e600/d; +v0x28756c0_0 .alias "S", 0 0, v0x289f760_0; +v0x2875760_0 .net "in0", 0 0, L_0x2a78680; 1 drivers +v0x2875800_0 .net "in1", 0 0, C4<0>; 1 drivers +v0x28758a0_0 .net "nS", 0 0, L_0x2a8e3b0; 1 drivers +v0x2875920_0 .net "out0", 0 0, L_0x2a8e450; 1 drivers +v0x28759c0_0 .net "out1", 0 0, L_0x2a8e560; 1 drivers +v0x2875aa0_0 .net "outfinal", 0 0, L_0x2a8e600; 1 drivers +S_0x2875050 .scope module, "setSLTres3" "TwoInMux" 3 336, 3 109, S_0x2874ee0; + .timescale -9 -12; +L_0x2a789d0/d .functor NOT 1, L_0x2aa3020, C4<0>, C4<0>, C4<0>; +L_0x2a789d0 .delay (10000,10000,10000) L_0x2a789d0/d; +L_0x2a8b580/d .functor AND 1, L_0x2a8f9b0, L_0x2a789d0, C4<1>, C4<1>; +L_0x2a8b580 .delay (20000,20000,20000) L_0x2a8b580/d; +L_0x2a8b690/d .functor AND 1, L_0x2a8faa0, L_0x2aa3020, C4<1>, C4<1>; +L_0x2a8b690 .delay (20000,20000,20000) L_0x2a8b690/d; +L_0x2a8f7d0/d .functor OR 1, L_0x2a8b580, L_0x2a8b690, C4<0>, C4<0>; +L_0x2a8f7d0 .delay (20000,20000,20000) L_0x2a8f7d0/d; +v0x2875140_0 .alias "S", 0 0, v0x289f760_0; +v0x28751c0_0 .net "in0", 0 0, L_0x2a8f9b0; 1 drivers +v0x2875260_0 .net "in1", 0 0, L_0x2a8faa0; 1 drivers +v0x2875300_0 .net "nS", 0 0, L_0x2a789d0; 1 drivers +v0x28753b0_0 .net "out0", 0 0, L_0x2a8b580; 1 drivers +v0x2875450_0 .net "out1", 0 0, L_0x2a8b690; 1 drivers +v0x2875530_0 .net "outfinal", 0 0, L_0x2a8f7d0; 1 drivers +S_0x2873160 .scope generate, "sltbits[23]" "sltbits[23]" 3 332, 3 332, S_0x2864a60; + .timescale -9 -12; +P_0x2872b78 .param/l "i" 3 332, +C4<010111>; +S_0x2873ec0 .scope module, "attempt" "MiddleAddSubSLT" 3 334, 3 189, S_0x2873160; + .timescale -9 -12; +L_0x2a8fb90/d .functor NOT 1, L_0x2a909e0, C4<0>, C4<0>, C4<0>; +L_0x2a8fb90 .delay (10000,10000,10000) L_0x2a8fb90/d; +L_0x2a913a0/d .functor NOT 1, L_0x2a91460, C4<0>, C4<0>, C4<0>; +L_0x2a913a0 .delay (10000,10000,10000) L_0x2a913a0/d; +L_0x2a91500/d .functor AND 1, L_0x2a91640, L_0x2a913a0, C4<1>, C4<1>; +L_0x2a91500 .delay (20000,20000,20000) L_0x2a91500/d; +L_0x2a916e0/d .functor XOR 1, L_0x2a90940, L_0x2a91130, C4<0>, C4<0>; +L_0x2a916e0 .delay (40000,40000,40000) L_0x2a916e0/d; +L_0x2a917d0/d .functor XOR 1, L_0x2a916e0, L_0x2a90b10, C4<0>, C4<0>; +L_0x2a917d0 .delay (40000,40000,40000) L_0x2a917d0/d; +L_0x2a918c0/d .functor AND 1, L_0x2a90940, L_0x2a91130, C4<1>, C4<1>; +L_0x2a918c0 .delay (20000,20000,20000) L_0x2a918c0/d; +L_0x2a91a30/d .functor AND 1, L_0x2a916e0, L_0x2a90b10, C4<1>, C4<1>; +L_0x2a91a30 .delay (20000,20000,20000) L_0x2a91a30/d; +L_0x2a91b20/d .functor OR 1, L_0x2a918c0, L_0x2a91a30, C4<0>, C4<0>; +L_0x2a91b20 .delay (20000,20000,20000) L_0x2a91b20/d; +v0x2874540_0 .net "A", 0 0, L_0x2a90940; 1 drivers +v0x2874600_0 .net "AandB", 0 0, L_0x2a918c0; 1 drivers +v0x28746a0_0 .net "AddSubSLTSum", 0 0, L_0x2a917d0; 1 drivers +v0x2874740_0 .net "AxorB", 0 0, L_0x2a916e0; 1 drivers +v0x28747c0_0 .net "B", 0 0, L_0x2a909e0; 1 drivers +v0x2874870_0 .net "BornB", 0 0, L_0x2a91130; 1 drivers +v0x2874930_0 .net "CINandAxorB", 0 0, L_0x2a91a30; 1 drivers +v0x28749b0_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x2874a30_0 .net *"_s3", 0 0, L_0x2a91460; 1 drivers +v0x2874ab0_0 .net *"_s5", 0 0, L_0x2a91640; 1 drivers +v0x2874b50_0 .net "carryin", 0 0, L_0x2a90b10; 1 drivers +v0x2874bf0_0 .net "carryout", 0 0, L_0x2a91b20; 1 drivers +v0x2874c90_0 .net "nB", 0 0, L_0x2a8fb90; 1 drivers +v0x2874d40_0 .net "nCmd2", 0 0, L_0x2a913a0; 1 drivers +v0x2874e40_0 .net "subtract", 0 0, L_0x2a91500; 1 drivers +L_0x2a91300 .part v0x2960210_0, 0, 1; +L_0x2a91460 .part v0x2960210_0, 2, 1; +L_0x2a91640 .part v0x2960210_0, 0, 1; +S_0x2873fb0 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x2873ec0; + .timescale -9 -12; +L_0x2a8fd60/d .functor NOT 1, L_0x2a91300, C4<0>, C4<0>, C4<0>; +L_0x2a8fd60 .delay (10000,10000,10000) L_0x2a8fd60/d; +L_0x2a8fe20/d .functor AND 1, L_0x2a909e0, L_0x2a8fd60, C4<1>, C4<1>; +L_0x2a8fe20 .delay (20000,20000,20000) L_0x2a8fe20/d; +L_0x2a91040/d .functor AND 1, L_0x2a8fb90, L_0x2a91300, C4<1>, C4<1>; +L_0x2a91040 .delay (20000,20000,20000) L_0x2a91040/d; +L_0x2a91130/d .functor OR 1, L_0x2a8fe20, L_0x2a91040, C4<0>, C4<0>; +L_0x2a91130 .delay (20000,20000,20000) L_0x2a91130/d; +v0x28740a0_0 .net "S", 0 0, L_0x2a91300; 1 drivers +v0x2874160_0 .alias "in0", 0 0, v0x28747c0_0; +v0x2874200_0 .alias "in1", 0 0, v0x2874c90_0; +v0x28742a0_0 .net "nS", 0 0, L_0x2a8fd60; 1 drivers +v0x2874320_0 .net "out0", 0 0, L_0x2a8fe20; 1 drivers +v0x28743c0_0 .net "out1", 0 0, L_0x2a91040; 1 drivers +v0x28744a0_0 .alias "outfinal", 0 0, v0x2874870_0; +S_0x2873950 .scope module, "setSLTres2" "TwoInMux" 3 335, 3 109, S_0x2873160; + .timescale -9 -12; +L_0x2a90bb0/d .functor NOT 1, L_0x2aa3020, C4<0>, C4<0>, C4<0>; +L_0x2a90bb0 .delay (10000,10000,10000) L_0x2a90bb0/d; +L_0x2a90c50/d .functor AND 1, L_0x2a92630, L_0x2a90bb0, C4<1>, C4<1>; +L_0x2a90c50 .delay (20000,20000,20000) L_0x2a90c50/d; +L_0x2a90d60/d .functor AND 1, C4<0>, L_0x2aa3020, C4<1>, C4<1>; +L_0x2a90d60 .delay (20000,20000,20000) L_0x2a90d60/d; +L_0x2a90e00/d .functor OR 1, L_0x2a90c50, L_0x2a90d60, C4<0>, C4<0>; +L_0x2a90e00 .delay (20000,20000,20000) L_0x2a90e00/d; +v0x2873a40_0 .alias "S", 0 0, v0x289f760_0; +v0x2873ae0_0 .net "in0", 0 0, L_0x2a92630; 1 drivers +v0x2873b80_0 .net "in1", 0 0, C4<0>; 1 drivers +v0x2873c20_0 .net "nS", 0 0, L_0x2a90bb0; 1 drivers +v0x2873ca0_0 .net "out0", 0 0, L_0x2a90c50; 1 drivers +v0x2873d40_0 .net "out1", 0 0, L_0x2a90d60; 1 drivers +v0x2873e20_0 .net "outfinal", 0 0, L_0x2a90e00; 1 drivers +S_0x28732d0 .scope module, "setSLTres3" "TwoInMux" 3 336, 3 109, S_0x2873160; + .timescale -9 -12; +L_0x2a91ef0/d .functor NOT 1, L_0x2aa3020, C4<0>, C4<0>, C4<0>; +L_0x2a91ef0 .delay (10000,10000,10000) L_0x2a91ef0/d; +L_0x2a92000/d .functor AND 1, L_0x2a92390, L_0x2a91ef0, C4<1>, C4<1>; +L_0x2a92000 .delay (20000,20000,20000) L_0x2a92000/d; +L_0x2a92110/d .functor AND 1, L_0x2a92480, L_0x2aa3020, C4<1>, C4<1>; +L_0x2a92110 .delay (20000,20000,20000) L_0x2a92110/d; +L_0x2a921b0/d .functor OR 1, L_0x2a92000, L_0x2a92110, C4<0>, C4<0>; +L_0x2a921b0 .delay (20000,20000,20000) L_0x2a921b0/d; +v0x28733c0_0 .alias "S", 0 0, v0x289f760_0; +v0x286c1b0_0 .net "in0", 0 0, L_0x2a92390; 1 drivers +v0x2873650_0 .net "in1", 0 0, L_0x2a92480; 1 drivers +v0x28736d0_0 .net "nS", 0 0, L_0x2a91ef0; 1 drivers +v0x2873750_0 .net "out0", 0 0, L_0x2a92000; 1 drivers +v0x28737d0_0 .net "out1", 0 0, L_0x2a92110; 1 drivers +v0x28738b0_0 .net "outfinal", 0 0, L_0x2a921b0; 1 drivers +S_0x28714e0 .scope generate, "sltbits[24]" "sltbits[24]" 3 332, 3 332, S_0x2864a60; + .timescale -9 -12; +P_0x2870ef8 .param/l "i" 3 332, +C4<011000>; +S_0x2872140 .scope module, "attempt" "MiddleAddSubSLT" 3 334, 3 189, S_0x28714e0; + .timescale -9 -12; +L_0x2a92570/d .functor NOT 1, L_0x2a929a0, C4<0>, C4<0>, C4<0>; +L_0x2a92570 .delay (10000,10000,10000) L_0x2a92570/d; +L_0x2a93580/d .functor NOT 1, L_0x2a93640, C4<0>, C4<0>, C4<0>; +L_0x2a93580 .delay (10000,10000,10000) L_0x2a93580/d; +L_0x2a936e0/d .functor AND 1, L_0x2a93820, L_0x2a93580, C4<1>, C4<1>; +L_0x2a936e0 .delay (20000,20000,20000) L_0x2a936e0/d; +L_0x2a938c0/d .functor XOR 1, L_0x2a92900, L_0x2a93310, C4<0>, C4<0>; +L_0x2a938c0 .delay (40000,40000,40000) L_0x2a938c0/d; +L_0x2a939b0/d .functor XOR 1, L_0x2a938c0, L_0x2a92ad0, C4<0>, C4<0>; +L_0x2a939b0 .delay (40000,40000,40000) L_0x2a939b0/d; +L_0x2a93aa0/d .functor AND 1, L_0x2a92900, L_0x2a93310, C4<1>, C4<1>; +L_0x2a93aa0 .delay (20000,20000,20000) L_0x2a93aa0/d; +L_0x2a93c10/d .functor AND 1, L_0x2a938c0, L_0x2a92ad0, C4<1>, C4<1>; +L_0x2a93c10 .delay (20000,20000,20000) L_0x2a93c10/d; +L_0x2a93d00/d .functor OR 1, L_0x2a93aa0, L_0x2a93c10, C4<0>, C4<0>; +L_0x2a93d00 .delay (20000,20000,20000) L_0x2a93d00/d; +v0x28727c0_0 .net "A", 0 0, L_0x2a92900; 1 drivers +v0x2872880_0 .net "AandB", 0 0, L_0x2a93aa0; 1 drivers +v0x2872920_0 .net "AddSubSLTSum", 0 0, L_0x2a939b0; 1 drivers +v0x28729c0_0 .net "AxorB", 0 0, L_0x2a938c0; 1 drivers +v0x2872a40_0 .net "B", 0 0, L_0x2a929a0; 1 drivers +v0x2872af0_0 .net "BornB", 0 0, L_0x2a93310; 1 drivers +v0x2872bb0_0 .net "CINandAxorB", 0 0, L_0x2a93c10; 1 drivers +v0x2872c30_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x2872cb0_0 .net *"_s3", 0 0, L_0x2a93640; 1 drivers +v0x2872d30_0 .net *"_s5", 0 0, L_0x2a93820; 1 drivers +v0x2872dd0_0 .net "carryin", 0 0, L_0x2a92ad0; 1 drivers +v0x2872e70_0 .net "carryout", 0 0, L_0x2a93d00; 1 drivers +v0x2872f10_0 .net "nB", 0 0, L_0x2a92570; 1 drivers +v0x2872fc0_0 .net "nCmd2", 0 0, L_0x2a93580; 1 drivers +v0x28730c0_0 .net "subtract", 0 0, L_0x2a936e0; 1 drivers +L_0x2a934e0 .part v0x2960210_0, 0, 1; +L_0x2a93640 .part v0x2960210_0, 2, 1; +L_0x2a93820 .part v0x2960210_0, 0, 1; +S_0x2872230 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x2872140; + .timescale -9 -12; +L_0x2a93030/d .functor NOT 1, L_0x2a934e0, C4<0>, C4<0>, C4<0>; +L_0x2a93030 .delay (10000,10000,10000) L_0x2a93030/d; +L_0x2a930f0/d .functor AND 1, L_0x2a929a0, L_0x2a93030, C4<1>, C4<1>; +L_0x2a930f0 .delay (20000,20000,20000) L_0x2a930f0/d; +L_0x2a93200/d .functor AND 1, L_0x2a92570, L_0x2a934e0, C4<1>, C4<1>; +L_0x2a93200 .delay (20000,20000,20000) L_0x2a93200/d; +L_0x2a93310/d .functor OR 1, L_0x2a930f0, L_0x2a93200, C4<0>, C4<0>; +L_0x2a93310 .delay (20000,20000,20000) L_0x2a93310/d; +v0x2872320_0 .net "S", 0 0, L_0x2a934e0; 1 drivers +v0x28723e0_0 .alias "in0", 0 0, v0x2872a40_0; +v0x2872480_0 .alias "in1", 0 0, v0x2872f10_0; +v0x2872520_0 .net "nS", 0 0, L_0x2a93030; 1 drivers +v0x28725a0_0 .net "out0", 0 0, L_0x2a930f0; 1 drivers +v0x2872640_0 .net "out1", 0 0, L_0x2a93200; 1 drivers +v0x2872720_0 .alias "outfinal", 0 0, v0x2872af0_0; +S_0x2871bd0 .scope module, "setSLTres2" "TwoInMux" 3 335, 3 109, S_0x28714e0; + .timescale -9 -12; +L_0x2a92b70/d .functor NOT 1, L_0x2aa3020, C4<0>, C4<0>, C4<0>; +L_0x2a92b70 .delay (10000,10000,10000) L_0x2a92b70/d; +L_0x2a92c10/d .functor AND 1, L_0x2a93f50, L_0x2a92b70, C4<1>, C4<1>; +L_0x2a92c10 .delay (20000,20000,20000) L_0x2a92c10/d; +L_0x2a92d20/d .functor AND 1, C4<0>, L_0x2aa3020, C4<1>, C4<1>; +L_0x2a92d20 .delay (20000,20000,20000) L_0x2a92d20/d; +L_0x2a92dc0/d .functor OR 1, L_0x2a92c10, L_0x2a92d20, C4<0>, C4<0>; +L_0x2a92dc0 .delay (20000,20000,20000) L_0x2a92dc0/d; +v0x2871cc0_0 .alias "S", 0 0, v0x289f760_0; +v0x2871d60_0 .net "in0", 0 0, L_0x2a93f50; 1 drivers +v0x2871e00_0 .net "in1", 0 0, C4<0>; 1 drivers +v0x2871ea0_0 .net "nS", 0 0, L_0x2a92b70; 1 drivers +v0x2871f20_0 .net "out0", 0 0, L_0x2a92c10; 1 drivers +v0x2871fc0_0 .net "out1", 0 0, L_0x2a92d20; 1 drivers +v0x28720a0_0 .net "outfinal", 0 0, L_0x2a92dc0; 1 drivers +S_0x2871650 .scope module, "setSLTres3" "TwoInMux" 3 336, 3 109, S_0x28714e0; + .timescale -9 -12; +L_0x2a92eb0/d .functor NOT 1, L_0x2aa3020, C4<0>, C4<0>, C4<0>; +L_0x2a92eb0 .delay (10000,10000,10000) L_0x2a92eb0/d; +L_0x2a94360/d .functor AND 1, L_0x2a78800, L_0x2a92eb0, C4<1>, C4<1>; +L_0x2a94360 .delay (20000,20000,20000) L_0x2a94360/d; +L_0x2a94470/d .functor AND 1, L_0x2a788f0, L_0x2aa3020, C4<1>, C4<1>; +L_0x2a94470 .delay (20000,20000,20000) L_0x2a94470/d; +L_0x2a94510/d .functor OR 1, L_0x2a94360, L_0x2a94470, C4<0>, C4<0>; +L_0x2a94510 .delay (20000,20000,20000) L_0x2a94510/d; +v0x2871740_0 .alias "S", 0 0, v0x289f760_0; +v0x28717c0_0 .net "in0", 0 0, L_0x2a78800; 1 drivers +v0x2871860_0 .net "in1", 0 0, L_0x2a788f0; 1 drivers +v0x2871900_0 .net "nS", 0 0, L_0x2a92eb0; 1 drivers +v0x28719b0_0 .net "out0", 0 0, L_0x2a94360; 1 drivers +v0x2871a50_0 .net "out1", 0 0, L_0x2a94470; 1 drivers +v0x2871b30_0 .net "outfinal", 0 0, L_0x2a94510; 1 drivers +S_0x286f860 .scope generate, "sltbits[25]" "sltbits[25]" 3 332, 3 332, S_0x2864a60; + .timescale -9 -12; +P_0x286f278 .param/l "i" 3 332, +C4<011001>; +S_0x28704c0 .scope module, "attempt" "MiddleAddSubSLT" 3 334, 3 189, S_0x286f860; + .timescale -9 -12; +L_0x2a950b0/d .functor NOT 1, L_0x2a949f0, C4<0>, C4<0>, C4<0>; +L_0x2a950b0 .delay (10000,10000,10000) L_0x2a950b0/d; +L_0x2a95770/d .functor NOT 1, L_0x2a95830, C4<0>, C4<0>, C4<0>; +L_0x2a95770 .delay (10000,10000,10000) L_0x2a95770/d; +L_0x2a958d0/d .functor AND 1, L_0x2a95a10, L_0x2a95770, C4<1>, C4<1>; +L_0x2a958d0 .delay (20000,20000,20000) L_0x2a958d0/d; +L_0x2a95ab0/d .functor XOR 1, L_0x2a94950, L_0x2a95500, C4<0>, C4<0>; +L_0x2a95ab0 .delay (40000,40000,40000) L_0x2a95ab0/d; +L_0x2a95ba0/d .functor XOR 1, L_0x2a95ab0, L_0x2a94b20, C4<0>, C4<0>; +L_0x2a95ba0 .delay (40000,40000,40000) L_0x2a95ba0/d; +L_0x2a95c90/d .functor AND 1, L_0x2a94950, L_0x2a95500, C4<1>, C4<1>; +L_0x2a95c90 .delay (20000,20000,20000) L_0x2a95c90/d; +L_0x2a95e00/d .functor AND 1, L_0x2a95ab0, L_0x2a94b20, C4<1>, C4<1>; +L_0x2a95e00 .delay (20000,20000,20000) L_0x2a95e00/d; +L_0x2a95ef0/d .functor OR 1, L_0x2a95c90, L_0x2a95e00, C4<0>, C4<0>; +L_0x2a95ef0 .delay (20000,20000,20000) L_0x2a95ef0/d; +v0x2870b40_0 .net "A", 0 0, L_0x2a94950; 1 drivers +v0x2870c00_0 .net "AandB", 0 0, L_0x2a95c90; 1 drivers +v0x2870ca0_0 .net "AddSubSLTSum", 0 0, L_0x2a95ba0; 1 drivers +v0x2870d40_0 .net "AxorB", 0 0, L_0x2a95ab0; 1 drivers +v0x2870dc0_0 .net "B", 0 0, L_0x2a949f0; 1 drivers +v0x2870e70_0 .net "BornB", 0 0, L_0x2a95500; 1 drivers +v0x2870f30_0 .net "CINandAxorB", 0 0, L_0x2a95e00; 1 drivers +v0x2870fb0_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x2871030_0 .net *"_s3", 0 0, L_0x2a95830; 1 drivers +v0x28710b0_0 .net *"_s5", 0 0, L_0x2a95a10; 1 drivers +v0x2871150_0 .net "carryin", 0 0, L_0x2a94b20; 1 drivers +v0x28711f0_0 .net "carryout", 0 0, L_0x2a95ef0; 1 drivers +v0x2871290_0 .net "nB", 0 0, L_0x2a950b0; 1 drivers +v0x2871340_0 .net "nCmd2", 0 0, L_0x2a95770; 1 drivers +v0x2871440_0 .net "subtract", 0 0, L_0x2a958d0; 1 drivers +L_0x2a956d0 .part v0x2960210_0, 0, 1; +L_0x2a95830 .part v0x2960210_0, 2, 1; +L_0x2a95a10 .part v0x2960210_0, 0, 1; +S_0x28705b0 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x28704c0; + .timescale -9 -12; +L_0x2a95220/d .functor NOT 1, L_0x2a956d0, C4<0>, C4<0>, C4<0>; +L_0x2a95220 .delay (10000,10000,10000) L_0x2a95220/d; +L_0x2a952e0/d .functor AND 1, L_0x2a949f0, L_0x2a95220, C4<1>, C4<1>; +L_0x2a952e0 .delay (20000,20000,20000) L_0x2a952e0/d; +L_0x2a953f0/d .functor AND 1, L_0x2a950b0, L_0x2a956d0, C4<1>, C4<1>; +L_0x2a953f0 .delay (20000,20000,20000) L_0x2a953f0/d; +L_0x2a95500/d .functor OR 1, L_0x2a952e0, L_0x2a953f0, C4<0>, C4<0>; +L_0x2a95500 .delay (20000,20000,20000) L_0x2a95500/d; +v0x28706a0_0 .net "S", 0 0, L_0x2a956d0; 1 drivers +v0x2870760_0 .alias "in0", 0 0, v0x2870dc0_0; +v0x2870800_0 .alias "in1", 0 0, v0x2871290_0; +v0x28708a0_0 .net "nS", 0 0, L_0x2a95220; 1 drivers +v0x2870920_0 .net "out0", 0 0, L_0x2a952e0; 1 drivers +v0x28709c0_0 .net "out1", 0 0, L_0x2a953f0; 1 drivers +v0x2870aa0_0 .alias "outfinal", 0 0, v0x2870e70_0; +S_0x286ff50 .scope module, "setSLTres2" "TwoInMux" 3 335, 3 109, S_0x286f860; + .timescale -9 -12; +L_0x2a94bc0/d .functor NOT 1, L_0x2aa3020, C4<0>, C4<0>, C4<0>; +L_0x2a94bc0 .delay (10000,10000,10000) L_0x2a94bc0/d; +L_0x2a94c60/d .functor AND 1, L_0x2a94ff0, L_0x2a94bc0, C4<1>, C4<1>; +L_0x2a94c60 .delay (20000,20000,20000) L_0x2a94c60/d; +L_0x2a94d70/d .functor AND 1, C4<0>, L_0x2aa3020, C4<1>, C4<1>; +L_0x2a94d70 .delay (20000,20000,20000) L_0x2a94d70/d; +L_0x2a94e10/d .functor OR 1, L_0x2a94c60, L_0x2a94d70, C4<0>, C4<0>; +L_0x2a94e10 .delay (20000,20000,20000) L_0x2a94e10/d; +v0x2870040_0 .alias "S", 0 0, v0x289f760_0; +v0x28700e0_0 .net "in0", 0 0, L_0x2a94ff0; 1 drivers +v0x2870180_0 .net "in1", 0 0, C4<0>; 1 drivers +v0x2870220_0 .net "nS", 0 0, L_0x2a94bc0; 1 drivers +v0x28702a0_0 .net "out0", 0 0, L_0x2a94c60; 1 drivers +v0x2870340_0 .net "out1", 0 0, L_0x2a94d70; 1 drivers +v0x2870420_0 .net "outfinal", 0 0, L_0x2a94e10; 1 drivers +S_0x286f9d0 .scope module, "setSLTres3" "TwoInMux" 3 336, 3 109, S_0x286f860; + .timescale -9 -12; +L_0x2a962c0/d .functor NOT 1, L_0x2aa3020, C4<0>, C4<0>, C4<0>; +L_0x2a962c0 .delay (10000,10000,10000) L_0x2a962c0/d; +L_0x2a963b0/d .functor AND 1, L_0x2a96740, L_0x2a962c0, C4<1>, C4<1>; +L_0x2a963b0 .delay (20000,20000,20000) L_0x2a963b0/d; +L_0x2a964c0/d .functor AND 1, L_0x2a96830, L_0x2aa3020, C4<1>, C4<1>; +L_0x2a964c0 .delay (20000,20000,20000) L_0x2a964c0/d; +L_0x2a96560/d .functor OR 1, L_0x2a963b0, L_0x2a964c0, C4<0>, C4<0>; +L_0x2a96560 .delay (20000,20000,20000) L_0x2a96560/d; +v0x286fac0_0 .alias "S", 0 0, v0x289f760_0; +v0x286fb40_0 .net "in0", 0 0, L_0x2a96740; 1 drivers +v0x286fbe0_0 .net "in1", 0 0, L_0x2a96830; 1 drivers +v0x286fc80_0 .net "nS", 0 0, L_0x2a962c0; 1 drivers +v0x286fd30_0 .net "out0", 0 0, L_0x2a963b0; 1 drivers +v0x286fdd0_0 .net "out1", 0 0, L_0x2a964c0; 1 drivers +v0x286feb0_0 .net "outfinal", 0 0, L_0x2a96560; 1 drivers +S_0x286dbe0 .scope generate, "sltbits[26]" "sltbits[26]" 3 332, 3 332, S_0x2864a60; + .timescale -9 -12; +P_0x286d5f8 .param/l "i" 3 332, +C4<011010>; +S_0x286e840 .scope module, "attempt" "MiddleAddSubSLT" 3 334, 3 189, S_0x286dbe0; + .timescale -9 -12; +L_0x2a96920/d .functor NOT 1, L_0x2a96d80, C4<0>, C4<0>, C4<0>; +L_0x2a96920 .delay (10000,10000,10000) L_0x2a96920/d; +L_0x2a97930/d .functor NOT 1, L_0x2a979f0, C4<0>, C4<0>, C4<0>; +L_0x2a97930 .delay (10000,10000,10000) L_0x2a97930/d; +L_0x2a97a90/d .functor AND 1, L_0x2a97bd0, L_0x2a97930, C4<1>, C4<1>; +L_0x2a97a90 .delay (20000,20000,20000) L_0x2a97a90/d; +L_0x2a97c70/d .functor XOR 1, L_0x2a96ce0, L_0x2a976c0, C4<0>, C4<0>; +L_0x2a97c70 .delay (40000,40000,40000) L_0x2a97c70/d; +L_0x2a97d60/d .functor XOR 1, L_0x2a97c70, L_0x2a96eb0, C4<0>, C4<0>; +L_0x2a97d60 .delay (40000,40000,40000) L_0x2a97d60/d; +L_0x2a97e50/d .functor AND 1, L_0x2a96ce0, L_0x2a976c0, C4<1>, C4<1>; +L_0x2a97e50 .delay (20000,20000,20000) L_0x2a97e50/d; +L_0x2a97fc0/d .functor AND 1, L_0x2a97c70, L_0x2a96eb0, C4<1>, C4<1>; +L_0x2a97fc0 .delay (20000,20000,20000) L_0x2a97fc0/d; +L_0x2a980b0/d .functor OR 1, L_0x2a97e50, L_0x2a97fc0, C4<0>, C4<0>; +L_0x2a980b0 .delay (20000,20000,20000) L_0x2a980b0/d; +v0x286eec0_0 .net "A", 0 0, L_0x2a96ce0; 1 drivers +v0x286ef80_0 .net "AandB", 0 0, L_0x2a97e50; 1 drivers +v0x286f020_0 .net "AddSubSLTSum", 0 0, L_0x2a97d60; 1 drivers +v0x286f0c0_0 .net "AxorB", 0 0, L_0x2a97c70; 1 drivers +v0x286f140_0 .net "B", 0 0, L_0x2a96d80; 1 drivers +v0x286f1f0_0 .net "BornB", 0 0, L_0x2a976c0; 1 drivers +v0x286f2b0_0 .net "CINandAxorB", 0 0, L_0x2a97fc0; 1 drivers +v0x286f330_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x286f3b0_0 .net *"_s3", 0 0, L_0x2a979f0; 1 drivers +v0x286f430_0 .net *"_s5", 0 0, L_0x2a97bd0; 1 drivers +v0x286f4d0_0 .net "carryin", 0 0, L_0x2a96eb0; 1 drivers +v0x286f570_0 .net "carryout", 0 0, L_0x2a980b0; 1 drivers +v0x286f610_0 .net "nB", 0 0, L_0x2a96920; 1 drivers +v0x286f6c0_0 .net "nCmd2", 0 0, L_0x2a97930; 1 drivers +v0x286f7c0_0 .net "subtract", 0 0, L_0x2a97a90; 1 drivers +L_0x2a97890 .part v0x2960210_0, 0, 1; +L_0x2a979f0 .part v0x2960210_0, 2, 1; +L_0x2a97bd0 .part v0x2960210_0, 0, 1; +S_0x286e930 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x286e840; + .timescale -9 -12; +L_0x2a973e0/d .functor NOT 1, L_0x2a97890, C4<0>, C4<0>, C4<0>; +L_0x2a973e0 .delay (10000,10000,10000) L_0x2a973e0/d; +L_0x2a974a0/d .functor AND 1, L_0x2a96d80, L_0x2a973e0, C4<1>, C4<1>; +L_0x2a974a0 .delay (20000,20000,20000) L_0x2a974a0/d; +L_0x2a975b0/d .functor AND 1, L_0x2a96920, L_0x2a97890, C4<1>, C4<1>; +L_0x2a975b0 .delay (20000,20000,20000) L_0x2a975b0/d; +L_0x2a976c0/d .functor OR 1, L_0x2a974a0, L_0x2a975b0, C4<0>, C4<0>; +L_0x2a976c0 .delay (20000,20000,20000) L_0x2a976c0/d; +v0x286ea20_0 .net "S", 0 0, L_0x2a97890; 1 drivers +v0x286eae0_0 .alias "in0", 0 0, v0x286f140_0; +v0x286eb80_0 .alias "in1", 0 0, v0x286f610_0; +v0x286ec20_0 .net "nS", 0 0, L_0x2a973e0; 1 drivers +v0x286eca0_0 .net "out0", 0 0, L_0x2a974a0; 1 drivers +v0x286ed40_0 .net "out1", 0 0, L_0x2a975b0; 1 drivers +v0x286ee20_0 .alias "outfinal", 0 0, v0x286f1f0_0; +S_0x286e2d0 .scope module, "setSLTres2" "TwoInMux" 3 335, 3 109, S_0x286dbe0; + .timescale -9 -12; +L_0x2a96f50/d .functor NOT 1, L_0x2aa3020, C4<0>, C4<0>, C4<0>; +L_0x2a96f50 .delay (10000,10000,10000) L_0x2a96f50/d; +L_0x2a96ff0/d .functor AND 1, L_0x2a98be0, L_0x2a96f50, C4<1>, C4<1>; +L_0x2a96ff0 .delay (20000,20000,20000) L_0x2a96ff0/d; +L_0x2a97100/d .functor AND 1, C4<0>, L_0x2aa3020, C4<1>, C4<1>; +L_0x2a97100 .delay (20000,20000,20000) L_0x2a97100/d; +L_0x2a971a0/d .functor OR 1, L_0x2a96ff0, L_0x2a97100, C4<0>, C4<0>; +L_0x2a971a0 .delay (20000,20000,20000) L_0x2a971a0/d; +v0x286e3c0_0 .alias "S", 0 0, v0x289f760_0; +v0x286e460_0 .net "in0", 0 0, L_0x2a98be0; 1 drivers +v0x286e500_0 .net "in1", 0 0, C4<0>; 1 drivers +v0x286e5a0_0 .net "nS", 0 0, L_0x2a96f50; 1 drivers +v0x286e620_0 .net "out0", 0 0, L_0x2a96ff0; 1 drivers +v0x286e6c0_0 .net "out1", 0 0, L_0x2a97100; 1 drivers +v0x286e7a0_0 .net "outfinal", 0 0, L_0x2a971a0; 1 drivers +S_0x286dd50 .scope module, "setSLTres3" "TwoInMux" 3 336, 3 109, S_0x286dbe0; + .timescale -9 -12; +L_0x2a940d0/d .functor NOT 1, L_0x2aa3020, C4<0>, C4<0>, C4<0>; +L_0x2a940d0 .delay (10000,10000,10000) L_0x2a940d0/d; +L_0x2a941c0/d .functor AND 1, L_0x2a98300, L_0x2a940d0, C4<1>, C4<1>; +L_0x2a941c0 .delay (20000,20000,20000) L_0x2a941c0/d; +L_0x2a98fa0/d .functor AND 1, L_0x2a983f0, L_0x2aa3020, C4<1>, C4<1>; +L_0x2a98fa0 .delay (20000,20000,20000) L_0x2a98fa0/d; +L_0x2a99040/d .functor OR 1, L_0x2a941c0, L_0x2a98fa0, C4<0>, C4<0>; +L_0x2a99040 .delay (20000,20000,20000) L_0x2a99040/d; +v0x286de40_0 .alias "S", 0 0, v0x289f760_0; +v0x286dec0_0 .net "in0", 0 0, L_0x2a98300; 1 drivers +v0x286df60_0 .net "in1", 0 0, L_0x2a983f0; 1 drivers +v0x286e000_0 .net "nS", 0 0, L_0x2a940d0; 1 drivers +v0x286e0b0_0 .net "out0", 0 0, L_0x2a941c0; 1 drivers +v0x286e150_0 .net "out1", 0 0, L_0x2a98fa0; 1 drivers +v0x286e230_0 .net "outfinal", 0 0, L_0x2a99040; 1 drivers +S_0x286bed0 .scope generate, "sltbits[27]" "sltbits[27]" 3 332, 3 332, S_0x2864a60; + .timescale -9 -12; +P_0x286b898 .param/l "i" 3 332, +C4<011011>; +S_0x286cbc0 .scope module, "attempt" "MiddleAddSubSLT" 3 334, 3 189, S_0x286bed0; + .timescale -9 -12; +L_0x2a984e0/d .functor NOT 1, L_0x2a993b0, C4<0>, C4<0>, C4<0>; +L_0x2a984e0 .delay (10000,10000,10000) L_0x2a984e0/d; +L_0x2a98b60/d .functor NOT 1, L_0x2a99c00, C4<0>, C4<0>, C4<0>; +L_0x2a98b60 .delay (10000,10000,10000) L_0x2a98b60/d; +L_0x2a99ca0/d .functor AND 1, L_0x2a99de0, L_0x2a98b60, C4<1>, C4<1>; +L_0x2a99ca0 .delay (20000,20000,20000) L_0x2a99ca0/d; +L_0x2a99e80/d .functor XOR 1, L_0x2a99310, L_0x2a98990, C4<0>, C4<0>; +L_0x2a99e80 .delay (40000,40000,40000) L_0x2a99e80/d; +L_0x2a99f70/d .functor XOR 1, L_0x2a99e80, L_0x2a994e0, C4<0>, C4<0>; +L_0x2a99f70 .delay (40000,40000,40000) L_0x2a99f70/d; +L_0x2a9a060/d .functor AND 1, L_0x2a99310, L_0x2a98990, C4<1>, C4<1>; +L_0x2a9a060 .delay (20000,20000,20000) L_0x2a9a060/d; +L_0x2a9a1d0/d .functor AND 1, L_0x2a99e80, L_0x2a994e0, C4<1>, C4<1>; +L_0x2a9a1d0 .delay (20000,20000,20000) L_0x2a9a1d0/d; +L_0x2a9a2c0/d .functor OR 1, L_0x2a9a060, L_0x2a9a1d0, C4<0>, C4<0>; +L_0x2a9a2c0 .delay (20000,20000,20000) L_0x2a9a2c0/d; +v0x286d240_0 .net "A", 0 0, L_0x2a99310; 1 drivers +v0x286d300_0 .net "AandB", 0 0, L_0x2a9a060; 1 drivers +v0x286d3a0_0 .net "AddSubSLTSum", 0 0, L_0x2a99f70; 1 drivers +v0x286d440_0 .net "AxorB", 0 0, L_0x2a99e80; 1 drivers +v0x286d4c0_0 .net "B", 0 0, L_0x2a993b0; 1 drivers +v0x286d570_0 .net "BornB", 0 0, L_0x2a98990; 1 drivers +v0x286d630_0 .net "CINandAxorB", 0 0, L_0x2a9a1d0; 1 drivers +v0x286d6b0_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x286d730_0 .net *"_s3", 0 0, L_0x2a99c00; 1 drivers +v0x286d7b0_0 .net *"_s5", 0 0, L_0x2a99de0; 1 drivers +v0x286d850_0 .net "carryin", 0 0, L_0x2a994e0; 1 drivers +v0x286d8f0_0 .net "carryout", 0 0, L_0x2a9a2c0; 1 drivers +v0x286d990_0 .net "nB", 0 0, L_0x2a984e0; 1 drivers +v0x286da40_0 .net "nCmd2", 0 0, L_0x2a98b60; 1 drivers +v0x286db40_0 .net "subtract", 0 0, L_0x2a99ca0; 1 drivers +L_0x2a99b20 .part v0x2960210_0, 0, 1; +L_0x2a99c00 .part v0x2960210_0, 2, 1; +L_0x2a99de0 .part v0x2960210_0, 0, 1; +S_0x286ccb0 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x286cbc0; + .timescale -9 -12; +L_0x2a986b0/d .functor NOT 1, L_0x2a99b20, C4<0>, C4<0>, C4<0>; +L_0x2a986b0 .delay (10000,10000,10000) L_0x2a986b0/d; +L_0x2a98770/d .functor AND 1, L_0x2a993b0, L_0x2a986b0, C4<1>, C4<1>; +L_0x2a98770 .delay (20000,20000,20000) L_0x2a98770/d; +L_0x2a98880/d .functor AND 1, L_0x2a984e0, L_0x2a99b20, C4<1>, C4<1>; +L_0x2a98880 .delay (20000,20000,20000) L_0x2a98880/d; +L_0x2a98990/d .functor OR 1, L_0x2a98770, L_0x2a98880, C4<0>, C4<0>; +L_0x2a98990 .delay (20000,20000,20000) L_0x2a98990/d; +v0x286cda0_0 .net "S", 0 0, L_0x2a99b20; 1 drivers +v0x286ce60_0 .alias "in0", 0 0, v0x286d4c0_0; +v0x286cf00_0 .alias "in1", 0 0, v0x286d990_0; +v0x286cfa0_0 .net "nS", 0 0, L_0x2a986b0; 1 drivers +v0x286d020_0 .net "out0", 0 0, L_0x2a98770; 1 drivers +v0x286d0c0_0 .net "out1", 0 0, L_0x2a98880; 1 drivers +v0x286d1a0_0 .alias "outfinal", 0 0, v0x286d570_0; +S_0x286c650 .scope module, "setSLTres2" "TwoInMux" 3 335, 3 109, S_0x286bed0; + .timescale -9 -12; +L_0x2a99580/d .functor NOT 1, L_0x2aa3020, C4<0>, C4<0>, C4<0>; +L_0x2a99580 .delay (10000,10000,10000) L_0x2a99580/d; +L_0x2a99620/d .functor AND 1, L_0x2a999b0, L_0x2a99580, C4<1>, C4<1>; +L_0x2a99620 .delay (20000,20000,20000) L_0x2a99620/d; +L_0x2a99730/d .functor AND 1, C4<0>, L_0x2aa3020, C4<1>, C4<1>; +L_0x2a99730 .delay (20000,20000,20000) L_0x2a99730/d; +L_0x2a997d0/d .functor OR 1, L_0x2a99620, L_0x2a99730, C4<0>, C4<0>; +L_0x2a997d0 .delay (20000,20000,20000) L_0x2a997d0/d; +v0x286c740_0 .alias "S", 0 0, v0x289f760_0; +v0x286c7e0_0 .net "in0", 0 0, L_0x2a999b0; 1 drivers +v0x286c880_0 .net "in1", 0 0, C4<0>; 1 drivers +v0x286c920_0 .net "nS", 0 0, L_0x2a99580; 1 drivers +v0x286c9a0_0 .net "out0", 0 0, L_0x2a99620; 1 drivers +v0x286ca40_0 .net "out1", 0 0, L_0x2a99730; 1 drivers +v0x286cb20_0 .net "outfinal", 0 0, L_0x2a997d0; 1 drivers +S_0x286c040 .scope module, "setSLTres3" "TwoInMux" 3 336, 3 109, S_0x286bed0; + .timescale -9 -12; +L_0x2a9af70/d .functor NOT 1, L_0x2aa3020, C4<0>, C4<0>, C4<0>; +L_0x2a9af70 .delay (10000,10000,10000) L_0x2a9af70/d; +L_0x2a9b020/d .functor AND 1, L_0x2a9b3f0, L_0x2a9af70, C4<1>, C4<1>; +L_0x2a9b020 .delay (20000,20000,20000) L_0x2a9b020/d; +L_0x2a9b110/d .functor AND 1, L_0x2a9a5e0, L_0x2aa3020, C4<1>, C4<1>; +L_0x2a9b110 .delay (20000,20000,20000) L_0x2a9b110/d; +L_0x2a9b1e0/d .functor OR 1, L_0x2a9b020, L_0x2a9b110, C4<0>, C4<0>; +L_0x2a9b1e0 .delay (20000,20000,20000) L_0x2a9b1e0/d; +v0x286c130_0 .alias "S", 0 0, v0x289f760_0; +v0x2868860_0 .net "in0", 0 0, L_0x2a9b3f0; 1 drivers +v0x286c2e0_0 .net "in1", 0 0, L_0x2a9a5e0; 1 drivers +v0x286c380_0 .net "nS", 0 0, L_0x2a9af70; 1 drivers +v0x286c430_0 .net "out0", 0 0, L_0x2a9b020; 1 drivers +v0x286c4d0_0 .net "out1", 0 0, L_0x2a9b110; 1 drivers +v0x286c5b0_0 .net "outfinal", 0 0, L_0x2a9b1e0; 1 drivers +S_0x286a220 .scope generate, "sltbits[28]" "sltbits[28]" 3 332, 3 332, S_0x2864a60; + .timescale -9 -12; +P_0x2868088 .param/l "i" 3 332, +C4<011100>; +S_0x286ae60 .scope module, "attempt" "MiddleAddSubSLT" 3 334, 3 189, S_0x286a220; + .timescale -9 -12; +L_0x2a9a6d0/d .functor NOT 1, L_0x2a9b760, C4<0>, C4<0>, C4<0>; +L_0x2a9a6d0 .delay (10000,10000,10000) L_0x2a9a6d0/d; +L_0x2a9ae10/d .functor NOT 1, L_0x2a9be30, C4<0>, C4<0>, C4<0>; +L_0x2a9ae10 .delay (10000,10000,10000) L_0x2a9ae10/d; +L_0x2a9bed0/d .functor AND 1, L_0x2a9bfc0, L_0x2a9ae10, C4<1>, C4<1>; +L_0x2a9bed0 .delay (20000,20000,20000) L_0x2a9bed0/d; +L_0x2a9c060/d .functor XOR 1, L_0x2a9b6c0, L_0x2a9aba0, C4<0>, C4<0>; +L_0x2a9c060 .delay (40000,40000,40000) L_0x2a9c060/d; +L_0x2a9c150/d .functor XOR 1, L_0x2a9c060, L_0x2a9b890, C4<0>, C4<0>; +L_0x2a9c150 .delay (40000,40000,40000) L_0x2a9c150/d; +L_0x2a9c240/d .functor AND 1, L_0x2a9b6c0, L_0x2a9aba0, C4<1>, C4<1>; +L_0x2a9c240 .delay (20000,20000,20000) L_0x2a9c240/d; +L_0x2a9c3b0/d .functor AND 1, L_0x2a9c060, L_0x2a9b890, C4<1>, C4<1>; +L_0x2a9c3b0 .delay (20000,20000,20000) L_0x2a9c3b0/d; +L_0x2a9c4a0/d .functor OR 1, L_0x2a9c240, L_0x2a9c3b0, C4<0>, C4<0>; +L_0x2a9c4a0 .delay (20000,20000,20000) L_0x2a9c4a0/d; +v0x286b4e0_0 .net "A", 0 0, L_0x2a9b6c0; 1 drivers +v0x286b5a0_0 .net "AandB", 0 0, L_0x2a9c240; 1 drivers +v0x286b640_0 .net "AddSubSLTSum", 0 0, L_0x2a9c150; 1 drivers +v0x286b6e0_0 .net "AxorB", 0 0, L_0x2a9c060; 1 drivers +v0x286b760_0 .net "B", 0 0, L_0x2a9b760; 1 drivers +v0x286b810_0 .net "BornB", 0 0, L_0x2a9aba0; 1 drivers +v0x286b8d0_0 .net "CINandAxorB", 0 0, L_0x2a9c3b0; 1 drivers +v0x286b950_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x286ba20_0 .net *"_s3", 0 0, L_0x2a9be30; 1 drivers +v0x286baa0_0 .net *"_s5", 0 0, L_0x2a9bfc0; 1 drivers +v0x286bb40_0 .net "carryin", 0 0, L_0x2a9b890; 1 drivers +v0x286bbe0_0 .net "carryout", 0 0, L_0x2a9c4a0; 1 drivers +v0x286bc80_0 .net "nB", 0 0, L_0x2a9a6d0; 1 drivers +v0x286bd30_0 .net "nCmd2", 0 0, L_0x2a9ae10; 1 drivers +v0x286be30_0 .net "subtract", 0 0, L_0x2a9bed0; 1 drivers +L_0x2a9ad70 .part v0x2960210_0, 0, 1; +L_0x2a9be30 .part v0x2960210_0, 2, 1; +L_0x2a9bfc0 .part v0x2960210_0, 0, 1; +S_0x286af50 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x286ae60; + .timescale -9 -12; +L_0x2a9a8c0/d .functor NOT 1, L_0x2a9ad70, C4<0>, C4<0>, C4<0>; +L_0x2a9a8c0 .delay (10000,10000,10000) L_0x2a9a8c0/d; +L_0x2a9a980/d .functor AND 1, L_0x2a9b760, L_0x2a9a8c0, C4<1>, C4<1>; +L_0x2a9a980 .delay (20000,20000,20000) L_0x2a9a980/d; +L_0x2a9aa90/d .functor AND 1, L_0x2a9a6d0, L_0x2a9ad70, C4<1>, C4<1>; +L_0x2a9aa90 .delay (20000,20000,20000) L_0x2a9aa90/d; +L_0x2a9aba0/d .functor OR 1, L_0x2a9a980, L_0x2a9aa90, C4<0>, C4<0>; +L_0x2a9aba0 .delay (20000,20000,20000) L_0x2a9aba0/d; +v0x286b040_0 .net "S", 0 0, L_0x2a9ad70; 1 drivers +v0x286b100_0 .alias "in0", 0 0, v0x286b760_0; +v0x286b1a0_0 .alias "in1", 0 0, v0x286bc80_0; +v0x286b240_0 .net "nS", 0 0, L_0x2a9a8c0; 1 drivers +v0x286b2c0_0 .net "out0", 0 0, L_0x2a9a980; 1 drivers +v0x286b360_0 .net "out1", 0 0, L_0x2a9aa90; 1 drivers +v0x286b440_0 .alias "outfinal", 0 0, v0x286b810_0; +S_0x286a8f0 .scope module, "setSLTres2" "TwoInMux" 3 335, 3 109, S_0x286a220; + .timescale -9 -12; +L_0x2a9b930/d .functor NOT 1, L_0x2aa3020, C4<0>, C4<0>, C4<0>; +L_0x2a9b930 .delay (10000,10000,10000) L_0x2a9b930/d; +L_0x2a9b9d0/d .functor AND 1, L_0x2a9bd60, L_0x2a9b930, C4<1>, C4<1>; +L_0x2a9b9d0 .delay (20000,20000,20000) L_0x2a9b9d0/d; +L_0x2a9bae0/d .functor AND 1, C4<0>, L_0x2aa3020, C4<1>, C4<1>; +L_0x2a9bae0 .delay (20000,20000,20000) L_0x2a9bae0/d; +L_0x2a9bb80/d .functor OR 1, L_0x2a9b9d0, L_0x2a9bae0, C4<0>, C4<0>; +L_0x2a9bb80 .delay (20000,20000,20000) L_0x2a9bb80/d; +v0x286a9e0_0 .alias "S", 0 0, v0x289f760_0; +v0x286aa80_0 .net "in0", 0 0, L_0x2a9bd60; 1 drivers +v0x286ab20_0 .net "in1", 0 0, C4<0>; 1 drivers +v0x286abc0_0 .net "nS", 0 0, L_0x2a9b930; 1 drivers +v0x286ac40_0 .net "out0", 0 0, L_0x2a9b9d0; 1 drivers +v0x286ace0_0 .net "out1", 0 0, L_0x2a9bae0; 1 drivers +v0x286adc0_0 .net "outfinal", 0 0, L_0x2a9bb80; 1 drivers +S_0x286a370 .scope module, "setSLTres3" "TwoInMux" 3 336, 3 109, S_0x286a220; + .timescale -9 -12; +L_0x2a98d60/d .functor NOT 1, L_0x2aa3020, C4<0>, C4<0>, C4<0>; +L_0x2a98d60 .delay (10000,10000,10000) L_0x2a98d60/d; +L_0x2a98e70/d .functor AND 1, L_0x2a9c6d0, L_0x2a98d60, C4<1>, C4<1>; +L_0x2a98e70 .delay (20000,20000,20000) L_0x2a98e70/d; +L_0x2a9d390/d .functor AND 1, L_0x2a9c7c0, L_0x2aa3020, C4<1>, C4<1>; +L_0x2a9d390 .delay (20000,20000,20000) L_0x2a9d390/d; +L_0x2a9d430/d .functor OR 1, L_0x2a98e70, L_0x2a9d390, C4<0>, C4<0>; +L_0x2a9d430 .delay (20000,20000,20000) L_0x2a9d430/d; +v0x286a460_0 .alias "S", 0 0, v0x289f760_0; +v0x286a4e0_0 .net "in0", 0 0, L_0x2a9c6d0; 1 drivers +v0x286a580_0 .net "in1", 0 0, L_0x2a9c7c0; 1 drivers +v0x286a620_0 .net "nS", 0 0, L_0x2a98d60; 1 drivers +v0x286a6d0_0 .net "out0", 0 0, L_0x2a98e70; 1 drivers +v0x286a770_0 .net "out1", 0 0, L_0x2a9d390; 1 drivers +v0x286a850_0 .net "outfinal", 0 0, L_0x2a9d430; 1 drivers +S_0x2868580 .scope generate, "sltbits[29]" "sltbits[29]" 3 332, 3 332, S_0x2864a60; + .timescale -9 -12; +P_0x2867f48 .param/l "i" 3 332, +C4<011101>; +S_0x2869270 .scope module, "attempt" "MiddleAddSubSLT" 3 334, 3 189, S_0x2868580; + .timescale -9 -12; +L_0x2a9c8b0/d .functor NOT 1, L_0x2a9d7a0, C4<0>, C4<0>, C4<0>; +L_0x2a9c8b0 .delay (10000,10000,10000) L_0x2a9c8b0/d; +L_0x2a9cfb0/d .functor NOT 1, L_0x2a9e000, C4<0>, C4<0>, C4<0>; +L_0x2a9cfb0 .delay (10000,10000,10000) L_0x2a9cfb0/d; +L_0x2a9e0a0/d .functor AND 1, L_0x2a9e1e0, L_0x2a9cfb0, C4<1>, C4<1>; +L_0x2a9e0a0 .delay (20000,20000,20000) L_0x2a9e0a0/d; +L_0x2a9e280/d .functor XOR 1, L_0x2a9d700, L_0x2a9cd40, C4<0>, C4<0>; +L_0x2a9e280 .delay (40000,40000,40000) L_0x2a9e280/d; +L_0x2a9e370/d .functor XOR 1, L_0x2a9e280, L_0x2a9d8d0, C4<0>, C4<0>; +L_0x2a9e370 .delay (40000,40000,40000) L_0x2a9e370/d; +L_0x2a9e460/d .functor AND 1, L_0x2a9d700, L_0x2a9cd40, C4<1>, C4<1>; +L_0x2a9e460 .delay (20000,20000,20000) L_0x2a9e460/d; +L_0x2a9e5d0/d .functor AND 1, L_0x2a9e280, L_0x2a9d8d0, C4<1>, C4<1>; +L_0x2a9e5d0 .delay (20000,20000,20000) L_0x2a9e5d0/d; +L_0x2a9e6c0/d .functor OR 1, L_0x2a9e460, L_0x2a9e5d0, C4<0>, C4<0>; +L_0x2a9e6c0 .delay (20000,20000,20000) L_0x2a9e6c0/d; +v0x28698f0_0 .net "A", 0 0, L_0x2a9d700; 1 drivers +v0x28699b0_0 .net "AandB", 0 0, L_0x2a9e460; 1 drivers +v0x2869a50_0 .net "AddSubSLTSum", 0 0, L_0x2a9e370; 1 drivers +v0x2869af0_0 .net "AxorB", 0 0, L_0x2a9e280; 1 drivers +v0x2869b70_0 .net "B", 0 0, L_0x2a9d7a0; 1 drivers +v0x2869c20_0 .net "BornB", 0 0, L_0x2a9cd40; 1 drivers +v0x2869ce0_0 .net "CINandAxorB", 0 0, L_0x2a9e5d0; 1 drivers +v0x2869d60_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x2869de0_0 .net *"_s3", 0 0, L_0x2a9e000; 1 drivers +v0x2869e60_0 .net *"_s5", 0 0, L_0x2a9e1e0; 1 drivers +v0x2869f00_0 .net "carryin", 0 0, L_0x2a9d8d0; 1 drivers +v0x2869fa0_0 .net "carryout", 0 0, L_0x2a9e6c0; 1 drivers +v0x286a020_0 .net "nB", 0 0, L_0x2a9c8b0; 1 drivers +v0x286a0a0_0 .net "nCmd2", 0 0, L_0x2a9cfb0; 1 drivers +v0x286a1a0_0 .net "subtract", 0 0, L_0x2a9e0a0; 1 drivers +L_0x2a9cf10 .part v0x2960210_0, 0, 1; +L_0x2a9e000 .part v0x2960210_0, 2, 1; +L_0x2a9e1e0 .part v0x2960210_0, 0, 1; +S_0x2869360 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x2869270; + .timescale -9 -12; +L_0x2a9ca60/d .functor NOT 1, L_0x2a9cf10, C4<0>, C4<0>, C4<0>; +L_0x2a9ca60 .delay (10000,10000,10000) L_0x2a9ca60/d; +L_0x2a9cb20/d .functor AND 1, L_0x2a9d7a0, L_0x2a9ca60, C4<1>, C4<1>; +L_0x2a9cb20 .delay (20000,20000,20000) L_0x2a9cb20/d; +L_0x2a9cc30/d .functor AND 1, L_0x2a9c8b0, L_0x2a9cf10, C4<1>, C4<1>; +L_0x2a9cc30 .delay (20000,20000,20000) L_0x2a9cc30/d; +L_0x2a9cd40/d .functor OR 1, L_0x2a9cb20, L_0x2a9cc30, C4<0>, C4<0>; +L_0x2a9cd40 .delay (20000,20000,20000) L_0x2a9cd40/d; +v0x2869450_0 .net "S", 0 0, L_0x2a9cf10; 1 drivers +v0x2869510_0 .alias "in0", 0 0, v0x2869b70_0; +v0x28695b0_0 .alias "in1", 0 0, v0x286a020_0; +v0x2869650_0 .net "nS", 0 0, L_0x2a9ca60; 1 drivers +v0x28696d0_0 .net "out0", 0 0, L_0x2a9cb20; 1 drivers +v0x2869770_0 .net "out1", 0 0, L_0x2a9cc30; 1 drivers +v0x2869850_0 .alias "outfinal", 0 0, v0x2869c20_0; +S_0x2868d00 .scope module, "setSLTres2" "TwoInMux" 3 335, 3 109, S_0x2868580; + .timescale -9 -12; +L_0x2a9d970/d .functor NOT 1, L_0x2aa3020, C4<0>, C4<0>, C4<0>; +L_0x2a9d970 .delay (10000,10000,10000) L_0x2a9d970/d; +L_0x2a9da10/d .functor AND 1, L_0x2a9dda0, L_0x2a9d970, C4<1>, C4<1>; +L_0x2a9da10 .delay (20000,20000,20000) L_0x2a9da10/d; +L_0x2a9db20/d .functor AND 1, C4<0>, L_0x2aa3020, C4<1>, C4<1>; +L_0x2a9db20 .delay (20000,20000,20000) L_0x2a9db20/d; +L_0x2a9dbc0/d .functor OR 1, L_0x2a9da10, L_0x2a9db20, C4<0>, C4<0>; +L_0x2a9dbc0 .delay (20000,20000,20000) L_0x2a9dbc0/d; +v0x2868df0_0 .alias "S", 0 0, v0x289f760_0; +v0x2868e90_0 .net "in0", 0 0, L_0x2a9dda0; 1 drivers +v0x2868f30_0 .net "in1", 0 0, C4<0>; 1 drivers +v0x2868fd0_0 .net "nS", 0 0, L_0x2a9d970; 1 drivers +v0x2869050_0 .net "out0", 0 0, L_0x2a9da10; 1 drivers +v0x28690f0_0 .net "out1", 0 0, L_0x2a9db20; 1 drivers +v0x28691d0_0 .net "outfinal", 0 0, L_0x2a9dbc0; 1 drivers +S_0x28686f0 .scope module, "setSLTres3" "TwoInMux" 3 336, 3 109, S_0x2868580; + .timescale -9 -12; +L_0x2a9df20/d .functor NOT 1, L_0x2aa3020, C4<0>, C4<0>, C4<0>; +L_0x2a9df20 .delay (10000,10000,10000) L_0x2a9df20/d; +L_0x2a9f420/d .functor AND 1, L_0x2a9f7c0, L_0x2a9df20, C4<1>, C4<1>; +L_0x2a9f420 .delay (20000,20000,20000) L_0x2a9f420/d; +L_0x2a9f510/d .functor AND 1, L_0x2a9e9e0, L_0x2aa3020, C4<1>, C4<1>; +L_0x2a9f510 .delay (20000,20000,20000) L_0x2a9f510/d; +L_0x2a9f5b0/d .functor OR 1, L_0x2a9f420, L_0x2a9f510, C4<0>, C4<0>; +L_0x2a9f5b0 .delay (20000,20000,20000) L_0x2a9f5b0/d; +v0x28687e0_0 .alias "S", 0 0, v0x289f760_0; +v0x28688f0_0 .net "in0", 0 0, L_0x2a9f7c0; 1 drivers +v0x2868990_0 .net "in1", 0 0, L_0x2a9e9e0; 1 drivers +v0x2868a30_0 .net "nS", 0 0, L_0x2a9df20; 1 drivers +v0x2868ae0_0 .net "out0", 0 0, L_0x2a9f420; 1 drivers +v0x2868b80_0 .net "out1", 0 0, L_0x2a9f510; 1 drivers +v0x2868c60_0 .net "outfinal", 0 0, L_0x2a9f5b0; 1 drivers +S_0x28668e0 .scope generate, "sltbits[30]" "sltbits[30]" 3 332, 3 332, S_0x2864a60; + .timescale -9 -12; +P_0x2866288 .param/l "i" 3 332, +C4<011110>; +S_0x2867510 .scope module, "attempt" "MiddleAddSubSLT" 3 334, 3 189, S_0x28668e0; + .timescale -9 -12; +L_0x2a9ead0/d .functor NOT 1, L_0x2a9fb30, C4<0>, C4<0>, C4<0>; +L_0x2a9ead0 .delay (10000,10000,10000) L_0x2a9ead0/d; +L_0x2a9f210/d .functor NOT 1, L_0x2a9f2d0, C4<0>, C4<0>, C4<0>; +L_0x2a9f210 .delay (10000,10000,10000) L_0x2a9f210/d; +L_0x2a9f370/d .functor AND 1, L_0x2aa0390, L_0x2a9f210, C4<1>, C4<1>; +L_0x2a9f370 .delay (20000,20000,20000) L_0x2a9f370/d; +L_0x2aa0430/d .functor XOR 1, L_0x2a9fa90, L_0x2a9efa0, C4<0>, C4<0>; +L_0x2aa0430 .delay (40000,40000,40000) L_0x2aa0430/d; +L_0x2aa0520/d .functor XOR 1, L_0x2aa0430, L_0x2a9fc60, C4<0>, C4<0>; +L_0x2aa0520 .delay (40000,40000,40000) L_0x2aa0520/d; +L_0x2aa0610/d .functor AND 1, L_0x2a9fa90, L_0x2a9efa0, C4<1>, C4<1>; +L_0x2aa0610 .delay (20000,20000,20000) L_0x2aa0610/d; +L_0x2aa0780/d .functor AND 1, L_0x2aa0430, L_0x2a9fc60, C4<1>, C4<1>; +L_0x2aa0780 .delay (20000,20000,20000) L_0x2aa0780/d; +L_0x2aa0870/d .functor OR 1, L_0x2aa0610, L_0x2aa0780, C4<0>, C4<0>; +L_0x2aa0870 .delay (20000,20000,20000) L_0x2aa0870/d; +v0x2867b90_0 .net "A", 0 0, L_0x2a9fa90; 1 drivers +v0x2867c50_0 .net "AandB", 0 0, L_0x2aa0610; 1 drivers +v0x2867cf0_0 .net "AddSubSLTSum", 0 0, L_0x2aa0520; 1 drivers +v0x2867d90_0 .net "AxorB", 0 0, L_0x2aa0430; 1 drivers +v0x2867e10_0 .net "B", 0 0, L_0x2a9fb30; 1 drivers +v0x2867ec0_0 .net "BornB", 0 0, L_0x2a9efa0; 1 drivers +v0x2867f80_0 .net "CINandAxorB", 0 0, L_0x2aa0780; 1 drivers +v0x2868000_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x28680d0_0 .net *"_s3", 0 0, L_0x2a9f2d0; 1 drivers +v0x2868150_0 .net *"_s5", 0 0, L_0x2aa0390; 1 drivers +v0x28681f0_0 .net "carryin", 0 0, L_0x2a9fc60; 1 drivers +v0x2868290_0 .net "carryout", 0 0, L_0x2aa0870; 1 drivers +v0x2868330_0 .net "nB", 0 0, L_0x2a9ead0; 1 drivers +v0x28683e0_0 .net "nCmd2", 0 0, L_0x2a9f210; 1 drivers +v0x28684e0_0 .net "subtract", 0 0, L_0x2a9f370; 1 drivers +L_0x2a9f170 .part v0x2960210_0, 0, 1; +L_0x2a9f2d0 .part v0x2960210_0, 2, 1; +L_0x2aa0390 .part v0x2960210_0, 0, 1; +S_0x2867600 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x2867510; + .timescale -9 -12; +L_0x2a9ecc0/d .functor NOT 1, L_0x2a9f170, C4<0>, C4<0>, C4<0>; +L_0x2a9ecc0 .delay (10000,10000,10000) L_0x2a9ecc0/d; +L_0x2a9ed80/d .functor AND 1, L_0x2a9fb30, L_0x2a9ecc0, C4<1>, C4<1>; +L_0x2a9ed80 .delay (20000,20000,20000) L_0x2a9ed80/d; +L_0x2a9ee90/d .functor AND 1, L_0x2a9ead0, L_0x2a9f170, C4<1>, C4<1>; +L_0x2a9ee90 .delay (20000,20000,20000) L_0x2a9ee90/d; +L_0x2a9efa0/d .functor OR 1, L_0x2a9ed80, L_0x2a9ee90, C4<0>, C4<0>; +L_0x2a9efa0 .delay (20000,20000,20000) L_0x2a9efa0/d; +v0x28676f0_0 .net "S", 0 0, L_0x2a9f170; 1 drivers +v0x28677b0_0 .alias "in0", 0 0, v0x2867e10_0; +v0x2867850_0 .alias "in1", 0 0, v0x2868330_0; +v0x28678f0_0 .net "nS", 0 0, L_0x2a9ecc0; 1 drivers +v0x2867970_0 .net "out0", 0 0, L_0x2a9ed80; 1 drivers +v0x2867a10_0 .net "out1", 0 0, L_0x2a9ee90; 1 drivers +v0x2867af0_0 .alias "outfinal", 0 0, v0x2867ec0_0; +S_0x2866fa0 .scope module, "setSLTres2" "TwoInMux" 3 335, 3 109, S_0x28668e0; + .timescale -9 -12; +L_0x2a9fd00/d .functor NOT 1, L_0x2aa3020, C4<0>, C4<0>, C4<0>; +L_0x2a9fd00 .delay (10000,10000,10000) L_0x2a9fd00/d; +L_0x2a9fda0/d .functor AND 1, L_0x2aa0130, L_0x2a9fd00, C4<1>, C4<1>; +L_0x2a9fda0 .delay (20000,20000,20000) L_0x2a9fda0/d; +L_0x2a9feb0/d .functor AND 1, C4<0>, L_0x2aa3020, C4<1>, C4<1>; +L_0x2a9feb0 .delay (20000,20000,20000) L_0x2a9feb0/d; +L_0x2a9ff50/d .functor OR 1, L_0x2a9fda0, L_0x2a9feb0, C4<0>, C4<0>; +L_0x2a9ff50 .delay (20000,20000,20000) L_0x2a9ff50/d; +v0x2867090_0 .alias "S", 0 0, v0x289f760_0; +v0x2867130_0 .net "in0", 0 0, L_0x2aa0130; 1 drivers +v0x28671d0_0 .net "in1", 0 0, C4<0>; 1 drivers +v0x2867270_0 .net "nS", 0 0, L_0x2a9fd00; 1 drivers +v0x28672f0_0 .net "out0", 0 0, L_0x2a9fda0; 1 drivers +v0x2867390_0 .net "out1", 0 0, L_0x2a9feb0; 1 drivers +v0x2867470_0 .net "outfinal", 0 0, L_0x2a9ff50; 1 drivers +S_0x2866a50 .scope module, "setSLTres3" "TwoInMux" 3 336, 3 109, S_0x28668e0; + .timescale -9 -12; +L_0x2a9d140/d .functor NOT 1, L_0x2aa3020, C4<0>, C4<0>, C4<0>; +L_0x2a9d140 .delay (10000,10000,10000) L_0x2a9d140/d; +L_0x2a9d250/d .functor AND 1, L_0x2aa0aa0, L_0x2a9d140, C4<1>, C4<1>; +L_0x2a9d250 .delay (20000,20000,20000) L_0x2a9d250/d; +L_0x2aa1740/d .functor AND 1, L_0x2aa0b90, L_0x2aa3020, C4<1>, C4<1>; +L_0x2aa1740 .delay (20000,20000,20000) L_0x2aa1740/d; +L_0x2aa17e0/d .functor OR 1, L_0x2a9d250, L_0x2aa1740, C4<0>, C4<0>; +L_0x2aa17e0 .delay (20000,20000,20000) L_0x2aa17e0/d; +v0x2866b40_0 .alias "S", 0 0, v0x289f760_0; +v0x2866bc0_0 .net "in0", 0 0, L_0x2aa0aa0; 1 drivers +v0x2866c60_0 .net "in1", 0 0, L_0x2aa0b90; 1 drivers +v0x2866d00_0 .net "nS", 0 0, L_0x2a9d140; 1 drivers +v0x2866d80_0 .net "out0", 0 0, L_0x2a9d250; 1 drivers +v0x2866e20_0 .net "out1", 0 0, L_0x2aa1740; 1 drivers +v0x2866f00_0 .net "outfinal", 0 0, L_0x2aa17e0; 1 drivers +S_0x2864bb0 .scope generate, "sltbits[31]" "sltbits[31]" 3 332, 3 332, S_0x2864a60; + .timescale -9 -12; +P_0x2864ca8 .param/l "i" 3 332, +C4<011111>; +S_0x2865850 .scope module, "attempt" "MiddleAddSubSLT" 3 334, 3 189, S_0x2864bb0; + .timescale -9 -12; +L_0x2aa0c80/d .functor NOT 1, L_0x2aa1b50, C4<0>, C4<0>, C4<0>; +L_0x2aa0c80 .delay (10000,10000,10000) L_0x2aa0c80/d; +L_0x2aa13a0/d .functor NOT 1, L_0x2aa2420, C4<0>, C4<0>, C4<0>; +L_0x2aa13a0 .delay (10000,10000,10000) L_0x2aa13a0/d; +L_0x2aa1460/d .functor AND 1, L_0x2aa25a0, L_0x2aa13a0, C4<1>, C4<1>; +L_0x2aa1460 .delay (20000,20000,20000) L_0x2aa1460/d; +L_0x2aa2640/d .functor XOR 1, L_0x2aa1ab0, L_0x2aa1130, C4<0>, C4<0>; +L_0x2aa2640 .delay (40000,40000,40000) L_0x2aa2640/d; +L_0x2aa2730/d .functor XOR 1, L_0x2aa2640, L_0x2aa1c80, C4<0>, C4<0>; +L_0x2aa2730 .delay (40000,40000,40000) L_0x2aa2730/d; +L_0x2aa2820/d .functor AND 1, L_0x2aa1ab0, L_0x2aa1130, C4<1>, C4<1>; +L_0x2aa2820 .delay (20000,20000,20000) L_0x2aa2820/d; +L_0x2aa2990/d .functor AND 1, L_0x2aa2640, L_0x2aa1c80, C4<1>, C4<1>; +L_0x2aa2990 .delay (20000,20000,20000) L_0x2aa2990/d; +L_0x2aa2a80/d .functor OR 1, L_0x2aa2820, L_0x2aa2990, C4<0>, C4<0>; +L_0x2aa2a80 .delay (20000,20000,20000) L_0x2aa2a80/d; +v0x2865ed0_0 .net "A", 0 0, L_0x2aa1ab0; 1 drivers +v0x2865f90_0 .net "AandB", 0 0, L_0x2aa2820; 1 drivers +v0x2866030_0 .net "AddSubSLTSum", 0 0, L_0x2aa2730; 1 drivers +v0x28660d0_0 .net "AxorB", 0 0, L_0x2aa2640; 1 drivers +v0x2866150_0 .net "B", 0 0, L_0x2aa1b50; 1 drivers +v0x2866200_0 .net "BornB", 0 0, L_0x2aa1130; 1 drivers +v0x28662c0_0 .net "CINandAxorB", 0 0, L_0x2aa2990; 1 drivers +v0x2866340_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x28663c0_0 .net *"_s3", 0 0, L_0x2aa2420; 1 drivers +v0x2866440_0 .net *"_s5", 0 0, L_0x2aa25a0; 1 drivers +v0x28664e0_0 .net "carryin", 0 0, L_0x2aa1c80; 1 drivers +v0x2866580_0 .net "carryout", 0 0, L_0x2aa2a80; 1 drivers +v0x2866690_0 .net "nB", 0 0, L_0x2aa0c80; 1 drivers +v0x2866740_0 .net "nCmd2", 0 0, L_0x2aa13a0; 1 drivers +v0x2866840_0 .net "subtract", 0 0, L_0x2aa1460; 1 drivers +L_0x2aa1300 .part v0x2960210_0, 0, 1; +L_0x2aa2420 .part v0x2960210_0, 2, 1; +L_0x2aa25a0 .part v0x2960210_0, 0, 1; +S_0x2865940 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x2865850; + .timescale -9 -12; +L_0x2aa0e50/d .functor NOT 1, L_0x2aa1300, C4<0>, C4<0>, C4<0>; +L_0x2aa0e50 .delay (10000,10000,10000) L_0x2aa0e50/d; +L_0x2aa0f10/d .functor AND 1, L_0x2aa1b50, L_0x2aa0e50, C4<1>, C4<1>; +L_0x2aa0f10 .delay (20000,20000,20000) L_0x2aa0f10/d; +L_0x2aa1020/d .functor AND 1, L_0x2aa0c80, L_0x2aa1300, C4<1>, C4<1>; +L_0x2aa1020 .delay (20000,20000,20000) L_0x2aa1020/d; +L_0x2aa1130/d .functor OR 1, L_0x2aa0f10, L_0x2aa1020, C4<0>, C4<0>; +L_0x2aa1130 .delay (20000,20000,20000) L_0x2aa1130/d; +v0x2865a30_0 .net "S", 0 0, L_0x2aa1300; 1 drivers +v0x2865af0_0 .alias "in0", 0 0, v0x2866150_0; +v0x2865b90_0 .alias "in1", 0 0, v0x2866690_0; +v0x2865c30_0 .net "nS", 0 0, L_0x2aa0e50; 1 drivers +v0x2865cb0_0 .net "out0", 0 0, L_0x2aa0f10; 1 drivers +v0x2865d50_0 .net "out1", 0 0, L_0x2aa1020; 1 drivers +v0x2865e30_0 .alias "outfinal", 0 0, v0x2866200_0; +S_0x28652d0 .scope module, "setSLTres2" "TwoInMux" 3 335, 3 109, S_0x2864bb0; + .timescale -9 -12; +L_0x2aa1d20/d .functor NOT 1, L_0x2aa3020, C4<0>, C4<0>, C4<0>; +L_0x2aa1d20 .delay (10000,10000,10000) L_0x2aa1d20/d; +L_0x2aa1dc0/d .functor AND 1, L_0x2aa2150, L_0x2aa1d20, C4<1>, C4<1>; +L_0x2aa1dc0 .delay (20000,20000,20000) L_0x2aa1dc0/d; +L_0x2aa1ed0/d .functor AND 1, C4<0>, L_0x2aa3020, C4<1>, C4<1>; +L_0x2aa1ed0 .delay (20000,20000,20000) L_0x2aa1ed0/d; +L_0x2aa1f70/d .functor OR 1, L_0x2aa1dc0, L_0x2aa1ed0, C4<0>, C4<0>; +L_0x2aa1f70 .delay (20000,20000,20000) L_0x2aa1f70/d; +v0x28653c0_0 .alias "S", 0 0, v0x289f760_0; +v0x2865460_0 .net "in0", 0 0, L_0x2aa2150; 1 drivers +v0x28654e0_0 .net "in1", 0 0, C4<0>; 1 drivers +v0x2865580_0 .net "nS", 0 0, L_0x2aa1d20; 1 drivers +v0x2865630_0 .net "out0", 0 0, L_0x2aa1dc0; 1 drivers +v0x28656d0_0 .net "out1", 0 0, L_0x2aa1ed0; 1 drivers +v0x28657b0_0 .net "outfinal", 0 0, L_0x2aa1f70; 1 drivers +S_0x2864d60 .scope module, "setSLTres3" "TwoInMux" 3 336, 3 109, S_0x2864bb0; + .timescale -9 -12; +L_0x2aa22d0/d .functor NOT 1, L_0x2aa3020, C4<0>, C4<0>, C4<0>; +L_0x2aa22d0 .delay (10000,10000,10000) L_0x2aa22d0/d; +L_0x2aa3840/d .functor AND 1, L_0x2aa3b70, L_0x2aa22d0, C4<1>, C4<1>; +L_0x2aa3840 .delay (20000,20000,20000) L_0x2aa3840/d; +L_0x2aa38f0/d .functor AND 1, L_0x2aa2da0, L_0x2aa3020, C4<1>, C4<1>; +L_0x2aa38f0 .delay (20000,20000,20000) L_0x2aa38f0/d; +L_0x2aa3990/d .functor OR 1, L_0x2aa3840, L_0x2aa38f0, C4<0>, C4<0>; +L_0x2aa3990 .delay (20000,20000,20000) L_0x2aa3990/d; +v0x2864e50_0 .alias "S", 0 0, v0x289f760_0; +v0x2864ef0_0 .net "in0", 0 0, L_0x2aa3b70; 1 drivers +v0x2864f90_0 .net "in1", 0 0, L_0x2aa2da0; 1 drivers +v0x2865030_0 .net "nS", 0 0, L_0x2aa22d0; 1 drivers +v0x28650b0_0 .net "out0", 0 0, L_0x2aa3840; 1 drivers +v0x2865150_0 .net "out1", 0 0, L_0x2aa38f0; 1 drivers +v0x2865230_0 .net "outfinal", 0 0, L_0x2aa3990; 1 drivers +S_0x2840e20 .scope module, "trial" "AddSubSLT32" 3 386, 3 267, S_0x25e6a40; + .timescale -9 -12; +P_0x2840f18 .param/l "size" 3 281, +C4<0100000>; +L_0x2ad5950/d .functor OR 1, L_0x2ad59d0, C4<0>, C4<0>, C4<0>; +L_0x2ad5950 .delay (20000,20000,20000) L_0x2ad5950/d; +L_0x2abcea0/d .functor XOR 1, RS_0x7f507e9ad6e8, L_0x2abcfb0, C4<0>, C4<0>; +L_0x2abcea0 .delay (40000,40000,40000) L_0x2abcea0/d; +v0x2864310_0 .alias "A", 31 0, v0x295f580_0; +v0x28643b0_0 .alias "AddSubSLTSum", 31 0, v0x295ff30_0; +v0x2864450_0 .alias "B", 31 0, v0x295f6a0_0; +RS_0x7f507e9ad5f8/0/0 .resolv tri, L_0x2aa89e0, L_0x2aa9f00, L_0x2aab440, L_0x2aaca40; +RS_0x7f507e9ad5f8/0/4 .resolv tri, L_0x2aadfe0, L_0x2aaf510, L_0x2ab0a30, L_0x2ab1f50; +RS_0x7f507e9ad5f8/0/8 .resolv tri, L_0x2ab3560, L_0x2ab4a70, L_0x2ab5f80, L_0x2ab7490; +RS_0x7f507e9ad5f8/0/12 .resolv tri, L_0x2ab8990, L_0x2ab9ea0, L_0x2abb3b0, L_0x2abc7e0; +RS_0x7f507e9ad5f8/0/16 .resolv tri, L_0x2abdea0, L_0x2abf310, L_0x2ac07c0, L_0x2ac1b90; +RS_0x7f507e9ad5f8/0/20 .resolv tri, L_0x2ac2f50, L_0x2ac4460, L_0x2ac5820, L_0x2ac6c60; +RS_0x7f507e9ad5f8/0/24 .resolv tri, L_0x2ac8920, L_0x2ac9e00, L_0x2997fb0, L_0x29994e0; +RS_0x7f507e9ad5f8/0/28 .resolv tri, L_0x299a9c0, L_0x2ad31f0, L_0x2a36e10, L_0x2ad6370; +RS_0x7f507e9ad5f8/1/0 .resolv tri, RS_0x7f507e9ad5f8/0/0, RS_0x7f507e9ad5f8/0/4, RS_0x7f507e9ad5f8/0/8, RS_0x7f507e9ad5f8/0/12; +RS_0x7f507e9ad5f8/1/4 .resolv tri, RS_0x7f507e9ad5f8/0/16, RS_0x7f507e9ad5f8/0/20, RS_0x7f507e9ad5f8/0/24, RS_0x7f507e9ad5f8/0/28; +RS_0x7f507e9ad5f8 .resolv tri, RS_0x7f507e9ad5f8/1/0, RS_0x7f507e9ad5f8/1/4, C4, C4; +v0x28644d0_0 .net8 "CarryoutWire", 31 0, RS_0x7f507e9ad5f8; 32 drivers +v0x2864580_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x2864600_0 .net *"_s292", 0 0, L_0x2ad59d0; 1 drivers +v0x28646a0_0 .net/s *"_s293", 0 0, C4<0>; 1 drivers +v0x2864740_0 .net *"_s296", 0 0, L_0x2abcfb0; 1 drivers +v0x28647e0_0 .alias "carryin", 31 0, v0x295fa50_0; +v0x2864880_0 .alias "carryout", 0 0, v0x2960870_0; +v0x2864920_0 .alias "overflow", 0 0, v0x2960980_0; +v0x28649c0_0 .alias "subtract", 31 0, v0x2960aa0_0; +L_0x2aa88d0 .part/pv L_0x2aa8440, 1, 1, 32; +L_0x2aa89e0 .part/pv L_0x2aa8790, 1, 1, 32; +L_0x2aa8ad0 .part/pv L_0x2aa6f80, 1, 1, 32; +L_0x2aa8bc0 .part v0x295fe90_0, 1, 1; +L_0x2aa8c60 .part v0x2960190_0, 1, 1; +L_0x2aa8d90 .part RS_0x7f507e9ad5f8, 0, 1; +L_0x2aa9e10 .part/pv L_0x2aa9960, 2, 1, 32; +L_0x2aa9f00 .part/pv L_0x2aa9cb0, 2, 1, 32; +L_0x2aaa040 .part/pv L_0x2aa9690, 2, 1, 32; +L_0x2aaa130 .part v0x295fe90_0, 2, 1; +L_0x2aaa230 .part v0x2960190_0, 2, 1; +L_0x2aaa360 .part RS_0x7f507e9ad5f8, 1, 1; +L_0x2aab350 .part/pv L_0x2aaaea0, 3, 1, 32; +L_0x2aab440 .part/pv L_0x2aab1f0, 3, 1, 32; +L_0x2aab5b0 .part/pv L_0x2aaabd0, 3, 1, 32; +L_0x2aab6a0 .part v0x295fe90_0, 3, 1; +L_0x2aab7d0 .part v0x2960190_0, 3, 1; +L_0x2aab900 .part RS_0x7f507e9ad5f8, 2, 1; +L_0x2aac950 .part/pv L_0x2aac4a0, 4, 1, 32; +L_0x2aaca40 .part/pv L_0x2aac7f0, 4, 1, 32; +L_0x2aab9a0 .part/pv L_0x2aac1d0, 4, 1, 32; +L_0x2aacc30 .part v0x295fe90_0, 4, 1; +L_0x2aacb30 .part v0x2960190_0, 4, 1; +L_0x2aace20 .part RS_0x7f507e9ad5f8, 3, 1; +L_0x2aadef0 .part/pv L_0x2aada40, 5, 1, 32; +L_0x2aadfe0 .part/pv L_0x2aadd90, 5, 1, 32; +L_0x2aacfd0 .part/pv L_0x2aad770, 5, 1, 32; +L_0x2aae200 .part v0x295fe90_0, 5, 1; +L_0x2aae0d0 .part v0x2960190_0, 5, 1; +L_0x2aae420 .part RS_0x7f507e9ad5f8, 4, 1; +L_0x2aaf420 .part/pv L_0x2aaef50, 6, 1, 32; +L_0x2aaf510 .part/pv L_0x2aaf2c0, 6, 1, 32; +L_0x2aae4c0 .part/pv L_0x2aaec80, 6, 1, 32; +L_0x2aaf710 .part v0x295fe90_0, 6, 1; +L_0x2aaf600 .part v0x2960190_0, 6, 1; +L_0x2aaf960 .part RS_0x7f507e9ad5f8, 5, 1; +L_0x2ab0940 .part/pv L_0x2ab0490, 7, 1, 32; +L_0x2ab0a30 .part/pv L_0x2ab07e0, 7, 1, 32; +L_0x2aafa00 .part/pv L_0x2ab01c0, 7, 1, 32; +L_0x2ab0c60 .part v0x295fe90_0, 7, 1; +L_0x2ab0b20 .part v0x2960190_0, 7, 1; +L_0x2ab0e50 .part RS_0x7f507e9ad5f8, 6, 1; +L_0x2ab1e60 .part/pv L_0x2ab19b0, 8, 1, 32; +L_0x2ab1f50 .part/pv L_0x2ab1d00, 8, 1, 32; +L_0x2ab0ef0 .part/pv L_0x2ab16e0, 8, 1, 32; +L_0x2ab21b0 .part v0x295fe90_0, 8, 1; +L_0x2ab2040 .part v0x2960190_0, 8, 1; +L_0x2ab23d0 .part RS_0x7f507e9ad5f8, 7, 1; +L_0x2ab3470 .part/pv L_0x2ab2fc0, 9, 1, 32; +L_0x2ab3560 .part/pv L_0x2ab3310, 9, 1, 32; +L_0x2ab2680 .part/pv L_0x2ab2cf0, 9, 1, 32; +L_0x2ab2770 .part v0x295fe90_0, 9, 1; +L_0x2ab3800 .part v0x2960190_0, 9, 1; +L_0x2ab3930 .part RS_0x7f507e9ad5f8, 8, 1; +L_0x2ab4980 .part/pv L_0x2ab44d0, 10, 1, 32; +L_0x2ab4a70 .part/pv L_0x2ab4820, 10, 1, 32; +L_0x2ab39d0 .part/pv L_0x2ab4200, 10, 1, 32; +L_0x2ab3ac0 .part v0x295fe90_0, 10, 1; +L_0x2ab4d40 .part v0x2960190_0, 10, 1; +L_0x2ab4e70 .part RS_0x7f507e9ad5f8, 9, 1; +L_0x2ab5e90 .part/pv L_0x2ab59e0, 11, 1, 32; +L_0x2ab5f80 .part/pv L_0x2ab5d30, 11, 1, 32; +L_0x2ab4f10 .part/pv L_0x2ab5710, 11, 1, 32; +L_0x2ab5000 .part v0x295fe90_0, 11, 1; +L_0x2ab6280 .part v0x2960190_0, 11, 1; +L_0x2ab63b0 .part RS_0x7f507e9ad5f8, 10, 1; +L_0x2ab73a0 .part/pv L_0x2ab6ef0, 12, 1, 32; +L_0x2ab7490 .part/pv L_0x2ab7240, 12, 1, 32; +L_0x2ab6450 .part/pv L_0x2ab6c20, 12, 1, 32; +L_0x2ab6540 .part v0x295fe90_0, 12, 1; +L_0x2ab77c0 .part v0x2960190_0, 12, 1; +L_0x2ab7860 .part RS_0x7f507e9ad5f8, 11, 1; +L_0x2ab88a0 .part/pv L_0x2ab83f0, 13, 1, 32; +L_0x2ab8990 .part/pv L_0x2ab8740, 13, 1, 32; +L_0x2ab7900 .part/pv L_0x2ab8120, 13, 1, 32; +L_0x2ab79f0 .part v0x295fe90_0, 13, 1; +L_0x2ab7a90 .part v0x2960190_0, 13, 1; +L_0x2ab8d80 .part RS_0x7f507e9ad5f8, 12, 1; +L_0x2ab9db0 .part/pv L_0x2ab9900, 14, 1, 32; +L_0x2ab9ea0 .part/pv L_0x2ab9c50, 14, 1, 32; +L_0x2ab8e20 .part/pv L_0x2ab9630, 14, 1, 32; +L_0x2ab8f10 .part v0x295fe90_0, 14, 1; +L_0x2ab8fb0 .part v0x2960190_0, 14, 1; +L_0x2aba2c0 .part RS_0x7f507e9ad5f8, 13, 1; +L_0x2abb2c0 .part/pv L_0x2abae10, 15, 1, 32; +L_0x2abb3b0 .part/pv L_0x2abb160, 15, 1, 32; +L_0x2aba360 .part/pv L_0x2abab40, 15, 1, 32; +L_0x2aba450 .part v0x295fe90_0, 15, 1; +L_0x2aba4f0 .part v0x2960190_0, 15, 1; +L_0x2abb800 .part RS_0x7f507e9ad5f8, 14, 1; +L_0x2abc6f0 .part/pv L_0x2abc260, 16, 1, 32; +L_0x2abc7e0 .part/pv L_0x2abc5b0, 16, 1, 32; +L_0x2abb8a0 .part/pv L_0x2aaa490, 16, 1, 32; +L_0x2abb990 .part v0x295fe90_0, 16, 1; +L_0x2abba30 .part v0x2960190_0, 16, 1; +L_0x2abcbd0 .part RS_0x7f507e9ad5f8, 15, 1; +L_0x2abddb0 .part/pv L_0x2abd920, 17, 1, 32; +L_0x2abdea0 .part/pv L_0x2abdc70, 17, 1, 32; +L_0x2abd080 .part/pv L_0x2abd650, 17, 1, 32; +L_0x2abd170 .part v0x295fe90_0, 17, 1; +L_0x2abd210 .part v0x2960190_0, 17, 1; +L_0x2abe2c0 .part RS_0x7f507e9ad5f8, 16, 1; +L_0x2abf220 .part/pv L_0x2abed90, 18, 1, 32; +L_0x2abf310 .part/pv L_0x2abf0e0, 18, 1, 32; +L_0x2abe360 .part/pv L_0x2abeac0, 18, 1, 32; +L_0x2abe450 .part v0x295fe90_0, 18, 1; +L_0x2abe4f0 .part v0x2960190_0, 18, 1; +L_0x2abf760 .part RS_0x7f507e9ad5f8, 17, 1; +L_0x2ac06d0 .part/pv L_0x2ac0240, 19, 1, 32; +L_0x2ac07c0 .part/pv L_0x2ac0590, 19, 1, 32; +L_0x2abf800 .part/pv L_0x2abff70, 19, 1, 32; +L_0x2abf8f0 .part v0x295fe90_0, 19, 1; +L_0x2abf990 .part v0x2960190_0, 19, 1; +L_0x2abfac0 .part RS_0x7f507e9ad5f8, 18, 1; +L_0x2ac1aa0 .part/pv L_0x2ac1610, 20, 1, 32; +L_0x2ac1b90 .part/pv L_0x2ac1960, 20, 1, 32; +L_0x2ac08b0 .part/pv L_0x2ac1340, 20, 1, 32; +L_0x2ac09a0 .part v0x295fe90_0, 20, 1; +L_0x2ac0a40 .part v0x2960190_0, 20, 1; +L_0x2ac0b70 .part RS_0x7f507e9ad5f8, 19, 1; +L_0x2ac2e60 .part/pv L_0x2ac29d0, 21, 1, 32; +L_0x2ac2f50 .part/pv L_0x2ac2d20, 21, 1, 32; +L_0x2ac1c80 .part/pv L_0x2ac2700, 21, 1, 32; +L_0x2ac1d70 .part v0x295fe90_0, 21, 1; +L_0x2ac1e10 .part v0x2960190_0, 21, 1; +L_0x2ac1f40 .part RS_0x7f507e9ad5f8, 20, 1; +L_0x2ac4370 .part/pv L_0x2ac3ec0, 22, 1, 32; +L_0x2ac4460 .part/pv L_0x2ac4210, 22, 1, 32; +L_0x2ac3040 .part/pv L_0x2ac3bf0, 22, 1, 32; +L_0x2ac3130 .part v0x295fe90_0, 22, 1; +L_0x2ac31d0 .part v0x2960190_0, 22, 1; +L_0x2ac3300 .part RS_0x7f507e9ad5f8, 21, 1; +L_0x2ac5730 .part/pv L_0x2ac52a0, 23, 1, 32; +L_0x2ac5820 .part/pv L_0x2ac55f0, 23, 1, 32; +L_0x2ac4550 .part/pv L_0x2ac4fd0, 23, 1, 32; +L_0x2ac4640 .part v0x295fe90_0, 23, 1; +L_0x2ac46e0 .part v0x2960190_0, 23, 1; +L_0x2ac4810 .part RS_0x7f507e9ad5f8, 22, 1; +L_0x2ac6b70 .part/pv L_0x2ac66a0, 24, 1, 32; +L_0x2ac6c60 .part/pv L_0x2ac6a10, 24, 1, 32; +L_0x2ac5910 .part/pv L_0x2ac63d0, 24, 1, 32; +L_0x2ac5a00 .part v0x295fe90_0, 24, 1; +L_0x2ac5aa0 .part v0x2960190_0, 24, 1; +L_0x2ac5bd0 .part RS_0x7f507e9ad5f8, 23, 1; +L_0x2ac8830 .part/pv L_0x2ac8360, 25, 1, 32; +L_0x2ac8920 .part/pv L_0x2ac86d0, 25, 1, 32; +L_0x29c6c30 .part/pv L_0x2ac7050, 25, 1, 32; +L_0x29c6d20 .part v0x295fe90_0, 25, 1; +L_0x29c6dc0 .part v0x2960190_0, 25, 1; +L_0x29c6ef0 .part RS_0x7f507e9ad5f8, 24, 1; +L_0x2ac9d10 .part/pv L_0x2ac97e0, 26, 1, 32; +L_0x2ac9e00 .part/pv L_0x2ac9bb0, 26, 1, 32; +L_0x2ac8a10 .part/pv L_0x2ac9510, 26, 1, 32; +L_0x2ac8b00 .part v0x295fe90_0, 26, 1; +L_0x2ac8ba0 .part v0x2960190_0, 26, 1; +L_0x2ac8cd0 .part RS_0x7f507e9ad5f8, 25, 1; +L_0x2997ec0 .part/pv L_0x2997990, 27, 1, 32; +L_0x2997fb0 .part/pv L_0x2997d60, 27, 1, 32; +L_0x2ac9ef0 .part/pv L_0x2aca9f0, 27, 1, 32; +L_0x2ac9fe0 .part v0x295fe90_0, 27, 1; +L_0x2aca080 .part v0x2960190_0, 27, 1; +L_0x2aca1b0 .part RS_0x7f507e9ad5f8, 26, 1; +L_0x29993f0 .part/pv L_0x2998f40, 28, 1, 32; +L_0x29994e0 .part/pv L_0x2999290, 28, 1, 32; +L_0x29980a0 .part/pv L_0x2998c70, 28, 1, 32; +L_0x2998190 .part v0x295fe90_0, 28, 1; +L_0x2998230 .part v0x2960190_0, 28, 1; +L_0x2998360 .part RS_0x7f507e9ad5f8, 27, 1; +L_0x299a8d0 .part/pv L_0x299a420, 29, 1, 32; +L_0x299a9c0 .part/pv L_0x299a770, 29, 1, 32; +L_0x29995d0 .part/pv L_0x299a150, 29, 1, 32; +L_0x29996c0 .part v0x295fe90_0, 29, 1; +L_0x2999760 .part v0x2960190_0, 29, 1; +L_0x2999890 .part RS_0x7f507e9ad5f8, 28, 1; +L_0x2ad3100 .part/pv L_0x2ad2c70, 30, 1, 32; +L_0x2ad31f0 .part/pv L_0x2ad2fc0, 30, 1, 32; +L_0x299aab0 .part/pv L_0x299b660, 30, 1, 32; +L_0x299aba0 .part v0x295fe90_0, 30, 1; +L_0x299ac40 .part v0x2960190_0, 30, 1; +L_0x299ad70 .part RS_0x7f507e9ad5f8, 29, 1; +L_0x2ad4540 .part/pv L_0x2ad40b0, 31, 1, 32; +L_0x2a36e10 .part/pv L_0x2ad4400, 31, 1, 32; +L_0x2a374c0 .part/pv L_0x2ad3de0, 31, 1, 32; +L_0x2ad32e0 .part v0x295fe90_0, 31, 1; +L_0x2ad3380 .part v0x2960190_0, 31, 1; +L_0x2ad34b0 .part RS_0x7f507e9ad5f8, 30, 1; +L_0x2ad6280 .part/pv L_0x2ad5df0, 0, 1, 32; +L_0x2ad6370 .part/pv L_0x2ad6140, 0, 1, 32; +L_0x2ad55f0 .part/pv L_0x2a373e0, 0, 1, 32; +L_0x2ad56e0 .part v0x295fe90_0, 0, 1; +L_0x2ad5780 .part v0x2960190_0, 0, 1; +L_0x2ad58b0 .part RS_0x7f507e9ad748, 0, 1; +L_0x2ad59d0 .part RS_0x7f507e9ad5f8, 31, 1; +L_0x2abcfb0 .part RS_0x7f507e9ad5f8, 30, 1; +S_0x2863300 .scope module, "attempt2" "MiddleAddSubSLT" 3 278, 3 189, S_0x2840e20; + .timescale -9 -12; +L_0x2ad3550/d .functor NOT 1, L_0x2ad5780, C4<0>, C4<0>, C4<0>; +L_0x2ad3550 .delay (10000,10000,10000) L_0x2ad3550/d; +L_0x2a37280/d .functor NOT 1, L_0x2a37340, C4<0>, C4<0>, C4<0>; +L_0x2a37280 .delay (10000,10000,10000) L_0x2a37280/d; +L_0x2a373e0/d .functor AND 1, L_0x2ad5c60, L_0x2a37280, C4<1>, C4<1>; +L_0x2a373e0 .delay (20000,20000,20000) L_0x2a373e0/d; +L_0x2ad5d00/d .functor XOR 1, L_0x2ad56e0, L_0x2a37010, C4<0>, C4<0>; +L_0x2ad5d00 .delay (40000,40000,40000) L_0x2ad5d00/d; +L_0x2ad5df0/d .functor XOR 1, L_0x2ad5d00, L_0x2ad58b0, C4<0>, C4<0>; +L_0x2ad5df0 .delay (40000,40000,40000) L_0x2ad5df0/d; +L_0x2ad5ee0/d .functor AND 1, L_0x2ad56e0, L_0x2a37010, C4<1>, C4<1>; +L_0x2ad5ee0 .delay (20000,20000,20000) L_0x2ad5ee0/d; +L_0x2ad6050/d .functor AND 1, L_0x2ad5d00, L_0x2ad58b0, C4<1>, C4<1>; +L_0x2ad6050 .delay (20000,20000,20000) L_0x2ad6050/d; +L_0x2ad6140/d .functor OR 1, L_0x2ad5ee0, L_0x2ad6050, C4<0>, C4<0>; +L_0x2ad6140 .delay (20000,20000,20000) L_0x2ad6140/d; +v0x2863970_0 .net "A", 0 0, L_0x2ad56e0; 1 drivers +v0x2863a30_0 .net "AandB", 0 0, L_0x2ad5ee0; 1 drivers +v0x2863ad0_0 .net "AddSubSLTSum", 0 0, L_0x2ad5df0; 1 drivers +v0x2863b70_0 .net "AxorB", 0 0, L_0x2ad5d00; 1 drivers +v0x2863bf0_0 .net "B", 0 0, L_0x2ad5780; 1 drivers +v0x2863ca0_0 .net "BornB", 0 0, L_0x2a37010; 1 drivers +v0x2863d60_0 .net "CINandAxorB", 0 0, L_0x2ad6050; 1 drivers +v0x2863de0_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x2863e60_0 .net *"_s3", 0 0, L_0x2a37340; 1 drivers +v0x2863ee0_0 .net *"_s5", 0 0, L_0x2ad5c60; 1 drivers +v0x2863f80_0 .net "carryin", 0 0, L_0x2ad58b0; 1 drivers +v0x2864020_0 .net "carryout", 0 0, L_0x2ad6140; 1 drivers +v0x28640c0_0 .net "nB", 0 0, L_0x2ad3550; 1 drivers +v0x2864170_0 .net "nCmd2", 0 0, L_0x2a37280; 1 drivers +v0x2864270_0 .net "subtract", 0 0, L_0x2a373e0; 1 drivers +L_0x2a371e0 .part v0x2960210_0, 0, 1; +L_0x2a37340 .part v0x2960210_0, 2, 1; +L_0x2ad5c60 .part v0x2960210_0, 0, 1; +S_0x28633f0 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x2863300; + .timescale -9 -12; +L_0x2ad3690/d .functor NOT 1, L_0x2a371e0, C4<0>, C4<0>, C4<0>; +L_0x2ad3690 .delay (10000,10000,10000) L_0x2ad3690/d; +L_0x2ad3750/d .functor AND 1, L_0x2ad5780, L_0x2ad3690, C4<1>, C4<1>; +L_0x2ad3750 .delay (20000,20000,20000) L_0x2ad3750/d; +L_0x2a36f00/d .functor AND 1, L_0x2ad3550, L_0x2a371e0, C4<1>, C4<1>; +L_0x2a36f00 .delay (20000,20000,20000) L_0x2a36f00/d; +L_0x2a37010/d .functor OR 1, L_0x2ad3750, L_0x2a36f00, C4<0>, C4<0>; +L_0x2a37010 .delay (20000,20000,20000) L_0x2a37010/d; +v0x28634e0_0 .net "S", 0 0, L_0x2a371e0; 1 drivers +v0x28635a0_0 .alias "in0", 0 0, v0x2863bf0_0; +v0x2863640_0 .alias "in1", 0 0, v0x28640c0_0; +v0x28636e0_0 .net "nS", 0 0, L_0x2ad3690; 1 drivers +v0x2863790_0 .net "out0", 0 0, L_0x2ad3750; 1 drivers +v0x2863830_0 .net "out1", 0 0, L_0x2a36f00; 1 drivers +v0x28638d0_0 .alias "outfinal", 0 0, v0x2863ca0_0; +S_0x2862160 .scope generate, "addbits[1]" "addbits[1]" 3 283, 3 283, S_0x2840e20; + .timescale -9 -12; +P_0x2861b78 .param/l "i" 3 283, +C4<01>; +S_0x28622d0 .scope module, "attempt" "MiddleAddSubSLT" 3 285, 3 189, S_0x2862160; + .timescale -9 -12; +L_0x2aa6700/d .functor NOT 1, L_0x2aa8c60, C4<0>, C4<0>, C4<0>; +L_0x2aa6700 .delay (10000,10000,10000) L_0x2aa6700/d; +L_0x2aa6e20/d .functor NOT 1, L_0x2aa6ee0, C4<0>, C4<0>, C4<0>; +L_0x2aa6e20 .delay (10000,10000,10000) L_0x2aa6e20/d; +L_0x2aa6f80/d .functor AND 1, L_0x2aa70c0, L_0x2aa6e20, C4<1>, C4<1>; +L_0x2aa6f80 .delay (20000,20000,20000) L_0x2aa6f80/d; +L_0x2aa7160/d .functor XOR 1, L_0x2aa8bc0, L_0x2aa6bb0, C4<0>, C4<0>; +L_0x2aa7160 .delay (40000,40000,40000) L_0x2aa7160/d; +L_0x2aa8440/d .functor XOR 1, L_0x2aa7160, L_0x2aa8d90, C4<0>, C4<0>; +L_0x2aa8440 .delay (40000,40000,40000) L_0x2aa8440/d; +L_0x2aa8530/d .functor AND 1, L_0x2aa8bc0, L_0x2aa6bb0, C4<1>, C4<1>; +L_0x2aa8530 .delay (20000,20000,20000) L_0x2aa8530/d; +L_0x2aa86a0/d .functor AND 1, L_0x2aa7160, L_0x2aa8d90, C4<1>, C4<1>; +L_0x2aa86a0 .delay (20000,20000,20000) L_0x2aa86a0/d; +L_0x2aa8790/d .functor OR 1, L_0x2aa8530, L_0x2aa86a0, C4<0>, C4<0>; +L_0x2aa8790 .delay (20000,20000,20000) L_0x2aa8790/d; +v0x2862960_0 .net "A", 0 0, L_0x2aa8bc0; 1 drivers +v0x2862a20_0 .net "AandB", 0 0, L_0x2aa8530; 1 drivers +v0x2862ac0_0 .net "AddSubSLTSum", 0 0, L_0x2aa8440; 1 drivers +v0x2862b60_0 .net "AxorB", 0 0, L_0x2aa7160; 1 drivers +v0x2862be0_0 .net "B", 0 0, L_0x2aa8c60; 1 drivers +v0x2862c90_0 .net "BornB", 0 0, L_0x2aa6bb0; 1 drivers +v0x2862d50_0 .net "CINandAxorB", 0 0, L_0x2aa86a0; 1 drivers +v0x2862dd0_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x2862e50_0 .net *"_s3", 0 0, L_0x2aa6ee0; 1 drivers +v0x2862ed0_0 .net *"_s5", 0 0, L_0x2aa70c0; 1 drivers +v0x2862f70_0 .net "carryin", 0 0, L_0x2aa8d90; 1 drivers +v0x2863010_0 .net "carryout", 0 0, L_0x2aa8790; 1 drivers +v0x28630b0_0 .net "nB", 0 0, L_0x2aa6700; 1 drivers +v0x2863160_0 .net "nCmd2", 0 0, L_0x2aa6e20; 1 drivers +v0x2863260_0 .net "subtract", 0 0, L_0x2aa6f80; 1 drivers +L_0x2aa6d80 .part v0x2960210_0, 0, 1; +L_0x2aa6ee0 .part v0x2960210_0, 2, 1; +L_0x2aa70c0 .part v0x2960210_0, 0, 1; +S_0x28623c0 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x28622d0; + .timescale -9 -12; +L_0x2aa68d0/d .functor NOT 1, L_0x2aa6d80, C4<0>, C4<0>, C4<0>; +L_0x2aa68d0 .delay (10000,10000,10000) L_0x2aa68d0/d; +L_0x2aa6990/d .functor AND 1, L_0x2aa8c60, L_0x2aa68d0, C4<1>, C4<1>; +L_0x2aa6990 .delay (20000,20000,20000) L_0x2aa6990/d; +L_0x2aa6aa0/d .functor AND 1, L_0x2aa6700, L_0x2aa6d80, C4<1>, C4<1>; +L_0x2aa6aa0 .delay (20000,20000,20000) L_0x2aa6aa0/d; +L_0x2aa6bb0/d .functor OR 1, L_0x2aa6990, L_0x2aa6aa0, C4<0>, C4<0>; +L_0x2aa6bb0 .delay (20000,20000,20000) L_0x2aa6bb0/d; +v0x28624b0_0 .net "S", 0 0, L_0x2aa6d80; 1 drivers +v0x2862550_0 .alias "in0", 0 0, v0x2862be0_0; +v0x28625f0_0 .alias "in1", 0 0, v0x28630b0_0; +v0x2862690_0 .net "nS", 0 0, L_0x2aa68d0; 1 drivers +v0x2862740_0 .net "out0", 0 0, L_0x2aa6990; 1 drivers +v0x28627e0_0 .net "out1", 0 0, L_0x2aa6aa0; 1 drivers +v0x28628c0_0 .alias "outfinal", 0 0, v0x2862c90_0; +S_0x2860fc0 .scope generate, "addbits[2]" "addbits[2]" 3 283, 3 283, S_0x2840e20; + .timescale -9 -12; +P_0x28609d8 .param/l "i" 3 283, +C4<010>; +S_0x2861130 .scope module, "attempt" "MiddleAddSubSLT" 3 285, 3 189, S_0x2860fc0; + .timescale -9 -12; +L_0x2aa8e30/d .functor NOT 1, L_0x2aaa230, C4<0>, C4<0>, C4<0>; +L_0x2aa8e30 .delay (10000,10000,10000) L_0x2aa8e30/d; +L_0x2aa9530/d .functor NOT 1, L_0x2aa95f0, C4<0>, C4<0>, C4<0>; +L_0x2aa9530 .delay (10000,10000,10000) L_0x2aa9530/d; +L_0x2aa9690/d .functor AND 1, L_0x2aa97d0, L_0x2aa9530, C4<1>, C4<1>; +L_0x2aa9690 .delay (20000,20000,20000) L_0x2aa9690/d; +L_0x2aa9870/d .functor XOR 1, L_0x2aaa130, L_0x2aa92c0, C4<0>, C4<0>; +L_0x2aa9870 .delay (40000,40000,40000) L_0x2aa9870/d; +L_0x2aa9960/d .functor XOR 1, L_0x2aa9870, L_0x2aaa360, C4<0>, C4<0>; +L_0x2aa9960 .delay (40000,40000,40000) L_0x2aa9960/d; +L_0x2aa9a50/d .functor AND 1, L_0x2aaa130, L_0x2aa92c0, C4<1>, C4<1>; +L_0x2aa9a50 .delay (20000,20000,20000) L_0x2aa9a50/d; +L_0x2aa9bc0/d .functor AND 1, L_0x2aa9870, L_0x2aaa360, C4<1>, C4<1>; +L_0x2aa9bc0 .delay (20000,20000,20000) L_0x2aa9bc0/d; +L_0x2aa9cb0/d .functor OR 1, L_0x2aa9a50, L_0x2aa9bc0, C4<0>, C4<0>; +L_0x2aa9cb0 .delay (20000,20000,20000) L_0x2aa9cb0/d; +v0x28617c0_0 .net "A", 0 0, L_0x2aaa130; 1 drivers +v0x2861880_0 .net "AandB", 0 0, L_0x2aa9a50; 1 drivers +v0x2861920_0 .net "AddSubSLTSum", 0 0, L_0x2aa9960; 1 drivers +v0x28619c0_0 .net "AxorB", 0 0, L_0x2aa9870; 1 drivers +v0x2861a40_0 .net "B", 0 0, L_0x2aaa230; 1 drivers +v0x2861af0_0 .net "BornB", 0 0, L_0x2aa92c0; 1 drivers +v0x2861bb0_0 .net "CINandAxorB", 0 0, L_0x2aa9bc0; 1 drivers +v0x2861c30_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x2861cb0_0 .net *"_s3", 0 0, L_0x2aa95f0; 1 drivers +v0x2861d30_0 .net *"_s5", 0 0, L_0x2aa97d0; 1 drivers +v0x2861dd0_0 .net "carryin", 0 0, L_0x2aaa360; 1 drivers +v0x2861e70_0 .net "carryout", 0 0, L_0x2aa9cb0; 1 drivers +v0x2861f10_0 .net "nB", 0 0, L_0x2aa8e30; 1 drivers +v0x2861fc0_0 .net "nCmd2", 0 0, L_0x2aa9530; 1 drivers +v0x28620c0_0 .net "subtract", 0 0, L_0x2aa9690; 1 drivers +L_0x2aa9490 .part v0x2960210_0, 0, 1; +L_0x2aa95f0 .part v0x2960210_0, 2, 1; +L_0x2aa97d0 .part v0x2960210_0, 0, 1; +S_0x2861220 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x2861130; + .timescale -9 -12; +L_0x2aa8fe0/d .functor NOT 1, L_0x2aa9490, C4<0>, C4<0>, C4<0>; +L_0x2aa8fe0 .delay (10000,10000,10000) L_0x2aa8fe0/d; +L_0x2aa90a0/d .functor AND 1, L_0x2aaa230, L_0x2aa8fe0, C4<1>, C4<1>; +L_0x2aa90a0 .delay (20000,20000,20000) L_0x2aa90a0/d; +L_0x2aa91b0/d .functor AND 1, L_0x2aa8e30, L_0x2aa9490, C4<1>, C4<1>; +L_0x2aa91b0 .delay (20000,20000,20000) L_0x2aa91b0/d; +L_0x2aa92c0/d .functor OR 1, L_0x2aa90a0, L_0x2aa91b0, C4<0>, C4<0>; +L_0x2aa92c0 .delay (20000,20000,20000) L_0x2aa92c0/d; +v0x2861310_0 .net "S", 0 0, L_0x2aa9490; 1 drivers +v0x28613b0_0 .alias "in0", 0 0, v0x2861a40_0; +v0x2861450_0 .alias "in1", 0 0, v0x2861f10_0; +v0x28614f0_0 .net "nS", 0 0, L_0x2aa8fe0; 1 drivers +v0x28615a0_0 .net "out0", 0 0, L_0x2aa90a0; 1 drivers +v0x2861640_0 .net "out1", 0 0, L_0x2aa91b0; 1 drivers +v0x2861720_0 .alias "outfinal", 0 0, v0x2861af0_0; +S_0x285fe20 .scope generate, "addbits[3]" "addbits[3]" 3 283, 3 283, S_0x2840e20; + .timescale -9 -12; +P_0x285f838 .param/l "i" 3 283, +C4<011>; +S_0x285ff90 .scope module, "attempt" "MiddleAddSubSLT" 3 285, 3 189, S_0x285fe20; + .timescale -9 -12; +L_0x2aaa1d0/d .functor NOT 1, L_0x2aab7d0, C4<0>, C4<0>, C4<0>; +L_0x2aaa1d0 .delay (10000,10000,10000) L_0x2aaa1d0/d; +L_0x2aaaa70/d .functor NOT 1, L_0x2aaab30, C4<0>, C4<0>, C4<0>; +L_0x2aaaa70 .delay (10000,10000,10000) L_0x2aaaa70/d; +L_0x2aaabd0/d .functor AND 1, L_0x2aaad10, L_0x2aaaa70, C4<1>, C4<1>; +L_0x2aaabd0 .delay (20000,20000,20000) L_0x2aaabd0/d; +L_0x2aaadb0/d .functor XOR 1, L_0x2aab6a0, L_0x2aaa800, C4<0>, C4<0>; +L_0x2aaadb0 .delay (40000,40000,40000) L_0x2aaadb0/d; +L_0x2aaaea0/d .functor XOR 1, L_0x2aaadb0, L_0x2aab900, C4<0>, C4<0>; +L_0x2aaaea0 .delay (40000,40000,40000) L_0x2aaaea0/d; +L_0x2aaaf90/d .functor AND 1, L_0x2aab6a0, L_0x2aaa800, C4<1>, C4<1>; +L_0x2aaaf90 .delay (20000,20000,20000) L_0x2aaaf90/d; +L_0x2aab100/d .functor AND 1, L_0x2aaadb0, L_0x2aab900, C4<1>, C4<1>; +L_0x2aab100 .delay (20000,20000,20000) L_0x2aab100/d; +L_0x2aab1f0/d .functor OR 1, L_0x2aaaf90, L_0x2aab100, C4<0>, C4<0>; +L_0x2aab1f0 .delay (20000,20000,20000) L_0x2aab1f0/d; +v0x2860620_0 .net "A", 0 0, L_0x2aab6a0; 1 drivers +v0x28606e0_0 .net "AandB", 0 0, L_0x2aaaf90; 1 drivers +v0x2860780_0 .net "AddSubSLTSum", 0 0, L_0x2aaaea0; 1 drivers +v0x2860820_0 .net "AxorB", 0 0, L_0x2aaadb0; 1 drivers +v0x28608a0_0 .net "B", 0 0, L_0x2aab7d0; 1 drivers +v0x2860950_0 .net "BornB", 0 0, L_0x2aaa800; 1 drivers +v0x2860a10_0 .net "CINandAxorB", 0 0, L_0x2aab100; 1 drivers +v0x2860a90_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x2860b10_0 .net *"_s3", 0 0, L_0x2aaab30; 1 drivers +v0x2860b90_0 .net *"_s5", 0 0, L_0x2aaad10; 1 drivers +v0x2860c30_0 .net "carryin", 0 0, L_0x2aab900; 1 drivers +v0x2860cd0_0 .net "carryout", 0 0, L_0x2aab1f0; 1 drivers +v0x2860d70_0 .net "nB", 0 0, L_0x2aaa1d0; 1 drivers +v0x2860e20_0 .net "nCmd2", 0 0, L_0x2aaaa70; 1 drivers +v0x2860f20_0 .net "subtract", 0 0, L_0x2aaabd0; 1 drivers +L_0x2aaa9d0 .part v0x2960210_0, 0, 1; +L_0x2aaab30 .part v0x2960210_0, 2, 1; +L_0x2aaad10 .part v0x2960210_0, 0, 1; +S_0x2860080 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x285ff90; + .timescale -9 -12; +L_0x2aaa560/d .functor NOT 1, L_0x2aaa9d0, C4<0>, C4<0>, C4<0>; +L_0x2aaa560 .delay (10000,10000,10000) L_0x2aaa560/d; +L_0x2aaa5e0/d .functor AND 1, L_0x2aab7d0, L_0x2aaa560, C4<1>, C4<1>; +L_0x2aaa5e0 .delay (20000,20000,20000) L_0x2aaa5e0/d; +L_0x2aaa6f0/d .functor AND 1, L_0x2aaa1d0, L_0x2aaa9d0, C4<1>, C4<1>; +L_0x2aaa6f0 .delay (20000,20000,20000) L_0x2aaa6f0/d; +L_0x2aaa800/d .functor OR 1, L_0x2aaa5e0, L_0x2aaa6f0, C4<0>, C4<0>; +L_0x2aaa800 .delay (20000,20000,20000) L_0x2aaa800/d; +v0x2860170_0 .net "S", 0 0, L_0x2aaa9d0; 1 drivers +v0x2860210_0 .alias "in0", 0 0, v0x28608a0_0; +v0x28602b0_0 .alias "in1", 0 0, v0x2860d70_0; +v0x2860350_0 .net "nS", 0 0, L_0x2aaa560; 1 drivers +v0x2860400_0 .net "out0", 0 0, L_0x2aaa5e0; 1 drivers +v0x28604a0_0 .net "out1", 0 0, L_0x2aaa6f0; 1 drivers +v0x2860580_0 .alias "outfinal", 0 0, v0x2860950_0; +S_0x285ec80 .scope generate, "addbits[4]" "addbits[4]" 3 283, 3 283, S_0x2840e20; + .timescale -9 -12; +P_0x285e698 .param/l "i" 3 283, +C4<0100>; +S_0x285edf0 .scope module, "attempt" "MiddleAddSubSLT" 3 285, 3 189, S_0x285ec80; + .timescale -9 -12; +L_0x2aab740/d .functor NOT 1, L_0x2aacb30, C4<0>, C4<0>, C4<0>; +L_0x2aab740 .delay (10000,10000,10000) L_0x2aab740/d; +L_0x2aac070/d .functor NOT 1, L_0x2aac130, C4<0>, C4<0>, C4<0>; +L_0x2aac070 .delay (10000,10000,10000) L_0x2aac070/d; +L_0x2aac1d0/d .functor AND 1, L_0x2aac310, L_0x2aac070, C4<1>, C4<1>; +L_0x2aac1d0 .delay (20000,20000,20000) L_0x2aac1d0/d; +L_0x2aac3b0/d .functor XOR 1, L_0x2aacc30, L_0x2aabe00, C4<0>, C4<0>; +L_0x2aac3b0 .delay (40000,40000,40000) L_0x2aac3b0/d; +L_0x2aac4a0/d .functor XOR 1, L_0x2aac3b0, L_0x2aace20, C4<0>, C4<0>; +L_0x2aac4a0 .delay (40000,40000,40000) L_0x2aac4a0/d; +L_0x2aac590/d .functor AND 1, L_0x2aacc30, L_0x2aabe00, C4<1>, C4<1>; +L_0x2aac590 .delay (20000,20000,20000) L_0x2aac590/d; +L_0x2aac700/d .functor AND 1, L_0x2aac3b0, L_0x2aace20, C4<1>, C4<1>; +L_0x2aac700 .delay (20000,20000,20000) L_0x2aac700/d; +L_0x2aac7f0/d .functor OR 1, L_0x2aac590, L_0x2aac700, C4<0>, C4<0>; +L_0x2aac7f0 .delay (20000,20000,20000) L_0x2aac7f0/d; +v0x285f480_0 .net "A", 0 0, L_0x2aacc30; 1 drivers +v0x285f540_0 .net "AandB", 0 0, L_0x2aac590; 1 drivers +v0x285f5e0_0 .net "AddSubSLTSum", 0 0, L_0x2aac4a0; 1 drivers +v0x285f680_0 .net "AxorB", 0 0, L_0x2aac3b0; 1 drivers +v0x285f700_0 .net "B", 0 0, L_0x2aacb30; 1 drivers +v0x285f7b0_0 .net "BornB", 0 0, L_0x2aabe00; 1 drivers +v0x285f870_0 .net "CINandAxorB", 0 0, L_0x2aac700; 1 drivers +v0x285f8f0_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x285f970_0 .net *"_s3", 0 0, L_0x2aac130; 1 drivers +v0x285f9f0_0 .net *"_s5", 0 0, L_0x2aac310; 1 drivers +v0x285fa90_0 .net "carryin", 0 0, L_0x2aace20; 1 drivers +v0x285fb30_0 .net "carryout", 0 0, L_0x2aac7f0; 1 drivers +v0x285fbd0_0 .net "nB", 0 0, L_0x2aab740; 1 drivers +v0x285fc80_0 .net "nCmd2", 0 0, L_0x2aac070; 1 drivers +v0x285fd80_0 .net "subtract", 0 0, L_0x2aac1d0; 1 drivers +L_0x2aabfd0 .part v0x2960210_0, 0, 1; +L_0x2aac130 .part v0x2960210_0, 2, 1; +L_0x2aac310 .part v0x2960210_0, 0, 1; +S_0x285eee0 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x285edf0; + .timescale -9 -12; +L_0x2aabb20/d .functor NOT 1, L_0x2aabfd0, C4<0>, C4<0>, C4<0>; +L_0x2aabb20 .delay (10000,10000,10000) L_0x2aabb20/d; +L_0x2aabbe0/d .functor AND 1, L_0x2aacb30, L_0x2aabb20, C4<1>, C4<1>; +L_0x2aabbe0 .delay (20000,20000,20000) L_0x2aabbe0/d; +L_0x2aabcf0/d .functor AND 1, L_0x2aab740, L_0x2aabfd0, C4<1>, C4<1>; +L_0x2aabcf0 .delay (20000,20000,20000) L_0x2aabcf0/d; +L_0x2aabe00/d .functor OR 1, L_0x2aabbe0, L_0x2aabcf0, C4<0>, C4<0>; +L_0x2aabe00 .delay (20000,20000,20000) L_0x2aabe00/d; +v0x285efd0_0 .net "S", 0 0, L_0x2aabfd0; 1 drivers +v0x285f070_0 .alias "in0", 0 0, v0x285f700_0; +v0x285f110_0 .alias "in1", 0 0, v0x285fbd0_0; +v0x285f1b0_0 .net "nS", 0 0, L_0x2aabb20; 1 drivers +v0x285f260_0 .net "out0", 0 0, L_0x2aabbe0; 1 drivers +v0x285f300_0 .net "out1", 0 0, L_0x2aabcf0; 1 drivers +v0x285f3e0_0 .alias "outfinal", 0 0, v0x285f7b0_0; +S_0x285dae0 .scope generate, "addbits[5]" "addbits[5]" 3 283, 3 283, S_0x2840e20; + .timescale -9 -12; +P_0x285d4f8 .param/l "i" 3 283, +C4<0101>; +S_0x285dc50 .scope module, "attempt" "MiddleAddSubSLT" 3 285, 3 189, S_0x285dae0; + .timescale -9 -12; +L_0x2aaa400/d .functor NOT 1, L_0x2aae0d0, C4<0>, C4<0>, C4<0>; +L_0x2aaa400 .delay (10000,10000,10000) L_0x2aaa400/d; +L_0x2aad610/d .functor NOT 1, L_0x2aad6d0, C4<0>, C4<0>, C4<0>; +L_0x2aad610 .delay (10000,10000,10000) L_0x2aad610/d; +L_0x2aad770/d .functor AND 1, L_0x2aad8b0, L_0x2aad610, C4<1>, C4<1>; +L_0x2aad770 .delay (20000,20000,20000) L_0x2aad770/d; +L_0x2aad950/d .functor XOR 1, L_0x2aae200, L_0x2aad3a0, C4<0>, C4<0>; +L_0x2aad950 .delay (40000,40000,40000) L_0x2aad950/d; +L_0x2aada40/d .functor XOR 1, L_0x2aad950, L_0x2aae420, C4<0>, C4<0>; +L_0x2aada40 .delay (40000,40000,40000) L_0x2aada40/d; +L_0x2aadb30/d .functor AND 1, L_0x2aae200, L_0x2aad3a0, C4<1>, C4<1>; +L_0x2aadb30 .delay (20000,20000,20000) L_0x2aadb30/d; +L_0x2aadca0/d .functor AND 1, L_0x2aad950, L_0x2aae420, C4<1>, C4<1>; +L_0x2aadca0 .delay (20000,20000,20000) L_0x2aadca0/d; +L_0x2aadd90/d .functor OR 1, L_0x2aadb30, L_0x2aadca0, C4<0>, C4<0>; +L_0x2aadd90 .delay (20000,20000,20000) L_0x2aadd90/d; +v0x285e2e0_0 .net "A", 0 0, L_0x2aae200; 1 drivers +v0x285e3a0_0 .net "AandB", 0 0, L_0x2aadb30; 1 drivers +v0x285e440_0 .net "AddSubSLTSum", 0 0, L_0x2aada40; 1 drivers +v0x285e4e0_0 .net "AxorB", 0 0, L_0x2aad950; 1 drivers +v0x285e560_0 .net "B", 0 0, L_0x2aae0d0; 1 drivers +v0x285e610_0 .net "BornB", 0 0, L_0x2aad3a0; 1 drivers +v0x285e6d0_0 .net "CINandAxorB", 0 0, L_0x2aadca0; 1 drivers +v0x285e750_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x285e7d0_0 .net *"_s3", 0 0, L_0x2aad6d0; 1 drivers +v0x285e850_0 .net *"_s5", 0 0, L_0x2aad8b0; 1 drivers +v0x285e8f0_0 .net "carryin", 0 0, L_0x2aae420; 1 drivers +v0x285e990_0 .net "carryout", 0 0, L_0x2aadd90; 1 drivers +v0x285ea30_0 .net "nB", 0 0, L_0x2aaa400; 1 drivers +v0x285eae0_0 .net "nCmd2", 0 0, L_0x2aad610; 1 drivers +v0x285ebe0_0 .net "subtract", 0 0, L_0x2aad770; 1 drivers +L_0x2aad570 .part v0x2960210_0, 0, 1; +L_0x2aad6d0 .part v0x2960210_0, 2, 1; +L_0x2aad8b0 .part v0x2960210_0, 0, 1; +S_0x285dd40 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x285dc50; + .timescale -9 -12; +L_0x2aad0c0/d .functor NOT 1, L_0x2aad570, C4<0>, C4<0>, C4<0>; +L_0x2aad0c0 .delay (10000,10000,10000) L_0x2aad0c0/d; +L_0x2aad180/d .functor AND 1, L_0x2aae0d0, L_0x2aad0c0, C4<1>, C4<1>; +L_0x2aad180 .delay (20000,20000,20000) L_0x2aad180/d; +L_0x2aad290/d .functor AND 1, L_0x2aaa400, L_0x2aad570, C4<1>, C4<1>; +L_0x2aad290 .delay (20000,20000,20000) L_0x2aad290/d; +L_0x2aad3a0/d .functor OR 1, L_0x2aad180, L_0x2aad290, C4<0>, C4<0>; +L_0x2aad3a0 .delay (20000,20000,20000) L_0x2aad3a0/d; +v0x285de30_0 .net "S", 0 0, L_0x2aad570; 1 drivers +v0x285ded0_0 .alias "in0", 0 0, v0x285e560_0; +v0x285df70_0 .alias "in1", 0 0, v0x285ea30_0; +v0x285e010_0 .net "nS", 0 0, L_0x2aad0c0; 1 drivers +v0x285e0c0_0 .net "out0", 0 0, L_0x2aad180; 1 drivers +v0x285e160_0 .net "out1", 0 0, L_0x2aad290; 1 drivers +v0x285e240_0 .alias "outfinal", 0 0, v0x285e610_0; +S_0x285c940 .scope generate, "addbits[6]" "addbits[6]" 3 283, 3 283, S_0x2840e20; + .timescale -9 -12; +P_0x285c358 .param/l "i" 3 283, +C4<0110>; +S_0x285cab0 .scope module, "attempt" "MiddleAddSubSLT" 3 285, 3 189, S_0x285c940; + .timescale -9 -12; +L_0x2aae2a0/d .functor NOT 1, L_0x2aaf600, C4<0>, C4<0>, C4<0>; +L_0x2aae2a0 .delay (10000,10000,10000) L_0x2aae2a0/d; +L_0x2aaeb20/d .functor NOT 1, L_0x2aaebe0, C4<0>, C4<0>, C4<0>; +L_0x2aaeb20 .delay (10000,10000,10000) L_0x2aaeb20/d; +L_0x2aaec80/d .functor AND 1, L_0x2aaedc0, L_0x2aaeb20, C4<1>, C4<1>; +L_0x2aaec80 .delay (20000,20000,20000) L_0x2aaec80/d; +L_0x2aaee60/d .functor XOR 1, L_0x2aaf710, L_0x2aae8b0, C4<0>, C4<0>; +L_0x2aaee60 .delay (40000,40000,40000) L_0x2aaee60/d; +L_0x2aaef50/d .functor XOR 1, L_0x2aaee60, L_0x2aaf960, C4<0>, C4<0>; +L_0x2aaef50 .delay (40000,40000,40000) L_0x2aaef50/d; +L_0x2aaf040/d .functor AND 1, L_0x2aaf710, L_0x2aae8b0, C4<1>, C4<1>; +L_0x2aaf040 .delay (20000,20000,20000) L_0x2aaf040/d; +L_0x2aaf1b0/d .functor AND 1, L_0x2aaee60, L_0x2aaf960, C4<1>, C4<1>; +L_0x2aaf1b0 .delay (20000,20000,20000) L_0x2aaf1b0/d; +L_0x2aaf2c0/d .functor OR 1, L_0x2aaf040, L_0x2aaf1b0, C4<0>, C4<0>; +L_0x2aaf2c0 .delay (20000,20000,20000) L_0x2aaf2c0/d; +v0x285d140_0 .net "A", 0 0, L_0x2aaf710; 1 drivers +v0x285d200_0 .net "AandB", 0 0, L_0x2aaf040; 1 drivers +v0x285d2a0_0 .net "AddSubSLTSum", 0 0, L_0x2aaef50; 1 drivers +v0x285d340_0 .net "AxorB", 0 0, L_0x2aaee60; 1 drivers +v0x285d3c0_0 .net "B", 0 0, L_0x2aaf600; 1 drivers +v0x285d470_0 .net "BornB", 0 0, L_0x2aae8b0; 1 drivers +v0x285d530_0 .net "CINandAxorB", 0 0, L_0x2aaf1b0; 1 drivers +v0x285d5b0_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x285d630_0 .net *"_s3", 0 0, L_0x2aaebe0; 1 drivers +v0x285d6b0_0 .net *"_s5", 0 0, L_0x2aaedc0; 1 drivers +v0x285d750_0 .net "carryin", 0 0, L_0x2aaf960; 1 drivers +v0x285d7f0_0 .net "carryout", 0 0, L_0x2aaf2c0; 1 drivers +v0x285d890_0 .net "nB", 0 0, L_0x2aae2a0; 1 drivers +v0x285d940_0 .net "nCmd2", 0 0, L_0x2aaeb20; 1 drivers +v0x285da40_0 .net "subtract", 0 0, L_0x2aaec80; 1 drivers +L_0x2aaea80 .part v0x2960210_0, 0, 1; +L_0x2aaebe0 .part v0x2960210_0, 2, 1; +L_0x2aaedc0 .part v0x2960210_0, 0, 1; +S_0x285cba0 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x285cab0; + .timescale -9 -12; +L_0x2aae610/d .functor NOT 1, L_0x2aaea80, C4<0>, C4<0>, C4<0>; +L_0x2aae610 .delay (10000,10000,10000) L_0x2aae610/d; +L_0x2aae6b0/d .functor AND 1, L_0x2aaf600, L_0x2aae610, C4<1>, C4<1>; +L_0x2aae6b0 .delay (20000,20000,20000) L_0x2aae6b0/d; +L_0x2aae7a0/d .functor AND 1, L_0x2aae2a0, L_0x2aaea80, C4<1>, C4<1>; +L_0x2aae7a0 .delay (20000,20000,20000) L_0x2aae7a0/d; +L_0x2aae8b0/d .functor OR 1, L_0x2aae6b0, L_0x2aae7a0, C4<0>, C4<0>; +L_0x2aae8b0 .delay (20000,20000,20000) L_0x2aae8b0/d; +v0x285cc90_0 .net "S", 0 0, L_0x2aaea80; 1 drivers +v0x285cd30_0 .alias "in0", 0 0, v0x285d3c0_0; +v0x285cdd0_0 .alias "in1", 0 0, v0x285d890_0; +v0x285ce70_0 .net "nS", 0 0, L_0x2aae610; 1 drivers +v0x285cf20_0 .net "out0", 0 0, L_0x2aae6b0; 1 drivers +v0x285cfc0_0 .net "out1", 0 0, L_0x2aae7a0; 1 drivers +v0x285d0a0_0 .alias "outfinal", 0 0, v0x285d470_0; +S_0x285b7a0 .scope generate, "addbits[7]" "addbits[7]" 3 283, 3 283, S_0x2840e20; + .timescale -9 -12; +P_0x285b1b8 .param/l "i" 3 283, +C4<0111>; +S_0x285b910 .scope module, "attempt" "MiddleAddSubSLT" 3 285, 3 189, S_0x285b7a0; + .timescale -9 -12; +L_0x2aaf6a0/d .functor NOT 1, L_0x2ab0b20, C4<0>, C4<0>, C4<0>; +L_0x2aaf6a0 .delay (10000,10000,10000) L_0x2aaf6a0/d; +L_0x2ab0060/d .functor NOT 1, L_0x2ab0120, C4<0>, C4<0>, C4<0>; +L_0x2ab0060 .delay (10000,10000,10000) L_0x2ab0060/d; +L_0x2ab01c0/d .functor AND 1, L_0x2ab0300, L_0x2ab0060, C4<1>, C4<1>; +L_0x2ab01c0 .delay (20000,20000,20000) L_0x2ab01c0/d; +L_0x2ab03a0/d .functor XOR 1, L_0x2ab0c60, L_0x2aafdf0, C4<0>, C4<0>; +L_0x2ab03a0 .delay (40000,40000,40000) L_0x2ab03a0/d; +L_0x2ab0490/d .functor XOR 1, L_0x2ab03a0, L_0x2ab0e50, C4<0>, C4<0>; +L_0x2ab0490 .delay (40000,40000,40000) L_0x2ab0490/d; +L_0x2ab0580/d .functor AND 1, L_0x2ab0c60, L_0x2aafdf0, C4<1>, C4<1>; +L_0x2ab0580 .delay (20000,20000,20000) L_0x2ab0580/d; +L_0x2ab06f0/d .functor AND 1, L_0x2ab03a0, L_0x2ab0e50, C4<1>, C4<1>; +L_0x2ab06f0 .delay (20000,20000,20000) L_0x2ab06f0/d; +L_0x2ab07e0/d .functor OR 1, L_0x2ab0580, L_0x2ab06f0, C4<0>, C4<0>; +L_0x2ab07e0 .delay (20000,20000,20000) L_0x2ab07e0/d; +v0x285bfa0_0 .net "A", 0 0, L_0x2ab0c60; 1 drivers +v0x285c060_0 .net "AandB", 0 0, L_0x2ab0580; 1 drivers +v0x285c100_0 .net "AddSubSLTSum", 0 0, L_0x2ab0490; 1 drivers +v0x285c1a0_0 .net "AxorB", 0 0, L_0x2ab03a0; 1 drivers +v0x285c220_0 .net "B", 0 0, L_0x2ab0b20; 1 drivers +v0x285c2d0_0 .net "BornB", 0 0, L_0x2aafdf0; 1 drivers +v0x285c390_0 .net "CINandAxorB", 0 0, L_0x2ab06f0; 1 drivers +v0x285c410_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x285c490_0 .net *"_s3", 0 0, L_0x2ab0120; 1 drivers +v0x285c510_0 .net *"_s5", 0 0, L_0x2ab0300; 1 drivers +v0x285c5b0_0 .net "carryin", 0 0, L_0x2ab0e50; 1 drivers +v0x285c650_0 .net "carryout", 0 0, L_0x2ab07e0; 1 drivers +v0x285c6f0_0 .net "nB", 0 0, L_0x2aaf6a0; 1 drivers +v0x285c7a0_0 .net "nCmd2", 0 0, L_0x2ab0060; 1 drivers +v0x285c8a0_0 .net "subtract", 0 0, L_0x2ab01c0; 1 drivers +L_0x2aaffc0 .part v0x2960210_0, 0, 1; +L_0x2ab0120 .part v0x2960210_0, 2, 1; +L_0x2ab0300 .part v0x2960210_0, 0, 1; +S_0x285ba00 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x285b910; + .timescale -9 -12; +L_0x2aafb30/d .functor NOT 1, L_0x2aaffc0, C4<0>, C4<0>, C4<0>; +L_0x2aafb30 .delay (10000,10000,10000) L_0x2aafb30/d; +L_0x2aafbd0/d .functor AND 1, L_0x2ab0b20, L_0x2aafb30, C4<1>, C4<1>; +L_0x2aafbd0 .delay (20000,20000,20000) L_0x2aafbd0/d; +L_0x2aafce0/d .functor AND 1, L_0x2aaf6a0, L_0x2aaffc0, C4<1>, C4<1>; +L_0x2aafce0 .delay (20000,20000,20000) L_0x2aafce0/d; +L_0x2aafdf0/d .functor OR 1, L_0x2aafbd0, L_0x2aafce0, C4<0>, C4<0>; +L_0x2aafdf0 .delay (20000,20000,20000) L_0x2aafdf0/d; +v0x285baf0_0 .net "S", 0 0, L_0x2aaffc0; 1 drivers +v0x285bb90_0 .alias "in0", 0 0, v0x285c220_0; +v0x285bc30_0 .alias "in1", 0 0, v0x285c6f0_0; +v0x285bcd0_0 .net "nS", 0 0, L_0x2aafb30; 1 drivers +v0x285bd80_0 .net "out0", 0 0, L_0x2aafbd0; 1 drivers +v0x285be20_0 .net "out1", 0 0, L_0x2aafce0; 1 drivers +v0x285bf00_0 .alias "outfinal", 0 0, v0x285c2d0_0; +S_0x285a600 .scope generate, "addbits[8]" "addbits[8]" 3 283, 3 283, S_0x2840e20; + .timescale -9 -12; +P_0x285a018 .param/l "i" 3 283, +C4<01000>; +S_0x285a770 .scope module, "attempt" "MiddleAddSubSLT" 3 285, 3 189, S_0x285a600; + .timescale -9 -12; +L_0x2ab0d00/d .functor NOT 1, L_0x2ab2040, C4<0>, C4<0>, C4<0>; +L_0x2ab0d00 .delay (10000,10000,10000) L_0x2ab0d00/d; +L_0x2ab1580/d .functor NOT 1, L_0x2ab1640, C4<0>, C4<0>, C4<0>; +L_0x2ab1580 .delay (10000,10000,10000) L_0x2ab1580/d; +L_0x2ab16e0/d .functor AND 1, L_0x2ab1820, L_0x2ab1580, C4<1>, C4<1>; +L_0x2ab16e0 .delay (20000,20000,20000) L_0x2ab16e0/d; +L_0x2ab18c0/d .functor XOR 1, L_0x2ab21b0, L_0x2ab1310, C4<0>, C4<0>; +L_0x2ab18c0 .delay (40000,40000,40000) L_0x2ab18c0/d; +L_0x2ab19b0/d .functor XOR 1, L_0x2ab18c0, L_0x2ab23d0, C4<0>, C4<0>; +L_0x2ab19b0 .delay (40000,40000,40000) L_0x2ab19b0/d; +L_0x2ab1aa0/d .functor AND 1, L_0x2ab21b0, L_0x2ab1310, C4<1>, C4<1>; +L_0x2ab1aa0 .delay (20000,20000,20000) L_0x2ab1aa0/d; +L_0x2ab1c10/d .functor AND 1, L_0x2ab18c0, L_0x2ab23d0, C4<1>, C4<1>; +L_0x2ab1c10 .delay (20000,20000,20000) L_0x2ab1c10/d; +L_0x2ab1d00/d .functor OR 1, L_0x2ab1aa0, L_0x2ab1c10, C4<0>, C4<0>; +L_0x2ab1d00 .delay (20000,20000,20000) L_0x2ab1d00/d; +v0x285ae00_0 .net "A", 0 0, L_0x2ab21b0; 1 drivers +v0x285aec0_0 .net "AandB", 0 0, L_0x2ab1aa0; 1 drivers +v0x285af60_0 .net "AddSubSLTSum", 0 0, L_0x2ab19b0; 1 drivers +v0x285b000_0 .net "AxorB", 0 0, L_0x2ab18c0; 1 drivers +v0x285b080_0 .net "B", 0 0, L_0x2ab2040; 1 drivers +v0x285b130_0 .net "BornB", 0 0, L_0x2ab1310; 1 drivers +v0x285b1f0_0 .net "CINandAxorB", 0 0, L_0x2ab1c10; 1 drivers +v0x285b270_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x285b2f0_0 .net *"_s3", 0 0, L_0x2ab1640; 1 drivers +v0x285b370_0 .net *"_s5", 0 0, L_0x2ab1820; 1 drivers +v0x285b410_0 .net "carryin", 0 0, L_0x2ab23d0; 1 drivers +v0x285b4b0_0 .net "carryout", 0 0, L_0x2ab1d00; 1 drivers +v0x285b550_0 .net "nB", 0 0, L_0x2ab0d00; 1 drivers +v0x285b600_0 .net "nCmd2", 0 0, L_0x2ab1580; 1 drivers +v0x285b700_0 .net "subtract", 0 0, L_0x2ab16e0; 1 drivers +L_0x2ab14e0 .part v0x2960210_0, 0, 1; +L_0x2ab1640 .part v0x2960210_0, 2, 1; +L_0x2ab1820 .part v0x2960210_0, 0, 1; +S_0x285a860 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x285a770; + .timescale -9 -12; +L_0x2ab1050/d .functor NOT 1, L_0x2ab14e0, C4<0>, C4<0>, C4<0>; +L_0x2ab1050 .delay (10000,10000,10000) L_0x2ab1050/d; +L_0x2ab10f0/d .functor AND 1, L_0x2ab2040, L_0x2ab1050, C4<1>, C4<1>; +L_0x2ab10f0 .delay (20000,20000,20000) L_0x2ab10f0/d; +L_0x2ab1200/d .functor AND 1, L_0x2ab0d00, L_0x2ab14e0, C4<1>, C4<1>; +L_0x2ab1200 .delay (20000,20000,20000) L_0x2ab1200/d; +L_0x2ab1310/d .functor OR 1, L_0x2ab10f0, L_0x2ab1200, C4<0>, C4<0>; +L_0x2ab1310 .delay (20000,20000,20000) L_0x2ab1310/d; +v0x285a950_0 .net "S", 0 0, L_0x2ab14e0; 1 drivers +v0x285a9f0_0 .alias "in0", 0 0, v0x285b080_0; +v0x285aa90_0 .alias "in1", 0 0, v0x285b550_0; +v0x285ab30_0 .net "nS", 0 0, L_0x2ab1050; 1 drivers +v0x285abe0_0 .net "out0", 0 0, L_0x2ab10f0; 1 drivers +v0x285ac80_0 .net "out1", 0 0, L_0x2ab1200; 1 drivers +v0x285ad60_0 .alias "outfinal", 0 0, v0x285b130_0; +S_0x2859460 .scope generate, "addbits[9]" "addbits[9]" 3 283, 3 283, S_0x2840e20; + .timescale -9 -12; +P_0x2858e78 .param/l "i" 3 283, +C4<01001>; +S_0x28595d0 .scope module, "attempt" "MiddleAddSubSLT" 3 285, 3 189, S_0x2859460; + .timescale -9 -12; +L_0x2ab0fe0/d .functor NOT 1, L_0x2ab3800, C4<0>, C4<0>, C4<0>; +L_0x2ab0fe0 .delay (10000,10000,10000) L_0x2ab0fe0/d; +L_0x2ab2b90/d .functor NOT 1, L_0x2ab2c50, C4<0>, C4<0>, C4<0>; +L_0x2ab2b90 .delay (10000,10000,10000) L_0x2ab2b90/d; +L_0x2ab2cf0/d .functor AND 1, L_0x2ab2e30, L_0x2ab2b90, C4<1>, C4<1>; +L_0x2ab2cf0 .delay (20000,20000,20000) L_0x2ab2cf0/d; +L_0x2ab2ed0/d .functor XOR 1, L_0x2ab2770, L_0x2ab2920, C4<0>, C4<0>; +L_0x2ab2ed0 .delay (40000,40000,40000) L_0x2ab2ed0/d; +L_0x2ab2fc0/d .functor XOR 1, L_0x2ab2ed0, L_0x2ab3930, C4<0>, C4<0>; +L_0x2ab2fc0 .delay (40000,40000,40000) L_0x2ab2fc0/d; +L_0x2ab30b0/d .functor AND 1, L_0x2ab2770, L_0x2ab2920, C4<1>, C4<1>; +L_0x2ab30b0 .delay (20000,20000,20000) L_0x2ab30b0/d; +L_0x2ab3220/d .functor AND 1, L_0x2ab2ed0, L_0x2ab3930, C4<1>, C4<1>; +L_0x2ab3220 .delay (20000,20000,20000) L_0x2ab3220/d; +L_0x2ab3310/d .functor OR 1, L_0x2ab30b0, L_0x2ab3220, C4<0>, C4<0>; +L_0x2ab3310 .delay (20000,20000,20000) L_0x2ab3310/d; +v0x2859c60_0 .net "A", 0 0, L_0x2ab2770; 1 drivers +v0x2859d20_0 .net "AandB", 0 0, L_0x2ab30b0; 1 drivers +v0x2859dc0_0 .net "AddSubSLTSum", 0 0, L_0x2ab2fc0; 1 drivers +v0x2859e60_0 .net "AxorB", 0 0, L_0x2ab2ed0; 1 drivers +v0x2859ee0_0 .net "B", 0 0, L_0x2ab3800; 1 drivers +v0x2859f90_0 .net "BornB", 0 0, L_0x2ab2920; 1 drivers +v0x285a050_0 .net "CINandAxorB", 0 0, L_0x2ab3220; 1 drivers +v0x285a0d0_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x285a150_0 .net *"_s3", 0 0, L_0x2ab2c50; 1 drivers +v0x285a1d0_0 .net *"_s5", 0 0, L_0x2ab2e30; 1 drivers +v0x285a270_0 .net "carryin", 0 0, L_0x2ab3930; 1 drivers +v0x285a310_0 .net "carryout", 0 0, L_0x2ab3310; 1 drivers +v0x285a3b0_0 .net "nB", 0 0, L_0x2ab0fe0; 1 drivers +v0x285a460_0 .net "nCmd2", 0 0, L_0x2ab2b90; 1 drivers +v0x285a560_0 .net "subtract", 0 0, L_0x2ab2cf0; 1 drivers +L_0x2ab2af0 .part v0x2960210_0, 0, 1; +L_0x2ab2c50 .part v0x2960210_0, 2, 1; +L_0x2ab2e30 .part v0x2960210_0, 0, 1; +S_0x28596c0 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x28595d0; + .timescale -9 -12; +L_0x2ab2250/d .functor NOT 1, L_0x2ab2af0, C4<0>, C4<0>, C4<0>; +L_0x2ab2250 .delay (10000,10000,10000) L_0x2ab2250/d; +L_0x2ab2310/d .functor AND 1, L_0x2ab3800, L_0x2ab2250, C4<1>, C4<1>; +L_0x2ab2310 .delay (20000,20000,20000) L_0x2ab2310/d; +L_0x2ab2810/d .functor AND 1, L_0x2ab0fe0, L_0x2ab2af0, C4<1>, C4<1>; +L_0x2ab2810 .delay (20000,20000,20000) L_0x2ab2810/d; +L_0x2ab2920/d .functor OR 1, L_0x2ab2310, L_0x2ab2810, C4<0>, C4<0>; +L_0x2ab2920 .delay (20000,20000,20000) L_0x2ab2920/d; +v0x28597b0_0 .net "S", 0 0, L_0x2ab2af0; 1 drivers +v0x2859850_0 .alias "in0", 0 0, v0x2859ee0_0; +v0x28598f0_0 .alias "in1", 0 0, v0x285a3b0_0; +v0x2859990_0 .net "nS", 0 0, L_0x2ab2250; 1 drivers +v0x2859a40_0 .net "out0", 0 0, L_0x2ab2310; 1 drivers +v0x2859ae0_0 .net "out1", 0 0, L_0x2ab2810; 1 drivers +v0x2859bc0_0 .alias "outfinal", 0 0, v0x2859f90_0; +S_0x28582c0 .scope generate, "addbits[10]" "addbits[10]" 3 283, 3 283, S_0x2840e20; + .timescale -9 -12; +P_0x2857cd8 .param/l "i" 3 283, +C4<01010>; +S_0x2858430 .scope module, "attempt" "MiddleAddSubSLT" 3 285, 3 189, S_0x28582c0; + .timescale -9 -12; +L_0x2ab3650/d .functor NOT 1, L_0x2ab4d40, C4<0>, C4<0>, C4<0>; +L_0x2ab3650 .delay (10000,10000,10000) L_0x2ab3650/d; +L_0x2ab40a0/d .functor NOT 1, L_0x2ab4160, C4<0>, C4<0>, C4<0>; +L_0x2ab40a0 .delay (10000,10000,10000) L_0x2ab40a0/d; +L_0x2ab4200/d .functor AND 1, L_0x2ab4340, L_0x2ab40a0, C4<1>, C4<1>; +L_0x2ab4200 .delay (20000,20000,20000) L_0x2ab4200/d; +L_0x2ab43e0/d .functor XOR 1, L_0x2ab3ac0, L_0x2ab3e30, C4<0>, C4<0>; +L_0x2ab43e0 .delay (40000,40000,40000) L_0x2ab43e0/d; +L_0x2ab44d0/d .functor XOR 1, L_0x2ab43e0, L_0x2ab4e70, C4<0>, C4<0>; +L_0x2ab44d0 .delay (40000,40000,40000) L_0x2ab44d0/d; +L_0x2ab45c0/d .functor AND 1, L_0x2ab3ac0, L_0x2ab3e30, C4<1>, C4<1>; +L_0x2ab45c0 .delay (20000,20000,20000) L_0x2ab45c0/d; +L_0x2ab4730/d .functor AND 1, L_0x2ab43e0, L_0x2ab4e70, C4<1>, C4<1>; +L_0x2ab4730 .delay (20000,20000,20000) L_0x2ab4730/d; +L_0x2ab4820/d .functor OR 1, L_0x2ab45c0, L_0x2ab4730, C4<0>, C4<0>; +L_0x2ab4820 .delay (20000,20000,20000) L_0x2ab4820/d; +v0x2858ac0_0 .net "A", 0 0, L_0x2ab3ac0; 1 drivers +v0x2858b80_0 .net "AandB", 0 0, L_0x2ab45c0; 1 drivers +v0x2858c20_0 .net "AddSubSLTSum", 0 0, L_0x2ab44d0; 1 drivers +v0x2858cc0_0 .net "AxorB", 0 0, L_0x2ab43e0; 1 drivers +v0x2858d40_0 .net "B", 0 0, L_0x2ab4d40; 1 drivers +v0x2858df0_0 .net "BornB", 0 0, L_0x2ab3e30; 1 drivers +v0x2858eb0_0 .net "CINandAxorB", 0 0, L_0x2ab4730; 1 drivers +v0x2858f30_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x2858fb0_0 .net *"_s3", 0 0, L_0x2ab4160; 1 drivers +v0x2859030_0 .net *"_s5", 0 0, L_0x2ab4340; 1 drivers +v0x28590d0_0 .net "carryin", 0 0, L_0x2ab4e70; 1 drivers +v0x2859170_0 .net "carryout", 0 0, L_0x2ab4820; 1 drivers +v0x2859210_0 .net "nB", 0 0, L_0x2ab3650; 1 drivers +v0x28592c0_0 .net "nCmd2", 0 0, L_0x2ab40a0; 1 drivers +v0x28593c0_0 .net "subtract", 0 0, L_0x2ab4200; 1 drivers +L_0x2ab4000 .part v0x2960210_0, 0, 1; +L_0x2ab4160 .part v0x2960210_0, 2, 1; +L_0x2ab4340 .part v0x2960210_0, 0, 1; +S_0x2858520 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x2858430; + .timescale -9 -12; +L_0x2ab3b90/d .functor NOT 1, L_0x2ab4000, C4<0>, C4<0>, C4<0>; +L_0x2ab3b90 .delay (10000,10000,10000) L_0x2ab3b90/d; +L_0x2ab3c30/d .functor AND 1, L_0x2ab4d40, L_0x2ab3b90, C4<1>, C4<1>; +L_0x2ab3c30 .delay (20000,20000,20000) L_0x2ab3c30/d; +L_0x2ab3d20/d .functor AND 1, L_0x2ab3650, L_0x2ab4000, C4<1>, C4<1>; +L_0x2ab3d20 .delay (20000,20000,20000) L_0x2ab3d20/d; +L_0x2ab3e30/d .functor OR 1, L_0x2ab3c30, L_0x2ab3d20, C4<0>, C4<0>; +L_0x2ab3e30 .delay (20000,20000,20000) L_0x2ab3e30/d; +v0x2858610_0 .net "S", 0 0, L_0x2ab4000; 1 drivers +v0x28586b0_0 .alias "in0", 0 0, v0x2858d40_0; +v0x2858750_0 .alias "in1", 0 0, v0x2859210_0; +v0x28587f0_0 .net "nS", 0 0, L_0x2ab3b90; 1 drivers +v0x28588a0_0 .net "out0", 0 0, L_0x2ab3c30; 1 drivers +v0x2858940_0 .net "out1", 0 0, L_0x2ab3d20; 1 drivers +v0x2858a20_0 .alias "outfinal", 0 0, v0x2858df0_0; +S_0x2857120 .scope generate, "addbits[11]" "addbits[11]" 3 283, 3 283, S_0x2840e20; + .timescale -9 -12; +P_0x2856b38 .param/l "i" 3 283, +C4<01011>; +S_0x2857290 .scope module, "attempt" "MiddleAddSubSLT" 3 285, 3 189, S_0x2857120; + .timescale -9 -12; +L_0x2ab4b60/d .functor NOT 1, L_0x2ab6280, C4<0>, C4<0>, C4<0>; +L_0x2ab4b60 .delay (10000,10000,10000) L_0x2ab4b60/d; +L_0x2ab55b0/d .functor NOT 1, L_0x2ab5670, C4<0>, C4<0>, C4<0>; +L_0x2ab55b0 .delay (10000,10000,10000) L_0x2ab55b0/d; +L_0x2ab5710/d .functor AND 1, L_0x2ab5850, L_0x2ab55b0, C4<1>, C4<1>; +L_0x2ab5710 .delay (20000,20000,20000) L_0x2ab5710/d; +L_0x2ab58f0/d .functor XOR 1, L_0x2ab5000, L_0x2ab5340, C4<0>, C4<0>; +L_0x2ab58f0 .delay (40000,40000,40000) L_0x2ab58f0/d; +L_0x2ab59e0/d .functor XOR 1, L_0x2ab58f0, L_0x2ab63b0, C4<0>, C4<0>; +L_0x2ab59e0 .delay (40000,40000,40000) L_0x2ab59e0/d; +L_0x2ab5ad0/d .functor AND 1, L_0x2ab5000, L_0x2ab5340, C4<1>, C4<1>; +L_0x2ab5ad0 .delay (20000,20000,20000) L_0x2ab5ad0/d; +L_0x2ab5c40/d .functor AND 1, L_0x2ab58f0, L_0x2ab63b0, C4<1>, C4<1>; +L_0x2ab5c40 .delay (20000,20000,20000) L_0x2ab5c40/d; +L_0x2ab5d30/d .functor OR 1, L_0x2ab5ad0, L_0x2ab5c40, C4<0>, C4<0>; +L_0x2ab5d30 .delay (20000,20000,20000) L_0x2ab5d30/d; +v0x2857920_0 .net "A", 0 0, L_0x2ab5000; 1 drivers +v0x28579e0_0 .net "AandB", 0 0, L_0x2ab5ad0; 1 drivers +v0x2857a80_0 .net "AddSubSLTSum", 0 0, L_0x2ab59e0; 1 drivers +v0x2857b20_0 .net "AxorB", 0 0, L_0x2ab58f0; 1 drivers +v0x2857ba0_0 .net "B", 0 0, L_0x2ab6280; 1 drivers +v0x2857c50_0 .net "BornB", 0 0, L_0x2ab5340; 1 drivers +v0x2857d10_0 .net "CINandAxorB", 0 0, L_0x2ab5c40; 1 drivers +v0x2857d90_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x2857e10_0 .net *"_s3", 0 0, L_0x2ab5670; 1 drivers +v0x2857e90_0 .net *"_s5", 0 0, L_0x2ab5850; 1 drivers +v0x2857f30_0 .net "carryin", 0 0, L_0x2ab63b0; 1 drivers +v0x2857fd0_0 .net "carryout", 0 0, L_0x2ab5d30; 1 drivers +v0x2858070_0 .net "nB", 0 0, L_0x2ab4b60; 1 drivers +v0x2858120_0 .net "nCmd2", 0 0, L_0x2ab55b0; 1 drivers +v0x2858220_0 .net "subtract", 0 0, L_0x2ab5710; 1 drivers +L_0x2ab5510 .part v0x2960210_0, 0, 1; +L_0x2ab5670 .part v0x2960210_0, 2, 1; +L_0x2ab5850 .part v0x2960210_0, 0, 1; +S_0x2857380 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x2857290; + .timescale -9 -12; +L_0x2ab4cc0/d .functor NOT 1, L_0x2ab5510, C4<0>, C4<0>, C4<0>; +L_0x2ab4cc0 .delay (10000,10000,10000) L_0x2ab4cc0/d; +L_0x2ab5140/d .functor AND 1, L_0x2ab6280, L_0x2ab4cc0, C4<1>, C4<1>; +L_0x2ab5140 .delay (20000,20000,20000) L_0x2ab5140/d; +L_0x2ab5230/d .functor AND 1, L_0x2ab4b60, L_0x2ab5510, C4<1>, C4<1>; +L_0x2ab5230 .delay (20000,20000,20000) L_0x2ab5230/d; +L_0x2ab5340/d .functor OR 1, L_0x2ab5140, L_0x2ab5230, C4<0>, C4<0>; +L_0x2ab5340 .delay (20000,20000,20000) L_0x2ab5340/d; +v0x2857470_0 .net "S", 0 0, L_0x2ab5510; 1 drivers +v0x2857510_0 .alias "in0", 0 0, v0x2857ba0_0; +v0x28575b0_0 .alias "in1", 0 0, v0x2858070_0; +v0x2857650_0 .net "nS", 0 0, L_0x2ab4cc0; 1 drivers +v0x2857700_0 .net "out0", 0 0, L_0x2ab5140; 1 drivers +v0x28577a0_0 .net "out1", 0 0, L_0x2ab5230; 1 drivers +v0x2857880_0 .alias "outfinal", 0 0, v0x2857c50_0; +S_0x2855f80 .scope generate, "addbits[12]" "addbits[12]" 3 283, 3 283, S_0x2840e20; + .timescale -9 -12; +P_0x2855998 .param/l "i" 3 283, +C4<01100>; +S_0x28560f0 .scope module, "attempt" "MiddleAddSubSLT" 3 285, 3 189, S_0x2855f80; + .timescale -9 -12; +L_0x2ab50a0/d .functor NOT 1, L_0x2ab77c0, C4<0>, C4<0>, C4<0>; +L_0x2ab50a0 .delay (10000,10000,10000) L_0x2ab50a0/d; +L_0x2ab6ac0/d .functor NOT 1, L_0x2ab6b80, C4<0>, C4<0>, C4<0>; +L_0x2ab6ac0 .delay (10000,10000,10000) L_0x2ab6ac0/d; +L_0x2ab6c20/d .functor AND 1, L_0x2ab6d60, L_0x2ab6ac0, C4<1>, C4<1>; +L_0x2ab6c20 .delay (20000,20000,20000) L_0x2ab6c20/d; +L_0x2ab6e00/d .functor XOR 1, L_0x2ab6540, L_0x2ab6850, C4<0>, C4<0>; +L_0x2ab6e00 .delay (40000,40000,40000) L_0x2ab6e00/d; +L_0x2ab6ef0/d .functor XOR 1, L_0x2ab6e00, L_0x2ab7860, C4<0>, C4<0>; +L_0x2ab6ef0 .delay (40000,40000,40000) L_0x2ab6ef0/d; +L_0x2ab6fe0/d .functor AND 1, L_0x2ab6540, L_0x2ab6850, C4<1>, C4<1>; +L_0x2ab6fe0 .delay (20000,20000,20000) L_0x2ab6fe0/d; +L_0x2ab7150/d .functor AND 1, L_0x2ab6e00, L_0x2ab7860, C4<1>, C4<1>; +L_0x2ab7150 .delay (20000,20000,20000) L_0x2ab7150/d; +L_0x2ab7240/d .functor OR 1, L_0x2ab6fe0, L_0x2ab7150, C4<0>, C4<0>; +L_0x2ab7240 .delay (20000,20000,20000) L_0x2ab7240/d; +v0x2856780_0 .net "A", 0 0, L_0x2ab6540; 1 drivers +v0x2856840_0 .net "AandB", 0 0, L_0x2ab6fe0; 1 drivers +v0x28568e0_0 .net "AddSubSLTSum", 0 0, L_0x2ab6ef0; 1 drivers +v0x2856980_0 .net "AxorB", 0 0, L_0x2ab6e00; 1 drivers +v0x2856a00_0 .net "B", 0 0, L_0x2ab77c0; 1 drivers +v0x2856ab0_0 .net "BornB", 0 0, L_0x2ab6850; 1 drivers +v0x2856b70_0 .net "CINandAxorB", 0 0, L_0x2ab7150; 1 drivers +v0x2856bf0_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x2856c70_0 .net *"_s3", 0 0, L_0x2ab6b80; 1 drivers +v0x2856cf0_0 .net *"_s5", 0 0, L_0x2ab6d60; 1 drivers +v0x2856d90_0 .net "carryin", 0 0, L_0x2ab7860; 1 drivers +v0x2856e30_0 .net "carryout", 0 0, L_0x2ab7240; 1 drivers +v0x2856ed0_0 .net "nB", 0 0, L_0x2ab50a0; 1 drivers +v0x2856f80_0 .net "nCmd2", 0 0, L_0x2ab6ac0; 1 drivers +v0x2857080_0 .net "subtract", 0 0, L_0x2ab6c20; 1 drivers +L_0x2ab6a20 .part v0x2960210_0, 0, 1; +L_0x2ab6b80 .part v0x2960210_0, 2, 1; +L_0x2ab6d60 .part v0x2960210_0, 0, 1; +S_0x28561e0 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x28560f0; + .timescale -9 -12; +L_0x2ab6170/d .functor NOT 1, L_0x2ab6a20, C4<0>, C4<0>, C4<0>; +L_0x2ab6170 .delay (10000,10000,10000) L_0x2ab6170/d; +L_0x2ab6670/d .functor AND 1, L_0x2ab77c0, L_0x2ab6170, C4<1>, C4<1>; +L_0x2ab6670 .delay (20000,20000,20000) L_0x2ab6670/d; +L_0x2ab6760/d .functor AND 1, L_0x2ab50a0, L_0x2ab6a20, C4<1>, C4<1>; +L_0x2ab6760 .delay (20000,20000,20000) L_0x2ab6760/d; +L_0x2ab6850/d .functor OR 1, L_0x2ab6670, L_0x2ab6760, C4<0>, C4<0>; +L_0x2ab6850 .delay (20000,20000,20000) L_0x2ab6850/d; +v0x28562d0_0 .net "S", 0 0, L_0x2ab6a20; 1 drivers +v0x2856370_0 .alias "in0", 0 0, v0x2856a00_0; +v0x2856410_0 .alias "in1", 0 0, v0x2856ed0_0; +v0x28564b0_0 .net "nS", 0 0, L_0x2ab6170; 1 drivers +v0x2856560_0 .net "out0", 0 0, L_0x2ab6670; 1 drivers +v0x2856600_0 .net "out1", 0 0, L_0x2ab6760; 1 drivers +v0x28566e0_0 .alias "outfinal", 0 0, v0x2856ab0_0; +S_0x2854de0 .scope generate, "addbits[13]" "addbits[13]" 3 283, 3 283, S_0x2840e20; + .timescale -9 -12; +P_0x28547f8 .param/l "i" 3 283, +C4<01101>; +S_0x2854f50 .scope module, "attempt" "MiddleAddSubSLT" 3 285, 3 189, S_0x2854de0; + .timescale -9 -12; +L_0x2ab7580/d .functor NOT 1, L_0x2ab7a90, C4<0>, C4<0>, C4<0>; +L_0x2ab7580 .delay (10000,10000,10000) L_0x2ab7580/d; +L_0x2ab7fc0/d .functor NOT 1, L_0x2ab8080, C4<0>, C4<0>, C4<0>; +L_0x2ab7fc0 .delay (10000,10000,10000) L_0x2ab7fc0/d; +L_0x2ab8120/d .functor AND 1, L_0x2ab8260, L_0x2ab7fc0, C4<1>, C4<1>; +L_0x2ab8120 .delay (20000,20000,20000) L_0x2ab8120/d; +L_0x2ab8300/d .functor XOR 1, L_0x2ab79f0, L_0x2ab7d50, C4<0>, C4<0>; +L_0x2ab8300 .delay (40000,40000,40000) L_0x2ab8300/d; +L_0x2ab83f0/d .functor XOR 1, L_0x2ab8300, L_0x2ab8d80, C4<0>, C4<0>; +L_0x2ab83f0 .delay (40000,40000,40000) L_0x2ab83f0/d; +L_0x2ab84e0/d .functor AND 1, L_0x2ab79f0, L_0x2ab7d50, C4<1>, C4<1>; +L_0x2ab84e0 .delay (20000,20000,20000) L_0x2ab84e0/d; +L_0x2ab8650/d .functor AND 1, L_0x2ab8300, L_0x2ab8d80, C4<1>, C4<1>; +L_0x2ab8650 .delay (20000,20000,20000) L_0x2ab8650/d; +L_0x2ab8740/d .functor OR 1, L_0x2ab84e0, L_0x2ab8650, C4<0>, C4<0>; +L_0x2ab8740 .delay (20000,20000,20000) L_0x2ab8740/d; +v0x28555e0_0 .net "A", 0 0, L_0x2ab79f0; 1 drivers +v0x28556a0_0 .net "AandB", 0 0, L_0x2ab84e0; 1 drivers +v0x2855740_0 .net "AddSubSLTSum", 0 0, L_0x2ab83f0; 1 drivers +v0x28557e0_0 .net "AxorB", 0 0, L_0x2ab8300; 1 drivers +v0x2855860_0 .net "B", 0 0, L_0x2ab7a90; 1 drivers +v0x2855910_0 .net "BornB", 0 0, L_0x2ab7d50; 1 drivers +v0x28559d0_0 .net "CINandAxorB", 0 0, L_0x2ab8650; 1 drivers +v0x2855a50_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x2855ad0_0 .net *"_s3", 0 0, L_0x2ab8080; 1 drivers +v0x2855b50_0 .net *"_s5", 0 0, L_0x2ab8260; 1 drivers +v0x2855bf0_0 .net "carryin", 0 0, L_0x2ab8d80; 1 drivers +v0x2855c90_0 .net "carryout", 0 0, L_0x2ab8740; 1 drivers +v0x2855d30_0 .net "nB", 0 0, L_0x2ab7580; 1 drivers +v0x2855de0_0 .net "nCmd2", 0 0, L_0x2ab7fc0; 1 drivers +v0x2855ee0_0 .net "subtract", 0 0, L_0x2ab8120; 1 drivers +L_0x2ab7f20 .part v0x2960210_0, 0, 1; +L_0x2ab8080 .part v0x2960210_0, 2, 1; +L_0x2ab8260 .part v0x2960210_0, 0, 1; +S_0x2855040 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x2854f50; + .timescale -9 -12; +L_0x2ab76e0/d .functor NOT 1, L_0x2ab7f20, C4<0>, C4<0>, C4<0>; +L_0x2ab76e0 .delay (10000,10000,10000) L_0x2ab76e0/d; +L_0x2ab7b50/d .functor AND 1, L_0x2ab7a90, L_0x2ab76e0, C4<1>, C4<1>; +L_0x2ab7b50 .delay (20000,20000,20000) L_0x2ab7b50/d; +L_0x2ab7c40/d .functor AND 1, L_0x2ab7580, L_0x2ab7f20, C4<1>, C4<1>; +L_0x2ab7c40 .delay (20000,20000,20000) L_0x2ab7c40/d; +L_0x2ab7d50/d .functor OR 1, L_0x2ab7b50, L_0x2ab7c40, C4<0>, C4<0>; +L_0x2ab7d50 .delay (20000,20000,20000) L_0x2ab7d50/d; +v0x2855130_0 .net "S", 0 0, L_0x2ab7f20; 1 drivers +v0x28551d0_0 .alias "in0", 0 0, v0x2855860_0; +v0x2855270_0 .alias "in1", 0 0, v0x2855d30_0; +v0x2855310_0 .net "nS", 0 0, L_0x2ab76e0; 1 drivers +v0x28553c0_0 .net "out0", 0 0, L_0x2ab7b50; 1 drivers +v0x2855460_0 .net "out1", 0 0, L_0x2ab7c40; 1 drivers +v0x2855540_0 .alias "outfinal", 0 0, v0x2855910_0; +S_0x2853c40 .scope generate, "addbits[14]" "addbits[14]" 3 283, 3 283, S_0x2840e20; + .timescale -9 -12; +P_0x2853658 .param/l "i" 3 283, +C4<01110>; +S_0x2853db0 .scope module, "attempt" "MiddleAddSubSLT" 3 285, 3 189, S_0x2853c40; + .timescale -9 -12; +L_0x2ab8a80/d .functor NOT 1, L_0x2ab8fb0, C4<0>, C4<0>, C4<0>; +L_0x2ab8a80 .delay (10000,10000,10000) L_0x2ab8a80/d; +L_0x2ab94d0/d .functor NOT 1, L_0x2ab9590, C4<0>, C4<0>, C4<0>; +L_0x2ab94d0 .delay (10000,10000,10000) L_0x2ab94d0/d; +L_0x2ab9630/d .functor AND 1, L_0x2ab9770, L_0x2ab94d0, C4<1>, C4<1>; +L_0x2ab9630 .delay (20000,20000,20000) L_0x2ab9630/d; +L_0x2ab9810/d .functor XOR 1, L_0x2ab8f10, L_0x2ab9260, C4<0>, C4<0>; +L_0x2ab9810 .delay (40000,40000,40000) L_0x2ab9810/d; +L_0x2ab9900/d .functor XOR 1, L_0x2ab9810, L_0x2aba2c0, C4<0>, C4<0>; +L_0x2ab9900 .delay (40000,40000,40000) L_0x2ab9900/d; +L_0x2ab99f0/d .functor AND 1, L_0x2ab8f10, L_0x2ab9260, C4<1>, C4<1>; +L_0x2ab99f0 .delay (20000,20000,20000) L_0x2ab99f0/d; +L_0x2ab9b60/d .functor AND 1, L_0x2ab9810, L_0x2aba2c0, C4<1>, C4<1>; +L_0x2ab9b60 .delay (20000,20000,20000) L_0x2ab9b60/d; +L_0x2ab9c50/d .functor OR 1, L_0x2ab99f0, L_0x2ab9b60, C4<0>, C4<0>; +L_0x2ab9c50 .delay (20000,20000,20000) L_0x2ab9c50/d; +v0x2854440_0 .net "A", 0 0, L_0x2ab8f10; 1 drivers +v0x2854500_0 .net "AandB", 0 0, L_0x2ab99f0; 1 drivers +v0x28545a0_0 .net "AddSubSLTSum", 0 0, L_0x2ab9900; 1 drivers +v0x2854640_0 .net "AxorB", 0 0, L_0x2ab9810; 1 drivers +v0x28546c0_0 .net "B", 0 0, L_0x2ab8fb0; 1 drivers +v0x2854770_0 .net "BornB", 0 0, L_0x2ab9260; 1 drivers +v0x2854830_0 .net "CINandAxorB", 0 0, L_0x2ab9b60; 1 drivers +v0x28548b0_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x2854930_0 .net *"_s3", 0 0, L_0x2ab9590; 1 drivers +v0x28549b0_0 .net *"_s5", 0 0, L_0x2ab9770; 1 drivers +v0x2854a50_0 .net "carryin", 0 0, L_0x2aba2c0; 1 drivers +v0x2854af0_0 .net "carryout", 0 0, L_0x2ab9c50; 1 drivers +v0x2854b90_0 .net "nB", 0 0, L_0x2ab8a80; 1 drivers +v0x2854c40_0 .net "nCmd2", 0 0, L_0x2ab94d0; 1 drivers +v0x2854d40_0 .net "subtract", 0 0, L_0x2ab9630; 1 drivers +L_0x2ab9430 .part v0x2960210_0, 0, 1; +L_0x2ab9590 .part v0x2960210_0, 2, 1; +L_0x2ab9770 .part v0x2960210_0, 0, 1; +S_0x2853ea0 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x2853db0; + .timescale -9 -12; +L_0x2ab8bc0/d .functor NOT 1, L_0x2ab9430, C4<0>, C4<0>, C4<0>; +L_0x2ab8bc0 .delay (10000,10000,10000) L_0x2ab8bc0/d; +L_0x2ab8c80/d .functor AND 1, L_0x2ab8fb0, L_0x2ab8bc0, C4<1>, C4<1>; +L_0x2ab8c80 .delay (20000,20000,20000) L_0x2ab8c80/d; +L_0x2ab9150/d .functor AND 1, L_0x2ab8a80, L_0x2ab9430, C4<1>, C4<1>; +L_0x2ab9150 .delay (20000,20000,20000) L_0x2ab9150/d; +L_0x2ab9260/d .functor OR 1, L_0x2ab8c80, L_0x2ab9150, C4<0>, C4<0>; +L_0x2ab9260 .delay (20000,20000,20000) L_0x2ab9260/d; +v0x2853f90_0 .net "S", 0 0, L_0x2ab9430; 1 drivers +v0x2854030_0 .alias "in0", 0 0, v0x28546c0_0; +v0x28540d0_0 .alias "in1", 0 0, v0x2854b90_0; +v0x2854170_0 .net "nS", 0 0, L_0x2ab8bc0; 1 drivers +v0x2854220_0 .net "out0", 0 0, L_0x2ab8c80; 1 drivers +v0x28542c0_0 .net "out1", 0 0, L_0x2ab9150; 1 drivers +v0x28543a0_0 .alias "outfinal", 0 0, v0x2854770_0; +S_0x2852aa0 .scope generate, "addbits[15]" "addbits[15]" 3 283, 3 283, S_0x2840e20; + .timescale -9 -12; +P_0x28524b8 .param/l "i" 3 283, +C4<01111>; +S_0x2852c10 .scope module, "attempt" "MiddleAddSubSLT" 3 285, 3 189, S_0x2852aa0; + .timescale -9 -12; +L_0x2ab9f90/d .functor NOT 1, L_0x2aba4f0, C4<0>, C4<0>, C4<0>; +L_0x2ab9f90 .delay (10000,10000,10000) L_0x2ab9f90/d; +L_0x2aba9e0/d .functor NOT 1, L_0x2abaaa0, C4<0>, C4<0>, C4<0>; +L_0x2aba9e0 .delay (10000,10000,10000) L_0x2aba9e0/d; +L_0x2abab40/d .functor AND 1, L_0x2abac80, L_0x2aba9e0, C4<1>, C4<1>; +L_0x2abab40 .delay (20000,20000,20000) L_0x2abab40/d; +L_0x2abad20/d .functor XOR 1, L_0x2aba450, L_0x2aba770, C4<0>, C4<0>; +L_0x2abad20 .delay (40000,40000,40000) L_0x2abad20/d; +L_0x2abae10/d .functor XOR 1, L_0x2abad20, L_0x2abb800, C4<0>, C4<0>; +L_0x2abae10 .delay (40000,40000,40000) L_0x2abae10/d; +L_0x2abaf00/d .functor AND 1, L_0x2aba450, L_0x2aba770, C4<1>, C4<1>; +L_0x2abaf00 .delay (20000,20000,20000) L_0x2abaf00/d; +L_0x2abb070/d .functor AND 1, L_0x2abad20, L_0x2abb800, C4<1>, C4<1>; +L_0x2abb070 .delay (20000,20000,20000) L_0x2abb070/d; +L_0x2abb160/d .functor OR 1, L_0x2abaf00, L_0x2abb070, C4<0>, C4<0>; +L_0x2abb160 .delay (20000,20000,20000) L_0x2abb160/d; +v0x28532a0_0 .net "A", 0 0, L_0x2aba450; 1 drivers +v0x2853360_0 .net "AandB", 0 0, L_0x2abaf00; 1 drivers +v0x2853400_0 .net "AddSubSLTSum", 0 0, L_0x2abae10; 1 drivers +v0x28534a0_0 .net "AxorB", 0 0, L_0x2abad20; 1 drivers +v0x2853520_0 .net "B", 0 0, L_0x2aba4f0; 1 drivers +v0x28535d0_0 .net "BornB", 0 0, L_0x2aba770; 1 drivers +v0x2853690_0 .net "CINandAxorB", 0 0, L_0x2abb070; 1 drivers +v0x2853710_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x2853790_0 .net *"_s3", 0 0, L_0x2abaaa0; 1 drivers +v0x2853810_0 .net *"_s5", 0 0, L_0x2abac80; 1 drivers +v0x28538b0_0 .net "carryin", 0 0, L_0x2abb800; 1 drivers +v0x2853950_0 .net "carryout", 0 0, L_0x2abb160; 1 drivers +v0x28539f0_0 .net "nB", 0 0, L_0x2ab9f90; 1 drivers +v0x2853aa0_0 .net "nCmd2", 0 0, L_0x2aba9e0; 1 drivers +v0x2853ba0_0 .net "subtract", 0 0, L_0x2abab40; 1 drivers +L_0x2aba940 .part v0x2960210_0, 0, 1; +L_0x2abaaa0 .part v0x2960210_0, 2, 1; +L_0x2abac80 .part v0x2960210_0, 0, 1; +S_0x2852d00 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x2852c10; + .timescale -9 -12; +L_0x2aba0a0/d .functor NOT 1, L_0x2aba940, C4<0>, C4<0>, C4<0>; +L_0x2aba0a0 .delay (10000,10000,10000) L_0x2aba0a0/d; +L_0x2aba160/d .functor AND 1, L_0x2aba4f0, L_0x2aba0a0, C4<1>, C4<1>; +L_0x2aba160 .delay (20000,20000,20000) L_0x2aba160/d; +L_0x2aba660/d .functor AND 1, L_0x2ab9f90, L_0x2aba940, C4<1>, C4<1>; +L_0x2aba660 .delay (20000,20000,20000) L_0x2aba660/d; +L_0x2aba770/d .functor OR 1, L_0x2aba160, L_0x2aba660, C4<0>, C4<0>; +L_0x2aba770 .delay (20000,20000,20000) L_0x2aba770/d; +v0x2852df0_0 .net "S", 0 0, L_0x2aba940; 1 drivers +v0x2852e90_0 .alias "in0", 0 0, v0x2853520_0; +v0x2852f30_0 .alias "in1", 0 0, v0x28539f0_0; +v0x2852fd0_0 .net "nS", 0 0, L_0x2aba0a0; 1 drivers +v0x2853080_0 .net "out0", 0 0, L_0x2aba160; 1 drivers +v0x2853120_0 .net "out1", 0 0, L_0x2aba660; 1 drivers +v0x2853200_0 .alias "outfinal", 0 0, v0x28535d0_0; +S_0x2851900 .scope generate, "addbits[16]" "addbits[16]" 3 283, 3 283, S_0x2840e20; + .timescale -9 -12; +P_0x2851318 .param/l "i" 3 283, +C4<010000>; +S_0x2851a70 .scope module, "attempt" "MiddleAddSubSLT" 3 285, 3 189, S_0x2851900; + .timescale -9 -12; +L_0x2aba590/d .functor NOT 1, L_0x2abba30, C4<0>, C4<0>, C4<0>; +L_0x2aba590 .delay (10000,10000,10000) L_0x2aba590/d; +L_0x2abbee0/d .functor NOT 1, L_0x2abbfa0, C4<0>, C4<0>, C4<0>; +L_0x2abbee0 .delay (10000,10000,10000) L_0x2abbee0/d; +L_0x2aaa490/d .functor AND 1, L_0x2abc0d0, L_0x2abbee0, C4<1>, C4<1>; +L_0x2aaa490 .delay (20000,20000,20000) L_0x2aaa490/d; +L_0x2abc170/d .functor XOR 1, L_0x2abb990, L_0x2abbc70, C4<0>, C4<0>; +L_0x2abc170 .delay (40000,40000,40000) L_0x2abc170/d; +L_0x2abc260/d .functor XOR 1, L_0x2abc170, L_0x2abcbd0, C4<0>, C4<0>; +L_0x2abc260 .delay (40000,40000,40000) L_0x2abc260/d; +L_0x2abc350/d .functor AND 1, L_0x2abb990, L_0x2abbc70, C4<1>, C4<1>; +L_0x2abc350 .delay (20000,20000,20000) L_0x2abc350/d; +L_0x2abc4c0/d .functor AND 1, L_0x2abc170, L_0x2abcbd0, C4<1>, C4<1>; +L_0x2abc4c0 .delay (20000,20000,20000) L_0x2abc4c0/d; +L_0x2abc5b0/d .functor OR 1, L_0x2abc350, L_0x2abc4c0, C4<0>, C4<0>; +L_0x2abc5b0 .delay (20000,20000,20000) L_0x2abc5b0/d; +v0x2852100_0 .net "A", 0 0, L_0x2abb990; 1 drivers +v0x28521c0_0 .net "AandB", 0 0, L_0x2abc350; 1 drivers +v0x2852260_0 .net "AddSubSLTSum", 0 0, L_0x2abc260; 1 drivers +v0x2852300_0 .net "AxorB", 0 0, L_0x2abc170; 1 drivers +v0x2852380_0 .net "B", 0 0, L_0x2abba30; 1 drivers +v0x2852430_0 .net "BornB", 0 0, L_0x2abbc70; 1 drivers +v0x28524f0_0 .net "CINandAxorB", 0 0, L_0x2abc4c0; 1 drivers +v0x2852570_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x28525f0_0 .net *"_s3", 0 0, L_0x2abbfa0; 1 drivers +v0x2852670_0 .net *"_s5", 0 0, L_0x2abc0d0; 1 drivers +v0x2852710_0 .net "carryin", 0 0, L_0x2abcbd0; 1 drivers +v0x28527b0_0 .net "carryout", 0 0, L_0x2abc5b0; 1 drivers +v0x2852850_0 .net "nB", 0 0, L_0x2aba590; 1 drivers +v0x2852900_0 .net "nCmd2", 0 0, L_0x2abbee0; 1 drivers +v0x2852a00_0 .net "subtract", 0 0, L_0x2aaa490; 1 drivers +L_0x2abbe40 .part v0x2960210_0, 0, 1; +L_0x2abbfa0 .part v0x2960210_0, 2, 1; +L_0x2abc0d0 .part v0x2960210_0, 0, 1; +S_0x2851b60 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x2851a70; + .timescale -9 -12; +L_0x2abb580/d .functor NOT 1, L_0x2abbe40, C4<0>, C4<0>, C4<0>; +L_0x2abb580 .delay (10000,10000,10000) L_0x2abb580/d; +L_0x2abb640/d .functor AND 1, L_0x2abba30, L_0x2abb580, C4<1>, C4<1>; +L_0x2abb640 .delay (20000,20000,20000) L_0x2abb640/d; +L_0x2abbb80/d .functor AND 1, L_0x2aba590, L_0x2abbe40, C4<1>, C4<1>; +L_0x2abbb80 .delay (20000,20000,20000) L_0x2abbb80/d; +L_0x2abbc70/d .functor OR 1, L_0x2abb640, L_0x2abbb80, C4<0>, C4<0>; +L_0x2abbc70 .delay (20000,20000,20000) L_0x2abbc70/d; +v0x2851c50_0 .net "S", 0 0, L_0x2abbe40; 1 drivers +v0x2851cf0_0 .alias "in0", 0 0, v0x2852380_0; +v0x2851d90_0 .alias "in1", 0 0, v0x2852850_0; +v0x2851e30_0 .net "nS", 0 0, L_0x2abb580; 1 drivers +v0x2851ee0_0 .net "out0", 0 0, L_0x2abb640; 1 drivers +v0x2851f80_0 .net "out1", 0 0, L_0x2abbb80; 1 drivers +v0x2852060_0 .alias "outfinal", 0 0, v0x2852430_0; +S_0x2850760 .scope generate, "addbits[17]" "addbits[17]" 3 283, 3 283, S_0x2840e20; + .timescale -9 -12; +P_0x2850178 .param/l "i" 3 283, +C4<010001>; +S_0x28508d0 .scope module, "attempt" "MiddleAddSubSLT" 3 285, 3 189, S_0x2850760; + .timescale -9 -12; +L_0x2ab2470/d .functor NOT 1, L_0x2abd210, C4<0>, C4<0>, C4<0>; +L_0x2ab2470 .delay (10000,10000,10000) L_0x2ab2470/d; +L_0x2abd510/d .functor NOT 1, L_0x2abd5b0, C4<0>, C4<0>, C4<0>; +L_0x2abd510 .delay (10000,10000,10000) L_0x2abd510/d; +L_0x2abd650/d .functor AND 1, L_0x2abd790, L_0x2abd510, C4<1>, C4<1>; +L_0x2abd650 .delay (20000,20000,20000) L_0x2abd650/d; +L_0x2abd830/d .functor XOR 1, L_0x2abd170, L_0x2abcaf0, C4<0>, C4<0>; +L_0x2abd830 .delay (40000,40000,40000) L_0x2abd830/d; +L_0x2abd920/d .functor XOR 1, L_0x2abd830, L_0x2abe2c0, C4<0>, C4<0>; +L_0x2abd920 .delay (40000,40000,40000) L_0x2abd920/d; +L_0x2abda10/d .functor AND 1, L_0x2abd170, L_0x2abcaf0, C4<1>, C4<1>; +L_0x2abda10 .delay (20000,20000,20000) L_0x2abda10/d; +L_0x2abdb80/d .functor AND 1, L_0x2abd830, L_0x2abe2c0, C4<1>, C4<1>; +L_0x2abdb80 .delay (20000,20000,20000) L_0x2abdb80/d; +L_0x2abdc70/d .functor OR 1, L_0x2abda10, L_0x2abdb80, C4<0>, C4<0>; +L_0x2abdc70 .delay (20000,20000,20000) L_0x2abdc70/d; +v0x2850f60_0 .net "A", 0 0, L_0x2abd170; 1 drivers +v0x2851020_0 .net "AandB", 0 0, L_0x2abda10; 1 drivers +v0x28510c0_0 .net "AddSubSLTSum", 0 0, L_0x2abd920; 1 drivers +v0x2851160_0 .net "AxorB", 0 0, L_0x2abd830; 1 drivers +v0x28511e0_0 .net "B", 0 0, L_0x2abd210; 1 drivers +v0x2851290_0 .net "BornB", 0 0, L_0x2abcaf0; 1 drivers +v0x2851350_0 .net "CINandAxorB", 0 0, L_0x2abdb80; 1 drivers +v0x28513d0_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x2851450_0 .net *"_s3", 0 0, L_0x2abd5b0; 1 drivers +v0x28514d0_0 .net *"_s5", 0 0, L_0x2abd790; 1 drivers +v0x2851570_0 .net "carryin", 0 0, L_0x2abe2c0; 1 drivers +v0x2851610_0 .net "carryout", 0 0, L_0x2abdc70; 1 drivers +v0x28516b0_0 .net "nB", 0 0, L_0x2ab2470; 1 drivers +v0x2851760_0 .net "nCmd2", 0 0, L_0x2abd510; 1 drivers +v0x2851860_0 .net "subtract", 0 0, L_0x2abd650; 1 drivers +L_0x2abd470 .part v0x2960210_0, 0, 1; +L_0x2abd5b0 .part v0x2960210_0, 2, 1; +L_0x2abd790 .part v0x2960210_0, 0, 1; +S_0x28509c0 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x28508d0; + .timescale -9 -12; +L_0x2ab25b0/d .functor NOT 1, L_0x2abd470, C4<0>, C4<0>, C4<0>; +L_0x2ab25b0 .delay (10000,10000,10000) L_0x2ab25b0/d; +L_0x2abc8d0/d .functor AND 1, L_0x2abd210, L_0x2ab25b0, C4<1>, C4<1>; +L_0x2abc8d0 .delay (20000,20000,20000) L_0x2abc8d0/d; +L_0x2abc9e0/d .functor AND 1, L_0x2ab2470, L_0x2abd470, C4<1>, C4<1>; +L_0x2abc9e0 .delay (20000,20000,20000) L_0x2abc9e0/d; +L_0x2abcaf0/d .functor OR 1, L_0x2abc8d0, L_0x2abc9e0, C4<0>, C4<0>; +L_0x2abcaf0 .delay (20000,20000,20000) L_0x2abcaf0/d; +v0x2850ab0_0 .net "S", 0 0, L_0x2abd470; 1 drivers +v0x2850b50_0 .alias "in0", 0 0, v0x28511e0_0; +v0x2850bf0_0 .alias "in1", 0 0, v0x28516b0_0; +v0x2850c90_0 .net "nS", 0 0, L_0x2ab25b0; 1 drivers +v0x2850d40_0 .net "out0", 0 0, L_0x2abc8d0; 1 drivers +v0x2850de0_0 .net "out1", 0 0, L_0x2abc9e0; 1 drivers +v0x2850ec0_0 .alias "outfinal", 0 0, v0x2851290_0; +S_0x284f5c0 .scope generate, "addbits[18]" "addbits[18]" 3 283, 3 283, S_0x2840e20; + .timescale -9 -12; +P_0x284efd8 .param/l "i" 3 283, +C4<010010>; +S_0x284f730 .scope module, "attempt" "MiddleAddSubSLT" 3 285, 3 189, S_0x284f5c0; + .timescale -9 -12; +L_0x2abdf90/d .functor NOT 1, L_0x2abe4f0, C4<0>, C4<0>, C4<0>; +L_0x2abdf90 .delay (10000,10000,10000) L_0x2abdf90/d; +L_0x2abe980/d .functor NOT 1, L_0x2abea20, C4<0>, C4<0>, C4<0>; +L_0x2abe980 .delay (10000,10000,10000) L_0x2abe980/d; +L_0x2abeac0/d .functor AND 1, L_0x2abec00, L_0x2abe980, C4<1>, C4<1>; +L_0x2abeac0 .delay (20000,20000,20000) L_0x2abeac0/d; +L_0x2abeca0/d .functor XOR 1, L_0x2abe450, L_0x2abe750, C4<0>, C4<0>; +L_0x2abeca0 .delay (40000,40000,40000) L_0x2abeca0/d; +L_0x2abed90/d .functor XOR 1, L_0x2abeca0, L_0x2abf760, C4<0>, C4<0>; +L_0x2abed90 .delay (40000,40000,40000) L_0x2abed90/d; +L_0x2abee80/d .functor AND 1, L_0x2abe450, L_0x2abe750, C4<1>, C4<1>; +L_0x2abee80 .delay (20000,20000,20000) L_0x2abee80/d; +L_0x2abeff0/d .functor AND 1, L_0x2abeca0, L_0x2abf760, C4<1>, C4<1>; +L_0x2abeff0 .delay (20000,20000,20000) L_0x2abeff0/d; +L_0x2abf0e0/d .functor OR 1, L_0x2abee80, L_0x2abeff0, C4<0>, C4<0>; +L_0x2abf0e0 .delay (20000,20000,20000) L_0x2abf0e0/d; +v0x284fdc0_0 .net "A", 0 0, L_0x2abe450; 1 drivers +v0x284fe80_0 .net "AandB", 0 0, L_0x2abee80; 1 drivers +v0x284ff20_0 .net "AddSubSLTSum", 0 0, L_0x2abed90; 1 drivers +v0x284ffc0_0 .net "AxorB", 0 0, L_0x2abeca0; 1 drivers +v0x2850040_0 .net "B", 0 0, L_0x2abe4f0; 1 drivers +v0x28500f0_0 .net "BornB", 0 0, L_0x2abe750; 1 drivers +v0x28501b0_0 .net "CINandAxorB", 0 0, L_0x2abeff0; 1 drivers +v0x2850230_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x28502b0_0 .net *"_s3", 0 0, L_0x2abea20; 1 drivers +v0x2850330_0 .net *"_s5", 0 0, L_0x2abec00; 1 drivers +v0x28503d0_0 .net "carryin", 0 0, L_0x2abf760; 1 drivers +v0x2850470_0 .net "carryout", 0 0, L_0x2abf0e0; 1 drivers +v0x2850510_0 .net "nB", 0 0, L_0x2abdf90; 1 drivers +v0x28505c0_0 .net "nCmd2", 0 0, L_0x2abe980; 1 drivers +v0x28506c0_0 .net "subtract", 0 0, L_0x2abeac0; 1 drivers +L_0x2abe8e0 .part v0x2960210_0, 0, 1; +L_0x2abea20 .part v0x2960210_0, 2, 1; +L_0x2abec00 .part v0x2960210_0, 0, 1; +S_0x284f820 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x284f730; + .timescale -9 -12; +L_0x2abe0a0/d .functor NOT 1, L_0x2abe8e0, C4<0>, C4<0>, C4<0>; +L_0x2abe0a0 .delay (10000,10000,10000) L_0x2abe0a0/d; +L_0x2abe160/d .functor AND 1, L_0x2abe4f0, L_0x2abe0a0, C4<1>, C4<1>; +L_0x2abe160 .delay (20000,20000,20000) L_0x2abe160/d; +L_0x2abe6a0/d .functor AND 1, L_0x2abdf90, L_0x2abe8e0, C4<1>, C4<1>; +L_0x2abe6a0 .delay (20000,20000,20000) L_0x2abe6a0/d; +L_0x2abe750/d .functor OR 1, L_0x2abe160, L_0x2abe6a0, C4<0>, C4<0>; +L_0x2abe750 .delay (20000,20000,20000) L_0x2abe750/d; +v0x284f910_0 .net "S", 0 0, L_0x2abe8e0; 1 drivers +v0x284f9b0_0 .alias "in0", 0 0, v0x2850040_0; +v0x284fa50_0 .alias "in1", 0 0, v0x2850510_0; +v0x284faf0_0 .net "nS", 0 0, L_0x2abe0a0; 1 drivers +v0x284fba0_0 .net "out0", 0 0, L_0x2abe160; 1 drivers +v0x284fc40_0 .net "out1", 0 0, L_0x2abe6a0; 1 drivers +v0x284fd20_0 .alias "outfinal", 0 0, v0x28500f0_0; +S_0x284e420 .scope generate, "addbits[19]" "addbits[19]" 3 283, 3 283, S_0x2840e20; + .timescale -9 -12; +P_0x284de38 .param/l "i" 3 283, +C4<010011>; +S_0x284e590 .scope module, "attempt" "MiddleAddSubSLT" 3 285, 3 189, S_0x284e420; + .timescale -9 -12; +L_0x2abe620/d .functor NOT 1, L_0x2abf990, C4<0>, C4<0>, C4<0>; +L_0x2abe620 .delay (10000,10000,10000) L_0x2abe620/d; +L_0x2abfe30/d .functor NOT 1, L_0x2abfed0, C4<0>, C4<0>, C4<0>; +L_0x2abfe30 .delay (10000,10000,10000) L_0x2abfe30/d; +L_0x2abff70/d .functor AND 1, L_0x2ac00b0, L_0x2abfe30, C4<1>, C4<1>; +L_0x2abff70 .delay (20000,20000,20000) L_0x2abff70/d; +L_0x2ac0150/d .functor XOR 1, L_0x2abf8f0, L_0x2abfc00, C4<0>, C4<0>; +L_0x2ac0150 .delay (40000,40000,40000) L_0x2ac0150/d; +L_0x2ac0240/d .functor XOR 1, L_0x2ac0150, L_0x2abfac0, C4<0>, C4<0>; +L_0x2ac0240 .delay (40000,40000,40000) L_0x2ac0240/d; +L_0x2ac0330/d .functor AND 1, L_0x2abf8f0, L_0x2abfc00, C4<1>, C4<1>; +L_0x2ac0330 .delay (20000,20000,20000) L_0x2ac0330/d; +L_0x2ac04a0/d .functor AND 1, L_0x2ac0150, L_0x2abfac0, C4<1>, C4<1>; +L_0x2ac04a0 .delay (20000,20000,20000) L_0x2ac04a0/d; +L_0x2ac0590/d .functor OR 1, L_0x2ac0330, L_0x2ac04a0, C4<0>, C4<0>; +L_0x2ac0590 .delay (20000,20000,20000) L_0x2ac0590/d; +v0x284ec20_0 .net "A", 0 0, L_0x2abf8f0; 1 drivers +v0x284ece0_0 .net "AandB", 0 0, L_0x2ac0330; 1 drivers +v0x284ed80_0 .net "AddSubSLTSum", 0 0, L_0x2ac0240; 1 drivers +v0x284ee20_0 .net "AxorB", 0 0, L_0x2ac0150; 1 drivers +v0x284eea0_0 .net "B", 0 0, L_0x2abf990; 1 drivers +v0x284ef50_0 .net "BornB", 0 0, L_0x2abfc00; 1 drivers +v0x284f010_0 .net "CINandAxorB", 0 0, L_0x2ac04a0; 1 drivers +v0x284f090_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x284f110_0 .net *"_s3", 0 0, L_0x2abfed0; 1 drivers +v0x284f190_0 .net *"_s5", 0 0, L_0x2ac00b0; 1 drivers +v0x284f230_0 .net "carryin", 0 0, L_0x2abfac0; 1 drivers +v0x284f2d0_0 .net "carryout", 0 0, L_0x2ac0590; 1 drivers +v0x284f370_0 .net "nB", 0 0, L_0x2abe620; 1 drivers +v0x284f420_0 .net "nCmd2", 0 0, L_0x2abfe30; 1 drivers +v0x284f520_0 .net "subtract", 0 0, L_0x2abff70; 1 drivers +L_0x2abfd90 .part v0x2960210_0, 0, 1; +L_0x2abfed0 .part v0x2960210_0, 2, 1; +L_0x2ac00b0 .part v0x2960210_0, 0, 1; +S_0x284e680 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x284e590; + .timescale -9 -12; +L_0x2abf4e0/d .functor NOT 1, L_0x2abfd90, C4<0>, C4<0>, C4<0>; +L_0x2abf4e0 .delay (10000,10000,10000) L_0x2abf4e0/d; +L_0x2abf5a0/d .functor AND 1, L_0x2abf990, L_0x2abf4e0, C4<1>, C4<1>; +L_0x2abf5a0 .delay (20000,20000,20000) L_0x2abf5a0/d; +L_0x2abf6b0/d .functor AND 1, L_0x2abe620, L_0x2abfd90, C4<1>, C4<1>; +L_0x2abf6b0 .delay (20000,20000,20000) L_0x2abf6b0/d; +L_0x2abfc00/d .functor OR 1, L_0x2abf5a0, L_0x2abf6b0, C4<0>, C4<0>; +L_0x2abfc00 .delay (20000,20000,20000) L_0x2abfc00/d; +v0x284e770_0 .net "S", 0 0, L_0x2abfd90; 1 drivers +v0x284e810_0 .alias "in0", 0 0, v0x284eea0_0; +v0x284e8b0_0 .alias "in1", 0 0, v0x284f370_0; +v0x284e950_0 .net "nS", 0 0, L_0x2abf4e0; 1 drivers +v0x284ea00_0 .net "out0", 0 0, L_0x2abf5a0; 1 drivers +v0x284eaa0_0 .net "out1", 0 0, L_0x2abf6b0; 1 drivers +v0x284eb80_0 .alias "outfinal", 0 0, v0x284ef50_0; +S_0x284d280 .scope generate, "addbits[20]" "addbits[20]" 3 283, 3 283, S_0x2840e20; + .timescale -9 -12; +P_0x284cc98 .param/l "i" 3 283, +C4<010100>; +S_0x284d3f0 .scope module, "attempt" "MiddleAddSubSLT" 3 285, 3 189, S_0x284d280; + .timescale -9 -12; +L_0x2ac0c50/d .functor NOT 1, L_0x2ac0a40, C4<0>, C4<0>, C4<0>; +L_0x2ac0c50 .delay (10000,10000,10000) L_0x2ac0c50/d; +L_0x2ac1200/d .functor NOT 1, L_0x2ac12a0, C4<0>, C4<0>, C4<0>; +L_0x2ac1200 .delay (10000,10000,10000) L_0x2ac1200/d; +L_0x2ac1340/d .functor AND 1, L_0x2ac1480, L_0x2ac1200, C4<1>, C4<1>; +L_0x2ac1340 .delay (20000,20000,20000) L_0x2ac1340/d; +L_0x2ac1520/d .functor XOR 1, L_0x2ac09a0, L_0x2ac0fd0, C4<0>, C4<0>; +L_0x2ac1520 .delay (40000,40000,40000) L_0x2ac1520/d; +L_0x2ac1610/d .functor XOR 1, L_0x2ac1520, L_0x2ac0b70, C4<0>, C4<0>; +L_0x2ac1610 .delay (40000,40000,40000) L_0x2ac1610/d; +L_0x2ac1700/d .functor AND 1, L_0x2ac09a0, L_0x2ac0fd0, C4<1>, C4<1>; +L_0x2ac1700 .delay (20000,20000,20000) L_0x2ac1700/d; +L_0x2ac1870/d .functor AND 1, L_0x2ac1520, L_0x2ac0b70, C4<1>, C4<1>; +L_0x2ac1870 .delay (20000,20000,20000) L_0x2ac1870/d; +L_0x2ac1960/d .functor OR 1, L_0x2ac1700, L_0x2ac1870, C4<0>, C4<0>; +L_0x2ac1960 .delay (20000,20000,20000) L_0x2ac1960/d; +v0x284da80_0 .net "A", 0 0, L_0x2ac09a0; 1 drivers +v0x284db40_0 .net "AandB", 0 0, L_0x2ac1700; 1 drivers +v0x284dbe0_0 .net "AddSubSLTSum", 0 0, L_0x2ac1610; 1 drivers +v0x284dc80_0 .net "AxorB", 0 0, L_0x2ac1520; 1 drivers +v0x284dd00_0 .net "B", 0 0, L_0x2ac0a40; 1 drivers +v0x284ddb0_0 .net "BornB", 0 0, L_0x2ac0fd0; 1 drivers +v0x284de70_0 .net "CINandAxorB", 0 0, L_0x2ac1870; 1 drivers +v0x284def0_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x284df70_0 .net *"_s3", 0 0, L_0x2ac12a0; 1 drivers +v0x284dff0_0 .net *"_s5", 0 0, L_0x2ac1480; 1 drivers +v0x284e090_0 .net "carryin", 0 0, L_0x2ac0b70; 1 drivers +v0x284e130_0 .net "carryout", 0 0, L_0x2ac1960; 1 drivers +v0x284e1d0_0 .net "nB", 0 0, L_0x2ac0c50; 1 drivers +v0x284e280_0 .net "nCmd2", 0 0, L_0x2ac1200; 1 drivers +v0x284e380_0 .net "subtract", 0 0, L_0x2ac1340; 1 drivers +L_0x2ac1160 .part v0x2960210_0, 0, 1; +L_0x2ac12a0 .part v0x2960210_0, 2, 1; +L_0x2ac1480 .part v0x2960210_0, 0, 1; +S_0x284d4e0 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x284d3f0; + .timescale -9 -12; +L_0x2ac0d50/d .functor NOT 1, L_0x2ac1160, C4<0>, C4<0>, C4<0>; +L_0x2ac0d50 .delay (10000,10000,10000) L_0x2ac0d50/d; +L_0x2ac0df0/d .functor AND 1, L_0x2ac0a40, L_0x2ac0d50, C4<1>, C4<1>; +L_0x2ac0df0 .delay (20000,20000,20000) L_0x2ac0df0/d; +L_0x2ac0ee0/d .functor AND 1, L_0x2ac0c50, L_0x2ac1160, C4<1>, C4<1>; +L_0x2ac0ee0 .delay (20000,20000,20000) L_0x2ac0ee0/d; +L_0x2ac0fd0/d .functor OR 1, L_0x2ac0df0, L_0x2ac0ee0, C4<0>, C4<0>; +L_0x2ac0fd0 .delay (20000,20000,20000) L_0x2ac0fd0/d; +v0x284d5d0_0 .net "S", 0 0, L_0x2ac1160; 1 drivers +v0x284d670_0 .alias "in0", 0 0, v0x284dd00_0; +v0x284d710_0 .alias "in1", 0 0, v0x284e1d0_0; +v0x284d7b0_0 .net "nS", 0 0, L_0x2ac0d50; 1 drivers +v0x284d860_0 .net "out0", 0 0, L_0x2ac0df0; 1 drivers +v0x284d900_0 .net "out1", 0 0, L_0x2ac0ee0; 1 drivers +v0x284d9e0_0 .alias "outfinal", 0 0, v0x284ddb0_0; +S_0x284c0e0 .scope generate, "addbits[21]" "addbits[21]" 3 283, 3 283, S_0x2840e20; + .timescale -9 -12; +P_0x284baf8 .param/l "i" 3 283, +C4<010101>; +S_0x284c250 .scope module, "attempt" "MiddleAddSubSLT" 3 285, 3 189, S_0x284c0e0; + .timescale -9 -12; +L_0x2ac2050/d .functor NOT 1, L_0x2ac1e10, C4<0>, C4<0>, C4<0>; +L_0x2ac2050 .delay (10000,10000,10000) L_0x2ac2050/d; +L_0x2ac25c0/d .functor NOT 1, L_0x2ac2660, C4<0>, C4<0>, C4<0>; +L_0x2ac25c0 .delay (10000,10000,10000) L_0x2ac25c0/d; +L_0x2ac2700/d .functor AND 1, L_0x2ac2840, L_0x2ac25c0, C4<1>, C4<1>; +L_0x2ac2700 .delay (20000,20000,20000) L_0x2ac2700/d; +L_0x2ac28e0/d .functor XOR 1, L_0x2ac1d70, L_0x2ac2390, C4<0>, C4<0>; +L_0x2ac28e0 .delay (40000,40000,40000) L_0x2ac28e0/d; +L_0x2ac29d0/d .functor XOR 1, L_0x2ac28e0, L_0x2ac1f40, C4<0>, C4<0>; +L_0x2ac29d0 .delay (40000,40000,40000) L_0x2ac29d0/d; +L_0x2ac2ac0/d .functor AND 1, L_0x2ac1d70, L_0x2ac2390, C4<1>, C4<1>; +L_0x2ac2ac0 .delay (20000,20000,20000) L_0x2ac2ac0/d; +L_0x2ac2c30/d .functor AND 1, L_0x2ac28e0, L_0x2ac1f40, C4<1>, C4<1>; +L_0x2ac2c30 .delay (20000,20000,20000) L_0x2ac2c30/d; +L_0x2ac2d20/d .functor OR 1, L_0x2ac2ac0, L_0x2ac2c30, C4<0>, C4<0>; +L_0x2ac2d20 .delay (20000,20000,20000) L_0x2ac2d20/d; +v0x284c8e0_0 .net "A", 0 0, L_0x2ac1d70; 1 drivers +v0x284c9a0_0 .net "AandB", 0 0, L_0x2ac2ac0; 1 drivers +v0x284ca40_0 .net "AddSubSLTSum", 0 0, L_0x2ac29d0; 1 drivers +v0x284cae0_0 .net "AxorB", 0 0, L_0x2ac28e0; 1 drivers +v0x284cb60_0 .net "B", 0 0, L_0x2ac1e10; 1 drivers +v0x284cc10_0 .net "BornB", 0 0, L_0x2ac2390; 1 drivers +v0x284ccd0_0 .net "CINandAxorB", 0 0, L_0x2ac2c30; 1 drivers +v0x284cd50_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x284cdd0_0 .net *"_s3", 0 0, L_0x2ac2660; 1 drivers +v0x284ce50_0 .net *"_s5", 0 0, L_0x2ac2840; 1 drivers +v0x284cef0_0 .net "carryin", 0 0, L_0x2ac1f40; 1 drivers +v0x284cf90_0 .net "carryout", 0 0, L_0x2ac2d20; 1 drivers +v0x284d030_0 .net "nB", 0 0, L_0x2ac2050; 1 drivers +v0x284d0e0_0 .net "nCmd2", 0 0, L_0x2ac25c0; 1 drivers +v0x284d1e0_0 .net "subtract", 0 0, L_0x2ac2700; 1 drivers +L_0x2ac2520 .part v0x2960210_0, 0, 1; +L_0x2ac2660 .part v0x2960210_0, 2, 1; +L_0x2ac2840 .part v0x2960210_0, 0, 1; +S_0x284c340 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x284c250; + .timescale -9 -12; +L_0x2ac2150/d .functor NOT 1, L_0x2ac2520, C4<0>, C4<0>, C4<0>; +L_0x2ac2150 .delay (10000,10000,10000) L_0x2ac2150/d; +L_0x2ac21b0/d .functor AND 1, L_0x2ac1e10, L_0x2ac2150, C4<1>, C4<1>; +L_0x2ac21b0 .delay (20000,20000,20000) L_0x2ac21b0/d; +L_0x2ac22a0/d .functor AND 1, L_0x2ac2050, L_0x2ac2520, C4<1>, C4<1>; +L_0x2ac22a0 .delay (20000,20000,20000) L_0x2ac22a0/d; +L_0x2ac2390/d .functor OR 1, L_0x2ac21b0, L_0x2ac22a0, C4<0>, C4<0>; +L_0x2ac2390 .delay (20000,20000,20000) L_0x2ac2390/d; +v0x284c430_0 .net "S", 0 0, L_0x2ac2520; 1 drivers +v0x284c4d0_0 .alias "in0", 0 0, v0x284cb60_0; +v0x284c570_0 .alias "in1", 0 0, v0x284d030_0; +v0x284c610_0 .net "nS", 0 0, L_0x2ac2150; 1 drivers +v0x284c6c0_0 .net "out0", 0 0, L_0x2ac21b0; 1 drivers +v0x284c760_0 .net "out1", 0 0, L_0x2ac22a0; 1 drivers +v0x284c840_0 .alias "outfinal", 0 0, v0x284cc10_0; +S_0x284af40 .scope generate, "addbits[22]" "addbits[22]" 3 283, 3 283, S_0x2840e20; + .timescale -9 -12; +P_0x284a958 .param/l "i" 3 283, +C4<010110>; +S_0x284b0b0 .scope module, "attempt" "MiddleAddSubSLT" 3 285, 3 189, S_0x284af40; + .timescale -9 -12; +L_0x2ac1fe0/d .functor NOT 1, L_0x2ac31d0, C4<0>, C4<0>, C4<0>; +L_0x2ac1fe0 .delay (10000,10000,10000) L_0x2ac1fe0/d; +L_0x2ac3a90/d .functor NOT 1, L_0x2ac3b50, C4<0>, C4<0>, C4<0>; +L_0x2ac3a90 .delay (10000,10000,10000) L_0x2ac3a90/d; +L_0x2ac3bf0/d .functor AND 1, L_0x2ac3d30, L_0x2ac3a90, C4<1>, C4<1>; +L_0x2ac3bf0 .delay (20000,20000,20000) L_0x2ac3bf0/d; +L_0x2ac3dd0/d .functor XOR 1, L_0x2ac3130, L_0x2ac3820, C4<0>, C4<0>; +L_0x2ac3dd0 .delay (40000,40000,40000) L_0x2ac3dd0/d; +L_0x2ac3ec0/d .functor XOR 1, L_0x2ac3dd0, L_0x2ac3300, C4<0>, C4<0>; +L_0x2ac3ec0 .delay (40000,40000,40000) L_0x2ac3ec0/d; +L_0x2ac3fb0/d .functor AND 1, L_0x2ac3130, L_0x2ac3820, C4<1>, C4<1>; +L_0x2ac3fb0 .delay (20000,20000,20000) L_0x2ac3fb0/d; +L_0x2ac4120/d .functor AND 1, L_0x2ac3dd0, L_0x2ac3300, C4<1>, C4<1>; +L_0x2ac4120 .delay (20000,20000,20000) L_0x2ac4120/d; +L_0x2ac4210/d .functor OR 1, L_0x2ac3fb0, L_0x2ac4120, C4<0>, C4<0>; +L_0x2ac4210 .delay (20000,20000,20000) L_0x2ac4210/d; +v0x284b740_0 .net "A", 0 0, L_0x2ac3130; 1 drivers +v0x284b800_0 .net "AandB", 0 0, L_0x2ac3fb0; 1 drivers +v0x284b8a0_0 .net "AddSubSLTSum", 0 0, L_0x2ac3ec0; 1 drivers +v0x284b940_0 .net "AxorB", 0 0, L_0x2ac3dd0; 1 drivers +v0x284b9c0_0 .net "B", 0 0, L_0x2ac31d0; 1 drivers +v0x284ba70_0 .net "BornB", 0 0, L_0x2ac3820; 1 drivers +v0x284bb30_0 .net "CINandAxorB", 0 0, L_0x2ac4120; 1 drivers +v0x284bbb0_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x284bc30_0 .net *"_s3", 0 0, L_0x2ac3b50; 1 drivers +v0x284bcb0_0 .net *"_s5", 0 0, L_0x2ac3d30; 1 drivers +v0x284bd50_0 .net "carryin", 0 0, L_0x2ac3300; 1 drivers +v0x284bdf0_0 .net "carryout", 0 0, L_0x2ac4210; 1 drivers +v0x284be90_0 .net "nB", 0 0, L_0x2ac1fe0; 1 drivers +v0x284bf40_0 .net "nCmd2", 0 0, L_0x2ac3a90; 1 drivers +v0x284c040_0 .net "subtract", 0 0, L_0x2ac3bf0; 1 drivers +L_0x2ac39f0 .part v0x2960210_0, 0, 1; +L_0x2ac3b50 .part v0x2960210_0, 2, 1; +L_0x2ac3d30 .part v0x2960210_0, 0, 1; +S_0x284b1a0 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x284b0b0; + .timescale -9 -12; +L_0x2ac3540/d .functor NOT 1, L_0x2ac39f0, C4<0>, C4<0>, C4<0>; +L_0x2ac3540 .delay (10000,10000,10000) L_0x2ac3540/d; +L_0x2ac3600/d .functor AND 1, L_0x2ac31d0, L_0x2ac3540, C4<1>, C4<1>; +L_0x2ac3600 .delay (20000,20000,20000) L_0x2ac3600/d; +L_0x2ac3710/d .functor AND 1, L_0x2ac1fe0, L_0x2ac39f0, C4<1>, C4<1>; +L_0x2ac3710 .delay (20000,20000,20000) L_0x2ac3710/d; +L_0x2ac3820/d .functor OR 1, L_0x2ac3600, L_0x2ac3710, C4<0>, C4<0>; +L_0x2ac3820 .delay (20000,20000,20000) L_0x2ac3820/d; +v0x284b290_0 .net "S", 0 0, L_0x2ac39f0; 1 drivers +v0x284b330_0 .alias "in0", 0 0, v0x284b9c0_0; +v0x284b3d0_0 .alias "in1", 0 0, v0x284be90_0; +v0x284b470_0 .net "nS", 0 0, L_0x2ac3540; 1 drivers +v0x284b520_0 .net "out0", 0 0, L_0x2ac3600; 1 drivers +v0x284b5c0_0 .net "out1", 0 0, L_0x2ac3710; 1 drivers +v0x284b6a0_0 .alias "outfinal", 0 0, v0x284ba70_0; +S_0x2849dd0 .scope generate, "addbits[23]" "addbits[23]" 3 283, 3 283, S_0x2840e20; + .timescale -9 -12; +P_0x28496a8 .param/l "i" 3 283, +C4<010111>; +S_0x2849f40 .scope module, "attempt" "MiddleAddSubSLT" 3 285, 3 189, S_0x2849dd0; + .timescale -9 -12; +L_0x2ac33a0/d .functor NOT 1, L_0x2ac46e0, C4<0>, C4<0>, C4<0>; +L_0x2ac33a0 .delay (10000,10000,10000) L_0x2ac33a0/d; +L_0x2ac4e90/d .functor NOT 1, L_0x2ac4f30, C4<0>, C4<0>, C4<0>; +L_0x2ac4e90 .delay (10000,10000,10000) L_0x2ac4e90/d; +L_0x2ac4fd0/d .functor AND 1, L_0x2ac5110, L_0x2ac4e90, C4<1>, C4<1>; +L_0x2ac4fd0 .delay (20000,20000,20000) L_0x2ac4fd0/d; +L_0x2ac51b0/d .functor XOR 1, L_0x2ac4640, L_0x2ac4c60, C4<0>, C4<0>; +L_0x2ac51b0 .delay (40000,40000,40000) L_0x2ac51b0/d; +L_0x2ac52a0/d .functor XOR 1, L_0x2ac51b0, L_0x2ac4810, C4<0>, C4<0>; +L_0x2ac52a0 .delay (40000,40000,40000) L_0x2ac52a0/d; +L_0x2ac5390/d .functor AND 1, L_0x2ac4640, L_0x2ac4c60, C4<1>, C4<1>; +L_0x2ac5390 .delay (20000,20000,20000) L_0x2ac5390/d; +L_0x2ac5500/d .functor AND 1, L_0x2ac51b0, L_0x2ac4810, C4<1>, C4<1>; +L_0x2ac5500 .delay (20000,20000,20000) L_0x2ac5500/d; +L_0x2ac55f0/d .functor OR 1, L_0x2ac5390, L_0x2ac5500, C4<0>, C4<0>; +L_0x2ac55f0 .delay (20000,20000,20000) L_0x2ac55f0/d; +v0x284a5a0_0 .net "A", 0 0, L_0x2ac4640; 1 drivers +v0x284a660_0 .net "AandB", 0 0, L_0x2ac5390; 1 drivers +v0x284a700_0 .net "AddSubSLTSum", 0 0, L_0x2ac52a0; 1 drivers +v0x284a7a0_0 .net "AxorB", 0 0, L_0x2ac51b0; 1 drivers +v0x284a820_0 .net "B", 0 0, L_0x2ac46e0; 1 drivers +v0x284a8d0_0 .net "BornB", 0 0, L_0x2ac4c60; 1 drivers +v0x284a990_0 .net "CINandAxorB", 0 0, L_0x2ac5500; 1 drivers +v0x284aa10_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x284aa90_0 .net *"_s3", 0 0, L_0x2ac4f30; 1 drivers +v0x284ab10_0 .net *"_s5", 0 0, L_0x2ac5110; 1 drivers +v0x284abb0_0 .net "carryin", 0 0, L_0x2ac4810; 1 drivers +v0x284ac50_0 .net "carryout", 0 0, L_0x2ac55f0; 1 drivers +v0x284acf0_0 .net "nB", 0 0, L_0x2ac33a0; 1 drivers +v0x284ada0_0 .net "nCmd2", 0 0, L_0x2ac4e90; 1 drivers +v0x284aea0_0 .net "subtract", 0 0, L_0x2ac4fd0; 1 drivers +L_0x2ac4df0 .part v0x2960210_0, 0, 1; +L_0x2ac4f30 .part v0x2960210_0, 2, 1; +L_0x2ac5110 .part v0x2960210_0, 0, 1; +S_0x284a030 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x2849f40; + .timescale -9 -12; +L_0x2ac4a20/d .functor NOT 1, L_0x2ac4df0, C4<0>, C4<0>, C4<0>; +L_0x2ac4a20 .delay (10000,10000,10000) L_0x2ac4a20/d; +L_0x2ac4a80/d .functor AND 1, L_0x2ac46e0, L_0x2ac4a20, C4<1>, C4<1>; +L_0x2ac4a80 .delay (20000,20000,20000) L_0x2ac4a80/d; +L_0x2ac4b70/d .functor AND 1, L_0x2ac33a0, L_0x2ac4df0, C4<1>, C4<1>; +L_0x2ac4b70 .delay (20000,20000,20000) L_0x2ac4b70/d; +L_0x2ac4c60/d .functor OR 1, L_0x2ac4a80, L_0x2ac4b70, C4<0>, C4<0>; +L_0x2ac4c60 .delay (20000,20000,20000) L_0x2ac4c60/d; +v0x284a120_0 .net "S", 0 0, L_0x2ac4df0; 1 drivers +v0x284a1c0_0 .alias "in0", 0 0, v0x284a820_0; +v0x284a260_0 .alias "in1", 0 0, v0x284acf0_0; +v0x284a300_0 .net "nS", 0 0, L_0x2ac4a20; 1 drivers +v0x284a380_0 .net "out0", 0 0, L_0x2ac4a80; 1 drivers +v0x284a420_0 .net "out1", 0 0, L_0x2ac4b70; 1 drivers +v0x284a500_0 .alias "outfinal", 0 0, v0x284a8d0_0; +S_0x2848be0 .scope generate, "addbits[24]" "addbits[24]" 3 283, 3 283, S_0x2840e20; + .timescale -9 -12; +P_0x28485f8 .param/l "i" 3 283, +C4<011000>; +S_0x2848d50 .scope module, "attempt" "MiddleAddSubSLT" 3 285, 3 189, S_0x2848be0; + .timescale -9 -12; +L_0x2ac48b0/d .functor NOT 1, L_0x2ac5aa0, C4<0>, C4<0>, C4<0>; +L_0x2ac48b0 .delay (10000,10000,10000) L_0x2ac48b0/d; +L_0x2ac6270/d .functor NOT 1, L_0x2ac6330, C4<0>, C4<0>, C4<0>; +L_0x2ac6270 .delay (10000,10000,10000) L_0x2ac6270/d; +L_0x2ac63d0/d .functor AND 1, L_0x2ac6510, L_0x2ac6270, C4<1>, C4<1>; +L_0x2ac63d0 .delay (20000,20000,20000) L_0x2ac63d0/d; +L_0x2ac65b0/d .functor XOR 1, L_0x2ac5a00, L_0x2ac6040, C4<0>, C4<0>; +L_0x2ac65b0 .delay (40000,40000,40000) L_0x2ac65b0/d; +L_0x2ac66a0/d .functor XOR 1, L_0x2ac65b0, L_0x2ac5bd0, C4<0>, C4<0>; +L_0x2ac66a0 .delay (40000,40000,40000) L_0x2ac66a0/d; +L_0x2ac6790/d .functor AND 1, L_0x2ac5a00, L_0x2ac6040, C4<1>, C4<1>; +L_0x2ac6790 .delay (20000,20000,20000) L_0x2ac6790/d; +L_0x2ac6900/d .functor AND 1, L_0x2ac65b0, L_0x2ac5bd0, C4<1>, C4<1>; +L_0x2ac6900 .delay (20000,20000,20000) L_0x2ac6900/d; +L_0x2ac6a10/d .functor OR 1, L_0x2ac6790, L_0x2ac6900, C4<0>, C4<0>; +L_0x2ac6a10 .delay (20000,20000,20000) L_0x2ac6a10/d; +v0x28492f0_0 .net "A", 0 0, L_0x2ac5a00; 1 drivers +v0x28493b0_0 .net "AandB", 0 0, L_0x2ac6790; 1 drivers +v0x2849450_0 .net "AddSubSLTSum", 0 0, L_0x2ac66a0; 1 drivers +v0x28494f0_0 .net "AxorB", 0 0, L_0x2ac65b0; 1 drivers +v0x2849570_0 .net "B", 0 0, L_0x2ac5aa0; 1 drivers +v0x2849620_0 .net "BornB", 0 0, L_0x2ac6040; 1 drivers +v0x28496e0_0 .net "CINandAxorB", 0 0, L_0x2ac6900; 1 drivers +v0x2849760_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x2849830_0 .net *"_s3", 0 0, L_0x2ac6330; 1 drivers +v0x28498b0_0 .net *"_s5", 0 0, L_0x2ac6510; 1 drivers +v0x28499b0_0 .net "carryin", 0 0, L_0x2ac5bd0; 1 drivers +v0x2849a50_0 .net "carryout", 0 0, L_0x2ac6a10; 1 drivers +v0x2849b60_0 .net "nB", 0 0, L_0x2ac48b0; 1 drivers +v0x2849c10_0 .net "nCmd2", 0 0, L_0x2ac6270; 1 drivers +v0x2849d30_0 .net "subtract", 0 0, L_0x2ac63d0; 1 drivers +L_0x2ac61d0 .part v0x2960210_0, 0, 1; +L_0x2ac6330 .part v0x2960210_0, 2, 1; +L_0x2ac6510 .part v0x2960210_0, 0, 1; +S_0x2848e40 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x2848d50; + .timescale -9 -12; +L_0x2ac5dc0/d .functor NOT 1, L_0x2ac61d0, C4<0>, C4<0>, C4<0>; +L_0x2ac5dc0 .delay (10000,10000,10000) L_0x2ac5dc0/d; +L_0x2ac5e60/d .functor AND 1, L_0x2ac5aa0, L_0x2ac5dc0, C4<1>, C4<1>; +L_0x2ac5e60 .delay (20000,20000,20000) L_0x2ac5e60/d; +L_0x2ac5f50/d .functor AND 1, L_0x2ac48b0, L_0x2ac61d0, C4<1>, C4<1>; +L_0x2ac5f50 .delay (20000,20000,20000) L_0x2ac5f50/d; +L_0x2ac6040/d .functor OR 1, L_0x2ac5e60, L_0x2ac5f50, C4<0>, C4<0>; +L_0x2ac6040 .delay (20000,20000,20000) L_0x2ac6040/d; +v0x2848f30_0 .net "S", 0 0, L_0x2ac61d0; 1 drivers +v0x2848fd0_0 .alias "in0", 0 0, v0x2849570_0; +v0x2849050_0 .alias "in1", 0 0, v0x2849b60_0; +v0x28490d0_0 .net "nS", 0 0, L_0x2ac5dc0; 1 drivers +v0x2849150_0 .net "out0", 0 0, L_0x2ac5e60; 1 drivers +v0x28491d0_0 .net "out1", 0 0, L_0x2ac5f50; 1 drivers +v0x2849250_0 .alias "outfinal", 0 0, v0x2849620_0; +S_0x2847a40 .scope generate, "addbits[25]" "addbits[25]" 3 283, 3 283, S_0x2840e20; + .timescale -9 -12; +P_0x2847458 .param/l "i" 3 283, +C4<011001>; +S_0x2847bb0 .scope module, "attempt" "MiddleAddSubSLT" 3 285, 3 189, S_0x2847a40; + .timescale -9 -12; +L_0x2841da0/d .functor NOT 1, L_0x29c6dc0, C4<0>, C4<0>, C4<0>; +L_0x2841da0 .delay (10000,10000,10000) L_0x2841da0/d; +L_0x2ac6ef0/d .functor NOT 1, L_0x2ac6fb0, C4<0>, C4<0>, C4<0>; +L_0x2ac6ef0 .delay (10000,10000,10000) L_0x2ac6ef0/d; +L_0x2ac7050/d .functor AND 1, L_0x2ac81d0, L_0x2ac6ef0, C4<1>, C4<1>; +L_0x2ac7050 .delay (20000,20000,20000) L_0x2ac7050/d; +L_0x2ac8270/d .functor XOR 1, L_0x29c6d20, L_0x29c7360, C4<0>, C4<0>; +L_0x2ac8270 .delay (40000,40000,40000) L_0x2ac8270/d; +L_0x2ac8360/d .functor XOR 1, L_0x2ac8270, L_0x29c6ef0, C4<0>, C4<0>; +L_0x2ac8360 .delay (40000,40000,40000) L_0x2ac8360/d; +L_0x2ac8450/d .functor AND 1, L_0x29c6d20, L_0x29c7360, C4<1>, C4<1>; +L_0x2ac8450 .delay (20000,20000,20000) L_0x2ac8450/d; +L_0x2ac85c0/d .functor AND 1, L_0x2ac8270, L_0x29c6ef0, C4<1>, C4<1>; +L_0x2ac85c0 .delay (20000,20000,20000) L_0x2ac85c0/d; +L_0x2ac86d0/d .functor OR 1, L_0x2ac8450, L_0x2ac85c0, C4<0>, C4<0>; +L_0x2ac86d0 .delay (20000,20000,20000) L_0x2ac86d0/d; +v0x2848240_0 .net "A", 0 0, L_0x29c6d20; 1 drivers +v0x2848300_0 .net "AandB", 0 0, L_0x2ac8450; 1 drivers +v0x28483a0_0 .net "AddSubSLTSum", 0 0, L_0x2ac8360; 1 drivers +v0x2848440_0 .net "AxorB", 0 0, L_0x2ac8270; 1 drivers +v0x28484c0_0 .net "B", 0 0, L_0x29c6dc0; 1 drivers +v0x2848570_0 .net "BornB", 0 0, L_0x29c7360; 1 drivers +v0x2848630_0 .net "CINandAxorB", 0 0, L_0x2ac85c0; 1 drivers +v0x28486b0_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x2848730_0 .net *"_s3", 0 0, L_0x2ac6fb0; 1 drivers +v0x28487b0_0 .net *"_s5", 0 0, L_0x2ac81d0; 1 drivers +v0x2848850_0 .net "carryin", 0 0, L_0x29c6ef0; 1 drivers +v0x28488f0_0 .net "carryout", 0 0, L_0x2ac86d0; 1 drivers +v0x2848990_0 .net "nB", 0 0, L_0x2841da0; 1 drivers +v0x2848a40_0 .net "nCmd2", 0 0, L_0x2ac6ef0; 1 drivers +v0x2848b40_0 .net "subtract", 0 0, L_0x2ac7050; 1 drivers +L_0x2ac6e50 .part v0x2960210_0, 0, 1; +L_0x2ac6fb0 .part v0x2960210_0, 2, 1; +L_0x2ac81d0 .part v0x2960210_0, 0, 1; +S_0x2847ca0 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x2847bb0; + .timescale -9 -12; +L_0x29c70c0/d .functor NOT 1, L_0x2ac6e50, C4<0>, C4<0>, C4<0>; +L_0x29c70c0 .delay (10000,10000,10000) L_0x29c70c0/d; +L_0x29c7140/d .functor AND 1, L_0x29c6dc0, L_0x29c70c0, C4<1>, C4<1>; +L_0x29c7140 .delay (20000,20000,20000) L_0x29c7140/d; +L_0x29c7250/d .functor AND 1, L_0x2841da0, L_0x2ac6e50, C4<1>, C4<1>; +L_0x29c7250 .delay (20000,20000,20000) L_0x29c7250/d; +L_0x29c7360/d .functor OR 1, L_0x29c7140, L_0x29c7250, C4<0>, C4<0>; +L_0x29c7360 .delay (20000,20000,20000) L_0x29c7360/d; +v0x2847d90_0 .net "S", 0 0, L_0x2ac6e50; 1 drivers +v0x2847e30_0 .alias "in0", 0 0, v0x28484c0_0; +v0x2847ed0_0 .alias "in1", 0 0, v0x2848990_0; +v0x2847f70_0 .net "nS", 0 0, L_0x29c70c0; 1 drivers +v0x2848020_0 .net "out0", 0 0, L_0x29c7140; 1 drivers +v0x28480c0_0 .net "out1", 0 0, L_0x29c7250; 1 drivers +v0x28481a0_0 .alias "outfinal", 0 0, v0x2848570_0; +S_0x28468a0 .scope generate, "addbits[26]" "addbits[26]" 3 283, 3 283, S_0x2840e20; + .timescale -9 -12; +P_0x28462b8 .param/l "i" 3 283, +C4<011010>; +S_0x2846a10 .scope module, "attempt" "MiddleAddSubSLT" 3 285, 3 189, S_0x28468a0; + .timescale -9 -12; +L_0x29c6f90/d .functor NOT 1, L_0x2ac8ba0, C4<0>, C4<0>, C4<0>; +L_0x29c6f90 .delay (10000,10000,10000) L_0x29c6f90/d; +L_0x2ac93b0/d .functor NOT 1, L_0x2ac9470, C4<0>, C4<0>, C4<0>; +L_0x2ac93b0 .delay (10000,10000,10000) L_0x2ac93b0/d; +L_0x2ac9510/d .functor AND 1, L_0x2ac9650, L_0x2ac93b0, C4<1>, C4<1>; +L_0x2ac9510 .delay (20000,20000,20000) L_0x2ac9510/d; +L_0x2ac96f0/d .functor XOR 1, L_0x2ac8b00, L_0x2ac9140, C4<0>, C4<0>; +L_0x2ac96f0 .delay (40000,40000,40000) L_0x2ac96f0/d; +L_0x2ac97e0/d .functor XOR 1, L_0x2ac96f0, L_0x2ac8cd0, C4<0>, C4<0>; +L_0x2ac97e0 .delay (40000,40000,40000) L_0x2ac97e0/d; +L_0x2ac9900/d .functor AND 1, L_0x2ac8b00, L_0x2ac9140, C4<1>, C4<1>; +L_0x2ac9900 .delay (20000,20000,20000) L_0x2ac9900/d; +L_0x2ac9aa0/d .functor AND 1, L_0x2ac96f0, L_0x2ac8cd0, C4<1>, C4<1>; +L_0x2ac9aa0 .delay (20000,20000,20000) L_0x2ac9aa0/d; +L_0x2ac9bb0/d .functor OR 1, L_0x2ac9900, L_0x2ac9aa0, C4<0>, C4<0>; +L_0x2ac9bb0 .delay (20000,20000,20000) L_0x2ac9bb0/d; +v0x28470a0_0 .net "A", 0 0, L_0x2ac8b00; 1 drivers +v0x2847160_0 .net "AandB", 0 0, L_0x2ac9900; 1 drivers +v0x2847200_0 .net "AddSubSLTSum", 0 0, L_0x2ac97e0; 1 drivers +v0x28472a0_0 .net "AxorB", 0 0, L_0x2ac96f0; 1 drivers +v0x2847320_0 .net "B", 0 0, L_0x2ac8ba0; 1 drivers +v0x28473d0_0 .net "BornB", 0 0, L_0x2ac9140; 1 drivers +v0x2847490_0 .net "CINandAxorB", 0 0, L_0x2ac9aa0; 1 drivers +v0x2847510_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x2847590_0 .net *"_s3", 0 0, L_0x2ac9470; 1 drivers +v0x2847610_0 .net *"_s5", 0 0, L_0x2ac9650; 1 drivers +v0x28476b0_0 .net "carryin", 0 0, L_0x2ac8cd0; 1 drivers +v0x2847750_0 .net "carryout", 0 0, L_0x2ac9bb0; 1 drivers +v0x28477f0_0 .net "nB", 0 0, L_0x29c6f90; 1 drivers +v0x28478a0_0 .net "nCmd2", 0 0, L_0x2ac93b0; 1 drivers +v0x28479a0_0 .net "subtract", 0 0, L_0x2ac9510; 1 drivers +L_0x2ac9310 .part v0x2960210_0, 0, 1; +L_0x2ac9470 .part v0x2960210_0, 2, 1; +L_0x2ac9650 .part v0x2960210_0, 0, 1; +S_0x2846b00 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x2846a10; + .timescale -9 -12; +L_0x29c7060/d .functor NOT 1, L_0x2ac9310, C4<0>, C4<0>, C4<0>; +L_0x29c7060 .delay (10000,10000,10000) L_0x29c7060/d; +L_0x2ac8f60/d .functor AND 1, L_0x2ac8ba0, L_0x29c7060, C4<1>, C4<1>; +L_0x2ac8f60 .delay (20000,20000,20000) L_0x2ac8f60/d; +L_0x2ac9050/d .functor AND 1, L_0x29c6f90, L_0x2ac9310, C4<1>, C4<1>; +L_0x2ac9050 .delay (20000,20000,20000) L_0x2ac9050/d; +L_0x2ac9140/d .functor OR 1, L_0x2ac8f60, L_0x2ac9050, C4<0>, C4<0>; +L_0x2ac9140 .delay (20000,20000,20000) L_0x2ac9140/d; +v0x2846bf0_0 .net "S", 0 0, L_0x2ac9310; 1 drivers +v0x2846c90_0 .alias "in0", 0 0, v0x2847320_0; +v0x2846d30_0 .alias "in1", 0 0, v0x28477f0_0; +v0x2846dd0_0 .net "nS", 0 0, L_0x29c7060; 1 drivers +v0x2846e80_0 .net "out0", 0 0, L_0x2ac8f60; 1 drivers +v0x2846f20_0 .net "out1", 0 0, L_0x2ac9050; 1 drivers +v0x2847000_0 .alias "outfinal", 0 0, v0x28473d0_0; +S_0x2845700 .scope generate, "addbits[27]" "addbits[27]" 3 283, 3 283, S_0x2840e20; + .timescale -9 -12; +P_0x2845118 .param/l "i" 3 283, +C4<011011>; +S_0x2845870 .scope module, "attempt" "MiddleAddSubSLT" 3 285, 3 189, S_0x2845700; + .timescale -9 -12; +L_0x2ac8d70/d .functor NOT 1, L_0x2aca080, C4<0>, C4<0>, C4<0>; +L_0x2ac8d70 .delay (10000,10000,10000) L_0x2ac8d70/d; +L_0x2aca890/d .functor NOT 1, L_0x2aca950, C4<0>, C4<0>, C4<0>; +L_0x2aca890 .delay (10000,10000,10000) L_0x2aca890/d; +L_0x2aca9f0/d .functor AND 1, L_0x2acab30, L_0x2aca890, C4<1>, C4<1>; +L_0x2aca9f0 .delay (20000,20000,20000) L_0x2aca9f0/d; +L_0x29978a0/d .functor XOR 1, L_0x2ac9fe0, L_0x2aca620, C4<0>, C4<0>; +L_0x29978a0 .delay (40000,40000,40000) L_0x29978a0/d; +L_0x2997990/d .functor XOR 1, L_0x29978a0, L_0x2aca1b0, C4<0>, C4<0>; +L_0x2997990 .delay (40000,40000,40000) L_0x2997990/d; +L_0x2997ab0/d .functor AND 1, L_0x2ac9fe0, L_0x2aca620, C4<1>, C4<1>; +L_0x2997ab0 .delay (20000,20000,20000) L_0x2997ab0/d; +L_0x2997c50/d .functor AND 1, L_0x29978a0, L_0x2aca1b0, C4<1>, C4<1>; +L_0x2997c50 .delay (20000,20000,20000) L_0x2997c50/d; +L_0x2997d60/d .functor OR 1, L_0x2997ab0, L_0x2997c50, C4<0>, C4<0>; +L_0x2997d60 .delay (20000,20000,20000) L_0x2997d60/d; +v0x2845f00_0 .net "A", 0 0, L_0x2ac9fe0; 1 drivers +v0x2845fc0_0 .net "AandB", 0 0, L_0x2997ab0; 1 drivers +v0x2846060_0 .net "AddSubSLTSum", 0 0, L_0x2997990; 1 drivers +v0x2846100_0 .net "AxorB", 0 0, L_0x29978a0; 1 drivers +v0x2846180_0 .net "B", 0 0, L_0x2aca080; 1 drivers +v0x2846230_0 .net "BornB", 0 0, L_0x2aca620; 1 drivers +v0x28462f0_0 .net "CINandAxorB", 0 0, L_0x2997c50; 1 drivers +v0x2846370_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x28463f0_0 .net *"_s3", 0 0, L_0x2aca950; 1 drivers +v0x2846470_0 .net *"_s5", 0 0, L_0x2acab30; 1 drivers +v0x2846510_0 .net "carryin", 0 0, L_0x2aca1b0; 1 drivers +v0x28465b0_0 .net "carryout", 0 0, L_0x2997d60; 1 drivers +v0x2846650_0 .net "nB", 0 0, L_0x2ac8d70; 1 drivers +v0x2846700_0 .net "nCmd2", 0 0, L_0x2aca890; 1 drivers +v0x2846800_0 .net "subtract", 0 0, L_0x2aca9f0; 1 drivers +L_0x2aca7f0 .part v0x2960210_0, 0, 1; +L_0x2aca950 .part v0x2960210_0, 2, 1; +L_0x2acab30 .part v0x2960210_0, 0, 1; +S_0x2845960 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x2845870; + .timescale -9 -12; +L_0x2aca3e0/d .functor NOT 1, L_0x2aca7f0, C4<0>, C4<0>, C4<0>; +L_0x2aca3e0 .delay (10000,10000,10000) L_0x2aca3e0/d; +L_0x2aca440/d .functor AND 1, L_0x2aca080, L_0x2aca3e0, C4<1>, C4<1>; +L_0x2aca440 .delay (20000,20000,20000) L_0x2aca440/d; +L_0x2aca530/d .functor AND 1, L_0x2ac8d70, L_0x2aca7f0, C4<1>, C4<1>; +L_0x2aca530 .delay (20000,20000,20000) L_0x2aca530/d; +L_0x2aca620/d .functor OR 1, L_0x2aca440, L_0x2aca530, C4<0>, C4<0>; +L_0x2aca620 .delay (20000,20000,20000) L_0x2aca620/d; +v0x2845a50_0 .net "S", 0 0, L_0x2aca7f0; 1 drivers +v0x2845af0_0 .alias "in0", 0 0, v0x2846180_0; +v0x2845b90_0 .alias "in1", 0 0, v0x2846650_0; +v0x2845c30_0 .net "nS", 0 0, L_0x2aca3e0; 1 drivers +v0x2845ce0_0 .net "out0", 0 0, L_0x2aca440; 1 drivers +v0x2845d80_0 .net "out1", 0 0, L_0x2aca530; 1 drivers +v0x2845e60_0 .alias "outfinal", 0 0, v0x2846230_0; +S_0x2844560 .scope generate, "addbits[28]" "addbits[28]" 3 283, 3 283, S_0x2840e20; + .timescale -9 -12; +P_0x2843f78 .param/l "i" 3 283, +C4<011100>; +S_0x28446d0 .scope module, "attempt" "MiddleAddSubSLT" 3 285, 3 189, S_0x2844560; + .timescale -9 -12; +L_0x2aca250/d .functor NOT 1, L_0x2998230, C4<0>, C4<0>, C4<0>; +L_0x2aca250 .delay (10000,10000,10000) L_0x2aca250/d; +L_0x2998b10/d .functor NOT 1, L_0x2998bd0, C4<0>, C4<0>, C4<0>; +L_0x2998b10 .delay (10000,10000,10000) L_0x2998b10/d; +L_0x2998c70/d .functor AND 1, L_0x2998db0, L_0x2998b10, C4<1>, C4<1>; +L_0x2998c70 .delay (20000,20000,20000) L_0x2998c70/d; +L_0x2998e50/d .functor XOR 1, L_0x2998190, L_0x29988a0, C4<0>, C4<0>; +L_0x2998e50 .delay (40000,40000,40000) L_0x2998e50/d; +L_0x2998f40/d .functor XOR 1, L_0x2998e50, L_0x2998360, C4<0>, C4<0>; +L_0x2998f40 .delay (40000,40000,40000) L_0x2998f40/d; +L_0x2999030/d .functor AND 1, L_0x2998190, L_0x29988a0, C4<1>, C4<1>; +L_0x2999030 .delay (20000,20000,20000) L_0x2999030/d; +L_0x29991a0/d .functor AND 1, L_0x2998e50, L_0x2998360, C4<1>, C4<1>; +L_0x29991a0 .delay (20000,20000,20000) L_0x29991a0/d; +L_0x2999290/d .functor OR 1, L_0x2999030, L_0x29991a0, C4<0>, C4<0>; +L_0x2999290 .delay (20000,20000,20000) L_0x2999290/d; +v0x2844d60_0 .net "A", 0 0, L_0x2998190; 1 drivers +v0x2844e20_0 .net "AandB", 0 0, L_0x2999030; 1 drivers +v0x2844ec0_0 .net "AddSubSLTSum", 0 0, L_0x2998f40; 1 drivers +v0x2844f60_0 .net "AxorB", 0 0, L_0x2998e50; 1 drivers +v0x2844fe0_0 .net "B", 0 0, L_0x2998230; 1 drivers +v0x2845090_0 .net "BornB", 0 0, L_0x29988a0; 1 drivers +v0x2845150_0 .net "CINandAxorB", 0 0, L_0x29991a0; 1 drivers +v0x28451d0_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x2845250_0 .net *"_s3", 0 0, L_0x2998bd0; 1 drivers +v0x28452d0_0 .net *"_s5", 0 0, L_0x2998db0; 1 drivers +v0x2845370_0 .net "carryin", 0 0, L_0x2998360; 1 drivers +v0x2845410_0 .net "carryout", 0 0, L_0x2999290; 1 drivers +v0x28454b0_0 .net "nB", 0 0, L_0x2aca250; 1 drivers +v0x2845560_0 .net "nCmd2", 0 0, L_0x2998b10; 1 drivers +v0x2845660_0 .net "subtract", 0 0, L_0x2998c70; 1 drivers +L_0x2998a70 .part v0x2960210_0, 0, 1; +L_0x2998bd0 .part v0x2960210_0, 2, 1; +L_0x2998db0 .part v0x2960210_0, 0, 1; +S_0x28447c0 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x28446d0; + .timescale -9 -12; +L_0x29985c0/d .functor NOT 1, L_0x2998a70, C4<0>, C4<0>, C4<0>; +L_0x29985c0 .delay (10000,10000,10000) L_0x29985c0/d; +L_0x2998680/d .functor AND 1, L_0x2998230, L_0x29985c0, C4<1>, C4<1>; +L_0x2998680 .delay (20000,20000,20000) L_0x2998680/d; +L_0x2998790/d .functor AND 1, L_0x2aca250, L_0x2998a70, C4<1>, C4<1>; +L_0x2998790 .delay (20000,20000,20000) L_0x2998790/d; +L_0x29988a0/d .functor OR 1, L_0x2998680, L_0x2998790, C4<0>, C4<0>; +L_0x29988a0 .delay (20000,20000,20000) L_0x29988a0/d; +v0x28448b0_0 .net "S", 0 0, L_0x2998a70; 1 drivers +v0x2844950_0 .alias "in0", 0 0, v0x2844fe0_0; +v0x28449f0_0 .alias "in1", 0 0, v0x28454b0_0; +v0x2844a90_0 .net "nS", 0 0, L_0x29985c0; 1 drivers +v0x2844b40_0 .net "out0", 0 0, L_0x2998680; 1 drivers +v0x2844be0_0 .net "out1", 0 0, L_0x2998790; 1 drivers +v0x2844cc0_0 .alias "outfinal", 0 0, v0x2845090_0; +S_0x28433c0 .scope generate, "addbits[29]" "addbits[29]" 3 283, 3 283, S_0x2840e20; + .timescale -9 -12; +P_0x2842dd8 .param/l "i" 3 283, +C4<011101>; +S_0x2843530 .scope module, "attempt" "MiddleAddSubSLT" 3 285, 3 189, S_0x28433c0; + .timescale -9 -12; +L_0x2998400/d .functor NOT 1, L_0x2999760, C4<0>, C4<0>, C4<0>; +L_0x2998400 .delay (10000,10000,10000) L_0x2998400/d; +L_0x2999ff0/d .functor NOT 1, L_0x299a0b0, C4<0>, C4<0>, C4<0>; +L_0x2999ff0 .delay (10000,10000,10000) L_0x2999ff0/d; +L_0x299a150/d .functor AND 1, L_0x299a290, L_0x2999ff0, C4<1>, C4<1>; +L_0x299a150 .delay (20000,20000,20000) L_0x299a150/d; +L_0x299a330/d .functor XOR 1, L_0x29996c0, L_0x2999d80, C4<0>, C4<0>; +L_0x299a330 .delay (40000,40000,40000) L_0x299a330/d; +L_0x299a420/d .functor XOR 1, L_0x299a330, L_0x2999890, C4<0>, C4<0>; +L_0x299a420 .delay (40000,40000,40000) L_0x299a420/d; +L_0x299a510/d .functor AND 1, L_0x29996c0, L_0x2999d80, C4<1>, C4<1>; +L_0x299a510 .delay (20000,20000,20000) L_0x299a510/d; +L_0x299a680/d .functor AND 1, L_0x299a330, L_0x2999890, C4<1>, C4<1>; +L_0x299a680 .delay (20000,20000,20000) L_0x299a680/d; +L_0x299a770/d .functor OR 1, L_0x299a510, L_0x299a680, C4<0>, C4<0>; +L_0x299a770 .delay (20000,20000,20000) L_0x299a770/d; +v0x2843bc0_0 .net "A", 0 0, L_0x29996c0; 1 drivers +v0x2843c80_0 .net "AandB", 0 0, L_0x299a510; 1 drivers +v0x2843d20_0 .net "AddSubSLTSum", 0 0, L_0x299a420; 1 drivers +v0x2843dc0_0 .net "AxorB", 0 0, L_0x299a330; 1 drivers +v0x2843e40_0 .net "B", 0 0, L_0x2999760; 1 drivers +v0x2843ef0_0 .net "BornB", 0 0, L_0x2999d80; 1 drivers +v0x2843fb0_0 .net "CINandAxorB", 0 0, L_0x299a680; 1 drivers +v0x2844030_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x28440b0_0 .net *"_s3", 0 0, L_0x299a0b0; 1 drivers +v0x2844130_0 .net *"_s5", 0 0, L_0x299a290; 1 drivers +v0x28441d0_0 .net "carryin", 0 0, L_0x2999890; 1 drivers +v0x2844270_0 .net "carryout", 0 0, L_0x299a770; 1 drivers +v0x2844310_0 .net "nB", 0 0, L_0x2998400; 1 drivers +v0x28443c0_0 .net "nCmd2", 0 0, L_0x2999ff0; 1 drivers +v0x28444c0_0 .net "subtract", 0 0, L_0x299a150; 1 drivers +L_0x2999f50 .part v0x2960210_0, 0, 1; +L_0x299a0b0 .part v0x2960210_0, 2, 1; +L_0x299a290 .part v0x2960210_0, 0, 1; +S_0x2843620 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x2843530; + .timescale -9 -12; +L_0x2998560/d .functor NOT 1, L_0x2999f50, C4<0>, C4<0>, C4<0>; +L_0x2998560 .delay (10000,10000,10000) L_0x2998560/d; +L_0x2999b60/d .functor AND 1, L_0x2999760, L_0x2998560, C4<1>, C4<1>; +L_0x2999b60 .delay (20000,20000,20000) L_0x2999b60/d; +L_0x2999c70/d .functor AND 1, L_0x2998400, L_0x2999f50, C4<1>, C4<1>; +L_0x2999c70 .delay (20000,20000,20000) L_0x2999c70/d; +L_0x2999d80/d .functor OR 1, L_0x2999b60, L_0x2999c70, C4<0>, C4<0>; +L_0x2999d80 .delay (20000,20000,20000) L_0x2999d80/d; +v0x2843710_0 .net "S", 0 0, L_0x2999f50; 1 drivers +v0x28437b0_0 .alias "in0", 0 0, v0x2843e40_0; +v0x2843850_0 .alias "in1", 0 0, v0x2844310_0; +v0x28438f0_0 .net "nS", 0 0, L_0x2998560; 1 drivers +v0x28439a0_0 .net "out0", 0 0, L_0x2999b60; 1 drivers +v0x2843a40_0 .net "out1", 0 0, L_0x2999c70; 1 drivers +v0x2843b20_0 .alias "outfinal", 0 0, v0x2843ef0_0; +S_0x2842220 .scope generate, "addbits[30]" "addbits[30]" 3 283, 3 283, S_0x2840e20; + .timescale -9 -12; +P_0x2841b68 .param/l "i" 3 283, +C4<011110>; +S_0x2842390 .scope module, "attempt" "MiddleAddSubSLT" 3 285, 3 189, S_0x2842220; + .timescale -9 -12; +L_0x2999930/d .functor NOT 1, L_0x299ac40, C4<0>, C4<0>, C4<0>; +L_0x2999930 .delay (10000,10000,10000) L_0x2999930/d; +L_0x299b500/d .functor NOT 1, L_0x299b5c0, C4<0>, C4<0>, C4<0>; +L_0x299b500 .delay (10000,10000,10000) L_0x299b500/d; +L_0x299b660/d .functor AND 1, L_0x299b7a0, L_0x299b500, C4<1>, C4<1>; +L_0x299b660 .delay (20000,20000,20000) L_0x299b660/d; +L_0x299b840/d .functor XOR 1, L_0x299aba0, L_0x299b290, C4<0>, C4<0>; +L_0x299b840 .delay (40000,40000,40000) L_0x299b840/d; +L_0x2ad2c70/d .functor XOR 1, L_0x299b840, L_0x299ad70, C4<0>, C4<0>; +L_0x2ad2c70 .delay (40000,40000,40000) L_0x2ad2c70/d; +L_0x2ad2d60/d .functor AND 1, L_0x299aba0, L_0x299b290, C4<1>, C4<1>; +L_0x2ad2d60 .delay (20000,20000,20000) L_0x2ad2d60/d; +L_0x2ad2ed0/d .functor AND 1, L_0x299b840, L_0x299ad70, C4<1>, C4<1>; +L_0x2ad2ed0 .delay (20000,20000,20000) L_0x2ad2ed0/d; +L_0x2ad2fc0/d .functor OR 1, L_0x2ad2d60, L_0x2ad2ed0, C4<0>, C4<0>; +L_0x2ad2fc0 .delay (20000,20000,20000) L_0x2ad2fc0/d; +v0x2842a20_0 .net "A", 0 0, L_0x299aba0; 1 drivers +v0x2842ae0_0 .net "AandB", 0 0, L_0x2ad2d60; 1 drivers +v0x2842b80_0 .net "AddSubSLTSum", 0 0, L_0x2ad2c70; 1 drivers +v0x2842c20_0 .net "AxorB", 0 0, L_0x299b840; 1 drivers +v0x2842ca0_0 .net "B", 0 0, L_0x299ac40; 1 drivers +v0x2842d50_0 .net "BornB", 0 0, L_0x299b290; 1 drivers +v0x2842e10_0 .net "CINandAxorB", 0 0, L_0x2ad2ed0; 1 drivers +v0x2842e90_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x2842f10_0 .net *"_s3", 0 0, L_0x299b5c0; 1 drivers +v0x2842f90_0 .net *"_s5", 0 0, L_0x299b7a0; 1 drivers +v0x2843030_0 .net "carryin", 0 0, L_0x299ad70; 1 drivers +v0x28430d0_0 .net "carryout", 0 0, L_0x2ad2fc0; 1 drivers +v0x2843170_0 .net "nB", 0 0, L_0x2999930; 1 drivers +v0x2843220_0 .net "nCmd2", 0 0, L_0x299b500; 1 drivers +v0x2843320_0 .net "subtract", 0 0, L_0x299b660; 1 drivers +L_0x299b460 .part v0x2960210_0, 0, 1; +L_0x299b5c0 .part v0x2960210_0, 2, 1; +L_0x299b7a0 .part v0x2960210_0, 0, 1; +S_0x2842480 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x2842390; + .timescale -9 -12; +L_0x2999a90/d .functor NOT 1, L_0x299b460, C4<0>, C4<0>, C4<0>; +L_0x2999a90 .delay (10000,10000,10000) L_0x2999a90/d; +L_0x299b070/d .functor AND 1, L_0x299ac40, L_0x2999a90, C4<1>, C4<1>; +L_0x299b070 .delay (20000,20000,20000) L_0x299b070/d; +L_0x299b180/d .functor AND 1, L_0x2999930, L_0x299b460, C4<1>, C4<1>; +L_0x299b180 .delay (20000,20000,20000) L_0x299b180/d; +L_0x299b290/d .functor OR 1, L_0x299b070, L_0x299b180, C4<0>, C4<0>; +L_0x299b290 .delay (20000,20000,20000) L_0x299b290/d; +v0x2842570_0 .net "S", 0 0, L_0x299b460; 1 drivers +v0x2842610_0 .alias "in0", 0 0, v0x2842ca0_0; +v0x28426b0_0 .alias "in1", 0 0, v0x2843170_0; +v0x2842750_0 .net "nS", 0 0, L_0x2999a90; 1 drivers +v0x2842800_0 .net "out0", 0 0, L_0x299b070; 1 drivers +v0x28428a0_0 .net "out1", 0 0, L_0x299b180; 1 drivers +v0x2842980_0 .alias "outfinal", 0 0, v0x2842d50_0; +S_0x2840fc0 .scope generate, "addbits[31]" "addbits[31]" 3 283, 3 283, S_0x2840e20; + .timescale -9 -12; +P_0x28410b8 .param/l "i" 3 283, +C4<011111>; +S_0x2841150 .scope module, "attempt" "MiddleAddSubSLT" 3 285, 3 189, S_0x2840fc0; + .timescale -9 -12; +L_0x299ae10/d .functor NOT 1, L_0x2ad3380, C4<0>, C4<0>, C4<0>; +L_0x299ae10 .delay (10000,10000,10000) L_0x299ae10/d; +L_0x2ad3ca0/d .functor NOT 1, L_0x2ad3d40, C4<0>, C4<0>, C4<0>; +L_0x2ad3ca0 .delay (10000,10000,10000) L_0x2ad3ca0/d; +L_0x2ad3de0/d .functor AND 1, L_0x2ad3f20, L_0x2ad3ca0, C4<1>, C4<1>; +L_0x2ad3de0 .delay (20000,20000,20000) L_0x2ad3de0/d; +L_0x2ad3fc0/d .functor XOR 1, L_0x2ad32e0, L_0x2ad3a70, C4<0>, C4<0>; +L_0x2ad3fc0 .delay (40000,40000,40000) L_0x2ad3fc0/d; +L_0x2ad40b0/d .functor XOR 1, L_0x2ad3fc0, L_0x2ad34b0, C4<0>, C4<0>; +L_0x2ad40b0 .delay (40000,40000,40000) L_0x2ad40b0/d; +L_0x2ad41a0/d .functor AND 1, L_0x2ad32e0, L_0x2ad3a70, C4<1>, C4<1>; +L_0x2ad41a0 .delay (20000,20000,20000) L_0x2ad41a0/d; +L_0x2ad4310/d .functor AND 1, L_0x2ad3fc0, L_0x2ad34b0, C4<1>, C4<1>; +L_0x2ad4310 .delay (20000,20000,20000) L_0x2ad4310/d; +L_0x2ad4400/d .functor OR 1, L_0x2ad41a0, L_0x2ad4310, C4<0>, C4<0>; +L_0x2ad4400 .delay (20000,20000,20000) L_0x2ad4400/d; +v0x28417b0_0 .net "A", 0 0, L_0x2ad32e0; 1 drivers +v0x2841870_0 .net "AandB", 0 0, L_0x2ad41a0; 1 drivers +v0x2841910_0 .net "AddSubSLTSum", 0 0, L_0x2ad40b0; 1 drivers +v0x28419b0_0 .net "AxorB", 0 0, L_0x2ad3fc0; 1 drivers +v0x2841a30_0 .net "B", 0 0, L_0x2ad3380; 1 drivers +v0x2841ae0_0 .net "BornB", 0 0, L_0x2ad3a70; 1 drivers +v0x2841ba0_0 .net "CINandAxorB", 0 0, L_0x2ad4310; 1 drivers +v0x2841c20_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x2841ca0_0 .net *"_s3", 0 0, L_0x2ad3d40; 1 drivers +v0x2841d20_0 .net *"_s5", 0 0, L_0x2ad3f20; 1 drivers +v0x2841e20_0 .net "carryin", 0 0, L_0x2ad34b0; 1 drivers +v0x2841ec0_0 .net "carryout", 0 0, L_0x2ad4400; 1 drivers +v0x2841fd0_0 .net "nB", 0 0, L_0x299ae10; 1 drivers +v0x2842080_0 .net "nCmd2", 0 0, L_0x2ad3ca0; 1 drivers +v0x2842180_0 .net "subtract", 0 0, L_0x2ad3de0; 1 drivers +L_0x2ad3c00 .part v0x2960210_0, 0, 1; +L_0x2ad3d40 .part v0x2960210_0, 2, 1; +L_0x2ad3f20 .part v0x2960210_0, 0, 1; +S_0x2841240 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x2841150; + .timescale -9 -12; +L_0x299af70/d .functor NOT 1, L_0x2ad3c00, C4<0>, C4<0>, C4<0>; +L_0x299af70 .delay (10000,10000,10000) L_0x299af70/d; +L_0x2ad3890/d .functor AND 1, L_0x2ad3380, L_0x299af70, C4<1>, C4<1>; +L_0x2ad3890 .delay (20000,20000,20000) L_0x2ad3890/d; +L_0x2ad3980/d .functor AND 1, L_0x299ae10, L_0x2ad3c00, C4<1>, C4<1>; +L_0x2ad3980 .delay (20000,20000,20000) L_0x2ad3980/d; +L_0x2ad3a70/d .functor OR 1, L_0x2ad3890, L_0x2ad3980, C4<0>, C4<0>; +L_0x2ad3a70 .delay (20000,20000,20000) L_0x2ad3a70/d; +v0x2841330_0 .net "S", 0 0, L_0x2ad3c00; 1 drivers +v0x28413d0_0 .alias "in0", 0 0, v0x2841a30_0; +v0x2841470_0 .alias "in1", 0 0, v0x2841fd0_0; +v0x2841510_0 .net "nS", 0 0, L_0x299af70; 1 drivers +v0x2841590_0 .net "out0", 0 0, L_0x2ad3890; 1 drivers +v0x2841630_0 .net "out1", 0 0, L_0x2ad3980; 1 drivers +v0x2841710_0 .alias "outfinal", 0 0, v0x2841ae0_0; +S_0x28293f0 .scope module, "trial1" "AndNand32" 3 387, 3 216, S_0x25e6a40; + .timescale -9 -12; +P_0x2828eb8 .param/l "size" 3 223, +C4<0100000>; +v0x2840c20_0 .alias "A", 31 0, v0x295f580_0; +v0x2840ca0_0 .alias "AndNandOut", 31 0, v0x2960110_0; +v0x2840d20_0 .alias "B", 31 0, v0x295f6a0_0; +v0x2840da0_0 .alias "Command", 2 0, v0x295f7a0_0; +L_0x2ad6970 .part/pv L_0x2ad6700, 1, 1, 32; +L_0x2ad78a0 .part v0x295fe90_0, 1, 1; +L_0x2ad7940 .part v0x2960190_0, 1, 1; +L_0x2ad8130 .part/pv L_0x2ad7ee0, 2, 1, 32; +L_0x2ad81d0 .part v0x295fe90_0, 2, 1; +L_0x2ad8270 .part v0x2960190_0, 2, 1; +L_0x2ad8ba0 .part/pv L_0x2ad8930, 3, 1, 32; +L_0x2ad8c40 .part v0x295fe90_0, 3, 1; +L_0x2ad8d30 .part v0x2960190_0, 3, 1; +L_0x2ad9600 .part/pv L_0x2ad9390, 4, 1, 32; +L_0x2ad9700 .part v0x295fe90_0, 4, 1; +L_0x2ad97a0 .part v0x2960190_0, 4, 1; +L_0x2ada070 .part/pv L_0x2ad9e00, 5, 1, 32; +L_0x2ada110 .part v0x295fe90_0, 5, 1; +L_0x2ada230 .part v0x2960190_0, 5, 1; +L_0x2adab40 .part/pv L_0x2ada8d0, 6, 1, 32; +L_0x2adac70 .part v0x295fe90_0, 6, 1; +L_0x2adad10 .part v0x2960190_0, 6, 1; +L_0x2adb640 .part/pv L_0x2adb3d0, 7, 1, 32; +L_0x2adb6e0 .part v0x295fe90_0, 7, 1; +L_0x2adae00 .part v0x2960190_0, 7, 1; +L_0x2adc0a0 .part/pv L_0x2adbe30, 8, 1, 32; +L_0x2adb780 .part v0x295fe90_0, 8, 1; +L_0x2adc200 .part v0x2960190_0, 8, 1; +L_0x2adcb20 .part/pv L_0x2adc8b0, 9, 1, 32; +L_0x2adcbc0 .part v0x295fe90_0, 9, 1; +L_0x2adc2f0 .part v0x2960190_0, 9, 1; +L_0x2add3f0 .part/pv L_0x2add1c0, 10, 1, 32; +L_0x2adcc60 .part v0x295fe90_0, 10, 1; +L_0x2add580 .part v0x2960190_0, 10, 1; +L_0x2addda0 .part/pv L_0x2addb70, 11, 1, 32; +L_0x2adde40 .part v0x295fe90_0, 11, 1; +L_0x2add670 .part v0x2960190_0, 11, 1; +L_0x2ade750 .part/pv L_0x2ade4e0, 12, 1, 32; +L_0x2addee0 .part v0x295fe90_0, 12, 1; +L_0x2ade910 .part v0x2960190_0, 12, 1; +L_0x2adf1d0 .part/pv L_0x2adef60, 13, 1, 32; +L_0x2adf270 .part v0x295fe90_0, 13, 1; +L_0x2ade9b0 .part v0x2960190_0, 13, 1; +L_0x2adfc30 .part/pv L_0x2adf9c0, 14, 1, 32; +L_0x2adf310 .part v0x295fe90_0, 14, 1; +L_0x2adf3b0 .part v0x2960190_0, 14, 1; +L_0x2ae06a0 .part/pv L_0x2ae0430, 15, 1, 32; +L_0x2ae0740 .part v0x295fe90_0, 15, 1; +L_0x2adfe70 .part v0x2960190_0, 15, 1; +L_0x2ae1110 .part/pv L_0x2ae0ea0, 16, 1, 32; +L_0x2ae07e0 .part v0x295fe90_0, 16, 1; +L_0x2ae0880 .part v0x2960190_0, 16, 1; +L_0x2ae1b90 .part/pv L_0x2ae1920, 17, 1, 32; +L_0x2ae1c30 .part v0x295fe90_0, 17, 1; +L_0x2ae1380 .part v0x2960190_0, 17, 1; +L_0x2ae25f0 .part/pv L_0x2ae2380, 18, 1, 32; +L_0x2ae1cd0 .part v0x295fe90_0, 18, 1; +L_0x2ae1d70 .part v0x2960190_0, 18, 1; +L_0x2ae3070 .part/pv L_0x2ae2e00, 19, 1, 32; +L_0x2ae3110 .part v0x295fe90_0, 19, 1; +L_0x2ae2690 .part v0x2960190_0, 19, 1; +L_0x2ae3ad0 .part/pv L_0x2ae3860, 20, 1, 32; +L_0x2ae31b0 .part v0x295fe90_0, 20, 1; +L_0x2ae3250 .part v0x2960190_0, 20, 1; +L_0x2ae4540 .part/pv L_0x2ae42d0, 21, 1, 32; +L_0x2ae45e0 .part v0x295fe90_0, 21, 1; +L_0x2ae3b70 .part v0x2960190_0, 21, 1; +L_0x2ae4fb0 .part/pv L_0x2ae4d40, 22, 1, 32; +L_0x2ae4680 .part v0x295fe90_0, 22, 1; +L_0x2ae4720 .part v0x2960190_0, 22, 1; +L_0x2ae5a30 .part/pv L_0x2ae57c0, 23, 1, 32; +L_0x2ae5ad0 .part v0x295fe90_0, 23, 1; +L_0x2ae5050 .part v0x2960190_0, 23, 1; +L_0x2ae6490 .part/pv L_0x2ae6220, 24, 1, 32; +L_0x2ae5b70 .part v0x295fe90_0, 24, 1; +L_0x2ae5c10 .part v0x2960190_0, 24, 1; +L_0x2ae6f00 .part/pv L_0x2ae6c90, 25, 1, 32; +L_0x2ae6fa0 .part v0x295fe90_0, 25, 1; +L_0x2ae6530 .part v0x2960190_0, 25, 1; +L_0x2ae7960 .part/pv L_0x2ae76f0, 26, 1, 32; +L_0x2ae7040 .part v0x295fe90_0, 26, 1; +L_0x2ae70e0 .part v0x2960190_0, 26, 1; +L_0x2ae83d0 .part/pv L_0x2ae8160, 27, 1, 32; +L_0x2ae8470 .part v0x295fe90_0, 27, 1; +L_0x2ae7a00 .part v0x2960190_0, 27, 1; +L_0x2ae8e40 .part/pv L_0x2ae8bd0, 28, 1, 32; +L_0x2ae8510 .part v0x295fe90_0, 28, 1; +L_0x2ae85b0 .part v0x2960190_0, 28, 1; +L_0x2ae98c0 .part/pv L_0x2ae9650, 29, 1, 32; +L_0x2ae9960 .part v0x295fe90_0, 29, 1; +L_0x2ae8ee0 .part v0x2960190_0, 29, 1; +L_0x2aea320 .part/pv L_0x2aea0b0, 30, 1, 32; +L_0x2ae9a00 .part v0x295fe90_0, 30, 1; +L_0x2ae9aa0 .part v0x2960190_0, 30, 1; +L_0x2aead90 .part/pv L_0x2aeab20, 31, 1, 32; +L_0x2a37f60 .part v0x295fe90_0, 31, 1; +L_0x2aea3c0 .part v0x2960190_0, 31, 1; +L_0x2aec010 .part/pv L_0x2a386c0, 0, 1, 32; +L_0x2a38000 .part v0x295fe90_0, 0, 1; +L_0x2a380a0 .part v0x2960190_0, 0, 1; +S_0x28401f0 .scope module, "attempt2" "AndNand" 3 227, 3 149, S_0x28293f0; + .timescale -9 -12; +L_0x2aea4b0/d .functor NAND 1, L_0x2a38000, L_0x2a380a0, C4<1>, C4<1>; +L_0x2aea4b0 .delay (10000,10000,10000) L_0x2aea4b0/d; +L_0x2aea610/d .functor NOT 1, L_0x2aea4b0, C4<0>, C4<0>, C4<0>; +L_0x2aea610 .delay (10000,10000,10000) L_0x2aea610/d; +v0x2840810_0 .net "A", 0 0, L_0x2a38000; 1 drivers +v0x28408d0_0 .net "AandB", 0 0, L_0x2aea610; 1 drivers +v0x2840950_0 .net "AnandB", 0 0, L_0x2aea4b0; 1 drivers +v0x2840a00_0 .net "AndNandOut", 0 0, L_0x2a386c0; 1 drivers +v0x2840ae0_0 .net "B", 0 0, L_0x2a380a0; 1 drivers +v0x2840b60_0 .alias "Command", 2 0, v0x295f7a0_0; +L_0x2aebf70 .part v0x2960210_0, 0, 1; +S_0x28402e0 .scope module, "potato" "TwoInMux" 3 161, 3 109, S_0x28401f0; + .timescale -9 -12; +L_0x2a383a0/d .functor NOT 1, L_0x2aebf70, C4<0>, C4<0>, C4<0>; +L_0x2a383a0 .delay (10000,10000,10000) L_0x2a383a0/d; +L_0x2a38460/d .functor AND 1, L_0x2aea610, L_0x2a383a0, C4<1>, C4<1>; +L_0x2a38460 .delay (20000,20000,20000) L_0x2a38460/d; +L_0x2a38570/d .functor AND 1, L_0x2aea4b0, L_0x2aebf70, C4<1>, C4<1>; +L_0x2a38570 .delay (20000,20000,20000) L_0x2a38570/d; +L_0x2a386c0/d .functor OR 1, L_0x2a38460, L_0x2a38570, C4<0>, C4<0>; +L_0x2a386c0 .delay (20000,20000,20000) L_0x2a386c0/d; +v0x28403d0_0 .net "S", 0 0, L_0x2aebf70; 1 drivers +v0x2840450_0 .alias "in0", 0 0, v0x28408d0_0; +v0x28404d0_0 .alias "in1", 0 0, v0x2840950_0; +v0x2840570_0 .net "nS", 0 0, L_0x2a383a0; 1 drivers +v0x28405f0_0 .net "out0", 0 0, L_0x2a38460; 1 drivers +v0x2840690_0 .net "out1", 0 0, L_0x2a38570; 1 drivers +v0x2840770_0 .alias "outfinal", 0 0, v0x2840a00_0; +S_0x283f630 .scope generate, "andbits[1]" "andbits[1]" 3 231, 3 231, S_0x28293f0; + .timescale -9 -12; +P_0x283f728 .param/l "i" 3 231, +C4<01>; +S_0x283f7a0 .scope module, "attempt" "AndNand" 3 233, 3 149, S_0x283f630; + .timescale -9 -12; +L_0x2ad5b00/d .functor NAND 1, L_0x2ad78a0, L_0x2ad7940, C4<1>, C4<1>; +L_0x2ad5b00 .delay (10000,10000,10000) L_0x2ad5b00/d; +L_0x2a82180/d .functor NOT 1, L_0x2ad5b00, C4<0>, C4<0>, C4<0>; +L_0x2a82180 .delay (10000,10000,10000) L_0x2a82180/d; +v0x283fde0_0 .net "A", 0 0, L_0x2ad78a0; 1 drivers +v0x283fea0_0 .net "AandB", 0 0, L_0x2a82180; 1 drivers +v0x283ff20_0 .net "AnandB", 0 0, L_0x2ad5b00; 1 drivers +v0x283ffd0_0 .net "AndNandOut", 0 0, L_0x2ad6700; 1 drivers +v0x28400b0_0 .net "B", 0 0, L_0x2ad7940; 1 drivers +v0x2840130_0 .alias "Command", 2 0, v0x295f7a0_0; +L_0x2ad68d0 .part v0x2960210_0, 0, 1; +S_0x283f890 .scope module, "potato" "TwoInMux" 3 161, 3 109, S_0x283f7a0; + .timescale -9 -12; +L_0x2a822b0/d .functor NOT 1, L_0x2ad68d0, C4<0>, C4<0>, C4<0>; +L_0x2a822b0 .delay (10000,10000,10000) L_0x2a822b0/d; +L_0x2ad64a0/d .functor AND 1, L_0x2a82180, L_0x2a822b0, C4<1>, C4<1>; +L_0x2ad64a0 .delay (20000,20000,20000) L_0x2ad64a0/d; +L_0x2ad65b0/d .functor AND 1, L_0x2ad5b00, L_0x2ad68d0, C4<1>, C4<1>; +L_0x2ad65b0 .delay (20000,20000,20000) L_0x2ad65b0/d; +L_0x2ad6700/d .functor OR 1, L_0x2ad64a0, L_0x2ad65b0, C4<0>, C4<0>; +L_0x2ad6700 .delay (20000,20000,20000) L_0x2ad6700/d; +v0x283f980_0 .net "S", 0 0, L_0x2ad68d0; 1 drivers +v0x283fa00_0 .alias "in0", 0 0, v0x283fea0_0; +v0x283faa0_0 .alias "in1", 0 0, v0x283ff20_0; +v0x283fb40_0 .net "nS", 0 0, L_0x2a822b0; 1 drivers +v0x283fbc0_0 .net "out0", 0 0, L_0x2ad64a0; 1 drivers +v0x283fc60_0 .net "out1", 0 0, L_0x2ad65b0; 1 drivers +v0x283fd40_0 .alias "outfinal", 0 0, v0x283ffd0_0; +S_0x283ea70 .scope generate, "andbits[2]" "andbits[2]" 3 231, 3 231, S_0x28293f0; + .timescale -9 -12; +P_0x283eb68 .param/l "i" 3 231, +C4<010>; +S_0x283ebe0 .scope module, "attempt" "AndNand" 3 233, 3 149, S_0x283ea70; + .timescale -9 -12; +L_0x2ad7a30/d .functor NAND 1, L_0x2ad81d0, L_0x2ad8270, C4<1>, C4<1>; +L_0x2ad7a30 .delay (10000,10000,10000) L_0x2ad7a30/d; +L_0x2ad7b30/d .functor NOT 1, L_0x2ad7a30, C4<0>, C4<0>, C4<0>; +L_0x2ad7b30 .delay (10000,10000,10000) L_0x2ad7b30/d; +v0x283f220_0 .net "A", 0 0, L_0x2ad81d0; 1 drivers +v0x283f2e0_0 .net "AandB", 0 0, L_0x2ad7b30; 1 drivers +v0x283f360_0 .net "AnandB", 0 0, L_0x2ad7a30; 1 drivers +v0x283f410_0 .net "AndNandOut", 0 0, L_0x2ad7ee0; 1 drivers +v0x283f4f0_0 .net "B", 0 0, L_0x2ad8270; 1 drivers +v0x283f570_0 .alias "Command", 2 0, v0x295f7a0_0; +L_0x2ad8090 .part v0x2960210_0, 0, 1; +S_0x283ecd0 .scope module, "potato" "TwoInMux" 3 161, 3 109, S_0x283ebe0; + .timescale -9 -12; +L_0x2ad7c20/d .functor NOT 1, L_0x2ad8090, C4<0>, C4<0>, C4<0>; +L_0x2ad7c20 .delay (10000,10000,10000) L_0x2ad7c20/d; +L_0x2ad7cc0/d .functor AND 1, L_0x2ad7b30, L_0x2ad7c20, C4<1>, C4<1>; +L_0x2ad7cc0 .delay (20000,20000,20000) L_0x2ad7cc0/d; +L_0x2ad7db0/d .functor AND 1, L_0x2ad7a30, L_0x2ad8090, C4<1>, C4<1>; +L_0x2ad7db0 .delay (20000,20000,20000) L_0x2ad7db0/d; +L_0x2ad7ee0/d .functor OR 1, L_0x2ad7cc0, L_0x2ad7db0, C4<0>, C4<0>; +L_0x2ad7ee0 .delay (20000,20000,20000) L_0x2ad7ee0/d; +v0x283edc0_0 .net "S", 0 0, L_0x2ad8090; 1 drivers +v0x283ee40_0 .alias "in0", 0 0, v0x283f2e0_0; +v0x283eee0_0 .alias "in1", 0 0, v0x283f360_0; +v0x283ef80_0 .net "nS", 0 0, L_0x2ad7c20; 1 drivers +v0x283f000_0 .net "out0", 0 0, L_0x2ad7cc0; 1 drivers +v0x283f0a0_0 .net "out1", 0 0, L_0x2ad7db0; 1 drivers +v0x283f180_0 .alias "outfinal", 0 0, v0x283f410_0; +S_0x283deb0 .scope generate, "andbits[3]" "andbits[3]" 3 231, 3 231, S_0x28293f0; + .timescale -9 -12; +P_0x283dfa8 .param/l "i" 3 231, +C4<011>; +S_0x283e020 .scope module, "attempt" "AndNand" 3 233, 3 149, S_0x283deb0; + .timescale -9 -12; +L_0x2ad83a0/d .functor NAND 1, L_0x2ad8c40, L_0x2ad8d30, C4<1>, C4<1>; +L_0x2ad83a0 .delay (10000,10000,10000) L_0x2ad83a0/d; +L_0x2ad84e0/d .functor NOT 1, L_0x2ad83a0, C4<0>, C4<0>, C4<0>; +L_0x2ad84e0 .delay (10000,10000,10000) L_0x2ad84e0/d; +v0x283e660_0 .net "A", 0 0, L_0x2ad8c40; 1 drivers +v0x283e720_0 .net "AandB", 0 0, L_0x2ad84e0; 1 drivers +v0x283e7a0_0 .net "AnandB", 0 0, L_0x2ad83a0; 1 drivers +v0x283e850_0 .net "AndNandOut", 0 0, L_0x2ad8930; 1 drivers +v0x283e930_0 .net "B", 0 0, L_0x2ad8d30; 1 drivers +v0x283e9b0_0 .alias "Command", 2 0, v0x295f7a0_0; +L_0x2ad8b00 .part v0x2960210_0, 0, 1; +S_0x283e110 .scope module, "potato" "TwoInMux" 3 161, 3 109, S_0x283e020; + .timescale -9 -12; +L_0x2ad8610/d .functor NOT 1, L_0x2ad8b00, C4<0>, C4<0>, C4<0>; +L_0x2ad8610 .delay (10000,10000,10000) L_0x2ad8610/d; +L_0x2ad86d0/d .functor AND 1, L_0x2ad84e0, L_0x2ad8610, C4<1>, C4<1>; +L_0x2ad86d0 .delay (20000,20000,20000) L_0x2ad86d0/d; +L_0x2ad87e0/d .functor AND 1, L_0x2ad83a0, L_0x2ad8b00, C4<1>, C4<1>; +L_0x2ad87e0 .delay (20000,20000,20000) L_0x2ad87e0/d; +L_0x2ad8930/d .functor OR 1, L_0x2ad86d0, L_0x2ad87e0, C4<0>, C4<0>; +L_0x2ad8930 .delay (20000,20000,20000) L_0x2ad8930/d; +v0x283e200_0 .net "S", 0 0, L_0x2ad8b00; 1 drivers +v0x283e280_0 .alias "in0", 0 0, v0x283e720_0; +v0x283e320_0 .alias "in1", 0 0, v0x283e7a0_0; +v0x283e3c0_0 .net "nS", 0 0, L_0x2ad8610; 1 drivers +v0x283e440_0 .net "out0", 0 0, L_0x2ad86d0; 1 drivers +v0x283e4e0_0 .net "out1", 0 0, L_0x2ad87e0; 1 drivers +v0x283e5c0_0 .alias "outfinal", 0 0, v0x283e850_0; +S_0x283d2f0 .scope generate, "andbits[4]" "andbits[4]" 3 231, 3 231, S_0x28293f0; + .timescale -9 -12; +P_0x283d3e8 .param/l "i" 3 231, +C4<0100>; +S_0x283d460 .scope module, "attempt" "AndNand" 3 233, 3 149, S_0x283d2f0; + .timescale -9 -12; +L_0x2ad8e20/d .functor NAND 1, L_0x2ad9700, L_0x2ad97a0, C4<1>, C4<1>; +L_0x2ad8e20 .delay (10000,10000,10000) L_0x2ad8e20/d; +L_0x2ad8f40/d .functor NOT 1, L_0x2ad8e20, C4<0>, C4<0>, C4<0>; +L_0x2ad8f40 .delay (10000,10000,10000) L_0x2ad8f40/d; +v0x283daa0_0 .net "A", 0 0, L_0x2ad9700; 1 drivers +v0x283db60_0 .net "AandB", 0 0, L_0x2ad8f40; 1 drivers +v0x283dbe0_0 .net "AnandB", 0 0, L_0x2ad8e20; 1 drivers +v0x283dc90_0 .net "AndNandOut", 0 0, L_0x2ad9390; 1 drivers +v0x283dd70_0 .net "B", 0 0, L_0x2ad97a0; 1 drivers +v0x283ddf0_0 .alias "Command", 2 0, v0x295f7a0_0; +L_0x2ad9560 .part v0x2960210_0, 0, 1; +S_0x283d550 .scope module, "potato" "TwoInMux" 3 161, 3 109, S_0x283d460; + .timescale -9 -12; +L_0x2ad9070/d .functor NOT 1, L_0x2ad9560, C4<0>, C4<0>, C4<0>; +L_0x2ad9070 .delay (10000,10000,10000) L_0x2ad9070/d; +L_0x2ad9130/d .functor AND 1, L_0x2ad8f40, L_0x2ad9070, C4<1>, C4<1>; +L_0x2ad9130 .delay (20000,20000,20000) L_0x2ad9130/d; +L_0x2ad9240/d .functor AND 1, L_0x2ad8e20, L_0x2ad9560, C4<1>, C4<1>; +L_0x2ad9240 .delay (20000,20000,20000) L_0x2ad9240/d; +L_0x2ad9390/d .functor OR 1, L_0x2ad9130, L_0x2ad9240, C4<0>, C4<0>; +L_0x2ad9390 .delay (20000,20000,20000) L_0x2ad9390/d; +v0x283d640_0 .net "S", 0 0, L_0x2ad9560; 1 drivers +v0x283d6c0_0 .alias "in0", 0 0, v0x283db60_0; +v0x283d760_0 .alias "in1", 0 0, v0x283dbe0_0; +v0x283d800_0 .net "nS", 0 0, L_0x2ad9070; 1 drivers +v0x283d880_0 .net "out0", 0 0, L_0x2ad9130; 1 drivers +v0x283d920_0 .net "out1", 0 0, L_0x2ad9240; 1 drivers +v0x283da00_0 .alias "outfinal", 0 0, v0x283dc90_0; +S_0x283c730 .scope generate, "andbits[5]" "andbits[5]" 3 231, 3 231, S_0x28293f0; + .timescale -9 -12; +P_0x283c828 .param/l "i" 3 231, +C4<0101>; +S_0x283c8a0 .scope module, "attempt" "AndNand" 3 233, 3 149, S_0x283c730; + .timescale -9 -12; +L_0x2ad96a0/d .functor NAND 1, L_0x2ada110, L_0x2ada230, C4<1>, C4<1>; +L_0x2ad96a0 .delay (10000,10000,10000) L_0x2ad96a0/d; +L_0x2ad99b0/d .functor NOT 1, L_0x2ad96a0, C4<0>, C4<0>, C4<0>; +L_0x2ad99b0 .delay (10000,10000,10000) L_0x2ad99b0/d; +v0x283cee0_0 .net "A", 0 0, L_0x2ada110; 1 drivers +v0x283cfa0_0 .net "AandB", 0 0, L_0x2ad99b0; 1 drivers +v0x283d020_0 .net "AnandB", 0 0, L_0x2ad96a0; 1 drivers +v0x283d0d0_0 .net "AndNandOut", 0 0, L_0x2ad9e00; 1 drivers +v0x283d1b0_0 .net "B", 0 0, L_0x2ada230; 1 drivers +v0x283d230_0 .alias "Command", 2 0, v0x295f7a0_0; +L_0x2ad9fd0 .part v0x2960210_0, 0, 1; +S_0x283c990 .scope module, "potato" "TwoInMux" 3 161, 3 109, S_0x283c8a0; + .timescale -9 -12; +L_0x2ad9ae0/d .functor NOT 1, L_0x2ad9fd0, C4<0>, C4<0>, C4<0>; +L_0x2ad9ae0 .delay (10000,10000,10000) L_0x2ad9ae0/d; +L_0x2ad9ba0/d .functor AND 1, L_0x2ad99b0, L_0x2ad9ae0, C4<1>, C4<1>; +L_0x2ad9ba0 .delay (20000,20000,20000) L_0x2ad9ba0/d; +L_0x2ad9cb0/d .functor AND 1, L_0x2ad96a0, L_0x2ad9fd0, C4<1>, C4<1>; +L_0x2ad9cb0 .delay (20000,20000,20000) L_0x2ad9cb0/d; +L_0x2ad9e00/d .functor OR 1, L_0x2ad9ba0, L_0x2ad9cb0, C4<0>, C4<0>; +L_0x2ad9e00 .delay (20000,20000,20000) L_0x2ad9e00/d; +v0x283ca80_0 .net "S", 0 0, L_0x2ad9fd0; 1 drivers +v0x283cb00_0 .alias "in0", 0 0, v0x283cfa0_0; +v0x283cba0_0 .alias "in1", 0 0, v0x283d020_0; +v0x283cc40_0 .net "nS", 0 0, L_0x2ad9ae0; 1 drivers +v0x283ccc0_0 .net "out0", 0 0, L_0x2ad9ba0; 1 drivers +v0x283cd60_0 .net "out1", 0 0, L_0x2ad9cb0; 1 drivers +v0x283ce40_0 .alias "outfinal", 0 0, v0x283d0d0_0; +S_0x283bb70 .scope generate, "andbits[6]" "andbits[6]" 3 231, 3 231, S_0x28293f0; + .timescale -9 -12; +P_0x283bc68 .param/l "i" 3 231, +C4<0110>; +S_0x283bce0 .scope module, "attempt" "AndNand" 3 233, 3 149, S_0x283bb70; + .timescale -9 -12; +L_0x2ada320/d .functor NAND 1, L_0x2adac70, L_0x2adad10, C4<1>, C4<1>; +L_0x2ada320 .delay (10000,10000,10000) L_0x2ada320/d; +L_0x2ada480/d .functor NOT 1, L_0x2ada320, C4<0>, C4<0>, C4<0>; +L_0x2ada480 .delay (10000,10000,10000) L_0x2ada480/d; +v0x283c320_0 .net "A", 0 0, L_0x2adac70; 1 drivers +v0x283c3e0_0 .net "AandB", 0 0, L_0x2ada480; 1 drivers +v0x283c460_0 .net "AnandB", 0 0, L_0x2ada320; 1 drivers +v0x283c510_0 .net "AndNandOut", 0 0, L_0x2ada8d0; 1 drivers +v0x283c5f0_0 .net "B", 0 0, L_0x2adad10; 1 drivers +v0x283c670_0 .alias "Command", 2 0, v0x295f7a0_0; +L_0x2adaaa0 .part v0x2960210_0, 0, 1; +S_0x283bdd0 .scope module, "potato" "TwoInMux" 3 161, 3 109, S_0x283bce0; + .timescale -9 -12; +L_0x2ada5b0/d .functor NOT 1, L_0x2adaaa0, C4<0>, C4<0>, C4<0>; +L_0x2ada5b0 .delay (10000,10000,10000) L_0x2ada5b0/d; +L_0x2ada670/d .functor AND 1, L_0x2ada480, L_0x2ada5b0, C4<1>, C4<1>; +L_0x2ada670 .delay (20000,20000,20000) L_0x2ada670/d; +L_0x2ada780/d .functor AND 1, L_0x2ada320, L_0x2adaaa0, C4<1>, C4<1>; +L_0x2ada780 .delay (20000,20000,20000) L_0x2ada780/d; +L_0x2ada8d0/d .functor OR 1, L_0x2ada670, L_0x2ada780, C4<0>, C4<0>; +L_0x2ada8d0 .delay (20000,20000,20000) L_0x2ada8d0/d; +v0x283bec0_0 .net "S", 0 0, L_0x2adaaa0; 1 drivers +v0x283bf40_0 .alias "in0", 0 0, v0x283c3e0_0; +v0x283bfe0_0 .alias "in1", 0 0, v0x283c460_0; +v0x283c080_0 .net "nS", 0 0, L_0x2ada5b0; 1 drivers +v0x283c100_0 .net "out0", 0 0, L_0x2ada670; 1 drivers +v0x283c1a0_0 .net "out1", 0 0, L_0x2ada780; 1 drivers +v0x283c280_0 .alias "outfinal", 0 0, v0x283c510_0; +S_0x283afb0 .scope generate, "andbits[7]" "andbits[7]" 3 231, 3 231, S_0x28293f0; + .timescale -9 -12; +P_0x283b0a8 .param/l "i" 3 231, +C4<0111>; +S_0x283b120 .scope module, "attempt" "AndNand" 3 233, 3 149, S_0x283afb0; + .timescale -9 -12; +L_0x2adabe0/d .functor NAND 1, L_0x2adb6e0, L_0x2adae00, C4<1>, C4<1>; +L_0x2adabe0 .delay (10000,10000,10000) L_0x2adabe0/d; +L_0x2adaf80/d .functor NOT 1, L_0x2adabe0, C4<0>, C4<0>, C4<0>; +L_0x2adaf80 .delay (10000,10000,10000) L_0x2adaf80/d; +v0x283b760_0 .net "A", 0 0, L_0x2adb6e0; 1 drivers +v0x283b820_0 .net "AandB", 0 0, L_0x2adaf80; 1 drivers +v0x283b8a0_0 .net "AnandB", 0 0, L_0x2adabe0; 1 drivers +v0x283b950_0 .net "AndNandOut", 0 0, L_0x2adb3d0; 1 drivers +v0x283ba30_0 .net "B", 0 0, L_0x2adae00; 1 drivers +v0x283bab0_0 .alias "Command", 2 0, v0x295f7a0_0; +L_0x2adb5a0 .part v0x2960210_0, 0, 1; +S_0x283b210 .scope module, "potato" "TwoInMux" 3 161, 3 109, S_0x283b120; + .timescale -9 -12; +L_0x2adb0b0/d .functor NOT 1, L_0x2adb5a0, C4<0>, C4<0>, C4<0>; +L_0x2adb0b0 .delay (10000,10000,10000) L_0x2adb0b0/d; +L_0x2adb170/d .functor AND 1, L_0x2adaf80, L_0x2adb0b0, C4<1>, C4<1>; +L_0x2adb170 .delay (20000,20000,20000) L_0x2adb170/d; +L_0x2adb280/d .functor AND 1, L_0x2adabe0, L_0x2adb5a0, C4<1>, C4<1>; +L_0x2adb280 .delay (20000,20000,20000) L_0x2adb280/d; +L_0x2adb3d0/d .functor OR 1, L_0x2adb170, L_0x2adb280, C4<0>, C4<0>; +L_0x2adb3d0 .delay (20000,20000,20000) L_0x2adb3d0/d; +v0x283b300_0 .net "S", 0 0, L_0x2adb5a0; 1 drivers +v0x283b380_0 .alias "in0", 0 0, v0x283b820_0; +v0x283b420_0 .alias "in1", 0 0, v0x283b8a0_0; +v0x283b4c0_0 .net "nS", 0 0, L_0x2adb0b0; 1 drivers +v0x283b540_0 .net "out0", 0 0, L_0x2adb170; 1 drivers +v0x283b5e0_0 .net "out1", 0 0, L_0x2adb280; 1 drivers +v0x283b6c0_0 .alias "outfinal", 0 0, v0x283b950_0; +S_0x283a3f0 .scope generate, "andbits[8]" "andbits[8]" 3 231, 3 231, S_0x28293f0; + .timescale -9 -12; +P_0x283a4e8 .param/l "i" 3 231, +C4<01000>; +S_0x283a560 .scope module, "attempt" "AndNand" 3 233, 3 149, S_0x283a3f0; + .timescale -9 -12; +L_0x2adb880/d .functor NAND 1, L_0x2adb780, L_0x2adc200, C4<1>, C4<1>; +L_0x2adb880 .delay (10000,10000,10000) L_0x2adb880/d; +L_0x2adb9e0/d .functor NOT 1, L_0x2adb880, C4<0>, C4<0>, C4<0>; +L_0x2adb9e0 .delay (10000,10000,10000) L_0x2adb9e0/d; +v0x283aba0_0 .net "A", 0 0, L_0x2adb780; 1 drivers +v0x283ac60_0 .net "AandB", 0 0, L_0x2adb9e0; 1 drivers +v0x283ace0_0 .net "AnandB", 0 0, L_0x2adb880; 1 drivers +v0x283ad90_0 .net "AndNandOut", 0 0, L_0x2adbe30; 1 drivers +v0x283ae70_0 .net "B", 0 0, L_0x2adc200; 1 drivers +v0x283aef0_0 .alias "Command", 2 0, v0x295f7a0_0; +L_0x2adc000 .part v0x2960210_0, 0, 1; +S_0x283a650 .scope module, "potato" "TwoInMux" 3 161, 3 109, S_0x283a560; + .timescale -9 -12; +L_0x2adbb10/d .functor NOT 1, L_0x2adc000, C4<0>, C4<0>, C4<0>; +L_0x2adbb10 .delay (10000,10000,10000) L_0x2adbb10/d; +L_0x2adbbd0/d .functor AND 1, L_0x2adb9e0, L_0x2adbb10, C4<1>, C4<1>; +L_0x2adbbd0 .delay (20000,20000,20000) L_0x2adbbd0/d; +L_0x2adbce0/d .functor AND 1, L_0x2adb880, L_0x2adc000, C4<1>, C4<1>; +L_0x2adbce0 .delay (20000,20000,20000) L_0x2adbce0/d; +L_0x2adbe30/d .functor OR 1, L_0x2adbbd0, L_0x2adbce0, C4<0>, C4<0>; +L_0x2adbe30 .delay (20000,20000,20000) L_0x2adbe30/d; +v0x283a740_0 .net "S", 0 0, L_0x2adc000; 1 drivers +v0x283a7c0_0 .alias "in0", 0 0, v0x283ac60_0; +v0x283a860_0 .alias "in1", 0 0, v0x283ace0_0; +v0x283a900_0 .net "nS", 0 0, L_0x2adbb10; 1 drivers +v0x283a980_0 .net "out0", 0 0, L_0x2adbbd0; 1 drivers +v0x283aa20_0 .net "out1", 0 0, L_0x2adbce0; 1 drivers +v0x283ab00_0 .alias "outfinal", 0 0, v0x283ad90_0; +S_0x2839830 .scope generate, "andbits[9]" "andbits[9]" 3 231, 3 231, S_0x28293f0; + .timescale -9 -12; +P_0x2839928 .param/l "i" 3 231, +C4<01001>; +S_0x28399a0 .scope module, "attempt" "AndNand" 3 233, 3 149, S_0x2839830; + .timescale -9 -12; +L_0x2adc140/d .functor NAND 1, L_0x2adcbc0, L_0x2adc2f0, C4<1>, C4<1>; +L_0x2adc140 .delay (10000,10000,10000) L_0x2adc140/d; +L_0x2adc460/d .functor NOT 1, L_0x2adc140, C4<0>, C4<0>, C4<0>; +L_0x2adc460 .delay (10000,10000,10000) L_0x2adc460/d; +v0x2839fe0_0 .net "A", 0 0, L_0x2adcbc0; 1 drivers +v0x283a0a0_0 .net "AandB", 0 0, L_0x2adc460; 1 drivers +v0x283a120_0 .net "AnandB", 0 0, L_0x2adc140; 1 drivers +v0x283a1d0_0 .net "AndNandOut", 0 0, L_0x2adc8b0; 1 drivers +v0x283a2b0_0 .net "B", 0 0, L_0x2adc2f0; 1 drivers +v0x283a330_0 .alias "Command", 2 0, v0x295f7a0_0; +L_0x2adca80 .part v0x2960210_0, 0, 1; +S_0x2839a90 .scope module, "potato" "TwoInMux" 3 161, 3 109, S_0x28399a0; + .timescale -9 -12; +L_0x2adc590/d .functor NOT 1, L_0x2adca80, C4<0>, C4<0>, C4<0>; +L_0x2adc590 .delay (10000,10000,10000) L_0x2adc590/d; +L_0x2adc650/d .functor AND 1, L_0x2adc460, L_0x2adc590, C4<1>, C4<1>; +L_0x2adc650 .delay (20000,20000,20000) L_0x2adc650/d; +L_0x2adc760/d .functor AND 1, L_0x2adc140, L_0x2adca80, C4<1>, C4<1>; +L_0x2adc760 .delay (20000,20000,20000) L_0x2adc760/d; +L_0x2adc8b0/d .functor OR 1, L_0x2adc650, L_0x2adc760, C4<0>, C4<0>; +L_0x2adc8b0 .delay (20000,20000,20000) L_0x2adc8b0/d; +v0x2839b80_0 .net "S", 0 0, L_0x2adca80; 1 drivers +v0x2839c00_0 .alias "in0", 0 0, v0x283a0a0_0; +v0x2839ca0_0 .alias "in1", 0 0, v0x283a120_0; +v0x2839d40_0 .net "nS", 0 0, L_0x2adc590; 1 drivers +v0x2839dc0_0 .net "out0", 0 0, L_0x2adc650; 1 drivers +v0x2839e60_0 .net "out1", 0 0, L_0x2adc760; 1 drivers +v0x2839f40_0 .alias "outfinal", 0 0, v0x283a1d0_0; +S_0x2838c70 .scope generate, "andbits[10]" "andbits[10]" 3 231, 3 231, S_0x28293f0; + .timescale -9 -12; +P_0x2838d68 .param/l "i" 3 231, +C4<01010>; +S_0x2838de0 .scope module, "attempt" "AndNand" 3 233, 3 149, S_0x2838c70; + .timescale -9 -12; +L_0x2adcd90/d .functor NAND 1, L_0x2adcc60, L_0x2add580, C4<1>, C4<1>; +L_0x2adcd90 .delay (10000,10000,10000) L_0x2adcd90/d; +L_0x2adced0/d .functor NOT 1, L_0x2adcd90, C4<0>, C4<0>, C4<0>; +L_0x2adced0 .delay (10000,10000,10000) L_0x2adced0/d; +v0x2839420_0 .net "A", 0 0, L_0x2adcc60; 1 drivers +v0x28394e0_0 .net "AandB", 0 0, L_0x2adced0; 1 drivers +v0x2839560_0 .net "AnandB", 0 0, L_0x2adcd90; 1 drivers +v0x2839610_0 .net "AndNandOut", 0 0, L_0x2add1c0; 1 drivers +v0x28396f0_0 .net "B", 0 0, L_0x2add580; 1 drivers +v0x2839770_0 .alias "Command", 2 0, v0x295f7a0_0; +L_0x2add350 .part v0x2960210_0, 0, 1; +S_0x2838ed0 .scope module, "potato" "TwoInMux" 3 161, 3 109, S_0x2838de0; + .timescale -9 -12; +L_0x2ad9840/d .functor NOT 1, L_0x2add350, C4<0>, C4<0>, C4<0>; +L_0x2ad9840 .delay (10000,10000,10000) L_0x2ad9840/d; +L_0x2adcf90/d .functor AND 1, L_0x2adced0, L_0x2ad9840, C4<1>, C4<1>; +L_0x2adcf90 .delay (20000,20000,20000) L_0x2adcf90/d; +L_0x2add090/d .functor AND 1, L_0x2adcd90, L_0x2add350, C4<1>, C4<1>; +L_0x2add090 .delay (20000,20000,20000) L_0x2add090/d; +L_0x2add1c0/d .functor OR 1, L_0x2adcf90, L_0x2add090, C4<0>, C4<0>; +L_0x2add1c0 .delay (20000,20000,20000) L_0x2add1c0/d; +v0x2838fc0_0 .net "S", 0 0, L_0x2add350; 1 drivers +v0x2839040_0 .alias "in0", 0 0, v0x28394e0_0; +v0x28390e0_0 .alias "in1", 0 0, v0x2839560_0; +v0x2839180_0 .net "nS", 0 0, L_0x2ad9840; 1 drivers +v0x2839200_0 .net "out0", 0 0, L_0x2adcf90; 1 drivers +v0x28392a0_0 .net "out1", 0 0, L_0x2add090; 1 drivers +v0x2839380_0 .alias "outfinal", 0 0, v0x2839610_0; +S_0x28380b0 .scope generate, "andbits[11]" "andbits[11]" 3 231, 3 231, S_0x28293f0; + .timescale -9 -12; +P_0x28381a8 .param/l "i" 3 231, +C4<01011>; +S_0x2838220 .scope module, "attempt" "AndNand" 3 233, 3 149, S_0x28380b0; + .timescale -9 -12; +L_0x2add490/d .functor NAND 1, L_0x2adde40, L_0x2add670, C4<1>, C4<1>; +L_0x2add490 .delay (10000,10000,10000) L_0x2add490/d; +L_0x2add7c0/d .functor NOT 1, L_0x2add490, C4<0>, C4<0>, C4<0>; +L_0x2add7c0 .delay (10000,10000,10000) L_0x2add7c0/d; +v0x2838860_0 .net "A", 0 0, L_0x2adde40; 1 drivers +v0x2838920_0 .net "AandB", 0 0, L_0x2add7c0; 1 drivers +v0x28389a0_0 .net "AnandB", 0 0, L_0x2add490; 1 drivers +v0x2838a50_0 .net "AndNandOut", 0 0, L_0x2addb70; 1 drivers +v0x2838b30_0 .net "B", 0 0, L_0x2add670; 1 drivers +v0x2838bb0_0 .alias "Command", 2 0, v0x295f7a0_0; +L_0x2addd00 .part v0x2960210_0, 0, 1; +S_0x2838310 .scope module, "potato" "TwoInMux" 3 161, 3 109, S_0x2838220; + .timescale -9 -12; +L_0x2add8b0/d .functor NOT 1, L_0x2addd00, C4<0>, C4<0>, C4<0>; +L_0x2add8b0 .delay (10000,10000,10000) L_0x2add8b0/d; +L_0x2add950/d .functor AND 1, L_0x2add7c0, L_0x2add8b0, C4<1>, C4<1>; +L_0x2add950 .delay (20000,20000,20000) L_0x2add950/d; +L_0x2adda40/d .functor AND 1, L_0x2add490, L_0x2addd00, C4<1>, C4<1>; +L_0x2adda40 .delay (20000,20000,20000) L_0x2adda40/d; +L_0x2addb70/d .functor OR 1, L_0x2add950, L_0x2adda40, C4<0>, C4<0>; +L_0x2addb70 .delay (20000,20000,20000) L_0x2addb70/d; +v0x2838400_0 .net "S", 0 0, L_0x2addd00; 1 drivers +v0x2838480_0 .alias "in0", 0 0, v0x2838920_0; +v0x2838520_0 .alias "in1", 0 0, v0x28389a0_0; +v0x28385c0_0 .net "nS", 0 0, L_0x2add8b0; 1 drivers +v0x2838640_0 .net "out0", 0 0, L_0x2add950; 1 drivers +v0x28386e0_0 .net "out1", 0 0, L_0x2adda40; 1 drivers +v0x28387c0_0 .alias "outfinal", 0 0, v0x2838a50_0; +S_0x28374f0 .scope generate, "andbits[12]" "andbits[12]" 3 231, 3 231, S_0x28293f0; + .timescale -9 -12; +P_0x28375e8 .param/l "i" 3 231, +C4<01100>; +S_0x2837660 .scope module, "attempt" "AndNand" 3 233, 3 149, S_0x28374f0; + .timescale -9 -12; +L_0x2addff0/d .functor NAND 1, L_0x2addee0, L_0x2ade910, C4<1>, C4<1>; +L_0x2addff0 .delay (10000,10000,10000) L_0x2addff0/d; +L_0x2ade130/d .functor NOT 1, L_0x2addff0, C4<0>, C4<0>, C4<0>; +L_0x2ade130 .delay (10000,10000,10000) L_0x2ade130/d; +v0x2837ca0_0 .net "A", 0 0, L_0x2addee0; 1 drivers +v0x2837d60_0 .net "AandB", 0 0, L_0x2ade130; 1 drivers +v0x2837de0_0 .net "AnandB", 0 0, L_0x2addff0; 1 drivers +v0x2837e90_0 .net "AndNandOut", 0 0, L_0x2ade4e0; 1 drivers +v0x2837f70_0 .net "B", 0 0, L_0x2ade910; 1 drivers +v0x2837ff0_0 .alias "Command", 2 0, v0x295f7a0_0; +L_0x2ade6b0 .part v0x2960210_0, 0, 1; +S_0x2837750 .scope module, "potato" "TwoInMux" 3 161, 3 109, S_0x2837660; + .timescale -9 -12; +L_0x2ade220/d .functor NOT 1, L_0x2ade6b0, C4<0>, C4<0>, C4<0>; +L_0x2ade220 .delay (10000,10000,10000) L_0x2ade220/d; +L_0x2ade2c0/d .functor AND 1, L_0x2ade130, L_0x2ade220, C4<1>, C4<1>; +L_0x2ade2c0 .delay (20000,20000,20000) L_0x2ade2c0/d; +L_0x2ade3b0/d .functor AND 1, L_0x2addff0, L_0x2ade6b0, C4<1>, C4<1>; +L_0x2ade3b0 .delay (20000,20000,20000) L_0x2ade3b0/d; +L_0x2ade4e0/d .functor OR 1, L_0x2ade2c0, L_0x2ade3b0, C4<0>, C4<0>; +L_0x2ade4e0 .delay (20000,20000,20000) L_0x2ade4e0/d; +v0x2837840_0 .net "S", 0 0, L_0x2ade6b0; 1 drivers +v0x28378c0_0 .alias "in0", 0 0, v0x2837d60_0; +v0x2837960_0 .alias "in1", 0 0, v0x2837de0_0; +v0x2837a00_0 .net "nS", 0 0, L_0x2ade220; 1 drivers +v0x2837a80_0 .net "out0", 0 0, L_0x2ade2c0; 1 drivers +v0x2837b20_0 .net "out1", 0 0, L_0x2ade3b0; 1 drivers +v0x2837c00_0 .alias "outfinal", 0 0, v0x2837e90_0; +S_0x2836930 .scope generate, "andbits[13]" "andbits[13]" 3 231, 3 231, S_0x28293f0; + .timescale -9 -12; +P_0x2836a28 .param/l "i" 3 231, +C4<01101>; +S_0x2836aa0 .scope module, "attempt" "AndNand" 3 233, 3 149, S_0x2836930; + .timescale -9 -12; +L_0x2ade7f0/d .functor NAND 1, L_0x2adf270, L_0x2ade9b0, C4<1>, C4<1>; +L_0x2ade7f0 .delay (10000,10000,10000) L_0x2ade7f0/d; +L_0x2adeb30/d .functor NOT 1, L_0x2ade7f0, C4<0>, C4<0>, C4<0>; +L_0x2adeb30 .delay (10000,10000,10000) L_0x2adeb30/d; +v0x28370e0_0 .net "A", 0 0, L_0x2adf270; 1 drivers +v0x28371a0_0 .net "AandB", 0 0, L_0x2adeb30; 1 drivers +v0x2837220_0 .net "AnandB", 0 0, L_0x2ade7f0; 1 drivers +v0x28372d0_0 .net "AndNandOut", 0 0, L_0x2adef60; 1 drivers +v0x28373b0_0 .net "B", 0 0, L_0x2ade9b0; 1 drivers +v0x2837430_0 .alias "Command", 2 0, v0x295f7a0_0; +L_0x2adf130 .part v0x2960210_0, 0, 1; +S_0x2836b90 .scope module, "potato" "TwoInMux" 3 161, 3 109, S_0x2836aa0; + .timescale -9 -12; +L_0x2adec40/d .functor NOT 1, L_0x2adf130, C4<0>, C4<0>, C4<0>; +L_0x2adec40 .delay (10000,10000,10000) L_0x2adec40/d; +L_0x2aded00/d .functor AND 1, L_0x2adeb30, L_0x2adec40, C4<1>, C4<1>; +L_0x2aded00 .delay (20000,20000,20000) L_0x2aded00/d; +L_0x2adee10/d .functor AND 1, L_0x2ade7f0, L_0x2adf130, C4<1>, C4<1>; +L_0x2adee10 .delay (20000,20000,20000) L_0x2adee10/d; +L_0x2adef60/d .functor OR 1, L_0x2aded00, L_0x2adee10, C4<0>, C4<0>; +L_0x2adef60 .delay (20000,20000,20000) L_0x2adef60/d; +v0x2836c80_0 .net "S", 0 0, L_0x2adf130; 1 drivers +v0x2836d00_0 .alias "in0", 0 0, v0x28371a0_0; +v0x2836da0_0 .alias "in1", 0 0, v0x2837220_0; +v0x2836e40_0 .net "nS", 0 0, L_0x2adec40; 1 drivers +v0x2836ec0_0 .net "out0", 0 0, L_0x2aded00; 1 drivers +v0x2836f60_0 .net "out1", 0 0, L_0x2adee10; 1 drivers +v0x2837040_0 .alias "outfinal", 0 0, v0x28372d0_0; +S_0x2835d70 .scope generate, "andbits[14]" "andbits[14]" 3 231, 3 231, S_0x28293f0; + .timescale -9 -12; +P_0x2835e68 .param/l "i" 3 231, +C4<01110>; +S_0x2835ee0 .scope module, "attempt" "AndNand" 3 233, 3 149, S_0x2835d70; + .timescale -9 -12; +L_0x2adf450/d .functor NAND 1, L_0x2adf310, L_0x2adf3b0, C4<1>, C4<1>; +L_0x2adf450 .delay (10000,10000,10000) L_0x2adf450/d; +L_0x2adf590/d .functor NOT 1, L_0x2adf450, C4<0>, C4<0>, C4<0>; +L_0x2adf590 .delay (10000,10000,10000) L_0x2adf590/d; +v0x2836520_0 .net "A", 0 0, L_0x2adf310; 1 drivers +v0x28365e0_0 .net "AandB", 0 0, L_0x2adf590; 1 drivers +v0x2836660_0 .net "AnandB", 0 0, L_0x2adf450; 1 drivers +v0x2836710_0 .net "AndNandOut", 0 0, L_0x2adf9c0; 1 drivers +v0x28367f0_0 .net "B", 0 0, L_0x2adf3b0; 1 drivers +v0x2836870_0 .alias "Command", 2 0, v0x295f7a0_0; +L_0x2adfb90 .part v0x2960210_0, 0, 1; +S_0x2835fd0 .scope module, "potato" "TwoInMux" 3 161, 3 109, S_0x2835ee0; + .timescale -9 -12; +L_0x2adf6a0/d .functor NOT 1, L_0x2adfb90, C4<0>, C4<0>, C4<0>; +L_0x2adf6a0 .delay (10000,10000,10000) L_0x2adf6a0/d; +L_0x2adf760/d .functor AND 1, L_0x2adf590, L_0x2adf6a0, C4<1>, C4<1>; +L_0x2adf760 .delay (20000,20000,20000) L_0x2adf760/d; +L_0x2adf870/d .functor AND 1, L_0x2adf450, L_0x2adfb90, C4<1>, C4<1>; +L_0x2adf870 .delay (20000,20000,20000) L_0x2adf870/d; +L_0x2adf9c0/d .functor OR 1, L_0x2adf760, L_0x2adf870, C4<0>, C4<0>; +L_0x2adf9c0 .delay (20000,20000,20000) L_0x2adf9c0/d; +v0x28360c0_0 .net "S", 0 0, L_0x2adfb90; 1 drivers +v0x2836140_0 .alias "in0", 0 0, v0x28365e0_0; +v0x28361e0_0 .alias "in1", 0 0, v0x2836660_0; +v0x2836280_0 .net "nS", 0 0, L_0x2adf6a0; 1 drivers +v0x2836300_0 .net "out0", 0 0, L_0x2adf760; 1 drivers +v0x28363a0_0 .net "out1", 0 0, L_0x2adf870; 1 drivers +v0x2836480_0 .alias "outfinal", 0 0, v0x2836710_0; +S_0x28351b0 .scope generate, "andbits[15]" "andbits[15]" 3 231, 3 231, S_0x28293f0; + .timescale -9 -12; +P_0x28352a8 .param/l "i" 3 231, +C4<01111>; +S_0x2835320 .scope module, "attempt" "AndNand" 3 233, 3 149, S_0x28351b0; + .timescale -9 -12; +L_0x2adfcd0/d .functor NAND 1, L_0x2ae0740, L_0x2adfe70, C4<1>, C4<1>; +L_0x2adfcd0 .delay (10000,10000,10000) L_0x2adfcd0/d; +L_0x2ae0020/d .functor NOT 1, L_0x2adfcd0, C4<0>, C4<0>, C4<0>; +L_0x2ae0020 .delay (10000,10000,10000) L_0x2ae0020/d; +v0x2835960_0 .net "A", 0 0, L_0x2ae0740; 1 drivers +v0x2835a20_0 .net "AandB", 0 0, L_0x2ae0020; 1 drivers +v0x2835aa0_0 .net "AnandB", 0 0, L_0x2adfcd0; 1 drivers +v0x2835b50_0 .net "AndNandOut", 0 0, L_0x2ae0430; 1 drivers +v0x2835c30_0 .net "B", 0 0, L_0x2adfe70; 1 drivers +v0x2835cb0_0 .alias "Command", 2 0, v0x295f7a0_0; +L_0x2ae0600 .part v0x2960210_0, 0, 1; +S_0x2835410 .scope module, "potato" "TwoInMux" 3 161, 3 109, S_0x2835320; + .timescale -9 -12; +L_0x2ae0110/d .functor NOT 1, L_0x2ae0600, C4<0>, C4<0>, C4<0>; +L_0x2ae0110 .delay (10000,10000,10000) L_0x2ae0110/d; +L_0x2ae01d0/d .functor AND 1, L_0x2ae0020, L_0x2ae0110, C4<1>, C4<1>; +L_0x2ae01d0 .delay (20000,20000,20000) L_0x2ae01d0/d; +L_0x2ae02e0/d .functor AND 1, L_0x2adfcd0, L_0x2ae0600, C4<1>, C4<1>; +L_0x2ae02e0 .delay (20000,20000,20000) L_0x2ae02e0/d; +L_0x2ae0430/d .functor OR 1, L_0x2ae01d0, L_0x2ae02e0, C4<0>, C4<0>; +L_0x2ae0430 .delay (20000,20000,20000) L_0x2ae0430/d; +v0x2835500_0 .net "S", 0 0, L_0x2ae0600; 1 drivers +v0x2835580_0 .alias "in0", 0 0, v0x2835a20_0; +v0x2835620_0 .alias "in1", 0 0, v0x2835aa0_0; +v0x28356c0_0 .net "nS", 0 0, L_0x2ae0110; 1 drivers +v0x2835740_0 .net "out0", 0 0, L_0x2ae01d0; 1 drivers +v0x28357e0_0 .net "out1", 0 0, L_0x2ae02e0; 1 drivers +v0x28358c0_0 .alias "outfinal", 0 0, v0x2835b50_0; +S_0x28345f0 .scope generate, "andbits[16]" "andbits[16]" 3 231, 3 231, S_0x28293f0; + .timescale -9 -12; +P_0x28346e8 .param/l "i" 3 231, +C4<010000>; +S_0x2834760 .scope module, "attempt" "AndNand" 3 233, 3 149, S_0x28345f0; + .timescale -9 -12; +L_0x2adff60/d .functor NAND 1, L_0x2ae07e0, L_0x2ae0880, C4<1>, C4<1>; +L_0x2adff60 .delay (10000,10000,10000) L_0x2adff60/d; +L_0x2ae0a50/d .functor NOT 1, L_0x2adff60, C4<0>, C4<0>, C4<0>; +L_0x2ae0a50 .delay (10000,10000,10000) L_0x2ae0a50/d; +v0x2834da0_0 .net "A", 0 0, L_0x2ae07e0; 1 drivers +v0x2834e60_0 .net "AandB", 0 0, L_0x2ae0a50; 1 drivers +v0x2834ee0_0 .net "AnandB", 0 0, L_0x2adff60; 1 drivers +v0x2834f90_0 .net "AndNandOut", 0 0, L_0x2ae0ea0; 1 drivers +v0x2835070_0 .net "B", 0 0, L_0x2ae0880; 1 drivers +v0x28350f0_0 .alias "Command", 2 0, v0x295f7a0_0; +L_0x2ae1070 .part v0x2960210_0, 0, 1; +S_0x2834850 .scope module, "potato" "TwoInMux" 3 161, 3 109, S_0x2834760; + .timescale -9 -12; +L_0x2ae0b80/d .functor NOT 1, L_0x2ae1070, C4<0>, C4<0>, C4<0>; +L_0x2ae0b80 .delay (10000,10000,10000) L_0x2ae0b80/d; +L_0x2ae0c40/d .functor AND 1, L_0x2ae0a50, L_0x2ae0b80, C4<1>, C4<1>; +L_0x2ae0c40 .delay (20000,20000,20000) L_0x2ae0c40/d; +L_0x2ae0d50/d .functor AND 1, L_0x2adff60, L_0x2ae1070, C4<1>, C4<1>; +L_0x2ae0d50 .delay (20000,20000,20000) L_0x2ae0d50/d; +L_0x2ae0ea0/d .functor OR 1, L_0x2ae0c40, L_0x2ae0d50, C4<0>, C4<0>; +L_0x2ae0ea0 .delay (20000,20000,20000) L_0x2ae0ea0/d; +v0x2834940_0 .net "S", 0 0, L_0x2ae1070; 1 drivers +v0x28349c0_0 .alias "in0", 0 0, v0x2834e60_0; +v0x2834a60_0 .alias "in1", 0 0, v0x2834ee0_0; +v0x2834b00_0 .net "nS", 0 0, L_0x2ae0b80; 1 drivers +v0x2834b80_0 .net "out0", 0 0, L_0x2ae0c40; 1 drivers +v0x2834c20_0 .net "out1", 0 0, L_0x2ae0d50; 1 drivers +v0x2834d00_0 .alias "outfinal", 0 0, v0x2834f90_0; +S_0x2833a30 .scope generate, "andbits[17]" "andbits[17]" 3 231, 3 231, S_0x28293f0; + .timescale -9 -12; +P_0x2833b28 .param/l "i" 3 231, +C4<010001>; +S_0x2833ba0 .scope module, "attempt" "AndNand" 3 233, 3 149, S_0x2833a30; + .timescale -9 -12; +L_0x2ae11b0/d .functor NAND 1, L_0x2ae1c30, L_0x2ae1380, C4<1>, C4<1>; +L_0x2ae11b0 .delay (10000,10000,10000) L_0x2ae11b0/d; +L_0x2ae1510/d .functor NOT 1, L_0x2ae11b0, C4<0>, C4<0>, C4<0>; +L_0x2ae1510 .delay (10000,10000,10000) L_0x2ae1510/d; +v0x28341e0_0 .net "A", 0 0, L_0x2ae1c30; 1 drivers +v0x28342a0_0 .net "AandB", 0 0, L_0x2ae1510; 1 drivers +v0x2834320_0 .net "AnandB", 0 0, L_0x2ae11b0; 1 drivers +v0x28343d0_0 .net "AndNandOut", 0 0, L_0x2ae1920; 1 drivers +v0x28344b0_0 .net "B", 0 0, L_0x2ae1380; 1 drivers +v0x2834530_0 .alias "Command", 2 0, v0x295f7a0_0; +L_0x2ae1af0 .part v0x2960210_0, 0, 1; +S_0x2833c90 .scope module, "potato" "TwoInMux" 3 161, 3 109, S_0x2833ba0; + .timescale -9 -12; +L_0x2ae1600/d .functor NOT 1, L_0x2ae1af0, C4<0>, C4<0>, C4<0>; +L_0x2ae1600 .delay (10000,10000,10000) L_0x2ae1600/d; +L_0x2ae16c0/d .functor AND 1, L_0x2ae1510, L_0x2ae1600, C4<1>, C4<1>; +L_0x2ae16c0 .delay (20000,20000,20000) L_0x2ae16c0/d; +L_0x2ae17d0/d .functor AND 1, L_0x2ae11b0, L_0x2ae1af0, C4<1>, C4<1>; +L_0x2ae17d0 .delay (20000,20000,20000) L_0x2ae17d0/d; +L_0x2ae1920/d .functor OR 1, L_0x2ae16c0, L_0x2ae17d0, C4<0>, C4<0>; +L_0x2ae1920 .delay (20000,20000,20000) L_0x2ae1920/d; +v0x2833d80_0 .net "S", 0 0, L_0x2ae1af0; 1 drivers +v0x2833e00_0 .alias "in0", 0 0, v0x28342a0_0; +v0x2833ea0_0 .alias "in1", 0 0, v0x2834320_0; +v0x2833f40_0 .net "nS", 0 0, L_0x2ae1600; 1 drivers +v0x2833fc0_0 .net "out0", 0 0, L_0x2ae16c0; 1 drivers +v0x2834060_0 .net "out1", 0 0, L_0x2ae17d0; 1 drivers +v0x2834140_0 .alias "outfinal", 0 0, v0x28343d0_0; +S_0x2832e70 .scope generate, "andbits[18]" "andbits[18]" 3 231, 3 231, S_0x28293f0; + .timescale -9 -12; +P_0x2832f68 .param/l "i" 3 231, +C4<010010>; +S_0x2832fe0 .scope module, "attempt" "AndNand" 3 233, 3 149, S_0x2832e70; + .timescale -9 -12; +L_0x2ae1470/d .functor NAND 1, L_0x2ae1cd0, L_0x2ae1d70, C4<1>, C4<1>; +L_0x2ae1470 .delay (10000,10000,10000) L_0x2ae1470/d; +L_0x2ae1f50/d .functor NOT 1, L_0x2ae1470, C4<0>, C4<0>, C4<0>; +L_0x2ae1f50 .delay (10000,10000,10000) L_0x2ae1f50/d; +v0x2833620_0 .net "A", 0 0, L_0x2ae1cd0; 1 drivers +v0x28336e0_0 .net "AandB", 0 0, L_0x2ae1f50; 1 drivers +v0x2833760_0 .net "AnandB", 0 0, L_0x2ae1470; 1 drivers +v0x2833810_0 .net "AndNandOut", 0 0, L_0x2ae2380; 1 drivers +v0x28338f0_0 .net "B", 0 0, L_0x2ae1d70; 1 drivers +v0x2833970_0 .alias "Command", 2 0, v0x295f7a0_0; +L_0x2ae2550 .part v0x2960210_0, 0, 1; +S_0x28330d0 .scope module, "potato" "TwoInMux" 3 161, 3 109, S_0x2832fe0; + .timescale -9 -12; +L_0x2ae2060/d .functor NOT 1, L_0x2ae2550, C4<0>, C4<0>, C4<0>; +L_0x2ae2060 .delay (10000,10000,10000) L_0x2ae2060/d; +L_0x2ae2120/d .functor AND 1, L_0x2ae1f50, L_0x2ae2060, C4<1>, C4<1>; +L_0x2ae2120 .delay (20000,20000,20000) L_0x2ae2120/d; +L_0x2ae2230/d .functor AND 1, L_0x2ae1470, L_0x2ae2550, C4<1>, C4<1>; +L_0x2ae2230 .delay (20000,20000,20000) L_0x2ae2230/d; +L_0x2ae2380/d .functor OR 1, L_0x2ae2120, L_0x2ae2230, C4<0>, C4<0>; +L_0x2ae2380 .delay (20000,20000,20000) L_0x2ae2380/d; +v0x28331c0_0 .net "S", 0 0, L_0x2ae2550; 1 drivers +v0x2833240_0 .alias "in0", 0 0, v0x28336e0_0; +v0x28332e0_0 .alias "in1", 0 0, v0x2833760_0; +v0x2833380_0 .net "nS", 0 0, L_0x2ae2060; 1 drivers +v0x2833400_0 .net "out0", 0 0, L_0x2ae2120; 1 drivers +v0x28334a0_0 .net "out1", 0 0, L_0x2ae2230; 1 drivers +v0x2833580_0 .alias "outfinal", 0 0, v0x2833810_0; +S_0x28322b0 .scope generate, "andbits[19]" "andbits[19]" 3 231, 3 231, S_0x28293f0; + .timescale -9 -12; +P_0x28323a8 .param/l "i" 3 231, +C4<010011>; +S_0x2832420 .scope module, "attempt" "AndNand" 3 233, 3 149, S_0x28322b0; + .timescale -9 -12; +L_0x2ae2850/d .functor NAND 1, L_0x2ae3110, L_0x2ae2690, C4<1>, C4<1>; +L_0x2ae2850 .delay (10000,10000,10000) L_0x2ae2850/d; +L_0x2ae29b0/d .functor NOT 1, L_0x2ae2850, C4<0>, C4<0>, C4<0>; +L_0x2ae29b0 .delay (10000,10000,10000) L_0x2ae29b0/d; +v0x2832a60_0 .net "A", 0 0, L_0x2ae3110; 1 drivers +v0x2832b20_0 .net "AandB", 0 0, L_0x2ae29b0; 1 drivers +v0x2832ba0_0 .net "AnandB", 0 0, L_0x2ae2850; 1 drivers +v0x2832c50_0 .net "AndNandOut", 0 0, L_0x2ae2e00; 1 drivers +v0x2832d30_0 .net "B", 0 0, L_0x2ae2690; 1 drivers +v0x2832db0_0 .alias "Command", 2 0, v0x295f7a0_0; +L_0x2ae2fd0 .part v0x2960210_0, 0, 1; +S_0x2832510 .scope module, "potato" "TwoInMux" 3 161, 3 109, S_0x2832420; + .timescale -9 -12; +L_0x2ae2ae0/d .functor NOT 1, L_0x2ae2fd0, C4<0>, C4<0>, C4<0>; +L_0x2ae2ae0 .delay (10000,10000,10000) L_0x2ae2ae0/d; +L_0x2ae2ba0/d .functor AND 1, L_0x2ae29b0, L_0x2ae2ae0, C4<1>, C4<1>; +L_0x2ae2ba0 .delay (20000,20000,20000) L_0x2ae2ba0/d; +L_0x2ae2cb0/d .functor AND 1, L_0x2ae2850, L_0x2ae2fd0, C4<1>, C4<1>; +L_0x2ae2cb0 .delay (20000,20000,20000) L_0x2ae2cb0/d; +L_0x2ae2e00/d .functor OR 1, L_0x2ae2ba0, L_0x2ae2cb0, C4<0>, C4<0>; +L_0x2ae2e00 .delay (20000,20000,20000) L_0x2ae2e00/d; +v0x2832600_0 .net "S", 0 0, L_0x2ae2fd0; 1 drivers +v0x2832680_0 .alias "in0", 0 0, v0x2832b20_0; +v0x2832720_0 .alias "in1", 0 0, v0x2832ba0_0; +v0x28327c0_0 .net "nS", 0 0, L_0x2ae2ae0; 1 drivers +v0x2832840_0 .net "out0", 0 0, L_0x2ae2ba0; 1 drivers +v0x28328e0_0 .net "out1", 0 0, L_0x2ae2cb0; 1 drivers +v0x28329c0_0 .alias "outfinal", 0 0, v0x2832c50_0; +S_0x28316f0 .scope generate, "andbits[20]" "andbits[20]" 3 231, 3 231, S_0x28293f0; + .timescale -9 -12; +P_0x28317e8 .param/l "i" 3 231, +C4<010100>; +S_0x2831860 .scope module, "attempt" "AndNand" 3 233, 3 149, S_0x28316f0; + .timescale -9 -12; +L_0x2ae2780/d .functor NAND 1, L_0x2ae31b0, L_0x2ae3250, C4<1>, C4<1>; +L_0x2ae2780 .delay (10000,10000,10000) L_0x2ae2780/d; +L_0x2ae3410/d .functor NOT 1, L_0x2ae2780, C4<0>, C4<0>, C4<0>; +L_0x2ae3410 .delay (10000,10000,10000) L_0x2ae3410/d; +v0x2831ea0_0 .net "A", 0 0, L_0x2ae31b0; 1 drivers +v0x2831f60_0 .net "AandB", 0 0, L_0x2ae3410; 1 drivers +v0x2831fe0_0 .net "AnandB", 0 0, L_0x2ae2780; 1 drivers +v0x2832090_0 .net "AndNandOut", 0 0, L_0x2ae3860; 1 drivers +v0x2832170_0 .net "B", 0 0, L_0x2ae3250; 1 drivers +v0x28321f0_0 .alias "Command", 2 0, v0x295f7a0_0; +L_0x2ae3a30 .part v0x2960210_0, 0, 1; +S_0x2831950 .scope module, "potato" "TwoInMux" 3 161, 3 109, S_0x2831860; + .timescale -9 -12; +L_0x2ae3540/d .functor NOT 1, L_0x2ae3a30, C4<0>, C4<0>, C4<0>; +L_0x2ae3540 .delay (10000,10000,10000) L_0x2ae3540/d; +L_0x2ae3600/d .functor AND 1, L_0x2ae3410, L_0x2ae3540, C4<1>, C4<1>; +L_0x2ae3600 .delay (20000,20000,20000) L_0x2ae3600/d; +L_0x2ae3710/d .functor AND 1, L_0x2ae2780, L_0x2ae3a30, C4<1>, C4<1>; +L_0x2ae3710 .delay (20000,20000,20000) L_0x2ae3710/d; +L_0x2ae3860/d .functor OR 1, L_0x2ae3600, L_0x2ae3710, C4<0>, C4<0>; +L_0x2ae3860 .delay (20000,20000,20000) L_0x2ae3860/d; +v0x2831a40_0 .net "S", 0 0, L_0x2ae3a30; 1 drivers +v0x2831ac0_0 .alias "in0", 0 0, v0x2831f60_0; +v0x2831b60_0 .alias "in1", 0 0, v0x2831fe0_0; +v0x2831c00_0 .net "nS", 0 0, L_0x2ae3540; 1 drivers +v0x2831c80_0 .net "out0", 0 0, L_0x2ae3600; 1 drivers +v0x2831d20_0 .net "out1", 0 0, L_0x2ae3710; 1 drivers +v0x2831e00_0 .alias "outfinal", 0 0, v0x2832090_0; +S_0x2830b30 .scope generate, "andbits[21]" "andbits[21]" 3 231, 3 231, S_0x28293f0; + .timescale -9 -12; +P_0x2830c28 .param/l "i" 3 231, +C4<010101>; +S_0x2830ca0 .scope module, "attempt" "AndNand" 3 233, 3 149, S_0x2830b30; + .timescale -9 -12; +L_0x2ae3d60/d .functor NAND 1, L_0x2ae45e0, L_0x2ae3b70, C4<1>, C4<1>; +L_0x2ae3d60 .delay (10000,10000,10000) L_0x2ae3d60/d; +L_0x2ae3ea0/d .functor NOT 1, L_0x2ae3d60, C4<0>, C4<0>, C4<0>; +L_0x2ae3ea0 .delay (10000,10000,10000) L_0x2ae3ea0/d; +v0x28312e0_0 .net "A", 0 0, L_0x2ae45e0; 1 drivers +v0x28313a0_0 .net "AandB", 0 0, L_0x2ae3ea0; 1 drivers +v0x2831420_0 .net "AnandB", 0 0, L_0x2ae3d60; 1 drivers +v0x28314d0_0 .net "AndNandOut", 0 0, L_0x2ae42d0; 1 drivers +v0x28315b0_0 .net "B", 0 0, L_0x2ae3b70; 1 drivers +v0x2831630_0 .alias "Command", 2 0, v0x295f7a0_0; +L_0x2ae44a0 .part v0x2960210_0, 0, 1; +S_0x2830d90 .scope module, "potato" "TwoInMux" 3 161, 3 109, S_0x2830ca0; + .timescale -9 -12; +L_0x2ae3fb0/d .functor NOT 1, L_0x2ae44a0, C4<0>, C4<0>, C4<0>; +L_0x2ae3fb0 .delay (10000,10000,10000) L_0x2ae3fb0/d; +L_0x2ae4070/d .functor AND 1, L_0x2ae3ea0, L_0x2ae3fb0, C4<1>, C4<1>; +L_0x2ae4070 .delay (20000,20000,20000) L_0x2ae4070/d; +L_0x2ae4180/d .functor AND 1, L_0x2ae3d60, L_0x2ae44a0, C4<1>, C4<1>; +L_0x2ae4180 .delay (20000,20000,20000) L_0x2ae4180/d; +L_0x2ae42d0/d .functor OR 1, L_0x2ae4070, L_0x2ae4180, C4<0>, C4<0>; +L_0x2ae42d0 .delay (20000,20000,20000) L_0x2ae42d0/d; +v0x2830e80_0 .net "S", 0 0, L_0x2ae44a0; 1 drivers +v0x2830f00_0 .alias "in0", 0 0, v0x28313a0_0; +v0x2830fa0_0 .alias "in1", 0 0, v0x2831420_0; +v0x2831040_0 .net "nS", 0 0, L_0x2ae3fb0; 1 drivers +v0x28310c0_0 .net "out0", 0 0, L_0x2ae4070; 1 drivers +v0x2831160_0 .net "out1", 0 0, L_0x2ae4180; 1 drivers +v0x2831240_0 .alias "outfinal", 0 0, v0x28314d0_0; +S_0x282ff70 .scope generate, "andbits[22]" "andbits[22]" 3 231, 3 231, S_0x28293f0; + .timescale -9 -12; +P_0x2830068 .param/l "i" 3 231, +C4<010110>; +S_0x28300e0 .scope module, "attempt" "AndNand" 3 233, 3 149, S_0x282ff70; + .timescale -9 -12; +L_0x2ae3c60/d .functor NAND 1, L_0x2ae4680, L_0x2ae4720, C4<1>, C4<1>; +L_0x2ae3c60 .delay (10000,10000,10000) L_0x2ae3c60/d; +L_0x2ae4910/d .functor NOT 1, L_0x2ae3c60, C4<0>, C4<0>, C4<0>; +L_0x2ae4910 .delay (10000,10000,10000) L_0x2ae4910/d; +v0x2830720_0 .net "A", 0 0, L_0x2ae4680; 1 drivers +v0x28307e0_0 .net "AandB", 0 0, L_0x2ae4910; 1 drivers +v0x2830860_0 .net "AnandB", 0 0, L_0x2ae3c60; 1 drivers +v0x2830910_0 .net "AndNandOut", 0 0, L_0x2ae4d40; 1 drivers +v0x28309f0_0 .net "B", 0 0, L_0x2ae4720; 1 drivers +v0x2830a70_0 .alias "Command", 2 0, v0x295f7a0_0; +L_0x2ae4f10 .part v0x2960210_0, 0, 1; +S_0x28301d0 .scope module, "potato" "TwoInMux" 3 161, 3 109, S_0x28300e0; + .timescale -9 -12; +L_0x2ae4a20/d .functor NOT 1, L_0x2ae4f10, C4<0>, C4<0>, C4<0>; +L_0x2ae4a20 .delay (10000,10000,10000) L_0x2ae4a20/d; +L_0x2ae4ae0/d .functor AND 1, L_0x2ae4910, L_0x2ae4a20, C4<1>, C4<1>; +L_0x2ae4ae0 .delay (20000,20000,20000) L_0x2ae4ae0/d; +L_0x2ae4bf0/d .functor AND 1, L_0x2ae3c60, L_0x2ae4f10, C4<1>, C4<1>; +L_0x2ae4bf0 .delay (20000,20000,20000) L_0x2ae4bf0/d; +L_0x2ae4d40/d .functor OR 1, L_0x2ae4ae0, L_0x2ae4bf0, C4<0>, C4<0>; +L_0x2ae4d40 .delay (20000,20000,20000) L_0x2ae4d40/d; +v0x28302c0_0 .net "S", 0 0, L_0x2ae4f10; 1 drivers +v0x2830340_0 .alias "in0", 0 0, v0x28307e0_0; +v0x28303e0_0 .alias "in1", 0 0, v0x2830860_0; +v0x2830480_0 .net "nS", 0 0, L_0x2ae4a20; 1 drivers +v0x2830500_0 .net "out0", 0 0, L_0x2ae4ae0; 1 drivers +v0x28305a0_0 .net "out1", 0 0, L_0x2ae4bf0; 1 drivers +v0x2830680_0 .alias "outfinal", 0 0, v0x2830910_0; +S_0x282f3b0 .scope generate, "andbits[23]" "andbits[23]" 3 231, 3 231, S_0x28293f0; + .timescale -9 -12; +P_0x282f4a8 .param/l "i" 3 231, +C4<010111>; +S_0x282f520 .scope module, "attempt" "AndNand" 3 233, 3 149, S_0x282f3b0; + .timescale -9 -12; +L_0x2ae4810/d .functor NAND 1, L_0x2ae5ad0, L_0x2ae5050, C4<1>, C4<1>; +L_0x2ae4810 .delay (10000,10000,10000) L_0x2ae4810/d; +L_0x2ae5370/d .functor NOT 1, L_0x2ae4810, C4<0>, C4<0>, C4<0>; +L_0x2ae5370 .delay (10000,10000,10000) L_0x2ae5370/d; +v0x282fb60_0 .net "A", 0 0, L_0x2ae5ad0; 1 drivers +v0x282fc20_0 .net "AandB", 0 0, L_0x2ae5370; 1 drivers +v0x282fca0_0 .net "AnandB", 0 0, L_0x2ae4810; 1 drivers +v0x282fd50_0 .net "AndNandOut", 0 0, L_0x2ae57c0; 1 drivers +v0x282fe30_0 .net "B", 0 0, L_0x2ae5050; 1 drivers +v0x282feb0_0 .alias "Command", 2 0, v0x295f7a0_0; +L_0x2ae5990 .part v0x2960210_0, 0, 1; +S_0x282f610 .scope module, "potato" "TwoInMux" 3 161, 3 109, S_0x282f520; + .timescale -9 -12; +L_0x2ae54a0/d .functor NOT 1, L_0x2ae5990, C4<0>, C4<0>, C4<0>; +L_0x2ae54a0 .delay (10000,10000,10000) L_0x2ae54a0/d; +L_0x2ae5560/d .functor AND 1, L_0x2ae5370, L_0x2ae54a0, C4<1>, C4<1>; +L_0x2ae5560 .delay (20000,20000,20000) L_0x2ae5560/d; +L_0x2ae5670/d .functor AND 1, L_0x2ae4810, L_0x2ae5990, C4<1>, C4<1>; +L_0x2ae5670 .delay (20000,20000,20000) L_0x2ae5670/d; +L_0x2ae57c0/d .functor OR 1, L_0x2ae5560, L_0x2ae5670, C4<0>, C4<0>; +L_0x2ae57c0 .delay (20000,20000,20000) L_0x2ae57c0/d; +v0x282f700_0 .net "S", 0 0, L_0x2ae5990; 1 drivers +v0x282f780_0 .alias "in0", 0 0, v0x282fc20_0; +v0x282f820_0 .alias "in1", 0 0, v0x282fca0_0; +v0x282f8c0_0 .net "nS", 0 0, L_0x2ae54a0; 1 drivers +v0x282f940_0 .net "out0", 0 0, L_0x2ae5560; 1 drivers +v0x282f9e0_0 .net "out1", 0 0, L_0x2ae5670; 1 drivers +v0x282fac0_0 .alias "outfinal", 0 0, v0x282fd50_0; +S_0x282e7f0 .scope generate, "andbits[24]" "andbits[24]" 3 231, 3 231, S_0x28293f0; + .timescale -9 -12; +P_0x282e8e8 .param/l "i" 3 231, +C4<011000>; +S_0x282e960 .scope module, "attempt" "AndNand" 3 233, 3 149, S_0x282e7f0; + .timescale -9 -12; +L_0x2ae5140/d .functor NAND 1, L_0x2ae5b70, L_0x2ae5c10, C4<1>, C4<1>; +L_0x2ae5140 .delay (10000,10000,10000) L_0x2ae5140/d; +L_0x2ae5df0/d .functor NOT 1, L_0x2ae5140, C4<0>, C4<0>, C4<0>; +L_0x2ae5df0 .delay (10000,10000,10000) L_0x2ae5df0/d; +v0x282efa0_0 .net "A", 0 0, L_0x2ae5b70; 1 drivers +v0x282f060_0 .net "AandB", 0 0, L_0x2ae5df0; 1 drivers +v0x282f0e0_0 .net "AnandB", 0 0, L_0x2ae5140; 1 drivers +v0x282f190_0 .net "AndNandOut", 0 0, L_0x2ae6220; 1 drivers +v0x282f270_0 .net "B", 0 0, L_0x2ae5c10; 1 drivers +v0x282f2f0_0 .alias "Command", 2 0, v0x295f7a0_0; +L_0x2ae63f0 .part v0x2960210_0, 0, 1; +S_0x282ea50 .scope module, "potato" "TwoInMux" 3 161, 3 109, S_0x282e960; + .timescale -9 -12; +L_0x2ae5f00/d .functor NOT 1, L_0x2ae63f0, C4<0>, C4<0>, C4<0>; +L_0x2ae5f00 .delay (10000,10000,10000) L_0x2ae5f00/d; +L_0x2ae5fc0/d .functor AND 1, L_0x2ae5df0, L_0x2ae5f00, C4<1>, C4<1>; +L_0x2ae5fc0 .delay (20000,20000,20000) L_0x2ae5fc0/d; +L_0x2ae60d0/d .functor AND 1, L_0x2ae5140, L_0x2ae63f0, C4<1>, C4<1>; +L_0x2ae60d0 .delay (20000,20000,20000) L_0x2ae60d0/d; +L_0x2ae6220/d .functor OR 1, L_0x2ae5fc0, L_0x2ae60d0, C4<0>, C4<0>; +L_0x2ae6220 .delay (20000,20000,20000) L_0x2ae6220/d; +v0x282eb40_0 .net "S", 0 0, L_0x2ae63f0; 1 drivers +v0x282ebc0_0 .alias "in0", 0 0, v0x282f060_0; +v0x282ec60_0 .alias "in1", 0 0, v0x282f0e0_0; +v0x282ed00_0 .net "nS", 0 0, L_0x2ae5f00; 1 drivers +v0x282ed80_0 .net "out0", 0 0, L_0x2ae5fc0; 1 drivers +v0x282ee20_0 .net "out1", 0 0, L_0x2ae60d0; 1 drivers +v0x282ef00_0 .alias "outfinal", 0 0, v0x282f190_0; +S_0x282dc30 .scope generate, "andbits[25]" "andbits[25]" 3 231, 3 231, S_0x28293f0; + .timescale -9 -12; +P_0x282dd28 .param/l "i" 3 231, +C4<011001>; +S_0x282dda0 .scope module, "attempt" "AndNand" 3 233, 3 149, S_0x282dc30; + .timescale -9 -12; +L_0x2ae5d00/d .functor NAND 1, L_0x2ae6fa0, L_0x2ae6530, C4<1>, C4<1>; +L_0x2ae5d00 .delay (10000,10000,10000) L_0x2ae5d00/d; +L_0x2ae6860/d .functor NOT 1, L_0x2ae5d00, C4<0>, C4<0>, C4<0>; +L_0x2ae6860 .delay (10000,10000,10000) L_0x2ae6860/d; +v0x282e3e0_0 .net "A", 0 0, L_0x2ae6fa0; 1 drivers +v0x282e4a0_0 .net "AandB", 0 0, L_0x2ae6860; 1 drivers +v0x282e520_0 .net "AnandB", 0 0, L_0x2ae5d00; 1 drivers +v0x282e5d0_0 .net "AndNandOut", 0 0, L_0x2ae6c90; 1 drivers +v0x282e6b0_0 .net "B", 0 0, L_0x2ae6530; 1 drivers +v0x282e730_0 .alias "Command", 2 0, v0x295f7a0_0; +L_0x2ae6e60 .part v0x2960210_0, 0, 1; +S_0x282de90 .scope module, "potato" "TwoInMux" 3 161, 3 109, S_0x282dda0; + .timescale -9 -12; +L_0x2ae6970/d .functor NOT 1, L_0x2ae6e60, C4<0>, C4<0>, C4<0>; +L_0x2ae6970 .delay (10000,10000,10000) L_0x2ae6970/d; +L_0x2ae6a30/d .functor AND 1, L_0x2ae6860, L_0x2ae6970, C4<1>, C4<1>; +L_0x2ae6a30 .delay (20000,20000,20000) L_0x2ae6a30/d; +L_0x2ae6b40/d .functor AND 1, L_0x2ae5d00, L_0x2ae6e60, C4<1>, C4<1>; +L_0x2ae6b40 .delay (20000,20000,20000) L_0x2ae6b40/d; +L_0x2ae6c90/d .functor OR 1, L_0x2ae6a30, L_0x2ae6b40, C4<0>, C4<0>; +L_0x2ae6c90 .delay (20000,20000,20000) L_0x2ae6c90/d; +v0x282df80_0 .net "S", 0 0, L_0x2ae6e60; 1 drivers +v0x282e000_0 .alias "in0", 0 0, v0x282e4a0_0; +v0x282e0a0_0 .alias "in1", 0 0, v0x282e520_0; +v0x282e140_0 .net "nS", 0 0, L_0x2ae6970; 1 drivers +v0x282e1c0_0 .net "out0", 0 0, L_0x2ae6a30; 1 drivers +v0x282e260_0 .net "out1", 0 0, L_0x2ae6b40; 1 drivers +v0x282e340_0 .alias "outfinal", 0 0, v0x282e5d0_0; +S_0x282d070 .scope generate, "andbits[26]" "andbits[26]" 3 231, 3 231, S_0x28293f0; + .timescale -9 -12; +P_0x282d168 .param/l "i" 3 231, +C4<011010>; +S_0x282d1e0 .scope module, "attempt" "AndNand" 3 233, 3 149, S_0x282d070; + .timescale -9 -12; +L_0x2ae6620/d .functor NAND 1, L_0x2ae7040, L_0x2ae70e0, C4<1>, C4<1>; +L_0x2ae6620 .delay (10000,10000,10000) L_0x2ae6620/d; +L_0x2ae72a0/d .functor NOT 1, L_0x2ae6620, C4<0>, C4<0>, C4<0>; +L_0x2ae72a0 .delay (10000,10000,10000) L_0x2ae72a0/d; +v0x282d820_0 .net "A", 0 0, L_0x2ae7040; 1 drivers +v0x282d8e0_0 .net "AandB", 0 0, L_0x2ae72a0; 1 drivers +v0x282d960_0 .net "AnandB", 0 0, L_0x2ae6620; 1 drivers +v0x282da10_0 .net "AndNandOut", 0 0, L_0x2ae76f0; 1 drivers +v0x282daf0_0 .net "B", 0 0, L_0x2ae70e0; 1 drivers +v0x282db70_0 .alias "Command", 2 0, v0x295f7a0_0; +L_0x2ae78c0 .part v0x2960210_0, 0, 1; +S_0x282d2d0 .scope module, "potato" "TwoInMux" 3 161, 3 109, S_0x282d1e0; + .timescale -9 -12; +L_0x2ae73d0/d .functor NOT 1, L_0x2ae78c0, C4<0>, C4<0>, C4<0>; +L_0x2ae73d0 .delay (10000,10000,10000) L_0x2ae73d0/d; +L_0x2ae7490/d .functor AND 1, L_0x2ae72a0, L_0x2ae73d0, C4<1>, C4<1>; +L_0x2ae7490 .delay (20000,20000,20000) L_0x2ae7490/d; +L_0x2ae75a0/d .functor AND 1, L_0x2ae6620, L_0x2ae78c0, C4<1>, C4<1>; +L_0x2ae75a0 .delay (20000,20000,20000) L_0x2ae75a0/d; +L_0x2ae76f0/d .functor OR 1, L_0x2ae7490, L_0x2ae75a0, C4<0>, C4<0>; +L_0x2ae76f0 .delay (20000,20000,20000) L_0x2ae76f0/d; +v0x282d3c0_0 .net "S", 0 0, L_0x2ae78c0; 1 drivers +v0x282d440_0 .alias "in0", 0 0, v0x282d8e0_0; +v0x282d4e0_0 .alias "in1", 0 0, v0x282d960_0; +v0x282d580_0 .net "nS", 0 0, L_0x2ae73d0; 1 drivers +v0x282d600_0 .net "out0", 0 0, L_0x2ae7490; 1 drivers +v0x282d6a0_0 .net "out1", 0 0, L_0x2ae75a0; 1 drivers +v0x282d780_0 .alias "outfinal", 0 0, v0x282da10_0; +S_0x282c4b0 .scope generate, "andbits[27]" "andbits[27]" 3 231, 3 231, S_0x28293f0; + .timescale -9 -12; +P_0x282c5a8 .param/l "i" 3 231, +C4<011011>; +S_0x282c620 .scope module, "attempt" "AndNand" 3 233, 3 149, S_0x282c4b0; + .timescale -9 -12; +L_0x2ae71d0/d .functor NAND 1, L_0x2ae8470, L_0x2ae7a00, C4<1>, C4<1>; +L_0x2ae71d0 .delay (10000,10000,10000) L_0x2ae71d0/d; +L_0x2ae7d10/d .functor NOT 1, L_0x2ae71d0, C4<0>, C4<0>, C4<0>; +L_0x2ae7d10 .delay (10000,10000,10000) L_0x2ae7d10/d; +v0x282cc60_0 .net "A", 0 0, L_0x2ae8470; 1 drivers +v0x282cd20_0 .net "AandB", 0 0, L_0x2ae7d10; 1 drivers +v0x282cda0_0 .net "AnandB", 0 0, L_0x2ae71d0; 1 drivers +v0x282ce50_0 .net "AndNandOut", 0 0, L_0x2ae8160; 1 drivers +v0x282cf30_0 .net "B", 0 0, L_0x2ae7a00; 1 drivers +v0x282cfb0_0 .alias "Command", 2 0, v0x295f7a0_0; +L_0x2ae8330 .part v0x2960210_0, 0, 1; +S_0x282c710 .scope module, "potato" "TwoInMux" 3 161, 3 109, S_0x282c620; + .timescale -9 -12; +L_0x2ae7e40/d .functor NOT 1, L_0x2ae8330, C4<0>, C4<0>, C4<0>; +L_0x2ae7e40 .delay (10000,10000,10000) L_0x2ae7e40/d; +L_0x2ae7f00/d .functor AND 1, L_0x2ae7d10, L_0x2ae7e40, C4<1>, C4<1>; +L_0x2ae7f00 .delay (20000,20000,20000) L_0x2ae7f00/d; +L_0x2ae8010/d .functor AND 1, L_0x2ae71d0, L_0x2ae8330, C4<1>, C4<1>; +L_0x2ae8010 .delay (20000,20000,20000) L_0x2ae8010/d; +L_0x2ae8160/d .functor OR 1, L_0x2ae7f00, L_0x2ae8010, C4<0>, C4<0>; +L_0x2ae8160 .delay (20000,20000,20000) L_0x2ae8160/d; +v0x282c800_0 .net "S", 0 0, L_0x2ae8330; 1 drivers +v0x282c880_0 .alias "in0", 0 0, v0x282cd20_0; +v0x282c920_0 .alias "in1", 0 0, v0x282cda0_0; +v0x282c9c0_0 .net "nS", 0 0, L_0x2ae7e40; 1 drivers +v0x282ca40_0 .net "out0", 0 0, L_0x2ae7f00; 1 drivers +v0x282cae0_0 .net "out1", 0 0, L_0x2ae8010; 1 drivers +v0x282cbc0_0 .alias "outfinal", 0 0, v0x282ce50_0; +S_0x282b8f0 .scope generate, "andbits[28]" "andbits[28]" 3 231, 3 231, S_0x28293f0; + .timescale -9 -12; +P_0x282b9e8 .param/l "i" 3 231, +C4<011100>; +S_0x282ba60 .scope module, "attempt" "AndNand" 3 233, 3 149, S_0x282b8f0; + .timescale -9 -12; +L_0x2ae7af0/d .functor NAND 1, L_0x2ae8510, L_0x2ae85b0, C4<1>, C4<1>; +L_0x2ae7af0 .delay (10000,10000,10000) L_0x2ae7af0/d; +L_0x2ae87a0/d .functor NOT 1, L_0x2ae7af0, C4<0>, C4<0>, C4<0>; +L_0x2ae87a0 .delay (10000,10000,10000) L_0x2ae87a0/d; +v0x282c0a0_0 .net "A", 0 0, L_0x2ae8510; 1 drivers +v0x282c160_0 .net "AandB", 0 0, L_0x2ae87a0; 1 drivers +v0x282c1e0_0 .net "AnandB", 0 0, L_0x2ae7af0; 1 drivers +v0x282c290_0 .net "AndNandOut", 0 0, L_0x2ae8bd0; 1 drivers +v0x282c370_0 .net "B", 0 0, L_0x2ae85b0; 1 drivers +v0x282c3f0_0 .alias "Command", 2 0, v0x295f7a0_0; +L_0x2ae8da0 .part v0x2960210_0, 0, 1; +S_0x282bb50 .scope module, "potato" "TwoInMux" 3 161, 3 109, S_0x282ba60; + .timescale -9 -12; +L_0x2ae88b0/d .functor NOT 1, L_0x2ae8da0, C4<0>, C4<0>, C4<0>; +L_0x2ae88b0 .delay (10000,10000,10000) L_0x2ae88b0/d; +L_0x2ae8970/d .functor AND 1, L_0x2ae87a0, L_0x2ae88b0, C4<1>, C4<1>; +L_0x2ae8970 .delay (20000,20000,20000) L_0x2ae8970/d; +L_0x2ae8a80/d .functor AND 1, L_0x2ae7af0, L_0x2ae8da0, C4<1>, C4<1>; +L_0x2ae8a80 .delay (20000,20000,20000) L_0x2ae8a80/d; +L_0x2ae8bd0/d .functor OR 1, L_0x2ae8970, L_0x2ae8a80, C4<0>, C4<0>; +L_0x2ae8bd0 .delay (20000,20000,20000) L_0x2ae8bd0/d; +v0x282bc40_0 .net "S", 0 0, L_0x2ae8da0; 1 drivers +v0x282bcc0_0 .alias "in0", 0 0, v0x282c160_0; +v0x282bd60_0 .alias "in1", 0 0, v0x282c1e0_0; +v0x282be00_0 .net "nS", 0 0, L_0x2ae88b0; 1 drivers +v0x282be80_0 .net "out0", 0 0, L_0x2ae8970; 1 drivers +v0x282bf20_0 .net "out1", 0 0, L_0x2ae8a80; 1 drivers +v0x282c000_0 .alias "outfinal", 0 0, v0x282c290_0; +S_0x282ad30 .scope generate, "andbits[29]" "andbits[29]" 3 231, 3 231, S_0x28293f0; + .timescale -9 -12; +P_0x282ae28 .param/l "i" 3 231, +C4<011101>; +S_0x282aea0 .scope module, "attempt" "AndNand" 3 233, 3 149, S_0x282ad30; + .timescale -9 -12; +L_0x2ae86a0/d .functor NAND 1, L_0x2ae9960, L_0x2ae8ee0, C4<1>, C4<1>; +L_0x2ae86a0 .delay (10000,10000,10000) L_0x2ae86a0/d; +L_0x2ae9220/d .functor NOT 1, L_0x2ae86a0, C4<0>, C4<0>, C4<0>; +L_0x2ae9220 .delay (10000,10000,10000) L_0x2ae9220/d; +v0x282b4e0_0 .net "A", 0 0, L_0x2ae9960; 1 drivers +v0x282b5a0_0 .net "AandB", 0 0, L_0x2ae9220; 1 drivers +v0x282b620_0 .net "AnandB", 0 0, L_0x2ae86a0; 1 drivers +v0x282b6d0_0 .net "AndNandOut", 0 0, L_0x2ae9650; 1 drivers +v0x282b7b0_0 .net "B", 0 0, L_0x2ae8ee0; 1 drivers +v0x282b830_0 .alias "Command", 2 0, v0x295f7a0_0; +L_0x2ae9820 .part v0x2960210_0, 0, 1; +S_0x282af90 .scope module, "potato" "TwoInMux" 3 161, 3 109, S_0x282aea0; + .timescale -9 -12; +L_0x2ae9330/d .functor NOT 1, L_0x2ae9820, C4<0>, C4<0>, C4<0>; +L_0x2ae9330 .delay (10000,10000,10000) L_0x2ae9330/d; +L_0x2ae93f0/d .functor AND 1, L_0x2ae9220, L_0x2ae9330, C4<1>, C4<1>; +L_0x2ae93f0 .delay (20000,20000,20000) L_0x2ae93f0/d; +L_0x2ae9500/d .functor AND 1, L_0x2ae86a0, L_0x2ae9820, C4<1>, C4<1>; +L_0x2ae9500 .delay (20000,20000,20000) L_0x2ae9500/d; +L_0x2ae9650/d .functor OR 1, L_0x2ae93f0, L_0x2ae9500, C4<0>, C4<0>; +L_0x2ae9650 .delay (20000,20000,20000) L_0x2ae9650/d; +v0x282b080_0 .net "S", 0 0, L_0x2ae9820; 1 drivers +v0x282b100_0 .alias "in0", 0 0, v0x282b5a0_0; +v0x282b1a0_0 .alias "in1", 0 0, v0x282b620_0; +v0x282b240_0 .net "nS", 0 0, L_0x2ae9330; 1 drivers +v0x282b2c0_0 .net "out0", 0 0, L_0x2ae93f0; 1 drivers +v0x282b360_0 .net "out1", 0 0, L_0x2ae9500; 1 drivers +v0x282b440_0 .alias "outfinal", 0 0, v0x282b6d0_0; +S_0x282a170 .scope generate, "andbits[30]" "andbits[30]" 3 231, 3 231, S_0x28293f0; + .timescale -9 -12; +P_0x282a268 .param/l "i" 3 231, +C4<011110>; +S_0x282a2e0 .scope module, "attempt" "AndNand" 3 233, 3 149, S_0x282a170; + .timescale -9 -12; +L_0x2ae8fd0/d .functor NAND 1, L_0x2ae9a00, L_0x2ae9aa0, C4<1>, C4<1>; +L_0x2ae8fd0 .delay (10000,10000,10000) L_0x2ae8fd0/d; +L_0x2ae9130/d .functor NOT 1, L_0x2ae8fd0, C4<0>, C4<0>, C4<0>; +L_0x2ae9130 .delay (10000,10000,10000) L_0x2ae9130/d; +v0x282a920_0 .net "A", 0 0, L_0x2ae9a00; 1 drivers +v0x282a9e0_0 .net "AandB", 0 0, L_0x2ae9130; 1 drivers +v0x282aa60_0 .net "AnandB", 0 0, L_0x2ae8fd0; 1 drivers +v0x282ab10_0 .net "AndNandOut", 0 0, L_0x2aea0b0; 1 drivers +v0x282abf0_0 .net "B", 0 0, L_0x2ae9aa0; 1 drivers +v0x282ac70_0 .alias "Command", 2 0, v0x295f7a0_0; +L_0x2aea280 .part v0x2960210_0, 0, 1; +S_0x282a3d0 .scope module, "potato" "TwoInMux" 3 161, 3 109, S_0x282a2e0; + .timescale -9 -12; +L_0x2ae9d90/d .functor NOT 1, L_0x2aea280, C4<0>, C4<0>, C4<0>; +L_0x2ae9d90 .delay (10000,10000,10000) L_0x2ae9d90/d; +L_0x2ae9e50/d .functor AND 1, L_0x2ae9130, L_0x2ae9d90, C4<1>, C4<1>; +L_0x2ae9e50 .delay (20000,20000,20000) L_0x2ae9e50/d; +L_0x2ae9f60/d .functor AND 1, L_0x2ae8fd0, L_0x2aea280, C4<1>, C4<1>; +L_0x2ae9f60 .delay (20000,20000,20000) L_0x2ae9f60/d; +L_0x2aea0b0/d .functor OR 1, L_0x2ae9e50, L_0x2ae9f60, C4<0>, C4<0>; +L_0x2aea0b0 .delay (20000,20000,20000) L_0x2aea0b0/d; +v0x282a4c0_0 .net "S", 0 0, L_0x2aea280; 1 drivers +v0x282a540_0 .alias "in0", 0 0, v0x282a9e0_0; +v0x282a5e0_0 .alias "in1", 0 0, v0x282aa60_0; +v0x282a680_0 .net "nS", 0 0, L_0x2ae9d90; 1 drivers +v0x282a700_0 .net "out0", 0 0, L_0x2ae9e50; 1 drivers +v0x282a7a0_0 .net "out1", 0 0, L_0x2ae9f60; 1 drivers +v0x282a880_0 .alias "outfinal", 0 0, v0x282ab10_0; +S_0x2829550 .scope generate, "andbits[31]" "andbits[31]" 3 231, 3 231, S_0x28293f0; + .timescale -9 -12; +P_0x2829648 .param/l "i" 3 231, +C4<011111>; +S_0x2829700 .scope module, "attempt" "AndNand" 3 233, 3 149, S_0x2829550; + .timescale -9 -12; +L_0x2ae9b90/d .functor NAND 1, L_0x2a37f60, L_0x2aea3c0, C4<1>, C4<1>; +L_0x2ae9b90 .delay (10000,10000,10000) L_0x2ae9b90/d; +L_0x2aea6f0/d .functor NOT 1, L_0x2ae9b90, C4<0>, C4<0>, C4<0>; +L_0x2aea6f0 .delay (10000,10000,10000) L_0x2aea6f0/d; +v0x2829d60_0 .net "A", 0 0, L_0x2a37f60; 1 drivers +v0x2829e20_0 .net "AandB", 0 0, L_0x2aea6f0; 1 drivers +v0x2829ea0_0 .net "AnandB", 0 0, L_0x2ae9b90; 1 drivers +v0x2829f50_0 .net "AndNandOut", 0 0, L_0x2aeab20; 1 drivers +v0x282a030_0 .net "B", 0 0, L_0x2aea3c0; 1 drivers +v0x282a0b0_0 .alias "Command", 2 0, v0x295f7a0_0; +L_0x2aeacf0 .part v0x2960210_0, 0, 1; +S_0x28297f0 .scope module, "potato" "TwoInMux" 3 161, 3 109, S_0x2829700; + .timescale -9 -12; +L_0x2aea800/d .functor NOT 1, L_0x2aeacf0, C4<0>, C4<0>, C4<0>; +L_0x2aea800 .delay (10000,10000,10000) L_0x2aea800/d; +L_0x2aea8c0/d .functor AND 1, L_0x2aea6f0, L_0x2aea800, C4<1>, C4<1>; +L_0x2aea8c0 .delay (20000,20000,20000) L_0x2aea8c0/d; +L_0x2aea9d0/d .functor AND 1, L_0x2ae9b90, L_0x2aeacf0, C4<1>, C4<1>; +L_0x2aea9d0 .delay (20000,20000,20000) L_0x2aea9d0/d; +L_0x2aeab20/d .functor OR 1, L_0x2aea8c0, L_0x2aea9d0, C4<0>, C4<0>; +L_0x2aeab20 .delay (20000,20000,20000) L_0x2aeab20/d; +v0x28298e0_0 .net "S", 0 0, L_0x2aeacf0; 1 drivers +v0x2829980_0 .alias "in0", 0 0, v0x2829e20_0; +v0x2829a20_0 .alias "in1", 0 0, v0x2829ea0_0; +v0x2829ac0_0 .net "nS", 0 0, L_0x2aea800; 1 drivers +v0x2829b40_0 .net "out0", 0 0, L_0x2aea8c0; 1 drivers +v0x2829be0_0 .net "out1", 0 0, L_0x2aea9d0; 1 drivers +v0x2829cc0_0 .alias "outfinal", 0 0, v0x2829f50_0; +S_0x2801850 .scope module, "trial2" "OrNorXor32" 3 388, 3 239, S_0x25e6a40; + .timescale -9 -12; +P_0x28009a8 .param/l "size" 3 246, +C4<0100000>; +v0x28291f0_0 .alias "A", 31 0, v0x295f580_0; +v0x2829270_0 .alias "B", 31 0, v0x295f6a0_0; +v0x28292f0_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x2829370_0 .alias "OrNorXorOut", 31 0, v0x29603c0_0; +L_0x2aed1f0 .part/pv L_0x2aecfc0, 1, 1, 32; +L_0x2aed290 .part v0x295fe90_0, 1, 1; +L_0x2aed330 .part v0x2960190_0, 1, 1; +L_0x2aee2f0 .part/pv L_0x2aee0c0, 2, 1, 32; +L_0x2aee390 .part v0x295fe90_0, 2, 1; +L_0x2aee430 .part v0x2960190_0, 2, 1; +L_0x2aef450 .part/pv L_0x2aef200, 3, 1, 32; +L_0x2aef4f0 .part v0x295fe90_0, 3, 1; +L_0x2aef590 .part v0x2960190_0, 3, 1; +L_0x2af0740 .part/pv L_0x2af04d0, 4, 1, 32; +L_0x2af0840 .part v0x295fe90_0, 4, 1; +L_0x2af08e0 .part v0x2960190_0, 4, 1; +L_0x2af1a40 .part/pv L_0x2af17d0, 5, 1, 32; +L_0x2af1ae0 .part v0x295fe90_0, 5, 1; +L_0x2af1c00 .part v0x2960190_0, 5, 1; +L_0x2af2da0 .part/pv L_0x2af2b30, 6, 1, 32; +L_0x2af2ed0 .part v0x295fe90_0, 6, 1; +L_0x2af2f70 .part v0x2960190_0, 6, 1; +L_0x2af4130 .part/pv L_0x2af3ec0, 7, 1, 32; +L_0x2af41d0 .part v0x295fe90_0, 7, 1; +L_0x2af3010 .part v0x2960190_0, 7, 1; +L_0x2af5420 .part/pv L_0x2af51b0, 8, 1, 32; +L_0x2af4270 .part v0x295fe90_0, 8, 1; +L_0x2af5580 .part v0x2960190_0, 8, 1; +L_0x2af6730 .part/pv L_0x2af64c0, 9, 1, 32; +L_0x2af67d0 .part v0x295fe90_0, 9, 1; +L_0x2af5620 .part v0x2960190_0, 9, 1; +L_0x2af7a30 .part/pv L_0x2af77c0, 10, 1, 32; +L_0x2af6870 .part v0x295fe90_0, 10, 1; +L_0x2af7bc0 .part v0x2960190_0, 10, 1; +L_0x2af8d30 .part/pv L_0x2af8ac0, 11, 1, 32; +L_0x2af8dd0 .part v0x295fe90_0, 11, 1; +L_0x2af7c60 .part v0x2960190_0, 11, 1; +L_0x2afa020 .part/pv L_0x2af9db0, 12, 1, 32; +L_0x2af8e70 .part v0x295fe90_0, 12, 1; +L_0x2afa1e0 .part v0x2960190_0, 12, 1; +L_0x2afb340 .part/pv L_0x2afb0d0, 13, 1, 32; +L_0x2afb3e0 .part v0x295fe90_0, 13, 1; +L_0x2afa280 .part v0x2960190_0, 13, 1; +L_0x2afc640 .part/pv L_0x2afc3d0, 14, 1, 32; +L_0x2afb480 .part v0x295fe90_0, 14, 1; +L_0x2afb520 .part v0x2960190_0, 14, 1; +L_0x2afd940 .part/pv L_0x2afd6d0, 15, 1, 32; +L_0x2afd9e0 .part v0x295fe90_0, 15, 1; +L_0x2afc6e0 .part v0x2960190_0, 15, 1; +L_0x2afea20 .part/pv L_0x2afe7f0, 16, 1, 32; +L_0x2afda80 .part v0x295fe90_0, 16, 1; +L_0x2afdb20 .part v0x2960190_0, 16, 1; +L_0x2affc30 .part/pv L_0x2aff9c0, 17, 1, 32; +L_0x2affcd0 .part v0x295fe90_0, 17, 1; +L_0x2afeac0 .part v0x2960190_0, 17, 1; +L_0x2b00f20 .part/pv L_0x2b00cb0, 18, 1, 32; +L_0x2affd70 .part v0x295fe90_0, 18, 1; +L_0x2affe10 .part v0x2960190_0, 18, 1; +L_0x2a011b0 .part/pv L_0x2a00f40, 19, 1, 32; +L_0x2a01250 .part v0x295fe90_0, 19, 1; +L_0x2a00140 .part v0x2960190_0, 19, 1; +L_0x2b054d0 .part/pv L_0x2b05280, 20, 1, 32; +L_0x2a012f0 .part v0x295fe90_0, 20, 1; +L_0x2a01390 .part v0x2960190_0, 20, 1; +L_0x2b067e0 .part/pv L_0x2b06570, 21, 1, 32; +L_0x2b06880 .part v0x295fe90_0, 21, 1; +L_0x2b05570 .part v0x2960190_0, 21, 1; +L_0x2b07ad0 .part/pv L_0x2b07860, 22, 1, 32; +L_0x2b06920 .part v0x295fe90_0, 22, 1; +L_0x2b069c0 .part v0x2960190_0, 22, 1; +L_0x2b08dd0 .part/pv L_0x2b08b60, 23, 1, 32; +L_0x2b08e70 .part v0x295fe90_0, 23, 1; +L_0x2b07b70 .part v0x2960190_0, 23, 1; +L_0x2b0a0d0 .part/pv L_0x2b09e60, 24, 1, 32; +L_0x2b08f10 .part v0x295fe90_0, 24, 1; +L_0x2b08fb0 .part v0x2960190_0, 24, 1; +L_0x2b0b3d0 .part/pv L_0x2b0b160, 25, 1, 32; +L_0x2b0b470 .part v0x295fe90_0, 25, 1; +L_0x2b0a170 .part v0x2960190_0, 25, 1; +L_0x2b0c6c0 .part/pv L_0x2b0c450, 26, 1, 32; +L_0x2b0b510 .part v0x295fe90_0, 26, 1; +L_0x2b0b5b0 .part v0x2960190_0, 26, 1; +L_0x2b0d9f0 .part/pv L_0x2b0d780, 27, 1, 32; +L_0x2b0da90 .part v0x295fe90_0, 27, 1; +L_0x2b0c760 .part v0x2960190_0, 27, 1; +L_0x2b0ecf0 .part/pv L_0x2b0ea80, 28, 1, 32; +L_0x2b0db30 .part v0x295fe90_0, 28, 1; +L_0x2b0dbd0 .part v0x2960190_0, 28, 1; +L_0x2b0fff0 .part/pv L_0x2b0fd80, 29, 1, 32; +L_0x2b10090 .part v0x295fe90_0, 29, 1; +L_0x2b0ed90 .part v0x2960190_0, 29, 1; +L_0x2b112e0 .part/pv L_0x2b11070, 30, 1, 32; +L_0x2b10130 .part v0x295fe90_0, 30, 1; +L_0x2b101d0 .part v0x2960190_0, 30, 1; +L_0x2b125f0 .part/pv L_0x2b12380, 31, 1, 32; +L_0x2b12690 .part v0x295fe90_0, 31, 1; +L_0x2b11380 .part v0x2960190_0, 31, 1; +L_0x2b13900 .part/pv L_0x2b13690, 0, 1, 32; +L_0x2b12730 .part v0x295fe90_0, 0, 1; +L_0x2b127d0 .part v0x2960190_0, 0, 1; +S_0x2827fc0 .scope module, "attempt2" "OrNorXor" 3 254, 3 165, S_0x2801850; + .timescale -9 -12; +L_0x2b11420/d .functor NOR 1, L_0x2b12730, L_0x2b127d0, C4<0>, C4<0>; +L_0x2b11420 .delay (10000,10000,10000) L_0x2b11420/d; +L_0x2b11510/d .functor NOT 1, L_0x2b11420, C4<0>, C4<0>, C4<0>; +L_0x2b11510 .delay (10000,10000,10000) L_0x2b11510/d; +L_0x2b12a20/d .functor NAND 1, L_0x2b12730, L_0x2b127d0, C4<1>, C4<1>; +L_0x2b12a20 .delay (10000,10000,10000) L_0x2b12a20/d; +L_0x2b12b60/d .functor NAND 1, L_0x2b12a20, L_0x2b11510, C4<1>, C4<1>; +L_0x2b12b60 .delay (10000,10000,10000) L_0x2b12b60/d; +L_0x2b12c70/d .functor NOT 1, L_0x2b12b60, C4<0>, C4<0>, C4<0>; +L_0x2b12c70 .delay (10000,10000,10000) L_0x2b12c70/d; +v0x2828ae0_0 .net "A", 0 0, L_0x2b12730; 1 drivers +v0x2828b80_0 .net "AnandB", 0 0, L_0x2b12a20; 1 drivers +v0x2828c20_0 .net "AnorB", 0 0, L_0x2b11420; 1 drivers +v0x2828cd0_0 .net "AorB", 0 0, L_0x2b11510; 1 drivers +v0x2828db0_0 .net "AxorB", 0 0, L_0x2b12c70; 1 drivers +v0x2828e30_0 .net "B", 0 0, L_0x2b127d0; 1 drivers +v0x2828ef0_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x2828f70_0 .net "OrNorXorOut", 0 0, L_0x2b13690; 1 drivers +v0x2829040_0 .net "XorNor", 0 0, L_0x2b130f0; 1 drivers +v0x2829110_0 .net "nXor", 0 0, L_0x2b12b60; 1 drivers +L_0x2b13270 .part v0x2960210_0, 2, 1; +L_0x2b13860 .part v0x2960210_0, 0, 1; +S_0x2828540 .scope module, "mux0" "TwoInMux" 3 184, 3 109, S_0x2827fc0; + .timescale -9 -12; +L_0x2b12dd0/d .functor NOT 1, L_0x2b13270, C4<0>, C4<0>, C4<0>; +L_0x2b12dd0 .delay (10000,10000,10000) L_0x2b12dd0/d; +L_0x2b12e90/d .functor AND 1, L_0x2b12c70, L_0x2b12dd0, C4<1>, C4<1>; +L_0x2b12e90 .delay (20000,20000,20000) L_0x2b12e90/d; +L_0x2b12fa0/d .functor AND 1, L_0x2b11420, L_0x2b13270, C4<1>, C4<1>; +L_0x2b12fa0 .delay (20000,20000,20000) L_0x2b12fa0/d; +L_0x2b130f0/d .functor OR 1, L_0x2b12e90, L_0x2b12fa0, C4<0>, C4<0>; +L_0x2b130f0 .delay (20000,20000,20000) L_0x2b130f0/d; +v0x2828630_0 .net "S", 0 0, L_0x2b13270; 1 drivers +v0x28286f0_0 .alias "in0", 0 0, v0x2828db0_0; +v0x2828790_0 .alias "in1", 0 0, v0x2828c20_0; +v0x2828830_0 .net "nS", 0 0, L_0x2b12dd0; 1 drivers +v0x28288e0_0 .net "out0", 0 0, L_0x2b12e90; 1 drivers +v0x2828980_0 .net "out1", 0 0, L_0x2b12fa0; 1 drivers +v0x2828a60_0 .alias "outfinal", 0 0, v0x2829040_0; +S_0x28280b0 .scope module, "mux1" "TwoInMux" 3 185, 3 109, S_0x2827fc0; + .timescale -9 -12; +L_0x2b13310/d .functor NOT 1, L_0x2b13860, C4<0>, C4<0>, C4<0>; +L_0x2b13310 .delay (10000,10000,10000) L_0x2b13310/d; +L_0x2b133d0/d .functor AND 1, L_0x2b130f0, L_0x2b13310, C4<1>, C4<1>; +L_0x2b133d0 .delay (20000,20000,20000) L_0x2b133d0/d; +L_0x2b13520/d .functor AND 1, L_0x2b11510, L_0x2b13860, C4<1>, C4<1>; +L_0x2b13520 .delay (20000,20000,20000) L_0x2b13520/d; +L_0x2b13690/d .functor OR 1, L_0x2b133d0, L_0x2b13520, C4<0>, C4<0>; +L_0x2b13690 .delay (20000,20000,20000) L_0x2b13690/d; +v0x28281a0_0 .net "S", 0 0, L_0x2b13860; 1 drivers +v0x2828220_0 .alias "in0", 0 0, v0x2829040_0; +v0x28282a0_0 .alias "in1", 0 0, v0x2828cd0_0; +v0x2828320_0 .net "nS", 0 0, L_0x2b13310; 1 drivers +v0x28283a0_0 .net "out0", 0 0, L_0x2b133d0; 1 drivers +v0x2828420_0 .net "out1", 0 0, L_0x2b13520; 1 drivers +v0x28284a0_0 .alias "outfinal", 0 0, v0x2828f70_0; +S_0x2826bf0 .scope generate, "orbits[1]" "orbits[1]" 3 258, 3 258, S_0x2801850; + .timescale -9 -12; +P_0x2826908 .param/l "i" 3 258, +C4<01>; +S_0x2826d20 .scope module, "attempt" "OrNorXor" 3 260, 3 165, S_0x2826bf0; + .timescale -9 -12; +L_0x2a38190/d .functor NOR 1, L_0x2aed290, L_0x2aed330, C4<0>, C4<0>; +L_0x2a38190 .delay (10000,10000,10000) L_0x2a38190/d; +L_0x2aec3c0/d .functor NOT 1, L_0x2a38190, C4<0>, C4<0>, C4<0>; +L_0x2aec3c0 .delay (10000,10000,10000) L_0x2aec3c0/d; +L_0x2aec4b0/d .functor NAND 1, L_0x2aed290, L_0x2aed330, C4<1>, C4<1>; +L_0x2aec4b0 .delay (10000,10000,10000) L_0x2aec4b0/d; +L_0x2aec5f0/d .functor NAND 1, L_0x2aec4b0, L_0x2aec3c0, C4<1>, C4<1>; +L_0x2aec5f0 .delay (10000,10000,10000) L_0x2aec5f0/d; +L_0x2aec6e0/d .functor NOT 1, L_0x2aec5f0, C4<0>, C4<0>, C4<0>; +L_0x2aec6e0 .delay (10000,10000,10000) L_0x2aec6e0/d; +v0x28278d0_0 .net "A", 0 0, L_0x2aed290; 1 drivers +v0x2827970_0 .net "AnandB", 0 0, L_0x2aec4b0; 1 drivers +v0x2827a10_0 .net "AnorB", 0 0, L_0x2a38190; 1 drivers +v0x2827ac0_0 .net "AorB", 0 0, L_0x2aec3c0; 1 drivers +v0x2827ba0_0 .net "AxorB", 0 0, L_0x2aec6e0; 1 drivers +v0x2827c50_0 .net "B", 0 0, L_0x2aed330; 1 drivers +v0x2827d10_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x2827d90_0 .net "OrNorXorOut", 0 0, L_0x2aecfc0; 1 drivers +v0x2827e10_0 .net "XorNor", 0 0, L_0x2aecae0; 1 drivers +v0x2827ee0_0 .net "nXor", 0 0, L_0x2aec5f0; 1 drivers +L_0x2aecc20 .part v0x2960210_0, 2, 1; +L_0x2aed150 .part v0x2960210_0, 0, 1; +S_0x2827360 .scope module, "mux0" "TwoInMux" 3 184, 3 109, S_0x2826d20; + .timescale -9 -12; +L_0x2aec820/d .functor NOT 1, L_0x2aecc20, C4<0>, C4<0>, C4<0>; +L_0x2aec820 .delay (10000,10000,10000) L_0x2aec820/d; +L_0x2aec8c0/d .functor AND 1, L_0x2aec6e0, L_0x2aec820, C4<1>, C4<1>; +L_0x2aec8c0 .delay (20000,20000,20000) L_0x2aec8c0/d; +L_0x2aec9b0/d .functor AND 1, L_0x2a38190, L_0x2aecc20, C4<1>, C4<1>; +L_0x2aec9b0 .delay (20000,20000,20000) L_0x2aec9b0/d; +L_0x2aecae0/d .functor OR 1, L_0x2aec8c0, L_0x2aec9b0, C4<0>, C4<0>; +L_0x2aecae0 .delay (20000,20000,20000) L_0x2aecae0/d; +v0x2827450_0 .net "S", 0 0, L_0x2aecc20; 1 drivers +v0x2827510_0 .alias "in0", 0 0, v0x2827ba0_0; +v0x28275b0_0 .alias "in1", 0 0, v0x2827a10_0; +v0x2827650_0 .net "nS", 0 0, L_0x2aec820; 1 drivers +v0x28276d0_0 .net "out0", 0 0, L_0x2aec8c0; 1 drivers +v0x2827770_0 .net "out1", 0 0, L_0x2aec9b0; 1 drivers +v0x2827850_0 .alias "outfinal", 0 0, v0x2827e10_0; +S_0x2826e10 .scope module, "mux1" "TwoInMux" 3 185, 3 109, S_0x2826d20; + .timescale -9 -12; +L_0x2aeccc0/d .functor NOT 1, L_0x2aed150, C4<0>, C4<0>, C4<0>; +L_0x2aeccc0 .delay (10000,10000,10000) L_0x2aeccc0/d; +L_0x2aecd60/d .functor AND 1, L_0x2aecae0, L_0x2aeccc0, C4<1>, C4<1>; +L_0x2aecd60 .delay (20000,20000,20000) L_0x2aecd60/d; +L_0x2aece90/d .functor AND 1, L_0x2aec3c0, L_0x2aed150, C4<1>, C4<1>; +L_0x2aece90 .delay (20000,20000,20000) L_0x2aece90/d; +L_0x2aecfc0/d .functor OR 1, L_0x2aecd60, L_0x2aece90, C4<0>, C4<0>; +L_0x2aecfc0 .delay (20000,20000,20000) L_0x2aecfc0/d; +v0x2826f00_0 .net "S", 0 0, L_0x2aed150; 1 drivers +v0x2826f80_0 .alias "in0", 0 0, v0x2827e10_0; +v0x2827020_0 .alias "in1", 0 0, v0x2827ac0_0; +v0x28270c0_0 .net "nS", 0 0, L_0x2aeccc0; 1 drivers +v0x2827140_0 .net "out0", 0 0, L_0x2aecd60; 1 drivers +v0x28271e0_0 .net "out1", 0 0, L_0x2aece90; 1 drivers +v0x28272c0_0 .alias "outfinal", 0 0, v0x2827d90_0; +S_0x2825820 .scope generate, "orbits[2]" "orbits[2]" 3 258, 3 258, S_0x2801850; + .timescale -9 -12; +P_0x2825538 .param/l "i" 3 258, +C4<010>; +S_0x2825950 .scope module, "attempt" "OrNorXor" 3 260, 3 165, S_0x2825820; + .timescale -9 -12; +L_0x2aed3d0/d .functor NOR 1, L_0x2aee390, L_0x2aee430, C4<0>, C4<0>; +L_0x2aed3d0 .delay (10000,10000,10000) L_0x2aed3d0/d; +L_0x2aed4c0/d .functor NOT 1, L_0x2aed3d0, C4<0>, C4<0>, C4<0>; +L_0x2aed4c0 .delay (10000,10000,10000) L_0x2aed4c0/d; +L_0x2aed5b0/d .functor NAND 1, L_0x2aee390, L_0x2aee430, C4<1>, C4<1>; +L_0x2aed5b0 .delay (10000,10000,10000) L_0x2aed5b0/d; +L_0x2aed6f0/d .functor NAND 1, L_0x2aed5b0, L_0x2aed4c0, C4<1>, C4<1>; +L_0x2aed6f0 .delay (10000,10000,10000) L_0x2aed6f0/d; +L_0x2aed7e0/d .functor NOT 1, L_0x2aed6f0, C4<0>, C4<0>, C4<0>; +L_0x2aed7e0 .delay (10000,10000,10000) L_0x2aed7e0/d; +v0x2826500_0 .net "A", 0 0, L_0x2aee390; 1 drivers +v0x28265a0_0 .net "AnandB", 0 0, L_0x2aed5b0; 1 drivers +v0x2826640_0 .net "AnorB", 0 0, L_0x2aed3d0; 1 drivers +v0x28266f0_0 .net "AorB", 0 0, L_0x2aed4c0; 1 drivers +v0x28267d0_0 .net "AxorB", 0 0, L_0x2aed7e0; 1 drivers +v0x2826880_0 .net "B", 0 0, L_0x2aee430; 1 drivers +v0x2826940_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x28269c0_0 .net "OrNorXorOut", 0 0, L_0x2aee0c0; 1 drivers +v0x2826a40_0 .net "XorNor", 0 0, L_0x2aedbe0; 1 drivers +v0x2826b10_0 .net "nXor", 0 0, L_0x2aed6f0; 1 drivers +L_0x2aedd20 .part v0x2960210_0, 2, 1; +L_0x2aee250 .part v0x2960210_0, 0, 1; +S_0x2825f90 .scope module, "mux0" "TwoInMux" 3 184, 3 109, S_0x2825950; + .timescale -9 -12; +L_0x2aed920/d .functor NOT 1, L_0x2aedd20, C4<0>, C4<0>, C4<0>; +L_0x2aed920 .delay (10000,10000,10000) L_0x2aed920/d; +L_0x2aed9c0/d .functor AND 1, L_0x2aed7e0, L_0x2aed920, C4<1>, C4<1>; +L_0x2aed9c0 .delay (20000,20000,20000) L_0x2aed9c0/d; +L_0x2aedab0/d .functor AND 1, L_0x2aed3d0, L_0x2aedd20, C4<1>, C4<1>; +L_0x2aedab0 .delay (20000,20000,20000) L_0x2aedab0/d; +L_0x2aedbe0/d .functor OR 1, L_0x2aed9c0, L_0x2aedab0, C4<0>, C4<0>; +L_0x2aedbe0 .delay (20000,20000,20000) L_0x2aedbe0/d; +v0x2826080_0 .net "S", 0 0, L_0x2aedd20; 1 drivers +v0x2826140_0 .alias "in0", 0 0, v0x28267d0_0; +v0x28261e0_0 .alias "in1", 0 0, v0x2826640_0; +v0x2826280_0 .net "nS", 0 0, L_0x2aed920; 1 drivers +v0x2826300_0 .net "out0", 0 0, L_0x2aed9c0; 1 drivers +v0x28263a0_0 .net "out1", 0 0, L_0x2aedab0; 1 drivers +v0x2826480_0 .alias "outfinal", 0 0, v0x2826a40_0; +S_0x2825a40 .scope module, "mux1" "TwoInMux" 3 185, 3 109, S_0x2825950; + .timescale -9 -12; +L_0x2aeddc0/d .functor NOT 1, L_0x2aee250, C4<0>, C4<0>, C4<0>; +L_0x2aeddc0 .delay (10000,10000,10000) L_0x2aeddc0/d; +L_0x2aede60/d .functor AND 1, L_0x2aedbe0, L_0x2aeddc0, C4<1>, C4<1>; +L_0x2aede60 .delay (20000,20000,20000) L_0x2aede60/d; +L_0x2aedf90/d .functor AND 1, L_0x2aed4c0, L_0x2aee250, C4<1>, C4<1>; +L_0x2aedf90 .delay (20000,20000,20000) L_0x2aedf90/d; +L_0x2aee0c0/d .functor OR 1, L_0x2aede60, L_0x2aedf90, C4<0>, C4<0>; +L_0x2aee0c0 .delay (20000,20000,20000) L_0x2aee0c0/d; +v0x2825b30_0 .net "S", 0 0, L_0x2aee250; 1 drivers +v0x2825bb0_0 .alias "in0", 0 0, v0x2826a40_0; +v0x2825c50_0 .alias "in1", 0 0, v0x28266f0_0; +v0x2825cf0_0 .net "nS", 0 0, L_0x2aeddc0; 1 drivers +v0x2825d70_0 .net "out0", 0 0, L_0x2aede60; 1 drivers +v0x2825e10_0 .net "out1", 0 0, L_0x2aedf90; 1 drivers +v0x2825ef0_0 .alias "outfinal", 0 0, v0x28269c0_0; +S_0x2824450 .scope generate, "orbits[3]" "orbits[3]" 3 258, 3 258, S_0x2801850; + .timescale -9 -12; +P_0x2824168 .param/l "i" 3 258, +C4<011>; +S_0x2824580 .scope module, "attempt" "OrNorXor" 3 260, 3 165, S_0x2824450; + .timescale -9 -12; +L_0x2aee510/d .functor NOR 1, L_0x2aef4f0, L_0x2aef590, C4<0>, C4<0>; +L_0x2aee510 .delay (10000,10000,10000) L_0x2aee510/d; +L_0x2aee600/d .functor NOT 1, L_0x2aee510, C4<0>, C4<0>, C4<0>; +L_0x2aee600 .delay (10000,10000,10000) L_0x2aee600/d; +L_0x2aee6f0/d .functor NAND 1, L_0x2aef4f0, L_0x2aef590, C4<1>, C4<1>; +L_0x2aee6f0 .delay (10000,10000,10000) L_0x2aee6f0/d; +L_0x2aee830/d .functor NAND 1, L_0x2aee6f0, L_0x2aee600, C4<1>, C4<1>; +L_0x2aee830 .delay (10000,10000,10000) L_0x2aee830/d; +L_0x2aee920/d .functor NOT 1, L_0x2aee830, C4<0>, C4<0>, C4<0>; +L_0x2aee920 .delay (10000,10000,10000) L_0x2aee920/d; +v0x2825130_0 .net "A", 0 0, L_0x2aef4f0; 1 drivers +v0x28251d0_0 .net "AnandB", 0 0, L_0x2aee6f0; 1 drivers +v0x2825270_0 .net "AnorB", 0 0, L_0x2aee510; 1 drivers +v0x2825320_0 .net "AorB", 0 0, L_0x2aee600; 1 drivers +v0x2825400_0 .net "AxorB", 0 0, L_0x2aee920; 1 drivers +v0x28254b0_0 .net "B", 0 0, L_0x2aef590; 1 drivers +v0x2825570_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x28255f0_0 .net "OrNorXorOut", 0 0, L_0x2aef200; 1 drivers +v0x2825670_0 .net "XorNor", 0 0, L_0x2aeed20; 1 drivers +v0x2825740_0 .net "nXor", 0 0, L_0x2aee830; 1 drivers +L_0x2aeee60 .part v0x2960210_0, 2, 1; +L_0x2aef3b0 .part v0x2960210_0, 0, 1; +S_0x2824bc0 .scope module, "mux0" "TwoInMux" 3 184, 3 109, S_0x2824580; + .timescale -9 -12; +L_0x2aeea60/d .functor NOT 1, L_0x2aeee60, C4<0>, C4<0>, C4<0>; +L_0x2aeea60 .delay (10000,10000,10000) L_0x2aeea60/d; +L_0x2aeeb00/d .functor AND 1, L_0x2aee920, L_0x2aeea60, C4<1>, C4<1>; +L_0x2aeeb00 .delay (20000,20000,20000) L_0x2aeeb00/d; +L_0x2aeebf0/d .functor AND 1, L_0x2aee510, L_0x2aeee60, C4<1>, C4<1>; +L_0x2aeebf0 .delay (20000,20000,20000) L_0x2aeebf0/d; +L_0x2aeed20/d .functor OR 1, L_0x2aeeb00, L_0x2aeebf0, C4<0>, C4<0>; +L_0x2aeed20 .delay (20000,20000,20000) L_0x2aeed20/d; +v0x2824cb0_0 .net "S", 0 0, L_0x2aeee60; 1 drivers +v0x2824d70_0 .alias "in0", 0 0, v0x2825400_0; +v0x2824e10_0 .alias "in1", 0 0, v0x2825270_0; +v0x2824eb0_0 .net "nS", 0 0, L_0x2aeea60; 1 drivers +v0x2824f30_0 .net "out0", 0 0, L_0x2aeeb00; 1 drivers +v0x2824fd0_0 .net "out1", 0 0, L_0x2aeebf0; 1 drivers +v0x28250b0_0 .alias "outfinal", 0 0, v0x2825670_0; +S_0x2824670 .scope module, "mux1" "TwoInMux" 3 185, 3 109, S_0x2824580; + .timescale -9 -12; +L_0x2aeef00/d .functor NOT 1, L_0x2aef3b0, C4<0>, C4<0>, C4<0>; +L_0x2aeef00 .delay (10000,10000,10000) L_0x2aeef00/d; +L_0x2aeefa0/d .functor AND 1, L_0x2aeed20, L_0x2aeef00, C4<1>, C4<1>; +L_0x2aeefa0 .delay (20000,20000,20000) L_0x2aeefa0/d; +L_0x2aef0d0/d .functor AND 1, L_0x2aee600, L_0x2aef3b0, C4<1>, C4<1>; +L_0x2aef0d0 .delay (20000,20000,20000) L_0x2aef0d0/d; +L_0x2aef200/d .functor OR 1, L_0x2aeefa0, L_0x2aef0d0, C4<0>, C4<0>; +L_0x2aef200 .delay (20000,20000,20000) L_0x2aef200/d; +v0x2824760_0 .net "S", 0 0, L_0x2aef3b0; 1 drivers +v0x28247e0_0 .alias "in0", 0 0, v0x2825670_0; +v0x2824880_0 .alias "in1", 0 0, v0x2825320_0; +v0x2824920_0 .net "nS", 0 0, L_0x2aeef00; 1 drivers +v0x28249a0_0 .net "out0", 0 0, L_0x2aeefa0; 1 drivers +v0x2824a40_0 .net "out1", 0 0, L_0x2aef0d0; 1 drivers +v0x2824b20_0 .alias "outfinal", 0 0, v0x28255f0_0; +S_0x2823080 .scope generate, "orbits[4]" "orbits[4]" 3 258, 3 258, S_0x2801850; + .timescale -9 -12; +P_0x2822d98 .param/l "i" 3 258, +C4<0100>; +S_0x28231b0 .scope module, "attempt" "OrNorXor" 3 260, 3 165, S_0x2823080; + .timescale -9 -12; +L_0x2aef630/d .functor NOR 1, L_0x2af0840, L_0x2af08e0, C4<0>, C4<0>; +L_0x2aef630 .delay (10000,10000,10000) L_0x2aef630/d; +L_0x2aef730/d .functor NOT 1, L_0x2aef630, C4<0>, C4<0>, C4<0>; +L_0x2aef730 .delay (10000,10000,10000) L_0x2aef730/d; +L_0x2aef860/d .functor NAND 1, L_0x2af0840, L_0x2af08e0, C4<1>, C4<1>; +L_0x2aef860 .delay (10000,10000,10000) L_0x2aef860/d; +L_0x2aef9c0/d .functor NAND 1, L_0x2aef860, L_0x2aef730, C4<1>, C4<1>; +L_0x2aef9c0 .delay (10000,10000,10000) L_0x2aef9c0/d; +L_0x2aefad0/d .functor NOT 1, L_0x2aef9c0, C4<0>, C4<0>, C4<0>; +L_0x2aefad0 .delay (10000,10000,10000) L_0x2aefad0/d; +v0x2823d60_0 .net "A", 0 0, L_0x2af0840; 1 drivers +v0x2823e00_0 .net "AnandB", 0 0, L_0x2aef860; 1 drivers +v0x2823ea0_0 .net "AnorB", 0 0, L_0x2aef630; 1 drivers +v0x2823f50_0 .net "AorB", 0 0, L_0x2aef730; 1 drivers +v0x2824030_0 .net "AxorB", 0 0, L_0x2aefad0; 1 drivers +v0x28240e0_0 .net "B", 0 0, L_0x2af08e0; 1 drivers +v0x28241a0_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x2824220_0 .net "OrNorXorOut", 0 0, L_0x2af04d0; 1 drivers +v0x28242a0_0 .net "XorNor", 0 0, L_0x2aeff50; 1 drivers +v0x2824370_0 .net "nXor", 0 0, L_0x2aef9c0; 1 drivers +L_0x2af00d0 .part v0x2960210_0, 2, 1; +L_0x2af06a0 .part v0x2960210_0, 0, 1; +S_0x28237f0 .scope module, "mux0" "TwoInMux" 3 184, 3 109, S_0x28231b0; + .timescale -9 -12; +L_0x2aefc30/d .functor NOT 1, L_0x2af00d0, C4<0>, C4<0>, C4<0>; +L_0x2aefc30 .delay (10000,10000,10000) L_0x2aefc30/d; +L_0x2aefcf0/d .functor AND 1, L_0x2aefad0, L_0x2aefc30, C4<1>, C4<1>; +L_0x2aefcf0 .delay (20000,20000,20000) L_0x2aefcf0/d; +L_0x2aefe00/d .functor AND 1, L_0x2aef630, L_0x2af00d0, C4<1>, C4<1>; +L_0x2aefe00 .delay (20000,20000,20000) L_0x2aefe00/d; +L_0x2aeff50/d .functor OR 1, L_0x2aefcf0, L_0x2aefe00, C4<0>, C4<0>; +L_0x2aeff50 .delay (20000,20000,20000) L_0x2aeff50/d; +v0x28238e0_0 .net "S", 0 0, L_0x2af00d0; 1 drivers +v0x28239a0_0 .alias "in0", 0 0, v0x2824030_0; +v0x2823a40_0 .alias "in1", 0 0, v0x2823ea0_0; +v0x2823ae0_0 .net "nS", 0 0, L_0x2aefc30; 1 drivers +v0x2823b60_0 .net "out0", 0 0, L_0x2aefcf0; 1 drivers +v0x2823c00_0 .net "out1", 0 0, L_0x2aefe00; 1 drivers +v0x2823ce0_0 .alias "outfinal", 0 0, v0x28242a0_0; +S_0x28232a0 .scope module, "mux1" "TwoInMux" 3 185, 3 109, S_0x28231b0; + .timescale -9 -12; +L_0x2af0170/d .functor NOT 1, L_0x2af06a0, C4<0>, C4<0>, C4<0>; +L_0x2af0170 .delay (10000,10000,10000) L_0x2af0170/d; +L_0x2af0230/d .functor AND 1, L_0x2aeff50, L_0x2af0170, C4<1>, C4<1>; +L_0x2af0230 .delay (20000,20000,20000) L_0x2af0230/d; +L_0x2af0380/d .functor AND 1, L_0x2aef730, L_0x2af06a0, C4<1>, C4<1>; +L_0x2af0380 .delay (20000,20000,20000) L_0x2af0380/d; +L_0x2af04d0/d .functor OR 1, L_0x2af0230, L_0x2af0380, C4<0>, C4<0>; +L_0x2af04d0 .delay (20000,20000,20000) L_0x2af04d0/d; +v0x2823390_0 .net "S", 0 0, L_0x2af06a0; 1 drivers +v0x2823410_0 .alias "in0", 0 0, v0x28242a0_0; +v0x28234b0_0 .alias "in1", 0 0, v0x2823f50_0; +v0x2823550_0 .net "nS", 0 0, L_0x2af0170; 1 drivers +v0x28235d0_0 .net "out0", 0 0, L_0x2af0230; 1 drivers +v0x2823670_0 .net "out1", 0 0, L_0x2af0380; 1 drivers +v0x2823750_0 .alias "outfinal", 0 0, v0x2824220_0; +S_0x2821cb0 .scope generate, "orbits[5]" "orbits[5]" 3 258, 3 258, S_0x2801850; + .timescale -9 -12; +P_0x28219c8 .param/l "i" 3 258, +C4<0101>; +S_0x2821de0 .scope module, "attempt" "OrNorXor" 3 260, 3 165, S_0x2821cb0; + .timescale -9 -12; +L_0x2af07e0/d .functor NOR 1, L_0x2af1ae0, L_0x2af1c00, C4<0>, C4<0>; +L_0x2af07e0 .delay (10000,10000,10000) L_0x2af07e0/d; +L_0x2af0a30/d .functor NOT 1, L_0x2af07e0, C4<0>, C4<0>, C4<0>; +L_0x2af0a30 .delay (10000,10000,10000) L_0x2af0a30/d; +L_0x2af0b60/d .functor NAND 1, L_0x2af1ae0, L_0x2af1c00, C4<1>, C4<1>; +L_0x2af0b60 .delay (10000,10000,10000) L_0x2af0b60/d; +L_0x2af0cc0/d .functor NAND 1, L_0x2af0b60, L_0x2af0a30, C4<1>, C4<1>; +L_0x2af0cc0 .delay (10000,10000,10000) L_0x2af0cc0/d; +L_0x2af0dd0/d .functor NOT 1, L_0x2af0cc0, C4<0>, C4<0>, C4<0>; +L_0x2af0dd0 .delay (10000,10000,10000) L_0x2af0dd0/d; +v0x2822990_0 .net "A", 0 0, L_0x2af1ae0; 1 drivers +v0x2822a30_0 .net "AnandB", 0 0, L_0x2af0b60; 1 drivers +v0x2822ad0_0 .net "AnorB", 0 0, L_0x2af07e0; 1 drivers +v0x2822b80_0 .net "AorB", 0 0, L_0x2af0a30; 1 drivers +v0x2822c60_0 .net "AxorB", 0 0, L_0x2af0dd0; 1 drivers +v0x2822d10_0 .net "B", 0 0, L_0x2af1c00; 1 drivers +v0x2822dd0_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x2822e50_0 .net "OrNorXorOut", 0 0, L_0x2af17d0; 1 drivers +v0x2822ed0_0 .net "XorNor", 0 0, L_0x2af1250; 1 drivers +v0x2822fa0_0 .net "nXor", 0 0, L_0x2af0cc0; 1 drivers +L_0x2af13d0 .part v0x2960210_0, 2, 1; +L_0x2af19a0 .part v0x2960210_0, 0, 1; +S_0x2822420 .scope module, "mux0" "TwoInMux" 3 184, 3 109, S_0x2821de0; + .timescale -9 -12; +L_0x2af0f30/d .functor NOT 1, L_0x2af13d0, C4<0>, C4<0>, C4<0>; +L_0x2af0f30 .delay (10000,10000,10000) L_0x2af0f30/d; +L_0x2af0ff0/d .functor AND 1, L_0x2af0dd0, L_0x2af0f30, C4<1>, C4<1>; +L_0x2af0ff0 .delay (20000,20000,20000) L_0x2af0ff0/d; +L_0x2af1100/d .functor AND 1, L_0x2af07e0, L_0x2af13d0, C4<1>, C4<1>; +L_0x2af1100 .delay (20000,20000,20000) L_0x2af1100/d; +L_0x2af1250/d .functor OR 1, L_0x2af0ff0, L_0x2af1100, C4<0>, C4<0>; +L_0x2af1250 .delay (20000,20000,20000) L_0x2af1250/d; +v0x2822510_0 .net "S", 0 0, L_0x2af13d0; 1 drivers +v0x28225d0_0 .alias "in0", 0 0, v0x2822c60_0; +v0x2822670_0 .alias "in1", 0 0, v0x2822ad0_0; +v0x2822710_0 .net "nS", 0 0, L_0x2af0f30; 1 drivers +v0x2822790_0 .net "out0", 0 0, L_0x2af0ff0; 1 drivers +v0x2822830_0 .net "out1", 0 0, L_0x2af1100; 1 drivers +v0x2822910_0 .alias "outfinal", 0 0, v0x2822ed0_0; +S_0x2821ed0 .scope module, "mux1" "TwoInMux" 3 185, 3 109, S_0x2821de0; + .timescale -9 -12; +L_0x2af1470/d .functor NOT 1, L_0x2af19a0, C4<0>, C4<0>, C4<0>; +L_0x2af1470 .delay (10000,10000,10000) L_0x2af1470/d; +L_0x2af1530/d .functor AND 1, L_0x2af1250, L_0x2af1470, C4<1>, C4<1>; +L_0x2af1530 .delay (20000,20000,20000) L_0x2af1530/d; +L_0x2af1680/d .functor AND 1, L_0x2af0a30, L_0x2af19a0, C4<1>, C4<1>; +L_0x2af1680 .delay (20000,20000,20000) L_0x2af1680/d; +L_0x2af17d0/d .functor OR 1, L_0x2af1530, L_0x2af1680, C4<0>, C4<0>; +L_0x2af17d0 .delay (20000,20000,20000) L_0x2af17d0/d; +v0x2821fc0_0 .net "S", 0 0, L_0x2af19a0; 1 drivers +v0x2822040_0 .alias "in0", 0 0, v0x2822ed0_0; +v0x28220e0_0 .alias "in1", 0 0, v0x2822b80_0; +v0x2822180_0 .net "nS", 0 0, L_0x2af1470; 1 drivers +v0x2822200_0 .net "out0", 0 0, L_0x2af1530; 1 drivers +v0x28222a0_0 .net "out1", 0 0, L_0x2af1680; 1 drivers +v0x2822380_0 .alias "outfinal", 0 0, v0x2822e50_0; +S_0x28208e0 .scope generate, "orbits[6]" "orbits[6]" 3 258, 3 258, S_0x2801850; + .timescale -9 -12; +P_0x28205f8 .param/l "i" 3 258, +C4<0110>; +S_0x2820a10 .scope module, "attempt" "OrNorXor" 3 260, 3 165, S_0x28208e0; + .timescale -9 -12; +L_0x2af1ca0/d .functor NOR 1, L_0x2af2ed0, L_0x2af2f70, C4<0>, C4<0>; +L_0x2af1ca0 .delay (10000,10000,10000) L_0x2af1ca0/d; +L_0x2af1d90/d .functor NOT 1, L_0x2af1ca0, C4<0>, C4<0>, C4<0>; +L_0x2af1d90 .delay (10000,10000,10000) L_0x2af1d90/d; +L_0x2af1ec0/d .functor NAND 1, L_0x2af2ed0, L_0x2af2f70, C4<1>, C4<1>; +L_0x2af1ec0 .delay (10000,10000,10000) L_0x2af1ec0/d; +L_0x2af2020/d .functor NAND 1, L_0x2af1ec0, L_0x2af1d90, C4<1>, C4<1>; +L_0x2af2020 .delay (10000,10000,10000) L_0x2af2020/d; +L_0x2af2130/d .functor NOT 1, L_0x2af2020, C4<0>, C4<0>, C4<0>; +L_0x2af2130 .delay (10000,10000,10000) L_0x2af2130/d; +v0x28215c0_0 .net "A", 0 0, L_0x2af2ed0; 1 drivers +v0x2821660_0 .net "AnandB", 0 0, L_0x2af1ec0; 1 drivers +v0x2821700_0 .net "AnorB", 0 0, L_0x2af1ca0; 1 drivers +v0x28217b0_0 .net "AorB", 0 0, L_0x2af1d90; 1 drivers +v0x2821890_0 .net "AxorB", 0 0, L_0x2af2130; 1 drivers +v0x2821940_0 .net "B", 0 0, L_0x2af2f70; 1 drivers +v0x2821a00_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x2821a80_0 .net "OrNorXorOut", 0 0, L_0x2af2b30; 1 drivers +v0x2821b00_0 .net "XorNor", 0 0, L_0x2af25b0; 1 drivers +v0x2821bd0_0 .net "nXor", 0 0, L_0x2af2020; 1 drivers +L_0x2af2730 .part v0x2960210_0, 2, 1; +L_0x2af2d00 .part v0x2960210_0, 0, 1; +S_0x2821050 .scope module, "mux0" "TwoInMux" 3 184, 3 109, S_0x2820a10; + .timescale -9 -12; +L_0x2af2290/d .functor NOT 1, L_0x2af2730, C4<0>, C4<0>, C4<0>; +L_0x2af2290 .delay (10000,10000,10000) L_0x2af2290/d; +L_0x2af2350/d .functor AND 1, L_0x2af2130, L_0x2af2290, C4<1>, C4<1>; +L_0x2af2350 .delay (20000,20000,20000) L_0x2af2350/d; +L_0x2af2460/d .functor AND 1, L_0x2af1ca0, L_0x2af2730, C4<1>, C4<1>; +L_0x2af2460 .delay (20000,20000,20000) L_0x2af2460/d; +L_0x2af25b0/d .functor OR 1, L_0x2af2350, L_0x2af2460, C4<0>, C4<0>; +L_0x2af25b0 .delay (20000,20000,20000) L_0x2af25b0/d; +v0x2821140_0 .net "S", 0 0, L_0x2af2730; 1 drivers +v0x2821200_0 .alias "in0", 0 0, v0x2821890_0; +v0x28212a0_0 .alias "in1", 0 0, v0x2821700_0; +v0x2821340_0 .net "nS", 0 0, L_0x2af2290; 1 drivers +v0x28213c0_0 .net "out0", 0 0, L_0x2af2350; 1 drivers +v0x2821460_0 .net "out1", 0 0, L_0x2af2460; 1 drivers +v0x2821540_0 .alias "outfinal", 0 0, v0x2821b00_0; +S_0x2820b00 .scope module, "mux1" "TwoInMux" 3 185, 3 109, S_0x2820a10; + .timescale -9 -12; +L_0x2af27d0/d .functor NOT 1, L_0x2af2d00, C4<0>, C4<0>, C4<0>; +L_0x2af27d0 .delay (10000,10000,10000) L_0x2af27d0/d; +L_0x2af2890/d .functor AND 1, L_0x2af25b0, L_0x2af27d0, C4<1>, C4<1>; +L_0x2af2890 .delay (20000,20000,20000) L_0x2af2890/d; +L_0x2af29e0/d .functor AND 1, L_0x2af1d90, L_0x2af2d00, C4<1>, C4<1>; +L_0x2af29e0 .delay (20000,20000,20000) L_0x2af29e0/d; +L_0x2af2b30/d .functor OR 1, L_0x2af2890, L_0x2af29e0, C4<0>, C4<0>; +L_0x2af2b30 .delay (20000,20000,20000) L_0x2af2b30/d; +v0x2820bf0_0 .net "S", 0 0, L_0x2af2d00; 1 drivers +v0x2820c70_0 .alias "in0", 0 0, v0x2821b00_0; +v0x2820d10_0 .alias "in1", 0 0, v0x28217b0_0; +v0x2820db0_0 .net "nS", 0 0, L_0x2af27d0; 1 drivers +v0x2820e30_0 .net "out0", 0 0, L_0x2af2890; 1 drivers +v0x2820ed0_0 .net "out1", 0 0, L_0x2af29e0; 1 drivers +v0x2820fb0_0 .alias "outfinal", 0 0, v0x2821a80_0; +S_0x281f510 .scope generate, "orbits[7]" "orbits[7]" 3 258, 3 258, S_0x2801850; + .timescale -9 -12; +P_0x281f228 .param/l "i" 3 258, +C4<0111>; +S_0x281f640 .scope module, "attempt" "OrNorXor" 3 260, 3 165, S_0x281f510; + .timescale -9 -12; +L_0x2af2e40/d .functor NOR 1, L_0x2af41d0, L_0x2af3010, C4<0>, C4<0>; +L_0x2af2e40 .delay (10000,10000,10000) L_0x2af2e40/d; +L_0x2af3140/d .functor NOT 1, L_0x2af2e40, C4<0>, C4<0>, C4<0>; +L_0x2af3140 .delay (10000,10000,10000) L_0x2af3140/d; +L_0x2af3250/d .functor NAND 1, L_0x2af41d0, L_0x2af3010, C4<1>, C4<1>; +L_0x2af3250 .delay (10000,10000,10000) L_0x2af3250/d; +L_0x2af33b0/d .functor NAND 1, L_0x2af3250, L_0x2af3140, C4<1>, C4<1>; +L_0x2af33b0 .delay (10000,10000,10000) L_0x2af33b0/d; +L_0x2af34c0/d .functor NOT 1, L_0x2af33b0, C4<0>, C4<0>, C4<0>; +L_0x2af34c0 .delay (10000,10000,10000) L_0x2af34c0/d; +v0x28201f0_0 .net "A", 0 0, L_0x2af41d0; 1 drivers +v0x2820290_0 .net "AnandB", 0 0, L_0x2af3250; 1 drivers +v0x2820330_0 .net "AnorB", 0 0, L_0x2af2e40; 1 drivers +v0x28203e0_0 .net "AorB", 0 0, L_0x2af3140; 1 drivers +v0x28204c0_0 .net "AxorB", 0 0, L_0x2af34c0; 1 drivers +v0x2820570_0 .net "B", 0 0, L_0x2af3010; 1 drivers +v0x2820630_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x28206b0_0 .net "OrNorXorOut", 0 0, L_0x2af3ec0; 1 drivers +v0x2820730_0 .net "XorNor", 0 0, L_0x2af3940; 1 drivers +v0x2820800_0 .net "nXor", 0 0, L_0x2af33b0; 1 drivers +L_0x2af3ac0 .part v0x2960210_0, 2, 1; +L_0x2af4090 .part v0x2960210_0, 0, 1; +S_0x281fc80 .scope module, "mux0" "TwoInMux" 3 184, 3 109, S_0x281f640; + .timescale -9 -12; +L_0x2af3620/d .functor NOT 1, L_0x2af3ac0, C4<0>, C4<0>, C4<0>; +L_0x2af3620 .delay (10000,10000,10000) L_0x2af3620/d; +L_0x2af36e0/d .functor AND 1, L_0x2af34c0, L_0x2af3620, C4<1>, C4<1>; +L_0x2af36e0 .delay (20000,20000,20000) L_0x2af36e0/d; +L_0x2af37f0/d .functor AND 1, L_0x2af2e40, L_0x2af3ac0, C4<1>, C4<1>; +L_0x2af37f0 .delay (20000,20000,20000) L_0x2af37f0/d; +L_0x2af3940/d .functor OR 1, L_0x2af36e0, L_0x2af37f0, C4<0>, C4<0>; +L_0x2af3940 .delay (20000,20000,20000) L_0x2af3940/d; +v0x281fd70_0 .net "S", 0 0, L_0x2af3ac0; 1 drivers +v0x281fe30_0 .alias "in0", 0 0, v0x28204c0_0; +v0x281fed0_0 .alias "in1", 0 0, v0x2820330_0; +v0x281ff70_0 .net "nS", 0 0, L_0x2af3620; 1 drivers +v0x281fff0_0 .net "out0", 0 0, L_0x2af36e0; 1 drivers +v0x2820090_0 .net "out1", 0 0, L_0x2af37f0; 1 drivers +v0x2820170_0 .alias "outfinal", 0 0, v0x2820730_0; +S_0x281f730 .scope module, "mux1" "TwoInMux" 3 185, 3 109, S_0x281f640; + .timescale -9 -12; +L_0x2af3b60/d .functor NOT 1, L_0x2af4090, C4<0>, C4<0>, C4<0>; +L_0x2af3b60 .delay (10000,10000,10000) L_0x2af3b60/d; +L_0x2af3c20/d .functor AND 1, L_0x2af3940, L_0x2af3b60, C4<1>, C4<1>; +L_0x2af3c20 .delay (20000,20000,20000) L_0x2af3c20/d; +L_0x2af3d70/d .functor AND 1, L_0x2af3140, L_0x2af4090, C4<1>, C4<1>; +L_0x2af3d70 .delay (20000,20000,20000) L_0x2af3d70/d; +L_0x2af3ec0/d .functor OR 1, L_0x2af3c20, L_0x2af3d70, C4<0>, C4<0>; +L_0x2af3ec0 .delay (20000,20000,20000) L_0x2af3ec0/d; +v0x281f820_0 .net "S", 0 0, L_0x2af4090; 1 drivers +v0x281f8a0_0 .alias "in0", 0 0, v0x2820730_0; +v0x281f940_0 .alias "in1", 0 0, v0x28203e0_0; +v0x281f9e0_0 .net "nS", 0 0, L_0x2af3b60; 1 drivers +v0x281fa60_0 .net "out0", 0 0, L_0x2af3c20; 1 drivers +v0x281fb00_0 .net "out1", 0 0, L_0x2af3d70; 1 drivers +v0x281fbe0_0 .alias "outfinal", 0 0, v0x28206b0_0; +S_0x281e140 .scope generate, "orbits[8]" "orbits[8]" 3 258, 3 258, S_0x2801850; + .timescale -9 -12; +P_0x281de58 .param/l "i" 3 258, +C4<01000>; +S_0x281e270 .scope module, "attempt" "OrNorXor" 3 260, 3 165, S_0x281e140; + .timescale -9 -12; +L_0x2af4320/d .functor NOR 1, L_0x2af4270, L_0x2af5580, C4<0>, C4<0>; +L_0x2af4320 .delay (10000,10000,10000) L_0x2af4320/d; +L_0x2af4410/d .functor NOT 1, L_0x2af4320, C4<0>, C4<0>, C4<0>; +L_0x2af4410 .delay (10000,10000,10000) L_0x2af4410/d; +L_0x2af4540/d .functor NAND 1, L_0x2af4270, L_0x2af5580, C4<1>, C4<1>; +L_0x2af4540 .delay (10000,10000,10000) L_0x2af4540/d; +L_0x2af46a0/d .functor NAND 1, L_0x2af4540, L_0x2af4410, C4<1>, C4<1>; +L_0x2af46a0 .delay (10000,10000,10000) L_0x2af46a0/d; +L_0x2af47b0/d .functor NOT 1, L_0x2af46a0, C4<0>, C4<0>, C4<0>; +L_0x2af47b0 .delay (10000,10000,10000) L_0x2af47b0/d; +v0x281ee20_0 .net "A", 0 0, L_0x2af4270; 1 drivers +v0x281eec0_0 .net "AnandB", 0 0, L_0x2af4540; 1 drivers +v0x281ef60_0 .net "AnorB", 0 0, L_0x2af4320; 1 drivers +v0x281f010_0 .net "AorB", 0 0, L_0x2af4410; 1 drivers +v0x281f0f0_0 .net "AxorB", 0 0, L_0x2af47b0; 1 drivers +v0x281f1a0_0 .net "B", 0 0, L_0x2af5580; 1 drivers +v0x281f260_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x281f2e0_0 .net "OrNorXorOut", 0 0, L_0x2af51b0; 1 drivers +v0x281f360_0 .net "XorNor", 0 0, L_0x2af4c30; 1 drivers +v0x281f430_0 .net "nXor", 0 0, L_0x2af46a0; 1 drivers +L_0x2af4db0 .part v0x2960210_0, 2, 1; +L_0x2af5380 .part v0x2960210_0, 0, 1; +S_0x281e8b0 .scope module, "mux0" "TwoInMux" 3 184, 3 109, S_0x281e270; + .timescale -9 -12; +L_0x2af4910/d .functor NOT 1, L_0x2af4db0, C4<0>, C4<0>, C4<0>; +L_0x2af4910 .delay (10000,10000,10000) L_0x2af4910/d; +L_0x2af49d0/d .functor AND 1, L_0x2af47b0, L_0x2af4910, C4<1>, C4<1>; +L_0x2af49d0 .delay (20000,20000,20000) L_0x2af49d0/d; +L_0x2af4ae0/d .functor AND 1, L_0x2af4320, L_0x2af4db0, C4<1>, C4<1>; +L_0x2af4ae0 .delay (20000,20000,20000) L_0x2af4ae0/d; +L_0x2af4c30/d .functor OR 1, L_0x2af49d0, L_0x2af4ae0, C4<0>, C4<0>; +L_0x2af4c30 .delay (20000,20000,20000) L_0x2af4c30/d; +v0x281e9a0_0 .net "S", 0 0, L_0x2af4db0; 1 drivers +v0x281ea60_0 .alias "in0", 0 0, v0x281f0f0_0; +v0x281eb00_0 .alias "in1", 0 0, v0x281ef60_0; +v0x281eba0_0 .net "nS", 0 0, L_0x2af4910; 1 drivers +v0x281ec20_0 .net "out0", 0 0, L_0x2af49d0; 1 drivers +v0x281ecc0_0 .net "out1", 0 0, L_0x2af4ae0; 1 drivers +v0x281eda0_0 .alias "outfinal", 0 0, v0x281f360_0; +S_0x281e360 .scope module, "mux1" "TwoInMux" 3 185, 3 109, S_0x281e270; + .timescale -9 -12; +L_0x2af4e50/d .functor NOT 1, L_0x2af5380, C4<0>, C4<0>, C4<0>; +L_0x2af4e50 .delay (10000,10000,10000) L_0x2af4e50/d; +L_0x2af4f10/d .functor AND 1, L_0x2af4c30, L_0x2af4e50, C4<1>, C4<1>; +L_0x2af4f10 .delay (20000,20000,20000) L_0x2af4f10/d; +L_0x2af5060/d .functor AND 1, L_0x2af4410, L_0x2af5380, C4<1>, C4<1>; +L_0x2af5060 .delay (20000,20000,20000) L_0x2af5060/d; +L_0x2af51b0/d .functor OR 1, L_0x2af4f10, L_0x2af5060, C4<0>, C4<0>; +L_0x2af51b0 .delay (20000,20000,20000) L_0x2af51b0/d; +v0x281e450_0 .net "S", 0 0, L_0x2af5380; 1 drivers +v0x281e4d0_0 .alias "in0", 0 0, v0x281f360_0; +v0x281e570_0 .alias "in1", 0 0, v0x281f010_0; +v0x281e610_0 .net "nS", 0 0, L_0x2af4e50; 1 drivers +v0x281e690_0 .net "out0", 0 0, L_0x2af4f10; 1 drivers +v0x281e730_0 .net "out1", 0 0, L_0x2af5060; 1 drivers +v0x281e810_0 .alias "outfinal", 0 0, v0x281f2e0_0; +S_0x281cd70 .scope generate, "orbits[9]" "orbits[9]" 3 258, 3 258, S_0x2801850; + .timescale -9 -12; +P_0x281ca88 .param/l "i" 3 258, +C4<01001>; +S_0x281cea0 .scope module, "attempt" "OrNorXor" 3 260, 3 165, S_0x281cd70; + .timescale -9 -12; +L_0x2af54c0/d .functor NOR 1, L_0x2af67d0, L_0x2af5620, C4<0>, C4<0>; +L_0x2af54c0 .delay (10000,10000,10000) L_0x2af54c0/d; +L_0x2af5740/d .functor NOT 1, L_0x2af54c0, C4<0>, C4<0>, C4<0>; +L_0x2af5740 .delay (10000,10000,10000) L_0x2af5740/d; +L_0x2af5850/d .functor NAND 1, L_0x2af67d0, L_0x2af5620, C4<1>, C4<1>; +L_0x2af5850 .delay (10000,10000,10000) L_0x2af5850/d; +L_0x2af59b0/d .functor NAND 1, L_0x2af5850, L_0x2af5740, C4<1>, C4<1>; +L_0x2af59b0 .delay (10000,10000,10000) L_0x2af59b0/d; +L_0x2af5ac0/d .functor NOT 1, L_0x2af59b0, C4<0>, C4<0>, C4<0>; +L_0x2af5ac0 .delay (10000,10000,10000) L_0x2af5ac0/d; +v0x281da50_0 .net "A", 0 0, L_0x2af67d0; 1 drivers +v0x281daf0_0 .net "AnandB", 0 0, L_0x2af5850; 1 drivers +v0x281db90_0 .net "AnorB", 0 0, L_0x2af54c0; 1 drivers +v0x281dc40_0 .net "AorB", 0 0, L_0x2af5740; 1 drivers +v0x281dd20_0 .net "AxorB", 0 0, L_0x2af5ac0; 1 drivers +v0x281ddd0_0 .net "B", 0 0, L_0x2af5620; 1 drivers +v0x281de90_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x281df10_0 .net "OrNorXorOut", 0 0, L_0x2af64c0; 1 drivers +v0x281df90_0 .net "XorNor", 0 0, L_0x2af5f40; 1 drivers +v0x281e060_0 .net "nXor", 0 0, L_0x2af59b0; 1 drivers +L_0x2af60c0 .part v0x2960210_0, 2, 1; +L_0x2af6690 .part v0x2960210_0, 0, 1; +S_0x281d4e0 .scope module, "mux0" "TwoInMux" 3 184, 3 109, S_0x281cea0; + .timescale -9 -12; +L_0x2af5c20/d .functor NOT 1, L_0x2af60c0, C4<0>, C4<0>, C4<0>; +L_0x2af5c20 .delay (10000,10000,10000) L_0x2af5c20/d; +L_0x2af5ce0/d .functor AND 1, L_0x2af5ac0, L_0x2af5c20, C4<1>, C4<1>; +L_0x2af5ce0 .delay (20000,20000,20000) L_0x2af5ce0/d; +L_0x2af5df0/d .functor AND 1, L_0x2af54c0, L_0x2af60c0, C4<1>, C4<1>; +L_0x2af5df0 .delay (20000,20000,20000) L_0x2af5df0/d; +L_0x2af5f40/d .functor OR 1, L_0x2af5ce0, L_0x2af5df0, C4<0>, C4<0>; +L_0x2af5f40 .delay (20000,20000,20000) L_0x2af5f40/d; +v0x281d5d0_0 .net "S", 0 0, L_0x2af60c0; 1 drivers +v0x281d690_0 .alias "in0", 0 0, v0x281dd20_0; +v0x281d730_0 .alias "in1", 0 0, v0x281db90_0; +v0x281d7d0_0 .net "nS", 0 0, L_0x2af5c20; 1 drivers +v0x281d850_0 .net "out0", 0 0, L_0x2af5ce0; 1 drivers +v0x281d8f0_0 .net "out1", 0 0, L_0x2af5df0; 1 drivers +v0x281d9d0_0 .alias "outfinal", 0 0, v0x281df90_0; +S_0x281cf90 .scope module, "mux1" "TwoInMux" 3 185, 3 109, S_0x281cea0; + .timescale -9 -12; +L_0x2af6160/d .functor NOT 1, L_0x2af6690, C4<0>, C4<0>, C4<0>; +L_0x2af6160 .delay (10000,10000,10000) L_0x2af6160/d; +L_0x2af6220/d .functor AND 1, L_0x2af5f40, L_0x2af6160, C4<1>, C4<1>; +L_0x2af6220 .delay (20000,20000,20000) L_0x2af6220/d; +L_0x2af6370/d .functor AND 1, L_0x2af5740, L_0x2af6690, C4<1>, C4<1>; +L_0x2af6370 .delay (20000,20000,20000) L_0x2af6370/d; +L_0x2af64c0/d .functor OR 1, L_0x2af6220, L_0x2af6370, C4<0>, C4<0>; +L_0x2af64c0 .delay (20000,20000,20000) L_0x2af64c0/d; +v0x281d080_0 .net "S", 0 0, L_0x2af6690; 1 drivers +v0x281d100_0 .alias "in0", 0 0, v0x281df90_0; +v0x281d1a0_0 .alias "in1", 0 0, v0x281dc40_0; +v0x281d240_0 .net "nS", 0 0, L_0x2af6160; 1 drivers +v0x281d2c0_0 .net "out0", 0 0, L_0x2af6220; 1 drivers +v0x281d360_0 .net "out1", 0 0, L_0x2af6370; 1 drivers +v0x281d440_0 .alias "outfinal", 0 0, v0x281df10_0; +S_0x281b9a0 .scope generate, "orbits[10]" "orbits[10]" 3 258, 3 258, S_0x2801850; + .timescale -9 -12; +P_0x281b6b8 .param/l "i" 3 258, +C4<01010>; +S_0x281bad0 .scope module, "attempt" "OrNorXor" 3 260, 3 165, S_0x281b9a0; + .timescale -9 -12; +L_0x2af6950/d .functor NOR 1, L_0x2af6870, L_0x2af7bc0, C4<0>, C4<0>; +L_0x2af6950 .delay (10000,10000,10000) L_0x2af6950/d; +L_0x2af6a40/d .functor NOT 1, L_0x2af6950, C4<0>, C4<0>, C4<0>; +L_0x2af6a40 .delay (10000,10000,10000) L_0x2af6a40/d; +L_0x2af6b50/d .functor NAND 1, L_0x2af6870, L_0x2af7bc0, C4<1>, C4<1>; +L_0x2af6b50 .delay (10000,10000,10000) L_0x2af6b50/d; +L_0x2af6cb0/d .functor NAND 1, L_0x2af6b50, L_0x2af6a40, C4<1>, C4<1>; +L_0x2af6cb0 .delay (10000,10000,10000) L_0x2af6cb0/d; +L_0x2af6dc0/d .functor NOT 1, L_0x2af6cb0, C4<0>, C4<0>, C4<0>; +L_0x2af6dc0 .delay (10000,10000,10000) L_0x2af6dc0/d; +v0x281c680_0 .net "A", 0 0, L_0x2af6870; 1 drivers +v0x281c720_0 .net "AnandB", 0 0, L_0x2af6b50; 1 drivers +v0x281c7c0_0 .net "AnorB", 0 0, L_0x2af6950; 1 drivers +v0x281c870_0 .net "AorB", 0 0, L_0x2af6a40; 1 drivers +v0x281c950_0 .net "AxorB", 0 0, L_0x2af6dc0; 1 drivers +v0x281ca00_0 .net "B", 0 0, L_0x2af7bc0; 1 drivers +v0x281cac0_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x281cb40_0 .net "OrNorXorOut", 0 0, L_0x2af77c0; 1 drivers +v0x281cbc0_0 .net "XorNor", 0 0, L_0x2af7240; 1 drivers +v0x281cc90_0 .net "nXor", 0 0, L_0x2af6cb0; 1 drivers +L_0x2af73c0 .part v0x2960210_0, 2, 1; +L_0x2af7990 .part v0x2960210_0, 0, 1; +S_0x281c110 .scope module, "mux0" "TwoInMux" 3 184, 3 109, S_0x281bad0; + .timescale -9 -12; +L_0x2af6f20/d .functor NOT 1, L_0x2af73c0, C4<0>, C4<0>, C4<0>; +L_0x2af6f20 .delay (10000,10000,10000) L_0x2af6f20/d; +L_0x2af6fe0/d .functor AND 1, L_0x2af6dc0, L_0x2af6f20, C4<1>, C4<1>; +L_0x2af6fe0 .delay (20000,20000,20000) L_0x2af6fe0/d; +L_0x2af70f0/d .functor AND 1, L_0x2af6950, L_0x2af73c0, C4<1>, C4<1>; +L_0x2af70f0 .delay (20000,20000,20000) L_0x2af70f0/d; +L_0x2af7240/d .functor OR 1, L_0x2af6fe0, L_0x2af70f0, C4<0>, C4<0>; +L_0x2af7240 .delay (20000,20000,20000) L_0x2af7240/d; +v0x281c200_0 .net "S", 0 0, L_0x2af73c0; 1 drivers +v0x281c2c0_0 .alias "in0", 0 0, v0x281c950_0; +v0x281c360_0 .alias "in1", 0 0, v0x281c7c0_0; +v0x281c400_0 .net "nS", 0 0, L_0x2af6f20; 1 drivers +v0x281c480_0 .net "out0", 0 0, L_0x2af6fe0; 1 drivers +v0x281c520_0 .net "out1", 0 0, L_0x2af70f0; 1 drivers +v0x281c600_0 .alias "outfinal", 0 0, v0x281cbc0_0; +S_0x281bbc0 .scope module, "mux1" "TwoInMux" 3 185, 3 109, S_0x281bad0; + .timescale -9 -12; +L_0x2af7460/d .functor NOT 1, L_0x2af7990, C4<0>, C4<0>, C4<0>; +L_0x2af7460 .delay (10000,10000,10000) L_0x2af7460/d; +L_0x2af7520/d .functor AND 1, L_0x2af7240, L_0x2af7460, C4<1>, C4<1>; +L_0x2af7520 .delay (20000,20000,20000) L_0x2af7520/d; +L_0x2af7670/d .functor AND 1, L_0x2af6a40, L_0x2af7990, C4<1>, C4<1>; +L_0x2af7670 .delay (20000,20000,20000) L_0x2af7670/d; +L_0x2af77c0/d .functor OR 1, L_0x2af7520, L_0x2af7670, C4<0>, C4<0>; +L_0x2af77c0 .delay (20000,20000,20000) L_0x2af77c0/d; +v0x281bcb0_0 .net "S", 0 0, L_0x2af7990; 1 drivers +v0x281bd30_0 .alias "in0", 0 0, v0x281cbc0_0; +v0x281bdd0_0 .alias "in1", 0 0, v0x281c870_0; +v0x281be70_0 .net "nS", 0 0, L_0x2af7460; 1 drivers +v0x281bef0_0 .net "out0", 0 0, L_0x2af7520; 1 drivers +v0x281bf90_0 .net "out1", 0 0, L_0x2af7670; 1 drivers +v0x281c070_0 .alias "outfinal", 0 0, v0x281cb40_0; +S_0x281a5d0 .scope generate, "orbits[11]" "orbits[11]" 3 258, 3 258, S_0x2801850; + .timescale -9 -12; +P_0x281a2e8 .param/l "i" 3 258, +C4<01011>; +S_0x281a700 .scope module, "attempt" "OrNorXor" 3 260, 3 165, S_0x281a5d0; + .timescale -9 -12; +L_0x2af7ad0/d .functor NOR 1, L_0x2af8dd0, L_0x2af7c60, C4<0>, C4<0>; +L_0x2af7ad0 .delay (10000,10000,10000) L_0x2af7ad0/d; +L_0x2af7d60/d .functor NOT 1, L_0x2af7ad0, C4<0>, C4<0>, C4<0>; +L_0x2af7d60 .delay (10000,10000,10000) L_0x2af7d60/d; +L_0x2af7e50/d .functor NAND 1, L_0x2af8dd0, L_0x2af7c60, C4<1>, C4<1>; +L_0x2af7e50 .delay (10000,10000,10000) L_0x2af7e50/d; +L_0x2af7fb0/d .functor NAND 1, L_0x2af7e50, L_0x2af7d60, C4<1>, C4<1>; +L_0x2af7fb0 .delay (10000,10000,10000) L_0x2af7fb0/d; +L_0x2af80c0/d .functor NOT 1, L_0x2af7fb0, C4<0>, C4<0>, C4<0>; +L_0x2af80c0 .delay (10000,10000,10000) L_0x2af80c0/d; +v0x281b2b0_0 .net "A", 0 0, L_0x2af8dd0; 1 drivers +v0x281b350_0 .net "AnandB", 0 0, L_0x2af7e50; 1 drivers +v0x281b3f0_0 .net "AnorB", 0 0, L_0x2af7ad0; 1 drivers +v0x281b4a0_0 .net "AorB", 0 0, L_0x2af7d60; 1 drivers +v0x281b580_0 .net "AxorB", 0 0, L_0x2af80c0; 1 drivers +v0x281b630_0 .net "B", 0 0, L_0x2af7c60; 1 drivers +v0x281b6f0_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x281b770_0 .net "OrNorXorOut", 0 0, L_0x2af8ac0; 1 drivers +v0x281b7f0_0 .net "XorNor", 0 0, L_0x2af8540; 1 drivers +v0x281b8c0_0 .net "nXor", 0 0, L_0x2af7fb0; 1 drivers +L_0x2af86c0 .part v0x2960210_0, 2, 1; +L_0x2af8c90 .part v0x2960210_0, 0, 1; +S_0x281ad40 .scope module, "mux0" "TwoInMux" 3 184, 3 109, S_0x281a700; + .timescale -9 -12; +L_0x2af8220/d .functor NOT 1, L_0x2af86c0, C4<0>, C4<0>, C4<0>; +L_0x2af8220 .delay (10000,10000,10000) L_0x2af8220/d; +L_0x2af82e0/d .functor AND 1, L_0x2af80c0, L_0x2af8220, C4<1>, C4<1>; +L_0x2af82e0 .delay (20000,20000,20000) L_0x2af82e0/d; +L_0x2af83f0/d .functor AND 1, L_0x2af7ad0, L_0x2af86c0, C4<1>, C4<1>; +L_0x2af83f0 .delay (20000,20000,20000) L_0x2af83f0/d; +L_0x2af8540/d .functor OR 1, L_0x2af82e0, L_0x2af83f0, C4<0>, C4<0>; +L_0x2af8540 .delay (20000,20000,20000) L_0x2af8540/d; +v0x281ae30_0 .net "S", 0 0, L_0x2af86c0; 1 drivers +v0x281aef0_0 .alias "in0", 0 0, v0x281b580_0; +v0x281af90_0 .alias "in1", 0 0, v0x281b3f0_0; +v0x281b030_0 .net "nS", 0 0, L_0x2af8220; 1 drivers +v0x281b0b0_0 .net "out0", 0 0, L_0x2af82e0; 1 drivers +v0x281b150_0 .net "out1", 0 0, L_0x2af83f0; 1 drivers +v0x281b230_0 .alias "outfinal", 0 0, v0x281b7f0_0; +S_0x281a7f0 .scope module, "mux1" "TwoInMux" 3 185, 3 109, S_0x281a700; + .timescale -9 -12; +L_0x2af8760/d .functor NOT 1, L_0x2af8c90, C4<0>, C4<0>, C4<0>; +L_0x2af8760 .delay (10000,10000,10000) L_0x2af8760/d; +L_0x2af8820/d .functor AND 1, L_0x2af8540, L_0x2af8760, C4<1>, C4<1>; +L_0x2af8820 .delay (20000,20000,20000) L_0x2af8820/d; +L_0x2af8970/d .functor AND 1, L_0x2af7d60, L_0x2af8c90, C4<1>, C4<1>; +L_0x2af8970 .delay (20000,20000,20000) L_0x2af8970/d; +L_0x2af8ac0/d .functor OR 1, L_0x2af8820, L_0x2af8970, C4<0>, C4<0>; +L_0x2af8ac0 .delay (20000,20000,20000) L_0x2af8ac0/d; +v0x281a8e0_0 .net "S", 0 0, L_0x2af8c90; 1 drivers +v0x281a960_0 .alias "in0", 0 0, v0x281b7f0_0; +v0x281aa00_0 .alias "in1", 0 0, v0x281b4a0_0; +v0x281aaa0_0 .net "nS", 0 0, L_0x2af8760; 1 drivers +v0x281ab20_0 .net "out0", 0 0, L_0x2af8820; 1 drivers +v0x281abc0_0 .net "out1", 0 0, L_0x2af8970; 1 drivers +v0x281aca0_0 .alias "outfinal", 0 0, v0x281b770_0; +S_0x2819200 .scope generate, "orbits[12]" "orbits[12]" 3 258, 3 258, S_0x2801850; + .timescale -9 -12; +P_0x2818f18 .param/l "i" 3 258, +C4<01100>; +S_0x2819330 .scope module, "attempt" "OrNorXor" 3 260, 3 165, S_0x2819200; + .timescale -9 -12; +L_0x2af7d00/d .functor NOR 1, L_0x2af8e70, L_0x2afa1e0, C4<0>, C4<0>; +L_0x2af7d00 .delay (10000,10000,10000) L_0x2af7d00/d; +L_0x2af9010/d .functor NOT 1, L_0x2af7d00, C4<0>, C4<0>, C4<0>; +L_0x2af9010 .delay (10000,10000,10000) L_0x2af9010/d; +L_0x2af9140/d .functor NAND 1, L_0x2af8e70, L_0x2afa1e0, C4<1>, C4<1>; +L_0x2af9140 .delay (10000,10000,10000) L_0x2af9140/d; +L_0x2af92a0/d .functor NAND 1, L_0x2af9140, L_0x2af9010, C4<1>, C4<1>; +L_0x2af92a0 .delay (10000,10000,10000) L_0x2af92a0/d; +L_0x2af93b0/d .functor NOT 1, L_0x2af92a0, C4<0>, C4<0>, C4<0>; +L_0x2af93b0 .delay (10000,10000,10000) L_0x2af93b0/d; +v0x2819ee0_0 .net "A", 0 0, L_0x2af8e70; 1 drivers +v0x2819f80_0 .net "AnandB", 0 0, L_0x2af9140; 1 drivers +v0x281a020_0 .net "AnorB", 0 0, L_0x2af7d00; 1 drivers +v0x281a0d0_0 .net "AorB", 0 0, L_0x2af9010; 1 drivers +v0x281a1b0_0 .net "AxorB", 0 0, L_0x2af93b0; 1 drivers +v0x281a260_0 .net "B", 0 0, L_0x2afa1e0; 1 drivers +v0x281a320_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x281a3a0_0 .net "OrNorXorOut", 0 0, L_0x2af9db0; 1 drivers +v0x281a420_0 .net "XorNor", 0 0, L_0x2af9830; 1 drivers +v0x281a4f0_0 .net "nXor", 0 0, L_0x2af92a0; 1 drivers +L_0x2af99b0 .part v0x2960210_0, 2, 1; +L_0x2af9f80 .part v0x2960210_0, 0, 1; +S_0x2819970 .scope module, "mux0" "TwoInMux" 3 184, 3 109, S_0x2819330; + .timescale -9 -12; +L_0x2af9510/d .functor NOT 1, L_0x2af99b0, C4<0>, C4<0>, C4<0>; +L_0x2af9510 .delay (10000,10000,10000) L_0x2af9510/d; +L_0x2af95d0/d .functor AND 1, L_0x2af93b0, L_0x2af9510, C4<1>, C4<1>; +L_0x2af95d0 .delay (20000,20000,20000) L_0x2af95d0/d; +L_0x2af96e0/d .functor AND 1, L_0x2af7d00, L_0x2af99b0, C4<1>, C4<1>; +L_0x2af96e0 .delay (20000,20000,20000) L_0x2af96e0/d; +L_0x2af9830/d .functor OR 1, L_0x2af95d0, L_0x2af96e0, C4<0>, C4<0>; +L_0x2af9830 .delay (20000,20000,20000) L_0x2af9830/d; +v0x2819a60_0 .net "S", 0 0, L_0x2af99b0; 1 drivers +v0x2819b20_0 .alias "in0", 0 0, v0x281a1b0_0; +v0x2819bc0_0 .alias "in1", 0 0, v0x281a020_0; +v0x2819c60_0 .net "nS", 0 0, L_0x2af9510; 1 drivers +v0x2819ce0_0 .net "out0", 0 0, L_0x2af95d0; 1 drivers +v0x2819d80_0 .net "out1", 0 0, L_0x2af96e0; 1 drivers +v0x2819e60_0 .alias "outfinal", 0 0, v0x281a420_0; +S_0x2819420 .scope module, "mux1" "TwoInMux" 3 185, 3 109, S_0x2819330; + .timescale -9 -12; +L_0x2af9a50/d .functor NOT 1, L_0x2af9f80, C4<0>, C4<0>, C4<0>; +L_0x2af9a50 .delay (10000,10000,10000) L_0x2af9a50/d; +L_0x2af9b10/d .functor AND 1, L_0x2af9830, L_0x2af9a50, C4<1>, C4<1>; +L_0x2af9b10 .delay (20000,20000,20000) L_0x2af9b10/d; +L_0x2af9c60/d .functor AND 1, L_0x2af9010, L_0x2af9f80, C4<1>, C4<1>; +L_0x2af9c60 .delay (20000,20000,20000) L_0x2af9c60/d; +L_0x2af9db0/d .functor OR 1, L_0x2af9b10, L_0x2af9c60, C4<0>, C4<0>; +L_0x2af9db0 .delay (20000,20000,20000) L_0x2af9db0/d; +v0x2819510_0 .net "S", 0 0, L_0x2af9f80; 1 drivers +v0x2819590_0 .alias "in0", 0 0, v0x281a420_0; +v0x2819630_0 .alias "in1", 0 0, v0x281a0d0_0; +v0x28196d0_0 .net "nS", 0 0, L_0x2af9a50; 1 drivers +v0x2819750_0 .net "out0", 0 0, L_0x2af9b10; 1 drivers +v0x28197f0_0 .net "out1", 0 0, L_0x2af9c60; 1 drivers +v0x28198d0_0 .alias "outfinal", 0 0, v0x281a3a0_0; +S_0x2817e30 .scope generate, "orbits[13]" "orbits[13]" 3 258, 3 258, S_0x2801850; + .timescale -9 -12; +P_0x2817b48 .param/l "i" 3 258, +C4<01101>; +S_0x2817f60 .scope module, "attempt" "OrNorXor" 3 260, 3 165, S_0x2817e30; + .timescale -9 -12; +L_0x2af8f10/d .functor NOR 1, L_0x2afb3e0, L_0x2afa280, C4<0>, C4<0>; +L_0x2af8f10 .delay (10000,10000,10000) L_0x2af8f10/d; +L_0x2afa150/d .functor NOT 1, L_0x2af8f10, C4<0>, C4<0>, C4<0>; +L_0x2afa150 .delay (10000,10000,10000) L_0x2afa150/d; +L_0x2afa460/d .functor NAND 1, L_0x2afb3e0, L_0x2afa280, C4<1>, C4<1>; +L_0x2afa460 .delay (10000,10000,10000) L_0x2afa460/d; +L_0x2afa5c0/d .functor NAND 1, L_0x2afa460, L_0x2afa150, C4<1>, C4<1>; +L_0x2afa5c0 .delay (10000,10000,10000) L_0x2afa5c0/d; +L_0x2afa6d0/d .functor NOT 1, L_0x2afa5c0, C4<0>, C4<0>, C4<0>; +L_0x2afa6d0 .delay (10000,10000,10000) L_0x2afa6d0/d; +v0x2818b10_0 .net "A", 0 0, L_0x2afb3e0; 1 drivers +v0x2818bb0_0 .net "AnandB", 0 0, L_0x2afa460; 1 drivers +v0x2818c50_0 .net "AnorB", 0 0, L_0x2af8f10; 1 drivers +v0x2818d00_0 .net "AorB", 0 0, L_0x2afa150; 1 drivers +v0x2818de0_0 .net "AxorB", 0 0, L_0x2afa6d0; 1 drivers +v0x2818e90_0 .net "B", 0 0, L_0x2afa280; 1 drivers +v0x2818f50_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x2818fd0_0 .net "OrNorXorOut", 0 0, L_0x2afb0d0; 1 drivers +v0x2819050_0 .net "XorNor", 0 0, L_0x2afab50; 1 drivers +v0x2819120_0 .net "nXor", 0 0, L_0x2afa5c0; 1 drivers +L_0x2afacd0 .part v0x2960210_0, 2, 1; +L_0x2afb2a0 .part v0x2960210_0, 0, 1; +S_0x28185a0 .scope module, "mux0" "TwoInMux" 3 184, 3 109, S_0x2817f60; + .timescale -9 -12; +L_0x2afa830/d .functor NOT 1, L_0x2afacd0, C4<0>, C4<0>, C4<0>; +L_0x2afa830 .delay (10000,10000,10000) L_0x2afa830/d; +L_0x2afa8f0/d .functor AND 1, L_0x2afa6d0, L_0x2afa830, C4<1>, C4<1>; +L_0x2afa8f0 .delay (20000,20000,20000) L_0x2afa8f0/d; +L_0x2afaa00/d .functor AND 1, L_0x2af8f10, L_0x2afacd0, C4<1>, C4<1>; +L_0x2afaa00 .delay (20000,20000,20000) L_0x2afaa00/d; +L_0x2afab50/d .functor OR 1, L_0x2afa8f0, L_0x2afaa00, C4<0>, C4<0>; +L_0x2afab50 .delay (20000,20000,20000) L_0x2afab50/d; +v0x2818690_0 .net "S", 0 0, L_0x2afacd0; 1 drivers +v0x2818750_0 .alias "in0", 0 0, v0x2818de0_0; +v0x28187f0_0 .alias "in1", 0 0, v0x2818c50_0; +v0x2818890_0 .net "nS", 0 0, L_0x2afa830; 1 drivers +v0x2818910_0 .net "out0", 0 0, L_0x2afa8f0; 1 drivers +v0x28189b0_0 .net "out1", 0 0, L_0x2afaa00; 1 drivers +v0x2818a90_0 .alias "outfinal", 0 0, v0x2819050_0; +S_0x2818050 .scope module, "mux1" "TwoInMux" 3 185, 3 109, S_0x2817f60; + .timescale -9 -12; +L_0x2afad70/d .functor NOT 1, L_0x2afb2a0, C4<0>, C4<0>, C4<0>; +L_0x2afad70 .delay (10000,10000,10000) L_0x2afad70/d; +L_0x2afae30/d .functor AND 1, L_0x2afab50, L_0x2afad70, C4<1>, C4<1>; +L_0x2afae30 .delay (20000,20000,20000) L_0x2afae30/d; +L_0x2afaf80/d .functor AND 1, L_0x2afa150, L_0x2afb2a0, C4<1>, C4<1>; +L_0x2afaf80 .delay (20000,20000,20000) L_0x2afaf80/d; +L_0x2afb0d0/d .functor OR 1, L_0x2afae30, L_0x2afaf80, C4<0>, C4<0>; +L_0x2afb0d0 .delay (20000,20000,20000) L_0x2afb0d0/d; +v0x2818140_0 .net "S", 0 0, L_0x2afb2a0; 1 drivers +v0x28181c0_0 .alias "in0", 0 0, v0x2819050_0; +v0x2818260_0 .alias "in1", 0 0, v0x2818d00_0; +v0x2818300_0 .net "nS", 0 0, L_0x2afad70; 1 drivers +v0x2818380_0 .net "out0", 0 0, L_0x2afae30; 1 drivers +v0x2818420_0 .net "out1", 0 0, L_0x2afaf80; 1 drivers +v0x2818500_0 .alias "outfinal", 0 0, v0x2818fd0_0; +S_0x2816a60 .scope generate, "orbits[14]" "orbits[14]" 3 258, 3 258, S_0x2801850; + .timescale -9 -12; +P_0x2816778 .param/l "i" 3 258, +C4<01110>; +S_0x2816b90 .scope module, "attempt" "OrNorXor" 3 260, 3 165, S_0x2816a60; + .timescale -9 -12; +L_0x2afa320/d .functor NOR 1, L_0x2afb480, L_0x2afb520, C4<0>, C4<0>; +L_0x2afa320 .delay (10000,10000,10000) L_0x2afa320/d; +L_0x2afb650/d .functor NOT 1, L_0x2afa320, C4<0>, C4<0>, C4<0>; +L_0x2afb650 .delay (10000,10000,10000) L_0x2afb650/d; +L_0x2afb760/d .functor NAND 1, L_0x2afb480, L_0x2afb520, C4<1>, C4<1>; +L_0x2afb760 .delay (10000,10000,10000) L_0x2afb760/d; +L_0x2afb8c0/d .functor NAND 1, L_0x2afb760, L_0x2afb650, C4<1>, C4<1>; +L_0x2afb8c0 .delay (10000,10000,10000) L_0x2afb8c0/d; +L_0x2afb9d0/d .functor NOT 1, L_0x2afb8c0, C4<0>, C4<0>, C4<0>; +L_0x2afb9d0 .delay (10000,10000,10000) L_0x2afb9d0/d; +v0x2817740_0 .net "A", 0 0, L_0x2afb480; 1 drivers +v0x28177e0_0 .net "AnandB", 0 0, L_0x2afb760; 1 drivers +v0x2817880_0 .net "AnorB", 0 0, L_0x2afa320; 1 drivers +v0x2817930_0 .net "AorB", 0 0, L_0x2afb650; 1 drivers +v0x2817a10_0 .net "AxorB", 0 0, L_0x2afb9d0; 1 drivers +v0x2817ac0_0 .net "B", 0 0, L_0x2afb520; 1 drivers +v0x2817b80_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x2817c00_0 .net "OrNorXorOut", 0 0, L_0x2afc3d0; 1 drivers +v0x2817c80_0 .net "XorNor", 0 0, L_0x2afbe50; 1 drivers +v0x2817d50_0 .net "nXor", 0 0, L_0x2afb8c0; 1 drivers +L_0x2afbfd0 .part v0x2960210_0, 2, 1; +L_0x2afc5a0 .part v0x2960210_0, 0, 1; +S_0x28171d0 .scope module, "mux0" "TwoInMux" 3 184, 3 109, S_0x2816b90; + .timescale -9 -12; +L_0x2afbb30/d .functor NOT 1, L_0x2afbfd0, C4<0>, C4<0>, C4<0>; +L_0x2afbb30 .delay (10000,10000,10000) L_0x2afbb30/d; +L_0x2afbbf0/d .functor AND 1, L_0x2afb9d0, L_0x2afbb30, C4<1>, C4<1>; +L_0x2afbbf0 .delay (20000,20000,20000) L_0x2afbbf0/d; +L_0x2afbd00/d .functor AND 1, L_0x2afa320, L_0x2afbfd0, C4<1>, C4<1>; +L_0x2afbd00 .delay (20000,20000,20000) L_0x2afbd00/d; +L_0x2afbe50/d .functor OR 1, L_0x2afbbf0, L_0x2afbd00, C4<0>, C4<0>; +L_0x2afbe50 .delay (20000,20000,20000) L_0x2afbe50/d; +v0x28172c0_0 .net "S", 0 0, L_0x2afbfd0; 1 drivers +v0x2817380_0 .alias "in0", 0 0, v0x2817a10_0; +v0x2817420_0 .alias "in1", 0 0, v0x2817880_0; +v0x28174c0_0 .net "nS", 0 0, L_0x2afbb30; 1 drivers +v0x2817540_0 .net "out0", 0 0, L_0x2afbbf0; 1 drivers +v0x28175e0_0 .net "out1", 0 0, L_0x2afbd00; 1 drivers +v0x28176c0_0 .alias "outfinal", 0 0, v0x2817c80_0; +S_0x2816c80 .scope module, "mux1" "TwoInMux" 3 185, 3 109, S_0x2816b90; + .timescale -9 -12; +L_0x2afc070/d .functor NOT 1, L_0x2afc5a0, C4<0>, C4<0>, C4<0>; +L_0x2afc070 .delay (10000,10000,10000) L_0x2afc070/d; +L_0x2afc130/d .functor AND 1, L_0x2afbe50, L_0x2afc070, C4<1>, C4<1>; +L_0x2afc130 .delay (20000,20000,20000) L_0x2afc130/d; +L_0x2afc280/d .functor AND 1, L_0x2afb650, L_0x2afc5a0, C4<1>, C4<1>; +L_0x2afc280 .delay (20000,20000,20000) L_0x2afc280/d; +L_0x2afc3d0/d .functor OR 1, L_0x2afc130, L_0x2afc280, C4<0>, C4<0>; +L_0x2afc3d0 .delay (20000,20000,20000) L_0x2afc3d0/d; +v0x2816d70_0 .net "S", 0 0, L_0x2afc5a0; 1 drivers +v0x2816df0_0 .alias "in0", 0 0, v0x2817c80_0; +v0x2816e90_0 .alias "in1", 0 0, v0x2817930_0; +v0x2816f30_0 .net "nS", 0 0, L_0x2afc070; 1 drivers +v0x2816fb0_0 .net "out0", 0 0, L_0x2afc130; 1 drivers +v0x2817050_0 .net "out1", 0 0, L_0x2afc280; 1 drivers +v0x2817130_0 .alias "outfinal", 0 0, v0x2817c00_0; +S_0x2815690 .scope generate, "orbits[15]" "orbits[15]" 3 258, 3 258, S_0x2801850; + .timescale -9 -12; +P_0x28153a8 .param/l "i" 3 258, +C4<01111>; +S_0x28157c0 .scope module, "attempt" "OrNorXor" 3 260, 3 165, S_0x2815690; + .timescale -9 -12; +L_0x2afc840/d .functor NOR 1, L_0x2afd9e0, L_0x2afc6e0, C4<0>, C4<0>; +L_0x2afc840 .delay (10000,10000,10000) L_0x2afc840/d; +L_0x2afc930/d .functor NOT 1, L_0x2afc840, C4<0>, C4<0>, C4<0>; +L_0x2afc930 .delay (10000,10000,10000) L_0x2afc930/d; +L_0x2afca60/d .functor NAND 1, L_0x2afd9e0, L_0x2afc6e0, C4<1>, C4<1>; +L_0x2afca60 .delay (10000,10000,10000) L_0x2afca60/d; +L_0x2afcbc0/d .functor NAND 1, L_0x2afca60, L_0x2afc930, C4<1>, C4<1>; +L_0x2afcbc0 .delay (10000,10000,10000) L_0x2afcbc0/d; +L_0x2afccd0/d .functor NOT 1, L_0x2afcbc0, C4<0>, C4<0>, C4<0>; +L_0x2afccd0 .delay (10000,10000,10000) L_0x2afccd0/d; +v0x2816370_0 .net "A", 0 0, L_0x2afd9e0; 1 drivers +v0x2816410_0 .net "AnandB", 0 0, L_0x2afca60; 1 drivers +v0x28164b0_0 .net "AnorB", 0 0, L_0x2afc840; 1 drivers +v0x2816560_0 .net "AorB", 0 0, L_0x2afc930; 1 drivers +v0x2816640_0 .net "AxorB", 0 0, L_0x2afccd0; 1 drivers +v0x28166f0_0 .net "B", 0 0, L_0x2afc6e0; 1 drivers +v0x28167b0_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x2816830_0 .net "OrNorXorOut", 0 0, L_0x2afd6d0; 1 drivers +v0x28168b0_0 .net "XorNor", 0 0, L_0x2afd150; 1 drivers +v0x2816980_0 .net "nXor", 0 0, L_0x2afcbc0; 1 drivers +L_0x2afd2d0 .part v0x2960210_0, 2, 1; +L_0x2afd8a0 .part v0x2960210_0, 0, 1; +S_0x2815e00 .scope module, "mux0" "TwoInMux" 3 184, 3 109, S_0x28157c0; + .timescale -9 -12; +L_0x2afce30/d .functor NOT 1, L_0x2afd2d0, C4<0>, C4<0>, C4<0>; +L_0x2afce30 .delay (10000,10000,10000) L_0x2afce30/d; +L_0x2afcef0/d .functor AND 1, L_0x2afccd0, L_0x2afce30, C4<1>, C4<1>; +L_0x2afcef0 .delay (20000,20000,20000) L_0x2afcef0/d; +L_0x2afd000/d .functor AND 1, L_0x2afc840, L_0x2afd2d0, C4<1>, C4<1>; +L_0x2afd000 .delay (20000,20000,20000) L_0x2afd000/d; +L_0x2afd150/d .functor OR 1, L_0x2afcef0, L_0x2afd000, C4<0>, C4<0>; +L_0x2afd150 .delay (20000,20000,20000) L_0x2afd150/d; +v0x2815ef0_0 .net "S", 0 0, L_0x2afd2d0; 1 drivers +v0x2815fb0_0 .alias "in0", 0 0, v0x2816640_0; +v0x2816050_0 .alias "in1", 0 0, v0x28164b0_0; +v0x28160f0_0 .net "nS", 0 0, L_0x2afce30; 1 drivers +v0x2816170_0 .net "out0", 0 0, L_0x2afcef0; 1 drivers +v0x2816210_0 .net "out1", 0 0, L_0x2afd000; 1 drivers +v0x28162f0_0 .alias "outfinal", 0 0, v0x28168b0_0; +S_0x28158b0 .scope module, "mux1" "TwoInMux" 3 185, 3 109, S_0x28157c0; + .timescale -9 -12; +L_0x2afd370/d .functor NOT 1, L_0x2afd8a0, C4<0>, C4<0>, C4<0>; +L_0x2afd370 .delay (10000,10000,10000) L_0x2afd370/d; +L_0x2afd430/d .functor AND 1, L_0x2afd150, L_0x2afd370, C4<1>, C4<1>; +L_0x2afd430 .delay (20000,20000,20000) L_0x2afd430/d; +L_0x2afd580/d .functor AND 1, L_0x2afc930, L_0x2afd8a0, C4<1>, C4<1>; +L_0x2afd580 .delay (20000,20000,20000) L_0x2afd580/d; +L_0x2afd6d0/d .functor OR 1, L_0x2afd430, L_0x2afd580, C4<0>, C4<0>; +L_0x2afd6d0 .delay (20000,20000,20000) L_0x2afd6d0/d; +v0x28159a0_0 .net "S", 0 0, L_0x2afd8a0; 1 drivers +v0x2815a20_0 .alias "in0", 0 0, v0x28168b0_0; +v0x2815ac0_0 .alias "in1", 0 0, v0x2816560_0; +v0x2815b60_0 .net "nS", 0 0, L_0x2afd370; 1 drivers +v0x2815be0_0 .net "out0", 0 0, L_0x2afd430; 1 drivers +v0x2815c80_0 .net "out1", 0 0, L_0x2afd580; 1 drivers +v0x2815d60_0 .alias "outfinal", 0 0, v0x2816830_0; +S_0x28142c0 .scope generate, "orbits[16]" "orbits[16]" 3 258, 3 258, S_0x2801850; + .timescale -9 -12; +P_0x2813fd8 .param/l "i" 3 258, +C4<010000>; +S_0x28143f0 .scope module, "attempt" "OrNorXor" 3 260, 3 165, S_0x28142c0; + .timescale -9 -12; +L_0x2afc780/d .functor NOR 1, L_0x2afda80, L_0x2afdb20, C4<0>, C4<0>; +L_0x2afc780 .delay (10000,10000,10000) L_0x2afc780/d; +L_0x2afdc40/d .functor NOT 1, L_0x2afc780, C4<0>, C4<0>, C4<0>; +L_0x2afdc40 .delay (10000,10000,10000) L_0x2afdc40/d; +L_0x2afdd50/d .functor NAND 1, L_0x2afda80, L_0x2afdb20, C4<1>, C4<1>; +L_0x2afdd50 .delay (10000,10000,10000) L_0x2afdd50/d; +L_0x2afdeb0/d .functor NAND 1, L_0x2afdd50, L_0x2afdc40, C4<1>, C4<1>; +L_0x2afdeb0 .delay (10000,10000,10000) L_0x2afdeb0/d; +L_0x2af0980/d .functor NOT 1, L_0x2afdeb0, C4<0>, C4<0>, C4<0>; +L_0x2af0980 .delay (10000,10000,10000) L_0x2af0980/d; +v0x2814fa0_0 .net "A", 0 0, L_0x2afda80; 1 drivers +v0x2815040_0 .net "AnandB", 0 0, L_0x2afdd50; 1 drivers +v0x28150e0_0 .net "AnorB", 0 0, L_0x2afc780; 1 drivers +v0x2815190_0 .net "AorB", 0 0, L_0x2afdc40; 1 drivers +v0x2815270_0 .net "AxorB", 0 0, L_0x2af0980; 1 drivers +v0x2815320_0 .net "B", 0 0, L_0x2afdb20; 1 drivers +v0x28153e0_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x2815460_0 .net "OrNorXorOut", 0 0, L_0x2afe7f0; 1 drivers +v0x28154e0_0 .net "XorNor", 0 0, L_0x2afe310; 1 drivers +v0x28155b0_0 .net "nXor", 0 0, L_0x2afdeb0; 1 drivers +L_0x2afe450 .part v0x2960210_0, 2, 1; +L_0x2afe980 .part v0x2960210_0, 0, 1; +S_0x2814a30 .scope module, "mux0" "TwoInMux" 3 184, 3 109, S_0x28143f0; + .timescale -9 -12; +L_0x2afe050/d .functor NOT 1, L_0x2afe450, C4<0>, C4<0>, C4<0>; +L_0x2afe050 .delay (10000,10000,10000) L_0x2afe050/d; +L_0x2afe0f0/d .functor AND 1, L_0x2af0980, L_0x2afe050, C4<1>, C4<1>; +L_0x2afe0f0 .delay (20000,20000,20000) L_0x2afe0f0/d; +L_0x2afe1e0/d .functor AND 1, L_0x2afc780, L_0x2afe450, C4<1>, C4<1>; +L_0x2afe1e0 .delay (20000,20000,20000) L_0x2afe1e0/d; +L_0x2afe310/d .functor OR 1, L_0x2afe0f0, L_0x2afe1e0, C4<0>, C4<0>; +L_0x2afe310 .delay (20000,20000,20000) L_0x2afe310/d; +v0x2814b20_0 .net "S", 0 0, L_0x2afe450; 1 drivers +v0x2814be0_0 .alias "in0", 0 0, v0x2815270_0; +v0x2814c80_0 .alias "in1", 0 0, v0x28150e0_0; +v0x2814d20_0 .net "nS", 0 0, L_0x2afe050; 1 drivers +v0x2814da0_0 .net "out0", 0 0, L_0x2afe0f0; 1 drivers +v0x2814e40_0 .net "out1", 0 0, L_0x2afe1e0; 1 drivers +v0x2814f20_0 .alias "outfinal", 0 0, v0x28154e0_0; +S_0x28144e0 .scope module, "mux1" "TwoInMux" 3 185, 3 109, S_0x28143f0; + .timescale -9 -12; +L_0x2afe4f0/d .functor NOT 1, L_0x2afe980, C4<0>, C4<0>, C4<0>; +L_0x2afe4f0 .delay (10000,10000,10000) L_0x2afe4f0/d; +L_0x2afe590/d .functor AND 1, L_0x2afe310, L_0x2afe4f0, C4<1>, C4<1>; +L_0x2afe590 .delay (20000,20000,20000) L_0x2afe590/d; +L_0x2afe6c0/d .functor AND 1, L_0x2afdc40, L_0x2afe980, C4<1>, C4<1>; +L_0x2afe6c0 .delay (20000,20000,20000) L_0x2afe6c0/d; +L_0x2afe7f0/d .functor OR 1, L_0x2afe590, L_0x2afe6c0, C4<0>, C4<0>; +L_0x2afe7f0 .delay (20000,20000,20000) L_0x2afe7f0/d; +v0x28145d0_0 .net "S", 0 0, L_0x2afe980; 1 drivers +v0x2814650_0 .alias "in0", 0 0, v0x28154e0_0; +v0x28146f0_0 .alias "in1", 0 0, v0x2815190_0; +v0x2814790_0 .net "nS", 0 0, L_0x2afe4f0; 1 drivers +v0x2814810_0 .net "out0", 0 0, L_0x2afe590; 1 drivers +v0x28148b0_0 .net "out1", 0 0, L_0x2afe6c0; 1 drivers +v0x2814990_0 .alias "outfinal", 0 0, v0x2815460_0; +S_0x2812ef0 .scope generate, "orbits[17]" "orbits[17]" 3 258, 3 258, S_0x2801850; + .timescale -9 -12; +P_0x2812c08 .param/l "i" 3 258, +C4<010001>; +S_0x2813020 .scope module, "attempt" "OrNorXor" 3 260, 3 165, S_0x2812ef0; + .timescale -9 -12; +L_0x2afec50/d .functor NOR 1, L_0x2affcd0, L_0x2afeac0, C4<0>, C4<0>; +L_0x2afec50 .delay (10000,10000,10000) L_0x2afec50/d; +L_0x2afed40/d .functor NOT 1, L_0x2afec50, C4<0>, C4<0>, C4<0>; +L_0x2afed40 .delay (10000,10000,10000) L_0x2afed40/d; +L_0x2afee30/d .functor NAND 1, L_0x2affcd0, L_0x2afeac0, C4<1>, C4<1>; +L_0x2afee30 .delay (10000,10000,10000) L_0x2afee30/d; +L_0x2afef70/d .functor NAND 1, L_0x2afee30, L_0x2afed40, C4<1>, C4<1>; +L_0x2afef70 .delay (10000,10000,10000) L_0x2afef70/d; +L_0x2aff060/d .functor NOT 1, L_0x2afef70, C4<0>, C4<0>, C4<0>; +L_0x2aff060 .delay (10000,10000,10000) L_0x2aff060/d; +v0x2813bd0_0 .net "A", 0 0, L_0x2affcd0; 1 drivers +v0x2813c70_0 .net "AnandB", 0 0, L_0x2afee30; 1 drivers +v0x2813d10_0 .net "AnorB", 0 0, L_0x2afec50; 1 drivers +v0x2813dc0_0 .net "AorB", 0 0, L_0x2afed40; 1 drivers +v0x2813ea0_0 .net "AxorB", 0 0, L_0x2aff060; 1 drivers +v0x2813f50_0 .net "B", 0 0, L_0x2afeac0; 1 drivers +v0x2814010_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x2814090_0 .net "OrNorXorOut", 0 0, L_0x2aff9c0; 1 drivers +v0x2814110_0 .net "XorNor", 0 0, L_0x2aff460; 1 drivers +v0x28141e0_0 .net "nXor", 0 0, L_0x2afef70; 1 drivers +L_0x2aff5c0 .part v0x2960210_0, 2, 1; +L_0x2affb90 .part v0x2960210_0, 0, 1; +S_0x2813660 .scope module, "mux0" "TwoInMux" 3 184, 3 109, S_0x2813020; + .timescale -9 -12; +L_0x2aff1a0/d .functor NOT 1, L_0x2aff5c0, C4<0>, C4<0>, C4<0>; +L_0x2aff1a0 .delay (10000,10000,10000) L_0x2aff1a0/d; +L_0x2aff240/d .functor AND 1, L_0x2aff060, L_0x2aff1a0, C4<1>, C4<1>; +L_0x2aff240 .delay (20000,20000,20000) L_0x2aff240/d; +L_0x2aff330/d .functor AND 1, L_0x2afec50, L_0x2aff5c0, C4<1>, C4<1>; +L_0x2aff330 .delay (20000,20000,20000) L_0x2aff330/d; +L_0x2aff460/d .functor OR 1, L_0x2aff240, L_0x2aff330, C4<0>, C4<0>; +L_0x2aff460 .delay (20000,20000,20000) L_0x2aff460/d; +v0x2813750_0 .net "S", 0 0, L_0x2aff5c0; 1 drivers +v0x2813810_0 .alias "in0", 0 0, v0x2813ea0_0; +v0x28138b0_0 .alias "in1", 0 0, v0x2813d10_0; +v0x2813950_0 .net "nS", 0 0, L_0x2aff1a0; 1 drivers +v0x28139d0_0 .net "out0", 0 0, L_0x2aff240; 1 drivers +v0x2813a70_0 .net "out1", 0 0, L_0x2aff330; 1 drivers +v0x2813b50_0 .alias "outfinal", 0 0, v0x2814110_0; +S_0x2813110 .scope module, "mux1" "TwoInMux" 3 185, 3 109, S_0x2813020; + .timescale -9 -12; +L_0x2aff660/d .functor NOT 1, L_0x2affb90, C4<0>, C4<0>, C4<0>; +L_0x2aff660 .delay (10000,10000,10000) L_0x2aff660/d; +L_0x2aff720/d .functor AND 1, L_0x2aff460, L_0x2aff660, C4<1>, C4<1>; +L_0x2aff720 .delay (20000,20000,20000) L_0x2aff720/d; +L_0x2aff870/d .functor AND 1, L_0x2afed40, L_0x2affb90, C4<1>, C4<1>; +L_0x2aff870 .delay (20000,20000,20000) L_0x2aff870/d; +L_0x2aff9c0/d .functor OR 1, L_0x2aff720, L_0x2aff870, C4<0>, C4<0>; +L_0x2aff9c0 .delay (20000,20000,20000) L_0x2aff9c0/d; +v0x2813200_0 .net "S", 0 0, L_0x2affb90; 1 drivers +v0x2813280_0 .alias "in0", 0 0, v0x2814110_0; +v0x2813320_0 .alias "in1", 0 0, v0x2813dc0_0; +v0x28133c0_0 .net "nS", 0 0, L_0x2aff660; 1 drivers +v0x2813440_0 .net "out0", 0 0, L_0x2aff720; 1 drivers +v0x28134e0_0 .net "out1", 0 0, L_0x2aff870; 1 drivers +v0x28135c0_0 .alias "outfinal", 0 0, v0x2814090_0; +S_0x2811b20 .scope generate, "orbits[18]" "orbits[18]" 3 258, 3 258, S_0x2801850; + .timescale -9 -12; +P_0x2811838 .param/l "i" 3 258, +C4<010010>; +S_0x2811c50 .scope module, "attempt" "OrNorXor" 3 260, 3 165, S_0x2811b20; + .timescale -9 -12; +L_0x2afeb60/d .functor NOR 1, L_0x2affd70, L_0x2affe10, C4<0>, C4<0>; +L_0x2afeb60 .delay (10000,10000,10000) L_0x2afeb60/d; +L_0x2afff10/d .functor NOT 1, L_0x2afeb60, C4<0>, C4<0>, C4<0>; +L_0x2afff10 .delay (10000,10000,10000) L_0x2afff10/d; +L_0x2b00040/d .functor NAND 1, L_0x2affd70, L_0x2affe10, C4<1>, C4<1>; +L_0x2b00040 .delay (10000,10000,10000) L_0x2b00040/d; +L_0x2b001a0/d .functor NAND 1, L_0x2b00040, L_0x2afff10, C4<1>, C4<1>; +L_0x2b001a0 .delay (10000,10000,10000) L_0x2b001a0/d; +L_0x2b002b0/d .functor NOT 1, L_0x2b001a0, C4<0>, C4<0>, C4<0>; +L_0x2b002b0 .delay (10000,10000,10000) L_0x2b002b0/d; +v0x2812800_0 .net "A", 0 0, L_0x2affd70; 1 drivers +v0x28128a0_0 .net "AnandB", 0 0, L_0x2b00040; 1 drivers +v0x2812940_0 .net "AnorB", 0 0, L_0x2afeb60; 1 drivers +v0x28129f0_0 .net "AorB", 0 0, L_0x2afff10; 1 drivers +v0x2812ad0_0 .net "AxorB", 0 0, L_0x2b002b0; 1 drivers +v0x2812b80_0 .net "B", 0 0, L_0x2affe10; 1 drivers +v0x2812c40_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x2812cc0_0 .net "OrNorXorOut", 0 0, L_0x2b00cb0; 1 drivers +v0x2812d40_0 .net "XorNor", 0 0, L_0x2b00730; 1 drivers +v0x2812e10_0 .net "nXor", 0 0, L_0x2b001a0; 1 drivers +L_0x2b008b0 .part v0x2960210_0, 2, 1; +L_0x2b00e80 .part v0x2960210_0, 0, 1; +S_0x2812290 .scope module, "mux0" "TwoInMux" 3 184, 3 109, S_0x2811c50; + .timescale -9 -12; +L_0x2b00410/d .functor NOT 1, L_0x2b008b0, C4<0>, C4<0>, C4<0>; +L_0x2b00410 .delay (10000,10000,10000) L_0x2b00410/d; +L_0x2b004d0/d .functor AND 1, L_0x2b002b0, L_0x2b00410, C4<1>, C4<1>; +L_0x2b004d0 .delay (20000,20000,20000) L_0x2b004d0/d; +L_0x2b005e0/d .functor AND 1, L_0x2afeb60, L_0x2b008b0, C4<1>, C4<1>; +L_0x2b005e0 .delay (20000,20000,20000) L_0x2b005e0/d; +L_0x2b00730/d .functor OR 1, L_0x2b004d0, L_0x2b005e0, C4<0>, C4<0>; +L_0x2b00730 .delay (20000,20000,20000) L_0x2b00730/d; +v0x2812380_0 .net "S", 0 0, L_0x2b008b0; 1 drivers +v0x2812440_0 .alias "in0", 0 0, v0x2812ad0_0; +v0x28124e0_0 .alias "in1", 0 0, v0x2812940_0; +v0x2812580_0 .net "nS", 0 0, L_0x2b00410; 1 drivers +v0x2812600_0 .net "out0", 0 0, L_0x2b004d0; 1 drivers +v0x28126a0_0 .net "out1", 0 0, L_0x2b005e0; 1 drivers +v0x2812780_0 .alias "outfinal", 0 0, v0x2812d40_0; +S_0x2811d40 .scope module, "mux1" "TwoInMux" 3 185, 3 109, S_0x2811c50; + .timescale -9 -12; +L_0x2b00950/d .functor NOT 1, L_0x2b00e80, C4<0>, C4<0>, C4<0>; +L_0x2b00950 .delay (10000,10000,10000) L_0x2b00950/d; +L_0x2b00a10/d .functor AND 1, L_0x2b00730, L_0x2b00950, C4<1>, C4<1>; +L_0x2b00a10 .delay (20000,20000,20000) L_0x2b00a10/d; +L_0x2b00b60/d .functor AND 1, L_0x2afff10, L_0x2b00e80, C4<1>, C4<1>; +L_0x2b00b60 .delay (20000,20000,20000) L_0x2b00b60/d; +L_0x2b00cb0/d .functor OR 1, L_0x2b00a10, L_0x2b00b60, C4<0>, C4<0>; +L_0x2b00cb0 .delay (20000,20000,20000) L_0x2b00cb0/d; +v0x2811e30_0 .net "S", 0 0, L_0x2b00e80; 1 drivers +v0x2811eb0_0 .alias "in0", 0 0, v0x2812d40_0; +v0x2811f50_0 .alias "in1", 0 0, v0x28129f0_0; +v0x2811ff0_0 .net "nS", 0 0, L_0x2b00950; 1 drivers +v0x2812070_0 .net "out0", 0 0, L_0x2b00a10; 1 drivers +v0x2812110_0 .net "out1", 0 0, L_0x2b00b60; 1 drivers +v0x28121f0_0 .alias "outfinal", 0 0, v0x2812cc0_0; +S_0x2810750 .scope generate, "orbits[19]" "orbits[19]" 3 258, 3 258, S_0x2801850; + .timescale -9 -12; +P_0x2810468 .param/l "i" 3 258, +C4<010011>; +S_0x2810880 .scope module, "attempt" "OrNorXor" 3 260, 3 165, S_0x2810750; + .timescale -9 -12; +L_0x2affeb0/d .functor NOR 1, L_0x2a01250, L_0x2a00140, C4<0>, C4<0>; +L_0x2affeb0 .delay (10000,10000,10000) L_0x2affeb0/d; +L_0x2b01050/d .functor NOT 1, L_0x2affeb0, C4<0>, C4<0>, C4<0>; +L_0x2b01050 .delay (10000,10000,10000) L_0x2b01050/d; +L_0x2b01110/d .functor NAND 1, L_0x2a01250, L_0x2a00140, C4<1>, C4<1>; +L_0x2b01110 .delay (10000,10000,10000) L_0x2b01110/d; +L_0x2a00430/d .functor NAND 1, L_0x2b01110, L_0x2b01050, C4<1>, C4<1>; +L_0x2a00430 .delay (10000,10000,10000) L_0x2a00430/d; +L_0x2a00540/d .functor NOT 1, L_0x2a00430, C4<0>, C4<0>, C4<0>; +L_0x2a00540 .delay (10000,10000,10000) L_0x2a00540/d; +v0x2811430_0 .net "A", 0 0, L_0x2a01250; 1 drivers +v0x28114d0_0 .net "AnandB", 0 0, L_0x2b01110; 1 drivers +v0x2811570_0 .net "AnorB", 0 0, L_0x2affeb0; 1 drivers +v0x2811620_0 .net "AorB", 0 0, L_0x2b01050; 1 drivers +v0x2811700_0 .net "AxorB", 0 0, L_0x2a00540; 1 drivers +v0x28117b0_0 .net "B", 0 0, L_0x2a00140; 1 drivers +v0x2811870_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x28118f0_0 .net "OrNorXorOut", 0 0, L_0x2a00f40; 1 drivers +v0x2811970_0 .net "XorNor", 0 0, L_0x2a009c0; 1 drivers +v0x2811a40_0 .net "nXor", 0 0, L_0x2a00430; 1 drivers +L_0x2a00b40 .part v0x2960210_0, 2, 1; +L_0x2a01110 .part v0x2960210_0, 0, 1; +S_0x2810ec0 .scope module, "mux0" "TwoInMux" 3 184, 3 109, S_0x2810880; + .timescale -9 -12; +L_0x2a006a0/d .functor NOT 1, L_0x2a00b40, C4<0>, C4<0>, C4<0>; +L_0x2a006a0 .delay (10000,10000,10000) L_0x2a006a0/d; +L_0x2a00760/d .functor AND 1, L_0x2a00540, L_0x2a006a0, C4<1>, C4<1>; +L_0x2a00760 .delay (20000,20000,20000) L_0x2a00760/d; +L_0x2a00870/d .functor AND 1, L_0x2affeb0, L_0x2a00b40, C4<1>, C4<1>; +L_0x2a00870 .delay (20000,20000,20000) L_0x2a00870/d; +L_0x2a009c0/d .functor OR 1, L_0x2a00760, L_0x2a00870, C4<0>, C4<0>; +L_0x2a009c0 .delay (20000,20000,20000) L_0x2a009c0/d; +v0x2810fb0_0 .net "S", 0 0, L_0x2a00b40; 1 drivers +v0x2811070_0 .alias "in0", 0 0, v0x2811700_0; +v0x2811110_0 .alias "in1", 0 0, v0x2811570_0; +v0x28111b0_0 .net "nS", 0 0, L_0x2a006a0; 1 drivers +v0x2811230_0 .net "out0", 0 0, L_0x2a00760; 1 drivers +v0x28112d0_0 .net "out1", 0 0, L_0x2a00870; 1 drivers +v0x28113b0_0 .alias "outfinal", 0 0, v0x2811970_0; +S_0x2810970 .scope module, "mux1" "TwoInMux" 3 185, 3 109, S_0x2810880; + .timescale -9 -12; +L_0x2a00be0/d .functor NOT 1, L_0x2a01110, C4<0>, C4<0>, C4<0>; +L_0x2a00be0 .delay (10000,10000,10000) L_0x2a00be0/d; +L_0x2a00ca0/d .functor AND 1, L_0x2a009c0, L_0x2a00be0, C4<1>, C4<1>; +L_0x2a00ca0 .delay (20000,20000,20000) L_0x2a00ca0/d; +L_0x2a00df0/d .functor AND 1, L_0x2b01050, L_0x2a01110, C4<1>, C4<1>; +L_0x2a00df0 .delay (20000,20000,20000) L_0x2a00df0/d; +L_0x2a00f40/d .functor OR 1, L_0x2a00ca0, L_0x2a00df0, C4<0>, C4<0>; +L_0x2a00f40 .delay (20000,20000,20000) L_0x2a00f40/d; +v0x2810a60_0 .net "S", 0 0, L_0x2a01110; 1 drivers +v0x2810ae0_0 .alias "in0", 0 0, v0x2811970_0; +v0x2810b80_0 .alias "in1", 0 0, v0x2811620_0; +v0x2810c20_0 .net "nS", 0 0, L_0x2a00be0; 1 drivers +v0x2810ca0_0 .net "out0", 0 0, L_0x2a00ca0; 1 drivers +v0x2810d40_0 .net "out1", 0 0, L_0x2a00df0; 1 drivers +v0x2810e20_0 .alias "outfinal", 0 0, v0x28118f0_0; +S_0x280f380 .scope generate, "orbits[20]" "orbits[20]" 3 258, 3 258, S_0x2801850; + .timescale -9 -12; +P_0x280f098 .param/l "i" 3 258, +C4<010100>; +S_0x280f4b0 .scope module, "attempt" "OrNorXor" 3 260, 3 165, S_0x280f380; + .timescale -9 -12; +L_0x2a001e0/d .functor NOR 1, L_0x2a012f0, L_0x2a01390, C4<0>, C4<0>; +L_0x2a001e0 .delay (10000,10000,10000) L_0x2a001e0/d; +L_0x2a014c0/d .functor NOT 1, L_0x2a001e0, C4<0>, C4<0>, C4<0>; +L_0x2a014c0 .delay (10000,10000,10000) L_0x2a014c0/d; +L_0x2a015f0/d .functor NAND 1, L_0x2a012f0, L_0x2a01390, C4<1>, C4<1>; +L_0x2a015f0 .delay (10000,10000,10000) L_0x2a015f0/d; +L_0x2a01750/d .functor NAND 1, L_0x2a015f0, L_0x2a014c0, C4<1>, C4<1>; +L_0x2a01750 .delay (10000,10000,10000) L_0x2a01750/d; +L_0x2a01860/d .functor NOT 1, L_0x2a01750, C4<0>, C4<0>, C4<0>; +L_0x2a01860 .delay (10000,10000,10000) L_0x2a01860/d; +v0x2810060_0 .net "A", 0 0, L_0x2a012f0; 1 drivers +v0x2810100_0 .net "AnandB", 0 0, L_0x2a015f0; 1 drivers +v0x28101a0_0 .net "AnorB", 0 0, L_0x2a001e0; 1 drivers +v0x2810250_0 .net "AorB", 0 0, L_0x2a014c0; 1 drivers +v0x2810330_0 .net "AxorB", 0 0, L_0x2a01860; 1 drivers +v0x28103e0_0 .net "B", 0 0, L_0x2a01390; 1 drivers +v0x28104a0_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x2810520_0 .net "OrNorXorOut", 0 0, L_0x2b05280; 1 drivers +v0x28105a0_0 .net "XorNor", 0 0, L_0x2a01ce0; 1 drivers +v0x2810670_0 .net "nXor", 0 0, L_0x2a01750; 1 drivers +L_0x2a01e60 .part v0x2960210_0, 2, 1; +L_0x2b05430 .part v0x2960210_0, 0, 1; +S_0x280faf0 .scope module, "mux0" "TwoInMux" 3 184, 3 109, S_0x280f4b0; + .timescale -9 -12; +L_0x2a019c0/d .functor NOT 1, L_0x2a01e60, C4<0>, C4<0>, C4<0>; +L_0x2a019c0 .delay (10000,10000,10000) L_0x2a019c0/d; +L_0x2a01a80/d .functor AND 1, L_0x2a01860, L_0x2a019c0, C4<1>, C4<1>; +L_0x2a01a80 .delay (20000,20000,20000) L_0x2a01a80/d; +L_0x2a01b90/d .functor AND 1, L_0x2a001e0, L_0x2a01e60, C4<1>, C4<1>; +L_0x2a01b90 .delay (20000,20000,20000) L_0x2a01b90/d; +L_0x2a01ce0/d .functor OR 1, L_0x2a01a80, L_0x2a01b90, C4<0>, C4<0>; +L_0x2a01ce0 .delay (20000,20000,20000) L_0x2a01ce0/d; +v0x280fbe0_0 .net "S", 0 0, L_0x2a01e60; 1 drivers +v0x280fca0_0 .alias "in0", 0 0, v0x2810330_0; +v0x280fd40_0 .alias "in1", 0 0, v0x28101a0_0; +v0x280fde0_0 .net "nS", 0 0, L_0x2a019c0; 1 drivers +v0x280fe60_0 .net "out0", 0 0, L_0x2a01a80; 1 drivers +v0x280ff00_0 .net "out1", 0 0, L_0x2a01b90; 1 drivers +v0x280ffe0_0 .alias "outfinal", 0 0, v0x28105a0_0; +S_0x280f5a0 .scope module, "mux1" "TwoInMux" 3 185, 3 109, S_0x280f4b0; + .timescale -9 -12; +L_0x2a01f00/d .functor NOT 1, L_0x2b05430, C4<0>, C4<0>, C4<0>; +L_0x2a01f00 .delay (10000,10000,10000) L_0x2a01f00/d; +L_0x2a01fc0/d .functor AND 1, L_0x2a01ce0, L_0x2a01f00, C4<1>, C4<1>; +L_0x2a01fc0 .delay (20000,20000,20000) L_0x2a01fc0/d; +L_0x2b05190/d .functor AND 1, L_0x2a014c0, L_0x2b05430, C4<1>, C4<1>; +L_0x2b05190 .delay (20000,20000,20000) L_0x2b05190/d; +L_0x2b05280/d .functor OR 1, L_0x2a01fc0, L_0x2b05190, C4<0>, C4<0>; +L_0x2b05280 .delay (20000,20000,20000) L_0x2b05280/d; +v0x280f690_0 .net "S", 0 0, L_0x2b05430; 1 drivers +v0x280f710_0 .alias "in0", 0 0, v0x28105a0_0; +v0x280f7b0_0 .alias "in1", 0 0, v0x2810250_0; +v0x280f850_0 .net "nS", 0 0, L_0x2a01f00; 1 drivers +v0x280f8d0_0 .net "out0", 0 0, L_0x2a01fc0; 1 drivers +v0x280f970_0 .net "out1", 0 0, L_0x2b05190; 1 drivers +v0x280fa50_0 .alias "outfinal", 0 0, v0x2810520_0; +S_0x280dfb0 .scope generate, "orbits[21]" "orbits[21]" 3 258, 3 258, S_0x2801850; + .timescale -9 -12; +P_0x280dcc8 .param/l "i" 3 258, +C4<010101>; +S_0x280e0e0 .scope module, "attempt" "OrNorXor" 3 260, 3 165, S_0x280dfb0; + .timescale -9 -12; +L_0x2a01430/d .functor NOR 1, L_0x2b06880, L_0x2b05570, C4<0>, C4<0>; +L_0x2a01430 .delay (10000,10000,10000) L_0x2a01430/d; +L_0x2b057f0/d .functor NOT 1, L_0x2a01430, C4<0>, C4<0>, C4<0>; +L_0x2b057f0 .delay (10000,10000,10000) L_0x2b057f0/d; +L_0x2b05900/d .functor NAND 1, L_0x2b06880, L_0x2b05570, C4<1>, C4<1>; +L_0x2b05900 .delay (10000,10000,10000) L_0x2b05900/d; +L_0x2b05a60/d .functor NAND 1, L_0x2b05900, L_0x2b057f0, C4<1>, C4<1>; +L_0x2b05a60 .delay (10000,10000,10000) L_0x2b05a60/d; +L_0x2b05b70/d .functor NOT 1, L_0x2b05a60, C4<0>, C4<0>, C4<0>; +L_0x2b05b70 .delay (10000,10000,10000) L_0x2b05b70/d; +v0x280ec90_0 .net "A", 0 0, L_0x2b06880; 1 drivers +v0x280ed30_0 .net "AnandB", 0 0, L_0x2b05900; 1 drivers +v0x280edd0_0 .net "AnorB", 0 0, L_0x2a01430; 1 drivers +v0x280ee80_0 .net "AorB", 0 0, L_0x2b057f0; 1 drivers +v0x280ef60_0 .net "AxorB", 0 0, L_0x2b05b70; 1 drivers +v0x280f010_0 .net "B", 0 0, L_0x2b05570; 1 drivers +v0x280f0d0_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x280f150_0 .net "OrNorXorOut", 0 0, L_0x2b06570; 1 drivers +v0x280f1d0_0 .net "XorNor", 0 0, L_0x2b05ff0; 1 drivers +v0x280f2a0_0 .net "nXor", 0 0, L_0x2b05a60; 1 drivers +L_0x2b06170 .part v0x2960210_0, 2, 1; +L_0x2b06740 .part v0x2960210_0, 0, 1; +S_0x280e720 .scope module, "mux0" "TwoInMux" 3 184, 3 109, S_0x280e0e0; + .timescale -9 -12; +L_0x2b05cd0/d .functor NOT 1, L_0x2b06170, C4<0>, C4<0>, C4<0>; +L_0x2b05cd0 .delay (10000,10000,10000) L_0x2b05cd0/d; +L_0x2b05d90/d .functor AND 1, L_0x2b05b70, L_0x2b05cd0, C4<1>, C4<1>; +L_0x2b05d90 .delay (20000,20000,20000) L_0x2b05d90/d; +L_0x2b05ea0/d .functor AND 1, L_0x2a01430, L_0x2b06170, C4<1>, C4<1>; +L_0x2b05ea0 .delay (20000,20000,20000) L_0x2b05ea0/d; +L_0x2b05ff0/d .functor OR 1, L_0x2b05d90, L_0x2b05ea0, C4<0>, C4<0>; +L_0x2b05ff0 .delay (20000,20000,20000) L_0x2b05ff0/d; +v0x280e810_0 .net "S", 0 0, L_0x2b06170; 1 drivers +v0x280e8d0_0 .alias "in0", 0 0, v0x280ef60_0; +v0x280e970_0 .alias "in1", 0 0, v0x280edd0_0; +v0x280ea10_0 .net "nS", 0 0, L_0x2b05cd0; 1 drivers +v0x280ea90_0 .net "out0", 0 0, L_0x2b05d90; 1 drivers +v0x280eb30_0 .net "out1", 0 0, L_0x2b05ea0; 1 drivers +v0x280ec10_0 .alias "outfinal", 0 0, v0x280f1d0_0; +S_0x280e1d0 .scope module, "mux1" "TwoInMux" 3 185, 3 109, S_0x280e0e0; + .timescale -9 -12; +L_0x2b06210/d .functor NOT 1, L_0x2b06740, C4<0>, C4<0>, C4<0>; +L_0x2b06210 .delay (10000,10000,10000) L_0x2b06210/d; +L_0x2b062d0/d .functor AND 1, L_0x2b05ff0, L_0x2b06210, C4<1>, C4<1>; +L_0x2b062d0 .delay (20000,20000,20000) L_0x2b062d0/d; +L_0x2b06420/d .functor AND 1, L_0x2b057f0, L_0x2b06740, C4<1>, C4<1>; +L_0x2b06420 .delay (20000,20000,20000) L_0x2b06420/d; +L_0x2b06570/d .functor OR 1, L_0x2b062d0, L_0x2b06420, C4<0>, C4<0>; +L_0x2b06570 .delay (20000,20000,20000) L_0x2b06570/d; +v0x280e2c0_0 .net "S", 0 0, L_0x2b06740; 1 drivers +v0x280e340_0 .alias "in0", 0 0, v0x280f1d0_0; +v0x280e3e0_0 .alias "in1", 0 0, v0x280ee80_0; +v0x280e480_0 .net "nS", 0 0, L_0x2b06210; 1 drivers +v0x280e500_0 .net "out0", 0 0, L_0x2b062d0; 1 drivers +v0x280e5a0_0 .net "out1", 0 0, L_0x2b06420; 1 drivers +v0x280e680_0 .alias "outfinal", 0 0, v0x280f150_0; +S_0x280cbe0 .scope generate, "orbits[22]" "orbits[22]" 3 258, 3 258, S_0x2801850; + .timescale -9 -12; +P_0x280c8f8 .param/l "i" 3 258, +C4<010110>; +S_0x280cd10 .scope module, "attempt" "OrNorXor" 3 260, 3 165, S_0x280cbe0; + .timescale -9 -12; +L_0x2b05610/d .functor NOR 1, L_0x2b06920, L_0x2b069c0, C4<0>, C4<0>; +L_0x2b05610 .delay (10000,10000,10000) L_0x2b05610/d; +L_0x2b05700/d .functor NOT 1, L_0x2b05610, C4<0>, C4<0>, C4<0>; +L_0x2b05700 .delay (10000,10000,10000) L_0x2b05700/d; +L_0x2b06bf0/d .functor NAND 1, L_0x2b06920, L_0x2b069c0, C4<1>, C4<1>; +L_0x2b06bf0 .delay (10000,10000,10000) L_0x2b06bf0/d; +L_0x2b06d50/d .functor NAND 1, L_0x2b06bf0, L_0x2b05700, C4<1>, C4<1>; +L_0x2b06d50 .delay (10000,10000,10000) L_0x2b06d50/d; +L_0x2b06e60/d .functor NOT 1, L_0x2b06d50, C4<0>, C4<0>, C4<0>; +L_0x2b06e60 .delay (10000,10000,10000) L_0x2b06e60/d; +v0x280d8c0_0 .net "A", 0 0, L_0x2b06920; 1 drivers +v0x280d960_0 .net "AnandB", 0 0, L_0x2b06bf0; 1 drivers +v0x280da00_0 .net "AnorB", 0 0, L_0x2b05610; 1 drivers +v0x280dab0_0 .net "AorB", 0 0, L_0x2b05700; 1 drivers +v0x280db90_0 .net "AxorB", 0 0, L_0x2b06e60; 1 drivers +v0x280dc40_0 .net "B", 0 0, L_0x2b069c0; 1 drivers +v0x280dd00_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x280dd80_0 .net "OrNorXorOut", 0 0, L_0x2b07860; 1 drivers +v0x280de00_0 .net "XorNor", 0 0, L_0x2b072e0; 1 drivers +v0x280ded0_0 .net "nXor", 0 0, L_0x2b06d50; 1 drivers +L_0x2b07460 .part v0x2960210_0, 2, 1; +L_0x2b07a30 .part v0x2960210_0, 0, 1; +S_0x280d350 .scope module, "mux0" "TwoInMux" 3 184, 3 109, S_0x280cd10; + .timescale -9 -12; +L_0x2b06fc0/d .functor NOT 1, L_0x2b07460, C4<0>, C4<0>, C4<0>; +L_0x2b06fc0 .delay (10000,10000,10000) L_0x2b06fc0/d; +L_0x2b07080/d .functor AND 1, L_0x2b06e60, L_0x2b06fc0, C4<1>, C4<1>; +L_0x2b07080 .delay (20000,20000,20000) L_0x2b07080/d; +L_0x2b07190/d .functor AND 1, L_0x2b05610, L_0x2b07460, C4<1>, C4<1>; +L_0x2b07190 .delay (20000,20000,20000) L_0x2b07190/d; +L_0x2b072e0/d .functor OR 1, L_0x2b07080, L_0x2b07190, C4<0>, C4<0>; +L_0x2b072e0 .delay (20000,20000,20000) L_0x2b072e0/d; +v0x280d440_0 .net "S", 0 0, L_0x2b07460; 1 drivers +v0x280d500_0 .alias "in0", 0 0, v0x280db90_0; +v0x280d5a0_0 .alias "in1", 0 0, v0x280da00_0; +v0x280d640_0 .net "nS", 0 0, L_0x2b06fc0; 1 drivers +v0x280d6c0_0 .net "out0", 0 0, L_0x2b07080; 1 drivers +v0x280d760_0 .net "out1", 0 0, L_0x2b07190; 1 drivers +v0x280d840_0 .alias "outfinal", 0 0, v0x280de00_0; +S_0x280ce00 .scope module, "mux1" "TwoInMux" 3 185, 3 109, S_0x280cd10; + .timescale -9 -12; +L_0x2b07500/d .functor NOT 1, L_0x2b07a30, C4<0>, C4<0>, C4<0>; +L_0x2b07500 .delay (10000,10000,10000) L_0x2b07500/d; +L_0x2b075c0/d .functor AND 1, L_0x2b072e0, L_0x2b07500, C4<1>, C4<1>; +L_0x2b075c0 .delay (20000,20000,20000) L_0x2b075c0/d; +L_0x2b07710/d .functor AND 1, L_0x2b05700, L_0x2b07a30, C4<1>, C4<1>; +L_0x2b07710 .delay (20000,20000,20000) L_0x2b07710/d; +L_0x2b07860/d .functor OR 1, L_0x2b075c0, L_0x2b07710, C4<0>, C4<0>; +L_0x2b07860 .delay (20000,20000,20000) L_0x2b07860/d; +v0x280cef0_0 .net "S", 0 0, L_0x2b07a30; 1 drivers +v0x280cf70_0 .alias "in0", 0 0, v0x280de00_0; +v0x280d010_0 .alias "in1", 0 0, v0x280dab0_0; +v0x280d0b0_0 .net "nS", 0 0, L_0x2b07500; 1 drivers +v0x280d130_0 .net "out0", 0 0, L_0x2b075c0; 1 drivers +v0x280d1d0_0 .net "out1", 0 0, L_0x2b07710; 1 drivers +v0x280d2b0_0 .alias "outfinal", 0 0, v0x280dd80_0; +S_0x280b810 .scope generate, "orbits[23]" "orbits[23]" 3 258, 3 258, S_0x2801850; + .timescale -9 -12; +P_0x280b528 .param/l "i" 3 258, +C4<010111>; +S_0x280b940 .scope module, "attempt" "OrNorXor" 3 260, 3 165, S_0x280b810; + .timescale -9 -12; +L_0x2b06a60/d .functor NOR 1, L_0x2b08e70, L_0x2b07b70, C4<0>, C4<0>; +L_0x2b06a60 .delay (10000,10000,10000) L_0x2b06a60/d; +L_0x2b07de0/d .functor NOT 1, L_0x2b06a60, C4<0>, C4<0>, C4<0>; +L_0x2b07de0 .delay (10000,10000,10000) L_0x2b07de0/d; +L_0x2b07ef0/d .functor NAND 1, L_0x2b08e70, L_0x2b07b70, C4<1>, C4<1>; +L_0x2b07ef0 .delay (10000,10000,10000) L_0x2b07ef0/d; +L_0x2b08050/d .functor NAND 1, L_0x2b07ef0, L_0x2b07de0, C4<1>, C4<1>; +L_0x2b08050 .delay (10000,10000,10000) L_0x2b08050/d; +L_0x2b08160/d .functor NOT 1, L_0x2b08050, C4<0>, C4<0>, C4<0>; +L_0x2b08160 .delay (10000,10000,10000) L_0x2b08160/d; +v0x280c4f0_0 .net "A", 0 0, L_0x2b08e70; 1 drivers +v0x280c590_0 .net "AnandB", 0 0, L_0x2b07ef0; 1 drivers +v0x280c630_0 .net "AnorB", 0 0, L_0x2b06a60; 1 drivers +v0x280c6e0_0 .net "AorB", 0 0, L_0x2b07de0; 1 drivers +v0x280c7c0_0 .net "AxorB", 0 0, L_0x2b08160; 1 drivers +v0x280c870_0 .net "B", 0 0, L_0x2b07b70; 1 drivers +v0x280c930_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x280c9b0_0 .net "OrNorXorOut", 0 0, L_0x2b08b60; 1 drivers +v0x280ca30_0 .net "XorNor", 0 0, L_0x2b085e0; 1 drivers +v0x280cb00_0 .net "nXor", 0 0, L_0x2b08050; 1 drivers +L_0x2b08760 .part v0x2960210_0, 2, 1; +L_0x2b08d30 .part v0x2960210_0, 0, 1; +S_0x280bf80 .scope module, "mux0" "TwoInMux" 3 184, 3 109, S_0x280b940; + .timescale -9 -12; +L_0x2b082c0/d .functor NOT 1, L_0x2b08760, C4<0>, C4<0>, C4<0>; +L_0x2b082c0 .delay (10000,10000,10000) L_0x2b082c0/d; +L_0x2b08380/d .functor AND 1, L_0x2b08160, L_0x2b082c0, C4<1>, C4<1>; +L_0x2b08380 .delay (20000,20000,20000) L_0x2b08380/d; +L_0x2b08490/d .functor AND 1, L_0x2b06a60, L_0x2b08760, C4<1>, C4<1>; +L_0x2b08490 .delay (20000,20000,20000) L_0x2b08490/d; +L_0x2b085e0/d .functor OR 1, L_0x2b08380, L_0x2b08490, C4<0>, C4<0>; +L_0x2b085e0 .delay (20000,20000,20000) L_0x2b085e0/d; +v0x280c070_0 .net "S", 0 0, L_0x2b08760; 1 drivers +v0x280c130_0 .alias "in0", 0 0, v0x280c7c0_0; +v0x280c1d0_0 .alias "in1", 0 0, v0x280c630_0; +v0x280c270_0 .net "nS", 0 0, L_0x2b082c0; 1 drivers +v0x280c2f0_0 .net "out0", 0 0, L_0x2b08380; 1 drivers +v0x280c390_0 .net "out1", 0 0, L_0x2b08490; 1 drivers +v0x280c470_0 .alias "outfinal", 0 0, v0x280ca30_0; +S_0x280ba30 .scope module, "mux1" "TwoInMux" 3 185, 3 109, S_0x280b940; + .timescale -9 -12; +L_0x2b08800/d .functor NOT 1, L_0x2b08d30, C4<0>, C4<0>, C4<0>; +L_0x2b08800 .delay (10000,10000,10000) L_0x2b08800/d; +L_0x2b088c0/d .functor AND 1, L_0x2b085e0, L_0x2b08800, C4<1>, C4<1>; +L_0x2b088c0 .delay (20000,20000,20000) L_0x2b088c0/d; +L_0x2b08a10/d .functor AND 1, L_0x2b07de0, L_0x2b08d30, C4<1>, C4<1>; +L_0x2b08a10 .delay (20000,20000,20000) L_0x2b08a10/d; +L_0x2b08b60/d .functor OR 1, L_0x2b088c0, L_0x2b08a10, C4<0>, C4<0>; +L_0x2b08b60 .delay (20000,20000,20000) L_0x2b08b60/d; +v0x280bb20_0 .net "S", 0 0, L_0x2b08d30; 1 drivers +v0x280bba0_0 .alias "in0", 0 0, v0x280ca30_0; +v0x280bc40_0 .alias "in1", 0 0, v0x280c6e0_0; +v0x280bce0_0 .net "nS", 0 0, L_0x2b08800; 1 drivers +v0x280bd60_0 .net "out0", 0 0, L_0x2b088c0; 1 drivers +v0x280be00_0 .net "out1", 0 0, L_0x2b08a10; 1 drivers +v0x280bee0_0 .alias "outfinal", 0 0, v0x280c9b0_0; +S_0x280a440 .scope generate, "orbits[24]" "orbits[24]" 3 258, 3 258, S_0x2801850; + .timescale -9 -12; +P_0x280a158 .param/l "i" 3 258, +C4<011000>; +S_0x280a570 .scope module, "attempt" "OrNorXor" 3 260, 3 165, S_0x280a440; + .timescale -9 -12; +L_0x2b07c10/d .functor NOR 1, L_0x2b08f10, L_0x2b08fb0, C4<0>, C4<0>; +L_0x2b07c10 .delay (10000,10000,10000) L_0x2b07c10/d; +L_0x2b07d00/d .functor NOT 1, L_0x2b07c10, C4<0>, C4<0>, C4<0>; +L_0x2b07d00 .delay (10000,10000,10000) L_0x2b07d00/d; +L_0x2b091f0/d .functor NAND 1, L_0x2b08f10, L_0x2b08fb0, C4<1>, C4<1>; +L_0x2b091f0 .delay (10000,10000,10000) L_0x2b091f0/d; +L_0x2b09350/d .functor NAND 1, L_0x2b091f0, L_0x2b07d00, C4<1>, C4<1>; +L_0x2b09350 .delay (10000,10000,10000) L_0x2b09350/d; +L_0x2b09460/d .functor NOT 1, L_0x2b09350, C4<0>, C4<0>, C4<0>; +L_0x2b09460 .delay (10000,10000,10000) L_0x2b09460/d; +v0x280b120_0 .net "A", 0 0, L_0x2b08f10; 1 drivers +v0x280b1c0_0 .net "AnandB", 0 0, L_0x2b091f0; 1 drivers +v0x280b260_0 .net "AnorB", 0 0, L_0x2b07c10; 1 drivers +v0x280b310_0 .net "AorB", 0 0, L_0x2b07d00; 1 drivers +v0x280b3f0_0 .net "AxorB", 0 0, L_0x2b09460; 1 drivers +v0x280b4a0_0 .net "B", 0 0, L_0x2b08fb0; 1 drivers +v0x280b560_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x280b5e0_0 .net "OrNorXorOut", 0 0, L_0x2b09e60; 1 drivers +v0x280b660_0 .net "XorNor", 0 0, L_0x2b098e0; 1 drivers +v0x280b730_0 .net "nXor", 0 0, L_0x2b09350; 1 drivers +L_0x2b09a60 .part v0x2960210_0, 2, 1; +L_0x2b0a030 .part v0x2960210_0, 0, 1; +S_0x280abb0 .scope module, "mux0" "TwoInMux" 3 184, 3 109, S_0x280a570; + .timescale -9 -12; +L_0x2b095c0/d .functor NOT 1, L_0x2b09a60, C4<0>, C4<0>, C4<0>; +L_0x2b095c0 .delay (10000,10000,10000) L_0x2b095c0/d; +L_0x2b09680/d .functor AND 1, L_0x2b09460, L_0x2b095c0, C4<1>, C4<1>; +L_0x2b09680 .delay (20000,20000,20000) L_0x2b09680/d; +L_0x2b09790/d .functor AND 1, L_0x2b07c10, L_0x2b09a60, C4<1>, C4<1>; +L_0x2b09790 .delay (20000,20000,20000) L_0x2b09790/d; +L_0x2b098e0/d .functor OR 1, L_0x2b09680, L_0x2b09790, C4<0>, C4<0>; +L_0x2b098e0 .delay (20000,20000,20000) L_0x2b098e0/d; +v0x280aca0_0 .net "S", 0 0, L_0x2b09a60; 1 drivers +v0x280ad60_0 .alias "in0", 0 0, v0x280b3f0_0; +v0x280ae00_0 .alias "in1", 0 0, v0x280b260_0; +v0x280aea0_0 .net "nS", 0 0, L_0x2b095c0; 1 drivers +v0x280af20_0 .net "out0", 0 0, L_0x2b09680; 1 drivers +v0x280afc0_0 .net "out1", 0 0, L_0x2b09790; 1 drivers +v0x280b0a0_0 .alias "outfinal", 0 0, v0x280b660_0; +S_0x280a660 .scope module, "mux1" "TwoInMux" 3 185, 3 109, S_0x280a570; + .timescale -9 -12; +L_0x2b09b00/d .functor NOT 1, L_0x2b0a030, C4<0>, C4<0>, C4<0>; +L_0x2b09b00 .delay (10000,10000,10000) L_0x2b09b00/d; +L_0x2b09bc0/d .functor AND 1, L_0x2b098e0, L_0x2b09b00, C4<1>, C4<1>; +L_0x2b09bc0 .delay (20000,20000,20000) L_0x2b09bc0/d; +L_0x2b09d10/d .functor AND 1, L_0x2b07d00, L_0x2b0a030, C4<1>, C4<1>; +L_0x2b09d10 .delay (20000,20000,20000) L_0x2b09d10/d; +L_0x2b09e60/d .functor OR 1, L_0x2b09bc0, L_0x2b09d10, C4<0>, C4<0>; +L_0x2b09e60 .delay (20000,20000,20000) L_0x2b09e60/d; +v0x280a750_0 .net "S", 0 0, L_0x2b0a030; 1 drivers +v0x280a7d0_0 .alias "in0", 0 0, v0x280b660_0; +v0x280a870_0 .alias "in1", 0 0, v0x280b310_0; +v0x280a910_0 .net "nS", 0 0, L_0x2b09b00; 1 drivers +v0x280a990_0 .net "out0", 0 0, L_0x2b09bc0; 1 drivers +v0x280aa30_0 .net "out1", 0 0, L_0x2b09d10; 1 drivers +v0x280ab10_0 .alias "outfinal", 0 0, v0x280b5e0_0; +S_0x2809070 .scope generate, "orbits[25]" "orbits[25]" 3 258, 3 258, S_0x2801850; + .timescale -9 -12; +P_0x2808d88 .param/l "i" 3 258, +C4<011001>; +S_0x28091a0 .scope module, "attempt" "OrNorXor" 3 260, 3 165, S_0x2809070; + .timescale -9 -12; +L_0x2b09050/d .functor NOR 1, L_0x2b0b470, L_0x2b0a170, C4<0>, C4<0>; +L_0x2b09050 .delay (10000,10000,10000) L_0x2b09050/d; +L_0x2b0a3c0/d .functor NOT 1, L_0x2b09050, C4<0>, C4<0>, C4<0>; +L_0x2b0a3c0 .delay (10000,10000,10000) L_0x2b0a3c0/d; +L_0x2b0a4f0/d .functor NAND 1, L_0x2b0b470, L_0x2b0a170, C4<1>, C4<1>; +L_0x2b0a4f0 .delay (10000,10000,10000) L_0x2b0a4f0/d; +L_0x2b0a650/d .functor NAND 1, L_0x2b0a4f0, L_0x2b0a3c0, C4<1>, C4<1>; +L_0x2b0a650 .delay (10000,10000,10000) L_0x2b0a650/d; +L_0x2b0a760/d .functor NOT 1, L_0x2b0a650, C4<0>, C4<0>, C4<0>; +L_0x2b0a760 .delay (10000,10000,10000) L_0x2b0a760/d; +v0x2809d50_0 .net "A", 0 0, L_0x2b0b470; 1 drivers +v0x2809df0_0 .net "AnandB", 0 0, L_0x2b0a4f0; 1 drivers +v0x2809e90_0 .net "AnorB", 0 0, L_0x2b09050; 1 drivers +v0x2809f40_0 .net "AorB", 0 0, L_0x2b0a3c0; 1 drivers +v0x280a020_0 .net "AxorB", 0 0, L_0x2b0a760; 1 drivers +v0x280a0d0_0 .net "B", 0 0, L_0x2b0a170; 1 drivers +v0x280a190_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x280a210_0 .net "OrNorXorOut", 0 0, L_0x2b0b160; 1 drivers +v0x280a290_0 .net "XorNor", 0 0, L_0x2b0abe0; 1 drivers +v0x280a360_0 .net "nXor", 0 0, L_0x2b0a650; 1 drivers +L_0x2b0ad60 .part v0x2960210_0, 2, 1; +L_0x2b0b330 .part v0x2960210_0, 0, 1; +S_0x28097e0 .scope module, "mux0" "TwoInMux" 3 184, 3 109, S_0x28091a0; + .timescale -9 -12; +L_0x2b0a8c0/d .functor NOT 1, L_0x2b0ad60, C4<0>, C4<0>, C4<0>; +L_0x2b0a8c0 .delay (10000,10000,10000) L_0x2b0a8c0/d; +L_0x2b0a980/d .functor AND 1, L_0x2b0a760, L_0x2b0a8c0, C4<1>, C4<1>; +L_0x2b0a980 .delay (20000,20000,20000) L_0x2b0a980/d; +L_0x2b0aa90/d .functor AND 1, L_0x2b09050, L_0x2b0ad60, C4<1>, C4<1>; +L_0x2b0aa90 .delay (20000,20000,20000) L_0x2b0aa90/d; +L_0x2b0abe0/d .functor OR 1, L_0x2b0a980, L_0x2b0aa90, C4<0>, C4<0>; +L_0x2b0abe0 .delay (20000,20000,20000) L_0x2b0abe0/d; +v0x28098d0_0 .net "S", 0 0, L_0x2b0ad60; 1 drivers +v0x2809990_0 .alias "in0", 0 0, v0x280a020_0; +v0x2809a30_0 .alias "in1", 0 0, v0x2809e90_0; +v0x2809ad0_0 .net "nS", 0 0, L_0x2b0a8c0; 1 drivers +v0x2809b50_0 .net "out0", 0 0, L_0x2b0a980; 1 drivers +v0x2809bf0_0 .net "out1", 0 0, L_0x2b0aa90; 1 drivers +v0x2809cd0_0 .alias "outfinal", 0 0, v0x280a290_0; +S_0x2809290 .scope module, "mux1" "TwoInMux" 3 185, 3 109, S_0x28091a0; + .timescale -9 -12; +L_0x2b0ae00/d .functor NOT 1, L_0x2b0b330, C4<0>, C4<0>, C4<0>; +L_0x2b0ae00 .delay (10000,10000,10000) L_0x2b0ae00/d; +L_0x2b0aec0/d .functor AND 1, L_0x2b0abe0, L_0x2b0ae00, C4<1>, C4<1>; +L_0x2b0aec0 .delay (20000,20000,20000) L_0x2b0aec0/d; +L_0x2b0b010/d .functor AND 1, L_0x2b0a3c0, L_0x2b0b330, C4<1>, C4<1>; +L_0x2b0b010 .delay (20000,20000,20000) L_0x2b0b010/d; +L_0x2b0b160/d .functor OR 1, L_0x2b0aec0, L_0x2b0b010, C4<0>, C4<0>; +L_0x2b0b160 .delay (20000,20000,20000) L_0x2b0b160/d; +v0x2809380_0 .net "S", 0 0, L_0x2b0b330; 1 drivers +v0x2809400_0 .alias "in0", 0 0, v0x280a290_0; +v0x28094a0_0 .alias "in1", 0 0, v0x2809f40_0; +v0x2809540_0 .net "nS", 0 0, L_0x2b0ae00; 1 drivers +v0x28095c0_0 .net "out0", 0 0, L_0x2b0aec0; 1 drivers +v0x2809660_0 .net "out1", 0 0, L_0x2b0b010; 1 drivers +v0x2809740_0 .alias "outfinal", 0 0, v0x280a210_0; +S_0x2807cb0 .scope generate, "orbits[26]" "orbits[26]" 3 258, 3 258, S_0x2801850; + .timescale -9 -12; +P_0x2807978 .param/l "i" 3 258, +C4<011010>; +S_0x2807de0 .scope module, "attempt" "OrNorXor" 3 260, 3 165, S_0x2807cb0; + .timescale -9 -12; +L_0x2b0a210/d .functor NOR 1, L_0x2b0b510, L_0x2b0b5b0, C4<0>, C4<0>; +L_0x2b0a210 .delay (10000,10000,10000) L_0x2b0a210/d; +L_0x2b0a300/d .functor NOT 1, L_0x2b0a210, C4<0>, C4<0>, C4<0>; +L_0x2b0a300 .delay (10000,10000,10000) L_0x2b0a300/d; +L_0x2b0b7e0/d .functor NAND 1, L_0x2b0b510, L_0x2b0b5b0, C4<1>, C4<1>; +L_0x2b0b7e0 .delay (10000,10000,10000) L_0x2b0b7e0/d; +L_0x2b0b940/d .functor NAND 1, L_0x2b0b7e0, L_0x2b0a300, C4<1>, C4<1>; +L_0x2b0b940 .delay (10000,10000,10000) L_0x2b0b940/d; +L_0x2b0ba50/d .functor NOT 1, L_0x2b0b940, C4<0>, C4<0>, C4<0>; +L_0x2b0ba50 .delay (10000,10000,10000) L_0x2b0ba50/d; +v0x28089b0_0 .net "A", 0 0, L_0x2b0b510; 1 drivers +v0x2808a50_0 .net "AnandB", 0 0, L_0x2b0b7e0; 1 drivers +v0x2808af0_0 .net "AnorB", 0 0, L_0x2b0a210; 1 drivers +v0x2808b70_0 .net "AorB", 0 0, L_0x2b0a300; 1 drivers +v0x2808c50_0 .net "AxorB", 0 0, L_0x2b0ba50; 1 drivers +v0x2808d00_0 .net "B", 0 0, L_0x2b0b5b0; 1 drivers +v0x2808dc0_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x2808e40_0 .net "OrNorXorOut", 0 0, L_0x2b0c450; 1 drivers +v0x2808ec0_0 .net "XorNor", 0 0, L_0x2b0bed0; 1 drivers +v0x2808f90_0 .net "nXor", 0 0, L_0x2b0b940; 1 drivers +L_0x2b0c050 .part v0x2960210_0, 2, 1; +L_0x2b0c620 .part v0x2960210_0, 0, 1; +S_0x2808440 .scope module, "mux0" "TwoInMux" 3 184, 3 109, S_0x2807de0; + .timescale -9 -12; +L_0x2b0bbb0/d .functor NOT 1, L_0x2b0c050, C4<0>, C4<0>, C4<0>; +L_0x2b0bbb0 .delay (10000,10000,10000) L_0x2b0bbb0/d; +L_0x2b0bc70/d .functor AND 1, L_0x2b0ba50, L_0x2b0bbb0, C4<1>, C4<1>; +L_0x2b0bc70 .delay (20000,20000,20000) L_0x2b0bc70/d; +L_0x2b0bd80/d .functor AND 1, L_0x2b0a210, L_0x2b0c050, C4<1>, C4<1>; +L_0x2b0bd80 .delay (20000,20000,20000) L_0x2b0bd80/d; +L_0x2b0bed0/d .functor OR 1, L_0x2b0bc70, L_0x2b0bd80, C4<0>, C4<0>; +L_0x2b0bed0 .delay (20000,20000,20000) L_0x2b0bed0/d; +v0x2808530_0 .net "S", 0 0, L_0x2b0c050; 1 drivers +v0x28085f0_0 .alias "in0", 0 0, v0x2808c50_0; +v0x2808690_0 .alias "in1", 0 0, v0x2808af0_0; +v0x2808730_0 .net "nS", 0 0, L_0x2b0bbb0; 1 drivers +v0x28087b0_0 .net "out0", 0 0, L_0x2b0bc70; 1 drivers +v0x2808850_0 .net "out1", 0 0, L_0x2b0bd80; 1 drivers +v0x2808930_0 .alias "outfinal", 0 0, v0x2808ec0_0; +S_0x2807ed0 .scope module, "mux1" "TwoInMux" 3 185, 3 109, S_0x2807de0; + .timescale -9 -12; +L_0x2b0c0f0/d .functor NOT 1, L_0x2b0c620, C4<0>, C4<0>, C4<0>; +L_0x2b0c0f0 .delay (10000,10000,10000) L_0x2b0c0f0/d; +L_0x2b0c1b0/d .functor AND 1, L_0x2b0bed0, L_0x2b0c0f0, C4<1>, C4<1>; +L_0x2b0c1b0 .delay (20000,20000,20000) L_0x2b0c1b0/d; +L_0x2b0c300/d .functor AND 1, L_0x2b0a300, L_0x2b0c620, C4<1>, C4<1>; +L_0x2b0c300 .delay (20000,20000,20000) L_0x2b0c300/d; +L_0x2b0c450/d .functor OR 1, L_0x2b0c1b0, L_0x2b0c300, C4<0>, C4<0>; +L_0x2b0c450 .delay (20000,20000,20000) L_0x2b0c450/d; +v0x2807fc0_0 .net "S", 0 0, L_0x2b0c620; 1 drivers +v0x2808060_0 .alias "in0", 0 0, v0x2808ec0_0; +v0x2808100_0 .alias "in1", 0 0, v0x2808b70_0; +v0x28081a0_0 .net "nS", 0 0, L_0x2b0c0f0; 1 drivers +v0x2808220_0 .net "out0", 0 0, L_0x2b0c1b0; 1 drivers +v0x28082c0_0 .net "out1", 0 0, L_0x2b0c300; 1 drivers +v0x28083a0_0 .alias "outfinal", 0 0, v0x2808e40_0; +S_0x28068c0 .scope generate, "orbits[27]" "orbits[27]" 3 258, 3 258, S_0x2801850; + .timescale -9 -12; +P_0x28065d8 .param/l "i" 3 258, +C4<011011>; +S_0x28069f0 .scope module, "attempt" "OrNorXor" 3 260, 3 165, S_0x28068c0; + .timescale -9 -12; +L_0x2b0b650/d .functor NOR 1, L_0x2b0da90, L_0x2b0c760, C4<0>, C4<0>; +L_0x2b0b650 .delay (10000,10000,10000) L_0x2b0b650/d; +L_0x2b0c9e0/d .functor NOT 1, L_0x2b0b650, C4<0>, C4<0>, C4<0>; +L_0x2b0c9e0 .delay (10000,10000,10000) L_0x2b0c9e0/d; +L_0x2b0caf0/d .functor NAND 1, L_0x2b0da90, L_0x2b0c760, C4<1>, C4<1>; +L_0x2b0caf0 .delay (10000,10000,10000) L_0x2b0caf0/d; +L_0x2b0cc50/d .functor NAND 1, L_0x2b0caf0, L_0x2b0c9e0, C4<1>, C4<1>; +L_0x2b0cc50 .delay (10000,10000,10000) L_0x2b0cc50/d; +L_0x2b0cd60/d .functor NOT 1, L_0x2b0cc50, C4<0>, C4<0>, C4<0>; +L_0x2b0cd60 .delay (10000,10000,10000) L_0x2b0cd60/d; +v0x2807570_0 .net "A", 0 0, L_0x2b0da90; 1 drivers +v0x2807610_0 .net "AnandB", 0 0, L_0x2b0caf0; 1 drivers +v0x28076b0_0 .net "AnorB", 0 0, L_0x2b0b650; 1 drivers +v0x2807760_0 .net "AorB", 0 0, L_0x2b0c9e0; 1 drivers +v0x2807840_0 .net "AxorB", 0 0, L_0x2b0cd60; 1 drivers +v0x28078f0_0 .net "B", 0 0, L_0x2b0c760; 1 drivers +v0x28079b0_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x2807a30_0 .net "OrNorXorOut", 0 0, L_0x2b0d780; 1 drivers +v0x2807b00_0 .net "XorNor", 0 0, L_0x2b0d200; 1 drivers +v0x2807bd0_0 .net "nXor", 0 0, L_0x2b0cc50; 1 drivers +L_0x2b0d380 .part v0x2960210_0, 2, 1; +L_0x2b0d950 .part v0x2960210_0, 0, 1; +S_0x2807010 .scope module, "mux0" "TwoInMux" 3 184, 3 109, S_0x28069f0; + .timescale -9 -12; +L_0x2b0cec0/d .functor NOT 1, L_0x2b0d380, C4<0>, C4<0>, C4<0>; +L_0x2b0cec0 .delay (10000,10000,10000) L_0x2b0cec0/d; +L_0x2b0cfa0/d .functor AND 1, L_0x2b0cd60, L_0x2b0cec0, C4<1>, C4<1>; +L_0x2b0cfa0 .delay (20000,20000,20000) L_0x2b0cfa0/d; +L_0x2b0d0b0/d .functor AND 1, L_0x2b0b650, L_0x2b0d380, C4<1>, C4<1>; +L_0x2b0d0b0 .delay (20000,20000,20000) L_0x2b0d0b0/d; +L_0x2b0d200/d .functor OR 1, L_0x2b0cfa0, L_0x2b0d0b0, C4<0>, C4<0>; +L_0x2b0d200 .delay (20000,20000,20000) L_0x2b0d200/d; +v0x2807100_0 .net "S", 0 0, L_0x2b0d380; 1 drivers +v0x2807180_0 .alias "in0", 0 0, v0x2807840_0; +v0x2807220_0 .alias "in1", 0 0, v0x28076b0_0; +v0x28072c0_0 .net "nS", 0 0, L_0x2b0cec0; 1 drivers +v0x2807370_0 .net "out0", 0 0, L_0x2b0cfa0; 1 drivers +v0x2807410_0 .net "out1", 0 0, L_0x2b0d0b0; 1 drivers +v0x28074f0_0 .alias "outfinal", 0 0, v0x2807b00_0; +S_0x2806ae0 .scope module, "mux1" "TwoInMux" 3 185, 3 109, S_0x28069f0; + .timescale -9 -12; +L_0x2b0d420/d .functor NOT 1, L_0x2b0d950, C4<0>, C4<0>, C4<0>; +L_0x2b0d420 .delay (10000,10000,10000) L_0x2b0d420/d; +L_0x2b0d4e0/d .functor AND 1, L_0x2b0d200, L_0x2b0d420, C4<1>, C4<1>; +L_0x2b0d4e0 .delay (20000,20000,20000) L_0x2b0d4e0/d; +L_0x2b0d630/d .functor AND 1, L_0x2b0c9e0, L_0x2b0d950, C4<1>, C4<1>; +L_0x2b0d630 .delay (20000,20000,20000) L_0x2b0d630/d; +L_0x2b0d780/d .functor OR 1, L_0x2b0d4e0, L_0x2b0d630, C4<0>, C4<0>; +L_0x2b0d780 .delay (20000,20000,20000) L_0x2b0d780/d; +v0x2806bd0_0 .net "S", 0 0, L_0x2b0d950; 1 drivers +v0x2806c50_0 .alias "in0", 0 0, v0x2807b00_0; +v0x2806cf0_0 .alias "in1", 0 0, v0x2807760_0; +v0x2806d90_0 .net "nS", 0 0, L_0x2b0d420; 1 drivers +v0x2806e10_0 .net "out0", 0 0, L_0x2b0d4e0; 1 drivers +v0x2806eb0_0 .net "out1", 0 0, L_0x2b0d630; 1 drivers +v0x2806f90_0 .alias "outfinal", 0 0, v0x2807a30_0; +S_0x28054f0 .scope generate, "orbits[28]" "orbits[28]" 3 258, 3 258, S_0x2801850; + .timescale -9 -12; +P_0x2805208 .param/l "i" 3 258, +C4<011100>; +S_0x2805620 .scope module, "attempt" "OrNorXor" 3 260, 3 165, S_0x28054f0; + .timescale -9 -12; +L_0x2b0c800/d .functor NOR 1, L_0x2b0db30, L_0x2b0dbd0, C4<0>, C4<0>; +L_0x2b0c800 .delay (10000,10000,10000) L_0x2b0c800/d; +L_0x2b0c8f0/d .functor NOT 1, L_0x2b0c800, C4<0>, C4<0>, C4<0>; +L_0x2b0c8f0 .delay (10000,10000,10000) L_0x2b0c8f0/d; +L_0x2b0de10/d .functor NAND 1, L_0x2b0db30, L_0x2b0dbd0, C4<1>, C4<1>; +L_0x2b0de10 .delay (10000,10000,10000) L_0x2b0de10/d; +L_0x2b0df70/d .functor NAND 1, L_0x2b0de10, L_0x2b0c8f0, C4<1>, C4<1>; +L_0x2b0df70 .delay (10000,10000,10000) L_0x2b0df70/d; +L_0x2b0e080/d .functor NOT 1, L_0x2b0df70, C4<0>, C4<0>, C4<0>; +L_0x2b0e080 .delay (10000,10000,10000) L_0x2b0e080/d; +v0x28061d0_0 .net "A", 0 0, L_0x2b0db30; 1 drivers +v0x2806270_0 .net "AnandB", 0 0, L_0x2b0de10; 1 drivers +v0x2806310_0 .net "AnorB", 0 0, L_0x2b0c800; 1 drivers +v0x28063c0_0 .net "AorB", 0 0, L_0x2b0c8f0; 1 drivers +v0x28064a0_0 .net "AxorB", 0 0, L_0x2b0e080; 1 drivers +v0x2806550_0 .net "B", 0 0, L_0x2b0dbd0; 1 drivers +v0x2806610_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x2806690_0 .net "OrNorXorOut", 0 0, L_0x2b0ea80; 1 drivers +v0x2806710_0 .net "XorNor", 0 0, L_0x2b0e500; 1 drivers +v0x28067e0_0 .net "nXor", 0 0, L_0x2b0df70; 1 drivers +L_0x2b0e680 .part v0x2960210_0, 2, 1; +L_0x2b0ec50 .part v0x2960210_0, 0, 1; +S_0x2805c60 .scope module, "mux0" "TwoInMux" 3 184, 3 109, S_0x2805620; + .timescale -9 -12; +L_0x2b0e1e0/d .functor NOT 1, L_0x2b0e680, C4<0>, C4<0>, C4<0>; +L_0x2b0e1e0 .delay (10000,10000,10000) L_0x2b0e1e0/d; +L_0x2b0e2a0/d .functor AND 1, L_0x2b0e080, L_0x2b0e1e0, C4<1>, C4<1>; +L_0x2b0e2a0 .delay (20000,20000,20000) L_0x2b0e2a0/d; +L_0x2b0e3b0/d .functor AND 1, L_0x2b0c800, L_0x2b0e680, C4<1>, C4<1>; +L_0x2b0e3b0 .delay (20000,20000,20000) L_0x2b0e3b0/d; +L_0x2b0e500/d .functor OR 1, L_0x2b0e2a0, L_0x2b0e3b0, C4<0>, C4<0>; +L_0x2b0e500 .delay (20000,20000,20000) L_0x2b0e500/d; +v0x2805d50_0 .net "S", 0 0, L_0x2b0e680; 1 drivers +v0x2805e10_0 .alias "in0", 0 0, v0x28064a0_0; +v0x2805eb0_0 .alias "in1", 0 0, v0x2806310_0; +v0x2805f50_0 .net "nS", 0 0, L_0x2b0e1e0; 1 drivers +v0x2805fd0_0 .net "out0", 0 0, L_0x2b0e2a0; 1 drivers +v0x2806070_0 .net "out1", 0 0, L_0x2b0e3b0; 1 drivers +v0x2806150_0 .alias "outfinal", 0 0, v0x2806710_0; +S_0x2805710 .scope module, "mux1" "TwoInMux" 3 185, 3 109, S_0x2805620; + .timescale -9 -12; +L_0x2b0e720/d .functor NOT 1, L_0x2b0ec50, C4<0>, C4<0>, C4<0>; +L_0x2b0e720 .delay (10000,10000,10000) L_0x2b0e720/d; +L_0x2b0e7e0/d .functor AND 1, L_0x2b0e500, L_0x2b0e720, C4<1>, C4<1>; +L_0x2b0e7e0 .delay (20000,20000,20000) L_0x2b0e7e0/d; +L_0x2b0e930/d .functor AND 1, L_0x2b0c8f0, L_0x2b0ec50, C4<1>, C4<1>; +L_0x2b0e930 .delay (20000,20000,20000) L_0x2b0e930/d; +L_0x2b0ea80/d .functor OR 1, L_0x2b0e7e0, L_0x2b0e930, C4<0>, C4<0>; +L_0x2b0ea80 .delay (20000,20000,20000) L_0x2b0ea80/d; +v0x2805800_0 .net "S", 0 0, L_0x2b0ec50; 1 drivers +v0x2805880_0 .alias "in0", 0 0, v0x2806710_0; +v0x2805920_0 .alias "in1", 0 0, v0x28063c0_0; +v0x28059c0_0 .net "nS", 0 0, L_0x2b0e720; 1 drivers +v0x2805a40_0 .net "out0", 0 0, L_0x2b0e7e0; 1 drivers +v0x2805ae0_0 .net "out1", 0 0, L_0x2b0e930; 1 drivers +v0x2805bc0_0 .alias "outfinal", 0 0, v0x2806690_0; +S_0x2804120 .scope generate, "orbits[29]" "orbits[29]" 3 258, 3 258, S_0x2801850; + .timescale -9 -12; +P_0x2803e38 .param/l "i" 3 258, +C4<011101>; +S_0x2804250 .scope module, "attempt" "OrNorXor" 3 260, 3 165, S_0x2804120; + .timescale -9 -12; +L_0x2b0dc70/d .functor NOR 1, L_0x2b10090, L_0x2b0ed90, C4<0>, C4<0>; +L_0x2b0dc70 .delay (10000,10000,10000) L_0x2b0dc70/d; +L_0x2b0dd60/d .functor NOT 1, L_0x2b0dc70, C4<0>, C4<0>, C4<0>; +L_0x2b0dd60 .delay (10000,10000,10000) L_0x2b0dd60/d; +L_0x2b0f110/d .functor NAND 1, L_0x2b10090, L_0x2b0ed90, C4<1>, C4<1>; +L_0x2b0f110 .delay (10000,10000,10000) L_0x2b0f110/d; +L_0x2b0f270/d .functor NAND 1, L_0x2b0f110, L_0x2b0dd60, C4<1>, C4<1>; +L_0x2b0f270 .delay (10000,10000,10000) L_0x2b0f270/d; +L_0x2b0f380/d .functor NOT 1, L_0x2b0f270, C4<0>, C4<0>, C4<0>; +L_0x2b0f380 .delay (10000,10000,10000) L_0x2b0f380/d; +v0x2804e00_0 .net "A", 0 0, L_0x2b10090; 1 drivers +v0x2804ea0_0 .net "AnandB", 0 0, L_0x2b0f110; 1 drivers +v0x2804f40_0 .net "AnorB", 0 0, L_0x2b0dc70; 1 drivers +v0x2804ff0_0 .net "AorB", 0 0, L_0x2b0dd60; 1 drivers +v0x28050d0_0 .net "AxorB", 0 0, L_0x2b0f380; 1 drivers +v0x2805180_0 .net "B", 0 0, L_0x2b0ed90; 1 drivers +v0x2805240_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x28052c0_0 .net "OrNorXorOut", 0 0, L_0x2b0fd80; 1 drivers +v0x2805340_0 .net "XorNor", 0 0, L_0x2b0f800; 1 drivers +v0x2805410_0 .net "nXor", 0 0, L_0x2b0f270; 1 drivers +L_0x2b0f980 .part v0x2960210_0, 2, 1; +L_0x2b0ff50 .part v0x2960210_0, 0, 1; +S_0x2804890 .scope module, "mux0" "TwoInMux" 3 184, 3 109, S_0x2804250; + .timescale -9 -12; +L_0x2b0f4e0/d .functor NOT 1, L_0x2b0f980, C4<0>, C4<0>, C4<0>; +L_0x2b0f4e0 .delay (10000,10000,10000) L_0x2b0f4e0/d; +L_0x2b0f5a0/d .functor AND 1, L_0x2b0f380, L_0x2b0f4e0, C4<1>, C4<1>; +L_0x2b0f5a0 .delay (20000,20000,20000) L_0x2b0f5a0/d; +L_0x2b0f6b0/d .functor AND 1, L_0x2b0dc70, L_0x2b0f980, C4<1>, C4<1>; +L_0x2b0f6b0 .delay (20000,20000,20000) L_0x2b0f6b0/d; +L_0x2b0f800/d .functor OR 1, L_0x2b0f5a0, L_0x2b0f6b0, C4<0>, C4<0>; +L_0x2b0f800 .delay (20000,20000,20000) L_0x2b0f800/d; +v0x2804980_0 .net "S", 0 0, L_0x2b0f980; 1 drivers +v0x2804a40_0 .alias "in0", 0 0, v0x28050d0_0; +v0x2804ae0_0 .alias "in1", 0 0, v0x2804f40_0; +v0x2804b80_0 .net "nS", 0 0, L_0x2b0f4e0; 1 drivers +v0x2804c00_0 .net "out0", 0 0, L_0x2b0f5a0; 1 drivers +v0x2804ca0_0 .net "out1", 0 0, L_0x2b0f6b0; 1 drivers +v0x2804d80_0 .alias "outfinal", 0 0, v0x2805340_0; +S_0x2804340 .scope module, "mux1" "TwoInMux" 3 185, 3 109, S_0x2804250; + .timescale -9 -12; +L_0x2b0fa20/d .functor NOT 1, L_0x2b0ff50, C4<0>, C4<0>, C4<0>; +L_0x2b0fa20 .delay (10000,10000,10000) L_0x2b0fa20/d; +L_0x2b0fae0/d .functor AND 1, L_0x2b0f800, L_0x2b0fa20, C4<1>, C4<1>; +L_0x2b0fae0 .delay (20000,20000,20000) L_0x2b0fae0/d; +L_0x2b0fc30/d .functor AND 1, L_0x2b0dd60, L_0x2b0ff50, C4<1>, C4<1>; +L_0x2b0fc30 .delay (20000,20000,20000) L_0x2b0fc30/d; +L_0x2b0fd80/d .functor OR 1, L_0x2b0fae0, L_0x2b0fc30, C4<0>, C4<0>; +L_0x2b0fd80 .delay (20000,20000,20000) L_0x2b0fd80/d; +v0x2804430_0 .net "S", 0 0, L_0x2b0ff50; 1 drivers +v0x28044b0_0 .alias "in0", 0 0, v0x2805340_0; +v0x2804550_0 .alias "in1", 0 0, v0x2804ff0_0; +v0x28045f0_0 .net "nS", 0 0, L_0x2b0fa20; 1 drivers +v0x2804670_0 .net "out0", 0 0, L_0x2b0fae0; 1 drivers +v0x2804710_0 .net "out1", 0 0, L_0x2b0fc30; 1 drivers +v0x28047f0_0 .alias "outfinal", 0 0, v0x28052c0_0; +S_0x2802d50 .scope generate, "orbits[30]" "orbits[30]" 3 258, 3 258, S_0x2801850; + .timescale -9 -12; +P_0x2802ac8 .param/l "i" 3 258, +C4<011110>; +S_0x2802e80 .scope module, "attempt" "OrNorXor" 3 260, 3 165, S_0x2802d50; + .timescale -9 -12; +L_0x2b0ee30/d .functor NOR 1, L_0x2b10130, L_0x2b101d0, C4<0>, C4<0>; +L_0x2b0ee30 .delay (10000,10000,10000) L_0x2b0ee30/d; +L_0x2b0ef20/d .functor NOT 1, L_0x2b0ee30, C4<0>, C4<0>, C4<0>; +L_0x2b0ef20 .delay (10000,10000,10000) L_0x2b0ef20/d; +L_0x2b0efe0/d .functor NAND 1, L_0x2b10130, L_0x2b101d0, C4<1>, C4<1>; +L_0x2b0efe0 .delay (10000,10000,10000) L_0x2b0efe0/d; +L_0x2b10560/d .functor NAND 1, L_0x2b0efe0, L_0x2b0ef20, C4<1>, C4<1>; +L_0x2b10560 .delay (10000,10000,10000) L_0x2b10560/d; +L_0x2b10670/d .functor NOT 1, L_0x2b10560, C4<0>, C4<0>, C4<0>; +L_0x2b10670 .delay (10000,10000,10000) L_0x2b10670/d; +v0x2803a30_0 .net "A", 0 0, L_0x2b10130; 1 drivers +v0x2803ad0_0 .net "AnandB", 0 0, L_0x2b0efe0; 1 drivers +v0x2803b70_0 .net "AnorB", 0 0, L_0x2b0ee30; 1 drivers +v0x2803c20_0 .net "AorB", 0 0, L_0x2b0ef20; 1 drivers +v0x2803d00_0 .net "AxorB", 0 0, L_0x2b10670; 1 drivers +v0x2803db0_0 .net "B", 0 0, L_0x2b101d0; 1 drivers +v0x2803e70_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x2803ef0_0 .net "OrNorXorOut", 0 0, L_0x2b11070; 1 drivers +v0x2803f70_0 .net "XorNor", 0 0, L_0x2b10af0; 1 drivers +v0x2804040_0 .net "nXor", 0 0, L_0x2b10560; 1 drivers +L_0x2b10c70 .part v0x2960210_0, 2, 1; +L_0x2b11240 .part v0x2960210_0, 0, 1; +S_0x28034c0 .scope module, "mux0" "TwoInMux" 3 184, 3 109, S_0x2802e80; + .timescale -9 -12; +L_0x2b107d0/d .functor NOT 1, L_0x2b10c70, C4<0>, C4<0>, C4<0>; +L_0x2b107d0 .delay (10000,10000,10000) L_0x2b107d0/d; +L_0x2b10890/d .functor AND 1, L_0x2b10670, L_0x2b107d0, C4<1>, C4<1>; +L_0x2b10890 .delay (20000,20000,20000) L_0x2b10890/d; +L_0x2b109a0/d .functor AND 1, L_0x2b0ee30, L_0x2b10c70, C4<1>, C4<1>; +L_0x2b109a0 .delay (20000,20000,20000) L_0x2b109a0/d; +L_0x2b10af0/d .functor OR 1, L_0x2b10890, L_0x2b109a0, C4<0>, C4<0>; +L_0x2b10af0 .delay (20000,20000,20000) L_0x2b10af0/d; +v0x28035b0_0 .net "S", 0 0, L_0x2b10c70; 1 drivers +v0x2803670_0 .alias "in0", 0 0, v0x2803d00_0; +v0x2803710_0 .alias "in1", 0 0, v0x2803b70_0; +v0x28037b0_0 .net "nS", 0 0, L_0x2b107d0; 1 drivers +v0x2803830_0 .net "out0", 0 0, L_0x2b10890; 1 drivers +v0x28038d0_0 .net "out1", 0 0, L_0x2b109a0; 1 drivers +v0x28039b0_0 .alias "outfinal", 0 0, v0x2803f70_0; +S_0x2802f70 .scope module, "mux1" "TwoInMux" 3 185, 3 109, S_0x2802e80; + .timescale -9 -12; +L_0x2b10d10/d .functor NOT 1, L_0x2b11240, C4<0>, C4<0>, C4<0>; +L_0x2b10d10 .delay (10000,10000,10000) L_0x2b10d10/d; +L_0x2b10dd0/d .functor AND 1, L_0x2b10af0, L_0x2b10d10, C4<1>, C4<1>; +L_0x2b10dd0 .delay (20000,20000,20000) L_0x2b10dd0/d; +L_0x2b10f20/d .functor AND 1, L_0x2b0ef20, L_0x2b11240, C4<1>, C4<1>; +L_0x2b10f20 .delay (20000,20000,20000) L_0x2b10f20/d; +L_0x2b11070/d .functor OR 1, L_0x2b10dd0, L_0x2b10f20, C4<0>, C4<0>; +L_0x2b11070 .delay (20000,20000,20000) L_0x2b11070/d; +v0x2803060_0 .net "S", 0 0, L_0x2b11240; 1 drivers +v0x28030e0_0 .alias "in0", 0 0, v0x2803f70_0; +v0x2803180_0 .alias "in1", 0 0, v0x2803c20_0; +v0x2803220_0 .net "nS", 0 0, L_0x2b10d10; 1 drivers +v0x28032a0_0 .net "out0", 0 0, L_0x2b10dd0; 1 drivers +v0x2803340_0 .net "out1", 0 0, L_0x2b10f20; 1 drivers +v0x2803420_0 .alias "outfinal", 0 0, v0x2803ef0_0; +S_0x28019a0 .scope generate, "orbits[31]" "orbits[31]" 3 258, 3 258, S_0x2801850; + .timescale -9 -12; +P_0x2801a98 .param/l "i" 3 258, +C4<011111>; +S_0x2801b50 .scope module, "attempt" "OrNorXor" 3 260, 3 165, S_0x28019a0; + .timescale -9 -12; +L_0x2b10270/d .functor NOR 1, L_0x2b12690, L_0x2b11380, C4<0>, C4<0>; +L_0x2b10270 .delay (10000,10000,10000) L_0x2b10270/d; +L_0x2b10360/d .functor NOT 1, L_0x2b10270, C4<0>, C4<0>, C4<0>; +L_0x2b10360 .delay (10000,10000,10000) L_0x2b10360/d; +L_0x2b11710/d .functor NAND 1, L_0x2b12690, L_0x2b11380, C4<1>, C4<1>; +L_0x2b11710 .delay (10000,10000,10000) L_0x2b11710/d; +L_0x2b11870/d .functor NAND 1, L_0x2b11710, L_0x2b10360, C4<1>, C4<1>; +L_0x2b11870 .delay (10000,10000,10000) L_0x2b11870/d; +L_0x2b11980/d .functor NOT 1, L_0x2b11870, C4<0>, C4<0>, C4<0>; +L_0x2b11980 .delay (10000,10000,10000) L_0x2b11980/d; +v0x2802720_0 .net "A", 0 0, L_0x2b12690; 1 drivers +v0x28027c0_0 .net "AnandB", 0 0, L_0x2b11710; 1 drivers +v0x2802860_0 .net "AnorB", 0 0, L_0x2b10270; 1 drivers +v0x28028e0_0 .net "AorB", 0 0, L_0x2b10360; 1 drivers +v0x2802990_0 .net "AxorB", 0 0, L_0x2b11980; 1 drivers +v0x2802a40_0 .net "B", 0 0, L_0x2b11380; 1 drivers +v0x2802b00_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x2802b80_0 .net "OrNorXorOut", 0 0, L_0x2b12380; 1 drivers +v0x2802c00_0 .net "XorNor", 0 0, L_0x2b11e00; 1 drivers +v0x2802cd0_0 .net "nXor", 0 0, L_0x2b11870; 1 drivers +L_0x2b11f80 .part v0x2960210_0, 2, 1; +L_0x2b12550 .part v0x2960210_0, 0, 1; +S_0x28021b0 .scope module, "mux0" "TwoInMux" 3 184, 3 109, S_0x2801b50; + .timescale -9 -12; +L_0x2b11ae0/d .functor NOT 1, L_0x2b11f80, C4<0>, C4<0>, C4<0>; +L_0x2b11ae0 .delay (10000,10000,10000) L_0x2b11ae0/d; +L_0x2b11ba0/d .functor AND 1, L_0x2b11980, L_0x2b11ae0, C4<1>, C4<1>; +L_0x2b11ba0 .delay (20000,20000,20000) L_0x2b11ba0/d; +L_0x2b11cb0/d .functor AND 1, L_0x2b10270, L_0x2b11f80, C4<1>, C4<1>; +L_0x2b11cb0 .delay (20000,20000,20000) L_0x2b11cb0/d; +L_0x2b11e00/d .functor OR 1, L_0x2b11ba0, L_0x2b11cb0, C4<0>, C4<0>; +L_0x2b11e00 .delay (20000,20000,20000) L_0x2b11e00/d; +v0x28022a0_0 .net "S", 0 0, L_0x2b11f80; 1 drivers +v0x2802360_0 .alias "in0", 0 0, v0x2802990_0; +v0x2802400_0 .alias "in1", 0 0, v0x2802860_0; +v0x28024a0_0 .net "nS", 0 0, L_0x2b11ae0; 1 drivers +v0x2802520_0 .net "out0", 0 0, L_0x2b11ba0; 1 drivers +v0x28025c0_0 .net "out1", 0 0, L_0x2b11cb0; 1 drivers +v0x28026a0_0 .alias "outfinal", 0 0, v0x2802c00_0; +S_0x2801c40 .scope module, "mux1" "TwoInMux" 3 185, 3 109, S_0x2801b50; + .timescale -9 -12; +L_0x2b12020/d .functor NOT 1, L_0x2b12550, C4<0>, C4<0>, C4<0>; +L_0x2b12020 .delay (10000,10000,10000) L_0x2b12020/d; +L_0x2b120e0/d .functor AND 1, L_0x2b11e00, L_0x2b12020, C4<1>, C4<1>; +L_0x2b120e0 .delay (20000,20000,20000) L_0x2b120e0/d; +L_0x2b12230/d .functor AND 1, L_0x2b10360, L_0x2b12550, C4<1>, C4<1>; +L_0x2b12230 .delay (20000,20000,20000) L_0x2b12230/d; +L_0x2b12380/d .functor OR 1, L_0x2b120e0, L_0x2b12230, C4<0>, C4<0>; +L_0x2b12380 .delay (20000,20000,20000) L_0x2b12380/d; +v0x2801d30_0 .net "S", 0 0, L_0x2b12550; 1 drivers +v0x2801dd0_0 .alias "in0", 0 0, v0x2802c00_0; +v0x2801e70_0 .alias "in1", 0 0, v0x28028e0_0; +v0x2801f10_0 .net "nS", 0 0, L_0x2b12020; 1 drivers +v0x2801f90_0 .net "out0", 0 0, L_0x2b120e0; 1 drivers +v0x2802030_0 .net "out1", 0 0, L_0x2b12230; 1 drivers +v0x2802110_0 .alias "outfinal", 0 0, v0x2802b80_0; +S_0x2800ed0 .scope module, "ZeroMux0case" "FourInMux" 3 390, 3 125, S_0x25e6a40; + .timescale -9 -12; +L_0x2b12870/d .functor NOT 1, L_0x2a61c30, C4<0>, C4<0>, C4<0>; +L_0x2b12870 .delay (10000,10000,10000) L_0x2b12870/d; +L_0x2b12910/d .functor NOT 1, L_0x2a61d60, C4<0>, C4<0>, C4<0>; +L_0x2b12910 .delay (10000,10000,10000) L_0x2b12910/d; +L_0x2b13cb0/d .functor NAND 1, L_0x2b12870, L_0x2b12910, L_0x2a61e90, C4<1>; +L_0x2b13cb0 .delay (10000,10000,10000) L_0x2b13cb0/d; +L_0x2b13da0/d .functor NAND 1, L_0x2a61c30, L_0x2b12910, L_0x2a61f30, C4<1>; +L_0x2b13da0 .delay (10000,10000,10000) L_0x2b13da0/d; +L_0x2b13e90/d .functor NAND 1, L_0x2b12870, L_0x2a61d60, L_0x2a61fd0, C4<1>; +L_0x2b13e90 .delay (10000,10000,10000) L_0x2b13e90/d; +L_0x2b13f80/d .functor NAND 1, L_0x2a61c30, L_0x2a61d60, L_0x2a620c0, C4<1>; +L_0x2b13f80 .delay (10000,10000,10000) L_0x2b13f80/d; +L_0x2b14060/d .functor NAND 1, L_0x2b13cb0, L_0x2b13da0, L_0x2b13e90, L_0x2b13f80; +L_0x2b14060 .delay (10000,10000,10000) L_0x2b14060/d; +v0x2800fc0_0 .net "S0", 0 0, L_0x2a61c30; 1 drivers +v0x2801080_0 .net "S1", 0 0, L_0x2a61d60; 1 drivers +v0x2801120_0 .net "in0", 0 0, L_0x2a61e90; 1 drivers +v0x28011c0_0 .net "in1", 0 0, L_0x2a61f30; 1 drivers +v0x2801240_0 .net "in2", 0 0, L_0x2a61fd0; 1 drivers +v0x28012e0_0 .net "in3", 0 0, L_0x2a620c0; 1 drivers +v0x2801380_0 .net "nS0", 0 0, L_0x2b12870; 1 drivers +v0x2801420_0 .net "nS1", 0 0, L_0x2b12910; 1 drivers +v0x28014c0_0 .net "out", 0 0, L_0x2b14060; 1 drivers +v0x2801560_0 .net "out0", 0 0, L_0x2b13cb0; 1 drivers +v0x2801600_0 .net "out1", 0 0, L_0x2b13da0; 1 drivers +v0x28016a0_0 .net "out2", 0 0, L_0x2b13e90; 1 drivers +v0x28017b0_0 .net "out3", 0 0, L_0x2b13f80; 1 drivers +S_0x2800510 .scope module, "OneMux0case" "FourInMux" 3 391, 3 125, S_0x25e6a40; + .timescale -9 -12; +L_0x2a621b0/d .functor NOT 1, L_0x2a629f0, C4<0>, C4<0>, C4<0>; +L_0x2a621b0 .delay (10000,10000,10000) L_0x2a621b0/d; +L_0x2a622a0/d .functor NOT 1, L_0x2a62b20, C4<0>, C4<0>, C4<0>; +L_0x2a622a0 .delay (10000,10000,10000) L_0x2a622a0/d; +L_0x2a62340/d .functor NAND 1, L_0x2a621b0, L_0x2a622a0, L_0x2a62c50, C4<1>; +L_0x2a62340 .delay (10000,10000,10000) L_0x2a62340/d; +L_0x2a62480/d .functor NAND 1, L_0x2a629f0, L_0x2a622a0, L_0x2a62cf0, C4<1>; +L_0x2a62480 .delay (10000,10000,10000) L_0x2a62480/d; +L_0x2a62570/d .functor NAND 1, L_0x2a621b0, L_0x2a62b20, L_0x2a62d90, C4<1>; +L_0x2a62570 .delay (10000,10000,10000) L_0x2a62570/d; +L_0x2a62660/d .functor NAND 1, L_0x2a629f0, L_0x2a62b20, L_0x2a62e80, C4<1>; +L_0x2a62660 .delay (10000,10000,10000) L_0x2a62660/d; +L_0x2a62740/d .functor NAND 1, L_0x2a62340, L_0x2a62480, L_0x2a62570, L_0x2a62660; +L_0x2a62740 .delay (10000,10000,10000) L_0x2a62740/d; +v0x2800600_0 .net "S0", 0 0, L_0x2a629f0; 1 drivers +v0x28006c0_0 .net "S1", 0 0, L_0x2a62b20; 1 drivers +v0x2800760_0 .net "in0", 0 0, L_0x2a62c50; 1 drivers +v0x2800800_0 .net "in1", 0 0, L_0x2a62cf0; 1 drivers +v0x2800880_0 .net "in2", 0 0, L_0x2a62d90; 1 drivers +v0x2800920_0 .net "in3", 0 0, L_0x2a62e80; 1 drivers +v0x2800a00_0 .net "nS0", 0 0, L_0x2a621b0; 1 drivers +v0x2800aa0_0 .net "nS1", 0 0, L_0x2a622a0; 1 drivers +v0x2800b40_0 .net "out", 0 0, L_0x2a62740; 1 drivers +v0x2800be0_0 .net "out0", 0 0, L_0x2a62340; 1 drivers +v0x2800c80_0 .net "out1", 0 0, L_0x2a62480; 1 drivers +v0x2800d20_0 .net "out2", 0 0, L_0x2a62570; 1 drivers +v0x2800e30_0 .net "out3", 0 0, L_0x2a62660; 1 drivers +S_0x27fffc0 .scope module, "TwoMux0case" "TwoInMux" 3 392, 3 109, S_0x25e6a40; + .timescale -9 -12; +L_0x2a62f70/d .functor NOT 1, L_0x2a3ade0, C4<0>, C4<0>, C4<0>; +L_0x2a62f70 .delay (10000,10000,10000) L_0x2a62f70/d; +L_0x2b157b0/d .functor AND 1, L_0x2a3ae80, L_0x2a62f70, C4<1>, C4<1>; +L_0x2b157b0 .delay (20000,20000,20000) L_0x2b157b0/d; +L_0x2b158a0/d .functor AND 1, L_0x2a3af70, L_0x2a3ade0, C4<1>, C4<1>; +L_0x2b158a0 .delay (20000,20000,20000) L_0x2b158a0/d; +L_0x2b15990/d .functor OR 1, L_0x2b157b0, L_0x2b158a0, C4<0>, C4<0>; +L_0x2b15990 .delay (20000,20000,20000) L_0x2b15990/d; +v0x28000b0_0 .net "S", 0 0, L_0x2a3ade0; 1 drivers +v0x2800170_0 .net "in0", 0 0, L_0x2a3ae80; 1 drivers +v0x2800210_0 .net "in1", 0 0, L_0x2a3af70; 1 drivers +v0x28002b0_0 .net "nS", 0 0, L_0x2a62f70; 1 drivers +v0x2800330_0 .net "out0", 0 0, L_0x2b157b0; 1 drivers +v0x28003d0_0 .net "out1", 0 0, L_0x2b158a0; 1 drivers +v0x2800470_0 .net "outfinal", 0 0, L_0x2b15990; 1 drivers +S_0x27fe440 .scope generate, "muxbits[1]" "muxbits[1]" 3 397, 3 397, S_0x25e6a40; + .timescale -9 -12; +P_0x27fd438 .param/l "i" 3 397, +C4<01>; +L_0x2a142f0/d .functor OR 1, L_0x2a143f0, L_0x2a141b0, C4<0>, C4<0>; +L_0x2a142f0 .delay (20000,20000,20000) L_0x2a142f0/d; +v0x27ffe60_0 .net *"_s15", 0 0, L_0x2a143f0; 1 drivers +v0x27fff20_0 .net *"_s16", 0 0, L_0x2a141b0; 1 drivers +S_0x27ff4e0 .scope module, "ZeroMux" "FourInMux" 3 399, 3 125, S_0x27fe440; + .timescale -9 -12; +L_0x2a107d0/d .functor NOT 1, L_0x2a123f0, C4<0>, C4<0>, C4<0>; +L_0x2a107d0 .delay (10000,10000,10000) L_0x2a107d0/d; +L_0x2a10870/d .functor NOT 1, L_0x2a12520, C4<0>, C4<0>, C4<0>; +L_0x2a10870 .delay (10000,10000,10000) L_0x2a10870/d; +L_0x2a11bf0/d .functor NAND 1, L_0x2a107d0, L_0x2a10870, L_0x2a12650, C4<1>; +L_0x2a11bf0 .delay (10000,10000,10000) L_0x2a11bf0/d; +L_0x2a11d30/d .functor NAND 1, L_0x2a123f0, L_0x2a10870, L_0x2a126f0, C4<1>; +L_0x2a11d30 .delay (10000,10000,10000) L_0x2a11d30/d; +L_0x2a11e80/d .functor NAND 1, L_0x2a107d0, L_0x2a12520, L_0x2a12790, C4<1>; +L_0x2a11e80 .delay (10000,10000,10000) L_0x2a11e80/d; +L_0x2a11fd0/d .functor NAND 1, L_0x2a123f0, L_0x2a12520, L_0x2a128c0, C4<1>; +L_0x2a11fd0 .delay (10000,10000,10000) L_0x2a11fd0/d; +L_0x2a12140/d .functor NAND 1, L_0x2a11bf0, L_0x2a11d30, L_0x2a11e80, L_0x2a11fd0; +L_0x2a12140 .delay (10000,10000,10000) L_0x2a12140/d; +v0x27ff5d0_0 .net "S0", 0 0, L_0x2a123f0; 1 drivers +v0x27ff690_0 .net "S1", 0 0, L_0x2a12520; 1 drivers +v0x27ff730_0 .net "in0", 0 0, L_0x2a12650; 1 drivers +v0x27ff7d0_0 .net "in1", 0 0, L_0x2a126f0; 1 drivers +v0x27ff850_0 .net "in2", 0 0, L_0x2a12790; 1 drivers +v0x27ff8f0_0 .net "in3", 0 0, L_0x2a128c0; 1 drivers +v0x27ff990_0 .net "nS0", 0 0, L_0x2a107d0; 1 drivers +v0x27ffa30_0 .net "nS1", 0 0, L_0x2a10870; 1 drivers +v0x27ffad0_0 .net "out", 0 0, L_0x2a12140; 1 drivers +v0x27ffb70_0 .net "out0", 0 0, L_0x2a11bf0; 1 drivers +v0x27ffc10_0 .net "out1", 0 0, L_0x2a11d30; 1 drivers +v0x27ffcb0_0 .net "out2", 0 0, L_0x2a11e80; 1 drivers +v0x27ffdc0_0 .net "out3", 0 0, L_0x2a11fd0; 1 drivers +S_0x27feb20 .scope module, "OneMux" "FourInMux" 3 400, 3 125, S_0x27fe440; + .timescale -9 -12; +L_0x2a129b0/d .functor NOT 1, L_0x2a13320, C4<0>, C4<0>, C4<0>; +L_0x2a129b0 .delay (10000,10000,10000) L_0x2a129b0/d; +L_0x2a12aa0/d .functor NOT 1, L_0x2a13450, C4<0>, C4<0>, C4<0>; +L_0x2a12aa0 .delay (10000,10000,10000) L_0x2a12aa0/d; +L_0x2a12b40/d .functor NAND 1, L_0x2a129b0, L_0x2a12aa0, L_0x2a135e0, C4<1>; +L_0x2a12b40 .delay (10000,10000,10000) L_0x2a12b40/d; +L_0x2a12c80/d .functor NAND 1, L_0x2a13320, L_0x2a12aa0, L_0x2a13680, C4<1>; +L_0x2a12c80 .delay (10000,10000,10000) L_0x2a12c80/d; +L_0x2a12d70/d .functor NAND 1, L_0x2a129b0, L_0x2a13450, L_0x2a13790, C4<1>; +L_0x2a12d70 .delay (10000,10000,10000) L_0x2a12d70/d; +L_0x2a12ec0/d .functor NAND 1, L_0x2a13320, L_0x2a13450, L_0x2a13830, C4<1>; +L_0x2a12ec0 .delay (10000,10000,10000) L_0x2a12ec0/d; +L_0x2a12ff0/d .functor NAND 1, L_0x2a12b40, L_0x2a12c80, L_0x2a12d70, L_0x2a12ec0; +L_0x2a12ff0 .delay (10000,10000,10000) L_0x2a12ff0/d; +v0x27fec10_0 .net "S0", 0 0, L_0x2a13320; 1 drivers +v0x27fecd0_0 .net "S1", 0 0, L_0x2a13450; 1 drivers +v0x27fed70_0 .net "in0", 0 0, L_0x2a135e0; 1 drivers +v0x27fee10_0 .net "in1", 0 0, L_0x2a13680; 1 drivers +v0x27fee90_0 .net "in2", 0 0, L_0x2a13790; 1 drivers +v0x27fef30_0 .net "in3", 0 0, L_0x2a13830; 1 drivers +v0x27ff010_0 .net "nS0", 0 0, L_0x2a129b0; 1 drivers +v0x27ff0b0_0 .net "nS1", 0 0, L_0x2a12aa0; 1 drivers +v0x27ff150_0 .net "out", 0 0, L_0x2a12ff0; 1 drivers +v0x27ff1f0_0 .net "out0", 0 0, L_0x2a12b40; 1 drivers +v0x27ff290_0 .net "out1", 0 0, L_0x2a12c80; 1 drivers +v0x27ff330_0 .net "out2", 0 0, L_0x2a12d70; 1 drivers +v0x27ff440_0 .net "out3", 0 0, L_0x2a12ec0; 1 drivers +S_0x27fe5b0 .scope module, "TwoMux" "TwoInMux" 3 401, 3 109, S_0x27fe440; + .timescale -9 -12; +L_0x2a13580/d .functor NOT 1, L_0x2a13e00, C4<0>, C4<0>, C4<0>; +L_0x2a13580 .delay (10000,10000,10000) L_0x2a13580/d; +L_0x2a139f0/d .functor AND 1, L_0x2a13f30, L_0x2a13580, C4<1>, C4<1>; +L_0x2a139f0 .delay (20000,20000,20000) L_0x2a139f0/d; +L_0x2a13ae0/d .functor AND 1, L_0x2a14070, L_0x2a13e00, C4<1>, C4<1>; +L_0x2a13ae0 .delay (20000,20000,20000) L_0x2a13ae0/d; +L_0x2a13bd0/d .functor OR 1, L_0x2a139f0, L_0x2a13ae0, C4<0>, C4<0>; +L_0x2a13bd0 .delay (20000,20000,20000) L_0x2a13bd0/d; +v0x27fe6a0_0 .net "S", 0 0, L_0x2a13e00; 1 drivers +v0x27fe740_0 .net "in0", 0 0, L_0x2a13f30; 1 drivers +v0x27fe7e0_0 .net "in1", 0 0, L_0x2a14070; 1 drivers +v0x27fe880_0 .net "nS", 0 0, L_0x2a13580; 1 drivers +v0x27fe900_0 .net "out0", 0 0, L_0x2a139f0; 1 drivers +v0x27fe9a0_0 .net "out1", 0 0, L_0x2a13ae0; 1 drivers +v0x27fea80_0 .net "outfinal", 0 0, L_0x2a13bd0; 1 drivers +S_0x27fc8c0 .scope generate, "muxbits[2]" "muxbits[2]" 3 397, 3 397, S_0x25e6a40; + .timescale -9 -12; +P_0x27fb8b8 .param/l "i" 3 397, +C4<010>; +L_0x2a162d0/d .functor OR 1, L_0x2a16ad0, L_0x2a16e50, C4<0>, C4<0>; +L_0x2a162d0 .delay (20000,20000,20000) L_0x2a162d0/d; +v0x27fe2e0_0 .net *"_s15", 0 0, L_0x2a16ad0; 1 drivers +v0x27fe3a0_0 .net *"_s16", 0 0, L_0x2a16e50; 1 drivers +S_0x27fd960 .scope module, "ZeroMux" "FourInMux" 3 399, 3 125, S_0x27fc8c0; + .timescale -9 -12; +L_0x2a14590/d .functor NOT 1, L_0x2a14490, C4<0>, C4<0>, C4<0>; +L_0x2a14590 .delay (10000,10000,10000) L_0x2a14590/d; +L_0x2a14680/d .functor NOT 1, L_0x2a14f80, C4<0>, C4<0>, C4<0>; +L_0x2a14680 .delay (10000,10000,10000) L_0x2a14680/d; +L_0x2a14720/d .functor NAND 1, L_0x2a14590, L_0x2a14680, L_0x2a14e30, C4<1>; +L_0x2a14720 .delay (10000,10000,10000) L_0x2a14720/d; +L_0x2a14860/d .functor NAND 1, L_0x2a14490, L_0x2a14680, L_0x2a15180, C4<1>; +L_0x2a14860 .delay (10000,10000,10000) L_0x2a14860/d; +L_0x2a14950/d .functor NAND 1, L_0x2a14590, L_0x2a14f80, L_0x2a150b0, C4<1>; +L_0x2a14950 .delay (10000,10000,10000) L_0x2a14950/d; +L_0x2a14a40/d .functor NAND 1, L_0x2a14490, L_0x2a14f80, L_0x2a15350, C4<1>; +L_0x2a14a40 .delay (10000,10000,10000) L_0x2a14a40/d; +L_0x2a14b80/d .functor NAND 1, L_0x2a14720, L_0x2a14860, L_0x2a14950, L_0x2a14a40; +L_0x2a14b80 .delay (10000,10000,10000) L_0x2a14b80/d; +v0x27fda50_0 .net "S0", 0 0, L_0x2a14490; 1 drivers +v0x27fdb10_0 .net "S1", 0 0, L_0x2a14f80; 1 drivers +v0x27fdbb0_0 .net "in0", 0 0, L_0x2a14e30; 1 drivers +v0x27fdc50_0 .net "in1", 0 0, L_0x2a15180; 1 drivers +v0x27fdcd0_0 .net "in2", 0 0, L_0x2a150b0; 1 drivers +v0x27fdd70_0 .net "in3", 0 0, L_0x2a15350; 1 drivers +v0x27fde10_0 .net "nS0", 0 0, L_0x2a14590; 1 drivers +v0x27fdeb0_0 .net "nS1", 0 0, L_0x2a14680; 1 drivers +v0x27fdf50_0 .net "out", 0 0, L_0x2a14b80; 1 drivers +v0x27fdff0_0 .net "out0", 0 0, L_0x2a14720; 1 drivers +v0x27fe090_0 .net "out1", 0 0, L_0x2a14860; 1 drivers +v0x27fe130_0 .net "out2", 0 0, L_0x2a14950; 1 drivers +v0x27fe240_0 .net "out3", 0 0, L_0x2a14a40; 1 drivers +S_0x27fcfa0 .scope module, "OneMux" "FourInMux" 3 400, 3 125, S_0x27fc8c0; + .timescale -9 -12; +L_0x2a15220/d .functor NOT 1, L_0x2a15d20, C4<0>, C4<0>, C4<0>; +L_0x2a15220 .delay (10000,10000,10000) L_0x2a15220/d; +L_0x2a15580/d .functor NOT 1, L_0x2a15440, C4<0>, C4<0>, C4<0>; +L_0x2a15580 .delay (10000,10000,10000) L_0x2a15580/d; +L_0x2a155e0/d .functor NAND 1, L_0x2a15220, L_0x2a15580, L_0x2a15fe0, C4<1>; +L_0x2a155e0 .delay (10000,10000,10000) L_0x2a155e0/d; +L_0x2a15720/d .functor NAND 1, L_0x2a15d20, L_0x2a15580, L_0x2a15e50, C4<1>; +L_0x2a15720 .delay (10000,10000,10000) L_0x2a15720/d; +L_0x2a15810/d .functor NAND 1, L_0x2a15220, L_0x2a15440, L_0x2a16190, C4<1>; +L_0x2a15810 .delay (10000,10000,10000) L_0x2a15810/d; +L_0x2a15900/d .functor NAND 1, L_0x2a15d20, L_0x2a15440, L_0x2a16080, C4<1>; +L_0x2a15900 .delay (10000,10000,10000) L_0x2a15900/d; +L_0x2a15a70/d .functor NAND 1, L_0x2a155e0, L_0x2a15720, L_0x2a15810, L_0x2a15900; +L_0x2a15a70 .delay (10000,10000,10000) L_0x2a15a70/d; +v0x27fd090_0 .net "S0", 0 0, L_0x2a15d20; 1 drivers +v0x27fd150_0 .net "S1", 0 0, L_0x2a15440; 1 drivers +v0x27fd1f0_0 .net "in0", 0 0, L_0x2a15fe0; 1 drivers +v0x27fd290_0 .net "in1", 0 0, L_0x2a15e50; 1 drivers +v0x27fd310_0 .net "in2", 0 0, L_0x2a16190; 1 drivers +v0x27fd3b0_0 .net "in3", 0 0, L_0x2a16080; 1 drivers +v0x27fd490_0 .net "nS0", 0 0, L_0x2a15220; 1 drivers +v0x27fd530_0 .net "nS1", 0 0, L_0x2a15580; 1 drivers +v0x27fd5d0_0 .net "out", 0 0, L_0x2a15a70; 1 drivers +v0x27fd670_0 .net "out0", 0 0, L_0x2a155e0; 1 drivers +v0x27fd710_0 .net "out1", 0 0, L_0x2a15720; 1 drivers +v0x27fd7b0_0 .net "out2", 0 0, L_0x2a15810; 1 drivers +v0x27fd8c0_0 .net "out3", 0 0, L_0x2a15900; 1 drivers +S_0x27fca30 .scope module, "TwoMux" "TwoInMux" 3 401, 3 109, S_0x27fc8c0; + .timescale -9 -12; +L_0x2a16120/d .functor NOT 1, L_0x2a16230, C4<0>, C4<0>, C4<0>; +L_0x2a16120 .delay (10000,10000,10000) L_0x2a16120/d; +L_0x2a163e0/d .functor AND 1, L_0x2a16960, L_0x2a16120, C4<1>, C4<1>; +L_0x2a163e0 .delay (20000,20000,20000) L_0x2a163e0/d; +L_0x2a164d0/d .functor AND 1, L_0x2a16830, L_0x2a16230, C4<1>, C4<1>; +L_0x2a164d0 .delay (20000,20000,20000) L_0x2a164d0/d; +L_0x2a165c0/d .functor OR 1, L_0x2a163e0, L_0x2a164d0, C4<0>, C4<0>; +L_0x2a165c0 .delay (20000,20000,20000) L_0x2a165c0/d; +v0x27fcb20_0 .net "S", 0 0, L_0x2a16230; 1 drivers +v0x27fcbc0_0 .net "in0", 0 0, L_0x2a16960; 1 drivers +v0x27fcc60_0 .net "in1", 0 0, L_0x2a16830; 1 drivers +v0x27fcd00_0 .net "nS", 0 0, L_0x2a16120; 1 drivers +v0x27fcd80_0 .net "out0", 0 0, L_0x2a163e0; 1 drivers +v0x27fce20_0 .net "out1", 0 0, L_0x2a164d0; 1 drivers +v0x27fcf00_0 .net "outfinal", 0 0, L_0x2a165c0; 1 drivers +S_0x27fad40 .scope generate, "muxbits[3]" "muxbits[3]" 3 397, 3 397, S_0x25e6a40; + .timescale -9 -12; +P_0x27f9d38 .param/l "i" 3 397, +C4<011>; +L_0x2a19200/d .functor OR 1, L_0x2a19580, L_0x2a19390, C4<0>, C4<0>; +L_0x2a19200 .delay (20000,20000,20000) L_0x2a19200/d; +v0x27fc760_0 .net *"_s15", 0 0, L_0x2a19580; 1 drivers +v0x27fc820_0 .net *"_s16", 0 0, L_0x2a19390; 1 drivers +S_0x27fbde0 .scope module, "ZeroMux" "FourInMux" 3 399, 3 125, S_0x27fad40; + .timescale -9 -12; +L_0x2a13720/d .functor NOT 1, L_0x2a17750, C4<0>, C4<0>, C4<0>; +L_0x2a13720 .delay (10000,10000,10000) L_0x2a13720/d; +L_0x2a16d50/d .functor NOT 1, L_0x2a16ef0, C4<0>, C4<0>, C4<0>; +L_0x2a16d50 .delay (10000,10000,10000) L_0x2a16d50/d; +L_0x2a16db0/d .functor NAND 1, L_0x2a13720, L_0x2a16d50, L_0x2a179f0, C4<1>; +L_0x2a16db0 .delay (10000,10000,10000) L_0x2a16db0/d; +L_0x2a170f0/d .functor NAND 1, L_0x2a17750, L_0x2a16d50, L_0x2a17880, C4<1>; +L_0x2a170f0 .delay (10000,10000,10000) L_0x2a170f0/d; +L_0x2a171e0/d .functor NAND 1, L_0x2a13720, L_0x2a16ef0, L_0x2a17920, C4<1>; +L_0x2a171e0 .delay (10000,10000,10000) L_0x2a171e0/d; +L_0x2a17330/d .functor NAND 1, L_0x2a17750, L_0x2a16ef0, L_0x2a17a90, C4<1>; +L_0x2a17330 .delay (10000,10000,10000) L_0x2a17330/d; +L_0x2a174a0/d .functor NAND 1, L_0x2a16db0, L_0x2a170f0, L_0x2a171e0, L_0x2a17330; +L_0x2a174a0 .delay (10000,10000,10000) L_0x2a174a0/d; +v0x27fbed0_0 .net "S0", 0 0, L_0x2a17750; 1 drivers +v0x27fbf90_0 .net "S1", 0 0, L_0x2a16ef0; 1 drivers +v0x27fc030_0 .net "in0", 0 0, L_0x2a179f0; 1 drivers +v0x27fc0d0_0 .net "in1", 0 0, L_0x2a17880; 1 drivers +v0x27fc150_0 .net "in2", 0 0, L_0x2a17920; 1 drivers +v0x27fc1f0_0 .net "in3", 0 0, L_0x2a17a90; 1 drivers +v0x27fc290_0 .net "nS0", 0 0, L_0x2a13720; 1 drivers +v0x27fc330_0 .net "nS1", 0 0, L_0x2a16d50; 1 drivers +v0x27fc3d0_0 .net "out", 0 0, L_0x2a174a0; 1 drivers +v0x27fc470_0 .net "out0", 0 0, L_0x2a16db0; 1 drivers +v0x27fc510_0 .net "out1", 0 0, L_0x2a170f0; 1 drivers +v0x27fc5b0_0 .net "out2", 0 0, L_0x2a171e0; 1 drivers +v0x27fc6c0_0 .net "out3", 0 0, L_0x2a17330; 1 drivers +S_0x27fb420 .scope module, "OneMux" "FourInMux" 3 400, 3 125, S_0x27fad40; + .timescale -9 -12; +L_0x2a17b80/d .functor NOT 1, L_0x2a17c60, C4<0>, C4<0>, C4<0>; +L_0x2a17b80 .delay (10000,10000,10000) L_0x2a17b80/d; +L_0x2a17e80/d .functor NOT 1, L_0x2a187a0, C4<0>, C4<0>, C4<0>; +L_0x2a17e80 .delay (10000,10000,10000) L_0x2a17e80/d; +L_0x2a17f20/d .functor NAND 1, L_0x2a17b80, L_0x2a17e80, L_0x2a18600, C4<1>; +L_0x2a17f20 .delay (10000,10000,10000) L_0x2a17f20/d; +L_0x2a18060/d .functor NAND 1, L_0x2a17c60, L_0x2a17e80, L_0x2a186a0, C4<1>; +L_0x2a18060 .delay (10000,10000,10000) L_0x2a18060/d; +L_0x2a18150/d .functor NAND 1, L_0x2a17b80, L_0x2a187a0, L_0x2a18a90, C4<1>; +L_0x2a18150 .delay (10000,10000,10000) L_0x2a18150/d; +L_0x2a18240/d .functor NAND 1, L_0x2a17c60, L_0x2a187a0, L_0x2a18b30, C4<1>; +L_0x2a18240 .delay (10000,10000,10000) L_0x2a18240/d; +L_0x2a18350/d .functor NAND 1, L_0x2a17f20, L_0x2a18060, L_0x2a18150, L_0x2a18240; +L_0x2a18350 .delay (10000,10000,10000) L_0x2a18350/d; +v0x27fb510_0 .net "S0", 0 0, L_0x2a17c60; 1 drivers +v0x27fb5d0_0 .net "S1", 0 0, L_0x2a187a0; 1 drivers +v0x27fb670_0 .net "in0", 0 0, L_0x2a18600; 1 drivers +v0x27fb710_0 .net "in1", 0 0, L_0x2a186a0; 1 drivers +v0x27fb790_0 .net "in2", 0 0, L_0x2a18a90; 1 drivers +v0x27fb830_0 .net "in3", 0 0, L_0x2a18b30; 1 drivers +v0x27fb910_0 .net "nS0", 0 0, L_0x2a17b80; 1 drivers +v0x27fb9b0_0 .net "nS1", 0 0, L_0x2a17e80; 1 drivers +v0x27fba50_0 .net "out", 0 0, L_0x2a18350; 1 drivers +v0x27fbaf0_0 .net "out0", 0 0, L_0x2a17f20; 1 drivers +v0x27fbb90_0 .net "out1", 0 0, L_0x2a18060; 1 drivers +v0x27fbc30_0 .net "out2", 0 0, L_0x2a18150; 1 drivers +v0x27fbd40_0 .net "out3", 0 0, L_0x2a18240; 1 drivers +S_0x27faeb0 .scope module, "TwoMux" "TwoInMux" 3 401, 3 109, S_0x27fad40; + .timescale -9 -12; +L_0x2a188d0/d .functor NOT 1, L_0x2a190c0, C4<0>, C4<0>, C4<0>; +L_0x2a188d0 .delay (10000,10000,10000) L_0x2a188d0/d; +L_0x2a189c0/d .functor AND 1, L_0x2a18bd0, L_0x2a188d0, C4<1>, C4<1>; +L_0x2a189c0 .delay (20000,20000,20000) L_0x2a189c0/d; +L_0x2a18df0/d .functor AND 1, L_0x2a18cc0, L_0x2a190c0, C4<1>, C4<1>; +L_0x2a18df0 .delay (20000,20000,20000) L_0x2a18df0/d; +L_0x2a18ee0/d .functor OR 1, L_0x2a189c0, L_0x2a18df0, C4<0>, C4<0>; +L_0x2a18ee0 .delay (20000,20000,20000) L_0x2a18ee0/d; +v0x27fafa0_0 .net "S", 0 0, L_0x2a190c0; 1 drivers +v0x27fb040_0 .net "in0", 0 0, L_0x2a18bd0; 1 drivers +v0x27fb0e0_0 .net "in1", 0 0, L_0x2a18cc0; 1 drivers +v0x27fb180_0 .net "nS", 0 0, L_0x2a188d0; 1 drivers +v0x27fb200_0 .net "out0", 0 0, L_0x2a189c0; 1 drivers +v0x27fb2a0_0 .net "out1", 0 0, L_0x2a18df0; 1 drivers +v0x27fb380_0 .net "outfinal", 0 0, L_0x2a18ee0; 1 drivers +S_0x27f91c0 .scope generate, "muxbits[4]" "muxbits[4]" 3 397, 3 397, S_0x25e6a40; + .timescale -9 -12; +P_0x27f81b8 .param/l "i" 3 397, +C4<0100>; +L_0x2a16a00/d .functor OR 1, L_0x2a1bc10, L_0x2a1bdf0, C4<0>, C4<0>; +L_0x2a16a00 .delay (20000,20000,20000) L_0x2a16a00/d; +v0x27fabe0_0 .net *"_s15", 0 0, L_0x2a1bc10; 1 drivers +v0x27faca0_0 .net *"_s16", 0 0, L_0x2a1bdf0; 1 drivers +S_0x27fa260 .scope module, "ZeroMux" "FourInMux" 3 399, 3 125, S_0x27f91c0; + .timescale -9 -12; +L_0x2a19480/d .functor NOT 1, L_0x2a19620, C4<0>, C4<0>, C4<0>; +L_0x2a19480 .delay (10000,10000,10000) L_0x2a19480/d; +L_0x2a19820/d .functor NOT 1, L_0x2a19750, C4<0>, C4<0>, C4<0>; +L_0x2a19820 .delay (10000,10000,10000) L_0x2a19820/d; +L_0x2a19880/d .functor NAND 1, L_0x2a19480, L_0x2a19820, L_0x2a19ff0, C4<1>; +L_0x2a19880 .delay (10000,10000,10000) L_0x2a19880/d; +L_0x2a199c0/d .functor NAND 1, L_0x2a19620, L_0x2a19820, L_0x2a1a090, C4<1>; +L_0x2a199c0 .delay (10000,10000,10000) L_0x2a199c0/d; +L_0x2a19ab0/d .functor NAND 1, L_0x2a19480, L_0x2a19750, L_0x2a1a130, C4<1>; +L_0x2a19ab0 .delay (10000,10000,10000) L_0x2a19ab0/d; +L_0x2a19bd0/d .functor NAND 1, L_0x2a19620, L_0x2a19750, L_0x2a1a510, C4<1>; +L_0x2a19bd0 .delay (10000,10000,10000) L_0x2a19bd0/d; +L_0x2a19d40/d .functor NAND 1, L_0x2a19880, L_0x2a199c0, L_0x2a19ab0, L_0x2a19bd0; +L_0x2a19d40 .delay (10000,10000,10000) L_0x2a19d40/d; +v0x27fa350_0 .net "S0", 0 0, L_0x2a19620; 1 drivers +v0x27fa410_0 .net "S1", 0 0, L_0x2a19750; 1 drivers +v0x27fa4b0_0 .net "in0", 0 0, L_0x2a19ff0; 1 drivers +v0x27fa550_0 .net "in1", 0 0, L_0x2a1a090; 1 drivers +v0x27fa5d0_0 .net "in2", 0 0, L_0x2a1a130; 1 drivers +v0x27fa670_0 .net "in3", 0 0, L_0x2a1a510; 1 drivers +v0x27fa710_0 .net "nS0", 0 0, L_0x2a19480; 1 drivers +v0x27fa7b0_0 .net "nS1", 0 0, L_0x2a19820; 1 drivers +v0x27fa850_0 .net "out", 0 0, L_0x2a19d40; 1 drivers +v0x27fa8f0_0 .net "out0", 0 0, L_0x2a19880; 1 drivers +v0x27fa990_0 .net "out1", 0 0, L_0x2a199c0; 1 drivers +v0x27faa30_0 .net "out2", 0 0, L_0x2a19ab0; 1 drivers +v0x27fab40_0 .net "out3", 0 0, L_0x2a19bd0; 1 drivers +S_0x27f98a0 .scope module, "OneMux" "FourInMux" 3 400, 3 125, S_0x27f91c0; + .timescale -9 -12; +L_0x2a1a290/d .functor NOT 1, L_0x2a1aeb0, C4<0>, C4<0>, C4<0>; +L_0x2a1a290 .delay (10000,10000,10000) L_0x2a1a290/d; +L_0x2a1a380/d .functor NOT 1, L_0x2a1a600, C4<0>, C4<0>, C4<0>; +L_0x2a1a380 .delay (10000,10000,10000) L_0x2a1a380/d; +L_0x2a1a420/d .functor NAND 1, L_0x2a1a290, L_0x2a1a380, L_0x2a1a730, C4<1>; +L_0x2a1a420 .delay (10000,10000,10000) L_0x2a1a420/d; +L_0x2a1a8e0/d .functor NAND 1, L_0x2a1aeb0, L_0x2a1a380, L_0x2a1b240, C4<1>; +L_0x2a1a8e0 .delay (10000,10000,10000) L_0x2a1a8e0/d; +L_0x2a1a9d0/d .functor NAND 1, L_0x2a1a290, L_0x2a1a600, L_0x2a1b2e0, C4<1>; +L_0x2a1a9d0 .delay (10000,10000,10000) L_0x2a1a9d0/d; +L_0x2a1aac0/d .functor NAND 1, L_0x2a1aeb0, L_0x2a1a600, L_0x2a1afe0, C4<1>; +L_0x2a1aac0 .delay (10000,10000,10000) L_0x2a1aac0/d; +L_0x2a1ac00/d .functor NAND 1, L_0x2a1a420, L_0x2a1a8e0, L_0x2a1a9d0, L_0x2a1aac0; +L_0x2a1ac00 .delay (10000,10000,10000) L_0x2a1ac00/d; +v0x27f9990_0 .net "S0", 0 0, L_0x2a1aeb0; 1 drivers +v0x27f9a50_0 .net "S1", 0 0, L_0x2a1a600; 1 drivers +v0x27f9af0_0 .net "in0", 0 0, L_0x2a1a730; 1 drivers +v0x27f9b90_0 .net "in1", 0 0, L_0x2a1b240; 1 drivers +v0x27f9c10_0 .net "in2", 0 0, L_0x2a1b2e0; 1 drivers +v0x27f9cb0_0 .net "in3", 0 0, L_0x2a1afe0; 1 drivers +v0x27f9d90_0 .net "nS0", 0 0, L_0x2a1a290; 1 drivers +v0x27f9e30_0 .net "nS1", 0 0, L_0x2a1a380; 1 drivers +v0x27f9ed0_0 .net "out", 0 0, L_0x2a1ac00; 1 drivers +v0x27f9f70_0 .net "out0", 0 0, L_0x2a1a420; 1 drivers +v0x27fa010_0 .net "out1", 0 0, L_0x2a1a8e0; 1 drivers +v0x27fa0b0_0 .net "out2", 0 0, L_0x2a1a9d0; 1 drivers +v0x27fa1c0_0 .net "out3", 0 0, L_0x2a1aac0; 1 drivers +S_0x27f9330 .scope module, "TwoMux" "TwoInMux" 3 401, 3 109, S_0x27f91c0; + .timescale -9 -12; +L_0x2a1b0d0/d .functor NOT 1, L_0x2a1b380, C4<0>, C4<0>, C4<0>; +L_0x2a1b0d0 .delay (10000,10000,10000) L_0x2a1b0d0/d; +L_0x2a1b1c0/d .functor AND 1, L_0x2a1b420, L_0x2a1b0d0, C4<1>, C4<1>; +L_0x2a1b1c0 .delay (20000,20000,20000) L_0x2a1b1c0/d; +L_0x2a1b680/d .functor AND 1, L_0x2a1b510, L_0x2a1b380, C4<1>, C4<1>; +L_0x2a1b680 .delay (20000,20000,20000) L_0x2a1b680/d; +L_0x2a1b770/d .functor OR 1, L_0x2a1b1c0, L_0x2a1b680, C4<0>, C4<0>; +L_0x2a1b770 .delay (20000,20000,20000) L_0x2a1b770/d; +v0x27f9420_0 .net "S", 0 0, L_0x2a1b380; 1 drivers +v0x27f94c0_0 .net "in0", 0 0, L_0x2a1b420; 1 drivers +v0x27f9560_0 .net "in1", 0 0, L_0x2a1b510; 1 drivers +v0x27f9600_0 .net "nS", 0 0, L_0x2a1b0d0; 1 drivers +v0x27f9680_0 .net "out0", 0 0, L_0x2a1b1c0; 1 drivers +v0x27f9720_0 .net "out1", 0 0, L_0x2a1b680; 1 drivers +v0x27f9800_0 .net "outfinal", 0 0, L_0x2a1b770; 1 drivers +S_0x27f7640 .scope generate, "muxbits[5]" "muxbits[5]" 3 397, 3 397, S_0x25e6a40; + .timescale -9 -12; +P_0x27f6638 .param/l "i" 3 397, +C4<0101>; +L_0x2a1e020/d .functor OR 1, L_0x2a1e8a0, L_0x2a1e4c0, C4<0>, C4<0>; +L_0x2a1e020 .delay (20000,20000,20000) L_0x2a1e020/d; +v0x27f9060_0 .net *"_s15", 0 0, L_0x2a1e8a0; 1 drivers +v0x27f9120_0 .net *"_s16", 0 0, L_0x2a1e4c0; 1 drivers +S_0x27f86e0 .scope module, "ZeroMux" "FourInMux" 3 399, 3 125, S_0x27f7640; + .timescale -9 -12; +L_0x2a1bee0/d .functor NOT 1, L_0x2a1cab0, C4<0>, C4<0>, C4<0>; +L_0x2a1bee0 .delay (10000,10000,10000) L_0x2a1bee0/d; +L_0x2a1bf90/d .functor NOT 1, L_0x2a1c190, C4<0>, C4<0>, C4<0>; +L_0x2a1bf90 .delay (10000,10000,10000) L_0x2a1bf90/d; +L_0x2a1bff0/d .functor NAND 1, L_0x2a1bee0, L_0x2a1bf90, L_0x2a1c2c0, C4<1>; +L_0x2a1bff0 .delay (10000,10000,10000) L_0x2a1bff0/d; +L_0x2a1c4e0/d .functor NAND 1, L_0x2a1cab0, L_0x2a1bf90, L_0x2a1c360, C4<1>; +L_0x2a1c4e0 .delay (10000,10000,10000) L_0x2a1c4e0/d; +L_0x2a1c5d0/d .functor NAND 1, L_0x2a1bee0, L_0x2a1c190, L_0x2a1ceb0, C4<1>; +L_0x2a1c5d0 .delay (10000,10000,10000) L_0x2a1c5d0/d; +L_0x2a1c6c0/d .functor NAND 1, L_0x2a1cab0, L_0x2a1c190, L_0x2a1cbe0, C4<1>; +L_0x2a1c6c0 .delay (10000,10000,10000) L_0x2a1c6c0/d; +L_0x2a1c800/d .functor NAND 1, L_0x2a1bff0, L_0x2a1c4e0, L_0x2a1c5d0, L_0x2a1c6c0; +L_0x2a1c800 .delay (10000,10000,10000) L_0x2a1c800/d; +v0x27f87d0_0 .net "S0", 0 0, L_0x2a1cab0; 1 drivers +v0x27f8890_0 .net "S1", 0 0, L_0x2a1c190; 1 drivers +v0x27f8930_0 .net "in0", 0 0, L_0x2a1c2c0; 1 drivers +v0x27f89d0_0 .net "in1", 0 0, L_0x2a1c360; 1 drivers +v0x27f8a50_0 .net "in2", 0 0, L_0x2a1ceb0; 1 drivers +v0x27f8af0_0 .net "in3", 0 0, L_0x2a1cbe0; 1 drivers +v0x27f8b90_0 .net "nS0", 0 0, L_0x2a1bee0; 1 drivers +v0x27f8c30_0 .net "nS1", 0 0, L_0x2a1bf90; 1 drivers +v0x27f8cd0_0 .net "out", 0 0, L_0x2a1c800; 1 drivers +v0x27f8d70_0 .net "out0", 0 0, L_0x2a1bff0; 1 drivers +v0x27f8e10_0 .net "out1", 0 0, L_0x2a1c4e0; 1 drivers +v0x27f8eb0_0 .net "out2", 0 0, L_0x2a1c5d0; 1 drivers +v0x27f8fc0_0 .net "out3", 0 0, L_0x2a1c6c0; 1 drivers +S_0x27f7d20 .scope module, "OneMux" "FourInMux" 3 400, 3 125, S_0x27f7640; + .timescale -9 -12; +L_0x2a1ccd0/d .functor NOT 1, L_0x2a1cfa0, C4<0>, C4<0>, C4<0>; +L_0x2a1ccd0 .delay (10000,10000,10000) L_0x2a1ccd0/d; +L_0x2a1cd80/d .functor NOT 1, L_0x2a1d0d0, C4<0>, C4<0>, C4<0>; +L_0x2a1cd80 .delay (10000,10000,10000) L_0x2a1cd80/d; +L_0x2a1ce20/d .functor NAND 1, L_0x2a1ccd0, L_0x2a1cd80, L_0x2a1dc60, C4<1>; +L_0x2a1ce20 .delay (10000,10000,10000) L_0x2a1ce20/d; +L_0x2a1d360/d .functor NAND 1, L_0x2a1cfa0, L_0x2a1cd80, L_0x2a1dd00, C4<1>; +L_0x2a1d360 .delay (10000,10000,10000) L_0x2a1d360/d; +L_0x2a1d450/d .functor NAND 1, L_0x2a1ccd0, L_0x2a1d0d0, L_0x2a1d960, C4<1>; +L_0x2a1d450 .delay (10000,10000,10000) L_0x2a1d450/d; +L_0x2a1d540/d .functor NAND 1, L_0x2a1cfa0, L_0x2a1d0d0, L_0x2a1da50, C4<1>; +L_0x2a1d540 .delay (10000,10000,10000) L_0x2a1d540/d; +L_0x2a1d6b0/d .functor NAND 1, L_0x2a1ce20, L_0x2a1d360, L_0x2a1d450, L_0x2a1d540; +L_0x2a1d6b0 .delay (10000,10000,10000) L_0x2a1d6b0/d; +v0x27f7e10_0 .net "S0", 0 0, L_0x2a1cfa0; 1 drivers +v0x27f7ed0_0 .net "S1", 0 0, L_0x2a1d0d0; 1 drivers +v0x27f7f70_0 .net "in0", 0 0, L_0x2a1dc60; 1 drivers +v0x27f8010_0 .net "in1", 0 0, L_0x2a1dd00; 1 drivers +v0x27f8090_0 .net "in2", 0 0, L_0x2a1d960; 1 drivers +v0x27f8130_0 .net "in3", 0 0, L_0x2a1da50; 1 drivers +v0x27f8210_0 .net "nS0", 0 0, L_0x2a1ccd0; 1 drivers +v0x27f82b0_0 .net "nS1", 0 0, L_0x2a1cd80; 1 drivers +v0x27f8350_0 .net "out", 0 0, L_0x2a1d6b0; 1 drivers +v0x27f83f0_0 .net "out0", 0 0, L_0x2a1ce20; 1 drivers +v0x27f8490_0 .net "out1", 0 0, L_0x2a1d360; 1 drivers +v0x27f8530_0 .net "out2", 0 0, L_0x2a1d450; 1 drivers +v0x27f8640_0 .net "out3", 0 0, L_0x2a1d540; 1 drivers +S_0x27f77b0 .scope module, "TwoMux" "TwoInMux" 3 401, 3 109, S_0x27f7640; + .timescale -9 -12; +L_0x2a1db40/d .functor NOT 1, L_0x2a1e420, C4<0>, C4<0>, C4<0>; +L_0x2a1db40 .delay (10000,10000,10000) L_0x2a1db40/d; +L_0x2a1d200/d .functor AND 1, L_0x2a1dda0, L_0x2a1db40, C4<1>, C4<1>; +L_0x2a1d200 .delay (20000,20000,20000) L_0x2a1d200/d; +L_0x2a1e150/d .functor AND 1, L_0x2a1de90, L_0x2a1e420, C4<1>, C4<1>; +L_0x2a1e150 .delay (20000,20000,20000) L_0x2a1e150/d; +L_0x2a1e240/d .functor OR 1, L_0x2a1d200, L_0x2a1e150, C4<0>, C4<0>; +L_0x2a1e240 .delay (20000,20000,20000) L_0x2a1e240/d; +v0x27f78a0_0 .net "S", 0 0, L_0x2a1e420; 1 drivers +v0x27f7940_0 .net "in0", 0 0, L_0x2a1dda0; 1 drivers +v0x27f79e0_0 .net "in1", 0 0, L_0x2a1de90; 1 drivers +v0x27f7a80_0 .net "nS", 0 0, L_0x2a1db40; 1 drivers +v0x27f7b00_0 .net "out0", 0 0, L_0x2a1d200; 1 drivers +v0x27f7ba0_0 .net "out1", 0 0, L_0x2a1e150; 1 drivers +v0x27f7c80_0 .net "outfinal", 0 0, L_0x2a1e240; 1 drivers +S_0x27f5ac0 .scope generate, "muxbits[6]" "muxbits[6]" 3 397, 3 397, S_0x25e6a40; + .timescale -9 -12; +P_0x27f4ab8 .param/l "i" 3 397, +C4<0110>; +L_0x2a20660/d .functor OR 1, L_0x2a21130, L_0x2a211d0, C4<0>, C4<0>; +L_0x2a20660 .delay (20000,20000,20000) L_0x2a20660/d; +v0x27f74e0_0 .net *"_s15", 0 0, L_0x2a21130; 1 drivers +v0x27f75a0_0 .net *"_s16", 0 0, L_0x2a211d0; 1 drivers +S_0x27f6b60 .scope module, "ZeroMux" "FourInMux" 3 399, 3 125, S_0x27f5ac0; + .timescale -9 -12; +L_0x2a1e5b0/d .functor NOT 1, L_0x2a1e940, C4<0>, C4<0>, C4<0>; +L_0x2a1e5b0 .delay (10000,10000,10000) L_0x2a1e5b0/d; +L_0x2a1e6a0/d .functor NOT 1, L_0x2a1ea70, C4<0>, C4<0>, C4<0>; +L_0x2a1e6a0 .delay (10000,10000,10000) L_0x2a1e6a0/d; +L_0x2a1e740/d .functor NAND 1, L_0x2a1e5b0, L_0x2a1e6a0, L_0x2a1eba0, C4<1>; +L_0x2a1e740 .delay (10000,10000,10000) L_0x2a1e740/d; +L_0x2a1ed20/d .functor NAND 1, L_0x2a1e940, L_0x2a1e6a0, L_0x2a1f6c0, C4<1>; +L_0x2a1ed20 .delay (10000,10000,10000) L_0x2a1ed20/d; +L_0x2a1ee10/d .functor NAND 1, L_0x2a1e5b0, L_0x2a1ea70, L_0x2a1f350, C4<1>; +L_0x2a1ee10 .delay (10000,10000,10000) L_0x2a1ee10/d; +L_0x2a1ef30/d .functor NAND 1, L_0x2a1e940, L_0x2a1ea70, L_0x2a1f3f0, C4<1>; +L_0x2a1ef30 .delay (10000,10000,10000) L_0x2a1ef30/d; +L_0x2a1f0a0/d .functor NAND 1, L_0x2a1e740, L_0x2a1ed20, L_0x2a1ee10, L_0x2a1ef30; +L_0x2a1f0a0 .delay (10000,10000,10000) L_0x2a1f0a0/d; +v0x27f6c50_0 .net "S0", 0 0, L_0x2a1e940; 1 drivers +v0x27f6d10_0 .net "S1", 0 0, L_0x2a1ea70; 1 drivers +v0x27f6db0_0 .net "in0", 0 0, L_0x2a1eba0; 1 drivers +v0x27f6e50_0 .net "in1", 0 0, L_0x2a1f6c0; 1 drivers +v0x27f6ed0_0 .net "in2", 0 0, L_0x2a1f350; 1 drivers +v0x27f6f70_0 .net "in3", 0 0, L_0x2a1f3f0; 1 drivers +v0x27f7010_0 .net "nS0", 0 0, L_0x2a1e5b0; 1 drivers +v0x27f70b0_0 .net "nS1", 0 0, L_0x2a1e6a0; 1 drivers +v0x27f7150_0 .net "out", 0 0, L_0x2a1f0a0; 1 drivers +v0x27f71f0_0 .net "out0", 0 0, L_0x2a1e740; 1 drivers +v0x27f7290_0 .net "out1", 0 0, L_0x2a1ed20; 1 drivers +v0x27f7330_0 .net "out2", 0 0, L_0x2a1ee10; 1 drivers +v0x27f7440_0 .net "out3", 0 0, L_0x2a1ef30; 1 drivers +S_0x27f61a0 .scope module, "OneMux" "FourInMux" 3 400, 3 125, S_0x27f5ac0; + .timescale -9 -12; +L_0x2a1f4e0/d .functor NOT 1, L_0x2a20210, C4<0>, C4<0>, C4<0>; +L_0x2a1f4e0 .delay (10000,10000,10000) L_0x2a1f4e0/d; +L_0x2a1f5d0/d .functor NOT 1, L_0x2a1f760, C4<0>, C4<0>, C4<0>; +L_0x2a1f5d0 .delay (10000,10000,10000) L_0x2a1f5d0/d; +L_0x2a1faf0/d .functor NAND 1, L_0x2a1f4e0, L_0x2a1f5d0, L_0x2a1f890, C4<1>; +L_0x2a1faf0 .delay (10000,10000,10000) L_0x2a1faf0/d; +L_0x2a1fbe0/d .functor NAND 1, L_0x2a20210, L_0x2a1f5d0, L_0x2a1f930, C4<1>; +L_0x2a1fbe0 .delay (10000,10000,10000) L_0x2a1fbe0/d; +L_0x2a1fcd0/d .functor NAND 1, L_0x2a1f4e0, L_0x2a1f760, L_0x2a1f9d0, C4<1>; +L_0x2a1fcd0 .delay (10000,10000,10000) L_0x2a1fcd0/d; +L_0x2a1fdf0/d .functor NAND 1, L_0x2a20210, L_0x2a1f760, L_0x2a20700, C4<1>; +L_0x2a1fdf0 .delay (10000,10000,10000) L_0x2a1fdf0/d; +L_0x2a1ff60/d .functor NAND 1, L_0x2a1faf0, L_0x2a1fbe0, L_0x2a1fcd0, L_0x2a1fdf0; +L_0x2a1ff60 .delay (10000,10000,10000) L_0x2a1ff60/d; +v0x27f6290_0 .net "S0", 0 0, L_0x2a20210; 1 drivers +v0x27f6350_0 .net "S1", 0 0, L_0x2a1f760; 1 drivers +v0x27f63f0_0 .net "in0", 0 0, L_0x2a1f890; 1 drivers +v0x27f6490_0 .net "in1", 0 0, L_0x2a1f930; 1 drivers +v0x27f6510_0 .net "in2", 0 0, L_0x2a1f9d0; 1 drivers +v0x27f65b0_0 .net "in3", 0 0, L_0x2a20700; 1 drivers +v0x27f6690_0 .net "nS0", 0 0, L_0x2a1f4e0; 1 drivers +v0x27f6730_0 .net "nS1", 0 0, L_0x2a1f5d0; 1 drivers +v0x27f67d0_0 .net "out", 0 0, L_0x2a1ff60; 1 drivers +v0x27f6870_0 .net "out0", 0 0, L_0x2a1faf0; 1 drivers +v0x27f6910_0 .net "out1", 0 0, L_0x2a1fbe0; 1 drivers +v0x27f69b0_0 .net "out2", 0 0, L_0x2a1fcd0; 1 drivers +v0x27f6ac0_0 .net "out3", 0 0, L_0x2a1fdf0; 1 drivers +S_0x27f5c30 .scope module, "TwoMux" "TwoInMux" 3 401, 3 109, S_0x27f5ac0; + .timescale -9 -12; +L_0x2a207f0/d .functor NOT 1, L_0x2a20340, C4<0>, C4<0>, C4<0>; +L_0x2a207f0 .delay (10000,10000,10000) L_0x2a207f0/d; +L_0x2a208e0/d .functor AND 1, L_0x2a203e0, L_0x2a207f0, C4<1>, C4<1>; +L_0x2a208e0 .delay (20000,20000,20000) L_0x2a208e0/d; +L_0x2a209d0/d .functor AND 1, L_0x2a204d0, L_0x2a20340, C4<1>, C4<1>; +L_0x2a209d0 .delay (20000,20000,20000) L_0x2a209d0/d; +L_0x2a20ac0/d .functor OR 1, L_0x2a208e0, L_0x2a209d0, C4<0>, C4<0>; +L_0x2a20ac0 .delay (20000,20000,20000) L_0x2a20ac0/d; +v0x27f5d20_0 .net "S", 0 0, L_0x2a20340; 1 drivers +v0x27f5dc0_0 .net "in0", 0 0, L_0x2a203e0; 1 drivers +v0x27f5e60_0 .net "in1", 0 0, L_0x2a204d0; 1 drivers +v0x27f5f00_0 .net "nS", 0 0, L_0x2a207f0; 1 drivers +v0x27f5f80_0 .net "out0", 0 0, L_0x2a208e0; 1 drivers +v0x27f6020_0 .net "out1", 0 0, L_0x2a209d0; 1 drivers +v0x27f6100_0 .net "outfinal", 0 0, L_0x2a20ac0; 1 drivers +S_0x27f40e0 .scope generate, "muxbits[7]" "muxbits[7]" 3 397, 3 397, S_0x25e6a40; + .timescale -9 -12; +P_0x2435818 .param/l "i" 3 397, +C4<0111>; +L_0x2a232a0/d .functor OR 1, L_0x2a233e0, L_0x2a23a20, C4<0>, C4<0>; +L_0x2a232a0 .delay (20000,20000,20000) L_0x2a232a0/d; +v0x27f5960_0 .net *"_s15", 0 0, L_0x2a233e0; 1 drivers +v0x27f5a20_0 .net *"_s16", 0 0, L_0x2a23a20; 1 drivers +S_0x27f4fe0 .scope module, "ZeroMux" "FourInMux" 3 399, 3 125, S_0x27f40e0; + .timescale -9 -12; +L_0x2a20ca0/d .functor NOT 1, L_0x2a21bd0, C4<0>, C4<0>, C4<0>; +L_0x2a20ca0 .delay (10000,10000,10000) L_0x2a20ca0/d; +L_0x2a20d90/d .functor NOT 1, L_0x2a212c0, C4<0>, C4<0>, C4<0>; +L_0x2a20d90 .delay (10000,10000,10000) L_0x2a20d90/d; +L_0x2a20e30/d .functor NAND 1, L_0x2a20ca0, L_0x2a20d90, L_0x2a213f0, C4<1>; +L_0x2a20e30 .delay (10000,10000,10000) L_0x2a20e30/d; +L_0x2a20f70/d .functor NAND 1, L_0x2a21bd0, L_0x2a20d90, L_0x2a21490, C4<1>; +L_0x2a20f70 .delay (10000,10000,10000) L_0x2a20f70/d; +L_0x2a216c0/d .functor NAND 1, L_0x2a20ca0, L_0x2a212c0, L_0x2a21530, C4<1>; +L_0x2a216c0 .delay (10000,10000,10000) L_0x2a216c0/d; +L_0x2a217b0/d .functor NAND 1, L_0x2a21bd0, L_0x2a212c0, L_0x2a21620, C4<1>; +L_0x2a217b0 .delay (10000,10000,10000) L_0x2a217b0/d; +L_0x2a21920/d .functor NAND 1, L_0x2a20e30, L_0x2a20f70, L_0x2a216c0, L_0x2a217b0; +L_0x2a21920 .delay (10000,10000,10000) L_0x2a21920/d; +v0x27f50d0_0 .net "S0", 0 0, L_0x2a21bd0; 1 drivers +v0x27f5190_0 .net "S1", 0 0, L_0x2a212c0; 1 drivers +v0x27f5230_0 .net "in0", 0 0, L_0x2a213f0; 1 drivers +v0x27f52d0_0 .net "in1", 0 0, L_0x2a21490; 1 drivers +v0x27f5350_0 .net "in2", 0 0, L_0x2a21530; 1 drivers +v0x27f53f0_0 .net "in3", 0 0, L_0x2a21620; 1 drivers +v0x27f5490_0 .net "nS0", 0 0, L_0x2a20ca0; 1 drivers +v0x27f5530_0 .net "nS1", 0 0, L_0x2a20d90; 1 drivers +v0x27f55d0_0 .net "out", 0 0, L_0x2a21920; 1 drivers +v0x27f5670_0 .net "out0", 0 0, L_0x2a20e30; 1 drivers +v0x27f5710_0 .net "out1", 0 0, L_0x2a20f70; 1 drivers +v0x27f57b0_0 .net "out2", 0 0, L_0x2a216c0; 1 drivers +v0x27f58c0_0 .net "out3", 0 0, L_0x2a217b0; 1 drivers +S_0x27f4640 .scope module, "OneMux" "FourInMux" 3 400, 3 125, S_0x27f40e0; + .timescale -9 -12; +L_0x2a22180/d .functor NOT 1, L_0x2a21d00, C4<0>, C4<0>, C4<0>; +L_0x2a22180 .delay (10000,10000,10000) L_0x2a22180/d; +L_0x2a22270/d .functor NOT 1, L_0x2a21e30, C4<0>, C4<0>, C4<0>; +L_0x2a22270 .delay (10000,10000,10000) L_0x2a22270/d; +L_0x2a22310/d .functor NAND 1, L_0x2a22180, L_0x2a22270, L_0x2a21f60, C4<1>; +L_0x2a22310 .delay (10000,10000,10000) L_0x2a22310/d; +L_0x2a22450/d .functor NAND 1, L_0x2a21d00, L_0x2a22270, L_0x2a22000, C4<1>; +L_0x2a22450 .delay (10000,10000,10000) L_0x2a22450/d; +L_0x2a22540/d .functor NAND 1, L_0x2a22180, L_0x2a21e30, L_0x2a22ee0, C4<1>; +L_0x2a22540 .delay (10000,10000,10000) L_0x2a22540/d; +L_0x2a22660/d .functor NAND 1, L_0x2a21d00, L_0x2a21e30, L_0x2a22f80, C4<1>; +L_0x2a22660 .delay (10000,10000,10000) L_0x2a22660/d; +L_0x2a227d0/d .functor NAND 1, L_0x2a22310, L_0x2a22450, L_0x2a22540, L_0x2a22660; +L_0x2a227d0 .delay (10000,10000,10000) L_0x2a227d0/d; +v0x27f4730_0 .net "S0", 0 0, L_0x2a21d00; 1 drivers +v0x27f47d0_0 .net "S1", 0 0, L_0x2a21e30; 1 drivers +v0x27f4870_0 .net "in0", 0 0, L_0x2a21f60; 1 drivers +v0x27f4910_0 .net "in1", 0 0, L_0x2a22000; 1 drivers +v0x27f4990_0 .net "in2", 0 0, L_0x2a22ee0; 1 drivers +v0x27f4a30_0 .net "in3", 0 0, L_0x2a22f80; 1 drivers +v0x27f4b10_0 .net "nS0", 0 0, L_0x2a22180; 1 drivers +v0x27f4bb0_0 .net "nS1", 0 0, L_0x2a22270; 1 drivers +v0x27f4c50_0 .net "out", 0 0, L_0x2a227d0; 1 drivers +v0x27f4cf0_0 .net "out0", 0 0, L_0x2a22310; 1 drivers +v0x27f4d90_0 .net "out1", 0 0, L_0x2a22450; 1 drivers +v0x27f4e30_0 .net "out2", 0 0, L_0x2a22540; 1 drivers +v0x27f4f40_0 .net "out3", 0 0, L_0x2a22660; 1 drivers +S_0x27f41d0 .scope module, "TwoMux" "TwoInMux" 3 401, 3 109, S_0x27f40e0; + .timescale -9 -12; +L_0x2a226f0/d .functor NOT 1, L_0x2a234e0, C4<0>, C4<0>, C4<0>; +L_0x2a226f0 .delay (10000,10000,10000) L_0x2a226f0/d; +L_0x2a22ad0/d .functor AND 1, L_0x2a23070, L_0x2a226f0, C4<1>, C4<1>; +L_0x2a22ad0 .delay (20000,20000,20000) L_0x2a22ad0/d; +L_0x2a22bc0/d .functor AND 1, L_0x2a23110, L_0x2a234e0, C4<1>, C4<1>; +L_0x2a22bc0 .delay (20000,20000,20000) L_0x2a22bc0/d; +L_0x2a22cb0/d .functor OR 1, L_0x2a22ad0, L_0x2a22bc0, C4<0>, C4<0>; +L_0x2a22cb0 .delay (20000,20000,20000) L_0x2a22cb0/d; +v0x27f42c0_0 .net "S", 0 0, L_0x2a234e0; 1 drivers +v0x27f4340_0 .net "in0", 0 0, L_0x2a23070; 1 drivers +v0x27f43c0_0 .net "in1", 0 0, L_0x2a23110; 1 drivers +v0x27f4440_0 .net "nS", 0 0, L_0x2a226f0; 1 drivers +v0x27f44c0_0 .net "out0", 0 0, L_0x2a22ad0; 1 drivers +v0x27f4540_0 .net "out1", 0 0, L_0x2a22bc0; 1 drivers +v0x27f45c0_0 .net "outfinal", 0 0, L_0x2a22cb0; 1 drivers +S_0x27f0f40 .scope generate, "muxbits[8]" "muxbits[8]" 3 397, 3 397, S_0x25e6a40; + .timescale -9 -12; +P_0x27efc68 .param/l "i" 3 397, +C4<01000>; +L_0x2a1bd80/d .functor OR 1, L_0x2a1c0d0, L_0x2a25e30, C4<0>, C4<0>; +L_0x2a1bd80 .delay (20000,20000,20000) L_0x2a1bd80/d; +v0x27f3fe0_0 .net *"_s15", 0 0, L_0x2a1c0d0; 1 drivers +v0x27f4060_0 .net *"_s16", 0 0, L_0x2a25e30; 1 drivers +S_0x27f3800 .scope module, "ZeroMux" "FourInMux" 3 399, 3 125, S_0x27f0f40; + .timescale -9 -12; +L_0x2a23ac0/d .functor NOT 1, L_0x2a23580, C4<0>, C4<0>, C4<0>; +L_0x2a23ac0 .delay (10000,10000,10000) L_0x2a23ac0/d; +L_0x2a23bb0/d .functor NOT 1, L_0x2a236b0, C4<0>, C4<0>, C4<0>; +L_0x2a23bb0 .delay (10000,10000,10000) L_0x2a23bb0/d; +L_0x2a23c50/d .functor NAND 1, L_0x2a23ac0, L_0x2a23bb0, L_0x2a237e0, C4<1>; +L_0x2a23c50 .delay (10000,10000,10000) L_0x2a23c50/d; +L_0x2a23d90/d .functor NAND 1, L_0x2a23580, L_0x2a23bb0, L_0x2a23880, C4<1>; +L_0x2a23d90 .delay (10000,10000,10000) L_0x2a23d90/d; +L_0x2a23ee0/d .functor NAND 1, L_0x2a23ac0, L_0x2a236b0, L_0x2a23920, C4<1>; +L_0x2a23ee0 .delay (10000,10000,10000) L_0x2a23ee0/d; +L_0x2a24030/d .functor NAND 1, L_0x2a23580, L_0x2a236b0, L_0x2a24920, C4<1>; +L_0x2a24030 .delay (10000,10000,10000) L_0x2a24030/d; +L_0x2a241a0/d .functor NAND 1, L_0x2a23c50, L_0x2a23d90, L_0x2a23ee0, L_0x2a24030; +L_0x2a241a0 .delay (10000,10000,10000) L_0x2a241a0/d; +v0x27f38f0_0 .net "S0", 0 0, L_0x2a23580; 1 drivers +v0x27f3970_0 .net "S1", 0 0, L_0x2a236b0; 1 drivers +v0x27f39f0_0 .net "in0", 0 0, L_0x2a237e0; 1 drivers +v0x27f3a70_0 .net "in1", 0 0, L_0x2a23880; 1 drivers +v0x27f3af0_0 .net "in2", 0 0, L_0x2a23920; 1 drivers +v0x27f3b70_0 .net "in3", 0 0, L_0x2a24920; 1 drivers +v0x27f3bf0_0 .net "nS0", 0 0, L_0x2a23ac0; 1 drivers +v0x27f3c70_0 .net "nS1", 0 0, L_0x2a23bb0; 1 drivers +v0x27f3cf0_0 .net "out", 0 0, L_0x2a241a0; 1 drivers +v0x27f3d70_0 .net "out0", 0 0, L_0x2a23c50; 1 drivers +v0x27f3df0_0 .net "out1", 0 0, L_0x2a23d90; 1 drivers +v0x27f3e70_0 .net "out2", 0 0, L_0x2a23ee0; 1 drivers +v0x27f3f60_0 .net "out3", 0 0, L_0x2a24030; 1 drivers +S_0x27f3020 .scope module, "OneMux" "FourInMux" 3 400, 3 125, S_0x27f0f40; + .timescale -9 -12; +L_0x2a240c0/d .functor NOT 1, L_0x2a25280, C4<0>, C4<0>, C4<0>; +L_0x2a240c0 .delay (10000,10000,10000) L_0x2a240c0/d; +L_0x2a244a0/d .functor NOT 1, L_0x2a24a10, C4<0>, C4<0>, C4<0>; +L_0x2a244a0 .delay (10000,10000,10000) L_0x2a244a0/d; +L_0x2a24500/d .functor NAND 1, L_0x2a240c0, L_0x2a244a0, L_0x2a24b40, C4<1>; +L_0x2a24500 .delay (10000,10000,10000) L_0x2a24500/d; +L_0x2a24600/d .functor NAND 1, L_0x2a25280, L_0x2a244a0, L_0x2a24be0, C4<1>; +L_0x2a24600 .delay (10000,10000,10000) L_0x2a24600/d; +L_0x2a24720/d .functor NAND 1, L_0x2a240c0, L_0x2a24a10, L_0x2a24c80, C4<1>; +L_0x2a24720 .delay (10000,10000,10000) L_0x2a24720/d; +L_0x2a24870/d .functor NAND 1, L_0x2a25280, L_0x2a24a10, L_0x2a24d70, C4<1>; +L_0x2a24870 .delay (10000,10000,10000) L_0x2a24870/d; +L_0x2a24fd0/d .functor NAND 1, L_0x2a24500, L_0x2a24600, L_0x2a24720, L_0x2a24870; +L_0x2a24fd0 .delay (10000,10000,10000) L_0x2a24fd0/d; +v0x27f3110_0 .net "S0", 0 0, L_0x2a25280; 1 drivers +v0x27f3190_0 .net "S1", 0 0, L_0x2a24a10; 1 drivers +v0x27f3210_0 .net "in0", 0 0, L_0x2a24b40; 1 drivers +v0x27f3290_0 .net "in1", 0 0, L_0x2a24be0; 1 drivers +v0x27f3310_0 .net "in2", 0 0, L_0x2a24c80; 1 drivers +v0x27f3390_0 .net "in3", 0 0, L_0x2a24d70; 1 drivers +v0x27f3410_0 .net "nS0", 0 0, L_0x2a240c0; 1 drivers +v0x27f3490_0 .net "nS1", 0 0, L_0x2a244a0; 1 drivers +v0x27f3510_0 .net "out", 0 0, L_0x2a24fd0; 1 drivers +v0x27f3590_0 .net "out0", 0 0, L_0x2a24500; 1 drivers +v0x27f3610_0 .net "out1", 0 0, L_0x2a24600; 1 drivers +v0x27f3690_0 .net "out2", 0 0, L_0x2a24720; 1 drivers +v0x27f3780_0 .net "out3", 0 0, L_0x2a24870; 1 drivers +S_0x27f10b0 .scope module, "TwoMux" "TwoInMux" 3 401, 3 109, S_0x27f0f40; + .timescale -9 -12; +L_0x2473930/d .functor NOT 1, L_0x2a1b950, C4<0>, C4<0>, C4<0>; +L_0x2473930 .delay (10000,10000,10000) L_0x2473930/d; +L_0x2a24eb0/d .functor AND 1, L_0x2a253b0, L_0x2473930, C4<1>, C4<1>; +L_0x2a24eb0 .delay (20000,20000,20000) L_0x2a24eb0/d; +L_0x2a25950/d .functor AND 1, L_0x2a1bce0, L_0x2a1b950, C4<1>, C4<1>; +L_0x2a25950 .delay (20000,20000,20000) L_0x2a25950/d; +L_0x2a25a40/d .functor OR 1, L_0x2a24eb0, L_0x2a25950, C4<0>, C4<0>; +L_0x2a25a40 .delay (20000,20000,20000) L_0x2a25a40/d; +v0x27f2ca0_0 .net "S", 0 0, L_0x2a1b950; 1 drivers +v0x27f2d20_0 .net "in0", 0 0, L_0x2a253b0; 1 drivers +v0x27f2da0_0 .net "in1", 0 0, L_0x2a1bce0; 1 drivers +v0x27f2e20_0 .net "nS", 0 0, L_0x2473930; 1 drivers +v0x27f2ea0_0 .net "out0", 0 0, L_0x2a24eb0; 1 drivers +v0x27f2f20_0 .net "out1", 0 0, L_0x2a25950; 1 drivers +v0x27f2fa0_0 .net "outfinal", 0 0, L_0x2a25a40; 1 drivers +S_0x20734b0 .scope generate, "muxbits[9]" "muxbits[9]" 3 397, 3 397, S_0x25e6a40; + .timescale -9 -12; +P_0x1d2bc88 .param/l "i" 3 397, +C4<01001>; +L_0x2a280a0/d .functor OR 1, L_0x2a281e0, L_0x2a28280, C4<0>, C4<0>; +L_0x2a280a0 .delay (20000,20000,20000) L_0x2a280a0/d; +v0x27f0de0_0 .net *"_s15", 0 0, L_0x2a281e0; 1 drivers +v0x27f0ea0_0 .net *"_s16", 0 0, L_0x2a28280; 1 drivers +S_0x1e82f90 .scope module, "ZeroMux" "FourInMux" 3 399, 3 125, S_0x20734b0; + .timescale -9 -12; +L_0x2a25f20/d .functor NOT 1, L_0x2a26f70, C4<0>, C4<0>, C4<0>; +L_0x2a25f20 .delay (10000,10000,10000) L_0x2a25f20/d; +L_0x2a26010/d .functor NOT 1, L_0x2a26570, C4<0>, C4<0>, C4<0>; +L_0x2a26010 .delay (10000,10000,10000) L_0x2a26010/d; +L_0x2a260b0/d .functor NAND 1, L_0x2a25f20, L_0x2a26010, L_0x2a266a0, C4<1>; +L_0x2a260b0 .delay (10000,10000,10000) L_0x2a260b0/d; +L_0x2a261f0/d .functor NAND 1, L_0x2a26f70, L_0x2a26010, L_0x2a26740, C4<1>; +L_0x2a261f0 .delay (10000,10000,10000) L_0x2a261f0/d; +L_0x2a262e0/d .functor NAND 1, L_0x2a25f20, L_0x2a26570, L_0x2a267e0, C4<1>; +L_0x2a262e0 .delay (10000,10000,10000) L_0x2a262e0/d; +L_0x2a26b50/d .functor NAND 1, L_0x2a26f70, L_0x2a26570, L_0x2a268d0, C4<1>; +L_0x2a26b50 .delay (10000,10000,10000) L_0x2a26b50/d; +L_0x2a26cc0/d .functor NAND 1, L_0x2a260b0, L_0x2a261f0, L_0x2a262e0, L_0x2a26b50; +L_0x2a26cc0 .delay (10000,10000,10000) L_0x2a26cc0/d; +v0x1e83080_0 .net "S0", 0 0, L_0x2a26f70; 1 drivers +v0x1e83140_0 .net "S1", 0 0, L_0x2a26570; 1 drivers +v0x27f06b0_0 .net "in0", 0 0, L_0x2a266a0; 1 drivers +v0x27f0750_0 .net "in1", 0 0, L_0x2a26740; 1 drivers +v0x27f07d0_0 .net "in2", 0 0, L_0x2a267e0; 1 drivers +v0x27f0870_0 .net "in3", 0 0, L_0x2a268d0; 1 drivers +v0x27f0910_0 .net "nS0", 0 0, L_0x2a25f20; 1 drivers +v0x27f09b0_0 .net "nS1", 0 0, L_0x2a26010; 1 drivers +v0x27f0a50_0 .net "out", 0 0, L_0x2a26cc0; 1 drivers +v0x27f0af0_0 .net "out0", 0 0, L_0x2a260b0; 1 drivers +v0x27f0b90_0 .net "out1", 0 0, L_0x2a261f0; 1 drivers +v0x27f0c30_0 .net "out2", 0 0, L_0x2a262e0; 1 drivers +v0x27f0d40_0 .net "out3", 0 0, L_0x2a26b50; 1 drivers +S_0x1f2b3b0 .scope module, "OneMux" "FourInMux" 3 400, 3 125, S_0x20734b0; + .timescale -9 -12; +L_0x2a269c0/d .functor NOT 1, L_0x2a270a0, C4<0>, C4<0>, C4<0>; +L_0x2a269c0 .delay (10000,10000,10000) L_0x2a269c0/d; +L_0x2a26a60/d .functor NOT 1, L_0x2a271d0, C4<0>, C4<0>, C4<0>; +L_0x2a26a60 .delay (10000,10000,10000) L_0x2a26a60/d; +L_0x2a276b0/d .functor NAND 1, L_0x2a269c0, L_0x2a26a60, L_0x2a27300, C4<1>; +L_0x2a276b0 .delay (10000,10000,10000) L_0x2a276b0/d; +L_0x2a277f0/d .functor NAND 1, L_0x2a270a0, L_0x2a26a60, L_0x2a273a0, C4<1>; +L_0x2a277f0 .delay (10000,10000,10000) L_0x2a277f0/d; +L_0x2a278e0/d .functor NAND 1, L_0x2a269c0, L_0x2a271d0, L_0x2a27440, C4<1>; +L_0x2a278e0 .delay (10000,10000,10000) L_0x2a278e0/d; +L_0x2a27a00/d .functor NAND 1, L_0x2a270a0, L_0x2a271d0, L_0x2a27530, C4<1>; +L_0x2a27a00 .delay (10000,10000,10000) L_0x2a27a00/d; +L_0x2a27b70/d .functor NAND 1, L_0x2a276b0, L_0x2a277f0, L_0x2a278e0, L_0x2a27a00; +L_0x2a27b70 .delay (10000,10000,10000) L_0x2a27b70/d; +v0x1e82770_0 .net "S0", 0 0, L_0x2a270a0; 1 drivers +v0x1e82830_0 .net "S1", 0 0, L_0x2a271d0; 1 drivers +v0x1e828d0_0 .net "in0", 0 0, L_0x2a27300; 1 drivers +v0x1e82970_0 .net "in1", 0 0, L_0x2a273a0; 1 drivers +v0x1e829f0_0 .net "in2", 0 0, L_0x2a27440; 1 drivers +v0x1e82a90_0 .net "in3", 0 0, L_0x2a27530; 1 drivers +v0x1e82b30_0 .net "nS0", 0 0, L_0x2a269c0; 1 drivers +v0x1e82bd0_0 .net "nS1", 0 0, L_0x2a26a60; 1 drivers +v0x1e82c70_0 .net "out", 0 0, L_0x2a27b70; 1 drivers +v0x1e82d10_0 .net "out0", 0 0, L_0x2a276b0; 1 drivers +v0x1e82db0_0 .net "out1", 0 0, L_0x2a277f0; 1 drivers +v0x1e82e50_0 .net "out2", 0 0, L_0x2a278e0; 1 drivers +v0x1e82ef0_0 .net "out3", 0 0, L_0x2a27a00; 1 drivers +S_0x20735e0 .scope module, "TwoMux" "TwoInMux" 3 401, 3 109, S_0x20734b0; + .timescale -9 -12; +L_0x2a283e0/d .functor NOT 1, L_0x2a28890, C4<0>, C4<0>, C4<0>; +L_0x2a283e0 .delay (10000,10000,10000) L_0x2a283e0/d; +L_0x2a284d0/d .functor AND 1, L_0x2a27e20, L_0x2a283e0, C4<1>, C4<1>; +L_0x2a284d0 .delay (20000,20000,20000) L_0x2a284d0/d; +L_0x2a285c0/d .functor AND 1, L_0x2a27f10, L_0x2a28890, C4<1>, C4<1>; +L_0x2a285c0 .delay (20000,20000,20000) L_0x2a285c0/d; +L_0x2a286b0/d .functor OR 1, L_0x2a284d0, L_0x2a285c0, C4<0>, C4<0>; +L_0x2a286b0 .delay (20000,20000,20000) L_0x2a286b0/d; +v0x20736d0_0 .net "S", 0 0, L_0x2a28890; 1 drivers +v0x2073770_0 .net "in0", 0 0, L_0x2a27e20; 1 drivers +v0x1f2b0b0_0 .net "in1", 0 0, L_0x2a27f10; 1 drivers +v0x1f2b150_0 .net "nS", 0 0, L_0x2a283e0; 1 drivers +v0x1f2b1d0_0 .net "out0", 0 0, L_0x2a284d0; 1 drivers +v0x1f2b270_0 .net "out1", 0 0, L_0x2a285c0; 1 drivers +v0x1f2b310_0 .net "outfinal", 0 0, L_0x2a286b0; 1 drivers +S_0x1d2e680 .scope generate, "muxbits[10]" "muxbits[10]" 3 397, 3 397, S_0x25e6a40; + .timescale -9 -12; +P_0x26814c8 .param/l "i" 3 397, +C4<01010>; +L_0x2a2a970/d .functor OR 1, L_0x2a2aab0, L_0x2a2ab50, C4<0>, C4<0>; +L_0x2a2a970 .delay (20000,20000,20000) L_0x2a2a970/d; +v0x27efbc0_0 .net *"_s15", 0 0, L_0x2a2aab0; 1 drivers +v0x2073410_0 .net *"_s16", 0 0, L_0x2a2ab50; 1 drivers +S_0x1d3d400 .scope module, "ZeroMux" "FourInMux" 3 399, 3 125, S_0x1d2e680; + .timescale -9 -12; +L_0x2a28370/d .functor NOT 1, L_0x2a28930, C4<0>, C4<0>, C4<0>; +L_0x2a28370 .delay (10000,10000,10000) L_0x2a28370/d; +L_0x2a28fb0/d .functor NOT 1, L_0x2a28a60, C4<0>, C4<0>, C4<0>; +L_0x2a28fb0 .delay (10000,10000,10000) L_0x2a28fb0/d; +L_0x2a29050/d .functor NAND 1, L_0x2a28370, L_0x2a28fb0, L_0x2a28b90, C4<1>; +L_0x2a29050 .delay (10000,10000,10000) L_0x2a29050/d; +L_0x2a29190/d .functor NAND 1, L_0x2a28930, L_0x2a28fb0, L_0x2a28c30, C4<1>; +L_0x2a29190 .delay (10000,10000,10000) L_0x2a29190/d; +L_0x2a29280/d .functor NAND 1, L_0x2a28370, L_0x2a28a60, L_0x2a28cd0, C4<1>; +L_0x2a29280 .delay (10000,10000,10000) L_0x2a29280/d; +L_0x2a293a0/d .functor NAND 1, L_0x2a28930, L_0x2a28a60, L_0x2a28dc0, C4<1>; +L_0x2a293a0 .delay (10000,10000,10000) L_0x2a293a0/d; +L_0x2a29510/d .functor NAND 1, L_0x2a29050, L_0x2a29190, L_0x2a29280, L_0x2a293a0; +L_0x2a29510 .delay (10000,10000,10000) L_0x2a29510/d; +v0x1d3d4f0_0 .net "S0", 0 0, L_0x2a28930; 1 drivers +v0x1d3d5b0_0 .net "S1", 0 0, L_0x2a28a60; 1 drivers +v0x1d2a250_0 .net "in0", 0 0, L_0x2a28b90; 1 drivers +v0x1d2a2f0_0 .net "in1", 0 0, L_0x2a28c30; 1 drivers +v0x1d2a370_0 .net "in2", 0 0, L_0x2a28cd0; 1 drivers +v0x1d2a410_0 .net "in3", 0 0, L_0x2a28dc0; 1 drivers +v0x1d4dac0_0 .net "nS0", 0 0, L_0x2a28370; 1 drivers +v0x1d4db60_0 .net "nS1", 0 0, L_0x2a28fb0; 1 drivers +v0x1d4dc00_0 .net "out", 0 0, L_0x2a29510; 1 drivers +v0x1d4dca0_0 .net "out0", 0 0, L_0x2a29050; 1 drivers +v0x27ef970_0 .net "out1", 0 0, L_0x2a29190; 1 drivers +v0x27efa10_0 .net "out2", 0 0, L_0x2a29280; 1 drivers +v0x27efb20_0 .net "out3", 0 0, L_0x2a293a0; 1 drivers +S_0x1d2ba30 .scope module, "OneMux" "FourInMux" 3 400, 3 125, S_0x1d2e680; + .timescale -9 -12; +L_0x2a28eb0/d .functor NOT 1, L_0x2a2a660, C4<0>, C4<0>, C4<0>; +L_0x2a28eb0 .delay (10000,10000,10000) L_0x2a28eb0/d; +L_0x2a29e80/d .functor NOT 1, L_0x2a297c0, C4<0>, C4<0>, C4<0>; +L_0x2a29e80 .delay (10000,10000,10000) L_0x2a29e80/d; +L_0x2a29f20/d .functor NAND 1, L_0x2a28eb0, L_0x2a29e80, L_0x2a298f0, C4<1>; +L_0x2a29f20 .delay (10000,10000,10000) L_0x2a29f20/d; +L_0x2a2a060/d .functor NAND 1, L_0x2a2a660, L_0x2a29e80, L_0x2a29990, C4<1>; +L_0x2a2a060 .delay (10000,10000,10000) L_0x2a2a060/d; +L_0x2a2a150/d .functor NAND 1, L_0x2a28eb0, L_0x2a297c0, L_0x2a29a30, C4<1>; +L_0x2a2a150 .delay (10000,10000,10000) L_0x2a2a150/d; +L_0x2a2a240/d .functor NAND 1, L_0x2a2a660, L_0x2a297c0, L_0x2a29b20, C4<1>; +L_0x2a2a240 .delay (10000,10000,10000) L_0x2a2a240/d; +L_0x2a2a3b0/d .functor NAND 1, L_0x2a29f20, L_0x2a2a060, L_0x2a2a150, L_0x2a2a240; +L_0x2a2a3b0 .delay (10000,10000,10000) L_0x2a2a3b0/d; +v0x1d2bb20_0 .net "S0", 0 0, L_0x2a2a660; 1 drivers +v0x1d2bbe0_0 .net "S1", 0 0, L_0x2a297c0; 1 drivers +v0x1d32190_0 .net "in0", 0 0, L_0x2a298f0; 1 drivers +v0x1d32230_0 .net "in1", 0 0, L_0x2a29990; 1 drivers +v0x1d322b0_0 .net "in2", 0 0, L_0x2a29a30; 1 drivers +v0x1d32350_0 .net "in3", 0 0, L_0x2a29b20; 1 drivers +v0x1d2fbf0_0 .net "nS0", 0 0, L_0x2a28eb0; 1 drivers +v0x1d2fc90_0 .net "nS1", 0 0, L_0x2a29e80; 1 drivers +v0x1d2fd30_0 .net "out", 0 0, L_0x2a2a3b0; 1 drivers +v0x1d2fdd0_0 .net "out0", 0 0, L_0x2a29f20; 1 drivers +v0x1d374a0_0 .net "out1", 0 0, L_0x2a2a060; 1 drivers +v0x1d37540_0 .net "out2", 0 0, L_0x2a2a150; 1 drivers +v0x1d37650_0 .net "out3", 0 0, L_0x2a2a240; 1 drivers +S_0x1d35290 .scope module, "TwoMux" "TwoInMux" 3 401, 3 109, S_0x1d2e680; + .timescale -9 -12; +L_0x2a29c10/d .functor NOT 1, L_0x2a0e1f0, C4<0>, C4<0>, C4<0>; +L_0x2a29c10 .delay (10000,10000,10000) L_0x2a29c10/d; +L_0x2a29d00/d .functor AND 1, L_0x2a0e290, L_0x2a29c10, C4<1>, C4<1>; +L_0x2a29d00 .delay (20000,20000,20000) L_0x2a29d00/d; +L_0x2a0df20/d .functor AND 1, L_0x2a2a7e0, L_0x2a0e1f0, C4<1>, C4<1>; +L_0x2a0df20 .delay (20000,20000,20000) L_0x2a0df20/d; +L_0x2a0e010/d .functor OR 1, L_0x2a29d00, L_0x2a0df20, C4<0>, C4<0>; +L_0x2a0e010 .delay (20000,20000,20000) L_0x2a0e010/d; +v0x1d35380_0 .net "S", 0 0, L_0x2a0e1f0; 1 drivers +v0x1d35420_0 .net "in0", 0 0, L_0x2a0e290; 1 drivers +v0x1d2e7b0_0 .net "in1", 0 0, L_0x2a2a7e0; 1 drivers +v0x1d44cf0_0 .net "nS", 0 0, L_0x2a29c10; 1 drivers +v0x1d44d70_0 .net "out0", 0 0, L_0x2a29d00; 1 drivers +v0x1d44df0_0 .net "out1", 0 0, L_0x2a0df20; 1 drivers +v0x1d44ed0_0 .net "outfinal", 0 0, L_0x2a0e010; 1 drivers +S_0x2677960 .scope generate, "muxbits[11]" "muxbits[11]" 3 397, 3 397, S_0x25e6a40; + .timescale -9 -12; +P_0x27aeeb8 .param/l "i" 3 397, +C4<01011>; +L_0x2a2d480/d .functor OR 1, L_0x2a2d5c0, L_0x2a2d660, C4<0>, C4<0>; +L_0x2a2d480 .delay (20000,20000,20000) L_0x2a2d480/d; +v0x1d39b80_0 .net *"_s15", 0 0, L_0x2a2d5c0; 1 drivers +v0x1d2e5e0_0 .net *"_s16", 0 0, L_0x2a2d660; 1 drivers +S_0x26ba7a0 .scope module, "ZeroMux" "FourInMux" 3 399, 3 125, S_0x2677960; + .timescale -9 -12; +L_0x2a2ac40/d .functor NOT 1, L_0x2a2c3a0, C4<0>, C4<0>, C4<0>; +L_0x2a2ac40 .delay (10000,10000,10000) L_0x2a2ac40/d; +L_0x2a2ad30/d .functor NOT 1, L_0x2a2b5f0, C4<0>, C4<0>, C4<0>; +L_0x2a2ad30 .delay (10000,10000,10000) L_0x2a2ad30/d; +L_0x2a2bc90/d .functor NAND 1, L_0x2a2ac40, L_0x2a2ad30, L_0x2a2b720, C4<1>; +L_0x2a2bc90 .delay (10000,10000,10000) L_0x2a2bc90/d; +L_0x2a2bdd0/d .functor NAND 1, L_0x2a2c3a0, L_0x2a2ad30, L_0x2a2b7c0, C4<1>; +L_0x2a2bdd0 .delay (10000,10000,10000) L_0x2a2bdd0/d; +L_0x2a2bec0/d .functor NAND 1, L_0x2a2ac40, L_0x2a2b5f0, L_0x2a2b860, C4<1>; +L_0x2a2bec0 .delay (10000,10000,10000) L_0x2a2bec0/d; +L_0x2a2bfb0/d .functor NAND 1, L_0x2a2c3a0, L_0x2a2b5f0, L_0x2a2b950, C4<1>; +L_0x2a2bfb0 .delay (10000,10000,10000) L_0x2a2bfb0/d; +L_0x2a2c0f0/d .functor NAND 1, L_0x2a2bc90, L_0x2a2bdd0, L_0x2a2bec0, L_0x2a2bfb0; +L_0x2a2c0f0 .delay (10000,10000,10000) L_0x2a2c0f0/d; +v0x26ba890_0 .net "S0", 0 0, L_0x2a2c3a0; 1 drivers +v0x26bf3b0_0 .net "S1", 0 0, L_0x2a2b5f0; 1 drivers +v0x26bf450_0 .net "in0", 0 0, L_0x2a2b720; 1 drivers +v0x26bf4f0_0 .net "in1", 0 0, L_0x2a2b7c0; 1 drivers +v0x26d7140_0 .net "in2", 0 0, L_0x2a2b860; 1 drivers +v0x26d71e0_0 .net "in3", 0 0, L_0x2a2b950; 1 drivers +v0x26d7280_0 .net "nS0", 0 0, L_0x2a2ac40; 1 drivers +v0x1ced690_0 .net "nS1", 0 0, L_0x2a2ad30; 1 drivers +v0x1ced730_0 .net "out", 0 0, L_0x2a2c0f0; 1 drivers +v0x1ced7d0_0 .net "out0", 0 0, L_0x2a2bc90; 1 drivers +v0x1ced870_0 .net "out1", 0 0, L_0x2a2bdd0; 1 drivers +v0x1d399d0_0 .net "out2", 0 0, L_0x2a2bec0; 1 drivers +v0x1d39ae0_0 .net "out3", 0 0, L_0x2a2bfb0; 1 drivers +S_0x2694350 .scope module, "OneMux" "FourInMux" 3 400, 3 125, S_0x2677960; + .timescale -9 -12; +L_0x2a2ba40/d .functor NOT 1, L_0x2a2c4d0, C4<0>, C4<0>, C4<0>; +L_0x2a2ba40 .delay (10000,10000,10000) L_0x2a2ba40/d; +L_0x2a2bb30/d .functor NOT 1, L_0x2a2c600, C4<0>, C4<0>, C4<0>; +L_0x2a2bb30 .delay (10000,10000,10000) L_0x2a2bb30/d; +L_0x2a2bbd0/d .functor NAND 1, L_0x2a2ba40, L_0x2a2bb30, L_0x2a2c730, C4<1>; +L_0x2a2bbd0 .delay (10000,10000,10000) L_0x2a2bbd0/d; +L_0x2a2cc30/d .functor NAND 1, L_0x2a2c4d0, L_0x2a2bb30, L_0x2a2c7d0, C4<1>; +L_0x2a2cc30 .delay (10000,10000,10000) L_0x2a2cc30/d; +L_0x2a2cd20/d .functor NAND 1, L_0x2a2ba40, L_0x2a2c600, L_0x2a2c870, C4<1>; +L_0x2a2cd20 .delay (10000,10000,10000) L_0x2a2cd20/d; +L_0x2a2ce10/d .functor NAND 1, L_0x2a2c4d0, L_0x2a2c600, L_0x2a2c960, C4<1>; +L_0x2a2ce10 .delay (10000,10000,10000) L_0x2a2ce10/d; +L_0x2a2cf50/d .functor NAND 1, L_0x2a2bbd0, L_0x2a2cc30, L_0x2a2cd20, L_0x2a2ce10; +L_0x2a2cf50 .delay (10000,10000,10000) L_0x2a2cf50/d; +v0x2694440_0 .net "S0", 0 0, L_0x2a2c4d0; 1 drivers +v0x2694500_0 .net "S1", 0 0, L_0x2a2c600; 1 drivers +v0x2699000_0 .net "in0", 0 0, L_0x2a2c730; 1 drivers +v0x26990a0_0 .net "in1", 0 0, L_0x2a2c7d0; 1 drivers +v0x2699120_0 .net "in2", 0 0, L_0x2a2c870; 1 drivers +v0x26991c0_0 .net "in3", 0 0, L_0x2a2c960; 1 drivers +v0x269dcb0_0 .net "nS0", 0 0, L_0x2a2ba40; 1 drivers +v0x269dd50_0 .net "nS1", 0 0, L_0x2a2bb30; 1 drivers +v0x269ddf0_0 .net "out", 0 0, L_0x2a2cf50; 1 drivers +v0x26b5a50_0 .net "out0", 0 0, L_0x2a2bbd0; 1 drivers +v0x26b5af0_0 .net "out1", 0 0, L_0x2a2cc30; 1 drivers +v0x26b5b90_0 .net "out2", 0 0, L_0x2a2cd20; 1 drivers +v0x26ba700_0 .net "out3", 0 0, L_0x2a2ce10; 1 drivers +S_0x267c610 .scope module, "TwoMux" "TwoInMux" 3 401, 3 109, S_0x2677960; + .timescale -9 -12; +L_0x2a2ca50/d .functor NOT 1, L_0x2a2dc70, C4<0>, C4<0>, C4<0>; +L_0x2a2ca50 .delay (10000,10000,10000) L_0x2a2ca50/d; +L_0x2a2cb40/d .functor AND 1, L_0x2a2d200, L_0x2a2ca50, C4<1>, C4<1>; +L_0x2a2cb40 .delay (20000,20000,20000) L_0x2a2cb40/d; +L_0x2a2d9a0/d .functor AND 1, L_0x2a2d2f0, L_0x2a2dc70, C4<1>, C4<1>; +L_0x2a2d9a0 .delay (20000,20000,20000) L_0x2a2d9a0/d; +L_0x2a2da90/d .functor OR 1, L_0x2a2cb40, L_0x2a2d9a0, C4<0>, C4<0>; +L_0x2a2da90 .delay (20000,20000,20000) L_0x2a2da90/d; +v0x267c700_0 .net "S", 0 0, L_0x2a2dc70; 1 drivers +v0x267c7a0_0 .net "in0", 0 0, L_0x2a2d200; 1 drivers +v0x2677ad0_0 .net "in1", 0 0, L_0x2a2d2f0; 1 drivers +v0x2672e10_0 .net "nS", 0 0, L_0x2a2ca50; 1 drivers +v0x26812c0_0 .net "out0", 0 0, L_0x2a2cb40; 1 drivers +v0x2681360_0 .net "out1", 0 0, L_0x2a2d9a0; 1 drivers +v0x2681440_0 .net "outfinal", 0 0, L_0x2a2da90; 1 drivers +S_0x2456cf0 .scope generate, "muxbits[12]" "muxbits[12]" 3 397, 3 397, S_0x25e6a40; + .timescale -9 -12; +P_0x2793248 .param/l "i" 3 397, +C4<01100>; +L_0x2a2fe10/d .functor OR 1, L_0x2a2ff50, L_0x2a2fff0, C4<0>, C4<0>; +L_0x2a2fe10 .delay (20000,20000,20000) L_0x2a2fe10/d; +v0x2672cb0_0 .net *"_s15", 0 0, L_0x2a2ff50; 1 drivers +v0x2672d70_0 .net *"_s16", 0 0, L_0x2a2fff0; 1 drivers +S_0x2499b90 .scope module, "ZeroMux" "FourInMux" 3 399, 3 125, S_0x2456cf0; + .timescale -9 -12; +L_0x2a2d750/d .functor NOT 1, L_0x2a2dd10, C4<0>, C4<0>, C4<0>; +L_0x2a2d750 .delay (10000,10000,10000) L_0x2a2d750/d; +L_0x2a2d840/d .functor NOT 1, L_0x2a2de40, C4<0>, C4<0>, C4<0>; +L_0x2a2d840 .delay (10000,10000,10000) L_0x2a2d840/d; +L_0x2a2e450/d .functor NAND 1, L_0x2a2d750, L_0x2a2d840, L_0x2a2df70, C4<1>; +L_0x2a2e450 .delay (10000,10000,10000) L_0x2a2e450/d; +L_0x2a2e590/d .functor NAND 1, L_0x2a2dd10, L_0x2a2d840, L_0x2a2e010, C4<1>; +L_0x2a2e590 .delay (10000,10000,10000) L_0x2a2e590/d; +L_0x2a2e680/d .functor NAND 1, L_0x2a2d750, L_0x2a2de40, L_0x2a2e0b0, C4<1>; +L_0x2a2e680 .delay (10000,10000,10000) L_0x2a2e680/d; +L_0x2a2e770/d .functor NAND 1, L_0x2a2dd10, L_0x2a2de40, L_0x2a2e1a0, C4<1>; +L_0x2a2e770 .delay (10000,10000,10000) L_0x2a2e770/d; +L_0x2a2e850/d .functor NAND 1, L_0x2a2e450, L_0x2a2e590, L_0x2a2e680, L_0x2a2e770; +L_0x2a2e850 .delay (10000,10000,10000) L_0x2a2e850/d; +v0x2499c80_0 .net "S0", 0 0, L_0x2a2dd10; 1 drivers +v0x249e7a0_0 .net "S1", 0 0, L_0x2a2de40; 1 drivers +v0x249e840_0 .net "in0", 0 0, L_0x2a2df70; 1 drivers +v0x249e8e0_0 .net "in1", 0 0, L_0x2a2e010; 1 drivers +v0x2656260_0 .net "in2", 0 0, L_0x2a2e0b0; 1 drivers +v0x2656300_0 .net "in3", 0 0, L_0x2a2e1a0; 1 drivers +v0x26563a0_0 .net "nS0", 0 0, L_0x2a2d750; 1 drivers +v0x265af10_0 .net "nS1", 0 0, L_0x2a2d840; 1 drivers +v0x265afb0_0 .net "out", 0 0, L_0x2a2e850; 1 drivers +v0x265b050_0 .net "out0", 0 0, L_0x2a2e450; 1 drivers +v0x265fbc0_0 .net "out1", 0 0, L_0x2a2e590; 1 drivers +v0x265fc60_0 .net "out2", 0 0, L_0x2a2e680; 1 drivers +v0x265fd70_0 .net "out3", 0 0, L_0x2a2e770; 1 drivers +S_0x2478400 .scope module, "OneMux" "FourInMux" 3 400, 3 125, S_0x2456cf0; + .timescale -9 -12; +L_0x2a2e290/d .functor NOT 1, L_0x2a2f9c0, C4<0>, C4<0>, C4<0>; +L_0x2a2e290 .delay (10000,10000,10000) L_0x2a2e290/d; +L_0x2a2e380/d .functor NOT 1, L_0x2a2eb00, C4<0>, C4<0>, C4<0>; +L_0x2a2e380 .delay (10000,10000,10000) L_0x2a2e380/d; +L_0x2a2f280/d .functor NAND 1, L_0x2a2e290, L_0x2a2e380, L_0x2a2ec30, C4<1>; +L_0x2a2f280 .delay (10000,10000,10000) L_0x2a2f280/d; +L_0x2a2f3c0/d .functor NAND 1, L_0x2a2f9c0, L_0x2a2e380, L_0x2a2ecd0, C4<1>; +L_0x2a2f3c0 .delay (10000,10000,10000) L_0x2a2f3c0/d; +L_0x2a2f4b0/d .functor NAND 1, L_0x2a2e290, L_0x2a2eb00, L_0x2a2ed70, C4<1>; +L_0x2a2f4b0 .delay (10000,10000,10000) L_0x2a2f4b0/d; +L_0x2a2f5a0/d .functor NAND 1, L_0x2a2f9c0, L_0x2a2eb00, L_0x2a2ee60, C4<1>; +L_0x2a2f5a0 .delay (10000,10000,10000) L_0x2a2f5a0/d; +L_0x2a2f710/d .functor NAND 1, L_0x2a2f280, L_0x2a2f3c0, L_0x2a2f4b0, L_0x2a2f5a0; +L_0x2a2f710 .delay (10000,10000,10000) L_0x2a2f710/d; +v0x24784f0_0 .net "S0", 0 0, L_0x2a2f9c0; 1 drivers +v0x24785b0_0 .net "S1", 0 0, L_0x2a2eb00; 1 drivers +v0x247d0b0_0 .net "in0", 0 0, L_0x2a2ec30; 1 drivers +v0x247d130_0 .net "in1", 0 0, L_0x2a2ecd0; 1 drivers +v0x247d1b0_0 .net "in2", 0 0, L_0x2a2ed70; 1 drivers +v0x247d250_0 .net "in3", 0 0, L_0x2a2ee60; 1 drivers +v0x2490190_0 .net "nS0", 0 0, L_0x2a2e290; 1 drivers +v0x2490230_0 .net "nS1", 0 0, L_0x2a2e380; 1 drivers +v0x24902d0_0 .net "out", 0 0, L_0x2a2f710; 1 drivers +v0x2494e40_0 .net "out0", 0 0, L_0x2a2f280; 1 drivers +v0x2494ee0_0 .net "out1", 0 0, L_0x2a2f3c0; 1 drivers +v0x2494f80_0 .net "out2", 0 0, L_0x2a2f4b0; 1 drivers +v0x2499af0_0 .net "out3", 0 0, L_0x2a2f5a0; 1 drivers +S_0x2456e20 .scope module, "TwoMux" "TwoInMux" 3 401, 3 109, S_0x2456cf0; + .timescale -9 -12; +L_0x2a2ef50/d .functor NOT 1, L_0x2a2faf0, C4<0>, C4<0>, C4<0>; +L_0x2a2ef50 .delay (10000,10000,10000) L_0x2a2ef50/d; +L_0x2a2f040/d .functor AND 1, L_0x2a2fb90, L_0x2a2ef50, C4<1>, C4<1>; +L_0x2a2f040 .delay (20000,20000,20000) L_0x2a2f040/d; +L_0x2a2f130/d .functor AND 1, L_0x2a2fc80, L_0x2a2faf0, C4<1>, C4<1>; +L_0x2a2f130 .delay (20000,20000,20000) L_0x2a2f130/d; +L_0x2a2f220/d .functor OR 1, L_0x2a2f040, L_0x2a2f130, C4<0>, C4<0>; +L_0x2a2f220 .delay (20000,20000,20000) L_0x2a2f220/d; +v0x245b9a0_0 .net "S", 0 0, L_0x2a2faf0; 1 drivers +v0x245ba20_0 .net "in0", 0 0, L_0x2a2fb90; 1 drivers +v0x245bac0_0 .net "in1", 0 0, L_0x2a2fc80; 1 drivers +v0x245bb60_0 .net "nS", 0 0, L_0x2a2ef50; 1 drivers +v0x2473750_0 .net "out0", 0 0, L_0x2a2f040; 1 drivers +v0x24737f0_0 .net "out1", 0 0, L_0x2a2f130; 1 drivers +v0x2473890_0 .net "outfinal", 0 0, L_0x2a2f220; 1 drivers +S_0x27a0f70 .scope generate, "muxbits[13]" "muxbits[13]" 3 397, 3 397, S_0x25e6a40; + .timescale -9 -12; +P_0x2779af8 .param/l "i" 3 397, +C4<01101>; +L_0x2a32410/d .functor OR 1, L_0x2a32550, L_0x2a325f0, C4<0>, C4<0>; +L_0x2a32410 .delay (20000,20000,20000) L_0x2a32410/d; +v0x24520c0_0 .net *"_s15", 0 0, L_0x2a32550; 1 drivers +v0x2452180_0 .net *"_s16", 0 0, L_0x2a325f0; 1 drivers +S_0x273cf00 .scope module, "ZeroMux" "FourInMux" 3 399, 3 125, S_0x27a0f70; + .timescale -9 -12; +L_0x2a300e0/d .functor NOT 1, L_0x2a31350, C4<0>, C4<0>, C4<0>; +L_0x2a300e0 .delay (10000,10000,10000) L_0x2a300e0/d; +L_0x2a301d0/d .functor NOT 1, L_0x2a30420, C4<0>, C4<0>, C4<0>; +L_0x2a301d0 .delay (10000,10000,10000) L_0x2a301d0/d; +L_0x2a30c10/d .functor NAND 1, L_0x2a300e0, L_0x2a301d0, L_0x2a30550, C4<1>; +L_0x2a30c10 .delay (10000,10000,10000) L_0x2a30c10/d; +L_0x2a30d50/d .functor NAND 1, L_0x2a31350, L_0x2a301d0, L_0x2a305f0, C4<1>; +L_0x2a30d50 .delay (10000,10000,10000) L_0x2a30d50/d; +L_0x2a30e40/d .functor NAND 1, L_0x2a300e0, L_0x2a30420, L_0x2a30690, C4<1>; +L_0x2a30e40 .delay (10000,10000,10000) L_0x2a30e40/d; +L_0x2a30f30/d .functor NAND 1, L_0x2a31350, L_0x2a30420, L_0x2a30780, C4<1>; +L_0x2a30f30 .delay (10000,10000,10000) L_0x2a30f30/d; +L_0x2a310a0/d .functor NAND 1, L_0x2a30c10, L_0x2a30d50, L_0x2a30e40, L_0x2a30f30; +L_0x2a310a0 .delay (10000,10000,10000) L_0x2a310a0/d; +v0x273cff0_0 .net "S0", 0 0, L_0x2a31350; 1 drivers +v0x273d0b0_0 .net "S1", 0 0, L_0x2a30420; 1 drivers +v0x2430980_0 .net "in0", 0 0, L_0x2a30550; 1 drivers +v0x2430a00_0 .net "in1", 0 0, L_0x2a305f0; 1 drivers +v0x2430a80_0 .net "in2", 0 0, L_0x2a30690; 1 drivers +v0x2430b20_0 .net "in3", 0 0, L_0x2a30780; 1 drivers +v0x2435630_0 .net "nS0", 0 0, L_0x2a300e0; 1 drivers +v0x24356d0_0 .net "nS1", 0 0, L_0x2a301d0; 1 drivers +v0x2435770_0 .net "out", 0 0, L_0x2a310a0; 1 drivers +v0x243a2e0_0 .net "out0", 0 0, L_0x2a30c10; 1 drivers +v0x243a380_0 .net "out1", 0 0, L_0x2a30d50; 1 drivers +v0x243a420_0 .net "out2", 0 0, L_0x2a30e40; 1 drivers +v0x2452040_0 .net "out3", 0 0, L_0x2a30f30; 1 drivers +S_0x27aa2f0 .scope module, "OneMux" "FourInMux" 3 400, 3 125, S_0x27a0f70; + .timescale -9 -12; +L_0x2a30870/d .functor NOT 1, L_0x2a31480, C4<0>, C4<0>, C4<0>; +L_0x2a30870 .delay (10000,10000,10000) L_0x2a30870/d; +L_0x2a30920/d .functor NOT 1, L_0x2a315b0, C4<0>, C4<0>, C4<0>; +L_0x2a30920 .delay (10000,10000,10000) L_0x2a30920/d; +L_0x2a309c0/d .functor NAND 1, L_0x2a30870, L_0x2a30920, L_0x2a316e0, C4<1>; +L_0x2a309c0 .delay (10000,10000,10000) L_0x2a309c0/d; +L_0x2a30b00/d .functor NAND 1, L_0x2a31480, L_0x2a30920, L_0x2a31780, C4<1>; +L_0x2a30b00 .delay (10000,10000,10000) L_0x2a30b00/d; +L_0x2a31ca0/d .functor NAND 1, L_0x2a30870, L_0x2a315b0, L_0x2a31820, C4<1>; +L_0x2a31ca0 .delay (10000,10000,10000) L_0x2a31ca0/d; +L_0x2a31dc0/d .functor NAND 1, L_0x2a31480, L_0x2a315b0, L_0x2a31910, C4<1>; +L_0x2a31dc0 .delay (10000,10000,10000) L_0x2a31dc0/d; +L_0x2a31f30/d .functor NAND 1, L_0x2a309c0, L_0x2a30b00, L_0x2a31ca0, L_0x2a31dc0; +L_0x2a31f30 .delay (10000,10000,10000) L_0x2a31f30/d; +v0x27aa3e0_0 .net "S0", 0 0, L_0x2a31480; 1 drivers +v0x27ac7f0_0 .net "S1", 0 0, L_0x2a315b0; 1 drivers +v0x27ac890_0 .net "in0", 0 0, L_0x2a316e0; 1 drivers +v0x27ac930_0 .net "in1", 0 0, L_0x2a31780; 1 drivers +v0x27aecf0_0 .net "in2", 0 0, L_0x2a31820; 1 drivers +v0x27aed90_0 .net "in3", 0 0, L_0x2a31910; 1 drivers +v0x27aee30_0 .net "nS0", 0 0, L_0x2a30870; 1 drivers +v0x22fb980_0 .net "nS1", 0 0, L_0x2a30920; 1 drivers +v0x22fba00_0 .net "out", 0 0, L_0x2a31f30; 1 drivers +v0x22fbaa0_0 .net "out0", 0 0, L_0x2a309c0; 1 drivers +v0x25128e0_0 .net "out1", 0 0, L_0x2a30b00; 1 drivers +v0x2512980_0 .net "out2", 0 0, L_0x2a31ca0; 1 drivers +v0x2512a20_0 .net "out3", 0 0, L_0x2a31dc0; 1 drivers +S_0x27a33e0 .scope module, "TwoMux" "TwoInMux" 3 401, 3 109, S_0x27a0f70; + .timescale -9 -12; +L_0x2a31a00/d .functor NOT 1, L_0x2a32c10, C4<0>, C4<0>, C4<0>; +L_0x2a31a00 .delay (10000,10000,10000) L_0x2a31a00/d; +L_0x2a31ab0/d .functor AND 1, L_0x2a321e0, L_0x2a31a00, C4<1>, C4<1>; +L_0x2a31ab0 .delay (20000,20000,20000) L_0x2a31ab0/d; +L_0x2a31ba0/d .functor AND 1, L_0x2a32280, L_0x2a32c10, C4<1>, C4<1>; +L_0x2a31ba0 .delay (20000,20000,20000) L_0x2a31ba0/d; +L_0x2a31c40/d .functor OR 1, L_0x2a31ab0, L_0x2a31ba0, C4<0>, C4<0>; +L_0x2a31c40 .delay (20000,20000,20000) L_0x2a31c40/d; +v0x27a34d0_0 .net "S", 0 0, L_0x2a32c10; 1 drivers +v0x27a58f0_0 .net "in0", 0 0, L_0x2a321e0; 1 drivers +v0x27a5990_0 .net "in1", 0 0, L_0x2a32280; 1 drivers +v0x27a5a30_0 .net "nS", 0 0, L_0x2a31a00; 1 drivers +v0x27a7df0_0 .net "out0", 0 0, L_0x2a31ab0; 1 drivers +v0x27a7e90_0 .net "out1", 0 0, L_0x2a31ba0; 1 drivers +v0x27a7f30_0 .net "outfinal", 0 0, L_0x2a31c40; 1 drivers +S_0x2780860 .scope generate, "muxbits[14]" "muxbits[14]" 3 397, 3 397, S_0x25e6a40; + .timescale -9 -12; +P_0x2765d48 .param/l "i" 3 397, +C4<01110>; +L_0x2a34dc0/d .functor OR 1, L_0x2a34f00, L_0x2a34fa0, C4<0>, C4<0>; +L_0x2a34dc0 .delay (20000,20000,20000) L_0x2a34dc0/d; +v0x279eb00_0 .net *"_s15", 0 0, L_0x2a34f00; 1 drivers +v0x27a0ed0_0 .net *"_s16", 0 0, L_0x2a34fa0; 1 drivers +S_0x2795580 .scope module, "ZeroMux" "FourInMux" 3 399, 3 125, S_0x2780860; + .timescale -9 -12; +L_0x2a326e0/d .functor NOT 1, L_0x2a32cb0, C4<0>, C4<0>, C4<0>; +L_0x2a326e0 .delay (10000,10000,10000) L_0x2a326e0/d; +L_0x2a327d0/d .functor NOT 1, L_0x2a32de0, C4<0>, C4<0>, C4<0>; +L_0x2a327d0 .delay (10000,10000,10000) L_0x2a327d0/d; +L_0x2a32870/d .functor NAND 1, L_0x2a326e0, L_0x2a327d0, L_0x2a32f10, C4<1>; +L_0x2a32870 .delay (10000,10000,10000) L_0x2a32870/d; +L_0x2a329b0/d .functor NAND 1, L_0x2a32cb0, L_0x2a327d0, L_0x2a32fb0, C4<1>; +L_0x2a329b0 .delay (10000,10000,10000) L_0x2a329b0/d; +L_0x2a335d0/d .functor NAND 1, L_0x2a326e0, L_0x2a32de0, L_0x2a33050, C4<1>; +L_0x2a335d0 .delay (10000,10000,10000) L_0x2a335d0/d; +L_0x2a336c0/d .functor NAND 1, L_0x2a32cb0, L_0x2a32de0, L_0x2a33140, C4<1>; +L_0x2a336c0 .delay (10000,10000,10000) L_0x2a336c0/d; +L_0x2a33830/d .functor NAND 1, L_0x2a32870, L_0x2a329b0, L_0x2a335d0, L_0x2a336c0; +L_0x2a33830 .delay (10000,10000,10000) L_0x2a33830/d; +v0x2795670_0 .net "S0", 0 0, L_0x2a32cb0; 1 drivers +v0x27931c0_0 .net "S1", 0 0, L_0x2a32de0; 1 drivers +v0x2797a90_0 .net "in0", 0 0, L_0x2a32f10; 1 drivers +v0x2797b10_0 .net "in1", 0 0, L_0x2a32fb0; 1 drivers +v0x2797b90_0 .net "in2", 0 0, L_0x2a33050; 1 drivers +v0x2799fa0_0 .net "in3", 0 0, L_0x2a33140; 1 drivers +v0x279a040_0 .net "nS0", 0 0, L_0x2a326e0; 1 drivers +v0x279a0e0_0 .net "nS1", 0 0, L_0x2a327d0; 1 drivers +v0x279c4b0_0 .net "out", 0 0, L_0x2a33830; 1 drivers +v0x279c530_0 .net "out0", 0 0, L_0x2a32870; 1 drivers +v0x279c5d0_0 .net "out1", 0 0, L_0x2a329b0; 1 drivers +v0x279e9c0_0 .net "out2", 0 0, L_0x2a335d0; 1 drivers +v0x279ea60_0 .net "out3", 0 0, L_0x2a336c0; 1 drivers +S_0x2789c80 .scope module, "OneMux" "FourInMux" 3 400, 3 125, S_0x2780860; + .timescale -9 -12; +L_0x2a33230/d .functor NOT 1, L_0x2a34970, C4<0>, C4<0>, C4<0>; +L_0x2a33230 .delay (10000,10000,10000) L_0x2a33230/d; +L_0x2a33320/d .functor NOT 1, L_0x2a33ae0, C4<0>, C4<0>, C4<0>; +L_0x2a33320 .delay (10000,10000,10000) L_0x2a33320/d; +L_0x2a333c0/d .functor NAND 1, L_0x2a33230, L_0x2a33320, L_0x2a33c10, C4<1>; +L_0x2a333c0 .delay (10000,10000,10000) L_0x2a333c0/d; +L_0x2a343b0/d .functor NAND 1, L_0x2a34970, L_0x2a33320, L_0x2a33cb0, C4<1>; +L_0x2a343b0 .delay (10000,10000,10000) L_0x2a343b0/d; +L_0x2a34460/d .functor NAND 1, L_0x2a33230, L_0x2a33ae0, L_0x2a33d50, C4<1>; +L_0x2a34460 .delay (10000,10000,10000) L_0x2a34460/d; +L_0x2a34550/d .functor NAND 1, L_0x2a34970, L_0x2a33ae0, L_0x2a33e40, C4<1>; +L_0x2a34550 .delay (10000,10000,10000) L_0x2a34550/d; +L_0x2a346c0/d .functor NAND 1, L_0x2a333c0, L_0x2a343b0, L_0x2a34460, L_0x2a34550; +L_0x2a346c0 .delay (10000,10000,10000) L_0x2a346c0/d; +v0x2789d70_0 .net "S0", 0 0, L_0x2a34970; 1 drivers +v0x27878c0_0 .net "S1", 0 0, L_0x2a33ae0; 1 drivers +v0x278c180_0 .net "in0", 0 0, L_0x2a33c10; 1 drivers +v0x278c220_0 .net "in1", 0 0, L_0x2a33cb0; 1 drivers +v0x278c2a0_0 .net "in2", 0 0, L_0x2a33d50; 1 drivers +v0x278e680_0 .net "in3", 0 0, L_0x2a33e40; 1 drivers +v0x278e720_0 .net "nS0", 0 0, L_0x2a33230; 1 drivers +v0x278e7c0_0 .net "nS1", 0 0, L_0x2a33320; 1 drivers +v0x2790b80_0 .net "out", 0 0, L_0x2a346c0; 1 drivers +v0x2790c00_0 .net "out0", 0 0, L_0x2a333c0; 1 drivers +v0x2790ca0_0 .net "out1", 0 0, L_0x2a343b0; 1 drivers +v0x2793080_0 .net "out2", 0 0, L_0x2a34460; 1 drivers +v0x2793120_0 .net "out3", 0 0, L_0x2a34550; 1 drivers +S_0x2782d70 .scope module, "TwoMux" "TwoInMux" 3 401, 3 109, S_0x2780860; + .timescale -9 -12; +L_0x2a33f30/d .functor NOT 1, L_0x2a34aa0, C4<0>, C4<0>, C4<0>; +L_0x2a33f30 .delay (10000,10000,10000) L_0x2a33f30/d; +L_0x2a34020/d .functor AND 1, L_0x2a34b40, L_0x2a33f30, C4<1>, C4<1>; +L_0x2a34020 .delay (20000,20000,20000) L_0x2a34020/d; +L_0x2a34110/d .functor AND 1, L_0x2a34c30, L_0x2a34aa0, C4<1>, C4<1>; +L_0x2a34110 .delay (20000,20000,20000) L_0x2a34110/d; +L_0x2a34200/d .functor OR 1, L_0x2a34020, L_0x2a34110, C4<0>, C4<0>; +L_0x2a34200 .delay (20000,20000,20000) L_0x2a34200/d; +v0x2782e60_0 .net "S", 0 0, L_0x2a34aa0; 1 drivers +v0x2780990_0 .net "in0", 0 0, L_0x2a34b40; 1 drivers +v0x2785280_0 .net "in1", 0 0, L_0x2a34c30; 1 drivers +v0x2785320_0 .net "nS", 0 0, L_0x2a33f30; 1 drivers +v0x27853a0_0 .net "out0", 0 0, L_0x2a34020; 1 drivers +v0x2787780_0 .net "out1", 0 0, L_0x2a34110; 1 drivers +v0x2787820_0 .net "outfinal", 0 0, L_0x2a34200; 1 drivers +S_0x2752b00 .scope generate, "muxbits[15]" "muxbits[15]" 3 397, 3 397, S_0x25e6a40; + .timescale -9 -12; +P_0x2745328 .param/l "i" 3 397, +C4<01111>; +L_0x2a375d0/d .functor OR 1, L_0x2a37710, L_0x2a377b0, C4<0>, C4<0>; +L_0x2a375d0 .delay (20000,20000,20000) L_0x2a375d0/d; +v0x277e3f0_0 .net *"_s15", 0 0, L_0x2a37710; 1 drivers +v0x277e4b0_0 .net *"_s16", 0 0, L_0x2a377b0; 1 drivers +S_0x2772ab0 .scope module, "ZeroMux" "FourInMux" 3 399, 3 125, S_0x2752b00; + .timescale -9 -12; +L_0x2a35090/d .functor NOT 1, L_0x2a36340, C4<0>, C4<0>, C4<0>; +L_0x2a35090 .delay (10000,10000,10000) L_0x2a35090/d; +L_0x2a35180/d .functor NOT 1, L_0x2a35440, C4<0>, C4<0>, C4<0>; +L_0x2a35180 .delay (10000,10000,10000) L_0x2a35180/d; +L_0x2a35220/d .functor NAND 1, L_0x2a35090, L_0x2a35180, L_0x2a35570, C4<1>; +L_0x2a35220 .delay (10000,10000,10000) L_0x2a35220/d; +L_0x2a34340/d .functor NAND 1, L_0x2a36340, L_0x2a35180, L_0x2986f60, C4<1>; +L_0x2a34340 .delay (10000,10000,10000) L_0x2a34340/d; +L_0x2a35dd0/d .functor NAND 1, L_0x2a35090, L_0x2a35440, L_0x2987000, C4<1>; +L_0x2a35dd0 .delay (10000,10000,10000) L_0x2a35dd0/d; +L_0x2a35f20/d .functor NAND 1, L_0x2a36340, L_0x2a35440, L_0x29870f0, C4<1>; +L_0x2a35f20 .delay (10000,10000,10000) L_0x2a35f20/d; +L_0x2a36090/d .functor NAND 1, L_0x2a35220, L_0x2a34340, L_0x2a35dd0, L_0x2a35f20; +L_0x2a36090 .delay (10000,10000,10000) L_0x2a36090/d; +v0x2774f10_0 .net "S0", 0 0, L_0x2a36340; 1 drivers +v0x2774fd0_0 .net "S1", 0 0, L_0x2a35440; 1 drivers +v0x2775070_0 .net "in0", 0 0, L_0x2a35570; 1 drivers +v0x2777420_0 .net "in1", 0 0, L_0x2986f60; 1 drivers +v0x27774a0_0 .net "in2", 0 0, L_0x2987000; 1 drivers +v0x2777540_0 .net "in3", 0 0, L_0x29870f0; 1 drivers +v0x2779930_0 .net "nS0", 0 0, L_0x2a35090; 1 drivers +v0x27799d0_0 .net "nS1", 0 0, L_0x2a35180; 1 drivers +v0x2779a70_0 .net "out", 0 0, L_0x2a36090; 1 drivers +v0x277be40_0 .net "out0", 0 0, L_0x2a35220; 1 drivers +v0x277bec0_0 .net "out1", 0 0, L_0x2a34340; 1 drivers +v0x277bf60_0 .net "out2", 0 0, L_0x2a35dd0; 1 drivers +v0x277e350_0 .net "out3", 0 0, L_0x2a35f20; 1 drivers +S_0x27b1290 .scope module, "OneMux" "FourInMux" 3 400, 3 125, S_0x2752b00; + .timescale -9 -12; +L_0x29871e0/d .functor NOT 1, L_0x2a36470, C4<0>, C4<0>, C4<0>; +L_0x29871e0 .delay (10000,10000,10000) L_0x29871e0/d; +L_0x29872d0/d .functor NOT 1, L_0x2a365a0, C4<0>, C4<0>, C4<0>; +L_0x29872d0 .delay (10000,10000,10000) L_0x29872d0/d; +L_0x2a35610/d .functor NAND 1, L_0x29871e0, L_0x29872d0, L_0x2a366d0, C4<1>; +L_0x2a35610 .delay (10000,10000,10000) L_0x2a35610/d; +L_0x2a35750/d .functor NAND 1, L_0x2a36470, L_0x29872d0, L_0x29e8f40, C4<1>; +L_0x2a35750 .delay (10000,10000,10000) L_0x2a35750/d; +L_0x2a35840/d .functor NAND 1, L_0x29871e0, L_0x2a365a0, L_0x29e8fe0, C4<1>; +L_0x2a35840 .delay (10000,10000,10000) L_0x2a35840/d; +L_0x2a35960/d .functor NAND 1, L_0x2a36470, L_0x2a365a0, L_0x29e90d0, C4<1>; +L_0x2a35960 .delay (10000,10000,10000) L_0x2a35960/d; +L_0x2a35ad0/d .functor NAND 1, L_0x2a35610, L_0x2a35750, L_0x2a35840, L_0x2a35960; +L_0x2a35ad0 .delay (10000,10000,10000) L_0x2a35ad0/d; +v0x2769560_0 .net "S0", 0 0, L_0x2a36470; 1 drivers +v0x2769620_0 .net "S1", 0 0, L_0x2a365a0; 1 drivers +v0x27696c0_0 .net "in0", 0 0, L_0x2a366d0; 1 drivers +v0x276bb10_0 .net "in1", 0 0, L_0x29e8f40; 1 drivers +v0x276bb90_0 .net "in2", 0 0, L_0x29e8fe0; 1 drivers +v0x276bc30_0 .net "in3", 0 0, L_0x29e90d0; 1 drivers +v0x276e010_0 .net "nS0", 0 0, L_0x29871e0; 1 drivers +v0x276e0b0_0 .net "nS1", 0 0, L_0x29872d0; 1 drivers +v0x276e150_0 .net "out", 0 0, L_0x2a35ad0; 1 drivers +v0x2770510_0 .net "out0", 0 0, L_0x2a35610; 1 drivers +v0x2770590_0 .net "out1", 0 0, L_0x2a35750; 1 drivers +v0x2770630_0 .net "out2", 0 0, L_0x2a35840; 1 drivers +v0x2772a10_0 .net "out3", 0 0, L_0x2a35960; 1 drivers +S_0x2764580 .scope module, "TwoMux" "TwoInMux" 3 401, 3 109, S_0x2752b00; + .timescale -9 -12; +L_0x29e91c0/d .functor NOT 1, L_0x2a36a90, C4<0>, C4<0>, C4<0>; +L_0x29e91c0 .delay (10000,10000,10000) L_0x29e91c0/d; +L_0x29e92b0/d .functor AND 1, L_0x2a36b30, L_0x29e91c0, C4<1>, C4<1>; +L_0x29e92b0 .delay (20000,20000,20000) L_0x29e92b0/d; +L_0x2a367c0/d .functor AND 1, L_0x2a36c20, L_0x2a36a90, C4<1>, C4<1>; +L_0x2a367c0 .delay (20000,20000,20000) L_0x2a367c0/d; +L_0x2a368b0/d .functor OR 1, L_0x29e92b0, L_0x2a367c0, C4<0>, C4<0>; +L_0x2a368b0 .delay (20000,20000,20000) L_0x2a368b0/d; +v0x2764670_0 .net "S", 0 0, L_0x2a36a90; 1 drivers +v0x2751640_0 .net "in0", 0 0, L_0x2a36b30; 1 drivers +v0x2752c30_0 .net "in1", 0 0, L_0x2a36c20; 1 drivers +v0x2765b80_0 .net "nS", 0 0, L_0x29e91c0; 1 drivers +v0x2765c00_0 .net "out0", 0 0, L_0x29e92b0; 1 drivers +v0x2765ca0_0 .net "out1", 0 0, L_0x2a367c0; 1 drivers +v0x27b11f0_0 .net "outfinal", 0 0, L_0x2a368b0; 1 drivers +S_0x26bb0a0 .scope generate, "muxbits[16]" "muxbits[16]" 3 397, 3 397, S_0x25e6a40; + .timescale -9 -12; +P_0x23ae358 .param/l "i" 3 397, +C4<010000>; +L_0x2a39d70/d .functor OR 1, L_0x2a3ad30, L_0x2a26360, C4<0>, C4<0>; +L_0x2a39d70 .delay (20000,20000,20000) L_0x2a39d70/d; +v0x2751500_0 .net *"_s15", 0 0, L_0x2a3ad30; 1 drivers +v0x27515a0_0 .net *"_s16", 0 0, L_0x2a26360; 1 drivers +S_0x274a880 .scope module, "ZeroMux" "FourInMux" 3 399, 3 125, S_0x26bb0a0; + .timescale -9 -12; +L_0x2a378a0/d .functor NOT 1, L_0x2a38770, C4<0>, C4<0>, C4<0>; +L_0x2a378a0 .delay (10000,10000,10000) L_0x2a378a0/d; +L_0x2a37990/d .functor NOT 1, L_0x2a388a0, C4<0>, C4<0>, C4<0>; +L_0x2a37990 .delay (10000,10000,10000) L_0x2a37990/d; +L_0x2a37a30/d .functor NAND 1, L_0x2a378a0, L_0x2a37990, L_0x2a389d0, C4<1>; +L_0x2a37a30 .delay (10000,10000,10000) L_0x2a37a30/d; +L_0x2a37b70/d .functor NAND 1, L_0x2a38770, L_0x2a37990, L_0x2a38a70, C4<1>; +L_0x2a37b70 .delay (10000,10000,10000) L_0x2a37b70/d; +L_0x2a37c60/d .functor NAND 1, L_0x2a378a0, L_0x2a388a0, L_0x2a38b10, C4<1>; +L_0x2a37c60 .delay (10000,10000,10000) L_0x2a37c60/d; +L_0x2a37db0/d .functor NAND 1, L_0x2a38770, L_0x2a388a0, L_0x2a38c00, C4<1>; +L_0x2a37db0 .delay (10000,10000,10000) L_0x2a37db0/d; +L_0x2a39150/d .functor NAND 1, L_0x2a37a30, L_0x2a37b70, L_0x2a37c60, L_0x2a37db0; +L_0x2a39150 .delay (10000,10000,10000) L_0x2a39150/d; +v0x274a970_0 .net "S0", 0 0, L_0x2a38770; 1 drivers +v0x274be00_0 .net "S1", 0 0, L_0x2a388a0; 1 drivers +v0x274bea0_0 .net "in0", 0 0, L_0x2a389d0; 1 drivers +v0x274bf40_0 .net "in1", 0 0, L_0x2a38a70; 1 drivers +v0x274d400_0 .net "in2", 0 0, L_0x2a38b10; 1 drivers +v0x274d4a0_0 .net "in3", 0 0, L_0x2a38c00; 1 drivers +v0x274d540_0 .net "nS0", 0 0, L_0x2a378a0; 1 drivers +v0x274e980_0 .net "nS1", 0 0, L_0x2a37990; 1 drivers +v0x274ea00_0 .net "out", 0 0, L_0x2a39150; 1 drivers +v0x274eaa0_0 .net "out0", 0 0, L_0x2a37a30; 1 drivers +v0x274ff80_0 .net "out1", 0 0, L_0x2a37b70; 1 drivers +v0x2750020_0 .net "out2", 0 0, L_0x2a37c60; 1 drivers +v0x27500c0_0 .net "out3", 0 0, L_0x2a37db0; 1 drivers +S_0x267cfb0 .scope module, "OneMux" "FourInMux" 3 400, 3 125, S_0x26bb0a0; + .timescale -9 -12; +L_0x2a38cf0/d .functor NOT 1, L_0x2a3a260, C4<0>, C4<0>, C4<0>; +L_0x2a38cf0 .delay (10000,10000,10000) L_0x2a38cf0/d; +L_0x2a38da0/d .functor NOT 1, L_0x2a393d0, C4<0>, C4<0>, C4<0>; +L_0x2a38da0 .delay (10000,10000,10000) L_0x2a38da0/d; +L_0x2a38e00/d .functor NAND 1, L_0x2a38cf0, L_0x2a38da0, L_0x2a39500, C4<1>; +L_0x2a38e00 .delay (10000,10000,10000) L_0x2a38e00/d; +L_0x2a38f40/d .functor NAND 1, L_0x2a3a260, L_0x2a38da0, L_0x2a395a0, C4<1>; +L_0x2a38f40 .delay (10000,10000,10000) L_0x2a38f40/d; +L_0x2a39030/d .functor NAND 1, L_0x2a38cf0, L_0x2a393d0, L_0x2a39640, C4<1>; +L_0x2a39030 .delay (10000,10000,10000) L_0x2a39030/d; +L_0x2a39e40/d .functor NAND 1, L_0x2a3a260, L_0x2a393d0, L_0x2a39730, C4<1>; +L_0x2a39e40 .delay (10000,10000,10000) L_0x2a39e40/d; +L_0x2a39fb0/d .functor NAND 1, L_0x2a38e00, L_0x2a38f40, L_0x2a39030, L_0x2a39e40; +L_0x2a39fb0 .delay (10000,10000,10000) L_0x2a39fb0/d; +v0x267d0a0_0 .net "S0", 0 0, L_0x2a3a260; 1 drivers +v0x2678300_0 .net "S1", 0 0, L_0x2a393d0; 1 drivers +v0x26783a0_0 .net "in0", 0 0, L_0x2a39500; 1 drivers +v0x2673650_0 .net "in1", 0 0, L_0x2a395a0; 1 drivers +v0x2745200_0 .net "in2", 0 0, L_0x2a39640; 1 drivers +v0x27452a0_0 .net "in3", 0 0, L_0x2a39730; 1 drivers +v0x2746700_0 .net "nS0", 0 0, L_0x2a38cf0; 1 drivers +v0x27467a0_0 .net "nS1", 0 0, L_0x2a38da0; 1 drivers +v0x2747d00_0 .net "out", 0 0, L_0x2a39fb0; 1 drivers +v0x2747da0_0 .net "out0", 0 0, L_0x2a38e00; 1 drivers +v0x2749280_0 .net "out1", 0 0, L_0x2a38f40; 1 drivers +v0x2749320_0 .net "out2", 0 0, L_0x2a39030; 1 drivers +v0x27493c0_0 .net "out3", 0 0, L_0x2a39e40; 1 drivers +S_0x26b63f0 .scope module, "TwoMux" "TwoInMux" 3 401, 3 109, S_0x26bb0a0; + .timescale -9 -12; +L_0x2a39820/d .functor NOT 1, L_0x2a39cd0, C4<0>, C4<0>, C4<0>; +L_0x2a39820 .delay (10000,10000,10000) L_0x2a39820/d; +L_0x2a39910/d .functor AND 1, L_0x2a25c20, L_0x2a39820, C4<1>, C4<1>; +L_0x2a39910 .delay (20000,20000,20000) L_0x2a39910/d; +L_0x2a39a00/d .functor AND 1, L_0x2a25d10, L_0x2a39cd0, C4<1>, C4<1>; +L_0x2a39a00 .delay (20000,20000,20000) L_0x2a39a00/d; +L_0x2a39af0/d .functor OR 1, L_0x2a39910, L_0x2a39a00, C4<0>, C4<0>; +L_0x2a39af0 .delay (20000,20000,20000) L_0x2a39af0/d; +v0x26b64e0_0 .net "S", 0 0, L_0x2a39cd0; 1 drivers +v0x269e650_0 .net "in0", 0 0, L_0x2a25c20; 1 drivers +v0x269e6d0_0 .net "in1", 0 0, L_0x2a25d10; 1 drivers +v0x26999a0_0 .net "nS", 0 0, L_0x2a39820; 1 drivers +v0x2699a20_0 .net "out0", 0 0, L_0x2a39910; 1 drivers +v0x2694cf0_0 .net "out1", 0 0, L_0x2a39a00; 1 drivers +v0x2694d90_0 .net "outfinal", 0 0, L_0x2a39af0; 1 drivers +S_0x25f26c0 .scope generate, "muxbits[17]" "muxbits[17]" 3 397, 3 397, S_0x25e6a40; + .timescale -9 -12; +P_0x23d0a18 .param/l "i" 3 397, +C4<010001>; +L_0x2a3d590/d .functor OR 1, L_0x2a3d6d0, L_0x2a3d770, C4<0>, C4<0>; +L_0x2a3d590 .delay (20000,20000,20000) L_0x2a3d590/d; +v0x26bfd50_0 .net *"_s15", 0 0, L_0x2a3d6d0; 1 drivers +v0x26bfe10_0 .net *"_s16", 0 0, L_0x2a3d770; 1 drivers +S_0x25b3ad0 .scope module, "ZeroMux" "FourInMux" 3 399, 3 125, S_0x25f26c0; + .timescale -9 -12; +L_0x2a26450/d .functor NOT 1, L_0x2a3c460, C4<0>, C4<0>, C4<0>; +L_0x2a26450 .delay (10000,10000,10000) L_0x2a26450/d; +L_0x2a3bc80/d .functor NOT 1, L_0x2a3b1f0, C4<0>, C4<0>, C4<0>; +L_0x2a3bc80 .delay (10000,10000,10000) L_0x2a3bc80/d; +L_0x2a3bd20/d .functor NAND 1, L_0x2a26450, L_0x2a3bc80, L_0x2a3b320, C4<1>; +L_0x2a3bd20 .delay (10000,10000,10000) L_0x2a3bd20/d; +L_0x2a3be60/d .functor NAND 1, L_0x2a3c460, L_0x2a3bc80, L_0x2a3b3c0, C4<1>; +L_0x2a3be60 .delay (10000,10000,10000) L_0x2a3be60/d; +L_0x2a3bf50/d .functor NAND 1, L_0x2a26450, L_0x2a3b1f0, L_0x2a3b460, C4<1>; +L_0x2a3bf50 .delay (10000,10000,10000) L_0x2a3bf50/d; +L_0x2a3c040/d .functor NAND 1, L_0x2a3c460, L_0x2a3b1f0, L_0x2a3b550, C4<1>; +L_0x2a3c040 .delay (10000,10000,10000) L_0x2a3c040/d; +L_0x2a3c1b0/d .functor NAND 1, L_0x2a3bd20, L_0x2a3be60, L_0x2a3bf50, L_0x2a3c040; +L_0x2a3c1b0 .delay (10000,10000,10000) L_0x2a3c1b0/d; +v0x25b3bc0_0 .net "S0", 0 0, L_0x2a3c460; 1 drivers +v0x2660560_0 .net "S1", 0 0, L_0x2a3b1f0; 1 drivers +v0x2660600_0 .net "in0", 0 0, L_0x2a3b320; 1 drivers +v0x265b8b0_0 .net "in1", 0 0, L_0x2a3b3c0; 1 drivers +v0x265b930_0 .net "in2", 0 0, L_0x2a3b460; 1 drivers +v0x2656c00_0 .net "in3", 0 0, L_0x2a3b550; 1 drivers +v0x2656ca0_0 .net "nS0", 0 0, L_0x2a26450; 1 drivers +v0x26d7ae0_0 .net "nS1", 0 0, L_0x2a3bc80; 1 drivers +v0x26d7b80_0 .net "out", 0 0, L_0x2a3c1b0; 1 drivers +v0x26d2e70_0 .net "out0", 0 0, L_0x2a3bd20; 1 drivers +v0x26d2f10_0 .net "out1", 0 0, L_0x2a3be60; 1 drivers +v0x2651f90_0 .net "out2", 0 0, L_0x2a3bf50; 1 drivers +v0x2652030_0 .net "out3", 0 0, L_0x2a3c040; 1 drivers +S_0x25d7030 .scope module, "OneMux" "FourInMux" 3 400, 3 125, S_0x25f26c0; + .timescale -9 -12; +L_0x2a3b640/d .functor NOT 1, L_0x2a3c590, C4<0>, C4<0>, C4<0>; +L_0x2a3b640 .delay (10000,10000,10000) L_0x2a3b640/d; +L_0x2a3b730/d .functor NOT 1, L_0x2a3c6c0, C4<0>, C4<0>, C4<0>; +L_0x2a3b730 .delay (10000,10000,10000) L_0x2a3b730/d; +L_0x2a3b7d0/d .functor NAND 1, L_0x2a3b640, L_0x2a3b730, L_0x2a3c7f0, C4<1>; +L_0x2a3b7d0 .delay (10000,10000,10000) L_0x2a3b7d0/d; +L_0x2a3b910/d .functor NAND 1, L_0x2a3c590, L_0x2a3b730, L_0x2a3c890, C4<1>; +L_0x2a3b910 .delay (10000,10000,10000) L_0x2a3b910/d; +L_0x2a3ba00/d .functor NAND 1, L_0x2a3b640, L_0x2a3c6c0, L_0x2a3c930, C4<1>; +L_0x2a3ba00 .delay (10000,10000,10000) L_0x2a3ba00/d; +L_0x2a3bb20/d .functor NAND 1, L_0x2a3c590, L_0x2a3c6c0, L_0x2a3ca20, C4<1>; +L_0x2a3bb20 .delay (10000,10000,10000) L_0x2a3bb20/d; +L_0x2a3d090/d .functor NAND 1, L_0x2a3b7d0, L_0x2a3b910, L_0x2a3ba00, L_0x2a3bb20; +L_0x2a3d090 .delay (10000,10000,10000) L_0x2a3d090/d; +v0x25d7120_0 .net "S0", 0 0, L_0x2a3c590; 1 drivers +v0x25d4f80_0 .net "S1", 0 0, L_0x2a3c6c0; 1 drivers +v0x25d5020_0 .net "in0", 0 0, L_0x2a3c7f0; 1 drivers +v0x25942c0_0 .net "in1", 0 0, L_0x2a3c890; 1 drivers +v0x2594340_0 .net "in2", 0 0, L_0x2a3c930; 1 drivers +v0x25bf710_0 .net "in3", 0 0, L_0x2a3ca20; 1 drivers +v0x25bf7b0_0 .net "nS0", 0 0, L_0x2a3b640; 1 drivers +v0x25bd660_0 .net "nS1", 0 0, L_0x2a3b730; 1 drivers +v0x25bd700_0 .net "out", 0 0, L_0x2a3d090; 1 drivers +v0x25b98f0_0 .net "out0", 0 0, L_0x2a3b7d0; 1 drivers +v0x25b9990_0 .net "out1", 0 0, L_0x2a3b910; 1 drivers +v0x25b7840_0 .net "out2", 0 0, L_0x2a3ba00; 1 drivers +v0x25b78e0_0 .net "out3", 0 0, L_0x2a3bb20; 1 drivers +S_0x25e0bc0 .scope module, "TwoMux" "TwoInMux" 3 401, 3 109, S_0x25f26c0; + .timescale -9 -12; +L_0x2a3cb10/d .functor NOT 1, L_0x2a3de10, C4<0>, C4<0>, C4<0>; +L_0x2a3cb10 .delay (10000,10000,10000) L_0x2a3cb10/d; +L_0x2a3cc00/d .functor AND 1, L_0x2a3d310, L_0x2a3cb10, C4<1>, C4<1>; +L_0x2a3cc00 .delay (20000,20000,20000) L_0x2a3cc00/d; +L_0x2a3ccf0/d .functor AND 1, L_0x2a3d400, L_0x2a3de10, C4<1>, C4<1>; +L_0x2a3ccf0 .delay (20000,20000,20000) L_0x2a3ccf0/d; +L_0x2a3cde0/d .functor OR 1, L_0x2a3cc00, L_0x2a3ccf0, C4<0>, C4<0>; +L_0x2a3cde0 .delay (20000,20000,20000) L_0x2a3cde0/d; +v0x25e0cb0_0 .net "S", 0 0, L_0x2a3de10; 1 drivers +v0x25dce50_0 .net "in0", 0 0, L_0x2a3d310; 1 drivers +v0x25dced0_0 .net "in1", 0 0, L_0x2a3d400; 1 drivers +v0x2596370_0 .net "nS", 0 0, L_0x2a3cb10; 1 drivers +v0x25963f0_0 .net "out0", 0 0, L_0x2a3cc00; 1 drivers +v0x25dada0_0 .net "out1", 0 0, L_0x2a3ccf0; 1 drivers +v0x25dae40_0 .net "outfinal", 0 0, L_0x2a3cde0; 1 drivers +S_0x2641070 .scope generate, "muxbits[18]" "muxbits[18]" 3 397, 3 397, S_0x25e6a40; + .timescale -9 -12; +P_0x23f9588 .param/l "i" 3 397, +C4<010010>; +L_0x2a3fcc0/d .functor OR 1, L_0x2a3fe00, L_0x2a3fea0, C4<0>, C4<0>; +L_0x2a3fcc0 .delay (20000,20000,20000) L_0x2a3fcc0/d; +v0x25f4790_0 .net *"_s15", 0 0, L_0x2a3fe00; 1 drivers +v0x25f4850_0 .net *"_s16", 0 0, L_0x2a3fea0; 1 drivers +S_0x2615c40 .scope module, "ZeroMux" "FourInMux" 3 399, 3 125, S_0x2641070; + .timescale -9 -12; +L_0x2a3d860/d .functor NOT 1, L_0x2a3deb0, C4<0>, C4<0>, C4<0>; +L_0x2a3d860 .delay (10000,10000,10000) L_0x2a3d860/d; +L_0x2a3d950/d .functor NOT 1, L_0x2a3dfe0, C4<0>, C4<0>, C4<0>; +L_0x2a3d950 .delay (10000,10000,10000) L_0x2a3d950/d; +L_0x2a3d9f0/d .functor NAND 1, L_0x2a3d860, L_0x2a3d950, L_0x2a3e110, C4<1>; +L_0x2a3d9f0 .delay (10000,10000,10000) L_0x2a3d9f0/d; +L_0x2a3db30/d .functor NAND 1, L_0x2a3deb0, L_0x2a3d950, L_0x2a3e1b0, C4<1>; +L_0x2a3db30 .delay (10000,10000,10000) L_0x2a3db30/d; +L_0x2a3dc20/d .functor NAND 1, L_0x2a3d860, L_0x2a3dfe0, L_0x2a3e250, C4<1>; +L_0x2a3dc20 .delay (10000,10000,10000) L_0x2a3dc20/d; +L_0x2a3dd40/d .functor NAND 1, L_0x2a3deb0, L_0x2a3dfe0, L_0x2a3e340, C4<1>; +L_0x2a3dd40 .delay (10000,10000,10000) L_0x2a3dd40/d; +L_0x2a3ea20/d .functor NAND 1, L_0x2a3d9f0, L_0x2a3db30, L_0x2a3dc20, L_0x2a3dd40; +L_0x2a3ea20 .delay (10000,10000,10000) L_0x2a3ea20/d; +v0x2615d30_0 .net "S0", 0 0, L_0x2a3deb0; 1 drivers +v0x2611f10_0 .net "S1", 0 0, L_0x2a3dfe0; 1 drivers +v0x2611fb0_0 .net "in0", 0 0, L_0x2a3e110; 1 drivers +v0x259a0e0_0 .net "in1", 0 0, L_0x2a3e1b0; 1 drivers +v0x259a160_0 .net "in2", 0 0, L_0x2a3e250; 1 drivers +v0x26003d0_0 .net "in3", 0 0, L_0x2a3e340; 1 drivers +v0x2600470_0 .net "nS0", 0 0, L_0x2a3d860; 1 drivers +v0x25fe320_0 .net "nS1", 0 0, L_0x2a3d950; 1 drivers +v0x25fe3c0_0 .net "out", 0 0, L_0x2a3ea20; 1 drivers +v0x25fa5b0_0 .net "out0", 0 0, L_0x2a3d9f0; 1 drivers +v0x25fa650_0 .net "out1", 0 0, L_0x2a3db30; 1 drivers +v0x25f8500_0 .net "out2", 0 0, L_0x2a3dc20; 1 drivers +v0x25f85a0_0 .net "out3", 0 0, L_0x2a3dd40; 1 drivers +S_0x2635430 .scope module, "OneMux" "FourInMux" 3 400, 3 125, S_0x2641070; + .timescale -9 -12; +L_0x2a3e430/d .functor NOT 1, L_0x2a3fb90, C4<0>, C4<0>, C4<0>; +L_0x2a3e430 .delay (10000,10000,10000) L_0x2a3e430/d; +L_0x2a3e520/d .functor NOT 1, L_0x2a3ec90, C4<0>, C4<0>, C4<0>; +L_0x2a3e520 .delay (10000,10000,10000) L_0x2a3e520/d; +L_0x2a3e5c0/d .functor NAND 1, L_0x2a3e430, L_0x2a3e520, L_0x2a3edc0, C4<1>; +L_0x2a3e5c0 .delay (10000,10000,10000) L_0x2a3e5c0/d; +L_0x2a3e700/d .functor NAND 1, L_0x2a3fb90, L_0x2a3e520, L_0x2a3ee60, C4<1>; +L_0x2a3e700 .delay (10000,10000,10000) L_0x2a3e700/d; +L_0x2a3e7f0/d .functor NAND 1, L_0x2a3e430, L_0x2a3ec90, L_0x2a3ef00, C4<1>; +L_0x2a3e7f0 .delay (10000,10000,10000) L_0x2a3e7f0/d; +L_0x2a3e940/d .functor NAND 1, L_0x2a3fb90, L_0x2a3ec90, L_0x2a3eff0, C4<1>; +L_0x2a3e940 .delay (10000,10000,10000) L_0x2a3e940/d; +L_0x2a3f8e0/d .functor NAND 1, L_0x2a3e5c0, L_0x2a3e700, L_0x2a3e7f0, L_0x2a3e940; +L_0x2a3f8e0 .delay (10000,10000,10000) L_0x2a3f8e0/d; +v0x2635520_0 .net "S0", 0 0, L_0x2a3fb90; 1 drivers +v0x26333a0_0 .net "S1", 0 0, L_0x2a3ec90; 1 drivers +v0x2633440_0 .net "in0", 0 0, L_0x2a3edc0; 1 drivers +v0x2621880_0 .net "in1", 0 0, L_0x2a3ee60; 1 drivers +v0x2621900_0 .net "in2", 0 0, L_0x2a3ef00; 1 drivers +v0x261db10_0 .net "in3", 0 0, L_0x2a3eff0; 1 drivers +v0x261dbb0_0 .net "nS0", 0 0, L_0x2a3e430; 1 drivers +v0x261ba60_0 .net "nS1", 0 0, L_0x2a3e520; 1 drivers +v0x261bb00_0 .net "out", 0 0, L_0x2a3f8e0; 1 drivers +v0x2617cf0_0 .net "out0", 0 0, L_0x2a3e5c0; 1 drivers +v0x2617d90_0 .net "out1", 0 0, L_0x2a3e700; 1 drivers +v0x259c190_0 .net "out2", 0 0, L_0x2a3e7f0; 1 drivers +v0x259c230_0 .net "out3", 0 0, L_0x2a3e940; 1 drivers +S_0x263efc0 .scope module, "TwoMux" "TwoInMux" 3 401, 3 109, S_0x2641070; + .timescale -9 -12; +L_0x2a3f0e0/d .functor NOT 1, L_0x2a3f590, C4<0>, C4<0>, C4<0>; +L_0x2a3f0e0 .delay (10000,10000,10000) L_0x2a3f0e0/d; +L_0x2a3f1d0/d .functor AND 1, L_0x2a3f630, L_0x2a3f0e0, C4<1>, C4<1>; +L_0x2a3f1d0 .delay (20000,20000,20000) L_0x2a3f1d0/d; +L_0x2a3f2c0/d .functor AND 1, L_0x2a3f720, L_0x2a3f590, C4<1>, C4<1>; +L_0x2a3f2c0 .delay (20000,20000,20000) L_0x2a3f2c0/d; +L_0x2a3f3b0/d .functor OR 1, L_0x2a3f1d0, L_0x2a3f2c0, C4<0>, C4<0>; +L_0x2a3f3b0 .delay (20000,20000,20000) L_0x2a3f3b0/d; +v0x263f0b0_0 .net "S", 0 0, L_0x2a3f590; 1 drivers +v0x259ff00_0 .net "in0", 0 0, L_0x2a3f630; 1 drivers +v0x259ff80_0 .net "in1", 0 0, L_0x2a3f720; 1 drivers +v0x263b250_0 .net "nS", 0 0, L_0x2a3f0e0; 1 drivers +v0x263b2d0_0 .net "out0", 0 0, L_0x2a3f1d0; 1 drivers +v0x26391a0_0 .net "out1", 0 0, L_0x2a3f2c0; 1 drivers +v0x2639240_0 .net "outfinal", 0 0, L_0x2a3f3b0; 1 drivers +S_0x23971f0 .scope generate, "muxbits[19]" "muxbits[19]" 3 397, 3 397, S_0x25e6a40; + .timescale -9 -12; +P_0x2410ec8 .param/l "i" 3 397, +C4<010011>; +L_0x2a42470/d .functor OR 1, L_0x2a425b0, L_0x2a42650, C4<0>, C4<0>; +L_0x2a42470 .delay (20000,20000,20000) L_0x2a42470/d; +v0x27b4c20_0 .net *"_s15", 0 0, L_0x2a425b0; 1 drivers +v0x27b4ce0_0 .net *"_s16", 0 0, L_0x2a42650; 1 drivers +S_0x246f440 .scope module, "ZeroMux" "FourInMux" 3 399, 3 125, S_0x23971f0; + .timescale -9 -12; +L_0x2a3ff90/d .functor NOT 1, L_0x2a415a0, C4<0>, C4<0>, C4<0>; +L_0x2a3ff90 .delay (10000,10000,10000) L_0x2a3ff90/d; +L_0x2a40080/d .functor NOT 1, L_0x2a40920, C4<0>, C4<0>, C4<0>; +L_0x2a40080 .delay (10000,10000,10000) L_0x2a40080/d; +L_0x2a40120/d .functor NAND 1, L_0x2a3ff90, L_0x2a40080, L_0x2a40a50, C4<1>; +L_0x2a40120 .delay (10000,10000,10000) L_0x2a40120/d; +L_0x2a40260/d .functor NAND 1, L_0x2a415a0, L_0x2a40080, L_0x2a40af0, C4<1>; +L_0x2a40260 .delay (10000,10000,10000) L_0x2a40260/d; +L_0x2a40350/d .functor NAND 1, L_0x2a3ff90, L_0x2a40920, L_0x2a40b90, C4<1>; +L_0x2a40350 .delay (10000,10000,10000) L_0x2a40350/d; +L_0x2a404a0/d .functor NAND 1, L_0x2a415a0, L_0x2a40920, L_0x2a40c80, C4<1>; +L_0x2a404a0 .delay (10000,10000,10000) L_0x2a404a0/d; +L_0x2a40610/d .functor NAND 1, L_0x2a40120, L_0x2a40260, L_0x2a40350, L_0x2a404a0; +L_0x2a40610 .delay (10000,10000,10000) L_0x2a40610/d; +v0x246f530_0 .net "S0", 0 0, L_0x2a415a0; 1 drivers +v0x245c340_0 .net "S1", 0 0, L_0x2a40920; 1 drivers +v0x245c3e0_0 .net "in0", 0 0, L_0x2a40a50; 1 drivers +v0x2457690_0 .net "in1", 0 0, L_0x2a40af0; 1 drivers +v0x2457730_0 .net "in2", 0 0, L_0x2a40b90; 1 drivers +v0x24529e0_0 .net "in3", 0 0, L_0x2a40c80; 1 drivers +v0x2452a80_0 .net "nS0", 0 0, L_0x2a3ff90; 1 drivers +v0x244dd70_0 .net "nS1", 0 0, L_0x2a40080; 1 drivers +v0x244de10_0 .net "out", 0 0, L_0x2a40610; 1 drivers +v0x243ac80_0 .net "out0", 0 0, L_0x2a40120; 1 drivers +v0x243ad20_0 .net "out1", 0 0, L_0x2a40260; 1 drivers +v0x23edda0_0 .net "out2", 0 0, L_0x2a40350; 1 drivers +v0x23ede40_0 .net "out3", 0 0, L_0x2a404a0; 1 drivers +S_0x2431320 .scope module, "OneMux" "FourInMux" 3 400, 3 125, S_0x23971f0; + .timescale -9 -12; +L_0x2a40820/d .functor NOT 1, L_0x2a416d0, C4<0>, C4<0>, C4<0>; +L_0x2a40820 .delay (10000,10000,10000) L_0x2a40820/d; +L_0x2a40e00/d .functor NOT 1, L_0x2a41800, C4<0>, C4<0>, C4<0>; +L_0x2a40e00 .delay (10000,10000,10000) L_0x2a40e00/d; +L_0x2a40ea0/d .functor NAND 1, L_0x2a40820, L_0x2a40e00, L_0x2a41930, C4<1>; +L_0x2a40ea0 .delay (10000,10000,10000) L_0x2a40ea0/d; +L_0x2a40fe0/d .functor NAND 1, L_0x2a416d0, L_0x2a40e00, L_0x2a419d0, C4<1>; +L_0x2a40fe0 .delay (10000,10000,10000) L_0x2a40fe0/d; +L_0x2a410d0/d .functor NAND 1, L_0x2a40820, L_0x2a41800, L_0x2a41a70, C4<1>; +L_0x2a410d0 .delay (10000,10000,10000) L_0x2a410d0/d; +L_0x2a411c0/d .functor NAND 1, L_0x2a416d0, L_0x2a41800, L_0x2a41b60, C4<1>; +L_0x2a411c0 .delay (10000,10000,10000) L_0x2a411c0/d; +L_0x2a41330/d .functor NAND 1, L_0x2a40ea0, L_0x2a40fe0, L_0x2a410d0, L_0x2a411c0; +L_0x2a41330 .delay (10000,10000,10000) L_0x2a41330/d; +v0x2431410_0 .net "S0", 0 0, L_0x2a416d0; 1 drivers +v0x249a490_0 .net "S1", 0 0, L_0x2a41800; 1 drivers +v0x249a530_0 .net "in0", 0 0, L_0x2a41930; 1 drivers +v0x24957e0_0 .net "in1", 0 0, L_0x2a419d0; 1 drivers +v0x2495880_0 .net "in2", 0 0, L_0x2a41a70; 1 drivers +v0x2490b30_0 .net "in3", 0 0, L_0x2a41b60; 1 drivers +v0x2490bd0_0 .net "nS0", 0 0, L_0x2a40820; 1 drivers +v0x247da50_0 .net "nS1", 0 0, L_0x2a40e00; 1 drivers +v0x247daf0_0 .net "out", 0 0, L_0x2a41330; 1 drivers +v0x2478da0_0 .net "out0", 0 0, L_0x2a40ea0; 1 drivers +v0x2478e40_0 .net "out1", 0 0, L_0x2a40fe0; 1 drivers +v0x24740f0_0 .net "out2", 0 0, L_0x2a410d0; 1 drivers +v0x2474190_0 .net "out3", 0 0, L_0x2a411c0; 1 drivers +S_0x2395200 .scope module, "TwoMux" "TwoInMux" 3 401, 3 109, S_0x23971f0; + .timescale -9 -12; +L_0x2a41c50/d .functor NOT 1, L_0x2a42100, C4<0>, C4<0>, C4<0>; +L_0x2a41c50 .delay (10000,10000,10000) L_0x2a41c50/d; +L_0x2a41d40/d .functor AND 1, L_0x2a421a0, L_0x2a41c50, C4<1>, C4<1>; +L_0x2a41d40 .delay (20000,20000,20000) L_0x2a41d40/d; +L_0x2a41e30/d .functor AND 1, L_0x2a43030, L_0x2a42100, C4<1>, C4<1>; +L_0x2a41e30 .delay (20000,20000,20000) L_0x2a41e30/d; +L_0x2a41f20/d .functor OR 1, L_0x2a41d40, L_0x2a41e30, C4<0>, C4<0>; +L_0x2a41f20 .delay (20000,20000,20000) L_0x2a41f20/d; +v0x23952f0_0 .net "S", 0 0, L_0x2a42100; 1 drivers +v0x2391690_0 .net "in0", 0 0, L_0x2a421a0; 1 drivers +v0x2391730_0 .net "in1", 0 0, L_0x2a43030; 1 drivers +v0x238f6a0_0 .net "nS", 0 0, L_0x2a41c50; 1 drivers +v0x238f720_0 .net "out0", 0 0, L_0x2a41d40; 1 drivers +v0x2435fd0_0 .net "out1", 0 0, L_0x2a41e30; 1 drivers +v0x2436070_0 .net "outfinal", 0 0, L_0x2a41f20; 1 drivers +S_0x23f3620 .scope generate, "muxbits[20]" "muxbits[20]" 3 397, 3 397, S_0x25e6a40; + .timescale -9 -12; +P_0x263fb58 .param/l "i" 3 397, +C4<010100>; +L_0x2a44be0/d .functor OR 1, L_0x2a45ad0, L_0x2a45b70, C4<0>, C4<0>; +L_0x2a44be0 .delay (20000,20000,20000) L_0x2a44be0/d; +v0x239ad60_0 .net *"_s15", 0 0, L_0x2a45ad0; 1 drivers +v0x239ae20_0 .net *"_s16", 0 0, L_0x2a45b70; 1 drivers +S_0x23b78e0 .scope module, "ZeroMux" "FourInMux" 3 399, 3 125, S_0x23f3620; + .timescale -9 -12; +L_0x2a42740/d .functor NOT 1, L_0x2a43d60, C4<0>, C4<0>, C4<0>; +L_0x2a42740 .delay (10000,10000,10000) L_0x2a42740/d; +L_0x2a42830/d .functor NOT 1, L_0x2a43e90, C4<0>, C4<0>, C4<0>; +L_0x2a42830 .delay (10000,10000,10000) L_0x2a42830/d; +L_0x2a428d0/d .functor NAND 1, L_0x2a42740, L_0x2a42830, L_0x2a430d0, C4<1>; +L_0x2a428d0 .delay (10000,10000,10000) L_0x2a428d0/d; +L_0x2a42a10/d .functor NAND 1, L_0x2a43d60, L_0x2a42830, L_0x2a43170, C4<1>; +L_0x2a42a10 .delay (10000,10000,10000) L_0x2a42a10/d; +L_0x2a42b00/d .functor NAND 1, L_0x2a42740, L_0x2a43e90, L_0x2a43210, C4<1>; +L_0x2a42b00 .delay (10000,10000,10000) L_0x2a42b00/d; +L_0x2a42bf0/d .functor NAND 1, L_0x2a43d60, L_0x2a43e90, L_0x2a43300, C4<1>; +L_0x2a42bf0 .delay (10000,10000,10000) L_0x2a42bf0/d; +L_0x2a42d60/d .functor NAND 1, L_0x2a428d0, L_0x2a42a10, L_0x2a42b00, L_0x2a42bf0; +L_0x2a42d60 .delay (10000,10000,10000) L_0x2a42d60/d; +v0x23b79d0_0 .net "S0", 0 0, L_0x2a43d60; 1 drivers +v0x23b3d70_0 .net "S1", 0 0, L_0x2a43e90; 1 drivers +v0x23b3e10_0 .net "in0", 0 0, L_0x2a430d0; 1 drivers +v0x236ef70_0 .net "in1", 0 0, L_0x2a43170; 1 drivers +v0x236f010_0 .net "in2", 0 0, L_0x2a43210; 1 drivers +v0x23b1d80_0 .net "in3", 0 0, L_0x2a43300; 1 drivers +v0x23b1e20_0 .net "nS0", 0 0, L_0x2a42740; 1 drivers +v0x23ae210_0 .net "nS1", 0 0, L_0x2a42830; 1 drivers +v0x23ae2b0_0 .net "out", 0 0, L_0x2a42d60; 1 drivers +v0x236cf80_0 .net "out0", 0 0, L_0x2a428d0; 1 drivers +v0x236d020_0 .net "out1", 0 0, L_0x2a42a10; 1 drivers +v0x239cd50_0 .net "out2", 0 0, L_0x2a42b00; 1 drivers +v0x239cdf0_0 .net "out3", 0 0, L_0x2a42bf0; 1 drivers +S_0x2372ae0 .scope module, "OneMux" "FourInMux" 3 400, 3 125, S_0x23f3620; + .timescale -9 -12; +L_0x2a433f0/d .functor NOT 1, L_0x2a43cc0, C4<0>, C4<0>, C4<0>; +L_0x2a433f0 .delay (10000,10000,10000) L_0x2a433f0/d; +L_0x2a434e0/d .functor NOT 1, L_0x2a43fc0, C4<0>, C4<0>, C4<0>; +L_0x2a434e0 .delay (10000,10000,10000) L_0x2a434e0/d; +L_0x2a43580/d .functor NAND 1, L_0x2a433f0, L_0x2a434e0, L_0x2a440f0, C4<1>; +L_0x2a43580 .delay (10000,10000,10000) L_0x2a43580/d; +L_0x2a436c0/d .functor NAND 1, L_0x2a43cc0, L_0x2a434e0, L_0x2a44190, C4<1>; +L_0x2a436c0 .delay (10000,10000,10000) L_0x2a436c0/d; +L_0x2a437b0/d .functor NAND 1, L_0x2a433f0, L_0x2a43fc0, L_0x2a44230, C4<1>; +L_0x2a437b0 .delay (10000,10000,10000) L_0x2a437b0/d; +L_0x2a438a0/d .functor NAND 1, L_0x2a43cc0, L_0x2a43fc0, L_0x2a44320, C4<1>; +L_0x2a438a0 .delay (10000,10000,10000) L_0x2a438a0/d; +L_0x2a43a10/d .functor NAND 1, L_0x2a43580, L_0x2a436c0, L_0x2a437b0, L_0x2a438a0; +L_0x2a43a10 .delay (10000,10000,10000) L_0x2a43a10/d; +v0x2372bd0_0 .net "S0", 0 0, L_0x2a43cc0; 1 drivers +v0x23d6430_0 .net "S1", 0 0, L_0x2a43fc0; 1 drivers +v0x23d64d0_0 .net "in0", 0 0, L_0x2a440f0; 1 drivers +v0x23d4440_0 .net "in1", 0 0, L_0x2a44190; 1 drivers +v0x23d44e0_0 .net "in2", 0 0, L_0x2a44230; 1 drivers +v0x23d08d0_0 .net "in3", 0 0, L_0x2a44320; 1 drivers +v0x23d0970_0 .net "nS0", 0 0, L_0x2a433f0; 1 drivers +v0x23ce8e0_0 .net "nS1", 0 0, L_0x2a434e0; 1 drivers +v0x23ce980_0 .net "out", 0 0, L_0x2a43a10; 1 drivers +v0x23bd440_0 .net "out0", 0 0, L_0x2a43580; 1 drivers +v0x23bd4e0_0 .net "out1", 0 0, L_0x2a436c0; 1 drivers +v0x23b98d0_0 .net "out2", 0 0, L_0x2a437b0; 1 drivers +v0x23b9970_0 .net "out3", 0 0, L_0x2a438a0; 1 drivers +S_0x23f1570 .scope module, "TwoMux" "TwoInMux" 3 401, 3 109, S_0x23f3620; + .timescale -9 -12; +L_0x2a44410/d .functor NOT 1, L_0x2a448c0, C4<0>, C4<0>, C4<0>; +L_0x2a44410 .delay (10000,10000,10000) L_0x2a44410/d; +L_0x2a44500/d .functor AND 1, L_0x2a44960, L_0x2a44410, C4<1>, C4<1>; +L_0x2a44500 .delay (20000,20000,20000) L_0x2a44500/d; +L_0x2a445f0/d .functor AND 1, L_0x2a44a50, L_0x2a448c0, C4<1>, C4<1>; +L_0x2a445f0 .delay (20000,20000,20000) L_0x2a445f0/d; +L_0x2a446e0/d .functor OR 1, L_0x2a44500, L_0x2a445f0, C4<0>, C4<0>; +L_0x2a446e0 .delay (20000,20000,20000) L_0x2a446e0/d; +v0x23f1660_0 .net "S", 0 0, L_0x2a448c0; 1 drivers +v0x2374ad0_0 .net "in0", 0 0, L_0x2a44960; 1 drivers +v0x2374b70_0 .net "in1", 0 0, L_0x2a44a50; 1 drivers +v0x23dbf90_0 .net "nS", 0 0, L_0x2a44410; 1 drivers +v0x23dc010_0 .net "out0", 0 0, L_0x2a44500; 1 drivers +v0x23d9fa0_0 .net "out1", 0 0, L_0x2a445f0; 1 drivers +v0x23da040_0 .net "outfinal", 0 0, L_0x2a446e0; 1 drivers +S_0x263baf0 .scope generate, "muxbits[21]" "muxbits[21]" 3 397, 3 397, S_0x25e6a40; + .timescale -9 -12; +P_0x262fc18 .param/l "i" 3 397, +C4<010101>; +L_0x2a47170/d .functor OR 1, L_0x2a472b0, L_0x2a47350, C4<0>, C4<0>; +L_0x2a47170 .delay (20000,20000,20000) L_0x2a47170/d; +v0x23f7390_0 .net *"_s15", 0 0, L_0x2a472b0; 1 drivers +v0x23f7450_0 .net *"_s16", 0 0, L_0x2a47350; 1 drivers +S_0x237a630 .scope module, "ZeroMux" "FourInMux" 3 399, 3 125, S_0x263baf0; + .timescale -9 -12; +L_0x2a44d10/d .functor NOT 1, L_0x2a455b0, C4<0>, C4<0>, C4<0>; +L_0x2a44d10 .delay (10000,10000,10000) L_0x2a44d10/d; +L_0x2a44e00/d .functor NOT 1, L_0x2a456e0, C4<0>, C4<0>, C4<0>; +L_0x2a44e00 .delay (10000,10000,10000) L_0x2a44e00/d; +L_0x2a44ea0/d .functor NAND 1, L_0x2a44d10, L_0x2a44e00, L_0x2a45810, C4<1>; +L_0x2a44ea0 .delay (10000,10000,10000) L_0x2a44ea0/d; +L_0x2a44fe0/d .functor NAND 1, L_0x2a455b0, L_0x2a44e00, L_0x2a458b0, C4<1>; +L_0x2a44fe0 .delay (10000,10000,10000) L_0x2a44fe0/d; +L_0x2a450d0/d .functor NAND 1, L_0x2a44d10, L_0x2a456e0, L_0x2a45950, C4<1>; +L_0x2a450d0 .delay (10000,10000,10000) L_0x2a450d0/d; +L_0x2a451c0/d .functor NAND 1, L_0x2a455b0, L_0x2a456e0, L_0x2a45c60, C4<1>; +L_0x2a451c0 .delay (10000,10000,10000) L_0x2a451c0/d; +L_0x2a45300/d .functor NAND 1, L_0x2a44ea0, L_0x2a44fe0, L_0x2a450d0, L_0x2a451c0; +L_0x2a45300 .delay (10000,10000,10000) L_0x2a45300/d; +v0x260fee0_0 .net "S0", 0 0, L_0x2a455b0; 1 drivers +v0x2414af0_0 .net "S1", 0 0, L_0x2a456e0; 1 drivers +v0x2414b90_0 .net "in0", 0 0, L_0x2a45810; 1 drivers +v0x2378640_0 .net "in1", 0 0, L_0x2a458b0; 1 drivers +v0x23786e0_0 .net "in2", 0 0, L_0x2a45950; 1 drivers +v0x2410d80_0 .net "in3", 0 0, L_0x2a45c60; 1 drivers +v0x2410e20_0 .net "nS0", 0 0, L_0x2a44d10; 1 drivers +v0x240ecb0_0 .net "nS1", 0 0, L_0x2a44e00; 1 drivers +v0x240ed50_0 .net "out", 0 0, L_0x2a45300; 1 drivers +v0x23fd1b0_0 .net "out0", 0 0, L_0x2a44ea0; 1 drivers +v0x23fd250_0 .net "out1", 0 0, L_0x2a44fe0; 1 drivers +v0x23f9440_0 .net "out2", 0 0, L_0x2a450d0; 1 drivers +v0x23f94e0_0 .net "out3", 0 0, L_0x2a451c0; 1 drivers +S_0x2639760 .scope module, "OneMux" "FourInMux" 3 400, 3 125, S_0x263baf0; + .timescale -9 -12; +L_0x2a45d50/d .functor NOT 1, L_0x2a46520, C4<0>, C4<0>, C4<0>; +L_0x2a45d50 .delay (10000,10000,10000) L_0x2a45d50/d; +L_0x2a45e00/d .functor NOT 1, L_0x2a46650, C4<0>, C4<0>, C4<0>; +L_0x2a45e00 .delay (10000,10000,10000) L_0x2a45e00/d; +L_0x2a45ea0/d .functor NAND 1, L_0x2a45d50, L_0x2a45e00, L_0x2a46780, C4<1>; +L_0x2a45ea0 .delay (10000,10000,10000) L_0x2a45ea0/d; +L_0x2a45fe0/d .functor NAND 1, L_0x2a46520, L_0x2a45e00, L_0x2a46820, C4<1>; +L_0x2a45fe0 .delay (10000,10000,10000) L_0x2a45fe0/d; +L_0x2a460d0/d .functor NAND 1, L_0x2a45d50, L_0x2a46650, L_0x2a468c0, C4<1>; +L_0x2a460d0 .delay (10000,10000,10000) L_0x2a460d0/d; +L_0x2a461c0/d .functor NAND 1, L_0x2a46520, L_0x2a46650, L_0x2a47790, C4<1>; +L_0x2a461c0 .delay (10000,10000,10000) L_0x2a461c0/d; +L_0x2a462a0/d .functor NAND 1, L_0x2a45ea0, L_0x2a45fe0, L_0x2a460d0, L_0x2a461c0; +L_0x2a462a0 .delay (10000,10000,10000) L_0x2a462a0/d; +v0x2639aa0_0 .net "S0", 0 0, L_0x2a46520; 1 drivers +v0x2641670_0 .net "S1", 0 0, L_0x2a46650; 1 drivers +v0x2641710_0 .net "in0", 0 0, L_0x2a46780; 1 drivers +v0x263fd80_0 .net "in1", 0 0, L_0x2a46820; 1 drivers +v0x263fe20_0 .net "in2", 0 0, L_0x2a468c0; 1 drivers +v0x263fad0_0 .net "in3", 0 0, L_0x2a47790; 1 drivers +v0x263f820_0 .net "nS0", 0 0, L_0x2a45d50; 1 drivers +v0x263f8c0_0 .net "nS1", 0 0, L_0x2a45e00; 1 drivers +v0x263f580_0 .net "out", 0 0, L_0x2a462a0; 1 drivers +v0x263f620_0 .net "out0", 0 0, L_0x2a45ea0; 1 drivers +v0x2221490_0 .net "out1", 0 0, L_0x2a45fe0; 1 drivers +v0x2221530_0 .net "out2", 0 0, L_0x2a460d0; 1 drivers +v0x260fe40_0 .net "out3", 0 0, L_0x2a461c0; 1 drivers +S_0x263b850 .scope module, "TwoMux" "TwoInMux" 3 401, 3 109, S_0x263baf0; + .timescale -9 -12; +L_0x2a45220/d .functor NOT 1, L_0x2a46e50, C4<0>, C4<0>, C4<0>; +L_0x2a45220 .delay (10000,10000,10000) L_0x2a45220/d; +L_0x2a46a90/d .functor AND 1, L_0x2a46ef0, L_0x2a45220, C4<1>, C4<1>; +L_0x2a46a90 .delay (20000,20000,20000) L_0x2a46a90/d; +L_0x2a46b80/d .functor AND 1, L_0x2a46fe0, L_0x2a46e50, C4<1>, C4<1>; +L_0x2a46b80 .delay (20000,20000,20000) L_0x2a46b80/d; +L_0x2a46c70/d .functor OR 1, L_0x2a46a90, L_0x2a46b80, C4<0>, C4<0>; +L_0x2a46c70 .delay (20000,20000,20000) L_0x2a46c70/d; +v0x2639f60_0 .net "S", 0 0, L_0x2a46e50; 1 drivers +v0x263a000_0 .net "in0", 0 0, L_0x2a46ef0; 1 drivers +v0x2639cb0_0 .net "in1", 0 0, L_0x2a46fe0; 1 drivers +v0x2639d50_0 .net "nS", 0 0, L_0x2a45220; 1 drivers +v0x263d270_0 .net "out0", 0 0, L_0x2a46a90; 1 drivers +v0x263d310_0 .net "out1", 0 0, L_0x2a46b80; 1 drivers +v0x2639a00_0 .net "outfinal", 0 0, L_0x2a46c70; 1 drivers +S_0x261c820 .scope generate, "muxbits[22]" "muxbits[22]" 3 397, 3 397, S_0x25e6a40; + .timescale -9 -12; +P_0x2618b78 .param/l "i" 3 397, +C4<010110>; +L_0x2a49710/d .functor OR 1, L_0x2a49850, L_0x2a4a8e0, C4<0>, C4<0>; +L_0x2a49710 .delay (20000,20000,20000) L_0x2a49710/d; +v0x263bda0_0 .net *"_s15", 0 0, L_0x2a49850; 1 drivers +v0x263be60_0 .net *"_s16", 0 0, L_0x2a4a8e0; 1 drivers +S_0x2635a30 .scope module, "ZeroMux" "FourInMux" 3 399, 3 125, S_0x261c820; + .timescale -9 -12; +L_0x2a47440/d .functor NOT 1, L_0x2a47880, C4<0>, C4<0>, C4<0>; +L_0x2a47440 .delay (10000,10000,10000) L_0x2a47440/d; +L_0x2a47530/d .functor NOT 1, L_0x2a479b0, C4<0>, C4<0>, C4<0>; +L_0x2a47530 .delay (10000,10000,10000) L_0x2a47530/d; +L_0x2a475d0/d .functor NAND 1, L_0x2a47440, L_0x2a47530, L_0x2a47ae0, C4<1>; +L_0x2a475d0 .delay (10000,10000,10000) L_0x2a475d0/d; +L_0x2a47710/d .functor NAND 1, L_0x2a47880, L_0x2a47530, L_0x2a47b80, C4<1>; +L_0x2a47710 .delay (10000,10000,10000) L_0x2a47710/d; +L_0x2a486e0/d .functor NAND 1, L_0x2a47440, L_0x2a479b0, L_0x2a47c20, C4<1>; +L_0x2a486e0 .delay (10000,10000,10000) L_0x2a486e0/d; +L_0x2a487d0/d .functor NAND 1, L_0x2a47880, L_0x2a479b0, L_0x2a47d10, C4<1>; +L_0x2a487d0 .delay (10000,10000,10000) L_0x2a487d0/d; +L_0x2a488b0/d .functor NAND 1, L_0x2a475d0, L_0x2a47710, L_0x2a486e0, L_0x2a487d0; +L_0x2a488b0 .delay (10000,10000,10000) L_0x2a488b0/d; +v0x2635d70_0 .net "S0", 0 0, L_0x2a47880; 1 drivers +v0x2634140_0 .net "S1", 0 0, L_0x2a479b0; 1 drivers +v0x26341e0_0 .net "in0", 0 0, L_0x2a47ae0; 1 drivers +v0x2633e90_0 .net "in1", 0 0, L_0x2a47b80; 1 drivers +v0x2633f30_0 .net "in2", 0 0, L_0x2a47c20; 1 drivers +v0x2637450_0 .net "in3", 0 0, L_0x2a47d10; 1 drivers +v0x26374f0_0 .net "nS0", 0 0, L_0x2a47440; 1 drivers +v0x2633be0_0 .net "nS1", 0 0, L_0x2a47530; 1 drivers +v0x2633c80_0 .net "out", 0 0, L_0x2a488b0; 1 drivers +v0x2633940_0 .net "out0", 0 0, L_0x2a475d0; 1 drivers +v0x26339e0_0 .net "out1", 0 0, L_0x2a47710; 1 drivers +v0x263c050_0 .net "out2", 0 0, L_0x2a486e0; 1 drivers +v0x263c0f0_0 .net "out3", 0 0, L_0x2a487d0; 1 drivers +S_0x2621e40 .scope module, "OneMux" "FourInMux" 3 400, 3 125, S_0x261c820; + .timescale -9 -12; +L_0x2a47e00/d .functor NOT 1, L_0x2a49940, C4<0>, C4<0>, C4<0>; +L_0x2a47e00 .delay (10000,10000,10000) L_0x2a47e00/d; +L_0x2a47ef0/d .functor NOT 1, L_0x2a48b30, C4<0>, C4<0>, C4<0>; +L_0x2a47ef0 .delay (10000,10000,10000) L_0x2a47ef0/d; +L_0x2a47f90/d .functor NAND 1, L_0x2a47e00, L_0x2a47ef0, L_0x2a48c60, C4<1>; +L_0x2a47f90 .delay (10000,10000,10000) L_0x2a47f90/d; +L_0x2a480d0/d .functor NAND 1, L_0x2a49940, L_0x2a47ef0, L_0x2a48d00, C4<1>; +L_0x2a480d0 .delay (10000,10000,10000) L_0x2a480d0/d; +L_0x2a481c0/d .functor NAND 1, L_0x2a47e00, L_0x2a48b30, L_0x2a48da0, C4<1>; +L_0x2a481c0 .delay (10000,10000,10000) L_0x2a481c0/d; +L_0x2a482b0/d .functor NAND 1, L_0x2a49940, L_0x2a48b30, L_0x2a48e90, C4<1>; +L_0x2a482b0 .delay (10000,10000,10000) L_0x2a482b0/d; +L_0x2a48390/d .functor NAND 1, L_0x2a47f90, L_0x2a480d0, L_0x2a481c0, L_0x2a482b0; +L_0x2a48390 .delay (10000,10000,10000) L_0x2a48390/d; +v0x2623f70_0 .net "S0", 0 0, L_0x2a49940; 1 drivers +v0x2629d30_0 .net "S1", 0 0, L_0x2a48b30; 1 drivers +v0x2629dd0_0 .net "in0", 0 0, L_0x2a48c60; 1 drivers +v0x2627c40_0 .net "in1", 0 0, L_0x2a48d00; 1 drivers +v0x2627ce0_0 .net "in2", 0 0, L_0x2a48da0; 1 drivers +v0x262fb90_0 .net "in3", 0 0, L_0x2a48e90; 1 drivers +v0x262daa0_0 .net "nS0", 0 0, L_0x2a47e00; 1 drivers +v0x262db40_0 .net "nS1", 0 0, L_0x2a47ef0; 1 drivers +v0x2636230_0 .net "out", 0 0, L_0x2a48390; 1 drivers +v0x26362d0_0 .net "out0", 0 0, L_0x2a47f90; 1 drivers +v0x2635f80_0 .net "out1", 0 0, L_0x2a480d0; 1 drivers +v0x2636020_0 .net "out2", 0 0, L_0x2a481c0; 1 drivers +v0x2635cd0_0 .net "out3", 0 0, L_0x2a482b0; 1 drivers +S_0x261c570 .scope module, "TwoMux" "TwoInMux" 3 401, 3 109, S_0x261c820; + .timescale -9 -12; +L_0x2a48f80/d .functor NOT 1, L_0x2a493f0, C4<0>, C4<0>, C4<0>; +L_0x2a48f80 .delay (10000,10000,10000) L_0x2a48f80/d; +L_0x2a49030/d .functor AND 1, L_0x2a49490, L_0x2a48f80, C4<1>, C4<1>; +L_0x2a49030 .delay (20000,20000,20000) L_0x2a49030/d; +L_0x2a49120/d .functor AND 1, L_0x2a49580, L_0x2a493f0, C4<1>, C4<1>; +L_0x2a49120 .delay (20000,20000,20000) L_0x2a49120/d; +L_0x2a49210/d .functor OR 1, L_0x2a49030, L_0x2a49120, C4<0>, C4<0>; +L_0x2a49210 .delay (20000,20000,20000) L_0x2a49210/d; +v0x261fb30_0 .net "S", 0 0, L_0x2a493f0; 1 drivers +v0x261fbd0_0 .net "in0", 0 0, L_0x2a49490; 1 drivers +v0x261c2c0_0 .net "in1", 0 0, L_0x2a49580; 1 drivers +v0x261c360_0 .net "nS", 0 0, L_0x2a48f80; 1 drivers +v0x261c020_0 .net "out0", 0 0, L_0x2a49030; 1 drivers +v0x261c0c0_0 .net "out1", 0 0, L_0x2a49120; 1 drivers +v0x2623ed0_0 .net "outfinal", 0 0, L_0x2a49210; 1 drivers +S_0x26046c0 .scope generate, "muxbits[23]" "muxbits[23]" 3 397, 3 397, S_0x25e6a40; + .timescale -9 -12; +P_0x25f9098 .param/l "i" 3 397, +C4<010111>; +L_0x2a4b6d0/d .functor OR 1, L_0x2a4ce70, L_0x2a4bf60, C4<0>, C4<0>; +L_0x2a4b6d0 .delay (20000,20000,20000) L_0x2a4b6d0/d; +v0x261e110_0 .net *"_s15", 0 0, L_0x2a4ce70; 1 drivers +v0x261e1d0_0 .net *"_s16", 0 0, L_0x2a4bf60; 1 drivers +S_0x2616750 .scope module, "ZeroMux" "FourInMux" 3 399, 3 125, S_0x26046c0; + .timescale -9 -12; +L_0x2a49a70/d .functor NOT 1, L_0x2a4a280, C4<0>, C4<0>, C4<0>; +L_0x2a49a70 .delay (10000,10000,10000) L_0x2a49a70/d; +L_0x2a49b60/d .functor NOT 1, L_0x2a4a3b0, C4<0>, C4<0>, C4<0>; +L_0x2a49b60 .delay (10000,10000,10000) L_0x2a49b60/d; +L_0x2a49c00/d .functor NAND 1, L_0x2a49a70, L_0x2a49b60, L_0x2a4a4e0, C4<1>; +L_0x2a49c00 .delay (10000,10000,10000) L_0x2a49c00/d; +L_0x2a49d40/d .functor NAND 1, L_0x2a4a280, L_0x2a49b60, L_0x2a4a580, C4<1>; +L_0x2a49d40 .delay (10000,10000,10000) L_0x2a49d40/d; +L_0x2a49e30/d .functor NAND 1, L_0x2a49a70, L_0x2a4a3b0, L_0x2a4a620, C4<1>; +L_0x2a49e30 .delay (10000,10000,10000) L_0x2a49e30/d; +L_0x2a49f20/d .functor NAND 1, L_0x2a4a280, L_0x2a4a3b0, L_0x2a4a710, C4<1>; +L_0x2a49f20 .delay (10000,10000,10000) L_0x2a49f20/d; +L_0x2a4a000/d .functor NAND 1, L_0x2a49c00, L_0x2a49d40, L_0x2a49e30, L_0x2a49f20; +L_0x2a4a000 .delay (10000,10000,10000) L_0x2a4a000/d; +v0x2616aa0_0 .net "S0", 0 0, L_0x2a4a280; 1 drivers +v0x2619d10_0 .net "S1", 0 0, L_0x2a4a3b0; 1 drivers +v0x2619db0_0 .net "in0", 0 0, L_0x2a4a4e0; 1 drivers +v0x26164a0_0 .net "in1", 0 0, L_0x2a4a580; 1 drivers +v0x2616540_0 .net "in2", 0 0, L_0x2a4a620; 1 drivers +v0x2616200_0 .net "in3", 0 0, L_0x2a4a710; 1 drivers +v0x26162a0_0 .net "nS0", 0 0, L_0x2a49a70; 1 drivers +v0x261e910_0 .net "nS1", 0 0, L_0x2a49b60; 1 drivers +v0x261e9b0_0 .net "out", 0 0, L_0x2a4a000; 1 drivers +v0x261e660_0 .net "out0", 0 0, L_0x2a49c00; 1 drivers +v0x261e700_0 .net "out1", 0 0, L_0x2a49d40; 1 drivers +v0x261e3b0_0 .net "out2", 0 0, L_0x2a49e30; 1 drivers +v0x261e450_0 .net "out3", 0 0, L_0x2a49f20; 1 drivers +S_0x26124d0 .scope module, "OneMux" "FourInMux" 3 400, 3 125, S_0x26046c0; + .timescale -9 -12; +L_0x2a4a800/d .functor NOT 1, L_0x2a4a980, C4<0>, C4<0>, C4<0>; +L_0x2a4a800 .delay (10000,10000,10000) L_0x2a4a800/d; +L_0x2a4b880/d .functor NOT 1, L_0x2a4aab0, C4<0>, C4<0>, C4<0>; +L_0x2a4b880 .delay (10000,10000,10000) L_0x2a4b880/d; +L_0x2a4b8e0/d .functor NAND 1, L_0x2a4a800, L_0x2a4b880, L_0x2a4abe0, C4<1>; +L_0x2a4b8e0 .delay (10000,10000,10000) L_0x2a4b8e0/d; +L_0x2a4ba20/d .functor NAND 1, L_0x2a4a980, L_0x2a4b880, L_0x2a4ac80, C4<1>; +L_0x2a4ba20 .delay (10000,10000,10000) L_0x2a4ba20/d; +L_0x2a4bb10/d .functor NAND 1, L_0x2a4a800, L_0x2a4aab0, L_0x2a4ad20, C4<1>; +L_0x2a4bb10 .delay (10000,10000,10000) L_0x2a4bb10/d; +L_0x2a4bc00/d .functor NAND 1, L_0x2a4a980, L_0x2a4aab0, L_0x2a4ae10, C4<1>; +L_0x2a4bc00 .delay (10000,10000,10000) L_0x2a4bc00/d; +L_0x2a4bce0/d .functor NAND 1, L_0x2a4b8e0, L_0x2a4ba20, L_0x2a4bb10, L_0x2a4bc00; +L_0x2a4bce0 .delay (10000,10000,10000) L_0x2a4bce0/d; +v0x2612810_0 .net "S0", 0 0, L_0x2a4a980; 1 drivers +v0x2613ef0_0 .net "S1", 0 0, L_0x2a4aab0; 1 drivers +v0x2613f90_0 .net "in0", 0 0, L_0x2a4abe0; 1 drivers +v0x2610380_0 .net "in1", 0 0, L_0x2a4ac80; 1 drivers +v0x2610420_0 .net "in2", 0 0, L_0x2a4ad20; 1 drivers +v0x2618af0_0 .net "in3", 0 0, L_0x2a4ae10; 1 drivers +v0x2618840_0 .net "nS0", 0 0, L_0x2a4a800; 1 drivers +v0x26188e0_0 .net "nS1", 0 0, L_0x2a4b880; 1 drivers +v0x2618590_0 .net "out", 0 0, L_0x2a4bce0; 1 drivers +v0x2618630_0 .net "out0", 0 0, L_0x2a4b8e0; 1 drivers +v0x26182f0_0 .net "out1", 0 0, L_0x2a4ba20; 1 drivers +v0x2618390_0 .net "out2", 0 0, L_0x2a4bb10; 1 drivers +v0x2616a00_0 .net "out3", 0 0, L_0x2a4bc00; 1 drivers +S_0x260c610 .scope module, "TwoMux" "TwoInMux" 3 401, 3 109, S_0x26046c0; + .timescale -9 -12; +L_0x2a4af00/d .functor NOT 1, L_0x2a4b3b0, C4<0>, C4<0>, C4<0>; +L_0x2a4af00 .delay (10000,10000,10000) L_0x2a4af00/d; +L_0x2a4aff0/d .functor AND 1, L_0x2a4b450, L_0x2a4af00, C4<1>, C4<1>; +L_0x2a4aff0 .delay (20000,20000,20000) L_0x2a4aff0/d; +L_0x2a4b0e0/d .functor AND 1, L_0x2a4b540, L_0x2a4b3b0, C4<1>, C4<1>; +L_0x2a4b0e0 .delay (20000,20000,20000) L_0x2a4b0e0/d; +L_0x2a4b1d0/d .functor OR 1, L_0x2a4aff0, L_0x2a4b0e0, C4<0>, C4<0>; +L_0x2a4b1d0 .delay (20000,20000,20000) L_0x2a4b1d0/d; +v0x260a520_0 .net "S", 0 0, L_0x2a4b3b0; 1 drivers +v0x260a5c0_0 .net "in0", 0 0, L_0x2a4b450; 1 drivers +v0x2612cd0_0 .net "in1", 0 0, L_0x2a4b540; 1 drivers +v0x2612d70_0 .net "nS", 0 0, L_0x2a4af00; 1 drivers +v0x2612a20_0 .net "out0", 0 0, L_0x2a4aff0; 1 drivers +v0x2612ac0_0 .net "out1", 0 0, L_0x2a4b0e0; 1 drivers +v0x2612770_0 .net "outfinal", 0 0, L_0x2a4b1d0; 1 drivers +S_0x25f31f0 .scope generate, "muxbits[24]" "muxbits[24]" 3 397, 3 397, S_0x25e6a40; + .timescale -9 -12; +P_0x25e3298 .param/l "i" 3 397, +C4<011000>; +L_0x2a4db30/d .functor OR 1, L_0x2a4dc70, L_0x2a4dd10, C4<0>, C4<0>; +L_0x2a4db30 .delay (20000,20000,20000) L_0x2a4db30/d; +v0x26067b0_0 .net *"_s15", 0 0, L_0x2a4dc70; 1 drivers +v0x2606870_0 .net *"_s16", 0 0, L_0x2a4dd10; 1 drivers +S_0x2600f20 .scope module, "ZeroMux" "FourInMux" 3 399, 3 125, S_0x25f31f0; + .timescale -9 -12; +L_0x2a4c050/d .functor NOT 1, L_0x2a4c860, C4<0>, C4<0>, C4<0>; +L_0x2a4c050 .delay (10000,10000,10000) L_0x2a4c050/d; +L_0x2a4c140/d .functor NOT 1, L_0x2a4c990, C4<0>, C4<0>, C4<0>; +L_0x2a4c140 .delay (10000,10000,10000) L_0x2a4c140/d; +L_0x2a4c1e0/d .functor NAND 1, L_0x2a4c050, L_0x2a4c140, L_0x2a4cac0, C4<1>; +L_0x2a4c1e0 .delay (10000,10000,10000) L_0x2a4c1e0/d; +L_0x2a4c320/d .functor NAND 1, L_0x2a4c860, L_0x2a4c140, L_0x2a4cb60, C4<1>; +L_0x2a4c320 .delay (10000,10000,10000) L_0x2a4c320/d; +L_0x2a4c410/d .functor NAND 1, L_0x2a4c050, L_0x2a4c990, L_0x2a4cc00, C4<1>; +L_0x2a4c410 .delay (10000,10000,10000) L_0x2a4c410/d; +L_0x2a4c500/d .functor NAND 1, L_0x2a4c860, L_0x2a4c990, L_0x2a4ccf0, C4<1>; +L_0x2a4c500 .delay (10000,10000,10000) L_0x2a4c500/d; +L_0x2a4c5e0/d .functor NAND 1, L_0x2a4c1e0, L_0x2a4c320, L_0x2a4c410, L_0x2a4c500; +L_0x2a4c5e0 .delay (10000,10000,10000) L_0x2a4c5e0/d; +v0x2601270_0 .net "S0", 0 0, L_0x2a4c860; 1 drivers +v0x2600c70_0 .net "S1", 0 0, L_0x2a4c990; 1 drivers +v0x2600d10_0 .net "in0", 0 0, L_0x2a4cac0; 1 drivers +v0x26009d0_0 .net "in1", 0 0, L_0x2a4cb60; 1 drivers +v0x2600a70_0 .net "in2", 0 0, L_0x2a4cc00; 1 drivers +v0x25ff0e0_0 .net "in3", 0 0, L_0x2a4ccf0; 1 drivers +v0x25ff180_0 .net "nS0", 0 0, L_0x2a4c050; 1 drivers +v0x25fee30_0 .net "nS1", 0 0, L_0x2a4c140; 1 drivers +v0x25feed0_0 .net "out", 0 0, L_0x2a4c5e0; 1 drivers +v0x25feb80_0 .net "out0", 0 0, L_0x2a4c1e0; 1 drivers +v0x25fec20_0 .net "out1", 0 0, L_0x2a4c320; 1 drivers +v0x25fe8e0_0 .net "out2", 0 0, L_0x2a4c410; 1 drivers +v0x25fe980_0 .net "out3", 0 0, L_0x2a4c500; 1 drivers +S_0x25fae50 .scope module, "OneMux" "FourInMux" 3 400, 3 125, S_0x25f31f0; + .timescale -9 -12; +L_0x2a4cde0/d .functor NOT 1, L_0x2a4e620, C4<0>, C4<0>, C4<0>; +L_0x2a4cde0 .delay (10000,10000,10000) L_0x2a4cde0/d; +L_0x2a4df00/d .functor NOT 1, L_0x2a4cf10, C4<0>, C4<0>, C4<0>; +L_0x2a4df00 .delay (10000,10000,10000) L_0x2a4df00/d; +L_0x2a4dfa0/d .functor NAND 1, L_0x2a4cde0, L_0x2a4df00, L_0x2a4d040, C4<1>; +L_0x2a4dfa0 .delay (10000,10000,10000) L_0x2a4dfa0/d; +L_0x2a4e0e0/d .functor NAND 1, L_0x2a4e620, L_0x2a4df00, L_0x2a4d0e0, C4<1>; +L_0x2a4e0e0 .delay (10000,10000,10000) L_0x2a4e0e0/d; +L_0x2a4e1d0/d .functor NAND 1, L_0x2a4cde0, L_0x2a4cf10, L_0x2a4d180, C4<1>; +L_0x2a4e1d0 .delay (10000,10000,10000) L_0x2a4e1d0/d; +L_0x2a4e2c0/d .functor NAND 1, L_0x2a4e620, L_0x2a4cf10, L_0x2a4d270, C4<1>; +L_0x2a4e2c0 .delay (10000,10000,10000) L_0x2a4e2c0/d; +L_0x2a4e3a0/d .functor NAND 1, L_0x2a4dfa0, L_0x2a4e0e0, L_0x2a4e1d0, L_0x2a4e2c0; +L_0x2a4e3a0 .delay (10000,10000,10000) L_0x2a4e3a0/d; +v0x25fb1a0_0 .net "S0", 0 0, L_0x2a4e620; 1 drivers +v0x25fabb0_0 .net "S1", 0 0, L_0x2a4cf10; 1 drivers +v0x25fac50_0 .net "in0", 0 0, L_0x2a4d040; 1 drivers +v0x25f92c0_0 .net "in1", 0 0, L_0x2a4d0e0; 1 drivers +v0x25f9360_0 .net "in2", 0 0, L_0x2a4d180; 1 drivers +v0x25f9010_0 .net "in3", 0 0, L_0x2a4d270; 1 drivers +v0x25fc5d0_0 .net "nS0", 0 0, L_0x2a4cde0; 1 drivers +v0x25fc670_0 .net "nS1", 0 0, L_0x2a4df00; 1 drivers +v0x25f8d60_0 .net "out", 0 0, L_0x2a4e3a0; 1 drivers +v0x25f8e00_0 .net "out0", 0 0, L_0x2a4dfa0; 1 drivers +v0x25f8ac0_0 .net "out1", 0 0, L_0x2a4e0e0; 1 drivers +v0x25f8b60_0 .net "out2", 0 0, L_0x2a4e1d0; 1 drivers +v0x26011d0_0 .net "out3", 0 0, L_0x2a4e2c0; 1 drivers +S_0x25f67b0 .scope module, "TwoMux" "TwoInMux" 3 401, 3 109, S_0x25f31f0; + .timescale -9 -12; +L_0x2a4d360/d .functor NOT 1, L_0x2a4d810, C4<0>, C4<0>, C4<0>; +L_0x2a4d360 .delay (10000,10000,10000) L_0x2a4d360/d; +L_0x2a4d450/d .functor AND 1, L_0x2a4d8b0, L_0x2a4d360, C4<1>, C4<1>; +L_0x2a4d450 .delay (20000,20000,20000) L_0x2a4d450/d; +L_0x2a4d540/d .functor AND 1, L_0x2a4d9a0, L_0x2a4d810, C4<1>, C4<1>; +L_0x2a4d540 .delay (20000,20000,20000) L_0x2a4d540/d; +L_0x2a4d630/d .functor OR 1, L_0x2a4d450, L_0x2a4d540, C4<0>, C4<0>; +L_0x2a4d630 .delay (20000,20000,20000) L_0x2a4d630/d; +v0x25f2f40_0 .net "S", 0 0, L_0x2a4d810; 1 drivers +v0x25f2fe0_0 .net "in0", 0 0, L_0x2a4d8b0; 1 drivers +v0x25f2ca0_0 .net "in1", 0 0, L_0x2a4d9a0; 1 drivers +v0x25f2d40_0 .net "nS", 0 0, L_0x2a4d360; 1 drivers +v0x25fb3b0_0 .net "out0", 0 0, L_0x2a4d450; 1 drivers +v0x25fb450_0 .net "out1", 0 0, L_0x2a4d540; 1 drivers +v0x25fb100_0 .net "outfinal", 0 0, L_0x2a4d630; 1 drivers +S_0x25ddc50 .scope generate, "muxbits[25]" "muxbits[25]" 3 397, 3 397, S_0x25e6a40; + .timescale -9 -12; +P_0x25c98e8 .param/l "i" 3 397, +C4<011001>; +L_0x2a509b0/d .functor OR 1, L_0x2a50af0, L_0x2a50b90, C4<0>, C4<0>; +L_0x2a509b0 .delay (20000,20000,20000) L_0x2a509b0/d; +v0x25f34a0_0 .net *"_s15", 0 0, L_0x2a50af0; 1 drivers +v0x25f3560_0 .net *"_s16", 0 0, L_0x2a50b90; 1 drivers +S_0x25e6f80 .scope module, "ZeroMux" "FourInMux" 3 399, 3 125, S_0x25ddc50; + .timescale -9 -12; +L_0x2a4de00/d .functor NOT 1, L_0x2a4fed0, C4<0>, C4<0>, C4<0>; +L_0x2a4de00 .delay (10000,10000,10000) L_0x2a4de00/d; +L_0x2a4f7b0/d .functor NOT 1, L_0x2a4e750, C4<0>, C4<0>, C4<0>; +L_0x2a4f7b0 .delay (10000,10000,10000) L_0x2a4f7b0/d; +L_0x2a4f850/d .functor NAND 1, L_0x2a4de00, L_0x2a4f7b0, L_0x2a4e880, C4<1>; +L_0x2a4f850 .delay (10000,10000,10000) L_0x2a4f850/d; +L_0x2a4f990/d .functor NAND 1, L_0x2a4fed0, L_0x2a4f7b0, L_0x2a4e920, C4<1>; +L_0x2a4f990 .delay (10000,10000,10000) L_0x2a4f990/d; +L_0x2a4fa80/d .functor NAND 1, L_0x2a4de00, L_0x2a4e750, L_0x2a4e9c0, C4<1>; +L_0x2a4fa80 .delay (10000,10000,10000) L_0x2a4fa80/d; +L_0x2a4fb70/d .functor NAND 1, L_0x2a4fed0, L_0x2a4e750, L_0x2a4eab0, C4<1>; +L_0x2a4fb70 .delay (10000,10000,10000) L_0x2a4fb70/d; +L_0x2a4fc50/d .functor NAND 1, L_0x2a4f850, L_0x2a4f990, L_0x2a4fa80, L_0x2a4fb70; +L_0x2a4fc50 .delay (10000,10000,10000) L_0x2a4fc50/d; +v0x25e9110_0 .net "S0", 0 0, L_0x2a4fed0; 1 drivers +v0x25eeed0_0 .net "S1", 0 0, L_0x2a4e750; 1 drivers +v0x25eef70_0 .net "in0", 0 0, L_0x2a4e880; 1 drivers +v0x25ecde0_0 .net "in1", 0 0, L_0x2a4e920; 1 drivers +v0x25ece80_0 .net "in2", 0 0, L_0x2a4e9c0; 1 drivers +v0x25f5590_0 .net "in3", 0 0, L_0x2a4eab0; 1 drivers +v0x25f5630_0 .net "nS0", 0 0, L_0x2a4de00; 1 drivers +v0x25f52e0_0 .net "nS1", 0 0, L_0x2a4f7b0; 1 drivers +v0x25f5380_0 .net "out", 0 0, L_0x2a4fc50; 1 drivers +v0x25f5030_0 .net "out0", 0 0, L_0x2a4f850; 1 drivers +v0x25f50d0_0 .net "out1", 0 0, L_0x2a4f990; 1 drivers +v0x25f4d90_0 .net "out2", 0 0, L_0x2a4fa80; 1 drivers +v0x25f4e30_0 .net "out3", 0 0, L_0x2a4fb70; 1 drivers +S_0x25dee70 .scope module, "OneMux" "FourInMux" 3 400, 3 125, S_0x25ddc50; + .timescale -9 -12; +L_0x2a4eba0/d .functor NOT 1, L_0x2a4f3b0, C4<0>, C4<0>, C4<0>; +L_0x2a4eba0 .delay (10000,10000,10000) L_0x2a4eba0/d; +L_0x2a4ec90/d .functor NOT 1, L_0x2a4f4e0, C4<0>, C4<0>, C4<0>; +L_0x2a4ec90 .delay (10000,10000,10000) L_0x2a4ec90/d; +L_0x2a4ed30/d .functor NAND 1, L_0x2a4eba0, L_0x2a4ec90, L_0x2a4f610, C4<1>; +L_0x2a4ed30 .delay (10000,10000,10000) L_0x2a4ed30/d; +L_0x2a4ee70/d .functor NAND 1, L_0x2a4f3b0, L_0x2a4ec90, L_0x2a51020, C4<1>; +L_0x2a4ee70 .delay (10000,10000,10000) L_0x2a4ee70/d; +L_0x2a4ef60/d .functor NAND 1, L_0x2a4eba0, L_0x2a4f4e0, L_0x2a50000, C4<1>; +L_0x2a4ef60 .delay (10000,10000,10000) L_0x2a4ef60/d; +L_0x2a4f050/d .functor NAND 1, L_0x2a4f3b0, L_0x2a4f4e0, L_0x2a500f0, C4<1>; +L_0x2a4f050 .delay (10000,10000,10000) L_0x2a4f050/d; +L_0x2a4f130/d .functor NAND 1, L_0x2a4ed30, L_0x2a4ee70, L_0x2a4ef60, L_0x2a4f050; +L_0x2a4f130 .delay (10000,10000,10000) L_0x2a4f130/d; +v0x25db950_0 .net "S0", 0 0, L_0x2a4f3b0; 1 drivers +v0x25db600_0 .net "S1", 0 0, L_0x2a4f4e0; 1 drivers +v0x25db6a0_0 .net "in0", 0 0, L_0x2a4f610; 1 drivers +v0x25db360_0 .net "in1", 0 0, L_0x2a51020; 1 drivers +v0x25db400_0 .net "in2", 0 0, L_0x2a50000; 1 drivers +v0x25e3210_0 .net "in3", 0 0, L_0x2a500f0; 1 drivers +v0x25e16d0_0 .net "nS0", 0 0, L_0x2a4eba0; 1 drivers +v0x25e1770_0 .net "nS1", 0 0, L_0x2a4ec90; 1 drivers +v0x25e1420_0 .net "out", 0 0, L_0x2a4f130; 1 drivers +v0x25e14c0_0 .net "out0", 0 0, L_0x2a4ed30; 1 drivers +v0x25e1180_0 .net "out1", 0 0, L_0x2a4ee70; 1 drivers +v0x25e1220_0 .net "out2", 0 0, L_0x2a4ef60; 1 drivers +v0x25e9070_0 .net "out3", 0 0, L_0x2a4f050; 1 drivers +S_0x25dd9a0 .scope module, "TwoMux" "TwoInMux" 3 401, 3 109, S_0x25ddc50; + .timescale -9 -12; +L_0x2a501e0/d .functor NOT 1, L_0x2a50690, C4<0>, C4<0>, C4<0>; +L_0x2a501e0 .delay (10000,10000,10000) L_0x2a501e0/d; +L_0x2a502d0/d .functor AND 1, L_0x2a50730, L_0x2a501e0, C4<1>, C4<1>; +L_0x2a502d0 .delay (20000,20000,20000) L_0x2a502d0/d; +L_0x2a503c0/d .functor AND 1, L_0x2a50820, L_0x2a50690, C4<1>, C4<1>; +L_0x2a503c0 .delay (20000,20000,20000) L_0x2a503c0/d; +L_0x2a504b0/d .functor OR 1, L_0x2a502d0, L_0x2a503c0, C4<0>, C4<0>; +L_0x2a504b0 .delay (20000,20000,20000) L_0x2a504b0/d; +v0x25dd6f0_0 .net "S", 0 0, L_0x2a50690; 1 drivers +v0x25dd790_0 .net "in0", 0 0, L_0x2a50730; 1 drivers +v0x25dd450_0 .net "in1", 0 0, L_0x2a50820; 1 drivers +v0x25dd4f0_0 .net "nS", 0 0, L_0x2a501e0; 1 drivers +v0x25dbb60_0 .net "out0", 0 0, L_0x2a502d0; 1 drivers +v0x25dbc00_0 .net "out1", 0 0, L_0x2a503c0; 1 drivers +v0x25db8b0_0 .net "outfinal", 0 0, L_0x2a504b0; 1 drivers +S_0x25bfd10 .scope generate, "muxbits[26]" "muxbits[26]" 3 397, 3 397, S_0x25e6a40; + .timescale -9 -12; +P_0x25b2308 .param/l "i" 3 397, +C4<011010>; +L_0x2a52fd0/d .functor OR 1, L_0x2a53110, L_0x2a531b0, C4<0>, C4<0>; +L_0x2a52fd0 .delay (20000,20000,20000) L_0x2a52fd0/d; +v0x25d5540_0 .net *"_s15", 0 0, L_0x2a53110; 1 drivers +v0x25d5600_0 .net *"_s16", 0 0, L_0x2a531b0; 1 drivers +S_0x25d7b80 .scope module, "ZeroMux" "FourInMux" 3 399, 3 125, S_0x25bfd10; + .timescale -9 -12; +L_0x2a50c80/d .functor NOT 1, L_0x2a510c0, C4<0>, C4<0>, C4<0>; +L_0x2a50c80 .delay (10000,10000,10000) L_0x2a50c80/d; +L_0x2a50d70/d .functor NOT 1, L_0x2a511f0, C4<0>, C4<0>, C4<0>; +L_0x2a50d70 .delay (10000,10000,10000) L_0x2a50d70/d; +L_0x2a50e10/d .functor NAND 1, L_0x2a50c80, L_0x2a50d70, L_0x2a51320, C4<1>; +L_0x2a50e10 .delay (10000,10000,10000) L_0x2a50e10/d; +L_0x2a50f50/d .functor NAND 1, L_0x2a510c0, L_0x2a50d70, L_0x2a513c0, C4<1>; +L_0x2a50f50 .delay (10000,10000,10000) L_0x2a50f50/d; +L_0x2a52130/d .functor NAND 1, L_0x2a50c80, L_0x2a511f0, L_0x2a51460, C4<1>; +L_0x2a52130 .delay (10000,10000,10000) L_0x2a52130/d; +L_0x2a52220/d .functor NAND 1, L_0x2a510c0, L_0x2a511f0, L_0x2a51550, C4<1>; +L_0x2a52220 .delay (10000,10000,10000) L_0x2a52220/d; +L_0x2a52300/d .functor NAND 1, L_0x2a50e10, L_0x2a50f50, L_0x2a52130, L_0x2a52220; +L_0x2a52300 .delay (10000,10000,10000) L_0x2a52300/d; +v0x25d7ed0_0 .net "S0", 0 0, L_0x2a510c0; 1 drivers +v0x25d78d0_0 .net "S1", 0 0, L_0x2a511f0; 1 drivers +v0x25d7970_0 .net "in0", 0 0, L_0x2a51320; 1 drivers +v0x25d7630_0 .net "in1", 0 0, L_0x2a513c0; 1 drivers +v0x25d76d0_0 .net "in2", 0 0, L_0x2a51460; 1 drivers +v0x25d5d40_0 .net "in3", 0 0, L_0x2a51550; 1 drivers +v0x25d5de0_0 .net "nS0", 0 0, L_0x2a50c80; 1 drivers +v0x25d5a90_0 .net "nS1", 0 0, L_0x2a50d70; 1 drivers +v0x25d5b30_0 .net "out", 0 0, L_0x2a52300; 1 drivers +v0x25d9050_0 .net "out0", 0 0, L_0x2a50e10; 1 drivers +v0x25d90f0_0 .net "out1", 0 0, L_0x2a50f50; 1 drivers +v0x25d57e0_0 .net "out2", 0 0, L_0x2a52130; 1 drivers +v0x25d5880_0 .net "out3", 0 0, L_0x2a52220; 1 drivers +S_0x25c5af0 .scope module, "OneMux" "FourInMux" 3 400, 3 125, S_0x25bfd10; + .timescale -9 -12; +L_0x2a51640/d .functor NOT 1, L_0x2a51e50, C4<0>, C4<0>, C4<0>; +L_0x2a51640 .delay (10000,10000,10000) L_0x2a51640/d; +L_0x2a51730/d .functor NOT 1, L_0x2a51f80, C4<0>, C4<0>, C4<0>; +L_0x2a51730 .delay (10000,10000,10000) L_0x2a51730/d; +L_0x2a517d0/d .functor NAND 1, L_0x2a51640, L_0x2a51730, L_0x2a53640, C4<1>; +L_0x2a517d0 .delay (10000,10000,10000) L_0x2a517d0/d; +L_0x2a51910/d .functor NAND 1, L_0x2a51e50, L_0x2a51730, L_0x2a52580, C4<1>; +L_0x2a51910 .delay (10000,10000,10000) L_0x2a51910/d; +L_0x2a51a00/d .functor NAND 1, L_0x2a51640, L_0x2a51f80, L_0x2a52620, C4<1>; +L_0x2a51a00 .delay (10000,10000,10000) L_0x2a51a00/d; +L_0x2a51af0/d .functor NAND 1, L_0x2a51e50, L_0x2a51f80, L_0x2a52710, C4<1>; +L_0x2a51af0 .delay (10000,10000,10000) L_0x2a51af0/d; +L_0x2a51bd0/d .functor NAND 1, L_0x2a517d0, L_0x2a51910, L_0x2a51a00, L_0x2a51af0; +L_0x2a51bd0 .delay (10000,10000,10000) L_0x2a51bd0/d; +v0x25bdcc0_0 .net "S0", 0 0, L_0x2a51e50; 1 drivers +v0x25c3a00_0 .net "S1", 0 0, L_0x2a51f80; 1 drivers +v0x25c3aa0_0 .net "in0", 0 0, L_0x2a53640; 1 drivers +v0x25cb950_0 .net "in1", 0 0, L_0x2a52580; 1 drivers +v0x25cb9f0_0 .net "in2", 0 0, L_0x2a52620; 1 drivers +v0x25c9860_0 .net "in3", 0 0, L_0x2a52710; 1 drivers +v0x25d2010_0 .net "nS0", 0 0, L_0x2a51640; 1 drivers +v0x25d20b0_0 .net "nS1", 0 0, L_0x2a51730; 1 drivers +v0x25d3230_0 .net "out", 0 0, L_0x2a51bd0; 1 drivers +v0x25d32d0_0 .net "out0", 0 0, L_0x2a517d0; 1 drivers +v0x25cf6c0_0 .net "out1", 0 0, L_0x2a51910; 1 drivers +v0x25cf760_0 .net "out2", 0 0, L_0x2a51a00; 1 drivers +v0x25d7e30_0 .net "out3", 0 0, L_0x2a51af0; 1 drivers +S_0x25be420 .scope module, "TwoMux" "TwoInMux" 3 401, 3 109, S_0x25bfd10; + .timescale -9 -12; +L_0x2a52800/d .functor NOT 1, L_0x2a52cb0, C4<0>, C4<0>, C4<0>; +L_0x2a52800 .delay (10000,10000,10000) L_0x2a52800/d; +L_0x2a528f0/d .functor AND 1, L_0x2a52d50, L_0x2a52800, C4<1>, C4<1>; +L_0x2a528f0 .delay (20000,20000,20000) L_0x2a528f0/d; +L_0x2a529e0/d .functor AND 1, L_0x2a52e40, L_0x2a52cb0, C4<1>, C4<1>; +L_0x2a529e0 .delay (20000,20000,20000) L_0x2a529e0/d; +L_0x2a52ad0/d .functor OR 1, L_0x2a528f0, L_0x2a529e0, C4<0>, C4<0>; +L_0x2a52ad0 .delay (20000,20000,20000) L_0x2a52ad0/d; +v0x25be170_0 .net "S", 0 0, L_0x2a52cb0; 1 drivers +v0x25be230_0 .net "in0", 0 0, L_0x2a52d50; 1 drivers +v0x25c1730_0 .net "in1", 0 0, L_0x2a52e40; 1 drivers +v0x25c17d0_0 .net "nS", 0 0, L_0x2a52800; 1 drivers +v0x25bdec0_0 .net "out0", 0 0, L_0x2a528f0; 1 drivers +v0x25bdf60_0 .net "out1", 0 0, L_0x2a529e0; 1 drivers +v0x25bdc20_0 .net "outfinal", 0 0, L_0x2a52ad0; 1 drivers +S_0x25ae210 .scope generate, "muxbits[27]" "muxbits[27]" 3 397, 3 397, S_0x25e6a40; + .timescale -9 -12; +P_0x259c818 .param/l "i" 3 397, +C4<011011>; +L_0x2a55550/d .functor OR 1, L_0x2a55690, L_0x2a55730, C4<0>, C4<0>; +L_0x2a55550 .delay (20000,20000,20000) L_0x2a55550/d; +v0x25bffb0_0 .net *"_s15", 0 0, L_0x2a55690; 1 drivers +v0x25c0070_0 .net *"_s16", 0 0, L_0x2a55730; 1 drivers +S_0x25b8600 .scope module, "ZeroMux" "FourInMux" 3 399, 3 125, S_0x25ae210; + .timescale -9 -12; +L_0x2a532a0/d .functor NOT 1, L_0x2a54c50, C4<0>, C4<0>, C4<0>; +L_0x2a532a0 .delay (10000,10000,10000) L_0x2a532a0/d; +L_0x2a53390/d .functor NOT 1, L_0x2a536e0, C4<0>, C4<0>, C4<0>; +L_0x2a53390 .delay (10000,10000,10000) L_0x2a53390/d; +L_0x2a53430/d .functor NAND 1, L_0x2a532a0, L_0x2a53390, L_0x2a53810, C4<1>; +L_0x2a53430 .delay (10000,10000,10000) L_0x2a53430/d; +L_0x2a53570/d .functor NAND 1, L_0x2a54c50, L_0x2a53390, L_0x2a538b0, C4<1>; +L_0x2a53570 .delay (10000,10000,10000) L_0x2a53570/d; +L_0x2a54800/d .functor NAND 1, L_0x2a532a0, L_0x2a536e0, L_0x2a53950, C4<1>; +L_0x2a54800 .delay (10000,10000,10000) L_0x2a54800/d; +L_0x2a548f0/d .functor NAND 1, L_0x2a54c50, L_0x2a536e0, L_0x2a53a40, C4<1>; +L_0x2a548f0 .delay (10000,10000,10000) L_0x2a548f0/d; +L_0x2a549d0/d .functor NAND 1, L_0x2a53430, L_0x2a53570, L_0x2a54800, L_0x2a548f0; +L_0x2a549d0 .delay (10000,10000,10000) L_0x2a549d0/d; +v0x25b9f90_0 .net "S0", 0 0, L_0x2a54c50; 1 drivers +v0x25b8350_0 .net "S1", 0 0, L_0x2a536e0; 1 drivers +v0x25b83f0_0 .net "in0", 0 0, L_0x2a53810; 1 drivers +v0x25bb910_0 .net "in1", 0 0, L_0x2a538b0; 1 drivers +v0x25bb9b0_0 .net "in2", 0 0, L_0x2a53950; 1 drivers +v0x25b80a0_0 .net "in3", 0 0, L_0x2a53a40; 1 drivers +v0x25b8140_0 .net "nS0", 0 0, L_0x2a532a0; 1 drivers +v0x25b7e00_0 .net "nS1", 0 0, L_0x2a53390; 1 drivers +v0x25b7ea0_0 .net "out", 0 0, L_0x2a549d0; 1 drivers +v0x25c0510_0 .net "out0", 0 0, L_0x2a53430; 1 drivers +v0x25c05b0_0 .net "out1", 0 0, L_0x2a53570; 1 drivers +v0x25c0260_0 .net "out2", 0 0, L_0x2a54800; 1 drivers +v0x25c0300_0 .net "out3", 0 0, L_0x2a548f0; 1 drivers +S_0x25b27e0 .scope module, "OneMux" "FourInMux" 3 400, 3 125, S_0x25ae210; + .timescale -9 -12; +L_0x2a53b30/d .functor NOT 1, L_0x2a54340, C4<0>, C4<0>, C4<0>; +L_0x2a53b30 .delay (10000,10000,10000) L_0x2a53b30/d; +L_0x2a53c20/d .functor NOT 1, L_0x2a54470, C4<0>, C4<0>, C4<0>; +L_0x2a53c20 .delay (10000,10000,10000) L_0x2a53c20/d; +L_0x2a53cc0/d .functor NAND 1, L_0x2a53b30, L_0x2a53c20, L_0x2a545a0, C4<1>; +L_0x2a53cc0 .delay (10000,10000,10000) L_0x2a53cc0/d; +L_0x2a53e00/d .functor NAND 1, L_0x2a54340, L_0x2a53c20, L_0x2a54640, C4<1>; +L_0x2a53e00 .delay (10000,10000,10000) L_0x2a53e00/d; +L_0x2a53ef0/d .functor NAND 1, L_0x2a53b30, L_0x2a54470, L_0x2a546e0, C4<1>; +L_0x2a53ef0 .delay (10000,10000,10000) L_0x2a53ef0/d; +L_0x2a53fe0/d .functor NAND 1, L_0x2a54340, L_0x2a54470, L_0x2a55f00, C4<1>; +L_0x2a53fe0 .delay (10000,10000,10000) L_0x2a53fe0/d; +L_0x2a540c0/d .functor NAND 1, L_0x2a53cc0, L_0x2a53e00, L_0x2a53ef0, L_0x2a53fe0; +L_0x2a540c0 .delay (10000,10000,10000) L_0x2a540c0/d; +v0x25b4170_0 .net "S0", 0 0, L_0x2a54340; 1 drivers +v0x25b2530_0 .net "S1", 0 0, L_0x2a54470; 1 drivers +v0x25b25d0_0 .net "in0", 0 0, L_0x2a545a0; 1 drivers +v0x25b5af0_0 .net "in1", 0 0, L_0x2a54640; 1 drivers +v0x25b5b90_0 .net "in2", 0 0, L_0x2a546e0; 1 drivers +v0x25b2280_0 .net "in3", 0 0, L_0x2a55f00; 1 drivers +v0x25ba6f0_0 .net "nS0", 0 0, L_0x2a53b30; 1 drivers +v0x25ba790_0 .net "nS1", 0 0, L_0x2a53c20; 1 drivers +v0x25ba440_0 .net "out", 0 0, L_0x2a540c0; 1 drivers +v0x25ba4e0_0 .net "out0", 0 0, L_0x2a53cc0; 1 drivers +v0x25ba190_0 .net "out1", 0 0, L_0x2a53e00; 1 drivers +v0x25ba230_0 .net "out2", 0 0, L_0x2a53ef0; 1 drivers +v0x25b9ef0_0 .net "out3", 0 0, L_0x2a53fe0; 1 drivers +S_0x25ac120 .scope module, "TwoMux" "TwoInMux" 3 401, 3 109, S_0x25ae210; + .timescale -9 -12; +L_0x2a54d80/d .functor NOT 1, L_0x2a55230, C4<0>, C4<0>, C4<0>; +L_0x2a54d80 .delay (10000,10000,10000) L_0x2a54d80/d; +L_0x2a54e70/d .functor AND 1, L_0x2a552d0, L_0x2a54d80, C4<1>, C4<1>; +L_0x2a54e70 .delay (20000,20000,20000) L_0x2a54e70/d; +L_0x2a54f60/d .functor AND 1, L_0x2a553c0, L_0x2a55230, C4<1>, C4<1>; +L_0x2a54f60 .delay (20000,20000,20000) L_0x2a54f60/d; +L_0x2a55050/d .functor OR 1, L_0x2a54e70, L_0x2a54f60, C4<0>, C4<0>; +L_0x2a55050 .delay (20000,20000,20000) L_0x2a55050/d; +v0x25b48d0_0 .net "S", 0 0, L_0x2a55230; 1 drivers +v0x25b4990_0 .net "in0", 0 0, L_0x2a552d0; 1 drivers +v0x25b4620_0 .net "in1", 0 0, L_0x2a553c0; 1 drivers +v0x25b46c0_0 .net "nS", 0 0, L_0x2a54d80; 1 drivers +v0x25b4370_0 .net "out0", 0 0, L_0x2a54e70; 1 drivers +v0x25b4410_0 .net "out1", 0 0, L_0x2a54f60; 1 drivers +v0x25b40d0_0 .net "outfinal", 0 0, L_0x2a55050; 1 drivers +S_0x2596970 .scope generate, "muxbits[28]" "muxbits[28]" 3 397, 3 397, S_0x25e6a40; + .timescale -9 -12; +P_0x2723898 .param/l "i" 3 397, +C4<011100>; +L_0x2a57b60/d .functor OR 1, L_0x2a57ca0, L_0x2a57d40, C4<0>, C4<0>; +L_0x2a57b60 .delay (20000,20000,20000) L_0x2a57b60/d; +v0x25a62c0_0 .net *"_s15", 0 0, L_0x2a57ca0; 1 drivers +v0x25a6380_0 .net *"_s16", 0 0, L_0x2a57d40; 1 drivers +S_0x259a6a0 .scope module, "ZeroMux" "FourInMux" 3 399, 3 125, S_0x2596970; + .timescale -9 -12; +L_0x2a55820/d .functor NOT 1, L_0x2a55ff0, C4<0>, C4<0>, C4<0>; +L_0x2a55820 .delay (10000,10000,10000) L_0x2a55820/d; +L_0x2a55910/d .functor NOT 1, L_0x2a56120, C4<0>, C4<0>, C4<0>; +L_0x2a55910 .delay (10000,10000,10000) L_0x2a55910/d; +L_0x2a559b0/d .functor NAND 1, L_0x2a55820, L_0x2a55910, L_0x2a56250, C4<1>; +L_0x2a559b0 .delay (10000,10000,10000) L_0x2a559b0/d; +L_0x2a55af0/d .functor NAND 1, L_0x2a55ff0, L_0x2a55910, L_0x2a562f0, C4<1>; +L_0x2a55af0 .delay (10000,10000,10000) L_0x2a55af0/d; +L_0x2a55be0/d .functor NAND 1, L_0x2a55820, L_0x2a56120, L_0x2a56390, C4<1>; +L_0x2a55be0 .delay (10000,10000,10000) L_0x2a55be0/d; +L_0x2a55cd0/d .functor NAND 1, L_0x2a55ff0, L_0x2a56120, L_0x2a56480, C4<1>; +L_0x2a55cd0 .delay (10000,10000,10000) L_0x2a55cd0/d; +L_0x2a55db0/d .functor NAND 1, L_0x2a559b0, L_0x2a55af0, L_0x2a55be0, L_0x2a55cd0; +L_0x2a55db0 .delay (10000,10000,10000) L_0x2a55db0/d; +v0x259a9e0_0 .net "S0", 0 0, L_0x2a55ff0; 1 drivers +v0x25a2550_0 .net "S1", 0 0, L_0x2a56120; 1 drivers +v0x25a25f0_0 .net "in0", 0 0, L_0x2a56250; 1 drivers +v0x25a0cc0_0 .net "in1", 0 0, L_0x2a562f0; 1 drivers +v0x25a0d60_0 .net "in2", 0 0, L_0x2a56390; 1 drivers +v0x25a0a10_0 .net "in3", 0 0, L_0x2a56480; 1 drivers +v0x25a0ab0_0 .net "nS0", 0 0, L_0x2a55820; 1 drivers +v0x25a0760_0 .net "nS1", 0 0, L_0x2a55910; 1 drivers +v0x25a0800_0 .net "out", 0 0, L_0x2a55db0; 1 drivers +v0x25a04c0_0 .net "out0", 0 0, L_0x2a559b0; 1 drivers +v0x25a0560_0 .net "out1", 0 0, L_0x2a55af0; 1 drivers +v0x25a83b0_0 .net "out2", 0 0, L_0x2a55be0; 1 drivers +v0x25a8450_0 .net "out3", 0 0, L_0x2a55cd0; 1 drivers +S_0x259cf90 .scope module, "OneMux" "FourInMux" 3 400, 3 125, S_0x2596970; + .timescale -9 -12; +L_0x2a56570/d .functor NOT 1, L_0x2a56d80, C4<0>, C4<0>, C4<0>; +L_0x2a56570 .delay (10000,10000,10000) L_0x2a56570/d; +L_0x2a56660/d .functor NOT 1, L_0x2a56eb0, C4<0>, C4<0>, C4<0>; +L_0x2a56660 .delay (10000,10000,10000) L_0x2a56660/d; +L_0x2a56700/d .functor NAND 1, L_0x2a56570, L_0x2a56660, L_0x2a56fe0, C4<1>; +L_0x2a56700 .delay (10000,10000,10000) L_0x2a56700/d; +L_0x2a56840/d .functor NAND 1, L_0x2a56d80, L_0x2a56660, L_0x2a57080, C4<1>; +L_0x2a56840 .delay (10000,10000,10000) L_0x2a56840/d; +L_0x2a56930/d .functor NAND 1, L_0x2a56570, L_0x2a56eb0, L_0x2a58500, C4<1>; +L_0x2a56930 .delay (10000,10000,10000) L_0x2a56930/d; +L_0x2a56a20/d .functor NAND 1, L_0x2a56d80, L_0x2a56eb0, L_0x2a572e0, C4<1>; +L_0x2a56a20 .delay (10000,10000,10000) L_0x2a56a20/d; +L_0x2a56b00/d .functor NAND 1, L_0x2a56700, L_0x2a56840, L_0x2a56930, L_0x2a56a20; +L_0x2a56b00 .delay (10000,10000,10000) L_0x2a56b00/d; +v0x2594920_0 .net "S0", 0 0, L_0x2a56d80; 1 drivers +v0x259cce0_0 .net "S1", 0 0, L_0x2a56eb0; 1 drivers +v0x259cd80_0 .net "in0", 0 0, L_0x2a56fe0; 1 drivers +v0x259ca30_0 .net "in1", 0 0, L_0x2a57080; 1 drivers +v0x259cad0_0 .net "in2", 0 0, L_0x2a58500; 1 drivers +v0x259c790_0 .net "in3", 0 0, L_0x2a572e0; 1 drivers +v0x259aea0_0 .net "nS0", 0 0, L_0x2a56570; 1 drivers +v0x259af40_0 .net "nS1", 0 0, L_0x2a56660; 1 drivers +v0x259abf0_0 .net "out", 0 0, L_0x2a56b00; 1 drivers +v0x259ac90_0 .net "out0", 0 0, L_0x2a56700; 1 drivers +v0x259e1b0_0 .net "out1", 0 0, L_0x2a56840; 1 drivers +v0x259e250_0 .net "out2", 0 0, L_0x2a56930; 1 drivers +v0x259a940_0 .net "out3", 0 0, L_0x2a56a20; 1 drivers +S_0x2595080 .scope module, "TwoMux" "TwoInMux" 3 401, 3 109, S_0x2596970; + .timescale -9 -12; +L_0x2a573d0/d .functor NOT 1, L_0x2a57840, C4<0>, C4<0>, C4<0>; +L_0x2a573d0 .delay (10000,10000,10000) L_0x2a573d0/d; +L_0x2a57480/d .functor AND 1, L_0x2a578e0, L_0x2a573d0, C4<1>, C4<1>; +L_0x2a57480 .delay (20000,20000,20000) L_0x2a57480/d; +L_0x2a57570/d .functor AND 1, L_0x2a579d0, L_0x2a57840, C4<1>, C4<1>; +L_0x2a57570 .delay (20000,20000,20000) L_0x2a57570/d; +L_0x2a57660/d .functor OR 1, L_0x2a57480, L_0x2a57570, C4<0>, C4<0>; +L_0x2a57660 .delay (20000,20000,20000) L_0x2a57660/d; +v0x2594dd0_0 .net "S", 0 0, L_0x2a57840; 1 drivers +v0x2594e90_0 .net "in0", 0 0, L_0x2a578e0; 1 drivers +v0x2598390_0 .net "in1", 0 0, L_0x2a579d0; 1 drivers +v0x2598430_0 .net "nS", 0 0, L_0x2a573d0; 1 drivers +v0x2594b20_0 .net "out0", 0 0, L_0x2a57480; 1 drivers +v0x2594bc0_0 .net "out1", 0 0, L_0x2a57570; 1 drivers +v0x2594880_0 .net "outfinal", 0 0, L_0x2a57660; 1 drivers +S_0x2646f50 .scope generate, "muxbits[29]" "muxbits[29]" 3 397, 3 397, S_0x25e6a40; + .timescale -9 -12; +P_0x264d3a8 .param/l "i" 3 397, +C4<011101>; +L_0x2a5a530/d .functor OR 1, L_0x2a5a670, L_0x2a5a710, C4<0>, C4<0>; +L_0x2a5a530 .delay (20000,20000,20000) L_0x2a5a530/d; +v0x2596c10_0 .net *"_s15", 0 0, L_0x2a5a670; 1 drivers +v0x2596cd0_0 .net *"_s16", 0 0, L_0x2a5a710; 1 drivers +S_0x27150d0 .scope module, "ZeroMux" "FourInMux" 3 399, 3 125, S_0x2646f50; + .timescale -9 -12; +L_0x2a57e30/d .functor NOT 1, L_0x2a59950, C4<0>, C4<0>, C4<0>; +L_0x2a57e30 .delay (10000,10000,10000) L_0x2a57e30/d; +L_0x2a57f20/d .functor NOT 1, L_0x2a585a0, C4<0>, C4<0>, C4<0>; +L_0x2a57f20 .delay (10000,10000,10000) L_0x2a57f20/d; +L_0x2a57fc0/d .functor NAND 1, L_0x2a57e30, L_0x2a57f20, L_0x2a586d0, C4<1>; +L_0x2a57fc0 .delay (10000,10000,10000) L_0x2a57fc0/d; +L_0x2a58100/d .functor NAND 1, L_0x2a59950, L_0x2a57f20, L_0x2a58770, C4<1>; +L_0x2a58100 .delay (10000,10000,10000) L_0x2a58100/d; +L_0x2a581f0/d .functor NAND 1, L_0x2a57e30, L_0x2a585a0, L_0x2a58810, C4<1>; +L_0x2a581f0 .delay (10000,10000,10000) L_0x2a581f0/d; +L_0x2a582e0/d .functor NAND 1, L_0x2a59950, L_0x2a585a0, L_0x2a58900, C4<1>; +L_0x2a582e0 .delay (10000,10000,10000) L_0x2a582e0/d; +L_0x2a583c0/d .functor NAND 1, L_0x2a57fc0, L_0x2a58100, L_0x2a581f0, L_0x2a582e0; +L_0x2a583c0 .delay (10000,10000,10000) L_0x2a583c0/d; +v0x2717fb0_0 .net "S0", 0 0, L_0x2a59950; 1 drivers +v0x26e2350_0 .net "S1", 0 0, L_0x2a585a0; 1 drivers +v0x26e23f0_0 .net "in0", 0 0, L_0x2a586d0; 1 drivers +v0x273d6e0_0 .net "in1", 0 0, L_0x2a58770; 1 drivers +v0x273d780_0 .net "in2", 0 0, L_0x2a58810; 1 drivers +v0x2590a50_0 .net "in3", 0 0, L_0x2a58900; 1 drivers +v0x2590af0_0 .net "nS0", 0 0, L_0x2a57e30; 1 drivers +v0x2592540_0 .net "nS1", 0 0, L_0x2a57f20; 1 drivers +v0x25925e0_0 .net "out", 0 0, L_0x2a583c0; 1 drivers +v0x2597170_0 .net "out0", 0 0, L_0x2a57fc0; 1 drivers +v0x2597210_0 .net "out1", 0 0, L_0x2a58100; 1 drivers +v0x2596ec0_0 .net "out2", 0 0, L_0x2a581f0; 1 drivers +v0x2596f60_0 .net "out3", 0 0, L_0x2a582e0; 1 drivers +S_0x273a6d0 .scope module, "OneMux" "FourInMux" 3 400, 3 125, S_0x2646f50; + .timescale -9 -12; +L_0x29cdc40/d .functor NOT 1, L_0x2a59600, C4<0>, C4<0>, C4<0>; +L_0x29cdc40 .delay (10000,10000,10000) L_0x29cdc40/d; +L_0x29cdd30/d .functor NOT 1, L_0x2a59730, C4<0>, C4<0>, C4<0>; +L_0x29cdd30 .delay (10000,10000,10000) L_0x29cdd30/d; +L_0x29cddd0/d .functor NAND 1, L_0x29cdc40, L_0x29cdd30, L_0x2a59a80, C4<1>; +L_0x29cddd0 .delay (10000,10000,10000) L_0x29cddd0/d; +L_0x29cdf10/d .functor NAND 1, L_0x2a59600, L_0x29cdd30, L_0x2a59b20, C4<1>; +L_0x29cdf10 .delay (10000,10000,10000) L_0x29cdf10/d; +L_0x2a59200/d .functor NAND 1, L_0x29cdc40, L_0x2a59730, L_0x2a59bc0, C4<1>; +L_0x2a59200 .delay (10000,10000,10000) L_0x2a59200/d; +L_0x2a592a0/d .functor NAND 1, L_0x2a59600, L_0x2a59730, L_0x2a59cb0, C4<1>; +L_0x2a592a0 .delay (10000,10000,10000) L_0x2a592a0/d; +L_0x2a59380/d .functor NAND 1, L_0x29cddd0, L_0x29cdf10, L_0x2a59200, L_0x2a592a0; +L_0x2a59380 .delay (10000,10000,10000) L_0x2a59380/d; +v0x26f57f0_0 .net "S0", 0 0, L_0x2a59600; 1 drivers +v0x2737890_0 .net "S1", 0 0, L_0x2a59730; 1 drivers +v0x2737930_0 .net "in0", 0 0, L_0x2a59a80; 1 drivers +v0x2734a50_0 .net "in1", 0 0, L_0x2a59b20; 1 drivers +v0x2734af0_0 .net "in2", 0 0, L_0x2a59bc0; 1 drivers +v0x2723810_0 .net "in3", 0 0, L_0x2a59cb0; 1 drivers +v0x27209d0_0 .net "nS0", 0 0, L_0x29cdc40; 1 drivers +v0x2720a70_0 .net "nS1", 0 0, L_0x29cdd30; 1 drivers +v0x271db90_0 .net "out", 0 0, L_0x2a59380; 1 drivers +v0x271dc30_0 .net "out0", 0 0, L_0x29cddd0; 1 drivers +v0x271ad50_0 .net "out1", 0 0, L_0x29cdf10; 1 drivers +v0x271adf0_0 .net "out2", 0 0, L_0x2a59200; 1 drivers +v0x2717f10_0 .net "out3", 0 0, L_0x2a592a0; 1 drivers +S_0x2701050 .scope module, "TwoMux" "TwoInMux" 3 401, 3 109, S_0x2646f50; + .timescale -9 -12; +L_0x2a59da0/d .functor NOT 1, L_0x2a5a210, C4<0>, C4<0>, C4<0>; +L_0x2a59da0 .delay (10000,10000,10000) L_0x2a59da0/d; +L_0x2a59e50/d .functor AND 1, L_0x2a5a2b0, L_0x2a59da0, C4<1>, C4<1>; +L_0x2a59e50 .delay (20000,20000,20000) L_0x2a59e50/d; +L_0x2a59f40/d .functor AND 1, L_0x2a5a3a0, L_0x2a5a210, C4<1>, C4<1>; +L_0x2a59f40 .delay (20000,20000,20000) L_0x2a59f40/d; +L_0x2a5a030/d .functor OR 1, L_0x2a59e50, L_0x2a59f40, C4<0>, C4<0>; +L_0x2a5a030 .delay (20000,20000,20000) L_0x2a5a030/d; +v0x26fe210_0 .net "S", 0 0, L_0x2a5a210; 1 drivers +v0x26fe2d0_0 .net "in0", 0 0, L_0x2a5a2b0; 1 drivers +v0x26fb3d0_0 .net "in1", 0 0, L_0x2a5a3a0; 1 drivers +v0x26fb470_0 .net "nS", 0 0, L_0x2a59da0; 1 drivers +v0x26f8590_0 .net "out0", 0 0, L_0x2a59e50; 1 drivers +v0x26f8630_0 .net "out1", 0 0, L_0x2a59f40; 1 drivers +v0x26f5750_0 .net "outfinal", 0 0, L_0x2a5a030; 1 drivers +S_0x26bd790 .scope generate, "muxbits[30]" "muxbits[30]" 3 397, 3 397, S_0x25e6a40; + .timescale -9 -12; +P_0x25eea88 .param/l "i" 3 397, +C4<011110>; +L_0x2a5c6f0/d .functor OR 1, L_0x2a5c830, L_0x2a5c8d0, C4<0>, C4<0>; +L_0x2a5c6f0 .delay (20000,20000,20000) L_0x2a5c6f0/d; +v0x2665160_0 .net *"_s15", 0 0, L_0x2a5c830; 1 drivers +v0x2665220_0 .net *"_s16", 0 0, L_0x2a5c8d0; 1 drivers +S_0x2686800 .scope module, "ZeroMux" "FourInMux" 3 399, 3 125, S_0x26bd790; + .timescale -9 -12; +L_0x2a5a800/d .functor NOT 1, L_0x2a5adc0, C4<0>, C4<0>, C4<0>; +L_0x2a5a800 .delay (10000,10000,10000) L_0x2a5a800/d; +L_0x2a5a8f0/d .functor NOT 1, L_0x2a5aef0, C4<0>, C4<0>, C4<0>; +L_0x2a5a8f0 .delay (10000,10000,10000) L_0x2a5a8f0/d; +L_0x2a5a990/d .functor NAND 1, L_0x2a5a800, L_0x2a5a8f0, L_0x2a5b020, C4<1>; +L_0x2a5a990 .delay (10000,10000,10000) L_0x2a5a990/d; +L_0x2a5aad0/d .functor NAND 1, L_0x2a5adc0, L_0x2a5a8f0, L_0x2a5b0c0, C4<1>; +L_0x2a5aad0 .delay (10000,10000,10000) L_0x2a5aad0/d; +L_0x2a5abc0/d .functor NAND 1, L_0x2a5a800, L_0x2a5aef0, L_0x2a5b160, C4<1>; +L_0x2a5abc0 .delay (10000,10000,10000) L_0x2a5abc0/d; +L_0x2a5acb0/d .functor NAND 1, L_0x2a5adc0, L_0x2a5aef0, L_0x2a5b250, C4<1>; +L_0x2a5acb0 .delay (10000,10000,10000) L_0x2a5acb0/d; +L_0x2a5c150/d .functor NAND 1, L_0x2a5a990, L_0x2a5aad0, L_0x2a5abc0, L_0x2a5acb0; +L_0x2a5c150 .delay (10000,10000,10000) L_0x2a5c150/d; +v0x268b510_0 .net "S0", 0 0, L_0x2a5adc0; 1 drivers +v0x267f6a0_0 .net "S1", 0 0, L_0x2a5aef0; 1 drivers +v0x267f740_0 .net "in0", 0 0, L_0x2a5b020; 1 drivers +v0x267a9f0_0 .net "in1", 0 0, L_0x2a5b0c0; 1 drivers +v0x267aa90_0 .net "in2", 0 0, L_0x2a5b160; 1 drivers +v0x2675d40_0 .net "in3", 0 0, L_0x2a5b250; 1 drivers +v0x2675de0_0 .net "nS0", 0 0, L_0x2a5a800; 1 drivers +v0x266ea40_0 .net "nS1", 0 0, L_0x2a5a8f0; 1 drivers +v0x266eae0_0 .net "out", 0 0, L_0x2a5c150; 1 drivers +v0x2669dd0_0 .net "out0", 0 0, L_0x2a5a990; 1 drivers +v0x2669e70_0 .net "out1", 0 0, L_0x2a5aad0; 1 drivers +v0x2648670_0 .net "out2", 0 0, L_0x2a5abc0; 1 drivers +v0x2648710_0 .net "out3", 0 0, L_0x2a5acb0; 1 drivers +S_0x26a3240 .scope module, "OneMux" "FourInMux" 3 400, 3 125, S_0x26bd790; + .timescale -9 -12; +L_0x2a5b340/d .functor NOT 1, L_0x2a5bb50, C4<0>, C4<0>, C4<0>; +L_0x2a5b340 .delay (10000,10000,10000) L_0x2a5b340/d; +L_0x2a5b430/d .functor NOT 1, L_0x2a5bc80, C4<0>, C4<0>, C4<0>; +L_0x2a5b430 .delay (10000,10000,10000) L_0x2a5b430/d; +L_0x2a5b4d0/d .functor NAND 1, L_0x2a5b340, L_0x2a5b430, L_0x2a5bdb0, C4<1>; +L_0x2a5b4d0 .delay (10000,10000,10000) L_0x2a5b4d0/d; +L_0x2a5b610/d .functor NAND 1, L_0x2a5bb50, L_0x2a5b430, L_0x2a5be50, C4<1>; +L_0x2a5b610 .delay (10000,10000,10000) L_0x2a5b610/d; +L_0x2a5b700/d .functor NAND 1, L_0x2a5b340, L_0x2a5bc80, L_0x2a5bef0, C4<1>; +L_0x2a5b700 .delay (10000,10000,10000) L_0x2a5b700/d; +L_0x2a5b7f0/d .functor NAND 1, L_0x2a5bb50, L_0x2a5bc80, L_0x2a5bfe0, C4<1>; +L_0x2a5b7f0 .delay (10000,10000,10000) L_0x2a5b7f0/d; +L_0x2a5b8d0/d .functor NAND 1, L_0x2a5b4d0, L_0x2a5b610, L_0x2a5b700, L_0x2a5b7f0; +L_0x2a5b8d0 .delay (10000,10000,10000) L_0x2a5b8d0/d; +v0x26a7f50_0 .net "S0", 0 0, L_0x2a5bb50; 1 drivers +v0x26a0d40_0 .net "S1", 0 0, L_0x2a5bc80; 1 drivers +v0x26a0de0_0 .net "in0", 0 0, L_0x2a5bdb0; 1 drivers +v0x269c090_0 .net "in1", 0 0, L_0x2a5be50; 1 drivers +v0x269c130_0 .net "in2", 0 0, L_0x2a5bef0; 1 drivers +v0x264d320_0 .net "in3", 0 0, L_0x2a5bfe0; 1 drivers +v0x26973e0_0 .net "nS0", 0 0, L_0x2a5b340; 1 drivers +v0x2697480_0 .net "nS1", 0 0, L_0x2a5b430; 1 drivers +v0x2692750_0 .net "out", 0 0, L_0x2a5b8d0; 1 drivers +v0x26927f0_0 .net "out0", 0 0, L_0x2a5b4d0; 1 drivers +v0x26900e0_0 .net "out1", 0 0, L_0x2a5b610; 1 drivers +v0x2690180_0 .net "out2", 0 0, L_0x2a5b700; 1 drivers +v0x268b470_0 .net "out3", 0 0, L_0x2a5b7f0; 1 drivers +S_0x26b8ae0 .scope module, "TwoMux" "TwoInMux" 3 401, 3 109, S_0x26bd790; + .timescale -9 -12; +L_0x2a5d750/d .functor NOT 1, L_0x2a5c3d0, C4<0>, C4<0>, C4<0>; +L_0x2a5d750 .delay (10000,10000,10000) L_0x2a5d750/d; +L_0x2a5d840/d .functor AND 1, L_0x2a5c470, L_0x2a5d750, C4<1>, C4<1>; +L_0x2a5d840 .delay (20000,20000,20000) L_0x2a5d840/d; +L_0x2a5d930/d .functor AND 1, L_0x2a5c560, L_0x2a5c3d0, C4<1>, C4<1>; +L_0x2a5d930 .delay (20000,20000,20000) L_0x2a5d930/d; +L_0x2a5da20/d .functor OR 1, L_0x2a5d840, L_0x2a5d930, C4<0>, C4<0>; +L_0x2a5da20 .delay (20000,20000,20000) L_0x2a5da20/d; +v0x26c49c0_0 .net "S", 0 0, L_0x2a5c3d0; 1 drivers +v0x26b3e30_0 .net "in0", 0 0, L_0x2a5c470; 1 drivers +v0x26b3ed0_0 .net "in1", 0 0, L_0x2a5c560; 1 drivers +v0x26b1790_0 .net "nS", 0 0, L_0x2a5d750; 1 drivers +v0x26b1830_0 .net "out0", 0 0, L_0x2a5d840; 1 drivers +v0x26acb20_0 .net "out1", 0 0, L_0x2a5d930; 1 drivers +v0x26a7eb0_0 .net "outfinal", 0 0, L_0x2a5da20; 1 drivers +S_0x25e2cb0 .scope generate, "muxbits[31]" "muxbits[31]" 3 397, 3 397, S_0x25e6a40; + .timescale -9 -12; +P_0x24174c8 .param/l "i" 3 397, +C4<011111>; +L_0x2a5e180/d .functor OR 1, L_0x2a5e280, L_0x2a5e320, C4<0>, C4<0>; +L_0x2a5e180 .delay (20000,20000,20000) L_0x2a5e180/d; +v0x26c9630_0 .net *"_s15", 0 0, L_0x2a5e280; 1 drivers +v0x26c4920_0 .net *"_s16", 0 0, L_0x2a5e320; 1 drivers +S_0x2662b10 .scope module, "ZeroMux" "FourInMux" 3 399, 3 125, S_0x25e2cb0; + .timescale -9 -12; +L_0x2a5c9c0/d .functor NOT 1, L_0x2a5d1d0, C4<0>, C4<0>, C4<0>; +L_0x2a5c9c0 .delay (10000,10000,10000) L_0x2a5c9c0/d; +L_0x2a5cab0/d .functor NOT 1, L_0x2a5d300, C4<0>, C4<0>, C4<0>; +L_0x2a5cab0 .delay (10000,10000,10000) L_0x2a5cab0/d; +L_0x2a5cb50/d .functor NAND 1, L_0x2a5c9c0, L_0x2a5cab0, L_0x2a5d430, C4<1>; +L_0x2a5cb50 .delay (10000,10000,10000) L_0x2a5cb50/d; +L_0x2a5cc90/d .functor NAND 1, L_0x2a5d1d0, L_0x2a5cab0, L_0x2a5d4d0, C4<1>; +L_0x2a5cc90 .delay (10000,10000,10000) L_0x2a5cc90/d; +L_0x2a5cd80/d .functor NAND 1, L_0x2a5c9c0, L_0x2a5d300, L_0x2a5d570, C4<1>; +L_0x2a5cd80 .delay (10000,10000,10000) L_0x2a5cd80/d; +L_0x2a5ce70/d .functor NAND 1, L_0x2a5d1d0, L_0x2a5d300, L_0x2a5d660, C4<1>; +L_0x2a5ce70 .delay (10000,10000,10000) L_0x2a5ce70/d; +L_0x2a5cf50/d .functor NAND 1, L_0x2a5cb50, L_0x2a5cc90, L_0x2a5cd80, L_0x2a5ce70; +L_0x2a5cf50 .delay (10000,10000,10000) L_0x2a5cf50/d; +v0x265dfa0_0 .net "S0", 0 0, L_0x2a5d1d0; 1 drivers +v0x265e060_0 .net "S1", 0 0, L_0x2a5d300; 1 drivers +v0x26592f0_0 .net "in0", 0 0, L_0x2a5d430; 1 drivers +v0x2659390_0 .net "in1", 0 0, L_0x2a5d4d0; 1 drivers +v0x26dadc0_0 .net "in2", 0 0, L_0x2a5d570; 1 drivers +v0x26dae60_0 .net "in3", 0 0, L_0x2a5d660; 1 drivers +v0x26d5520_0 .net "nS0", 0 0, L_0x2a5c9c0; 1 drivers +v0x26d55c0_0 .net "nS1", 0 0, L_0x2a5cab0; 1 drivers +v0x2654640_0 .net "out", 0 0, L_0x2a5cf50; 1 drivers +v0x26546e0_0 .net "out0", 0 0, L_0x2a5cb50; 1 drivers +v0x26ce200_0 .net "out1", 0 0, L_0x2a5cc90; 1 drivers +v0x26ce2a0_0 .net "out2", 0 0, L_0x2a5cd80; 1 drivers +v0x26c9590_0 .net "out3", 0 0, L_0x2a5ce70; 1 drivers +S_0x25c34c0 .scope module, "OneMux" "FourInMux" 3 400, 3 125, S_0x25e2cb0; + .timescale -9 -12; +L_0x2a5eff0/d .functor NOT 1, L_0x2a5dc00, C4<0>, C4<0>, C4<0>; +L_0x2a5eff0 .delay (10000,10000,10000) L_0x2a5eff0/d; +L_0x2a5f0e0/d .functor NOT 1, L_0x2a5dd30, C4<0>, C4<0>, C4<0>; +L_0x2a5f0e0 .delay (10000,10000,10000) L_0x2a5f0e0/d; +L_0x2a5f180/d .functor NAND 1, L_0x2a5eff0, L_0x2a5f0e0, L_0x2a5de60, C4<1>; +L_0x2a5f180 .delay (10000,10000,10000) L_0x2a5f180/d; +L_0x2a5f2c0/d .functor NAND 1, L_0x2a5dc00, L_0x2a5f0e0, L_0x2a5df00, C4<1>; +L_0x2a5f2c0 .delay (10000,10000,10000) L_0x2a5f2c0/d; +L_0x2a5f3b0/d .functor NAND 1, L_0x2a5eff0, L_0x2a5dd30, L_0x2a5dfa0, C4<1>; +L_0x2a5f3b0 .delay (10000,10000,10000) L_0x2a5f3b0/d; +L_0x2a5f4a0/d .functor NAND 1, L_0x2a5dc00, L_0x2a5dd30, L_0x2a5e090, C4<1>; +L_0x2a5f4a0 .delay (10000,10000,10000) L_0x2a5f4a0/d; +L_0x2a5f580/d .functor NAND 1, L_0x2a5f180, L_0x2a5f2c0, L_0x2a5f3b0, L_0x2a5f4a0; +L_0x2a5f580 .delay (10000,10000,10000) L_0x2a5f580/d; +v0x25c5630_0 .net "S0", 0 0, L_0x2a5dc00; 1 drivers +v0x25b1a40_0 .net "S1", 0 0, L_0x2a5dd30; 1 drivers +v0x25b1ae0_0 .net "in0", 0 0, L_0x2a5de60; 1 drivers +v0x25adcb0_0 .net "in1", 0 0, L_0x2a5df00; 1 drivers +v0x25add50_0 .net "in2", 0 0, L_0x2a5dfa0; 1 drivers +v0x25abbe0_0 .net "in3", 0 0, L_0x2a5e090; 1 drivers +v0x25abc80_0 .net "nS0", 0 0, L_0x2a5eff0; 1 drivers +v0x25a7e50_0 .net "nS1", 0 0, L_0x2a5f0e0; 1 drivers +v0x25a7ef0_0 .net "out", 0 0, L_0x2a5f580; 1 drivers +v0x25a5d80_0 .net "out0", 0 0, L_0x2a5f180; 1 drivers +v0x25a5e20_0 .net "out1", 0 0, L_0x2a5f2c0; 1 drivers +v0x258e2e0_0 .net "out2", 0 0, L_0x2a5f3b0; 1 drivers +v0x258e380_0 .net "out3", 0 0, L_0x2a5f4a0; 1 drivers +S_0x25d1250 .scope module, "TwoMux" "TwoInMux" 3 401, 3 109, S_0x25e2cb0; + .timescale -9 -12; +L_0x2a2ade0/d .functor NOT 1, L_0x2a2b290, C4<0>, C4<0>, C4<0>; +L_0x2a2ade0 .delay (10000,10000,10000) L_0x2a2ade0/d; +L_0x2a2aed0/d .functor AND 1, L_0x2a2b330, L_0x2a2ade0, C4<1>, C4<1>; +L_0x2a2aed0 .delay (20000,20000,20000) L_0x2a2aed0/d; +L_0x2a2afc0/d .functor AND 1, L_0x2a2b420, L_0x2a2b290, C4<1>, C4<1>; +L_0x2a2afc0 .delay (20000,20000,20000) L_0x2a2afc0/d; +L_0x2a2b0b0/d .functor OR 1, L_0x2a2aed0, L_0x2a2afc0, C4<0>, C4<0>; +L_0x2a2b0b0 .delay (20000,20000,20000) L_0x2a2b0b0/d; +v0x25cf180_0 .net "S", 0 0, L_0x2a2b290; 1 drivers +v0x25cf220_0 .net "in0", 0 0, L_0x2a2b330; 1 drivers +v0x25cb3f0_0 .net "in1", 0 0, L_0x2a2b420; 1 drivers +v0x25cb490_0 .net "nS", 0 0, L_0x2a2ade0; 1 drivers +v0x25c9320_0 .net "out0", 0 0, L_0x2a2aed0; 1 drivers +v0x25c93c0_0 .net "out1", 0 0, L_0x2a2afc0; 1 drivers +v0x25c5590_0 .net "outfinal", 0 0, L_0x2a2b0b0; 1 drivers +S_0x1f6b890 .scope module, "testALU" "ALU" 2 164, 3 8, S_0x22efd20; + .timescale -9 -12; +P_0x1d35098 .param/l "size" 3 37, +C4<0100000>; +L_0x2b3ff10/d .functor AND 1, L_0x2c14570, L_0x2c14610, C4<1>, C4<1>; +L_0x2b3ff10 .delay (20000,20000,20000) L_0x2b3ff10/d; +L_0x2c14700/d .functor NOT 1, L_0x2c14810, C4<0>, C4<0>, C4<0>; +L_0x2c14700 .delay (10000,10000,10000) L_0x2c14700/d; +L_0x2c148b0/d .functor AND 1, L_0x2c14700, L_0x2c14700, C4<1>, C4<1>; +L_0x2c148b0 .delay (20000,20000,20000) L_0x2c148b0/d; +RS_0x7f507e9e4aa8/0/0 .resolv tri, L_0x2baea80, L_0x2bb02e0, L_0x2bb16e0, L_0x2bb2c80; +RS_0x7f507e9e4aa8/0/4 .resolv tri, L_0x2bb4260, L_0x2bb57b0, L_0x2bb6d10, L_0x2bb8250; +RS_0x7f507e9e4aa8/0/8 .resolv tri, L_0x2bb98a0, L_0x2bbadf0, L_0x2bbc300, L_0x2bbd7d0; +RS_0x7f507e9e4aa8/0/12 .resolv tri, L_0x2bbec90, L_0x2bc0160, L_0x2bc1620, L_0x2bc2ae0; +RS_0x7f507e9e4aa8/0/16 .resolv tri, L_0x2bc40c0, L_0x2bc54d0, L_0x2bc6940, L_0x2bc7cd0; +RS_0x7f507e9e4aa8/0/20 .resolv tri, L_0x2bc9050, L_0x2bca4a0, L_0x2bcb860, L_0x2bccd20; +RS_0x7f507e9e4aa8/0/24 .resolv tri, L_0x2bce1f0, L_0x2bcf6b0, L_0x2bd0b90, L_0x2bd2040; +RS_0x7f507e9e4aa8/0/28 .resolv tri, L_0x2bd3520, L_0x2bd4e20, L_0x2bd62e0, L_0x2bd77c0; +RS_0x7f507e9e4aa8/1/0 .resolv tri, RS_0x7f507e9e4aa8/0/0, RS_0x7f507e9e4aa8/0/4, RS_0x7f507e9e4aa8/0/8, RS_0x7f507e9e4aa8/0/12; +RS_0x7f507e9e4aa8/1/4 .resolv tri, RS_0x7f507e9e4aa8/0/16, RS_0x7f507e9e4aa8/0/20, RS_0x7f507e9e4aa8/0/24, RS_0x7f507e9e4aa8/0/28; +RS_0x7f507e9e4aa8 .resolv tri, RS_0x7f507e9e4aa8/1/0, RS_0x7f507e9e4aa8/1/4, C4, C4; +v0x2415680_0 .net8 "AddSubSLTSum", 31 0, RS_0x7f507e9e4aa8; 32 drivers +RS_0x7f507e9dde78/0/0 .resolv tri, L_0x2bd7eb0, L_0x2bd9ac0, L_0x2bda570, L_0x2bdafd0; +RS_0x7f507e9dde78/0/4 .resolv tri, L_0x2bdba60, L_0x2bdc530, L_0x2bdd050, L_0x2bddab0; +RS_0x7f507e9dde78/0/8 .resolv tri, L_0x2bde550, L_0x2bdefc0, L_0x2bdfa50, L_0x2be04c0; +RS_0x7f507e9dde78/0/12 .resolv tri, L_0x2be0f60, L_0x2be19c0, L_0x2be2450, L_0x2be2ec0; +RS_0x7f507e9dde78/0/16 .resolv tri, L_0x2be3960, L_0x2be43c0, L_0x2be4e60, L_0x2be58c0; +RS_0x7f507e9dde78/0/20 .resolv tri, L_0x2be6250, L_0x2be6c00, L_0x2be7580, L_0x2be7f20; +RS_0x7f507e9dde78/0/24 .resolv tri, L_0x2be8890, L_0x2be9210, L_0x2be9ba0, L_0x2bea5b0; +RS_0x7f507e9dde78/0/28 .resolv tri, L_0x2beb050, L_0x2bebab0, L_0x2bec540, L_0x2becfb0; +RS_0x7f507e9dde78/1/0 .resolv tri, RS_0x7f507e9dde78/0/0, RS_0x7f507e9dde78/0/4, RS_0x7f507e9dde78/0/8, RS_0x7f507e9dde78/0/12; +RS_0x7f507e9dde78/1/4 .resolv tri, RS_0x7f507e9dde78/0/16, RS_0x7f507e9dde78/0/20, RS_0x7f507e9dde78/0/24, RS_0x7f507e9dde78/0/28; +RS_0x7f507e9dde78 .resolv tri, RS_0x7f507e9dde78/1/0, RS_0x7f507e9dde78/1/4, C4, C4; +v0x2418bc0_0 .net8 "AndNandOut", 31 0, RS_0x7f507e9dde78; 32 drivers +RS_0x7f507e9f0418/0/0 .resolv tri, L_0x2b17c40, L_0x2b1a6f0, L_0x2b1d060, L_0x2b1f730; +RS_0x7f507e9f0418/0/4 .resolv tri, L_0x2b22280, L_0x2b24bb0, L_0x2b272b0, L_0x2b29a40; +RS_0x7f507e9f0418/0/8 .resolv tri, L_0x2b2c750, L_0x2b2ee40, L_0x2b31550, L_0x2b33e60; +RS_0x7f507e9f0418/0/12 .resolv tri, L_0x2b365a0, L_0x2b38d50, L_0x2b3b520, L_0x2b3ddf0; +RS_0x7f507e9f0418/0/16 .resolv tri, L_0x2b403b0, L_0x2b43a60, L_0x2b45560, L_0x2b47cc0; +RS_0x7f507e9f0418/0/20 .resolv tri, L_0x2b4a290, L_0x2b4ddb0, L_0x2b4f690, L_0x2b51e50; +RS_0x7f507e9f0418/0/24 .resolv tri, L_0x2b542f0, L_0x2b57f10, L_0x2b5a7b0, L_0x2b5d020; +RS_0x7f507e9f0418/0/28 .resolv tri, L_0x2b5f890, L_0x2b62130, L_0x2b62ff0, L_0x2c13460; +RS_0x7f507e9f0418/1/0 .resolv tri, RS_0x7f507e9f0418/0/0, RS_0x7f507e9f0418/0/4, RS_0x7f507e9f0418/0/8, RS_0x7f507e9f0418/0/12; +RS_0x7f507e9f0418/1/4 .resolv tri, RS_0x7f507e9f0418/0/16, RS_0x7f507e9f0418/0/20, RS_0x7f507e9f0418/0/24, RS_0x7f507e9f0418/0/28; +RS_0x7f507e9f0418 .resolv tri, RS_0x7f507e9f0418/1/0, RS_0x7f507e9f0418/1/4, C4, C4; +v0x2418c40_0 .net8 "Cmd0Start", 31 0, RS_0x7f507e9f0418; 32 drivers +RS_0x7f507e9f0448/0/0 .resolv tri, L_0x2b18b60, L_0x2b1b5c0, L_0x2b1dfa0, L_0x2b20640; +RS_0x7f507e9f0448/0/4 .resolv tri, L_0x2b23100, L_0x2b25a40, L_0x2b28130, L_0x2b2a980; +RS_0x7f507e9f0448/0/8 .resolv tri, L_0x2b2d550, L_0x2b2fc60, L_0x2b31aa0, L_0x2b34c70; +RS_0x7f507e9f0448/0/12 .resolv tri, L_0x2b37400, L_0x2b39be0, L_0x2b3c4c0, L_0x2b3eea0; +RS_0x7f507e9f0448/0/16 .resolv tri, L_0x2b420e0, L_0x2b44900, L_0x2b470b0, L_0x2b48950; +RS_0x7f507e9f0448/0/20 .resolv tri, L_0x2b4b270, L_0x2b4ec60, L_0x2b51460, L_0x2b52cd0; +RS_0x7f507e9f0448/0/24 .resolv tri, L_0x2b554a0, L_0x2b57790, L_0x2b59e50, L_0x2b5cac0; +RS_0x7f507e9f0448/0/28 .resolv tri, L_0x2b5f150, L_0x2b61b80, L_0x2b65a00, L_0x2b66730; +RS_0x7f507e9f0448/1/0 .resolv tri, RS_0x7f507e9f0448/0/0, RS_0x7f507e9f0448/0/4, RS_0x7f507e9f0448/0/8, RS_0x7f507e9f0448/0/12; +RS_0x7f507e9f0448/1/4 .resolv tri, RS_0x7f507e9f0448/0/16, RS_0x7f507e9f0448/0/20, RS_0x7f507e9f0448/0/24, RS_0x7f507e9f0448/0/28; +RS_0x7f507e9f0448 .resolv tri, RS_0x7f507e9f0448/1/0, RS_0x7f507e9f0448/1/4, C4, C4; +v0x2415350_0 .net8 "Cmd1Start", 31 0, RS_0x7f507e9f0448; 32 drivers +RS_0x7f507e9da848/0/0 .resolv tri, L_0x2bee390, L_0x2bef6b0, L_0x2bf09d0, L_0x2bf1ce0; +RS_0x7f507e9da848/0/4 .resolv tri, L_0x2bf3000, L_0x2bf4380, L_0x2bf5730, L_0x2bf6a40; +RS_0x7f507e9da848/0/8 .resolv tri, L_0x2bf7d70, L_0x2bf9090, L_0x2bfa3b0, L_0x2bfb6c0; +RS_0x7f507e9da848/0/12 .resolv tri, L_0x2bfca00, L_0x2bfdd00, L_0x2bff020, L_0x2c00330; +RS_0x7f507e9da848/0/16 .resolv tri, L_0x2c01660, L_0x2c02970, L_0x2c03c90, L_0x2c04fb0; +RS_0x7f507e9da848/0/20 .resolv tri, L_0x2c062e0, L_0x2c074b0, L_0x2c085f0, L_0x2c09730; +RS_0x7f507e9da848/0/24 .resolv tri, L_0x2c0a850, L_0x2c0b980, L_0x2c0cbd0, L_0x2c0def0; +RS_0x7f507e9da848/0/28 .resolv tri, L_0x2c0f1f0, L_0x2c10500, L_0x2c11830, L_0x2c12b20; +RS_0x7f507e9da848/1/0 .resolv tri, RS_0x7f507e9da848/0/0, RS_0x7f507e9da848/0/4, RS_0x7f507e9da848/0/8, RS_0x7f507e9da848/0/12; +RS_0x7f507e9da848/1/4 .resolv tri, RS_0x7f507e9da848/0/16, RS_0x7f507e9da848/0/20, RS_0x7f507e9da848/0/24, RS_0x7f507e9da848/0/28; +RS_0x7f507e9da848 .resolv tri, RS_0x7f507e9da848/1/0, RS_0x7f507e9da848/1/4, C4, C4; +v0x24153d0_0 .net8 "OrNorXorOut", 31 0, RS_0x7f507e9da848; 32 drivers +RS_0x7f507e9f0178/0/0 .resolv tri, L_0x2b68d70, L_0x2b6afd0, L_0x2b6d050, L_0x2b6f2a0; +RS_0x7f507e9f0178/0/4 .resolv tri, L_0x2b71320, L_0x2b735f0, L_0x2b75900, L_0x2b77e40; +RS_0x7f507e9f0178/0/8 .resolv tri, L_0x2b7a0e0, L_0x2b7c410, L_0x2b7e700, L_0x2b7c370; +RS_0x7f507e9f0178/0/12 .resolv tri, L_0x2b82b60, L_0x2b84ea0, L_0x2b866e0, L_0x2b895a0; +RS_0x7f507e9f0178/0/16 .resolv tri, L_0x2b8a930, L_0x2b8e0e0, L_0x2b8f910, L_0x2b8d4f0; +RS_0x7f507e9f0178/0/20 .resolv tri, L_0x2b93bb0, L_0x2b7ea10, L_0x2b98290, L_0x2b95780; +RS_0x7f507e9f0178/0/24 .resolv tri, L_0x2b9c440, L_0x2b99f10, L_0x2ba0f30, L_0x2ba3180; +RS_0x7f507e9f0178/0/28 .resolv tri, L_0x2ba5340, L_0x2ba6f40, L_0x2ba9860, L_0x2bad4c0; +RS_0x7f507e9f0178/1/0 .resolv tri, RS_0x7f507e9f0178/0/0, RS_0x7f507e9f0178/0/4, RS_0x7f507e9f0178/0/8, RS_0x7f507e9f0178/0/12; +RS_0x7f507e9f0178/1/4 .resolv tri, RS_0x7f507e9f0178/0/16, RS_0x7f507e9f0178/0/20, RS_0x7f507e9f0178/0/24, RS_0x7f507e9f0178/0/28; +RS_0x7f507e9f0178 .resolv tri, RS_0x7f507e9f0178/1/0, RS_0x7f507e9f0178/1/4, C4, C4; +v0x24150b0_0 .net8 "SLTSum", 31 0, RS_0x7f507e9f0178; 32 drivers +v0x2415130_0 .net "SLTflag", 0 0, L_0x2bad020; 1 drivers +RS_0x7f507e9f0478/0/0 .resolv tri, L_0x2b19c10, L_0x2b1c560, L_0x2b1eba0, L_0x2b21450; +RS_0x7f507e9f0478/0/4 .resolv tri, L_0x2b23b00, L_0x2b25e90, L_0x2b28770, L_0x2b212d0; +RS_0x7f507e9f0478/0/8 .resolv tri, L_0x2b2d7d0, L_0x2b300b0, L_0x2b32a20, L_0x2b350c0; +RS_0x7f507e9f0478/0/12 .resolv tri, L_0x2b37680, L_0x2b3a030, L_0x2b3c740, L_0x2b2ad30; +RS_0x7f507e9f0478/0/16 .resolv tri, L_0x2b42360, L_0x2b456e0, L_0x2b47150, L_0x2b49870; +RS_0x7f507e9f0478/0/20 .resolv tri, L_0x2b4ba50, L_0x2b4e980, L_0x2b509f0, L_0x2b53720; +RS_0x7f507e9f0478/0/24 .resolv tri, L_0x2b56160, L_0x2b58960, L_0x2b5b050, L_0x2b5d8a0; +RS_0x7f507e9f0478/0/28 .resolv tri, L_0x2b600f0, L_0x2b62450, L_0x2b647a0, L_0x2b3fe70; +RS_0x7f507e9f0478/1/0 .resolv tri, RS_0x7f507e9f0478/0/0, RS_0x7f507e9f0478/0/4, RS_0x7f507e9f0478/0/8, RS_0x7f507e9f0478/0/12; +RS_0x7f507e9f0478/1/4 .resolv tri, RS_0x7f507e9f0478/0/16, RS_0x7f507e9f0478/0/20, RS_0x7f507e9f0478/0/24, RS_0x7f507e9f0478/0/28; +RS_0x7f507e9f0478 .resolv tri, RS_0x7f507e9f0478/1/0, RS_0x7f507e9f0478/1/4, C4, C4; +v0x25a1fd0_0 .net8 "ZeroFlag", 31 0, RS_0x7f507e9f0478; 32 drivers +v0x25a2050_0 .net *"_s121", 0 0, L_0x2b23ba0; 1 drivers +v0x27b6660_0 .net *"_s146", 0 0, L_0x2b25f30; 1 drivers +v0x27b66e0_0 .net *"_s171", 0 0, L_0x2b28810; 1 drivers +v0x25904b0_0 .net *"_s196", 0 0, L_0x2b29750; 1 drivers +v0x2590550_0 .net *"_s21", 0 0, L_0x2b19860; 1 drivers +v0x27b5460_0 .net *"_s221", 0 0, L_0x2b2d870; 1 drivers +v0x27b51c0_0 .net *"_s246", 0 0, L_0x2b30150; 1 drivers +v0x27b5260_0 .net *"_s271", 0 0, L_0x2b32ac0; 1 drivers +v0x27b54e0_0 .net *"_s296", 0 0, L_0x2b35160; 1 drivers +v0x27b4ff0_0 .net *"_s321", 0 0, L_0x2b37720; 1 drivers +v0x27b4f20_0 .net *"_s346", 0 0, L_0x2b3a0d0; 1 drivers +v0x27b4740_0 .net *"_s371", 0 0, L_0x2b3c7e0; 1 drivers +v0x27b36f0_0 .net *"_s396", 0 0, L_0x2b2add0; 1 drivers +v0x27b46a0_0 .net *"_s421", 0 0, L_0x2b42400; 1 drivers +v0x27b3460_0 .net *"_s446", 0 0, L_0x2b44ad0; 1 drivers +v0x27b3640_0 .net *"_s46", 0 0, L_0x2b1bca0; 1 drivers +v0x27b31d0_0 .net *"_s471", 0 0, L_0x2b471f0; 1 drivers +v0x27b33a0_0 .net *"_s496", 0 0, L_0x2b49910; 1 drivers +v0x27b3100_0 .net *"_s521", 0 0, L_0x2b32190; 1 drivers +v0x27b2b60_0 .net *"_s546", 0 0, L_0x2b4ea20; 1 drivers +v0x27b2c00_0 .net *"_s571", 0 0, L_0x2b50a90; 1 drivers +v0x27b25e0_0 .net *"_s596", 0 0, L_0x2b537c0; 1 drivers +v0x27b2660_0 .net *"_s621", 0 0, L_0x2b56200; 1 drivers +v0x27b2e60_0 .net *"_s646", 0 0, L_0x2b58a00; 1 drivers +v0x262d560_0 .net *"_s671", 0 0, L_0x2b5b0f0; 1 drivers +v0x262d600_0 .net *"_s696", 0 0, L_0x2b5d940; 1 drivers +v0x262f630_0 .net *"_s71", 0 0, L_0x2b1ec40; 1 drivers +v0x2627700_0 .net *"_s721", 0 0, L_0x2b60190; 1 drivers +v0x2627780_0 .net *"_s746", 0 0, L_0x2b624f0; 1 drivers +v0x2623970_0 .net *"_s771", 0 0, L_0x2b64840; 1 drivers +v0x26239f0_0 .net *"_s811", 0 0, L_0x2b3ff10; 1 drivers +v0x26297d0_0 .net *"_s814", 0 0, L_0x2c14570; 1 drivers +v0x2629870_0 .net *"_s816", 0 0, L_0x2c14610; 1 drivers +v0x260c0b0_0 .net *"_s818", 0 0, L_0x2c14810; 1 drivers +v0x260c130_0 .net *"_s96", 0 0, L_0x2b214f0; 1 drivers +v0x2609fe0_0 .net "carryin", 31 0, C4; 0 drivers +v0x260a060_0 .alias "carryout", 0 0, v0x2960740_0; +v0x2606250_0 .alias "command", 2 0, v0x295f7a0_0; +v0x26062d0_0 .alias "operandA", 31 0, v0x295f580_0; +v0x2604210_0 .alias "operandB", 31 0, v0x295f6a0_0; +v0x25eea00_0 .alias "overflow", 0 0, v0x29608f0_0; +v0x25ec8a0_0 .alias "result", 31 0, v0x2960310_0; +RS_0x7f507e9e4c28/0/0 .resolv tri, L_0x2b67c00, L_0x2b6a180, L_0x2b6b260, L_0x2b6e490; +RS_0x7f507e9e4c28/0/4 .resolv tri, L_0x2b6f540, L_0x2b715a0, L_0x2b73690, L_0x2b75b80; +RS_0x7f507e9e4c28/0/8 .resolv tri, L_0x2b77ee0, L_0x2b7a360, L_0x2b7c4b0, L_0x2b7ed90; +RS_0x7f507e9e4c28/0/12 .resolv tri, L_0x2b80aa0, L_0x2b82de0, L_0x2b84f40, L_0x2b87240; +RS_0x7f507e9e4c28/0/16 .resolv tri, L_0x2b89640, L_0x2b8bff0, L_0x2b8e180, L_0x2b8fe50; +RS_0x7f507e9e4c28/0/20 .resolv tri, L_0x2b925b0, L_0x2b94110, L_0x2b96830, L_0x2b987b0; +RS_0x7f507e9e4c28/0/24 .resolv tri, L_0x2b9a6e0, L_0x2b9c970, L_0x2b9e920, L_0x2ba11b0; +RS_0x7f507e9e4c28/0/28 .resolv tri, L_0x2ba3220, L_0x2ba55c0, L_0x2ba7200, L_0x2ba99f0; +RS_0x7f507e9e4c28/0/32 .resolv tri, L_0x2b3d500, L_0x2bb0510, L_0x2bb1940, L_0x2bb1d30; +RS_0x7f507e9e4c28/0/36 .resolv tri, L_0x2bb3300, L_0x2bb4830, L_0x2bb5d90, L_0x2bb72c0; +RS_0x7f507e9e4c28/0/40 .resolv tri, L_0x2bb8a70, L_0x2bb9e00, L_0x2bbb380, L_0x2bbc8c0; +RS_0x7f507e9e4c28/0/44 .resolv tri, L_0x2bbdd30, L_0x2bbf210, L_0x2bc0710, L_0x2bc1c00; +RS_0x7f507e9e4c28/0/48 .resolv tri, L_0x2bc3470, L_0x2bc4670, L_0x2bc5ab0, L_0x2bc6b20; +RS_0x7f507e9e4c28/0/52 .resolv tri, L_0x2bc7eb0, L_0x2bc9230, L_0x2bca680, L_0x2bcba40; +RS_0x7f507e9e4c28/0/56 .resolv tri, L_0x2bccf00, L_0x2bce3d0, L_0x2bcf890, L_0x2bd0d70; +RS_0x7f507e9e4c28/0/60 .resolv tri, L_0x2bd2220, L_0x2bd4470, L_0x2bd5000, L_0x2bd64c0; +RS_0x7f507e9e4c28/1/0 .resolv tri, RS_0x7f507e9e4c28/0/0, RS_0x7f507e9e4c28/0/4, RS_0x7f507e9e4c28/0/8, RS_0x7f507e9e4c28/0/12; +RS_0x7f507e9e4c28/1/4 .resolv tri, RS_0x7f507e9e4c28/0/16, RS_0x7f507e9e4c28/0/20, RS_0x7f507e9e4c28/0/24, RS_0x7f507e9e4c28/0/28; +RS_0x7f507e9e4c28/1/8 .resolv tri, RS_0x7f507e9e4c28/0/32, RS_0x7f507e9e4c28/0/36, RS_0x7f507e9e4c28/0/40, RS_0x7f507e9e4c28/0/44; +RS_0x7f507e9e4c28/1/12 .resolv tri, RS_0x7f507e9e4c28/0/48, RS_0x7f507e9e4c28/0/52, RS_0x7f507e9e4c28/0/56, RS_0x7f507e9e4c28/0/60; +RS_0x7f507e9e4c28 .resolv tri, RS_0x7f507e9e4c28/1/0, RS_0x7f507e9e4c28/1/4, RS_0x7f507e9e4c28/1/8, RS_0x7f507e9e4c28/1/12; +v0x25ec920_0 .net8 "subtract", 31 0, RS_0x7f507e9e4c28; 64 drivers +v0x25e8b10_0 .net "yeszero", 0 0, L_0x2c14700; 1 drivers +v0x25e8b90_0 .alias "zero", 0 0, v0x2960030_0; +L_0x2b17c40 .part/pv L_0x2b17a30, 1, 1, 32; +L_0x2b17ce0 .part v0x2960210_0, 0, 1; +L_0x2b17e10 .part v0x2960210_0, 1, 1; +L_0x2b17f40 .part RS_0x7f507e9e4aa8, 1, 1; +L_0x2b17fe0 .part RS_0x7f507e9e4aa8, 1, 1; +L_0x2b180d0 .part RS_0x7f507e9da848, 1, 1; +L_0x2b18250 .part RS_0x7f507e9f0178, 1, 1; +L_0x2b18b60 .part/pv L_0x2b18950, 1, 1, 32; +L_0x2b18c50 .part v0x2960210_0, 0, 1; +L_0x2b18d80 .part v0x2960210_0, 1, 1; +L_0x2b18f10 .part RS_0x7f507e9dde78, 1, 1; +L_0x2b18fb0 .part RS_0x7f507e9dde78, 1, 1; +L_0x2b190c0 .part RS_0x7f507e9da848, 1, 1; +L_0x2b191b0 .part RS_0x7f507e9da848, 1, 1; +L_0x2b196d0 .part/pv L_0x2b19590, 1, 1, 32; +L_0x2b197c0 .part v0x2960210_0, 2, 1; +L_0x2b198f0 .part RS_0x7f507e9f0418, 1, 1; +L_0x2b19a30 .part RS_0x7f507e9f0448, 1, 1; +L_0x2b19c10 .part/pv L_0x2b19860, 1, 1, 32; +L_0x2b19d90 .part RS_0x7f507e9f0478, 0, 1; +L_0x2b19b70 .part RS_0x7f507e9f0b38, 1, 1; +L_0x2b1a6f0 .part/pv L_0x2b1a510, 2, 1, 32; +L_0x2b19e80 .part v0x2960210_0, 0, 1; +L_0x2b1a8e0 .part v0x2960210_0, 1, 1; +L_0x2b1a790 .part RS_0x7f507e9e4aa8, 2, 1; +L_0x2b1ab70 .part RS_0x7f507e9e4aa8, 2, 1; +L_0x2b1aa10 .part RS_0x7f507e9da848, 2, 1; +L_0x2b1acf0 .part RS_0x7f507e9f0178, 2, 1; +L_0x2b1b5c0 .part/pv L_0x2b1b3b0, 2, 1, 32; +L_0x2b1b660 .part v0x2960210_0, 0, 1; +L_0x2b1ade0 .part v0x2960210_0, 1, 1; +L_0x2b1b920 .part RS_0x7f507e9dde78, 2, 1; +L_0x2b1b790 .part RS_0x7f507e9dde78, 2, 1; +L_0x2b1bb60 .part RS_0x7f507e9da848, 2, 1; +L_0x2b1ba50 .part RS_0x7f507e9da848, 2, 1; +L_0x2b1c090 .part/pv L_0x2b1bf50, 2, 1, 32; +L_0x2b1bc00 .part v0x2960210_0, 2, 1; +L_0x2b1c2f0 .part RS_0x7f507e9f0418, 2, 1; +L_0x2b1c1c0 .part RS_0x7f507e9f0448, 2, 1; +L_0x2b1c560 .part/pv L_0x2b1bca0, 2, 1, 32; +L_0x2b1c4b0 .part RS_0x7f507e9f0478, 1, 1; +L_0x2b1c7e0 .part RS_0x7f507e9f0b38, 2, 1; +L_0x2b1d060 .part/pv L_0x2b1ce50, 3, 1, 32; +L_0x2b1d100 .part v0x2960210_0, 0, 1; +L_0x2b1c880 .part v0x2960210_0, 1, 1; +L_0x2b1d3a0 .part RS_0x7f507e9e4aa8, 3, 1; +L_0x2b1d230 .part RS_0x7f507e9e4aa8, 3, 1; +L_0x2b1d2d0 .part RS_0x7f507e9da848, 3, 1; +L_0x2b1d440 .part RS_0x7f507e9f0178, 3, 1; +L_0x2b1dfa0 .part/pv L_0x2b1dd90, 3, 1, 32; +L_0x2b1d720 .part v0x2960210_0, 0, 1; +L_0x2b1e1e0 .part v0x2960210_0, 1, 1; +L_0x2b1e040 .part RS_0x7f507e9dde78, 3, 1; +L_0x2b1e0e0 .part RS_0x7f507e9dde78, 3, 1; +L_0x2b1e4d0 .part RS_0x7f507e9da848, 3, 1; +L_0x2b1e570 .part RS_0x7f507e9da848, 3, 1; +L_0x2b1ea60 .part/pv L_0x2b1e920, 3, 1, 32; +L_0x2b1eb00 .part v0x2960210_0, 2, 1; +L_0x2b1e610 .part RS_0x7f507e9f0418, 3, 1; +L_0x2b1e700 .part RS_0x7f507e9f0448, 3, 1; +L_0x2b1eba0 .part/pv L_0x2b1ec40, 3, 1, 32; +L_0x2b1efc0 .part RS_0x7f507e9f0478, 2, 1; +L_0x2b1edd0 .part RS_0x7f507e9f0b38, 3, 1; +L_0x2b1f730 .part/pv L_0x2b1f520, 4, 1, 32; +L_0x2b1f060 .part v0x2960210_0, 0, 1; +L_0x2b1f190 .part v0x2960210_0, 1, 1; +L_0x2b1f7d0 .part RS_0x7f507e9e4aa8, 4, 1; +L_0x2b1fc90 .part RS_0x7f507e9e4aa8, 4, 1; +L_0x2b1fa70 .part RS_0x7f507e9da848, 4, 1; +L_0x2b1fb60 .part RS_0x7f507e9f0178, 4, 1; +L_0x2b20640 .part/pv L_0x2b20430, 4, 1, 32; +L_0x2b206e0 .part v0x2960210_0, 0, 1; +L_0x2b1fd30 .part v0x2960210_0, 1, 1; +L_0x2b1fe60 .part RS_0x7f507e9dde78, 4, 1; +L_0x2b20810 .part RS_0x7f507e9dde78, 4, 1; +L_0x2b208b0 .part RS_0x7f507e9da848, 4, 1; +L_0x2b209a0 .part RS_0x7f507e9da848, 4, 1; +L_0x2b21190 .part/pv L_0x2b21050, 4, 1, 32; +L_0x2b20b70 .part v0x2960210_0, 2, 1; +L_0x2b20c10 .part RS_0x7f507e9f0418, 4, 1; +L_0x2b20d00 .part RS_0x7f507e9f0448, 4, 1; +L_0x2b21450 .part/pv L_0x2b214f0, 4, 1, 32; +L_0x2b21970 .part RS_0x7f507e9f0478, 3, 1; +L_0x2b21b20 .part RS_0x7f507e9f0b38, 4, 1; +L_0x2b22280 .part/pv L_0x2b22070, 5, 1, 32; +L_0x2b22320 .part v0x2960210_0, 0, 1; +L_0x2b21bc0 .part v0x2960210_0, 1, 1; +L_0x2b21cf0 .part RS_0x7f507e9e4aa8, 5, 1; +L_0x2b21d90 .part RS_0x7f507e9e4aa8, 5, 1; +L_0x2b22720 .part RS_0x7f507e9da848, 5, 1; +L_0x2b22450 .part RS_0x7f507e9f0178, 5, 1; +L_0x2b23100 .part/pv L_0x2b22ef0, 5, 1, 32; +L_0x2b22810 .part v0x2960210_0, 0, 1; +L_0x2b22940 .part v0x2960210_0, 1, 1; +L_0x2b234a0 .part RS_0x7f507e9dde78, 5, 1; +L_0x2b23540 .part RS_0x7f507e9dde78, 5, 1; +L_0x2b231a0 .part RS_0x7f507e9da848, 5, 1; +L_0x2b23290 .part RS_0x7f507e9da848, 5, 1; +L_0x2b237b0 .part/pv L_0x2b23670, 5, 1, 32; +L_0x2b23850 .part v0x2960210_0, 2, 1; +L_0x2b23e30 .part RS_0x7f507e9f0418, 5, 1; +L_0x2b23f20 .part RS_0x7f507e9f0448, 5, 1; +L_0x2b23b00 .part/pv L_0x2b23ba0, 5, 1, 32; +L_0x2b23ce0 .part RS_0x7f507e9f0478, 4, 1; +L_0x2b23d80 .part RS_0x7f507e9f0b38, 5, 1; +L_0x2b24bb0 .part/pv L_0x2b249a0, 6, 1, 32; +L_0x2b24010 .part v0x2960210_0, 0, 1; +L_0x2b24140 .part v0x2960210_0, 1, 1; +L_0x2b24270 .part RS_0x7f507e9e4aa8, 6, 1; +L_0x2b24fc0 .part RS_0x7f507e9e4aa8, 6, 1; +L_0x2b24c50 .part RS_0x7f507e9da848, 6, 1; +L_0x2b24cf0 .part RS_0x7f507e9f0178, 6, 1; +L_0x2b25a40 .part/pv L_0x2b25830, 6, 1, 32; +L_0x2b25ae0 .part v0x2960210_0, 0, 1; +L_0x2b25060 .part v0x2960210_0, 1, 1; +L_0x2b25190 .part RS_0x7f507e9dde78, 6, 1; +L_0x2b25230 .part RS_0x7f507e9dde78, 6, 1; +L_0x2b252d0 .part RS_0x7f507e9da848, 6, 1; +L_0x2b25fd0 .part RS_0x7f507e9da848, 6, 1; +L_0x2b264d0 .part/pv L_0x2b26390, 6, 1, 32; +L_0x2b25c10 .part v0x2960210_0, 2, 1; +L_0x2b25cb0 .part RS_0x7f507e9f0418, 6, 1; +L_0x2b25da0 .part RS_0x7f507e9f0448, 6, 1; +L_0x2b25e90 .part/pv L_0x2b25f30, 6, 1, 32; +L_0x2b26a00 .part RS_0x7f507e9f0478, 5, 1; +L_0x2b26aa0 .part RS_0x7f507e9f0b38, 6, 1; +L_0x2b272b0 .part/pv L_0x2b270a0, 7, 1, 32; +L_0x2b27350 .part v0x2960210_0, 0, 1; +L_0x2b26b90 .part v0x2960210_0, 1, 1; +L_0x2b26cc0 .part RS_0x7f507e9e4aa8, 7, 1; +L_0x2b26d60 .part RS_0x7f507e9e4aa8, 7, 1; +L_0x2b26e00 .part RS_0x7f507e9da848, 7, 1; +L_0x2b26ef0 .part RS_0x7f507e9f0178, 7, 1; +L_0x2b28130 .part/pv L_0x2b27f20, 7, 1, 32; +L_0x2b27480 .part v0x2960210_0, 0, 1; +L_0x2b275b0 .part v0x2960210_0, 1, 1; +L_0x2b276e0 .part RS_0x7f507e9dde78, 7, 1; +L_0x2b27780 .part RS_0x7f507e9dde78, 7, 1; +L_0x2b28630 .part RS_0x7f507e9da848, 7, 1; +L_0x2b286d0 .part RS_0x7f507e9da848, 7, 1; +L_0x2b284c0 .part/pv L_0x2b28380, 7, 1, 32; +L_0x2b28560 .part v0x2960210_0, 2, 1; +L_0x2b28bf0 .part RS_0x7f507e9f0418, 7, 1; +L_0x2b28ce0 .part RS_0x7f507e9f0448, 7, 1; +L_0x2b28770 .part/pv L_0x2b28810, 7, 1, 32; +L_0x2b28950 .part RS_0x7f507e9f0478, 6, 1; +L_0x2b289f0 .part RS_0x7f507e9f0b38, 7, 1; +L_0x2b29a40 .part/pv L_0x2b29830, 8, 1, 32; +L_0x2b28dd0 .part v0x2960210_0, 0, 1; +L_0x2b28f00 .part v0x2960210_0, 1, 1; +L_0x2b29030 .part RS_0x7f507e9e4aa8, 8, 1; +L_0x2b1f870 .part RS_0x7f507e9e4aa8, 8, 1; +L_0x2b290d0 .part RS_0x7f507e9da848, 8, 1; +L_0x2b291c0 .part RS_0x7f507e9f0178, 8, 1; +L_0x2b2a980 .part/pv L_0x2b2a770, 8, 1, 32; +L_0x2b2aa20 .part v0x2960210_0, 0, 1; +L_0x2b2a1b0 .part v0x2960210_0, 1, 1; +L_0x2b2a2e0 .part RS_0x7f507e9dde78, 8, 1; +L_0x2b2a590 .part RS_0x7f507e9dde78, 8, 1; +L_0x2b20a40 .part RS_0x7f507e9da848, 8, 1; +L_0x2b2b060 .part RS_0x7f507e9da848, 8, 1; +L_0x2b2b410 .part/pv L_0x2b2b310, 8, 1, 32; +L_0x2b21230 .part v0x2960210_0, 2, 1; +L_0x2b2ab50 .part RS_0x7f507e9f0418, 8, 1; +L_0x2b215a0 .part RS_0x7f507e9f0448, 8, 1; +L_0x2b212d0 .part/pv L_0x2b29750, 8, 1, 32; +L_0x2b2bc00 .part RS_0x7f507e9f0478, 7, 1; +L_0x2b21a10 .part RS_0x7f507e9f0b38, 8, 1; +L_0x2b2c750 .part/pv L_0x2b2c540, 9, 1, 32; +L_0x2b2c7f0 .part v0x2960210_0, 0, 1; +L_0x2b2beb0 .part v0x2960210_0, 1, 1; +L_0x2b2bfe0 .part RS_0x7f507e9e4aa8, 9, 1; +L_0x2b2c080 .part RS_0x7f507e9e4aa8, 9, 1; +L_0x2b2c120 .part RS_0x7f507e9da848, 9, 1; +L_0x2b2c210 .part RS_0x7f507e9f0178, 9, 1; +L_0x2b2d550 .part/pv L_0x2b2d340, 9, 1, 32; +L_0x2b2c920 .part v0x2960210_0, 0, 1; +L_0x2b2ca50 .part v0x2960210_0, 1, 1; +L_0x2b2cb80 .part RS_0x7f507e9dde78, 9, 1; +L_0x2b2cc20 .part RS_0x7f507e9dde78, 9, 1; +L_0x2b2ccc0 .part RS_0x7f507e9da848, 9, 1; +L_0x2b2cdb0 .part RS_0x7f507e9da848, 9, 1; +L_0x2b2dee0 .part/pv L_0x2b2dda0, 9, 1, 32; +L_0x2b2df80 .part v0x2960210_0, 2, 1; +L_0x2b2d5f0 .part RS_0x7f507e9f0418, 9, 1; +L_0x2b2d6e0 .part RS_0x7f507e9f0448, 9, 1; +L_0x2b2d7d0 .part/pv L_0x2b2d870, 9, 1, 32; +L_0x2b2d9b0 .part RS_0x7f507e9f0478, 8, 1; +L_0x2b2da50 .part RS_0x7f507e9f0b38, 9, 1; +L_0x2b2ee40 .part/pv L_0x2b2ec30, 10, 1, 32; +L_0x2b2e020 .part v0x2960210_0, 0, 1; +L_0x2b2e150 .part v0x2960210_0, 1, 1; +L_0x2b2e280 .part RS_0x7f507e9e4aa8, 10, 1; +L_0x2b2e320 .part RS_0x7f507e9e4aa8, 10, 1; +L_0x2b2e3c0 .part RS_0x7f507e9da848, 10, 1; +L_0x2b2e4b0 .part RS_0x7f507e9f0178, 10, 1; +L_0x2b2fc60 .part/pv L_0x2b2fa50, 10, 1, 32; +L_0x2b2fd00 .part v0x2960210_0, 0, 1; +L_0x2b2eee0 .part v0x2960210_0, 1, 1; +L_0x2b2f010 .part RS_0x7f507e9dde78, 10, 1; +L_0x2b2f0b0 .part RS_0x7f507e9dde78, 10, 1; +L_0x2b2f150 .part RS_0x7f507e9da848, 10, 1; +L_0x2b2f240 .part RS_0x7f507e9da848, 10, 1; +L_0x2b305e0 .part/pv L_0x2b304e0, 10, 1, 32; +L_0x2b2fe30 .part v0x2960210_0, 2, 1; +L_0x2b2fed0 .part RS_0x7f507e9f0418, 10, 1; +L_0x2b2ffc0 .part RS_0x7f507e9f0448, 10, 1; +L_0x2b300b0 .part/pv L_0x2b30150, 10, 1, 32; +L_0x2b30290 .part RS_0x7f507e9f0478, 9, 1; +L_0x2b30330 .part RS_0x7f507e9f0b38, 10, 1; +L_0x2b31550 .part/pv L_0x2b31340, 11, 1, 32; +L_0x2b315f0 .part v0x2960210_0, 0, 1; +L_0x2b30680 .part v0x2960210_0, 1, 1; +L_0x2b307b0 .part RS_0x7f507e9e4aa8, 11, 1; +L_0x2b30850 .part RS_0x7f507e9e4aa8, 11, 1; +L_0x2b308f0 .part RS_0x7f507e9da848, 11, 1; +L_0x2b238f0 .part RS_0x7f507e9f0178, 11, 1; +L_0x2b31aa0 .part/pv L_0x2b31890, 11, 1, 32; +L_0x2b31b40 .part v0x2960210_0, 0, 1; +L_0x2b31c70 .part v0x2960210_0, 1, 1; +L_0x2b328e0 .part RS_0x7f507e9dde78, 11, 1; +L_0x2b32980 .part RS_0x7f507e9dde78, 11, 1; +L_0x2b321f0 .part RS_0x7f507e9da848, 11, 1; +L_0x2b322e0 .part RS_0x7f507e9da848, 11, 1; +L_0x2b326c0 .part/pv L_0x2b32580, 11, 1, 32; +L_0x2b32760 .part v0x2960210_0, 2, 1; +L_0x2b32800 .part RS_0x7f507e9f0418, 11, 1; +L_0x2b33190 .part RS_0x7f507e9f0448, 11, 1; +L_0x2b32a20 .part/pv L_0x2b32ac0, 11, 1, 32; +L_0x2b32bc0 .part RS_0x7f507e9f0478, 10, 1; +L_0x2b32c60 .part RS_0x7f507e9f0b38, 11, 1; +L_0x2b33e60 .part/pv L_0x2b33c50, 12, 1, 32; +L_0x2b33280 .part v0x2960210_0, 0, 1; +L_0x2b333b0 .part v0x2960210_0, 1, 1; +L_0x2b334e0 .part RS_0x7f507e9e4aa8, 12, 1; +L_0x2b33580 .part RS_0x7f507e9e4aa8, 12, 1; +L_0x2b33620 .part RS_0x7f507e9da848, 12, 1; +L_0x2b33710 .part RS_0x7f507e9f0178, 12, 1; +L_0x2b34c70 .part/pv L_0x2b34a60, 12, 1, 32; +L_0x2b34d10 .part v0x2960210_0, 0, 1; +L_0x2b33f00 .part v0x2960210_0, 1, 1; +L_0x2b34030 .part RS_0x7f507e9dde78, 12, 1; +L_0x2b340d0 .part RS_0x7f507e9dde78, 12, 1; +L_0x2b34170 .part RS_0x7f507e9da848, 12, 1; +L_0x2b34260 .part RS_0x7f507e9da848, 12, 1; +L_0x2b35640 .part/pv L_0x2b34560, 12, 1, 32; +L_0x2b34e40 .part v0x2960210_0, 2, 1; +L_0x2b34ee0 .part RS_0x7f507e9f0418, 12, 1; +L_0x2b34fd0 .part RS_0x7f507e9f0448, 12, 1; +L_0x2b350c0 .part/pv L_0x2b35160, 12, 1, 32; +L_0x2b352a0 .part RS_0x7f507e9f0478, 11, 1; +L_0x2b35340 .part RS_0x7f507e9f0b38, 12, 1; +L_0x2b365a0 .part/pv L_0x2b36390, 13, 1, 32; +L_0x2b36640 .part v0x2960210_0, 0, 1; +L_0x2b356e0 .part v0x2960210_0, 1, 1; +L_0x2b35810 .part RS_0x7f507e9e4aa8, 13, 1; +L_0x2b358b0 .part RS_0x7f507e9e4aa8, 13, 1; +L_0x2b35950 .part RS_0x7f507e9da848, 13, 1; +L_0x2b35a40 .part RS_0x7f507e9f0178, 13, 1; +L_0x2b37400 .part/pv L_0x2b371f0, 13, 1, 32; +L_0x2b36770 .part v0x2960210_0, 0, 1; +L_0x2b368a0 .part v0x2960210_0, 1, 1; +L_0x2b369d0 .part RS_0x7f507e9dde78, 13, 1; +L_0x2b36a70 .part RS_0x7f507e9dde78, 13, 1; +L_0x2b36b10 .part RS_0x7f507e9da848, 13, 1; +L_0x2b36c00 .part RS_0x7f507e9da848, 13, 1; +L_0x2b37e90 .part/pv L_0x2b37d50, 13, 1, 32; +L_0x2b37f30 .part v0x2960210_0, 2, 1; +L_0x2b374a0 .part RS_0x7f507e9f0418, 13, 1; +L_0x2b37590 .part RS_0x7f507e9f0448, 13, 1; +L_0x2b37680 .part/pv L_0x2b37720, 13, 1, 32; +L_0x2b37860 .part RS_0x7f507e9f0478, 12, 1; +L_0x2b37900 .part RS_0x7f507e9f0b38, 13, 1; +L_0x2b38d50 .part/pv L_0x2b38b40, 14, 1, 32; +L_0x2b37fd0 .part v0x2960210_0, 0, 1; +L_0x2b38100 .part v0x2960210_0, 1, 1; +L_0x2b38230 .part RS_0x7f507e9e4aa8, 14, 1; +L_0x2b382d0 .part RS_0x7f507e9e4aa8, 14, 1; +L_0x2b38370 .part RS_0x7f507e9da848, 14, 1; +L_0x2b38460 .part RS_0x7f507e9f0178, 14, 1; +L_0x2b39be0 .part/pv L_0x2b399d0, 14, 1, 32; +L_0x2b39c80 .part v0x2960210_0, 0, 1; +L_0x2b38df0 .part v0x2960210_0, 1, 1; +L_0x2b38f20 .part RS_0x7f507e9dde78, 14, 1; +L_0x2b38fc0 .part RS_0x7f507e9dde78, 14, 1; +L_0x2b39060 .part RS_0x7f507e9da848, 14, 1; +L_0x2b39150 .part RS_0x7f507e9da848, 14, 1; +L_0x2b3a6b0 .part/pv L_0x2b39510, 14, 1, 32; +L_0x2b39db0 .part v0x2960210_0, 2, 1; +L_0x2b39e50 .part RS_0x7f507e9f0418, 14, 1; +L_0x2b39f40 .part RS_0x7f507e9f0448, 14, 1; +L_0x2b3a030 .part/pv L_0x2b3a0d0, 14, 1, 32; +L_0x2b3a210 .part RS_0x7f507e9f0478, 13, 1; +L_0x2b3a2b0 .part RS_0x7f507e9f0b38, 14, 1; +L_0x2b3b520 .part/pv L_0x2b3b310, 15, 1, 32; +L_0x2b3b5c0 .part v0x2960210_0, 0, 1; +L_0x2b3a750 .part v0x2960210_0, 1, 1; +L_0x2b3a880 .part RS_0x7f507e9e4aa8, 15, 1; +L_0x2b3a920 .part RS_0x7f507e9e4aa8, 15, 1; +L_0x2b3a9c0 .part RS_0x7f507e9da848, 15, 1; +L_0x2b3aab0 .part RS_0x7f507e9f0178, 15, 1; +L_0x2b3c4c0 .part/pv L_0x2b3c2b0, 15, 1, 32; +L_0x2b3b6f0 .part v0x2960210_0, 0, 1; +L_0x2b3b820 .part v0x2960210_0, 1, 1; +L_0x2b3b950 .part RS_0x7f507e9dde78, 15, 1; +L_0x2b3b9f0 .part RS_0x7f507e9dde78, 15, 1; +L_0x2b3ba90 .part RS_0x7f507e9da848, 15, 1; +L_0x2b3bb80 .part RS_0x7f507e9da848, 15, 1; +L_0x2b3cf60 .part/pv L_0x2b3bf40, 15, 1, 32; +L_0x2b3d000 .part v0x2960210_0, 2, 1; +L_0x2b3c560 .part RS_0x7f507e9f0418, 15, 1; +L_0x2b3c650 .part RS_0x7f507e9f0448, 15, 1; +L_0x2b3c740 .part/pv L_0x2b3c7e0, 15, 1, 32; +L_0x2b3c920 .part RS_0x7f507e9f0478, 14, 1; +L_0x2b3c9c0 .part RS_0x7f507e9f0b38, 15, 1; +L_0x2b3ddf0 .part/pv L_0x2b3dbe0, 16, 1, 32; +L_0x2b3d0a0 .part v0x2960210_0, 0, 1; +L_0x2b3d1d0 .part v0x2960210_0, 1, 1; +L_0x2b3d300 .part RS_0x7f507e9e4aa8, 16, 1; +L_0x2b29fa0 .part RS_0x7f507e9e4aa8, 16, 1; +L_0x2b2a040 .part RS_0x7f507e9da848, 16, 1; +L_0x2b3d7b0 .part RS_0x7f507e9f0178, 16, 1; +L_0x2b3eea0 .part/pv L_0x2b3ec90, 16, 1, 32; +L_0x2b3ef40 .part v0x2960210_0, 0, 1; +L_0x2b3de90 .part v0x2960210_0, 1, 1; +L_0x2b3dfc0 .part RS_0x7f507e9dde78, 16, 1; +L_0x2b2a380 .part RS_0x7f507e9dde78, 16, 1; +L_0x2b2a420 .part RS_0x7f507e9da848, 16, 1; +L_0x2b3e470 .part RS_0x7f507e9da848, 16, 1; +L_0x2b3fb50 .part/pv L_0x2b2a510, 16, 1, 32; +L_0x2b2b4b0 .part v0x2960210_0, 2, 1; +L_0x2b2b550 .part RS_0x7f507e9f0418, 16, 1; +L_0x2b2ac40 .part RS_0x7f507e9f0448, 16, 1; +L_0x2b2ad30 .part/pv L_0x2b2add0, 16, 1, 32; +L_0x2b2af10 .part RS_0x7f507e9f0478, 15, 1; +L_0x2b2afb0 .part RS_0x7f507e9f0b38, 16, 1; +L_0x2b403b0 .part/pv L_0x2b401a0, 17, 1, 32; +L_0x2b40450 .part v0x2960210_0, 0, 1; +L_0x2b40580 .part v0x2960210_0, 1, 1; +L_0x2b406b0 .part RS_0x7f507e9e4aa8, 17, 1; +L_0x2b40750 .part RS_0x7f507e9e4aa8, 17, 1; +L_0x2b407f0 .part RS_0x7f507e9da848, 17, 1; +L_0x2b408e0 .part RS_0x7f507e9f0178, 17, 1; +L_0x2b420e0 .part/pv L_0x2b41ed0, 17, 1, 32; +L_0x2b40e90 .part v0x2960210_0, 0, 1; +L_0x2b40fc0 .part v0x2960210_0, 1, 1; +L_0x2b410f0 .part RS_0x7f507e9dde78, 17, 1; +L_0x2b41190 .part RS_0x7f507e9dde78, 17, 1; +L_0x2b41230 .part RS_0x7f507e9da848, 17, 1; +L_0x2b41320 .part RS_0x7f507e9da848, 17, 1; +L_0x2b41820 .part/pv L_0x2b416e0, 17, 1, 32; +L_0x2b42c80 .part v0x2960210_0, 2, 1; +L_0x2b42180 .part RS_0x7f507e9f0418, 17, 1; +L_0x2b42270 .part RS_0x7f507e9f0448, 17, 1; +L_0x2b42360 .part/pv L_0x2b42400, 17, 1, 32; +L_0x2b42540 .part RS_0x7f507e9f0478, 16, 1; +L_0x2b425e0 .part RS_0x7f507e9f0b38, 17, 1; +L_0x2b43a60 .part/pv L_0x2b43850, 18, 1, 32; +L_0x2b42d20 .part v0x2960210_0, 0, 1; +L_0x2b42e50 .part v0x2960210_0, 1, 1; +L_0x2b42f80 .part RS_0x7f507e9e4aa8, 18, 1; +L_0x2b43020 .part RS_0x7f507e9e4aa8, 18, 1; +L_0x2b430c0 .part RS_0x7f507e9da848, 18, 1; +L_0x2b431b0 .part RS_0x7f507e9f0178, 18, 1; +L_0x2b44900 .part/pv L_0x2b446f0, 18, 1, 32; +L_0x2b449a0 .part v0x2960210_0, 0, 1; +L_0x2b43b00 .part v0x2960210_0, 1, 1; +L_0x2b43c30 .part RS_0x7f507e9dde78, 18, 1; +L_0x2b43cd0 .part RS_0x7f507e9dde78, 18, 1; +L_0x2b43d70 .part RS_0x7f507e9da848, 18, 1; +L_0x2b43e60 .part RS_0x7f507e9da848, 18, 1; +L_0x2b44360 .part/pv L_0x2b44220, 18, 1, 32; +L_0x2b44400 .part v0x2960210_0, 2, 1; +L_0x2b444a0 .part RS_0x7f507e9f0418, 18, 1; +L_0x2b44590 .part RS_0x7f507e9f0448, 18, 1; +L_0x2b456e0 .part/pv L_0x2b44ad0, 18, 1, 32; +L_0x2b44bd0 .part RS_0x7f507e9f0478, 17, 1; +L_0x2b44c70 .part RS_0x7f507e9f0b38, 18, 1; +L_0x2b45560 .part/pv L_0x2b45350, 19, 1, 32; +L_0x2b46360 .part v0x2960210_0, 0, 1; +L_0x2b45780 .part v0x2960210_0, 1, 1; +L_0x2b458b0 .part RS_0x7f507e9e4aa8, 19, 1; +L_0x2b45950 .part RS_0x7f507e9e4aa8, 19, 1; +L_0x2b459f0 .part RS_0x7f507e9da848, 19, 1; +L_0x2b45ae0 .part RS_0x7f507e9f0178, 19, 1; +L_0x2b470b0 .part/pv L_0x2b461f0, 19, 1, 32; +L_0x2b46400 .part v0x2960210_0, 0, 1; +L_0x2b46530 .part v0x2960210_0, 1, 1; +L_0x2b46660 .part RS_0x7f507e9dde78, 19, 1; +L_0x2b46700 .part RS_0x7f507e9dde78, 19, 1; +L_0x2b467a0 .part RS_0x7f507e9da848, 19, 1; +L_0x2b46890 .part RS_0x7f507e9da848, 19, 1; +L_0x2b46d90 .part/pv L_0x2b46c50, 19, 1, 32; +L_0x2b46e30 .part v0x2960210_0, 2, 1; +L_0x2b46ed0 .part RS_0x7f507e9f0418, 19, 1; +L_0x2b47db0 .part RS_0x7f507e9f0448, 19, 1; +L_0x2b47150 .part/pv L_0x2b471f0, 19, 1, 32; +L_0x2b47330 .part RS_0x7f507e9f0478, 18, 1; +L_0x2b473d0 .part RS_0x7f507e9f0b38, 19, 1; +L_0x2b47cc0 .part/pv L_0x2b47ab0, 20, 1, 32; +L_0x2b48ae0 .part v0x2960210_0, 0, 1; +L_0x2b48c10 .part v0x2960210_0, 1, 1; +L_0x2b47e50 .part RS_0x7f507e9e4aa8, 20, 1; +L_0x2b47ef0 .part RS_0x7f507e9e4aa8, 20, 1; +L_0x2b47f90 .part RS_0x7f507e9da848, 20, 1; +L_0x2b48030 .part RS_0x7f507e9f0178, 20, 1; +L_0x2b48950 .part/pv L_0x2b48740, 20, 1, 32; +L_0x2b489f0 .part v0x2960210_0, 0, 1; +L_0x2b48d40 .part v0x2960210_0, 1, 1; +L_0x2b48e70 .part RS_0x7f507e9dde78, 20, 1; +L_0x2b48f10 .part RS_0x7f507e9dde78, 20, 1; +L_0x2b48fb0 .part RS_0x7f507e9da848, 20, 1; +L_0x2b49050 .part RS_0x7f507e9da848, 20, 1; +L_0x2b49550 .part/pv L_0x2b49410, 20, 1, 32; +L_0x2b495f0 .part v0x2960210_0, 2, 1; +L_0x2b49690 .part RS_0x7f507e9f0418, 20, 1; +L_0x2b49780 .part RS_0x7f507e9f0448, 20, 1; +L_0x2b49870 .part/pv L_0x2b49910, 20, 1, 32; +L_0x2b4a800 .part RS_0x7f507e9f0478, 19, 1; +L_0x2b4a8a0 .part RS_0x7f507e9f0b38, 20, 1; +L_0x2b4a290 .part/pv L_0x2b4a080, 21, 1, 32; +L_0x2b4a330 .part v0x2960210_0, 0, 1; +L_0x2b4a460 .part v0x2960210_0, 1, 1; +L_0x2b4a590 .part RS_0x7f507e9e4aa8, 21, 1; +L_0x2b4a630 .part RS_0x7f507e9e4aa8, 21, 1; +L_0x2b4a6d0 .part RS_0x7f507e9da848, 21, 1; +L_0x2b4a990 .part RS_0x7f507e9f0178, 21, 1; +L_0x2b4b270 .part/pv L_0x2b4b060, 21, 1, 32; +L_0x2b4b310 .part v0x2960210_0, 0, 1; +L_0x2b4b440 .part v0x2960210_0, 1, 1; +L_0x2b4b570 .part RS_0x7f507e9dde78, 21, 1; +L_0x2b4b610 .part RS_0x7f507e9dde78, 21, 1; +L_0x2b4c4c0 .part RS_0x7f507e9da848, 21, 1; +L_0x2b4c5b0 .part RS_0x7f507e9da848, 21, 1; +L_0x2b4b730 .part/pv L_0x2b32050, 21, 1, 32; +L_0x2b4b7d0 .part v0x2960210_0, 2, 1; +L_0x2b4b870 .part RS_0x7f507e9f0418, 21, 1; +L_0x2b4b960 .part RS_0x7f507e9f0448, 21, 1; +L_0x2b4ba50 .part/pv L_0x2b32190, 21, 1, 32; +L_0x2b4bbd0 .part RS_0x7f507e9f0478, 20, 1; +L_0x2b4bc70 .part RS_0x7f507e9f0b38, 21, 1; +L_0x2b4ddb0 .part/pv L_0x2b4c3b0, 22, 1, 32; +L_0x2b4ceb0 .part v0x2960210_0, 0, 1; +L_0x2b4cfe0 .part v0x2960210_0, 1, 1; +L_0x2b4d110 .part RS_0x7f507e9e4aa8, 22, 1; +L_0x2b4d1b0 .part RS_0x7f507e9e4aa8, 22, 1; +L_0x2b4d250 .part RS_0x7f507e9da848, 22, 1; +L_0x2b4d340 .part RS_0x7f507e9f0178, 22, 1; +L_0x2b4ec60 .part/pv L_0x2b4da20, 22, 1, 32; +L_0x2b4ed00 .part v0x2960210_0, 0, 1; +L_0x2b4de50 .part v0x2960210_0, 1, 1; +L_0x2b4df80 .part RS_0x7f507e9dde78, 22, 1; +L_0x2b4e020 .part RS_0x7f507e9dde78, 22, 1; +L_0x2b4e0c0 .part RS_0x7f507e9da848, 22, 1; +L_0x2b4e160 .part RS_0x7f507e9da848, 22, 1; +L_0x2b4e660 .part/pv L_0x2b4e520, 22, 1, 32; +L_0x2b4e700 .part v0x2960210_0, 2, 1; +L_0x2b4e7a0 .part RS_0x7f507e9f0418, 22, 1; +L_0x2b4e890 .part RS_0x7f507e9f0448, 22, 1; +L_0x2b4e980 .part/pv L_0x2b4ea20, 22, 1, 32; +L_0x2b4eb60 .part RS_0x7f507e9f0478, 21, 1; +L_0x2b4fca0 .part RS_0x7f507e9f0b38, 22, 1; +L_0x2b4f690 .part/pv L_0x2b4f480, 23, 1, 32; +L_0x2b4f730 .part v0x2960210_0, 0, 1; +L_0x2b4f860 .part v0x2960210_0, 1, 1; +L_0x2b4f990 .part RS_0x7f507e9e4aa8, 23, 1; +L_0x2b4fa30 .part RS_0x7f507e9e4aa8, 23, 1; +L_0x2b4fad0 .part RS_0x7f507e9da848, 23, 1; +L_0x2b4fbc0 .part RS_0x7f507e9f0178, 23, 1; +L_0x2b51460 .part/pv L_0x2b51250, 23, 1, 32; +L_0x2b4fd40 .part v0x2960210_0, 0, 1; +L_0x2b4fe70 .part v0x2960210_0, 1, 1; +L_0x2b4ffa0 .part RS_0x7f507e9dde78, 23, 1; +L_0x2b50040 .part RS_0x7f507e9dde78, 23, 1; +L_0x2b500e0 .part RS_0x7f507e9da848, 23, 1; +L_0x2b501d0 .part RS_0x7f507e9da848, 23, 1; +L_0x2b506d0 .part/pv L_0x2b50590, 23, 1, 32; +L_0x2b50770 .part v0x2960210_0, 2, 1; +L_0x2b50810 .part RS_0x7f507e9f0418, 23, 1; +L_0x2b50900 .part RS_0x7f507e9f0448, 23, 1; +L_0x2b509f0 .part/pv L_0x2b50a90, 23, 1, 32; +L_0x2b52410 .part RS_0x7f507e9f0478, 22, 1; +L_0x2b51500 .part RS_0x7f507e9f0b38, 23, 1; +L_0x2b51e50 .part/pv L_0x2b51c40, 24, 1, 32; +L_0x2b51ef0 .part v0x2960210_0, 0, 1; +L_0x2b52020 .part v0x2960210_0, 1, 1; +L_0x2b52150 .part RS_0x7f507e9e4aa8, 24, 1; +L_0x2b521f0 .part RS_0x7f507e9e4aa8, 24, 1; +L_0x2b52290 .part RS_0x7f507e9da848, 24, 1; +L_0x2b53400 .part RS_0x7f507e9f0178, 24, 1; +L_0x2b52cd0 .part/pv L_0x2b52ac0, 24, 1, 32; +L_0x2b52d70 .part v0x2960210_0, 0, 1; +L_0x2b52ea0 .part v0x2960210_0, 1, 1; +L_0x2b52fd0 .part RS_0x7f507e9dde78, 24, 1; +L_0x2b53070 .part RS_0x7f507e9dde78, 24, 1; +L_0x2b53110 .part RS_0x7f507e9da848, 24, 1; +L_0x2b53200 .part RS_0x7f507e9da848, 24, 1; +L_0x2b54750 .part/pv L_0x2b54610, 24, 1, 32; +L_0x2b534a0 .part v0x2960210_0, 2, 1; +L_0x2b53540 .part RS_0x7f507e9f0418, 24, 1; +L_0x2b53630 .part RS_0x7f507e9f0448, 24, 1; +L_0x2b53720 .part/pv L_0x2b537c0, 24, 1, 32; +L_0x2b53900 .part RS_0x7f507e9f0478, 23, 1; +L_0x2b539a0 .part RS_0x7f507e9f0b38, 24, 1; +L_0x2b542f0 .part/pv L_0x2b540e0, 25, 1, 32; +L_0x2b54390 .part v0x2960210_0, 0, 1; +L_0x2b547f0 .part v0x2960210_0, 1, 1; +L_0x2b54920 .part RS_0x7f507e9e4aa8, 25, 1; +L_0x2b549c0 .part RS_0x7f507e9e4aa8, 25, 1; +L_0x2b54a60 .part RS_0x7f507e9da848, 25, 1; +L_0x2b54b50 .part RS_0x7f507e9f0178, 25, 1; +L_0x2b554a0 .part/pv L_0x2b55290, 25, 1, 32; +L_0x2b55540 .part v0x2960210_0, 0, 1; +L_0x2b55670 .part v0x2960210_0, 1, 1; +L_0x2b56870 .part RS_0x7f507e9dde78, 25, 1; +L_0x2b56910 .part RS_0x7f507e9dde78, 25, 1; +L_0x2b55850 .part RS_0x7f507e9da848, 25, 1; +L_0x2b55940 .part RS_0x7f507e9da848, 25, 1; +L_0x2b55e40 .part/pv L_0x2b55d00, 25, 1, 32; +L_0x2b55ee0 .part v0x2960210_0, 2, 1; +L_0x2b55f80 .part RS_0x7f507e9f0418, 25, 1; +L_0x2b56070 .part RS_0x7f507e9f0448, 25, 1; +L_0x2b56160 .part/pv L_0x2b56200, 25, 1, 32; +L_0x2b56340 .part RS_0x7f507e9f0478, 24, 1; +L_0x2b563e0 .part RS_0x7f507e9f0b38, 25, 1; +L_0x2b57f10 .part/pv L_0x2b57d00, 26, 1, 32; +L_0x2b569b0 .part v0x2960210_0, 0, 1; +L_0x2b56ae0 .part v0x2960210_0, 1, 1; +L_0x2b56c10 .part RS_0x7f507e9e4aa8, 26, 1; +L_0x2b56cb0 .part RS_0x7f507e9e4aa8, 26, 1; +L_0x2b56d50 .part RS_0x7f507e9da848, 26, 1; +L_0x2b56e40 .part RS_0x7f507e9f0178, 26, 1; +L_0x2b57790 .part/pv L_0x2b57580, 26, 1, 32; +L_0x2b57830 .part v0x2960210_0, 0, 1; +L_0x2b57960 .part v0x2960210_0, 1, 1; +L_0x2b59100 .part RS_0x7f507e9dde78, 26, 1; +L_0x2b57fb0 .part RS_0x7f507e9dde78, 26, 1; +L_0x2b58050 .part RS_0x7f507e9da848, 26, 1; +L_0x2b58140 .part RS_0x7f507e9da848, 26, 1; +L_0x2b58640 .part/pv L_0x2b58500, 26, 1, 32; +L_0x2b586e0 .part v0x2960210_0, 2, 1; +L_0x2b58780 .part RS_0x7f507e9f0418, 26, 1; +L_0x2b58870 .part RS_0x7f507e9f0448, 26, 1; +L_0x2b58960 .part/pv L_0x2b58a00, 26, 1, 32; +L_0x2b58b40 .part RS_0x7f507e9f0478, 25, 1; +L_0x2b58be0 .part RS_0x7f507e9f0b38, 26, 1; +L_0x2b5a7b0 .part/pv L_0x2b5a5a0, 27, 1, 32; +L_0x2b5a850 .part v0x2960210_0, 0, 1; +L_0x2b591a0 .part v0x2960210_0, 1, 1; +L_0x2b592d0 .part RS_0x7f507e9e4aa8, 27, 1; +L_0x2b59370 .part RS_0x7f507e9e4aa8, 27, 1; +L_0x2b59410 .part RS_0x7f507e9da848, 27, 1; +L_0x2b59500 .part RS_0x7f507e9f0178, 27, 1; +L_0x2b59e50 .part/pv L_0x2b59c40, 27, 1, 32; +L_0x2b59ef0 .part v0x2960210_0, 0, 1; +L_0x2b5a020 .part v0x2960210_0, 1, 1; +L_0x2b5a150 .part RS_0x7f507e9dde78, 27, 1; +L_0x2b5a1f0 .part RS_0x7f507e9dde78, 27, 1; +L_0x2b5bb00 .part RS_0x7f507e9da848, 27, 1; +L_0x2b5bbf0 .part RS_0x7f507e9da848, 27, 1; +L_0x2b5ad30 .part/pv L_0x2b5abf0, 27, 1, 32; +L_0x2b5add0 .part v0x2960210_0, 2, 1; +L_0x2b5ae70 .part RS_0x7f507e9f0418, 27, 1; +L_0x2b5af60 .part RS_0x7f507e9f0448, 27, 1; +L_0x2b5b050 .part/pv L_0x2b5b0f0, 27, 1, 32; +L_0x2b5b230 .part RS_0x7f507e9f0478, 26, 1; +L_0x2b5b2d0 .part RS_0x7f507e9f0b38, 27, 1; +L_0x2b5d020 .part/pv L_0x2b5ba70, 28, 1, 32; +L_0x2b5bce0 .part v0x2960210_0, 0, 1; +L_0x2b5be10 .part v0x2960210_0, 1, 1; +L_0x2b5bf40 .part RS_0x7f507e9e4aa8, 28, 1; +L_0x2b5bfe0 .part RS_0x7f507e9e4aa8, 28, 1; +L_0x2b5c080 .part RS_0x7f507e9da848, 28, 1; +L_0x2b5c170 .part RS_0x7f507e9f0178, 28, 1; +L_0x2b5cac0 .part/pv L_0x2b5c8b0, 28, 1, 32; +L_0x2b5cb60 .part v0x2960210_0, 0, 1; +L_0x2b5cc90 .part v0x2960210_0, 1, 1; +L_0x2b5cdc0 .part RS_0x7f507e9dde78, 28, 1; +L_0x2b5e2e0 .part RS_0x7f507e9dde78, 28, 1; +L_0x2b5e380 .part RS_0x7f507e9da848, 28, 1; +L_0x2b5d0c0 .part RS_0x7f507e9da848, 28, 1; +L_0x2b5d580 .part/pv L_0x2b5d440, 28, 1, 32; +L_0x2b5d620 .part v0x2960210_0, 2, 1; +L_0x2b5d6c0 .part RS_0x7f507e9f0418, 28, 1; +L_0x2b5d7b0 .part RS_0x7f507e9f0448, 28, 1; +L_0x2b5d8a0 .part/pv L_0x2b5d940, 28, 1, 32; +L_0x2b5da80 .part RS_0x7f507e9f0478, 27, 1; +L_0x2b5db20 .part RS_0x7f507e9f0b38, 28, 1; +L_0x2b5f890 .part/pv L_0x2b5e260, 29, 1, 32; +L_0x2b5f930 .part v0x2960210_0, 0, 1; +L_0x2b5e470 .part v0x2960210_0, 1, 1; +L_0x2b5e5a0 .part RS_0x7f507e9e4aa8, 29, 1; +L_0x2b5e640 .part RS_0x7f507e9e4aa8, 29, 1; +L_0x2b5e6e0 .part RS_0x7f507e9da848, 29, 1; +L_0x2b5e7d0 .part RS_0x7f507e9f0178, 29, 1; +L_0x2b5f150 .part/pv L_0x2b5ef40, 29, 1, 32; +L_0x2b5f1f0 .part v0x2960210_0, 0, 1; +L_0x2b5f320 .part v0x2960210_0, 1, 1; +L_0x2b5f450 .part RS_0x7f507e9dde78, 29, 1; +L_0x2b5f4f0 .part RS_0x7f507e9dde78, 29, 1; +L_0x2b5f590 .part RS_0x7f507e9da848, 29, 1; +L_0x2b60d30 .part RS_0x7f507e9da848, 29, 1; +L_0x2b5fdd0 .part/pv L_0x2b5fc90, 29, 1, 32; +L_0x2b5fe70 .part v0x2960210_0, 2, 1; +L_0x2b5ff10 .part RS_0x7f507e9f0418, 29, 1; +L_0x2b60000 .part RS_0x7f507e9f0448, 29, 1; +L_0x2b600f0 .part/pv L_0x2b60190, 29, 1, 32; +L_0x2b602d0 .part RS_0x7f507e9f0478, 28, 1; +L_0x2b60370 .part RS_0x7f507e9f0b38, 29, 1; +L_0x2b62130 .part/pv L_0x2b60b40, 30, 1, 32; +L_0x2b60dd0 .part v0x2960210_0, 0, 1; +L_0x2b60f00 .part v0x2960210_0, 1, 1; +L_0x2b61030 .part RS_0x7f507e9e4aa8, 30, 1; +L_0x2b610d0 .part RS_0x7f507e9e4aa8, 30, 1; +L_0x2b61170 .part RS_0x7f507e9da848, 30, 1; +L_0x2b61260 .part RS_0x7f507e9f0178, 30, 1; +L_0x2b61b80 .part/pv L_0x2b61970, 30, 1, 32; +L_0x2b61c20 .part v0x2960210_0, 0, 1; +L_0x2b61d50 .part v0x2960210_0, 1, 1; +L_0x2b61e80 .part RS_0x7f507e9dde78, 30, 1; +L_0x2b61f20 .part RS_0x7f507e9dde78, 30, 1; +L_0x2b61fc0 .part RS_0x7f507e9da848, 30, 1; +L_0x2b63550 .part RS_0x7f507e9da848, 30, 1; +L_0x2b63a50 .part/pv L_0x2b63910, 30, 1, 32; +L_0x2b621d0 .part v0x2960210_0, 2, 1; +L_0x2b62270 .part RS_0x7f507e9f0418, 30, 1; +L_0x2b62360 .part RS_0x7f507e9f0448, 30, 1; +L_0x2b62450 .part/pv L_0x2b624f0, 30, 1, 32; +L_0x2b62630 .part RS_0x7f507e9f0478, 29, 1; +L_0x2b626d0 .part RS_0x7f507e9f0b38, 30, 1; +L_0x2b62ff0 .part/pv L_0x2b62de0, 31, 1, 32; +L_0x2b63090 .part v0x2960210_0, 0, 1; +L_0x2b631c0 .part v0x2960210_0, 1, 1; +L_0x2b632f0 .part RS_0x7f507e9e4aa8, 31, 1; +L_0x2b63390 .part RS_0x7f507e9e4aa8, 31, 1; +L_0x2b63430 .part RS_0x7f507e9da848, 31, 1; +L_0x2b64ee0 .part RS_0x7f507e9f0178, 31, 1; +L_0x2b65a00 .part/pv L_0x2b657f0, 31, 1, 32; +L_0x2b63af0 .part v0x2960210_0, 0, 1; +L_0x2b63c20 .part v0x2960210_0, 1, 1; +L_0x2b63d50 .part RS_0x7f507e9dde78, 31, 1; +L_0x2b63df0 .part RS_0x7f507e9dde78, 31, 1; +L_0x2b63e90 .part RS_0x7f507e9da848, 31, 1; +L_0x2b63f80 .part RS_0x7f507e9da848, 31, 1; +L_0x2b64480 .part/pv L_0x2b64340, 31, 1, 32; +L_0x2b64520 .part v0x2960210_0, 2, 1; +L_0x2b645c0 .part RS_0x7f507e9f0418, 31, 1; +L_0x2b646b0 .part RS_0x7f507e9f0448, 31, 1; +L_0x2b647a0 .part/pv L_0x2b64840, 31, 1, 32; +L_0x2b64980 .part RS_0x7f507e9f0478, 30, 1; +L_0x2b64a20 .part RS_0x7f507e9f0b38, 31, 1; +L_0x2c13460 .part/pv L_0x2c13280, 0, 1, 32; +L_0x2b65aa0 .part v0x2960210_0, 0, 1; +L_0x2b65bd0 .part v0x2960210_0, 1, 1; +L_0x2b65d00 .part RS_0x7f507e9e4aa8, 0, 1; +L_0x2b65da0 .part RS_0x7f507e9e4aa8, 0, 1; +L_0x2b65e40 .part RS_0x7f507e9da848, 0, 1; +L_0x2b65f30 .part RS_0x7f507e9f0178, 0, 1; +L_0x2b66730 .part/pv L_0x2b66550, 0, 1, 32; +L_0x2b667d0 .part v0x2960210_0, 0, 1; +L_0x2b66900 .part v0x2960210_0, 1, 1; +L_0x2b66a30 .part RS_0x7f507e9dde78, 0, 1; +L_0x2b66ad0 .part RS_0x7f507e9dde78, 0, 1; +L_0x2b66b70 .part RS_0x7f507e9da848, 0, 1; +L_0x2b66c60 .part RS_0x7f507e9da848, 0, 1; +L_0x2b4c8d0 .part/pv L_0x2b4c790, 0, 1, 32; +L_0x2b3fbf0 .part v0x2960210_0, 2, 1; +L_0x2b3fc90 .part RS_0x7f507e9f0418, 0, 1; +L_0x2b3fd80 .part RS_0x7f507e9f0448, 0, 1; +L_0x2b3fe70 .part/pv L_0x2b3ff10, 0, 1, 32; +L_0x2c14570 .part RS_0x7f507e9f0b38, 0, 1; +L_0x2c14610 .part RS_0x7f507e9f0b38, 0, 1; +L_0x2c14810 .part RS_0x7f507e9f0478, 31, 1; +S_0x2753240 .scope module, "test" "SLT32" 3 52, 3 298, S_0x1f6b890; + .timescale -9 -12; +P_0x24071c8 .param/l "size" 3 330, +C4<0100000>; +L_0x2ba8c20/d .functor NOT 1, L_0x2ba8d30, C4<0>, C4<0>, C4<0>; +L_0x2ba8c20 .delay (10000,10000,10000) L_0x2ba8c20/d; +L_0x2ba8dd0/d .functor AND 1, L_0x2ba8f10, L_0x2ba8fb0, L_0x2ba8c20, C4<1>; +L_0x2ba8dd0 .delay (20000,20000,20000) L_0x2ba8dd0/d; +L_0x2b886f0/d .functor OR 1, L_0x2baa410, C4<0>, C4<0>, C4<0>; +L_0x2b886f0 .delay (20000,20000,20000) L_0x2b886f0/d; +L_0x2bab990/d .functor XOR 1, RS_0x7f507e9e4bc8, L_0x2babac0, C4<0>, C4<0>; +L_0x2bab990 .delay (40000,40000,40000) L_0x2bab990/d; +L_0x2babb60/d .functor NOT 1, RS_0x7f507e9e4bf8, C4<0>, C4<0>, C4<0>; +L_0x2babb60 .delay (10000,10000,10000) L_0x2babb60/d; +L_0x2ba6870/d .functor NOT 1, L_0x2ba6970, C4<0>, C4<0>, C4<0>; +L_0x2ba6870 .delay (10000,10000,10000) L_0x2ba6870/d; +L_0x2ba6a10/d .functor AND 1, L_0x2babb60, L_0x2b88880, C4<1>, C4<1>; +L_0x2ba6a10 .delay (20000,20000,20000) L_0x2ba6a10/d; +L_0x2b88920/d .functor AND 1, RS_0x7f507e9e4bf8, L_0x2ba6870, C4<1>, C4<1>; +L_0x2b88920 .delay (20000,20000,20000) L_0x2b88920/d; +L_0x2b88a60/d .functor AND 1, L_0x2ba6a10, L_0x2ba8dd0, C4<1>, C4<1>; +L_0x2b88a60 .delay (20000,20000,20000) L_0x2b88a60/d; +L_0x2b88b80/d .functor AND 1, L_0x2b88920, L_0x2ba8dd0, C4<1>, C4<1>; +L_0x2b88b80 .delay (20000,20000,20000) L_0x2b88b80/d; +L_0x2bad020/d .functor OR 1, L_0x2b88a60, L_0x2b88b80, C4<0>, C4<0>; +L_0x2bad020 .delay (20000,20000,20000) L_0x2bad020/d; +v0x2409470_0 .alias "A", 31 0, v0x295f580_0; +RS_0x7f507e9f0088/0/0 .resolv tri, L_0x21be620, L_0x2b6a940, L_0x2b6ca60, L_0x2b6ec10; +RS_0x7f507e9f0088/0/4 .resolv tri, L_0x2b70d10, L_0x2b72e50, L_0x2b75280, L_0x2b77670; +RS_0x7f507e9f0088/0/8 .resolv tri, L_0x2b79a60, L_0x2b7bd90, L_0x2b7e070, L_0x2b80360; +RS_0x7f507e9f0088/0/12 .resolv tri, L_0x2b824d0, L_0x2b84860, L_0x2b869b0, L_0x2b88ce0; +RS_0x7f507e9f0088/0/16 .resolv tri, L_0x2b68120, L_0x2b8da20, L_0x2b8fbd0, L_0x2b91ca0; +RS_0x7f507e9f0088/0/20 .resolv tri, L_0x2b93e90, L_0x2b95f80, L_0x2b96f20, L_0x2b9a640; +RS_0x7f507e9f0088/0/24 .resolv tri, L_0x2b9adf0, L_0x2b9e880, L_0x2b9f050, L_0x2ba18c0; +RS_0x7f507e9f0088/0/28 .resolv tri, L_0x2ba3930, L_0x2ba7160, L_0x2ba7910, L_0x2baa120; +RS_0x7f507e9f0088/1/0 .resolv tri, RS_0x7f507e9f0088/0/0, RS_0x7f507e9f0088/0/4, RS_0x7f507e9f0088/0/8, RS_0x7f507e9f0088/0/12; +RS_0x7f507e9f0088/1/4 .resolv tri, RS_0x7f507e9f0088/0/16, RS_0x7f507e9f0088/0/20, RS_0x7f507e9f0088/0/24, RS_0x7f507e9f0088/0/28; +RS_0x7f507e9f0088 .resolv tri, RS_0x7f507e9f0088/1/0, RS_0x7f507e9f0088/1/4, C4, C4; +v0x2411b80_0 .net8 "AddSubSLTSum", 31 0, RS_0x7f507e9f0088; 32 drivers +v0x2411c20_0 .alias "B", 31 0, v0x295f6a0_0; +RS_0x7f507e9f00b8/0/0 .resolv tri, L_0x2b67b10, L_0x2b6a090, L_0x2b6c240, L_0x2b6d2f0; +RS_0x7f507e9f00b8/0/4 .resolv tri, L_0x2b70540, L_0x2b714b0, L_0x2b74a20, L_0x2b75a90; +RS_0x7f507e9f00b8/0/8 .resolv tri, L_0x2b79200, L_0x2b7a270, L_0x2b7d820, L_0x2b7eca0; +RS_0x7f507e9f00b8/0/12 .resolv tri, L_0x2b81cb0, L_0x2b82cf0, L_0x2b86180, L_0x2b87150; +RS_0x7f507e9f00b8/0/16 .resolv tri, L_0x2b8a840, L_0x2b8bf00, L_0x2b8f390, L_0x2b8fd60; +RS_0x7f507e9f00b8/0/20 .resolv tri, L_0x2b93630, L_0x2b94020, L_0x2b97d10, L_0x2b986c0; +RS_0x7f507e9f00b8/0/24 .resolv tri, L_0x2b9bec0, L_0x2b9c880, L_0x2ba00f0, L_0x2ba10c0; +RS_0x7f507e9f00b8/0/28 .resolv tri, L_0x2ba4500, L_0x2ba54d0, L_0x2ba8a40, L_0x2bab040; +RS_0x7f507e9f00b8/1/0 .resolv tri, RS_0x7f507e9f00b8/0/0, RS_0x7f507e9f00b8/0/4, RS_0x7f507e9f00b8/0/8, RS_0x7f507e9f00b8/0/12; +RS_0x7f507e9f00b8/1/4 .resolv tri, RS_0x7f507e9f00b8/0/16, RS_0x7f507e9f00b8/0/20, RS_0x7f507e9f00b8/0/24, RS_0x7f507e9f00b8/0/28; +RS_0x7f507e9f00b8 .resolv tri, RS_0x7f507e9f00b8/1/0, RS_0x7f507e9f00b8/1/4, C4, C4; +v0x24118d0_0 .net8 "CarryoutWire", 31 0, RS_0x7f507e9f00b8; 32 drivers +v0x2411970_0 .alias "Command", 2 0, v0x295f7a0_0; +RS_0x7f507e9f00e8/0/0 .resolv tri, L_0x2b67a20, L_0x2b69f30, L_0x2b6c150, L_0x2b6e280; +RS_0x7f507e9f00e8/0/4 .resolv tri, L_0x2b70450, L_0x2b724a0, L_0x2b74930, L_0x2b76c20; +RS_0x7f507e9f00e8/0/8 .resolv tri, L_0x2b79110, L_0x2b7b440, L_0x2b7d730, L_0x2b7faa0; +RS_0x7f507e9f00e8/0/12 .resolv tri, L_0x2b81bc0, L_0x2b83d80, L_0x2b86090, L_0x2b881e0; +RS_0x7f507e9f00e8/0/16 .resolv tri, L_0x2b8a750, L_0x2b8d0f0, L_0x2b8f2a0, L_0x2b91370; +RS_0x7f507e9f00e8/0/20 .resolv tri, L_0x2b93540, L_0x2b95640, L_0x2b97c20, L_0x2b99ce0; +RS_0x7f507e9f00e8/0/24 .resolv tri, L_0x2b9bdd0, L_0x2b9dec0, L_0x2ba0000, L_0x2ba2210; +RS_0x7f507e9f00e8/0/28 .resolv tri, L_0x2ba4410, L_0x2ba65f0, L_0x2ba8950, L_0x2baaf50; +RS_0x7f507e9f00e8/1/0 .resolv tri, RS_0x7f507e9f00e8/0/0, RS_0x7f507e9f00e8/0/4, RS_0x7f507e9f00e8/0/8, RS_0x7f507e9f00e8/0/12; +RS_0x7f507e9f00e8/1/4 .resolv tri, RS_0x7f507e9f00e8/0/16, RS_0x7f507e9f00e8/0/20, RS_0x7f507e9f00e8/0/24, RS_0x7f507e9f00e8/0/28; +RS_0x7f507e9f00e8 .resolv tri, RS_0x7f507e9f00e8/1/0, RS_0x7f507e9f00e8/1/4, C4, C4; +v0x2411620_0 .net8 "NewVal", 31 0, RS_0x7f507e9f00e8; 32 drivers +v0x24116c0_0 .net "Res0OF1", 0 0, L_0x2b88920; 1 drivers +v0x2411380_0 .net "Res1OF0", 0 0, L_0x2ba6a10; 1 drivers +v0x2411420_0 .alias "SLTSum", 31 0, v0x24150b0_0; +v0x240fa90_0 .alias "SLTflag", 0 0, v0x2415130_0; +v0x240fb10_0 .net "SLTflag0", 0 0, L_0x2b88a60; 1 drivers +v0x240f7e0_0 .net "SLTflag1", 0 0, L_0x2b88b80; 1 drivers +v0x240f880_0 .net "SLTon", 0 0, L_0x2ba8dd0; 1 drivers +v0x2412da0_0 .net *"_s497", 0 0, L_0x2ba8d30; 1 drivers +v0x240f530_0 .net *"_s499", 0 0, L_0x2ba8f10; 1 drivers +v0x240f5d0_0 .net *"_s501", 0 0, L_0x2ba8fb0; 1 drivers +v0x2412e20_0 .net *"_s521", 0 0, L_0x2baa410; 1 drivers +v0x240f360_0 .net/s *"_s522", 0 0, C4<0>; 1 drivers +v0x240f290_0 .net *"_s525", 0 0, L_0x2babac0; 1 drivers +v0x2417a40_0 .net *"_s527", 0 0, L_0x2ba6970; 1 drivers +v0x24177a0_0 .net *"_s529", 0 0, L_0x2b88880; 1 drivers +v0x24179a0_0 .alias "carryin", 31 0, v0x2609fe0_0; +v0x2417500_0 .alias "carryout", 0 0, v0x2960740_0; +v0x24176f0_0 .net "nAddSubSLTSum", 0 0, L_0x2ba6870; 1 drivers +v0x2417270_0 .net "nCmd2", 0 0, L_0x2ba8c20; 1 drivers +v0x2417440_0 .net "nOF", 0 0, L_0x2babb60; 1 drivers +v0x24171a0_0 .alias "overflow", 0 0, v0x29608f0_0; +v0x2415600_0 .alias "subtract", 31 0, v0x25ec920_0; +L_0x2b67a20 .part/pv L_0x2b67590, 1, 1, 32; +L_0x2b67b10 .part/pv L_0x2b678e0, 1, 1, 32; +L_0x2b67c00 .part/pv L_0x2b672c0, 1, 1, 32; +L_0x2b67cf0 .part v0x295fe90_0, 1, 1; +L_0x2b67d90 .part v0x2960190_0, 1, 1; +L_0x2b67ec0 .part RS_0x7f507e9f00b8, 0, 1; +L_0x21be620 .part/pv L_0x21be4e0, 1, 1, 32; +L_0x2b687d0 .part RS_0x7f507e9f00e8, 1, 1; +L_0x2b68d70 .part/pv L_0x2b68c30, 1, 1, 32; +L_0x2b68e10 .part RS_0x7f507e9f0088, 1, 1; +L_0x2b68fb0 .part RS_0x7f507e9f0088, 1, 1; +L_0x2b69f30 .part/pv L_0x2b69aa0, 2, 1, 32; +L_0x2b6a090 .part/pv L_0x2b69df0, 2, 1, 32; +L_0x2b6a180 .part/pv L_0x2b697d0, 2, 1, 32; +L_0x2b6a330 .part v0x295fe90_0, 2, 1; +L_0x2b6a3d0 .part v0x2960190_0, 2, 1; +L_0x2b6a590 .part RS_0x7f507e9f00b8, 1, 1; +L_0x2b6a940 .part/pv L_0x2b6a800, 2, 1, 32; +L_0x2b6ab10 .part RS_0x7f507e9f00e8, 2, 1; +L_0x2b6afd0 .part/pv L_0x2b6ae90, 2, 1, 32; +L_0x2b6aa70 .part RS_0x7f507e9f0088, 2, 1; +L_0x2b6b170 .part RS_0x7f507e9f0088, 2, 1; +L_0x2b6c150 .part/pv L_0x2b6bcc0, 3, 1, 32; +L_0x2b6c240 .part/pv L_0x2b6c010, 3, 1, 32; +L_0x2b6b260 .part/pv L_0x2b6b9f0, 3, 1, 32; +L_0x2b6c450 .part v0x295fe90_0, 3, 1; +L_0x2b6c330 .part v0x2960190_0, 3, 1; +L_0x2b6c660 .part RS_0x7f507e9f00b8, 2, 1; +L_0x2b6ca60 .part/pv L_0x2b6c920, 3, 1, 32; +L_0x2b6cb00 .part RS_0x7f507e9f00e8, 3, 1; +L_0x2b6d050 .part/pv L_0x2b6cf10, 3, 1, 32; +L_0x2b6d0f0 .part RS_0x7f507e9f0088, 3, 1; +L_0x2b6cbf0 .part RS_0x7f507e9f0088, 3, 1; +L_0x2b6e280 .part/pv L_0x2b6ddf0, 4, 1, 32; +L_0x2b6d2f0 .part/pv L_0x2b6e140, 4, 1, 32; +L_0x2b6e490 .part/pv L_0x2b6db20, 4, 1, 32; +L_0x2b6e370 .part v0x295fe90_0, 4, 1; +L_0x2b6e6b0 .part v0x2960190_0, 4, 1; +L_0x2b6e580 .part RS_0x7f507e9f00b8, 3, 1; +L_0x2b6ec10 .part/pv L_0x2b6ead0, 4, 1, 32; +L_0x2b6e7e0 .part RS_0x7f507e9f00e8, 4, 1; +L_0x2b6f2a0 .part/pv L_0x2b6f160, 4, 1, 32; +L_0x2b6ecb0 .part RS_0x7f507e9f0088, 4, 1; +L_0x2b6f4a0 .part RS_0x7f507e9f0088, 4, 1; +L_0x2b70450 .part/pv L_0x2b6ffc0, 5, 1, 32; +L_0x2b70540 .part/pv L_0x2b70310, 5, 1, 32; +L_0x2b6f540 .part/pv L_0x2b6fcf0, 5, 1, 32; +L_0x2b707b0 .part v0x295fe90_0, 5, 1; +L_0x2b70630 .part v0x2960190_0, 5, 1; +L_0x2b709e0 .part RS_0x7f507e9f00b8, 4, 1; +L_0x2b70d10 .part/pv L_0x2b70c20, 5, 1, 32; +L_0x2b70db0 .part RS_0x7f507e9f00e8, 5, 1; +L_0x2b71320 .part/pv L_0x2b711e0, 5, 1, 32; +L_0x2b713c0 .part RS_0x7f507e9f0088, 5, 1; +L_0x2b70ea0 .part RS_0x7f507e9f0088, 5, 1; +L_0x2b724a0 .part/pv L_0x2b72010, 6, 1, 32; +L_0x2b714b0 .part/pv L_0x2b72360, 6, 1, 32; +L_0x2b715a0 .part/pv L_0x2b71d40, 6, 1, 32; +L_0x2b72590 .part v0x295fe90_0, 6, 1; +L_0x2b72630 .part v0x2960190_0, 6, 1; +L_0x2b72a60 .part RS_0x7f507e9f00b8, 5, 1; +L_0x2b72e50 .part/pv L_0x2b72cf0, 6, 1, 32; +L_0x2b6d1e0 .part RS_0x7f507e9f00e8, 6, 1; +L_0x2b735f0 .part/pv L_0x2b6f090, 6, 1, 32; +L_0x2b73100 .part RS_0x7f507e9f0088, 6, 1; +L_0x2b731f0 .part RS_0x7f507e9f0088, 6, 1; +L_0x2b74930 .part/pv L_0x2b74420, 7, 1, 32; +L_0x2b74a20 .part/pv L_0x2b747d0, 7, 1, 32; +L_0x2b73690 .part/pv L_0x2b74150, 7, 1, 32; +L_0x2b73780 .part v0x295fe90_0, 7, 1; +L_0x2b74d50 .part v0x2960190_0, 7, 1; +L_0x2b74df0 .part RS_0x7f507e9f00b8, 6, 1; +L_0x2b75280 .part/pv L_0x2b75120, 7, 1, 32; +L_0x2b75320 .part RS_0x7f507e9f00e8, 7, 1; +L_0x2b75900 .part/pv L_0x2b757a0, 7, 1, 32; +L_0x2b759a0 .part RS_0x7f507e9f0088, 7, 1; +L_0x2b75410 .part RS_0x7f507e9f0088, 7, 1; +L_0x2b76c20 .part/pv L_0x2b76730, 8, 1, 32; +L_0x2b75a90 .part/pv L_0x2b76ac0, 8, 1, 32; +L_0x2b75b80 .part/pv L_0x2b76460, 8, 1, 32; +L_0x2b76fa0 .part v0x295fe90_0, 8, 1; +L_0x2b77040 .part v0x2960190_0, 8, 1; +L_0x2b76d10 .part RS_0x7f507e9f00b8, 7, 1; +L_0x2b77670 .part/pv L_0x2b76f20, 8, 1, 32; +L_0x2b770e0 .part RS_0x7f507e9f00e8, 8, 1; +L_0x2b77e40 .part/pv L_0x2b733b0, 8, 1, 32; +L_0x2b77710 .part RS_0x7f507e9f0088, 8, 1; +L_0x2b777b0 .part RS_0x7f507e9f0088, 8, 1; +L_0x2b79110 .part/pv L_0x2b78c20, 9, 1, 32; +L_0x2b79200 .part/pv L_0x2b78fb0, 9, 1, 32; +L_0x2b77ee0 .part/pv L_0x2b78950, 9, 1, 32; +L_0x2b77fd0 .part v0x295fe90_0, 9, 1; +L_0x2b78070 .part v0x2960190_0, 9, 1; +L_0x2b795e0 .part RS_0x7f507e9f00b8, 8, 1; +L_0x2b79a60 .part/pv L_0x2b79560, 9, 1, 32; +L_0x2b79b00 .part RS_0x7f507e9f00e8, 9, 1; +L_0x2b7a0e0 .part/pv L_0x2b79fa0, 9, 1, 32; +L_0x2b7a180 .part RS_0x7f507e9f0088, 9, 1; +L_0x2b79bf0 .part RS_0x7f507e9f0088, 9, 1; +L_0x2b7b440 .part/pv L_0x2b7af30, 10, 1, 32; +L_0x2b7a270 .part/pv L_0x2b7b2e0, 10, 1, 32; +L_0x2b7a360 .part/pv L_0x2b7ac60, 10, 1, 32; +L_0x2b7a450 .part v0x295fe90_0, 10, 1; +L_0x2b7a4f0 .part v0x2960190_0, 10, 1; +L_0x2b7b530 .part RS_0x7f507e9f00b8, 9, 1; +L_0x2b7bd90 .part/pv L_0x2b7bc50, 10, 1, 32; +L_0x2b7b900 .part RS_0x7f507e9f00e8, 10, 1; +L_0x2b7c410 .part/pv L_0x2b79820, 10, 1, 32; +L_0x2b7be30 .part RS_0x7f507e9f0088, 10, 1; +L_0x2b7bf20 .part RS_0x7f507e9f0088, 10, 1; +L_0x2b7d730 .part/pv L_0x2b7d240, 11, 1, 32; +L_0x2b7d820 .part/pv L_0x2b7d5d0, 11, 1, 32; +L_0x2b7c4b0 .part/pv L_0x2b7cf70, 11, 1, 32; +L_0x2b7c5a0 .part v0x295fe90_0, 11, 1; +L_0x2b7c640 .part v0x2960190_0, 11, 1; +L_0x2b7c770 .part RS_0x7f507e9f00b8, 10, 1; +L_0x2b7e070 .part/pv L_0x2b7df10, 11, 1, 32; +L_0x2b7e110 .part RS_0x7f507e9f00e8, 11, 1; +L_0x2b7e700 .part/pv L_0x2b7e5c0, 11, 1, 32; +L_0x2b7e7a0 .part RS_0x7f507e9f0088, 11, 1; +L_0x2b72ef0 .part RS_0x7f507e9f0088, 11, 1; +L_0x2b7faa0 .part/pv L_0x2b7f610, 12, 1, 32; +L_0x2b7eca0 .part/pv L_0x2b7f960, 12, 1, 32; +L_0x2b7ed90 .part/pv L_0x2b7f340, 12, 1, 32; +L_0x2b7ee80 .part v0x295fe90_0, 12, 1; +L_0x2b7ef20 .part v0x2960190_0, 12, 1; +L_0x2b7ff90 .part RS_0x7f507e9f00b8, 11, 1; +L_0x2b80360 .part/pv L_0x2b80220, 12, 1, 32; +L_0x2b7fb90 .part RS_0x7f507e9f00e8, 12, 1; +L_0x2b7c370 .part/pv L_0x2b7c210, 12, 1, 32; +L_0x2b80400 .part RS_0x7f507e9f0088, 12, 1; +L_0x2b804f0 .part RS_0x7f507e9f0088, 12, 1; +L_0x2b81bc0 .part/pv L_0x2b81730, 13, 1, 32; +L_0x2b81cb0 .part/pv L_0x2b81a80, 13, 1, 32; +L_0x2b80aa0 .part/pv L_0x2b81460, 13, 1, 32; +L_0x2b80b90 .part v0x295fe90_0, 13, 1; +L_0x2b80c30 .part v0x2960190_0, 13, 1; +L_0x2b80d60 .part RS_0x7f507e9f00b8, 12, 1; +L_0x2b824d0 .part/pv L_0x2b82390, 13, 1, 32; +L_0x2b82570 .part RS_0x7f507e9f00e8, 13, 1; +L_0x2b82b60 .part/pv L_0x2b82110, 13, 1, 32; +L_0x2b82c00 .part RS_0x7f507e9f0088, 13, 1; +L_0x2b82660 .part RS_0x7f507e9f0088, 13, 1; +L_0x2b83d80 .part/pv L_0x2b838f0, 14, 1, 32; +L_0x2b82cf0 .part/pv L_0x2b83c40, 14, 1, 32; +L_0x2b82de0 .part/pv L_0x2b83620, 14, 1, 32; +L_0x2b72760 .part v0x295fe90_0, 14, 1; +L_0x2b84310 .part v0x2960190_0, 14, 1; +L_0x2b83e70 .part RS_0x7f507e9f00b8, 13, 1; +L_0x2b84860 .part/pv L_0x2b84180, 14, 1, 32; +L_0x2b843b0 .part RS_0x7f507e9f00e8, 14, 1; +L_0x2b84ea0 .part/pv L_0x2b80a30, 14, 1, 32; +L_0x2b84900 .part RS_0x7f507e9f0088, 14, 1; +L_0x2b849f0 .part RS_0x7f507e9f0088, 14, 1; +L_0x2b86090 .part/pv L_0x2b85c00, 15, 1, 32; +L_0x2b86180 .part/pv L_0x2b85f50, 15, 1, 32; +L_0x2b84f40 .part/pv L_0x2b85930, 15, 1, 32; +L_0x2b85030 .part v0x295fe90_0, 15, 1; +L_0x2b850d0 .part v0x2960190_0, 15, 1; +L_0x2b85200 .part RS_0x7f507e9f00b8, 14, 1; +L_0x2b869b0 .part/pv L_0x2b86870, 15, 1, 32; +L_0x2b86a50 .part RS_0x7f507e9f00e8, 15, 1; +L_0x2b866e0 .part/pv L_0x2b865a0, 15, 1, 32; +L_0x2b87060 .part RS_0x7f507e9f0088, 15, 1; +L_0x2b86b40 .part RS_0x7f507e9f0088, 15, 1; +L_0x2b881e0 .part/pv L_0x2b87d50, 16, 1, 32; +L_0x2b87150 .part/pv L_0x2b880a0, 16, 1, 32; +L_0x2b87240 .part/pv L_0x2b87a80, 16, 1, 32; +L_0x2b87330 .part v0x295fe90_0, 16, 1; +L_0x2b873d0 .part v0x2960190_0, 16, 1; +L_0x2b87500 .part RS_0x7f507e9f00b8, 15, 1; +L_0x2b88ce0 .part/pv L_0x2b774f0, 16, 1, 32; +L_0x2b882d0 .part RS_0x7f507e9f00e8, 16, 1; +L_0x2b895a0 .part/pv L_0x2b84620, 16, 1, 32; +L_0x2b88d80 .part RS_0x7f507e9f0088, 16, 1; +L_0x2b88e70 .part RS_0x7f507e9f0088, 16, 1; +L_0x2b8a750 .part/pv L_0x2b8a2c0, 17, 1, 32; +L_0x2b8a840 .part/pv L_0x2b8a610, 17, 1, 32; +L_0x2b89640 .part/pv L_0x2b89ff0, 17, 1, 32; +L_0x2b89730 .part v0x295fe90_0, 17, 1; +L_0x2b897d0 .part v0x2960190_0, 17, 1; +L_0x2b89900 .part RS_0x7f507e9f00b8, 16, 1; +L_0x2b68120 .part/pv L_0x2b67fc0, 17, 1, 32; +L_0x2b681c0 .part RS_0x7f507e9f00e8, 17, 1; +L_0x2b8a930 .part/pv L_0x2b68620, 17, 1, 32; +L_0x2b8a9d0 .part RS_0x7f507e9f0088, 17, 1; +L_0x2b8aac0 .part RS_0x7f507e9f0088, 17, 1; +L_0x2b8d0f0 .part/pv L_0x2b8cc60, 18, 1, 32; +L_0x2b8bf00 .part/pv L_0x2b8cfb0, 18, 1, 32; +L_0x2b8bff0 .part/pv L_0x2b8c990, 18, 1, 32; +L_0x2b8c0e0 .part v0x295fe90_0, 18, 1; +L_0x2b8c180 .part v0x2960190_0, 18, 1; +L_0x2b8c2b0 .part RS_0x7f507e9f00b8, 17, 1; +L_0x2b8da20 .part/pv L_0x2b8d8e0, 18, 1, 32; +L_0x2b8d1e0 .part RS_0x7f507e9f00e8, 18, 1; +L_0x2b8e0e0 .part/pv L_0x2b893e0, 18, 1, 32; +L_0x2b8dac0 .part RS_0x7f507e9f0088, 18, 1; +L_0x2b8dbb0 .part RS_0x7f507e9f0088, 18, 1; +L_0x2b8f2a0 .part/pv L_0x2b8ee10, 19, 1, 32; +L_0x2b8f390 .part/pv L_0x2b8f160, 19, 1, 32; +L_0x2b8e180 .part/pv L_0x2b8eb40, 19, 1, 32; +L_0x2b8e270 .part v0x295fe90_0, 19, 1; +L_0x2b8e310 .part v0x2960190_0, 19, 1; +L_0x2b8e440 .part RS_0x7f507e9f00b8, 18, 1; +L_0x2b8fbd0 .part/pv L_0x2b8e730, 19, 1, 32; +L_0x2b8fc70 .part RS_0x7f507e9f00e8, 19, 1; +L_0x2b8f910 .part/pv L_0x2b8f7d0, 19, 1, 32; +L_0x2b8f9b0 .part RS_0x7f507e9f0088, 19, 1; +L_0x2b903f0 .part RS_0x7f507e9f0088, 19, 1; +L_0x2b91370 .part/pv L_0x2b90ee0, 20, 1, 32; +L_0x2b8fd60 .part/pv L_0x2b91230, 20, 1, 32; +L_0x2b8fe50 .part/pv L_0x2b90c10, 20, 1, 32; +L_0x2b8ff40 .part v0x295fe90_0, 20, 1; +L_0x2b8ffe0 .part v0x2960190_0, 20, 1; +L_0x2b90110 .part RS_0x7f507e9f00b8, 19, 1; +L_0x2b91ca0 .part/pv L_0x2b91b60, 20, 1, 32; +L_0x2b91460 .part RS_0x7f507e9f00e8, 20, 1; +L_0x2b8d4f0 .part/pv L_0x2b8d400, 20, 1, 32; +L_0x2b92420 .part RS_0x7f507e9f0088, 20, 1; +L_0x2b924c0 .part RS_0x7f507e9f0088, 20, 1; +L_0x2b93540 .part/pv L_0x2b930b0, 21, 1, 32; +L_0x2b93630 .part/pv L_0x2b93400, 21, 1, 32; +L_0x2b925b0 .part/pv L_0x2b92de0, 21, 1, 32; +L_0x2b926a0 .part v0x295fe90_0, 21, 1; +L_0x2b92740 .part v0x2960190_0, 21, 1; +L_0x2b92870 .part RS_0x7f507e9f00b8, 20, 1; +L_0x2b93e90 .part/pv L_0x2b92b60, 21, 1, 32; +L_0x2b93f30 .part RS_0x7f507e9f00e8, 21, 1; +L_0x2b93bb0 .part/pv L_0x2b93a70, 21, 1, 32; +L_0x2b93c50 .part RS_0x7f507e9f0088, 21, 1; +L_0x2b93d40 .part RS_0x7f507e9f0088, 21, 1; +L_0x2b95640 .part/pv L_0x2b951b0, 22, 1, 32; +L_0x2b94020 .part/pv L_0x2b95500, 22, 1, 32; +L_0x2b94110 .part/pv L_0x2b94ee0, 22, 1, 32; +L_0x2b94200 .part v0x295fe90_0, 22, 1; +L_0x2b942a0 .part v0x2960190_0, 22, 1; +L_0x2b943d0 .part RS_0x7f507e9f00b8, 21, 1; +L_0x2b95f80 .part/pv L_0x2b946e0, 22, 1, 32; +L_0x2b7e890 .part RS_0x7f507e9f00e8, 22, 1; +L_0x2b7ea10 .part/pv L_0x2b95cd0, 22, 1, 32; +L_0x2b7eab0 .part RS_0x7f507e9f0088, 22, 1; +L_0x2b7eba0 .part RS_0x7f507e9f0088, 22, 1; +L_0x2b97c20 .part/pv L_0x2b97790, 23, 1, 32; +L_0x2b97d10 .part/pv L_0x2b97ae0, 23, 1, 32; +L_0x2b96830 .part/pv L_0x2b974c0, 23, 1, 32; +L_0x2b96920 .part v0x295fe90_0, 23, 1; +L_0x2b969c0 .part v0x2960190_0, 23, 1; +L_0x2b96af0 .part RS_0x7f507e9f00b8, 22, 1; +L_0x2b96f20 .part/pv L_0x2b96de0, 23, 1, 32; +L_0x2b985d0 .part RS_0x7f507e9f00e8, 23, 1; +L_0x2b98290 .part/pv L_0x2b98150, 23, 1, 32; +L_0x2b98330 .part RS_0x7f507e9f0088, 23, 1; +L_0x2b98420 .part RS_0x7f507e9f0088, 23, 1; +L_0x2b99ce0 .part/pv L_0x2b99850, 24, 1, 32; +L_0x2b986c0 .part/pv L_0x2b99ba0, 24, 1, 32; +L_0x2b987b0 .part/pv L_0x2b99580, 24, 1, 32; +L_0x2b988a0 .part v0x295fe90_0, 24, 1; +L_0x2b98940 .part v0x2960190_0, 24, 1; +L_0x2b98a70 .part RS_0x7f507e9f00b8, 23, 1; +L_0x2b9a640 .part/pv L_0x2b98d60, 24, 1, 32; +L_0x2b99dd0 .part RS_0x7f507e9f00e8, 24, 1; +L_0x2b95780 .part/pv L_0x2b9a4c0, 24, 1, 32; +L_0x2b95820 .part RS_0x7f507e9f0088, 24, 1; +L_0x2b95910 .part RS_0x7f507e9f0088, 24, 1; +L_0x2b9bdd0 .part/pv L_0x2b9b940, 25, 1, 32; +L_0x2b9bec0 .part/pv L_0x2b9bc90, 25, 1, 32; +L_0x2b9a6e0 .part/pv L_0x2b9b670, 25, 1, 32; +L_0x2b9a7d0 .part v0x295fe90_0, 25, 1; +L_0x2b9a870 .part v0x2960190_0, 25, 1; +L_0x2b9a9a0 .part RS_0x7f507e9f00b8, 24, 1; +L_0x2b9adf0 .part/pv L_0x2b9ac90, 25, 1, 32; +L_0x2b9ae90 .part RS_0x7f507e9f00e8, 25, 1; +L_0x2b9c440 .part/pv L_0x2b9c300, 25, 1, 32; +L_0x2b9c4e0 .part RS_0x7f507e9f0088, 25, 1; +L_0x2b9c5d0 .part RS_0x7f507e9f0088, 25, 1; +L_0x2b9dec0 .part/pv L_0x2b9da30, 26, 1, 32; +L_0x2b9c880 .part/pv L_0x2b9dd80, 26, 1, 32; +L_0x2b9c970 .part/pv L_0x2b9d760, 26, 1, 32; +L_0x2b9ca60 .part v0x295fe90_0, 26, 1; +L_0x2b9cb00 .part v0x2960190_0, 26, 1; +L_0x2b9cc30 .part RS_0x7f507e9f00b8, 25, 1; +L_0x2b9e880 .part/pv L_0x2b9cf40, 26, 1, 32; +L_0x2b9dfb0 .part RS_0x7f507e9f00e8, 26, 1; +L_0x2b99f10 .part/pv L_0x2b9e6f0, 26, 1, 32; +L_0x2b99fb0 .part RS_0x7f507e9f0088, 26, 1; +L_0x2b9a050 .part RS_0x7f507e9f0088, 26, 1; +L_0x2ba0000 .part/pv L_0x2b9fb70, 27, 1, 32; +L_0x2ba00f0 .part/pv L_0x2b9fec0, 27, 1, 32; +L_0x2b9e920 .part/pv L_0x2b9f8a0, 27, 1, 32; +L_0x2b9ea10 .part v0x295fe90_0, 27, 1; +L_0x2b9eab0 .part v0x2960190_0, 27, 1; +L_0x2b9ebe0 .part RS_0x7f507e9f00b8, 26, 1; +L_0x2b9f050 .part/pv L_0x2b9eef0, 27, 1, 32; +L_0x2b9f0f0 .part RS_0x7f507e9f00e8, 27, 1; +L_0x2ba0f30 .part/pv L_0x2ba0df0, 27, 1, 32; +L_0x2ba0fd0 .part RS_0x7f507e9f0088, 27, 1; +L_0x2ba01e0 .part RS_0x7f507e9f0088, 27, 1; +L_0x2ba2210 .part/pv L_0x2ba1d80, 28, 1, 32; +L_0x2ba10c0 .part/pv L_0x2ba20d0, 28, 1, 32; +L_0x2ba11b0 .part/pv L_0x2ba1ab0, 28, 1, 32; +L_0x2ba12a0 .part v0x295fe90_0, 28, 1; +L_0x2ba1340 .part v0x2960190_0, 28, 1; +L_0x2ba1470 .part RS_0x7f507e9f00b8, 27, 1; +L_0x2ba18c0 .part/pv L_0x2ba1760, 28, 1, 32; +L_0x2ba1960 .part RS_0x7f507e9f00e8, 28, 1; +L_0x2ba3180 .part/pv L_0x2ba3080, 28, 1, 32; +L_0x2ba2300 .part RS_0x7f507e9f0088, 28, 1; +L_0x2ba23f0 .part RS_0x7f507e9f0088, 28, 1; +L_0x2ba4410 .part/pv L_0x2ba3f80, 29, 1, 32; +L_0x2ba4500 .part/pv L_0x2ba42d0, 29, 1, 32; +L_0x2ba3220 .part/pv L_0x2ba3cb0, 29, 1, 32; +L_0x2ba3310 .part v0x295fe90_0, 29, 1; +L_0x2ba33b0 .part v0x2960190_0, 29, 1; +L_0x2ba34e0 .part RS_0x7f507e9f00b8, 28, 1; +L_0x2ba3930 .part/pv L_0x2ba37d0, 29, 1, 32; +L_0x2ba39d0 .part RS_0x7f507e9f00e8, 29, 1; +L_0x2ba5340 .part/pv L_0x2ba5200, 29, 1, 32; +L_0x2ba53e0 .part RS_0x7f507e9f0088, 29, 1; +L_0x2ba45f0 .part RS_0x7f507e9f0088, 29, 1; +L_0x2ba65f0 .part/pv L_0x2ba6160, 30, 1, 32; +L_0x2ba54d0 .part/pv L_0x2ba64b0, 30, 1, 32; +L_0x2ba55c0 .part/pv L_0x2ba5ed0, 30, 1, 32; +L_0x2b82ed0 .part v0x295fe90_0, 30, 1; +L_0x2b82f70 .part v0x2960190_0, 30, 1; +L_0x2ba5b00 .part RS_0x7f507e9f00b8, 29, 1; +L_0x2ba7160 .part/pv L_0x2ba5df0, 30, 1, 32; +L_0x2ba66e0 .part RS_0x7f507e9f00e8, 30, 1; +L_0x2ba6f40 .part/pv L_0x2ba6e00, 30, 1, 32; +L_0x2ba6fe0 .part RS_0x7f507e9f0088, 30, 1; +L_0x2ba2d70 .part RS_0x7f507e9f0088, 30, 1; +L_0x2ba8950 .part/pv L_0x2ba84c0, 31, 1, 32; +L_0x2ba8a40 .part/pv L_0x2ba8810, 31, 1, 32; +L_0x2ba7200 .part/pv L_0x2ba81f0, 31, 1, 32; +L_0x2ba72f0 .part v0x295fe90_0, 31, 1; +L_0x2ba7390 .part v0x2960190_0, 31, 1; +L_0x2ba74c0 .part RS_0x7f507e9f00b8, 30, 1; +L_0x2ba7910 .part/pv L_0x2ba77d0, 31, 1, 32; +L_0x2ba79b0 .part RS_0x7f507e9f00e8, 31, 1; +L_0x2ba9860 .part/pv L_0x2ba9720, 31, 1, 32; +L_0x2ba9900 .part RS_0x7f507e9f0088, 31, 1; +L_0x2ba8b30 .part RS_0x7f507e9f0088, 31, 1; +L_0x2ba8d30 .part v0x2960210_0, 2, 1; +L_0x2ba8f10 .part v0x2960210_0, 0, 1; +L_0x2ba8fb0 .part v0x2960210_0, 1, 1; +L_0x2baaf50 .part/pv L_0x2baaac0, 0, 1, 32; +L_0x2bab040 .part/pv L_0x2baae10, 0, 1, 32; +L_0x2ba99f0 .part/pv L_0x2baa7f0, 0, 1, 32; +L_0x2ba9ae0 .part v0x295fe90_0, 0, 1; +L_0x2ba9b80 .part v0x2960190_0, 0, 1; +L_0x2ba9cb0 .part RS_0x7f507e9e4c28, 0, 1; +L_0x2baa120 .part/pv L_0x2ba9fc0, 0, 1, 32; +L_0x2baa1c0 .part RS_0x7f507e9f00e8, 0, 1; +L_0x2baa410 .part RS_0x7f507e9f00b8, 31, 1; +L_0x2babac0 .part RS_0x7f507e9f00b8, 30, 1; +L_0x2ba6970 .part RS_0x7f507e9f0088, 31, 1; +L_0x2b88880 .part RS_0x7f507e9f00e8, 31, 1; +L_0x2bad4c0 .part/pv L_0x2bad380, 0, 1, 32; +L_0x2b64fd0 .part RS_0x7f507e9f0088, 0, 1; +S_0x23f9f90 .scope module, "attempt2" "MiddleAddSubSLT" 3 326, 3 189, S_0x2753240; + .timescale -9 -12; +L_0x2ba90a0/d .functor NOT 1, L_0x2ba9b80, C4<0>, C4<0>, C4<0>; +L_0x2ba90a0 .delay (10000,10000,10000) L_0x2ba90a0/d; +L_0x2baa6b0/d .functor NOT 1, L_0x2baa750, C4<0>, C4<0>, C4<0>; +L_0x2baa6b0 .delay (10000,10000,10000) L_0x2baa6b0/d; +L_0x2baa7f0/d .functor AND 1, L_0x2baa930, L_0x2baa6b0, C4<1>, C4<1>; +L_0x2baa7f0 .delay (20000,20000,20000) L_0x2baa7f0/d; +L_0x2baa9d0/d .functor XOR 1, L_0x2ba9ae0, L_0x2baa4c0, C4<0>, C4<0>; +L_0x2baa9d0 .delay (40000,40000,40000) L_0x2baa9d0/d; +L_0x2baaac0/d .functor XOR 1, L_0x2baa9d0, L_0x2ba9cb0, C4<0>, C4<0>; +L_0x2baaac0 .delay (40000,40000,40000) L_0x2baaac0/d; +L_0x2baabb0/d .functor AND 1, L_0x2ba9ae0, L_0x2baa4c0, C4<1>, C4<1>; +L_0x2baabb0 .delay (20000,20000,20000) L_0x2baabb0/d; +L_0x2baad20/d .functor AND 1, L_0x2baa9d0, L_0x2ba9cb0, C4<1>, C4<1>; +L_0x2baad20 .delay (20000,20000,20000) L_0x2baad20/d; +L_0x2baae10/d .functor OR 1, L_0x2baabb0, L_0x2baad20, C4<0>, C4<0>; +L_0x2baae10 .delay (20000,20000,20000) L_0x2baae10/d; +v0x23fb500_0 .net "A", 0 0, L_0x2ba9ae0; 1 drivers +v0x23f7bf0_0 .net "AandB", 0 0, L_0x2baabb0; 1 drivers +v0x23f7c90_0 .net "AddSubSLTSum", 0 0, L_0x2baaac0; 1 drivers +v0x23f7950_0 .net "AxorB", 0 0, L_0x2baa9d0; 1 drivers +v0x23f79f0_0 .net "B", 0 0, L_0x2ba9b80; 1 drivers +v0x23ff800_0 .net "BornB", 0 0, L_0x2baa4c0; 1 drivers +v0x23ff8c0_0 .net "CINandAxorB", 0 0, L_0x2baad20; 1 drivers +v0x23fd770_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x23fd7f0_0 .net *"_s3", 0 0, L_0x2baa750; 1 drivers +v0x2405660_0 .net *"_s5", 0 0, L_0x2baa930; 1 drivers +v0x2405700_0 .net "carryin", 0 0, L_0x2ba9cb0; 1 drivers +v0x2403570_0 .net "carryout", 0 0, L_0x2baae10; 1 drivers +v0x2403610_0 .net "nB", 0 0, L_0x2ba90a0; 1 drivers +v0x240b4c0_0 .net "nCmd2", 0 0, L_0x2baa6b0; 1 drivers +v0x24093d0_0 .net "subtract", 0 0, L_0x2baa7f0; 1 drivers +L_0x2baa610 .part v0x2960210_0, 0, 1; +L_0x2baa750 .part v0x2960210_0, 2, 1; +L_0x2baa930 .part v0x2960210_0, 0, 1; +S_0x23f9ce0 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x23f9f90; + .timescale -9 -12; +L_0x2ba9270/d .functor NOT 1, L_0x2baa610, C4<0>, C4<0>, C4<0>; +L_0x2ba9270 .delay (10000,10000,10000) L_0x2ba9270/d; +L_0x2ba9350/d .functor AND 1, L_0x2ba9b80, L_0x2ba9270, C4<1>, C4<1>; +L_0x2ba9350 .delay (20000,20000,20000) L_0x2ba9350/d; +L_0x2ba9480/d .functor AND 1, L_0x2ba90a0, L_0x2baa610, C4<1>, C4<1>; +L_0x2ba9480 .delay (20000,20000,20000) L_0x2ba9480/d; +L_0x2baa4c0/d .functor OR 1, L_0x2ba9350, L_0x2ba9480, C4<0>, C4<0>; +L_0x2baa4c0 .delay (20000,20000,20000) L_0x2baa4c0/d; +v0x23fa2e0_0 .net "S", 0 0, L_0x2baa610; 1 drivers +v0x23f9a40_0 .alias "in0", 0 0, v0x23f79f0_0; +v0x23f9ae0_0 .alias "in1", 0 0, v0x2403610_0; +v0x23f8150_0 .net "nS", 0 0, L_0x2ba9270; 1 drivers +v0x23f81f0_0 .net "out0", 0 0, L_0x2ba9350; 1 drivers +v0x23f7ea0_0 .net "out1", 0 0, L_0x2ba9480; 1 drivers +v0x23fb460_0 .alias "outfinal", 0 0, v0x23ff800_0; +S_0x23f2080 .scope module, "setSLTresult" "TwoInMux" 3 327, 3 109, S_0x2753240; + .timescale -9 -12; +L_0x2ba9d50/d .functor NOT 1, L_0x2ba8dd0, C4<0>, C4<0>, C4<0>; +L_0x2ba9d50 .delay (10000,10000,10000) L_0x2ba9d50/d; +L_0x2ba9df0/d .functor AND 1, L_0x2baa1c0, L_0x2ba9d50, C4<1>, C4<1>; +L_0x2ba9df0 .delay (20000,20000,20000) L_0x2ba9df0/d; +L_0x2ba9f00/d .functor AND 1, C4<0>, L_0x2ba8dd0, C4<1>, C4<1>; +L_0x2ba9f00 .delay (20000,20000,20000) L_0x2ba9f00/d; +L_0x2ba9fc0/d .functor OR 1, L_0x2ba9df0, L_0x2ba9f00, C4<0>, C4<0>; +L_0x2ba9fc0 .delay (20000,20000,20000) L_0x2ba9fc0/d; +v0x23f5640_0 .alias "S", 0 0, v0x240f880_0; +v0x23f56e0_0 .net "in0", 0 0, L_0x2baa1c0; 1 drivers +v0x23f1dd0_0 .net "in1", 0 0, C4<0>; 1 drivers +v0x23f1e70_0 .net "nS", 0 0, L_0x2ba9d50; 1 drivers +v0x23f1b30_0 .net "out0", 0 0, L_0x2ba9df0; 1 drivers +v0x23f1bd0_0 .net "out1", 0 0, L_0x2ba9f00; 1 drivers +v0x23fa240_0 .net "outfinal", 0 0, L_0x2ba9fc0; 1 drivers +S_0x23f4170 .scope module, "FinalSLT" "TwoInMux" 3 354, 3 109, S_0x2753240; + .timescale -9 -12; +L_0x2bad150/d .functor NOT 1, L_0x2bad020, C4<0>, C4<0>, C4<0>; +L_0x2bad150 .delay (10000,10000,10000) L_0x2bad150/d; +L_0x2bad1f0/d .functor AND 1, L_0x2b64fd0, L_0x2bad150, C4<1>, C4<1>; +L_0x2bad1f0 .delay (20000,20000,20000) L_0x2bad1f0/d; +L_0x2bad2e0/d .functor AND 1, L_0x2bad020, L_0x2bad020, C4<1>, C4<1>; +L_0x2bad2e0 .delay (20000,20000,20000) L_0x2bad2e0/d; +L_0x2bad380/d .functor OR 1, L_0x2bad1f0, L_0x2bad2e0, C4<0>, C4<0>; +L_0x2bad380 .delay (20000,20000,20000) L_0x2bad380/d; +v0x23f44c0_0 .alias "S", 0 0, v0x2415130_0; +v0x23f3ec0_0 .net "in0", 0 0, L_0x2b64fd0; 1 drivers +v0x23f3f60_0 .alias "in1", 0 0, v0x2415130_0; +v0x23f3c20_0 .net "nS", 0 0, L_0x2bad150; 1 drivers +v0x23f3cc0_0 .net "out0", 0 0, L_0x2bad1f0; 1 drivers +v0x23f2330_0 .net "out1", 0 0, L_0x2bad2e0; 1 drivers +v0x23f23d0_0 .net "outfinal", 0 0, L_0x2bad380; 1 drivers +S_0x23d6ee0 .scope generate, "sltbits[1]" "sltbits[1]" 3 332, 3 332, S_0x2753240; + .timescale -9 -12; +P_0x26424b8 .param/l "i" 3 332, +C4<01>; +S_0x23dc530 .scope module, "attempt" "MiddleAddSubSLT" 3 334, 3 189, S_0x23d6ee0; + .timescale -9 -12; +L_0x2b64b10/d .functor NOT 1, L_0x2b67d90, C4<0>, C4<0>, C4<0>; +L_0x2b64b10 .delay (10000,10000,10000) L_0x2b64b10/d; +L_0x2b67180/d .functor NOT 1, L_0x2b67220, C4<0>, C4<0>, C4<0>; +L_0x2b67180 .delay (10000,10000,10000) L_0x2b67180/d; +L_0x2b672c0/d .functor AND 1, L_0x2b67400, L_0x2b67180, C4<1>, C4<1>; +L_0x2b672c0 .delay (20000,20000,20000) L_0x2b672c0/d; +L_0x2b674a0/d .functor XOR 1, L_0x2b67cf0, L_0x2b66f50, C4<0>, C4<0>; +L_0x2b674a0 .delay (40000,40000,40000) L_0x2b674a0/d; +L_0x2b67590/d .functor XOR 1, L_0x2b674a0, L_0x2b67ec0, C4<0>, C4<0>; +L_0x2b67590 .delay (40000,40000,40000) L_0x2b67590/d; +L_0x2b67680/d .functor AND 1, L_0x2b67cf0, L_0x2b66f50, C4<1>, C4<1>; +L_0x2b67680 .delay (20000,20000,20000) L_0x2b67680/d; +L_0x2b677f0/d .functor AND 1, L_0x2b674a0, L_0x2b67ec0, C4<1>, C4<1>; +L_0x2b677f0 .delay (20000,20000,20000) L_0x2b677f0/d; +L_0x2b678e0/d .functor OR 1, L_0x2b67680, L_0x2b677f0, C4<0>, C4<0>; +L_0x2b678e0 .delay (20000,20000,20000) L_0x2b678e0/d; +v0x23e2180_0 .net "A", 0 0, L_0x2b67cf0; 1 drivers +v0x23e7f40_0 .net "AandB", 0 0, L_0x2b67680; 1 drivers +v0x23e7fe0_0 .net "AddSubSLTSum", 0 0, L_0x2b67590; 1 drivers +v0x23e5e50_0 .net "AxorB", 0 0, L_0x2b674a0; 1 drivers +v0x23e5ef0_0 .net "B", 0 0, L_0x2b67d90; 1 drivers +v0x23ee600_0 .net "BornB", 0 0, L_0x2b66f50; 1 drivers +v0x23ee6c0_0 .net "CINandAxorB", 0 0, L_0x2b677f0; 1 drivers +v0x23ee350_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x23ee3d0_0 .net *"_s3", 0 0, L_0x2b67220; 1 drivers +v0x23ee0a0_0 .net *"_s5", 0 0, L_0x2b67400; 1 drivers +v0x23ee140_0 .net "carryin", 0 0, L_0x2b67ec0; 1 drivers +v0x23ef820_0 .net "carryout", 0 0, L_0x2b678e0; 1 drivers +v0x23ef8c0_0 .net "nB", 0 0, L_0x2b64b10; 1 drivers +v0x23ebcb0_0 .net "nCmd2", 0 0, L_0x2b67180; 1 drivers +v0x23f4420_0 .net "subtract", 0 0, L_0x2b672c0; 1 drivers +L_0x2b670e0 .part v0x2960210_0, 0, 1; +L_0x2b67220 .part v0x2960210_0, 2, 1; +L_0x2b67400 .part v0x2960210_0, 0, 1; +S_0x23dace0 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x23dc530; + .timescale -9 -12; +L_0x2b64ca0/d .functor NOT 1, L_0x2b670e0, C4<0>, C4<0>, C4<0>; +L_0x2b64ca0 .delay (10000,10000,10000) L_0x2b64ca0/d; +L_0x2b64d40/d .functor AND 1, L_0x2b67d90, L_0x2b64ca0, C4<1>, C4<1>; +L_0x2b64d40 .delay (20000,20000,20000) L_0x2b64d40/d; +L_0x2b64e30/d .functor AND 1, L_0x2b64b10, L_0x2b670e0, C4<1>, C4<1>; +L_0x2b64e30 .delay (20000,20000,20000) L_0x2b64e30/d; +L_0x2b66f50/d .functor OR 1, L_0x2b64d40, L_0x2b64e30, C4<0>, C4<0>; +L_0x2b66f50 .delay (20000,20000,20000) L_0x2b66f50/d; +v0x23dc850_0 .net "S", 0 0, L_0x2b670e0; 1 drivers +v0x23daa50_0 .alias "in0", 0 0, v0x23e5ef0_0; +v0x23daaf0_0 .alias "in1", 0 0, v0x23ef8c0_0; +v0x23da7c0_0 .net "nS", 0 0, L_0x2b64ca0; 1 drivers +v0x23da860_0 .net "out0", 0 0, L_0x2b64d40; 1 drivers +v0x23da540_0 .net "out1", 0 0, L_0x2b64e30; 1 drivers +v0x23e20e0_0 .alias "outfinal", 0 0, v0x23ee600_0; +S_0x23d4c60 .scope module, "setSLTres2" "TwoInMux" 3 335, 3 109, S_0x23d6ee0; + .timescale -9 -12; +L_0x2b67f60/d .functor NOT 1, L_0x2ba8dd0, C4<0>, C4<0>, C4<0>; +L_0x2b67f60 .delay (10000,10000,10000) L_0x2b67f60/d; +L_0x21be350/d .functor AND 1, L_0x2b687d0, L_0x2b67f60, C4<1>, C4<1>; +L_0x21be350 .delay (20000,20000,20000) L_0x21be350/d; +L_0x21be440/d .functor AND 1, C4<0>, L_0x2ba8dd0, C4<1>, C4<1>; +L_0x21be440 .delay (20000,20000,20000) L_0x21be440/d; +L_0x21be4e0/d .functor OR 1, L_0x21be350, L_0x21be440, C4<0>, C4<0>; +L_0x21be4e0 .delay (20000,20000,20000) L_0x21be4e0/d; +v0x23d83b0_0 .alias "S", 0 0, v0x240f880_0; +v0x23d49e0_0 .net "in0", 0 0, L_0x2b687d0; 1 drivers +v0x23d4a80_0 .net "in1", 0 0, C4<0>; 1 drivers +v0x23dccd0_0 .net "nS", 0 0, L_0x2b67f60; 1 drivers +v0x23dcd70_0 .net "out0", 0 0, L_0x21be350; 1 drivers +v0x23dca40_0 .net "out1", 0 0, L_0x21be440; 1 drivers +v0x23dc7b0_0 .net "outfinal", 0 0, L_0x21be4e0; 1 drivers +S_0x23d6c50 .scope module, "setSLTres3" "TwoInMux" 3 336, 3 109, S_0x23d6ee0; + .timescale -9 -12; +L_0x2b689b0/d .functor NOT 1, L_0x2ba8dd0, C4<0>, C4<0>, C4<0>; +L_0x2b689b0 .delay (10000,10000,10000) L_0x2b689b0/d; +L_0x2b68aa0/d .functor AND 1, L_0x2b68e10, L_0x2b689b0, C4<1>, C4<1>; +L_0x2b68aa0 .delay (20000,20000,20000) L_0x2b68aa0/d; +L_0x2b68b90/d .functor AND 1, L_0x2b68fb0, L_0x2ba8dd0, C4<1>, C4<1>; +L_0x2b68b90 .delay (20000,20000,20000) L_0x2b68b90/d; +L_0x2b68c30/d .functor OR 1, L_0x2b68aa0, L_0x2b68b90, C4<0>, C4<0>; +L_0x2b68c30 .delay (20000,20000,20000) L_0x2b68c30/d; +v0x23d7210_0 .alias "S", 0 0, v0x240f880_0; +v0x23d69d0_0 .net "in0", 0 0, L_0x2b68e10; 1 drivers +v0x23d6a70_0 .net "in1", 0 0, L_0x2b68fb0; 1 drivers +v0x23d5180_0 .net "nS", 0 0, L_0x2b689b0; 1 drivers +v0x23d5220_0 .net "out0", 0 0, L_0x2b68aa0; 1 drivers +v0x23d4ef0_0 .net "out1", 0 0, L_0x2b68b90; 1 drivers +v0x23d8310_0 .net "outfinal", 0 0, L_0x2b68c30; 1 drivers +S_0x23b4310 .scope generate, "sltbits[2]" "sltbits[2]" 3 332, 3 332, S_0x2753240; + .timescale -9 -12; +P_0x26a59e8 .param/l "i" 3 332, +C4<010>; +S_0x23b8390 .scope module, "attempt" "MiddleAddSubSLT" 3 334, 3 189, S_0x23b4310; + .timescale -9 -12; +L_0x2b69050/d .functor NOT 1, L_0x2b6a3d0, C4<0>, C4<0>, C4<0>; +L_0x2b69050 .delay (10000,10000,10000) L_0x2b69050/d; +L_0x2b69690/d .functor NOT 1, L_0x2b69730, C4<0>, C4<0>, C4<0>; +L_0x2b69690 .delay (10000,10000,10000) L_0x2b69690/d; +L_0x2b697d0/d .functor AND 1, L_0x2b69910, L_0x2b69690, C4<1>, C4<1>; +L_0x2b697d0 .delay (20000,20000,20000) L_0x2b697d0/d; +L_0x2b699b0/d .functor XOR 1, L_0x2b6a330, L_0x2b69460, C4<0>, C4<0>; +L_0x2b699b0 .delay (40000,40000,40000) L_0x2b699b0/d; +L_0x2b69aa0/d .functor XOR 1, L_0x2b699b0, L_0x2b6a590, C4<0>, C4<0>; +L_0x2b69aa0 .delay (40000,40000,40000) L_0x2b69aa0/d; +L_0x2b69b90/d .functor AND 1, L_0x2b6a330, L_0x2b69460, C4<1>, C4<1>; +L_0x2b69b90 .delay (20000,20000,20000) L_0x2b69b90/d; +L_0x2b69d00/d .functor AND 1, L_0x2b699b0, L_0x2b6a590, C4<1>, C4<1>; +L_0x2b69d00 .delay (20000,20000,20000) L_0x2b69d00/d; +L_0x2b69df0/d .functor OR 1, L_0x2b69b90, L_0x2b69d00, C4<0>, C4<0>; +L_0x2b69df0 .delay (20000,20000,20000) L_0x2b69df0/d; +v0x23d1420_0 .net "A", 0 0, L_0x2b6a330; 1 drivers +v0x23d10f0_0 .net "AandB", 0 0, L_0x2b69b90; 1 drivers +v0x23d1190_0 .net "AddSubSLTSum", 0 0, L_0x2b69aa0; 1 drivers +v0x23d0e70_0 .net "AxorB", 0 0, L_0x2b699b0; 1 drivers +v0x23d0f10_0 .net "B", 0 0, L_0x2b6a3d0; 1 drivers +v0x23cf620_0 .net "BornB", 0 0, L_0x2b69460; 1 drivers +v0x23cf6e0_0 .net "CINandAxorB", 0 0, L_0x2b69d00; 1 drivers +v0x23cf390_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x23cf410_0 .net *"_s3", 0 0, L_0x2b69730; 1 drivers +v0x23d27b0_0 .net *"_s5", 0 0, L_0x2b69910; 1 drivers +v0x23d2850_0 .net "carryin", 0 0, L_0x2b6a590; 1 drivers +v0x23cf100_0 .net "carryout", 0 0, L_0x2b69df0; 1 drivers +v0x23cf1a0_0 .net "nB", 0 0, L_0x2b69050; 1 drivers +v0x23cee80_0 .net "nCmd2", 0 0, L_0x2b69690; 1 drivers +v0x23d7170_0 .net "subtract", 0 0, L_0x2b697d0; 1 drivers +L_0x2b695f0 .part v0x2960210_0, 0, 1; +L_0x2b69730 .part v0x2960210_0, 2, 1; +L_0x2b69910 .part v0x2960210_0, 0, 1; +S_0x23bb7b0 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x23b8390; + .timescale -9 -12; +L_0x2b691e0/d .functor NOT 1, L_0x2b695f0, C4<0>, C4<0>, C4<0>; +L_0x2b691e0 .delay (10000,10000,10000) L_0x2b691e0/d; +L_0x2b69280/d .functor AND 1, L_0x2b6a3d0, L_0x2b691e0, C4<1>, C4<1>; +L_0x2b69280 .delay (20000,20000,20000) L_0x2b69280/d; +L_0x2b69370/d .functor AND 1, L_0x2b69050, L_0x2b695f0, C4<1>, C4<1>; +L_0x2b69370 .delay (20000,20000,20000) L_0x2b69370/d; +L_0x2b69460/d .functor OR 1, L_0x2b69280, L_0x2b69370, C4<0>, C4<0>; +L_0x2b69460 .delay (20000,20000,20000) L_0x2b69460/d; +v0x23b86c0_0 .net "S", 0 0, L_0x2b695f0; 1 drivers +v0x23b8100_0 .alias "in0", 0 0, v0x23d0f10_0; +v0x23b81a0_0 .alias "in1", 0 0, v0x23cf1a0_0; +v0x23b7e80_0 .net "nS", 0 0, L_0x2b691e0; 1 drivers +v0x23b7f20_0 .net "out0", 0 0, L_0x2b69280; 1 drivers +v0x23d1610_0 .net "out1", 0 0, L_0x2b69370; 1 drivers +v0x23d1380_0 .alias "outfinal", 0 0, v0x23cf620_0; +S_0x23ba610 .scope module, "setSLTres2" "TwoInMux" 3 335, 3 109, S_0x23b4310; + .timescale -9 -12; +L_0x2b68f50/d .functor NOT 1, L_0x2ba8dd0, C4<0>, C4<0>, C4<0>; +L_0x2b68f50 .delay (10000,10000,10000) L_0x2b68f50/d; +L_0x2b6a6c0/d .functor AND 1, L_0x2b6ab10, L_0x2b68f50, C4<1>, C4<1>; +L_0x2b6a6c0 .delay (20000,20000,20000) L_0x2b6a6c0/d; +L_0x2b6a760/d .functor AND 1, C4<0>, L_0x2ba8dd0, C4<1>, C4<1>; +L_0x2b6a760 .delay (20000,20000,20000) L_0x2b6a760/d; +L_0x2b6a800/d .functor OR 1, L_0x2b6a6c0, L_0x2b6a760, C4<0>, C4<0>; +L_0x2b6a800 .delay (20000,20000,20000) L_0x2b6a800/d; +v0x23b23c0_0 .alias "S", 0 0, v0x240f880_0; +v0x23ba380_0 .net "in0", 0 0, L_0x2b6ab10; 1 drivers +v0x23ba420_0 .net "in1", 0 0, C4<0>; 1 drivers +v0x23ba0f0_0 .net "nS", 0 0, L_0x2b68f50; 1 drivers +v0x23ba190_0 .net "out0", 0 0, L_0x2b6a6c0; 1 drivers +v0x23b9e70_0 .net "out1", 0 0, L_0x2b6a760; 1 drivers +v0x23b8620_0 .net "outfinal", 0 0, L_0x2b6a800; 1 drivers +S_0x23b2ac0 .scope module, "setSLTres3" "TwoInMux" 3 336, 3 109, S_0x23b4310; + .timescale -9 -12; +L_0x2abcc70/d .functor NOT 1, L_0x2ba8dd0, C4<0>, C4<0>, C4<0>; +L_0x2abcc70 .delay (10000,10000,10000) L_0x2abcc70/d; +L_0x2abcd60/d .functor AND 1, L_0x2b6aa70, L_0x2abcc70, C4<1>, C4<1>; +L_0x2abcd60 .delay (20000,20000,20000) L_0x2abcd60/d; +L_0x2b6ae30/d .functor AND 1, L_0x2b6b170, L_0x2ba8dd0, C4<1>, C4<1>; +L_0x2b6ae30 .delay (20000,20000,20000) L_0x2b6ae30/d; +L_0x2b6ae90/d .functor OR 1, L_0x2abcd60, L_0x2b6ae30, C4<0>, C4<0>; +L_0x2b6ae90 .delay (20000,20000,20000) L_0x2b6ae90/d; +v0x23b4630_0 .alias "S", 0 0, v0x240f880_0; +v0x23b2830_0 .net "in0", 0 0, L_0x2b6aa70; 1 drivers +v0x23b28d0_0 .net "in1", 0 0, L_0x2b6b170; 1 drivers +v0x23b5c50_0 .net "nS", 0 0, L_0x2abcc70; 1 drivers +v0x23b5cf0_0 .net "out0", 0 0, L_0x2abcd60; 1 drivers +v0x23b25a0_0 .net "out1", 0 0, L_0x2b6ae30; 1 drivers +v0x23b2320_0 .net "outfinal", 0 0, L_0x2b6ae90; 1 drivers +S_0x238fc40 .scope generate, "sltbits[3]" "sltbits[3]" 3 332, 3 332, S_0x2753240; + .timescale -9 -12; +P_0x2391f38 .param/l "i" 3 332, +C4<011>; +S_0x239d570 .scope module, "attempt" "MiddleAddSubSLT" 3 334, 3 189, S_0x238fc40; + .timescale -9 -12; +L_0x2b6b070/d .functor NOT 1, L_0x2b6c330, C4<0>, C4<0>, C4<0>; +L_0x2b6b070 .delay (10000,10000,10000) L_0x2b6b070/d; +L_0x2b6b8b0/d .functor NOT 1, L_0x2b6b950, C4<0>, C4<0>, C4<0>; +L_0x2b6b8b0 .delay (10000,10000,10000) L_0x2b6b8b0/d; +L_0x2b6b9f0/d .functor AND 1, L_0x2b6bb30, L_0x2b6b8b0, C4<1>, C4<1>; +L_0x2b6b9f0 .delay (20000,20000,20000) L_0x2b6b9f0/d; +L_0x2b6bbd0/d .functor XOR 1, L_0x2b6c450, L_0x2b6b680, C4<0>, C4<0>; +L_0x2b6bbd0 .delay (40000,40000,40000) L_0x2b6bbd0/d; +L_0x2b6bcc0/d .functor XOR 1, L_0x2b6bbd0, L_0x2b6c660, C4<0>, C4<0>; +L_0x2b6bcc0 .delay (40000,40000,40000) L_0x2b6bcc0/d; +L_0x2b6bdb0/d .functor AND 1, L_0x2b6c450, L_0x2b6b680, C4<1>, C4<1>; +L_0x2b6bdb0 .delay (20000,20000,20000) L_0x2b6bdb0/d; +L_0x2b6bf20/d .functor AND 1, L_0x2b6bbd0, L_0x2b6c660, C4<1>, C4<1>; +L_0x2b6bf20 .delay (20000,20000,20000) L_0x2b6bf20/d; +L_0x2b6c010/d .functor OR 1, L_0x2b6bdb0, L_0x2b6bf20, C4<0>, C4<0>; +L_0x2b6c010 .delay (20000,20000,20000) L_0x2b6c010/d; +v0x239b3a0_0 .net "A", 0 0, L_0x2b6c450; 1 drivers +v0x23aef50_0 .net "AandB", 0 0, L_0x2b6bdb0; 1 drivers +v0x23aeff0_0 .net "AddSubSLTSum", 0 0, L_0x2b6bcc0; 1 drivers +v0x23aecc0_0 .net "AxorB", 0 0, L_0x2b6bbd0; 1 drivers +v0x23aed60_0 .net "B", 0 0, L_0x2b6c330; 1 drivers +v0x23aea30_0 .net "BornB", 0 0, L_0x2b6b680; 1 drivers +v0x23aeab0_0 .net "CINandAxorB", 0 0, L_0x2b6bf20; 1 drivers +v0x23ae7b0_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x23ae830_0 .net *"_s3", 0 0, L_0x2b6b950; 1 drivers +v0x23b00f0_0 .net *"_s5", 0 0, L_0x2b6bb30; 1 drivers +v0x23b0190_0 .net "carryin", 0 0, L_0x2b6c660; 1 drivers +v0x23b4ab0_0 .net "carryout", 0 0, L_0x2b6c010; 1 drivers +v0x23b4b50_0 .net "nB", 0 0, L_0x2b6b070; 1 drivers +v0x23b4820_0 .net "nCmd2", 0 0, L_0x2b6b8b0; 1 drivers +v0x23b4590_0 .net "subtract", 0 0, L_0x2b6b9f0; 1 drivers +L_0x2b6b810 .part v0x2960210_0, 0, 1; +L_0x2b6b950 .part v0x2960210_0, 2, 1; +L_0x2b6bb30 .part v0x2960210_0, 0, 1; +S_0x239d2f0 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x239d570; + .timescale -9 -12; +L_0x2b6b400/d .functor NOT 1, L_0x2b6b810, C4<0>, C4<0>, C4<0>; +L_0x2b6b400 .delay (10000,10000,10000) L_0x2b6b400/d; +L_0x2b6b4a0/d .functor AND 1, L_0x2b6c330, L_0x2b6b400, C4<1>, C4<1>; +L_0x2b6b4a0 .delay (20000,20000,20000) L_0x2b6b4a0/d; +L_0x2b6b590/d .functor AND 1, L_0x2b6b070, L_0x2b6b810, C4<1>, C4<1>; +L_0x2b6b590 .delay (20000,20000,20000) L_0x2b6b590/d; +L_0x2b6b680/d .functor OR 1, L_0x2b6b4a0, L_0x2b6b590, C4<0>, C4<0>; +L_0x2b6b680 .delay (20000,20000,20000) L_0x2b6b680/d; +v0x239d8a0_0 .net "S", 0 0, L_0x2b6b810; 1 drivers +v0x239baa0_0 .alias "in0", 0 0, v0x23aed60_0; +v0x239bb40_0 .alias "in1", 0 0, v0x23b4b50_0; +v0x239b810_0 .net "nS", 0 0, L_0x2b6b400; 1 drivers +v0x239b8b0_0 .net "out0", 0 0, L_0x2b6b4a0; 1 drivers +v0x239b580_0 .net "out1", 0 0, L_0x2b6b590; 1 drivers +v0x239b300_0 .alias "outfinal", 0 0, v0x23aea30_0; +S_0x2395cb0 .scope module, "setSLTres2" "TwoInMux" 3 335, 3 109, S_0x238fc40; + .timescale -9 -12; +L_0x2b6c4f0/d .functor NOT 1, L_0x2ba8dd0, C4<0>, C4<0>, C4<0>; +L_0x2b6c4f0 .delay (10000,10000,10000) L_0x2b6c4f0/d; +L_0x2b6c550/d .functor AND 1, L_0x2b6cb00, L_0x2b6c4f0, C4<1>, C4<1>; +L_0x2b6c550 .delay (20000,20000,20000) L_0x2b6c550/d; +L_0x2b6c880/d .functor AND 1, C4<0>, L_0x2ba8dd0, C4<1>, C4<1>; +L_0x2b6c880 .delay (20000,20000,20000) L_0x2b6c880/d; +L_0x2b6c920/d .functor OR 1, L_0x2b6c550, L_0x2b6c880, C4<0>, C4<0>; +L_0x2b6c920 .delay (20000,20000,20000) L_0x2b6c920/d; +v0x2395fe0_0 .alias "S", 0 0, v0x240f880_0; +v0x23990d0_0 .net "in0", 0 0, L_0x2b6cb00; 1 drivers +v0x2399170_0 .net "in1", 0 0, C4<0>; 1 drivers +v0x2395a20_0 .net "nS", 0 0, L_0x2b6c4f0; 1 drivers +v0x2395ac0_0 .net "out0", 0 0, L_0x2b6c550; 1 drivers +v0x23957a0_0 .net "out1", 0 0, L_0x2b6c880; 1 drivers +v0x239d800_0 .net "outfinal", 0 0, L_0x2b6c920; 1 drivers +S_0x2397f30 .scope module, "setSLTres3" "TwoInMux" 3 336, 3 109, S_0x238fc40; + .timescale -9 -12; +L_0x2b6c790/d .functor NOT 1, L_0x2ba8dd0, C4<0>, C4<0>, C4<0>; +L_0x2b6c790 .delay (10000,10000,10000) L_0x2b6c790/d; +L_0x2b6cd80/d .functor AND 1, L_0x2b6d0f0, L_0x2b6c790, C4<1>, C4<1>; +L_0x2b6cd80 .delay (20000,20000,20000) L_0x2b6cd80/d; +L_0x2b6ce70/d .functor AND 1, L_0x2b6cbf0, L_0x2ba8dd0, C4<1>, C4<1>; +L_0x2b6ce70 .delay (20000,20000,20000) L_0x2b6ce70/d; +L_0x2b6cf10/d .functor OR 1, L_0x2b6cd80, L_0x2b6ce70, C4<0>, C4<0>; +L_0x2b6cf10 .delay (20000,20000,20000) L_0x2b6cf10/d; +v0x238ff60_0 .alias "S", 0 0, v0x240f880_0; +v0x2397ca0_0 .net "in0", 0 0, L_0x2b6d0f0; 1 drivers +v0x2397d40_0 .net "in1", 0 0, L_0x2b6cbf0; 1 drivers +v0x2397a10_0 .net "nS", 0 0, L_0x2b6c790; 1 drivers +v0x2397ab0_0 .net "out0", 0 0, L_0x2b6cd80; 1 drivers +v0x2397790_0 .net "out1", 0 0, L_0x2b6ce70; 1 drivers +v0x2395f40_0 .net "outfinal", 0 0, L_0x2b6cf10; 1 drivers +S_0x2375580 .scope generate, "sltbits[4]" "sltbits[4]" 3 332, 3 332, S_0x2753240; + .timescale -9 -12; +P_0x236dd48 .param/l "i" 3 332, +C4<0100>; +S_0x237abd0 .scope module, "attempt" "MiddleAddSubSLT" 3 334, 3 189, S_0x2375580; + .timescale -9 -12; +L_0x2b6a9e0/d .functor NOT 1, L_0x2b6e6b0, C4<0>, C4<0>, C4<0>; +L_0x2b6a9e0 .delay (10000,10000,10000) L_0x2b6a9e0/d; +L_0x2b6d9e0/d .functor NOT 1, L_0x2b6da80, C4<0>, C4<0>, C4<0>; +L_0x2b6d9e0 .delay (10000,10000,10000) L_0x2b6d9e0/d; +L_0x2b6db20/d .functor AND 1, L_0x2b6dc60, L_0x2b6d9e0, C4<1>, C4<1>; +L_0x2b6db20 .delay (20000,20000,20000) L_0x2b6db20/d; +L_0x2b6dd00/d .functor XOR 1, L_0x2b6e370, L_0x2b6d7b0, C4<0>, C4<0>; +L_0x2b6dd00 .delay (40000,40000,40000) L_0x2b6dd00/d; +L_0x2b6ddf0/d .functor XOR 1, L_0x2b6dd00, L_0x2b6e580, C4<0>, C4<0>; +L_0x2b6ddf0 .delay (40000,40000,40000) L_0x2b6ddf0/d; +L_0x2b6dee0/d .functor AND 1, L_0x2b6e370, L_0x2b6d7b0, C4<1>, C4<1>; +L_0x2b6dee0 .delay (20000,20000,20000) L_0x2b6dee0/d; +L_0x2b6e050/d .functor AND 1, L_0x2b6dd00, L_0x2b6e580, C4<1>, C4<1>; +L_0x2b6e050 .delay (20000,20000,20000) L_0x2b6e050/d; +L_0x2b6e140/d .functor OR 1, L_0x2b6dee0, L_0x2b6e050, C4<0>, C4<0>; +L_0x2b6e140 .delay (20000,20000,20000) L_0x2b6e140/d; +v0x2378c80_0 .net "A", 0 0, L_0x2b6e370; 1 drivers +v0x23923d0_0 .net "AandB", 0 0, L_0x2b6dee0; 1 drivers +v0x2392470_0 .net "AddSubSLTSum", 0 0, L_0x2b6ddf0; 1 drivers +v0x2392140_0 .net "AxorB", 0 0, L_0x2b6dd00; 1 drivers +v0x23921e0_0 .net "B", 0 0, L_0x2b6e6b0; 1 drivers +v0x2391eb0_0 .net "BornB", 0 0, L_0x2b6d7b0; 1 drivers +v0x2391f70_0 .net "CINandAxorB", 0 0, L_0x2b6e050; 1 drivers +v0x2391c30_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x2391cb0_0 .net *"_s3", 0 0, L_0x2b6da80; 1 drivers +v0x23903e0_0 .net *"_s5", 0 0, L_0x2b6dc60; 1 drivers +v0x2390480_0 .net "carryin", 0 0, L_0x2b6e580; 1 drivers +v0x2390150_0 .net "carryout", 0 0, L_0x2b6e140; 1 drivers +v0x23901f0_0 .net "nB", 0 0, L_0x2b6a9e0; 1 drivers +v0x2393570_0 .net "nCmd2", 0 0, L_0x2b6d9e0; 1 drivers +v0x238fec0_0 .net "subtract", 0 0, L_0x2b6db20; 1 drivers +L_0x2b6d940 .part v0x2960210_0, 0, 1; +L_0x2b6da80 .part v0x2960210_0, 2, 1; +L_0x2b6dc60 .part v0x2960210_0, 0, 1; +S_0x2379380 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x237abd0; + .timescale -9 -12; +L_0x2b6d530/d .functor NOT 1, L_0x2b6d940, C4<0>, C4<0>, C4<0>; +L_0x2b6d530 .delay (10000,10000,10000) L_0x2b6d530/d; +L_0x2b6d5d0/d .functor AND 1, L_0x2b6e6b0, L_0x2b6d530, C4<1>, C4<1>; +L_0x2b6d5d0 .delay (20000,20000,20000) L_0x2b6d5d0/d; +L_0x2b6d6c0/d .functor AND 1, L_0x2b6a9e0, L_0x2b6d940, C4<1>, C4<1>; +L_0x2b6d6c0 .delay (20000,20000,20000) L_0x2b6d6c0/d; +L_0x2b6d7b0/d .functor OR 1, L_0x2b6d5d0, L_0x2b6d6c0, C4<0>, C4<0>; +L_0x2b6d7b0 .delay (20000,20000,20000) L_0x2b6d7b0/d; +v0x237aef0_0 .net "S", 0 0, L_0x2b6d940; 1 drivers +v0x23790f0_0 .alias "in0", 0 0, v0x23921e0_0; +v0x2379190_0 .alias "in1", 0 0, v0x23901f0_0; +v0x237c510_0 .net "nS", 0 0, L_0x2b6d530; 1 drivers +v0x237c5b0_0 .net "out0", 0 0, L_0x2b6d5d0; 1 drivers +v0x2378e60_0 .net "out1", 0 0, L_0x2b6d6c0; 1 drivers +v0x2378be0_0 .alias "outfinal", 0 0, v0x2391eb0_0; +S_0x2373300 .scope module, "setSLTres2" "TwoInMux" 3 335, 3 109, S_0x2375580; + .timescale -9 -12; +L_0x2b6e410/d .functor NOT 1, L_0x2ba8dd0, C4<0>, C4<0>, C4<0>; +L_0x2b6e410 .delay (10000,10000,10000) L_0x2b6e410/d; +L_0x2b6e620/d .functor AND 1, L_0x2b6e7e0, L_0x2b6e410, C4<1>, C4<1>; +L_0x2b6e620 .delay (20000,20000,20000) L_0x2b6e620/d; +L_0x2b6ea30/d .functor AND 1, C4<0>, L_0x2ba8dd0, C4<1>, C4<1>; +L_0x2b6ea30 .delay (20000,20000,20000) L_0x2b6ea30/d; +L_0x2b6ead0/d .functor OR 1, L_0x2b6e620, L_0x2b6ea30, C4<0>, C4<0>; +L_0x2b6ead0 .delay (20000,20000,20000) L_0x2b6ead0/d; +v0x2376a50_0 .alias "S", 0 0, v0x240f880_0; +v0x2373080_0 .net "in0", 0 0, L_0x2b6e7e0; 1 drivers +v0x2373120_0 .net "in1", 0 0, C4<0>; 1 drivers +v0x237b370_0 .net "nS", 0 0, L_0x2b6e410; 1 drivers +v0x237b410_0 .net "out0", 0 0, L_0x2b6e620; 1 drivers +v0x237b0e0_0 .net "out1", 0 0, L_0x2b6ea30; 1 drivers +v0x237ae50_0 .net "outfinal", 0 0, L_0x2b6ead0; 1 drivers +S_0x23752f0 .scope module, "setSLTres3" "TwoInMux" 3 336, 3 109, S_0x2375580; + .timescale -9 -12; +L_0x2b6abf0/d .functor NOT 1, L_0x2ba8dd0, C4<0>, C4<0>, C4<0>; +L_0x2b6abf0 .delay (10000,10000,10000) L_0x2b6abf0/d; +L_0x2b6aca0/d .functor AND 1, L_0x2b6ecb0, L_0x2b6abf0, C4<1>, C4<1>; +L_0x2b6aca0 .delay (20000,20000,20000) L_0x2b6aca0/d; +L_0x2b6ad90/d .functor AND 1, L_0x2b6f4a0, L_0x2ba8dd0, C4<1>, C4<1>; +L_0x2b6ad90 .delay (20000,20000,20000) L_0x2b6ad90/d; +L_0x2b6f160/d .functor OR 1, L_0x2b6aca0, L_0x2b6ad90, C4<0>, C4<0>; +L_0x2b6f160 .delay (20000,20000,20000) L_0x2b6f160/d; +v0x23758b0_0 .alias "S", 0 0, v0x240f880_0; +v0x2375070_0 .net "in0", 0 0, L_0x2b6ecb0; 1 drivers +v0x2375110_0 .net "in1", 0 0, L_0x2b6f4a0; 1 drivers +v0x2373820_0 .net "nS", 0 0, L_0x2b6abf0; 1 drivers +v0x23738c0_0 .net "out0", 0 0, L_0x2b6aca0; 1 drivers +v0x2373590_0 .net "out1", 0 0, L_0x2b6ad90; 1 drivers +v0x23769b0_0 .net "outfinal", 0 0, L_0x2b6f160; 1 drivers +S_0x24b9f10 .scope generate, "sltbits[5]" "sltbits[5]" 3 332, 3 332, S_0x2753240; + .timescale -9 -12; +P_0x27b6c88 .param/l "i" 3 332, +C4<0101>; +S_0x24dc710 .scope module, "attempt" "MiddleAddSubSLT" 3 334, 3 189, S_0x24b9f10; + .timescale -9 -12; +L_0x2b6f340/d .functor NOT 1, L_0x2b70630, C4<0>, C4<0>, C4<0>; +L_0x2b6f340 .delay (10000,10000,10000) L_0x2b6f340/d; +L_0x2b6fbb0/d .functor NOT 1, L_0x2b6fc50, C4<0>, C4<0>, C4<0>; +L_0x2b6fbb0 .delay (10000,10000,10000) L_0x2b6fbb0/d; +L_0x2b6fcf0/d .functor AND 1, L_0x2b6fe30, L_0x2b6fbb0, C4<1>, C4<1>; +L_0x2b6fcf0 .delay (20000,20000,20000) L_0x2b6fcf0/d; +L_0x2b6fed0/d .functor XOR 1, L_0x2b707b0, L_0x2b6f980, C4<0>, C4<0>; +L_0x2b6fed0 .delay (40000,40000,40000) L_0x2b6fed0/d; +L_0x2b6ffc0/d .functor XOR 1, L_0x2b6fed0, L_0x2b709e0, C4<0>, C4<0>; +L_0x2b6ffc0 .delay (40000,40000,40000) L_0x2b6ffc0/d; +L_0x2b700b0/d .functor AND 1, L_0x2b707b0, L_0x2b6f980, C4<1>, C4<1>; +L_0x2b700b0 .delay (20000,20000,20000) L_0x2b700b0/d; +L_0x2b70220/d .functor AND 1, L_0x2b6fed0, L_0x2b709e0, C4<1>, C4<1>; +L_0x2b70220 .delay (20000,20000,20000) L_0x2b70220/d; +L_0x2b70310/d .functor OR 1, L_0x2b700b0, L_0x2b70220, C4<0>, C4<0>; +L_0x2b70310 .delay (20000,20000,20000) L_0x2b70310/d; +v0x236fac0_0 .net "A", 0 0, L_0x2b707b0; 1 drivers +v0x236f790_0 .net "AandB", 0 0, L_0x2b700b0; 1 drivers +v0x236f830_0 .net "AddSubSLTSum", 0 0, L_0x2b6ffc0; 1 drivers +v0x236f510_0 .net "AxorB", 0 0, L_0x2b6fed0; 1 drivers +v0x236f5b0_0 .net "B", 0 0, L_0x2b70630; 1 drivers +v0x236dcc0_0 .net "BornB", 0 0, L_0x2b6f980; 1 drivers +v0x236dd80_0 .net "CINandAxorB", 0 0, L_0x2b70220; 1 drivers +v0x236da30_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x236dab0_0 .net *"_s3", 0 0, L_0x2b6fc50; 1 drivers +v0x2370e50_0 .net *"_s5", 0 0, L_0x2b6fe30; 1 drivers +v0x2370ef0_0 .net "carryin", 0 0, L_0x2b709e0; 1 drivers +v0x236d7a0_0 .net "carryout", 0 0, L_0x2b70310; 1 drivers +v0x236d840_0 .net "nB", 0 0, L_0x2b6f340; 1 drivers +v0x236d520_0 .net "nCmd2", 0 0, L_0x2b6fbb0; 1 drivers +v0x2375810_0 .net "subtract", 0 0, L_0x2b6fcf0; 1 drivers +L_0x2b6fb10 .part v0x2960210_0, 0, 1; +L_0x2b6fc50 .part v0x2960210_0, 2, 1; +L_0x2b6fe30 .part v0x2960210_0, 0, 1; +S_0x24d98d0 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x24dc710; + .timescale -9 -12; +L_0x2b6f700/d .functor NOT 1, L_0x2b6fb10, C4<0>, C4<0>, C4<0>; +L_0x2b6f700 .delay (10000,10000,10000) L_0x2b6f700/d; +L_0x2b6f7a0/d .functor AND 1, L_0x2b70630, L_0x2b6f700, C4<1>, C4<1>; +L_0x2b6f7a0 .delay (20000,20000,20000) L_0x2b6f7a0/d; +L_0x2b6f890/d .functor AND 1, L_0x2b6f340, L_0x2b6fb10, C4<1>, C4<1>; +L_0x2b6f890 .delay (20000,20000,20000) L_0x2b6f890/d; +L_0x2b6f980/d .functor OR 1, L_0x2b6f7a0, L_0x2b6f890, C4<0>, C4<0>; +L_0x2b6f980 .delay (20000,20000,20000) L_0x2b6f980/d; +v0x24df5f0_0 .net "S", 0 0, L_0x2b6fb10; 1 drivers +v0x24b7db0_0 .alias "in0", 0 0, v0x236f5b0_0; +v0x24b7e50_0 .alias "in1", 0 0, v0x236d840_0; +v0x25130c0_0 .net "nS", 0 0, L_0x2b6f700; 1 drivers +v0x2513160_0 .net "out0", 0 0, L_0x2b6f7a0; 1 drivers +v0x236fcb0_0 .net "out1", 0 0, L_0x2b6f890; 1 drivers +v0x236fa20_0 .alias "outfinal", 0 0, v0x236dcc0_0; +S_0x24f63b0 .scope module, "setSLTres2" "TwoInMux" 3 335, 3 109, S_0x24b9f10; + .timescale -9 -12; +L_0x2b6f630/d .functor NOT 1, L_0x2ba8dd0, C4<0>, C4<0>, C4<0>; +L_0x2b6f630 .delay (10000,10000,10000) L_0x2b6f630/d; +L_0x2b70850/d .functor AND 1, L_0x2b70db0, L_0x2b6f630, C4<1>, C4<1>; +L_0x2b70850 .delay (20000,20000,20000) L_0x2b70850/d; +L_0x2b708f0/d .functor AND 1, C4<0>, L_0x2ba8dd0, C4<1>, C4<1>; +L_0x2b708f0 .delay (20000,20000,20000) L_0x2b708f0/d; +L_0x2b70c20/d .functor OR 1, L_0x2b70850, L_0x2b708f0, C4<0>, C4<0>; +L_0x2b70c20 .delay (20000,20000,20000) L_0x2b70c20/d; +v0x24f9290_0 .alias "S", 0 0, v0x240f880_0; +v0x24f3570_0 .net "in0", 0 0, L_0x2b70db0; 1 drivers +v0x24f3610_0 .net "in1", 0 0, C4<0>; 1 drivers +v0x24f0750_0 .net "nS", 0 0, L_0x2b6f630; 1 drivers +v0x24f07f0_0 .net "out0", 0 0, L_0x2b70850; 1 drivers +v0x24bcd50_0 .net "out1", 0 0, L_0x2b708f0; 1 drivers +v0x24df550_0 .net "outfinal", 0 0, L_0x2b70c20; 1 drivers +S_0x24d0e10 .scope module, "setSLTres3" "TwoInMux" 3 336, 3 109, S_0x24b9f10; + .timescale -9 -12; +L_0x2b70b10/d .functor NOT 1, L_0x2ba8dd0, C4<0>, C4<0>, C4<0>; +L_0x2b70b10 .delay (10000,10000,10000) L_0x2b70b10/d; +L_0x2b71050/d .functor AND 1, L_0x2b713c0, L_0x2b70b10, C4<1>, C4<1>; +L_0x2b71050 .delay (20000,20000,20000) L_0x2b71050/d; +L_0x2b71140/d .functor AND 1, L_0x2b70ea0, L_0x2ba8dd0, C4<1>, C4<1>; +L_0x2b71140 .delay (20000,20000,20000) L_0x2b71140/d; +L_0x2b711e0/d .functor OR 1, L_0x2b71050, L_0x2b71140, C4<0>, C4<0>; +L_0x2b711e0 .delay (20000,20000,20000) L_0x2b711e0/d; +v0x24d3cf0_0 .alias "S", 0 0, v0x240f880_0; +v0x2510110_0 .net "in0", 0 0, L_0x2b713c0; 1 drivers +v0x25101b0_0 .net "in1", 0 0, L_0x2b70ea0; 1 drivers +v0x24fee70_0 .net "nS", 0 0, L_0x2b70b10; 1 drivers +v0x24fef10_0 .net "out0", 0 0, L_0x2b71050; 1 drivers +v0x24fc030_0 .net "out1", 0 0, L_0x2b71140; 1 drivers +v0x24f91f0_0 .net "outfinal", 0 0, L_0x2b711e0; 1 drivers +S_0x248bf20 .scope generate, "sltbits[6]" "sltbits[6]" 3 332, 3 332, S_0x2753240; + .timescale -9 -12; +P_0x24a89d8 .param/l "i" 3 332, +C4<0110>; +S_0x2460f30 .scope module, "attempt" "MiddleAddSubSLT" 3 334, 3 189, S_0x248bf20; + .timescale -9 -12; +L_0x2b70f90/d .functor NOT 1, L_0x2b72630, C4<0>, C4<0>, C4<0>; +L_0x2b70f90 .delay (10000,10000,10000) L_0x2b70f90/d; +L_0x2b71c00/d .functor NOT 1, L_0x2b71ca0, C4<0>, C4<0>, C4<0>; +L_0x2b71c00 .delay (10000,10000,10000) L_0x2b71c00/d; +L_0x2b71d40/d .functor AND 1, L_0x2b71e80, L_0x2b71c00, C4<1>, C4<1>; +L_0x2b71d40 .delay (20000,20000,20000) L_0x2b71d40/d; +L_0x2b71f20/d .functor XOR 1, L_0x2b72590, L_0x2b719d0, C4<0>, C4<0>; +L_0x2b71f20 .delay (40000,40000,40000) L_0x2b71f20/d; +L_0x2b72010/d .functor XOR 1, L_0x2b71f20, L_0x2b72a60, C4<0>, C4<0>; +L_0x2b72010 .delay (40000,40000,40000) L_0x2b72010/d; +L_0x2b72100/d .functor AND 1, L_0x2b72590, L_0x2b719d0, C4<1>, C4<1>; +L_0x2b72100 .delay (20000,20000,20000) L_0x2b72100/d; +L_0x2b72270/d .functor AND 1, L_0x2b71f20, L_0x2b72a60, C4<1>, C4<1>; +L_0x2b72270 .delay (20000,20000,20000) L_0x2b72270/d; +L_0x2b72360/d .functor OR 1, L_0x2b72100, L_0x2b72270, C4<0>, C4<0>; +L_0x2b72360 .delay (20000,20000,20000) L_0x2b72360/d; +v0x24504c0_0 .net "A", 0 0, L_0x2b72590; 1 drivers +v0x2449100_0 .net "AandB", 0 0, L_0x2b72100; 1 drivers +v0x24491a0_0 .net "AddSubSLTSum", 0 0, L_0x2b72010; 1 drivers +v0x2444490_0 .net "AxorB", 0 0, L_0x2b71f20; 1 drivers +v0x2444530_0 .net "B", 0 0, L_0x2b72630; 1 drivers +v0x243f820_0 .net "BornB", 0 0, L_0x2b719d0; 1 drivers +v0x243f8a0_0 .net "CINandAxorB", 0 0, L_0x2b72270; 1 drivers +v0x243d370_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x243d3f0_0 .net *"_s3", 0 0, L_0x2b71ca0; 1 drivers +v0x241e6d0_0 .net *"_s5", 0 0, L_0x2b71e80; 1 drivers +v0x241e770_0 .net "carryin", 0 0, L_0x2b72a60; 1 drivers +v0x241c810_0 .net "carryout", 0 0, L_0x2b72360; 1 drivers +v0x241c8b0_0 .net "nB", 0 0, L_0x2b70f90; 1 drivers +v0x24d6a90_0 .net "nCmd2", 0 0, L_0x2b71c00; 1 drivers +v0x24d3c50_0 .net "subtract", 0 0, L_0x2b71d40; 1 drivers +L_0x2b71b60 .part v0x2960210_0, 0, 1; +L_0x2b71ca0 .part v0x2960210_0, 2, 1; +L_0x2b71e80 .part v0x2960210_0, 0, 1; +S_0x245ee90 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x2460f30; + .timescale -9 -12; +L_0x2b71750/d .functor NOT 1, L_0x2b71b60, C4<0>, C4<0>, C4<0>; +L_0x2b71750 .delay (10000,10000,10000) L_0x2b71750/d; +L_0x2b717f0/d .functor AND 1, L_0x2b72630, L_0x2b71750, C4<1>, C4<1>; +L_0x2b717f0 .delay (20000,20000,20000) L_0x2b717f0/d; +L_0x2b718e0/d .functor AND 1, L_0x2b70f90, L_0x2b71b60, C4<1>, C4<1>; +L_0x2b718e0 .delay (20000,20000,20000) L_0x2b718e0/d; +L_0x2b719d0/d .functor OR 1, L_0x2b717f0, L_0x2b718e0, C4<0>, C4<0>; +L_0x2b719d0 .delay (20000,20000,20000) L_0x2b719d0/d; +v0x2465c40_0 .net "S", 0 0, L_0x2b71b60; 1 drivers +v0x245e940_0 .alias "in0", 0 0, v0x2444530_0; +v0x245e9e0_0 .alias "in1", 0 0, v0x241c8b0_0; +v0x2459d80_0 .net "nS", 0 0, L_0x2b71750; 1 drivers +v0x2459e20_0 .net "out0", 0 0, L_0x2b717f0; 1 drivers +v0x24550d0_0 .net "out1", 0 0, L_0x2b718e0; 1 drivers +v0x2450420_0 .alias "outfinal", 0 0, v0x243f820_0; +S_0x24767e0 .scope module, "setSLTres2" "TwoInMux" 3 335, 3 109, S_0x248bf20; + .timescale -9 -12; +L_0x2b72b00/d .functor NOT 1, L_0x2ba8dd0, C4<0>, C4<0>, C4<0>; +L_0x2b72b00 .delay (10000,10000,10000) L_0x2b72b00/d; +L_0x2b72b60/d .functor AND 1, L_0x2b6d1e0, L_0x2b72b00, C4<1>, C4<1>; +L_0x2b72b60 .delay (20000,20000,20000) L_0x2b72b60/d; +L_0x2b72c50/d .functor AND 1, C4<0>, L_0x2ba8dd0, C4<1>, C4<1>; +L_0x2b72c50 .delay (20000,20000,20000) L_0x2b72c50/d; +L_0x2b72cf0/d .functor OR 1, L_0x2b72b60, L_0x2b72c50, C4<0>, C4<0>; +L_0x2b72cf0 .delay (20000,20000,20000) L_0x2b72cf0/d; +v0x247b530_0 .alias "S", 0 0, v0x240f880_0; +v0x2471b30_0 .net "in0", 0 0, L_0x2b6d1e0; 1 drivers +v0x2471bd0_0 .net "in1", 0 0, C4<0>; 1 drivers +v0x2422de0_0 .net "nS", 0 0, L_0x2b72b00; 1 drivers +v0x2422e80_0 .net "out0", 0 0, L_0x2b72b60; 1 drivers +v0x246a810_0 .net "out1", 0 0, L_0x2b72c50; 1 drivers +v0x2465ba0_0 .net "outfinal", 0 0, L_0x2b72cf0; 1 drivers +S_0x24872b0 .scope module, "setSLTres3" "TwoInMux" 3 336, 3 109, S_0x248bf20; + .timescale -9 -12; +L_0x2b72900/d .functor NOT 1, L_0x2ba8dd0, C4<0>, C4<0>, C4<0>; +L_0x2b72900 .delay (10000,10000,10000) L_0x2b72900/d; +L_0x2b6ef10/d .functor AND 1, L_0x2b73100, L_0x2b72900, C4<1>, C4<1>; +L_0x2b6ef10 .delay (20000,20000,20000) L_0x2b6ef10/d; +L_0x2b6efd0/d .functor AND 1, L_0x2b731f0, L_0x2ba8dd0, C4<1>, C4<1>; +L_0x2b6efd0 .delay (20000,20000,20000) L_0x2b6efd0/d; +L_0x2b6f090/d .functor OR 1, L_0x2b6ef10, L_0x2b6efd0, C4<0>, C4<0>; +L_0x2b6f090 .delay (20000,20000,20000) L_0x2b6f090/d; +v0x24932c0_0 .alias "S", 0 0, v0x240f880_0; +v0x2482640_0 .net "in0", 0 0, L_0x2b73100; 1 drivers +v0x24826e0_0 .net "in1", 0 0, L_0x2b731f0; 1 drivers +v0x24805a0_0 .net "nS", 0 0, L_0x2b72900; 1 drivers +v0x2480640_0 .net "out0", 0 0, L_0x2b6ef10; 1 drivers +v0x2480050_0 .net "out1", 0 0, L_0x2b6efd0; 1 drivers +v0x247b490_0 .net "outfinal", 0 0, L_0x2b6f090; 1 drivers +S_0x23bf470 .scope generate, "sltbits[7]" "sltbits[7]" 3 332, 3 332, S_0x2753240; + .timescale -9 -12; +P_0x23e1c08 .param/l "i" 3 332, +C4<0111>; +S_0x237e1f0 .scope module, "attempt" "MiddleAddSubSLT" 3 334, 3 189, S_0x23bf470; + .timescale -9 -12; +L_0x2b738b0/d .functor NOT 1, L_0x2b74d50, C4<0>, C4<0>, C4<0>; +L_0x2b738b0 .delay (10000,10000,10000) L_0x2b738b0/d; +L_0x2b73ff0/d .functor NOT 1, L_0x2b740b0, C4<0>, C4<0>, C4<0>; +L_0x2b73ff0 .delay (10000,10000,10000) L_0x2b73ff0/d; +L_0x2b74150/d .functor AND 1, L_0x2b74290, L_0x2b73ff0, C4<1>, C4<1>; +L_0x2b74150 .delay (20000,20000,20000) L_0x2b74150/d; +L_0x2b74330/d .functor XOR 1, L_0x2b73780, L_0x2b73d80, C4<0>, C4<0>; +L_0x2b74330 .delay (40000,40000,40000) L_0x2b74330/d; +L_0x2b74420/d .functor XOR 1, L_0x2b74330, L_0x2b74df0, C4<0>, C4<0>; +L_0x2b74420 .delay (40000,40000,40000) L_0x2b74420/d; +L_0x2b74530/d .functor AND 1, L_0x2b73780, L_0x2b73d80, C4<1>, C4<1>; +L_0x2b74530 .delay (20000,20000,20000) L_0x2b74530/d; +L_0x2b746c0/d .functor AND 1, L_0x2b74330, L_0x2b74df0, C4<1>, C4<1>; +L_0x2b746c0 .delay (20000,20000,20000) L_0x2b746c0/d; +L_0x2b747d0/d .functor OR 1, L_0x2b74530, L_0x2b746c0, C4<0>, C4<0>; +L_0x2b747d0 .delay (20000,20000,20000) L_0x2b747d0/d; +v0x242c760_0 .net "A", 0 0, L_0x2b73780; 1 drivers +v0x24b0840_0 .net "AandB", 0 0, L_0x2b74530; 1 drivers +v0x24b08e0_0 .net "AddSubSLTSum", 0 0, L_0x2b74420; 1 drivers +v0x24ad5c0_0 .net "AxorB", 0 0, L_0x2b74330; 1 drivers +v0x24ad660_0 .net "B", 0 0, L_0x2b74d50; 1 drivers +v0x24a8950_0 .net "BornB", 0 0, L_0x2b73d80; 1 drivers +v0x24a8a10_0 .net "CINandAxorB", 0 0, L_0x2b746c0; 1 drivers +v0x24a3ce0_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x24a3d60_0 .net *"_s3", 0 0, L_0x2b740b0; 1 drivers +v0x2427a50_0 .net *"_s5", 0 0, L_0x2b74290; 1 drivers +v0x2427af0_0 .net "carryin", 0 0, L_0x2b74df0; 1 drivers +v0x249cb80_0 .net "carryout", 0 0, L_0x2b747d0; 1 drivers +v0x249cc20_0 .net "nB", 0 0, L_0x2b738b0; 1 drivers +v0x2497ed0_0 .net "nCmd2", 0 0, L_0x2b73ff0; 1 drivers +v0x2493220_0 .net "subtract", 0 0, L_0x2b74150; 1 drivers +L_0x2b73f50 .part v0x2960210_0, 0, 1; +L_0x2b740b0 .part v0x2960210_0, 2, 1; +L_0x2b74290 .part v0x2960210_0, 0, 1; +S_0x2367140 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x237e1f0; + .timescale -9 -12; +L_0x2b73a60/d .functor NOT 1, L_0x2b73f50, C4<0>, C4<0>, C4<0>; +L_0x2b73a60 .delay (10000,10000,10000) L_0x2b73a60/d; +L_0x2b73b40/d .functor AND 1, L_0x2b74d50, L_0x2b73a60, C4<1>, C4<1>; +L_0x2b73b40 .delay (20000,20000,20000) L_0x2b73b40/d; +L_0x2b73c70/d .functor AND 1, L_0x2b738b0, L_0x2b73f50, C4<1>, C4<1>; +L_0x2b73c70 .delay (20000,20000,20000) L_0x2b73c70/d; +L_0x2b73d80/d .functor OR 1, L_0x2b73b40, L_0x2b73c70, C4<0>, C4<0>; +L_0x2b73d80 .delay (20000,20000,20000) L_0x2b73d80/d; +v0x23802d0_0 .net "S", 0 0, L_0x2b73f50; 1 drivers +v0x24386c0_0 .alias "in0", 0 0, v0x24ad660_0; +v0x2438760_0 .alias "in1", 0 0, v0x249cc20_0; +v0x2433a10_0 .net "nS", 0 0, L_0x2b73a60; 1 drivers +v0x2433ab0_0 .net "out0", 0 0, L_0x2b73b40; 1 drivers +v0x242ed60_0 .net "out1", 0 0, L_0x2b73c70; 1 drivers +v0x242c6c0_0 .alias "outfinal", 0 0, v0x24a8950_0; +S_0x238bad0 .scope module, "setSLTres2" "TwoInMux" 3 335, 3 109, S_0x23bf470; + .timescale -9 -12; +L_0x2b74b10/d .functor NOT 1, L_0x2ba8dd0, C4<0>, C4<0>, C4<0>; +L_0x2b74b10 .delay (10000,10000,10000) L_0x2b74b10/d; +L_0x2b74bb0/d .functor AND 1, L_0x2b75320, L_0x2b74b10, C4<1>, C4<1>; +L_0x2b74bb0 .delay (20000,20000,20000) L_0x2b74bb0/d; +L_0x2b74cc0/d .functor AND 1, C4<0>, L_0x2ba8dd0, C4<1>, C4<1>; +L_0x2b74cc0 .delay (20000,20000,20000) L_0x2b74cc0/d; +L_0x2b75120/d .functor OR 1, L_0x2b74bb0, L_0x2b74cc0, C4<0>, C4<0>; +L_0x2b75120 .delay (20000,20000,20000) L_0x2b75120/d; +v0x23a09f0_0 .alias "S", 0 0, v0x240f880_0; +v0x2389a90_0 .net "in0", 0 0, L_0x2b75320; 1 drivers +v0x2389b30_0 .net "in1", 0 0, C4<0>; 1 drivers +v0x2385e80_0 .net "nS", 0 0, L_0x2b74b10; 1 drivers +v0x2385f20_0 .net "out0", 0 0, L_0x2b74bb0; 1 drivers +v0x2383e40_0 .net "out1", 0 0, L_0x2b74cc0; 1 drivers +v0x2380230_0 .net "outfinal", 0 0, L_0x2b75120; 1 drivers +S_0x23ac1f0 .scope module, "setSLTres3" "TwoInMux" 3 336, 3 109, S_0x23bf470; + .timescale -9 -12; +L_0x2b74f20/d .functor NOT 1, L_0x2ba8dd0, C4<0>, C4<0>, C4<0>; +L_0x2b74f20 .delay (10000,10000,10000) L_0x2b74f20/d; +L_0x2b75030/d .functor AND 1, L_0x2b759a0, L_0x2b74f20, C4<1>, C4<1>; +L_0x2b75030 .delay (20000,20000,20000) L_0x2b75030/d; +L_0x2b75700/d .functor AND 1, L_0x2b75410, L_0x2ba8dd0, C4<1>, C4<1>; +L_0x2b75700 .delay (20000,20000,20000) L_0x2b75700/d; +L_0x2b757a0/d .functor OR 1, L_0x2b75030, L_0x2b75700, C4<0>, C4<0>; +L_0x2b757a0 .delay (20000,20000,20000) L_0x2b757a0/d; +v0x23c3120_0 .alias "S", 0 0, v0x240f880_0; +v0x23a85e0_0 .net "in0", 0 0, L_0x2b759a0; 1 drivers +v0x23a8680_0 .net "in1", 0 0, L_0x2b75410; 1 drivers +v0x23a65a0_0 .net "nS", 0 0, L_0x2b74f20; 1 drivers +v0x23a6640_0 .net "out0", 0 0, L_0x2b75030; 1 drivers +v0x23a2990_0 .net "out1", 0 0, L_0x2b75700; 1 drivers +v0x23a0950_0 .net "outfinal", 0 0, L_0x2b757a0; 1 drivers +S_0x258ad10 .scope generate, "sltbits[8]" "sltbits[8]" 3 332, 3 332, S_0x2753240; + .timescale -9 -12; +P_0x240c368 .param/l "i" 3 332, +C4<01000>; +S_0x2408e90 .scope module, "attempt" "MiddleAddSubSLT" 3 334, 3 189, S_0x258ad10; + .timescale -9 -12; +L_0x2b75500/d .functor NOT 1, L_0x2b77040, C4<0>, C4<0>, C4<0>; +L_0x2b75500 .delay (10000,10000,10000) L_0x2b75500/d; +L_0x2b76300/d .functor NOT 1, L_0x2b763c0, C4<0>, C4<0>, C4<0>; +L_0x2b76300 .delay (10000,10000,10000) L_0x2b76300/d; +L_0x2b76460/d .functor AND 1, L_0x2b765a0, L_0x2b76300, C4<1>, C4<1>; +L_0x2b76460 .delay (20000,20000,20000) L_0x2b76460/d; +L_0x2b76640/d .functor XOR 1, L_0x2b76fa0, L_0x2b76090, C4<0>, C4<0>; +L_0x2b76640 .delay (40000,40000,40000) L_0x2b76640/d; +L_0x2b76730/d .functor XOR 1, L_0x2b76640, L_0x2b76d10, C4<0>, C4<0>; +L_0x2b76730 .delay (40000,40000,40000) L_0x2b76730/d; +L_0x2b76820/d .functor AND 1, L_0x2b76fa0, L_0x2b76090, C4<1>, C4<1>; +L_0x2b76820 .delay (20000,20000,20000) L_0x2b76820/d; +L_0x2b769b0/d .functor AND 1, L_0x2b76640, L_0x2b76d10, C4<1>, C4<1>; +L_0x2b769b0 .delay (20000,20000,20000) L_0x2b769b0/d; +L_0x2b76ac0/d .functor OR 1, L_0x2b76820, L_0x2b769b0, C4<0>, C4<0>; +L_0x2b76ac0 .delay (20000,20000,20000) L_0x2b76ac0/d; +v0x23eb810_0 .net "A", 0 0, L_0x2b76fa0; 1 drivers +v0x23e79e0_0 .net "AandB", 0 0, L_0x2b76820; 1 drivers +v0x23e7a80_0 .net "AddSubSLTSum", 0 0, L_0x2b76730; 1 drivers +v0x23e5910_0 .net "AxorB", 0 0, L_0x2b76640; 1 drivers +v0x23e59b0_0 .net "B", 0 0, L_0x2b77040; 1 drivers +v0x23e1b80_0 .net "BornB", 0 0, L_0x2b76090; 1 drivers +v0x23e1c40_0 .net "CINandAxorB", 0 0, L_0x2b769b0; 1 drivers +v0x23dfb40_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x23dfbc0_0 .net *"_s3", 0 0, L_0x2b763c0; 1 drivers +v0x23cad10_0 .net *"_s5", 0 0, L_0x2b765a0; 1 drivers +v0x23cadb0_0 .net "carryin", 0 0, L_0x2b76d10; 1 drivers +v0x23c8cd0_0 .net "carryout", 0 0, L_0x2b76ac0; 1 drivers +v0x23c8d70_0 .net "nB", 0 0, L_0x2b75500; 1 drivers +v0x23c50c0_0 .net "nCmd2", 0 0, L_0x2b76300; 1 drivers +v0x23c3080_0 .net "subtract", 0 0, L_0x2b76460; 1 drivers +L_0x2b76260 .part v0x2960210_0, 0, 1; +L_0x2b763c0 .part v0x2960210_0, 2, 1; +L_0x2b765a0 .part v0x2960210_0, 0, 1; +S_0x2405100 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x2408e90; + .timescale -9 -12; +L_0x2b75d70/d .functor NOT 1, L_0x2b76260, C4<0>, C4<0>, C4<0>; +L_0x2b75d70 .delay (10000,10000,10000) L_0x2b75d70/d; +L_0x2b75e50/d .functor AND 1, L_0x2b77040, L_0x2b75d70, C4<1>, C4<1>; +L_0x2b75e50 .delay (20000,20000,20000) L_0x2b75e50/d; +L_0x2b75f80/d .functor AND 1, L_0x2b75500, L_0x2b76260, C4<1>, C4<1>; +L_0x2b75f80 .delay (20000,20000,20000) L_0x2b75f80/d; +L_0x2b76090/d .functor OR 1, L_0x2b75e50, L_0x2b75f80, C4<0>, C4<0>; +L_0x2b76090 .delay (20000,20000,20000) L_0x2b76090/d; +v0x240b000_0 .net "S", 0 0, L_0x2b76260; 1 drivers +v0x2403030_0 .alias "in0", 0 0, v0x23e59b0_0; +v0x24030d0_0 .alias "in1", 0 0, v0x23c8d70_0; +v0x23ff2a0_0 .net "nS", 0 0, L_0x2b75d70; 1 drivers +v0x23ff340_0 .net "out0", 0 0, L_0x2b75e50; 1 drivers +v0x23ed840_0 .net "out1", 0 0, L_0x2b75f80; 1 drivers +v0x23eb770_0 .alias "outfinal", 0 0, v0x23e1b80_0; +S_0x2588c50 .scope module, "setSLTres2" "TwoInMux" 3 335, 3 109, S_0x258ad10; + .timescale -9 -12; +L_0x2b6e920/d .functor NOT 1, L_0x2ba8dd0, C4<0>, C4<0>, C4<0>; +L_0x2b6e920 .delay (10000,10000,10000) L_0x2b6e920/d; +L_0x2b6e9c0/d .functor AND 1, L_0x2b770e0, L_0x2b6e920, C4<1>, C4<1>; +L_0x2b6e9c0 .delay (20000,20000,20000) L_0x2b6e9c0/d; +L_0x2b76e60/d .functor AND 1, C4<0>, L_0x2ba8dd0, C4<1>, C4<1>; +L_0x2b76e60 .delay (20000,20000,20000) L_0x2b76e60/d; +L_0x2b76f20/d .functor OR 1, L_0x2b6e9c0, L_0x2b76e60, C4<0>, C4<0>; +L_0x2b76f20 .delay (20000,20000,20000) L_0x2b76f20/d; +v0x2588f90_0 .alias "S", 0 0, v0x240f880_0; +v0x25889b0_0 .net "in0", 0 0, L_0x2b770e0; 1 drivers +v0x2588a50_0 .net "in1", 0 0, C4<0>; 1 drivers +v0x25886b0_0 .net "nS", 0 0, L_0x2b6e920; 1 drivers +v0x2588750_0 .net "out0", 0 0, L_0x2b6e9c0; 1 drivers +v0x2588130_0 .net "out1", 0 0, L_0x2b76e60; 1 drivers +v0x240af60_0 .net "outfinal", 0 0, L_0x2b76f20; 1 drivers +S_0x258aa70 .scope module, "setSLTres3" "TwoInMux" 3 336, 3 109, S_0x258ad10; + .timescale -9 -12; +L_0x2b6ee90/d .functor NOT 1, L_0x2ba8dd0, C4<0>, C4<0>, C4<0>; +L_0x2b6ee90 .delay (10000,10000,10000) L_0x2b6ee90/d; +L_0x2b77260/d .functor AND 1, L_0x2b77710, L_0x2b6ee90, C4<1>, C4<1>; +L_0x2b77260 .delay (20000,20000,20000) L_0x2b77260/d; +L_0x2b77320/d .functor AND 1, L_0x2b777b0, L_0x2ba8dd0, C4<1>, C4<1>; +L_0x2b77320 .delay (20000,20000,20000) L_0x2b77320/d; +L_0x2b733b0/d .functor OR 1, L_0x2b77260, L_0x2b77320, C4<0>, C4<0>; +L_0x2b733b0 .delay (20000,20000,20000) L_0x2b733b0/d; +v0x258b050_0 .alias "S", 0 0, v0x240f880_0; +v0x258a770_0 .net "in0", 0 0, L_0x2b77710; 1 drivers +v0x258a810_0 .net "in1", 0 0, L_0x2b777b0; 1 drivers +v0x258a1f0_0 .net "nS", 0 0, L_0x2b6ee90; 1 drivers +v0x258a290_0 .net "out0", 0 0, L_0x2b77260; 1 drivers +v0x2589190_0 .net "out1", 0 0, L_0x2b77320; 1 drivers +v0x2588ef0_0 .net "outfinal", 0 0, L_0x2b733b0; 1 drivers +S_0x2294e40 .scope generate, "sltbits[9]" "sltbits[9]" 3 332, 3 332, S_0x2753240; + .timescale -9 -12; +P_0x2299de8 .param/l "i" 3 332, +C4<01001>; +S_0x22823d0 .scope module, "attempt" "MiddleAddSubSLT" 3 334, 3 189, S_0x2294e40; + .timescale -9 -12; +L_0x2b778a0/d .functor NOT 1, L_0x2b78070, C4<0>, C4<0>, C4<0>; +L_0x2b778a0 .delay (10000,10000,10000) L_0x2b778a0/d; +L_0x2b787f0/d .functor NOT 1, L_0x2b788b0, C4<0>, C4<0>, C4<0>; +L_0x2b787f0 .delay (10000,10000,10000) L_0x2b787f0/d; +L_0x2b78950/d .functor AND 1, L_0x2b78a90, L_0x2b787f0, C4<1>, C4<1>; +L_0x2b78950 .delay (20000,20000,20000) L_0x2b78950/d; +L_0x2b78b30/d .functor XOR 1, L_0x2b77fd0, L_0x2b78580, C4<0>, C4<0>; +L_0x2b78b30 .delay (40000,40000,40000) L_0x2b78b30/d; +L_0x2b78c20/d .functor XOR 1, L_0x2b78b30, L_0x2b795e0, C4<0>, C4<0>; +L_0x2b78c20 .delay (40000,40000,40000) L_0x2b78c20/d; +L_0x2b78d10/d .functor AND 1, L_0x2b77fd0, L_0x2b78580, C4<1>, C4<1>; +L_0x2b78d10 .delay (20000,20000,20000) L_0x2b78d10/d; +L_0x2b78ea0/d .functor AND 1, L_0x2b78b30, L_0x2b795e0, C4<1>, C4<1>; +L_0x2b78ea0 .delay (20000,20000,20000) L_0x2b78ea0/d; +L_0x2b78fb0/d .functor OR 1, L_0x2b78d10, L_0x2b78ea0, C4<0>, C4<0>; +L_0x2b78fb0 .delay (20000,20000,20000) L_0x2b78fb0/d; +v0x2279330_0 .net "A", 0 0, L_0x2b77fd0; 1 drivers +v0x225cbe0_0 .net "AandB", 0 0, L_0x2b78d10; 1 drivers +v0x225cc80_0 .net "AddSubSLTSum", 0 0, L_0x2b78c20; 1 drivers +v0x225db80_0 .net "AxorB", 0 0, L_0x2b78b30; 1 drivers +v0x225dc20_0 .net "B", 0 0, L_0x2b78070; 1 drivers +v0x22f4150_0 .net "BornB", 0 0, L_0x2b78580; 1 drivers +v0x22f41d0_0 .net "CINandAxorB", 0 0, L_0x2b78ea0; 1 drivers +v0x258c460_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x258c4e0_0 .net *"_s3", 0 0, L_0x2b788b0; 1 drivers +v0x258c1c0_0 .net *"_s5", 0 0, L_0x2b78a90; 1 drivers +v0x258c260_0 .net "carryin", 0 0, L_0x2b795e0; 1 drivers +v0x258b250_0 .net "carryout", 0 0, L_0x2b78fb0; 1 drivers +v0x258b2f0_0 .net "nB", 0 0, L_0x2b778a0; 1 drivers +v0x2369280_0 .net "nCmd2", 0 0, L_0x2b787f0; 1 drivers +v0x258afb0_0 .net "subtract", 0 0, L_0x2b78950; 1 drivers +L_0x2b78750 .part v0x2960210_0, 0, 1; +L_0x2b788b0 .part v0x2960210_0, 2, 1; +L_0x2b78a90 .part v0x2960210_0, 0, 1; +S_0x225f2b0 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x22823d0; + .timescale -9 -12; +L_0x2b78260/d .functor NOT 1, L_0x2b78750, C4<0>, C4<0>, C4<0>; +L_0x2b78260 .delay (10000,10000,10000) L_0x2b78260/d; +L_0x2b78340/d .functor AND 1, L_0x2b78070, L_0x2b78260, C4<1>, C4<1>; +L_0x2b78340 .delay (20000,20000,20000) L_0x2b78340/d; +L_0x2b78470/d .functor AND 1, L_0x2b778a0, L_0x2b78750, C4<1>, C4<1>; +L_0x2b78470 .delay (20000,20000,20000) L_0x2b78470/d; +L_0x2b78580/d .functor OR 1, L_0x2b78340, L_0x2b78470, C4<0>, C4<0>; +L_0x2b78580 .delay (20000,20000,20000) L_0x2b78580/d; +v0x22829c0_0 .net "S", 0 0, L_0x2b78750; 1 drivers +v0x227ddd0_0 .alias "in0", 0 0, v0x225dc20_0; +v0x227de70_0 .alias "in1", 0 0, v0x258b2f0_0; +v0x227d880_0 .net "nS", 0 0, L_0x2b78260; 1 drivers +v0x227d920_0 .net "out0", 0 0, L_0x2b78340; 1 drivers +v0x227b270_0 .net "out1", 0 0, L_0x2b78470; 1 drivers +v0x2279290_0 .alias "outfinal", 0 0, v0x22f4150_0; +S_0x228ba20 .scope module, "setSLTres2" "TwoInMux" 3 335, 3 109, S_0x2294e40; + .timescale -9 -12; +L_0x2b792f0/d .functor NOT 1, L_0x2ba8dd0, C4<0>, C4<0>, C4<0>; +L_0x2b792f0 .delay (10000,10000,10000) L_0x2b792f0/d; +L_0x2b79390/d .functor AND 1, L_0x2b79b00, L_0x2b792f0, C4<1>, C4<1>; +L_0x2b79390 .delay (20000,20000,20000) L_0x2b79390/d; +L_0x2b794a0/d .functor AND 1, C4<0>, L_0x2ba8dd0, C4<1>, C4<1>; +L_0x2b794a0 .delay (20000,20000,20000) L_0x2b794a0/d; +L_0x2b79560/d .functor OR 1, L_0x2b79390, L_0x2b794a0, C4<0>, C4<0>; +L_0x2b79560 .delay (20000,20000,20000) L_0x2b79560/d; +v0x228bfd0_0 .alias "S", 0 0, v0x240f880_0; +v0x2261900_0 .net "in0", 0 0, L_0x2b79b00; 1 drivers +v0x22619a0_0 .net "in1", 0 0, C4<0>; 1 drivers +v0x2287470_0 .net "nS", 0 0, L_0x2b792f0; 1 drivers +v0x2287510_0 .net "out0", 0 0, L_0x2b79390; 1 drivers +v0x2286f20_0 .net "out1", 0 0, L_0x2b794a0; 1 drivers +v0x2282920_0 .net "outfinal", 0 0, L_0x2b79560; 1 drivers +S_0x22929c0 .scope module, "setSLTres3" "TwoInMux" 3 336, 3 109, S_0x2294e40; + .timescale -9 -12; +L_0x2b77bd0/d .functor NOT 1, L_0x2ba8dd0, C4<0>, C4<0>, C4<0>; +L_0x2b77bd0 .delay (10000,10000,10000) L_0x2b77bd0/d; +L_0x2b77ce0/d .functor AND 1, L_0x2b7a180, L_0x2b77bd0, C4<1>, C4<1>; +L_0x2b77ce0 .delay (20000,20000,20000) L_0x2b77ce0/d; +L_0x2b79f00/d .functor AND 1, L_0x2b79bf0, L_0x2ba8dd0, C4<1>, C4<1>; +L_0x2b79f00 .delay (20000,20000,20000) L_0x2b79f00/d; +L_0x2b79fa0/d .functor OR 1, L_0x2b77ce0, L_0x2b79f00, C4<0>, C4<0>; +L_0x2b79fa0 .delay (20000,20000,20000) L_0x2b79fa0/d; +v0x22953f0_0 .alias "S", 0 0, v0x240f880_0; +v0x2290940_0 .net "in0", 0 0, L_0x2b7a180; 1 drivers +v0x22909e0_0 .net "in1", 0 0, L_0x2b79bf0; 1 drivers +v0x2290430_0 .net "nS", 0 0, L_0x2b77bd0; 1 drivers +v0x22904d0_0 .net "out0", 0 0, L_0x2b77ce0; 1 drivers +v0x228dfb0_0 .net "out1", 0 0, L_0x2b79f00; 1 drivers +v0x228bf30_0 .net "outfinal", 0 0, L_0x2b79fa0; 1 drivers +S_0x22ba820 .scope generate, "sltbits[10]" "sltbits[10]" 3 332, 3 332, S_0x2753240; + .timescale -9 -12; +P_0x22c8528 .param/l "i" 3 332, +C4<01010>; +S_0x22ac4e0 .scope module, "attempt" "MiddleAddSubSLT" 3 334, 3 189, S_0x22ba820; + .timescale -9 -12; +L_0x2b79ce0/d .functor NOT 1, L_0x2b7a4f0, C4<0>, C4<0>, C4<0>; +L_0x2b79ce0 .delay (10000,10000,10000) L_0x2b79ce0/d; +L_0x2b7ab00/d .functor NOT 1, L_0x2b7abc0, C4<0>, C4<0>, C4<0>; +L_0x2b7ab00 .delay (10000,10000,10000) L_0x2b7ab00/d; +L_0x2b7ac60/d .functor AND 1, L_0x2b7ada0, L_0x2b7ab00, C4<1>, C4<1>; +L_0x2b7ac60 .delay (20000,20000,20000) L_0x2b7ac60/d; +L_0x2b7ae40/d .functor XOR 1, L_0x2b7a450, L_0x2b7a870, C4<0>, C4<0>; +L_0x2b7ae40 .delay (40000,40000,40000) L_0x2b7ae40/d; +L_0x2b7af30/d .functor XOR 1, L_0x2b7ae40, L_0x2b7b530, C4<0>, C4<0>; +L_0x2b7af30 .delay (40000,40000,40000) L_0x2b7af30/d; +L_0x2b7b040/d .functor AND 1, L_0x2b7a450, L_0x2b7a870, C4<1>, C4<1>; +L_0x2b7b040 .delay (20000,20000,20000) L_0x2b7b040/d; +L_0x2b7b1d0/d .functor AND 1, L_0x2b7ae40, L_0x2b7b530, C4<1>, C4<1>; +L_0x2b7b1d0 .delay (20000,20000,20000) L_0x2b7b1d0/d; +L_0x2b7b2e0/d .functor OR 1, L_0x2b7b040, L_0x2b7b1d0, C4<0>, C4<0>; +L_0x2b7b2e0 .delay (20000,20000,20000) L_0x2b7b2e0/d; +v0x229e930_0 .net "A", 0 0, L_0x2b7a450; 1 drivers +v0x229e340_0 .net "AandB", 0 0, L_0x2b7b040; 1 drivers +v0x229e3e0_0 .net "AddSubSLTSum", 0 0, L_0x2b7af30; 1 drivers +v0x229bd30_0 .net "AxorB", 0 0, L_0x2b7ae40; 1 drivers +v0x229bdd0_0 .net "B", 0 0, L_0x2b7a4f0; 1 drivers +v0x2299d60_0 .net "BornB", 0 0, L_0x2b7a870; 1 drivers +v0x2299e20_0 .net "CINandAxorB", 0 0, L_0x2b7b1d0; 1 drivers +v0x2299850_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x22998d0_0 .net *"_s3", 0 0, L_0x2b7abc0; 1 drivers +v0x22973d0_0 .net *"_s5", 0 0, L_0x2b7ada0; 1 drivers +v0x2297470_0 .net "carryin", 0 0, L_0x2b7b530; 1 drivers +v0x2261e50_0 .net "carryout", 0 0, L_0x2b7b2e0; 1 drivers +v0x2261ef0_0 .net "nB", 0 0, L_0x2b79ce0; 1 drivers +v0x225cf20_0 .net "nCmd2", 0 0, L_0x2b7ab00; 1 drivers +v0x2295350_0 .net "subtract", 0 0, L_0x2b7ac60; 1 drivers +L_0x2b7aa40 .part v0x2960210_0, 0, 1; +L_0x2b7abc0 .part v0x2960210_0, 2, 1; +L_0x2b7ada0 .part v0x2960210_0, 0, 1; +S_0x22a7f30 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x22ac4e0; + .timescale -9 -12; +L_0x2b7a590/d .functor NOT 1, L_0x2b7aa40, C4<0>, C4<0>, C4<0>; +L_0x2b7a590 .delay (10000,10000,10000) L_0x2b7a590/d; +L_0x2b7a630/d .functor AND 1, L_0x2b7a4f0, L_0x2b7a590, C4<1>, C4<1>; +L_0x2b7a630 .delay (20000,20000,20000) L_0x2b7a630/d; +L_0x2b7a760/d .functor AND 1, L_0x2b79ce0, L_0x2b7aa40, C4<1>, C4<1>; +L_0x2b7a760 .delay (20000,20000,20000) L_0x2b7a760/d; +L_0x2b7a870/d .functor OR 1, L_0x2b7a630, L_0x2b7a760, C4<0>, C4<0>; +L_0x2b7a870 .delay (20000,20000,20000) L_0x2b7a870/d; +v0x22aca90_0 .net "S", 0 0, L_0x2b7aa40; 1 drivers +v0x22a79e0_0 .alias "in0", 0 0, v0x229bdd0_0; +v0x22a7a80_0 .alias "in1", 0 0, v0x2261ef0_0; +v0x22a33e0_0 .net "nS", 0 0, L_0x2b7a590; 1 drivers +v0x22a3480_0 .net "out0", 0 0, L_0x2b7a630; 1 drivers +v0x22a2e90_0 .net "out1", 0 0, L_0x2b7a760; 1 drivers +v0x229e890_0 .alias "outfinal", 0 0, v0x2299d60_0; +S_0x22b3480 .scope module, "setSLTres2" "TwoInMux" 3 335, 3 109, S_0x22ba820; + .timescale -9 -12; +L_0x2b7b5d0/d .functor NOT 1, L_0x2ba8dd0, C4<0>, C4<0>, C4<0>; +L_0x2b7b5d0 .delay (10000,10000,10000) L_0x2b7b5d0/d; +L_0x2b7b670/d .functor AND 1, L_0x2b7b900, L_0x2b7b5d0, C4<1>, C4<1>; +L_0x2b7b670 .delay (20000,20000,20000) L_0x2b7b670/d; +L_0x2b7b780/d .functor AND 1, C4<0>, L_0x2ba8dd0, C4<1>, C4<1>; +L_0x2b7b780 .delay (20000,20000,20000) L_0x2b7b780/d; +L_0x2b7bc50/d .functor OR 1, L_0x2b7b670, L_0x2b7b780, C4<0>, C4<0>; +L_0x2b7bc50 .delay (20000,20000,20000) L_0x2b7bc50/d; +v0x22b59a0_0 .alias "S", 0 0, v0x240f880_0; +v0x22b1400_0 .net "in0", 0 0, L_0x2b7b900; 1 drivers +v0x22b14a0_0 .net "in1", 0 0, C4<0>; 1 drivers +v0x22b0ef0_0 .net "nS", 0 0, L_0x2b7b5d0; 1 drivers +v0x22b0f90_0 .net "out0", 0 0, L_0x2b7b670; 1 drivers +v0x22aea70_0 .net "out1", 0 0, L_0x2b7b780; 1 drivers +v0x22ac9f0_0 .net "outfinal", 0 0, L_0x2b7bc50; 1 drivers +S_0x22ba310 .scope module, "setSLTres3" "TwoInMux" 3 336, 3 109, S_0x22ba820; + .timescale -9 -12; +L_0x2b7ba80/d .functor NOT 1, L_0x2ba8dd0, C4<0>, C4<0>, C4<0>; +L_0x2b7ba80 .delay (10000,10000,10000) L_0x2b7ba80/d; +L_0x2b7bb90/d .functor AND 1, L_0x2b7be30, L_0x2b7ba80, C4<1>, C4<1>; +L_0x2b7bb90 .delay (20000,20000,20000) L_0x2b7bb90/d; +L_0x2b79760/d .functor AND 1, L_0x2b7bf20, L_0x2ba8dd0, C4<1>, C4<1>; +L_0x2b79760 .delay (20000,20000,20000) L_0x2b79760/d; +L_0x2b79820/d .functor OR 1, L_0x2b7bb90, L_0x2b79760, C4<0>, C4<0>; +L_0x2b79820 .delay (20000,20000,20000) L_0x2b79820/d; +v0x22beea0_0 .alias "S", 0 0, v0x240f880_0; +v0x2266450_0 .net "in0", 0 0, L_0x2b7be30; 1 drivers +v0x22664f0_0 .net "in1", 0 0, L_0x2b7bf20; 1 drivers +v0x22b7e90_0 .net "nS", 0 0, L_0x2b7ba80; 1 drivers +v0x22b7f30_0 .net "out0", 0 0, L_0x2b7bb90; 1 drivers +v0x22b5e10_0 .net "out1", 0 0, L_0x2b79760; 1 drivers +v0x22b5900_0 .net "outfinal", 0 0, L_0x2b79820; 1 drivers +S_0x22e94d0 .scope generate, "sltbits[11]" "sltbits[11]" 3 332, 3 332, S_0x2753240; + .timescale -9 -12; +P_0x2403c08 .param/l "i" 3 332, +C4<01011>; +S_0x22d3f40 .scope module, "attempt" "MiddleAddSubSLT" 3 334, 3 189, S_0x22e94d0; + .timescale -9 -12; +L_0x2b7c010/d .functor NOT 1, L_0x2b7c640, C4<0>, C4<0>, C4<0>; +L_0x2b7c010 .delay (10000,10000,10000) L_0x2b7c010/d; +L_0x2b7ce10/d .functor NOT 1, L_0x2b7ced0, C4<0>, C4<0>, C4<0>; +L_0x2b7ce10 .delay (10000,10000,10000) L_0x2b7ce10/d; +L_0x2b7cf70/d .functor AND 1, L_0x2b7d0b0, L_0x2b7ce10, C4<1>, C4<1>; +L_0x2b7cf70 .delay (20000,20000,20000) L_0x2b7cf70/d; +L_0x2b7d150/d .functor XOR 1, L_0x2b7c5a0, L_0x2b7cba0, C4<0>, C4<0>; +L_0x2b7d150 .delay (40000,40000,40000) L_0x2b7d150/d; +L_0x2b7d240/d .functor XOR 1, L_0x2b7d150, L_0x2b7c770, C4<0>, C4<0>; +L_0x2b7d240 .delay (40000,40000,40000) L_0x2b7d240/d; +L_0x2b7d330/d .functor AND 1, L_0x2b7c5a0, L_0x2b7cba0, C4<1>, C4<1>; +L_0x2b7d330 .delay (20000,20000,20000) L_0x2b7d330/d; +L_0x2b7d4c0/d .functor AND 1, L_0x2b7d150, L_0x2b7c770, C4<1>, C4<1>; +L_0x2b7d4c0 .delay (20000,20000,20000) L_0x2b7d4c0/d; +L_0x2b7d5d0/d .functor OR 1, L_0x2b7d330, L_0x2b7d4c0, C4<0>, C4<0>; +L_0x2b7d5d0 .delay (20000,20000,20000) L_0x2b7d5d0/d; +v0x22cd550_0 .net "A", 0 0, L_0x2b7c5a0; 1 drivers +v0x22ccfa0_0 .net "AandB", 0 0, L_0x2b7d330; 1 drivers +v0x22cd040_0 .net "AddSubSLTSum", 0 0, L_0x2b7d240; 1 drivers +v0x22c89f0_0 .net "AxorB", 0 0, L_0x2b7d150; 1 drivers +v0x22c8a90_0 .net "B", 0 0, L_0x2b7c640; 1 drivers +v0x22c84a0_0 .net "BornB", 0 0, L_0x2b7cba0; 1 drivers +v0x22c8560_0 .net "CINandAxorB", 0 0, L_0x2b7d4c0; 1 drivers +v0x22669a0_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x2266a20_0 .net *"_s3", 0 0, L_0x2b7ced0; 1 drivers +v0x22c3ea0_0 .net *"_s5", 0 0, L_0x2b7d0b0; 1 drivers +v0x22c3f40_0 .net "carryin", 0 0, L_0x2b7c770; 1 drivers +v0x22c3950_0 .net "carryout", 0 0, L_0x2b7d5d0; 1 drivers +v0x22c39f0_0 .net "nB", 0 0, L_0x2b7c010; 1 drivers +v0x22bf350_0 .net "nCmd2", 0 0, L_0x2b7ce10; 1 drivers +v0x22bee00_0 .net "subtract", 0 0, L_0x2b7cf70; 1 drivers +L_0x2b7cd70 .part v0x2960210_0, 0, 1; +L_0x2b7ced0 .part v0x2960210_0, 2, 1; +L_0x2b7d0b0 .part v0x2960210_0, 0, 1; +S_0x22d1ec0 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x22d3f40; + .timescale -9 -12; +L_0x2b7c880/d .functor NOT 1, L_0x2b7cd70, C4<0>, C4<0>, C4<0>; +L_0x2b7c880 .delay (10000,10000,10000) L_0x2b7c880/d; +L_0x2b7c960/d .functor AND 1, L_0x2b7c640, L_0x2b7c880, C4<1>, C4<1>; +L_0x2b7c960 .delay (20000,20000,20000) L_0x2b7c960/d; +L_0x2b7ca90/d .functor AND 1, L_0x2b7c010, L_0x2b7cd70, C4<1>, C4<1>; +L_0x2b7ca90 .delay (20000,20000,20000) L_0x2b7ca90/d; +L_0x2b7cba0/d .functor OR 1, L_0x2b7c960, L_0x2b7ca90, C4<0>, C4<0>; +L_0x2b7cba0 .delay (20000,20000,20000) L_0x2b7cba0/d; +v0x22d6460_0 .net "S", 0 0, L_0x2b7cd70; 1 drivers +v0x22d19b0_0 .alias "in0", 0 0, v0x22c8a90_0; +v0x22d1a50_0 .alias "in1", 0 0, v0x22c39f0_0; +v0x225d160_0 .net "nS", 0 0, L_0x2b7c880; 1 drivers +v0x225d200_0 .net "out0", 0 0, L_0x2b7c960; 1 drivers +v0x22cf530_0 .net "out1", 0 0, L_0x2b7ca90; 1 drivers +v0x22cd4b0_0 .alias "outfinal", 0 0, v0x22c84a0_0; +S_0x22df8e0 .scope module, "setSLTres2" "TwoInMux" 3 335, 3 109, S_0x22e94d0; + .timescale -9 -12; +L_0x2b7dcc0/d .functor NOT 1, L_0x2ba8dd0, C4<0>, C4<0>, C4<0>; +L_0x2b7dcc0 .delay (10000,10000,10000) L_0x2b7dcc0/d; +L_0x2b7dd40/d .functor AND 1, L_0x2b7e110, L_0x2b7dcc0, C4<1>, C4<1>; +L_0x2b7dd40 .delay (20000,20000,20000) L_0x2b7dd40/d; +L_0x2b7de50/d .functor AND 1, C4<0>, L_0x2ba8dd0, C4<1>, C4<1>; +L_0x2b7de50 .delay (20000,20000,20000) L_0x2b7de50/d; +L_0x2b7df10/d .functor OR 1, L_0x2b7dd40, L_0x2b7de50, C4<0>, C4<0>; +L_0x2b7df10 .delay (20000,20000,20000) L_0x2b7df10/d; +v0x22dfed0_0 .alias "S", 0 0, v0x240f880_0; +v0x22db2e0_0 .net "in0", 0 0, L_0x2b7e110; 1 drivers +v0x22db380_0 .net "in1", 0 0, C4<0>; 1 drivers +v0x22d8950_0 .net "nS", 0 0, L_0x2b7dcc0; 1 drivers +v0x22d89f0_0 .net "out0", 0 0, L_0x2b7dd40; 1 drivers +v0x22d68d0_0 .net "out1", 0 0, L_0x2b7de50; 1 drivers +v0x22d63c0_0 .net "outfinal", 0 0, L_0x2b7df10; 1 drivers +S_0x22e8f80 .scope module, "setSLTres3" "TwoInMux" 3 336, 3 109, S_0x22e94d0; + .timescale -9 -12; +L_0x2b7d9a0/d .functor NOT 1, L_0x2ba8dd0, C4<0>, C4<0>, C4<0>; +L_0x2b7d9a0 .delay (10000,10000,10000) L_0x2b7d9a0/d; +L_0x2b7dab0/d .functor AND 1, L_0x2b7e7a0, L_0x2b7d9a0, C4<1>, C4<1>; +L_0x2b7dab0 .delay (20000,20000,20000) L_0x2b7dab0/d; +L_0x2b7dbc0/d .functor AND 1, L_0x2b72ef0, L_0x2ba8dd0, C4<1>, C4<1>; +L_0x2b7dbc0 .delay (20000,20000,20000) L_0x2b7dbc0/d; +L_0x2b7e5c0/d .functor OR 1, L_0x2b7dab0, L_0x2b7dbc0, C4<0>, C4<0>; +L_0x2b7e5c0 .delay (20000,20000,20000) L_0x2b7e5c0/d; +v0x22ee6a0_0 .alias "S", 0 0, v0x240f880_0; +v0x226af50_0 .net "in0", 0 0, L_0x2b7e7a0; 1 drivers +v0x226aff0_0 .net "in1", 0 0, L_0x2b72ef0; 1 drivers +v0x22e4980_0 .net "nS", 0 0, L_0x2b7d9a0; 1 drivers +v0x22e4a20_0 .net "out0", 0 0, L_0x2b7dab0; 1 drivers +v0x22e4430_0 .net "out1", 0 0, L_0x2b7dbc0; 1 drivers +v0x22dfe30_0 .net "outfinal", 0 0, L_0x2b7e5c0; 1 drivers +S_0x222f970 .scope generate, "sltbits[12]" "sltbits[12]" 3 332, 3 332, S_0x2753240; + .timescale -9 -12; +P_0x2237f18 .param/l "i" 3 332, +C4<01100>; +S_0x22219e0 .scope module, "attempt" "MiddleAddSubSLT" 3 334, 3 189, S_0x222f970; + .timescale -9 -12; +L_0x2b72fe0/d .functor NOT 1, L_0x2b7ef20, C4<0>, C4<0>, C4<0>; +L_0x2b72fe0 .delay (10000,10000,10000) L_0x2b72fe0/d; +L_0x2b7f200/d .functor NOT 1, L_0x2b7f2a0, C4<0>, C4<0>, C4<0>; +L_0x2b7f200 .delay (10000,10000,10000) L_0x2b7f200/d; +L_0x2b7f340/d .functor AND 1, L_0x2b7f480, L_0x2b7f200, C4<1>, C4<1>; +L_0x2b7f340 .delay (20000,20000,20000) L_0x2b7f340/d; +L_0x2b7f520/d .functor XOR 1, L_0x2b7ee80, L_0x2b7e520, C4<0>, C4<0>; +L_0x2b7f520 .delay (40000,40000,40000) L_0x2b7f520/d; +L_0x2b7f610/d .functor XOR 1, L_0x2b7f520, L_0x2b7ff90, C4<0>, C4<0>; +L_0x2b7f610 .delay (40000,40000,40000) L_0x2b7f610/d; +L_0x2b7f700/d .functor AND 1, L_0x2b7ee80, L_0x2b7e520, C4<1>, C4<1>; +L_0x2b7f700 .delay (20000,20000,20000) L_0x2b7f700/d; +L_0x2b7f870/d .functor AND 1, L_0x2b7f520, L_0x2b7ff90, C4<1>, C4<1>; +L_0x2b7f870 .delay (20000,20000,20000) L_0x2b7f870/d; +L_0x2b7f960/d .functor OR 1, L_0x2b7f700, L_0x2b7f870, C4<0>, C4<0>; +L_0x2b7f960 .delay (20000,20000,20000) L_0x2b7f960/d; +v0x2274920_0 .net "A", 0 0, L_0x2b7ee80; 1 drivers +v0x2274370_0 .net "AandB", 0 0, L_0x2b7f700; 1 drivers +v0x2274410_0 .net "AddSubSLTSum", 0 0, L_0x2b7f610; 1 drivers +v0x2271ef0_0 .net "AxorB", 0 0, L_0x2b7f520; 1 drivers +v0x2271f90_0 .net "B", 0 0, L_0x2b7ef20; 1 drivers +v0x226fe70_0 .net "BornB", 0 0, L_0x2b7e520; 1 drivers +v0x226fef0_0 .net "CINandAxorB", 0 0, L_0x2b7f870; 1 drivers +v0x226f960_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x226f9e0_0 .net *"_s3", 0 0, L_0x2b7f2a0; 1 drivers +v0x226d4e0_0 .net *"_s5", 0 0, L_0x2b7f480; 1 drivers +v0x226d580_0 .net "carryin", 0 0, L_0x2b7ff90; 1 drivers +v0x226b460_0 .net "carryout", 0 0, L_0x2b7f960; 1 drivers +v0x226b500_0 .net "nB", 0 0, L_0x2b72fe0; 1 drivers +v0x22eeb10_0 .net "nCmd2", 0 0, L_0x2b7f200; 1 drivers +v0x22ee600_0 .net "subtract", 0 0, L_0x2b7f340; 1 drivers +L_0x2b7f160 .part v0x2960210_0, 0, 1; +L_0x2b7f2a0 .part v0x2960210_0, 2, 1; +L_0x2b7f480 .part v0x2960210_0, 0, 1; +S_0x2202790 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x22219e0; + .timescale -9 -12; +L_0x2b7e200/d .functor NOT 1, L_0x2b7f160, C4<0>, C4<0>, C4<0>; +L_0x2b7e200 .delay (10000,10000,10000) L_0x2b7e200/d; +L_0x2b7e2e0/d .functor AND 1, L_0x2b7ef20, L_0x2b7e200, C4<1>, C4<1>; +L_0x2b7e2e0 .delay (20000,20000,20000) L_0x2b7e2e0/d; +L_0x2b7e410/d .functor AND 1, L_0x2b72fe0, L_0x2b7f160, C4<1>, C4<1>; +L_0x2b7e410 .delay (20000,20000,20000) L_0x2b7e410/d; +L_0x2b7e520/d .functor OR 1, L_0x2b7e2e0, L_0x2b7e410, C4<0>, C4<0>; +L_0x2b7e520 .delay (20000,20000,20000) L_0x2b7e520/d; +v0x2224250_0 .net "S", 0 0, L_0x2b7f160; 1 drivers +v0x2203700_0 .alias "in0", 0 0, v0x2271f90_0; +v0x22037a0_0 .alias "in1", 0 0, v0x226b500_0; +v0x2278d80_0 .net "nS", 0 0, L_0x2b7e200; 1 drivers +v0x2278e20_0 .net "out0", 0 0, L_0x2b7e2e0; 1 drivers +v0x2276900_0 .net "out1", 0 0, L_0x2b7e410; 1 drivers +v0x2274880_0 .alias "outfinal", 0 0, v0x226fe70_0; +S_0x2229ba0 .scope module, "setSLTres2" "TwoInMux" 3 335, 3 109, S_0x222f970; + .timescale -9 -12; +L_0x2b80030/d .functor NOT 1, L_0x2ba8dd0, C4<0>, C4<0>, C4<0>; +L_0x2b80030 .delay (10000,10000,10000) L_0x2b80030/d; +L_0x2b80090/d .functor AND 1, L_0x2b7fb90, L_0x2b80030, C4<1>, C4<1>; +L_0x2b80090 .delay (20000,20000,20000) L_0x2b80090/d; +L_0x2b80180/d .functor AND 1, C4<0>, L_0x2ba8dd0, C4<1>, C4<1>; +L_0x2b80180 .delay (20000,20000,20000) L_0x2b80180/d; +L_0x2b80220/d .functor OR 1, L_0x2b80090, L_0x2b80180, C4<0>, C4<0>; +L_0x2b80220 .delay (20000,20000,20000) L_0x2b80220/d; +v0x2205b70_0 .alias "S", 0 0, v0x240f880_0; +v0x2227420_0 .net "in0", 0 0, L_0x2b7fb90; 1 drivers +v0x22274c0_0 .net "in1", 0 0, C4<0>; 1 drivers +v0x2226ed0_0 .net "nS", 0 0, L_0x2b80030; 1 drivers +v0x2226f70_0 .net "out0", 0 0, L_0x2b80090; 1 drivers +v0x2224700_0 .net "out1", 0 0, L_0x2b80180; 1 drivers +v0x22241b0_0 .net "outfinal", 0 0, L_0x2b80220; 1 drivers +S_0x222f460 .scope module, "setSLTres3" "TwoInMux" 3 336, 3 109, S_0x222f970; + .timescale -9 -12; +L_0x2b7fd10/d .functor NOT 1, L_0x2ba8dd0, C4<0>, C4<0>, C4<0>; +L_0x2b7fd10 .delay (10000,10000,10000) L_0x2b7fd10/d; +L_0x2b7fe40/d .functor AND 1, L_0x2b80400, L_0x2b7fd10, C4<1>, C4<1>; +L_0x2b7fe40 .delay (20000,20000,20000) L_0x2b7fe40/d; +L_0x2b7c190/d .functor AND 1, L_0x2b804f0, L_0x2ba8dd0, C4<1>, C4<1>; +L_0x2b7c190 .delay (20000,20000,20000) L_0x2b7c190/d; +L_0x2b7c210/d .functor OR 1, L_0x2b7fe40, L_0x2b7c190, C4<0>, C4<0>; +L_0x2b7c210 .delay (20000,20000,20000) L_0x2b7c210/d; +v0x2232160_0 .alias "S", 0 0, v0x240f880_0; +v0x222cd10_0 .net "in0", 0 0, L_0x2b80400; 1 drivers +v0x222cdb0_0 .net "in1", 0 0, L_0x2b804f0; 1 drivers +v0x222c800_0 .net "nS", 0 0, L_0x2b7fd10; 1 drivers +v0x222c8a0_0 .net "out0", 0 0, L_0x2b7fe40; 1 drivers +v0x222a0b0_0 .net "out1", 0 0, L_0x2b7c190; 1 drivers +v0x2205ad0_0 .net "outfinal", 0 0, L_0x2b7c210; 1 drivers +S_0x2250da0 .scope generate, "sltbits[13]" "sltbits[13]" 3 332, 3 332, S_0x2753240; + .timescale -9 -12; +P_0x2256bf8 .param/l "i" 3 332, +C4<01101>; +S_0x2242dd0 .scope module, "attempt" "MiddleAddSubSLT" 3 334, 3 189, S_0x2250da0; + .timescale -9 -12; +L_0x2b805e0/d .functor NOT 1, L_0x2b80c30, C4<0>, C4<0>, C4<0>; +L_0x2b805e0 .delay (10000,10000,10000) L_0x2b805e0/d; +L_0x2b81320/d .functor NOT 1, L_0x2b813c0, C4<0>, C4<0>, C4<0>; +L_0x2b81320 .delay (10000,10000,10000) L_0x2b81320/d; +L_0x2b81460/d .functor AND 1, L_0x2b815a0, L_0x2b81320, C4<1>, C4<1>; +L_0x2b81460 .delay (20000,20000,20000) L_0x2b81460/d; +L_0x2b81640/d .functor XOR 1, L_0x2b80b90, L_0x2b810f0, C4<0>, C4<0>; +L_0x2b81640 .delay (40000,40000,40000) L_0x2b81640/d; +L_0x2b81730/d .functor XOR 1, L_0x2b81640, L_0x2b80d60, C4<0>, C4<0>; +L_0x2b81730 .delay (40000,40000,40000) L_0x2b81730/d; +L_0x2b81820/d .functor AND 1, L_0x2b80b90, L_0x2b810f0, C4<1>, C4<1>; +L_0x2b81820 .delay (20000,20000,20000) L_0x2b81820/d; +L_0x2b81990/d .functor AND 1, L_0x2b81640, L_0x2b80d60, C4<1>, C4<1>; +L_0x2b81990 .delay (20000,20000,20000) L_0x2b81990/d; +L_0x2b81a80/d .functor OR 1, L_0x2b81820, L_0x2b81990, C4<0>, C4<0>; +L_0x2b81a80 .delay (20000,20000,20000) L_0x2b81a80/d; +v0x223ac60_0 .net "A", 0 0, L_0x2b80b90; 1 drivers +v0x223a670_0 .net "AandB", 0 0, L_0x2b81820; 1 drivers +v0x223a710_0 .net "AddSubSLTSum", 0 0, L_0x2b81730; 1 drivers +v0x22082a0_0 .net "AxorB", 0 0, L_0x2b81640; 1 drivers +v0x2208340_0 .net "B", 0 0, L_0x2b80c30; 1 drivers +v0x2237e90_0 .net "BornB", 0 0, L_0x2b810f0; 1 drivers +v0x2237f50_0 .net "CINandAxorB", 0 0, L_0x2b81990; 1 drivers +v0x2237980_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x2237a00_0 .net *"_s3", 0 0, L_0x2b813c0; 1 drivers +v0x2235230_0 .net *"_s5", 0 0, L_0x2b815a0; 1 drivers +v0x22352d0_0 .net "carryin", 0 0, L_0x2b80d60; 1 drivers +v0x2234d20_0 .net "carryout", 0 0, L_0x2b81a80; 1 drivers +v0x2234dc0_0 .net "nB", 0 0, L_0x2b805e0; 1 drivers +v0x22325d0_0 .net "nCmd2", 0 0, L_0x2b81320; 1 drivers +v0x22320c0_0 .net "subtract", 0 0, L_0x2b81460; 1 drivers +L_0x2b81280 .part v0x2960210_0, 0, 1; +L_0x2b813c0 .part v0x2960210_0, 2, 1; +L_0x2b815a0 .part v0x2960210_0, 0, 1; +S_0x2240600 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x2242dd0; + .timescale -9 -12; +L_0x2b807b0/d .functor NOT 1, L_0x2b81280, C4<0>, C4<0>, C4<0>; +L_0x2b807b0 .delay (10000,10000,10000) L_0x2b807b0/d; +L_0x2b80f10/d .functor AND 1, L_0x2b80c30, L_0x2b807b0, C4<1>, C4<1>; +L_0x2b80f10 .delay (20000,20000,20000) L_0x2b80f10/d; +L_0x2b81000/d .functor AND 1, L_0x2b805e0, L_0x2b81280, C4<1>, C4<1>; +L_0x2b81000 .delay (20000,20000,20000) L_0x2b81000/d; +L_0x2b810f0/d .functor OR 1, L_0x2b80f10, L_0x2b81000, C4<0>, C4<0>; +L_0x2b810f0 .delay (20000,20000,20000) L_0x2b810f0/d; +v0x22433c0_0 .net "S", 0 0, L_0x2b81280; 1 drivers +v0x22400b0_0 .alias "in0", 0 0, v0x2208340_0; +v0x2240150_0 .alias "in1", 0 0, v0x2234dc0_0; +v0x223d8e0_0 .net "nS", 0 0, L_0x2b807b0; 1 drivers +v0x223d980_0 .net "out0", 0 0, L_0x2b80f10; 1 drivers +v0x223d390_0 .net "out1", 0 0, L_0x2b81000; 1 drivers +v0x223abc0_0 .alias "outfinal", 0 0, v0x2237e90_0; +S_0x2248810 .scope module, "setSLTres2" "TwoInMux" 3 335, 3 109, S_0x2250da0; + .timescale -9 -12; +L_0x2b80e00/d .functor NOT 1, L_0x2ba8dd0, C4<0>, C4<0>, C4<0>; +L_0x2b80e00 .delay (10000,10000,10000) L_0x2b80e00/d; +L_0x2b82200/d .functor AND 1, L_0x2b82570, L_0x2b80e00, C4<1>, C4<1>; +L_0x2b82200 .delay (20000,20000,20000) L_0x2b82200/d; +L_0x2b822f0/d .functor AND 1, C4<0>, L_0x2ba8dd0, C4<1>, C4<1>; +L_0x2b822f0 .delay (20000,20000,20000) L_0x2b822f0/d; +L_0x2b82390/d .functor OR 1, L_0x2b82200, L_0x2b822f0, C4<0>, C4<0>; +L_0x2b82390 .delay (20000,20000,20000) L_0x2b82390/d; +v0x2248e00_0 .alias "S", 0 0, v0x240f880_0; +v0x2246040_0 .net "in0", 0 0, L_0x2b82570; 1 drivers +v0x22460e0_0 .net "in1", 0 0, C4<0>; 1 drivers +v0x22087b0_0 .net "nS", 0 0, L_0x2b80e00; 1 drivers +v0x2208850_0 .net "out0", 0 0, L_0x2b82200; 1 drivers +v0x2245af0_0 .net "out1", 0 0, L_0x2b822f0; 1 drivers +v0x2243320_0 .net "outfinal", 0 0, L_0x2b82390; 1 drivers +S_0x224e650 .scope module, "setSLTres3" "TwoInMux" 3 336, 3 109, S_0x2250da0; + .timescale -9 -12; +L_0x2b81e30/d .functor NOT 1, L_0x2ba8dd0, C4<0>, C4<0>, C4<0>; +L_0x2b81e30 .delay (10000,10000,10000) L_0x2b81e30/d; +L_0x2b81f40/d .functor AND 1, L_0x2b82c00, L_0x2b81e30, C4<1>, C4<1>; +L_0x2b81f40 .delay (20000,20000,20000) L_0x2b81f40/d; +L_0x2b82050/d .functor AND 1, L_0x2b82660, L_0x2ba8dd0, C4<1>, C4<1>; +L_0x2b82050 .delay (20000,20000,20000) L_0x2b82050/d; +L_0x2b82110/d .functor OR 1, L_0x2b81f40, L_0x2b82050, C4<0>, C4<0>; +L_0x2b82110 .delay (20000,20000,20000) L_0x2b82110/d; +v0x2251350_0 .alias "S", 0 0, v0x240f880_0; +v0x224e140_0 .net "in0", 0 0, L_0x2b82c00; 1 drivers +v0x224e1e0_0 .net "in1", 0 0, L_0x2b82660; 1 drivers +v0x224b9f0_0 .net "nS", 0 0, L_0x2b81e30; 1 drivers +v0x224ba90_0 .net "out0", 0 0, L_0x2b81f40; 1 drivers +v0x224b4e0_0 .net "out1", 0 0, L_0x2b82050; 1 drivers +v0x2248d60_0 .net "outfinal", 0 0, L_0x2b82110; 1 drivers +S_0x221e770 .scope generate, "sltbits[14]" "sltbits[14]" 3 332, 3 332, S_0x2753240; + .timescale -9 -12; +P_0x221edc8 .param/l "i" 3 332, +C4<01110>; +S_0x22107c0 .scope module, "attempt" "MiddleAddSubSLT" 3 334, 3 189, S_0x221e770; + .timescale -9 -12; +L_0x2b82750/d .functor NOT 1, L_0x2b84310, C4<0>, C4<0>, C4<0>; +L_0x2b82750 .delay (10000,10000,10000) L_0x2b82750/d; +L_0x2b834e0/d .functor NOT 1, L_0x2b83580, C4<0>, C4<0>, C4<0>; +L_0x2b834e0 .delay (10000,10000,10000) L_0x2b834e0/d; +L_0x2b83620/d .functor AND 1, L_0x2b83760, L_0x2b834e0, C4<1>, C4<1>; +L_0x2b83620 .delay (20000,20000,20000) L_0x2b83620/d; +L_0x2b83800/d .functor XOR 1, L_0x2b72760, L_0x2b832b0, C4<0>, C4<0>; +L_0x2b83800 .delay (40000,40000,40000) L_0x2b83800/d; +L_0x2b838f0/d .functor XOR 1, L_0x2b83800, L_0x2b83e70, C4<0>, C4<0>; +L_0x2b838f0 .delay (40000,40000,40000) L_0x2b838f0/d; +L_0x2b839e0/d .functor AND 1, L_0x2b72760, L_0x2b832b0, C4<1>, C4<1>; +L_0x2b839e0 .delay (20000,20000,20000) L_0x2b839e0/d; +L_0x2b83b50/d .functor AND 1, L_0x2b83800, L_0x2b83e70, C4<1>, C4<1>; +L_0x2b83b50 .delay (20000,20000,20000) L_0x2b83b50/d; +L_0x2b83c40/d .functor OR 1, L_0x2b839e0, L_0x2b83b50, C4<0>, C4<0>; +L_0x2b83c40 .delay (20000,20000,20000) L_0x2b83c40/d; +v0x2259d00_0 .net "A", 0 0, L_0x2b72760; 1 drivers +v0x22597d0_0 .net "AandB", 0 0, L_0x2b839e0; 1 drivers +v0x2259870_0 .net "AddSubSLTSum", 0 0, L_0x2b838f0; 1 drivers +v0x22592c0_0 .net "AxorB", 0 0, L_0x2b83800; 1 drivers +v0x2259360_0 .net "B", 0 0, L_0x2b84310; 1 drivers +v0x2256b70_0 .net "BornB", 0 0, L_0x2b832b0; 1 drivers +v0x2256c30_0 .net "CINandAxorB", 0 0, L_0x2b83b50; 1 drivers +v0x2256660_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x22566e0_0 .net *"_s3", 0 0, L_0x2b83580; 1 drivers +v0x220af00_0 .net *"_s5", 0 0, L_0x2b83760; 1 drivers +v0x220afa0_0 .net "carryin", 0 0, L_0x2b83e70; 1 drivers +v0x2253f10_0 .net "carryout", 0 0, L_0x2b83c40; 1 drivers +v0x2253fb0_0 .net "nB", 0 0, L_0x2b82750; 1 drivers +v0x2253a00_0 .net "nCmd2", 0 0, L_0x2b834e0; 1 drivers +v0x22512b0_0 .net "subtract", 0 0, L_0x2b83620; 1 drivers +L_0x2b83440 .part v0x2960210_0, 0, 1; +L_0x2b83580 .part v0x2960210_0, 2, 1; +L_0x2b83760 .part v0x2960210_0, 0, 1; +S_0x220e070 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x22107c0; + .timescale -9 -12; +L_0x2b82900/d .functor NOT 1, L_0x2b83440, C4<0>, C4<0>, C4<0>; +L_0x2b82900 .delay (10000,10000,10000) L_0x2b82900/d; +L_0x2b829e0/d .functor AND 1, L_0x2b84310, L_0x2b82900, C4<1>, C4<1>; +L_0x2b829e0 .delay (20000,20000,20000) L_0x2b829e0/d; +L_0x2b831c0/d .functor AND 1, L_0x2b82750, L_0x2b83440, C4<1>, C4<1>; +L_0x2b831c0 .delay (20000,20000,20000) L_0x2b831c0/d; +L_0x2b832b0/d .functor OR 1, L_0x2b829e0, L_0x2b831c0, C4<0>, C4<0>; +L_0x2b832b0 .delay (20000,20000,20000) L_0x2b832b0/d; +v0x2210d70_0 .net "S", 0 0, L_0x2b83440; 1 drivers +v0x2202ce0_0 .alias "in0", 0 0, v0x2259360_0; +v0x2202d80_0 .alias "in1", 0 0, v0x2253fb0_0; +v0x220db60_0 .net "nS", 0 0, L_0x2b82900; 1 drivers +v0x220dc00_0 .net "out0", 0 0, L_0x2b829e0; 1 drivers +v0x220b410_0 .net "out1", 0 0, L_0x2b831c0; 1 drivers +v0x2259c60_0 .alias "outfinal", 0 0, v0x2256b70_0; +S_0x2216590 .scope module, "setSLTres2" "TwoInMux" 3 335, 3 109, S_0x221e770; + .timescale -9 -12; +L_0x2b83f10/d .functor NOT 1, L_0x2ba8dd0, C4<0>, C4<0>, C4<0>; +L_0x2b83f10 .delay (10000,10000,10000) L_0x2b83f10/d; +L_0x2b83fb0/d .functor AND 1, L_0x2b843b0, L_0x2b83f10, C4<1>, C4<1>; +L_0x2b83fb0 .delay (20000,20000,20000) L_0x2b83fb0/d; +L_0x2b840c0/d .functor AND 1, C4<0>, L_0x2ba8dd0, C4<1>, C4<1>; +L_0x2b840c0 .delay (20000,20000,20000) L_0x2b840c0/d; +L_0x2b84180/d .functor OR 1, L_0x2b83fb0, L_0x2b840c0, C4<0>, C4<0>; +L_0x2b84180 .delay (20000,20000,20000) L_0x2b84180/d; +v0x2218dd0_0 .alias "S", 0 0, v0x240f880_0; +v0x2216080_0 .net "in0", 0 0, L_0x2b843b0; 1 drivers +v0x2216120_0 .net "in1", 0 0, C4<0>; 1 drivers +v0x2213930_0 .net "nS", 0 0, L_0x2b83f10; 1 drivers +v0x22139d0_0 .net "out0", 0 0, L_0x2b83fb0; 1 drivers +v0x2213420_0 .net "out1", 0 0, L_0x2b840c0; 1 drivers +v0x2210cd0_0 .net "outfinal", 0 0, L_0x2b84180; 1 drivers +S_0x2205580 .scope module, "setSLTres3" "TwoInMux" 3 336, 3 109, S_0x221e770; + .timescale -9 -12; +L_0x2b847d0/d .functor NOT 1, L_0x2ba8dd0, C4<0>, C4<0>, C4<0>; +L_0x2b847d0 .delay (10000,10000,10000) L_0x2b847d0/d; +L_0x2b80880/d .functor AND 1, L_0x2b84900, L_0x2b847d0, C4<1>, C4<1>; +L_0x2b80880 .delay (20000,20000,20000) L_0x2b80880/d; +L_0x2b80990/d .functor AND 1, L_0x2b849f0, L_0x2ba8dd0, C4<1>, C4<1>; +L_0x2b80990 .delay (20000,20000,20000) L_0x2b80990/d; +L_0x2b80a30/d .functor OR 1, L_0x2b80880, L_0x2b80990, C4<0>, C4<0>; +L_0x2b80a30 .delay (20000,20000,20000) L_0x2b80a30/d; +v0x221bfa0_0 .alias "S", 0 0, v0x240f880_0; +v0x221c020_0 .net "in0", 0 0, L_0x2b84900; 1 drivers +v0x221ba50_0 .net "in1", 0 0, L_0x2b849f0; 1 drivers +v0x221baf0_0 .net "nS", 0 0, L_0x2b847d0; 1 drivers +v0x2219280_0 .net "out0", 0 0, L_0x2b80880; 1 drivers +v0x2219320_0 .net "out1", 0 0, L_0x2b80990; 1 drivers +v0x2218d30_0 .net "outfinal", 0 0, L_0x2b80a30; 1 drivers +S_0x263c5b0 .scope generate, "sltbits[15]" "sltbits[15]" 3 332, 3 332, S_0x2753240; + .timescale -9 -12; +P_0x232d428 .param/l "i" 3 332, +C4<01111>; +S_0x2641910 .scope module, "attempt" "MiddleAddSubSLT" 3 334, 3 189, S_0x263c5b0; + .timescale -9 -12; +L_0x2b84ae0/d .functor NOT 1, L_0x2b850d0, C4<0>, C4<0>, C4<0>; +L_0x2b84ae0 .delay (10000,10000,10000) L_0x2b84ae0/d; +L_0x2b857f0/d .functor NOT 1, L_0x2b85890, C4<0>, C4<0>, C4<0>; +L_0x2b857f0 .delay (10000,10000,10000) L_0x2b857f0/d; +L_0x2b85930/d .functor AND 1, L_0x2b85a70, L_0x2b857f0, C4<1>, C4<1>; +L_0x2b85930 .delay (20000,20000,20000) L_0x2b85930/d; +L_0x2b85b10/d .functor XOR 1, L_0x2b85030, L_0x2b855c0, C4<0>, C4<0>; +L_0x2b85b10 .delay (40000,40000,40000) L_0x2b85b10/d; +L_0x2b85c00/d .functor XOR 1, L_0x2b85b10, L_0x2b85200, C4<0>, C4<0>; +L_0x2b85c00 .delay (40000,40000,40000) L_0x2b85c00/d; +L_0x2b85cf0/d .functor AND 1, L_0x2b85030, L_0x2b855c0, C4<1>, C4<1>; +L_0x2b85cf0 .delay (20000,20000,20000) L_0x2b85cf0/d; +L_0x2b85e60/d .functor AND 1, L_0x2b85b10, L_0x2b85200, C4<1>, C4<1>; +L_0x2b85e60 .delay (20000,20000,20000) L_0x2b85e60/d; +L_0x2b85f50/d .functor OR 1, L_0x2b85cf0, L_0x2b85e60, C4<0>, C4<0>; +L_0x2b85f50 .delay (20000,20000,20000) L_0x2b85f50/d; +v0x26400b0_0 .net "A", 0 0, L_0x2b85030; 1 drivers +v0x2643610_0 .net "AandB", 0 0, L_0x2b85cf0; 1 drivers +v0x2643690_0 .net "AddSubSLTSum", 0 0, L_0x2b85c00; 1 drivers +v0x2643360_0 .net "AxorB", 0 0, L_0x2b85b10; 1 drivers +v0x26433e0_0 .net "B", 0 0, L_0x2b850d0; 1 drivers +v0x26423d0_0 .net "BornB", 0 0, L_0x2b855c0; 1 drivers +v0x2642120_0 .net "CINandAxorB", 0 0, L_0x2b85e60; 1 drivers +v0x26421a0_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x2442bb0_0 .net *"_s3", 0 0, L_0x2b85890; 1 drivers +v0x2442c30_0 .net *"_s5", 0 0, L_0x2b85a70; 1 drivers +v0x2794b90_0 .net "carryin", 0 0, L_0x2b85200; 1 drivers +v0x2794c10_0 .net "carryout", 0 0, L_0x2b85f50; 1 drivers +v0x1d47970_0 .net "nB", 0 0, L_0x2b84ae0; 1 drivers +v0x1d479f0_0 .net "nCmd2", 0 0, L_0x2b857f0; 1 drivers +v0x221ed40_0 .net "subtract", 0 0, L_0x2b85930; 1 drivers +L_0x2b85750 .part v0x2960210_0, 0, 1; +L_0x2b85890 .part v0x2960210_0, 2, 1; +L_0x2b85a70 .part v0x2960210_0, 0, 1; +S_0x26402e0 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x2641910; + .timescale -9 -12; +L_0x2b84cb0/d .functor NOT 1, L_0x2b85750, C4<0>, C4<0>, C4<0>; +L_0x2b84cb0 .delay (10000,10000,10000) L_0x2b84cb0/d; +L_0x2b85420/d .functor AND 1, L_0x2b850d0, L_0x2b84cb0, C4<1>, C4<1>; +L_0x2b85420 .delay (20000,20000,20000) L_0x2b85420/d; +L_0x2b854d0/d .functor AND 1, L_0x2b84ae0, L_0x2b85750, C4<1>, C4<1>; +L_0x2b854d0 .delay (20000,20000,20000) L_0x2b854d0/d; +L_0x2b855c0/d .functor OR 1, L_0x2b85420, L_0x2b854d0, C4<0>, C4<0>; +L_0x2b855c0 .delay (20000,20000,20000) L_0x2b855c0/d; +v0x2704790_0 .net "S", 0 0, L_0x2b85750; 1 drivers +v0x26f45d0_0 .alias "in0", 0 0, v0x26433e0_0; +v0x26eaa20_0 .alias "in1", 0 0, v0x1d47970_0; +v0x2704090_0 .net "nS", 0 0, L_0x2b84cb0; 1 drivers +v0x26e7200_0 .net "out0", 0 0, L_0x2b85420; 1 drivers +v0x2735090_0 .net "out1", 0 0, L_0x2b854d0; 1 drivers +v0x2640030_0 .alias "outfinal", 0 0, v0x26423d0_0; +S_0x2641bc0 .scope module, "setSLTres2" "TwoInMux" 3 335, 3 109, S_0x263c5b0; + .timescale -9 -12; +L_0x2b852a0/d .functor NOT 1, L_0x2ba8dd0, C4<0>, C4<0>, C4<0>; +L_0x2b852a0 .delay (10000,10000,10000) L_0x2b852a0/d; +L_0x2b85340/d .functor AND 1, L_0x2b86a50, L_0x2b852a0, C4<1>, C4<1>; +L_0x2b85340 .delay (20000,20000,20000) L_0x2b85340/d; +L_0x2b867d0/d .functor AND 1, C4<0>, L_0x2ba8dd0, C4<1>, C4<1>; +L_0x2b867d0 .delay (20000,20000,20000) L_0x2b867d0/d; +L_0x2b86870/d .functor OR 1, L_0x2b85340, L_0x2b867d0, C4<0>, C4<0>; +L_0x2b86870 .delay (20000,20000,20000) L_0x2b86870/d; +v0x278dd10_0 .alias "S", 0 0, v0x240f880_0; +v0x275cb00_0 .net "in0", 0 0, L_0x2b86a50; 1 drivers +v0x2750740_0 .net "in1", 0 0, C4<0>; 1 drivers +v0x2741670_0 .net "nS", 0 0, L_0x2b852a0; 1 drivers +v0x2730ad0_0 .net "out0", 0 0, L_0x2b85340; 1 drivers +v0x2719bd0_0 .net "out1", 0 0, L_0x2b867d0; 1 drivers +v0x2710240_0 .net "outfinal", 0 0, L_0x2b86870; 1 drivers +S_0x263c300 .scope module, "setSLTres3" "TwoInMux" 3 336, 3 109, S_0x263c5b0; + .timescale -9 -12; +L_0x2b86300/d .functor NOT 1, L_0x2ba8dd0, C4<0>, C4<0>, C4<0>; +L_0x2b86300 .delay (10000,10000,10000) L_0x2b86300/d; +L_0x2b863f0/d .functor AND 1, L_0x2b87060, L_0x2b86300, C4<1>, C4<1>; +L_0x2b863f0 .delay (20000,20000,20000) L_0x2b863f0/d; +L_0x2b86500/d .functor AND 1, L_0x2b86b40, L_0x2ba8dd0, C4<1>, C4<1>; +L_0x2b86500 .delay (20000,20000,20000) L_0x2b86500/d; +L_0x2b865a0/d .functor OR 1, L_0x2b863f0, L_0x2b86500, C4<0>, C4<0>; +L_0x2b865a0 .delay (20000,20000,20000) L_0x2b865a0/d; +v0x2641e70_0 .alias "S", 0 0, v0x240f880_0; +v0x2641ef0_0 .net "in0", 0 0, L_0x2b87060; 1 drivers +v0x2636810_0 .net "in1", 0 0, L_0x2b86b40; 1 drivers +v0x26075f0_0 .net "nS", 0 0, L_0x2b86300; 1 drivers +v0x25f6ae0_0 .net "out0", 0 0, L_0x2b863f0; 1 drivers +v0x25c78c0_0 .net "out1", 0 0, L_0x2b86500; 1 drivers +v0x25b2b10_0 .net "outfinal", 0 0, L_0x2b865a0; 1 drivers +S_0x262aaf0 .scope generate, "sltbits[16]" "sltbits[16]" 3 332, 3 332, S_0x2753240; + .timescale -9 -12; +P_0x2317748 .param/l "i" 3 332, +C4<010000>; +S_0x26318e0 .scope module, "attempt" "MiddleAddSubSLT" 3 334, 3 189, S_0x262aaf0; + .timescale -9 -12; +L_0x2b86c30/d .functor NOT 1, L_0x2b873d0, C4<0>, C4<0>, C4<0>; +L_0x2b86c30 .delay (10000,10000,10000) L_0x2b86c30/d; +L_0x2b87940/d .functor NOT 1, L_0x2b879e0, C4<0>, C4<0>, C4<0>; +L_0x2b87940 .delay (10000,10000,10000) L_0x2b87940/d; +L_0x2b87a80/d .functor AND 1, L_0x2b87bc0, L_0x2b87940, C4<1>, C4<1>; +L_0x2b87a80 .delay (20000,20000,20000) L_0x2b87a80/d; +L_0x2b87c60/d .functor XOR 1, L_0x2b87330, L_0x2b87710, C4<0>, C4<0>; +L_0x2b87c60 .delay (40000,40000,40000) L_0x2b87c60/d; +L_0x2b87d50/d .functor XOR 1, L_0x2b87c60, L_0x2b87500, C4<0>, C4<0>; +L_0x2b87d50 .delay (40000,40000,40000) L_0x2b87d50/d; +L_0x2b87e40/d .functor AND 1, L_0x2b87330, L_0x2b87710, C4<1>, C4<1>; +L_0x2b87e40 .delay (20000,20000,20000) L_0x2b87e40/d; +L_0x2b87fb0/d .functor AND 1, L_0x2b87c60, L_0x2b87500, C4<1>, C4<1>; +L_0x2b87fb0 .delay (20000,20000,20000) L_0x2b87fb0/d; +L_0x2b880a0/d .functor OR 1, L_0x2b87e40, L_0x2b87fb0, C4<0>, C4<0>; +L_0x2b880a0 .delay (20000,20000,20000) L_0x2b880a0/d; +v0x2634490_0 .net "A", 0 0, L_0x2b87330; 1 drivers +v0x26379b0_0 .net "AandB", 0 0, L_0x2b87e40; 1 drivers +v0x2637a30_0 .net "AddSubSLTSum", 0 0, L_0x2b87d50; 1 drivers +v0x2637700_0 .net "AxorB", 0 0, L_0x2b87c60; 1 drivers +v0x2637780_0 .net "B", 0 0, L_0x2b873d0; 1 drivers +v0x2636790_0 .net "BornB", 0 0, L_0x2b87710; 1 drivers +v0x26364e0_0 .net "CINandAxorB", 0 0, L_0x2b87fb0; 1 drivers +v0x2636560_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x263a4c0_0 .net *"_s3", 0 0, L_0x2b879e0; 1 drivers +v0x263a540_0 .net *"_s5", 0 0, L_0x2b87bc0; 1 drivers +v0x263a210_0 .net "carryin", 0 0, L_0x2b87500; 1 drivers +v0x263a290_0 .net "carryout", 0 0, L_0x2b880a0; 1 drivers +v0x263d7d0_0 .net "nB", 0 0, L_0x2b86c30; 1 drivers +v0x263d850_0 .net "nCmd2", 0 0, L_0x2b87940; 1 drivers +v0x263d5a0_0 .net "subtract", 0 0, L_0x2b87a80; 1 drivers +L_0x2b878a0 .part v0x2960210_0, 0, 1; +L_0x2b879e0 .part v0x2960210_0, 2, 1; +L_0x2b87bc0 .part v0x2960210_0, 0, 1; +S_0x2630950 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x26318e0; + .timescale -9 -12; +L_0x2b86e00/d .functor NOT 1, L_0x2b878a0, C4<0>, C4<0>, C4<0>; +L_0x2b86e00 .delay (10000,10000,10000) L_0x2b86e00/d; +L_0x2b86ee0/d .functor AND 1, L_0x2b873d0, L_0x2b86e00, C4<1>, C4<1>; +L_0x2b86ee0 .delay (20000,20000,20000) L_0x2b86ee0/d; +L_0x2b86ff0/d .functor AND 1, L_0x2b86c30, L_0x2b878a0, C4<1>, C4<1>; +L_0x2b86ff0 .delay (20000,20000,20000) L_0x2b86ff0/d; +L_0x2b87710/d .functor OR 1, L_0x2b86ee0, L_0x2b86ff0, C4<0>, C4<0>; +L_0x2b87710 .delay (20000,20000,20000) L_0x2b87710/d; +v0x2631c30_0 .net "S", 0 0, L_0x2b878a0; 1 drivers +v0x26306a0_0 .alias "in0", 0 0, v0x2637780_0; +v0x2630740_0 .alias "in1", 0 0, v0x263d7d0_0; +v0x262dda0_0 .net "nS", 0 0, L_0x2b86e00; 1 drivers +v0x262de40_0 .net "out0", 0 0, L_0x2b86ee0; 1 drivers +v0x26346a0_0 .net "out1", 0 0, L_0x2b86ff0; 1 drivers +v0x26343f0_0 .alias "outfinal", 0 0, v0x2636790_0; +S_0x262e860 .scope module, "setSLTres2" "TwoInMux" 3 335, 3 109, S_0x262aaf0; + .timescale -9 -12; +L_0x2b875a0/d .functor NOT 1, L_0x2ba8dd0, C4<0>, C4<0>, C4<0>; +L_0x2b875a0 .delay (10000,10000,10000) L_0x2b875a0/d; +L_0x2b77380/d .functor AND 1, L_0x2b882d0, L_0x2b875a0, C4<1>, C4<1>; +L_0x2b77380 .delay (20000,20000,20000) L_0x2b77380/d; +L_0x2b77450/d .functor AND 1, C4<0>, L_0x2ba8dd0, C4<1>, C4<1>; +L_0x2b77450 .delay (20000,20000,20000) L_0x2b77450/d; +L_0x2b774f0/d .functor OR 1, L_0x2b77380, L_0x2b77450, C4<0>, C4<0>; +L_0x2b774f0 .delay (20000,20000,20000) L_0x2b774f0/d; +v0x262ff30_0 .alias "S", 0 0, v0x240f880_0; +v0x262e5b0_0 .net "in0", 0 0, L_0x2b882d0; 1 drivers +v0x262e650_0 .net "in1", 0 0, C4<0>; 1 drivers +v0x262e300_0 .net "nS", 0 0, L_0x2b875a0; 1 drivers +v0x262e3a0_0 .net "out0", 0 0, L_0x2b77380; 1 drivers +v0x262e050_0 .net "out1", 0 0, L_0x2b77450; 1 drivers +v0x2631b90_0 .net "outfinal", 0 0, L_0x2b774f0; 1 drivers +S_0x262a840 .scope module, "setSLTres3" "TwoInMux" 3 336, 3 109, S_0x262aaf0; + .timescale -9 -12; +L_0x2b77a10/d .functor NOT 1, L_0x2ba8dd0, C4<0>, C4<0>, C4<0>; +L_0x2b77a10 .delay (10000,10000,10000) L_0x2b77a10/d; +L_0x2b77b00/d .functor AND 1, L_0x2b88d80, L_0x2b77a10, C4<1>, C4<1>; +L_0x2b77b00 .delay (20000,20000,20000) L_0x2b77b00/d; +L_0x2b84580/d .functor AND 1, L_0x2b88e70, L_0x2ba8dd0, C4<1>, C4<1>; +L_0x2b84580 .delay (20000,20000,20000) L_0x2b84580/d; +L_0x2b84620/d .functor OR 1, L_0x2b77b00, L_0x2b84580, C4<0>, C4<0>; +L_0x2b84620 .delay (20000,20000,20000) L_0x2b84620/d; +v0x262bb00_0 .alias "S", 0 0, v0x240f880_0; +v0x2627f40_0 .net "in0", 0 0, L_0x2b88d80; 1 drivers +v0x2627fc0_0 .net "in1", 0 0, L_0x2b88e70; 1 drivers +v0x26303f0_0 .net "nS", 0 0, L_0x2b77a10; 1 drivers +v0x2630470_0 .net "out0", 0 0, L_0x2b77b00; 1 drivers +v0x2630140_0 .net "out1", 0 0, L_0x2b84580; 1 drivers +v0x262fe90_0 .net "outfinal", 0 0, L_0x2b84620; 1 drivers +S_0x2620090 .scope generate, "sltbits[17]" "sltbits[17]" 3 332, 3 332, S_0x2753240; + .timescale -9 -12; +P_0x2309348 .param/l "i" 3 332, +C4<010001>; +S_0x2622390 .scope module, "attempt" "MiddleAddSubSLT" 3 334, 3 189, S_0x2620090; + .timescale -9 -12; +L_0x2b88f60/d .functor NOT 1, L_0x2b897d0, C4<0>, C4<0>, C4<0>; +L_0x2b88f60 .delay (10000,10000,10000) L_0x2b88f60/d; +L_0x2b89eb0/d .functor NOT 1, L_0x2b89f50, C4<0>, C4<0>, C4<0>; +L_0x2b89eb0 .delay (10000,10000,10000) L_0x2b89eb0/d; +L_0x2b89ff0/d .functor AND 1, L_0x2b8a130, L_0x2b89eb0, C4<1>, C4<1>; +L_0x2b89ff0 .delay (20000,20000,20000) L_0x2b89ff0/d; +L_0x2b8a1d0/d .functor XOR 1, L_0x2b89730, L_0x2b89c80, C4<0>, C4<0>; +L_0x2b8a1d0 .delay (40000,40000,40000) L_0x2b8a1d0/d; +L_0x2b8a2c0/d .functor XOR 1, L_0x2b8a1d0, L_0x2b89900, C4<0>, C4<0>; +L_0x2b8a2c0 .delay (40000,40000,40000) L_0x2b8a2c0/d; +L_0x2b8a3b0/d .functor AND 1, L_0x2b89730, L_0x2b89c80, C4<1>, C4<1>; +L_0x2b8a3b0 .delay (20000,20000,20000) L_0x2b8a3b0/d; +L_0x2b8a520/d .functor AND 1, L_0x2b8a1d0, L_0x2b89900, C4<1>, C4<1>; +L_0x2b8a520 .delay (20000,20000,20000) L_0x2b8a520/d; +L_0x2b8a610/d .functor OR 1, L_0x2b8a3b0, L_0x2b8a520, C4<0>, C4<0>; +L_0x2b8a610 .delay (20000,20000,20000) L_0x2b8a610/d; +v0x262a590_0 .net "A", 0 0, L_0x2b89730; 1 drivers +v0x262a2e0_0 .net "AandB", 0 0, L_0x2b8a3b0; 1 drivers +v0x262a380_0 .net "AddSubSLTSum", 0 0, L_0x2b8a2c0; 1 drivers +v0x262a030_0 .net "AxorB", 0 0, L_0x2b8a1d0; 1 drivers +v0x262a0b0_0 .net "B", 0 0, L_0x2b897d0; 1 drivers +v0x2628a00_0 .net "BornB", 0 0, L_0x2b89c80; 1 drivers +v0x2628a80_0 .net "CINandAxorB", 0 0, L_0x2b8a520; 1 drivers +v0x2628750_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x26287d0_0 .net *"_s3", 0 0, L_0x2b89f50; 1 drivers +v0x26284a0_0 .net *"_s5", 0 0, L_0x2b8a130; 1 drivers +v0x2628520_0 .net "carryin", 0 0, L_0x2b89900; 1 drivers +v0x26281f0_0 .net "carryout", 0 0, L_0x2b8a610; 1 drivers +v0x2628270_0 .net "nB", 0 0, L_0x2b88f60; 1 drivers +v0x262bd30_0 .net "nCmd2", 0 0, L_0x2b89eb0; 1 drivers +v0x262ba80_0 .net "subtract", 0 0, L_0x2b89ff0; 1 drivers +L_0x2b89e10 .part v0x2960210_0, 0, 1; +L_0x2b89f50 .part v0x2960210_0, 2, 1; +L_0x2b8a130 .part v0x2960210_0, 0, 1; +S_0x2625ed0 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x2622390; + .timescale -9 -12; +L_0x2b89130/d .functor NOT 1, L_0x2b89e10, C4<0>, C4<0>, C4<0>; +L_0x2b89130 .delay (10000,10000,10000) L_0x2b89130/d; +L_0x2b891f0/d .functor AND 1, L_0x2b897d0, L_0x2b89130, C4<1>, C4<1>; +L_0x2b891f0 .delay (20000,20000,20000) L_0x2b891f0/d; +L_0x2b89bd0/d .functor AND 1, L_0x2b88f60, L_0x2b89e10, C4<1>, C4<1>; +L_0x2b89bd0 .delay (20000,20000,20000) L_0x2b89bd0/d; +L_0x2b89c80/d .functor OR 1, L_0x2b891f0, L_0x2b89bd0, C4<0>, C4<0>; +L_0x2b89c80 .delay (20000,20000,20000) L_0x2b89c80/d; +v0x2625c20_0 .net "S", 0 0, L_0x2b89e10; 1 drivers +v0x2624c90_0 .alias "in0", 0 0, v0x262a0b0_0; +v0x2624d30_0 .alias "in1", 0 0, v0x2628270_0; +v0x26249e0_0 .net "nS", 0 0, L_0x2b89130; 1 drivers +v0x2624a60_0 .net "out0", 0 0, L_0x2b891f0; 1 drivers +v0x26220e0_0 .net "out1", 0 0, L_0x2b89bd0; 1 drivers +v0x2622180_0 .alias "outfinal", 0 0, v0x2628a00_0; +S_0x26241d0 .scope module, "setSLTres2" "TwoInMux" 3 335, 3 109, S_0x2620090; + .timescale -9 -12; +L_0x2b899a0/d .functor NOT 1, L_0x2ba8dd0, C4<0>, C4<0>, C4<0>; +L_0x2b899a0 .delay (10000,10000,10000) L_0x2b899a0/d; +L_0x2b89a20/d .functor AND 1, L_0x2b681c0, L_0x2b899a0, C4<1>, C4<1>; +L_0x2b89a20 .delay (20000,20000,20000) L_0x2b89a20/d; +L_0x2b89b30/d .functor AND 1, C4<0>, L_0x2ba8dd0, C4<1>, C4<1>; +L_0x2b89b30 .delay (20000,20000,20000) L_0x2b89b30/d; +L_0x2b67fc0/d .functor OR 1, L_0x2b89a20, L_0x2b89b30, C4<0>, C4<0>; +L_0x2b67fc0 .delay (20000,20000,20000) L_0x2b67fc0/d; +v0x2624520_0 .alias "S", 0 0, v0x240f880_0; +v0x2622ba0_0 .net "in0", 0 0, L_0x2b681c0; 1 drivers +v0x2622c40_0 .net "in1", 0 0, C4<0>; 1 drivers +v0x26228f0_0 .net "nS", 0 0, L_0x2b899a0; 1 drivers +v0x2622990_0 .net "out0", 0 0, L_0x2b89a20; 1 drivers +v0x2622640_0 .net "out1", 0 0, L_0x2b89b30; 1 drivers +v0x26226e0_0 .net "outfinal", 0 0, L_0x2b67fc0; 1 drivers +S_0x261fde0 .scope module, "setSLTres3" "TwoInMux" 3 336, 3 109, S_0x2620090; + .timescale -9 -12; +L_0x2b68340/d .functor NOT 1, L_0x2ba8dd0, C4<0>, C4<0>, C4<0>; +L_0x2b68340 .delay (10000,10000,10000) L_0x2b68340/d; +L_0x2b68470/d .functor AND 1, L_0x2b8a9d0, L_0x2b68340, C4<1>, C4<1>; +L_0x2b68470 .delay (20000,20000,20000) L_0x2b68470/d; +L_0x2b68580/d .functor AND 1, L_0x2b8aac0, L_0x2ba8dd0, C4<1>, C4<1>; +L_0x2b68580 .delay (20000,20000,20000) L_0x2b68580/d; +L_0x2b68620/d .functor OR 1, L_0x2b68470, L_0x2b68580, C4<0>, C4<0>; +L_0x2b68620 .delay (20000,20000,20000) L_0x2b68620/d; +v0x261cb50_0 .alias "S", 0 0, v0x240f880_0; +v0x261ee70_0 .net "in0", 0 0, L_0x2b8a9d0; 1 drivers +v0x261eef0_0 .net "in1", 0 0, L_0x2b8aac0; 1 drivers +v0x261ebc0_0 .net "nS", 0 0, L_0x2b68340; 1 drivers +v0x261ec40_0 .net "out0", 0 0, L_0x2b68470; 1 drivers +v0x2624730_0 .net "out1", 0 0, L_0x2b68580; 1 drivers +v0x2624480_0 .net "outfinal", 0 0, L_0x2b68620; 1 drivers +S_0x260b030 .scope generate, "sltbits[18]" "sltbits[18]" 3 332, 3 332, S_0x2753240; + .timescale -9 -12; +P_0x23000c8 .param/l "i" 3 332, +C4<010010>; +S_0x2610930 .scope module, "attempt" "MiddleAddSubSLT" 3 334, 3 189, S_0x260b030; + .timescale -9 -12; +L_0x2b8abb0/d .functor NOT 1, L_0x2b8c180, C4<0>, C4<0>, C4<0>; +L_0x2b8abb0 .delay (10000,10000,10000) L_0x2b8abb0/d; +L_0x2b8c850/d .functor NOT 1, L_0x2b8c8f0, C4<0>, C4<0>, C4<0>; +L_0x2b8c850 .delay (10000,10000,10000) L_0x2b8c850/d; +L_0x2b8c990/d .functor AND 1, L_0x2b8cad0, L_0x2b8c850, C4<1>, C4<1>; +L_0x2b8c990 .delay (20000,20000,20000) L_0x2b8c990/d; +L_0x2b8cb70/d .functor XOR 1, L_0x2b8c0e0, L_0x2b8c620, C4<0>, C4<0>; +L_0x2b8cb70 .delay (40000,40000,40000) L_0x2b8cb70/d; +L_0x2b8cc60/d .functor XOR 1, L_0x2b8cb70, L_0x2b8c2b0, C4<0>, C4<0>; +L_0x2b8cc60 .delay (40000,40000,40000) L_0x2b8cc60/d; +L_0x2b8cd50/d .functor AND 1, L_0x2b8c0e0, L_0x2b8c620, C4<1>, C4<1>; +L_0x2b8cd50 .delay (20000,20000,20000) L_0x2b8cd50/d; +L_0x2b8cec0/d .functor AND 1, L_0x2b8cb70, L_0x2b8c2b0, C4<1>, C4<1>; +L_0x2b8cec0 .delay (20000,20000,20000) L_0x2b8cec0/d; +L_0x2b8cfb0/d .functor OR 1, L_0x2b8cd50, L_0x2b8cec0, C4<0>, C4<0>; +L_0x2b8cfb0 .delay (20000,20000,20000) L_0x2b8cfb0/d; +v0x2610720_0 .net "A", 0 0, L_0x2b8c0e0; 1 drivers +v0x2616f60_0 .net "AandB", 0 0, L_0x2b8cd50; 1 drivers +v0x2617000_0 .net "AddSubSLTSum", 0 0, L_0x2b8cc60; 1 drivers +v0x2616cb0_0 .net "AxorB", 0 0, L_0x2b8cb70; 1 drivers +v0x2616d30_0 .net "B", 0 0, L_0x2b8c180; 1 drivers +v0x261a270_0 .net "BornB", 0 0, L_0x2b8c620; 1 drivers +v0x261a2f0_0 .net "CINandAxorB", 0 0, L_0x2b8cec0; 1 drivers +v0x2619fc0_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x261a040_0 .net *"_s3", 0 0, L_0x2b8c8f0; 1 drivers +v0x2619050_0 .net *"_s5", 0 0, L_0x2b8cad0; 1 drivers +v0x26190d0_0 .net "carryin", 0 0, L_0x2b8c2b0; 1 drivers +v0x2618da0_0 .net "carryout", 0 0, L_0x2b8cfb0; 1 drivers +v0x2618e20_0 .net "nB", 0 0, L_0x2b8abb0; 1 drivers +v0x261cd80_0 .net "nCmd2", 0 0, L_0x2b8c850; 1 drivers +v0x261cad0_0 .net "subtract", 0 0, L_0x2b8c990; 1 drivers +L_0x2b8c7b0 .part v0x2960210_0, 0, 1; +L_0x2b8c8f0 .part v0x2960210_0, 2, 1; +L_0x2b8cad0 .part v0x2960210_0, 0, 1; +S_0x2614450 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x2610930; + .timescale -9 -12; +L_0x2b8ad80/d .functor NOT 1, L_0x2b8c7b0, C4<0>, C4<0>, C4<0>; +L_0x2b8ad80 .delay (10000,10000,10000) L_0x2b8ad80/d; +L_0x2b8ae60/d .functor AND 1, L_0x2b8c180, L_0x2b8ad80, C4<1>, C4<1>; +L_0x2b8ae60 .delay (20000,20000,20000) L_0x2b8ae60/d; +L_0x2b8c530/d .functor AND 1, L_0x2b8abb0, L_0x2b8c7b0, C4<1>, C4<1>; +L_0x2b8c530 .delay (20000,20000,20000) L_0x2b8c530/d; +L_0x2b8c620/d .functor OR 1, L_0x2b8ae60, L_0x2b8c530, C4<0>, C4<0>; +L_0x2b8c620 .delay (20000,20000,20000) L_0x2b8c620/d; +v0x2610c80_0 .net "S", 0 0, L_0x2b8c7b0; 1 drivers +v0x26141a0_0 .alias "in0", 0 0, v0x2616d30_0; +v0x2614240_0 .alias "in1", 0 0, v0x2618e20_0; +v0x2613230_0 .net "nS", 0 0, L_0x2b8ad80; 1 drivers +v0x26132b0_0 .net "out0", 0 0, L_0x2b8ae60; 1 drivers +v0x2612f80_0 .net "out1", 0 0, L_0x2b8c530; 1 drivers +v0x2610680_0 .alias "outfinal", 0 0, v0x261a270_0; +S_0x260d120 .scope module, "setSLTres2" "TwoInMux" 3 335, 3 109, S_0x260b030; + .timescale -9 -12; +L_0x2b8c350/d .functor NOT 1, L_0x2ba8dd0, C4<0>, C4<0>, C4<0>; +L_0x2b8c350 .delay (10000,10000,10000) L_0x2b8c350/d; +L_0x2b8c3f0/d .functor AND 1, L_0x2b8d1e0, L_0x2b8c350, C4<1>, C4<1>; +L_0x2b8c3f0 .delay (20000,20000,20000) L_0x2b8c3f0/d; +L_0x2b8d840/d .functor AND 1, C4<0>, L_0x2ba8dd0, C4<1>, C4<1>; +L_0x2b8d840 .delay (20000,20000,20000) L_0x2b8d840/d; +L_0x2b8d8e0/d .functor OR 1, L_0x2b8c3f0, L_0x2b8d840, C4<0>, C4<0>; +L_0x2b8d8e0 .delay (20000,20000,20000) L_0x2b8d8e0/d; +v0x260d470_0 .alias "S", 0 0, v0x240f880_0; +v0x260a820_0 .net "in0", 0 0, L_0x2b8d1e0; 1 drivers +v0x260a8c0_0 .net "in1", 0 0, C4<0>; 1 drivers +v0x2611140_0 .net "nS", 0 0, L_0x2b8c350; 1 drivers +v0x26111e0_0 .net "out0", 0 0, L_0x2b8c3f0; 1 drivers +v0x2610e90_0 .net "out1", 0 0, L_0x2b8d840; 1 drivers +v0x2610be0_0 .net "outfinal", 0 0, L_0x2b8d8e0; 1 drivers +S_0x260ad80 .scope module, "setSLTres3" "TwoInMux" 3 336, 3 109, S_0x260b030; + .timescale -9 -12; +L_0x2b8d620/d .functor NOT 1, L_0x2ba8dd0, C4<0>, C4<0>, C4<0>; +L_0x2b8d620 .delay (10000,10000,10000) L_0x2b8d620/d; +L_0x2b8d730/d .functor AND 1, L_0x2b8dac0, L_0x2b8d620, C4<1>, C4<1>; +L_0x2b8d730 .delay (20000,20000,20000) L_0x2b8d730/d; +L_0x2b89340/d .functor AND 1, L_0x2b8dbb0, L_0x2ba8dd0, C4<1>, C4<1>; +L_0x2b89340 .delay (20000,20000,20000) L_0x2b89340/d; +L_0x2b893e0/d .functor OR 1, L_0x2b8d730, L_0x2b89340, C4<0>, C4<0>; +L_0x2b893e0 .delay (20000,20000,20000) L_0x2b893e0/d; +v0x260b360_0 .alias "S", 0 0, v0x240f880_0; +v0x260aad0_0 .net "in0", 0 0, L_0x2b8dac0; 1 drivers +v0x260ab50_0 .net "in1", 0 0, L_0x2b8dbb0; 1 drivers +v0x260e610_0 .net "nS", 0 0, L_0x2b8d620; 1 drivers +v0x260e690_0 .net "out0", 0 0, L_0x2b8d730; 1 drivers +v0x260e360_0 .net "out1", 0 0, L_0x2b89340; 1 drivers +v0x260d3d0_0 .net "outfinal", 0 0, L_0x2b893e0; 1 drivers +S_0x25fc880 .scope generate, "sltbits[19]" "sltbits[19]" 3 332, 3 332, S_0x2753240; + .timescale -9 -12; +P_0x22d5328 .param/l "i" 3 332, +C4<010011>; +S_0x2606d60 .scope module, "attempt" "MiddleAddSubSLT" 3 334, 3 189, S_0x25fc880; + .timescale -9 -12; +L_0x2b8dca0/d .functor NOT 1, L_0x2b8e310, C4<0>, C4<0>, C4<0>; +L_0x2b8dca0 .delay (10000,10000,10000) L_0x2b8dca0/d; +L_0x2b8ea00/d .functor NOT 1, L_0x2b8eaa0, C4<0>, C4<0>, C4<0>; +L_0x2b8ea00 .delay (10000,10000,10000) L_0x2b8ea00/d; +L_0x2b8eb40/d .functor AND 1, L_0x2b8ec80, L_0x2b8ea00, C4<1>, C4<1>; +L_0x2b8eb40 .delay (20000,20000,20000) L_0x2b8eb40/d; +L_0x2b8ed20/d .functor XOR 1, L_0x2b8e270, L_0x2b8e810, C4<0>, C4<0>; +L_0x2b8ed20 .delay (40000,40000,40000) L_0x2b8ed20/d; +L_0x2b8ee10/d .functor XOR 1, L_0x2b8ed20, L_0x2b8e440, C4<0>, C4<0>; +L_0x2b8ee10 .delay (40000,40000,40000) L_0x2b8ee10/d; +L_0x2b8ef00/d .functor AND 1, L_0x2b8e270, L_0x2b8e810, C4<1>, C4<1>; +L_0x2b8ef00 .delay (20000,20000,20000) L_0x2b8ef00/d; +L_0x2b8f070/d .functor AND 1, L_0x2b8ed20, L_0x2b8e440, C4<1>, C4<1>; +L_0x2b8f070 .delay (20000,20000,20000) L_0x2b8f070/d; +L_0x2b8f160/d .functor OR 1, L_0x2b8ef00, L_0x2b8f070, C4<0>, C4<0>; +L_0x2b8f160 .delay (20000,20000,20000) L_0x2b8f160/d; +v0x2604c70_0 .net "A", 0 0, L_0x2b8e270; 1 drivers +v0x26087b0_0 .net "AandB", 0 0, L_0x2b8ef00; 1 drivers +v0x2608850_0 .net "AddSubSLTSum", 0 0, L_0x2b8ee10; 1 drivers +v0x2608500_0 .net "AxorB", 0 0, L_0x2b8ed20; 1 drivers +v0x2608580_0 .net "B", 0 0, L_0x2b8e310; 1 drivers +v0x2607570_0 .net "BornB", 0 0, L_0x2b8e810; 1 drivers +v0x26072c0_0 .net "CINandAxorB", 0 0, L_0x2b8f070; 1 drivers +v0x2607340_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x26049c0_0 .net *"_s3", 0 0, L_0x2b8eaa0; 1 drivers +v0x2604a40_0 .net *"_s5", 0 0, L_0x2b8ec80; 1 drivers +v0x260ce70_0 .net "carryin", 0 0, L_0x2b8e440; 1 drivers +v0x260cef0_0 .net "carryout", 0 0, L_0x2b8f160; 1 drivers +v0x260cbc0_0 .net "nB", 0 0, L_0x2b8dca0; 1 drivers +v0x260c910_0 .net "nCmd2", 0 0, L_0x2b8ea00; 1 drivers +v0x260b2e0_0 .net "subtract", 0 0, L_0x2b8eb40; 1 drivers +L_0x2b8e960 .part v0x2960210_0, 0, 1; +L_0x2b8eaa0 .part v0x2960210_0, 2, 1; +L_0x2b8ec80 .part v0x2960210_0, 0, 1; +S_0x2606ab0 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x2606d60; + .timescale -9 -12; +L_0x2b8de70/d .functor NOT 1, L_0x2b8e960, C4<0>, C4<0>, C4<0>; +L_0x2b8de70 .delay (10000,10000,10000) L_0x2b8de70/d; +L_0x2b8df50/d .functor AND 1, L_0x2b8e310, L_0x2b8de70, C4<1>, C4<1>; +L_0x2b8df50 .delay (20000,20000,20000) L_0x2b8df50/d; +L_0x2b8e080/d .functor AND 1, L_0x2b8dca0, L_0x2b8e960, C4<1>, C4<1>; +L_0x2b8e080 .delay (20000,20000,20000) L_0x2b8e080/d; +L_0x2b8e810/d .functor OR 1, L_0x2b8df50, L_0x2b8e080, C4<0>, C4<0>; +L_0x2b8e810 .delay (20000,20000,20000) L_0x2b8e810/d; +v0x26070b0_0 .net "S", 0 0, L_0x2b8e960; 1 drivers +v0x2605480_0 .alias "in0", 0 0, v0x2608580_0; +v0x2605520_0 .alias "in1", 0 0, v0x260cbc0_0; +v0x26051d0_0 .net "nS", 0 0, L_0x2b8de70; 1 drivers +v0x2605270_0 .net "out0", 0 0, L_0x2b8df50; 1 drivers +v0x2604f20_0 .net "out1", 0 0, L_0x2b8e080; 1 drivers +v0x2604fc0_0 .alias "outfinal", 0 0, v0x2607570_0; +S_0x26026a0 .scope module, "setSLTres2" "TwoInMux" 3 335, 3 109, S_0x25fc880; + .timescale -9 -12; +L_0x2b8e4e0/d .functor NOT 1, L_0x2ba8dd0, C4<0>, C4<0>, C4<0>; +L_0x2b8e4e0 .delay (10000,10000,10000) L_0x2b8e4e0/d; +L_0x2b8e580/d .functor AND 1, L_0x2b8fc70, L_0x2b8e4e0, C4<1>, C4<1>; +L_0x2b8e580 .delay (20000,20000,20000) L_0x2b8e580/d; +L_0x2b8e690/d .functor AND 1, C4<0>, L_0x2ba8dd0, C4<1>, C4<1>; +L_0x2b8e690 .delay (20000,20000,20000) L_0x2b8e690/d; +L_0x2b8e730/d .functor OR 1, L_0x2b8e580, L_0x2b8e690, C4<0>, C4<0>; +L_0x2b8e730 .delay (20000,20000,20000) L_0x2b8e730/d; +v0x26029d0_0 .alias "S", 0 0, v0x240f880_0; +v0x26023f0_0 .net "in0", 0 0, L_0x2b8fc70; 1 drivers +v0x2602470_0 .net "in1", 0 0, C4<0>; 1 drivers +v0x2601730_0 .net "nS", 0 0, L_0x2b8e4e0; 1 drivers +v0x26017b0_0 .net "out0", 0 0, L_0x2b8e580; 1 drivers +v0x2601480_0 .net "out1", 0 0, L_0x2b8e690; 1 drivers +v0x2607010_0 .net "outfinal", 0 0, L_0x2b8e730; 1 drivers +S_0x25fb910 .scope module, "setSLTres3" "TwoInMux" 3 336, 3 109, S_0x25fc880; + .timescale -9 -12; +L_0x2b8f510/d .functor NOT 1, L_0x2ba8dd0, C4<0>, C4<0>, C4<0>; +L_0x2b8f510 .delay (10000,10000,10000) L_0x2b8f510/d; +L_0x2b8f620/d .functor AND 1, L_0x2b8f9b0, L_0x2b8f510, C4<1>, C4<1>; +L_0x2b8f620 .delay (20000,20000,20000) L_0x2b8f620/d; +L_0x2b8f730/d .functor AND 1, L_0x2b903f0, L_0x2ba8dd0, C4<1>, C4<1>; +L_0x2b8f730 .delay (20000,20000,20000) L_0x2b8f730/d; +L_0x2b8f7d0/d .functor OR 1, L_0x2b8f620, L_0x2b8f730, C4<0>, C4<0>; +L_0x2b8f7d0 .delay (20000,20000,20000) L_0x2b8f7d0/d; +v0x25fb660_0 .alias "S", 0 0, v0x240f880_0; +v0x25fb6e0_0 .net "in0", 0 0, L_0x2b8f9b0; 1 drivers +v0x25ff640_0 .net "in1", 0 0, L_0x2b903f0; 1 drivers +v0x25ff6c0_0 .net "nS", 0 0, L_0x2b8f510; 1 drivers +v0x25ff390_0 .net "out0", 0 0, L_0x2b8f620; 1 drivers +v0x25ff410_0 .net "out1", 0 0, L_0x2b8f730; 1 drivers +v0x2602950_0 .net "outfinal", 0 0, L_0x2b8f7d0; 1 drivers +S_0x25eadc0 .scope generate, "sltbits[20]" "sltbits[20]" 3 332, 3 332, S_0x2753240; + .timescale -9 -12; +P_0x22afe78 .param/l "i" 3 332, +C4<010100>; +S_0x25f0ed0 .scope module, "attempt" "MiddleAddSubSLT" 3 334, 3 189, S_0x25eadc0; + .timescale -9 -12; +L_0x2b90490/d .functor NOT 1, L_0x2b8ffe0, C4<0>, C4<0>, C4<0>; +L_0x2b90490 .delay (10000,10000,10000) L_0x2b90490/d; +L_0x2b90ad0/d .functor NOT 1, L_0x2b90b70, C4<0>, C4<0>, C4<0>; +L_0x2b90ad0 .delay (10000,10000,10000) L_0x2b90ad0/d; +L_0x2b90c10/d .functor AND 1, L_0x2b90d50, L_0x2b90ad0, C4<1>, C4<1>; +L_0x2b90c10 .delay (20000,20000,20000) L_0x2b90c10/d; +L_0x2b90df0/d .functor XOR 1, L_0x2b8ff40, L_0x2b908a0, C4<0>, C4<0>; +L_0x2b90df0 .delay (40000,40000,40000) L_0x2b90df0/d; +L_0x2b90ee0/d .functor XOR 1, L_0x2b90df0, L_0x2b90110, C4<0>, C4<0>; +L_0x2b90ee0 .delay (40000,40000,40000) L_0x2b90ee0/d; +L_0x2b90fd0/d .functor AND 1, L_0x2b8ff40, L_0x2b908a0, C4<1>, C4<1>; +L_0x2b90fd0 .delay (20000,20000,20000) L_0x2b90fd0/d; +L_0x2b91140/d .functor AND 1, L_0x2b90df0, L_0x2b90110, C4<1>, C4<1>; +L_0x2b91140 .delay (20000,20000,20000) L_0x2b91140/d; +L_0x2b91230/d .functor OR 1, L_0x2b90fd0, L_0x2b91140, C4<0>, C4<0>; +L_0x2b91230 .delay (20000,20000,20000) L_0x2b91230/d; +v0x25f3aa0_0 .net "A", 0 0, L_0x2b8ff40; 1 drivers +v0x25f3750_0 .net "AandB", 0 0, L_0x2b90fd0; 1 drivers +v0x25f37d0_0 .net "AddSubSLTSum", 0 0, L_0x2b90ee0; 1 drivers +v0x25f6d10_0 .net "AxorB", 0 0, L_0x2b90df0; 1 drivers +v0x25f6d90_0 .net "B", 0 0, L_0x2b8ffe0; 1 drivers +v0x25f6a60_0 .net "BornB", 0 0, L_0x2b908a0; 1 drivers +v0x25f5af0_0 .net "CINandAxorB", 0 0, L_0x2b91140; 1 drivers +v0x25f5b70_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x25f5840_0 .net *"_s3", 0 0, L_0x2b90b70; 1 drivers +v0x25f58c0_0 .net *"_s5", 0 0, L_0x2b90d50; 1 drivers +v0x25f9820_0 .net "carryin", 0 0, L_0x2b90110; 1 drivers +v0x25f98a0_0 .net "carryout", 0 0, L_0x2b91230; 1 drivers +v0x25f9570_0 .net "nB", 0 0, L_0x2b90490; 1 drivers +v0x25f95f0_0 .net "nCmd2", 0 0, L_0x2b90ad0; 1 drivers +v0x25fcbb0_0 .net "subtract", 0 0, L_0x2b90c10; 1 drivers +L_0x2b90a30 .part v0x2960210_0, 0, 1; +L_0x2b90b70 .part v0x2960210_0, 2, 1; +L_0x2b90d50 .part v0x2960210_0, 0, 1; +S_0x25f0c20 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x25f0ed0; + .timescale -9 -12; +L_0x2b90620/d .functor NOT 1, L_0x2b90a30, C4<0>, C4<0>, C4<0>; +L_0x2b90620 .delay (10000,10000,10000) L_0x2b90620/d; +L_0x2b906c0/d .functor AND 1, L_0x2b8ffe0, L_0x2b90620, C4<1>, C4<1>; +L_0x2b906c0 .delay (20000,20000,20000) L_0x2b906c0/d; +L_0x2b907b0/d .functor AND 1, L_0x2b90490, L_0x2b90a30, C4<1>, C4<1>; +L_0x2b907b0 .delay (20000,20000,20000) L_0x2b907b0/d; +L_0x2b908a0/d .functor OR 1, L_0x2b906c0, L_0x2b907b0, C4<0>, C4<0>; +L_0x2b908a0 .delay (20000,20000,20000) L_0x2b908a0/d; +v0x25ed430_0 .net "S", 0 0, L_0x2b90a30; 1 drivers +v0x25efc90_0 .alias "in0", 0 0, v0x25f6d90_0; +v0x25efd30_0 .alias "in1", 0 0, v0x25f9570_0; +v0x25ef9e0_0 .net "nS", 0 0, L_0x2b90620; 1 drivers +v0x25efa80_0 .net "out0", 0 0, L_0x2b906c0; 1 drivers +v0x25ed0e0_0 .net "out1", 0 0, L_0x2b907b0; 1 drivers +v0x25f3a00_0 .alias "outfinal", 0 0, v0x25f6a60_0; +S_0x25ef1d0 .scope module, "setSLTres2" "TwoInMux" 3 335, 3 109, S_0x25eadc0; + .timescale -9 -12; +L_0x2b901b0/d .functor NOT 1, L_0x2ba8dd0, C4<0>, C4<0>, C4<0>; +L_0x2b901b0 .delay (10000,10000,10000) L_0x2b901b0/d; +L_0x2b90250/d .functor AND 1, L_0x2b91460, L_0x2b901b0, C4<1>, C4<1>; +L_0x2b90250 .delay (20000,20000,20000) L_0x2b90250/d; +L_0x2b90360/d .functor AND 1, C4<0>, L_0x2ba8dd0, C4<1>, C4<1>; +L_0x2b90360 .delay (20000,20000,20000) L_0x2b90360/d; +L_0x2b91b60/d .functor OR 1, L_0x2b90250, L_0x2b90360, C4<0>, C4<0>; +L_0x2b91b60 .delay (20000,20000,20000) L_0x2b91b60/d; +v0x25ef520_0 .alias "S", 0 0, v0x240f880_0; +v0x25edba0_0 .net "in0", 0 0, L_0x2b91460; 1 drivers +v0x25edc40_0 .net "in1", 0 0, C4<0>; 1 drivers +v0x25ed8f0_0 .net "nS", 0 0, L_0x2b901b0; 1 drivers +v0x25ed990_0 .net "out0", 0 0, L_0x2b90250; 1 drivers +v0x25ed640_0 .net "out1", 0 0, L_0x2b90360; 1 drivers +v0x25ed390_0 .net "outfinal", 0 0, L_0x2b91b60; 1 drivers +S_0x25e9e30 .scope module, "setSLTres3" "TwoInMux" 3 336, 3 109, S_0x25eadc0; + .timescale -9 -12; +L_0x2b918b0/d .functor NOT 1, L_0x2ba8dd0, C4<0>, C4<0>, C4<0>; +L_0x2b918b0 .delay (10000,10000,10000) L_0x2b918b0/d; +L_0x2b919c0/d .functor AND 1, L_0x2b92420, L_0x2b918b0, C4<1>, C4<1>; +L_0x2b919c0 .delay (20000,20000,20000) L_0x2b919c0/d; +L_0x2b8d360/d .functor AND 1, L_0x2b924c0, L_0x2ba8dd0, C4<1>, C4<1>; +L_0x2b8d360 .delay (20000,20000,20000) L_0x2b8d360/d; +L_0x2b8d400/d .functor OR 1, L_0x2b919c0, L_0x2b8d360, C4<0>, C4<0>; +L_0x2b8d400 .delay (20000,20000,20000) L_0x2b8d400/d; +v0x25eb0f0_0 .alias "S", 0 0, v0x240f880_0; +v0x25e9b80_0 .net "in0", 0 0, L_0x2b92420; 1 drivers +v0x25e9c00_0 .net "in1", 0 0, L_0x2b924c0; 1 drivers +v0x25e7280_0 .net "nS", 0 0, L_0x2b918b0; 1 drivers +v0x25e7300_0 .net "out0", 0 0, L_0x2b919c0; 1 drivers +v0x25ef730_0 .net "out1", 0 0, L_0x2b8d360; 1 drivers +v0x25ef480_0 .net "outfinal", 0 0, L_0x2b8d400; 1 drivers +S_0x25d80e0 .scope generate, "sltbits[21]" "sltbits[21]" 3 332, 3 332, S_0x2753240; + .timescale -9 -12; +P_0x228a9a8 .param/l "i" 3 332, +C4<010101>; +S_0x25e1ee0 .scope module, "attempt" "MiddleAddSubSLT" 3 334, 3 189, S_0x25d80e0; + .timescale -9 -12; +L_0x2b91d40/d .functor NOT 1, L_0x2b92740, C4<0>, C4<0>, C4<0>; +L_0x2b91d40 .delay (10000,10000,10000) L_0x2b91d40/d; +L_0x2b92ca0/d .functor NOT 1, L_0x2b92d40, C4<0>, C4<0>, C4<0>; +L_0x2b92ca0 .delay (10000,10000,10000) L_0x2b92ca0/d; +L_0x2b92de0/d .functor AND 1, L_0x2b92f20, L_0x2b92ca0, C4<1>, C4<1>; +L_0x2b92de0 .delay (20000,20000,20000) L_0x2b92de0/d; +L_0x2b92fc0/d .functor XOR 1, L_0x2b926a0, L_0x2b921b0, C4<0>, C4<0>; +L_0x2b92fc0 .delay (40000,40000,40000) L_0x2b92fc0/d; +L_0x2b930b0/d .functor XOR 1, L_0x2b92fc0, L_0x2b92870, C4<0>, C4<0>; +L_0x2b930b0 .delay (40000,40000,40000) L_0x2b930b0/d; +L_0x2b931a0/d .functor AND 1, L_0x2b926a0, L_0x2b921b0, C4<1>, C4<1>; +L_0x2b931a0 .delay (20000,20000,20000) L_0x2b931a0/d; +L_0x2b93310/d .functor AND 1, L_0x2b92fc0, L_0x2b92870, C4<1>, C4<1>; +L_0x2b93310 .delay (20000,20000,20000) L_0x2b93310/d; +L_0x2b93400/d .functor OR 1, L_0x2b931a0, L_0x2b93310, C4<0>, C4<0>; +L_0x2b93400 .delay (20000,20000,20000) L_0x2b93400/d; +v0x25e3d20_0 .net "A", 0 0, L_0x2b926a0; 1 drivers +v0x25e98d0_0 .net "AandB", 0 0, L_0x2b931a0; 1 drivers +v0x25e9970_0 .net "AddSubSLTSum", 0 0, L_0x2b930b0; 1 drivers +v0x25e9620_0 .net "AxorB", 0 0, L_0x2b92fc0; 1 drivers +v0x25e96a0_0 .net "B", 0 0, L_0x2b92740; 1 drivers +v0x25e9370_0 .net "BornB", 0 0, L_0x2b921b0; 1 drivers +v0x25e93f0_0 .net "CINandAxorB", 0 0, L_0x2b93310; 1 drivers +v0x25e7d40_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x25e7dc0_0 .net *"_s3", 0 0, L_0x2b92d40; 1 drivers +v0x25e7a90_0 .net *"_s5", 0 0, L_0x2b92f20; 1 drivers +v0x25e7b10_0 .net "carryin", 0 0, L_0x2b92870; 1 drivers +v0x25e77e0_0 .net "carryout", 0 0, L_0x2b93400; 1 drivers +v0x25e7860_0 .net "nB", 0 0, L_0x2b91d40; 1 drivers +v0x25e7530_0 .net "nCmd2", 0 0, L_0x2b92ca0; 1 drivers +v0x25eb070_0 .net "subtract", 0 0, L_0x2b92de0; 1 drivers +L_0x2b92380 .part v0x2960210_0, 0, 1; +L_0x2b92d40 .part v0x2960210_0, 2, 1; +L_0x2b92f20 .part v0x2960210_0, 0, 1; +S_0x25e1c30 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x25e1ee0; + .timescale -9 -12; +L_0x2b91ed0/d .functor NOT 1, L_0x2b92380, C4<0>, C4<0>, C4<0>; +L_0x2b91ed0 .delay (10000,10000,10000) L_0x2b91ed0/d; +L_0x2b91f90/d .functor AND 1, L_0x2b92740, L_0x2b91ed0, C4<1>, C4<1>; +L_0x2b91f90 .delay (20000,20000,20000) L_0x2b91f90/d; +L_0x2b920a0/d .functor AND 1, L_0x2b91d40, L_0x2b92380, C4<1>, C4<1>; +L_0x2b920a0 .delay (20000,20000,20000) L_0x2b920a0/d; +L_0x2b921b0/d .functor OR 1, L_0x2b91f90, L_0x2b920a0, C4<0>, C4<0>; +L_0x2b921b0 .delay (20000,20000,20000) L_0x2b921b0/d; +v0x25e1980_0 .net "S", 0 0, L_0x2b92380; 1 drivers +v0x25e5210_0 .alias "in0", 0 0, v0x25e96a0_0; +v0x25e52b0_0 .alias "in1", 0 0, v0x25e7860_0; +v0x25e4f60_0 .net "nS", 0 0, L_0x2b91ed0; 1 drivers +v0x25e4fe0_0 .net "out0", 0 0, L_0x2b91f90; 1 drivers +v0x25e3fd0_0 .net "out1", 0 0, L_0x2b920a0; 1 drivers +v0x25e4070_0 .alias "outfinal", 0 0, v0x25e9370_0; +S_0x25ddf00 .scope module, "setSLTres2" "TwoInMux" 3 335, 3 109, S_0x25d80e0; + .timescale -9 -12; +L_0x2b92910/d .functor NOT 1, L_0x2ba8dd0, C4<0>, C4<0>, C4<0>; +L_0x2b92910 .delay (10000,10000,10000) L_0x2b92910/d; +L_0x2b929b0/d .functor AND 1, L_0x2b93f30, L_0x2b92910, C4<1>, C4<1>; +L_0x2b929b0 .delay (20000,20000,20000) L_0x2b929b0/d; +L_0x2b92ac0/d .functor AND 1, C4<0>, L_0x2ba8dd0, C4<1>, C4<1>; +L_0x2b92ac0 .delay (20000,20000,20000) L_0x2b92ac0/d; +L_0x2b92b60/d .functor OR 1, L_0x2b929b0, L_0x2b92ac0, C4<0>, C4<0>; +L_0x2b92b60 .delay (20000,20000,20000) L_0x2b92b60/d; +v0x25de250_0 .alias "S", 0 0, v0x240f880_0; +v0x25e3a70_0 .net "in0", 0 0, L_0x2b93f30; 1 drivers +v0x25e3b10_0 .net "in1", 0 0, C4<0>; 1 drivers +v0x25e37c0_0 .net "nS", 0 0, L_0x2b92910; 1 drivers +v0x25e3860_0 .net "out0", 0 0, L_0x2b929b0; 1 drivers +v0x25e3510_0 .net "out1", 0 0, L_0x2b92ac0; 1 drivers +v0x25e35b0_0 .net "outfinal", 0 0, L_0x2b92b60; 1 drivers +S_0x25dc0c0 .scope module, "setSLTres3" "TwoInMux" 3 336, 3 109, S_0x25d80e0; + .timescale -9 -12; +L_0x2b937b0/d .functor NOT 1, L_0x2ba8dd0, C4<0>, C4<0>, C4<0>; +L_0x2b937b0 .delay (10000,10000,10000) L_0x2b937b0/d; +L_0x2b938c0/d .functor AND 1, L_0x2b93c50, L_0x2b937b0, C4<1>, C4<1>; +L_0x2b938c0 .delay (20000,20000,20000) L_0x2b938c0/d; +L_0x2b939d0/d .functor AND 1, L_0x2b93d40, L_0x2ba8dd0, C4<1>, C4<1>; +L_0x2b939d0 .delay (20000,20000,20000) L_0x2b939d0/d; +L_0x2b93a70/d .functor OR 1, L_0x2b938c0, L_0x2b939d0, C4<0>, C4<0>; +L_0x2b93a70 .delay (20000,20000,20000) L_0x2b93a70/d; +v0x25d8410_0 .alias "S", 0 0, v0x240f880_0; +v0x25dbe10_0 .net "in0", 0 0, L_0x2b93c50; 1 drivers +v0x25dbe90_0 .net "in1", 0 0, L_0x2b93d40; 1 drivers +v0x25df3d0_0 .net "nS", 0 0, L_0x2b937b0; 1 drivers +v0x25df450_0 .net "out0", 0 0, L_0x2b938c0; 1 drivers +v0x25df120_0 .net "out1", 0 0, L_0x2b939d0; 1 drivers +v0x25de1b0_0 .net "outfinal", 0 0, L_0x2b93a70; 1 drivers +S_0x25ca620 .scope generate, "sltbits[22]" "sltbits[22]" 3 332, 3 332, S_0x2753240; + .timescale -9 -12; +P_0x227baf8 .param/l "i" 3 332, +C4<010110>; +S_0x25d0480 .scope module, "attempt" "MiddleAddSubSLT" 3 334, 3 189, S_0x25ca620; + .timescale -9 -12; +L_0x2b94760/d .functor NOT 1, L_0x2b942a0, C4<0>, C4<0>, C4<0>; +L_0x2b94760 .delay (10000,10000,10000) L_0x2b94760/d; +L_0x2b94da0/d .functor NOT 1, L_0x2b94e40, C4<0>, C4<0>, C4<0>; +L_0x2b94da0 .delay (10000,10000,10000) L_0x2b94da0/d; +L_0x2b94ee0/d .functor AND 1, L_0x2b95020, L_0x2b94da0, C4<1>, C4<1>; +L_0x2b94ee0 .delay (20000,20000,20000) L_0x2b94ee0/d; +L_0x2b950c0/d .functor XOR 1, L_0x2b94200, L_0x2b94b70, C4<0>, C4<0>; +L_0x2b950c0 .delay (40000,40000,40000) L_0x2b950c0/d; +L_0x2b951b0/d .functor XOR 1, L_0x2b950c0, L_0x2b943d0, C4<0>, C4<0>; +L_0x2b951b0 .delay (40000,40000,40000) L_0x2b951b0/d; +L_0x2b952a0/d .functor AND 1, L_0x2b94200, L_0x2b94b70, C4<1>, C4<1>; +L_0x2b952a0 .delay (20000,20000,20000) L_0x2b952a0/d; +L_0x2b95410/d .functor AND 1, L_0x2b950c0, L_0x2b943d0, C4<1>, C4<1>; +L_0x2b95410 .delay (20000,20000,20000) L_0x2b95410/d; +L_0x2b95500/d .functor OR 1, L_0x2b952a0, L_0x2b95410, C4<0>, C4<0>; +L_0x2b95500 .delay (20000,20000,20000) L_0x2b95500/d; +v0x25d3580_0 .net "A", 0 0, L_0x2b94200; 1 drivers +v0x25d2570_0 .net "AandB", 0 0, L_0x2b952a0; 1 drivers +v0x25d2610_0 .net "AddSubSLTSum", 0 0, L_0x2b951b0; 1 drivers +v0x25d22c0_0 .net "AxorB", 0 0, L_0x2b950c0; 1 drivers +v0x25d2340_0 .net "B", 0 0, L_0x2b942a0; 1 drivers +v0x25cf9c0_0 .net "BornB", 0 0, L_0x2b94b70; 1 drivers +v0x25cfa40_0 .net "CINandAxorB", 0 0, L_0x2b95410; 1 drivers +v0x25d62a0_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x25d6320_0 .net *"_s3", 0 0, L_0x2b94e40; 1 drivers +v0x25d5ff0_0 .net *"_s5", 0 0, L_0x2b95020; 1 drivers +v0x25d6070_0 .net "carryin", 0 0, L_0x2b943d0; 1 drivers +v0x25d95b0_0 .net "carryout", 0 0, L_0x2b95500; 1 drivers +v0x25d9630_0 .net "nB", 0 0, L_0x2b94760; 1 drivers +v0x25d9300_0 .net "nCmd2", 0 0, L_0x2b94da0; 1 drivers +v0x25d8390_0 .net "subtract", 0 0, L_0x2b94ee0; 1 drivers +L_0x2b94d00 .part v0x2960210_0, 0, 1; +L_0x2b94e40 .part v0x2960210_0, 2, 1; +L_0x2b95020 .part v0x2960210_0, 0, 1; +S_0x25d01d0 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x25d0480; + .timescale -9 -12; +L_0x2b948f0/d .functor NOT 1, L_0x2b94d00, C4<0>, C4<0>, C4<0>; +L_0x2b948f0 .delay (10000,10000,10000) L_0x2b948f0/d; +L_0x2b94990/d .functor AND 1, L_0x2b942a0, L_0x2b948f0, C4<1>, C4<1>; +L_0x2b94990 .delay (20000,20000,20000) L_0x2b94990/d; +L_0x2b94a80/d .functor AND 1, L_0x2b94760, L_0x2b94d00, C4<1>, C4<1>; +L_0x2b94a80 .delay (20000,20000,20000) L_0x2b94a80/d; +L_0x2b94b70/d .functor OR 1, L_0x2b94990, L_0x2b94a80, C4<0>, C4<0>; +L_0x2b94b70 .delay (20000,20000,20000) L_0x2b94b70/d; +v0x25d1b50_0 .net "S", 0 0, L_0x2b94d00; 1 drivers +v0x25cff20_0 .alias "in0", 0 0, v0x25d2340_0; +v0x25cffc0_0 .alias "in1", 0 0, v0x25d9630_0; +v0x25cfc70_0 .net "nS", 0 0, L_0x2b948f0; 1 drivers +v0x25cfcf0_0 .net "out0", 0 0, L_0x2b94990; 1 drivers +v0x25d3790_0 .net "out1", 0 0, L_0x2b94a80; 1 drivers +v0x25d34e0_0 .alias "outfinal", 0 0, v0x25cf9c0_0; +S_0x25cc710 .scope module, "setSLTres2" "TwoInMux" 3 335, 3 109, S_0x25ca620; + .timescale -9 -12; +L_0x2b94470/d .functor NOT 1, L_0x2ba8dd0, C4<0>, C4<0>, C4<0>; +L_0x2b94470 .delay (10000,10000,10000) L_0x2b94470/d; +L_0x2b94510/d .functor AND 1, L_0x2b7e890, L_0x2b94470, C4<1>, C4<1>; +L_0x2b94510 .delay (20000,20000,20000) L_0x2b94510/d; +L_0x2b94620/d .functor AND 1, C4<0>, L_0x2ba8dd0, C4<1>, C4<1>; +L_0x2b94620 .delay (20000,20000,20000) L_0x2b94620/d; +L_0x2b946e0/d .functor OR 1, L_0x2b94510, L_0x2b94620, C4<0>, C4<0>; +L_0x2b946e0 .delay (20000,20000,20000) L_0x2b946e0/d; +v0x25cd740_0 .alias "S", 0 0, v0x240f880_0; +v0x25cc460_0 .net "in0", 0 0, L_0x2b7e890; 1 drivers +v0x25cc500_0 .net "in1", 0 0, C4<0>; 1 drivers +v0x25c9b60_0 .net "nS", 0 0, L_0x2b94470; 1 drivers +v0x25c9c00_0 .net "out0", 0 0, L_0x2b94510; 1 drivers +v0x25d1d60_0 .net "out1", 0 0, L_0x2b94620; 1 drivers +v0x25d1ab0_0 .net "outfinal", 0 0, L_0x2b946e0; 1 drivers +S_0x25ca370 .scope module, "setSLTres3" "TwoInMux" 3 336, 3 109, S_0x25ca620; + .timescale -9 -12; +L_0x2b95a10/d .functor NOT 1, L_0x2ba8dd0, C4<0>, C4<0>, C4<0>; +L_0x2b95a10 .delay (10000,10000,10000) L_0x2b95a10/d; +L_0x2b95b20/d .functor AND 1, L_0x2b7eab0, L_0x2b95a10, C4<1>, C4<1>; +L_0x2b95b20 .delay (20000,20000,20000) L_0x2b95b20/d; +L_0x2b95c30/d .functor AND 1, L_0x2b7eba0, L_0x2ba8dd0, C4<1>, C4<1>; +L_0x2b95c30 .delay (20000,20000,20000) L_0x2b95c30/d; +L_0x2b95cd0/d .functor OR 1, L_0x2b95b20, L_0x2b95c30, C4<0>, C4<0>; +L_0x2b95cd0 .delay (20000,20000,20000) L_0x2b95cd0/d; +v0x25cbcd0_0 .alias "S", 0 0, v0x240f880_0; +v0x25ca0c0_0 .net "in0", 0 0, L_0x2b7eab0; 1 drivers +v0x25ca140_0 .net "in1", 0 0, L_0x2b7eba0; 1 drivers +v0x25c9e10_0 .net "nS", 0 0, L_0x2b95a10; 1 drivers +v0x25c9e90_0 .net "out0", 0 0, L_0x2b95b20; 1 drivers +v0x25cd950_0 .net "out1", 0 0, L_0x2b95c30; 1 drivers +v0x25cd6a0_0 .net "outfinal", 0 0, L_0x2b95cd0; 1 drivers +S_0x25b88b0 .scope generate, "sltbits[23]" "sltbits[23]" 3 332, 3 332, S_0x2753240; + .timescale -9 -12; +P_0x22a3298 .param/l "i" 3 332, +C4<010111>; +S_0x25c6350 .scope module, "attempt" "MiddleAddSubSLT" 3 334, 3 189, S_0x25b88b0; + .timescale -9 -12; +L_0x2b95e10/d .functor NOT 1, L_0x2b969c0, C4<0>, C4<0>, C4<0>; +L_0x2b95e10 .delay (10000,10000,10000) L_0x2b95e10/d; +L_0x2b97380/d .functor NOT 1, L_0x2b97420, C4<0>, C4<0>, C4<0>; +L_0x2b97380 .delay (10000,10000,10000) L_0x2b97380/d; +L_0x2b974c0/d .functor AND 1, L_0x2b97600, L_0x2b97380, C4<1>, C4<1>; +L_0x2b974c0 .delay (20000,20000,20000) L_0x2b974c0/d; +L_0x2b976a0/d .functor XOR 1, L_0x2b96920, L_0x2b97150, C4<0>, C4<0>; +L_0x2b976a0 .delay (40000,40000,40000) L_0x2b976a0/d; +L_0x2b97790/d .functor XOR 1, L_0x2b976a0, L_0x2b96af0, C4<0>, C4<0>; +L_0x2b97790 .delay (40000,40000,40000) L_0x2b97790/d; +L_0x2b97880/d .functor AND 1, L_0x2b96920, L_0x2b97150, C4<1>, C4<1>; +L_0x2b97880 .delay (20000,20000,20000) L_0x2b97880/d; +L_0x2b979f0/d .functor AND 1, L_0x2b976a0, L_0x2b96af0, C4<1>, C4<1>; +L_0x2b979f0 .delay (20000,20000,20000) L_0x2b979f0/d; +L_0x2b97ae0/d .functor OR 1, L_0x2b97880, L_0x2b979f0, C4<0>, C4<0>; +L_0x2b97ae0 .delay (20000,20000,20000) L_0x2b97ae0/d; +v0x25c4260_0 .net "A", 0 0, L_0x2b96920; 1 drivers +v0x25c3fb0_0 .net "AandB", 0 0, L_0x2b97880; 1 drivers +v0x25c4050_0 .net "AddSubSLTSum", 0 0, L_0x2b97790; 1 drivers +v0x25c7af0_0 .net "AxorB", 0 0, L_0x2b976a0; 1 drivers +v0x25c7b70_0 .net "B", 0 0, L_0x2b969c0; 1 drivers +v0x25c7840_0 .net "BornB", 0 0, L_0x2b97150; 1 drivers +v0x25c68b0_0 .net "CINandAxorB", 0 0, L_0x2b979f0; 1 drivers +v0x25c6930_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x25c6600_0 .net *"_s3", 0 0, L_0x2b97420; 1 drivers +v0x25c6680_0 .net *"_s5", 0 0, L_0x2b97600; 1 drivers +v0x25c3d00_0 .net "carryin", 0 0, L_0x2b96af0; 1 drivers +v0x25c3d80_0 .net "carryout", 0 0, L_0x2b97ae0; 1 drivers +v0x25cc1b0_0 .net "nB", 0 0, L_0x2b95e10; 1 drivers +v0x25cbf00_0 .net "nCmd2", 0 0, L_0x2b97380; 1 drivers +v0x25cbc50_0 .net "subtract", 0 0, L_0x2b974c0; 1 drivers +L_0x2b972e0 .part v0x2960210_0, 0, 1; +L_0x2b97420 .part v0x2960210_0, 2, 1; +L_0x2b97600 .part v0x2960210_0, 0, 1; +S_0x25c60a0 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x25c6350; + .timescale -9 -12; +L_0x2b91750/d .functor NOT 1, L_0x2b972e0, C4<0>, C4<0>, C4<0>; +L_0x2b91750 .delay (10000,10000,10000) L_0x2b91750/d; +L_0x2b91830/d .functor AND 1, L_0x2b969c0, L_0x2b91750, C4<1>, C4<1>; +L_0x2b91830 .delay (20000,20000,20000) L_0x2b91830/d; +L_0x2b97060/d .functor AND 1, L_0x2b95e10, L_0x2b972e0, C4<1>, C4<1>; +L_0x2b97060 .delay (20000,20000,20000) L_0x2b97060/d; +L_0x2b97150/d .functor OR 1, L_0x2b91830, L_0x2b97060, C4<0>, C4<0>; +L_0x2b97150 .delay (20000,20000,20000) L_0x2b97150/d; +v0x25c0860_0 .net "S", 0 0, L_0x2b972e0; 1 drivers +v0x25c5df0_0 .alias "in0", 0 0, v0x25c7b70_0; +v0x25c5e90_0 .alias "in1", 0 0, v0x25cc1b0_0; +v0x25c47c0_0 .net "nS", 0 0, L_0x2b91750; 1 drivers +v0x25c4860_0 .net "out0", 0 0, L_0x2b91830; 1 drivers +v0x25c4510_0 .net "out1", 0 0, L_0x2b97060; 1 drivers +v0x25c45b0_0 .alias "outfinal", 0 0, v0x25c7840_0; +S_0x25be6d0 .scope module, "setSLTres2" "TwoInMux" 3 335, 3 109, S_0x25b88b0; + .timescale -9 -12; +L_0x2b96b90/d .functor NOT 1, L_0x2ba8dd0, C4<0>, C4<0>, C4<0>; +L_0x2b96b90 .delay (10000,10000,10000) L_0x2b96b90/d; +L_0x2b96c30/d .functor AND 1, L_0x2b985d0, L_0x2b96b90, C4<1>, C4<1>; +L_0x2b96c30 .delay (20000,20000,20000) L_0x2b96c30/d; +L_0x2b96d40/d .functor AND 1, C4<0>, L_0x2ba8dd0, C4<1>, C4<1>; +L_0x2b96d40 .delay (20000,20000,20000) L_0x2b96d40/d; +L_0x2b96de0/d .functor OR 1, L_0x2b96c30, L_0x2b96d40, C4<0>, C4<0>; +L_0x2b96de0 .delay (20000,20000,20000) L_0x2b96de0/d; +v0x25bea00_0 .alias "S", 0 0, v0x240f880_0; +v0x25c1c90_0 .net "in0", 0 0, L_0x2b985d0; 1 drivers +v0x25c1d10_0 .net "in1", 0 0, C4<0>; 1 drivers +v0x25c19e0_0 .net "nS", 0 0, L_0x2b96b90; 1 drivers +v0x25c1a60_0 .net "out0", 0 0, L_0x2b96c30; 1 drivers +v0x25c0a70_0 .net "out1", 0 0, L_0x2b96d40; 1 drivers +v0x25c07c0_0 .net "outfinal", 0 0, L_0x2b96de0; 1 drivers +S_0x25bbe70 .scope module, "setSLTres3" "TwoInMux" 3 336, 3 109, S_0x25b88b0; + .timescale -9 -12; +L_0x2b97e90/d .functor NOT 1, L_0x2ba8dd0, C4<0>, C4<0>, C4<0>; +L_0x2b97e90 .delay (10000,10000,10000) L_0x2b97e90/d; +L_0x2b97fa0/d .functor AND 1, L_0x2b98330, L_0x2b97e90, C4<1>, C4<1>; +L_0x2b97fa0 .delay (20000,20000,20000) L_0x2b97fa0/d; +L_0x2b980b0/d .functor AND 1, L_0x2b98420, L_0x2ba8dd0, C4<1>, C4<1>; +L_0x2b980b0 .delay (20000,20000,20000) L_0x2b980b0/d; +L_0x2b98150/d .functor OR 1, L_0x2b97fa0, L_0x2b980b0, C4<0>, C4<0>; +L_0x2b98150 .delay (20000,20000,20000) L_0x2b98150/d; +v0x25bbbc0_0 .alias "S", 0 0, v0x240f880_0; +v0x25bbc40_0 .net "in0", 0 0, L_0x2b98330; 1 drivers +v0x25bac50_0 .net "in1", 0 0, L_0x2b98420; 1 drivers +v0x25bacd0_0 .net "nS", 0 0, L_0x2b97e90; 1 drivers +v0x25ba9a0_0 .net "out0", 0 0, L_0x2b97fa0; 1 drivers +v0x25baa20_0 .net "out1", 0 0, L_0x2b980b0; 1 drivers +v0x25be980_0 .net "outfinal", 0 0, L_0x2b98150; 1 drivers +S_0x25a6870 .scope generate, "sltbits[24]" "sltbits[24]" 3 332, 3 332, S_0x2753240; + .timescale -9 -12; +P_0x2244a28 .param/l "i" 3 332, +C4<011000>; +S_0x25ac980 .scope module, "attempt" "MiddleAddSubSLT" 3 334, 3 189, S_0x25a6870; + .timescale -9 -12; +L_0x2b98510/d .functor NOT 1, L_0x2b98940, C4<0>, C4<0>, C4<0>; +L_0x2b98510 .delay (10000,10000,10000) L_0x2b98510/d; +L_0x2b99440/d .functor NOT 1, L_0x2b994e0, C4<0>, C4<0>, C4<0>; +L_0x2b99440 .delay (10000,10000,10000) L_0x2b99440/d; +L_0x2b99580/d .functor AND 1, L_0x2b996c0, L_0x2b99440, C4<1>, C4<1>; +L_0x2b99580 .delay (20000,20000,20000) L_0x2b99580/d; +L_0x2b99760/d .functor XOR 1, L_0x2b988a0, L_0x2b99210, C4<0>, C4<0>; +L_0x2b99760 .delay (40000,40000,40000) L_0x2b99760/d; +L_0x2b99850/d .functor XOR 1, L_0x2b99760, L_0x2b98a70, C4<0>, C4<0>; +L_0x2b99850 .delay (40000,40000,40000) L_0x2b99850/d; +L_0x2b99940/d .functor AND 1, L_0x2b988a0, L_0x2b99210, C4<1>, C4<1>; +L_0x2b99940 .delay (20000,20000,20000) L_0x2b99940/d; +L_0x2b99ab0/d .functor AND 1, L_0x2b99760, L_0x2b98a70, C4<1>, C4<1>; +L_0x2b99ab0 .delay (20000,20000,20000) L_0x2b99ab0/d; +L_0x2b99ba0/d .functor OR 1, L_0x2b99940, L_0x2b99ab0, C4<0>, C4<0>; +L_0x2b99ba0 .delay (20000,20000,20000) L_0x2b99ba0/d; +v0x25aedc0_0 .net "A", 0 0, L_0x2b988a0; 1 drivers +v0x25ac420_0 .net "AandB", 0 0, L_0x2b99940; 1 drivers +v0x25ac4a0_0 .net "AddSubSLTSum", 0 0, L_0x2b99850; 1 drivers +v0x25b2d40_0 .net "AxorB", 0 0, L_0x2b99760; 1 drivers +v0x25b2dc0_0 .net "B", 0 0, L_0x2b98940; 1 drivers +v0x25b2a90_0 .net "BornB", 0 0, L_0x2b99210; 1 drivers +v0x25b6050_0 .net "CINandAxorB", 0 0, L_0x2b99ab0; 1 drivers +v0x25b60d0_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x25b5da0_0 .net *"_s3", 0 0, L_0x2b994e0; 1 drivers +v0x25b5e20_0 .net *"_s5", 0 0, L_0x2b996c0; 1 drivers +v0x25b4e30_0 .net "carryin", 0 0, L_0x2b98a70; 1 drivers +v0x25b4eb0_0 .net "carryout", 0 0, L_0x2b99ba0; 1 drivers +v0x25b4b80_0 .net "nB", 0 0, L_0x2b98510; 1 drivers +v0x25b4c00_0 .net "nCmd2", 0 0, L_0x2b99440; 1 drivers +v0x25b8be0_0 .net "subtract", 0 0, L_0x2b99580; 1 drivers +L_0x2b993a0 .part v0x2960210_0, 0, 1; +L_0x2b994e0 .part v0x2960210_0, 2, 1; +L_0x2b996c0 .part v0x2960210_0, 0, 1; +S_0x25ac6d0 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x25ac980; + .timescale -9 -12; +L_0x2b98f90/d .functor NOT 1, L_0x2b993a0, C4<0>, C4<0>, C4<0>; +L_0x2b98f90 .delay (10000,10000,10000) L_0x2b98f90/d; +L_0x2b99030/d .functor AND 1, L_0x2b98940, L_0x2b98f90, C4<1>, C4<1>; +L_0x2b99030 .delay (20000,20000,20000) L_0x2b99030/d; +L_0x2b99120/d .functor AND 1, L_0x2b98510, L_0x2b993a0, C4<1>, C4<1>; +L_0x2b99120 .delay (20000,20000,20000) L_0x2b99120/d; +L_0x2b99210/d .functor OR 1, L_0x2b99030, L_0x2b99120, C4<0>, C4<0>; +L_0x2b99210 .delay (20000,20000,20000) L_0x2b99210/d; +v0x25accd0_0 .net "S", 0 0, L_0x2b993a0; 1 drivers +v0x25b0210_0 .alias "in0", 0 0, v0x25b2dc0_0; +v0x25b02b0_0 .alias "in1", 0 0, v0x25b4b80_0; +v0x25aff60_0 .net "nS", 0 0, L_0x2b98f90; 1 drivers +v0x25b0000_0 .net "out0", 0 0, L_0x2b99030; 1 drivers +v0x25aefd0_0 .net "out1", 0 0, L_0x2b99120; 1 drivers +v0x25aed20_0 .alias "outfinal", 0 0, v0x25b2a90_0; +S_0x25aea70 .scope module, "setSLTres2" "TwoInMux" 3 335, 3 109, S_0x25a6870; + .timescale -9 -12; +L_0x2b98b10/d .functor NOT 1, L_0x2ba8dd0, C4<0>, C4<0>, C4<0>; +L_0x2b98b10 .delay (10000,10000,10000) L_0x2b98b10/d; +L_0x2b98bb0/d .functor AND 1, L_0x2b99dd0, L_0x2b98b10, C4<1>, C4<1>; +L_0x2b98bb0 .delay (20000,20000,20000) L_0x2b98bb0/d; +L_0x2b98cc0/d .functor AND 1, C4<0>, L_0x2ba8dd0, C4<1>, C4<1>; +L_0x2b98cc0 .delay (20000,20000,20000) L_0x2b98cc0/d; +L_0x2b98d60/d .functor OR 1, L_0x2b98bb0, L_0x2b98cc0, C4<0>, C4<0>; +L_0x2b98d60 .delay (20000,20000,20000) L_0x2b98d60/d; +v0x25a6660_0 .alias "S", 0 0, v0x240f880_0; +v0x25ae7c0_0 .net "in0", 0 0, L_0x2b99dd0; 1 drivers +v0x25ae860_0 .net "in1", 0 0, C4<0>; 1 drivers +v0x25ae510_0 .net "nS", 0 0, L_0x2b98b10; 1 drivers +v0x25ae5b0_0 .net "out0", 0 0, L_0x2b98bb0; 1 drivers +v0x25acee0_0 .net "out1", 0 0, L_0x2b98cc0; 1 drivers +v0x25acc30_0 .net "outfinal", 0 0, L_0x2b98d60; 1 drivers +S_0x25aa3b0 .scope module, "setSLTres3" "TwoInMux" 3 336, 3 109, S_0x25a6870; + .timescale -9 -12; +L_0x2b9a200/d .functor NOT 1, L_0x2ba8dd0, C4<0>, C4<0>, C4<0>; +L_0x2b9a200 .delay (10000,10000,10000) L_0x2b9a200/d; +L_0x2b9a310/d .functor AND 1, L_0x2b95820, L_0x2b9a200, C4<1>, C4<1>; +L_0x2b9a310 .delay (20000,20000,20000) L_0x2b9a310/d; +L_0x2b9a420/d .functor AND 1, L_0x2b95910, L_0x2ba8dd0, C4<1>, C4<1>; +L_0x2b9a420 .delay (20000,20000,20000) L_0x2b9a420/d; +L_0x2b9a4c0/d .functor OR 1, L_0x2b9a310, L_0x2b9a420, C4<0>, C4<0>; +L_0x2b9a4c0 .delay (20000,20000,20000) L_0x2b9a4c0/d; +v0x25a6ba0_0 .alias "S", 0 0, v0x240f880_0; +v0x25aa100_0 .net "in0", 0 0, L_0x2b95820; 1 drivers +v0x25aa180_0 .net "in1", 0 0, L_0x2b95910; 1 drivers +v0x25a9170_0 .net "nS", 0 0, L_0x2b9a200; 1 drivers +v0x25a91f0_0 .net "out0", 0 0, L_0x2b9a310; 1 drivers +v0x25a8ec0_0 .net "out1", 0 0, L_0x2b9a420; 1 drivers +v0x25a65c0_0 .net "outfinal", 0 0, L_0x2b9a4c0; 1 drivers +S_0x25988f0 .scope generate, "sltbits[25]" "sltbits[25]" 3 332, 3 332, S_0x2753240; + .timescale -9 -12; +P_0x226fd48 .param/l "i" 3 332, +C4<011001>; +S_0x25a2db0 .scope module, "attempt" "MiddleAddSubSLT" 3 334, 3 189, S_0x25988f0; + .timescale -9 -12; +L_0x2b9af30/d .functor NOT 1, L_0x2b9a870, C4<0>, C4<0>, C4<0>; +L_0x2b9af30 .delay (10000,10000,10000) L_0x2b9af30/d; +L_0x2b9b530/d .functor NOT 1, L_0x2b9b5d0, C4<0>, C4<0>, C4<0>; +L_0x2b9b530 .delay (10000,10000,10000) L_0x2b9b530/d; +L_0x2b9b670/d .functor AND 1, L_0x2b9b7b0, L_0x2b9b530, C4<1>, C4<1>; +L_0x2b9b670 .delay (20000,20000,20000) L_0x2b9b670/d; +L_0x2b9b850/d .functor XOR 1, L_0x2b9a7d0, L_0x2b9b300, C4<0>, C4<0>; +L_0x2b9b850 .delay (40000,40000,40000) L_0x2b9b850/d; +L_0x2b9b940/d .functor XOR 1, L_0x2b9b850, L_0x2b9a9a0, C4<0>, C4<0>; +L_0x2b9b940 .delay (40000,40000,40000) L_0x2b9b940/d; +L_0x2b9ba30/d .functor AND 1, L_0x2b9a7d0, L_0x2b9b300, C4<1>, C4<1>; +L_0x2b9ba30 .delay (20000,20000,20000) L_0x2b9ba30/d; +L_0x2b9bba0/d .functor AND 1, L_0x2b9b850, L_0x2b9a9a0, C4<1>, C4<1>; +L_0x2b9bba0 .delay (20000,20000,20000) L_0x2b9bba0/d; +L_0x2b9bc90/d .functor OR 1, L_0x2b9ba30, L_0x2b9bba0, C4<0>, C4<0>; +L_0x2b9bc90 .delay (20000,20000,20000) L_0x2b9bc90/d; +v0x25a42a0_0 .net "A", 0 0, L_0x2b9a7d0; 1 drivers +v0x25a3310_0 .net "AandB", 0 0, L_0x2b9ba30; 1 drivers +v0x25a33b0_0 .net "AddSubSLTSum", 0 0, L_0x2b9b940; 1 drivers +v0x25a3060_0 .net "AxorB", 0 0, L_0x2b9b850; 1 drivers +v0x25a30e0_0 .net "B", 0 0, L_0x2b9a870; 1 drivers +v0x25a8c10_0 .net "BornB", 0 0, L_0x2b9b300; 1 drivers +v0x25a8c90_0 .net "CINandAxorB", 0 0, L_0x2b9bba0; 1 drivers +v0x25a8960_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x25a89e0_0 .net *"_s3", 0 0, L_0x2b9b5d0; 1 drivers +v0x25a86b0_0 .net *"_s5", 0 0, L_0x2b9b7b0; 1 drivers +v0x25a8730_0 .net "carryin", 0 0, L_0x2b9a9a0; 1 drivers +v0x25a7080_0 .net "carryout", 0 0, L_0x2b9bc90; 1 drivers +v0x25a7100_0 .net "nB", 0 0, L_0x2b9af30; 1 drivers +v0x25a6dd0_0 .net "nCmd2", 0 0, L_0x2b9b530; 1 drivers +v0x25a6b20_0 .net "subtract", 0 0, L_0x2b9b670; 1 drivers +L_0x2b9b490 .part v0x2960210_0, 0, 1; +L_0x2b9b5d0 .part v0x2960210_0, 2, 1; +L_0x2b9b7b0 .part v0x2960210_0, 0, 1; +S_0x25a2b00 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x25a2db0; + .timescale -9 -12; +L_0x2b9b080/d .functor NOT 1, L_0x2b9b490, C4<0>, C4<0>, C4<0>; +L_0x2b9b080 .delay (10000,10000,10000) L_0x2b9b080/d; +L_0x2b9b120/d .functor AND 1, L_0x2b9a870, L_0x2b9b080, C4<1>, C4<1>; +L_0x2b9b120 .delay (20000,20000,20000) L_0x2b9b120/d; +L_0x2b9b210/d .functor AND 1, L_0x2b9af30, L_0x2b9b490, C4<1>, C4<1>; +L_0x2b9b210 .delay (20000,20000,20000) L_0x2b9b210/d; +L_0x2b9b300/d .functor OR 1, L_0x2b9b120, L_0x2b9b210, C4<0>, C4<0>; +L_0x2b9b300 .delay (20000,20000,20000) L_0x2b9b300/d; +v0x25a2850_0 .net "S", 0 0, L_0x2b9b490; 1 drivers +v0x25a1220_0 .alias "in0", 0 0, v0x25a30e0_0; +v0x25a12c0_0 .alias "in1", 0 0, v0x25a7100_0; +v0x25a0f70_0 .net "nS", 0 0, L_0x2b9b080; 1 drivers +v0x25a0ff0_0 .net "out0", 0 0, L_0x2b9b120; 1 drivers +v0x25a4550_0 .net "out1", 0 0, L_0x2b9b210; 1 drivers +v0x25a45f0_0 .alias "outfinal", 0 0, v0x25a8c10_0; +S_0x259e710 .scope module, "setSLTres2" "TwoInMux" 3 335, 3 109, S_0x25988f0; + .timescale -9 -12; +L_0x2b9aa40/d .functor NOT 1, L_0x2ba8dd0, C4<0>, C4<0>, C4<0>; +L_0x2b9aa40 .delay (10000,10000,10000) L_0x2b9aa40/d; +L_0x2b9aae0/d .functor AND 1, L_0x2b9ae90, L_0x2b9aa40, C4<1>, C4<1>; +L_0x2b9aae0 .delay (20000,20000,20000) L_0x2b9aae0/d; +L_0x2b9abf0/d .functor AND 1, C4<0>, L_0x2ba8dd0, C4<1>, C4<1>; +L_0x2b9abf0 .delay (20000,20000,20000) L_0x2b9abf0/d; +L_0x2b9ac90/d .functor OR 1, L_0x2b9aae0, L_0x2b9abf0, C4<0>, C4<0>; +L_0x2b9ac90 .delay (20000,20000,20000) L_0x2b9ac90/d; +v0x259b1f0_0 .alias "S", 0 0, v0x240f880_0; +v0x259e460_0 .net "in0", 0 0, L_0x2b9ae90; 1 drivers +v0x259e500_0 .net "in1", 0 0, C4<0>; 1 drivers +v0x259d4f0_0 .net "nS", 0 0, L_0x2b9aa40; 1 drivers +v0x259d590_0 .net "out0", 0 0, L_0x2b9aae0; 1 drivers +v0x259d240_0 .net "out1", 0 0, L_0x2b9abf0; 1 drivers +v0x259d2e0_0 .net "outfinal", 0 0, L_0x2b9ac90; 1 drivers +S_0x2598640 .scope module, "setSLTres3" "TwoInMux" 3 336, 3 109, S_0x25988f0; + .timescale -9 -12; +L_0x2b9c040/d .functor NOT 1, L_0x2ba8dd0, C4<0>, C4<0>, C4<0>; +L_0x2b9c040 .delay (10000,10000,10000) L_0x2b9c040/d; +L_0x2b9c150/d .functor AND 1, L_0x2b9c4e0, L_0x2b9c040, C4<1>, C4<1>; +L_0x2b9c150 .delay (20000,20000,20000) L_0x2b9c150/d; +L_0x2b9c260/d .functor AND 1, L_0x2b9c5d0, L_0x2ba8dd0, C4<1>, C4<1>; +L_0x2b9c260 .delay (20000,20000,20000) L_0x2b9c260/d; +L_0x2b9c300/d .functor OR 1, L_0x2b9c150, L_0x2b9c260, C4<0>, C4<0>; +L_0x2b9c300 .delay (20000,20000,20000) L_0x2b9c300/d; +v0x25953b0_0 .alias "S", 0 0, v0x240f880_0; +v0x25976d0_0 .net "in0", 0 0, L_0x2b9c4e0; 1 drivers +v0x2597750_0 .net "in1", 0 0, L_0x2b9c5d0; 1 drivers +v0x2597420_0 .net "nS", 0 0, L_0x2b9c040; 1 drivers +v0x25974a0_0 .net "out0", 0 0, L_0x2b9c150; 1 drivers +v0x259b400_0 .net "out1", 0 0, L_0x2b9c260; 1 drivers +v0x259b150_0 .net "outfinal", 0 0, L_0x2b9c300; 1 drivers +S_0x27a82d0 .scope generate, "sltbits[26]" "sltbits[26]" 3 332, 3 332, S_0x2753240; + .timescale -9 -12; +P_0x2275378 .param/l "i" 3 332, +C4<011010>; +S_0x25912e0 .scope module, "attempt" "MiddleAddSubSLT" 3 334, 3 189, S_0x27a82d0; + .timescale -9 -12; +L_0x2b9c6c0/d .functor NOT 1, L_0x2b9cb00, C4<0>, C4<0>, C4<0>; +L_0x2b9c6c0 .delay (10000,10000,10000) L_0x2b9c6c0/d; +L_0x2b9d620/d .functor NOT 1, L_0x2b9d6c0, C4<0>, C4<0>, C4<0>; +L_0x2b9d620 .delay (10000,10000,10000) L_0x2b9d620/d; +L_0x2b9d760/d .functor AND 1, L_0x2b9d8a0, L_0x2b9d620, C4<1>, C4<1>; +L_0x2b9d760 .delay (20000,20000,20000) L_0x2b9d760/d; +L_0x2b9d940/d .functor XOR 1, L_0x2b9ca60, L_0x2b9d3f0, C4<0>, C4<0>; +L_0x2b9d940 .delay (40000,40000,40000) L_0x2b9d940/d; +L_0x2b9da30/d .functor XOR 1, L_0x2b9d940, L_0x2b9cc30, C4<0>, C4<0>; +L_0x2b9da30 .delay (40000,40000,40000) L_0x2b9da30/d; +L_0x2b9db20/d .functor AND 1, L_0x2b9ca60, L_0x2b9d3f0, C4<1>, C4<1>; +L_0x2b9db20 .delay (20000,20000,20000) L_0x2b9db20/d; +L_0x2b9dc90/d .functor AND 1, L_0x2b9d940, L_0x2b9cc30, C4<1>, C4<1>; +L_0x2b9dc90 .delay (20000,20000,20000) L_0x2b9dc90/d; +L_0x2b9dd80/d .functor OR 1, L_0x2b9db20, L_0x2b9dc90, C4<0>, C4<0>; +L_0x2b9dd80 .delay (20000,20000,20000) L_0x2b9dd80/d; +v0x258f1c0_0 .net "A", 0 0, L_0x2b9ca60; 1 drivers +v0x258ee40_0 .net "AandB", 0 0, L_0x2b9db20; 1 drivers +v0x258eee0_0 .net "AddSubSLTSum", 0 0, L_0x2b9da30; 1 drivers +v0x2592aa0_0 .net "AxorB", 0 0, L_0x2b9d940; 1 drivers +v0x2592b20_0 .net "B", 0 0, L_0x2b9cb00; 1 drivers +v0x25927f0_0 .net "BornB", 0 0, L_0x2b9d3f0; 1 drivers +v0x2592870_0 .net "CINandAxorB", 0 0, L_0x2b9dc90; 1 drivers +v0x2591840_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x25918c0_0 .net *"_s3", 0 0, L_0x2b9d6c0; 1 drivers +v0x2591590_0 .net *"_s5", 0 0, L_0x2b9d8a0; 1 drivers +v0x2591610_0 .net "carryin", 0 0, L_0x2b9cc30; 1 drivers +v0x258eb90_0 .net "carryout", 0 0, L_0x2b9dd80; 1 drivers +v0x258ec10_0 .net "nB", 0 0, L_0x2b9c6c0; 1 drivers +v0x25955e0_0 .net "nCmd2", 0 0, L_0x2b9d620; 1 drivers +v0x2595330_0 .net "subtract", 0 0, L_0x2b9d760; 1 drivers +L_0x2b9d580 .part v0x2960210_0, 0, 1; +L_0x2b9d6c0 .part v0x2960210_0, 2, 1; +L_0x2b9d8a0 .part v0x2960210_0, 0, 1; +S_0x2591000 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x25912e0; + .timescale -9 -12; +L_0x2b9d170/d .functor NOT 1, L_0x2b9d580, C4<0>, C4<0>, C4<0>; +L_0x2b9d170 .delay (10000,10000,10000) L_0x2b9d170/d; +L_0x2b9d210/d .functor AND 1, L_0x2b9cb00, L_0x2b9d170, C4<1>, C4<1>; +L_0x2b9d210 .delay (20000,20000,20000) L_0x2b9d210/d; +L_0x2b9d300/d .functor AND 1, L_0x2b9c6c0, L_0x2b9d580, C4<1>, C4<1>; +L_0x2b9d300 .delay (20000,20000,20000) L_0x2b9d300/d; +L_0x2b9d3f0/d .functor OR 1, L_0x2b9d210, L_0x2b9d300, C4<0>, C4<0>; +L_0x2b9d3f0 .delay (20000,20000,20000) L_0x2b9d3f0/d; +v0x27ae3a0_0 .net "S", 0 0, L_0x2b9d580; 1 drivers +v0x2590d50_0 .alias "in0", 0 0, v0x2592b20_0; +v0x2590df0_0 .alias "in1", 0 0, v0x258ec10_0; +v0x258f6b0_0 .net "nS", 0 0, L_0x2b9d170; 1 drivers +v0x258f730_0 .net "out0", 0 0, L_0x2b9d210; 1 drivers +v0x258f3d0_0 .net "out1", 0 0, L_0x2b9d300; 1 drivers +v0x258f120_0 .alias "outfinal", 0 0, v0x25927f0_0; +S_0x27accd0 .scope module, "setSLTres2" "TwoInMux" 3 335, 3 109, S_0x27a82d0; + .timescale -9 -12; +L_0x2b9ccd0/d .functor NOT 1, L_0x2ba8dd0, C4<0>, C4<0>, C4<0>; +L_0x2b9ccd0 .delay (10000,10000,10000) L_0x2b9ccd0/d; +L_0x2b9cd70/d .functor AND 1, L_0x2b9dfb0, L_0x2b9ccd0, C4<1>, C4<1>; +L_0x2b9cd70 .delay (20000,20000,20000) L_0x2b9cd70/d; +L_0x2b9ce80/d .functor AND 1, C4<0>, L_0x2ba8dd0, C4<1>, C4<1>; +L_0x2b9ce80 .delay (20000,20000,20000) L_0x2b9ce80/d; +L_0x2b9cf40/d .functor OR 1, L_0x2b9cd70, L_0x2b9ce80, C4<0>, C4<0>; +L_0x2b9cf40 .delay (20000,20000,20000) L_0x2b9cf40/d; +v0x27acff0_0 .alias "S", 0 0, v0x240f880_0; +v0x27abe00_0 .net "in0", 0 0, L_0x2b9dfb0; 1 drivers +v0x27abea0_0 .net "in1", 0 0, C4<0>; 1 drivers +v0x27af450_0 .net "nS", 0 0, L_0x2b9ccd0; 1 drivers +v0x27af4f0_0 .net "out0", 0 0, L_0x2b9cd70; 1 drivers +v0x27af1d0_0 .net "out1", 0 0, L_0x2b9ce80; 1 drivers +v0x27ae300_0 .net "outfinal", 0 0, L_0x2b9cf40; 1 drivers +S_0x27a7400 .scope module, "setSLTres3" "TwoInMux" 3 336, 3 109, S_0x27a82d0; + .timescale -9 -12; +L_0x2b9e430/d .functor NOT 1, L_0x2ba8dd0, C4<0>, C4<0>, C4<0>; +L_0x2b9e430 .delay (10000,10000,10000) L_0x2b9e430/d; +L_0x2b9e540/d .functor AND 1, L_0x2b99fb0, L_0x2b9e430, C4<1>, C4<1>; +L_0x2b9e540 .delay (20000,20000,20000) L_0x2b9e540/d; +L_0x2b9e650/d .functor AND 1, L_0x2b9a050, L_0x2ba8dd0, C4<1>, C4<1>; +L_0x2b9e650 .delay (20000,20000,20000) L_0x2b9e650/d; +L_0x2b9e6f0/d .functor OR 1, L_0x2b9e540, L_0x2b9e650, C4<0>, C4<0>; +L_0x2b9e6f0 .delay (20000,20000,20000) L_0x2b9e6f0/d; +v0x27a85d0_0 .alias "S", 0 0, v0x240f880_0; +v0x27aaa50_0 .net "in0", 0 0, L_0x2b99fb0; 1 drivers +v0x27aaad0_0 .net "in1", 0 0, L_0x2b9a050; 1 drivers +v0x27aa7d0_0 .net "nS", 0 0, L_0x2b9e430; 1 drivers +v0x27aa850_0 .net "out0", 0 0, L_0x2b9e540; 1 drivers +v0x27a9900_0 .net "out1", 0 0, L_0x2b9e650; 1 drivers +v0x27acf50_0 .net "outfinal", 0 0, L_0x2b9e6f0; 1 drivers +S_0x2792690 .scope generate, "sltbits[27]" "sltbits[27]" 3 332, 3 332, S_0x2753240; + .timescale -9 -12; +P_0x230e458 .param/l "i" 3 332, +C4<011011>; +S_0x279ba90 .scope module, "attempt" "MiddleAddSubSLT" 3 334, 3 189, S_0x2792690; + .timescale -9 -12; +L_0x2b9a140/d .functor NOT 1, L_0x2b9eab0, C4<0>, C4<0>, C4<0>; +L_0x2b9a140 .delay (10000,10000,10000) L_0x2b9a140/d; +L_0x2b9f760/d .functor NOT 1, L_0x2b9f800, C4<0>, C4<0>, C4<0>; +L_0x2b9f760 .delay (10000,10000,10000) L_0x2b9f760/d; +L_0x2b9f8a0/d .functor AND 1, L_0x2b9f9e0, L_0x2b9f760, C4<1>, C4<1>; +L_0x2b9f8a0 .delay (20000,20000,20000) L_0x2b9f8a0/d; +L_0x2b9fa80/d .functor XOR 1, L_0x2b9ea10, L_0x2b9f530, C4<0>, C4<0>; +L_0x2b9fa80 .delay (40000,40000,40000) L_0x2b9fa80/d; +L_0x2b9fb70/d .functor XOR 1, L_0x2b9fa80, L_0x2b9ebe0, C4<0>, C4<0>; +L_0x2b9fb70 .delay (40000,40000,40000) L_0x2b9fb70/d; +L_0x2b9fc60/d .functor AND 1, L_0x2b9ea10, L_0x2b9f530, C4<1>, C4<1>; +L_0x2b9fc60 .delay (20000,20000,20000) L_0x2b9fc60/d; +L_0x2b9fdd0/d .functor AND 1, L_0x2b9fa80, L_0x2b9ebe0, C4<1>, C4<1>; +L_0x2b9fdd0 .delay (20000,20000,20000) L_0x2b9fdd0/d; +L_0x2b9fec0/d .functor OR 1, L_0x2b9fc60, L_0x2b9fdd0, C4<0>, C4<0>; +L_0x2b9fec0 .delay (20000,20000,20000) L_0x2b9fec0/d; +v0x27a1440_0 .net "A", 0 0, L_0x2b9ea10; 1 drivers +v0x27a04b0_0 .net "AandB", 0 0, L_0x2b9fc60; 1 drivers +v0x27a0550_0 .net "AddSubSLTSum", 0 0, L_0x2b9fb70; 1 drivers +v0x27a3b30_0 .net "AxorB", 0 0, L_0x2b9fa80; 1 drivers +v0x27a3bb0_0 .net "B", 0 0, L_0x2b9eab0; 1 drivers +v0x27a38b0_0 .net "BornB", 0 0, L_0x2b9f530; 1 drivers +v0x27a3930_0 .net "CINandAxorB", 0 0, L_0x2b9fdd0; 1 drivers +v0x27a29c0_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x27a2a40_0 .net *"_s3", 0 0, L_0x2b9f800; 1 drivers +v0x27a6050_0 .net *"_s5", 0 0, L_0x2b9f9e0; 1 drivers +v0x27a60d0_0 .net "carryin", 0 0, L_0x2b9ebe0; 1 drivers +v0x27a5dd0_0 .net "carryout", 0 0, L_0x2b9fec0; 1 drivers +v0x27a5e50_0 .net "nB", 0 0, L_0x2b9a140; 1 drivers +v0x27a4ed0_0 .net "nCmd2", 0 0, L_0x2b9f760; 1 drivers +v0x27a8550_0 .net "subtract", 0 0, L_0x2b9f8a0; 1 drivers +L_0x2b9f6c0 .part v0x2960210_0, 0, 1; +L_0x2b9f800 .part v0x2960210_0, 2, 1; +L_0x2b9f9e0 .part v0x2960210_0, 0, 1; +S_0x279f110 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x279ba90; + .timescale -9 -12; +L_0x2b9f2b0/d .functor NOT 1, L_0x2b9f6c0, C4<0>, C4<0>, C4<0>; +L_0x2b9f2b0 .delay (10000,10000,10000) L_0x2b9f2b0/d; +L_0x2b9f350/d .functor AND 1, L_0x2b9eab0, L_0x2b9f2b0, C4<1>, C4<1>; +L_0x2b9f350 .delay (20000,20000,20000) L_0x2b9f350/d; +L_0x2b9f440/d .functor AND 1, L_0x2b9a140, L_0x2b9f6c0, C4<1>, C4<1>; +L_0x2b9f440 .delay (20000,20000,20000) L_0x2b9f440/d; +L_0x2b9f530/d .functor OR 1, L_0x2b9f350, L_0x2b9f440, C4<0>, C4<0>; +L_0x2b9f530 .delay (20000,20000,20000) L_0x2b9f530/d; +v0x279ca20_0 .net "S", 0 0, L_0x2b9f6c0; 1 drivers +v0x279ee90_0 .alias "in0", 0 0, v0x27a3bb0_0; +v0x279ef30_0 .alias "in1", 0 0, v0x27a5e50_0; +v0x279dfa0_0 .net "nS", 0 0, L_0x2b9f2b0; 1 drivers +v0x279e020_0 .net "out0", 0 0, L_0x2b9f350; 1 drivers +v0x27a1620_0 .net "out1", 0 0, L_0x2b9f440; 1 drivers +v0x27a13a0_0 .alias "outfinal", 0 0, v0x27a38b0_0; +S_0x279a6f0 .scope module, "setSLTres2" "TwoInMux" 3 335, 3 109, S_0x2792690; + .timescale -9 -12; +L_0x2b9ec80/d .functor NOT 1, L_0x2ba8dd0, C4<0>, C4<0>, C4<0>; +L_0x2b9ec80 .delay (10000,10000,10000) L_0x2b9ec80/d; +L_0x2b9ed20/d .functor AND 1, L_0x2b9f0f0, L_0x2b9ec80, C4<1>, C4<1>; +L_0x2b9ed20 .delay (20000,20000,20000) L_0x2b9ed20/d; +L_0x2b9ee30/d .functor AND 1, C4<0>, L_0x2ba8dd0, C4<1>, C4<1>; +L_0x2b9ee30 .delay (20000,20000,20000) L_0x2b9ee30/d; +L_0x2b9eef0/d .functor OR 1, L_0x2b9ed20, L_0x2b9ee30, C4<0>, C4<0>; +L_0x2b9eef0 .delay (20000,20000,20000) L_0x2b9eef0/d; +v0x2797110_0 .alias "S", 0 0, v0x240f880_0; +v0x279a470_0 .net "in0", 0 0, L_0x2b9f0f0; 1 drivers +v0x279a510_0 .net "in1", 0 0, C4<0>; 1 drivers +v0x2799580_0 .net "nS", 0 0, L_0x2b9ec80; 1 drivers +v0x2799620_0 .net "out0", 0 0, L_0x2b9ed20; 1 drivers +v0x279cc00_0 .net "out1", 0 0, L_0x2b9ee30; 1 drivers +v0x279c980_0 .net "outfinal", 0 0, L_0x2b9eef0; 1 drivers +S_0x2795cd0 .scope module, "setSLTres3" "TwoInMux" 3 336, 3 109, S_0x2792690; + .timescale -9 -12; +L_0x2ba0b70/d .functor NOT 1, L_0x2ba8dd0, C4<0>, C4<0>, C4<0>; +L_0x2ba0b70 .delay (10000,10000,10000) L_0x2ba0b70/d; +L_0x2ba0c60/d .functor AND 1, L_0x2ba0fd0, L_0x2ba0b70, C4<1>, C4<1>; +L_0x2ba0c60 .delay (20000,20000,20000) L_0x2ba0c60/d; +L_0x2ba0d50/d .functor AND 1, L_0x2ba01e0, L_0x2ba8dd0, C4<1>, C4<1>; +L_0x2ba0d50 .delay (20000,20000,20000) L_0x2ba0d50/d; +L_0x2ba0df0/d .functor OR 1, L_0x2ba0c60, L_0x2ba0d50, C4<0>, C4<0>; +L_0x2ba0df0 .delay (20000,20000,20000) L_0x2ba0df0/d; +v0x2795a50_0 .alias "S", 0 0, v0x240f880_0; +v0x276d620_0 .net "in0", 0 0, L_0x2ba0fd0; 1 drivers +v0x2795ad0_0 .net "in1", 0 0, L_0x2ba01e0; 1 drivers +v0x27981e0_0 .net "nS", 0 0, L_0x2ba0b70; 1 drivers +v0x2798260_0 .net "out0", 0 0, L_0x2ba0c60; 1 drivers +v0x2797f60_0 .net "out1", 0 0, L_0x2ba0d50; 1 drivers +v0x2797070_0 .net "outfinal", 0 0, L_0x2ba0df0; 1 drivers +S_0x2780d30 .scope generate, "sltbits[28]" "sltbits[28]" 3 332, 3 332, S_0x2753240; + .timescale -9 -12; +P_0x248f6b8 .param/l "i" 3 332, +C4<011100>; +S_0x278a3e0 .scope module, "attempt" "MiddleAddSubSLT" 3 334, 3 189, S_0x2780d30; + .timescale -9 -12; +L_0x2ba02d0/d .functor NOT 1, L_0x2ba1340, C4<0>, C4<0>, C4<0>; +L_0x2ba02d0 .delay (10000,10000,10000) L_0x2ba02d0/d; +L_0x2ba0a30/d .functor NOT 1, L_0x2ba1a10, C4<0>, C4<0>, C4<0>; +L_0x2ba0a30 .delay (10000,10000,10000) L_0x2ba0a30/d; +L_0x2ba1ab0/d .functor AND 1, L_0x2ba1bf0, L_0x2ba0a30, C4<1>, C4<1>; +L_0x2ba1ab0 .delay (20000,20000,20000) L_0x2ba1ab0/d; +L_0x2ba1c90/d .functor XOR 1, L_0x2ba12a0, L_0x2ba07c0, C4<0>, C4<0>; +L_0x2ba1c90 .delay (40000,40000,40000) L_0x2ba1c90/d; +L_0x2ba1d80/d .functor XOR 1, L_0x2ba1c90, L_0x2ba1470, C4<0>, C4<0>; +L_0x2ba1d80 .delay (40000,40000,40000) L_0x2ba1d80/d; +L_0x2ba1e70/d .functor AND 1, L_0x2ba12a0, L_0x2ba07c0, C4<1>, C4<1>; +L_0x2ba1e70 .delay (20000,20000,20000) L_0x2ba1e70/d; +L_0x2ba1fe0/d .functor AND 1, L_0x2ba1c90, L_0x2ba1470, C4<1>, C4<1>; +L_0x2ba1fe0 .delay (20000,20000,20000) L_0x2ba1fe0/d; +L_0x2ba20d0/d .functor OR 1, L_0x2ba1e70, L_0x2ba1fe0, C4<0>, C4<0>; +L_0x2ba20d0 .delay (20000,20000,20000) L_0x2ba20d0/d; +v0x278b830_0 .net "A", 0 0, L_0x2ba12a0; 1 drivers +v0x278ede0_0 .net "AandB", 0 0, L_0x2ba1e70; 1 drivers +v0x278ee60_0 .net "AddSubSLTSum", 0 0, L_0x2ba1d80; 1 drivers +v0x278eb60_0 .net "AxorB", 0 0, L_0x2ba1c90; 1 drivers +v0x278ebe0_0 .net "B", 0 0, L_0x2ba1340; 1 drivers +v0x278dc90_0 .net "BornB", 0 0, L_0x2ba07c0; 1 drivers +v0x27912e0_0 .net "CINandAxorB", 0 0, L_0x2ba1fe0; 1 drivers +v0x2791360_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x2791060_0 .net *"_s3", 0 0, L_0x2ba1a10; 1 drivers +v0x27910e0_0 .net *"_s5", 0 0, L_0x2ba1bf0; 1 drivers +v0x2790190_0 .net "carryin", 0 0, L_0x2ba1470; 1 drivers +v0x2790210_0 .net "carryout", 0 0, L_0x2ba20d0; 1 drivers +v0x27937e0_0 .net "nB", 0 0, L_0x2ba02d0; 1 drivers +v0x2793860_0 .net "nCmd2", 0 0, L_0x2ba0a30; 1 drivers +v0x27935e0_0 .net "subtract", 0 0, L_0x2ba1ab0; 1 drivers +L_0x2ba0990 .part v0x2960210_0, 0, 1; +L_0x2ba1a10 .part v0x2960210_0, 2, 1; +L_0x2ba1bf0 .part v0x2960210_0, 0, 1; +S_0x278a160 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x278a3e0; + .timescale -9 -12; +L_0x2ba04c0/d .functor NOT 1, L_0x2ba0990, C4<0>, C4<0>, C4<0>; +L_0x2ba04c0 .delay (10000,10000,10000) L_0x2ba04c0/d; +L_0x2ba05a0/d .functor AND 1, L_0x2ba1340, L_0x2ba04c0, C4<1>, C4<1>; +L_0x2ba05a0 .delay (20000,20000,20000) L_0x2ba05a0/d; +L_0x2ba06b0/d .functor AND 1, L_0x2ba02d0, L_0x2ba0990, C4<1>, C4<1>; +L_0x2ba06b0 .delay (20000,20000,20000) L_0x2ba06b0/d; +L_0x2ba07c0/d .functor OR 1, L_0x2ba05a0, L_0x2ba06b0, C4<0>, C4<0>; +L_0x2ba07c0 .delay (20000,20000,20000) L_0x2ba07c0/d; +v0x2786e30_0 .net "S", 0 0, L_0x2ba0990; 1 drivers +v0x2789290_0 .alias "in0", 0 0, v0x278ebe0_0; +v0x2789330_0 .alias "in1", 0 0, v0x27937e0_0; +v0x278c8e0_0 .net "nS", 0 0, L_0x2ba04c0; 1 drivers +v0x278c980_0 .net "out0", 0 0, L_0x2ba05a0; 1 drivers +v0x278c660_0 .net "out1", 0 0, L_0x2ba06b0; 1 drivers +v0x278b790_0 .alias "outfinal", 0 0, v0x278dc90_0; +S_0x2785760 .scope module, "setSLTres2" "TwoInMux" 3 335, 3 109, S_0x2780d30; + .timescale -9 -12; +L_0x2ba1510/d .functor NOT 1, L_0x2ba8dd0, C4<0>, C4<0>, C4<0>; +L_0x2ba1510 .delay (10000,10000,10000) L_0x2ba1510/d; +L_0x2ba15b0/d .functor AND 1, L_0x2ba1960, L_0x2ba1510, C4<1>, C4<1>; +L_0x2ba15b0 .delay (20000,20000,20000) L_0x2ba15b0/d; +L_0x2ba16c0/d .functor AND 1, C4<0>, L_0x2ba8dd0, C4<1>, C4<1>; +L_0x2ba16c0 .delay (20000,20000,20000) L_0x2ba16c0/d; +L_0x2ba1760/d .functor OR 1, L_0x2ba15b0, L_0x2ba16c0, C4<0>, C4<0>; +L_0x2ba1760 .delay (20000,20000,20000) L_0x2ba1760/d; +v0x2785a80_0 .alias "S", 0 0, v0x240f880_0; +v0x2784860_0 .net "in0", 0 0, L_0x2ba1960; 1 drivers +v0x2784900_0 .net "in1", 0 0, C4<0>; 1 drivers +v0x2787ee0_0 .net "nS", 0 0, L_0x2ba1510; 1 drivers +v0x2787f80_0 .net "out0", 0 0, L_0x2ba15b0; 1 drivers +v0x2787c60_0 .net "out1", 0 0, L_0x2ba16c0; 1 drivers +v0x2786d90_0 .net "outfinal", 0 0, L_0x2ba1760; 1 drivers +S_0x277fe40 .scope module, "setSLTres3" "TwoInMux" 3 336, 3 109, S_0x2780d30; + .timescale -9 -12; +L_0x2b9e130/d .functor NOT 1, L_0x2ba8dd0, C4<0>, C4<0>, C4<0>; +L_0x2b9e130 .delay (10000,10000,10000) L_0x2b9e130/d; +L_0x2b9e240/d .functor AND 1, L_0x2ba2300, L_0x2b9e130, C4<1>, C4<1>; +L_0x2b9e240 .delay (20000,20000,20000) L_0x2b9e240/d; +L_0x2b9e350/d .functor AND 1, L_0x2ba23f0, L_0x2ba8dd0, C4<1>, C4<1>; +L_0x2b9e350 .delay (20000,20000,20000) L_0x2b9e350/d; +L_0x2ba3080/d .functor OR 1, L_0x2b9e240, L_0x2b9e350, C4<0>, C4<0>; +L_0x2ba3080 .delay (20000,20000,20000) L_0x2ba3080/d; +v0x2781030_0 .alias "S", 0 0, v0x240f880_0; +v0x27834c0_0 .net "in0", 0 0, L_0x2ba2300; 1 drivers +v0x2783540_0 .net "in1", 0 0, L_0x2ba23f0; 1 drivers +v0x2783240_0 .net "nS", 0 0, L_0x2b9e130; 1 drivers +v0x27832c0_0 .net "out0", 0 0, L_0x2b9e240; 1 drivers +v0x2782350_0 .net "out1", 0 0, L_0x2b9e350; 1 drivers +v0x27859e0_0 .net "outfinal", 0 0, L_0x2ba3080; 1 drivers +S_0x276e770 .scope generate, "sltbits[29]" "sltbits[29]" 3 332, 3 332, S_0x2753240; + .timescale -9 -12; +P_0x24d9cf8 .param/l "i" 3 332, +C4<011101>; +S_0x27753e0 .scope module, "attempt" "MiddleAddSubSLT" 3 334, 3 189, S_0x276e770; + .timescale -9 -12; +L_0x2ba24e0/d .functor NOT 1, L_0x2ba33b0, C4<0>, C4<0>, C4<0>; +L_0x2ba24e0 .delay (10000,10000,10000) L_0x2ba24e0/d; +L_0x2ba2c00/d .functor NOT 1, L_0x2ba3c10, C4<0>, C4<0>, C4<0>; +L_0x2ba2c00 .delay (10000,10000,10000) L_0x2ba2c00/d; +L_0x2ba3cb0/d .functor AND 1, L_0x2ba3df0, L_0x2ba2c00, C4<1>, C4<1>; +L_0x2ba3cb0 .delay (20000,20000,20000) L_0x2ba3cb0/d; +L_0x2ba3e90/d .functor XOR 1, L_0x2ba3310, L_0x2ba2990, C4<0>, C4<0>; +L_0x2ba3e90 .delay (40000,40000,40000) L_0x2ba3e90/d; +L_0x2ba3f80/d .functor XOR 1, L_0x2ba3e90, L_0x2ba34e0, C4<0>, C4<0>; +L_0x2ba3f80 .delay (40000,40000,40000) L_0x2ba3f80/d; +L_0x2ba4070/d .functor AND 1, L_0x2ba3310, L_0x2ba2990, C4<1>, C4<1>; +L_0x2ba4070 .delay (20000,20000,20000) L_0x2ba4070/d; +L_0x2ba41e0/d .functor AND 1, L_0x2ba3e90, L_0x2ba34e0, C4<1>, C4<1>; +L_0x2ba41e0 .delay (20000,20000,20000) L_0x2ba41e0/d; +L_0x2ba42d0/d .functor OR 1, L_0x2ba4070, L_0x2ba41e0, C4<0>, C4<0>; +L_0x2ba42d0 .delay (20000,20000,20000) L_0x2ba42d0/d; +v0x2779e00_0 .net "A", 0 0, L_0x2ba3310; 1 drivers +v0x2778f10_0 .net "AandB", 0 0, L_0x2ba4070; 1 drivers +v0x2778fb0_0 .net "AddSubSLTSum", 0 0, L_0x2ba3f80; 1 drivers +v0x277c590_0 .net "AxorB", 0 0, L_0x2ba3e90; 1 drivers +v0x277c610_0 .net "B", 0 0, L_0x2ba33b0; 1 drivers +v0x277c310_0 .net "BornB", 0 0, L_0x2ba2990; 1 drivers +v0x277c390_0 .net "CINandAxorB", 0 0, L_0x2ba41e0; 1 drivers +v0x277b420_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x277b4a0_0 .net *"_s3", 0 0, L_0x2ba3c10; 1 drivers +v0x277eaa0_0 .net *"_s5", 0 0, L_0x2ba3df0; 1 drivers +v0x277eb20_0 .net "carryin", 0 0, L_0x2ba34e0; 1 drivers +v0x277e820_0 .net "carryout", 0 0, L_0x2ba42d0; 1 drivers +v0x277e8a0_0 .net "nB", 0 0, L_0x2ba24e0; 1 drivers +v0x277d930_0 .net "nCmd2", 0 0, L_0x2ba2c00; 1 drivers +v0x2780fb0_0 .net "subtract", 0 0, L_0x2ba3cb0; 1 drivers +L_0x2ba2b60 .part v0x2960210_0, 0, 1; +L_0x2ba3c10 .part v0x2960210_0, 2, 1; +L_0x2ba3df0 .part v0x2960210_0, 0, 1; +S_0x2774520 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x27753e0; + .timescale -9 -12; +L_0x2ba26b0/d .functor NOT 1, L_0x2ba2b60, C4<0>, C4<0>, C4<0>; +L_0x2ba26b0 .delay (10000,10000,10000) L_0x2ba26b0/d; +L_0x2ba2770/d .functor AND 1, L_0x2ba33b0, L_0x2ba26b0, C4<1>, C4<1>; +L_0x2ba2770 .delay (20000,20000,20000) L_0x2ba2770/d; +L_0x2ba2880/d .functor AND 1, L_0x2ba24e0, L_0x2ba2b60, C4<1>, C4<1>; +L_0x2ba2880 .delay (20000,20000,20000) L_0x2ba2880/d; +L_0x2ba2990/d .functor OR 1, L_0x2ba2770, L_0x2ba2880, C4<0>, C4<0>; +L_0x2ba2990 .delay (20000,20000,20000) L_0x2ba2990/d; +v0x2777b70_0 .net "S", 0 0, L_0x2ba2b60; 1 drivers +v0x27778f0_0 .alias "in0", 0 0, v0x277c610_0; +v0x2777990_0 .alias "in1", 0 0, v0x277e8a0_0; +v0x2776a00_0 .net "nS", 0 0, L_0x2ba26b0; 1 drivers +v0x2776a80_0 .net "out0", 0 0, L_0x2ba2770; 1 drivers +v0x277a080_0 .net "out1", 0 0, L_0x2ba2880; 1 drivers +v0x277a120_0 .alias "outfinal", 0 0, v0x277c310_0; +S_0x2773170 .scope module, "setSLTres2" "TwoInMux" 3 335, 3 109, S_0x276e770; + .timescale -9 -12; +L_0x2ba3580/d .functor NOT 1, L_0x2ba8dd0, C4<0>, C4<0>, C4<0>; +L_0x2ba3580 .delay (10000,10000,10000) L_0x2ba3580/d; +L_0x2ba3620/d .functor AND 1, L_0x2ba39d0, L_0x2ba3580, C4<1>, C4<1>; +L_0x2ba3620 .delay (20000,20000,20000) L_0x2ba3620/d; +L_0x2ba3730/d .functor AND 1, C4<0>, L_0x2ba8dd0, C4<1>, C4<1>; +L_0x2ba3730 .delay (20000,20000,20000) L_0x2ba3730/d; +L_0x2ba37d0/d .functor OR 1, L_0x2ba3620, L_0x2ba3730, C4<0>, C4<0>; +L_0x2ba37d0 .delay (20000,20000,20000) L_0x2ba37d0/d; +v0x276fbc0_0 .alias "S", 0 0, v0x240f880_0; +v0x2772ef0_0 .net "in0", 0 0, L_0x2ba39d0; 1 drivers +v0x2772f90_0 .net "in1", 0 0, C4<0>; 1 drivers +v0x2772020_0 .net "nS", 0 0, L_0x2ba3580; 1 drivers +v0x27720c0_0 .net "out0", 0 0, L_0x2ba3620; 1 drivers +v0x2775660_0 .net "out1", 0 0, L_0x2ba3730; 1 drivers +v0x2775700_0 .net "outfinal", 0 0, L_0x2ba37d0; 1 drivers +S_0x276e4f0 .scope module, "setSLTres3" "TwoInMux" 3 336, 3 109, S_0x276e770; + .timescale -9 -12; +L_0x2ba3b50/d .functor NOT 1, L_0x2ba8dd0, C4<0>, C4<0>, C4<0>; +L_0x2ba3b50 .delay (10000,10000,10000) L_0x2ba3b50/d; +L_0x2ba5070/d .functor AND 1, L_0x2ba53e0, L_0x2ba3b50, C4<1>, C4<1>; +L_0x2ba5070 .delay (20000,20000,20000) L_0x2ba5070/d; +L_0x2ba5160/d .functor AND 1, L_0x2ba45f0, L_0x2ba8dd0, C4<1>, C4<1>; +L_0x2ba5160 .delay (20000,20000,20000) L_0x2ba5160/d; +L_0x2ba5200/d .functor OR 1, L_0x2ba5070, L_0x2ba5160, C4<0>, C4<0>; +L_0x2ba5200 .delay (20000,20000,20000) L_0x2ba5200/d; +v0x276b170_0 .alias "S", 0 0, v0x240f880_0; +v0x276d6b0_0 .net "in0", 0 0, L_0x2ba53e0; 1 drivers +v0x2770c70_0 .net "in1", 0 0, L_0x2ba45f0; 1 drivers +v0x2770d10_0 .net "nS", 0 0, L_0x2ba3b50; 1 drivers +v0x27709f0_0 .net "out0", 0 0, L_0x2ba5070; 1 drivers +v0x2770a90_0 .net "out1", 0 0, L_0x2ba5160; 1 drivers +v0x276fb20_0 .net "outfinal", 0 0, L_0x2ba5200; 1 drivers +S_0x275f600 .scope generate, "sltbits[30]" "sltbits[30]" 3 332, 3 332, S_0x2753240; + .timescale -9 -12; +P_0x251c3a8 .param/l "i" 3 332, +C4<011110>; +S_0x2762fc0 .scope module, "attempt" "MiddleAddSubSLT" 3 334, 3 189, S_0x275f600; + .timescale -9 -12; +L_0x2ba46e0/d .functor NOT 1, L_0x2b82f70, C4<0>, C4<0>, C4<0>; +L_0x2ba46e0 .delay (10000,10000,10000) L_0x2ba46e0/d; +L_0x2ba4e40/d .functor NOT 1, L_0x2ba4f00, C4<0>, C4<0>, C4<0>; +L_0x2ba4e40 .delay (10000,10000,10000) L_0x2ba4e40/d; +L_0x2ba5ed0/d .functor AND 1, L_0x2ba5fd0, L_0x2ba4e40, C4<1>, C4<1>; +L_0x2ba5ed0 .delay (20000,20000,20000) L_0x2ba5ed0/d; +L_0x2ba6070/d .functor XOR 1, L_0x2b82ed0, L_0x2ba4bd0, C4<0>, C4<0>; +L_0x2ba6070 .delay (40000,40000,40000) L_0x2ba6070/d; +L_0x2ba6160/d .functor XOR 1, L_0x2ba6070, L_0x2ba5b00, C4<0>, C4<0>; +L_0x2ba6160 .delay (40000,40000,40000) L_0x2ba6160/d; +L_0x2ba6250/d .functor AND 1, L_0x2b82ed0, L_0x2ba4bd0, C4<1>, C4<1>; +L_0x2ba6250 .delay (20000,20000,20000) L_0x2ba6250/d; +L_0x2ba63c0/d .functor AND 1, L_0x2ba6070, L_0x2ba5b00, C4<1>, C4<1>; +L_0x2ba63c0 .delay (20000,20000,20000) L_0x2ba63c0/d; +L_0x2ba64b0/d .functor OR 1, L_0x2ba6250, L_0x2ba63c0, C4<0>, C4<0>; +L_0x2ba64b0 .delay (20000,20000,20000) L_0x2ba64b0/d; +v0x27b1930_0 .net "A", 0 0, L_0x2b82ed0; 1 drivers +v0x27b16c0_0 .net "AandB", 0 0, L_0x2ba6250; 1 drivers +v0x27b1760_0 .net "AddSubSLTSum", 0 0, L_0x2ba6160; 1 drivers +v0x27b0800_0 .net "AxorB", 0 0, L_0x2ba6070; 1 drivers +v0x27b0880_0 .net "B", 0 0, L_0x2b82f70; 1 drivers +v0x2769d00_0 .net "BornB", 0 0, L_0x2ba4bd0; 1 drivers +v0x2769d80_0 .net "CINandAxorB", 0 0, L_0x2ba63c0; 1 drivers +v0x2769a20_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x2769aa0_0 .net *"_s3", 0 0, L_0x2ba4f00; 1 drivers +v0x2768b70_0 .net *"_s5", 0 0, L_0x2ba5fd0; 1 drivers +v0x2768bf0_0 .net "carryin", 0 0, L_0x2ba5b00; 1 drivers +v0x276c270_0 .net "carryout", 0 0, L_0x2ba64b0; 1 drivers +v0x276c2f0_0 .net "nB", 0 0, L_0x2ba46e0; 1 drivers +v0x276bff0_0 .net "nCmd2", 0 0, L_0x2ba4e40; 1 drivers +v0x276b0f0_0 .net "subtract", 0 0, L_0x2ba5ed0; 1 drivers +L_0x2ba4da0 .part v0x2960210_0, 0, 1; +L_0x2ba4f00 .part v0x2960210_0, 2, 1; +L_0x2ba5fd0 .part v0x2960210_0, 0, 1; +S_0x2764d00 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x2762fc0; + .timescale -9 -12; +L_0x2ba48b0/d .functor NOT 1, L_0x2ba4da0, C4<0>, C4<0>, C4<0>; +L_0x2ba48b0 .delay (10000,10000,10000) L_0x2ba48b0/d; +L_0x2ba4990/d .functor AND 1, L_0x2b82f70, L_0x2ba48b0, C4<1>, C4<1>; +L_0x2ba4990 .delay (20000,20000,20000) L_0x2ba4990/d; +L_0x2ba4ac0/d .functor AND 1, L_0x2ba46e0, L_0x2ba4da0, C4<1>, C4<1>; +L_0x2ba4ac0 .delay (20000,20000,20000) L_0x2ba4ac0/d; +L_0x2ba4bd0/d .functor OR 1, L_0x2ba4990, L_0x2ba4ac0, C4<0>, C4<0>; +L_0x2ba4bd0 .delay (20000,20000,20000) L_0x2ba4bd0/d; +v0x2763560_0 .net "S", 0 0, L_0x2ba4da0; 1 drivers +v0x2764a80_0 .alias "in0", 0 0, v0x27b0880_0; +v0x2764b20_0 .alias "in1", 0 0, v0x276c2f0_0; +v0x27662c0_0 .net "nS", 0 0, L_0x2ba48b0; 1 drivers +v0x2766360_0 .net "out0", 0 0, L_0x2ba4990; 1 drivers +v0x2766020_0 .net "out1", 0 0, L_0x2ba4ac0; 1 drivers +v0x27660c0_0 .alias "outfinal", 0 0, v0x2769d00_0; +S_0x2762180 .scope module, "setSLTres2" "TwoInMux" 3 335, 3 109, S_0x275f600; + .timescale -9 -12; +L_0x2ba5ba0/d .functor NOT 1, L_0x2ba8dd0, C4<0>, C4<0>, C4<0>; +L_0x2ba5ba0 .delay (10000,10000,10000) L_0x2ba5ba0/d; +L_0x2ba5c40/d .functor AND 1, L_0x2ba66e0, L_0x2ba5ba0, C4<1>, C4<1>; +L_0x2ba5c40 .delay (20000,20000,20000) L_0x2ba5c40/d; +L_0x2ba5d50/d .functor AND 1, C4<0>, L_0x2ba8dd0, C4<1>, C4<1>; +L_0x2ba5d50 .delay (20000,20000,20000) L_0x2ba5d50/d; +L_0x2ba5df0/d .functor OR 1, L_0x2ba5c40, L_0x2ba5d50, C4<0>, C4<0>; +L_0x2ba5df0 .delay (20000,20000,20000) L_0x2ba5df0/d; +v0x27604c0_0 .alias "S", 0 0, v0x240f880_0; +v0x2761f00_0 .net "in0", 0 0, L_0x2ba66e0; 1 drivers +v0x2761f80_0 .net "in1", 0 0, C4<0>; 1 drivers +v0x2761a00_0 .net "nS", 0 0, L_0x2ba5ba0; 1 drivers +v0x2761a80_0 .net "out0", 0 0, L_0x2ba5c40; 1 drivers +v0x2763740_0 .net "out1", 0 0, L_0x2ba5d50; 1 drivers +v0x27634c0_0 .net "outfinal", 0 0, L_0x2ba5df0; 1 drivers +S_0x275f380 .scope module, "setSLTres3" "TwoInMux" 3 336, 3 109, S_0x275f600; + .timescale -9 -12; +L_0x2ba6b40/d .functor NOT 1, L_0x2ba8dd0, C4<0>, C4<0>, C4<0>; +L_0x2ba6b40 .delay (10000,10000,10000) L_0x2ba6b40/d; +L_0x2ba6c50/d .functor AND 1, L_0x2ba6fe0, L_0x2ba6b40, C4<1>, C4<1>; +L_0x2ba6c50 .delay (20000,20000,20000) L_0x2ba6c50/d; +L_0x2ba6d60/d .functor AND 1, L_0x2ba2d70, L_0x2ba8dd0, C4<1>, C4<1>; +L_0x2ba6d60 .delay (20000,20000,20000) L_0x2ba6d60/d; +L_0x2ba6e00/d .functor OR 1, L_0x2ba6c50, L_0x2ba6d60, C4<0>, C4<0>; +L_0x2ba6e00 .delay (20000,20000,20000) L_0x2ba6e00/d; +v0x275ee80_0 .alias "S", 0 0, v0x240f880_0; +v0x275ef00_0 .net "in0", 0 0, L_0x2ba6fe0; 1 drivers +v0x2760bc0_0 .net "in1", 0 0, L_0x2ba2d70; 1 drivers +v0x2760c40_0 .net "nS", 0 0, L_0x2ba6b40; 1 drivers +v0x2760940_0 .net "out0", 0 0, L_0x2ba6c50; 1 drivers +v0x27609c0_0 .net "out1", 0 0, L_0x2ba6d60; 1 drivers +v0x2760440_0 .net "outfinal", 0 0, L_0x2ba6e00; 1 drivers +S_0x2752fa0 .scope generate, "sltbits[31]" "sltbits[31]" 3 332, 3 332, S_0x2753240; + .timescale -9 -12; +P_0x2534b48 .param/l "i" 3 332, +C4<011111>; +S_0x27586c0 .scope module, "attempt" "MiddleAddSubSLT" 3 334, 3 189, S_0x2752fa0; + .timescale -9 -12; +L_0x2ba2e60/d .functor NOT 1, L_0x2ba7390, C4<0>, C4<0>, C4<0>; +L_0x2ba2e60 .delay (10000,10000,10000) L_0x2ba2e60/d; +L_0x2ba80b0/d .functor NOT 1, L_0x2ba8150, C4<0>, C4<0>, C4<0>; +L_0x2ba80b0 .delay (10000,10000,10000) L_0x2ba80b0/d; +L_0x2ba81f0/d .functor AND 1, L_0x2ba8330, L_0x2ba80b0, C4<1>, C4<1>; +L_0x2ba81f0 .delay (20000,20000,20000) L_0x2ba81f0/d; +L_0x2ba83d0/d .functor XOR 1, L_0x2ba72f0, L_0x2ba7e80, C4<0>, C4<0>; +L_0x2ba83d0 .delay (40000,40000,40000) L_0x2ba83d0/d; +L_0x2ba84c0/d .functor XOR 1, L_0x2ba83d0, L_0x2ba74c0, C4<0>, C4<0>; +L_0x2ba84c0 .delay (40000,40000,40000) L_0x2ba84c0/d; +L_0x2ba85b0/d .functor AND 1, L_0x2ba72f0, L_0x2ba7e80, C4<1>, C4<1>; +L_0x2ba85b0 .delay (20000,20000,20000) L_0x2ba85b0/d; +L_0x2ba8720/d .functor AND 1, L_0x2ba83d0, L_0x2ba74c0, C4<1>, C4<1>; +L_0x2ba8720 .delay (20000,20000,20000) L_0x2ba8720/d; +L_0x2ba8810/d .functor OR 1, L_0x2ba85b0, L_0x2ba8720, C4<0>, C4<0>; +L_0x2ba8810 .delay (20000,20000,20000) L_0x2ba8810/d; +v0x275b4c0_0 .net "A", 0 0, L_0x2ba72f0; 1 drivers +v0x275b240_0 .net "AandB", 0 0, L_0x2ba85b0; 1 drivers +v0x275b2e0_0 .net "AddSubSLTSum", 0 0, L_0x2ba84c0; 1 drivers +v0x275ad40_0 .net "AxorB", 0 0, L_0x2ba83d0; 1 drivers +v0x275adc0_0 .net "B", 0 0, L_0x2ba7390; 1 drivers +v0x275ca80_0 .net "BornB", 0 0, L_0x2ba7e80; 1 drivers +v0x275c800_0 .net "CINandAxorB", 0 0, L_0x2ba8720; 1 drivers +v0x275c880_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x275c300_0 .net *"_s3", 0 0, L_0x2ba8150; 1 drivers +v0x275c380_0 .net *"_s5", 0 0, L_0x2ba8330; 1 drivers +v0x275e040_0 .net "carryin", 0 0, L_0x2ba74c0; 1 drivers +v0x275e0c0_0 .net "carryout", 0 0, L_0x2ba8810; 1 drivers +v0x275ddc0_0 .net "nB", 0 0, L_0x2ba2e60; 1 drivers +v0x275de40_0 .net "nCmd2", 0 0, L_0x2ba80b0; 1 drivers +v0x275d940_0 .net "subtract", 0 0, L_0x2ba81f0; 1 drivers +L_0x2ba8010 .part v0x2960210_0, 0, 1; +L_0x2ba8150 .part v0x2960210_0, 2, 1; +L_0x2ba8330 .part v0x2960210_0, 0, 1; +S_0x27581c0 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x27586c0; + .timescale -9 -12; +L_0x2ba2ff0/d .functor NOT 1, L_0x2ba8010, C4<0>, C4<0>, C4<0>; +L_0x2ba2ff0 .delay (10000,10000,10000) L_0x2ba2ff0/d; +L_0x2ba7ca0/d .functor AND 1, L_0x2ba7390, L_0x2ba2ff0, C4<1>, C4<1>; +L_0x2ba7ca0 .delay (20000,20000,20000) L_0x2ba7ca0/d; +L_0x2ba7d90/d .functor AND 1, L_0x2ba2e60, L_0x2ba8010, C4<1>, C4<1>; +L_0x2ba7d90 .delay (20000,20000,20000) L_0x2ba7d90/d; +L_0x2ba7e80/d .functor OR 1, L_0x2ba7ca0, L_0x2ba7d90, C4<0>, C4<0>; +L_0x2ba7e80 .delay (20000,20000,20000) L_0x2ba7e80/d; +v0x27589e0_0 .net "S", 0 0, L_0x2ba8010; 1 drivers +v0x2759f00_0 .alias "in0", 0 0, v0x275adc0_0; +v0x2759fa0_0 .alias "in1", 0 0, v0x275ddc0_0; +v0x2759c80_0 .net "nS", 0 0, L_0x2ba2ff0; 1 drivers +v0x2759d20_0 .net "out0", 0 0, L_0x2ba7ca0; 1 drivers +v0x2759780_0 .net "out1", 0 0, L_0x2ba7d90; 1 drivers +v0x2759820_0 .alias "outfinal", 0 0, v0x275ca80_0; +S_0x2755640 .scope module, "setSLTres2" "TwoInMux" 3 335, 3 109, S_0x2752fa0; + .timescale -9 -12; +L_0x2ba7560/d .functor NOT 1, L_0x2ba8dd0, C4<0>, C4<0>, C4<0>; +L_0x2ba7560 .delay (10000,10000,10000) L_0x2ba7560/d; +L_0x2ba7600/d .functor AND 1, L_0x2ba79b0, L_0x2ba7560, C4<1>, C4<1>; +L_0x2ba7600 .delay (20000,20000,20000) L_0x2ba7600/d; +L_0x2ba7710/d .functor AND 1, C4<0>, L_0x2ba8dd0, C4<1>, C4<1>; +L_0x2ba7710 .delay (20000,20000,20000) L_0x2ba7710/d; +L_0x2ba77d0/d .functor OR 1, L_0x2ba7600, L_0x2ba7710, C4<0>, C4<0>; +L_0x2ba77d0 .delay (20000,20000,20000) L_0x2ba77d0/d; +v0x2755be0_0 .alias "S", 0 0, v0x240f880_0; +v0x2757380_0 .net "in0", 0 0, L_0x2ba79b0; 1 drivers +v0x2757400_0 .net "in1", 0 0, C4<0>; 1 drivers +v0x2757100_0 .net "nS", 0 0, L_0x2ba7560; 1 drivers +v0x27571a0_0 .net "out0", 0 0, L_0x2ba7600; 1 drivers +v0x2756c00_0 .net "out1", 0 0, L_0x2ba7710; 1 drivers +v0x2758940_0 .net "outfinal", 0 0, L_0x2ba77d0; 1 drivers +S_0x2754800 .scope module, "setSLTres3" "TwoInMux" 3 336, 3 109, S_0x2752fa0; + .timescale -9 -12; +L_0x2ba7b30/d .functor NOT 1, L_0x2ba8dd0, C4<0>, C4<0>, C4<0>; +L_0x2ba7b30 .delay (10000,10000,10000) L_0x2ba7b30/d; +L_0x2ba95d0/d .functor AND 1, L_0x2ba9900, L_0x2ba7b30, C4<1>, C4<1>; +L_0x2ba95d0 .delay (20000,20000,20000) L_0x2ba95d0/d; +L_0x2ba9680/d .functor AND 1, L_0x2ba8b30, L_0x2ba8dd0, C4<1>, C4<1>; +L_0x2ba9680 .delay (20000,20000,20000) L_0x2ba9680/d; +L_0x2ba9720/d .functor OR 1, L_0x2ba95d0, L_0x2ba9680, C4<0>, C4<0>; +L_0x2ba9720 .delay (20000,20000,20000) L_0x2ba9720/d; +v0x2754580_0 .alias "S", 0 0, v0x240f880_0; +v0x2754600_0 .net "in0", 0 0, L_0x2ba9900; 1 drivers +v0x2754080_0 .net "in1", 0 0, L_0x2ba8b30; 1 drivers +v0x2754120_0 .net "nS", 0 0, L_0x2ba7b30; 1 drivers +v0x2755dc0_0 .net "out0", 0 0, L_0x2ba95d0; 1 drivers +v0x2755e60_0 .net "out1", 0 0, L_0x2ba9680; 1 drivers +v0x2755b40_0 .net "outfinal", 0 0, L_0x2ba9720; 1 drivers +S_0x23ec510 .scope module, "trial" "AddSubSLT32" 3 53, 3 267, S_0x1f6b890; + .timescale -9 -12; +P_0x22ac8c8 .param/l "size" 3 281, +C4<0100000>; +L_0x2bd6820/d .functor OR 1, L_0x2bd68a0, C4<0>, C4<0>, C4<0>; +L_0x2bd6820 .delay (20000,20000,20000) L_0x2bd6820/d; +L_0x2bc33a0/d .functor XOR 1, RS_0x7f507e9e4bc8, L_0x2b883c0, C4<0>, C4<0>; +L_0x2bc33a0 .delay (40000,40000,40000) L_0x2bc33a0/d; +v0x274d920_0 .alias "A", 31 0, v0x295f580_0; +v0x274f100_0 .alias "AddSubSLTSum", 31 0, v0x2415680_0; +v0x274f1a0_0 .alias "B", 31 0, v0x295f6a0_0; +RS_0x7f507e9e4ad8/0/0 .resolv tri, L_0x2b3d410, L_0x2bb03d0, L_0x2bb17d0, L_0x2bb2d70; +RS_0x7f507e9e4ad8/0/4 .resolv tri, L_0x2bb4350, L_0x2bb58a0, L_0x2bb6e00, L_0x2bb8340; +RS_0x7f507e9e4ad8/0/8 .resolv tri, L_0x2bb9990, L_0x2bbaee0, L_0x2bbc3f0, L_0x2bbd8c0; +RS_0x7f507e9e4ad8/0/12 .resolv tri, L_0x2bbed80, L_0x2bc0250, L_0x2bc1710, L_0x2bc2bd0; +RS_0x7f507e9e4ad8/0/16 .resolv tri, L_0x2bc41b0, L_0x2bc55c0, L_0x2bc6a30, L_0x2bc7dc0; +RS_0x7f507e9e4ad8/0/20 .resolv tri, L_0x2bc9140, L_0x2bca590, L_0x2bcb950, L_0x2bcce10; +RS_0x7f507e9e4ad8/0/24 .resolv tri, L_0x2bce2e0, L_0x2bcf7a0, L_0x2bd0c80, L_0x2bd2130; +RS_0x7f507e9e4ad8/0/28 .resolv tri, L_0x2bd3610, L_0x2bd4f10, L_0x2bd63d0, L_0x2bd78b0; +RS_0x7f507e9e4ad8/1/0 .resolv tri, RS_0x7f507e9e4ad8/0/0, RS_0x7f507e9e4ad8/0/4, RS_0x7f507e9e4ad8/0/8, RS_0x7f507e9e4ad8/0/12; +RS_0x7f507e9e4ad8/1/4 .resolv tri, RS_0x7f507e9e4ad8/0/16, RS_0x7f507e9e4ad8/0/20, RS_0x7f507e9e4ad8/0/24, RS_0x7f507e9e4ad8/0/28; +RS_0x7f507e9e4ad8 .resolv tri, RS_0x7f507e9e4ad8/1/0, RS_0x7f507e9e4ad8/1/4, C4, C4; +v0x274ee80_0 .net8 "CarryoutWire", 31 0, RS_0x7f507e9e4ad8; 32 drivers +v0x274ef00_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x27506c0_0 .net *"_s292", 0 0, L_0x2bd68a0; 1 drivers +v0x2750420_0 .net/s *"_s293", 0 0, C4<0>; 1 drivers +v0x27504c0_0 .net *"_s296", 0 0, L_0x2b883c0; 1 drivers +v0x2751c80_0 .alias "carryin", 31 0, v0x2609fe0_0; +v0x2751d20_0 .alias "carryout", 0 0, v0x2960740_0; +v0x2751a00_0 .alias "overflow", 0 0, v0x29608f0_0; +v0x2751a80_0 .alias "subtract", 31 0, v0x25ec920_0; +L_0x2baea80 .part/pv L_0x2bacc80, 1, 1, 32; +L_0x2b3d410 .part/pv L_0x2bae940, 1, 1, 32; +L_0x2b3d500 .part/pv L_0x2bac9b0, 1, 1, 32; +L_0x2b3d5f0 .part v0x295fe90_0, 1, 1; +L_0x2b3d690 .part v0x2960190_0, 1, 1; +L_0x2baf3c0 .part RS_0x7f507e9e4ad8, 0, 1; +L_0x2bb02e0 .part/pv L_0x2bafe50, 2, 1, 32; +L_0x2bb03d0 .part/pv L_0x2bb01a0, 2, 1, 32; +L_0x2bb0510 .part/pv L_0x2bafb80, 2, 1, 32; +L_0x2bb0600 .part v0x295fe90_0, 2, 1; +L_0x2bb0700 .part v0x2960190_0, 2, 1; +L_0x2bb0830 .part RS_0x7f507e9e4ad8, 1, 1; +L_0x2bb16e0 .part/pv L_0x2bb1250, 3, 1, 32; +L_0x2bb17d0 .part/pv L_0x2bb15a0, 3, 1, 32; +L_0x2bb1940 .part/pv L_0x2bb0f80, 3, 1, 32; +L_0x2bb1a30 .part v0x295fe90_0, 3, 1; +L_0x2bb1b60 .part v0x2960190_0, 3, 1; +L_0x2bb1c90 .part RS_0x7f507e9e4ad8, 2, 1; +L_0x2bb2c80 .part/pv L_0x2bb27d0, 4, 1, 32; +L_0x2bb2d70 .part/pv L_0x2bb2b20, 4, 1, 32; +L_0x2bb1d30 .part/pv L_0x2bb2500, 4, 1, 32; +L_0x2bb2f60 .part v0x295fe90_0, 4, 1; +L_0x2bb2e60 .part v0x2960190_0, 4, 1; +L_0x2bb3150 .part RS_0x7f507e9e4ad8, 3, 1; +L_0x2bb4260 .part/pv L_0x2bb3d90, 5, 1, 32; +L_0x2bb4350 .part/pv L_0x2bb4100, 5, 1, 32; +L_0x2bb3300 .part/pv L_0x2bb3ac0, 5, 1, 32; +L_0x2bb4570 .part v0x295fe90_0, 5, 1; +L_0x2bb4440 .part v0x2960190_0, 5, 1; +L_0x2bb4790 .part RS_0x7f507e9e4ad8, 4, 1; +L_0x2bb57b0 .part/pv L_0x2bb52c0, 6, 1, 32; +L_0x2bb58a0 .part/pv L_0x2bb5650, 6, 1, 32; +L_0x2bb4830 .part/pv L_0x2bb4ff0, 6, 1, 32; +L_0x2bb5aa0 .part v0x295fe90_0, 6, 1; +L_0x2bb5990 .part v0x2960190_0, 6, 1; +L_0x2bb5cf0 .part RS_0x7f507e9e4ad8, 5, 1; +L_0x2bb6d10 .part/pv L_0x2bb6840, 7, 1, 32; +L_0x2bb6e00 .part/pv L_0x2bb6bb0, 7, 1, 32; +L_0x2bb5d90 .part/pv L_0x2bb6570, 7, 1, 32; +L_0x2bb7030 .part v0x295fe90_0, 7, 1; +L_0x2bb6ef0 .part v0x2960190_0, 7, 1; +L_0x2bb7220 .part RS_0x7f507e9e4ad8, 6, 1; +L_0x2bb8250 .part/pv L_0x2bb7d80, 8, 1, 32; +L_0x2bb8340 .part/pv L_0x2bb80f0, 8, 1, 32; +L_0x2bb72c0 .part/pv L_0x2bb7ab0, 8, 1, 32; +L_0x2bb85a0 .part v0x295fe90_0, 8, 1; +L_0x2bb8430 .part v0x2960190_0, 8, 1; +L_0x2bb87c0 .part RS_0x7f507e9e4ad8, 7, 1; +L_0x2bb98a0 .part/pv L_0x2bb93d0, 9, 1, 32; +L_0x2bb9990 .part/pv L_0x2bb9740, 9, 1, 32; +L_0x2bb8a70 .part/pv L_0x2bb9100, 9, 1, 32; +L_0x2bb8b60 .part v0x295fe90_0, 9, 1; +L_0x2bb9c30 .part v0x2960190_0, 9, 1; +L_0x2bb9d60 .part RS_0x7f507e9e4ad8, 8, 1; +L_0x2bbadf0 .part/pv L_0x2bba920, 10, 1, 32; +L_0x2bbaee0 .part/pv L_0x2bbac90, 10, 1, 32; +L_0x2bb9e00 .part/pv L_0x2bba650, 10, 1, 32; +L_0x2bb9ef0 .part v0x295fe90_0, 10, 1; +L_0x2bbb1b0 .part v0x2960190_0, 10, 1; +L_0x2bbb2e0 .part RS_0x7f507e9e4ad8, 9, 1; +L_0x2bbc300 .part/pv L_0x2bbbe50, 11, 1, 32; +L_0x2bbc3f0 .part/pv L_0x2bbc1a0, 11, 1, 32; +L_0x2bbb380 .part/pv L_0x2bbbb80, 11, 1, 32; +L_0x2bbb470 .part v0x295fe90_0, 11, 1; +L_0x2bbc6f0 .part v0x2960190_0, 11, 1; +L_0x2bbc820 .part RS_0x7f507e9e4ad8, 10, 1; +L_0x2bbd7d0 .part/pv L_0x2bbd320, 12, 1, 32; +L_0x2bbd8c0 .part/pv L_0x2bbd670, 12, 1, 32; +L_0x2bbc8c0 .part/pv L_0x2bbd050, 12, 1, 32; +L_0x2bbc9b0 .part v0x295fe90_0, 12, 1; +L_0x2bbdbf0 .part v0x2960190_0, 12, 1; +L_0x2bbdc90 .part RS_0x7f507e9e4ad8, 11, 1; +L_0x2bbec90 .part/pv L_0x2bbe7e0, 13, 1, 32; +L_0x2bbed80 .part/pv L_0x2bbeb30, 13, 1, 32; +L_0x2bbdd30 .part/pv L_0x2bbe510, 13, 1, 32; +L_0x2bbde20 .part v0x295fe90_0, 13, 1; +L_0x2bbdec0 .part v0x2960190_0, 13, 1; +L_0x2bbf170 .part RS_0x7f507e9e4ad8, 12, 1; +L_0x2bc0160 .part/pv L_0x2bbfcb0, 14, 1, 32; +L_0x2bc0250 .part/pv L_0x2bc0000, 14, 1, 32; +L_0x2bbf210 .part/pv L_0x2bbf9e0, 14, 1, 32; +L_0x2bbf300 .part v0x295fe90_0, 14, 1; +L_0x2bbf3a0 .part v0x2960190_0, 14, 1; +L_0x2bc0670 .part RS_0x7f507e9e4ad8, 13, 1; +L_0x2bc1620 .part/pv L_0x2bc1170, 15, 1, 32; +L_0x2bc1710 .part/pv L_0x2bc14c0, 15, 1, 32; +L_0x2bc0710 .part/pv L_0x2bc0ea0, 15, 1, 32; +L_0x2bc0800 .part v0x295fe90_0, 15, 1; +L_0x2bc08a0 .part v0x2960190_0, 15, 1; +L_0x2bc1b60 .part RS_0x7f507e9e4ad8, 14, 1; +L_0x2bc2ae0 .part/pv L_0x2bc2630, 16, 1, 32; +L_0x2bc2bd0 .part/pv L_0x2bc2980, 16, 1, 32; +L_0x2bc1c00 .part/pv L_0x2bc2360, 16, 1, 32; +L_0x2bc1cf0 .part v0x295fe90_0, 16, 1; +L_0x2bc1d90 .part v0x2960190_0, 16, 1; +L_0x2bc2fc0 .part RS_0x7f507e9e4ad8, 15, 1; +L_0x2bc40c0 .part/pv L_0x2bc3c30, 17, 1, 32; +L_0x2bc41b0 .part/pv L_0x2bc3f80, 17, 1, 32; +L_0x2bc3470 .part/pv L_0x2bc3960, 17, 1, 32; +L_0x2bc3560 .part v0x295fe90_0, 17, 1; +L_0x2bc3600 .part v0x2960190_0, 17, 1; +L_0x2bc45d0 .part RS_0x7f507e9e4ad8, 16, 1; +L_0x2bc54d0 .part/pv L_0x2bc5040, 18, 1, 32; +L_0x2bc55c0 .part/pv L_0x2bc5390, 18, 1, 32; +L_0x2bc4670 .part/pv L_0x2bc4db0, 18, 1, 32; +L_0x2bc4760 .part v0x295fe90_0, 18, 1; +L_0x2bc4800 .part v0x2960190_0, 18, 1; +L_0x2bc5a10 .part RS_0x7f507e9e4ad8, 17, 1; +L_0x2bc6940 .part/pv L_0x2bc64b0, 19, 1, 32; +L_0x2bc6a30 .part/pv L_0x2bc6800, 19, 1, 32; +L_0x2bc5ab0 .part/pv L_0x2bc61e0, 19, 1, 32; +L_0x2bc5ba0 .part v0x295fe90_0, 19, 1; +L_0x2bc5c40 .part v0x2960190_0, 19, 1; +L_0x2bc5d70 .part RS_0x7f507e9e4ad8, 18, 1; +L_0x2bc7cd0 .part/pv L_0x2bc7840, 20, 1, 32; +L_0x2bc7dc0 .part/pv L_0x2bc7b90, 20, 1, 32; +L_0x2bc6b20 .part/pv L_0x2bc7570, 20, 1, 32; +L_0x2bc6c10 .part v0x295fe90_0, 20, 1; +L_0x2bc6cb0 .part v0x2960190_0, 20, 1; +L_0x2bc6de0 .part RS_0x7f507e9e4ad8, 19, 1; +L_0x2bc9050 .part/pv L_0x2bc8bc0, 21, 1, 32; +L_0x2bc9140 .part/pv L_0x2bc8f10, 21, 1, 32; +L_0x2bc7eb0 .part/pv L_0x2bc88f0, 21, 1, 32; +L_0x2bc7fa0 .part v0x295fe90_0, 21, 1; +L_0x2bc8040 .part v0x2960190_0, 21, 1; +L_0x2bc8170 .part RS_0x7f507e9e4ad8, 20, 1; +L_0x2bca4a0 .part/pv L_0x2bc9fd0, 22, 1, 32; +L_0x2bca590 .part/pv L_0x2bca340, 22, 1, 32; +L_0x2bc9230 .part/pv L_0x2bc9d00, 22, 1, 32; +L_0x2bc9320 .part v0x295fe90_0, 22, 1; +L_0x2bc93c0 .part v0x2960190_0, 22, 1; +L_0x2bc94f0 .part RS_0x7f507e9e4ad8, 21, 1; +L_0x2bcb860 .part/pv L_0x2bcb390, 23, 1, 32; +L_0x2bcb950 .part/pv L_0x2bcb700, 23, 1, 32; +L_0x2bca680 .part/pv L_0x2bcb0c0, 23, 1, 32; +L_0x2bca770 .part v0x295fe90_0, 23, 1; +L_0x2bca810 .part v0x2960190_0, 23, 1; +L_0x2bca940 .part RS_0x7f507e9e4ad8, 22, 1; +L_0x2bccd20 .part/pv L_0x2bcc7f0, 24, 1, 32; +L_0x2bcce10 .part/pv L_0x2bccbc0, 24, 1, 32; +L_0x2bcba40 .part/pv L_0x2bcc520, 24, 1, 32; +L_0x2bcbb30 .part v0x295fe90_0, 24, 1; +L_0x2bcbbd0 .part v0x2960190_0, 24, 1; +L_0x2bcbd00 .part RS_0x7f507e9e4ad8, 23, 1; +L_0x2bce1f0 .part/pv L_0x2bcdcc0, 25, 1, 32; +L_0x2bce2e0 .part/pv L_0x2bce090, 25, 1, 32; +L_0x2bccf00 .part/pv L_0x2bcd9f0, 25, 1, 32; +L_0x2bccff0 .part v0x295fe90_0, 25, 1; +L_0x2bcd090 .part v0x2960190_0, 25, 1; +L_0x2bcd1c0 .part RS_0x7f507e9e4ad8, 24, 1; +L_0x2bcf6b0 .part/pv L_0x2bcf1e0, 26, 1, 32; +L_0x2bcf7a0 .part/pv L_0x2bcf550, 26, 1, 32; +L_0x2bce3d0 .part/pv L_0x2bcef10, 26, 1, 32; +L_0x2bce4c0 .part v0x295fe90_0, 26, 1; +L_0x2bce560 .part v0x2960190_0, 26, 1; +L_0x2bce690 .part RS_0x7f507e9e4ad8, 25, 1; +L_0x2bd0b90 .part/pv L_0x2bd06a0, 27, 1, 32; +L_0x2bd0c80 .part/pv L_0x2bd0a30, 27, 1, 32; +L_0x2bcf890 .part/pv L_0x2bd03d0, 27, 1, 32; +L_0x2bcf980 .part v0x295fe90_0, 27, 1; +L_0x2bcfa20 .part v0x2960190_0, 27, 1; +L_0x2bcfb50 .part RS_0x7f507e9e4ad8, 26, 1; +L_0x2bd2040 .part/pv L_0x2bd1b70, 28, 1, 32; +L_0x2bd2130 .part/pv L_0x2bd1ee0, 28, 1, 32; +L_0x2bd0d70 .part/pv L_0x2bd18a0, 28, 1, 32; +L_0x2bd0e60 .part v0x295fe90_0, 28, 1; +L_0x2bd0f00 .part v0x2960190_0, 28, 1; +L_0x2bd1030 .part RS_0x7f507e9e4ad8, 27, 1; +L_0x2bd3520 .part/pv L_0x2bd3020, 29, 1, 32; +L_0x2bd3610 .part/pv L_0x2bd33c0, 29, 1, 32; +L_0x2bd2220 .part/pv L_0x2bd2d20, 29, 1, 32; +L_0x2ba56b0 .part v0x295fe90_0, 29, 1; +L_0x2ba5750 .part v0x2960190_0, 29, 1; +L_0x2ba5880 .part RS_0x7f507e9e4ad8, 28, 1; +L_0x2bd4e20 .part/pv L_0x2bd3bd0, 30, 1, 32; +L_0x2bd4f10 .part/pv L_0x2bd4ce0, 30, 1, 32; +L_0x2bd4470 .part/pv L_0x2bd3900, 30, 1, 32; +L_0x2bd4560 .part v0x295fe90_0, 30, 1; +L_0x2bd4600 .part v0x2960190_0, 30, 1; +L_0x2bd4730 .part RS_0x7f507e9e4ad8, 29, 1; +L_0x2bd62e0 .part/pv L_0x2bd5dd0, 31, 1, 32; +L_0x2bd63d0 .part/pv L_0x2bd6180, 31, 1, 32; +L_0x2bd5000 .part/pv L_0x2bd5b00, 31, 1, 32; +L_0x2bd50f0 .part v0x295fe90_0, 31, 1; +L_0x2bd5190 .part v0x2960190_0, 31, 1; +L_0x2bd52c0 .part RS_0x7f507e9e4ad8, 30, 1; +L_0x2bd77c0 .part/pv L_0x2bd72b0, 0, 1, 32; +L_0x2bd78b0 .part/pv L_0x2bd7660, 0, 1, 32; +L_0x2bd64c0 .part/pv L_0x2bd6fb0, 0, 1, 32; +L_0x2bd65b0 .part v0x295fe90_0, 0, 1; +L_0x2bd6650 .part v0x2960190_0, 0, 1; +L_0x2bd6780 .part RS_0x7f507e9e4c28, 0, 1; +L_0x2bd68a0 .part RS_0x7f507e9e4ad8, 31, 1; +L_0x2b883c0 .part RS_0x7f507e9e4ad8, 30, 1; +S_0x2743c70 .scope module, "attempt2" "MiddleAddSubSLT" 3 278, 3 189, S_0x23ec510; + .timescale -9 -12; +L_0x2bd5360/d .functor NOT 1, L_0x2bd6650, C4<0>, C4<0>, C4<0>; +L_0x2bd5360 .delay (10000,10000,10000) L_0x2bd5360/d; +L_0x2bd6e70/d .functor NOT 1, L_0x2bd6f10, C4<0>, C4<0>, C4<0>; +L_0x2bd6e70 .delay (10000,10000,10000) L_0x2bd6e70/d; +L_0x2bd6fb0/d .functor AND 1, L_0x2bd70f0, L_0x2bd6e70, C4<1>, C4<1>; +L_0x2bd6fb0 .delay (20000,20000,20000) L_0x2bd6fb0/d; +L_0x2bd7190/d .functor XOR 1, L_0x2bd65b0, L_0x2bd6c40, C4<0>, C4<0>; +L_0x2bd7190 .delay (40000,40000,40000) L_0x2bd7190/d; +L_0x2bd72b0/d .functor XOR 1, L_0x2bd7190, L_0x2bd6780, C4<0>, C4<0>; +L_0x2bd72b0 .delay (40000,40000,40000) L_0x2bd72b0/d; +L_0x2bd73d0/d .functor AND 1, L_0x2bd65b0, L_0x2bd6c40, C4<1>, C4<1>; +L_0x2bd73d0 .delay (20000,20000,20000) L_0x2bd73d0/d; +L_0x2bd7570/d .functor AND 1, L_0x2bd7190, L_0x2bd6780, C4<1>, C4<1>; +L_0x2bd7570 .delay (20000,20000,20000) L_0x2bd7570/d; +L_0x2bd7660/d .functor OR 1, L_0x2bd73d0, L_0x2bd7570, C4<0>, C4<0>; +L_0x2bd7660 .delay (20000,20000,20000) L_0x2bd7660/d; +v0x27484e0_0 .net "A", 0 0, L_0x2bd65b0; 1 drivers +v0x27481a0_0 .net "AandB", 0 0, L_0x2bd73d0; 1 drivers +v0x2748240_0 .net "AddSubSLTSum", 0 0, L_0x2bd72b0; 1 drivers +v0x2749a00_0 .net "AxorB", 0 0, L_0x2bd7190; 1 drivers +v0x2749a80_0 .net "B", 0 0, L_0x2bd6650; 1 drivers +v0x2749780_0 .net "BornB", 0 0, L_0x2bd6c40; 1 drivers +v0x274afc0_0 .net "CINandAxorB", 0 0, L_0x2bd7570; 1 drivers +v0x274b040_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x274ad20_0 .net *"_s3", 0 0, L_0x2bd6f10; 1 drivers +v0x274ada0_0 .net *"_s5", 0 0, L_0x2bd70f0; 1 drivers +v0x274c580_0 .net "carryin", 0 0, L_0x2bd6780; 1 drivers +v0x274c600_0 .net "carryout", 0 0, L_0x2bd7660; 1 drivers +v0x274c300_0 .net "nB", 0 0, L_0x2bd5360; 1 drivers +v0x274db40_0 .net "nCmd2", 0 0, L_0x2bd6e70; 1 drivers +v0x274d8a0_0 .net "subtract", 0 0, L_0x2bd6fb0; 1 drivers +L_0x2bd6dd0 .part v0x2960210_0, 0, 1; +L_0x2bd6f10 .part v0x2960210_0, 2, 1; +L_0x2bd70f0 .part v0x2960210_0, 0, 1; +S_0x27458c0 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x2743c70; + .timescale -9 -12; +L_0x2bd54c0/d .functor NOT 1, L_0x2bd6dd0, C4<0>, C4<0>, C4<0>; +L_0x2bd54c0 .delay (10000,10000,10000) L_0x2bd54c0/d; +L_0x2bd6aa0/d .functor AND 1, L_0x2bd6650, L_0x2bd54c0, C4<1>, C4<1>; +L_0x2bd6aa0 .delay (20000,20000,20000) L_0x2bd6aa0/d; +L_0x2bd6b50/d .functor AND 1, L_0x2bd5360, L_0x2bd6dd0, C4<1>, C4<1>; +L_0x2bd6b50 .delay (20000,20000,20000) L_0x2bd6b50/d; +L_0x2bd6c40/d .functor OR 1, L_0x2bd6aa0, L_0x2bd6b50, C4<0>, C4<0>; +L_0x2bd6c40 .delay (20000,20000,20000) L_0x2bd6c40/d; +v0x2744100_0 .net "S", 0 0, L_0x2bd6dd0; 1 drivers +v0x2745620_0 .alias "in0", 0 0, v0x2749a80_0; +v0x27456c0_0 .alias "in1", 0 0, v0x274c300_0; +v0x2746e80_0 .net "nS", 0 0, L_0x2bd54c0; 1 drivers +v0x2746f00_0 .net "out0", 0 0, L_0x2bd6aa0; 1 drivers +v0x2746c00_0 .net "out1", 0 0, L_0x2bd6b50; 1 drivers +v0x2748440_0 .alias "outfinal", 0 0, v0x2749780_0; +S_0x2767860 .scope generate, "addbits[1]" "addbits[1]" 3 283, 3 283, S_0x23ec510; + .timescale -9 -12; +P_0x25ea758 .param/l "i" 3 283, +C4<01>; +S_0x27675f0 .scope module, "attempt" "MiddleAddSubSLT" 3 285, 3 189, S_0x2767860; + .timescale -9 -12; +L_0x2b650c0/d .functor NOT 1, L_0x2b3d690, C4<0>, C4<0>, C4<0>; +L_0x2b650c0 .delay (10000,10000,10000) L_0x2b650c0/d; +L_0x2bac850/d .functor NOT 1, L_0x2bac910, C4<0>, C4<0>, C4<0>; +L_0x2bac850 .delay (10000,10000,10000) L_0x2bac850/d; +L_0x2bac9b0/d .functor AND 1, L_0x2bacaf0, L_0x2bac850, C4<1>, C4<1>; +L_0x2bac9b0 .delay (20000,20000,20000) L_0x2bac9b0/d; +L_0x2bacb90/d .functor XOR 1, L_0x2b3d5f0, L_0x2bac5e0, C4<0>, C4<0>; +L_0x2bacb90 .delay (40000,40000,40000) L_0x2bacb90/d; +L_0x2bacc80/d .functor XOR 1, L_0x2bacb90, L_0x2baf3c0, C4<0>, C4<0>; +L_0x2bacc80 .delay (40000,40000,40000) L_0x2bacc80/d; +L_0x2bacd70/d .functor AND 1, L_0x2b3d5f0, L_0x2bac5e0, C4<1>, C4<1>; +L_0x2bacd70 .delay (20000,20000,20000) L_0x2bacd70/d; +L_0x2bacee0/d .functor AND 1, L_0x2bacb90, L_0x2baf3c0, C4<1>, C4<1>; +L_0x2bacee0 .delay (20000,20000,20000) L_0x2bacee0/d; +L_0x2bae940/d .functor OR 1, L_0x2bacd70, L_0x2bacee0, C4<0>, C4<0>; +L_0x2bae940 .delay (20000,20000,20000) L_0x2bae940/d; +v0x27400d0_0 .net "A", 0 0, L_0x2b3d5f0; 1 drivers +v0x273fb30_0 .net "AandB", 0 0, L_0x2bacd70; 1 drivers +v0x273fbd0_0 .net "AddSubSLTSum", 0 0, L_0x2bacc80; 1 drivers +v0x2741870_0 .net "AxorB", 0 0, L_0x2bacb90; 1 drivers +v0x27418f0_0 .net "B", 0 0, L_0x2b3d690; 1 drivers +v0x27415f0_0 .net "BornB", 0 0, L_0x2bac5e0; 1 drivers +v0x27410f0_0 .net "CINandAxorB", 0 0, L_0x2bacee0; 1 drivers +v0x2741170_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x2742e30_0 .net *"_s3", 0 0, L_0x2bac910; 1 drivers +v0x2742eb0_0 .net *"_s5", 0 0, L_0x2bacaf0; 1 drivers +v0x2742bb0_0 .net "carryin", 0 0, L_0x2baf3c0; 1 drivers +v0x2742c30_0 .net "carryout", 0 0, L_0x2bae940; 1 drivers +v0x27426b0_0 .net "nB", 0 0, L_0x2b650c0; 1 drivers +v0x2744300_0 .net "nCmd2", 0 0, L_0x2bac850; 1 drivers +v0x2744080_0 .net "subtract", 0 0, L_0x2bac9b0; 1 drivers +L_0x2bac7b0 .part v0x2960210_0, 0, 1; +L_0x2bac910 .part v0x2960210_0, 2, 1; +L_0x2bacaf0 .part v0x2960210_0, 0, 1; +S_0x273d400 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x27675f0; + .timescale -9 -12; +L_0x2b652b0/d .functor NOT 1, L_0x2bac7b0, C4<0>, C4<0>, C4<0>; +L_0x2b652b0 .delay (10000,10000,10000) L_0x2b652b0/d; +L_0x2b65370/d .functor AND 1, L_0x2b3d690, L_0x2b652b0, C4<1>, C4<1>; +L_0x2b65370 .delay (20000,20000,20000) L_0x2b65370/d; +L_0x2bac4d0/d .functor AND 1, L_0x2b650c0, L_0x2bac7b0, C4<1>, C4<1>; +L_0x2bac4d0 .delay (20000,20000,20000) L_0x2bac4d0/d; +L_0x2bac5e0/d .functor OR 1, L_0x2b65370, L_0x2bac4d0, C4<0>, C4<0>; +L_0x2bac5e0 .delay (20000,20000,20000) L_0x2bac5e0/d; +v0x2736710_0 .net "S", 0 0, L_0x2bac7b0; 1 drivers +v0x273ecf0_0 .alias "in0", 0 0, v0x27418f0_0; +v0x273ed90_0 .alias "in1", 0 0, v0x27426b0_0; +v0x273ea70_0 .net "nS", 0 0, L_0x2b652b0; 1 drivers +v0x273eaf0_0 .net "out0", 0 0, L_0x2b65370; 1 drivers +v0x27402b0_0 .net "out1", 0 0, L_0x2bac4d0; 1 drivers +v0x2740030_0 .alias "outfinal", 0 0, v0x27415f0_0; +S_0x272ca90 .scope generate, "addbits[2]" "addbits[2]" 3 283, 3 283, S_0x23ec510; + .timescale -9 -12; +P_0x26bf0f8 .param/l "i" 3 283, +C4<010>; +S_0x272ae50 .scope module, "attempt" "MiddleAddSubSLT" 3 285, 3 189, S_0x272ca90; + .timescale -9 -12; +L_0x2b3d730/d .functor NOT 1, L_0x2bb0700, C4<0>, C4<0>, C4<0>; +L_0x2b3d730 .delay (10000,10000,10000) L_0x2b3d730/d; +L_0x2bafa40/d .functor NOT 1, L_0x2bafae0, C4<0>, C4<0>, C4<0>; +L_0x2bafa40 .delay (10000,10000,10000) L_0x2bafa40/d; +L_0x2bafb80/d .functor AND 1, L_0x2bafcc0, L_0x2bafa40, C4<1>, C4<1>; +L_0x2bafb80 .delay (20000,20000,20000) L_0x2bafb80/d; +L_0x2bafd60/d .functor XOR 1, L_0x2bb0600, L_0x2baf810, C4<0>, C4<0>; +L_0x2bafd60 .delay (40000,40000,40000) L_0x2bafd60/d; +L_0x2bafe50/d .functor XOR 1, L_0x2bafd60, L_0x2bb0830, C4<0>, C4<0>; +L_0x2bafe50 .delay (40000,40000,40000) L_0x2bafe50/d; +L_0x2baff40/d .functor AND 1, L_0x2bb0600, L_0x2baf810, C4<1>, C4<1>; +L_0x2baff40 .delay (20000,20000,20000) L_0x2baff40/d; +L_0x2bb00b0/d .functor AND 1, L_0x2bafd60, L_0x2bb0830, C4<1>, C4<1>; +L_0x2bb00b0 .delay (20000,20000,20000) L_0x2bb00b0/d; +L_0x2bb01a0/d .functor OR 1, L_0x2baff40, L_0x2bb00b0, C4<0>, C4<0>; +L_0x2bb01a0 .delay (20000,20000,20000) L_0x2bb01a0/d; +v0x2732c40_0 .net "A", 0 0, L_0x2bb0600; 1 drivers +v0x2732940_0 .net "AandB", 0 0, L_0x2baff40; 1 drivers +v0x27329e0_0 .net "AddSubSLTSum", 0 0, L_0x2bafe50; 1 drivers +v0x2732690_0 .net "AxorB", 0 0, L_0x2bafd60; 1 drivers +v0x2732710_0 .net "B", 0 0, L_0x2bb0700; 1 drivers +v0x2730a50_0 .net "BornB", 0 0, L_0x2baf810; 1 drivers +v0x2735790_0 .net "CINandAxorB", 0 0, L_0x2bb00b0; 1 drivers +v0x2735810_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x27354e0_0 .net *"_s3", 0 0, L_0x2bafae0; 1 drivers +v0x2735560_0 .net *"_s5", 0 0, L_0x2bafcc0; 1 drivers +v0x2733850_0 .net "carryin", 0 0, L_0x2bb0830; 1 drivers +v0x27338d0_0 .net "carryout", 0 0, L_0x2bb01a0; 1 drivers +v0x27385d0_0 .net "nB", 0 0, L_0x2b3d730; 1 drivers +v0x2738320_0 .net "nCmd2", 0 0, L_0x2bafa40; 1 drivers +v0x2736690_0 .net "subtract", 0 0, L_0x2bafb80; 1 drivers +L_0x2baf9a0 .part v0x2960210_0, 0, 1; +L_0x2bafae0 .part v0x2960210_0, 2, 1; +L_0x2bafcc0 .part v0x2960210_0, 0, 1; +S_0x272fda0 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x272ae50; + .timescale -9 -12; +L_0x2baf590/d .functor NOT 1, L_0x2baf9a0, C4<0>, C4<0>, C4<0>; +L_0x2baf590 .delay (10000,10000,10000) L_0x2baf590/d; +L_0x2baf630/d .functor AND 1, L_0x2bb0700, L_0x2baf590, C4<1>, C4<1>; +L_0x2baf630 .delay (20000,20000,20000) L_0x2baf630/d; +L_0x2baf720/d .functor AND 1, L_0x2b3d730, L_0x2baf9a0, C4<1>, C4<1>; +L_0x2baf720 .delay (20000,20000,20000) L_0x2baf720/d; +L_0x2baf810/d .functor OR 1, L_0x2baf630, L_0x2baf720, C4<0>, C4<0>; +L_0x2baf810 .delay (20000,20000,20000) L_0x2baf810/d; +v0x272cdc0_0 .net "S", 0 0, L_0x2baf9a0; 1 drivers +v0x272fb40_0 .alias "in0", 0 0, v0x2732710_0; +v0x272fbe0_0 .alias "in1", 0 0, v0x27385d0_0; +v0x272f890_0 .net "nS", 0 0, L_0x2baf590; 1 drivers +v0x272f910_0 .net "out0", 0 0, L_0x2baf630; 1 drivers +v0x272dc50_0 .net "out1", 0 0, L_0x2baf720; 1 drivers +v0x2732ba0_0 .alias "outfinal", 0 0, v0x2730a50_0; +S_0x271f7d0 .scope generate, "addbits[3]" "addbits[3]" 3 283, 3 283, S_0x23ec510; + .timescale -9 -12; +P_0x26b5778 .param/l "i" 3 283, +C4<011>; +S_0x27245a0 .scope module, "attempt" "MiddleAddSubSLT" 3 285, 3 189, S_0x271f7d0; + .timescale -9 -12; +L_0x2bb06a0/d .functor NOT 1, L_0x2bb1b60, C4<0>, C4<0>, C4<0>; +L_0x2bb06a0 .delay (10000,10000,10000) L_0x2bb06a0/d; +L_0x2bb0e40/d .functor NOT 1, L_0x2bb0ee0, C4<0>, C4<0>, C4<0>; +L_0x2bb0e40 .delay (10000,10000,10000) L_0x2bb0e40/d; +L_0x2bb0f80/d .functor AND 1, L_0x2bb10c0, L_0x2bb0e40, C4<1>, C4<1>; +L_0x2bb0f80 .delay (20000,20000,20000) L_0x2bb0f80/d; +L_0x2bb1160/d .functor XOR 1, L_0x2bb1a30, L_0x2bb0c10, C4<0>, C4<0>; +L_0x2bb1160 .delay (40000,40000,40000) L_0x2bb1160/d; +L_0x2bb1250/d .functor XOR 1, L_0x2bb1160, L_0x2bb1c90, C4<0>, C4<0>; +L_0x2bb1250 .delay (40000,40000,40000) L_0x2bb1250/d; +L_0x2bb1340/d .functor AND 1, L_0x2bb1a30, L_0x2bb0c10, C4<1>, C4<1>; +L_0x2bb1340 .delay (20000,20000,20000) L_0x2bb1340/d; +L_0x2bb14b0/d .functor AND 1, L_0x2bb1160, L_0x2bb1c90, C4<1>, C4<1>; +L_0x2bb14b0 .delay (20000,20000,20000) L_0x2bb14b0/d; +L_0x2bb15a0/d .functor OR 1, L_0x2bb1340, L_0x2bb14b0, C4<0>, C4<0>; +L_0x2bb15a0 .delay (20000,20000,20000) L_0x2bb15a0/d; +v0x27271e0_0 .net "A", 0 0, L_0x2bb1a30; 1 drivers +v0x2726e90_0 .net "AandB", 0 0, L_0x2bb1340; 1 drivers +v0x2726f30_0 .net "AddSubSLTSum", 0 0, L_0x2bb1250; 1 drivers +v0x2725250_0 .net "AxorB", 0 0, L_0x2bb1160; 1 drivers +v0x27252f0_0 .net "B", 0 0, L_0x2bb1b60; 1 drivers +v0x272a1a0_0 .net "BornB", 0 0, L_0x2bb0c10; 1 drivers +v0x272a220_0 .net "CINandAxorB", 0 0, L_0x2bb14b0; 1 drivers +v0x2729f40_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x2729fc0_0 .net *"_s3", 0 0, L_0x2bb0ee0; 1 drivers +v0x2729c90_0 .net *"_s5", 0 0, L_0x2bb10c0; 1 drivers +v0x2729d10_0 .net "carryin", 0 0, L_0x2bb1c90; 1 drivers +v0x2728050_0 .net "carryout", 0 0, L_0x2bb15a0; 1 drivers +v0x27280d0_0 .net "nB", 0 0, L_0x2bb06a0; 1 drivers +v0x272cfa0_0 .net "nCmd2", 0 0, L_0x2bb0e40; 1 drivers +v0x272cd40_0 .net "subtract", 0 0, L_0x2bb0f80; 1 drivers +L_0x2bb0da0 .part v0x2960210_0, 0, 1; +L_0x2bb0ee0 .part v0x2960210_0, 2, 1; +L_0x2bb10c0 .part v0x2960210_0, 0, 1; +S_0x2724340 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x27245a0; + .timescale -9 -12; +L_0x2bb09d0/d .functor NOT 1, L_0x2bb0da0, C4<0>, C4<0>, C4<0>; +L_0x2bb09d0 .delay (10000,10000,10000) L_0x2bb09d0/d; +L_0x2bb0a30/d .functor AND 1, L_0x2bb1b60, L_0x2bb09d0, C4<1>, C4<1>; +L_0x2bb0a30 .delay (20000,20000,20000) L_0x2bb0a30/d; +L_0x2bb0b20/d .functor AND 1, L_0x2bb06a0, L_0x2bb0da0, C4<1>, C4<1>; +L_0x2bb0b20 .delay (20000,20000,20000) L_0x2bb0b20/d; +L_0x2bb0c10/d .functor OR 1, L_0x2bb0a30, L_0x2bb0b20, C4<0>, C4<0>; +L_0x2bb0c10 .delay (20000,20000,20000) L_0x2bb0c10/d; +v0x2724090_0 .net "S", 0 0, L_0x2bb0da0; 1 drivers +v0x2724110_0 .alias "in0", 0 0, v0x27252f0_0; +v0x2722610_0 .alias "in1", 0 0, v0x27280d0_0; +v0x27226b0_0 .net "nS", 0 0, L_0x2bb09d0; 1 drivers +v0x27273a0_0 .net "out0", 0 0, L_0x2bb0a30; 1 drivers +v0x2727440_0 .net "out1", 0 0, L_0x2bb0b20; 1 drivers +v0x2727140_0 .alias "outfinal", 0 0, v0x272a1a0_0; +S_0x27110d0 .scope generate, "addbits[4]" "addbits[4]" 3 283, 3 283, S_0x23ec510; + .timescale -9 -12; +P_0x2663f98 .param/l "i" 3 283, +C4<0100>; +S_0x2715e10 .scope module, "attempt" "MiddleAddSubSLT" 3 285, 3 189, S_0x27110d0; + .timescale -9 -12; +L_0x2bb1ad0/d .functor NOT 1, L_0x2bb2e60, C4<0>, C4<0>, C4<0>; +L_0x2bb1ad0 .delay (10000,10000,10000) L_0x2bb1ad0/d; +L_0x2bb23a0/d .functor NOT 1, L_0x2bb2460, C4<0>, C4<0>, C4<0>; +L_0x2bb23a0 .delay (10000,10000,10000) L_0x2bb23a0/d; +L_0x2bb2500/d .functor AND 1, L_0x2bb2640, L_0x2bb23a0, C4<1>, C4<1>; +L_0x2bb2500 .delay (20000,20000,20000) L_0x2bb2500/d; +L_0x2bb26e0/d .functor XOR 1, L_0x2bb2f60, L_0x2bb2130, C4<0>, C4<0>; +L_0x2bb26e0 .delay (40000,40000,40000) L_0x2bb26e0/d; +L_0x2bb27d0/d .functor XOR 1, L_0x2bb26e0, L_0x2bb3150, C4<0>, C4<0>; +L_0x2bb27d0 .delay (40000,40000,40000) L_0x2bb27d0/d; +L_0x2bb28c0/d .functor AND 1, L_0x2bb2f60, L_0x2bb2130, C4<1>, C4<1>; +L_0x2bb28c0 .delay (20000,20000,20000) L_0x2bb28c0/d; +L_0x2bb2a30/d .functor AND 1, L_0x2bb26e0, L_0x2bb3150, C4<1>, C4<1>; +L_0x2bb2a30 .delay (20000,20000,20000) L_0x2bb2a30/d; +L_0x2bb2b20/d .functor OR 1, L_0x2bb28c0, L_0x2bb2a30, C4<0>, C4<0>; +L_0x2bb2b20 .delay (20000,20000,20000) L_0x2bb2b20/d; +v0x2716db0_0 .net "A", 0 0, L_0x2bb2f60; 1 drivers +v0x271ba90_0 .net "AandB", 0 0, L_0x2bb28c0; 1 drivers +v0x271bb30_0 .net "AddSubSLTSum", 0 0, L_0x2bb27d0; 1 drivers +v0x271b7e0_0 .net "AxorB", 0 0, L_0x2bb26e0; 1 drivers +v0x271b860_0 .net "B", 0 0, L_0x2bb2e60; 1 drivers +v0x2719b50_0 .net "BornB", 0 0, L_0x2bb2130; 1 drivers +v0x271e8d0_0 .net "CINandAxorB", 0 0, L_0x2bb2a30; 1 drivers +v0x271e950_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x271e620_0 .net *"_s3", 0 0, L_0x2bb2460; 1 drivers +v0x271e6a0_0 .net *"_s5", 0 0, L_0x2bb2640; 1 drivers +v0x271c990_0 .net "carryin", 0 0, L_0x2bb3150; 1 drivers +v0x271ca10_0 .net "carryout", 0 0, L_0x2bb2b20; 1 drivers +v0x2721710_0 .net "nB", 0 0, L_0x2bb1ad0; 1 drivers +v0x2721790_0 .net "nCmd2", 0 0, L_0x2bb23a0; 1 drivers +v0x27214e0_0 .net "subtract", 0 0, L_0x2bb2500; 1 drivers +L_0x2bb2300 .part v0x2960210_0, 0, 1; +L_0x2bb2460 .part v0x2960210_0, 2, 1; +L_0x2bb2640 .part v0x2960210_0, 0, 1; +S_0x2715b60 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x2715e10; + .timescale -9 -12; +L_0x2bb1e90/d .functor NOT 1, L_0x2bb2300, C4<0>, C4<0>, C4<0>; +L_0x2bb1e90 .delay (10000,10000,10000) L_0x2bb1e90/d; +L_0x2bb1f10/d .functor AND 1, L_0x2bb2e60, L_0x2bb1e90, C4<1>, C4<1>; +L_0x2bb1f10 .delay (20000,20000,20000) L_0x2bb1f10/d; +L_0x2bb2020/d .functor AND 1, L_0x2bb1ad0, L_0x2bb2300, C4<1>, C4<1>; +L_0x2bb2020 .delay (20000,20000,20000) L_0x2bb2020/d; +L_0x2bb2130/d .functor OR 1, L_0x2bb1f10, L_0x2bb2020, C4<0>, C4<0>; +L_0x2bb2130 .delay (20000,20000,20000) L_0x2bb2130/d; +v0x2713ed0_0 .net "S", 0 0, L_0x2bb2300; 1 drivers +v0x2713f70_0 .alias "in0", 0 0, v0x271b860_0; +v0x2718c50_0 .alias "in1", 0 0, v0x2721710_0; +v0x2718cf0_0 .net "nS", 0 0, L_0x2bb1e90; 1 drivers +v0x27189a0_0 .net "out0", 0 0, L_0x2bb1f10; 1 drivers +v0x2718a40_0 .net "out1", 0 0, L_0x2bb2020; 1 drivers +v0x2716d10_0 .alias "outfinal", 0 0, v0x2719b50_0; +S_0x270a820 .scope generate, "addbits[5]" "addbits[5]" 3 283, 3 283, S_0x23ec510; + .timescale -9 -12; +P_0x25ccbd8 .param/l "i" 3 283, +C4<0101>; +S_0x270a5c0 .scope module, "attempt" "MiddleAddSubSLT" 3 285, 3 189, S_0x270a820; + .timescale -9 -12; +L_0x2bb08d0/d .functor NOT 1, L_0x2bb4440, C4<0>, C4<0>, C4<0>; +L_0x2bb08d0 .delay (10000,10000,10000) L_0x2bb08d0/d; +L_0x2bb3960/d .functor NOT 1, L_0x2bb3a20, C4<0>, C4<0>, C4<0>; +L_0x2bb3960 .delay (10000,10000,10000) L_0x2bb3960/d; +L_0x2bb3ac0/d .functor AND 1, L_0x2bb3c00, L_0x2bb3960, C4<1>, C4<1>; +L_0x2bb3ac0 .delay (20000,20000,20000) L_0x2bb3ac0/d; +L_0x2bb3ca0/d .functor XOR 1, L_0x2bb4570, L_0x2bb36f0, C4<0>, C4<0>; +L_0x2bb3ca0 .delay (40000,40000,40000) L_0x2bb3ca0/d; +L_0x2bb3d90/d .functor XOR 1, L_0x2bb3ca0, L_0x2bb4790, C4<0>, C4<0>; +L_0x2bb3d90 .delay (40000,40000,40000) L_0x2bb3d90/d; +L_0x2bb3e80/d .functor AND 1, L_0x2bb4570, L_0x2bb36f0, C4<1>, C4<1>; +L_0x2bb3e80 .delay (20000,20000,20000) L_0x2bb3e80/d; +L_0x2bb3ff0/d .functor AND 1, L_0x2bb3ca0, L_0x2bb4790, C4<1>, C4<1>; +L_0x2bb3ff0 .delay (20000,20000,20000) L_0x2bb3ff0/d; +L_0x2bb4100/d .functor OR 1, L_0x2bb3e80, L_0x2bb3ff0, C4<0>, C4<0>; +L_0x2bb4100 .delay (20000,20000,20000) L_0x2bb4100/d; +v0x270d1b0_0 .net "A", 0 0, L_0x2bb4570; 1 drivers +v0x270b4d0_0 .net "AandB", 0 0, L_0x2bb3e80; 1 drivers +v0x270b570_0 .net "AddSubSLTSum", 0 0, L_0x2bb3d90; 1 drivers +v0x2710420_0 .net "AxorB", 0 0, L_0x2bb3ca0; 1 drivers +v0x27104a0_0 .net "B", 0 0, L_0x2bb4440; 1 drivers +v0x27101c0_0 .net "BornB", 0 0, L_0x2bb36f0; 1 drivers +v0x270ff10_0 .net "CINandAxorB", 0 0, L_0x2bb3ff0; 1 drivers +v0x270ff90_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x270e2d0_0 .net *"_s3", 0 0, L_0x2bb3a20; 1 drivers +v0x270e350_0 .net *"_s5", 0 0, L_0x2bb3c00; 1 drivers +v0x2713220_0 .net "carryin", 0 0, L_0x2bb4790; 1 drivers +v0x27132a0_0 .net "carryout", 0 0, L_0x2bb4100; 1 drivers +v0x2712fc0_0 .net "nB", 0 0, L_0x2bb08d0; 1 drivers +v0x2713040_0 .net "nCmd2", 0 0, L_0x2bb3960; 1 drivers +v0x2712d90_0 .net "subtract", 0 0, L_0x2bb3ac0; 1 drivers +L_0x2bb38c0 .part v0x2960210_0, 0, 1; +L_0x2bb3a20 .part v0x2960210_0, 2, 1; +L_0x2bb3c00 .part v0x2960210_0, 0, 1; +S_0x270a310 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x270a5c0; + .timescale -9 -12; +L_0x2bb33f0/d .functor NOT 1, L_0x2bb38c0, C4<0>, C4<0>, C4<0>; +L_0x2bb33f0 .delay (10000,10000,10000) L_0x2bb33f0/d; +L_0x2bb34b0/d .functor AND 1, L_0x2bb4440, L_0x2bb33f0, C4<1>, C4<1>; +L_0x2bb34b0 .delay (20000,20000,20000) L_0x2bb34b0/d; +L_0x2bb35c0/d .functor AND 1, L_0x2bb08d0, L_0x2bb38c0, C4<1>, C4<1>; +L_0x2bb35c0 .delay (20000,20000,20000) L_0x2bb35c0/d; +L_0x2bb36f0/d .functor OR 1, L_0x2bb34b0, L_0x2bb35c0, C4<0>, C4<0>; +L_0x2bb36f0 .delay (20000,20000,20000) L_0x2bb36f0/d; +v0x27086d0_0 .net "S", 0 0, L_0x2bb38c0; 1 drivers +v0x2708770_0 .alias "in0", 0 0, v0x27104a0_0; +v0x270d620_0 .alias "in1", 0 0, v0x2712fc0_0; +v0x270d6c0_0 .net "nS", 0 0, L_0x2bb33f0; 1 drivers +v0x270d3c0_0 .net "out0", 0 0, L_0x2bb34b0; 1 drivers +v0x270d460_0 .net "out1", 0 0, L_0x2bb35c0; 1 drivers +v0x270d110_0 .alias "outfinal", 0 0, v0x27101c0_0; +S_0x26fa1d0 .scope generate, "addbits[6]" "addbits[6]" 3 283, 3 283, S_0x23ec510; + .timescale -9 -12; +P_0x2625158 .param/l "i" 3 283, +C4<0110>; +S_0x26fef50 .scope module, "attempt" "MiddleAddSubSLT" 3 285, 3 189, S_0x26fa1d0; + .timescale -9 -12; +L_0x2bb4610/d .functor NOT 1, L_0x2bb5990, C4<0>, C4<0>, C4<0>; +L_0x2bb4610 .delay (10000,10000,10000) L_0x2bb4610/d; +L_0x2bb4e90/d .functor NOT 1, L_0x2bb4f50, C4<0>, C4<0>, C4<0>; +L_0x2bb4e90 .delay (10000,10000,10000) L_0x2bb4e90/d; +L_0x2bb4ff0/d .functor AND 1, L_0x2bb5130, L_0x2bb4e90, C4<1>, C4<1>; +L_0x2bb4ff0 .delay (20000,20000,20000) L_0x2bb4ff0/d; +L_0x2bb51d0/d .functor XOR 1, L_0x2bb5aa0, L_0x2bb4c20, C4<0>, C4<0>; +L_0x2bb51d0 .delay (40000,40000,40000) L_0x2bb51d0/d; +L_0x2bb52c0/d .functor XOR 1, L_0x2bb51d0, L_0x2bb5cf0, C4<0>, C4<0>; +L_0x2bb52c0 .delay (40000,40000,40000) L_0x2bb52c0/d; +L_0x2bb53b0/d .functor AND 1, L_0x2bb5aa0, L_0x2bb4c20, C4<1>, C4<1>; +L_0x2bb53b0 .delay (20000,20000,20000) L_0x2bb53b0/d; +L_0x2bb5540/d .functor AND 1, L_0x2bb51d0, L_0x2bb5cf0, C4<1>, C4<1>; +L_0x2bb5540 .delay (20000,20000,20000) L_0x2bb5540/d; +L_0x2bb5650/d .functor OR 1, L_0x2bb53b0, L_0x2bb5540, C4<0>, C4<0>; +L_0x2bb5650 .delay (20000,20000,20000) L_0x2bb5650/d; +v0x26ffef0_0 .net "A", 0 0, L_0x2bb5aa0; 1 drivers +v0x2704c20_0 .net "AandB", 0 0, L_0x2bb53b0; 1 drivers +v0x2704cc0_0 .net "AddSubSLTSum", 0 0, L_0x2bb52c0; 1 drivers +v0x27049c0_0 .net "AxorB", 0 0, L_0x2bb51d0; 1 drivers +v0x2704a60_0 .net "B", 0 0, L_0x2bb5990; 1 drivers +v0x2704710_0 .net "BornB", 0 0, L_0x2bb4c20; 1 drivers +v0x2702c90_0 .net "CINandAxorB", 0 0, L_0x2bb5540; 1 drivers +v0x2702d10_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x2707a20_0 .net *"_s3", 0 0, L_0x2bb4f50; 1 drivers +v0x2707aa0_0 .net *"_s5", 0 0, L_0x2bb5130; 1 drivers +v0x27077c0_0 .net "carryin", 0 0, L_0x2bb5cf0; 1 drivers +v0x2707860_0 .net "carryout", 0 0, L_0x2bb5650; 1 drivers +v0x2707510_0 .net "nB", 0 0, L_0x2bb4610; 1 drivers +v0x2707590_0 .net "nCmd2", 0 0, L_0x2bb4e90; 1 drivers +v0x2705950_0 .net "subtract", 0 0, L_0x2bb4ff0; 1 drivers +L_0x2bb4df0 .part v0x2960210_0, 0, 1; +L_0x2bb4f50 .part v0x2960210_0, 2, 1; +L_0x2bb5130 .part v0x2960210_0, 0, 1; +S_0x26feca0 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x26fef50; + .timescale -9 -12; +L_0x2bb4980/d .functor NOT 1, L_0x2bb4df0, C4<0>, C4<0>, C4<0>; +L_0x2bb4980 .delay (10000,10000,10000) L_0x2bb4980/d; +L_0x2bb4a20/d .functor AND 1, L_0x2bb5990, L_0x2bb4980, C4<1>, C4<1>; +L_0x2bb4a20 .delay (20000,20000,20000) L_0x2bb4a20/d; +L_0x2bb4b10/d .functor AND 1, L_0x2bb4610, L_0x2bb4df0, C4<1>, C4<1>; +L_0x2bb4b10 .delay (20000,20000,20000) L_0x2bb4b10/d; +L_0x2bb4c20/d .functor OR 1, L_0x2bb4a20, L_0x2bb4b10, C4<0>, C4<0>; +L_0x2bb4c20 .delay (20000,20000,20000) L_0x2bb4c20/d; +v0x26fd010_0 .net "S", 0 0, L_0x2bb4df0; 1 drivers +v0x26fd0b0_0 .alias "in0", 0 0, v0x2704a60_0; +v0x2701d90_0 .alias "in1", 0 0, v0x2707510_0; +v0x2701e30_0 .net "nS", 0 0, L_0x2bb4980; 1 drivers +v0x2701ae0_0 .net "out0", 0 0, L_0x2bb4a20; 1 drivers +v0x2701b80_0 .net "out1", 0 0, L_0x2bb4b10; 1 drivers +v0x26ffe50_0 .alias "outfinal", 0 0, v0x2704710_0; +S_0x26f0ab0 .scope generate, "addbits[7]" "addbits[7]" 3 283, 3 283, S_0x23ec510; + .timescale -9 -12; +P_0x241de78 .param/l "i" 3 283, +C4<0111>; +S_0x26f0850 .scope module, "attempt" "MiddleAddSubSLT" 3 285, 3 189, S_0x26f0ab0; + .timescale -9 -12; +L_0x2bb5a30/d .functor NOT 1, L_0x2bb6ef0, C4<0>, C4<0>, C4<0>; +L_0x2bb5a30 .delay (10000,10000,10000) L_0x2bb5a30/d; +L_0x2bb6410/d .functor NOT 1, L_0x2bb64d0, C4<0>, C4<0>, C4<0>; +L_0x2bb6410 .delay (10000,10000,10000) L_0x2bb6410/d; +L_0x2bb6570/d .functor AND 1, L_0x2bb66b0, L_0x2bb6410, C4<1>, C4<1>; +L_0x2bb6570 .delay (20000,20000,20000) L_0x2bb6570/d; +L_0x2bb6750/d .functor XOR 1, L_0x2bb7030, L_0x2bb61a0, C4<0>, C4<0>; +L_0x2bb6750 .delay (40000,40000,40000) L_0x2bb6750/d; +L_0x2bb6840/d .functor XOR 1, L_0x2bb6750, L_0x2bb7220, C4<0>, C4<0>; +L_0x2bb6840 .delay (40000,40000,40000) L_0x2bb6840/d; +L_0x2bb6930/d .functor AND 1, L_0x2bb7030, L_0x2bb61a0, C4<1>, C4<1>; +L_0x2bb6930 .delay (20000,20000,20000) L_0x2bb6930/d; +L_0x2bb6aa0/d .functor AND 1, L_0x2bb6750, L_0x2bb7220, C4<1>, C4<1>; +L_0x2bb6aa0 .delay (20000,20000,20000) L_0x2bb6aa0/d; +L_0x2bb6bb0/d .functor OR 1, L_0x2bb6930, L_0x2bb6aa0, C4<0>, C4<0>; +L_0x2bb6bb0 .delay (20000,20000,20000) L_0x2bb6bb0/d; +v0x26f1800_0 .net "A", 0 0, L_0x2bb7030; 1 drivers +v0x26f6490_0 .net "AandB", 0 0, L_0x2bb6930; 1 drivers +v0x26f6530_0 .net "AddSubSLTSum", 0 0, L_0x2bb6840; 1 drivers +v0x26f61e0_0 .net "AxorB", 0 0, L_0x2bb6750; 1 drivers +v0x26f6260_0 .net "B", 0 0, L_0x2bb6ef0; 1 drivers +v0x26f4550_0 .net "BornB", 0 0, L_0x2bb61a0; 1 drivers +v0x26f92d0_0 .net "CINandAxorB", 0 0, L_0x2bb6aa0; 1 drivers +v0x26f9350_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x26f9020_0 .net *"_s3", 0 0, L_0x2bb64d0; 1 drivers +v0x26f90a0_0 .net *"_s5", 0 0, L_0x2bb66b0; 1 drivers +v0x26f7390_0 .net "carryin", 0 0, L_0x2bb7220; 1 drivers +v0x26f7410_0 .net "carryout", 0 0, L_0x2bb6bb0; 1 drivers +v0x26fc110_0 .net "nB", 0 0, L_0x2bb5a30; 1 drivers +v0x26fc190_0 .net "nCmd2", 0 0, L_0x2bb6410; 1 drivers +v0x26fbee0_0 .net "subtract", 0 0, L_0x2bb6570; 1 drivers +L_0x2bb6370 .part v0x2960210_0, 0, 1; +L_0x2bb64d0 .part v0x2960210_0, 2, 1; +L_0x2bb66b0 .part v0x2960210_0, 0, 1; +S_0x26f05a0 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x26f0850; + .timescale -9 -12; +L_0x2bb5ec0/d .functor NOT 1, L_0x2bb6370, C4<0>, C4<0>, C4<0>; +L_0x2bb5ec0 .delay (10000,10000,10000) L_0x2bb5ec0/d; +L_0x2bb5f60/d .functor AND 1, L_0x2bb6ef0, L_0x2bb5ec0, C4<1>, C4<1>; +L_0x2bb5f60 .delay (20000,20000,20000) L_0x2bb5f60/d; +L_0x2bb6070/d .functor AND 1, L_0x2bb5a30, L_0x2bb6370, C4<1>, C4<1>; +L_0x2bb6070 .delay (20000,20000,20000) L_0x2bb6070/d; +L_0x2bb61a0/d .functor OR 1, L_0x2bb5f60, L_0x2bb6070, C4<0>, C4<0>; +L_0x2bb61a0 .delay (20000,20000,20000) L_0x2bb61a0/d; +v0x26ee960_0 .net "S", 0 0, L_0x2bb6370; 1 drivers +v0x26eea00_0 .alias "in0", 0 0, v0x26f6260_0; +v0x26f3650_0 .alias "in1", 0 0, v0x26fc110_0; +v0x26f36f0_0 .net "nS", 0 0, L_0x2bb5ec0; 1 drivers +v0x26f33a0_0 .net "out0", 0 0, L_0x2bb5f60; 1 drivers +v0x26f3440_0 .net "out1", 0 0, L_0x2bb6070; 1 drivers +v0x26f1760_0 .alias "outfinal", 0 0, v0x26f4550_0; +S_0x26e52b0 .scope generate, "addbits[8]" "addbits[8]" 3 283, 3 283, S_0x23ec510; + .timescale -9 -12; +P_0x238d208 .param/l "i" 3 283, +C4<01000>; +S_0x26e5050 .scope module, "attempt" "MiddleAddSubSLT" 3 285, 3 189, S_0x26e52b0; + .timescale -9 -12; +L_0x2bb70d0/d .functor NOT 1, L_0x2bb8430, C4<0>, C4<0>, C4<0>; +L_0x2bb70d0 .delay (10000,10000,10000) L_0x2bb70d0/d; +L_0x2bb7950/d .functor NOT 1, L_0x2bb7a10, C4<0>, C4<0>, C4<0>; +L_0x2bb7950 .delay (10000,10000,10000) L_0x2bb7950/d; +L_0x2bb7ab0/d .functor AND 1, L_0x2bb7bf0, L_0x2bb7950, C4<1>, C4<1>; +L_0x2bb7ab0 .delay (20000,20000,20000) L_0x2bb7ab0/d; +L_0x2bb7c90/d .functor XOR 1, L_0x2bb85a0, L_0x2bb76e0, C4<0>, C4<0>; +L_0x2bb7c90 .delay (40000,40000,40000) L_0x2bb7c90/d; +L_0x2bb7d80/d .functor XOR 1, L_0x2bb7c90, L_0x2bb87c0, C4<0>, C4<0>; +L_0x2bb7d80 .delay (40000,40000,40000) L_0x2bb7d80/d; +L_0x2bb7e70/d .functor AND 1, L_0x2bb85a0, L_0x2bb76e0, C4<1>, C4<1>; +L_0x2bb7e70 .delay (20000,20000,20000) L_0x2bb7e70/d; +L_0x2bb7fe0/d .functor AND 1, L_0x2bb7c90, L_0x2bb87c0, C4<1>, C4<1>; +L_0x2bb7fe0 .delay (20000,20000,20000) L_0x2bb7fe0/d; +L_0x2bb80f0/d .functor OR 1, L_0x2bb7e70, L_0x2bb7fe0, C4<0>, C4<0>; +L_0x2bb80f0 .delay (20000,20000,20000) L_0x2bb80f0/d; +v0x26e6000_0 .net "A", 0 0, L_0x2bb85a0; 1 drivers +v0x26eaeb0_0 .net "AandB", 0 0, L_0x2bb7e70; 1 drivers +v0x26eaf50_0 .net "AddSubSLTSum", 0 0, L_0x2bb7d80; 1 drivers +v0x26eac50_0 .net "AxorB", 0 0, L_0x2bb7c90; 1 drivers +v0x26eacf0_0 .net "B", 0 0, L_0x2bb8430; 1 drivers +v0x26ea9a0_0 .net "BornB", 0 0, L_0x2bb76e0; 1 drivers +v0x26e8d60_0 .net "CINandAxorB", 0 0, L_0x2bb7fe0; 1 drivers +v0x26e8de0_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x26edcb0_0 .net *"_s3", 0 0, L_0x2bb7a10; 1 drivers +v0x26edd30_0 .net *"_s5", 0 0, L_0x2bb7bf0; 1 drivers +v0x26eda50_0 .net "carryin", 0 0, L_0x2bb87c0; 1 drivers +v0x26edaf0_0 .net "carryout", 0 0, L_0x2bb80f0; 1 drivers +v0x26ed7a0_0 .net "nB", 0 0, L_0x2bb70d0; 1 drivers +v0x26ed820_0 .net "nCmd2", 0 0, L_0x2bb7950; 1 drivers +v0x26ebbe0_0 .net "subtract", 0 0, L_0x2bb7ab0; 1 drivers +L_0x2bb78b0 .part v0x2960210_0, 0, 1; +L_0x2bb7a10 .part v0x2960210_0, 2, 1; +L_0x2bb7bf0 .part v0x2960210_0, 0, 1; +S_0x26e4da0 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x26e5050; + .timescale -9 -12; +L_0x2bb7420/d .functor NOT 1, L_0x2bb78b0, C4<0>, C4<0>, C4<0>; +L_0x2bb7420 .delay (10000,10000,10000) L_0x2bb7420/d; +L_0x2bb74c0/d .functor AND 1, L_0x2bb8430, L_0x2bb7420, C4<1>, C4<1>; +L_0x2bb74c0 .delay (20000,20000,20000) L_0x2bb74c0/d; +L_0x2bb75d0/d .functor AND 1, L_0x2bb70d0, L_0x2bb78b0, C4<1>, C4<1>; +L_0x2bb75d0 .delay (20000,20000,20000) L_0x2bb75d0/d; +L_0x2bb76e0/d .functor OR 1, L_0x2bb74c0, L_0x2bb75d0, C4<0>, C4<0>; +L_0x2bb76e0 .delay (20000,20000,20000) L_0x2bb76e0/d; +v0x26e80b0_0 .net "S", 0 0, L_0x2bb78b0; 1 drivers +v0x26e8150_0 .alias "in0", 0 0, v0x26eacf0_0; +v0x26e7e50_0 .alias "in1", 0 0, v0x26ed7a0_0; +v0x26e7ef0_0 .net "nS", 0 0, L_0x2bb7420; 1 drivers +v0x26e7ba0_0 .net "out0", 0 0, L_0x2bb74c0; 1 drivers +v0x26e7c40_0 .net "out1", 0 0, L_0x2bb75d0; 1 drivers +v0x26e5f60_0 .alias "outfinal", 0 0, v0x26ea9a0_0; +S_0x270f4f0 .scope generate, "addbits[9]" "addbits[9]" 3 283, 3 283, S_0x23ec510; + .timescale -9 -12; +P_0x23c67f8 .param/l "i" 3 283, +C4<01001>; +S_0x270cc70 .scope module, "attempt" "MiddleAddSubSLT" 3 285, 3 189, S_0x270f4f0; + .timescale -9 -12; +L_0x2bb73b0/d .functor NOT 1, L_0x2bb9c30, C4<0>, C4<0>, C4<0>; +L_0x2bb73b0 .delay (10000,10000,10000) L_0x2bb73b0/d; +L_0x2bb8fa0/d .functor NOT 1, L_0x2bb9060, C4<0>, C4<0>, C4<0>; +L_0x2bb8fa0 .delay (10000,10000,10000) L_0x2bb8fa0/d; +L_0x2bb9100/d .functor AND 1, L_0x2bb9240, L_0x2bb8fa0, C4<1>, C4<1>; +L_0x2bb9100 .delay (20000,20000,20000) L_0x2bb9100/d; +L_0x2bb92e0/d .functor XOR 1, L_0x2bb8b60, L_0x2bb8d30, C4<0>, C4<0>; +L_0x2bb92e0 .delay (40000,40000,40000) L_0x2bb92e0/d; +L_0x2bb93d0/d .functor XOR 1, L_0x2bb92e0, L_0x2bb9d60, C4<0>, C4<0>; +L_0x2bb93d0 .delay (40000,40000,40000) L_0x2bb93d0/d; +L_0x2bb94c0/d .functor AND 1, L_0x2bb8b60, L_0x2bb8d30, C4<1>, C4<1>; +L_0x2bb94c0 .delay (20000,20000,20000) L_0x2bb94c0/d; +L_0x2bb9630/d .functor AND 1, L_0x2bb92e0, L_0x2bb9d60, C4<1>, C4<1>; +L_0x2bb9630 .delay (20000,20000,20000) L_0x2bb9630/d; +L_0x2bb9740/d .functor OR 1, L_0x2bb94c0, L_0x2bb9630, C4<0>, C4<0>; +L_0x2bb9740 .delay (20000,20000,20000) L_0x2bb9740/d; +v0x2707110_0 .net "A", 0 0, L_0x2bb8b60; 1 drivers +v0x2706af0_0 .net "AandB", 0 0, L_0x2bb94c0; 1 drivers +v0x2706b90_0 .net "AddSubSLTSum", 0 0, L_0x2bb93d0; 1 drivers +v0x2704270_0 .net "AxorB", 0 0, L_0x2bb92e0; 1 drivers +v0x27042f0_0 .net "B", 0 0, L_0x2bb9c30; 1 drivers +v0x2704010_0 .net "BornB", 0 0, L_0x2bb8d30; 1 drivers +v0x2703cd0_0 .net "CINandAxorB", 0 0, L_0x2bb9630; 1 drivers +v0x2703d50_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x2701610_0 .net *"_s3", 0 0, L_0x2bb9060; 1 drivers +v0x2701690_0 .net *"_s5", 0 0, L_0x2bb9240; 1 drivers +v0x27394d0_0 .net "carryin", 0 0, L_0x2bb9d60; 1 drivers +v0x2739550_0 .net "carryout", 0 0, L_0x2bb9740; 1 drivers +v0x26e2070_0 .net "nB", 0 0, L_0x2bb73b0; 1 drivers +v0x26e20f0_0 .net "nCmd2", 0 0, L_0x2bb8fa0; 1 drivers +v0x26e03a0_0 .net "subtract", 0 0, L_0x2bb9100; 1 drivers +L_0x2bb8f00 .part v0x2960210_0, 0, 1; +L_0x2bb9060 .part v0x2960210_0, 2, 1; +L_0x2bb9240 .part v0x2960210_0, 0, 1; +S_0x270c6f0 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x270cc70; + .timescale -9 -12; +L_0x2bb8640/d .functor NOT 1, L_0x2bb8f00, C4<0>, C4<0>, C4<0>; +L_0x2bb8640 .delay (10000,10000,10000) L_0x2bb8640/d; +L_0x2bb8700/d .functor AND 1, L_0x2bb9c30, L_0x2bb8640, C4<1>, C4<1>; +L_0x2bb8700 .delay (20000,20000,20000) L_0x2bb8700/d; +L_0x2bb8c00/d .functor AND 1, L_0x2bb73b0, L_0x2bb8f00, C4<1>, C4<1>; +L_0x2bb8c00 .delay (20000,20000,20000) L_0x2bb8c00/d; +L_0x2bb8d30/d .functor OR 1, L_0x2bb8700, L_0x2bb8c00, C4<0>, C4<0>; +L_0x2bb8d30 .delay (20000,20000,20000) L_0x2bb8d30/d; +v0x2709e70_0 .net "S", 0 0, L_0x2bb8f00; 1 drivers +v0x2709f10_0 .alias "in0", 0 0, v0x27042f0_0; +v0x26e4900_0 .alias "in1", 0 0, v0x26e2070_0; +v0x26e49a0_0 .net "nS", 0 0, L_0x2bb8640; 1 drivers +v0x27098f0_0 .net "out0", 0 0, L_0x2bb8700; 1 drivers +v0x2709990_0 .net "out1", 0 0, L_0x2bb8c00; 1 drivers +v0x2707070_0 .alias "outfinal", 0 0, v0x2704010_0; +S_0x272c070 .scope generate, "addbits[10]" "addbits[10]" 3 283, 3 283, S_0x23ec510; + .timescale -9 -12; +P_0x24068e8 .param/l "i" 3 283, +C4<01010>; +S_0x27297f0 .scope module, "attempt" "MiddleAddSubSLT" 3 285, 3 189, S_0x272c070; + .timescale -9 -12; +L_0x2bb9a80/d .functor NOT 1, L_0x2bbb1b0, C4<0>, C4<0>, C4<0>; +L_0x2bb9a80 .delay (10000,10000,10000) L_0x2bb9a80/d; +L_0x2bba4f0/d .functor NOT 1, L_0x2bba5b0, C4<0>, C4<0>, C4<0>; +L_0x2bba4f0 .delay (10000,10000,10000) L_0x2bba4f0/d; +L_0x2bba650/d .functor AND 1, L_0x2bba790, L_0x2bba4f0, C4<1>, C4<1>; +L_0x2bba650 .delay (20000,20000,20000) L_0x2bba650/d; +L_0x2bba830/d .functor XOR 1, L_0x2bb9ef0, L_0x2bba280, C4<0>, C4<0>; +L_0x2bba830 .delay (40000,40000,40000) L_0x2bba830/d; +L_0x2bba920/d .functor XOR 1, L_0x2bba830, L_0x2bbb2e0, C4<0>, C4<0>; +L_0x2bba920 .delay (40000,40000,40000) L_0x2bba920/d; +L_0x2bbaa10/d .functor AND 1, L_0x2bb9ef0, L_0x2bba280, C4<1>, C4<1>; +L_0x2bbaa10 .delay (20000,20000,20000) L_0x2bbaa10/d; +L_0x2bbab80/d .functor AND 1, L_0x2bba830, L_0x2bbb2e0, C4<1>, C4<1>; +L_0x2bbab80 .delay (20000,20000,20000) L_0x2bbab80/d; +L_0x2bbac90/d .functor OR 1, L_0x2bbaa10, L_0x2bbab80, C4<0>, C4<0>; +L_0x2bbac90 .delay (20000,20000,20000) L_0x2bbac90/d; +v0x2721030_0 .net "A", 0 0, L_0x2bb9ef0; 1 drivers +v0x271e150_0 .net "AandB", 0 0, L_0x2bbaa10; 1 drivers +v0x271e1f0_0 .net "AddSubSLTSum", 0 0, L_0x2bba920; 1 drivers +v0x271b310_0 .net "AxorB", 0 0, L_0x2bba830; 1 drivers +v0x271b3b0_0 .net "B", 0 0, L_0x2bbb1b0; 1 drivers +v0x26e7180_0 .net "BornB", 0 0, L_0x2bba280; 1 drivers +v0x27184d0_0 .net "CINandAxorB", 0 0, L_0x2bbab80; 1 drivers +v0x2718550_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x2715690_0 .net *"_s3", 0 0, L_0x2bba5b0; 1 drivers +v0x2715710_0 .net *"_s5", 0 0, L_0x2bba790; 1 drivers +v0x2712870_0 .net "carryin", 0 0, L_0x2bbb2e0; 1 drivers +v0x2712910_0 .net "carryout", 0 0, L_0x2bbac90; 1 drivers +v0x27122f0_0 .net "nB", 0 0, L_0x2bb9a80; 1 drivers +v0x2712370_0 .net "nCmd2", 0 0, L_0x2bba4f0; 1 drivers +v0x270faf0_0 .net "subtract", 0 0, L_0x2bba650; 1 drivers +L_0x2bba450 .part v0x2960210_0, 0, 1; +L_0x2bba5b0 .part v0x2960210_0, 2, 1; +L_0x2bba790 .part v0x2960210_0, 0, 1; +S_0x2729270 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x27297f0; + .timescale -9 -12; +L_0x2bb9fc0/d .functor NOT 1, L_0x2bba450, C4<0>, C4<0>, C4<0>; +L_0x2bb9fc0 .delay (10000,10000,10000) L_0x2bb9fc0/d; +L_0x2bba060/d .functor AND 1, L_0x2bbb1b0, L_0x2bb9fc0, C4<1>, C4<1>; +L_0x2bba060 .delay (20000,20000,20000) L_0x2bba060/d; +L_0x2bba150/d .functor AND 1, L_0x2bb9a80, L_0x2bba450, C4<1>, C4<1>; +L_0x2bba150 .delay (20000,20000,20000) L_0x2bba150/d; +L_0x2bba280/d .functor OR 1, L_0x2bba060, L_0x2bba150, C4<0>, C4<0>; +L_0x2bba280 .delay (20000,20000,20000) L_0x2bba280/d; +v0x27269f0_0 .net "S", 0 0, L_0x2bba450; 1 drivers +v0x2726a90_0 .alias "in0", 0 0, v0x271b3b0_0; +v0x26e7700_0 .alias "in1", 0 0, v0x27122f0_0; +v0x26e77a0_0 .net "nS", 0 0, L_0x2bb9fc0; 1 drivers +v0x2726470_0 .net "out0", 0 0, L_0x2bba060; 1 drivers +v0x2726510_0 .net "out1", 0 0, L_0x2bba150; 1 drivers +v0x2720f90_0 .alias "outfinal", 0 0, v0x26e7180_0; +S_0x26e1ba0 .scope generate, "addbits[11]" "addbits[11]" 3 283, 3 283, S_0x23ec510; + .timescale -9 -12; +P_0x2210ba8 .param/l "i" 3 283, +C4<01011>; +S_0x26ecd80 .scope module, "attempt" "MiddleAddSubSLT" 3 285, 3 189, S_0x26e1ba0; + .timescale -9 -12; +L_0x2bbafd0/d .functor NOT 1, L_0x2bbc6f0, C4<0>, C4<0>, C4<0>; +L_0x2bbafd0 .delay (10000,10000,10000) L_0x2bbafd0/d; +L_0x2bbba20/d .functor NOT 1, L_0x2bbbae0, C4<0>, C4<0>, C4<0>; +L_0x2bbba20 .delay (10000,10000,10000) L_0x2bbba20/d; +L_0x2bbbb80/d .functor AND 1, L_0x2bbbcc0, L_0x2bbba20, C4<1>, C4<1>; +L_0x2bbbb80 .delay (20000,20000,20000) L_0x2bbbb80/d; +L_0x2bbbd60/d .functor XOR 1, L_0x2bbb470, L_0x2bbb7b0, C4<0>, C4<0>; +L_0x2bbbd60 .delay (40000,40000,40000) L_0x2bbbd60/d; +L_0x2bbbe50/d .functor XOR 1, L_0x2bbbd60, L_0x2bbc820, C4<0>, C4<0>; +L_0x2bbbe50 .delay (40000,40000,40000) L_0x2bbbe50/d; +L_0x2bbbf40/d .functor AND 1, L_0x2bbb470, L_0x2bbb7b0, C4<1>, C4<1>; +L_0x2bbbf40 .delay (20000,20000,20000) L_0x2bbbf40/d; +L_0x2bbc0b0/d .functor AND 1, L_0x2bbbd60, L_0x2bbc820, C4<1>, C4<1>; +L_0x2bbc0b0 .delay (20000,20000,20000) L_0x2bbc0b0/d; +L_0x2bbc1a0/d .functor OR 1, L_0x2bbbf40, L_0x2bbc0b0, C4<0>, C4<0>; +L_0x2bbc1a0 .delay (20000,20000,20000) L_0x2bbc1a0/d; +v0x273ac90_0 .net "A", 0 0, L_0x2bbb470; 1 drivers +v0x2737e50_0 .net "AandB", 0 0, L_0x2bbbf40; 1 drivers +v0x2737ef0_0 .net "AddSubSLTSum", 0 0, L_0x2bbbe50; 1 drivers +v0x26e9f80_0 .net "AxorB", 0 0, L_0x2bbbd60; 1 drivers +v0x26ea000_0 .net "B", 0 0, L_0x2bbc6f0; 1 drivers +v0x2735010_0 .net "BornB", 0 0, L_0x2bbb7b0; 1 drivers +v0x27321f0_0 .net "CINandAxorB", 0 0, L_0x2bbc0b0; 1 drivers +v0x2732270_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x2731c70_0 .net *"_s3", 0 0, L_0x2bbbae0; 1 drivers +v0x2731cf0_0 .net *"_s5", 0 0, L_0x2bbbcc0; 1 drivers +v0x272f3f0_0 .net "carryin", 0 0, L_0x2bbc820; 1 drivers +v0x272f470_0 .net "carryout", 0 0, L_0x2bbc1a0; 1 drivers +v0x272ee70_0 .net "nB", 0 0, L_0x2bbafd0; 1 drivers +v0x272eef0_0 .net "nCmd2", 0 0, L_0x2bbba20; 1 drivers +v0x272c670_0 .net "subtract", 0 0, L_0x2bbbb80; 1 drivers +L_0x2bbb980 .part v0x2960210_0, 0, 1; +L_0x2bbbae0 .part v0x2960210_0, 2, 1; +L_0x2bbbcc0 .part v0x2960210_0, 0, 1; +S_0x26ea500 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x26ecd80; + .timescale -9 -12; +L_0x2bbb130/d .functor NOT 1, L_0x2bbb980, C4<0>, C4<0>, C4<0>; +L_0x2bbb130 .delay (10000,10000,10000) L_0x2bbb130/d; +L_0x2bbb5b0/d .functor AND 1, L_0x2bbc6f0, L_0x2bbb130, C4<1>, C4<1>; +L_0x2bbb5b0 .delay (20000,20000,20000) L_0x2bbb5b0/d; +L_0x2bbb6a0/d .functor AND 1, L_0x2bbafd0, L_0x2bbb980, C4<1>, C4<1>; +L_0x2bbb6a0 .delay (20000,20000,20000) L_0x2bbb6a0/d; +L_0x2bbb7b0/d .functor OR 1, L_0x2bbb5b0, L_0x2bbb6a0, C4<0>, C4<0>; +L_0x2bbb7b0 .delay (20000,20000,20000) L_0x2bbb7b0/d; +v0x26ed380_0 .net "S", 0 0, L_0x2bbb980; 1 drivers +v0x273b660_0 .alias "in0", 0 0, v0x26ea000_0; +v0x273b700_0 .alias "in1", 0 0, v0x272ee70_0; +v0x273b3f0_0 .net "nS", 0 0, L_0x2bbb130; 1 drivers +v0x273b470_0 .net "out0", 0 0, L_0x2bbb5b0; 1 drivers +v0x273b150_0 .net "out1", 0 0, L_0x2bbb6a0; 1 drivers +v0x273b1f0_0 .alias "outfinal", 0 0, v0x2735010_0; +S_0x26d8330 .scope generate, "addbits[12]" "addbits[12]" 3 283, 3 283, S_0x23ec510; + .timescale -9 -12; +P_0x2253de8 .param/l "i" 3 283, +C4<01100>; +S_0x26d8080 .scope module, "attempt" "MiddleAddSubSLT" 3 285, 3 189, S_0x26d8330; + .timescale -9 -12; +L_0x2bbb510/d .functor NOT 1, L_0x2bbdbf0, C4<0>, C4<0>, C4<0>; +L_0x2bbb510 .delay (10000,10000,10000) L_0x2bbb510/d; +L_0x2bbcef0/d .functor NOT 1, L_0x2bbcfb0, C4<0>, C4<0>, C4<0>; +L_0x2bbcef0 .delay (10000,10000,10000) L_0x2bbcef0/d; +L_0x2bbd050/d .functor AND 1, L_0x2bbd190, L_0x2bbcef0, C4<1>, C4<1>; +L_0x2bbd050 .delay (20000,20000,20000) L_0x2bbd050/d; +L_0x2bbd230/d .functor XOR 1, L_0x2bbc9b0, L_0x2bbcc80, C4<0>, C4<0>; +L_0x2bbd230 .delay (40000,40000,40000) L_0x2bbd230/d; +L_0x2bbd320/d .functor XOR 1, L_0x2bbd230, L_0x2bbdc90, C4<0>, C4<0>; +L_0x2bbd320 .delay (40000,40000,40000) L_0x2bbd320/d; +L_0x2bbd410/d .functor AND 1, L_0x2bbc9b0, L_0x2bbcc80, C4<1>, C4<1>; +L_0x2bbd410 .delay (20000,20000,20000) L_0x2bbd410/d; +L_0x2bbd580/d .functor AND 1, L_0x2bbd230, L_0x2bbdc90, C4<1>, C4<1>; +L_0x2bbd580 .delay (20000,20000,20000) L_0x2bbd580/d; +L_0x2bbd670/d .functor OR 1, L_0x2bbd410, L_0x2bbd580, C4<0>, C4<0>; +L_0x2bbd670 .delay (20000,20000,20000) L_0x2bbd670/d; +v0x26e4380_0 .net "A", 0 0, L_0x2bbc9b0; 1 drivers +v0x26fb990_0 .net "AandB", 0 0, L_0x2bbd410; 1 drivers +v0x26fba30_0 .net "AddSubSLTSum", 0 0, L_0x2bbd320; 1 drivers +v0x26f8b50_0 .net "AxorB", 0 0, L_0x2bbd230; 1 drivers +v0x26f8bd0_0 .net "B", 0 0, L_0x2bbdbf0; 1 drivers +v0x26f5d10_0 .net "BornB", 0 0, L_0x2bbcc80; 1 drivers +v0x26f5d90_0 .net "CINandAxorB", 0 0, L_0x2bbd580; 1 drivers +v0x26f2f00_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x26f2f80_0 .net *"_s3", 0 0, L_0x2bbcfb0; 1 drivers +v0x26f2980_0 .net *"_s5", 0 0, L_0x2bbd190; 1 drivers +v0x26f2a00_0 .net "carryin", 0 0, L_0x2bbdc90; 1 drivers +v0x26f0100_0 .net "carryout", 0 0, L_0x2bbd670; 1 drivers +v0x26f0180_0 .net "nB", 0 0, L_0x2bbb510; 1 drivers +v0x26efb80_0 .net "nCmd2", 0 0, L_0x2bbcef0; 1 drivers +v0x26ed300_0 .net "subtract", 0 0, L_0x2bbd050; 1 drivers +L_0x2bbce50 .part v0x2960210_0, 0, 1; +L_0x2bbcfb0 .part v0x2960210_0, 2, 1; +L_0x2bbd190 .part v0x2960210_0, 0, 1; +S_0x26d6260 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x26d8080; + .timescale -9 -12; +L_0x2bbc5e0/d .functor NOT 1, L_0x2bbce50, C4<0>, C4<0>, C4<0>; +L_0x2bbc5e0 .delay (10000,10000,10000) L_0x2bbc5e0/d; +L_0x2bbc660/d .functor AND 1, L_0x2bbdbf0, L_0x2bbc5e0, C4<1>, C4<1>; +L_0x2bbc660 .delay (20000,20000,20000) L_0x2bbc660/d; +L_0x2bbcb70/d .functor AND 1, L_0x2bbb510, L_0x2bbce50, C4<1>, C4<1>; +L_0x2bbcb70 .delay (20000,20000,20000) L_0x2bbcb70/d; +L_0x2bbcc80/d .functor OR 1, L_0x2bbc660, L_0x2bbcb70, C4<0>, C4<0>; +L_0x2bbcc80 .delay (20000,20000,20000) L_0x2bbcc80/d; +v0x26cf720_0 .net "S", 0 0, L_0x2bbce50; 1 drivers +v0x26d5fb0_0 .alias "in0", 0 0, v0x26f8bd0_0; +v0x26d6050_0 .alias "in1", 0 0, v0x26f0180_0; +v0x26d4320_0 .net "nS", 0 0, L_0x2bbc5e0; 1 drivers +v0x26d43a0_0 .net "out0", 0 0, L_0x2bbc660; 1 drivers +v0x26fe7d0_0 .net "out1", 0 0, L_0x2bbcb70; 1 drivers +v0x26fe870_0 .alias "outfinal", 0 0, v0x26f5d10_0; +S_0x26c7cb0 .scope generate, "addbits[13]" "addbits[13]" 3 283, 3 283, S_0x23ec510; + .timescale -9 -12; +P_0x2237d68 .param/l "i" 3 283, +C4<01101>; +S_0x26c7a00 .scope module, "attempt" "MiddleAddSubSLT" 3 285, 3 189, S_0x26c7cb0; + .timescale -9 -12; +L_0x2bbd9b0/d .functor NOT 1, L_0x2bbdec0, C4<0>, C4<0>, C4<0>; +L_0x2bbd9b0 .delay (10000,10000,10000) L_0x2bbd9b0/d; +L_0x2bbe3b0/d .functor NOT 1, L_0x2bbe470, C4<0>, C4<0>, C4<0>; +L_0x2bbe3b0 .delay (10000,10000,10000) L_0x2bbe3b0/d; +L_0x2bbe510/d .functor AND 1, L_0x2bbe650, L_0x2bbe3b0, C4<1>, C4<1>; +L_0x2bbe510 .delay (20000,20000,20000) L_0x2bbe510/d; +L_0x2bbe6f0/d .functor XOR 1, L_0x2bbde20, L_0x2bbe140, C4<0>, C4<0>; +L_0x2bbe6f0 .delay (40000,40000,40000) L_0x2bbe6f0/d; +L_0x2bbe7e0/d .functor XOR 1, L_0x2bbe6f0, L_0x2bbf170, C4<0>, C4<0>; +L_0x2bbe7e0 .delay (40000,40000,40000) L_0x2bbe7e0/d; +L_0x2bbe8d0/d .functor AND 1, L_0x2bbde20, L_0x2bbe140, C4<1>, C4<1>; +L_0x2bbe8d0 .delay (20000,20000,20000) L_0x2bbe8d0/d; +L_0x2bbea40/d .functor AND 1, L_0x2bbe6f0, L_0x2bbf170, C4<1>, C4<1>; +L_0x2bbea40 .delay (20000,20000,20000) L_0x2bbea40/d; +L_0x2bbeb30/d .functor OR 1, L_0x2bbe8d0, L_0x2bbea40, C4<0>, C4<0>; +L_0x2bbeb30 .delay (20000,20000,20000) L_0x2bbeb30/d; +v0x26cc920_0 .net "A", 0 0, L_0x2bbde20; 1 drivers +v0x26cc670_0 .net "AandB", 0 0, L_0x2bbe8d0; 1 drivers +v0x26cc710_0 .net "AddSubSLTSum", 0 0, L_0x2bbe7e0; 1 drivers +v0x26caa30_0 .net "AxorB", 0 0, L_0x2bbe6f0; 1 drivers +v0x26caab0_0 .net "B", 0 0, L_0x2bbdec0; 1 drivers +v0x26d3680_0 .net "BornB", 0 0, L_0x2bbe140; 1 drivers +v0x26d3700_0 .net "CINandAxorB", 0 0, L_0x2bbea40; 1 drivers +v0x26d33d0_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x26d3450_0 .net *"_s3", 0 0, L_0x2bbe470; 1 drivers +v0x26d17f0_0 .net *"_s5", 0 0, L_0x2bbe650; 1 drivers +v0x26d1870_0 .net "carryin", 0 0, L_0x2bbf170; 1 drivers +v0x26d1590_0 .net "carryout", 0 0, L_0x2bbeb30; 1 drivers +v0x26d1610_0 .net "nB", 0 0, L_0x2bbd9b0; 1 drivers +v0x26d12e0_0 .net "nCmd2", 0 0, L_0x2bbe3b0; 1 drivers +v0x26cf6a0_0 .net "subtract", 0 0, L_0x2bbe510; 1 drivers +L_0x2bbe310 .part v0x2960210_0, 0, 1; +L_0x2bbe470 .part v0x2960210_0, 2, 1; +L_0x2bbe650 .part v0x2960210_0, 0, 1; +S_0x26c5dc0 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x26c7a00; + .timescale -9 -12; +L_0x2bbdb10/d .functor NOT 1, L_0x2bbe310, C4<0>, C4<0>, C4<0>; +L_0x2bbdb10 .delay (10000,10000,10000) L_0x2bbdb10/d; +L_0x2bbdb90/d .functor AND 1, L_0x2bbdec0, L_0x2bbdb10, C4<1>, C4<1>; +L_0x2bbdb90 .delay (20000,20000,20000) L_0x2bbdb90/d; +L_0x2bbe030/d .functor AND 1, L_0x2bbd9b0, L_0x2bbe310, C4<1>, C4<1>; +L_0x2bbe030 .delay (20000,20000,20000) L_0x2bbe030/d; +L_0x2bbe140/d .functor OR 1, L_0x2bbdb90, L_0x2bbe030, C4<0>, C4<0>; +L_0x2bbe140 .delay (20000,20000,20000) L_0x2bbe140/d; +v0x26c7f90_0 .net "S", 0 0, L_0x2bbe310; 1 drivers +v0x26cea00_0 .alias "in0", 0 0, v0x26caab0_0; +v0x26ceaa0_0 .alias "in1", 0 0, v0x26d1610_0; +v0x26ce750_0 .net "nS", 0 0, L_0x2bbdb10; 1 drivers +v0x26ce7d0_0 .net "out0", 0 0, L_0x2bbdb90; 1 drivers +v0x26ccb80_0 .net "out1", 0 0, L_0x2bbe030; 1 drivers +v0x26ccc20_0 .alias "outfinal", 0 0, v0x26d3680_0; +S_0x26b9570 .scope generate, "addbits[14]" "addbits[14]" 3 283, 3 283, S_0x23ec510; + .timescale -9 -12; +P_0x22062e8 .param/l "i" 3 283, +C4<01110>; +S_0x26b78e0 .scope module, "attempt" "MiddleAddSubSLT" 3 285, 3 189, S_0x26b9570; + .timescale -9 -12; +L_0x2bbee70/d .functor NOT 1, L_0x2bbf3a0, C4<0>, C4<0>, C4<0>; +L_0x2bbee70 .delay (10000,10000,10000) L_0x2bbee70/d; +L_0x2bbf880/d .functor NOT 1, L_0x2bbf940, C4<0>, C4<0>, C4<0>; +L_0x2bbf880 .delay (10000,10000,10000) L_0x2bbf880/d; +L_0x2bbf9e0/d .functor AND 1, L_0x2bbfb20, L_0x2bbf880, C4<1>, C4<1>; +L_0x2bbf9e0 .delay (20000,20000,20000) L_0x2bbf9e0/d; +L_0x2bbfbc0/d .functor XOR 1, L_0x2bbf300, L_0x2bbf610, C4<0>, C4<0>; +L_0x2bbfbc0 .delay (40000,40000,40000) L_0x2bbfbc0/d; +L_0x2bbfcb0/d .functor XOR 1, L_0x2bbfbc0, L_0x2bc0670, C4<0>, C4<0>; +L_0x2bbfcb0 .delay (40000,40000,40000) L_0x2bbfcb0/d; +L_0x2bbfda0/d .functor AND 1, L_0x2bbf300, L_0x2bbf610, C4<1>, C4<1>; +L_0x2bbfda0 .delay (20000,20000,20000) L_0x2bbfda0/d; +L_0x2bbff10/d .functor AND 1, L_0x2bbfbc0, L_0x2bc0670, C4<1>, C4<1>; +L_0x2bbff10 .delay (20000,20000,20000) L_0x2bbff10/d; +L_0x2bc0000/d .functor OR 1, L_0x2bbfda0, L_0x2bbff10, C4<0>, C4<0>; +L_0x2bc0000 .delay (20000,20000,20000) L_0x2bc0000/d; +v0x26bc590_0 .net "A", 0 0, L_0x2bbf300; 1 drivers +v0x26c5120_0 .net "AandB", 0 0, L_0x2bbfda0; 1 drivers +v0x26c51c0_0 .net "AddSubSLTSum", 0 0, L_0x2bbfcb0; 1 drivers +v0x26c4e70_0 .net "AxorB", 0 0, L_0x2bbfbc0; 1 drivers +v0x26c4ef0_0 .net "B", 0 0, L_0x2bbf3a0; 1 drivers +v0x26c3290_0 .net "BornB", 0 0, L_0x2bbf610; 1 drivers +v0x26c3310_0 .net "CINandAxorB", 0 0, L_0x2bbff10; 1 drivers +v0x26c3030_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x26c30b0_0 .net *"_s3", 0 0, L_0x2bbf940; 1 drivers +v0x26c1240_0 .net *"_s5", 0 0, L_0x2bbfb20; 1 drivers +v0x26c12c0_0 .net "carryin", 0 0, L_0x2bc0670; 1 drivers +v0x26c9d90_0 .net "carryout", 0 0, L_0x2bc0000; 1 drivers +v0x26c9e10_0 .net "nB", 0 0, L_0x2bbee70; 1 drivers +v0x26c9ae0_0 .net "nCmd2", 0 0, L_0x2bbf880; 1 drivers +v0x26c7f10_0 .net "subtract", 0 0, L_0x2bbf9e0; 1 drivers +L_0x2bbf7e0 .part v0x2960210_0, 0, 1; +L_0x2bbf940 .part v0x2960210_0, 2, 1; +L_0x2bbfb20 .part v0x2960210_0, 0, 1; +S_0x26c05a0 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x26b78e0; + .timescale -9 -12; +L_0x2bbefb0/d .functor NOT 1, L_0x2bbf7e0, C4<0>, C4<0>, C4<0>; +L_0x2bbefb0 .delay (10000,10000,10000) L_0x2bbefb0/d; +L_0x2bbf030/d .functor AND 1, L_0x2bbf3a0, L_0x2bbefb0, C4<1>, C4<1>; +L_0x2bbf030 .delay (20000,20000,20000) L_0x2bbf030/d; +L_0x2bbf520/d .functor AND 1, L_0x2bbee70, L_0x2bbf7e0, C4<1>, C4<1>; +L_0x2bbf520 .delay (20000,20000,20000) L_0x2bbf520/d; +L_0x2bbf610/d .functor OR 1, L_0x2bbf030, L_0x2bbf520, C4<0>, C4<0>; +L_0x2bbf610 .delay (20000,20000,20000) L_0x2bbf610/d; +v0x26b98a0_0 .net "S", 0 0, L_0x2bbf7e0; 1 drivers +v0x26c02f0_0 .alias "in0", 0 0, v0x26c4ef0_0; +v0x26c0390_0 .alias "in1", 0 0, v0x26c9e10_0; +v0x26be4d0_0 .net "nS", 0 0, L_0x2bbefb0; 1 drivers +v0x26be550_0 .net "out0", 0 0, L_0x2bbf030; 1 drivers +v0x26be220_0 .net "out1", 0 0, L_0x2bbf520; 1 drivers +v0x26be2c0_0 .alias "outfinal", 0 0, v0x26c3290_0; +S_0x26a9350 .scope generate, "addbits[15]" "addbits[15]" 3 283, 3 283, S_0x23ec510; + .timescale -9 -12; +P_0x22117c8 .param/l "i" 3 283, +C4<01111>; +S_0x26b1f90 .scope module, "attempt" "MiddleAddSubSLT" 3 285, 3 189, S_0x26a9350; + .timescale -9 -12; +L_0x2bc0340/d .functor NOT 1, L_0x2bc08a0, C4<0>, C4<0>, C4<0>; +L_0x2bc0340 .delay (10000,10000,10000) L_0x2bc0340/d; +L_0x2bc0d40/d .functor NOT 1, L_0x2bc0e00, C4<0>, C4<0>, C4<0>; +L_0x2bc0d40 .delay (10000,10000,10000) L_0x2bc0d40/d; +L_0x2bc0ea0/d .functor AND 1, L_0x2bc0fe0, L_0x2bc0d40, C4<1>, C4<1>; +L_0x2bc0ea0 .delay (20000,20000,20000) L_0x2bc0ea0/d; +L_0x2bc1080/d .functor XOR 1, L_0x2bc0800, L_0x2bc0ad0, C4<0>, C4<0>; +L_0x2bc1080 .delay (40000,40000,40000) L_0x2bc1080/d; +L_0x2bc1170/d .functor XOR 1, L_0x2bc1080, L_0x2bc1b60, C4<0>, C4<0>; +L_0x2bc1170 .delay (40000,40000,40000) L_0x2bc1170/d; +L_0x2bc1260/d .functor AND 1, L_0x2bc0800, L_0x2bc0ad0, C4<1>, C4<1>; +L_0x2bc1260 .delay (20000,20000,20000) L_0x2bc1260/d; +L_0x2bc13d0/d .functor AND 1, L_0x2bc1080, L_0x2bc1b60, C4<1>, C4<1>; +L_0x2bc13d0 .delay (20000,20000,20000) L_0x2bc13d0/d; +L_0x2bc14c0/d .functor OR 1, L_0x2bc1260, L_0x2bc13d0, C4<0>, C4<0>; +L_0x2bc14c0 .delay (20000,20000,20000) L_0x2bc14c0/d; +v0x26adfc0_0 .net "A", 0 0, L_0x2bc0800; 1 drivers +v0x26b6c40_0 .net "AandB", 0 0, L_0x2bc1260; 1 drivers +v0x26b6ce0_0 .net "AddSubSLTSum", 0 0, L_0x2bc1170; 1 drivers +v0x26b6990_0 .net "AxorB", 0 0, L_0x2bc1080; 1 drivers +v0x26b6a10_0 .net "B", 0 0, L_0x2bc08a0; 1 drivers +v0x26b4b70_0 .net "BornB", 0 0, L_0x2bc0ad0; 1 drivers +v0x26b4bf0_0 .net "CINandAxorB", 0 0, L_0x2bc13d0; 1 drivers +v0x26b48c0_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x26b4940_0 .net *"_s3", 0 0, L_0x2bc0e00; 1 drivers +v0x26b2c30_0 .net *"_s5", 0 0, L_0x2bc0fe0; 1 drivers +v0x26b2cb0_0 .net "carryin", 0 0, L_0x2bc1b60; 1 drivers +v0x26bb8f0_0 .net "carryout", 0 0, L_0x2bc14c0; 1 drivers +v0x26bb970_0 .net "nB", 0 0, L_0x2bc0340; 1 drivers +v0x26bb640_0 .net "nCmd2", 0 0, L_0x2bc0d40; 1 drivers +v0x26b9820_0 .net "subtract", 0 0, L_0x2bc0ea0; 1 drivers +L_0x2bc0ca0 .part v0x2960210_0, 0, 1; +L_0x2bc0e00 .part v0x2960210_0, 2, 1; +L_0x2bc0fe0 .part v0x2960210_0, 0, 1; +S_0x26b1ce0 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x26b1f90; + .timescale -9 -12; +L_0x2bc0450/d .functor NOT 1, L_0x2bc0ca0, C4<0>, C4<0>, C4<0>; +L_0x2bc0450 .delay (10000,10000,10000) L_0x2bc0450/d; +L_0x2bc04d0/d .functor AND 1, L_0x2bc08a0, L_0x2bc0450, C4<1>, C4<1>; +L_0x2bc04d0 .delay (20000,20000,20000) L_0x2bc04d0/d; +L_0x2bc09c0/d .functor AND 1, L_0x2bc0340, L_0x2bc0ca0, C4<1>, C4<1>; +L_0x2bc09c0 .delay (20000,20000,20000) L_0x2bc09c0/d; +L_0x2bc0ad0/d .functor OR 1, L_0x2bc04d0, L_0x2bc09c0, C4<0>, C4<0>; +L_0x2bc0ad0 .delay (20000,20000,20000) L_0x2bc0ad0/d; +v0x26ab010_0 .net "S", 0 0, L_0x2bc0ca0; 1 drivers +v0x26b0110_0 .alias "in0", 0 0, v0x26b6a10_0; +v0x26b01b0_0 .alias "in1", 0 0, v0x26bb970_0; +v0x26afeb0_0 .net "nS", 0 0, L_0x2bc0450; 1 drivers +v0x26aff30_0 .net "out0", 0 0, L_0x2bc04d0; 1 drivers +v0x26afc00_0 .net "out1", 0 0, L_0x2bc09c0; 1 drivers +v0x26afca0_0 .alias "outfinal", 0 0, v0x26b4b70_0; +S_0x26a3790 .scope generate, "addbits[16]" "addbits[16]" 3 283, 3 283, S_0x23ec510; + .timescale -9 -12; +P_0x221c538 .param/l "i" 3 283, +C4<010000>; +S_0x26a1a80 .scope module, "attempt" "MiddleAddSubSLT" 3 285, 3 189, S_0x26a3790; + .timescale -9 -12; +L_0x2bc0940/d .functor NOT 1, L_0x2bc1d90, C4<0>, C4<0>, C4<0>; +L_0x2bc0940 .delay (10000,10000,10000) L_0x2bc0940/d; +L_0x2bc2200/d .functor NOT 1, L_0x2bc22c0, C4<0>, C4<0>, C4<0>; +L_0x2bc2200 .delay (10000,10000,10000) L_0x2bc2200/d; +L_0x2bc2360/d .functor AND 1, L_0x2bc24a0, L_0x2bc2200, C4<1>, C4<1>; +L_0x2bc2360 .delay (20000,20000,20000) L_0x2bc2360/d; +L_0x2bc2540/d .functor XOR 1, L_0x2bc1cf0, L_0x2bc1f90, C4<0>, C4<0>; +L_0x2bc2540 .delay (40000,40000,40000) L_0x2bc2540/d; +L_0x2bc2630/d .functor XOR 1, L_0x2bc2540, L_0x2bc2fc0, C4<0>, C4<0>; +L_0x2bc2630 .delay (40000,40000,40000) L_0x2bc2630/d; +L_0x2bc2720/d .functor AND 1, L_0x2bc1cf0, L_0x2bc1f90, C4<1>, C4<1>; +L_0x2bc2720 .delay (20000,20000,20000) L_0x2bc2720/d; +L_0x2bc2890/d .functor AND 1, L_0x2bc2540, L_0x2bc2fc0, C4<1>, C4<1>; +L_0x2bc2890 .delay (20000,20000,20000) L_0x2bc2890/d; +L_0x2bc2980/d .functor OR 1, L_0x2bc2720, L_0x2bc2890, C4<0>, C4<0>; +L_0x2bc2980 .delay (20000,20000,20000) L_0x2bc2980/d; +v0x26a6830_0 .net "A", 0 0, L_0x2bc1cf0; 1 drivers +v0x26a65d0_0 .net "AandB", 0 0, L_0x2bc2720; 1 drivers +v0x26a6670_0 .net "AddSubSLTSum", 0 0, L_0x2bc2630; 1 drivers +v0x26a6320_0 .net "AxorB", 0 0, L_0x2bc2540; 1 drivers +v0x26a63a0_0 .net "B", 0 0, L_0x2bc1d90; 1 drivers +v0x26a46e0_0 .net "BornB", 0 0, L_0x2bc1f90; 1 drivers +v0x26a4760_0 .net "CINandAxorB", 0 0, L_0x2bc2890; 1 drivers +v0x26ad320_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x26ad3a0_0 .net *"_s3", 0 0, L_0x2bc22c0; 1 drivers +v0x26ad070_0 .net *"_s5", 0 0, L_0x2bc24a0; 1 drivers +v0x26ad0f0_0 .net "carryin", 0 0, L_0x2bc2fc0; 1 drivers +v0x26ab4a0_0 .net "carryout", 0 0, L_0x2bc2980; 1 drivers +v0x26ab520_0 .net "nB", 0 0, L_0x2bc0940; 1 drivers +v0x26ab240_0 .net "nCmd2", 0 0, L_0x2bc2200; 1 drivers +v0x26aaf90_0 .net "subtract", 0 0, L_0x2bc2360; 1 drivers +L_0x2bc2160 .part v0x2960210_0, 0, 1; +L_0x2bc22c0 .part v0x2960210_0, 2, 1; +L_0x2bc24a0 .part v0x2960210_0, 0, 1; +S_0x26a17d0 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x26a1a80; + .timescale -9 -12; +L_0x2bc18e0/d .functor NOT 1, L_0x2bc2160, C4<0>, C4<0>, C4<0>; +L_0x2bc18e0 .delay (10000,10000,10000) L_0x2bc18e0/d; +L_0x2bc1960/d .functor AND 1, L_0x2bc1d90, L_0x2bc18e0, C4<1>, C4<1>; +L_0x2bc1960 .delay (20000,20000,20000) L_0x2bc1960/d; +L_0x2bc1a70/d .functor AND 1, L_0x2bc0940, L_0x2bc2160, C4<1>, C4<1>; +L_0x2bc1a70 .delay (20000,20000,20000) L_0x2bc1a70/d; +L_0x2bc1f90/d .functor OR 1, L_0x2bc1960, L_0x2bc1a70, C4<0>, C4<0>; +L_0x2bc1f90 .delay (20000,20000,20000) L_0x2bc1f90/d; +v0x26a3ac0_0 .net "S", 0 0, L_0x2bc2160; 1 drivers +v0x269fb40_0 .alias "in0", 0 0, v0x26a63a0_0; +v0x269fbe0_0 .alias "in1", 0 0, v0x26ab520_0; +v0x26a86b0_0 .net "nS", 0 0, L_0x2bc18e0; 1 drivers +v0x26a8730_0 .net "out0", 0 0, L_0x2bc1960; 1 drivers +v0x26a8400_0 .net "out1", 0 0, L_0x2bc1a70; 1 drivers +v0x26a84a0_0 .alias "outfinal", 0 0, v0x26a46e0_0; +S_0x2695290 .scope generate, "addbits[17]" "addbits[17]" 3 283, 3 283, S_0x23ec510; + .timescale -9 -12; +P_0x2224c98 .param/l "i" 3 283, +C4<010001>; +S_0x2693470 .scope module, "attempt" "MiddleAddSubSLT" 3 285, 3 189, S_0x2695290; + .timescale -9 -12; +L_0x2bb0960/d .functor NOT 1, L_0x2bc3600, C4<0>, C4<0>, C4<0>; +L_0x2bb0960 .delay (10000,10000,10000) L_0x2bb0960/d; +L_0x2bc3820/d .functor NOT 1, L_0x2bc38c0, C4<0>, C4<0>, C4<0>; +L_0x2bc3820 .delay (10000,10000,10000) L_0x2bc3820/d; +L_0x2bc3960/d .functor AND 1, L_0x2bc3aa0, L_0x2bc3820, C4<1>, C4<1>; +L_0x2bc3960 .delay (20000,20000,20000) L_0x2bc3960/d; +L_0x2bc3b40/d .functor XOR 1, L_0x2bc3560, L_0x2bc2de0, C4<0>, C4<0>; +L_0x2bc3b40 .delay (40000,40000,40000) L_0x2bc3b40/d; +L_0x2bc3c30/d .functor XOR 1, L_0x2bc3b40, L_0x2bc45d0, C4<0>, C4<0>; +L_0x2bc3c30 .delay (40000,40000,40000) L_0x2bc3c30/d; +L_0x2bc3d20/d .functor AND 1, L_0x2bc3560, L_0x2bc2de0, C4<1>, C4<1>; +L_0x2bc3d20 .delay (20000,20000,20000) L_0x2bc3d20/d; +L_0x2bc3e90/d .functor AND 1, L_0x2bc3b40, L_0x2bc45d0, C4<1>, C4<1>; +L_0x2bc3e90 .delay (20000,20000,20000) L_0x2bc3e90/d; +L_0x2bc3f80/d .functor OR 1, L_0x2bc3d20, L_0x2bc3e90, C4<0>, C4<0>; +L_0x2bc3f80 .delay (20000,20000,20000) L_0x2bc3f80/d; +v0x2698120_0 .net "A", 0 0, L_0x2bc3560; 1 drivers +v0x2697e70_0 .net "AandB", 0 0, L_0x2bc3d20; 1 drivers +v0x2697f10_0 .net "AddSubSLTSum", 0 0, L_0x2bc3c30; 1 drivers +v0x26961e0_0 .net "AxorB", 0 0, L_0x2bc3b40; 1 drivers +v0x2696260_0 .net "B", 0 0, L_0x2bc3600; 1 drivers +v0x269eea0_0 .net "BornB", 0 0, L_0x2bc2de0; 1 drivers +v0x269ef20_0 .net "CINandAxorB", 0 0, L_0x2bc3e90; 1 drivers +v0x269ebf0_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x269ec70_0 .net *"_s3", 0 0, L_0x2bc38c0; 1 drivers +v0x269cdd0_0 .net *"_s5", 0 0, L_0x2bc3aa0; 1 drivers +v0x269ce50_0 .net "carryin", 0 0, L_0x2bc45d0; 1 drivers +v0x269cb20_0 .net "carryout", 0 0, L_0x2bc3f80; 1 drivers +v0x269cba0_0 .net "nB", 0 0, L_0x2bb0960; 1 drivers +v0x269ae90_0 .net "nCmd2", 0 0, L_0x2bc3820; 1 drivers +v0x26a3a40_0 .net "subtract", 0 0, L_0x2bc3960; 1 drivers +L_0x2bc3780 .part v0x2960210_0, 0, 1; +L_0x2bc38c0 .part v0x2960210_0, 2, 1; +L_0x2bc3aa0 .part v0x2960210_0, 0, 1; +S_0x26931c0 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x2693470; + .timescale -9 -12; +L_0x2bb88f0/d .functor NOT 1, L_0x2bc3780, C4<0>, C4<0>, C4<0>; +L_0x2bb88f0 .delay (10000,10000,10000) L_0x2bb88f0/d; +L_0x2bb8970/d .functor AND 1, L_0x2bc3600, L_0x2bb88f0, C4<1>, C4<1>; +L_0x2bb8970 .delay (20000,20000,20000) L_0x2bb8970/d; +L_0x2bc2d10/d .functor AND 1, L_0x2bb0960, L_0x2bc3780, C4<1>, C4<1>; +L_0x2bc2d10 .delay (20000,20000,20000) L_0x2bc2d10/d; +L_0x2bc2de0/d .functor OR 1, L_0x2bb8970, L_0x2bc2d10, C4<0>, C4<0>; +L_0x2bc2de0 .delay (20000,20000,20000) L_0x2bc2de0/d; +v0x26955c0_0 .net "S", 0 0, L_0x2bc3780; 1 drivers +v0x2691580_0 .alias "in0", 0 0, v0x2696260_0; +v0x2691620_0 .alias "in1", 0 0, v0x269cba0_0; +v0x269a1f0_0 .net "nS", 0 0, L_0x2bb88f0; 1 drivers +v0x269a270_0 .net "out0", 0 0, L_0x2bb8970; 1 drivers +v0x2699f40_0 .net "out1", 0 0, L_0x2bc2d10; 1 drivers +v0x2699fe0_0 .alias "outfinal", 0 0, v0x269eea0_0; +S_0x2684c70 .scope generate, "addbits[18]" "addbits[18]" 3 283, 3 283, S_0x23ec510; + .timescale -9 -12; +P_0x2230468 .param/l "i" 3 283, +C4<010010>; +S_0x2683030 .scope module, "attempt" "MiddleAddSubSLT" 3 285, 3 189, S_0x2684c70; + .timescale -9 -12; +L_0x2bc42a0/d .functor NOT 1, L_0x2bc4800, C4<0>, C4<0>, C4<0>; +L_0x2bc42a0 .delay (10000,10000,10000) L_0x2bc42a0/d; +L_0x2bc4c70/d .functor NOT 1, L_0x2bc4d10, C4<0>, C4<0>, C4<0>; +L_0x2bc4c70 .delay (10000,10000,10000) L_0x2bc4c70/d; +L_0x2bc4db0/d .functor AND 1, L_0x2bc4ef0, L_0x2bc4c70, C4<1>, C4<1>; +L_0x2bc4db0 .delay (20000,20000,20000) L_0x2bc4db0/d; +L_0x2bc4f90/d .functor XOR 1, L_0x2bc4760, L_0x2bc4a40, C4<0>, C4<0>; +L_0x2bc4f90 .delay (40000,40000,40000) L_0x2bc4f90/d; +L_0x2bc5040/d .functor XOR 1, L_0x2bc4f90, L_0x2bc5a10, C4<0>, C4<0>; +L_0x2bc5040 .delay (40000,40000,40000) L_0x2bc5040/d; +L_0x2bc5130/d .functor AND 1, L_0x2bc4760, L_0x2bc4a40, C4<1>, C4<1>; +L_0x2bc5130 .delay (20000,20000,20000) L_0x2bc5130/d; +L_0x2bc52a0/d .functor AND 1, L_0x2bc4f90, L_0x2bc5a10, C4<1>, C4<1>; +L_0x2bc52a0 .delay (20000,20000,20000) L_0x2bc52a0/d; +L_0x2bc5390/d .functor OR 1, L_0x2bc5130, L_0x2bc52a0, C4<0>, C4<0>; +L_0x2bc5390 .delay (20000,20000,20000) L_0x2bc5390/d; +v0x26898e0_0 .net "A", 0 0, L_0x2bc4760; 1 drivers +v0x2687ca0_0 .net "AandB", 0 0, L_0x2bc5130; 1 drivers +v0x2687d40_0 .net "AddSubSLTSum", 0 0, L_0x2bc5040; 1 drivers +v0x26908e0_0 .net "AxorB", 0 0, L_0x2bc4f90; 1 drivers +v0x2690960_0 .net "B", 0 0, L_0x2bc4800; 1 drivers +v0x2690630_0 .net "BornB", 0 0, L_0x2bc4a40; 1 drivers +v0x26906b0_0 .net "CINandAxorB", 0 0, L_0x2bc52a0; 1 drivers +v0x268ea60_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x268eae0_0 .net *"_s3", 0 0, L_0x2bc4d10; 1 drivers +v0x268e800_0 .net *"_s5", 0 0, L_0x2bc4ef0; 1 drivers +v0x268e880_0 .net "carryin", 0 0, L_0x2bc5a10; 1 drivers +v0x268e550_0 .net "carryout", 0 0, L_0x2bc5390; 1 drivers +v0x268e5d0_0 .net "nB", 0 0, L_0x2bc42a0; 1 drivers +v0x268c910_0 .net "nCmd2", 0 0, L_0x2bc4c70; 1 drivers +v0x2695540_0 .net "subtract", 0 0, L_0x2bc4db0; 1 drivers +L_0x2bc4bd0 .part v0x2960210_0, 0, 1; +L_0x2bc4d10 .part v0x2960210_0, 2, 1; +L_0x2bc4ef0 .part v0x2960210_0, 0, 1; +S_0x268bc70 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x2683030; + .timescale -9 -12; +L_0x2bc43b0/d .functor NOT 1, L_0x2bc4bd0, C4<0>, C4<0>, C4<0>; +L_0x2bc43b0 .delay (10000,10000,10000) L_0x2bc43b0/d; +L_0x2bc4430/d .functor AND 1, L_0x2bc4800, L_0x2bc43b0, C4<1>, C4<1>; +L_0x2bc4430 .delay (20000,20000,20000) L_0x2bc4430/d; +L_0x2bc4540/d .functor AND 1, L_0x2bc42a0, L_0x2bc4bd0, C4<1>, C4<1>; +L_0x2bc4540 .delay (20000,20000,20000) L_0x2bc4540/d; +L_0x2bc4a40/d .functor OR 1, L_0x2bc4430, L_0x2bc4540, C4<0>, C4<0>; +L_0x2bc4a40 .delay (20000,20000,20000) L_0x2bc4a40/d; +v0x2684fa0_0 .net "S", 0 0, L_0x2bc4bd0; 1 drivers +v0x268b9c0_0 .alias "in0", 0 0, v0x2690960_0; +v0x268ba60_0 .alias "in1", 0 0, v0x268e5d0_0; +v0x2689df0_0 .net "nS", 0 0, L_0x2bc43b0; 1 drivers +v0x2689e70_0 .net "out0", 0 0, L_0x2bc4430; 1 drivers +v0x2689b90_0 .net "out1", 0 0, L_0x2bc4540; 1 drivers +v0x2689c30_0 .alias "outfinal", 0 0, v0x2690630_0; +S_0x26767d0 .scope generate, "addbits[19]" "addbits[19]" 3 283, 3 283, S_0x23ec510; + .timescale -9 -12; +P_0x223b158 .param/l "i" 3 283, +C4<010011>; +S_0x2674b40 .scope module, "attempt" "MiddleAddSubSLT" 3 285, 3 189, S_0x26767d0; + .timescale -9 -12; +L_0x2bc4930/d .functor NOT 1, L_0x2bc5c40, C4<0>, C4<0>, C4<0>; +L_0x2bc4930 .delay (10000,10000,10000) L_0x2bc4930/d; +L_0x2bc60a0/d .functor NOT 1, L_0x2bc6140, C4<0>, C4<0>, C4<0>; +L_0x2bc60a0 .delay (10000,10000,10000) L_0x2bc60a0/d; +L_0x2bc61e0/d .functor AND 1, L_0x2bc6320, L_0x2bc60a0, C4<1>, C4<1>; +L_0x2bc61e0 .delay (20000,20000,20000) L_0x2bc61e0/d; +L_0x2bc63c0/d .functor XOR 1, L_0x2bc5ba0, L_0x2bc5e70, C4<0>, C4<0>; +L_0x2bc63c0 .delay (40000,40000,40000) L_0x2bc63c0/d; +L_0x2bc64b0/d .functor XOR 1, L_0x2bc63c0, L_0x2bc5d70, C4<0>, C4<0>; +L_0x2bc64b0 .delay (40000,40000,40000) L_0x2bc64b0/d; +L_0x2bc65a0/d .functor AND 1, L_0x2bc5ba0, L_0x2bc5e70, C4<1>, C4<1>; +L_0x2bc65a0 .delay (20000,20000,20000) L_0x2bc65a0/d; +L_0x2bc6710/d .functor AND 1, L_0x2bc63c0, L_0x2bc5d70, C4<1>, C4<1>; +L_0x2bc6710 .delay (20000,20000,20000) L_0x2bc6710/d; +L_0x2bc6800/d .functor OR 1, L_0x2bc65a0, L_0x2bc6710, C4<0>, C4<0>; +L_0x2bc6800 .delay (20000,20000,20000) L_0x2bc6800/d; +v0x26797f0_0 .net "A", 0 0, L_0x2bc5ba0; 1 drivers +v0x2682390_0 .net "AandB", 0 0, L_0x2bc65a0; 1 drivers +v0x2682430_0 .net "AddSubSLTSum", 0 0, L_0x2bc64b0; 1 drivers +v0x26803e0_0 .net "AxorB", 0 0, L_0x2bc63c0; 1 drivers +v0x2680460_0 .net "B", 0 0, L_0x2bc5c40; 1 drivers +v0x2680130_0 .net "BornB", 0 0, L_0x2bc5e70; 1 drivers +v0x26801b0_0 .net "CINandAxorB", 0 0, L_0x2bc6710; 1 drivers +v0x267e4a0_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x267e520_0 .net *"_s3", 0 0, L_0x2bc6140; 1 drivers +v0x2687000_0 .net *"_s5", 0 0, L_0x2bc6320; 1 drivers +v0x2687080_0 .net "carryin", 0 0, L_0x2bc5d70; 1 drivers +v0x2686d50_0 .net "carryout", 0 0, L_0x2bc6800; 1 drivers +v0x2686dd0_0 .net "nB", 0 0, L_0x2bc4930; 1 drivers +v0x2685180_0 .net "nCmd2", 0 0, L_0x2bc60a0; 1 drivers +v0x2684f20_0 .net "subtract", 0 0, L_0x2bc61e0; 1 drivers +L_0x2bc6000 .part v0x2960210_0, 0, 1; +L_0x2bc6140 .part v0x2960210_0, 2, 1; +L_0x2bc6320 .part v0x2960210_0, 0, 1; +S_0x267d800 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x2674b40; + .timescale -9 -12; +L_0x2bc5790/d .functor NOT 1, L_0x2bc6000, C4<0>, C4<0>, C4<0>; +L_0x2bc5790 .delay (10000,10000,10000) L_0x2bc5790/d; +L_0x2bc5810/d .functor AND 1, L_0x2bc5c40, L_0x2bc5790, C4<1>, C4<1>; +L_0x2bc5810 .delay (20000,20000,20000) L_0x2bc5810/d; +L_0x2bc5920/d .functor AND 1, L_0x2bc4930, L_0x2bc6000, C4<1>, C4<1>; +L_0x2bc5920 .delay (20000,20000,20000) L_0x2bc5920/d; +L_0x2bc5e70/d .functor OR 1, L_0x2bc5810, L_0x2bc5920, C4<0>, C4<0>; +L_0x2bc5e70 .delay (20000,20000,20000) L_0x2bc5e70/d; +v0x2676b00_0 .net "S", 0 0, L_0x2bc6000; 1 drivers +v0x267d550_0 .alias "in0", 0 0, v0x2680460_0; +v0x267d5f0_0 .alias "in1", 0 0, v0x2686dd0_0; +v0x267b730_0 .net "nS", 0 0, L_0x2bc5790; 1 drivers +v0x267b7b0_0 .net "out0", 0 0, L_0x2bc5810; 1 drivers +v0x267b480_0 .net "out1", 0 0, L_0x2bc5920; 1 drivers +v0x267b520_0 .alias "outfinal", 0 0, v0x2680130_0; +S_0x2666600 .scope generate, "addbits[20]" "addbits[20]" 3 283, 3 283, S_0x23ec510; + .timescale -9 -12; +P_0x22438b8 .param/l "i" 3 283, +C4<010100>; +S_0x266f240 .scope module, "attempt" "MiddleAddSubSLT" 3 285, 3 189, S_0x2666600; + .timescale -9 -12; +L_0x2bc6ec0/d .functor NOT 1, L_0x2bc6cb0, C4<0>, C4<0>, C4<0>; +L_0x2bc6ec0 .delay (10000,10000,10000) L_0x2bc6ec0/d; +L_0x2bc7430/d .functor NOT 1, L_0x2bc74d0, C4<0>, C4<0>, C4<0>; +L_0x2bc7430 .delay (10000,10000,10000) L_0x2bc7430/d; +L_0x2bc7570/d .functor AND 1, L_0x2bc76b0, L_0x2bc7430, C4<1>, C4<1>; +L_0x2bc7570 .delay (20000,20000,20000) L_0x2bc7570/d; +L_0x2bc7750/d .functor XOR 1, L_0x2bc6c10, L_0x2bc7200, C4<0>, C4<0>; +L_0x2bc7750 .delay (40000,40000,40000) L_0x2bc7750/d; +L_0x2bc7840/d .functor XOR 1, L_0x2bc7750, L_0x2bc6de0, C4<0>, C4<0>; +L_0x2bc7840 .delay (40000,40000,40000) L_0x2bc7840/d; +L_0x2bc7930/d .functor AND 1, L_0x2bc6c10, L_0x2bc7200, C4<1>, C4<1>; +L_0x2bc7930 .delay (20000,20000,20000) L_0x2bc7930/d; +L_0x2bc7aa0/d .functor AND 1, L_0x2bc7750, L_0x2bc6de0, C4<1>, C4<1>; +L_0x2bc7aa0 .delay (20000,20000,20000) L_0x2bc7aa0/d; +L_0x2bc7b90/d .functor OR 1, L_0x2bc7930, L_0x2bc7aa0, C4<0>, C4<0>; +L_0x2bc7b90 .delay (20000,20000,20000) L_0x2bc7b90/d; +v0x266b270_0 .net "A", 0 0, L_0x2bc6c10; 1 drivers +v0x2673ea0_0 .net "AandB", 0 0, L_0x2bc7930; 1 drivers +v0x2673f40_0 .net "AddSubSLTSum", 0 0, L_0x2bc7840; 1 drivers +v0x2673bf0_0 .net "AxorB", 0 0, L_0x2bc7750; 1 drivers +v0x2673c70_0 .net "B", 0 0, L_0x2bc6cb0; 1 drivers +v0x2671dd0_0 .net "BornB", 0 0, L_0x2bc7200; 1 drivers +v0x2671e50_0 .net "CINandAxorB", 0 0, L_0x2bc7aa0; 1 drivers +v0x2671b20_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x2671ba0_0 .net *"_s3", 0 0, L_0x2bc74d0; 1 drivers +v0x266fee0_0 .net *"_s5", 0 0, L_0x2bc76b0; 1 drivers +v0x266ff60_0 .net "carryin", 0 0, L_0x2bc6de0; 1 drivers +v0x2678b50_0 .net "carryout", 0 0, L_0x2bc7b90; 1 drivers +v0x2678bd0_0 .net "nB", 0 0, L_0x2bc6ec0; 1 drivers +v0x26788a0_0 .net "nCmd2", 0 0, L_0x2bc7430; 1 drivers +v0x2676a80_0 .net "subtract", 0 0, L_0x2bc7570; 1 drivers +L_0x2bc7390 .part v0x2960210_0, 0, 1; +L_0x2bc74d0 .part v0x2960210_0, 2, 1; +L_0x2bc76b0 .part v0x2960210_0, 0, 1; +S_0x266ef90 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x266f240; + .timescale -9 -12; +L_0x2bc6fc0/d .functor NOT 1, L_0x2bc7390, C4<0>, C4<0>, C4<0>; +L_0x2bc6fc0 .delay (10000,10000,10000) L_0x2bc6fc0/d; +L_0x2bc7020/d .functor AND 1, L_0x2bc6cb0, L_0x2bc6fc0, C4<1>, C4<1>; +L_0x2bc7020 .delay (20000,20000,20000) L_0x2bc7020/d; +L_0x2bc7110/d .functor AND 1, L_0x2bc6ec0, L_0x2bc7390, C4<1>, C4<1>; +L_0x2bc7110 .delay (20000,20000,20000) L_0x2bc7110/d; +L_0x2bc7200/d .functor OR 1, L_0x2bc7020, L_0x2bc7110, C4<0>, C4<0>; +L_0x2bc7200 .delay (20000,20000,20000) L_0x2bc7200/d; +v0x26682c0_0 .net "S", 0 0, L_0x2bc7390; 1 drivers +v0x266d3c0_0 .alias "in0", 0 0, v0x2673c70_0; +v0x266d460_0 .alias "in1", 0 0, v0x2678bd0_0; +v0x266d160_0 .net "nS", 0 0, L_0x2bc6fc0; 1 drivers +v0x266d1e0_0 .net "out0", 0 0, L_0x2bc7020; 1 drivers +v0x266ceb0_0 .net "out1", 0 0, L_0x2bc7110; 1 drivers +v0x266cf50_0 .alias "outfinal", 0 0, v0x2671dd0_0; +S_0x2660db0 .scope generate, "addbits[21]" "addbits[21]" 3 283, 3 283, S_0x23ec510; + .timescale -9 -12; +P_0x224c4e8 .param/l "i" 3 283, +C4<010101>; +S_0x2660b00 .scope module, "attempt" "MiddleAddSubSLT" 3 285, 3 189, S_0x2660db0; + .timescale -9 -12; +L_0x2bc8280/d .functor NOT 1, L_0x2bc8040, C4<0>, C4<0>, C4<0>; +L_0x2bc8280 .delay (10000,10000,10000) L_0x2bc8280/d; +L_0x2bc87b0/d .functor NOT 1, L_0x2bc8850, C4<0>, C4<0>, C4<0>; +L_0x2bc87b0 .delay (10000,10000,10000) L_0x2bc87b0/d; +L_0x2bc88f0/d .functor AND 1, L_0x2bc8a30, L_0x2bc87b0, C4<1>, C4<1>; +L_0x2bc88f0 .delay (20000,20000,20000) L_0x2bc88f0/d; +L_0x2bc8ad0/d .functor XOR 1, L_0x2bc7fa0, L_0x2bc8580, C4<0>, C4<0>; +L_0x2bc8ad0 .delay (40000,40000,40000) L_0x2bc8ad0/d; +L_0x2bc8bc0/d .functor XOR 1, L_0x2bc8ad0, L_0x2bc8170, C4<0>, C4<0>; +L_0x2bc8bc0 .delay (40000,40000,40000) L_0x2bc8bc0/d; +L_0x2bc8cb0/d .functor AND 1, L_0x2bc7fa0, L_0x2bc8580, C4<1>, C4<1>; +L_0x2bc8cb0 .delay (20000,20000,20000) L_0x2bc8cb0/d; +L_0x2bc8e20/d .functor AND 1, L_0x2bc8ad0, L_0x2bc8170, C4<1>, C4<1>; +L_0x2bc8e20 .delay (20000,20000,20000) L_0x2bc8e20/d; +L_0x2bc8f10/d .functor OR 1, L_0x2bc8cb0, L_0x2bc8e20, C4<0>, C4<0>; +L_0x2bc8f10 .delay (20000,20000,20000) L_0x2bc8f10/d; +v0x26656b0_0 .net "A", 0 0, L_0x2bc7fa0; 1 drivers +v0x2663ad0_0 .net "AandB", 0 0, L_0x2bc8cb0; 1 drivers +v0x2663b70_0 .net "AddSubSLTSum", 0 0, L_0x2bc8bc0; 1 drivers +v0x2663870_0 .net "AxorB", 0 0, L_0x2bc8ad0; 1 drivers +v0x26638f0_0 .net "B", 0 0, L_0x2bc8040; 1 drivers +v0x2661a50_0 .net "BornB", 0 0, L_0x2bc8580; 1 drivers +v0x2661ad0_0 .net "CINandAxorB", 0 0, L_0x2bc8e20; 1 drivers +v0x266a5d0_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x266a650_0 .net *"_s3", 0 0, L_0x2bc8850; 1 drivers +v0x266a320_0 .net *"_s5", 0 0, L_0x2bc8a30; 1 drivers +v0x266a3a0_0 .net "carryin", 0 0, L_0x2bc8170; 1 drivers +v0x2668750_0 .net "carryout", 0 0, L_0x2bc8f10; 1 drivers +v0x26687d0_0 .net "nB", 0 0, L_0x2bc8280; 1 drivers +v0x26684f0_0 .net "nCmd2", 0 0, L_0x2bc87b0; 1 drivers +v0x2668240_0 .net "subtract", 0 0, L_0x2bc88f0; 1 drivers +L_0x2bc8710 .part v0x2960210_0, 0, 1; +L_0x2bc8850 .part v0x2960210_0, 2, 1; +L_0x2bc8a30 .part v0x2960210_0, 0, 1; +S_0x265ece0 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x2660b00; + .timescale -9 -12; +L_0x2bc8380/d .functor NOT 1, L_0x2bc8710, C4<0>, C4<0>, C4<0>; +L_0x2bc8380 .delay (10000,10000,10000) L_0x2bc8380/d; +L_0x2bc83e0/d .functor AND 1, L_0x2bc8040, L_0x2bc8380, C4<1>, C4<1>; +L_0x2bc83e0 .delay (20000,20000,20000) L_0x2bc83e0/d; +L_0x2bc8490/d .functor AND 1, L_0x2bc8280, L_0x2bc8710, C4<1>, C4<1>; +L_0x2bc8490 .delay (20000,20000,20000) L_0x2bc8490/d; +L_0x2bc8580/d .functor OR 1, L_0x2bc83e0, L_0x2bc8490, C4<0>, C4<0>; +L_0x2bc8580 .delay (20000,20000,20000) L_0x2bc8580/d; +v0x2658170_0 .net "S", 0 0, L_0x2bc8710; 1 drivers +v0x265ea30_0 .alias "in0", 0 0, v0x26638f0_0; +v0x265ead0_0 .alias "in1", 0 0, v0x26687d0_0; +v0x265cda0_0 .net "nS", 0 0, L_0x2bc8380; 1 drivers +v0x265ce20_0 .net "out0", 0 0, L_0x2bc83e0; 1 drivers +v0x2665960_0 .net "out1", 0 0, L_0x2bc8490; 1 drivers +v0x2665a00_0 .alias "outfinal", 0 0, v0x2661a50_0; +S_0x26524f0 .scope generate, "addbits[22]" "addbits[22]" 3 283, 3 283, S_0x23ec510; + .timescale -9 -12; +P_0x2279168 .param/l "i" 3 283, +C4<010110>; +S_0x2650910 .scope module, "attempt" "MiddleAddSubSLT" 3 285, 3 189, S_0x26524f0; + .timescale -9 -12; +L_0x2bc8210/d .functor NOT 1, L_0x2bc93c0, C4<0>, C4<0>, C4<0>; +L_0x2bc8210 .delay (10000,10000,10000) L_0x2bc8210/d; +L_0x2bc9ba0/d .functor NOT 1, L_0x2bc9c60, C4<0>, C4<0>, C4<0>; +L_0x2bc9ba0 .delay (10000,10000,10000) L_0x2bc9ba0/d; +L_0x2bc9d00/d .functor AND 1, L_0x2bc9e40, L_0x2bc9ba0, C4<1>, C4<1>; +L_0x2bc9d00 .delay (20000,20000,20000) L_0x2bc9d00/d; +L_0x2bc9ee0/d .functor XOR 1, L_0x2bc9320, L_0x2bc9930, C4<0>, C4<0>; +L_0x2bc9ee0 .delay (40000,40000,40000) L_0x2bc9ee0/d; +L_0x2bc9fd0/d .functor XOR 1, L_0x2bc9ee0, L_0x2bc94f0, C4<0>, C4<0>; +L_0x2bc9fd0 .delay (40000,40000,40000) L_0x2bc9fd0/d; +L_0x2bca0c0/d .functor AND 1, L_0x2bc9320, L_0x2bc9930, C4<1>, C4<1>; +L_0x2bca0c0 .delay (20000,20000,20000) L_0x2bca0c0/d; +L_0x2bca230/d .functor AND 1, L_0x2bc9ee0, L_0x2bc94f0, C4<1>, C4<1>; +L_0x2bca230 .delay (20000,20000,20000) L_0x2bca230/d; +L_0x2bca340/d .functor OR 1, L_0x2bca0c0, L_0x2bca230, C4<0>, C4<0>; +L_0x2bca340 .delay (20000,20000,20000) L_0x2bca340/d; +v0x26571a0_0 .net "A", 0 0, L_0x2bc9320; 1 drivers +v0x2655380_0 .net "AandB", 0 0, L_0x2bca0c0; 1 drivers +v0x2655420_0 .net "AddSubSLTSum", 0 0, L_0x2bc9fd0; 1 drivers +v0x26550d0_0 .net "AxorB", 0 0, L_0x2bc9ee0; 1 drivers +v0x2655150_0 .net "B", 0 0, L_0x2bc93c0; 1 drivers +v0x2653440_0 .net "BornB", 0 0, L_0x2bc9930; 1 drivers +v0x26534c0_0 .net "CINandAxorB", 0 0, L_0x2bca230; 1 drivers +v0x265c100_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x265c180_0 .net *"_s3", 0 0, L_0x2bc9c60; 1 drivers +v0x265be50_0 .net *"_s5", 0 0, L_0x2bc9e40; 1 drivers +v0x265bed0_0 .net "carryin", 0 0, L_0x2bc94f0; 1 drivers +v0x265a030_0 .net "carryout", 0 0, L_0x2bca340; 1 drivers +v0x265a0b0_0 .net "nB", 0 0, L_0x2bc8210; 1 drivers +v0x2659d80_0 .net "nCmd2", 0 0, L_0x2bc9ba0; 1 drivers +v0x26580f0_0 .net "subtract", 0 0, L_0x2bc9d00; 1 drivers +L_0x2bc9b00 .part v0x2960210_0, 0, 1; +L_0x2bc9c60 .part v0x2960210_0, 2, 1; +L_0x2bc9e40 .part v0x2960210_0, 0, 1; +S_0x26506b0 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x2650910; + .timescale -9 -12; +L_0x2bc96d0/d .functor NOT 1, L_0x2bc9b00, C4<0>, C4<0>, C4<0>; +L_0x2bc96d0 .delay (10000,10000,10000) L_0x2bc96d0/d; +L_0x2bc9730/d .functor AND 1, L_0x2bc93c0, L_0x2bc96d0, C4<1>, C4<1>; +L_0x2bc9730 .delay (20000,20000,20000) L_0x2bc9730/d; +L_0x2bc9820/d .functor AND 1, L_0x2bc8210, L_0x2bc9b00, C4<1>, C4<1>; +L_0x2bc9820 .delay (20000,20000,20000) L_0x2bc9820/d; +L_0x2bc9930/d .functor OR 1, L_0x2bc9730, L_0x2bc9820, C4<0>, C4<0>; +L_0x2bc9930 .delay (20000,20000,20000) L_0x2bc9930/d; +v0x2652820_0 .net "S", 0 0, L_0x2bc9b00; 1 drivers +v0x2650400_0 .alias "in0", 0 0, v0x2655150_0; +v0x26504a0_0 .alias "in1", 0 0, v0x265a0b0_0; +v0x264e7c0_0 .net "nS", 0 0, L_0x2bc96d0; 1 drivers +v0x264e840_0 .net "out0", 0 0, L_0x2bc9730; 1 drivers +v0x2657450_0 .net "out1", 0 0, L_0x2bc9820; 1 drivers +v0x26574f0_0 .alias "outfinal", 0 0, v0x2653440_0; +S_0x26630f0 .scope generate, "addbits[23]" "addbits[23]" 3 283, 3 283, S_0x23ec510; + .timescale -9 -12; +P_0x22f2948 .param/l "i" 3 283, +C4<010111>; +S_0x2645f50 .scope module, "attempt" "MiddleAddSubSLT" 3 285, 3 189, S_0x26630f0; + .timescale -9 -12; +L_0x2bc9590/d .functor NOT 1, L_0x2bca810, C4<0>, C4<0>, C4<0>; +L_0x2bc9590 .delay (10000,10000,10000) L_0x2bc9590/d; +L_0x2bcaf80/d .functor NOT 1, L_0x2bcb020, C4<0>, C4<0>, C4<0>; +L_0x2bcaf80 .delay (10000,10000,10000) L_0x2bcaf80/d; +L_0x2bcb0c0/d .functor AND 1, L_0x2bcb200, L_0x2bcaf80, C4<1>, C4<1>; +L_0x2bcb0c0 .delay (20000,20000,20000) L_0x2bcb0c0/d; +L_0x2bcb2a0/d .functor XOR 1, L_0x2bca770, L_0x2bcad50, C4<0>, C4<0>; +L_0x2bcb2a0 .delay (40000,40000,40000) L_0x2bcb2a0/d; +L_0x2bcb390/d .functor XOR 1, L_0x2bcb2a0, L_0x2bca940, C4<0>, C4<0>; +L_0x2bcb390 .delay (40000,40000,40000) L_0x2bcb390/d; +L_0x2bcb480/d .functor AND 1, L_0x2bca770, L_0x2bcad50, C4<1>, C4<1>; +L_0x2bcb480 .delay (20000,20000,20000) L_0x2bcb480/d; +L_0x2bcb5f0/d .functor AND 1, L_0x2bcb2a0, L_0x2bca940, C4<1>, C4<1>; +L_0x2bcb5f0 .delay (20000,20000,20000) L_0x2bcb5f0/d; +L_0x2bcb700/d .functor OR 1, L_0x2bcb480, L_0x2bcb5f0, C4<0>, C4<0>; +L_0x2bcb700 .delay (20000,20000,20000) L_0x2bcb700/d; +v0x2646a00_0 .net "A", 0 0, L_0x2bca770; 1 drivers +v0x2644d00_0 .net "AandB", 0 0, L_0x2bcb480; 1 drivers +v0x2644da0_0 .net "AddSubSLTSum", 0 0, L_0x2bcb390; 1 drivers +v0x264db20_0 .net "AxorB", 0 0, L_0x2bcb2a0; 1 drivers +v0x264dba0_0 .net "B", 0 0, L_0x2bca810; 1 drivers +v0x264d870_0 .net "BornB", 0 0, L_0x2bcad50; 1 drivers +v0x264d8f0_0 .net "CINandAxorB", 0 0, L_0x2bcb5f0; 1 drivers +v0x264bca0_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x264bd20_0 .net *"_s3", 0 0, L_0x2bcb020; 1 drivers +v0x264ba40_0 .net *"_s5", 0 0, L_0x2bcb200; 1 drivers +v0x264bac0_0 .net "carryin", 0 0, L_0x2bca940; 1 drivers +v0x264b790_0 .net "carryout", 0 0, L_0x2bcb700; 1 drivers +v0x264b810_0 .net "nB", 0 0, L_0x2bc9590; 1 drivers +v0x2649b50_0 .net "nCmd2", 0 0, L_0x2bcaf80; 1 drivers +v0x26527a0_0 .net "subtract", 0 0, L_0x2bcb0c0; 1 drivers +L_0x2bcaee0 .part v0x2960210_0, 0, 1; +L_0x2bcb020 .part v0x2960210_0, 2, 1; +L_0x2bcb200 .part v0x2960210_0, 0, 1; +S_0x26d9b90 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x2645f50; + .timescale -9 -12; +L_0x2bcab50/d .functor NOT 1, L_0x2bcaee0, C4<0>, C4<0>, C4<0>; +L_0x2bcab50 .delay (10000,10000,10000) L_0x2bcab50/d; +L_0x2bcabb0/d .functor AND 1, L_0x2bca810, L_0x2bcab50, C4<1>, C4<1>; +L_0x2bcabb0 .delay (20000,20000,20000) L_0x2bcabb0/d; +L_0x2bcac60/d .functor AND 1, L_0x2bc9590, L_0x2bcaee0, C4<1>, C4<1>; +L_0x2bcac60 .delay (20000,20000,20000) L_0x2bcac60/d; +L_0x2bcad50/d .functor OR 1, L_0x2bcabb0, L_0x2bcac60, C4<0>, C4<0>; +L_0x2bcad50 .delay (20000,20000,20000) L_0x2bcad50/d; +v0x26678a0_0 .net "S", 0 0, L_0x2bcaee0; 1 drivers +v0x2648eb0_0 .alias "in0", 0 0, v0x264dba0_0; +v0x2648f50_0 .alias "in1", 0 0, v0x264b810_0; +v0x2648c00_0 .net "nS", 0 0, L_0x2bcab50; 1 drivers +v0x2648c80_0 .net "out0", 0 0, L_0x2bcabb0; 1 drivers +v0x2646ce0_0 .net "out1", 0 0, L_0x2bcac60; 1 drivers +v0x2646d80_0 .alias "outfinal", 0 0, v0x264d870_0; +S_0x2688ec0 .scope generate, "addbits[24]" "addbits[24]" 3 283, 3 283, S_0x23ec510; + .timescale -9 -12; +P_0x22e6b48 .param/l "i" 3 283, +C4<011000>; +S_0x26847d0 .scope module, "attempt" "MiddleAddSubSLT" 3 285, 3 189, S_0x2688ec0; + .timescale -9 -12; +L_0x2bca9e0/d .functor NOT 1, L_0x2bcbbd0, C4<0>, C4<0>, C4<0>; +L_0x2bca9e0 .delay (10000,10000,10000) L_0x2bca9e0/d; +L_0x2bcc3c0/d .functor NOT 1, L_0x2bcc480, C4<0>, C4<0>, C4<0>; +L_0x2bcc3c0 .delay (10000,10000,10000) L_0x2bcc3c0/d; +L_0x2bcc520/d .functor AND 1, L_0x2bcc660, L_0x2bcc3c0, C4<1>, C4<1>; +L_0x2bcc520 .delay (20000,20000,20000) L_0x2bcc520/d; +L_0x2bcc700/d .functor XOR 1, L_0x2bcbb30, L_0x2bcc150, C4<0>, C4<0>; +L_0x2bcc700 .delay (40000,40000,40000) L_0x2bcc700/d; +L_0x2bcc7f0/d .functor XOR 1, L_0x2bcc700, L_0x2bcbd00, C4<0>, C4<0>; +L_0x2bcc7f0 .delay (40000,40000,40000) L_0x2bcc7f0/d; +L_0x2bcc910/d .functor AND 1, L_0x2bcbb30, L_0x2bcc150, C4<1>, C4<1>; +L_0x2bcc910 .delay (20000,20000,20000) L_0x2bcc910/d; +L_0x2bccab0/d .functor AND 1, L_0x2bcc700, L_0x2bcbd00, C4<1>, C4<1>; +L_0x2bccab0 .delay (20000,20000,20000) L_0x2bccab0/d; +L_0x2bccbc0/d .functor OR 1, L_0x2bcc910, L_0x2bccab0, C4<0>, C4<0>; +L_0x2bccbc0 .delay (20000,20000,20000) L_0x2bccbc0/d; +v0x267afb0_0 .net "A", 0 0, L_0x2bcbb30; 1 drivers +v0x2676300_0 .net "AandB", 0 0, L_0x2bcc910; 1 drivers +v0x26763a0_0 .net "AddSubSLTSum", 0 0, L_0x2bcc7f0; 1 drivers +v0x264ad70_0 .net "AxorB", 0 0, L_0x2bcc700; 1 drivers +v0x264adf0_0 .net "B", 0 0, L_0x2bcbbd0; 1 drivers +v0x2671680_0 .net "BornB", 0 0, L_0x2bcc150; 1 drivers +v0x2671700_0 .net "CINandAxorB", 0 0, L_0x2bccab0; 1 drivers +v0x2671100_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x2671180_0 .net *"_s3", 0 0, L_0x2bcc480; 1 drivers +v0x266ca10_0 .net *"_s5", 0 0, L_0x2bcc660; 1 drivers +v0x266ca90_0 .net "carryin", 0 0, L_0x2bcbd00; 1 drivers +v0x266c490_0 .net "carryout", 0 0, L_0x2bccbc0; 1 drivers +v0x266c510_0 .net "nB", 0 0, L_0x2bca9e0; 1 drivers +v0x2667da0_0 .net "nCmd2", 0 0, L_0x2bcc3c0; 1 drivers +v0x2667820_0 .net "subtract", 0 0, L_0x2bcc520; 1 drivers +L_0x2bcc320 .part v0x2960210_0, 0, 1; +L_0x2bcc480 .part v0x2960210_0, 2, 1; +L_0x2bcc660 .part v0x2960210_0, 0, 1; +S_0x2684250 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x26847d0; + .timescale -9 -12; +L_0x2bcbef0/d .functor NOT 1, L_0x2bcc320, C4<0>, C4<0>, C4<0>; +L_0x2bcbef0 .delay (10000,10000,10000) L_0x2bcbef0/d; +L_0x2bcbf50/d .functor AND 1, L_0x2bcbbd0, L_0x2bcbef0, C4<1>, C4<1>; +L_0x2bcbf50 .delay (20000,20000,20000) L_0x2bcbf50/d; +L_0x2bcc040/d .functor AND 1, L_0x2bca9e0, L_0x2bcc320, C4<1>, C4<1>; +L_0x2bcc040 .delay (20000,20000,20000) L_0x2bcc040/d; +L_0x2bcc150/d .functor OR 1, L_0x2bcbf50, L_0x2bcc040, C4<0>, C4<0>; +L_0x2bcc150 .delay (20000,20000,20000) L_0x2bcc150/d; +v0x26894c0_0 .net "S", 0 0, L_0x2bcc320; 1 drivers +v0x2681c60_0 .alias "in0", 0 0, v0x264adf0_0; +v0x2681d00_0 .alias "in1", 0 0, v0x266c510_0; +v0x264b2f0_0 .net "nS", 0 0, L_0x2bcbef0; 1 drivers +v0x264b370_0 .net "out0", 0 0, L_0x2bcbf50; 1 drivers +v0x267fc60_0 .net "out1", 0 0, L_0x2bcc040; 1 drivers +v0x267fd00_0 .alias "outfinal", 0 0, v0x2671680_0; +S_0x264ff60 .scope generate, "addbits[25]" "addbits[25]" 3 283, 3 283, S_0x23ec510; + .timescale -9 -12; +P_0x22dc5d8 .param/l "i" 3 283, +C4<011001>; +S_0x26af760 .scope module, "attempt" "MiddleAddSubSLT" 3 285, 3 189, S_0x264ff60; + .timescale -9 -12; +L_0x2bcbda0/d .functor NOT 1, L_0x2bcd090, C4<0>, C4<0>, C4<0>; +L_0x2bcbda0 .delay (10000,10000,10000) L_0x2bcbda0/d; +L_0x2bcd890/d .functor NOT 1, L_0x2bcd950, C4<0>, C4<0>, C4<0>; +L_0x2bcd890 .delay (10000,10000,10000) L_0x2bcd890/d; +L_0x2bcd9f0/d .functor AND 1, L_0x2bcdb30, L_0x2bcd890, C4<1>, C4<1>; +L_0x2bcd9f0 .delay (20000,20000,20000) L_0x2bcd9f0/d; +L_0x2bcdbd0/d .functor XOR 1, L_0x2bccff0, L_0x2bcd620, C4<0>, C4<0>; +L_0x2bcdbd0 .delay (40000,40000,40000) L_0x2bcdbd0/d; +L_0x2bcdcc0/d .functor XOR 1, L_0x2bcdbd0, L_0x2bcd1c0, C4<0>, C4<0>; +L_0x2bcdcc0 .delay (40000,40000,40000) L_0x2bcdcc0/d; +L_0x2bcdde0/d .functor AND 1, L_0x2bccff0, L_0x2bcd620, C4<1>, C4<1>; +L_0x2bcdde0 .delay (20000,20000,20000) L_0x2bcdde0/d; +L_0x2bcdf80/d .functor AND 1, L_0x2bcdbd0, L_0x2bcd1c0, C4<1>, C4<1>; +L_0x2bcdf80 .delay (20000,20000,20000) L_0x2bcdf80/d; +L_0x2bce090/d .functor OR 1, L_0x2bcdde0, L_0x2bcdf80, C4<0>, C4<0>; +L_0x2bce090 .delay (20000,20000,20000) L_0x2bce090/d; +v0x26a5900_0 .net "A", 0 0, L_0x2bccff0; 1 drivers +v0x264f9e0_0 .net "AandB", 0 0, L_0x2bcdde0; 1 drivers +v0x264fa80_0 .net "AddSubSLTSum", 0 0, L_0x2bcdcc0; 1 drivers +v0x26a1300_0 .net "AxorB", 0 0, L_0x2bcdbd0; 1 drivers +v0x26a1380_0 .net "B", 0 0, L_0x2bcd090; 1 drivers +v0x269c650_0 .net "BornB", 0 0, L_0x2bcd620; 1 drivers +v0x269c6d0_0 .net "CINandAxorB", 0 0, L_0x2bcdf80; 1 drivers +v0x26979a0_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x2697a20_0 .net *"_s3", 0 0, L_0x2bcd950; 1 drivers +v0x2692cf0_0 .net *"_s5", 0 0, L_0x2bcdb30; 1 drivers +v0x2692d70_0 .net "carryin", 0 0, L_0x2bcd1c0; 1 drivers +v0x268e0b0_0 .net "carryout", 0 0, L_0x2bce090; 1 drivers +v0x268e130_0 .net "nB", 0 0, L_0x2bcbda0; 1 drivers +v0x268db30_0 .net "nCmd2", 0 0, L_0x2bcd890; 1 drivers +v0x2689440_0 .net "subtract", 0 0, L_0x2bcd9f0; 1 drivers +L_0x2bcd7f0 .part v0x2960210_0, 0, 1; +L_0x2bcd950 .part v0x2960210_0, 2, 1; +L_0x2bcdb30 .part v0x2960210_0, 0, 1; +S_0x26af1e0 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x26af760; + .timescale -9 -12; +L_0x2bcd3e0/d .functor NOT 1, L_0x2bcd7f0, C4<0>, C4<0>, C4<0>; +L_0x2bcd3e0 .delay (10000,10000,10000) L_0x2bcd3e0/d; +L_0x2bcd440/d .functor AND 1, L_0x2bcd090, L_0x2bcd3e0, C4<1>, C4<1>; +L_0x2bcd440 .delay (20000,20000,20000) L_0x2bcd440/d; +L_0x2bcd530/d .functor AND 1, L_0x2bcbda0, L_0x2bcd7f0, C4<1>, C4<1>; +L_0x2bcd530 .delay (20000,20000,20000) L_0x2bcd530/d; +L_0x2bcd620/d .functor OR 1, L_0x2bcd440, L_0x2bcd530, C4<0>, C4<0>; +L_0x2bcd620 .delay (20000,20000,20000) L_0x2bcd620/d; +v0x26b4470_0 .net "S", 0 0, L_0x2bcd7f0; 1 drivers +v0x26aaaf0_0 .alias "in0", 0 0, v0x26a1380_0; +v0x26aab90_0 .alias "in1", 0 0, v0x268e130_0; +v0x26aa570_0 .net "nS", 0 0, L_0x2bcd3e0; 1 drivers +v0x26aa5f0_0 .net "out0", 0 0, L_0x2bcd440; 1 drivers +v0x26a5e80_0 .net "out1", 0 0, L_0x2bcd530; 1 drivers +v0x26a5f20_0 .alias "outfinal", 0 0, v0x269c650_0; +S_0x26dbd50 .scope generate, "addbits[26]" "addbits[26]" 3 283, 3 283, S_0x23ec510; + .timescale -9 -12; +P_0x2267c98 .param/l "i" 3 283, +C4<011010>; +S_0x26dbae0 .scope module, "attempt" "MiddleAddSubSLT" 3 285, 3 189, S_0x26dbd50; + .timescale -9 -12; +L_0x2bcd260/d .functor NOT 1, L_0x2bce560, C4<0>, C4<0>, C4<0>; +L_0x2bcd260 .delay (10000,10000,10000) L_0x2bcd260/d; +L_0x2bcedb0/d .functor NOT 1, L_0x2bcee70, C4<0>, C4<0>, C4<0>; +L_0x2bcedb0 .delay (10000,10000,10000) L_0x2bcedb0/d; +L_0x2bcef10/d .functor AND 1, L_0x2bcf050, L_0x2bcedb0, C4<1>, C4<1>; +L_0x2bcef10 .delay (20000,20000,20000) L_0x2bcef10/d; +L_0x2bcf0f0/d .functor XOR 1, L_0x2bce4c0, L_0x2bceb20, C4<0>, C4<0>; +L_0x2bcf0f0 .delay (40000,40000,40000) L_0x2bcf0f0/d; +L_0x2bcf1e0/d .functor XOR 1, L_0x2bcf0f0, L_0x2bce690, C4<0>, C4<0>; +L_0x2bcf1e0 .delay (40000,40000,40000) L_0x2bcf1e0/d; +L_0x2bcf2d0/d .functor AND 1, L_0x2bce4c0, L_0x2bceb20, C4<1>, C4<1>; +L_0x2bcf2d0 .delay (20000,20000,20000) L_0x2bcf2d0/d; +L_0x2bcf440/d .functor AND 1, L_0x2bcf0f0, L_0x2bce690, C4<1>, C4<1>; +L_0x2bcf440 .delay (20000,20000,20000) L_0x2bcf440/d; +L_0x2bcf550/d .functor OR 1, L_0x2bcf2d0, L_0x2bcf440, C4<0>, C4<0>; +L_0x2bcf550 .delay (20000,20000,20000) L_0x2bcf550/d; +v0x26d08c0_0 .net "A", 0 0, L_0x2bce4c0; 1 drivers +v0x26d0960_0 .net "AandB", 0 0, L_0x2bcf2d0; 1 drivers +v0x26cc1d0_0 .net "AddSubSLTSum", 0 0, L_0x2bcf1e0; 1 drivers +v0x26cc250_0 .net "AxorB", 0 0, L_0x2bcf0f0; 1 drivers +v0x26cbc50_0 .net "B", 0 0, L_0x2bce560; 1 drivers +v0x26cbcd0_0 .net "BornB", 0 0, L_0x2bceb20; 1 drivers +v0x26c7560_0 .net "CINandAxorB", 0 0, L_0x2bcf440; 1 drivers +v0x26c75e0_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x26c6fe0_0 .net *"_s3", 0 0, L_0x2bcee70; 1 drivers +v0x26c7060_0 .net *"_s5", 0 0, L_0x2bcf050; 1 drivers +v0x26c28b0_0 .net "carryin", 0 0, L_0x2bce690; 1 drivers +v0x26c2930_0 .net "carryout", 0 0, L_0x2bcf550; 1 drivers +v0x26bdd50_0 .net "nB", 0 0, L_0x2bcd260; 1 drivers +v0x26b90a0_0 .net "nCmd2", 0 0, L_0x2bcedb0; 1 drivers +v0x26b43f0_0 .net "subtract", 0 0, L_0x2bcef10; 1 drivers +L_0x2bcecf0 .part v0x2960210_0, 0, 1; +L_0x2bcee70 .part v0x2960210_0, 2, 1; +L_0x2bcf050 .part v0x2960210_0, 0, 1; +S_0x26db840 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x26dbae0; + .timescale -9 -12; +L_0x2bcd330/d .functor NOT 1, L_0x2bcecf0, C4<0>, C4<0>, C4<0>; +L_0x2bcd330 .delay (10000,10000,10000) L_0x2bcd330/d; +L_0x2bce920/d .functor AND 1, L_0x2bce560, L_0x2bcd330, C4<1>, C4<1>; +L_0x2bce920 .delay (20000,20000,20000) L_0x2bce920/d; +L_0x2bcea10/d .functor AND 1, L_0x2bcd260, L_0x2bcecf0, C4<1>, C4<1>; +L_0x2bcea10 .delay (20000,20000,20000) L_0x2bcea10/d; +L_0x2bceb20/d .functor OR 1, L_0x2bce920, L_0x2bcea10, C4<0>, C4<0>; +L_0x2bceb20 .delay (20000,20000,20000) L_0x2bceb20/d; +v0x2654c80_0 .net "S", 0 0, L_0x2bcecf0; 1 drivers +v0x26db380_0 .alias "in0", 0 0, v0x26cbc50_0; +v0x26db420_0 .alias "in1", 0 0, v0x26bdd50_0; +v0x26d5ae0_0 .net "nS", 0 0, L_0x2bcd330; 1 drivers +v0x26d5b60_0 .net "out0", 0 0, L_0x2bce920; 1 drivers +v0x26d0e40_0 .net "out1", 0 0, L_0x2bcea10; 1 drivers +v0x26d0ee0_0 .alias "outfinal", 0 0, v0x26cbcd0_0; +S_0x2415e10 .scope generate, "addbits[27]" "addbits[27]" 3 283, 3 283, S_0x23ec510; + .timescale -9 -12; +P_0x22cd388 .param/l "i" 3 283, +C4<011011>; +S_0x2415b60 .scope module, "attempt" "MiddleAddSubSLT" 3 285, 3 189, S_0x2415e10; + .timescale -9 -12; +L_0x2bce730/d .functor NOT 1, L_0x2bcfa20, C4<0>, C4<0>, C4<0>; +L_0x2bce730 .delay (10000,10000,10000) L_0x2bce730/d; +L_0x2bd0270/d .functor NOT 1, L_0x2bd0330, C4<0>, C4<0>, C4<0>; +L_0x2bd0270 .delay (10000,10000,10000) L_0x2bd0270/d; +L_0x2bd03d0/d .functor AND 1, L_0x2bd0510, L_0x2bd0270, C4<1>, C4<1>; +L_0x2bd03d0 .delay (20000,20000,20000) L_0x2bd03d0/d; +L_0x2bd05b0/d .functor XOR 1, L_0x2bcf980, L_0x2bcffe0, C4<0>, C4<0>; +L_0x2bd05b0 .delay (40000,40000,40000) L_0x2bd05b0/d; +L_0x2bd06a0/d .functor XOR 1, L_0x2bd05b0, L_0x2bcfb50, C4<0>, C4<0>; +L_0x2bd06a0 .delay (40000,40000,40000) L_0x2bd06a0/d; +L_0x2bd0790/d .functor AND 1, L_0x2bcf980, L_0x2bcffe0, C4<1>, C4<1>; +L_0x2bd0790 .delay (20000,20000,20000) L_0x2bd0790/d; +L_0x2bd0920/d .functor AND 1, L_0x2bd05b0, L_0x2bcfb50, C4<1>, C4<1>; +L_0x2bd0920 .delay (20000,20000,20000) L_0x2bd0920/d; +L_0x2bd0a30/d .functor OR 1, L_0x2bd0790, L_0x2bd0920, C4<0>, C4<0>; +L_0x2bd0a30 .delay (20000,20000,20000) L_0x2bd0a30/d; +v0x27b6ba0_0 .net "A", 0 0, L_0x2bcf980; 1 drivers +v0x27b6900_0 .net "AandB", 0 0, L_0x2bd0790; 1 drivers +v0x27b69a0_0 .net "AddSubSLTSum", 0 0, L_0x2bd06a0; 1 drivers +v0x27b59a0_0 .net "AxorB", 0 0, L_0x2bd05b0; 1 drivers +v0x27b5a20_0 .net "B", 0 0, L_0x2bcfa20; 1 drivers +v0x27b5700_0 .net "BornB", 0 0, L_0x2bcffe0; 1 drivers +v0x27b5780_0 .net "CINandAxorB", 0 0, L_0x2bd0920; 1 drivers +v0x27b38e0_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x27b3960_0 .net *"_s3", 0 0, L_0x2bd0330; 1 drivers +v0x265e560_0 .net *"_s5", 0 0, L_0x2bd0510; 1 drivers +v0x265e5e0_0 .net "carryin", 0 0, L_0x2bcfb50; 1 drivers +v0x26598b0_0 .net "carryout", 0 0, L_0x2bd0a30; 1 drivers +v0x2659930_0 .net "nB", 0 0, L_0x2bce730; 1 drivers +v0x26df700_0 .net "nCmd2", 0 0, L_0x2bd0270; 1 drivers +v0x2654c00_0 .net "subtract", 0 0, L_0x2bd03d0; 1 drivers +L_0x2bd01b0 .part v0x2960210_0, 0, 1; +L_0x2bd0330 .part v0x2960210_0, 2, 1; +L_0x2bd0510 .part v0x2960210_0, 0, 1; +S_0x2419120 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x2415b60; + .timescale -9 -12; +L_0x2bcfd80/d .functor NOT 1, L_0x2bd01b0, C4<0>, C4<0>, C4<0>; +L_0x2bcfd80 .delay (10000,10000,10000) L_0x2bcfd80/d; +L_0x2bcfde0/d .functor AND 1, L_0x2bcfa20, L_0x2bcfd80, C4<1>, C4<1>; +L_0x2bcfde0 .delay (20000,20000,20000) L_0x2bcfde0/d; +L_0x2bcfed0/d .functor AND 1, L_0x2bce730, L_0x2bd01b0, C4<1>, C4<1>; +L_0x2bcfed0 .delay (20000,20000,20000) L_0x2bcfed0/d; +L_0x2bcffe0/d .functor OR 1, L_0x2bcfde0, L_0x2bcfed0, C4<0>, C4<0>; +L_0x2bcffe0 .delay (20000,20000,20000) L_0x2bcffe0/d; +v0x2411eb0_0 .net "S", 0 0, L_0x2bd01b0; 1 drivers +v0x2418e70_0 .alias "in0", 0 0, v0x27b5a20_0; +v0x2418f10_0 .alias "in1", 0 0, v0x2659930_0; +v0x2417f00_0 .net "nS", 0 0, L_0x2bcfd80; 1 drivers +v0x2417f80_0 .net "out0", 0 0, L_0x2bcfde0; 1 drivers +v0x2417c50_0 .net "out1", 0 0, L_0x2bcfed0; 1 drivers +v0x2417cf0_0 .alias "outfinal", 0 0, v0x27b5700_0; +S_0x240a190 .scope generate, "addbits[28]" "addbits[28]" 3 283, 3 283, S_0x23ec510; + .timescale -9 -12; +P_0x22c6068 .param/l "i" 3 283, +C4<011100>; +S_0x2409ee0 .scope module, "attempt" "MiddleAddSubSLT" 3 285, 3 189, S_0x240a190; + .timescale -9 -12; +L_0x2bcfbf0/d .functor NOT 1, L_0x2bd0f00, C4<0>, C4<0>, C4<0>; +L_0x2bcfbf0 .delay (10000,10000,10000) L_0x2bcfbf0/d; +L_0x2bd1740/d .functor NOT 1, L_0x2bd1800, C4<0>, C4<0>, C4<0>; +L_0x2bd1740 .delay (10000,10000,10000) L_0x2bd1740/d; +L_0x2bd18a0/d .functor AND 1, L_0x2bd19e0, L_0x2bd1740, C4<1>, C4<1>; +L_0x2bd18a0 .delay (20000,20000,20000) L_0x2bd18a0/d; +L_0x2bd1a80/d .functor XOR 1, L_0x2bd0e60, L_0x2bd1510, C4<0>, C4<0>; +L_0x2bd1a80 .delay (40000,40000,40000) L_0x2bd1a80/d; +L_0x2bd1b70/d .functor XOR 1, L_0x2bd1a80, L_0x2bd1030, C4<0>, C4<0>; +L_0x2bd1b70 .delay (40000,40000,40000) L_0x2bd1b70/d; +L_0x2bd1c60/d .functor AND 1, L_0x2bd0e60, L_0x2bd1510, C4<1>, C4<1>; +L_0x2bd1c60 .delay (20000,20000,20000) L_0x2bd1c60/d; +L_0x2bd1dd0/d .functor AND 1, L_0x2bd1a80, L_0x2bd1030, C4<1>, C4<1>; +L_0x2bd1dd0 .delay (20000,20000,20000) L_0x2bd1dd0/d; +L_0x2bd1ee0/d .functor OR 1, L_0x2bd1c60, L_0x2bd1dd0, C4<0>, C4<0>; +L_0x2bd1ee0 .delay (20000,20000,20000) L_0x2bd1ee0/d; +v0x240c280_0 .net "A", 0 0, L_0x2bd0e60; 1 drivers +v0x240bfd0_0 .net "AandB", 0 0, L_0x2bd1c60; 1 drivers +v0x240c070_0 .net "AddSubSLTSum", 0 0, L_0x2bd1b70; 1 drivers +v0x24096d0_0 .net "AxorB", 0 0, L_0x2bd1a80; 1 drivers +v0x2409750_0 .net "B", 0 0, L_0x2bd0f00; 1 drivers +v0x240fff0_0 .net "BornB", 0 0, L_0x2bd1510; 1 drivers +v0x2410070_0 .net "CINandAxorB", 0 0, L_0x2bd1dd0; 1 drivers +v0x240fd40_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x240fdc0_0 .net *"_s3", 0 0, L_0x2bd1800; 1 drivers +v0x2413300_0 .net *"_s5", 0 0, L_0x2bd19e0; 1 drivers +v0x2413380_0 .net "carryin", 0 0, L_0x2bd1030; 1 drivers +v0x2413050_0 .net "carryout", 0 0, L_0x2bd1ee0; 1 drivers +v0x24130d0_0 .net "nB", 0 0, L_0x2bcfbf0; 1 drivers +v0x24120e0_0 .net "nCmd2", 0 0, L_0x2bd1740; 1 drivers +v0x2411e30_0 .net "subtract", 0 0, L_0x2bd18a0; 1 drivers +L_0x2bd16a0 .part v0x2960210_0, 0, 1; +L_0x2bd1800 .part v0x2960210_0, 2, 1; +L_0x2bd19e0 .part v0x2960210_0, 0, 1; +S_0x2409c30 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x2409ee0; + .timescale -9 -12; +L_0x2bd1290/d .functor NOT 1, L_0x2bd16a0, C4<0>, C4<0>, C4<0>; +L_0x2bd1290 .delay (10000,10000,10000) L_0x2bd1290/d; +L_0x2bd1330/d .functor AND 1, L_0x2bd0f00, L_0x2bd1290, C4<1>, C4<1>; +L_0x2bd1330 .delay (20000,20000,20000) L_0x2bd1330/d; +L_0x2bd1420/d .functor AND 1, L_0x2bcfbf0, L_0x2bd16a0, C4<1>, C4<1>; +L_0x2bd1420 .delay (20000,20000,20000) L_0x2bd1420/d; +L_0x2bd1510/d .functor OR 1, L_0x2bd1330, L_0x2bd1420, C4<0>, C4<0>; +L_0x2bd1510 .delay (20000,20000,20000) L_0x2bd1510/d; +v0x240b840_0 .net "S", 0 0, L_0x2bd16a0; 1 drivers +v0x2409980_0 .alias "in0", 0 0, v0x2409750_0; +v0x2409a20_0 .alias "in1", 0 0, v0x24130d0_0; +v0x240d4c0_0 .net "nS", 0 0, L_0x2bd1290; 1 drivers +v0x240d540_0 .net "out0", 0 0, L_0x2bd1330; 1 drivers +v0x240d210_0 .net "out1", 0 0, L_0x2bd1420; 1 drivers +v0x240d2b0_0 .alias "outfinal", 0 0, v0x240fff0_0; +S_0x2405ec0 .scope generate, "addbits[29]" "addbits[29]" 3 283, 3 283, S_0x23ec510; + .timescale -9 -12; +P_0x22c0648 .param/l "i" 3 283, +C4<011101>; +S_0x2405c10 .scope module, "attempt" "MiddleAddSubSLT" 3 285, 3 189, S_0x2405ec0; + .timescale -9 -12; +L_0x2bd10d0/d .functor NOT 1, L_0x2ba5750, C4<0>, C4<0>, C4<0>; +L_0x2bd10d0 .delay (10000,10000,10000) L_0x2bd10d0/d; +L_0x2bd2bc0/d .functor NOT 1, L_0x2bd2c80, C4<0>, C4<0>, C4<0>; +L_0x2bd2bc0 .delay (10000,10000,10000) L_0x2bd2bc0/d; +L_0x2bd2d20/d .functor AND 1, L_0x2bd2e60, L_0x2bd2bc0, C4<1>, C4<1>; +L_0x2bd2d20 .delay (20000,20000,20000) L_0x2bd2d20/d; +L_0x2bd2f00/d .functor XOR 1, L_0x2ba56b0, L_0x2bd2990, C4<0>, C4<0>; +L_0x2bd2f00 .delay (40000,40000,40000) L_0x2bd2f00/d; +L_0x2bd3020/d .functor XOR 1, L_0x2bd2f00, L_0x2ba5880, C4<0>, C4<0>; +L_0x2bd3020 .delay (40000,40000,40000) L_0x2bd3020/d; +L_0x2bd3140/d .functor AND 1, L_0x2ba56b0, L_0x2bd2990, C4<1>, C4<1>; +L_0x2bd3140 .delay (20000,20000,20000) L_0x2bd3140/d; +L_0x2bd32b0/d .functor AND 1, L_0x2bd2f00, L_0x2ba5880, C4<1>, C4<1>; +L_0x2bd32b0 .delay (20000,20000,20000) L_0x2bd32b0/d; +L_0x2bd33c0/d .functor OR 1, L_0x2bd3140, L_0x2bd32b0, C4<0>, C4<0>; +L_0x2bd33c0 .delay (20000,20000,20000) L_0x2bd33c0/d; +v0x2403b20_0 .net "A", 0 0, L_0x2ba56b0; 1 drivers +v0x2407660_0 .net "AandB", 0 0, L_0x2bd3140; 1 drivers +v0x2407700_0 .net "AddSubSLTSum", 0 0, L_0x2bd3020; 1 drivers +v0x24073b0_0 .net "AxorB", 0 0, L_0x2bd2f00; 1 drivers +v0x2407430_0 .net "B", 0 0, L_0x2ba5750; 1 drivers +v0x2406420_0 .net "BornB", 0 0, L_0x2bd2990; 1 drivers +v0x24064a0_0 .net "CINandAxorB", 0 0, L_0x2bd32b0; 1 drivers +v0x2406170_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x24061f0_0 .net *"_s3", 0 0, L_0x2bd2c80; 1 drivers +v0x2403870_0 .net *"_s5", 0 0, L_0x2bd2e60; 1 drivers +v0x24038f0_0 .net "carryin", 0 0, L_0x2ba5880; 1 drivers +v0x240bd20_0 .net "carryout", 0 0, L_0x2bd33c0; 1 drivers +v0x240bda0_0 .net "nB", 0 0, L_0x2bd10d0; 1 drivers +v0x240ba70_0 .net "nCmd2", 0 0, L_0x2bd2bc0; 1 drivers +v0x240b7c0_0 .net "subtract", 0 0, L_0x2bd2d20; 1 drivers +L_0x2bd2b20 .part v0x2960210_0, 0, 1; +L_0x2bd2c80 .part v0x2960210_0, 2, 1; +L_0x2bd2e60 .part v0x2960210_0, 0, 1; +S_0x2405960 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x2405c10; + .timescale -9 -12; +L_0x2bd1230/d .functor NOT 1, L_0x2bd2b20, C4<0>, C4<0>, C4<0>; +L_0x2bd1230 .delay (10000,10000,10000) L_0x2bd1230/d; +L_0x2bd27b0/d .functor AND 1, L_0x2ba5750, L_0x2bd1230, C4<1>, C4<1>; +L_0x2bd27b0 .delay (20000,20000,20000) L_0x2bd27b0/d; +L_0x2bd28a0/d .functor AND 1, L_0x2bd10d0, L_0x2bd2b20, C4<1>, C4<1>; +L_0x2bd28a0 .delay (20000,20000,20000) L_0x2bd28a0/d; +L_0x2bd2990/d .functor OR 1, L_0x2bd27b0, L_0x2bd28a0, C4<0>, C4<0>; +L_0x2bd2990 .delay (20000,20000,20000) L_0x2bd2990/d; +v0x23fda90_0 .net "S", 0 0, L_0x2bd2b20; 1 drivers +v0x2404330_0 .alias "in0", 0 0, v0x2407430_0; +v0x24043d0_0 .alias "in1", 0 0, v0x240bda0_0; +v0x2404080_0 .net "nS", 0 0, L_0x2bd1230; 1 drivers +v0x2404100_0 .net "out0", 0 0, L_0x2bd27b0; 1 drivers +v0x2403dd0_0 .net "out1", 0 0, L_0x2bd28a0; 1 drivers +v0x2403e70_0 .alias "outfinal", 0 0, v0x2406420_0; +S_0x23fb710 .scope generate, "addbits[30]" "addbits[30]" 3 283, 3 283, S_0x23ec510; + .timescale -9 -12; +P_0x22ba6f8 .param/l "i" 3 283, +C4<011110>; +S_0x23fa7a0 .scope module, "attempt" "MiddleAddSubSLT" 3 285, 3 189, S_0x23fb710; + .timescale -9 -12; +L_0x2ba5920/d .functor NOT 1, L_0x2bd4600, C4<0>, C4<0>, C4<0>; +L_0x2ba5920 .delay (10000,10000,10000) L_0x2ba5920/d; +L_0x2bd37a0/d .functor NOT 1, L_0x2bd3860, C4<0>, C4<0>, C4<0>; +L_0x2bd37a0 .delay (10000,10000,10000) L_0x2bd37a0/d; +L_0x2bd3900/d .functor AND 1, L_0x2bd3a40, L_0x2bd37a0, C4<1>, C4<1>; +L_0x2bd3900 .delay (20000,20000,20000) L_0x2bd3900/d; +L_0x2bd3ae0/d .functor XOR 1, L_0x2bd4560, L_0x2bd25a0, C4<0>, C4<0>; +L_0x2bd3ae0 .delay (40000,40000,40000) L_0x2bd3ae0/d; +L_0x2bd3bd0/d .functor XOR 1, L_0x2bd3ae0, L_0x2bd4730, C4<0>, C4<0>; +L_0x2bd3bd0 .delay (40000,40000,40000) L_0x2bd3bd0/d; +L_0x2bd4a80/d .functor AND 1, L_0x2bd4560, L_0x2bd25a0, C4<1>, C4<1>; +L_0x2bd4a80 .delay (20000,20000,20000) L_0x2bd4a80/d; +L_0x2bd4bf0/d .functor AND 1, L_0x2bd3ae0, L_0x2bd4730, C4<1>, C4<1>; +L_0x2bd4bf0 .delay (20000,20000,20000) L_0x2bd4bf0/d; +L_0x2bd4ce0/d .functor OR 1, L_0x2bd4a80, L_0x2bd4bf0, C4<0>, C4<0>; +L_0x2bd4ce0 .delay (20000,20000,20000) L_0x2bd4ce0/d; +v0x23fe4d0_0 .net "A", 0 0, L_0x2bd4560; 1 drivers +v0x23fe220_0 .net "AandB", 0 0, L_0x2bd4a80; 1 drivers +v0x23fe2c0_0 .net "AddSubSLTSum", 0 0, L_0x2bd3bd0; 1 drivers +v0x23fdf70_0 .net "AxorB", 0 0, L_0x2bd3ae0; 1 drivers +v0x23fdff0_0 .net "B", 0 0, L_0x2bd4600; 1 drivers +v0x23fdcc0_0 .net "BornB", 0 0, L_0x2bd25a0; 1 drivers +v0x23fdd40_0 .net "CINandAxorB", 0 0, L_0x2bd4bf0; 1 drivers +v0x2401800_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x2401880_0 .net *"_s3", 0 0, L_0x2bd3860; 1 drivers +v0x2401550_0 .net *"_s5", 0 0, L_0x2bd3a40; 1 drivers +v0x24015d0_0 .net "carryin", 0 0, L_0x2bd4730; 1 drivers +v0x24005c0_0 .net "carryout", 0 0, L_0x2bd4ce0; 1 drivers +v0x2400640_0 .net "nB", 0 0, L_0x2ba5920; 1 drivers +v0x2400310_0 .net "nCmd2", 0 0, L_0x2bd37a0; 1 drivers +v0x23fda10_0 .net "subtract", 0 0, L_0x2bd3900; 1 drivers +L_0x2bd3700 .part v0x2960210_0, 0, 1; +L_0x2bd3860 .part v0x2960210_0, 2, 1; +L_0x2bd3a40 .part v0x2960210_0, 0, 1; +S_0x23fa4f0 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x23fa7a0; + .timescale -9 -12; +L_0x2bd22c0/d .functor NOT 1, L_0x2bd3700, C4<0>, C4<0>, C4<0>; +L_0x2bd22c0 .delay (10000,10000,10000) L_0x2bd22c0/d; +L_0x2bd2380/d .functor AND 1, L_0x2bd4600, L_0x2bd22c0, C4<1>, C4<1>; +L_0x2bd2380 .delay (20000,20000,20000) L_0x2bd2380/d; +L_0x2bd2490/d .functor AND 1, L_0x2ba5920, L_0x2bd3700, C4<1>, C4<1>; +L_0x2bd2490 .delay (20000,20000,20000) L_0x2bd2490/d; +L_0x2bd25a0/d .functor OR 1, L_0x2bd2380, L_0x2bd2490, C4<0>, C4<0>; +L_0x2bd25a0 .delay (20000,20000,20000) L_0x2bd25a0/d; +v0x23fba40_0 .net "S", 0 0, L_0x2bd3700; 1 drivers +v0x2400060_0 .alias "in0", 0 0, v0x23fdff0_0; +v0x24000e0_0 .alias "in1", 0 0, v0x2400640_0; +v0x23ffdb0_0 .net "nS", 0 0, L_0x2bd22c0; 1 drivers +v0x23ffe30_0 .net "out0", 0 0, L_0x2bd2380; 1 drivers +v0x23ffb00_0 .net "out1", 0 0, L_0x2bd2490; 1 drivers +v0x23ffba0_0 .alias "outfinal", 0 0, v0x23fdcc0_0; +S_0x23ec260 .scope generate, "addbits[31]" "addbits[31]" 3 283, 3 283, S_0x23ec510; + .timescale -9 -12; +P_0x22b12d8 .param/l "i" 3 283, +C4<011111>; +S_0x23efd80 .scope module, "attempt" "MiddleAddSubSLT" 3 285, 3 189, S_0x23ec260; + .timescale -9 -12; +L_0x2bd47d0/d .functor NOT 1, L_0x2bd5190, C4<0>, C4<0>, C4<0>; +L_0x2bd47d0 .delay (10000,10000,10000) L_0x2bd47d0/d; +L_0x2bd59c0/d .functor NOT 1, L_0x2bd5a60, C4<0>, C4<0>, C4<0>; +L_0x2bd59c0 .delay (10000,10000,10000) L_0x2bd59c0/d; +L_0x2bd5b00/d .functor AND 1, L_0x2bd5c40, L_0x2bd59c0, C4<1>, C4<1>; +L_0x2bd5b00 .delay (20000,20000,20000) L_0x2bd5b00/d; +L_0x2bd5ce0/d .functor XOR 1, L_0x2bd50f0, L_0x2bd5790, C4<0>, C4<0>; +L_0x2bd5ce0 .delay (40000,40000,40000) L_0x2bd5ce0/d; +L_0x2bd5dd0/d .functor XOR 1, L_0x2bd5ce0, L_0x2bd52c0, C4<0>, C4<0>; +L_0x2bd5dd0 .delay (40000,40000,40000) L_0x2bd5dd0/d; +L_0x2bd5ef0/d .functor AND 1, L_0x2bd50f0, L_0x2bd5790, C4<1>, C4<1>; +L_0x2bd5ef0 .delay (20000,20000,20000) L_0x2bd5ef0/d; +L_0x2bd6090/d .functor AND 1, L_0x2bd5ce0, L_0x2bd52c0, C4<1>, C4<1>; +L_0x2bd6090 .delay (20000,20000,20000) L_0x2bd6090/d; +L_0x2bd6180/d .functor OR 1, L_0x2bd5ef0, L_0x2bd6090, C4<0>, C4<0>; +L_0x2bd6180 .delay (20000,20000,20000) L_0x2bd6180/d; +v0x23f2910_0 .net "A", 0 0, L_0x2bd50f0; 1 drivers +v0x23f25e0_0 .net "AandB", 0 0, L_0x2bd5ef0; 1 drivers +v0x23f2660_0 .net "AddSubSLTSum", 0 0, L_0x2bd5dd0; 1 drivers +v0x23f5ba0_0 .net "AxorB", 0 0, L_0x2bd5ce0; 1 drivers +v0x23f5c20_0 .net "B", 0 0, L_0x2bd5190; 1 drivers +v0x23f58f0_0 .net "BornB", 0 0, L_0x2bd5790; 1 drivers +v0x23f5970_0 .net "CINandAxorB", 0 0, L_0x2bd6090; 1 drivers +v0x23f4980_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x23f4a00_0 .net *"_s3", 0 0, L_0x2bd5a60; 1 drivers +v0x23f46d0_0 .net *"_s5", 0 0, L_0x2bd5c40; 1 drivers +v0x23f4750_0 .net "carryin", 0 0, L_0x2bd52c0; 1 drivers +v0x23f86b0_0 .net "carryout", 0 0, L_0x2bd6180; 1 drivers +v0x23f8730_0 .net "nB", 0 0, L_0x2bd47d0; 1 drivers +v0x23f8400_0 .net "nCmd2", 0 0, L_0x2bd59c0; 1 drivers +v0x23fb9c0_0 .net "subtract", 0 0, L_0x2bd5b00; 1 drivers +L_0x2bd5920 .part v0x2960210_0, 0, 1; +L_0x2bd5a60 .part v0x2960210_0, 2, 1; +L_0x2bd5c40 .part v0x2960210_0, 0, 1; +S_0x23efad0 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x23efd80; + .timescale -9 -12; +L_0x2bd4930/d .functor NOT 1, L_0x2bd5920, C4<0>, C4<0>, C4<0>; +L_0x2bd4930 .delay (10000,10000,10000) L_0x2bd4930/d; +L_0x2bd55b0/d .functor AND 1, L_0x2bd5190, L_0x2bd4930, C4<1>, C4<1>; +L_0x2bd55b0 .delay (20000,20000,20000) L_0x2bd55b0/d; +L_0x2bd56a0/d .functor AND 1, L_0x2bd47d0, L_0x2bd5920, C4<1>, C4<1>; +L_0x2bd56a0 .delay (20000,20000,20000) L_0x2bd56a0/d; +L_0x2bd5790/d .functor OR 1, L_0x2bd55b0, L_0x2bd56a0, C4<0>, C4<0>; +L_0x2bd5790 .delay (20000,20000,20000) L_0x2bd5790/d; +v0x23eeb60_0 .net "S", 0 0, L_0x2bd5920; 1 drivers +v0x23eebe0_0 .alias "in0", 0 0, v0x23f5c20_0; +v0x23ee8b0_0 .alias "in1", 0 0, v0x23f8730_0; +v0x23ee930_0 .net "nS", 0 0, L_0x2bd4930; 1 drivers +v0x23ebfb0_0 .net "out0", 0 0, L_0x2bd55b0; 1 drivers +v0x23ec030_0 .net "out1", 0 0, L_0x2bd56a0; 1 drivers +v0x23f2890_0 .alias "outfinal", 0 0, v0x23f58f0_0; +S_0x2543140 .scope module, "trial1" "AndNand32" 3 54, 3 216, S_0x1f6b890; + .timescale -9 -12; +P_0x24b4d58 .param/l "size" 3 223, +C4<0100000>; +v0x23eca70_0 .alias "A", 31 0, v0x295f580_0; +v0x23ecaf0_0 .alias "AndNandOut", 31 0, v0x2418bc0_0; +v0x23ec7c0_0 .alias "B", 31 0, v0x295f6a0_0; +v0x23ec840_0 .alias "Command", 2 0, v0x295f7a0_0; +L_0x2bd7eb0 .part/pv L_0x2bd7c40, 1, 1, 32; +L_0x2b3e060 .part v0x295fe90_0, 1, 1; +L_0x2b3e100 .part v0x2960190_0, 1, 1; +L_0x2bd9ac0 .part/pv L_0x2bd9870, 2, 1, 32; +L_0x2bd9b60 .part v0x295fe90_0, 2, 1; +L_0x2bd9c00 .part v0x2960190_0, 2, 1; +L_0x2bda570 .part/pv L_0x2bda300, 3, 1, 32; +L_0x2bda610 .part v0x295fe90_0, 3, 1; +L_0x2bda700 .part v0x2960190_0, 3, 1; +L_0x2bdafd0 .part/pv L_0x2bdad60, 4, 1, 32; +L_0x2bdb0d0 .part v0x295fe90_0, 4, 1; +L_0x2bdb170 .part v0x2960190_0, 4, 1; +L_0x2bdba60 .part/pv L_0x2bdb7f0, 5, 1, 32; +L_0x2bdbb00 .part v0x295fe90_0, 5, 1; +L_0x2bdbc20 .part v0x2960190_0, 5, 1; +L_0x2bdc530 .part/pv L_0x2bdc2c0, 6, 1, 32; +L_0x2bdc660 .part v0x295fe90_0, 6, 1; +L_0x2bdc700 .part v0x2960190_0, 6, 1; +L_0x2bdd050 .part/pv L_0x2bdcde0, 7, 1, 32; +L_0x2bdd0f0 .part v0x295fe90_0, 7, 1; +L_0x2bdc7f0 .part v0x2960190_0, 7, 1; +L_0x2bddab0 .part/pv L_0x2bdd840, 8, 1, 32; +L_0x2bdd190 .part v0x295fe90_0, 8, 1; +L_0x2bddc10 .part v0x2960190_0, 8, 1; +L_0x2bde550 .part/pv L_0x2bde2e0, 9, 1, 32; +L_0x2bde5f0 .part v0x295fe90_0, 9, 1; +L_0x2bddd00 .part v0x2960190_0, 9, 1; +L_0x2bdefc0 .part/pv L_0x2bded50, 10, 1, 32; +L_0x2bde690 .part v0x295fe90_0, 10, 1; +L_0x2bdf150 .part v0x2960190_0, 10, 1; +L_0x2bdfa50 .part/pv L_0x2bdf7e0, 11, 1, 32; +L_0x2bdfaf0 .part v0x295fe90_0, 11, 1; +L_0x2bdf240 .part v0x2960190_0, 11, 1; +L_0x2be04c0 .part/pv L_0x2be0250, 12, 1, 32; +L_0x2bdfb90 .part v0x295fe90_0, 12, 1; +L_0x2be0680 .part v0x2960190_0, 12, 1; +L_0x2be0f60 .part/pv L_0x2be0cf0, 13, 1, 32; +L_0x2be1000 .part v0x295fe90_0, 13, 1; +L_0x2be0720 .part v0x2960190_0, 13, 1; +L_0x2be19c0 .part/pv L_0x2be1750, 14, 1, 32; +L_0x2be10a0 .part v0x295fe90_0, 14, 1; +L_0x2be1140 .part v0x2960190_0, 14, 1; +L_0x2be2450 .part/pv L_0x2be21e0, 15, 1, 32; +L_0x2be24f0 .part v0x295fe90_0, 15, 1; +L_0x2be1c00 .part v0x2960190_0, 15, 1; +L_0x2be2ec0 .part/pv L_0x2be2c50, 16, 1, 32; +L_0x2be2590 .part v0x295fe90_0, 16, 1; +L_0x2be2630 .part v0x2960190_0, 16, 1; +L_0x2be3960 .part/pv L_0x2be36f0, 17, 1, 32; +L_0x2be3a00 .part v0x295fe90_0, 17, 1; +L_0x2be3130 .part v0x2960190_0, 17, 1; +L_0x2be43c0 .part/pv L_0x2be4150, 18, 1, 32; +L_0x2be3aa0 .part v0x295fe90_0, 18, 1; +L_0x2be3b40 .part v0x2960190_0, 18, 1; +L_0x2be4e60 .part/pv L_0x2be4bf0, 19, 1, 32; +L_0x2be4f00 .part v0x295fe90_0, 19, 1; +L_0x2be4460 .part v0x2960190_0, 19, 1; +L_0x2be58c0 .part/pv L_0x2be5650, 20, 1, 32; +L_0x2be4fa0 .part v0x295fe90_0, 20, 1; +L_0x2be5040 .part v0x2960190_0, 20, 1; +L_0x2be6250 .part/pv L_0x2bdbba0, 21, 1, 32; +L_0x2be62f0 .part v0x295fe90_0, 21, 1; +L_0x2be5960 .part v0x2960190_0, 21, 1; +L_0x2be6c00 .part/pv L_0x2be69d0, 22, 1, 32; +L_0x2be6390 .part v0x295fe90_0, 22, 1; +L_0x2be6430 .part v0x2960190_0, 22, 1; +L_0x2be7580 .part/pv L_0x2be7350, 23, 1, 32; +L_0x2be7620 .part v0x295fe90_0, 23, 1; +L_0x2be6ca0 .part v0x2960190_0, 23, 1; +L_0x2be7f20 .part/pv L_0x2be7cf0, 24, 1, 32; +L_0x2be76c0 .part v0x295fe90_0, 24, 1; +L_0x2be7760 .part v0x2960190_0, 24, 1; +L_0x2be8890 .part/pv L_0x2be8660, 25, 1, 32; +L_0x2be8930 .part v0x295fe90_0, 25, 1; +L_0x2be7fc0 .part v0x2960190_0, 25, 1; +L_0x2be9210 .part/pv L_0x2be8fe0, 26, 1, 32; +L_0x2be89d0 .part v0x295fe90_0, 26, 1; +L_0x2be8a70 .part v0x2960190_0, 26, 1; +L_0x2be9ba0 .part/pv L_0x2be9970, 27, 1, 32; +L_0x2be9c40 .part v0x295fe90_0, 27, 1; +L_0x2be92b0 .part v0x2960190_0, 27, 1; +L_0x2bea5b0 .part/pv L_0x2bea340, 28, 1, 32; +L_0x2be9ce0 .part v0x295fe90_0, 28, 1; +L_0x2be9d80 .part v0x2960190_0, 28, 1; +L_0x2beb050 .part/pv L_0x2beade0, 29, 1, 32; +L_0x2beb0f0 .part v0x295fe90_0, 29, 1; +L_0x2bea650 .part v0x2960190_0, 29, 1; +L_0x2bebab0 .part/pv L_0x2beb840, 30, 1, 32; +L_0x2beb190 .part v0x295fe90_0, 30, 1; +L_0x2beb230 .part v0x2960190_0, 30, 1; +L_0x2bec540 .part/pv L_0x2bec2d0, 31, 1, 32; +L_0x2bec5e0 .part v0x295fe90_0, 31, 1; +L_0x2bebb50 .part v0x2960190_0, 31, 1; +L_0x2becfb0 .part/pv L_0x2becd40, 0, 1, 32; +L_0x2bec680 .part v0x295fe90_0, 0, 1; +L_0x2bec720 .part v0x2960190_0, 0, 1; +S_0x23e6960 .scope module, "attempt2" "AndNand" 3 227, 3 149, S_0x2543140; + .timescale -9 -12; +L_0x2bebc40/d .functor NAND 1, L_0x2bec680, L_0x2bec720, C4<1>, C4<1>; +L_0x2bebc40 .delay (10000,10000,10000) L_0x2bebc40/d; +L_0x2bebda0/d .functor NOT 1, L_0x2bebc40, C4<0>, C4<0>, C4<0>; +L_0x2bebda0 .delay (10000,10000,10000) L_0x2bebda0/d; +v0x23e8d00_0 .net "A", 0 0, L_0x2bec680; 1 drivers +v0x23e8d80_0 .net "AandB", 0 0, L_0x2bebda0; 1 drivers +v0x23e8a50_0 .net "AnandB", 0 0, L_0x2bebc40; 1 drivers +v0x23e8ad0_0 .net "AndNandOut", 0 0, L_0x2becd40; 1 drivers +v0x23e6150_0 .net "B", 0 0, L_0x2bec720; 1 drivers +v0x23e61d0_0 .alias "Command", 2 0, v0x295f7a0_0; +L_0x2becf10 .part v0x2960210_0, 0, 1; +S_0x23e66b0 .scope module, "potato" "TwoInMux" 3 161, 3 109, S_0x23e6960; + .timescale -9 -12; +L_0x2beca20/d .functor NOT 1, L_0x2becf10, C4<0>, C4<0>, C4<0>; +L_0x2beca20 .delay (10000,10000,10000) L_0x2beca20/d; +L_0x2becae0/d .functor AND 1, L_0x2bebda0, L_0x2beca20, C4<1>, C4<1>; +L_0x2becae0 .delay (20000,20000,20000) L_0x2becae0/d; +L_0x2becbf0/d .functor AND 1, L_0x2bebc40, L_0x2becf10, C4<1>, C4<1>; +L_0x2becbf0 .delay (20000,20000,20000) L_0x2becbf0/d; +L_0x2becd40/d .functor OR 1, L_0x2becae0, L_0x2becbf0, C4<0>, C4<0>; +L_0x2becd40 .delay (20000,20000,20000) L_0x2becd40/d; +v0x23e6c90_0 .net "S", 0 0, L_0x2becf10; 1 drivers +v0x23e6400_0 .alias "in0", 0 0, v0x23e8d80_0; +v0x23e6480_0 .alias "in1", 0 0, v0x23e8a50_0; +v0x23e9f40_0 .net "nS", 0 0, L_0x2beca20; 1 drivers +v0x23e9fc0_0 .net "out0", 0 0, L_0x2becae0; 1 drivers +v0x23e9c90_0 .net "out1", 0 0, L_0x2becbf0; 1 drivers +v0x23e9d10_0 .alias "outfinal", 0 0, v0x23e8ad0_0; +S_0x23e0600 .scope generate, "andbits[1]" "andbits[1]" 3 231, 3 231, S_0x2543140; + .timescale -9 -12; +P_0x22a0a58 .param/l "i" 3 231, +C4<01>; +S_0x23e40e0 .scope module, "attempt" "AndNand" 3 233, 3 149, S_0x23e0600; + .timescale -9 -12; +L_0x2bd6a20/d .functor NAND 1, L_0x2b3e060, L_0x2b3e100, C4<1>, C4<1>; +L_0x2bd6a20 .delay (10000,10000,10000) L_0x2bd6a20/d; +L_0x2b88560/d .functor NOT 1, L_0x2bd6a20, C4<0>, C4<0>, C4<0>; +L_0x2b88560 .delay (10000,10000,10000) L_0x2b88560/d; +v0x23e8820_0 .net "A", 0 0, L_0x2b3e060; 1 drivers +v0x23e84f0_0 .net "AandB", 0 0, L_0x2b88560; 1 drivers +v0x23e8570_0 .net "AnandB", 0 0, L_0x2bd6a20; 1 drivers +v0x23e8240_0 .net "AndNandOut", 0 0, L_0x2bd7c40; 1 drivers +v0x23e82c0_0 .net "B", 0 0, L_0x2b3e100; 1 drivers +v0x23e6c10_0 .alias "Command", 2 0, v0x295f7a0_0; +L_0x2bd7e10 .part v0x2960210_0, 0, 1; +S_0x23e3e30 .scope module, "potato" "TwoInMux" 3 161, 3 109, S_0x23e40e0; + .timescale -9 -12; +L_0x2b88690/d .functor NOT 1, L_0x2bd7e10, C4<0>, C4<0>, C4<0>; +L_0x2b88690 .delay (10000,10000,10000) L_0x2b88690/d; +L_0x2bd79e0/d .functor AND 1, L_0x2b88560, L_0x2b88690, C4<1>, C4<1>; +L_0x2bd79e0 .delay (20000,20000,20000) L_0x2bd79e0/d; +L_0x2bd7af0/d .functor AND 1, L_0x2bd6a20, L_0x2bd7e10, C4<1>, C4<1>; +L_0x2bd7af0 .delay (20000,20000,20000) L_0x2bd7af0/d; +L_0x2bd7c40/d .functor OR 1, L_0x2bd79e0, L_0x2bd7af0, C4<0>, C4<0>; +L_0x2bd7c40 .delay (20000,20000,20000) L_0x2bd7c40/d; +v0x23e2ea0_0 .net "S", 0 0, L_0x2bd7e10; 1 drivers +v0x23e2f20_0 .alias "in0", 0 0, v0x23e84f0_0; +v0x23e2bf0_0 .alias "in1", 0 0, v0x23e8570_0; +v0x23e2c70_0 .net "nS", 0 0, L_0x2b88690; 1 drivers +v0x23e0080_0 .net "out0", 0 0, L_0x2bd79e0; 1 drivers +v0x23e0100_0 .net "out1", 0 0, L_0x2bd7af0; 1 drivers +v0x23e87a0_0 .alias "outfinal", 0 0, v0x23e8240_0; +S_0x23dde70 .scope generate, "andbits[2]" "andbits[2]" 3 231, 3 231, S_0x2543140; + .timescale -9 -12; +P_0x2296668 .param/l "i" 3 231, +C4<010>; +S_0x23dd1f0 .scope module, "attempt" "AndNand" 3 233, 3 149, S_0x23dde70; + .timescale -9 -12; +L_0x2bd7f50/d .functor NAND 1, L_0x2bd9b60, L_0x2bd9c00, C4<1>, C4<1>; +L_0x2bd7f50 .delay (10000,10000,10000) L_0x2bd7f50/d; +L_0x2b3e2f0/d .functor NOT 1, L_0x2bd7f50, C4<0>, C4<0>, C4<0>; +L_0x2b3e2f0 .delay (10000,10000,10000) L_0x2b3e2f0/d; +v0x23e0db0_0 .net "A", 0 0, L_0x2bd9b60; 1 drivers +v0x23e0e50_0 .net "AandB", 0 0, L_0x2b3e2f0; 1 drivers +v0x23e0b20_0 .net "AnandB", 0 0, L_0x2bd7f50; 1 drivers +v0x23e0ba0_0 .net "AndNandOut", 0 0, L_0x2bd9870; 1 drivers +v0x23e0890_0 .net "B", 0 0, L_0x2bd9c00; 1 drivers +v0x23e0910_0 .alias "Command", 2 0, v0x295f7a0_0; +L_0x2bd9a20 .part v0x2960210_0, 0, 1; +S_0x23dcf60 .scope module, "potato" "TwoInMux" 3 161, 3 109, S_0x23dd1f0; + .timescale -9 -12; +L_0x2bd95f0/d .functor NOT 1, L_0x2bd9a20, C4<0>, C4<0>, C4<0>; +L_0x2bd95f0 .delay (10000,10000,10000) L_0x2bd95f0/d; +L_0x2bd9650/d .functor AND 1, L_0x2b3e2f0, L_0x2bd95f0, C4<1>, C4<1>; +L_0x2bd9650 .delay (20000,20000,20000) L_0x2bd9650/d; +L_0x2bd9740/d .functor AND 1, L_0x2bd7f50, L_0x2bd9a20, C4<1>, C4<1>; +L_0x2bd9740 .delay (20000,20000,20000) L_0x2bd9740/d; +L_0x2bd9870/d .functor OR 1, L_0x2bd9650, L_0x2bd9740, C4<0>, C4<0>; +L_0x2bd9870 .delay (20000,20000,20000) L_0x2bd9870/d; +v0x23de180_0 .net "S", 0 0, L_0x2bd9a20; 1 drivers +v0x23e2940_0 .alias "in0", 0 0, v0x23e0e50_0; +v0x23e29c0_0 .alias "in1", 0 0, v0x23e0b20_0; +v0x23e2690_0 .net "nS", 0 0, L_0x2bd95f0; 1 drivers +v0x23e2710_0 .net "out0", 0 0, L_0x2bd9650; 1 drivers +v0x23e23e0_0 .net "out1", 0 0, L_0x2bd9740; 1 drivers +v0x23e2460_0 .alias "outfinal", 0 0, v0x23e0ba0_0; +S_0x23d56a0 .scope generate, "andbits[3]" "andbits[3]" 3 231, 3 231, S_0x2543140; + .timescale -9 -12; +P_0x228d248 .param/l "i" 3 231, +C4<011>; +S_0x23d5410 .scope module, "attempt" "AndNand" 3 233, 3 149, S_0x23d56a0; + .timescale -9 -12; +L_0x2bd9d30/d .functor NAND 1, L_0x2bda610, L_0x2bda700, C4<1>, C4<1>; +L_0x2bd9d30 .delay (10000,10000,10000) L_0x2bd9d30/d; +L_0x2bd9eb0/d .functor NOT 1, L_0x2bd9d30, C4<0>, C4<0>, C4<0>; +L_0x2bd9eb0 .delay (10000,10000,10000) L_0x2bd9eb0/d; +v0x23db280_0 .net "A", 0 0, L_0x2bda610; 1 drivers +v0x23daf70_0 .net "AandB", 0 0, L_0x2bd9eb0; 1 drivers +v0x23daff0_0 .net "AnandB", 0 0, L_0x2bd9d30; 1 drivers +v0x23de390_0 .net "AndNandOut", 0 0, L_0x2bda300; 1 drivers +v0x23de410_0 .net "B", 0 0, L_0x2bda700; 1 drivers +v0x23de100_0 .alias "Command", 2 0, v0x295f7a0_0; +L_0x2bda4d0 .part v0x2960210_0, 0, 1; +S_0x23d8830 .scope module, "potato" "TwoInMux" 3 161, 3 109, S_0x23d5410; + .timescale -9 -12; +L_0x2bd9fe0/d .functor NOT 1, L_0x2bda4d0, C4<0>, C4<0>, C4<0>; +L_0x2bd9fe0 .delay (10000,10000,10000) L_0x2bd9fe0/d; +L_0x2bda0a0/d .functor AND 1, L_0x2bd9eb0, L_0x2bd9fe0, C4<1>, C4<1>; +L_0x2bda0a0 .delay (20000,20000,20000) L_0x2bda0a0/d; +L_0x2bda1b0/d .functor AND 1, L_0x2bd9d30, L_0x2bda4d0, C4<1>, C4<1>; +L_0x2bda1b0 .delay (20000,20000,20000) L_0x2bda1b0/d; +L_0x2bda300/d .functor OR 1, L_0x2bda0a0, L_0x2bda1b0, C4<0>, C4<0>; +L_0x2bda300 .delay (20000,20000,20000) L_0x2bda300/d; +v0x23d85a0_0 .net "S", 0 0, L_0x2bda4d0; 1 drivers +v0x23d8620_0 .alias "in0", 0 0, v0x23daf70_0; +v0x23d7690_0 .alias "in1", 0 0, v0x23daff0_0; +v0x23d7710_0 .net "nS", 0 0, L_0x2bd9fe0; 1 drivers +v0x23d7400_0 .net "out0", 0 0, L_0x2bda0a0; 1 drivers +v0x23d7480_0 .net "out1", 0 0, L_0x2bda1b0; 1 drivers +v0x23db200_0 .alias "outfinal", 0 0, v0x23de390_0; +S_0x23cbf80 .scope generate, "andbits[4]" "andbits[4]" 3 231, 3 231, S_0x2543140; + .timescale -9 -12; +P_0x2283c18 .param/l "i" 3 231, +C4<0100>; +S_0x23cbcf0 .scope module, "attempt" "AndNand" 3 233, 3 149, S_0x23cbf80; + .timescale -9 -12; +L_0x2bda7f0/d .functor NAND 1, L_0x2bdb0d0, L_0x2bdb170, C4<1>, C4<1>; +L_0x2bda7f0 .delay (10000,10000,10000) L_0x2bda7f0/d; +L_0x2bda910/d .functor NOT 1, L_0x2bda7f0, C4<0>, C4<0>, C4<0>; +L_0x2bda910 .delay (10000,10000,10000) L_0x2bda910/d; +v0x23d2a40_0 .net "A", 0 0, L_0x2bdb0d0; 1 drivers +v0x23d2ae0_0 .net "AandB", 0 0, L_0x2bda910; 1 drivers +v0x23d1b30_0 .net "AnandB", 0 0, L_0x2bda7f0; 1 drivers +v0x23d1bb0_0 .net "AndNandOut", 0 0, L_0x2bdad60; 1 drivers +v0x23d18a0_0 .net "B", 0 0, L_0x2bdb170; 1 drivers +v0x23d1920_0 .alias "Command", 2 0, v0x295f7a0_0; +L_0x2bdaf30 .part v0x2960210_0, 0, 1; +S_0x23c9210 .scope module, "potato" "TwoInMux" 3 161, 3 109, S_0x23cbcf0; + .timescale -9 -12; +L_0x2bdaa40/d .functor NOT 1, L_0x2bdaf30, C4<0>, C4<0>, C4<0>; +L_0x2bdaa40 .delay (10000,10000,10000) L_0x2bdaa40/d; +L_0x2bdab00/d .functor AND 1, L_0x2bda910, L_0x2bdaa40, C4<1>, C4<1>; +L_0x2bdab00 .delay (20000,20000,20000) L_0x2bdab00/d; +L_0x2bdac10/d .functor AND 1, L_0x2bda7f0, L_0x2bdaf30, C4<1>, C4<1>; +L_0x2bdac10 .delay (20000,20000,20000) L_0x2bdac10/d; +L_0x2bdad60/d .functor OR 1, L_0x2bdab00, L_0x2bdac10, C4<0>, C4<0>; +L_0x2bdad60 .delay (20000,20000,20000) L_0x2bdad60/d; +v0x23ccca0_0 .net "S", 0 0, L_0x2bdaf30; 1 drivers +v0x23cfb40_0 .alias "in0", 0 0, v0x23d2ae0_0; +v0x23cfbc0_0 .alias "in1", 0 0, v0x23d1b30_0; +v0x23cf8b0_0 .net "nS", 0 0, L_0x2bdaa40; 1 drivers +v0x23cf930_0 .net "out0", 0 0, L_0x2bdab00; 1 drivers +v0x23d2cd0_0 .net "out1", 0 0, L_0x2bdac10; 1 drivers +v0x23d2d50_0 .alias "outfinal", 0 0, v0x23d1bb0_0; +S_0x23cba60 .scope generate, "andbits[5]" "andbits[5]" 3 231, 3 231, S_0x2543140; + .timescale -9 -12; +P_0x22646e8 .param/l "i" 3 231, +C4<0101>; +S_0x23cb7d0 .scope module, "attempt" "AndNand" 3 233, 3 149, S_0x23cba60; + .timescale -9 -12; +L_0x2bdb070/d .functor NAND 1, L_0x2bdbb00, L_0x2bdbc20, C4<1>, C4<1>; +L_0x2bdb070 .delay (10000,10000,10000) L_0x2bdb070/d; +L_0x2bdb3a0/d .functor NOT 1, L_0x2bdb070, C4<0>, C4<0>, C4<0>; +L_0x2bdb3a0 .delay (10000,10000,10000) L_0x2bdb3a0/d; +v0x23c9810_0 .net "A", 0 0, L_0x2bdbb00; 1 drivers +v0x23cd170_0 .net "AandB", 0 0, L_0x2bdb3a0; 1 drivers +v0x23cd1f0_0 .net "AnandB", 0 0, L_0x2bdb070; 1 drivers +v0x23ccee0_0 .net "AndNandOut", 0 0, L_0x2bdb7f0; 1 drivers +v0x23ccf60_0 .net "B", 0 0, L_0x2bdbc20; 1 drivers +v0x23ccc20_0 .alias "Command", 2 0, v0x295f7a0_0; +L_0x2bdb9c0 .part v0x2960210_0, 0, 1; +S_0x23cb250 .scope module, "potato" "TwoInMux" 3 161, 3 109, S_0x23cb7d0; + .timescale -9 -12; +L_0x2bdb4d0/d .functor NOT 1, L_0x2bdb9c0, C4<0>, C4<0>, C4<0>; +L_0x2bdb4d0 .delay (10000,10000,10000) L_0x2bdb4d0/d; +L_0x2bdb590/d .functor AND 1, L_0x2bdb3a0, L_0x2bdb4d0, C4<1>, C4<1>; +L_0x2bdb590 .delay (20000,20000,20000) L_0x2bdb590/d; +L_0x2bdb6a0/d .functor AND 1, L_0x2bdb070, L_0x2bdb9c0, C4<1>, C4<1>; +L_0x2bdb6a0 .delay (20000,20000,20000) L_0x2bdb6a0/d; +L_0x2bdb7f0/d .functor OR 1, L_0x2bdb590, L_0x2bdb6a0, C4<0>, C4<0>; +L_0x2bdb7f0 .delay (20000,20000,20000) L_0x2bdb7f0/d; +v0x23c9f40_0 .net "S", 0 0, L_0x2bdb9c0; 1 drivers +v0x23c9fc0_0 .alias "in0", 0 0, v0x23cd170_0; +v0x23c9cb0_0 .alias "in1", 0 0, v0x23cd1f0_0; +v0x23c9d30_0 .net "nS", 0 0, L_0x2bdb4d0; 1 drivers +v0x23c9a20_0 .net "out0", 0 0, L_0x2bdb590; 1 drivers +v0x23c9aa0_0 .net "out1", 0 0, L_0x2bdb6a0; 1 drivers +v0x23c9790_0 .alias "outfinal", 0 0, v0x23ccee0_0; +S_0x23c4060 .scope generate, "andbits[6]" "andbits[6]" 3 231, 3 231, S_0x2543140; + .timescale -9 -12; +P_0x2269238 .param/l "i" 3 231, +C4<0110>; +S_0x23c3dd0 .scope module, "attempt" "AndNand" 3 233, 3 149, S_0x23c4060; + .timescale -9 -12; +L_0x2bdbd10/d .functor NAND 1, L_0x2bdc660, L_0x2bdc700, C4<1>, C4<1>; +L_0x2bdbd10 .delay (10000,10000,10000) L_0x2bdbd10/d; +L_0x2bdbe70/d .functor NOT 1, L_0x2bdbd10, C4<0>, C4<0>, C4<0>; +L_0x2bdbe70 .delay (10000,10000,10000) L_0x2bdbe70/d; +v0x23c6330_0 .net "A", 0 0, L_0x2bdc660; 1 drivers +v0x23c63d0_0 .net "AandB", 0 0, L_0x2bdbe70; 1 drivers +v0x23c60a0_0 .net "AnandB", 0 0, L_0x2bdbd10; 1 drivers +v0x23c6120_0 .net "AndNandOut", 0 0, L_0x2bdc2c0; 1 drivers +v0x23c35c0_0 .net "B", 0 0, L_0x2bdc700; 1 drivers +v0x23c3640_0 .alias "Command", 2 0, v0x295f7a0_0; +L_0x2bdc490 .part v0x2960210_0, 0, 1; +S_0x23c3b40 .scope module, "potato" "TwoInMux" 3 161, 3 109, S_0x23c3dd0; + .timescale -9 -12; +L_0x2bdbfa0/d .functor NOT 1, L_0x2bdc490, C4<0>, C4<0>, C4<0>; +L_0x2bdbfa0 .delay (10000,10000,10000) L_0x2bdbfa0/d; +L_0x2bdc060/d .functor AND 1, L_0x2bdbe70, L_0x2bdbfa0, C4<1>, C4<1>; +L_0x2bdc060 .delay (20000,20000,20000) L_0x2bdc060/d; +L_0x2bdc170/d .functor AND 1, L_0x2bdbd10, L_0x2bdc490, C4<1>, C4<1>; +L_0x2bdc170 .delay (20000,20000,20000) L_0x2bdc170/d; +L_0x2bdc2c0/d .functor OR 1, L_0x2bdc060, L_0x2bdc170, C4<0>, C4<0>; +L_0x2bdc2c0 .delay (20000,20000,20000) L_0x2bdc2c0/d; +v0x23c4370_0 .net "S", 0 0, L_0x2bdc490; 1 drivers +v0x23c7520_0 .alias "in0", 0 0, v0x23c63d0_0; +v0x23c75a0_0 .alias "in1", 0 0, v0x23c60a0_0; +v0x23c7290_0 .net "nS", 0 0, L_0x2bdbfa0; 1 drivers +v0x23c7310_0 .net "out0", 0 0, L_0x2bdc060; 1 drivers +v0x23c6fd0_0 .net "out1", 0 0, L_0x2bdc170; 1 drivers +v0x23c7050_0 .alias "outfinal", 0 0, v0x23c6120_0; +S_0x23c1640 .scope generate, "andbits[7]" "andbits[7]" 3 231, 3 231, S_0x2543140; + .timescale -9 -12; +P_0x2270968 .param/l "i" 3 231, +C4<0111>; +S_0x23c1380 .scope module, "attempt" "AndNand" 3 233, 3 149, S_0x23c1640; + .timescale -9 -12; +L_0x2bdc5d0/d .functor NAND 1, L_0x2bdd0f0, L_0x2bdc7f0, C4<1>, C4<1>; +L_0x2bdc5d0 .delay (10000,10000,10000) L_0x2bdc5d0/d; +L_0x2bdc990/d .functor NOT 1, L_0x2bdc5d0, C4<0>, C4<0>, C4<0>; +L_0x2bdc990 .delay (10000,10000,10000) L_0x2bdc990/d; +v0x23c5e90_0 .net "A", 0 0, L_0x2bdd0f0; 1 drivers +v0x23c5b80_0 .net "AandB", 0 0, L_0x2bdc990; 1 drivers +v0x23c5c00_0 .net "AnandB", 0 0, L_0x2bdc5d0; 1 drivers +v0x23c5600_0 .net "AndNandOut", 0 0, L_0x2bdcde0; 1 drivers +v0x23c5680_0 .net "B", 0 0, L_0x2bdc7f0; 1 drivers +v0x23c42f0_0 .alias "Command", 2 0, v0x295f7a0_0; +L_0x2bdcfb0 .part v0x2960210_0, 0, 1; +S_0x23c06e0 .scope module, "potato" "TwoInMux" 3 161, 3 109, S_0x23c1380; + .timescale -9 -12; +L_0x2bdcac0/d .functor NOT 1, L_0x2bdcfb0, C4<0>, C4<0>, C4<0>; +L_0x2bdcac0 .delay (10000,10000,10000) L_0x2bdcac0/d; +L_0x2bdcb80/d .functor AND 1, L_0x2bdc990, L_0x2bdcac0, C4<1>, C4<1>; +L_0x2bdcb80 .delay (20000,20000,20000) L_0x2bdcb80/d; +L_0x2bdcc90/d .functor AND 1, L_0x2bdc5d0, L_0x2bdcfb0, C4<1>, C4<1>; +L_0x2bdcc90 .delay (20000,20000,20000) L_0x2bdcc90/d; +L_0x2bdcde0/d .functor OR 1, L_0x2bdcb80, L_0x2bdcc90, C4<0>, C4<0>; +L_0x2bdcde0 .delay (20000,20000,20000) L_0x2bdcde0/d; +v0x23c0450_0 .net "S", 0 0, L_0x2bdcfb0; 1 drivers +v0x23c04d0_0 .alias "in0", 0 0, v0x23c5b80_0; +v0x23bdc60_0 .alias "in1", 0 0, v0x23c5c00_0; +v0x23bdce0_0 .net "nS", 0 0, L_0x2bdcac0; 1 drivers +v0x23bd9e0_0 .net "out0", 0 0, L_0x2bdcb80; 1 drivers +v0x23bda60_0 .net "out1", 0 0, L_0x2bdcc90; 1 drivers +v0x23c5e10_0 .alias "outfinal", 0 0, v0x23c5600_0; +S_0x23ba8a0 .scope generate, "andbits[8]" "andbits[8]" 3 231, 3 231, S_0x2543140; + .timescale -9 -12; +P_0x227e5e8 .param/l "i" 3 231, +C4<01000>; +S_0x23c01c0 .scope module, "attempt" "AndNand" 3 233, 3 149, S_0x23ba8a0; + .timescale -9 -12; +L_0x2bdd290/d .functor NAND 1, L_0x2bdd190, L_0x2bddc10, C4<1>, C4<1>; +L_0x2bdd290 .delay (10000,10000,10000) L_0x2bdd290/d; +L_0x2bdd3f0/d .functor NOT 1, L_0x2bdd290, C4<0>, C4<0>, C4<0>; +L_0x2bdd3f0 .delay (10000,10000,10000) L_0x2bdd3f0/d; +v0x23be180_0 .net "A", 0 0, L_0x2bdd190; 1 drivers +v0x23be220_0 .net "AandB", 0 0, L_0x2bdd3f0; 1 drivers +v0x23bdef0_0 .net "AnandB", 0 0, L_0x2bdd290; 1 drivers +v0x23bdf70_0 .net "AndNandOut", 0 0, L_0x2bdd840; 1 drivers +v0x23c18d0_0 .net "B", 0 0, L_0x2bddc10; 1 drivers +v0x23c1950_0 .alias "Command", 2 0, v0x295f7a0_0; +L_0x2bdda10 .part v0x2960210_0, 0, 1; +S_0x23bff30 .scope module, "potato" "TwoInMux" 3 161, 3 109, S_0x23c01c0; + .timescale -9 -12; +L_0x2bdd520/d .functor NOT 1, L_0x2bdda10, C4<0>, C4<0>, C4<0>; +L_0x2bdd520 .delay (10000,10000,10000) L_0x2bdd520/d; +L_0x2bdd5e0/d .functor AND 1, L_0x2bdd3f0, L_0x2bdd520, C4<1>, C4<1>; +L_0x2bdd5e0 .delay (20000,20000,20000) L_0x2bdd5e0/d; +L_0x2bdd6f0/d .functor AND 1, L_0x2bdd290, L_0x2bdda10, C4<1>, C4<1>; +L_0x2bdd6f0 .delay (20000,20000,20000) L_0x2bdd6f0/d; +L_0x2bdd840/d .functor OR 1, L_0x2bdd5e0, L_0x2bdd6f0, C4<0>, C4<0>; +L_0x2bdd840 .delay (20000,20000,20000) L_0x2bdd840/d; +v0x23babb0_0 .net "S", 0 0, L_0x2bdda10; 1 drivers +v0x23bf9b0_0 .alias "in0", 0 0, v0x23be220_0; +v0x23bfa30_0 .alias "in1", 0 0, v0x23bdef0_0; +v0x23be6a0_0 .net "nS", 0 0, L_0x2bdd520; 1 drivers +v0x23be720_0 .net "out0", 0 0, L_0x2bdd5e0; 1 drivers +v0x23be410_0 .net "out1", 0 0, L_0x2bdd6f0; 1 drivers +v0x23be490_0 .alias "outfinal", 0 0, v0x23bdf70_0; +S_0x23b2d50 .scope generate, "andbits[9]" "andbits[9]" 3 231, 3 231, S_0x2543140; + .timescale -9 -12; +P_0x2283138 .param/l "i" 3 231, +C4<01001>; +S_0x23b6170 .scope module, "attempt" "AndNand" 3 233, 3 149, S_0x23b2d50; + .timescale -9 -12; +L_0x2bddb50/d .functor NAND 1, L_0x2bde5f0, L_0x2bddd00, C4<1>, C4<1>; +L_0x2bddb50 .delay (10000,10000,10000) L_0x2bddb50/d; +L_0x2bdde90/d .functor NOT 1, L_0x2bddb50, C4<0>, C4<0>, C4<0>; +L_0x2bdde90 .delay (10000,10000,10000) L_0x2bdde90/d; +v0x23b8930_0 .net "A", 0 0, L_0x2bde5f0; 1 drivers +v0x23bbcd0_0 .net "AandB", 0 0, L_0x2bdde90; 1 drivers +v0x23bbd50_0 .net "AnandB", 0 0, L_0x2bddb50; 1 drivers +v0x23bba40_0 .net "AndNandOut", 0 0, L_0x2bde2e0; 1 drivers +v0x23bbac0_0 .net "B", 0 0, L_0x2bddd00; 1 drivers +v0x23bab30_0 .alias "Command", 2 0, v0x295f7a0_0; +L_0x2bde4b0 .part v0x2960210_0, 0, 1; +S_0x23b5ee0 .scope module, "potato" "TwoInMux" 3 161, 3 109, S_0x23b6170; + .timescale -9 -12; +L_0x2bddfc0/d .functor NOT 1, L_0x2bde4b0, C4<0>, C4<0>, C4<0>; +L_0x2bddfc0 .delay (10000,10000,10000) L_0x2bddfc0/d; +L_0x2bde080/d .functor AND 1, L_0x2bdde90, L_0x2bddfc0, C4<1>, C4<1>; +L_0x2bde080 .delay (20000,20000,20000) L_0x2bde080/d; +L_0x2bde190/d .functor AND 1, L_0x2bddb50, L_0x2bde4b0, C4<1>, C4<1>; +L_0x2bde190 .delay (20000,20000,20000) L_0x2bde190/d; +L_0x2bde2e0/d .functor OR 1, L_0x2bde080, L_0x2bde190, C4<0>, C4<0>; +L_0x2bde2e0 .delay (20000,20000,20000) L_0x2bde2e0/d; +v0x23b4fd0_0 .net "S", 0 0, L_0x2bde4b0; 1 drivers +v0x23b5050_0 .alias "in0", 0 0, v0x23bbcd0_0; +v0x23b4d40_0 .alias "in1", 0 0, v0x23bbd50_0; +v0x23b4dc0_0 .net "nS", 0 0, L_0x2bddfc0; 1 drivers +v0x23b8b40_0 .net "out0", 0 0, L_0x2bde080; 1 drivers +v0x23b8bc0_0 .net "out1", 0 0, L_0x2bde190; 1 drivers +v0x23b88b0_0 .alias "outfinal", 0 0, v0x23bba40_0; +S_0x23ad1d0 .scope generate, "andbits[10]" "andbits[10]" 3 231, 3 231, S_0x2543140; + .timescale -9 -12; +P_0x2287c88 .param/l "i" 3 231, +C4<01010>; +S_0x23acf40 .scope module, "attempt" "AndNand" 3 233, 3 149, S_0x23ad1d0; + .timescale -9 -12; +L_0x2bde7c0/d .functor NAND 1, L_0x2bde690, L_0x2bdf150, C4<1>, C4<1>; +L_0x2bde7c0 .delay (10000,10000,10000) L_0x2bde7c0/d; +L_0x2bde900/d .functor NOT 1, L_0x2bde7c0, C4<0>, C4<0>, C4<0>; +L_0x2bde900 .delay (10000,10000,10000) L_0x2bde900/d; +v0x23af1e0_0 .net "A", 0 0, L_0x2bde690; 1 drivers +v0x23af280_0 .net "AandB", 0 0, L_0x2bde900; 1 drivers +v0x23ac730_0 .net "AnandB", 0 0, L_0x2bde7c0; 1 drivers +v0x23ac7b0_0 .net "AndNandOut", 0 0, L_0x2bded50; 1 drivers +v0x23b2fe0_0 .net "B", 0 0, L_0x2bdf150; 1 drivers +v0x23b3060_0 .alias "Command", 2 0, v0x295f7a0_0; +L_0x2bdef20 .part v0x2960210_0, 0, 1; +S_0x23accb0 .scope module, "potato" "TwoInMux" 3 161, 3 109, S_0x23acf40; + .timescale -9 -12; +L_0x2bdea30/d .functor NOT 1, L_0x2bdef20, C4<0>, C4<0>, C4<0>; +L_0x2bdea30 .delay (10000,10000,10000) L_0x2bdea30/d; +L_0x2bdeaf0/d .functor AND 1, L_0x2bde900, L_0x2bdea30, C4<1>, C4<1>; +L_0x2bdeaf0 .delay (20000,20000,20000) L_0x2bdeaf0/d; +L_0x2bdec00/d .functor AND 1, L_0x2bde7c0, L_0x2bdef20, C4<1>, C4<1>; +L_0x2bdec00 .delay (20000,20000,20000) L_0x2bdec00/d; +L_0x2bded50/d .functor OR 1, L_0x2bdeaf0, L_0x2bdec00, C4<0>, C4<0>; +L_0x2bded50 .delay (20000,20000,20000) L_0x2bded50/d; +v0x23ad4e0_0 .net "S", 0 0, L_0x2bdef20; 1 drivers +v0x23b0610_0 .alias "in0", 0 0, v0x23af280_0; +v0x23b0690_0 .alias "in1", 0 0, v0x23ac730_0; +v0x23b0380_0 .net "nS", 0 0, L_0x2bdea30; 1 drivers +v0x23b0400_0 .net "out0", 0 0, L_0x2bdeaf0; 1 drivers +v0x23af470_0 .net "out1", 0 0, L_0x2bdec00; 1 drivers +v0x23af4f0_0 .alias "outfinal", 0 0, v0x23ac7b0_0; +S_0x23a7580 .scope generate, "andbits[11]" "andbits[11]" 3 231, 3 231, S_0x2543140; + .timescale -9 -12; +P_0x2295e48 .param/l "i" 3 231, +C4<01011>; +S_0x23a72f0 .scope module, "attempt" "AndNand" 3 233, 3 149, S_0x23a7580; + .timescale -9 -12; +L_0x2bdf060/d .functor NAND 1, L_0x2bdfaf0, L_0x2bdf240, C4<1>, C4<1>; +L_0x2bdf060 .delay (10000,10000,10000) L_0x2bdf060/d; +L_0x2bdf390/d .functor NOT 1, L_0x2bdf060, C4<0>, C4<0>, C4<0>; +L_0x2bdf390 .delay (10000,10000,10000) L_0x2bdf390/d; +v0x23a98d0_0 .net "A", 0 0, L_0x2bdfaf0; 1 drivers +v0x23a95c0_0 .net "AandB", 0 0, L_0x2bdf390; 1 drivers +v0x23a9640_0 .net "AnandB", 0 0, L_0x2bdf060; 1 drivers +v0x23a6ae0_0 .net "AndNandOut", 0 0, L_0x2bdf7e0; 1 drivers +v0x23a6b60_0 .net "B", 0 0, L_0x2bdf240; 1 drivers +v0x23ad460_0 .alias "Command", 2 0, v0x295f7a0_0; +L_0x2bdf9b0 .part v0x2960210_0, 0, 1; +S_0x23a7060 .scope module, "potato" "TwoInMux" 3 161, 3 109, S_0x23a72f0; + .timescale -9 -12; +L_0x2bdf4c0/d .functor NOT 1, L_0x2bdf9b0, C4<0>, C4<0>, C4<0>; +L_0x2bdf4c0 .delay (10000,10000,10000) L_0x2bdf4c0/d; +L_0x2bdf580/d .functor AND 1, L_0x2bdf390, L_0x2bdf4c0, C4<1>, C4<1>; +L_0x2bdf580 .delay (20000,20000,20000) L_0x2bdf580/d; +L_0x2bdf690/d .functor AND 1, L_0x2bdf060, L_0x2bdf9b0, C4<1>, C4<1>; +L_0x2bdf690 .delay (20000,20000,20000) L_0x2bdf690/d; +L_0x2bdf7e0/d .functor OR 1, L_0x2bdf580, L_0x2bdf690, C4<0>, C4<0>; +L_0x2bdf7e0 .delay (20000,20000,20000) L_0x2bdf7e0/d; +v0x23aaa40_0 .net "S", 0 0, L_0x2bdf9b0; 1 drivers +v0x23aaac0_0 .alias "in0", 0 0, v0x23a95c0_0; +v0x23aa7b0_0 .alias "in1", 0 0, v0x23a9640_0; +v0x23aa830_0 .net "nS", 0 0, L_0x2bdf4c0; 1 drivers +v0x23aa4f0_0 .net "out0", 0 0, L_0x2bdf580; 1 drivers +v0x23aa570_0 .net "out1", 0 0, L_0x2bdf690; 1 drivers +v0x23a9850_0 .alias "outfinal", 0 0, v0x23a6ae0_0; +S_0x23a4b60 .scope generate, "andbits[12]" "andbits[12]" 3 231, 3 231, S_0x2543140; + .timescale -9 -12; +P_0x229ee28 .param/l "i" 3 231, +C4<01100>; +S_0x23a48a0 .scope module, "attempt" "AndNand" 3 233, 3 149, S_0x23a4b60; + .timescale -9 -12; +L_0x2bdfca0/d .functor NAND 1, L_0x2bdfb90, L_0x2be0680, C4<1>, C4<1>; +L_0x2bdfca0 .delay (10000,10000,10000) L_0x2bdfca0/d; +L_0x2bdfe00/d .functor NOT 1, L_0x2bdfca0, C4<0>, C4<0>, C4<0>; +L_0x2bdfe00 .delay (10000,10000,10000) L_0x2bdfe00/d; +v0x23a90a0_0 .net "A", 0 0, L_0x2bdfb90; 1 drivers +v0x23a9140_0 .net "AandB", 0 0, L_0x2bdfe00; 1 drivers +v0x23a8b20_0 .net "AnandB", 0 0, L_0x2bdfca0; 1 drivers +v0x23a8ba0_0 .net "AndNandOut", 0 0, L_0x2be0250; 1 drivers +v0x23a7810_0 .net "B", 0 0, L_0x2be0680; 1 drivers +v0x23a7890_0 .alias "Command", 2 0, v0x295f7a0_0; +L_0x2be0420 .part v0x2960210_0, 0, 1; +S_0x23a3c00 .scope module, "potato" "TwoInMux" 3 161, 3 109, S_0x23a48a0; + .timescale -9 -12; +L_0x2bdff30/d .functor NOT 1, L_0x2be0420, C4<0>, C4<0>, C4<0>; +L_0x2bdff30 .delay (10000,10000,10000) L_0x2bdff30/d; +L_0x2bdfff0/d .functor AND 1, L_0x2bdfe00, L_0x2bdff30, C4<1>, C4<1>; +L_0x2bdfff0 .delay (20000,20000,20000) L_0x2bdfff0/d; +L_0x2be0100/d .functor AND 1, L_0x2bdfca0, L_0x2be0420, C4<1>, C4<1>; +L_0x2be0100 .delay (20000,20000,20000) L_0x2be0100/d; +L_0x2be0250/d .functor OR 1, L_0x2bdfff0, L_0x2be0100, C4<0>, C4<0>; +L_0x2be0250 .delay (20000,20000,20000) L_0x2be0250/d; +v0x23a4e70_0 .net "S", 0 0, L_0x2be0420; 1 drivers +v0x23a3970_0 .alias "in0", 0 0, v0x23a9140_0; +v0x23a39f0_0 .alias "in1", 0 0, v0x23a8b20_0; +v0x23a0e90_0 .net "nS", 0 0, L_0x2bdff30; 1 drivers +v0x23a0f10_0 .net "out0", 0 0, L_0x2bdfff0; 1 drivers +v0x23a9330_0 .net "out1", 0 0, L_0x2be0100; 1 drivers +v0x23a93b0_0 .alias "outfinal", 0 0, v0x23a8ba0_0; +S_0x239dfb0 .scope generate, "andbits[13]" "andbits[13]" 3 231, 3 231, S_0x2543140; + .timescale -9 -12; +P_0x22a3978 .param/l "i" 3 231, +C4<01101>; +S_0x239dd20 .scope module, "attempt" "AndNand" 3 233, 3 149, S_0x239dfb0; + .timescale -9 -12; +L_0x2be0560/d .functor NAND 1, L_0x2be1000, L_0x2be0720, C4<1>, C4<1>; +L_0x2be0560 .delay (10000,10000,10000) L_0x2be0560/d; +L_0x2be08a0/d .functor NOT 1, L_0x2be0560, C4<0>, C4<0>, C4<0>; +L_0x2be08a0 .delay (10000,10000,10000) L_0x2be08a0/d; +v0x23a19b0_0 .net "A", 0 0, L_0x2be1000; 1 drivers +v0x23a16a0_0 .net "AandB", 0 0, L_0x2be08a0; 1 drivers +v0x23a1720_0 .net "AnandB", 0 0, L_0x2be0560; 1 drivers +v0x23a1410_0 .net "AndNandOut", 0 0, L_0x2be0cf0; 1 drivers +v0x23a1490_0 .net "B", 0 0, L_0x2be0720; 1 drivers +v0x23a4df0_0 .alias "Command", 2 0, v0x295f7a0_0; +L_0x2be0ec0 .part v0x2960210_0, 0, 1; +S_0x23a36e0 .scope module, "potato" "TwoInMux" 3 161, 3 109, S_0x239dd20; + .timescale -9 -12; +L_0x2be09d0/d .functor NOT 1, L_0x2be0ec0, C4<0>, C4<0>, C4<0>; +L_0x2be09d0 .delay (10000,10000,10000) L_0x2be09d0/d; +L_0x2be0a90/d .functor AND 1, L_0x2be08a0, L_0x2be09d0, C4<1>, C4<1>; +L_0x2be0a90 .delay (20000,20000,20000) L_0x2be0a90/d; +L_0x2be0ba0/d .functor AND 1, L_0x2be0560, L_0x2be0ec0, C4<1>, C4<1>; +L_0x2be0ba0 .delay (20000,20000,20000) L_0x2be0ba0/d; +L_0x2be0cf0/d .functor OR 1, L_0x2be0a90, L_0x2be0ba0, C4<0>, C4<0>; +L_0x2be0cf0 .delay (20000,20000,20000) L_0x2be0cf0/d; +v0x23a3450_0 .net "S", 0 0, L_0x2be0ec0; 1 drivers +v0x23a34d0_0 .alias "in0", 0 0, v0x23a16a0_0; +v0x23a2ed0_0 .alias "in1", 0 0, v0x23a1720_0; +v0x23a2f50_0 .net "nS", 0 0, L_0x2be09d0; 1 drivers +v0x23a1bc0_0 .net "out0", 0 0, L_0x2be0a90; 1 drivers +v0x23a1c40_0 .net "out1", 0 0, L_0x2be0ba0; 1 drivers +v0x23a1930_0 .alias "outfinal", 0 0, v0x23a1410_0; +S_0x2399360 .scope generate, "andbits[14]" "andbits[14]" 3 231, 3 231, S_0x2543140; + .timescale -9 -12; +P_0x22a84c8 .param/l "i" 3 231, +C4<01110>; +S_0x2398450 .scope module, "attempt" "AndNand" 3 233, 3 149, S_0x2399360; + .timescale -9 -12; +L_0x2be11e0/d .functor NAND 1, L_0x2be10a0, L_0x2be1140, C4<1>, C4<1>; +L_0x2be11e0 .delay (10000,10000,10000) L_0x2be11e0/d; +L_0x2be1320/d .functor NOT 1, L_0x2be11e0, C4<0>, C4<0>, C4<0>; +L_0x2be1320 .delay (10000,10000,10000) L_0x2be1320/d; +v0x239f1a0_0 .net "A", 0 0, L_0x2be10a0; 1 drivers +v0x239f240_0 .net "AandB", 0 0, L_0x2be1320; 1 drivers +v0x239ef10_0 .net "AnandB", 0 0, L_0x2be11e0; 1 drivers +v0x239ef90_0 .net "AndNandOut", 0 0, L_0x2be1750; 1 drivers +v0x239ec50_0 .net "B", 0 0, L_0x2be1140; 1 drivers +v0x239ecd0_0 .alias "Command", 2 0, v0x295f7a0_0; +L_0x2be1920 .part v0x2960210_0, 0, 1; +S_0x23981c0 .scope module, "potato" "TwoInMux" 3 161, 3 109, S_0x2398450; + .timescale -9 -12; +L_0x2be1430/d .functor NOT 1, L_0x2be1920, C4<0>, C4<0>, C4<0>; +L_0x2be1430 .delay (10000,10000,10000) L_0x2be1430/d; +L_0x2be14f0/d .functor AND 1, L_0x2be1320, L_0x2be1430, C4<1>, C4<1>; +L_0x2be14f0 .delay (20000,20000,20000) L_0x2be14f0/d; +L_0x2be1600/d .functor AND 1, L_0x2be11e0, L_0x2be1920, C4<1>, C4<1>; +L_0x2be1600 .delay (20000,20000,20000) L_0x2be1600/d; +L_0x2be1750/d .functor OR 1, L_0x2be14f0, L_0x2be1600, C4<0>, C4<0>; +L_0x2be1750 .delay (20000,20000,20000) L_0x2be1750/d; +v0x2399670_0 .net "S", 0 0, L_0x2be1920; 1 drivers +v0x239da90_0 .alias "in0", 0 0, v0x239f240_0; +v0x239db10_0 .alias "in1", 0 0, v0x239ef10_0; +v0x239bfc0_0 .net "nS", 0 0, L_0x2be1430; 1 drivers +v0x239c040_0 .net "out0", 0 0, L_0x2be14f0; 1 drivers +v0x239bd30_0 .net "out1", 0 0, L_0x2be1600; 1 drivers +v0x239bdb0_0 .alias "outfinal", 0 0, v0x239ef90_0; +S_0x2389fd0 .scope generate, "andbits[15]" "andbits[15]" 3 231, 3 231, S_0x2543140; + .timescale -9 -12; +P_0x22bce48 .param/l "i" 3 231, +C4<01111>; +S_0x2390900 .scope module, "attempt" "AndNand" 3 233, 3 149, S_0x2389fd0; + .timescale -9 -12; +L_0x2be1a60/d .functor NAND 1, L_0x2be24f0, L_0x2be1c00, C4<1>, C4<1>; +L_0x2be1a60 .delay (10000,10000,10000) L_0x2be1a60/d; +L_0x2be1db0/d .functor NOT 1, L_0x2be1a60, C4<0>, C4<0>, C4<0>; +L_0x2be1db0 .delay (10000,10000,10000) L_0x2be1db0/d; +v0x23926e0_0 .net "A", 0 0, L_0x2be24f0; 1 drivers +v0x2396460_0 .net "AandB", 0 0, L_0x2be1db0; 1 drivers +v0x23964e0_0 .net "AnandB", 0 0, L_0x2be1a60; 1 drivers +v0x23961d0_0 .net "AndNandOut", 0 0, L_0x2be21e0; 1 drivers +v0x2396250_0 .net "B", 0 0, L_0x2be1c00; 1 drivers +v0x23995f0_0 .alias "Command", 2 0, v0x295f7a0_0; +L_0x2be23b0 .part v0x2960210_0, 0, 1; +S_0x2390670 .scope module, "potato" "TwoInMux" 3 161, 3 109, S_0x2390900; + .timescale -9 -12; +L_0x2be1ec0/d .functor NOT 1, L_0x2be23b0, C4<0>, C4<0>, C4<0>; +L_0x2be1ec0 .delay (10000,10000,10000) L_0x2be1ec0/d; +L_0x2be1f80/d .functor AND 1, L_0x2be1db0, L_0x2be1ec0, C4<1>, C4<1>; +L_0x2be1f80 .delay (20000,20000,20000) L_0x2be1f80/d; +L_0x2be2090/d .functor AND 1, L_0x2be1a60, L_0x2be23b0, C4<1>, C4<1>; +L_0x2be2090 .delay (20000,20000,20000) L_0x2be2090/d; +L_0x2be21e0/d .functor OR 1, L_0x2be1f80, L_0x2be2090, C4<0>, C4<0>; +L_0x2be21e0 .delay (20000,20000,20000) L_0x2be21e0/d; +v0x2393a90_0 .net "S", 0 0, L_0x2be23b0; 1 drivers +v0x2393b10_0 .alias "in0", 0 0, v0x2396460_0; +v0x2393800_0 .alias "in1", 0 0, v0x23964e0_0; +v0x2393880_0 .net "nS", 0 0, L_0x2be1ec0; 1 drivers +v0x23928f0_0 .net "out0", 0 0, L_0x2be1f80; 1 drivers +v0x2392970_0 .net "out1", 0 0, L_0x2be2090; 1 drivers +v0x2392660_0 .alias "outfinal", 0 0, v0x23961d0_0; +S_0x238ad00 .scope generate, "andbits[16]" "andbits[16]" 3 231, 3 231, S_0x2543140; + .timescale -9 -12; +P_0x22c6738 .param/l "i" 3 231, +C4<010000>; +S_0x238aa70 .scope module, "attempt" "AndNand" 3 233, 3 149, S_0x238ad00; + .timescale -9 -12; +L_0x2be1cf0/d .functor NAND 1, L_0x2be2590, L_0x2be2630, C4<1>, C4<1>; +L_0x2be1cf0 .delay (10000,10000,10000) L_0x2be1cf0/d; +L_0x2be2800/d .functor NOT 1, L_0x2be1cf0, C4<0>, C4<0>, C4<0>; +L_0x2be2800 .delay (10000,10000,10000) L_0x2be2800/d; +v0x238d9e0_0 .net "A", 0 0, L_0x2be2590; 1 drivers +v0x238da80_0 .net "AandB", 0 0, L_0x2be2800; 1 drivers +v0x238cd40_0 .net "AnandB", 0 0, L_0x2be1cf0; 1 drivers +v0x238cdc0_0 .net "AndNandOut", 0 0, L_0x2be2c50; 1 drivers +v0x238cab0_0 .net "B", 0 0, L_0x2be2630; 1 drivers +v0x238cb30_0 .alias "Command", 2 0, v0x295f7a0_0; +L_0x2be2e20 .part v0x2960210_0, 0, 1; +S_0x238a7e0 .scope module, "potato" "TwoInMux" 3 161, 3 109, S_0x238aa70; + .timescale -9 -12; +L_0x2be2930/d .functor NOT 1, L_0x2be2e20, C4<0>, C4<0>, C4<0>; +L_0x2be2930 .delay (10000,10000,10000) L_0x2be2930/d; +L_0x2be29f0/d .functor AND 1, L_0x2be2800, L_0x2be2930, C4<1>, C4<1>; +L_0x2be29f0 .delay (20000,20000,20000) L_0x2be29f0/d; +L_0x2be2b00/d .functor AND 1, L_0x2be1cf0, L_0x2be2e20, C4<1>, C4<1>; +L_0x2be2b00 .delay (20000,20000,20000) L_0x2be2b00/d; +L_0x2be2c50/d .functor OR 1, L_0x2be29f0, L_0x2be2b00, C4<0>, C4<0>; +L_0x2be2c50 .delay (20000,20000,20000) L_0x2be2c50/d; +v0x238c090_0 .net "S", 0 0, L_0x2be2e20; 1 drivers +v0x238a550_0 .alias "in0", 0 0, v0x238da80_0; +v0x238a5d0_0 .alias "in1", 0 0, v0x238cd40_0; +v0x238df30_0 .net "nS", 0 0, L_0x2be2930; 1 drivers +v0x238dfb0_0 .net "out0", 0 0, L_0x2be29f0; 1 drivers +v0x238dca0_0 .net "out1", 0 0, L_0x2be2b00; 1 drivers +v0x238dd20_0 .alias "outfinal", 0 0, v0x238cdc0_0; +S_0x2384900 .scope generate, "andbits[17]" "andbits[17]" 3 231, 3 231, S_0x2543140; + .timescale -9 -12; +P_0x22cb288 .param/l "i" 3 231, +C4<010001>; +S_0x23882e0 .scope module, "attempt" "AndNand" 3 233, 3 149, S_0x2384900; + .timescale -9 -12; +L_0x2be2f60/d .functor NAND 1, L_0x2be3a00, L_0x2be3130, C4<1>, C4<1>; +L_0x2be2f60 .delay (10000,10000,10000) L_0x2be2f60/d; +L_0x2be32c0/d .functor NOT 1, L_0x2be2f60, C4<0>, C4<0>, C4<0>; +L_0x2be32c0 .delay (10000,10000,10000) L_0x2be32c0/d; +v0x2384400_0 .net "A", 0 0, L_0x2be3a00; 1 drivers +v0x238c820_0 .net "AandB", 0 0, L_0x2be32c0; 1 drivers +v0x238c8a0_0 .net "AnandB", 0 0, L_0x2be2f60; 1 drivers +v0x238c590_0 .net "AndNandOut", 0 0, L_0x2be36f0; 1 drivers +v0x238c610_0 .net "B", 0 0, L_0x2be3130; 1 drivers +v0x238c010_0 .alias "Command", 2 0, v0x295f7a0_0; +L_0x2be38c0 .part v0x2960210_0, 0, 1; +S_0x2388050 .scope module, "potato" "TwoInMux" 3 161, 3 109, S_0x23882e0; + .timescale -9 -12; +L_0x2be33d0/d .functor NOT 1, L_0x2be38c0, C4<0>, C4<0>, C4<0>; +L_0x2be33d0 .delay (10000,10000,10000) L_0x2be33d0/d; +L_0x2be3490/d .functor AND 1, L_0x2be32c0, L_0x2be33d0, C4<1>, C4<1>; +L_0x2be3490 .delay (20000,20000,20000) L_0x2be3490/d; +L_0x2be35a0/d .functor AND 1, L_0x2be2f60, L_0x2be38c0, C4<1>, C4<1>; +L_0x2be35a0 .delay (20000,20000,20000) L_0x2be35a0/d; +L_0x2be36f0/d .functor OR 1, L_0x2be3490, L_0x2be35a0, C4<0>, C4<0>; +L_0x2be36f0 .delay (20000,20000,20000) L_0x2be36f0/d; +v0x2387d90_0 .net "S", 0 0, L_0x2be38c0; 1 drivers +v0x2387e10_0 .alias "in0", 0 0, v0x238c820_0; +v0x23870f0_0 .alias "in1", 0 0, v0x238c8a0_0; +v0x2387170_0 .net "nS", 0 0, L_0x2be33d0; 1 drivers +v0x2386e60_0 .net "out0", 0 0, L_0x2be3490; 1 drivers +v0x2386ee0_0 .net "out1", 0 0, L_0x2be35a0; 1 drivers +v0x2384380_0 .alias "outfinal", 0 0, v0x238c590_0; +S_0x23814a0 .scope generate, "andbits[18]" "andbits[18]" 3 231, 3 231, S_0x2543140; + .timescale -9 -12; +P_0x22cdfa8 .param/l "i" 3 231, +C4<010010>; +S_0x2381210 .scope module, "attempt" "AndNand" 3 233, 3 149, S_0x23814a0; + .timescale -9 -12; +L_0x2be3220/d .functor NAND 1, L_0x2be3aa0, L_0x2be3b40, C4<1>, C4<1>; +L_0x2be3220 .delay (10000,10000,10000) L_0x2be3220/d; +L_0x2be3d20/d .functor NOT 1, L_0x2be3220, C4<0>, C4<0>, C4<0>; +L_0x2be3d20 .delay (10000,10000,10000) L_0x2be3d20/d; +v0x23850b0_0 .net "A", 0 0, L_0x2be3aa0; 1 drivers +v0x2385150_0 .net "AandB", 0 0, L_0x2be3d20; 1 drivers +v0x2384e20_0 .net "AnandB", 0 0, L_0x2be3220; 1 drivers +v0x2384ea0_0 .net "AndNandOut", 0 0, L_0x2be4150; 1 drivers +v0x2384b90_0 .net "B", 0 0, L_0x2be3b40; 1 drivers +v0x2384c10_0 .alias "Command", 2 0, v0x295f7a0_0; +L_0x2be4320 .part v0x2960210_0, 0, 1; +S_0x237e730 .scope module, "potato" "TwoInMux" 3 161, 3 109, S_0x2381210; + .timescale -9 -12; +L_0x2be3e30/d .functor NOT 1, L_0x2be4320, C4<0>, C4<0>, C4<0>; +L_0x2be3e30 .delay (10000,10000,10000) L_0x2be3e30/d; +L_0x2be3ef0/d .functor AND 1, L_0x2be3d20, L_0x2be3e30, C4<1>, C4<1>; +L_0x2be3ef0 .delay (20000,20000,20000) L_0x2be3ef0/d; +L_0x2be4000/d .functor AND 1, L_0x2be3220, L_0x2be4320, C4<1>, C4<1>; +L_0x2be4000 .delay (20000,20000,20000) L_0x2be4000/d; +L_0x2be4150/d .functor OR 1, L_0x2be3ef0, L_0x2be4000, C4<0>, C4<0>; +L_0x2be4150 .delay (20000,20000,20000) L_0x2be4150/d; +v0x23821c0_0 .net "S", 0 0, L_0x2be4320; 1 drivers +v0x2386bd0_0 .alias "in0", 0 0, v0x2385150_0; +v0x2386c50_0 .alias "in1", 0 0, v0x2384e20_0; +v0x2386940_0 .net "nS", 0 0, L_0x2be3e30; 1 drivers +v0x23869c0_0 .net "out0", 0 0, L_0x2be3ef0; 1 drivers +v0x23863c0_0 .net "out1", 0 0, L_0x2be4000; 1 drivers +v0x2386440_0 .alias "outfinal", 0 0, v0x2384ea0_0; +S_0x2380f80 .scope generate, "andbits[19]" "andbits[19]" 3 231, 3 231, S_0x2543140; + .timescale -9 -12; +P_0x22dd928 .param/l "i" 3 231, +C4<010011>; +S_0x2380cf0 .scope module, "attempt" "AndNand" 3 233, 3 149, S_0x2380f80; + .timescale -9 -12; +L_0x2be4620/d .functor NAND 1, L_0x2be4f00, L_0x2be4460, C4<1>, C4<1>; +L_0x2be4620 .delay (10000,10000,10000) L_0x2be4620/d; +L_0x2be47a0/d .functor NOT 1, L_0x2be4620, C4<0>, C4<0>, C4<0>; +L_0x2be47a0 .delay (10000,10000,10000) L_0x2be47a0/d; +v0x237ed30_0 .net "A", 0 0, L_0x2be4f00; 1 drivers +v0x2382690_0 .net "AandB", 0 0, L_0x2be47a0; 1 drivers +v0x2382710_0 .net "AnandB", 0 0, L_0x2be4620; 1 drivers +v0x2382400_0 .net "AndNandOut", 0 0, L_0x2be4bf0; 1 drivers +v0x2382480_0 .net "B", 0 0, L_0x2be4460; 1 drivers +v0x2382140_0 .alias "Command", 2 0, v0x295f7a0_0; +L_0x2be4dc0 .part v0x2960210_0, 0, 1; +S_0x2380770 .scope module, "potato" "TwoInMux" 3 161, 3 109, S_0x2380cf0; + .timescale -9 -12; +L_0x2be48d0/d .functor NOT 1, L_0x2be4dc0, C4<0>, C4<0>, C4<0>; +L_0x2be48d0 .delay (10000,10000,10000) L_0x2be48d0/d; +L_0x2be4990/d .functor AND 1, L_0x2be47a0, L_0x2be48d0, C4<1>, C4<1>; +L_0x2be4990 .delay (20000,20000,20000) L_0x2be4990/d; +L_0x2be4aa0/d .functor AND 1, L_0x2be4620, L_0x2be4dc0, C4<1>, C4<1>; +L_0x2be4aa0 .delay (20000,20000,20000) L_0x2be4aa0/d; +L_0x2be4bf0/d .functor OR 1, L_0x2be4990, L_0x2be4aa0, C4<0>, C4<0>; +L_0x2be4bf0 .delay (20000,20000,20000) L_0x2be4bf0/d; +v0x237f460_0 .net "S", 0 0, L_0x2be4dc0; 1 drivers +v0x237f4e0_0 .alias "in0", 0 0, v0x2382690_0; +v0x237f1d0_0 .alias "in1", 0 0, v0x2382710_0; +v0x237f250_0 .net "nS", 0 0, L_0x2be48d0; 1 drivers +v0x237ef40_0 .net "out0", 0 0, L_0x2be4990; 1 drivers +v0x237efc0_0 .net "out1", 0 0, L_0x2be4aa0; 1 drivers +v0x237ecb0_0 .alias "outfinal", 0 0, v0x2382400_0; +S_0x2376c40 .scope generate, "andbits[20]" "andbits[20]" 3 231, 3 231, S_0x2543140; + .timescale -9 -12; +P_0x22e0648 .param/l "i" 3 231, +C4<010100>; +S_0x2375d30 .scope module, "attempt" "AndNand" 3 233, 3 149, S_0x2376c40; + .timescale -9 -12; +L_0x2be4550/d .functor NAND 1, L_0x2be4fa0, L_0x2be5040, C4<1>, C4<1>; +L_0x2be4550 .delay (10000,10000,10000) L_0x2be4550/d; +L_0x2be5200/d .functor NOT 1, L_0x2be4550, C4<0>, C4<0>, C4<0>; +L_0x2be5200 .delay (10000,10000,10000) L_0x2be5200/d; +v0x237c7a0_0 .net "A", 0 0, L_0x2be4fa0; 1 drivers +v0x237c840_0 .net "AandB", 0 0, L_0x2be5200; 1 drivers +v0x237b890_0 .net "AnandB", 0 0, L_0x2be4550; 1 drivers +v0x237b910_0 .net "AndNandOut", 0 0, L_0x2be5650; 1 drivers +v0x237b600_0 .net "B", 0 0, L_0x2be5040; 1 drivers +v0x237b680_0 .alias "Command", 2 0, v0x295f7a0_0; +L_0x2be5820 .part v0x2960210_0, 0, 1; +S_0x2375aa0 .scope module, "potato" "TwoInMux" 3 161, 3 109, S_0x2375d30; + .timescale -9 -12; +L_0x2be5330/d .functor NOT 1, L_0x2be5820, C4<0>, C4<0>, C4<0>; +L_0x2be5330 .delay (10000,10000,10000) L_0x2be5330/d; +L_0x2be53f0/d .functor AND 1, L_0x2be5200, L_0x2be5330, C4<1>, C4<1>; +L_0x2be53f0 .delay (20000,20000,20000) L_0x2be53f0/d; +L_0x2be5500/d .functor AND 1, L_0x2be4550, L_0x2be5820, C4<1>, C4<1>; +L_0x2be5500 .delay (20000,20000,20000) L_0x2be5500/d; +L_0x2be5650/d .functor OR 1, L_0x2be53f0, L_0x2be5500, C4<0>, C4<0>; +L_0x2be5650 .delay (20000,20000,20000) L_0x2be5650/d; +v0x2376f50_0 .net "S", 0 0, L_0x2be5820; 1 drivers +v0x23798a0_0 .alias "in0", 0 0, v0x237c840_0; +v0x2379920_0 .alias "in1", 0 0, v0x237b890_0; +v0x2379610_0 .net "nS", 0 0, L_0x2be5330; 1 drivers +v0x2379690_0 .net "out0", 0 0, L_0x2be53f0; 1 drivers +v0x237ca30_0 .net "out1", 0 0, L_0x2be5500; 1 drivers +v0x237cab0_0 .alias "outfinal", 0 0, v0x237b910_0; +S_0x23676f0 .scope generate, "andbits[21]" "andbits[21]" 3 231, 3 231, S_0x2543140; + .timescale -9 -12; +P_0x22e5198 .param/l "i" 3 231, +C4<010101>; +S_0x236e1e0 .scope module, "attempt" "AndNand" 3 233, 3 149, S_0x23676f0; + .timescale -9 -12; +L_0x2be5b50/d .functor NAND 1, L_0x2be62f0, L_0x2be5960, C4<1>, C4<1>; +L_0x2be5b50 .delay (10000,10000,10000) L_0x2be5b50/d; +L_0x2be5c90/d .functor NOT 1, L_0x2be5b50, C4<0>, C4<0>, C4<0>; +L_0x2be5c90 .delay (10000,10000,10000) L_0x2be5c90/d; +v0x236ffc0_0 .net "A", 0 0, L_0x2be62f0; 1 drivers +v0x2373d40_0 .net "AandB", 0 0, L_0x2be5c90; 1 drivers +v0x2373dc0_0 .net "AnandB", 0 0, L_0x2be5b50; 1 drivers +v0x2373ab0_0 .net "AndNandOut", 0 0, L_0x2bdbba0; 1 drivers +v0x2373b30_0 .net "B", 0 0, L_0x2be5960; 1 drivers +v0x2376ed0_0 .alias "Command", 2 0, v0x295f7a0_0; +L_0x2be61b0 .part v0x2960210_0, 0, 1; +S_0x236df50 .scope module, "potato" "TwoInMux" 3 161, 3 109, S_0x236e1e0; + .timescale -9 -12; +L_0x2be5dc0/d .functor NOT 1, L_0x2be61b0, C4<0>, C4<0>, C4<0>; +L_0x2be5dc0 .delay (10000,10000,10000) L_0x2be5dc0/d; +L_0x2be5e80/d .functor AND 1, L_0x2be5c90, L_0x2be5dc0, C4<1>, C4<1>; +L_0x2be5e80 .delay (20000,20000,20000) L_0x2be5e80/d; +L_0x2be5f90/d .functor AND 1, L_0x2be5b50, L_0x2be61b0, C4<1>, C4<1>; +L_0x2be5f90 .delay (20000,20000,20000) L_0x2be5f90/d; +L_0x2bdbba0/d .functor OR 1, L_0x2be5e80, L_0x2be5f90, C4<0>, C4<0>; +L_0x2bdbba0 .delay (20000,20000,20000) L_0x2bdbba0/d; +v0x2371370_0 .net "S", 0 0, L_0x2be61b0; 1 drivers +v0x23713f0_0 .alias "in0", 0 0, v0x2373d40_0; +v0x23710e0_0 .alias "in1", 0 0, v0x2373dc0_0; +v0x2371160_0 .net "nS", 0 0, L_0x2be5dc0; 1 drivers +v0x23701d0_0 .net "out0", 0 0, L_0x2be5e80; 1 drivers +v0x2370250_0 .net "out1", 0 0, L_0x2be5f90; 1 drivers +v0x236ff40_0 .alias "outfinal", 0 0, v0x2373ab0_0; +S_0x2369800 .scope generate, "andbits[22]" "andbits[22]" 3 231, 3 231, S_0x2543140; + .timescale -9 -12; +P_0x22e9ce8 .param/l "i" 3 231, +C4<010110>; +S_0x2368480 .scope module, "attempt" "AndNand" 3 233, 3 149, S_0x2369800; + .timescale -9 -12; +L_0x2be5a50/d .functor NAND 1, L_0x2be6390, L_0x2be6430, C4<1>, C4<1>; +L_0x2be5a50 .delay (10000,10000,10000) L_0x2be5a50/d; +L_0x2be6620/d .functor NOT 1, L_0x2be5a50, C4<0>, C4<0>, C4<0>; +L_0x2be6620 .delay (10000,10000,10000) L_0x2be6620/d; +v0x236b500_0 .net "A", 0 0, L_0x2be6390; 1 drivers +v0x236b5a0_0 .net "AandB", 0 0, L_0x2be6620; 1 drivers +v0x236a560_0 .net "AnandB", 0 0, L_0x2be5a50; 1 drivers +v0x236a5e0_0 .net "AndNandOut", 0 0, L_0x2be69d0; 1 drivers +v0x236a2d0_0 .net "B", 0 0, L_0x2be6430; 1 drivers +v0x236a350_0 .alias "Command", 2 0, v0x295f7a0_0; +L_0x2be6b60 .part v0x2960210_0, 0, 1; +S_0x23681c0 .scope module, "potato" "TwoInMux" 3 161, 3 109, S_0x2368480; + .timescale -9 -12; +L_0x2be6710/d .functor NOT 1, L_0x2be6b60, C4<0>, C4<0>, C4<0>; +L_0x2be6710 .delay (10000,10000,10000) L_0x2be6710/d; +L_0x2be67b0/d .functor AND 1, L_0x2be6620, L_0x2be6710, C4<1>, C4<1>; +L_0x2be67b0 .delay (20000,20000,20000) L_0x2be67b0/d; +L_0x2be68a0/d .functor AND 1, L_0x2be5a50, L_0x2be6b60, C4<1>, C4<1>; +L_0x2be68a0 .delay (20000,20000,20000) L_0x2be68a0/d; +L_0x2be69d0/d .functor OR 1, L_0x2be67b0, L_0x2be68a0, C4<0>, C4<0>; +L_0x2be69d0 .delay (20000,20000,20000) L_0x2be69d0/d; +v0x2369e00_0 .net "S", 0 0, L_0x2be6b60; 1 drivers +v0x2367f30_0 .alias "in0", 0 0, v0x236b5a0_0; +v0x2367fb0_0 .alias "in1", 0 0, v0x236a560_0; +v0x2367c70_0 .net "nS", 0 0, L_0x2be6710; 1 drivers +v0x2367cf0_0 .net "out0", 0 0, L_0x2be67b0; 1 drivers +v0x236b790_0 .net "out1", 0 0, L_0x2be68a0; 1 drivers +v0x236b810_0 .alias "outfinal", 0 0, v0x236a5e0_0; +S_0x2580300 .scope generate, "andbits[23]" "andbits[23]" 3 231, 3 231, S_0x2543140; + .timescale -9 -12; +P_0x230f998 .param/l "i" 3 231, +C4<010111>; +S_0x257f410 .scope module, "attempt" "AndNand" 3 233, 3 149, S_0x2580300; + .timescale -9 -12; +L_0x2be6520/d .functor NAND 1, L_0x2be7620, L_0x2be6ca0, C4<1>, C4<1>; +L_0x2be6520 .delay (10000,10000,10000) L_0x2be6520/d; +L_0x2be6fa0/d .functor NOT 1, L_0x2be6520, C4<0>, C4<0>, C4<0>; +L_0x2be6fa0 .delay (10000,10000,10000) L_0x2be6fa0/d; +v0x2584da0_0 .net "A", 0 0, L_0x2be7620; 1 drivers +v0x2583e50_0 .net "AandB", 0 0, L_0x2be6fa0; 1 drivers +v0x2583ed0_0 .net "AnandB", 0 0, L_0x2be6520; 1 drivers +v0x236a040_0 .net "AndNandOut", 0 0, L_0x2be7350; 1 drivers +v0x236a0c0_0 .net "B", 0 0, L_0x2be6ca0; 1 drivers +v0x2369d80_0 .alias "Command", 2 0, v0x295f7a0_0; +L_0x2be74e0 .part v0x2960210_0, 0, 1; +S_0x2582aa0 .scope module, "potato" "TwoInMux" 3 161, 3 109, S_0x257f410; + .timescale -9 -12; +L_0x2be7090/d .functor NOT 1, L_0x2be74e0, C4<0>, C4<0>, C4<0>; +L_0x2be7090 .delay (10000,10000,10000) L_0x2be7090/d; +L_0x2be7130/d .functor AND 1, L_0x2be6fa0, L_0x2be7090, C4<1>, C4<1>; +L_0x2be7130 .delay (20000,20000,20000) L_0x2be7130/d; +L_0x2be7220/d .functor AND 1, L_0x2be6520, L_0x2be74e0, C4<1>, C4<1>; +L_0x2be7220 .delay (20000,20000,20000) L_0x2be7220/d; +L_0x2be7350/d .functor OR 1, L_0x2be7130, L_0x2be7220, C4<0>, C4<0>; +L_0x2be7350 .delay (20000,20000,20000) L_0x2be7350/d; +v0x2582820_0 .net "S", 0 0, L_0x2be74e0; 1 drivers +v0x25828a0_0 .alias "in0", 0 0, v0x2583e50_0; +v0x2581920_0 .alias "in1", 0 0, v0x2583ed0_0; +v0x25819a0_0 .net "nS", 0 0, L_0x2be7090; 1 drivers +v0x2584fa0_0 .net "out0", 0 0, L_0x2be7130; 1 drivers +v0x2585020_0 .net "out1", 0 0, L_0x2be7220; 1 drivers +v0x2584d20_0 .alias "outfinal", 0 0, v0x236a040_0; +S_0x25793d0 .scope generate, "andbits[24]" "andbits[24]" 3 231, 3 231, S_0x2543140; + .timescale -9 -12; +P_0x22f9138 .param/l "i" 3 231, +C4<011000>; +S_0x25784e0 .scope module, "attempt" "AndNand" 3 233, 3 149, S_0x25793d0; + .timescale -9 -12; +L_0x2be6d90/d .functor NAND 1, L_0x2be76c0, L_0x2be7760, C4<1>, C4<1>; +L_0x2be6d90 .delay (10000,10000,10000) L_0x2be6d90/d; +L_0x2be7940/d .functor NOT 1, L_0x2be6d90, C4<0>, C4<0>, C4<0>; +L_0x2be7940 .delay (10000,10000,10000) L_0x2be7940/d; +v0x257ddf0_0 .net "A", 0 0, L_0x2be76c0; 1 drivers +v0x257de90_0 .net "AandB", 0 0, L_0x2be7940; 1 drivers +v0x257cf00_0 .net "AnandB", 0 0, L_0x2be6d90; 1 drivers +v0x257cf80_0 .net "AndNandOut", 0 0, L_0x2be7cf0; 1 drivers +v0x2580580_0 .net "B", 0 0, L_0x2be7760; 1 drivers +v0x2580600_0 .alias "Command", 2 0, v0x295f7a0_0; +L_0x2be7e80 .part v0x2960210_0, 0, 1; +S_0x257bb60 .scope module, "potato" "TwoInMux" 3 161, 3 109, S_0x25784e0; + .timescale -9 -12; +L_0x2be7a30/d .functor NOT 1, L_0x2be7e80, C4<0>, C4<0>, C4<0>; +L_0x2be7a30 .delay (10000,10000,10000) L_0x2be7a30/d; +L_0x2be7ad0/d .functor AND 1, L_0x2be7940, L_0x2be7a30, C4<1>, C4<1>; +L_0x2be7ad0 .delay (20000,20000,20000) L_0x2be7ad0/d; +L_0x2be7bc0/d .functor AND 1, L_0x2be6d90, L_0x2be7e80, C4<1>, C4<1>; +L_0x2be7bc0 .delay (20000,20000,20000) L_0x2be7bc0/d; +L_0x2be7cf0/d .functor OR 1, L_0x2be7ad0, L_0x2be7bc0, C4<0>, C4<0>; +L_0x2be7cf0 .delay (20000,20000,20000) L_0x2be7cf0/d; +v0x25796d0_0 .net "S", 0 0, L_0x2be7e80; 1 drivers +v0x257b8e0_0 .alias "in0", 0 0, v0x257de90_0; +v0x257b960_0 .alias "in1", 0 0, v0x257cf00_0; +v0x257a9f0_0 .net "nS", 0 0, L_0x2be7a30; 1 drivers +v0x257aa70_0 .net "out0", 0 0, L_0x2be7ad0; 1 drivers +v0x257e070_0 .net "out1", 0 0, L_0x2be7bc0; 1 drivers +v0x257e0f0_0 .alias "outfinal", 0 0, v0x257cf80_0; +S_0x2572720 .scope generate, "andbits[25]" "andbits[25]" 3 231, 3 231, S_0x2543140; + .timescale -9 -12; +P_0x2318d78 .param/l "i" 3 231, +C4<011001>; +S_0x25724a0 .scope module, "attempt" "AndNand" 3 233, 3 149, S_0x2572720; + .timescale -9 -12; +L_0x2be7850/d .functor NAND 1, L_0x2be8930, L_0x2be7fc0, C4<1>, C4<1>; +L_0x2be7850 .delay (10000,10000,10000) L_0x2be7850/d; +L_0x2be82b0/d .functor NOT 1, L_0x2be7850, C4<0>, C4<0>, C4<0>; +L_0x2be82b0 .delay (10000,10000,10000) L_0x2be82b0/d; +v0x25771c0_0 .net "A", 0 0, L_0x2be8930; 1 drivers +v0x2576ec0_0 .net "AandB", 0 0, L_0x2be82b0; 1 drivers +v0x2576f40_0 .net "AnandB", 0 0, L_0x2be7850; 1 drivers +v0x2575fd0_0 .net "AndNandOut", 0 0, L_0x2be8660; 1 drivers +v0x2576050_0 .net "B", 0 0, L_0x2be7fc0; 1 drivers +v0x2579650_0 .alias "Command", 2 0, v0x295f7a0_0; +L_0x2be87f0 .part v0x2960210_0, 0, 1; +S_0x25715e0 .scope module, "potato" "TwoInMux" 3 161, 3 109, S_0x25724a0; + .timescale -9 -12; +L_0x2be83a0/d .functor NOT 1, L_0x2be87f0, C4<0>, C4<0>, C4<0>; +L_0x2be83a0 .delay (10000,10000,10000) L_0x2be83a0/d; +L_0x2be8440/d .functor AND 1, L_0x2be82b0, L_0x2be83a0, C4<1>, C4<1>; +L_0x2be8440 .delay (20000,20000,20000) L_0x2be8440/d; +L_0x2be8530/d .functor AND 1, L_0x2be7850, L_0x2be87f0, C4<1>, C4<1>; +L_0x2be8530 .delay (20000,20000,20000) L_0x2be8530/d; +L_0x2be8660/d .functor OR 1, L_0x2be8440, L_0x2be8530, C4<0>, C4<0>; +L_0x2be8660 .delay (20000,20000,20000) L_0x2be8660/d; +v0x2574c30_0 .net "S", 0 0, L_0x2be87f0; 1 drivers +v0x2574cb0_0 .alias "in0", 0 0, v0x2576ec0_0; +v0x25749b0_0 .alias "in1", 0 0, v0x2576f40_0; +v0x2574a30_0 .net "nS", 0 0, L_0x2be83a0; 1 drivers +v0x2573ac0_0 .net "out0", 0 0, L_0x2be8440; 1 drivers +v0x2573b40_0 .net "out1", 0 0, L_0x2be8530; 1 drivers +v0x2577140_0 .alias "outfinal", 0 0, v0x2575fd0_0; +S_0x256b830 .scope generate, "andbits[26]" "andbits[26]" 3 231, 3 231, S_0x2543140; + .timescale -9 -12; +P_0x22fbec8 .param/l "i" 3 231, +C4<011010>; +S_0x256b5b0 .scope module, "attempt" "AndNand" 3 233, 3 149, S_0x256b830; + .timescale -9 -12; +L_0x2be80b0/d .functor NAND 1, L_0x2be89d0, L_0x2be8a70, C4<1>, C4<1>; +L_0x2be80b0 .delay (10000,10000,10000) L_0x2be80b0/d; +L_0x2be8c30/d .functor NOT 1, L_0x2be80b0, C4<0>, C4<0>, C4<0>; +L_0x2be8c30 .delay (10000,10000,10000) L_0x2be8c30/d; +v0x2570230_0 .net "A", 0 0, L_0x2be89d0; 1 drivers +v0x25702d0_0 .net "AandB", 0 0, L_0x2be8c30; 1 drivers +v0x256ffb0_0 .net "AnandB", 0 0, L_0x2be80b0; 1 drivers +v0x2570030_0 .net "AndNandOut", 0 0, L_0x2be8fe0; 1 drivers +v0x256f0e0_0 .net "B", 0 0, L_0x2be8a70; 1 drivers +v0x256f160_0 .alias "Command", 2 0, v0x295f7a0_0; +L_0x2be9170 .part v0x2960210_0, 0, 1; +S_0x256a6e0 .scope module, "potato" "TwoInMux" 3 161, 3 109, S_0x256b5b0; + .timescale -9 -12; +L_0x2be8d20/d .functor NOT 1, L_0x2be9170, C4<0>, C4<0>, C4<0>; +L_0x2be8d20 .delay (10000,10000,10000) L_0x2be8d20/d; +L_0x2be8dc0/d .functor AND 1, L_0x2be8c30, L_0x2be8d20, C4<1>, C4<1>; +L_0x2be8dc0 .delay (20000,20000,20000) L_0x2be8dc0/d; +L_0x2be8eb0/d .functor AND 1, L_0x2be80b0, L_0x2be9170, C4<1>, C4<1>; +L_0x2be8eb0 .delay (20000,20000,20000) L_0x2be8eb0/d; +L_0x2be8fe0/d .functor OR 1, L_0x2be8dc0, L_0x2be8eb0, C4<0>, C4<0>; +L_0x2be8fe0 .delay (20000,20000,20000) L_0x2be8fe0/d; +v0x2568260_0 .net "S", 0 0, L_0x2be9170; 1 drivers +v0x256dd30_0 .alias "in0", 0 0, v0x25702d0_0; +v0x256ddb0_0 .alias "in1", 0 0, v0x256ffb0_0; +v0x256dab0_0 .net "nS", 0 0, L_0x2be8d20; 1 drivers +v0x256db30_0 .net "out0", 0 0, L_0x2be8dc0; 1 drivers +v0x256cbe0_0 .net "out1", 0 0, L_0x2be8eb0; 1 drivers +v0x256cc60_0 .alias "outfinal", 0 0, v0x2570030_0; +S_0x25612b0 .scope generate, "andbits[27]" "andbits[27]" 3 231, 3 231, S_0x2543140; + .timescale -9 -12; +P_0x2400f08 .param/l "i" 3 231, +C4<011011>; +S_0x2564930 .scope module, "attempt" "AndNand" 3 233, 3 149, S_0x25612b0; + .timescale -9 -12; +L_0x2be8b60/d .functor NAND 1, L_0x2be9c40, L_0x2be92b0, C4<1>, C4<1>; +L_0x2be8b60 .delay (10000,10000,10000) L_0x2be8b60/d; +L_0x2be95c0/d .functor NOT 1, L_0x2be8b60, C4<0>, C4<0>, C4<0>; +L_0x2be95c0 .delay (10000,10000,10000) L_0x2be95c0/d; +v0x2565d60_0 .net "A", 0 0, L_0x2be9c40; 1 drivers +v0x2569330_0 .net "AandB", 0 0, L_0x2be95c0; 1 drivers +v0x25693b0_0 .net "AnandB", 0 0, L_0x2be8b60; 1 drivers +v0x25690b0_0 .net "AndNandOut", 0 0, L_0x2be9970; 1 drivers +v0x2569130_0 .net "B", 0 0, L_0x2be92b0; 1 drivers +v0x25681e0_0 .alias "Command", 2 0, v0x295f7a0_0; +L_0x2be9b00 .part v0x2960210_0, 0, 1; +S_0x25646b0 .scope module, "potato" "TwoInMux" 3 161, 3 109, S_0x2564930; + .timescale -9 -12; +L_0x2be96b0/d .functor NOT 1, L_0x2be9b00, C4<0>, C4<0>, C4<0>; +L_0x2be96b0 .delay (10000,10000,10000) L_0x2be96b0/d; +L_0x2be9750/d .functor AND 1, L_0x2be95c0, L_0x2be96b0, C4<1>, C4<1>; +L_0x2be9750 .delay (20000,20000,20000) L_0x2be9750/d; +L_0x2be9840/d .functor AND 1, L_0x2be8b60, L_0x2be9b00, C4<1>, C4<1>; +L_0x2be9840 .delay (20000,20000,20000) L_0x2be9840/d; +L_0x2be9970/d .functor OR 1, L_0x2be9750, L_0x2be9840, C4<0>, C4<0>; +L_0x2be9970 .delay (20000,20000,20000) L_0x2be9970/d; +v0x25637e0_0 .net "S", 0 0, L_0x2be9b00; 1 drivers +v0x2563860_0 .alias "in0", 0 0, v0x2569330_0; +v0x2566e30_0 .alias "in1", 0 0, v0x25693b0_0; +v0x2566eb0_0 .net "nS", 0 0, L_0x2be96b0; 1 drivers +v0x2566bb0_0 .net "out0", 0 0, L_0x2be9750; 1 drivers +v0x2566c30_0 .net "out1", 0 0, L_0x2be9840; 1 drivers +v0x2565ce0_0 .alias "outfinal", 0 0, v0x25690b0_0; +S_0x255a380 .scope generate, "andbits[28]" "andbits[28]" 3 231, 3 231, S_0x2543140; + .timescale -9 -12; +P_0x23c1028 .param/l "i" 3 231, +C4<011100>; +S_0x255da00 .scope module, "attempt" "AndNand" 3 233, 3 149, S_0x255a380; + .timescale -9 -12; +L_0x2be93a0/d .functor NAND 1, L_0x2be9ce0, L_0x2be9d80, C4<1>, C4<1>; +L_0x2be93a0 .delay (10000,10000,10000) L_0x2be93a0/d; +L_0x2be9f70/d .functor NOT 1, L_0x2be93a0, C4<0>, C4<0>, C4<0>; +L_0x2be9f70 .delay (10000,10000,10000) L_0x2be9f70/d; +v0x255eda0_0 .net "A", 0 0, L_0x2be9ce0; 1 drivers +v0x255ee40_0 .net "AandB", 0 0, L_0x2be9f70; 1 drivers +v0x2562430_0 .net "AnandB", 0 0, L_0x2be93a0; 1 drivers +v0x25624b0_0 .net "AndNandOut", 0 0, L_0x2bea340; 1 drivers +v0x25621b0_0 .net "B", 0 0, L_0x2be9d80; 1 drivers +v0x2562230_0 .alias "Command", 2 0, v0x295f7a0_0; +L_0x2bea510 .part v0x2960210_0, 0, 1; +S_0x255d780 .scope module, "potato" "TwoInMux" 3 161, 3 109, S_0x255da00; + .timescale -9 -12; +L_0x2bea060/d .functor NOT 1, L_0x2bea510, C4<0>, C4<0>, C4<0>; +L_0x2bea060 .delay (10000,10000,10000) L_0x2bea060/d; +L_0x2bea100/d .functor AND 1, L_0x2be9f70, L_0x2bea060, C4<1>, C4<1>; +L_0x2bea100 .delay (20000,20000,20000) L_0x2bea100/d; +L_0x2bea1f0/d .functor AND 1, L_0x2be93a0, L_0x2bea510, C4<1>, C4<1>; +L_0x2bea1f0 .delay (20000,20000,20000) L_0x2bea1f0/d; +L_0x2bea340/d .functor OR 1, L_0x2bea100, L_0x2bea1f0, C4<0>, C4<0>; +L_0x2bea340 .delay (20000,20000,20000) L_0x2bea340/d; +v0x255b2f0_0 .net "S", 0 0, L_0x2bea510; 1 drivers +v0x255c890_0 .alias "in0", 0 0, v0x255ee40_0; +v0x255c910_0 .alias "in1", 0 0, v0x2562430_0; +v0x255ff10_0 .net "nS", 0 0, L_0x2bea060; 1 drivers +v0x255ff90_0 .net "out0", 0 0, L_0x2bea100; 1 drivers +v0x255fc90_0 .net "out1", 0 0, L_0x2bea1f0; 1 drivers +v0x255fd10_0 .alias "outfinal", 0 0, v0x25624b0_0; +S_0x2554340 .scope generate, "andbits[29]" "andbits[29]" 3 231, 3 231, S_0x2543140; + .timescale -9 -12; +P_0x238d688 .param/l "i" 3 231, +C4<011101>; +S_0x2553450 .scope module, "attempt" "AndNand" 3 233, 3 149, S_0x2554340; + .timescale -9 -12; +L_0x2be9e70/d .functor NAND 1, L_0x2beb0f0, L_0x2bea650, C4<1>, C4<1>; +L_0x2be9e70 .delay (10000,10000,10000) L_0x2be9e70/d; +L_0x2bea990/d .functor NOT 1, L_0x2be9e70, C4<0>, C4<0>, C4<0>; +L_0x2bea990 .delay (10000,10000,10000) L_0x2bea990/d; +v0x2558de0_0 .net "A", 0 0, L_0x2beb0f0; 1 drivers +v0x2557e70_0 .net "AandB", 0 0, L_0x2bea990; 1 drivers +v0x2557ef0_0 .net "AnandB", 0 0, L_0x2be9e70; 1 drivers +v0x255b4f0_0 .net "AndNandOut", 0 0, L_0x2beade0; 1 drivers +v0x255b570_0 .net "B", 0 0, L_0x2bea650; 1 drivers +v0x255b270_0 .alias "Command", 2 0, v0x295f7a0_0; +L_0x2beafb0 .part v0x2960210_0, 0, 1; +S_0x2556ad0 .scope module, "potato" "TwoInMux" 3 161, 3 109, S_0x2553450; + .timescale -9 -12; +L_0x2beaac0/d .functor NOT 1, L_0x2beafb0, C4<0>, C4<0>, C4<0>; +L_0x2beaac0 .delay (10000,10000,10000) L_0x2beaac0/d; +L_0x2beab80/d .functor AND 1, L_0x2bea990, L_0x2beaac0, C4<1>, C4<1>; +L_0x2beab80 .delay (20000,20000,20000) L_0x2beab80/d; +L_0x2beac90/d .functor AND 1, L_0x2be9e70, L_0x2beafb0, C4<1>, C4<1>; +L_0x2beac90 .delay (20000,20000,20000) L_0x2beac90/d; +L_0x2beade0/d .functor OR 1, L_0x2beab80, L_0x2beac90, C4<0>, C4<0>; +L_0x2beade0 .delay (20000,20000,20000) L_0x2beade0/d; +v0x2556850_0 .net "S", 0 0, L_0x2beafb0; 1 drivers +v0x25568d0_0 .alias "in0", 0 0, v0x2557e70_0; +v0x2555960_0 .alias "in1", 0 0, v0x2557ef0_0; +v0x25559e0_0 .net "nS", 0 0, L_0x2beaac0; 1 drivers +v0x2558fe0_0 .net "out0", 0 0, L_0x2beab80; 1 drivers +v0x2559060_0 .net "out1", 0 0, L_0x2beac90; 1 drivers +v0x2558d60_0 .alias "outfinal", 0 0, v0x255b4f0_0; +S_0x254d410 .scope generate, "andbits[30]" "andbits[30]" 3 231, 3 231, S_0x2543140; + .timescale -9 -12; +P_0x1f6b408 .param/l "i" 3 231, +C4<011110>; +S_0x254c580 .scope module, "attempt" "AndNand" 3 233, 3 149, S_0x254d410; + .timescale -9 -12; +L_0x2bea740/d .functor NAND 1, L_0x2beb190, L_0x2beb230, C4<1>, C4<1>; +L_0x2bea740 .delay (10000,10000,10000) L_0x2bea740/d; +L_0x2bea8a0/d .functor NOT 1, L_0x2bea740, C4<0>, C4<0>, C4<0>; +L_0x2bea8a0 .delay (10000,10000,10000) L_0x2bea8a0/d; +v0x2551e30_0 .net "A", 0 0, L_0x2beb190; 1 drivers +v0x2551ed0_0 .net "AandB", 0 0, L_0x2bea8a0; 1 drivers +v0x2550fa0_0 .net "AnandB", 0 0, L_0x2bea740; 1 drivers +v0x2551020_0 .net "AndNandOut", 0 0, L_0x2beb840; 1 drivers +v0x25545c0_0 .net "B", 0 0, L_0x2beb230; 1 drivers +v0x2554640_0 .alias "Command", 2 0, v0x295f7a0_0; +L_0x2beba10 .part v0x2960210_0, 0, 1; +S_0x254fba0 .scope module, "potato" "TwoInMux" 3 161, 3 109, S_0x254c580; + .timescale -9 -12; +L_0x2beb520/d .functor NOT 1, L_0x2beba10, C4<0>, C4<0>, C4<0>; +L_0x2beb520 .delay (10000,10000,10000) L_0x2beb520/d; +L_0x2beb5e0/d .functor AND 1, L_0x2bea8a0, L_0x2beb520, C4<1>, C4<1>; +L_0x2beb5e0 .delay (20000,20000,20000) L_0x2beb5e0/d; +L_0x2beb6f0/d .functor AND 1, L_0x2bea740, L_0x2beba10, C4<1>, C4<1>; +L_0x2beb6f0 .delay (20000,20000,20000) L_0x2beb6f0/d; +L_0x2beb840/d .functor OR 1, L_0x2beb5e0, L_0x2beb6f0, C4<0>, C4<0>; +L_0x2beb840 .delay (20000,20000,20000) L_0x2beb840/d; +v0x254d710_0 .net "S", 0 0, L_0x2beba10; 1 drivers +v0x254f920_0 .alias "in0", 0 0, v0x2551ed0_0; +v0x254f9a0_0 .alias "in1", 0 0, v0x2550fa0_0; +v0x254ea90_0 .net "nS", 0 0, L_0x2beb520; 1 drivers +v0x254eb10_0 .net "out0", 0 0, L_0x2beb5e0; 1 drivers +v0x25520b0_0 .net "out1", 0 0, L_0x2beb6f0; 1 drivers +v0x2552130_0 .alias "outfinal", 0 0, v0x2551020_0; +S_0x2546760 .scope generate, "andbits[31]" "andbits[31]" 3 231, 3 231, S_0x2543140; + .timescale -9 -12; +P_0x24306c8 .param/l "i" 3 231, +C4<011111>; +S_0x25464e0 .scope module, "attempt" "AndNand" 3 233, 3 149, S_0x2546760; + .timescale -9 -12; +L_0x2beb320/d .functor NAND 1, L_0x2bec5e0, L_0x2bebb50, C4<1>, C4<1>; +L_0x2beb320 .delay (10000,10000,10000) L_0x2beb320/d; +L_0x2bebe80/d .functor NOT 1, L_0x2beb320, C4<0>, C4<0>, C4<0>; +L_0x2bebe80 .delay (10000,10000,10000) L_0x2bebe80/d; +v0x254b200_0 .net "A", 0 0, L_0x2bec5e0; 1 drivers +v0x254af00_0 .net "AandB", 0 0, L_0x2bebe80; 1 drivers +v0x254af80_0 .net "AnandB", 0 0, L_0x2beb320; 1 drivers +v0x254a070_0 .net "AndNandOut", 0 0, L_0x2bec2d0; 1 drivers +v0x254a0f0_0 .net "B", 0 0, L_0x2bebb50; 1 drivers +v0x254d690_0 .alias "Command", 2 0, v0x295f7a0_0; +L_0x2bec4a0 .part v0x2960210_0, 0, 1; +S_0x2545650 .scope module, "potato" "TwoInMux" 3 161, 3 109, S_0x25464e0; + .timescale -9 -12; +L_0x2bebfb0/d .functor NOT 1, L_0x2bec4a0, C4<0>, C4<0>, C4<0>; +L_0x2bebfb0 .delay (10000,10000,10000) L_0x2bebfb0/d; +L_0x2bec070/d .functor AND 1, L_0x2bebe80, L_0x2bebfb0, C4<1>, C4<1>; +L_0x2bec070 .delay (20000,20000,20000) L_0x2bec070/d; +L_0x2bec180/d .functor AND 1, L_0x2beb320, L_0x2bec4a0, C4<1>, C4<1>; +L_0x2bec180 .delay (20000,20000,20000) L_0x2bec180/d; +L_0x2bec2d0/d .functor OR 1, L_0x2bec070, L_0x2bec180, C4<0>, C4<0>; +L_0x2bec2d0 .delay (20000,20000,20000) L_0x2bec2d0/d; +v0x2548c70_0 .net "S", 0 0, L_0x2bec4a0; 1 drivers +v0x2548cf0_0 .alias "in0", 0 0, v0x254af00_0; +v0x25489f0_0 .alias "in1", 0 0, v0x254af80_0; +v0x2548a70_0 .net "nS", 0 0, L_0x2bebfb0; 1 drivers +v0x2547b60_0 .net "out0", 0 0, L_0x2bec070; 1 drivers +v0x2547be0_0 .net "out1", 0 0, L_0x2bec180; 1 drivers +v0x254b180_0 .alias "outfinal", 0 0, v0x254a070_0; +S_0x2340a70 .scope module, "trial2" "OrNorXor32" 3 55, 3 239, S_0x1f6b890; + .timescale -9 -12; +P_0x23bfd58 .param/l "size" 3 246, +C4<0100000>; +v0x2544250_0 .alias "A", 31 0, v0x295f580_0; +v0x25442d0_0 .alias "B", 31 0, v0x295f6a0_0; +v0x2543fd0_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x2544050_0 .alias "OrNorXorOut", 31 0, v0x24153d0_0; +L_0x2bee390 .part/pv L_0x2bee120, 1, 1, 32; +L_0x2bee430 .part v0x295fe90_0, 1, 1; +L_0x2bee4d0 .part v0x2960190_0, 1, 1; +L_0x2bef6b0 .part/pv L_0x2bef440, 2, 1, 32; +L_0x2bef750 .part v0x295fe90_0, 2, 1; +L_0x2bef7f0 .part v0x2960190_0, 2, 1; +L_0x2bf09d0 .part/pv L_0x2bf0760, 3, 1, 32; +L_0x2bf0a70 .part v0x295fe90_0, 3, 1; +L_0x2bf0b10 .part v0x2960190_0, 3, 1; +L_0x2bf1ce0 .part/pv L_0x2bf1a70, 4, 1, 32; +L_0x2bf1de0 .part v0x295fe90_0, 4, 1; +L_0x2bf1e80 .part v0x2960190_0, 4, 1; +L_0x2bf3000 .part/pv L_0x2bf2d90, 5, 1, 32; +L_0x2bf30a0 .part v0x295fe90_0, 5, 1; +L_0x2bf31c0 .part v0x2960190_0, 5, 1; +L_0x2bf4380 .part/pv L_0x2bf4110, 6, 1, 32; +L_0x2bf44b0 .part v0x295fe90_0, 6, 1; +L_0x2bf4550 .part v0x2960190_0, 6, 1; +L_0x2bf5730 .part/pv L_0x2bf54c0, 7, 1, 32; +L_0x2bf57d0 .part v0x295fe90_0, 7, 1; +L_0x2bf45f0 .part v0x2960190_0, 7, 1; +L_0x2bf6a40 .part/pv L_0x2bf67d0, 8, 1, 32; +L_0x2bf5870 .part v0x295fe90_0, 8, 1; +L_0x2bf6ba0 .part v0x2960190_0, 8, 1; +L_0x2bf7d70 .part/pv L_0x2bf7b00, 9, 1, 32; +L_0x2bf7e10 .part v0x295fe90_0, 9, 1; +L_0x2bf6c40 .part v0x2960190_0, 9, 1; +L_0x2bf9090 .part/pv L_0x2bf8e20, 10, 1, 32; +L_0x2bf7eb0 .part v0x295fe90_0, 10, 1; +L_0x2bf9220 .part v0x2960190_0, 10, 1; +L_0x2bfa3b0 .part/pv L_0x2bfa140, 11, 1, 32; +L_0x2bfa450 .part v0x295fe90_0, 11, 1; +L_0x2bf92c0 .part v0x2960190_0, 11, 1; +L_0x2bfb6c0 .part/pv L_0x2bfb450, 12, 1, 32; +L_0x2bfa4f0 .part v0x295fe90_0, 12, 1; +L_0x2bfb880 .part v0x2960190_0, 12, 1; +L_0x2bfca00 .part/pv L_0x2bfc790, 13, 1, 32; +L_0x2bfcaa0 .part v0x295fe90_0, 13, 1; +L_0x2bfb920 .part v0x2960190_0, 13, 1; +L_0x2bfdd00 .part/pv L_0x2bfda90, 14, 1, 32; +L_0x2bfcb40 .part v0x295fe90_0, 14, 1; +L_0x2bfcbe0 .part v0x2960190_0, 14, 1; +L_0x2bff020 .part/pv L_0x2bfedb0, 15, 1, 32; +L_0x2bff0c0 .part v0x295fe90_0, 15, 1; +L_0x2bfdda0 .part v0x2960190_0, 15, 1; +L_0x2c00330 .part/pv L_0x2c000c0, 16, 1, 32; +L_0x2bff160 .part v0x295fe90_0, 16, 1; +L_0x2bff200 .part v0x2960190_0, 16, 1; +L_0x2c01660 .part/pv L_0x2c013f0, 17, 1, 32; +L_0x2c01700 .part v0x295fe90_0, 17, 1; +L_0x2c003d0 .part v0x2960190_0, 17, 1; +L_0x2c02970 .part/pv L_0x2c02700, 18, 1, 32; +L_0x2c017a0 .part v0x295fe90_0, 18, 1; +L_0x2c01840 .part v0x2960190_0, 18, 1; +L_0x2c03c90 .part/pv L_0x2c03a20, 19, 1, 32; +L_0x2c03d30 .part v0x295fe90_0, 19, 1; +L_0x2c02a10 .part v0x2960190_0, 19, 1; +L_0x2c04fb0 .part/pv L_0x2c04d40, 20, 1, 32; +L_0x2c03dd0 .part v0x295fe90_0, 20, 1; +L_0x2c03e70 .part v0x2960190_0, 20, 1; +L_0x2c062e0 .part/pv L_0x2c06070, 21, 1, 32; +L_0x2c06380 .part v0x295fe90_0, 21, 1; +L_0x2c05050 .part v0x2960190_0, 21, 1; +L_0x2c074b0 .part/pv L_0x2c07280, 22, 1, 32; +L_0x2c06420 .part v0x295fe90_0, 22, 1; +L_0x2c064c0 .part v0x2960190_0, 22, 1; +L_0x2c085f0 .part/pv L_0x2c083c0, 23, 1, 32; +L_0x2c08690 .part v0x295fe90_0, 23, 1; +L_0x2c07550 .part v0x2960190_0, 23, 1; +L_0x2c09730 .part/pv L_0x2c09500, 24, 1, 32; +L_0x2c08730 .part v0x295fe90_0, 24, 1; +L_0x2c087d0 .part v0x2960190_0, 24, 1; +L_0x2c0a850 .part/pv L_0x2c0a620, 25, 1, 32; +L_0x2c0a8f0 .part v0x295fe90_0, 25, 1; +L_0x2c097d0 .part v0x2960190_0, 25, 1; +L_0x2c0b980 .part/pv L_0x2c0b750, 26, 1, 32; +L_0x2c0a990 .part v0x295fe90_0, 26, 1; +L_0x2c0aa30 .part v0x2960190_0, 26, 1; +L_0x2c0cbd0 .part/pv L_0x2c0c960, 27, 1, 32; +L_0x2c0cc70 .part v0x295fe90_0, 27, 1; +L_0x2c0ba20 .part v0x2960190_0, 27, 1; +L_0x2c0def0 .part/pv L_0x2c0dc80, 28, 1, 32; +L_0x2c0cd10 .part v0x295fe90_0, 28, 1; +L_0x2c0cdb0 .part v0x2960190_0, 28, 1; +L_0x2c0f1f0 .part/pv L_0x2c0ef80, 29, 1, 32; +L_0x2c0f290 .part v0x295fe90_0, 29, 1; +L_0x2c0df90 .part v0x2960190_0, 29, 1; +L_0x2c10500 .part/pv L_0x2c10290, 30, 1, 32; +L_0x2c0f330 .part v0x295fe90_0, 30, 1; +L_0x2c0f3d0 .part v0x2960190_0, 30, 1; +L_0x2c11830 .part/pv L_0x2c115c0, 31, 1, 32; +L_0x2c118d0 .part v0x295fe90_0, 31, 1; +L_0x2c105a0 .part v0x2960190_0, 31, 1; +L_0x2c12b20 .part/pv L_0x2c128b0, 0, 1, 32; +L_0x2c11970 .part v0x295fe90_0, 0, 1; +L_0x2c11a10 .part v0x2960190_0, 0, 1; +S_0x253a7f0 .scope module, "attempt2" "OrNorXor" 3 254, 3 165, S_0x2340a70; + .timescale -9 -12; +L_0x2c10640/d .functor NOR 1, L_0x2c11970, L_0x2c11a10, C4<0>, C4<0>; +L_0x2c10640 .delay (10000,10000,10000) L_0x2c10640/d; +L_0x2c10730/d .functor NOT 1, L_0x2c10640, C4<0>, C4<0>, C4<0>; +L_0x2c10730 .delay (10000,10000,10000) L_0x2c10730/d; +L_0x2c11c60/d .functor NAND 1, L_0x2c11970, L_0x2c11a10, C4<1>, C4<1>; +L_0x2c11c60 .delay (10000,10000,10000) L_0x2c11c60/d; +L_0x2c11da0/d .functor NAND 1, L_0x2c11c60, L_0x2c10730, C4<1>, C4<1>; +L_0x2c11da0 .delay (10000,10000,10000) L_0x2c11da0/d; +L_0x2c11eb0/d .functor NOT 1, L_0x2c11da0, C4<0>, C4<0>, C4<0>; +L_0x2c11eb0 .delay (10000,10000,10000) L_0x2c11eb0/d; +v0x253f500_0 .net "A", 0 0, L_0x2c11970; 1 drivers +v0x253f580_0 .net "AnandB", 0 0, L_0x2c11c60; 1 drivers +v0x253e660_0 .net "AnorB", 0 0, L_0x2c10640; 1 drivers +v0x253e6e0_0 .net "AorB", 0 0, L_0x2c10730; 1 drivers +v0x2541d40_0 .net "AxorB", 0 0, L_0x2c11eb0; 1 drivers +v0x2541dc0_0 .net "B", 0 0, L_0x2c11a10; 1 drivers +v0x2541aa0_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x2541b20_0 .net "OrNorXorOut", 0 0, L_0x2c128b0; 1 drivers +v0x2540c10_0 .net "XorNor", 0 0, L_0x2c12330; 1 drivers +v0x2540c90_0 .net "nXor", 0 0, L_0x2c11da0; 1 drivers +L_0x2c124b0 .part v0x2960210_0, 2, 1; +L_0x2c12a80 .part v0x2960210_0, 0, 1; +S_0x2587480 .scope module, "mux0" "TwoInMux" 3 184, 3 109, S_0x253a7f0; + .timescale -9 -12; +L_0x2c12010/d .functor NOT 1, L_0x2c124b0, C4<0>, C4<0>, C4<0>; +L_0x2c12010 .delay (10000,10000,10000) L_0x2c12010/d; +L_0x2c120d0/d .functor AND 1, L_0x2c11eb0, L_0x2c12010, C4<1>, C4<1>; +L_0x2c120d0 .delay (20000,20000,20000) L_0x2c120d0/d; +L_0x2c121e0/d .functor AND 1, L_0x2c10640, L_0x2c124b0, C4<1>, C4<1>; +L_0x2c121e0 .delay (20000,20000,20000) L_0x2c121e0/d; +L_0x2c12330/d .functor OR 1, L_0x2c120d0, L_0x2c121e0, C4<0>, C4<0>; +L_0x2c12330 .delay (20000,20000,20000) L_0x2c12330/d; +v0x253b6b0_0 .net "S", 0 0, L_0x2c124b0; 1 drivers +v0x2587210_0 .alias "in0", 0 0, v0x2541d40_0; +v0x2587290_0 .alias "in1", 0 0, v0x253e660_0; +v0x2586350_0 .net "nS", 0 0, L_0x2c12010; 1 drivers +v0x25863d0_0 .net "out0", 0 0, L_0x2c120d0; 1 drivers +v0x253f7e0_0 .net "out1", 0 0, L_0x2c121e0; 1 drivers +v0x253f860_0 .alias "outfinal", 0 0, v0x2540c10_0; +S_0x253a570 .scope module, "mux1" "TwoInMux" 3 185, 3 109, S_0x253a7f0; + .timescale -9 -12; +L_0x2c12550/d .functor NOT 1, L_0x2c12a80, C4<0>, C4<0>, C4<0>; +L_0x2c12550 .delay (10000,10000,10000) L_0x2c12550/d; +L_0x2c12610/d .functor AND 1, L_0x2c12330, L_0x2c12550, C4<1>, C4<1>; +L_0x2c12610 .delay (20000,20000,20000) L_0x2c12610/d; +L_0x2c12760/d .functor AND 1, L_0x2c10730, L_0x2c12a80, C4<1>, C4<1>; +L_0x2c12760 .delay (20000,20000,20000) L_0x2c12760/d; +L_0x2c128b0/d .functor OR 1, L_0x2c12610, L_0x2c12760, C4<0>, C4<0>; +L_0x2c128b0 .delay (20000,20000,20000) L_0x2c128b0/d; +v0x253a070_0 .net "S", 0 0, L_0x2c12a80; 1 drivers +v0x253a0f0_0 .alias "in0", 0 0, v0x2540c10_0; +v0x253bdb0_0 .alias "in1", 0 0, v0x253e6e0_0; +v0x253be30_0 .net "nS", 0 0, L_0x2c12550; 1 drivers +v0x253bb30_0 .net "out0", 0 0, L_0x2c12610; 1 drivers +v0x253bbb0_0 .net "out1", 0 0, L_0x2c12760; 1 drivers +v0x253b630_0 .alias "outfinal", 0 0, v0x2541b20_0; +S_0x2531df0 .scope generate, "orbits[1]" "orbits[1]" 3 258, 3 258, S_0x2340a70; + .timescale -9 -12; +P_0x24a2fa8 .param/l "i" 3 258, +C4<01>; +S_0x2533b30 .scope module, "attempt" "OrNorXor" 3 260, 3 165, S_0x2531df0; + .timescale -9 -12; +L_0x2bec810/d .functor NOR 1, L_0x2bee430, L_0x2bee4d0, C4<0>, C4<0>; +L_0x2bec810 .delay (10000,10000,10000) L_0x2bec810/d; +L_0x2bed360/d .functor NOT 1, L_0x2bec810, C4<0>, C4<0>, C4<0>; +L_0x2bed360 .delay (10000,10000,10000) L_0x2bed360/d; +L_0x2bed490/d .functor NAND 1, L_0x2bee430, L_0x2bee4d0, C4<1>, C4<1>; +L_0x2bed490 .delay (10000,10000,10000) L_0x2bed490/d; +L_0x2bed610/d .functor NAND 1, L_0x2bed490, L_0x2bed360, C4<1>, C4<1>; +L_0x2bed610 .delay (10000,10000,10000) L_0x2bed610/d; +L_0x2bed720/d .functor NOT 1, L_0x2bed610, C4<0>, C4<0>, C4<0>; +L_0x2bed720 .delay (10000,10000,10000) L_0x2bed720/d; +v0x25379f0_0 .net "A", 0 0, L_0x2bee430; 1 drivers +v0x2537a90_0 .net "AnandB", 0 0, L_0x2bed490; 1 drivers +v0x25374f0_0 .net "AnorB", 0 0, L_0x2bec810; 1 drivers +v0x2537570_0 .net "AorB", 0 0, L_0x2bed360; 1 drivers +v0x2539230_0 .net "AxorB", 0 0, L_0x2bed720; 1 drivers +v0x25392b0_0 .net "B", 0 0, L_0x2bee4d0; 1 drivers +v0x2538fb0_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x2539030_0 .net "OrNorXorOut", 0 0, L_0x2bee120; 1 drivers +v0x2538ab0_0 .net "XorNor", 0 0, L_0x2bedba0; 1 drivers +v0x2538b30_0 .net "nXor", 0 0, L_0x2bed610; 1 drivers +L_0x2bedd20 .part v0x2960210_0, 2, 1; +L_0x2bee2f0 .part v0x2960210_0, 0, 1; +S_0x25366b0 .scope module, "mux0" "TwoInMux" 3 184, 3 109, S_0x2533b30; + .timescale -9 -12; +L_0x2bed880/d .functor NOT 1, L_0x2bedd20, C4<0>, C4<0>, C4<0>; +L_0x2bed880 .delay (10000,10000,10000) L_0x2bed880/d; +L_0x2bed940/d .functor AND 1, L_0x2bed720, L_0x2bed880, C4<1>, C4<1>; +L_0x2bed940 .delay (20000,20000,20000) L_0x2bed940/d; +L_0x2beda50/d .functor AND 1, L_0x2bec810, L_0x2bedd20, C4<1>, C4<1>; +L_0x2beda50 .delay (20000,20000,20000) L_0x2beda50/d; +L_0x2bedba0/d .functor OR 1, L_0x2bed940, L_0x2beda50, C4<0>, C4<0>; +L_0x2bedba0 .delay (20000,20000,20000) L_0x2bedba0/d; +v0x25349f0_0 .net "S", 0 0, L_0x2bedd20; 1 drivers +v0x2536430_0 .alias "in0", 0 0, v0x2539230_0; +v0x25364b0_0 .alias "in1", 0 0, v0x25374f0_0; +v0x2535f30_0 .net "nS", 0 0, L_0x2bed880; 1 drivers +v0x2535fb0_0 .net "out0", 0 0, L_0x2bed940; 1 drivers +v0x2537c70_0 .net "out1", 0 0, L_0x2beda50; 1 drivers +v0x2537d10_0 .alias "outfinal", 0 0, v0x2538ab0_0; +S_0x25338b0 .scope module, "mux1" "TwoInMux" 3 185, 3 109, S_0x2533b30; + .timescale -9 -12; +L_0x2beddc0/d .functor NOT 1, L_0x2bee2f0, C4<0>, C4<0>, C4<0>; +L_0x2beddc0 .delay (10000,10000,10000) L_0x2beddc0/d; +L_0x2bede80/d .functor AND 1, L_0x2bedba0, L_0x2beddc0, C4<1>, C4<1>; +L_0x2bede80 .delay (20000,20000,20000) L_0x2bede80/d; +L_0x2bedfd0/d .functor AND 1, L_0x2bed360, L_0x2bee2f0, C4<1>, C4<1>; +L_0x2bedfd0 .delay (20000,20000,20000) L_0x2bedfd0/d; +L_0x2bee120/d .functor OR 1, L_0x2bede80, L_0x2bedfd0, C4<0>, C4<0>; +L_0x2bee120 .delay (20000,20000,20000) L_0x2bee120/d; +v0x25333b0_0 .net "S", 0 0, L_0x2bee2f0; 1 drivers +v0x2533430_0 .alias "in0", 0 0, v0x2538ab0_0; +v0x25350f0_0 .alias "in1", 0 0, v0x2537570_0; +v0x2535170_0 .net "nS", 0 0, L_0x2beddc0; 1 drivers +v0x2534e70_0 .net "out0", 0 0, L_0x2bede80; 1 drivers +v0x2534ef0_0 .net "out1", 0 0, L_0x2bedfd0; 1 drivers +v0x2534970_0 .alias "outfinal", 0 0, v0x2539030_0; +S_0x2528d30 .scope generate, "orbits[2]" "orbits[2]" 3 258, 3 258, S_0x2340a70; + .timescale -9 -12; +P_0x2499838 .param/l "i" 3 258, +C4<010>; +S_0x2528ab0 .scope module, "attempt" "OrNorXor" 3 260, 3 165, S_0x2528d30; + .timescale -9 -12; +L_0x2bee570/d .functor NOR 1, L_0x2bef750, L_0x2bef7f0, C4<0>, C4<0>; +L_0x2bee570 .delay (10000,10000,10000) L_0x2bee570/d; +L_0x2bee680/d .functor NOT 1, L_0x2bee570, C4<0>, C4<0>, C4<0>; +L_0x2bee680 .delay (10000,10000,10000) L_0x2bee680/d; +L_0x2bee7b0/d .functor NAND 1, L_0x2bef750, L_0x2bef7f0, C4<1>, C4<1>; +L_0x2bee7b0 .delay (10000,10000,10000) L_0x2bee7b0/d; +L_0x2bee930/d .functor NAND 1, L_0x2bee7b0, L_0x2bee680, C4<1>, C4<1>; +L_0x2bee930 .delay (10000,10000,10000) L_0x2bee930/d; +L_0x2beea40/d .functor NOT 1, L_0x2bee930, C4<0>, C4<0>, C4<0>; +L_0x2beea40 .delay (10000,10000,10000) L_0x2beea40/d; +v0x252f750_0 .net "A", 0 0, L_0x2bef750; 1 drivers +v0x252f7f0_0 .net "AnandB", 0 0, L_0x2bee7b0; 1 drivers +v0x2530fb0_0 .net "AnorB", 0 0, L_0x2bee570; 1 drivers +v0x2531030_0 .net "AorB", 0 0, L_0x2bee680; 1 drivers +v0x2530d30_0 .net "AxorB", 0 0, L_0x2beea40; 1 drivers +v0x2530db0_0 .net "B", 0 0, L_0x2bef7f0; 1 drivers +v0x2532570_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x25325f0_0 .net "OrNorXorOut", 0 0, L_0x2bef440; 1 drivers +v0x25322f0_0 .net "XorNor", 0 0, L_0x2beeec0; 1 drivers +v0x2532370_0 .net "nXor", 0 0, L_0x2bee930; 1 drivers +L_0x2bef040 .part v0x2960210_0, 2, 1; +L_0x2bef610 .part v0x2960210_0, 0, 1; +S_0x252cbd0 .scope module, "mux0" "TwoInMux" 3 184, 3 109, S_0x2528ab0; + .timescale -9 -12; +L_0x2beeba0/d .functor NOT 1, L_0x2bef040, C4<0>, C4<0>, C4<0>; +L_0x2beeba0 .delay (10000,10000,10000) L_0x2beeba0/d; +L_0x2beec60/d .functor AND 1, L_0x2beea40, L_0x2beeba0, C4<1>, C4<1>; +L_0x2beec60 .delay (20000,20000,20000) L_0x2beec60/d; +L_0x2beed70/d .functor AND 1, L_0x2bee570, L_0x2bef040, C4<1>, C4<1>; +L_0x2beed70 .delay (20000,20000,20000) L_0x2beed70/d; +L_0x2beeec0/d .functor OR 1, L_0x2beec60, L_0x2beed70, C4<0>, C4<0>; +L_0x2beeec0 .delay (20000,20000,20000) L_0x2beeec0/d; +v0x252cef0_0 .net "S", 0 0, L_0x2bef040; 1 drivers +v0x252e430_0 .alias "in0", 0 0, v0x2530d30_0; +v0x252e4b0_0 .alias "in1", 0 0, v0x2530fb0_0; +v0x252e1b0_0 .net "nS", 0 0, L_0x2beeba0; 1 drivers +v0x252e230_0 .net "out0", 0 0, L_0x2beec60; 1 drivers +v0x252f9f0_0 .net "out1", 0 0, L_0x2beed70; 1 drivers +v0x252fa90_0 .alias "outfinal", 0 0, v0x25322f0_0; +S_0x252a2f0 .scope module, "mux1" "TwoInMux" 3 185, 3 109, S_0x2528ab0; + .timescale -9 -12; +L_0x2bef0e0/d .functor NOT 1, L_0x2bef610, C4<0>, C4<0>, C4<0>; +L_0x2bef0e0 .delay (10000,10000,10000) L_0x2bef0e0/d; +L_0x2bef1a0/d .functor AND 1, L_0x2beeec0, L_0x2bef0e0, C4<1>, C4<1>; +L_0x2bef1a0 .delay (20000,20000,20000) L_0x2bef1a0/d; +L_0x2bef2f0/d .functor AND 1, L_0x2bee680, L_0x2bef610, C4<1>, C4<1>; +L_0x2bef2f0 .delay (20000,20000,20000) L_0x2bef2f0/d; +L_0x2bef440/d .functor OR 1, L_0x2bef1a0, L_0x2bef2f0, C4<0>, C4<0>; +L_0x2bef440 .delay (20000,20000,20000) L_0x2bef440/d; +v0x252a050_0 .net "S", 0 0, L_0x2bef610; 1 drivers +v0x252a0d0_0 .alias "in0", 0 0, v0x25322f0_0; +v0x252b8b0_0 .alias "in1", 0 0, v0x2531030_0; +v0x252b930_0 .net "nS", 0 0, L_0x2bef0e0; 1 drivers +v0x252b630_0 .net "out0", 0 0, L_0x2bef1a0; 1 drivers +v0x252b6b0_0 .net "out1", 0 0, L_0x2bef2f0; 1 drivers +v0x252ce70_0 .alias "outfinal", 0 0, v0x25325f0_0; +S_0x251d790 .scope generate, "orbits[3]" "orbits[3]" 3 258, 3 258, S_0x2340a70; + .timescale -9 -12; +P_0x2493648 .param/l "i" 3 258, +C4<011>; +S_0x251f4d0 .scope module, "attempt" "OrNorXor" 3 260, 3 165, S_0x251d790; + .timescale -9 -12; +L_0x2bef8d0/d .functor NOR 1, L_0x2bf0a70, L_0x2bf0b10, C4<0>, C4<0>; +L_0x2bef8d0 .delay (10000,10000,10000) L_0x2bef8d0/d; +L_0x2bef9c0/d .functor NOT 1, L_0x2bef8d0, C4<0>, C4<0>, C4<0>; +L_0x2bef9c0 .delay (10000,10000,10000) L_0x2bef9c0/d; +L_0x2befad0/d .functor NAND 1, L_0x2bf0a70, L_0x2bf0b10, C4<1>, C4<1>; +L_0x2befad0 .delay (10000,10000,10000) L_0x2befad0/d; +L_0x2befc50/d .functor NAND 1, L_0x2befad0, L_0x2bef9c0, C4<1>, C4<1>; +L_0x2befc50 .delay (10000,10000,10000) L_0x2befc50/d; +L_0x2befd60/d .functor NOT 1, L_0x2befc50, C4<0>, C4<0>, C4<0>; +L_0x2befd60 .delay (10000,10000,10000) L_0x2befd60/d; +v0x2524950_0 .net "A", 0 0, L_0x2bf0a70; 1 drivers +v0x25249f0_0 .net "AnandB", 0 0, L_0x2befad0; 1 drivers +v0x25261b0_0 .net "AnorB", 0 0, L_0x2bef8d0; 1 drivers +v0x2526230_0 .net "AorB", 0 0, L_0x2bef9c0; 1 drivers +v0x2525f30_0 .net "AxorB", 0 0, L_0x2befd60; 1 drivers +v0x2525fb0_0 .net "B", 0 0, L_0x2bf0b10; 1 drivers +v0x2527770_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x25277f0_0 .net "OrNorXorOut", 0 0, L_0x2bf0760; 1 drivers +v0x25274d0_0 .net "XorNor", 0 0, L_0x2bf01e0; 1 drivers +v0x2527550_0 .net "nXor", 0 0, L_0x2befc50; 1 drivers +L_0x2bf0360 .part v0x2960210_0, 2, 1; +L_0x2bf0930 .part v0x2960210_0, 0, 1; +S_0x2521dd0 .scope module, "mux0" "TwoInMux" 3 184, 3 109, S_0x251f4d0; + .timescale -9 -12; +L_0x2befec0/d .functor NOT 1, L_0x2bf0360, C4<0>, C4<0>, C4<0>; +L_0x2befec0 .delay (10000,10000,10000) L_0x2befec0/d; +L_0x2beff80/d .functor AND 1, L_0x2befd60, L_0x2befec0, C4<1>, C4<1>; +L_0x2beff80 .delay (20000,20000,20000) L_0x2beff80/d; +L_0x2bf0090/d .functor AND 1, L_0x2bef8d0, L_0x2bf0360, C4<1>, C4<1>; +L_0x2bf0090 .delay (20000,20000,20000) L_0x2bf0090/d; +L_0x2bf01e0/d .functor OR 1, L_0x2beff80, L_0x2bf0090, C4<0>, C4<0>; +L_0x2bf01e0 .delay (20000,20000,20000) L_0x2bf01e0/d; +v0x25220f0_0 .net "S", 0 0, L_0x2bf0360; 1 drivers +v0x2523630_0 .alias "in0", 0 0, v0x2525f30_0; +v0x25236b0_0 .alias "in1", 0 0, v0x25261b0_0; +v0x25233b0_0 .net "nS", 0 0, L_0x2befec0; 1 drivers +v0x2523430_0 .net "out0", 0 0, L_0x2beff80; 1 drivers +v0x2524bf0_0 .net "out1", 0 0, L_0x2bf0090; 1 drivers +v0x2524c90_0 .alias "outfinal", 0 0, v0x25274d0_0; +S_0x251f250 .scope module, "mux1" "TwoInMux" 3 185, 3 109, S_0x251f4d0; + .timescale -9 -12; +L_0x2bf0400/d .functor NOT 1, L_0x2bf0930, C4<0>, C4<0>, C4<0>; +L_0x2bf0400 .delay (10000,10000,10000) L_0x2bf0400/d; +L_0x2bf04c0/d .functor AND 1, L_0x2bf01e0, L_0x2bf0400, C4<1>, C4<1>; +L_0x2bf04c0 .delay (20000,20000,20000) L_0x2bf04c0/d; +L_0x2bf0610/d .functor AND 1, L_0x2bef9c0, L_0x2bf0930, C4<1>, C4<1>; +L_0x2bf0610 .delay (20000,20000,20000) L_0x2bf0610/d; +L_0x2bf0760/d .functor OR 1, L_0x2bf04c0, L_0x2bf0610, C4<0>, C4<0>; +L_0x2bf0760 .delay (20000,20000,20000) L_0x2bf0760/d; +v0x251ed50_0 .net "S", 0 0, L_0x2bf0930; 1 drivers +v0x251edd0_0 .alias "in0", 0 0, v0x25274d0_0; +v0x2520ab0_0 .alias "in1", 0 0, v0x2526230_0; +v0x2520b30_0 .net "nS", 0 0, L_0x2bf0400; 1 drivers +v0x2520830_0 .net "out0", 0 0, L_0x2bf04c0; 1 drivers +v0x25208b0_0 .net "out1", 0 0, L_0x2bf0610; 1 drivers +v0x2522070_0 .alias "outfinal", 0 0, v0x25277f0_0; +S_0x2516fd0 .scope generate, "orbits[4]" "orbits[4]" 3 258, 3 258, S_0x2340a70; + .timescale -9 -12; +P_0x2486578 .param/l "i" 3 258, +C4<0100>; +S_0x2516ad0 .scope module, "attempt" "OrNorXor" 3 260, 3 165, S_0x2516fd0; + .timescale -9 -12; +L_0x2bf0bb0/d .functor NOR 1, L_0x2bf1de0, L_0x2bf1e80, C4<0>, C4<0>; +L_0x2bf0bb0 .delay (10000,10000,10000) L_0x2bf0bb0/d; +L_0x2bf0cb0/d .functor NOT 1, L_0x2bf0bb0, C4<0>, C4<0>, C4<0>; +L_0x2bf0cb0 .delay (10000,10000,10000) L_0x2bf0cb0/d; +L_0x2bf0de0/d .functor NAND 1, L_0x2bf1de0, L_0x2bf1e80, C4<1>, C4<1>; +L_0x2bf0de0 .delay (10000,10000,10000) L_0x2bf0de0/d; +L_0x2bf0f60/d .functor NAND 1, L_0x2bf0de0, L_0x2bf0cb0, C4<1>, C4<1>; +L_0x2bf0f60 .delay (10000,10000,10000) L_0x2bf0f60/d; +L_0x2bf1070/d .functor NOT 1, L_0x2bf0f60, C4<0>, C4<0>, C4<0>; +L_0x2bf1070 .delay (10000,10000,10000) L_0x2bf1070/d; +v0x251c950_0 .net "A", 0 0, L_0x2bf1de0; 1 drivers +v0x251c9f0_0 .net "AnandB", 0 0, L_0x2bf0de0; 1 drivers +v0x251c6d0_0 .net "AnorB", 0 0, L_0x2bf0bb0; 1 drivers +v0x251c750_0 .net "AorB", 0 0, L_0x2bf0cb0; 1 drivers +v0x251c1d0_0 .net "AxorB", 0 0, L_0x2bf1070; 1 drivers +v0x251c250_0 .net "B", 0 0, L_0x2bf1e80; 1 drivers +v0x251df10_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x251df90_0 .net "OrNorXorOut", 0 0, L_0x2bf1a70; 1 drivers +v0x251dc90_0 .net "XorNor", 0 0, L_0x2bf14f0; 1 drivers +v0x251dd10_0 .net "nXor", 0 0, L_0x2bf0f60; 1 drivers +L_0x2bf1670 .part v0x2960210_0, 2, 1; +L_0x2bf1c40 .part v0x2960210_0, 0, 1; +S_0x2519650 .scope module, "mux0" "TwoInMux" 3 184, 3 109, S_0x2516ad0; + .timescale -9 -12; +L_0x2bf11d0/d .functor NOT 1, L_0x2bf1670, C4<0>, C4<0>, C4<0>; +L_0x2bf11d0 .delay (10000,10000,10000) L_0x2bf11d0/d; +L_0x2bf1290/d .functor AND 1, L_0x2bf1070, L_0x2bf11d0, C4<1>, C4<1>; +L_0x2bf1290 .delay (20000,20000,20000) L_0x2bf1290/d; +L_0x2bf13a0/d .functor AND 1, L_0x2bf0bb0, L_0x2bf1670, C4<1>, C4<1>; +L_0x2bf13a0 .delay (20000,20000,20000) L_0x2bf13a0/d; +L_0x2bf14f0/d .functor OR 1, L_0x2bf1290, L_0x2bf13a0, C4<0>, C4<0>; +L_0x2bf14f0 .delay (20000,20000,20000) L_0x2bf14f0/d; +v0x2519bd0_0 .net "S", 0 0, L_0x2bf1670; 1 drivers +v0x251b390_0 .alias "in0", 0 0, v0x251c1d0_0; +v0x251b410_0 .alias "in1", 0 0, v0x251c6d0_0; +v0x251b110_0 .net "nS", 0 0, L_0x2bf11d0; 1 drivers +v0x251b190_0 .net "out0", 0 0, L_0x2bf1290; 1 drivers +v0x251ac10_0 .net "out1", 0 0, L_0x2bf13a0; 1 drivers +v0x251acb0_0 .alias "outfinal", 0 0, v0x251dc90_0; +S_0x2518810 .scope module, "mux1" "TwoInMux" 3 185, 3 109, S_0x2516ad0; + .timescale -9 -12; +L_0x2bf1710/d .functor NOT 1, L_0x2bf1c40, C4<0>, C4<0>, C4<0>; +L_0x2bf1710 .delay (10000,10000,10000) L_0x2bf1710/d; +L_0x2bf17d0/d .functor AND 1, L_0x2bf14f0, L_0x2bf1710, C4<1>, C4<1>; +L_0x2bf17d0 .delay (20000,20000,20000) L_0x2bf17d0/d; +L_0x2bf1920/d .functor AND 1, L_0x2bf0cb0, L_0x2bf1c40, C4<1>, C4<1>; +L_0x2bf1920 .delay (20000,20000,20000) L_0x2bf1920/d; +L_0x2bf1a70/d .functor OR 1, L_0x2bf17d0, L_0x2bf1920, C4<0>, C4<0>; +L_0x2bf1a70 .delay (20000,20000,20000) L_0x2bf1a70/d; +v0x2518590_0 .net "S", 0 0, L_0x2bf1c40; 1 drivers +v0x2518610_0 .alias "in0", 0 0, v0x251dc90_0; +v0x2518090_0 .alias "in1", 0 0, v0x251c750_0; +v0x2518110_0 .net "nS", 0 0, L_0x2bf1710; 1 drivers +v0x2519dd0_0 .net "out0", 0 0, L_0x2bf17d0; 1 drivers +v0x2519e50_0 .net "out1", 0 0, L_0x2bf1920; 1 drivers +v0x2519b50_0 .alias "outfinal", 0 0, v0x251df90_0; +S_0x250af40 .scope generate, "orbits[5]" "orbits[5]" 3 258, 3 258, S_0x2340a70; + .timescale -9 -12; +P_0x247cdf8 .param/l "i" 3 258, +C4<0101>; +S_0x2509300 .scope module, "attempt" "OrNorXor" 3 260, 3 165, S_0x250af40; + .timescale -9 -12; +L_0x2bf1d80/d .functor NOR 1, L_0x2bf30a0, L_0x2bf31c0, C4<0>, C4<0>; +L_0x2bf1d80 .delay (10000,10000,10000) L_0x2bf1d80/d; +L_0x2bf1fd0/d .functor NOT 1, L_0x2bf1d80, C4<0>, C4<0>, C4<0>; +L_0x2bf1fd0 .delay (10000,10000,10000) L_0x2bf1fd0/d; +L_0x2bf2100/d .functor NAND 1, L_0x2bf30a0, L_0x2bf31c0, C4<1>, C4<1>; +L_0x2bf2100 .delay (10000,10000,10000) L_0x2bf2100/d; +L_0x2bf2280/d .functor NAND 1, L_0x2bf2100, L_0x2bf1fd0, C4<1>, C4<1>; +L_0x2bf2280 .delay (10000,10000,10000) L_0x2bf2280/d; +L_0x2bf2390/d .functor NOT 1, L_0x2bf2280, C4<0>, C4<0>, C4<0>; +L_0x2bf2390 .delay (10000,10000,10000) L_0x2bf2390/d; +v0x2514450_0 .net "A", 0 0, L_0x2bf30a0; 1 drivers +v0x25144f0_0 .net "AnandB", 0 0, L_0x2bf2100; 1 drivers +v0x2515c90_0 .net "AnorB", 0 0, L_0x2bf1d80; 1 drivers +v0x2515d10_0 .net "AorB", 0 0, L_0x2bf1fd0; 1 drivers +v0x2515a10_0 .net "AxorB", 0 0, L_0x2bf2390; 1 drivers +v0x2515a90_0 .net "B", 0 0, L_0x2bf31c0; 1 drivers +v0x2515510_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x2515590_0 .net "OrNorXorOut", 0 0, L_0x2bf2d90; 1 drivers +v0x2517250_0 .net "XorNor", 0 0, L_0x2bf2810; 1 drivers +v0x25172d0_0 .net "nXor", 0 0, L_0x2bf2280; 1 drivers +L_0x2bf2990 .part v0x2960210_0, 2, 1; +L_0x2bf2f60 .part v0x2960210_0, 0, 1; +S_0x253d0e0 .scope module, "mux0" "TwoInMux" 3 184, 3 109, S_0x2509300; + .timescale -9 -12; +L_0x2bf24f0/d .functor NOT 1, L_0x2bf2990, C4<0>, C4<0>, C4<0>; +L_0x2bf24f0 .delay (10000,10000,10000) L_0x2bf24f0/d; +L_0x2bf25b0/d .functor AND 1, L_0x2bf2390, L_0x2bf24f0, C4<1>, C4<1>; +L_0x2bf25b0 .delay (20000,20000,20000) L_0x2bf25b0/d; +L_0x2bf26c0/d .functor AND 1, L_0x2bf1d80, L_0x2bf2990, C4<1>, C4<1>; +L_0x2bf26c0 .delay (20000,20000,20000) L_0x2bf26c0/d; +L_0x2bf2810/d .functor OR 1, L_0x2bf25b0, L_0x2bf26c0, C4<0>, C4<0>; +L_0x2bf2810 .delay (20000,20000,20000) L_0x2bf2810/d; +v0x253d3d0_0 .net "S", 0 0, L_0x2bf2990; 1 drivers +v0x253cbf0_0 .alias "in0", 0 0, v0x2515a10_0; +v0x253cc70_0 .alias "in1", 0 0, v0x2515c90_0; +v0x2512de0_0 .net "nS", 0 0, L_0x2bf24f0; 1 drivers +v0x2512e60_0 .net "out0", 0 0, L_0x2bf25b0; 1 drivers +v0x25146d0_0 .net "out1", 0 0, L_0x2bf26c0; 1 drivers +v0x2514770_0 .alias "outfinal", 0 0, v0x2517250_0; +S_0x250e250 .scope module, "mux1" "TwoInMux" 3 185, 3 109, S_0x2509300; + .timescale -9 -12; +L_0x2bf2a30/d .functor NOT 1, L_0x2bf2f60, C4<0>, C4<0>, C4<0>; +L_0x2bf2a30 .delay (10000,10000,10000) L_0x2bf2a30/d; +L_0x2bf2af0/d .functor AND 1, L_0x2bf2810, L_0x2bf2a30, C4<1>, C4<1>; +L_0x2bf2af0 .delay (20000,20000,20000) L_0x2bf2af0/d; +L_0x2bf2c40/d .functor AND 1, L_0x2bf1fd0, L_0x2bf2f60, C4<1>, C4<1>; +L_0x2bf2c40 .delay (20000,20000,20000) L_0x2bf2c40/d; +L_0x2bf2d90/d .functor OR 1, L_0x2bf2af0, L_0x2bf2c40, C4<0>, C4<0>; +L_0x2bf2d90 .delay (20000,20000,20000) L_0x2bf2d90/d; +v0x250dff0_0 .net "S", 0 0, L_0x2bf2f60; 1 drivers +v0x250e070_0 .alias "in0", 0 0, v0x2517250_0; +v0x250dd40_0 .alias "in1", 0 0, v0x2515d10_0; +v0x250ddc0_0 .net "nS", 0 0, L_0x2bf2a30; 1 drivers +v0x250c100_0 .net "out0", 0 0, L_0x2bf2af0; 1 drivers +v0x250c180_0 .net "out1", 0 0, L_0x2bf2c40; 1 drivers +v0x253d350_0 .alias "outfinal", 0 0, v0x2515590_0; +S_0x24ff900 .scope generate, "orbits[6]" "orbits[6]" 3 258, 3 258, S_0x2340a70; + .timescale -9 -12; +P_0x2473498 .param/l "i" 3 258, +C4<0110>; +S_0x24fdc70 .scope module, "attempt" "OrNorXor" 3 260, 3 165, S_0x24ff900; + .timescale -9 -12; +L_0x2bf3260/d .functor NOR 1, L_0x2bf44b0, L_0x2bf4550, C4<0>, C4<0>; +L_0x2bf3260 .delay (10000,10000,10000) L_0x2bf3260/d; +L_0x2bf3350/d .functor NOT 1, L_0x2bf3260, C4<0>, C4<0>, C4<0>; +L_0x2bf3350 .delay (10000,10000,10000) L_0x2bf3350/d; +L_0x2bf3480/d .functor NAND 1, L_0x2bf44b0, L_0x2bf4550, C4<1>, C4<1>; +L_0x2bf3480 .delay (10000,10000,10000) L_0x2bf3480/d; +L_0x2bf3600/d .functor NAND 1, L_0x2bf3480, L_0x2bf3350, C4<1>, C4<1>; +L_0x2bf3600 .delay (10000,10000,10000) L_0x2bf3600/d; +L_0x2bf3710/d .functor NOT 1, L_0x2bf3600, C4<0>, C4<0>, C4<0>; +L_0x2bf3710 .delay (10000,10000,10000) L_0x2bf3710/d; +v0x25083f0_0 .net "A", 0 0, L_0x2bf44b0; 1 drivers +v0x2508490_0 .net "AnandB", 0 0, L_0x2bf3480; 1 drivers +v0x2508140_0 .net "AnorB", 0 0, L_0x2bf3260; 1 drivers +v0x25081c0_0 .net "AorB", 0 0, L_0x2bf3350; 1 drivers +v0x2506500_0 .net "AxorB", 0 0, L_0x2bf3710; 1 drivers +v0x2506580_0 .net "B", 0 0, L_0x2bf4550; 1 drivers +v0x250b450_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x250b4d0_0 .net "OrNorXorOut", 0 0, L_0x2bf4110; 1 drivers +v0x250b1f0_0 .net "XorNor", 0 0, L_0x2bf3b90; 1 drivers +v0x250b270_0 .net "nXor", 0 0, L_0x2bf3600; 1 drivers +L_0x2bf3d10 .part v0x2960210_0, 2, 1; +L_0x2bf42e0 .part v0x2960210_0, 0, 1; +S_0x25055f0 .scope module, "mux0" "TwoInMux" 3 184, 3 109, S_0x24fdc70; + .timescale -9 -12; +L_0x2bf3870/d .functor NOT 1, L_0x2bf3d10, C4<0>, C4<0>, C4<0>; +L_0x2bf3870 .delay (10000,10000,10000) L_0x2bf3870/d; +L_0x2bf3930/d .functor AND 1, L_0x2bf3710, L_0x2bf3870, C4<1>, C4<1>; +L_0x2bf3930 .delay (20000,20000,20000) L_0x2bf3930/d; +L_0x2bf3a40/d .functor AND 1, L_0x2bf3260, L_0x2bf3d10, C4<1>, C4<1>; +L_0x2bf3a40 .delay (20000,20000,20000) L_0x2bf3a40/d; +L_0x2bf3b90/d .functor OR 1, L_0x2bf3930, L_0x2bf3a40, C4<0>, C4<0>; +L_0x2bf3b90 .delay (20000,20000,20000) L_0x2bf3b90/d; +v0x25058d0_0 .net "S", 0 0, L_0x2bf3d10; 1 drivers +v0x2505340_0 .alias "in0", 0 0, v0x2506500_0; +v0x25053c0_0 .alias "in1", 0 0, v0x2508140_0; +v0x2503700_0 .net "nS", 0 0, L_0x2bf3870; 1 drivers +v0x2503780_0 .net "out0", 0 0, L_0x2bf3930; 1 drivers +v0x2508650_0 .net "out1", 0 0, L_0x2bf3a40; 1 drivers +v0x25086f0_0 .alias "outfinal", 0 0, v0x250b1f0_0; +S_0x2502a50 .scope module, "mux1" "TwoInMux" 3 185, 3 109, S_0x24fdc70; + .timescale -9 -12; +L_0x2bf3db0/d .functor NOT 1, L_0x2bf42e0, C4<0>, C4<0>, C4<0>; +L_0x2bf3db0 .delay (10000,10000,10000) L_0x2bf3db0/d; +L_0x2bf3e70/d .functor AND 1, L_0x2bf3b90, L_0x2bf3db0, C4<1>, C4<1>; +L_0x2bf3e70 .delay (20000,20000,20000) L_0x2bf3e70/d; +L_0x2bf3fc0/d .functor AND 1, L_0x2bf3350, L_0x2bf42e0, C4<1>, C4<1>; +L_0x2bf3fc0 .delay (20000,20000,20000) L_0x2bf3fc0/d; +L_0x2bf4110/d .functor OR 1, L_0x2bf3e70, L_0x2bf3fc0, C4<0>, C4<0>; +L_0x2bf4110 .delay (20000,20000,20000) L_0x2bf4110/d; +v0x25027f0_0 .net "S", 0 0, L_0x2bf42e0; 1 drivers +v0x2502870_0 .alias "in0", 0 0, v0x250b1f0_0; +v0x2502540_0 .alias "in1", 0 0, v0x25081c0_0; +v0x25025c0_0 .net "nS", 0 0, L_0x2bf3db0; 1 drivers +v0x25008d0_0 .net "out0", 0 0, L_0x2bf3e70; 1 drivers +v0x2500950_0 .net "out1", 0 0, L_0x2bf3fc0; 1 drivers +v0x2505850_0 .alias "outfinal", 0 0, v0x250b4d0_0; +S_0x24f1470 .scope generate, "orbits[7]" "orbits[7]" 3 258, 3 258, S_0x2340a70; + .timescale -9 -12; +P_0x24220a8 .param/l "i" 3 258, +C4<0111>; +S_0x24f11c0 .scope module, "attempt" "OrNorXor" 3 260, 3 165, S_0x24f1470; + .timescale -9 -12; +L_0x2bf4420/d .functor NOR 1, L_0x2bf57d0, L_0x2bf45f0, C4<0>, C4<0>; +L_0x2bf4420 .delay (10000,10000,10000) L_0x2bf4420/d; +L_0x2bf4720/d .functor NOT 1, L_0x2bf4420, C4<0>, C4<0>, C4<0>; +L_0x2bf4720 .delay (10000,10000,10000) L_0x2bf4720/d; +L_0x2bf4830/d .functor NAND 1, L_0x2bf57d0, L_0x2bf45f0, C4<1>, C4<1>; +L_0x2bf4830 .delay (10000,10000,10000) L_0x2bf4830/d; +L_0x2bf49b0/d .functor NAND 1, L_0x2bf4830, L_0x2bf4720, C4<1>, C4<1>; +L_0x2bf49b0 .delay (10000,10000,10000) L_0x2bf49b0/d; +L_0x2bf4ac0/d .functor NOT 1, L_0x2bf49b0, C4<0>, C4<0>, C4<0>; +L_0x2bf4ac0 .delay (10000,10000,10000) L_0x2bf4ac0/d; +v0x24f7ff0_0 .net "A", 0 0, L_0x2bf57d0; 1 drivers +v0x24f8090_0 .net "AnandB", 0 0, L_0x2bf4830; 1 drivers +v0x24fcd70_0 .net "AnorB", 0 0, L_0x2bf4420; 1 drivers +v0x24fcdf0_0 .net "AorB", 0 0, L_0x2bf4720; 1 drivers +v0x24fcac0_0 .net "AxorB", 0 0, L_0x2bf4ac0; 1 drivers +v0x24fcb40_0 .net "B", 0 0, L_0x2bf45f0; 1 drivers +v0x24fae30_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x24faeb0_0 .net "OrNorXorOut", 0 0, L_0x2bf54c0; 1 drivers +v0x24ffbb0_0 .net "XorNor", 0 0, L_0x2bf4f40; 1 drivers +v0x24ffc30_0 .net "nXor", 0 0, L_0x2bf49b0; 1 drivers +L_0x2bf50c0 .part v0x2960210_0, 2, 1; +L_0x2bf5690 .part v0x2960210_0, 0, 1; +S_0x24f6e40 .scope module, "mux0" "TwoInMux" 3 184, 3 109, S_0x24f11c0; + .timescale -9 -12; +L_0x2bf4c20/d .functor NOT 1, L_0x2bf50c0, C4<0>, C4<0>, C4<0>; +L_0x2bf4c20 .delay (10000,10000,10000) L_0x2bf4c20/d; +L_0x2bf4ce0/d .functor AND 1, L_0x2bf4ac0, L_0x2bf4c20, C4<1>, C4<1>; +L_0x2bf4ce0 .delay (20000,20000,20000) L_0x2bf4ce0/d; +L_0x2bf4df0/d .functor AND 1, L_0x2bf4420, L_0x2bf50c0, C4<1>, C4<1>; +L_0x2bf4df0 .delay (20000,20000,20000) L_0x2bf4df0/d; +L_0x2bf4f40/d .functor OR 1, L_0x2bf4ce0, L_0x2bf4df0, C4<0>, C4<0>; +L_0x2bf4f40 .delay (20000,20000,20000) L_0x2bf4f40/d; +v0x24f7170_0 .net "S", 0 0, L_0x2bf50c0; 1 drivers +v0x24f51b0_0 .alias "in0", 0 0, v0x24fcac0_0; +v0x24f5230_0 .alias "in1", 0 0, v0x24fcd70_0; +v0x24f9f30_0 .net "nS", 0 0, L_0x2bf4c20; 1 drivers +v0x24f9fb0_0 .net "out0", 0 0, L_0x2bf4ce0; 1 drivers +v0x24f9c80_0 .net "out1", 0 0, L_0x2bf4df0; 1 drivers +v0x24f9d20_0 .alias "outfinal", 0 0, v0x24ffbb0_0; +S_0x24ef580 .scope module, "mux1" "TwoInMux" 3 185, 3 109, S_0x24f11c0; + .timescale -9 -12; +L_0x2bf5160/d .functor NOT 1, L_0x2bf5690, C4<0>, C4<0>, C4<0>; +L_0x2bf5160 .delay (10000,10000,10000) L_0x2bf5160/d; +L_0x2bf5220/d .functor AND 1, L_0x2bf4f40, L_0x2bf5160, C4<1>, C4<1>; +L_0x2bf5220 .delay (20000,20000,20000) L_0x2bf5220/d; +L_0x2bf5370/d .functor AND 1, L_0x2bf4720, L_0x2bf5690, C4<1>, C4<1>; +L_0x2bf5370 .delay (20000,20000,20000) L_0x2bf5370/d; +L_0x2bf54c0/d .functor OR 1, L_0x2bf5220, L_0x2bf5370, C4<0>, C4<0>; +L_0x2bf54c0 .delay (20000,20000,20000) L_0x2bf54c0/d; +v0x24f42b0_0 .net "S", 0 0, L_0x2bf5690; 1 drivers +v0x24f4330_0 .alias "in0", 0 0, v0x24ffbb0_0; +v0x24f4000_0 .alias "in1", 0 0, v0x24fcdf0_0; +v0x24f4080_0 .net "nS", 0 0, L_0x2bf5160; 1 drivers +v0x24f2370_0 .net "out0", 0 0, L_0x2bf5220; 1 drivers +v0x24f23f0_0 .net "out1", 0 0, L_0x2bf5370; 1 drivers +v0x24f70f0_0 .alias "outfinal", 0 0, v0x24faeb0_0; +S_0x24e5ed0 .scope generate, "orbits[8]" "orbits[8]" 3 258, 3 258, S_0x2340a70; + .timescale -9 -12; +P_0x245b6e8 .param/l "i" 3 258, +C4<01000>; +S_0x24e5c70 .scope module, "attempt" "OrNorXor" 3 260, 3 165, S_0x24e5ed0; + .timescale -9 -12; +L_0x2bf5920/d .functor NOR 1, L_0x2bf5870, L_0x2bf6ba0, C4<0>, C4<0>; +L_0x2bf5920 .delay (10000,10000,10000) L_0x2bf5920/d; +L_0x2bf5a10/d .functor NOT 1, L_0x2bf5920, C4<0>, C4<0>, C4<0>; +L_0x2bf5a10 .delay (10000,10000,10000) L_0x2bf5a10/d; +L_0x2bf5b40/d .functor NAND 1, L_0x2bf5870, L_0x2bf6ba0, C4<1>, C4<1>; +L_0x2bf5b40 .delay (10000,10000,10000) L_0x2bf5b40/d; +L_0x2bf5cc0/d .functor NAND 1, L_0x2bf5b40, L_0x2bf5a10, C4<1>, C4<1>; +L_0x2bf5cc0 .delay (10000,10000,10000) L_0x2bf5cc0/d; +L_0x2bf5dd0/d .functor NOT 1, L_0x2bf5cc0, C4<0>, C4<0>, C4<0>; +L_0x2bf5dd0 .delay (10000,10000,10000) L_0x2bf5dd0/d; +v0x24e9980_0 .net "A", 0 0, L_0x2bf5870; 1 drivers +v0x24e9a20_0 .net "AnandB", 0 0, L_0x2bf5b40; 1 drivers +v0x24ee8d0_0 .net "AnorB", 0 0, L_0x2bf5920; 1 drivers +v0x24ee950_0 .net "AorB", 0 0, L_0x2bf5a10; 1 drivers +v0x24ee670_0 .net "AxorB", 0 0, L_0x2bf5dd0; 1 drivers +v0x24ee6f0_0 .net "B", 0 0, L_0x2bf6ba0; 1 drivers +v0x24ee3c0_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x24ee440_0 .net "OrNorXorOut", 0 0, L_0x2bf67d0; 1 drivers +v0x24ec780_0 .net "XorNor", 0 0, L_0x2bf6250; 1 drivers +v0x24ec800_0 .net "nXor", 0 0, L_0x2bf5cc0; 1 drivers +L_0x2bf63d0 .part v0x2960210_0, 2, 1; +L_0x2bf69a0 .part v0x2960210_0, 0, 1; +S_0x24e6b80 .scope module, "mux0" "TwoInMux" 3 184, 3 109, S_0x24e5c70; + .timescale -9 -12; +L_0x2bf5f30/d .functor NOT 1, L_0x2bf63d0, C4<0>, C4<0>, C4<0>; +L_0x2bf5f30 .delay (10000,10000,10000) L_0x2bf5f30/d; +L_0x2bf5ff0/d .functor AND 1, L_0x2bf5dd0, L_0x2bf5f30, C4<1>, C4<1>; +L_0x2bf5ff0 .delay (20000,20000,20000) L_0x2bf5ff0/d; +L_0x2bf6100/d .functor AND 1, L_0x2bf5920, L_0x2bf63d0, C4<1>, C4<1>; +L_0x2bf6100 .delay (20000,20000,20000) L_0x2bf6100/d; +L_0x2bf6250/d .functor OR 1, L_0x2bf5ff0, L_0x2bf6100, C4<0>, C4<0>; +L_0x2bf6250 .delay (20000,20000,20000) L_0x2bf6250/d; +v0x24e8840_0 .net "S", 0 0, L_0x2bf63d0; 1 drivers +v0x24ebad0_0 .alias "in0", 0 0, v0x24ee670_0; +v0x24ebb50_0 .alias "in1", 0 0, v0x24ee8d0_0; +v0x24eb870_0 .net "nS", 0 0, L_0x2bf5f30; 1 drivers +v0x24eb8f0_0 .net "out0", 0 0, L_0x2bf5ff0; 1 drivers +v0x24eb5c0_0 .net "out1", 0 0, L_0x2bf6100; 1 drivers +v0x24eb660_0 .alias "outfinal", 0 0, v0x24ec780_0; +S_0x24e59c0 .scope module, "mux1" "TwoInMux" 3 185, 3 109, S_0x24e5c70; + .timescale -9 -12; +L_0x2bf6470/d .functor NOT 1, L_0x2bf69a0, C4<0>, C4<0>, C4<0>; +L_0x2bf6470 .delay (10000,10000,10000) L_0x2bf6470/d; +L_0x2bf6530/d .functor AND 1, L_0x2bf6250, L_0x2bf6470, C4<1>, C4<1>; +L_0x2bf6530 .delay (20000,20000,20000) L_0x2bf6530/d; +L_0x2bf6680/d .functor AND 1, L_0x2bf5a10, L_0x2bf69a0, C4<1>, C4<1>; +L_0x2bf6680 .delay (20000,20000,20000) L_0x2bf6680/d; +L_0x2bf67d0/d .functor OR 1, L_0x2bf6530, L_0x2bf6680, C4<0>, C4<0>; +L_0x2bf67d0 .delay (20000,20000,20000) L_0x2bf67d0/d; +v0x24e3d80_0 .net "S", 0 0, L_0x2bf69a0; 1 drivers +v0x24e3e00_0 .alias "in0", 0 0, v0x24ec780_0; +v0x24e8cd0_0 .alias "in1", 0 0, v0x24ee950_0; +v0x24e8d50_0 .net "nS", 0 0, L_0x2bf6470; 1 drivers +v0x24e8a70_0 .net "out0", 0 0, L_0x2bf6530; 1 drivers +v0x24e8af0_0 .net "out1", 0 0, L_0x2bf6680; 1 drivers +v0x24e87c0_0 .alias "outfinal", 0 0, v0x24ee440_0; +S_0x24d2a50 .scope generate, "orbits[9]" "orbits[9]" 3 258, 3 258, S_0x2340a70; + .timescale -9 -12; +P_0x24554f8 .param/l "i" 3 258, +C4<01001>; +S_0x24d77d0 .scope module, "attempt" "OrNorXor" 3 260, 3 165, S_0x24d2a50; + .timescale -9 -12; +L_0x2bf6ae0/d .functor NOR 1, L_0x2bf7e10, L_0x2bf6c40, C4<0>, C4<0>; +L_0x2bf6ae0 .delay (10000,10000,10000) L_0x2bf6ae0/d; +L_0x2bf6d60/d .functor NOT 1, L_0x2bf6ae0, C4<0>, C4<0>, C4<0>; +L_0x2bf6d60 .delay (10000,10000,10000) L_0x2bf6d60/d; +L_0x2bf6e70/d .functor NAND 1, L_0x2bf7e10, L_0x2bf6c40, C4<1>, C4<1>; +L_0x2bf6e70 .delay (10000,10000,10000) L_0x2bf6e70/d; +L_0x2bf6ff0/d .functor NAND 1, L_0x2bf6e70, L_0x2bf6d60, C4<1>, C4<1>; +L_0x2bf6ff0 .delay (10000,10000,10000) L_0x2bf6ff0/d; +L_0x2bf7100/d .functor NOT 1, L_0x2bf6ff0, C4<0>, C4<0>, C4<0>; +L_0x2bf7100 .delay (10000,10000,10000) L_0x2bf7100/d; +v0x24de350_0 .net "A", 0 0, L_0x2bf7e10; 1 drivers +v0x24de3f0_0 .net "AnandB", 0 0, L_0x2bf6e70; 1 drivers +v0x24e30d0_0 .net "AnorB", 0 0, L_0x2bf6ae0; 1 drivers +v0x24e3150_0 .net "AorB", 0 0, L_0x2bf6d60; 1 drivers +v0x24e2e70_0 .net "AxorB", 0 0, L_0x2bf7100; 1 drivers +v0x24e2ef0_0 .net "B", 0 0, L_0x2bf6c40; 1 drivers +v0x24e2bc0_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x24e2c40_0 .net "OrNorXorOut", 0 0, L_0x2bf7b00; 1 drivers +v0x24e0f80_0 .net "XorNor", 0 0, L_0x2bf7580; 1 drivers +v0x24e1000_0 .net "nXor", 0 0, L_0x2bf6ff0; 1 drivers +L_0x2bf7700 .part v0x2960210_0, 2, 1; +L_0x2bf7cd0 .part v0x2960210_0, 0, 1; +S_0x24dd450 .scope module, "mux0" "TwoInMux" 3 184, 3 109, S_0x24d77d0; + .timescale -9 -12; +L_0x2bf7260/d .functor NOT 1, L_0x2bf7700, C4<0>, C4<0>, C4<0>; +L_0x2bf7260 .delay (10000,10000,10000) L_0x2bf7260/d; +L_0x2bf7320/d .functor AND 1, L_0x2bf7100, L_0x2bf7260, C4<1>, C4<1>; +L_0x2bf7320 .delay (20000,20000,20000) L_0x2bf7320/d; +L_0x2bf7430/d .functor AND 1, L_0x2bf6ae0, L_0x2bf7700, C4<1>, C4<1>; +L_0x2bf7430 .delay (20000,20000,20000) L_0x2bf7430/d; +L_0x2bf7580/d .functor OR 1, L_0x2bf7320, L_0x2bf7430, C4<0>, C4<0>; +L_0x2bf7580 .delay (20000,20000,20000) L_0x2bf7580/d; +v0x24d8750_0 .net "S", 0 0, L_0x2bf7700; 1 drivers +v0x24dd1a0_0 .alias "in0", 0 0, v0x24e2e70_0; +v0x24dd220_0 .alias "in1", 0 0, v0x24e30d0_0; +v0x24db510_0 .net "nS", 0 0, L_0x2bf7260; 1 drivers +v0x24db590_0 .net "out0", 0 0, L_0x2bf7320; 1 drivers +v0x24e02e0_0 .net "out1", 0 0, L_0x2bf7430; 1 drivers +v0x24e0380_0 .alias "outfinal", 0 0, v0x24e0f80_0; +S_0x24d7520 .scope module, "mux1" "TwoInMux" 3 185, 3 109, S_0x24d77d0; + .timescale -9 -12; +L_0x2bf77a0/d .functor NOT 1, L_0x2bf7cd0, C4<0>, C4<0>, C4<0>; +L_0x2bf77a0 .delay (10000,10000,10000) L_0x2bf77a0/d; +L_0x2bf7860/d .functor AND 1, L_0x2bf7580, L_0x2bf77a0, C4<1>, C4<1>; +L_0x2bf7860 .delay (20000,20000,20000) L_0x2bf7860/d; +L_0x2bf79b0/d .functor AND 1, L_0x2bf6d60, L_0x2bf7cd0, C4<1>, C4<1>; +L_0x2bf79b0 .delay (20000,20000,20000) L_0x2bf79b0/d; +L_0x2bf7b00/d .functor OR 1, L_0x2bf7860, L_0x2bf79b0, C4<0>, C4<0>; +L_0x2bf7b00 .delay (20000,20000,20000) L_0x2bf7b00/d; +v0x24d5890_0 .net "S", 0 0, L_0x2bf7cd0; 1 drivers +v0x24d5910_0 .alias "in0", 0 0, v0x24e0f80_0; +v0x24da610_0 .alias "in1", 0 0, v0x24e3150_0; +v0x24da690_0 .net "nS", 0 0, L_0x2bf77a0; 1 drivers +v0x24da360_0 .net "out0", 0 0, L_0x2bf7860; 1 drivers +v0x24da3e0_0 .net "out1", 0 0, L_0x2bf79b0; 1 drivers +v0x24d86d0_0 .alias "outfinal", 0 0, v0x24e2c40_0; +S_0x24c9100 .scope generate, "orbits[10]" "orbits[10]" 3 258, 3 258, S_0x2340a70; + .timescale -9 -12; +P_0x244d038 .param/l "i" 3 258, +C4<01010>; +S_0x24c8e50 .scope module, "attempt" "OrNorXor" 3 260, 3 165, S_0x24c9100; + .timescale -9 -12; +L_0x2bf7f90/d .functor NOR 1, L_0x2bf7eb0, L_0x2bf9220, C4<0>, C4<0>; +L_0x2bf7f90 .delay (10000,10000,10000) L_0x2bf7f90/d; +L_0x2bf8080/d .functor NOT 1, L_0x2bf7f90, C4<0>, C4<0>, C4<0>; +L_0x2bf8080 .delay (10000,10000,10000) L_0x2bf8080/d; +L_0x2bf8190/d .functor NAND 1, L_0x2bf7eb0, L_0x2bf9220, C4<1>, C4<1>; +L_0x2bf8190 .delay (10000,10000,10000) L_0x2bf8190/d; +L_0x2bf8310/d .functor NAND 1, L_0x2bf8190, L_0x2bf8080, C4<1>, C4<1>; +L_0x2bf8310 .delay (10000,10000,10000) L_0x2bf8310/d; +L_0x2bf8420/d .functor NOT 1, L_0x2bf8310, C4<0>, C4<0>, C4<0>; +L_0x2bf8420 .delay (10000,10000,10000) L_0x2bf8420/d; +v0x24d1b50_0 .net "A", 0 0, L_0x2bf7eb0; 1 drivers +v0x24d1bf0_0 .net "AnandB", 0 0, L_0x2bf8190; 1 drivers +v0x24d18a0_0 .net "AnorB", 0 0, L_0x2bf7f90; 1 drivers +v0x24d1920_0 .net "AorB", 0 0, L_0x2bf8080; 1 drivers +v0x24cfc10_0 .net "AxorB", 0 0, L_0x2bf8420; 1 drivers +v0x24cfc90_0 .net "B", 0 0, L_0x2bf9220; 1 drivers +v0x24d4990_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x24d4a10_0 .net "OrNorXorOut", 0 0, L_0x2bf8e20; 1 drivers +v0x24d46e0_0 .net "XorNor", 0 0, L_0x2bf88a0; 1 drivers +v0x24d4760_0 .net "nXor", 0 0, L_0x2bf8310; 1 drivers +L_0x2bf8a20 .part v0x2960210_0, 2, 1; +L_0x2bf8ff0 .part v0x2960210_0, 0, 1; +S_0x24cef60 .scope module, "mux0" "TwoInMux" 3 184, 3 109, S_0x24c8e50; + .timescale -9 -12; +L_0x2bf8580/d .functor NOT 1, L_0x2bf8a20, C4<0>, C4<0>, C4<0>; +L_0x2bf8580 .delay (10000,10000,10000) L_0x2bf8580/d; +L_0x2bf8640/d .functor AND 1, L_0x2bf8420, L_0x2bf8580, C4<1>, C4<1>; +L_0x2bf8640 .delay (20000,20000,20000) L_0x2bf8640/d; +L_0x2bf8750/d .functor AND 1, L_0x2bf7f90, L_0x2bf8a20, C4<1>, C4<1>; +L_0x2bf8750 .delay (20000,20000,20000) L_0x2bf8750/d; +L_0x2bf88a0/d .functor OR 1, L_0x2bf8640, L_0x2bf8750, C4<0>, C4<0>; +L_0x2bf88a0 .delay (20000,20000,20000) L_0x2bf88a0/d; +v0x24ca090_0 .net "S", 0 0, L_0x2bf8a20; 1 drivers +v0x24ced00_0 .alias "in0", 0 0, v0x24cfc10_0; +v0x24ced80_0 .alias "in1", 0 0, v0x24d18a0_0; +v0x24cea50_0 .net "nS", 0 0, L_0x2bf8580; 1 drivers +v0x24cead0_0 .net "out0", 0 0, L_0x2bf8640; 1 drivers +v0x24cce10_0 .net "out1", 0 0, L_0x2bf8750; 1 drivers +v0x24cceb0_0 .alias "outfinal", 0 0, v0x24d46e0_0; +S_0x24c7210 .scope module, "mux1" "TwoInMux" 3 185, 3 109, S_0x24c8e50; + .timescale -9 -12; +L_0x2bf8ac0/d .functor NOT 1, L_0x2bf8ff0, C4<0>, C4<0>, C4<0>; +L_0x2bf8ac0 .delay (10000,10000,10000) L_0x2bf8ac0/d; +L_0x2bf8b80/d .functor AND 1, L_0x2bf88a0, L_0x2bf8ac0, C4<1>, C4<1>; +L_0x2bf8b80 .delay (20000,20000,20000) L_0x2bf8b80/d; +L_0x2bf8cd0/d .functor AND 1, L_0x2bf8080, L_0x2bf8ff0, C4<1>, C4<1>; +L_0x2bf8cd0 .delay (20000,20000,20000) L_0x2bf8cd0/d; +L_0x2bf8e20/d .functor OR 1, L_0x2bf8b80, L_0x2bf8cd0, C4<0>, C4<0>; +L_0x2bf8e20 .delay (20000,20000,20000) L_0x2bf8e20/d; +v0x24cc160_0 .net "S", 0 0, L_0x2bf8ff0; 1 drivers +v0x24cc1e0_0 .alias "in0", 0 0, v0x24d46e0_0; +v0x24cbf00_0 .alias "in1", 0 0, v0x24d1920_0; +v0x24cbf80_0 .net "nS", 0 0, L_0x2bf8ac0; 1 drivers +v0x24cbc50_0 .net "out0", 0 0, L_0x2bf8b80; 1 drivers +v0x24cbcd0_0 .net "out1", 0 0, L_0x2bf8cd0; 1 drivers +v0x24ca010_0 .alias "outfinal", 0 0, v0x24d4a10_0; +S_0x24bda90 .scope generate, "orbits[11]" "orbits[11]" 3 258, 3 258, S_0x2340a70; + .timescale -9 -12; +P_0x2443758 .param/l "i" 3 258, +C4<01011>; +S_0x24bd7e0 .scope module, "attempt" "OrNorXor" 3 260, 3 165, S_0x24bda90; + .timescale -9 -12; +L_0x2bf9130/d .functor NOR 1, L_0x2bfa450, L_0x2bf92c0, C4<0>, C4<0>; +L_0x2bf9130 .delay (10000,10000,10000) L_0x2bf9130/d; +L_0x2bf93c0/d .functor NOT 1, L_0x2bf9130, C4<0>, C4<0>, C4<0>; +L_0x2bf93c0 .delay (10000,10000,10000) L_0x2bf93c0/d; +L_0x2bf94b0/d .functor NAND 1, L_0x2bfa450, L_0x2bf92c0, C4<1>, C4<1>; +L_0x2bf94b0 .delay (10000,10000,10000) L_0x2bf94b0/d; +L_0x2bf9630/d .functor NAND 1, L_0x2bf94b0, L_0x2bf93c0, C4<1>, C4<1>; +L_0x2bf9630 .delay (10000,10000,10000) L_0x2bf9630/d; +L_0x2bf9740/d .functor NOT 1, L_0x2bf9630, C4<0>, C4<0>, C4<0>; +L_0x2bf9740 .delay (10000,10000,10000) L_0x2bf9740/d; +v0x24c6560_0 .net "A", 0 0, L_0x2bfa450; 1 drivers +v0x24c6600_0 .net "AnandB", 0 0, L_0x2bf94b0; 1 drivers +v0x24c6300_0 .net "AnorB", 0 0, L_0x2bf9130; 1 drivers +v0x24c6380_0 .net "AorB", 0 0, L_0x2bf93c0; 1 drivers +v0x24c6050_0 .net "AxorB", 0 0, L_0x2bf9740; 1 drivers +v0x24c60d0_0 .net "B", 0 0, L_0x2bf92c0; 1 drivers +v0x24c4410_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x24c4490_0 .net "OrNorXorOut", 0 0, L_0x2bfa140; 1 drivers +v0x24c9360_0 .net "XorNor", 0 0, L_0x2bf9bc0; 1 drivers +v0x24c93e0_0 .net "nXor", 0 0, L_0x2bf9630; 1 drivers +L_0x2bf9d40 .part v0x2960210_0, 2, 1; +L_0x2bfa310 .part v0x2960210_0, 0, 1; +S_0x24c3760 .scope module, "mux0" "TwoInMux" 3 184, 3 109, S_0x24bd7e0; + .timescale -9 -12; +L_0x2bf98a0/d .functor NOT 1, L_0x2bf9d40, C4<0>, C4<0>, C4<0>; +L_0x2bf98a0 .delay (10000,10000,10000) L_0x2bf98a0/d; +L_0x2bf9960/d .functor AND 1, L_0x2bf9740, L_0x2bf98a0, C4<1>, C4<1>; +L_0x2bf9960 .delay (20000,20000,20000) L_0x2bf9960/d; +L_0x2bf9a70/d .functor AND 1, L_0x2bf9130, L_0x2bf9d40, C4<1>, C4<1>; +L_0x2bf9a70 .delay (20000,20000,20000) L_0x2bf9a70/d; +L_0x2bf9bc0/d .functor OR 1, L_0x2bf9960, L_0x2bf9a70, C4<0>, C4<0>; +L_0x2bf9bc0 .delay (20000,20000,20000) L_0x2bf9bc0/d; +v0x24bea10_0 .net "S", 0 0, L_0x2bf9d40; 1 drivers +v0x24c3500_0 .alias "in0", 0 0, v0x24c6050_0; +v0x24c3580_0 .alias "in1", 0 0, v0x24c6300_0; +v0x24c3250_0 .net "nS", 0 0, L_0x2bf98a0; 1 drivers +v0x24c32d0_0 .net "out0", 0 0, L_0x2bf9960; 1 drivers +v0x24c1610_0 .net "out1", 0 0, L_0x2bf9a70; 1 drivers +v0x24c16b0_0 .alias "outfinal", 0 0, v0x24c9360_0; +S_0x24bbb50 .scope module, "mux1" "TwoInMux" 3 185, 3 109, S_0x24bd7e0; + .timescale -9 -12; +L_0x2bf9de0/d .functor NOT 1, L_0x2bfa310, C4<0>, C4<0>, C4<0>; +L_0x2bf9de0 .delay (10000,10000,10000) L_0x2bf9de0/d; +L_0x2bf9ea0/d .functor AND 1, L_0x2bf9bc0, L_0x2bf9de0, C4<1>, C4<1>; +L_0x2bf9ea0 .delay (20000,20000,20000) L_0x2bf9ea0/d; +L_0x2bf9ff0/d .functor AND 1, L_0x2bf93c0, L_0x2bfa310, C4<1>, C4<1>; +L_0x2bf9ff0 .delay (20000,20000,20000) L_0x2bf9ff0/d; +L_0x2bfa140/d .functor OR 1, L_0x2bf9ea0, L_0x2bf9ff0, C4<0>, C4<0>; +L_0x2bfa140 .delay (20000,20000,20000) L_0x2bfa140/d; +v0x24c0960_0 .net "S", 0 0, L_0x2bfa310; 1 drivers +v0x24c09e0_0 .alias "in0", 0 0, v0x24c9360_0; +v0x24c0700_0 .alias "in1", 0 0, v0x24c6380_0; +v0x24c0780_0 .net "nS", 0 0, L_0x2bf9de0; 1 drivers +v0x24c0450_0 .net "out0", 0 0, L_0x2bf9ea0; 1 drivers +v0x24c04d0_0 .net "out1", 0 0, L_0x2bf9ff0; 1 drivers +v0x24be990_0 .alias "outfinal", 0 0, v0x24c4490_0; +S_0x24e7da0 .scope generate, "orbits[12]" "orbits[12]" 3 258, 3 258, S_0x2340a70; + .timescale -9 -12; +P_0x243a028 .param/l "i" 3 258, +C4<01100>; +S_0x24e5520 .scope module, "attempt" "OrNorXor" 3 260, 3 165, S_0x24e7da0; + .timescale -9 -12; +L_0x2bf9360/d .functor NOR 1, L_0x2bfa4f0, L_0x2bfb880, C4<0>, C4<0>; +L_0x2bf9360 .delay (10000,10000,10000) L_0x2bf9360/d; +L_0x2bfa690/d .functor NOT 1, L_0x2bf9360, C4<0>, C4<0>, C4<0>; +L_0x2bfa690 .delay (10000,10000,10000) L_0x2bfa690/d; +L_0x2bfa7c0/d .functor NAND 1, L_0x2bfa4f0, L_0x2bfb880, C4<1>, C4<1>; +L_0x2bfa7c0 .delay (10000,10000,10000) L_0x2bfa7c0/d; +L_0x2bfa940/d .functor NAND 1, L_0x2bfa7c0, L_0x2bfa690, C4<1>, C4<1>; +L_0x2bfa940 .delay (10000,10000,10000) L_0x2bfa940/d; +L_0x2bfaa50/d .functor NOT 1, L_0x2bfa940, C4<0>, C4<0>, C4<0>; +L_0x2bfaa50 .delay (10000,10000,10000) L_0x2bfaa50/d; +v0x24b7ad0_0 .net "A", 0 0, L_0x2bfa4f0; 1 drivers +v0x24b7b70_0 .net "AnandB", 0 0, L_0x2bfa7c0; 1 drivers +v0x24b5d80_0 .net "AnorB", 0 0, L_0x2bf9360; 1 drivers +v0x24b5e00_0 .net "AorB", 0 0, L_0x2bfa690; 1 drivers +v0x24bac50_0 .net "AxorB", 0 0, L_0x2bfaa50; 1 drivers +v0x24bacd0_0 .net "B", 0 0, L_0x2bfb880; 1 drivers +v0x24ba9a0_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x24baa20_0 .net "OrNorXorOut", 0 0, L_0x2bfb450; 1 drivers +v0x24b8d10_0 .net "XorNor", 0 0, L_0x2bfaed0; 1 drivers +v0x24b8d90_0 .net "nXor", 0 0, L_0x2bfa940; 1 drivers +L_0x2bfb050 .part v0x2960210_0, 2, 1; +L_0x2bfb620 .part v0x2960210_0, 0, 1; +S_0x24dccd0 .scope module, "mux0" "TwoInMux" 3 184, 3 109, S_0x24e5520; + .timescale -9 -12; +L_0x2bfabb0/d .functor NOT 1, L_0x2bfb050, C4<0>, C4<0>, C4<0>; +L_0x2bfabb0 .delay (10000,10000,10000) L_0x2bfabb0/d; +L_0x2bfac70/d .functor AND 1, L_0x2bfaa50, L_0x2bfabb0, C4<1>, C4<1>; +L_0x2bfac70 .delay (20000,20000,20000) L_0x2bfac70/d; +L_0x2bfad80/d .functor AND 1, L_0x2bf9360, L_0x2bfb050, C4<1>, C4<1>; +L_0x2bfad80 .delay (20000,20000,20000) L_0x2bfad80/d; +L_0x2bfaed0/d .functor OR 1, L_0x2bfac70, L_0x2bfad80, C4<0>, C4<0>; +L_0x2bfaed0 .delay (20000,20000,20000) L_0x2bfaed0/d; +v0x24ba550_0 .net "S", 0 0, L_0x2bfb050; 1 drivers +v0x24d9e90_0 .alias "in0", 0 0, v0x24bac50_0; +v0x24d9f10_0 .alias "in1", 0 0, v0x24b5d80_0; +v0x24d7050_0 .net "nS", 0 0, L_0x2bfabb0; 1 drivers +v0x24d70d0_0 .net "out0", 0 0, L_0x2bfac70; 1 drivers +v0x250ef00_0 .net "out1", 0 0, L_0x2bfad80; 1 drivers +v0x250efa0_0 .alias "outfinal", 0 0, v0x24b8d10_0; +S_0x24e4fa0 .scope module, "mux1" "TwoInMux" 3 185, 3 109, S_0x24e5520; + .timescale -9 -12; +L_0x2bfb0f0/d .functor NOT 1, L_0x2bfb620, C4<0>, C4<0>, C4<0>; +L_0x2bfb0f0 .delay (10000,10000,10000) L_0x2bfb0f0/d; +L_0x2bfb1b0/d .functor AND 1, L_0x2bfaed0, L_0x2bfb0f0, C4<1>, C4<1>; +L_0x2bfb1b0 .delay (20000,20000,20000) L_0x2bfb1b0/d; +L_0x2bfb300/d .functor AND 1, L_0x2bfa690, L_0x2bfb620, C4<1>, C4<1>; +L_0x2bfb300 .delay (20000,20000,20000) L_0x2bfb300/d; +L_0x2bfb450/d .functor OR 1, L_0x2bfb1b0, L_0x2bfb300, C4<0>, C4<0>; +L_0x2bfb450 .delay (20000,20000,20000) L_0x2bfb450/d; +v0x24e2720_0 .net "S", 0 0, L_0x2bfb620; 1 drivers +v0x24e27a0_0 .alias "in0", 0 0, v0x24b8d10_0; +v0x24e21a0_0 .alias "in1", 0 0, v0x24b5e00_0; +v0x24e2220_0 .net "nS", 0 0, L_0x2bfb0f0; 1 drivers +v0x24dfb10_0 .net "out0", 0 0, L_0x2bfb1b0; 1 drivers +v0x24dfb90_0 .net "out1", 0 0, L_0x2bfb300; 1 drivers +v0x24ba4d0_0 .alias "outfinal", 0 0, v0x24baa20_0; +S_0x2504ea0 .scope generate, "orbits[13]" "orbits[13]" 3 258, 3 258, S_0x2340a70; + .timescale -9 -12; +P_0x2434b58 .param/l "i" 3 258, +C4<01101>; +S_0x2504920 .scope module, "attempt" "OrNorXor" 3 260, 3 165, S_0x2504ea0; + .timescale -9 -12; +L_0x2bfa590/d .functor NOR 1, L_0x2bfcaa0, L_0x2bfb920, C4<0>, C4<0>; +L_0x2bfa590 .delay (10000,10000,10000) L_0x2bfa590/d; +L_0x2bfb7f0/d .functor NOT 1, L_0x2bfa590, C4<0>, C4<0>, C4<0>; +L_0x2bfb7f0 .delay (10000,10000,10000) L_0x2bfb7f0/d; +L_0x2bfbb00/d .functor NAND 1, L_0x2bfcaa0, L_0x2bfb920, C4<1>, C4<1>; +L_0x2bfbb00 .delay (10000,10000,10000) L_0x2bfbb00/d; +L_0x2bfbc80/d .functor NAND 1, L_0x2bfbb00, L_0x2bfb7f0, C4<1>, C4<1>; +L_0x2bfbc80 .delay (10000,10000,10000) L_0x2bfbc80/d; +L_0x2bfbd90/d .functor NOT 1, L_0x2bfbc80, C4<0>, C4<0>, C4<0>; +L_0x2bfbd90 .delay (10000,10000,10000) L_0x2bfbd90/d; +v0x24edf20_0 .net "A", 0 0, L_0x2bfcaa0; 1 drivers +v0x24edfc0_0 .net "AnandB", 0 0, L_0x2bfbb00; 1 drivers +v0x24ed9a0_0 .net "AnorB", 0 0, L_0x2bfa590; 1 drivers +v0x24eda20_0 .net "AorB", 0 0, L_0x2bfb7f0; 1 drivers +v0x24eb120_0 .net "AxorB", 0 0, L_0x2bfbd90; 1 drivers +v0x24eb1a0_0 .net "B", 0 0, L_0x2bfb920; 1 drivers +v0x24eaba0_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x24eac20_0 .net "OrNorXorOut", 0 0, L_0x2bfc790; 1 drivers +v0x24e8320_0 .net "XorNor", 0 0, L_0x2bfc210; 1 drivers +v0x24e83a0_0 .net "nXor", 0 0, L_0x2bfbc80; 1 drivers +L_0x2bfc390 .part v0x2960210_0, 2, 1; +L_0x2bfc960 .part v0x2960210_0, 0, 1; +S_0x24f97b0 .scope module, "mux0" "TwoInMux" 3 184, 3 109, S_0x2504920; + .timescale -9 -12; +L_0x2bfbef0/d .functor NOT 1, L_0x2bfc390, C4<0>, C4<0>, C4<0>; +L_0x2bfbef0 .delay (10000,10000,10000) L_0x2bfbef0/d; +L_0x2bfbfb0/d .functor AND 1, L_0x2bfbd90, L_0x2bfbef0, C4<1>, C4<1>; +L_0x2bfbfb0 .delay (20000,20000,20000) L_0x2bfbfb0/d; +L_0x2bfc0c0/d .functor AND 1, L_0x2bfa590, L_0x2bfc390, C4<1>, C4<1>; +L_0x2bfc0c0 .delay (20000,20000,20000) L_0x2bfc0c0/d; +L_0x2bfc210/d .functor OR 1, L_0x2bfbfb0, L_0x2bfc0c0, C4<0>, C4<0>; +L_0x2bfc210 .delay (20000,20000,20000) L_0x2bfc210/d; +v0x24bd390_0 .net "S", 0 0, L_0x2bfc390; 1 drivers +v0x24f6970_0 .alias "in0", 0 0, v0x24eb120_0; +v0x24f69f0_0 .alias "in1", 0 0, v0x24ed9a0_0; +v0x24f3b30_0 .net "nS", 0 0, L_0x2bfbef0; 1 drivers +v0x24f3bb0_0 .net "out0", 0 0, L_0x2bfbfb0; 1 drivers +v0x24f0cf0_0 .net "out1", 0 0, L_0x2bfc0c0; 1 drivers +v0x24f0d90_0 .alias "outfinal", 0 0, v0x24e8320_0; +S_0x25020a0 .scope module, "mux1" "TwoInMux" 3 185, 3 109, S_0x2504920; + .timescale -9 -12; +L_0x2bfc430/d .functor NOT 1, L_0x2bfc960, C4<0>, C4<0>, C4<0>; +L_0x2bfc430 .delay (10000,10000,10000) L_0x2bfc430/d; +L_0x2bfc4f0/d .functor AND 1, L_0x2bfc210, L_0x2bfc430, C4<1>, C4<1>; +L_0x2bfc4f0 .delay (20000,20000,20000) L_0x2bfc4f0/d; +L_0x2bfc640/d .functor AND 1, L_0x2bfb7f0, L_0x2bfc960, C4<1>, C4<1>; +L_0x2bfc640 .delay (20000,20000,20000) L_0x2bfc640/d; +L_0x2bfc790/d .functor OR 1, L_0x2bfc4f0, L_0x2bfc640, C4<0>, C4<0>; +L_0x2bfc790 .delay (20000,20000,20000) L_0x2bfc790/d; +v0x2501b20_0 .net "S", 0 0, L_0x2bfc960; 1 drivers +v0x2501ba0_0 .alias "in0", 0 0, v0x24e8320_0; +v0x24ff430_0 .alias "in1", 0 0, v0x24eda20_0; +v0x24ff4b0_0 .net "nS", 0 0, L_0x2bfc430; 1 drivers +v0x24fc5f0_0 .net "out0", 0 0, L_0x2bfc4f0; 1 drivers +v0x24fc670_0 .net "out1", 0 0, L_0x2bfc640; 1 drivers +v0x24bd310_0 .alias "outfinal", 0 0, v0x24eac20_0; +S_0x24c5bb0 .scope generate, "orbits[14]" "orbits[14]" 3 258, 3 258, S_0x2340a70; + .timescale -9 -12; +P_0x2451568 .param/l "i" 3 258, +C4<01110>; +S_0x24c5630 .scope module, "attempt" "OrNorXor" 3 260, 3 165, S_0x24c5bb0; + .timescale -9 -12; +L_0x2bfb9c0/d .functor NOR 1, L_0x2bfcb40, L_0x2bfcbe0, C4<0>, C4<0>; +L_0x2bfb9c0 .delay (10000,10000,10000) L_0x2bfb9c0/d; +L_0x2bfcd10/d .functor NOT 1, L_0x2bfb9c0, C4<0>, C4<0>, C4<0>; +L_0x2bfcd10 .delay (10000,10000,10000) L_0x2bfcd10/d; +L_0x2bfce20/d .functor NAND 1, L_0x2bfcb40, L_0x2bfcbe0, C4<1>, C4<1>; +L_0x2bfce20 .delay (10000,10000,10000) L_0x2bfce20/d; +L_0x2bfcf80/d .functor NAND 1, L_0x2bfce20, L_0x2bfcd10, C4<1>, C4<1>; +L_0x2bfcf80 .delay (10000,10000,10000) L_0x2bfcf80/d; +L_0x2bfd090/d .functor NOT 1, L_0x2bfcf80, C4<0>, C4<0>, C4<0>; +L_0x2bfd090 .delay (10000,10000,10000) L_0x2bfd090/d; +v0x24bfb90_0 .net "A", 0 0, L_0x2bfcb40; 1 drivers +v0x24bfc10_0 .net "AnandB", 0 0, L_0x2bfce20; 1 drivers +v0x250aaa0_0 .net "AnorB", 0 0, L_0x2bfb9c0; 1 drivers +v0x250ab20_0 .net "AorB", 0 0, L_0x2bfcd10; 1 drivers +v0x250a520_0 .net "AxorB", 0 0, L_0x2bfd090; 1 drivers +v0x250a5a0_0 .net "B", 0 0, L_0x2bfcbe0; 1 drivers +v0x2507ca0_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x2507d20_0 .net "OrNorXorOut", 0 0, L_0x2bfda90; 1 drivers +v0x2507720_0 .net "XorNor", 0 0, L_0x2bfd510; 1 drivers +v0x25077a0_0 .net "nXor", 0 0, L_0x2bfcf80; 1 drivers +L_0x2bfd690 .part v0x2960210_0, 2, 1; +L_0x2bfdc60 .part v0x2960210_0, 0, 1; +S_0x2510b30 .scope module, "mux0" "TwoInMux" 3 184, 3 109, S_0x24c5630; + .timescale -9 -12; +L_0x2bfd1f0/d .functor NOT 1, L_0x2bfd690, C4<0>, C4<0>, C4<0>; +L_0x2bfd1f0 .delay (10000,10000,10000) L_0x2bfd1f0/d; +L_0x2bfd2b0/d .functor AND 1, L_0x2bfd090, L_0x2bfd1f0, C4<1>, C4<1>; +L_0x2bfd2b0 .delay (20000,20000,20000) L_0x2bfd2b0/d; +L_0x2bfd3c0/d .functor AND 1, L_0x2bfb9c0, L_0x2bfd690, C4<1>, C4<1>; +L_0x2bfd3c0 .delay (20000,20000,20000) L_0x2bfd3c0/d; +L_0x2bfd510/d .functor OR 1, L_0x2bfd2b0, L_0x2bfd3c0, C4<0>, C4<0>; +L_0x2bfd510 .delay (20000,20000,20000) L_0x2bfd510/d; +v0x2510e50_0 .net "S", 0 0, L_0x2bfd690; 1 drivers +v0x2510670_0 .alias "in0", 0 0, v0x250a520_0; +v0x25106f0_0 .alias "in1", 0 0, v0x250aaa0_0; +v0x250d8a0_0 .net "nS", 0 0, L_0x2bfd1f0; 1 drivers +v0x250d920_0 .net "out0", 0 0, L_0x2bfd2b0; 1 drivers +v0x250d320_0 .net "out1", 0 0, L_0x2bfd3c0; 1 drivers +v0x250d3a0_0 .alias "outfinal", 0 0, v0x2507720_0; +S_0x24c2db0 .scope module, "mux1" "TwoInMux" 3 185, 3 109, S_0x24c5630; + .timescale -9 -12; +L_0x2bfd730/d .functor NOT 1, L_0x2bfdc60, C4<0>, C4<0>, C4<0>; +L_0x2bfd730 .delay (10000,10000,10000) L_0x2bfd730/d; +L_0x2bfd7f0/d .functor AND 1, L_0x2bfd510, L_0x2bfd730, C4<1>, C4<1>; +L_0x2bfd7f0 .delay (20000,20000,20000) L_0x2bfd7f0/d; +L_0x2bfd940/d .functor AND 1, L_0x2bfcd10, L_0x2bfdc60, C4<1>, C4<1>; +L_0x2bfd940 .delay (20000,20000,20000) L_0x2bfd940/d; +L_0x2bfda90/d .functor OR 1, L_0x2bfd7f0, L_0x2bfd940, C4<0>, C4<0>; +L_0x2bfda90 .delay (20000,20000,20000) L_0x2bfda90/d; +v0x24b7600_0 .net "S", 0 0, L_0x2bfdc60; 1 drivers +v0x24b7680_0 .alias "in0", 0 0, v0x2507720_0; +v0x24c2830_0 .alias "in1", 0 0, v0x250ab20_0; +v0x24c28b0_0 .net "nS", 0 0, L_0x2bfd730; 1 drivers +v0x2511040_0 .net "out0", 0 0, L_0x2bfd7f0; 1 drivers +v0x25110c0_0 .net "out1", 0 0, L_0x2bfd940; 1 drivers +v0x2510dd0_0 .alias "outfinal", 0 0, v0x2507d20_0; +S_0x24a6dc0 .scope generate, "orbits[15]" "orbits[15]" 3 258, 3 258, S_0x2340a70; + .timescale -9 -12; +P_0x247c5d8 .param/l "i" 3 258, +C4<01111>; +S_0x24a5180 .scope module, "attempt" "OrNorXor" 3 260, 3 165, S_0x24a6dc0; + .timescale -9 -12; +L_0x2bfdf00/d .functor NOR 1, L_0x2bff0c0, L_0x2bfdda0, C4<0>, C4<0>; +L_0x2bfdf00 .delay (10000,10000,10000) L_0x2bfdf00/d; +L_0x2bfdff0/d .functor NOT 1, L_0x2bfdf00, C4<0>, C4<0>, C4<0>; +L_0x2bfdff0 .delay (10000,10000,10000) L_0x2bfdff0/d; +L_0x2bfe120/d .functor NAND 1, L_0x2bff0c0, L_0x2bfdda0, C4<1>, C4<1>; +L_0x2bfe120 .delay (10000,10000,10000) L_0x2bfe120/d; +L_0x2bfe2a0/d .functor NAND 1, L_0x2bfe120, L_0x2bfdff0, C4<1>, C4<1>; +L_0x2bfe2a0 .delay (10000,10000,10000) L_0x2bfe2a0/d; +L_0x2bfe3b0/d .functor NOT 1, L_0x2bfe2a0, C4<0>, C4<0>, C4<0>; +L_0x2bfe3b0 .delay (10000,10000,10000) L_0x2bfe3b0/d; +v0x24ce030_0 .net "A", 0 0, L_0x2bff0c0; 1 drivers +v0x24ce0d0_0 .net "AnandB", 0 0, L_0x2bfe120; 1 drivers +v0x24cb7b0_0 .net "AnorB", 0 0, L_0x2bfdf00; 1 drivers +v0x24cb830_0 .net "AorB", 0 0, L_0x2bfdff0; 1 drivers +v0x24cb230_0 .net "AxorB", 0 0, L_0x2bfe3b0; 1 drivers +v0x24cb2b0_0 .net "B", 0 0, L_0x2bfdda0; 1 drivers +v0x24c89b0_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x24c8a30_0 .net "OrNorXorOut", 0 0, L_0x2bfedb0; 1 drivers +v0x24c8430_0 .net "XorNor", 0 0, L_0x2bfe830; 1 drivers +v0x24c84b0_0 .net "nXor", 0 0, L_0x2bfe2a0; 1 drivers +L_0x2bfe9b0 .part v0x2960210_0, 2, 1; +L_0x2bfef80 .part v0x2960210_0, 0, 1; +S_0x24a9df0 .scope module, "mux0" "TwoInMux" 3 184, 3 109, S_0x24a5180; + .timescale -9 -12; +L_0x2bfe510/d .functor NOT 1, L_0x2bfe9b0, C4<0>, C4<0>, C4<0>; +L_0x2bfe510 .delay (10000,10000,10000) L_0x2bfe510/d; +L_0x2bfe5d0/d .functor AND 1, L_0x2bfe3b0, L_0x2bfe510, C4<1>, C4<1>; +L_0x2bfe5d0 .delay (20000,20000,20000) L_0x2bfe5d0/d; +L_0x2bfe6e0/d .functor AND 1, L_0x2bfdf00, L_0x2bfe9b0, C4<1>, C4<1>; +L_0x2bfe6e0 .delay (20000,20000,20000) L_0x2bfe6e0/d; +L_0x2bfe830/d .functor OR 1, L_0x2bfe5d0, L_0x2bfe6e0, C4<0>, C4<0>; +L_0x2bfe830 .delay (20000,20000,20000) L_0x2bfe830/d; +v0x24abab0_0 .net "S", 0 0, L_0x2bfe9b0; 1 drivers +v0x24d4210_0 .alias "in0", 0 0, v0x24cb230_0; +v0x24d4290_0 .alias "in1", 0 0, v0x24cb7b0_0; +v0x24d13d0_0 .net "nS", 0 0, L_0x2bfe510; 1 drivers +v0x24d1450_0 .net "out0", 0 0, L_0x2bfe5d0; 1 drivers +v0x24ce5b0_0 .net "out1", 0 0, L_0x2bfe6e0; 1 drivers +v0x24ce650_0 .alias "outfinal", 0 0, v0x24c8430_0; +S_0x24addc0 .scope module, "mux1" "TwoInMux" 3 185, 3 109, S_0x24a5180; + .timescale -9 -12; +L_0x2bfea50/d .functor NOT 1, L_0x2bfef80, C4<0>, C4<0>, C4<0>; +L_0x2bfea50 .delay (10000,10000,10000) L_0x2bfea50/d; +L_0x2bfeb10/d .functor AND 1, L_0x2bfe830, L_0x2bfea50, C4<1>, C4<1>; +L_0x2bfeb10 .delay (20000,20000,20000) L_0x2bfeb10/d; +L_0x2bfec60/d .functor AND 1, L_0x2bfdff0, L_0x2bfef80, C4<1>, C4<1>; +L_0x2bfec60 .delay (20000,20000,20000) L_0x2bfec60/d; +L_0x2bfedb0/d .functor OR 1, L_0x2bfeb10, L_0x2bfec60, C4<0>, C4<0>; +L_0x2bfedb0 .delay (20000,20000,20000) L_0x2bfedb0/d; +v0x24adb10_0 .net "S", 0 0, L_0x2bfef80; 1 drivers +v0x24adb90_0 .alias "in0", 0 0, v0x24c8430_0; +v0x24abf40_0 .alias "in1", 0 0, v0x24cb830_0; +v0x24abfc0_0 .net "nS", 0 0, L_0x2bfea50; 1 drivers +v0x24abce0_0 .net "out0", 0 0, L_0x2bfeb10; 1 drivers +v0x24abd60_0 .net "out1", 0 0, L_0x2bfec60; 1 drivers +v0x24aba30_0 .alias "outfinal", 0 0, v0x24c8a30_0; +S_0x2496cd0 .scope generate, "orbits[16]" "orbits[16]" 3 258, 3 258, S_0x2340a70; + .timescale -9 -12; +P_0x2499018 .param/l "i" 3 258, +C4<010000>; +S_0x249f870 .scope module, "attempt" "OrNorXor" 3 260, 3 165, S_0x2496cd0; + .timescale -9 -12; +L_0x2bfde40/d .functor NOR 1, L_0x2bff160, L_0x2bff200, C4<0>, C4<0>; +L_0x2bfde40 .delay (10000,10000,10000) L_0x2bfde40/d; +L_0x2bff320/d .functor NOT 1, L_0x2bfde40, C4<0>, C4<0>, C4<0>; +L_0x2bff320 .delay (10000,10000,10000) L_0x2bff320/d; +L_0x2bff430/d .functor NAND 1, L_0x2bff160, L_0x2bff200, C4<1>, C4<1>; +L_0x2bff430 .delay (10000,10000,10000) L_0x2bff430/d; +L_0x2bff5b0/d .functor NAND 1, L_0x2bff430, L_0x2bff320, C4<1>, C4<1>; +L_0x2bff5b0 .delay (10000,10000,10000) L_0x2bff5b0/d; +L_0x2bff6c0/d .functor NOT 1, L_0x2bff5b0, C4<0>, C4<0>, C4<0>; +L_0x2bff6c0 .delay (10000,10000,10000) L_0x2bff6c0/d; +v0x24a0510_0 .net "A", 0 0, L_0x2bff160; 1 drivers +v0x24a05b0_0 .net "AnandB", 0 0, L_0x2bff430; 1 drivers +v0x24a9150_0 .net "AnorB", 0 0, L_0x2bfde40; 1 drivers +v0x24a91d0_0 .net "AorB", 0 0, L_0x2bff320; 1 drivers +v0x24a8ea0_0 .net "AxorB", 0 0, L_0x2bff6c0; 1 drivers +v0x24a8f20_0 .net "B", 0 0, L_0x2bff200; 1 drivers +v0x24a72d0_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x24a7350_0 .net "OrNorXorOut", 0 0, L_0x2c000c0; 1 drivers +v0x24a7070_0 .net "XorNor", 0 0, L_0x2bffb40; 1 drivers +v0x24a70f0_0 .net "nXor", 0 0, L_0x2bff5b0; 1 drivers +L_0x2bffcc0 .part v0x2960210_0, 2, 1; +L_0x2c00290 .part v0x2960210_0, 0, 1; +S_0x24a4230 .scope module, "mux0" "TwoInMux" 3 184, 3 109, S_0x249f870; + .timescale -9 -12; +L_0x2bff820/d .functor NOT 1, L_0x2bffcc0, C4<0>, C4<0>, C4<0>; +L_0x2bff820 .delay (10000,10000,10000) L_0x2bff820/d; +L_0x2bff8e0/d .functor AND 1, L_0x2bff6c0, L_0x2bff820, C4<1>, C4<1>; +L_0x2bff8e0 .delay (20000,20000,20000) L_0x2bff8e0/d; +L_0x2bff9f0/d .functor AND 1, L_0x2bfde40, L_0x2bffcc0, C4<1>, C4<1>; +L_0x2bff9f0 .delay (20000,20000,20000) L_0x2bff9f0/d; +L_0x2bffb40/d .functor OR 1, L_0x2bff8e0, L_0x2bff9f0, C4<0>, C4<0>; +L_0x2bffb40 .delay (20000,20000,20000) L_0x2bffb40/d; +v0x24a4560_0 .net "S", 0 0, L_0x2bffcc0; 1 drivers +v0x24a2660_0 .alias "in0", 0 0, v0x24a8ea0_0; +v0x24a26e0_0 .alias "in1", 0 0, v0x24a9150_0; +v0x24a2400_0 .net "nS", 0 0, L_0x2bff820; 1 drivers +v0x24a2480_0 .net "out0", 0 0, L_0x2bff8e0; 1 drivers +v0x24a2150_0 .net "out1", 0 0, L_0x2bff9f0; 1 drivers +v0x24a21f0_0 .alias "outfinal", 0 0, v0x24a7070_0; +S_0x249f5c0 .scope module, "mux1" "TwoInMux" 3 185, 3 109, S_0x249f870; + .timescale -9 -12; +L_0x2bffd60/d .functor NOT 1, L_0x2c00290, C4<0>, C4<0>, C4<0>; +L_0x2bffd60 .delay (10000,10000,10000) L_0x2bffd60/d; +L_0x2bffe20/d .functor AND 1, L_0x2bffb40, L_0x2bffd60, C4<1>, C4<1>; +L_0x2bffe20 .delay (20000,20000,20000) L_0x2bffe20/d; +L_0x2bfff70/d .functor AND 1, L_0x2bff320, L_0x2c00290, C4<1>, C4<1>; +L_0x2bfff70 .delay (20000,20000,20000) L_0x2bfff70/d; +L_0x2c000c0/d .functor OR 1, L_0x2bffe20, L_0x2bfff70, C4<0>, C4<0>; +L_0x2c000c0 .delay (20000,20000,20000) L_0x2c000c0/d; +v0x249d8c0_0 .net "S", 0 0, L_0x2c00290; 1 drivers +v0x249d940_0 .alias "in0", 0 0, v0x24a7070_0; +v0x249d610_0 .alias "in1", 0 0, v0x24a91d0_0; +v0x249d690_0 .net "nS", 0 0, L_0x2bffd60; 1 drivers +v0x249b980_0 .net "out0", 0 0, L_0x2bffe20; 1 drivers +v0x249ba00_0 .net "out1", 0 0, L_0x2bfff70; 1 drivers +v0x24a44e0_0 .alias "outfinal", 0 0, v0x24a7350_0; +S_0x248a390 .scope generate, "orbits[17]" "orbits[17]" 3 258, 3 258, S_0x2340a70; + .timescale -9 -12; +P_0x24ce418 .param/l "i" 3 258, +C4<010001>; +S_0x2488750 .scope module, "attempt" "OrNorXor" 3 260, 3 165, S_0x248a390; + .timescale -9 -12; +L_0x2c00560/d .functor NOR 1, L_0x2c01700, L_0x2c003d0, C4<0>, C4<0>; +L_0x2c00560 .delay (10000,10000,10000) L_0x2c00560/d; +L_0x2c00650/d .functor NOT 1, L_0x2c00560, C4<0>, C4<0>, C4<0>; +L_0x2c00650 .delay (10000,10000,10000) L_0x2c00650/d; +L_0x2c00760/d .functor NAND 1, L_0x2c01700, L_0x2c003d0, C4<1>, C4<1>; +L_0x2c00760 .delay (10000,10000,10000) L_0x2c00760/d; +L_0x2c008e0/d .functor NAND 1, L_0x2c00760, L_0x2c00650, C4<1>, C4<1>; +L_0x2c008e0 .delay (10000,10000,10000) L_0x2c008e0/d; +L_0x2c009f0/d .functor NOT 1, L_0x2c008e0, C4<0>, C4<0>, C4<0>; +L_0x2c009f0 .delay (10000,10000,10000) L_0x2c009f0/d; +v0x2492020_0 .net "A", 0 0, L_0x2c01700; 1 drivers +v0x24920c0_0 .net "AnandB", 0 0, L_0x2c00760; 1 drivers +v0x249ace0_0 .net "AnorB", 0 0, L_0x2c00560; 1 drivers +v0x249ad60_0 .net "AorB", 0 0, L_0x2c00650; 1 drivers +v0x249aa30_0 .net "AxorB", 0 0, L_0x2c009f0; 1 drivers +v0x249aab0_0 .net "B", 0 0, L_0x2c003d0; 1 drivers +v0x2498c10_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x2498c90_0 .net "OrNorXorOut", 0 0, L_0x2c013f0; 1 drivers +v0x2498960_0 .net "XorNor", 0 0, L_0x2c00e70; 1 drivers +v0x24989e0_0 .net "nXor", 0 0, L_0x2c008e0; 1 drivers +L_0x2c00ff0 .part v0x2960210_0, 2, 1; +L_0x2c015c0 .part v0x2960210_0, 0, 1; +S_0x2496030 .scope module, "mux0" "TwoInMux" 3 184, 3 109, S_0x2488750; + .timescale -9 -12; +L_0x2c00b50/d .functor NOT 1, L_0x2c00ff0, C4<0>, C4<0>, C4<0>; +L_0x2c00b50 .delay (10000,10000,10000) L_0x2c00b50/d; +L_0x2c00c10/d .functor AND 1, L_0x2c009f0, L_0x2c00b50, C4<1>, C4<1>; +L_0x2c00c10 .delay (20000,20000,20000) L_0x2c00c10/d; +L_0x2c00d20/d .functor AND 1, L_0x2c00560, L_0x2c00ff0, C4<1>, C4<1>; +L_0x2c00d20 .delay (20000,20000,20000) L_0x2c00d20/d; +L_0x2c00e70/d .functor OR 1, L_0x2c00c10, L_0x2c00d20, C4<0>, C4<0>; +L_0x2c00e70 .delay (20000,20000,20000) L_0x2c00e70/d; +v0x248d440_0 .net "S", 0 0, L_0x2c00ff0; 1 drivers +v0x2495d80_0 .alias "in0", 0 0, v0x249aa30_0; +v0x2495e00_0 .alias "in1", 0 0, v0x249ace0_0; +v0x2493f60_0 .net "nS", 0 0, L_0x2c00b50; 1 drivers +v0x2493fe0_0 .net "out0", 0 0, L_0x2c00c10; 1 drivers +v0x2493cb0_0 .net "out1", 0 0, L_0x2c00d20; 1 drivers +v0x2493d50_0 .alias "outfinal", 0 0, v0x2498960_0; +S_0x2491380 .scope module, "mux1" "TwoInMux" 3 185, 3 109, S_0x2488750; + .timescale -9 -12; +L_0x2c01090/d .functor NOT 1, L_0x2c015c0, C4<0>, C4<0>, C4<0>; +L_0x2c01090 .delay (10000,10000,10000) L_0x2c01090/d; +L_0x2c01150/d .functor AND 1, L_0x2c00e70, L_0x2c01090, C4<1>, C4<1>; +L_0x2c01150 .delay (20000,20000,20000) L_0x2c01150/d; +L_0x2c012a0/d .functor AND 1, L_0x2c00650, L_0x2c015c0, C4<1>, C4<1>; +L_0x2c012a0 .delay (20000,20000,20000) L_0x2c012a0/d; +L_0x2c013f0/d .functor OR 1, L_0x2c01150, L_0x2c012a0, C4<0>, C4<0>; +L_0x2c013f0 .delay (20000,20000,20000) L_0x2c013f0/d; +v0x24910d0_0 .net "S", 0 0, L_0x2c015c0; 1 drivers +v0x2491150_0 .alias "in0", 0 0, v0x2498960_0; +v0x248f2b0_0 .alias "in1", 0 0, v0x249ad60_0; +v0x248f330_0 .net "nS", 0 0, L_0x2c01090; 1 drivers +v0x248f000_0 .net "out0", 0 0, L_0x2c01150; 1 drivers +v0x248f080_0 .net "out1", 0 0, L_0x2c012a0; 1 drivers +v0x248d3c0_0 .alias "outfinal", 0 0, v0x2498c90_0; +S_0x247bf20 .scope generate, "orbits[18]" "orbits[18]" 3 258, 3 258, S_0x2340a70; + .timescale -9 -12; +P_0x24c2c18 .param/l "i" 3 258, +C4<010010>; +S_0x247a290 .scope module, "attempt" "OrNorXor" 3 260, 3 165, S_0x247bf20; + .timescale -9 -12; +L_0x2c00470/d .functor NOR 1, L_0x2c017a0, L_0x2c01840, C4<0>, C4<0>; +L_0x2c00470 .delay (10000,10000,10000) L_0x2c00470/d; +L_0x2c01940/d .functor NOT 1, L_0x2c00470, C4<0>, C4<0>, C4<0>; +L_0x2c01940 .delay (10000,10000,10000) L_0x2c01940/d; +L_0x2c01a70/d .functor NAND 1, L_0x2c017a0, L_0x2c01840, C4<1>, C4<1>; +L_0x2c01a70 .delay (10000,10000,10000) L_0x2c01a70/d; +L_0x2c01bf0/d .functor NAND 1, L_0x2c01a70, L_0x2c01940, C4<1>, C4<1>; +L_0x2c01bf0 .delay (10000,10000,10000) L_0x2c01bf0/d; +L_0x2c01d00/d .functor NOT 1, L_0x2c01bf0, C4<0>, C4<0>, C4<0>; +L_0x2c01d00 .delay (10000,10000,10000) L_0x2c01d00/d; +v0x2483ae0_0 .net "A", 0 0, L_0x2c017a0; 1 drivers +v0x2483b80_0 .net "AnandB", 0 0, L_0x2c01a70; 1 drivers +v0x248c720_0 .net "AnorB", 0 0, L_0x2c00470; 1 drivers +v0x248c7a0_0 .net "AorB", 0 0, L_0x2c01940; 1 drivers +v0x248c470_0 .net "AxorB", 0 0, L_0x2c01d00; 1 drivers +v0x248c4f0_0 .net "B", 0 0, L_0x2c01840; 1 drivers +v0x248a8a0_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x248a920_0 .net "OrNorXorOut", 0 0, L_0x2c02700; 1 drivers +v0x248a640_0 .net "XorNor", 0 0, L_0x2c02180; 1 drivers +v0x248a6c0_0 .net "nXor", 0 0, L_0x2c01bf0; 1 drivers +L_0x2c02300 .part v0x2960210_0, 2, 1; +L_0x2c028d0 .part v0x2960210_0, 0, 1; +S_0x2487800 .scope module, "mux0" "TwoInMux" 3 184, 3 109, S_0x247a290; + .timescale -9 -12; +L_0x2c01e60/d .functor NOT 1, L_0x2c02300, C4<0>, C4<0>, C4<0>; +L_0x2c01e60 .delay (10000,10000,10000) L_0x2c01e60/d; +L_0x2c01f20/d .functor AND 1, L_0x2c01d00, L_0x2c01e60, C4<1>, C4<1>; +L_0x2c01f20 .delay (20000,20000,20000) L_0x2c01f20/d; +L_0x2c02030/d .functor AND 1, L_0x2c00470, L_0x2c02300, C4<1>, C4<1>; +L_0x2c02030 .delay (20000,20000,20000) L_0x2c02030/d; +L_0x2c02180/d .functor OR 1, L_0x2c01f20, L_0x2c02030, C4<0>, C4<0>; +L_0x2c02180 .delay (20000,20000,20000) L_0x2c02180/d; +v0x2487b30_0 .net "S", 0 0, L_0x2c02300; 1 drivers +v0x2485c30_0 .alias "in0", 0 0, v0x248c470_0; +v0x2485cb0_0 .alias "in1", 0 0, v0x248c720_0; +v0x24859d0_0 .net "nS", 0 0, L_0x2c01e60; 1 drivers +v0x2485a50_0 .net "out0", 0 0, L_0x2c01f20; 1 drivers +v0x2485720_0 .net "out1", 0 0, L_0x2c02030; 1 drivers +v0x24857c0_0 .alias "outfinal", 0 0, v0x248a640_0; +S_0x2482e40 .scope module, "mux1" "TwoInMux" 3 185, 3 109, S_0x247a290; + .timescale -9 -12; +L_0x2c023a0/d .functor NOT 1, L_0x2c028d0, C4<0>, C4<0>, C4<0>; +L_0x2c023a0 .delay (10000,10000,10000) L_0x2c023a0/d; +L_0x2c02460/d .functor AND 1, L_0x2c02180, L_0x2c023a0, C4<1>, C4<1>; +L_0x2c02460 .delay (20000,20000,20000) L_0x2c02460/d; +L_0x2c025b0/d .functor AND 1, L_0x2c01940, L_0x2c028d0, C4<1>, C4<1>; +L_0x2c025b0 .delay (20000,20000,20000) L_0x2c025b0/d; +L_0x2c02700/d .functor OR 1, L_0x2c02460, L_0x2c025b0, C4<0>, C4<0>; +L_0x2c02700 .delay (20000,20000,20000) L_0x2c02700/d; +v0x2482b90_0 .net "S", 0 0, L_0x2c028d0; 1 drivers +v0x2482c10_0 .alias "in0", 0 0, v0x248a640_0; +v0x2480fb0_0 .alias "in1", 0 0, v0x248c7a0_0; +v0x2481030_0 .net "nS", 0 0, L_0x2c023a0; 1 drivers +v0x2480d50_0 .net "out0", 0 0, L_0x2c02460; 1 drivers +v0x2480dd0_0 .net "out1", 0 0, L_0x2c025b0; 1 drivers +v0x2487ab0_0 .alias "outfinal", 0 0, v0x248a920_0; +S_0x246dba0 .scope generate, "orbits[19]" "orbits[19]" 3 258, 3 258, S_0x2340a70; + .timescale -9 -12; +P_0x250a908 .param/l "i" 3 258, +C4<010011>; +S_0x246d8f0 .scope module, "attempt" "OrNorXor" 3 260, 3 165, S_0x246dba0; + .timescale -9 -12; +L_0x2c018e0/d .functor NOR 1, L_0x2c03d30, L_0x2c02a10, C4<0>, C4<0>; +L_0x2c018e0 .delay (10000,10000,10000) L_0x2c018e0/d; +L_0x2c02c60/d .functor NOT 1, L_0x2c018e0, C4<0>, C4<0>, C4<0>; +L_0x2c02c60 .delay (10000,10000,10000) L_0x2c02c60/d; +L_0x2c02d90/d .functor NAND 1, L_0x2c03d30, L_0x2c02a10, C4<1>, C4<1>; +L_0x2c02d90 .delay (10000,10000,10000) L_0x2c02d90/d; +L_0x2c02f10/d .functor NAND 1, L_0x2c02d90, L_0x2c02c60, C4<1>, C4<1>; +L_0x2c02f10 .delay (10000,10000,10000) L_0x2c02f10/d; +L_0x2c03020/d .functor NOT 1, L_0x2c02f10, C4<0>, C4<0>, C4<0>; +L_0x2c03020 .delay (10000,10000,10000) L_0x2c03020/d; +v0x2477270_0 .net "A", 0 0, L_0x2c03d30; 1 drivers +v0x2477310_0 .net "AnandB", 0 0, L_0x2c02d90; 1 drivers +v0x24755e0_0 .net "AnorB", 0 0, L_0x2c018e0; 1 drivers +v0x2475660_0 .net "AorB", 0 0, L_0x2c02c60; 1 drivers +v0x247e2a0_0 .net "AxorB", 0 0, L_0x2c03020; 1 drivers +v0x247e320_0 .net "B", 0 0, L_0x2c02a10; 1 drivers +v0x247dff0_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x247e070_0 .net "OrNorXorOut", 0 0, L_0x2c03a20; 1 drivers +v0x247c1d0_0 .net "XorNor", 0 0, L_0x2c034a0; 1 drivers +v0x247c250_0 .net "nXor", 0 0, L_0x2c02f10; 1 drivers +L_0x2c03620 .part v0x2960210_0, 2, 1; +L_0x2c03bf0 .part v0x2960210_0, 0, 1; +S_0x2470930 .scope module, "mux0" "TwoInMux" 3 184, 3 109, S_0x246d8f0; + .timescale -9 -12; +L_0x2c03180/d .functor NOT 1, L_0x2c03620, C4<0>, C4<0>, C4<0>; +L_0x2c03180 .delay (10000,10000,10000) L_0x2c03180/d; +L_0x2c03240/d .functor AND 1, L_0x2c03020, L_0x2c03180, C4<1>, C4<1>; +L_0x2c03240 .delay (20000,20000,20000) L_0x2c03240/d; +L_0x2c03350/d .functor AND 1, L_0x2c018e0, L_0x2c03620, C4<1>, C4<1>; +L_0x2c03350 .delay (20000,20000,20000) L_0x2c03350/d; +L_0x2c034a0/d .functor OR 1, L_0x2c03240, L_0x2c03350, C4<0>, C4<0>; +L_0x2c034a0 .delay (20000,20000,20000) L_0x2c034a0/d; +v0x2472640_0 .net "S", 0 0, L_0x2c03620; 1 drivers +v0x24795f0_0 .alias "in0", 0 0, v0x247e2a0_0; +v0x2479670_0 .alias "in1", 0 0, v0x24755e0_0; +v0x2479340_0 .net "nS", 0 0, L_0x2c03180; 1 drivers +v0x24793c0_0 .net "out0", 0 0, L_0x2c03240; 1 drivers +v0x2477520_0 .net "out1", 0 0, L_0x2c03350; 1 drivers +v0x24775c0_0 .alias "outfinal", 0 0, v0x247c1d0_0; +S_0x246bcb0 .scope module, "mux1" "TwoInMux" 3 185, 3 109, S_0x246d8f0; + .timescale -9 -12; +L_0x2c036c0/d .functor NOT 1, L_0x2c03bf0, C4<0>, C4<0>, C4<0>; +L_0x2c036c0 .delay (10000,10000,10000) L_0x2c036c0/d; +L_0x2c03780/d .functor AND 1, L_0x2c034a0, L_0x2c036c0, C4<1>, C4<1>; +L_0x2c03780 .delay (20000,20000,20000) L_0x2c03780/d; +L_0x2c038d0/d .functor AND 1, L_0x2c02c60, L_0x2c03bf0, C4<1>, C4<1>; +L_0x2c038d0 .delay (20000,20000,20000) L_0x2c038d0/d; +L_0x2c03a20/d .functor OR 1, L_0x2c03780, L_0x2c038d0, C4<0>, C4<0>; +L_0x2c03a20 .delay (20000,20000,20000) L_0x2c03a20/d; +v0x2474940_0 .net "S", 0 0, L_0x2c03bf0; 1 drivers +v0x24749c0_0 .alias "in0", 0 0, v0x247c1d0_0; +v0x2474690_0 .alias "in1", 0 0, v0x2475660_0; +v0x2474710_0 .net "nS", 0 0, L_0x2c036c0; 1 drivers +v0x2472870_0 .net "out0", 0 0, L_0x2c03780; 1 drivers +v0x24728f0_0 .net "out1", 0 0, L_0x2c038d0; 1 drivers +v0x24725c0_0 .alias "outfinal", 0 0, v0x247e070_0; +S_0x245d830 .scope generate, "orbits[20]" "orbits[20]" 3 258, 3 258, S_0x2340a70; + .timescale -9 -12; +P_0x24ff298 .param/l "i" 3 258, +C4<010100>; +S_0x24663a0 .scope module, "attempt" "OrNorXor" 3 260, 3 165, S_0x245d830; + .timescale -9 -12; +L_0x2c02ab0/d .functor NOR 1, L_0x2c03dd0, L_0x2c03e70, C4<0>, C4<0>; +L_0x2c02ab0 .delay (10000,10000,10000) L_0x2c02ab0/d; +L_0x2c03fa0/d .functor NOT 1, L_0x2c02ab0, C4<0>, C4<0>, C4<0>; +L_0x2c03fa0 .delay (10000,10000,10000) L_0x2c03fa0/d; +L_0x2c040b0/d .functor NAND 1, L_0x2c03dd0, L_0x2c03e70, C4<1>, C4<1>; +L_0x2c040b0 .delay (10000,10000,10000) L_0x2c040b0/d; +L_0x2c04230/d .functor NAND 1, L_0x2c040b0, L_0x2c03fa0, C4<1>, C4<1>; +L_0x2c04230 .delay (10000,10000,10000) L_0x2c04230/d; +L_0x2c04340/d .functor NOT 1, L_0x2c04230, C4<0>, C4<0>, C4<0>; +L_0x2c04340 .delay (10000,10000,10000) L_0x2c04340/d; +v0x2468c80_0 .net "A", 0 0, L_0x2c03dd0; 1 drivers +v0x2468d20_0 .net "AnandB", 0 0, L_0x2c040b0; 1 drivers +v0x2467040_0 .net "AnorB", 0 0, L_0x2c02ab0; 1 drivers +v0x24670c0_0 .net "AorB", 0 0, L_0x2c03fa0; 1 drivers +v0x246fc90_0 .net "AxorB", 0 0, L_0x2c04340; 1 drivers +v0x246fd10_0 .net "B", 0 0, L_0x2c03e70; 1 drivers +v0x246f9e0_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x246fa60_0 .net "OrNorXorOut", 0 0, L_0x2c04d40; 1 drivers +v0x246de00_0 .net "XorNor", 0 0, L_0x2c047c0; 1 drivers +v0x246de80_0 .net "nXor", 0 0, L_0x2c04230; 1 drivers +L_0x2c04940 .part v0x2960210_0, 2, 1; +L_0x2c04f10 .part v0x2960210_0, 0, 1; +S_0x246b010 .scope module, "mux0" "TwoInMux" 3 184, 3 109, S_0x24663a0; + .timescale -9 -12; +L_0x2c044a0/d .functor NOT 1, L_0x2c04940, C4<0>, C4<0>, C4<0>; +L_0x2c044a0 .delay (10000,10000,10000) L_0x2c044a0/d; +L_0x2c04560/d .functor AND 1, L_0x2c04340, L_0x2c044a0, C4<1>, C4<1>; +L_0x2c04560 .delay (20000,20000,20000) L_0x2c04560/d; +L_0x2c04670/d .functor AND 1, L_0x2c02ab0, L_0x2c04940, C4<1>, C4<1>; +L_0x2c04670 .delay (20000,20000,20000) L_0x2c04670/d; +L_0x2c047c0/d .functor OR 1, L_0x2c04560, L_0x2c04670, C4<0>, C4<0>; +L_0x2c047c0 .delay (20000,20000,20000) L_0x2c047c0/d; +v0x2462450_0 .net "S", 0 0, L_0x2c04940; 1 drivers +v0x246ad60_0 .alias "in0", 0 0, v0x246fc90_0; +v0x246ade0_0 .alias "in1", 0 0, v0x2467040_0; +v0x2469190_0 .net "nS", 0 0, L_0x2c044a0; 1 drivers +v0x2469210_0 .net "out0", 0 0, L_0x2c04560; 1 drivers +v0x2468f30_0 .net "out1", 0 0, L_0x2c04670; 1 drivers +v0x2468fd0_0 .alias "outfinal", 0 0, v0x246de00_0; +S_0x24660f0 .scope module, "mux1" "TwoInMux" 3 185, 3 109, S_0x24663a0; + .timescale -9 -12; +L_0x2c049e0/d .functor NOT 1, L_0x2c04f10, C4<0>, C4<0>, C4<0>; +L_0x2c049e0 .delay (10000,10000,10000) L_0x2c049e0/d; +L_0x2c04aa0/d .functor AND 1, L_0x2c047c0, L_0x2c049e0, C4<1>, C4<1>; +L_0x2c04aa0 .delay (20000,20000,20000) L_0x2c04aa0/d; +L_0x2c04bf0/d .functor AND 1, L_0x2c03fa0, L_0x2c04f10, C4<1>, C4<1>; +L_0x2c04bf0 .delay (20000,20000,20000) L_0x2c04bf0/d; +L_0x2c04d40/d .functor OR 1, L_0x2c04aa0, L_0x2c04bf0, C4<0>, C4<0>; +L_0x2c04d40 .delay (20000,20000,20000) L_0x2c04d40/d; +v0x2464520_0 .net "S", 0 0, L_0x2c04f10; 1 drivers +v0x24645a0_0 .alias "in0", 0 0, v0x246de00_0; +v0x24642c0_0 .alias "in1", 0 0, v0x24670c0_0; +v0x2464340_0 .net "nS", 0 0, L_0x2c049e0; 1 drivers +v0x2464010_0 .net "out0", 0 0, L_0x2c04aa0; 1 drivers +v0x2464090_0 .net "out1", 0 0, L_0x2c04bf0; 1 drivers +v0x24623d0_0 .alias "outfinal", 0 0, v0x246fa60_0; +S_0x2450eb0 .scope generate, "orbits[21]" "orbits[21]" 3 258, 3 258, S_0x2340a70; + .timescale -9 -12; +P_0x24bd178 .param/l "i" 3 258, +C4<010101>; +S_0x244f220 .scope module, "attempt" "OrNorXor" 3 260, 3 165, S_0x2450eb0; + .timescale -9 -12; +L_0x2c03f10/d .functor NOR 1, L_0x2c06380, L_0x2c05050, C4<0>, C4<0>; +L_0x2c03f10 .delay (10000,10000,10000) L_0x2c03f10/d; +L_0x2c052d0/d .functor NOT 1, L_0x2c03f10, C4<0>, C4<0>, C4<0>; +L_0x2c052d0 .delay (10000,10000,10000) L_0x2c052d0/d; +L_0x2c053e0/d .functor NAND 1, L_0x2c06380, L_0x2c05050, C4<1>, C4<1>; +L_0x2c053e0 .delay (10000,10000,10000) L_0x2c053e0/d; +L_0x2c05560/d .functor NAND 1, L_0x2c053e0, L_0x2c052d0, C4<1>, C4<1>; +L_0x2c05560 .delay (10000,10000,10000) L_0x2c05560/d; +L_0x2c05670/d .functor NOT 1, L_0x2c05560, C4<0>, C4<0>, C4<0>; +L_0x2c05670 .delay (10000,10000,10000) L_0x2c05670/d; +v0x2458b80_0 .net "A", 0 0, L_0x2c06380; 1 drivers +v0x2458c20_0 .net "AnandB", 0 0, L_0x2c053e0; 1 drivers +v0x2461730_0 .net "AnorB", 0 0, L_0x2c03f10; 1 drivers +v0x24617b0_0 .net "AorB", 0 0, L_0x2c052d0; 1 drivers +v0x2461480_0 .net "AxorB", 0 0, L_0x2c05670; 1 drivers +v0x2461500_0 .net "B", 0 0, L_0x2c05050; 1 drivers +v0x245f8a0_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x245f920_0 .net "OrNorXorOut", 0 0, L_0x2c06070; 1 drivers +v0x245f640_0 .net "XorNor", 0 0, L_0x2c05af0; 1 drivers +v0x245f6c0_0 .net "nXor", 0 0, L_0x2c05560; 1 drivers +L_0x2c05c70 .part v0x2960210_0, 2, 1; +L_0x2c06240 .part v0x2960210_0, 0, 1; +S_0x245cb90 .scope module, "mux0" "TwoInMux" 3 184, 3 109, S_0x244f220; + .timescale -9 -12; +L_0x2c057d0/d .functor NOT 1, L_0x2c05c70, C4<0>, C4<0>, C4<0>; +L_0x2c057d0 .delay (10000,10000,10000) L_0x2c057d0/d; +L_0x2c05890/d .functor AND 1, L_0x2c05670, L_0x2c057d0, C4<1>, C4<1>; +L_0x2c05890 .delay (20000,20000,20000) L_0x2c05890/d; +L_0x2c059a0/d .functor AND 1, L_0x2c03f10, L_0x2c05c70, C4<1>, C4<1>; +L_0x2c059a0 .delay (20000,20000,20000) L_0x2c059a0/d; +L_0x2c05af0/d .functor OR 1, L_0x2c05890, L_0x2c059a0, C4<0>, C4<0>; +L_0x2c05af0 .delay (20000,20000,20000) L_0x2c05af0/d; +v0x2453f50_0 .net "S", 0 0, L_0x2c05c70; 1 drivers +v0x245c8e0_0 .alias "in0", 0 0, v0x2461480_0; +v0x245c960_0 .alias "in1", 0 0, v0x2461730_0; +v0x245aac0_0 .net "nS", 0 0, L_0x2c057d0; 1 drivers +v0x245ab40_0 .net "out0", 0 0, L_0x2c05890; 1 drivers +v0x245a810_0 .net "out1", 0 0, L_0x2c059a0; 1 drivers +v0x245a8b0_0 .alias "outfinal", 0 0, v0x245f640_0; +S_0x2457ee0 .scope module, "mux1" "TwoInMux" 3 185, 3 109, S_0x244f220; + .timescale -9 -12; +L_0x2c05d10/d .functor NOT 1, L_0x2c06240, C4<0>, C4<0>, C4<0>; +L_0x2c05d10 .delay (10000,10000,10000) L_0x2c05d10/d; +L_0x2c05dd0/d .functor AND 1, L_0x2c05af0, L_0x2c05d10, C4<1>, C4<1>; +L_0x2c05dd0 .delay (20000,20000,20000) L_0x2c05dd0/d; +L_0x2c05f20/d .functor AND 1, L_0x2c052d0, L_0x2c06240, C4<1>, C4<1>; +L_0x2c05f20 .delay (20000,20000,20000) L_0x2c05f20/d; +L_0x2c06070/d .functor OR 1, L_0x2c05dd0, L_0x2c05f20, C4<0>, C4<0>; +L_0x2c06070 .delay (20000,20000,20000) L_0x2c06070/d; +v0x2457c30_0 .net "S", 0 0, L_0x2c06240; 1 drivers +v0x2457cb0_0 .alias "in0", 0 0, v0x245f640_0; +v0x2455e10_0 .alias "in1", 0 0, v0x24617b0_0; +v0x2455e90_0 .net "nS", 0 0, L_0x2c05d10; 1 drivers +v0x2455b60_0 .net "out0", 0 0, L_0x2c05dd0; 1 drivers +v0x2455be0_0 .net "out1", 0 0, L_0x2c05f20; 1 drivers +v0x2453ed0_0 .alias "outfinal", 0 0, v0x245f920_0; +S_0x2440cc0 .scope generate, "orbits[22]" "orbits[22]" 3 258, 3 258, S_0x2340a70; + .timescale -9 -12; +P_0x24eaf88 .param/l "i" 3 258, +C4<010110>; +S_0x2449900 .scope module, "attempt" "OrNorXor" 3 260, 3 165, S_0x2440cc0; + .timescale -9 -12; +L_0x2c050f0/d .functor NOR 1, L_0x2c06420, L_0x2c064c0, C4<0>, C4<0>; +L_0x2c050f0 .delay (10000,10000,10000) L_0x2c050f0/d; +L_0x2c051e0/d .functor NOT 1, L_0x2c050f0, C4<0>, C4<0>, C4<0>; +L_0x2c051e0 .delay (10000,10000,10000) L_0x2c051e0/d; +L_0x2c066f0/d .functor NAND 1, L_0x2c06420, L_0x2c064c0, C4<1>, C4<1>; +L_0x2c066f0 .delay (10000,10000,10000) L_0x2c066f0/d; +L_0x2c06870/d .functor NAND 1, L_0x2c066f0, L_0x2c051e0, C4<1>, C4<1>; +L_0x2c06870 .delay (10000,10000,10000) L_0x2c06870/d; +L_0x2c06980/d .functor NOT 1, L_0x2c06870, C4<0>, C4<0>, C4<0>; +L_0x2c06980 .delay (10000,10000,10000) L_0x2c06980/d; +v0x244c1e0_0 .net "A", 0 0, L_0x2c06420; 1 drivers +v0x244c280_0 .net "AnandB", 0 0, L_0x2c066f0; 1 drivers +v0x244a5a0_0 .net "AnorB", 0 0, L_0x2c050f0; 1 drivers +v0x244a620_0 .net "AorB", 0 0, L_0x2c051e0; 1 drivers +v0x2453230_0 .net "AxorB", 0 0, L_0x2c06980; 1 drivers +v0x24532b0_0 .net "B", 0 0, L_0x2c064c0; 1 drivers +v0x2452f80_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x2453000_0 .net "OrNorXorOut", 0 0, L_0x2c07280; 1 drivers +v0x2451160_0 .net "XorNor", 0 0, L_0x2c06e00; 1 drivers +v0x24511e0_0 .net "nXor", 0 0, L_0x2c06870; 1 drivers +L_0x2c06f80 .part v0x2960210_0, 2, 1; +L_0x2c07410 .part v0x2960210_0, 0, 1; +S_0x244e580 .scope module, "mux0" "TwoInMux" 3 184, 3 109, S_0x2449900; + .timescale -9 -12; +L_0x2c06ae0/d .functor NOT 1, L_0x2c06f80, C4<0>, C4<0>, C4<0>; +L_0x2c06ae0 .delay (10000,10000,10000) L_0x2c06ae0/d; +L_0x2c06ba0/d .functor AND 1, L_0x2c06980, L_0x2c06ae0, C4<1>, C4<1>; +L_0x2c06ba0 .delay (20000,20000,20000) L_0x2c06ba0/d; +L_0x2c06cb0/d .functor AND 1, L_0x2c050f0, L_0x2c06f80, C4<1>, C4<1>; +L_0x2c06cb0 .delay (20000,20000,20000) L_0x2c06cb0/d; +L_0x2c06e00/d .functor OR 1, L_0x2c06ba0, L_0x2c06cb0, C4<0>, C4<0>; +L_0x2c06e00 .delay (20000,20000,20000) L_0x2c06e00/d; +v0x24459b0_0 .net "S", 0 0, L_0x2c06f80; 1 drivers +v0x244e2d0_0 .alias "in0", 0 0, v0x2453230_0; +v0x244e350_0 .alias "in1", 0 0, v0x244a5a0_0; +v0x244c6f0_0 .net "nS", 0 0, L_0x2c06ae0; 1 drivers +v0x244c770_0 .net "out0", 0 0, L_0x2c06ba0; 1 drivers +v0x244c490_0 .net "out1", 0 0, L_0x2c06cb0; 1 drivers +v0x244c530_0 .alias "outfinal", 0 0, v0x2451160_0; +S_0x2449650 .scope module, "mux1" "TwoInMux" 3 185, 3 109, S_0x2449900; + .timescale -9 -12; +L_0x2bf1f20/d .functor NOT 1, L_0x2c07410, C4<0>, C4<0>, C4<0>; +L_0x2bf1f20 .delay (10000,10000,10000) L_0x2bf1f20/d; +L_0x2c07020/d .functor AND 1, L_0x2c06e00, L_0x2bf1f20, C4<1>, C4<1>; +L_0x2c07020 .delay (20000,20000,20000) L_0x2c07020/d; +L_0x2c07150/d .functor AND 1, L_0x2c051e0, L_0x2c07410, C4<1>, C4<1>; +L_0x2c07150 .delay (20000,20000,20000) L_0x2c07150/d; +L_0x2c07280/d .functor OR 1, L_0x2c07020, L_0x2c07150, C4<0>, C4<0>; +L_0x2c07280 .delay (20000,20000,20000) L_0x2c07280/d; +v0x2447a80_0 .net "S", 0 0, L_0x2c07410; 1 drivers +v0x2447b00_0 .alias "in0", 0 0, v0x2451160_0; +v0x2447820_0 .alias "in1", 0 0, v0x244a620_0; +v0x24478a0_0 .net "nS", 0 0, L_0x2bf1f20; 1 drivers +v0x2447570_0 .net "out0", 0 0, L_0x2c07020; 1 drivers +v0x24475f0_0 .net "out1", 0 0, L_0x2c07150; 1 drivers +v0x2445930_0 .alias "outfinal", 0 0, v0x2453000_0; +S_0x24344a0 .scope generate, "orbits[23]" "orbits[23]" 3 258, 3 258, S_0x2340a70; + .timescale -9 -12; +P_0x24d6eb8 .param/l "i" 3 258, +C4<010111>; +S_0x2432810 .scope module, "attempt" "OrNorXor" 3 260, 3 165, S_0x24344a0; + .timescale -9 -12; +L_0x2c06560/d .functor NOR 1, L_0x2c08690, L_0x2c07550, C4<0>, C4<0>; +L_0x2c06560 .delay (10000,10000,10000) L_0x2c06560/d; +L_0x2c077c0/d .functor NOT 1, L_0x2c06560, C4<0>, C4<0>, C4<0>; +L_0x2c077c0 .delay (10000,10000,10000) L_0x2c077c0/d; +L_0x2c078b0/d .functor NAND 1, L_0x2c08690, L_0x2c07550, C4<1>, C4<1>; +L_0x2c078b0 .delay (10000,10000,10000) L_0x2c078b0/d; +L_0x2c079f0/d .functor NAND 1, L_0x2c078b0, L_0x2c077c0, C4<1>, C4<1>; +L_0x2c079f0 .delay (10000,10000,10000) L_0x2c079f0/d; +L_0x2c07ae0/d .functor NOT 1, L_0x2c079f0, C4<0>, C4<0>, C4<0>; +L_0x2c07ae0 .delay (10000,10000,10000) L_0x2c07ae0/d; +v0x243c1f0_0 .net "A", 0 0, L_0x2c08690; 1 drivers +v0x2444c90_0 .net "AnandB", 0 0, L_0x2c078b0; 1 drivers +v0x2444d30_0 .net "AnorB", 0 0, L_0x2c06560; 1 drivers +v0x24449e0_0 .net "AorB", 0 0, L_0x2c077c0; 1 drivers +v0x2444a60_0 .net "AxorB", 0 0, L_0x2c07ae0; 1 drivers +v0x2442e10_0 .net "B", 0 0, L_0x2c07550; 1 drivers +v0x2442e90_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x2472170_0 .net "OrNorXorOut", 0 0, L_0x2c083c0; 1 drivers +v0x2442900_0 .net "XorNor", 0 0, L_0x2c07ee0; 1 drivers +v0x2442980_0 .net "nXor", 0 0, L_0x2c079f0; 1 drivers +L_0x2c08020 .part v0x2960210_0, 2, 1; +L_0x2c08550 .part v0x2960210_0, 0, 1; +S_0x24374c0 .scope module, "mux0" "TwoInMux" 3 184, 3 109, S_0x2432810; + .timescale -9 -12; +L_0x2c07c20/d .functor NOT 1, L_0x2c08020, C4<0>, C4<0>, C4<0>; +L_0x2c07c20 .delay (10000,10000,10000) L_0x2c07c20/d; +L_0x2c07cc0/d .functor AND 1, L_0x2c07ae0, L_0x2c07c20, C4<1>, C4<1>; +L_0x2c07cc0 .delay (20000,20000,20000) L_0x2c07cc0/d; +L_0x2c07db0/d .functor AND 1, L_0x2c06560, L_0x2c08020, C4<1>, C4<1>; +L_0x2c07db0 .delay (20000,20000,20000) L_0x2c07db0/d; +L_0x2c07ee0/d .functor OR 1, L_0x2c07cc0, L_0x2c07db0, C4<0>, C4<0>; +L_0x2c07ee0 .delay (20000,20000,20000) L_0x2c07ee0/d; +v0x2440020_0 .net "S", 0 0, L_0x2c08020; 1 drivers +v0x24400a0_0 .alias "in0", 0 0, v0x2444a60_0; +v0x243fd70_0 .alias "in1", 0 0, v0x2444d30_0; +v0x243fe10_0 .net "nS", 0 0, L_0x2c07c20; 1 drivers +v0x243e190_0 .net "out0", 0 0, L_0x2c07cc0; 1 drivers +v0x243e230_0 .net "out1", 0 0, L_0x2c07db0; 1 drivers +v0x243c170_0 .alias "outfinal", 0 0, v0x2442900_0; +S_0x243b4d0 .scope module, "mux1" "TwoInMux" 3 185, 3 109, S_0x2432810; + .timescale -9 -12; +L_0x2c080c0/d .functor NOT 1, L_0x2c08550, C4<0>, C4<0>, C4<0>; +L_0x2c080c0 .delay (10000,10000,10000) L_0x2c080c0/d; +L_0x2c08160/d .functor AND 1, L_0x2c07ee0, L_0x2c080c0, C4<1>, C4<1>; +L_0x2c08160 .delay (20000,20000,20000) L_0x2c08160/d; +L_0x2c08290/d .functor AND 1, L_0x2c077c0, L_0x2c08550, C4<1>, C4<1>; +L_0x2c08290 .delay (20000,20000,20000) L_0x2c08290/d; +L_0x2c083c0/d .functor OR 1, L_0x2c08160, L_0x2c08290, C4<0>, C4<0>; +L_0x2c083c0 .delay (20000,20000,20000) L_0x2c083c0/d; +v0x24347d0_0 .net "S", 0 0, L_0x2c08550; 1 drivers +v0x243b220_0 .alias "in0", 0 0, v0x2442900_0; +v0x243b2a0_0 .alias "in1", 0 0, v0x24449e0_0; +v0x2439400_0 .net "nS", 0 0, L_0x2c080c0; 1 drivers +v0x2439480_0 .net "out0", 0 0, L_0x2c08160; 1 drivers +v0x2439150_0 .net "out1", 0 0, L_0x2c08290; 1 drivers +v0x24391d0_0 .alias "outfinal", 0 0, v0x2472170_0; +S_0x2425ec0 .scope generate, "orbits[24]" "orbits[24]" 3 258, 3 258, S_0x2340a70; + .timescale -9 -12; +P_0x24bde98 .param/l "i" 3 258, +C4<011000>; +S_0x2424280 .scope module, "attempt" "OrNorXor" 3 260, 3 165, S_0x2425ec0; + .timescale -9 -12; +L_0x2c075f0/d .functor NOR 1, L_0x2c08730, L_0x2c087d0, C4<0>, C4<0>; +L_0x2c075f0 .delay (10000,10000,10000) L_0x2c075f0/d; +L_0x2c076e0/d .functor NOT 1, L_0x2c075f0, C4<0>, C4<0>, C4<0>; +L_0x2c076e0 .delay (10000,10000,10000) L_0x2c076e0/d; +L_0x2c089f0/d .functor NAND 1, L_0x2c08730, L_0x2c087d0, C4<1>, C4<1>; +L_0x2c089f0 .delay (10000,10000,10000) L_0x2c089f0/d; +L_0x2c08b30/d .functor NAND 1, L_0x2c089f0, L_0x2c076e0, C4<1>, C4<1>; +L_0x2c08b30 .delay (10000,10000,10000) L_0x2c08b30/d; +L_0x2c08c20/d .functor NOT 1, L_0x2c08b30, C4<0>, C4<0>, C4<0>; +L_0x2c08c20 .delay (10000,10000,10000) L_0x2c08c20/d; +v0x242fb20_0 .net "A", 0 0, L_0x2c08730; 1 drivers +v0x242f7f0_0 .net "AnandB", 0 0, L_0x2c089f0; 1 drivers +v0x242f890_0 .net "AnorB", 0 0, L_0x2c075f0; 1 drivers +v0x242db60_0 .net "AorB", 0 0, L_0x2c076e0; 1 drivers +v0x242dbe0_0 .net "AxorB", 0 0, L_0x2c08c20; 1 drivers +v0x2436820_0 .net "B", 0 0, L_0x2c087d0; 1 drivers +v0x24368a0_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x2436570_0 .net "OrNorXorOut", 0 0, L_0x2c09500; 1 drivers +v0x24365f0_0 .net "XorNor", 0 0, L_0x2c09020; 1 drivers +v0x2434750_0 .net "nXor", 0 0, L_0x2c08b30; 1 drivers +L_0x2c09160 .part v0x2960210_0, 2, 1; +L_0x2c09690 .part v0x2960210_0, 0, 1; +S_0x242ab30 .scope module, "mux0" "TwoInMux" 3 184, 3 109, S_0x2424280; + .timescale -9 -12; +L_0x2c08d60/d .functor NOT 1, L_0x2c09160, C4<0>, C4<0>, C4<0>; +L_0x2c08d60 .delay (10000,10000,10000) L_0x2c08d60/d; +L_0x2c08e00/d .functor AND 1, L_0x2c08c20, L_0x2c08d60, C4<1>, C4<1>; +L_0x2c08e00 .delay (20000,20000,20000) L_0x2c08e00/d; +L_0x2c08ef0/d .functor AND 1, L_0x2c075f0, L_0x2c09160, C4<1>, C4<1>; +L_0x2c08ef0 .delay (20000,20000,20000) L_0x2c08ef0/d; +L_0x2c09020/d .functor OR 1, L_0x2c08e00, L_0x2c08ef0, C4<0>, C4<0>; +L_0x2c09020 .delay (20000,20000,20000) L_0x2c09020/d; +v0x2428ef0_0 .net "S", 0 0, L_0x2c09160; 1 drivers +v0x2428f70_0 .alias "in0", 0 0, v0x242dbe0_0; +v0x2431b70_0 .alias "in1", 0 0, v0x242f890_0; +v0x2431c10_0 .net "nS", 0 0, L_0x2c08d60; 1 drivers +v0x24318c0_0 .net "out0", 0 0, L_0x2c08e00; 1 drivers +v0x2431960_0 .net "out1", 0 0, L_0x2c08ef0; 1 drivers +v0x242faa0_0 .alias "outfinal", 0 0, v0x24365f0_0; +S_0x242cec0 .scope module, "mux1" "TwoInMux" 3 185, 3 109, S_0x2424280; + .timescale -9 -12; +L_0x2c09200/d .functor NOT 1, L_0x2c09690, C4<0>, C4<0>, C4<0>; +L_0x2c09200 .delay (10000,10000,10000) L_0x2c09200/d; +L_0x2c092a0/d .functor AND 1, L_0x2c09020, L_0x2c09200, C4<1>, C4<1>; +L_0x2c092a0 .delay (20000,20000,20000) L_0x2c092a0/d; +L_0x2c093d0/d .functor AND 1, L_0x2c076e0, L_0x2c09690, C4<1>, C4<1>; +L_0x2c093d0 .delay (20000,20000,20000) L_0x2c093d0/d; +L_0x2c09500/d .functor OR 1, L_0x2c092a0, L_0x2c093d0, C4<0>, C4<0>; +L_0x2c09500 .delay (20000,20000,20000) L_0x2c09500/d; +v0x24261f0_0 .net "S", 0 0, L_0x2c09690; 1 drivers +v0x242cc10_0 .alias "in0", 0 0, v0x24365f0_0; +v0x242cc90_0 .alias "in1", 0 0, v0x242db60_0; +v0x242b040_0 .net "nS", 0 0, L_0x2c09200; 1 drivers +v0x242b0c0_0 .net "out0", 0 0, L_0x2c092a0; 1 drivers +v0x242ade0_0 .net "out1", 0 0, L_0x2c093d0; 1 drivers +v0x242ae60_0 .alias "outfinal", 0 0, v0x2436570_0; +S_0x243d930 .scope generate, "orbits[25]" "orbits[25]" 3 258, 3 258, S_0x2340a70; + .timescale -9 -12; +P_0x24daa18 .param/l "i" 3 258, +C4<011001>; +S_0x2438c80 .scope module, "attempt" "OrNorXor" 3 260, 3 165, S_0x243d930; + .timescale -9 -12; +L_0x2c08870/d .functor NOR 1, L_0x2c0a8f0, L_0x2c097d0, C4<0>, C4<0>; +L_0x2c08870 .delay (10000,10000,10000) L_0x2c08870/d; +L_0x2c09a20/d .functor NOT 1, L_0x2c08870, C4<0>, C4<0>, C4<0>; +L_0x2c09a20 .delay (10000,10000,10000) L_0x2c09a20/d; +L_0x2c09b10/d .functor NAND 1, L_0x2c0a8f0, L_0x2c097d0, C4<1>, C4<1>; +L_0x2c09b10 .delay (10000,10000,10000) L_0x2c09b10/d; +L_0x2c09c50/d .functor NAND 1, L_0x2c09b10, L_0x2c09a20, C4<1>, C4<1>; +L_0x2c09c50 .delay (10000,10000,10000) L_0x2c09c50/d; +L_0x2c09d40/d .functor NOT 1, L_0x2c09c50, C4<0>, C4<0>, C4<0>; +L_0x2c09d40 .delay (10000,10000,10000) L_0x2c09d40/d; +v0x24212d0_0 .net "A", 0 0, L_0x2c0a8f0; 1 drivers +v0x241f610_0 .net "AnandB", 0 0, L_0x2c09b10; 1 drivers +v0x241f6b0_0 .net "AnorB", 0 0, L_0x2c08870; 1 drivers +v0x2428250_0 .net "AorB", 0 0, L_0x2c09a20; 1 drivers +v0x24282d0_0 .net "AxorB", 0 0, L_0x2c09d40; 1 drivers +v0x2427fa0_0 .net "B", 0 0, L_0x2c097d0; 1 drivers +v0x2428020_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x24263d0_0 .net "OrNorXorOut", 0 0, L_0x2c0a620; 1 drivers +v0x2426450_0 .net "XorNor", 0 0, L_0x2c0a140; 1 drivers +v0x2426170_0 .net "nXor", 0 0, L_0x2c09c50; 1 drivers +L_0x2c0a280 .part v0x2960210_0, 2, 1; +L_0x2c0a7b0 .part v0x2960210_0, 0, 1; +S_0x24235e0 .scope module, "mux0" "TwoInMux" 3 184, 3 109, S_0x2438c80; + .timescale -9 -12; +L_0x2c09e80/d .functor NOT 1, L_0x2c0a280, C4<0>, C4<0>, C4<0>; +L_0x2c09e80 .delay (10000,10000,10000) L_0x2c09e80/d; +L_0x2c09f20/d .functor AND 1, L_0x2c09d40, L_0x2c09e80, C4<1>, C4<1>; +L_0x2c09f20 .delay (20000,20000,20000) L_0x2c09f20/d; +L_0x2c0a010/d .functor AND 1, L_0x2c08870, L_0x2c0a280, C4<1>, C4<1>; +L_0x2c0a010 .delay (20000,20000,20000) L_0x2c0a010/d; +L_0x2c0a140/d .functor OR 1, L_0x2c09f20, L_0x2c0a010, C4<0>, C4<0>; +L_0x2c0a140 .delay (20000,20000,20000) L_0x2c0a140/d; +v0x2423330_0 .net "S", 0 0, L_0x2c0a280; 1 drivers +v0x24233b0_0 .alias "in0", 0 0, v0x24282d0_0; +v0x2421760_0 .alias "in1", 0 0, v0x241f6b0_0; +v0x2421800_0 .net "nS", 0 0, L_0x2c09e80; 1 drivers +v0x2421500_0 .net "out0", 0 0, L_0x2c09f20; 1 drivers +v0x24215a0_0 .net "out1", 0 0, L_0x2c0a010; 1 drivers +v0x2421250_0 .alias "outfinal", 0 0, v0x2426450_0; +S_0x24af640 .scope module, "mux1" "TwoInMux" 3 185, 3 109, S_0x2438c80; + .timescale -9 -12; +L_0x2c0a320/d .functor NOT 1, L_0x2c0a7b0, C4<0>, C4<0>, C4<0>; +L_0x2c0a320 .delay (10000,10000,10000) L_0x2c0a320/d; +L_0x2c0a3c0/d .functor AND 1, L_0x2c0a140, L_0x2c0a320, C4<1>, C4<1>; +L_0x2c0a3c0 .delay (20000,20000,20000) L_0x2c0a3c0/d; +L_0x2c0a4f0/d .functor AND 1, L_0x2c09a20, L_0x2c0a7b0, C4<1>, C4<1>; +L_0x2c0a4f0 .delay (20000,20000,20000) L_0x2c0a4f0/d; +L_0x2c0a620/d .functor OR 1, L_0x2c0a3c0, L_0x2c0a4f0, C4<0>, C4<0>; +L_0x2c0a620 .delay (20000,20000,20000) L_0x2c0a620/d; +v0x2441f60_0 .net "S", 0 0, L_0x2c0a7b0; 1 drivers +v0x241e970_0 .alias "in0", 0 0, v0x2426450_0; +v0x241e9f0_0 .alias "in1", 0 0, v0x2428250_0; +v0x241c530_0 .net "nS", 0 0, L_0x2c0a320; 1 drivers +v0x241c5b0_0 .net "out0", 0 0, L_0x2c0a3c0; 1 drivers +v0x241a810_0 .net "out1", 0 0, L_0x2c0a4f0; 1 drivers +v0x241a890_0 .alias "outfinal", 0 0, v0x24263d0_0; +S_0x24687e0 .scope generate, "orbits[26]" "orbits[26]" 3 258, 3 258, S_0x2340a70; + .timescale -9 -12; +P_0x24f46b8 .param/l "i" 3 258, +C4<011010>; +S_0x2468260 .scope module, "attempt" "OrNorXor" 3 260, 3 165, S_0x24687e0; + .timescale -9 -12; +L_0x2c09870/d .functor NOR 1, L_0x2c0a990, L_0x2c0aa30, C4<0>, C4<0>; +L_0x2c09870 .delay (10000,10000,10000) L_0x2c09870/d; +L_0x2c09960/d .functor NOT 1, L_0x2c09870, C4<0>, C4<0>, C4<0>; +L_0x2c09960 .delay (10000,10000,10000) L_0x2c09960/d; +L_0x2c0ac40/d .functor NAND 1, L_0x2c0a990, L_0x2c0aa30, C4<1>, C4<1>; +L_0x2c0ac40 .delay (10000,10000,10000) L_0x2c0ac40/d; +L_0x2c0ad80/d .functor NAND 1, L_0x2c0ac40, L_0x2c09960, C4<1>, C4<1>; +L_0x2c0ad80 .delay (10000,10000,10000) L_0x2c0ad80/d; +L_0x2c0ae70/d .functor NOT 1, L_0x2c0ad80, C4<0>, C4<0>, C4<0>; +L_0x2c0ae70 .delay (10000,10000,10000) L_0x2c0ae70/d; +v0x244b840_0 .net "A", 0 0, L_0x2c0a990; 1 drivers +v0x2420830_0 .net "AnandB", 0 0, L_0x2c0ac40; 1 drivers +v0x24208d0_0 .net "AnorB", 0 0, L_0x2c09870; 1 drivers +v0x24470d0_0 .net "AorB", 0 0, L_0x2c09960; 1 drivers +v0x2447150_0 .net "AxorB", 0 0, L_0x2c0ae70; 1 drivers +v0x2446b50_0 .net "B", 0 0, L_0x2c0aa30; 1 drivers +v0x2446bd0_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x2442460_0 .net "OrNorXorOut", 0 0, L_0x2c0b750; 1 drivers +v0x24424e0_0 .net "XorNor", 0 0, L_0x2c0b270; 1 drivers +v0x2441ee0_0 .net "nXor", 0 0, L_0x2c0ad80; 1 drivers +L_0x2c0b3b0 .part v0x2960210_0, 2, 1; +L_0x2c0b8e0 .part v0x2960210_0, 0, 1; +S_0x2420db0 .scope module, "mux0" "TwoInMux" 3 184, 3 109, S_0x2468260; + .timescale -9 -12; +L_0x2c0afb0/d .functor NOT 1, L_0x2c0b3b0, C4<0>, C4<0>, C4<0>; +L_0x2c0afb0 .delay (10000,10000,10000) L_0x2c0afb0/d; +L_0x2c0b050/d .functor AND 1, L_0x2c0ae70, L_0x2c0afb0, C4<1>, C4<1>; +L_0x2c0b050 .delay (20000,20000,20000) L_0x2c0b050/d; +L_0x2c0b140/d .functor AND 1, L_0x2c09870, L_0x2c0b3b0, C4<1>, C4<1>; +L_0x2c0b140 .delay (20000,20000,20000) L_0x2c0b140/d; +L_0x2c0b270/d .functor OR 1, L_0x2c0b050, L_0x2c0b140, C4<0>, C4<0>; +L_0x2c0b270 .delay (20000,20000,20000) L_0x2c0b270/d; +v0x2455690_0 .net "S", 0 0, L_0x2c0b3b0; 1 drivers +v0x2455710_0 .alias "in0", 0 0, v0x2447150_0; +v0x24509e0_0 .alias "in1", 0 0, v0x24208d0_0; +v0x2450a80_0 .net "nS", 0 0, L_0x2c0afb0; 1 drivers +v0x244bd40_0 .net "out0", 0 0, L_0x2c0b050; 1 drivers +v0x244bde0_0 .net "out1", 0 0, L_0x2c0b140; 1 drivers +v0x244b7c0_0 .alias "outfinal", 0 0, v0x24424e0_0; +S_0x2463b70 .scope module, "mux1" "TwoInMux" 3 185, 3 109, S_0x2468260; + .timescale -9 -12; +L_0x2c0b450/d .functor NOT 1, L_0x2c0b8e0, C4<0>, C4<0>, C4<0>; +L_0x2c0b450 .delay (10000,10000,10000) L_0x2c0b450/d; +L_0x2c0b4f0/d .functor AND 1, L_0x2c0b270, L_0x2c0b450, C4<1>, C4<1>; +L_0x2c0b4f0 .delay (20000,20000,20000) L_0x2c0b4f0/d; +L_0x2c0b620/d .functor AND 1, L_0x2c09960, L_0x2c0b8e0, C4<1>, C4<1>; +L_0x2c0b620 .delay (20000,20000,20000) L_0x2c0b620/d; +L_0x2c0b750/d .functor OR 1, L_0x2c0b4f0, L_0x2c0b620, C4<0>, C4<0>; +L_0x2c0b750 .delay (20000,20000,20000) L_0x2c0b750/d; +v0x246cf50_0 .net "S", 0 0, L_0x2c0b8e0; 1 drivers +v0x24635f0_0 .alias "in0", 0 0, v0x24424e0_0; +v0x2463670_0 .alias "in1", 0 0, v0x24470d0_0; +v0x245ec80_0 .net "nS", 0 0, L_0x2c0b450; 1 drivers +v0x245ed00_0 .net "out0", 0 0, L_0x2c0b4f0; 1 drivers +v0x245a340_0 .net "out1", 0 0, L_0x2c0b620; 1 drivers +v0x245a3c0_0 .alias "outfinal", 0 0, v0x2442460_0; +S_0x2498490 .scope generate, "orbits[27]" "orbits[27]" 3 258, 3 258, S_0x2340a70; + .timescale -9 -12; +P_0x24fffb8 .param/l "i" 3 258, +C4<011011>; +S_0x24937e0 .scope module, "attempt" "OrNorXor" 3 260, 3 165, S_0x2498490; + .timescale -9 -12; +L_0x2c0aad0/d .functor NOR 1, L_0x2c0cc70, L_0x2c0ba20, C4<0>, C4<0>; +L_0x2c0aad0 .delay (10000,10000,10000) L_0x2c0aad0/d; +L_0x2c0bca0/d .functor NOT 1, L_0x2c0aad0, C4<0>, C4<0>, C4<0>; +L_0x2c0bca0 .delay (10000,10000,10000) L_0x2c0bca0/d; +L_0x2c0bd90/d .functor NAND 1, L_0x2c0cc70, L_0x2c0ba20, C4<1>, C4<1>; +L_0x2c0bd90 .delay (10000,10000,10000) L_0x2c0bd90/d; +L_0x2c0bed0/d .functor NAND 1, L_0x2c0bd90, L_0x2c0bca0, C4<1>, C4<1>; +L_0x2c0bed0 .delay (10000,10000,10000) L_0x2c0bed0/d; +L_0x2c0bfc0/d .functor NOT 1, L_0x2c0bed0, C4<0>, C4<0>, C4<0>; +L_0x2c0bfc0 .delay (10000,10000,10000) L_0x2c0bfc0/d; +v0x247ba50_0 .net "A", 0 0, L_0x2c0cc70; 1 drivers +v0x247baf0_0 .net "AnandB", 0 0, L_0x2c0bd90; 1 drivers +v0x24254a0_0 .net "AnorB", 0 0, L_0x2c0aad0; 1 drivers +v0x2425520_0 .net "AorB", 0 0, L_0x2c0bca0; 1 drivers +v0x2476da0_0 .net "AxorB", 0 0, L_0x2c0bfc0; 1 drivers +v0x2476e20_0 .net "B", 0 0, L_0x2c0ba20; 1 drivers +v0x24720f0_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x246d450_0 .net "OrNorXorOut", 0 0, L_0x2c0c960; 1 drivers +v0x246d4d0_0 .net "XorNor", 0 0, L_0x2c0c3e0; 1 drivers +v0x246ced0_0 .net "nXor", 0 0, L_0x2c0bed0; 1 drivers +L_0x2c0c560 .part v0x2960210_0, 2, 1; +L_0x2c0cb30 .part v0x2960210_0, 0, 1; +S_0x2425a20 .scope module, "mux0" "TwoInMux" 3 184, 3 109, S_0x24937e0; + .timescale -9 -12; +L_0x2c0c100/d .functor NOT 1, L_0x2c0c560, C4<0>, C4<0>, C4<0>; +L_0x2c0c100 .delay (10000,10000,10000) L_0x2c0c100/d; +L_0x2c0c1a0/d .functor AND 1, L_0x2c0bfc0, L_0x2c0c100, C4<1>, C4<1>; +L_0x2c0c1a0 .delay (20000,20000,20000) L_0x2c0c1a0/d; +L_0x2c0c290/d .functor AND 1, L_0x2c0aad0, L_0x2c0c560, C4<1>, C4<1>; +L_0x2c0c290 .delay (20000,20000,20000) L_0x2c0c290/d; +L_0x2c0c3e0/d .functor OR 1, L_0x2c0c1a0, L_0x2c0c290, C4<0>, C4<0>; +L_0x2c0c3e0 .delay (20000,20000,20000) L_0x2c0c3e0/d; +v0x24899f0_0 .net "S", 0 0, L_0x2c0c560; 1 drivers +v0x2485280_0 .alias "in0", 0 0, v0x2476da0_0; +v0x2485300_0 .alias "in1", 0 0, v0x24254a0_0; +v0x2484d00_0 .net "nS", 0 0, L_0x2c0c100; 1 drivers +v0x2484d80_0 .net "out0", 0 0, L_0x2c0c1a0; 1 drivers +v0x2480390_0 .net "out1", 0 0, L_0x2c0c290; 1 drivers +v0x2480430_0 .alias "outfinal", 0 0, v0x246d4d0_0; +S_0x241c060 .scope module, "mux1" "TwoInMux" 3 185, 3 109, S_0x24937e0; + .timescale -9 -12; +L_0x2c0c600/d .functor NOT 1, L_0x2c0cb30, C4<0>, C4<0>, C4<0>; +L_0x2c0c600 .delay (10000,10000,10000) L_0x2c0c600/d; +L_0x2c0c6c0/d .functor AND 1, L_0x2c0c3e0, L_0x2c0c600, C4<1>, C4<1>; +L_0x2c0c6c0 .delay (20000,20000,20000) L_0x2c0c6c0/d; +L_0x2c0c810/d .functor AND 1, L_0x2c0bca0, L_0x2c0cb30, C4<1>, C4<1>; +L_0x2c0c810 .delay (20000,20000,20000) L_0x2c0c810/d; +L_0x2c0c960/d .functor OR 1, L_0x2c0c6c0, L_0x2c0c810, C4<0>, C4<0>; +L_0x2c0c960 .delay (20000,20000,20000) L_0x2c0c960/d; +v0x248eb60_0 .net "S", 0 0, L_0x2c0cb30; 1 drivers +v0x248ebe0_0 .alias "in0", 0 0, v0x246d4d0_0; +v0x248e5e0_0 .alias "in1", 0 0, v0x2425520_0; +v0x248e660_0 .net "nS", 0 0, L_0x2c0c600; 1 drivers +v0x2489ef0_0 .net "out0", 0 0, L_0x2c0c6c0; 1 drivers +v0x2489f70_0 .net "out1", 0 0, L_0x2c0c810; 1 drivers +v0x2489970_0 .alias "outfinal", 0 0, v0x246d450_0; +S_0x2433fd0 .scope generate, "orbits[28]" "orbits[28]" 3 258, 3 258, S_0x2340a70; + .timescale -9 -12; +P_0x251ef48 .param/l "i" 3 258, +C4<011100>; +S_0x242f320 .scope module, "attempt" "OrNorXor" 3 260, 3 165, S_0x2433fd0; + .timescale -9 -12; +L_0x2c0bac0/d .functor NOR 1, L_0x2c0cd10, L_0x2c0cdb0, C4<0>, C4<0>; +L_0x2c0bac0 .delay (10000,10000,10000) L_0x2c0bac0/d; +L_0x2c0bbb0/d .functor NOT 1, L_0x2c0bac0, C4<0>, C4<0>, C4<0>; +L_0x2c0bbb0 .delay (10000,10000,10000) L_0x2c0bbb0/d; +L_0x2c0cff0/d .functor NAND 1, L_0x2c0cd10, L_0x2c0cdb0, C4<1>, C4<1>; +L_0x2c0cff0 .delay (10000,10000,10000) L_0x2c0cff0/d; +L_0x2c0d170/d .functor NAND 1, L_0x2c0cff0, L_0x2c0bbb0, C4<1>, C4<1>; +L_0x2c0d170 .delay (10000,10000,10000) L_0x2c0d170/d; +L_0x2c0d280/d .functor NOT 1, L_0x2c0d170, C4<0>, C4<0>, C4<0>; +L_0x2c0d280 .delay (10000,10000,10000) L_0x2c0d280/d; +v0x24a6920_0 .net "A", 0 0, L_0x2c0cd10; 1 drivers +v0x24a69c0_0 .net "AnandB", 0 0, L_0x2c0cff0; 1 drivers +v0x24a63a0_0 .net "AnorB", 0 0, L_0x2c0bac0; 1 drivers +v0x24a6420_0 .net "AorB", 0 0, L_0x2c0bbb0; 1 drivers +v0x24a1cb0_0 .net "AxorB", 0 0, L_0x2c0d280; 1 drivers +v0x24a1d30_0 .net "B", 0 0, L_0x2c0cdb0; 1 drivers +v0x24a1730_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x24a17b0_0 .net "OrNorXorOut", 0 0, L_0x2c0dc80; 1 drivers +v0x249d140_0 .net "XorNor", 0 0, L_0x2c0d700; 1 drivers +v0x249d1c0_0 .net "nXor", 0 0, L_0x2c0d170; 1 drivers +L_0x2c0d880 .part v0x2960210_0, 2, 1; +L_0x2c0de50 .part v0x2960210_0, 0, 1; +S_0x24b0de0 .scope module, "mux0" "TwoInMux" 3 184, 3 109, S_0x242f320; + .timescale -9 -12; +L_0x2c0d3e0/d .functor NOT 1, L_0x2c0d880, C4<0>, C4<0>, C4<0>; +L_0x2c0d3e0 .delay (10000,10000,10000) L_0x2c0d3e0/d; +L_0x2c0d4a0/d .functor AND 1, L_0x2c0d280, L_0x2c0d3e0, C4<1>, C4<1>; +L_0x2c0d4a0 .delay (20000,20000,20000) L_0x2c0d4a0/d; +L_0x2c0d5b0/d .functor AND 1, L_0x2c0bac0, L_0x2c0d880, C4<1>, C4<1>; +L_0x2c0d5b0 .delay (20000,20000,20000) L_0x2c0d5b0/d; +L_0x2c0d700/d .functor OR 1, L_0x2c0d4a0, L_0x2c0d5b0, C4<0>, C4<0>; +L_0x2c0d700 .delay (20000,20000,20000) L_0x2c0d700/d; +v0x24b1320_0 .net "S", 0 0, L_0x2c0d880; 1 drivers +v0x24ab590_0 .alias "in0", 0 0, v0x24a1cb0_0; +v0x24ab610_0 .alias "in1", 0 0, v0x24a63a0_0; +v0x24ab010_0 .net "nS", 0 0, L_0x2c0d3e0; 1 drivers +v0x24ab090_0 .net "out0", 0 0, L_0x2c0d4a0; 1 drivers +v0x242a110_0 .net "out1", 0 0, L_0x2c0d5b0; 1 drivers +v0x242a1b0_0 .alias "outfinal", 0 0, v0x249d140_0; +S_0x24b5160 .scope module, "mux1" "TwoInMux" 3 185, 3 109, S_0x242f320; + .timescale -9 -12; +L_0x2c0d920/d .functor NOT 1, L_0x2c0de50, C4<0>, C4<0>, C4<0>; +L_0x2c0d920 .delay (10000,10000,10000) L_0x2c0d920/d; +L_0x2c0d9e0/d .functor AND 1, L_0x2c0d700, L_0x2c0d920, C4<1>, C4<1>; +L_0x2c0d9e0 .delay (20000,20000,20000) L_0x2c0d9e0/d; +L_0x2c0db30/d .functor AND 1, L_0x2c0bbb0, L_0x2c0de50, C4<1>, C4<1>; +L_0x2c0db30 .delay (20000,20000,20000) L_0x2c0db30/d; +L_0x2c0dc80/d .functor OR 1, L_0x2c0d9e0, L_0x2c0db30, C4<0>, C4<0>; +L_0x2c0dc80 .delay (20000,20000,20000) L_0x2c0dc80/d; +v0x242a690_0 .net "S", 0 0, L_0x2c0de50; 1 drivers +v0x242a710_0 .alias "in0", 0 0, v0x249d140_0; +v0x24b17b0_0 .alias "in1", 0 0, v0x24a6420_0; +v0x24b1830_0 .net "nS", 0 0, L_0x2c0d920; 1 drivers +v0x24b1540_0 .net "out0", 0 0, L_0x2c0d9e0; 1 drivers +v0x24b15c0_0 .net "out1", 0 0, L_0x2c0db30; 1 drivers +v0x24b12a0_0 .alias "outfinal", 0 0, v0x24a17b0_0; +S_0x2359c10 .scope generate, "orbits[29]" "orbits[29]" 3 258, 3 258, S_0x2340a70; + .timescale -9 -12; +P_0x2518288 .param/l "i" 3 258, +C4<011101>; +S_0x235d130 .scope module, "attempt" "OrNorXor" 3 260, 3 165, S_0x2359c10; + .timescale -9 -12; +L_0x2c0ce50/d .functor NOR 1, L_0x2c0f290, L_0x2c0df90, C4<0>, C4<0>; +L_0x2c0ce50 .delay (10000,10000,10000) L_0x2c0ce50/d; +L_0x2c0cf40/d .functor NOT 1, L_0x2c0ce50, C4<0>, C4<0>, C4<0>; +L_0x2c0cf40 .delay (10000,10000,10000) L_0x2c0cf40/d; +L_0x2c0e310/d .functor NAND 1, L_0x2c0f290, L_0x2c0df90, C4<1>, C4<1>; +L_0x2c0e310 .delay (10000,10000,10000) L_0x2c0e310/d; +L_0x2c0e470/d .functor NAND 1, L_0x2c0e310, L_0x2c0cf40, C4<1>, C4<1>; +L_0x2c0e470 .delay (10000,10000,10000) L_0x2c0e470/d; +L_0x2c0e580/d .functor NOT 1, L_0x2c0e470, C4<0>, C4<0>, C4<0>; +L_0x2c0e580 .delay (10000,10000,10000) L_0x2c0e580/d; +v0x2363d20_0 .net "A", 0 0, L_0x2c0f290; 1 drivers +v0x2363da0_0 .net "AnandB", 0 0, L_0x2c0e310; 1 drivers +v0x2362e90_0 .net "AnorB", 0 0, L_0x2c0ce50; 1 drivers +v0x2362f10_0 .net "AorB", 0 0, L_0x2c0cf40; 1 drivers +v0x258c700_0 .net "AxorB", 0 0, L_0x2c0e580; 1 drivers +v0x258c780_0 .net "B", 0 0, L_0x2c0df90; 1 drivers +v0x258b4f0_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x258b570_0 .net "OrNorXorOut", 0 0, L_0x2c0ef80; 1 drivers +v0x2589430_0 .net "XorNor", 0 0, L_0x2c0ea00; 1 drivers +v0x25894b0_0 .net "nXor", 0 0, L_0x2c0e470; 1 drivers +L_0x2c0eb80 .part v0x2960210_0, 2, 1; +L_0x2c0f150 .part v0x2960210_0, 0, 1; +S_0x2361ad0 .scope module, "mux0" "TwoInMux" 3 184, 3 109, S_0x235d130; + .timescale -9 -12; +L_0x2c0e6e0/d .functor NOT 1, L_0x2c0eb80, C4<0>, C4<0>, C4<0>; +L_0x2c0e6e0 .delay (10000,10000,10000) L_0x2c0e6e0/d; +L_0x2c0e7a0/d .functor AND 1, L_0x2c0e580, L_0x2c0e6e0, C4<1>, C4<1>; +L_0x2c0e7a0 .delay (20000,20000,20000) L_0x2c0e7a0/d; +L_0x2c0e8b0/d .functor AND 1, L_0x2c0ce50, L_0x2c0eb80, C4<1>, C4<1>; +L_0x2c0e8b0 .delay (20000,20000,20000) L_0x2c0e8b0/d; +L_0x2c0ea00/d .functor OR 1, L_0x2c0e7a0, L_0x2c0e8b0, C4<0>, C4<0>; +L_0x2c0ea00 .delay (20000,20000,20000) L_0x2c0ea00/d; +v0x235e5b0_0 .net "S", 0 0, L_0x2c0eb80; 1 drivers +v0x2361870_0 .alias "in0", 0 0, v0x258c700_0; +v0x23618f0_0 .alias "in1", 0 0, v0x2362e90_0; +v0x23609e0_0 .net "nS", 0 0, L_0x2c0e6e0; 1 drivers +v0x2360a60_0 .net "out0", 0 0, L_0x2c0e7a0; 1 drivers +v0x2363f80_0 .net "out1", 0 0, L_0x2c0e8b0; 1 drivers +v0x2364000_0 .alias "outfinal", 0 0, v0x2589430_0; +S_0x235ced0 .scope module, "mux1" "TwoInMux" 3 185, 3 109, S_0x235d130; + .timescale -9 -12; +L_0x2c0ec20/d .functor NOT 1, L_0x2c0f150, C4<0>, C4<0>, C4<0>; +L_0x2c0ec20 .delay (10000,10000,10000) L_0x2c0ec20/d; +L_0x2c0ece0/d .functor AND 1, L_0x2c0ea00, L_0x2c0ec20, C4<1>, C4<1>; +L_0x2c0ece0 .delay (20000,20000,20000) L_0x2c0ece0/d; +L_0x2c0ee30/d .functor AND 1, L_0x2c0cf40, L_0x2c0f150, C4<1>, C4<1>; +L_0x2c0ee30 .delay (20000,20000,20000) L_0x2c0ee30/d; +L_0x2c0ef80/d .functor OR 1, L_0x2c0ece0, L_0x2c0ee30, C4<0>, C4<0>; +L_0x2c0ef80 .delay (20000,20000,20000) L_0x2c0ef80/d; +v0x235c070_0 .net "S", 0 0, L_0x2c0f150; 1 drivers +v0x235c0f0_0 .alias "in0", 0 0, v0x2589430_0; +v0x235f620_0 .alias "in1", 0 0, v0x2362f10_0; +v0x235f6a0_0 .net "nS", 0 0, L_0x2c0ec20; 1 drivers +v0x235f3c0_0 .net "out0", 0 0, L_0x2c0ece0; 1 drivers +v0x235f440_0 .net "out1", 0 0, L_0x2c0ee30; 1 drivers +v0x235e530_0 .alias "outfinal", 0 0, v0x258b570_0; +S_0x234f490 .scope generate, "orbits[30]" "orbits[30]" 3 258, 3 258, S_0x2340a70; + .timescale -9 -12; +P_0x2538ca8 .param/l "i" 3 258, +C4<011110>; +S_0x234e630 .scope module, "attempt" "OrNorXor" 3 260, 3 165, S_0x234f490; + .timescale -9 -12; +L_0x2c0e030/d .functor NOR 1, L_0x2c0f330, L_0x2c0f3d0, C4<0>, C4<0>; +L_0x2c0e030 .delay (10000,10000,10000) L_0x2c0e030/d; +L_0x2c0e120/d .functor NOT 1, L_0x2c0e030, C4<0>, C4<0>, C4<0>; +L_0x2c0e120 .delay (10000,10000,10000) L_0x2c0e120/d; +L_0x2c0e1e0/d .functor NAND 1, L_0x2c0f330, L_0x2c0f3d0, C4<1>, C4<1>; +L_0x2c0e1e0 .delay (10000,10000,10000) L_0x2c0e1e0/d; +L_0x2c0f780/d .functor NAND 1, L_0x2c0e1e0, L_0x2c0e120, C4<1>, C4<1>; +L_0x2c0f780 .delay (10000,10000,10000) L_0x2c0f780/d; +L_0x2c0f890/d .functor NOT 1, L_0x2c0f780, C4<0>, C4<0>, C4<0>; +L_0x2c0f890 .delay (10000,10000,10000) L_0x2c0f890/d; +v0x2358870_0 .net "A", 0 0, L_0x2c0f330; 1 drivers +v0x2358910_0 .net "AnandB", 0 0, L_0x2c0e1e0; 1 drivers +v0x2358610_0 .net "AnorB", 0 0, L_0x2c0e030; 1 drivers +v0x2358690_0 .net "AorB", 0 0, L_0x2c0e120; 1 drivers +v0x23577b0_0 .net "AxorB", 0 0, L_0x2c0f890; 1 drivers +v0x2357830_0 .net "B", 0 0, L_0x2c0f3d0; 1 drivers +v0x235acd0_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x235ad50_0 .net "OrNorXorOut", 0 0, L_0x2c10290; 1 drivers +v0x235aa70_0 .net "XorNor", 0 0, L_0x2c0fd10; 1 drivers +v0x235aaf0_0 .net "nXor", 0 0, L_0x2c0f780; 1 drivers +L_0x2c0fe90 .part v0x2960210_0, 2, 1; +L_0x2c10460 .part v0x2960210_0, 0, 1; +S_0x2352ef0 .scope module, "mux0" "TwoInMux" 3 184, 3 109, S_0x234e630; + .timescale -9 -12; +L_0x2c0f9f0/d .functor NOT 1, L_0x2c0fe90, C4<0>, C4<0>, C4<0>; +L_0x2c0f9f0 .delay (10000,10000,10000) L_0x2c0f9f0/d; +L_0x2c0fab0/d .functor AND 1, L_0x2c0f890, L_0x2c0f9f0, C4<1>, C4<1>; +L_0x2c0fab0 .delay (20000,20000,20000) L_0x2c0fab0/d; +L_0x2c0fbc0/d .functor AND 1, L_0x2c0e030, L_0x2c0fe90, C4<1>, C4<1>; +L_0x2c0fbc0 .delay (20000,20000,20000) L_0x2c0fbc0/d; +L_0x2c0fd10/d .functor OR 1, L_0x2c0fab0, L_0x2c0fbc0, C4<0>, C4<0>; +L_0x2c0fd10 .delay (20000,20000,20000) L_0x2c0fd10/d; +v0x2353dd0_0 .net "S", 0 0, L_0x2c0fe90; 1 drivers +v0x2356410_0 .alias "in0", 0 0, v0x23577b0_0; +v0x2356490_0 .alias "in1", 0 0, v0x2358610_0; +v0x23561b0_0 .net "nS", 0 0, L_0x2c0f9f0; 1 drivers +v0x2356230_0 .net "out0", 0 0, L_0x2c0fab0; 1 drivers +v0x2355350_0 .net "out1", 0 0, L_0x2c0fbc0; 1 drivers +v0x23553f0_0 .alias "outfinal", 0 0, v0x235aa70_0; +S_0x2351b50 .scope module, "mux1" "TwoInMux" 3 185, 3 109, S_0x234e630; + .timescale -9 -12; +L_0x2c0ff30/d .functor NOT 1, L_0x2c10460, C4<0>, C4<0>, C4<0>; +L_0x2c0ff30 .delay (10000,10000,10000) L_0x2c0ff30/d; +L_0x2c0fff0/d .functor AND 1, L_0x2c0fd10, L_0x2c0ff30, C4<1>, C4<1>; +L_0x2c0fff0 .delay (20000,20000,20000) L_0x2c0fff0/d; +L_0x2c10140/d .functor AND 1, L_0x2c0e120, L_0x2c10460, C4<1>, C4<1>; +L_0x2c10140 .delay (20000,20000,20000) L_0x2c10140/d; +L_0x2c10290/d .functor OR 1, L_0x2c0fff0, L_0x2c10140, C4<0>, C4<0>; +L_0x2c10290 .delay (20000,20000,20000) L_0x2c10290/d; +v0x23518f0_0 .net "S", 0 0, L_0x2c10460; 1 drivers +v0x2351970_0 .alias "in0", 0 0, v0x235aa70_0; +v0x2350a90_0 .alias "in1", 0 0, v0x2358690_0; +v0x2350b10_0 .net "nS", 0 0, L_0x2c0ff30; 1 drivers +v0x2353fb0_0 .net "out0", 0 0, L_0x2c0fff0; 1 drivers +v0x2354030_0 .net "out1", 0 0, L_0x2c10140; 1 drivers +v0x2353d50_0 .alias "outfinal", 0 0, v0x235ad50_0; +S_0x2344010 .scope generate, "orbits[31]" "orbits[31]" 3 258, 3 258, S_0x2340a70; + .timescale -9 -12; +P_0x238c3b8 .param/l "i" 3 258, +C4<011111>; +S_0x2343db0 .scope module, "attempt" "OrNorXor" 3 260, 3 165, S_0x2344010; + .timescale -9 -12; +L_0x2c0f470/d .functor NOR 1, L_0x2c118d0, L_0x2c105a0, C4<0>, C4<0>; +L_0x2c0f470 .delay (10000,10000,10000) L_0x2c0f470/d; +L_0x2c0f560/d .functor NOT 1, L_0x2c0f470, C4<0>, C4<0>, C4<0>; +L_0x2c0f560 .delay (10000,10000,10000) L_0x2c0f560/d; +L_0x2c10930/d .functor NAND 1, L_0x2c118d0, L_0x2c105a0, C4<1>, C4<1>; +L_0x2c10930 .delay (10000,10000,10000) L_0x2c10930/d; +L_0x2c10a90/d .functor NAND 1, L_0x2c10930, L_0x2c0f560, C4<1>, C4<1>; +L_0x2c10a90 .delay (10000,10000,10000) L_0x2c10a90/d; +L_0x2c10ba0/d .functor NOT 1, L_0x2c10a90, C4<0>, C4<0>, C4<0>; +L_0x2c10ba0 .delay (10000,10000,10000) L_0x2c10ba0/d; +v0x2349d30_0 .net "A", 0 0, L_0x2c118d0; 1 drivers +v0x2349dd0_0 .net "AnandB", 0 0, L_0x2c10930; 1 drivers +v0x234d2d0_0 .net "AnorB", 0 0, L_0x2c0f470; 1 drivers +v0x234d350_0 .net "AorB", 0 0, L_0x2c0f560; 1 drivers +v0x234d070_0 .net "AxorB", 0 0, L_0x2c10ba0; 1 drivers +v0x234d0f0_0 .net "B", 0 0, L_0x2c105a0; 1 drivers +v0x234c1e0_0 .alias "Command", 2 0, v0x295f7a0_0; +v0x234c260_0 .net "OrNorXorOut", 0 0, L_0x2c115c0; 1 drivers +v0x234f6f0_0 .net "XorNor", 0 0, L_0x2c11020; 1 drivers +v0x234f770_0 .net "nXor", 0 0, L_0x2c10a90; 1 drivers +L_0x2c111a0 .part v0x2960210_0, 2, 1; +L_0x2c11790 .part v0x2960210_0, 0, 1; +S_0x2348710 .scope module, "mux0" "TwoInMux" 3 184, 3 109, S_0x2343db0; + .timescale -9 -12; +L_0x2c10d00/d .functor NOT 1, L_0x2c111a0, C4<0>, C4<0>, C4<0>; +L_0x2c10d00 .delay (10000,10000,10000) L_0x2c10d00/d; +L_0x2c10dc0/d .functor AND 1, L_0x2c10ba0, L_0x2c10d00, C4<1>, C4<1>; +L_0x2c10dc0 .delay (20000,20000,20000) L_0x2c10dc0/d; +L_0x2c10ed0/d .functor AND 1, L_0x2c0f470, L_0x2c111a0, C4<1>, C4<1>; +L_0x2c10ed0 .delay (20000,20000,20000) L_0x2c10ed0/d; +L_0x2c11020/d .functor OR 1, L_0x2c10dc0, L_0x2c10ed0, C4<0>, C4<0>; +L_0x2c11020 .delay (20000,20000,20000) L_0x2c11020/d; +v0x2348a10_0 .net "S", 0 0, L_0x2c111a0; 1 drivers +v0x2347880_0 .alias "in0", 0 0, v0x234d070_0; +v0x2347900_0 .alias "in1", 0 0, v0x234d2d0_0; +v0x234ae20_0 .net "nS", 0 0, L_0x2c10d00; 1 drivers +v0x234aec0_0 .net "out0", 0 0, L_0x2c10dc0; 1 drivers +v0x234abc0_0 .net "out1", 0 0, L_0x2c10ed0; 1 drivers +v0x234ac40_0 .alias "outfinal", 0 0, v0x234f6f0_0; +S_0x2342f20 .scope module, "mux1" "TwoInMux" 3 185, 3 109, S_0x2343db0; + .timescale -9 -12; +L_0x2c11240/d .functor NOT 1, L_0x2c11790, C4<0>, C4<0>, C4<0>; +L_0x2c11240 .delay (10000,10000,10000) L_0x2c11240/d; +L_0x2c11300/d .functor AND 1, L_0x2c11020, L_0x2c11240, C4<1>, C4<1>; +L_0x2c11300 .delay (20000,20000,20000) L_0x2c11300/d; +L_0x2c11450/d .functor AND 1, L_0x2c0f560, L_0x2c11790, C4<1>, C4<1>; +L_0x2c11450 .delay (20000,20000,20000) L_0x2c11450/d; +L_0x2c115c0/d .functor OR 1, L_0x2c11300, L_0x2c11450, C4<0>, C4<0>; +L_0x2c115c0 .delay (20000,20000,20000) L_0x2c115c0/d; +v0x23464c0_0 .net "S", 0 0, L_0x2c11790; 1 drivers +v0x2346560_0 .alias "in0", 0 0, v0x234f6f0_0; +v0x2346260_0 .alias "in1", 0 0, v0x234d350_0; +v0x2346300_0 .net "nS", 0 0, L_0x2c11240; 1 drivers +v0x23453d0_0 .net "out0", 0 0, L_0x2c11300; 1 drivers +v0x2345470_0 .net "out1", 0 0, L_0x2c11450; 1 drivers +v0x2348970_0 .alias "outfinal", 0 0, v0x234c260_0; +S_0x233d1c0 .scope module, "ZeroMux0case" "FourInMux" 3 57, 3 125, S_0x1f6b890; + .timescale -9 -12; +L_0x2c11ab0/d .functor NOT 1, L_0x2b65aa0, C4<0>, C4<0>, C4<0>; +L_0x2c11ab0 .delay (10000,10000,10000) L_0x2c11ab0/d; +L_0x2c11b50/d .functor NOT 1, L_0x2b65bd0, C4<0>, C4<0>, C4<0>; +L_0x2c11b50 .delay (10000,10000,10000) L_0x2c11b50/d; +L_0x2c12ed0/d .functor NAND 1, L_0x2c11ab0, L_0x2c11b50, L_0x2b65d00, C4<1>; +L_0x2c12ed0 .delay (10000,10000,10000) L_0x2c12ed0/d; +L_0x2c12fc0/d .functor NAND 1, L_0x2b65aa0, L_0x2c11b50, L_0x2b65da0, C4<1>; +L_0x2c12fc0 .delay (10000,10000,10000) L_0x2c12fc0/d; +L_0x2c130b0/d .functor NAND 1, L_0x2c11ab0, L_0x2b65bd0, L_0x2b65e40, C4<1>; +L_0x2c130b0 .delay (10000,10000,10000) L_0x2c130b0/d; +L_0x2c131a0/d .functor NAND 1, L_0x2b65aa0, L_0x2b65bd0, L_0x2b65f30, C4<1>; +L_0x2c131a0 .delay (10000,10000,10000) L_0x2c131a0/d; +L_0x2c13280/d .functor NAND 1, L_0x2c12ed0, L_0x2c12fc0, L_0x2c130b0, L_0x2c131a0; +L_0x2c13280 .delay (10000,10000,10000) L_0x2c13280/d; +v0x233cf60_0 .net "S0", 0 0, L_0x2b65aa0; 1 drivers +v0x233c100_0 .net "S1", 0 0, L_0x2b65bd0; 1 drivers +v0x233c1a0_0 .net "in0", 0 0, L_0x2b65d00; 1 drivers +v0x233f6b0_0 .net "in1", 0 0, L_0x2b65da0; 1 drivers +v0x233f730_0 .net "in2", 0 0, L_0x2b65e40; 1 drivers +v0x233f450_0 .net "in3", 0 0, L_0x2b65f30; 1 drivers +v0x233f4f0_0 .net "nS0", 0 0, L_0x2c11ab0; 1 drivers +v0x233e5c0_0 .net "nS1", 0 0, L_0x2c11b50; 1 drivers +v0x233e640_0 .net "out", 0 0, L_0x2c13280; 1 drivers +v0x2341b60_0 .net "out0", 0 0, L_0x2c12ed0; 1 drivers +v0x2341c00_0 .net "out1", 0 0, L_0x2c12fc0; 1 drivers +v0x2341900_0 .net "out2", 0 0, L_0x2c130b0; 1 drivers +v0x2341980_0 .net "out3", 0 0, L_0x2c131a0; 1 drivers +S_0x2336240 .scope module, "OneMux0case" "FourInMux" 3 58, 3 125, S_0x1f6b890; + .timescale -9 -12; +L_0x2b66020/d .functor NOT 1, L_0x2b667d0, C4<0>, C4<0>, C4<0>; +L_0x2b66020 .delay (10000,10000,10000) L_0x2b66020/d; +L_0x2b660d0/d .functor NOT 1, L_0x2b66900, C4<0>, C4<0>, C4<0>; +L_0x2b660d0 .delay (10000,10000,10000) L_0x2b660d0/d; +L_0x2b66150/d .functor NAND 1, L_0x2b66020, L_0x2b660d0, L_0x2b66a30, C4<1>; +L_0x2b66150 .delay (10000,10000,10000) L_0x2b66150/d; +L_0x2b66290/d .functor NAND 1, L_0x2b667d0, L_0x2b660d0, L_0x2b66ad0, C4<1>; +L_0x2b66290 .delay (10000,10000,10000) L_0x2b66290/d; +L_0x2b66380/d .functor NAND 1, L_0x2b66020, L_0x2b66900, L_0x2b66b70, C4<1>; +L_0x2b66380 .delay (10000,10000,10000) L_0x2b66380/d; +L_0x2b66470/d .functor NAND 1, L_0x2b667d0, L_0x2b66900, L_0x2b66c60, C4<1>; +L_0x2b66470 .delay (10000,10000,10000) L_0x2b66470/d; +L_0x2b66550/d .functor NAND 1, L_0x2b66150, L_0x2b66290, L_0x2b66380, L_0x2b66470; +L_0x2b66550 .delay (10000,10000,10000) L_0x2b66550/d; +v0x23353e0_0 .net "S0", 0 0, L_0x2b667d0; 1 drivers +v0x2338900_0 .net "S1", 0 0, L_0x2b66900; 1 drivers +v0x23389a0_0 .net "in0", 0 0, L_0x2b66a30; 1 drivers +v0x23386a0_0 .net "in1", 0 0, L_0x2b66ad0; 1 drivers +v0x2338720_0 .net "in2", 0 0, L_0x2b66b70; 1 drivers +v0x2337840_0 .net "in3", 0 0, L_0x2b66c60; 1 drivers +v0x23378e0_0 .net "nS0", 0 0, L_0x2b66020; 1 drivers +v0x233ad60_0 .net "nS1", 0 0, L_0x2b660d0; 1 drivers +v0x233ade0_0 .net "out", 0 0, L_0x2b66550; 1 drivers +v0x233ab00_0 .net "out0", 0 0, L_0x2b66150; 1 drivers +v0x233aba0_0 .net "out1", 0 0, L_0x2b66290; 1 drivers +v0x2339ca0_0 .net "out2", 0 0, L_0x2b66380; 1 drivers +v0x2339d20_0 .net "out3", 0 0, L_0x2b66470; 1 drivers +S_0x2334040 .scope module, "TwoMux0case" "TwoInMux" 3 59, 3 109, S_0x1f6b890; + .timescale -9 -12; +L_0x2b66d50/d .functor NOT 1, L_0x2b3fbf0, C4<0>, C4<0>, C4<0>; +L_0x2b66d50 .delay (10000,10000,10000) L_0x2b66d50/d; +L_0x2b66e00/d .functor AND 1, L_0x2b3fc90, L_0x2b66d50, C4<1>, C4<1>; +L_0x2b66e00 .delay (20000,20000,20000) L_0x2b66e00/d; +L_0x2b4c6a0/d .functor AND 1, L_0x2b3fd80, L_0x2b3fbf0, C4<1>, C4<1>; +L_0x2b4c6a0 .delay (20000,20000,20000) L_0x2b4c6a0/d; +L_0x2b4c790/d .functor OR 1, L_0x2b66e00, L_0x2b4c6a0, C4<0>, C4<0>; +L_0x2b4c790 .delay (20000,20000,20000) L_0x2b4c790/d; +v0x2330bc0_0 .net "S", 0 0, L_0x2b3fbf0; 1 drivers +v0x2333de0_0 .net "in0", 0 0, L_0x2b3fc90; 1 drivers +v0x2333e60_0 .net "in1", 0 0, L_0x2b3fd80; 1 drivers +v0x2332f80_0 .net "nS", 0 0, L_0x2b66d50; 1 drivers +v0x2333020_0 .net "out0", 0 0, L_0x2b66e00; 1 drivers +v0x23364a0_0 .net "out1", 0 0, L_0x2b4c6a0; 1 drivers +v0x2336520_0 .net "outfinal", 0 0, L_0x2b4c790; 1 drivers +S_0x2321990 .scope generate, "muxbits[1]" "muxbits[1]" 3 64, 3 64, S_0x1f6b890; + .timescale -9 -12; +P_0x25e4918 .param/l "i" 3 64, +C4<01>; +L_0x2b19860/d .functor OR 1, L_0x2b19d90, L_0x2b19b70, C4<0>, C4<0>; +L_0x2b19860 .delay (20000,20000,20000) L_0x2b19860/d; +v0x2331980_0 .net *"_s15", 0 0, L_0x2b19d90; 1 drivers +v0x2330b20_0 .net *"_s16", 0 0, L_0x2b19b70; 1 drivers +S_0x2329dc0 .scope module, "ZeroMux" "FourInMux" 3 66, 3 125, S_0x2321990; + .timescale -9 -12; +L_0x2b153e0/d .functor NOT 1, L_0x2b17ce0, C4<0>, C4<0>, C4<0>; +L_0x2b153e0 .delay (10000,10000,10000) L_0x2b153e0/d; +L_0x2b15480/d .functor NOT 1, L_0x2b17e10, C4<0>, C4<0>, C4<0>; +L_0x2b15480 .delay (10000,10000,10000) L_0x2b15480/d; +L_0x2b15520/d .functor NAND 1, L_0x2b153e0, L_0x2b15480, L_0x2b17f40, C4<1>; +L_0x2b15520 .delay (10000,10000,10000) L_0x2b15520/d; +L_0x2b15660/d .functor NAND 1, L_0x2b17ce0, L_0x2b15480, L_0x2b17fe0, C4<1>; +L_0x2b15660 .delay (10000,10000,10000) L_0x2b15660/d; +L_0x2b15750/d .functor NAND 1, L_0x2b153e0, L_0x2b17e10, L_0x2b180d0, C4<1>; +L_0x2b15750 .delay (10000,10000,10000) L_0x2b15750/d; +L_0x2b17920/d .functor NAND 1, L_0x2b17ce0, L_0x2b17e10, L_0x2b18250, C4<1>; +L_0x2b17920 .delay (10000,10000,10000) L_0x2b17920/d; +L_0x2b17a30/d .functor NAND 1, L_0x2b15520, L_0x2b15660, L_0x2b15750, L_0x2b17920; +L_0x2b17a30 .delay (10000,10000,10000) L_0x2b17a30/d; +v0x232d360_0 .net "S0", 0 0, L_0x2b17ce0; 1 drivers +v0x232d100_0 .net "S1", 0 0, L_0x2b17e10; 1 drivers +v0x232d1a0_0 .net "in0", 0 0, L_0x2b17f40; 1 drivers +v0x232c270_0 .net "in1", 0 0, L_0x2b17fe0; 1 drivers +v0x232c2f0_0 .net "in2", 0 0, L_0x2b180d0; 1 drivers +v0x232f780_0 .net "in3", 0 0, L_0x2b18250; 1 drivers +v0x232f820_0 .net "nS0", 0 0, L_0x2b153e0; 1 drivers +v0x232f520_0 .net "nS1", 0 0, L_0x2b15480; 1 drivers +v0x232f5a0_0 .net "out", 0 0, L_0x2b17a30; 1 drivers +v0x232e6c0_0 .net "out0", 0 0, L_0x2b15520; 1 drivers +v0x232e760_0 .net "out1", 0 0, L_0x2b15660; 1 drivers +v0x2331be0_0 .net "out2", 0 0, L_0x2b15750; 1 drivers +v0x2331c60_0 .net "out3", 0 0, L_0x2b17920; 1 drivers +S_0x2326550 .scope module, "OneMux" "FourInMux" 3 67, 3 125, S_0x2321990; + .timescale -9 -12; +L_0x2b18390/d .functor NOT 1, L_0x2b18c50, C4<0>, C4<0>, C4<0>; +L_0x2b18390 .delay (10000,10000,10000) L_0x2b18390/d; +L_0x2b18480/d .functor NOT 1, L_0x2b18d80, C4<0>, C4<0>, C4<0>; +L_0x2b18480 .delay (10000,10000,10000) L_0x2b18480/d; +L_0x2b18520/d .functor NAND 1, L_0x2b18390, L_0x2b18480, L_0x2b18f10, C4<1>; +L_0x2b18520 .delay (10000,10000,10000) L_0x2b18520/d; +L_0x2b18660/d .functor NAND 1, L_0x2b18c50, L_0x2b18480, L_0x2b18fb0, C4<1>; +L_0x2b18660 .delay (10000,10000,10000) L_0x2b18660/d; +L_0x2b18750/d .functor NAND 1, L_0x2b18390, L_0x2b18d80, L_0x2b190c0, C4<1>; +L_0x2b18750 .delay (10000,10000,10000) L_0x2b18750/d; +L_0x2b18840/d .functor NAND 1, L_0x2b18c50, L_0x2b18d80, L_0x2b191b0, C4<1>; +L_0x2b18840 .delay (10000,10000,10000) L_0x2b18840/d; +L_0x2b18950/d .functor NAND 1, L_0x2b18520, L_0x2b18660, L_0x2b18750, L_0x2b18840; +L_0x2b18950 .delay (10000,10000,10000) L_0x2b18950/d; +v0x23262f0_0 .net "S0", 0 0, L_0x2b18c50; 1 drivers +v0x2325460_0 .net "S1", 0 0, L_0x2b18d80; 1 drivers +v0x2325500_0 .net "in0", 0 0, L_0x2b18f10; 1 drivers +v0x2328a00_0 .net "in1", 0 0, L_0x2b18fb0; 1 drivers +v0x2328a80_0 .net "in2", 0 0, L_0x2b190c0; 1 drivers +v0x23287a0_0 .net "in3", 0 0, L_0x2b191b0; 1 drivers +v0x2328840_0 .net "nS0", 0 0, L_0x2b18390; 1 drivers +v0x2327910_0 .net "nS1", 0 0, L_0x2b18480; 1 drivers +v0x2327990_0 .net "out", 0 0, L_0x2b18950; 1 drivers +v0x232aeb0_0 .net "out0", 0 0, L_0x2b18520; 1 drivers +v0x232af50_0 .net "out1", 0 0, L_0x2b18660; 1 drivers +v0x232ac50_0 .net "out2", 0 0, L_0x2b18750; 1 drivers +v0x232acd0_0 .net "out3", 0 0, L_0x2b18840; 1 drivers +S_0x2320b00 .scope module, "TwoMux" "TwoInMux" 3 68, 3 109, S_0x2321990; + .timescale -9 -12; +L_0x2b18eb0/d .functor NOT 1, L_0x2b197c0, C4<0>, C4<0>, C4<0>; +L_0x2b18eb0 .delay (10000,10000,10000) L_0x2b18eb0/d; +L_0x2b193b0/d .functor AND 1, L_0x2b198f0, L_0x2b18eb0, C4<1>, C4<1>; +L_0x2b193b0 .delay (20000,20000,20000) L_0x2b193b0/d; +L_0x2b194a0/d .functor AND 1, L_0x2b19a30, L_0x2b197c0, C4<1>, C4<1>; +L_0x2b194a0 .delay (20000,20000,20000) L_0x2b194a0/d; +L_0x2b19590/d .functor OR 1, L_0x2b193b0, L_0x2b194a0, C4<0>, C4<0>; +L_0x2b19590 .delay (20000,20000,20000) L_0x2b19590/d; +v0x2321c90_0 .net "S", 0 0, L_0x2b197c0; 1 drivers +v0x23240a0_0 .net "in0", 0 0, L_0x2b198f0; 1 drivers +v0x2324140_0 .net "in1", 0 0, L_0x2b19a30; 1 drivers +v0x2323e40_0 .net "nS", 0 0, L_0x2b18eb0; 1 drivers +v0x2323ec0_0 .net "out0", 0 0, L_0x2b193b0; 1 drivers +v0x2322fb0_0 .net "out1", 0 0, L_0x2b194a0; 1 drivers +v0x2323030_0 .net "outfinal", 0 0, L_0x2b19590; 1 drivers +S_0x2314c20 .scope generate, "muxbits[2]" "muxbits[2]" 3 64, 3 64, S_0x1f6b890; + .timescale -9 -12; +P_0x26478f8 .param/l "i" 3 64, +C4<010>; +L_0x2b1bca0/d .functor OR 1, L_0x2b1c4b0, L_0x2b1c7e0, C4<0>, C4<0>; +L_0x2b1bca0 .delay (20000,20000,20000) L_0x2b1bca0/d; +v0x231e5b0_0 .net *"_s15", 0 0, L_0x2b1c4b0; 1 drivers +v0x2321bf0_0 .net *"_s16", 0 0, L_0x2b1c7e0; 1 drivers +S_0x231bcc0 .scope module, "ZeroMux" "FourInMux" 3 66, 3 125, S_0x2314c20; + .timescale -9 -12; +L_0x2b19f80/d .functor NOT 1, L_0x2b19e80, C4<0>, C4<0>, C4<0>; +L_0x2b19f80 .delay (10000,10000,10000) L_0x2b19f80/d; +L_0x2b1a070/d .functor NOT 1, L_0x2b1a8e0, C4<0>, C4<0>, C4<0>; +L_0x2b1a070 .delay (10000,10000,10000) L_0x2b1a070/d; +L_0x2b1a110/d .functor NAND 1, L_0x2b19f80, L_0x2b1a070, L_0x2b1a790, C4<1>; +L_0x2b1a110 .delay (10000,10000,10000) L_0x2b1a110/d; +L_0x2b1a250/d .functor NAND 1, L_0x2b19e80, L_0x2b1a070, L_0x2b1ab70, C4<1>; +L_0x2b1a250 .delay (10000,10000,10000) L_0x2b1a250/d; +L_0x2b1a340/d .functor NAND 1, L_0x2b19f80, L_0x2b1a8e0, L_0x2b1aa10, C4<1>; +L_0x2b1a340 .delay (10000,10000,10000) L_0x2b1a340/d; +L_0x2b1a430/d .functor NAND 1, L_0x2b19e80, L_0x2b1a8e0, L_0x2b1acf0, C4<1>; +L_0x2b1a430 .delay (10000,10000,10000) L_0x2b1a430/d; +L_0x2b1a510/d .functor NAND 1, L_0x2b1a110, L_0x2b1a250, L_0x2b1a340, L_0x2b1a430; +L_0x2b1a510 .delay (10000,10000,10000) L_0x2b1a510/d; +v0x231ba60_0 .net "S0", 0 0, L_0x2b19e80; 1 drivers +v0x231b5c0_0 .net "S1", 0 0, L_0x2b1a8e0; 1 drivers +v0x231b660_0 .net "in0", 0 0, L_0x2b1a790; 1 drivers +v0x2366410_0 .net "in1", 0 0, L_0x2b1ab70; 1 drivers +v0x2366490_0 .net "in2", 0 0, L_0x2b1aa10; 1 drivers +v0x23661c0_0 .net "in3", 0 0, L_0x2b1acf0; 1 drivers +v0x2366260_0 .net "nS0", 0 0, L_0x2b19f80; 1 drivers +v0x2365340_0 .net "nS1", 0 0, L_0x2b1a070; 1 drivers +v0x23653c0_0 .net "out", 0 0, L_0x2b1a510; 1 drivers +v0x231f6d0_0 .net "out0", 0 0, L_0x2b1a110; 1 drivers +v0x231f770_0 .net "out1", 0 0, L_0x2b1a250; 1 drivers +v0x231f440_0 .net "out2", 0 0, L_0x2b1a340; 1 drivers +v0x231f4c0_0 .net "out3", 0 0, L_0x2b1a430; 1 drivers +S_0x2317b00 .scope module, "OneMux" "FourInMux" 3 67, 3 125, S_0x2314c20; + .timescale -9 -12; +L_0x2b1ac10/d .functor NOT 1, L_0x2b1b660, C4<0>, C4<0>, C4<0>; +L_0x2b1ac10 .delay (10000,10000,10000) L_0x2b1ac10/d; +L_0x2b1af20/d .functor NOT 1, L_0x2b1ade0, C4<0>, C4<0>, C4<0>; +L_0x2b1af20 .delay (10000,10000,10000) L_0x2b1af20/d; +L_0x2b1af80/d .functor NAND 1, L_0x2b1ac10, L_0x2b1af20, L_0x2b1b920, C4<1>; +L_0x2b1af80 .delay (10000,10000,10000) L_0x2b1af80/d; +L_0x2b1b0c0/d .functor NAND 1, L_0x2b1b660, L_0x2b1af20, L_0x2b1b790, C4<1>; +L_0x2b1b0c0 .delay (10000,10000,10000) L_0x2b1b0c0/d; +L_0x2b1b1b0/d .functor NAND 1, L_0x2b1ac10, L_0x2b1ade0, L_0x2b1bb60, C4<1>; +L_0x2b1b1b0 .delay (10000,10000,10000) L_0x2b1b1b0/d; +L_0x2b1b2a0/d .functor NAND 1, L_0x2b1b660, L_0x2b1ade0, L_0x2b1ba50, C4<1>; +L_0x2b1b2a0 .delay (10000,10000,10000) L_0x2b1b2a0/d; +L_0x2b1b3b0/d .functor NAND 1, L_0x2b1af80, L_0x2b1b0c0, L_0x2b1b1b0, L_0x2b1b2a0; +L_0x2b1b3b0 .delay (10000,10000,10000) L_0x2b1b3b0/d; +v0x2317660_0 .net "S0", 0 0, L_0x2b1b660; 1 drivers +v0x2319280_0 .net "S1", 0 0, L_0x2b1ade0; 1 drivers +v0x2319320_0 .net "in0", 0 0, L_0x2b1b920; 1 drivers +v0x2319020_0 .net "in1", 0 0, L_0x2b1b790; 1 drivers +v0x23190a0_0 .net "in2", 0 0, L_0x2b1bb60; 1 drivers +v0x2318b80_0 .net "in3", 0 0, L_0x2b1ba50; 1 drivers +v0x2318c20_0 .net "nS0", 0 0, L_0x2b1ac10; 1 drivers +v0x231a7a0_0 .net "nS1", 0 0, L_0x2b1af20; 1 drivers +v0x231a820_0 .net "out", 0 0, L_0x2b1b3b0; 1 drivers +v0x231a540_0 .net "out0", 0 0, L_0x2b1af80; 1 drivers +v0x231a5e0_0 .net "out1", 0 0, L_0x2b1b0c0; 1 drivers +v0x231a0a0_0 .net "out2", 0 0, L_0x2b1b1b0; 1 drivers +v0x231a120_0 .net "out3", 0 0, L_0x2b1b2a0; 1 drivers +S_0x2316840 .scope module, "TwoMux" "TwoInMux" 3 68, 3 109, S_0x2314c20; + .timescale -9 -12; +L_0x2b1b830/d .functor NOT 1, L_0x2b1bc00, C4<0>, C4<0>, C4<0>; +L_0x2b1b830 .delay (10000,10000,10000) L_0x2b1b830/d; +L_0x2b1bd70/d .functor AND 1, L_0x2b1c2f0, L_0x2b1b830, C4<1>, C4<1>; +L_0x2b1bd70 .delay (20000,20000,20000) L_0x2b1bd70/d; +L_0x2b1be60/d .functor AND 1, L_0x2b1c1c0, L_0x2b1bc00, C4<1>, C4<1>; +L_0x2b1be60 .delay (20000,20000,20000) L_0x2b1be60/d; +L_0x2b1bf50/d .functor OR 1, L_0x2b1bd70, L_0x2b1be60, C4<0>, C4<0>; +L_0x2b1bf50 .delay (20000,20000,20000) L_0x2b1bf50/d; +v0x2315160_0 .net "S", 0 0, L_0x2b1bc00; 1 drivers +v0x23165e0_0 .net "in0", 0 0, L_0x2b1c2f0; 1 drivers +v0x2316680_0 .net "in1", 0 0, L_0x2b1c1c0; 1 drivers +v0x2316140_0 .net "nS", 0 0, L_0x2b1b830; 1 drivers +v0x23161c0_0 .net "out0", 0 0, L_0x2b1bd70; 1 drivers +v0x2317d60_0 .net "out1", 0 0, L_0x2b1be60; 1 drivers +v0x2317de0_0 .net "outfinal", 0 0, L_0x2b1bf50; 1 drivers +S_0x230a7a0 .scope generate, "muxbits[3]" "muxbits[3]" 3 64, 3 64, S_0x1f6b890; + .timescale -9 -12; +P_0x26d5948 .param/l "i" 3 64, +C4<011>; +L_0x2b1ec40/d .functor OR 1, L_0x2b1efc0, L_0x2b1edd0, C4<0>, C4<0>; +L_0x2b1ec40 .delay (20000,20000,20000) L_0x2b1ec40/d; +v0x2315320_0 .net *"_s15", 0 0, L_0x2b1efc0; 1 drivers +v0x23150c0_0 .net *"_s16", 0 0, L_0x2b1edd0; 1 drivers +S_0x2311160 .scope module, "ZeroMux" "FourInMux" 3 66, 3 125, S_0x230a7a0; + .timescale -9 -12; +L_0x2b1c600/d .functor NOT 1, L_0x2b1d100, C4<0>, C4<0>, C4<0>; +L_0x2b1c600 .delay (10000,10000,10000) L_0x2b1c600/d; +L_0x2b1c6f0/d .functor NOT 1, L_0x2b1c880, C4<0>, C4<0>, C4<0>; +L_0x2b1c6f0 .delay (10000,10000,10000) L_0x2b1c6f0/d; +L_0x2b1ca20/d .functor NAND 1, L_0x2b1c600, L_0x2b1c6f0, L_0x2b1d3a0, C4<1>; +L_0x2b1ca20 .delay (10000,10000,10000) L_0x2b1ca20/d; +L_0x2b1cb60/d .functor NAND 1, L_0x2b1d100, L_0x2b1c6f0, L_0x2b1d230, C4<1>; +L_0x2b1cb60 .delay (10000,10000,10000) L_0x2b1cb60/d; +L_0x2b1cc50/d .functor NAND 1, L_0x2b1c600, L_0x2b1c880, L_0x2b1d2d0, C4<1>; +L_0x2b1cc50 .delay (10000,10000,10000) L_0x2b1cc50/d; +L_0x2b1cd40/d .functor NAND 1, L_0x2b1d100, L_0x2b1c880, L_0x2b1d440, C4<1>; +L_0x2b1cd40 .delay (10000,10000,10000) L_0x2b1cd40/d; +L_0x2b1ce50/d .functor NAND 1, L_0x2b1ca20, L_0x2b1cb60, L_0x2b1cc50, L_0x2b1cd40; +L_0x2b1ce50 .delay (10000,10000,10000) L_0x2b1ce50/d; +v0x2310cc0_0 .net "S0", 0 0, L_0x2b1d100; 1 drivers +v0x23128e0_0 .net "S1", 0 0, L_0x2b1c880; 1 drivers +v0x2312980_0 .net "in0", 0 0, L_0x2b1d3a0; 1 drivers +v0x2312680_0 .net "in1", 0 0, L_0x2b1d230; 1 drivers +v0x2312700_0 .net "in2", 0 0, L_0x2b1d2d0; 1 drivers +v0x23121e0_0 .net "in3", 0 0, L_0x2b1d440; 1 drivers +v0x2312280_0 .net "nS0", 0 0, L_0x2b1c600; 1 drivers +v0x2313e00_0 .net "nS1", 0 0, L_0x2b1c6f0; 1 drivers +v0x2313e80_0 .net "out", 0 0, L_0x2b1ce50; 1 drivers +v0x2313ba0_0 .net "out0", 0 0, L_0x2b1ca20; 1 drivers +v0x2313c40_0 .net "out1", 0 0, L_0x2b1cb60; 1 drivers +v0x2313700_0 .net "out2", 0 0, L_0x2b1cc50; 1 drivers +v0x2313780_0 .net "out3", 0 0, L_0x2b1cd40; 1 drivers +S_0x230cd60 .scope module, "OneMux" "FourInMux" 3 67, 3 125, S_0x230a7a0; + .timescale -9 -12; +L_0x2b1d530/d .functor NOT 1, L_0x2b1d720, C4<0>, C4<0>, C4<0>; +L_0x2b1d530 .delay (10000,10000,10000) L_0x2b1d530/d; +L_0x2b1d8f0/d .functor NOT 1, L_0x2b1e1e0, C4<0>, C4<0>, C4<0>; +L_0x2b1d8f0 .delay (10000,10000,10000) L_0x2b1d8f0/d; +L_0x2b1d990/d .functor NAND 1, L_0x2b1d530, L_0x2b1d8f0, L_0x2b1e040, C4<1>; +L_0x2b1d990 .delay (10000,10000,10000) L_0x2b1d990/d; +L_0x2b1dad0/d .functor NAND 1, L_0x2b1d720, L_0x2b1d8f0, L_0x2b1e0e0, C4<1>; +L_0x2b1dad0 .delay (10000,10000,10000) L_0x2b1dad0/d; +L_0x2b1dbc0/d .functor NAND 1, L_0x2b1d530, L_0x2b1e1e0, L_0x2b1e4d0, C4<1>; +L_0x2b1dbc0 .delay (10000,10000,10000) L_0x2b1dbc0/d; +L_0x2b1dcb0/d .functor NAND 1, L_0x2b1d720, L_0x2b1e1e0, L_0x2b1e570, C4<1>; +L_0x2b1dcb0 .delay (10000,10000,10000) L_0x2b1dcb0/d; +L_0x2b1dd90/d .functor NAND 1, L_0x2b1d990, L_0x2b1dad0, L_0x2b1dbc0, L_0x2b1dcb0; +L_0x2b1dd90 .delay (10000,10000,10000) L_0x2b1dd90/d; +v0x230e980_0 .net "S0", 0 0, L_0x2b1d720; 1 drivers +v0x230e720_0 .net "S1", 0 0, L_0x2b1e1e0; 1 drivers +v0x230e7c0_0 .net "in0", 0 0, L_0x2b1e040; 1 drivers +v0x230e280_0 .net "in1", 0 0, L_0x2b1e0e0; 1 drivers +v0x230e300_0 .net "in2", 0 0, L_0x2b1e4d0; 1 drivers +v0x230fea0_0 .net "in3", 0 0, L_0x2b1e570; 1 drivers +v0x230ff40_0 .net "nS0", 0 0, L_0x2b1d530; 1 drivers +v0x230fc40_0 .net "nS1", 0 0, L_0x2b1d8f0; 1 drivers +v0x230fcc0_0 .net "out", 0 0, L_0x2b1dd90; 1 drivers +v0x230f7a0_0 .net "out0", 0 0, L_0x2b1d990; 1 drivers +v0x230f840_0 .net "out1", 0 0, L_0x2b1dad0; 1 drivers +v0x23113c0_0 .net "out2", 0 0, L_0x2b1dbc0; 1 drivers +v0x2311440_0 .net "out3", 0 0, L_0x2b1dcb0; 1 drivers +S_0x230bf40 .scope module, "TwoMux" "TwoInMux" 3 68, 3 109, S_0x230a7a0; + .timescale -9 -12; +L_0x2b1e310/d .functor NOT 1, L_0x2b1eb00, C4<0>, C4<0>, C4<0>; +L_0x2b1e310 .delay (10000,10000,10000) L_0x2b1e310/d; +L_0x2b1e400/d .functor AND 1, L_0x2b1e610, L_0x2b1e310, C4<1>, C4<1>; +L_0x2b1e400 .delay (20000,20000,20000) L_0x2b1e400/d; +L_0x2b1e830/d .functor AND 1, L_0x2b1e700, L_0x2b1eb00, C4<1>, C4<1>; +L_0x2b1e830 .delay (20000,20000,20000) L_0x2b1e830/d; +L_0x2b1e920/d .functor OR 1, L_0x2b1e400, L_0x2b1e830, C4<0>, C4<0>; +L_0x2b1e920 .delay (20000,20000,20000) L_0x2b1e920/d; +v0x230aaa0_0 .net "S", 0 0, L_0x2b1eb00; 1 drivers +v0x230bce0_0 .net "in0", 0 0, L_0x2b1e610; 1 drivers +v0x230bd80_0 .net "in1", 0 0, L_0x2b1e700; 1 drivers +v0x230d460_0 .net "nS", 0 0, L_0x2b1e310; 1 drivers +v0x230d4e0_0 .net "out0", 0 0, L_0x2b1e400; 1 drivers +v0x230d200_0 .net "out1", 0 0, L_0x2b1e830; 1 drivers +v0x230d280_0 .net "outfinal", 0 0, L_0x2b1e920; 1 drivers +S_0x22fa460 .scope generate, "muxbits[4]" "muxbits[4]" 3 64, 3 64, S_0x1f6b890; + .timescale -9 -12; +P_0x2651258 .param/l "i" 3 64, +C4<0100>; +L_0x2b214f0/d .functor OR 1, L_0x2b21970, L_0x2b21b20, C4<0>, C4<0>; +L_0x2b214f0 .delay (20000,20000,20000) L_0x2b214f0/d; +v0x2309260_0 .net *"_s15", 0 0, L_0x2b21970; 1 drivers +v0x230aa00_0 .net *"_s16", 0 0, L_0x2b21b20; 1 drivers +S_0x2303d60 .scope module, "ZeroMux" "FourInMux" 3 66, 3 125, S_0x22fa460; + .timescale -9 -12; +L_0x2b1eec0/d .functor NOT 1, L_0x2b1f060, C4<0>, C4<0>, C4<0>; +L_0x2b1eec0 .delay (10000,10000,10000) L_0x2b1eec0/d; +L_0x2b19330/d .functor NOT 1, L_0x2b1f190, C4<0>, C4<0>, C4<0>; +L_0x2b19330 .delay (10000,10000,10000) L_0x2b19330/d; +L_0x2b1ecf0/d .functor NAND 1, L_0x2b1eec0, L_0x2b19330, L_0x2b1f7d0, C4<1>; +L_0x2b1ecf0 .delay (10000,10000,10000) L_0x2b1ecf0/d; +L_0x2b1f2b0/d .functor NAND 1, L_0x2b1f060, L_0x2b19330, L_0x2b1fc90, C4<1>; +L_0x2b1f2b0 .delay (10000,10000,10000) L_0x2b1f2b0/d; +L_0x2b1f360/d .functor NAND 1, L_0x2b1eec0, L_0x2b1f190, L_0x2b1fa70, C4<1>; +L_0x2b1f360 .delay (10000,10000,10000) L_0x2b1f360/d; +L_0x2b1f410/d .functor NAND 1, L_0x2b1f060, L_0x2b1f190, L_0x2b1fb60, C4<1>; +L_0x2b1f410 .delay (10000,10000,10000) L_0x2b1f410/d; +L_0x2b1f520/d .functor NAND 1, L_0x2b1ecf0, L_0x2b1f2b0, L_0x2b1f360, L_0x2b1f410; +L_0x2b1f520 .delay (10000,10000,10000) L_0x2b1f520/d; +v0x2305500_0 .net "S0", 0 0, L_0x2b1f060; 1 drivers +v0x23052a0_0 .net "S1", 0 0, L_0x2b1f190; 1 drivers +v0x2305340_0 .net "in0", 0 0, L_0x2b1f7d0; 1 drivers +v0x2306a40_0 .net "in1", 0 0, L_0x2b1fc90; 1 drivers +v0x2306ac0_0 .net "in2", 0 0, L_0x2b1fa70; 1 drivers +v0x23067e0_0 .net "in3", 0 0, L_0x2b1fb60; 1 drivers +v0x2306880_0 .net "nS0", 0 0, L_0x2b1eec0; 1 drivers +v0x2307f80_0 .net "nS1", 0 0, L_0x2b19330; 1 drivers +v0x2308000_0 .net "out", 0 0, L_0x2b1f520; 1 drivers +v0x2307d20_0 .net "out0", 0 0, L_0x2b1ecf0; 1 drivers +v0x2307dc0_0 .net "out1", 0 0, L_0x2b1f2b0; 1 drivers +v0x23094c0_0 .net "out2", 0 0, L_0x2b1f360; 1 drivers +v0x2309540_0 .net "out3", 0 0, L_0x2b1f410; 1 drivers +S_0x22fe860 .scope module, "OneMux" "FourInMux" 3 67, 3 125, S_0x22fa460; + .timescale -9 -12; +L_0x2b1f980/d .functor NOT 1, L_0x2b206e0, C4<0>, C4<0>, C4<0>; +L_0x2b1f980 .delay (10000,10000,10000) L_0x2b1f980/d; +L_0x2b1ff70/d .functor NOT 1, L_0x2b1fd30, C4<0>, C4<0>, C4<0>; +L_0x2b1ff70 .delay (10000,10000,10000) L_0x2b1ff70/d; +L_0x2b1ffd0/d .functor NAND 1, L_0x2b1f980, L_0x2b1ff70, L_0x2b1fe60, C4<1>; +L_0x2b1ffd0 .delay (10000,10000,10000) L_0x2b1ffd0/d; +L_0x2b20110/d .functor NAND 1, L_0x2b206e0, L_0x2b1ff70, L_0x2b20810, C4<1>; +L_0x2b20110 .delay (10000,10000,10000) L_0x2b20110/d; +L_0x2b20200/d .functor NAND 1, L_0x2b1f980, L_0x2b1fd30, L_0x2b208b0, C4<1>; +L_0x2b20200 .delay (10000,10000,10000) L_0x2b20200/d; +L_0x2b202f0/d .functor NAND 1, L_0x2b206e0, L_0x2b1fd30, L_0x2b209a0, C4<1>; +L_0x2b202f0 .delay (10000,10000,10000) L_0x2b202f0/d; +L_0x2b20430/d .functor NAND 1, L_0x2b1ffd0, L_0x2b20110, L_0x2b20200, L_0x2b202f0; +L_0x2b20430 .delay (10000,10000,10000) L_0x2b20430/d; +v0x2300000_0 .net "S0", 0 0, L_0x2b206e0; 1 drivers +v0x22ffda0_0 .net "S1", 0 0, L_0x2b1fd30; 1 drivers +v0x22ffe40_0 .net "in0", 0 0, L_0x2b1fe60; 1 drivers +v0x2301540_0 .net "in1", 0 0, L_0x2b20810; 1 drivers +v0x23015c0_0 .net "in2", 0 0, L_0x2b208b0; 1 drivers +v0x23012e0_0 .net "in3", 0 0, L_0x2b209a0; 1 drivers +v0x2301380_0 .net "nS0", 0 0, L_0x2b1f980; 1 drivers +v0x2302a80_0 .net "nS1", 0 0, L_0x2b1ff70; 1 drivers +v0x2302b00_0 .net "out", 0 0, L_0x2b20430; 1 drivers +v0x2302820_0 .net "out0", 0 0, L_0x2b1ffd0; 1 drivers +v0x23028c0_0 .net "out1", 0 0, L_0x2b20110; 1 drivers +v0x2303fc0_0 .net "out2", 0 0, L_0x2b20200; 1 drivers +v0x2304040_0 .net "out3", 0 0, L_0x2b202f0; 1 drivers +S_0x22fc040 .scope module, "TwoMux" "TwoInMux" 3 68, 3 109, S_0x22fa460; + .timescale -9 -12; +L_0x2b1b9c0/d .functor NOT 1, L_0x2b20b70, C4<0>, C4<0>, C4<0>; +L_0x2b1b9c0 .delay (10000,10000,10000) L_0x2b1b9c0/d; +L_0x2b20e70/d .functor AND 1, L_0x2b20c10, L_0x2b1b9c0, C4<1>, C4<1>; +L_0x2b20e70 .delay (20000,20000,20000) L_0x2b20e70/d; +L_0x2b20f60/d .functor AND 1, L_0x2b20d00, L_0x2b20b70, C4<1>, C4<1>; +L_0x2b20f60 .delay (20000,20000,20000) L_0x2b20f60/d; +L_0x2b21050/d .functor OR 1, L_0x2b20e70, L_0x2b20f60, C4<0>, C4<0>; +L_0x2b21050 .delay (20000,20000,20000) L_0x2b21050/d; +v0x22fa9a0_0 .net "S", 0 0, L_0x2b20b70; 1 drivers +v0x22fd580_0 .net "in0", 0 0, L_0x2b20c10; 1 drivers +v0x22fd620_0 .net "in1", 0 0, L_0x2b20d00; 1 drivers +v0x22fd320_0 .net "nS", 0 0, L_0x2b1b9c0; 1 drivers +v0x22fd3a0_0 .net "out0", 0 0, L_0x2b20e70; 1 drivers +v0x22feac0_0 .net "out1", 0 0, L_0x2b20f60; 1 drivers +v0x22feb40_0 .net "outfinal", 0 0, L_0x2b21050; 1 drivers +S_0x22d9c70 .scope generate, "muxbits[5]" "muxbits[5]" 3 64, 3 64, S_0x1f6b890; + .timescale -9 -12; +P_0x26a5ce8 .param/l "i" 3 64, +C4<0101>; +L_0x2b23ba0/d .functor OR 1, L_0x2b23ce0, L_0x2b23d80, C4<0>, C4<0>; +L_0x2b23ba0 .delay (20000,20000,20000) L_0x2b23ba0/d; +v0x22fab60_0 .net *"_s15", 0 0, L_0x2b23ce0; 1 drivers +v0x22fa900_0 .net *"_s16", 0 0, L_0x2b23d80; 1 drivers +S_0x22f69a0 .scope module, "ZeroMux" "FourInMux" 3 66, 3 125, S_0x22d9c70; + .timescale -9 -12; +L_0x2b1c750/d .functor NOT 1, L_0x2b22320, C4<0>, C4<0>, C4<0>; +L_0x2b1c750 .delay (10000,10000,10000) L_0x2b1c750/d; +L_0x2b21720/d .functor NOT 1, L_0x2b21bc0, C4<0>, C4<0>, C4<0>; +L_0x2b21720 .delay (10000,10000,10000) L_0x2b21720/d; +L_0x2b21780/d .functor NAND 1, L_0x2b1c750, L_0x2b21720, L_0x2b21cf0, C4<1>; +L_0x2b21780 .delay (10000,10000,10000) L_0x2b21780/d; +L_0x2b21880/d .functor NAND 1, L_0x2b22320, L_0x2b21720, L_0x2b21d90, C4<1>; +L_0x2b21880 .delay (10000,10000,10000) L_0x2b21880/d; +L_0x2b21e70/d .functor NAND 1, L_0x2b1c750, L_0x2b21bc0, L_0x2b22720, C4<1>; +L_0x2b21e70 .delay (10000,10000,10000) L_0x2b21e70/d; +L_0x2b21f60/d .functor NAND 1, L_0x2b22320, L_0x2b21bc0, L_0x2b22450, C4<1>; +L_0x2b21f60 .delay (10000,10000,10000) L_0x2b21f60/d; +L_0x2b22070/d .functor NAND 1, L_0x2b21780, L_0x2b21880, L_0x2b21e70, L_0x2b21f60; +L_0x2b22070 .delay (10000,10000,10000) L_0x2b22070/d; +v0x22f6500_0 .net "S0", 0 0, L_0x2b22320; 1 drivers +v0x22f8120_0 .net "S1", 0 0, L_0x2b21bc0; 1 drivers +v0x22f81c0_0 .net "in0", 0 0, L_0x2b21cf0; 1 drivers +v0x22f7ec0_0 .net "in1", 0 0, L_0x2b21d90; 1 drivers +v0x22f7f40_0 .net "in2", 0 0, L_0x2b22720; 1 drivers +v0x22f7a20_0 .net "in3", 0 0, L_0x2b22450; 1 drivers +v0x22f7ac0_0 .net "nS0", 0 0, L_0x2b1c750; 1 drivers +v0x22f9640_0 .net "nS1", 0 0, L_0x2b21720; 1 drivers +v0x22f96c0_0 .net "out", 0 0, L_0x2b22070; 1 drivers +v0x22f93e0_0 .net "out0", 0 0, L_0x2b21780; 1 drivers +v0x22f9480_0 .net "out1", 0 0, L_0x2b21880; 1 drivers +v0x22f8f40_0 .net "out2", 0 0, L_0x2b21e70; 1 drivers +v0x22f8fc0_0 .net "out3", 0 0, L_0x2b21f60; 1 drivers +S_0x22e9e50 .scope module, "OneMux" "FourInMux" 3 67, 3 125, S_0x22d9c70; + .timescale -9 -12; +L_0x2b22540/d .functor NOT 1, L_0x2b22810, C4<0>, C4<0>, C4<0>; +L_0x2b22540 .delay (10000,10000,10000) L_0x2b22540/d; +L_0x2b225f0/d .functor NOT 1, L_0x2b22940, C4<0>, C4<0>, C4<0>; +L_0x2b225f0 .delay (10000,10000,10000) L_0x2b225f0/d; +L_0x2b22690/d .functor NAND 1, L_0x2b22540, L_0x2b225f0, L_0x2b234a0, C4<1>; +L_0x2b22690 .delay (10000,10000,10000) L_0x2b22690/d; +L_0x2b22bd0/d .functor NAND 1, L_0x2b22810, L_0x2b225f0, L_0x2b23540, C4<1>; +L_0x2b22bd0 .delay (10000,10000,10000) L_0x2b22bd0/d; +L_0x2b22cc0/d .functor NAND 1, L_0x2b22540, L_0x2b22940, L_0x2b231a0, C4<1>; +L_0x2b22cc0 .delay (10000,10000,10000) L_0x2b22cc0/d; +L_0x2b22db0/d .functor NAND 1, L_0x2b22810, L_0x2b22940, L_0x2b23290, C4<1>; +L_0x2b22db0 .delay (10000,10000,10000) L_0x2b22db0/d; +L_0x2b22ef0/d .functor NAND 1, L_0x2b22690, L_0x2b22bd0, L_0x2b22cc0, L_0x2b22db0; +L_0x2b22ef0 .delay (10000,10000,10000) L_0x2b22ef0/d; +v0x22e7dd0_0 .net "S0", 0 0, L_0x2b22810; 1 drivers +v0x231d250_0 .net "S1", 0 0, L_0x2b22940; 1 drivers +v0x231d2f0_0 .net "in0", 0 0, L_0x2b234a0; 1 drivers +v0x231d000_0 .net "in1", 0 0, L_0x2b23540; 1 drivers +v0x231d080_0 .net "in2", 0 0, L_0x2b231a0; 1 drivers +v0x22f3e90_0 .net "in3", 0 0, L_0x2b23290; 1 drivers +v0x22f3f30_0 .net "nS0", 0 0, L_0x2b22540; 1 drivers +v0x22f56e0_0 .net "nS1", 0 0, L_0x2b225f0; 1 drivers +v0x22f5760_0 .net "out", 0 0, L_0x2b22ef0; 1 drivers +v0x22f5480_0 .net "out0", 0 0, L_0x2b22690; 1 drivers +v0x22f5520_0 .net "out1", 0 0, L_0x2b22bd0; 1 drivers +v0x22f6c00_0 .net "out2", 0 0, L_0x2b22cc0; 1 drivers +v0x22f6c80_0 .net "out3", 0 0, L_0x2b22db0; 1 drivers +S_0x22e07b0 .scope module, "TwoMux" "TwoInMux" 3 68, 3 109, S_0x22d9c70; + .timescale -9 -12; +L_0x2b22a70/d .functor NOT 1, L_0x2b23850, C4<0>, C4<0>, C4<0>; +L_0x2b22a70 .delay (10000,10000,10000) L_0x2b22a70/d; +L_0x2b1d6a0/d .functor AND 1, L_0x2b23e30, L_0x2b22a70, C4<1>, C4<1>; +L_0x2b1d6a0 .delay (20000,20000,20000) L_0x2b1d6a0/d; +L_0x2b23410/d .functor AND 1, L_0x2b23f20, L_0x2b23850, C4<1>, C4<1>; +L_0x2b23410 .delay (20000,20000,20000) L_0x2b23410/d; +L_0x2b23670/d .functor OR 1, L_0x2b1d6a0, L_0x2b23410, C4<0>, C4<0>; +L_0x2b23670 .delay (20000,20000,20000) L_0x2b23670/d; +v0x22dbd00_0 .net "S", 0 0, L_0x2b23850; 1 drivers +v0x22de730_0 .net "in0", 0 0, L_0x2b23e30; 1 drivers +v0x22de7d0_0 .net "in1", 0 0, L_0x2b23f20; 1 drivers +v0x22e5300_0 .net "nS", 0 0, L_0x2b22a70; 1 drivers +v0x22e5380_0 .net "out0", 0 0, L_0x2b1d6a0; 1 drivers +v0x22e3280_0 .net "out1", 0 0, L_0x2b23410; 1 drivers +v0x22e3300_0 .net "outfinal", 0 0, L_0x2b23670; 1 drivers +S_0x22b91b0 .scope generate, "muxbits[6]" "muxbits[6]" 3 64, 3 64, S_0x1f6b890; + .timescale -9 -12; +P_0x268f3a8 .param/l "i" 3 64, +C4<0110>; +L_0x2b25f30/d .functor OR 1, L_0x2b26a00, L_0x2b26aa0, C4<0>, C4<0>; +L_0x2b25f30 .delay (20000,20000,20000) L_0x2b25f30/d; +v0x22d5260_0 .net *"_s15", 0 0, L_0x2b26a00; 1 drivers +v0x22dbc60_0 .net *"_s16", 0 0, L_0x2b26aa0; 1 drivers +S_0x22d4330 .scope module, "ZeroMux" "FourInMux" 3 66, 3 125, S_0x22b91b0; + .timescale -9 -12; +L_0x2b243b0/d .functor NOT 1, L_0x2b24010, C4<0>, C4<0>, C4<0>; +L_0x2b243b0 .delay (10000,10000,10000) L_0x2b243b0/d; +L_0x2b244a0/d .functor NOT 1, L_0x2b24140, C4<0>, C4<0>, C4<0>; +L_0x2b244a0 .delay (10000,10000,10000) L_0x2b244a0/d; +L_0x2b24540/d .functor NAND 1, L_0x2b243b0, L_0x2b244a0, L_0x2b24270, C4<1>; +L_0x2b24540 .delay (10000,10000,10000) L_0x2b24540/d; +L_0x2b24680/d .functor NAND 1, L_0x2b24010, L_0x2b244a0, L_0x2b24fc0, C4<1>; +L_0x2b24680 .delay (10000,10000,10000) L_0x2b24680/d; +L_0x2b24770/d .functor NAND 1, L_0x2b243b0, L_0x2b24140, L_0x2b24c50, C4<1>; +L_0x2b24770 .delay (10000,10000,10000) L_0x2b24770/d; +L_0x2b24860/d .functor NAND 1, L_0x2b24010, L_0x2b24140, L_0x2b24cf0, C4<1>; +L_0x2b24860 .delay (10000,10000,10000) L_0x2b24860/d; +L_0x2b249a0/d .functor NAND 1, L_0x2b24540, L_0x2b24680, L_0x2b24770, L_0x2b24860; +L_0x2b249a0 .delay (10000,10000,10000) L_0x2b249a0/d; +v0x22d25f0_0 .net "S0", 0 0, L_0x2b24010; 1 drivers +v0x22d2360_0 .net "S1", 0 0, L_0x2b24140; 1 drivers +v0x22d2400_0 .net "in0", 0 0, L_0x2b24270; 1 drivers +v0x22d0850_0 .net "in1", 0 0, L_0x2b24fc0; 1 drivers +v0x22d08d0_0 .net "in2", 0 0, L_0x2b24c50; 1 drivers +v0x22d8fd0_0 .net "in3", 0 0, L_0x2b24cf0; 1 drivers +v0x22d9070_0 .net "nS0", 0 0, L_0x2b243b0; 1 drivers +v0x22d8d40_0 .net "nS1", 0 0, L_0x2b244a0; 1 drivers +v0x22d8dc0_0 .net "out", 0 0, L_0x2b249a0; 1 drivers +v0x22d7000_0 .net "out0", 0 0, L_0x2b24540; 1 drivers +v0x22d70a0_0 .net "out1", 0 0, L_0x2b24680; 1 drivers +v0x22d6d70_0 .net "out2", 0 0, L_0x2b24770; 1 drivers +v0x22d6df0_0 .net "out3", 0 0, L_0x2b24860; 1 drivers +S_0x22c9370 .scope module, "OneMux" "FourInMux" 3 67, 3 125, S_0x22b91b0; + .timescale -9 -12; +L_0x2b24de0/d .functor NOT 1, L_0x2b25ae0, C4<0>, C4<0>, C4<0>; +L_0x2b24de0 .delay (10000,10000,10000) L_0x2b24de0/d; +L_0x2b24ed0/d .functor NOT 1, L_0x2b25060, C4<0>, C4<0>, C4<0>; +L_0x2b24ed0 .delay (10000,10000,10000) L_0x2b24ed0/d; +L_0x2b253f0/d .functor NAND 1, L_0x2b24de0, L_0x2b24ed0, L_0x2b25190, C4<1>; +L_0x2b253f0 .delay (10000,10000,10000) L_0x2b253f0/d; +L_0x2b254e0/d .functor NAND 1, L_0x2b25ae0, L_0x2b24ed0, L_0x2b25230, C4<1>; +L_0x2b254e0 .delay (10000,10000,10000) L_0x2b254e0/d; +L_0x2b255d0/d .functor NAND 1, L_0x2b24de0, L_0x2b25060, L_0x2b252d0, C4<1>; +L_0x2b255d0 .delay (10000,10000,10000) L_0x2b255d0/d; +L_0x2b256c0/d .functor NAND 1, L_0x2b25ae0, L_0x2b25060, L_0x2b25fd0, C4<1>; +L_0x2b256c0 .delay (10000,10000,10000) L_0x2b256c0/d; +L_0x2b25830/d .functor NAND 1, L_0x2b253f0, L_0x2b254e0, L_0x2b255d0, L_0x2b256c0; +L_0x2b25830 .delay (10000,10000,10000) L_0x2b25830/d; +v0x22c72f0_0 .net "S0", 0 0, L_0x2b25ae0; 1 drivers +v0x22cfbb0_0 .net "S1", 0 0, L_0x2b25060; 1 drivers +v0x22cfc50_0 .net "in0", 0 0, L_0x2b25190; 1 drivers +v0x22cf920_0 .net "in1", 0 0, L_0x2b25230; 1 drivers +v0x22cf9a0_0 .net "in2", 0 0, L_0x2b252d0; 1 drivers +v0x22cdbe0_0 .net "in3", 0 0, L_0x2b25fd0; 1 drivers +v0x22cdc80_0 .net "nS0", 0 0, L_0x2b24de0; 1 drivers +v0x22cd950_0 .net "nS1", 0 0, L_0x2b24ed0; 1 drivers +v0x22cd9d0_0 .net "out", 0 0, L_0x2b25830; 1 drivers +v0x22cbe40_0 .net "out0", 0 0, L_0x2b253f0; 1 drivers +v0x22cbee0_0 .net "out1", 0 0, L_0x2b254e0; 1 drivers +v0x22d45c0_0 .net "out2", 0 0, L_0x2b255d0; 1 drivers +v0x22d4640_0 .net "out3", 0 0, L_0x2b256c0; 1 drivers +S_0x22bfcd0 .scope module, "TwoMux" "TwoInMux" 3 68, 3 109, S_0x22b91b0; + .timescale -9 -12; +L_0x2b260c0/d .functor NOT 1, L_0x2b25c10, C4<0>, C4<0>, C4<0>; +L_0x2b260c0 .delay (10000,10000,10000) L_0x2b260c0/d; +L_0x2b261b0/d .functor AND 1, L_0x2b25cb0, L_0x2b260c0, C4<1>, C4<1>; +L_0x2b261b0 .delay (20000,20000,20000) L_0x2b261b0/d; +L_0x2b262a0/d .functor AND 1, L_0x2b25da0, L_0x2b25c10, C4<1>, C4<1>; +L_0x2b262a0 .delay (20000,20000,20000) L_0x2b262a0/d; +L_0x2b26390/d .functor OR 1, L_0x2b261b0, L_0x2b262a0, C4<0>, C4<0>; +L_0x2b26390 .delay (20000,20000,20000) L_0x2b26390/d; +v0x22bad60_0 .net "S", 0 0, L_0x2b25c10; 1 drivers +v0x22bdc50_0 .net "in0", 0 0, L_0x2b25cb0; 1 drivers +v0x22bdcf0_0 .net "in1", 0 0, L_0x2b25da0; 1 drivers +v0x22c4820_0 .net "nS", 0 0, L_0x2b260c0; 1 drivers +v0x22c48a0_0 .net "out0", 0 0, L_0x2b261b0; 1 drivers +v0x22c27a0_0 .net "out1", 0 0, L_0x2b262a0; 1 drivers +v0x22c2820_0 .net "outfinal", 0 0, L_0x2b26390; 1 drivers +S_0x229d190 .scope generate, "muxbits[7]" "muxbits[7]" 3 64, 3 64, S_0x1f6b890; + .timescale -9 -12; +P_0x264b158 .param/l "i" 3 64, +C4<0111>; +L_0x2b28810/d .functor OR 1, L_0x2b28950, L_0x2b289f0, C4<0>, C4<0>; +L_0x2b28810 .delay (20000,20000,20000) L_0x2b28810/d; +v0x22baf50_0 .net *"_s15", 0 0, L_0x2b28950; 1 drivers +v0x22bacc0_0 .net *"_s16", 0 0, L_0x2b289f0; 1 drivers +S_0x22b18a0 .scope module, "ZeroMux" "FourInMux" 3 66, 3 125, S_0x229d190; + .timescale -9 -12; +L_0x2b248c0/d .functor NOT 1, L_0x2b27350, C4<0>, C4<0>, C4<0>; +L_0x2b248c0 .delay (10000,10000,10000) L_0x2b248c0/d; +L_0x2b265c0/d .functor NOT 1, L_0x2b26b90, C4<0>, C4<0>, C4<0>; +L_0x2b265c0 .delay (10000,10000,10000) L_0x2b265c0/d; +L_0x2b26620/d .functor NAND 1, L_0x2b248c0, L_0x2b265c0, L_0x2b26cc0, C4<1>; +L_0x2b26620 .delay (10000,10000,10000) L_0x2b26620/d; +L_0x2b26720/d .functor NAND 1, L_0x2b27350, L_0x2b265c0, L_0x2b26d60, C4<1>; +L_0x2b26720 .delay (10000,10000,10000) L_0x2b26720/d; +L_0x2b267d0/d .functor NAND 1, L_0x2b248c0, L_0x2b26b90, L_0x2b26e00, C4<1>; +L_0x2b267d0 .delay (10000,10000,10000) L_0x2b267d0/d; +L_0x2b268f0/d .functor NAND 1, L_0x2b27350, L_0x2b26b90, L_0x2b26ef0, C4<1>; +L_0x2b268f0 .delay (10000,10000,10000) L_0x2b268f0/d; +L_0x2b270a0/d .functor NAND 1, L_0x2b26620, L_0x2b26720, L_0x2b267d0, L_0x2b268f0; +L_0x2b270a0 .delay (10000,10000,10000) L_0x2b270a0/d; +v0x22afd90_0 .net "S0", 0 0, L_0x2b27350; 1 drivers +v0x22b8510_0 .net "S1", 0 0, L_0x2b26b90; 1 drivers +v0x22b85b0_0 .net "in0", 0 0, L_0x2b26cc0; 1 drivers +v0x22b8280_0 .net "in1", 0 0, L_0x2b26d60; 1 drivers +v0x22b8300_0 .net "in2", 0 0, L_0x2b26e00; 1 drivers +v0x22b6540_0 .net "in3", 0 0, L_0x2b26ef0; 1 drivers +v0x22b65e0_0 .net "nS0", 0 0, L_0x2b248c0; 1 drivers +v0x22b62b0_0 .net "nS1", 0 0, L_0x2b265c0; 1 drivers +v0x22b6330_0 .net "out", 0 0, L_0x2b270a0; 1 drivers +v0x22b47a0_0 .net "out0", 0 0, L_0x2b26620; 1 drivers +v0x22b4840_0 .net "out1", 0 0, L_0x2b26720; 1 drivers +v0x22bb1b0_0 .net "out2", 0 0, L_0x2b267d0; 1 drivers +v0x22bb230_0 .net "out3", 0 0, L_0x2b268f0; 1 drivers +S_0x22af0f0 .scope module, "OneMux" "FourInMux" 3 67, 3 125, S_0x229d190; + .timescale -9 -12; +L_0x2b192a0/d .functor NOT 1, L_0x2b27480, C4<0>, C4<0>, C4<0>; +L_0x2b192a0 .delay (10000,10000,10000) L_0x2b192a0/d; +L_0x2b27a60/d .functor NOT 1, L_0x2b275b0, C4<0>, C4<0>, C4<0>; +L_0x2b27a60 .delay (10000,10000,10000) L_0x2b27a60/d; +L_0x2b27ac0/d .functor NAND 1, L_0x2b192a0, L_0x2b27a60, L_0x2b276e0, C4<1>; +L_0x2b27ac0 .delay (10000,10000,10000) L_0x2b27ac0/d; +L_0x2b27c00/d .functor NAND 1, L_0x2b27480, L_0x2b27a60, L_0x2b27780, C4<1>; +L_0x2b27c00 .delay (10000,10000,10000) L_0x2b27c00/d; +L_0x2b27cf0/d .functor NAND 1, L_0x2b192a0, L_0x2b275b0, L_0x2b28630, C4<1>; +L_0x2b27cf0 .delay (10000,10000,10000) L_0x2b27cf0/d; +L_0x2b27de0/d .functor NAND 1, L_0x2b27480, L_0x2b275b0, L_0x2b286d0, C4<1>; +L_0x2b27de0 .delay (10000,10000,10000) L_0x2b27de0/d; +L_0x2b27f20/d .functor NAND 1, L_0x2b27ac0, L_0x2b27c00, L_0x2b27cf0, L_0x2b27de0; +L_0x2b27f20 .delay (10000,10000,10000) L_0x2b27f20/d; +v0x22aee60_0 .net "S0", 0 0, L_0x2b27480; 1 drivers +v0x22ad120_0 .net "S1", 0 0, L_0x2b275b0; 1 drivers +v0x22ad1c0_0 .net "in0", 0 0, L_0x2b276e0; 1 drivers +v0x22ace90_0 .net "in1", 0 0, L_0x2b27780; 1 drivers +v0x22acf10_0 .net "in2", 0 0, L_0x2b28630; 1 drivers +v0x22ab380_0 .net "in3", 0 0, L_0x2b286d0; 1 drivers +v0x22ab420_0 .net "nS0", 0 0, L_0x2b192a0; 1 drivers +v0x22b3b00_0 .net "nS1", 0 0, L_0x2b27a60; 1 drivers +v0x22b3b80_0 .net "out", 0 0, L_0x2b27f20; 1 drivers +v0x22b3870_0 .net "out0", 0 0, L_0x2b27ac0; 1 drivers +v0x22b3910_0 .net "out1", 0 0, L_0x2b27c00; 1 drivers +v0x22b1b30_0 .net "out2", 0 0, L_0x2b27cf0; 1 drivers +v0x22b1bb0_0 .net "out3", 0 0, L_0x2b27de0; 1 drivers +S_0x22a3d60 .scope module, "TwoMux" "TwoInMux" 3 68, 3 109, S_0x229d190; + .timescale -9 -12; +L_0x2b27e40/d .functor NOT 1, L_0x2b28560, C4<0>, C4<0>, C4<0>; +L_0x2b27e40 .delay (10000,10000,10000) L_0x2b27e40/d; +L_0x2b28220/d .functor AND 1, L_0x2b28bf0, L_0x2b27e40, C4<1>, C4<1>; +L_0x2b28220 .delay (20000,20000,20000) L_0x2b28220/d; +L_0x2b282d0/d .functor AND 1, L_0x2b28ce0, L_0x2b28560, C4<1>, C4<1>; +L_0x2b282d0 .delay (20000,20000,20000) L_0x2b282d0/d; +L_0x2b28380/d .functor OR 1, L_0x2b28220, L_0x2b282d0, C4<0>, C4<0>; +L_0x2b28380 .delay (20000,20000,20000) L_0x2b28380/d; +v0x229f2b0_0 .net "S", 0 0, L_0x2b28560; 1 drivers +v0x22a1ce0_0 .net "in0", 0 0, L_0x2b28bf0; 1 drivers +v0x22a1d80_0 .net "in1", 0 0, L_0x2b28ce0; 1 drivers +v0x22a88b0_0 .net "nS", 0 0, L_0x2b27e40; 1 drivers +v0x22a8930_0 .net "out0", 0 0, L_0x2b28220; 1 drivers +v0x22a6830_0 .net "out1", 0 0, L_0x2b282d0; 1 drivers +v0x22a68b0_0 .net "outfinal", 0 0, L_0x2b28380; 1 drivers +S_0x2287df0 .scope generate, "muxbits[8]" "muxbits[8]" 3 64, 3 64, S_0x1f6b890; + .timescale -9 -12; +P_0x265f0e8 .param/l "i" 3 64, +C4<01000>; +L_0x2b29750/d .functor OR 1, L_0x2b2bc00, L_0x2b21a10, C4<0>, C4<0>; +L_0x2b29750 .delay (20000,20000,20000) L_0x2b29750/d; +v0x22986f0_0 .net *"_s15", 0 0, L_0x2b2bc00; 1 drivers +v0x229f210_0 .net *"_s16", 0 0, L_0x2b21a10; 1 drivers +S_0x22977c0 .scope module, "ZeroMux" "FourInMux" 3 66, 3 125, S_0x2287df0; + .timescale -9 -12; +L_0x2b28ae0/d .functor NOT 1, L_0x2b28dd0, C4<0>, C4<0>, C4<0>; +L_0x2b28ae0 .delay (10000,10000,10000) L_0x2b28ae0/d; +L_0x2b29270/d .functor NOT 1, L_0x2b28f00, C4<0>, C4<0>, C4<0>; +L_0x2b29270 .delay (10000,10000,10000) L_0x2b29270/d; +L_0x2b29310/d .functor NAND 1, L_0x2b28ae0, L_0x2b29270, L_0x2b29030, C4<1>; +L_0x2b29310 .delay (10000,10000,10000) L_0x2b29310/d; +L_0x2b29450/d .functor NAND 1, L_0x2b28dd0, L_0x2b29270, L_0x2b1f870, C4<1>; +L_0x2b29450 .delay (10000,10000,10000) L_0x2b29450/d; +L_0x2b29570/d .functor NAND 1, L_0x2b28ae0, L_0x2b28f00, L_0x2b290d0, C4<1>; +L_0x2b29570 .delay (10000,10000,10000) L_0x2b29570/d; +L_0x2b296c0/d .functor NAND 1, L_0x2b28dd0, L_0x2b28f00, L_0x2b291c0, C4<1>; +L_0x2b296c0 .delay (10000,10000,10000) L_0x2b296c0/d; +L_0x2b29830/d .functor NAND 1, L_0x2b29310, L_0x2b29450, L_0x2b29570, L_0x2b296c0; +L_0x2b29830 .delay (10000,10000,10000) L_0x2b29830/d; +v0x2295a80_0 .net "S0", 0 0, L_0x2b28dd0; 1 drivers +v0x22957f0_0 .net "S1", 0 0, L_0x2b28f00; 1 drivers +v0x2295890_0 .net "in0", 0 0, L_0x2b29030; 1 drivers +v0x2293ce0_0 .net "in1", 0 0, L_0x2b1f870; 1 drivers +v0x2293d60_0 .net "in2", 0 0, L_0x2b290d0; 1 drivers +v0x229c4f0_0 .net "in3", 0 0, L_0x2b291c0; 1 drivers +v0x229c590_0 .net "nS0", 0 0, L_0x2b28ae0; 1 drivers +v0x229c260_0 .net "nS1", 0 0, L_0x2b29270; 1 drivers +v0x229c2e0_0 .net "out", 0 0, L_0x2b29830; 1 drivers +v0x229a490_0 .net "out0", 0 0, L_0x2b29310; 1 drivers +v0x229a530_0 .net "out1", 0 0, L_0x2b29450; 1 drivers +v0x229a200_0 .net "out2", 0 0, L_0x2b29570; 1 drivers +v0x229a280_0 .net "out3", 0 0, L_0x2b296c0; 1 drivers +S_0x228c3d0 .scope module, "OneMux" "FourInMux" 3 67, 3 125, S_0x2287df0; + .timescale -9 -12; +L_0x2b29ae0/d .functor NOT 1, L_0x2b2aa20, C4<0>, C4<0>, C4<0>; +L_0x2b29ae0 .delay (10000,10000,10000) L_0x2b29ae0/d; +L_0x2b29b90/d .functor NOT 1, L_0x2b2a1b0, C4<0>, C4<0>, C4<0>; +L_0x2b29b90 .delay (10000,10000,10000) L_0x2b29b90/d; +L_0x2b29bf0/d .functor NAND 1, L_0x2b29ae0, L_0x2b29b90, L_0x2b2a2e0, C4<1>; +L_0x2b29bf0 .delay (10000,10000,10000) L_0x2b29bf0/d; +L_0x2b29d30/d .functor NAND 1, L_0x2b2aa20, L_0x2b29b90, L_0x2b2a590, C4<1>; +L_0x2b29d30 .delay (10000,10000,10000) L_0x2b29d30/d; +L_0x2b29e20/d .functor NAND 1, L_0x2b29ae0, L_0x2b2a1b0, L_0x2b20a40, C4<1>; +L_0x2b29e20 .delay (10000,10000,10000) L_0x2b29e20/d; +L_0x2b29f10/d .functor NAND 1, L_0x2b2aa20, L_0x2b2a1b0, L_0x2b2b060, C4<1>; +L_0x2b29f10 .delay (10000,10000,10000) L_0x2b29f10/d; +L_0x2b2a770/d .functor NAND 1, L_0x2b29bf0, L_0x2b29d30, L_0x2b29e20, L_0x2b29f10; +L_0x2b2a770 .delay (10000,10000,10000) L_0x2b2a770/d; +v0x228a8c0_0 .net "S0", 0 0, L_0x2b2aa20; 1 drivers +v0x2293040_0 .net "S1", 0 0, L_0x2b2a1b0; 1 drivers +v0x22930e0_0 .net "in0", 0 0, L_0x2b2a2e0; 1 drivers +v0x2292db0_0 .net "in1", 0 0, L_0x2b2a590; 1 drivers +v0x2292e30_0 .net "in2", 0 0, L_0x2b20a40; 1 drivers +v0x2291070_0 .net "in3", 0 0, L_0x2b2b060; 1 drivers +v0x2291110_0 .net "nS0", 0 0, L_0x2b29ae0; 1 drivers +v0x2290de0_0 .net "nS1", 0 0, L_0x2b29b90; 1 drivers +v0x2290e60_0 .net "out", 0 0, L_0x2b2a770; 1 drivers +v0x228f2d0_0 .net "out0", 0 0, L_0x2b29bf0; 1 drivers +v0x228f370_0 .net "out1", 0 0, L_0x2b29d30; 1 drivers +v0x2297a50_0 .net "out2", 0 0, L_0x2b29e20; 1 drivers +v0x2297ad0_0 .net "out3", 0 0, L_0x2b29f10; 1 drivers +S_0x2285d70 .scope module, "TwoMux" "TwoInMux" 3 68, 3 109, S_0x2287df0; + .timescale -9 -12; +L_0x2b2b100/d .functor NOT 1, L_0x2b21230, C4<0>, C4<0>, C4<0>; +L_0x2b2b100 .delay (10000,10000,10000) L_0x2b2b100/d; +L_0x2b2b1b0/d .functor AND 1, L_0x2b2ab50, L_0x2b2b100, C4<1>, C4<1>; +L_0x2b2b1b0 .delay (20000,20000,20000) L_0x2b2b1b0/d; +L_0x2b2b260/d .functor AND 1, L_0x2b215a0, L_0x2b21230, C4<1>, C4<1>; +L_0x2b2b260 .delay (20000,20000,20000) L_0x2b2b260/d; +L_0x2b2b310/d .functor OR 1, L_0x2b2b1b0, L_0x2b2b260, C4<0>, C4<0>; +L_0x2b2b310 .delay (20000,20000,20000) L_0x2b2b310/d; +v0x22812c0_0 .net "S", 0 0, L_0x2b21230; 1 drivers +v0x228e630_0 .net "in0", 0 0, L_0x2b2ab50; 1 drivers +v0x228e6d0_0 .net "in1", 0 0, L_0x2b215a0; 1 drivers +v0x228e3a0_0 .net "nS", 0 0, L_0x2b2b100; 1 drivers +v0x228e420_0 .net "out0", 0 0, L_0x2b2b1b0; 1 drivers +v0x228c660_0 .net "out1", 0 0, L_0x2b2b260; 1 drivers +v0x228c6e0_0 .net "outfinal", 0 0, L_0x2b2b310; 1 drivers +S_0x226d8d0 .scope generate, "muxbits[9]" "muxbits[9]" 3 64, 3 64, S_0x1f6b890; + .timescale -9 -12; +P_0x26a1e88 .param/l "i" 3 64, +C4<01001>; +L_0x2b2d870/d .functor OR 1, L_0x2b2d9b0, L_0x2b2da50, C4<0>, C4<0>; +L_0x2b2d870 .delay (20000,20000,20000) L_0x2b2d870/d; +v0x22832a0_0 .net *"_s15", 0 0, L_0x2b2d9b0; 1 drivers +v0x2281220_0 .net *"_s16", 0 0, L_0x2b2da50; 1 drivers +S_0x2273210 .scope module, "ZeroMux" "FourInMux" 3 66, 3 125, S_0x226d8d0; + .timescale -9 -12; +L_0x2b2b6c0/d .functor NOT 1, L_0x2b2c7f0, C4<0>, C4<0>, C4<0>; +L_0x2b2b6c0 .delay (10000,10000,10000) L_0x2b2b6c0/d; +L_0x2b2b770/d .functor NOT 1, L_0x2b2beb0, C4<0>, C4<0>, C4<0>; +L_0x2b2b770 .delay (10000,10000,10000) L_0x2b2b770/d; +L_0x2b2b810/d .functor NAND 1, L_0x2b2b6c0, L_0x2b2b770, L_0x2b2bfe0, C4<1>; +L_0x2b2b810 .delay (10000,10000,10000) L_0x2b2b810/d; +L_0x2b2b950/d .functor NAND 1, L_0x2b2c7f0, L_0x2b2b770, L_0x2b2c080, C4<1>; +L_0x2b2b950 .delay (10000,10000,10000) L_0x2b2b950/d; +L_0x2b2ba70/d .functor NAND 1, L_0x2b2b6c0, L_0x2b2beb0, L_0x2b2c120, C4<1>; +L_0x2b2ba70 .delay (10000,10000,10000) L_0x2b2ba70/d; +L_0x2b2c400/d .functor NAND 1, L_0x2b2c7f0, L_0x2b2beb0, L_0x2b2c210, C4<1>; +L_0x2b2c400 .delay (10000,10000,10000) L_0x2b2c400/d; +L_0x2b2c540/d .functor NAND 1, L_0x2b2b810, L_0x2b2b950, L_0x2b2ba70, L_0x2b2c400; +L_0x2b2c540 .delay (10000,10000,10000) L_0x2b2c540/d; +v0x227ba30_0 .net "S0", 0 0, L_0x2b2c7f0; 1 drivers +v0x227b7a0_0 .net "S1", 0 0, L_0x2b2beb0; 1 drivers +v0x227b840_0 .net "in0", 0 0, L_0x2b2bfe0; 1 drivers +v0x22799c0_0 .net "in1", 0 0, L_0x2b2c080; 1 drivers +v0x2279a40_0 .net "in2", 0 0, L_0x2b2c120; 1 drivers +v0x2279730_0 .net "in3", 0 0, L_0x2b2c210; 1 drivers +v0x22797d0_0 .net "nS0", 0 0, L_0x2b2b6c0; 1 drivers +v0x2277c20_0 .net "nS1", 0 0, L_0x2b2b770; 1 drivers +v0x2277ca0_0 .net "out", 0 0, L_0x2b2c540; 1 drivers +v0x227e750_0 .net "out0", 0 0, L_0x2b2b810; 1 drivers +v0x227e7f0_0 .net "out1", 0 0, L_0x2b2b950; 1 drivers +v0x227c6d0_0 .net "out2", 0 0, L_0x2b2ba70; 1 drivers +v0x227c750_0 .net "out3", 0 0, L_0x2b2c400; 1 drivers +S_0x22722e0 .scope module, "OneMux" "FourInMux" 3 67, 3 125, S_0x226d8d0; + .timescale -9 -12; +L_0x2b2c300/d .functor NOT 1, L_0x2b2c920, C4<0>, C4<0>, C4<0>; +L_0x2b2c300 .delay (10000,10000,10000) L_0x2b2c300/d; +L_0x2b2cea0/d .functor NOT 1, L_0x2b2ca50, C4<0>, C4<0>, C4<0>; +L_0x2b2cea0 .delay (10000,10000,10000) L_0x2b2cea0/d; +L_0x2b2cf00/d .functor NAND 1, L_0x2b2c300, L_0x2b2cea0, L_0x2b2cb80, C4<1>; +L_0x2b2cf00 .delay (10000,10000,10000) L_0x2b2cf00/d; +L_0x2b2cff0/d .functor NAND 1, L_0x2b2c920, L_0x2b2cea0, L_0x2b2cc20, C4<1>; +L_0x2b2cff0 .delay (10000,10000,10000) L_0x2b2cff0/d; +L_0x2b2d0e0/d .functor NAND 1, L_0x2b2c300, L_0x2b2ca50, L_0x2b2ccc0, C4<1>; +L_0x2b2d0e0 .delay (10000,10000,10000) L_0x2b2d0e0/d; +L_0x2b2d1d0/d .functor NAND 1, L_0x2b2c920, L_0x2b2ca50, L_0x2b2cdb0, C4<1>; +L_0x2b2d1d0 .delay (10000,10000,10000) L_0x2b2d1d0/d; +L_0x2b2d340/d .functor NAND 1, L_0x2b2cf00, L_0x2b2cff0, L_0x2b2d0e0, L_0x2b2d1d0; +L_0x2b2d340 .delay (10000,10000,10000) L_0x2b2d340/d; +v0x22705a0_0 .net "S0", 0 0, L_0x2b2c920; 1 drivers +v0x2270310_0 .net "S1", 0 0, L_0x2b2ca50; 1 drivers +v0x22703b0_0 .net "in0", 0 0, L_0x2b2cb80; 1 drivers +v0x226e800_0 .net "in1", 0 0, L_0x2b2cc20; 1 drivers +v0x226e880_0 .net "in2", 0 0, L_0x2b2ccc0; 1 drivers +v0x2276f80_0 .net "in3", 0 0, L_0x2b2cdb0; 1 drivers +v0x2277020_0 .net "nS0", 0 0, L_0x2b2c300; 1 drivers +v0x2276cf0_0 .net "nS1", 0 0, L_0x2b2cea0; 1 drivers +v0x2276d70_0 .net "out", 0 0, L_0x2b2d340; 1 drivers +v0x2274fb0_0 .net "out0", 0 0, L_0x2b2cf00; 1 drivers +v0x2275050_0 .net "out1", 0 0, L_0x2b2cff0; 1 drivers +v0x2274d20_0 .net "out2", 0 0, L_0x2b2d0e0; 1 drivers +v0x2274da0_0 .net "out3", 0 0, L_0x2b2d1d0; 1 drivers +S_0x226bb90 .scope module, "TwoMux" "TwoInMux" 3 68, 3 109, S_0x226d8d0; + .timescale -9 -12; +L_0x2b2c460/d .functor NOT 1, L_0x2b2df80, C4<0>, C4<0>, C4<0>; +L_0x2b2c460 .delay (10000,10000,10000) L_0x2b2c460/d; +L_0x2b2dc00/d .functor AND 1, L_0x2b2d5f0, L_0x2b2c460, C4<1>, C4<1>; +L_0x2b2dc00 .delay (20000,20000,20000) L_0x2b2dc00/d; +L_0x2b2dcb0/d .functor AND 1, L_0x2b2d6e0, L_0x2b2df80, C4<1>, C4<1>; +L_0x2b2dcb0 .delay (20000,20000,20000) L_0x2b2dcb0/d; +L_0x2b2dda0/d .functor OR 1, L_0x2b2dc00, L_0x2b2dcb0, C4<0>, C4<0>; +L_0x2b2dda0 .delay (20000,20000,20000) L_0x2b2dda0/d; +v0x226dc00_0 .net "S", 0 0, L_0x2b2df80; 1 drivers +v0x226b900_0 .net "in0", 0 0, L_0x2b2d5f0; 1 drivers +v0x226b9a0_0 .net "in1", 0 0, L_0x2b2d6e0; 1 drivers +v0x2269df0_0 .net "nS", 0 0, L_0x2b2c460; 1 drivers +v0x2269e70_0 .net "out0", 0 0, L_0x2b2dc00; 1 drivers +v0x2272570_0 .net "out1", 0 0, L_0x2b2dcb0; 1 drivers +v0x22725f0_0 .net "outfinal", 0 0, L_0x2b2dda0; 1 drivers +S_0x22dadd0 .scope generate, "muxbits[10]" "muxbits[10]" 3 64, 3 64, S_0x1f6b890; + .timescale -9 -12; +P_0x26f2d68 .param/l "i" 3 64, +C4<01010>; +L_0x2b30150/d .functor OR 1, L_0x2b30290, L_0x2b30330, C4<0>, C4<0>; +L_0x2b30150 .delay (20000,20000,20000) L_0x2b30150/d; +v0x22652a0_0 .net *"_s15", 0 0, L_0x2b30290; 1 drivers +v0x226db60_0 .net *"_s16", 0 0, L_0x2b30330; 1 drivers +S_0x225fab0 .scope module, "ZeroMux" "FourInMux" 3 66, 3 125, S_0x22dadd0; + .timescale -9 -12; +L_0x2b2db40/d .functor NOT 1, L_0x2b2e020, C4<0>, C4<0>, C4<0>; +L_0x2b2db40 .delay (10000,10000,10000) L_0x2b2db40/d; +L_0x2b2e6a0/d .functor NOT 1, L_0x2b2e150, C4<0>, C4<0>, C4<0>; +L_0x2b2e6a0 .delay (10000,10000,10000) L_0x2b2e6a0/d; +L_0x2b2e740/d .functor NAND 1, L_0x2b2db40, L_0x2b2e6a0, L_0x2b2e280, C4<1>; +L_0x2b2e740 .delay (10000,10000,10000) L_0x2b2e740/d; +L_0x2b2e880/d .functor NAND 1, L_0x2b2e020, L_0x2b2e6a0, L_0x2b2e320, C4<1>; +L_0x2b2e880 .delay (10000,10000,10000) L_0x2b2e880/d; +L_0x2b2e970/d .functor NAND 1, L_0x2b2db40, L_0x2b2e150, L_0x2b2e3c0, C4<1>; +L_0x2b2e970 .delay (10000,10000,10000) L_0x2b2e970/d; +L_0x2b2eac0/d .functor NAND 1, L_0x2b2e020, L_0x2b2e150, L_0x2b2e4b0, C4<1>; +L_0x2b2eac0 .delay (10000,10000,10000) L_0x2b2eac0/d; +L_0x2b2ec30/d .functor NAND 1, L_0x2b2e740, L_0x2b2e880, L_0x2b2e970, L_0x2b2eac0; +L_0x2b2ec30 .delay (10000,10000,10000) L_0x2b2ec30/d; +v0x225f820_0 .net "S0", 0 0, L_0x2b2e020; 1 drivers +v0x225d930_0 .net "S1", 0 0, L_0x2b2e150; 1 drivers +v0x225d9d0_0 .net "in0", 0 0, L_0x2b2e280; 1 drivers +v0x225d670_0 .net "in1", 0 0, L_0x2b2e320; 1 drivers +v0x225d6f0_0 .net "in2", 0 0, L_0x2b2e3c0; 1 drivers +v0x225ba30_0 .net "in3", 0 0, L_0x2b2e4b0; 1 drivers +v0x225bad0_0 .net "nS0", 0 0, L_0x2b2db40; 1 drivers +v0x22627d0_0 .net "nS1", 0 0, L_0x2b2e6a0; 1 drivers +v0x2262850_0 .net "out", 0 0, L_0x2b2ec30; 1 drivers +v0x2260750_0 .net "out0", 0 0, L_0x2b2e740; 1 drivers +v0x22607f0_0 .net "out1", 0 0, L_0x2b2e880; 1 drivers +v0x2267320_0 .net "out2", 0 0, L_0x2b2e970; 1 drivers +v0x22673a0_0 .net "out3", 0 0, L_0x2b2eac0; 1 drivers +S_0x22a7d20 .scope module, "OneMux" "FourInMux" 3 67, 3 125, S_0x22dadd0; + .timescale -9 -12; +L_0x2b2e5a0/d .functor NOT 1, L_0x2b2fd00, C4<0>, C4<0>, C4<0>; +L_0x2b2e5a0 .delay (10000,10000,10000) L_0x2b2e5a0/d; +L_0x2b2f560/d .functor NOT 1, L_0x2b2eee0, C4<0>, C4<0>, C4<0>; +L_0x2b2f560 .delay (10000,10000,10000) L_0x2b2f560/d; +L_0x2b2f5c0/d .functor NAND 1, L_0x2b2e5a0, L_0x2b2f560, L_0x2b2f010, C4<1>; +L_0x2b2f5c0 .delay (10000,10000,10000) L_0x2b2f5c0/d; +L_0x2b2f700/d .functor NAND 1, L_0x2b2fd00, L_0x2b2f560, L_0x2b2f0b0, C4<1>; +L_0x2b2f700 .delay (10000,10000,10000) L_0x2b2f700/d; +L_0x2b2f7f0/d .functor NAND 1, L_0x2b2e5a0, L_0x2b2eee0, L_0x2b2f150, C4<1>; +L_0x2b2f7f0 .delay (10000,10000,10000) L_0x2b2f7f0/d; +L_0x2b2f8e0/d .functor NAND 1, L_0x2b2fd00, L_0x2b2eee0, L_0x2b2f240, C4<1>; +L_0x2b2f8e0 .delay (10000,10000,10000) L_0x2b2f8e0/d; +L_0x2b2fa50/d .functor NAND 1, L_0x2b2f5c0, L_0x2b2f700, L_0x2b2f7f0, L_0x2b2f8e0; +L_0x2b2fa50 .delay (10000,10000,10000) L_0x2b2fa50/d; +v0x22a31d0_0 .net "S0", 0 0, L_0x2b2fd00; 1 drivers +v0x229e680_0 .net "S1", 0 0, L_0x2b2eee0; 1 drivers +v0x229e720_0 .net "in0", 0 0, L_0x2b2f010; 1 drivers +v0x2261c40_0 .net "in1", 0 0, L_0x2b2f0b0; 1 drivers +v0x2261cc0_0 .net "in2", 0 0, L_0x2b2f150; 1 drivers +v0x2287260_0 .net "in3", 0 0, L_0x2b2f240; 1 drivers +v0x2287300_0 .net "nS0", 0 0, L_0x2b2e5a0; 1 drivers +v0x2282710_0 .net "nS1", 0 0, L_0x2b2f560; 1 drivers +v0x2282790_0 .net "out", 0 0, L_0x2b2fa50; 1 drivers +v0x227dbc0_0 .net "out0", 0 0, L_0x2b2f5c0; 1 drivers +v0x227dc60_0 .net "out1", 0 0, L_0x2b2f700; 1 drivers +v0x22ed4a0_0 .net "out2", 0 0, L_0x2b2f7f0; 1 drivers +v0x22ed520_0 .net "out3", 0 0, L_0x2b2f8e0; 1 drivers +S_0x22c87e0 .scope module, "TwoMux" "TwoInMux" 3 68, 3 109, S_0x22dadd0; + .timescale -9 -12; +L_0x2b2eb50/d .functor NOT 1, L_0x2b2fe30, C4<0>, C4<0>, C4<0>; +L_0x2b2eb50 .delay (10000,10000,10000) L_0x2b2eb50/d; +L_0x2b2f380/d .functor AND 1, L_0x2b2fed0, L_0x2b2eb50, C4<1>, C4<1>; +L_0x2b2f380 .delay (20000,20000,20000) L_0x2b2f380/d; +L_0x2b2f430/d .functor AND 1, L_0x2b2ffc0, L_0x2b2fe30, C4<1>, C4<1>; +L_0x2b2f430 .delay (20000,20000,20000) L_0x2b2f430/d; +L_0x2b304e0/d .functor OR 1, L_0x2b2f380, L_0x2b2f430, C4<0>, C4<0>; +L_0x2b304e0 .delay (20000,20000,20000) L_0x2b304e0/d; +v0x22dfcc0_0 .net "S", 0 0, L_0x2b2fe30; 1 drivers +v0x22c3c90_0 .net "in0", 0 0, L_0x2b2fed0; 1 drivers +v0x22c3d30_0 .net "in1", 0 0, L_0x2b2ffc0; 1 drivers +v0x2266790_0 .net "nS", 0 0, L_0x2b2eb50; 1 drivers +v0x2266810_0 .net "out0", 0 0, L_0x2b2f380; 1 drivers +v0x22bf140_0 .net "out1", 0 0, L_0x2b2f430; 1 drivers +v0x22bf1c0_0 .net "outfinal", 0 0, L_0x2b304e0; 1 drivers +S_0x2247660 .scope generate, "muxbits[11]" "muxbits[11]" 3 64, 3 64, S_0x1f6b890; + .timescale -9 -12; +P_0x2723c38 .param/l "i" 3 64, +C4<01011>; +L_0x2b32ac0/d .functor OR 1, L_0x2b32bc0, L_0x2b32c60, C4<0>, C4<0>; +L_0x2b32ac0 .delay (20000,20000,20000) L_0x2b32ac0/d; +v0x22e4770_0 .net *"_s15", 0 0, L_0x2b32bc0; 1 drivers +v0x22dfc20_0 .net *"_s16", 0 0, L_0x2b32c60; 1 drivers +S_0x22572a0 .scope module, "ZeroMux" "FourInMux" 3 66, 3 125, S_0x2247660; + .timescale -9 -12; +L_0x2b30420/d .functor NOT 1, L_0x2b315f0, C4<0>, C4<0>, C4<0>; +L_0x2b30420 .delay (10000,10000,10000) L_0x2b30420/d; +L_0x2b30db0/d .functor NOT 1, L_0x2b30680, C4<0>, C4<0>, C4<0>; +L_0x2b30db0 .delay (10000,10000,10000) L_0x2b30db0/d; +L_0x2b30e50/d .functor NAND 1, L_0x2b30420, L_0x2b30db0, L_0x2b307b0, C4<1>; +L_0x2b30e50 .delay (10000,10000,10000) L_0x2b30e50/d; +L_0x2b30f90/d .functor NAND 1, L_0x2b315f0, L_0x2b30db0, L_0x2b30850, C4<1>; +L_0x2b30f90 .delay (10000,10000,10000) L_0x2b30f90/d; +L_0x2b31080/d .functor NAND 1, L_0x2b30420, L_0x2b30680, L_0x2b308f0, C4<1>; +L_0x2b31080 .delay (10000,10000,10000) L_0x2b31080/d; +L_0x2b311d0/d .functor NAND 1, L_0x2b315f0, L_0x2b30680, L_0x2b238f0, C4<1>; +L_0x2b311d0 .delay (10000,10000,10000) L_0x2b311d0/d; +L_0x2b31340/d .functor NAND 1, L_0x2b30e50, L_0x2b30f90, L_0x2b31080, L_0x2b311d0; +L_0x2b31340 .delay (10000,10000,10000) L_0x2b31340/d; +v0x2257010_0 .net "S0", 0 0, L_0x2b315f0; 1 drivers +v0x2255500_0 .net "S1", 0 0, L_0x2b30680; 1 drivers +v0x22555a0_0 .net "in0", 0 0, L_0x2b307b0; 1 drivers +v0x22f2d30_0 .net "in1", 0 0, L_0x2b30850; 1 drivers +v0x22f2db0_0 .net "in2", 0 0, L_0x2b308f0; 1 drivers +v0x22ef470_0 .net "in3", 0 0, L_0x2b238f0; 1 drivers +v0x22ef510_0 .net "nS0", 0 0, L_0x2b30420; 1 drivers +v0x22ef220_0 .net "nS1", 0 0, L_0x2b30db0; 1 drivers +v0x22ef2a0_0 .net "out", 0 0, L_0x2b31340; 1 drivers +v0x22eefa0_0 .net "out0", 0 0, L_0x2b30e50; 1 drivers +v0x22ef040_0 .net "out1", 0 0, L_0x2b30f90; 1 drivers +v0x22e92c0_0 .net "out2", 0 0, L_0x2b31080; 1 drivers +v0x22e9340_0 .net "out3", 0 0, L_0x2b311d0; 1 drivers +S_0x224eaf0 .scope module, "OneMux" "FourInMux" 3 67, 3 125, S_0x2247660; + .timescale -9 -12; +L_0x2b239e0/d .functor NOT 1, L_0x2b31b40, C4<0>, C4<0>, C4<0>; +L_0x2b239e0 .delay (10000,10000,10000) L_0x2b239e0/d; +L_0x2b23a90/d .functor NOT 1, L_0x2b31c70, C4<0>, C4<0>, C4<0>; +L_0x2b23a90 .delay (10000,10000,10000) L_0x2b23a90/d; +L_0x2b309e0/d .functor NAND 1, L_0x2b239e0, L_0x2b23a90, L_0x2b328e0, C4<1>; +L_0x2b309e0 .delay (10000,10000,10000) L_0x2b309e0/d; +L_0x2b30b20/d .functor NAND 1, L_0x2b31b40, L_0x2b23a90, L_0x2b32980, C4<1>; +L_0x2b30b20 .delay (10000,10000,10000) L_0x2b30b20/d; +L_0x2b30c10/d .functor NAND 1, L_0x2b239e0, L_0x2b31c70, L_0x2b321f0, C4<1>; +L_0x2b30c10 .delay (10000,10000,10000) L_0x2b30c10/d; +L_0x2b31720/d .functor NAND 1, L_0x2b31b40, L_0x2b31c70, L_0x2b322e0, C4<1>; +L_0x2b31720 .delay (10000,10000,10000) L_0x2b31720/d; +L_0x2b31890/d .functor NAND 1, L_0x2b309e0, L_0x2b30b20, L_0x2b30c10, L_0x2b31720; +L_0x2b31890 .delay (10000,10000,10000) L_0x2b31890/d; +v0x224cfe0_0 .net "S0", 0 0, L_0x2b31b40; 1 drivers +v0x22519e0_0 .net "S1", 0 0, L_0x2b31c70; 1 drivers +v0x2251a80_0 .net "in0", 0 0, L_0x2b328e0; 1 drivers +v0x2251750_0 .net "in1", 0 0, L_0x2b32980; 1 drivers +v0x22517d0_0 .net "in2", 0 0, L_0x2b321f0; 1 drivers +v0x224fc40_0 .net "in3", 0 0, L_0x2b322e0; 1 drivers +v0x224fce0_0 .net "nS0", 0 0, L_0x2b239e0; 1 drivers +v0x2254640_0 .net "nS1", 0 0, L_0x2b23a90; 1 drivers +v0x22546c0_0 .net "out", 0 0, L_0x2b31890; 1 drivers +v0x22543b0_0 .net "out0", 0 0, L_0x2b309e0; 1 drivers +v0x2254450_0 .net "out1", 0 0, L_0x2b30b20; 1 drivers +v0x22528a0_0 .net "out2", 0 0, L_0x2b30c10; 1 drivers +v0x2252920_0 .net "out3", 0 0, L_0x2b31720; 1 drivers +S_0x224c120 .scope module, "TwoMux" "TwoInMux" 3 68, 3 109, S_0x2247660; + .timescale -9 -12; +L_0x2b31260/d .functor NOT 1, L_0x2b32760, C4<0>, C4<0>, C4<0>; +L_0x2b31260 .delay (10000,10000,10000) L_0x2b31260/d; +L_0x2b32420/d .functor AND 1, L_0x2b32800, L_0x2b31260, C4<1>, C4<1>; +L_0x2b32420 .delay (20000,20000,20000) L_0x2b32420/d; +L_0x2b324d0/d .functor AND 1, L_0x2b33190, L_0x2b32760, C4<1>, C4<1>; +L_0x2b324d0 .delay (20000,20000,20000) L_0x2b324d0/d; +L_0x2b32580/d .functor OR 1, L_0x2b32420, L_0x2b324d0, C4<0>, C4<0>; +L_0x2b32580 .delay (20000,20000,20000) L_0x2b32580/d; +v0x2249780_0 .net "S", 0 0, L_0x2b32760; 1 drivers +v0x224be90_0 .net "in0", 0 0, L_0x2b32800; 1 drivers +v0x224bf30_0 .net "in1", 0 0, L_0x2b33190; 1 drivers +v0x224a380_0 .net "nS", 0 0, L_0x2b31260; 1 drivers +v0x224a400_0 .net "out0", 0 0, L_0x2b32420; 1 drivers +v0x224ed80_0 .net "out1", 0 0, L_0x2b324d0; 1 drivers +v0x224ee00_0 .net "outfinal", 0 0, L_0x2b32580; 1 drivers +S_0x22300a0 .scope generate, "muxbits[12]" "muxbits[12]" 3 64, 3 64, S_0x1f6b890; + .timescale -9 -12; +P_0x2709cd8 .param/l "i" 3 64, +C4<01100>; +L_0x2b35160/d .functor OR 1, L_0x2b352a0, L_0x2b35340, C4<0>, C4<0>; +L_0x2b35160 .delay (20000,20000,20000) L_0x2b35160/d; +v0x2244940_0 .net *"_s15", 0 0, L_0x2b352a0; 1 drivers +v0x22496e0_0 .net *"_s16", 0 0, L_0x2b35340; 1 drivers +S_0x22394c0 .scope module, "ZeroMux" "FourInMux" 3 66, 3 125, S_0x22300a0; + .timescale -9 -12; +L_0x2b32d50/d .functor NOT 1, L_0x2b33280, C4<0>, C4<0>, C4<0>; +L_0x2b32d50 .delay (10000,10000,10000) L_0x2b32d50/d; +L_0x2b32e40/d .functor NOT 1, L_0x2b333b0, C4<0>, C4<0>, C4<0>; +L_0x2b32e40 .delay (10000,10000,10000) L_0x2b32e40/d; +L_0x2b32ee0/d .functor NAND 1, L_0x2b32d50, L_0x2b32e40, L_0x2b334e0, C4<1>; +L_0x2b32ee0 .delay (10000,10000,10000) L_0x2b32ee0/d; +L_0x2b33020/d .functor NAND 1, L_0x2b33280, L_0x2b32e40, L_0x2b33580, C4<1>; +L_0x2b33020 .delay (10000,10000,10000) L_0x2b33020/d; +L_0x2b339c0/d .functor NAND 1, L_0x2b32d50, L_0x2b333b0, L_0x2b33620, C4<1>; +L_0x2b339c0 .delay (10000,10000,10000) L_0x2b339c0/d; +L_0x2b33ae0/d .functor NAND 1, L_0x2b33280, L_0x2b333b0, L_0x2b33710, C4<1>; +L_0x2b33ae0 .delay (10000,10000,10000) L_0x2b33ae0/d; +L_0x2b33c50/d .functor NAND 1, L_0x2b32ee0, L_0x2b33020, L_0x2b339c0, L_0x2b33ae0; +L_0x2b33c50 .delay (10000,10000,10000) L_0x2b33c50/d; +v0x223e260_0 .net "S0", 0 0, L_0x2b33280; 1 drivers +v0x223c1e0_0 .net "S1", 0 0, L_0x2b333b0; 1 drivers +v0x223c280_0 .net "in0", 0 0, L_0x2b334e0; 1 drivers +v0x2240f80_0 .net "in1", 0 0, L_0x2b33580; 1 drivers +v0x2241000_0 .net "in2", 0 0, L_0x2b33620; 1 drivers +v0x223ef00_0 .net "in3", 0 0, L_0x2b33710; 1 drivers +v0x223efa0_0 .net "nS0", 0 0, L_0x2b32d50; 1 drivers +v0x2243ca0_0 .net "nS1", 0 0, L_0x2b32e40; 1 drivers +v0x2243d20_0 .net "out", 0 0, L_0x2b33c50; 1 drivers +v0x2241c20_0 .net "out0", 0 0, L_0x2b32ee0; 1 drivers +v0x2241cc0_0 .net "out1", 0 0, L_0x2b33020; 1 drivers +v0x22469c0_0 .net "out2", 0 0, L_0x2b339c0; 1 drivers +v0x2246a40_0 .net "out3", 0 0, L_0x2b33ae0; 1 drivers +S_0x2230f60 .scope module, "OneMux" "FourInMux" 3 67, 3 125, S_0x22300a0; + .timescale -9 -12; +L_0x2b33800/d .functor NOT 1, L_0x2b34d10, C4<0>, C4<0>, C4<0>; +L_0x2b33800 .delay (10000,10000,10000) L_0x2b33800/d; +L_0x2b338b0/d .functor NOT 1, L_0x2b33f00, C4<0>, C4<0>, C4<0>; +L_0x2b338b0 .delay (10000,10000,10000) L_0x2b338b0/d; +L_0x2b33910/d .functor NAND 1, L_0x2b33800, L_0x2b338b0, L_0x2b34030, C4<1>; +L_0x2b33910 .delay (10000,10000,10000) L_0x2b33910/d; +L_0x2b34710/d .functor NAND 1, L_0x2b34d10, L_0x2b338b0, L_0x2b340d0, C4<1>; +L_0x2b34710 .delay (10000,10000,10000) L_0x2b34710/d; +L_0x2b34800/d .functor NAND 1, L_0x2b33800, L_0x2b33f00, L_0x2b34170, C4<1>; +L_0x2b34800 .delay (10000,10000,10000) L_0x2b34800/d; +L_0x2b348f0/d .functor NAND 1, L_0x2b34d10, L_0x2b33f00, L_0x2b34260, C4<1>; +L_0x2b348f0 .delay (10000,10000,10000) L_0x2b348f0/d; +L_0x2b34a60/d .functor NAND 1, L_0x2b33910, L_0x2b34710, L_0x2b34800, L_0x2b348f0; +L_0x2b34a60 .delay (10000,10000,10000) L_0x2b34a60/d; +v0x2235960_0 .net "S0", 0 0, L_0x2b34d10; 1 drivers +v0x22356d0_0 .net "S1", 0 0, L_0x2b33f00; 1 drivers +v0x2235770_0 .net "in0", 0 0, L_0x2b34030; 1 drivers +v0x2233bc0_0 .net "in1", 0 0, L_0x2b340d0; 1 drivers +v0x2233c40_0 .net "in2", 0 0, L_0x2b34170; 1 drivers +v0x22385c0_0 .net "in3", 0 0, L_0x2b34260; 1 drivers +v0x2238660_0 .net "nS0", 0 0, L_0x2b33800; 1 drivers +v0x2238330_0 .net "nS1", 0 0, L_0x2b338b0; 1 drivers +v0x22383b0_0 .net "out", 0 0, L_0x2b34a60; 1 drivers +v0x2236820_0 .net "out0", 0 0, L_0x2b33910; 1 drivers +v0x22368c0_0 .net "out1", 0 0, L_0x2b34710; 1 drivers +v0x223b540_0 .net "out2", 0 0, L_0x2b34800; 1 drivers +v0x223b5c0_0 .net "out3", 0 0, L_0x2b348f0; 1 drivers +S_0x222fe10 .scope module, "TwoMux" "TwoInMux" 3 68, 3 109, S_0x22300a0; + .timescale -9 -12; +L_0x2b33b70/d .functor NOT 1, L_0x2b34e40, C4<0>, C4<0>, C4<0>; +L_0x2b33b70 .delay (10000,10000,10000) L_0x2b33b70/d; +L_0x2b343a0/d .functor AND 1, L_0x2b34ee0, L_0x2b33b70, C4<1>, C4<1>; +L_0x2b343a0 .delay (20000,20000,20000) L_0x2b343a0/d; +L_0x2b34470/d .functor AND 1, L_0x2b34fd0, L_0x2b34e40, C4<1>, C4<1>; +L_0x2b34470 .delay (20000,20000,20000) L_0x2b34470/d; +L_0x2b34560/d .functor OR 1, L_0x2b343a0, L_0x2b34470, C4<0>, C4<0>; +L_0x2b34560 .delay (20000,20000,20000) L_0x2b34560/d; +v0x222b740_0 .net "S", 0 0, L_0x2b34e40; 1 drivers +v0x222e300_0 .net "in0", 0 0, L_0x2b34ee0; 1 drivers +v0x222e3a0_0 .net "in1", 0 0, L_0x2b34fd0; 1 drivers +v0x2232d00_0 .net "nS", 0 0, L_0x2b33b70; 1 drivers +v0x2232d80_0 .net "out0", 0 0, L_0x2b343a0; 1 drivers +v0x2232a70_0 .net "out1", 0 0, L_0x2b34470; 1 drivers +v0x2232af0_0 .net "outfinal", 0 0, L_0x2b34560; 1 drivers +S_0x22122c0 .scope generate, "muxbits[13]" "muxbits[13]" 3 64, 3 64, S_0x1f6b890; + .timescale -9 -12; +P_0x26e3268 .param/l "i" 3 64, +C4<01101>; +L_0x2b37720/d .functor OR 1, L_0x2b37860, L_0x2b37900, C4<0>, C4<0>; +L_0x2b37720 .delay (20000,20000,20000) L_0x2b37720/d; +v0x222d250_0 .net *"_s15", 0 0, L_0x2b37860; 1 drivers +v0x222b6a0_0 .net *"_s16", 0 0, L_0x2b37900; 1 drivers +S_0x2223000 .scope module, "ZeroMux" "FourInMux" 3 66, 3 125, S_0x22122c0; + .timescale -9 -12; +L_0x2b35430/d .functor NOT 1, L_0x2b36640, C4<0>, C4<0>, C4<0>; +L_0x2b35430 .delay (10000,10000,10000) L_0x2b35430/d; +L_0x2b35520/d .functor NOT 1, L_0x2b356e0, C4<0>, C4<0>, C4<0>; +L_0x2b35520 .delay (10000,10000,10000) L_0x2b35520/d; +L_0x2b35ed0/d .functor NAND 1, L_0x2b35430, L_0x2b35520, L_0x2b35810, C4<1>; +L_0x2b35ed0 .delay (10000,10000,10000) L_0x2b35ed0/d; +L_0x2b36010/d .functor NAND 1, L_0x2b36640, L_0x2b35520, L_0x2b358b0, C4<1>; +L_0x2b36010 .delay (10000,10000,10000) L_0x2b36010/d; +L_0x2b36100/d .functor NAND 1, L_0x2b35430, L_0x2b356e0, L_0x2b35950, C4<1>; +L_0x2b36100 .delay (10000,10000,10000) L_0x2b36100/d; +L_0x2b36220/d .functor NAND 1, L_0x2b36640, L_0x2b356e0, L_0x2b35a40, C4<1>; +L_0x2b36220 .delay (10000,10000,10000) L_0x2b36220/d; +L_0x2b36390/d .functor NAND 1, L_0x2b35ed0, L_0x2b36010, L_0x2b36100, L_0x2b36220; +L_0x2b36390 .delay (10000,10000,10000) L_0x2b36390/d; +v0x2227da0_0 .net "S0", 0 0, L_0x2b36640; 1 drivers +v0x2227e40_0 .net "S1", 0 0, L_0x2b356e0; 1 drivers +v0x2225d20_0 .net "in0", 0 0, L_0x2b35810; 1 drivers +v0x2225dc0_0 .net "in1", 0 0, L_0x2b358b0; 1 drivers +v0x222a7e0_0 .net "in2", 0 0, L_0x2b35950; 1 drivers +v0x222a880_0 .net "in3", 0 0, L_0x2b35a40; 1 drivers +v0x222a550_0 .net "nS0", 0 0, L_0x2b35430; 1 drivers +v0x222a5d0_0 .net "nS1", 0 0, L_0x2b35520; 1 drivers +v0x2228a40_0 .net "out", 0 0, L_0x2b36390; 1 drivers +v0x2228ae0_0 .net "out0", 0 0, L_0x2b35ed0; 1 drivers +v0x222d440_0 .net "out1", 0 0, L_0x2b36010; 1 drivers +v0x222d4c0_0 .net "out2", 0 0, L_0x2b36100; 1 drivers +v0x222d1b0_0 .net "out3", 0 0, L_0x2b36220; 1 drivers +S_0x221c920 .scope module, "OneMux" "FourInMux" 3 67, 3 125, S_0x22122c0; + .timescale -9 -12; +L_0x2b35b30/d .functor NOT 1, L_0x2b36770, C4<0>, C4<0>, C4<0>; +L_0x2b35b30 .delay (10000,10000,10000) L_0x2b35b30/d; +L_0x2b35be0/d .functor NOT 1, L_0x2b368a0, C4<0>, C4<0>, C4<0>; +L_0x2b35be0 .delay (10000,10000,10000) L_0x2b35be0/d; +L_0x2b35c80/d .functor NAND 1, L_0x2b35b30, L_0x2b35be0, L_0x2b369d0, C4<1>; +L_0x2b35c80 .delay (10000,10000,10000) L_0x2b35c80/d; +L_0x2b35dc0/d .functor NAND 1, L_0x2b36770, L_0x2b35be0, L_0x2b36a70, C4<1>; +L_0x2b35dc0 .delay (10000,10000,10000) L_0x2b35dc0/d; +L_0x2b36f90/d .functor NAND 1, L_0x2b35b30, L_0x2b368a0, L_0x2b36b10, C4<1>; +L_0x2b36f90 .delay (10000,10000,10000) L_0x2b36f90/d; +L_0x2b37080/d .functor NAND 1, L_0x2b36770, L_0x2b368a0, L_0x2b36c00, C4<1>; +L_0x2b37080 .delay (10000,10000,10000) L_0x2b37080/d; +L_0x2b371f0/d .functor NAND 1, L_0x2b35c80, L_0x2b35dc0, L_0x2b36f90, L_0x2b37080; +L_0x2b371f0 .delay (10000,10000,10000) L_0x2b371f0/d; +v0x2217c00_0 .net "S0", 0 0, L_0x2b36770; 1 drivers +v0x221a8a0_0 .net "S1", 0 0, L_0x2b368a0; 1 drivers +v0x221a940_0 .net "in0", 0 0, L_0x2b369d0; 1 drivers +v0x221f640_0 .net "in1", 0 0, L_0x2b36a70; 1 drivers +v0x221f6c0_0 .net "in2", 0 0, L_0x2b36b10; 1 drivers +v0x221d5c0_0 .net "in3", 0 0, L_0x2b36c00; 1 drivers +v0x221d640_0 .net "nS0", 0 0, L_0x2b35b30; 1 drivers +v0x2222360_0 .net "nS1", 0 0, L_0x2b35be0; 1 drivers +v0x2222400_0 .net "out", 0 0, L_0x2b371f0; 1 drivers +v0x22202e0_0 .net "out0", 0 0, L_0x2b35c80; 1 drivers +v0x2220360_0 .net "out1", 0 0, L_0x2b35dc0; 1 drivers +v0x2225080_0 .net "out2", 0 0, L_0x2b36f90; 1 drivers +v0x2225120_0 .net "out3", 0 0, L_0x2b37080; 1 drivers +S_0x2216cc0 .scope module, "TwoMux" "TwoInMux" 3 68, 3 109, S_0x22122c0; + .timescale -9 -12; +L_0x2b36cf0/d .functor NOT 1, L_0x2b37f30, C4<0>, C4<0>, C4<0>; +L_0x2b36cf0 .delay (10000,10000,10000) L_0x2b36cf0/d; +L_0x2b36de0/d .functor AND 1, L_0x2b374a0, L_0x2b36cf0, C4<1>, C4<1>; +L_0x2b36de0 .delay (20000,20000,20000) L_0x2b36de0/d; +L_0x2b36ed0/d .functor AND 1, L_0x2b37590, L_0x2b37f30, C4<1>, C4<1>; +L_0x2b36ed0 .delay (20000,20000,20000) L_0x2b36ed0/d; +L_0x2b37d50/d .functor OR 1, L_0x2b36de0, L_0x2b36ed0, C4<0>, C4<0>; +L_0x2b37d50 .delay (20000,20000,20000) L_0x2b37d50/d; +v0x2216a30_0 .net "S", 0 0, L_0x2b37f30; 1 drivers +v0x2216ad0_0 .net "in0", 0 0, L_0x2b374a0; 1 drivers +v0x2214f20_0 .net "in1", 0 0, L_0x2b37590; 1 drivers +v0x2214fc0_0 .net "nS", 0 0, L_0x2b36cf0; 1 drivers +v0x2219c00_0 .net "out0", 0 0, L_0x2b36de0; 1 drivers +v0x2219ca0_0 .net "out1", 0 0, L_0x2b36ed0; 1 drivers +v0x2217b80_0 .net "outfinal", 0 0, L_0x2b37d50; 1 drivers +S_0x2211170 .scope generate, "muxbits[14]" "muxbits[14]" 3 64, 3 64, S_0x1f6b890; + .timescale -9 -12; +P_0x26ff358 .param/l "i" 3 64, +C4<01110>; +L_0x2b3a0d0/d .functor OR 1, L_0x2b3a210, L_0x2b3a2b0, C4<0>, C4<0>; +L_0x2b3a0d0 .delay (20000,20000,20000) L_0x2b3a0d0/d; +v0x2213760_0 .net *"_s15", 0 0, L_0x2b3a210; 1 drivers +v0x22163c0_0 .net *"_s16", 0 0, L_0x2b3a2b0; 1 drivers +S_0x2213dd0 .scope module, "ZeroMux" "FourInMux" 3 66, 3 125, S_0x2211170; + .timescale -9 -12; +L_0x2b379f0/d .functor NOT 1, L_0x2b37fd0, C4<0>, C4<0>, C4<0>; +L_0x2b379f0 .delay (10000,10000,10000) L_0x2b379f0/d; +L_0x2b37ae0/d .functor NOT 1, L_0x2b38100, C4<0>, C4<0>, C4<0>; +L_0x2b37ae0 .delay (10000,10000,10000) L_0x2b37ae0/d; +L_0x2b37b80/d .functor NAND 1, L_0x2b379f0, L_0x2b37ae0, L_0x2b38230, C4<1>; +L_0x2b37b80 .delay (10000,10000,10000) L_0x2b37b80/d; +L_0x2b38860/d .functor NAND 1, L_0x2b37fd0, L_0x2b37ae0, L_0x2b382d0, C4<1>; +L_0x2b38860 .delay (10000,10000,10000) L_0x2b38860/d; +L_0x2b38910/d .functor NAND 1, L_0x2b379f0, L_0x2b38100, L_0x2b38370, C4<1>; +L_0x2b38910 .delay (10000,10000,10000) L_0x2b38910/d; +L_0x2b38a00/d .functor NAND 1, L_0x2b37fd0, L_0x2b38100, L_0x2b38460, C4<1>; +L_0x2b38a00 .delay (10000,10000,10000) L_0x2b38a00/d; +L_0x2b38b40/d .functor NAND 1, L_0x2b37b80, L_0x2b38860, L_0x2b38910, L_0x2b38a00; +L_0x2b38b40 .delay (10000,10000,10000) L_0x2b38b40/d; +v0x2232400_0 .net "S0", 0 0, L_0x2b37fd0; 1 drivers +v0x2235060_0 .net "S1", 0 0, L_0x2b38100; 1 drivers +v0x2237cc0_0 .net "in0", 0 0, L_0x2b38230; 1 drivers +v0x22085e0_0 .net "in1", 0 0, L_0x2b382d0; 1 drivers +v0x224b820_0 .net "in2", 0 0, L_0x2b38370; 1 drivers +v0x224e480_0 .net "in3", 0 0, L_0x2b38460; 1 drivers +v0x22510e0_0 .net "nS0", 0 0, L_0x2b379f0; 1 drivers +v0x2253d40_0 .net "nS1", 0 0, L_0x2b37ae0; 1 drivers +v0x22569a0_0 .net "out", 0 0, L_0x2b38b40; 1 drivers +v0x2259600_0 .net "out0", 0 0, L_0x2b37b80; 1 drivers +v0x220b240_0 .net "out1", 0 0, L_0x2b38860; 1 drivers +v0x220dea0_0 .net "out2", 0 0, L_0x2b38910; 1 drivers +v0x2210b00_0 .net "out3", 0 0, L_0x2b38a00; 1 drivers +S_0x2214060 .scope module, "OneMux" "FourInMux" 3 67, 3 125, S_0x2211170; + .timescale -9 -12; +L_0x2b38550/d .functor NOT 1, L_0x2b39c80, C4<0>, C4<0>, C4<0>; +L_0x2b38550 .delay (10000,10000,10000) L_0x2b38550/d; +L_0x2b38640/d .functor NOT 1, L_0x2b38df0, C4<0>, C4<0>, C4<0>; +L_0x2b38640 .delay (10000,10000,10000) L_0x2b38640/d; +L_0x2b386e0/d .functor NAND 1, L_0x2b38550, L_0x2b38640, L_0x2b38f20, C4<1>; +L_0x2b386e0 .delay (10000,10000,10000) L_0x2b386e0/d; +L_0x2b396c0/d .functor NAND 1, L_0x2b39c80, L_0x2b38640, L_0x2b38fc0, C4<1>; +L_0x2b396c0 .delay (10000,10000,10000) L_0x2b396c0/d; +L_0x2b39770/d .functor NAND 1, L_0x2b38550, L_0x2b38df0, L_0x2b39060, C4<1>; +L_0x2b39770 .delay (10000,10000,10000) L_0x2b39770/d; +L_0x2b39860/d .functor NAND 1, L_0x2b39c80, L_0x2b38df0, L_0x2b39150, C4<1>; +L_0x2b39860 .delay (10000,10000,10000) L_0x2b39860/d; +L_0x2b399d0/d .functor NAND 1, L_0x2b386e0, L_0x2b396c0, L_0x2b39770, L_0x2b39860; +L_0x2b399d0 .delay (10000,10000,10000) L_0x2b399d0/d; +v0x2219770_0 .net "S0", 0 0, L_0x2b39c80; 1 drivers +v0x22199f0_0 .net "S1", 0 0, L_0x2b38df0; 1 drivers +v0x2216fe0_0 .net "in0", 0 0, L_0x2b38f20; 1 drivers +v0x2214380_0 .net "in1", 0 0, L_0x2b38fc0; 1 drivers +v0x2211720_0 .net "in2", 0 0, L_0x2b39060; 1 drivers +v0x220eac0_0 .net "in3", 0 0, L_0x2b39150; 1 drivers +v0x220be60_0 .net "nS0", 0 0, L_0x2b38550; 1 drivers +v0x2209200_0 .net "nS1", 0 0, L_0x2b38640; 1 drivers +v0x2205fc0_0 .net "out", 0 0, L_0x2b399d0; 1 drivers +v0x2206240_0 .net "out0", 0 0, L_0x2b386e0; 1 drivers +v0x2229ee0_0 .net "out1", 0 0, L_0x2b396c0; 1 drivers +v0x222cb40_0 .net "out2", 0 0, L_0x2b39770; 1 drivers +v0x222f7a0_0 .net "out3", 0 0, L_0x2b39860; 1 drivers +S_0x220f660 .scope module, "TwoMux" "TwoInMux" 3 68, 3 109, S_0x2211170; + .timescale -9 -12; +L_0x2b39240/d .functor NOT 1, L_0x2b39db0, C4<0>, C4<0>, C4<0>; +L_0x2b39240 .delay (10000,10000,10000) L_0x2b39240/d; +L_0x2b39330/d .functor AND 1, L_0x2b39e50, L_0x2b39240, C4<1>, C4<1>; +L_0x2b39330 .delay (20000,20000,20000) L_0x2b39330/d; +L_0x2b39420/d .functor AND 1, L_0x2b39f40, L_0x2b39db0, C4<1>, C4<1>; +L_0x2b39420 .delay (20000,20000,20000) L_0x2b39420/d; +L_0x2b39510/d .functor OR 1, L_0x2b39330, L_0x2b39420, C4<0>, C4<0>; +L_0x2b39510 .delay (20000,20000,20000) L_0x2b39510/d; +v0x2224e70_0 .net "S", 0 0, L_0x2b39db0; 1 drivers +v0x2221ed0_0 .net "in0", 0 0, L_0x2b39e50; 1 drivers +v0x2222150_0 .net "in1", 0 0, L_0x2b39f40; 1 drivers +v0x221f1b0_0 .net "nS", 0 0, L_0x2b39240; 1 drivers +v0x221f430_0 .net "out0", 0 0, L_0x2b39330; 1 drivers +v0x221c490_0 .net "out1", 0 0, L_0x2b39420; 1 drivers +v0x221c710_0 .net "outfinal", 0 0, L_0x2b39510; 1 drivers +S_0x220e7a0 .scope generate, "muxbits[15]" "muxbits[15]" 3 64, 3 64, S_0x1f6b890; + .timescale -9 -12; +P_0x271be98 .param/l "i" 3 64, +C4<01111>; +L_0x2b3c7e0/d .functor OR 1, L_0x2b3c920, L_0x2b3c9c0, C4<0>, C4<0>; +L_0x2b3c7e0 .delay (20000,20000,20000) L_0x2b3c7e0/d; +v0x2227b90_0 .net *"_s15", 0 0, L_0x2b3c920; 1 drivers +v0x2224bf0_0 .net *"_s16", 0 0, L_0x2b3c9c0; 1 drivers +S_0x2211400 .scope module, "ZeroMux" "FourInMux" 3 66, 3 125, S_0x220e7a0; + .timescale -9 -12; +L_0x2b3a3a0/d .functor NOT 1, L_0x2b3b5c0, C4<0>, C4<0>, C4<0>; +L_0x2b3a3a0 .delay (10000,10000,10000) L_0x2b3a3a0/d; +L_0x2b3a490/d .functor NOT 1, L_0x2b3a750, C4<0>, C4<0>, C4<0>; +L_0x2b3a490 .delay (10000,10000,10000) L_0x2b3a490/d; +L_0x2b3a530/d .functor NAND 1, L_0x2b3a3a0, L_0x2b3a490, L_0x2b3a880, C4<1>; +L_0x2b3a530 .delay (10000,10000,10000) L_0x2b3a530/d; +L_0x2b39650/d .functor NAND 1, L_0x2b3b5c0, L_0x2b3a490, L_0x2b3a920, C4<1>; +L_0x2b39650 .delay (10000,10000,10000) L_0x2b39650/d; +L_0x2b3b0e0/d .functor NAND 1, L_0x2b3a3a0, L_0x2b3a750, L_0x2b3a9c0, C4<1>; +L_0x2b3b0e0 .delay (10000,10000,10000) L_0x2b3b0e0/d; +L_0x2b3b1d0/d .functor NAND 1, L_0x2b3b5c0, L_0x2b3a750, L_0x2b3aab0, C4<1>; +L_0x2b3b1d0 .delay (10000,10000,10000) L_0x2b3b1d0/d; +L_0x2b3b310/d .functor NAND 1, L_0x2b3a530, L_0x2b39650, L_0x2b3b0e0, L_0x2b3b1d0; +L_0x2b3b310 .delay (10000,10000,10000) L_0x2b3b310/d; +v0x2240af0_0 .net "S0", 0 0, L_0x2b3b5c0; 1 drivers +v0x2240d70_0 .net "S1", 0 0, L_0x2b3a750; 1 drivers +v0x223ddd0_0 .net "in0", 0 0, L_0x2b3a880; 1 drivers +v0x223e050_0 .net "in1", 0 0, L_0x2b3a920; 1 drivers +v0x223b0b0_0 .net "in2", 0 0, L_0x2b3a9c0; 1 drivers +v0x223b330_0 .net "in3", 0 0, L_0x2b3aab0; 1 drivers +v0x22388e0_0 .net "nS0", 0 0, L_0x2b3a3a0; 1 drivers +v0x2235c80_0 .net "nS1", 0 0, L_0x2b3a490; 1 drivers +v0x2233020_0 .net "out", 0 0, L_0x2b3b310; 1 drivers +v0x22303c0_0 .net "out0", 0 0, L_0x2b3a530; 1 drivers +v0x222d760_0 .net "out1", 0 0, L_0x2b39650; 1 drivers +v0x222ab00_0 .net "out2", 0 0, L_0x2b3b0e0; 1 drivers +v0x2227910_0 .net "out3", 0 0, L_0x2b3b1d0; 1 drivers +S_0x220ca00 .scope module, "OneMux" "FourInMux" 3 67, 3 125, S_0x220e7a0; + .timescale -9 -12; +L_0x2b27900/d .functor NOT 1, L_0x2b3b6f0, C4<0>, C4<0>, C4<0>; +L_0x2b27900 .delay (10000,10000,10000) L_0x2b27900/d; +L_0x2b3adb0/d .functor NOT 1, L_0x2b3b820, C4<0>, C4<0>, C4<0>; +L_0x2b3adb0 .delay (10000,10000,10000) L_0x2b3adb0/d; +L_0x2b3ae50/d .functor NAND 1, L_0x2b27900, L_0x2b3adb0, L_0x2b3b950, C4<1>; +L_0x2b3ae50 .delay (10000,10000,10000) L_0x2b3ae50/d; +L_0x2b3af90/d .functor NAND 1, L_0x2b3b6f0, L_0x2b3adb0, L_0x2b3b9f0, C4<1>; +L_0x2b3af90 .delay (10000,10000,10000) L_0x2b3af90/d; +L_0x2b3b030/d .functor NAND 1, L_0x2b27900, L_0x2b3b820, L_0x2b3ba90, C4<1>; +L_0x2b3b030 .delay (10000,10000,10000) L_0x2b3b030/d; +L_0x2b3c140/d .functor NAND 1, L_0x2b3b6f0, L_0x2b3b820, L_0x2b3bb80, C4<1>; +L_0x2b3c140 .delay (10000,10000,10000) L_0x2b3c140/d; +L_0x2b3c2b0/d .functor NAND 1, L_0x2b3ae50, L_0x2b3af90, L_0x2b3b030, L_0x2b3c140; +L_0x2b3c2b0 .delay (10000,10000,10000) L_0x2b3c2b0/d; +v0x225e480_0 .net "S0", 0 0, L_0x2b3b6f0; 1 drivers +v0x22790c0_0 .net "S1", 0 0, L_0x2b3b820; 1 drivers +v0x22575c0_0 .net "in0", 0 0, L_0x2b3b950; 1 drivers +v0x2254960_0 .net "in1", 0 0, L_0x2b3b9f0; 1 drivers +v0x2251d00_0 .net "in2", 0 0, L_0x2b3ba90; 1 drivers +v0x224f0a0_0 .net "in3", 0 0, L_0x2b3bb80; 1 drivers +v0x224c440_0 .net "nS0", 0 0, L_0x2b27900; 1 drivers +v0x2249250_0 .net "nS1", 0 0, L_0x2b3adb0; 1 drivers +v0x22494d0_0 .net "out", 0 0, L_0x2b3c2b0; 1 drivers +v0x2246530_0 .net "out0", 0 0, L_0x2b3ae50; 1 drivers +v0x22467b0_0 .net "out1", 0 0, L_0x2b3af90; 1 drivers +v0x2243810_0 .net "out2", 0 0, L_0x2b3b030; 1 drivers +v0x2243a90_0 .net "out3", 0 0, L_0x2b3c140; 1 drivers +S_0x220e510 .scope module, "TwoMux" "TwoInMux" 3 68, 3 109, S_0x220e7a0; + .timescale -9 -12; +L_0x2b3bc70/d .functor NOT 1, L_0x2b3d000, C4<0>, C4<0>, C4<0>; +L_0x2b3bc70 .delay (10000,10000,10000) L_0x2b3bc70/d; +L_0x2b3bd60/d .functor AND 1, L_0x2b3c560, L_0x2b3bc70, C4<1>, C4<1>; +L_0x2b3bd60 .delay (20000,20000,20000) L_0x2b3bd60/d; +L_0x2b3be50/d .functor AND 1, L_0x2b3c650, L_0x2b3d000, C4<1>, C4<1>; +L_0x2b3be50 .delay (20000,20000,20000) L_0x2b3be50/d; +L_0x2b3bf40/d .functor OR 1, L_0x2b3bd60, L_0x2b3be50, C4<0>, C4<0>; +L_0x2b3bf40 .delay (20000,20000,20000) L_0x2b3bf40/d; +v0x22ee940_0 .net "S", 0 0, L_0x2b3d000; 1 drivers +v0x22f28a0_0 .net "in0", 0 0, L_0x2b3c560; 1 drivers +v0x226c6d0_0 .net "in1", 0 0, L_0x2b3c650; 1 drivers +v0x226fca0_0 .net "nS", 0 0, L_0x2b3bc70; 1 drivers +v0x22710e0_0 .net "out0", 0 0, L_0x2b3bd60; 1 drivers +v0x22746b0_0 .net "out1", 0 0, L_0x2b3be50; 1 drivers +v0x2275af0_0 .net "outfinal", 0 0, L_0x2b3bf40; 1 drivers +S_0x22070f0 .scope generate, "muxbits[16]" "muxbits[16]" 3 64, 3 64, S_0x1f6b890; + .timescale -9 -12; +P_0x275af38 .param/l "i" 3 64, +C4<010000>; +L_0x2b2add0/d .functor OR 1, L_0x2b2af10, L_0x2b2afb0, C4<0>, C4<0>; +L_0x2b2add0 .delay (20000,20000,20000) L_0x2b2add0/d; +v0x22eb5f0_0 .net *"_s15", 0 0, L_0x2b2af10; 1 drivers +v0x226b290_0 .net *"_s16", 0 0, L_0x2b2afb0; 1 drivers +S_0x2209da0 .scope module, "ZeroMux" "FourInMux" 3 66, 3 125, S_0x22070f0; + .timescale -9 -12; +L_0x2b3cab0/d .functor NOT 1, L_0x2b3d0a0, C4<0>, C4<0>, C4<0>; +L_0x2b3cab0 .delay (10000,10000,10000) L_0x2b3cab0/d; +L_0x2b3cba0/d .functor NOT 1, L_0x2b3d1d0, C4<0>, C4<0>, C4<0>; +L_0x2b3cba0 .delay (10000,10000,10000) L_0x2b3cba0/d; +L_0x2b3cc40/d .functor NAND 1, L_0x2b3cab0, L_0x2b3cba0, L_0x2b3d300, C4<1>; +L_0x2b3cc40 .delay (10000,10000,10000) L_0x2b3cc40/d; +L_0x2b3cd80/d .functor NAND 1, L_0x2b3d0a0, L_0x2b3cba0, L_0x2b29fa0, C4<1>; +L_0x2b3cd80 .delay (10000,10000,10000) L_0x2b3cd80/d; +L_0x2b3ce70/d .functor NAND 1, L_0x2b3cab0, L_0x2b3d1d0, L_0x2b2a040, C4<1>; +L_0x2b3ce70 .delay (10000,10000,10000) L_0x2b3ce70/d; +L_0x2b3dad0/d .functor NAND 1, L_0x2b3d0a0, L_0x2b3d1d0, L_0x2b3d7b0, C4<1>; +L_0x2b3dad0 .delay (10000,10000,10000) L_0x2b3dad0/d; +L_0x2b3dbe0/d .functor NAND 1, L_0x2b3cc40, L_0x2b3cd80, L_0x2b3ce70, L_0x2b3dad0; +L_0x2b3dbe0 .delay (10000,10000,10000) L_0x2b3dbe0/d; +v0x22d3130_0 .net "S0", 0 0, L_0x2b3d0a0; 1 drivers +v0x2267bf0_0 .net "S1", 0 0, L_0x2b3d1d0; 1 drivers +v0x22d6700_0 .net "in0", 0 0, L_0x2b3d300; 1 drivers +v0x22d7b40_0 .net "in1", 0 0, L_0x2b29fa0; 1 drivers +v0x22db110_0 .net "in2", 0 0, L_0x2b2a040; 1 drivers +v0x2268ac0_0 .net "in3", 0 0, L_0x2b3d7b0; 1 drivers +v0x22dc530_0 .net "nS0", 0 0, L_0x2b3cab0; 1 drivers +v0x22dd400_0 .net "nS1", 0 0, L_0x2b3cba0; 1 drivers +v0x22e1080_0 .net "out", 0 0, L_0x2b3dbe0; 1 drivers +v0x22e1f50_0 .net "out0", 0 0, L_0x2b3cc40; 1 drivers +v0x22e5bd0_0 .net "out1", 0 0, L_0x2b3cd80; 1 drivers +v0x22e6aa0_0 .net "out2", 0 0, L_0x2b3ce70; 1 drivers +v0x22ea720_0 .net "out3", 0 0, L_0x2b3dad0; 1 drivers +S_0x220b8b0 .scope module, "OneMux" "FourInMux" 3 67, 3 125, S_0x22070f0; + .timescale -9 -12; +L_0x2b3d8a0/d .functor NOT 1, L_0x2b3ef40, C4<0>, C4<0>, C4<0>; +L_0x2b3d8a0 .delay (10000,10000,10000) L_0x2b3d8a0/d; +L_0x2b3d990/d .functor NOT 1, L_0x2b3de90, C4<0>, C4<0>, C4<0>; +L_0x2b3d990 .delay (10000,10000,10000) L_0x2b3d990/d; +L_0x2b2a130/d .functor NAND 1, L_0x2b3d8a0, L_0x2b3d990, L_0x2b3dfc0, C4<1>; +L_0x2b2a130 .delay (10000,10000,10000) L_0x2b2a130/d; +L_0x2b3e940/d .functor NAND 1, L_0x2b3ef40, L_0x2b3d990, L_0x2b2a380, C4<1>; +L_0x2b3e940 .delay (10000,10000,10000) L_0x2b3e940/d; +L_0x2b3ea30/d .functor NAND 1, L_0x2b3d8a0, L_0x2b3de90, L_0x2b2a420, C4<1>; +L_0x2b3ea30 .delay (10000,10000,10000) L_0x2b3ea30/d; +L_0x2b3eb20/d .functor NAND 1, L_0x2b3ef40, L_0x2b3de90, L_0x2b3e470, C4<1>; +L_0x2b3eb20 .delay (10000,10000,10000) L_0x2b3eb20/d; +L_0x2b3ec90/d .functor NAND 1, L_0x2b2a130, L_0x2b3e940, L_0x2b3ea30, L_0x2b3eb20; +L_0x2b3ec90 .delay (10000,10000,10000) L_0x2b3ec90/d; +v0x22b7080_0 .net "S0", 0 0, L_0x2b3ef40; 1 drivers +v0x22ba650_0 .net "S1", 0 0, L_0x2b3de90; 1 drivers +v0x22bba50_0 .net "in0", 0 0, L_0x2b3dfc0; 1 drivers +v0x22bc920_0 .net "in1", 0 0, L_0x2b2a380; 1 drivers +v0x22c05a0_0 .net "in2", 0 0, L_0x2b2a420; 1 drivers +v0x22c1470_0 .net "in3", 0 0, L_0x2b3e470; 1 drivers +v0x22c50f0_0 .net "nS0", 0 0, L_0x2b3d8a0; 1 drivers +v0x22c5fc0_0 .net "nS1", 0 0, L_0x2b3d990; 1 drivers +v0x22c9c40_0 .net "out", 0 0, L_0x2b3ec90; 1 drivers +v0x22cab10_0 .net "out0", 0 0, L_0x2b2a130; 1 drivers +v0x22cd2e0_0 .net "out1", 0 0, L_0x2b3e940; 1 drivers +v0x22ce720_0 .net "out2", 0 0, L_0x2b3ea30; 1 drivers +v0x22d1cf0_0 .net "out3", 0 0, L_0x2b3eb20; 1 drivers +S_0x220bb40 .scope module, "TwoMux" "TwoInMux" 3 68, 3 109, S_0x22070f0; + .timescale -9 -12; +L_0x2b3e560/d .functor NOT 1, L_0x2b2b4b0, C4<0>, C4<0>, C4<0>; +L_0x2b3e560 .delay (10000,10000,10000) L_0x2b3e560/d; +L_0x2b3e650/d .functor AND 1, L_0x2b2b550, L_0x2b3e560, C4<1>, C4<1>; +L_0x2b3e650 .delay (20000,20000,20000) L_0x2b3e650/d; +L_0x2b3e740/d .functor AND 1, L_0x2b2ac40, L_0x2b2b4b0, C4<1>, C4<1>; +L_0x2b3e740 .delay (20000,20000,20000) L_0x2b3e740/d; +L_0x2b2a510/d .functor OR 1, L_0x2b3e650, L_0x2b3e740, C4<0>, C4<0>; +L_0x2b2a510 .delay (20000,20000,20000) L_0x2b2a510/d; +v0x22aa050_0 .net "S", 0 0, L_0x2b2b4b0; 1 drivers +v0x22ac820_0 .net "in0", 0 0, L_0x2b2b550; 1 drivers +v0x2263f70_0 .net "in1", 0 0, L_0x2b2ac40; 1 drivers +v0x22adc60_0 .net "nS", 0 0, L_0x2b3e560; 1 drivers +v0x22b1230_0 .net "out0", 0 0, L_0x2b3e650; 1 drivers +v0x22b2670_0 .net "out1", 0 0, L_0x2b3e740; 1 drivers +v0x22b5c40_0 .net "outfinal", 0 0, L_0x2b2a510; 1 drivers +S_0x2206450 .scope generate, "muxbits[17]" "muxbits[17]" 3 64, 3 64, S_0x1f6b890; + .timescale -9 -12; +P_0x2756df8 .param/l "i" 3 64, +C4<010001>; +L_0x2b42400/d .functor OR 1, L_0x2b42540, L_0x2b425e0, C4<0>, C4<0>; +L_0x2b42400 .delay (20000,20000,20000) L_0x2b42400/d; +v0x22a5500_0 .net *"_s15", 0 0, L_0x2b42540; 1 drivers +v0x22a9180_0 .net *"_s16", 0 0, L_0x2b425e0; 1 drivers +S_0x2208c50 .scope module, "ZeroMux" "FourInMux" 3 66, 3 125, S_0x2206450; + .timescale -9 -12; +L_0x2b2bca0/d .functor NOT 1, L_0x2b40450, C4<0>, C4<0>, C4<0>; +L_0x2b2bca0 .delay (10000,10000,10000) L_0x2b2bca0/d; +L_0x2b2bd90/d .functor NOT 1, L_0x2b40580, C4<0>, C4<0>, C4<0>; +L_0x2b2bd90 .delay (10000,10000,10000) L_0x2b2bd90/d; +L_0x2b2be30/d .functor NAND 1, L_0x2b2bca0, L_0x2b2bd90, L_0x2b406b0, C4<1>; +L_0x2b2be30 .delay (10000,10000,10000) L_0x2b2be30/d; +L_0x2b3f970/d .functor NAND 1, L_0x2b40450, L_0x2b2bd90, L_0x2b40750, C4<1>; +L_0x2b3f970 .delay (10000,10000,10000) L_0x2b3f970/d; +L_0x2b3fa60/d .functor NAND 1, L_0x2b2bca0, L_0x2b40580, L_0x2b407f0, C4<1>; +L_0x2b3fa60 .delay (10000,10000,10000) L_0x2b3fa60/d; +L_0x2b40090/d .functor NAND 1, L_0x2b40450, L_0x2b40580, L_0x2b408e0, C4<1>; +L_0x2b40090 .delay (10000,10000,10000) L_0x2b40090/d; +L_0x2b401a0/d .functor NAND 1, L_0x2b2be30, L_0x2b3f970, L_0x2b3fa60, L_0x2b40090; +L_0x2b401a0 .delay (10000,10000,10000) L_0x2b401a0/d; +v0x2289590_0 .net "S0", 0 0, L_0x2b40450; 1 drivers +v0x228bd60_0 .net "S1", 0 0, L_0x2b40580; 1 drivers +v0x228d1a0_0 .net "in0", 0 0, L_0x2b406b0; 1 drivers +v0x2290770_0 .net "in1", 0 0, L_0x2b40750; 1 drivers +v0x2291bb0_0 .net "in2", 0 0, L_0x2b407f0; 1 drivers +v0x2295180_0 .net "in3", 0 0, L_0x2b408e0; 1 drivers +v0x22965c0_0 .net "nS0", 0 0, L_0x2b2bca0; 1 drivers +v0x2299b90_0 .net "nS1", 0 0, L_0x2b2bd90; 1 drivers +v0x229afd0_0 .net "out", 0 0, L_0x2b401a0; 1 drivers +v0x229fae0_0 .net "out0", 0 0, L_0x2b2be30; 1 drivers +v0x22a09b0_0 .net "out1", 0 0, L_0x2b3f970; 1 drivers +v0x22a4630_0 .net "out2", 0 0, L_0x2b3fa60; 1 drivers +v0x22630a0_0 .net "out3", 0 0, L_0x2b40090; 1 drivers +S_0x2208ee0 .scope module, "OneMux" "FourInMux" 3 67, 3 125, S_0x2206450; + .timescale -9 -12; +L_0x2b409d0/d .functor NOT 1, L_0x2b40e90, C4<0>, C4<0>, C4<0>; +L_0x2b409d0 .delay (10000,10000,10000) L_0x2b409d0/d; +L_0x2b419a0/d .functor NOT 1, L_0x2b40fc0, C4<0>, C4<0>, C4<0>; +L_0x2b419a0 .delay (10000,10000,10000) L_0x2b419a0/d; +L_0x2b41a40/d .functor NAND 1, L_0x2b409d0, L_0x2b419a0, L_0x2b410f0, C4<1>; +L_0x2b41a40 .delay (10000,10000,10000) L_0x2b41a40/d; +L_0x2b41b80/d .functor NAND 1, L_0x2b40e90, L_0x2b419a0, L_0x2b41190, C4<1>; +L_0x2b41b80 .delay (10000,10000,10000) L_0x2b41b80/d; +L_0x2b41c70/d .functor NAND 1, L_0x2b409d0, L_0x2b40fc0, L_0x2b41230, C4<1>; +L_0x2b41c70 .delay (10000,10000,10000) L_0x2b41c70/d; +L_0x2b41d60/d .functor NAND 1, L_0x2b40e90, L_0x2b40fc0, L_0x2b41320, C4<1>; +L_0x2b41d60 .delay (10000,10000,10000) L_0x2b41d60/d; +L_0x2b41ed0/d .functor NAND 1, L_0x2b41a40, L_0x2b41b80, L_0x2b41c70, L_0x2b41d60; +L_0x2b41ed0 .delay (10000,10000,10000) L_0x2b41ed0/d; +v0x2267110_0 .net "S0", 0 0, L_0x2b40e90; 1 drivers +v0x2268f40_0 .net "S1", 0 0, L_0x2b40fc0; 1 drivers +v0x2269190_0 .net "in0", 0 0, L_0x2b410f0; 1 drivers +v0x2262340_0 .net "in1", 0 0, L_0x2b41190; 1 drivers +v0x22625c0_0 .net "in2", 0 0, L_0x2b41230; 1 drivers +v0x22643f0_0 .net "in3", 0 0, L_0x2b41320; 1 drivers +v0x2264640_0 .net "nS0", 0 0, L_0x2b409d0; 1 drivers +v0x227a4f0_0 .net "nS1", 0 0, L_0x2b419a0; 1 drivers +v0x227f020_0 .net "out", 0 0, L_0x2b41ed0; 1 drivers +v0x227fef0_0 .net "out0", 0 0, L_0x2b41a40; 1 drivers +v0x2283b70_0 .net "out1", 0 0, L_0x2b41b80; 1 drivers +v0x2284a40_0 .net "out2", 0 0, L_0x2b41c70; 1 drivers +v0x22886c0_0 .net "out3", 0 0, L_0x2b41d60; 1 drivers +S_0x22043d0 .scope module, "TwoMux" "TwoInMux" 3 68, 3 109, S_0x2206450; + .timescale -9 -12; +L_0x2b41410/d .functor NOT 1, L_0x2b42c80, C4<0>, C4<0>, C4<0>; +L_0x2b41410 .delay (10000,10000,10000) L_0x2b41410/d; +L_0x2b41500/d .functor AND 1, L_0x2b42180, L_0x2b41410, C4<1>, C4<1>; +L_0x2b41500 .delay (20000,20000,20000) L_0x2b41500/d; +L_0x2b415f0/d .functor AND 1, L_0x2b42270, L_0x2b42c80, C4<1>, C4<1>; +L_0x2b415f0 .delay (20000,20000,20000) L_0x2b415f0/d; +L_0x2b416e0/d .functor OR 1, L_0x2b41500, L_0x2b415f0, C4<0>, C4<0>; +L_0x2b416e0 .delay (20000,20000,20000) L_0x2b416e0/d; +v0x2280370_0 .net "S", 0 0, L_0x2b42c80; 1 drivers +v0x22805c0_0 .net "in0", 0 0, L_0x2b42180; 1 drivers +v0x2279ce0_0 .net "in1", 0 0, L_0x2b42270; 1 drivers +v0x22752d0_0 .net "nS", 0 0, L_0x2b41410; 1 drivers +v0x22708c0_0 .net "out0", 0 0, L_0x2b41500; 1 drivers +v0x226beb0_0 .net "out1", 0 0, L_0x2b415f0; 1 drivers +v0x2266e90_0 .net "outfinal", 0 0, L_0x2b416e0; 1 drivers +S_0x2258160 .scope generate, "muxbits[18]" "muxbits[18]" 3 64, 3 64, S_0x1f6b890; + .timescale -9 -12; +P_0x27428a8 .param/l "i" 3 64, +C4<010010>; +L_0x2b44ad0/d .functor OR 1, L_0x2b44bd0, L_0x2b44c70, C4<0>, C4<0>; +L_0x2b44ad0 .delay (20000,20000,20000) L_0x2b44ad0/d; +v0x227e2c0_0 .net *"_s15", 0 0, L_0x2b44bd0; 1 drivers +v0x227e540_0 .net *"_s16", 0 0, L_0x2b44c70; 1 drivers +S_0x22015c0 .scope module, "ZeroMux" "FourInMux" 3 66, 3 125, S_0x2258160; + .timescale -9 -12; +L_0x2b426d0/d .functor NOT 1, L_0x2b42d20, C4<0>, C4<0>, C4<0>; +L_0x2b426d0 .delay (10000,10000,10000) L_0x2b426d0/d; +L_0x2b427c0/d .functor NOT 1, L_0x2b42e50, C4<0>, C4<0>, C4<0>; +L_0x2b427c0 .delay (10000,10000,10000) L_0x2b427c0/d; +L_0x2b42860/d .functor NAND 1, L_0x2b426d0, L_0x2b427c0, L_0x2b42f80, C4<1>; +L_0x2b42860 .delay (10000,10000,10000) L_0x2b42860/d; +L_0x2b429a0/d .functor NAND 1, L_0x2b42d20, L_0x2b427c0, L_0x2b43020, C4<1>; +L_0x2b429a0 .delay (10000,10000,10000) L_0x2b429a0/d; +L_0x2b42a90/d .functor NAND 1, L_0x2b426d0, L_0x2b42e50, L_0x2b430c0, C4<1>; +L_0x2b42a90 .delay (10000,10000,10000) L_0x2b42a90/d; +L_0x2b42b80/d .functor NAND 1, L_0x2b42d20, L_0x2b42e50, L_0x2b431b0, C4<1>; +L_0x2b42b80 .delay (10000,10000,10000) L_0x2b42b80/d; +L_0x2b43850/d .functor NAND 1, L_0x2b42860, L_0x2b429a0, L_0x2b42a90, L_0x2b42b80; +L_0x2b43850 .delay (10000,10000,10000) L_0x2b43850/d; +v0x22a1080_0 .net "S0", 0 0, L_0x2b42d20; 1 drivers +v0x229a7b0_0 .net "S1", 0 0, L_0x2b42e50; 1 drivers +v0x2295da0_0 .net "in0", 0 0, L_0x2b42f80; 1 drivers +v0x2291390_0 .net "in1", 0 0, L_0x2b43020; 1 drivers +v0x228c980_0 .net "in2", 0 0, L_0x2b430c0; 1 drivers +v0x2287960_0 .net "in3", 0 0, L_0x2b431b0; 1 drivers +v0x2287be0_0 .net "nS0", 0 0, L_0x2b426d0; 1 drivers +v0x2289a10_0 .net "nS1", 0 0, L_0x2b427c0; 1 drivers +v0x2289c60_0 .net "out", 0 0, L_0x2b43850; 1 drivers +v0x2282e10_0 .net "out0", 0 0, L_0x2b42860; 1 drivers +v0x2283090_0 .net "out1", 0 0, L_0x2b429a0; 1 drivers +v0x2284ec0_0 .net "out2", 0 0, L_0x2b42a90; 1 drivers +v0x2285110_0 .net "out3", 0 0, L_0x2b42b80; 1 drivers +S_0x22031f0 .scope module, "OneMux" "FourInMux" 3 67, 3 125, S_0x2258160; + .timescale -9 -12; +L_0x2b432a0/d .functor NOT 1, L_0x2b449a0, C4<0>, C4<0>, C4<0>; +L_0x2b432a0 .delay (10000,10000,10000) L_0x2b432a0/d; +L_0x2b43350/d .functor NOT 1, L_0x2b43b00, C4<0>, C4<0>, C4<0>; +L_0x2b43350 .delay (10000,10000,10000) L_0x2b43350/d; +L_0x2b433f0/d .functor NAND 1, L_0x2b432a0, L_0x2b43350, L_0x2b43c30, C4<1>; +L_0x2b433f0 .delay (10000,10000,10000) L_0x2b433f0/d; +L_0x2b43530/d .functor NAND 1, L_0x2b449a0, L_0x2b43350, L_0x2b43cd0, C4<1>; +L_0x2b43530 .delay (10000,10000,10000) L_0x2b43530/d; +L_0x2b43620/d .functor NAND 1, L_0x2b432a0, L_0x2b43b00, L_0x2b43d70, C4<1>; +L_0x2b43620 .delay (10000,10000,10000) L_0x2b43620/d; +L_0x2b43740/d .functor NAND 1, L_0x2b449a0, L_0x2b43b00, L_0x2b43e60, C4<1>; +L_0x2b43740 .delay (10000,10000,10000) L_0x2b43740/d; +L_0x2b446f0/d .functor NAND 1, L_0x2b433f0, L_0x2b43530, L_0x2b43620, L_0x2b43740; +L_0x2b446f0 .delay (10000,10000,10000) L_0x2b446f0/d; +v0x22b1e50_0 .net "S0", 0 0, L_0x2b449a0; 1 drivers +v0x22ad440_0 .net "S1", 0 0, L_0x2b43b00; 1 drivers +v0x22a8420_0 .net "in0", 0 0, L_0x2b43c30; 1 drivers +v0x22a86a0_0 .net "in1", 0 0, L_0x2b43cd0; 1 drivers +v0x22aa4d0_0 .net "in2", 0 0, L_0x2b43d70; 1 drivers +v0x22aa720_0 .net "in3", 0 0, L_0x2b43e60; 1 drivers +v0x22a38d0_0 .net "nS0", 0 0, L_0x2b432a0; 1 drivers +v0x22a3b50_0 .net "nS1", 0 0, L_0x2b43350; 1 drivers +v0x22a5980_0 .net "out", 0 0, L_0x2b446f0; 1 drivers +v0x22a5bd0_0 .net "out0", 0 0, L_0x2b433f0; 1 drivers +v0x229ed80_0 .net "out1", 0 0, L_0x2b43530; 1 drivers +v0x229f000_0 .net "out2", 0 0, L_0x2b43620; 1 drivers +v0x22a0e30_0 .net "out3", 0 0, L_0x2b43740; 1 drivers +S_0x22034b0 .scope module, "TwoMux" "TwoInMux" 3 68, 3 109, S_0x2258160; + .timescale -9 -12; +L_0x2b43f50/d .functor NOT 1, L_0x2b44400, C4<0>, C4<0>, C4<0>; +L_0x2b43f50 .delay (10000,10000,10000) L_0x2b43f50/d; +L_0x2b44040/d .functor AND 1, L_0x2b444a0, L_0x2b43f50, C4<1>, C4<1>; +L_0x2b44040 .delay (20000,20000,20000) L_0x2b44040/d; +L_0x2b44130/d .functor AND 1, L_0x2b44590, L_0x2b44400, C4<1>, C4<1>; +L_0x2b44130 .delay (20000,20000,20000) L_0x2b44130/d; +L_0x2b44220/d .functor OR 1, L_0x2b44040, L_0x2b44130, C4<0>, C4<0>; +L_0x2b44220 .delay (20000,20000,20000) L_0x2b44220/d; +v0x22bf840_0 .net "S", 0 0, L_0x2b44400; 1 drivers +v0x22bfac0_0 .net "in0", 0 0, L_0x2b444a0; 1 drivers +v0x22c18f0_0 .net "in1", 0 0, L_0x2b44590; 1 drivers +v0x22c1b40_0 .net "nS", 0 0, L_0x2b43f50; 1 drivers +v0x22bcda0_0 .net "out0", 0 0, L_0x2b44040; 1 drivers +v0x22bcff0_0 .net "out1", 0 0, L_0x2b44130; 1 drivers +v0x22b6860_0 .net "outfinal", 0 0, L_0x2b44220; 1 drivers +S_0x2227210 .scope generate, "muxbits[19]" "muxbits[19]" 3 64, 3 64, S_0x1f6b890; + .timescale -9 -12; +P_0x275f078 .param/l "i" 3 64, +C4<010011>; +L_0x2b471f0/d .functor OR 1, L_0x2b47330, L_0x2b473d0, C4<0>, C4<0>; +L_0x2b471f0 .delay (20000,20000,20000) L_0x2b471f0/d; +v0x22c6440_0 .net *"_s15", 0 0, L_0x2b47330; 1 drivers +v0x22c6690_0 .net *"_s16", 0 0, L_0x2b473d0; 1 drivers +S_0x22217d0 .scope module, "ZeroMux" "FourInMux" 3 66, 3 125, S_0x2227210; + .timescale -9 -12; +L_0x2b44d60/d .functor NOT 1, L_0x2b46360, C4<0>, C4<0>, C4<0>; +L_0x2b44d60 .delay (10000,10000,10000) L_0x2b44d60/d; +L_0x2b44e50/d .functor NOT 1, L_0x2b45780, C4<0>, C4<0>, C4<0>; +L_0x2b44e50 .delay (10000,10000,10000) L_0x2b44e50/d; +L_0x2b44ef0/d .functor NAND 1, L_0x2b44d60, L_0x2b44e50, L_0x2b458b0, C4<1>; +L_0x2b44ef0 .delay (10000,10000,10000) L_0x2b44ef0/d; +L_0x2b45030/d .functor NAND 1, L_0x2b46360, L_0x2b44e50, L_0x2b45950, C4<1>; +L_0x2b45030 .delay (10000,10000,10000) L_0x2b45030/d; +L_0x2b45120/d .functor NAND 1, L_0x2b44d60, L_0x2b45780, L_0x2b459f0, C4<1>; +L_0x2b45120 .delay (10000,10000,10000) L_0x2b45120/d; +L_0x2b45210/d .functor NAND 1, L_0x2b46360, L_0x2b45780, L_0x2b45ae0, C4<1>; +L_0x2b45210 .delay (10000,10000,10000) L_0x2b45210/d; +L_0x2b45350/d .functor NAND 1, L_0x2b44ef0, L_0x2b45030, L_0x2b45120, L_0x2b45210; +L_0x2b45350 .delay (10000,10000,10000) L_0x2b45350/d; +v0x22db7d0_0 .net "S0", 0 0, L_0x2b46360; 1 drivers +v0x22dba50_0 .net "S1", 0 0, L_0x2b45780; 1 drivers +v0x22dd880_0 .net "in0", 0 0, L_0x2b458b0; 1 drivers +v0x22ddad0_0 .net "in1", 0 0, L_0x2b45950; 1 drivers +v0x22d7320_0 .net "in2", 0 0, L_0x2b459f0; 1 drivers +v0x22d2910_0 .net "in3", 0 0, L_0x2b45ae0; 1 drivers +v0x22cdf00_0 .net "nS0", 0 0, L_0x2b44d60; 1 drivers +v0x22c8ee0_0 .net "nS1", 0 0, L_0x2b44e50; 1 drivers +v0x22c9160_0 .net "out", 0 0, L_0x2b45350; 1 drivers +v0x22caf90_0 .net "out0", 0 0, L_0x2b44ef0; 1 drivers +v0x22cb1e0_0 .net "out1", 0 0, L_0x2b45030; 1 drivers +v0x22c4390_0 .net "out2", 0 0, L_0x2b45120; 1 drivers +v0x22c4610_0 .net "out3", 0 0, L_0x2b45210; 1 drivers +S_0x22058c0 .scope module, "OneMux" "FourInMux" 3 67, 3 125, S_0x2227210; + .timescale -9 -12; +L_0x2b45bd0/d .functor NOT 1, L_0x2b46400, C4<0>, C4<0>, C4<0>; +L_0x2b45bd0 .delay (10000,10000,10000) L_0x2b45bd0/d; +L_0x2b45cc0/d .functor NOT 1, L_0x2b46530, C4<0>, C4<0>, C4<0>; +L_0x2b45cc0 .delay (10000,10000,10000) L_0x2b45cc0/d; +L_0x2b45d60/d .functor NAND 1, L_0x2b45bd0, L_0x2b45cc0, L_0x2b46660, C4<1>; +L_0x2b45d60 .delay (10000,10000,10000) L_0x2b45d60/d; +L_0x2b45ea0/d .functor NAND 1, L_0x2b46400, L_0x2b45cc0, L_0x2b46700, C4<1>; +L_0x2b45ea0 .delay (10000,10000,10000) L_0x2b45ea0/d; +L_0x2b45f90/d .functor NAND 1, L_0x2b45bd0, L_0x2b46530, L_0x2b467a0, C4<1>; +L_0x2b45f90 .delay (10000,10000,10000) L_0x2b45f90/d; +L_0x2b46080/d .functor NAND 1, L_0x2b46400, L_0x2b46530, L_0x2b46890, C4<1>; +L_0x2b46080 .delay (10000,10000,10000) L_0x2b46080/d; +L_0x2b461f0/d .functor NAND 1, L_0x2b45d60, L_0x2b45ea0, L_0x2b45f90, L_0x2b46080; +L_0x2b461f0 .delay (10000,10000,10000) L_0x2b461f0/d; +v0x2313850_0 .net "S0", 0 0, L_0x2b46400; 1 drivers +v0x22e99c0_0 .net "S1", 0 0, L_0x2b46530; 1 drivers +v0x22e9c40_0 .net "in0", 0 0, L_0x2b46660; 1 drivers +v0x22eba70_0 .net "in1", 0 0, L_0x2b46700; 1 drivers +v0x22ebcc0_0 .net "in2", 0 0, L_0x2b467a0; 1 drivers +v0x22e4e70_0 .net "in3", 0 0, L_0x2b46890; 1 drivers +v0x22e50f0_0 .net "nS0", 0 0, L_0x2b45bd0; 1 drivers +v0x22e6f20_0 .net "nS1", 0 0, L_0x2b45cc0; 1 drivers +v0x22e7170_0 .net "out", 0 0, L_0x2b461f0; 1 drivers +v0x22e0320_0 .net "out0", 0 0, L_0x2b45d60; 1 drivers +v0x22e05a0_0 .net "out1", 0 0, L_0x2b45ea0; 1 drivers +v0x22e23d0_0 .net "out2", 0 0, L_0x2b45f90; 1 drivers +v0x22e2620_0 .net "out3", 0 0, L_0x2b46080; 1 drivers +S_0x22244f0 .scope module, "TwoMux" "TwoInMux" 3 68, 3 109, S_0x2227210; + .timescale -9 -12; +L_0x2b46980/d .functor NOT 1, L_0x2b46e30, C4<0>, C4<0>, C4<0>; +L_0x2b46980 .delay (10000,10000,10000) L_0x2b46980/d; +L_0x2b46a70/d .functor AND 1, L_0x2b46ed0, L_0x2b46980, C4<1>, C4<1>; +L_0x2b46a70 .delay (20000,20000,20000) L_0x2b46a70/d; +L_0x2b46b60/d .functor AND 1, L_0x2b47db0, L_0x2b46e30, C4<1>, C4<1>; +L_0x2b46b60 .delay (20000,20000,20000) L_0x2b46b60/d; +L_0x2b46c50/d .functor OR 1, L_0x2b46a70, L_0x2b46b60, C4<0>, C4<0>; +L_0x2b46c50 .delay (20000,20000,20000) L_0x2b46c50/d; +v0x22fa5b0_0 .net "S", 0 0, L_0x2b46e30; 1 drivers +v0x230ceb0_0 .net "in0", 0 0, L_0x2b46ed0; 1 drivers +v0x22f6650_0 .net "in1", 0 0, L_0x2b47db0; 1 drivers +v0x230e3d0_0 .net "nS", 0 0, L_0x2b46980; 1 drivers +v0x230f8f0_0 .net "out0", 0 0, L_0x2b46a70; 1 drivers +v0x2310e10_0 .net "out1", 0 0, L_0x2b46b60; 1 drivers +v0x2312330_0 .net "outfinal", 0 0, L_0x2b46c50; 1 drivers +S_0x22403f0 .scope generate, "muxbits[20]" "muxbits[20]" 3 64, 3 64, S_0x1f6b890; + .timescale -9 -12; +P_0x25c7678 .param/l "i" 3 64, +C4<010100>; +L_0x2b49910/d .functor OR 1, L_0x2b4a800, L_0x2b4a8a0, C4<0>, C4<0>; +L_0x2b49910 .delay (20000,20000,20000) L_0x2b49910/d; +v0x231b710_0 .net *"_s15", 0 0, L_0x2b4a800; 1 drivers +v0x22f9090_0 .net *"_s16", 0 0, L_0x2b4a8a0; 1 drivers +S_0x223a9b0 .scope module, "ZeroMux" "FourInMux" 3 66, 3 125, S_0x22403f0; + .timescale -9 -12; +L_0x2b474c0/d .functor NOT 1, L_0x2b48ae0, C4<0>, C4<0>, C4<0>; +L_0x2b474c0 .delay (10000,10000,10000) L_0x2b474c0/d; +L_0x2b475b0/d .functor NOT 1, L_0x2b48c10, C4<0>, C4<0>, C4<0>; +L_0x2b475b0 .delay (10000,10000,10000) L_0x2b475b0/d; +L_0x2b47650/d .functor NAND 1, L_0x2b474c0, L_0x2b475b0, L_0x2b47e50, C4<1>; +L_0x2b47650 .delay (10000,10000,10000) L_0x2b47650/d; +L_0x2b47790/d .functor NAND 1, L_0x2b48ae0, L_0x2b475b0, L_0x2b47ef0, C4<1>; +L_0x2b47790 .delay (10000,10000,10000) L_0x2b47790/d; +L_0x2b47880/d .functor NAND 1, L_0x2b474c0, L_0x2b48c10, L_0x2b47f90, C4<1>; +L_0x2b47880 .delay (10000,10000,10000) L_0x2b47880/d; +L_0x2b47970/d .functor NAND 1, L_0x2b48ae0, L_0x2b48c10, L_0x2b48030, C4<1>; +L_0x2b47970 .delay (10000,10000,10000) L_0x2b47970/d; +L_0x2b47ab0/d .functor NAND 1, L_0x2b47650, L_0x2b47790, L_0x2b47880, L_0x2b47970; +L_0x2b47ab0 .delay (10000,10000,10000) L_0x2b47ab0/d; +v0x23e3740_0 .net "S0", 0 0, L_0x2b48ae0; 1 drivers +v0x23e95a0_0 .net "S1", 0 0, L_0x2b48c10; 1 drivers +v0x2400e60_0 .net "in0", 0 0, L_0x2b47e50; 1 drivers +v0x2406cc0_0 .net "in1", 0 0, L_0x2b47ef0; 1 drivers +v0x240cb20_0 .net "in2", 0 0, L_0x2b47f90; 1 drivers +v0x258bd90_0 .net "in3", 0 0, L_0x2b48030; 1 drivers +v0x22fbe20_0 .net "nS0", 0 0, L_0x2b474c0; 1 drivers +v0x2314d70_0 .net "nS1", 0 0, L_0x2b475b0; 1 drivers +v0x2316290_0 .net "out", 0 0, L_0x2b47ab0; 1 drivers +v0x23177b0_0 .net "out0", 0 0, L_0x2b47650; 1 drivers +v0x2318cd0_0 .net "out1", 0 0, L_0x2b47790; 1 drivers +v0x231a1f0_0 .net "out2", 0 0, L_0x2b47880; 1 drivers +v0x22f7b70_0 .net "out3", 0 0, L_0x2b47970; 1 drivers +S_0x223d6d0 .scope module, "OneMux" "FourInMux" 3 67, 3 125, S_0x22403f0; + .timescale -9 -12; +L_0x2b48120/d .functor NOT 1, L_0x2b489f0, C4<0>, C4<0>, C4<0>; +L_0x2b48120 .delay (10000,10000,10000) L_0x2b48120/d; +L_0x2b48210/d .functor NOT 1, L_0x2b48d40, C4<0>, C4<0>, C4<0>; +L_0x2b48210 .delay (10000,10000,10000) L_0x2b48210/d; +L_0x2b482b0/d .functor NAND 1, L_0x2b48120, L_0x2b48210, L_0x2b48e70, C4<1>; +L_0x2b482b0 .delay (10000,10000,10000) L_0x2b482b0/d; +L_0x2b483f0/d .functor NAND 1, L_0x2b489f0, L_0x2b48210, L_0x2b48f10, C4<1>; +L_0x2b483f0 .delay (10000,10000,10000) L_0x2b483f0/d; +L_0x2b484e0/d .functor NAND 1, L_0x2b48120, L_0x2b48d40, L_0x2b48fb0, C4<1>; +L_0x2b484e0 .delay (10000,10000,10000) L_0x2b484e0/d; +L_0x2b485d0/d .functor NAND 1, L_0x2b489f0, L_0x2b48d40, L_0x2b49050, C4<1>; +L_0x2b485d0 .delay (10000,10000,10000) L_0x2b485d0/d; +L_0x2b48740/d .functor NAND 1, L_0x2b482b0, L_0x2b483f0, L_0x2b484e0, L_0x2b485d0; +L_0x2b48740 .delay (10000,10000,10000) L_0x2b48740/d; +v0x241d3f0_0 .net "S0", 0 0, L_0x2b489f0; 1 drivers +v0x2438a40_0 .net "S1", 0 0, L_0x2b48d40; 1 drivers +v0x1f6b360_0 .net "in0", 0 0, L_0x2b48e70; 1 drivers +v0x2381d40_0 .net "in1", 0 0, L_0x2b48f10; 1 drivers +v0x2387990_0 .net "in2", 0 0, L_0x2b48fb0; 1 drivers +v0x236ae00_0 .net "in3", 0 0, L_0x2b49050; 1 drivers +v0x238d5e0_0 .net "nS0", 0 0, L_0x2b48120; 1 drivers +v0x239e850_0 .net "nS1", 0 0, L_0x2b48210; 1 drivers +v0x23a44a0_0 .net "out", 0 0, L_0x2b48740; 1 drivers +v0x23aa0f0_0 .net "out0", 0 0, L_0x2b482b0; 1 drivers +v0x23c0f80_0 .net "out1", 0 0, L_0x2b483f0; 1 drivers +v0x23c6bd0_0 .net "out2", 0 0, L_0x2b484e0; 1 drivers +v0x23cc820_0 .net "out3", 0 0, L_0x2b485d0; 1 drivers +S_0x2202ad0 .scope module, "TwoMux" "TwoInMux" 3 68, 3 109, S_0x22403f0; + .timescale -9 -12; +L_0x2b49140/d .functor NOT 1, L_0x2b495f0, C4<0>, C4<0>, C4<0>; +L_0x2b49140 .delay (10000,10000,10000) L_0x2b49140/d; +L_0x2b49230/d .functor AND 1, L_0x2b49690, L_0x2b49140, C4<1>, C4<1>; +L_0x2b49230 .delay (20000,20000,20000) L_0x2b49230/d; +L_0x2b49320/d .functor AND 1, L_0x2b49780, L_0x2b495f0, C4<1>, C4<1>; +L_0x2b49320 .delay (20000,20000,20000) L_0x2b49320/d; +L_0x2b49410/d .functor OR 1, L_0x2b49230, L_0x2b49320, C4<0>, C4<0>; +L_0x2b49410 .delay (20000,20000,20000) L_0x2b49410/d; +v0x24b0ba0_0 .net "S", 0 0, L_0x2b495f0; 1 drivers +v0x24b4cb0_0 .net "in0", 0 0, L_0x2b49690; 1 drivers +v0x242b8e0_0 .net "in1", 0 0, L_0x2b49780; 1 drivers +v0x242f0e0_0 .net "nS", 0 0, L_0x2b49140; 1 drivers +v0x2430620_0 .net "out0", 0 0, L_0x2b49230; 1 drivers +v0x2433d90_0 .net "out1", 0 0, L_0x2b49320; 1 drivers +v0x24352d0_0 .net "outfinal", 0 0, L_0x2b49410; 1 drivers +S_0x2259ee0 .scope generate, "muxbits[21]" "muxbits[21]" 3 64, 3 64, S_0x1f6b890; + .timescale -9 -12; +P_0x25f0a58 .param/l "i" 3 64, +C4<010101>; +L_0x2b32190/d .functor OR 1, L_0x2b4bbd0, L_0x2b4bc70, C4<0>, C4<0>; +L_0x2b32190 .delay (20000,20000,20000) L_0x2b32190/d; +v0x24ac7e0_0 .net *"_s15", 0 0, L_0x2b4bbd0; 1 drivers +v0x242a450_0 .net *"_s16", 0 0, L_0x2b4bc70; 1 drivers +S_0x2243110 .scope module, "ZeroMux" "FourInMux" 3 66, 3 125, S_0x2259ee0; + .timescale -9 -12; +L_0x2b49a90/d .functor NOT 1, L_0x2b4a330, C4<0>, C4<0>, C4<0>; +L_0x2b49a90 .delay (10000,10000,10000) L_0x2b49a90/d; +L_0x2b49b80/d .functor NOT 1, L_0x2b4a460, C4<0>, C4<0>, C4<0>; +L_0x2b49b80 .delay (10000,10000,10000) L_0x2b49b80/d; +L_0x2b49c20/d .functor NAND 1, L_0x2b49a90, L_0x2b49b80, L_0x2b4a590, C4<1>; +L_0x2b49c20 .delay (10000,10000,10000) L_0x2b49c20/d; +L_0x2b49d60/d .functor NAND 1, L_0x2b4a330, L_0x2b49b80, L_0x2b4a630, C4<1>; +L_0x2b49d60 .delay (10000,10000,10000) L_0x2b49d60/d; +L_0x2b49e50/d .functor NAND 1, L_0x2b49a90, L_0x2b4a460, L_0x2b4a6d0, C4<1>; +L_0x2b49e50 .delay (10000,10000,10000) L_0x2b49e50/d; +L_0x2b49f40/d .functor NAND 1, L_0x2b4a330, L_0x2b4a460, L_0x2b4a990, C4<1>; +L_0x2b49f40 .delay (10000,10000,10000) L_0x2b49f40/d; +L_0x2b4a080/d .functor NAND 1, L_0x2b49c20, L_0x2b49d60, L_0x2b49e50, L_0x2b49f40; +L_0x2b4a080 .delay (10000,10000,10000) L_0x2b4a080/d; +v0x248fe30_0 .net "S0", 0 0, L_0x2b4a330; 1 drivers +v0x24935a0_0 .net "S1", 0 0, L_0x2b4a460; 1 drivers +v0x2494ae0_0 .net "in0", 0 0, L_0x2b4a590; 1 drivers +v0x2426c70_0 .net "in1", 0 0, L_0x2b4a630; 1 drivers +v0x2498250_0 .net "in2", 0 0, L_0x2b4a6d0; 1 drivers +v0x2499790_0 .net "in3", 0 0, L_0x2b4a990; 1 drivers +v0x249cf00_0 .net "nS0", 0 0, L_0x2b49a90; 1 drivers +v0x249e440_0 .net "nS1", 0 0, L_0x2b49b80; 1 drivers +v0x24a1a70_0 .net "out", 0 0, L_0x2b4a080; 1 drivers +v0x24a2f00_0 .net "out0", 0 0, L_0x2b49c20; 1 drivers +v0x24a66e0_0 .net "out1", 0 0, L_0x2b49d60; 1 drivers +v0x24a7b70_0 .net "out2", 0 0, L_0x2b49e50; 1 drivers +v0x24ab350_0 .net "out3", 0 0, L_0x2b49f40; 1 drivers +S_0x2245e30 .scope module, "OneMux" "FourInMux" 3 67, 3 125, S_0x2259ee0; + .timescale -9 -12; +L_0x2b4aa80/d .functor NOT 1, L_0x2b4b310, C4<0>, C4<0>, C4<0>; +L_0x2b4aa80 .delay (10000,10000,10000) L_0x2b4aa80/d; +L_0x2b4ab30/d .functor NOT 1, L_0x2b4b440, C4<0>, C4<0>, C4<0>; +L_0x2b4ab30 .delay (10000,10000,10000) L_0x2b4ab30/d; +L_0x2b4abd0/d .functor NAND 1, L_0x2b4aa80, L_0x2b4ab30, L_0x2b4b570, C4<1>; +L_0x2b4abd0 .delay (10000,10000,10000) L_0x2b4abd0/d; +L_0x2b4ad10/d .functor NAND 1, L_0x2b4b310, L_0x2b4ab30, L_0x2b4b610, C4<1>; +L_0x2b4ad10 .delay (10000,10000,10000) L_0x2b4ad10/d; +L_0x2b4ae00/d .functor NAND 1, L_0x2b4aa80, L_0x2b4b440, L_0x2b4c4c0, C4<1>; +L_0x2b4ae00 .delay (10000,10000,10000) L_0x2b4ae00/d; +L_0x2b4aef0/d .functor NAND 1, L_0x2b4b310, L_0x2b4b440, L_0x2b4c5b0, C4<1>; +L_0x2b4aef0 .delay (10000,10000,10000) L_0x2b4aef0/d; +L_0x2b4b060/d .functor NAND 1, L_0x2b4abd0, L_0x2b4ad10, L_0x2b4ae00, L_0x2b4aef0; +L_0x2b4b060 .delay (10000,10000,10000) L_0x2b4b060/d; +v0x2471eb0_0 .net "S0", 0 0, L_0x2b4b310; 1 drivers +v0x24733f0_0 .net "S1", 0 0, L_0x2b4b440; 1 drivers +v0x2476b60_0 .net "in0", 0 0, L_0x2b4b570; 1 drivers +v0x24780a0_0 .net "in1", 0 0, L_0x2b4b610; 1 drivers +v0x247b810_0 .net "in2", 0 0, L_0x2b4c4c0; 1 drivers +v0x247cd50_0 .net "in3", 0 0, L_0x2b4c5b0; 1 drivers +v0x24257e0_0 .net "nS0", 0 0, L_0x2b4aa80; 1 drivers +v0x2481850_0 .net "nS1", 0 0, L_0x2b4ab30; 1 drivers +v0x2485040_0 .net "out", 0 0, L_0x2b4b060; 1 drivers +v0x24864d0_0 .net "out0", 0 0, L_0x2b4abd0; 1 drivers +v0x2489cb0_0 .net "out1", 0 0, L_0x2b4ad10; 1 drivers +v0x248b140_0 .net "out2", 0 0, L_0x2b4ae00; 1 drivers +v0x248e920_0 .net "out3", 0 0, L_0x2b4aef0; 1 drivers +S_0x2248b50 .scope module, "TwoMux" "TwoInMux" 3 68, 3 109, S_0x2259ee0; + .timescale -9 -12; +L_0x2b4af80/d .functor NOT 1, L_0x2b4b7d0, C4<0>, C4<0>, C4<0>; +L_0x2b4af80 .delay (10000,10000,10000) L_0x2b4af80/d; +L_0x2b31e70/d .functor AND 1, L_0x2b4b870, L_0x2b4af80, C4<1>, C4<1>; +L_0x2b31e70 .delay (20000,20000,20000) L_0x2b31e70/d; +L_0x2b31f60/d .functor AND 1, L_0x2b4b960, L_0x2b4b7d0, C4<1>, C4<1>; +L_0x2b31f60 .delay (20000,20000,20000) L_0x2b31f60/d; +L_0x2b32050/d .functor OR 1, L_0x2b31e70, L_0x2b31f60, C4<0>, C4<0>; +L_0x2b32050 .delay (20000,20000,20000) L_0x2b32050/d; +v0x2463930_0 .net "S", 0 0, L_0x2b4b7d0; 1 drivers +v0x2464dc0_0 .net "in0", 0 0, L_0x2b4b870; 1 drivers +v0x2422000_0 .net "in1", 0 0, L_0x2b4b960; 1 drivers +v0x24685a0_0 .net "nS", 0 0, L_0x2b4af80; 1 drivers +v0x2469a30_0 .net "out0", 0 0, L_0x2b31e70; 1 drivers +v0x246d210_0 .net "out1", 0 0, L_0x2b31f60; 1 drivers +v0x246e6a0_0 .net "outfinal", 0 0, L_0x2b32050; 1 drivers +S_0x221eab0 .scope generate, "muxbits[22]" "muxbits[22]" 3 64, 3 64, S_0x1f6b890; + .timescale -9 -12; +P_0x1d278c8 .param/l "i" 3 64, +C4<010110>; +L_0x2b4ea20/d .functor OR 1, L_0x2b4eb60, L_0x2b4fca0, C4<0>, C4<0>; +L_0x2b4ea20 .delay (20000,20000,20000) L_0x2b4ea20/d; +v0x245b640_0 .net *"_s15", 0 0, L_0x2b4eb60; 1 drivers +v0x2460140_0 .net *"_s16", 0 0, L_0x2b4fca0; 1 drivers +S_0x225a130 .scope module, "ZeroMux" "FourInMux" 3 66, 3 125, S_0x221eab0; + .timescale -9 -12; +L_0x2b4bd60/d .functor NOT 1, L_0x2b4ceb0, C4<0>, C4<0>, C4<0>; +L_0x2b4bd60 .delay (10000,10000,10000) L_0x2b4bd60/d; +L_0x2b4be50/d .functor NOT 1, L_0x2b4cfe0, C4<0>, C4<0>, C4<0>; +L_0x2b4be50 .delay (10000,10000,10000) L_0x2b4be50/d; +L_0x2b4bef0/d .functor NAND 1, L_0x2b4bd60, L_0x2b4be50, L_0x2b4d110, C4<1>; +L_0x2b4bef0 .delay (10000,10000,10000) L_0x2b4bef0/d; +L_0x2b4c030/d .functor NAND 1, L_0x2b4ceb0, L_0x2b4be50, L_0x2b4d1b0, C4<1>; +L_0x2b4c030 .delay (10000,10000,10000) L_0x2b4c030/d; +L_0x2b4c120/d .functor NAND 1, L_0x2b4bd60, L_0x2b4cfe0, L_0x2b4d250, C4<1>; +L_0x2b4c120 .delay (10000,10000,10000) L_0x2b4c120/d; +L_0x2b4c240/d .functor NAND 1, L_0x2b4ceb0, L_0x2b4cfe0, L_0x2b4d340, C4<1>; +L_0x2b4c240 .delay (10000,10000,10000) L_0x2b4c240/d; +L_0x2b4c3b0/d .functor NAND 1, L_0x2b4bef0, L_0x2b4c030, L_0x2b4c120, L_0x2b4c240; +L_0x2b4c3b0 .delay (10000,10000,10000) L_0x2b4c3b0/d; +v0x2442220_0 .net "S0", 0 0, L_0x2b4ceb0; 1 drivers +v0x24436b0_0 .net "S1", 0 0, L_0x2b4cfe0; 1 drivers +v0x2446e90_0 .net "in0", 0 0, L_0x2b4d110; 1 drivers +v0x2448320_0 .net "in1", 0 0, L_0x2b4d1b0; 1 drivers +v0x244bb00_0 .net "in2", 0 0, L_0x2b4d250; 1 drivers +v0x244cf90_0 .net "in3", 0 0, L_0x2b4d340; 1 drivers +v0x24507a0_0 .net "nS0", 0 0, L_0x2b4bd60; 1 drivers +v0x2420b70_0 .net "nS1", 0 0, L_0x2b4be50; 1 drivers +v0x2451ce0_0 .net "out", 0 0, L_0x2b4c3b0; 1 drivers +v0x2455450_0 .net "out0", 0 0, L_0x2b4bef0; 1 drivers +v0x241bdf0_0 .net "out1", 0 0, L_0x2b4c030; 1 drivers +v0x2456990_0 .net "out2", 0 0, L_0x2b4c120; 1 drivers +v0x245a100_0 .net "out3", 0 0, L_0x2b4c240; 1 drivers +S_0x2219070 .scope module, "OneMux" "FourInMux" 3 67, 3 125, S_0x221eab0; + .timescale -9 -12; +L_0x2b4d430/d .functor NOT 1, L_0x2b4ed00, C4<0>, C4<0>, C4<0>; +L_0x2b4d430 .delay (10000,10000,10000) L_0x2b4d430/d; +L_0x2b4d520/d .functor NOT 1, L_0x2b4de50, C4<0>, C4<0>, C4<0>; +L_0x2b4d520 .delay (10000,10000,10000) L_0x2b4d520/d; +L_0x2b4d5c0/d .functor NAND 1, L_0x2b4d430, L_0x2b4d520, L_0x2b4df80, C4<1>; +L_0x2b4d5c0 .delay (10000,10000,10000) L_0x2b4d5c0/d; +L_0x2b4d700/d .functor NAND 1, L_0x2b4ed00, L_0x2b4d520, L_0x2b4e020, C4<1>; +L_0x2b4d700 .delay (10000,10000,10000) L_0x2b4d700/d; +L_0x2b4d7f0/d .functor NAND 1, L_0x2b4d430, L_0x2b4de50, L_0x2b4e0c0, C4<1>; +L_0x2b4d7f0 .delay (10000,10000,10000) L_0x2b4d7f0/d; +L_0x2b4d8e0/d .functor NAND 1, L_0x2b4ed00, L_0x2b4de50, L_0x2b4e160, C4<1>; +L_0x2b4d8e0 .delay (10000,10000,10000) L_0x2b4d8e0/d; +L_0x2b4da20/d .functor NAND 1, L_0x2b4d5c0, L_0x2b4d700, L_0x2b4d7f0, L_0x2b4d8e0; +L_0x2b4da20 .delay (10000,10000,10000) L_0x2b4da20/d; +v0x2456170_0 .net "S0", 0 0, L_0x2b4ed00; 1 drivers +v0x24514c0_0 .net "S1", 0 0, L_0x2b4de50; 1 drivers +v0x243de00_0 .net "in0", 0 0, L_0x2b4df80; 1 drivers +v0x243df80_0 .net "in1", 0 0, L_0x2b4e020; 1 drivers +v0x2439760_0 .net "in2", 0 0, L_0x2b4e0c0; 1 drivers +v0x2434ab0_0 .net "in3", 0 0, L_0x2b4e160; 1 drivers +v0x242fe00_0 .net "nS0", 0 0, L_0x2b4d430; 1 drivers +v0x241cbd0_0 .net "nS1", 0 0, L_0x2b4d520; 1 drivers +v0x241ba80_0 .net "out", 0 0, L_0x2b4da20; 1 drivers +v0x2439f80_0 .net "out0", 0 0, L_0x2b4d5c0; 1 drivers +v0x243d6f0_0 .net "out1", 0 0, L_0x2b4d700; 1 drivers +v0x241e250_0 .net "out2", 0 0, L_0x2b4d7f0; 1 drivers +v0x243ea60_0 .net "out3", 0 0, L_0x2b4d8e0; 1 drivers +S_0x221bd90 .scope module, "TwoMux" "TwoInMux" 3 68, 3 109, S_0x221eab0; + .timescale -9 -12; +L_0x2b4e250/d .functor NOT 1, L_0x2b4e700, C4<0>, C4<0>, C4<0>; +L_0x2b4e250 .delay (10000,10000,10000) L_0x2b4e250/d; +L_0x2b4e340/d .functor AND 1, L_0x2b4e7a0, L_0x2b4e250, C4<1>, C4<1>; +L_0x2b4e340 .delay (20000,20000,20000) L_0x2b4e340/d; +L_0x2b4e430/d .functor AND 1, L_0x2b4e890, L_0x2b4e700, C4<1>, C4<1>; +L_0x2b4e430 .delay (20000,20000,20000) L_0x2b4e430/d; +L_0x2b4e520/d .functor OR 1, L_0x2b4e340, L_0x2b4e430, C4<0>, C4<0>; +L_0x2b4e520 .delay (20000,20000,20000) L_0x2b4e520/d; +v0x247ef40_0 .net "S", 0 0, L_0x2b4e700; 1 drivers +v0x2480ad0_0 .net "in0", 0 0, L_0x2b4e7a0; 1 drivers +v0x247c530_0 .net "in1", 0 0, L_0x2b4e890; 1 drivers +v0x2477880_0 .net "nS", 0 0, L_0x2b4e250; 1 drivers +v0x2472bd0_0 .net "out0", 0 0, L_0x2b4e340; 1 drivers +v0x245f3c0_0 .net "out1", 0 0, L_0x2b4e430; 1 drivers +v0x245ae20_0 .net "outfinal", 0 0, L_0x2b4e520; 1 drivers +S_0x2619900 .scope generate, "muxbits[23]" "muxbits[23]" 3 64, 3 64, S_0x1f6b890; + .timescale -9 -12; +P_0x1cee118 .param/l "i" 3 64, +C4<010111>; +L_0x2b50a90/d .functor OR 1, L_0x2b52410, L_0x2b51500, C4<0>, C4<0>; +L_0x2b50a90 .delay (20000,20000,20000) L_0x2b50a90/d; +v0x24942c0_0 .net *"_s15", 0 0, L_0x2b52410; 1 drivers +v0x248f610_0 .net *"_s16", 0 0, L_0x2b51500; 1 drivers +S_0x263ce60 .scope module, "ZeroMux" "FourInMux" 3 66, 3 125, S_0x2619900; + .timescale -9 -12; +L_0x2b4ee30/d .functor NOT 1, L_0x2b4f730, C4<0>, C4<0>, C4<0>; +L_0x2b4ee30 .delay (10000,10000,10000) L_0x2b4ee30/d; +L_0x2b4ef20/d .functor NOT 1, L_0x2b4f860, C4<0>, C4<0>, C4<0>; +L_0x2b4ef20 .delay (10000,10000,10000) L_0x2b4ef20/d; +L_0x2b4efc0/d .functor NAND 1, L_0x2b4ee30, L_0x2b4ef20, L_0x2b4f990, C4<1>; +L_0x2b4efc0 .delay (10000,10000,10000) L_0x2b4efc0/d; +L_0x2b4f100/d .functor NAND 1, L_0x2b4f730, L_0x2b4ef20, L_0x2b4fa30, C4<1>; +L_0x2b4f100 .delay (10000,10000,10000) L_0x2b4f100/d; +L_0x2b4f1f0/d .functor NAND 1, L_0x2b4ee30, L_0x2b4f860, L_0x2b4fad0, C4<1>; +L_0x2b4f1f0 .delay (10000,10000,10000) L_0x2b4f1f0/d; +L_0x2b4f310/d .functor NAND 1, L_0x2b4f730, L_0x2b4f860, L_0x2b4fbc0, C4<1>; +L_0x2b4f310 .delay (10000,10000,10000) L_0x2b4f310/d; +L_0x2b4f480/d .functor NAND 1, L_0x2b4efc0, L_0x2b4f100, L_0x2b4f1f0, L_0x2b4f310; +L_0x2b4f480 .delay (10000,10000,10000) L_0x2b4f480/d; +v0x250d660_0 .net "S0", 0 0, L_0x2b4f730; 1 drivers +v0x2510450_0 .net "S1", 0 0, L_0x2b4f860; 1 drivers +v0x24bfed0_0 .net "in0", 0 0, L_0x2b4f990; 1 drivers +v0x24c0050_0 .net "in1", 0 0, L_0x2b4fa30; 1 drivers +v0x24c2b70_0 .net "in2", 0 0, L_0x2b4fad0; 1 drivers +v0x24c5970_0 .net "in3", 0 0, L_0x2b4fbc0; 1 drivers +v0x24c8770_0 .net "nS0", 0 0, L_0x2b4ee30; 1 drivers +v0x24cb570_0 .net "nS1", 0 0, L_0x2b4ef20; 1 drivers +v0x24ce370_0 .net "out", 0 0, L_0x2b4f480; 1 drivers +v0x24d1190_0 .net "out0", 0 0, L_0x2b4efc0; 1 drivers +v0x24d3fd0_0 .net "out1", 0 0, L_0x2b4f100; 1 drivers +v0x249dc20_0 .net "out2", 0 0, L_0x2b4f1f0; 1 drivers +v0x2498f70_0 .net "out3", 0 0, L_0x2b4f310; 1 drivers +S_0x2637040 .scope module, "OneMux" "FourInMux" 3 67, 3 125, S_0x2619900; + .timescale -9 -12; +L_0x2b50c40/d .functor NOT 1, L_0x2b4fd40, C4<0>, C4<0>, C4<0>; +L_0x2b50c40 .delay (10000,10000,10000) L_0x2b50c40/d; +L_0x2b50cf0/d .functor NOT 1, L_0x2b4fe70, C4<0>, C4<0>, C4<0>; +L_0x2b50cf0 .delay (10000,10000,10000) L_0x2b50cf0/d; +L_0x2b50d90/d .functor NAND 1, L_0x2b50c40, L_0x2b50cf0, L_0x2b4ffa0, C4<1>; +L_0x2b50d90 .delay (10000,10000,10000) L_0x2b50d90/d; +L_0x2b50ed0/d .functor NAND 1, L_0x2b4fd40, L_0x2b50cf0, L_0x2b50040, C4<1>; +L_0x2b50ed0 .delay (10000,10000,10000) L_0x2b50ed0/d; +L_0x2b50fc0/d .functor NAND 1, L_0x2b50c40, L_0x2b4fe70, L_0x2b500e0, C4<1>; +L_0x2b50fc0 .delay (10000,10000,10000) L_0x2b50fc0/d; +L_0x2b510e0/d .functor NAND 1, L_0x2b4fd40, L_0x2b4fe70, L_0x2b501d0, C4<1>; +L_0x2b510e0 .delay (10000,10000,10000) L_0x2b510e0/d; +L_0x2b51250/d .functor NAND 1, L_0x2b50d90, L_0x2b50ed0, L_0x2b50fc0, L_0x2b510e0; +L_0x2b51250 .delay (10000,10000,10000) L_0x2b51250/d; +v0x24edce0_0 .net "S0", 0 0, L_0x2b4fd40; 1 drivers +v0x24f0ab0_0 .net "S1", 0 0, L_0x2b4fe70; 1 drivers +v0x24f38f0_0 .net "in0", 0 0, L_0x2b4ffa0; 1 drivers +v0x24b7390_0 .net "in1", 0 0, L_0x2b50040; 1 drivers +v0x24bd0d0_0 .net "in2", 0 0, L_0x2b500e0; 1 drivers +v0x24f6730_0 .net "in3", 0 0, L_0x2b501d0; 1 drivers +v0x24f9570_0 .net "nS0", 0 0, L_0x2b50c40; 1 drivers +v0x24fc3b0_0 .net "nS1", 0 0, L_0x2b50cf0; 1 drivers +v0x24ff1f0_0 .net "out", 0 0, L_0x2b51250; 1 drivers +v0x2501e60_0 .net "out0", 0 0, L_0x2b50d90; 1 drivers +v0x2504c60_0 .net "out1", 0 0, L_0x2b50ed0; 1 drivers +v0x2507a60_0 .net "out2", 0 0, L_0x2b50fc0; 1 drivers +v0x250a860_0 .net "out3", 0 0, L_0x2b510e0; 1 drivers +S_0x261f720 .scope module, "TwoMux" "TwoInMux" 3 68, 3 109, S_0x2619900; + .timescale -9 -12; +L_0x2b502c0/d .functor NOT 1, L_0x2b50770, C4<0>, C4<0>, C4<0>; +L_0x2b502c0 .delay (10000,10000,10000) L_0x2b502c0/d; +L_0x2b503b0/d .functor AND 1, L_0x2b50810, L_0x2b502c0, C4<1>, C4<1>; +L_0x2b503b0 .delay (20000,20000,20000) L_0x2b503b0/d; +L_0x2b504a0/d .functor AND 1, L_0x2b50900, L_0x2b50770, C4<1>, C4<1>; +L_0x2b504a0 .delay (20000,20000,20000) L_0x2b504a0/d; +L_0x2b50590/d .functor OR 1, L_0x2b503b0, L_0x2b504a0, C4<0>, C4<0>; +L_0x2b50590 .delay (20000,20000,20000) L_0x2b50590/d; +v0x24d9c50_0 .net "S", 0 0, L_0x2b50770; 1 drivers +v0x24dca90_0 .net "in0", 0 0, L_0x2b50810; 1 drivers +v0x24df8d0_0 .net "in1", 0 0, L_0x2b50900; 1 drivers +v0x24e24e0_0 .net "nS", 0 0, L_0x2b502c0; 1 drivers +v0x24e52e0_0 .net "out0", 0 0, L_0x2b503b0; 1 drivers +v0x24e80e0_0 .net "out1", 0 0, L_0x2b504a0; 1 drivers +v0x24eaee0_0 .net "outfinal", 0 0, L_0x2b50590; 1 drivers +S_0x25dea60 .scope generate, "muxbits[24]" "muxbits[24]" 3 64, 3 64, S_0x1f6b890; + .timescale -9 -12; +P_0x1d23f68 .param/l "i" 3 64, +C4<011000>; +L_0x2b537c0/d .functor OR 1, L_0x2b53900, L_0x2b539a0, C4<0>, C4<0>; +L_0x2b537c0 .delay (20000,20000,20000) L_0x2b537c0/d; +v0x24d6e10_0 .net *"_s15", 0 0, L_0x2b53900; 1 drivers +v0x24ba290_0 .net *"_s16", 0 0, L_0x2b539a0; 1 drivers +S_0x2613ae0 .scope module, "ZeroMux" "FourInMux" 3 66, 3 125, S_0x25dea60; + .timescale -9 -12; +L_0x2b515f0/d .functor NOT 1, L_0x2b51ef0, C4<0>, C4<0>, C4<0>; +L_0x2b515f0 .delay (10000,10000,10000) L_0x2b515f0/d; +L_0x2b516e0/d .functor NOT 1, L_0x2b52020, C4<0>, C4<0>, C4<0>; +L_0x2b516e0 .delay (10000,10000,10000) L_0x2b516e0/d; +L_0x2b51780/d .functor NAND 1, L_0x2b515f0, L_0x2b516e0, L_0x2b52150, C4<1>; +L_0x2b51780 .delay (10000,10000,10000) L_0x2b51780/d; +L_0x2b518c0/d .functor NAND 1, L_0x2b51ef0, L_0x2b516e0, L_0x2b521f0, C4<1>; +L_0x2b518c0 .delay (10000,10000,10000) L_0x2b518c0/d; +L_0x2b519b0/d .functor NAND 1, L_0x2b515f0, L_0x2b52020, L_0x2b52290, C4<1>; +L_0x2b519b0 .delay (10000,10000,10000) L_0x2b519b0/d; +L_0x2b51ad0/d .functor NAND 1, L_0x2b51ef0, L_0x2b52020, L_0x2b53400, C4<1>; +L_0x2b51ad0 .delay (10000,10000,10000) L_0x2b51ad0/d; +L_0x2b51c40/d .functor NAND 1, L_0x2b51780, L_0x2b518c0, L_0x2b519b0, L_0x2b51ad0; +L_0x2b51c40 .delay (10000,10000,10000) L_0x2b51c40/d; +v0x24f4610_0 .net "S0", 0 0, L_0x2b51ef0; 1 drivers +v0x24f17d0_0 .net "S1", 0 0, L_0x2b52020; 1 drivers +v0x24dffe0_0 .net "in0", 0 0, L_0x2b52150; 1 drivers +v0x24e0160_0 .net "in1", 0 0, L_0x2b521f0; 1 drivers +v0x24dd7b0_0 .net "in2", 0 0, L_0x2b52290; 1 drivers +v0x24da970_0 .net "in3", 0 0, L_0x2b53400; 1 drivers +v0x24d7b30_0 .net "nS0", 0 0, L_0x2b515f0; 1 drivers +v0x24d4cf0_0 .net "nS1", 0 0, L_0x2b516e0; 1 drivers +v0x24d1eb0_0 .net "out", 0 0, L_0x2b51c40; 1 drivers +v0x24bddf0_0 .net "out0", 0 0, L_0x2b51780; 1 drivers +v0x24bafb0_0 .net "out1", 0 0, L_0x2b518c0; 1 drivers +v0x24b8170_0 .net "out2", 0 0, L_0x2b519b0; 1 drivers +v0x24b7020_0 .net "out3", 0 0, L_0x2b51ad0; 1 drivers +S_0x25fc1c0 .scope module, "OneMux" "FourInMux" 3 67, 3 125, S_0x25dea60; + .timescale -9 -12; +L_0x2b51b60/d .functor NOT 1, L_0x2b52d70, C4<0>, C4<0>, C4<0>; +L_0x2b51b60 .delay (10000,10000,10000) L_0x2b51b60/d; +L_0x2b52500/d .functor NOT 1, L_0x2b52ea0, C4<0>, C4<0>, C4<0>; +L_0x2b52500 .delay (10000,10000,10000) L_0x2b52500/d; +L_0x2b525a0/d .functor NAND 1, L_0x2b51b60, L_0x2b52500, L_0x2b52fd0, C4<1>; +L_0x2b525a0 .delay (10000,10000,10000) L_0x2b525a0/d; +L_0x2b526e0/d .functor NAND 1, L_0x2b52d70, L_0x2b52500, L_0x2b53070, C4<1>; +L_0x2b526e0 .delay (10000,10000,10000) L_0x2b526e0/d; +L_0x2b52800/d .functor NAND 1, L_0x2b51b60, L_0x2b52ea0, L_0x2b53110, C4<1>; +L_0x2b52800 .delay (10000,10000,10000) L_0x2b52800/d; +L_0x2b52950/d .functor NAND 1, L_0x2b52d70, L_0x2b52ea0, L_0x2b53200, C4<1>; +L_0x2b52950 .delay (10000,10000,10000) L_0x2b52950/d; +L_0x2b52ac0/d .functor NAND 1, L_0x2b525a0, L_0x2b526e0, L_0x2b52800, L_0x2b52950; +L_0x2b52ac0 .delay (10000,10000,10000) L_0x2b52ac0/d; +v0x25181e0_0 .net "S0", 0 0, L_0x2b52d70; 1 drivers +v0x25197a0_0 .net "S1", 0 0, L_0x2b52ea0; 1 drivers +v0x251ad60_0 .net "in0", 0 0, L_0x2b52fd0; 1 drivers +v0x251c320_0 .net "in1", 0 0, L_0x2b53070; 1 drivers +v0x251d8e0_0 .net "in2", 0 0, L_0x2b53110; 1 drivers +v0x251eea0_0 .net "in3", 0 0, L_0x2b53200; 1 drivers +v0x2515660_0 .net "nS0", 0 0, L_0x2b51b60; 1 drivers +v0x2531f40_0 .net "nS1", 0 0, L_0x2b52500; 1 drivers +v0x2533500_0 .net "out", 0 0, L_0x2b52ac0; 1 drivers +v0x24fff10_0 .net "out0", 0 0, L_0x2b525a0; 1 drivers +v0x24fd0d0_0 .net "out1", 0 0, L_0x2b526e0; 1 drivers +v0x24fa290_0 .net "out2", 0 0, L_0x2b52800; 1 drivers +v0x24f7450_0 .net "out3", 0 0, L_0x2b52950; 1 drivers +S_0x25f63a0 .scope module, "TwoMux" "TwoInMux" 3 68, 3 109, S_0x25dea60; + .timescale -9 -12; +L_0x2b532f0/d .functor NOT 1, L_0x2b534a0, C4<0>, C4<0>, C4<0>; +L_0x2b532f0 .delay (10000,10000,10000) L_0x2b532f0/d; +L_0x2b54430/d .functor AND 1, L_0x2b53540, L_0x2b532f0, C4<1>, C4<1>; +L_0x2b54430 .delay (20000,20000,20000) L_0x2b54430/d; +L_0x2b54520/d .functor AND 1, L_0x2b53630, L_0x2b534a0, C4<1>, C4<1>; +L_0x2b54520 .delay (20000,20000,20000) L_0x2b54520/d; +L_0x2b54610/d .functor OR 1, L_0x2b54430, L_0x2b54520, C4<0>, C4<0>; +L_0x2b54610 .delay (20000,20000,20000) L_0x2b54610/d; +v0x2536080_0 .net "S", 0 0, L_0x2b534a0; 1 drivers +v0x2537640_0 .net "in0", 0 0, L_0x2b53540; 1 drivers +v0x2538c00_0 .net "in1", 0 0, L_0x2b53630; 1 drivers +v0x253a1c0_0 .net "nS", 0 0, L_0x2b532f0; 1 drivers +v0x2516c20_0 .net "out0", 0 0, L_0x2b54430; 1 drivers +v0x253b780_0 .net "out1", 0 0, L_0x2b54520; 1 drivers +v0x253cd40_0 .net "outfinal", 0 0, L_0x2b54610; 1 drivers +S_0x25bb500 .scope generate, "muxbits[25]" "muxbits[25]" 3 64, 3 64, S_0x1f6b890; + .timescale -9 -12; +P_0x1d23478 .param/l "i" 3 64, +C4<011001>; +L_0x2b56200/d .functor OR 1, L_0x2b56340, L_0x2b563e0, C4<0>, C4<0>; +L_0x2b56200 .delay (20000,20000,20000) L_0x2b56200/d; +v0x2369b00_0 .net *"_s15", 0 0, L_0x2b56340; 1 drivers +v0x2534ac0_0 .net *"_s16", 0 0, L_0x2b563e0; 1 drivers +S_0x25d8c40 .scope module, "ZeroMux" "FourInMux" 3 66, 3 125, S_0x25bb500; + .timescale -9 -12; +L_0x2b53a90/d .functor NOT 1, L_0x2b54390, C4<0>, C4<0>, C4<0>; +L_0x2b53a90 .delay (10000,10000,10000) L_0x2b53a90/d; +L_0x2b53b80/d .functor NOT 1, L_0x2b547f0, C4<0>, C4<0>, C4<0>; +L_0x2b53b80 .delay (10000,10000,10000) L_0x2b53b80/d; +L_0x2b53c20/d .functor NAND 1, L_0x2b53a90, L_0x2b53b80, L_0x2b54920, C4<1>; +L_0x2b53c20 .delay (10000,10000,10000) L_0x2b53c20/d; +L_0x2b53d60/d .functor NAND 1, L_0x2b54390, L_0x2b53b80, L_0x2b549c0, C4<1>; +L_0x2b53d60 .delay (10000,10000,10000) L_0x2b53d60/d; +L_0x2b53e50/d .functor NAND 1, L_0x2b53a90, L_0x2b547f0, L_0x2b54a60, C4<1>; +L_0x2b53e50 .delay (10000,10000,10000) L_0x2b53e50/d; +L_0x2b53f70/d .functor NAND 1, L_0x2b54390, L_0x2b547f0, L_0x2b54b50, C4<1>; +L_0x2b53f70 .delay (10000,10000,10000) L_0x2b53f70/d; +L_0x2b540e0/d .functor NAND 1, L_0x2b53c20, L_0x2b53d60, L_0x2b53e50, L_0x2b53f70; +L_0x2b540e0 .delay (10000,10000,10000) L_0x2b540e0/d; +v0x23aca30_0 .net "S0", 0 0, L_0x2b54390; 1 drivers +v0x23a6de0_0 .net "S1", 0 0, L_0x2b547f0; 1 drivers +v0x23a8e20_0 .net "in0", 0 0, L_0x2b54920; 1 drivers +v0x23a1190_0 .net "in1", 0 0, L_0x2b549c0; 1 drivers +v0x23a31d0_0 .net "in2", 0 0, L_0x2b54a60; 1 drivers +v0x238a2d0_0 .net "in3", 0 0, L_0x2b54b50; 1 drivers +v0x238c310_0 .net "nS0", 0 0, L_0x2b53a90; 1 drivers +v0x2384680_0 .net "nS1", 0 0, L_0x2b53b80; 1 drivers +v0x23866c0_0 .net "out", 0 0, L_0x2b540e0; 1 drivers +v0x237ea30_0 .net "out0", 0 0, L_0x2b53c20; 1 drivers +v0x2380a70_0 .net "out1", 0 0, L_0x2b53d60; 1 drivers +v0x23679f0_0 .net "out2", 0 0, L_0x2b53e50; 1 drivers +v0x236b280_0 .net "out3", 0 0, L_0x2b53f70; 1 drivers +S_0x25d2e20 .scope module, "OneMux" "FourInMux" 3 67, 3 125, S_0x25bb500; + .timescale -9 -12; +L_0x2b54c40/d .functor NOT 1, L_0x2b55540, C4<0>, C4<0>, C4<0>; +L_0x2b54c40 .delay (10000,10000,10000) L_0x2b54c40/d; +L_0x2b54d30/d .functor NOT 1, L_0x2b55670, C4<0>, C4<0>, C4<0>; +L_0x2b54d30 .delay (10000,10000,10000) L_0x2b54d30/d; +L_0x2b54dd0/d .functor NAND 1, L_0x2b54c40, L_0x2b54d30, L_0x2b56870, C4<1>; +L_0x2b54dd0 .delay (10000,10000,10000) L_0x2b54dd0/d; +L_0x2b54f10/d .functor NAND 1, L_0x2b55540, L_0x2b54d30, L_0x2b56910, C4<1>; +L_0x2b54f10 .delay (10000,10000,10000) L_0x2b54f10/d; +L_0x2b55000/d .functor NAND 1, L_0x2b54c40, L_0x2b55670, L_0x2b55850, C4<1>; +L_0x2b55000 .delay (10000,10000,10000) L_0x2b55000/d; +L_0x2b55120/d .functor NAND 1, L_0x2b55540, L_0x2b55670, L_0x2b55940, C4<1>; +L_0x2b55120 .delay (10000,10000,10000) L_0x2b55120/d; +L_0x2b55290/d .functor NAND 1, L_0x2b54dd0, L_0x2b54f10, L_0x2b55000, L_0x2b55120; +L_0x2b55290 .delay (10000,10000,10000) L_0x2b55290/d; +v0x2642c70_0 .net "S0", 0 0, L_0x2b55540; 1 drivers +v0x25a3bb0_0 .net "S1", 0 0, L_0x2b55670; 1 drivers +v0x240cfa0_0 .net "in0", 0 0, L_0x2b56870; 1 drivers +v0x2407140_0 .net "in1", 0 0, L_0x2b56910; 1 drivers +v0x24012e0_0 .net "in2", 0 0, L_0x2b55850; 1 drivers +v0x23e9a20_0 .net "in3", 0 0, L_0x2b55940; 1 drivers +v0x23e0380_0 .net "nS0", 0 0, L_0x2b54c40; 1 drivers +v0x23e3bc0_0 .net "nS1", 0 0, L_0x2b54d30; 1 drivers +v0x23c9510_0 .net "out", 0 0, L_0x2b55290; 1 drivers +v0x23cb550_0 .net "out0", 0 0, L_0x2b54dd0; 1 drivers +v0x23c38c0_0 .net "out1", 0 0, L_0x2b54f10; 1 drivers +v0x23c5900_0 .net "out2", 0 0, L_0x2b55000; 1 drivers +v0x23bfcb0_0 .net "out3", 0 0, L_0x2b55120; 1 drivers +S_0x25c1320 .scope module, "TwoMux" "TwoInMux" 3 68, 3 109, S_0x25bb500; + .timescale -9 -12; +L_0x2b55a30/d .functor NOT 1, L_0x2b55ee0, C4<0>, C4<0>, C4<0>; +L_0x2b55a30 .delay (10000,10000,10000) L_0x2b55a30/d; +L_0x2b55b20/d .functor AND 1, L_0x2b55f80, L_0x2b55a30, C4<1>, C4<1>; +L_0x2b55b20 .delay (20000,20000,20000) L_0x2b55b20/d; +L_0x2b55c10/d .functor AND 1, L_0x2b56070, L_0x2b55ee0, C4<1>, C4<1>; +L_0x2b55c10 .delay (20000,20000,20000) L_0x2b55c10/d; +L_0x2b55d00/d .functor OR 1, L_0x2b55b20, L_0x2b55c10, C4<0>, C4<0>; +L_0x2b55d00 .delay (20000,20000,20000) L_0x2b55d00/d; +v0x25f0530_0 .net "S", 0 0, L_0x2b55ee0; 1 drivers +v0x2601fe0_0 .net "in0", 0 0, L_0x2b55f80; 1 drivers +v0x2607e10_0 .net "in1", 0 0, L_0x2b56070; 1 drivers +v0x260dc70_0 .net "nS", 0 0, L_0x2b55a30; 1 drivers +v0x2625530_0 .net "out0", 0 0, L_0x2b55b20; 1 drivers +v0x262b390_0 .net "out1", 0 0, L_0x2b55c10; 1 drivers +v0x26311f0_0 .net "outfinal", 0 0, L_0x2b55d00; 1 drivers +S_0x2646500 .scope generate, "muxbits[26]" "muxbits[26]" 3 64, 3 64, S_0x1f6b890; + .timescale -9 -12; +P_0x1d3b9c8 .param/l "i" 3 64, +C4<011010>; +L_0x2b58a00/d .functor OR 1, L_0x2b58b40, L_0x2b58be0, C4<0>, C4<0>; +L_0x2b58a00 .delay (20000,20000,20000) L_0x2b58a00/d; +v0x25e4870_0 .net *"_s15", 0 0, L_0x2b58b40; 1 drivers +v0x25ea6d0_0 .net *"_s16", 0 0, L_0x2b58be0; 1 drivers +S_0x25b56e0 .scope module, "ZeroMux" "FourInMux" 3 66, 3 125, S_0x2646500; + .timescale -9 -12; +L_0x2b564d0/d .functor NOT 1, L_0x2b569b0, C4<0>, C4<0>, C4<0>; +L_0x2b564d0 .delay (10000,10000,10000) L_0x2b564d0/d; +L_0x2b565c0/d .functor NOT 1, L_0x2b56ae0, C4<0>, C4<0>, C4<0>; +L_0x2b565c0 .delay (10000,10000,10000) L_0x2b565c0/d; +L_0x2b56660/d .functor NAND 1, L_0x2b564d0, L_0x2b565c0, L_0x2b56c10, C4<1>; +L_0x2b56660 .delay (10000,10000,10000) L_0x2b56660/d; +L_0x2b567a0/d .functor NAND 1, L_0x2b569b0, L_0x2b565c0, L_0x2b56cb0, C4<1>; +L_0x2b567a0 .delay (10000,10000,10000) L_0x2b567a0/d; +L_0x2b57a70/d .functor NAND 1, L_0x2b564d0, L_0x2b56ae0, L_0x2b56d50, C4<1>; +L_0x2b57a70 .delay (10000,10000,10000) L_0x2b57a70/d; +L_0x2b57b90/d .functor NAND 1, L_0x2b569b0, L_0x2b56ae0, L_0x2b56e40, C4<1>; +L_0x2b57b90 .delay (10000,10000,10000) L_0x2b57b90/d; +L_0x2b57d00/d .functor NAND 1, L_0x2b56660, L_0x2b567a0, L_0x2b57a70, L_0x2b57b90; +L_0x2b57d00 .delay (10000,10000,10000) L_0x2b57d00/d; +v0x2659670_0 .net "S0", 0 0, L_0x2b569b0; 1 drivers +v0x265abb0_0 .net "S1", 0 0, L_0x2b56ae0; 1 drivers +v0x265e320_0 .net "in0", 0 0, L_0x2b56c10; 1 drivers +v0x265f860_0 .net "in1", 0 0, L_0x2b56cb0; 1 drivers +v0x2647850_0 .net "in2", 0 0, L_0x2b56d50; 1 drivers +v0x2662ed0_0 .net "in3", 0 0, L_0x2b56e40; 1 drivers +v0x20b5e10_0 .net "nS0", 0 0, L_0x2b564d0; 1 drivers +v0x20b6230_0 .net "nS1", 0 0, L_0x2b565c0; 1 drivers +v0x25a9a10_0 .net "out", 0 0, L_0x2b57d00; 1 drivers +v0x25af870_0 .net "out0", 0 0, L_0x2b56660; 1 drivers +v0x2592150_0 .net "out1", 0 0, L_0x2b567a0; 1 drivers +v0x25c7150_0 .net "out2", 0 0, L_0x2b57a70; 1 drivers +v0x25ccfb0_0 .net "out3", 0 0, L_0x2b57b90; 1 drivers +S_0x259dda0 .scope module, "OneMux" "FourInMux" 3 67, 3 125, S_0x2646500; + .timescale -9 -12; +L_0x2b56f30/d .functor NOT 1, L_0x2b57830, C4<0>, C4<0>, C4<0>; +L_0x2b56f30 .delay (10000,10000,10000) L_0x2b56f30/d; +L_0x2b57020/d .functor NOT 1, L_0x2b57960, C4<0>, C4<0>, C4<0>; +L_0x2b57020 .delay (10000,10000,10000) L_0x2b57020/d; +L_0x2b570c0/d .functor NAND 1, L_0x2b56f30, L_0x2b57020, L_0x2b59100, C4<1>; +L_0x2b570c0 .delay (10000,10000,10000) L_0x2b570c0/d; +L_0x2b57200/d .functor NAND 1, L_0x2b57830, L_0x2b57020, L_0x2b57fb0, C4<1>; +L_0x2b57200 .delay (10000,10000,10000) L_0x2b57200/d; +L_0x2b572f0/d .functor NAND 1, L_0x2b56f30, L_0x2b57960, L_0x2b58050, C4<1>; +L_0x2b572f0 .delay (10000,10000,10000) L_0x2b572f0/d; +L_0x2b57410/d .functor NAND 1, L_0x2b57830, L_0x2b57960, L_0x2b58140, C4<1>; +L_0x2b57410 .delay (10000,10000,10000) L_0x2b57410/d; +L_0x2b57580/d .functor NAND 1, L_0x2b570c0, L_0x2b57200, L_0x2b572f0, L_0x2b57410; +L_0x2b57580 .delay (10000,10000,10000) L_0x2b57580/d; +v0x26c3b30_0 .net "S0", 0 0, L_0x2b57830; 1 drivers +v0x26c7320_0 .net "S1", 0 0, L_0x2b57960; 1 drivers +v0x26c87b0_0 .net "in0", 0 0, L_0x2b59100; 1 drivers +v0x26cbf90_0 .net "in1", 0 0, L_0x2b57fb0; 1 drivers +v0x26cd420_0 .net "in2", 0 0, L_0x2b58050; 1 drivers +v0x26d0c00_0 .net "in3", 0 0, L_0x2b58140; 1 drivers +v0x26d2090_0 .net "nS0", 0 0, L_0x2b56f30; 1 drivers +v0x26d58a0_0 .net "nS1", 0 0, L_0x2b57020; 1 drivers +v0x26d6de0_0 .net "out", 0 0, L_0x2b57580; 1 drivers +v0x26549c0_0 .net "out0", 0 0, L_0x2b570c0; 1 drivers +v0x26db140_0 .net "out1", 0 0, L_0x2b57200; 1 drivers +v0x26df250_0 .net "out2", 0 0, L_0x2b572f0; 1 drivers +v0x2655f00_0 .net "out3", 0 0, L_0x2b57410; 1 drivers +S_0x2597f80 .scope module, "TwoMux" "TwoInMux" 3 68, 3 109, S_0x2646500; + .timescale -9 -12; +L_0x2b58230/d .functor NOT 1, L_0x2b586e0, C4<0>, C4<0>, C4<0>; +L_0x2b58230 .delay (10000,10000,10000) L_0x2b58230/d; +L_0x2b58320/d .functor AND 1, L_0x2b58780, L_0x2b58230, C4<1>, C4<1>; +L_0x2b58320 .delay (20000,20000,20000) L_0x2b58320/d; +L_0x2b58410/d .functor AND 1, L_0x2b58870, L_0x2b586e0, C4<1>, C4<1>; +L_0x2b58410 .delay (20000,20000,20000) L_0x2b58410/d; +L_0x2b58500/d .functor OR 1, L_0x2b58320, L_0x2b58410, C4<0>, C4<0>; +L_0x2b58500 .delay (20000,20000,20000) L_0x2b58500/d; +v0x26b8e60_0 .net "S", 0 0, L_0x2b586e0; 1 drivers +v0x26ba3a0_0 .net "in0", 0 0, L_0x2b58780; 1 drivers +v0x26bdb10_0 .net "in1", 0 0, L_0x2b58870; 1 drivers +v0x26bf050_0 .net "nS", 0 0, L_0x2b58230; 1 drivers +v0x26511b0_0 .net "out0", 0 0, L_0x2b58320; 1 drivers +v0x26c2490_0 .net "out1", 0 0, L_0x2b58410; 1 drivers +v0x26c2690_0 .net "outfinal", 0 0, L_0x2b58500; 1 drivers +S_0x2412990 .scope generate, "muxbits[27]" "muxbits[27]" 3 64, 3 64, S_0x1f6b890; + .timescale -9 -12; +P_0x1d3aa88 .param/l "i" 3 64, +C4<011011>; +L_0x2b5b0f0/d .functor OR 1, L_0x2b5b230, L_0x2b5b2d0, C4<0>, C4<0>; +L_0x2b5b0f0 .delay (20000,20000,20000) L_0x2b5b0f0/d; +v0x26b41b0_0 .net *"_s15", 0 0, L_0x2b5b230; 1 drivers +v0x26b56f0_0 .net *"_s16", 0 0, L_0x2b5b2d0; 1 drivers +S_0x26dc600 .scope module, "ZeroMux" "FourInMux" 3 66, 3 125, S_0x2412990; + .timescale -9 -12; +L_0x2b58cd0/d .functor NOT 1, L_0x2b5a850, C4<0>, C4<0>, C4<0>; +L_0x2b58cd0 .delay (10000,10000,10000) L_0x2b58cd0/d; +L_0x2b58dc0/d .functor NOT 1, L_0x2b591a0, C4<0>, C4<0>, C4<0>; +L_0x2b58dc0 .delay (10000,10000,10000) L_0x2b58dc0/d; +L_0x2b58e60/d .functor NAND 1, L_0x2b58cd0, L_0x2b58dc0, L_0x2b592d0, C4<1>; +L_0x2b58e60 .delay (10000,10000,10000) L_0x2b58e60/d; +L_0x2b58fa0/d .functor NAND 1, L_0x2b5a850, L_0x2b58dc0, L_0x2b59370, C4<1>; +L_0x2b58fa0 .delay (10000,10000,10000) L_0x2b58fa0/d; +L_0x2b5a310/d .functor NAND 1, L_0x2b58cd0, L_0x2b591a0, L_0x2b59410, C4<1>; +L_0x2b5a310 .delay (10000,10000,10000) L_0x2b5a310/d; +L_0x2b5a430/d .functor NAND 1, L_0x2b5a850, L_0x2b591a0, L_0x2b59500, C4<1>; +L_0x2b5a430 .delay (10000,10000,10000) L_0x2b5a430/d; +L_0x2b5a5a0/d .functor NAND 1, L_0x2b58e60, L_0x2b58fa0, L_0x2b5a310, L_0x2b5a430; +L_0x2b5a5a0 .delay (10000,10000,10000) L_0x2b5a5a0/d; +v0x2697760_0 .net "S0", 0 0, L_0x2b5a850; 1 drivers +v0x2698ca0_0 .net "S1", 0 0, L_0x2b591a0; 1 drivers +v0x269c410_0 .net "in0", 0 0, L_0x2b592d0; 1 drivers +v0x269d950_0 .net "in1", 0 0, L_0x2b59370; 1 drivers +v0x26a10c0_0 .net "in2", 0 0, L_0x2b59410; 1 drivers +v0x26a2460_0 .net "in3", 0 0, L_0x2b59500; 1 drivers +v0x26a5c40_0 .net "nS0", 0 0, L_0x2b58cd0; 1 drivers +v0x26a70d0_0 .net "nS1", 0 0, L_0x2b58dc0; 1 drivers +v0x26aa8b0_0 .net "out", 0 0, L_0x2b5a5a0; 1 drivers +v0x264fd20_0 .net "out0", 0 0, L_0x2b58e60; 1 drivers +v0x26abd40_0 .net "out1", 0 0, L_0x2b58fa0; 1 drivers +v0x26af520_0 .net "out2", 0 0, L_0x2b5a310; 1 drivers +v0x26b09b0_0 .net "out3", 0 0, L_0x2b5a430; 1 drivers +S_0x27b6250 .scope module, "OneMux" "FourInMux" 3 67, 3 125, S_0x2412990; + .timescale -9 -12; +L_0x2b595f0/d .functor NOT 1, L_0x2b59ef0, C4<0>, C4<0>, C4<0>; +L_0x2b595f0 .delay (10000,10000,10000) L_0x2b595f0/d; +L_0x2b596e0/d .functor NOT 1, L_0x2b5a020, C4<0>, C4<0>, C4<0>; +L_0x2b596e0 .delay (10000,10000,10000) L_0x2b596e0/d; +L_0x2b59780/d .functor NAND 1, L_0x2b595f0, L_0x2b596e0, L_0x2b5a150, C4<1>; +L_0x2b59780 .delay (10000,10000,10000) L_0x2b59780/d; +L_0x2b598c0/d .functor NAND 1, L_0x2b59ef0, L_0x2b596e0, L_0x2b5a1f0, C4<1>; +L_0x2b598c0 .delay (10000,10000,10000) L_0x2b598c0/d; +L_0x2b599b0/d .functor NAND 1, L_0x2b595f0, L_0x2b5a020, L_0x2b5bb00, C4<1>; +L_0x2b599b0 .delay (10000,10000,10000) L_0x2b599b0/d; +L_0x2b59ad0/d .functor NAND 1, L_0x2b59ef0, L_0x2b5a020, L_0x2b5bbf0, C4<1>; +L_0x2b59ad0 .delay (10000,10000,10000) L_0x2b59ad0/d; +L_0x2b59c40/d .functor NAND 1, L_0x2b59780, L_0x2b598c0, L_0x2b599b0, L_0x2b59ad0; +L_0x2b59c40 .delay (10000,10000,10000) L_0x2b59c40/d; +v0x267c2b0_0 .net "S0", 0 0, L_0x2b59ef0; 1 drivers +v0x267fa20_0 .net "S1", 0 0, L_0x2b5a020; 1 drivers +v0x2646290_0 .net "in0", 0 0, L_0x2b5a150; 1 drivers +v0x2680f60_0 .net "in1", 0 0, L_0x2b5a1f0; 1 drivers +v0x2684590_0 .net "in2", 0 0, L_0x2b5bb00; 1 drivers +v0x2685a20_0 .net "in3", 0 0, L_0x2b5bbf0; 1 drivers +v0x2689200_0 .net "nS0", 0 0, L_0x2b595f0; 1 drivers +v0x268a690_0 .net "nS1", 0 0, L_0x2b596e0; 1 drivers +v0x268de70_0 .net "out", 0 0, L_0x2b59c40; 1 drivers +v0x268f300_0 .net "out0", 0 0, L_0x2b59780; 1 drivers +v0x264c540_0 .net "out1", 0 0, L_0x2b598c0; 1 drivers +v0x2692ab0_0 .net "out2", 0 0, L_0x2b599b0; 1 drivers +v0x2693ff0_0 .net "out3", 0 0, L_0x2b59ad0; 1 drivers +S_0x24187b0 .scope module, "TwoMux" "TwoInMux" 3 68, 3 109, S_0x2412990; + .timescale -9 -12; +L_0x2b59b60/d .functor NOT 1, L_0x2b5add0, C4<0>, C4<0>, C4<0>; +L_0x2b59b60 .delay (10000,10000,10000) L_0x2b59b60/d; +L_0x2b5aa10/d .functor AND 1, L_0x2b5ae70, L_0x2b59b60, C4<1>, C4<1>; +L_0x2b5aa10 .delay (20000,20000,20000) L_0x2b5aa10/d; +L_0x2b5ab00/d .functor AND 1, L_0x2b5af60, L_0x2b5add0, C4<1>, C4<1>; +L_0x2b5ab00 .delay (20000,20000,20000) L_0x2b5ab00/d; +L_0x2b5abf0/d .functor OR 1, L_0x2b5aa10, L_0x2b5ab00, C4<0>, C4<0>; +L_0x2b5abf0 .delay (20000,20000,20000) L_0x2b5abf0/d; +v0x266dc60_0 .net "S", 0 0, L_0x2b5add0; 1 drivers +v0x2671440_0 .net "in0", 0 0, L_0x2b5ae70; 1 drivers +v0x2672950_0 .net "in1", 0 0, L_0x2b5af60; 1 drivers +v0x26760c0_0 .net "nS", 0 0, L_0x2b59b60; 1 drivers +v0x2677600_0 .net "out0", 0 0, L_0x2b5aa10; 1 drivers +v0x267ad70_0 .net "out1", 0 0, L_0x2b5ab00; 1 drivers +v0x264b0b0_0 .net "outfinal", 0 0, L_0x2b5abf0; 1 drivers +S_0x23ddaa0 .scope generate, "muxbits[28]" "muxbits[28]" 3 64, 3 64, S_0x1f6b890; + .timescale -9 -12; +P_0x1d2f118 .param/l "i" 3 64, +C4<011100>; +L_0x2b5d940/d .functor OR 1, L_0x2b5da80, L_0x2b5db20, C4<0>, C4<0>; +L_0x2b5d940 .delay (20000,20000,20000) L_0x2b5d940/d; +v0x2668ff0_0 .net *"_s15", 0 0, L_0x2b5da80; 1 drivers +v0x266c7d0_0 .net *"_s16", 0 0, L_0x2b5db20; 1 drivers +S_0x23fb050 .scope module, "ZeroMux" "FourInMux" 3 66, 3 125, S_0x23ddaa0; + .timescale -9 -12; +L_0x2b5b3c0/d .functor NOT 1, L_0x2b5bce0, C4<0>, C4<0>, C4<0>; +L_0x2b5b3c0 .delay (10000,10000,10000) L_0x2b5b3c0/d; +L_0x2b5b4b0/d .functor NOT 1, L_0x2b5be10, C4<0>, C4<0>, C4<0>; +L_0x2b5b4b0 .delay (10000,10000,10000) L_0x2b5b4b0/d; +L_0x2b5b550/d .functor NAND 1, L_0x2b5b3c0, L_0x2b5b4b0, L_0x2b5bf40, C4<1>; +L_0x2b5b550 .delay (10000,10000,10000) L_0x2b5b550/d; +L_0x2b5b690/d .functor NAND 1, L_0x2b5bce0, L_0x2b5b4b0, L_0x2b5bfe0, C4<1>; +L_0x2b5b690 .delay (10000,10000,10000) L_0x2b5b690/d; +L_0x2b5b7b0/d .functor NAND 1, L_0x2b5b3c0, L_0x2b5be10, L_0x2b5c080, C4<1>; +L_0x2b5b7b0 .delay (10000,10000,10000) L_0x2b5b7b0/d; +L_0x2b5b900/d .functor NAND 1, L_0x2b5bce0, L_0x2b5be10, L_0x2b5c170, C4<1>; +L_0x2b5b900 .delay (10000,10000,10000) L_0x2b5b900/d; +L_0x2b5ba70/d .functor NAND 1, L_0x2b5b550, L_0x2b5b690, L_0x2b5b7b0, L_0x2b5b900; +L_0x2b5ba70 .delay (10000,10000,10000) L_0x2b5ba70/d; +v0x2698480_0 .net "S0", 0 0, L_0x2b5bce0; 1 drivers +v0x26937d0_0 .net "S1", 0 0, L_0x2b5be10; 1 drivers +v0x2680740_0 .net "in0", 0 0, L_0x2b5bf40; 1 drivers +v0x2682110_0 .net "in1", 0 0, L_0x2b5bfe0; 1 drivers +v0x267ba90_0 .net "in2", 0 0, L_0x2b5c080; 1 drivers +v0x2676de0_0 .net "in3", 0 0, L_0x2b5c170; 1 drivers +v0x2672130_0 .net "nS0", 0 0, L_0x2b5b3c0; 1 drivers +v0x26635f0_0 .net "nS1", 0 0, L_0x2b5b4b0; 1 drivers +v0x265f040_0 .net "out", 0 0, L_0x2b5ba70; 1 drivers +v0x265a390_0 .net "out0", 0 0, L_0x2b5b550; 1 drivers +v0x26556e0_0 .net "out1", 0 0, L_0x2b5b690; 1 drivers +v0x2664370_0 .net "out2", 0 0, L_0x2b5b7b0; 1 drivers +v0x2667b60_0 .net "out3", 0 0, L_0x2b5b900; 1 drivers +S_0x23f5230 .scope module, "OneMux" "FourInMux" 3 67, 3 125, S_0x23ddaa0; + .timescale -9 -12; +L_0x2b5c260/d .functor NOT 1, L_0x2b5cb60, C4<0>, C4<0>, C4<0>; +L_0x2b5c260 .delay (10000,10000,10000) L_0x2b5c260/d; +L_0x2b5c350/d .functor NOT 1, L_0x2b5cc90, C4<0>, C4<0>, C4<0>; +L_0x2b5c350 .delay (10000,10000,10000) L_0x2b5c350/d; +L_0x2b5c3f0/d .functor NAND 1, L_0x2b5c260, L_0x2b5c350, L_0x2b5cdc0, C4<1>; +L_0x2b5c3f0 .delay (10000,10000,10000) L_0x2b5c3f0/d; +L_0x2b5c530/d .functor NAND 1, L_0x2b5cb60, L_0x2b5c350, L_0x2b5e2e0, C4<1>; +L_0x2b5c530 .delay (10000,10000,10000) L_0x2b5c530/d; +L_0x2b5c620/d .functor NAND 1, L_0x2b5c260, L_0x2b5cc90, L_0x2b5e380, C4<1>; +L_0x2b5c620 .delay (10000,10000,10000) L_0x2b5c620/d; +L_0x2b5c740/d .functor NAND 1, L_0x2b5cb60, L_0x2b5cc90, L_0x2b5d0c0, C4<1>; +L_0x2b5c740 .delay (10000,10000,10000) L_0x2b5c740/d; +L_0x2b5c8b0/d .functor NAND 1, L_0x2b5c3f0, L_0x2b5c530, L_0x2b5c620, L_0x2b5c740; +L_0x2b5c8b0 .delay (10000,10000,10000) L_0x2b5c8b0/d; +v0x26efec0_0 .net "S0", 0 0, L_0x2b5cb60; 1 drivers +v0x26f2cc0_0 .net "S1", 0 0, L_0x2b5cc90; 1 drivers +v0x26f5ad0_0 .net "in0", 0 0, L_0x2b5cdc0; 1 drivers +v0x26f8910_0 .net "in1", 0 0, L_0x2b5e2e0; 1 drivers +v0x26fb750_0 .net "in2", 0 0, L_0x2b5e380; 1 drivers +v0x26fe590_0 .net "in3", 0 0, L_0x2b5d0c0; 1 drivers +v0x26d65c0_0 .net "nS0", 0 0, L_0x2b5c260; 1 drivers +v0x26c2db0_0 .net "nS1", 0 0, L_0x2b5c350; 1 drivers +v0x26be830_0 .net "out", 0 0, L_0x2b5c8b0; 1 drivers +v0x26b9b80_0 .net "out0", 0 0, L_0x2b5c3f0; 1 drivers +v0x26b4ed0_0 .net "out1", 0 0, L_0x2b5c530; 1 drivers +v0x26a1de0_0 .net "out2", 0 0, L_0x2b5c620; 1 drivers +v0x269d130_0 .net "out3", 0 0, L_0x2b5c740; 1 drivers +S_0x23ef410 .scope module, "TwoMux" "TwoInMux" 3 68, 3 109, S_0x23ddaa0; + .timescale -9 -12; +L_0x2b5d1b0/d .functor NOT 1, L_0x2b5d620, C4<0>, C4<0>, C4<0>; +L_0x2b5d1b0 .delay (10000,10000,10000) L_0x2b5d1b0/d; +L_0x2b5d260/d .functor AND 1, L_0x2b5d6c0, L_0x2b5d1b0, C4<1>, C4<1>; +L_0x2b5d260 .delay (20000,20000,20000) L_0x2b5d260/d; +L_0x2b5d350/d .functor AND 1, L_0x2b5d7b0, L_0x2b5d620, C4<1>, C4<1>; +L_0x2b5d350 .delay (20000,20000,20000) L_0x2b5d350/d; +L_0x2b5d440/d .functor OR 1, L_0x2b5d260, L_0x2b5d350, C4<0>, C4<0>; +L_0x2b5d440 .delay (20000,20000,20000) L_0x2b5d440/d; +v0x272f1b0_0 .net "S", 0 0, L_0x2b5d620; 1 drivers +v0x2731fb0_0 .net "in0", 0 0, L_0x2b5d6c0; 1 drivers +v0x2734dd0_0 .net "in1", 0 0, L_0x2b5d7b0; 1 drivers +v0x2737c10_0 .net "nS", 0 0, L_0x2b5d1b0; 1 drivers +v0x273aa50_0 .net "out0", 0 0, L_0x2b5d260; 1 drivers +v0x26ea2c0_0 .net "out1", 0 0, L_0x2b5d350; 1 drivers +v0x26ed0c0_0 .net "outfinal", 0 0, L_0x2b5d440; 1 drivers +S_0x23b5880 .scope generate, "muxbits[29]" "muxbits[29]" 3 64, 3 64, S_0x1f6b890; + .timescale -9 -12; +P_0x1d35f18 .param/l "i" 3 64, +C4<011101>; +L_0x2b60190/d .functor OR 1, L_0x2b602d0, L_0x2b60370, C4<0>, C4<0>; +L_0x2b60190 .delay (20000,20000,20000) L_0x2b60190/d; +v0x27295b0_0 .net *"_s15", 0 0, L_0x2b602d0; 1 drivers +v0x272c3b0_0 .net *"_s16", 0 0, L_0x2b60370; 1 drivers +S_0x23d7f40 .scope module, "ZeroMux" "FourInMux" 3 66, 3 125, S_0x23b5880; + .timescale -9 -12; +L_0x2b5dc10/d .functor NOT 1, L_0x2b5f930, C4<0>, C4<0>, C4<0>; +L_0x2b5dc10 .delay (10000,10000,10000) L_0x2b5dc10/d; +L_0x2b5dd00/d .functor NOT 1, L_0x2b5e470, C4<0>, C4<0>, C4<0>; +L_0x2b5dd00 .delay (10000,10000,10000) L_0x2b5dd00/d; +L_0x2b5dda0/d .functor NAND 1, L_0x2b5dc10, L_0x2b5dd00, L_0x2b5e5a0, C4<1>; +L_0x2b5dda0 .delay (10000,10000,10000) L_0x2b5dda0/d; +L_0x2b5dee0/d .functor NAND 1, L_0x2b5f930, L_0x2b5dd00, L_0x2b5e640, C4<1>; +L_0x2b5dee0 .delay (10000,10000,10000) L_0x2b5dee0/d; +L_0x2b5dfd0/d .functor NAND 1, L_0x2b5dc10, L_0x2b5e470, L_0x2b5e6e0, C4<1>; +L_0x2b5dfd0 .delay (10000,10000,10000) L_0x2b5dfd0/d; +L_0x2b5e0f0/d .functor NAND 1, L_0x2b5f930, L_0x2b5e470, L_0x2b5e7d0, C4<1>; +L_0x2b5e0f0 .delay (10000,10000,10000) L_0x2b5e0f0/d; +L_0x2b5e260/d .functor NAND 1, L_0x2b5dda0, L_0x2b5dee0, L_0x2b5dfd0, L_0x2b5e0f0; +L_0x2b5e260 .delay (10000,10000,10000) L_0x2b5e260/d; +v0x270ca30_0 .net "S0", 0 0, L_0x2b5f930; 1 drivers +v0x270f830_0 .net "S1", 0 0, L_0x2b5e470; 1 drivers +v0x2712630_0 .net "in0", 0 0, L_0x2b5e5a0; 1 drivers +v0x2715450_0 .net "in1", 0 0, L_0x2b5e640; 1 drivers +v0x2718290_0 .net "in2", 0 0, L_0x2b5e6e0; 1 drivers +v0x271b0d0_0 .net "in3", 0 0, L_0x2b5e7d0; 1 drivers +v0x271df10_0 .net "nS0", 0 0, L_0x2b5dc10; 1 drivers +v0x26e1930_0 .net "nS1", 0 0, L_0x2b5dd00; 1 drivers +v0x26e74c0_0 .net "out", 0 0, L_0x2b5e260; 1 drivers +v0x2720d50_0 .net "out0", 0 0, L_0x2b5dda0; 1 drivers +v0x2723b90_0 .net "out1", 0 0, L_0x2b5dee0; 1 drivers +v0x2723dd0_0 .net "out2", 0 0, L_0x2b5dfd0; 1 drivers +v0x27267b0_0 .net "out3", 0 0, L_0x2b5e0f0; 1 drivers +S_0x23d23e0 .scope module, "OneMux" "FourInMux" 3 67, 3 125, S_0x23b5880; + .timescale -9 -12; +L_0x2b5e8c0/d .functor NOT 1, L_0x2b5f1f0, C4<0>, C4<0>, C4<0>; +L_0x2b5e8c0 .delay (10000,10000,10000) L_0x2b5e8c0/d; +L_0x2b5e9b0/d .functor NOT 1, L_0x2b5f320, C4<0>, C4<0>, C4<0>; +L_0x2b5e9b0 .delay (10000,10000,10000) L_0x2b5e9b0/d; +L_0x2b5ea50/d .functor NAND 1, L_0x2b5e8c0, L_0x2b5e9b0, L_0x2b5f450, C4<1>; +L_0x2b5ea50 .delay (10000,10000,10000) L_0x2b5ea50/d; +L_0x2b5eb90/d .functor NAND 1, L_0x2b5f1f0, L_0x2b5e9b0, L_0x2b5f4f0, C4<1>; +L_0x2b5eb90 .delay (10000,10000,10000) L_0x2b5eb90/d; +L_0x2b5ec80/d .functor NAND 1, L_0x2b5e8c0, L_0x2b5f320, L_0x2b5f590, C4<1>; +L_0x2b5ec80 .delay (10000,10000,10000) L_0x2b5ec80/d; +L_0x2b5edd0/d .functor NAND 1, L_0x2b5f1f0, L_0x2b5f320, L_0x2b60d30, C4<1>; +L_0x2b5edd0 .delay (10000,10000,10000) L_0x2b5edd0/d; +L_0x2b5ef40/d .functor NAND 1, L_0x2b5ea50, L_0x2b5eb90, L_0x2b5ec80, L_0x2b5edd0; +L_0x2b5ef40 .delay (10000,10000,10000) L_0x2b5ef40/d; +v0x27020f0_0 .net "S0", 0 0, L_0x2b5f1f0; 1 drivers +v0x26ff2b0_0 .net "S1", 0 0, L_0x2b5f320; 1 drivers +v0x26fc470_0 .net "in0", 0 0, L_0x2b5f450; 1 drivers +v0x26f9630_0 .net "in1", 0 0, L_0x2b5f4f0; 1 drivers +v0x26f67f0_0 .net "in2", 0 0, L_0x2b5f590; 1 drivers +v0x26f39b0_0 .net "in3", 0 0, L_0x2b60d30; 1 drivers +v0x26e31c0_0 .net "nS0", 0 0, L_0x2b5e8c0; 1 drivers +v0x26e2710_0 .net "nS1", 0 0, L_0x2b5e9b0; 1 drivers +v0x26e15c0_0 .net "out", 0 0, L_0x2b5ef40; 1 drivers +v0x27013d0_0 .net "out0", 0 0, L_0x2b5ea50; 1 drivers +v0x26e46c0_0 .net "out1", 0 0, L_0x2b5eb90; 1 drivers +v0x2706e30_0 .net "out2", 0 0, L_0x2b5ec80; 1 drivers +v0x2709c30_0 .net "out3", 0 0, L_0x2b5edd0; 1 drivers +S_0x23bb3e0 .scope module, "TwoMux" "TwoInMux" 3 68, 3 109, S_0x23b5880; + .timescale -9 -12; +L_0x2b5ee60/d .functor NOT 1, L_0x2b5fe70, C4<0>, C4<0>, C4<0>; +L_0x2b5ee60 .delay (10000,10000,10000) L_0x2b5ee60/d; +L_0x2b5fab0/d .functor AND 1, L_0x2b5ff10, L_0x2b5ee60, C4<1>, C4<1>; +L_0x2b5fab0 .delay (20000,20000,20000) L_0x2b5fab0/d; +L_0x2b5fba0/d .functor AND 1, L_0x2b60000, L_0x2b5fe70, C4<1>, C4<1>; +L_0x2b5fba0 .delay (20000,20000,20000) L_0x2b5fba0/d; +L_0x2b5fc90/d .functor OR 1, L_0x2b5fab0, L_0x2b5fba0, C4<0>, C4<0>; +L_0x2b5fc90 .delay (20000,20000,20000) L_0x2b5fc90/d; +v0x2738930_0 .net "S", 0 0, L_0x2b5fe70; 1 drivers +v0x2735af0_0 .net "in0", 0 0, L_0x2b5ff10; 1 drivers +v0x2721a70_0 .net "in1", 0 0, L_0x2b60000; 1 drivers +v0x271ec30_0 .net "nS", 0 0, L_0x2b5ee60; 1 drivers +v0x271bdf0_0 .net "out0", 0 0, L_0x2b5fab0; 1 drivers +v0x2718fb0_0 .net "out1", 0 0, L_0x2b5fba0; 1 drivers +v0x2716170_0 .net "outfinal", 0 0, L_0x2b5fc90; 1 drivers +S_0x237c140 .scope generate, "muxbits[30]" "muxbits[30]" 3 64, 3 64, S_0x1f6b890; + .timescale -9 -12; +P_0x1d36378 .param/l "i" 3 64, +C4<011110>; +L_0x2b624f0/d .functor OR 1, L_0x2b62630, L_0x2b626d0, C4<0>, C4<0>; +L_0x2b624f0 .delay (20000,20000,20000) L_0x2b624f0/d; +v0x275c450_0 .net *"_s15", 0 0, L_0x2b62630; 1 drivers +v0x275da10_0 .net *"_s16", 0 0, L_0x2b626d0; 1 drivers +S_0x23afd20 .scope module, "ZeroMux" "FourInMux" 3 66, 3 125, S_0x237c140; + .timescale -9 -12; +L_0x2b60460/d .functor NOT 1, L_0x2b60dd0, C4<0>, C4<0>, C4<0>; +L_0x2b60460 .delay (10000,10000,10000) L_0x2b60460/d; +L_0x2b60550/d .functor NOT 1, L_0x2b60f00, C4<0>, C4<0>, C4<0>; +L_0x2b60550 .delay (10000,10000,10000) L_0x2b60550/d; +L_0x2b605f0/d .functor NAND 1, L_0x2b60460, L_0x2b60550, L_0x2b61030, C4<1>; +L_0x2b605f0 .delay (10000,10000,10000) L_0x2b605f0/d; +L_0x2b60730/d .functor NAND 1, L_0x2b60dd0, L_0x2b60550, L_0x2b610d0, C4<1>; +L_0x2b60730 .delay (10000,10000,10000) L_0x2b60730/d; +L_0x2b60880/d .functor NAND 1, L_0x2b60460, L_0x2b60f00, L_0x2b61170, C4<1>; +L_0x2b60880 .delay (10000,10000,10000) L_0x2b60880/d; +L_0x2b609d0/d .functor NAND 1, L_0x2b60dd0, L_0x2b60f00, L_0x2b61260, C4<1>; +L_0x2b609d0 .delay (10000,10000,10000) L_0x2b609d0/d; +L_0x2b60b40/d .functor NAND 1, L_0x2b605f0, L_0x2b60730, L_0x2b60880, L_0x2b609d0; +L_0x2b60b40 .delay (10000,10000,10000) L_0x2b60b40/d; +v0x2760590_0 .net "S0", 0 0, L_0x2b60dd0; 1 drivers +v0x2761b50_0 .net "S1", 0 0, L_0x2b60f00; 1 drivers +v0x2763110_0 .net "in0", 0 0, L_0x2b61030; 1 drivers +v0x2741240_0 .net "in1", 0 0, L_0x2b610d0; 1 drivers +v0x2742800_0 .net "in2", 0 0, L_0x2b61170; 1 drivers +v0x2743dc0_0 .net "in3", 0 0, L_0x2b61260; 1 drivers +v0x27541d0_0 .net "nS0", 0 0, L_0x2b60460; 1 drivers +v0x2755790_0 .net "nS1", 0 0, L_0x2b60550; 1 drivers +v0x2756d50_0 .net "out", 0 0, L_0x2b60b40; 1 drivers +v0x273fc80_0 .net "out0", 0 0, L_0x2b605f0; 1 drivers +v0x2758310_0 .net "out1", 0 0, L_0x2b60730; 1 drivers +v0x27598d0_0 .net "out2", 0 0, L_0x2b60880; 1 drivers +v0x275ae90_0 .net "out3", 0 0, L_0x2b609d0; 1 drivers +S_0x2398d00 .scope module, "OneMux" "FourInMux" 3 67, 3 125, S_0x237c140; + .timescale -9 -12; +L_0x2b61350/d .functor NOT 1, L_0x2b61c20, C4<0>, C4<0>, C4<0>; +L_0x2b61350 .delay (10000,10000,10000) L_0x2b61350/d; +L_0x2b61440/d .functor NOT 1, L_0x2b61d50, C4<0>, C4<0>, C4<0>; +L_0x2b61440 .delay (10000,10000,10000) L_0x2b61440/d; +L_0x2b614e0/d .functor NAND 1, L_0x2b61350, L_0x2b61440, L_0x2b61e80, C4<1>; +L_0x2b614e0 .delay (10000,10000,10000) L_0x2b614e0/d; +L_0x2b61620/d .functor NAND 1, L_0x2b61c20, L_0x2b61440, L_0x2b61f20, C4<1>; +L_0x2b61620 .delay (10000,10000,10000) L_0x2b61620/d; +L_0x2b61710/d .functor NAND 1, L_0x2b61350, L_0x2b61d50, L_0x2b61fc0, C4<1>; +L_0x2b61710 .delay (10000,10000,10000) L_0x2b61710/d; +L_0x2b61800/d .functor NAND 1, L_0x2b61c20, L_0x2b61d50, L_0x2b63550, C4<1>; +L_0x2b61800 .delay (10000,10000,10000) L_0x2b61800/d; +L_0x2b61970/d .functor NAND 1, L_0x2b614e0, L_0x2b61620, L_0x2b61710, L_0x2b61800; +L_0x2b61970 .delay (10000,10000,10000) L_0x2b61970/d; +v0x262b810_0 .net "S0", 0 0, L_0x2b61c20; 1 drivers +v0x26259b0_0 .net "S1", 0 0, L_0x2b61d50; 1 drivers +v0x260e0f0_0 .net "in0", 0 0, L_0x2b61e80; 1 drivers +v0x2608290_0 .net "in1", 0 0, L_0x2b61f20; 1 drivers +v0x25f09b0_0 .net "in2", 0 0, L_0x2b61fc0; 1 drivers +v0x25eab50_0 .net "in3", 0 0, L_0x2b63550; 1 drivers +v0x25e4cf0_0 .net "nS0", 0 0, L_0x2b61350; 1 drivers +v0x25cd430_0 .net "nS1", 0 0, L_0x2b61440; 1 drivers +v0x25c75d0_0 .net "out", 0 0, L_0x2b61970; 1 drivers +v0x25afcf0_0 .net "out0", 0 0, L_0x2b614e0; 1 drivers +v0x25a9e90_0 .net "out1", 0 0, L_0x2b61620; 1 drivers +v0x25a4030_0 .net "out2", 0 0, L_0x2b61710; 1 drivers +v0x275efd0_0 .net "out3", 0 0, L_0x2b61800; 1 drivers +S_0x23931a0 .scope module, "TwoMux" "TwoInMux" 3 68, 3 109, S_0x237c140; + .timescale -9 -12; +L_0x2b63640/d .functor NOT 1, L_0x2b621d0, C4<0>, C4<0>, C4<0>; +L_0x2b63640 .delay (10000,10000,10000) L_0x2b63640/d; +L_0x2b63730/d .functor AND 1, L_0x2b62270, L_0x2b63640, C4<1>, C4<1>; +L_0x2b63730 .delay (20000,20000,20000) L_0x2b63730/d; +L_0x2b63820/d .functor AND 1, L_0x2b62360, L_0x2b621d0, C4<1>, C4<1>; +L_0x2b63820 .delay (20000,20000,20000) L_0x2b63820/d; +L_0x2b63910/d .functor OR 1, L_0x2b63730, L_0x2b63820, C4<0>, C4<0>; +L_0x2b63910 .delay (20000,20000,20000) L_0x2b63910/d; +v0x27479c0_0 .net "S", 0 0, L_0x2b621d0; 1 drivers +v0x2744e40_0 .net "in0", 0 0, L_0x2b62270; 1 drivers +v0x2765840_0 .net "in1", 0 0, L_0x2b62360; 1 drivers +v0x1d410e0_0 .net "nS", 0 0, L_0x2b63640; 1 drivers +v0x1d3bc20_0 .net "out0", 0 0, L_0x2b63730; 1 drivers +v0x26430f0_0 .net "out1", 0 0, L_0x2b63820; 1 drivers +v0x2631670_0 .net "outfinal", 0 0, L_0x2b63910; 1 drivers +S_0x24b2060 .scope generate, "muxbits[31]" "muxbits[31]" 3 64, 3 64, S_0x1f6b890; + .timescale -9 -12; +P_0x1dd20e8 .param/l "i" 3 64, +C4<011111>; +L_0x2b64840/d .functor OR 1, L_0x2b64980, L_0x2b64a20, C4<0>, C4<0>; +L_0x2b64840 .delay (20000,20000,20000) L_0x2b64840/d; +v0x274d0c0_0 .net *"_s15", 0 0, L_0x2b64980; 1 drivers +v0x274a540_0 .net *"_s16", 0 0, L_0x2b64a20; 1 drivers +S_0x23765e0 .scope module, "ZeroMux" "FourInMux" 3 66, 3 125, S_0x24b2060; + .timescale -9 -12; +L_0x2b627c0/d .functor NOT 1, L_0x2b63090, C4<0>, C4<0>, C4<0>; +L_0x2b627c0 .delay (10000,10000,10000) L_0x2b627c0/d; +L_0x2b628b0/d .functor NOT 1, L_0x2b631c0, C4<0>, C4<0>, C4<0>; +L_0x2b628b0 .delay (10000,10000,10000) L_0x2b628b0/d; +L_0x2b62950/d .functor NAND 1, L_0x2b627c0, L_0x2b628b0, L_0x2b632f0, C4<1>; +L_0x2b62950 .delay (10000,10000,10000) L_0x2b62950/d; +L_0x2b62a90/d .functor NAND 1, L_0x2b63090, L_0x2b628b0, L_0x2b63390, C4<1>; +L_0x2b62a90 .delay (10000,10000,10000) L_0x2b62a90/d; +L_0x2b62b80/d .functor NAND 1, L_0x2b627c0, L_0x2b631c0, L_0x2b63430, C4<1>; +L_0x2b62b80 .delay (10000,10000,10000) L_0x2b62b80/d; +L_0x2b62c70/d .functor NAND 1, L_0x2b63090, L_0x2b631c0, L_0x2b64ee0, C4<1>; +L_0x2b62c70 .delay (10000,10000,10000) L_0x2b62c70/d; +L_0x2b62de0/d .functor NAND 1, L_0x2b62950, L_0x2b62a90, L_0x2b62b80, L_0x2b62c70; +L_0x2b62de0 .delay (10000,10000,10000) L_0x2b62de0/d; +v0x23a3090_0 .net "S0", 0 0, L_0x2b63090; 1 drivers +v0x23a1050_0 .net "S1", 0 0, L_0x2b631c0; 1 drivers +v0x23a8ce0_0 .net "in0", 0 0, L_0x2b632f0; 1 drivers +v0x23a6ca0_0 .net "in1", 0 0, L_0x2b63390; 1 drivers +v0x23ac8f0_0 .net "in2", 0 0, L_0x2b63430; 1 drivers +v0x23bfb70_0 .net "in3", 0 0, L_0x2b64ee0; 1 drivers +v0x23c57c0_0 .net "nS0", 0 0, L_0x2b627c0; 1 drivers +v0x23c3780_0 .net "nS1", 0 0, L_0x2b628b0; 1 drivers +v0x23cb410_0 .net "out", 0 0, L_0x2b62de0; 1 drivers +v0x23c93d0_0 .net "out0", 0 0, L_0x2b62950; 1 drivers +v0x23e0240_0 .net "out1", 0 0, L_0x2b62a90; 1 drivers +v0x27527c0_0 .net "out2", 0 0, L_0x2b62b80; 1 drivers +v0x274fc40_0 .net "out3", 0 0, L_0x2b62c70; 1 drivers +S_0x2370a80 .scope module, "OneMux" "FourInMux" 3 67, 3 125, S_0x24b2060; + .timescale -9 -12; +L_0x2b62d00/d .functor NOT 1, L_0x2b63af0, C4<0>, C4<0>, C4<0>; +L_0x2b62d00 .delay (10000,10000,10000) L_0x2b62d00/d; +L_0x2b3ac30/d .functor NOT 1, L_0x2b63c20, C4<0>, C4<0>, C4<0>; +L_0x2b3ac30 .delay (10000,10000,10000) L_0x2b3ac30/d; +L_0x2b3acd0/d .functor NAND 1, L_0x2b62d00, L_0x2b3ac30, L_0x2b63d50, C4<1>; +L_0x2b3acd0 .delay (10000,10000,10000) L_0x2b3acd0/d; +L_0x2b65470/d .functor NAND 1, L_0x2b63af0, L_0x2b3ac30, L_0x2b63df0, C4<1>; +L_0x2b65470 .delay (10000,10000,10000) L_0x2b65470/d; +L_0x2b65560/d .functor NAND 1, L_0x2b62d00, L_0x2b63c20, L_0x2b63e90, C4<1>; +L_0x2b65560 .delay (10000,10000,10000) L_0x2b65560/d; +L_0x2b65680/d .functor NAND 1, L_0x2b63af0, L_0x2b63c20, L_0x2b63f80, C4<1>; +L_0x2b65680 .delay (10000,10000,10000) L_0x2b65680/d; +L_0x2b657f0/d .functor NAND 1, L_0x2b3acd0, L_0x2b65470, L_0x2b65560, L_0x2b65680; +L_0x2b657f0 .delay (10000,10000,10000) L_0x2b657f0/d; +v0x252c3f0_0 .net "S0", 0 0, L_0x2b63af0; 1 drivers +v0x2529870_0 .net "S1", 0 0, L_0x2b63c20; 1 drivers +v0x2526cf0_0 .net "in0", 0 0, L_0x2b63d50; 1 drivers +v0x2524170_0 .net "in1", 0 0, L_0x2b63df0; 1 drivers +v0x25215f0_0 .net "in2", 0 0, L_0x2b63e90; 1 drivers +v0x23699c0_0 .net "in3", 0 0, L_0x2b63f80; 1 drivers +v0x23678b0_0 .net "nS0", 0 0, L_0x2b62d00; 1 drivers +v0x2380930_0 .net "nS1", 0 0, L_0x2b3ac30; 1 drivers +v0x237e8f0_0 .net "out", 0 0, L_0x2b657f0; 1 drivers +v0x2386580_0 .net "out0", 0 0, L_0x2b3acd0; 1 drivers +v0x2384540_0 .net "out1", 0 0, L_0x2b65470; 1 drivers +v0x238c1d0_0 .net "out2", 0 0, L_0x2b65560; 1 drivers +v0x238a190_0 .net "out3", 0 0, L_0x2b65680; 1 drivers +S_0x249f0b0 .scope module, "TwoMux" "TwoInMux" 3 68, 3 109, S_0x24b2060; + .timescale -9 -12; +L_0x2b64070/d .functor NOT 1, L_0x2b64520, C4<0>, C4<0>, C4<0>; +L_0x2b64070 .delay (10000,10000,10000) L_0x2b64070/d; +L_0x2b64160/d .functor AND 1, L_0x2b645c0, L_0x2b64070, C4<1>, C4<1>; +L_0x2b64160 .delay (20000,20000,20000) L_0x2b64160/d; +L_0x2b64250/d .functor AND 1, L_0x2b646b0, L_0x2b64520, C4<1>, C4<1>; +L_0x2b64250 .delay (20000,20000,20000) L_0x2b64250/d; +L_0x2b64340/d .functor OR 1, L_0x2b64160, L_0x2b64250, C4<0>, C4<0>; +L_0x2b64340 .delay (20000,20000,20000) L_0x2b64340/d; +v0x1d33020_0 .net "S", 0 0, L_0x2b64520; 1 drivers +v0x1d2c820_0 .net "in0", 0 0, L_0x2b645c0; 1 drivers +v0x1d22e40_0 .net "in1", 0 0, L_0x2b646b0; 1 drivers +v0x236b130_0 .net "nS", 0 0, L_0x2b64070; 1 drivers +v0x27ee2c0_0 .net "out0", 0 0, L_0x2b64160; 1 drivers +v0x1d3b070_0 .net "out1", 0 0, L_0x2b64250; 1 drivers +v0x1d4dd80_0 .net "outfinal", 0 0, L_0x2b64340; 1 drivers + .scope S_0x22efd20; T_0 ; - %vpi_call 2 158 "$dumpfile", "FullALU.vcd"; - %vpi_call 2 159 "$dumpvars"; - %vpi_call 2 161 "$display", "Test 4 Bit Adder Functionality"; - %vpi_call 2 163 "$display", " A | B |Command| Out|ExpectedOut|Cout|OF"; - %movi 8, 2, 4; - %set/v v0xffc310_0, 8, 4; - %movi 8, 4, 4; - %set/v v0xffc560_0, 8, 4; - %set/v v0xffc5e0_0, 0, 3; + %vpi_call 2 167 "$dumpfile", "FullALU.vcd"; + %vpi_call 2 168 "$dumpvars"; + %vpi_call 2 170 "$display", "Test 4 Bit Adder Functionality"; + %vpi_call 2 172 "$display", " A | B |Command| Out|ExpectedOut|Cout|OF"; + %movi 8, 2, 32; + %set/v v0x295fe90_0, 8, 32; + %movi 8, 4, 32; + %set/v v0x2960190_0, 8, 32; + %set/v v0x2960210_0, 0, 3; %delay 1000000, 0; - %vpi_call 2 167 "$display", "%b | %b | %b | %b | Expect 0110| %b | %b ", v0xffc310_0, v0xffc560_0, v0xffc5e0_0, v0xffc3b0_0, v0xffcb10_0, v0xffcc10_0; - %movi 8, 1, 4; - %set/v v0xffc310_0, 8, 4; - %movi 8, 6, 4; - %set/v v0xffc560_0, 8, 4; - %set/v v0xffc5e0_0, 0, 3; + %vpi_call 2 176 "$display", "%b | %b | %b | %b | Expect 0110| %b | %b ", v0x295fe90_0, v0x2960190_0, v0x2960210_0, v0x295ff30_0, v0x2960870_0, v0x2960980_0; + %movi 8, 1, 32; + %set/v v0x295fe90_0, 8, 32; + %movi 8, 6, 32; + %set/v v0x2960190_0, 8, 32; + %set/v v0x2960210_0, 0, 3; %delay 1000000, 0; - %vpi_call 2 171 "$display", "%b | %b | %b | %b | Expect 0111| %b | %b ", v0xffc310_0, v0xffc560_0, v0xffc5e0_0, v0xffc3b0_0, v0xffcb10_0, v0xffcc10_0; - %movi 8, 5, 4; - %set/v v0xffc310_0, 8, 4; - %movi 8, 13, 4; - %set/v v0xffc560_0, 8, 4; - %set/v v0xffc5e0_0, 0, 3; + %vpi_call 2 180 "$display", "%b | %b | %b | %b | Expect 0111| %b | %b ", v0x295fe90_0, v0x2960190_0, v0x2960210_0, v0x295ff30_0, v0x2960870_0, v0x2960980_0; + %movi 8, 5, 32; + %set/v v0x295fe90_0, 8, 32; + %movi 8, 13, 32; + %set/v v0x2960190_0, 8, 32; + %set/v v0x2960210_0, 0, 3; %delay 1000000, 0; - %vpi_call 2 175 "$display", "%b | %b | %b | %b | Expect 0010| %b | %b ", v0xffc310_0, v0xffc560_0, v0xffc5e0_0, v0xffc3b0_0, v0xffcb10_0, v0xffcc10_0; - %movi 8, 2, 4; - %set/v v0xffc310_0, 8, 4; - %set/v v0xffc560_0, 1, 4; - %set/v v0xffc5e0_0, 0, 3; + %vpi_call 2 184 "$display", "%b | %b | %b | %b | Expect 0010| %b | %b ", v0x295fe90_0, v0x2960190_0, v0x2960210_0, v0x295ff30_0, v0x2960870_0, v0x2960980_0; + %movi 8, 2, 32; + %set/v v0x295fe90_0, 8, 32; + %movi 8, 15, 32; + %set/v v0x2960190_0, 8, 32; + %set/v v0x2960210_0, 0, 3; %delay 1000000, 0; - %vpi_call 2 179 "$display", "%b | %b | %b | %b | Expect 0001| %b | %b ", v0xffc310_0, v0xffc560_0, v0xffc5e0_0, v0xffc3b0_0, v0xffcb10_0, v0xffcc10_0; - %movi 8, 8, 4; - %set/v v0xffc310_0, 8, 4; - %movi 8, 3, 4; - %set/v v0xffc560_0, 8, 4; - %set/v v0xffc5e0_0, 0, 3; + %vpi_call 2 188 "$display", "%b | %b | %b | %b | Expect 0001| %b | %b ", v0x295fe90_0, v0x2960190_0, v0x2960210_0, v0x295ff30_0, v0x2960870_0, v0x2960980_0; + %movi 8, 8, 32; + %set/v v0x295fe90_0, 8, 32; + %movi 8, 3, 32; + %set/v v0x2960190_0, 8, 32; + %set/v v0x2960210_0, 0, 3; %delay 1000000, 0; - %vpi_call 2 183 "$display", "%b | %b | %b | %b | Expect 1011| %b | %b ", v0xffc310_0, v0xffc560_0, v0xffc5e0_0, v0xffc3b0_0, v0xffcb10_0, v0xffcc10_0; - %movi 8, 12, 4; - %set/v v0xffc310_0, 8, 4; - %movi 8, 2, 4; - %set/v v0xffc560_0, 8, 4; - %set/v v0xffc5e0_0, 0, 3; + %vpi_call 2 192 "$display", "%b | %b | %b | %b | Expect 1011| %b | %b ", v0x295fe90_0, v0x2960190_0, v0x2960210_0, v0x295ff30_0, v0x2960870_0, v0x2960980_0; + %movi 8, 12, 32; + %set/v v0x295fe90_0, 8, 32; + %movi 8, 2, 32; + %set/v v0x2960190_0, 8, 32; + %set/v v0x2960210_0, 0, 3; %delay 1000000, 0; - %vpi_call 2 187 "$display", "%b | %b | %b | %b | Expect 1110| %b | %b ", v0xffc310_0, v0xffc560_0, v0xffc5e0_0, v0xffc3b0_0, v0xffcb10_0, v0xffcc10_0; - %movi 8, 11, 4; - %set/v v0xffc310_0, 8, 4; - %movi 8, 5, 4; - %set/v v0xffc560_0, 8, 4; - %set/v v0xffc5e0_0, 0, 3; + %vpi_call 2 196 "$display", "%b | %b | %b | %b | Expect 1110| %b | %b ", v0x295fe90_0, v0x2960190_0, v0x2960210_0, v0x295ff30_0, v0x2960870_0, v0x2960980_0; + %movi 8, 11, 32; + %set/v v0x295fe90_0, 8, 32; + %movi 8, 5, 32; + %set/v v0x2960190_0, 8, 32; + %set/v v0x2960210_0, 0, 3; %delay 1000000, 0; - %vpi_call 2 191 "$display", "%b | %b | %b | %b | Expect 0000| %b | %b ", v0xffc310_0, v0xffc560_0, v0xffc5e0_0, v0xffc3b0_0, v0xffcb10_0, v0xffcc10_0; - %movi 8, 7, 4; - %set/v v0xffc310_0, 8, 4; - %movi 8, 9, 4; - %set/v v0xffc560_0, 8, 4; - %set/v v0xffc5e0_0, 0, 3; + %vpi_call 2 200 "$display", "%b | %b | %b | %b | Expect 0000| %b | %b ", v0x295fe90_0, v0x2960190_0, v0x2960210_0, v0x295ff30_0, v0x2960870_0, v0x2960980_0; + %movi 8, 7, 32; + %set/v v0x295fe90_0, 8, 32; + %movi 8, 9, 32; + %set/v v0x2960190_0, 8, 32; + %set/v v0x2960210_0, 0, 3; %delay 1000000, 0; - %vpi_call 2 195 "$display", "%b | %b | %b | %b | Expect 0000| %b | %b ", v0xffc310_0, v0xffc560_0, v0xffc5e0_0, v0xffc3b0_0, v0xffcb10_0, v0xffcc10_0; - %movi 8, 13, 4; - %set/v v0xffc310_0, 8, 4; - %movi 8, 12, 4; - %set/v v0xffc560_0, 8, 4; - %set/v v0xffc5e0_0, 0, 3; + %vpi_call 2 204 "$display", "%b | %b | %b | %b | Expect 0000| %b | %b ", v0x295fe90_0, v0x2960190_0, v0x2960210_0, v0x295ff30_0, v0x2960870_0, v0x2960980_0; + %movi 8, 13, 32; + %set/v v0x295fe90_0, 8, 32; + %movi 8, 12, 32; + %set/v v0x2960190_0, 8, 32; + %set/v v0x2960210_0, 0, 3; %delay 1000000, 0; - %vpi_call 2 199 "$display", "%b | %b | %b | %b | Expect 1001| %b | %b ", v0xffc310_0, v0xffc560_0, v0xffc5e0_0, v0xffc3b0_0, v0xffcb10_0, v0xffcc10_0; - %movi 8, 14, 4; - %set/v v0xffc310_0, 8, 4; - %movi 8, 10, 4; - %set/v v0xffc560_0, 8, 4; - %set/v v0xffc5e0_0, 0, 3; + %vpi_call 2 208 "$display", "%b | %b | %b | %b | Expect 1001| %b | %b ", v0x295fe90_0, v0x2960190_0, v0x2960210_0, v0x295ff30_0, v0x2960870_0, v0x2960980_0; + %movi 8, 14, 32; + %set/v v0x295fe90_0, 8, 32; + %movi 8, 10, 32; + %set/v v0x2960190_0, 8, 32; + %set/v v0x2960210_0, 0, 3; %delay 1000000, 0; - %vpi_call 2 203 "$display", "%b | %b | %b | %b | Expect 1000| %b | %b ", v0xffc310_0, v0xffc560_0, v0xffc5e0_0, v0xffc3b0_0, v0xffcb10_0, v0xffcc10_0; - %movi 8, 5, 4; - %set/v v0xffc310_0, 8, 4; - %movi 8, 6, 4; - %set/v v0xffc560_0, 8, 4; - %set/v v0xffc5e0_0, 0, 3; + %vpi_call 2 212 "$display", "%b | %b | %b | %b | Expect 1000| %b | %b ", v0x295fe90_0, v0x2960190_0, v0x2960210_0, v0x295ff30_0, v0x2960870_0, v0x2960980_0; + %movi 8, 5, 32; + %set/v v0x295fe90_0, 8, 32; + %movi 8, 6, 32; + %set/v v0x2960190_0, 8, 32; + %set/v v0x2960210_0, 0, 3; %delay 1000000, 0; - %vpi_call 2 207 "$display", "%b | %b | %b | %b | Expect XXXX| %b | %b ", v0xffc310_0, v0xffc560_0, v0xffc5e0_0, v0xffc3b0_0, v0xffcb10_0, v0xffcc10_0; - %movi 8, 2, 4; - %set/v v0xffc310_0, 8, 4; - %movi 8, 7, 4; - %set/v v0xffc560_0, 8, 4; - %set/v v0xffc5e0_0, 0, 3; + %vpi_call 2 216 "$display", "%b | %b | %b | %b | Expect XXXX| %b | %b ", v0x295fe90_0, v0x2960190_0, v0x2960210_0, v0x295ff30_0, v0x2960870_0, v0x2960980_0; + %movi 8, 2, 32; + %set/v v0x295fe90_0, 8, 32; + %movi 8, 7, 32; + %set/v v0x2960190_0, 8, 32; + %set/v v0x2960210_0, 0, 3; %delay 1000000, 0; - %vpi_call 2 211 "$display", "%b | %b | %b | %b | Expect XXXX| %b | %b ", v0xffc310_0, v0xffc560_0, v0xffc5e0_0, v0xffc3b0_0, v0xffcb10_0, v0xffcc10_0; - %movi 8, 7, 4; - %set/v v0xffc310_0, 8, 4; - %movi 8, 7, 4; - %set/v v0xffc560_0, 8, 4; - %set/v v0xffc5e0_0, 0, 3; + %vpi_call 2 220 "$display", "%b | %b | %b | %b | Expect XXXX| %b | %b ", v0x295fe90_0, v0x2960190_0, v0x2960210_0, v0x295ff30_0, v0x2960870_0, v0x2960980_0; + %movi 8, 7, 32; + %set/v v0x295fe90_0, 8, 32; + %movi 8, 7, 32; + %set/v v0x2960190_0, 8, 32; + %set/v v0x2960210_0, 0, 3; %delay 1000000, 0; - %vpi_call 2 215 "$display", "%b | %b | %b | %b | Expect XXXX| %b | %b ", v0xffc310_0, v0xffc560_0, v0xffc5e0_0, v0xffc3b0_0, v0xffcb10_0, v0xffcc10_0; - %movi 8, 8, 4; - %set/v v0xffc310_0, 8, 4; - %set/v v0xffc560_0, 1, 4; - %set/v v0xffc5e0_0, 0, 3; + %vpi_call 2 224 "$display", "%b | %b | %b | %b | Expect XXXX| %b | %b ", v0x295fe90_0, v0x2960190_0, v0x2960210_0, v0x295ff30_0, v0x2960870_0, v0x2960980_0; + %movi 8, 8, 32; + %set/v v0x295fe90_0, 8, 32; + %movi 8, 15, 32; + %set/v v0x2960190_0, 8, 32; + %set/v v0x2960210_0, 0, 3; %delay 1000000, 0; - %vpi_call 2 219 "$display", "%b | %b | %b | %b | Expect XXXX| %b | %b ", v0xffc310_0, v0xffc560_0, v0xffc5e0_0, v0xffc3b0_0, v0xffcb10_0, v0xffcc10_0; - %movi 8, 8, 4; - %set/v v0xffc310_0, 8, 4; - %movi 8, 13, 4; - %set/v v0xffc560_0, 8, 4; - %set/v v0xffc5e0_0, 0, 3; + %vpi_call 2 228 "$display", "%b | %b | %b | %b | Expect XXXX| %b | %b ", v0x295fe90_0, v0x2960190_0, v0x2960210_0, v0x295ff30_0, v0x2960870_0, v0x2960980_0; + %movi 8, 8, 32; + %set/v v0x295fe90_0, 8, 32; + %movi 8, 13, 32; + %set/v v0x2960190_0, 8, 32; + %set/v v0x2960210_0, 0, 3; %delay 1000000, 0; - %vpi_call 2 223 "$display", "%b | %b | %b | %b | Expect XXXX| %b | %b ", v0xffc310_0, v0xffc560_0, v0xffc5e0_0, v0xffc3b0_0, v0xffcb10_0, v0xffcc10_0; - %movi 8, 11, 4; - %set/v v0xffc310_0, 8, 4; - %movi 8, 12, 4; - %set/v v0xffc560_0, 8, 4; - %set/v v0xffc5e0_0, 0, 3; + %vpi_call 2 232 "$display", "%b | %b | %b | %b | Expect XXXX| %b | %b ", v0x295fe90_0, v0x2960190_0, v0x2960210_0, v0x295ff30_0, v0x2960870_0, v0x2960980_0; + %movi 8, 11, 32; + %set/v v0x295fe90_0, 8, 32; + %movi 8, 12, 32; + %set/v v0x2960190_0, 8, 32; + %set/v v0x2960210_0, 0, 3; %delay 1000000, 0; - %vpi_call 2 227 "$display", "%b | %b | %b | %b | Expect XXXX| %b | %b ", v0xffc310_0, v0xffc560_0, v0xffc5e0_0, v0xffc3b0_0, v0xffcb10_0, v0xffcc10_0; - %vpi_call 2 229 "$display", "Test 4 Bit SLT Functionality"; - %vpi_call 2 231 "$display", " A | B |Command| Out|ExpectedOut|Cout|OF |SLTflag"; - %movi 8, 2, 4; - %set/v v0xffc310_0, 8, 4; - %movi 8, 4, 4; - %set/v v0xffc560_0, 8, 4; + %vpi_call 2 236 "$display", "%b | %b | %b | %b | Expect XXXX| %b | %b ", v0x295fe90_0, v0x2960190_0, v0x2960210_0, v0x295ff30_0, v0x2960870_0, v0x2960980_0; + %vpi_call 2 238 "$display", "Test 4 Bit SLT Functionality"; + %vpi_call 2 240 "$display", " A | B |Command| Out|ExpectedOut|Cout|OF |SLTflag"; + %movi 8, 2, 32; + %set/v v0x295fe90_0, 8, 32; + %movi 8, 4, 32; + %set/v v0x2960190_0, 8, 32; %movi 8, 3, 3; - %set/v v0xffc5e0_0, 8, 3; + %set/v v0x2960210_0, 8, 3; %delay 1000000, 0; - %vpi_call 2 235 "$display", "%b | %b | %b | %b | Expect 0001| %b | %b | %b", v0xffc310_0, v0xffc560_0, v0xffc5e0_0, v0xffc760_0, v0xffcb10_0, v0xffcc10_0, v0xffc8f0_0; - %movi 8, 4, 4; - %set/v v0xffc310_0, 8, 4; - %movi 8, 2, 4; - %set/v v0xffc560_0, 8, 4; + %vpi_call 2 244 "$display", "%b | %b | %b | %b | Expect 0001| %b | %b | %b", v0x295fe90_0, v0x2960190_0, v0x2960210_0, v0x2960440_0, v0x2960870_0, v0x2960980_0, v0x2960640_0; + %movi 8, 4, 32; + %set/v v0x295fe90_0, 8, 32; + %movi 8, 2, 32; + %set/v v0x2960190_0, 8, 32; %movi 8, 3, 3; - %set/v v0xffc5e0_0, 8, 3; + %set/v v0x2960210_0, 8, 3; %delay 1000000, 0; - %vpi_call 2 239 "$display", "%b | %b | %b | %b | Expect 0000| %b | %b | %b", v0xffc310_0, v0xffc560_0, v0xffc5e0_0, v0xffc760_0, v0xffcb10_0, v0xffcc10_0, v0xffc8f0_0; - %movi 8, 14, 4; - %set/v v0xffc310_0, 8, 4; - %movi 8, 4, 4; - %set/v v0xffc560_0, 8, 4; + %vpi_call 2 248 "$display", "%b | %b | %b | %b | Expect 0000| %b | %b | %b", v0x295fe90_0, v0x2960190_0, v0x2960210_0, v0x2960440_0, v0x2960870_0, v0x2960980_0, v0x2960640_0; + %movi 8, 14, 32; + %set/v v0x295fe90_0, 8, 32; + %movi 8, 4, 32; + %set/v v0x2960190_0, 8, 32; %movi 8, 3, 3; - %set/v v0xffc5e0_0, 8, 3; + %set/v v0x2960210_0, 8, 3; %delay 1000000, 0; - %vpi_call 2 243 "$display", "%b | %b | %b | %b | Expect 0001| %b | %b | %b", v0xffc310_0, v0xffc560_0, v0xffc5e0_0, v0xffc760_0, v0xffcb10_0, v0xffcc10_0, v0xffc8f0_0; - %movi 8, 4, 4; - %set/v v0xffc310_0, 8, 4; - %movi 8, 14, 4; - %set/v v0xffc560_0, 8, 4; + %vpi_call 2 252 "$display", "%b | %b | %b | %b | Expect 0001| %b | %b | %b", v0x295fe90_0, v0x2960190_0, v0x2960210_0, v0x2960440_0, v0x2960870_0, v0x2960980_0, v0x2960640_0; + %movi 8, 4, 32; + %set/v v0x295fe90_0, 8, 32; + %movi 8, 14, 32; + %set/v v0x2960190_0, 8, 32; %movi 8, 3, 3; - %set/v v0xffc5e0_0, 8, 3; + %set/v v0x2960210_0, 8, 3; %delay 1000000, 0; - %vpi_call 2 247 "$display", "%b | %b | %b | %b | Expect 0000| %b | %b | %b", v0xffc310_0, v0xffc560_0, v0xffc5e0_0, v0xffc760_0, v0xffcb10_0, v0xffcc10_0, v0xffc8f0_0; - %movi 8, 14, 4; - %set/v v0xffc310_0, 8, 4; - %set/v v0xffc560_0, 1, 4; + %vpi_call 2 256 "$display", "%b | %b | %b | %b | Expect 0000| %b | %b | %b", v0x295fe90_0, v0x2960190_0, v0x2960210_0, v0x2960440_0, v0x2960870_0, v0x2960980_0, v0x2960640_0; + %movi 8, 14, 32; + %set/v v0x295fe90_0, 8, 32; + %movi 8, 15, 32; + %set/v v0x2960190_0, 8, 32; %movi 8, 3, 3; - %set/v v0xffc5e0_0, 8, 3; + %set/v v0x2960210_0, 8, 3; %delay 1000000, 0; - %vpi_call 2 251 "$display", "%b | %b | %b | %b | Expect 0001| %b | %b | %b", v0xffc310_0, v0xffc560_0, v0xffc5e0_0, v0xffc760_0, v0xffcb10_0, v0xffcc10_0, v0xffc8f0_0; - %set/v v0xffc310_0, 1, 4; - %movi 8, 14, 4; - %set/v v0xffc560_0, 8, 4; + %vpi_call 2 260 "$display", "%b | %b | %b | %b | Expect 0001| %b | %b | %b", v0x295fe90_0, v0x2960190_0, v0x2960210_0, v0x2960440_0, v0x2960870_0, v0x2960980_0, v0x2960640_0; + %movi 8, 15, 32; + %set/v v0x295fe90_0, 8, 32; + %movi 8, 14, 32; + %set/v v0x2960190_0, 8, 32; %movi 8, 3, 3; - %set/v v0xffc5e0_0, 8, 3; + %set/v v0x2960210_0, 8, 3; %delay 1000000, 0; - %vpi_call 2 255 "$display", "%b | %b | %b | %b | Expect 0000| %b | %b | %b", v0xffc310_0, v0xffc560_0, v0xffc5e0_0, v0xffc760_0, v0xffcb10_0, v0xffcc10_0, v0xffc8f0_0; - %movi 8, 13, 4; - %set/v v0xffc310_0, 8, 4; - %movi 8, 13, 4; - %set/v v0xffc560_0, 8, 4; + %vpi_call 2 264 "$display", "%b | %b | %b | %b | Expect 0000| %b | %b | %b", v0x295fe90_0, v0x2960190_0, v0x2960210_0, v0x2960440_0, v0x2960870_0, v0x2960980_0, v0x2960640_0; + %movi 8, 13, 32; + %set/v v0x295fe90_0, 8, 32; + %movi 8, 13, 32; + %set/v v0x2960190_0, 8, 32; %movi 8, 3, 3; - %set/v v0xffc5e0_0, 8, 3; + %set/v v0x2960210_0, 8, 3; %delay 1000000, 0; - %vpi_call 2 259 "$display", "%b | %b | %b | %b | Expect 0000| %b | %b | %b", v0xffc310_0, v0xffc560_0, v0xffc5e0_0, v0xffc760_0, v0xffcb10_0, v0xffcc10_0, v0xffc8f0_0; - %movi 8, 5, 4; - %set/v v0xffc310_0, 8, 4; - %movi 8, 5, 4; - %set/v v0xffc560_0, 8, 4; + %vpi_call 2 268 "$display", "%b | %b | %b | %b | Expect 0000| %b | %b | %b", v0x295fe90_0, v0x2960190_0, v0x2960210_0, v0x2960440_0, v0x2960870_0, v0x2960980_0, v0x2960640_0; + %movi 8, 5, 32; + %set/v v0x295fe90_0, 8, 32; + %movi 8, 5, 32; + %set/v v0x2960190_0, 8, 32; %movi 8, 3, 3; - %set/v v0xffc5e0_0, 8, 3; + %set/v v0x2960210_0, 8, 3; %delay 1000000, 0; - %vpi_call 2 263 "$display", "%b | %b | %b | %b | Expect 0000| %b | %b | %b", v0xffc310_0, v0xffc560_0, v0xffc5e0_0, v0xffc760_0, v0xffcb10_0, v0xffcc10_0, v0xffc8f0_0; - %movi 8, 9, 4; - %set/v v0xffc310_0, 8, 4; - %movi 8, 5, 4; - %set/v v0xffc560_0, 8, 4; + %vpi_call 2 272 "$display", "%b | %b | %b | %b | Expect 0000| %b | %b | %b", v0x295fe90_0, v0x2960190_0, v0x2960210_0, v0x2960440_0, v0x2960870_0, v0x2960980_0, v0x2960640_0; + %movi 8, 9, 32; + %set/v v0x295fe90_0, 8, 32; + %movi 8, 5, 32; + %set/v v0x2960190_0, 8, 32; %movi 8, 3, 3; - %set/v v0xffc5e0_0, 8, 3; + %set/v v0x2960210_0, 8, 3; %delay 1000000, 0; - %vpi_call 2 267 "$display", "%b | %b | %b | %b | Expect 0001| %b | %b | %b", v0xffc310_0, v0xffc560_0, v0xffc5e0_0, v0xffc760_0, v0xffcb10_0, v0xffcc10_0, v0xffc8f0_0; - %vpi_call 2 269 "$display", "Test 4 Bit AND/NAND Functionality"; - %vpi_call 2 271 "$display", " A | B |Command| Out |ExpectedOut-AND"; - %set/v v0xffc310_0, 1, 4; - %set/v v0xffc560_0, 1, 4; + %vpi_call 2 276 "$display", "%b | %b | %b | %b | Expect 0001| %b | %b | %b", v0x295fe90_0, v0x2960190_0, v0x2960210_0, v0x2960440_0, v0x2960870_0, v0x2960980_0, v0x2960640_0; + %vpi_call 2 278 "$display", "Test 4 Bit AND/NAND Functionality"; + %vpi_call 2 280 "$display", " A | B |Command| Out |ExpectedOut-AND"; + %movi 8, 15, 32; + %set/v v0x295fe90_0, 8, 32; + %movi 8, 15, 32; + %set/v v0x2960190_0, 8, 32; %movi 8, 4, 3; - %set/v v0xffc5e0_0, 8, 3; + %set/v v0x2960210_0, 8, 3; %delay 1000000, 0; - %vpi_call 2 275 "$display", "%b | %b | %b | %b | 1111", v0xffc310_0, v0xffc560_0, v0xffc5e0_0, v0xffc4b0_0; - %set/v v0xffc310_0, 1, 4; - %movi 8, 10, 4; - %set/v v0xffc560_0, 8, 4; + %vpi_call 2 284 "$display", "%b | %b | %b | %b | 1111", v0x295fe90_0, v0x2960190_0, v0x2960210_0, v0x2960110_0; + %movi 8, 15, 32; + %set/v v0x295fe90_0, 8, 32; + %movi 8, 10, 32; + %set/v v0x2960190_0, 8, 32; %movi 8, 4, 3; - %set/v v0xffc5e0_0, 8, 3; + %set/v v0x2960210_0, 8, 3; %delay 1000000, 0; - %vpi_call 2 279 "$display", "%b | %b | %b | %b | 1010", v0xffc310_0, v0xffc560_0, v0xffc5e0_0, v0xffc4b0_0; - %set/v v0xffc310_0, 1, 4; - %movi 8, 5, 4; - %set/v v0xffc560_0, 8, 4; + %vpi_call 2 288 "$display", "%b | %b | %b | %b | 1010", v0x295fe90_0, v0x2960190_0, v0x2960210_0, v0x2960110_0; + %movi 8, 15, 32; + %set/v v0x295fe90_0, 8, 32; + %movi 8, 5, 32; + %set/v v0x2960190_0, 8, 32; %movi 8, 4, 3; - %set/v v0xffc5e0_0, 8, 3; + %set/v v0x2960210_0, 8, 3; %delay 1000000, 0; - %vpi_call 2 283 "$display", "%b | %b | %b | %b | 0101", v0xffc310_0, v0xffc560_0, v0xffc5e0_0, v0xffc4b0_0; - %set/v v0xffc310_0, 1, 4; - %set/v v0xffc560_0, 0, 4; + %vpi_call 2 292 "$display", "%b | %b | %b | %b | 0101", v0x295fe90_0, v0x2960190_0, v0x2960210_0, v0x2960110_0; + %movi 8, 15, 32; + %set/v v0x295fe90_0, 8, 32; + %set/v v0x2960190_0, 0, 32; %movi 8, 4, 3; - %set/v v0xffc5e0_0, 8, 3; + %set/v v0x2960210_0, 8, 3; %delay 1000000, 0; - %vpi_call 2 287 "$display", "%b | %b | %b | %b | 0000", v0xffc310_0, v0xffc560_0, v0xffc5e0_0, v0xffc4b0_0; - %vpi_call 2 290 "$display", " A | B |Command| Out |ExpectedOut-NAND"; - %set/v v0xffc310_0, 1, 4; - %set/v v0xffc560_0, 1, 4; + %vpi_call 2 296 "$display", "%b | %b | %b | %b | 0000", v0x295fe90_0, v0x2960190_0, v0x2960210_0, v0x2960110_0; + %vpi_call 2 299 "$display", " A | B |Command| Out |ExpectedOut-NAND"; + %movi 8, 15, 32; + %set/v v0x295fe90_0, 8, 32; + %movi 8, 15, 32; + %set/v v0x2960190_0, 8, 32; %movi 8, 5, 3; - %set/v v0xffc5e0_0, 8, 3; + %set/v v0x2960210_0, 8, 3; %delay 1000000, 0; - %vpi_call 2 294 "$display", "%b | %b | %b | %b | 0000", v0xffc310_0, v0xffc560_0, v0xffc5e0_0, v0xffc4b0_0; - %set/v v0xffc310_0, 1, 4; - %movi 8, 10, 4; - %set/v v0xffc560_0, 8, 4; + %vpi_call 2 303 "$display", "%b | %b | %b | %b | 0000", v0x295fe90_0, v0x2960190_0, v0x2960210_0, v0x2960110_0; + %movi 8, 15, 32; + %set/v v0x295fe90_0, 8, 32; + %movi 8, 10, 32; + %set/v v0x2960190_0, 8, 32; %movi 8, 5, 3; - %set/v v0xffc5e0_0, 8, 3; + %set/v v0x2960210_0, 8, 3; %delay 1000000, 0; - %vpi_call 2 298 "$display", "%b | %b | %b | %b | 0101", v0xffc310_0, v0xffc560_0, v0xffc5e0_0, v0xffc4b0_0; - %set/v v0xffc310_0, 1, 4; - %movi 8, 5, 4; - %set/v v0xffc560_0, 8, 4; + %vpi_call 2 307 "$display", "%b | %b | %b | %b | 0101", v0x295fe90_0, v0x2960190_0, v0x2960210_0, v0x2960110_0; + %movi 8, 15, 32; + %set/v v0x295fe90_0, 8, 32; + %movi 8, 5, 32; + %set/v v0x2960190_0, 8, 32; %movi 8, 5, 3; - %set/v v0xffc5e0_0, 8, 3; + %set/v v0x2960210_0, 8, 3; %delay 1000000, 0; - %vpi_call 2 302 "$display", "%b | %b | %b | %b | 1010", v0xffc310_0, v0xffc560_0, v0xffc5e0_0, v0xffc4b0_0; - %set/v v0xffc310_0, 1, 4; - %set/v v0xffc560_0, 0, 4; + %vpi_call 2 311 "$display", "%b | %b | %b | %b | 1010", v0x295fe90_0, v0x2960190_0, v0x2960210_0, v0x2960110_0; + %movi 8, 15, 32; + %set/v v0x295fe90_0, 8, 32; + %set/v v0x2960190_0, 0, 32; %movi 8, 5, 3; - %set/v v0xffc5e0_0, 8, 3; + %set/v v0x2960210_0, 8, 3; %delay 1000000, 0; - %vpi_call 2 306 "$display", "%b | %b | %b | %b | 1111", v0xffc310_0, v0xffc560_0, v0xffc5e0_0, v0xffc4b0_0; - %vpi_call 2 308 "$display", "Test 4 Bit OR/NOR/XOR Functionality"; - %vpi_call 2 310 "$display", " A | B |Command | Out |ExpectedOut-OR"; - %movi 8, 10, 4; - %set/v v0xffc310_0, 8, 4; - %movi 8, 5, 4; - %set/v v0xffc560_0, 8, 4; - %set/v v0xffc5e0_0, 1, 3; + %vpi_call 2 315 "$display", "%b | %b | %b | %b | 1111", v0x295fe90_0, v0x2960190_0, v0x2960210_0, v0x2960110_0; + %vpi_call 2 317 "$display", "Test 4 Bit OR/NOR/XOR Functionality"; + %vpi_call 2 319 "$display", " A | B |Command | Out |ExpectedOut-OR"; + %movi 8, 10, 32; + %set/v v0x295fe90_0, 8, 32; + %movi 8, 5, 32; + %set/v v0x2960190_0, 8, 32; + %set/v v0x2960210_0, 1, 3; %delay 1000000, 0; - %vpi_call 2 314 "$display", "%b | %b | %b | %b | 1111", v0xffc310_0, v0xffc560_0, v0xffc5e0_0, v0xffc6e0_0; - %set/v v0xffc310_0, 1, 4; - %movi 8, 5, 4; - %set/v v0xffc560_0, 8, 4; - %set/v v0xffc5e0_0, 1, 3; + %vpi_call 2 323 "$display", "%b | %b | %b | %b | 1111", v0x295fe90_0, v0x2960190_0, v0x2960210_0, v0x29603c0_0; + %movi 8, 15, 32; + %set/v v0x295fe90_0, 8, 32; + %movi 8, 5, 32; + %set/v v0x2960190_0, 8, 32; + %set/v v0x2960210_0, 1, 3; %delay 1000000, 0; - %vpi_call 2 318 "$display", "%b | %b | %b | %b | 1111", v0xffc310_0, v0xffc560_0, v0xffc5e0_0, v0xffc6e0_0; - %movi 8, 11, 4; - %set/v v0xffc310_0, 8, 4; - %set/v v0xffc560_0, 0, 4; - %set/v v0xffc5e0_0, 1, 3; + %vpi_call 2 327 "$display", "%b | %b | %b | %b | 1111", v0x295fe90_0, v0x2960190_0, v0x2960210_0, v0x29603c0_0; + %movi 8, 11, 32; + %set/v v0x295fe90_0, 8, 32; + %set/v v0x2960190_0, 0, 32; + %set/v v0x2960210_0, 1, 3; %delay 1000000, 0; - %vpi_call 2 322 "$display", "%b | %b | %b | %b | 1011", v0xffc310_0, v0xffc560_0, v0xffc5e0_0, v0xffc6e0_0; - %vpi_call 2 324 "$display", " A | B |Command | Out |ExpectedOut-NOR"; - %movi 8, 10, 4; - %set/v v0xffc310_0, 8, 4; - %movi 8, 5, 4; - %set/v v0xffc560_0, 8, 4; + %vpi_call 2 331 "$display", "%b | %b | %b | %b | 1011", v0x295fe90_0, v0x2960190_0, v0x2960210_0, v0x29603c0_0; + %vpi_call 2 333 "$display", " A | B |Command | Out |ExpectedOut-NOR"; + %movi 8, 10, 32; + %set/v v0x295fe90_0, 8, 32; + %movi 8, 5, 32; + %set/v v0x2960190_0, 8, 32; %movi 8, 6, 3; - %set/v v0xffc5e0_0, 8, 3; + %set/v v0x2960210_0, 8, 3; %delay 1000000, 0; - %vpi_call 2 328 "$display", "%b | %b | %b | %b | 0000", v0xffc310_0, v0xffc560_0, v0xffc5e0_0, v0xffc6e0_0; - %set/v v0xffc310_0, 1, 4; - %movi 8, 5, 4; - %set/v v0xffc560_0, 8, 4; + %vpi_call 2 337 "$display", "%b | %b | %b | %b | 0000", v0x295fe90_0, v0x2960190_0, v0x2960210_0, v0x29603c0_0; + %movi 8, 15, 32; + %set/v v0x295fe90_0, 8, 32; + %movi 8, 5, 32; + %set/v v0x2960190_0, 8, 32; %movi 8, 6, 3; - %set/v v0xffc5e0_0, 8, 3; + %set/v v0x2960210_0, 8, 3; %delay 1000000, 0; - %vpi_call 2 332 "$display", "%b | %b | %b | %b | 0000", v0xffc310_0, v0xffc560_0, v0xffc5e0_0, v0xffc6e0_0; - %movi 8, 11, 4; - %set/v v0xffc310_0, 8, 4; - %set/v v0xffc560_0, 0, 4; + %vpi_call 2 341 "$display", "%b | %b | %b | %b | 0000", v0x295fe90_0, v0x2960190_0, v0x2960210_0, v0x29603c0_0; + %movi 8, 11, 32; + %set/v v0x295fe90_0, 8, 32; + %set/v v0x2960190_0, 0, 32; %movi 8, 6, 3; - %set/v v0xffc5e0_0, 8, 3; + %set/v v0x2960210_0, 8, 3; %delay 1000000, 0; - %vpi_call 2 336 "$display", "%b | %b | %b | %b | 0100", v0xffc310_0, v0xffc560_0, v0xffc5e0_0, v0xffc6e0_0; - %vpi_call 2 338 "$display", " A | B |Command | Out |ExpectedOut-XOR"; - %movi 8, 10, 4; - %set/v v0xffc310_0, 8, 4; - %movi 8, 5, 4; - %set/v v0xffc560_0, 8, 4; + %vpi_call 2 345 "$display", "%b | %b | %b | %b | 0100", v0x295fe90_0, v0x2960190_0, v0x2960210_0, v0x29603c0_0; + %vpi_call 2 347 "$display", " A | B |Command | Out |ExpectedOut-XOR"; + %movi 8, 10, 32; + %set/v v0x295fe90_0, 8, 32; + %movi 8, 5, 32; + %set/v v0x2960190_0, 8, 32; %movi 8, 2, 3; - %set/v v0xffc5e0_0, 8, 3; + %set/v v0x2960210_0, 8, 3; %delay 1000000, 0; - %vpi_call 2 342 "$display", "%b | %b | %b | %b | 1111", v0xffc310_0, v0xffc560_0, v0xffc5e0_0, v0xffc6e0_0; - %set/v v0xffc310_0, 1, 4; - %movi 8, 5, 4; - %set/v v0xffc560_0, 8, 4; + %vpi_call 2 351 "$display", "%b | %b | %b | %b | 1111", v0x295fe90_0, v0x2960190_0, v0x2960210_0, v0x29603c0_0; + %movi 8, 15, 32; + %set/v v0x295fe90_0, 8, 32; + %movi 8, 5, 32; + %set/v v0x2960190_0, 8, 32; %movi 8, 2, 3; - %set/v v0xffc5e0_0, 8, 3; + %set/v v0x2960210_0, 8, 3; %delay 1000000, 0; - %vpi_call 2 346 "$display", "%b | %b | %b | %b | 1010", v0xffc310_0, v0xffc560_0, v0xffc5e0_0, v0xffc6e0_0; - %movi 8, 11, 4; - %set/v v0xffc310_0, 8, 4; - %set/v v0xffc560_0, 0, 4; + %vpi_call 2 355 "$display", "%b | %b | %b | %b | 1010", v0x295fe90_0, v0x2960190_0, v0x2960210_0, v0x29603c0_0; + %movi 8, 11, 32; + %set/v v0x295fe90_0, 8, 32; + %set/v v0x2960190_0, 0, 32; %movi 8, 2, 3; - %set/v v0xffc5e0_0, 8, 3; + %set/v v0x2960210_0, 8, 3; %delay 1000000, 0; - %vpi_call 2 350 "$display", "%b | %b | %b | %b | 1011", v0xffc310_0, v0xffc560_0, v0xffc5e0_0, v0xffc6e0_0; - %vpi_call 2 352 "$display", "Test 4 Bit ALU Functionality"; - %vpi_call 2 354 "$display", " A | B |Command | Out |ExpectedOut | COut | OF |SLT|Zero"; - %set/v v0xffc310_0, 1, 4; - %set/v v0xffc560_0, 1, 4; + %vpi_call 2 359 "$display", "%b | %b | %b | %b | 1011", v0x295fe90_0, v0x2960190_0, v0x2960210_0, v0x29603c0_0; + %vpi_call 2 361 "$display", "Test 4 Bit ALU Functionality"; + %vpi_call 2 363 "$display", " A | B |Command | Out |ExpectedOut | COut | OF |SLT|Zero"; + %movi 8, 15, 32; + %set/v v0x295fe90_0, 8, 32; + %movi 8, 15, 32; + %set/v v0x2960190_0, 8, 32; %movi 8, 4, 3; - %set/v v0xffc5e0_0, 8, 3; + %set/v v0x2960210_0, 8, 3; %delay 1000000, 0; - %vpi_call 2 359 "$display", "%b | %b | %b - AND | %b | 1111 | %b | %b | %b | %b", v0xffc310_0, v0xffc560_0, v0xffc5e0_0, v0xffc660_0, v0xffcb10_0, v0xffcc10_0, v0xffc7e0_0, v0xffc430_0; - %set/v v0xffc310_0, 1, 4; - %set/v v0xffc560_0, 0, 4; + %vpi_call 2 368 "$display", "%b | %b | %b - AND | %b | 1111 | %b | %b | %b | %b", v0x295fe90_0, v0x2960190_0, v0x2960210_0, v0x2960290_0, v0x2960870_0, v0x2960980_0, v0x29604c0_0, v0x295ffb0_0; + %movi 8, 15, 32; + %set/v v0x295fe90_0, 8, 32; + %set/v v0x2960190_0, 0, 32; %movi 8, 5, 3; - %set/v v0xffc5e0_0, 8, 3; + %set/v v0x2960210_0, 8, 3; %delay 1000000, 0; - %vpi_call 2 364 "$display", "%b | %b | %b - NAND | %b | 1111 | %b | %b | %b | %b", v0xffc310_0, v0xffc560_0, v0xffc5e0_0, v0xffc660_0, v0xffcb10_0, v0xffcc10_0, v0xffc7e0_0, v0xffc430_0; - %set/v v0xffc310_0, 1, 4; - %movi 8, 5, 4; - %set/v v0xffc560_0, 8, 4; - %set/v v0xffc5e0_0, 1, 3; + %vpi_call 2 373 "$display", "%b | %b | %b - NAND | %b | 1111 | %b | %b | %b | %b", v0x295fe90_0, v0x2960190_0, v0x2960210_0, v0x2960290_0, v0x2960870_0, v0x2960980_0, v0x29604c0_0, v0x295ffb0_0; + %movi 8, 15, 32; + %set/v v0x295fe90_0, 8, 32; + %movi 8, 5, 32; + %set/v v0x2960190_0, 8, 32; + %set/v v0x2960210_0, 1, 3; %delay 1000000, 0; - %vpi_call 2 369 "$display", "%b | %b | %b - OR | %b | 1111 | %b | %b | %b | %b", v0xffc310_0, v0xffc560_0, v0xffc5e0_0, v0xffc660_0, v0xffcb10_0, v0xffcc10_0, v0xffc7e0_0, v0xffc430_0; - %movi 8, 11, 4; - %set/v v0xffc310_0, 8, 4; - %set/v v0xffc560_0, 0, 4; + %vpi_call 2 378 "$display", "%b | %b | %b - OR | %b | 1111 | %b | %b | %b | %b", v0x295fe90_0, v0x2960190_0, v0x2960210_0, v0x2960290_0, v0x2960870_0, v0x2960980_0, v0x29604c0_0, v0x295ffb0_0; + %movi 8, 11, 32; + %set/v v0x295fe90_0, 8, 32; + %set/v v0x2960190_0, 0, 32; %movi 8, 6, 3; - %set/v v0xffc5e0_0, 8, 3; + %set/v v0x2960210_0, 8, 3; %delay 1000000, 0; - %vpi_call 2 374 "$display", "%b | %b | %b - NOR | %b | 0100 | %b | %b | %b | %b", v0xffc310_0, v0xffc560_0, v0xffc5e0_0, v0xffc660_0, v0xffcb10_0, v0xffcc10_0, v0xffc7e0_0, v0xffc430_0; - %movi 8, 11, 4; - %set/v v0xffc310_0, 8, 4; - %set/v v0xffc560_0, 0, 4; + %vpi_call 2 383 "$display", "%b | %b | %b - NOR | %b | 0100 | %b | %b | %b | %b", v0x295fe90_0, v0x2960190_0, v0x2960210_0, v0x2960290_0, v0x2960870_0, v0x2960980_0, v0x29604c0_0, v0x295ffb0_0; + %movi 8, 11, 32; + %set/v v0x295fe90_0, 8, 32; + %set/v v0x2960190_0, 0, 32; %movi 8, 2, 3; - %set/v v0xffc5e0_0, 8, 3; + %set/v v0x2960210_0, 8, 3; %delay 1000000, 0; - %vpi_call 2 379 "$display", "%b | %b | %b - XOR | %b | 1011 | %b | %b | %b | %b", v0xffc310_0, v0xffc560_0, v0xffc5e0_0, v0xffc660_0, v0xffcb10_0, v0xffcc10_0, v0xffc7e0_0, v0xffc430_0; - %movi 8, 2, 4; - %set/v v0xffc310_0, 8, 4; - %movi 8, 4, 4; - %set/v v0xffc560_0, 8, 4; - %set/v v0xffc5e0_0, 0, 3; + %vpi_call 2 388 "$display", "%b | %b | %b - XOR | %b | 1011 | %b | %b | %b | %b", v0x295fe90_0, v0x2960190_0, v0x2960210_0, v0x2960290_0, v0x2960870_0, v0x2960980_0, v0x29604c0_0, v0x295ffb0_0; + %movi 8, 2, 32; + %set/v v0x295fe90_0, 8, 32; + %movi 8, 4, 32; + %set/v v0x2960190_0, 8, 32; + %set/v v0x2960210_0, 0, 3; %delay 1000000, 0; - %vpi_call 2 384 "$display", "%b | %b | %b - ADD | %b | 0110 | %b | %b | %b | %b", v0xffc310_0, v0xffc560_0, v0xffc5e0_0, v0xffc660_0, v0xffcb10_0, v0xffcc10_0, v0xffc7e0_0, v0xffc430_0; - %movi 8, 11, 4; - %set/v v0xffc310_0, 8, 4; - %movi 8, 12, 4; - %set/v v0xffc560_0, 8, 4; - %set/v v0xffc5e0_0, 0, 3; + %vpi_call 2 393 "$display", "%b | %b | %b - ADD | %b | 0110 | %b | %b | %b | %b", v0x295fe90_0, v0x2960190_0, v0x2960210_0, v0x2960290_0, v0x2960870_0, v0x2960980_0, v0x29604c0_0, v0x295ffb0_0; + %movi 8, 11, 32; + %set/v v0x295fe90_0, 8, 32; + %movi 8, 12, 32; + %set/v v0x2960190_0, 8, 32; + %set/v v0x2960210_0, 0, 3; %delay 1000000, 0; - %vpi_call 2 388 "$display", "%b | %b | %b - ADD | %b | XXXX | %b | %b | %b | %b", v0xffc310_0, v0xffc560_0, v0xffc5e0_0, v0xffc660_0, v0xffcb10_0, v0xffcc10_0, v0xffc7e0_0, v0xffc430_0; - %movi 8, 2, 4; - %set/v v0xffc310_0, 8, 4; - %movi 8, 4, 4; - %set/v v0xffc560_0, 8, 4; + %vpi_call 2 397 "$display", "%b | %b | %b - ADD | %b | XXXX | %b | %b | %b | %b", v0x295fe90_0, v0x2960190_0, v0x2960210_0, v0x2960290_0, v0x2960870_0, v0x2960980_0, v0x29604c0_0, v0x295ffb0_0; + %movi 8, 2, 32; + %set/v v0x295fe90_0, 8, 32; + %movi 8, 4, 32; + %set/v v0x2960190_0, 8, 32; %movi 8, 1, 3; - %set/v v0xffc5e0_0, 8, 3; + %set/v v0x2960210_0, 8, 3; %delay 1000000, 0; - %vpi_call 2 393 "$display", "%b | %b | %b - SUB | %b | 1110 | %b | %b | %b | %b", v0xffc310_0, v0xffc560_0, v0xffc5e0_0, v0xffc660_0, v0xffcb10_0, v0xffcc10_0, v0xffc7e0_0, v0xffc430_0; - %movi 8, 9, 4; - %set/v v0xffc310_0, 8, 4; - %movi 8, 3, 4; - %set/v v0xffc560_0, 8, 4; + %vpi_call 2 402 "$display", "%b | %b | %b - SUB | %b | 1110 | %b | %b | %b | %b", v0x295fe90_0, v0x2960190_0, v0x2960210_0, v0x2960290_0, v0x2960870_0, v0x2960980_0, v0x29604c0_0, v0x295ffb0_0; + %movi 8, 9, 32; + %set/v v0x295fe90_0, 8, 32; + %movi 8, 3, 32; + %set/v v0x2960190_0, 8, 32; %movi 8, 1, 3; - %set/v v0xffc5e0_0, 8, 3; + %set/v v0x2960210_0, 8, 3; %delay 1000000, 0; - %vpi_call 2 397 "$display", "%b | %b | %b - SUB | %b | XXXX | %b | %b | %b | %b", v0xffc310_0, v0xffc560_0, v0xffc5e0_0, v0xffc660_0, v0xffcb10_0, v0xffcc10_0, v0xffc7e0_0, v0xffc430_0; - %movi 8, 4, 4; - %set/v v0xffc310_0, 8, 4; - %movi 8, 2, 4; - %set/v v0xffc560_0, 8, 4; + %vpi_call 2 406 "$display", "%b | %b | %b - SUB | %b | XXXX | %b | %b | %b | %b", v0x295fe90_0, v0x2960190_0, v0x2960210_0, v0x2960290_0, v0x2960870_0, v0x2960980_0, v0x29604c0_0, v0x295ffb0_0; + %movi 8, 4, 32; + %set/v v0x295fe90_0, 8, 32; + %movi 8, 2, 32; + %set/v v0x2960190_0, 8, 32; %movi 8, 3, 3; - %set/v v0xffc5e0_0, 8, 3; + %set/v v0x2960210_0, 8, 3; %delay 1000000, 0; - %vpi_call 2 403 "$display", "%b | %b | %b - SLT | %b | 0010 | %b | %b | %b | %b", v0xffc310_0, v0xffc560_0, v0xffc5e0_0, v0xffc660_0, v0xffcb10_0, v0xffcc10_0, v0xffc8f0_0, v0xffc430_0; - %movi 8, 9, 4; - %set/v v0xffc310_0, 8, 4; - %movi 8, 5, 4; - %set/v v0xffc560_0, 8, 4; + %vpi_call 2 412 "$display", "%b | %b | %b - SLT | %b | 0010 | %b | %b | %b | %b", v0x295fe90_0, v0x2960190_0, v0x2960210_0, v0x2960290_0, v0x2960870_0, v0x2960980_0, v0x2960640_0, v0x295ffb0_0; + %movi 8, 9, 32; + %set/v v0x295fe90_0, 8, 32; + %movi 8, 5, 32; + %set/v v0x2960190_0, 8, 32; %movi 8, 3, 3; - %set/v v0xffc5e0_0, 8, 3; + %set/v v0x2960210_0, 8, 3; %delay 1000000, 0; - %vpi_call 2 407 "$display", "%b | %b | %b - SLT | %b | XXXX | %b | %b | %b | %b", v0xffc310_0, v0xffc560_0, v0xffc5e0_0, v0xffc660_0, v0xffcb10_0, v0xffcc10_0, v0xffc8f0_0, v0xffc430_0; - %movi 8, 2, 4; - %set/v v0xffc310_0, 8, 4; - %movi 8, 4, 4; - %set/v v0xffc560_0, 8, 4; + %vpi_call 2 416 "$display", "%b | %b | %b - SLT | %b | XXXX | %b | %b | %b | %b", v0x295fe90_0, v0x2960190_0, v0x2960210_0, v0x2960290_0, v0x2960870_0, v0x2960980_0, v0x2960640_0, v0x295ffb0_0; + %movi 8, 2, 32; + %set/v v0x295fe90_0, 8, 32; + %movi 8, 4, 32; + %set/v v0x2960190_0, 8, 32; %movi 8, 3, 3; - %set/v v0xffc5e0_0, 8, 3; + %set/v v0x2960210_0, 8, 3; %delay 1000000, 0; - %vpi_call 2 411 "$display", "%b | %b | %b - SLT | %b | XXXX | %b | %b | %b | %b", v0xffc310_0, v0xffc560_0, v0xffc5e0_0, v0xffc660_0, v0xffcb10_0, v0xffcc10_0, v0xffc8f0_0, v0xffc430_0; - %set/v v0xffc310_0, 0, 4; - %set/v v0xffc560_0, 1, 4; + %vpi_call 2 420 "$display", "%b | %b | %b - SLT | %b | XXXX | %b | %b | %b | %b", v0x295fe90_0, v0x2960190_0, v0x2960210_0, v0x2960290_0, v0x2960870_0, v0x2960980_0, v0x2960640_0, v0x295ffb0_0; + %set/v v0x295fe90_0, 0, 32; + %movi 8, 15, 32; + %set/v v0x2960190_0, 8, 32; %movi 8, 4, 3; - %set/v v0xffc5e0_0, 8, 3; + %set/v v0x2960210_0, 8, 3; %delay 1000000, 0; - %vpi_call 2 419 "$display", "%b | %b | %b - AND | %b | 0000 | %b | %b | %b | %b", v0xffc310_0, v0xffc560_0, v0xffc5e0_0, v0xffc660_0, v0xffcb10_0, v0xffcc10_0, v0xffc7e0_0, v0xffc430_0; - %set/v v0xffc310_0, 1, 4; - %set/v v0xffc560_0, 1, 4; + %vpi_call 2 428 "$display", "%b | %b | %b - AND | %b | 0000 | %b | %b | %b | %b", v0x295fe90_0, v0x2960190_0, v0x2960210_0, v0x2960290_0, v0x2960870_0, v0x2960980_0, v0x29604c0_0, v0x295ffb0_0; + %movi 8, 15, 32; + %set/v v0x295fe90_0, 8, 32; + %movi 8, 15, 32; + %set/v v0x2960190_0, 8, 32; %movi 8, 5, 3; - %set/v v0xffc5e0_0, 8, 3; + %set/v v0x2960210_0, 8, 3; %delay 1000000, 0; - %vpi_call 2 422 "$display", "%b | %b | %b - NAND | %b | 0000 | %b | %b | %b | %b", v0xffc310_0, v0xffc560_0, v0xffc5e0_0, v0xffc660_0, v0xffcb10_0, v0xffcc10_0, v0xffc7e0_0, v0xffc430_0; - %set/v v0xffc310_0, 0, 4; - %set/v v0xffc560_0, 0, 4; - %set/v v0xffc5e0_0, 1, 3; + %vpi_call 2 431 "$display", "%b | %b | %b - NAND | %b | 0000 | %b | %b | %b | %b", v0x295fe90_0, v0x2960190_0, v0x2960210_0, v0x2960290_0, v0x2960870_0, v0x2960980_0, v0x29604c0_0, v0x295ffb0_0; + %set/v v0x295fe90_0, 0, 32; + %set/v v0x2960190_0, 0, 32; + %set/v v0x2960210_0, 1, 3; %delay 1000000, 0; - %vpi_call 2 425 "$display", "%b | %b | %b - OR | %b | 0000 | %b | %b | %b | %b", v0xffc310_0, v0xffc560_0, v0xffc5e0_0, v0xffc660_0, v0xffcb10_0, v0xffcc10_0, v0xffc7e0_0, v0xffc430_0; - %movi 8, 11, 4; - %set/v v0xffc310_0, 8, 4; - %movi 8, 4, 4; - %set/v v0xffc560_0, 8, 4; + %vpi_call 2 434 "$display", "%b | %b | %b - OR | %b | 0000 | %b | %b | %b | %b", v0x295fe90_0, v0x2960190_0, v0x2960210_0, v0x2960290_0, v0x2960870_0, v0x2960980_0, v0x29604c0_0, v0x295ffb0_0; + %movi 8, 11, 32; + %set/v v0x295fe90_0, 8, 32; + %movi 8, 4, 32; + %set/v v0x2960190_0, 8, 32; %movi 8, 6, 3; - %set/v v0xffc5e0_0, 8, 3; + %set/v v0x2960210_0, 8, 3; %delay 1000000, 0; - %vpi_call 2 427 "$display", "%b | %b | %b - NOR | %b | 0000 | %b | %b | %b | %b", v0xffc310_0, v0xffc560_0, v0xffc5e0_0, v0xffc660_0, v0xffcb10_0, v0xffcc10_0, v0xffc7e0_0, v0xffc430_0; - %movi 8, 11, 4; - %set/v v0xffc310_0, 8, 4; - %movi 8, 11, 4; - %set/v v0xffc560_0, 8, 4; + %vpi_call 2 436 "$display", "%b | %b | %b - NOR | %b | 0000 | %b | %b | %b | %b", v0x295fe90_0, v0x2960190_0, v0x2960210_0, v0x2960290_0, v0x2960870_0, v0x2960980_0, v0x29604c0_0, v0x295ffb0_0; + %movi 8, 11, 32; + %set/v v0x295fe90_0, 8, 32; + %movi 8, 11, 32; + %set/v v0x2960190_0, 8, 32; %movi 8, 2, 3; - %set/v v0xffc5e0_0, 8, 3; + %set/v v0x2960210_0, 8, 3; %delay 1000000, 0; - %vpi_call 2 430 "$display", "%b | %b | %b - XOR | %b | 0000 | %b | %b | %b | %b", v0xffc310_0, v0xffc560_0, v0xffc5e0_0, v0xffc660_0, v0xffcb10_0, v0xffcc10_0, v0xffc7e0_0, v0xffc430_0; - %movi 8, 2, 4; - %set/v v0xffc310_0, 8, 4; - %movi 8, 14, 4; - %set/v v0xffc560_0, 8, 4; - %set/v v0xffc5e0_0, 0, 3; + %vpi_call 2 439 "$display", "%b | %b | %b - XOR | %b | 0000 | %b | %b | %b | %b", v0x295fe90_0, v0x2960190_0, v0x2960210_0, v0x2960290_0, v0x2960870_0, v0x2960980_0, v0x29604c0_0, v0x295ffb0_0; + %movi 8, 2, 32; + %set/v v0x295fe90_0, 8, 32; + %movi 8, 14, 32; + %set/v v0x2960190_0, 8, 32; + %set/v v0x2960210_0, 0, 3; %delay 1000000, 0; - %vpi_call 2 433 "$display", "%b | %b | %b - ADD | %b | 0000 | %b | %b | %b | %b", v0xffc310_0, v0xffc560_0, v0xffc5e0_0, v0xffc660_0, v0xffcb10_0, v0xffcc10_0, v0xffc7e0_0, v0xffc430_0; - %movi 8, 2, 4; - %set/v v0xffc310_0, 8, 4; - %movi 8, 2, 4; - %set/v v0xffc560_0, 8, 4; + %vpi_call 2 442 "$display", "%b | %b | %b - ADD | %b | 0000 | %b | %b | %b | %b", v0x295fe90_0, v0x2960190_0, v0x2960210_0, v0x2960290_0, v0x2960870_0, v0x2960980_0, v0x29604c0_0, v0x295ffb0_0; + %movi 8, 2, 32; + %set/v v0x295fe90_0, 8, 32; + %movi 8, 2, 32; + %set/v v0x2960190_0, 8, 32; %movi 8, 1, 3; - %set/v v0xffc5e0_0, 8, 3; + %set/v v0x2960210_0, 8, 3; + %delay 1000000, 0; + %vpi_call 2 445 "$display", "%b | %b | %b - SUB | %b | 0000 | %b | %b | %b | %b", v0x295fe90_0, v0x2960190_0, v0x2960210_0, v0x2960290_0, v0x2960870_0, v0x2960980_0, v0x29604c0_0, v0x295ffb0_0; + %set/v v0x295fe90_0, 0, 32; + %set/v v0x2960190_0, 0, 32; + %movi 8, 3, 3; + %set/v v0x2960210_0, 8, 3; %delay 1000000, 0; - %vpi_call 2 436 "$display", "%b | %b | %b - SUB | %b | 0000 | %b | %b | %b | %b", v0xffc310_0, v0xffc560_0, v0xffc5e0_0, v0xffc660_0, v0xffcb10_0, v0xffcc10_0, v0xffc7e0_0, v0xffc430_0; - %set/v v0xffc310_0, 0, 4; - %set/v v0xffc560_0, 0, 4; + %vpi_call 2 449 "$display", "%b | %b | %b - SLT | %b | 0000 | %b | %b | %b | %b", v0x295fe90_0, v0x2960190_0, v0x2960210_0, v0x2960290_0, v0x2960870_0, v0x2960980_0, v0x29604c0_0, v0x295ffb0_0; + %vpi_call 2 455 "$display", " A \011\011\011\011 | B \011\011\011 \011 |Command \011 | Out \011 \011\011\011\011 |ExpectedOut \011| COut | OF |Zero"; + %set/v v0x295fe90_0, 1, 32; + %movi 8, 4294967294, 32; + %set/v v0x2960190_0, 8, 32; %movi 8, 3, 3; - %set/v v0xffc5e0_0, 8, 3; + %set/v v0x2960210_0, 8, 3; %delay 1000000, 0; - %vpi_call 2 440 "$display", "%b | %b | %b - SLT | %b | 0000 | %b | %b | %b | %b", v0xffc310_0, v0xffc560_0, v0xffc5e0_0, v0xffc660_0, v0xffcb10_0, v0xffcc10_0, v0xffc7e0_0, v0xffc430_0; + %vpi_call 2 457 "$display", "%b | %b | %b - SLT | %b | 00000000000000000000000000000001 | %b | %b | %b", v0x295fe90_0, v0x2960190_0, v0x2960210_0, v0x2960310_0, v0x2960740_0, v0x29608f0_0, v0x2960030_0; %end; .thread T_0; # The file index is used to find the file name in the following table. diff --git a/testing.t.v b/testing.t.v index 88a9987..83c4676 100644 --- a/testing.t.v +++ b/testing.t.v @@ -124,7 +124,7 @@ endmodule */ module test32Adder(); -parameter size = 4; +parameter size = 32; wire [size-1:0] OneBitFinalOut; wire [size-1:0] OrNorXorOut; wire [size-1:0] AndNandOut; @@ -144,6 +144,13 @@ wire Cmd0Start [size-1:0]; wire Cmd1Start [size-1:0]; wire [size-1:0] CarryoutWire; +// creating new variables for ALU to make sure nothing gets mixed up +wire [size-1:0] OneBitFinalOut2; +wire AllZeros2; +wire carryout2; +wire overflow2; + + AddSubSLT32 trial(AddSubSLTSum, carryout, overflow, subtract, A, B, Command, carryin); SLT32 test2(SLTSum, carryout, overflow, SLTflag1, subtract, A, B, Command, carryin); @@ -154,6 +161,8 @@ OrNorXor32 trial2(OrNorXorOut, A, B, Command); Bitslice32 superalu(OneBitFinalOut, AddSubSLTSum, SLTSum, carryout, overflow, SLTflag, OrNorXorOut, AndNandOut, subtract, ZeroFlag, AllZeros, A, B, Command, carryin); +ALU testALU(OneBitFinalOut2, carryout2, AllZeros2, overflow2, A, B, Command); + initial begin $dumpfile("FullALU.vcd"); $dumpvars(); @@ -439,6 +448,15 @@ A = 4'b0010; B = 4'b0010; Command =3'b001; #1000 A = 4'b0000; B = 4'b0000; Command =3'b011; #1000 $display("%b | %b | %b - SLT | %b | 0000 | %b | %b | %b | %b", A, B, Command, OneBitFinalOut, carryout, overflow, SLTflag, AllZeros); + + + +// test the ALU module (should be same as BitSlice32) +$display(" A | B |Command | Out |ExpectedOut | COut | OF |Zero"); +A = 32'b11111111111111111111111111111111; B = 32'b11111111111111111111111111111110; Command =3'b011; #1000 + $display("%b | %b | %b - SLT | %b | 00000000000000000000000000000001 | %b | %b | %b", A, B, Command, OneBitFinalOut2, carryout2, overflow2, AllZeros2); + + end endmodule From 79aa7c2f9f246554bda89b9f5df7ca7655139cf2 Mon Sep 17 00:00:00 2001 From: mjakus Date: Wed, 11 Oct 2017 23:26:06 -0400 Subject: [PATCH 27/28] Cleaned &Done --- alu.v | 51 +++++---------------------------------------------- 1 file changed, 5 insertions(+), 46 deletions(-) diff --git a/alu.v b/alu.v index 2eb50df..3ec7989 100644 --- a/alu.v +++ b/alu.v @@ -5,6 +5,8 @@ `define NOR nor #10 // base is 10 `define XOR xor #40 // and with or is 40 + +// This module is the same as the BitSlice32 module at the very end. We wrote BitSlice32 before ALU, and we only created ALU at the end as the cleanest version of our work. module ALU ( output[31:0] result, // OneBitFinalOut @@ -15,29 +17,11 @@ input[31:0] operandA, // A input[31:0] operandB, // B input[2:0] command //Command ); - // Your code here -/* -output [size-1:0] OneBitFinalOut, -output [size-1:0]AddSubSLTSum, -output [size-1:0]SLTSum, -output carryout, -output overflow, -output SLTflag, -output [size-1:0] OrNorXorOut, -output [size-1:0] AndNandOut, -output [size-1:0] subtract, -output [size-1:0] ZeroFlag, -output AllZeros, -input [size-1:0] A, -input [size-1:0] B, -input[2:0] Command, -input [size-1:0]carryin // don't think this does anything but don't want to break it! -); -*/ + parameter size = 32; wire [size-1:0] Cmd0Start; - wire [size-1:0] Cmd1Start; - wire [size-1:0] CarryoutWire; + wire [size-1:0] Cmd1Start; + wire [size-1:0] CarryoutWire; wire yeszero; wire [size-1:0] NewVal; wire [size-1:0] SLTSum; @@ -81,31 +65,6 @@ endmodule - - - - - - - - - - - - - - - - - - - - - - - - - module TwoInMux // this module is a two input mux that takes in two inputs (in0 and in1) and uses switch S to pick the value for outfinal ( output outfinal, From 4d4baa0deb26cf206d4f804adb8f3065313394c2 Mon Sep 17 00:00:00 2001 From: Logan Sweet Date: Thu, 12 Oct 2017 09:42:03 -0400 Subject: [PATCH 28/28] Lab Writeup Added --- CompArch_Lab1_Jakus_Sweet.pdf | Bin 0 -> 275167 bytes 1 file changed, 0 insertions(+), 0 deletions(-) create mode 100644 CompArch_Lab1_Jakus_Sweet.pdf diff --git a/CompArch_Lab1_Jakus_Sweet.pdf b/CompArch_Lab1_Jakus_Sweet.pdf new file mode 100644 index 0000000000000000000000000000000000000000..a4e9c51be36debfae8b1b5c777fb4144e992c62c GIT binary patch literal 275167 zcmeFYWo#u)v*&4MX7(|)nYqo(%*@Qp%*@Pex0#{M%x*I?Gc#>J^S*cP-MOpPeA@jo zC6!8<8Ol@nPsJ~yjv~qAg+*x@=~!XNdY%ivU|2Z;3;;VrOBil$0KK$@t%-r7g{O%z zfbnk&z{JkV$i@z!7YAqo7@1kw089)F0386m9Dt1(KraH|U|?YRYbXog0MIM{wPs;u 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zQlrRFOPL3QEjv%aPau5V*E%uE`S9V-1n3QNy$MDv=n}gD{mj?@bG82EhyQD}{-<)4 zh2_7=;{UFm{CBaVu>lB}I5P2gU+*1}WJA!^{+3~xSJ>uf~f<25>Mmw*KU-e-4u|^>nv)GI9QgRXKZ;|J|UXikJq2_@`df$k5Kt^wY44 zg{3p#^W|V-_UVBRpl0gi{0Rxb!T@9ivT-r9v(Ym%u+sw>SeY1roB$oFzc^$q-An<0 z(dtkGtQ`zpESyaZ0dD{KO?C!m29{4yica<>uEu|T{L}WoYD1|4t7Z=fA~I<@59bj2cRx0bu->+L-B6#42uS zFp}5G@UYMdcn89NPwSUF{%(|$eH$MYaF#{wYMga3gxWxT7@FeLjf@CYy zabrr>y);~XZdKs%mEs1;bOy=t22RjvydcfiuxXPbX=A&HDXP$!w|Js(fw~N}FgAx2 zwHX?<={^R`sIq#Hi3X`GO+jNWwUV%DZ;-N3L1X3yH-MkwwYcK7U9vWS`ZI_$0+1W{ z7LxF)22eV%2Y6$sG#3L95EmmNg1__Q?DDyYZT~e>fd9W5oU@CelZ(gaj|q+$$PPzN JE~X$3_a9o~UI+jH literal 0 HcmV?d00001

P nS $end +$var wire 1 ?P out0 $end +$var wire 1 @P out1 $end +$var wire 1 ;P outfinal $end +$upscope $end +$scope module mux1 $end +$var wire 1 AP S $end +$var wire 1 ;P in0 $end +$var wire 1 6P in1 $end +$var wire 1 BP nS $end +$var wire 1 CP out0 $end +$var wire 1 DP out1 $end +$var wire 1 :P outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin orbits[11] $end +$scope module attempt $end +$var wire 1 EP A $end +$var wire 1 FP AnandB $end +$var wire 1 GP AnorB $end +$var wire 1 HP AorB $end +$var wire 1 IP AxorB $end +$var wire 1 JP B $end +$var wire 3 KP Command [2:0] $end +$var wire 1 LP OrNorXorOut $end +$var wire 1 MP XorNor $end +$var wire 1 NP nXor $end +$scope module mux0 $end +$var wire 1 OP S $end +$var wire 1 IP in0 $end +$var wire 1 GP in1 $end +$var wire 1 PP nS $end +$var wire 1 QP out0 $end +$var wire 1 RP out1 $end +$var wire 1 MP outfinal $end +$upscope $end +$scope module mux1 $end +$var wire 1 SP S $end +$var wire 1 MP in0 $end +$var wire 1 HP in1 $end +$var wire 1 TP nS $end +$var wire 1 UP out0 $end +$var wire 1 VP out1 $end +$var wire 1 LP outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin orbits[12] $end +$scope module attempt $end +$var wire 1 WP A $end +$var wire 1 XP AnandB $end +$var wire 1 YP AnorB $end +$var wire 1 ZP AorB $end +$var wire 1 [P AxorB $end +$var wire 1 \P B $end +$var wire 3 ]P Command [2:0] $end +$var wire 1 ^P OrNorXorOut $end +$var wire 1 _P XorNor $end +$var wire 1 `P nXor $end +$scope module mux0 $end +$var wire 1 aP S $end +$var wire 1 [P in0 $end +$var wire 1 YP in1 $end +$var wire 1 bP nS $end +$var wire 1 cP out0 $end +$var wire 1 dP out1 $end +$var wire 1 _P outfinal $end +$upscope $end +$scope module mux1 $end +$var wire 1 eP S $end +$var wire 1 _P in0 $end +$var wire 1 ZP in1 $end +$var wire 1 fP nS $end +$var wire 1 gP out0 $end +$var wire 1 hP out1 $end +$var wire 1 ^P outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin orbits[13] $end +$scope module attempt $end +$var wire 1 iP A $end +$var wire 1 jP AnandB $end +$var wire 1 kP AnorB $end +$var wire 1 lP AorB $end +$var wire 1 mP AxorB $end +$var wire 1 nP B $end +$var wire 3 oP Command [2:0] $end +$var wire 1 pP OrNorXorOut $end +$var wire 1 qP XorNor $end +$var wire 1 rP nXor $end +$scope module mux0 $end +$var wire 1 sP S $end +$var wire 1 mP in0 $end +$var wire 1 kP in1 $end +$var wire 1 tP nS $end +$var wire 1 uP out0 $end +$var wire 1 vP out1 $end +$var wire 1 qP outfinal $end +$upscope $end +$scope module mux1 $end +$var wire 1 wP S $end +$var wire 1 qP in0 $end +$var wire 1 lP in1 $end +$var wire 1 xP nS $end +$var wire 1 yP out0 $end +$var wire 1 zP out1 $end +$var wire 1 pP outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin orbits[14] $end +$scope module attempt $end +$var wire 1 {P A $end +$var wire 1 |P AnandB $end +$var wire 1 }P AnorB $end +$var wire 1 ~P AorB $end +$var wire 1 !Q AxorB $end +$var wire 1 "Q B $end +$var wire 3 #Q Command [2:0] $end +$var wire 1 $Q OrNorXorOut $end +$var wire 1 %Q XorNor $end +$var wire 1 &Q nXor $end +$scope module mux0 $end +$var wire 1 'Q S $end +$var wire 1 !Q in0 $end +$var wire 1 }P in1 $end +$var wire 1 (Q nS $end +$var wire 1 )Q out0 $end +$var wire 1 *Q out1 $end +$var wire 1 %Q outfinal $end +$upscope $end +$scope module mux1 $end +$var wire 1 +Q S $end +$var wire 1 %Q in0 $end +$var wire 1 ~P in1 $end +$var wire 1 ,Q nS $end +$var wire 1 -Q out0 $end +$var wire 1 .Q out1 $end +$var wire 1 $Q outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin orbits[15] $end +$scope module attempt $end +$var wire 1 /Q A $end +$var wire 1 0Q AnandB $end +$var wire 1 1Q AnorB $end +$var wire 1 2Q AorB $end +$var wire 1 3Q AxorB $end +$var wire 1 4Q B $end +$var wire 3 5Q Command [2:0] $end +$var wire 1 6Q OrNorXorOut $end +$var wire 1 7Q XorNor $end +$var wire 1 8Q nXor $end +$scope module mux0 $end +$var wire 1 9Q S $end +$var wire 1 3Q in0 $end +$var wire 1 1Q in1 $end +$var wire 1 :Q nS $end +$var wire 1 ;Q out0 $end +$var wire 1 Q nS $end +$var wire 1 ?Q out0 $end +$var wire 1 @Q out1 $end +$var wire 1 6Q outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin orbits[16] $end +$scope module attempt $end +$var wire 1 AQ A $end +$var wire 1 BQ AnandB $end +$var wire 1 CQ AnorB $end +$var wire 1 DQ AorB $end +$var wire 1 EQ AxorB $end +$var wire 1 FQ B $end +$var wire 3 GQ Command [2:0] $end +$var wire 1 HQ OrNorXorOut $end +$var wire 1 IQ XorNor $end +$var wire 1 JQ nXor $end +$scope module mux0 $end +$var wire 1 KQ S $end +$var wire 1 EQ in0 $end +$var wire 1 CQ in1 $end +$var wire 1 LQ nS $end +$var wire 1 MQ out0 $end +$var wire 1 NQ out1 $end +$var wire 1 IQ outfinal $end +$upscope $end +$scope module mux1 $end +$var wire 1 OQ S $end +$var wire 1 IQ in0 $end +$var wire 1 DQ in1 $end +$var wire 1 PQ nS $end +$var wire 1 QQ out0 $end +$var wire 1 RQ out1 $end +$var wire 1 HQ outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin orbits[17] $end +$scope module attempt $end +$var wire 1 SQ A $end +$var wire 1 TQ AnandB $end +$var wire 1 UQ AnorB $end +$var wire 1 VQ AorB $end +$var wire 1 WQ AxorB $end +$var wire 1 XQ B $end +$var wire 3 YQ Command [2:0] $end +$var wire 1 ZQ OrNorXorOut $end +$var wire 1 [Q XorNor $end +$var wire 1 \Q nXor $end +$scope module mux0 $end +$var wire 1 ]Q S $end +$var wire 1 WQ in0 $end +$var wire 1 UQ in1 $end +$var wire 1 ^Q nS $end +$var wire 1 _Q out0 $end +$var wire 1 `Q out1 $end +$var wire 1 [Q outfinal $end +$upscope $end +$scope module mux1 $end +$var wire 1 aQ S $end +$var wire 1 [Q in0 $end +$var wire 1 VQ in1 $end +$var wire 1 bQ nS $end +$var wire 1 cQ out0 $end +$var wire 1 dQ out1 $end +$var wire 1 ZQ outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin orbits[18] $end +$scope module attempt $end +$var wire 1 eQ A $end +$var wire 1 fQ AnandB $end +$var wire 1 gQ AnorB $end +$var wire 1 hQ AorB $end +$var wire 1 iQ AxorB $end +$var wire 1 jQ B $end +$var wire 3 kQ Command [2:0] $end +$var wire 1 lQ OrNorXorOut $end +$var wire 1 mQ XorNor $end +$var wire 1 nQ nXor $end +$scope module mux0 $end +$var wire 1 oQ S $end +$var wire 1 iQ in0 $end +$var wire 1 gQ in1 $end +$var wire 1 pQ nS $end +$var wire 1 qQ out0 $end +$var wire 1 rQ out1 $end +$var wire 1 mQ outfinal $end +$upscope $end +$scope module mux1 $end +$var wire 1 sQ S $end +$var wire 1 mQ in0 $end +$var wire 1 hQ in1 $end +$var wire 1 tQ nS $end +$var wire 1 uQ out0 $end +$var wire 1 vQ out1 $end +$var wire 1 lQ outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin orbits[19] $end +$scope module attempt $end +$var wire 1 wQ A $end +$var wire 1 xQ AnandB $end +$var wire 1 yQ AnorB $end +$var wire 1 zQ AorB $end +$var wire 1 {Q AxorB $end +$var wire 1 |Q B $end +$var wire 3 }Q Command [2:0] $end +$var wire 1 ~Q OrNorXorOut $end +$var wire 1 !R XorNor $end +$var wire 1 "R nXor $end +$scope module mux0 $end +$var wire 1 #R S $end +$var wire 1 {Q in0 $end +$var wire 1 yQ in1 $end +$var wire 1 $R nS $end +$var wire 1 %R out0 $end +$var wire 1 &R out1 $end +$var wire 1 !R outfinal $end +$upscope $end +$scope module mux1 $end +$var wire 1 'R S $end +$var wire 1 !R in0 $end +$var wire 1 zQ in1 $end +$var wire 1 (R nS $end +$var wire 1 )R out0 $end +$var wire 1 *R out1 $end +$var wire 1 ~Q outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin orbits[20] $end +$scope module attempt $end +$var wire 1 +R A $end +$var wire 1 ,R AnandB $end +$var wire 1 -R AnorB $end +$var wire 1 .R AorB $end +$var wire 1 /R AxorB $end +$var wire 1 0R B $end +$var wire 3 1R Command [2:0] $end +$var wire 1 2R OrNorXorOut $end +$var wire 1 3R XorNor $end +$var wire 1 4R nXor $end +$scope module mux0 $end +$var wire 1 5R S $end +$var wire 1 /R in0 $end +$var wire 1 -R in1 $end +$var wire 1 6R nS $end +$var wire 1 7R out0 $end +$var wire 1 8R out1 $end +$var wire 1 3R outfinal $end +$upscope $end +$scope module mux1 $end +$var wire 1 9R S $end +$var wire 1 3R in0 $end +$var wire 1 .R in1 $end +$var wire 1 :R nS $end +$var wire 1 ;R out0 $end +$var wire 1 R AnandB $end +$var wire 1 ?R AnorB $end +$var wire 1 @R AorB $end +$var wire 1 AR AxorB $end +$var wire 1 BR B $end +$var wire 3 CR Command [2:0] $end +$var wire 1 DR OrNorXorOut $end +$var wire 1 ER XorNor $end +$var wire 1 FR nXor $end +$scope module mux0 $end +$var wire 1 GR S $end +$var wire 1 AR in0 $end +$var wire 1 ?R in1 $end +$var wire 1 HR nS $end +$var wire 1 IR out0 $end +$var wire 1 JR out1 $end +$var wire 1 ER outfinal $end +$upscope $end +$scope module mux1 $end +$var wire 1 KR S $end +$var wire 1 ER in0 $end +$var wire 1 @R in1 $end +$var wire 1 LR nS $end +$var wire 1 MR out0 $end +$var wire 1 NR out1 $end +$var wire 1 DR outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin orbits[22] $end +$scope module attempt $end +$var wire 1 OR A $end +$var wire 1 PR AnandB $end +$var wire 1 QR AnorB $end +$var wire 1 RR AorB $end +$var wire 1 SR AxorB $end +$var wire 1 TR B $end +$var wire 3 UR Command [2:0] $end +$var wire 1 VR OrNorXorOut $end +$var wire 1 WR XorNor $end +$var wire 1 XR nXor $end +$scope module mux0 $end +$var wire 1 YR S $end +$var wire 1 SR in0 $end +$var wire 1 QR in1 $end +$var wire 1 ZR nS $end +$var wire 1 [R out0 $end +$var wire 1 \R out1 $end +$var wire 1 WR outfinal $end +$upscope $end +$scope module mux1 $end +$var wire 1 ]R S $end +$var wire 1 WR in0 $end +$var wire 1 RR in1 $end +$var wire 1 ^R nS $end +$var wire 1 _R out0 $end +$var wire 1 `R out1 $end +$var wire 1 VR outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin orbits[23] $end +$scope module attempt $end +$var wire 1 aR A $end +$var wire 1 bR AnandB $end +$var wire 1 cR AnorB $end +$var wire 1 dR AorB $end +$var wire 1 eR AxorB $end +$var wire 1 fR B $end +$var wire 3 gR Command [2:0] $end +$var wire 1 hR OrNorXorOut $end +$var wire 1 iR XorNor $end +$var wire 1 jR nXor $end +$scope module mux0 $end +$var wire 1 kR S $end +$var wire 1 eR in0 $end +$var wire 1 cR in1 $end +$var wire 1 lR nS $end +$var wire 1 mR out0 $end +$var wire 1 nR out1 $end +$var wire 1 iR outfinal $end +$upscope $end +$scope module mux1 $end +$var wire 1 oR S $end +$var wire 1 iR in0 $end +$var wire 1 dR in1 $end +$var wire 1 pR nS $end +$var wire 1 qR out0 $end +$var wire 1 rR out1 $end +$var wire 1 hR outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin orbits[24] $end +$scope module attempt $end +$var wire 1 sR A $end +$var wire 1 tR AnandB $end +$var wire 1 uR AnorB $end +$var wire 1 vR AorB $end +$var wire 1 wR AxorB $end +$var wire 1 xR B $end +$var wire 3 yR Command [2:0] $end +$var wire 1 zR OrNorXorOut $end +$var wire 1 {R XorNor $end +$var wire 1 |R nXor $end +$scope module mux0 $end +$var wire 1 }R S $end +$var wire 1 wR in0 $end +$var wire 1 uR in1 $end +$var wire 1 ~R nS $end +$var wire 1 !S out0 $end +$var wire 1 "S out1 $end +$var wire 1 {R outfinal $end +$upscope $end +$scope module mux1 $end +$var wire 1 #S S $end +$var wire 1 {R in0 $end +$var wire 1 vR in1 $end +$var wire 1 $S nS $end +$var wire 1 %S out0 $end +$var wire 1 &S out1 $end +$var wire 1 zR outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin orbits[25] $end +$scope module attempt $end +$var wire 1 'S A $end +$var wire 1 (S AnandB $end +$var wire 1 )S AnorB $end +$var wire 1 *S AorB $end +$var wire 1 +S AxorB $end +$var wire 1 ,S B $end +$var wire 3 -S Command [2:0] $end +$var wire 1 .S OrNorXorOut $end +$var wire 1 /S XorNor $end +$var wire 1 0S nXor $end +$scope module mux0 $end +$var wire 1 1S S $end +$var wire 1 +S in0 $end +$var wire 1 )S in1 $end +$var wire 1 2S nS $end +$var wire 1 3S out0 $end +$var wire 1 4S out1 $end +$var wire 1 /S outfinal $end +$upscope $end +$scope module mux1 $end +$var wire 1 5S S $end +$var wire 1 /S in0 $end +$var wire 1 *S in1 $end +$var wire 1 6S nS $end +$var wire 1 7S out0 $end +$var wire 1 8S out1 $end +$var wire 1 .S outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin orbits[26] $end +$scope module attempt $end +$var wire 1 9S A $end +$var wire 1 :S AnandB $end +$var wire 1 ;S AnorB $end +$var wire 1 S B $end +$var wire 3 ?S Command [2:0] $end +$var wire 1 @S OrNorXorOut $end +$var wire 1 AS XorNor $end +$var wire 1 BS nXor $end +$scope module mux0 $end +$var wire 1 CS S $end +$var wire 1 =S in0 $end +$var wire 1 ;S in1 $end +$var wire 1 DS nS $end +$var wire 1 ES out0 $end +$var wire 1 FS out1 $end +$var wire 1 AS outfinal $end +$upscope $end +$scope module mux1 $end +$var wire 1 GS S $end +$var wire 1 AS in0 $end +$var wire 1 T nXor $end +$scope module mux0 $end +$var wire 1 ?T S $end +$var wire 1 9T in0 $end +$var wire 1 7T in1 $end +$var wire 1 @T nS $end +$var wire 1 AT out0 $end +$var wire 1 BT out1 $end +$var wire 1 =T outfinal $end +$upscope $end +$scope module mux1 $end +$var wire 1 CT S $end +$var wire 1 =T in0 $end +$var wire 1 8T in1 $end +$var wire 1 DT nS $end +$var wire 1 ET out0 $end +$var wire 1 FT out1 $end +$var wire 1 U nS0 $end +$var wire 1 ?U nS1 $end +$var wire 1 @U out $end +$var wire 1 AU out0 $end +$var wire 1 BU out1 $end +$var wire 1 CU out2 $end +$var wire 1 DU out3 $end +$upscope $end +$scope module TwoMux $end +$var wire 1 EU S $end +$var wire 1 FU in0 $end +$var wire 1 GU in1 $end +$var wire 1 HU nS $end +$var wire 1 IU out0 $end +$var wire 1 JU out1 $end +$var wire 1 KU outfinal $end +$upscope $end +$upscope $end +$scope begin muxbits[3] $end +$scope module ZeroMux $end +$var wire 1 LU S0 $end +$var wire 1 MU S1 $end +$var wire 1 NU in0 $end +$var wire 1 OU in1 $end +$var wire 1 PU in2 $end +$var wire 1 QU in3 $end +$var wire 1 RU nS0 $end +$var wire 1 SU nS1 $end +$var wire 1 TU out $end +$var wire 1 UU out0 $end +$var wire 1 VU out1 $end +$var wire 1 WU out2 $end +$var wire 1 XU out3 $end +$upscope $end +$scope module OneMux $end +$var wire 1 YU S0 $end +$var wire 1 ZU S1 $end +$var wire 1 [U in0 $end +$var wire 1 \U in1 $end +$var wire 1 ]U in2 $end +$var wire 1 ^U in3 $end +$var wire 1 _U nS0 $end +$var wire 1 `U nS1 $end +$var wire 1 aU out $end +$var wire 1 bU out0 $end +$var wire 1 cU out1 $end +$var wire 1 dU out2 $end +$var wire 1 eU out3 $end +$upscope $end +$scope module TwoMux $end +$var wire 1 fU S $end +$var wire 1 gU in0 $end +$var wire 1 hU in1 $end +$var wire 1 iU nS $end +$var wire 1 jU out0 $end +$var wire 1 kU out1 $end +$var wire 1 lU outfinal $end +$upscope $end +$upscope $end +$scope begin muxbits[4] $end +$scope module ZeroMux $end +$var wire 1 mU S0 $end +$var wire 1 nU S1 $end +$var wire 1 oU in0 $end +$var wire 1 pU in1 $end +$var wire 1 qU in2 $end +$var wire 1 rU in3 $end +$var wire 1 sU nS0 $end +$var wire 1 tU nS1 $end +$var wire 1 uU out $end +$var wire 1 vU out0 $end +$var wire 1 wU out1 $end +$var wire 1 xU out2 $end +$var wire 1 yU out3 $end +$upscope $end +$scope module OneMux $end +$var wire 1 zU S0 $end +$var wire 1 {U S1 $end +$var wire 1 |U in0 $end +$var wire 1 }U in1 $end +$var wire 1 ~U in2 $end +$var wire 1 !V in3 $end +$var wire 1 "V nS0 $end +$var wire 1 #V nS1 $end +$var wire 1 $V out $end +$var wire 1 %V out0 $end +$var wire 1 &V out1 $end +$var wire 1 'V out2 $end +$var wire 1 (V out3 $end +$upscope $end +$scope module TwoMux $end +$var wire 1 )V S $end +$var wire 1 *V in0 $end +$var wire 1 +V in1 $end +$var wire 1 ,V nS $end +$var wire 1 -V out0 $end +$var wire 1 .V out1 $end +$var wire 1 /V outfinal $end +$upscope $end +$upscope $end +$scope begin muxbits[5] $end +$scope module ZeroMux $end +$var wire 1 0V S0 $end +$var wire 1 1V S1 $end +$var wire 1 2V in0 $end +$var wire 1 3V in1 $end +$var wire 1 4V in2 $end +$var wire 1 5V in3 $end +$var wire 1 6V nS0 $end +$var wire 1 7V nS1 $end +$var wire 1 8V out $end +$var wire 1 9V out0 $end +$var wire 1 :V out1 $end +$var wire 1 ;V out2 $end +$var wire 1 V S1 $end +$var wire 1 ?V in0 $end +$var wire 1 @V in1 $end +$var wire 1 AV in2 $end +$var wire 1 BV in3 $end +$var wire 1 CV nS0 $end +$var wire 1 DV nS1 $end +$var wire 1 EV out $end +$var wire 1 FV out0 $end +$var wire 1 GV out1 $end +$var wire 1 HV out2 $end +$var wire 1 IV out3 $end +$upscope $end +$scope module TwoMux $end +$var wire 1 JV S $end +$var wire 1 KV in0 $end +$var wire 1 LV in1 $end +$var wire 1 MV nS $end +$var wire 1 NV out0 $end +$var wire 1 OV out1 $end +$var wire 1 PV outfinal $end +$upscope $end +$upscope $end +$scope begin muxbits[6] $end +$scope module ZeroMux $end +$var wire 1 QV S0 $end +$var wire 1 RV S1 $end +$var wire 1 SV in0 $end +$var wire 1 TV in1 $end +$var wire 1 UV in2 $end +$var wire 1 VV in3 $end +$var wire 1 WV nS0 $end +$var wire 1 XV nS1 $end +$var wire 1 YV out $end +$var wire 1 ZV out0 $end +$var wire 1 [V out1 $end +$var wire 1 \V out2 $end +$var wire 1 ]V out3 $end +$upscope $end +$scope module OneMux $end +$var wire 1 ^V S0 $end +$var wire 1 _V S1 $end +$var wire 1 `V in0 $end +$var wire 1 aV in1 $end +$var wire 1 bV in2 $end +$var wire 1 cV in3 $end +$var wire 1 dV nS0 $end +$var wire 1 eV nS1 $end +$var wire 1 fV out $end +$var wire 1 gV out0 $end +$var wire 1 hV out1 $end +$var wire 1 iV out2 $end +$var wire 1 jV out3 $end +$upscope $end +$scope module TwoMux $end +$var wire 1 kV S $end +$var wire 1 lV in0 $end +$var wire 1 mV in1 $end +$var wire 1 nV nS $end +$var wire 1 oV out0 $end +$var wire 1 pV out1 $end +$var wire 1 qV outfinal $end +$upscope $end +$upscope $end +$scope begin muxbits[7] $end +$scope module ZeroMux $end +$var wire 1 rV S0 $end +$var wire 1 sV S1 $end +$var wire 1 tV in0 $end +$var wire 1 uV in1 $end +$var wire 1 vV in2 $end +$var wire 1 wV in3 $end +$var wire 1 xV nS0 $end +$var wire 1 yV nS1 $end +$var wire 1 zV out $end +$var wire 1 {V out0 $end +$var wire 1 |V out1 $end +$var wire 1 }V out2 $end +$var wire 1 ~V out3 $end +$upscope $end +$scope module OneMux $end +$var wire 1 !W S0 $end +$var wire 1 "W S1 $end +$var wire 1 #W in0 $end +$var wire 1 $W in1 $end +$var wire 1 %W in2 $end +$var wire 1 &W in3 $end +$var wire 1 'W nS0 $end +$var wire 1 (W nS1 $end +$var wire 1 )W out $end +$var wire 1 *W out0 $end +$var wire 1 +W out1 $end +$var wire 1 ,W out2 $end +$var wire 1 -W out3 $end +$upscope $end +$scope module TwoMux $end +$var wire 1 .W S $end +$var wire 1 /W in0 $end +$var wire 1 0W in1 $end +$var wire 1 1W nS $end +$var wire 1 2W out0 $end +$var wire 1 3W out1 $end +$var wire 1 4W outfinal $end +$upscope $end +$upscope $end +$scope begin muxbits[8] $end +$scope module ZeroMux $end +$var wire 1 5W S0 $end +$var wire 1 6W S1 $end +$var wire 1 7W in0 $end +$var wire 1 8W in1 $end +$var wire 1 9W in2 $end +$var wire 1 :W in3 $end +$var wire 1 ;W nS0 $end +$var wire 1 W out0 $end +$var wire 1 ?W out1 $end +$var wire 1 @W out2 $end +$var wire 1 AW out3 $end +$upscope $end +$scope module OneMux $end +$var wire 1 BW S0 $end +$var wire 1 CW S1 $end +$var wire 1 DW in0 $end +$var wire 1 EW in1 $end +$var wire 1 FW in2 $end +$var wire 1 GW in3 $end +$var wire 1 HW nS0 $end +$var wire 1 IW nS1 $end +$var wire 1 JW out $end +$var wire 1 KW out0 $end +$var wire 1 LW out1 $end +$var wire 1 MW out2 $end +$var wire 1 NW out3 $end +$upscope $end +$scope module TwoMux $end +$var wire 1 OW S $end +$var wire 1 PW in0 $end +$var wire 1 QW in1 $end +$var wire 1 RW nS $end +$var wire 1 SW out0 $end +$var wire 1 TW out1 $end +$var wire 1 UW outfinal $end +$upscope $end +$upscope $end +$scope begin muxbits[9] $end +$scope module ZeroMux $end +$var wire 1 VW S0 $end +$var wire 1 WW S1 $end +$var wire 1 XW in0 $end +$var wire 1 YW in1 $end +$var wire 1 ZW in2 $end +$var wire 1 [W in3 $end +$var wire 1 \W nS0 $end +$var wire 1 ]W nS1 $end +$var wire 1 ^W out $end +$var wire 1 _W out0 $end +$var wire 1 `W out1 $end +$var wire 1 aW out2 $end +$var wire 1 bW out3 $end +$upscope $end +$scope module OneMux $end +$var wire 1 cW S0 $end +$var wire 1 dW S1 $end +$var wire 1 eW in0 $end +$var wire 1 fW in1 $end +$var wire 1 gW in2 $end +$var wire 1 hW in3 $end +$var wire 1 iW nS0 $end +$var wire 1 jW nS1 $end +$var wire 1 kW out $end +$var wire 1 lW out0 $end +$var wire 1 mW out1 $end +$var wire 1 nW out2 $end +$var wire 1 oW out3 $end +$upscope $end +$scope module TwoMux $end +$var wire 1 pW S $end +$var wire 1 qW in0 $end +$var wire 1 rW in1 $end +$var wire 1 sW nS $end +$var wire 1 tW out0 $end +$var wire 1 uW out1 $end +$var wire 1 vW outfinal $end +$upscope $end +$upscope $end +$scope begin muxbits[10] $end +$scope module ZeroMux $end +$var wire 1 wW S0 $end +$var wire 1 xW S1 $end +$var wire 1 yW in0 $end +$var wire 1 zW in1 $end +$var wire 1 {W in2 $end +$var wire 1 |W in3 $end +$var wire 1 }W nS0 $end +$var wire 1 ~W nS1 $end +$var wire 1 !X out $end +$var wire 1 "X out0 $end +$var wire 1 #X out1 $end +$var wire 1 $X out2 $end +$var wire 1 %X out3 $end +$upscope $end +$scope module OneMux $end +$var wire 1 &X S0 $end +$var wire 1 'X S1 $end +$var wire 1 (X in0 $end +$var wire 1 )X in1 $end +$var wire 1 *X in2 $end +$var wire 1 +X in3 $end +$var wire 1 ,X nS0 $end +$var wire 1 -X nS1 $end +$var wire 1 .X out $end +$var wire 1 /X out0 $end +$var wire 1 0X out1 $end +$var wire 1 1X out2 $end +$var wire 1 2X out3 $end +$upscope $end +$scope module TwoMux $end +$var wire 1 3X S $end +$var wire 1 4X in0 $end +$var wire 1 5X in1 $end +$var wire 1 6X nS $end +$var wire 1 7X out0 $end +$var wire 1 8X out1 $end +$var wire 1 9X outfinal $end +$upscope $end +$upscope $end +$scope begin muxbits[11] $end +$scope module ZeroMux $end +$var wire 1 :X S0 $end +$var wire 1 ;X S1 $end +$var wire 1 X in2 $end +$var wire 1 ?X in3 $end +$var wire 1 @X nS0 $end +$var wire 1 AX nS1 $end +$var wire 1 BX out $end +$var wire 1 CX out0 $end +$var wire 1 DX out1 $end +$var wire 1 EX out2 $end +$var wire 1 FX out3 $end +$upscope $end +$scope module OneMux $end +$var wire 1 GX S0 $end +$var wire 1 HX S1 $end +$var wire 1 IX in0 $end +$var wire 1 JX in1 $end +$var wire 1 KX in2 $end +$var wire 1 LX in3 $end +$var wire 1 MX nS0 $end +$var wire 1 NX nS1 $end +$var wire 1 OX out $end +$var wire 1 PX out0 $end +$var wire 1 QX out1 $end +$var wire 1 RX out2 $end +$var wire 1 SX out3 $end +$upscope $end +$scope module TwoMux $end +$var wire 1 TX S $end +$var wire 1 UX in0 $end +$var wire 1 VX in1 $end +$var wire 1 WX nS $end +$var wire 1 XX out0 $end +$var wire 1 YX out1 $end +$var wire 1 ZX outfinal $end +$upscope $end +$upscope $end +$scope begin muxbits[12] $end +$scope module ZeroMux $end +$var wire 1 [X S0 $end +$var wire 1 \X S1 $end +$var wire 1 ]X in0 $end +$var wire 1 ^X in1 $end +$var wire 1 _X in2 $end +$var wire 1 `X in3 $end +$var wire 1 aX nS0 $end +$var wire 1 bX nS1 $end +$var wire 1 cX out $end +$var wire 1 dX out0 $end +$var wire 1 eX out1 $end +$var wire 1 fX out2 $end +$var wire 1 gX out3 $end +$upscope $end +$scope module OneMux $end +$var wire 1 hX S0 $end +$var wire 1 iX S1 $end +$var wire 1 jX in0 $end +$var wire 1 kX in1 $end +$var wire 1 lX in2 $end +$var wire 1 mX in3 $end +$var wire 1 nX nS0 $end +$var wire 1 oX nS1 $end +$var wire 1 pX out $end +$var wire 1 qX out0 $end +$var wire 1 rX out1 $end +$var wire 1 sX out2 $end +$var wire 1 tX out3 $end +$upscope $end +$scope module TwoMux $end +$var wire 1 uX S $end +$var wire 1 vX in0 $end +$var wire 1 wX in1 $end +$var wire 1 xX nS $end +$var wire 1 yX out0 $end +$var wire 1 zX out1 $end +$var wire 1 {X outfinal $end +$upscope $end +$upscope $end +$scope begin muxbits[13] $end +$scope module ZeroMux $end +$var wire 1 |X S0 $end +$var wire 1 }X S1 $end +$var wire 1 ~X in0 $end +$var wire 1 !Y in1 $end +$var wire 1 "Y in2 $end +$var wire 1 #Y in3 $end +$var wire 1 $Y nS0 $end +$var wire 1 %Y nS1 $end +$var wire 1 &Y out $end +$var wire 1 'Y out0 $end +$var wire 1 (Y out1 $end +$var wire 1 )Y out2 $end +$var wire 1 *Y out3 $end +$upscope $end +$scope module OneMux $end +$var wire 1 +Y S0 $end +$var wire 1 ,Y S1 $end +$var wire 1 -Y in0 $end +$var wire 1 .Y in1 $end +$var wire 1 /Y in2 $end +$var wire 1 0Y in3 $end +$var wire 1 1Y nS0 $end +$var wire 1 2Y nS1 $end +$var wire 1 3Y out $end +$var wire 1 4Y out0 $end +$var wire 1 5Y out1 $end +$var wire 1 6Y out2 $end +$var wire 1 7Y out3 $end +$upscope $end +$scope module TwoMux $end +$var wire 1 8Y S $end +$var wire 1 9Y in0 $end +$var wire 1 :Y in1 $end +$var wire 1 ;Y nS $end +$var wire 1 Y outfinal $end +$upscope $end +$upscope $end +$scope begin muxbits[14] $end +$scope module ZeroMux $end +$var wire 1 ?Y S0 $end +$var wire 1 @Y S1 $end +$var wire 1 AY in0 $end +$var wire 1 BY in1 $end +$var wire 1 CY in2 $end +$var wire 1 DY in3 $end +$var wire 1 EY nS0 $end +$var wire 1 FY nS1 $end +$var wire 1 GY out $end +$var wire 1 HY out0 $end +$var wire 1 IY out1 $end +$var wire 1 JY out2 $end +$var wire 1 KY out3 $end +$upscope $end +$scope module OneMux $end +$var wire 1 LY S0 $end +$var wire 1 MY S1 $end +$var wire 1 NY in0 $end +$var wire 1 OY in1 $end +$var wire 1 PY in2 $end +$var wire 1 QY in3 $end +$var wire 1 RY nS0 $end +$var wire 1 SY nS1 $end +$var wire 1 TY out $end +$var wire 1 UY out0 $end +$var wire 1 VY out1 $end +$var wire 1 WY out2 $end +$var wire 1 XY out3 $end +$upscope $end +$scope module TwoMux $end +$var wire 1 YY S $end +$var wire 1 ZY in0 $end +$var wire 1 [Y in1 $end +$var wire 1 \Y nS $end +$var wire 1 ]Y out0 $end +$var wire 1 ^Y out1 $end +$var wire 1 _Y outfinal $end +$upscope $end +$upscope $end +$scope begin muxbits[15] $end +$scope module ZeroMux $end +$var wire 1 `Y S0 $end +$var wire 1 aY S1 $end +$var wire 1 bY in0 $end +$var wire 1 cY in1 $end +$var wire 1 dY in2 $end +$var wire 1 eY in3 $end +$var wire 1 fY nS0 $end +$var wire 1 gY nS1 $end +$var wire 1 hY out $end +$var wire 1 iY out0 $end +$var wire 1 jY out1 $end +$var wire 1 kY out2 $end +$var wire 1 lY out3 $end +$upscope $end +$scope module OneMux $end +$var wire 1 mY S0 $end +$var wire 1 nY S1 $end +$var wire 1 oY in0 $end +$var wire 1 pY in1 $end +$var wire 1 qY in2 $end +$var wire 1 rY in3 $end +$var wire 1 sY nS0 $end +$var wire 1 tY nS1 $end +$var wire 1 uY out $end +$var wire 1 vY out0 $end +$var wire 1 wY out1 $end +$var wire 1 xY out2 $end +$var wire 1 yY out3 $end +$upscope $end +$scope module TwoMux $end +$var wire 1 zY S $end +$var wire 1 {Y in0 $end +$var wire 1 |Y in1 $end +$var wire 1 }Y nS $end +$var wire 1 ~Y out0 $end +$var wire 1 !Z out1 $end +$var wire 1 "Z outfinal $end +$upscope $end +$upscope $end +$scope begin muxbits[16] $end +$scope module ZeroMux $end +$var wire 1 #Z S0 $end +$var wire 1 $Z S1 $end +$var wire 1 %Z in0 $end +$var wire 1 &Z in1 $end +$var wire 1 'Z in2 $end +$var wire 1 (Z in3 $end +$var wire 1 )Z nS0 $end +$var wire 1 *Z nS1 $end +$var wire 1 +Z out $end +$var wire 1 ,Z out0 $end +$var wire 1 -Z out1 $end +$var wire 1 .Z out2 $end +$var wire 1 /Z out3 $end +$upscope $end +$scope module OneMux $end +$var wire 1 0Z S0 $end +$var wire 1 1Z S1 $end +$var wire 1 2Z in0 $end +$var wire 1 3Z in1 $end +$var wire 1 4Z in2 $end +$var wire 1 5Z in3 $end +$var wire 1 6Z nS0 $end +$var wire 1 7Z nS1 $end +$var wire 1 8Z out $end +$var wire 1 9Z out0 $end +$var wire 1 :Z out1 $end +$var wire 1 ;Z out2 $end +$var wire 1 Z in0 $end +$var wire 1 ?Z in1 $end +$var wire 1 @Z nS $end +$var wire 1 AZ out0 $end +$var wire 1 BZ out1 $end +$var wire 1 CZ outfinal $end +$upscope $end +$upscope $end +$scope begin muxbits[17] $end +$scope module ZeroMux $end +$var wire 1 DZ S0 $end +$var wire 1 EZ S1 $end +$var wire 1 FZ in0 $end +$var wire 1 GZ in1 $end +$var wire 1 HZ in2 $end +$var wire 1 IZ in3 $end +$var wire 1 JZ nS0 $end +$var wire 1 KZ nS1 $end +$var wire 1 LZ out $end +$var wire 1 MZ out0 $end +$var wire 1 NZ out1 $end +$var wire 1 OZ out2 $end +$var wire 1 PZ out3 $end +$upscope $end +$scope module OneMux $end +$var wire 1 QZ S0 $end +$var wire 1 RZ S1 $end +$var wire 1 SZ in0 $end +$var wire 1 TZ in1 $end +$var wire 1 UZ in2 $end +$var wire 1 VZ in3 $end +$var wire 1 WZ nS0 $end +$var wire 1 XZ nS1 $end +$var wire 1 YZ out $end +$var wire 1 ZZ out0 $end +$var wire 1 [Z out1 $end +$var wire 1 \Z out2 $end +$var wire 1 ]Z out3 $end +$upscope $end +$scope module TwoMux $end +$var wire 1 ^Z S $end +$var wire 1 _Z in0 $end +$var wire 1 `Z in1 $end +$var wire 1 aZ nS $end +$var wire 1 bZ out0 $end +$var wire 1 cZ out1 $end +$var wire 1 dZ outfinal $end +$upscope $end +$upscope $end +$scope begin muxbits[18] $end +$scope module ZeroMux $end +$var wire 1 eZ S0 $end +$var wire 1 fZ S1 $end +$var wire 1 gZ in0 $end +$var wire 1 hZ in1 $end +$var wire 1 iZ in2 $end +$var wire 1 jZ in3 $end +$var wire 1 kZ nS0 $end +$var wire 1 lZ nS1 $end +$var wire 1 mZ out $end +$var wire 1 nZ out0 $end +$var wire 1 oZ out1 $end +$var wire 1 pZ out2 $end +$var wire 1 qZ out3 $end +$upscope $end +$scope module OneMux $end +$var wire 1 rZ S0 $end +$var wire 1 sZ S1 $end +$var wire 1 tZ in0 $end +$var wire 1 uZ in1 $end +$var wire 1 vZ in2 $end +$var wire 1 wZ in3 $end +$var wire 1 xZ nS0 $end +$var wire 1 yZ nS1 $end +$var wire 1 zZ out $end +$var wire 1 {Z out0 $end +$var wire 1 |Z out1 $end +$var wire 1 }Z out2 $end +$var wire 1 ~Z out3 $end +$upscope $end +$scope module TwoMux $end +$var wire 1 ![ S $end +$var wire 1 "[ in0 $end +$var wire 1 #[ in1 $end +$var wire 1 $[ nS $end +$var wire 1 %[ out0 $end +$var wire 1 &[ out1 $end +$var wire 1 '[ outfinal $end +$upscope $end +$upscope $end +$scope begin muxbits[19] $end +$scope module ZeroMux $end +$var wire 1 ([ S0 $end +$var wire 1 )[ S1 $end +$var wire 1 *[ in0 $end +$var wire 1 +[ in1 $end +$var wire 1 ,[ in2 $end +$var wire 1 -[ in3 $end +$var wire 1 .[ nS0 $end +$var wire 1 /[ nS1 $end +$var wire 1 0[ out $end +$var wire 1 1[ out0 $end +$var wire 1 2[ out1 $end +$var wire 1 3[ out2 $end +$var wire 1 4[ out3 $end +$upscope $end +$scope module OneMux $end +$var wire 1 5[ S0 $end +$var wire 1 6[ S1 $end +$var wire 1 7[ in0 $end +$var wire 1 8[ in1 $end +$var wire 1 9[ in2 $end +$var wire 1 :[ in3 $end +$var wire 1 ;[ nS0 $end +$var wire 1 <[ nS1 $end +$var wire 1 =[ out $end +$var wire 1 >[ out0 $end +$var wire 1 ?[ out1 $end +$var wire 1 @[ out2 $end +$var wire 1 A[ out3 $end +$upscope $end +$scope module TwoMux $end +$var wire 1 B[ S $end +$var wire 1 C[ in0 $end +$var wire 1 D[ in1 $end +$var wire 1 E[ nS $end +$var wire 1 F[ out0 $end +$var wire 1 G[ out1 $end +$var wire 1 H[ outfinal $end +$upscope $end +$upscope $end +$scope begin muxbits[20] $end +$scope module ZeroMux $end +$var wire 1 I[ S0 $end +$var wire 1 J[ S1 $end +$var wire 1 K[ in0 $end +$var wire 1 L[ in1 $end +$var wire 1 M[ in2 $end +$var wire 1 N[ in3 $end +$var wire 1 O[ nS0 $end +$var wire 1 P[ nS1 $end +$var wire 1 Q[ out $end +$var wire 1 R[ out0 $end +$var wire 1 S[ out1 $end +$var wire 1 T[ out2 $end +$var wire 1 U[ out3 $end +$upscope $end +$scope module OneMux $end +$var wire 1 V[ S0 $end +$var wire 1 W[ S1 $end +$var wire 1 X[ in0 $end +$var wire 1 Y[ in1 $end +$var wire 1 Z[ in2 $end +$var wire 1 [[ in3 $end +$var wire 1 \[ nS0 $end +$var wire 1 ][ nS1 $end +$var wire 1 ^[ out $end +$var wire 1 _[ out0 $end +$var wire 1 `[ out1 $end +$var wire 1 a[ out2 $end +$var wire 1 b[ out3 $end +$upscope $end +$scope module TwoMux $end +$var wire 1 c[ S $end +$var wire 1 d[ in0 $end +$var wire 1 e[ in1 $end +$var wire 1 f[ nS $end +$var wire 1 g[ out0 $end +$var wire 1 h[ out1 $end +$var wire 1 i[ outfinal $end +$upscope $end +$upscope $end +$scope begin muxbits[21] $end +$scope module ZeroMux $end +$var wire 1 j[ S0 $end +$var wire 1 k[ S1 $end +$var wire 1 l[ in0 $end +$var wire 1 m[ in1 $end +$var wire 1 n[ in2 $end +$var wire 1 o[ in3 $end +$var wire 1 p[ nS0 $end +$var wire 1 q[ nS1 $end +$var wire 1 r[ out $end +$var wire 1 s[ out0 $end +$var wire 1 t[ out1 $end +$var wire 1 u[ out2 $end +$var wire 1 v[ out3 $end +$upscope $end +$scope module OneMux $end +$var wire 1 w[ S0 $end +$var wire 1 x[ S1 $end +$var wire 1 y[ in0 $end +$var wire 1 z[ in1 $end +$var wire 1 {[ in2 $end +$var wire 1 |[ in3 $end +$var wire 1 }[ nS0 $end +$var wire 1 ~[ nS1 $end +$var wire 1 !\ out $end +$var wire 1 "\ out0 $end +$var wire 1 #\ out1 $end +$var wire 1 $\ out2 $end +$var wire 1 %\ out3 $end +$upscope $end +$scope module TwoMux $end +$var wire 1 &\ S $end +$var wire 1 '\ in0 $end +$var wire 1 (\ in1 $end +$var wire 1 )\ nS $end +$var wire 1 *\ out0 $end +$var wire 1 +\ out1 $end +$var wire 1 ,\ outfinal $end +$upscope $end +$upscope $end +$scope begin muxbits[22] $end +$scope module ZeroMux $end +$var wire 1 -\ S0 $end +$var wire 1 .\ S1 $end +$var wire 1 /\ in0 $end +$var wire 1 0\ in1 $end +$var wire 1 1\ in2 $end +$var wire 1 2\ in3 $end +$var wire 1 3\ nS0 $end +$var wire 1 4\ nS1 $end +$var wire 1 5\ out $end +$var wire 1 6\ out0 $end +$var wire 1 7\ out1 $end +$var wire 1 8\ out2 $end +$var wire 1 9\ out3 $end +$upscope $end +$scope module OneMux $end +$var wire 1 :\ S0 $end +$var wire 1 ;\ S1 $end +$var wire 1 <\ in0 $end +$var wire 1 =\ in1 $end +$var wire 1 >\ in2 $end +$var wire 1 ?\ in3 $end +$var wire 1 @\ nS0 $end +$var wire 1 A\ nS1 $end +$var wire 1 B\ out $end +$var wire 1 C\ out0 $end +$var wire 1 D\ out1 $end +$var wire 1 E\ out2 $end +$var wire 1 F\ out3 $end +$upscope $end +$scope module TwoMux $end +$var wire 1 G\ S $end +$var wire 1 H\ in0 $end +$var wire 1 I\ in1 $end +$var wire 1 J\ nS $end +$var wire 1 K\ out0 $end +$var wire 1 L\ out1 $end +$var wire 1 M\ outfinal $end +$upscope $end +$upscope $end +$scope begin muxbits[23] $end +$scope module ZeroMux $end +$var wire 1 N\ S0 $end +$var wire 1 O\ S1 $end +$var wire 1 P\ in0 $end +$var wire 1 Q\ in1 $end +$var wire 1 R\ in2 $end +$var wire 1 S\ in3 $end +$var wire 1 T\ nS0 $end +$var wire 1 U\ nS1 $end +$var wire 1 V\ out $end +$var wire 1 W\ out0 $end +$var wire 1 X\ out1 $end +$var wire 1 Y\ out2 $end +$var wire 1 Z\ out3 $end +$upscope $end +$scope module OneMux $end +$var wire 1 [\ S0 $end +$var wire 1 \\ S1 $end +$var wire 1 ]\ in0 $end +$var wire 1 ^\ in1 $end +$var wire 1 _\ in2 $end +$var wire 1 `\ in3 $end +$var wire 1 a\ nS0 $end +$var wire 1 b\ nS1 $end +$var wire 1 c\ out $end +$var wire 1 d\ out0 $end +$var wire 1 e\ out1 $end +$var wire 1 f\ out2 $end +$var wire 1 g\ out3 $end +$upscope $end +$scope module TwoMux $end +$var wire 1 h\ S $end +$var wire 1 i\ in0 $end +$var wire 1 j\ in1 $end +$var wire 1 k\ nS $end +$var wire 1 l\ out0 $end +$var wire 1 m\ out1 $end +$var wire 1 n\ outfinal $end +$upscope $end +$upscope $end +$scope begin muxbits[24] $end +$scope module ZeroMux $end +$var wire 1 o\ S0 $end +$var wire 1 p\ S1 $end +$var wire 1 q\ in0 $end +$var wire 1 r\ in1 $end +$var wire 1 s\ in2 $end +$var wire 1 t\ in3 $end +$var wire 1 u\ nS0 $end +$var wire 1 v\ nS1 $end +$var wire 1 w\ out $end +$var wire 1 x\ out0 $end +$var wire 1 y\ out1 $end +$var wire 1 z\ out2 $end +$var wire 1 {\ out3 $end +$upscope $end +$scope module OneMux $end +$var wire 1 |\ S0 $end +$var wire 1 }\ S1 $end +$var wire 1 ~\ in0 $end +$var wire 1 !] in1 $end +$var wire 1 "] in2 $end +$var wire 1 #] in3 $end +$var wire 1 $] nS0 $end +$var wire 1 %] nS1 $end +$var wire 1 &] out $end +$var wire 1 '] out0 $end +$var wire 1 (] out1 $end +$var wire 1 )] out2 $end +$var wire 1 *] out3 $end +$upscope $end +$scope module TwoMux $end +$var wire 1 +] S $end +$var wire 1 ,] in0 $end +$var wire 1 -] in1 $end +$var wire 1 .] nS $end +$var wire 1 /] out0 $end +$var wire 1 0] out1 $end +$var wire 1 1] outfinal $end +$upscope $end +$upscope $end +$scope begin muxbits[25] $end +$scope module ZeroMux $end +$var wire 1 2] S0 $end +$var wire 1 3] S1 $end +$var wire 1 4] in0 $end +$var wire 1 5] in1 $end +$var wire 1 6] in2 $end +$var wire 1 7] in3 $end +$var wire 1 8] nS0 $end +$var wire 1 9] nS1 $end +$var wire 1 :] out $end +$var wire 1 ;] out0 $end +$var wire 1 <] out1 $end +$var wire 1 =] out2 $end +$var wire 1 >] out3 $end +$upscope $end +$scope module OneMux $end +$var wire 1 ?] S0 $end +$var wire 1 @] S1 $end +$var wire 1 A] in0 $end +$var wire 1 B] in1 $end +$var wire 1 C] in2 $end +$var wire 1 D] in3 $end +$var wire 1 E] nS0 $end +$var wire 1 F] nS1 $end +$var wire 1 G] out $end +$var wire 1 H] out0 $end +$var wire 1 I] out1 $end +$var wire 1 J] out2 $end +$var wire 1 K] out3 $end +$upscope $end +$scope module TwoMux $end +$var wire 1 L] S $end +$var wire 1 M] in0 $end +$var wire 1 N] in1 $end +$var wire 1 O] nS $end +$var wire 1 P] out0 $end +$var wire 1 Q] out1 $end +$var wire 1 R] outfinal $end +$upscope $end +$upscope $end +$scope begin muxbits[26] $end +$scope module ZeroMux $end +$var wire 1 S] S0 $end +$var wire 1 T] S1 $end +$var wire 1 U] in0 $end +$var wire 1 V] in1 $end +$var wire 1 W] in2 $end +$var wire 1 X] in3 $end +$var wire 1 Y] nS0 $end +$var wire 1 Z] nS1 $end +$var wire 1 [] out $end +$var wire 1 \] out0 $end +$var wire 1 ]] out1 $end +$var wire 1 ^] out2 $end +$var wire 1 _] out3 $end +$upscope $end +$scope module OneMux $end +$var wire 1 `] S0 $end +$var wire 1 a] S1 $end +$var wire 1 b] in0 $end +$var wire 1 c] in1 $end +$var wire 1 d] in2 $end +$var wire 1 e] in3 $end +$var wire 1 f] nS0 $end +$var wire 1 g] nS1 $end +$var wire 1 h] out $end +$var wire 1 i] out0 $end +$var wire 1 j] out1 $end +$var wire 1 k] out2 $end +$var wire 1 l] out3 $end +$upscope $end +$scope module TwoMux $end +$var wire 1 m] S $end +$var wire 1 n] in0 $end +$var wire 1 o] in1 $end +$var wire 1 p] nS $end +$var wire 1 q] out0 $end +$var wire 1 r] out1 $end +$var wire 1 s] outfinal $end +$upscope $end +$upscope $end +$scope begin muxbits[27] $end +$scope module ZeroMux $end +$var wire 1 t] S0 $end +$var wire 1 u] S1 $end +$var wire 1 v] in0 $end +$var wire 1 w] in1 $end +$var wire 1 x] in2 $end +$var wire 1 y] in3 $end +$var wire 1 z] nS0 $end +$var wire 1 {] nS1 $end +$var wire 1 |] out $end +$var wire 1 }] out0 $end +$var wire 1 ~] out1 $end +$var wire 1 !^ out2 $end +$var wire 1 "^ out3 $end +$upscope $end +$scope module OneMux $end +$var wire 1 #^ S0 $end +$var wire 1 $^ S1 $end +$var wire 1 %^ in0 $end +$var wire 1 &^ in1 $end +$var wire 1 '^ in2 $end +$var wire 1 (^ in3 $end +$var wire 1 )^ nS0 $end +$var wire 1 *^ nS1 $end +$var wire 1 +^ out $end +$var wire 1 ,^ out0 $end +$var wire 1 -^ out1 $end +$var wire 1 .^ out2 $end +$var wire 1 /^ out3 $end +$upscope $end +$scope module TwoMux $end +$var wire 1 0^ S $end +$var wire 1 1^ in0 $end +$var wire 1 2^ in1 $end +$var wire 1 3^ nS $end +$var wire 1 4^ out0 $end +$var wire 1 5^ out1 $end +$var wire 1 6^ outfinal $end +$upscope $end +$upscope $end +$scope begin muxbits[28] $end +$scope module ZeroMux $end +$var wire 1 7^ S0 $end +$var wire 1 8^ S1 $end +$var wire 1 9^ in0 $end +$var wire 1 :^ in1 $end +$var wire 1 ;^ in2 $end +$var wire 1 <^ in3 $end +$var wire 1 =^ nS0 $end +$var wire 1 >^ nS1 $end +$var wire 1 ?^ out $end +$var wire 1 @^ out0 $end +$var wire 1 A^ out1 $end +$var wire 1 B^ out2 $end +$var wire 1 C^ out3 $end +$upscope $end +$scope module OneMux $end +$var wire 1 D^ S0 $end +$var wire 1 E^ S1 $end +$var wire 1 F^ in0 $end +$var wire 1 G^ in1 $end +$var wire 1 H^ in2 $end +$var wire 1 I^ in3 $end +$var wire 1 J^ nS0 $end +$var wire 1 K^ nS1 $end +$var wire 1 L^ out $end +$var wire 1 M^ out0 $end +$var wire 1 N^ out1 $end +$var wire 1 O^ out2 $end +$var wire 1 P^ out3 $end +$upscope $end +$scope module TwoMux $end +$var wire 1 Q^ S $end +$var wire 1 R^ in0 $end +$var wire 1 S^ in1 $end +$var wire 1 T^ nS $end +$var wire 1 U^ out0 $end +$var wire 1 V^ out1 $end +$var wire 1 W^ outfinal $end +$upscope $end +$upscope $end +$scope begin muxbits[29] $end +$scope module ZeroMux $end +$var wire 1 X^ S0 $end +$var wire 1 Y^ S1 $end +$var wire 1 Z^ in0 $end +$var wire 1 [^ in1 $end +$var wire 1 \^ in2 $end +$var wire 1 ]^ in3 $end +$var wire 1 ^^ nS0 $end +$var wire 1 _^ nS1 $end +$var wire 1 `^ out $end +$var wire 1 a^ out0 $end +$var wire 1 b^ out1 $end +$var wire 1 c^ out2 $end +$var wire 1 d^ out3 $end +$upscope $end +$scope module OneMux $end +$var wire 1 e^ S0 $end +$var wire 1 f^ S1 $end +$var wire 1 g^ in0 $end +$var wire 1 h^ in1 $end +$var wire 1 i^ in2 $end +$var wire 1 j^ in3 $end +$var wire 1 k^ nS0 $end +$var wire 1 l^ nS1 $end +$var wire 1 m^ out $end +$var wire 1 n^ out0 $end +$var wire 1 o^ out1 $end +$var wire 1 p^ out2 $end +$var wire 1 q^ out3 $end +$upscope $end +$scope module TwoMux $end +$var wire 1 r^ S $end +$var wire 1 s^ in0 $end +$var wire 1 t^ in1 $end +$var wire 1 u^ nS $end +$var wire 1 v^ out0 $end +$var wire 1 w^ out1 $end +$var wire 1 x^ outfinal $end +$upscope $end +$upscope $end +$scope begin muxbits[30] $end +$scope module ZeroMux $end +$var wire 1 y^ S0 $end +$var wire 1 z^ S1 $end +$var wire 1 {^ in0 $end +$var wire 1 |^ in1 $end +$var wire 1 }^ in2 $end +$var wire 1 ~^ in3 $end +$var wire 1 !_ nS0 $end +$var wire 1 "_ nS1 $end +$var wire 1 #_ out $end +$var wire 1 $_ out0 $end +$var wire 1 %_ out1 $end +$var wire 1 &_ out2 $end +$var wire 1 '_ out3 $end +$upscope $end +$scope module OneMux $end +$var wire 1 (_ S0 $end +$var wire 1 )_ S1 $end +$var wire 1 *_ in0 $end +$var wire 1 +_ in1 $end +$var wire 1 ,_ in2 $end +$var wire 1 -_ in3 $end +$var wire 1 ._ nS0 $end +$var wire 1 /_ nS1 $end +$var wire 1 0_ out $end +$var wire 1 1_ out0 $end +$var wire 1 2_ out1 $end +$var wire 1 3_ out2 $end +$var wire 1 4_ out3 $end +$upscope $end +$scope module TwoMux $end +$var wire 1 5_ S $end +$var wire 1 6_ in0 $end +$var wire 1 7_ in1 $end +$var wire 1 8_ nS $end +$var wire 1 9_ out0 $end +$var wire 1 :_ out1 $end +$var wire 1 ;_ outfinal $end +$upscope $end +$upscope $end +$scope begin muxbits[31] $end +$scope module ZeroMux $end +$var wire 1 <_ S0 $end +$var wire 1 =_ S1 $end +$var wire 1 >_ in0 $end +$var wire 1 ?_ in1 $end +$var wire 1 @_ in2 $end +$var wire 1 A_ in3 $end +$var wire 1 B_ nS0 $end +$var wire 1 C_ nS1 $end +$var wire 1 D_ out $end +$var wire 1 E_ out0 $end +$var wire 1 F_ out1 $end +$var wire 1 G_ out2 $end +$var wire 1 H_ out3 $end +$upscope $end +$scope module OneMux $end +$var wire 1 I_ S0 $end +$var wire 1 J_ S1 $end +$var wire 1 K_ in0 $end +$var wire 1 L_ in1 $end +$var wire 1 M_ in2 $end +$var wire 1 N_ in3 $end +$var wire 1 O_ nS0 $end +$var wire 1 P_ nS1 $end +$var wire 1 Q_ out $end +$var wire 1 R_ out0 $end +$var wire 1 S_ out1 $end +$var wire 1 T_ out2 $end +$var wire 1 U_ out3 $end +$upscope $end +$scope module TwoMux $end +$var wire 1 V_ S $end +$var wire 1 W_ in0 $end +$var wire 1 X_ in1 $end +$var wire 1 Y_ nS $end +$var wire 1 Z_ out0 $end +$var wire 1 [_ out1 $end +$var wire 1 \_ outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope module testALU $end +$var wire 32 ]_ AddSubSLTSum [31:0] $end +$var wire 32 ^_ AndNandOut [31:0] $end +$var wire 32 __ Cmd0Start [31:0] $end +$var wire 32 `_ Cmd1Start [31:0] $end +$var wire 32 a_ OrNorXorOut [31:0] $end +$var wire 32 b_ SLTSum [31:0] $end +$var wire 1 c_ SLTflag $end +$var wire 32 d_ ZeroFlag [31:0] $end +$var wire 32 e_ carryin [31:0] $end +$var wire 1 - carryout $end +$var wire 3 f_ command [2:0] $end +$var wire 32 g_ operandA [31:0] $end +$var wire 32 h_ operandB [31:0] $end +$var wire 1 / overflow $end +$var wire 32 i_ result [31:0] $end +$var wire 32 j_ subtract [31:0] $end +$var wire 1 k_ yeszero $end +$var wire 1 # zero $end +$scope module test $end +$var wire 32 l_ A [31:0] $end +$var wire 32 m_ AddSubSLTSum [31:0] $end +$var wire 32 n_ B [31:0] $end +$var wire 32 o_ CarryoutWire [31:0] $end +$var wire 3 p_ Command [2:0] $end +$var wire 32 q_ NewVal [31:0] $end +$var wire 1 r_ Res0OF1 $end +$var wire 1 s_ Res1OF0 $end +$var wire 32 t_ SLTSum [31:0] $end +$var wire 1 c_ SLTflag $end +$var wire 1 u_ SLTflag0 $end +$var wire 1 v_ SLTflag1 $end +$var wire 1 w_ SLTon $end +$var wire 32 x_ carryin [31:0] $end +$var wire 1 - carryout $end +$var wire 1 y_ nAddSubSLTSum $end +$var wire 1 z_ nCmd2 $end +$var wire 1 {_ nOF $end +$var wire 1 / overflow $end +$var wire 32 |_ subtract [31:0] $end +$scope module attempt2 $end +$var wire 1 }_ A $end +$var wire 1 ~_ AandB $end +$var wire 1 !` AddSubSLTSum $end +$var wire 1 "` AxorB $end +$var wire 1 #` B $end +$var wire 1 $` BornB $end +$var wire 1 %` CINandAxorB $end +$var wire 3 &` Command [2:0] $end +$var wire 1 '` carryin $end +$var wire 1 (` carryout $end +$var wire 1 )` nB $end +$var wire 1 *` nCmd2 $end +$var wire 1 +` subtract $end +$scope module mux0 $end +$var wire 1 ,` S $end +$var wire 1 #` in0 $end +$var wire 1 )` in1 $end +$var wire 1 -` nS $end +$var wire 1 .` out0 $end +$var wire 1 /` out1 $end +$var wire 1 $` outfinal $end +$upscope $end +$upscope $end +$scope module setSLTresult $end +$var wire 1 w_ S $end +$var wire 1 0` in0 $end +$var wire 1 1` in1 $end +$var wire 1 2` nS $end +$var wire 1 3` out0 $end +$var wire 1 4` out1 $end +$var wire 1 5` outfinal $end +$upscope $end +$scope module FinalSLT $end +$var wire 1 c_ S $end +$var wire 1 6` in0 $end +$var wire 1 c_ in1 $end +$var wire 1 7` nS $end +$var wire 1 8` out0 $end +$var wire 1 9` out1 $end +$var wire 1 :` outfinal $end +$upscope $end +$scope begin sltbits[1] $end +$scope module attempt $end +$var wire 1 ;` A $end +$var wire 1 <` AandB $end +$var wire 1 =` AddSubSLTSum $end +$var wire 1 >` AxorB $end +$var wire 1 ?` B $end +$var wire 1 @` BornB $end +$var wire 1 A` CINandAxorB $end +$var wire 3 B` Command [2:0] $end +$var wire 1 C` carryin $end +$var wire 1 D` carryout $end +$var wire 1 E` nB $end +$var wire 1 F` nCmd2 $end +$var wire 1 G` subtract $end +$scope module mux0 $end +$var wire 1 H` S $end +$var wire 1 ?` in0 $end +$var wire 1 E` in1 $end +$var wire 1 I` nS $end +$var wire 1 J` out0 $end +$var wire 1 K` out1 $end +$var wire 1 @` outfinal $end +$upscope $end +$upscope $end +$scope module setSLTres2 $end +$var wire 1 w_ S $end +$var wire 1 L` in0 $end +$var wire 1 M` in1 $end +$var wire 1 N` nS $end +$var wire 1 O` out0 $end +$var wire 1 P` out1 $end +$var wire 1 Q` outfinal $end +$upscope $end +$scope module setSLTres3 $end +$var wire 1 w_ S $end +$var wire 1 R` in0 $end +$var wire 1 S` in1 $end +$var wire 1 T` nS $end +$var wire 1 U` out0 $end +$var wire 1 V` out1 $end +$var wire 1 W` outfinal $end +$upscope $end +$upscope $end +$scope begin sltbits[2] $end +$scope module attempt $end +$var wire 1 X` A $end +$var wire 1 Y` AandB $end +$var wire 1 Z` AddSubSLTSum $end +$var wire 1 [` AxorB $end +$var wire 1 \` B $end +$var wire 1 ]` BornB $end +$var wire 1 ^` CINandAxorB $end +$var wire 3 _` Command [2:0] $end +$var wire 1 `` carryin $end +$var wire 1 a` carryout $end +$var wire 1 b` nB $end +$var wire 1 c` nCmd2 $end +$var wire 1 d` subtract $end +$scope module mux0 $end +$var wire 1 e` S $end +$var wire 1 \` in0 $end +$var wire 1 b` in1 $end +$var wire 1 f` nS $end +$var wire 1 g` out0 $end +$var wire 1 h` out1 $end +$var wire 1 ]` outfinal $end +$upscope $end +$upscope $end +$scope module setSLTres2 $end +$var wire 1 w_ S $end +$var wire 1 i` in0 $end +$var wire 1 j` in1 $end +$var wire 1 k` nS $end +$var wire 1 l` out0 $end +$var wire 1 m` out1 $end +$var wire 1 n` outfinal $end +$upscope $end +$scope module setSLTres3 $end +$var wire 1 w_ S $end +$var wire 1 o` in0 $end +$var wire 1 p` in1 $end +$var wire 1 q` nS $end +$var wire 1 r` out0 $end +$var wire 1 s` out1 $end +$var wire 1 t` outfinal $end +$upscope $end +$upscope $end +$scope begin sltbits[3] $end +$scope module attempt $end +$var wire 1 u` A $end +$var wire 1 v` AandB $end +$var wire 1 w` AddSubSLTSum $end +$var wire 1 x` AxorB $end +$var wire 1 y` B $end +$var wire 1 z` BornB $end +$var wire 1 {` CINandAxorB $end +$var wire 3 |` Command [2:0] $end +$var wire 1 }` carryin $end +$var wire 1 ~` carryout $end +$var wire 1 !a nB $end +$var wire 1 "a nCmd2 $end +$var wire 1 #a subtract $end +$scope module mux0 $end +$var wire 1 $a S $end +$var wire 1 y` in0 $end +$var wire 1 !a in1 $end +$var wire 1 %a nS $end +$var wire 1 &a out0 $end +$var wire 1 'a out1 $end +$var wire 1 z` outfinal $end +$upscope $end +$upscope $end +$scope module setSLTres2 $end +$var wire 1 w_ S $end +$var wire 1 (a in0 $end +$var wire 1 )a in1 $end +$var wire 1 *a nS $end +$var wire 1 +a out0 $end +$var wire 1 ,a out1 $end +$var wire 1 -a outfinal $end +$upscope $end +$scope module setSLTres3 $end +$var wire 1 w_ S $end +$var wire 1 .a in0 $end +$var wire 1 /a in1 $end +$var wire 1 0a nS $end +$var wire 1 1a out0 $end +$var wire 1 2a out1 $end +$var wire 1 3a outfinal $end +$upscope $end +$upscope $end +$scope begin sltbits[4] $end +$scope module attempt $end +$var wire 1 4a A $end +$var wire 1 5a AandB $end +$var wire 1 6a AddSubSLTSum $end +$var wire 1 7a AxorB $end +$var wire 1 8a B $end +$var wire 1 9a BornB $end +$var wire 1 :a CINandAxorB $end +$var wire 3 ;a Command [2:0] $end +$var wire 1 a nB $end +$var wire 1 ?a nCmd2 $end +$var wire 1 @a subtract $end +$scope module mux0 $end +$var wire 1 Aa S $end +$var wire 1 8a in0 $end +$var wire 1 >a in1 $end +$var wire 1 Ba nS $end +$var wire 1 Ca out0 $end +$var wire 1 Da out1 $end +$var wire 1 9a outfinal $end +$upscope $end +$upscope $end +$scope module setSLTres2 $end +$var wire 1 w_ S $end +$var wire 1 Ea in0 $end +$var wire 1 Fa in1 $end +$var wire 1 Ga nS $end +$var wire 1 Ha out0 $end +$var wire 1 Ia out1 $end +$var wire 1 Ja outfinal $end +$upscope $end +$scope module setSLTres3 $end +$var wire 1 w_ S $end +$var wire 1 Ka in0 $end +$var wire 1 La in1 $end +$var wire 1 Ma nS $end +$var wire 1 Na out0 $end +$var wire 1 Oa out1 $end +$var wire 1 Pa outfinal $end +$upscope $end +$upscope $end +$scope begin sltbits[5] $end +$scope module attempt $end +$var wire 1 Qa A $end +$var wire 1 Ra AandB $end +$var wire 1 Sa AddSubSLTSum $end +$var wire 1 Ta AxorB $end +$var wire 1 Ua B $end +$var wire 1 Va BornB $end +$var wire 1 Wa CINandAxorB $end +$var wire 3 Xa Command [2:0] $end +$var wire 1 Ya carryin $end +$var wire 1 Za carryout $end +$var wire 1 [a nB $end +$var wire 1 \a nCmd2 $end +$var wire 1 ]a subtract $end +$scope module mux0 $end +$var wire 1 ^a S $end +$var wire 1 Ua in0 $end +$var wire 1 [a in1 $end +$var wire 1 _a nS $end +$var wire 1 `a out0 $end +$var wire 1 aa out1 $end +$var wire 1 Va outfinal $end +$upscope $end +$upscope $end +$scope module setSLTres2 $end +$var wire 1 w_ S $end +$var wire 1 ba in0 $end +$var wire 1 ca in1 $end +$var wire 1 da nS $end +$var wire 1 ea out0 $end +$var wire 1 fa out1 $end +$var wire 1 ga outfinal $end +$upscope $end +$scope module setSLTres3 $end +$var wire 1 w_ S $end +$var wire 1 ha in0 $end +$var wire 1 ia in1 $end +$var wire 1 ja nS $end +$var wire 1 ka out0 $end +$var wire 1 la out1 $end +$var wire 1 ma outfinal $end +$upscope $end +$upscope $end +$scope begin sltbits[6] $end +$scope module attempt $end +$var wire 1 na A $end +$var wire 1 oa AandB $end +$var wire 1 pa AddSubSLTSum $end +$var wire 1 qa AxorB $end +$var wire 1 ra B $end +$var wire 1 sa BornB $end +$var wire 1 ta CINandAxorB $end +$var wire 3 ua Command [2:0] $end +$var wire 1 va carryin $end +$var wire 1 wa carryout $end +$var wire 1 xa nB $end +$var wire 1 ya nCmd2 $end +$var wire 1 za subtract $end +$scope module mux0 $end +$var wire 1 {a S $end +$var wire 1 ra in0 $end +$var wire 1 xa in1 $end +$var wire 1 |a nS $end +$var wire 1 }a out0 $end +$var wire 1 ~a out1 $end +$var wire 1 sa outfinal $end +$upscope $end +$upscope $end +$scope module setSLTres2 $end +$var wire 1 w_ S $end +$var wire 1 !b in0 $end +$var wire 1 "b in1 $end +$var wire 1 #b nS $end +$var wire 1 $b out0 $end +$var wire 1 %b out1 $end +$var wire 1 &b outfinal $end +$upscope $end +$scope module setSLTres3 $end +$var wire 1 w_ S $end +$var wire 1 'b in0 $end +$var wire 1 (b in1 $end +$var wire 1 )b nS $end +$var wire 1 *b out0 $end +$var wire 1 +b out1 $end +$var wire 1 ,b outfinal $end +$upscope $end +$upscope $end +$scope begin sltbits[7] $end +$scope module attempt $end +$var wire 1 -b A $end +$var wire 1 .b AandB $end +$var wire 1 /b AddSubSLTSum $end +$var wire 1 0b AxorB $end +$var wire 1 1b B $end +$var wire 1 2b BornB $end +$var wire 1 3b CINandAxorB $end +$var wire 3 4b Command [2:0] $end +$var wire 1 5b carryin $end +$var wire 1 6b carryout $end +$var wire 1 7b nB $end +$var wire 1 8b nCmd2 $end +$var wire 1 9b subtract $end +$scope module mux0 $end +$var wire 1 :b S $end +$var wire 1 1b in0 $end +$var wire 1 7b in1 $end +$var wire 1 ;b nS $end +$var wire 1 b in0 $end +$var wire 1 ?b in1 $end +$var wire 1 @b nS $end +$var wire 1 Ab out0 $end +$var wire 1 Bb out1 $end +$var wire 1 Cb outfinal $end +$upscope $end +$scope module setSLTres3 $end +$var wire 1 w_ S $end +$var wire 1 Db in0 $end +$var wire 1 Eb in1 $end +$var wire 1 Fb nS $end +$var wire 1 Gb out0 $end +$var wire 1 Hb out1 $end +$var wire 1 Ib outfinal $end +$upscope $end +$upscope $end +$scope begin sltbits[8] $end +$scope module attempt $end +$var wire 1 Jb A $end +$var wire 1 Kb AandB $end +$var wire 1 Lb AddSubSLTSum $end +$var wire 1 Mb AxorB $end +$var wire 1 Nb B $end +$var wire 1 Ob BornB $end +$var wire 1 Pb CINandAxorB $end +$var wire 3 Qb Command [2:0] $end +$var wire 1 Rb carryin $end +$var wire 1 Sb carryout $end +$var wire 1 Tb nB $end +$var wire 1 Ub nCmd2 $end +$var wire 1 Vb subtract $end +$scope module mux0 $end +$var wire 1 Wb S $end +$var wire 1 Nb in0 $end +$var wire 1 Tb in1 $end +$var wire 1 Xb nS $end +$var wire 1 Yb out0 $end +$var wire 1 Zb out1 $end +$var wire 1 Ob outfinal $end +$upscope $end +$upscope $end +$scope module setSLTres2 $end +$var wire 1 w_ S $end +$var wire 1 [b in0 $end +$var wire 1 \b in1 $end +$var wire 1 ]b nS $end +$var wire 1 ^b out0 $end +$var wire 1 _b out1 $end +$var wire 1 `b outfinal $end +$upscope $end +$scope module setSLTres3 $end +$var wire 1 w_ S $end +$var wire 1 ab in0 $end +$var wire 1 bb in1 $end +$var wire 1 cb nS $end +$var wire 1 db out0 $end +$var wire 1 eb out1 $end +$var wire 1 fb outfinal $end +$upscope $end +$upscope $end +$scope begin sltbits[9] $end +$scope module attempt $end +$var wire 1 gb A $end +$var wire 1 hb AandB $end +$var wire 1 ib AddSubSLTSum $end +$var wire 1 jb AxorB $end +$var wire 1 kb B $end +$var wire 1 lb BornB $end +$var wire 1 mb CINandAxorB $end +$var wire 3 nb Command [2:0] $end +$var wire 1 ob carryin $end +$var wire 1 pb carryout $end +$var wire 1 qb nB $end +$var wire 1 rb nCmd2 $end +$var wire 1 sb subtract $end +$scope module mux0 $end +$var wire 1 tb S $end +$var wire 1 kb in0 $end +$var wire 1 qb in1 $end +$var wire 1 ub nS $end +$var wire 1 vb out0 $end +$var wire 1 wb out1 $end +$var wire 1 lb outfinal $end +$upscope $end +$upscope $end +$scope module setSLTres2 $end +$var wire 1 w_ S $end +$var wire 1 xb in0 $end +$var wire 1 yb in1 $end +$var wire 1 zb nS $end +$var wire 1 {b out0 $end +$var wire 1 |b out1 $end +$var wire 1 }b outfinal $end +$upscope $end +$scope module setSLTres3 $end +$var wire 1 w_ S $end +$var wire 1 ~b in0 $end +$var wire 1 !c in1 $end +$var wire 1 "c nS $end +$var wire 1 #c out0 $end +$var wire 1 $c out1 $end +$var wire 1 %c outfinal $end +$upscope $end +$upscope $end +$scope begin sltbits[10] $end +$scope module attempt $end +$var wire 1 &c A $end +$var wire 1 'c AandB $end +$var wire 1 (c AddSubSLTSum $end +$var wire 1 )c AxorB $end +$var wire 1 *c B $end +$var wire 1 +c BornB $end +$var wire 1 ,c CINandAxorB $end +$var wire 3 -c Command [2:0] $end +$var wire 1 .c carryin $end +$var wire 1 /c carryout $end +$var wire 1 0c nB $end +$var wire 1 1c nCmd2 $end +$var wire 1 2c subtract $end +$scope module mux0 $end +$var wire 1 3c S $end +$var wire 1 *c in0 $end +$var wire 1 0c in1 $end +$var wire 1 4c nS $end +$var wire 1 5c out0 $end +$var wire 1 6c out1 $end +$var wire 1 +c outfinal $end +$upscope $end +$upscope $end +$scope module setSLTres2 $end +$var wire 1 w_ S $end +$var wire 1 7c in0 $end +$var wire 1 8c in1 $end +$var wire 1 9c nS $end +$var wire 1 :c out0 $end +$var wire 1 ;c out1 $end +$var wire 1 c in1 $end +$var wire 1 ?c nS $end +$var wire 1 @c out0 $end +$var wire 1 Ac out1 $end +$var wire 1 Bc outfinal $end +$upscope $end +$upscope $end +$scope begin sltbits[11] $end +$scope module attempt $end +$var wire 1 Cc A $end +$var wire 1 Dc AandB $end +$var wire 1 Ec AddSubSLTSum $end +$var wire 1 Fc AxorB $end +$var wire 1 Gc B $end +$var wire 1 Hc BornB $end +$var wire 1 Ic CINandAxorB $end +$var wire 3 Jc Command [2:0] $end +$var wire 1 Kc carryin $end +$var wire 1 Lc carryout $end +$var wire 1 Mc nB $end +$var wire 1 Nc nCmd2 $end +$var wire 1 Oc subtract $end +$scope module mux0 $end +$var wire 1 Pc S $end +$var wire 1 Gc in0 $end +$var wire 1 Mc in1 $end +$var wire 1 Qc nS $end +$var wire 1 Rc out0 $end +$var wire 1 Sc out1 $end +$var wire 1 Hc outfinal $end +$upscope $end +$upscope $end +$scope module setSLTres2 $end +$var wire 1 w_ S $end +$var wire 1 Tc in0 $end +$var wire 1 Uc in1 $end +$var wire 1 Vc nS $end +$var wire 1 Wc out0 $end +$var wire 1 Xc out1 $end +$var wire 1 Yc outfinal $end +$upscope $end +$scope module setSLTres3 $end +$var wire 1 w_ S $end +$var wire 1 Zc in0 $end +$var wire 1 [c in1 $end +$var wire 1 \c nS $end +$var wire 1 ]c out0 $end +$var wire 1 ^c out1 $end +$var wire 1 _c outfinal $end +$upscope $end +$upscope $end +$scope begin sltbits[12] $end +$scope module attempt $end +$var wire 1 `c A $end +$var wire 1 ac AandB $end +$var wire 1 bc AddSubSLTSum $end +$var wire 1 cc AxorB $end +$var wire 1 dc B $end +$var wire 1 ec BornB $end +$var wire 1 fc CINandAxorB $end +$var wire 3 gc Command [2:0] $end +$var wire 1 hc carryin $end +$var wire 1 ic carryout $end +$var wire 1 jc nB $end +$var wire 1 kc nCmd2 $end +$var wire 1 lc subtract $end +$scope module mux0 $end +$var wire 1 mc S $end +$var wire 1 dc in0 $end +$var wire 1 jc in1 $end +$var wire 1 nc nS $end +$var wire 1 oc out0 $end +$var wire 1 pc out1 $end +$var wire 1 ec outfinal $end +$upscope $end +$upscope $end +$scope module setSLTres2 $end +$var wire 1 w_ S $end +$var wire 1 qc in0 $end +$var wire 1 rc in1 $end +$var wire 1 sc nS $end +$var wire 1 tc out0 $end +$var wire 1 uc out1 $end +$var wire 1 vc outfinal $end +$upscope $end +$scope module setSLTres3 $end +$var wire 1 w_ S $end +$var wire 1 wc in0 $end +$var wire 1 xc in1 $end +$var wire 1 yc nS $end +$var wire 1 zc out0 $end +$var wire 1 {c out1 $end +$var wire 1 |c outfinal $end +$upscope $end +$upscope $end +$scope begin sltbits[13] $end +$scope module attempt $end +$var wire 1 }c A $end +$var wire 1 ~c AandB $end +$var wire 1 !d AddSubSLTSum $end +$var wire 1 "d AxorB $end +$var wire 1 #d B $end +$var wire 1 $d BornB $end +$var wire 1 %d CINandAxorB $end +$var wire 3 &d Command [2:0] $end +$var wire 1 'd carryin $end +$var wire 1 (d carryout $end +$var wire 1 )d nB $end +$var wire 1 *d nCmd2 $end +$var wire 1 +d subtract $end +$scope module mux0 $end +$var wire 1 ,d S $end +$var wire 1 #d in0 $end +$var wire 1 )d in1 $end +$var wire 1 -d nS $end +$var wire 1 .d out0 $end +$var wire 1 /d out1 $end +$var wire 1 $d outfinal $end +$upscope $end +$upscope $end +$scope module setSLTres2 $end +$var wire 1 w_ S $end +$var wire 1 0d in0 $end +$var wire 1 1d in1 $end +$var wire 1 2d nS $end +$var wire 1 3d out0 $end +$var wire 1 4d out1 $end +$var wire 1 5d outfinal $end +$upscope $end +$scope module setSLTres3 $end +$var wire 1 w_ S $end +$var wire 1 6d in0 $end +$var wire 1 7d in1 $end +$var wire 1 8d nS $end +$var wire 1 9d out0 $end +$var wire 1 :d out1 $end +$var wire 1 ;d outfinal $end +$upscope $end +$upscope $end +$scope begin sltbits[14] $end +$scope module attempt $end +$var wire 1 d AddSubSLTSum $end +$var wire 1 ?d AxorB $end +$var wire 1 @d B $end +$var wire 1 Ad BornB $end +$var wire 1 Bd CINandAxorB $end +$var wire 3 Cd Command [2:0] $end +$var wire 1 Dd carryin $end +$var wire 1 Ed carryout $end +$var wire 1 Fd nB $end +$var wire 1 Gd nCmd2 $end +$var wire 1 Hd subtract $end +$scope module mux0 $end +$var wire 1 Id S $end +$var wire 1 @d in0 $end +$var wire 1 Fd in1 $end +$var wire 1 Jd nS $end +$var wire 1 Kd out0 $end +$var wire 1 Ld out1 $end +$var wire 1 Ad outfinal $end +$upscope $end +$upscope $end +$scope module setSLTres2 $end +$var wire 1 w_ S $end +$var wire 1 Md in0 $end +$var wire 1 Nd in1 $end +$var wire 1 Od nS $end +$var wire 1 Pd out0 $end +$var wire 1 Qd out1 $end +$var wire 1 Rd outfinal $end +$upscope $end +$scope module setSLTres3 $end +$var wire 1 w_ S $end +$var wire 1 Sd in0 $end +$var wire 1 Td in1 $end +$var wire 1 Ud nS $end +$var wire 1 Vd out0 $end +$var wire 1 Wd out1 $end +$var wire 1 Xd outfinal $end +$upscope $end +$upscope $end +$scope begin sltbits[15] $end +$scope module attempt $end +$var wire 1 Yd A $end +$var wire 1 Zd AandB $end +$var wire 1 [d AddSubSLTSum $end +$var wire 1 \d AxorB $end +$var wire 1 ]d B $end +$var wire 1 ^d BornB $end +$var wire 1 _d CINandAxorB $end +$var wire 3 `d Command [2:0] $end +$var wire 1 ad carryin $end +$var wire 1 bd carryout $end +$var wire 1 cd nB $end +$var wire 1 dd nCmd2 $end +$var wire 1 ed subtract $end +$scope module mux0 $end +$var wire 1 fd S $end +$var wire 1 ]d in0 $end +$var wire 1 cd in1 $end +$var wire 1 gd nS $end +$var wire 1 hd out0 $end +$var wire 1 id out1 $end +$var wire 1 ^d outfinal $end +$upscope $end +$upscope $end +$scope module setSLTres2 $end +$var wire 1 w_ S $end +$var wire 1 jd in0 $end +$var wire 1 kd in1 $end +$var wire 1 ld nS $end +$var wire 1 md out0 $end +$var wire 1 nd out1 $end +$var wire 1 od outfinal $end +$upscope $end +$scope module setSLTres3 $end +$var wire 1 w_ S $end +$var wire 1 pd in0 $end +$var wire 1 qd in1 $end +$var wire 1 rd nS $end +$var wire 1 sd out0 $end +$var wire 1 td out1 $end +$var wire 1 ud outfinal $end +$upscope $end +$upscope $end +$scope begin sltbits[16] $end +$scope module attempt $end +$var wire 1 vd A $end +$var wire 1 wd AandB $end +$var wire 1 xd AddSubSLTSum $end +$var wire 1 yd AxorB $end +$var wire 1 zd B $end +$var wire 1 {d BornB $end +$var wire 1 |d CINandAxorB $end +$var wire 3 }d Command [2:0] $end +$var wire 1 ~d carryin $end +$var wire 1 !e carryout $end +$var wire 1 "e nB $end +$var wire 1 #e nCmd2 $end +$var wire 1 $e subtract $end +$scope module mux0 $end +$var wire 1 %e S $end +$var wire 1 zd in0 $end +$var wire 1 "e in1 $end +$var wire 1 &e nS $end +$var wire 1 'e out0 $end +$var wire 1 (e out1 $end +$var wire 1 {d outfinal $end +$upscope $end +$upscope $end +$scope module setSLTres2 $end +$var wire 1 w_ S $end +$var wire 1 )e in0 $end +$var wire 1 *e in1 $end +$var wire 1 +e nS $end +$var wire 1 ,e out0 $end +$var wire 1 -e out1 $end +$var wire 1 .e outfinal $end +$upscope $end +$scope module setSLTres3 $end +$var wire 1 w_ S $end +$var wire 1 /e in0 $end +$var wire 1 0e in1 $end +$var wire 1 1e nS $end +$var wire 1 2e out0 $end +$var wire 1 3e out1 $end +$var wire 1 4e outfinal $end +$upscope $end +$upscope $end +$scope begin sltbits[17] $end +$scope module attempt $end +$var wire 1 5e A $end +$var wire 1 6e AandB $end +$var wire 1 7e AddSubSLTSum $end +$var wire 1 8e AxorB $end +$var wire 1 9e B $end +$var wire 1 :e BornB $end +$var wire 1 ;e CINandAxorB $end +$var wire 3 e carryout $end +$var wire 1 ?e nB $end +$var wire 1 @e nCmd2 $end +$var wire 1 Ae subtract $end +$scope module mux0 $end +$var wire 1 Be S $end +$var wire 1 9e in0 $end +$var wire 1 ?e in1 $end +$var wire 1 Ce nS $end +$var wire 1 De out0 $end +$var wire 1 Ee out1 $end +$var wire 1 :e outfinal $end +$upscope $end +$upscope $end +$scope module setSLTres2 $end +$var wire 1 w_ S $end +$var wire 1 Fe in0 $end +$var wire 1 Ge in1 $end +$var wire 1 He nS $end +$var wire 1 Ie out0 $end +$var wire 1 Je out1 $end +$var wire 1 Ke outfinal $end +$upscope $end +$scope module setSLTres3 $end +$var wire 1 w_ S $end +$var wire 1 Le in0 $end +$var wire 1 Me in1 $end +$var wire 1 Ne nS $end +$var wire 1 Oe out0 $end +$var wire 1 Pe out1 $end +$var wire 1 Qe outfinal $end +$upscope $end +$upscope $end +$scope begin sltbits[18] $end +$scope module attempt $end +$var wire 1 Re A $end +$var wire 1 Se AandB $end +$var wire 1 Te AddSubSLTSum $end +$var wire 1 Ue AxorB $end +$var wire 1 Ve B $end +$var wire 1 We BornB $end +$var wire 1 Xe CINandAxorB $end +$var wire 3 Ye Command [2:0] $end +$var wire 1 Ze carryin $end +$var wire 1 [e carryout $end +$var wire 1 \e nB $end +$var wire 1 ]e nCmd2 $end +$var wire 1 ^e subtract $end +$scope module mux0 $end +$var wire 1 _e S $end +$var wire 1 Ve in0 $end +$var wire 1 \e in1 $end +$var wire 1 `e nS $end +$var wire 1 ae out0 $end +$var wire 1 be out1 $end +$var wire 1 We outfinal $end +$upscope $end +$upscope $end +$scope module setSLTres2 $end +$var wire 1 w_ S $end +$var wire 1 ce in0 $end +$var wire 1 de in1 $end +$var wire 1 ee nS $end +$var wire 1 fe out0 $end +$var wire 1 ge out1 $end +$var wire 1 he outfinal $end +$upscope $end +$scope module setSLTres3 $end +$var wire 1 w_ S $end +$var wire 1 ie in0 $end +$var wire 1 je in1 $end +$var wire 1 ke nS $end +$var wire 1 le out0 $end +$var wire 1 me out1 $end +$var wire 1 ne outfinal $end +$upscope $end +$upscope $end +$scope begin sltbits[19] $end +$scope module attempt $end +$var wire 1 oe A $end +$var wire 1 pe AandB $end +$var wire 1 qe AddSubSLTSum $end +$var wire 1 re AxorB $end +$var wire 1 se B $end +$var wire 1 te BornB $end +$var wire 1 ue CINandAxorB $end +$var wire 3 ve Command [2:0] $end +$var wire 1 we carryin $end +$var wire 1 xe carryout $end +$var wire 1 ye nB $end +$var wire 1 ze nCmd2 $end +$var wire 1 {e subtract $end +$scope module mux0 $end +$var wire 1 |e S $end +$var wire 1 se in0 $end +$var wire 1 ye in1 $end +$var wire 1 }e nS $end +$var wire 1 ~e out0 $end +$var wire 1 !f out1 $end +$var wire 1 te outfinal $end +$upscope $end +$upscope $end +$scope module setSLTres2 $end +$var wire 1 w_ S $end +$var wire 1 "f in0 $end +$var wire 1 #f in1 $end +$var wire 1 $f nS $end +$var wire 1 %f out0 $end +$var wire 1 &f out1 $end +$var wire 1 'f outfinal $end +$upscope $end +$scope module setSLTres3 $end +$var wire 1 w_ S $end +$var wire 1 (f in0 $end +$var wire 1 )f in1 $end +$var wire 1 *f nS $end +$var wire 1 +f out0 $end +$var wire 1 ,f out1 $end +$var wire 1 -f outfinal $end +$upscope $end +$upscope $end +$scope begin sltbits[20] $end +$scope module attempt $end +$var wire 1 .f A $end +$var wire 1 /f AandB $end +$var wire 1 0f AddSubSLTSum $end +$var wire 1 1f AxorB $end +$var wire 1 2f B $end +$var wire 1 3f BornB $end +$var wire 1 4f CINandAxorB $end +$var wire 3 5f Command [2:0] $end +$var wire 1 6f carryin $end +$var wire 1 7f carryout $end +$var wire 1 8f nB $end +$var wire 1 9f nCmd2 $end +$var wire 1 :f subtract $end +$scope module mux0 $end +$var wire 1 ;f S $end +$var wire 1 2f in0 $end +$var wire 1 8f in1 $end +$var wire 1 f out1 $end +$var wire 1 3f outfinal $end +$upscope $end +$upscope $end +$scope module setSLTres2 $end +$var wire 1 w_ S $end +$var wire 1 ?f in0 $end +$var wire 1 @f in1 $end +$var wire 1 Af nS $end +$var wire 1 Bf out0 $end +$var wire 1 Cf out1 $end +$var wire 1 Df outfinal $end +$upscope $end +$scope module setSLTres3 $end +$var wire 1 w_ S $end +$var wire 1 Ef in0 $end +$var wire 1 Ff in1 $end +$var wire 1 Gf nS $end +$var wire 1 Hf out0 $end +$var wire 1 If out1 $end +$var wire 1 Jf outfinal $end +$upscope $end +$upscope $end +$scope begin sltbits[21] $end +$scope module attempt $end +$var wire 1 Kf A $end +$var wire 1 Lf AandB $end +$var wire 1 Mf AddSubSLTSum $end +$var wire 1 Nf AxorB $end +$var wire 1 Of B $end +$var wire 1 Pf BornB $end +$var wire 1 Qf CINandAxorB $end +$var wire 3 Rf Command [2:0] $end +$var wire 1 Sf carryin $end +$var wire 1 Tf carryout $end +$var wire 1 Uf nB $end +$var wire 1 Vf nCmd2 $end +$var wire 1 Wf subtract $end +$scope module mux0 $end +$var wire 1 Xf S $end +$var wire 1 Of in0 $end +$var wire 1 Uf in1 $end +$var wire 1 Yf nS $end +$var wire 1 Zf out0 $end +$var wire 1 [f out1 $end +$var wire 1 Pf outfinal $end +$upscope $end +$upscope $end +$scope module setSLTres2 $end +$var wire 1 w_ S $end +$var wire 1 \f in0 $end +$var wire 1 ]f in1 $end +$var wire 1 ^f nS $end +$var wire 1 _f out0 $end +$var wire 1 `f out1 $end +$var wire 1 af outfinal $end +$upscope $end +$scope module setSLTres3 $end +$var wire 1 w_ S $end +$var wire 1 bf in0 $end +$var wire 1 cf in1 $end +$var wire 1 df nS $end +$var wire 1 ef out0 $end +$var wire 1 ff out1 $end +$var wire 1 gf outfinal $end +$upscope $end +$upscope $end +$scope begin sltbits[22] $end +$scope module attempt $end +$var wire 1 hf A $end +$var wire 1 if AandB $end +$var wire 1 jf AddSubSLTSum $end +$var wire 1 kf AxorB $end +$var wire 1 lf B $end +$var wire 1 mf BornB $end +$var wire 1 nf CINandAxorB $end +$var wire 3 of Command [2:0] $end +$var wire 1 pf carryin $end +$var wire 1 qf carryout $end +$var wire 1 rf nB $end +$var wire 1 sf nCmd2 $end +$var wire 1 tf subtract $end +$scope module mux0 $end +$var wire 1 uf S $end +$var wire 1 lf in0 $end +$var wire 1 rf in1 $end +$var wire 1 vf nS $end +$var wire 1 wf out0 $end +$var wire 1 xf out1 $end +$var wire 1 mf outfinal $end +$upscope $end +$upscope $end +$scope module setSLTres2 $end +$var wire 1 w_ S $end +$var wire 1 yf in0 $end +$var wire 1 zf in1 $end +$var wire 1 {f nS $end +$var wire 1 |f out0 $end +$var wire 1 }f out1 $end +$var wire 1 ~f outfinal $end +$upscope $end +$scope module setSLTres3 $end +$var wire 1 w_ S $end +$var wire 1 !g in0 $end +$var wire 1 "g in1 $end +$var wire 1 #g nS $end +$var wire 1 $g out0 $end +$var wire 1 %g out1 $end +$var wire 1 &g outfinal $end +$upscope $end +$upscope $end +$scope begin sltbits[23] $end +$scope module attempt $end +$var wire 1 'g A $end +$var wire 1 (g AandB $end +$var wire 1 )g AddSubSLTSum $end +$var wire 1 *g AxorB $end +$var wire 1 +g B $end +$var wire 1 ,g BornB $end +$var wire 1 -g CINandAxorB $end +$var wire 3 .g Command [2:0] $end +$var wire 1 /g carryin $end +$var wire 1 0g carryout $end +$var wire 1 1g nB $end +$var wire 1 2g nCmd2 $end +$var wire 1 3g subtract $end +$scope module mux0 $end +$var wire 1 4g S $end +$var wire 1 +g in0 $end +$var wire 1 1g in1 $end +$var wire 1 5g nS $end +$var wire 1 6g out0 $end +$var wire 1 7g out1 $end +$var wire 1 ,g outfinal $end +$upscope $end +$upscope $end +$scope module setSLTres2 $end +$var wire 1 w_ S $end +$var wire 1 8g in0 $end +$var wire 1 9g in1 $end +$var wire 1 :g nS $end +$var wire 1 ;g out0 $end +$var wire 1 g in0 $end +$var wire 1 ?g in1 $end +$var wire 1 @g nS $end +$var wire 1 Ag out0 $end +$var wire 1 Bg out1 $end +$var wire 1 Cg outfinal $end +$upscope $end +$upscope $end +$scope begin sltbits[24] $end +$scope module attempt $end +$var wire 1 Dg A $end +$var wire 1 Eg AandB $end +$var wire 1 Fg AddSubSLTSum $end +$var wire 1 Gg AxorB $end +$var wire 1 Hg B $end +$var wire 1 Ig BornB $end +$var wire 1 Jg CINandAxorB $end +$var wire 3 Kg Command [2:0] $end +$var wire 1 Lg carryin $end +$var wire 1 Mg carryout $end +$var wire 1 Ng nB $end +$var wire 1 Og nCmd2 $end +$var wire 1 Pg subtract $end +$scope module mux0 $end +$var wire 1 Qg S $end +$var wire 1 Hg in0 $end +$var wire 1 Ng in1 $end +$var wire 1 Rg nS $end +$var wire 1 Sg out0 $end +$var wire 1 Tg out1 $end +$var wire 1 Ig outfinal $end +$upscope $end +$upscope $end +$scope module setSLTres2 $end +$var wire 1 w_ S $end +$var wire 1 Ug in0 $end +$var wire 1 Vg in1 $end +$var wire 1 Wg nS $end +$var wire 1 Xg out0 $end +$var wire 1 Yg out1 $end +$var wire 1 Zg outfinal $end +$upscope $end +$scope module setSLTres3 $end +$var wire 1 w_ S $end +$var wire 1 [g in0 $end +$var wire 1 \g in1 $end +$var wire 1 ]g nS $end +$var wire 1 ^g out0 $end +$var wire 1 _g out1 $end +$var wire 1 `g outfinal $end +$upscope $end +$upscope $end +$scope begin sltbits[25] $end +$scope module attempt $end +$var wire 1 ag A $end +$var wire 1 bg AandB $end +$var wire 1 cg AddSubSLTSum $end +$var wire 1 dg AxorB $end +$var wire 1 eg B $end +$var wire 1 fg BornB $end +$var wire 1 gg CINandAxorB $end +$var wire 3 hg Command [2:0] $end +$var wire 1 ig carryin $end +$var wire 1 jg carryout $end +$var wire 1 kg nB $end +$var wire 1 lg nCmd2 $end +$var wire 1 mg subtract $end +$scope module mux0 $end +$var wire 1 ng S $end +$var wire 1 eg in0 $end +$var wire 1 kg in1 $end +$var wire 1 og nS $end +$var wire 1 pg out0 $end +$var wire 1 qg out1 $end +$var wire 1 fg outfinal $end +$upscope $end +$upscope $end +$scope module setSLTres2 $end +$var wire 1 w_ S $end +$var wire 1 rg in0 $end +$var wire 1 sg in1 $end +$var wire 1 tg nS $end +$var wire 1 ug out0 $end +$var wire 1 vg out1 $end +$var wire 1 wg outfinal $end +$upscope $end +$scope module setSLTres3 $end +$var wire 1 w_ S $end +$var wire 1 xg in0 $end +$var wire 1 yg in1 $end +$var wire 1 zg nS $end +$var wire 1 {g out0 $end +$var wire 1 |g out1 $end +$var wire 1 }g outfinal $end +$upscope $end +$upscope $end +$scope begin sltbits[26] $end +$scope module attempt $end +$var wire 1 ~g A $end +$var wire 1 !h AandB $end +$var wire 1 "h AddSubSLTSum $end +$var wire 1 #h AxorB $end +$var wire 1 $h B $end +$var wire 1 %h BornB $end +$var wire 1 &h CINandAxorB $end +$var wire 3 'h Command [2:0] $end +$var wire 1 (h carryin $end +$var wire 1 )h carryout $end +$var wire 1 *h nB $end +$var wire 1 +h nCmd2 $end +$var wire 1 ,h subtract $end +$scope module mux0 $end +$var wire 1 -h S $end +$var wire 1 $h in0 $end +$var wire 1 *h in1 $end +$var wire 1 .h nS $end +$var wire 1 /h out0 $end +$var wire 1 0h out1 $end +$var wire 1 %h outfinal $end +$upscope $end +$upscope $end +$scope module setSLTres2 $end +$var wire 1 w_ S $end +$var wire 1 1h in0 $end +$var wire 1 2h in1 $end +$var wire 1 3h nS $end +$var wire 1 4h out0 $end +$var wire 1 5h out1 $end +$var wire 1 6h outfinal $end +$upscope $end +$scope module setSLTres3 $end +$var wire 1 w_ S $end +$var wire 1 7h in0 $end +$var wire 1 8h in1 $end +$var wire 1 9h nS $end +$var wire 1 :h out0 $end +$var wire 1 ;h out1 $end +$var wire 1 h AandB $end +$var wire 1 ?h AddSubSLTSum $end +$var wire 1 @h AxorB $end +$var wire 1 Ah B $end +$var wire 1 Bh BornB $end +$var wire 1 Ch CINandAxorB $end +$var wire 3 Dh Command [2:0] $end +$var wire 1 Eh carryin $end +$var wire 1 Fh carryout $end +$var wire 1 Gh nB $end +$var wire 1 Hh nCmd2 $end +$var wire 1 Ih subtract $end +$scope module mux0 $end +$var wire 1 Jh S $end +$var wire 1 Ah in0 $end +$var wire 1 Gh in1 $end +$var wire 1 Kh nS $end +$var wire 1 Lh out0 $end +$var wire 1 Mh out1 $end +$var wire 1 Bh outfinal $end +$upscope $end +$upscope $end +$scope module setSLTres2 $end +$var wire 1 w_ S $end +$var wire 1 Nh in0 $end +$var wire 1 Oh in1 $end +$var wire 1 Ph nS $end +$var wire 1 Qh out0 $end +$var wire 1 Rh out1 $end +$var wire 1 Sh outfinal $end +$upscope $end +$scope module setSLTres3 $end +$var wire 1 w_ S $end +$var wire 1 Th in0 $end +$var wire 1 Uh in1 $end +$var wire 1 Vh nS $end +$var wire 1 Wh out0 $end +$var wire 1 Xh out1 $end +$var wire 1 Yh outfinal $end +$upscope $end +$upscope $end +$scope begin sltbits[28] $end +$scope module attempt $end +$var wire 1 Zh A $end +$var wire 1 [h AandB $end +$var wire 1 \h AddSubSLTSum $end +$var wire 1 ]h AxorB $end +$var wire 1 ^h B $end +$var wire 1 _h BornB $end +$var wire 1 `h CINandAxorB $end +$var wire 3 ah Command [2:0] $end +$var wire 1 bh carryin $end +$var wire 1 ch carryout $end +$var wire 1 dh nB $end +$var wire 1 eh nCmd2 $end +$var wire 1 fh subtract $end +$scope module mux0 $end +$var wire 1 gh S $end +$var wire 1 ^h in0 $end +$var wire 1 dh in1 $end +$var wire 1 hh nS $end +$var wire 1 ih out0 $end +$var wire 1 jh out1 $end +$var wire 1 _h outfinal $end +$upscope $end +$upscope $end +$scope module setSLTres2 $end +$var wire 1 w_ S $end +$var wire 1 kh in0 $end +$var wire 1 lh in1 $end +$var wire 1 mh nS $end +$var wire 1 nh out0 $end +$var wire 1 oh out1 $end +$var wire 1 ph outfinal $end +$upscope $end +$scope module setSLTres3 $end +$var wire 1 w_ S $end +$var wire 1 qh in0 $end +$var wire 1 rh in1 $end +$var wire 1 sh nS $end +$var wire 1 th out0 $end +$var wire 1 uh out1 $end +$var wire 1 vh outfinal $end +$upscope $end +$upscope $end +$scope begin sltbits[29] $end +$scope module attempt $end +$var wire 1 wh A $end +$var wire 1 xh AandB $end +$var wire 1 yh AddSubSLTSum $end +$var wire 1 zh AxorB $end +$var wire 1 {h B $end +$var wire 1 |h BornB $end +$var wire 1 }h CINandAxorB $end +$var wire 3 ~h Command [2:0] $end +$var wire 1 !i carryin $end +$var wire 1 "i carryout $end +$var wire 1 #i nB $end +$var wire 1 $i nCmd2 $end +$var wire 1 %i subtract $end +$scope module mux0 $end +$var wire 1 &i S $end +$var wire 1 {h in0 $end +$var wire 1 #i in1 $end +$var wire 1 'i nS $end +$var wire 1 (i out0 $end +$var wire 1 )i out1 $end +$var wire 1 |h outfinal $end +$upscope $end +$upscope $end +$scope module setSLTres2 $end +$var wire 1 w_ S $end +$var wire 1 *i in0 $end +$var wire 1 +i in1 $end +$var wire 1 ,i nS $end +$var wire 1 -i out0 $end +$var wire 1 .i out1 $end +$var wire 1 /i outfinal $end +$upscope $end +$scope module setSLTres3 $end +$var wire 1 w_ S $end +$var wire 1 0i in0 $end +$var wire 1 1i in1 $end +$var wire 1 2i nS $end +$var wire 1 3i out0 $end +$var wire 1 4i out1 $end +$var wire 1 5i outfinal $end +$upscope $end +$upscope $end +$scope begin sltbits[30] $end +$scope module attempt $end +$var wire 1 6i A $end +$var wire 1 7i AandB $end +$var wire 1 8i AddSubSLTSum $end +$var wire 1 9i AxorB $end +$var wire 1 :i B $end +$var wire 1 ;i BornB $end +$var wire 1 i carryin $end +$var wire 1 ?i carryout $end +$var wire 1 @i nB $end +$var wire 1 Ai nCmd2 $end +$var wire 1 Bi subtract $end +$scope module mux0 $end +$var wire 1 Ci S $end +$var wire 1 :i in0 $end +$var wire 1 @i in1 $end +$var wire 1 Di nS $end +$var wire 1 Ei out0 $end +$var wire 1 Fi out1 $end +$var wire 1 ;i outfinal $end +$upscope $end +$upscope $end +$scope module setSLTres2 $end +$var wire 1 w_ S $end +$var wire 1 Gi in0 $end +$var wire 1 Hi in1 $end +$var wire 1 Ii nS $end +$var wire 1 Ji out0 $end +$var wire 1 Ki out1 $end +$var wire 1 Li outfinal $end +$upscope $end +$scope module setSLTres3 $end +$var wire 1 w_ S $end +$var wire 1 Mi in0 $end +$var wire 1 Ni in1 $end +$var wire 1 Oi nS $end +$var wire 1 Pi out0 $end +$var wire 1 Qi out1 $end +$var wire 1 Ri outfinal $end +$upscope $end +$upscope $end +$scope begin sltbits[31] $end +$scope module attempt $end +$var wire 1 Si A $end +$var wire 1 Ti AandB $end +$var wire 1 Ui AddSubSLTSum $end +$var wire 1 Vi AxorB $end +$var wire 1 Wi B $end +$var wire 1 Xi BornB $end +$var wire 1 Yi CINandAxorB $end +$var wire 3 Zi Command [2:0] $end +$var wire 1 [i carryin $end +$var wire 1 \i carryout $end +$var wire 1 ]i nB $end +$var wire 1 ^i nCmd2 $end +$var wire 1 _i subtract $end +$scope module mux0 $end +$var wire 1 `i S $end +$var wire 1 Wi in0 $end +$var wire 1 ]i in1 $end +$var wire 1 ai nS $end +$var wire 1 bi out0 $end +$var wire 1 ci out1 $end +$var wire 1 Xi outfinal $end +$upscope $end +$upscope $end +$scope module setSLTres2 $end +$var wire 1 w_ S $end +$var wire 1 di in0 $end +$var wire 1 ei in1 $end +$var wire 1 fi nS $end +$var wire 1 gi out0 $end +$var wire 1 hi out1 $end +$var wire 1 ii outfinal $end +$upscope $end +$scope module setSLTres3 $end +$var wire 1 w_ S $end +$var wire 1 ji in0 $end +$var wire 1 ki in1 $end +$var wire 1 li nS $end +$var wire 1 mi out0 $end +$var wire 1 ni out1 $end +$var wire 1 oi outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope module trial $end +$var wire 32 pi A [31:0] $end +$var wire 32 qi AddSubSLTSum [31:0] $end +$var wire 32 ri B [31:0] $end +$var wire 32 si CarryoutWire [31:0] $end +$var wire 3 ti Command [2:0] $end +$var wire 32 ui carryin [31:0] $end +$var wire 1 - carryout $end +$var wire 1 / overflow $end +$var wire 32 vi subtract [31:0] $end +$scope module attempt2 $end +$var wire 1 wi A $end +$var wire 1 xi AandB $end +$var wire 1 yi AddSubSLTSum $end +$var wire 1 zi AxorB $end +$var wire 1 {i B $end +$var wire 1 |i BornB $end +$var wire 1 }i CINandAxorB $end +$var wire 3 ~i Command [2:0] $end +$var wire 1 !j carryin $end +$var wire 1 "j carryout $end +$var wire 1 #j nB $end +$var wire 1 $j nCmd2 $end +$var wire 1 %j subtract $end +$scope module mux0 $end +$var wire 1 &j S $end +$var wire 1 {i in0 $end +$var wire 1 #j in1 $end +$var wire 1 'j nS $end +$var wire 1 (j out0 $end +$var wire 1 )j out1 $end +$var wire 1 |i outfinal $end +$upscope $end +$upscope $end +$scope begin addbits[1] $end +$scope module attempt $end +$var wire 1 *j A $end +$var wire 1 +j AandB $end +$var wire 1 ,j AddSubSLTSum $end +$var wire 1 -j AxorB $end +$var wire 1 .j B $end +$var wire 1 /j BornB $end +$var wire 1 0j CINandAxorB $end +$var wire 3 1j Command [2:0] $end +$var wire 1 2j carryin $end +$var wire 1 3j carryout $end +$var wire 1 4j nB $end +$var wire 1 5j nCmd2 $end +$var wire 1 6j subtract $end +$scope module mux0 $end +$var wire 1 7j S $end +$var wire 1 .j in0 $end +$var wire 1 4j in1 $end +$var wire 1 8j nS $end +$var wire 1 9j out0 $end +$var wire 1 :j out1 $end +$var wire 1 /j outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin addbits[2] $end +$scope module attempt $end +$var wire 1 ;j A $end +$var wire 1 j AxorB $end +$var wire 1 ?j B $end +$var wire 1 @j BornB $end +$var wire 1 Aj CINandAxorB $end +$var wire 3 Bj Command [2:0] $end +$var wire 1 Cj carryin $end +$var wire 1 Dj carryout $end +$var wire 1 Ej nB $end +$var wire 1 Fj nCmd2 $end +$var wire 1 Gj subtract $end +$scope module mux0 $end +$var wire 1 Hj S $end +$var wire 1 ?j in0 $end +$var wire 1 Ej in1 $end +$var wire 1 Ij nS $end +$var wire 1 Jj out0 $end +$var wire 1 Kj out1 $end +$var wire 1 @j outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin addbits[3] $end +$scope module attempt $end +$var wire 1 Lj A $end +$var wire 1 Mj AandB $end +$var wire 1 Nj AddSubSLTSum $end +$var wire 1 Oj AxorB $end +$var wire 1 Pj B $end +$var wire 1 Qj BornB $end +$var wire 1 Rj CINandAxorB $end +$var wire 3 Sj Command [2:0] $end +$var wire 1 Tj carryin $end +$var wire 1 Uj carryout $end +$var wire 1 Vj nB $end +$var wire 1 Wj nCmd2 $end +$var wire 1 Xj subtract $end +$scope module mux0 $end +$var wire 1 Yj S $end +$var wire 1 Pj in0 $end +$var wire 1 Vj in1 $end +$var wire 1 Zj nS $end +$var wire 1 [j out0 $end +$var wire 1 \j out1 $end +$var wire 1 Qj outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin addbits[4] $end +$scope module attempt $end +$var wire 1 ]j A $end +$var wire 1 ^j AandB $end +$var wire 1 _j AddSubSLTSum $end +$var wire 1 `j AxorB $end +$var wire 1 aj B $end +$var wire 1 bj BornB $end +$var wire 1 cj CINandAxorB $end +$var wire 3 dj Command [2:0] $end +$var wire 1 ej carryin $end +$var wire 1 fj carryout $end +$var wire 1 gj nB $end +$var wire 1 hj nCmd2 $end +$var wire 1 ij subtract $end +$scope module mux0 $end +$var wire 1 jj S $end +$var wire 1 aj in0 $end +$var wire 1 gj in1 $end +$var wire 1 kj nS $end +$var wire 1 lj out0 $end +$var wire 1 mj out1 $end +$var wire 1 bj outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin addbits[5] $end +$scope module attempt $end +$var wire 1 nj A $end +$var wire 1 oj AandB $end +$var wire 1 pj AddSubSLTSum $end +$var wire 1 qj AxorB $end +$var wire 1 rj B $end +$var wire 1 sj BornB $end +$var wire 1 tj CINandAxorB $end +$var wire 3 uj Command [2:0] $end +$var wire 1 vj carryin $end +$var wire 1 wj carryout $end +$var wire 1 xj nB $end +$var wire 1 yj nCmd2 $end +$var wire 1 zj subtract $end +$scope module mux0 $end +$var wire 1 {j S $end +$var wire 1 rj in0 $end +$var wire 1 xj in1 $end +$var wire 1 |j nS $end +$var wire 1 }j out0 $end +$var wire 1 ~j out1 $end +$var wire 1 sj outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin addbits[6] $end +$scope module attempt $end +$var wire 1 !k A $end +$var wire 1 "k AandB $end +$var wire 1 #k AddSubSLTSum $end +$var wire 1 $k AxorB $end +$var wire 1 %k B $end +$var wire 1 &k BornB $end +$var wire 1 'k CINandAxorB $end +$var wire 3 (k Command [2:0] $end +$var wire 1 )k carryin $end +$var wire 1 *k carryout $end +$var wire 1 +k nB $end +$var wire 1 ,k nCmd2 $end +$var wire 1 -k subtract $end +$scope module mux0 $end +$var wire 1 .k S $end +$var wire 1 %k in0 $end +$var wire 1 +k in1 $end +$var wire 1 /k nS $end +$var wire 1 0k out0 $end +$var wire 1 1k out1 $end +$var wire 1 &k outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin addbits[7] $end +$scope module attempt $end +$var wire 1 2k A $end +$var wire 1 3k AandB $end +$var wire 1 4k AddSubSLTSum $end +$var wire 1 5k AxorB $end +$var wire 1 6k B $end +$var wire 1 7k BornB $end +$var wire 1 8k CINandAxorB $end +$var wire 3 9k Command [2:0] $end +$var wire 1 :k carryin $end +$var wire 1 ;k carryout $end +$var wire 1 k subtract $end +$scope module mux0 $end +$var wire 1 ?k S $end +$var wire 1 6k in0 $end +$var wire 1 l B $end +$var wire 1 ?l BornB $end +$var wire 1 @l CINandAxorB $end +$var wire 3 Al Command [2:0] $end +$var wire 1 Bl carryin $end +$var wire 1 Cl carryout $end +$var wire 1 Dl nB $end +$var wire 1 El nCmd2 $end +$var wire 1 Fl subtract $end +$scope module mux0 $end +$var wire 1 Gl S $end +$var wire 1 >l in0 $end +$var wire 1 Dl in1 $end +$var wire 1 Hl nS $end +$var wire 1 Il out0 $end +$var wire 1 Jl out1 $end +$var wire 1 ?l outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin addbits[14] $end +$scope module attempt $end +$var wire 1 Kl A $end +$var wire 1 Ll AandB $end +$var wire 1 Ml AddSubSLTSum $end +$var wire 1 Nl AxorB $end +$var wire 1 Ol B $end +$var wire 1 Pl BornB $end +$var wire 1 Ql CINandAxorB $end +$var wire 3 Rl Command [2:0] $end +$var wire 1 Sl carryin $end +$var wire 1 Tl carryout $end +$var wire 1 Ul nB $end +$var wire 1 Vl nCmd2 $end +$var wire 1 Wl subtract $end +$scope module mux0 $end +$var wire 1 Xl S $end +$var wire 1 Ol in0 $end +$var wire 1 Ul in1 $end +$var wire 1 Yl nS $end +$var wire 1 Zl out0 $end +$var wire 1 [l out1 $end +$var wire 1 Pl outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin addbits[15] $end +$scope module attempt $end +$var wire 1 \l A $end +$var wire 1 ]l AandB $end +$var wire 1 ^l AddSubSLTSum $end +$var wire 1 _l AxorB $end +$var wire 1 `l B $end +$var wire 1 al BornB $end +$var wire 1 bl CINandAxorB $end +$var wire 3 cl Command [2:0] $end +$var wire 1 dl carryin $end +$var wire 1 el carryout $end +$var wire 1 fl nB $end +$var wire 1 gl nCmd2 $end +$var wire 1 hl subtract $end +$scope module mux0 $end +$var wire 1 il S $end +$var wire 1 `l in0 $end +$var wire 1 fl in1 $end +$var wire 1 jl nS $end +$var wire 1 kl out0 $end +$var wire 1 ll out1 $end +$var wire 1 al outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin addbits[16] $end +$scope module attempt $end +$var wire 1 ml A $end +$var wire 1 nl AandB $end +$var wire 1 ol AddSubSLTSum $end +$var wire 1 pl AxorB $end +$var wire 1 ql B $end +$var wire 1 rl BornB $end +$var wire 1 sl CINandAxorB $end +$var wire 3 tl Command [2:0] $end +$var wire 1 ul carryin $end +$var wire 1 vl carryout $end +$var wire 1 wl nB $end +$var wire 1 xl nCmd2 $end +$var wire 1 yl subtract $end +$scope module mux0 $end +$var wire 1 zl S $end +$var wire 1 ql in0 $end +$var wire 1 wl in1 $end +$var wire 1 {l nS $end +$var wire 1 |l out0 $end +$var wire 1 }l out1 $end +$var wire 1 rl outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin addbits[17] $end +$scope module attempt $end +$var wire 1 ~l A $end +$var wire 1 !m AandB $end +$var wire 1 "m AddSubSLTSum $end +$var wire 1 #m AxorB $end +$var wire 1 $m B $end +$var wire 1 %m BornB $end +$var wire 1 &m CINandAxorB $end +$var wire 3 'm Command [2:0] $end +$var wire 1 (m carryin $end +$var wire 1 )m carryout $end +$var wire 1 *m nB $end +$var wire 1 +m nCmd2 $end +$var wire 1 ,m subtract $end +$scope module mux0 $end +$var wire 1 -m S $end +$var wire 1 $m in0 $end +$var wire 1 *m in1 $end +$var wire 1 .m nS $end +$var wire 1 /m out0 $end +$var wire 1 0m out1 $end +$var wire 1 %m outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin addbits[18] $end +$scope module attempt $end +$var wire 1 1m A $end +$var wire 1 2m AandB $end +$var wire 1 3m AddSubSLTSum $end +$var wire 1 4m AxorB $end +$var wire 1 5m B $end +$var wire 1 6m BornB $end +$var wire 1 7m CINandAxorB $end +$var wire 3 8m Command [2:0] $end +$var wire 1 9m carryin $end +$var wire 1 :m carryout $end +$var wire 1 ;m nB $end +$var wire 1 m S $end +$var wire 1 5m in0 $end +$var wire 1 ;m in1 $end +$var wire 1 ?m nS $end +$var wire 1 @m out0 $end +$var wire 1 Am out1 $end +$var wire 1 6m outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin addbits[19] $end +$scope module attempt $end +$var wire 1 Bm A $end +$var wire 1 Cm AandB $end +$var wire 1 Dm AddSubSLTSum $end +$var wire 1 Em AxorB $end +$var wire 1 Fm B $end +$var wire 1 Gm BornB $end +$var wire 1 Hm CINandAxorB $end +$var wire 3 Im Command [2:0] $end +$var wire 1 Jm carryin $end +$var wire 1 Km carryout $end +$var wire 1 Lm nB $end +$var wire 1 Mm nCmd2 $end +$var wire 1 Nm subtract $end +$scope module mux0 $end +$var wire 1 Om S $end +$var wire 1 Fm in0 $end +$var wire 1 Lm in1 $end +$var wire 1 Pm nS $end +$var wire 1 Qm out0 $end +$var wire 1 Rm out1 $end +$var wire 1 Gm outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin addbits[20] $end +$scope module attempt $end +$var wire 1 Sm A $end +$var wire 1 Tm AandB $end +$var wire 1 Um AddSubSLTSum $end +$var wire 1 Vm AxorB $end +$var wire 1 Wm B $end +$var wire 1 Xm BornB $end +$var wire 1 Ym CINandAxorB $end +$var wire 3 Zm Command [2:0] $end +$var wire 1 [m carryin $end +$var wire 1 \m carryout $end +$var wire 1 ]m nB $end +$var wire 1 ^m nCmd2 $end +$var wire 1 _m subtract $end +$scope module mux0 $end +$var wire 1 `m S $end +$var wire 1 Wm in0 $end +$var wire 1 ]m in1 $end +$var wire 1 am nS $end +$var wire 1 bm out0 $end +$var wire 1 cm out1 $end +$var wire 1 Xm outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin addbits[21] $end +$scope module attempt $end +$var wire 1 dm A $end +$var wire 1 em AandB $end +$var wire 1 fm AddSubSLTSum $end +$var wire 1 gm AxorB $end +$var wire 1 hm B $end +$var wire 1 im BornB $end +$var wire 1 jm CINandAxorB $end +$var wire 3 km Command [2:0] $end +$var wire 1 lm carryin $end +$var wire 1 mm carryout $end +$var wire 1 nm nB $end +$var wire 1 om nCmd2 $end +$var wire 1 pm subtract $end +$scope module mux0 $end +$var wire 1 qm S $end +$var wire 1 hm in0 $end +$var wire 1 nm in1 $end +$var wire 1 rm nS $end +$var wire 1 sm out0 $end +$var wire 1 tm out1 $end +$var wire 1 im outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin addbits[22] $end +$scope module attempt $end +$var wire 1 um A $end +$var wire 1 vm AandB $end +$var wire 1 wm AddSubSLTSum $end +$var wire 1 xm AxorB $end +$var wire 1 ym B $end +$var wire 1 zm BornB $end +$var wire 1 {m CINandAxorB $end +$var wire 3 |m Command [2:0] $end +$var wire 1 }m carryin $end +$var wire 1 ~m carryout $end +$var wire 1 !n nB $end +$var wire 1 "n nCmd2 $end +$var wire 1 #n subtract $end +$scope module mux0 $end +$var wire 1 $n S $end +$var wire 1 ym in0 $end +$var wire 1 !n in1 $end +$var wire 1 %n nS $end +$var wire 1 &n out0 $end +$var wire 1 'n out1 $end +$var wire 1 zm outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin addbits[23] $end +$scope module attempt $end +$var wire 1 (n A $end +$var wire 1 )n AandB $end +$var wire 1 *n AddSubSLTSum $end +$var wire 1 +n AxorB $end +$var wire 1 ,n B $end +$var wire 1 -n BornB $end +$var wire 1 .n CINandAxorB $end +$var wire 3 /n Command [2:0] $end +$var wire 1 0n carryin $end +$var wire 1 1n carryout $end +$var wire 1 2n nB $end +$var wire 1 3n nCmd2 $end +$var wire 1 4n subtract $end +$scope module mux0 $end +$var wire 1 5n S $end +$var wire 1 ,n in0 $end +$var wire 1 2n in1 $end +$var wire 1 6n nS $end +$var wire 1 7n out0 $end +$var wire 1 8n out1 $end +$var wire 1 -n outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin addbits[24] $end +$scope module attempt $end +$var wire 1 9n A $end +$var wire 1 :n AandB $end +$var wire 1 ;n AddSubSLTSum $end +$var wire 1 n BornB $end +$var wire 1 ?n CINandAxorB $end +$var wire 3 @n Command [2:0] $end +$var wire 1 An carryin $end +$var wire 1 Bn carryout $end +$var wire 1 Cn nB $end +$var wire 1 Dn nCmd2 $end +$var wire 1 En subtract $end +$scope module mux0 $end +$var wire 1 Fn S $end +$var wire 1 =n in0 $end +$var wire 1 Cn in1 $end +$var wire 1 Gn nS $end +$var wire 1 Hn out0 $end +$var wire 1 In out1 $end +$var wire 1 >n outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin addbits[25] $end +$scope module attempt $end +$var wire 1 Jn A $end +$var wire 1 Kn AandB $end +$var wire 1 Ln AddSubSLTSum $end +$var wire 1 Mn AxorB $end +$var wire 1 Nn B $end +$var wire 1 On BornB $end +$var wire 1 Pn CINandAxorB $end +$var wire 3 Qn Command [2:0] $end +$var wire 1 Rn carryin $end +$var wire 1 Sn carryout $end +$var wire 1 Tn nB $end +$var wire 1 Un nCmd2 $end +$var wire 1 Vn subtract $end +$scope module mux0 $end +$var wire 1 Wn S $end +$var wire 1 Nn in0 $end +$var wire 1 Tn in1 $end +$var wire 1 Xn nS $end +$var wire 1 Yn out0 $end +$var wire 1 Zn out1 $end +$var wire 1 On outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin addbits[26] $end +$scope module attempt $end +$var wire 1 [n A $end +$var wire 1 \n AandB $end +$var wire 1 ]n AddSubSLTSum $end +$var wire 1 ^n AxorB $end +$var wire 1 _n B $end +$var wire 1 `n BornB $end +$var wire 1 an CINandAxorB $end +$var wire 3 bn Command [2:0] $end +$var wire 1 cn carryin $end +$var wire 1 dn carryout $end +$var wire 1 en nB $end +$var wire 1 fn nCmd2 $end +$var wire 1 gn subtract $end +$scope module mux0 $end +$var wire 1 hn S $end +$var wire 1 _n in0 $end +$var wire 1 en in1 $end +$var wire 1 in nS $end +$var wire 1 jn out0 $end +$var wire 1 kn out1 $end +$var wire 1 `n outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin addbits[27] $end +$scope module attempt $end +$var wire 1 ln A $end +$var wire 1 mn AandB $end +$var wire 1 nn AddSubSLTSum $end +$var wire 1 on AxorB $end +$var wire 1 pn B $end +$var wire 1 qn BornB $end +$var wire 1 rn CINandAxorB $end +$var wire 3 sn Command [2:0] $end +$var wire 1 tn carryin $end +$var wire 1 un carryout $end +$var wire 1 vn nB $end +$var wire 1 wn nCmd2 $end +$var wire 1 xn subtract $end +$scope module mux0 $end +$var wire 1 yn S $end +$var wire 1 pn in0 $end +$var wire 1 vn in1 $end +$var wire 1 zn nS $end +$var wire 1 {n out0 $end +$var wire 1 |n out1 $end +$var wire 1 qn outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin addbits[28] $end +$scope module attempt $end +$var wire 1 }n A $end +$var wire 1 ~n AandB $end +$var wire 1 !o AddSubSLTSum $end +$var wire 1 "o AxorB $end +$var wire 1 #o B $end +$var wire 1 $o BornB $end +$var wire 1 %o CINandAxorB $end +$var wire 3 &o Command [2:0] $end +$var wire 1 'o carryin $end +$var wire 1 (o carryout $end +$var wire 1 )o nB $end +$var wire 1 *o nCmd2 $end +$var wire 1 +o subtract $end +$scope module mux0 $end +$var wire 1 ,o S $end +$var wire 1 #o in0 $end +$var wire 1 )o in1 $end +$var wire 1 -o nS $end +$var wire 1 .o out0 $end +$var wire 1 /o out1 $end +$var wire 1 $o outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin addbits[29] $end +$scope module attempt $end +$var wire 1 0o A $end +$var wire 1 1o AandB $end +$var wire 1 2o AddSubSLTSum $end +$var wire 1 3o AxorB $end +$var wire 1 4o B $end +$var wire 1 5o BornB $end +$var wire 1 6o CINandAxorB $end +$var wire 3 7o Command [2:0] $end +$var wire 1 8o carryin $end +$var wire 1 9o carryout $end +$var wire 1 :o nB $end +$var wire 1 ;o nCmd2 $end +$var wire 1 o nS $end +$var wire 1 ?o out0 $end +$var wire 1 @o out1 $end +$var wire 1 5o outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin addbits[30] $end +$scope module attempt $end +$var wire 1 Ao A $end +$var wire 1 Bo AandB $end +$var wire 1 Co AddSubSLTSum $end +$var wire 1 Do AxorB $end +$var wire 1 Eo B $end +$var wire 1 Fo BornB $end +$var wire 1 Go CINandAxorB $end +$var wire 3 Ho Command [2:0] $end +$var wire 1 Io carryin $end +$var wire 1 Jo carryout $end +$var wire 1 Ko nB $end +$var wire 1 Lo nCmd2 $end +$var wire 1 Mo subtract $end +$scope module mux0 $end +$var wire 1 No S $end +$var wire 1 Eo in0 $end +$var wire 1 Ko in1 $end +$var wire 1 Oo nS $end +$var wire 1 Po out0 $end +$var wire 1 Qo out1 $end +$var wire 1 Fo outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin addbits[31] $end +$scope module attempt $end +$var wire 1 Ro A $end +$var wire 1 So AandB $end +$var wire 1 To AddSubSLTSum $end +$var wire 1 Uo AxorB $end +$var wire 1 Vo B $end +$var wire 1 Wo BornB $end +$var wire 1 Xo CINandAxorB $end +$var wire 3 Yo Command [2:0] $end +$var wire 1 Zo carryin $end +$var wire 1 [o carryout $end +$var wire 1 \o nB $end +$var wire 1 ]o nCmd2 $end +$var wire 1 ^o subtract $end +$scope module mux0 $end +$var wire 1 _o S $end +$var wire 1 Vo in0 $end +$var wire 1 \o in1 $end +$var wire 1 `o nS $end +$var wire 1 ao out0 $end +$var wire 1 bo out1 $end +$var wire 1 Wo outfinal $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope module trial1 $end +$var wire 32 co A [31:0] $end +$var wire 32 do AndNandOut [31:0] $end +$var wire 32 eo B [31:0] $end +$var wire 3 fo Command [2:0] $end +$scope module attempt2 $end +$var wire 1 go A $end +$var wire 1 ho AandB $end +$var wire 1 io AnandB $end +$var wire 1 jo AndNandOut $end +$var wire 1 ko B $end +$var wire 3 lo Command [2:0] $end +$scope module potato $end +$var wire 1 mo S $end +$var wire 1 ho in0 $end +$var wire 1 io in1 $end +$var wire 1 no nS $end +$var wire 1 oo out0 $end +$var wire 1 po out1 $end +$var wire 1 jo outfinal $end +$upscope $end +$upscope $end +$scope begin andbits[1] $end +$scope module attempt $end +$var wire 1 qo A $end +$var wire 1 ro AandB $end +$var wire 1 so AnandB $end +$var wire 1 to AndNandOut $end +$var wire 1 uo B $end +$var wire 3 vo Command [2:0] $end +$scope module potato $end +$var wire 1 wo S $end +$var wire 1 ro in0 $end +$var wire 1 so in1 $end +$var wire 1 xo nS $end +$var wire 1 yo out0 $end +$var wire 1 zo out1 $end +$var wire 1 to outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin andbits[2] $end +$scope module attempt $end +$var wire 1 {o A $end +$var wire 1 |o AandB $end +$var wire 1 }o AnandB $end +$var wire 1 ~o AndNandOut $end +$var wire 1 !p B $end +$var wire 3 "p Command [2:0] $end +$scope module potato $end +$var wire 1 #p S $end +$var wire 1 |o in0 $end +$var wire 1 }o in1 $end +$var wire 1 $p nS $end +$var wire 1 %p out0 $end +$var wire 1 &p out1 $end +$var wire 1 ~o outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin andbits[3] $end +$scope module attempt $end +$var wire 1 'p A $end +$var wire 1 (p AandB $end +$var wire 1 )p AnandB $end +$var wire 1 *p AndNandOut $end +$var wire 1 +p B $end +$var wire 3 ,p Command [2:0] $end +$scope module potato $end +$var wire 1 -p S $end +$var wire 1 (p in0 $end +$var wire 1 )p in1 $end +$var wire 1 .p nS $end +$var wire 1 /p out0 $end +$var wire 1 0p out1 $end +$var wire 1 *p outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin andbits[4] $end +$scope module attempt $end +$var wire 1 1p A $end +$var wire 1 2p AandB $end +$var wire 1 3p AnandB $end +$var wire 1 4p AndNandOut $end +$var wire 1 5p B $end +$var wire 3 6p Command [2:0] $end +$scope module potato $end +$var wire 1 7p S $end +$var wire 1 2p in0 $end +$var wire 1 3p in1 $end +$var wire 1 8p nS $end +$var wire 1 9p out0 $end +$var wire 1 :p out1 $end +$var wire 1 4p outfinal $end +$upscope $end +$upscope $end +$upscope $end +$scope begin andbits[5] $end +$scope module attempt $end +$var wire 1 ;p A $end +$var wire 1