diff --git a/Lab1 report.pdf b/Lab1 report.pdf new file mode 100644 index 0000000..84f7467 Binary files /dev/null and b/Lab1 report.pdf differ diff --git a/adder.t.v b/adder.t.v new file mode 100644 index 0000000..15be0b5 --- /dev/null +++ b/adder.t.v @@ -0,0 +1,89 @@ +`timescale 1 ns / 1 ps +`include "adder.v" + +module test4BitFullAdder(); + reg[3:0] a; //Bus for a registers. + reg[3:0] b; //Bus for b registers. + wire[3:0] sum; //Bus for the individual sums. + wire carryout; //final carryout wire. + wire carryout2; + wire overflow; //Overflow wire. + + FullAdder4bit adder(sum, carryout, carryout2, overflow, a, b); + + initial begin + $dumpfile("fulladder.vcd"); + $dumpvars(0, a[3:0], b[3:0], sum[3:0], carryout, carryout2, overflow); + + + $display(" a | b | S C2 | COut | OverFlow | Sum | ECout | EOvrflow"); + a = 0; //Set register a. + b = 0; //Set register b. + #1000 //Delay. + $display(" %d | %d | %d %b | %b | %b | 0 | 0 | 0 ", $signed(a), $signed(b), $signed(sum), carryout2, carryout, overflow); + a = -1; + b = -1; + #1000 + $display(" %d | %d | %d %b | %b | %b | -2 | 1 | 0 ", $signed(a), $signed(b), $signed(sum), carryout2, carryout, overflow); + a = 1; + b = 1; + #1000 + $display(" %d | %d | %d %b | %b | %b | 2 | 0 | 0 ", $signed(a), $signed(b), $signed(sum), carryout2, carryout, overflow); + a = 7; + b = -7; + #1000 + $display(" %d | %d | %d %b | %b | %b | 0 | 1 | 0 ", $signed(a), $signed(b), $signed(sum), carryout2, carryout, overflow); + a = 6; + b = -2; + #1000 + $display(" %d | %d | %d %b | %b | %b | 4 | 1 | 0 ", $signed(a), $signed(b), $signed(sum), carryout2, carryout, overflow); + a = 6; + b = 5; + #1000 + $display(" %d | %d | %d %b | %b | %b |11(-5)| 0 | 1 ", $signed(a), $signed(b), $signed(sum), carryout2, carryout, overflow); + a = 5; + b = -7; + #1000 + $display(" %d | %d | %d %b | %b | %b | -2 | 0 | 0 ", $signed(a), $signed(b), $signed(sum), carryout2, carryout, overflow); + a = 7; + b = 3; + #1000 + $display(" %d | %d | %d %b | %b | %b |10(-6)| 0 | 1 ", $signed(a), $signed(b), $signed(sum), carryout2, carryout, overflow); + a = -5; + b = -5; + #1000 + $display(" %d | %d | %d %b | %b | %b |-10(6)| 1 | 1 ", $signed(a), $signed(b), $signed(sum), carryout2, carryout, overflow); + a = -8; + b = -8; + #1000 + $display(" %d | %d | %d %b | %b | %b |-16(0)| 1 | 1 ", $signed(a), $signed(b), $signed(sum), carryout2, carryout, overflow); + a = 7; + b = -8; + #1000 + $display(" %d | %d | %d %b | %b | %b | -1 | 0 | 0 ", $signed(a), $signed(b), $signed(sum), carryout2, carryout, overflow); + a = 7; + b = 7; + #1000 + $display(" %d | %d | %d %b | %b | %b |14(-2)| 0 | 1 ", $signed(a), $signed(b), $signed(sum), carryout2, carryout, overflow); + a = 5; + b = 2; + #1000 + $display(" %d | %d | %d %b | %b | %b | 7 | 0 | 0 ", $signed(a), $signed(b), $signed(sum), carryout2, carryout, overflow); + a = 5; + b = 3; + #1000 + $display(" %d | %d | %d %b | %b | %b |8(-8) | 0 | 1 ", $signed(a), $signed(b), $signed(sum), carryout2, carryout, overflow); + a = -5; + b = -3; + #1000 + $display(" %d | %d | %d %b | %b | %b | -8 | 1 | 0 ", $signed(a), $signed(b), $signed(sum), carryout2, carryout, overflow); + a = -5; + b = -4; + #1000 + $display(" %d | %d | %d %b | %b | %b |-9(7) | 1 | 1 ", $signed(a), $signed(b), $signed(sum), carryout2, carryout, overflow); + + //end + //end + + end +endmodule diff --git a/adder.v b/adder.v new file mode 100644 index 0000000..b6cfd34 --- /dev/null +++ b/adder.v @@ -0,0 +1,44 @@ +`define AND and #30 +`define OR or #30 +`define XOR xor #50 + +// Adder circuit + +module structFullAdder +( + output sum, + output carryout, + input a, + input b, + input carryin +); + wire AxorB; + wire AandB; + wire AxorBandCarryIn; + + `XOR (AxorB, a, b); + `XOR (sum, AxorB, carryin); + `AND (AandB, a, b); + `AND (AxorBandCarryIn, AxorB, carryin); + `OR (carryout, AxorBandCarryIn, AandB); +endmodule + +module FullAdder4bit +( + output[3:0] sum, // 2's complement sum of a and b + output carryout, carryout2, // Carry out of the summation of a and b + output overflow, // True if the calculation resulted in an overflow + input[3:0] a, // First operand in 2's complement format + input[3:0] b // Second operand in 2's complement format +); + + wire carryout0; //Carryout of first adder. + wire carryout1; //Carryout of second adder. + + structFullAdder a0(sum[0], carryout0, a[0], b[0], 1'b0); //Structural Full Adder with specific initial values. + structFullAdder a1(sum[1], carryout1, a[1], b[1], carryout0); + structFullAdder a2(sum[2], carryout2, a[2], b[2], carryout1); + structFullAdder a3(sum[3], carryout, a[3], b[3], carryout2); + + `XOR (overflow, carryout2, carryout); //XOR handles overflow. +endmodule diff --git a/alu b/alu new file mode 100644 index 0000000..dbc0bca --- /dev/null +++ b/alu @@ -0,0 +1,4725 @@ +#! c:/iverilog-x64/bin/vvp +:ivl_version "10.1 (stable)" "(v10_1_1)"; +:ivl_delay_selection "TYPICAL"; +:vpi_time_precision - 12; +:vpi_module "system"; +:vpi_module "vhdl_sys"; +:vpi_module "v2005_math"; +:vpi_module "va_math"; +S_0000000000dcf580 .scope module, "FullAdder4bit" "FullAdder4bit" 2 26; + .timescale -9 -12; + .port_info 0 /OUTPUT 4 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /OUTPUT 1 "carryout2" + .port_info 3 /OUTPUT 1 "overflow" + .port_info 4 /INPUT 4 "a" + .port_info 5 /INPUT 4 "b" +L_0000000000eb2f50/d .functor XOR 1, L_0000000000eb3b20, L_0000000000eb2af0, C4<0>, C4<0>; +L_0000000000eb2f50 .delay 1 (50000,50000,50000) L_0000000000eb2f50/d; +o0000000000f25898 .functor BUFZ 4, C4; HiZ drive +v0000000000e9af40_0 .net "a", 3 0, o0000000000f25898; 0 drivers +o0000000000f258c8 .functor BUFZ 4, C4; HiZ drive +v0000000000e9b800_0 .net "b", 3 0, o0000000000f258c8; 0 drivers +v0000000000e9b8a0_0 .net "carryout", 0 0, L_0000000000eb2af0; 1 drivers +v0000000000e9b940_0 .net "carryout0", 0 0, L_0000000000eb3030; 1 drivers +v0000000000e9bc60_0 .net "carryout1", 0 0, L_0000000000eb2930; 1 drivers +v0000000000e9c0c0_0 .net "carryout2", 0 0, L_0000000000eb3b20; 1 drivers +v0000000000e9f0e0_0 .net "overflow", 0 0, L_0000000000eb2f50; 1 drivers +v0000000000e9d4c0_0 .net "sum", 3 0, L_00000000027919c0; 1 drivers +L_00000000027908e0 .part o0000000000f25898, 0, 1; +L_00000000027923c0 .part o0000000000f258c8, 0, 1; +L_0000000002792000 .part o0000000000f25898, 1, 1; +L_0000000002790c00 .part o0000000000f258c8, 1, 1; +L_0000000002792140 .part o0000000000f25898, 2, 1; +L_00000000027928c0 .part o0000000000f258c8, 2, 1; +L_00000000027919c0 .concat8 [ 1 1 1 1], L_0000000000eb32d0, L_0000000000eb2a80, L_0000000000eb3960, L_0000000000eb3c70; +L_0000000002791f60 .part o0000000000f25898, 3, 1; +L_0000000002790e80 .part o0000000000f258c8, 3, 1; +S_0000000000cd8870 .scope module, "a0" "structFullAdder" 2 38, 2 7 0, S_0000000000dcf580; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "carryin" +L_0000000000eb2ee0/d .functor XOR 1, L_00000000027908e0, L_00000000027923c0, C4<0>, C4<0>; +L_0000000000eb2ee0 .delay 1 (50000,50000,50000) L_0000000000eb2ee0/d; +L_00000000027a00f8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0000000000eb32d0/d .functor XOR 1, L_0000000000eb2ee0, L_00000000027a00f8, C4<0>, C4<0>; +L_0000000000eb32d0 .delay 1 (50000,50000,50000) L_0000000000eb32d0/d; +L_0000000000eb3340/d .functor AND 1, L_00000000027908e0, L_00000000027923c0, C4<1>, C4<1>; +L_0000000000eb3340 .delay 1 (30000,30000,30000) L_0000000000eb3340/d; +L_0000000000eb2bd0/d .functor AND 1, L_0000000000eb2ee0, L_00000000027a00f8, C4<1>, C4<1>; +L_0000000000eb2bd0 .delay 1 (30000,30000,30000) L_0000000000eb2bd0/d; +L_0000000000eb3030/d .functor OR 1, L_0000000000eb2bd0, L_0000000000eb3340, C4<0>, C4<0>; +L_0000000000eb3030 .delay 1 (30000,30000,30000) L_0000000000eb3030/d; +v0000000000e9b300_0 .net "AandB", 0 0, L_0000000000eb3340; 1 drivers +v0000000000e9b1c0_0 .net "AxorB", 0 0, L_0000000000eb2ee0; 1 drivers +v0000000000e9a540_0 .net "AxorBandCarryIn", 0 0, L_0000000000eb2bd0; 1 drivers +v0000000000e9c520_0 .net "a", 0 0, L_00000000027908e0; 1 drivers +v0000000000e9b4e0_0 .net "b", 0 0, L_00000000027923c0; 1 drivers +v0000000000e9ad60_0 .net "carryin", 0 0, L_00000000027a00f8; 1 drivers +v0000000000e9c340_0 .net "carryout", 0 0, L_0000000000eb3030; alias, 1 drivers +v0000000000e9c980_0 .net "sum", 0 0, L_0000000000eb32d0; 1 drivers +S_0000000000cc1560 .scope module, "a1" "structFullAdder" 2 39, 2 7 0, S_0000000000dcf580; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "carryin" +L_0000000000eb4140/d .functor XOR 1, L_0000000002792000, L_0000000002790c00, C4<0>, C4<0>; +L_0000000000eb4140 .delay 1 (50000,50000,50000) L_0000000000eb4140/d; +L_0000000000eb2a80/d .functor XOR 1, L_0000000000eb4140, L_0000000000eb3030, C4<0>, C4<0>; +L_0000000000eb2a80 .delay 1 (50000,50000,50000) L_0000000000eb2a80/d; +L_0000000000eb3650/d .functor AND 1, L_0000000002792000, L_0000000002790c00, C4<1>, C4<1>; +L_0000000000eb3650 .delay 1 (30000,30000,30000) L_0000000000eb3650/d; +L_0000000000eb3c00/d .functor AND 1, L_0000000000eb4140, L_0000000000eb3030, C4<1>, C4<1>; +L_0000000000eb3c00 .delay 1 (30000,30000,30000) L_0000000000eb3c00/d; +L_0000000000eb2930/d .functor OR 1, L_0000000000eb3c00, L_0000000000eb3650, C4<0>, C4<0>; +L_0000000000eb2930 .delay 1 (30000,30000,30000) L_0000000000eb2930/d; +v0000000000e9bee0_0 .net "AandB", 0 0, L_0000000000eb3650; 1 drivers +v0000000000e9c160_0 .net "AxorB", 0 0, L_0000000000eb4140; 1 drivers +v0000000000e9bf80_0 .net "AxorBandCarryIn", 0 0, L_0000000000eb3c00; 1 drivers +v0000000000e9c700_0 .net "a", 0 0, L_0000000002792000; 1 drivers +v0000000000e9b080_0 .net "b", 0 0, L_0000000002790c00; 1 drivers +v0000000000e9a860_0 .net "carryin", 0 0, L_0000000000eb3030; alias, 1 drivers +v0000000000e9c020_0 .net "carryout", 0 0, L_0000000000eb2930; alias, 1 drivers +v0000000000e9c7a0_0 .net "sum", 0 0, L_0000000000eb2a80; 1 drivers +S_0000000000cc16e0 .scope module, "a2" "structFullAdder" 2 40, 2 7 0, S_0000000000dcf580; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "carryin" +L_0000000000eb29a0/d .functor XOR 1, L_0000000002792140, L_00000000027928c0, C4<0>, C4<0>; +L_0000000000eb29a0 .delay 1 (50000,50000,50000) L_0000000000eb29a0/d; +L_0000000000eb3960/d .functor XOR 1, L_0000000000eb29a0, L_0000000000eb2930, C4<0>, C4<0>; +L_0000000000eb3960 .delay 1 (50000,50000,50000) L_0000000000eb3960/d; +L_0000000000eb2e70/d .functor AND 1, L_0000000002792140, L_00000000027928c0, C4<1>, C4<1>; +L_0000000000eb2e70 .delay 1 (30000,30000,30000) L_0000000000eb2e70/d; +L_0000000000eb33b0/d .functor AND 1, L_0000000000eb29a0, L_0000000000eb2930, C4<1>, C4<1>; +L_0000000000eb33b0 .delay 1 (30000,30000,30000) L_0000000000eb33b0/d; +L_0000000000eb3b20/d .functor OR 1, L_0000000000eb33b0, L_0000000000eb2e70, C4<0>, C4<0>; +L_0000000000eb3b20 .delay 1 (30000,30000,30000) L_0000000000eb3b20/d; +v0000000000e9c840_0 .net "AandB", 0 0, L_0000000000eb2e70; 1 drivers +v0000000000e9b9e0_0 .net "AxorB", 0 0, L_0000000000eb29a0; 1 drivers +v0000000000e9c3e0_0 .net "AxorBandCarryIn", 0 0, L_0000000000eb33b0; 1 drivers +v0000000000e9aea0_0 .net "a", 0 0, L_0000000002792140; 1 drivers +v0000000000e9bbc0_0 .net "b", 0 0, L_00000000027928c0; 1 drivers +v0000000000e9ca20_0 .net "carryin", 0 0, L_0000000000eb2930; alias, 1 drivers +v0000000000e9b3a0_0 .net "carryout", 0 0, L_0000000000eb3b20; alias, 1 drivers +v0000000000e9a900_0 .net "sum", 0 0, L_0000000000eb3960; 1 drivers +S_0000000000cc7310 .scope module, "a3" "structFullAdder" 2 41, 2 7 0, S_0000000000dcf580; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "carryin" +L_0000000000eb44c0/d .functor XOR 1, L_0000000002791f60, L_0000000002790e80, C4<0>, C4<0>; +L_0000000000eb44c0 .delay 1 (50000,50000,50000) L_0000000000eb44c0/d; +L_0000000000eb3c70/d .functor XOR 1, L_0000000000eb44c0, L_0000000000eb3b20, C4<0>, C4<0>; +L_0000000000eb3c70 .delay 1 (50000,50000,50000) L_0000000000eb3c70/d; +L_0000000000eb30a0/d .functor AND 1, L_0000000002791f60, L_0000000002790e80, C4<1>, C4<1>; +L_0000000000eb30a0 .delay 1 (30000,30000,30000) L_0000000000eb30a0/d; +L_0000000000eb3110/d .functor AND 1, L_0000000000eb44c0, L_0000000000eb3b20, C4<1>, C4<1>; +L_0000000000eb3110 .delay 1 (30000,30000,30000) L_0000000000eb3110/d; +L_0000000000eb2af0/d .functor OR 1, L_0000000000eb3110, L_0000000000eb30a0, C4<0>, C4<0>; +L_0000000000eb2af0 .delay 1 (30000,30000,30000) L_0000000000eb2af0/d; +v0000000000e9b760_0 .net "AandB", 0 0, L_0000000000eb30a0; 1 drivers +v0000000000e9aae0_0 .net "AxorB", 0 0, L_0000000000eb44c0; 1 drivers +v0000000000e9a4a0_0 .net "AxorBandCarryIn", 0 0, L_0000000000eb3110; 1 drivers +v0000000000e9ba80_0 .net "a", 0 0, L_0000000002791f60; 1 drivers +v0000000000e9b580_0 .net "b", 0 0, L_0000000002790e80; 1 drivers +v0000000000e9acc0_0 .net "carryin", 0 0, L_0000000000eb3b20; alias, 1 drivers +v0000000000e9ae00_0 .net "carryout", 0 0, L_0000000000eb2af0; alias, 1 drivers +v0000000000e9c480_0 .net "sum", 0 0, L_0000000000eb3c70; 1 drivers +S_0000000000cd86f0 .scope module, "testALU" "testALU" 3 15; + .timescale -9 -12; +v0000000002791920_0 .net "carryout", 0 0, L_000000000282d390; 1 drivers +v0000000002790a20_0 .var "command", 2 0; +v0000000002790660_0 .var/s "operandA", 31 0; +v0000000002790b60_0 .var/s "operandB", 31 0; +v0000000002792320_0 .net "overflow", 0 0, L_000000000282c130; 1 drivers +v0000000002791ec0_0 .net/s "result", 31 0, L_000000000282fb30; 1 drivers +v0000000002790700_0 .net "zero", 0 0, L_000000000282c440; 1 drivers +S_0000000000cc7490 .scope module, "alu" "ALU" 3 24, 4 13 0, S_0000000000cd86f0; + .timescale -9 -12; + .port_info 0 /OUTPUT 32 "result" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /OUTPUT 1 "zero" + .port_info 3 /OUTPUT 1 "overflow" + .port_info 4 /INPUT 32 "operandA" + .port_info 5 /INPUT 32 "operandB" + .port_info 6 /INPUT 3 "command" +L_000000000282bf70/d .functor XOR 1, L_000000000279d9a0, v0000000000e68bd0_0, C4<0>, C4<0>; +L_000000000282bf70 .delay 1 (20000,20000,20000) L_000000000282bf70/d; +L_000000000282c830/d .functor AND 1, v0000000000e67370_0, L_000000000279de00, C4<1>, C4<1>; +L_000000000282c830 .delay 1 (30000,30000,30000) L_000000000282c830/d; +L_000000000282c750/d .functor NOT 1, L_000000000279ffc0, C4<0>, C4<0>, C4<0>; +L_000000000282c750 .delay 1 (10000,10000,10000) L_000000000282c750/d; +L_000000000282c280/d .functor NAND 1, L_000000000279fb60, L_000000000279f5c0, L_000000000279f700, C4<1>; +L_000000000282c280 .delay 1 (30000,30000,30000) L_000000000282c280/d; +L_000000000282d0f0/d .functor NOT 1, L_000000000282c280, C4<0>, C4<0>, C4<0>; +L_000000000282d0f0 .delay 1 (10000,10000,10000) L_000000000282d0f0/d; +L_000000000282bf00/d .functor AND 1, L_000000000279f7a0, L_000000000282c280, C4<1>, C4<1>; +L_000000000282bf00 .delay 1 (30000,30000,30000) L_000000000282bf00/d; +L_000000000282d940/d .functor XOR 1, L_000000000279f520, L_000000000279fde0, C4<0>, C4<0>; +L_000000000282d940 .delay 1 (20000,20000,20000) L_000000000282d940/d; +L_000000000282cec0/d .functor OR 1, L_000000000279fac0, L_000000000279f8e0, C4<0>, C4<0>; +L_000000000282cec0 .delay 1 (30000,30000,30000) L_000000000282cec0/d; +L_000000000282d630/d .functor NOT 1, L_000000000279f980, C4<0>, C4<0>, C4<0>; +L_000000000282d630 .delay 1 (10000,10000,10000) L_000000000282d630/d; +L_000000000282cb40/d .functor NOT 1, L_000000000279f160, C4<0>, C4<0>, C4<0>; +L_000000000282cb40 .delay 1 (10000,10000,10000) L_000000000282cb40/d; +L_000000000282c440/d .functor AND 1, L_000000000282d630, L_000000000279fa20, L_000000000279fd40, C4<1>; +L_000000000282c440 .delay 1 (40000,40000,40000) L_000000000282c440/d; +L_000000000282d390/d .functor AND 1, L_000000000279f2a0, L_000000000282fbd0, L_000000000282e5f0, C4<1>; +L_000000000282d390 .delay 1 (40000,40000,40000) L_000000000282d390/d; +L_000000000282c130/d .functor AND 1, L_000000000282d940, L_000000000282e730, L_000000000282f450, C4<1>; +L_000000000282c130 .delay 1 (40000,40000,40000) L_000000000282c130/d; +L_000000000282d400/d .functor XOR 1, L_000000000282d940, L_0000000002830990, C4<0>, C4<0>; +L_000000000282d400 .delay 1 (20000,20000,20000) L_000000000282d400/d; +L_000000000282c210/d .functor AND 1, L_000000000282d400, L_000000000282d0f0, C4<1>, C4<1>; +L_000000000282c210 .delay 1 (30000,30000,30000) L_000000000282c210/d; +L_000000000282d8d0/d .functor OR 1, L_000000000282bf00, L_000000000282c210, C4<0>, C4<0>; +L_000000000282d8d0 .delay 1 (30000,30000,30000) L_000000000282d8d0/d; +v0000000002783440_0 .net *"_s0", 0 0, L_0000000000eb3490; 1 drivers +v0000000002783580_0 .net *"_s102", 0 0, L_00000000027ed660; 1 drivers +v0000000002783ee0_0 .net *"_s105", 0 0, L_00000000027ed6d0; 1 drivers +v0000000002783da0_0 .net *"_s116", 0 0, L_00000000027ede40; 1 drivers +v00000000027838a0_0 .net *"_s119", 0 0, L_00000000027edf20; 1 drivers +v0000000002783620_0 .net *"_s122", 0 0, L_00000000027f6f10; 1 drivers +v00000000027836c0_0 .net *"_s133", 0 0, L_00000000027f7610; 1 drivers +v0000000002783f80_0 .net *"_s136", 0 0, L_00000000027f6960; 1 drivers +v0000000002783bc0_0 .net *"_s139", 0 0, L_00000000027f6d50; 1 drivers +v0000000002783a80_0 .net *"_s14", 0 0, L_0000000000eb2c40; 1 drivers +v0000000002783760_0 .net *"_s150", 0 0, L_00000000027f7300; 1 drivers +v0000000002783800_0 .net *"_s153", 0 0, L_00000000027f7840; 1 drivers +v0000000002783940_0 .net *"_s156", 0 0, L_00000000027f6dc0; 1 drivers +v00000000027839e0_0 .net *"_s167", 0 0, L_00000000027f7290; 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+L_0000000002795f20 .part v0000000002790b60_0, 13, 1; +L_0000000002795660 .part L_000000000279f3e0, 12, 1; +L_0000000002795480 .part v0000000002790660_0, 13, 1; +L_0000000002796380 .part L_000000000279d540, 13, 1; +L_0000000002796e20 .part L_000000000279dae0, 13, 1; +L_0000000002797460 .part v0000000002790a20_0, 0, 1; +L_0000000002797640 .part L_000000000279fca0, 13, 1; +L_00000000027964c0 .part v0000000002790b60_0, 14, 1; +L_0000000002796600 .part L_000000000279f3e0, 13, 1; +L_0000000002795d40 .part v0000000002790660_0, 14, 1; +L_00000000027953e0 .part L_000000000279d540, 14, 1; +L_00000000027978c0 .part L_000000000279dae0, 14, 1; +L_00000000027976e0 .part v0000000002790a20_0, 0, 1; +L_0000000002795160 .part L_000000000279fca0, 14, 1; +L_0000000002795e80 .part v0000000002790b60_0, 15, 1; +L_0000000002795fc0 .part L_000000000279f3e0, 14, 1; +L_00000000027973c0 .part v0000000002790660_0, 15, 1; +L_0000000002796920 .part L_000000000279d540, 15, 1; +L_0000000002796ec0 .part L_000000000279dae0, 15, 1; +L_0000000002797320 .part v0000000002790a20_0, 0, 1; +L_0000000002797780 .part L_000000000279fca0, 15, 1; +L_00000000027952a0 .part v0000000002790b60_0, 16, 1; +L_0000000002796740 .part L_000000000279f3e0, 15, 1; +L_0000000002796b00 .part v0000000002790660_0, 16, 1; +L_0000000002796f60 .part L_000000000279d540, 16, 1; +L_0000000002797500 .part L_000000000279dae0, 16, 1; +L_00000000027970a0 .part v0000000002790a20_0, 0, 1; +L_0000000002795700 .part L_000000000279fca0, 16, 1; +L_0000000002797000 .part v0000000002790b60_0, 17, 1; +L_0000000002795340 .part L_000000000279f3e0, 16, 1; +L_00000000027971e0 .part v0000000002790660_0, 17, 1; +L_0000000002795520 .part L_000000000279d540, 17, 1; +L_00000000027955c0 .part L_000000000279dae0, 17, 1; +L_0000000002797d20 .part v0000000002790a20_0, 0, 1; +L_00000000027999e0 .part L_000000000279fca0, 17, 1; +L_00000000027989a0 .part v0000000002790b60_0, 18, 1; +L_0000000002797fa0 .part L_000000000279f3e0, 17, 1; +L_0000000002799a80 .part v0000000002790660_0, 18, 1; +L_00000000027987c0 .part L_000000000279d540, 18, 1; +L_0000000002798680 .part L_000000000279dae0, 18, 1; +L_0000000002798040 .part v0000000002790a20_0, 0, 1; +L_0000000002799440 .part L_000000000279fca0, 18, 1; +L_00000000027994e0 .part v0000000002790b60_0, 19, 1; +L_0000000002799b20 .part L_000000000279f3e0, 18, 1; +L_0000000002798220 .part v0000000002790660_0, 19, 1; +L_0000000002798180 .part L_000000000279d540, 19, 1; +L_0000000002799da0 .part L_000000000279dae0, 19, 1; +L_0000000002798c20 .part v0000000002790a20_0, 0, 1; +L_0000000002797f00 .part L_000000000279fca0, 19, 1; +L_0000000002799c60 .part v0000000002790b60_0, 20, 1; +L_00000000027982c0 .part L_000000000279f3e0, 19, 1; +L_0000000002798900 .part v0000000002790660_0, 20, 1; +L_0000000002798720 .part L_000000000279d540, 20, 1; +L_0000000002797a00 .part L_000000000279dae0, 20, 1; +L_0000000002799620 .part v0000000002790a20_0, 0, 1; +L_0000000002798360 .part L_000000000279fca0, 20, 1; +L_0000000002798860 .part v0000000002790b60_0, 21, 1; +L_0000000002797e60 .part L_000000000279f3e0, 20, 1; +L_0000000002798a40 .part v0000000002790660_0, 21, 1; +L_0000000002798ae0 .part L_000000000279d540, 21, 1; +L_0000000002797c80 .part L_000000000279dae0, 21, 1; +L_0000000002798b80 .part v0000000002790a20_0, 0, 1; +L_0000000002799080 .part L_000000000279fca0, 21, 1; +L_0000000002798d60 .part v0000000002790b60_0, 22, 1; +L_000000000279a0c0 .part L_000000000279f3e0, 21, 1; +L_0000000002798e00 .part v0000000002790660_0, 22, 1; +L_0000000002798f40 .part L_000000000279d540, 22, 1; +L_0000000002799260 .part L_000000000279dae0, 22, 1; +L_0000000002798400 .part v0000000002790a20_0, 0, 1; +L_00000000027991c0 .part L_000000000279fca0, 22, 1; +L_0000000002799ee0 .part v0000000002790b60_0, 23, 1; +L_0000000002798fe0 .part L_000000000279f3e0, 22, 1; +L_00000000027996c0 .part v0000000002790660_0, 23, 1; +L_0000000002797aa0 .part L_000000000279d540, 23, 1; +L_00000000027993a0 .part L_000000000279dae0, 23, 1; +L_00000000027984a0 .part v0000000002790a20_0, 0, 1; +L_0000000002799760 .part L_000000000279fca0, 23, 1; +L_0000000002799800 .part v0000000002790b60_0, 24, 1; +L_00000000027998a0 .part L_000000000279f3e0, 23, 1; +L_0000000002799f80 .part v0000000002790660_0, 24, 1; +L_0000000002799940 .part L_000000000279d540, 24, 1; +L_0000000002797dc0 .part L_000000000279dae0, 24, 1; +L_00000000027980e0 .part v0000000002790a20_0, 0, 1; +L_000000000279afc0 .part L_000000000279fca0, 24, 1; +L_000000000279ab60 .part v0000000002790b60_0, 25, 1; +L_000000000279ba60 .part L_000000000279f3e0, 24, 1; +L_000000000279a660 .part v0000000002790660_0, 25, 1; +L_000000000279c140 .part L_000000000279d540, 25, 1; +L_000000000279b240 .part L_000000000279dae0, 25, 1; +L_000000000279c8c0 .part v0000000002790a20_0, 0, 1; +L_000000000279a160 .part L_000000000279fca0, 25, 1; +L_000000000279bb00 .part v0000000002790b60_0, 26, 1; +L_000000000279b060 .part L_000000000279f3e0, 25, 1; +L_000000000279a5c0 .part v0000000002790660_0, 26, 1; +L_000000000279c320 .part L_000000000279d540, 26, 1; +L_000000000279c780 .part L_000000000279dae0, 26, 1; +L_000000000279a840 .part v0000000002790a20_0, 0, 1; +L_000000000279ade0 .part L_000000000279fca0, 26, 1; +L_000000000279bc40 .part v0000000002790b60_0, 27, 1; +L_000000000279bce0 .part L_000000000279f3e0, 26, 1; +L_000000000279a520 .part v0000000002790660_0, 27, 1; +L_000000000279a8e0 .part L_000000000279d540, 27, 1; +L_000000000279a980 .part L_000000000279dae0, 27, 1; +L_000000000279b420 .part v0000000002790a20_0, 0, 1; +L_000000000279c280 .part L_000000000279fca0, 27, 1; +L_000000000279a700 .part v0000000002790b60_0, 28, 1; +L_000000000279c460 .part L_000000000279f3e0, 27, 1; +L_000000000279b4c0 .part v0000000002790660_0, 28, 1; +L_000000000279a200 .part L_000000000279d540, 28, 1; +L_000000000279b6a0 .part L_000000000279dae0, 28, 1; +L_000000000279b1a0 .part v0000000002790a20_0, 0, 1; +L_000000000279a2a0 .part L_000000000279fca0, 28, 1; +L_000000000279ac00 .part v0000000002790b60_0, 29, 1; +L_000000000279af20 .part L_000000000279f3e0, 28, 1; +L_000000000279c500 .part v0000000002790660_0, 29, 1; +L_000000000279b2e0 .part L_000000000279d540, 29, 1; +L_000000000279b600 .part L_000000000279dae0, 29, 1; +L_000000000279c0a0 .part v0000000002790a20_0, 0, 1; +L_000000000279a480 .part L_000000000279fca0, 29, 1; +L_000000000279b920 .part v0000000002790b60_0, 30, 1; +L_000000000279b740 .part L_000000000279f3e0, 29, 1; +L_000000000279c3c0 .part v0000000002790660_0, 30, 1; +L_000000000279bd80 .part L_000000000279d540, 30, 1; +L_000000000279c5a0 .part L_000000000279dae0, 30, 1; +L_000000000279aac0 .part v0000000002790a20_0, 0, 1; +L_000000000279bba0 .part L_000000000279fca0, 30, 1; +L_000000000279b9c0 .part v0000000002790b60_0, 31, 1; +L_000000000279be20 .part L_000000000279f3e0, 30, 1; +L_000000000279c640 .part v0000000002790660_0, 31, 1; +L_000000000279a3e0 .part L_000000000279d540, 31, 1; +L_000000000279bf60 .part L_000000000279dae0, 31, 1; +L_000000000279c6e0 .part v0000000002790a20_0, 0, 1; +L_000000000279c820 .part L_000000000279fca0, 31, 1; +L_000000000279ee40 .part L_000000000282fb30, 1, 1; +L_000000000279d680 .part L_000000000279f840, 0, 1; +L_000000000279db80 .part L_000000000282fb30, 2, 1; +L_000000000279e620 .part L_000000000279f840, 1, 1; +L_000000000279e440 .part L_000000000282fb30, 3, 1; +L_000000000279e580 .part L_000000000279f840, 2, 1; +L_000000000279ce60 .part L_000000000282fb30, 4, 1; +L_000000000279da40 .part L_000000000279f840, 3, 1; +L_000000000279e4e0 .part L_000000000282fb30, 5, 1; +L_000000000279e260 .part L_000000000279f840, 4, 1; +L_000000000279e6c0 .part L_000000000282fb30, 6, 1; +L_000000000279d180 .part L_000000000279f840, 5, 1; +L_000000000279e940 .part L_000000000282fb30, 7, 1; +L_000000000279eda0 .part L_000000000279f840, 6, 1; +L_000000000279df40 .part L_000000000282fb30, 8, 1; +L_000000000279e760 .part L_000000000279f840, 7, 1; +L_000000000279dea0 .part L_000000000282fb30, 9, 1; +L_000000000279e080 .part L_000000000279f840, 8, 1; +L_000000000279d040 .part L_000000000282fb30, 10, 1; +L_000000000279e800 .part L_000000000279f840, 9, 1; +L_000000000279d5e0 .part L_000000000282fb30, 11, 1; +L_000000000279ec60 .part L_000000000279f840, 10, 1; +L_000000000279e1c0 .part L_000000000282fb30, 12, 1; +L_000000000279cd20 .part L_000000000279f840, 11, 1; +L_000000000279e8a0 .part L_000000000282fb30, 13, 1; +L_000000000279d360 .part L_000000000279f840, 12, 1; +L_000000000279eee0 .part L_000000000282fb30, 14, 1; +L_000000000279d7c0 .part L_000000000279f840, 13, 1; +L_000000000279e120 .part L_000000000282fb30, 15, 1; +L_000000000279d720 .part L_000000000279f840, 14, 1; +L_000000000279cbe0 .part L_000000000282fb30, 16, 1; +L_000000000279cdc0 .part L_000000000279f840, 15, 1; +L_000000000279d860 .part L_000000000282fb30, 17, 1; +L_000000000279d0e0 .part L_000000000279f840, 16, 1; +L_000000000279dfe0 .part L_000000000282fb30, 18, 1; +L_000000000279ed00 .part L_000000000279f840, 17, 1; +L_000000000279ebc0 .part L_000000000282fb30, 19, 1; +L_000000000279e300 .part L_000000000279f840, 18, 1; +L_000000000279ef80 .part L_000000000282fb30, 20, 1; +L_000000000279f020 .part L_000000000279f840, 19, 1; +L_000000000279dc20 .part L_000000000282fb30, 21, 1; +L_000000000279dcc0 .part L_000000000279f840, 20, 1; +L_000000000279cf00 .part L_000000000282fb30, 22, 1; +L_000000000279cc80 .part L_000000000279f840, 21, 1; +L_000000000279e9e0 .part L_000000000282fb30, 23, 1; +L_000000000279d900 .part L_000000000279f840, 22, 1; +L_000000000279e3a0 .part L_000000000282fb30, 24, 1; +L_000000000279f0c0 .part L_000000000279f840, 23, 1; +L_000000000279ea80 .part L_000000000282fb30, 25, 1; +L_000000000279caa0 .part L_000000000279f840, 24, 1; +L_000000000279d4a0 .part L_000000000282fb30, 26, 1; +L_000000000279dd60 .part L_000000000279f840, 25, 1; +L_000000000279eb20 .part L_000000000282fb30, 27, 1; +L_000000000279c960 .part L_000000000279f840, 26, 1; +L_000000000279d400 .part L_000000000282fb30, 28, 1; +L_000000000279d220 .part L_000000000279f840, 27, 1; +L_000000000279ca00 .part L_000000000282fb30, 29, 1; +L_000000000279cb40 .part L_000000000279f840, 28, 1; +L_000000000279cfa0 .part L_000000000282fb30, 30, 1; +L_000000000279d2c0 .part L_000000000279f840, 29, 1; +LS_000000000279d540_0_0 .concat8 [ 1 1 1 1], L_000000000282bf70, L_0000000000eb3490, L_0000000000eb3dc0, L_0000000000eb2d90; +LS_000000000279d540_0_4 .concat8 [ 1 1 1 1], L_00000000027ec710, L_00000000027ed270, L_00000000027ec390, L_00000000027ed660; +LS_000000000279d540_0_8 .concat8 [ 1 1 1 1], L_00000000027edf20, L_00000000027f6960, L_00000000027f7840, L_00000000027f7450; +LS_000000000279d540_0_12 .concat8 [ 1 1 1 1], L_00000000027f7df0, L_0000000002800520, L_00000000028006e0, L_0000000002801160; +LS_000000000279d540_0_16 .concat8 [ 1 1 1 1], L_00000000028015c0, L_00000000028084d0, L_00000000028093b0, L_0000000002808460; +LS_000000000279d540_0_20 .concat8 [ 1 1 1 1], L_00000000028085b0, L_0000000002809dc0, L_0000000002807ba0, L_0000000002806f60; +LS_000000000279d540_0_24 .concat8 [ 1 1 1 1], L_00000000028073c0, L_0000000002807350, L_000000000280b520, L_000000000280a720; +LS_000000000279d540_0_28 .concat8 [ 1 1 1 1], L_000000000280a4f0, L_000000000280c2b0, L_000000000280d120, L_000000000280d430; +LS_000000000279d540_1_0 .concat8 [ 4 4 4 4], LS_000000000279d540_0_0, LS_000000000279d540_0_4, LS_000000000279d540_0_8, LS_000000000279d540_0_12; +LS_000000000279d540_1_4 .concat8 [ 4 4 4 4], LS_000000000279d540_0_16, LS_000000000279d540_0_20, LS_000000000279d540_0_24, LS_000000000279d540_0_28; +L_000000000279d540 .concat8 [ 16 16 0 0], LS_000000000279d540_1_0, LS_000000000279d540_1_4; +L_000000000279d9a0 .part v0000000002790b60_0, 0, 1; +LS_000000000279dae0_0_0 .concat8 [ 1 1 1 1], L_000000000282c830, L_0000000000eb4290, L_0000000000eb2cb0, L_0000000000eb3b90; +LS_000000000279dae0_0_4 .concat8 [ 1 1 1 1], L_00000000027ed4a0, L_00000000027ece80, L_00000000027ec630, L_00000000027ed6d0; +LS_000000000279dae0_0_8 .concat8 [ 1 1 1 1], L_00000000027f6f10, L_00000000027f6d50, L_00000000027f6dc0, L_00000000027f76f0; +LS_000000000279dae0_0_12 .concat8 [ 1 1 1 1], L_00000000027f8020, L_0000000002800590, L_0000000002800360, L_00000000028008a0; +LS_000000000279dae0_0_16 .concat8 [ 1 1 1 1], L_0000000002801e80, L_00000000028089a0, L_0000000002808fc0, L_0000000002808a10; +LS_000000000279dae0_0_20 .concat8 [ 1 1 1 1], L_0000000002808620, L_0000000002809ea0, L_0000000002806ef0, L_00000000028069b0; +LS_000000000279dae0_0_24 .concat8 [ 1 1 1 1], L_0000000002807cf0, L_000000000280a8e0, L_000000000280a2c0, L_000000000280a480; +LS_000000000279dae0_0_28 .concat8 [ 1 1 1 1], L_000000000280aa30, L_000000000280c160, L_000000000280d7b0, L_000000000280cd30; +LS_000000000279dae0_1_0 .concat8 [ 4 4 4 4], LS_000000000279dae0_0_0, LS_000000000279dae0_0_4, LS_000000000279dae0_0_8, LS_000000000279dae0_0_12; +LS_000000000279dae0_1_4 .concat8 [ 4 4 4 4], LS_000000000279dae0_0_16, LS_000000000279dae0_0_20, LS_000000000279dae0_0_24, LS_000000000279dae0_0_28; +L_000000000279dae0 .concat8 [ 16 16 0 0], LS_000000000279dae0_1_0, LS_000000000279dae0_1_4; +L_000000000279de00 .part v0000000002790a20_0, 0, 1; +L_000000000279ffc0 .part v0000000002790a20_0, 2, 1; +L_000000000279fb60 .part v0000000002790a20_0, 0, 1; +L_000000000279f5c0 .part v0000000002790a20_0, 1, 1; +L_000000000279f700 .part L_000000000279f200, 1, 1; +LS_000000000279fca0_0_0 .concat8 [ 1 1 1 1], L_000000000282cd00, L_0000000000eb3730, L_0000000000eb3a40, L_00000000027ec860; +LS_000000000279fca0_0_4 .concat8 [ 1 1 1 1], L_00000000027ec240, L_00000000027ed970, L_00000000027ed9e0, L_00000000027eddd0; +LS_000000000279fca0_0_8 .concat8 [ 1 1 1 1], L_00000000027f6180, L_00000000027f73e0, L_00000000027f7680, L_00000000027f7fb0; +LS_000000000279fca0_0_12 .concat8 [ 1 1 1 1], L_0000000002801be0, L_00000000028010f0, L_0000000002801b70, L_0000000002801320; +LS_000000000279fca0_0_16 .concat8 [ 1 1 1 1], L_0000000002807dd0, L_0000000002809340, L_0000000002809490, L_0000000002808c40; +LS_000000000279fca0_0_20 .concat8 [ 1 1 1 1], L_0000000002809ab0, L_00000000028077b0, L_0000000002807820, L_0000000002806b70; +LS_000000000279fca0_0_24 .concat8 [ 1 1 1 1], L_0000000002807580, L_000000000280a5d0, L_000000000280b670, L_000000000280b7c0; +LS_000000000279fca0_0_28 .concat8 [ 1 1 1 1], L_000000000280c710, L_000000000280cfd0, L_000000000280d190, L_000000000280d580; +LS_000000000279fca0_1_0 .concat8 [ 4 4 4 4], LS_000000000279fca0_0_0, LS_000000000279fca0_0_4, LS_000000000279fca0_0_8, LS_000000000279fca0_0_12; +LS_000000000279fca0_1_4 .concat8 [ 4 4 4 4], LS_000000000279fca0_0_16, LS_000000000279fca0_0_20, LS_000000000279fca0_0_24, LS_000000000279fca0_0_28; +L_000000000279fca0 .concat8 [ 16 16 0 0], LS_000000000279fca0_1_0, LS_000000000279fca0_1_4; +LS_000000000279f3e0_0_0 .concat8 [ 1 1 1 1], L_000000000282d240, L_0000000000eb2a10, L_0000000000eb43e0, L_0000000000eb41b0; +LS_000000000279f3e0_0_4 .concat8 [ 1 1 1 1], L_00000000027ed0b0, L_00000000027ed430, L_00000000027eca90, L_00000000027ec1d0; +LS_000000000279f3e0_0_8 .concat8 [ 1 1 1 1], L_00000000027f7d10, L_00000000027f7990, L_00000000027f6f80, L_00000000027f77d0; +LS_000000000279f3e0_0_12 .concat8 [ 1 1 1 1], L_00000000028018d0, L_0000000002801a90, L_0000000002800600, L_0000000002800bb0; +LS_000000000279f3e0_0_16 .concat8 [ 1 1 1 1], L_00000000028020b0, L_00000000028095e0, L_0000000002809180, L_0000000002809810; +LS_000000000279f3e0_0_20 .concat8 [ 1 1 1 1], L_0000000002809ff0, L_0000000002807ac0, L_0000000002807d60, L_00000000028068d0; +LS_000000000279f3e0_0_24 .concat8 [ 1 1 1 1], L_0000000002807430, L_000000000280b8a0, L_000000000280ae90, L_000000000280b050; +LS_000000000279f3e0_0_28 .concat8 [ 1 1 1 1], L_000000000280ab80, L_000000000280c550, L_000000000280c390, L_000000000280c5c0; +LS_000000000279f3e0_1_0 .concat8 [ 4 4 4 4], LS_000000000279f3e0_0_0, LS_000000000279f3e0_0_4, LS_000000000279f3e0_0_8, LS_000000000279f3e0_0_12; +LS_000000000279f3e0_1_4 .concat8 [ 4 4 4 4], LS_000000000279f3e0_0_16, LS_000000000279f3e0_0_20, LS_000000000279f3e0_0_24, LS_000000000279f3e0_0_28; +L_000000000279f3e0 .concat8 [ 16 16 0 0], LS_000000000279f3e0_1_0, LS_000000000279f3e0_1_4; +L_000000000279f340 .part v0000000002790660_0, 0, 1; +L_000000000279ff20 .part L_000000000279d540, 0, 1; +L_000000000279f480 .part L_000000000279dae0, 0, 1; +L_000000000279f660 .part v0000000002790a20_0, 0, 1; +L_000000000279f7a0 .part L_000000000279fca0, 0, 1; +L_000000000279f520 .part L_000000000279f3e0, 30, 1; +L_000000000279fde0 .part L_000000000279f3e0, 31, 1; +LS_000000000279f840_0_0 .concat8 [ 1 1 1 1], L_000000000282cec0, L_000000000280d660, L_000000000280d4a0, L_000000000280d6d0; +LS_000000000279f840_0_4 .concat8 [ 1 1 1 1], L_000000000280d820, L_000000000280bde0, L_000000000280d890, L_000000000280be50; +LS_000000000279f840_0_8 .concat8 [ 1 1 1 1], L_000000000280bfa0, L_000000000280c010, L_000000000280c0f0, L_000000000280deb0; +LS_000000000279f840_0_12 .concat8 [ 1 1 1 1], L_000000000280df90, L_000000000280d9e0, L_000000000280e0e0, L_000000000280dcf0; +LS_000000000279f840_0_16 .concat8 [ 1 1 1 1], L_000000000280df20, L_000000000280db30, L_000000000280dba0, L_000000000280da50; +LS_000000000279f840_0_20 .concat8 [ 1 1 1 1], L_000000000280dac0, L_000000000280e000, L_000000000280dc10, L_000000000280dc80; +LS_000000000279f840_0_24 .concat8 [ 1 1 1 1], L_000000000280de40, L_000000000280dd60, L_000000000280ddd0, L_000000000280e070; +LS_000000000279f840_0_28 .concat8 [ 1 1 1 0], L_000000000282c8a0, L_000000000282cad0, L_000000000282c2f0; +LS_000000000279f840_1_0 .concat8 [ 4 4 4 4], LS_000000000279f840_0_0, LS_000000000279f840_0_4, LS_000000000279f840_0_8, LS_000000000279f840_0_12; +LS_000000000279f840_1_4 .concat8 [ 4 4 4 3], LS_000000000279f840_0_16, LS_000000000279f840_0_20, LS_000000000279f840_0_24, LS_000000000279f840_0_28; +L_000000000279f840 .concat8 [ 16 15 0 0], LS_000000000279f840_1_0, LS_000000000279f840_1_4; +L_000000000279fac0 .part L_000000000282fb30, 0, 1; +L_000000000279f8e0 .part L_000000000282fb30, 1, 1; +L_000000000279f980 .part L_000000000279f840, 30, 1; +L_000000000279f200 .concat8 [ 1 1 0 0], L_000000000282cb40, L_000000000282c750; +L_000000000279f160 .part v0000000002790a20_0, 1, 1; +L_000000000279fa20 .part L_000000000279f200, 0, 1; +L_000000000279fd40 .part L_000000000279f200, 1, 1; +L_000000000279f2a0 .part L_000000000279f3e0, 31, 1; +L_000000000282fbd0 .part L_000000000279f200, 0, 1; +L_000000000282e5f0 .part L_000000000279f200, 1, 1; +L_000000000282e730 .part L_000000000279f200, 0, 1; +L_000000000282f450 .part L_000000000279f200, 1, 1; +L_0000000002830990 .part L_000000000279fca0, 31, 1; +LS_000000000282fb30_0_0 .concat8 [ 1 1 1 1], L_000000000282d8d0, L_0000000000eb2c40, L_0000000000eb3ab0, L_00000000027ec400; +LS_000000000282fb30_0_4 .concat8 [ 1 1 1 1], L_00000000027ece10, L_00000000027eccc0, L_00000000027eda50, L_00000000027ede40; +LS_000000000282fb30_0_8 .concat8 [ 1 1 1 1], L_00000000027f7610, L_00000000027f7300, L_00000000027f7290, L_00000000027f8090; +LS_000000000282fb30_0_12 .concat8 [ 1 1 1 1], L_0000000002800670, L_0000000002800440, L_0000000002800830, L_0000000002801550; +LS_000000000282fb30_0_16 .concat8 [ 1 1 1 1], L_0000000002809260, L_0000000002808ee0, L_00000000028083f0, L_0000000002808000; +LS_000000000282fb30_0_20 .concat8 [ 1 1 1 1], L_0000000002809ce0, L_0000000002807510, L_0000000002807900, L_0000000002806fd0; +LS_000000000282fb30_0_24 .concat8 [ 1 1 1 1], L_00000000028076d0, L_000000000280bd00, L_000000000280bd70, L_000000000280b210; +LS_000000000282fb30_0_28 .concat8 [ 1 1 1 1], L_000000000280cb00, L_000000000280bf30, L_000000000280d510, L_000000000280d3c0; +LS_000000000282fb30_1_0 .concat8 [ 4 4 4 4], LS_000000000282fb30_0_0, LS_000000000282fb30_0_4, LS_000000000282fb30_0_8, LS_000000000282fb30_0_12; +LS_000000000282fb30_1_4 .concat8 [ 4 4 4 4], LS_000000000282fb30_0_16, LS_000000000282fb30_0_20, LS_000000000282fb30_0_24, LS_000000000282fb30_0_28; +L_000000000282fb30 .concat8 [ 16 16 0 0], LS_000000000282fb30_1_0, LS_000000000282fb30_1_4; +S_0000000000cbebc0 .scope module, "_bit" "aluFullBit" 4 44, 5 6 0, S_0000000000cc7490; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "res" + .port_info 1 /OUTPUT 1 "carryAND" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "cin" + .port_info 5 /INPUT 1 "ctrl0" + .port_info 6 /INPUT 2 "sel" +v0000000000e65e30_0 .net "a", 0 0, L_000000000279f340; 1 drivers +v0000000000e675f0_0 .net "b", 0 0, L_000000000279ff20; 1 drivers +v0000000000e66e70_0 .net "carryAND", 0 0, L_000000000282d240; 1 drivers +v0000000000e67ff0_0 .net "cin", 0 0, L_000000000279f480; 1 drivers +v0000000000e663d0_0 .net "ctrl0", 0 0, L_000000000279f660; 1 drivers +v0000000000e66b50_0 .net "nab", 0 0, L_000000000282cbb0; 1 drivers +v0000000000e66bf0_0 .net "orNOR", 0 0, L_000000000282d080; 1 drivers +v0000000000e66fb0_0 .net "res", 0 0, L_000000000282cd00; 1 drivers +v0000000000e67190_0 .net "sel", 1 0, v0000000000e625f0_0; alias, 1 drivers +v0000000000e67730_0 .net "sumXOR", 0 0, L_000000000282d010; 1 drivers +L_000000000279fc00 .part v0000000000e625f0_0, 1, 1; +L_000000000279fe80 .part v0000000000e625f0_0, 0, 1; +S_0000000000cbed40 .scope module, "alu" "aluBit" 5 18, 6 14 0, S_0000000000cbebc0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sumXOR" + .port_info 1 /OUTPUT 1 "carryAND" + .port_info 2 /OUTPUT 1 "nab" + .port_info 3 /OUTPUT 1 "orNOR" + .port_info 4 /INPUT 1 "a" + .port_info 5 /INPUT 1 "b" + .port_info 6 /INPUT 1 "carryin" + .port_info 7 /INPUT 1 "i0" +L_000000000282cbb0/d .functor NAND 1, L_000000000279f340, L_000000000279ff20, C4<1>, C4<1>; +L_000000000282cbb0 .delay 1 (20000,20000,20000) L_000000000282cbb0/d; +L_000000000282c910/d .functor NAND 1, L_000000000279ff20, L_000000000279f480, C4<1>, C4<1>; +L_000000000282c910 .delay 1 (20000,20000,20000) L_000000000282c910/d; +L_000000000282c6e0/d .functor NAND 1, L_000000000279f340, L_000000000279f480, C4<1>, C4<1>; +L_000000000282c6e0 .delay 1 (20000,20000,20000) L_000000000282c6e0/d; +L_000000000282d240/d .functor NAND 1, L_000000000282cbb0, L_000000000282c6e0, L_000000000282c910, C4<1>; +L_000000000282d240 .delay 1 (30000,30000,30000) L_000000000282d240/d; +L_000000000282d010/d .functor XOR 1, L_000000000279f340, L_000000000279ff20, L_000000000279f480, C4<0>; +L_000000000282d010 .delay 1 (30000,30000,30000) L_000000000282d010/d; +L_000000000282c9f0/d .functor NOR 1, L_000000000279f340, L_000000000279ff20, C4<0>, C4<0>; +L_000000000282c9f0 .delay 1 (20000,20000,20000) L_000000000282c9f0/d; +L_000000000282d080/d .functor XOR 1, L_000000000282c9f0, L_000000000279f660, C4<0>, C4<0>; +L_000000000282d080 .delay 1 (20000,20000,20000) L_000000000282d080/d; +v0000000000e9e0a0_0 .net "a", 0 0, L_000000000279f340; alias, 1 drivers +v0000000000e9e1e0_0 .net "anorb", 0 0, L_000000000282c9f0; 1 drivers +v0000000000e9e3c0_0 .net "b", 0 0, L_000000000279ff20; alias, 1 drivers +v0000000000e9f180_0 .net "carryAND", 0 0, L_000000000282d240; alias, 1 drivers +v0000000000e9cc00_0 .net "carryin", 0 0, L_000000000279f480; alias, 1 drivers +v0000000000e9eaa0_0 .net "i0", 0 0, L_000000000279f660; alias, 1 drivers +v0000000000e9e640_0 .net "nab", 0 0, L_000000000282cbb0; alias, 1 drivers +v0000000000e9d6a0_0 .net "nac", 0 0, L_000000000282c6e0; 1 drivers +v0000000000e9eb40_0 .net "nbc", 0 0, L_000000000282c910; 1 drivers +v0000000000e9e780_0 .net "orNOR", 0 0, L_000000000282d080; alias, 1 drivers +v0000000000e9e960_0 .net "sumXOR", 0 0, L_000000000282d010; alias, 1 drivers +S_0000000000cb5eb0 .scope module, "mux" "multiplexer" 5 20, 7 7 0, S_0000000000cbebc0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "a" + .port_info 2 /INPUT 1 "b" + .port_info 3 /INPUT 1 "c" + .port_info 4 /INPUT 1 "d" + .port_info 5 /INPUT 1 "s1" + .port_info 6 /INPUT 1 "s0" +L_000000000282c0c0/d .functor NOT 1, L_000000000279fe80, C4<0>, C4<0>, C4<0>; +L_000000000282c0c0 .delay 1 (10000,10000,10000) L_000000000282c0c0/d; +L_000000000282d160/d .functor NOT 1, L_000000000279fc00, C4<0>, C4<0>, C4<0>; +L_000000000282d160 .delay 1 (10000,10000,10000) L_000000000282d160/d; +L_000000000282d710/d .functor NAND 1, L_000000000279fc00, L_000000000279fe80, L_000000000282d010, C4<1>; +L_000000000282d710 .delay 1 (30000,30000,30000) L_000000000282d710/d; +L_000000000282d780/d .functor NAND 1, L_000000000279fc00, L_000000000282c0c0, L_000000000282d080, C4<1>; +L_000000000282d780 .delay 1 (30000,30000,30000) L_000000000282d780/d; +L_000000000282c1a0/d .functor NAND 1, L_000000000282d160, L_000000000279fe80, L_000000000282d240, C4<1>; +L_000000000282c1a0 .delay 1 (30000,30000,30000) L_000000000282c1a0/d; +L_000000000282ce50/d .functor NAND 1, L_000000000282d160, L_000000000282c0c0, L_000000000282cbb0, C4<1>; +L_000000000282ce50 .delay 1 (30000,30000,30000) L_000000000282ce50/d; +L_000000000282cd00/d .functor NAND 1, L_000000000282d710, L_000000000282d780, L_000000000282c1a0, L_000000000282ce50; +L_000000000282cd00 .delay 1 (40000,40000,40000) L_000000000282cd00/d; +v0000000000e9d100_0 .net "a", 0 0, L_000000000282d010; alias, 1 drivers +v0000000000e9cca0_0 .net "aout", 0 0, L_000000000282d710; 1 drivers +v0000000000e9d1a0_0 .net "b", 0 0, L_000000000282d080; alias, 1 drivers +v0000000000e643f0_0 .net "bout", 0 0, L_000000000282d780; 1 drivers +v0000000000e65570_0 .net "c", 0 0, L_000000000282d240; alias, 1 drivers +v0000000000e656b0_0 .net "cout", 0 0, L_000000000282c1a0; 1 drivers +v0000000000e63c70_0 .net "d", 0 0, L_000000000282cbb0; alias, 1 drivers +v0000000000e65d90_0 .net "dout", 0 0, L_000000000282ce50; 1 drivers +v0000000000e657f0_0 .net "ns0", 0 0, L_000000000282c0c0; 1 drivers +v0000000000e64850_0 .net "ns1", 0 0, L_000000000282d160; 1 drivers +v0000000000e65930_0 .net "out", 0 0, L_000000000282cd00; alias, 1 drivers +v0000000000e65a70_0 .net "s0", 0 0, L_000000000279fe80; 1 drivers +v0000000000e65b10_0 .net "s1", 0 0, L_000000000279fc00; 1 drivers +S_0000000000cb6030 .scope module, "_lut" "ALULut" 4 35, 8 13 0, S_0000000000cc7490; + .timescale -9 -12; + .port_info 0 /OUTPUT 2 "select" + .port_info 1 /OUTPUT 1 "invert" + .port_info 2 /OUTPUT 1 "carry" + .port_info 3 /INPUT 3 "operation" +v0000000000e67370_0 .var "carry", 0 0; +v0000000000e68bd0_0 .var "invert", 0 0; +v0000000000e68db0_0 .net "operation", 2 0, v0000000002790a20_0; alias, 1 drivers +v0000000000e625f0_0 .var "select", 1 0; +E_0000000000f05e20 .event edge, v0000000000e68db0_0; +S_000000000119e8a0 .scope generate, "aluBits[1]" "aluBits[1]" 4 49, 4 49 0, S_0000000000cc7490; + .timescale -9 -12; +P_0000000000f04ee0 .param/l "i" 0 4 49, +C4<01>; +L_0000000000eb3490/d .functor XOR 1, L_0000000002790200, v0000000000e68bd0_0, C4<0>, C4<0>; +L_0000000000eb3490 .delay 1 (20000,20000,20000) L_0000000000eb3490/d; +L_0000000000eb4290/d .functor AND 1, v0000000000e67370_0, L_0000000002790ca0, C4<1>, C4<1>; +L_0000000000eb4290 .delay 1 (30000,30000,30000) L_0000000000eb4290/d; +L_0000000000eb2c40/d .functor AND 1, L_0000000002792280, L_000000000282c280, C4<1>, C4<1>; +L_0000000000eb2c40 .delay 1 (30000,30000,30000) L_0000000000eb2c40/d; +v0000000000e48230_0 .net *"_s1", 0 0, L_0000000002790200; 1 drivers +v0000000000e45e90_0 .net *"_s3", 0 0, L_0000000002790ca0; 1 drivers +v0000000000e49450_0 .net *"_s9", 0 0, L_0000000002792280; 1 drivers +S_000000000119ea20 .scope module, "_bit" "aluFullBit" 4 52, 5 6 0, S_000000000119e8a0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "res" + .port_info 1 /OUTPUT 1 "carryAND" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "cin" + .port_info 5 /INPUT 1 "ctrl0" + .port_info 6 /INPUT 2 "sel" +v0000000000e2c950_0 .net "a", 0 0, L_0000000002790de0; 1 drivers +v0000000000e2cf90_0 .net "b", 0 0, L_0000000002791a60; 1 drivers +v0000000000e46390_0 .net "carryAND", 0 0, L_0000000000eb2a10; 1 drivers +v0000000000e46d90_0 .net "cin", 0 0, L_0000000002790d40; 1 drivers +v0000000000e464d0_0 .net "ctrl0", 0 0, L_0000000002791ba0; 1 drivers +v0000000000e47e70_0 .net "nab", 0 0, L_0000000000eb39d0; 1 drivers +v0000000000e470b0_0 .net "orNOR", 0 0, L_0000000000eb3d50; 1 drivers +v0000000000e47150_0 .net "res", 0 0, L_0000000000eb3730; 1 drivers +v0000000000e473d0_0 .net "sel", 1 0, v0000000000e625f0_0; alias, 1 drivers +v0000000000e48050_0 .net "sumXOR", 0 0, L_0000000000eb4300; 1 drivers +L_00000000027902a0 .part v0000000000e625f0_0, 1, 1; +L_0000000002790340 .part v0000000000e625f0_0, 0, 1; +S_0000000000cc88e0 .scope module, "alu" "aluBit" 5 18, 6 14 0, S_000000000119ea20; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sumXOR" + .port_info 1 /OUTPUT 1 "carryAND" + .port_info 2 /OUTPUT 1 "nab" + .port_info 3 /OUTPUT 1 "orNOR" + .port_info 4 /INPUT 1 "a" + .port_info 5 /INPUT 1 "b" + .port_info 6 /INPUT 1 "carryin" + .port_info 7 /INPUT 1 "i0" +L_0000000000eb39d0/d .functor NAND 1, L_0000000002790de0, L_0000000002791a60, C4<1>, C4<1>; +L_0000000000eb39d0 .delay 1 (20000,20000,20000) L_0000000000eb39d0/d; +L_0000000000eb31f0/d .functor NAND 1, L_0000000002791a60, L_0000000002790d40, C4<1>, C4<1>; +L_0000000000eb31f0 .delay 1 (20000,20000,20000) L_0000000000eb31f0/d; +L_0000000000eb3f10/d .functor NAND 1, L_0000000002790de0, L_0000000002790d40, C4<1>, C4<1>; +L_0000000000eb3f10 .delay 1 (20000,20000,20000) L_0000000000eb3f10/d; +L_0000000000eb2a10/d .functor NAND 1, L_0000000000eb39d0, L_0000000000eb3f10, L_0000000000eb31f0, C4<1>; +L_0000000000eb2a10 .delay 1 (30000,30000,30000) L_0000000000eb2a10/d; +L_0000000000eb4300/d .functor XOR 1, L_0000000002790de0, L_0000000002791a60, L_0000000002790d40, C4<0>; +L_0000000000eb4300 .delay 1 (30000,30000,30000) L_0000000000eb4300/d; +L_0000000000eb3ce0/d .functor NOR 1, L_0000000002790de0, L_0000000002791a60, C4<0>, C4<0>; +L_0000000000eb3ce0 .delay 1 (20000,20000,20000) L_0000000000eb3ce0/d; +L_0000000000eb3d50/d .functor XOR 1, L_0000000000eb3ce0, L_0000000002791ba0, C4<0>, C4<0>; +L_0000000000eb3d50 .delay 1 (20000,20000,20000) L_0000000000eb3d50/d; +v0000000000e611f0_0 .net "a", 0 0, L_0000000002790de0; alias, 1 drivers +v0000000000e627d0_0 .net "anorb", 0 0, L_0000000000eb3ce0; 1 drivers +v0000000000e61e70_0 .net "b", 0 0, L_0000000002791a60; alias, 1 drivers +v0000000000e629b0_0 .net "carryAND", 0 0, L_0000000000eb2a10; alias, 1 drivers +v0000000000e63270_0 .net "carryin", 0 0, L_0000000002790d40; alias, 1 drivers +v0000000000e62a50_0 .net "i0", 0 0, L_0000000002791ba0; alias, 1 drivers +v0000000000e62b90_0 .net "nab", 0 0, L_0000000000eb39d0; alias, 1 drivers +v0000000000e62cd0_0 .net "nac", 0 0, L_0000000000eb3f10; 1 drivers +v0000000000e63310_0 .net "nbc", 0 0, L_0000000000eb31f0; 1 drivers +v0000000000e29f70_0 .net "orNOR", 0 0, L_0000000000eb3d50; alias, 1 drivers +v0000000000e2c130_0 .net "sumXOR", 0 0, L_0000000000eb4300; alias, 1 drivers +S_0000000000cc8a60 .scope module, "mux" "multiplexer" 5 20, 7 7 0, S_000000000119ea20; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "a" + .port_info 2 /INPUT 1 "b" + .port_info 3 /INPUT 1 "c" + .port_info 4 /INPUT 1 "d" + .port_info 5 /INPUT 1 "s1" + .port_info 6 /INPUT 1 "s0" +L_0000000000eb3e30/d .functor NOT 1, L_0000000002790340, C4<0>, C4<0>, C4<0>; +L_0000000000eb3e30 .delay 1 (10000,10000,10000) L_0000000000eb3e30/d; +L_0000000000eb2b60/d .functor NOT 1, L_00000000027902a0, C4<0>, C4<0>, C4<0>; +L_0000000000eb2b60 .delay 1 (10000,10000,10000) L_0000000000eb2b60/d; +L_0000000000eb3260/d .functor NAND 1, L_00000000027902a0, L_0000000002790340, L_0000000000eb4300, C4<1>; +L_0000000000eb3260 .delay 1 (30000,30000,30000) L_0000000000eb3260/d; +L_0000000000eb2fc0/d .functor NAND 1, L_00000000027902a0, L_0000000000eb3e30, L_0000000000eb3d50, C4<1>; +L_0000000000eb2fc0 .delay 1 (30000,30000,30000) L_0000000000eb2fc0/d; +L_0000000000eb3880/d .functor NAND 1, L_0000000000eb2b60, L_0000000002790340, L_0000000000eb2a10, C4<1>; +L_0000000000eb3880 .delay 1 (30000,30000,30000) L_0000000000eb3880/d; +L_0000000000eb3ff0/d .functor NAND 1, L_0000000000eb2b60, L_0000000000eb3e30, L_0000000000eb39d0, C4<1>; +L_0000000000eb3ff0 .delay 1 (30000,30000,30000) L_0000000000eb3ff0/d; +L_0000000000eb3730/d .functor NAND 1, L_0000000000eb3260, L_0000000000eb2fc0, L_0000000000eb3880, L_0000000000eb3ff0; +L_0000000000eb3730 .delay 1 (40000,40000,40000) L_0000000000eb3730/d; +v0000000000e2bf50_0 .net "a", 0 0, L_0000000000eb4300; alias, 1 drivers +v0000000000e2b370_0 .net "aout", 0 0, L_0000000000eb3260; 1 drivers +v0000000000e2a010_0 .net "b", 0 0, L_0000000000eb3d50; alias, 1 drivers +v0000000000e2a790_0 .net "bout", 0 0, L_0000000000eb2fc0; 1 drivers +v0000000000e2ab50_0 .net "c", 0 0, L_0000000000eb2a10; alias, 1 drivers +v0000000000e2a510_0 .net "cout", 0 0, L_0000000000eb3880; 1 drivers +v0000000000e2b550_0 .net "d", 0 0, L_0000000000eb39d0; alias, 1 drivers +v0000000000e2c090_0 .net "dout", 0 0, L_0000000000eb3ff0; 1 drivers +v0000000000e2c450_0 .net "ns0", 0 0, L_0000000000eb3e30; 1 drivers +v0000000000e2ca90_0 .net "ns1", 0 0, L_0000000000eb2b60; 1 drivers +v0000000000e2c630_0 .net "out", 0 0, L_0000000000eb3730; alias, 1 drivers +v0000000000e2c810_0 .net "s0", 0 0, L_0000000002790340; 1 drivers +v0000000000e2c8b0_0 .net "s1", 0 0, L_00000000027902a0; 1 drivers +S_0000000001196790 .scope generate, "aluBits[2]" "aluBits[2]" 4 49, 4 49 0, S_0000000000cc7490; + .timescale -9 -12; +P_0000000000f05b20 .param/l "i" 0 4 49, +C4<010>; +L_0000000000eb3dc0/d .functor XOR 1, L_0000000002792460, v0000000000e68bd0_0, C4<0>, C4<0>; +L_0000000000eb3dc0 .delay 1 (20000,20000,20000) L_0000000000eb3dc0/d; +L_0000000000eb2cb0/d .functor AND 1, v0000000000e67370_0, L_0000000002790f20, C4<1>, C4<1>; +L_0000000000eb2cb0 .delay 1 (30000,30000,30000) L_0000000000eb2cb0/d; +L_0000000000eb3ab0/d .functor AND 1, L_0000000002791560, L_000000000282c280, C4<1>, C4<1>; +L_0000000000eb3ab0 .delay 1 (30000,30000,30000) L_0000000000eb3ab0/d; +v0000000000e1fea0_0 .net *"_s1", 0 0, L_0000000002792460; 1 drivers +v0000000000e1ff40_0 .net *"_s3", 0 0, L_0000000002790f20; 1 drivers +v0000000000e20080_0 .net *"_s9", 0 0, L_0000000002791560; 1 drivers +S_0000000001196910 .scope module, "_bit" "aluFullBit" 4 52, 5 6 0, S_0000000001196790; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "res" + .port_info 1 /OUTPUT 1 "carryAND" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "cin" + .port_info 5 /INPUT 1 "ctrl0" + .port_info 6 /INPUT 2 "sel" +v0000000000e1e780_0 .net "a", 0 0, L_0000000002791060; 1 drivers +v0000000000e1e3c0_0 .net "b", 0 0, L_0000000002791d80; 1 drivers +v0000000000e1ef00_0 .net "carryAND", 0 0, L_0000000000eb43e0; 1 drivers +v0000000000e1dc40_0 .net "cin", 0 0, L_0000000002791100; 1 drivers +v0000000000e1d060_0 .net "ctrl0", 0 0, L_00000000027912e0; 1 drivers +v0000000000e1d380_0 .net "nab", 0 0, L_0000000000eb2d20; 1 drivers +v0000000000e1d420_0 .net "orNOR", 0 0, L_0000000000eb3420; 1 drivers +v0000000000e1d600_0 .net "res", 0 0, L_0000000000eb3a40; 1 drivers +v0000000000e1f680_0 .net "sel", 1 0, v0000000000e625f0_0; alias, 1 drivers +v0000000000e203a0_0 .net "sumXOR", 0 0, L_0000000000eb4220; 1 drivers +L_0000000002791240 .part v0000000000e625f0_0, 1, 1; +L_0000000002790fc0 .part v0000000000e625f0_0, 0, 1; +S_0000000000ed0740 .scope module, "alu" "aluBit" 5 18, 6 14 0, S_0000000001196910; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sumXOR" + .port_info 1 /OUTPUT 1 "carryAND" + .port_info 2 /OUTPUT 1 "nab" + .port_info 3 /OUTPUT 1 "orNOR" + .port_info 4 /INPUT 1 "a" + .port_info 5 /INPUT 1 "b" + .port_info 6 /INPUT 1 "carryin" + .port_info 7 /INPUT 1 "i0" +L_0000000000eb2d20/d .functor NAND 1, L_0000000002791060, L_0000000002791d80, C4<1>, C4<1>; +L_0000000000eb2d20 .delay 1 (20000,20000,20000) L_0000000000eb2d20/d; +L_0000000000eb3180/d .functor NAND 1, L_0000000002791d80, L_0000000002791100, C4<1>, C4<1>; +L_0000000000eb3180 .delay 1 (20000,20000,20000) L_0000000000eb3180/d; +L_0000000000eb3f80/d .functor NAND 1, L_0000000002791060, L_0000000002791100, C4<1>, C4<1>; +L_0000000000eb3f80 .delay 1 (20000,20000,20000) L_0000000000eb3f80/d; +L_0000000000eb43e0/d .functor NAND 1, L_0000000000eb2d20, L_0000000000eb3f80, L_0000000000eb3180, C4<1>; +L_0000000000eb43e0 .delay 1 (30000,30000,30000) L_0000000000eb43e0/d; +L_0000000000eb4220/d .functor XOR 1, L_0000000002791060, L_0000000002791d80, L_0000000002791100, C4<0>; +L_0000000000eb4220 .delay 1 (30000,30000,30000) L_0000000000eb4220/d; +L_0000000000eb38f0/d .functor NOR 1, L_0000000002791060, L_0000000002791d80, C4<0>, C4<0>; +L_0000000000eb38f0 .delay 1 (20000,20000,20000) L_0000000000eb38f0/d; +L_0000000000eb3420/d .functor XOR 1, L_0000000000eb38f0, L_00000000027912e0, C4<0>, C4<0>; +L_0000000000eb3420 .delay 1 (20000,20000,20000) L_0000000000eb3420/d; +v0000000000e48550_0 .net "a", 0 0, L_0000000002791060; alias, 1 drivers +v0000000000e48af0_0 .net "anorb", 0 0, L_0000000000eb38f0; 1 drivers +v0000000000e48cd0_0 .net "b", 0 0, L_0000000002791d80; alias, 1 drivers +v0000000000e49590_0 .net "carryAND", 0 0, L_0000000000eb43e0; alias, 1 drivers +v0000000000e48eb0_0 .net "carryin", 0 0, L_0000000002791100; alias, 1 drivers +v0000000000e496d0_0 .net "i0", 0 0, L_00000000027912e0; alias, 1 drivers +v0000000000e56a40_0 .net "nab", 0 0, L_0000000000eb2d20; alias, 1 drivers +v0000000000e571c0_0 .net "nac", 0 0, L_0000000000eb3f80; 1 drivers +v0000000000e57580_0 .net "nbc", 0 0, L_0000000000eb3180; 1 drivers +v0000000000e56ae0_0 .net "orNOR", 0 0, L_0000000000eb3420; alias, 1 drivers +v0000000000e56d60_0 .net "sumXOR", 0 0, L_0000000000eb4220; alias, 1 drivers +S_0000000000ed0bc0 .scope module, "mux" "multiplexer" 5 20, 7 7 0, S_0000000001196910; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "a" + .port_info 2 /INPUT 1 "b" + .port_info 3 /INPUT 1 "c" + .port_info 4 /INPUT 1 "d" + .port_info 5 /INPUT 1 "s1" + .port_info 6 /INPUT 1 "s0" +L_0000000000eb3810/d .functor NOT 1, L_0000000002790fc0, C4<0>, C4<0>, C4<0>; +L_0000000000eb3810 .delay 1 (10000,10000,10000) L_0000000000eb3810/d; +L_0000000000eb4450/d .functor NOT 1, L_0000000002791240, C4<0>, C4<0>, C4<0>; +L_0000000000eb4450 .delay 1 (10000,10000,10000) L_0000000000eb4450/d; +L_0000000000eb3500/d .functor NAND 1, L_0000000002791240, L_0000000002790fc0, L_0000000000eb4220, C4<1>; +L_0000000000eb3500 .delay 1 (30000,30000,30000) L_0000000000eb3500/d; +L_0000000000eb3570/d .functor NAND 1, L_0000000002791240, L_0000000000eb3810, L_0000000000eb3420, C4<1>; +L_0000000000eb3570 .delay 1 (30000,30000,30000) L_0000000000eb3570/d; +L_0000000000eb37a0/d .functor NAND 1, L_0000000000eb4450, L_0000000002790fc0, L_0000000000eb43e0, C4<1>; +L_0000000000eb37a0 .delay 1 (30000,30000,30000) L_0000000000eb37a0/d; +L_0000000000eb3ea0/d .functor NAND 1, L_0000000000eb4450, L_0000000000eb3810, L_0000000000eb2d20, C4<1>; +L_0000000000eb3ea0 .delay 1 (30000,30000,30000) L_0000000000eb3ea0/d; +L_0000000000eb3a40/d .functor NAND 1, L_0000000000eb3500, L_0000000000eb3570, L_0000000000eb37a0, L_0000000000eb3ea0; +L_0000000000eb3a40 .delay 1 (40000,40000,40000) L_0000000000eb3a40/d; +v0000000000e555a0_0 .net "a", 0 0, L_0000000000eb4220; alias, 1 drivers +v0000000000e551e0_0 .net "aout", 0 0, L_0000000000eb3500; 1 drivers +v0000000000e55aa0_0 .net "b", 0 0, L_0000000000eb3420; alias, 1 drivers +v0000000000e55be0_0 .net "bout", 0 0, L_0000000000eb3570; 1 drivers +v0000000000e549c0_0 .net "c", 0 0, L_0000000000eb43e0; alias, 1 drivers +v0000000000e56220_0 .net "cout", 0 0, L_0000000000eb37a0; 1 drivers +v0000000000e564a0_0 .net "d", 0 0, L_0000000000eb2d20; alias, 1 drivers +v0000000000e562c0_0 .net "dout", 0 0, L_0000000000eb3ea0; 1 drivers +v0000000000e553c0_0 .net "ns0", 0 0, L_0000000000eb3810; 1 drivers +v0000000000e54060_0 .net "ns1", 0 0, L_0000000000eb4450; 1 drivers +v0000000000e54100_0 .net "out", 0 0, L_0000000000eb3a40; alias, 1 drivers +v0000000000e1db00_0 .net "s0", 0 0, L_0000000002790fc0; 1 drivers +v0000000000e1e820_0 .net "s1", 0 0, L_0000000002791240; 1 drivers +S_0000000000ed0d40 .scope generate, "aluBits[3]" "aluBits[3]" 4 49, 4 49 0, S_0000000000cc7490; + .timescale -9 -12; +P_0000000000f04f60 .param/l "i" 0 4 49, +C4<011>; +L_0000000000eb2d90/d .functor XOR 1, L_0000000002791380, v0000000000e68bd0_0, C4<0>, C4<0>; +L_0000000000eb2d90 .delay 1 (20000,20000,20000) L_0000000000eb2d90/d; +L_0000000000eb3b90/d .functor AND 1, v0000000000e67370_0, L_0000000002792500, C4<1>, C4<1>; +L_0000000000eb3b90 .delay 1 (30000,30000,30000) L_0000000000eb3b90/d; +L_00000000027ec400/d .functor AND 1, L_0000000002793180, L_000000000282c280, C4<1>, C4<1>; +L_00000000027ec400 .delay 1 (30000,30000,30000) L_00000000027ec400/d; +v0000000000df1f10_0 .net *"_s1", 0 0, L_0000000002791380; 1 drivers +v0000000000df25f0_0 .net *"_s3", 0 0, L_0000000002792500; 1 drivers +v0000000000df2690_0 .net *"_s9", 0 0, L_0000000002793180; 1 drivers +S_0000000000ed0440 .scope module, "_bit" "aluFullBit" 4 52, 5 6 0, S_0000000000ed0d40; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "res" + .port_info 1 /OUTPUT 1 "carryAND" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "cin" + .port_info 5 /INPUT 1 "ctrl0" + .port_info 6 /INPUT 2 "sel" +v0000000000df9560_0 .net "a", 0 0, L_0000000002791740; 1 drivers +v0000000000dfa3c0_0 .net "b", 0 0, L_00000000027949e0; 1 drivers +v0000000000df97e0_0 .net "carryAND", 0 0, L_0000000000eb41b0; 1 drivers +v0000000000dfa500_0 .net "cin", 0 0, L_00000000027934a0; 1 drivers +v0000000000df9a60_0 .net "ctrl0", 0 0, L_00000000027930e0; 1 drivers +v0000000000df3270_0 .net "nab", 0 0, L_0000000000eb4060; 1 drivers +v0000000000df33b0_0 .net "orNOR", 0 0, L_0000000000eb4610; 1 drivers +v0000000000df1b50_0 .net "res", 0 0, L_00000000027ec860; 1 drivers +v0000000000df2550_0 .net "sel", 1 0, v0000000000e625f0_0; alias, 1 drivers +v0000000000df1830_0 .net "sumXOR", 0 0, L_0000000000eb4530; 1 drivers +L_0000000002791420 .part v0000000000e625f0_0, 1, 1; +L_0000000002791600 .part v0000000000e625f0_0, 0, 1; +S_0000000000ed0140 .scope module, "alu" "aluBit" 5 18, 6 14 0, S_0000000000ed0440; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sumXOR" + .port_info 1 /OUTPUT 1 "carryAND" + .port_info 2 /OUTPUT 1 "nab" + .port_info 3 /OUTPUT 1 "orNOR" + .port_info 4 /INPUT 1 "a" + .port_info 5 /INPUT 1 "b" + .port_info 6 /INPUT 1 "carryin" + .port_info 7 /INPUT 1 "i0" +L_0000000000eb4060/d .functor NAND 1, L_0000000002791740, L_00000000027949e0, C4<1>, C4<1>; +L_0000000000eb4060 .delay 1 (20000,20000,20000) L_0000000000eb4060/d; +L_0000000000eb2e00/d .functor NAND 1, L_00000000027949e0, L_00000000027934a0, C4<1>, C4<1>; +L_0000000000eb2e00 .delay 1 (20000,20000,20000) L_0000000000eb2e00/d; +L_0000000000eb40d0/d .functor NAND 1, L_0000000002791740, L_00000000027934a0, C4<1>, C4<1>; +L_0000000000eb40d0 .delay 1 (20000,20000,20000) L_0000000000eb40d0/d; +L_0000000000eb41b0/d .functor NAND 1, L_0000000000eb4060, L_0000000000eb40d0, L_0000000000eb2e00, C4<1>; +L_0000000000eb41b0 .delay 1 (30000,30000,30000) L_0000000000eb41b0/d; +L_0000000000eb4530/d .functor XOR 1, L_0000000002791740, L_00000000027949e0, L_00000000027934a0, C4<0>; +L_0000000000eb4530 .delay 1 (30000,30000,30000) L_0000000000eb4530/d; +L_0000000000eb46f0/d .functor NOR 1, L_0000000002791740, L_00000000027949e0, C4<0>, C4<0>; +L_0000000000eb46f0 .delay 1 (20000,20000,20000) L_0000000000eb46f0/d; +L_0000000000eb4610/d .functor XOR 1, L_0000000000eb46f0, L_00000000027930e0, C4<0>, C4<0>; +L_0000000000eb4610 .delay 1 (20000,20000,20000) L_0000000000eb4610/d; +v0000000000ddf790_0 .net "a", 0 0, L_0000000002791740; alias, 1 drivers +v0000000000de09b0_0 .net "anorb", 0 0, L_0000000000eb46f0; 1 drivers +v0000000000ddfdd0_0 .net "b", 0 0, L_00000000027949e0; alias, 1 drivers +v0000000000ddf8d0_0 .net "carryAND", 0 0, L_0000000000eb41b0; alias, 1 drivers +v0000000000de0370_0 .net "carryin", 0 0, L_00000000027934a0; alias, 1 drivers +v0000000000de0cd0_0 .net "i0", 0 0, L_00000000027930e0; alias, 1 drivers +v0000000000ddfe70_0 .net "nab", 0 0, L_0000000000eb4060; alias, 1 drivers +v0000000000de0f50_0 .net "nac", 0 0, L_0000000000eb40d0; 1 drivers +v0000000000ddffb0_0 .net "nbc", 0 0, L_0000000000eb2e00; 1 drivers +v0000000000de0050_0 .net "orNOR", 0 0, L_0000000000eb4610; alias, 1 drivers +v0000000000e042d0_0 .net "sumXOR", 0 0, L_0000000000eb4530; alias, 1 drivers +S_0000000000ed08c0 .scope module, "mux" "multiplexer" 5 20, 7 7 0, S_0000000000ed0440; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "a" + .port_info 2 /INPUT 1 "b" + .port_info 3 /INPUT 1 "c" + .port_info 4 /INPUT 1 "d" + .port_info 5 /INPUT 1 "s1" + .port_info 6 /INPUT 1 "s0" +L_0000000000eb4840/d .functor NOT 1, L_0000000002791600, C4<0>, C4<0>, C4<0>; +L_0000000000eb4840 .delay 1 (10000,10000,10000) L_0000000000eb4840/d; +L_0000000000eb47d0/d .functor NOT 1, L_0000000002791420, C4<0>, C4<0>, C4<0>; +L_0000000000eb47d0 .delay 1 (10000,10000,10000) L_0000000000eb47d0/d; +L_0000000000eb45a0/d .functor NAND 1, L_0000000002791420, L_0000000002791600, L_0000000000eb4530, C4<1>; +L_0000000000eb45a0 .delay 1 (30000,30000,30000) L_0000000000eb45a0/d; +L_0000000000eb4680/d .functor NAND 1, L_0000000002791420, L_0000000000eb4840, L_0000000000eb4610, C4<1>; +L_0000000000eb4680 .delay 1 (30000,30000,30000) L_0000000000eb4680/d; +L_0000000000eb4760/d .functor NAND 1, L_0000000000eb47d0, L_0000000002791600, L_0000000000eb41b0, C4<1>; +L_0000000000eb4760 .delay 1 (30000,30000,30000) L_0000000000eb4760/d; +L_00000000027ec5c0/d .functor NAND 1, L_0000000000eb47d0, L_0000000000eb4840, L_0000000000eb4060, C4<1>; +L_00000000027ec5c0 .delay 1 (30000,30000,30000) L_00000000027ec5c0/d; +L_00000000027ec860/d .functor NAND 1, L_0000000000eb45a0, L_0000000000eb4680, L_0000000000eb4760, L_00000000027ec5c0; +L_00000000027ec860 .delay 1 (40000,40000,40000) L_00000000027ec860/d; +v0000000000e03a10_0 .net "a", 0 0, L_0000000000eb4530; alias, 1 drivers +v0000000000e05450_0 .net "aout", 0 0, L_0000000000eb45a0; 1 drivers +v0000000000e03dd0_0 .net "b", 0 0, L_0000000000eb4610; alias, 1 drivers +v0000000000e04410_0 .net "bout", 0 0, L_0000000000eb4680; 1 drivers +v0000000000e04eb0_0 .net "c", 0 0, L_0000000000eb41b0; alias, 1 drivers +v0000000000e04730_0 .net "cout", 0 0, L_0000000000eb4760; 1 drivers +v0000000000e04910_0 .net "d", 0 0, L_0000000000eb4060; alias, 1 drivers +v0000000000e04af0_0 .net "dout", 0 0, L_00000000027ec5c0; 1 drivers +v0000000000e04b90_0 .net "ns0", 0 0, L_0000000000eb4840; 1 drivers +v0000000000df9ec0_0 .net "ns1", 0 0, L_0000000000eb47d0; 1 drivers +v0000000000df99c0_0 .net "out", 0 0, L_00000000027ec860; alias, 1 drivers +v0000000000dfa0a0_0 .net "s0", 0 0, L_0000000002791600; 1 drivers +v0000000000dfa1e0_0 .net "s1", 0 0, L_0000000002791420; 1 drivers +S_0000000000ed05c0 .scope generate, "aluBits[4]" "aluBits[4]" 4 49, 4 49 0, S_0000000000cc7490; + .timescale -9 -12; +P_0000000000f052e0 .param/l "i" 0 4 49, +C4<0100>; +L_00000000027ec710/d .functor XOR 1, L_00000000027944e0, v0000000000e68bd0_0, C4<0>, C4<0>; +L_00000000027ec710 .delay 1 (20000,20000,20000) L_00000000027ec710/d; +L_00000000027ed4a0/d .functor AND 1, v0000000000e67370_0, L_0000000002794580, C4<1>, C4<1>; +L_00000000027ed4a0 .delay 1 (30000,30000,30000) L_00000000027ed4a0/d; +L_00000000027ece10/d .functor AND 1, L_0000000002793ea0, L_000000000282c280, C4<1>, C4<1>; +L_00000000027ece10 .delay 1 (30000,30000,30000) L_00000000027ece10/d; +v000000000274b7f0_0 .net *"_s1", 0 0, L_00000000027944e0; 1 drivers +v000000000274d370_0 .net *"_s3", 0 0, L_0000000002794580; 1 drivers +v000000000274b1b0_0 .net *"_s9", 0 0, L_0000000002793ea0; 1 drivers +S_0000000000ed0a40 .scope module, "_bit" "aluFullBit" 4 52, 5 6 0, S_0000000000ed05c0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "res" + .port_info 1 /OUTPUT 1 "carryAND" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "cin" + .port_info 5 /INPUT 1 "ctrl0" + .port_info 6 /INPUT 2 "sel" +v000000000274bcf0_0 .net "a", 0 0, L_0000000002794c60; 1 drivers +v000000000274c470_0 .net "b", 0 0, L_00000000027935e0; 1 drivers +v000000000274b2f0_0 .net "carryAND", 0 0, L_00000000027ed0b0; 1 drivers +v000000000274d190_0 .net "cin", 0 0, L_0000000002793fe0; 1 drivers +v000000000274d2d0_0 .net "ctrl0", 0 0, L_0000000002792b40; 1 drivers +v000000000274c3d0_0 .net "nab", 0 0, L_00000000027ed900; 1 drivers +v000000000274d690_0 .net "orNOR", 0 0, L_00000000027ec470; 1 drivers +v000000000274d230_0 .net "res", 0 0, L_00000000027ec240; 1 drivers +v000000000274bf70_0 .net "sel", 1 0, v0000000000e625f0_0; alias, 1 drivers +v000000000274d410_0 .net "sumXOR", 0 0, L_00000000027ec940; 1 drivers +L_0000000002792aa0 .part v0000000000e625f0_0, 1, 1; +L_0000000002792c80 .part v0000000000e625f0_0, 0, 1; +S_0000000000ecffc0 .scope module, "alu" "aluBit" 5 18, 6 14 0, S_0000000000ed0a40; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sumXOR" + .port_info 1 /OUTPUT 1 "carryAND" + .port_info 2 /OUTPUT 1 "nab" + .port_info 3 /OUTPUT 1 "orNOR" + .port_info 4 /INPUT 1 "a" + .port_info 5 /INPUT 1 "b" + .port_info 6 /INPUT 1 "carryin" + .port_info 7 /INPUT 1 "i0" +L_00000000027ed900/d .functor NAND 1, L_0000000002794c60, L_00000000027935e0, C4<1>, C4<1>; +L_00000000027ed900 .delay 1 (20000,20000,20000) L_00000000027ed900/d; +L_00000000027ecf60/d .functor NAND 1, L_00000000027935e0, L_0000000002793fe0, C4<1>, C4<1>; +L_00000000027ecf60 .delay 1 (20000,20000,20000) L_00000000027ecf60/d; +L_00000000027ed5f0/d .functor NAND 1, L_0000000002794c60, L_0000000002793fe0, C4<1>, C4<1>; +L_00000000027ed5f0 .delay 1 (20000,20000,20000) L_00000000027ed5f0/d; +L_00000000027ed0b0/d .functor NAND 1, L_00000000027ed900, L_00000000027ed5f0, L_00000000027ecf60, C4<1>; +L_00000000027ed0b0 .delay 1 (30000,30000,30000) L_00000000027ed0b0/d; +L_00000000027ec940/d .functor XOR 1, L_0000000002794c60, L_00000000027935e0, L_0000000002793fe0, C4<0>; +L_00000000027ec940 .delay 1 (30000,30000,30000) L_00000000027ec940/d; +L_00000000027ecc50/d .functor NOR 1, L_0000000002794c60, L_00000000027935e0, C4<0>, C4<0>; +L_00000000027ecc50 .delay 1 (20000,20000,20000) L_00000000027ecc50/d; +L_00000000027ec470/d .functor XOR 1, L_00000000027ecc50, L_0000000002792b40, C4<0>, C4<0>; +L_00000000027ec470 .delay 1 (20000,20000,20000) L_00000000027ec470/d; +v0000000000dedf50_0 .net "a", 0 0, L_0000000002794c60; alias, 1 drivers +v0000000000dee4f0_0 .net "anorb", 0 0, L_00000000027ecc50; 1 drivers +v0000000000ded550_0 .net "b", 0 0, L_00000000027935e0; alias, 1 drivers +v0000000000dee770_0 .net "carryAND", 0 0, L_00000000027ed0b0; alias, 1 drivers +v0000000000dee8b0_0 .net "carryin", 0 0, L_0000000002793fe0; alias, 1 drivers +v0000000000deeb30_0 .net "i0", 0 0, L_0000000002792b40; alias, 1 drivers +v0000000000ded5f0_0 .net "nab", 0 0, L_00000000027ed900; alias, 1 drivers +v0000000000dd1dc0_0 .net "nac", 0 0, L_00000000027ed5f0; 1 drivers +v0000000000dd0ec0_0 .net "nbc", 0 0, L_00000000027ecf60; 1 drivers +v0000000000dd0420_0 .net "orNOR", 0 0, L_00000000027ec470; alias, 1 drivers +v0000000000dd0740_0 .net "sumXOR", 0 0, L_00000000027ec940; alias, 1 drivers +S_0000000000ed02c0 .scope module, "mux" "multiplexer" 5 20, 7 7 0, S_0000000000ed0a40; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "a" + .port_info 2 /INPUT 1 "b" + .port_info 3 /INPUT 1 "c" + .port_info 4 /INPUT 1 "d" + .port_info 5 /INPUT 1 "s1" + .port_info 6 /INPUT 1 "s0" +L_00000000027ec8d0/d .functor NOT 1, L_0000000002792c80, C4<0>, C4<0>, C4<0>; +L_00000000027ec8d0 .delay 1 (10000,10000,10000) L_00000000027ec8d0/d; +L_00000000027ec320/d .functor NOT 1, L_0000000002792aa0, C4<0>, C4<0>, C4<0>; +L_00000000027ec320 .delay 1 (10000,10000,10000) L_00000000027ec320/d; +L_00000000027ecda0/d .functor NAND 1, L_0000000002792aa0, L_0000000002792c80, L_00000000027ec940, C4<1>; +L_00000000027ecda0 .delay 1 (30000,30000,30000) L_00000000027ecda0/d; +L_00000000027edc10/d .functor NAND 1, L_0000000002792aa0, L_00000000027ec8d0, L_00000000027ec470, C4<1>; +L_00000000027edc10 .delay 1 (30000,30000,30000) L_00000000027edc10/d; +L_00000000027ed120/d .functor NAND 1, L_00000000027ec320, L_0000000002792c80, L_00000000027ed0b0, C4<1>; +L_00000000027ed120 .delay 1 (30000,30000,30000) L_00000000027ed120/d; +L_00000000027ecd30/d .functor NAND 1, L_00000000027ec320, L_00000000027ec8d0, L_00000000027ed900, C4<1>; +L_00000000027ecd30 .delay 1 (30000,30000,30000) L_00000000027ecd30/d; +L_00000000027ec240/d .functor NAND 1, L_00000000027ecda0, L_00000000027edc10, L_00000000027ed120, L_00000000027ecd30; +L_00000000027ec240 .delay 1 (40000,40000,40000) L_00000000027ec240/d; +v0000000000dd0f60_0 .net "a", 0 0, L_00000000027ec940; alias, 1 drivers +v0000000000dd1140_0 .net "aout", 0 0, L_00000000027ecda0; 1 drivers +v0000000000e00ad0_0 .net "b", 0 0, L_00000000027ec470; alias, 1 drivers +v0000000000dff590_0 .net "bout", 0 0, L_00000000027edc10; 1 drivers +v0000000000e01430_0 .net "c", 0 0, L_00000000027ed0b0; alias, 1 drivers +v0000000000e00cb0_0 .net "cout", 0 0, L_00000000027ed120; 1 drivers +v0000000000dffbd0_0 .net "d", 0 0, L_00000000027ed900; alias, 1 drivers +v0000000000e00210_0 .net "dout", 0 0, L_00000000027ecd30; 1 drivers +v0000000000d29cd0_0 .net "ns0", 0 0, L_00000000027ec8d0; 1 drivers +v000000000274d7d0_0 .net "ns1", 0 0, L_00000000027ec320; 1 drivers +v000000000274b070_0 .net "out", 0 0, L_00000000027ec240; alias, 1 drivers +v000000000274b4d0_0 .net "s0", 0 0, L_0000000002792c80; 1 drivers +v000000000274cab0_0 .net "s1", 0 0, L_0000000002792aa0; 1 drivers +S_0000000000f6c0b0 .scope generate, "aluBits[5]" "aluBits[5]" 4 49, 4 49 0, S_0000000000cc7490; + .timescale -9 -12; +P_0000000000f051a0 .param/l "i" 0 4 49, +C4<0101>; +L_00000000027ed270/d .functor XOR 1, L_0000000002792e60, v0000000000e68bd0_0, C4<0>, C4<0>; +L_00000000027ed270 .delay 1 (20000,20000,20000) L_00000000027ed270/d; +L_00000000027ece80/d .functor AND 1, v0000000000e67370_0, L_0000000002792f00, C4<1>, C4<1>; +L_00000000027ece80 .delay 1 (30000,30000,30000) L_00000000027ece80/d; +L_00000000027eccc0/d .functor AND 1, L_0000000002794620, L_000000000282c280, C4<1>, C4<1>; +L_00000000027eccc0 .delay 1 (30000,30000,30000) L_00000000027eccc0/d; +v000000000274b9d0_0 .net *"_s1", 0 0, L_0000000002792e60; 1 drivers +v000000000274bc50_0 .net *"_s3", 0 0, L_0000000002792f00; 1 drivers +v000000000274c150_0 .net *"_s9", 0 0, L_0000000002794620; 1 drivers +S_0000000000f6ccb0 .scope module, "_bit" "aluFullBit" 4 52, 5 6 0, S_0000000000f6c0b0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "res" + .port_info 1 /OUTPUT 1 "carryAND" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "cin" + .port_info 5 /INPUT 1 "ctrl0" + .port_info 6 /INPUT 2 "sel" +v000000000274b250_0 .net "a", 0 0, L_0000000002793720; 1 drivers +v000000000274bed0_0 .net "b", 0 0, L_00000000027941c0; 1 drivers +v000000000274d550_0 .net "carryAND", 0 0, L_00000000027ed430; 1 drivers +v000000000274c010_0 .net "cin", 0 0, L_0000000002793540; 1 drivers +v000000000274ca10_0 .net "ctrl0", 0 0, L_0000000002794da0; 1 drivers +v000000000274cf10_0 .net "nab", 0 0, L_00000000027ecef0; 1 drivers +v000000000274b430_0 .net "orNOR", 0 0, L_00000000027ecfd0; 1 drivers +v000000000274cbf0_0 .net "res", 0 0, L_00000000027ed970; 1 drivers +v000000000274b6b0_0 .net "sel", 1 0, v0000000000e625f0_0; alias, 1 drivers +v000000000274b930_0 .net "sumXOR", 0 0, L_00000000027ec2b0; 1 drivers +L_0000000002792d20 .part v0000000000e625f0_0, 1, 1; +L_0000000002793860 .part v0000000000e625f0_0, 0, 1; +S_0000000000f6b4b0 .scope module, "alu" "aluBit" 5 18, 6 14 0, S_0000000000f6ccb0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sumXOR" + .port_info 1 /OUTPUT 1 "carryAND" + .port_info 2 /OUTPUT 1 "nab" + .port_info 3 /OUTPUT 1 "orNOR" + .port_info 4 /INPUT 1 "a" + .port_info 5 /INPUT 1 "b" + .port_info 6 /INPUT 1 "carryin" + .port_info 7 /INPUT 1 "i0" +L_00000000027ecef0/d .functor NAND 1, L_0000000002793720, L_00000000027941c0, C4<1>, C4<1>; +L_00000000027ecef0 .delay 1 (20000,20000,20000) L_00000000027ecef0/d; +L_00000000027ecbe0/d .functor NAND 1, L_00000000027941c0, L_0000000002793540, C4<1>, C4<1>; +L_00000000027ecbe0 .delay 1 (20000,20000,20000) L_00000000027ecbe0/d; +L_00000000027ed2e0/d .functor NAND 1, L_0000000002793720, L_0000000002793540, C4<1>, C4<1>; +L_00000000027ed2e0 .delay 1 (20000,20000,20000) L_00000000027ed2e0/d; +L_00000000027ed430/d .functor NAND 1, L_00000000027ecef0, L_00000000027ed2e0, L_00000000027ecbe0, C4<1>; +L_00000000027ed430 .delay 1 (30000,30000,30000) L_00000000027ed430/d; +L_00000000027ec2b0/d .functor XOR 1, L_0000000002793720, L_00000000027941c0, L_0000000002793540, C4<0>; +L_00000000027ec2b0 .delay 1 (30000,30000,30000) L_00000000027ec2b0/d; +L_00000000027ec4e0/d .functor NOR 1, L_0000000002793720, L_00000000027941c0, C4<0>, C4<0>; +L_00000000027ec4e0 .delay 1 (20000,20000,20000) L_00000000027ec4e0/d; +L_00000000027ecfd0/d .functor XOR 1, L_00000000027ec4e0, L_0000000002794da0, C4<0>, C4<0>; +L_00000000027ecfd0 .delay 1 (20000,20000,20000) L_00000000027ecfd0/d; +v000000000274b610_0 .net "a", 0 0, L_0000000002793720; alias, 1 drivers +v000000000274b110_0 .net "anorb", 0 0, L_00000000027ec4e0; 1 drivers +v000000000274d5f0_0 .net "b", 0 0, L_00000000027941c0; alias, 1 drivers +v000000000274c830_0 .net "carryAND", 0 0, L_00000000027ed430; alias, 1 drivers +v000000000274cfb0_0 .net "carryin", 0 0, L_0000000002793540; alias, 1 drivers +v000000000274bb10_0 .net "i0", 0 0, L_0000000002794da0; alias, 1 drivers +v000000000274ba70_0 .net "nab", 0 0, L_00000000027ecef0; alias, 1 drivers +v000000000274cb50_0 .net "nac", 0 0, L_00000000027ed2e0; 1 drivers +v000000000274bd90_0 .net "nbc", 0 0, L_00000000027ecbe0; 1 drivers +v000000000274d4b0_0 .net "orNOR", 0 0, L_00000000027ecfd0; alias, 1 drivers +v000000000274d050_0 .net "sumXOR", 0 0, L_00000000027ec2b0; alias, 1 drivers +S_0000000000f6b7b0 .scope module, "mux" "multiplexer" 5 20, 7 7 0, S_0000000000f6ccb0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "a" + .port_info 2 /INPUT 1 "b" + .port_info 3 /INPUT 1 "c" + .port_info 4 /INPUT 1 "d" + .port_info 5 /INPUT 1 "s1" + .port_info 6 /INPUT 1 "s0" +L_00000000027ed820/d .functor NOT 1, L_0000000002793860, C4<0>, C4<0>, C4<0>; +L_00000000027ed820 .delay 1 (10000,10000,10000) L_00000000027ed820/d; +L_00000000027ec780/d .functor NOT 1, L_0000000002792d20, C4<0>, C4<0>, C4<0>; +L_00000000027ec780 .delay 1 (10000,10000,10000) L_00000000027ec780/d; +L_00000000027ec7f0/d .functor NAND 1, L_0000000002792d20, L_0000000002793860, L_00000000027ec2b0, C4<1>; +L_00000000027ec7f0 .delay 1 (30000,30000,30000) L_00000000027ec7f0/d; +L_00000000027ec9b0/d .functor NAND 1, L_0000000002792d20, L_00000000027ed820, L_00000000027ecfd0, C4<1>; +L_00000000027ec9b0 .delay 1 (30000,30000,30000) L_00000000027ec9b0/d; +L_00000000027ed510/d .functor NAND 1, L_00000000027ec780, L_0000000002793860, L_00000000027ed430, C4<1>; +L_00000000027ed510 .delay 1 (30000,30000,30000) L_00000000027ed510/d; +L_00000000027ec550/d .functor NAND 1, L_00000000027ec780, L_00000000027ed820, L_00000000027ecef0, C4<1>; +L_00000000027ec550 .delay 1 (30000,30000,30000) L_00000000027ec550/d; +L_00000000027ed970/d .functor NAND 1, L_00000000027ec7f0, L_00000000027ec9b0, L_00000000027ed510, L_00000000027ec550; +L_00000000027ed970 .delay 1 (40000,40000,40000) L_00000000027ed970/d; +v000000000274c8d0_0 .net "a", 0 0, L_00000000027ec2b0; alias, 1 drivers +v000000000274c0b0_0 .net "aout", 0 0, L_00000000027ec7f0; 1 drivers +v000000000274d0f0_0 .net "b", 0 0, L_00000000027ecfd0; alias, 1 drivers +v000000000274be30_0 .net "bout", 0 0, L_00000000027ec9b0; 1 drivers +v000000000274b890_0 .net "c", 0 0, L_00000000027ed430; alias, 1 drivers +v000000000274b570_0 .net "cout", 0 0, L_00000000027ed510; 1 drivers +v000000000274c970_0 .net "d", 0 0, L_00000000027ecef0; alias, 1 drivers +v000000000274cdd0_0 .net "dout", 0 0, L_00000000027ec550; 1 drivers +v000000000274b390_0 .net "ns0", 0 0, L_00000000027ed820; 1 drivers +v000000000274b750_0 .net "ns1", 0 0, L_00000000027ec780; 1 drivers +v000000000274bbb0_0 .net "out", 0 0, L_00000000027ed970; alias, 1 drivers +v000000000274d730_0 .net "s0", 0 0, L_0000000002793860; 1 drivers +v000000000274c510_0 .net "s1", 0 0, L_0000000002792d20; 1 drivers +S_0000000000f6c3b0 .scope generate, "aluBits[6]" "aluBits[6]" 4 49, 4 49 0, S_0000000000cc7490; + .timescale -9 -12; +P_0000000000f05320 .param/l "i" 0 4 49, +C4<0110>; +L_00000000027ec390/d .functor XOR 1, L_0000000002794e40, v0000000000e68bd0_0, C4<0>, C4<0>; +L_00000000027ec390 .delay 1 (20000,20000,20000) L_00000000027ec390/d; +L_00000000027ec630/d .functor AND 1, v0000000000e67370_0, L_0000000002793c20, C4<1>, C4<1>; +L_00000000027ec630 .delay 1 (30000,30000,30000) L_00000000027ec630/d; +L_00000000027eda50/d .functor AND 1, L_0000000002794ee0, L_000000000282c280, C4<1>, C4<1>; +L_00000000027eda50 .delay 1 (30000,30000,30000) L_00000000027eda50/d; +v0000000002746610_0 .net *"_s1", 0 0, L_0000000002794e40; 1 drivers +v0000000002746110_0 .net *"_s3", 0 0, L_0000000002793c20; 1 drivers +v0000000002747010_0 .net *"_s9", 0 0, L_0000000002794ee0; 1 drivers +S_0000000000f6bdb0 .scope module, "_bit" "aluFullBit" 4 52, 5 6 0, S_0000000000f6c3b0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "res" + .port_info 1 /OUTPUT 1 "carryAND" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "cin" + .port_info 5 /INPUT 1 "ctrl0" + .port_info 6 /INPUT 2 "sel" +v0000000002746930_0 .net "a", 0 0, L_00000000027948a0; 1 drivers +v0000000002748730_0 .net "b", 0 0, L_0000000002793220; 1 drivers +v0000000002748190_0 .net "carryAND", 0 0, L_00000000027eca90; 1 drivers +v00000000027467f0_0 .net "cin", 0 0, L_0000000002794a80; 1 drivers +v0000000002746430_0 .net "ctrl0", 0 0, L_0000000002792fa0; 1 drivers +v0000000002747290_0 .net "nab", 0 0, L_00000000027ec6a0; 1 drivers +v00000000027470b0_0 .net "orNOR", 0 0, L_00000000027ed350; 1 drivers +v0000000002747a10_0 .net "res", 0 0, L_00000000027ed9e0; 1 drivers +v0000000002747150_0 .net "sel", 1 0, v0000000000e625f0_0; alias, 1 drivers +v0000000002748550_0 .net "sumXOR", 0 0, L_00000000027ecb00; 1 drivers +L_0000000002794300 .part v0000000000e625f0_0, 1, 1; +L_0000000002794440 .part v0000000000e625f0_0, 0, 1; +S_0000000000f6c230 .scope module, "alu" "aluBit" 5 18, 6 14 0, S_0000000000f6bdb0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sumXOR" + .port_info 1 /OUTPUT 1 "carryAND" + .port_info 2 /OUTPUT 1 "nab" + .port_info 3 /OUTPUT 1 "orNOR" + .port_info 4 /INPUT 1 "a" + .port_info 5 /INPUT 1 "b" + .port_info 6 /INPUT 1 "carryin" + .port_info 7 /INPUT 1 "i0" +L_00000000027ec6a0/d .functor NAND 1, L_00000000027948a0, L_0000000002793220, C4<1>, C4<1>; +L_00000000027ec6a0 .delay 1 (20000,20000,20000) L_00000000027ec6a0/d; +L_00000000027ed040/d .functor NAND 1, L_0000000002793220, L_0000000002794a80, C4<1>, C4<1>; +L_00000000027ed040 .delay 1 (20000,20000,20000) L_00000000027ed040/d; +L_00000000027eca20/d .functor NAND 1, L_00000000027948a0, L_0000000002794a80, C4<1>, C4<1>; +L_00000000027eca20 .delay 1 (20000,20000,20000) L_00000000027eca20/d; +L_00000000027eca90/d .functor NAND 1, L_00000000027ec6a0, L_00000000027eca20, L_00000000027ed040, C4<1>; +L_00000000027eca90 .delay 1 (30000,30000,30000) L_00000000027eca90/d; +L_00000000027ecb00/d .functor XOR 1, L_00000000027948a0, L_0000000002793220, L_0000000002794a80, C4<0>; +L_00000000027ecb00 .delay 1 (30000,30000,30000) L_00000000027ecb00/d; +L_00000000027ec160/d .functor NOR 1, L_00000000027948a0, L_0000000002793220, C4<0>, C4<0>; +L_00000000027ec160 .delay 1 (20000,20000,20000) L_00000000027ec160/d; +L_00000000027ed350/d .functor XOR 1, L_00000000027ec160, L_0000000002792fa0, C4<0>, C4<0>; +L_00000000027ed350 .delay 1 (20000,20000,20000) L_00000000027ed350/d; +v000000000274c1f0_0 .net "a", 0 0, L_00000000027948a0; alias, 1 drivers +v000000000274c290_0 .net "anorb", 0 0, L_00000000027ec160; 1 drivers +v000000000274c330_0 .net "b", 0 0, L_0000000002793220; alias, 1 drivers +v000000000274c5b0_0 .net "carryAND", 0 0, L_00000000027eca90; alias, 1 drivers +v000000000274c650_0 .net "carryin", 0 0, L_0000000002794a80; alias, 1 drivers +v000000000274c6f0_0 .net "i0", 0 0, L_0000000002792fa0; alias, 1 drivers +v000000000274cc90_0 .net "nab", 0 0, L_00000000027ec6a0; alias, 1 drivers +v000000000274cd30_0 .net "nac", 0 0, L_00000000027eca20; 1 drivers +v000000000274ce70_0 .net "nbc", 0 0, L_00000000027ed040; 1 drivers +v000000000274c790_0 .net "orNOR", 0 0, L_00000000027ed350; alias, 1 drivers +v000000000274daf0_0 .net "sumXOR", 0 0, L_00000000027ecb00; alias, 1 drivers +S_0000000000f6c530 .scope module, "mux" "multiplexer" 5 20, 7 7 0, S_0000000000f6bdb0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "a" + .port_info 2 /INPUT 1 "b" + .port_info 3 /INPUT 1 "c" + .port_info 4 /INPUT 1 "d" + .port_info 5 /INPUT 1 "s1" + .port_info 6 /INPUT 1 "s0" +L_00000000027ed200/d .functor NOT 1, L_0000000002794440, C4<0>, C4<0>, C4<0>; +L_00000000027ed200 .delay 1 (10000,10000,10000) L_00000000027ed200/d; +L_00000000027ed190/d .functor NOT 1, L_0000000002794300, C4<0>, C4<0>, C4<0>; +L_00000000027ed190 .delay 1 (10000,10000,10000) L_00000000027ed190/d; +L_00000000027ecb70/d .functor NAND 1, L_0000000002794300, L_0000000002794440, L_00000000027ecb00, C4<1>; +L_00000000027ecb70 .delay 1 (30000,30000,30000) L_00000000027ecb70/d; +L_00000000027ed3c0/d .functor NAND 1, L_0000000002794300, L_00000000027ed200, L_00000000027ed350, C4<1>; +L_00000000027ed3c0 .delay 1 (30000,30000,30000) L_00000000027ed3c0/d; +L_00000000027ed580/d .functor NAND 1, L_00000000027ed190, L_0000000002794440, L_00000000027eca90, C4<1>; +L_00000000027ed580 .delay 1 (30000,30000,30000) L_00000000027ed580/d; +L_00000000027edc80/d .functor NAND 1, L_00000000027ed190, L_00000000027ed200, L_00000000027ec6a0, C4<1>; +L_00000000027edc80 .delay 1 (30000,30000,30000) L_00000000027edc80/d; +L_00000000027ed9e0/d .functor NAND 1, L_00000000027ecb70, L_00000000027ed3c0, L_00000000027ed580, L_00000000027edc80; +L_00000000027ed9e0 .delay 1 (40000,40000,40000) L_00000000027ed9e0/d; +v000000000274db90_0 .net "a", 0 0, L_00000000027ecb00; alias, 1 drivers +v000000000274da50_0 .net "aout", 0 0, L_00000000027ecb70; 1 drivers +v000000000274deb0_0 .net "b", 0 0, L_00000000027ed350; alias, 1 drivers +v000000000274df50_0 .net "bout", 0 0, L_00000000027ed3c0; 1 drivers +v000000000274d870_0 .net "c", 0 0, L_00000000027eca90; alias, 1 drivers +v000000000274d910_0 .net "cout", 0 0, L_00000000027ed580; 1 drivers +v000000000274d9b0_0 .net "d", 0 0, L_00000000027ec6a0; alias, 1 drivers +v000000000274de10_0 .net "dout", 0 0, L_00000000027edc80; 1 drivers +v000000000274dc30_0 .net "ns0", 0 0, L_00000000027ed200; 1 drivers +v000000000274dcd0_0 .net "ns1", 0 0, L_00000000027ed190; 1 drivers +v000000000274dd70_0 .net "out", 0 0, L_00000000027ed9e0; alias, 1 drivers +v00000000027484b0_0 .net "s0", 0 0, L_0000000002794440; 1 drivers +v00000000027464d0_0 .net "s1", 0 0, L_0000000002794300; 1 drivers +S_0000000000f6b630 .scope generate, "aluBits[7]" "aluBits[7]" 4 49, 4 49 0, S_0000000000cc7490; + .timescale -9 -12; +P_0000000000f05620 .param/l "i" 0 4 49, +C4<0111>; +L_00000000027ed660/d .functor XOR 1, L_0000000002793040, v0000000000e68bd0_0, C4<0>, C4<0>; +L_00000000027ed660 .delay 1 (20000,20000,20000) L_00000000027ed660/d; +L_00000000027ed6d0/d .functor AND 1, v0000000000e67370_0, L_0000000002792dc0, C4<1>, C4<1>; +L_00000000027ed6d0 .delay 1 (30000,30000,30000) L_00000000027ed6d0/d; +L_00000000027ede40/d .functor AND 1, L_0000000002793680, L_000000000282c280, C4<1>, C4<1>; +L_00000000027ede40 .delay 1 (30000,30000,30000) L_00000000027ede40/d; +v0000000002747e70_0 .net *"_s1", 0 0, L_0000000002793040; 1 drivers +v0000000002747f10_0 .net *"_s3", 0 0, L_0000000002792dc0; 1 drivers +v00000000027466b0_0 .net *"_s9", 0 0, L_0000000002793680; 1 drivers +S_0000000000f6c9b0 .scope module, "_bit" "aluFullBit" 4 52, 5 6 0, S_0000000000f6b630; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "res" + .port_info 1 /OUTPUT 1 "carryAND" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "cin" + .port_info 5 /INPUT 1 "ctrl0" + .port_info 6 /INPUT 2 "sel" +v00000000027480f0_0 .net "a", 0 0, L_00000000027950c0; 1 drivers +v0000000002746a70_0 .net "b", 0 0, L_00000000027932c0; 1 drivers +v00000000027462f0_0 .net "carryAND", 0 0, L_00000000027ec1d0; 1 drivers +v0000000002747790_0 .net "cin", 0 0, L_0000000002793360; 1 drivers +v0000000002747ab0_0 .net "ctrl0", 0 0, L_0000000002794760; 1 drivers +v0000000002747b50_0 .net "nab", 0 0, L_00000000027ed740; 1 drivers +v0000000002746b10_0 .net "orNOR", 0 0, L_00000000027edba0; 1 drivers +v0000000002746390_0 .net "res", 0 0, L_00000000027eddd0; 1 drivers +v0000000002746570_0 .net "sel", 1 0, v0000000000e625f0_0; alias, 1 drivers +v0000000002746f70_0 .net "sumXOR", 0 0, L_00000000027ed890; 1 drivers +L_00000000027946c0 .part v0000000000e625f0_0, 1, 1; +L_0000000002794080 .part v0000000000e625f0_0, 0, 1; +S_0000000000f6c6b0 .scope module, "alu" "aluBit" 5 18, 6 14 0, S_0000000000f6c9b0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sumXOR" + .port_info 1 /OUTPUT 1 "carryAND" + .port_info 2 /OUTPUT 1 "nab" + .port_info 3 /OUTPUT 1 "orNOR" + .port_info 4 /INPUT 1 "a" + .port_info 5 /INPUT 1 "b" + .port_info 6 /INPUT 1 "carryin" + .port_info 7 /INPUT 1 "i0" +L_00000000027ed740/d .functor NAND 1, L_00000000027950c0, L_00000000027932c0, C4<1>, C4<1>; +L_00000000027ed740 .delay 1 (20000,20000,20000) L_00000000027ed740/d; +L_00000000027ed7b0/d .functor NAND 1, L_00000000027932c0, L_0000000002793360, C4<1>, C4<1>; +L_00000000027ed7b0 .delay 1 (20000,20000,20000) L_00000000027ed7b0/d; +L_00000000027edac0/d .functor NAND 1, L_00000000027950c0, L_0000000002793360, C4<1>, C4<1>; +L_00000000027edac0 .delay 1 (20000,20000,20000) L_00000000027edac0/d; +L_00000000027ec1d0/d .functor NAND 1, L_00000000027ed740, L_00000000027edac0, L_00000000027ed7b0, C4<1>; +L_00000000027ec1d0 .delay 1 (30000,30000,30000) L_00000000027ec1d0/d; +L_00000000027ed890/d .functor XOR 1, L_00000000027950c0, L_00000000027932c0, L_0000000002793360, C4<0>; +L_00000000027ed890 .delay 1 (30000,30000,30000) L_00000000027ed890/d; +L_00000000027edb30/d .functor NOR 1, L_00000000027950c0, L_00000000027932c0, C4<0>, C4<0>; +L_00000000027edb30 .delay 1 (20000,20000,20000) L_00000000027edb30/d; +L_00000000027edba0/d .functor XOR 1, L_00000000027edb30, L_0000000002794760, C4<0>, C4<0>; +L_00000000027edba0 .delay 1 (20000,20000,20000) L_00000000027edba0/d; +v0000000002746890_0 .net "a", 0 0, L_00000000027950c0; alias, 1 drivers +v00000000027471f0_0 .net "anorb", 0 0, L_00000000027edb30; 1 drivers +v0000000002746d90_0 .net "b", 0 0, L_00000000027932c0; alias, 1 drivers +v0000000002746e30_0 .net "carryAND", 0 0, L_00000000027ec1d0; alias, 1 drivers +v0000000002746bb0_0 .net "carryin", 0 0, L_0000000002793360; alias, 1 drivers +v0000000002748230_0 .net "i0", 0 0, L_0000000002794760; alias, 1 drivers +v0000000002748050_0 .net "nab", 0 0, L_00000000027ed740; alias, 1 drivers +v0000000002747830_0 .net "nac", 0 0, L_00000000027edac0; 1 drivers +v0000000002748690_0 .net "nbc", 0 0, L_00000000027ed7b0; 1 drivers +v0000000002747fb0_0 .net "orNOR", 0 0, L_00000000027edba0; alias, 1 drivers +v0000000002747330_0 .net "sumXOR", 0 0, L_00000000027ed890; alias, 1 drivers +S_0000000000f6c830 .scope module, "mux" "multiplexer" 5 20, 7 7 0, S_0000000000f6c9b0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "a" + .port_info 2 /INPUT 1 "b" + .port_info 3 /INPUT 1 "c" + .port_info 4 /INPUT 1 "d" + .port_info 5 /INPUT 1 "s1" + .port_info 6 /INPUT 1 "s0" +L_00000000027edcf0/d .functor NOT 1, L_0000000002794080, C4<0>, C4<0>, C4<0>; +L_00000000027edcf0 .delay 1 (10000,10000,10000) L_00000000027edcf0/d; +L_00000000027edeb0/d .functor NOT 1, L_00000000027946c0, C4<0>, C4<0>, C4<0>; +L_00000000027edeb0 .delay 1 (10000,10000,10000) L_00000000027edeb0/d; +L_00000000027edf90/d .functor NAND 1, L_00000000027946c0, L_0000000002794080, L_00000000027ed890, C4<1>; +L_00000000027edf90 .delay 1 (30000,30000,30000) L_00000000027edf90/d; +L_00000000027ee070/d .functor NAND 1, L_00000000027946c0, L_00000000027edcf0, L_00000000027edba0, C4<1>; +L_00000000027ee070 .delay 1 (30000,30000,30000) L_00000000027ee070/d; +L_00000000027ee000/d .functor NAND 1, L_00000000027edeb0, L_0000000002794080, L_00000000027ec1d0, C4<1>; +L_00000000027ee000 .delay 1 (30000,30000,30000) L_00000000027ee000/d; +L_00000000027edd60/d .functor NAND 1, L_00000000027edeb0, L_00000000027edcf0, L_00000000027ed740, C4<1>; +L_00000000027edd60 .delay 1 (30000,30000,30000) L_00000000027edd60/d; +L_00000000027eddd0/d .functor NAND 1, L_00000000027edf90, L_00000000027ee070, L_00000000027ee000, L_00000000027edd60; +L_00000000027eddd0 .delay 1 (40000,40000,40000) L_00000000027eddd0/d; +v00000000027473d0_0 .net "a", 0 0, L_00000000027ed890; alias, 1 drivers +v0000000002746070_0 .net "aout", 0 0, L_00000000027edf90; 1 drivers +v00000000027487d0_0 .net "b", 0 0, L_00000000027edba0; alias, 1 drivers +v00000000027482d0_0 .net "bout", 0 0, L_00000000027ee070; 1 drivers +v0000000002746cf0_0 .net "c", 0 0, L_00000000027ec1d0; alias, 1 drivers +v0000000002748370_0 .net "cout", 0 0, L_00000000027ee000; 1 drivers +v0000000002747470_0 .net "d", 0 0, L_00000000027ed740; alias, 1 drivers +v0000000002746250_0 .net "dout", 0 0, L_00000000027edd60; 1 drivers +v00000000027461b0_0 .net "ns0", 0 0, L_00000000027edcf0; 1 drivers +v00000000027469d0_0 .net "ns1", 0 0, L_00000000027edeb0; 1 drivers +v0000000002746ed0_0 .net "out", 0 0, L_00000000027eddd0; alias, 1 drivers +v0000000002747510_0 .net "s0", 0 0, L_0000000002794080; 1 drivers +v00000000027476f0_0 .net "s1", 0 0, L_00000000027946c0; 1 drivers +S_0000000000f6b030 .scope generate, "aluBits[8]" "aluBits[8]" 4 49, 4 49 0, S_0000000000cc7490; + .timescale -9 -12; +P_0000000000f05960 .param/l "i" 0 4 49, +C4<01000>; +L_00000000027edf20/d .functor XOR 1, L_0000000002793cc0, v0000000000e68bd0_0, C4<0>, C4<0>; +L_00000000027edf20 .delay 1 (20000,20000,20000) L_00000000027edf20/d; +L_00000000027f6f10/d .functor AND 1, v0000000000e67370_0, L_00000000027937c0, C4<1>, C4<1>; +L_00000000027f6f10 .delay 1 (30000,30000,30000) L_00000000027f6f10/d; +L_00000000027f7610/d .functor AND 1, L_0000000002793a40, L_000000000282c280, C4<1>, C4<1>; +L_00000000027f7610 .delay 1 (30000,30000,30000) L_00000000027f7610/d; +v0000000002748910_0 .net *"_s1", 0 0, L_0000000002793cc0; 1 drivers +v0000000002749450_0 .net *"_s3", 0 0, L_00000000027937c0; 1 drivers +v0000000002749630_0 .net *"_s9", 0 0, L_0000000002793a40; 1 drivers +S_0000000000f6cb30 .scope module, "_bit" "aluFullBit" 4 52, 5 6 0, S_0000000000f6b030; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "res" + .port_info 1 /OUTPUT 1 "carryAND" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "cin" + .port_info 5 /INPUT 1 "ctrl0" + .port_info 6 /INPUT 2 "sel" +v000000000274a3f0_0 .net "a", 0 0, L_00000000027939a0; 1 drivers +v00000000027491d0_0 .net "b", 0 0, L_0000000002794260; 1 drivers +v0000000002748eb0_0 .net "carryAND", 0 0, L_00000000027f7d10; 1 drivers +v0000000002749810_0 .net "cin", 0 0, L_0000000002794b20; 1 drivers +v000000000274ab70_0 .net "ctrl0", 0 0, L_0000000002794940; 1 drivers +v0000000002749d10_0 .net "nab", 0 0, L_00000000027f6b20; 1 drivers +v0000000002749270_0 .net "orNOR", 0 0, L_00000000027f78b0; 1 drivers +v0000000002749310_0 .net "res", 0 0, L_00000000027f6180; 1 drivers +v0000000002748e10_0 .net "sel", 1 0, v0000000000e625f0_0; alias, 1 drivers +v00000000027493b0_0 .net "sumXOR", 0 0, L_00000000027f74c0; 1 drivers +L_0000000002793400 .part v0000000000e625f0_0, 1, 1; +L_0000000002793900 .part v0000000000e625f0_0, 0, 1; +S_0000000000f6b930 .scope module, "alu" "aluBit" 5 18, 6 14 0, S_0000000000f6cb30; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sumXOR" + .port_info 1 /OUTPUT 1 "carryAND" + .port_info 2 /OUTPUT 1 "nab" + .port_info 3 /OUTPUT 1 "orNOR" + .port_info 4 /INPUT 1 "a" + .port_info 5 /INPUT 1 "b" + .port_info 6 /INPUT 1 "carryin" + .port_info 7 /INPUT 1 "i0" +L_00000000027f6b20/d .functor NAND 1, L_00000000027939a0, L_0000000002794260, C4<1>, C4<1>; +L_00000000027f6b20 .delay 1 (20000,20000,20000) L_00000000027f6b20/d; +L_00000000027f6500/d .functor NAND 1, L_0000000002794260, L_0000000002794b20, C4<1>, C4<1>; +L_00000000027f6500 .delay 1 (20000,20000,20000) L_00000000027f6500/d; +L_00000000027f6b90/d .functor NAND 1, L_00000000027939a0, L_0000000002794b20, C4<1>, C4<1>; +L_00000000027f6b90 .delay 1 (20000,20000,20000) L_00000000027f6b90/d; +L_00000000027f7d10/d .functor NAND 1, L_00000000027f6b20, L_00000000027f6b90, L_00000000027f6500, C4<1>; +L_00000000027f7d10 .delay 1 (30000,30000,30000) L_00000000027f7d10/d; +L_00000000027f74c0/d .functor XOR 1, L_00000000027939a0, L_0000000002794260, L_0000000002794b20, C4<0>; +L_00000000027f74c0 .delay 1 (30000,30000,30000) L_00000000027f74c0/d; +L_00000000027f68f0/d .functor NOR 1, L_00000000027939a0, L_0000000002794260, C4<0>, C4<0>; +L_00000000027f68f0 .delay 1 (20000,20000,20000) L_00000000027f68f0/d; +L_00000000027f78b0/d .functor XOR 1, L_00000000027f68f0, L_0000000002794940, C4<0>, C4<0>; +L_00000000027f78b0 .delay 1 (20000,20000,20000) L_00000000027f78b0/d; +v0000000002746750_0 .net "a", 0 0, L_00000000027939a0; alias, 1 drivers +v0000000002746c50_0 .net "anorb", 0 0, L_00000000027f68f0; 1 drivers +v0000000002748410_0 .net "b", 0 0, L_0000000002794260; alias, 1 drivers +v00000000027475b0_0 .net "carryAND", 0 0, L_00000000027f7d10; alias, 1 drivers +v0000000002747bf0_0 .net "carryin", 0 0, L_0000000002794b20; alias, 1 drivers +v0000000002747650_0 .net "i0", 0 0, L_0000000002794940; alias, 1 drivers +v00000000027478d0_0 .net "nab", 0 0, L_00000000027f6b20; alias, 1 drivers +v00000000027485f0_0 .net "nac", 0 0, L_00000000027f6b90; 1 drivers +v0000000002747970_0 .net "nbc", 0 0, L_00000000027f6500; 1 drivers +v0000000002747c90_0 .net "orNOR", 0 0, L_00000000027f78b0; alias, 1 drivers +v0000000002747d30_0 .net "sumXOR", 0 0, L_00000000027f74c0; alias, 1 drivers +S_0000000000f6ce30 .scope module, "mux" "multiplexer" 5 20, 7 7 0, S_0000000000f6cb30; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "a" + .port_info 2 /INPUT 1 "b" + .port_info 3 /INPUT 1 "c" + .port_info 4 /INPUT 1 "d" + .port_info 5 /INPUT 1 "s1" + .port_info 6 /INPUT 1 "s0" +L_00000000027f6880/d .functor NOT 1, L_0000000002793900, C4<0>, C4<0>, C4<0>; +L_00000000027f6880 .delay 1 (10000,10000,10000) L_00000000027f6880/d; +L_00000000027f65e0/d .functor NOT 1, L_0000000002793400, C4<0>, C4<0>, C4<0>; +L_00000000027f65e0 .delay 1 (10000,10000,10000) L_00000000027f65e0/d; +L_00000000027f70d0/d .functor NAND 1, L_0000000002793400, L_0000000002793900, L_00000000027f74c0, C4<1>; +L_00000000027f70d0 .delay 1 (30000,30000,30000) L_00000000027f70d0/d; +L_00000000027f6420/d .functor NAND 1, L_0000000002793400, L_00000000027f6880, L_00000000027f78b0, C4<1>; +L_00000000027f6420 .delay 1 (30000,30000,30000) L_00000000027f6420/d; +L_00000000027f6ce0/d .functor NAND 1, L_00000000027f65e0, L_0000000002793900, L_00000000027f7d10, C4<1>; +L_00000000027f6ce0 .delay 1 (30000,30000,30000) L_00000000027f6ce0/d; +L_00000000027f7ae0/d .functor NAND 1, L_00000000027f65e0, L_00000000027f6880, L_00000000027f6b20, C4<1>; +L_00000000027f7ae0 .delay 1 (30000,30000,30000) L_00000000027f7ae0/d; +L_00000000027f6180/d .functor NAND 1, L_00000000027f70d0, L_00000000027f6420, L_00000000027f6ce0, L_00000000027f7ae0; +L_00000000027f6180 .delay 1 (40000,40000,40000) L_00000000027f6180/d; +v0000000002747dd0_0 .net "a", 0 0, L_00000000027f74c0; alias, 1 drivers +v000000000274aa30_0 .net "aout", 0 0, L_00000000027f70d0; 1 drivers +v0000000002749a90_0 .net "b", 0 0, L_00000000027f78b0; alias, 1 drivers +v0000000002748af0_0 .net "bout", 0 0, L_00000000027f6420; 1 drivers +v000000000274aad0_0 .net "c", 0 0, L_00000000027f7d10; alias, 1 drivers +v0000000002748f50_0 .net "cout", 0 0, L_00000000027f6ce0; 1 drivers +v0000000002748ff0_0 .net "d", 0 0, L_00000000027f6b20; alias, 1 drivers +v0000000002748c30_0 .net "dout", 0 0, L_00000000027f7ae0; 1 drivers +v0000000002749090_0 .net "ns0", 0 0, L_00000000027f6880; 1 drivers +v00000000027498b0_0 .net "ns1", 0 0, L_00000000027f65e0; 1 drivers +v000000000274a210_0 .net "out", 0 0, L_00000000027f6180; alias, 1 drivers +v0000000002749950_0 .net "s0", 0 0, L_0000000002793900; 1 drivers +v0000000002749130_0 .net "s1", 0 0, L_0000000002793400; 1 drivers +S_0000000000f6bf30 .scope generate, "aluBits[9]" "aluBits[9]" 4 49, 4 49 0, S_0000000000cc7490; + .timescale -9 -12; +P_0000000000f05720 .param/l "i" 0 4 49, +C4<01001>; +L_00000000027f6960/d .functor XOR 1, L_0000000002793ae0, v0000000000e68bd0_0, C4<0>, C4<0>; +L_00000000027f6960 .delay 1 (20000,20000,20000) L_00000000027f6960/d; +L_00000000027f6d50/d .functor AND 1, v0000000000e67370_0, L_0000000002792be0, C4<1>, C4<1>; +L_00000000027f6d50 .delay 1 (30000,30000,30000) L_00000000027f6d50/d; +L_00000000027f7300/d .functor AND 1, L_0000000002793b80, L_000000000282c280, C4<1>, C4<1>; +L_00000000027f7300 .delay 1 (30000,30000,30000) L_00000000027f7300/d; +v000000000274a490_0 .net *"_s1", 0 0, L_0000000002793ae0; 1 drivers +v000000000274a530_0 .net *"_s3", 0 0, L_0000000002792be0; 1 drivers +v000000000274a5d0_0 .net *"_s9", 0 0, L_0000000002793b80; 1 drivers +S_0000000000f6bab0 .scope module, "_bit" "aluFullBit" 4 52, 5 6 0, S_0000000000f6bf30; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "res" + .port_info 1 /OUTPUT 1 "carryAND" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "cin" + .port_info 5 /INPUT 1 "ctrl0" + .port_info 6 /INPUT 2 "sel" +v000000000274a990_0 .net "a", 0 0, L_0000000002792960; 1 drivers +v000000000274a7b0_0 .net "b", 0 0, L_0000000002794d00; 1 drivers +v0000000002748d70_0 .net "carryAND", 0 0, L_00000000027f7990; 1 drivers +v0000000002749bd0_0 .net "cin", 0 0, L_0000000002794800; 1 drivers +v0000000002749c70_0 .net "ctrl0", 0 0, L_0000000002794120; 1 drivers +v0000000002749db0_0 .net "nab", 0 0, L_00000000027f6490; 1 drivers +v0000000002749ef0_0 .net "orNOR", 0 0, L_00000000027f6650; 1 drivers +v0000000002749e50_0 .net "res", 0 0, L_00000000027f73e0; 1 drivers +v0000000002749f90_0 .net "sel", 1 0, v0000000000e625f0_0; alias, 1 drivers +v000000000274a2b0_0 .net "sumXOR", 0 0, L_00000000027f62d0; 1 drivers +L_0000000002794bc0 .part v0000000000e625f0_0, 1, 1; +L_00000000027943a0 .part v0000000000e625f0_0, 0, 1; +S_0000000000f6b1b0 .scope module, "alu" "aluBit" 5 18, 6 14 0, S_0000000000f6bab0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sumXOR" + .port_info 1 /OUTPUT 1 "carryAND" + .port_info 2 /OUTPUT 1 "nab" + .port_info 3 /OUTPUT 1 "orNOR" + .port_info 4 /INPUT 1 "a" + .port_info 5 /INPUT 1 "b" + .port_info 6 /INPUT 1 "carryin" + .port_info 7 /INPUT 1 "i0" +L_00000000027f6490/d .functor NAND 1, L_0000000002792960, L_0000000002794d00, C4<1>, C4<1>; +L_00000000027f6490 .delay 1 (20000,20000,20000) L_00000000027f6490/d; +L_00000000027f69d0/d .functor NAND 1, L_0000000002794d00, L_0000000002794800, C4<1>, C4<1>; +L_00000000027f69d0 .delay 1 (20000,20000,20000) L_00000000027f69d0/d; +L_00000000027f6340/d .functor NAND 1, L_0000000002792960, L_0000000002794800, C4<1>, C4<1>; +L_00000000027f6340 .delay 1 (20000,20000,20000) L_00000000027f6340/d; +L_00000000027f7990/d .functor NAND 1, L_00000000027f6490, L_00000000027f6340, L_00000000027f69d0, C4<1>; +L_00000000027f7990 .delay 1 (30000,30000,30000) L_00000000027f7990/d; +L_00000000027f62d0/d .functor XOR 1, L_0000000002792960, L_0000000002794d00, L_0000000002794800, C4<0>; +L_00000000027f62d0 .delay 1 (30000,30000,30000) L_00000000027f62d0/d; +L_00000000027f6e30/d .functor NOR 1, L_0000000002792960, L_0000000002794d00, C4<0>, C4<0>; +L_00000000027f6e30 .delay 1 (20000,20000,20000) L_00000000027f6e30/d; +L_00000000027f6650/d .functor XOR 1, L_00000000027f6e30, L_0000000002794120, C4<0>, C4<0>; +L_00000000027f6650 .delay 1 (20000,20000,20000) L_00000000027f6650/d; +v000000000274ac10_0 .net "a", 0 0, L_0000000002792960; alias, 1 drivers +v000000000274a030_0 .net "anorb", 0 0, L_00000000027f6e30; 1 drivers +v000000000274af30_0 .net "b", 0 0, L_0000000002794d00; alias, 1 drivers +v000000000274acb0_0 .net "carryAND", 0 0, L_00000000027f7990; alias, 1 drivers +v0000000002748a50_0 .net "carryin", 0 0, L_0000000002794800; alias, 1 drivers +v0000000002748cd0_0 .net "i0", 0 0, L_0000000002794120; alias, 1 drivers +v000000000274ae90_0 .net "nab", 0 0, L_00000000027f6490; alias, 1 drivers +v000000000274afd0_0 .net "nac", 0 0, L_00000000027f6340; 1 drivers +v00000000027499f0_0 .net "nbc", 0 0, L_00000000027f69d0; 1 drivers +v000000000274a350_0 .net "orNOR", 0 0, L_00000000027f6650; alias, 1 drivers +v000000000274a0d0_0 .net "sumXOR", 0 0, L_00000000027f62d0; alias, 1 drivers +S_0000000000f6b330 .scope module, "mux" "multiplexer" 5 20, 7 7 0, S_0000000000f6bab0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "a" + .port_info 2 /INPUT 1 "b" + .port_info 3 /INPUT 1 "c" + .port_info 4 /INPUT 1 "d" + .port_info 5 /INPUT 1 "s1" + .port_info 6 /INPUT 1 "s0" +L_00000000027f7a00/d .functor NOT 1, L_00000000027943a0, C4<0>, C4<0>, C4<0>; +L_00000000027f7a00 .delay 1 (10000,10000,10000) L_00000000027f7a00/d; +L_00000000027f7370/d .functor NOT 1, L_0000000002794bc0, C4<0>, C4<0>, C4<0>; +L_00000000027f7370 .delay 1 (10000,10000,10000) L_00000000027f7370/d; +L_00000000027f6ab0/d .functor NAND 1, L_0000000002794bc0, L_00000000027943a0, L_00000000027f62d0, C4<1>; +L_00000000027f6ab0 .delay 1 (30000,30000,30000) L_00000000027f6ab0/d; +L_00000000027f6ea0/d .functor NAND 1, L_0000000002794bc0, L_00000000027f7a00, L_00000000027f6650, C4<1>; +L_00000000027f6ea0 .delay 1 (30000,30000,30000) L_00000000027f6ea0/d; +L_00000000027f7530/d .functor NAND 1, L_00000000027f7370, L_00000000027943a0, L_00000000027f7990, C4<1>; +L_00000000027f7530 .delay 1 (30000,30000,30000) L_00000000027f7530/d; +L_00000000027f6a40/d .functor NAND 1, L_00000000027f7370, L_00000000027f7a00, L_00000000027f6490, C4<1>; +L_00000000027f6a40 .delay 1 (30000,30000,30000) L_00000000027f6a40/d; +L_00000000027f73e0/d .functor NAND 1, L_00000000027f6ab0, L_00000000027f6ea0, L_00000000027f7530, L_00000000027f6a40; +L_00000000027f73e0 .delay 1 (40000,40000,40000) L_00000000027f73e0/d; +v000000000274ad50_0 .net "a", 0 0, L_00000000027f62d0; alias, 1 drivers +v00000000027494f0_0 .net "aout", 0 0, L_00000000027f6ab0; 1 drivers +v0000000002748870_0 .net "b", 0 0, L_00000000027f6650; alias, 1 drivers +v000000000274a670_0 .net "bout", 0 0, L_00000000027f6ea0; 1 drivers +v0000000002749590_0 .net "c", 0 0, L_00000000027f7990; alias, 1 drivers +v00000000027489b0_0 .net "cout", 0 0, L_00000000027f7530; 1 drivers +v00000000027496d0_0 .net "d", 0 0, L_00000000027f6490; alias, 1 drivers +v0000000002749b30_0 .net "dout", 0 0, L_00000000027f6a40; 1 drivers +v000000000274a710_0 .net "ns0", 0 0, L_00000000027f7a00; 1 drivers +v0000000002749770_0 .net "ns1", 0 0, L_00000000027f7370; 1 drivers +v0000000002748b90_0 .net "out", 0 0, L_00000000027f73e0; alias, 1 drivers +v000000000274a170_0 .net "s0", 0 0, L_00000000027943a0; 1 drivers +v000000000274adf0_0 .net "s1", 0 0, L_0000000002794bc0; 1 drivers +S_0000000000f6bc30 .scope generate, "aluBits[10]" "aluBits[10]" 4 49, 4 49 0, S_0000000000cc7490; + .timescale -9 -12; +P_0000000000f057e0 .param/l "i" 0 4 49, +C4<01010>; +L_00000000027f7840/d .functor XOR 1, L_0000000002793d60, v0000000000e68bd0_0, C4<0>, C4<0>; +L_00000000027f7840 .delay 1 (20000,20000,20000) L_00000000027f7840/d; +L_00000000027f6dc0/d .functor AND 1, v0000000000e67370_0, L_0000000002794f80, C4<1>, C4<1>; +L_00000000027f6dc0 .delay 1 (30000,30000,30000) L_00000000027f6dc0/d; +L_00000000027f7290/d .functor AND 1, L_0000000002797140, L_000000000282c280, C4<1>, C4<1>; +L_00000000027f7290 .delay 1 (30000,30000,30000) L_00000000027f7290/d; +v0000000002754e60_0 .net *"_s1", 0 0, L_0000000002793d60; 1 drivers +v00000000027554a0_0 .net *"_s3", 0 0, L_0000000002794f80; 1 drivers +v00000000027543c0_0 .net *"_s9", 0 0, L_0000000002797140; 1 drivers +S_0000000002753880 .scope module, "_bit" "aluFullBit" 4 52, 5 6 0, S_0000000000f6bc30; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "res" + .port_info 1 /OUTPUT 1 "carryAND" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "cin" + .port_info 5 /INPUT 1 "ctrl0" + .port_info 6 /INPUT 2 "sel" +v0000000002754c80_0 .net "a", 0 0, L_0000000002793e00; 1 drivers +v0000000002754d20_0 .net "b", 0 0, L_0000000002793f40; 1 drivers +v0000000002754f00_0 .net "carryAND", 0 0, L_00000000027f6f80; 1 drivers +v0000000002754dc0_0 .net "cin", 0 0, L_0000000002797280; 1 drivers +v00000000027550e0_0 .net "ctrl0", 0 0, L_00000000027969c0; 1 drivers +v0000000002756080_0 .net "nab", 0 0, L_00000000027f66c0; 1 drivers +v0000000002755860_0 .net "orNOR", 0 0, L_00000000027f6c70; 1 drivers +v00000000027566c0_0 .net "res", 0 0, L_00000000027f7680; 1 drivers +v00000000027559a0_0 .net "sel", 1 0, v0000000000e625f0_0; alias, 1 drivers +v00000000027552c0_0 .net "sumXOR", 0 0, L_00000000027f7b50; 1 drivers +L_0000000002795020 .part v0000000000e625f0_0, 1, 1; +L_0000000002792a00 .part v0000000000e625f0_0, 0, 1; +S_0000000002752800 .scope module, "alu" "aluBit" 5 18, 6 14 0, S_0000000002753880; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sumXOR" + .port_info 1 /OUTPUT 1 "carryAND" + .port_info 2 /OUTPUT 1 "nab" + .port_info 3 /OUTPUT 1 "orNOR" + .port_info 4 /INPUT 1 "a" + .port_info 5 /INPUT 1 "b" + .port_info 6 /INPUT 1 "carryin" + .port_info 7 /INPUT 1 "i0" +L_00000000027f66c0/d .functor NAND 1, L_0000000002793e00, L_0000000002793f40, C4<1>, C4<1>; +L_00000000027f66c0 .delay 1 (20000,20000,20000) L_00000000027f66c0/d; +L_00000000027f7140/d .functor NAND 1, L_0000000002793f40, L_0000000002797280, C4<1>, C4<1>; +L_00000000027f7140 .delay 1 (20000,20000,20000) L_00000000027f7140/d; +L_00000000027f6730/d .functor NAND 1, L_0000000002793e00, L_0000000002797280, C4<1>, C4<1>; +L_00000000027f6730 .delay 1 (20000,20000,20000) L_00000000027f6730/d; +L_00000000027f6f80/d .functor NAND 1, L_00000000027f66c0, L_00000000027f6730, L_00000000027f7140, C4<1>; +L_00000000027f6f80 .delay 1 (30000,30000,30000) L_00000000027f6f80/d; +L_00000000027f7b50/d .functor XOR 1, L_0000000002793e00, L_0000000002793f40, L_0000000002797280, C4<0>; +L_00000000027f7b50 .delay 1 (30000,30000,30000) L_00000000027f7b50/d; +L_00000000027f6c00/d .functor NOR 1, L_0000000002793e00, L_0000000002793f40, C4<0>, C4<0>; +L_00000000027f6c00 .delay 1 (20000,20000,20000) L_00000000027f6c00/d; +L_00000000027f6c70/d .functor XOR 1, L_00000000027f6c00, L_00000000027969c0, C4<0>, C4<0>; +L_00000000027f6c70 .delay 1 (20000,20000,20000) L_00000000027f6c70/d; +v000000000274a850_0 .net "a", 0 0, L_0000000002793e00; alias, 1 drivers +v000000000274a8f0_0 .net "anorb", 0 0, L_00000000027f6c00; 1 drivers +v00000000027548c0_0 .net "b", 0 0, L_0000000002793f40; alias, 1 drivers +v0000000002755900_0 .net "carryAND", 0 0, L_00000000027f6f80; alias, 1 drivers +v0000000002755400_0 .net "carryin", 0 0, L_0000000002797280; alias, 1 drivers +v0000000002754960_0 .net "i0", 0 0, L_00000000027969c0; alias, 1 drivers +v0000000002754320_0 .net "nab", 0 0, L_00000000027f66c0; alias, 1 drivers +v0000000002756300_0 .net "nac", 0 0, L_00000000027f6730; 1 drivers +v00000000027561c0_0 .net "nbc", 0 0, L_00000000027f7140; 1 drivers +v0000000002754820_0 .net "orNOR", 0 0, L_00000000027f6c70; alias, 1 drivers +v0000000002754460_0 .net "sumXOR", 0 0, L_00000000027f7b50; alias, 1 drivers +S_0000000002752680 .scope module, "mux" "multiplexer" 5 20, 7 7 0, S_0000000002753880; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "a" + .port_info 2 /INPUT 1 "b" + .port_info 3 /INPUT 1 "c" + .port_info 4 /INPUT 1 "d" + .port_info 5 /INPUT 1 "s1" + .port_info 6 /INPUT 1 "s0" +L_00000000027f6570/d .functor NOT 1, L_0000000002792a00, C4<0>, C4<0>, C4<0>; +L_00000000027f6570 .delay 1 (10000,10000,10000) L_00000000027f6570/d; +L_00000000027f75a0/d .functor NOT 1, L_0000000002795020, C4<0>, C4<0>, C4<0>; +L_00000000027f75a0 .delay 1 (10000,10000,10000) L_00000000027f75a0/d; +L_00000000027f6ff0/d .functor NAND 1, L_0000000002795020, L_0000000002792a00, L_00000000027f7b50, C4<1>; +L_00000000027f6ff0 .delay 1 (30000,30000,30000) L_00000000027f6ff0/d; +L_00000000027f7060/d .functor NAND 1, L_0000000002795020, L_00000000027f6570, L_00000000027f6c70, C4<1>; +L_00000000027f7060 .delay 1 (30000,30000,30000) L_00000000027f7060/d; +L_00000000027f71b0/d .functor NAND 1, L_00000000027f75a0, L_0000000002792a00, L_00000000027f6f80, C4<1>; +L_00000000027f71b0 .delay 1 (30000,30000,30000) L_00000000027f71b0/d; +L_00000000027f7220/d .functor NAND 1, L_00000000027f75a0, L_00000000027f6570, L_00000000027f66c0, C4<1>; +L_00000000027f7220 .delay 1 (30000,30000,30000) L_00000000027f7220/d; +L_00000000027f7680/d .functor NAND 1, L_00000000027f6ff0, L_00000000027f7060, L_00000000027f71b0, L_00000000027f7220; +L_00000000027f7680 .delay 1 (40000,40000,40000) L_00000000027f7680/d; +v0000000002754780_0 .net "a", 0 0, L_00000000027f7b50; alias, 1 drivers +v0000000002755c20_0 .net "aout", 0 0, L_00000000027f6ff0; 1 drivers +v0000000002754640_0 .net "b", 0 0, L_00000000027f6c70; alias, 1 drivers +v00000000027540a0_0 .net "bout", 0 0, L_00000000027f7060; 1 drivers +v00000000027546e0_0 .net "c", 0 0, L_00000000027f6f80; alias, 1 drivers +v0000000002755040_0 .net "cout", 0 0, L_00000000027f71b0; 1 drivers +v0000000002756260_0 .net "d", 0 0, L_00000000027f66c0; alias, 1 drivers +v0000000002754a00_0 .net "dout", 0 0, L_00000000027f7220; 1 drivers +v0000000002754b40_0 .net "ns0", 0 0, L_00000000027f6570; 1 drivers +v0000000002754aa0_0 .net "ns1", 0 0, L_00000000027f75a0; 1 drivers +v0000000002754be0_0 .net "out", 0 0, L_00000000027f7680; alias, 1 drivers +v00000000027563a0_0 .net "s0", 0 0, L_0000000002792a00; 1 drivers +v0000000002756440_0 .net "s1", 0 0, L_0000000002795020; 1 drivers +S_0000000002753e80 .scope generate, "aluBits[11]" "aluBits[11]" 4 49, 4 49 0, S_0000000000cc7490; + .timescale -9 -12; +P_0000000000f065a0 .param/l "i" 0 4 49, +C4<01011>; +L_00000000027f7450/d .functor XOR 1, L_0000000002795840, v0000000000e68bd0_0, C4<0>, C4<0>; +L_00000000027f7450 .delay 1 (20000,20000,20000) L_00000000027f7450/d; +L_00000000027f76f0/d .functor AND 1, v0000000000e67370_0, L_0000000002796880, C4<1>, C4<1>; +L_00000000027f76f0 .delay 1 (30000,30000,30000) L_00000000027f76f0/d; +L_00000000027f8090/d .functor AND 1, L_0000000002795b60, L_000000000282c280, C4<1>, C4<1>; +L_00000000027f8090 .delay 1 (30000,30000,30000) L_00000000027f8090/d; +v0000000002756b20_0 .net *"_s1", 0 0, L_0000000002795840; 1 drivers +v0000000002756d00_0 .net *"_s3", 0 0, L_0000000002796880; 1 drivers +v00000000027587e0_0 .net *"_s9", 0 0, L_0000000002795b60; 1 drivers +S_0000000002753a00 .scope module, "_bit" "aluFullBit" 4 52, 5 6 0, S_0000000002753e80; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "res" + .port_info 1 /OUTPUT 1 "carryAND" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "cin" + .port_info 5 /INPUT 1 "ctrl0" + .port_info 6 /INPUT 2 "sel" +v00000000027564e0_0 .net "a", 0 0, L_00000000027958e0; 1 drivers +v0000000002755f40_0 .net "b", 0 0, L_0000000002796240; 1 drivers +v0000000002755fe0_0 .net "carryAND", 0 0, L_00000000027f77d0; 1 drivers +v0000000002756580_0 .net "cin", 0 0, L_0000000002795a20; 1 drivers +v0000000002756760_0 .net "ctrl0", 0 0, L_0000000002795ac0; 1 drivers +v0000000002758ce0_0 .net "nab", 0 0, L_00000000027f7920; 1 drivers +v0000000002758ec0_0 .net "orNOR", 0 0, L_00000000027f7bc0; 1 drivers +v0000000002757d40_0 .net "res", 0 0, L_00000000027f7fb0; 1 drivers +v00000000027584c0_0 .net "sel", 1 0, v0000000000e625f0_0; alias, 1 drivers +v0000000002758740_0 .net "sumXOR", 0 0, L_00000000027f6810; 1 drivers +L_0000000002795980 .part v0000000000e625f0_0, 1, 1; +L_00000000027961a0 .part v0000000000e625f0_0, 0, 1; +S_0000000002753280 .scope module, "alu" "aluBit" 5 18, 6 14 0, S_0000000002753a00; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sumXOR" + .port_info 1 /OUTPUT 1 "carryAND" + .port_info 2 /OUTPUT 1 "nab" + .port_info 3 /OUTPUT 1 "orNOR" + .port_info 4 /INPUT 1 "a" + .port_info 5 /INPUT 1 "b" + .port_info 6 /INPUT 1 "carryin" + .port_info 7 /INPUT 1 "i0" +L_00000000027f7920/d .functor NAND 1, L_00000000027958e0, L_0000000002796240, C4<1>, C4<1>; +L_00000000027f7920 .delay 1 (20000,20000,20000) L_00000000027f7920/d; +L_00000000027f67a0/d .functor NAND 1, L_0000000002796240, L_0000000002795a20, C4<1>, C4<1>; +L_00000000027f67a0 .delay 1 (20000,20000,20000) L_00000000027f67a0/d; +L_00000000027f7760/d .functor NAND 1, L_00000000027958e0, L_0000000002795a20, C4<1>, C4<1>; +L_00000000027f7760 .delay 1 (20000,20000,20000) L_00000000027f7760/d; +L_00000000027f77d0/d .functor NAND 1, L_00000000027f7920, L_00000000027f7760, L_00000000027f67a0, C4<1>; +L_00000000027f77d0 .delay 1 (30000,30000,30000) L_00000000027f77d0/d; +L_00000000027f6810/d .functor XOR 1, L_00000000027958e0, L_0000000002796240, L_0000000002795a20, C4<0>; +L_00000000027f6810 .delay 1 (30000,30000,30000) L_00000000027f6810/d; +L_00000000027f7a70/d .functor NOR 1, L_00000000027958e0, L_0000000002796240, C4<0>, C4<0>; +L_00000000027f7a70 .delay 1 (20000,20000,20000) L_00000000027f7a70/d; +L_00000000027f7bc0/d .functor XOR 1, L_00000000027f7a70, L_0000000002795ac0, C4<0>, C4<0>; +L_00000000027f7bc0 .delay 1 (20000,20000,20000) L_00000000027f7bc0/d; +v0000000002756120_0 .net "a", 0 0, L_00000000027958e0; alias, 1 drivers +v0000000002755360_0 .net "anorb", 0 0, L_00000000027f7a70; 1 drivers +v0000000002755680_0 .net "b", 0 0, L_0000000002796240; alias, 1 drivers +v0000000002756800_0 .net "carryAND", 0 0, L_00000000027f77d0; alias, 1 drivers +v0000000002754fa0_0 .net "carryin", 0 0, L_0000000002795a20; alias, 1 drivers +v0000000002755180_0 .net "i0", 0 0, L_0000000002795ac0; alias, 1 drivers +v0000000002755ea0_0 .net "nab", 0 0, L_00000000027f7920; alias, 1 drivers +v0000000002755220_0 .net "nac", 0 0, L_00000000027f7760; 1 drivers +v0000000002755720_0 .net "nbc", 0 0, L_00000000027f67a0; 1 drivers +v0000000002755540_0 .net "orNOR", 0 0, L_00000000027f7bc0; alias, 1 drivers +v00000000027555e0_0 .net "sumXOR", 0 0, L_00000000027f6810; alias, 1 drivers +S_0000000002753d00 .scope module, "mux" "multiplexer" 5 20, 7 7 0, S_0000000002753a00; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "a" + .port_info 2 /INPUT 1 "b" + .port_info 3 /INPUT 1 "c" + .port_info 4 /INPUT 1 "d" + .port_info 5 /INPUT 1 "s1" + .port_info 6 /INPUT 1 "s0" +L_00000000027f7c30/d .functor NOT 1, L_00000000027961a0, C4<0>, C4<0>, C4<0>; +L_00000000027f7c30 .delay 1 (10000,10000,10000) L_00000000027f7c30/d; +L_00000000027f61f0/d .functor NOT 1, L_0000000002795980, C4<0>, C4<0>, C4<0>; +L_00000000027f61f0 .delay 1 (10000,10000,10000) L_00000000027f61f0/d; +L_00000000027f7ca0/d .functor NAND 1, L_0000000002795980, L_00000000027961a0, L_00000000027f6810, C4<1>; +L_00000000027f7ca0 .delay 1 (30000,30000,30000) L_00000000027f7ca0/d; +L_00000000027f6260/d .functor NAND 1, L_0000000002795980, L_00000000027f7c30, L_00000000027f7bc0, C4<1>; +L_00000000027f6260 .delay 1 (30000,30000,30000) L_00000000027f6260/d; +L_00000000027f63b0/d .functor NAND 1, L_00000000027f61f0, L_00000000027961a0, L_00000000027f77d0, C4<1>; +L_00000000027f63b0 .delay 1 (30000,30000,30000) L_00000000027f63b0/d; +L_00000000027f7f40/d .functor NAND 1, L_00000000027f61f0, L_00000000027f7c30, L_00000000027f7920, C4<1>; +L_00000000027f7f40 .delay 1 (30000,30000,30000) L_00000000027f7f40/d; +L_00000000027f7fb0/d .functor NAND 1, L_00000000027f7ca0, L_00000000027f6260, L_00000000027f63b0, L_00000000027f7f40; +L_00000000027f7fb0 .delay 1 (40000,40000,40000) L_00000000027f7fb0/d; +v00000000027557c0_0 .net "a", 0 0, L_00000000027f6810; alias, 1 drivers +v0000000002755a40_0 .net "aout", 0 0, L_00000000027f7ca0; 1 drivers +v0000000002755ae0_0 .net "b", 0 0, L_00000000027f7bc0; alias, 1 drivers +v0000000002754500_0 .net "bout", 0 0, L_00000000027f6260; 1 drivers +v0000000002754140_0 .net "c", 0 0, L_00000000027f77d0; alias, 1 drivers +v0000000002756620_0 .net "cout", 0 0, L_00000000027f63b0; 1 drivers +v0000000002754280_0 .net "d", 0 0, L_00000000027f7920; alias, 1 drivers +v0000000002755b80_0 .net "dout", 0 0, L_00000000027f7f40; 1 drivers +v00000000027541e0_0 .net "ns0", 0 0, L_00000000027f7c30; 1 drivers +v00000000027545a0_0 .net "ns1", 0 0, L_00000000027f61f0; 1 drivers +v0000000002755cc0_0 .net "out", 0 0, L_00000000027f7fb0; alias, 1 drivers +v0000000002755d60_0 .net "s0", 0 0, L_00000000027961a0; 1 drivers +v0000000002755e00_0 .net "s1", 0 0, L_0000000002795980; 1 drivers +S_0000000002752080 .scope generate, "aluBits[12]" "aluBits[12]" 4 49, 4 49 0, S_0000000000cc7490; + .timescale -9 -12; +P_0000000000f05fa0 .param/l "i" 0 4 49, +C4<01100>; +L_00000000027f7df0/d .functor XOR 1, L_0000000002796100, v0000000000e68bd0_0, C4<0>, C4<0>; +L_00000000027f7df0 .delay 1 (20000,20000,20000) L_00000000027f7df0/d; +L_00000000027f8020/d .functor AND 1, v0000000000e67370_0, L_0000000002796560, C4<1>, C4<1>; +L_00000000027f8020 .delay 1 (30000,30000,30000) L_00000000027f8020/d; +L_0000000002800670/d .functor AND 1, L_0000000002795c00, L_000000000282c280, C4<1>, C4<1>; +L_0000000002800670 .delay 1 (30000,30000,30000) L_0000000002800670/d; +v0000000002758c40_0 .net *"_s1", 0 0, L_0000000002796100; 1 drivers +v0000000002756c60_0 .net *"_s3", 0 0, L_0000000002796560; 1 drivers +v0000000002759000_0 .net *"_s9", 0 0, L_0000000002795c00; 1 drivers +S_0000000002753b80 .scope module, "_bit" "aluFullBit" 4 52, 5 6 0, S_0000000002752080; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "res" + .port_info 1 /OUTPUT 1 "carryAND" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "cin" + .port_info 5 /INPUT 1 "ctrl0" + .port_info 6 /INPUT 2 "sel" +v0000000002757700_0 .net "a", 0 0, L_00000000027962e0; 1 drivers +v00000000027572a0_0 .net "b", 0 0, L_0000000002795de0; 1 drivers +v0000000002758920_0 .net "carryAND", 0 0, L_00000000028018d0; 1 drivers +v0000000002757b60_0 .net "cin", 0 0, L_0000000002795200; 1 drivers +v0000000002756bc0_0 .net "ctrl0", 0 0, L_0000000002796d80; 1 drivers +v0000000002758a60_0 .net "nab", 0 0, L_00000000027f7e60; 1 drivers +v0000000002757200_0 .net "orNOR", 0 0, L_0000000002800fa0; 1 drivers +v0000000002758ba0_0 .net "res", 0 0, L_0000000002801be0; 1 drivers +v0000000002757520_0 .net "sel", 1 0, v0000000000e625f0_0; alias, 1 drivers +v00000000027589c0_0 .net "sumXOR", 0 0, L_00000000028003d0; 1 drivers +L_0000000002796420 .part v0000000000e625f0_0, 1, 1; +L_0000000002796ce0 .part v0000000000e625f0_0, 0, 1; +S_0000000002752380 .scope module, "alu" "aluBit" 5 18, 6 14 0, S_0000000002753b80; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sumXOR" + .port_info 1 /OUTPUT 1 "carryAND" + .port_info 2 /OUTPUT 1 "nab" + .port_info 3 /OUTPUT 1 "orNOR" + .port_info 4 /INPUT 1 "a" + .port_info 5 /INPUT 1 "b" + .port_info 6 /INPUT 1 "carryin" + .port_info 7 /INPUT 1 "i0" +L_00000000027f7e60/d .functor NAND 1, L_00000000027962e0, L_0000000002795de0, C4<1>, C4<1>; +L_00000000027f7e60 .delay 1 (20000,20000,20000) L_00000000027f7e60/d; +L_00000000027f7ed0/d .functor NAND 1, L_0000000002795de0, L_0000000002795200, C4<1>, C4<1>; +L_00000000027f7ed0 .delay 1 (20000,20000,20000) L_00000000027f7ed0/d; +L_00000000027f7d80/d .functor NAND 1, L_00000000027962e0, L_0000000002795200, C4<1>, C4<1>; +L_00000000027f7d80 .delay 1 (20000,20000,20000) L_00000000027f7d80/d; +L_00000000028018d0/d .functor NAND 1, L_00000000027f7e60, L_00000000027f7d80, L_00000000027f7ed0, C4<1>; +L_00000000028018d0 .delay 1 (30000,30000,30000) L_00000000028018d0/d; +L_00000000028003d0/d .functor XOR 1, L_00000000027962e0, L_0000000002795de0, L_0000000002795200, C4<0>; +L_00000000028003d0 .delay 1 (30000,30000,30000) L_00000000028003d0/d; +L_0000000002800b40/d .functor NOR 1, L_00000000027962e0, L_0000000002795de0, C4<0>, C4<0>; +L_0000000002800b40 .delay 1 (20000,20000,20000) L_0000000002800b40/d; +L_0000000002800fa0/d .functor XOR 1, L_0000000002800b40, L_0000000002796d80, C4<0>, C4<0>; +L_0000000002800fa0 .delay 1 (20000,20000,20000) L_0000000002800fa0/d; +v00000000027578e0_0 .net "a", 0 0, L_00000000027962e0; alias, 1 drivers +v0000000002757020_0 .net "anorb", 0 0, L_0000000002800b40; 1 drivers +v00000000027570c0_0 .net "b", 0 0, L_0000000002795de0; alias, 1 drivers +v0000000002758d80_0 .net "carryAND", 0 0, L_00000000028018d0; alias, 1 drivers +v0000000002756f80_0 .net "carryin", 0 0, L_0000000002795200; alias, 1 drivers +v0000000002758420_0 .net "i0", 0 0, L_0000000002796d80; alias, 1 drivers +v0000000002758560_0 .net "nab", 0 0, L_00000000027f7e60; alias, 1 drivers +v00000000027575c0_0 .net "nac", 0 0, L_00000000027f7d80; 1 drivers +v00000000027568a0_0 .net "nbc", 0 0, L_00000000027f7ed0; 1 drivers +v0000000002758e20_0 .net "orNOR", 0 0, L_0000000002800fa0; alias, 1 drivers +v0000000002757840_0 .net "sumXOR", 0 0, L_00000000028003d0; alias, 1 drivers +S_0000000002752500 .scope module, "mux" "multiplexer" 5 20, 7 7 0, S_0000000002753b80; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "a" + .port_info 2 /INPUT 1 "b" + .port_info 3 /INPUT 1 "c" + .port_info 4 /INPUT 1 "d" + .port_info 5 /INPUT 1 "s1" + .port_info 6 /INPUT 1 "s0" +L_0000000002801c50/d .functor NOT 1, L_0000000002796ce0, C4<0>, C4<0>, C4<0>; +L_0000000002801c50 .delay 1 (10000,10000,10000) L_0000000002801c50/d; +L_0000000002801940/d .functor NOT 1, L_0000000002796420, C4<0>, C4<0>, C4<0>; +L_0000000002801940 .delay 1 (10000,10000,10000) L_0000000002801940/d; +L_0000000002801710/d .functor NAND 1, L_0000000002796420, L_0000000002796ce0, L_00000000028003d0, C4<1>; +L_0000000002801710 .delay 1 (30000,30000,30000) L_0000000002801710/d; +L_0000000002801d30/d .functor NAND 1, L_0000000002796420, L_0000000002801c50, L_0000000002800fa0, C4<1>; +L_0000000002801d30 .delay 1 (30000,30000,30000) L_0000000002801d30/d; +L_0000000002800f30/d .functor NAND 1, L_0000000002801940, L_0000000002796ce0, L_00000000028018d0, C4<1>; +L_0000000002800f30 .delay 1 (30000,30000,30000) L_0000000002800f30/d; +L_0000000002801390/d .functor NAND 1, L_0000000002801940, L_0000000002801c50, L_00000000027f7e60, C4<1>; +L_0000000002801390 .delay 1 (30000,30000,30000) L_0000000002801390/d; +L_0000000002801be0/d .functor NAND 1, L_0000000002801710, L_0000000002801d30, L_0000000002800f30, L_0000000002801390; +L_0000000002801be0 .delay 1 (40000,40000,40000) L_0000000002801be0/d; +v0000000002758600_0 .net "a", 0 0, L_00000000028003d0; alias, 1 drivers +v0000000002757340_0 .net "aout", 0 0, L_0000000002801710; 1 drivers +v00000000027581a0_0 .net "b", 0 0, L_0000000002800fa0; alias, 1 drivers +v0000000002757160_0 .net "bout", 0 0, L_0000000002801d30; 1 drivers +v0000000002758b00_0 .net "c", 0 0, L_00000000028018d0; alias, 1 drivers +v0000000002757c00_0 .net "cout", 0 0, L_0000000002800f30; 1 drivers +v0000000002757660_0 .net "d", 0 0, L_00000000027f7e60; alias, 1 drivers +v00000000027573e0_0 .net "dout", 0 0, L_0000000002801390; 1 drivers +v0000000002757980_0 .net "ns0", 0 0, L_0000000002801c50; 1 drivers +v0000000002758880_0 .net "ns1", 0 0, L_0000000002801940; 1 drivers +v0000000002758060_0 .net "out", 0 0, L_0000000002801be0; alias, 1 drivers +v0000000002758f60_0 .net "s0", 0 0, L_0000000002796ce0; 1 drivers +v0000000002758240_0 .net "s1", 0 0, L_0000000002796420; 1 drivers +S_0000000002753700 .scope generate, "aluBits[13]" "aluBits[13]" 4 49, 4 49 0, S_0000000000cc7490; + .timescale -9 -12; +P_0000000000f06aa0 .param/l "i" 0 4 49, +C4<01101>; +L_0000000002800520/d .functor XOR 1, L_0000000002795f20, v0000000000e68bd0_0, C4<0>, C4<0>; +L_0000000002800520 .delay 1 (20000,20000,20000) L_0000000002800520/d; +L_0000000002800590/d .functor AND 1, v0000000000e67370_0, L_0000000002795660, C4<1>, C4<1>; +L_0000000002800590 .delay 1 (30000,30000,30000) L_0000000002800590/d; +L_0000000002800440/d .functor AND 1, L_0000000002797640, L_000000000282c280, C4<1>, C4<1>; +L_0000000002800440 .delay 1 (30000,30000,30000) L_0000000002800440/d; +v000000000275a0e0_0 .net *"_s1", 0 0, L_0000000002795f20; 1 drivers +v000000000275a180_0 .net *"_s3", 0 0, L_0000000002795660; 1 drivers +v000000000275a360_0 .net *"_s9", 0 0, L_0000000002797640; 1 drivers +S_0000000002753400 .scope module, "_bit" "aluFullBit" 4 52, 5 6 0, S_0000000002753700; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "res" + .port_info 1 /OUTPUT 1 "carryAND" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "cin" + .port_info 5 /INPUT 1 "ctrl0" + .port_info 6 /INPUT 2 "sel" +v0000000002759a00_0 .net "a", 0 0, L_0000000002795480; 1 drivers +v0000000002759320_0 .net "b", 0 0, L_0000000002796380; 1 drivers +v000000000275af40_0 .net "carryAND", 0 0, L_0000000002801a90; 1 drivers +v00000000027598c0_0 .net "cin", 0 0, L_0000000002796e20; 1 drivers +v000000000275afe0_0 .net "ctrl0", 0 0, L_0000000002797460; 1 drivers +v000000000275a400_0 .net "nab", 0 0, L_0000000002800c20; 1 drivers +v00000000027595a0_0 .net "orNOR", 0 0, L_00000000028019b0; 1 drivers +v0000000002759820_0 .net "res", 0 0, L_00000000028010f0; 1 drivers +v000000000275b760_0 .net "sel", 1 0, v0000000000e625f0_0; alias, 1 drivers +v000000000275b1c0_0 .net "sumXOR", 0 0, L_0000000002801780; 1 drivers +L_0000000002796a60 .part v0000000000e625f0_0, 1, 1; +L_00000000027975a0 .part v0000000000e625f0_0, 0, 1; +S_0000000002752e00 .scope module, "alu" "aluBit" 5 18, 6 14 0, S_0000000002753400; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sumXOR" + .port_info 1 /OUTPUT 1 "carryAND" + .port_info 2 /OUTPUT 1 "nab" + .port_info 3 /OUTPUT 1 "orNOR" + .port_info 4 /INPUT 1 "a" + .port_info 5 /INPUT 1 "b" + .port_info 6 /INPUT 1 "carryin" + .port_info 7 /INPUT 1 "i0" +L_0000000002800c20/d .functor NAND 1, L_0000000002795480, L_0000000002796380, C4<1>, C4<1>; +L_0000000002800c20 .delay 1 (20000,20000,20000) L_0000000002800c20/d; +L_00000000028012b0/d .functor NAND 1, L_0000000002796380, L_0000000002796e20, C4<1>, C4<1>; +L_00000000028012b0 .delay 1 (20000,20000,20000) L_00000000028012b0/d; +L_0000000002801860/d .functor NAND 1, L_0000000002795480, L_0000000002796e20, C4<1>, C4<1>; +L_0000000002801860 .delay 1 (20000,20000,20000) L_0000000002801860/d; +L_0000000002801a90/d .functor NAND 1, L_0000000002800c20, L_0000000002801860, L_00000000028012b0, C4<1>; +L_0000000002801a90 .delay 1 (30000,30000,30000) L_0000000002801a90/d; +L_0000000002801780/d .functor XOR 1, L_0000000002795480, L_0000000002796380, L_0000000002796e20, C4<0>; +L_0000000002801780 .delay 1 (30000,30000,30000) L_0000000002801780/d; +L_00000000028001a0/d .functor NOR 1, L_0000000002795480, L_0000000002796380, C4<0>, C4<0>; +L_00000000028001a0 .delay 1 (20000,20000,20000) L_00000000028001a0/d; +L_00000000028019b0/d .functor XOR 1, L_00000000028001a0, L_0000000002797460, C4<0>, C4<0>; +L_00000000028019b0 .delay 1 (20000,20000,20000) L_00000000028019b0/d; +v0000000002757480_0 .net "a", 0 0, L_0000000002795480; alias, 1 drivers +v0000000002756940_0 .net "anorb", 0 0, L_00000000028001a0; 1 drivers +v00000000027569e0_0 .net "b", 0 0, L_0000000002796380; alias, 1 drivers +v00000000027577a0_0 .net "carryAND", 0 0, L_0000000002801a90; alias, 1 drivers +v0000000002757f20_0 .net "carryin", 0 0, L_0000000002796e20; alias, 1 drivers +v0000000002757a20_0 .net "i0", 0 0, L_0000000002797460; alias, 1 drivers +v0000000002756a80_0 .net "nab", 0 0, L_0000000002800c20; alias, 1 drivers +v0000000002757ac0_0 .net "nac", 0 0, L_0000000002801860; 1 drivers +v0000000002756da0_0 .net "nbc", 0 0, L_00000000028012b0; 1 drivers +v0000000002756e40_0 .net "orNOR", 0 0, L_00000000028019b0; alias, 1 drivers +v0000000002756ee0_0 .net "sumXOR", 0 0, L_0000000002801780; alias, 1 drivers +S_0000000002752f80 .scope module, "mux" "multiplexer" 5 20, 7 7 0, S_0000000002753400; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "a" + .port_info 2 /INPUT 1 "b" + .port_info 3 /INPUT 1 "c" + .port_info 4 /INPUT 1 "d" + .port_info 5 /INPUT 1 "s1" + .port_info 6 /INPUT 1 "s0" +L_0000000002800750/d .functor NOT 1, L_00000000027975a0, C4<0>, C4<0>, C4<0>; +L_0000000002800750 .delay 1 (10000,10000,10000) L_0000000002800750/d; +L_00000000028007c0/d .functor NOT 1, L_0000000002796a60, C4<0>, C4<0>, C4<0>; +L_00000000028007c0 .delay 1 (10000,10000,10000) L_00000000028007c0/d; +L_0000000002801b00/d .functor NAND 1, L_0000000002796a60, L_00000000027975a0, L_0000000002801780, C4<1>; +L_0000000002801b00 .delay 1 (30000,30000,30000) L_0000000002801b00/d; +L_0000000002801cc0/d .functor NAND 1, L_0000000002796a60, L_0000000002800750, L_00000000028019b0, C4<1>; +L_0000000002801cc0 .delay 1 (30000,30000,30000) L_0000000002801cc0/d; +L_0000000002800a60/d .functor NAND 1, L_00000000028007c0, L_00000000027975a0, L_0000000002801a90, C4<1>; +L_0000000002800a60 .delay 1 (30000,30000,30000) L_0000000002800a60/d; +L_0000000002801630/d .functor NAND 1, L_00000000028007c0, L_0000000002800750, L_0000000002800c20, C4<1>; +L_0000000002801630 .delay 1 (30000,30000,30000) L_0000000002801630/d; +L_00000000028010f0/d .functor NAND 1, L_0000000002801b00, L_0000000002801cc0, L_0000000002800a60, L_0000000002801630; +L_00000000028010f0 .delay 1 (40000,40000,40000) L_00000000028010f0/d; +v0000000002757ca0_0 .net "a", 0 0, L_0000000002801780; alias, 1 drivers +v0000000002757de0_0 .net "aout", 0 0, L_0000000002801b00; 1 drivers +v0000000002757e80_0 .net "b", 0 0, L_00000000028019b0; alias, 1 drivers +v0000000002757fc0_0 .net "bout", 0 0, L_0000000002801cc0; 1 drivers +v0000000002758100_0 .net "c", 0 0, L_0000000002801a90; alias, 1 drivers +v00000000027582e0_0 .net "cout", 0 0, L_0000000002800a60; 1 drivers +v0000000002758380_0 .net "d", 0 0, L_0000000002800c20; alias, 1 drivers +v00000000027586a0_0 .net "dout", 0 0, L_0000000002801630; 1 drivers +v0000000002759b40_0 .net "ns0", 0 0, L_0000000002800750; 1 drivers +v000000000275b4e0_0 .net "ns1", 0 0, L_00000000028007c0; 1 drivers +v000000000275b6c0_0 .net "out", 0 0, L_00000000028010f0; alias, 1 drivers +v000000000275a540_0 .net "s0", 0 0, L_00000000027975a0; 1 drivers +v000000000275acc0_0 .net "s1", 0 0, L_0000000002796a60; 1 drivers +S_0000000002752980 .scope generate, "aluBits[14]" "aluBits[14]" 4 49, 4 49 0, S_0000000000cc7490; + .timescale -9 -12; +P_0000000000f069a0 .param/l "i" 0 4 49, +C4<01110>; +L_00000000028006e0/d .functor XOR 1, L_00000000027964c0, v0000000000e68bd0_0, C4<0>, C4<0>; +L_00000000028006e0 .delay 1 (20000,20000,20000) L_00000000028006e0/d; +L_0000000002800360/d .functor AND 1, v0000000000e67370_0, L_0000000002796600, C4<1>, C4<1>; +L_0000000002800360 .delay 1 (30000,30000,30000) L_0000000002800360/d; +L_0000000002800830/d .functor AND 1, L_0000000002795160, L_000000000282c280, C4<1>, C4<1>; +L_0000000002800830 .delay 1 (30000,30000,30000) L_0000000002800830/d; +v000000000275a220_0 .net *"_s1", 0 0, L_00000000027964c0; 1 drivers +v000000000275aa40_0 .net *"_s3", 0 0, L_0000000002796600; 1 drivers +v000000000275b440_0 .net *"_s9", 0 0, L_0000000002795160; 1 drivers +S_0000000002752200 .scope module, "_bit" "aluFullBit" 4 52, 5 6 0, S_0000000002752980; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "res" + .port_info 1 /OUTPUT 1 "carryAND" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "cin" + .port_info 5 /INPUT 1 "ctrl0" + .port_info 6 /INPUT 2 "sel" +v0000000002759fa0_0 .net "a", 0 0, L_0000000002795d40; 1 drivers +v000000000275b120_0 .net "b", 0 0, L_00000000027953e0; 1 drivers +v000000000275a2c0_0 .net "carryAND", 0 0, L_0000000002800600; 1 drivers +v000000000275a7c0_0 .net "cin", 0 0, L_00000000027978c0; 1 drivers +v00000000027590a0_0 .net "ctrl0", 0 0, L_00000000027976e0; 1 drivers +v000000000275a040_0 .net "nab", 0 0, L_0000000002800910; 1 drivers +v0000000002759140_0 .net "orNOR", 0 0, L_0000000002801a20; 1 drivers +v000000000275b3a0_0 .net "res", 0 0, L_0000000002801b70; 1 drivers +v00000000027591e0_0 .net "sel", 1 0, v0000000000e625f0_0; alias, 1 drivers +v000000000275a9a0_0 .net "sumXOR", 0 0, L_00000000028011d0; 1 drivers +L_0000000002796060 .part v0000000000e625f0_0, 1, 1; +L_0000000002795ca0 .part v0000000000e625f0_0, 0, 1; +S_0000000002752b00 .scope module, "alu" "aluBit" 5 18, 6 14 0, S_0000000002752200; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sumXOR" + .port_info 1 /OUTPUT 1 "carryAND" + .port_info 2 /OUTPUT 1 "nab" + .port_info 3 /OUTPUT 1 "orNOR" + .port_info 4 /INPUT 1 "a" + .port_info 5 /INPUT 1 "b" + .port_info 6 /INPUT 1 "carryin" + .port_info 7 /INPUT 1 "i0" +L_0000000002800910/d .functor NAND 1, L_0000000002795d40, L_00000000027953e0, C4<1>, C4<1>; +L_0000000002800910 .delay 1 (20000,20000,20000) L_0000000002800910/d; +L_0000000002800210/d .functor NAND 1, L_00000000027953e0, L_00000000027978c0, C4<1>, C4<1>; +L_0000000002800210 .delay 1 (20000,20000,20000) L_0000000002800210/d; +L_00000000028004b0/d .functor NAND 1, L_0000000002795d40, L_00000000027978c0, C4<1>, C4<1>; +L_00000000028004b0 .delay 1 (20000,20000,20000) L_00000000028004b0/d; +L_0000000002800600/d .functor NAND 1, L_0000000002800910, L_00000000028004b0, L_0000000002800210, C4<1>; +L_0000000002800600 .delay 1 (30000,30000,30000) L_0000000002800600/d; +L_00000000028011d0/d .functor XOR 1, L_0000000002795d40, L_00000000027953e0, L_00000000027978c0, C4<0>; +L_00000000028011d0 .delay 1 (30000,30000,30000) L_00000000028011d0/d; +L_0000000002801400/d .functor NOR 1, L_0000000002795d40, L_00000000027953e0, C4<0>, C4<0>; +L_0000000002801400 .delay 1 (20000,20000,20000) L_0000000002801400/d; +L_0000000002801a20/d .functor XOR 1, L_0000000002801400, L_00000000027976e0, C4<0>, C4<0>; +L_0000000002801a20 .delay 1 (20000,20000,20000) L_0000000002801a20/d; +v000000000275a5e0_0 .net "a", 0 0, L_0000000002795d40; alias, 1 drivers +v0000000002759aa0_0 .net "anorb", 0 0, L_0000000002801400; 1 drivers +v0000000002759640_0 .net "b", 0 0, L_00000000027953e0; alias, 1 drivers +v0000000002759960_0 .net "carryAND", 0 0, L_0000000002800600; alias, 1 drivers +v000000000275ad60_0 .net "carryin", 0 0, L_00000000027978c0; alias, 1 drivers +v0000000002759be0_0 .net "i0", 0 0, L_00000000027976e0; alias, 1 drivers +v00000000027596e0_0 .net "nab", 0 0, L_0000000002800910; alias, 1 drivers +v0000000002759c80_0 .net "nac", 0 0, L_00000000028004b0; 1 drivers +v0000000002759d20_0 .net "nbc", 0 0, L_0000000002800210; 1 drivers +v0000000002759dc0_0 .net "orNOR", 0 0, L_0000000002801a20; alias, 1 drivers +v000000000275a4a0_0 .net "sumXOR", 0 0, L_00000000028011d0; alias, 1 drivers +S_0000000002752c80 .scope module, "mux" "multiplexer" 5 20, 7 7 0, S_0000000002752200; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "a" + .port_info 2 /INPUT 1 "b" + .port_info 3 /INPUT 1 "c" + .port_info 4 /INPUT 1 "d" + .port_info 5 /INPUT 1 "s1" + .port_info 6 /INPUT 1 "s0" +L_0000000002800ec0/d .functor NOT 1, L_0000000002795ca0, C4<0>, C4<0>, C4<0>; +L_0000000002800ec0 .delay 1 (10000,10000,10000) L_0000000002800ec0/d; +L_0000000002800280/d .functor NOT 1, L_0000000002796060, C4<0>, C4<0>, C4<0>; +L_0000000002800280 .delay 1 (10000,10000,10000) L_0000000002800280/d; +L_0000000002801470/d .functor NAND 1, L_0000000002796060, L_0000000002795ca0, L_00000000028011d0, C4<1>; +L_0000000002801470 .delay 1 (30000,30000,30000) L_0000000002801470/d; +L_00000000028016a0/d .functor NAND 1, L_0000000002796060, L_0000000002800ec0, L_0000000002801a20, C4<1>; +L_00000000028016a0 .delay 1 (30000,30000,30000) L_00000000028016a0/d; +L_00000000028002f0/d .functor NAND 1, L_0000000002800280, L_0000000002795ca0, L_0000000002800600, C4<1>; +L_00000000028002f0 .delay 1 (30000,30000,30000) L_00000000028002f0/d; +L_00000000028014e0/d .functor NAND 1, L_0000000002800280, L_0000000002800ec0, L_0000000002800910, C4<1>; +L_00000000028014e0 .delay 1 (30000,30000,30000) L_00000000028014e0/d; +L_0000000002801b70/d .functor NAND 1, L_0000000002801470, L_00000000028016a0, L_00000000028002f0, L_00000000028014e0; +L_0000000002801b70 .delay 1 (40000,40000,40000) L_0000000002801b70/d; +v000000000275b080_0 .net "a", 0 0, L_00000000028011d0; alias, 1 drivers +v000000000275a900_0 .net "aout", 0 0, L_0000000002801470; 1 drivers +v000000000275ae00_0 .net "b", 0 0, L_0000000002801a20; alias, 1 drivers +v0000000002759e60_0 .net "bout", 0 0, L_00000000028016a0; 1 drivers +v000000000275a860_0 .net "c", 0 0, L_0000000002800600; alias, 1 drivers +v000000000275b800_0 .net "cout", 0 0, L_00000000028002f0; 1 drivers +v000000000275a680_0 .net "d", 0 0, L_0000000002800910; alias, 1 drivers +v000000000275a720_0 .net "dout", 0 0, L_00000000028014e0; 1 drivers +v00000000027593c0_0 .net "ns0", 0 0, L_0000000002800ec0; 1 drivers +v000000000275b260_0 .net "ns1", 0 0, L_0000000002800280; 1 drivers +v0000000002759780_0 .net "out", 0 0, L_0000000002801b70; alias, 1 drivers +v000000000275b300_0 .net "s0", 0 0, L_0000000002795ca0; 1 drivers +v0000000002759f00_0 .net "s1", 0 0, L_0000000002796060; 1 drivers +S_0000000002753100 .scope generate, "aluBits[15]" "aluBits[15]" 4 49, 4 49 0, S_0000000000cc7490; + .timescale -9 -12; +P_0000000000f064e0 .param/l "i" 0 4 49, +C4<01111>; +L_0000000002801160/d .functor XOR 1, L_0000000002795e80, v0000000000e68bd0_0, C4<0>, C4<0>; +L_0000000002801160 .delay 1 (20000,20000,20000) L_0000000002801160/d; +L_00000000028008a0/d .functor AND 1, v0000000000e67370_0, L_0000000002795fc0, C4<1>, C4<1>; +L_00000000028008a0 .delay 1 (30000,30000,30000) L_00000000028008a0/d; +L_0000000002801550/d .functor AND 1, L_0000000002797780, L_000000000282c280, C4<1>, C4<1>; +L_0000000002801550 .delay 1 (30000,30000,30000) L_0000000002801550/d; +v0000000002760e80_0 .net *"_s1", 0 0, L_0000000002795e80; 1 drivers +v0000000002762aa0_0 .net *"_s3", 0 0, L_0000000002795fc0; 1 drivers +v0000000002761380_0 .net *"_s9", 0 0, L_0000000002797780; 1 drivers +S_0000000002753580 .scope module, "_bit" "aluFullBit" 4 52, 5 6 0, S_0000000002753100; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "res" + .port_info 1 /OUTPUT 1 "carryAND" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "cin" + .port_info 5 /INPUT 1 "ctrl0" + .port_info 6 /INPUT 2 "sel" +v0000000002762280_0 .net "a", 0 0, L_00000000027973c0; 1 drivers +v00000000027611a0_0 .net "b", 0 0, L_0000000002796920; 1 drivers +v0000000002761ba0_0 .net "carryAND", 0 0, L_0000000002800bb0; 1 drivers +v0000000002760fc0_0 .net "cin", 0 0, L_0000000002796ec0; 1 drivers +v0000000002762d20_0 .net "ctrl0", 0 0, L_0000000002797320; 1 drivers +v0000000002762460_0 .net "nab", 0 0, L_0000000002800980; 1 drivers +v00000000027616a0_0 .net "orNOR", 0 0, L_0000000002800d00; 1 drivers +v00000000027608e0_0 .net "res", 0 0, L_0000000002801320; 1 drivers +v0000000002760f20_0 .net "sel", 1 0, v0000000000e625f0_0; alias, 1 drivers +v00000000027620a0_0 .net "sumXOR", 0 0, L_0000000002800c90; 1 drivers +L_0000000002796c40 .part v0000000000e625f0_0, 1, 1; +L_00000000027966a0 .part v0000000000e625f0_0, 0, 1; +S_000000000275cca0 .scope module, "alu" "aluBit" 5 18, 6 14 0, S_0000000002753580; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sumXOR" + .port_info 1 /OUTPUT 1 "carryAND" + .port_info 2 /OUTPUT 1 "nab" + .port_info 3 /OUTPUT 1 "orNOR" + .port_info 4 /INPUT 1 "a" + .port_info 5 /INPUT 1 "b" + .port_info 6 /INPUT 1 "carryin" + .port_info 7 /INPUT 1 "i0" +L_0000000002800980/d .functor NAND 1, L_00000000027973c0, L_0000000002796920, C4<1>, C4<1>; +L_0000000002800980 .delay 1 (20000,20000,20000) L_0000000002800980/d; +L_00000000028009f0/d .functor NAND 1, L_0000000002796920, L_0000000002796ec0, C4<1>, C4<1>; +L_00000000028009f0 .delay 1 (20000,20000,20000) L_00000000028009f0/d; +L_0000000002800ad0/d .functor NAND 1, L_00000000027973c0, L_0000000002796ec0, C4<1>, C4<1>; +L_0000000002800ad0 .delay 1 (20000,20000,20000) L_0000000002800ad0/d; +L_0000000002800bb0/d .functor NAND 1, L_0000000002800980, L_0000000002800ad0, L_00000000028009f0, C4<1>; +L_0000000002800bb0 .delay 1 (30000,30000,30000) L_0000000002800bb0/d; +L_0000000002800c90/d .functor XOR 1, L_00000000027973c0, L_0000000002796920, L_0000000002796ec0, C4<0>; +L_0000000002800c90 .delay 1 (30000,30000,30000) L_0000000002800c90/d; +L_00000000028017f0/d .functor NOR 1, L_00000000027973c0, L_0000000002796920, C4<0>, C4<0>; +L_00000000028017f0 .delay 1 (20000,20000,20000) L_00000000028017f0/d; +L_0000000002800d00/d .functor XOR 1, L_00000000028017f0, L_0000000002797320, C4<0>, C4<0>; +L_0000000002800d00 .delay 1 (20000,20000,20000) L_0000000002800d00/d; +v000000000275aea0_0 .net "a", 0 0, L_00000000027973c0; alias, 1 drivers +v000000000275aae0_0 .net "anorb", 0 0, L_00000000028017f0; 1 drivers +v000000000275ab80_0 .net "b", 0 0, L_0000000002796920; alias, 1 drivers +v000000000275ac20_0 .net "carryAND", 0 0, L_0000000002800bb0; alias, 1 drivers +v000000000275b580_0 .net "carryin", 0 0, L_0000000002796ec0; alias, 1 drivers +v0000000002759280_0 .net "i0", 0 0, L_0000000002797320; alias, 1 drivers +v0000000002759460_0 .net "nab", 0 0, L_0000000002800980; alias, 1 drivers +v0000000002759500_0 .net "nac", 0 0, L_0000000002800ad0; 1 drivers +v000000000275b620_0 .net "nbc", 0 0, L_00000000028009f0; 1 drivers +v000000000275b8a0_0 .net "orNOR", 0 0, L_0000000002800d00; alias, 1 drivers +v000000000275bbc0_0 .net "sumXOR", 0 0, L_0000000002800c90; alias, 1 drivers +S_000000000275ce20 .scope module, "mux" "multiplexer" 5 20, 7 7 0, S_0000000002753580; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "a" + .port_info 2 /INPUT 1 "b" + .port_info 3 /INPUT 1 "c" + .port_info 4 /INPUT 1 "d" + .port_info 5 /INPUT 1 "s1" + .port_info 6 /INPUT 1 "s0" +L_0000000002800d70/d .functor NOT 1, L_00000000027966a0, C4<0>, C4<0>, C4<0>; +L_0000000002800d70 .delay 1 (10000,10000,10000) L_0000000002800d70/d; +L_0000000002800de0/d .functor NOT 1, L_0000000002796c40, C4<0>, C4<0>, C4<0>; +L_0000000002800de0 .delay 1 (10000,10000,10000) L_0000000002800de0/d; +L_0000000002800e50/d .functor NAND 1, L_0000000002796c40, L_00000000027966a0, L_0000000002800c90, C4<1>; +L_0000000002800e50 .delay 1 (30000,30000,30000) L_0000000002800e50/d; +L_0000000002801010/d .functor NAND 1, L_0000000002796c40, L_0000000002800d70, L_0000000002800d00, C4<1>; +L_0000000002801010 .delay 1 (30000,30000,30000) L_0000000002801010/d; +L_0000000002801080/d .functor NAND 1, L_0000000002800de0, L_00000000027966a0, L_0000000002800bb0, C4<1>; +L_0000000002801080 .delay 1 (30000,30000,30000) L_0000000002801080/d; +L_0000000002801240/d .functor NAND 1, L_0000000002800de0, L_0000000002800d70, L_0000000002800980, C4<1>; +L_0000000002801240 .delay 1 (30000,30000,30000) L_0000000002801240/d; +L_0000000002801320/d .functor NAND 1, L_0000000002800e50, L_0000000002801010, L_0000000002801080, L_0000000002801240; +L_0000000002801320 .delay 1 (40000,40000,40000) L_0000000002801320/d; +v000000000275bf80_0 .net "a", 0 0, L_0000000002800c90; alias, 1 drivers +v000000000275bc60_0 .net "aout", 0 0, L_0000000002800e50; 1 drivers +v000000000275ba80_0 .net "b", 0 0, L_0000000002800d00; alias, 1 drivers +v000000000275b940_0 .net "bout", 0 0, L_0000000002801010; 1 drivers +v000000000275b9e0_0 .net "c", 0 0, L_0000000002800bb0; alias, 1 drivers +v000000000275bb20_0 .net "cout", 0 0, L_0000000002801080; 1 drivers +v000000000275bda0_0 .net "d", 0 0, L_0000000002800980; alias, 1 drivers +v000000000275bd00_0 .net "dout", 0 0, L_0000000002801240; 1 drivers +v000000000275be40_0 .net "ns0", 0 0, L_0000000002800d70; 1 drivers +v000000000275bee0_0 .net "ns1", 0 0, L_0000000002800de0; 1 drivers +v0000000002761880_0 .net "out", 0 0, L_0000000002801320; alias, 1 drivers +v0000000002761600_0 .net "s0", 0 0, L_00000000027966a0; 1 drivers +v0000000002762000_0 .net "s1", 0 0, L_0000000002796c40; 1 drivers +S_000000000275c6a0 .scope generate, "aluBits[16]" "aluBits[16]" 4 49, 4 49 0, S_0000000000cc7490; + .timescale -9 -12; +P_0000000000f06c60 .param/l "i" 0 4 49, +C4<010000>; +L_00000000028015c0/d .functor XOR 1, L_00000000027952a0, v0000000000e68bd0_0, C4<0>, C4<0>; +L_00000000028015c0 .delay 1 (20000,20000,20000) L_00000000028015c0/d; +L_0000000002801e80/d .functor AND 1, v0000000000e67370_0, L_0000000002796740, C4<1>, C4<1>; +L_0000000002801e80 .delay 1 (30000,30000,30000) L_0000000002801e80/d; +L_0000000002809260/d .functor AND 1, L_0000000002795700, L_000000000282c280, C4<1>, C4<1>; +L_0000000002809260 .delay 1 (30000,30000,30000) L_0000000002809260/d; +v0000000002761ce0_0 .net *"_s1", 0 0, L_00000000027952a0; 1 drivers +v0000000002762a00_0 .net *"_s3", 0 0, L_0000000002796740; 1 drivers +v0000000002761420_0 .net *"_s9", 0 0, L_0000000002795700; 1 drivers +S_000000000275cb20 .scope module, "_bit" "aluFullBit" 4 52, 5 6 0, S_000000000275c6a0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "res" + .port_info 1 /OUTPUT 1 "carryAND" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "cin" + .port_info 5 /INPUT 1 "ctrl0" + .port_info 6 /INPUT 2 "sel" +v0000000002760ca0_0 .net "a", 0 0, L_0000000002796b00; 1 drivers +v0000000002762dc0_0 .net "b", 0 0, L_0000000002796f60; 1 drivers +v0000000002761560_0 .net "carryAND", 0 0, L_00000000028020b0; 1 drivers +v0000000002762320_0 .net "cin", 0 0, L_0000000002797500; 1 drivers +v0000000002761a60_0 .net "ctrl0", 0 0, L_00000000027970a0; 1 drivers +v0000000002761920_0 .net "nab", 0 0, L_0000000002801e10; 1 drivers +v0000000002762780_0 .net "orNOR", 0 0, L_0000000002802040; 1 drivers +v00000000027612e0_0 .net "res", 0 0, L_0000000002807dd0; 1 drivers +v0000000002762820_0 .net "sel", 1 0, v0000000000e625f0_0; alias, 1 drivers +v0000000002762500_0 .net "sumXOR", 0 0, L_0000000002801da0; 1 drivers +L_0000000002796ba0 .part v0000000000e625f0_0, 1, 1; +L_00000000027967e0 .part v0000000000e625f0_0, 0, 1; +S_000000000275cfa0 .scope module, "alu" "aluBit" 5 18, 6 14 0, S_000000000275cb20; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sumXOR" + .port_info 1 /OUTPUT 1 "carryAND" + .port_info 2 /OUTPUT 1 "nab" + .port_info 3 /OUTPUT 1 "orNOR" + .port_info 4 /INPUT 1 "a" + .port_info 5 /INPUT 1 "b" + .port_info 6 /INPUT 1 "carryin" + .port_info 7 /INPUT 1 "i0" +L_0000000002801e10/d .functor NAND 1, L_0000000002796b00, L_0000000002796f60, C4<1>, C4<1>; +L_0000000002801e10 .delay 1 (20000,20000,20000) L_0000000002801e10/d; +L_0000000002801ef0/d .functor NAND 1, L_0000000002796f60, L_0000000002797500, C4<1>, C4<1>; +L_0000000002801ef0 .delay 1 (20000,20000,20000) L_0000000002801ef0/d; +L_0000000002801fd0/d .functor NAND 1, L_0000000002796b00, L_0000000002797500, C4<1>, C4<1>; +L_0000000002801fd0 .delay 1 (20000,20000,20000) L_0000000002801fd0/d; +L_00000000028020b0/d .functor NAND 1, L_0000000002801e10, L_0000000002801fd0, L_0000000002801ef0, C4<1>; +L_00000000028020b0 .delay 1 (30000,30000,30000) L_00000000028020b0/d; +L_0000000002801da0/d .functor XOR 1, L_0000000002796b00, L_0000000002796f60, L_0000000002797500, C4<0>; +L_0000000002801da0 .delay 1 (30000,30000,30000) L_0000000002801da0/d; +L_0000000002801f60/d .functor NOR 1, L_0000000002796b00, L_0000000002796f60, C4<0>, C4<0>; +L_0000000002801f60 .delay 1 (20000,20000,20000) L_0000000002801f60/d; +L_0000000002802040/d .functor XOR 1, L_0000000002801f60, L_00000000027970a0, C4<0>, C4<0>; +L_0000000002802040 .delay 1 (20000,20000,20000) L_0000000002802040/d; +v0000000002762140_0 .net "a", 0 0, L_0000000002796b00; alias, 1 drivers +v0000000002761060_0 .net "anorb", 0 0, L_0000000002801f60; 1 drivers +v0000000002760de0_0 .net "b", 0 0, L_0000000002796f60; alias, 1 drivers +v0000000002762b40_0 .net "carryAND", 0 0, L_00000000028020b0; alias, 1 drivers +v0000000002762640_0 .net "carryin", 0 0, L_0000000002797500; alias, 1 drivers +v0000000002761740_0 .net "i0", 0 0, L_00000000027970a0; alias, 1 drivers +v00000000027621e0_0 .net "nab", 0 0, L_0000000002801e10; alias, 1 drivers +v00000000027626e0_0 .net "nac", 0 0, L_0000000002801fd0; 1 drivers +v0000000002762960_0 .net "nbc", 0 0, L_0000000002801ef0; 1 drivers +v0000000002761c40_0 .net "orNOR", 0 0, L_0000000002802040; alias, 1 drivers +v0000000002760b60_0 .net "sumXOR", 0 0, L_0000000002801da0; alias, 1 drivers +S_000000000275d5a0 .scope module, "mux" "multiplexer" 5 20, 7 7 0, S_000000000275cb20; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "a" + .port_info 2 /INPUT 1 "b" + .port_info 3 /INPUT 1 "c" + .port_info 4 /INPUT 1 "d" + .port_info 5 /INPUT 1 "s1" + .port_info 6 /INPUT 1 "s0" +L_0000000002808f50/d .functor NOT 1, L_00000000027967e0, C4<0>, C4<0>, C4<0>; +L_0000000002808f50 .delay 1 (10000,10000,10000) L_0000000002808f50/d; +L_0000000002808230/d .functor NOT 1, L_0000000002796ba0, C4<0>, C4<0>, C4<0>; +L_0000000002808230 .delay 1 (10000,10000,10000) L_0000000002808230/d; +L_0000000002808d20/d .functor NAND 1, L_0000000002796ba0, L_00000000027967e0, L_0000000002801da0, C4<1>; +L_0000000002808d20 .delay 1 (30000,30000,30000) L_0000000002808d20/d; +L_0000000002808070/d .functor NAND 1, L_0000000002796ba0, L_0000000002808f50, L_0000000002802040, C4<1>; +L_0000000002808070 .delay 1 (30000,30000,30000) L_0000000002808070/d; +L_0000000002808930/d .functor NAND 1, L_0000000002808230, L_00000000027967e0, L_00000000028020b0, C4<1>; +L_0000000002808930 .delay 1 (30000,30000,30000) L_0000000002808930/d; +L_0000000002809730/d .functor NAND 1, L_0000000002808230, L_0000000002808f50, L_0000000002801e10, C4<1>; +L_0000000002809730 .delay 1 (30000,30000,30000) L_0000000002809730/d; +L_0000000002807dd0/d .functor NAND 1, L_0000000002808d20, L_0000000002808070, L_0000000002808930, L_0000000002809730; +L_0000000002807dd0 .delay 1 (40000,40000,40000) L_0000000002807dd0/d; +v0000000002760ac0_0 .net "a", 0 0, L_0000000002801da0; alias, 1 drivers +v0000000002761240_0 .net "aout", 0 0, L_0000000002808d20; 1 drivers +v00000000027628c0_0 .net "b", 0 0, L_0000000002802040; alias, 1 drivers +v0000000002761b00_0 .net "bout", 0 0, L_0000000002808070; 1 drivers +v0000000002761f60_0 .net "c", 0 0, L_00000000028020b0; alias, 1 drivers +v0000000002763040_0 .net "cout", 0 0, L_0000000002808930; 1 drivers +v0000000002761100_0 .net "d", 0 0, L_0000000002801e10; alias, 1 drivers +v00000000027623c0_0 .net "dout", 0 0, L_0000000002809730; 1 drivers +v00000000027619c0_0 .net "ns0", 0 0, L_0000000002808f50; 1 drivers +v0000000002760980_0 .net "ns1", 0 0, L_0000000002808230; 1 drivers +v0000000002760a20_0 .net "out", 0 0, L_0000000002807dd0; alias, 1 drivers +v0000000002760c00_0 .net "s0", 0 0, L_00000000027967e0; 1 drivers +v00000000027617e0_0 .net "s1", 0 0, L_0000000002796ba0; 1 drivers +S_000000000275dea0 .scope generate, "aluBits[17]" "aluBits[17]" 4 49, 4 49 0, S_0000000000cc7490; + .timescale -9 -12; +P_0000000000f060e0 .param/l "i" 0 4 49, +C4<010001>; +L_00000000028084d0/d .functor XOR 1, L_0000000002797000, v0000000000e68bd0_0, C4<0>, C4<0>; +L_00000000028084d0 .delay 1 (20000,20000,20000) L_00000000028084d0/d; +L_00000000028089a0/d .functor AND 1, v0000000000e67370_0, L_0000000002795340, C4<1>, C4<1>; +L_00000000028089a0 .delay 1 (30000,30000,30000) L_00000000028089a0/d; +L_0000000002808ee0/d .functor AND 1, L_00000000027999e0, L_000000000282c280, C4<1>, C4<1>; +L_0000000002808ee0 .delay 1 (30000,30000,30000) L_0000000002808ee0/d; +v00000000027648a0_0 .net *"_s1", 0 0, L_0000000002797000; 1 drivers +v0000000002764a80_0 .net *"_s3", 0 0, L_0000000002795340; 1 drivers +v0000000002764940_0 .net *"_s9", 0 0, L_00000000027999e0; 1 drivers +S_000000000275c0a0 .scope module, "_bit" "aluFullBit" 4 52, 5 6 0, S_000000000275dea0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "res" + .port_info 1 /OUTPUT 1 "carryAND" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "cin" + .port_info 5 /INPUT 1 "ctrl0" + .port_info 6 /INPUT 2 "sel" +v0000000002763b80_0 .net "a", 0 0, L_00000000027971e0; 1 drivers +v0000000002763720_0 .net "b", 0 0, L_0000000002795520; 1 drivers +v0000000002763c20_0 .net "carryAND", 0 0, L_00000000028095e0; 1 drivers +v0000000002765020_0 .net "cin", 0 0, L_00000000027955c0; 1 drivers +v0000000002763cc0_0 .net "ctrl0", 0 0, L_0000000002797d20; 1 drivers +v00000000027649e0_0 .net "nab", 0 0, L_00000000028080e0; 1 drivers +v0000000002763220_0 .net "orNOR", 0 0, L_00000000028090a0; 1 drivers +v0000000002764080_0 .net "res", 0 0, L_0000000002809340; 1 drivers +v0000000002763d60_0 .net "sel", 1 0, v0000000000e625f0_0; alias, 1 drivers +v0000000002763f40_0 .net "sumXOR", 0 0, L_0000000002808310; 1 drivers +L_00000000027957a0 .part v0000000000e625f0_0, 1, 1; +L_0000000002797820 .part v0000000000e625f0_0, 0, 1; +S_000000000275c9a0 .scope module, "alu" "aluBit" 5 18, 6 14 0, S_000000000275c0a0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sumXOR" + .port_info 1 /OUTPUT 1 "carryAND" + .port_info 2 /OUTPUT 1 "nab" + .port_info 3 /OUTPUT 1 "orNOR" + .port_info 4 /INPUT 1 "a" + .port_info 5 /INPUT 1 "b" + .port_info 6 /INPUT 1 "carryin" + .port_info 7 /INPUT 1 "i0" +L_00000000028080e0/d .functor NAND 1, L_00000000027971e0, L_0000000002795520, C4<1>, C4<1>; +L_00000000028080e0 .delay 1 (20000,20000,20000) L_00000000028080e0/d; +L_0000000002808540/d .functor NAND 1, L_0000000002795520, L_00000000027955c0, C4<1>, C4<1>; +L_0000000002808540 .delay 1 (20000,20000,20000) L_0000000002808540/d; +L_0000000002807f90/d .functor NAND 1, L_00000000027971e0, L_00000000027955c0, C4<1>, C4<1>; +L_0000000002807f90 .delay 1 (20000,20000,20000) L_0000000002807f90/d; +L_00000000028095e0/d .functor NAND 1, L_00000000028080e0, L_0000000002807f90, L_0000000002808540, C4<1>; +L_00000000028095e0 .delay 1 (30000,30000,30000) L_00000000028095e0/d; +L_0000000002808310/d .functor XOR 1, L_00000000027971e0, L_0000000002795520, L_00000000027955c0, C4<0>; +L_0000000002808310 .delay 1 (30000,30000,30000) L_0000000002808310/d; +L_0000000002808d90/d .functor NOR 1, L_00000000027971e0, L_0000000002795520, C4<0>, C4<0>; +L_0000000002808d90 .delay 1 (20000,20000,20000) L_0000000002808d90/d; +L_00000000028090a0/d .functor XOR 1, L_0000000002808d90, L_0000000002797d20, C4<0>, C4<0>; +L_00000000028090a0 .delay 1 (20000,20000,20000) L_00000000028090a0/d; +v0000000002762f00_0 .net "a", 0 0, L_00000000027971e0; alias, 1 drivers +v0000000002761d80_0 .net "anorb", 0 0, L_0000000002808d90; 1 drivers +v00000000027614c0_0 .net "b", 0 0, L_0000000002795520; alias, 1 drivers +v0000000002762e60_0 .net "carryAND", 0 0, L_00000000028095e0; alias, 1 drivers +v0000000002761e20_0 .net "carryin", 0 0, L_00000000027955c0; alias, 1 drivers +v0000000002761ec0_0 .net "i0", 0 0, L_0000000002797d20; alias, 1 drivers +v00000000027625a0_0 .net "nab", 0 0, L_00000000028080e0; alias, 1 drivers +v0000000002760d40_0 .net "nac", 0 0, L_0000000002807f90; 1 drivers +v0000000002762be0_0 .net "nbc", 0 0, L_0000000002808540; 1 drivers +v0000000002762c80_0 .net "orNOR", 0 0, L_00000000028090a0; alias, 1 drivers +v0000000002762fa0_0 .net "sumXOR", 0 0, L_0000000002808310; alias, 1 drivers +S_000000000275dba0 .scope module, "mux" "multiplexer" 5 20, 7 7 0, S_000000000275c0a0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "a" + .port_info 2 /INPUT 1 "b" + .port_info 3 /INPUT 1 "c" + .port_info 4 /INPUT 1 "d" + .port_info 5 /INPUT 1 "s1" + .port_info 6 /INPUT 1 "s0" +L_0000000002808e00/d .functor NOT 1, L_0000000002797820, C4<0>, C4<0>, C4<0>; +L_0000000002808e00 .delay 1 (10000,10000,10000) L_0000000002808e00/d; +L_0000000002809110/d .functor NOT 1, L_00000000027957a0, C4<0>, C4<0>, C4<0>; +L_0000000002809110 .delay 1 (10000,10000,10000) L_0000000002809110/d; +L_0000000002809570/d .functor NAND 1, L_00000000027957a0, L_0000000002797820, L_0000000002808310, C4<1>; +L_0000000002809570 .delay 1 (30000,30000,30000) L_0000000002809570/d; +L_0000000002808a80/d .functor NAND 1, L_00000000027957a0, L_0000000002808e00, L_00000000028090a0, C4<1>; +L_0000000002808a80 .delay 1 (30000,30000,30000) L_0000000002808a80/d; +L_00000000028088c0/d .functor NAND 1, L_0000000002809110, L_0000000002797820, L_00000000028095e0, C4<1>; +L_00000000028088c0 .delay 1 (30000,30000,30000) L_00000000028088c0/d; +L_0000000002808150/d .functor NAND 1, L_0000000002809110, L_0000000002808e00, L_00000000028080e0, C4<1>; +L_0000000002808150 .delay 1 (30000,30000,30000) L_0000000002808150/d; +L_0000000002809340/d .functor NAND 1, L_0000000002809570, L_0000000002808a80, L_00000000028088c0, L_0000000002808150; +L_0000000002809340 .delay 1 (40000,40000,40000) L_0000000002809340/d; +v0000000002763ae0_0 .net "a", 0 0, L_0000000002808310; alias, 1 drivers +v0000000002763900_0 .net "aout", 0 0, L_0000000002809570; 1 drivers +v0000000002764120_0 .net "b", 0 0, L_00000000028090a0; alias, 1 drivers +v0000000002763860_0 .net "bout", 0 0, L_0000000002808a80; 1 drivers +v00000000027639a0_0 .net "c", 0 0, L_00000000028095e0; alias, 1 drivers +v00000000027643a0_0 .net "cout", 0 0, L_00000000028088c0; 1 drivers +v0000000002764bc0_0 .net "d", 0 0, L_00000000028080e0; alias, 1 drivers +v00000000027637c0_0 .net "dout", 0 0, L_0000000002808150; 1 drivers +v0000000002764c60_0 .net "ns0", 0 0, L_0000000002808e00; 1 drivers +v0000000002763680_0 .net "ns1", 0 0, L_0000000002809110; 1 drivers +v0000000002763a40_0 .net "out", 0 0, L_0000000002809340; alias, 1 drivers +v0000000002763180_0 .net "s0", 0 0, L_0000000002797820; 1 drivers +v0000000002765660_0 .net "s1", 0 0, L_00000000027957a0; 1 drivers +S_000000000275c3a0 .scope generate, "aluBits[18]" "aluBits[18]" 4 49, 4 49 0, S_0000000000cc7490; + .timescale -9 -12; +P_0000000000f06820 .param/l "i" 0 4 49, +C4<010010>; +L_00000000028093b0/d .functor XOR 1, L_00000000027989a0, v0000000000e68bd0_0, C4<0>, C4<0>; +L_00000000028093b0 .delay 1 (20000,20000,20000) L_00000000028093b0/d; +L_0000000002808fc0/d .functor AND 1, v0000000000e67370_0, L_0000000002797fa0, C4<1>, C4<1>; +L_0000000002808fc0 .delay 1 (30000,30000,30000) L_0000000002808fc0/d; +L_00000000028083f0/d .functor AND 1, L_0000000002799440, L_000000000282c280, C4<1>, C4<1>; +L_00000000028083f0 .delay 1 (30000,30000,30000) L_00000000028083f0/d; +v0000000002765700_0 .net *"_s1", 0 0, L_00000000027989a0; 1 drivers +v0000000002765520_0 .net *"_s3", 0 0, L_0000000002797fa0; 1 drivers +v00000000027655c0_0 .net *"_s9", 0 0, L_0000000002799440; 1 drivers +S_000000000275dd20 .scope module, "_bit" "aluFullBit" 4 52, 5 6 0, S_000000000275c3a0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "res" + .port_info 1 /OUTPUT 1 "carryAND" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "cin" + .port_info 5 /INPUT 1 "ctrl0" + .port_info 6 /INPUT 2 "sel" +v0000000002764e40_0 .net "a", 0 0, L_0000000002799a80; 1 drivers +v0000000002765160_0 .net "b", 0 0, L_00000000027987c0; 1 drivers +v0000000002765200_0 .net "carryAND", 0 0, L_0000000002809180; 1 drivers +v00000000027652a0_0 .net "cin", 0 0, L_0000000002798680; 1 drivers +v00000000027635e0_0 .net "ctrl0", 0 0, L_0000000002798040; 1 drivers +v0000000002763360_0 .net "nab", 0 0, L_0000000002809030; 1 drivers +v00000000027634a0_0 .net "orNOR", 0 0, L_0000000002809650; 1 drivers +v0000000002763540_0 .net "res", 0 0, L_0000000002809490; 1 drivers +v0000000002765340_0 .net "sel", 1 0, v0000000000e625f0_0; alias, 1 drivers +v0000000002765480_0 .net "sumXOR", 0 0, L_00000000028082a0; 1 drivers +L_000000000279a020 .part v0000000000e625f0_0, 1, 1; +L_00000000027985e0 .part v0000000000e625f0_0, 0, 1; +S_000000000275c520 .scope module, "alu" "aluBit" 5 18, 6 14 0, S_000000000275dd20; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sumXOR" + .port_info 1 /OUTPUT 1 "carryAND" + .port_info 2 /OUTPUT 1 "nab" + .port_info 3 /OUTPUT 1 "orNOR" + .port_info 4 /INPUT 1 "a" + .port_info 5 /INPUT 1 "b" + .port_info 6 /INPUT 1 "carryin" + .port_info 7 /INPUT 1 "i0" +L_0000000002809030/d .functor NAND 1, L_0000000002799a80, L_00000000027987c0, C4<1>, C4<1>; +L_0000000002809030 .delay 1 (20000,20000,20000) L_0000000002809030/d; +L_00000000028091f0/d .functor NAND 1, L_00000000027987c0, L_0000000002798680, C4<1>, C4<1>; +L_00000000028091f0 .delay 1 (20000,20000,20000) L_00000000028091f0/d; +L_00000000028081c0/d .functor NAND 1, L_0000000002799a80, L_0000000002798680, C4<1>, C4<1>; +L_00000000028081c0 .delay 1 (20000,20000,20000) L_00000000028081c0/d; +L_0000000002809180/d .functor NAND 1, L_0000000002809030, L_00000000028081c0, L_00000000028091f0, C4<1>; +L_0000000002809180 .delay 1 (30000,30000,30000) L_0000000002809180/d; +L_00000000028082a0/d .functor XOR 1, L_0000000002799a80, L_00000000027987c0, L_0000000002798680, C4<0>; +L_00000000028082a0 .delay 1 (30000,30000,30000) L_00000000028082a0/d; +L_0000000002807e40/d .functor NOR 1, L_0000000002799a80, L_00000000027987c0, C4<0>, C4<0>; +L_0000000002807e40 .delay 1 (20000,20000,20000) L_0000000002807e40/d; +L_0000000002809650/d .functor XOR 1, L_0000000002807e40, L_0000000002798040, C4<0>, C4<0>; +L_0000000002809650 .delay 1 (20000,20000,20000) L_0000000002809650/d; +v0000000002763e00_0 .net "a", 0 0, L_0000000002799a80; alias, 1 drivers +v0000000002764260_0 .net "anorb", 0 0, L_0000000002807e40; 1 drivers +v0000000002764d00_0 .net "b", 0 0, L_00000000027987c0; alias, 1 drivers +v00000000027644e0_0 .net "carryAND", 0 0, L_0000000002809180; alias, 1 drivers +v00000000027632c0_0 .net "carryin", 0 0, L_0000000002798680; alias, 1 drivers +v0000000002763ea0_0 .net "i0", 0 0, L_0000000002798040; alias, 1 drivers +v0000000002763fe0_0 .net "nab", 0 0, L_0000000002809030; alias, 1 drivers +v00000000027641c0_0 .net "nac", 0 0, L_00000000028081c0; 1 drivers +v0000000002764300_0 .net "nbc", 0 0, L_00000000028091f0; 1 drivers +v00000000027646c0_0 .net "orNOR", 0 0, L_0000000002809650; alias, 1 drivers +v0000000002765840_0 .net "sumXOR", 0 0, L_00000000028082a0; alias, 1 drivers +S_000000000275c220 .scope module, "mux" "multiplexer" 5 20, 7 7 0, S_000000000275dd20; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "a" + .port_info 2 /INPUT 1 "b" + .port_info 3 /INPUT 1 "c" + .port_info 4 /INPUT 1 "d" + .port_info 5 /INPUT 1 "s1" + .port_info 6 /INPUT 1 "s0" +L_0000000002808bd0/d .functor NOT 1, L_00000000027985e0, C4<0>, C4<0>, C4<0>; +L_0000000002808bd0 .delay 1 (10000,10000,10000) L_0000000002808bd0/d; +L_00000000028092d0/d .functor NOT 1, L_000000000279a020, C4<0>, C4<0>, C4<0>; +L_00000000028092d0 .delay 1 (10000,10000,10000) L_00000000028092d0/d; +L_0000000002808380/d .functor NAND 1, L_000000000279a020, L_00000000027985e0, L_00000000028082a0, C4<1>; +L_0000000002808380 .delay 1 (30000,30000,30000) L_0000000002808380/d; +L_0000000002809420/d .functor NAND 1, L_000000000279a020, L_0000000002808bd0, L_0000000002809650, C4<1>; +L_0000000002809420 .delay 1 (30000,30000,30000) L_0000000002809420/d; +L_00000000028096c0/d .functor NAND 1, L_00000000028092d0, L_00000000027985e0, L_0000000002809180, C4<1>; +L_00000000028096c0 .delay 1 (30000,30000,30000) L_00000000028096c0/d; +L_00000000028097a0/d .functor NAND 1, L_00000000028092d0, L_0000000002808bd0, L_0000000002809030, C4<1>; +L_00000000028097a0 .delay 1 (30000,30000,30000) L_00000000028097a0/d; +L_0000000002809490/d .functor NAND 1, L_0000000002808380, L_0000000002809420, L_00000000028096c0, L_00000000028097a0; +L_0000000002809490 .delay 1 (40000,40000,40000) L_0000000002809490/d; +v0000000002764800_0 .net "a", 0 0, L_00000000028082a0; alias, 1 drivers +v0000000002764f80_0 .net "aout", 0 0, L_0000000002808380; 1 drivers +v0000000002764440_0 .net "b", 0 0, L_0000000002809650; alias, 1 drivers +v00000000027630e0_0 .net "bout", 0 0, L_0000000002809420; 1 drivers +v0000000002763400_0 .net "c", 0 0, L_0000000002809180; alias, 1 drivers +v00000000027653e0_0 .net "cout", 0 0, L_00000000028096c0; 1 drivers +v0000000002764580_0 .net "d", 0 0, L_0000000002809030; alias, 1 drivers +v0000000002764b20_0 .net "dout", 0 0, L_00000000028097a0; 1 drivers +v0000000002764620_0 .net "ns0", 0 0, L_0000000002808bd0; 1 drivers +v0000000002764760_0 .net "ns1", 0 0, L_00000000028092d0; 1 drivers +v0000000002764ee0_0 .net "out", 0 0, L_0000000002809490; alias, 1 drivers +v0000000002764da0_0 .net "s0", 0 0, L_00000000027985e0; 1 drivers +v00000000027650c0_0 .net "s1", 0 0, L_000000000279a020; 1 drivers +S_000000000275da20 .scope generate, "aluBits[19]" "aluBits[19]" 4 49, 4 49 0, S_0000000000cc7490; + .timescale -9 -12; +P_0000000000f062e0 .param/l "i" 0 4 49, +C4<010011>; +L_0000000002808460/d .functor XOR 1, L_00000000027994e0, v0000000000e68bd0_0, C4<0>, C4<0>; +L_0000000002808460 .delay 1 (20000,20000,20000) L_0000000002808460/d; +L_0000000002808a10/d .functor AND 1, v0000000000e67370_0, L_0000000002799b20, C4<1>, C4<1>; +L_0000000002808a10 .delay 1 (30000,30000,30000) L_0000000002808a10/d; +L_0000000002808000/d .functor AND 1, L_0000000002797f00, L_000000000282c280, C4<1>, C4<1>; +L_0000000002808000 .delay 1 (30000,30000,30000) L_0000000002808000/d; +v0000000002766600_0 .net *"_s1", 0 0, L_00000000027994e0; 1 drivers +v00000000027666a0_0 .net *"_s3", 0 0, L_0000000002799b20; 1 drivers +v0000000002767320_0 .net *"_s9", 0 0, L_0000000002797f00; 1 drivers +S_000000000275c820 .scope module, "_bit" "aluFullBit" 4 52, 5 6 0, S_000000000275da20; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "res" + .port_info 1 /OUTPUT 1 "carryAND" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "cin" + .port_info 5 /INPUT 1 "ctrl0" + .port_info 6 /INPUT 2 "sel" +v0000000002765de0_0 .net "a", 0 0, L_0000000002798220; 1 drivers +v00000000027670a0_0 .net "b", 0 0, L_0000000002798180; 1 drivers +v00000000027664c0_0 .net "carryAND", 0 0, L_0000000002809810; 1 drivers +v0000000002765e80_0 .net "cin", 0 0, L_0000000002799da0; 1 drivers +v0000000002767140_0 .net "ctrl0", 0 0, L_0000000002798c20; 1 drivers +v0000000002767640_0 .net "nab", 0 0, L_0000000002808e70; 1 drivers +v0000000002767c80_0 .net "orNOR", 0 0, L_00000000028087e0; 1 drivers +v0000000002765fc0_0 .net "res", 0 0, L_0000000002808c40; 1 drivers +v0000000002766560_0 .net "sel", 1 0, v0000000000e625f0_0; alias, 1 drivers +v0000000002767a00_0 .net "sumXOR", 0 0, L_0000000002808770; 1 drivers +L_0000000002798ea0 .part v0000000000e625f0_0, 1, 1; +L_0000000002799300 .part v0000000000e625f0_0, 0, 1; +S_000000000275d120 .scope module, "alu" "aluBit" 5 18, 6 14 0, S_000000000275c820; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sumXOR" + .port_info 1 /OUTPUT 1 "carryAND" + .port_info 2 /OUTPUT 1 "nab" + .port_info 3 /OUTPUT 1 "orNOR" + .port_info 4 /INPUT 1 "a" + .port_info 5 /INPUT 1 "b" + .port_info 6 /INPUT 1 "carryin" + .port_info 7 /INPUT 1 "i0" +L_0000000002808e70/d .functor NAND 1, L_0000000002798220, L_0000000002798180, C4<1>, C4<1>; +L_0000000002808e70 .delay 1 (20000,20000,20000) L_0000000002808e70/d; +L_0000000002809500/d .functor NAND 1, L_0000000002798180, L_0000000002799da0, C4<1>, C4<1>; +L_0000000002809500 .delay 1 (20000,20000,20000) L_0000000002809500/d; +L_0000000002808af0/d .functor NAND 1, L_0000000002798220, L_0000000002799da0, C4<1>, C4<1>; +L_0000000002808af0 .delay 1 (20000,20000,20000) L_0000000002808af0/d; +L_0000000002809810/d .functor NAND 1, L_0000000002808e70, L_0000000002808af0, L_0000000002809500, C4<1>; +L_0000000002809810 .delay 1 (30000,30000,30000) L_0000000002809810/d; +L_0000000002808770/d .functor XOR 1, L_0000000002798220, L_0000000002798180, L_0000000002799da0, C4<0>; +L_0000000002808770 .delay 1 (30000,30000,30000) L_0000000002808770/d; +L_0000000002809880/d .functor NOR 1, L_0000000002798220, L_0000000002798180, C4<0>, C4<0>; +L_0000000002809880 .delay 1 (20000,20000,20000) L_0000000002809880/d; +L_00000000028087e0/d .functor XOR 1, L_0000000002809880, L_0000000002798c20, C4<0>, C4<0>; +L_00000000028087e0 .delay 1 (20000,20000,20000) L_00000000028087e0/d; +v00000000027657a0_0 .net "a", 0 0, L_0000000002798220; alias, 1 drivers +v00000000027671e0_0 .net "anorb", 0 0, L_0000000002809880; 1 drivers +v0000000002767960_0 .net "b", 0 0, L_0000000002798180; alias, 1 drivers +v0000000002767000_0 .net "carryAND", 0 0, L_0000000002809810; alias, 1 drivers +v00000000027662e0_0 .net "carryin", 0 0, L_0000000002799da0; alias, 1 drivers +v0000000002766100_0 .net "i0", 0 0, L_0000000002798c20; alias, 1 drivers +v0000000002766e20_0 .net "nab", 0 0, L_0000000002808e70; alias, 1 drivers +v0000000002767780_0 .net "nac", 0 0, L_0000000002808af0; 1 drivers +v0000000002766060_0 .net "nbc", 0 0, L_0000000002809500; 1 drivers +v00000000027661a0_0 .net "orNOR", 0 0, L_00000000028087e0; alias, 1 drivers +v0000000002766ba0_0 .net "sumXOR", 0 0, L_0000000002808770; alias, 1 drivers +S_000000000275d720 .scope module, "mux" "multiplexer" 5 20, 7 7 0, S_000000000275c820; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "a" + .port_info 2 /INPUT 1 "b" + .port_info 3 /INPUT 1 "c" + .port_info 4 /INPUT 1 "d" + .port_info 5 /INPUT 1 "s1" + .port_info 6 /INPUT 1 "s0" +L_00000000028098f0/d .functor NOT 1, L_0000000002799300, C4<0>, C4<0>, C4<0>; +L_00000000028098f0 .delay 1 (10000,10000,10000) L_00000000028098f0/d; +L_0000000002809960/d .functor NOT 1, L_0000000002798ea0, C4<0>, C4<0>, C4<0>; +L_0000000002809960 .delay 1 (10000,10000,10000) L_0000000002809960/d; +L_0000000002807eb0/d .functor NAND 1, L_0000000002798ea0, L_0000000002799300, L_0000000002808770, C4<1>; +L_0000000002807eb0 .delay 1 (30000,30000,30000) L_0000000002807eb0/d; +L_0000000002808850/d .functor NAND 1, L_0000000002798ea0, L_00000000028098f0, L_00000000028087e0, C4<1>; +L_0000000002808850 .delay 1 (30000,30000,30000) L_0000000002808850/d; +L_0000000002807f20/d .functor NAND 1, L_0000000002809960, L_0000000002799300, L_0000000002809810, C4<1>; +L_0000000002807f20 .delay 1 (30000,30000,30000) L_0000000002807f20/d; +L_0000000002808b60/d .functor NAND 1, L_0000000002809960, L_00000000028098f0, L_0000000002808e70, C4<1>; +L_0000000002808b60 .delay 1 (30000,30000,30000) L_0000000002808b60/d; +L_0000000002808c40/d .functor NAND 1, L_0000000002807eb0, L_0000000002808850, L_0000000002807f20, L_0000000002808b60; +L_0000000002808c40 .delay 1 (40000,40000,40000) L_0000000002808c40/d; +v0000000002767500_0 .net "a", 0 0, L_0000000002808770; alias, 1 drivers +v0000000002767aa0_0 .net "aout", 0 0, L_0000000002807eb0; 1 drivers +v0000000002766d80_0 .net "b", 0 0, L_00000000028087e0; alias, 1 drivers +v0000000002766380_0 .net "bout", 0 0, L_0000000002808850; 1 drivers +v00000000027673c0_0 .net "c", 0 0, L_0000000002809810; alias, 1 drivers +v0000000002767b40_0 .net "cout", 0 0, L_0000000002807f20; 1 drivers +v0000000002767be0_0 .net "d", 0 0, L_0000000002808e70; alias, 1 drivers +v0000000002767820_0 .net "dout", 0 0, L_0000000002808b60; 1 drivers +v0000000002766420_0 .net "ns0", 0 0, L_00000000028098f0; 1 drivers +v0000000002767280_0 .net "ns1", 0 0, L_0000000002809960; 1 drivers +v0000000002765980_0 .net "out", 0 0, L_0000000002808c40; alias, 1 drivers +v0000000002766880_0 .net "s0", 0 0, L_0000000002799300; 1 drivers +v0000000002766240_0 .net "s1", 0 0, L_0000000002798ea0; 1 drivers +S_000000000275d2a0 .scope generate, "aluBits[20]" "aluBits[20]" 4 49, 4 49 0, S_0000000000cc7490; + .timescale -9 -12; +P_0000000000f061e0 .param/l "i" 0 4 49, +C4<010100>; +L_00000000028085b0/d .functor XOR 1, L_0000000002799c60, v0000000000e68bd0_0, C4<0>, C4<0>; +L_00000000028085b0 .delay 1 (20000,20000,20000) L_00000000028085b0/d; +L_0000000002808620/d .functor AND 1, v0000000000e67370_0, L_00000000027982c0, C4<1>, C4<1>; +L_0000000002808620 .delay 1 (30000,30000,30000) L_0000000002808620/d; +L_0000000002809ce0/d .functor AND 1, L_0000000002798360, L_000000000282c280, C4<1>, C4<1>; +L_0000000002809ce0 .delay 1 (30000,30000,30000) L_0000000002809ce0/d; +v00000000027696c0_0 .net *"_s1", 0 0, L_0000000002799c60; 1 drivers +v000000000276a160_0 .net *"_s3", 0 0, L_00000000027982c0; 1 drivers +v0000000002768860_0 .net *"_s9", 0 0, L_0000000002798360; 1 drivers +S_000000000275d420 .scope module, "_bit" "aluFullBit" 4 52, 5 6 0, S_000000000275d2a0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "res" + .port_info 1 /OUTPUT 1 "carryAND" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "cin" + .port_info 5 /INPUT 1 "ctrl0" + .port_info 6 /INPUT 2 "sel" +v0000000002766b00_0 .net "a", 0 0, L_0000000002798900; 1 drivers +v0000000002766ec0_0 .net "b", 0 0, L_0000000002798720; 1 drivers +v0000000002766c40_0 .net "carryAND", 0 0, L_0000000002809ff0; 1 drivers +v0000000002766f60_0 .net "cin", 0 0, L_0000000002797a00; 1 drivers +v0000000002768b80_0 .net "ctrl0", 0 0, L_0000000002799620; 1 drivers +v000000000276a700_0 .net "nab", 0 0, L_0000000002808cb0; 1 drivers +v0000000002769800_0 .net "orNOR", 0 0, L_0000000002809d50; 1 drivers +v0000000002768360_0 .net "res", 0 0, L_0000000002809ab0; 1 drivers +v000000000276a520_0 .net "sel", 1 0, v0000000000e625f0_0; alias, 1 drivers +v000000000276a480_0 .net "sumXOR", 0 0, L_0000000002809a40; 1 drivers +L_0000000002798cc0 .part v0000000000e625f0_0, 1, 1; +L_0000000002799580 .part v0000000000e625f0_0, 0, 1; +S_000000000275d8a0 .scope module, "alu" "aluBit" 5 18, 6 14 0, S_000000000275d420; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sumXOR" + .port_info 1 /OUTPUT 1 "carryAND" + .port_info 2 /OUTPUT 1 "nab" + .port_info 3 /OUTPUT 1 "orNOR" + .port_info 4 /INPUT 1 "a" + .port_info 5 /INPUT 1 "b" + .port_info 6 /INPUT 1 "carryin" + .port_info 7 /INPUT 1 "i0" +L_0000000002808cb0/d .functor NAND 1, L_0000000002798900, L_0000000002798720, C4<1>, C4<1>; +L_0000000002808cb0 .delay 1 (20000,20000,20000) L_0000000002808cb0/d; +L_0000000002808690/d .functor NAND 1, L_0000000002798720, L_0000000002797a00, C4<1>, C4<1>; +L_0000000002808690 .delay 1 (20000,20000,20000) L_0000000002808690/d; +L_0000000002808700/d .functor NAND 1, L_0000000002798900, L_0000000002797a00, C4<1>, C4<1>; +L_0000000002808700 .delay 1 (20000,20000,20000) L_0000000002808700/d; +L_0000000002809ff0/d .functor NAND 1, L_0000000002808cb0, L_0000000002808700, L_0000000002808690, C4<1>; +L_0000000002809ff0 .delay 1 (30000,30000,30000) L_0000000002809ff0/d; +L_0000000002809a40/d .functor XOR 1, L_0000000002798900, L_0000000002798720, L_0000000002797a00, C4<0>; +L_0000000002809a40 .delay 1 (30000,30000,30000) L_0000000002809a40/d; +L_0000000002809c00/d .functor NOR 1, L_0000000002798900, L_0000000002798720, C4<0>, C4<0>; +L_0000000002809c00 .delay 1 (20000,20000,20000) L_0000000002809c00/d; +L_0000000002809d50/d .functor XOR 1, L_0000000002809c00, L_0000000002799620, C4<0>, C4<0>; +L_0000000002809d50 .delay 1 (20000,20000,20000) L_0000000002809d50/d; +v0000000002767fa0_0 .net "a", 0 0, L_0000000002798900; alias, 1 drivers +v00000000027676e0_0 .net "anorb", 0 0, L_0000000002809c00; 1 drivers +v00000000027658e0_0 .net "b", 0 0, L_0000000002798720; alias, 1 drivers +v0000000002766ce0_0 .net "carryAND", 0 0, L_0000000002809ff0; alias, 1 drivers +v0000000002767460_0 .net "carryin", 0 0, L_0000000002797a00; alias, 1 drivers +v00000000027678c0_0 .net "i0", 0 0, L_0000000002799620; alias, 1 drivers +v00000000027675a0_0 .net "nab", 0 0, L_0000000002808cb0; alias, 1 drivers +v0000000002766740_0 .net "nac", 0 0, L_0000000002808700; 1 drivers +v0000000002765a20_0 .net "nbc", 0 0, L_0000000002808690; 1 drivers +v0000000002767d20_0 .net "orNOR", 0 0, L_0000000002809d50; alias, 1 drivers +v0000000002767dc0_0 .net "sumXOR", 0 0, L_0000000002809a40; alias, 1 drivers +S_000000000276e0c0 .scope module, "mux" "multiplexer" 5 20, 7 7 0, S_000000000275d420; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "a" + .port_info 2 /INPUT 1 "b" + .port_info 3 /INPUT 1 "c" + .port_info 4 /INPUT 1 "d" + .port_info 5 /INPUT 1 "s1" + .port_info 6 /INPUT 1 "s0" +L_000000000280a0d0/d .functor NOT 1, L_0000000002799580, C4<0>, C4<0>, C4<0>; +L_000000000280a0d0 .delay 1 (10000,10000,10000) L_000000000280a0d0/d; +L_000000000280a060/d .functor NOT 1, L_0000000002798cc0, C4<0>, C4<0>, C4<0>; +L_000000000280a060 .delay 1 (10000,10000,10000) L_000000000280a060/d; +L_0000000002809c70/d .functor NAND 1, L_0000000002798cc0, L_0000000002799580, L_0000000002809a40, C4<1>; +L_0000000002809c70 .delay 1 (30000,30000,30000) L_0000000002809c70/d; +L_00000000028099d0/d .functor NAND 1, L_0000000002798cc0, L_000000000280a0d0, L_0000000002809d50, C4<1>; +L_00000000028099d0 .delay 1 (30000,30000,30000) L_00000000028099d0/d; +L_0000000002809e30/d .functor NAND 1, L_000000000280a060, L_0000000002799580, L_0000000002809ff0, C4<1>; +L_0000000002809e30 .delay 1 (30000,30000,30000) L_0000000002809e30/d; +L_0000000002809f80/d .functor NAND 1, L_000000000280a060, L_000000000280a0d0, L_0000000002808cb0, C4<1>; +L_0000000002809f80 .delay 1 (30000,30000,30000) L_0000000002809f80/d; +L_0000000002809ab0/d .functor NAND 1, L_0000000002809c70, L_00000000028099d0, L_0000000002809e30, L_0000000002809f80; +L_0000000002809ab0 .delay 1 (40000,40000,40000) L_0000000002809ab0/d; +v0000000002767e60_0 .net "a", 0 0, L_0000000002809a40; alias, 1 drivers +v0000000002767f00_0 .net "aout", 0 0, L_0000000002809c70; 1 drivers +v00000000027667e0_0 .net "b", 0 0, L_0000000002809d50; alias, 1 drivers +v0000000002768040_0 .net "bout", 0 0, L_00000000028099d0; 1 drivers +v0000000002765ac0_0 .net "c", 0 0, L_0000000002809ff0; alias, 1 drivers +v0000000002765b60_0 .net "cout", 0 0, L_0000000002809e30; 1 drivers +v0000000002766920_0 .net "d", 0 0, L_0000000002808cb0; alias, 1 drivers +v0000000002765f20_0 .net "dout", 0 0, L_0000000002809f80; 1 drivers +v00000000027669c0_0 .net "ns0", 0 0, L_000000000280a0d0; 1 drivers +v0000000002765c00_0 .net "ns1", 0 0, L_000000000280a060; 1 drivers +v0000000002765d40_0 .net "out", 0 0, L_0000000002809ab0; alias, 1 drivers +v0000000002765ca0_0 .net "s0", 0 0, L_0000000002799580; 1 drivers +v0000000002766a60_0 .net "s1", 0 0, L_0000000002798cc0; 1 drivers +S_000000000276e840 .scope generate, "aluBits[21]" "aluBits[21]" 4 49, 4 49 0, S_0000000000cc7490; + .timescale -9 -12; +P_0000000000f06ba0 .param/l "i" 0 4 49, +C4<010101>; +L_0000000002809dc0/d .functor XOR 1, L_0000000002798860, v0000000000e68bd0_0, C4<0>, C4<0>; +L_0000000002809dc0 .delay 1 (20000,20000,20000) L_0000000002809dc0/d; +L_0000000002809ea0/d .functor AND 1, v0000000000e67370_0, L_0000000002797e60, C4<1>, C4<1>; +L_0000000002809ea0 .delay 1 (30000,30000,30000) L_0000000002809ea0/d; +L_0000000002807510/d .functor AND 1, L_0000000002799080, L_000000000282c280, C4<1>, C4<1>; +L_0000000002807510 .delay 1 (30000,30000,30000) L_0000000002807510/d; +v000000000276a660_0 .net *"_s1", 0 0, L_0000000002798860; 1 drivers +v0000000002768220_0 .net *"_s3", 0 0, L_0000000002797e60; 1 drivers +v0000000002769120_0 .net *"_s9", 0 0, L_0000000002799080; 1 drivers +S_000000000276e9c0 .scope module, "_bit" "aluFullBit" 4 52, 5 6 0, S_000000000276e840; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "res" + .port_info 1 /OUTPUT 1 "carryAND" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "cin" + .port_info 5 /INPUT 1 "ctrl0" + .port_info 6 /INPUT 2 "sel" +v000000000276a840_0 .net "a", 0 0, L_0000000002798a40; 1 drivers +v000000000276a5c0_0 .net "b", 0 0, L_0000000002798ae0; 1 drivers +v0000000002768fe0_0 .net "carryAND", 0 0, L_0000000002807ac0; 1 drivers +v0000000002769a80_0 .net "cin", 0 0, L_0000000002797c80; 1 drivers +v0000000002769080_0 .net "ctrl0", 0 0, L_0000000002798b80; 1 drivers +v00000000027680e0_0 .net "nab", 0 0, L_0000000002809f10; 1 drivers +v000000000276a020_0 .net "orNOR", 0 0, L_0000000002807890; 1 drivers +v000000000276a0c0_0 .net "res", 0 0, L_00000000028077b0; 1 drivers +v0000000002769c60_0 .net "sel", 1 0, v0000000000e625f0_0; alias, 1 drivers +v0000000002769760_0 .net "sumXOR", 0 0, L_0000000002806780; 1 drivers +L_0000000002797b40 .part v0000000000e625f0_0, 1, 1; +L_0000000002799bc0 .part v0000000000e625f0_0, 0, 1; +S_000000000276f740 .scope module, "alu" "aluBit" 5 18, 6 14 0, S_000000000276e9c0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sumXOR" + .port_info 1 /OUTPUT 1 "carryAND" + .port_info 2 /OUTPUT 1 "nab" + .port_info 3 /OUTPUT 1 "orNOR" + .port_info 4 /INPUT 1 "a" + .port_info 5 /INPUT 1 "b" + .port_info 6 /INPUT 1 "carryin" + .port_info 7 /INPUT 1 "i0" +L_0000000002809f10/d .functor NAND 1, L_0000000002798a40, L_0000000002798ae0, C4<1>, C4<1>; +L_0000000002809f10 .delay 1 (20000,20000,20000) L_0000000002809f10/d; +L_0000000002809b20/d .functor NAND 1, L_0000000002798ae0, L_0000000002797c80, C4<1>, C4<1>; +L_0000000002809b20 .delay 1 (20000,20000,20000) L_0000000002809b20/d; +L_0000000002809b90/d .functor NAND 1, L_0000000002798a40, L_0000000002797c80, C4<1>, C4<1>; +L_0000000002809b90 .delay 1 (20000,20000,20000) L_0000000002809b90/d; +L_0000000002807ac0/d .functor NAND 1, L_0000000002809f10, L_0000000002809b90, L_0000000002809b20, C4<1>; +L_0000000002807ac0 .delay 1 (30000,30000,30000) L_0000000002807ac0/d; +L_0000000002806780/d .functor XOR 1, L_0000000002798a40, L_0000000002798ae0, L_0000000002797c80, C4<0>; +L_0000000002806780 .delay 1 (30000,30000,30000) L_0000000002806780/d; +L_00000000028061d0/d .functor NOR 1, L_0000000002798a40, L_0000000002798ae0, C4<0>, C4<0>; +L_00000000028061d0 .delay 1 (20000,20000,20000) L_00000000028061d0/d; +L_0000000002807890/d .functor XOR 1, L_00000000028061d0, L_0000000002798b80, C4<0>, C4<0>; +L_0000000002807890 .delay 1 (20000,20000,20000) L_0000000002807890/d; +v0000000002768a40_0 .net "a", 0 0, L_0000000002798a40; alias, 1 drivers +v0000000002768e00_0 .net "anorb", 0 0, L_00000000028061d0; 1 drivers +v0000000002768180_0 .net "b", 0 0, L_0000000002798ae0; alias, 1 drivers +v0000000002769d00_0 .net "carryAND", 0 0, L_0000000002807ac0; alias, 1 drivers +v00000000027698a0_0 .net "carryin", 0 0, L_0000000002797c80; alias, 1 drivers +v0000000002768900_0 .net "i0", 0 0, L_0000000002798b80; alias, 1 drivers +v0000000002768c20_0 .net "nab", 0 0, L_0000000002809f10; alias, 1 drivers +v0000000002768ae0_0 .net "nac", 0 0, L_0000000002809b90; 1 drivers +v0000000002769bc0_0 .net "nbc", 0 0, L_0000000002809b20; 1 drivers +v000000000276a2a0_0 .net "orNOR", 0 0, L_0000000002807890; alias, 1 drivers +v000000000276a340_0 .net "sumXOR", 0 0, L_0000000002806780; alias, 1 drivers +S_000000000276ee40 .scope module, "mux" "multiplexer" 5 20, 7 7 0, S_000000000276e9c0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "a" + .port_info 2 /INPUT 1 "b" + .port_info 3 /INPUT 1 "c" + .port_info 4 /INPUT 1 "d" + .port_info 5 /INPUT 1 "s1" + .port_info 6 /INPUT 1 "s0" +L_00000000028067f0/d .functor NOT 1, L_0000000002799bc0, C4<0>, C4<0>, C4<0>; +L_00000000028067f0 .delay 1 (10000,10000,10000) L_00000000028067f0/d; +L_0000000002806860/d .functor NOT 1, L_0000000002797b40, C4<0>, C4<0>, C4<0>; +L_0000000002806860 .delay 1 (10000,10000,10000) L_0000000002806860/d; +L_0000000002807b30/d .functor NAND 1, L_0000000002797b40, L_0000000002799bc0, L_0000000002806780, C4<1>; +L_0000000002807b30 .delay 1 (30000,30000,30000) L_0000000002807b30/d; +L_0000000002807c10/d .functor NAND 1, L_0000000002797b40, L_00000000028067f0, L_0000000002807890, C4<1>; +L_0000000002807c10 .delay 1 (30000,30000,30000) L_0000000002807c10/d; +L_0000000002806550/d .functor NAND 1, L_0000000002806860, L_0000000002799bc0, L_0000000002807ac0, C4<1>; +L_0000000002806550 .delay 1 (30000,30000,30000) L_0000000002806550/d; +L_00000000028075f0/d .functor NAND 1, L_0000000002806860, L_00000000028067f0, L_0000000002809f10, C4<1>; +L_00000000028075f0 .delay 1 (30000,30000,30000) L_00000000028075f0/d; +L_00000000028077b0/d .functor NAND 1, L_0000000002807b30, L_0000000002807c10, L_0000000002806550, L_00000000028075f0; +L_00000000028077b0 .delay 1 (40000,40000,40000) L_00000000028077b0/d; +v0000000002768f40_0 .net "a", 0 0, L_0000000002806780; alias, 1 drivers +v0000000002768cc0_0 .net "aout", 0 0, L_0000000002807b30; 1 drivers +v000000000276a200_0 .net "b", 0 0, L_0000000002807890; alias, 1 drivers +v0000000002769f80_0 .net "bout", 0 0, L_0000000002807c10; 1 drivers +v0000000002768ea0_0 .net "c", 0 0, L_0000000002807ac0; alias, 1 drivers +v00000000027699e0_0 .net "cout", 0 0, L_0000000002806550; 1 drivers +v00000000027685e0_0 .net "d", 0 0, L_0000000002809f10; alias, 1 drivers +v0000000002769940_0 .net "dout", 0 0, L_00000000028075f0; 1 drivers +v0000000002769e40_0 .net "ns0", 0 0, L_00000000028067f0; 1 drivers +v000000000276a3e0_0 .net "ns1", 0 0, L_0000000002806860; 1 drivers +v00000000027687c0_0 .net "out", 0 0, L_00000000028077b0; alias, 1 drivers +v0000000002768d60_0 .net "s0", 0 0, L_0000000002799bc0; 1 drivers +v000000000276a7a0_0 .net "s1", 0 0, L_0000000002797b40; 1 drivers +S_000000000276fa40 .scope generate, "aluBits[22]" "aluBits[22]" 4 49, 4 49 0, S_0000000000cc7490; + .timescale -9 -12; +P_0000000000f06260 .param/l "i" 0 4 49, +C4<010110>; +L_0000000002807ba0/d .functor XOR 1, L_0000000002798d60, v0000000000e68bd0_0, C4<0>, C4<0>; +L_0000000002807ba0 .delay 1 (20000,20000,20000) L_0000000002807ba0/d; +L_0000000002806ef0/d .functor AND 1, v0000000000e67370_0, L_000000000279a0c0, C4<1>, C4<1>; +L_0000000002806ef0 .delay 1 (30000,30000,30000) L_0000000002806ef0/d; +L_0000000002807900/d .functor AND 1, L_00000000027991c0, L_000000000282c280, C4<1>, C4<1>; +L_0000000002807900 .delay 1 (30000,30000,30000) L_0000000002807900/d; +v000000000276b240_0 .net *"_s1", 0 0, L_0000000002798d60; 1 drivers +v000000000276afc0_0 .net *"_s3", 0 0, L_000000000279a0c0; 1 drivers +v000000000276ce60_0 .net *"_s9", 0 0, L_00000000027991c0; 1 drivers +S_000000000276e3c0 .scope module, "_bit" "aluFullBit" 4 52, 5 6 0, S_000000000276fa40; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "res" + .port_info 1 /OUTPUT 1 "carryAND" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "cin" + .port_info 5 /INPUT 1 "ctrl0" + .port_info 6 /INPUT 2 "sel" +v000000000276a8e0_0 .net "a", 0 0, L_0000000002798e00; 1 drivers +v000000000276bec0_0 .net "b", 0 0, L_0000000002798f40; 1 drivers +v000000000276b880_0 .net "carryAND", 0 0, L_0000000002807d60; 1 drivers +v000000000276b420_0 .net "cin", 0 0, L_0000000002799260; 1 drivers +v000000000276b060_0 .net "ctrl0", 0 0, L_0000000002798400; 1 drivers +v000000000276b100_0 .net "nab", 0 0, L_0000000002806e10; 1 drivers +v000000000276bb00_0 .net "orNOR", 0 0, L_0000000002806b00; 1 drivers +v000000000276b920_0 .net "res", 0 0, L_0000000002807820; 1 drivers +v000000000276c280_0 .net "sel", 1 0, v0000000000e625f0_0; alias, 1 drivers +v000000000276b1a0_0 .net "sumXOR", 0 0, L_00000000028079e0; 1 drivers +L_0000000002799d00 .part v0000000000e625f0_0, 1, 1; +L_0000000002799e40 .part v0000000000e625f0_0, 0, 1; +S_000000000276ecc0 .scope module, "alu" "aluBit" 5 18, 6 14 0, S_000000000276e3c0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sumXOR" + .port_info 1 /OUTPUT 1 "carryAND" + .port_info 2 /OUTPUT 1 "nab" + .port_info 3 /OUTPUT 1 "orNOR" + .port_info 4 /INPUT 1 "a" + .port_info 5 /INPUT 1 "b" + .port_info 6 /INPUT 1 "carryin" + .port_info 7 /INPUT 1 "i0" +L_0000000002806e10/d .functor NAND 1, L_0000000002798e00, L_0000000002798f40, C4<1>, C4<1>; +L_0000000002806e10 .delay 1 (20000,20000,20000) L_0000000002806e10/d; +L_00000000028066a0/d .functor NAND 1, L_0000000002798f40, L_0000000002799260, C4<1>, C4<1>; +L_00000000028066a0 .delay 1 (20000,20000,20000) L_00000000028066a0/d; +L_00000000028074a0/d .functor NAND 1, L_0000000002798e00, L_0000000002799260, C4<1>, C4<1>; +L_00000000028074a0 .delay 1 (20000,20000,20000) L_00000000028074a0/d; +L_0000000002807d60/d .functor NAND 1, L_0000000002806e10, L_00000000028074a0, L_00000000028066a0, C4<1>; +L_0000000002807d60 .delay 1 (30000,30000,30000) L_0000000002807d60/d; +L_00000000028079e0/d .functor XOR 1, L_0000000002798e00, L_0000000002798f40, L_0000000002799260, C4<0>; +L_00000000028079e0 .delay 1 (30000,30000,30000) L_00000000028079e0/d; +L_0000000002807740/d .functor NOR 1, L_0000000002798e00, L_0000000002798f40, C4<0>, C4<0>; +L_0000000002807740 .delay 1 (20000,20000,20000) L_0000000002807740/d; +L_0000000002806b00/d .functor XOR 1, L_0000000002807740, L_0000000002798400, C4<0>, C4<0>; +L_0000000002806b00 .delay 1 (20000,20000,20000) L_0000000002806b00/d; +v00000000027682c0_0 .net "a", 0 0, L_0000000002798e00; alias, 1 drivers +v00000000027691c0_0 .net "anorb", 0 0, L_0000000002807740; 1 drivers +v0000000002768400_0 .net "b", 0 0, L_0000000002798f40; alias, 1 drivers +v0000000002769300_0 .net "carryAND", 0 0, L_0000000002807d60; alias, 1 drivers +v0000000002769b20_0 .net "carryin", 0 0, L_0000000002799260; alias, 1 drivers +v00000000027684a0_0 .net "i0", 0 0, L_0000000002798400; alias, 1 drivers +v0000000002768540_0 .net "nab", 0 0, L_0000000002806e10; alias, 1 drivers +v0000000002769da0_0 .net "nac", 0 0, L_00000000028074a0; 1 drivers +v0000000002769ee0_0 .net "nbc", 0 0, L_00000000028066a0; 1 drivers +v00000000027693a0_0 .net "orNOR", 0 0, L_0000000002806b00; alias, 1 drivers +v0000000002768680_0 .net "sumXOR", 0 0, L_00000000028079e0; alias, 1 drivers +S_000000000276e540 .scope module, "mux" "multiplexer" 5 20, 7 7 0, S_000000000276e3c0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "a" + .port_info 2 /INPUT 1 "b" + .port_info 3 /INPUT 1 "c" + .port_info 4 /INPUT 1 "d" + .port_info 5 /INPUT 1 "s1" + .port_info 6 /INPUT 1 "s0" +L_00000000028070b0/d .functor NOT 1, L_0000000002799e40, C4<0>, C4<0>, C4<0>; +L_00000000028070b0 .delay 1 (10000,10000,10000) L_00000000028070b0/d; +L_0000000002806cc0/d .functor NOT 1, L_0000000002799d00, C4<0>, C4<0>, C4<0>; +L_0000000002806cc0 .delay 1 (10000,10000,10000) L_0000000002806cc0/d; +L_0000000002807660/d .functor NAND 1, L_0000000002799d00, L_0000000002799e40, L_00000000028079e0, C4<1>; +L_0000000002807660 .delay 1 (30000,30000,30000) L_0000000002807660/d; +L_0000000002806e80/d .functor NAND 1, L_0000000002799d00, L_00000000028070b0, L_0000000002806b00, C4<1>; +L_0000000002806e80 .delay 1 (30000,30000,30000) L_0000000002806e80/d; +L_0000000002806240/d .functor NAND 1, L_0000000002806cc0, L_0000000002799e40, L_0000000002807d60, C4<1>; +L_0000000002806240 .delay 1 (30000,30000,30000) L_0000000002806240/d; +L_00000000028062b0/d .functor NAND 1, L_0000000002806cc0, L_00000000028070b0, L_0000000002806e10, C4<1>; +L_00000000028062b0 .delay 1 (30000,30000,30000) L_00000000028062b0/d; +L_0000000002807820/d .functor NAND 1, L_0000000002807660, L_0000000002806e80, L_0000000002806240, L_00000000028062b0; +L_0000000002807820 .delay 1 (40000,40000,40000) L_0000000002807820/d; +v0000000002768720_0 .net "a", 0 0, L_00000000028079e0; alias, 1 drivers +v00000000027689a0_0 .net "aout", 0 0, L_0000000002807660; 1 drivers +v0000000002769260_0 .net "b", 0 0, L_0000000002806b00; alias, 1 drivers +v0000000002769440_0 .net "bout", 0 0, L_0000000002806e80; 1 drivers +v00000000027694e0_0 .net "c", 0 0, L_0000000002807d60; alias, 1 drivers +v0000000002769580_0 .net "cout", 0 0, L_0000000002806240; 1 drivers +v0000000002769620_0 .net "d", 0 0, L_0000000002806e10; alias, 1 drivers +v000000000276cb40_0 .net "dout", 0 0, L_00000000028062b0; 1 drivers +v000000000276b380_0 .net "ns0", 0 0, L_00000000028070b0; 1 drivers +v000000000276cf00_0 .net "ns1", 0 0, L_0000000002806cc0; 1 drivers +v000000000276c000_0 .net "out", 0 0, L_0000000002807820; alias, 1 drivers +v000000000276ab60_0 .net "s0", 0 0, L_0000000002799e40; 1 drivers +v000000000276cd20_0 .net "s1", 0 0, L_0000000002799d00; 1 drivers +S_000000000276fbc0 .scope generate, "aluBits[23]" "aluBits[23]" 4 49, 4 49 0, S_0000000000cc7490; + .timescale -9 -12; +P_0000000000f06360 .param/l "i" 0 4 49, +C4<010111>; +L_0000000002806f60/d .functor XOR 1, L_0000000002799ee0, v0000000000e68bd0_0, C4<0>, C4<0>; +L_0000000002806f60 .delay 1 (20000,20000,20000) L_0000000002806f60/d; +L_00000000028069b0/d .functor AND 1, v0000000000e67370_0, L_0000000002798fe0, C4<1>, C4<1>; +L_00000000028069b0 .delay 1 (30000,30000,30000) L_00000000028069b0/d; +L_0000000002806fd0/d .functor AND 1, L_0000000002799760, L_000000000282c280, C4<1>, C4<1>; +L_0000000002806fd0 .delay 1 (30000,30000,30000) L_0000000002806fd0/d; +v000000000276ae80_0 .net *"_s1", 0 0, L_0000000002799ee0; 1 drivers +v000000000276be20_0 .net *"_s3", 0 0, L_0000000002798fe0; 1 drivers +v000000000276c640_0 .net *"_s9", 0 0, L_0000000002799760; 1 drivers +S_000000000276f8c0 .scope module, "_bit" "aluFullBit" 4 52, 5 6 0, S_000000000276fbc0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "res" + .port_info 1 /OUTPUT 1 "carryAND" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "cin" + .port_info 5 /INPUT 1 "ctrl0" + .port_info 6 /INPUT 2 "sel" +v000000000276c500_0 .net "a", 0 0, L_00000000027996c0; 1 drivers +v000000000276ca00_0 .net "b", 0 0, L_0000000002797aa0; 1 drivers +v000000000276b6a0_0 .net "carryAND", 0 0, L_00000000028068d0; 1 drivers +v000000000276ac00_0 .net "cin", 0 0, L_00000000027993a0; 1 drivers +v000000000276bce0_0 .net "ctrl0", 0 0, L_00000000027984a0; 1 drivers +v000000000276c320_0 .net "nab", 0 0, L_0000000002807970; 1 drivers +v000000000276c5a0_0 .net "orNOR", 0 0, L_0000000002806940; 1 drivers +v000000000276bd80_0 .net "res", 0 0, L_0000000002806b70; 1 drivers +v000000000276aca0_0 .net "sel", 1 0, v0000000000e625f0_0; alias, 1 drivers +v000000000276ad40_0 .net "sumXOR", 0 0, L_0000000002806470; 1 drivers +L_0000000002799120 .part v0000000000e625f0_0, 1, 1; +L_0000000002797960 .part v0000000000e625f0_0, 0, 1; +S_000000000276fd40 .scope module, "alu" "aluBit" 5 18, 6 14 0, S_000000000276f8c0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sumXOR" + .port_info 1 /OUTPUT 1 "carryAND" + .port_info 2 /OUTPUT 1 "nab" + .port_info 3 /OUTPUT 1 "orNOR" + .port_info 4 /INPUT 1 "a" + .port_info 5 /INPUT 1 "b" + .port_info 6 /INPUT 1 "carryin" + .port_info 7 /INPUT 1 "i0" +L_0000000002807970/d .functor NAND 1, L_00000000027996c0, L_0000000002797aa0, C4<1>, C4<1>; +L_0000000002807970 .delay 1 (20000,20000,20000) L_0000000002807970/d; +L_0000000002807c80/d .functor NAND 1, L_0000000002797aa0, L_00000000027993a0, C4<1>, C4<1>; +L_0000000002807c80 .delay 1 (20000,20000,20000) L_0000000002807c80/d; +L_00000000028065c0/d .functor NAND 1, L_00000000027996c0, L_00000000027993a0, C4<1>, C4<1>; +L_00000000028065c0 .delay 1 (20000,20000,20000) L_00000000028065c0/d; +L_00000000028068d0/d .functor NAND 1, L_0000000002807970, L_00000000028065c0, L_0000000002807c80, C4<1>; +L_00000000028068d0 .delay 1 (30000,30000,30000) L_00000000028068d0/d; +L_0000000002806470/d .functor XOR 1, L_00000000027996c0, L_0000000002797aa0, L_00000000027993a0, C4<0>; +L_0000000002806470 .delay 1 (30000,30000,30000) L_0000000002806470/d; +L_0000000002807a50/d .functor NOR 1, L_00000000027996c0, L_0000000002797aa0, C4<0>, C4<0>; +L_0000000002807a50 .delay 1 (20000,20000,20000) L_0000000002807a50/d; +L_0000000002806940/d .functor XOR 1, L_0000000002807a50, L_00000000027984a0, C4<0>, C4<0>; +L_0000000002806940 .delay 1 (20000,20000,20000) L_0000000002806940/d; +v000000000276bba0_0 .net "a", 0 0, L_00000000027996c0; alias, 1 drivers +v000000000276b2e0_0 .net "anorb", 0 0, L_0000000002807a50; 1 drivers +v000000000276b9c0_0 .net "b", 0 0, L_0000000002797aa0; alias, 1 drivers +v000000000276b600_0 .net "carryAND", 0 0, L_00000000028068d0; alias, 1 drivers +v000000000276b740_0 .net "carryin", 0 0, L_00000000027993a0; alias, 1 drivers +v000000000276b4c0_0 .net "i0", 0 0, L_00000000027984a0; alias, 1 drivers +v000000000276ba60_0 .net "nab", 0 0, L_0000000002807970; alias, 1 drivers +v000000000276ade0_0 .net "nac", 0 0, L_00000000028065c0; 1 drivers +v000000000276c780_0 .net "nbc", 0 0, L_0000000002807c80; 1 drivers +v000000000276cfa0_0 .net "orNOR", 0 0, L_0000000002806940; alias, 1 drivers +v000000000276c1e0_0 .net "sumXOR", 0 0, L_0000000002806470; alias, 1 drivers +S_000000000276e6c0 .scope module, "mux" "multiplexer" 5 20, 7 7 0, S_000000000276f8c0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "a" + .port_info 2 /INPUT 1 "b" + .port_info 3 /INPUT 1 "c" + .port_info 4 /INPUT 1 "d" + .port_info 5 /INPUT 1 "s1" + .port_info 6 /INPUT 1 "s0" +L_0000000002806d30/d .functor NOT 1, L_0000000002797960, C4<0>, C4<0>, C4<0>; +L_0000000002806d30 .delay 1 (10000,10000,10000) L_0000000002806d30/d; +L_0000000002806da0/d .functor NOT 1, L_0000000002799120, C4<0>, C4<0>, C4<0>; +L_0000000002806da0 .delay 1 (10000,10000,10000) L_0000000002806da0/d; +L_0000000002806320/d .functor NAND 1, L_0000000002799120, L_0000000002797960, L_0000000002806470, C4<1>; +L_0000000002806320 .delay 1 (30000,30000,30000) L_0000000002806320/d; +L_0000000002806a20/d .functor NAND 1, L_0000000002799120, L_0000000002806d30, L_0000000002806940, C4<1>; +L_0000000002806a20 .delay 1 (30000,30000,30000) L_0000000002806a20/d; +L_0000000002806390/d .functor NAND 1, L_0000000002806da0, L_0000000002797960, L_00000000028068d0, C4<1>; +L_0000000002806390 .delay 1 (30000,30000,30000) L_0000000002806390/d; +L_0000000002806a90/d .functor NAND 1, L_0000000002806da0, L_0000000002806d30, L_0000000002807970, C4<1>; +L_0000000002806a90 .delay 1 (30000,30000,30000) L_0000000002806a90/d; +L_0000000002806b70/d .functor NAND 1, L_0000000002806320, L_0000000002806a20, L_0000000002806390, L_0000000002806a90; +L_0000000002806b70 .delay 1 (40000,40000,40000) L_0000000002806b70/d; +v000000000276c960_0 .net "a", 0 0, L_0000000002806470; alias, 1 drivers +v000000000276bc40_0 .net "aout", 0 0, L_0000000002806320; 1 drivers +v000000000276a980_0 .net "b", 0 0, L_0000000002806940; alias, 1 drivers +v000000000276d040_0 .net "bout", 0 0, L_0000000002806a20; 1 drivers +v000000000276aa20_0 .net "c", 0 0, L_00000000028068d0; alias, 1 drivers +v000000000276b560_0 .net "cout", 0 0, L_0000000002806390; 1 drivers +v000000000276c3c0_0 .net "d", 0 0, L_0000000002807970; alias, 1 drivers +v000000000276c140_0 .net "dout", 0 0, L_0000000002806a90; 1 drivers +v000000000276b7e0_0 .net "ns0", 0 0, L_0000000002806d30; 1 drivers +v000000000276aac0_0 .net "ns1", 0 0, L_0000000002806da0; 1 drivers +v000000000276c820_0 .net "out", 0 0, L_0000000002806b70; alias, 1 drivers +v000000000276c8c0_0 .net "s0", 0 0, L_0000000002797960; 1 drivers +v000000000276c460_0 .net "s1", 0 0, L_0000000002799120; 1 drivers +S_000000000276eb40 .scope generate, "aluBits[24]" "aluBits[24]" 4 49, 4 49 0, S_0000000000cc7490; + .timescale -9 -12; +P_0000000000f06e60 .param/l "i" 0 4 49, +C4<011000>; +L_00000000028073c0/d .functor XOR 1, L_0000000002799800, v0000000000e68bd0_0, C4<0>, C4<0>; +L_00000000028073c0 .delay 1 (20000,20000,20000) L_00000000028073c0/d; +L_0000000002807cf0/d .functor AND 1, v0000000000e67370_0, L_00000000027998a0, C4<1>, C4<1>; +L_0000000002807cf0 .delay 1 (30000,30000,30000) L_0000000002807cf0/d; +L_00000000028076d0/d .functor AND 1, L_000000000279afc0, L_000000000282c280, C4<1>, C4<1>; +L_00000000028076d0 .delay 1 (30000,30000,30000) L_00000000028076d0/d; +v000000000275f3a0_0 .net *"_s1", 0 0, L_0000000002799800; 1 drivers +v000000000275e180_0 .net *"_s3", 0 0, L_00000000027998a0; 1 drivers +v000000000275eae0_0 .net *"_s9", 0 0, L_000000000279afc0; 1 drivers +S_000000000276f440 .scope module, "_bit" "aluFullBit" 4 52, 5 6 0, S_000000000276eb40; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "res" + .port_info 1 /OUTPUT 1 "carryAND" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "cin" + .port_info 5 /INPUT 1 "ctrl0" + .port_info 6 /INPUT 2 "sel" +v000000000276d680_0 .net "a", 0 0, L_0000000002799f80; 1 drivers +v000000000276d900_0 .net "b", 0 0, L_0000000002799940; 1 drivers +v000000000276de00_0 .net "carryAND", 0 0, L_0000000002807430; 1 drivers +v000000000276d180_0 .net "cin", 0 0, L_0000000002797dc0; 1 drivers +v000000000276d220_0 .net "ctrl0", 0 0, L_00000000027980e0; 1 drivers +v000000000276dea0_0 .net "nab", 0 0, L_0000000002807040; 1 drivers +v000000000276d2c0_0 .net "orNOR", 0 0, L_0000000002806c50; 1 drivers +v000000000276d360_0 .net "res", 0 0, L_0000000002807580; 1 drivers +v000000000275ea40_0 .net "sel", 1 0, v0000000000e625f0_0; alias, 1 drivers +v000000000275fbc0_0 .net "sumXOR", 0 0, L_0000000002806400; 1 drivers +L_0000000002797be0 .part v0000000000e625f0_0, 1, 1; +L_0000000002798540 .part v0000000000e625f0_0, 0, 1; +S_000000000276fec0 .scope module, "alu" "aluBit" 5 18, 6 14 0, S_000000000276f440; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sumXOR" + .port_info 1 /OUTPUT 1 "carryAND" + .port_info 2 /OUTPUT 1 "nab" + .port_info 3 /OUTPUT 1 "orNOR" + .port_info 4 /INPUT 1 "a" + .port_info 5 /INPUT 1 "b" + .port_info 6 /INPUT 1 "carryin" + .port_info 7 /INPUT 1 "i0" +L_0000000002807040/d .functor NAND 1, L_0000000002799f80, L_0000000002799940, C4<1>, C4<1>; +L_0000000002807040 .delay 1 (20000,20000,20000) L_0000000002807040/d; +L_0000000002806710/d .functor NAND 1, L_0000000002799940, L_0000000002797dc0, C4<1>, C4<1>; +L_0000000002806710 .delay 1 (20000,20000,20000) L_0000000002806710/d; +L_0000000002806be0/d .functor NAND 1, L_0000000002799f80, L_0000000002797dc0, C4<1>, C4<1>; +L_0000000002806be0 .delay 1 (20000,20000,20000) L_0000000002806be0/d; +L_0000000002807430/d .functor NAND 1, L_0000000002807040, L_0000000002806be0, L_0000000002806710, C4<1>; +L_0000000002807430 .delay 1 (30000,30000,30000) L_0000000002807430/d; +L_0000000002806400/d .functor XOR 1, L_0000000002799f80, L_0000000002799940, L_0000000002797dc0, C4<0>; +L_0000000002806400 .delay 1 (30000,30000,30000) L_0000000002806400/d; +L_00000000028064e0/d .functor NOR 1, L_0000000002799f80, L_0000000002799940, C4<0>, C4<0>; +L_00000000028064e0 .delay 1 (20000,20000,20000) L_00000000028064e0/d; +L_0000000002806c50/d .functor XOR 1, L_00000000028064e0, L_00000000027980e0, C4<0>, C4<0>; +L_0000000002806c50 .delay 1 (20000,20000,20000) L_0000000002806c50/d; +v000000000276caa0_0 .net "a", 0 0, L_0000000002799f80; alias, 1 drivers +v000000000276af20_0 .net "anorb", 0 0, L_00000000028064e0; 1 drivers +v000000000276bf60_0 .net "b", 0 0, L_0000000002799940; alias, 1 drivers +v000000000276c0a0_0 .net "carryAND", 0 0, L_0000000002807430; alias, 1 drivers +v000000000276c6e0_0 .net "carryin", 0 0, L_0000000002797dc0; alias, 1 drivers +v000000000276cbe0_0 .net "i0", 0 0, L_00000000027980e0; alias, 1 drivers +v000000000276cc80_0 .net "nab", 0 0, L_0000000002807040; alias, 1 drivers +v000000000276cdc0_0 .net "nac", 0 0, L_0000000002806be0; 1 drivers +v000000000276df40_0 .net "nbc", 0 0, L_0000000002806710; 1 drivers +v000000000276d860_0 .net "orNOR", 0 0, L_0000000002806c50; alias, 1 drivers +v000000000276db80_0 .net "sumXOR", 0 0, L_0000000002806400; alias, 1 drivers +S_000000000276f5c0 .scope module, "mux" "multiplexer" 5 20, 7 7 0, S_000000000276f440; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "a" + .port_info 2 /INPUT 1 "b" + .port_info 3 /INPUT 1 "c" + .port_info 4 /INPUT 1 "d" + .port_info 5 /INPUT 1 "s1" + .port_info 6 /INPUT 1 "s0" +L_0000000002806630/d .functor NOT 1, L_0000000002798540, C4<0>, C4<0>, C4<0>; +L_0000000002806630 .delay 1 (10000,10000,10000) L_0000000002806630/d; +L_0000000002807120/d .functor NOT 1, L_0000000002797be0, C4<0>, C4<0>, C4<0>; +L_0000000002807120 .delay 1 (10000,10000,10000) L_0000000002807120/d; +L_0000000002807190/d .functor NAND 1, L_0000000002797be0, L_0000000002798540, L_0000000002806400, C4<1>; +L_0000000002807190 .delay 1 (30000,30000,30000) L_0000000002807190/d; +L_0000000002807200/d .functor NAND 1, L_0000000002797be0, L_0000000002806630, L_0000000002806c50, C4<1>; +L_0000000002807200 .delay 1 (30000,30000,30000) L_0000000002807200/d; +L_0000000002807270/d .functor NAND 1, L_0000000002807120, L_0000000002798540, L_0000000002807430, C4<1>; +L_0000000002807270 .delay 1 (30000,30000,30000) L_0000000002807270/d; +L_00000000028072e0/d .functor NAND 1, L_0000000002807120, L_0000000002806630, L_0000000002807040, C4<1>; +L_00000000028072e0 .delay 1 (30000,30000,30000) L_00000000028072e0/d; +L_0000000002807580/d .functor NAND 1, L_0000000002807190, L_0000000002807200, L_0000000002807270, L_00000000028072e0; +L_0000000002807580 .delay 1 (40000,40000,40000) L_0000000002807580/d; +v000000000276dc20_0 .net "a", 0 0, L_0000000002806400; alias, 1 drivers +v000000000276d400_0 .net "aout", 0 0, L_0000000002807190; 1 drivers +v000000000276d9a0_0 .net "b", 0 0, L_0000000002806c50; alias, 1 drivers +v000000000276d0e0_0 .net "bout", 0 0, L_0000000002807200; 1 drivers +v000000000276da40_0 .net "c", 0 0, L_0000000002807430; alias, 1 drivers +v000000000276dcc0_0 .net "cout", 0 0, L_0000000002807270; 1 drivers +v000000000276dd60_0 .net "d", 0 0, L_0000000002807040; alias, 1 drivers +v000000000276d540_0 .net "dout", 0 0, L_00000000028072e0; 1 drivers +v000000000276d4a0_0 .net "ns0", 0 0, L_0000000002806630; 1 drivers +v000000000276d5e0_0 .net "ns1", 0 0, L_0000000002807120; 1 drivers +v000000000276d7c0_0 .net "out", 0 0, L_0000000002807580; alias, 1 drivers +v000000000276d720_0 .net "s0", 0 0, L_0000000002798540; 1 drivers +v000000000276dae0_0 .net "s1", 0 0, L_0000000002797be0; 1 drivers +S_000000000276efc0 .scope generate, "aluBits[25]" "aluBits[25]" 4 49, 4 49 0, S_0000000000cc7490; + .timescale -9 -12; +P_0000000000f067a0 .param/l "i" 0 4 49, +C4<011001>; +L_0000000002807350/d .functor XOR 1, L_000000000279ab60, v0000000000e68bd0_0, C4<0>, C4<0>; +L_0000000002807350 .delay 1 (20000,20000,20000) L_0000000002807350/d; +L_000000000280a8e0/d .functor AND 1, v0000000000e67370_0, L_000000000279ba60, C4<1>, C4<1>; +L_000000000280a8e0 .delay 1 (30000,30000,30000) L_000000000280a8e0/d; +L_000000000280bd00/d .functor AND 1, L_000000000279a160, L_000000000282c280, C4<1>, C4<1>; +L_000000000280bd00 .delay 1 (30000,30000,30000) L_000000000280bd00/d; +v000000000275e4a0_0 .net *"_s1", 0 0, L_000000000279ab60; 1 drivers +v000000000275e7c0_0 .net *"_s3", 0 0, L_000000000279ba60; 1 drivers +v0000000002760340_0 .net *"_s9", 0 0, L_000000000279a160; 1 drivers +S_000000000276e240 .scope module, "_bit" "aluFullBit" 4 52, 5 6 0, S_000000000276efc0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "res" + .port_info 1 /OUTPUT 1 "carryAND" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "cin" + .port_info 5 /INPUT 1 "ctrl0" + .port_info 6 /INPUT 2 "sel" +v000000000275f260_0 .net "a", 0 0, L_000000000279a660; 1 drivers +v000000000275e400_0 .net "b", 0 0, L_000000000279c140; 1 drivers +v000000000275e680_0 .net "carryAND", 0 0, L_000000000280b8a0; 1 drivers +v000000000275fda0_0 .net "cin", 0 0, L_000000000279b240; 1 drivers +v000000000275ec20_0 .net "ctrl0", 0 0, L_000000000279c8c0; 1 drivers +v000000000275f120_0 .net "nab", 0 0, L_000000000280adb0; 1 drivers +v000000000275efe0_0 .net "orNOR", 0 0, L_000000000280acd0; 1 drivers +v000000000275e900_0 .net "res", 0 0, L_000000000280a5d0; 1 drivers +v000000000275e5e0_0 .net "sel", 1 0, v0000000000e625f0_0; alias, 1 drivers +v000000000275fa80_0 .net "sumXOR", 0 0, L_000000000280bc90; 1 drivers +L_000000000279b380 .part v0000000000e625f0_0, 1, 1; +L_000000000279c000 .part v0000000000e625f0_0, 0, 1; +S_000000000276f140 .scope module, "alu" "aluBit" 5 18, 6 14 0, S_000000000276e240; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sumXOR" + .port_info 1 /OUTPUT 1 "carryAND" + .port_info 2 /OUTPUT 1 "nab" + .port_info 3 /OUTPUT 1 "orNOR" + .port_info 4 /INPUT 1 "a" + .port_info 5 /INPUT 1 "b" + .port_info 6 /INPUT 1 "carryin" + .port_info 7 /INPUT 1 "i0" +L_000000000280adb0/d .functor NAND 1, L_000000000279a660, L_000000000279c140, C4<1>, C4<1>; +L_000000000280adb0 .delay 1 (20000,20000,20000) L_000000000280adb0/d; +L_000000000280a410/d .functor NAND 1, L_000000000279c140, L_000000000279b240, C4<1>, C4<1>; +L_000000000280a410 .delay 1 (20000,20000,20000) L_000000000280a410/d; +L_000000000280bbb0/d .functor NAND 1, L_000000000279a660, L_000000000279b240, C4<1>, C4<1>; +L_000000000280bbb0 .delay 1 (20000,20000,20000) L_000000000280bbb0/d; +L_000000000280b8a0/d .functor NAND 1, L_000000000280adb0, L_000000000280bbb0, L_000000000280a410, C4<1>; +L_000000000280b8a0 .delay 1 (30000,30000,30000) L_000000000280b8a0/d; +L_000000000280bc90/d .functor XOR 1, L_000000000279a660, L_000000000279c140, L_000000000279b240, C4<0>; +L_000000000280bc90 .delay 1 (30000,30000,30000) L_000000000280bc90/d; +L_000000000280abf0/d .functor NOR 1, L_000000000279a660, L_000000000279c140, C4<0>, C4<0>; +L_000000000280abf0 .delay 1 (20000,20000,20000) L_000000000280abf0/d; +L_000000000280acd0/d .functor XOR 1, L_000000000280abf0, L_000000000279c8c0, C4<0>, C4<0>; +L_000000000280acd0 .delay 1 (20000,20000,20000) L_000000000280acd0/d; +v000000000275fe40_0 .net "a", 0 0, L_000000000279a660; alias, 1 drivers +v000000000275eea0_0 .net "anorb", 0 0, L_000000000280abf0; 1 drivers +v000000000275eb80_0 .net "b", 0 0, L_000000000279c140; alias, 1 drivers +v0000000002760160_0 .net "carryAND", 0 0, L_000000000280b8a0; alias, 1 drivers +v00000000027602a0_0 .net "carryin", 0 0, L_000000000279b240; alias, 1 drivers +v000000000275e360_0 .net "i0", 0 0, L_000000000279c8c0; alias, 1 drivers +v000000000275e540_0 .net "nab", 0 0, L_000000000280adb0; alias, 1 drivers +v0000000002760700_0 .net "nac", 0 0, L_000000000280bbb0; 1 drivers +v00000000027607a0_0 .net "nbc", 0 0, L_000000000280a410; 1 drivers +v000000000275ed60_0 .net "orNOR", 0 0, L_000000000280acd0; alias, 1 drivers +v000000000275fc60_0 .net "sumXOR", 0 0, L_000000000280bc90; alias, 1 drivers +S_000000000276f2c0 .scope module, "mux" "multiplexer" 5 20, 7 7 0, S_000000000276e240; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "a" + .port_info 2 /INPUT 1 "b" + .port_info 3 /INPUT 1 "c" + .port_info 4 /INPUT 1 "d" + .port_info 5 /INPUT 1 "s1" + .port_info 6 /INPUT 1 "s0" +L_000000000280b130/d .functor NOT 1, L_000000000279c000, C4<0>, C4<0>, C4<0>; +L_000000000280b130 .delay 1 (10000,10000,10000) L_000000000280b130/d; +L_000000000280ae20/d .functor NOT 1, L_000000000279b380, C4<0>, C4<0>, C4<0>; +L_000000000280ae20 .delay 1 (10000,10000,10000) L_000000000280ae20/d; +L_000000000280b980/d .functor NAND 1, L_000000000279b380, L_000000000279c000, L_000000000280bc90, C4<1>; +L_000000000280b980 .delay 1 (30000,30000,30000) L_000000000280b980/d; +L_000000000280b750/d .functor NAND 1, L_000000000279b380, L_000000000280b130, L_000000000280acd0, C4<1>; +L_000000000280b750 .delay 1 (30000,30000,30000) L_000000000280b750/d; +L_000000000280a250/d .functor NAND 1, L_000000000280ae20, L_000000000279c000, L_000000000280b8a0, C4<1>; +L_000000000280a250 .delay 1 (30000,30000,30000) L_000000000280a250/d; +L_000000000280ad40/d .functor NAND 1, L_000000000280ae20, L_000000000280b130, L_000000000280adb0, C4<1>; +L_000000000280ad40 .delay 1 (30000,30000,30000) L_000000000280ad40/d; +L_000000000280a5d0/d .functor NAND 1, L_000000000280b980, L_000000000280b750, L_000000000280a250, L_000000000280ad40; +L_000000000280a5d0 .delay 1 (40000,40000,40000) L_000000000280a5d0/d; +v000000000275f760_0 .net "a", 0 0, L_000000000280bc90; alias, 1 drivers +v0000000002760840_0 .net "aout", 0 0, L_000000000280b980; 1 drivers +v000000000275e720_0 .net "b", 0 0, L_000000000280acd0; alias, 1 drivers +v000000000275f1c0_0 .net "bout", 0 0, L_000000000280b750; 1 drivers +v000000000275fee0_0 .net "c", 0 0, L_000000000280b8a0; alias, 1 drivers +v000000000275e0e0_0 .net "cout", 0 0, L_000000000280a250; 1 drivers +v000000000275e220_0 .net "d", 0 0, L_000000000280adb0; alias, 1 drivers +v000000000275ee00_0 .net "dout", 0 0, L_000000000280ad40; 1 drivers +v000000000275f080_0 .net "ns0", 0 0, L_000000000280b130; 1 drivers +v000000000275fd00_0 .net "ns1", 0 0, L_000000000280ae20; 1 drivers +v000000000275e9a0_0 .net "out", 0 0, L_000000000280a5d0; alias, 1 drivers +v000000000275e2c0_0 .net "s0", 0 0, L_000000000279c000; 1 drivers +v000000000275f8a0_0 .net "s1", 0 0, L_000000000279b380; 1 drivers +S_0000000002772260 .scope generate, "aluBits[26]" "aluBits[26]" 4 49, 4 49 0, S_0000000000cc7490; + .timescale -9 -12; +P_0000000000f06e20 .param/l "i" 0 4 49, +C4<011010>; +L_000000000280b520/d .functor XOR 1, L_000000000279bb00, v0000000000e68bd0_0, C4<0>, C4<0>; +L_000000000280b520 .delay 1 (20000,20000,20000) L_000000000280b520/d; +L_000000000280a2c0/d .functor AND 1, v0000000000e67370_0, L_000000000279b060, C4<1>, C4<1>; +L_000000000280a2c0 .delay 1 (30000,30000,30000) L_000000000280a2c0/d; +L_000000000280bd70/d .functor AND 1, L_000000000279ade0, L_000000000282c280, C4<1>, C4<1>; +L_000000000280bd70 .delay 1 (30000,30000,30000) L_000000000280bd70/d; +v0000000002779800_0 .net *"_s1", 0 0, L_000000000279bb00; 1 drivers +v000000000277b7e0_0 .net *"_s3", 0 0, L_000000000279b060; 1 drivers +v000000000277a3e0_0 .net *"_s9", 0 0, L_000000000279ade0; 1 drivers +S_0000000002772e60 .scope module, "_bit" "aluFullBit" 4 52, 5 6 0, S_0000000002772260; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "res" + .port_info 1 /OUTPUT 1 "carryAND" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "cin" + .port_info 5 /INPUT 1 "ctrl0" + .port_info 6 /INPUT 2 "sel" +v0000000002779940_0 .net "a", 0 0, L_000000000279a5c0; 1 drivers +v000000000277a0c0_0 .net "b", 0 0, L_000000000279c320; 1 drivers +v0000000002779e40_0 .net "carryAND", 0 0, L_000000000280ae90; 1 drivers +v0000000002779ee0_0 .net "cin", 0 0, L_000000000279c780; 1 drivers +v0000000002779c60_0 .net "ctrl0", 0 0, L_000000000279a840; 1 drivers +v000000000277b240_0 .net "nab", 0 0, L_000000000280a330; 1 drivers +v000000000277b560_0 .net "orNOR", 0 0, L_000000000280a870; 1 drivers +v0000000002779f80_0 .net "res", 0 0, L_000000000280b670; 1 drivers +v000000000277a160_0 .net "sel", 1 0, v0000000000e625f0_0; alias, 1 drivers +v0000000002779440_0 .net "sumXOR", 0 0, L_000000000280a800; 1 drivers +L_000000000279b560 .part v0000000000e625f0_0, 1, 1; +L_000000000279a340 .part v0000000000e625f0_0, 0, 1; +S_0000000002773be0 .scope module, "alu" "aluBit" 5 18, 6 14 0, S_0000000002772e60; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sumXOR" + .port_info 1 /OUTPUT 1 "carryAND" + .port_info 2 /OUTPUT 1 "nab" + .port_info 3 /OUTPUT 1 "orNOR" + .port_info 4 /INPUT 1 "a" + .port_info 5 /INPUT 1 "b" + .port_info 6 /INPUT 1 "carryin" + .port_info 7 /INPUT 1 "i0" +L_000000000280a330/d .functor NAND 1, L_000000000279a5c0, L_000000000279c320, C4<1>, C4<1>; +L_000000000280a330 .delay 1 (20000,20000,20000) L_000000000280a330/d; +L_000000000280a790/d .functor NAND 1, L_000000000279c320, L_000000000279c780, C4<1>, C4<1>; +L_000000000280a790 .delay 1 (20000,20000,20000) L_000000000280a790/d; +L_000000000280af70/d .functor NAND 1, L_000000000279a5c0, L_000000000279c780, C4<1>, C4<1>; +L_000000000280af70 .delay 1 (20000,20000,20000) L_000000000280af70/d; +L_000000000280ae90/d .functor NAND 1, L_000000000280a330, L_000000000280af70, L_000000000280a790, C4<1>; +L_000000000280ae90 .delay 1 (30000,30000,30000) L_000000000280ae90/d; +L_000000000280a800/d .functor XOR 1, L_000000000279a5c0, L_000000000279c320, L_000000000279c780, C4<0>; +L_000000000280a800 .delay 1 (30000,30000,30000) L_000000000280a800/d; +L_000000000280af00/d .functor NOR 1, L_000000000279a5c0, L_000000000279c320, C4<0>, C4<0>; +L_000000000280af00 .delay 1 (20000,20000,20000) L_000000000280af00/d; +L_000000000280a870/d .functor XOR 1, L_000000000280af00, L_000000000279a840, C4<0>, C4<0>; +L_000000000280a870 .delay 1 (20000,20000,20000) L_000000000280a870/d; +v000000000275e860_0 .net "a", 0 0, L_000000000279a5c0; alias, 1 drivers +v000000000275ecc0_0 .net "anorb", 0 0, L_000000000280af00; 1 drivers +v0000000002760520_0 .net "b", 0 0, L_000000000279c320; alias, 1 drivers +v0000000002760480_0 .net "carryAND", 0 0, L_000000000280ae90; alias, 1 drivers +v000000000275ef40_0 .net "carryin", 0 0, L_000000000279c780; alias, 1 drivers +v000000000275f300_0 .net "i0", 0 0, L_000000000279a840; alias, 1 drivers +v000000000275f440_0 .net "nab", 0 0, L_000000000280a330; alias, 1 drivers +v000000000275f800_0 .net "nac", 0 0, L_000000000280af70; 1 drivers +v000000000275f9e0_0 .net "nbc", 0 0, L_000000000280a790; 1 drivers +v0000000002760200_0 .net "orNOR", 0 0, L_000000000280a870; alias, 1 drivers +v000000000275f4e0_0 .net "sumXOR", 0 0, L_000000000280a800; alias, 1 drivers +S_0000000002773460 .scope module, "mux" "multiplexer" 5 20, 7 7 0, S_0000000002772e60; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "a" + .port_info 2 /INPUT 1 "b" + .port_info 3 /INPUT 1 "c" + .port_info 4 /INPUT 1 "d" + .port_info 5 /INPUT 1 "s1" + .port_info 6 /INPUT 1 "s0" +L_000000000280bc20/d .functor NOT 1, L_000000000279a340, C4<0>, C4<0>, C4<0>; +L_000000000280bc20 .delay 1 (10000,10000,10000) L_000000000280bc20/d; +L_000000000280b440/d .functor NOT 1, L_000000000279b560, C4<0>, C4<0>, C4<0>; +L_000000000280b440 .delay 1 (10000,10000,10000) L_000000000280b440/d; +L_000000000280ac60/d .functor NAND 1, L_000000000279b560, L_000000000279a340, L_000000000280a800, C4<1>; +L_000000000280ac60 .delay 1 (30000,30000,30000) L_000000000280ac60/d; +L_000000000280b590/d .functor NAND 1, L_000000000279b560, L_000000000280bc20, L_000000000280a870, C4<1>; +L_000000000280b590 .delay 1 (30000,30000,30000) L_000000000280b590/d; +L_000000000280a6b0/d .functor NAND 1, L_000000000280b440, L_000000000279a340, L_000000000280ae90, C4<1>; +L_000000000280a6b0 .delay 1 (30000,30000,30000) L_000000000280a6b0/d; +L_000000000280b600/d .functor NAND 1, L_000000000280b440, L_000000000280bc20, L_000000000280a330, C4<1>; +L_000000000280b600 .delay 1 (30000,30000,30000) L_000000000280b600/d; +L_000000000280b670/d .functor NAND 1, L_000000000280ac60, L_000000000280b590, L_000000000280a6b0, L_000000000280b600; +L_000000000280b670 .delay 1 (40000,40000,40000) L_000000000280b670/d; +v00000000027605c0_0 .net "a", 0 0, L_000000000280a800; alias, 1 drivers +v000000000275ff80_0 .net "aout", 0 0, L_000000000280ac60; 1 drivers +v0000000002760660_0 .net "b", 0 0, L_000000000280a870; alias, 1 drivers +v0000000002760020_0 .net "bout", 0 0, L_000000000280b590; 1 drivers +v000000000275f580_0 .net "c", 0 0, L_000000000280ae90; alias, 1 drivers +v000000000275f620_0 .net "cout", 0 0, L_000000000280a6b0; 1 drivers +v000000000275f6c0_0 .net "d", 0 0, L_000000000280a330; alias, 1 drivers +v000000000275f940_0 .net "dout", 0 0, L_000000000280b600; 1 drivers +v00000000027603e0_0 .net "ns0", 0 0, L_000000000280bc20; 1 drivers +v000000000275fb20_0 .net "ns1", 0 0, L_000000000280b440; 1 drivers +v00000000027600c0_0 .net "out", 0 0, L_000000000280b670; alias, 1 drivers +v000000000277a200_0 .net "s0", 0 0, L_000000000279a340; 1 drivers +v000000000277ade0_0 .net "s1", 0 0, L_000000000279b560; 1 drivers +S_00000000027723e0 .scope generate, "aluBits[27]" "aluBits[27]" 4 49, 4 49 0, S_0000000000cc7490; + .timescale -9 -12; +P_0000000000f05ee0 .param/l "i" 0 4 49, +C4<011011>; +L_000000000280a720/d .functor XOR 1, L_000000000279bc40, v0000000000e68bd0_0, C4<0>, C4<0>; +L_000000000280a720 .delay 1 (20000,20000,20000) L_000000000280a720/d; +L_000000000280a480/d .functor AND 1, v0000000000e67370_0, L_000000000279bce0, C4<1>, C4<1>; +L_000000000280a480 .delay 1 (30000,30000,30000) L_000000000280a480/d; +L_000000000280b210/d .functor AND 1, L_000000000279c280, L_000000000282c280, C4<1>, C4<1>; +L_000000000280b210 .delay 1 (30000,30000,30000) L_000000000280b210/d; +v000000000277aa20_0 .net *"_s1", 0 0, L_000000000279bc40; 1 drivers +v000000000277b600_0 .net *"_s3", 0 0, L_000000000279bce0; 1 drivers +v0000000002779a80_0 .net *"_s9", 0 0, L_000000000279c280; 1 drivers +S_0000000002772860 .scope module, "_bit" "aluFullBit" 4 52, 5 6 0, S_00000000027723e0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "res" + .port_info 1 /OUTPUT 1 "carryAND" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "cin" + .port_info 5 /INPUT 1 "ctrl0" + .port_info 6 /INPUT 2 "sel" +v000000000277b740_0 .net "a", 0 0, L_000000000279a520; 1 drivers +v0000000002779760_0 .net "b", 0 0, L_000000000279a8e0; 1 drivers +v000000000277a660_0 .net "carryAND", 0 0, L_000000000280b050; 1 drivers +v000000000277b1a0_0 .net "cin", 0 0, L_000000000279a980; 1 drivers +v000000000277a8e0_0 .net "ctrl0", 0 0, L_000000000279b420; 1 drivers +v000000000277a980_0 .net "nab", 0 0, L_000000000280afe0; 1 drivers +v0000000002779b20_0 .net "orNOR", 0 0, L_000000000280a9c0; 1 drivers +v0000000002779120_0 .net "res", 0 0, L_000000000280b7c0; 1 drivers +v000000000277a700_0 .net "sel", 1 0, v0000000000e625f0_0; alias, 1 drivers +v000000000277b100_0 .net "sumXOR", 0 0, L_000000000280b0c0; 1 drivers +L_000000000279c1e0 .part v0000000000e625f0_0, 1, 1; +L_000000000279b880 .part v0000000000e625f0_0, 0, 1; +S_0000000002772b60 .scope module, "alu" "aluBit" 5 18, 6 14 0, S_0000000002772860; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sumXOR" + .port_info 1 /OUTPUT 1 "carryAND" + .port_info 2 /OUTPUT 1 "nab" + .port_info 3 /OUTPUT 1 "orNOR" + .port_info 4 /INPUT 1 "a" + .port_info 5 /INPUT 1 "b" + .port_info 6 /INPUT 1 "carryin" + .port_info 7 /INPUT 1 "i0" +L_000000000280afe0/d .functor NAND 1, L_000000000279a520, L_000000000279a8e0, C4<1>, C4<1>; +L_000000000280afe0 .delay 1 (20000,20000,20000) L_000000000280afe0/d; +L_000000000280b9f0/d .functor NAND 1, L_000000000279a8e0, L_000000000279a980, C4<1>, C4<1>; +L_000000000280b9f0 .delay 1 (20000,20000,20000) L_000000000280b9f0/d; +L_000000000280a950/d .functor NAND 1, L_000000000279a520, L_000000000279a980, C4<1>, C4<1>; +L_000000000280a950 .delay 1 (20000,20000,20000) L_000000000280a950/d; +L_000000000280b050/d .functor NAND 1, L_000000000280afe0, L_000000000280a950, L_000000000280b9f0, C4<1>; +L_000000000280b050 .delay 1 (30000,30000,30000) L_000000000280b050/d; +L_000000000280b0c0/d .functor XOR 1, L_000000000279a520, L_000000000279a8e0, L_000000000279a980, C4<0>; +L_000000000280b0c0 .delay 1 (30000,30000,30000) L_000000000280b0c0/d; +L_000000000280b1a0/d .functor NOR 1, L_000000000279a520, L_000000000279a8e0, C4<0>, C4<0>; +L_000000000280b1a0 .delay 1 (20000,20000,20000) L_000000000280b1a0/d; +L_000000000280a9c0/d .functor XOR 1, L_000000000280b1a0, L_000000000279b420, C4<0>, C4<0>; +L_000000000280a9c0 .delay 1 (20000,20000,20000) L_000000000280a9c0/d; +v000000000277afc0_0 .net "a", 0 0, L_000000000279a520; alias, 1 drivers +v000000000277a020_0 .net "anorb", 0 0, L_000000000280b1a0; 1 drivers +v00000000027794e0_0 .net "b", 0 0, L_000000000279a8e0; alias, 1 drivers +v000000000277b4c0_0 .net "carryAND", 0 0, L_000000000280b050; alias, 1 drivers +v000000000277b880_0 .net "carryin", 0 0, L_000000000279a980; alias, 1 drivers +v000000000277ac00_0 .net "i0", 0 0, L_000000000279b420; alias, 1 drivers +v000000000277a2a0_0 .net "nab", 0 0, L_000000000280afe0; alias, 1 drivers +v000000000277af20_0 .net "nac", 0 0, L_000000000280a950; 1 drivers +v00000000027798a0_0 .net "nbc", 0 0, L_000000000280b9f0; 1 drivers +v0000000002779260_0 .net "orNOR", 0 0, L_000000000280a9c0; alias, 1 drivers +v000000000277a340_0 .net "sumXOR", 0 0, L_000000000280b0c0; alias, 1 drivers +S_00000000027732e0 .scope module, "mux" "multiplexer" 5 20, 7 7 0, S_0000000002772860; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "a" + .port_info 2 /INPUT 1 "b" + .port_info 3 /INPUT 1 "c" + .port_info 4 /INPUT 1 "d" + .port_info 5 /INPUT 1 "s1" + .port_info 6 /INPUT 1 "s0" +L_000000000280b6e0/d .functor NOT 1, L_000000000279b880, C4<0>, C4<0>, C4<0>; +L_000000000280b6e0 .delay 1 (10000,10000,10000) L_000000000280b6e0/d; +L_000000000280a1e0/d .functor NOT 1, L_000000000279c1e0, C4<0>, C4<0>, C4<0>; +L_000000000280a1e0 .delay 1 (10000,10000,10000) L_000000000280a1e0/d; +L_000000000280a3a0/d .functor NAND 1, L_000000000279c1e0, L_000000000279b880, L_000000000280b0c0, C4<1>; +L_000000000280a3a0 .delay 1 (30000,30000,30000) L_000000000280a3a0/d; +L_000000000280b3d0/d .functor NAND 1, L_000000000279c1e0, L_000000000280b6e0, L_000000000280a9c0, C4<1>; +L_000000000280b3d0 .delay 1 (30000,30000,30000) L_000000000280b3d0/d; +L_000000000280a640/d .functor NAND 1, L_000000000280a1e0, L_000000000279b880, L_000000000280b050, C4<1>; +L_000000000280a640 .delay 1 (30000,30000,30000) L_000000000280a640/d; +L_000000000280b830/d .functor NAND 1, L_000000000280a1e0, L_000000000280b6e0, L_000000000280afe0, C4<1>; +L_000000000280b830 .delay 1 (30000,30000,30000) L_000000000280b830/d; +L_000000000280b7c0/d .functor NAND 1, L_000000000280a3a0, L_000000000280b3d0, L_000000000280a640, L_000000000280b830; +L_000000000280b7c0 .delay 1 (40000,40000,40000) L_000000000280b7c0/d; +v0000000002779da0_0 .net "a", 0 0, L_000000000280b0c0; alias, 1 drivers +v000000000277a840_0 .net "aout", 0 0, L_000000000280a3a0; 1 drivers +v0000000002779300_0 .net "b", 0 0, L_000000000280a9c0; alias, 1 drivers +v000000000277a480_0 .net "bout", 0 0, L_000000000280b3d0; 1 drivers +v00000000027796c0_0 .net "c", 0 0, L_000000000280b050; alias, 1 drivers +v000000000277ad40_0 .net "cout", 0 0, L_000000000280a640; 1 drivers +v0000000002779d00_0 .net "d", 0 0, L_000000000280afe0; alias, 1 drivers +v0000000002779580_0 .net "dout", 0 0, L_000000000280b830; 1 drivers +v000000000277b060_0 .net "ns0", 0 0, L_000000000280b6e0; 1 drivers +v00000000027799e0_0 .net "ns1", 0 0, L_000000000280a1e0; 1 drivers +v0000000002779620_0 .net "out", 0 0, L_000000000280b7c0; alias, 1 drivers +v000000000277a520_0 .net "s0", 0 0, L_000000000279b880; 1 drivers +v000000000277a5c0_0 .net "s1", 0 0, L_000000000279c1e0; 1 drivers +S_0000000002772560 .scope generate, "aluBits[28]" "aluBits[28]" 4 49, 4 49 0, S_0000000000cc7490; + .timescale -9 -12; +P_0000000000f069e0 .param/l "i" 0 4 49, +C4<011100>; +L_000000000280a4f0/d .functor XOR 1, L_000000000279a700, v0000000000e68bd0_0, C4<0>, C4<0>; +L_000000000280a4f0 .delay 1 (20000,20000,20000) L_000000000280a4f0/d; +L_000000000280aa30/d .functor AND 1, v0000000000e67370_0, L_000000000279c460, C4<1>, C4<1>; +L_000000000280aa30 .delay 1 (30000,30000,30000) L_000000000280aa30/d; +L_000000000280cb00/d .functor AND 1, L_000000000279a2a0, L_000000000282c280, C4<1>, C4<1>; +L_000000000280cb00 .delay 1 (30000,30000,30000) L_000000000280cb00/d; +v000000000277d7c0_0 .net *"_s1", 0 0, L_000000000279a700; 1 drivers +v000000000277d400_0 .net *"_s3", 0 0, L_000000000279c460; 1 drivers +v000000000277cf00_0 .net *"_s9", 0 0, L_000000000279a2a0; 1 drivers +S_0000000002772ce0 .scope module, "_bit" "aluFullBit" 4 52, 5 6 0, S_0000000002772560; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "res" + .port_info 1 /OUTPUT 1 "carryAND" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "cin" + .port_info 5 /INPUT 1 "ctrl0" + .port_info 6 /INPUT 2 "sel" +v000000000277bc40_0 .net "a", 0 0, L_000000000279b4c0; 1 drivers +v000000000277c000_0 .net "b", 0 0, L_000000000279a200; 1 drivers +v000000000277d720_0 .net "carryAND", 0 0, L_000000000280ab80; 1 drivers +v000000000277cd20_0 .net "cin", 0 0, L_000000000279b6a0; 1 drivers +v000000000277cdc0_0 .net "ctrl0", 0 0, L_000000000279b1a0; 1 drivers +v000000000277b920_0 .net "nab", 0 0, L_000000000280b910; 1 drivers +v000000000277dae0_0 .net "orNOR", 0 0, L_000000000280b280; 1 drivers +v000000000277c0a0_0 .net "res", 0 0, L_000000000280c710; 1 drivers +v000000000277db80_0 .net "sel", 1 0, v0000000000e625f0_0; alias, 1 drivers +v000000000277c3c0_0 .net "sumXOR", 0 0, L_000000000280b360; 1 drivers +L_000000000279ae80 .part v0000000000e625f0_0, 1, 1; +L_000000000279b100 .part v0000000000e625f0_0, 0, 1; +S_00000000027726e0 .scope module, "alu" "aluBit" 5 18, 6 14 0, S_0000000002772ce0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sumXOR" + .port_info 1 /OUTPUT 1 "carryAND" + .port_info 2 /OUTPUT 1 "nab" + .port_info 3 /OUTPUT 1 "orNOR" + .port_info 4 /INPUT 1 "a" + .port_info 5 /INPUT 1 "b" + .port_info 6 /INPUT 1 "carryin" + .port_info 7 /INPUT 1 "i0" +L_000000000280b910/d .functor NAND 1, L_000000000279b4c0, L_000000000279a200, C4<1>, C4<1>; +L_000000000280b910 .delay 1 (20000,20000,20000) L_000000000280b910/d; +L_000000000280aaa0/d .functor NAND 1, L_000000000279a200, L_000000000279b6a0, C4<1>, C4<1>; +L_000000000280aaa0 .delay 1 (20000,20000,20000) L_000000000280aaa0/d; +L_000000000280ab10/d .functor NAND 1, L_000000000279b4c0, L_000000000279b6a0, C4<1>, C4<1>; +L_000000000280ab10 .delay 1 (20000,20000,20000) L_000000000280ab10/d; +L_000000000280ab80/d .functor NAND 1, L_000000000280b910, L_000000000280ab10, L_000000000280aaa0, C4<1>; +L_000000000280ab80 .delay 1 (30000,30000,30000) L_000000000280ab80/d; +L_000000000280b360/d .functor XOR 1, L_000000000279b4c0, L_000000000279a200, L_000000000279b6a0, C4<0>; +L_000000000280b360 .delay 1 (30000,30000,30000) L_000000000280b360/d; +L_000000000280ba60/d .functor NOR 1, L_000000000279b4c0, L_000000000279a200, C4<0>, C4<0>; +L_000000000280ba60 .delay 1 (20000,20000,20000) L_000000000280ba60/d; +L_000000000280b280/d .functor XOR 1, L_000000000280ba60, L_000000000279b1a0, C4<0>, C4<0>; +L_000000000280b280 .delay 1 (20000,20000,20000) L_000000000280b280/d; +v000000000277a7a0_0 .net "a", 0 0, L_000000000279b4c0; alias, 1 drivers +v000000000277b2e0_0 .net "anorb", 0 0, L_000000000280ba60; 1 drivers +v000000000277aac0_0 .net "b", 0 0, L_000000000279a200; alias, 1 drivers +v000000000277b6a0_0 .net "carryAND", 0 0, L_000000000280ab80; alias, 1 drivers +v00000000027791c0_0 .net "carryin", 0 0, L_000000000279b6a0; alias, 1 drivers +v0000000002779bc0_0 .net "i0", 0 0, L_000000000279b1a0; alias, 1 drivers +v000000000277aca0_0 .net "nab", 0 0, L_000000000280b910; alias, 1 drivers +v000000000277ae80_0 .net "nac", 0 0, L_000000000280ab10; 1 drivers +v000000000277ab60_0 .net "nbc", 0 0, L_000000000280aaa0; 1 drivers +v00000000027793a0_0 .net "orNOR", 0 0, L_000000000280b280; alias, 1 drivers +v000000000277b380_0 .net "sumXOR", 0 0, L_000000000280b360; alias, 1 drivers +S_00000000027729e0 .scope module, "mux" "multiplexer" 5 20, 7 7 0, S_0000000002772ce0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "a" + .port_info 2 /INPUT 1 "b" + .port_info 3 /INPUT 1 "c" + .port_info 4 /INPUT 1 "d" + .port_info 5 /INPUT 1 "s1" + .port_info 6 /INPUT 1 "s0" +L_000000000280a560/d .functor NOT 1, L_000000000279b100, C4<0>, C4<0>, C4<0>; +L_000000000280a560 .delay 1 (10000,10000,10000) L_000000000280a560/d; +L_000000000280b2f0/d .functor NOT 1, L_000000000279ae80, C4<0>, C4<0>, C4<0>; +L_000000000280b2f0 .delay 1 (10000,10000,10000) L_000000000280b2f0/d; +L_000000000280b4b0/d .functor NAND 1, L_000000000279ae80, L_000000000279b100, L_000000000280b360, C4<1>; +L_000000000280b4b0 .delay 1 (30000,30000,30000) L_000000000280b4b0/d; +L_000000000280bad0/d .functor NAND 1, L_000000000279ae80, L_000000000280a560, L_000000000280b280, C4<1>; +L_000000000280bad0 .delay 1 (30000,30000,30000) L_000000000280bad0/d; +L_000000000280bb40/d .functor NAND 1, L_000000000280b2f0, L_000000000279b100, L_000000000280ab80, C4<1>; +L_000000000280bb40 .delay 1 (30000,30000,30000) L_000000000280bb40/d; +L_000000000280cb70/d .functor NAND 1, L_000000000280b2f0, L_000000000280a560, L_000000000280b910, C4<1>; +L_000000000280cb70 .delay 1 (30000,30000,30000) L_000000000280cb70/d; +L_000000000280c710/d .functor NAND 1, L_000000000280b4b0, L_000000000280bad0, L_000000000280bb40, L_000000000280cb70; +L_000000000280c710 .delay 1 (40000,40000,40000) L_000000000280c710/d; +v000000000277b420_0 .net "a", 0 0, L_000000000280b360; alias, 1 drivers +v000000000277d860_0 .net "aout", 0 0, L_000000000280b4b0; 1 drivers +v000000000277cbe0_0 .net "b", 0 0, L_000000000280b280; alias, 1 drivers +v000000000277c140_0 .net "bout", 0 0, L_000000000280bad0; 1 drivers +v000000000277c1e0_0 .net "c", 0 0, L_000000000280ab80; alias, 1 drivers +v000000000277c280_0 .net "cout", 0 0, L_000000000280bb40; 1 drivers +v000000000277cc80_0 .net "d", 0 0, L_000000000280b910; alias, 1 drivers +v000000000277c6e0_0 .net "dout", 0 0, L_000000000280cb70; 1 drivers +v000000000277c460_0 .net "ns0", 0 0, L_000000000280a560; 1 drivers +v000000000277da40_0 .net "ns1", 0 0, L_000000000280b2f0; 1 drivers +v000000000277dd60_0 .net "out", 0 0, L_000000000280c710; alias, 1 drivers +v000000000277c780_0 .net "s0", 0 0, L_000000000279b100; 1 drivers +v000000000277c8c0_0 .net "s1", 0 0, L_000000000279ae80; 1 drivers +S_0000000002772fe0 .scope generate, "aluBits[29]" "aluBits[29]" 4 49, 4 49 0, S_0000000000cc7490; + .timescale -9 -12; +P_0000000000f06a20 .param/l "i" 0 4 49, +C4<011101>; +L_000000000280c2b0/d .functor XOR 1, L_000000000279ac00, v0000000000e68bd0_0, C4<0>, C4<0>; +L_000000000280c2b0 .delay 1 (20000,20000,20000) L_000000000280c2b0/d; +L_000000000280c160/d .functor AND 1, v0000000000e67370_0, L_000000000279af20, C4<1>, C4<1>; +L_000000000280c160 .delay 1 (30000,30000,30000) L_000000000280c160/d; +L_000000000280bf30/d .functor AND 1, L_000000000279a480, L_000000000282c280, C4<1>, C4<1>; +L_000000000280bf30 .delay 1 (30000,30000,30000) L_000000000280bf30/d; +v000000000277bb00_0 .net *"_s1", 0 0, L_000000000279ac00; 1 drivers +v000000000277bba0_0 .net *"_s3", 0 0, L_000000000279af20; 1 drivers +v000000000277bce0_0 .net *"_s9", 0 0, L_000000000279a480; 1 drivers +S_0000000002773160 .scope module, "_bit" "aluFullBit" 4 52, 5 6 0, S_0000000002772fe0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "res" + .port_info 1 /OUTPUT 1 "carryAND" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "cin" + .port_info 5 /INPUT 1 "ctrl0" + .port_info 6 /INPUT 2 "sel" +v000000000277d5e0_0 .net "a", 0 0, L_000000000279c500; 1 drivers +v000000000277d680_0 .net "b", 0 0, L_000000000279b2e0; 1 drivers +v000000000277e080_0 .net "carryAND", 0 0, L_000000000280c550; 1 drivers +v000000000277bd80_0 .net "cin", 0 0, L_000000000279b600; 1 drivers +v000000000277c640_0 .net "ctrl0", 0 0, L_000000000279c0a0; 1 drivers +v000000000277dea0_0 .net "nab", 0 0, L_000000000280c1d0; 1 drivers +v000000000277cfa0_0 .net "orNOR", 0 0, L_000000000280cef0; 1 drivers +v000000000277be20_0 .net "res", 0 0, L_000000000280cfd0; 1 drivers +v000000000277b9c0_0 .net "sel", 1 0, v0000000000e625f0_0; alias, 1 drivers +v000000000277cb40_0 .net "sumXOR", 0 0, L_000000000280c860; 1 drivers +L_000000000279ad40 .part v0000000000e625f0_0, 1, 1; +L_000000000279aa20 .part v0000000000e625f0_0, 0, 1; +S_00000000027735e0 .scope module, "alu" "aluBit" 5 18, 6 14 0, S_0000000002773160; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sumXOR" + .port_info 1 /OUTPUT 1 "carryAND" + .port_info 2 /OUTPUT 1 "nab" + .port_info 3 /OUTPUT 1 "orNOR" + .port_info 4 /INPUT 1 "a" + .port_info 5 /INPUT 1 "b" + .port_info 6 /INPUT 1 "carryin" + .port_info 7 /INPUT 1 "i0" +L_000000000280c1d0/d .functor NAND 1, L_000000000279c500, L_000000000279b2e0, C4<1>, C4<1>; +L_000000000280c1d0 .delay 1 (20000,20000,20000) L_000000000280c1d0/d; +L_000000000280c240/d .functor NAND 1, L_000000000279b2e0, L_000000000279b600, C4<1>, C4<1>; +L_000000000280c240 .delay 1 (20000,20000,20000) L_000000000280c240/d; +L_000000000280cf60/d .functor NAND 1, L_000000000279c500, L_000000000279b600, C4<1>, C4<1>; +L_000000000280cf60 .delay 1 (20000,20000,20000) L_000000000280cf60/d; +L_000000000280c550/d .functor NAND 1, L_000000000280c1d0, L_000000000280cf60, L_000000000280c240, C4<1>; +L_000000000280c550 .delay 1 (30000,30000,30000) L_000000000280c550/d; +L_000000000280c860/d .functor XOR 1, L_000000000279c500, L_000000000279b2e0, L_000000000279b600, C4<0>; +L_000000000280c860 .delay 1 (30000,30000,30000) L_000000000280c860/d; +L_000000000280bec0/d .functor NOR 1, L_000000000279c500, L_000000000279b2e0, C4<0>, C4<0>; +L_000000000280bec0 .delay 1 (20000,20000,20000) L_000000000280bec0/d; +L_000000000280cef0/d .functor XOR 1, L_000000000280bec0, L_000000000279c0a0, C4<0>, C4<0>; +L_000000000280cef0 .delay 1 (20000,20000,20000) L_000000000280cef0/d; +v000000000277d4a0_0 .net "a", 0 0, L_000000000279c500; alias, 1 drivers +v000000000277c320_0 .net "anorb", 0 0, L_000000000280bec0; 1 drivers +v000000000277d0e0_0 .net "b", 0 0, L_000000000279b2e0; alias, 1 drivers +v000000000277ca00_0 .net "carryAND", 0 0, L_000000000280c550; alias, 1 drivers +v000000000277c5a0_0 .net "carryin", 0 0, L_000000000279b600; alias, 1 drivers +v000000000277d040_0 .net "i0", 0 0, L_000000000279c0a0; alias, 1 drivers +v000000000277caa0_0 .net "nab", 0 0, L_000000000280c1d0; alias, 1 drivers +v000000000277dc20_0 .net "nac", 0 0, L_000000000280cf60; 1 drivers +v000000000277c820_0 .net "nbc", 0 0, L_000000000280c240; 1 drivers +v000000000277ba60_0 .net "orNOR", 0 0, L_000000000280cef0; alias, 1 drivers +v000000000277d540_0 .net "sumXOR", 0 0, L_000000000280c860; alias, 1 drivers +S_0000000002773760 .scope module, "mux" "multiplexer" 5 20, 7 7 0, S_0000000002773160; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "a" + .port_info 2 /INPUT 1 "b" + .port_info 3 /INPUT 1 "c" + .port_info 4 /INPUT 1 "d" + .port_info 5 /INPUT 1 "s1" + .port_info 6 /INPUT 1 "s0" +L_000000000280d200/d .functor NOT 1, L_000000000279aa20, C4<0>, C4<0>, C4<0>; +L_000000000280d200 .delay 1 (10000,10000,10000) L_000000000280d200/d; +L_000000000280c080/d .functor NOT 1, L_000000000279ad40, C4<0>, C4<0>, C4<0>; +L_000000000280c080 .delay 1 (10000,10000,10000) L_000000000280c080/d; +L_000000000280d5f0/d .functor NAND 1, L_000000000279ad40, L_000000000279aa20, L_000000000280c860, C4<1>; +L_000000000280d5f0 .delay 1 (30000,30000,30000) L_000000000280d5f0/d; +L_000000000280d740/d .functor NAND 1, L_000000000279ad40, L_000000000280d200, L_000000000280cef0, C4<1>; +L_000000000280d740 .delay 1 (30000,30000,30000) L_000000000280d740/d; +L_000000000280c320/d .functor NAND 1, L_000000000280c080, L_000000000279aa20, L_000000000280c550, C4<1>; +L_000000000280c320 .delay 1 (30000,30000,30000) L_000000000280c320/d; +L_000000000280d040/d .functor NAND 1, L_000000000280c080, L_000000000280d200, L_000000000280c1d0, C4<1>; +L_000000000280d040 .delay 1 (30000,30000,30000) L_000000000280d040/d; +L_000000000280cfd0/d .functor NAND 1, L_000000000280d5f0, L_000000000280d740, L_000000000280c320, L_000000000280d040; +L_000000000280cfd0 .delay 1 (40000,40000,40000) L_000000000280cfd0/d; +v000000000277d2c0_0 .net "a", 0 0, L_000000000280c860; alias, 1 drivers +v000000000277c960_0 .net "aout", 0 0, L_000000000280d5f0; 1 drivers +v000000000277d900_0 .net "b", 0 0, L_000000000280cef0; alias, 1 drivers +v000000000277df40_0 .net "bout", 0 0, L_000000000280d740; 1 drivers +v000000000277dcc0_0 .net "c", 0 0, L_000000000280c550; alias, 1 drivers +v000000000277d360_0 .net "cout", 0 0, L_000000000280c320; 1 drivers +v000000000277de00_0 .net "d", 0 0, L_000000000280c1d0; alias, 1 drivers +v000000000277d9a0_0 .net "dout", 0 0, L_000000000280d040; 1 drivers +v000000000277d180_0 .net "ns0", 0 0, L_000000000280d200; 1 drivers +v000000000277d220_0 .net "ns1", 0 0, L_000000000280c080; 1 drivers +v000000000277c500_0 .net "out", 0 0, L_000000000280cfd0; alias, 1 drivers +v000000000277dfe0_0 .net "s0", 0 0, L_000000000279aa20; 1 drivers +v000000000277ce60_0 .net "s1", 0 0, L_000000000279ad40; 1 drivers +S_00000000027738e0 .scope generate, "aluBits[30]" "aluBits[30]" 4 49, 4 49 0, S_0000000000cc7490; + .timescale -9 -12; +P_0000000000f05fe0 .param/l "i" 0 4 49, +C4<011110>; +L_000000000280d120/d .functor XOR 1, L_000000000279b920, v0000000000e68bd0_0, C4<0>, C4<0>; +L_000000000280d120 .delay 1 (20000,20000,20000) L_000000000280d120/d; +L_000000000280d7b0/d .functor AND 1, v0000000000e67370_0, L_000000000279b740, C4<1>, C4<1>; +L_000000000280d7b0 .delay 1 (30000,30000,30000) L_000000000280d7b0/d; +L_000000000280d510/d .functor AND 1, L_000000000279bba0, L_000000000282c280, C4<1>, C4<1>; +L_000000000280d510 .delay 1 (30000,30000,30000) L_000000000280d510/d; +v000000000277fc00_0 .net *"_s1", 0 0, L_000000000279b920; 1 drivers +v000000000277e260_0 .net *"_s3", 0 0, L_000000000279b740; 1 drivers +v0000000002780560_0 .net *"_s9", 0 0, L_000000000279bba0; 1 drivers +S_0000000002773a60 .scope module, "_bit" "aluFullBit" 4 52, 5 6 0, S_00000000027738e0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "res" + .port_info 1 /OUTPUT 1 "carryAND" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "cin" + .port_info 5 /INPUT 1 "ctrl0" + .port_info 6 /INPUT 2 "sel" +v000000000277f980_0 .net "a", 0 0, L_000000000279c3c0; 1 drivers +v000000000277ffc0_0 .net "b", 0 0, L_000000000279bd80; 1 drivers +v000000000277ee40_0 .net "carryAND", 0 0, L_000000000280c390; 1 drivers +v000000000277e580_0 .net "cin", 0 0, L_000000000279c5a0; 1 drivers +v000000000277f700_0 .net "ctrl0", 0 0, L_000000000279aac0; 1 drivers +v0000000002780880_0 .net "nab", 0 0, L_000000000280cbe0; 1 drivers +v000000000277e760_0 .net "orNOR", 0 0, L_000000000280ce10; 1 drivers +v000000000277e1c0_0 .net "res", 0 0, L_000000000280d190; 1 drivers +v0000000002780240_0 .net "sel", 1 0, v0000000000e625f0_0; alias, 1 drivers +v000000000277e9e0_0 .net "sumXOR", 0 0, L_000000000280d970; 1 drivers +L_000000000279aca0 .part v0000000000e625f0_0, 1, 1; +L_000000000279b7e0 .part v0000000000e625f0_0, 0, 1; +S_0000000002773d60 .scope module, "alu" "aluBit" 5 18, 6 14 0, S_0000000002773a60; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sumXOR" + .port_info 1 /OUTPUT 1 "carryAND" + .port_info 2 /OUTPUT 1 "nab" + .port_info 3 /OUTPUT 1 "orNOR" + .port_info 4 /INPUT 1 "a" + .port_info 5 /INPUT 1 "b" + .port_info 6 /INPUT 1 "carryin" + .port_info 7 /INPUT 1 "i0" +L_000000000280cbe0/d .functor NAND 1, L_000000000279c3c0, L_000000000279bd80, C4<1>, C4<1>; +L_000000000280cbe0 .delay 1 (20000,20000,20000) L_000000000280cbe0/d; +L_000000000280d900/d .functor NAND 1, L_000000000279bd80, L_000000000279c5a0, C4<1>, C4<1>; +L_000000000280d900 .delay 1 (20000,20000,20000) L_000000000280d900/d; +L_000000000280c6a0/d .functor NAND 1, L_000000000279c3c0, L_000000000279c5a0, C4<1>, C4<1>; +L_000000000280c6a0 .delay 1 (20000,20000,20000) L_000000000280c6a0/d; +L_000000000280c390/d .functor NAND 1, L_000000000280cbe0, L_000000000280c6a0, L_000000000280d900, C4<1>; +L_000000000280c390 .delay 1 (30000,30000,30000) L_000000000280c390/d; +L_000000000280d970/d .functor XOR 1, L_000000000279c3c0, L_000000000279bd80, L_000000000279c5a0, C4<0>; +L_000000000280d970 .delay 1 (30000,30000,30000) L_000000000280d970/d; +L_000000000280cc50/d .functor NOR 1, L_000000000279c3c0, L_000000000279bd80, C4<0>, C4<0>; +L_000000000280cc50 .delay 1 (20000,20000,20000) L_000000000280cc50/d; +L_000000000280ce10/d .functor XOR 1, L_000000000280cc50, L_000000000279aac0, C4<0>, C4<0>; +L_000000000280ce10 .delay 1 (20000,20000,20000) L_000000000280ce10/d; +v000000000277bec0_0 .net "a", 0 0, L_000000000279c3c0; alias, 1 drivers +v000000000277bf60_0 .net "anorb", 0 0, L_000000000280cc50; 1 drivers +v000000000277e440_0 .net "b", 0 0, L_000000000279bd80; alias, 1 drivers +v000000000277e8a0_0 .net "carryAND", 0 0, L_000000000280c390; alias, 1 drivers +v00000000027801a0_0 .net "carryin", 0 0, L_000000000279c5a0; alias, 1 drivers +v0000000002780060_0 .net "i0", 0 0, L_000000000279aac0; alias, 1 drivers +v000000000277ebc0_0 .net "nab", 0 0, L_000000000280cbe0; alias, 1 drivers +v000000000277e6c0_0 .net "nac", 0 0, L_000000000280c6a0; 1 drivers +v000000000277e940_0 .net "nbc", 0 0, L_000000000280d900; 1 drivers +v000000000277f0c0_0 .net "orNOR", 0 0, L_000000000280ce10; alias, 1 drivers +v000000000277ea80_0 .net "sumXOR", 0 0, L_000000000280d970; alias, 1 drivers +S_0000000002773ee0 .scope module, "mux" "multiplexer" 5 20, 7 7 0, S_0000000002773a60; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "a" + .port_info 2 /INPUT 1 "b" + .port_info 3 /INPUT 1 "c" + .port_info 4 /INPUT 1 "d" + .port_info 5 /INPUT 1 "s1" + .port_info 6 /INPUT 1 "s0" +L_000000000280d350/d .functor NOT 1, L_000000000279b7e0, C4<0>, C4<0>, C4<0>; +L_000000000280d350 .delay 1 (10000,10000,10000) L_000000000280d350/d; +L_000000000280ccc0/d .functor NOT 1, L_000000000279aca0, C4<0>, C4<0>, C4<0>; +L_000000000280ccc0 .delay 1 (10000,10000,10000) L_000000000280ccc0/d; +L_000000000280d270/d .functor NAND 1, L_000000000279aca0, L_000000000279b7e0, L_000000000280d970, C4<1>; +L_000000000280d270 .delay 1 (30000,30000,30000) L_000000000280d270/d; +L_000000000280d2e0/d .functor NAND 1, L_000000000279aca0, L_000000000280d350, L_000000000280ce10, C4<1>; +L_000000000280d2e0 .delay 1 (30000,30000,30000) L_000000000280d2e0/d; +L_000000000280d0b0/d .functor NAND 1, L_000000000280ccc0, L_000000000279b7e0, L_000000000280c390, C4<1>; +L_000000000280d0b0 .delay 1 (30000,30000,30000) L_000000000280d0b0/d; +L_000000000280c9b0/d .functor NAND 1, L_000000000280ccc0, L_000000000280d350, L_000000000280cbe0, C4<1>; +L_000000000280c9b0 .delay 1 (30000,30000,30000) L_000000000280c9b0/d; +L_000000000280d190/d .functor NAND 1, L_000000000280d270, L_000000000280d2e0, L_000000000280d0b0, L_000000000280c9b0; +L_000000000280d190 .delay 1 (40000,40000,40000) L_000000000280d190/d; +v000000000277fca0_0 .net "a", 0 0, L_000000000280d970; alias, 1 drivers +v000000000277e620_0 .net "aout", 0 0, L_000000000280d270; 1 drivers +v00000000027802e0_0 .net "b", 0 0, L_000000000280ce10; alias, 1 drivers +v000000000277e4e0_0 .net "bout", 0 0, L_000000000280d2e0; 1 drivers +v000000000277eee0_0 .net "c", 0 0, L_000000000280c390; alias, 1 drivers +v000000000277eb20_0 .net "cout", 0 0, L_000000000280d0b0; 1 drivers +v00000000027807e0_0 .net "d", 0 0, L_000000000280cbe0; alias, 1 drivers +v000000000277f520_0 .net "dout", 0 0, L_000000000280c9b0; 1 drivers +v000000000277f3e0_0 .net "ns0", 0 0, L_000000000280d350; 1 drivers +v000000000277e120_0 .net "ns1", 0 0, L_000000000280ccc0; 1 drivers +v0000000002780380_0 .net "out", 0 0, L_000000000280d190; alias, 1 drivers +v000000000277e800_0 .net "s0", 0 0, L_000000000279b7e0; 1 drivers +v0000000002780420_0 .net "s1", 0 0, L_000000000279aca0; 1 drivers +S_00000000027720e0 .scope generate, "aluBits[31]" "aluBits[31]" 4 49, 4 49 0, S_0000000000cc7490; + .timescale -9 -12; +P_0000000000f061a0 .param/l "i" 0 4 49, +C4<011111>; +L_000000000280d430/d .functor XOR 1, L_000000000279b9c0, v0000000000e68bd0_0, C4<0>, C4<0>; +L_000000000280d430 .delay 1 (20000,20000,20000) L_000000000280d430/d; +L_000000000280cd30/d .functor AND 1, v0000000000e67370_0, L_000000000279be20, C4<1>, C4<1>; +L_000000000280cd30 .delay 1 (30000,30000,30000) L_000000000280cd30/d; +L_000000000280d3c0/d .functor AND 1, L_000000000279c820, L_000000000282c280, C4<1>, C4<1>; +L_000000000280d3c0 .delay 1 (30000,30000,30000) L_000000000280d3c0/d; +v00000000027813c0_0 .net *"_s1", 0 0, L_000000000279b9c0; 1 drivers +v00000000027815a0_0 .net *"_s3", 0 0, L_000000000279be20; 1 drivers +v00000000027829a0_0 .net *"_s9", 0 0, L_000000000279c820; 1 drivers +S_0000000002784580 .scope module, "_bit" "aluFullBit" 4 52, 5 6 0, S_00000000027720e0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "res" + .port_info 1 /OUTPUT 1 "carryAND" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "cin" + .port_info 5 /INPUT 1 "ctrl0" + .port_info 6 /INPUT 2 "sel" +v000000000277f660_0 .net "a", 0 0, L_000000000279c640; 1 drivers +v0000000002780740_0 .net "b", 0 0, L_000000000279a3e0; 1 drivers +v000000000277fd40_0 .net "carryAND", 0 0, L_000000000280c5c0; 1 drivers +v000000000277fde0_0 .net "cin", 0 0, L_000000000279bf60; 1 drivers +v000000000277ff20_0 .net "ctrl0", 0 0, L_000000000279c6e0; 1 drivers +v0000000002781000_0 .net "nab", 0 0, L_000000000280c400; 1 drivers +v00000000027824a0_0 .net "orNOR", 0 0, L_000000000280c7f0; 1 drivers +v0000000002782540_0 .net "res", 0 0, L_000000000280d580; 1 drivers +v0000000002781640_0 .net "sel", 1 0, v0000000000e625f0_0; alias, 1 drivers +v00000000027809c0_0 .net "sumXOR", 0 0, L_000000000280c780; 1 drivers +L_000000000279bec0 .part v0000000000e625f0_0, 1, 1; +L_000000000279a7a0 .part v0000000000e625f0_0, 0, 1; +S_0000000002785300 .scope module, "alu" "aluBit" 5 18, 6 14 0, S_0000000002784580; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sumXOR" + .port_info 1 /OUTPUT 1 "carryAND" + .port_info 2 /OUTPUT 1 "nab" + .port_info 3 /OUTPUT 1 "orNOR" + .port_info 4 /INPUT 1 "a" + .port_info 5 /INPUT 1 "b" + .port_info 6 /INPUT 1 "carryin" + .port_info 7 /INPUT 1 "i0" +L_000000000280c400/d .functor NAND 1, L_000000000279c640, L_000000000279a3e0, C4<1>, C4<1>; +L_000000000280c400 .delay 1 (20000,20000,20000) L_000000000280c400/d; +L_000000000280c470/d .functor NAND 1, L_000000000279a3e0, L_000000000279bf60, C4<1>, C4<1>; +L_000000000280c470 .delay 1 (20000,20000,20000) L_000000000280c470/d; +L_000000000280c4e0/d .functor NAND 1, L_000000000279c640, L_000000000279bf60, C4<1>, C4<1>; +L_000000000280c4e0 .delay 1 (20000,20000,20000) L_000000000280c4e0/d; +L_000000000280c5c0/d .functor NAND 1, L_000000000280c400, L_000000000280c4e0, L_000000000280c470, C4<1>; +L_000000000280c5c0 .delay 1 (30000,30000,30000) L_000000000280c5c0/d; +L_000000000280c780/d .functor XOR 1, L_000000000279c640, L_000000000279a3e0, L_000000000279bf60, C4<0>; +L_000000000280c780 .delay 1 (30000,30000,30000) L_000000000280c780/d; +L_000000000280c630/d .functor NOR 1, L_000000000279c640, L_000000000279a3e0, C4<0>, C4<0>; +L_000000000280c630 .delay 1 (20000,20000,20000) L_000000000280c630/d; +L_000000000280c7f0/d .functor XOR 1, L_000000000280c630, L_000000000279c6e0, C4<0>, C4<0>; +L_000000000280c7f0 .delay 1 (20000,20000,20000) L_000000000280c7f0/d; +v000000000277e300_0 .net "a", 0 0, L_000000000279c640; alias, 1 drivers +v000000000277ec60_0 .net "anorb", 0 0, L_000000000280c630; 1 drivers +v000000000277fac0_0 .net "b", 0 0, L_000000000279a3e0; alias, 1 drivers +v000000000277fe80_0 .net "carryAND", 0 0, L_000000000280c5c0; alias, 1 drivers +v000000000277ef80_0 .net "carryin", 0 0, L_000000000279bf60; alias, 1 drivers +v0000000002780100_0 .net "i0", 0 0, L_000000000279c6e0; alias, 1 drivers +v000000000277e3a0_0 .net "nab", 0 0, L_000000000280c400; alias, 1 drivers +v000000000277ed00_0 .net "nac", 0 0, L_000000000280c4e0; 1 drivers +v000000000277eda0_0 .net "nbc", 0 0, L_000000000280c470; 1 drivers +v000000000277f020_0 .net "orNOR", 0 0, L_000000000280c7f0; alias, 1 drivers +v000000000277f160_0 .net "sumXOR", 0 0, L_000000000280c780; alias, 1 drivers +S_0000000002784d00 .scope module, "mux" "multiplexer" 5 20, 7 7 0, S_0000000002784580; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "a" + .port_info 2 /INPUT 1 "b" + .port_info 3 /INPUT 1 "c" + .port_info 4 /INPUT 1 "d" + .port_info 5 /INPUT 1 "s1" + .port_info 6 /INPUT 1 "s0" +L_000000000280c8d0/d .functor NOT 1, L_000000000279a7a0, C4<0>, C4<0>, C4<0>; +L_000000000280c8d0 .delay 1 (10000,10000,10000) L_000000000280c8d0/d; +L_000000000280c940/d .functor NOT 1, L_000000000279bec0, C4<0>, C4<0>, C4<0>; +L_000000000280c940 .delay 1 (10000,10000,10000) L_000000000280c940/d; +L_000000000280ca20/d .functor NAND 1, L_000000000279bec0, L_000000000279a7a0, L_000000000280c780, C4<1>; +L_000000000280ca20 .delay 1 (30000,30000,30000) L_000000000280ca20/d; +L_000000000280ca90/d .functor NAND 1, L_000000000279bec0, L_000000000280c8d0, L_000000000280c7f0, C4<1>; +L_000000000280ca90 .delay 1 (30000,30000,30000) L_000000000280ca90/d; +L_000000000280cda0/d .functor NAND 1, L_000000000280c940, L_000000000279a7a0, L_000000000280c5c0, C4<1>; +L_000000000280cda0 .delay 1 (30000,30000,30000) L_000000000280cda0/d; +L_000000000280ce80/d .functor NAND 1, L_000000000280c940, L_000000000280c8d0, L_000000000280c400, C4<1>; +L_000000000280ce80 .delay 1 (30000,30000,30000) L_000000000280ce80/d; +L_000000000280d580/d .functor NAND 1, L_000000000280ca20, L_000000000280ca90, L_000000000280cda0, L_000000000280ce80; +L_000000000280d580 .delay 1 (40000,40000,40000) L_000000000280d580/d; +v000000000277f200_0 .net "a", 0 0, L_000000000280c780; alias, 1 drivers +v0000000002780600_0 .net "aout", 0 0, L_000000000280ca20; 1 drivers +v000000000277f840_0 .net "b", 0 0, L_000000000280c7f0; alias, 1 drivers +v000000000277f8e0_0 .net "bout", 0 0, L_000000000280ca90; 1 drivers +v000000000277f2a0_0 .net "c", 0 0, L_000000000280c5c0; alias, 1 drivers +v00000000027804c0_0 .net "cout", 0 0, L_000000000280cda0; 1 drivers +v00000000027806a0_0 .net "d", 0 0, L_000000000280c400; alias, 1 drivers +v000000000277f340_0 .net "dout", 0 0, L_000000000280ce80; 1 drivers +v000000000277fa20_0 .net "ns0", 0 0, L_000000000280c8d0; 1 drivers +v000000000277f480_0 .net "ns1", 0 0, L_000000000280c940; 1 drivers +v000000000277f7a0_0 .net "out", 0 0, L_000000000280d580; alias, 1 drivers +v000000000277fb60_0 .net "s0", 0 0, L_000000000279a7a0; 1 drivers +v000000000277f5c0_0 .net "s1", 0 0, L_000000000279bec0; 1 drivers +S_0000000002785780 .scope generate, "zeroFlag[0]" "zeroFlag[0]" 4 66, 4 66 0, S_0000000000cc7490; + .timescale -9 -12; +P_0000000000f078a0 .param/l "i" 0 4 66, +C4<00>; +L_000000000280d660/d .functor OR 1, L_000000000279ee40, L_000000000279d680, C4<0>, C4<0>; +L_000000000280d660 .delay 1 (30000,30000,30000) L_000000000280d660/d; +v00000000027818c0_0 .net *"_s1", 0 0, L_000000000279ee40; 1 drivers +v0000000002781c80_0 .net *"_s2", 0 0, L_000000000279d680; 1 drivers +S_0000000002784880 .scope generate, "zeroFlag[1]" "zeroFlag[1]" 4 66, 4 66 0, S_0000000000cc7490; + .timescale -9 -12; +P_0000000000f070a0 .param/l "i" 0 4 66, +C4<01>; +L_000000000280d4a0/d .functor OR 1, L_000000000279db80, L_000000000279e620, C4<0>, C4<0>; +L_000000000280d4a0 .delay 1 (30000,30000,30000) L_000000000280d4a0/d; +v0000000002780c40_0 .net *"_s1", 0 0, L_000000000279db80; 1 drivers +v0000000002780ce0_0 .net *"_s2", 0 0, L_000000000279e620; 1 drivers +S_0000000002785a80 .scope generate, "zeroFlag[2]" "zeroFlag[2]" 4 66, 4 66 0, S_0000000000cc7490; + .timescale -9 -12; +P_0000000000f07ca0 .param/l "i" 0 4 66, +C4<010>; +L_000000000280d6d0/d .functor OR 1, L_000000000279e440, L_000000000279e580, C4<0>, C4<0>; +L_000000000280d6d0 .delay 1 (30000,30000,30000) L_000000000280d6d0/d; +v0000000002781320_0 .net *"_s1", 0 0, L_000000000279e440; 1 drivers +v0000000002781d20_0 .net *"_s2", 0 0, L_000000000279e580; 1 drivers +S_0000000002784280 .scope generate, "zeroFlag[3]" "zeroFlag[3]" 4 66, 4 66 0, S_0000000000cc7490; + .timescale -9 -12; +P_0000000000f07de0 .param/l "i" 0 4 66, +C4<011>; +L_000000000280d820/d .functor OR 1, L_000000000279ce60, L_000000000279da40, C4<0>, C4<0>; +L_000000000280d820 .delay 1 (30000,30000,30000) L_000000000280d820/d; +v0000000002781aa0_0 .net *"_s1", 0 0, L_000000000279ce60; 1 drivers +v0000000002782a40_0 .net *"_s2", 0 0, L_000000000279da40; 1 drivers +S_0000000002784100 .scope generate, "zeroFlag[4]" "zeroFlag[4]" 4 66, 4 66 0, S_0000000000cc7490; + .timescale -9 -12; +P_0000000000f07ae0 .param/l "i" 0 4 66, +C4<0100>; +L_000000000280bde0/d .functor OR 1, L_000000000279e4e0, L_000000000279e260, C4<0>, C4<0>; +L_000000000280bde0 .delay 1 (30000,30000,30000) L_000000000280bde0/d; +v0000000002782400_0 .net *"_s1", 0 0, L_000000000279e4e0; 1 drivers +v0000000002781f00_0 .net *"_s2", 0 0, L_000000000279e260; 1 drivers +S_0000000002784a00 .scope generate, "zeroFlag[5]" "zeroFlag[5]" 4 66, 4 66 0, S_0000000000cc7490; + .timescale -9 -12; +P_0000000000f07560 .param/l "i" 0 4 66, +C4<0101>; +L_000000000280d890/d .functor OR 1, L_000000000279e6c0, L_000000000279d180, C4<0>, C4<0>; +L_000000000280d890 .delay 1 (30000,30000,30000) L_000000000280d890/d; +v00000000027810a0_0 .net *"_s1", 0 0, L_000000000279e6c0; 1 drivers +v0000000002781dc0_0 .net *"_s2", 0 0, L_000000000279d180; 1 drivers +S_0000000002785900 .scope generate, "zeroFlag[6]" "zeroFlag[6]" 4 66, 4 66 0, S_0000000000cc7490; + .timescale -9 -12; +P_0000000000f07220 .param/l "i" 0 4 66, +C4<0110>; +L_000000000280be50/d .functor OR 1, L_000000000279e940, L_000000000279eda0, C4<0>, C4<0>; +L_000000000280be50 .delay 1 (30000,30000,30000) L_000000000280be50/d; +v00000000027820e0_0 .net *"_s1", 0 0, L_000000000279e940; 1 drivers +v0000000002782c20_0 .net *"_s2", 0 0, L_000000000279eda0; 1 drivers +S_0000000002785600 .scope generate, "zeroFlag[7]" "zeroFlag[7]" 4 66, 4 66 0, S_0000000000cc7490; + .timescale -9 -12; +P_0000000000f07be0 .param/l "i" 0 4 66, +C4<0111>; +L_000000000280bfa0/d .functor OR 1, L_000000000279df40, L_000000000279e760, C4<0>, C4<0>; +L_000000000280bfa0 .delay 1 (30000,30000,30000) L_000000000280bfa0/d; +v0000000002780d80_0 .net *"_s1", 0 0, L_000000000279df40; 1 drivers +v0000000002782f40_0 .net *"_s2", 0 0, L_000000000279e760; 1 drivers +S_0000000002785000 .scope generate, "zeroFlag[8]" "zeroFlag[8]" 4 66, 4 66 0, S_0000000000cc7490; + .timescale -9 -12; +P_0000000000f071e0 .param/l "i" 0 4 66, +C4<01000>; +L_000000000280c010/d .functor OR 1, L_000000000279dea0, L_000000000279e080, C4<0>, C4<0>; +L_000000000280c010 .delay 1 (30000,30000,30000) L_000000000280c010/d; +v0000000002781b40_0 .net *"_s1", 0 0, L_000000000279dea0; 1 drivers +v0000000002782680_0 .net *"_s2", 0 0, L_000000000279e080; 1 drivers +S_0000000002784700 .scope generate, "zeroFlag[9]" "zeroFlag[9]" 4 66, 4 66 0, S_0000000000cc7490; + .timescale -9 -12; +P_0000000000f07e20 .param/l "i" 0 4 66, +C4<01001>; +L_000000000280c0f0/d .functor OR 1, L_000000000279d040, L_000000000279e800, C4<0>, C4<0>; +L_000000000280c0f0 .delay 1 (30000,30000,30000) L_000000000280c0f0/d; +v0000000002780e20_0 .net *"_s1", 0 0, L_000000000279d040; 1 drivers +v0000000002780920_0 .net *"_s2", 0 0, L_000000000279e800; 1 drivers +S_0000000002785c00 .scope generate, "zeroFlag[10]" "zeroFlag[10]" 4 66, 4 66 0, S_0000000000cc7490; + .timescale -9 -12; +P_0000000000f072a0 .param/l "i" 0 4 66, +C4<01010>; +L_000000000280deb0/d .functor OR 1, L_000000000279d5e0, L_000000000279ec60, C4<0>, C4<0>; +L_000000000280deb0 .delay 1 (30000,30000,30000) L_000000000280deb0/d; +v0000000002781e60_0 .net *"_s1", 0 0, L_000000000279d5e0; 1 drivers +v0000000002780f60_0 .net *"_s2", 0 0, L_000000000279ec60; 1 drivers +S_0000000002784b80 .scope generate, "zeroFlag[11]" "zeroFlag[11]" 4 66, 4 66 0, S_0000000000cc7490; + .timescale -9 -12; +P_0000000000f07260 .param/l "i" 0 4 66, +C4<01011>; +L_000000000280df90/d .functor OR 1, L_000000000279e1c0, L_000000000279cd20, C4<0>, C4<0>; +L_000000000280df90 .delay 1 (30000,30000,30000) L_000000000280df90/d; +v0000000002783080_0 .net *"_s1", 0 0, L_000000000279e1c0; 1 drivers +v0000000002782cc0_0 .net *"_s2", 0 0, L_000000000279cd20; 1 drivers +S_0000000002785d80 .scope generate, "zeroFlag[12]" "zeroFlag[12]" 4 66, 4 66 0, S_0000000000cc7490; + .timescale -9 -12; +P_0000000000f070e0 .param/l "i" 0 4 66, +C4<01100>; +L_000000000280d9e0/d .functor OR 1, L_000000000279e8a0, L_000000000279d360, C4<0>, C4<0>; +L_000000000280d9e0 .delay 1 (30000,30000,30000) L_000000000280d9e0/d; +v00000000027825e0_0 .net *"_s1", 0 0, L_000000000279e8a0; 1 drivers +v0000000002781460_0 .net *"_s2", 0 0, L_000000000279d360; 1 drivers +S_0000000002784e80 .scope generate, "zeroFlag[13]" "zeroFlag[13]" 4 66, 4 66 0, S_0000000000cc7490; + .timescale -9 -12; +P_0000000000f07720 .param/l "i" 0 4 66, +C4<01101>; +L_000000000280e0e0/d .functor OR 1, L_000000000279eee0, L_000000000279d7c0, C4<0>, C4<0>; +L_000000000280e0e0 .delay 1 (30000,30000,30000) L_000000000280e0e0/d; +v0000000002781140_0 .net *"_s1", 0 0, L_000000000279eee0; 1 drivers +v0000000002782d60_0 .net *"_s2", 0 0, L_000000000279d7c0; 1 drivers +S_0000000002785180 .scope generate, "zeroFlag[14]" "zeroFlag[14]" 4 66, 4 66 0, S_0000000000cc7490; + .timescale -9 -12; +P_0000000000f072e0 .param/l "i" 0 4 66, +C4<01110>; +L_000000000280dcf0/d .functor OR 1, L_000000000279e120, L_000000000279d720, C4<0>, C4<0>; +L_000000000280dcf0 .delay 1 (30000,30000,30000) L_000000000280dcf0/d; +v00000000027811e0_0 .net *"_s1", 0 0, L_000000000279e120; 1 drivers +v0000000002782ea0_0 .net *"_s2", 0 0, L_000000000279d720; 1 drivers +S_0000000002785f00 .scope generate, "zeroFlag[15]" "zeroFlag[15]" 4 66, 4 66 0, S_0000000000cc7490; + .timescale -9 -12; +P_0000000000f07320 .param/l "i" 0 4 66, +C4<01111>; +L_000000000280df20/d .functor OR 1, L_000000000279cbe0, L_000000000279cdc0, C4<0>, C4<0>; +L_000000000280df20 .delay 1 (30000,30000,30000) L_000000000280df20/d; +v0000000002781280_0 .net *"_s1", 0 0, L_000000000279cbe0; 1 drivers +v0000000002782720_0 .net *"_s2", 0 0, L_000000000279cdc0; 1 drivers +S_0000000002785480 .scope generate, "zeroFlag[16]" "zeroFlag[16]" 4 66, 4 66 0, S_0000000000cc7490; + .timescale -9 -12; +P_0000000000f06ee0 .param/l "i" 0 4 66, +C4<010000>; +L_000000000280db30/d .functor OR 1, L_000000000279d860, L_000000000279d0e0, C4<0>, C4<0>; +L_000000000280db30 .delay 1 (30000,30000,30000) L_000000000280db30/d; +v0000000002781500_0 .net *"_s1", 0 0, L_000000000279d860; 1 drivers +v00000000027816e0_0 .net *"_s2", 0 0, L_000000000279d0e0; 1 drivers +S_0000000002784400 .scope generate, "zeroFlag[17]" "zeroFlag[17]" 4 66, 4 66 0, S_0000000000cc7490; + .timescale -9 -12; +P_0000000000f075a0 .param/l "i" 0 4 66, +C4<010001>; +L_000000000280dba0/d .functor OR 1, L_000000000279dfe0, L_000000000279ed00, C4<0>, C4<0>; +L_000000000280dba0 .delay 1 (30000,30000,30000) L_000000000280dba0/d; +v00000000027827c0_0 .net *"_s1", 0 0, L_000000000279dfe0; 1 drivers +v0000000002781be0_0 .net *"_s2", 0 0, L_000000000279ed00; 1 drivers +S_000000000278fda0 .scope generate, "zeroFlag[18]" "zeroFlag[18]" 4 66, 4 66 0, S_0000000000cc7490; + .timescale -9 -12; +P_0000000000f07360 .param/l "i" 0 4 66, +C4<010010>; +L_000000000280da50/d .functor OR 1, L_000000000279ebc0, L_000000000279e300, C4<0>, C4<0>; +L_000000000280da50 .delay 1 (30000,30000,30000) L_000000000280da50/d; +v0000000002781fa0_0 .net *"_s1", 0 0, L_000000000279ebc0; 1 drivers +v0000000002780ba0_0 .net *"_s2", 0 0, L_000000000279e300; 1 drivers +S_000000000278ff20 .scope generate, "zeroFlag[19]" "zeroFlag[19]" 4 66, 4 66 0, S_0000000000cc7490; + .timescale -9 -12; +P_0000000000f075e0 .param/l "i" 0 4 66, +C4<010011>; +L_000000000280dac0/d .functor OR 1, L_000000000279ef80, L_000000000279f020, C4<0>, C4<0>; +L_000000000280dac0 .delay 1 (30000,30000,30000) L_000000000280dac0/d; +v0000000002782ae0_0 .net *"_s1", 0 0, L_000000000279ef80; 1 drivers +v0000000002780b00_0 .net *"_s2", 0 0, L_000000000279f020; 1 drivers +S_000000000278f920 .scope generate, "zeroFlag[20]" "zeroFlag[20]" 4 66, 4 66 0, S_0000000000cc7490; + .timescale -9 -12; +P_0000000000f07960 .param/l "i" 0 4 66, +C4<010100>; +L_000000000280e000/d .functor OR 1, L_000000000279dc20, L_000000000279dcc0, C4<0>, C4<0>; +L_000000000280e000 .delay 1 (30000,30000,30000) L_000000000280e000/d; +v0000000002782040_0 .net *"_s1", 0 0, L_000000000279dc20; 1 drivers +v0000000002781780_0 .net *"_s2", 0 0, L_000000000279dcc0; 1 drivers +S_000000000278eea0 .scope generate, "zeroFlag[21]" "zeroFlag[21]" 4 66, 4 66 0, S_0000000000cc7490; + .timescale -9 -12; +P_0000000000f071a0 .param/l "i" 0 4 66, +C4<010101>; +L_000000000280dc10/d .functor OR 1, L_000000000279cf00, L_000000000279cc80, C4<0>, C4<0>; +L_000000000280dc10 .delay 1 (30000,30000,30000) L_000000000280dc10/d; +v0000000002782180_0 .net *"_s1", 0 0, L_000000000279cf00; 1 drivers +v00000000027822c0_0 .net *"_s2", 0 0, L_000000000279cc80; 1 drivers +S_000000000278e720 .scope generate, "zeroFlag[22]" "zeroFlag[22]" 4 66, 4 66 0, S_0000000000cc7490; + .timescale -9 -12; +P_0000000000f07820 .param/l "i" 0 4 66, +C4<010110>; +L_000000000280dc80/d .functor OR 1, L_000000000279e9e0, L_000000000279d900, C4<0>, C4<0>; +L_000000000280dc80 .delay 1 (30000,30000,30000) L_000000000280dc80/d; +v0000000002782e00_0 .net *"_s1", 0 0, L_000000000279e9e0; 1 drivers +v0000000002782220_0 .net *"_s2", 0 0, L_000000000279d900; 1 drivers +S_000000000278faa0 .scope generate, "zeroFlag[23]" "zeroFlag[23]" 4 66, 4 66 0, S_0000000000cc7490; + .timescale -9 -12; +P_0000000000f07060 .param/l "i" 0 4 66, +C4<010111>; +L_000000000280de40/d .functor OR 1, L_000000000279e3a0, L_000000000279f0c0, C4<0>, C4<0>; +L_000000000280de40 .delay 1 (30000,30000,30000) L_000000000280de40/d; +v0000000002782fe0_0 .net *"_s1", 0 0, L_000000000279e3a0; 1 drivers +v0000000002781960_0 .net *"_s2", 0 0, L_000000000279f0c0; 1 drivers +S_000000000278e8a0 .scope generate, "zeroFlag[24]" "zeroFlag[24]" 4 66, 4 66 0, S_0000000000cc7490; + .timescale -9 -12; +P_0000000000f07620 .param/l "i" 0 4 66, +C4<011000>; +L_000000000280dd60/d .functor OR 1, L_000000000279ea80, L_000000000279caa0, C4<0>, C4<0>; +L_000000000280dd60 .delay 1 (30000,30000,30000) L_000000000280dd60/d; +v0000000002782860_0 .net *"_s1", 0 0, L_000000000279ea80; 1 drivers +v0000000002780ec0_0 .net *"_s2", 0 0, L_000000000279caa0; 1 drivers +S_000000000278e120 .scope generate, "zeroFlag[25]" "zeroFlag[25]" 4 66, 4 66 0, S_0000000000cc7490; + .timescale -9 -12; +P_0000000000f07120 .param/l "i" 0 4 66, +C4<011001>; +L_000000000280ddd0/d .functor OR 1, L_000000000279d4a0, L_000000000279dd60, C4<0>, C4<0>; +L_000000000280ddd0 .delay 1 (30000,30000,30000) L_000000000280ddd0/d; +v0000000002780a60_0 .net *"_s1", 0 0, L_000000000279d4a0; 1 drivers +v0000000002782360_0 .net *"_s2", 0 0, L_000000000279dd60; 1 drivers +S_000000000278ea20 .scope generate, "zeroFlag[26]" "zeroFlag[26]" 4 66, 4 66 0, S_0000000000cc7490; + .timescale -9 -12; +P_0000000000f076e0 .param/l "i" 0 4 66, +C4<011010>; +L_000000000280e070/d .functor OR 1, L_000000000279eb20, L_000000000279c960, C4<0>, C4<0>; +L_000000000280e070 .delay 1 (30000,30000,30000) L_000000000280e070/d; +v0000000002781820_0 .net *"_s1", 0 0, L_000000000279eb20; 1 drivers +v0000000002781a00_0 .net *"_s2", 0 0, L_000000000279c960; 1 drivers +S_000000000278eba0 .scope generate, "zeroFlag[27]" "zeroFlag[27]" 4 66, 4 66 0, S_0000000000cc7490; + .timescale -9 -12; +P_0000000000f07e60 .param/l "i" 0 4 66, +C4<011011>; +L_000000000282c8a0/d .functor OR 1, L_000000000279d400, L_000000000279d220, C4<0>, C4<0>; +L_000000000282c8a0 .delay 1 (30000,30000,30000) L_000000000282c8a0/d; +v0000000002782900_0 .net *"_s1", 0 0, L_000000000279d400; 1 drivers +v0000000002782b80_0 .net *"_s2", 0 0, L_000000000279d220; 1 drivers +S_000000000278e5a0 .scope generate, "zeroFlag[28]" "zeroFlag[28]" 4 66, 4 66 0, S_0000000000cc7490; + .timescale -9 -12; +P_0000000000f07a20 .param/l "i" 0 4 66, +C4<011100>; +L_000000000282cad0/d .functor OR 1, L_000000000279ca00, L_000000000279cb40, C4<0>, C4<0>; +L_000000000282cad0 .delay 1 (30000,30000,30000) L_000000000282cad0/d; +v00000000027834e0_0 .net *"_s1", 0 0, L_000000000279ca00; 1 drivers +v0000000002783260_0 .net *"_s2", 0 0, L_000000000279cb40; 1 drivers +S_000000000278f320 .scope generate, "zeroFlag[29]" "zeroFlag[29]" 4 66, 4 66 0, S_0000000000cc7490; + .timescale -9 -12; +P_0000000000f07420 .param/l "i" 0 4 66, +C4<011101>; +L_000000000282c2f0/d .functor OR 1, L_000000000279cfa0, L_000000000279d2c0, C4<0>, C4<0>; +L_000000000282c2f0 .delay 1 (30000,30000,30000) L_000000000282c2f0/d; +v0000000002783e40_0 .net *"_s1", 0 0, L_000000000279cfa0; 1 drivers +v00000000027833a0_0 .net *"_s2", 0 0, L_000000000279d2c0; 1 drivers + .scope S_0000000000cb6030; +T_0 ; + %wait E_0000000000f05e20; + %load/vec4 v0000000000e68db0_0; + %dup/vec4; + %pushi/vec4 0, 0, 3; + %cmp/u; + %jmp/1 T_0.0, 6; + %dup/vec4; + %pushi/vec4 1, 0, 3; + %cmp/u; + %jmp/1 T_0.1, 6; + %dup/vec4; + %pushi/vec4 4, 0, 3; + %cmp/u; + %jmp/1 T_0.2, 6; + %dup/vec4; + %pushi/vec4 5, 0, 3; + %cmp/u; + %jmp/1 T_0.3, 6; + %dup/vec4; + %pushi/vec4 6, 0, 3; + %cmp/u; + %jmp/1 T_0.4, 6; + %dup/vec4; + %pushi/vec4 7, 0, 3; + %cmp/u; + %jmp/1 T_0.5, 6; + %dup/vec4; + %pushi/vec4 2, 0, 3; + %cmp/u; + %jmp/1 T_0.6, 6; + %dup/vec4; + %pushi/vec4 3, 0, 3; + %cmp/u; + %jmp/1 T_0.7, 6; + %jmp T_0.8; +T_0.0 ; + %pushi/vec4 3, 0, 2; + %store/vec4 v0000000000e625f0_0, 0, 2; + %pushi/vec4 0, 0, 1; + %store/vec4 v0000000000e68bd0_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0000000000e67370_0, 0, 1; + %jmp T_0.8; +T_0.1 ; + %pushi/vec4 3, 0, 2; + %store/vec4 v0000000000e625f0_0, 0, 2; + %pushi/vec4 1, 0, 1; + %store/vec4 v0000000000e68bd0_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0000000000e67370_0, 0, 1; + %jmp T_0.8; +T_0.2 ; + %pushi/vec4 1, 0, 2; + %store/vec4 v0000000000e625f0_0, 0, 2; + %pushi/vec4 0, 0, 1; + %store/vec4 v0000000000e68bd0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0000000000e67370_0, 0, 1; + %jmp T_0.8; +T_0.3 ; + %pushi/vec4 0, 0, 2; + %store/vec4 v0000000000e625f0_0, 0, 2; + %pushi/vec4 0, 0, 1; + %store/vec4 v0000000000e68bd0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0000000000e67370_0, 0, 1; + %jmp T_0.8; +T_0.4 ; + %pushi/vec4 2, 0, 2; + %store/vec4 v0000000000e625f0_0, 0, 2; + %pushi/vec4 0, 0, 1; + %store/vec4 v0000000000e68bd0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0000000000e67370_0, 0, 1; + %jmp T_0.8; +T_0.5 ; + %pushi/vec4 2, 0, 2; + %store/vec4 v0000000000e625f0_0, 0, 2; + %pushi/vec4 0, 0, 1; + %store/vec4 v0000000000e68bd0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0000000000e67370_0, 0, 1; + %jmp T_0.8; +T_0.6 ; + %pushi/vec4 3, 0, 2; + %store/vec4 v0000000000e625f0_0, 0, 2; + %pushi/vec4 0, 0, 1; + %store/vec4 v0000000000e68bd0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0000000000e67370_0, 0, 1; + %jmp T_0.8; +T_0.7 ; + %pushi/vec4 3, 0, 2; + %store/vec4 v0000000000e625f0_0, 0, 2; + %pushi/vec4 1, 0, 1; + %store/vec4 v0000000000e68bd0_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0000000000e67370_0, 0, 1; + %jmp T_0.8; +T_0.8 ; + %pop/vec4 1; + %jmp T_0; + .thread T_0, $push; + .scope S_0000000000cd86f0; +T_1 ; + %vpi_call 3 28 "$display", " operandA | operandB | cmd | result | eResult | cOut | eCOut | Overflow | eOverflow | Zero | eZero" {0 0 0}; + %vpi_call 3 29 "$display" {0 0 0}; + %vpi_call 3 30 "$display", "ADD COMMAND -----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------" {0 0 0}; + %pushi/vec4 2000, 0, 32; + %store/vec4 v0000000002790660_0, 0, 32; + %pushi/vec4 2147483000, 0, 32; + %store/vec4 v0000000002790b60_0, 0, 32; + %pushi/vec4 0, 0, 3; + %store/vec4 v0000000002790a20_0, 0, 3; + %delay 10000000, 0; + %vpi_call 3 34 "$display", "| %b | %b | ADD | %b | 10000000000000000000010101001000 | %b | 0 | %b | 1 | %b | 0 |", v0000000002790660_0, v0000000002790b60_0, v0000000002791ec0_0, v0000000002791920_0, v0000000002792320_0, v0000000002790700_0 {0 0 0}; + %pushi/vec4 4294967266, 0, 32; + %store/vec4 v0000000002790660_0, 0, 32; + %pushi/vec4 50, 0, 32; + %store/vec4 v0000000002790b60_0, 0, 32; + %pushi/vec4 0, 0, 3; + %store/vec4 v0000000002790a20_0, 0, 3; + %delay 10000000, 0; + %vpi_call 3 38 "$display", "| %b | %b | ADD | %b | 00000000000000000000000000010100 | %b | 1 | %b | 0 | %b | 0 |", v0000000002790660_0, v0000000002790b60_0, v0000000002791ec0_0, v0000000002791920_0, v0000000002792320_0, v0000000002790700_0 {0 0 0}; + %pushi/vec4 2, 0, 32; + %store/vec4 v0000000002790660_0, 0, 32; + %pushi/vec4 4294967291, 0, 32; + %store/vec4 v0000000002790b60_0, 0, 32; + %pushi/vec4 0, 0, 3; + %store/vec4 v0000000002790a20_0, 0, 3; + %delay 10000000, 0; + %vpi_call 3 42 "$display", "| %b | %b | ADD | %b | 11111111111111111111111111111101 | %b | 0 | %b | 0 | %b | 0 |", v0000000002790660_0, v0000000002790b60_0, v0000000002791ec0_0, v0000000002791920_0, v0000000002792320_0, v0000000002790700_0 {0 0 0}; + %pushi/vec4 4294967096, 0, 32; + %store/vec4 v0000000002790660_0, 0, 32; + %pushi/vec4 200, 0, 32; + %store/vec4 v0000000002790b60_0, 0, 32; + %pushi/vec4 0, 0, 3; + %store/vec4 v0000000002790a20_0, 0, 3; + %delay 10000000, 0; + %vpi_call 3 46 "$display", "| %b | %b | ADD | %b | 00000000000000000000000000000000 | %b | 1 | %b | 0 | %b | 1 |", v0000000002790660_0, v0000000002790b60_0, v0000000002791ec0_0, v0000000002791920_0, v0000000002792320_0, v0000000002790700_0 {0 0 0}; + %pushi/vec4 4294967294, 0, 32; + %store/vec4 v0000000002790660_0, 0, 32; + %pushi/vec4 4294967294, 0, 32; + %store/vec4 v0000000002790b60_0, 0, 32; + %pushi/vec4 0, 0, 3; + %store/vec4 v0000000002790a20_0, 0, 3; + %delay 10000000, 0; + %vpi_call 3 50 "$display", "| %b | %b | ADD | %b | 11111111111111111111111111111100 | %b | 1 | %b | 0 | %b | 0 |", v0000000002790660_0, v0000000002790b60_0, v0000000002791ec0_0, v0000000002791920_0, v0000000002792320_0, v0000000002790700_0 {0 0 0}; + %vpi_call 3 51 "$display", "-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------" {0 0 0}; + %vpi_call 3 53 "$display", "SUB COMMAND -----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------" {0 0 0}; + %pushi/vec4 5, 0, 32; + %store/vec4 v0000000002790660_0, 0, 32; + %pushi/vec4 3, 0, 32; + %store/vec4 v0000000002790b60_0, 0, 32; + %pushi/vec4 1, 0, 3; + %store/vec4 v0000000002790a20_0, 0, 3; + %delay 10000000, 0; + %vpi_call 3 57 "$display", "| %b | %b | SUB | %b | 00000000000000000000000000000010 | %b | 1 | %b | 0 | %b | 0 |", v0000000002790660_0, v0000000002790b60_0, v0000000002791ec0_0, v0000000002791920_0, v0000000002792320_0, v0000000002790700_0 {0 0 0}; + %pushi/vec4 4294957396, 0, 32; + %store/vec4 v0000000002790660_0, 0, 32; + %pushi/vec4 2147483000, 0, 32; + %store/vec4 v0000000002790b60_0, 0, 32; + %pushi/vec4 1, 0, 3; + %store/vec4 v0000000002790a20_0, 0, 3; + %delay 10000000, 0; + %vpi_call 3 61 "$display", "| %b | %b | SUB | %b | 11111111111111111111111110110000 | %b | 1 | %b | 1 | %b | 0 |", v0000000002790660_0, v0000000002790b60_0, v0000000002791ec0_0, v0000000002791920_0, v0000000002792320_0, v0000000002790700_0 {0 0 0}; + %pushi/vec4 2, 0, 32; + %store/vec4 v0000000002790660_0, 0, 32; + %pushi/vec4 4294967291, 0, 32; + %store/vec4 v0000000002790b60_0, 0, 32; + %pushi/vec4 1, 0, 3; + %store/vec4 v0000000002790a20_0, 0, 3; + %delay 10000000, 0; + %vpi_call 3 65 "$display", "| %b | %b | SUB | %b | 00000000000000000000000000000111 | %b | 0 | %b | 0 | %b | 0 |", v0000000002790660_0, v0000000002790b60_0, v0000000002791ec0_0, v0000000002791920_0, v0000000002792320_0, v0000000002790700_0 {0 0 0}; + %pushi/vec4 4294967096, 0, 32; + %store/vec4 v0000000002790660_0, 0, 32; + %pushi/vec4 4294967096, 0, 32; + %store/vec4 v0000000002790b60_0, 0, 32; + %pushi/vec4 1, 0, 3; + %store/vec4 v0000000002790a20_0, 0, 3; + %delay 10000000, 0; + %vpi_call 3 69 "$display", "| %b | %b | SUB | %b | 00000000000000000000000000000000 | %b | 1 | %b | 0 | %b | 1 |", v0000000002790660_0, v0000000002790b60_0, v0000000002791ec0_0, v0000000002791920_0, v0000000002792320_0, v0000000002790700_0 {0 0 0}; + %pushi/vec4 2, 0, 32; + %store/vec4 v0000000002790660_0, 0, 32; + %pushi/vec4 5, 0, 32; + %store/vec4 v0000000002790b60_0, 0, 32; + %pushi/vec4 1, 0, 3; + %store/vec4 v0000000002790a20_0, 0, 3; + %delay 10000000, 0; + %vpi_call 3 73 "$display", "| %b | %b | SUB | %b | 11111111111111111111111111111101 | %b | 0 | %b | 0 | %b | 0 |", v0000000002790660_0, v0000000002790b60_0, v0000000002791ec0_0, v0000000002791920_0, v0000000002792320_0, v0000000002790700_0 {0 0 0}; + %vpi_call 3 74 "$display", "-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------" {0 0 0}; + %vpi_call 3 76 "$display", "XOR COMMAND -----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------" {0 0 0}; + %pushi/vec4 773499565, 0, 32; + %store/vec4 v0000000002790660_0, 0, 32; + %pushi/vec4 2860817687, 0, 32; + %store/vec4 v0000000002790b60_0, 0, 32; + %pushi/vec4 2, 0, 3; + %store/vec4 v0000000002790a20_0, 0, 3; + %delay 10000000, 0; + %vpi_call 3 80 "$display", "| %b | %b | XOR | %b | 10000100100111100011011110111010 | %b | 0 | %b | 0 | %b | 0 |", v0000000002790660_0, v0000000002790b60_0, v0000000002791ec0_0, v0000000002791920_0, v0000000002792320_0, v0000000002790700_0 {0 0 0}; + %pushi/vec4 4294962296, 0, 32; + %store/vec4 v0000000002790660_0, 0, 32; + %pushi/vec4 123123, 0, 32; + %store/vec4 v0000000002790b60_0, 0, 32; + %pushi/vec4 2, 0, 3; + %store/vec4 v0000000002790a20_0, 0, 3; + %delay 10000000, 0; + %vpi_call 3 84 "$display", "| %b | %b | XOR | %b | 11111111111111100000110010001011 | %b | 0 | %b | 0 | %b | 0 |", v0000000002790660_0, v0000000002790b60_0, v0000000002791ec0_0, v0000000002791920_0, v0000000002792320_0, v0000000002790700_0 {0 0 0}; + %pushi/vec4 332, 0, 32; + %store/vec4 v0000000002790660_0, 0, 32; + %pushi/vec4 4294965173, 0, 32; + %store/vec4 v0000000002790b60_0, 0, 32; + %pushi/vec4 2, 0, 3; + %store/vec4 v0000000002790a20_0, 0, 3; + %delay 10000000, 0; + %vpi_call 3 88 "$display", "| %b | %b | XOR | %b | 11111111111111111111011011111001 | %b | 0 | %b | 0 | %b | 0 |", v0000000002790660_0, v0000000002790b60_0, v0000000002791ec0_0, v0000000002791920_0, v0000000002792320_0, v0000000002790700_0 {0 0 0}; + %pushi/vec4 0, 0, 32; + %store/vec4 v0000000002790660_0, 0, 32; + %pushi/vec4 0, 0, 32; + %store/vec4 v0000000002790b60_0, 0, 32; + %pushi/vec4 2, 0, 3; + %store/vec4 v0000000002790a20_0, 0, 3; + %delay 10000000, 0; + %vpi_call 3 92 "$display", "| %b | %b | XOR | %b | 00000000000000000000000000000000 | %b | 0 | %b | 0 | %b | 0 |", v0000000002790660_0, v0000000002790b60_0, v0000000002791ec0_0, v0000000002791920_0, v0000000002792320_0, v0000000002790700_0 {0 0 0}; + %pushi/vec4 4294074932, 0, 32; + %store/vec4 v0000000002790660_0, 0, 32; + %pushi/vec4 4294962311, 0, 32; + %store/vec4 v0000000002790b60_0, 0, 32; + %pushi/vec4 2, 0, 3; + %store/vec4 v0000000002790a20_0, 0, 3; + %delay 10000000, 0; + %vpi_call 3 96 "$display", "| %b | %b | XOR | %b | 00000000000011011000111010110011 | %b | 0 | %b | 0 | %b | 0 |", v0000000002790660_0, v0000000002790b60_0, v0000000002791ec0_0, v0000000002791920_0, v0000000002792320_0, v0000000002790700_0 {0 0 0}; + %vpi_call 3 97 "$display", "-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------" {0 0 0}; + %vpi_call 3 99 "$display", "SLT COMMAND -----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------" {0 0 0}; + %pushi/vec4 3320106349, 0, 32; + %store/vec4 v0000000002790660_0, 0, 32; + %pushi/vec4 626512242, 0, 32; + %store/vec4 v0000000002790b60_0, 0, 32; + %pushi/vec4 3, 0, 3; + %store/vec4 v0000000002790a20_0, 0, 3; + %delay 10000000, 0; + %vpi_call 3 103 "$display", "| %b | %b | SLT | %b | 00000000000000000000000000000001 | %b | 0 | %b | 0 | %b | 0 |", v0000000002790660_0, v0000000002790b60_0, v0000000002791ec0_0, v0000000002791920_0, v0000000002792320_0, v0000000002790700_0 {0 0 0}; + %pushi/vec4 4294962296, 0, 32; + %store/vec4 v0000000002790660_0, 0, 32; + %pushi/vec4 123123, 0, 32; + %store/vec4 v0000000002790b60_0, 0, 32; + %pushi/vec4 3, 0, 3; + %store/vec4 v0000000002790a20_0, 0, 3; + %delay 10000000, 0; + %vpi_call 3 107 "$display", "| %b | %b | SLT | %b | 00000000000000000000000000000001 | %b | 0 | %b | 0 | %b | 0 |", v0000000002790660_0, v0000000002790b60_0, v0000000002791ec0_0, v0000000002791920_0, v0000000002792320_0, v0000000002790700_0 {0 0 0}; + %pushi/vec4 332, 0, 32; + %store/vec4 v0000000002790660_0, 0, 32; + %pushi/vec4 4294965173, 0, 32; + %store/vec4 v0000000002790b60_0, 0, 32; + %pushi/vec4 3, 0, 3; + %store/vec4 v0000000002790a20_0, 0, 3; + %delay 10000000, 0; + %vpi_call 3 111 "$display", "| %b | %b | SLT | %b | 00000000000000000000000000000000 | %b | 0 | %b | 0 | %b | 0 |", v0000000002790660_0, v0000000002790b60_0, v0000000002791ec0_0, v0000000002791920_0, v0000000002792320_0, v0000000002790700_0 {0 0 0}; + %pushi/vec4 0, 0, 32; + %store/vec4 v0000000002790660_0, 0, 32; + %pushi/vec4 0, 0, 32; + %store/vec4 v0000000002790b60_0, 0, 32; + %pushi/vec4 3, 0, 3; + %store/vec4 v0000000002790a20_0, 0, 3; + %delay 10000000, 0; + %vpi_call 3 115 "$display", "| %b | %b | SLT | %b | 00000000000000000000000000000000 | %b | 0 | %b | 0 | %b | 0 |", v0000000002790660_0, v0000000002790b60_0, v0000000002791ec0_0, v0000000002791920_0, v0000000002792320_0, v0000000002790700_0 {0 0 0}; + %pushi/vec4 4294074932, 0, 32; + %store/vec4 v0000000002790660_0, 0, 32; + %pushi/vec4 4294962311, 0, 32; + %store/vec4 v0000000002790b60_0, 0, 32; + %pushi/vec4 3, 0, 3; + %store/vec4 v0000000002790a20_0, 0, 3; + %delay 10000000, 0; + %vpi_call 3 119 "$display", "| %b | %b | SLT | %b | 00000000000000000000000000000001 | %b | 0 | %b | 0 | %b | 0 |", v0000000002790660_0, v0000000002790b60_0, v0000000002791ec0_0, v0000000002791920_0, v0000000002792320_0, v0000000002790700_0 {0 0 0}; + %vpi_call 3 120 "$display", "-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------" {0 0 0}; + %vpi_call 3 122 "$display", "AND COMMAND -----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------" {0 0 0}; + %pushi/vec4 3320106349, 0, 32; + %store/vec4 v0000000002790660_0, 0, 32; + %pushi/vec4 626512242, 0, 32; + %store/vec4 v0000000002790b60_0, 0, 32; + %pushi/vec4 4, 0, 3; + %store/vec4 v0000000002790a20_0, 0, 3; + %delay 10000000, 0; + %vpi_call 3 126 "$display", "| %b | %b | AND | %b | 00000101010001001100000101100000 | %b | 0 | %b | 0 | %b | 0 |", v0000000002790660_0, v0000000002790b60_0, v0000000002791ec0_0, v0000000002791920_0, v0000000002792320_0, v0000000002790700_0 {0 0 0}; + %pushi/vec4 4294954993, 0, 32; + %store/vec4 v0000000002790660_0, 0, 32; + %pushi/vec4 222, 0, 32; + %store/vec4 v0000000002790b60_0, 0, 32; + %pushi/vec4 4, 0, 3; + %store/vec4 v0000000002790a20_0, 0, 3; + %delay 10000000, 0; + %vpi_call 3 130 "$display", "| %b | %b | AND | %b | 00000000000000000000000011010000 | %b | 0 | %b | 0 | %b | 0 |", v0000000002790660_0, v0000000002790b60_0, v0000000002791ec0_0, v0000000002791920_0, v0000000002792320_0, v0000000002790700_0 {0 0 0}; + %pushi/vec4 9732, 0, 32; + %store/vec4 v0000000002790660_0, 0, 32; + %pushi/vec4 4294921673, 0, 32; + %store/vec4 v0000000002790b60_0, 0, 32; + %pushi/vec4 4, 0, 3; + %store/vec4 v0000000002790a20_0, 0, 3; + %delay 10000000, 0; + %vpi_call 3 134 "$display", "| %b | %b | AND | %b | 00000000000000000000010000000000 | %b | 0 | %b | 0 | %b | 0 |", v0000000002790660_0, v0000000002790b60_0, v0000000002791ec0_0, v0000000002791920_0, v0000000002792320_0, v0000000002790700_0 {0 0 0}; + %pushi/vec4 0, 0, 32; + %store/vec4 v0000000002790660_0, 0, 32; + %pushi/vec4 0, 0, 32; + %store/vec4 v0000000002790b60_0, 0, 32; + %pushi/vec4 4, 0, 3; + %store/vec4 v0000000002790a20_0, 0, 3; + %delay 10000000, 0; + %vpi_call 3 138 "$display", "| %b | %b | AND | %b | 00000000000000000000000000000000 | %b | 0 | %b | 0 | %b | 0 |", v0000000002790660_0, v0000000002790b60_0, v0000000002791ec0_0, v0000000002791920_0, v0000000002792320_0, v0000000002790700_0 {0 0 0}; + %pushi/vec4 4294967062, 0, 32; + %store/vec4 v0000000002790660_0, 0, 32; + %pushi/vec4 4294962311, 0, 32; + %store/vec4 v0000000002790b60_0, 0, 32; + %pushi/vec4 4, 0, 3; + %store/vec4 v0000000002790a20_0, 0, 3; + %delay 10000000, 0; + %vpi_call 3 142 "$display", "| %b | %b | AND | %b | 11111111111111111110110000000110 | %b | 0 | %b | 0 | %b | 0 |", v0000000002790660_0, v0000000002790b60_0, v0000000002791ec0_0, v0000000002791920_0, v0000000002792320_0, v0000000002790700_0 {0 0 0}; + %vpi_call 3 143 "$display", "-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------" {0 0 0}; + %vpi_call 3 145 "$display", "NAND COMMAND ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------" {0 0 0}; + %pushi/vec4 950744538, 0, 32; + %store/vec4 v0000000002790660_0, 0, 32; + %pushi/vec4 2466067877, 0, 32; + %store/vec4 v0000000002790b60_0, 0, 32; + %pushi/vec4 5, 0, 3; + %store/vec4 v0000000002790a20_0, 0, 3; + %delay 10000000, 0; + %vpi_call 3 149 "$display", "| %b | %b | NAND | %b | 11101111010101101100101001111111 | %b | 0 | %b | 0 | %b | 0 |", v0000000002790660_0, v0000000002790b60_0, v0000000002791ec0_0, v0000000002791920_0, v0000000002792320_0, v0000000002790700_0 {0 0 0}; + %pushi/vec4 4294868203, 0, 32; + %store/vec4 v0000000002790660_0, 0, 32; + %pushi/vec4 222, 0, 32; + %store/vec4 v0000000002790b60_0, 0, 32; + %pushi/vec4 5, 0, 3; + %store/vec4 v0000000002790a20_0, 0, 3; + %delay 10000000, 0; + %vpi_call 3 153 "$display", "| %b | %b | NAND | %b | 11111111111111111111111100110101 | %b | 0 | %b | 0 | %b | 0 |", v0000000002790660_0, v0000000002790b60_0, v0000000002791ec0_0, v0000000002791920_0, v0000000002792320_0, v0000000002790700_0 {0 0 0}; + %pushi/vec4 122, 0, 32; + %store/vec4 v0000000002790660_0, 0, 32; + %pushi/vec4 4293967398, 0, 32; + %store/vec4 v0000000002790b60_0, 0, 32; + %pushi/vec4 5, 0, 3; + %store/vec4 v0000000002790a20_0, 0, 3; + %delay 10000000, 0; + %vpi_call 3 157 "$display", "| %b | %b | NAND | %b | 11111111111111111111111111011101 | %b | 0 | %b | 0 | %b | 0 |", v0000000002790660_0, v0000000002790b60_0, v0000000002791ec0_0, v0000000002791920_0, v0000000002792320_0, v0000000002790700_0 {0 0 0}; + %pushi/vec4 0, 0, 32; + %store/vec4 v0000000002790660_0, 0, 32; + %pushi/vec4 0, 0, 32; + %store/vec4 v0000000002790b60_0, 0, 32; + %pushi/vec4 5, 0, 3; + %store/vec4 v0000000002790a20_0, 0, 3; + %delay 10000000, 0; + %vpi_call 3 161 "$display", "| %b | %b | NAND | %b | 11111111111111111111111111111111 | %b | 0 | %b | 0 | %b | 0 |", v0000000002790660_0, v0000000002790b60_0, v0000000002791ec0_0, v0000000002791920_0, v0000000002792320_0, v0000000002790700_0 {0 0 0}; + %pushi/vec4 4294957297, 0, 32; + %store/vec4 v0000000002790660_0, 0, 32; + %pushi/vec4 4294967294, 0, 32; + %store/vec4 v0000000002790b60_0, 0, 32; + %pushi/vec4 5, 0, 3; + %store/vec4 v0000000002790a20_0, 0, 3; + %delay 10000000, 0; + %vpi_call 3 165 "$display", "| %b | %b | NAND | %b | 00000000000000000010011100001111 | %b | 0 | %b | 0 | %b | 0 |", v0000000002790660_0, v0000000002790b60_0, v0000000002791ec0_0, v0000000002791920_0, v0000000002792320_0, v0000000002790700_0 {0 0 0}; + %vpi_call 3 166 "$display", "-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------" {0 0 0}; + %vpi_call 3 168 "$display", "NOR COMMAND -----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------" {0 0 0}; + %pushi/vec4 3443074421, 0, 32; + %store/vec4 v0000000002790660_0, 0, 32; + %pushi/vec4 3849243493, 0, 32; + %store/vec4 v0000000002790b60_0, 0, 32; + %pushi/vec4 6, 0, 3; + %store/vec4 v0000000002790a20_0, 0, 3; + %delay 10000000, 0; + %vpi_call 3 172 "$display", "| %b | %b | NOR | %b | 00010010100000000001000010001010 | %b | 0 | %b | 0 | %b | 0 |", v0000000002790660_0, v0000000002790b60_0, v0000000002791ec0_0, v0000000002791920_0, v0000000002792320_0, v0000000002790700_0 {0 0 0}; + %pushi/vec4 4294844173, 0, 32; + %store/vec4 v0000000002790660_0, 0, 32; + %pushi/vec4 9882, 0, 32; + %store/vec4 v0000000002790b60_0, 0, 32; + %pushi/vec4 6, 0, 3; + %store/vec4 v0000000002790a20_0, 0, 3; + %delay 10000000, 0; + %vpi_call 3 176 "$display", "| %b | %b | NOR | %b | 00000000000000011100000001100000 | %b | 0 | %b | 0 | %b | 0 |", v0000000002790660_0, v0000000002790b60_0, v0000000002791ec0_0, v0000000002791920_0, v0000000002792320_0, v0000000002790700_0 {0 0 0}; + %pushi/vec4 2, 0, 32; + %store/vec4 v0000000002790660_0, 0, 32; + %pushi/vec4 4294967290, 0, 32; + %store/vec4 v0000000002790b60_0, 0, 32; + %pushi/vec4 6, 0, 3; + %store/vec4 v0000000002790a20_0, 0, 3; + %delay 10000000, 0; + %vpi_call 3 180 "$display", "| %b | %b | NOR | %b | 00000000000000000000000000000101 | %b | 0 | %b | 0 | %b | 0 |", v0000000002790660_0, v0000000002790b60_0, v0000000002791ec0_0, v0000000002791920_0, v0000000002792320_0, v0000000002790700_0 {0 0 0}; + %pushi/vec4 0, 0, 32; + %store/vec4 v0000000002790660_0, 0, 32; + %pushi/vec4 0, 0, 32; + %store/vec4 v0000000002790b60_0, 0, 32; + %pushi/vec4 6, 0, 3; + %store/vec4 v0000000002790a20_0, 0, 3; + %delay 10000000, 0; + %vpi_call 3 184 "$display", "| %b | %b | NOR | %b | 11111111111111111111111111111111 | %b | 0 | %b | 0 | %b | 0 |", v0000000002790660_0, v0000000002790b60_0, v0000000002791ec0_0, v0000000002791920_0, v0000000002792320_0, v0000000002790700_0 {0 0 0}; + %pushi/vec4 4294844173, 0, 32; + %store/vec4 v0000000002790660_0, 0, 32; + %pushi/vec4 4294967197, 0, 32; + %store/vec4 v0000000002790b60_0, 0, 32; + %pushi/vec4 6, 0, 3; + %store/vec4 v0000000002790a20_0, 0, 3; + %delay 10000000, 0; + %vpi_call 3 188 "$display", "| %b | %b | NOR | %b | 00000000000000000000000001100010 | %b | 0 | %b | 0 | %b | 0 |", v0000000002790660_0, v0000000002790b60_0, v0000000002791ec0_0, v0000000002791920_0, v0000000002792320_0, v0000000002790700_0 {0 0 0}; + %vpi_call 3 189 "$display", "-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------" {0 0 0}; + %vpi_call 3 191 "$display", "OR COMMAND ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------" {0 0 0}; + %pushi/vec4 886281674, 0, 32; + %store/vec4 v0000000002790660_0, 0, 32; + %pushi/vec4 3375262922, 0, 32; + %store/vec4 v0000000002790b60_0, 0, 32; + %pushi/vec4 7, 0, 3; + %store/vec4 v0000000002790a20_0, 0, 3; + %delay 10000000, 0; + %vpi_call 3 195 "$display", "| %b | %b | OR | %b | 11111101111111111111110111001010 | %b | 0 | %b | 0 | %b | 0 |", v0000000002790660_0, v0000000002790b60_0, v0000000002791ec0_0, v0000000002791920_0, v0000000002792320_0, v0000000002790700_0 {0 0 0}; + %pushi/vec4 4204159197, 0, 32; + %store/vec4 v0000000002790660_0, 0, 32; + %pushi/vec4 1239, 0, 32; + %store/vec4 v0000000002790b60_0, 0, 32; + %pushi/vec4 7, 0, 3; + %store/vec4 v0000000002790a20_0, 0, 3; + %delay 10000000, 0; + %vpi_call 3 199 "$display", "| %b | %b | OR | %b | 11111010100101100110010011011111 | %b | 0 | %b | 0 | %b | 0 |", v0000000002790660_0, v0000000002790b60_0, v0000000002791ec0_0, v0000000002791920_0, v0000000002792320_0, v0000000002790700_0 {0 0 0}; + %pushi/vec4 90, 0, 32; + %store/vec4 v0000000002790660_0, 0, 32; + %pushi/vec4 4294966204, 0, 32; + %store/vec4 v0000000002790b60_0, 0, 32; + %pushi/vec4 7, 0, 3; + %store/vec4 v0000000002790a20_0, 0, 3; + %delay 10000000, 0; + %vpi_call 3 203 "$display", "| %b | %b | OR | %b | 11111111111111111111101111111110 | %b | 0 | %b | 0 | %b | 0 |", v0000000002790660_0, v0000000002790b60_0, v0000000002791ec0_0, v0000000002791920_0, v0000000002792320_0, v0000000002790700_0 {0 0 0}; + %pushi/vec4 0, 0, 32; + %store/vec4 v0000000002790660_0, 0, 32; + %pushi/vec4 0, 0, 32; + %store/vec4 v0000000002790b60_0, 0, 32; + %pushi/vec4 7, 0, 3; + %store/vec4 v0000000002790a20_0, 0, 3; + %delay 10000000, 0; + %vpi_call 3 207 "$display", "| %b | %b | OR | %b | 00000000000000000000000000000000 | %b | 0 | %b | 0 | %b | 0 |", v0000000002790660_0, v0000000002790b60_0, v0000000002791ec0_0, v0000000002791920_0, v0000000002792320_0, v0000000002790700_0 {0 0 0}; + %pushi/vec4 4274975084, 0, 32; + %store/vec4 v0000000002790660_0, 0, 32; + %pushi/vec4 4294957469, 0, 32; + %store/vec4 v0000000002790b60_0, 0, 32; + %pushi/vec4 7, 0, 3; + %store/vec4 v0000000002790a20_0, 0, 3; + %delay 10000000, 0; + %vpi_call 3 211 "$display", "| %b | %b | OR | %b | 11111111111111111111100111111101 | %b | 0 | %b | 0 | %b | 0 |", v0000000002790660_0, v0000000002790b60_0, v0000000002791ec0_0, v0000000002791920_0, v0000000002792320_0, v0000000002790700_0 {0 0 0}; + %vpi_call 3 212 "$display", "-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------" {0 0 0}; + %end; + .thread T_1; +# The file index is used to find the file name in the following table. +:file_names 9; + "N/A"; + ""; + "./adder.v"; + "alu.t.v"; + "./alu.v"; + "./aluFullBit.v"; + "./aluBit.v"; + "./mux.v"; + "./lut.v"; diff --git a/alu.t.v b/alu.t.v new file mode 100644 index 0000000..1fb1aba --- /dev/null +++ b/alu.t.v @@ -0,0 +1,216 @@ +// 32-bit alu testbench + +`timescale 1 ns / 1 ps +`include "alu.v" + +`define ADD 3'd0 +`define SUB 3'd1 +`define XOR 3'd2 +`define SLT 3'd3 +`define AND 3'd4 +`define NAND 3'd5 +`define NOR 3'd6 +`define OR 3'd7 + +module testALU(); + + reg signed [31:0] operandA; + reg signed [31:0] operandB; + reg[2:0] command; + + wire signed [31:0] result; + wire carryout, zero, overflow; + + ALU alu(result, carryout, zero, overflow, operandA, operandB, command); + + initial begin + + $display(" operandA | operandB | cmd | result | eResult | cOut | eCOut | Overflow | eOverflow | Zero | eZero"); + $display(); + $display("ADD COMMAND -----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------"); + // 2000 + 2147483000 = + operandA=32'd2000;operandB=32'd2147483000;command=`ADD; + #10000; + $display("| %b | %b | ADD | %b | 10000000000000000000010101001000 | %b | 0 | %b | 1 | %b | 0 |", operandA, operandB, result, carryout, overflow, zero); + // -30 + 50 = 20 + operandA=-32'd30;operandB=32'd50;command=`ADD; + #10000; + $display("| %b | %b | ADD | %b | 00000000000000000000000000010100 | %b | 1 | %b | 0 | %b | 0 |", operandA, operandB, result, carryout, overflow, zero); + // 2 + (-5) = -3 + operandA=32'd2;operandB=-32'd5;command=`ADD; + #10000; + $display("| %b | %b | ADD | %b | 11111111111111111111111111111101 | %b | 0 | %b | 0 | %b | 0 |", operandA, operandB, result, carryout, overflow, zero); + // -200 + 200 = 0 + operandA=-32'd200;operandB=32'd200;command=`ADD; + #10000; + $display("| %b | %b | ADD | %b | 00000000000000000000000000000000 | %b | 1 | %b | 0 | %b | 1 |", operandA, operandB, result, carryout, overflow, zero); + // -2 + (-2) = -4 + operandA=-32'd2;operandB=-32'd2;command=`ADD; + #10000; + $display("| %b | %b | ADD | %b | 11111111111111111111111111111100 | %b | 1 | %b | 0 | %b | 0 |", operandA, operandB, result, carryout, overflow, zero); + $display("-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------"); + + $display("SUB COMMAND -----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------"); + // 5 - 3 = 2 + operandA=32'd5;operandB=32'd3;command=`SUB; + #10000; + $display("| %b | %b | SUB | %b | 00000000000000000000000000000010 | %b | 1 | %b | 0 | %b | 0 |", operandA, operandB, result, carryout, overflow, zero); + // -9900 - 2147483000 = + operandA=-32'd9900;operandB=32'd2147483000;command=`SUB; + #10000; + $display("| %b | %b | SUB | %b | 11111111111111111111111110110000 | %b | 1 | %b | 1 | %b | 0 |", operandA, operandB, result, carryout, overflow, zero); + // 2 - (-5) = 7 + operandA=32'd2;operandB=-32'd5;command=`SUB; + #10000; + $display("| %b | %b | SUB | %b | 00000000000000000000000000000111 | %b | 0 | %b | 0 | %b | 0 |", operandA, operandB, result, carryout, overflow, zero); + // -200 - (-200) = 0 + operandA=-32'd200;operandB=-32'd200;command=`SUB; + #10000; + $display("| %b | %b | SUB | %b | 00000000000000000000000000000000 | %b | 1 | %b | 0 | %b | 1 |", operandA, operandB, result, carryout, overflow, zero); + // 2 - 5 = -3 + operandA=32'd2;operandB=32'd5;command=`SUB; + #10000; + $display("| %b | %b | SUB | %b | 11111111111111111111111111111101 | %b | 0 | %b | 0 | %b | 0 |", operandA, operandB, result, carryout, overflow, zero); + $display("-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------"); + + $display("XOR COMMAND -----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------"); + // + operandA=32'b00101110000110101010101010101101;operandB=32'b10101010100001001001110100010111;command=`XOR; + #10000; + $display("| %b | %b | XOR | %b | 10000100100111100011011110111010 | %b | 0 | %b | 0 | %b | 0 |", operandA, operandB, result, carryout, overflow, zero); + // + operandA=-32'd5000;operandB=32'd123123;command=`XOR; + #10000; + $display("| %b | %b | XOR | %b | 11111111111111100000110010001011 | %b | 0 | %b | 0 | %b | 0 |", operandA, operandB, result, carryout, overflow, zero); + // + operandA=32'd332;operandB=-32'd2123;command=`XOR; + #10000; + $display("| %b | %b | XOR | %b | 11111111111111111111011011111001 | %b | 0 | %b | 0 | %b | 0 |", operandA, operandB, result, carryout, overflow, zero); + // + operandA=32'd0;operandB=32'd0;command=`XOR; + #10000; + $display("| %b | %b | XOR | %b | 00000000000000000000000000000000 | %b | 0 | %b | 0 | %b | 0 |", operandA, operandB, result, carryout, overflow, zero); + // + operandA=-32'd892364;operandB=-32'd4985;command=`XOR; + #10000; + $display("| %b | %b | XOR | %b | 00000000000011011000111010110011 | %b | 0 | %b | 0 | %b | 0 |", operandA, operandB, result, carryout, overflow, zero); + $display("-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------"); + + $display("SLT COMMAND -----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------"); +// + operandA=32'b11000101111001001100110101101101;operandB=32'b00100101010101111101000101110010;command=`SLT; + #10000; + $display("| %b | %b | SLT | %b | 00000000000000000000000000000001 | %b | 0 | %b | 0 | %b | 0 |", operandA, operandB, result, carryout, overflow, zero); +// + operandA=-32'd5000;operandB=32'd123123;command=`SLT; + #10000; + $display("| %b | %b | SLT | %b | 00000000000000000000000000000001 | %b | 0 | %b | 0 | %b | 0 |", operandA, operandB, result, carryout, overflow, zero); +// + operandA=32'd332;operandB=-32'd2123;command=`SLT; + #10000; + $display("| %b | %b | SLT | %b | 00000000000000000000000000000000 | %b | 0 | %b | 0 | %b | 0 |", operandA, operandB, result, carryout, overflow, zero); +// + operandA=32'd0;operandB=32'd0;command=`SLT; + #10000; + $display("| %b | %b | SLT | %b | 00000000000000000000000000000000 | %b | 0 | %b | 0 | %b | 0 |", operandA, operandB, result, carryout, overflow, zero); +// + operandA=-32'd892364;operandB=-32'd4985;command=`SLT; + #10000; + $display("| %b | %b | SLT | %b | 00000000000000000000000000000001 | %b | 0 | %b | 0 | %b | 0 |", operandA, operandB, result, carryout, overflow, zero); + $display("-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------"); + + $display("AND COMMAND -----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------"); +// + operandA=32'b11000101111001001100110101101101;operandB=32'b00100101010101111101000101110010;command=`AND; + #10000; + $display("| %b | %b | AND | %b | 00000101010001001100000101100000 | %b | 0 | %b | 0 | %b | 0 |", operandA, operandB, result, carryout, overflow, zero); +// + operandA=-32'd12303;operandB=32'd222;command=`AND; + #10000; + $display("| %b | %b | AND | %b | 00000000000000000000000011010000 | %b | 0 | %b | 0 | %b | 0 |", operandA, operandB, result, carryout, overflow, zero); +// + operandA=32'd9732;operandB=-32'd45623;command=`AND; + #10000; + $display("| %b | %b | AND | %b | 00000000000000000000010000000000 | %b | 0 | %b | 0 | %b | 0 |", operandA, operandB, result, carryout, overflow, zero); +// + operandA=32'd0;operandB=32'd0;command=`AND; + #10000; + $display("| %b | %b | AND | %b | 00000000000000000000000000000000 | %b | 0 | %b | 0 | %b | 0 |", operandA, operandB, result, carryout, overflow, zero); +// + operandA=-32'd234;operandB=-32'd4985;command=`AND; + #10000; + $display("| %b | %b | AND | %b | 11111111111111111110110000000110 | %b | 0 | %b | 0 | %b | 0 |", operandA, operandB, result, carryout, overflow, zero); + $display("-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------"); + + $display("NAND COMMAND ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------"); +// + operandA=32'b00111000101010110011010111011010;operandB=32'b10010010111111010011010110100101;command=`NAND; + #10000; + $display("| %b | %b | NAND | %b | 11101111010101101100101001111111 | %b | 0 | %b | 0 | %b | 0 |", operandA, operandB, result, carryout, overflow, zero); +// + operandA=-32'd99093;operandB=32'd222;command=`NAND; + #10000; + $display("| %b | %b | NAND | %b | 11111111111111111111111100110101 | %b | 0 | %b | 0 | %b | 0 |", operandA, operandB, result, carryout, overflow, zero); +// + operandA=32'd122;operandB=-32'd999898;command=`NAND; + #10000; + $display("| %b | %b | NAND | %b | 11111111111111111111111111011101 | %b | 0 | %b | 0 | %b | 0 |", operandA, operandB, result, carryout, overflow, zero); +// + operandA=32'd0;operandB=32'd0;command=`NAND; + #10000; + $display("| %b | %b | NAND | %b | 11111111111111111111111111111111 | %b | 0 | %b | 0 | %b | 0 |", operandA, operandB, result, carryout, overflow, zero); +// + operandA=-32'd9999;operandB=-32'd2;command=`NAND; + #10000; + $display("| %b | %b | NAND | %b | 00000000000000000010011100001111 | %b | 0 | %b | 0 | %b | 0 |", operandA, operandB, result, carryout, overflow, zero); + $display("-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------"); + + $display("NOR COMMAND -----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------"); +// + operandA=32'b11001101001110010010010101110101;operandB=32'b11100101011011101100101101100101;command=`NOR; + #10000; + $display("| %b | %b | NOR | %b | 00010010100000000001000010001010 | %b | 0 | %b | 0 | %b | 0 |", operandA, operandB, result, carryout, overflow, zero); +// + operandA=-32'd123123;operandB=32'd9882;command=`NOR; + #10000; + $display("| %b | %b | NOR | %b | 00000000000000011100000001100000 | %b | 0 | %b | 0 | %b | 0 |", operandA, operandB, result, carryout, overflow, zero); +// + operandA=32'd2;operandB=-32'd6;command=`NOR; + #10000; + $display("| %b | %b | NOR | %b | 00000000000000000000000000000101 | %b | 0 | %b | 0 | %b | 0 |", operandA, operandB, result, carryout, overflow, zero); +// + operandA=32'd0;operandB=32'd0;command=`NOR; + #10000; + $display("| %b | %b | NOR | %b | 11111111111111111111111111111111 | %b | 0 | %b | 0 | %b | 0 |", operandA, operandB, result, carryout, overflow, zero); +// + operandA=-32'd123123;operandB=-32'd99;command=`NOR; + #10000; + $display("| %b | %b | NOR | %b | 00000000000000000000000001100010 | %b | 0 | %b | 0 | %b | 0 |", operandA, operandB, result, carryout, overflow, zero); + $display("-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------"); + + $display("OR COMMAND ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------"); +// + operandA=32'b00110100110100111001010111001010;operandB=32'b11001001001011100110110011001010;command=`OR; + #10000; + $display("| %b | %b | OR | %b | 11111101111111111111110111001010 | %b | 0 | %b | 0 | %b | 0 |", operandA, operandB, result, carryout, overflow, zero); +// + operandA=-32'd90808099;operandB=32'd1239;command=`OR; + #10000; + $display("| %b | %b | OR | %b | 11111010100101100110010011011111 | %b | 0 | %b | 0 | %b | 0 |", operandA, operandB, result, carryout, overflow, zero); +// + operandA=32'd90;operandB=-32'd1092;command=`OR; + #10000; + $display("| %b | %b | OR | %b | 11111111111111111111101111111110 | %b | 0 | %b | 0 | %b | 0 |", operandA, operandB, result, carryout, overflow, zero); +// + operandA=32'd0;operandB=32'd0;command=`OR; + #10000; + $display("| %b | %b | OR | %b | 00000000000000000000000000000000 | %b | 0 | %b | 0 | %b | 0 |", operandA, operandB, result, carryout, overflow, zero); +// + operandA=-32'd19992212;operandB=-32'd9827;command=`OR; + #10000; + $display("| %b | %b | OR | %b | 11111111111111111111100111111101 | %b | 0 | %b | 0 | %b | 0 |", operandA, operandB, result, carryout, overflow, zero); + $display("-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------"); + end + +endmodule + diff --git a/alu.v b/alu.v new file mode 100644 index 0000000..a00155c --- /dev/null +++ b/alu.v @@ -0,0 +1,83 @@ +`include "adder.v" +`include "lut.v" +`include "aluFullBit.v" + +// Define gates and timings. +`define AND and #30 +`define OR or #30 +`define NOT not #10 +`define XOR xor #20 +`define NAND nand #20 +`define NOR nor #20 + + +module ALU +( +output[31:0] result, +output carryout, +output zero, +output overflow, +input[31:0] operandA, +input[31:0] operandB, +input[2:0] command +); + +wire [31:0] operandA, operandB, finalB, partialResult, result, cIn, cOut; +wire [2:0] command; +wire [1:0] select; + +wire nSltFlag; +wire sltFlag; +wire aLessB; +wire [1:0]nCommand; +wire partialResult2; +wire finalSlt; + +ALULut _lut(select[1:0], invert, carry, command[2:0]); + +`XOR (finalB[0], operandB[0], invert); +`AND (cIn[0], carry, command[0]); + +`NOT (nCommand[1], command[2]); +nand #30 (nSltFlag, command[0], command[1], nCommand[1]); +`NOT (sltFlag, nSltFlag); + +aluFullBit _bit(partialResult[0], cOut[0], operandA[0], finalB[0], cIn[0], command[0], select[1:0]); +`AND (partialResult2, partialResult[0], nSltFlag); + +genvar i; + generate + for (i=1; i < 32; i=i+1) begin : aluBits + `XOR (finalB[i], operandB[i], invert); + `AND (cIn[i], carry, cOut[i-1]); + aluFullBit _bit(partialResult[i], cOut[i], operandA[i], finalB[i], cIn[i], command[0], select[1:0]); + `AND (result[i], partialResult[i], nSltFlag); + end + endgenerate + +wire partialOverflow; +`XOR (partialOverflow, cOut[30], cOut[31]); + +wire [1:0] nSelect; + +wire [30:0] zeroFlags; +`OR (zeroFlags[0], result[0], result[1]); + +generate + for (i=0; i < 30; i=i+1) begin : zeroFlag + `OR (zeroFlags[i+1], result[i+1], zeroFlags[i]); + end +endgenerate + +wire zeroPartial; +`NOT (zeroPartial, zeroFlags[30]); +`NOT (nCommand[0], command[1]); +and #40 (zero, zeroPartial, nCommand[0], nCommand[1]); +and #40 (carryout, cOut[31], nCommand[0], nCommand[1]); +and #40 (overflow, partialOverflow, nCommand[0], nCommand[1]); + +`XOR (aLessB, partialOverflow, partialResult[31]); +`AND (finalSlt, aLessB, sltFlag); +`OR (result[0], partialResult2, finalSlt); + +endmodule diff --git a/aluBit.t.v b/aluBit.t.v new file mode 100644 index 0000000..4bf0cbe --- /dev/null +++ b/aluBit.t.v @@ -0,0 +1,67 @@ +// Test bench for bitslice of ALU without MUX + +`timescale 1 ns / 1 ps +`include "aluBit.v" + +module testBitslice(); + reg a, b, c, i0; + reg[4:0] i; + wire sumXOR, carryAND, nab, orNOR; + wire val; + reg[4:0] count; + + aluBit bitslice (sumXOR, carryAND, nab, orNOR, a, b, c, i0); + +initial begin + count = 0; + i = 5'b00000; + for (i=5'b00000; i<5'b10000; i=i+1) + begin + a = i[0]; + b = i[1]; + c = i[2]; + i0 = i[3]; + #1000 + if ((sumXOR^(a^b))&~c) + begin + $display("failed xor: a b c i0 result"); + $display(" %b %b %b %b %b", a, b, c, i0, sumXOR); + end + else if ((carryAND^(a&b))&~c) + begin + $display("failed and: a b c i0 result"); + $display(" %b %b %b %b %b", a, b, c, i0, carryAND); + end + else if (nab^(a~&b)) + begin + $display("failed nand: a b c i0 result"); + $display(" %b %b %b %b %b", a, b, c, i0, nab); + end + else if ((orNOR^(a~|b))&~i0) + begin + $display("failed nor: a b c i0 result"); + $display(" %b %b %b %b %b", a, b, c, i0, orNOR); + end + else if ((orNOR^(a|b))&i0) + begin + $display("failed or: a b c i0 result"); + $display(" %b %b %b %b %b", a, b, c, i0, orNOR); + end + else if (sumXOR^(a^b^c)) + begin + $display("failed sum: a b c i0 result"); + $display(" %b %b %b %b %b", a, b, c, i0, sumXOR); + end + else if (carryAND^((a&b)|(a&c)|(b&c))) + begin + $display("failed carry: a b c i0 result"); + $display(" %b %b %b %b %b", a, b, c, i0, carryAND); + end + else + begin + count = count + 1; + end + end + $display("all tests passed for %d cases", count); +end +endmodule diff --git a/aluBit.v b/aluBit.v new file mode 100644 index 0000000..469a533 --- /dev/null +++ b/aluBit.v @@ -0,0 +1,47 @@ +// ALU main circuit +// Calculates the solutions for addition, subtraction, SLT. xor, and, nand, nor, or +// but doesn't include MUX +// Note: this also doesn't fully manage the carryout, something else must determine +// wheter or not to pass the "carryAND" out the carryout line. +// external reqirements: +// i0 is the 2^0 digit of the control signal (according to the spec) +// c can only be true if carryout is allowed (for all bits) +`define NAND nand #20 +`define NOR nor #20 +`define XOR2 xor #20 +`define XOR3 xor #30 + +module aluBit +( + output sumXOR, + output carryAND, + output nab, + output orNOR, + input a, + input b, + input carryin, + input i0 +); + wire nab; + wire nbc; + wire nac; + wire sumXOR; + wire ab; + wire carryout; + wire anorb; + wire orNOR; + wire carryAND; + // level 1 for plus/minus, nand, and + `NAND aNANDb(nab, a, b); + `NAND bNANDc(nbc, b, carryin); + `NAND aNANDc(nac, a, carryin); + // level 2 for plus/minus, and + nand #30 cand(carryAND, nab, nac, nbc); + // xor/sum + `XOR3 sumxor(sumXOR, a, b, carryin); + // or/nor + `NOR aNORb(anorb, a, b); + `XOR2 ornor(orNOR, anorb, i0); + + +endmodule diff --git a/aluFullBit.t.v b/aluFullBit.t.v new file mode 100644 index 0000000..0c14a7f --- /dev/null +++ b/aluFullBit.t.v @@ -0,0 +1,140 @@ +// Full BitSlice testbench +`timescale 1 ns / 1 ps +`include "aluFullBit.v" + +`define ADD 3'd0 +`define SUB 3'd1 +`define XOR 3'd2 +`define SLT 3'd3 +`define AND 3'd4 +`define NAND 3'd5 +`define NOR 3'd6 +`define OR 3'd7 + +module testFullBit(); + reg a, b, c, i0; + reg[3:0] in; + reg s0, s1; + wire out, carry; + + reg[4:0] i; + reg[1:0] sel; + reg err; + reg tmp_s0; + reg tmp_s1; + + aluFullBit aluSlice (out, carry, a, b, c, i0, {s1, s0}); + +initial begin + err = 0; + for (in=0; in<4'b1000; in=in+1) + begin + tmp_s0 = in[1]|in[0]; + tmp_s1 = ~in[1]; + s0 = tmp_s0~&in[2]; + s1 = tmp_s1~&in[2]; + sel = {s1, s0}; + for (i=0; i<5'b10000; i=i+1) + begin + a=i[3]; b=i[2]; c=i[1]; i0=in[0]; + #10000 + case (in[2:0]) + `ADD: + begin + if (out^(a^b^c)) + begin + $display("failed sum: a b c i0 sel result"); + $display(" %b %b %b %b %b %b", a, b, c, i0, sel, out); + err = 1; + end + if (carry^((a&b)|(a&c)|(b&c))) + begin + $display("failed carry: a b c i0 sel result carry"); + $display(" %b %b %b %b %b %b %b", a, b, c, i0, sel, out, carry); + err = 1; + end + end + `SUB: + begin + if (out^(a^b^c)) + begin + $display("failed subtract: a b c i0 sel result"); + $display(" %b %b %b %b %b %b", a, b, c, i0, sel, out); + err = 1; + end + if (carry^((a&b)|(a&c)|(b&c))) + begin + $display("failed carry: a b c i0 sel result"); + $display(" %b %b %b %b %b %b", a, b, c, i0, sel, out); + err = 1; + end + end + `XOR: + begin + if ((out^(a^b))&~c) + begin + $display("failed xor: a b c i0 sel result"); + $display(" %b %b %b %b %b %b", a, b, c, i0, sel, out); + err = 1; + end + end + `SLT: + begin + if (out^(a^b^c)) + begin + $display("failed slt: a b c i0 sel result"); + $display(" %b %b %b %b %b %b", a, b, c, i0, sel, out); + err = 1; + end + if (carry^((a&b)|(a&c)|(b&c))) + begin + $display("failed carry: a b c i0 sel result"); + $display(" %b %b %b %b %b %b", a, b, c, i0, sel, out); + err = 1; + end + end + `AND: + begin + if ((out^(a&b))&~c) + begin + $display("failed and: a b c i0 sel result"); + $display(" %b %b %b %b %b %b", a, b, c, i0, sel, out); + err = 1; + end + end + `NAND: + begin + if (out^(a~&b)) + begin + $display("failed nand: a b c i0 sel result"); + $display(" %b %b %b %b %b %b", a, b, c, i0, sel, out); + err = 1; + end + end + `NOR: + begin + if (out^(a~|b)) + begin + $display("failed nor: a b c i0 sel result"); + $display(" %b %b %b %b %b %b", a, b, c, i0, sel, out); + err = 1; + end + end + `OR: + begin + if (out^(a|b)) + begin + $display("failed or: a b c i0 sel result"); + $display(" %b %b %b %b %b %b", a, b, c, i0, sel, out); + err = 1; + end + end + endcase + end + end + if (~err) + begin + $display("all tests passed"); + end +end +endmodule diff --git a/aluFullBit.v b/aluFullBit.v new file mode 100644 index 0000000..c44868f --- /dev/null +++ b/aluFullBit.v @@ -0,0 +1,22 @@ +// Full bitslice of ALUE (attaching logic to mux) + +`include "aluBit.v" +`include "mux.v" + +module aluFullBit +( + output res, + output carryAND, + input a, + input b, + input cin, + input ctrl0, + input[1:0] sel +); + + wire sumXOR, nab, orNOR; + aluBit alu (sumXOR, carryAND, nab, orNOR, a, b, cin, ctrl0); + + multiplexer mux (res, sumXOR, orNOR, carryAND, nab, sel[1], sel[0]); + +endmodule diff --git a/lut.v b/lut.v new file mode 100644 index 0000000..5d3ec5f --- /dev/null +++ b/lut.v @@ -0,0 +1,35 @@ +// LUT for translating commands to control logic + +// define commands +`define ADD 3'd0 +`define SUB 3'd1 +`define XOR 3'd2 +`define SLT 3'd3 +`define AND 3'd4 +`define NAND 3'd5 +`define NOR 3'd6 +`define OR 3'd7 + +module ALULut +( + output reg[1:0] select, + output reg invert, + output reg carry, + input[2:0] operation +); + wire[2:0] operation; + + always @(operation) begin + case (operation) + `ADD: begin select = 3; invert = 0; carry = 1; end + `SUB: begin select = 3; invert = 1; carry = 1; end + `AND: begin select = 1; invert = 0; carry = 0; end + `NAND: begin select = 0; invert = 0; carry = 0; end + `NOR: begin select = 2; invert = 0; carry = 0; end + `OR: begin select = 2; invert = 0; carry = 0; end + `XOR: begin select = 3; invert = 0; carry = 0; end + `SLT: begin select = 3; invert = 1; carry = 1; end + endcase + end + +endmodule diff --git a/mux.t.v b/mux.t.v new file mode 100644 index 0000000..45fdb3e --- /dev/null +++ b/mux.t.v @@ -0,0 +1,39 @@ +// MUX testbench +`timescale 1 ns / 1 ps +`include "mux.v" + +module testMUX(); + reg a, b, c, d; + reg s0, s1; + wire out; + + reg[4:0] i; + reg[2:0] sel; + reg err; + + multiplexer mux (out, a, b, c, d, s1, s0); + +initial begin + err = 0; + for (sel=0; sel<3'b100; sel=sel+1) + begin + s0=sel[0]; + s1=sel[1]; + for (i=0; i<5'b10000; i=i+1) + begin + a=i[3]; b=i[2]; c=i[1]; d=i[0]; + #1000 + //if (1) + if (out^i[sel]) + begin + $display("failed case input: %b, select: %b, output: %b", i[3:0], sel[1:0], out); + err = 1; + end + end + end + if (~err) + begin + $display("all tests passed"); + end +end +endmodule diff --git a/mux.v b/mux.v new file mode 100644 index 0000000..7c23cf6 --- /dev/null +++ b/mux.v @@ -0,0 +1,35 @@ +// 4 input MUX +// takes in 4 inputs and two selects and passes through the selected input + +`define NAND nand #30 +`define NOT not #10 + +module multiplexer +( + output out, + input a, + input b, + input c, + input d, + input s1, + input s0 +); + wire ns0, ns1; + wire aout, bout, cout, dout; + + `NOT(ns0, s0); + `NOT(ns1, s1); + `NAND(aout, s1, s0, a); + `NAND(bout, s1, ns0, b); + `NAND(cout, ns1, s0, c); + `NAND(dout, ns1, ns0, d); + + nand #40 (out, aout, bout, cout, dout); +endmodule + +// propogation delays: +// 3 layers: +// 1: nots (10) +// 2: nands (30) +// 3: nand (40) +// total: 80 diff --git a/tests.png b/tests.png new file mode 100644 index 0000000..13bf92f Binary files /dev/null and b/tests.png differ