diff --git a/LUTs.v b/LUTs.v new file mode 100644 index 0000000..c7c8dfc --- /dev/null +++ b/LUTs.v @@ -0,0 +1,71 @@ +// defining command numbers +`define ADD 3'd0 +`define SUB 3'd1 +`define XOR 3'd2 +`define SLT 3'd3 +`define AND 3'd4 +`define NAND 3'd5 +`define NOR 3'd6 +`define OR 3'd7 + +// implementing a control logic LUT to determine ALU operation +module ALUcontrolLUT +( +output reg[2:0] muxindex, +output reg invertB, +output reg othercontrolsignal, +input[2:0] ALUcommand +); + + always @(ALUcommand) begin + case (ALUcommand) + `ADD: begin muxindex = 0; invertB=0; othercontrolsignal = 0; end + `SUB: begin muxindex = 0; invertB=1; othercontrolsignal = 0; end + `XOR: begin muxindex = 1; invertB=0; othercontrolsignal = 0; end + `SLT: begin muxindex = 2; invertB=0; othercontrolsignal = 0; end + `AND: begin muxindex = 3; invertB=0; othercontrolsignal = 0; end + `NAND: begin muxindex = 3; invertB=0; othercontrolsignal = 1; end + `NOR: begin muxindex = 4; invertB=0; othercontrolsignal = 1; end + `OR: begin muxindex = 4; invertB=0; othercontrolsignal = 0; end + endcase + end +endmodule + +`define ADD/SUB 3'd0 +`define XOR 3'd1 +`define SLT 3'd2 +`define AND/NAND 3'd3 +`define NOR/OR 3'd4 + +module ALUoutputLUT +( +input[2:0] muxindex, +input invertB, +input othercontrolsignal, +output[31:0] result, +output carryout, +output overflow, +output zero +); +wire resAddsub[31:0]; +wire resXor[31:0]; +wire resSlt[31:0]; +wire resAndnand[31:0]; +wire resNoror[31:0]; + +32bit_addsub dut (resAddsub, carryout, zero, overflow, operandA, operandB, invertB); +32bit_xor dut (resXor, carryout, zero, overflow, operandA, operandB); +32bit_slt dut (resSlt, carryout, zero, overflow, operandA, operandB); +32bit_andnand dut (resAndnand, carryout, zero, overflow, operandA, operandB, othercontrolsignal); +32bit_andnand dut (resNoror, carryout, zero, overflow, operandA, operandB, othercontrolsignal); + + always @(muxindex) begin + case(muxindex) + `ADD/SUB: begin result = resAddsub; end + `XOR: begin result = ; end + `SLT: begin result = ; end + `AND/NAND: begin result = ; end + `NOR/OR: begin result = ; end + endcase + end +endmodule diff --git a/Lab 1 Writeup.pdf b/Lab 1 Writeup.pdf new file mode 100644 index 0000000..b203104 Binary files /dev/null and b/Lab 1 Writeup.pdf differ diff --git a/alu b/alu new file mode 100755 index 0000000..2b142bf --- /dev/null +++ b/alu @@ -0,0 +1,6022 @@ +#! /usr/local/bin/vvp +:ivl_version "10.1 (stable)" "(v10_1-81-g95d3579)"; +:ivl_delay_selection "TYPICAL"; +:vpi_time_precision + 0; +:vpi_module "system"; +:vpi_module "vhdl_sys"; +:vpi_module "v2005_math"; +:vpi_module "va_math"; +S_0x18c4020 .scope module, "ALU" "ALU" 2 275; + .timescale 0 0; + .port_info 0 /OUTPUT 32 "result" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /OUTPUT 1 "zero" + .port_info 3 /OUTPUT 1 "overflow" + .port_info 4 /INPUT 32 "operandA" + .port_info 5 /INPUT 32 "operandB" + .port_info 6 /INPUT 3 "command" +v0x194c3a0_0 .net "carryout", 0 0, v0x194acb0_0; 1 drivers +o0x7f93f4ee9018 .functor BUFZ 3, C4; HiZ drive +v0x194c490_0 .net "command", 2 0, o0x7f93f4ee9018; 0 drivers +v0x194c560_0 .net "invertB", 0 0, v0x17b6f60_0; 1 drivers +v0x194c630_0 .net "muxindex", 2 0, v0x17b8fa0_0; 1 drivers +o0x7f93f4eeeb98 .functor BUFZ 32, C4; HiZ drive +v0x194c6d0_0 .net "operandA", 31 0, o0x7f93f4eeeb98; 0 drivers +o0x7f93f4eeebc8 .functor BUFZ 32, C4; HiZ drive +v0x194c7c0_0 .net "operandB", 31 0, o0x7f93f4eeebc8; 0 drivers +v0x194c880_0 .net "othercontrolsignal", 0 0, v0x17bafe0_0; 1 drivers +v0x194c9b0_0 .net "overflow", 0 0, v0x194b530_0; 1 drivers +v0x194ca50_0 .net "result", 31 0, v0x194be40_0; 1 drivers +v0x194cb80_0 .net "zero", 0 0, v0x194bee0_0; 1 drivers +S_0x190a3b0 .scope module, "controlLookup" "ALUcontrolLUT" 2 290, 2 191 0, S_0x18c4020; + .timescale 0 0; + .port_info 0 /OUTPUT 3 "muxindex" + .port_info 1 /OUTPUT 1 "invertB" + .port_info 2 /OUTPUT 1 "othercontrolsignal" + .port_info 3 /INPUT 3 "ALUcommand" +v0x18ce300_0 .net "ALUcommand", 2 0, o0x7f93f4ee9018; alias, 0 drivers +v0x17b6f60_0 .var "invertB", 0 0; +v0x17b8fa0_0 .var "muxindex", 2 0; +v0x17bafe0_0 .var "othercontrolsignal", 0 0; +E_0x1907540 .event edge, v0x18ce300_0; +S_0x17ef170 .scope module, "outputLookup" "ALUoutputLUT" 2 292, 2 221 0, S_0x18c4020; + .timescale 0 0; + .port_info 0 /INPUT 32 "operandA" + .port_info 1 /INPUT 32 "operandB" + .port_info 2 /INPUT 3 "muxindex" + .port_info 3 /INPUT 1 "invertB" + .port_info 4 /INPUT 1 "othercontrolsignal" + .port_info 5 /OUTPUT 32 "result" + .port_info 6 /OUTPUT 1 "carryout" + .port_info 7 /OUTPUT 1 "zero" + .port_info 8 /OUTPUT 1 "overflow" +v0x194acb0_0 .var "carryout", 0 0; +L_0x7f93f4ea0258 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +v0x194ad90_0 .net "carryoutAND", 0 0, L_0x7f93f4ea0258; 1 drivers +v0x194ae50_0 .net "carryoutAddSub", 0 0, L_0x198b810; 1 drivers +v0x194aef0_0 .net "carryoutOR", 0 0, L_0x19d4670; 1 drivers +L_0x7f93f4ea0180 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +v0x194afc0_0 .net "carryoutSLT", 0 0, L_0x7f93f4ea0180; 1 drivers +L_0x7f93f4ea0018 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +v0x194b0b0_0 .net "carryoutXor", 0 0, L_0x7f93f4ea0018; 1 drivers +v0x194b180_0 .net "invertB", 0 0, v0x17b6f60_0; alias, 1 drivers +v0x194b220_0 .net "muxindex", 2 0, v0x17b8fa0_0; alias, 1 drivers +v0x194b2c0_0 .net "operandA", 31 0, o0x7f93f4eeeb98; alias, 0 drivers +v0x194b3f0_0 .net "operandB", 31 0, o0x7f93f4eeebc8; alias, 0 drivers +v0x194b490_0 .net "othercontrolsignal", 0 0, v0x17bafe0_0; alias, 1 drivers +v0x194b530_0 .var "overflow", 0 0; +L_0x7f93f4ea02e8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +v0x194b5d0_0 .net "overflowAND", 0 0, L_0x7f93f4ea02e8; 1 drivers +v0x194b6a0_0 .net "overflowAddSub", 0 0, L_0x198b250; 1 drivers +v0x194b770_0 .net "overflowOR", 0 0, L_0x19d48e0; 1 drivers +L_0x7f93f4ea0210 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +v0x194b840_0 .net "overflowSLT", 0 0, L_0x7f93f4ea0210; 1 drivers +L_0x7f93f4ea00a8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +v0x194b910_0 .net "overflowXor", 0 0, L_0x7f93f4ea00a8; 1 drivers +v0x194bac0_0 .net "resAddsub", 31 0, L_0x198b970; 1 drivers +v0x194bb60_0 .net "resAndnand", 31 0, L_0x19c9920; 1 drivers +v0x194bc00_0 .net "resNoror", 31 0, L_0x19d38f0; 1 drivers +L_0x7f93f4ea0138 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +RS_0x7f93f4ef6a28 .resolv tri, L_0x7f93f4ea0138, L_0x19aea00; +v0x194bca0_0 .net8 "resSlt", 31 0, RS_0x7f93f4ef6a28; 2 drivers +v0x194bd70_0 .net "resXor", 31 0, L_0x19937c0; 1 drivers +v0x194be40_0 .var "result", 31 0; +v0x194bee0_0 .var "zero", 0 0; +L_0x7f93f4ea02a0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +v0x194bf80_0 .net "zeroAND", 0 0, L_0x7f93f4ea02a0; 1 drivers +v0x194c050_0 .net "zeroAddSub", 0 0, L_0x1988490; 1 drivers +v0x194c120_0 .net "zeroOR", 0 0, L_0x19d47d0; 1 drivers +L_0x7f93f4ea01c8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +v0x194c1c0_0 .net "zeroSLT", 0 0, L_0x7f93f4ea01c8; 1 drivers +L_0x7f93f4ea0060 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +v0x194c290_0 .net "zeroXor", 0 0, L_0x7f93f4ea0060; 1 drivers +E_0x17bf140 .event edge, v0x17b8fa0_0; +S_0x180cd20 .scope module, "dut0" "AddSub" 2 257, 2 32 0, S_0x17ef170; + .timescale 0 0; + .port_info 0 /OUTPUT 32 "result" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /OUTPUT 1 "zero" + .port_info 3 /OUTPUT 1 "overflow" + .port_info 4 /INPUT 32 "operandA" + .port_info 5 /INPUT 32 "operandB" + .port_info 6 /INPUT 1 "subtract" +L_0x198b250/d .functor XOR 1, L_0x1985950, L_0x198b810, C4<0>, C4<0>; +L_0x198b250 .delay 1 (20,20,20) L_0x198b250/d; +L_0x198c890/d .functor NOR 1, L_0x198c9f0, L_0x19883a0, C4<0>, C4<0>; +L_0x198c890 .delay 1 (10,10,10) L_0x198c890/d; +o0x7f93f4eef228 .functor BUFZ 1, C4; HiZ drive +L_0x1988490/d .functor NOR 1, o0x7f93f4eef228, L_0x198c590, C4<0>, C4<0>; +L_0x1988490 .delay 1 (10,10,10) L_0x1988490/d; +v0x17c3480_0 .net *"_s166", 0 0, L_0x198c9f0; 1 drivers +v0x17c1400_0 .net *"_s168", 0 0, L_0x19883a0; 1 drivers +v0x17af190_0 .net *"_s172", 0 0, L_0x198c590; 1 drivers +v0x17ad160_0 .net "carryout", 0 0, L_0x198b810; alias, 1 drivers +v0x17ab130 .array "carryoutmid", 0 30; +v0x17ab130_0 .net v0x17ab130 0, 0 0, L_0x198ad70; 1 drivers +v0x17ab130_1 .net v0x17ab130 1, 0 0, L_0x1972380; 1 drivers +v0x17ab130_2 .net v0x17ab130 2, 0 0, L_0x1972ed0; 1 drivers +v0x17ab130_3 .net v0x17ab130 3, 0 0, L_0x1973900; 1 drivers +v0x17ab130_4 .net v0x17ab130 4, 0 0, L_0x1974370; 1 drivers +v0x17ab130_5 .net v0x17ab130 5, 0 0, L_0x1974df0; 1 drivers +v0x17ab130_6 .net v0x17ab130 6, 0 0, L_0x1975780; 1 drivers +v0x17ab130_7 .net v0x17ab130 7, 0 0, L_0x19761d0; 1 drivers +v0x17ab130_8 .net v0x17ab130 8, 0 0, L_0x1976c10; 1 drivers +v0x17ab130_9 .net v0x17ab130 9, 0 0, L_0x1976580; 1 drivers +v0x17ab130_10 .net v0x17ab130 10, 0 0, L_0x19782c0; 1 drivers +v0x17ab130_11 .net v0x17ab130 11, 0 0, L_0x1978d30; 1 drivers +v0x17ab130_12 .net v0x17ab130 12, 0 0, L_0x19797b0; 1 drivers +v0x17ab130_13 .net v0x17ab130 13, 0 0, L_0x197a1a0; 1 drivers +v0x17ab130_14 .net v0x17ab130 14, 0 0, L_0x167f9f0; 1 drivers +v0x17ab130_15 .net v0x17ab130 15, 0 0, L_0x197ba20; 1 drivers +v0x17ab130_16 .net v0x17ab130 16, 0 0, L_0x197c490; 1 drivers +v0x17ab130_17 .net v0x17ab130 17, 0 0, L_0x197ced0; 1 drivers +v0x17ab130_18 .net v0x17ab130 18, 0 0, L_0x197d920; 1 drivers +v0x17ab130_19 .net v0x17ab130 19, 0 0, L_0x197e380; 1 drivers +v0x17ab130_20 .net v0x17ab130 20, 0 0, L_0x197edf0; 1 drivers +v0x17ab130_21 .net v0x17ab130 21, 0 0, L_0x197f870; 1 drivers +v0x17ab130_22 .net v0x17ab130 22, 0 0, L_0x1980260; 1 drivers +v0x17ab130_23 .net v0x17ab130 23, 0 0, L_0x1980cb0; 1 drivers +v0x17ab130_24 .net v0x17ab130 24, 0 0, L_0x1981710; 1 drivers +v0x17ab130_25 .net v0x17ab130 25, 0 0, L_0x1982180; 1 drivers +v0x17ab130_26 .net v0x17ab130 26, 0 0, L_0x1983030; 1 drivers +v0x17ab130_27 .net v0x17ab130 27, 0 0, L_0x1983a70; 1 drivers +v0x17ab130_28 .net v0x17ab130 28, 0 0, L_0x19844c0; 1 drivers +v0x17ab130_29 .net v0x17ab130 29, 0 0, L_0x1984f00; 1 drivers +v0x17ab130_30 .net v0x17ab130 30, 0 0, L_0x1985950; 1 drivers +v0x17ab1d0_0 .net "operandA", 31 0, o0x7f93f4eeeb98; alias, 0 drivers +v0x17a70d0_0 .net "operandB", 31 0, o0x7f93f4eeebc8; alias, 0 drivers +v0x17a50a0_0 .net "overflow", 0 0, L_0x198b250; alias, 1 drivers +v0x17a3070_0 .net "result", 31 0, L_0x198b970; alias, 1 drivers +v0x17a1040_0 .net "subtract", 0 0, v0x17b6f60_0; alias, 1 drivers +v0x17a10e0_0 .net "zero", 0 0, L_0x1988490; alias, 1 drivers +v0x190c830 .array "zeromid", 0 30; +v0x190c830_0 .net v0x190c830 0, 0 0, L_0x198c890; 1 drivers +v0x190c830_1 .net v0x190c830 1, 0 0, L_0x19852b0; 1 drivers +v0x190c830_2 .net v0x190c830 2, 0 0, L_0x1985fe0; 1 drivers +v0x190c830_3 .net v0x190c830 3, 0 0, L_0x1985d50; 1 drivers +v0x190c830_4 .net v0x190c830 4, 0 0, L_0x1986580; 1 drivers +v0x190c830_5 .net v0x190c830 5, 0 0, L_0x1986250; 1 drivers +v0x190c830_6 .net v0x190c830 6, 0 0, L_0x1986a00; 1 drivers +v0x190c830_7 .net v0x190c830 7, 0 0, L_0x19867a0; 1 drivers +v0x190c830_8 .net v0x190c830 8, 0 0, L_0x19864f0; 1 drivers +v0x190c830_9 .net v0x190c830 9, 0 0, L_0x1986c70; 1 drivers +v0x190c830_10 .net v0x190c830 10, 0 0, L_0x1987470; 1 drivers +v0x190c830_11 .net v0x190c830 11, 0 0, L_0x19871f0; 1 drivers +v0x190c830_12 .net v0x190c830 12, 0 0, L_0x1987970; 1 drivers +v0x190c830_13 .net v0x190c830 13, 0 0, L_0x19876e0; 1 drivers +v0x190c830_14 .net v0x190c830 14, 0 0, L_0x1987e80; 1 drivers +v0x190c830_15 .net v0x190c830 15, 0 0, L_0x1987be0; 1 drivers +v0x190c830_16 .net v0x190c830 16, 0 0, L_0x1986ee0; 1 drivers +v0x190c830_17 .net v0x190c830 17, 0 0, L_0x19880f0; 1 drivers +v0x190c830_18 .net v0x190c830 18, 0 0, L_0x1988960; 1 drivers +v0x190c830_19 .net v0x190c830 19, 0 0, L_0x19886a0; 1 drivers +v0x190c830_20 .net v0x190c830 20, 0 0, L_0x1988e00; 1 drivers +v0x190c830_21 .net v0x190c830 21, 0 0, L_0x1988b80; 1 drivers +v0x190c830_22 .net v0x190c830 22, 0 0, L_0x1989300; 1 drivers +v0x190c830_23 .net v0x190c830 23, 0 0, L_0x1989070; 1 drivers +v0x190c830_24 .net v0x190c830 24, 0 0, L_0x1989810; 1 drivers +v0x190c830_25 .net v0x190c830 25, 0 0, L_0x1989570; 1 drivers +v0x190c830_26 .net v0x190c830 26, 0 0, L_0x1989d30; 1 drivers +v0x190c830_27 .net v0x190c830 27, 0 0, L_0x1989a80; 1 drivers +v0x190c830_28 .net v0x190c830 28, 0 0, L_0x198a260; 1 drivers +v0x190c830_29 .net v0x190c830 29, 0 0, L_0x1989fa0; 1 drivers +v0x190c830_30 .net v0x190c830 30, 0 0, o0x7f93f4eef228; 0 drivers +L_0x19724e0 .part o0x7f93f4eeeb98, 1, 1; +L_0x1972750 .part o0x7f93f4eeebc8, 1, 1; +L_0x1973070 .part o0x7f93f4eeeb98, 2, 1; +L_0x1973190 .part o0x7f93f4eeebc8, 2, 1; +L_0x1973aa0 .part o0x7f93f4eeeb98, 3, 1; +L_0x1973bc0 .part o0x7f93f4eeebc8, 3, 1; +L_0x1974510 .part o0x7f93f4eeeb98, 4, 1; +L_0x1974630 .part o0x7f93f4eeebc8, 4, 1; +L_0x1974f50 .part o0x7f93f4eeeb98, 5, 1; +L_0x19750b0 .part o0x7f93f4eeebc8, 5, 1; +L_0x1975920 .part o0x7f93f4eeeb98, 6, 1; +L_0x1975a40 .part o0x7f93f4eeebc8, 6, 1; +L_0x1976370 .part o0x7f93f4eeeb98, 7, 1; +L_0x1976490 .part o0x7f93f4eeebc8, 7, 1; +L_0x1976db0 .part o0x7f93f4eeeb98, 8, 1; +L_0x1976ed0 .part o0x7f93f4eeebc8, 8, 1; +L_0x1977800 .part o0x7f93f4eeeb98, 9, 1; +L_0x1972640 .part o0x7f93f4eeebc8, 9, 1; +L_0x1978460 .part o0x7f93f4eeeb98, 10, 1; +L_0x1978580 .part o0x7f93f4eeebc8, 10, 1; +L_0x1978ed0 .part o0x7f93f4eeeb98, 11, 1; +L_0x1978ff0 .part o0x7f93f4eeebc8, 11, 1; +L_0x1979910 .part o0x7f93f4eeeb98, 12, 1; +L_0x1979a70 .part o0x7f93f4eeebc8, 12, 1; +L_0x197a340 .part o0x7f93f4eeeb98, 13, 1; +L_0x197a460 .part o0x7f93f4eeebc8, 13, 1; +L_0x167fb90 .part o0x7f93f4eeeb98, 14, 1; +L_0x167fcb0 .part o0x7f93f4eeebc8, 14, 1; +L_0x197bbc0 .part o0x7f93f4eeeb98, 15, 1; +L_0x197bce0 .part o0x7f93f4eeebc8, 15, 1; +L_0x197c630 .part o0x7f93f4eeeb98, 16, 1; +L_0x197c750 .part o0x7f93f4eeebc8, 16, 1; +L_0x197d070 .part o0x7f93f4eeeb98, 17, 1; +L_0x197d190 .part o0x7f93f4eeebc8, 17, 1; +L_0x197dac0 .part o0x7f93f4eeeb98, 18, 1; +L_0x197dbe0 .part o0x7f93f4eeebc8, 18, 1; +L_0x197e520 .part o0x7f93f4eeeb98, 19, 1; +L_0x197e640 .part o0x7f93f4eeebc8, 19, 1; +L_0x197ef90 .part o0x7f93f4eeeb98, 20, 1; +L_0x197f0b0 .part o0x7f93f4eeebc8, 20, 1; +L_0x197f9d0 .part o0x7f93f4eeeb98, 21, 1; +L_0x197fb30 .part o0x7f93f4eeebc8, 21, 1; +L_0x1980400 .part o0x7f93f4eeeb98, 22, 1; +L_0x1980520 .part o0x7f93f4eeebc8, 22, 1; +L_0x1980e50 .part o0x7f93f4eeeb98, 23, 1; +L_0x1980f70 .part o0x7f93f4eeebc8, 23, 1; +L_0x19818b0 .part o0x7f93f4eeeb98, 24, 1; +L_0x19819d0 .part o0x7f93f4eeebc8, 24, 1; +L_0x1982320 .part o0x7f93f4eeeb98, 25, 1; +L_0x1977920 .part o0x7f93f4eeebc8, 25, 1; +L_0x19831d0 .part o0x7f93f4eeeb98, 26, 1; +L_0x19832f0 .part o0x7f93f4eeebc8, 26, 1; +L_0x1983c10 .part o0x7f93f4eeeb98, 27, 1; +L_0x1983d30 .part o0x7f93f4eeebc8, 27, 1; +L_0x1984660 .part o0x7f93f4eeeb98, 28, 1; +L_0x1984780 .part o0x7f93f4eeebc8, 28, 1; +L_0x19850a0 .part o0x7f93f4eeeb98, 29, 1; +L_0x19851c0 .part o0x7f93f4eeebc8, 29, 1; +L_0x1985b40 .part o0x7f93f4eeeb98, 30, 1; +L_0x1985c60 .part o0x7f93f4eeebc8, 30, 1; +L_0x1985370 .part L_0x198b970, 1, 1; +L_0x19860f0 .part L_0x198b970, 2, 1; +L_0x1986450 .part L_0x198b970, 3, 1; +L_0x1986640 .part L_0x198b970, 4, 1; +L_0x19863b0 .part L_0x198b970, 5, 1; +L_0x1986b10 .part L_0x198b970, 6, 1; +L_0x1986900 .part L_0x198b970, 7, 1; +L_0x1987090 .part L_0x198b970, 8, 1; +L_0x1986d80 .part L_0x198b970, 9, 1; +L_0x1987580 .part L_0x198b970, 10, 1; +L_0x1987300 .part L_0x198b970, 11, 1; +L_0x1987a80 .part L_0x198b970, 12, 1; +L_0x19877f0 .part L_0x198b970, 13, 1; +L_0x1987f90 .part L_0x198b970, 14, 1; +L_0x1987cf0 .part L_0x198b970, 15, 1; +L_0x19885b0 .part L_0x198b970, 16, 1; +L_0x1988200 .part L_0x198b970, 17, 1; +L_0x1988a20 .part L_0x198b970, 18, 1; +L_0x19887b0 .part L_0x198b970, 19, 1; +L_0x1988f10 .part L_0x198b970, 20, 1; +L_0x1988c90 .part L_0x198b970, 21, 1; +L_0x1989410 .part L_0x198b970, 22, 1; +L_0x1989180 .part L_0x198b970, 23, 1; +L_0x1989920 .part L_0x198b970, 24, 1; +L_0x1989680 .part L_0x198b970, 25, 1; +L_0x1989e40 .part L_0x198b970, 26, 1; +L_0x1989b90 .part L_0x198b970, 27, 1; +L_0x198a370 .part L_0x198b970, 28, 1; +L_0x198a0b0 .part L_0x198b970, 29, 1; +L_0x198af60 .part o0x7f93f4eeeb98, 0, 1; +L_0x198a4d0 .part o0x7f93f4eeebc8, 0, 1; +LS_0x198b970_0_0 .concat8 [ 1 1 1 1], L_0x198a950, L_0x1971f60, L_0x1972ab0, L_0x19734e0; +LS_0x198b970_0_4 .concat8 [ 1 1 1 1], L_0x1973f50, L_0x19749d0, L_0x1975360, L_0x1975e00; +LS_0x198b970_0_8 .concat8 [ 1 1 1 1], L_0x19767f0, L_0x19772b0, L_0x1977ea0, L_0x1978910; +LS_0x198b970_0_12 .concat8 [ 1 1 1 1], L_0x1979390, L_0x1979d80, L_0x197a7d0, L_0x197b600; +LS_0x198b970_0_16 .concat8 [ 1 1 1 1], L_0x197c070, L_0x197cab0, L_0x197d500, L_0x197df60; +LS_0x198b970_0_20 .concat8 [ 1 1 1 1], L_0x197e9d0, L_0x197f450, L_0x197fe40, L_0x1980890; +LS_0x198b970_0_24 .concat8 [ 1 1 1 1], L_0x19812f0, L_0x1981d60, L_0x1982c60, L_0x1983650; +LS_0x198b970_0_28 .concat8 [ 1 1 1 1], L_0x19840a0, L_0x1984ae0, L_0x1985530, L_0x198b3f0; +LS_0x198b970_1_0 .concat8 [ 4 4 4 4], LS_0x198b970_0_0, LS_0x198b970_0_4, LS_0x198b970_0_8, LS_0x198b970_0_12; +LS_0x198b970_1_4 .concat8 [ 4 4 4 4], LS_0x198b970_0_16, LS_0x198b970_0_20, LS_0x198b970_0_24, LS_0x198b970_0_28; +L_0x198b970 .concat8 [ 16 16 0 0], LS_0x198b970_1_0, LS_0x198b970_1_4; +L_0x198b0c0 .part o0x7f93f4eeeb98, 31, 1; +L_0x198b160 .part o0x7f93f4eeebc8, 31, 1; +L_0x198c9f0 .part L_0x198b970, 0, 1; +L_0x19883a0 .part L_0x198b970, 1, 1; +L_0x198c590 .part L_0x198b970, 31, 1; +S_0x18ea4f0 .scope module, "adderfinal" "FullAdder1bit" 2 50, 2 8 0, S_0x180cd20; + .timescale 0 0; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b0" + .port_info 4 /INPUT 1 "carryin" + .port_info 5 /INPUT 1 "subtract" +L_0x198b000/d .functor XOR 1, L_0x198b160, L_0x198b810, C4<0>, C4<0>; +L_0x198b000 .delay 1 (20,20,20) L_0x198b000/d; +L_0x198a650/d .functor XOR 1, L_0x198b0c0, L_0x198b000, C4<0>, C4<0>; +L_0x198a650 .delay 1 (20,20,20) L_0x198a650/d; +L_0x198b3f0/d .functor XOR 1, L_0x198a650, v0x17b6f60_0, C4<0>, C4<0>; +L_0x198b3f0 .delay 1 (20,20,20) L_0x198b3f0/d; +L_0x198b550/d .functor AND 1, L_0x198b0c0, L_0x198b000, C4<1>, C4<1>; +L_0x198b550 .delay 1 (20,20,20) L_0x198b550/d; +L_0x198b6b0/d .functor AND 1, L_0x198a650, v0x17b6f60_0, C4<1>, C4<1>; +L_0x198b6b0 .delay 1 (20,20,20) L_0x198b6b0/d; +L_0x198b810/d .functor OR 1, L_0x198b550, L_0x198b6b0, C4<0>, C4<0>; +L_0x198b810 .delay 1 (20,20,20) L_0x198b810/d; +v0x1810c30_0 .net "a", 0 0, L_0x198b0c0; 1 drivers +v0x1812000_0 .net "b", 0 0, L_0x198b000; 1 drivers +v0x18129e0_0 .net "b0", 0 0, L_0x198b160; 1 drivers +v0x1814a20_0 .net "carryin", 0 0, v0x17b6f60_0; alias, 1 drivers +v0x1816a60_0 .net "carryout", 0 0, L_0x198b810; alias, 1 drivers +v0x1818aa0_0 .net "cout1", 0 0, L_0x198b550; 1 drivers +v0x181aae0_0 .net "cout2", 0 0, L_0x198b6b0; 1 drivers +v0x181cb20_0 .net "subtract", 0 0, L_0x198b810; alias, 1 drivers +v0x181eb60_0 .net "sum", 0 0, L_0x198b3f0; 1 drivers +v0x1820b90_0 .net "sumAB", 0 0, L_0x198a650; 1 drivers +S_0x18d0140 .scope module, "adderinit" "FullAdder1bit" 2 45, 2 8 0, S_0x180cd20; + .timescale 0 0; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b0" + .port_info 4 /INPUT 1 "carryin" + .port_info 5 /INPUT 1 "subtract" +L_0x198a150/d .functor XOR 1, L_0x198a4d0, v0x17b6f60_0, C4<0>, C4<0>; +L_0x198a150 .delay 1 (20,20,20) L_0x198a150/d; +L_0x198a7f0/d .functor XOR 1, L_0x198af60, L_0x198a150, C4<0>, C4<0>; +L_0x198a7f0 .delay 1 (20,20,20) L_0x198a7f0/d; +L_0x198a950/d .functor XOR 1, L_0x198a7f0, v0x17b6f60_0, C4<0>, C4<0>; +L_0x198a950 .delay 1 (20,20,20) L_0x198a950/d; +L_0x198aab0/d .functor AND 1, L_0x198af60, L_0x198a150, C4<1>, C4<1>; +L_0x198aab0 .delay 1 (20,20,20) L_0x198aab0/d; +L_0x198ac10/d .functor AND 1, L_0x198a7f0, v0x17b6f60_0, C4<1>, C4<1>; +L_0x198ac10 .delay 1 (20,20,20) L_0x198ac10/d; +L_0x198ad70/d .functor OR 1, L_0x198aab0, L_0x198ac10, C4<0>, C4<0>; +L_0x198ad70 .delay 1 (20,20,20) L_0x198ad70/d; +v0x1824c00_0 .net "a", 0 0, L_0x198af60; 1 drivers +v0x1826c30_0 .net "b", 0 0, L_0x198a150; 1 drivers +v0x1828c60_0 .net "b0", 0 0, L_0x198a4d0; 1 drivers +v0x182ad30_0 .net "carryin", 0 0, v0x17b6f60_0; alias, 1 drivers +v0x182cd60_0 .net "carryout", 0 0, L_0x198ad70; alias, 1 drivers +v0x182ed90_0 .net "cout1", 0 0, L_0x198aab0; 1 drivers +v0x1830dc0_0 .net "cout2", 0 0, L_0x198ac10; 1 drivers +v0x1832310_0 .net "subtract", 0 0, v0x17b6f60_0; alias, 1 drivers +v0x1832e00_0 .net "sum", 0 0, L_0x198a950; 1 drivers +v0x1834e50_0 .net "sumAB", 0 0, L_0x198a7f0; 1 drivers +S_0x1810150 .scope generate, "genblk1[1]" "genblk1[1]" 2 47, 2 47 0, S_0x180cd20; + .timescale 0 0; +P_0x182ee50 .param/l "i" 0 2 47, +C4<01>; +S_0x1812380 .scope module, "addermid" "FullAdder1bit" 2 48, 2 8 0, S_0x1810150; + .timescale 0 0; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b0" + .port_info 4 /INPUT 1 "carryin" + .port_info 5 /INPUT 1 "subtract" +L_0x1971d40/d .functor XOR 1, L_0x1972750, L_0x198ad70, C4<0>, C4<0>; +L_0x1971d40 .delay 1 (20,20,20) L_0x1971d40/d; +L_0x1971e00/d .functor XOR 1, L_0x19724e0, L_0x1971d40, C4<0>, C4<0>; +L_0x1971e00 .delay 1 (20,20,20) L_0x1971e00/d; +L_0x1971f60/d .functor XOR 1, L_0x1971e00, v0x17b6f60_0, C4<0>, C4<0>; +L_0x1971f60 .delay 1 (20,20,20) L_0x1971f60/d; +L_0x19720c0/d .functor AND 1, L_0x19724e0, L_0x1971d40, C4<1>, C4<1>; +L_0x19720c0 .delay 1 (20,20,20) L_0x19720c0/d; +L_0x1972220/d .functor AND 1, L_0x1971e00, v0x17b6f60_0, C4<1>, C4<1>; +L_0x1972220 .delay 1 (20,20,20) L_0x1972220/d; +L_0x1972380/d .functor OR 1, L_0x19720c0, L_0x1972220, C4<0>, C4<0>; +L_0x1972380 .delay 1 (20,20,20) L_0x1972380/d; +v0x1836ea0_0 .net "a", 0 0, L_0x19724e0; 1 drivers +v0x1838400_0 .net "b", 0 0, L_0x1971d40; 1 drivers +v0x1838ef0_0 .net "b0", 0 0, L_0x1972750; 1 drivers +v0x183a450_0 .net "carryin", 0 0, v0x17b6f60_0; alias, 1 drivers +v0x183c4a0_0 .net "carryout", 0 0, L_0x1972380; alias, 1 drivers +v0x183cf90_0 .net "cout1", 0 0, L_0x19720c0; 1 drivers +v0x183e4f0_0 .net "cout2", 0 0, L_0x1972220; 1 drivers +v0x183efe0_0 .net "subtract", 0 0, L_0x198ad70; alias, 1 drivers +v0x1840540_0 .net "sum", 0 0, L_0x1971f60; 1 drivers +v0x1841030_0 .net "sumAB", 0 0, L_0x1971e00; 1 drivers +S_0x18e2a90 .scope generate, "genblk1[2]" "genblk1[2]" 2 47, 2 47 0, S_0x180cd20; + .timescale 0 0; +P_0x183c560 .param/l "i" 0 2 47, +C4<010>; +S_0x18e0a40 .scope module, "addermid" "FullAdder1bit" 2 48, 2 8 0, S_0x18e2a90; + .timescale 0 0; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b0" + .port_info 4 /INPUT 1 "carryin" + .port_info 5 /INPUT 1 "subtract" +L_0x1938db0/d .functor XOR 1, L_0x1973190, L_0x1972380, C4<0>, C4<0>; +L_0x1938db0 .delay 1 (20,20,20) L_0x1938db0/d; +L_0x1972950/d .functor XOR 1, L_0x1973070, L_0x1938db0, C4<0>, C4<0>; +L_0x1972950 .delay 1 (20,20,20) L_0x1972950/d; +L_0x1972ab0/d .functor XOR 1, L_0x1972950, v0x17b6f60_0, C4<0>, C4<0>; +L_0x1972ab0 .delay 1 (20,20,20) L_0x1972ab0/d; +L_0x1972c10/d .functor AND 1, L_0x1973070, L_0x1938db0, C4<1>, C4<1>; +L_0x1972c10 .delay 1 (20,20,20) L_0x1972c10/d; +L_0x1972d70/d .functor AND 1, L_0x1972950, v0x17b6f60_0, C4<1>, C4<1>; +L_0x1972d70 .delay 1 (20,20,20) L_0x1972d70/d; +L_0x1972ed0/d .functor OR 1, L_0x1972c10, L_0x1972d70, C4<0>, C4<0>; +L_0x1972ed0 .delay 1 (20,20,20) L_0x1972ed0/d; +v0x18450a0_0 .net "a", 0 0, L_0x1973070; 1 drivers +v0x18472f0_0 .net "b", 0 0, L_0x1938db0; 1 drivers +v0x1847780_0 .net "b0", 0 0, L_0x1973190; 1 drivers +v0x1847e80_0 .net "carryin", 0 0, v0x17b6f60_0; alias, 1 drivers +v0x1848350_0 .net "carryout", 0 0, L_0x1972ed0; alias, 1 drivers +v0x1848a20_0 .net "cout1", 0 0, L_0x1972c10; 1 drivers +v0x1848ef0_0 .net "cout2", 0 0, L_0x1972d70; 1 drivers +v0x18495c0_0 .net "subtract", 0 0, L_0x1972380; alias, 1 drivers +v0x1849a90_0 .net "sum", 0 0, L_0x1972ab0; 1 drivers +v0x184a630_0 .net "sumAB", 0 0, L_0x1972950; 1 drivers +S_0x18de9f0 .scope generate, "genblk1[3]" "genblk1[3]" 2 47, 2 47 0, S_0x180cd20; + .timescale 0 0; +P_0x1848fb0 .param/l "i" 0 2 47, +C4<011>; +S_0x18dc9a0 .scope module, "addermid" "FullAdder1bit" 2 48, 2 8 0, S_0x18de9f0; + .timescale 0 0; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b0" + .port_info 4 /INPUT 1 "carryin" + .port_info 5 /INPUT 1 "subtract" +L_0x1973280/d .functor XOR 1, L_0x1973bc0, L_0x1972ed0, C4<0>, C4<0>; +L_0x1973280 .delay 1 (20,20,20) L_0x1973280/d; +L_0x1973380/d .functor XOR 1, L_0x1973aa0, L_0x1973280, C4<0>, C4<0>; +L_0x1973380 .delay 1 (20,20,20) L_0x1973380/d; +L_0x19734e0/d .functor XOR 1, L_0x1973380, v0x17b6f60_0, C4<0>, C4<0>; +L_0x19734e0 .delay 1 (20,20,20) L_0x19734e0/d; +L_0x1973640/d .functor AND 1, L_0x1973aa0, L_0x1973280, C4<1>, C4<1>; +L_0x1973640 .delay 1 (20,20,20) L_0x1973640/d; +L_0x19737a0/d .functor AND 1, L_0x1973380, v0x17b6f60_0, C4<1>, C4<1>; +L_0x19737a0 .delay 1 (20,20,20) L_0x19737a0/d; +L_0x1973900/d .functor OR 1, L_0x1973640, L_0x19737a0, C4<0>, C4<0>; +L_0x1973900 .delay 1 (20,20,20) L_0x1973900/d; +v0x184b1d0_0 .net "a", 0 0, L_0x1973aa0; 1 drivers +v0x184b8a0_0 .net "b", 0 0, L_0x1973280; 1 drivers +v0x184bd70_0 .net "b0", 0 0, L_0x1973bc0; 1 drivers +v0x184c440_0 .net "carryin", 0 0, v0x17b6f60_0; alias, 1 drivers +v0x184c910_0 .net "carryout", 0 0, L_0x1973900; alias, 1 drivers +v0x184cfe0_0 .net "cout1", 0 0, L_0x1973640; 1 drivers +v0x184d4b0_0 .net "cout2", 0 0, L_0x19737a0; 1 drivers +v0x184db80_0 .net "subtract", 0 0, L_0x1972ed0; alias, 1 drivers +v0x184e050_0 .net "sum", 0 0, L_0x19734e0; 1 drivers +v0x184e720_0 .net "sumAB", 0 0, L_0x1973380; 1 drivers +S_0x18da950 .scope generate, "genblk1[4]" "genblk1[4]" 2 47, 2 47 0, S_0x180cd20; + .timescale 0 0; +P_0x184d570 .param/l "i" 0 2 47, +C4<0100>; +S_0x18d8900 .scope module, "addermid" "FullAdder1bit" 2 48, 2 8 0, S_0x18da950; + .timescale 0 0; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b0" + .port_info 4 /INPUT 1 "carryin" + .port_info 5 /INPUT 1 "subtract" +L_0x1973cf0/d .functor XOR 1, L_0x1974630, L_0x1973900, C4<0>, C4<0>; +L_0x1973cf0 .delay 1 (20,20,20) L_0x1973cf0/d; +L_0x1973df0/d .functor XOR 1, L_0x1974510, L_0x1973cf0, C4<0>, C4<0>; +L_0x1973df0 .delay 1 (20,20,20) L_0x1973df0/d; +L_0x1973f50/d .functor XOR 1, L_0x1973df0, v0x17b6f60_0, C4<0>, C4<0>; +L_0x1973f50 .delay 1 (20,20,20) L_0x1973f50/d; +L_0x19740b0/d .functor AND 1, L_0x1974510, L_0x1973cf0, C4<1>, C4<1>; +L_0x19740b0 .delay 1 (20,20,20) L_0x19740b0/d; +L_0x1974210/d .functor AND 1, L_0x1973df0, v0x17b6f60_0, C4<1>, C4<1>; +L_0x1974210 .delay 1 (20,20,20) L_0x1974210/d; +L_0x1974370/d .functor OR 1, L_0x19740b0, L_0x1974210, C4<0>, C4<0>; +L_0x1974370 .delay 1 (20,20,20) L_0x1974370/d; +v0x184f2c0_0 .net "a", 0 0, L_0x1974510; 1 drivers +v0x184f790_0 .net "b", 0 0, L_0x1973cf0; 1 drivers +v0x184fe60_0 .net "b0", 0 0, L_0x1974630; 1 drivers +v0x1850330_0 .net "carryin", 0 0, v0x17b6f60_0; alias, 1 drivers +v0x1850a00_0 .net "carryout", 0 0, L_0x1974370; alias, 1 drivers +v0x1850ed0_0 .net "cout1", 0 0, L_0x19740b0; 1 drivers +v0x18515a0_0 .net "cout2", 0 0, L_0x1974210; 1 drivers +v0x1851a70_0 .net "subtract", 0 0, L_0x1973900; alias, 1 drivers +v0x18520f0_0 .net "sum", 0 0, L_0x1973f50; 1 drivers +v0x1852ce0_0 .net "sumAB", 0 0, L_0x1973df0; 1 drivers +S_0x18d68b0 .scope generate, "genblk1[5]" "genblk1[5]" 2 47, 2 47 0, S_0x180cd20; + .timescale 0 0; +P_0x184f850 .param/l "i" 0 2 47, +C4<0101>; +S_0x18d4bf0 .scope module, "addermid" "FullAdder1bit" 2 48, 2 8 0, S_0x18d68b0; + .timescale 0 0; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b0" + .port_info 4 /INPUT 1 "carryin" + .port_info 5 /INPUT 1 "subtract" +L_0x1974770/d .functor XOR 1, L_0x19750b0, L_0x1974370, C4<0>, C4<0>; +L_0x1974770 .delay 1 (20,20,20) L_0x1974770/d; +L_0x1974870/d .functor XOR 1, L_0x1974f50, L_0x1974770, C4<0>, C4<0>; +L_0x1974870 .delay 1 (20,20,20) L_0x1974870/d; +L_0x19749d0/d .functor XOR 1, L_0x1974870, v0x17b6f60_0, C4<0>, C4<0>; +L_0x19749d0 .delay 1 (20,20,20) L_0x19749d0/d; +L_0x1974b30/d .functor AND 1, L_0x1974f50, L_0x1974770, C4<1>, C4<1>; +L_0x1974b30 .delay 1 (20,20,20) L_0x1974b30/d; +L_0x1974c90/d .functor AND 1, L_0x1974870, v0x17b6f60_0, C4<1>, C4<1>; +L_0x1974c90 .delay 1 (20,20,20) L_0x1974c90/d; +L_0x1974df0/d .functor OR 1, L_0x1974b30, L_0x1974c90, C4<0>, C4<0>; +L_0x1974df0 .delay 1 (20,20,20) L_0x1974df0/d; +v0x18538a0_0 .net "a", 0 0, L_0x1974f50; 1 drivers +v0x1853d80_0 .net "b", 0 0, L_0x1974770; 1 drivers +v0x1854450_0 .net "b0", 0 0, L_0x19750b0; 1 drivers +v0x1854930_0 .net "carryin", 0 0, v0x17b6f60_0; alias, 1 drivers +v0x18554e0_0 .net "carryout", 0 0, L_0x1974df0; alias, 1 drivers +v0x1855bb0_0 .net "cout1", 0 0, L_0x1974b30; 1 drivers +v0x1856090_0 .net "cout2", 0 0, L_0x1974c90; 1 drivers +v0x1856760_0 .net "subtract", 0 0, L_0x1974370; alias, 1 drivers +v0x1856c40_0 .net "sum", 0 0, L_0x19749d0; 1 drivers +v0x1857310_0 .net "sumAB", 0 0, L_0x1974870; 1 drivers +S_0x18d4870 .scope generate, "genblk1[6]" "genblk1[6]" 2 47, 2 47 0, S_0x180cd20; + .timescale 0 0; +P_0x1856150 .param/l "i" 0 2 47, +C4<0110>; +S_0x18d2bb0 .scope module, "addermid" "FullAdder1bit" 2 48, 2 8 0, S_0x18d4870; + .timescale 0 0; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b0" + .port_info 4 /INPUT 1 "carryin" + .port_info 5 /INPUT 1 "subtract" +L_0x1975150/d .functor XOR 1, L_0x1975a40, L_0x1974df0, C4<0>, C4<0>; +L_0x1975150 .delay 1 (20,20,20) L_0x1975150/d; +L_0x1975250/d .functor XOR 1, L_0x1975920, L_0x1975150, C4<0>, C4<0>; +L_0x1975250 .delay 1 (20,20,20) L_0x1975250/d; +L_0x1975360/d .functor XOR 1, L_0x1975250, v0x17b6f60_0, C4<0>, C4<0>; +L_0x1975360 .delay 1 (20,20,20) L_0x1975360/d; +L_0x19754c0/d .functor AND 1, L_0x1975920, L_0x1975150, C4<1>, C4<1>; +L_0x19754c0 .delay 1 (20,20,20) L_0x19754c0/d; +L_0x1975620/d .functor AND 1, L_0x1975250, v0x17b6f60_0, C4<1>, C4<1>; +L_0x1975620 .delay 1 (20,20,20) L_0x1975620/d; +L_0x1975780/d .functor OR 1, L_0x19754c0, L_0x1975620, C4<0>, C4<0>; +L_0x1975780 .delay 1 (20,20,20) L_0x1975780/d; +v0x1857ec0_0 .net "a", 0 0, L_0x1975920; 1 drivers +v0x18583a0_0 .net "b", 0 0, L_0x1975150; 1 drivers +v0x1858a70_0 .net "b0", 0 0, L_0x1975a40; 1 drivers +v0x1858f50_0 .net "carryin", 0 0, v0x17b6f60_0; alias, 1 drivers +v0x1859620_0 .net "carryout", 0 0, L_0x1975780; alias, 1 drivers +v0x1859b00_0 .net "cout1", 0 0, L_0x19754c0; 1 drivers +v0x185a1d0_0 .net "cout2", 0 0, L_0x1975620; 1 drivers +v0x185a6b0_0 .net "subtract", 0 0, L_0x1974df0; alias, 1 drivers +v0x185ad80_0 .net "sum", 0 0, L_0x1975360; 1 drivers +v0x185b930_0 .net "sumAB", 0 0, L_0x1975250; 1 drivers +S_0x18d2830 .scope generate, "genblk1[7]" "genblk1[7]" 2 47, 2 47 0, S_0x180cd20; + .timescale 0 0; +P_0x183e260 .param/l "i" 0 2 47, +C4<0111>; +S_0x18c09d0 .scope module, "addermid" "FullAdder1bit" 2 48, 2 8 0, S_0x18d2830; + .timescale 0 0; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b0" + .port_info 4 /INPUT 1 "carryin" + .port_info 5 /INPUT 1 "subtract" +L_0x1975ba0/d .functor XOR 1, L_0x1976490, L_0x1975780, C4<0>, C4<0>; +L_0x1975ba0 .delay 1 (20,20,20) L_0x1975ba0/d; +L_0x1975ca0/d .functor XOR 1, L_0x1976370, L_0x1975ba0, C4<0>, C4<0>; +L_0x1975ca0 .delay 1 (20,20,20) L_0x1975ca0/d; +L_0x1975e00/d .functor XOR 1, L_0x1975ca0, v0x17b6f60_0, C4<0>, C4<0>; +L_0x1975e00 .delay 1 (20,20,20) L_0x1975e00/d; +L_0x1975f60/d .functor AND 1, L_0x1976370, L_0x1975ba0, C4<1>, C4<1>; +L_0x1975f60 .delay 1 (20,20,20) L_0x1975f60/d; +L_0x1976070/d .functor AND 1, L_0x1975ca0, v0x17b6f60_0, C4<1>, C4<1>; +L_0x1976070 .delay 1 (20,20,20) L_0x1976070/d; +L_0x19761d0/d .functor OR 1, L_0x1975f60, L_0x1976070, C4<0>, C4<0>; +L_0x19761d0 .delay 1 (20,20,20) L_0x19761d0/d; +v0x1811ce0_0 .net "a", 0 0, L_0x1976370; 1 drivers +v0x185d4f0_0 .net "b", 0 0, L_0x1975ba0; 1 drivers +v0x185f380_0 .net "b0", 0 0, L_0x1976490; 1 drivers +v0x1813cd0_0 .net "carryin", 0 0, v0x17b6f60_0; alias, 1 drivers +v0x185fec0_0 .net "carryout", 0 0, L_0x19761d0; alias, 1 drivers +v0x1860550_0 .net "cout1", 0 0, L_0x1975f60; 1 drivers +v0x1815d10_0 .net "cout2", 0 0, L_0x1976070; 1 drivers +v0x1817d50_0 .net "subtract", 0 0, L_0x1975780; alias, 1 drivers +v0x1819d90_0 .net "sum", 0 0, L_0x1975e00; 1 drivers +v0x181de10_0 .net "sumAB", 0 0, L_0x1975ca0; 1 drivers +S_0x18c0650 .scope generate, "genblk1[8]" "genblk1[8]" 2 47, 2 47 0, S_0x180cd20; + .timescale 0 0; +P_0x1815dd0 .param/l "i" 0 2 47, +C4<01000>; +S_0x18be990 .scope module, "addermid" "FullAdder1bit" 2 48, 2 8 0, S_0x18c0650; + .timescale 0 0; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b0" + .port_info 4 /INPUT 1 "carryin" + .port_info 5 /INPUT 1 "subtract" +L_0x1975b30/d .functor XOR 1, L_0x1976ed0, L_0x19761d0, C4<0>, C4<0>; +L_0x1975b30 .delay 1 (20,20,20) L_0x1975b30/d; +L_0x1976690/d .functor XOR 1, L_0x1976db0, L_0x1975b30, C4<0>, C4<0>; +L_0x1976690 .delay 1 (20,20,20) L_0x1976690/d; +L_0x19767f0/d .functor XOR 1, L_0x1976690, v0x17b6f60_0, C4<0>, C4<0>; +L_0x19767f0 .delay 1 (20,20,20) L_0x19767f0/d; +L_0x1976950/d .functor AND 1, L_0x1976db0, L_0x1975b30, C4<1>, C4<1>; +L_0x1976950 .delay 1 (20,20,20) L_0x1976950/d; +L_0x1976ab0/d .functor AND 1, L_0x1976690, v0x17b6f60_0, C4<1>, C4<1>; +L_0x1976ab0 .delay 1 (20,20,20) L_0x1976ab0/d; +L_0x1976c10/d .functor OR 1, L_0x1976950, L_0x1976ab0, C4<0>, C4<0>; +L_0x1976c10 .delay 1 (20,20,20) L_0x1976c10/d; +v0x1821e80_0 .net "a", 0 0, L_0x1976db0; 1 drivers +v0x1832050_0 .net "b", 0 0, L_0x1975b30; 1 drivers +v0x1834040_0 .net "b0", 0 0, L_0x1976ed0; 1 drivers +v0x1836090_0 .net "carryin", 0 0, v0x17b6f60_0; alias, 1 drivers +v0x18380e0_0 .net "carryout", 0 0, L_0x1976c10; alias, 1 drivers +v0x183a130_0 .net "cout1", 0 0, L_0x1976950; 1 drivers +v0x183c180_0 .net "cout2", 0 0, L_0x1976ab0; 1 drivers +v0x18614e0_0 .net "subtract", 0 0, L_0x19761d0; alias, 1 drivers +v0x187b8f0_0 .net "sum", 0 0, L_0x19767f0; 1 drivers +v0x187ca10_0 .net "sumAB", 0 0, L_0x1976690; 1 drivers +S_0x18be610 .scope generate, "genblk1[9]" "genblk1[9]" 2 47, 2 47 0, S_0x180cd20; + .timescale 0 0; +P_0x1832110 .param/l "i" 0 2 47, +C4<01001>; +S_0x18bc950 .scope module, "addermid" "FullAdder1bit" 2 48, 2 8 0, S_0x18be610; + .timescale 0 0; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b0" + .port_info 4 /INPUT 1 "carryin" + .port_info 5 /INPUT 1 "subtract" +L_0x1977050/d .functor XOR 1, L_0x1972640, L_0x1976c10, C4<0>, C4<0>; +L_0x1977050 .delay 1 (20,20,20) L_0x1977050/d; +L_0x1977150/d .functor XOR 1, L_0x1977800, L_0x1977050, C4<0>, C4<0>; +L_0x1977150 .delay 1 (20,20,20) L_0x1977150/d; +L_0x19772b0/d .functor XOR 1, L_0x1977150, v0x17b6f60_0, C4<0>, C4<0>; +L_0x19772b0 .delay 1 (20,20,20) L_0x19772b0/d; +L_0x1977410/d .functor AND 1, L_0x1977800, L_0x1977050, C4<1>, C4<1>; +L_0x1977410 .delay 1 (20,20,20) L_0x1977410/d; +L_0x1977570/d .functor AND 1, L_0x1977150, v0x17b6f60_0, C4<1>, C4<1>; +L_0x1977570 .delay 1 (20,20,20) L_0x1977570/d; +L_0x1976580/d .functor OR 1, L_0x1977410, L_0x1977570, C4<0>, C4<0>; +L_0x1976580 .delay 1 (20,20,20) L_0x1976580/d; +v0x187db30_0 .net "a", 0 0, L_0x1977800; 1 drivers +v0x187e3c0_0 .net "b", 0 0, L_0x1977050; 1 drivers +v0x187ec50_0 .net "b0", 0 0, L_0x1972640; 1 drivers +v0x187f4e0_0 .net "carryin", 0 0, v0x17b6f60_0; alias, 1 drivers +v0x187fd70_0 .net "carryout", 0 0, L_0x1976580; alias, 1 drivers +v0x1880600_0 .net "cout1", 0 0, L_0x1977410; 1 drivers +v0x1880e90_0 .net "cout2", 0 0, L_0x1977570; 1 drivers +v0x1881720_0 .net "subtract", 0 0, L_0x1976c10; alias, 1 drivers +v0x1881fb0_0 .net "sum", 0 0, L_0x19772b0; 1 drivers +v0x18830d0_0 .net "sumAB", 0 0, L_0x1977150; 1 drivers +S_0x18bc5d0 .scope generate, "genblk1[10]" "genblk1[10]" 2 47, 2 47 0, S_0x180cd20; + .timescale 0 0; +P_0x1880f50 .param/l "i" 0 2 47, +C4<01010>; +S_0x18ba910 .scope module, "addermid" "FullAdder1bit" 2 48, 2 8 0, S_0x18bc5d0; + .timescale 0 0; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b0" + .port_info 4 /INPUT 1 "carryin" + .port_info 5 /INPUT 1 "subtract" +L_0x1972890/d .functor XOR 1, L_0x1978580, L_0x1976580, C4<0>, C4<0>; +L_0x1972890 .delay 1 (20,20,20) L_0x1972890/d; +L_0x1977d40/d .functor XOR 1, L_0x1978460, L_0x1972890, C4<0>, C4<0>; +L_0x1977d40 .delay 1 (20,20,20) L_0x1977d40/d; +L_0x1977ea0/d .functor XOR 1, L_0x1977d40, v0x17b6f60_0, C4<0>, C4<0>; +L_0x1977ea0 .delay 1 (20,20,20) L_0x1977ea0/d; +L_0x1978000/d .functor AND 1, L_0x1978460, L_0x1972890, C4<1>, C4<1>; +L_0x1978000 .delay 1 (20,20,20) L_0x1978000/d; +L_0x1978160/d .functor AND 1, L_0x1977d40, v0x17b6f60_0, C4<1>, C4<1>; +L_0x1978160 .delay 1 (20,20,20) L_0x1978160/d; +L_0x19782c0/d .functor OR 1, L_0x1978000, L_0x1978160, C4<0>, C4<0>; +L_0x19782c0 .delay 1 (20,20,20) L_0x19782c0/d; +v0x18841f0_0 .net "a", 0 0, L_0x1978460; 1 drivers +v0x1884a80_0 .net "b", 0 0, L_0x1972890; 1 drivers +v0x1885310_0 .net "b0", 0 0, L_0x1978580; 1 drivers +v0x1885ba0_0 .net "carryin", 0 0, v0x17b6f60_0; alias, 1 drivers +v0x1886430_0 .net "carryout", 0 0, L_0x19782c0; alias, 1 drivers +v0x1886cc0_0 .net "cout1", 0 0, L_0x1978000; 1 drivers +v0x1887550_0 .net "cout2", 0 0, L_0x1978160; 1 drivers +v0x1887de0_0 .net "subtract", 0 0, L_0x1976580; alias, 1 drivers +v0x1888670_0 .net "sum", 0 0, L_0x1977ea0; 1 drivers +v0x1889790_0 .net "sumAB", 0 0, L_0x1977d40; 1 drivers +S_0x18ba590 .scope generate, "genblk1[11]" "genblk1[11]" 2 47, 2 47 0, S_0x180cd20; + .timescale 0 0; +P_0x1884b40 .param/l "i" 0 2 47, +C4<01011>; +S_0x1861ba0 .scope module, "addermid" "FullAdder1bit" 2 48, 2 8 0, S_0x18ba590; + .timescale 0 0; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b0" + .port_info 4 /INPUT 1 "carryin" + .port_info 5 /INPUT 1 "subtract" +L_0x19727f0/d .functor XOR 1, L_0x1978ff0, L_0x19782c0, C4<0>, C4<0>; +L_0x19727f0 .delay 1 (20,20,20) L_0x19727f0/d; +L_0x19787b0/d .functor XOR 1, L_0x1978ed0, L_0x19727f0, C4<0>, C4<0>; +L_0x19787b0 .delay 1 (20,20,20) L_0x19787b0/d; +L_0x1978910/d .functor XOR 1, L_0x19787b0, v0x17b6f60_0, C4<0>, C4<0>; +L_0x1978910 .delay 1 (20,20,20) L_0x1978910/d; +L_0x1978a70/d .functor AND 1, L_0x1978ed0, L_0x19727f0, C4<1>, C4<1>; +L_0x1978a70 .delay 1 (20,20,20) L_0x1978a70/d; +L_0x1978bd0/d .functor AND 1, L_0x19787b0, v0x17b6f60_0, C4<1>, C4<1>; +L_0x1978bd0 .delay 1 (20,20,20) L_0x1978bd0/d; +L_0x1978d30/d .functor OR 1, L_0x1978a70, L_0x1978bd0, C4<0>, C4<0>; +L_0x1978d30 .delay 1 (20,20,20) L_0x1978d30/d; +v0x188a8b0_0 .net "a", 0 0, L_0x1978ed0; 1 drivers +v0x188b140_0 .net "b", 0 0, L_0x19727f0; 1 drivers +v0x188b9d0_0 .net "b0", 0 0, L_0x1978ff0; 1 drivers +v0x188bd10_0 .net "carryin", 0 0, v0x17b6f60_0; alias, 1 drivers +v0x188ce20_0 .net "carryout", 0 0, L_0x1978d30; alias, 1 drivers +v0x18a4f30_0 .net "cout1", 0 0, L_0x1978a70; 1 drivers +v0x18a57c0_0 .net "cout2", 0 0, L_0x1978bd0; 1 drivers +v0x18a6050_0 .net "subtract", 0 0, L_0x19782c0; alias, 1 drivers +v0x18a68e0_0 .net "sum", 0 0, L_0x1978910; 1 drivers +v0x18a7a00_0 .net "sumAB", 0 0, L_0x19787b0; 1 drivers +S_0x18617f0 .scope generate, "genblk1[12]" "genblk1[12]" 2 47, 2 47 0, S_0x180cd20; + .timescale 0 0; +P_0x18a5880 .param/l "i" 0 2 47, +C4<01100>; +S_0x1840920 .scope module, "addermid" "FullAdder1bit" 2 48, 2 8 0, S_0x18617f0; + .timescale 0 0; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b0" + .port_info 4 /INPUT 1 "carryin" + .port_info 5 /INPUT 1 "subtract" +L_0x1978670/d .functor XOR 1, L_0x1979a70, L_0x1978d30, C4<0>, C4<0>; +L_0x1978670 .delay 1 (20,20,20) L_0x1978670/d; +L_0x1979230/d .functor XOR 1, L_0x1979910, L_0x1978670, C4<0>, C4<0>; +L_0x1979230 .delay 1 (20,20,20) L_0x1979230/d; +L_0x1979390/d .functor XOR 1, L_0x1979230, v0x17b6f60_0, C4<0>, C4<0>; +L_0x1979390 .delay 1 (20,20,20) L_0x1979390/d; +L_0x19794f0/d .functor AND 1, L_0x1979910, L_0x1978670, C4<1>, C4<1>; +L_0x19794f0 .delay 1 (20,20,20) L_0x19794f0/d; +L_0x1979650/d .functor AND 1, L_0x1979230, v0x17b6f60_0, C4<1>, C4<1>; +L_0x1979650 .delay 1 (20,20,20) L_0x1979650/d; +L_0x19797b0/d .functor OR 1, L_0x19794f0, L_0x1979650, C4<0>, C4<0>; +L_0x19797b0 .delay 1 (20,20,20) L_0x19797b0/d; +v0x18a8b20_0 .net "a", 0 0, L_0x1979910; 1 drivers +v0x18a93b0_0 .net "b", 0 0, L_0x1978670; 1 drivers +v0x18a9c40_0 .net "b0", 0 0, L_0x1979a70; 1 drivers +v0x18aa4d0_0 .net "carryin", 0 0, v0x17b6f60_0; alias, 1 drivers +v0x18aad60_0 .net "carryout", 0 0, L_0x19797b0; alias, 1 drivers +v0x18ab5f0_0 .net "cout1", 0 0, L_0x19794f0; 1 drivers +v0x18ac710_0 .net "cout2", 0 0, L_0x1979650; 1 drivers +v0x18acfa0_0 .net "subtract", 0 0, L_0x1978d30; alias, 1 drivers +v0x18ad830_0 .net "sum", 0 0, L_0x1979390; 1 drivers +v0x18ae950_0 .net "sumAB", 0 0, L_0x1979230; 1 drivers +S_0x183e8d0 .scope generate, "genblk1[13]" "genblk1[13]" 2 47, 2 47 0, S_0x180cd20; + .timescale 0 0; +P_0x18a9470 .param/l "i" 0 2 47, +C4<01101>; +S_0x183c880 .scope module, "addermid" "FullAdder1bit" 2 48, 2 8 0, S_0x183e8d0; + .timescale 0 0; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b0" + .port_info 4 /INPUT 1 "carryin" + .port_info 5 /INPUT 1 "subtract" +L_0x19790e0/d .functor XOR 1, L_0x197a460, L_0x19797b0, C4<0>, C4<0>; +L_0x19790e0 .delay 1 (20,20,20) L_0x19790e0/d; +L_0x1979c70/d .functor XOR 1, L_0x197a340, L_0x19790e0, C4<0>, C4<0>; +L_0x1979c70 .delay 1 (20,20,20) L_0x1979c70/d; +L_0x1979d80/d .functor XOR 1, L_0x1979c70, v0x17b6f60_0, C4<0>, C4<0>; +L_0x1979d80 .delay 1 (20,20,20) L_0x1979d80/d; +L_0x1979ee0/d .functor AND 1, L_0x197a340, L_0x19790e0, C4<1>, C4<1>; +L_0x1979ee0 .delay 1 (20,20,20) L_0x1979ee0/d; +L_0x197a040/d .functor AND 1, L_0x1979c70, v0x17b6f60_0, C4<1>, C4<1>; +L_0x197a040 .delay 1 (20,20,20) L_0x197a040/d; +L_0x197a1a0/d .functor OR 1, L_0x1979ee0, L_0x197a040, C4<0>, C4<0>; +L_0x197a1a0 .delay 1 (20,20,20) L_0x197a1a0/d; +v0x18afa70_0 .net "a", 0 0, L_0x197a340; 1 drivers +v0x18b0300_0 .net "b", 0 0, L_0x19790e0; 1 drivers +v0x18b0b90_0 .net "b0", 0 0, L_0x197a460; 1 drivers +v0x18b1420_0 .net "carryin", 0 0, v0x17b6f60_0; alias, 1 drivers +v0x18b1cb0_0 .net "carryout", 0 0, L_0x197a1a0; alias, 1 drivers +v0x18b2540_0 .net "cout1", 0 0, L_0x1979ee0; 1 drivers +v0x18b2dd0_0 .net "cout2", 0 0, L_0x197a040; 1 drivers +v0x18b3660_0 .net "subtract", 0 0, L_0x19797b0; alias, 1 drivers +v0x18b3ef0_0 .net "sum", 0 0, L_0x1979d80; 1 drivers +v0x18b5010_0 .net "sumAB", 0 0, L_0x1979c70; 1 drivers +S_0x183a830 .scope generate, "genblk1[14]" "genblk1[14]" 2 47, 2 47 0, S_0x180cd20; + .timescale 0 0; +P_0x18b2e90 .param/l "i" 0 2 47, +C4<01110>; +S_0x18387e0 .scope module, "addermid" "FullAdder1bit" 2 48, 2 8 0, S_0x183a830; + .timescale 0 0; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b0" + .port_info 4 /INPUT 1 "carryin" + .port_info 5 /INPUT 1 "subtract" +L_0x1979b10/d .functor XOR 1, L_0x167fcb0, L_0x197a1a0, C4<0>, C4<0>; +L_0x1979b10 .delay 1 (20,20,20) L_0x1979b10/d; +L_0x197a6c0/d .functor XOR 1, L_0x167fb90, L_0x1979b10, C4<0>, C4<0>; +L_0x197a6c0 .delay 1 (20,20,20) L_0x197a6c0/d; +L_0x197a7d0/d .functor XOR 1, L_0x197a6c0, v0x17b6f60_0, C4<0>, C4<0>; +L_0x197a7d0 .delay 1 (20,20,20) L_0x197a7d0/d; +L_0x197a930/d .functor AND 1, L_0x167fb90, L_0x1979b10, C4<1>, C4<1>; +L_0x197a930 .delay 1 (20,20,20) L_0x197a930/d; +L_0x197aa90/d .functor AND 1, L_0x197a6c0, v0x17b6f60_0, C4<1>, C4<1>; +L_0x197aa90 .delay 1 (20,20,20) L_0x197aa90/d; +L_0x167f9f0/d .functor OR 1, L_0x197a930, L_0x197aa90, C4<0>, C4<0>; +L_0x167f9f0 .delay 1 (20,20,20) L_0x167f9f0/d; +v0x18b8b80_0 .net "a", 0 0, L_0x167fb90; 1 drivers +v0x18bac00_0 .net "b", 0 0, L_0x1979b10; 1 drivers +v0x18bcc40_0 .net "b0", 0 0, L_0x167fcb0; 1 drivers +v0x18bec80_0 .net "carryin", 0 0, v0x17b6f60_0; alias, 1 drivers +v0x18c0cc0_0 .net "carryout", 0 0, L_0x167f9f0; alias, 1 drivers +v0x18c2d00_0 .net "cout1", 0 0, L_0x197a930; 1 drivers +v0x18c4d30_0 .net "cout2", 0 0, L_0x197aa90; 1 drivers +v0x18c6d60_0 .net "subtract", 0 0, L_0x197a1a0; alias, 1 drivers +v0x18c8d90_0 .net "sum", 0 0, L_0x197a7d0; 1 drivers +v0x18ccdf0_0 .net "sumAB", 0 0, L_0x197a6c0; 1 drivers +S_0x1836790 .scope generate, "genblk1[15]" "genblk1[15]" 2 47, 2 47 0, S_0x180cd20; + .timescale 0 0; +P_0x18bacc0 .param/l "i" 0 2 47, +C4<01111>; +S_0x1834740 .scope module, "addermid" "FullAdder1bit" 2 48, 2 8 0, S_0x1836790; + .timescale 0 0; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b0" + .port_info 4 /INPUT 1 "carryin" + .port_info 5 /INPUT 1 "subtract" +L_0x167fda0/d .functor XOR 1, L_0x197bce0, L_0x167f9f0, C4<0>, C4<0>; +L_0x167fda0 .delay 1 (20,20,20) L_0x167fda0/d; +L_0x197b4f0/d .functor XOR 1, L_0x197bbc0, L_0x167fda0, C4<0>, C4<0>; +L_0x197b4f0 .delay 1 (20,20,20) L_0x197b4f0/d; +L_0x197b600/d .functor XOR 1, L_0x197b4f0, v0x17b6f60_0, C4<0>, C4<0>; +L_0x197b600 .delay 1 (20,20,20) L_0x197b600/d; +L_0x197b760/d .functor AND 1, L_0x197bbc0, L_0x167fda0, C4<1>, C4<1>; +L_0x197b760 .delay 1 (20,20,20) L_0x197b760/d; +L_0x197b8c0/d .functor AND 1, L_0x197b4f0, v0x17b6f60_0, C4<1>, C4<1>; +L_0x197b8c0 .delay 1 (20,20,20) L_0x197b8c0/d; +L_0x197ba20/d .functor OR 1, L_0x197b760, L_0x197b8c0, C4<0>, C4<0>; +L_0x197ba20 .delay 1 (20,20,20) L_0x197ba20/d; +v0x18d2ea0_0 .net "a", 0 0, L_0x197bbc0; 1 drivers +v0x18d4ee0_0 .net "b", 0 0, L_0x167fda0; 1 drivers +v0x18d64f0_0 .net "b0", 0 0, L_0x197bce0; 1 drivers +v0x18d6fc0_0 .net "carryin", 0 0, v0x17b6f60_0; alias, 1 drivers +v0x18d8520_0 .net "carryout", 0 0, L_0x197ba20; alias, 1 drivers +v0x18d9010_0 .net "cout1", 0 0, L_0x197b760; 1 drivers +v0x18da570_0 .net "cout2", 0 0, L_0x197b8c0; 1 drivers +v0x18db060_0 .net "subtract", 0 0, L_0x167f9f0; alias, 1 drivers +v0x18dc5c0_0 .net "sum", 0 0, L_0x197b600; 1 drivers +v0x18dd0b0_0 .net "sumAB", 0 0, L_0x197b4f0; 1 drivers +S_0x18326f0 .scope generate, "genblk1[16]" "genblk1[16]" 2 47, 2 47 0, S_0x180cd20; + .timescale 0 0; +P_0x18da630 .param/l "i" 0 2 47, +C4<010000>; +S_0x18208a0 .scope module, "addermid" "FullAdder1bit" 2 48, 2 8 0, S_0x18326f0; + .timescale 0 0; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b0" + .port_info 4 /INPUT 1 "carryin" + .port_info 5 /INPUT 1 "subtract" +L_0x197b400/d .functor XOR 1, L_0x197c750, L_0x197ba20, C4<0>, C4<0>; +L_0x197b400 .delay 1 (20,20,20) L_0x197b400/d; +L_0x197bf60/d .functor XOR 1, L_0x197c630, L_0x197b400, C4<0>, C4<0>; +L_0x197bf60 .delay 1 (20,20,20) L_0x197bf60/d; +L_0x197c070/d .functor XOR 1, L_0x197bf60, v0x17b6f60_0, C4<0>, C4<0>; +L_0x197c070 .delay 1 (20,20,20) L_0x197c070/d; +L_0x197c1d0/d .functor AND 1, L_0x197c630, L_0x197b400, C4<1>, C4<1>; +L_0x197c1d0 .delay 1 (20,20,20) L_0x197c1d0/d; +L_0x197c330/d .functor AND 1, L_0x197bf60, v0x17b6f60_0, C4<1>, C4<1>; +L_0x197c330 .delay 1 (20,20,20) L_0x197c330/d; +L_0x197c490/d .functor OR 1, L_0x197c1d0, L_0x197c330, C4<0>, C4<0>; +L_0x197c490 .delay 1 (20,20,20) L_0x197c490/d; +v0x18df100_0 .net "a", 0 0, L_0x197c630; 1 drivers +v0x18e0660_0 .net "b", 0 0, L_0x197b400; 1 drivers +v0x18e1150_0 .net "b0", 0 0, L_0x197c750; 1 drivers +v0x18e31a0_0 .net "carryin", 0 0, v0x17b6f60_0; alias, 1 drivers +v0x18e51d0_0 .net "carryout", 0 0, L_0x197c490; alias, 1 drivers +v0x18e7200_0 .net "cout1", 0 0, L_0x197c1d0; 1 drivers +v0x18e9230_0 .net "cout2", 0 0, L_0x197c330; 1 drivers +v0x18eb260_0 .net "subtract", 0 0, L_0x197ba20; alias, 1 drivers +v0x18ed290_0 .net "sum", 0 0, L_0x197c070; 1 drivers +v0x18f12f0_0 .net "sumAB", 0 0, L_0x197bf60; 1 drivers +S_0x1820520 .scope generate, "genblk1[17]" "genblk1[17]" 2 47, 2 47 0, S_0x180cd20; + .timescale 0 0; +P_0x18f13b0 .param/l "i" 0 2 47, +C4<010001>; +S_0x181e870 .scope module, "addermid" "FullAdder1bit" 2 48, 2 8 0, S_0x1820520; + .timescale 0 0; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b0" + .port_info 4 /INPUT 1 "carryin" + .port_info 5 /INPUT 1 "subtract" +L_0x197bdd0/d .functor XOR 1, L_0x197d190, L_0x197c490, C4<0>, C4<0>; +L_0x197bdd0 .delay 1 (20,20,20) L_0x197bdd0/d; +L_0x197c950/d .functor XOR 1, L_0x197d070, L_0x197bdd0, C4<0>, C4<0>; +L_0x197c950 .delay 1 (20,20,20) L_0x197c950/d; +L_0x197cab0/d .functor XOR 1, L_0x197c950, v0x17b6f60_0, C4<0>, C4<0>; +L_0x197cab0 .delay 1 (20,20,20) L_0x197cab0/d; +L_0x197cc10/d .functor AND 1, L_0x197d070, L_0x197bdd0, C4<1>, C4<1>; +L_0x197cc10 .delay 1 (20,20,20) L_0x197cc10/d; +L_0x197cd70/d .functor AND 1, L_0x197c950, v0x17b6f60_0, C4<1>, C4<1>; +L_0x197cd70 .delay 1 (20,20,20) L_0x197cd70/d; +L_0x197ced0/d .functor OR 1, L_0x197cc10, L_0x197cd70, C4<0>, C4<0>; +L_0x197ced0 .delay 1 (20,20,20) L_0x197ced0/d; +v0x18f3520_0 .net "a", 0 0, L_0x197d070; 1 drivers +v0x18f4030_0 .net "b", 0 0, L_0x197bdd0; 1 drivers +v0x18f4c40_0 .net "b0", 0 0, L_0x197d190; 1 drivers +v0x18f51b0_0 .net "carryin", 0 0, v0x17b6f60_0; alias, 1 drivers +v0x18f57d0_0 .net "carryout", 0 0, L_0x197ced0; alias, 1 drivers +v0x18f63a0_0 .net "cout1", 0 0, L_0x197cc10; 1 drivers +v0x18f6910_0 .net "cout2", 0 0, L_0x197cd70; 1 drivers +v0x18f6f30_0 .net "subtract", 0 0, L_0x197c490; alias, 1 drivers +v0x18f7b00_0 .net "sum", 0 0, L_0x197cab0; 1 drivers +v0x18f8690_0 .net "sumAB", 0 0, L_0x197c950; 1 drivers +S_0x181e4f0 .scope generate, "genblk1[18]" "genblk1[18]" 2 47, 2 47 0, S_0x180cd20; + .timescale 0 0; +P_0x18f8750 .param/l "i" 0 2 47, +C4<010010>; +S_0x181c830 .scope module, "addermid" "FullAdder1bit" 2 48, 2 8 0, S_0x181e4f0; + .timescale 0 0; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b0" + .port_info 4 /INPUT 1 "carryin" + .port_info 5 /INPUT 1 "subtract" +L_0x197c840/d .functor XOR 1, L_0x197dbe0, L_0x197ced0, C4<0>, C4<0>; +L_0x197c840 .delay 1 (20,20,20) L_0x197c840/d; +L_0x197d3a0/d .functor XOR 1, L_0x197dac0, L_0x197c840, C4<0>, C4<0>; +L_0x197d3a0 .delay 1 (20,20,20) L_0x197d3a0/d; +L_0x197d500/d .functor XOR 1, L_0x197d3a0, v0x17b6f60_0, C4<0>, C4<0>; +L_0x197d500 .delay 1 (20,20,20) L_0x197d500/d; +L_0x197d660/d .functor AND 1, L_0x197dac0, L_0x197c840, C4<1>, C4<1>; +L_0x197d660 .delay 1 (20,20,20) L_0x197d660/d; +L_0x197d7c0/d .functor AND 1, L_0x197d3a0, v0x17b6f60_0, C4<1>, C4<1>; +L_0x197d7c0 .delay 1 (20,20,20) L_0x197d7c0/d; +L_0x197d920/d .functor OR 1, L_0x197d660, L_0x197d7c0, C4<0>, C4<0>; +L_0x197d920 .delay 1 (20,20,20) L_0x197d920/d; +v0x18f9260_0 .net "a", 0 0, L_0x197dac0; 1 drivers +v0x18f9790_0 .net "b", 0 0, L_0x197c840; 1 drivers +v0x18f9e10_0 .net "b0", 0 0, L_0x197dbe0; 1 drivers +v0x18fa340_0 .net "carryin", 0 0, v0x17b6f60_0; alias, 1 drivers +v0x18fa9c0_0 .net "carryout", 0 0, L_0x197d920; alias, 1 drivers +v0x18faef0_0 .net "cout1", 0 0, L_0x197d660; 1 drivers +v0x18fb570_0 .net "cout2", 0 0, L_0x197d7c0; 1 drivers +v0x18fbaa0_0 .net "subtract", 0 0, L_0x197ced0; alias, 1 drivers +v0x18fc120_0 .net "sum", 0 0, L_0x197d500; 1 drivers +v0x18fccd0_0 .net "sumAB", 0 0, L_0x197d3a0; 1 drivers +S_0x181c4b0 .scope generate, "genblk1[19]" "genblk1[19]" 2 47, 2 47 0, S_0x180cd20; + .timescale 0 0; +P_0x18fcd90 .param/l "i" 0 2 47, +C4<010011>; +S_0x181a7f0 .scope module, "addermid" "FullAdder1bit" 2 48, 2 8 0, S_0x181c4b0; + .timescale 0 0; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b0" + .port_info 4 /INPUT 1 "carryin" + .port_info 5 /INPUT 1 "subtract" +L_0x197d280/d .functor XOR 1, L_0x197e640, L_0x197d920, C4<0>, C4<0>; +L_0x197d280 .delay 1 (20,20,20) L_0x197d280/d; +L_0x197de00/d .functor XOR 1, L_0x197e520, L_0x197d280, C4<0>, C4<0>; +L_0x197de00 .delay 1 (20,20,20) L_0x197de00/d; +L_0x197df60/d .functor XOR 1, L_0x197de00, v0x17b6f60_0, C4<0>, C4<0>; +L_0x197df60 .delay 1 (20,20,20) L_0x197df60/d; +L_0x197e0c0/d .functor AND 1, L_0x197e520, L_0x197d280, C4<1>, C4<1>; +L_0x197e0c0 .delay 1 (20,20,20) L_0x197e0c0/d; +L_0x197e220/d .functor AND 1, L_0x197de00, v0x17b6f60_0, C4<1>, C4<1>; +L_0x197e220 .delay 1 (20,20,20) L_0x197e220/d; +L_0x197e380/d .functor OR 1, L_0x197e0c0, L_0x197e220, C4<0>, C4<0>; +L_0x197e380 .delay 1 (20,20,20) L_0x197e380/d; +v0x18fd880_0 .net "a", 0 0, L_0x197e520; 1 drivers +v0x18fddb0_0 .net "b", 0 0, L_0x197d280; 1 drivers +v0x18fe430_0 .net "b0", 0 0, L_0x197e640; 1 drivers +v0x18fe960_0 .net "carryin", 0 0, v0x17b6f60_0; alias, 1 drivers +v0x18ff020_0 .net "carryout", 0 0, L_0x197e380; alias, 1 drivers +v0x18ff510_0 .net "cout1", 0 0, L_0x197e0c0; 1 drivers +v0x18ffbe0_0 .net "cout2", 0 0, L_0x197e220; 1 drivers +v0x19000c0_0 .net "subtract", 0 0, L_0x197d920; alias, 1 drivers +v0x1900790_0 .net "sum", 0 0, L_0x197df60; 1 drivers +v0x1901340_0 .net "sumAB", 0 0, L_0x197de00; 1 drivers +S_0x181a470 .scope generate, "genblk1[20]" "genblk1[20]" 2 47, 2 47 0, S_0x180cd20; + .timescale 0 0; +P_0x1901400 .param/l "i" 0 2 47, +C4<010100>; +S_0x18187b0 .scope module, "addermid" "FullAdder1bit" 2 48, 2 8 0, S_0x181a470; + .timescale 0 0; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b0" + .port_info 4 /INPUT 1 "carryin" + .port_info 5 /INPUT 1 "subtract" +L_0x197dcd0/d .functor XOR 1, L_0x197f0b0, L_0x197e380, C4<0>, C4<0>; +L_0x197dcd0 .delay 1 (20,20,20) L_0x197dcd0/d; +L_0x197e870/d .functor XOR 1, L_0x197ef90, L_0x197dcd0, C4<0>, C4<0>; +L_0x197e870 .delay 1 (20,20,20) L_0x197e870/d; +L_0x197e9d0/d .functor XOR 1, L_0x197e870, v0x17b6f60_0, C4<0>, C4<0>; +L_0x197e9d0 .delay 1 (20,20,20) L_0x197e9d0/d; +L_0x197eb30/d .functor AND 1, L_0x197ef90, L_0x197dcd0, C4<1>, C4<1>; +L_0x197eb30 .delay 1 (20,20,20) L_0x197eb30/d; +L_0x197ec90/d .functor AND 1, L_0x197e870, v0x17b6f60_0, C4<1>, C4<1>; +L_0x197ec90 .delay 1 (20,20,20) L_0x197ec90/d; +L_0x197edf0/d .functor OR 1, L_0x197eb30, L_0x197ec90, C4<0>, C4<0>; +L_0x197edf0 .delay 1 (20,20,20) L_0x197edf0/d; +v0x1901ef0_0 .net "a", 0 0, L_0x197ef90; 1 drivers +v0x19023d0_0 .net "b", 0 0, L_0x197dcd0; 1 drivers +v0x1902aa0_0 .net "b0", 0 0, L_0x197f0b0; 1 drivers +v0x1903ba0_0 .net "carryin", 0 0, v0x17b6f60_0; alias, 1 drivers +v0x1904740_0 .net "carryout", 0 0, L_0x197edf0; alias, 1 drivers +v0x19052e0_0 .net "cout1", 0 0, L_0x197eb30; 1 drivers +v0x1905e80_0 .net "cout2", 0 0, L_0x197ec90; 1 drivers +v0x1906a20_0 .net "subtract", 0 0, L_0x197e380; alias, 1 drivers +v0x19075c0_0 .net "sum", 0 0, L_0x197e9d0; 1 drivers +v0x18b7d30_0 .net "sumAB", 0 0, L_0x197e870; 1 drivers +S_0x1818430 .scope generate, "genblk1[21]" "genblk1[21]" 2 47, 2 47 0, S_0x180cd20; + .timescale 0 0; +P_0x18b7df0 .param/l "i" 0 2 47, +C4<010101>; +S_0x1816770 .scope module, "addermid" "FullAdder1bit" 2 48, 2 8 0, S_0x1818430; + .timescale 0 0; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b0" + .port_info 4 /INPUT 1 "carryin" + .port_info 5 /INPUT 1 "subtract" +L_0x197e730/d .functor XOR 1, L_0x197fb30, L_0x197edf0, C4<0>, C4<0>; +L_0x197e730 .delay 1 (20,20,20) L_0x197e730/d; +L_0x197f2f0/d .functor XOR 1, L_0x197f9d0, L_0x197e730, C4<0>, C4<0>; +L_0x197f2f0 .delay 1 (20,20,20) L_0x197f2f0/d; +L_0x197f450/d .functor XOR 1, L_0x197f2f0, v0x17b6f60_0, C4<0>, C4<0>; +L_0x197f450 .delay 1 (20,20,20) L_0x197f450/d; +L_0x197f5b0/d .functor AND 1, L_0x197f9d0, L_0x197e730, C4<1>, C4<1>; +L_0x197f5b0 .delay 1 (20,20,20) L_0x197f5b0/d; +L_0x197f710/d .functor AND 1, L_0x197f2f0, v0x17b6f60_0, C4<1>, C4<1>; +L_0x197f710 .delay 1 (20,20,20) L_0x197f710/d; +L_0x197f870/d .functor OR 1, L_0x197f5b0, L_0x197f710, C4<0>, C4<0>; +L_0x197f870 .delay 1 (20,20,20) L_0x197f870/d; +v0x1909c30_0 .net "a", 0 0, L_0x197f9d0; 1 drivers +v0x18bff70_0 .net "b", 0 0, L_0x197e730; 1 drivers +v0x190be50_0 .net "b0", 0 0, L_0x197fb30; 1 drivers +v0x18c1fb0_0 .net "carryin", 0 0, v0x17b6f60_0; alias, 1 drivers +v0x18d2140_0 .net "carryout", 0 0, L_0x197f870; alias, 1 drivers +v0x18d4190_0 .net "cout1", 0 0, L_0x197f5b0; 1 drivers +v0x18d61d0_0 .net "cout2", 0 0, L_0x197f710; 1 drivers +v0x18d8200_0 .net "subtract", 0 0, L_0x197edf0; alias, 1 drivers +v0x18da250_0 .net "sum", 0 0, L_0x197f450; 1 drivers +v0x18de2f0_0 .net "sumAB", 0 0, L_0x197f2f0; 1 drivers +S_0x18163f0 .scope generate, "genblk1[22]" "genblk1[22]" 2 47, 2 47 0, S_0x180cd20; + .timescale 0 0; +P_0x18de3b0 .param/l "i" 0 2 47, +C4<010110>; +S_0x1814730 .scope module, "addermid" "FullAdder1bit" 2 48, 2 8 0, S_0x18163f0; + .timescale 0 0; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b0" + .port_info 4 /INPUT 1 "carryin" + .port_info 5 /INPUT 1 "subtract" +L_0x197f1a0/d .functor XOR 1, L_0x1980520, L_0x197f870, C4<0>, C4<0>; +L_0x197f1a0 .delay 1 (20,20,20) L_0x197f1a0/d; +L_0x197fd30/d .functor XOR 1, L_0x1980400, L_0x197f1a0, C4<0>, C4<0>; +L_0x197fd30 .delay 1 (20,20,20) L_0x197fd30/d; +L_0x197fe40/d .functor XOR 1, L_0x197fd30, v0x17b6f60_0, C4<0>, C4<0>; +L_0x197fe40 .delay 1 (20,20,20) L_0x197fe40/d; +L_0x197ffa0/d .functor AND 1, L_0x1980400, L_0x197f1a0, C4<1>, C4<1>; +L_0x197ffa0 .delay 1 (20,20,20) L_0x197ffa0/d; +L_0x1980100/d .functor AND 1, L_0x197fd30, v0x17b6f60_0, C4<1>, C4<1>; +L_0x1980100 .delay 1 (20,20,20) L_0x1980100/d; +L_0x1980260/d .functor OR 1, L_0x197ffa0, L_0x1980100, C4<0>, C4<0>; +L_0x1980260 .delay 1 (20,20,20) L_0x1980260/d; +v0x18e0340_0 .net "a", 0 0, L_0x1980400; 1 drivers +v0x18e2390_0 .net "b", 0 0, L_0x197f1a0; 1 drivers +v0x1855000_0 .net "b0", 0 0, L_0x1980520; 1 drivers +v0x1907c90_0 .net "carryin", 0 0, v0x17b6f60_0; alias, 1 drivers +v0x1907d30_0 .net "carryout", 0 0, L_0x1980260; alias, 1 drivers +v0x19070f0_0 .net "cout1", 0 0, L_0x197ffa0; 1 drivers +v0x1906550_0 .net "cout2", 0 0, L_0x1980100; 1 drivers +v0x19059b0_0 .net "subtract", 0 0, L_0x197f870; alias, 1 drivers +v0x1905a50_0 .net "sum", 0 0, L_0x197fe40; 1 drivers +v0x1904270_0 .net "sumAB", 0 0, L_0x197fd30; 1 drivers +S_0x18143b0 .scope generate, "genblk1[23]" "genblk1[23]" 2 47, 2 47 0, S_0x180cd20; + .timescale 0 0; +P_0x1847f20 .param/l "i" 0 2 47, +C4<010111>; +S_0x17d7a30 .scope module, "addermid" "FullAdder1bit" 2 48, 2 8 0, S_0x18143b0; + .timescale 0 0; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b0" + .port_info 4 /INPUT 1 "carryin" + .port_info 5 /INPUT 1 "subtract" +L_0x197fbd0/d .functor XOR 1, L_0x1980f70, L_0x1980260, C4<0>, C4<0>; +L_0x197fbd0 .delay 1 (20,20,20) L_0x197fbd0/d; +L_0x1980780/d .functor XOR 1, L_0x1980e50, L_0x197fbd0, C4<0>, C4<0>; +L_0x1980780 .delay 1 (20,20,20) L_0x1980780/d; +L_0x1980890/d .functor XOR 1, L_0x1980780, v0x17b6f60_0, C4<0>, C4<0>; +L_0x1980890 .delay 1 (20,20,20) L_0x1980890/d; +L_0x19809f0/d .functor AND 1, L_0x1980e50, L_0x197fbd0, C4<1>, C4<1>; +L_0x19809f0 .delay 1 (20,20,20) L_0x19809f0/d; +L_0x1980b50/d .functor AND 1, L_0x1980780, v0x17b6f60_0, C4<1>, C4<1>; +L_0x1980b50 .delay 1 (20,20,20) L_0x1980b50/d; +L_0x1980cb0/d .functor OR 1, L_0x19809f0, L_0x1980b50, C4<0>, C4<0>; +L_0x1980cb0 .delay 1 (20,20,20) L_0x1980cb0/d; +v0x1903770_0 .net "a", 0 0, L_0x1980e50; 1 drivers +v0x18f7460_0 .net "b", 0 0, L_0x197fbd0; 1 drivers +v0x18f5d00_0 .net "b0", 0 0, L_0x1980f70; 1 drivers +v0x18f5da0_0 .net "carryin", 0 0, v0x17b6f60_0; alias, 1 drivers +v0x18f45a0_0 .net "carryout", 0 0, L_0x1980cb0; alias, 1 drivers +v0x18f39c0_0 .net "cout1", 0 0, L_0x19809f0; 1 drivers +v0x18f28c0_0 .net "cout2", 0 0, L_0x1980b50; 1 drivers +v0x18f0890_0 .net "subtract", 0 0, L_0x1980260; alias, 1 drivers +v0x18f0930_0 .net "sum", 0 0, L_0x1980890; 1 drivers +v0x18ee860_0 .net "sumAB", 0 0, L_0x1980780; 1 drivers +S_0x17d59e0 .scope generate, "genblk1[24]" "genblk1[24]" 2 47, 2 47 0, S_0x180cd20; + .timescale 0 0; +P_0x184be10 .param/l "i" 0 2 47, +C4<011000>; +S_0x17d3990 .scope module, "addermid" "FullAdder1bit" 2 48, 2 8 0, S_0x17d59e0; + .timescale 0 0; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b0" + .port_info 4 /INPUT 1 "carryin" + .port_info 5 /INPUT 1 "subtract" +L_0x1980610/d .functor XOR 1, L_0x19819d0, L_0x1980cb0, C4<0>, C4<0>; +L_0x1980610 .delay 1 (20,20,20) L_0x1980610/d; +L_0x19811e0/d .functor XOR 1, L_0x19818b0, L_0x1980610, C4<0>, C4<0>; +L_0x19811e0 .delay 1 (20,20,20) L_0x19811e0/d; +L_0x19812f0/d .functor XOR 1, L_0x19811e0, v0x17b6f60_0, C4<0>, C4<0>; +L_0x19812f0 .delay 1 (20,20,20) L_0x19812f0/d; +L_0x1981450/d .functor AND 1, L_0x19818b0, L_0x1980610, C4<1>, C4<1>; +L_0x1981450 .delay 1 (20,20,20) L_0x1981450/d; +L_0x19815b0/d .functor AND 1, L_0x19811e0, v0x17b6f60_0, C4<1>, C4<1>; +L_0x19815b0 .delay 1 (20,20,20) L_0x19815b0/d; +L_0x1981710/d .functor OR 1, L_0x1981450, L_0x19815b0, C4<0>, C4<0>; +L_0x1981710 .delay 1 (20,20,20) L_0x1981710/d; +v0x18ec8d0_0 .net "a", 0 0, L_0x19818b0; 1 drivers +v0x18ea800_0 .net "b", 0 0, L_0x1980610; 1 drivers +v0x18e87d0_0 .net "b0", 0 0, L_0x19819d0; 1 drivers +v0x18e8870_0 .net "carryin", 0 0, v0x17b6f60_0; alias, 1 drivers +v0x18e67a0_0 .net "carryout", 0 0, L_0x1981710; alias, 1 drivers +v0x18e4770_0 .net "cout1", 0 0, L_0x1981450; 1 drivers +v0x18d0440_0 .net "cout2", 0 0, L_0x19815b0; 1 drivers +v0x18ce410_0 .net "subtract", 0 0, L_0x1980cb0; alias, 1 drivers +v0x18ce4b0_0 .net "sum", 0 0, L_0x19812f0; 1 drivers +v0x18cc470_0 .net "sumAB", 0 0, L_0x19811e0; 1 drivers +S_0x17d1940 .scope generate, "genblk1[25]" "genblk1[25]" 2 47, 2 47 0, S_0x180cd20; + .timescale 0 0; +P_0x18503d0 .param/l "i" 0 2 47, +C4<011001>; +S_0x17bf760 .scope module, "addermid" "FullAdder1bit" 2 48, 2 8 0, S_0x17d1940; + .timescale 0 0; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b0" + .port_info 4 /INPUT 1 "carryin" + .port_info 5 /INPUT 1 "subtract" +L_0x1981060/d .functor XOR 1, L_0x1977920, L_0x1981710, C4<0>, C4<0>; +L_0x1981060 .delay 1 (20,20,20) L_0x1981060/d; +L_0x1981c50/d .functor XOR 1, L_0x1982320, L_0x1981060, C4<0>, C4<0>; +L_0x1981c50 .delay 1 (20,20,20) L_0x1981c50/d; +L_0x1981d60/d .functor XOR 1, L_0x1981c50, v0x17b6f60_0, C4<0>, C4<0>; +L_0x1981d60 .delay 1 (20,20,20) L_0x1981d60/d; +L_0x1981ec0/d .functor AND 1, L_0x1982320, L_0x1981060, C4<1>, C4<1>; +L_0x1981ec0 .delay 1 (20,20,20) L_0x1981ec0/d; +L_0x1982020/d .functor AND 1, L_0x1981c50, v0x17b6f60_0, C4<1>, C4<1>; +L_0x1982020 .delay 1 (20,20,20) L_0x1982020/d; +L_0x1982180/d .functor OR 1, L_0x1981ec0, L_0x1982020, C4<0>, C4<0>; +L_0x1982180 .delay 1 (20,20,20) L_0x1982180/d; +v0x18ca450_0 .net "a", 0 0, L_0x1982320; 1 drivers +v0x18c8380_0 .net "b", 0 0, L_0x1981060; 1 drivers +v0x18c6350_0 .net "b0", 0 0, L_0x1977920; 1 drivers +v0x18c63f0_0 .net "carryin", 0 0, v0x17b6f60_0; alias, 1 drivers +v0x18c4320_0 .net "carryout", 0 0, L_0x1982180; alias, 1 drivers +v0x18c22f0_0 .net "cout1", 0 0, L_0x1981ec0; 1 drivers +v0x18a3c70_0 .net "cout2", 0 0, L_0x1982020; 1 drivers +v0x18a2ff0_0 .net "subtract", 0 0, L_0x1981710; alias, 1 drivers +v0x18a3090_0 .net "sum", 0 0, L_0x1981d60; 1 drivers +v0x18a2400_0 .net "sumAB", 0 0, L_0x1981c50; 1 drivers +S_0x17bd710 .scope generate, "genblk1[26]" "genblk1[26]" 2 47, 2 47 0, S_0x180cd20; + .timescale 0 0; +P_0x1854510 .param/l "i" 0 2 47, +C4<011010>; +S_0x17bb6c0 .scope module, "addermid" "FullAdder1bit" 2 48, 2 8 0, S_0x17bd710; + .timescale 0 0; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b0" + .port_info 4 /INPUT 1 "carryin" + .port_info 5 /INPUT 1 "subtract" +L_0x1977bb0/d .functor XOR 1, L_0x19832f0, L_0x1982180, C4<0>, C4<0>; +L_0x1977bb0 .delay 1 (20,20,20) L_0x1977bb0/d; +L_0x1977cb0/d .functor XOR 1, L_0x19831d0, L_0x1977bb0, C4<0>, C4<0>; +L_0x1977cb0 .delay 1 (20,20,20) L_0x1977cb0/d; +L_0x1982c60/d .functor XOR 1, L_0x1977cb0, v0x17b6f60_0, C4<0>, C4<0>; +L_0x1982c60 .delay 1 (20,20,20) L_0x1982c60/d; +L_0x1982d70/d .functor AND 1, L_0x19831d0, L_0x1977bb0, C4<1>, C4<1>; +L_0x1982d70 .delay 1 (20,20,20) L_0x1982d70/d; +L_0x1982ed0/d .functor AND 1, L_0x1977cb0, v0x17b6f60_0, C4<1>, C4<1>; +L_0x1982ed0 .delay 1 (20,20,20) L_0x1982ed0/d; +L_0x1983030/d .functor OR 1, L_0x1982d70, L_0x1982ed0, C4<0>, C4<0>; +L_0x1983030 .delay 1 (20,20,20) L_0x1983030/d; +v0x1891c50_0 .net "a", 0 0, L_0x19831d0; 1 drivers +v0x1890f30_0 .net "b", 0 0, L_0x1977bb0; 1 drivers +v0x18902b0_0 .net "b0", 0 0, L_0x19832f0; 1 drivers +v0x188f770_0 .net "carryin", 0 0, v0x17b6f60_0; alias, 1 drivers +v0x188f810_0 .net "carryout", 0 0, L_0x1983030; alias, 1 drivers +v0x188ec80_0 .net "cout1", 0 0, L_0x1982d70; 1 drivers +v0x188e190_0 .net "cout2", 0 0, L_0x1982ed0; 1 drivers +v0x188d6a0_0 .net "subtract", 0 0, L_0x1982180; alias, 1 drivers +v0x188d740_0 .net "sum", 0 0, L_0x1982c60; 1 drivers +v0x1871c80_0 .net "sumAB", 0 0, L_0x1977cb0; 1 drivers +S_0x17b9a00 .scope generate, "genblk1[27]" "genblk1[27]" 2 47, 2 47 0, S_0x180cd20; + .timescale 0 0; +P_0x1858ff0 .param/l "i" 0 2 47, +C4<011011>; +S_0x17b9680 .scope module, "addermid" "FullAdder1bit" 2 48, 2 8 0, S_0x17b9a00; + .timescale 0 0; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b0" + .port_info 4 /INPUT 1 "carryin" + .port_info 5 /INPUT 1 "subtract" +L_0x1977a10/d .functor XOR 1, L_0x1983d30, L_0x1983030, C4<0>, C4<0>; +L_0x1977a10 .delay 1 (20,20,20) L_0x1977a10/d; +L_0x1983590/d .functor XOR 1, L_0x1983c10, L_0x1977a10, C4<0>, C4<0>; +L_0x1983590 .delay 1 (20,20,20) L_0x1983590/d; +L_0x1983650/d .functor XOR 1, L_0x1983590, v0x17b6f60_0, C4<0>, C4<0>; +L_0x1983650 .delay 1 (20,20,20) L_0x1983650/d; +L_0x19837b0/d .functor AND 1, L_0x1983c10, L_0x1977a10, C4<1>, C4<1>; +L_0x19837b0 .delay 1 (20,20,20) L_0x19837b0/d; +L_0x1983910/d .functor AND 1, L_0x1983590, v0x17b6f60_0, C4<1>, C4<1>; +L_0x1983910 .delay 1 (20,20,20) L_0x1983910/d; +L_0x1983a70/d .functor OR 1, L_0x19837b0, L_0x1983910, C4<0>, C4<0>; +L_0x1983a70 .delay 1 (20,20,20) L_0x1983a70/d; +v0x1871010_0 .net "a", 0 0, L_0x1983c10; 1 drivers +v0x18702f0_0 .net "b", 0 0, L_0x1977a10; 1 drivers +v0x186f670_0 .net "b0", 0 0, L_0x1983d30; 1 drivers +v0x186f710_0 .net "carryin", 0 0, v0x17b6f60_0; alias, 1 drivers +v0x186e9f0_0 .net "carryout", 0 0, L_0x1983a70; alias, 1 drivers +v0x186dd70_0 .net "cout1", 0 0, L_0x19837b0; 1 drivers +v0x186d0f0_0 .net "cout2", 0 0, L_0x1983910; 1 drivers +v0x186c470_0 .net "subtract", 0 0, L_0x1983030; alias, 1 drivers +v0x186c510_0 .net "sum", 0 0, L_0x1983650; 1 drivers +v0x186b880_0 .net "sumAB", 0 0, L_0x1983590; 1 drivers +S_0x17b79c0 .scope generate, "genblk1[28]" "genblk1[28]" 2 47, 2 47 0, S_0x180cd20; + .timescale 0 0; +P_0x185f420 .param/l "i" 0 2 47, +C4<011100>; +S_0x17b7640 .scope module, "addermid" "FullAdder1bit" 2 48, 2 8 0, S_0x17b79c0; + .timescale 0 0; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b0" + .port_info 4 /INPUT 1 "carryin" + .port_info 5 /INPUT 1 "subtract" +L_0x19833e0/d .functor XOR 1, L_0x1984780, L_0x1983a70, C4<0>, C4<0>; +L_0x19833e0 .delay 1 (20,20,20) L_0x19833e0/d; +L_0x1983fe0/d .functor XOR 1, L_0x1984660, L_0x19833e0, C4<0>, C4<0>; +L_0x1983fe0 .delay 1 (20,20,20) L_0x1983fe0/d; +L_0x19840a0/d .functor XOR 1, L_0x1983fe0, v0x17b6f60_0, C4<0>, C4<0>; +L_0x19840a0 .delay 1 (20,20,20) L_0x19840a0/d; +L_0x1984200/d .functor AND 1, L_0x1984660, L_0x19833e0, C4<1>, C4<1>; +L_0x1984200 .delay 1 (20,20,20) L_0x1984200/d; +L_0x1984360/d .functor AND 1, L_0x1983fe0, v0x17b6f60_0, C4<1>, C4<1>; +L_0x1984360 .delay 1 (20,20,20) L_0x1984360/d; +L_0x19844c0/d .functor OR 1, L_0x1984200, L_0x1984360, C4<0>, C4<0>; +L_0x19844c0 .delay 1 (20,20,20) L_0x19844c0/d; +v0x186ac10_0 .net "a", 0 0, L_0x1984660; 1 drivers +v0x1869ef0_0 .net "b", 0 0, L_0x19833e0; 1 drivers +v0x1869270_0 .net "b0", 0 0, L_0x1984780; 1 drivers +v0x1869310_0 .net "carryin", 0 0, v0x17b6f60_0; alias, 1 drivers +v0x18685f0_0 .net "carryout", 0 0, L_0x19844c0; alias, 1 drivers +v0x1867970_0 .net "cout1", 0 0, L_0x1984200; 1 drivers +v0x1866cf0_0 .net "cout2", 0 0, L_0x1984360; 1 drivers +v0x1866070_0 .net "subtract", 0 0, L_0x1983a70; alias, 1 drivers +v0x1866110_0 .net "sum", 0 0, L_0x19840a0; 1 drivers +v0x1865480_0 .net "sumAB", 0 0, L_0x1983fe0; 1 drivers +S_0x17b5980 .scope generate, "genblk1[29]" "genblk1[29]" 2 47, 2 47 0, S_0x180cd20; + .timescale 0 0; +P_0x18340e0 .param/l "i" 0 2 47, +C4<011101>; +S_0x17b5600 .scope module, "addermid" "FullAdder1bit" 2 48, 2 8 0, S_0x17b5980; + .timescale 0 0; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b0" + .port_info 4 /INPUT 1 "carryin" + .port_info 5 /INPUT 1 "subtract" +L_0x1983e20/d .functor XOR 1, L_0x19851c0, L_0x19844c0, C4<0>, C4<0>; +L_0x1983e20 .delay 1 (20,20,20) L_0x1983e20/d; +L_0x1983f70/d .functor XOR 1, L_0x19850a0, L_0x1983e20, C4<0>, C4<0>; +L_0x1983f70 .delay 1 (20,20,20) L_0x1983f70/d; +L_0x1984ae0/d .functor XOR 1, L_0x1983f70, v0x17b6f60_0, C4<0>, C4<0>; +L_0x1984ae0 .delay 1 (20,20,20) L_0x1984ae0/d; +L_0x1984c40/d .functor AND 1, L_0x19850a0, L_0x1983e20, C4<1>, C4<1>; +L_0x1984c40 .delay 1 (20,20,20) L_0x1984c40/d; +L_0x1984da0/d .functor AND 1, L_0x1983f70, v0x17b6f60_0, C4<1>, C4<1>; +L_0x1984da0 .delay 1 (20,20,20) L_0x1984da0/d; +L_0x1984f00/d .functor OR 1, L_0x1984c40, L_0x1984da0, C4<0>, C4<0>; +L_0x1984f00 .delay 1 (20,20,20) L_0x1984f00/d; +v0x1864810_0 .net "a", 0 0, L_0x19850a0; 1 drivers +v0x1863af0_0 .net "b", 0 0, L_0x1983e20; 1 drivers +v0x1862e70_0 .net "b0", 0 0, L_0x19851c0; 1 drivers +v0x1862f10_0 .net "carryin", 0 0, v0x17b6f60_0; alias, 1 drivers +v0x1862140_0 .net "carryout", 0 0, L_0x1984f00; alias, 1 drivers +v0x185bdf0_0 .net "cout1", 0 0, L_0x1984c40; 1 drivers +v0x180c3f0_0 .net "cout2", 0 0, L_0x1984da0; 1 drivers +v0x1846670_0 .net "subtract", 0 0, L_0x19844c0; alias, 1 drivers +v0x1846710_0 .net "sum", 0 0, L_0x1984ae0; 1 drivers +v0x18446d0_0 .net "sumAB", 0 0, L_0x1983f70; 1 drivers +S_0x17b3940 .scope generate, "genblk1[30]" "genblk1[30]" 2 47, 2 47 0, S_0x180cd20; + .timescale 0 0; +P_0x187d340 .param/l "i" 0 2 47, +C4<011110>; +S_0x17b35c0 .scope module, "addermid" "FullAdder1bit" 2 48, 2 8 0, S_0x17b3940; + .timescale 0 0; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b0" + .port_info 4 /INPUT 1 "carryin" + .port_info 5 /INPUT 1 "subtract" +L_0x1984870/d .functor XOR 1, L_0x1985c60, L_0x1984f00, C4<0>, C4<0>; +L_0x1984870 .delay 1 (20,20,20) L_0x1984870/d; +L_0x19849c0/d .functor XOR 1, L_0x1985b40, L_0x1984870, C4<0>, C4<0>; +L_0x19849c0 .delay 1 (20,20,20) L_0x19849c0/d; +L_0x1985530/d .functor XOR 1, L_0x19849c0, v0x17b6f60_0, C4<0>, C4<0>; +L_0x1985530 .delay 1 (20,20,20) L_0x1985530/d; +L_0x1985690/d .functor AND 1, L_0x1985b40, L_0x1984870, C4<1>, C4<1>; +L_0x1985690 .delay 1 (20,20,20) L_0x1985690/d; +L_0x19857f0/d .functor AND 1, L_0x19849c0, v0x17b6f60_0, C4<1>, C4<1>; +L_0x19857f0 .delay 1 (20,20,20) L_0x19857f0/d; +L_0x1985950/d .functor OR 1, L_0x1985690, L_0x19857f0, C4<0>, C4<0>; +L_0x1985950 .delay 1 (20,20,20) L_0x1985950/d; +v0x1842660_0 .net "a", 0 0, L_0x1985b40; 1 drivers +v0x1830360_0 .net "b", 0 0, L_0x1984870; 1 drivers +v0x182e330_0 .net "b0", 0 0, L_0x1985c60; 1 drivers +v0x182e3d0_0 .net "carryin", 0 0, v0x17b6f60_0; alias, 1 drivers +v0x182c300_0 .net "carryout", 0 0, L_0x1985950; alias, 1 drivers +v0x182a280_0 .net "cout1", 0 0, L_0x1985690; 1 drivers +v0x1828250_0 .net "cout2", 0 0, L_0x19857f0; 1 drivers +v0x1826220_0 .net "subtract", 0 0, L_0x1984f00; alias, 1 drivers +v0x18262c0_0 .net "sum", 0 0, L_0x1985530; 1 drivers +v0x1824280_0 .net "sumAB", 0 0, L_0x19849c0; 1 drivers +S_0x17b1900 .scope generate, "genblk2[0]" "genblk2[0]" 2 57, 2 57 0, S_0x180cd20; + .timescale 0 0; +P_0x1882050 .param/l "j" 0 2 57, +C4<00>; +L_0x19852b0/d .functor NOR 1, L_0x198c890, L_0x1985370, C4<0>, C4<0>; +L_0x19852b0 .delay 1 (10,10,10) L_0x19852b0/d; +v0x18cee20_0 .net *"_s3", 0 0, L_0x1985370; 1 drivers +S_0x17b1580 .scope generate, "genblk2[1]" "genblk2[1]" 2 57, 2 57 0, S_0x180cd20; + .timescale 0 0; +P_0x1885c40 .param/l "j" 0 2 57, +C4<01>; +L_0x1985fe0/d .functor NOR 1, L_0x19852b0, L_0x19860f0, C4<0>, C4<0>; +L_0x1985fe0 .delay 1 (10,10,10) L_0x1985fe0/d; +v0x18221c0_0 .net *"_s3", 0 0, L_0x19860f0; 1 drivers +S_0x179f720 .scope generate, "genblk2[2]" "genblk2[2]" 2 57, 2 57 0, S_0x180cd20; + .timescale 0 0; +P_0x1888710 .param/l "j" 0 2 57, +C4<010>; +L_0x1985d50/d .functor NOR 1, L_0x1985fe0, L_0x1986450, C4<0>, C4<0>; +L_0x1985d50 .delay 1 (10,10,10) L_0x1985d50/d; +v0x1810400_0 .net *"_s3", 0 0, L_0x1986450; 1 drivers +S_0x179f3a0 .scope generate, "genblk2[3]" "genblk2[3]" 2 57, 2 57 0, S_0x180cd20; + .timescale 0 0; +P_0x188a950 .param/l "j" 0 2 57, +C4<011>; +L_0x1986580/d .functor NOR 1, L_0x1985d50, L_0x1986640, C4<0>, C4<0>; +L_0x1986580 .delay 1 (10,10,10) L_0x1986580/d; +v0x180e600_0 .net *"_s3", 0 0, L_0x1986640; 1 drivers +S_0x18f2f90 .scope generate, "genblk2[4]" "genblk2[4]" 2 57, 2 57 0, S_0x180cd20; + .timescale 0 0; +P_0x188bdb0 .param/l "j" 0 2 57, +C4<0100>; +L_0x1986250/d .functor NOR 1, L_0x1986580, L_0x19863b0, C4<0>, C4<0>; +L_0x1986250 .delay 1 (10,10,10) L_0x1986250/d; +v0x180c740_0 .net *"_s3", 0 0, L_0x19863b0; 1 drivers +S_0x18e2e10 .scope generate, "genblk2[5]" "genblk2[5]" 2 57, 2 57 0, S_0x180cd20; + .timescale 0 0; +P_0x18a6980 .param/l "j" 0 2 57, +C4<0101>; +L_0x1986a00/d .functor NOR 1, L_0x1986250, L_0x1986b10, C4<0>, C4<0>; +L_0x1986a00 .delay 1 (10,10,10) L_0x1986a00/d; +v0x17eca50_0 .net *"_s3", 0 0, L_0x1986b10; 1 drivers +S_0x18e0dc0 .scope generate, "genblk2[6]" "genblk2[6]" 2 57, 2 57 0, S_0x180cd20; + .timescale 0 0; +P_0x18a9ce0 .param/l "j" 0 2 57, +C4<0110>; +L_0x19867a0/d .functor NOR 1, L_0x1986a00, L_0x1986900, C4<0>, C4<0>; +L_0x19867a0 .delay 1 (10,10,10) L_0x19867a0/d; +v0x17ebeb0_0 .net *"_s3", 0 0, L_0x1986900; 1 drivers +S_0x18ded70 .scope generate, "genblk2[7]" "genblk2[7]" 2 57, 2 57 0, S_0x180cd20; + .timescale 0 0; +P_0x18ad040 .param/l "j" 0 2 57, +C4<0111>; +L_0x19864f0/d .functor NOR 1, L_0x19867a0, L_0x1987090, C4<0>, C4<0>; +L_0x19864f0 .delay 1 (10,10,10) L_0x19864f0/d; +v0x17eb310_0 .net *"_s3", 0 0, L_0x1987090; 1 drivers +S_0x18dcd20 .scope generate, "genblk2[8]" "genblk2[8]" 2 57, 2 57 0, S_0x180cd20; + .timescale 0 0; +P_0x18af280 .param/l "j" 0 2 57, +C4<01000>; +L_0x1986c70/d .functor NOR 1, L_0x19864f0, L_0x1986d80, C4<0>, C4<0>; +L_0x1986c70 .delay 1 (10,10,10) L_0x1986c70/d; +v0x17ea770_0 .net *"_s3", 0 0, L_0x1986d80; 1 drivers +S_0x18dacd0 .scope generate, "genblk2[9]" "genblk2[9]" 2 57, 2 57 0, S_0x180cd20; + .timescale 0 0; +P_0x18b0c30 .param/l "j" 0 2 57, +C4<01001>; +L_0x1987470/d .functor NOR 1, L_0x1986c70, L_0x1987580, C4<0>, C4<0>; +L_0x1987470 .delay 1 (10,10,10) L_0x1987470/d; +v0x17e9bd0_0 .net *"_s3", 0 0, L_0x1987580; 1 drivers +S_0x18d8c80 .scope generate, "genblk2[10]" "genblk2[10]" 2 57, 2 57 0, S_0x180cd20; + .timescale 0 0; +P_0x18b3700 .param/l "j" 0 2 57, +C4<01010>; +L_0x19871f0/d .functor NOR 1, L_0x1987470, L_0x1987300, C4<0>, C4<0>; +L_0x19871f0 .delay 1 (10,10,10) L_0x19871f0/d; +v0x17e9030_0 .net *"_s3", 0 0, L_0x1987300; 1 drivers +S_0x18d6c30 .scope generate, "genblk2[11]" "genblk2[11]" 2 57, 2 57 0, S_0x180cd20; + .timescale 0 0; +P_0x18b5b30 .param/l "j" 0 2 57, +C4<01011>; +L_0x1987970/d .functor NOR 1, L_0x19871f0, L_0x1987a80, C4<0>, C4<0>; +L_0x1987970 .delay 1 (10,10,10) L_0x1987970/d; +v0x17e8490_0 .net *"_s3", 0 0, L_0x1987a80; 1 drivers +S_0x18d0850 .scope generate, "genblk2[12]" "genblk2[12]" 2 57, 2 57 0, S_0x180cd20; + .timescale 0 0; +P_0x18bed20 .param/l "j" 0 2 57, +C4<01100>; +L_0x19876e0/d .functor NOR 1, L_0x1987970, L_0x19877f0, C4<0>, C4<0>; +L_0x19876e0 .delay 1 (10,10,10) L_0x19876e0/d; +v0x17e78f0_0 .net *"_s3", 0 0, L_0x19877f0; 1 drivers +S_0x18ce820 .scope generate, "genblk2[13]" "genblk2[13]" 2 57, 2 57 0, S_0x180cd20; + .timescale 0 0; +P_0x18c8e30 .param/l "j" 0 2 57, +C4<01101>; +L_0x1987e80/d .functor NOR 1, L_0x19876e0, L_0x1987f90, C4<0>, C4<0>; +L_0x1987e80 .delay 1 (10,10,10) L_0x1987e80/d; +v0x17e6d50_0 .net *"_s3", 0 0, L_0x1987f90; 1 drivers +S_0x18cc7f0 .scope generate, "genblk2[14]" "genblk2[14]" 2 57, 2 57 0, S_0x180cd20; + .timescale 0 0; +P_0x18d2f40 .param/l "j" 0 2 57, +C4<01110>; +L_0x1987be0/d .functor NOR 1, L_0x1987e80, L_0x1987cf0, C4<0>, C4<0>; +L_0x1987be0 .delay 1 (10,10,10) L_0x1987be0/d; +v0x17e61b0_0 .net *"_s3", 0 0, L_0x1987cf0; 1 drivers +S_0x18ca7c0 .scope generate, "genblk2[15]" "genblk2[15]" 2 57, 2 57 0, S_0x180cd20; + .timescale 0 0; +P_0x18d7060 .param/l "j" 0 2 57, +C4<01111>; +L_0x1986ee0/d .functor NOR 1, L_0x1987be0, L_0x19885b0, C4<0>, C4<0>; +L_0x1986ee0 .delay 1 (10,10,10) L_0x1986ee0/d; +v0x17e5610_0 .net *"_s3", 0 0, L_0x19885b0; 1 drivers +S_0x18c8790 .scope generate, "genblk2[16]" "genblk2[16]" 2 57, 2 57 0, S_0x180cd20; + .timescale 0 0; +P_0x18de6b0 .param/l "j" 0 2 57, +C4<010000>; +L_0x19880f0/d .functor NOR 1, L_0x1986ee0, L_0x1988200, C4<0>, C4<0>; +L_0x19880f0 .delay 1 (10,10,10) L_0x19880f0/d; +v0x17e4a70_0 .net *"_s3", 0 0, L_0x1988200; 1 drivers +S_0x18c6760 .scope generate, "genblk2[17]" "genblk2[17]" 2 57, 2 57 0, S_0x180cd20; + .timescale 0 0; +P_0x18e11f0 .param/l "j" 0 2 57, +C4<010001>; +L_0x1988960/d .functor NOR 1, L_0x19880f0, L_0x1988a20, C4<0>, C4<0>; +L_0x1988960 .delay 1 (10,10,10) L_0x1988960/d; +v0x17e3ed0_0 .net *"_s3", 0 0, L_0x1988a20; 1 drivers +S_0x18c4730 .scope generate, "genblk2[18]" "genblk2[18]" 2 57, 2 57 0, S_0x180cd20; + .timescale 0 0; +P_0x18eb300 .param/l "j" 0 2 57, +C4<010010>; +L_0x19886a0/d .functor NOR 1, L_0x1988960, L_0x19887b0, C4<0>, C4<0>; +L_0x19886a0 .delay 1 (10,10,10) L_0x19886a0/d; +v0x17dce40_0 .net *"_s3", 0 0, L_0x19887b0; 1 drivers +S_0x18c2700 .scope generate, "genblk2[19]" "genblk2[19]" 2 57, 2 57 0, S_0x180cd20; + .timescale 0 0; +P_0x18f33c0 .param/l "j" 0 2 57, +C4<010011>; +L_0x1988e00/d .functor NOR 1, L_0x19886a0, L_0x1988f10, C4<0>, C4<0>; +L_0x1988e00 .delay 1 (10,10,10) L_0x1988e00/d; +v0x17db6e0_0 .net *"_s3", 0 0, L_0x1988f10; 1 drivers +S_0x18b8480 .scope generate, "genblk2[20]" "genblk2[20]" 2 57, 2 57 0, S_0x180cd20; + .timescale 0 0; +P_0x18f4ce0 .param/l "j" 0 2 57, +C4<010100>; +L_0x1988b80/d .functor NOR 1, L_0x1988e00, L_0x1988c90, C4<0>, C4<0>; +L_0x1988b80 .delay 1 (10,10,10) L_0x1988b80/d; +v0x17d9f80_0 .net *"_s3", 0 0, L_0x1988c90; 1 drivers +S_0x185e090 .scope generate, "genblk2[21]" "genblk2[21]" 2 57, 2 57 0, S_0x180cd20; + .timescale 0 0; +P_0x18f6fd0 .param/l "j" 0 2 57, +C4<010101>; +L_0x1989300/d .functor NOR 1, L_0x1988b80, L_0x1989410, C4<0>, C4<0>; +L_0x1989300 .delay 1 (10,10,10) L_0x1989300/d; +v0x17d8810_0 .net *"_s3", 0 0, L_0x1989410; 1 drivers +S_0x185dca0 .scope generate, "genblk2[22]" "genblk2[22]" 2 57, 2 57 0, S_0x180cd20; + .timescale 0 0; +P_0x18f8c80 .param/l "j" 0 2 57, +C4<010110>; +L_0x1989070/d .functor NOR 1, L_0x1989300, L_0x1989180, C4<0>, C4<0>; +L_0x1989070 .delay 1 (10,10,10) L_0x1989070/d; +v0x17d8140_0 .net *"_s3", 0 0, L_0x1989180; 1 drivers +S_0x1840ca0 .scope generate, "genblk2[23]" "genblk2[23]" 2 57, 2 57 0, S_0x180cd20; + .timescale 0 0; +P_0x18f9eb0 .param/l "j" 0 2 57, +C4<010111>; +L_0x1989810/d .functor NOR 1, L_0x1989070, L_0x1989920, C4<0>, C4<0>; +L_0x1989810 .delay 1 (10,10,10) L_0x1989810/d; +v0x17cf5a0_0 .net *"_s3", 0 0, L_0x1989920; 1 drivers +S_0x183ec50 .scope generate, "genblk2[24]" "genblk2[24]" 2 57, 2 57 0, S_0x180cd20; + .timescale 0 0; +P_0x18fbb40 .param/l "j" 0 2 57, +C4<011000>; +L_0x1989570/d .functor NOR 1, L_0x1989810, L_0x1989680, C4<0>, C4<0>; +L_0x1989570 .delay 1 (10,10,10) L_0x1989570/d; +v0x17cd570_0 .net *"_s3", 0 0, L_0x1989680; 1 drivers +S_0x183cc00 .scope generate, "genblk2[25]" "genblk2[25]" 2 57, 2 57 0, S_0x180cd20; + .timescale 0 0; +P_0x18fd2a0 .param/l "j" 0 2 57, +C4<011001>; +L_0x1989d30/d .functor NOR 1, L_0x1989570, L_0x1989e40, C4<0>, C4<0>; +L_0x1989d30 .delay 1 (10,10,10) L_0x1989d30/d; +v0x17cb540_0 .net *"_s3", 0 0, L_0x1989e40; 1 drivers +S_0x183abb0 .scope generate, "genblk2[26]" "genblk2[26]" 2 57, 2 57 0, S_0x180cd20; + .timescale 0 0; +P_0x18fe4d0 .param/l "j" 0 2 57, +C4<011010>; +L_0x1989a80/d .functor NOR 1, L_0x1989d30, L_0x1989b90, C4<0>, C4<0>; +L_0x1989a80 .delay 1 (10,10,10) L_0x1989a80/d; +v0x17c9510_0 .net *"_s3", 0 0, L_0x1989b90; 1 drivers +S_0x1838b60 .scope generate, "genblk2[27]" "genblk2[27]" 2 57, 2 57 0, S_0x180cd20; + .timescale 0 0; +P_0x1900160 .param/l "j" 0 2 57, +C4<011011>; +L_0x198a260/d .functor NOR 1, L_0x1989a80, L_0x198a370, C4<0>, C4<0>; +L_0x198a260 .delay 1 (10,10,10) L_0x198a260/d; +v0x17c74e0_0 .net *"_s3", 0 0, L_0x198a370; 1 drivers +S_0x1836b10 .scope generate, "genblk2[28]" "genblk2[28]" 2 57, 2 57 0, S_0x180cd20; + .timescale 0 0; +P_0x19018c0 .param/l "j" 0 2 57, +C4<011100>; +L_0x1989fa0/d .functor NOR 1, L_0x198a260, L_0x198a0b0, C4<0>, C4<0>; +L_0x1989fa0 .delay 1 (10,10,10) L_0x1989fa0/d; +v0x17c54b0_0 .net *"_s3", 0 0, L_0x198a0b0; 1 drivers +S_0x1834ac0 .scope module, "dut1" "alu32bitxor" 2 258, 2 64 0, S_0x17ef170; + .timescale 0 0; + .port_info 0 /OUTPUT 32 "result" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /OUTPUT 1 "zero" + .port_info 3 /OUTPUT 1 "overflow" + .port_info 4 /INPUT 32 "operandA" + .port_info 5 /INPUT 32 "operandB" +v0x190cdf0_0 .net *"_s0", 0 0, L_0x198c630; 1 drivers +v0x18b9e90_0 .net *"_s100", 0 0, L_0x198e690; 1 drivers +v0x18f2c80_0 .net *"_s104", 0 0, L_0x1982530; 1 drivers +v0x18f2d40_0 .net *"_s108", 0 0, L_0x1982b20; 1 drivers +v0x18f0fd0_0 .net *"_s112", 0 0, L_0x1982be0; 1 drivers +v0x18eefa0_0 .net *"_s116", 0 0, L_0x19931e0; 1 drivers +v0x18ecf70_0 .net *"_s12", 0 0, L_0x198d980; 1 drivers +v0x18eaf40_0 .net *"_s120", 0 0, L_0x19934a0; 1 drivers +v0x18e8f10_0 .net *"_s124", 0 0, L_0x19946f0; 1 drivers +v0x18e6ee0_0 .net *"_s16", 0 0, L_0x198dce0; 1 drivers +v0x18e4eb0_0 .net *"_s20", 0 0, L_0x198e050; 1 drivers +v0x18d0bd0_0 .net *"_s24", 0 0, L_0x198e380; 1 drivers +v0x18ceba0_0 .net *"_s28", 0 0, L_0x198e310; 1 drivers +v0x18ccb70_0 .net *"_s32", 0 0, L_0x198ea40; 1 drivers +v0x18cab40_0 .net *"_s36", 0 0, L_0x198e9b0; 1 drivers +v0x18c8b10_0 .net *"_s4", 0 0, L_0x198d360; 1 drivers +v0x18c6ae0_0 .net *"_s40", 0 0, L_0x198ed50; 1 drivers +v0x18c6b80_0 .net *"_s44", 0 0, L_0x198f090; 1 drivers +v0x18c2a80_0 .net *"_s48", 0 0, L_0x198f3e0; 1 drivers +v0x1846db0_0 .net *"_s52", 0 0, L_0x198f740; 1 drivers +v0x1844d80_0 .net *"_s56", 0 0, L_0x198fa60; 1 drivers +v0x1842d50_0 .net *"_s60", 0 0, L_0x198fd90; 1 drivers +v0x1830aa0_0 .net *"_s64", 0 0, L_0x19900d0; 1 drivers +v0x182ea70_0 .net *"_s68", 0 0, L_0x1990420; 1 drivers +v0x182ca40_0 .net *"_s72", 0 0, L_0x1990780; 1 drivers +v0x182aa10_0 .net *"_s76", 0 0, L_0x1990a80; 1 drivers +v0x18289e0_0 .net *"_s8", 0 0, L_0x198d670; 1 drivers +v0x18269b0_0 .net *"_s80", 0 0, L_0x1990d90; 1 drivers +v0x1824980_0 .net *"_s84", 0 0, L_0x19910b0; 1 drivers +v0x1822950_0 .net *"_s88", 0 0, L_0x19913e0; 1 drivers +v0x18109b0_0 .net *"_s92", 0 0, L_0x1991720; 1 drivers +v0x180ebb0_0 .net *"_s96", 0 0, L_0x1991a20; 1 drivers +v0x180ca10_0 .net "carryout", 0 0, L_0x7f93f4ea0018; alias, 1 drivers +v0x180cab0_0 .net "operandA", 31 0, o0x7f93f4eeeb98; alias, 0 drivers +v0x17cfce0_0 .net "operandB", 31 0, o0x7f93f4eeebc8; alias, 0 drivers +v0x17cfda0_0 .net "overflow", 0 0, L_0x7f93f4ea00a8; alias, 1 drivers +v0x17cdcb0_0 .net "result", 31 0, L_0x19937c0; alias, 1 drivers +v0x17cbc80_0 .net "zero", 0 0, L_0x7f93f4ea0060; alias, 1 drivers +L_0x198c740 .part o0x7f93f4eeeb98, 0, 1; +L_0x198d2c0 .part o0x7f93f4eeebc8, 0, 1; +L_0x198d420 .part o0x7f93f4eeeb98, 1, 1; +L_0x198d580 .part o0x7f93f4eeebc8, 1, 1; +L_0x198d730 .part o0x7f93f4eeeb98, 2, 1; +L_0x198d890 .part o0x7f93f4eeebc8, 2, 1; +L_0x198da40 .part o0x7f93f4eeeb98, 3, 1; +L_0x198dba0 .part o0x7f93f4eeebc8, 3, 1; +L_0x198dda0 .part o0x7f93f4eeeb98, 4, 1; +L_0x198df00 .part o0x7f93f4eeebc8, 4, 1; +L_0x198e0c0 .part o0x7f93f4eeeb98, 5, 1; +L_0x198e220 .part o0x7f93f4eeebc8, 5, 1; +L_0x198e440 .part o0x7f93f4eeeb98, 6, 1; +L_0x198e5a0 .part o0x7f93f4eeebc8, 6, 1; +L_0x198e760 .part o0x7f93f4eeeb98, 7, 1; +L_0x198e8c0 .part o0x7f93f4eeebc8, 7, 1; +L_0x198eb00 .part o0x7f93f4eeeb98, 8, 1; +L_0x198ec60 .part o0x7f93f4eeebc8, 8, 1; +L_0x198ee40 .part o0x7f93f4eeeb98, 9, 1; +L_0x198efa0 .part o0x7f93f4eeebc8, 9, 1; +L_0x198f190 .part o0x7f93f4eeeb98, 10, 1; +L_0x198f2f0 .part o0x7f93f4eeebc8, 10, 1; +L_0x198f4f0 .part o0x7f93f4eeeb98, 11, 1; +L_0x198f650 .part o0x7f93f4eeebc8, 11, 1; +L_0x198f810 .part o0x7f93f4eeeb98, 12, 1; +L_0x198f970 .part o0x7f93f4eeebc8, 12, 1; +L_0x198fb40 .part o0x7f93f4eeeb98, 13, 1; +L_0x198fca0 .part o0x7f93f4eeebc8, 13, 1; +L_0x198fe80 .part o0x7f93f4eeeb98, 14, 1; +L_0x198ffe0 .part o0x7f93f4eeebc8, 14, 1; +L_0x19901d0 .part o0x7f93f4eeeb98, 15, 1; +L_0x1990330 .part o0x7f93f4eeebc8, 15, 1; +L_0x1990530 .part o0x7f93f4eeeb98, 16, 1; +L_0x1990690 .part o0x7f93f4eeebc8, 16, 1; +L_0x19908a0 .part o0x7f93f4eeeb98, 17, 1; +L_0x1990990 .part o0x7f93f4eeebc8, 17, 1; +L_0x1990bb0 .part o0x7f93f4eeeb98, 18, 1; +L_0x1990ca0 .part o0x7f93f4eeebc8, 18, 1; +L_0x1990ed0 .part o0x7f93f4eeeb98, 19, 1; +L_0x1990fc0 .part o0x7f93f4eeebc8, 19, 1; +L_0x1991200 .part o0x7f93f4eeeb98, 20, 1; +L_0x19912f0 .part o0x7f93f4eeebc8, 20, 1; +L_0x1991540 .part o0x7f93f4eeeb98, 21, 1; +L_0x1991630 .part o0x7f93f4eeebc8, 21, 1; +L_0x1991890 .part o0x7f93f4eeeb98, 22, 1; +L_0x1991930 .part o0x7f93f4eeebc8, 22, 1; +L_0x1991ba0 .part o0x7f93f4eeeb98, 23, 1; +L_0x1991c40 .part o0x7f93f4eeebc8, 23, 1; +L_0x1991ec0 .part o0x7f93f4eeeb98, 24, 1; +L_0x1982440 .part o0x7f93f4eeebc8, 24, 1; +L_0x1991d30 .part o0x7f93f4eeeb98, 25, 1; +L_0x19826d0 .part o0x7f93f4eeebc8, 25, 1; +L_0x19825f0 .part o0x7f93f4eeeb98, 26, 1; +L_0x19829c0 .part o0x7f93f4eeebc8, 26, 1; +L_0x19827c0 .part o0x7f93f4eeeb98, 27, 1; +L_0x1993140 .part o0x7f93f4eeebc8, 27, 1; +L_0x1992fd0 .part o0x7f93f4eeeb98, 28, 1; +L_0x19933b0 .part o0x7f93f4eeebc8, 28, 1; +L_0x19932a0 .part o0x7f93f4eeeb98, 29, 1; +L_0x19936d0 .part o0x7f93f4eeebc8, 29, 1; +L_0x1993560 .part o0x7f93f4eeeb98, 30, 1; +L_0x1993a00 .part o0x7f93f4eeebc8, 30, 1; +LS_0x19937c0_0_0 .concat8 [ 1 1 1 1], L_0x198c630, L_0x198d360, L_0x198d670, L_0x198d980; +LS_0x19937c0_0_4 .concat8 [ 1 1 1 1], L_0x198dce0, L_0x198e050, L_0x198e380, L_0x198e310; +LS_0x19937c0_0_8 .concat8 [ 1 1 1 1], L_0x198ea40, L_0x198e9b0, L_0x198ed50, L_0x198f090; +LS_0x19937c0_0_12 .concat8 [ 1 1 1 1], L_0x198f3e0, L_0x198f740, L_0x198fa60, L_0x198fd90; +LS_0x19937c0_0_16 .concat8 [ 1 1 1 1], L_0x19900d0, L_0x1990420, L_0x1990780, L_0x1990a80; +LS_0x19937c0_0_20 .concat8 [ 1 1 1 1], L_0x1990d90, L_0x19910b0, L_0x19913e0, L_0x1991720; +LS_0x19937c0_0_24 .concat8 [ 1 1 1 1], L_0x1991a20, L_0x198e690, L_0x1982530, L_0x1982b20; +LS_0x19937c0_0_28 .concat8 [ 1 1 1 1], L_0x1982be0, L_0x19931e0, L_0x19934a0, L_0x19946f0; +LS_0x19937c0_1_0 .concat8 [ 4 4 4 4], LS_0x19937c0_0_0, LS_0x19937c0_0_4, LS_0x19937c0_0_8, LS_0x19937c0_0_12; +LS_0x19937c0_1_4 .concat8 [ 4 4 4 4], LS_0x19937c0_0_16, LS_0x19937c0_0_20, LS_0x19937c0_0_24, LS_0x19937c0_0_28; +L_0x19937c0 .concat8 [ 16 16 0 0], LS_0x19937c0_1_0, LS_0x19937c0_1_4; +L_0x1994800 .part o0x7f93f4eeeb98, 31, 1; +L_0x1993af0 .part o0x7f93f4eeebc8, 31, 1; +S_0x1832a70 .scope generate, "ripple[0]" "ripple[0]" 2 76, 2 76 0, S_0x1834ac0; + .timescale 0 0; +P_0x17a71b0 .param/l "i" 0 2 76, +C4<00>; +L_0x198c630/d .functor XOR 1, L_0x198c740, L_0x198d2c0, C4<0>, C4<0>; +L_0x198c630 .delay 1 (20,20,20) L_0x198c630/d; +v0x18e4460_0 .net *"_s0", 0 0, L_0x198c740; 1 drivers +v0x18ce110_0 .net *"_s1", 0 0, L_0x198d2c0; 1 drivers +S_0x1828660 .scope generate, "ripple[1]" "ripple[1]" 2 76, 2 76 0, S_0x1834ac0; + .timescale 0 0; +P_0x18ce1f0 .param/l "i" 0 2 76, +C4<01>; +L_0x198d360/d .functor XOR 1, L_0x198d420, L_0x198d580, C4<0>, C4<0>; +L_0x198d360 .delay 1 (20,20,20) L_0x198d360/d; +v0x18cc0e0_0 .net *"_s0", 0 0, L_0x198d420; 1 drivers +v0x18ca0b0_0 .net *"_s1", 0 0, L_0x198d580; 1 drivers +S_0x1826630 .scope generate, "ripple[2]" "ripple[2]" 2 76, 2 76 0, S_0x1834ac0; + .timescale 0 0; +P_0x18ca190 .param/l "i" 0 2 76, +C4<010>; +L_0x198d670/d .functor XOR 1, L_0x198d730, L_0x198d890, C4<0>, C4<0>; +L_0x198d670 .delay 1 (20,20,20) L_0x198d670/d; +v0x18c8080_0 .net *"_s0", 0 0, L_0x198d730; 1 drivers +v0x18c6050_0 .net *"_s1", 0 0, L_0x198d890; 1 drivers +S_0x1824600 .scope generate, "ripple[3]" "ripple[3]" 2 76, 2 76 0, S_0x1834ac0; + .timescale 0 0; +P_0x1867a30 .param/l "i" 0 2 76, +C4<011>; +L_0x198d980/d .functor XOR 1, L_0x198da40, L_0x198dba0, C4<0>, C4<0>; +L_0x198d980 .delay 1 (20,20,20) L_0x198d980/d; +v0x1909880_0 .net *"_s0", 0 0, L_0x198da40; 1 drivers +v0x18f25b0_0 .net *"_s1", 0 0, L_0x198dba0; 1 drivers +S_0x18225d0 .scope generate, "ripple[4]" "ripple[4]" 2 76, 2 76 0, S_0x1834ac0; + .timescale 0 0; +P_0x1863bb0 .param/l "i" 0 2 76, +C4<0100>; +L_0x198dce0/d .functor XOR 1, L_0x198dda0, L_0x198df00, C4<0>, C4<0>; +L_0x198dce0 .delay 1 (20,20,20) L_0x198dce0/d; +v0x18f0580_0 .net *"_s0", 0 0, L_0x198dda0; 1 drivers +v0x18ee550_0 .net *"_s1", 0 0, L_0x198df00; 1 drivers +S_0x18126f0 .scope generate, "ripple[5]" "ripple[5]" 2 76, 2 76 0, S_0x1834ac0; + .timescale 0 0; +P_0x18ee630 .param/l "i" 0 2 76, +C4<0101>; +L_0x198e050/d .functor XOR 1, L_0x198e0c0, L_0x198e220, C4<0>, C4<0>; +L_0x198e050 .delay 1 (20,20,20) L_0x198e050/d; +v0x18ec520_0 .net *"_s0", 0 0, L_0x198e0c0; 1 drivers +v0x18a1600_0 .net *"_s1", 0 0, L_0x198e220; 1 drivers +S_0x18106d0 .scope generate, "ripple[6]" "ripple[6]" 2 76, 2 76 0, S_0x1834ac0; + .timescale 0 0; +P_0x18a16e0 .param/l "i" 0 2 76, +C4<0110>; +L_0x198e380/d .functor XOR 1, L_0x198e440, L_0x198e5a0, C4<0>, C4<0>; +L_0x198e380 .delay 1 (20,20,20) L_0x198e380/d; +v0x18a0970_0 .net *"_s0", 0 0, L_0x198e440; 1 drivers +v0x189fce0_0 .net *"_s1", 0 0, L_0x198e5a0; 1 drivers +S_0x180e8d0 .scope generate, "ripple[7]" "ripple[7]" 2 76, 2 76 0, S_0x1834ac0; + .timescale 0 0; +P_0x189fdc0 .param/l "i" 0 2 76, +C4<0111>; +L_0x198e310/d .functor XOR 1, L_0x198e760, L_0x198e8c0, C4<0>, C4<0>; +L_0x198e310 .delay 1 (20,20,20) L_0x198e310/d; +v0x189f050_0 .net *"_s0", 0 0, L_0x198e760; 1 drivers +v0x189e3c0_0 .net *"_s1", 0 0, L_0x198e8c0; 1 drivers +S_0x17d7db0 .scope generate, "ripple[8]" "ripple[8]" 2 76, 2 76 0, S_0x1834ac0; + .timescale 0 0; +P_0x18f2690 .param/l "i" 0 2 76, +C4<01000>; +L_0x198ea40/d .functor XOR 1, L_0x198eb00, L_0x198ec60, C4<0>, C4<0>; +L_0x198ea40 .delay 1 (20,20,20) L_0x198ea40/d; +v0x189d730_0 .net *"_s0", 0 0, L_0x198eb00; 1 drivers +v0x189caa0_0 .net *"_s1", 0 0, L_0x198ec60; 1 drivers +S_0x17d5d60 .scope generate, "ripple[9]" "ripple[9]" 2 76, 2 76 0, S_0x1834ac0; + .timescale 0 0; +P_0x189cb80 .param/l "i" 0 2 76, +C4<01001>; +L_0x198e9b0/d .functor XOR 1, L_0x198ee40, L_0x198efa0, C4<0>, C4<0>; +L_0x198e9b0 .delay 1 (20,20,20) L_0x198e9b0/d; +v0x189be10_0 .net *"_s0", 0 0, L_0x198ee40; 1 drivers +v0x189b180_0 .net *"_s1", 0 0, L_0x198efa0; 1 drivers +S_0x17d3d10 .scope generate, "ripple[10]" "ripple[10]" 2 76, 2 76 0, S_0x1834ac0; + .timescale 0 0; +P_0x189b260 .param/l "i" 0 2 76, +C4<01010>; +L_0x198ed50/d .functor XOR 1, L_0x198f190, L_0x198f2f0, C4<0>, C4<0>; +L_0x198ed50 .delay 1 (20,20,20) L_0x198ed50/d; +v0x189a4f0_0 .net *"_s0", 0 0, L_0x198f190; 1 drivers +v0x1899860_0 .net *"_s1", 0 0, L_0x198f2f0; 1 drivers +S_0x17d1cc0 .scope generate, "ripple[11]" "ripple[11]" 2 76, 2 76 0, S_0x1834ac0; + .timescale 0 0; +P_0x1899940 .param/l "i" 0 2 76, +C4<01011>; +L_0x198f090/d .functor XOR 1, L_0x198f4f0, L_0x198f650, C4<0>, C4<0>; +L_0x198f090 .delay 1 (20,20,20) L_0x198f090/d; +v0x1898bd0_0 .net *"_s0", 0 0, L_0x198f4f0; 1 drivers +v0x1897f40_0 .net *"_s1", 0 0, L_0x198f650; 1 drivers +S_0x17bfae0 .scope generate, "ripple[12]" "ripple[12]" 2 76, 2 76 0, S_0x1834ac0; + .timescale 0 0; +P_0x1898020 .param/l "i" 0 2 76, +C4<01100>; +L_0x198f3e0/d .functor XOR 1, L_0x198f810, L_0x198f970, C4<0>, C4<0>; +L_0x198f3e0 .delay 1 (20,20,20) L_0x198f3e0/d; +v0x1897300_0 .net *"_s0", 0 0, L_0x198f810; 1 drivers +v0x1896620_0 .net *"_s1", 0 0, L_0x198f970; 1 drivers +S_0x17bda90 .scope generate, "ripple[13]" "ripple[13]" 2 76, 2 76 0, S_0x1834ac0; + .timescale 0 0; +P_0x1895990 .param/l "i" 0 2 76, +C4<01101>; +L_0x198f740/d .functor XOR 1, L_0x198fb40, L_0x198fca0, C4<0>, C4<0>; +L_0x198f740 .delay 1 (20,20,20) L_0x198f740/d; +v0x1894d00_0 .net *"_s0", 0 0, L_0x198fb40; 1 drivers +v0x1894070_0 .net *"_s1", 0 0, L_0x198fca0; 1 drivers +S_0x17bba40 .scope generate, "ripple[14]" "ripple[14]" 2 76, 2 76 0, S_0x1834ac0; + .timescale 0 0; +P_0x1894150 .param/l "i" 0 2 76, +C4<01110>; +L_0x198fa60/d .functor XOR 1, L_0x198fe80, L_0x198ffe0, C4<0>, C4<0>; +L_0x198fa60 .delay 1 (20,20,20) L_0x198fa60/d; +v0x18933e0_0 .net *"_s0", 0 0, L_0x198fe80; 1 drivers +v0x1892750_0 .net *"_s1", 0 0, L_0x198ffe0; 1 drivers +S_0x17af5a0 .scope generate, "ripple[15]" "ripple[15]" 2 76, 2 76 0, S_0x1834ac0; + .timescale 0 0; +P_0x1892830 .param/l "i" 0 2 76, +C4<01111>; +L_0x198fd90/d .functor XOR 1, L_0x19901d0, L_0x1990330, C4<0>, C4<0>; +L_0x198fd90 .delay 1 (20,20,20) L_0x198fd90/d; +v0x187a580_0 .net *"_s0", 0 0, L_0x19901d0; 1 drivers +v0x18798a0_0 .net *"_s1", 0 0, L_0x1990330; 1 drivers +S_0x17ad570 .scope generate, "ripple[16]" "ripple[16]" 2 76, 2 76 0, S_0x1834ac0; + .timescale 0 0; +P_0x18c8140 .param/l "i" 0 2 76, +C4<010000>; +L_0x19900d0/d .functor XOR 1, L_0x1990530, L_0x1990690, C4<0>, C4<0>; +L_0x19900d0 .delay 1 (20,20,20) L_0x19900d0/d; +v0x1877ff0_0 .net *"_s0", 0 0, L_0x1990530; 1 drivers +v0x18772f0_0 .net *"_s1", 0 0, L_0x1990690; 1 drivers +S_0x17ab540 .scope generate, "ripple[17]" "ripple[17]" 2 76, 2 76 0, S_0x1834ac0; + .timescale 0 0; +P_0x1876660 .param/l "i" 0 2 76, +C4<010001>; +L_0x1990420/d .functor XOR 1, L_0x19908a0, L_0x1990990, C4<0>, C4<0>; +L_0x1990420 .delay 1 (20,20,20) L_0x1990420/d; +v0x18759d0_0 .net *"_s0", 0 0, L_0x19908a0; 1 drivers +v0x1874d40_0 .net *"_s1", 0 0, L_0x1990990; 1 drivers +S_0x17a9510 .scope generate, "ripple[18]" "ripple[18]" 2 76, 2 76 0, S_0x1834ac0; + .timescale 0 0; +P_0x1874e20 .param/l "i" 0 2 76, +C4<010010>; +L_0x1990780/d .functor XOR 1, L_0x1990bb0, L_0x1990ca0, C4<0>, C4<0>; +L_0x1990780 .delay 1 (20,20,20) L_0x1990780/d; +v0x18740b0_0 .net *"_s0", 0 0, L_0x1990bb0; 1 drivers +v0x1873420_0 .net *"_s1", 0 0, L_0x1990ca0; 1 drivers +S_0x17a74e0 .scope generate, "ripple[19]" "ripple[19]" 2 76, 2 76 0, S_0x1834ac0; + .timescale 0 0; +P_0x1873500 .param/l "i" 0 2 76, +C4<010011>; +L_0x1990a80/d .functor XOR 1, L_0x1990ed0, L_0x1990fc0, C4<0>, C4<0>; +L_0x1990a80 .delay 1 (20,20,20) L_0x1990a80/d; +v0x18727e0_0 .net *"_s0", 0 0, L_0x1990ed0; 1 drivers +v0x1830050_0 .net *"_s1", 0 0, L_0x1990fc0; 1 drivers +S_0x17a54b0 .scope generate, "ripple[20]" "ripple[20]" 2 76, 2 76 0, S_0x1834ac0; + .timescale 0 0; +P_0x182e020 .param/l "i" 0 2 76, +C4<010100>; +L_0x1990d90/d .functor XOR 1, L_0x1991200, L_0x19912f0, C4<0>, C4<0>; +L_0x1990d90 .delay 1 (20,20,20) L_0x1990d90/d; +v0x182bff0_0 .net *"_s0", 0 0, L_0x1991200; 1 drivers +v0x1829f80_0 .net *"_s1", 0 0, L_0x19912f0; 1 drivers +S_0x17a3480 .scope generate, "ripple[21]" "ripple[21]" 2 76, 2 76 0, S_0x1834ac0; + .timescale 0 0; +P_0x182a060 .param/l "i" 0 2 76, +C4<010101>; +L_0x19910b0/d .functor XOR 1, L_0x1991540, L_0x1991630, C4<0>, C4<0>; +L_0x19910b0 .delay 1 (20,20,20) L_0x19910b0/d; +v0x1827f50_0 .net *"_s0", 0 0, L_0x1991540; 1 drivers +v0x1825f20_0 .net *"_s1", 0 0, L_0x1991630; 1 drivers +S_0x17a1450 .scope generate, "ripple[22]" "ripple[22]" 2 76, 2 76 0, S_0x1834ac0; + .timescale 0 0; +P_0x1826000 .param/l "i" 0 2 76, +C4<010110>; +L_0x19913e0/d .functor XOR 1, L_0x1991890, L_0x1991930, C4<0>, C4<0>; +L_0x19913e0 .delay 1 (20,20,20) L_0x19913e0/d; +v0x1823f40_0 .net *"_s0", 0 0, L_0x1991890; 1 drivers +v0x180e350_0 .net *"_s1", 0 0, L_0x1991930; 1 drivers +S_0x179d290 .scope generate, "ripple[23]" "ripple[23]" 2 76, 2 76 0, S_0x1834ac0; + .timescale 0 0; +P_0x185d880 .param/l "i" 0 2 76, +C4<010111>; +L_0x1991720/d .functor XOR 1, L_0x1991ba0, L_0x1991c40, C4<0>, C4<0>; +L_0x1991720 .delay 1 (20,20,20) L_0x1991720/d; +v0x1846360_0 .net *"_s0", 0 0, L_0x1991ba0; 1 drivers +v0x1844330_0 .net *"_s1", 0 0, L_0x1991c40; 1 drivers +S_0x18b8830 .scope generate, "ripple[24]" "ripple[24]" 2 76, 2 76 0, S_0x1834ac0; + .timescale 0 0; +P_0x1846440 .param/l "i" 0 2 76, +C4<011000>; +L_0x1991a20/d .functor XOR 1, L_0x1991ec0, L_0x1982440, C4<0>, C4<0>; +L_0x1991a20 .delay 1 (20,20,20) L_0x1991a20/d; +v0x18422a0_0 .net *"_s0", 0 0, L_0x1991ec0; 1 drivers +v0x17cd260_0 .net *"_s1", 0 0, L_0x1982440; 1 drivers +S_0x179d640 .scope generate, "ripple[25]" "ripple[25]" 2 76, 2 76 0, S_0x1834ac0; + .timescale 0 0; +P_0x17cd340 .param/l "i" 0 2 76, +C4<011001>; +L_0x198e690/d .functor XOR 1, L_0x1991d30, L_0x19826d0, C4<0>, C4<0>; +L_0x198e690 .delay 1 (20,20,20) L_0x198e690/d; +v0x17cb230_0 .net *"_s0", 0 0, L_0x1991d30; 1 drivers +v0x17c9200_0 .net *"_s1", 0 0, L_0x19826d0; 1 drivers +S_0x18ecbf0 .scope generate, "ripple[26]" "ripple[26]" 2 76, 2 76 0, S_0x1834ac0; + .timescale 0 0; +P_0x17cb310 .param/l "i" 0 2 76, +C4<011010>; +L_0x1982530/d .functor XOR 1, L_0x19825f0, L_0x19829c0, C4<0>, C4<0>; +L_0x1982530 .delay 1 (20,20,20) L_0x1982530/d; +v0x17c71d0_0 .net *"_s0", 0 0, L_0x19825f0; 1 drivers +v0x17c51a0_0 .net *"_s1", 0 0, L_0x19829c0; 1 drivers +S_0x18eabc0 .scope generate, "ripple[27]" "ripple[27]" 2 76, 2 76 0, S_0x1834ac0; + .timescale 0 0; +P_0x17c5280 .param/l "i" 0 2 76, +C4<011011>; +L_0x1982b20/d .functor XOR 1, L_0x19827c0, L_0x1993140, C4<0>, C4<0>; +L_0x1982b20 .delay 1 (20,20,20) L_0x1982b20/d; +v0x17c3170_0 .net *"_s0", 0 0, L_0x19827c0; 1 drivers +v0x17c10e0_0 .net *"_s1", 0 0, L_0x1993140; 1 drivers +S_0x18e8b90 .scope generate, "ripple[28]" "ripple[28]" 2 76, 2 76 0, S_0x1834ac0; + .timescale 0 0; +P_0x17c3250 .param/l "i" 0 2 76, +C4<011100>; +L_0x1982be0/d .functor XOR 1, L_0x1992fd0, L_0x19933b0, C4<0>, C4<0>; +L_0x1982be0 .delay 1 (20,20,20) L_0x1982be0/d; +v0x17aee90_0 .net *"_s0", 0 0, L_0x1992fd0; 1 drivers +v0x17ace60_0 .net *"_s1", 0 0, L_0x19933b0; 1 drivers +S_0x18e6b60 .scope generate, "ripple[29]" "ripple[29]" 2 76, 2 76 0, S_0x1834ac0; + .timescale 0 0; +P_0x17acf40 .param/l "i" 0 2 76, +C4<011101>; +L_0x19931e0/d .functor XOR 1, L_0x19932a0, L_0x19936d0, C4<0>, C4<0>; +L_0x19931e0 .delay 1 (20,20,20) L_0x19931e0/d; +v0x17aae30_0 .net *"_s0", 0 0, L_0x19932a0; 1 drivers +v0x17a6dd0_0 .net *"_s1", 0 0, L_0x19936d0; 1 drivers +S_0x18e4b30 .scope generate, "ripple[30]" "ripple[30]" 2 76, 2 76 0, S_0x1834ac0; + .timescale 0 0; +P_0x17aaf10 .param/l "i" 0 2 76, +C4<011110>; +L_0x19934a0/d .functor XOR 1, L_0x1993560, L_0x1993a00, C4<0>, C4<0>; +L_0x19934a0 .delay 1 (20,20,20) L_0x19934a0/d; +v0x17a4da0_0 .net *"_s0", 0 0, L_0x1993560; 1 drivers +v0x17ee640_0 .net *"_s1", 0 0, L_0x1993a00; 1 drivers +S_0x1846a30 .scope generate, "ripple[31]" "ripple[31]" 2 76, 2 76 0, S_0x1834ac0; + .timescale 0 0; +P_0x17ee720 .param/l "i" 0 2 76, +C4<011111>; +L_0x19946f0/d .functor XOR 1, L_0x1994800, L_0x1993af0, C4<0>, C4<0>; +L_0x19946f0 .delay 1 (20,20,20) L_0x19946f0/d; +v0x17a2d70_0 .net *"_s0", 0 0, L_0x1994800; 1 drivers +v0x17cf290_0 .net *"_s1", 0 0, L_0x1993af0; 1 drivers +S_0x18429d0 .scope module, "dut2" "alu32bitslt" 2 259, 2 90 0, S_0x17ef170; + .timescale 0 0; + .port_info 0 /OUTPUT 32 "result" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /OUTPUT 1 "zero" + .port_info 3 /OUTPUT 1 "overflow" + .port_info 4 /INPUT 32 "operandA" + .port_info 5 /INPUT 32 "operandB" +L_0x19bf4f0/d .functor XOR 1, L_0x19bf5b0, L_0x19ad4c0, C4<0>, C4<0>; +L_0x19bf4f0 .delay 1 (20,20,20) L_0x19bf4f0/d; +v0x1927560_0 .net *"_s4", 0 0, L_0x19bf4f0; 1 drivers +v0x1927660_0 .net *"_s7", 0 0, L_0x19bf5b0; 1 drivers +v0x1927740_0 .net "carryout", 0 0, L_0x7f93f4ea0180; alias, 1 drivers +v0x19277e0_0 .net "operandA", 31 0, o0x7f93f4eeeb98; alias, 0 drivers +v0x19278a0_0 .net "operandB", 31 0, o0x7f93f4eeebc8; alias, 0 drivers +v0x1927960_0 .net "overflow", 0 0, L_0x7f93f4ea0210; alias, 1 drivers +v0x1927a20_0 .net8 "result", 31 0, RS_0x7f93f4ef6a28; alias, 2 drivers +v0x1927b00_0 .net "subcarryout", 0 0, L_0x19ada80; 1 drivers +v0x1927ba0_0 .net "suboverflow", 0 0, L_0x19ad4c0; 1 drivers +v0x1927cd0_0 .net "subresult", 31 0, L_0x19adbe0; 1 drivers +v0x1927d70_0 .net "subzero", 0 0, L_0x19aa750; 1 drivers +v0x1927e10_0 .net "zero", 0 0, L_0x7f93f4ea01c8; alias, 1 drivers +L_0x19aea00 .part/pv L_0x19bf4f0, 0, 1, 32; +L_0x19bf5b0 .part L_0x19adbe0, 0, 1; +S_0x1830720 .scope module, "subtractor" "AddSub" 2 105, 2 32 0, S_0x18429d0; + .timescale 0 0; + .port_info 0 /OUTPUT 32 "result" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /OUTPUT 1 "zero" + .port_info 3 /OUTPUT 1 "overflow" + .port_info 4 /INPUT 32 "operandA" + .port_info 5 /INPUT 32 "operandB" + .port_info 6 /INPUT 1 "subtract" +L_0x19ad4c0/d .functor XOR 1, L_0x19a7c10, L_0x19ada80, C4<0>, C4<0>; +L_0x19ad4c0 .delay 1 (20,20,20) L_0x19ad4c0/d; +L_0x19aeb00/d .functor NOR 1, L_0x19aec60, L_0x19aa660, C4<0>, C4<0>; +L_0x19aeb00 .delay 1 (10,10,10) L_0x19aeb00/d; +o0x7f93f4ef67e8 .functor BUFZ 1, C4; HiZ drive +L_0x19aa750/d .functor NOR 1, o0x7f93f4ef67e8, L_0x19ae800, C4<0>, C4<0>; +L_0x19aa750 .delay 1 (10,10,10) L_0x19aa750/d; +v0x1925a60_0 .net *"_s166", 0 0, L_0x19aec60; 1 drivers +v0x1925b60_0 .net *"_s168", 0 0, L_0x19aa660; 1 drivers +v0x1925c40_0 .net *"_s172", 0 0, L_0x19ae800; 1 drivers +v0x1925d30_0 .net "carryout", 0 0, L_0x19ada80; alias, 1 drivers +v0x1925e20 .array "carryoutmid", 0 30; +v0x1925e20_0 .net v0x1925e20 0, 0 0, L_0x19ad030; 1 drivers +v0x1925e20_1 .net v0x1925e20 1, 0 0, L_0x19951b0; 1 drivers +v0x1925e20_2 .net v0x1925e20 2, 0 0, L_0x1995b90; 1 drivers +v0x1925e20_3 .net v0x1925e20 3, 0 0, L_0x1996570; 1 drivers +v0x1925e20_4 .net v0x1925e20 4, 0 0, L_0x1996f50; 1 drivers +v0x1925e20_5 .net v0x1925e20 5, 0 0, L_0x1997980; 1 drivers +v0x1925e20_6 .net v0x1925e20 6, 0 0, L_0x1998370; 1 drivers +v0x1925e20_7 .net v0x1925e20 7, 0 0, L_0x1998dc0; 1 drivers +v0x1925e20_8 .net v0x1925e20 8, 0 0, L_0x1999760; 1 drivers +v0x1925e20_9 .net v0x1925e20 9, 0 0, L_0x19990d0; 1 drivers +v0x1925e20_10 .net v0x1925e20 10, 0 0, L_0x199abc0; 1 drivers +v0x1925e20_11 .net v0x1925e20 11, 0 0, L_0x199b5e0; 1 drivers +v0x1925e20_12 .net v0x1925e20 12, 0 0, L_0x199c010; 1 drivers +v0x1925e20_13 .net v0x1925e20 13, 0 0, L_0x199c9b0; 1 drivers +v0x1925e20_14 .net v0x1925e20 14, 0 0, L_0x199d3b0; 1 drivers +v0x1925e20_15 .net v0x1925e20 15, 0 0, L_0x199ddc0; 1 drivers +v0x1925e20_16 .net v0x1925e20 16, 0 0, L_0x191e9b0; 1 drivers +v0x1925e20_17 .net v0x1925e20 17, 0 0, L_0x199f610; 1 drivers +v0x1925e20_18 .net v0x1925e20 18, 0 0, L_0x19a0060; 1 drivers +v0x1925e20_19 .net v0x1925e20 19, 0 0, L_0x19a0ac0; 1 drivers +v0x1925e20_20 .net v0x1925e20 20, 0 0, L_0x19a1530; 1 drivers +v0x1925e20_21 .net v0x1925e20 21, 0 0, L_0x19a1fb0; 1 drivers +v0x1925e20_22 .net v0x1925e20 22, 0 0, L_0x19a29a0; 1 drivers +v0x1925e20_23 .net v0x1925e20 23, 0 0, L_0x19a33f0; 1 drivers +v0x1925e20_24 .net v0x1925e20 24, 0 0, L_0x19a3e50; 1 drivers +v0x1925e20_25 .net v0x1925e20 25, 0 0, L_0x19a48c0; 1 drivers +v0x1925e20_26 .net v0x1925e20 26, 0 0, L_0x19a5340; 1 drivers +v0x1925e20_27 .net v0x1925e20 27, 0 0, L_0x19a5d30; 1 drivers +v0x1925e20_28 .net v0x1925e20 28, 0 0, L_0x19a6780; 1 drivers +v0x1925e20_29 .net v0x1925e20 29, 0 0, L_0x19a71c0; 1 drivers +v0x1925e20_30 .net v0x1925e20 30, 0 0, L_0x19a7c10; 1 drivers +v0x1926970_0 .net "operandA", 31 0, o0x7f93f4eeeb98; alias, 0 drivers +v0x1926a60_0 .net "operandB", 31 0, o0x7f93f4eeebc8; alias, 0 drivers +v0x1926b70_0 .net "overflow", 0 0, L_0x19ad4c0; alias, 1 drivers +v0x1926c30_0 .net "result", 31 0, L_0x19adbe0; alias, 1 drivers +L_0x7f93f4ea00f0 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>; +v0x1926da0_0 .net "subtract", 0 0, L_0x7f93f4ea00f0; 1 drivers +v0x1926e40_0 .net "zero", 0 0, L_0x19aa750; alias, 1 drivers +v0x1926f00 .array "zeromid", 0 30; +v0x1926f00_0 .net v0x1926f00 0, 0 0, L_0x19aeb00; 1 drivers +v0x1926f00_1 .net v0x1926f00 1, 0 0, L_0x19a7570; 1 drivers +v0x1926f00_2 .net v0x1926f00 2, 0 0, L_0x19a82a0; 1 drivers +v0x1926f00_3 .net v0x1926f00 3, 0 0, L_0x19a8010; 1 drivers +v0x1926f00_4 .net v0x1926f00 4, 0 0, L_0x19a8840; 1 drivers +v0x1926f00_5 .net v0x1926f00 5, 0 0, L_0x19a8510; 1 drivers +v0x1926f00_6 .net v0x1926f00 6, 0 0, L_0x19a8cc0; 1 drivers +v0x1926f00_7 .net v0x1926f00 7, 0 0, L_0x19a8a60; 1 drivers +v0x1926f00_8 .net v0x1926f00 8, 0 0, L_0x19a87b0; 1 drivers +v0x1926f00_9 .net v0x1926f00 9, 0 0, L_0x19a8f30; 1 drivers +v0x1926f00_10 .net v0x1926f00 10, 0 0, L_0x19a9730; 1 drivers +v0x1926f00_11 .net v0x1926f00 11, 0 0, L_0x19a94b0; 1 drivers +v0x1926f00_12 .net v0x1926f00 12, 0 0, L_0x19a9c30; 1 drivers +v0x1926f00_13 .net v0x1926f00 13, 0 0, L_0x19a99a0; 1 drivers +v0x1926f00_14 .net v0x1926f00 14, 0 0, L_0x19aa140; 1 drivers +v0x1926f00_15 .net v0x1926f00 15, 0 0, L_0x19a9ea0; 1 drivers +v0x1926f00_16 .net v0x1926f00 16, 0 0, L_0x19a91a0; 1 drivers +v0x1926f00_17 .net v0x1926f00 17, 0 0, L_0x19aa3b0; 1 drivers +v0x1926f00_18 .net v0x1926f00 18, 0 0, L_0x19aac20; 1 drivers +v0x1926f00_19 .net v0x1926f00 19, 0 0, L_0x19aa960; 1 drivers +v0x1926f00_20 .net v0x1926f00 20, 0 0, L_0x19ab0c0; 1 drivers +v0x1926f00_21 .net v0x1926f00 21, 0 0, L_0x19aae40; 1 drivers +v0x1926f00_22 .net v0x1926f00 22, 0 0, L_0x19ab5c0; 1 drivers +v0x1926f00_23 .net v0x1926f00 23, 0 0, L_0x19ab330; 1 drivers +v0x1926f00_24 .net v0x1926f00 24, 0 0, L_0x19abad0; 1 drivers +v0x1926f00_25 .net v0x1926f00 25, 0 0, L_0x19ab830; 1 drivers +v0x1926f00_26 .net v0x1926f00 26, 0 0, L_0x19abff0; 1 drivers +v0x1926f00_27 .net v0x1926f00 27, 0 0, L_0x19abd40; 1 drivers +v0x1926f00_28 .net v0x1926f00 28, 0 0, L_0x19ac520; 1 drivers +v0x1926f00_29 .net v0x1926f00 29, 0 0, L_0x19ac260; 1 drivers +v0x1926f00_30 .net v0x1926f00 30, 0 0, o0x7f93f4ef67e8; 0 drivers +L_0x1995310 .part o0x7f93f4eeeb98, 1, 1; +L_0x1995470 .part o0x7f93f4eeebc8, 1, 1; +L_0x1995cf0 .part o0x7f93f4eeeb98, 2, 1; +L_0x1995e50 .part o0x7f93f4eeebc8, 2, 1; +L_0x19966d0 .part o0x7f93f4eeeb98, 3, 1; +L_0x1996830 .part o0x7f93f4eeebc8, 3, 1; +L_0x19970b0 .part o0x7f93f4eeeb98, 4, 1; +L_0x1997210 .part o0x7f93f4eeebc8, 4, 1; +L_0x1997ae0 .part o0x7f93f4eeeb98, 5, 1; +L_0x1997c40 .part o0x7f93f4eeebc8, 5, 1; +L_0x19984d0 .part o0x7f93f4eeeb98, 6, 1; +L_0x1998630 .part o0x7f93f4eeebc8, 6, 1; +L_0x1998ed0 .part o0x7f93f4eeeb98, 7, 1; +L_0x1999030 .part o0x7f93f4eeebc8, 7, 1; +L_0x19998c0 .part o0x7f93f4eeeb98, 8, 1; +L_0x1999a20 .part o0x7f93f4eeebc8, 8, 1; +L_0x199a300 .part o0x7f93f4eeeb98, 9, 1; +L_0x199a420 .part o0x7f93f4eeebc8, 9, 1; +L_0x199ad20 .part o0x7f93f4eeeb98, 10, 1; +L_0x199ae80 .part o0x7f93f4eeebc8, 10, 1; +L_0x199b740 .part o0x7f93f4eeeb98, 11, 1; +L_0x199b8a0 .part o0x7f93f4eeebc8, 11, 1; +L_0x199c170 .part o0x7f93f4eeeb98, 12, 1; +L_0x199c2d0 .part o0x7f93f4eeebc8, 12, 1; +L_0x199cb10 .part o0x7f93f4eeeb98, 13, 1; +L_0x199cc70 .part o0x7f93f4eeebc8, 13, 1; +L_0x199d510 .part o0x7f93f4eeeb98, 14, 1; +L_0x199d670 .part o0x7f93f4eeebc8, 14, 1; +L_0x199df20 .part o0x7f93f4eeeb98, 15, 1; +L_0x199e080 .part o0x7f93f4eeebc8, 15, 1; +L_0x199ed80 .part o0x7f93f4eeeb98, 16, 1; +L_0x199eee0 .part o0x7f93f4eeebc8, 16, 1; +L_0x199f7b0 .part o0x7f93f4eeeb98, 17, 1; +L_0x199f8d0 .part o0x7f93f4eeebc8, 17, 1; +L_0x19a0200 .part o0x7f93f4eeeb98, 18, 1; +L_0x19a0320 .part o0x7f93f4eeebc8, 18, 1; +L_0x19a0c60 .part o0x7f93f4eeeb98, 19, 1; +L_0x19a0d80 .part o0x7f93f4eeebc8, 19, 1; +L_0x19a16d0 .part o0x7f93f4eeeb98, 20, 1; +L_0x19a17f0 .part o0x7f93f4eeebc8, 20, 1; +L_0x19a2110 .part o0x7f93f4eeeb98, 21, 1; +L_0x19a2270 .part o0x7f93f4eeebc8, 21, 1; +L_0x19a2b40 .part o0x7f93f4eeeb98, 22, 1; +L_0x19a2c60 .part o0x7f93f4eeebc8, 22, 1; +L_0x19a3590 .part o0x7f93f4eeeb98, 23, 1; +L_0x19a36b0 .part o0x7f93f4eeebc8, 23, 1; +L_0x19a3ff0 .part o0x7f93f4eeeb98, 24, 1; +L_0x19a4110 .part o0x7f93f4eeebc8, 24, 1; +L_0x19a4a60 .part o0x7f93f4eeeb98, 25, 1; +L_0x19a4b80 .part o0x7f93f4eeebc8, 25, 1; +L_0x19a54a0 .part o0x7f93f4eeeb98, 26, 1; +L_0x19a5600 .part o0x7f93f4eeebc8, 26, 1; +L_0x19a5ed0 .part o0x7f93f4eeeb98, 27, 1; +L_0x19a5ff0 .part o0x7f93f4eeebc8, 27, 1; +L_0x19a6920 .part o0x7f93f4eeeb98, 28, 1; +L_0x19a6a40 .part o0x7f93f4eeebc8, 28, 1; +L_0x19a7360 .part o0x7f93f4eeeb98, 29, 1; +L_0x19a7480 .part o0x7f93f4eeebc8, 29, 1; +L_0x19a7e00 .part o0x7f93f4eeeb98, 30, 1; +L_0x19a7f20 .part o0x7f93f4eeebc8, 30, 1; +L_0x19a7630 .part L_0x19adbe0, 1, 1; +L_0x19a83b0 .part L_0x19adbe0, 2, 1; +L_0x19a8710 .part L_0x19adbe0, 3, 1; +L_0x19a8900 .part L_0x19adbe0, 4, 1; +L_0x19a8670 .part L_0x19adbe0, 5, 1; +L_0x19a8dd0 .part L_0x19adbe0, 6, 1; +L_0x19a8bc0 .part L_0x19adbe0, 7, 1; +L_0x19a9350 .part L_0x19adbe0, 8, 1; +L_0x19a9040 .part L_0x19adbe0, 9, 1; +L_0x19a9840 .part L_0x19adbe0, 10, 1; +L_0x19a95c0 .part L_0x19adbe0, 11, 1; +L_0x19a9d40 .part L_0x19adbe0, 12, 1; +L_0x19a9ab0 .part L_0x19adbe0, 13, 1; +L_0x19aa250 .part L_0x19adbe0, 14, 1; +L_0x19a9fb0 .part L_0x19adbe0, 15, 1; +L_0x19aa870 .part L_0x19adbe0, 16, 1; +L_0x19aa4c0 .part L_0x19adbe0, 17, 1; +L_0x19aace0 .part L_0x19adbe0, 18, 1; +L_0x19aaa70 .part L_0x19adbe0, 19, 1; +L_0x19ab1d0 .part L_0x19adbe0, 20, 1; +L_0x19aaf50 .part L_0x19adbe0, 21, 1; +L_0x19ab6d0 .part L_0x19adbe0, 22, 1; +L_0x19ab440 .part L_0x19adbe0, 23, 1; +L_0x19abbe0 .part L_0x19adbe0, 24, 1; +L_0x19ab940 .part L_0x19adbe0, 25, 1; +L_0x19ac100 .part L_0x19adbe0, 26, 1; +L_0x19abe50 .part L_0x19adbe0, 27, 1; +L_0x19ac630 .part L_0x19adbe0, 28, 1; +L_0x19ac370 .part L_0x19adbe0, 29, 1; +L_0x19ad1d0 .part o0x7f93f4eeeb98, 0, 1; +L_0x19ac790 .part o0x7f93f4eeebc8, 0, 1; +LS_0x19adbe0_0_0 .concat8 [ 1 1 1 1], L_0x19acc10, L_0x1994d90, L_0x1995770, L_0x1996150; +LS_0x19adbe0_0_4 .concat8 [ 1 1 1 1], L_0x1996b30, L_0x1997560, L_0x1997f50, L_0x19989a0; +LS_0x19adbe0_0_8 .concat8 [ 1 1 1 1], L_0x1999340, L_0x1999db0, L_0x199a7a0, L_0x199b1c0; +LS_0x19adbe0_0_12 .concat8 [ 1 1 1 1], L_0x199bbf0, L_0x199c590, L_0x199cf90, L_0x199d9a0; +LS_0x19adbe0_0_16 .concat8 [ 1 1 1 1], L_0x199e3c0, L_0x199f1f0, L_0x199fc40, L_0x19a06a0; +LS_0x19adbe0_0_20 .concat8 [ 1 1 1 1], L_0x19a1110, L_0x19a1b90, L_0x19a2580, L_0x19a2fd0; +LS_0x19adbe0_0_24 .concat8 [ 1 1 1 1], L_0x19a3a30, L_0x19a44a0, L_0x19a4f20, L_0x19a5910; +LS_0x19adbe0_0_28 .concat8 [ 1 1 1 1], L_0x19a6360, L_0x19a6da0, L_0x19a77f0, L_0x19ad660; +LS_0x19adbe0_1_0 .concat8 [ 4 4 4 4], LS_0x19adbe0_0_0, LS_0x19adbe0_0_4, LS_0x19adbe0_0_8, LS_0x19adbe0_0_12; +LS_0x19adbe0_1_4 .concat8 [ 4 4 4 4], LS_0x19adbe0_0_16, LS_0x19adbe0_0_20, LS_0x19adbe0_0_24, LS_0x19adbe0_0_28; +L_0x19adbe0 .concat8 [ 16 16 0 0], LS_0x19adbe0_1_0, LS_0x19adbe0_1_4; +L_0x19ad330 .part o0x7f93f4eeeb98, 31, 1; +L_0x19ad3d0 .part o0x7f93f4eeebc8, 31, 1; +L_0x19aec60 .part L_0x19adbe0, 0, 1; +L_0x19aa660 .part L_0x19adbe0, 1, 1; +L_0x19ae800 .part L_0x19adbe0, 31, 1; +S_0x182e6f0 .scope module, "adderfinal" "FullAdder1bit" 2 50, 2 8 0, S_0x1830720; + .timescale 0 0; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b0" + .port_info 4 /INPUT 1 "carryin" + .port_info 5 /INPUT 1 "subtract" +L_0x19ad270/d .functor XOR 1, L_0x19ad3d0, L_0x19ada80, C4<0>, C4<0>; +L_0x19ad270 .delay 1 (20,20,20) L_0x19ad270/d; +L_0x19ac910/d .functor XOR 1, L_0x19ad330, L_0x19ad270, C4<0>, C4<0>; +L_0x19ac910 .delay 1 (20,20,20) L_0x19ac910/d; +L_0x19ad660/d .functor XOR 1, L_0x19ac910, L_0x7f93f4ea00f0, C4<0>, C4<0>; +L_0x19ad660 .delay 1 (20,20,20) L_0x19ad660/d; +L_0x19ad7c0/d .functor AND 1, L_0x19ad330, L_0x19ad270, C4<1>, C4<1>; +L_0x19ad7c0 .delay 1 (20,20,20) L_0x19ad7c0/d; +L_0x19ad920/d .functor AND 1, L_0x19ac910, L_0x7f93f4ea00f0, C4<1>, C4<1>; +L_0x19ad920 .delay 1 (20,20,20) L_0x19ad920/d; +L_0x19ada80/d .functor OR 1, L_0x19ad7c0, L_0x19ad920, C4<0>, C4<0>; +L_0x19ada80 .delay 1 (20,20,20) L_0x19ada80/d; +v0x17c7c20_0 .net "a", 0 0, L_0x19ad330; 1 drivers +v0x17c5bf0_0 .net "b", 0 0, L_0x19ad270; 1 drivers +v0x17c5cb0_0 .net "b0", 0 0, L_0x19ad3d0; 1 drivers +v0x17c3bc0_0 .net "carryin", 0 0, L_0x7f93f4ea00f0; alias, 1 drivers +v0x17c3c80_0 .net "carryout", 0 0, L_0x19ada80; alias, 1 drivers +v0x17c1b90_0 .net "cout1", 0 0, L_0x19ad7c0; 1 drivers +v0x17c1c50_0 .net "cout2", 0 0, L_0x19ad920; 1 drivers +v0x17af920_0 .net "subtract", 0 0, L_0x19ada80; alias, 1 drivers +v0x17af9c0_0 .net "sum", 0 0, L_0x19ad660; 1 drivers +v0x17ad8f0_0 .net "sumAB", 0 0, L_0x19ac910; 1 drivers +S_0x182c6c0 .scope module, "adderinit" "FullAdder1bit" 2 45, 2 8 0, S_0x1830720; + .timescale 0 0; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b0" + .port_info 4 /INPUT 1 "carryin" + .port_info 5 /INPUT 1 "subtract" +L_0x19ac410/d .functor XOR 1, L_0x19ac790, L_0x7f93f4ea00f0, C4<0>, C4<0>; +L_0x19ac410 .delay 1 (20,20,20) L_0x19ac410/d; +L_0x19acab0/d .functor XOR 1, L_0x19ad1d0, L_0x19ac410, C4<0>, C4<0>; +L_0x19acab0 .delay 1 (20,20,20) L_0x19acab0/d; +L_0x19acc10/d .functor XOR 1, L_0x19acab0, L_0x7f93f4ea00f0, C4<0>, C4<0>; +L_0x19acc10 .delay 1 (20,20,20) L_0x19acc10/d; +L_0x19acd70/d .functor AND 1, L_0x19ad1d0, L_0x19ac410, C4<1>, C4<1>; +L_0x19acd70 .delay 1 (20,20,20) L_0x19acd70/d; +L_0x19aced0/d .functor AND 1, L_0x19acab0, L_0x7f93f4ea00f0, C4<1>, C4<1>; +L_0x19aced0 .delay 1 (20,20,20) L_0x19aced0/d; +L_0x19ad030/d .functor OR 1, L_0x19acd70, L_0x19aced0, C4<0>, C4<0>; +L_0x19ad030 .delay 1 (20,20,20) L_0x19ad030/d; +v0x17ab960_0 .net "a", 0 0, L_0x19ad1d0; 1 drivers +v0x17a9890_0 .net "b", 0 0, L_0x19ac410; 1 drivers +v0x17a9950_0 .net "b0", 0 0, L_0x19ac790; 1 drivers +v0x17a7860_0 .net "carryin", 0 0, L_0x7f93f4ea00f0; alias, 1 drivers +v0x17a7900_0 .net "carryout", 0 0, L_0x19ad030; alias, 1 drivers +v0x17a5830_0 .net "cout1", 0 0, L_0x19acd70; 1 drivers +v0x17a58d0_0 .net "cout2", 0 0, L_0x19aced0; 1 drivers +v0x17a3800_0 .net "subtract", 0 0, L_0x7f93f4ea00f0; alias, 1 drivers +v0x17a17d0_0 .net "sum", 0 0, L_0x19acc10; 1 drivers +v0x18e84f0_0 .net "sumAB", 0 0, L_0x19acab0; 1 drivers +S_0x182a690 .scope generate, "genblk1[1]" "genblk1[1]" 2 47, 2 47 0, S_0x1830720; + .timescale 0 0; +P_0x182a850 .param/l "i" 0 2 47, +C4<01>; +S_0x17cf960 .scope module, "addermid" "FullAdder1bit" 2 48, 2 8 0, S_0x182a690; + .timescale 0 0; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b0" + .port_info 4 /INPUT 1 "carryin" + .port_info 5 /INPUT 1 "subtract" +L_0x1994b70/d .functor XOR 1, L_0x1995470, L_0x19ad030, C4<0>, C4<0>; +L_0x1994b70 .delay 1 (20,20,20) L_0x1994b70/d; +L_0x1994c30/d .functor XOR 1, L_0x1995310, L_0x1994b70, C4<0>, C4<0>; +L_0x1994c30 .delay 1 (20,20,20) L_0x1994c30/d; +L_0x1994d90/d .functor XOR 1, L_0x1994c30, L_0x7f93f4ea00f0, C4<0>, C4<0>; +L_0x1994d90 .delay 1 (20,20,20) L_0x1994d90/d; +L_0x1994ef0/d .functor AND 1, L_0x1995310, L_0x1994b70, C4<1>, C4<1>; +L_0x1994ef0 .delay 1 (20,20,20) L_0x1994ef0/d; +L_0x1995050/d .functor AND 1, L_0x1994c30, L_0x7f93f4ea00f0, C4<1>, C4<1>; +L_0x1995050 .delay 1 (20,20,20) L_0x1995050/d; +L_0x19951b0/d .functor OR 1, L_0x1994ef0, L_0x1995050, C4<0>, C4<0>; +L_0x19951b0 .delay 1 (20,20,20) L_0x19951b0/d; +v0x190a090_0 .net "a", 0 0, L_0x1995310; 1 drivers +v0x18e26b0_0 .net "b", 0 0, L_0x1994b70; 1 drivers +v0x18e2770_0 .net "b0", 0 0, L_0x1995470; 1 drivers +v0x18d44b0_0 .net "carryin", 0 0, L_0x7f93f4ea00f0; alias, 1 drivers +v0x18d4550_0 .net "carryout", 0 0, L_0x19951b0; alias, 1 drivers +v0x18d2450_0 .net "cout1", 0 0, L_0x1994ef0; 1 drivers +v0x18d2510_0 .net "cout2", 0 0, L_0x1995050; 1 drivers +v0x18c0290_0 .net "subtract", 0 0, L_0x19ad030; alias, 1 drivers +v0x18c0330_0 .net "sum", 0 0, L_0x1994d90; 1 drivers +v0x18be2e0_0 .net "sumAB", 0 0, L_0x1994c30; 1 drivers +S_0x17cd930 .scope generate, "genblk1[2]" "genblk1[2]" 2 47, 2 47 0, S_0x1830720; + .timescale 0 0; +P_0x17cdaf0 .param/l "i" 0 2 47, +C4<010>; +S_0x17cb900 .scope module, "addermid" "FullAdder1bit" 2 48, 2 8 0, S_0x17cd930; + .timescale 0 0; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b0" + .port_info 4 /INPUT 1 "carryin" + .port_info 5 /INPUT 1 "subtract" +L_0x1995510/d .functor XOR 1, L_0x1995e50, L_0x19951b0, C4<0>, C4<0>; +L_0x1995510 .delay 1 (20,20,20) L_0x1995510/d; +L_0x1995610/d .functor XOR 1, L_0x1995cf0, L_0x1995510, C4<0>, C4<0>; +L_0x1995610 .delay 1 (20,20,20) L_0x1995610/d; +L_0x1995770/d .functor XOR 1, L_0x1995610, L_0x7f93f4ea00f0, C4<0>, C4<0>; +L_0x1995770 .delay 1 (20,20,20) L_0x1995770/d; +L_0x19958d0/d .functor AND 1, L_0x1995cf0, L_0x1995510, C4<1>, C4<1>; +L_0x19958d0 .delay 1 (20,20,20) L_0x19958d0/d; +L_0x1995a30/d .functor AND 1, L_0x1995610, L_0x7f93f4ea00f0, C4<1>, C4<1>; +L_0x1995a30 .delay 1 (20,20,20) L_0x1995a30/d; +L_0x1995b90/d .functor OR 1, L_0x19958d0, L_0x1995a30, C4<0>, C4<0>; +L_0x1995b90 .delay 1 (20,20,20) L_0x1995b90/d; +v0x18bc2b0_0 .net "a", 0 0, L_0x1995cf0; 1 drivers +v0x18ba1b0_0 .net "b", 0 0, L_0x1995510; 1 drivers +v0x18ba270_0 .net "b0", 0 0, L_0x1995e50; 1 drivers +v0x18b80a0_0 .net "carryin", 0 0, L_0x7f93f4ea00f0; alias, 1 drivers +v0x188c8a0_0 .net "carryout", 0 0, L_0x1995b90; alias, 1 drivers +v0x188c960_0 .net "cout1", 0 0, L_0x19958d0; 1 drivers +v0x18470d0_0 .net "cout2", 0 0, L_0x1995a30; 1 drivers +v0x1847190_0 .net "subtract", 0 0, L_0x19951b0; alias, 1 drivers +v0x1820140_0 .net "sum", 0 0, L_0x1995770; 1 drivers +v0x181e130_0 .net "sumAB", 0 0, L_0x1995610; 1 drivers +S_0x17c98d0 .scope generate, "genblk1[3]" "genblk1[3]" 2 47, 2 47 0, S_0x1830720; + .timescale 0 0; +P_0x17c9a90 .param/l "i" 0 2 47, +C4<011>; +S_0x17c78a0 .scope module, "addermid" "FullAdder1bit" 2 48, 2 8 0, S_0x17c98d0; + .timescale 0 0; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b0" + .port_info 4 /INPUT 1 "carryin" + .port_info 5 /INPUT 1 "subtract" +L_0x1995ef0/d .functor XOR 1, L_0x1996830, L_0x1995b90, C4<0>, C4<0>; +L_0x1995ef0 .delay 1 (20,20,20) L_0x1995ef0/d; +L_0x1995ff0/d .functor XOR 1, L_0x19966d0, L_0x1995ef0, C4<0>, C4<0>; +L_0x1995ff0 .delay 1 (20,20,20) L_0x1995ff0/d; +L_0x1996150/d .functor XOR 1, L_0x1995ff0, L_0x7f93f4ea00f0, C4<0>, C4<0>; +L_0x1996150 .delay 1 (20,20,20) L_0x1996150/d; +L_0x19962b0/d .functor AND 1, L_0x19966d0, L_0x1995ef0, C4<1>, C4<1>; +L_0x19962b0 .delay 1 (20,20,20) L_0x19962b0/d; +L_0x1996410/d .functor AND 1, L_0x1995ff0, L_0x7f93f4ea00f0, C4<1>, C4<1>; +L_0x1996410 .delay 1 (20,20,20) L_0x1996410/d; +L_0x1996570/d .functor OR 1, L_0x19962b0, L_0x1996410, C4<0>, C4<0>; +L_0x1996570 .delay 1 (20,20,20) L_0x1996570/d; +v0x181c190_0 .net "a", 0 0, L_0x19966d0; 1 drivers +v0x181a0b0_0 .net "b", 0 0, L_0x1995ef0; 1 drivers +v0x181a170_0 .net "b0", 0 0, L_0x1996830; 1 drivers +v0x1818070_0 .net "carryin", 0 0, L_0x7f93f4ea00f0; alias, 1 drivers +v0x1818110_0 .net "carryout", 0 0, L_0x1996570; alias, 1 drivers +v0x1816030_0 .net "cout1", 0 0, L_0x19962b0; 1 drivers +v0x18160f0_0 .net "cout2", 0 0, L_0x1996410; 1 drivers +v0x1813ff0_0 .net "subtract", 0 0, L_0x1995b90; alias, 1 drivers +v0x1814090_0 .net "sum", 0 0, L_0x1996150; 1 drivers +v0x17b4fb0_0 .net "sumAB", 0 0, L_0x1995ff0; 1 drivers +S_0x17c5870 .scope generate, "genblk1[4]" "genblk1[4]" 2 47, 2 47 0, S_0x1830720; + .timescale 0 0; +P_0x17c5a30 .param/l "i" 0 2 47, +C4<0100>; +S_0x17c3840 .scope module, "addermid" "FullAdder1bit" 2 48, 2 8 0, S_0x17c5870; + .timescale 0 0; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b0" + .port_info 4 /INPUT 1 "carryin" + .port_info 5 /INPUT 1 "subtract" +L_0x19968d0/d .functor XOR 1, L_0x1997210, L_0x1996570, C4<0>, C4<0>; +L_0x19968d0 .delay 1 (20,20,20) L_0x19968d0/d; +L_0x19969d0/d .functor XOR 1, L_0x19970b0, L_0x19968d0, C4<0>, C4<0>; +L_0x19969d0 .delay 1 (20,20,20) L_0x19969d0/d; +L_0x1996b30/d .functor XOR 1, L_0x19969d0, L_0x7f93f4ea00f0, C4<0>, C4<0>; +L_0x1996b30 .delay 1 (20,20,20) L_0x1996b30/d; +L_0x1996c90/d .functor AND 1, L_0x19970b0, L_0x19968d0, C4<1>, C4<1>; +L_0x1996c90 .delay 1 (20,20,20) L_0x1996c90/d; +L_0x1996df0/d .functor AND 1, L_0x19969d0, L_0x7f93f4ea00f0, C4<1>, C4<1>; +L_0x1996df0 .delay 1 (20,20,20) L_0x1996df0/d; +L_0x1996f50/d .functor OR 1, L_0x1996c90, L_0x1996df0, C4<0>, C4<0>; +L_0x1996f50 .delay 1 (20,20,20) L_0x1996f50/d; +v0x17eee50_0 .net "a", 0 0, L_0x19970b0; 1 drivers +v0x17b92c0_0 .net "b", 0 0, L_0x19968d0; 1 drivers +v0x17b9380_0 .net "b0", 0 0, L_0x1997210; 1 drivers +v0x17b7280_0 .net "carryin", 0 0, L_0x7f93f4ea00f0; alias, 1 drivers +v0x17b7320_0 .net "carryout", 0 0, L_0x1996f50; alias, 1 drivers +v0x17b5240_0 .net "cout1", 0 0, L_0x1996c90; 1 drivers +v0x17b5300_0 .net "cout2", 0 0, L_0x1996df0; 1 drivers +v0x17b3200_0 .net "subtract", 0 0, L_0x1996570; alias, 1 drivers +v0x17b32a0_0 .net "sum", 0 0, L_0x1996b30; 1 drivers +v0x17b1230_0 .net "sumAB", 0 0, L_0x19969d0; 1 drivers +S_0x17c1810 .scope generate, "genblk1[5]" "genblk1[5]" 2 47, 2 47 0, S_0x1830720; + .timescale 0 0; +P_0x17c19d0 .param/l "i" 0 2 47, +C4<0101>; +S_0x18f0c50 .scope module, "addermid" "FullAdder1bit" 2 48, 2 8 0, S_0x17c1810; + .timescale 0 0; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b0" + .port_info 4 /INPUT 1 "carryin" + .port_info 5 /INPUT 1 "subtract" +L_0x1997300/d .functor XOR 1, L_0x1997c40, L_0x1996f50, C4<0>, C4<0>; +L_0x1997300 .delay 1 (20,20,20) L_0x1997300/d; +L_0x1997400/d .functor XOR 1, L_0x1997ae0, L_0x1997300, C4<0>, C4<0>; +L_0x1997400 .delay 1 (20,20,20) L_0x1997400/d; +L_0x1997560/d .functor XOR 1, L_0x1997400, L_0x7f93f4ea00f0, C4<0>, C4<0>; +L_0x1997560 .delay 1 (20,20,20) L_0x1997560/d; +L_0x19976c0/d .functor AND 1, L_0x1997ae0, L_0x1997300, C4<1>, C4<1>; +L_0x19976c0 .delay 1 (20,20,20) L_0x19976c0/d; +L_0x1997820/d .functor AND 1, L_0x1997400, L_0x7f93f4ea00f0, C4<1>, C4<1>; +L_0x1997820 .delay 1 (20,20,20) L_0x1997820/d; +L_0x1997980/d .functor OR 1, L_0x19976c0, L_0x1997820, C4<0>, C4<0>; +L_0x1997980 .delay 1 (20,20,20) L_0x1997980/d; +v0x179f060_0 .net "a", 0 0, L_0x1997ae0; 1 drivers +v0x179ceb0_0 .net "b", 0 0, L_0x1997300; 1 drivers +v0x179cf70_0 .net "b0", 0 0, L_0x1997c40; 1 drivers +v0x18c4ab0_0 .net "carryin", 0 0, L_0x7f93f4ea00f0; alias, 1 drivers +v0x18c4b50_0 .net "carryout", 0 0, L_0x1997980; alias, 1 drivers +v0x185f540_0 .net "cout1", 0 0, L_0x19976c0; 1 drivers +v0x185f600_0 .net "cout2", 0 0, L_0x1997820; 1 drivers +v0x18abe30_0 .net "subtract", 0 0, L_0x1996f50; alias, 1 drivers +v0x18abed0_0 .net "sum", 0 0, L_0x1997560; 1 drivers +v0x17dda90_0 .net "sumAB", 0 0, L_0x1997400; 1 drivers +S_0x17f0f50 .scope generate, "genblk1[6]" "genblk1[6]" 2 47, 2 47 0, S_0x1830720; + .timescale 0 0; +P_0x17f10f0 .param/l "i" 0 2 47, +C4<0110>; +S_0x185fb70 .scope module, "addermid" "FullAdder1bit" 2 48, 2 8 0, S_0x17f0f50; + .timescale 0 0; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b0" + .port_info 4 /INPUT 1 "carryin" + .port_info 5 /INPUT 1 "subtract" +L_0x1997d40/d .functor XOR 1, L_0x1998630, L_0x1997980, C4<0>, C4<0>; +L_0x1997d40 .delay 1 (20,20,20) L_0x1997d40/d; +L_0x1997e40/d .functor XOR 1, L_0x19984d0, L_0x1997d40, C4<0>, C4<0>; +L_0x1997e40 .delay 1 (20,20,20) L_0x1997e40/d; +L_0x1997f50/d .functor XOR 1, L_0x1997e40, L_0x7f93f4ea00f0, C4<0>, C4<0>; +L_0x1997f50 .delay 1 (20,20,20) L_0x1997f50/d; +L_0x19980b0/d .functor AND 1, L_0x19984d0, L_0x1997d40, C4<1>, C4<1>; +L_0x19980b0 .delay 1 (20,20,20) L_0x19980b0/d; +L_0x1998210/d .functor AND 1, L_0x1997e40, L_0x7f93f4ea00f0, C4<1>, C4<1>; +L_0x1998210 .delay 1 (20,20,20) L_0x1998210/d; +L_0x1998370/d .functor OR 1, L_0x19980b0, L_0x1998210, C4<0>, C4<0>; +L_0x1998370 .delay 1 (20,20,20) L_0x1998370/d; +v0x1902fd0_0 .net "a", 0 0, L_0x19984d0; 1 drivers +v0x1860790_0 .net "b", 0 0, L_0x1997d40; 1 drivers +v0x1860850_0 .net "b0", 0 0, L_0x1998630; 1 drivers +v0x18608f0_0 .net "carryin", 0 0, L_0x7f93f4ea00f0; alias, 1 drivers +v0x190c2a0_0 .net "carryout", 0 0, L_0x1998370; alias, 1 drivers +v0x17f0450_0 .net "cout1", 0 0, L_0x19980b0; 1 drivers +v0x17f04f0_0 .net "cout2", 0 0, L_0x1998210; 1 drivers +v0x17f05b0_0 .net "subtract", 0 0, L_0x1997980; alias, 1 drivers +v0x17f0650_0 .net "sum", 0 0, L_0x1997f50; 1 drivers +v0x190b660_0 .net "sumAB", 0 0, L_0x1997e40; 1 drivers +S_0x180b4b0 .scope generate, "genblk1[7]" "genblk1[7]" 2 47, 2 47 0, S_0x1830720; + .timescale 0 0; +P_0x17cbad0 .param/l "i" 0 2 47, +C4<0111>; +S_0x188c490 .scope module, "addermid" "FullAdder1bit" 2 48, 2 8 0, S_0x180b4b0; + .timescale 0 0; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b0" + .port_info 4 /INPUT 1 "carryin" + .port_info 5 /INPUT 1 "subtract" +L_0x1998740/d .functor XOR 1, L_0x1999030, L_0x1998370, C4<0>, C4<0>; +L_0x1998740 .delay 1 (20,20,20) L_0x1998740/d; +L_0x1998840/d .functor XOR 1, L_0x1998ed0, L_0x1998740, C4<0>, C4<0>; +L_0x1998840 .delay 1 (20,20,20) L_0x1998840/d; +L_0x19989a0/d .functor XOR 1, L_0x1998840, L_0x7f93f4ea00f0, C4<0>, C4<0>; +L_0x19989a0 .delay 1 (20,20,20) L_0x19989a0/d; +L_0x1998b00/d .functor AND 1, L_0x1998ed0, L_0x1998740, C4<1>, C4<1>; +L_0x1998b00 .delay 1 (20,20,20) L_0x1998b00/d; +L_0x1998c60/d .functor AND 1, L_0x1998840, L_0x7f93f4ea00f0, C4<1>, C4<1>; +L_0x1998c60 .delay 1 (20,20,20) L_0x1998c60/d; +L_0x1998dc0/d .functor OR 1, L_0x1998b00, L_0x1998c60, C4<0>, C4<0>; +L_0x1998dc0 .delay 1 (20,20,20) L_0x1998dc0/d; +v0x188c660_0 .net "a", 0 0, L_0x1998ed0; 1 drivers +v0x188c740_0 .net "b", 0 0, L_0x1998740; 1 drivers +v0x190b7e0_0 .net "b0", 0 0, L_0x1999030; 1 drivers +v0x190b880_0 .net "carryin", 0 0, L_0x7f93f4ea00f0; alias, 1 drivers +v0x168c960_0 .net "carryout", 0 0, L_0x1998dc0; alias, 1 drivers +v0x168ca50_0 .net "cout1", 0 0, L_0x1998b00; 1 drivers +v0x168caf0_0 .net "cout2", 0 0, L_0x1998c60; 1 drivers +v0x168cbb0_0 .net "subtract", 0 0, L_0x1998370; alias, 1 drivers +v0x168cc50_0 .net "sum", 0 0, L_0x19989a0; 1 drivers +v0x16921a0_0 .net "sumAB", 0 0, L_0x1998840; 1 drivers +S_0x1692320 .scope generate, "genblk1[8]" "genblk1[8]" 2 47, 2 47 0, S_0x1830720; + .timescale 0 0; +P_0x16924e0 .param/l "i" 0 2 47, +C4<01000>; +S_0x1679f50 .scope module, "addermid" "FullAdder1bit" 2 48, 2 8 0, S_0x1692320; + .timescale 0 0; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b0" + .port_info 4 /INPUT 1 "carryin" + .port_info 5 /INPUT 1 "subtract" +L_0x19986d0/d .functor XOR 1, L_0x1999a20, L_0x1998dc0, C4<0>, C4<0>; +L_0x19986d0 .delay 1 (20,20,20) L_0x19986d0/d; +L_0x19991e0/d .functor XOR 1, L_0x19998c0, L_0x19986d0, C4<0>, C4<0>; +L_0x19991e0 .delay 1 (20,20,20) L_0x19991e0/d; +L_0x1999340/d .functor XOR 1, L_0x19991e0, L_0x7f93f4ea00f0, C4<0>, C4<0>; +L_0x1999340 .delay 1 (20,20,20) L_0x1999340/d; +L_0x19994a0/d .functor AND 1, L_0x19998c0, L_0x19986d0, C4<1>, C4<1>; +L_0x19994a0 .delay 1 (20,20,20) L_0x19994a0/d; +L_0x1999600/d .functor AND 1, L_0x19991e0, L_0x7f93f4ea00f0, C4<1>, C4<1>; +L_0x1999600 .delay 1 (20,20,20) L_0x1999600/d; +L_0x1999760/d .functor OR 1, L_0x19994a0, L_0x1999600, C4<0>, C4<0>; +L_0x1999760 .delay 1 (20,20,20) L_0x1999760/d; +v0x167a1c0_0 .net "a", 0 0, L_0x19998c0; 1 drivers +v0x167a280_0 .net "b", 0 0, L_0x19986d0; 1 drivers +v0x1688e10_0 .net "b0", 0 0, L_0x1999a20; 1 drivers +v0x1688eb0_0 .net "carryin", 0 0, L_0x7f93f4ea00f0; alias, 1 drivers +v0x1688f50_0 .net "carryout", 0 0, L_0x1999760; alias, 1 drivers +v0x1689060_0 .net "cout1", 0 0, L_0x19994a0; 1 drivers +v0x1689120_0 .net "cout2", 0 0, L_0x1999600; 1 drivers +v0x169e700_0 .net "subtract", 0 0, L_0x1998dc0; alias, 1 drivers +v0x169e7a0_0 .net "sum", 0 0, L_0x1999340; 1 drivers +v0x169e8d0_0 .net "sumAB", 0 0, L_0x19991e0; 1 drivers +S_0x16853b0 .scope generate, "genblk1[9]" "genblk1[9]" 2 47, 2 47 0, S_0x1830720; + .timescale 0 0; +P_0x16891e0 .param/l "i" 0 2 47, +C4<01001>; +S_0x16855e0 .scope module, "addermid" "FullAdder1bit" 2 48, 2 8 0, S_0x16853b0; + .timescale 0 0; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b0" + .port_info 4 /INPUT 1 "carryin" + .port_info 5 /INPUT 1 "subtract" +L_0x1999b50/d .functor XOR 1, L_0x199a420, L_0x1999760, C4<0>, C4<0>; +L_0x1999b50 .delay 1 (20,20,20) L_0x1999b50/d; +L_0x1999c50/d .functor XOR 1, L_0x199a300, L_0x1999b50, C4<0>, C4<0>; +L_0x1999c50 .delay 1 (20,20,20) L_0x1999c50/d; +L_0x1999db0/d .functor XOR 1, L_0x1999c50, L_0x7f93f4ea00f0, C4<0>, C4<0>; +L_0x1999db0 .delay 1 (20,20,20) L_0x1999db0/d; +L_0x1999f10/d .functor AND 1, L_0x199a300, L_0x1999b50, C4<1>, C4<1>; +L_0x1999f10 .delay 1 (20,20,20) L_0x1999f10/d; +L_0x199a070/d .functor AND 1, L_0x1999c50, L_0x7f93f4ea00f0, C4<1>, C4<1>; +L_0x199a070 .delay 1 (20,20,20) L_0x199a070/d; +L_0x19990d0/d .functor OR 1, L_0x1999f10, L_0x199a070, C4<0>, C4<0>; +L_0x19990d0 .delay 1 (20,20,20) L_0x19990d0/d; +v0x1682280_0 .net "a", 0 0, L_0x199a300; 1 drivers +v0x1682340_0 .net "b", 0 0, L_0x1999b50; 1 drivers +v0x1682400_0 .net "b0", 0 0, L_0x199a420; 1 drivers +v0x16824a0_0 .net "carryin", 0 0, L_0x7f93f4ea00f0; alias, 1 drivers +v0x1682540_0 .net "carryout", 0 0, L_0x19990d0; alias, 1 drivers +v0x169bac0_0 .net "cout1", 0 0, L_0x1999f10; 1 drivers +v0x169bb80_0 .net "cout2", 0 0, L_0x199a070; 1 drivers +v0x169bc40_0 .net "subtract", 0 0, L_0x1999760; alias, 1 drivers +v0x169bce0_0 .net "sum", 0 0, L_0x1999db0; 1 drivers +v0x169be10_0 .net "sumAB", 0 0, L_0x1999c50; 1 drivers +S_0x1642cf0 .scope generate, "genblk1[10]" "genblk1[10]" 2 47, 2 47 0, S_0x1830720; + .timescale 0 0; +P_0x1682650 .param/l "i" 0 2 47, +C4<01010>; +S_0x1642f20 .scope module, "addermid" "FullAdder1bit" 2 48, 2 8 0, S_0x1642cf0; + .timescale 0 0; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b0" + .port_info 4 /INPUT 1 "carryin" + .port_info 5 /INPUT 1 "subtract" +L_0x1999ac0/d .functor XOR 1, L_0x199ae80, L_0x19990d0, C4<0>, C4<0>; +L_0x1999ac0 .delay 1 (20,20,20) L_0x1999ac0/d; +L_0x199a640/d .functor XOR 1, L_0x199ad20, L_0x1999ac0, C4<0>, C4<0>; +L_0x199a640 .delay 1 (20,20,20) L_0x199a640/d; +L_0x199a7a0/d .functor XOR 1, L_0x199a640, L_0x7f93f4ea00f0, C4<0>, C4<0>; +L_0x199a7a0 .delay 1 (20,20,20) L_0x199a7a0/d; +L_0x199a900/d .functor AND 1, L_0x199ad20, L_0x1999ac0, C4<1>, C4<1>; +L_0x199a900 .delay 1 (20,20,20) L_0x199a900/d; +L_0x199aa60/d .functor AND 1, L_0x199a640, L_0x7f93f4ea00f0, C4<1>, C4<1>; +L_0x199aa60 .delay 1 (20,20,20) L_0x199aa60/d; +L_0x199abc0/d .functor OR 1, L_0x199a900, L_0x199aa60, C4<0>, C4<0>; +L_0x199abc0 .delay 1 (20,20,20) L_0x199abc0/d; +v0x190d8a0_0 .net "a", 0 0, L_0x199ad20; 1 drivers +v0x190d940_0 .net "b", 0 0, L_0x1999ac0; 1 drivers +v0x190d9e0_0 .net "b0", 0 0, L_0x199ae80; 1 drivers +v0x190da80_0 .net "carryin", 0 0, L_0x7f93f4ea00f0; alias, 1 drivers +v0x190db20_0 .net "carryout", 0 0, L_0x199abc0; alias, 1 drivers +v0x190dbc0_0 .net "cout1", 0 0, L_0x199a900; 1 drivers +v0x190dc60_0 .net "cout2", 0 0, L_0x199aa60; 1 drivers +v0x190dd00_0 .net "subtract", 0 0, L_0x19990d0; alias, 1 drivers +v0x190dda0_0 .net "sum", 0 0, L_0x199a7a0; 1 drivers +v0x190ded0_0 .net "sumAB", 0 0, L_0x199a640; 1 drivers +S_0x190df70 .scope generate, "genblk1[11]" "genblk1[11]" 2 47, 2 47 0, S_0x1830720; + .timescale 0 0; +P_0x18e4f90 .param/l "i" 0 2 47, +C4<01011>; +S_0x190e0f0 .scope module, "addermid" "FullAdder1bit" 2 48, 2 8 0, S_0x190df70; + .timescale 0 0; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b0" + .port_info 4 /INPUT 1 "carryin" + .port_info 5 /INPUT 1 "subtract" +L_0x199a510/d .functor XOR 1, L_0x199b8a0, L_0x199abc0, C4<0>, C4<0>; +L_0x199a510 .delay 1 (20,20,20) L_0x199a510/d; +L_0x199b060/d .functor XOR 1, L_0x199b740, L_0x199a510, C4<0>, C4<0>; +L_0x199b060 .delay 1 (20,20,20) L_0x199b060/d; +L_0x199b1c0/d .functor XOR 1, L_0x199b060, L_0x7f93f4ea00f0, C4<0>, C4<0>; +L_0x199b1c0 .delay 1 (20,20,20) L_0x199b1c0/d; +L_0x199b320/d .functor AND 1, L_0x199b740, L_0x199a510, C4<1>, C4<1>; +L_0x199b320 .delay 1 (20,20,20) L_0x199b320/d; +L_0x199b480/d .functor AND 1, L_0x199b060, L_0x7f93f4ea00f0, C4<1>, C4<1>; +L_0x199b480 .delay 1 (20,20,20) L_0x199b480/d; +L_0x199b5e0/d .functor OR 1, L_0x199b320, L_0x199b480, C4<0>, C4<0>; +L_0x199b5e0 .delay 1 (20,20,20) L_0x199b5e0/d; +v0x190e310_0 .net "a", 0 0, L_0x199b740; 1 drivers +v0x190e3b0_0 .net "b", 0 0, L_0x199a510; 1 drivers +v0x190e450_0 .net "b0", 0 0, L_0x199b8a0; 1 drivers +v0x190e4f0_0 .net "carryin", 0 0, L_0x7f93f4ea00f0; alias, 1 drivers +v0x190e590_0 .net "carryout", 0 0, L_0x199b5e0; alias, 1 drivers +v0x190e630_0 .net "cout1", 0 0, L_0x199b320; 1 drivers +v0x190e6d0_0 .net "cout2", 0 0, L_0x199b480; 1 drivers +v0x190e770_0 .net "subtract", 0 0, L_0x199abc0; alias, 1 drivers +v0x190e810_0 .net "sum", 0 0, L_0x199b1c0; 1 drivers +v0x190e940_0 .net "sumAB", 0 0, L_0x199b060; 1 drivers +S_0x190e9e0 .scope generate, "genblk1[12]" "genblk1[12]" 2 47, 2 47 0, S_0x1830720; + .timescale 0 0; +P_0x1844e60 .param/l "i" 0 2 47, +C4<01100>; +S_0x190eb60 .scope module, "addermid" "FullAdder1bit" 2 48, 2 8 0, S_0x190e9e0; + .timescale 0 0; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b0" + .port_info 4 /INPUT 1 "carryin" + .port_info 5 /INPUT 1 "subtract" +L_0x199af20/d .functor XOR 1, L_0x199c2d0, L_0x199b5e0, C4<0>, C4<0>; +L_0x199af20 .delay 1 (20,20,20) L_0x199af20/d; +L_0x199ba90/d .functor XOR 1, L_0x199c170, L_0x199af20, C4<0>, C4<0>; +L_0x199ba90 .delay 1 (20,20,20) L_0x199ba90/d; +L_0x199bbf0/d .functor XOR 1, L_0x199ba90, L_0x7f93f4ea00f0, C4<0>, C4<0>; +L_0x199bbf0 .delay 1 (20,20,20) L_0x199bbf0/d; +L_0x199bd50/d .functor AND 1, L_0x199c170, L_0x199af20, C4<1>, C4<1>; +L_0x199bd50 .delay 1 (20,20,20) L_0x199bd50/d; +L_0x199beb0/d .functor AND 1, L_0x199ba90, L_0x7f93f4ea00f0, C4<1>, C4<1>; +L_0x199beb0 .delay 1 (20,20,20) L_0x199beb0/d; +L_0x199c010/d .functor OR 1, L_0x199bd50, L_0x199beb0, C4<0>, C4<0>; +L_0x199c010 .delay 1 (20,20,20) L_0x199c010/d; +v0x190ed80_0 .net "a", 0 0, L_0x199c170; 1 drivers +v0x190ee20_0 .net "b", 0 0, L_0x199af20; 1 drivers +v0x190eec0_0 .net "b0", 0 0, L_0x199c2d0; 1 drivers +v0x190ef60_0 .net "carryin", 0 0, L_0x7f93f4ea00f0; alias, 1 drivers +v0x190f000_0 .net "carryout", 0 0, L_0x199c010; alias, 1 drivers +v0x190f0a0_0 .net "cout1", 0 0, L_0x199bd50; 1 drivers +v0x190f140_0 .net "cout2", 0 0, L_0x199beb0; 1 drivers +v0x190f1e0_0 .net "subtract", 0 0, L_0x199b5e0; alias, 1 drivers +v0x190f280_0 .net "sum", 0 0, L_0x199bbf0; 1 drivers +v0x190f3b0_0 .net "sumAB", 0 0, L_0x199ba90; 1 drivers +S_0x190f450 .scope generate, "genblk1[13]" "genblk1[13]" 2 47, 2 47 0, S_0x1830720; + .timescale 0 0; +P_0x1824a60 .param/l "i" 0 2 47, +C4<01101>; +S_0x190f5d0 .scope module, "addermid" "FullAdder1bit" 2 48, 2 8 0, S_0x190f450; + .timescale 0 0; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b0" + .port_info 4 /INPUT 1 "carryin" + .port_info 5 /INPUT 1 "subtract" +L_0x199b940/d .functor XOR 1, L_0x199cc70, L_0x199c010, C4<0>, C4<0>; +L_0x199b940 .delay 1 (20,20,20) L_0x199b940/d; +L_0x199c4d0/d .functor XOR 1, L_0x199cb10, L_0x199b940, C4<0>, C4<0>; +L_0x199c4d0 .delay 1 (20,20,20) L_0x199c4d0/d; +L_0x199c590/d .functor XOR 1, L_0x199c4d0, L_0x7f93f4ea00f0, C4<0>, C4<0>; +L_0x199c590 .delay 1 (20,20,20) L_0x199c590/d; +L_0x199c6f0/d .functor AND 1, L_0x199cb10, L_0x199b940, C4<1>, C4<1>; +L_0x199c6f0 .delay 1 (20,20,20) L_0x199c6f0/d; +L_0x199c850/d .functor AND 1, L_0x199c4d0, L_0x7f93f4ea00f0, C4<1>, C4<1>; +L_0x199c850 .delay 1 (20,20,20) L_0x199c850/d; +L_0x199c9b0/d .functor OR 1, L_0x199c6f0, L_0x199c850, C4<0>, C4<0>; +L_0x199c9b0 .delay 1 (20,20,20) L_0x199c9b0/d; +v0x190f7f0_0 .net "a", 0 0, L_0x199cb10; 1 drivers +v0x190f890_0 .net "b", 0 0, L_0x199b940; 1 drivers +v0x190f930_0 .net "b0", 0 0, L_0x199cc70; 1 drivers +v0x190f9d0_0 .net "carryin", 0 0, L_0x7f93f4ea00f0; alias, 1 drivers +v0x190fa70_0 .net "carryout", 0 0, L_0x199c9b0; alias, 1 drivers +v0x190fb10_0 .net "cout1", 0 0, L_0x199c6f0; 1 drivers +v0x190fbb0_0 .net "cout2", 0 0, L_0x199c850; 1 drivers +v0x190fc50_0 .net "subtract", 0 0, L_0x199c010; alias, 1 drivers +v0x190fcf0_0 .net "sum", 0 0, L_0x199c590; 1 drivers +v0x190fe20_0 .net "sumAB", 0 0, L_0x199c4d0; 1 drivers +S_0x190ff00 .scope generate, "genblk1[14]" "genblk1[14]" 2 47, 2 47 0, S_0x1830720; + .timescale 0 0; +P_0x19100c0 .param/l "i" 0 2 47, +C4<01110>; +S_0x1910180 .scope module, "addermid" "FullAdder1bit" 2 48, 2 8 0, S_0x190ff00; + .timescale 0 0; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b0" + .port_info 4 /INPUT 1 "carryin" + .port_info 5 /INPUT 1 "subtract" +L_0x199c370/d .functor XOR 1, L_0x199d670, L_0x199c9b0, C4<0>, C4<0>; +L_0x199c370 .delay 1 (20,20,20) L_0x199c370/d; +L_0x199ce80/d .functor XOR 1, L_0x199d510, L_0x199c370, C4<0>, C4<0>; +L_0x199ce80 .delay 1 (20,20,20) L_0x199ce80/d; +L_0x199cf90/d .functor XOR 1, L_0x199ce80, L_0x7f93f4ea00f0, C4<0>, C4<0>; +L_0x199cf90 .delay 1 (20,20,20) L_0x199cf90/d; +L_0x199d0f0/d .functor AND 1, L_0x199d510, L_0x199c370, C4<1>, C4<1>; +L_0x199d0f0 .delay 1 (20,20,20) L_0x199d0f0/d; +L_0x199d250/d .functor AND 1, L_0x199ce80, L_0x7f93f4ea00f0, C4<1>, C4<1>; +L_0x199d250 .delay 1 (20,20,20) L_0x199d250/d; +L_0x199d3b0/d .functor OR 1, L_0x199d0f0, L_0x199d250, C4<0>, C4<0>; +L_0x199d3b0 .delay 1 (20,20,20) L_0x199d3b0/d; +v0x19103f0_0 .net "a", 0 0, L_0x199d510; 1 drivers +v0x19104d0_0 .net "b", 0 0, L_0x199c370; 1 drivers +v0x1910590_0 .net "b0", 0 0, L_0x199d670; 1 drivers +v0x1910630_0 .net "carryin", 0 0, L_0x7f93f4ea00f0; alias, 1 drivers +v0x190c190_0 .net "carryout", 0 0, L_0x199d3b0; alias, 1 drivers +v0x19108e0_0 .net "cout1", 0 0, L_0x199d0f0; 1 drivers +v0x19109a0_0 .net "cout2", 0 0, L_0x199d250; 1 drivers +v0x1910a60_0 .net "subtract", 0 0, L_0x199c9b0; alias, 1 drivers +v0x1910b00_0 .net "sum", 0 0, L_0x199cf90; 1 drivers +v0x1910c50_0 .net "sumAB", 0 0, L_0x199ce80; 1 drivers +S_0x1910e10 .scope generate, "genblk1[15]" "genblk1[15]" 2 47, 2 47 0, S_0x1830720; + .timescale 0 0; +P_0x180b670 .param/l "i" 0 2 47, +C4<01111>; +S_0x1911130 .scope module, "addermid" "FullAdder1bit" 2 48, 2 8 0, S_0x1910e10; + .timescale 0 0; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b0" + .port_info 4 /INPUT 1 "carryin" + .port_info 5 /INPUT 1 "subtract" +L_0x199cd10/d .functor XOR 1, L_0x199e080, L_0x199d3b0, C4<0>, C4<0>; +L_0x199cd10 .delay 1 (20,20,20) L_0x199cd10/d; +L_0x199d890/d .functor XOR 1, L_0x199df20, L_0x199cd10, C4<0>, C4<0>; +L_0x199d890 .delay 1 (20,20,20) L_0x199d890/d; +L_0x199d9a0/d .functor XOR 1, L_0x199d890, L_0x7f93f4ea00f0, C4<0>, C4<0>; +L_0x199d9a0 .delay 1 (20,20,20) L_0x199d9a0/d; +L_0x199db00/d .functor AND 1, L_0x199df20, L_0x199cd10, C4<1>, C4<1>; +L_0x199db00 .delay 1 (20,20,20) L_0x199db00/d; +L_0x199dc60/d .functor AND 1, L_0x199d890, L_0x7f93f4ea00f0, C4<1>, C4<1>; +L_0x199dc60 .delay 1 (20,20,20) L_0x199dc60/d; +L_0x199ddc0/d .functor OR 1, L_0x199db00, L_0x199dc60, C4<0>, C4<0>; +L_0x199ddc0 .delay 1 (20,20,20) L_0x199ddc0/d; +v0x19113a0_0 .net "a", 0 0, L_0x199df20; 1 drivers +v0x1911460_0 .net "b", 0 0, L_0x199cd10; 1 drivers +v0x1911520_0 .net "b0", 0 0, L_0x199e080; 1 drivers +v0x19115c0_0 .net "carryin", 0 0, L_0x7f93f4ea00f0; alias, 1 drivers +v0x1911660_0 .net "carryout", 0 0, L_0x199ddc0; alias, 1 drivers +v0x1911770_0 .net "cout1", 0 0, L_0x199db00; 1 drivers +v0x1911830_0 .net "cout2", 0 0, L_0x199dc60; 1 drivers +v0x19118f0_0 .net "subtract", 0 0, L_0x199d3b0; alias, 1 drivers +v0x1911990_0 .net "sum", 0 0, L_0x199d9a0; 1 drivers +v0x1911ac0_0 .net "sumAB", 0 0, L_0x199d890; 1 drivers +S_0x1911c80 .scope generate, "genblk1[16]" "genblk1[16]" 2 47, 2 47 0, S_0x1830720; + .timescale 0 0; +P_0x1911e40 .param/l "i" 0 2 47, +C4<010000>; +S_0x1911f00 .scope module, "addermid" "FullAdder1bit" 2 48, 2 8 0, S_0x1911c80; + .timescale 0 0; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b0" + .port_info 4 /INPUT 1 "carryin" + .port_info 5 /INPUT 1 "subtract" +L_0x199d710/d .functor XOR 1, L_0x199eee0, L_0x199ddc0, C4<0>, C4<0>; +L_0x199d710 .delay 1 (20,20,20) L_0x199d710/d; +L_0x199e2b0/d .functor XOR 1, L_0x199ed80, L_0x199d710, C4<0>, C4<0>; +L_0x199e2b0 .delay 1 (20,20,20) L_0x199e2b0/d; +L_0x199e3c0/d .functor XOR 1, L_0x199e2b0, L_0x7f93f4ea00f0, C4<0>, C4<0>; +L_0x199e3c0 .delay 1 (20,20,20) L_0x199e3c0/d; +L_0x191e6f0/d .functor AND 1, L_0x199ed80, L_0x199d710, C4<1>, C4<1>; +L_0x191e6f0 .delay 1 (20,20,20) L_0x191e6f0/d; +L_0x191e850/d .functor AND 1, L_0x199e2b0, L_0x7f93f4ea00f0, C4<1>, C4<1>; +L_0x191e850 .delay 1 (20,20,20) L_0x191e850/d; +L_0x191e9b0/d .functor OR 1, L_0x191e6f0, L_0x191e850, C4<0>, C4<0>; +L_0x191e9b0 .delay 1 (20,20,20) L_0x191e9b0/d; +v0x1912170_0 .net "a", 0 0, L_0x199ed80; 1 drivers +v0x1912250_0 .net "b", 0 0, L_0x199d710; 1 drivers +v0x1912310_0 .net "b0", 0 0, L_0x199eee0; 1 drivers +v0x19123b0_0 .net "carryin", 0 0, L_0x7f93f4ea00f0; alias, 1 drivers +v0x1912450_0 .net "carryout", 0 0, L_0x191e9b0; alias, 1 drivers +v0x1912560_0 .net "cout1", 0 0, L_0x191e6f0; 1 drivers +v0x1912620_0 .net "cout2", 0 0, L_0x191e850; 1 drivers +v0x19126e0_0 .net "subtract", 0 0, L_0x199ddc0; alias, 1 drivers +v0x1912780_0 .net "sum", 0 0, L_0x199e3c0; 1 drivers +v0x19128b0_0 .net "sumAB", 0 0, L_0x199e2b0; 1 drivers +S_0x1912a70 .scope generate, "genblk1[17]" "genblk1[17]" 2 47, 2 47 0, S_0x1830720; + .timescale 0 0; +P_0x1912c30 .param/l "i" 0 2 47, +C4<010001>; +S_0x1912cf0 .scope module, "addermid" "FullAdder1bit" 2 48, 2 8 0, S_0x1912a70; + .timescale 0 0; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b0" + .port_info 4 /INPUT 1 "carryin" + .port_info 5 /INPUT 1 "subtract" +L_0x199e120/d .functor XOR 1, L_0x199f8d0, L_0x191e9b0, C4<0>, C4<0>; +L_0x199e120 .delay 1 (20,20,20) L_0x199e120/d; +L_0x199f090/d .functor XOR 1, L_0x199f7b0, L_0x199e120, C4<0>, C4<0>; +L_0x199f090 .delay 1 (20,20,20) L_0x199f090/d; +L_0x199f1f0/d .functor XOR 1, L_0x199f090, L_0x7f93f4ea00f0, C4<0>, C4<0>; +L_0x199f1f0 .delay 1 (20,20,20) L_0x199f1f0/d; +L_0x199f350/d .functor AND 1, L_0x199f7b0, L_0x199e120, C4<1>, C4<1>; +L_0x199f350 .delay 1 (20,20,20) L_0x199f350/d; +L_0x199f4b0/d .functor AND 1, L_0x199f090, L_0x7f93f4ea00f0, C4<1>, C4<1>; +L_0x199f4b0 .delay 1 (20,20,20) L_0x199f4b0/d; +L_0x199f610/d .functor OR 1, L_0x199f350, L_0x199f4b0, C4<0>, C4<0>; +L_0x199f610 .delay 1 (20,20,20) L_0x199f610/d; +v0x1912f60_0 .net "a", 0 0, L_0x199f7b0; 1 drivers +v0x1913000_0 .net "b", 0 0, L_0x199e120; 1 drivers +v0x19130a0_0 .net "b0", 0 0, L_0x199f8d0; 1 drivers +v0x1913140_0 .net "carryin", 0 0, L_0x7f93f4ea00f0; alias, 1 drivers +v0x19131e0_0 .net "carryout", 0 0, L_0x199f610; alias, 1 drivers +v0x1913280_0 .net "cout1", 0 0, L_0x199f350; 1 drivers +v0x1913320_0 .net "cout2", 0 0, L_0x199f4b0; 1 drivers +v0x19133c0_0 .net "subtract", 0 0, L_0x191e9b0; alias, 1 drivers +v0x1913460_0 .net "sum", 0 0, L_0x199f1f0; 1 drivers +v0x1913590_0 .net "sumAB", 0 0, L_0x199f090; 1 drivers +S_0x1913670 .scope generate, "genblk1[18]" "genblk1[18]" 2 47, 2 47 0, S_0x1830720; + .timescale 0 0; +P_0x1913840 .param/l "i" 0 2 47, +C4<010010>; +S_0x19138e0 .scope module, "addermid" "FullAdder1bit" 2 48, 2 8 0, S_0x1913670; + .timescale 0 0; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b0" + .port_info 4 /INPUT 1 "carryin" + .port_info 5 /INPUT 1 "subtract" +L_0x199ef80/d .functor XOR 1, L_0x19a0320, L_0x199f610, C4<0>, C4<0>; +L_0x199ef80 .delay 1 (20,20,20) L_0x199ef80/d; +L_0x199fae0/d .functor XOR 1, L_0x19a0200, L_0x199ef80, C4<0>, C4<0>; +L_0x199fae0 .delay 1 (20,20,20) L_0x199fae0/d; +L_0x199fc40/d .functor XOR 1, L_0x199fae0, L_0x7f93f4ea00f0, C4<0>, C4<0>; +L_0x199fc40 .delay 1 (20,20,20) L_0x199fc40/d; +L_0x199fda0/d .functor AND 1, L_0x19a0200, L_0x199ef80, C4<1>, C4<1>; +L_0x199fda0 .delay 1 (20,20,20) L_0x199fda0/d; +L_0x199ff00/d .functor AND 1, L_0x199fae0, L_0x7f93f4ea00f0, C4<1>, C4<1>; +L_0x199ff00 .delay 1 (20,20,20) L_0x199ff00/d; +L_0x19a0060/d .functor OR 1, L_0x199fda0, L_0x199ff00, C4<0>, C4<0>; +L_0x19a0060 .delay 1 (20,20,20) L_0x19a0060/d; +v0x1913b50_0 .net "a", 0 0, L_0x19a0200; 1 drivers +v0x1913bf0_0 .net "b", 0 0, L_0x199ef80; 1 drivers +v0x1913cd0_0 .net "b0", 0 0, L_0x19a0320; 1 drivers +v0x1913d70_0 .net "carryin", 0 0, L_0x7f93f4ea00f0; alias, 1 drivers +v0x1913e10_0 .net "carryout", 0 0, L_0x19a0060; alias, 1 drivers +v0x1913f20_0 .net "cout1", 0 0, L_0x199fda0; 1 drivers +v0x1913fe0_0 .net "cout2", 0 0, L_0x199ff00; 1 drivers +v0x19140a0_0 .net "subtract", 0 0, L_0x199f610; alias, 1 drivers +v0x1914140_0 .net "sum", 0 0, L_0x199fc40; 1 drivers +v0x1914290_0 .net "sumAB", 0 0, L_0x199fae0; 1 drivers +S_0x1914450 .scope generate, "genblk1[19]" "genblk1[19]" 2 47, 2 47 0, S_0x1830720; + .timescale 0 0; +P_0x1914610 .param/l "i" 0 2 47, +C4<010011>; +S_0x19146d0 .scope module, "addermid" "FullAdder1bit" 2 48, 2 8 0, S_0x1914450; + .timescale 0 0; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b0" + .port_info 4 /INPUT 1 "carryin" + .port_info 5 /INPUT 1 "subtract" +L_0x199f9c0/d .functor XOR 1, L_0x19a0d80, L_0x19a0060, C4<0>, C4<0>; +L_0x199f9c0 .delay 1 (20,20,20) L_0x199f9c0/d; +L_0x19a0540/d .functor XOR 1, L_0x19a0c60, L_0x199f9c0, C4<0>, C4<0>; +L_0x19a0540 .delay 1 (20,20,20) L_0x19a0540/d; +L_0x19a06a0/d .functor XOR 1, L_0x19a0540, L_0x7f93f4ea00f0, C4<0>, C4<0>; +L_0x19a06a0 .delay 1 (20,20,20) L_0x19a06a0/d; +L_0x19a0800/d .functor AND 1, L_0x19a0c60, L_0x199f9c0, C4<1>, C4<1>; +L_0x19a0800 .delay 1 (20,20,20) L_0x19a0800/d; +L_0x19a0960/d .functor AND 1, L_0x19a0540, L_0x7f93f4ea00f0, C4<1>, C4<1>; +L_0x19a0960 .delay 1 (20,20,20) L_0x19a0960/d; +L_0x19a0ac0/d .functor OR 1, L_0x19a0800, L_0x19a0960, C4<0>, C4<0>; +L_0x19a0ac0 .delay 1 (20,20,20) L_0x19a0ac0/d; +v0x1914940_0 .net "a", 0 0, L_0x19a0c60; 1 drivers +v0x1914a20_0 .net "b", 0 0, L_0x199f9c0; 1 drivers +v0x1914ae0_0 .net "b0", 0 0, L_0x19a0d80; 1 drivers +v0x1914b80_0 .net "carryin", 0 0, L_0x7f93f4ea00f0; alias, 1 drivers +v0x1914c20_0 .net "carryout", 0 0, L_0x19a0ac0; alias, 1 drivers +v0x1914d30_0 .net "cout1", 0 0, L_0x19a0800; 1 drivers +v0x1914df0_0 .net "cout2", 0 0, L_0x19a0960; 1 drivers +v0x1914eb0_0 .net "subtract", 0 0, L_0x19a0060; alias, 1 drivers +v0x1914f50_0 .net "sum", 0 0, L_0x19a06a0; 1 drivers +v0x1915080_0 .net "sumAB", 0 0, L_0x19a0540; 1 drivers +S_0x1915240 .scope generate, "genblk1[20]" "genblk1[20]" 2 47, 2 47 0, S_0x1830720; + .timescale 0 0; +P_0x1915400 .param/l "i" 0 2 47, +C4<010100>; +S_0x19154c0 .scope module, "addermid" "FullAdder1bit" 2 48, 2 8 0, S_0x1915240; + .timescale 0 0; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b0" + .port_info 4 /INPUT 1 "carryin" + .port_info 5 /INPUT 1 "subtract" +L_0x19a0410/d .functor XOR 1, L_0x19a17f0, L_0x19a0ac0, C4<0>, C4<0>; +L_0x19a0410 .delay 1 (20,20,20) L_0x19a0410/d; +L_0x19a0fb0/d .functor XOR 1, L_0x19a16d0, L_0x19a0410, C4<0>, C4<0>; +L_0x19a0fb0 .delay 1 (20,20,20) L_0x19a0fb0/d; +L_0x19a1110/d .functor XOR 1, L_0x19a0fb0, L_0x7f93f4ea00f0, C4<0>, C4<0>; +L_0x19a1110 .delay 1 (20,20,20) L_0x19a1110/d; +L_0x19a1270/d .functor AND 1, L_0x19a16d0, L_0x19a0410, C4<1>, C4<1>; +L_0x19a1270 .delay 1 (20,20,20) L_0x19a1270/d; +L_0x19a13d0/d .functor AND 1, L_0x19a0fb0, L_0x7f93f4ea00f0, C4<1>, C4<1>; +L_0x19a13d0 .delay 1 (20,20,20) L_0x19a13d0/d; +L_0x19a1530/d .functor OR 1, L_0x19a1270, L_0x19a13d0, C4<0>, C4<0>; +L_0x19a1530 .delay 1 (20,20,20) L_0x19a1530/d; +v0x1915730_0 .net "a", 0 0, L_0x19a16d0; 1 drivers +v0x1915810_0 .net "b", 0 0, L_0x19a0410; 1 drivers +v0x19158d0_0 .net "b0", 0 0, L_0x19a17f0; 1 drivers +v0x1915970_0 .net "carryin", 0 0, L_0x7f93f4ea00f0; alias, 1 drivers +v0x1915a10_0 .net "carryout", 0 0, L_0x19a1530; alias, 1 drivers +v0x1915b20_0 .net "cout1", 0 0, L_0x19a1270; 1 drivers +v0x1915be0_0 .net "cout2", 0 0, L_0x19a13d0; 1 drivers +v0x1915ca0_0 .net "subtract", 0 0, L_0x19a0ac0; alias, 1 drivers +v0x1915d40_0 .net "sum", 0 0, L_0x19a1110; 1 drivers +v0x1915e70_0 .net "sumAB", 0 0, L_0x19a0fb0; 1 drivers +S_0x1916030 .scope generate, "genblk1[21]" "genblk1[21]" 2 47, 2 47 0, S_0x1830720; + .timescale 0 0; +P_0x19161f0 .param/l "i" 0 2 47, +C4<010101>; +S_0x19162b0 .scope module, "addermid" "FullAdder1bit" 2 48, 2 8 0, S_0x1916030; + .timescale 0 0; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b0" + .port_info 4 /INPUT 1 "carryin" + .port_info 5 /INPUT 1 "subtract" +L_0x19a0e70/d .functor XOR 1, L_0x19a2270, L_0x19a1530, C4<0>, C4<0>; +L_0x19a0e70 .delay 1 (20,20,20) L_0x19a0e70/d; +L_0x19a1a30/d .functor XOR 1, L_0x19a2110, L_0x19a0e70, C4<0>, C4<0>; +L_0x19a1a30 .delay 1 (20,20,20) L_0x19a1a30/d; +L_0x19a1b90/d .functor XOR 1, L_0x19a1a30, L_0x7f93f4ea00f0, C4<0>, C4<0>; +L_0x19a1b90 .delay 1 (20,20,20) L_0x19a1b90/d; +L_0x19a1cf0/d .functor AND 1, L_0x19a2110, L_0x19a0e70, C4<1>, C4<1>; +L_0x19a1cf0 .delay 1 (20,20,20) L_0x19a1cf0/d; +L_0x19a1e50/d .functor AND 1, L_0x19a1a30, L_0x7f93f4ea00f0, C4<1>, C4<1>; +L_0x19a1e50 .delay 1 (20,20,20) L_0x19a1e50/d; +L_0x19a1fb0/d .functor OR 1, L_0x19a1cf0, L_0x19a1e50, C4<0>, C4<0>; +L_0x19a1fb0 .delay 1 (20,20,20) L_0x19a1fb0/d; +v0x1916520_0 .net "a", 0 0, L_0x19a2110; 1 drivers +v0x1916600_0 .net "b", 0 0, L_0x19a0e70; 1 drivers +v0x19166c0_0 .net "b0", 0 0, L_0x19a2270; 1 drivers +v0x1916760_0 .net "carryin", 0 0, L_0x7f93f4ea00f0; alias, 1 drivers +v0x1916800_0 .net "carryout", 0 0, L_0x19a1fb0; alias, 1 drivers +v0x1916910_0 .net "cout1", 0 0, L_0x19a1cf0; 1 drivers +v0x19169d0_0 .net "cout2", 0 0, L_0x19a1e50; 1 drivers +v0x1916a90_0 .net "subtract", 0 0, L_0x19a1530; alias, 1 drivers +v0x1916b30_0 .net "sum", 0 0, L_0x19a1b90; 1 drivers +v0x1916c60_0 .net "sumAB", 0 0, L_0x19a1a30; 1 drivers +S_0x1916e20 .scope generate, "genblk1[22]" "genblk1[22]" 2 47, 2 47 0, S_0x1830720; + .timescale 0 0; +P_0x1916fe0 .param/l "i" 0 2 47, +C4<010110>; +S_0x19170a0 .scope module, "addermid" "FullAdder1bit" 2 48, 2 8 0, S_0x1916e20; + .timescale 0 0; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b0" + .port_info 4 /INPUT 1 "carryin" + .port_info 5 /INPUT 1 "subtract" +L_0x19a18e0/d .functor XOR 1, L_0x19a2c60, L_0x19a1fb0, C4<0>, C4<0>; +L_0x19a18e0 .delay 1 (20,20,20) L_0x19a18e0/d; +L_0x19a2470/d .functor XOR 1, L_0x19a2b40, L_0x19a18e0, C4<0>, C4<0>; +L_0x19a2470 .delay 1 (20,20,20) L_0x19a2470/d; +L_0x19a2580/d .functor XOR 1, L_0x19a2470, L_0x7f93f4ea00f0, C4<0>, C4<0>; +L_0x19a2580 .delay 1 (20,20,20) L_0x19a2580/d; +L_0x19a26e0/d .functor AND 1, L_0x19a2b40, L_0x19a18e0, C4<1>, C4<1>; +L_0x19a26e0 .delay 1 (20,20,20) L_0x19a26e0/d; +L_0x19a2840/d .functor AND 1, L_0x19a2470, L_0x7f93f4ea00f0, C4<1>, C4<1>; +L_0x19a2840 .delay 1 (20,20,20) L_0x19a2840/d; +L_0x19a29a0/d .functor OR 1, L_0x19a26e0, L_0x19a2840, C4<0>, C4<0>; +L_0x19a29a0 .delay 1 (20,20,20) L_0x19a29a0/d; +v0x1917310_0 .net "a", 0 0, L_0x19a2b40; 1 drivers +v0x19173f0_0 .net "b", 0 0, L_0x19a18e0; 1 drivers +v0x19174b0_0 .net "b0", 0 0, L_0x19a2c60; 1 drivers +v0x1917550_0 .net "carryin", 0 0, L_0x7f93f4ea00f0; alias, 1 drivers +v0x19175f0_0 .net "carryout", 0 0, L_0x19a29a0; alias, 1 drivers +v0x1917700_0 .net "cout1", 0 0, L_0x19a26e0; 1 drivers +v0x19177c0_0 .net "cout2", 0 0, L_0x19a2840; 1 drivers +v0x1917880_0 .net "subtract", 0 0, L_0x19a1fb0; alias, 1 drivers +v0x1917920_0 .net "sum", 0 0, L_0x19a2580; 1 drivers +v0x1917a50_0 .net "sumAB", 0 0, L_0x19a2470; 1 drivers +S_0x1917c10 .scope generate, "genblk1[23]" "genblk1[23]" 2 47, 2 47 0, S_0x1830720; + .timescale 0 0; +P_0x1917dd0 .param/l "i" 0 2 47, +C4<010111>; +S_0x1917e90 .scope module, "addermid" "FullAdder1bit" 2 48, 2 8 0, S_0x1917c10; + .timescale 0 0; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b0" + .port_info 4 /INPUT 1 "carryin" + .port_info 5 /INPUT 1 "subtract" +L_0x19a2310/d .functor XOR 1, L_0x19a36b0, L_0x19a29a0, C4<0>, C4<0>; +L_0x19a2310 .delay 1 (20,20,20) L_0x19a2310/d; +L_0x19a2ec0/d .functor XOR 1, L_0x19a3590, L_0x19a2310, C4<0>, C4<0>; +L_0x19a2ec0 .delay 1 (20,20,20) L_0x19a2ec0/d; +L_0x19a2fd0/d .functor XOR 1, L_0x19a2ec0, L_0x7f93f4ea00f0, C4<0>, C4<0>; +L_0x19a2fd0 .delay 1 (20,20,20) L_0x19a2fd0/d; +L_0x19a3130/d .functor AND 1, L_0x19a3590, L_0x19a2310, C4<1>, C4<1>; +L_0x19a3130 .delay 1 (20,20,20) L_0x19a3130/d; +L_0x19a3290/d .functor AND 1, L_0x19a2ec0, L_0x7f93f4ea00f0, C4<1>, C4<1>; +L_0x19a3290 .delay 1 (20,20,20) L_0x19a3290/d; +L_0x19a33f0/d .functor OR 1, L_0x19a3130, L_0x19a3290, C4<0>, C4<0>; +L_0x19a33f0 .delay 1 (20,20,20) L_0x19a33f0/d; +v0x1918100_0 .net "a", 0 0, L_0x19a3590; 1 drivers +v0x19181e0_0 .net "b", 0 0, L_0x19a2310; 1 drivers +v0x19182a0_0 .net "b0", 0 0, L_0x19a36b0; 1 drivers +v0x1918370_0 .net "carryin", 0 0, L_0x7f93f4ea00f0; alias, 1 drivers +v0x1918410_0 .net "carryout", 0 0, L_0x19a33f0; alias, 1 drivers +v0x1918520_0 .net "cout1", 0 0, L_0x19a3130; 1 drivers +v0x19185e0_0 .net "cout2", 0 0, L_0x19a3290; 1 drivers +v0x19186a0_0 .net "subtract", 0 0, L_0x19a29a0; alias, 1 drivers +v0x1918740_0 .net "sum", 0 0, L_0x19a2fd0; 1 drivers +v0x1918870_0 .net "sumAB", 0 0, L_0x19a2ec0; 1 drivers +S_0x1918a30 .scope generate, "genblk1[24]" "genblk1[24]" 2 47, 2 47 0, S_0x1830720; + .timescale 0 0; +P_0x1918bf0 .param/l "i" 0 2 47, +C4<011000>; +S_0x1918cb0 .scope module, "addermid" "FullAdder1bit" 2 48, 2 8 0, S_0x1918a30; + .timescale 0 0; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b0" + .port_info 4 /INPUT 1 "carryin" + .port_info 5 /INPUT 1 "subtract" +L_0x19a2d50/d .functor XOR 1, L_0x19a4110, L_0x19a33f0, C4<0>, C4<0>; +L_0x19a2d50 .delay 1 (20,20,20) L_0x19a2d50/d; +L_0x19a3920/d .functor XOR 1, L_0x19a3ff0, L_0x19a2d50, C4<0>, C4<0>; +L_0x19a3920 .delay 1 (20,20,20) L_0x19a3920/d; +L_0x19a3a30/d .functor XOR 1, L_0x19a3920, L_0x7f93f4ea00f0, C4<0>, C4<0>; +L_0x19a3a30 .delay 1 (20,20,20) L_0x19a3a30/d; +L_0x19a3b90/d .functor AND 1, L_0x19a3ff0, L_0x19a2d50, C4<1>, C4<1>; +L_0x19a3b90 .delay 1 (20,20,20) L_0x19a3b90/d; +L_0x19a3cf0/d .functor AND 1, L_0x19a3920, L_0x7f93f4ea00f0, C4<1>, C4<1>; +L_0x19a3cf0 .delay 1 (20,20,20) L_0x19a3cf0/d; +L_0x19a3e50/d .functor OR 1, L_0x19a3b90, L_0x19a3cf0, C4<0>, C4<0>; +L_0x19a3e50 .delay 1 (20,20,20) L_0x19a3e50/d; +v0x1918f20_0 .net "a", 0 0, L_0x19a3ff0; 1 drivers +v0x1919000_0 .net "b", 0 0, L_0x19a2d50; 1 drivers +v0x19190c0_0 .net "b0", 0 0, L_0x19a4110; 1 drivers +v0x1919190_0 .net "carryin", 0 0, L_0x7f93f4ea00f0; alias, 1 drivers +v0x1919230_0 .net "carryout", 0 0, L_0x19a3e50; alias, 1 drivers +v0x1919340_0 .net "cout1", 0 0, L_0x19a3b90; 1 drivers +v0x1919400_0 .net "cout2", 0 0, L_0x19a3cf0; 1 drivers +v0x19194c0_0 .net "subtract", 0 0, L_0x19a33f0; alias, 1 drivers +v0x1919560_0 .net "sum", 0 0, L_0x19a3a30; 1 drivers +v0x1919690_0 .net "sumAB", 0 0, L_0x19a3920; 1 drivers +S_0x1919850 .scope generate, "genblk1[25]" "genblk1[25]" 2 47, 2 47 0, S_0x1830720; + .timescale 0 0; +P_0x1919a10 .param/l "i" 0 2 47, +C4<011001>; +S_0x1919ad0 .scope module, "addermid" "FullAdder1bit" 2 48, 2 8 0, S_0x1919850; + .timescale 0 0; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b0" + .port_info 4 /INPUT 1 "carryin" + .port_info 5 /INPUT 1 "subtract" +L_0x19a37a0/d .functor XOR 1, L_0x19a4b80, L_0x19a3e50, C4<0>, C4<0>; +L_0x19a37a0 .delay 1 (20,20,20) L_0x19a37a0/d; +L_0x19a4390/d .functor XOR 1, L_0x19a4a60, L_0x19a37a0, C4<0>, C4<0>; +L_0x19a4390 .delay 1 (20,20,20) L_0x19a4390/d; +L_0x19a44a0/d .functor XOR 1, L_0x19a4390, L_0x7f93f4ea00f0, C4<0>, C4<0>; +L_0x19a44a0 .delay 1 (20,20,20) L_0x19a44a0/d; +L_0x19a4600/d .functor AND 1, L_0x19a4a60, L_0x19a37a0, C4<1>, C4<1>; +L_0x19a4600 .delay 1 (20,20,20) L_0x19a4600/d; +L_0x19a4760/d .functor AND 1, L_0x19a4390, L_0x7f93f4ea00f0, C4<1>, C4<1>; +L_0x19a4760 .delay 1 (20,20,20) L_0x19a4760/d; +L_0x19a48c0/d .functor OR 1, L_0x19a4600, L_0x19a4760, C4<0>, C4<0>; +L_0x19a48c0 .delay 1 (20,20,20) L_0x19a48c0/d; +v0x1919d40_0 .net "a", 0 0, L_0x19a4a60; 1 drivers +v0x1919e20_0 .net "b", 0 0, L_0x19a37a0; 1 drivers +v0x1919ee0_0 .net "b0", 0 0, L_0x19a4b80; 1 drivers +v0x1919fb0_0 .net "carryin", 0 0, L_0x7f93f4ea00f0; alias, 1 drivers +v0x191a050_0 .net "carryout", 0 0, L_0x19a48c0; alias, 1 drivers +v0x191a160_0 .net "cout1", 0 0, L_0x19a4600; 1 drivers +v0x191a220_0 .net "cout2", 0 0, L_0x19a4760; 1 drivers +v0x191a2e0_0 .net "subtract", 0 0, L_0x19a3e50; alias, 1 drivers +v0x191a380_0 .net "sum", 0 0, L_0x19a44a0; 1 drivers +v0x191a4b0_0 .net "sumAB", 0 0, L_0x19a4390; 1 drivers +S_0x191a670 .scope generate, "genblk1[26]" "genblk1[26]" 2 47, 2 47 0, S_0x1830720; + .timescale 0 0; +P_0x191a830 .param/l "i" 0 2 47, +C4<011010>; +S_0x191a8f0 .scope module, "addermid" "FullAdder1bit" 2 48, 2 8 0, S_0x191a670; + .timescale 0 0; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b0" + .port_info 4 /INPUT 1 "carryin" + .port_info 5 /INPUT 1 "subtract" +L_0x19a4200/d .functor XOR 1, L_0x19a5600, L_0x19a48c0, C4<0>, C4<0>; +L_0x19a4200 .delay 1 (20,20,20) L_0x19a4200/d; +L_0x19a4e10/d .functor XOR 1, L_0x19a54a0, L_0x19a4200, C4<0>, C4<0>; +L_0x19a4e10 .delay 1 (20,20,20) L_0x19a4e10/d; +L_0x19a4f20/d .functor XOR 1, L_0x19a4e10, L_0x7f93f4ea00f0, C4<0>, C4<0>; +L_0x19a4f20 .delay 1 (20,20,20) L_0x19a4f20/d; +L_0x19a5080/d .functor AND 1, L_0x19a54a0, L_0x19a4200, C4<1>, C4<1>; +L_0x19a5080 .delay 1 (20,20,20) L_0x19a5080/d; +L_0x19a51e0/d .functor AND 1, L_0x19a4e10, L_0x7f93f4ea00f0, C4<1>, C4<1>; +L_0x19a51e0 .delay 1 (20,20,20) L_0x19a51e0/d; +L_0x19a5340/d .functor OR 1, L_0x19a5080, L_0x19a51e0, C4<0>, C4<0>; +L_0x19a5340 .delay 1 (20,20,20) L_0x19a5340/d; +v0x191ab60_0 .net "a", 0 0, L_0x19a54a0; 1 drivers +v0x191ac40_0 .net "b", 0 0, L_0x19a4200; 1 drivers +v0x191ad00_0 .net "b0", 0 0, L_0x19a5600; 1 drivers +v0x191add0_0 .net "carryin", 0 0, L_0x7f93f4ea00f0; alias, 1 drivers +v0x191ae70_0 .net "carryout", 0 0, L_0x19a5340; alias, 1 drivers +v0x191af80_0 .net "cout1", 0 0, L_0x19a5080; 1 drivers +v0x191b040_0 .net "cout2", 0 0, L_0x19a51e0; 1 drivers +v0x191b100_0 .net "subtract", 0 0, L_0x19a48c0; alias, 1 drivers +v0x191b1a0_0 .net "sum", 0 0, L_0x19a4f20; 1 drivers +v0x191b2d0_0 .net "sumAB", 0 0, L_0x19a4e10; 1 drivers +S_0x191b490 .scope generate, "genblk1[27]" "genblk1[27]" 2 47, 2 47 0, S_0x1830720; + .timescale 0 0; +P_0x191b650 .param/l "i" 0 2 47, +C4<011011>; +S_0x191b710 .scope module, "addermid" "FullAdder1bit" 2 48, 2 8 0, S_0x191b490; + .timescale 0 0; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b0" + .port_info 4 /INPUT 1 "carryin" + .port_info 5 /INPUT 1 "subtract" +L_0x19a4c70/d .functor XOR 1, L_0x19a5ff0, L_0x19a5340, C4<0>, C4<0>; +L_0x19a4c70 .delay 1 (20,20,20) L_0x19a4c70/d; +L_0x19a5850/d .functor XOR 1, L_0x19a5ed0, L_0x19a4c70, C4<0>, C4<0>; +L_0x19a5850 .delay 1 (20,20,20) L_0x19a5850/d; +L_0x19a5910/d .functor XOR 1, L_0x19a5850, L_0x7f93f4ea00f0, C4<0>, C4<0>; +L_0x19a5910 .delay 1 (20,20,20) L_0x19a5910/d; +L_0x19a5a70/d .functor AND 1, L_0x19a5ed0, L_0x19a4c70, C4<1>, C4<1>; +L_0x19a5a70 .delay 1 (20,20,20) L_0x19a5a70/d; +L_0x19a5bd0/d .functor AND 1, L_0x19a5850, L_0x7f93f4ea00f0, C4<1>, C4<1>; +L_0x19a5bd0 .delay 1 (20,20,20) L_0x19a5bd0/d; +L_0x19a5d30/d .functor OR 1, L_0x19a5a70, L_0x19a5bd0, C4<0>, C4<0>; +L_0x19a5d30 .delay 1 (20,20,20) L_0x19a5d30/d; +v0x191b980_0 .net "a", 0 0, L_0x19a5ed0; 1 drivers +v0x191ba60_0 .net "b", 0 0, L_0x19a4c70; 1 drivers +v0x191bb20_0 .net "b0", 0 0, L_0x19a5ff0; 1 drivers +v0x191bbf0_0 .net "carryin", 0 0, L_0x7f93f4ea00f0; alias, 1 drivers +v0x191bc90_0 .net "carryout", 0 0, L_0x19a5d30; alias, 1 drivers +v0x191bda0_0 .net "cout1", 0 0, L_0x19a5a70; 1 drivers +v0x191be60_0 .net "cout2", 0 0, L_0x19a5bd0; 1 drivers +v0x191bf20_0 .net "subtract", 0 0, L_0x19a5340; alias, 1 drivers +v0x191bfc0_0 .net "sum", 0 0, L_0x19a5910; 1 drivers +v0x191c0f0_0 .net "sumAB", 0 0, L_0x19a5850; 1 drivers +S_0x191c2b0 .scope generate, "genblk1[28]" "genblk1[28]" 2 47, 2 47 0, S_0x1830720; + .timescale 0 0; +P_0x191c470 .param/l "i" 0 2 47, +C4<011100>; +S_0x191c530 .scope module, "addermid" "FullAdder1bit" 2 48, 2 8 0, S_0x191c2b0; + .timescale 0 0; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b0" + .port_info 4 /INPUT 1 "carryin" + .port_info 5 /INPUT 1 "subtract" +L_0x19a56a0/d .functor XOR 1, L_0x19a6a40, L_0x19a5d30, C4<0>, C4<0>; +L_0x19a56a0 .delay 1 (20,20,20) L_0x19a56a0/d; +L_0x19a62a0/d .functor XOR 1, L_0x19a6920, L_0x19a56a0, C4<0>, C4<0>; +L_0x19a62a0 .delay 1 (20,20,20) L_0x19a62a0/d; +L_0x19a6360/d .functor XOR 1, L_0x19a62a0, L_0x7f93f4ea00f0, C4<0>, C4<0>; +L_0x19a6360 .delay 1 (20,20,20) L_0x19a6360/d; +L_0x19a64c0/d .functor AND 1, L_0x19a6920, L_0x19a56a0, C4<1>, C4<1>; +L_0x19a64c0 .delay 1 (20,20,20) L_0x19a64c0/d; +L_0x19a6620/d .functor AND 1, L_0x19a62a0, L_0x7f93f4ea00f0, C4<1>, C4<1>; +L_0x19a6620 .delay 1 (20,20,20) L_0x19a6620/d; +L_0x19a6780/d .functor OR 1, L_0x19a64c0, L_0x19a6620, C4<0>, C4<0>; +L_0x19a6780 .delay 1 (20,20,20) L_0x19a6780/d; +v0x191c7a0_0 .net "a", 0 0, L_0x19a6920; 1 drivers +v0x191c880_0 .net "b", 0 0, L_0x19a56a0; 1 drivers +v0x191c940_0 .net "b0", 0 0, L_0x19a6a40; 1 drivers +v0x191ca10_0 .net "carryin", 0 0, L_0x7f93f4ea00f0; alias, 1 drivers +v0x191cab0_0 .net "carryout", 0 0, L_0x19a6780; alias, 1 drivers +v0x191cbc0_0 .net "cout1", 0 0, L_0x19a64c0; 1 drivers +v0x191cc80_0 .net "cout2", 0 0, L_0x19a6620; 1 drivers +v0x191cd40_0 .net "subtract", 0 0, L_0x19a5d30; alias, 1 drivers +v0x191cde0_0 .net "sum", 0 0, L_0x19a6360; 1 drivers +v0x191cf10_0 .net "sumAB", 0 0, L_0x19a62a0; 1 drivers +S_0x191d0d0 .scope generate, "genblk1[29]" "genblk1[29]" 2 47, 2 47 0, S_0x1830720; + .timescale 0 0; +P_0x191d290 .param/l "i" 0 2 47, +C4<011101>; +S_0x191d350 .scope module, "addermid" "FullAdder1bit" 2 48, 2 8 0, S_0x191d0d0; + .timescale 0 0; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b0" + .port_info 4 /INPUT 1 "carryin" + .port_info 5 /INPUT 1 "subtract" +L_0x19a60e0/d .functor XOR 1, L_0x19a7480, L_0x19a6780, C4<0>, C4<0>; +L_0x19a60e0 .delay 1 (20,20,20) L_0x19a60e0/d; +L_0x19a6230/d .functor XOR 1, L_0x19a7360, L_0x19a60e0, C4<0>, C4<0>; +L_0x19a6230 .delay 1 (20,20,20) L_0x19a6230/d; +L_0x19a6da0/d .functor XOR 1, L_0x19a6230, L_0x7f93f4ea00f0, C4<0>, C4<0>; +L_0x19a6da0 .delay 1 (20,20,20) L_0x19a6da0/d; +L_0x19a6f00/d .functor AND 1, L_0x19a7360, L_0x19a60e0, C4<1>, C4<1>; +L_0x19a6f00 .delay 1 (20,20,20) L_0x19a6f00/d; +L_0x19a7060/d .functor AND 1, L_0x19a6230, L_0x7f93f4ea00f0, C4<1>, C4<1>; +L_0x19a7060 .delay 1 (20,20,20) L_0x19a7060/d; +L_0x19a71c0/d .functor OR 1, L_0x19a6f00, L_0x19a7060, C4<0>, C4<0>; +L_0x19a71c0 .delay 1 (20,20,20) L_0x19a71c0/d; +v0x191d5c0_0 .net "a", 0 0, L_0x19a7360; 1 drivers +v0x191d6a0_0 .net "b", 0 0, L_0x19a60e0; 1 drivers +v0x191d760_0 .net "b0", 0 0, L_0x19a7480; 1 drivers +v0x191d830_0 .net "carryin", 0 0, L_0x7f93f4ea00f0; alias, 1 drivers +v0x191d8d0_0 .net "carryout", 0 0, L_0x19a71c0; alias, 1 drivers +v0x191d9e0_0 .net "cout1", 0 0, L_0x19a6f00; 1 drivers +v0x191daa0_0 .net "cout2", 0 0, L_0x19a7060; 1 drivers +v0x191db60_0 .net "subtract", 0 0, L_0x19a6780; alias, 1 drivers +v0x191dc00_0 .net "sum", 0 0, L_0x19a6da0; 1 drivers +v0x191dd30_0 .net "sumAB", 0 0, L_0x19a6230; 1 drivers +S_0x191def0 .scope generate, "genblk1[30]" "genblk1[30]" 2 47, 2 47 0, S_0x1830720; + .timescale 0 0; +P_0x191e0b0 .param/l "i" 0 2 47, +C4<011110>; +S_0x191e170 .scope module, "addermid" "FullAdder1bit" 2 48, 2 8 0, S_0x191def0; + .timescale 0 0; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b0" + .port_info 4 /INPUT 1 "carryin" + .port_info 5 /INPUT 1 "subtract" +L_0x19a6b30/d .functor XOR 1, L_0x19a7f20, L_0x19a71c0, C4<0>, C4<0>; +L_0x19a6b30 .delay 1 (20,20,20) L_0x19a6b30/d; +L_0x19a6c80/d .functor XOR 1, L_0x19a7e00, L_0x19a6b30, C4<0>, C4<0>; +L_0x19a6c80 .delay 1 (20,20,20) L_0x19a6c80/d; +L_0x19a77f0/d .functor XOR 1, L_0x19a6c80, L_0x7f93f4ea00f0, C4<0>, C4<0>; +L_0x19a77f0 .delay 1 (20,20,20) L_0x19a77f0/d; +L_0x19a7950/d .functor AND 1, L_0x19a7e00, L_0x19a6b30, C4<1>, C4<1>; +L_0x19a7950 .delay 1 (20,20,20) L_0x19a7950/d; +L_0x19a7ab0/d .functor AND 1, L_0x19a6c80, L_0x7f93f4ea00f0, C4<1>, C4<1>; +L_0x19a7ab0 .delay 1 (20,20,20) L_0x19a7ab0/d; +L_0x19a7c10/d .functor OR 1, L_0x19a7950, L_0x19a7ab0, C4<0>, C4<0>; +L_0x19a7c10 .delay 1 (20,20,20) L_0x19a7c10/d; +v0x191e3e0_0 .net "a", 0 0, L_0x19a7e00; 1 drivers +v0x191e4c0_0 .net "b", 0 0, L_0x19a6b30; 1 drivers +v0x191e580_0 .net "b0", 0 0, L_0x19a7f20; 1 drivers +v0x191e650_0 .net "carryin", 0 0, L_0x7f93f4ea00f0; alias, 1 drivers +v0x19106d0_0 .net "carryout", 0 0, L_0x19a7c10; alias, 1 drivers +v0x19107e0_0 .net "cout1", 0 0, L_0x19a7950; 1 drivers +v0x191eb00_0 .net "cout2", 0 0, L_0x19a7ab0; 1 drivers +v0x191eba0_0 .net "subtract", 0 0, L_0x19a71c0; alias, 1 drivers +v0x191ec40_0 .net "sum", 0 0, L_0x19a77f0; 1 drivers +v0x191ed70_0 .net "sumAB", 0 0, L_0x19a6c80; 1 drivers +S_0x191eeb0 .scope generate, "genblk2[0]" "genblk2[0]" 2 57, 2 57 0, S_0x1830720; + .timescale 0 0; +P_0x1910fd0 .param/l "j" 0 2 57, +C4<00>; +L_0x19a7570/d .functor NOR 1, L_0x19aeb00, L_0x19a7630, C4<0>, C4<0>; +L_0x19a7570 .delay 1 (10,10,10) L_0x19a7570/d; +v0x191f280_0 .net *"_s3", 0 0, L_0x19a7630; 1 drivers +S_0x191f320 .scope generate, "genblk2[1]" "genblk2[1]" 2 57, 2 57 0, S_0x1830720; + .timescale 0 0; +P_0x191f530 .param/l "j" 0 2 57, +C4<01>; +L_0x19a82a0/d .functor NOR 1, L_0x19a7570, L_0x19a83b0, C4<0>, C4<0>; +L_0x19a82a0 .delay 1 (10,10,10) L_0x19a82a0/d; +v0x191f5f0_0 .net *"_s3", 0 0, L_0x19a83b0; 1 drivers +S_0x191f6d0 .scope generate, "genblk2[2]" "genblk2[2]" 2 57, 2 57 0, S_0x1830720; + .timescale 0 0; +P_0x191f8e0 .param/l "j" 0 2 57, +C4<010>; +L_0x19a8010/d .functor NOR 1, L_0x19a82a0, L_0x19a8710, C4<0>, C4<0>; +L_0x19a8010 .delay 1 (10,10,10) L_0x19a8010/d; +v0x191f9a0_0 .net *"_s3", 0 0, L_0x19a8710; 1 drivers +S_0x191fa80 .scope generate, "genblk2[3]" "genblk2[3]" 2 57, 2 57 0, S_0x1830720; + .timescale 0 0; +P_0x191fc90 .param/l "j" 0 2 57, +C4<011>; +L_0x19a8840/d .functor NOR 1, L_0x19a8010, L_0x19a8900, C4<0>, C4<0>; +L_0x19a8840 .delay 1 (10,10,10) L_0x19a8840/d; +v0x191fd50_0 .net *"_s3", 0 0, L_0x19a8900; 1 drivers +S_0x191fe30 .scope generate, "genblk2[4]" "genblk2[4]" 2 57, 2 57 0, S_0x1830720; + .timescale 0 0; +P_0x1920040 .param/l "j" 0 2 57, +C4<0100>; +L_0x19a8510/d .functor NOR 1, L_0x19a8840, L_0x19a8670, C4<0>, C4<0>; +L_0x19a8510 .delay 1 (10,10,10) L_0x19a8510/d; +v0x1920100_0 .net *"_s3", 0 0, L_0x19a8670; 1 drivers +S_0x19201e0 .scope generate, "genblk2[5]" "genblk2[5]" 2 57, 2 57 0, S_0x1830720; + .timescale 0 0; +P_0x19203f0 .param/l "j" 0 2 57, +C4<0101>; +L_0x19a8cc0/d .functor NOR 1, L_0x19a8510, L_0x19a8dd0, C4<0>, C4<0>; +L_0x19a8cc0 .delay 1 (10,10,10) L_0x19a8cc0/d; +v0x19204b0_0 .net *"_s3", 0 0, L_0x19a8dd0; 1 drivers +S_0x1920590 .scope generate, "genblk2[6]" "genblk2[6]" 2 57, 2 57 0, S_0x1830720; + .timescale 0 0; +P_0x19207a0 .param/l "j" 0 2 57, +C4<0110>; +L_0x19a8a60/d .functor NOR 1, L_0x19a8cc0, L_0x19a8bc0, C4<0>, C4<0>; +L_0x19a8a60 .delay 1 (10,10,10) L_0x19a8a60/d; +v0x1920860_0 .net *"_s3", 0 0, L_0x19a8bc0; 1 drivers +S_0x1920940 .scope generate, "genblk2[7]" "genblk2[7]" 2 57, 2 57 0, S_0x1830720; + .timescale 0 0; +P_0x1920b50 .param/l "j" 0 2 57, +C4<0111>; +L_0x19a87b0/d .functor NOR 1, L_0x19a8a60, L_0x19a9350, C4<0>, C4<0>; +L_0x19a87b0 .delay 1 (10,10,10) L_0x19a87b0/d; +v0x1920c10_0 .net *"_s3", 0 0, L_0x19a9350; 1 drivers +S_0x1920cf0 .scope generate, "genblk2[8]" "genblk2[8]" 2 57, 2 57 0, S_0x1830720; + .timescale 0 0; +P_0x1920f00 .param/l "j" 0 2 57, +C4<01000>; +L_0x19a8f30/d .functor NOR 1, L_0x19a87b0, L_0x19a9040, C4<0>, C4<0>; +L_0x19a8f30 .delay 1 (10,10,10) L_0x19a8f30/d; +v0x1920fc0_0 .net *"_s3", 0 0, L_0x19a9040; 1 drivers +S_0x19210a0 .scope generate, "genblk2[9]" "genblk2[9]" 2 57, 2 57 0, S_0x1830720; + .timescale 0 0; +P_0x19212b0 .param/l "j" 0 2 57, +C4<01001>; +L_0x19a9730/d .functor NOR 1, L_0x19a8f30, L_0x19a9840, C4<0>, C4<0>; +L_0x19a9730 .delay 1 (10,10,10) L_0x19a9730/d; +v0x1921370_0 .net *"_s3", 0 0, L_0x19a9840; 1 drivers +S_0x1921450 .scope generate, "genblk2[10]" "genblk2[10]" 2 57, 2 57 0, S_0x1830720; + .timescale 0 0; +P_0x1921660 .param/l "j" 0 2 57, +C4<01010>; +L_0x19a94b0/d .functor NOR 1, L_0x19a9730, L_0x19a95c0, C4<0>, C4<0>; +L_0x19a94b0 .delay 1 (10,10,10) L_0x19a94b0/d; +v0x1921720_0 .net *"_s3", 0 0, L_0x19a95c0; 1 drivers +S_0x1921800 .scope generate, "genblk2[11]" "genblk2[11]" 2 57, 2 57 0, S_0x1830720; + .timescale 0 0; +P_0x1921a10 .param/l "j" 0 2 57, +C4<01011>; +L_0x19a9c30/d .functor NOR 1, L_0x19a94b0, L_0x19a9d40, C4<0>, C4<0>; +L_0x19a9c30 .delay 1 (10,10,10) L_0x19a9c30/d; +v0x1921ad0_0 .net *"_s3", 0 0, L_0x19a9d40; 1 drivers +S_0x1921bb0 .scope generate, "genblk2[12]" "genblk2[12]" 2 57, 2 57 0, S_0x1830720; + .timescale 0 0; +P_0x1921dc0 .param/l "j" 0 2 57, +C4<01100>; +L_0x19a99a0/d .functor NOR 1, L_0x19a9c30, L_0x19a9ab0, C4<0>, C4<0>; +L_0x19a99a0 .delay 1 (10,10,10) L_0x19a99a0/d; +v0x1921e80_0 .net *"_s3", 0 0, L_0x19a9ab0; 1 drivers +S_0x1921f60 .scope generate, "genblk2[13]" "genblk2[13]" 2 57, 2 57 0, S_0x1830720; + .timescale 0 0; +P_0x1922170 .param/l "j" 0 2 57, +C4<01101>; +L_0x19aa140/d .functor NOR 1, L_0x19a99a0, L_0x19aa250, C4<0>, C4<0>; +L_0x19aa140 .delay 1 (10,10,10) L_0x19aa140/d; +v0x1922230_0 .net *"_s3", 0 0, L_0x19aa250; 1 drivers +S_0x1922310 .scope generate, "genblk2[14]" "genblk2[14]" 2 57, 2 57 0, S_0x1830720; + .timescale 0 0; +P_0x1922520 .param/l "j" 0 2 57, +C4<01110>; +L_0x19a9ea0/d .functor NOR 1, L_0x19aa140, L_0x19a9fb0, C4<0>, C4<0>; +L_0x19a9ea0 .delay 1 (10,10,10) L_0x19a9ea0/d; +v0x19225e0_0 .net *"_s3", 0 0, L_0x19a9fb0; 1 drivers +S_0x19226c0 .scope generate, "genblk2[15]" "genblk2[15]" 2 57, 2 57 0, S_0x1830720; + .timescale 0 0; +P_0x19228d0 .param/l "j" 0 2 57, +C4<01111>; +L_0x19a91a0/d .functor NOR 1, L_0x19a9ea0, L_0x19aa870, C4<0>, C4<0>; +L_0x19a91a0 .delay 1 (10,10,10) L_0x19a91a0/d; +v0x1922990_0 .net *"_s3", 0 0, L_0x19aa870; 1 drivers +S_0x1922a70 .scope generate, "genblk2[16]" "genblk2[16]" 2 57, 2 57 0, S_0x1830720; + .timescale 0 0; +P_0x1922c80 .param/l "j" 0 2 57, +C4<010000>; +L_0x19aa3b0/d .functor NOR 1, L_0x19a91a0, L_0x19aa4c0, C4<0>, C4<0>; +L_0x19aa3b0 .delay 1 (10,10,10) L_0x19aa3b0/d; +v0x1922d40_0 .net *"_s3", 0 0, L_0x19aa4c0; 1 drivers +S_0x1922e20 .scope generate, "genblk2[17]" "genblk2[17]" 2 57, 2 57 0, S_0x1830720; + .timescale 0 0; +P_0x1923030 .param/l "j" 0 2 57, +C4<010001>; +L_0x19aac20/d .functor NOR 1, L_0x19aa3b0, L_0x19aace0, C4<0>, C4<0>; +L_0x19aac20 .delay 1 (10,10,10) L_0x19aac20/d; +v0x19230f0_0 .net *"_s3", 0 0, L_0x19aace0; 1 drivers +S_0x19231d0 .scope generate, "genblk2[18]" "genblk2[18]" 2 57, 2 57 0, S_0x1830720; + .timescale 0 0; +P_0x19233e0 .param/l "j" 0 2 57, +C4<010010>; +L_0x19aa960/d .functor NOR 1, L_0x19aac20, L_0x19aaa70, C4<0>, C4<0>; +L_0x19aa960 .delay 1 (10,10,10) L_0x19aa960/d; +v0x19234a0_0 .net *"_s3", 0 0, L_0x19aaa70; 1 drivers +S_0x1923580 .scope generate, "genblk2[19]" "genblk2[19]" 2 57, 2 57 0, S_0x1830720; + .timescale 0 0; +P_0x1923790 .param/l "j" 0 2 57, +C4<010011>; +L_0x19ab0c0/d .functor NOR 1, L_0x19aa960, L_0x19ab1d0, C4<0>, C4<0>; +L_0x19ab0c0 .delay 1 (10,10,10) L_0x19ab0c0/d; +v0x1923850_0 .net *"_s3", 0 0, L_0x19ab1d0; 1 drivers +S_0x1923930 .scope generate, "genblk2[20]" "genblk2[20]" 2 57, 2 57 0, S_0x1830720; + .timescale 0 0; +P_0x1923b40 .param/l "j" 0 2 57, +C4<010100>; +L_0x19aae40/d .functor NOR 1, L_0x19ab0c0, L_0x19aaf50, C4<0>, C4<0>; +L_0x19aae40 .delay 1 (10,10,10) L_0x19aae40/d; +v0x1923c00_0 .net *"_s3", 0 0, L_0x19aaf50; 1 drivers +S_0x1923ce0 .scope generate, "genblk2[21]" "genblk2[21]" 2 57, 2 57 0, S_0x1830720; + .timescale 0 0; +P_0x1923ef0 .param/l "j" 0 2 57, +C4<010101>; +L_0x19ab5c0/d .functor NOR 1, L_0x19aae40, L_0x19ab6d0, C4<0>, C4<0>; +L_0x19ab5c0 .delay 1 (10,10,10) L_0x19ab5c0/d; +v0x1923fb0_0 .net *"_s3", 0 0, L_0x19ab6d0; 1 drivers +S_0x1924090 .scope generate, "genblk2[22]" "genblk2[22]" 2 57, 2 57 0, S_0x1830720; + .timescale 0 0; +P_0x19242a0 .param/l "j" 0 2 57, +C4<010110>; +L_0x19ab330/d .functor NOR 1, L_0x19ab5c0, L_0x19ab440, C4<0>, C4<0>; +L_0x19ab330 .delay 1 (10,10,10) L_0x19ab330/d; +v0x1924360_0 .net *"_s3", 0 0, L_0x19ab440; 1 drivers +S_0x1924440 .scope generate, "genblk2[23]" "genblk2[23]" 2 57, 2 57 0, S_0x1830720; + .timescale 0 0; +P_0x1924650 .param/l "j" 0 2 57, +C4<010111>; +L_0x19abad0/d .functor NOR 1, L_0x19ab330, L_0x19abbe0, C4<0>, C4<0>; +L_0x19abad0 .delay 1 (10,10,10) L_0x19abad0/d; +v0x1924710_0 .net *"_s3", 0 0, L_0x19abbe0; 1 drivers +S_0x19247f0 .scope generate, "genblk2[24]" "genblk2[24]" 2 57, 2 57 0, S_0x1830720; + .timescale 0 0; +P_0x1924a00 .param/l "j" 0 2 57, +C4<011000>; +L_0x19ab830/d .functor NOR 1, L_0x19abad0, L_0x19ab940, C4<0>, C4<0>; +L_0x19ab830 .delay 1 (10,10,10) L_0x19ab830/d; +v0x1924ac0_0 .net *"_s3", 0 0, L_0x19ab940; 1 drivers +S_0x1924ba0 .scope generate, "genblk2[25]" "genblk2[25]" 2 57, 2 57 0, S_0x1830720; + .timescale 0 0; +P_0x1924db0 .param/l "j" 0 2 57, +C4<011001>; +L_0x19abff0/d .functor NOR 1, L_0x19ab830, L_0x19ac100, C4<0>, C4<0>; +L_0x19abff0 .delay 1 (10,10,10) L_0x19abff0/d; +v0x1924e70_0 .net *"_s3", 0 0, L_0x19ac100; 1 drivers +S_0x1924f50 .scope generate, "genblk2[26]" "genblk2[26]" 2 57, 2 57 0, S_0x1830720; + .timescale 0 0; +P_0x1925160 .param/l "j" 0 2 57, +C4<011010>; +L_0x19abd40/d .functor NOR 1, L_0x19abff0, L_0x19abe50, C4<0>, C4<0>; +L_0x19abd40 .delay 1 (10,10,10) L_0x19abd40/d; +v0x1925220_0 .net *"_s3", 0 0, L_0x19abe50; 1 drivers +S_0x1925300 .scope generate, "genblk2[27]" "genblk2[27]" 2 57, 2 57 0, S_0x1830720; + .timescale 0 0; +P_0x1925510 .param/l "j" 0 2 57, +C4<011011>; +L_0x19ac520/d .functor NOR 1, L_0x19abd40, L_0x19ac630, C4<0>, C4<0>; +L_0x19ac520 .delay 1 (10,10,10) L_0x19ac520/d; +v0x19255d0_0 .net *"_s3", 0 0, L_0x19ac630; 1 drivers +S_0x19256b0 .scope generate, "genblk2[28]" "genblk2[28]" 2 57, 2 57 0, S_0x1830720; + .timescale 0 0; +P_0x19258c0 .param/l "j" 0 2 57, +C4<011100>; +L_0x19ac260/d .functor NOR 1, L_0x19ac520, L_0x19ac370, C4<0>, C4<0>; +L_0x19ac260 .delay 1 (10,10,10) L_0x19ac260/d; +v0x1925980_0 .net *"_s3", 0 0, L_0x19ac370; 1 drivers +S_0x1927f50 .scope module, "dut3" "alu32bitandn" 2 260, 2 118 0, S_0x17ef170; + .timescale 0 0; + .port_info 0 /OUTPUT 32 "result" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /OUTPUT 1 "zero" + .port_info 3 /OUTPUT 1 "overflow" + .port_info 4 /INPUT 32 "operandA" + .port_info 5 /INPUT 32 "operandB" + .port_info 6 /INPUT 1 "othercontrolsignal" +v0x19367f0_0 .net *"_s100", 0 0, L_0x19c84e0; 1 drivers +v0x19368d0_0 .net *"_s102", 0 0, L_0x19c8640; 1 drivers +v0x19369b0_0 .net *"_s104", 0 0, L_0x19c87a0; 1 drivers +v0x1936aa0_0 .net *"_s106", 0 0, L_0x19c8900; 1 drivers +v0x1936b80_0 .net *"_s108", 0 0, L_0x19c8a60; 1 drivers +v0x1936cb0_0 .net *"_s110", 0 0, L_0x19c8bc0; 1 drivers +v0x1936d90_0 .net *"_s112", 0 0, L_0x19c8d20; 1 drivers +v0x1936e70_0 .net *"_s114", 0 0, L_0x19c8e80; 1 drivers +v0x1936f50_0 .net *"_s116", 0 0, L_0x19c8fe0; 1 drivers +v0x19370c0_0 .net *"_s118", 0 0, L_0x19c9140; 1 drivers +v0x19371a0_0 .net *"_s120", 0 0, L_0x19c7d00; 1 drivers +v0x1937280_0 .net *"_s122", 0 0, L_0x19c96b0; 1 drivers +v0x1937360_0 .net *"_s124", 0 0, L_0x19c97c0; 1 drivers +v0x1937440_0 .net *"_s126", 0 0, L_0x19ca540; 1 drivers +v0x1937520_0 .net *"_s64", 0 0, L_0x19c6820; 1 drivers +v0x1937600_0 .net *"_s66", 0 0, L_0x19c6980; 1 drivers +v0x19376e0_0 .net *"_s68", 0 0, L_0x19c6d70; 1 drivers +v0x1937890_0 .net *"_s70", 0 0, L_0x19c6e80; 1 drivers +v0x1937930_0 .net *"_s72", 0 0, L_0x19c70f0; 1 drivers +v0x1937a10_0 .net *"_s74", 0 0, L_0x19c7200; 1 drivers +v0x1937af0_0 .net *"_s76", 0 0, L_0x19c7360; 1 drivers +v0x1937bd0_0 .net *"_s78", 0 0, L_0x19c74c0; 1 drivers +v0x1937cb0_0 .net *"_s80", 0 0, L_0x19c7620; 1 drivers +v0x1937d90_0 .net *"_s82", 0 0, L_0x19c7780; 1 drivers +v0x1937e70_0 .net *"_s84", 0 0, L_0x19c78e0; 1 drivers +v0x1937f50_0 .net *"_s86", 0 0, L_0x19c7a40; 1 drivers +v0x1938030_0 .net *"_s88", 0 0, L_0x19c6fe0; 1 drivers +v0x1938110_0 .net *"_s90", 0 0, L_0x19c7e00; 1 drivers +v0x19381f0_0 .net *"_s92", 0 0, L_0x19c7f60; 1 drivers +v0x19382d0_0 .net *"_s94", 0 0, L_0x19c80c0; 1 drivers +v0x19383b0_0 .net *"_s96", 0 0, L_0x19c8220; 1 drivers +v0x1938490_0 .net *"_s98", 0 0, L_0x19c8380; 1 drivers +v0x1938570_0 .net "carryout", 0 0, L_0x7f93f4ea0258; alias, 1 drivers +v0x19377a0 .array "interresult", 0 31; +v0x19377a0_0 .net v0x19377a0 0, 0 0, L_0x19bf800; 1 drivers +v0x19377a0_1 .net v0x19377a0 1, 0 0, L_0x19bfb10; 1 drivers +v0x19377a0_2 .net v0x19377a0 2, 0 0, L_0x19bfe20; 1 drivers +v0x19377a0_3 .net v0x19377a0 3, 0 0, L_0x19c0130; 1 drivers +v0x19377a0_4 .net v0x19377a0 4, 0 0, L_0x19c0490; 1 drivers +v0x19377a0_5 .net v0x19377a0 5, 0 0, L_0x19c0800; 1 drivers +v0x19377a0_6 .net v0x19377a0 6, 0 0, L_0x19c0b30; 1 drivers +v0x19377a0_7 .net v0x19377a0 7, 0 0, L_0x19c0ac0; 1 drivers +v0x19377a0_8 .net v0x19377a0 8, 0 0, L_0x19c11f0; 1 drivers +v0x19377a0_9 .net v0x19377a0 9, 0 0, L_0x19c1160; 1 drivers +v0x19377a0_10 .net v0x19377a0 10, 0 0, L_0x19c1500; 1 drivers +v0x19377a0_11 .net v0x19377a0 11, 0 0, L_0x19c1840; 1 drivers +v0x19377a0_12 .net v0x19377a0 12, 0 0, L_0x19c1b90; 1 drivers +v0x19377a0_13 .net v0x19377a0 13, 0 0, L_0x19c1ef0; 1 drivers +v0x19377a0_14 .net v0x19377a0 14, 0 0, L_0x19c2210; 1 drivers +v0x19377a0_15 .net v0x19377a0 15, 0 0, L_0x19c2540; 1 drivers +v0x19377a0_16 .net v0x19377a0 16, 0 0, L_0x19c2880; 1 drivers +v0x19377a0_17 .net v0x19377a0 17, 0 0, L_0x19c2bd0; 1 drivers +v0x19377a0_18 .net v0x19377a0 18, 0 0, L_0x1938ac0; 1 drivers +v0x19377a0_19 .net v0x19377a0 19, 0 0, L_0x19c2f30; 1 drivers +v0x19377a0_20 .net v0x19377a0 20, 0 0, L_0x19c32b0; 1 drivers +v0x19377a0_21 .net v0x19377a0 21, 0 0, L_0x19c35d0; 1 drivers +v0x19377a0_22 .net v0x19377a0 22, 0 0, L_0x19c38b0; 1 drivers +v0x19377a0_23 .net v0x19377a0 23, 0 0, L_0x19c3bf0; 1 drivers +v0x19377a0_24 .net v0x19377a0 24, 0 0, L_0x19c3ef0; 1 drivers +v0x19377a0_25 .net v0x19377a0 25, 0 0, L_0x19c41b0; 1 drivers +v0x19377a0_26 .net v0x19377a0 26, 0 0, L_0x1992050; 1 drivers +v0x19377a0_27 .net v0x19377a0 27, 0 0, L_0x19923a0; 1 drivers +v0x19377a0_28 .net v0x19377a0 28, 0 0, L_0x1992700; 1 drivers +v0x19377a0_29 .net v0x19377a0 29, 0 0, L_0x1992a20; 1 drivers +v0x19377a0_30 .net v0x19377a0 30, 0 0, L_0x1992d50; 1 drivers +v0x19377a0_31 .net v0x19377a0 31, 0 0, L_0x19c64f0; 1 drivers +v0x1938cf0_0 .net "operandA", 31 0, o0x7f93f4eeeb98; alias, 0 drivers +v0x1938e40_0 .net "operandB", 31 0, o0x7f93f4eeebc8; alias, 0 drivers +v0x1938f90_0 .net "othercontrolsignal", 0 0, v0x17bafe0_0; alias, 1 drivers +v0x1939030_0 .net "overflow", 0 0, L_0x7f93f4ea02e8; alias, 1 drivers +v0x19390d0_0 .net "result", 31 0, L_0x19c9920; alias, 1 drivers +v0x19391b0_0 .net "zero", 0 0, L_0x7f93f4ea02a0; alias, 1 drivers +L_0x19bf8c0 .part o0x7f93f4eeeb98, 0, 1; +L_0x19bfa20 .part o0x7f93f4eeebc8, 0, 1; +L_0x19bfbd0 .part o0x7f93f4eeeb98, 1, 1; +L_0x19bfd30 .part o0x7f93f4eeebc8, 1, 1; +L_0x19bfee0 .part o0x7f93f4eeeb98, 2, 1; +L_0x19c0040 .part o0x7f93f4eeebc8, 2, 1; +L_0x19c01f0 .part o0x7f93f4eeeb98, 3, 1; +L_0x19c0350 .part o0x7f93f4eeebc8, 3, 1; +L_0x19c0550 .part o0x7f93f4eeeb98, 4, 1; +L_0x19c06b0 .part o0x7f93f4eeebc8, 4, 1; +L_0x19c0870 .part o0x7f93f4eeeb98, 5, 1; +L_0x19c09d0 .part o0x7f93f4eeebc8, 5, 1; +L_0x19c0bf0 .part o0x7f93f4eeeb98, 6, 1; +L_0x19c0d50 .part o0x7f93f4eeebc8, 6, 1; +L_0x19c0f10 .part o0x7f93f4eeeb98, 7, 1; +L_0x19c1070 .part o0x7f93f4eeebc8, 7, 1; +L_0x19c12b0 .part o0x7f93f4eeeb98, 8, 1; +L_0x19c1410 .part o0x7f93f4eeebc8, 8, 1; +L_0x19c15f0 .part o0x7f93f4eeeb98, 9, 1; +L_0x19c1750 .part o0x7f93f4eeebc8, 9, 1; +L_0x19c1940 .part o0x7f93f4eeeb98, 10, 1; +L_0x19c1aa0 .part o0x7f93f4eeebc8, 10, 1; +L_0x19c1ca0 .part o0x7f93f4eeeb98, 11, 1; +L_0x19c1e00 .part o0x7f93f4eeebc8, 11, 1; +L_0x19c1fc0 .part o0x7f93f4eeeb98, 12, 1; +L_0x19c2120 .part o0x7f93f4eeebc8, 12, 1; +L_0x19c22f0 .part o0x7f93f4eeeb98, 13, 1; +L_0x19c2450 .part o0x7f93f4eeebc8, 13, 1; +L_0x19c2630 .part o0x7f93f4eeeb98, 14, 1; +L_0x19c2790 .part o0x7f93f4eeebc8, 14, 1; +L_0x19c2980 .part o0x7f93f4eeeb98, 15, 1; +L_0x19c2ae0 .part o0x7f93f4eeebc8, 15, 1; +L_0x19c2ce0 .part o0x7f93f4eeeb98, 16, 1; +L_0x19c2e40 .part o0x7f93f4eeebc8, 16, 1; +L_0x1938930 .part o0x7f93f4eeeb98, 17, 1; +L_0x1938a20 .part o0x7f93f4eeebc8, 17, 1; +L_0x19c3060 .part o0x7f93f4eeeb98, 18, 1; +L_0x19c31c0 .part o0x7f93f4eeebc8, 18, 1; +L_0x19c33f0 .part o0x7f93f4eeeb98, 19, 1; +L_0x19c34e0 .part o0x7f93f4eeebc8, 19, 1; +L_0x19c3720 .part o0x7f93f4eeeb98, 20, 1; +L_0x19c37c0 .part o0x7f93f4eeebc8, 20, 1; +L_0x19c3a10 .part o0x7f93f4eeeb98, 21, 1; +L_0x19c3b00 .part o0x7f93f4eeebc8, 21, 1; +L_0x19c3d60 .part o0x7f93f4eeeb98, 22, 1; +L_0x19c3e00 .part o0x7f93f4eeebc8, 22, 1; +L_0x19c4070 .part o0x7f93f4eeeb98, 23, 1; +L_0x19c4110 .part o0x7f93f4eeebc8, 23, 1; +L_0x19c4340 .part o0x7f93f4eeeb98, 24, 1; +L_0x1991f60 .part o0x7f93f4eeebc8, 24, 1; +L_0x19c4270 .part o0x7f93f4eeeb98, 25, 1; +L_0x1992240 .part o0x7f93f4eeebc8, 25, 1; +L_0x1992110 .part o0x7f93f4eeeb98, 26, 1; +L_0x19925a0 .part o0x7f93f4eeebc8, 26, 1; +L_0x1992460 .part o0x7f93f4eeeb98, 27, 1; +L_0x19928c0 .part o0x7f93f4eeebc8, 27, 1; +L_0x19927c0 .part o0x7f93f4eeeb98, 28, 1; +L_0x1992bf0 .part o0x7f93f4eeebc8, 28, 1; +L_0x1992a90 .part o0x7f93f4eeeb98, 29, 1; +L_0x19c6400 .part o0x7f93f4eeebc8, 29, 1; +L_0x1992e10 .part o0x7f93f4eeeb98, 30, 1; +L_0x19c6730 .part o0x7f93f4eeebc8, 30, 1; +L_0x19c65b0 .part o0x7f93f4eeeb98, 31, 1; +L_0x19c6a70 .part o0x7f93f4eeebc8, 31, 1; +LS_0x19c9920_0_0 .concat8 [ 1 1 1 1], L_0x19c6820, L_0x19c6980, L_0x19c6d70, L_0x19c6e80; +LS_0x19c9920_0_4 .concat8 [ 1 1 1 1], L_0x19c70f0, L_0x19c7200, L_0x19c7360, L_0x19c74c0; +LS_0x19c9920_0_8 .concat8 [ 1 1 1 1], L_0x19c7620, L_0x19c7780, L_0x19c78e0, L_0x19c7a40; +LS_0x19c9920_0_12 .concat8 [ 1 1 1 1], L_0x19c6fe0, L_0x19c7e00, L_0x19c7f60, L_0x19c80c0; +LS_0x19c9920_0_16 .concat8 [ 1 1 1 1], L_0x19c8220, L_0x19c8380, L_0x19c84e0, L_0x19c8640; +LS_0x19c9920_0_20 .concat8 [ 1 1 1 1], L_0x19c87a0, L_0x19c8900, L_0x19c8a60, L_0x19c8bc0; +LS_0x19c9920_0_24 .concat8 [ 1 1 1 1], L_0x19c8d20, L_0x19c8e80, L_0x19c8fe0, L_0x19c9140; +LS_0x19c9920_0_28 .concat8 [ 1 1 1 1], L_0x19c7d00, L_0x19c96b0, L_0x19c97c0, L_0x19ca540; +LS_0x19c9920_1_0 .concat8 [ 4 4 4 4], LS_0x19c9920_0_0, LS_0x19c9920_0_4, LS_0x19c9920_0_8, LS_0x19c9920_0_12; +LS_0x19c9920_1_4 .concat8 [ 4 4 4 4], LS_0x19c9920_0_16, LS_0x19c9920_0_20, LS_0x19c9920_0_24, LS_0x19c9920_0_28; +L_0x19c9920 .concat8 [ 16 16 0 0], LS_0x19c9920_1_0, LS_0x19c9920_1_4; +S_0x1928180 .scope generate, "ripple0[0]" "ripple0[0]" 2 132, 2 132 0, S_0x1927f50; + .timescale 0 0; +P_0x1928390 .param/l "i" 0 2 132, +C4<00>; +L_0x19bf800/d .functor AND 1, L_0x19bf8c0, L_0x19bfa20, C4<1>, C4<1>; +L_0x19bf800 .delay 1 (20,20,20) L_0x19bf800/d; +v0x1928470_0 .net *"_s1", 0 0, L_0x19bf8c0; 1 drivers +v0x1928550_0 .net *"_s2", 0 0, L_0x19bfa20; 1 drivers +S_0x1928630 .scope generate, "ripple0[1]" "ripple0[1]" 2 132, 2 132 0, S_0x1927f50; + .timescale 0 0; +P_0x1928840 .param/l "i" 0 2 132, +C4<01>; +L_0x19bfb10/d .functor AND 1, L_0x19bfbd0, L_0x19bfd30, C4<1>, C4<1>; +L_0x19bfb10 .delay 1 (20,20,20) L_0x19bfb10/d; +v0x1928900_0 .net *"_s1", 0 0, L_0x19bfbd0; 1 drivers +v0x19289e0_0 .net *"_s2", 0 0, L_0x19bfd30; 1 drivers +S_0x1928ac0 .scope generate, "ripple0[2]" "ripple0[2]" 2 132, 2 132 0, S_0x1927f50; + .timescale 0 0; +P_0x1928cd0 .param/l "i" 0 2 132, +C4<010>; +L_0x19bfe20/d .functor AND 1, L_0x19bfee0, L_0x19c0040, C4<1>, C4<1>; +L_0x19bfe20 .delay 1 (20,20,20) L_0x19bfe20/d; +v0x1928d70_0 .net *"_s1", 0 0, L_0x19bfee0; 1 drivers +v0x1928e50_0 .net *"_s2", 0 0, L_0x19c0040; 1 drivers +S_0x1928f30 .scope generate, "ripple0[3]" "ripple0[3]" 2 132, 2 132 0, S_0x1927f50; + .timescale 0 0; +P_0x1929140 .param/l "i" 0 2 132, +C4<011>; +L_0x19c0130/d .functor AND 1, L_0x19c01f0, L_0x19c0350, C4<1>, C4<1>; +L_0x19c0130 .delay 1 (20,20,20) L_0x19c0130/d; +v0x1929200_0 .net *"_s1", 0 0, L_0x19c01f0; 1 drivers +v0x19292e0_0 .net *"_s2", 0 0, L_0x19c0350; 1 drivers +S_0x19293c0 .scope generate, "ripple0[4]" "ripple0[4]" 2 132, 2 132 0, S_0x1927f50; + .timescale 0 0; +P_0x1929620 .param/l "i" 0 2 132, +C4<0100>; +L_0x19c0490/d .functor AND 1, L_0x19c0550, L_0x19c06b0, C4<1>, C4<1>; +L_0x19c0490 .delay 1 (20,20,20) L_0x19c0490/d; +v0x19296e0_0 .net *"_s1", 0 0, L_0x19c0550; 1 drivers +v0x19297c0_0 .net *"_s2", 0 0, L_0x19c06b0; 1 drivers +S_0x19298a0 .scope generate, "ripple0[5]" "ripple0[5]" 2 132, 2 132 0, S_0x1927f50; + .timescale 0 0; +P_0x1929ab0 .param/l "i" 0 2 132, +C4<0101>; +L_0x19c0800/d .functor AND 1, L_0x19c0870, L_0x19c09d0, C4<1>, C4<1>; +L_0x19c0800 .delay 1 (20,20,20) L_0x19c0800/d; +v0x1929b70_0 .net *"_s1", 0 0, L_0x19c0870; 1 drivers +v0x1929c50_0 .net *"_s2", 0 0, L_0x19c09d0; 1 drivers +S_0x1929d30 .scope generate, "ripple0[6]" "ripple0[6]" 2 132, 2 132 0, S_0x1927f50; + .timescale 0 0; +P_0x1929f40 .param/l "i" 0 2 132, +C4<0110>; +L_0x19c0b30/d .functor AND 1, L_0x19c0bf0, L_0x19c0d50, C4<1>, C4<1>; +L_0x19c0b30 .delay 1 (20,20,20) L_0x19c0b30/d; +v0x192a000_0 .net *"_s1", 0 0, L_0x19c0bf0; 1 drivers +v0x192a0e0_0 .net *"_s2", 0 0, L_0x19c0d50; 1 drivers +S_0x192a1c0 .scope generate, "ripple0[7]" "ripple0[7]" 2 132, 2 132 0, S_0x1927f50; + .timescale 0 0; +P_0x192a3d0 .param/l "i" 0 2 132, +C4<0111>; +L_0x19c0ac0/d .functor AND 1, L_0x19c0f10, L_0x19c1070, C4<1>, C4<1>; +L_0x19c0ac0 .delay 1 (20,20,20) L_0x19c0ac0/d; +v0x192a490_0 .net *"_s1", 0 0, L_0x19c0f10; 1 drivers +v0x192a570_0 .net *"_s2", 0 0, L_0x19c1070; 1 drivers +S_0x192a650 .scope generate, "ripple0[8]" "ripple0[8]" 2 132, 2 132 0, S_0x1927f50; + .timescale 0 0; +P_0x19295d0 .param/l "i" 0 2 132, +C4<01000>; +L_0x19c11f0/d .functor AND 1, L_0x19c12b0, L_0x19c1410, C4<1>, C4<1>; +L_0x19c11f0 .delay 1 (20,20,20) L_0x19c11f0/d; +v0x192a960_0 .net *"_s1", 0 0, L_0x19c12b0; 1 drivers +v0x192aa40_0 .net *"_s2", 0 0, L_0x19c1410; 1 drivers +S_0x192ab20 .scope generate, "ripple0[9]" "ripple0[9]" 2 132, 2 132 0, S_0x1927f50; + .timescale 0 0; +P_0x192ad30 .param/l "i" 0 2 132, +C4<01001>; +L_0x19c1160/d .functor AND 1, L_0x19c15f0, L_0x19c1750, C4<1>, C4<1>; +L_0x19c1160 .delay 1 (20,20,20) L_0x19c1160/d; +v0x192adf0_0 .net *"_s1", 0 0, L_0x19c15f0; 1 drivers +v0x192aed0_0 .net *"_s2", 0 0, L_0x19c1750; 1 drivers +S_0x192afb0 .scope generate, "ripple0[10]" "ripple0[10]" 2 132, 2 132 0, S_0x1927f50; + .timescale 0 0; +P_0x192b1c0 .param/l "i" 0 2 132, +C4<01010>; +L_0x19c1500/d .functor AND 1, L_0x19c1940, L_0x19c1aa0, C4<1>, C4<1>; +L_0x19c1500 .delay 1 (20,20,20) L_0x19c1500/d; +v0x192b280_0 .net *"_s1", 0 0, L_0x19c1940; 1 drivers +v0x192b360_0 .net *"_s2", 0 0, L_0x19c1aa0; 1 drivers +S_0x192b440 .scope generate, "ripple0[11]" "ripple0[11]" 2 132, 2 132 0, S_0x1927f50; + .timescale 0 0; +P_0x192b650 .param/l "i" 0 2 132, +C4<01011>; +L_0x19c1840/d .functor AND 1, L_0x19c1ca0, L_0x19c1e00, C4<1>, C4<1>; +L_0x19c1840 .delay 1 (20,20,20) L_0x19c1840/d; +v0x192b710_0 .net *"_s1", 0 0, L_0x19c1ca0; 1 drivers +v0x192b7f0_0 .net *"_s2", 0 0, L_0x19c1e00; 1 drivers +S_0x192b8d0 .scope generate, "ripple0[12]" "ripple0[12]" 2 132, 2 132 0, S_0x1927f50; + .timescale 0 0; +P_0x192bae0 .param/l "i" 0 2 132, +C4<01100>; +L_0x19c1b90/d .functor AND 1, L_0x19c1fc0, L_0x19c2120, C4<1>, C4<1>; +L_0x19c1b90 .delay 1 (20,20,20) L_0x19c1b90/d; +v0x192bba0_0 .net *"_s1", 0 0, L_0x19c1fc0; 1 drivers +v0x192bc80_0 .net *"_s2", 0 0, L_0x19c2120; 1 drivers +S_0x192bd60 .scope generate, "ripple0[13]" "ripple0[13]" 2 132, 2 132 0, S_0x1927f50; + .timescale 0 0; +P_0x192bf70 .param/l "i" 0 2 132, +C4<01101>; +L_0x19c1ef0/d .functor AND 1, L_0x19c22f0, L_0x19c2450, C4<1>, C4<1>; +L_0x19c1ef0 .delay 1 (20,20,20) L_0x19c1ef0/d; +v0x192c030_0 .net *"_s1", 0 0, L_0x19c22f0; 1 drivers +v0x192c110_0 .net *"_s2", 0 0, L_0x19c2450; 1 drivers +S_0x192c1f0 .scope generate, "ripple0[14]" "ripple0[14]" 2 132, 2 132 0, S_0x1927f50; + .timescale 0 0; +P_0x192c400 .param/l "i" 0 2 132, +C4<01110>; +L_0x19c2210/d .functor AND 1, L_0x19c2630, L_0x19c2790, C4<1>, C4<1>; +L_0x19c2210 .delay 1 (20,20,20) L_0x19c2210/d; +v0x192c4c0_0 .net *"_s1", 0 0, L_0x19c2630; 1 drivers +v0x192c5a0_0 .net *"_s2", 0 0, L_0x19c2790; 1 drivers +S_0x192c680 .scope generate, "ripple0[15]" "ripple0[15]" 2 132, 2 132 0, S_0x1927f50; + .timescale 0 0; +P_0x192c890 .param/l "i" 0 2 132, +C4<01111>; +L_0x19c2540/d .functor AND 1, L_0x19c2980, L_0x19c2ae0, C4<1>, C4<1>; +L_0x19c2540 .delay 1 (20,20,20) L_0x19c2540/d; +v0x192c950_0 .net *"_s1", 0 0, L_0x19c2980; 1 drivers +v0x192ca30_0 .net *"_s2", 0 0, L_0x19c2ae0; 1 drivers +S_0x192cb10 .scope generate, "ripple0[16]" "ripple0[16]" 2 132, 2 132 0, S_0x1927f50; + .timescale 0 0; +P_0x192a860 .param/l "i" 0 2 132, +C4<010000>; +L_0x19c2880/d .functor AND 1, L_0x19c2ce0, L_0x19c2e40, C4<1>, C4<1>; +L_0x19c2880 .delay 1 (20,20,20) L_0x19c2880/d; +v0x192ce80_0 .net *"_s1", 0 0, L_0x19c2ce0; 1 drivers +v0x192cf40_0 .net *"_s2", 0 0, L_0x19c2e40; 1 drivers +S_0x192d020 .scope generate, "ripple0[17]" "ripple0[17]" 2 132, 2 132 0, S_0x1927f50; + .timescale 0 0; +P_0x192d230 .param/l "i" 0 2 132, +C4<010001>; +L_0x19c2bd0/d .functor AND 1, L_0x1938930, L_0x1938a20, C4<1>, C4<1>; +L_0x19c2bd0 .delay 1 (20,20,20) L_0x19c2bd0/d; +v0x192d2f0_0 .net *"_s1", 0 0, L_0x1938930; 1 drivers +v0x192d3d0_0 .net *"_s2", 0 0, L_0x1938a20; 1 drivers +S_0x192d4b0 .scope generate, "ripple0[18]" "ripple0[18]" 2 132, 2 132 0, S_0x1927f50; + .timescale 0 0; +P_0x192d6c0 .param/l "i" 0 2 132, +C4<010010>; +L_0x1938ac0/d .functor AND 1, L_0x19c3060, L_0x19c31c0, C4<1>, C4<1>; +L_0x1938ac0 .delay 1 (20,20,20) L_0x1938ac0/d; +v0x192d780_0 .net *"_s1", 0 0, L_0x19c3060; 1 drivers +v0x192d860_0 .net *"_s2", 0 0, L_0x19c31c0; 1 drivers +S_0x192d940 .scope generate, "ripple0[19]" "ripple0[19]" 2 132, 2 132 0, S_0x1927f50; + .timescale 0 0; +P_0x192db50 .param/l "i" 0 2 132, +C4<010011>; +L_0x19c2f30/d .functor AND 1, L_0x19c33f0, L_0x19c34e0, C4<1>, C4<1>; +L_0x19c2f30 .delay 1 (20,20,20) L_0x19c2f30/d; +v0x192dc10_0 .net *"_s1", 0 0, L_0x19c33f0; 1 drivers +v0x192dcf0_0 .net *"_s2", 0 0, L_0x19c34e0; 1 drivers +S_0x192ddd0 .scope generate, "ripple0[20]" "ripple0[20]" 2 132, 2 132 0, S_0x1927f50; + .timescale 0 0; +P_0x192dfe0 .param/l "i" 0 2 132, +C4<010100>; +L_0x19c32b0/d .functor AND 1, L_0x19c3720, L_0x19c37c0, C4<1>, C4<1>; +L_0x19c32b0 .delay 1 (20,20,20) L_0x19c32b0/d; +v0x192e0a0_0 .net *"_s1", 0 0, L_0x19c3720; 1 drivers +v0x192e180_0 .net *"_s2", 0 0, L_0x19c37c0; 1 drivers +S_0x192e260 .scope generate, "ripple0[21]" "ripple0[21]" 2 132, 2 132 0, S_0x1927f50; + .timescale 0 0; +P_0x192e470 .param/l "i" 0 2 132, +C4<010101>; +L_0x19c35d0/d .functor AND 1, L_0x19c3a10, L_0x19c3b00, C4<1>, C4<1>; +L_0x19c35d0 .delay 1 (20,20,20) L_0x19c35d0/d; +v0x192e530_0 .net *"_s1", 0 0, L_0x19c3a10; 1 drivers +v0x192e610_0 .net *"_s2", 0 0, L_0x19c3b00; 1 drivers +S_0x192e6f0 .scope generate, "ripple0[22]" "ripple0[22]" 2 132, 2 132 0, S_0x1927f50; + .timescale 0 0; +P_0x192e900 .param/l "i" 0 2 132, +C4<010110>; +L_0x19c38b0/d .functor AND 1, L_0x19c3d60, L_0x19c3e00, C4<1>, C4<1>; +L_0x19c38b0 .delay 1 (20,20,20) L_0x19c38b0/d; +v0x192e9c0_0 .net *"_s1", 0 0, L_0x19c3d60; 1 drivers +v0x192eaa0_0 .net *"_s2", 0 0, L_0x19c3e00; 1 drivers +S_0x192eb80 .scope generate, "ripple0[23]" "ripple0[23]" 2 132, 2 132 0, S_0x1927f50; + .timescale 0 0; +P_0x192ed90 .param/l "i" 0 2 132, +C4<010111>; +L_0x19c3bf0/d .functor AND 1, L_0x19c4070, L_0x19c4110, C4<1>, C4<1>; +L_0x19c3bf0 .delay 1 (20,20,20) L_0x19c3bf0/d; +v0x192ee50_0 .net *"_s1", 0 0, L_0x19c4070; 1 drivers +v0x192ef30_0 .net *"_s2", 0 0, L_0x19c4110; 1 drivers +S_0x192f010 .scope generate, "ripple0[24]" "ripple0[24]" 2 132, 2 132 0, S_0x1927f50; + .timescale 0 0; +P_0x192f220 .param/l "i" 0 2 132, +C4<011000>; +L_0x19c3ef0/d .functor AND 1, L_0x19c4340, L_0x1991f60, C4<1>, C4<1>; +L_0x19c3ef0 .delay 1 (20,20,20) L_0x19c3ef0/d; +v0x192f2e0_0 .net *"_s1", 0 0, L_0x19c4340; 1 drivers +v0x192f3c0_0 .net *"_s2", 0 0, L_0x1991f60; 1 drivers +S_0x192f4a0 .scope generate, "ripple0[25]" "ripple0[25]" 2 132, 2 132 0, S_0x1927f50; + .timescale 0 0; +P_0x192f6b0 .param/l "i" 0 2 132, +C4<011001>; +L_0x19c41b0/d .functor AND 1, L_0x19c4270, L_0x1992240, C4<1>, C4<1>; +L_0x19c41b0 .delay 1 (20,20,20) L_0x19c41b0/d; +v0x192f770_0 .net *"_s1", 0 0, L_0x19c4270; 1 drivers +v0x192f850_0 .net *"_s2", 0 0, L_0x1992240; 1 drivers +S_0x192f930 .scope generate, "ripple0[26]" "ripple0[26]" 2 132, 2 132 0, S_0x1927f50; + .timescale 0 0; +P_0x192fb40 .param/l "i" 0 2 132, +C4<011010>; +L_0x1992050/d .functor AND 1, L_0x1992110, L_0x19925a0, C4<1>, C4<1>; +L_0x1992050 .delay 1 (20,20,20) L_0x1992050/d; +v0x192fc00_0 .net *"_s1", 0 0, L_0x1992110; 1 drivers +v0x192fce0_0 .net *"_s2", 0 0, L_0x19925a0; 1 drivers +S_0x192fdc0 .scope generate, "ripple0[27]" "ripple0[27]" 2 132, 2 132 0, S_0x1927f50; + .timescale 0 0; +P_0x192ffd0 .param/l "i" 0 2 132, +C4<011011>; +L_0x19923a0/d .functor AND 1, L_0x1992460, L_0x19928c0, C4<1>, C4<1>; +L_0x19923a0 .delay 1 (20,20,20) L_0x19923a0/d; +v0x1930090_0 .net *"_s1", 0 0, L_0x1992460; 1 drivers +v0x1930170_0 .net *"_s2", 0 0, L_0x19928c0; 1 drivers +S_0x1930250 .scope generate, "ripple0[28]" "ripple0[28]" 2 132, 2 132 0, S_0x1927f50; + .timescale 0 0; +P_0x1930460 .param/l "i" 0 2 132, +C4<011100>; +L_0x1992700/d .functor AND 1, L_0x19927c0, L_0x1992bf0, C4<1>, C4<1>; +L_0x1992700 .delay 1 (20,20,20) L_0x1992700/d; +v0x1930520_0 .net *"_s1", 0 0, L_0x19927c0; 1 drivers +v0x1930600_0 .net *"_s2", 0 0, L_0x1992bf0; 1 drivers +S_0x19306e0 .scope generate, "ripple0[29]" "ripple0[29]" 2 132, 2 132 0, S_0x1927f50; + .timescale 0 0; +P_0x19308f0 .param/l "i" 0 2 132, +C4<011101>; +L_0x1992a20/d .functor AND 1, L_0x1992a90, L_0x19c6400, C4<1>, C4<1>; +L_0x1992a20 .delay 1 (20,20,20) L_0x1992a20/d; +v0x19309b0_0 .net *"_s1", 0 0, L_0x1992a90; 1 drivers +v0x1930a90_0 .net *"_s2", 0 0, L_0x19c6400; 1 drivers +S_0x1930b70 .scope generate, "ripple0[30]" "ripple0[30]" 2 132, 2 132 0, S_0x1927f50; + .timescale 0 0; +P_0x1930d80 .param/l "i" 0 2 132, +C4<011110>; +L_0x1992d50/d .functor AND 1, L_0x1992e10, L_0x19c6730, C4<1>, C4<1>; +L_0x1992d50 .delay 1 (20,20,20) L_0x1992d50/d; +v0x1930e40_0 .net *"_s1", 0 0, L_0x1992e10; 1 drivers +v0x1930f20_0 .net *"_s2", 0 0, L_0x19c6730; 1 drivers +S_0x1931000 .scope generate, "ripple0[31]" "ripple0[31]" 2 132, 2 132 0, S_0x1927f50; + .timescale 0 0; +P_0x1931210 .param/l "i" 0 2 132, +C4<011111>; +L_0x19c64f0/d .functor AND 1, L_0x19c65b0, L_0x19c6a70, C4<1>, C4<1>; +L_0x19c64f0 .delay 1 (20,20,20) L_0x19c64f0/d; +v0x19312d0_0 .net *"_s1", 0 0, L_0x19c65b0; 1 drivers +v0x19313b0_0 .net *"_s2", 0 0, L_0x19c6a70; 1 drivers +S_0x1931490 .scope generate, "ripple1[0]" "ripple1[0]" 2 140, 2 140 0, S_0x1927f50; + .timescale 0 0; +P_0x192cd20 .param/l "j" 0 2 140, +C4<00>; +L_0x19c6820/d .functor XOR 1, v0x17bafe0_0, L_0x19bf800, C4<0>, C4<0>; +L_0x19c6820 .delay 1 (20,20,20) L_0x19c6820/d; +S_0x19318b0 .scope generate, "ripple1[1]" "ripple1[1]" 2 140, 2 140 0, S_0x1927f50; + .timescale 0 0; +P_0x1931a50 .param/l "j" 0 2 140, +C4<01>; +L_0x19c6980/d .functor XOR 1, v0x17bafe0_0, L_0x19bfb10, C4<0>, C4<0>; +L_0x19c6980 .delay 1 (20,20,20) L_0x19c6980/d; +S_0x1931b10 .scope generate, "ripple1[2]" "ripple1[2]" 2 140, 2 140 0, S_0x1927f50; + .timescale 0 0; +P_0x1931d00 .param/l "j" 0 2 140, +C4<010>; +L_0x19c6d70/d .functor XOR 1, v0x17bafe0_0, L_0x19bfe20, C4<0>, C4<0>; +L_0x19c6d70 .delay 1 (20,20,20) L_0x19c6d70/d; +S_0x1931dc0 .scope generate, "ripple1[3]" "ripple1[3]" 2 140, 2 140 0, S_0x1927f50; + .timescale 0 0; +P_0x1931fb0 .param/l "j" 0 2 140, +C4<011>; +L_0x19c6e80/d .functor XOR 1, v0x17bafe0_0, L_0x19c0130, C4<0>, C4<0>; +L_0x19c6e80 .delay 1 (20,20,20) L_0x19c6e80/d; +S_0x1932070 .scope generate, "ripple1[4]" "ripple1[4]" 2 140, 2 140 0, S_0x1927f50; + .timescale 0 0; +P_0x1932260 .param/l "j" 0 2 140, +C4<0100>; +L_0x19c70f0/d .functor XOR 1, v0x17bafe0_0, L_0x19c0490, C4<0>, C4<0>; +L_0x19c70f0 .delay 1 (20,20,20) L_0x19c70f0/d; +S_0x1932320 .scope generate, "ripple1[5]" "ripple1[5]" 2 140, 2 140 0, S_0x1927f50; + .timescale 0 0; +P_0x1932510 .param/l "j" 0 2 140, +C4<0101>; +L_0x19c7200/d .functor XOR 1, v0x17bafe0_0, L_0x19c0800, C4<0>, C4<0>; +L_0x19c7200 .delay 1 (20,20,20) L_0x19c7200/d; +S_0x19325d0 .scope generate, "ripple1[6]" "ripple1[6]" 2 140, 2 140 0, S_0x1927f50; + .timescale 0 0; +P_0x19327c0 .param/l "j" 0 2 140, +C4<0110>; +L_0x19c7360/d .functor XOR 1, v0x17bafe0_0, L_0x19c0b30, C4<0>, C4<0>; +L_0x19c7360 .delay 1 (20,20,20) L_0x19c7360/d; +S_0x1932880 .scope generate, "ripple1[7]" "ripple1[7]" 2 140, 2 140 0, S_0x1927f50; + .timescale 0 0; +P_0x1932a70 .param/l "j" 0 2 140, +C4<0111>; +L_0x19c74c0/d .functor XOR 1, v0x17bafe0_0, L_0x19c0ac0, C4<0>, C4<0>; +L_0x19c74c0 .delay 1 (20,20,20) L_0x19c74c0/d; +S_0x1932b30 .scope generate, "ripple1[8]" "ripple1[8]" 2 140, 2 140 0, S_0x1927f50; + .timescale 0 0; +P_0x1932d20 .param/l "j" 0 2 140, +C4<01000>; +L_0x19c7620/d .functor XOR 1, v0x17bafe0_0, L_0x19c11f0, C4<0>, C4<0>; +L_0x19c7620 .delay 1 (20,20,20) L_0x19c7620/d; +S_0x1932de0 .scope generate, "ripple1[9]" "ripple1[9]" 2 140, 2 140 0, S_0x1927f50; + .timescale 0 0; +P_0x1932fd0 .param/l "j" 0 2 140, +C4<01001>; +L_0x19c7780/d .functor XOR 1, v0x17bafe0_0, L_0x19c1160, C4<0>, C4<0>; +L_0x19c7780 .delay 1 (20,20,20) L_0x19c7780/d; +S_0x1933090 .scope generate, "ripple1[10]" "ripple1[10]" 2 140, 2 140 0, S_0x1927f50; + .timescale 0 0; +P_0x1933280 .param/l "j" 0 2 140, +C4<01010>; +L_0x19c78e0/d .functor XOR 1, v0x17bafe0_0, L_0x19c1500, C4<0>, C4<0>; +L_0x19c78e0 .delay 1 (20,20,20) L_0x19c78e0/d; +S_0x1933340 .scope generate, "ripple1[11]" "ripple1[11]" 2 140, 2 140 0, S_0x1927f50; + .timescale 0 0; +P_0x1933530 .param/l "j" 0 2 140, +C4<01011>; +L_0x19c7a40/d .functor XOR 1, v0x17bafe0_0, L_0x19c1840, C4<0>, C4<0>; +L_0x19c7a40 .delay 1 (20,20,20) L_0x19c7a40/d; +S_0x19335f0 .scope generate, "ripple1[12]" "ripple1[12]" 2 140, 2 140 0, S_0x1927f50; + .timescale 0 0; +P_0x19337e0 .param/l "j" 0 2 140, +C4<01100>; +L_0x19c6fe0/d .functor XOR 1, v0x17bafe0_0, L_0x19c1b90, C4<0>, C4<0>; +L_0x19c6fe0 .delay 1 (20,20,20) L_0x19c6fe0/d; +S_0x19338a0 .scope generate, "ripple1[13]" "ripple1[13]" 2 140, 2 140 0, S_0x1927f50; + .timescale 0 0; +P_0x1933a90 .param/l "j" 0 2 140, +C4<01101>; +L_0x19c7e00/d .functor XOR 1, v0x17bafe0_0, L_0x19c1ef0, C4<0>, C4<0>; +L_0x19c7e00 .delay 1 (20,20,20) L_0x19c7e00/d; +S_0x1933b50 .scope generate, "ripple1[14]" "ripple1[14]" 2 140, 2 140 0, S_0x1927f50; + .timescale 0 0; +P_0x1933d40 .param/l "j" 0 2 140, +C4<01110>; +L_0x19c7f60/d .functor XOR 1, v0x17bafe0_0, L_0x19c2210, C4<0>, C4<0>; +L_0x19c7f60 .delay 1 (20,20,20) L_0x19c7f60/d; +S_0x1933e00 .scope generate, "ripple1[15]" "ripple1[15]" 2 140, 2 140 0, S_0x1927f50; + .timescale 0 0; +P_0x1933ff0 .param/l "j" 0 2 140, +C4<01111>; +L_0x19c80c0/d .functor XOR 1, v0x17bafe0_0, L_0x19c2540, C4<0>, C4<0>; +L_0x19c80c0 .delay 1 (20,20,20) L_0x19c80c0/d; +S_0x1934090 .scope generate, "ripple1[16]" "ripple1[16]" 2 140, 2 140 0, S_0x1927f50; + .timescale 0 0; +P_0x1934260 .param/l "j" 0 2 140, +C4<010000>; +L_0x19c8220/d .functor XOR 1, v0x17bafe0_0, L_0x19c2880, C4<0>, C4<0>; +L_0x19c8220 .delay 1 (20,20,20) L_0x19c8220/d; +S_0x1934300 .scope generate, "ripple1[17]" "ripple1[17]" 2 140, 2 140 0, S_0x1927f50; + .timescale 0 0; +P_0x19344d0 .param/l "j" 0 2 140, +C4<010001>; +L_0x19c8380/d .functor XOR 1, v0x17bafe0_0, L_0x19c2bd0, C4<0>, C4<0>; +L_0x19c8380 .delay 1 (20,20,20) L_0x19c8380/d; +S_0x1934570 .scope generate, "ripple1[18]" "ripple1[18]" 2 140, 2 140 0, S_0x1927f50; + .timescale 0 0; +P_0x1934740 .param/l "j" 0 2 140, +C4<010010>; +L_0x19c84e0/d .functor XOR 1, v0x17bafe0_0, L_0x1938ac0, C4<0>, C4<0>; +L_0x19c84e0 .delay 1 (20,20,20) L_0x19c84e0/d; +S_0x19347e0 .scope generate, "ripple1[19]" "ripple1[19]" 2 140, 2 140 0, S_0x1927f50; + .timescale 0 0; +P_0x19349b0 .param/l "j" 0 2 140, +C4<010011>; +L_0x19c8640/d .functor XOR 1, v0x17bafe0_0, L_0x19c2f30, C4<0>, C4<0>; +L_0x19c8640 .delay 1 (20,20,20) L_0x19c8640/d; +S_0x1934a50 .scope generate, "ripple1[20]" "ripple1[20]" 2 140, 2 140 0, S_0x1927f50; + .timescale 0 0; +P_0x1934c20 .param/l "j" 0 2 140, +C4<010100>; +L_0x19c87a0/d .functor XOR 1, v0x17bafe0_0, L_0x19c32b0, C4<0>, C4<0>; +L_0x19c87a0 .delay 1 (20,20,20) L_0x19c87a0/d; +S_0x1934cc0 .scope generate, "ripple1[21]" "ripple1[21]" 2 140, 2 140 0, S_0x1927f50; + .timescale 0 0; +P_0x1934e90 .param/l "j" 0 2 140, +C4<010101>; +L_0x19c8900/d .functor XOR 1, v0x17bafe0_0, L_0x19c35d0, C4<0>, C4<0>; +L_0x19c8900 .delay 1 (20,20,20) L_0x19c8900/d; +S_0x1934f30 .scope generate, "ripple1[22]" "ripple1[22]" 2 140, 2 140 0, S_0x1927f50; + .timescale 0 0; +P_0x1935100 .param/l "j" 0 2 140, +C4<010110>; +L_0x19c8a60/d .functor XOR 1, v0x17bafe0_0, L_0x19c38b0, C4<0>, C4<0>; +L_0x19c8a60 .delay 1 (20,20,20) L_0x19c8a60/d; +S_0x19351a0 .scope generate, "ripple1[23]" "ripple1[23]" 2 140, 2 140 0, S_0x1927f50; + .timescale 0 0; +P_0x1935370 .param/l "j" 0 2 140, +C4<010111>; +L_0x19c8bc0/d .functor XOR 1, v0x17bafe0_0, L_0x19c3bf0, C4<0>, C4<0>; +L_0x19c8bc0 .delay 1 (20,20,20) L_0x19c8bc0/d; +S_0x1935410 .scope generate, "ripple1[24]" "ripple1[24]" 2 140, 2 140 0, S_0x1927f50; + .timescale 0 0; +P_0x19355e0 .param/l "j" 0 2 140, +C4<011000>; +L_0x19c8d20/d .functor XOR 1, v0x17bafe0_0, L_0x19c3ef0, C4<0>, C4<0>; +L_0x19c8d20 .delay 1 (20,20,20) L_0x19c8d20/d; +S_0x1935680 .scope generate, "ripple1[25]" "ripple1[25]" 2 140, 2 140 0, S_0x1927f50; + .timescale 0 0; +P_0x1935850 .param/l "j" 0 2 140, +C4<011001>; +L_0x19c8e80/d .functor XOR 1, v0x17bafe0_0, L_0x19c41b0, C4<0>, C4<0>; +L_0x19c8e80 .delay 1 (20,20,20) L_0x19c8e80/d; +S_0x19358f0 .scope generate, "ripple1[26]" "ripple1[26]" 2 140, 2 140 0, S_0x1927f50; + .timescale 0 0; +P_0x1935ac0 .param/l "j" 0 2 140, +C4<011010>; +L_0x19c8fe0/d .functor XOR 1, v0x17bafe0_0, L_0x1992050, C4<0>, C4<0>; +L_0x19c8fe0 .delay 1 (20,20,20) L_0x19c8fe0/d; +S_0x1935b60 .scope generate, "ripple1[27]" "ripple1[27]" 2 140, 2 140 0, S_0x1927f50; + .timescale 0 0; +P_0x1935d30 .param/l "j" 0 2 140, +C4<011011>; +L_0x19c9140/d .functor XOR 1, v0x17bafe0_0, L_0x19923a0, C4<0>, C4<0>; +L_0x19c9140 .delay 1 (20,20,20) L_0x19c9140/d; +S_0x1935dd0 .scope generate, "ripple1[28]" "ripple1[28]" 2 140, 2 140 0, S_0x1927f50; + .timescale 0 0; +P_0x1935fa0 .param/l "j" 0 2 140, +C4<011100>; +L_0x19c7d00/d .functor XOR 1, v0x17bafe0_0, L_0x1992700, C4<0>, C4<0>; +L_0x19c7d00 .delay 1 (20,20,20) L_0x19c7d00/d; +S_0x1936040 .scope generate, "ripple1[29]" "ripple1[29]" 2 140, 2 140 0, S_0x1927f50; + .timescale 0 0; +P_0x1936210 .param/l "j" 0 2 140, +C4<011101>; +L_0x19c96b0/d .functor XOR 1, v0x17bafe0_0, L_0x1992a20, C4<0>, C4<0>; +L_0x19c96b0 .delay 1 (20,20,20) L_0x19c96b0/d; +S_0x19362b0 .scope generate, "ripple1[30]" "ripple1[30]" 2 140, 2 140 0, S_0x1927f50; + .timescale 0 0; +P_0x1936480 .param/l "j" 0 2 140, +C4<011110>; +L_0x19c97c0/d .functor XOR 1, v0x17bafe0_0, L_0x1992d50, C4<0>, C4<0>; +L_0x19c97c0 .delay 1 (20,20,20) L_0x19c97c0/d; +S_0x1936540 .scope generate, "ripple1[31]" "ripple1[31]" 2 140, 2 140 0, S_0x1927f50; + .timescale 0 0; +P_0x1936730 .param/l "j" 0 2 140, +C4<011111>; +L_0x19ca540/d .functor XOR 1, v0x17bafe0_0, L_0x19c64f0, C4<0>, C4<0>; +L_0x19ca540 .delay 1 (20,20,20) L_0x19ca540/d; +S_0x1939390 .scope module, "dut4" "NOROR" 2 261, 2 153 0, S_0x17ef170; + .timescale 0 0; + .port_info 0 /OUTPUT 32 "result" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /OUTPUT 1 "zero" + .port_info 3 /OUTPUT 1 "overflow" + .port_info 4 /INPUT 32 "operandA" + .port_info 5 /INPUT 32 "operandB" + .port_info 6 /INPUT 1 "invertnor" +L_0x7f93f4ea0330 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x19d4670 .functor BUF 1, L_0x7f93f4ea0330, C4<0>, C4<0>, C4<0>; +L_0x7f93f4ea0378 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x19d47d0 .functor BUF 1, L_0x7f93f4ea0378, C4<0>, C4<0>, C4<0>; +L_0x7f93f4ea03c0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x19d48e0 .functor BUF 1, L_0x7f93f4ea03c0, C4<0>, C4<0>, C4<0>; +v0x1947fa0_0 .net *"_s100", 0 0, L_0x19d22d0; 1 drivers +v0x1948080_0 .net *"_s102", 0 0, L_0x19d2430; 1 drivers +v0x1948160_0 .net *"_s104", 0 0, L_0x19d2590; 1 drivers +v0x1948220_0 .net *"_s106", 0 0, L_0x19d26f0; 1 drivers +v0x1948300_0 .net *"_s108", 0 0, L_0x19d2850; 1 drivers +v0x1948430_0 .net *"_s110", 0 0, L_0x19d29b0; 1 drivers +v0x1948510_0 .net *"_s112", 0 0, L_0x19d2b10; 1 drivers +v0x19485f0_0 .net *"_s114", 0 0, L_0x19d2c70; 1 drivers +v0x19486d0_0 .net *"_s116", 0 0, L_0x19d2dd0; 1 drivers +v0x1948840_0 .net *"_s118", 0 0, L_0x19d2f30; 1 drivers +v0x1948920_0 .net *"_s120", 0 0, L_0x19c92a0; 1 drivers +v0x1948a00_0 .net *"_s122", 0 0, L_0x19c9400; 1 drivers +v0x1948ae0_0 .net *"_s124", 0 0, L_0x19c9560; 1 drivers +v0x1948bc0_0 .net *"_s126", 0 0, L_0x19d4510; 1 drivers +v0x1948ca0_0 .net/2u *"_s129", 0 0, L_0x7f93f4ea0330; 1 drivers +v0x1948d80_0 .net/2u *"_s131", 0 0, L_0x7f93f4ea0378; 1 drivers +v0x1948e60_0 .net/2u *"_s133", 0 0, L_0x7f93f4ea03c0; 1 drivers +v0x1949010_0 .net *"_s64", 0 0, L_0x19d06e0; 1 drivers +v0x19490b0_0 .net *"_s66", 0 0, L_0x19d0840; 1 drivers +v0x1949190_0 .net *"_s68", 0 0, L_0x19d0cd0; 1 drivers +v0x1949270_0 .net *"_s70", 0 0, L_0x19d0e30; 1 drivers +v0x1949350_0 .net *"_s72", 0 0, L_0x19d0f90; 1 drivers +v0x1949430_0 .net *"_s74", 0 0, L_0x19d10f0; 1 drivers +v0x1949510_0 .net *"_s76", 0 0, L_0x19d1250; 1 drivers +v0x19495f0_0 .net *"_s78", 0 0, L_0x19d13b0; 1 drivers +v0x19496d0_0 .net *"_s80", 0 0, L_0x19d1510; 1 drivers +v0x19497b0_0 .net *"_s82", 0 0, L_0x19d1670; 1 drivers +v0x1949890_0 .net *"_s84", 0 0, L_0x19d17d0; 1 drivers +v0x1949970_0 .net *"_s86", 0 0, L_0x19d1930; 1 drivers +v0x1949a50_0 .net *"_s88", 0 0, L_0x19d1a90; 1 drivers +v0x1949b30_0 .net *"_s90", 0 0, L_0x19d1bf0; 1 drivers +v0x1949c10_0 .net *"_s92", 0 0, L_0x19d1d50; 1 drivers +v0x1949cf0_0 .net *"_s94", 0 0, L_0x19d1eb0; 1 drivers +v0x1948f40_0 .net *"_s96", 0 0, L_0x19d2010; 1 drivers +v0x1949fc0_0 .net *"_s98", 0 0, L_0x19d2170; 1 drivers +v0x194a0a0_0 .net "carryout", 0 0, L_0x19d4670; alias, 1 drivers +v0x194a160_0 .net "invertnor", 0 0, v0x17bafe0_0; alias, 1 drivers +v0x194a200 .array "norres", 0 31; +v0x194a200_0 .net v0x194a200 0, 0 0, L_0x19ca850; 1 drivers +v0x194a200_1 .net v0x194a200 1, 0 0, L_0x19cab60; 1 drivers +v0x194a200_2 .net v0x194a200 2, 0 0, L_0x19cae70; 1 drivers +v0x194a200_3 .net v0x194a200 3, 0 0, L_0x19cb180; 1 drivers +v0x194a200_4 .net v0x194a200 4, 0 0, L_0x19cb4e0; 1 drivers +v0x194a200_5 .net v0x194a200 5, 0 0, L_0x19cb850; 1 drivers +v0x194a200_6 .net v0x194a200 6, 0 0, L_0x19cbb80; 1 drivers +v0x194a200_7 .net v0x194a200 7, 0 0, L_0x19cbb10; 1 drivers +v0x194a200_8 .net v0x194a200 8, 0 0, L_0x19cc240; 1 drivers +v0x194a200_9 .net v0x194a200 9, 0 0, L_0x19cc1b0; 1 drivers +v0x194a200_10 .net v0x194a200 10, 0 0, L_0x19cc550; 1 drivers +v0x194a200_11 .net v0x194a200 11, 0 0, L_0x19cc890; 1 drivers +v0x194a200_12 .net v0x194a200 12, 0 0, L_0x19ccbe0; 1 drivers +v0x194a200_13 .net v0x194a200 13, 0 0, L_0x19ccf40; 1 drivers +v0x194a200_14 .net v0x194a200 14, 0 0, L_0x19cd260; 1 drivers +v0x194a200_15 .net v0x194a200 15, 0 0, L_0x19cd590; 1 drivers +v0x194a200_16 .net v0x194a200 16, 0 0, L_0x19cd8d0; 1 drivers +v0x194a200_17 .net v0x194a200 17, 0 0, L_0x19cdc20; 1 drivers +v0x194a200_18 .net v0x194a200 18, 0 0, L_0x19cbe90; 1 drivers +v0x194a200_19 .net v0x194a200 19, 0 0, L_0x19cdf80; 1 drivers +v0x194a200_20 .net v0x194a200 20, 0 0, L_0x19ce240; 1 drivers +v0x194a200_21 .net v0x194a200 21, 0 0, L_0x19ce560; 1 drivers +v0x194a200_22 .net v0x194a200 22, 0 0, L_0x19ce890; 1 drivers +v0x194a200_23 .net v0x194a200 23, 0 0, L_0x19ceb80; 1 drivers +v0x194a200_24 .net v0x194a200 24, 0 0, L_0x19cee80; 1 drivers +v0x194a200_25 .net v0x194a200 25, 0 0, L_0x19cf190; 1 drivers +v0x194a200_26 .net v0x194a200 26, 0 0, L_0x19cf460; 1 drivers +v0x194a200_27 .net v0x194a200 27, 0 0, L_0x19cf790; 1 drivers +v0x194a200_28 .net v0x194a200 28, 0 0, L_0x19cfad0; 1 drivers +v0x194a200_29 .net v0x194a200 29, 0 0, L_0x19cfd80; 1 drivers +v0x194a200_30 .net v0x194a200 30, 0 0, L_0x19d0090; 1 drivers +v0x194a200_31 .net v0x194a200 31, 0 0, L_0x19d03b0; 1 drivers +v0x194a7b0_0 .net "operandA", 31 0, o0x7f93f4eeeb98; alias, 0 drivers +v0x194a870_0 .net "operandB", 31 0, o0x7f93f4eeebc8; alias, 0 drivers +v0x194a930_0 .net "overflow", 0 0, L_0x19d48e0; alias, 1 drivers +v0x194a9f0_0 .net "result", 31 0, L_0x19d38f0; alias, 1 drivers +v0x194aad0_0 .net "zero", 0 0, L_0x19d47d0; alias, 1 drivers +L_0x19ca910 .part o0x7f93f4eeeb98, 0, 1; +L_0x19caa70 .part o0x7f93f4eeebc8, 0, 1; +L_0x19cac20 .part o0x7f93f4eeeb98, 1, 1; +L_0x19cad80 .part o0x7f93f4eeebc8, 1, 1; +L_0x19caf30 .part o0x7f93f4eeeb98, 2, 1; +L_0x19cb090 .part o0x7f93f4eeebc8, 2, 1; +L_0x19cb240 .part o0x7f93f4eeeb98, 3, 1; +L_0x19cb3a0 .part o0x7f93f4eeebc8, 3, 1; +L_0x19cb5a0 .part o0x7f93f4eeeb98, 4, 1; +L_0x19cb700 .part o0x7f93f4eeebc8, 4, 1; +L_0x19cb8c0 .part o0x7f93f4eeeb98, 5, 1; +L_0x19cba20 .part o0x7f93f4eeebc8, 5, 1; +L_0x19cbc40 .part o0x7f93f4eeeb98, 6, 1; +L_0x19cbda0 .part o0x7f93f4eeebc8, 6, 1; +L_0x19cbf60 .part o0x7f93f4eeeb98, 7, 1; +L_0x19cc0c0 .part o0x7f93f4eeebc8, 7, 1; +L_0x19cc300 .part o0x7f93f4eeeb98, 8, 1; +L_0x19cc460 .part o0x7f93f4eeebc8, 8, 1; +L_0x19cc640 .part o0x7f93f4eeeb98, 9, 1; +L_0x19cc7a0 .part o0x7f93f4eeebc8, 9, 1; +L_0x19cc990 .part o0x7f93f4eeeb98, 10, 1; +L_0x19ccaf0 .part o0x7f93f4eeebc8, 10, 1; +L_0x19cccf0 .part o0x7f93f4eeeb98, 11, 1; +L_0x19cce50 .part o0x7f93f4eeebc8, 11, 1; +L_0x19cd010 .part o0x7f93f4eeeb98, 12, 1; +L_0x19cd170 .part o0x7f93f4eeebc8, 12, 1; +L_0x19cd340 .part o0x7f93f4eeeb98, 13, 1; +L_0x19cd4a0 .part o0x7f93f4eeebc8, 13, 1; +L_0x19cd680 .part o0x7f93f4eeeb98, 14, 1; +L_0x19cd7e0 .part o0x7f93f4eeebc8, 14, 1; +L_0x19cd9d0 .part o0x7f93f4eeeb98, 15, 1; +L_0x19cdb30 .part o0x7f93f4eeebc8, 15, 1; +L_0x19cdd30 .part o0x7f93f4eeeb98, 16, 1; +L_0x19cde90 .part o0x7f93f4eeebc8, 16, 1; +L_0x194a3d0 .part o0x7f93f4eeeb98, 17, 1; +L_0x194a4c0 .part o0x7f93f4eeebc8, 17, 1; +L_0x19ce0b0 .part o0x7f93f4eeeb98, 18, 1; +L_0x19ce150 .part o0x7f93f4eeebc8, 18, 1; +L_0x19ce380 .part o0x7f93f4eeeb98, 19, 1; +L_0x19ce470 .part o0x7f93f4eeebc8, 19, 1; +L_0x19ce6b0 .part o0x7f93f4eeeb98, 20, 1; +L_0x19ce7a0 .part o0x7f93f4eeebc8, 20, 1; +L_0x19ce9f0 .part o0x7f93f4eeeb98, 21, 1; +L_0x19cea90 .part o0x7f93f4eeebc8, 21, 1; +L_0x19cecf0 .part o0x7f93f4eeeb98, 22, 1; +L_0x19ced90 .part o0x7f93f4eeebc8, 22, 1; +L_0x19cf000 .part o0x7f93f4eeeb98, 23, 1; +L_0x19cf0a0 .part o0x7f93f4eeebc8, 23, 1; +L_0x19cf320 .part o0x7f93f4eeeb98, 24, 1; +L_0x19cf3c0 .part o0x7f93f4eeebc8, 24, 1; +L_0x19cf600 .part o0x7f93f4eeeb98, 25, 1; +L_0x19cf6a0 .part o0x7f93f4eeebc8, 25, 1; +L_0x19cf940 .part o0x7f93f4eeeb98, 26, 1; +L_0x19cf9e0 .part o0x7f93f4eeebc8, 26, 1; +L_0x19cf8a0 .part o0x7f93f4eeeb98, 27, 1; +L_0x19cfc90 .part o0x7f93f4eeebc8, 27, 1; +L_0x19cfbe0 .part o0x7f93f4eeeb98, 28, 1; +L_0x19cffa0 .part o0x7f93f4eeebc8, 28, 1; +L_0x19cfe40 .part o0x7f93f4eeeb98, 29, 1; +L_0x19d02c0 .part o0x7f93f4eeebc8, 29, 1; +L_0x19d0150 .part o0x7f93f4eeeb98, 30, 1; +L_0x19d05f0 .part o0x7f93f4eeebc8, 30, 1; +L_0x19d0470 .part o0x7f93f4eeeb98, 31, 1; +L_0x19d0930 .part o0x7f93f4eeebc8, 31, 1; +LS_0x19d38f0_0_0 .concat8 [ 1 1 1 1], L_0x19d06e0, L_0x19d0840, L_0x19d0cd0, L_0x19d0e30; +LS_0x19d38f0_0_4 .concat8 [ 1 1 1 1], L_0x19d0f90, L_0x19d10f0, L_0x19d1250, L_0x19d13b0; +LS_0x19d38f0_0_8 .concat8 [ 1 1 1 1], L_0x19d1510, L_0x19d1670, L_0x19d17d0, L_0x19d1930; +LS_0x19d38f0_0_12 .concat8 [ 1 1 1 1], L_0x19d1a90, L_0x19d1bf0, L_0x19d1d50, L_0x19d1eb0; +LS_0x19d38f0_0_16 .concat8 [ 1 1 1 1], L_0x19d2010, L_0x19d2170, L_0x19d22d0, L_0x19d2430; +LS_0x19d38f0_0_20 .concat8 [ 1 1 1 1], L_0x19d2590, L_0x19d26f0, L_0x19d2850, L_0x19d29b0; +LS_0x19d38f0_0_24 .concat8 [ 1 1 1 1], L_0x19d2b10, L_0x19d2c70, L_0x19d2dd0, L_0x19d2f30; +LS_0x19d38f0_0_28 .concat8 [ 1 1 1 1], L_0x19c92a0, L_0x19c9400, L_0x19c9560, L_0x19d4510; +LS_0x19d38f0_1_0 .concat8 [ 4 4 4 4], LS_0x19d38f0_0_0, LS_0x19d38f0_0_4, LS_0x19d38f0_0_8, LS_0x19d38f0_0_12; +LS_0x19d38f0_1_4 .concat8 [ 4 4 4 4], LS_0x19d38f0_0_16, LS_0x19d38f0_0_20, LS_0x19d38f0_0_24, LS_0x19d38f0_0_28; +L_0x19d38f0 .concat8 [ 16 16 0 0], LS_0x19d38f0_1_0, LS_0x19d38f0_1_4; +S_0x19395c0 .scope generate, "genblk1[0]" "genblk1[0]" 2 166, 2 166 0, S_0x1939390; + .timescale 0 0; +P_0x1939780 .param/l "i" 0 2 166, +C4<00>; +L_0x19ca850/d .functor NOR 1, L_0x19ca910, L_0x19caa70, C4<0>, C4<0>; +L_0x19ca850 .delay 1 (10,10,10) L_0x19ca850/d; +v0x1939860_0 .net *"_s1", 0 0, L_0x19ca910; 1 drivers +v0x1939940_0 .net *"_s2", 0 0, L_0x19caa70; 1 drivers +S_0x1939a20 .scope generate, "genblk1[1]" "genblk1[1]" 2 166, 2 166 0, S_0x1939390; + .timescale 0 0; +P_0x1939c30 .param/l "i" 0 2 166, +C4<01>; +L_0x19cab60/d .functor NOR 1, L_0x19cac20, L_0x19cad80, C4<0>, C4<0>; +L_0x19cab60 .delay 1 (10,10,10) L_0x19cab60/d; +v0x1939cf0_0 .net *"_s1", 0 0, L_0x19cac20; 1 drivers +v0x1939dd0_0 .net *"_s2", 0 0, L_0x19cad80; 1 drivers +S_0x1939eb0 .scope generate, "genblk1[2]" "genblk1[2]" 2 166, 2 166 0, S_0x1939390; + .timescale 0 0; +P_0x193a0c0 .param/l "i" 0 2 166, +C4<010>; +L_0x19cae70/d .functor NOR 1, L_0x19caf30, L_0x19cb090, C4<0>, C4<0>; +L_0x19cae70 .delay 1 (10,10,10) L_0x19cae70/d; +v0x193a160_0 .net *"_s1", 0 0, L_0x19caf30; 1 drivers +v0x193a240_0 .net *"_s2", 0 0, L_0x19cb090; 1 drivers +S_0x193a320 .scope generate, "genblk1[3]" "genblk1[3]" 2 166, 2 166 0, S_0x1939390; + .timescale 0 0; +P_0x193a530 .param/l "i" 0 2 166, +C4<011>; +L_0x19cb180/d .functor NOR 1, L_0x19cb240, L_0x19cb3a0, C4<0>, C4<0>; +L_0x19cb180 .delay 1 (10,10,10) L_0x19cb180/d; +v0x193a5f0_0 .net *"_s1", 0 0, L_0x19cb240; 1 drivers +v0x193a6d0_0 .net *"_s2", 0 0, L_0x19cb3a0; 1 drivers +S_0x193a7b0 .scope generate, "genblk1[4]" "genblk1[4]" 2 166, 2 166 0, S_0x1939390; + .timescale 0 0; +P_0x193aa10 .param/l "i" 0 2 166, +C4<0100>; +L_0x19cb4e0/d .functor NOR 1, L_0x19cb5a0, L_0x19cb700, C4<0>, C4<0>; +L_0x19cb4e0 .delay 1 (10,10,10) L_0x19cb4e0/d; +v0x193aad0_0 .net *"_s1", 0 0, L_0x19cb5a0; 1 drivers +v0x193abb0_0 .net *"_s2", 0 0, L_0x19cb700; 1 drivers +S_0x193ac90 .scope generate, "genblk1[5]" "genblk1[5]" 2 166, 2 166 0, S_0x1939390; + .timescale 0 0; +P_0x193aea0 .param/l "i" 0 2 166, +C4<0101>; +L_0x19cb850/d .functor NOR 1, L_0x19cb8c0, L_0x19cba20, C4<0>, C4<0>; +L_0x19cb850 .delay 1 (10,10,10) L_0x19cb850/d; +v0x193af60_0 .net *"_s1", 0 0, L_0x19cb8c0; 1 drivers +v0x193b040_0 .net *"_s2", 0 0, L_0x19cba20; 1 drivers +S_0x193b120 .scope generate, "genblk1[6]" "genblk1[6]" 2 166, 2 166 0, S_0x1939390; + .timescale 0 0; +P_0x193b330 .param/l "i" 0 2 166, +C4<0110>; +L_0x19cbb80/d .functor NOR 1, L_0x19cbc40, L_0x19cbda0, C4<0>, C4<0>; +L_0x19cbb80 .delay 1 (10,10,10) L_0x19cbb80/d; +v0x193b3f0_0 .net *"_s1", 0 0, L_0x19cbc40; 1 drivers +v0x193b4d0_0 .net *"_s2", 0 0, L_0x19cbda0; 1 drivers +S_0x193b5b0 .scope generate, "genblk1[7]" "genblk1[7]" 2 166, 2 166 0, S_0x1939390; + .timescale 0 0; +P_0x193b7c0 .param/l "i" 0 2 166, +C4<0111>; +L_0x19cbb10/d .functor NOR 1, L_0x19cbf60, L_0x19cc0c0, C4<0>, C4<0>; +L_0x19cbb10 .delay 1 (10,10,10) L_0x19cbb10/d; +v0x193b880_0 .net *"_s1", 0 0, L_0x19cbf60; 1 drivers +v0x193b960_0 .net *"_s2", 0 0, L_0x19cc0c0; 1 drivers +S_0x193ba40 .scope generate, "genblk1[8]" "genblk1[8]" 2 166, 2 166 0, S_0x1939390; + .timescale 0 0; +P_0x193a9c0 .param/l "i" 0 2 166, +C4<01000>; +L_0x19cc240/d .functor NOR 1, L_0x19cc300, L_0x19cc460, C4<0>, C4<0>; +L_0x19cc240 .delay 1 (10,10,10) L_0x19cc240/d; +v0x193bd50_0 .net *"_s1", 0 0, L_0x19cc300; 1 drivers +v0x193be30_0 .net *"_s2", 0 0, L_0x19cc460; 1 drivers +S_0x193bf10 .scope generate, "genblk1[9]" "genblk1[9]" 2 166, 2 166 0, S_0x1939390; + .timescale 0 0; +P_0x193c120 .param/l "i" 0 2 166, +C4<01001>; +L_0x19cc1b0/d .functor NOR 1, L_0x19cc640, L_0x19cc7a0, C4<0>, C4<0>; +L_0x19cc1b0 .delay 1 (10,10,10) L_0x19cc1b0/d; +v0x193c1e0_0 .net *"_s1", 0 0, L_0x19cc640; 1 drivers +v0x193c2c0_0 .net *"_s2", 0 0, L_0x19cc7a0; 1 drivers +S_0x193c3a0 .scope generate, "genblk1[10]" "genblk1[10]" 2 166, 2 166 0, S_0x1939390; + .timescale 0 0; +P_0x193c5b0 .param/l "i" 0 2 166, +C4<01010>; +L_0x19cc550/d .functor NOR 1, L_0x19cc990, L_0x19ccaf0, C4<0>, C4<0>; +L_0x19cc550 .delay 1 (10,10,10) L_0x19cc550/d; +v0x193c670_0 .net *"_s1", 0 0, L_0x19cc990; 1 drivers +v0x193c750_0 .net *"_s2", 0 0, L_0x19ccaf0; 1 drivers +S_0x193c830 .scope generate, "genblk1[11]" "genblk1[11]" 2 166, 2 166 0, S_0x1939390; + .timescale 0 0; +P_0x193ca40 .param/l "i" 0 2 166, +C4<01011>; +L_0x19cc890/d .functor NOR 1, L_0x19cccf0, L_0x19cce50, C4<0>, C4<0>; +L_0x19cc890 .delay 1 (10,10,10) L_0x19cc890/d; +v0x193cb00_0 .net *"_s1", 0 0, L_0x19cccf0; 1 drivers +v0x193cbe0_0 .net *"_s2", 0 0, L_0x19cce50; 1 drivers +S_0x193ccc0 .scope generate, "genblk1[12]" "genblk1[12]" 2 166, 2 166 0, S_0x1939390; + .timescale 0 0; +P_0x193ced0 .param/l "i" 0 2 166, +C4<01100>; +L_0x19ccbe0/d .functor NOR 1, L_0x19cd010, L_0x19cd170, C4<0>, C4<0>; +L_0x19ccbe0 .delay 1 (10,10,10) L_0x19ccbe0/d; +v0x193cf90_0 .net *"_s1", 0 0, L_0x19cd010; 1 drivers +v0x193d070_0 .net *"_s2", 0 0, L_0x19cd170; 1 drivers +S_0x193d150 .scope generate, "genblk1[13]" "genblk1[13]" 2 166, 2 166 0, S_0x1939390; + .timescale 0 0; +P_0x193d360 .param/l "i" 0 2 166, +C4<01101>; +L_0x19ccf40/d .functor NOR 1, L_0x19cd340, L_0x19cd4a0, C4<0>, C4<0>; +L_0x19ccf40 .delay 1 (10,10,10) L_0x19ccf40/d; +v0x193d420_0 .net *"_s1", 0 0, L_0x19cd340; 1 drivers +v0x193d500_0 .net *"_s2", 0 0, L_0x19cd4a0; 1 drivers +S_0x193d5e0 .scope generate, "genblk1[14]" "genblk1[14]" 2 166, 2 166 0, S_0x1939390; + .timescale 0 0; +P_0x193d7f0 .param/l "i" 0 2 166, +C4<01110>; +L_0x19cd260/d .functor NOR 1, L_0x19cd680, L_0x19cd7e0, C4<0>, C4<0>; +L_0x19cd260 .delay 1 (10,10,10) L_0x19cd260/d; +v0x193d8b0_0 .net *"_s1", 0 0, L_0x19cd680; 1 drivers +v0x193d990_0 .net *"_s2", 0 0, L_0x19cd7e0; 1 drivers +S_0x193da70 .scope generate, "genblk1[15]" "genblk1[15]" 2 166, 2 166 0, S_0x1939390; + .timescale 0 0; +P_0x193dc80 .param/l "i" 0 2 166, +C4<01111>; +L_0x19cd590/d .functor NOR 1, L_0x19cd9d0, L_0x19cdb30, C4<0>, C4<0>; +L_0x19cd590 .delay 1 (10,10,10) L_0x19cd590/d; +v0x193dd40_0 .net *"_s1", 0 0, L_0x19cd9d0; 1 drivers +v0x193de20_0 .net *"_s2", 0 0, L_0x19cdb30; 1 drivers +S_0x193df00 .scope generate, "genblk1[16]" "genblk1[16]" 2 166, 2 166 0, S_0x1939390; + .timescale 0 0; +P_0x193bc50 .param/l "i" 0 2 166, +C4<010000>; +L_0x19cd8d0/d .functor NOR 1, L_0x19cdd30, L_0x19cde90, C4<0>, C4<0>; +L_0x19cd8d0 .delay 1 (10,10,10) L_0x19cd8d0/d; +v0x193e270_0 .net *"_s1", 0 0, L_0x19cdd30; 1 drivers +v0x193e330_0 .net *"_s2", 0 0, L_0x19cde90; 1 drivers +S_0x193e410 .scope generate, "genblk1[17]" "genblk1[17]" 2 166, 2 166 0, S_0x1939390; + .timescale 0 0; +P_0x193e620 .param/l "i" 0 2 166, +C4<010001>; +L_0x19cdc20/d .functor NOR 1, L_0x194a3d0, L_0x194a4c0, C4<0>, C4<0>; +L_0x19cdc20 .delay 1 (10,10,10) L_0x19cdc20/d; +v0x193e6e0_0 .net *"_s1", 0 0, L_0x194a3d0; 1 drivers +v0x193e7c0_0 .net *"_s2", 0 0, L_0x194a4c0; 1 drivers +S_0x193e8a0 .scope generate, "genblk1[18]" "genblk1[18]" 2 166, 2 166 0, S_0x1939390; + .timescale 0 0; +P_0x193eab0 .param/l "i" 0 2 166, +C4<010010>; +L_0x19cbe90/d .functor NOR 1, L_0x19ce0b0, L_0x19ce150, C4<0>, C4<0>; +L_0x19cbe90 .delay 1 (10,10,10) L_0x19cbe90/d; +v0x193eb70_0 .net *"_s1", 0 0, L_0x19ce0b0; 1 drivers +v0x193ec50_0 .net *"_s2", 0 0, L_0x19ce150; 1 drivers +S_0x193ed30 .scope generate, "genblk1[19]" "genblk1[19]" 2 166, 2 166 0, S_0x1939390; + .timescale 0 0; +P_0x193ef40 .param/l "i" 0 2 166, +C4<010011>; +L_0x19cdf80/d .functor NOR 1, L_0x19ce380, L_0x19ce470, C4<0>, C4<0>; +L_0x19cdf80 .delay 1 (10,10,10) L_0x19cdf80/d; +v0x193f000_0 .net *"_s1", 0 0, L_0x19ce380; 1 drivers +v0x193f0e0_0 .net *"_s2", 0 0, L_0x19ce470; 1 drivers +S_0x193f1c0 .scope generate, "genblk1[20]" "genblk1[20]" 2 166, 2 166 0, S_0x1939390; + .timescale 0 0; +P_0x193f3d0 .param/l "i" 0 2 166, +C4<010100>; +L_0x19ce240/d .functor NOR 1, L_0x19ce6b0, L_0x19ce7a0, C4<0>, C4<0>; +L_0x19ce240 .delay 1 (10,10,10) L_0x19ce240/d; +v0x193f490_0 .net *"_s1", 0 0, L_0x19ce6b0; 1 drivers +v0x193f570_0 .net *"_s2", 0 0, L_0x19ce7a0; 1 drivers +S_0x193f650 .scope generate, "genblk1[21]" "genblk1[21]" 2 166, 2 166 0, S_0x1939390; + .timescale 0 0; +P_0x193f860 .param/l "i" 0 2 166, +C4<010101>; +L_0x19ce560/d .functor NOR 1, L_0x19ce9f0, L_0x19cea90, C4<0>, C4<0>; +L_0x19ce560 .delay 1 (10,10,10) L_0x19ce560/d; +v0x193f920_0 .net *"_s1", 0 0, L_0x19ce9f0; 1 drivers +v0x193fa00_0 .net *"_s2", 0 0, L_0x19cea90; 1 drivers +S_0x193fae0 .scope generate, "genblk1[22]" "genblk1[22]" 2 166, 2 166 0, S_0x1939390; + .timescale 0 0; +P_0x193fcf0 .param/l "i" 0 2 166, +C4<010110>; +L_0x19ce890/d .functor NOR 1, L_0x19cecf0, L_0x19ced90, C4<0>, C4<0>; +L_0x19ce890 .delay 1 (10,10,10) L_0x19ce890/d; +v0x193fdb0_0 .net *"_s1", 0 0, L_0x19cecf0; 1 drivers +v0x193fe90_0 .net *"_s2", 0 0, L_0x19ced90; 1 drivers +S_0x193ff70 .scope generate, "genblk1[23]" "genblk1[23]" 2 166, 2 166 0, S_0x1939390; + .timescale 0 0; +P_0x1940180 .param/l "i" 0 2 166, +C4<010111>; +L_0x19ceb80/d .functor NOR 1, L_0x19cf000, L_0x19cf0a0, C4<0>, C4<0>; +L_0x19ceb80 .delay 1 (10,10,10) L_0x19ceb80/d; +v0x1940240_0 .net *"_s1", 0 0, L_0x19cf000; 1 drivers +v0x1940320_0 .net *"_s2", 0 0, L_0x19cf0a0; 1 drivers +S_0x1940400 .scope generate, "genblk1[24]" "genblk1[24]" 2 166, 2 166 0, S_0x1939390; + .timescale 0 0; +P_0x1940610 .param/l "i" 0 2 166, +C4<011000>; +L_0x19cee80/d .functor NOR 1, L_0x19cf320, L_0x19cf3c0, C4<0>, C4<0>; +L_0x19cee80 .delay 1 (10,10,10) L_0x19cee80/d; +v0x19406d0_0 .net *"_s1", 0 0, L_0x19cf320; 1 drivers +v0x19407b0_0 .net *"_s2", 0 0, L_0x19cf3c0; 1 drivers +S_0x1940890 .scope generate, "genblk1[25]" "genblk1[25]" 2 166, 2 166 0, S_0x1939390; + .timescale 0 0; +P_0x1940aa0 .param/l "i" 0 2 166, +C4<011001>; +L_0x19cf190/d .functor NOR 1, L_0x19cf600, L_0x19cf6a0, C4<0>, C4<0>; +L_0x19cf190 .delay 1 (10,10,10) L_0x19cf190/d; +v0x1940b60_0 .net *"_s1", 0 0, L_0x19cf600; 1 drivers +v0x1940c40_0 .net *"_s2", 0 0, L_0x19cf6a0; 1 drivers +S_0x1940d20 .scope generate, "genblk1[26]" "genblk1[26]" 2 166, 2 166 0, S_0x1939390; + .timescale 0 0; +P_0x1940f30 .param/l "i" 0 2 166, +C4<011010>; +L_0x19cf460/d .functor NOR 1, L_0x19cf940, L_0x19cf9e0, C4<0>, C4<0>; +L_0x19cf460 .delay 1 (10,10,10) L_0x19cf460/d; +v0x1940ff0_0 .net *"_s1", 0 0, L_0x19cf940; 1 drivers +v0x19410d0_0 .net *"_s2", 0 0, L_0x19cf9e0; 1 drivers +S_0x19411b0 .scope generate, "genblk1[27]" "genblk1[27]" 2 166, 2 166 0, S_0x1939390; + .timescale 0 0; +P_0x19413c0 .param/l "i" 0 2 166, +C4<011011>; +L_0x19cf790/d .functor NOR 1, L_0x19cf8a0, L_0x19cfc90, C4<0>, C4<0>; +L_0x19cf790 .delay 1 (10,10,10) L_0x19cf790/d; +v0x1941480_0 .net *"_s1", 0 0, L_0x19cf8a0; 1 drivers +v0x1941560_0 .net *"_s2", 0 0, L_0x19cfc90; 1 drivers +S_0x1941640 .scope generate, "genblk1[28]" "genblk1[28]" 2 166, 2 166 0, S_0x1939390; + .timescale 0 0; +P_0x1941850 .param/l "i" 0 2 166, +C4<011100>; +L_0x19cfad0/d .functor NOR 1, L_0x19cfbe0, L_0x19cffa0, C4<0>, C4<0>; +L_0x19cfad0 .delay 1 (10,10,10) L_0x19cfad0/d; +v0x1941910_0 .net *"_s1", 0 0, L_0x19cfbe0; 1 drivers +v0x19419f0_0 .net *"_s2", 0 0, L_0x19cffa0; 1 drivers +S_0x1941ad0 .scope generate, "genblk1[29]" "genblk1[29]" 2 166, 2 166 0, S_0x1939390; + .timescale 0 0; +P_0x1941ce0 .param/l "i" 0 2 166, +C4<011101>; +L_0x19cfd80/d .functor NOR 1, L_0x19cfe40, L_0x19d02c0, C4<0>, C4<0>; +L_0x19cfd80 .delay 1 (10,10,10) L_0x19cfd80/d; +v0x1941da0_0 .net *"_s1", 0 0, L_0x19cfe40; 1 drivers +v0x1941e80_0 .net *"_s2", 0 0, L_0x19d02c0; 1 drivers +S_0x1941f60 .scope generate, "genblk1[30]" "genblk1[30]" 2 166, 2 166 0, S_0x1939390; + .timescale 0 0; +P_0x1942170 .param/l "i" 0 2 166, +C4<011110>; +L_0x19d0090/d .functor NOR 1, L_0x19d0150, L_0x19d05f0, C4<0>, C4<0>; +L_0x19d0090 .delay 1 (10,10,10) L_0x19d0090/d; +v0x1942230_0 .net *"_s1", 0 0, L_0x19d0150; 1 drivers +v0x1942310_0 .net *"_s2", 0 0, L_0x19d05f0; 1 drivers +S_0x19423f0 .scope generate, "genblk1[31]" "genblk1[31]" 2 166, 2 166 0, S_0x1939390; + .timescale 0 0; +P_0x1942600 .param/l "i" 0 2 166, +C4<011111>; +L_0x19d03b0/d .functor NOR 1, L_0x19d0470, L_0x19d0930, C4<0>, C4<0>; +L_0x19d03b0 .delay 1 (10,10,10) L_0x19d03b0/d; +v0x19426c0_0 .net *"_s1", 0 0, L_0x19d0470; 1 drivers +v0x19427a0_0 .net *"_s2", 0 0, L_0x19d0930; 1 drivers +S_0x1942880 .scope generate, "genblk2[0]" "genblk2[0]" 2 171, 2 171 0, S_0x1939390; + .timescale 0 0; +P_0x193e110 .param/l "j" 0 2 171, +C4<00>; +L_0x19d06e0/d .functor XOR 1, v0x17bafe0_0, L_0x19ca850, C4<0>, C4<0>; +L_0x19d06e0 .delay 1 (20,20,20) L_0x19d06e0/d; +S_0x1942ca0 .scope generate, "genblk2[1]" "genblk2[1]" 2 171, 2 171 0, S_0x1939390; + .timescale 0 0; +P_0x1942e40 .param/l "j" 0 2 171, +C4<01>; +L_0x19d0840/d .functor XOR 1, v0x17bafe0_0, L_0x19cab60, C4<0>, C4<0>; +L_0x19d0840 .delay 1 (20,20,20) L_0x19d0840/d; +S_0x1942f00 .scope generate, "genblk2[2]" "genblk2[2]" 2 171, 2 171 0, S_0x1939390; + .timescale 0 0; +P_0x19430f0 .param/l "j" 0 2 171, +C4<010>; +L_0x19d0cd0/d .functor XOR 1, v0x17bafe0_0, L_0x19cae70, C4<0>, C4<0>; +L_0x19d0cd0 .delay 1 (20,20,20) L_0x19d0cd0/d; +S_0x19431b0 .scope generate, "genblk2[3]" "genblk2[3]" 2 171, 2 171 0, S_0x1939390; + .timescale 0 0; +P_0x19433a0 .param/l "j" 0 2 171, +C4<011>; +L_0x19d0e30/d .functor XOR 1, v0x17bafe0_0, L_0x19cb180, C4<0>, C4<0>; +L_0x19d0e30 .delay 1 (20,20,20) L_0x19d0e30/d; +S_0x1943460 .scope generate, "genblk2[4]" "genblk2[4]" 2 171, 2 171 0, S_0x1939390; + .timescale 0 0; +P_0x1943650 .param/l "j" 0 2 171, +C4<0100>; +L_0x19d0f90/d .functor XOR 1, v0x17bafe0_0, L_0x19cb4e0, C4<0>, C4<0>; +L_0x19d0f90 .delay 1 (20,20,20) L_0x19d0f90/d; +S_0x1943710 .scope generate, "genblk2[5]" "genblk2[5]" 2 171, 2 171 0, S_0x1939390; + .timescale 0 0; +P_0x1943900 .param/l "j" 0 2 171, +C4<0101>; +L_0x19d10f0/d .functor XOR 1, v0x17bafe0_0, L_0x19cb850, C4<0>, C4<0>; +L_0x19d10f0 .delay 1 (20,20,20) L_0x19d10f0/d; +S_0x19439c0 .scope generate, "genblk2[6]" "genblk2[6]" 2 171, 2 171 0, S_0x1939390; + .timescale 0 0; +P_0x1943bb0 .param/l "j" 0 2 171, +C4<0110>; +L_0x19d1250/d .functor XOR 1, v0x17bafe0_0, L_0x19cbb80, C4<0>, C4<0>; +L_0x19d1250 .delay 1 (20,20,20) L_0x19d1250/d; +S_0x1943c70 .scope generate, "genblk2[7]" "genblk2[7]" 2 171, 2 171 0, S_0x1939390; + .timescale 0 0; +P_0x1943e60 .param/l "j" 0 2 171, +C4<0111>; +L_0x19d13b0/d .functor XOR 1, v0x17bafe0_0, L_0x19cbb10, C4<0>, C4<0>; +L_0x19d13b0 .delay 1 (20,20,20) L_0x19d13b0/d; +S_0x1943f20 .scope generate, "genblk2[8]" "genblk2[8]" 2 171, 2 171 0, S_0x1939390; + .timescale 0 0; +P_0x1944110 .param/l "j" 0 2 171, +C4<01000>; +L_0x19d1510/d .functor XOR 1, v0x17bafe0_0, L_0x19cc240, C4<0>, C4<0>; +L_0x19d1510 .delay 1 (20,20,20) L_0x19d1510/d; +S_0x19441d0 .scope generate, "genblk2[9]" "genblk2[9]" 2 171, 2 171 0, S_0x1939390; + .timescale 0 0; +P_0x19443c0 .param/l "j" 0 2 171, +C4<01001>; +L_0x19d1670/d .functor XOR 1, v0x17bafe0_0, L_0x19cc1b0, C4<0>, C4<0>; +L_0x19d1670 .delay 1 (20,20,20) L_0x19d1670/d; +S_0x1944480 .scope generate, "genblk2[10]" "genblk2[10]" 2 171, 2 171 0, S_0x1939390; + .timescale 0 0; +P_0x1944670 .param/l "j" 0 2 171, +C4<01010>; +L_0x19d17d0/d .functor XOR 1, v0x17bafe0_0, L_0x19cc550, C4<0>, C4<0>; +L_0x19d17d0 .delay 1 (20,20,20) L_0x19d17d0/d; +S_0x1944730 .scope generate, "genblk2[11]" "genblk2[11]" 2 171, 2 171 0, S_0x1939390; + .timescale 0 0; +P_0x1944920 .param/l "j" 0 2 171, +C4<01011>; +L_0x19d1930/d .functor XOR 1, v0x17bafe0_0, L_0x19cc890, C4<0>, C4<0>; +L_0x19d1930 .delay 1 (20,20,20) L_0x19d1930/d; +S_0x19449e0 .scope generate, "genblk2[12]" "genblk2[12]" 2 171, 2 171 0, S_0x1939390; + .timescale 0 0; +P_0x1944bd0 .param/l "j" 0 2 171, +C4<01100>; +L_0x19d1a90/d .functor XOR 1, v0x17bafe0_0, L_0x19ccbe0, C4<0>, C4<0>; +L_0x19d1a90 .delay 1 (20,20,20) L_0x19d1a90/d; +S_0x1944c90 .scope generate, "genblk2[13]" "genblk2[13]" 2 171, 2 171 0, S_0x1939390; + .timescale 0 0; +P_0x1944e80 .param/l "j" 0 2 171, +C4<01101>; +L_0x19d1bf0/d .functor XOR 1, v0x17bafe0_0, L_0x19ccf40, C4<0>, C4<0>; +L_0x19d1bf0 .delay 1 (20,20,20) L_0x19d1bf0/d; +S_0x1944f40 .scope generate, "genblk2[14]" "genblk2[14]" 2 171, 2 171 0, S_0x1939390; + .timescale 0 0; +P_0x1945130 .param/l "j" 0 2 171, +C4<01110>; +L_0x19d1d50/d .functor XOR 1, v0x17bafe0_0, L_0x19cd260, C4<0>, C4<0>; +L_0x19d1d50 .delay 1 (20,20,20) L_0x19d1d50/d; +S_0x19451f0 .scope generate, "genblk2[15]" "genblk2[15]" 2 171, 2 171 0, S_0x1939390; + .timescale 0 0; +P_0x19453e0 .param/l "j" 0 2 171, +C4<01111>; +L_0x19d1eb0/d .functor XOR 1, v0x17bafe0_0, L_0x19cd590, C4<0>, C4<0>; +L_0x19d1eb0 .delay 1 (20,20,20) L_0x19d1eb0/d; +S_0x19454a0 .scope generate, "genblk2[16]" "genblk2[16]" 2 171, 2 171 0, S_0x1939390; + .timescale 0 0; +P_0x1945690 .param/l "j" 0 2 171, +C4<010000>; +L_0x19d2010/d .functor XOR 1, v0x17bafe0_0, L_0x19cd8d0, C4<0>, C4<0>; +L_0x19d2010 .delay 1 (20,20,20) L_0x19d2010/d; +S_0x1945750 .scope generate, "genblk2[17]" "genblk2[17]" 2 171, 2 171 0, S_0x1939390; + .timescale 0 0; +P_0x1945940 .param/l "j" 0 2 171, +C4<010001>; +L_0x19d2170/d .functor XOR 1, v0x17bafe0_0, L_0x19cdc20, C4<0>, C4<0>; +L_0x19d2170 .delay 1 (20,20,20) L_0x19d2170/d; +S_0x1945a00 .scope generate, "genblk2[18]" "genblk2[18]" 2 171, 2 171 0, S_0x1939390; + .timescale 0 0; +P_0x1945bf0 .param/l "j" 0 2 171, +C4<010010>; +L_0x19d22d0/d .functor XOR 1, v0x17bafe0_0, L_0x19cbe90, C4<0>, C4<0>; +L_0x19d22d0 .delay 1 (20,20,20) L_0x19d22d0/d; +S_0x1945cb0 .scope generate, "genblk2[19]" "genblk2[19]" 2 171, 2 171 0, S_0x1939390; + .timescale 0 0; +P_0x1945ea0 .param/l "j" 0 2 171, +C4<010011>; +L_0x19d2430/d .functor XOR 1, v0x17bafe0_0, L_0x19cdf80, C4<0>, C4<0>; +L_0x19d2430 .delay 1 (20,20,20) L_0x19d2430/d; +S_0x1945f60 .scope generate, "genblk2[20]" "genblk2[20]" 2 171, 2 171 0, S_0x1939390; + .timescale 0 0; +P_0x1946150 .param/l "j" 0 2 171, +C4<010100>; +L_0x19d2590/d .functor XOR 1, v0x17bafe0_0, L_0x19ce240, C4<0>, C4<0>; +L_0x19d2590 .delay 1 (20,20,20) L_0x19d2590/d; +S_0x1946210 .scope generate, "genblk2[21]" "genblk2[21]" 2 171, 2 171 0, S_0x1939390; + .timescale 0 0; +P_0x1946400 .param/l "j" 0 2 171, +C4<010101>; +L_0x19d26f0/d .functor XOR 1, v0x17bafe0_0, L_0x19ce560, C4<0>, C4<0>; +L_0x19d26f0 .delay 1 (20,20,20) L_0x19d26f0/d; +S_0x19464c0 .scope generate, "genblk2[22]" "genblk2[22]" 2 171, 2 171 0, S_0x1939390; + .timescale 0 0; +P_0x19466b0 .param/l "j" 0 2 171, +C4<010110>; +L_0x19d2850/d .functor XOR 1, v0x17bafe0_0, L_0x19ce890, C4<0>, C4<0>; +L_0x19d2850 .delay 1 (20,20,20) L_0x19d2850/d; +S_0x1946770 .scope generate, "genblk2[23]" "genblk2[23]" 2 171, 2 171 0, S_0x1939390; + .timescale 0 0; +P_0x1946960 .param/l "j" 0 2 171, +C4<010111>; +L_0x19d29b0/d .functor XOR 1, v0x17bafe0_0, L_0x19ceb80, C4<0>, C4<0>; +L_0x19d29b0 .delay 1 (20,20,20) L_0x19d29b0/d; +S_0x1946a20 .scope generate, "genblk2[24]" "genblk2[24]" 2 171, 2 171 0, S_0x1939390; + .timescale 0 0; +P_0x1946c10 .param/l "j" 0 2 171, +C4<011000>; +L_0x19d2b10/d .functor XOR 1, v0x17bafe0_0, L_0x19cee80, C4<0>, C4<0>; +L_0x19d2b10 .delay 1 (20,20,20) L_0x19d2b10/d; +S_0x1946cd0 .scope generate, "genblk2[25]" "genblk2[25]" 2 171, 2 171 0, S_0x1939390; + .timescale 0 0; +P_0x1946ec0 .param/l "j" 0 2 171, +C4<011001>; +L_0x19d2c70/d .functor XOR 1, v0x17bafe0_0, L_0x19cf190, C4<0>, C4<0>; +L_0x19d2c70 .delay 1 (20,20,20) L_0x19d2c70/d; +S_0x1946f80 .scope generate, "genblk2[26]" "genblk2[26]" 2 171, 2 171 0, S_0x1939390; + .timescale 0 0; +P_0x1947170 .param/l "j" 0 2 171, +C4<011010>; +L_0x19d2dd0/d .functor XOR 1, v0x17bafe0_0, L_0x19cf460, C4<0>, C4<0>; +L_0x19d2dd0 .delay 1 (20,20,20) L_0x19d2dd0/d; +S_0x1947230 .scope generate, "genblk2[27]" "genblk2[27]" 2 171, 2 171 0, S_0x1939390; + .timescale 0 0; +P_0x1947420 .param/l "j" 0 2 171, +C4<011011>; +L_0x19d2f30/d .functor XOR 1, v0x17bafe0_0, L_0x19cf790, C4<0>, C4<0>; +L_0x19d2f30 .delay 1 (20,20,20) L_0x19d2f30/d; +S_0x19474e0 .scope generate, "genblk2[28]" "genblk2[28]" 2 171, 2 171 0, S_0x1939390; + .timescale 0 0; +P_0x19476d0 .param/l "j" 0 2 171, +C4<011100>; +L_0x19c92a0/d .functor XOR 1, v0x17bafe0_0, L_0x19cfad0, C4<0>, C4<0>; +L_0x19c92a0 .delay 1 (20,20,20) L_0x19c92a0/d; +S_0x1947790 .scope generate, "genblk2[29]" "genblk2[29]" 2 171, 2 171 0, S_0x1939390; + .timescale 0 0; +P_0x1947980 .param/l "j" 0 2 171, +C4<011101>; +L_0x19c9400/d .functor XOR 1, v0x17bafe0_0, L_0x19cfd80, C4<0>, C4<0>; +L_0x19c9400 .delay 1 (20,20,20) L_0x19c9400/d; +S_0x1947a40 .scope generate, "genblk2[30]" "genblk2[30]" 2 171, 2 171 0, S_0x1939390; + .timescale 0 0; +P_0x1947c30 .param/l "j" 0 2 171, +C4<011110>; +L_0x19c9560/d .functor XOR 1, v0x17bafe0_0, L_0x19d0090, C4<0>, C4<0>; +L_0x19c9560 .delay 1 (20,20,20) L_0x19c9560/d; +S_0x1947cf0 .scope generate, "genblk2[31]" "genblk2[31]" 2 171, 2 171 0, S_0x1939390; + .timescale 0 0; +P_0x1947ee0 .param/l "j" 0 2 171, +C4<011111>; +L_0x19d4510/d .functor XOR 1, v0x17bafe0_0, L_0x19d03b0, C4<0>, C4<0>; +L_0x19d4510 .delay 1 (20,20,20) L_0x19d4510/d; +S_0x17a8e00 .scope module, "TEST" "TEST" 2 295; + .timescale 0 0; +v0x1971940_0 .net "carryout", 0 0, L_0x19edfe0; 1 drivers +v0x1971a00_0 .var "operandA", 31 0; +v0x1971ac0_0 .var "operandB", 31 0; +v0x1971b60_0 .net "overflow", 0 0, L_0x19eda30; 1 drivers +v0x1971c00_0 .net "result", 31 0, L_0x19ee140; 1 drivers +v0x1971ca0_0 .net "zero", 0 0, L_0x19ea8b0; 1 drivers +S_0x194ccf0 .scope module, "add" "AddSub" 2 305, 2 32 0, S_0x17a8e00; + .timescale 0 0; + .port_info 0 /OUTPUT 32 "result" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /OUTPUT 1 "zero" + .port_info 3 /OUTPUT 1 "overflow" + .port_info 4 /INPUT 32 "operandA" + .port_info 5 /INPUT 32 "operandB" + .port_info 6 /INPUT 1 "subtract" +L_0x19eda30/d .functor XOR 1, L_0x19e7dc0, L_0x19edfe0, C4<0>, C4<0>; +L_0x19eda30 .delay 1 (20,20,20) L_0x19eda30/d; +L_0x19ef060/d .functor NOR 1, L_0x19ef1c0, L_0x19ea7c0, C4<0>, C4<0>; +L_0x19ef060 .delay 1 (10,10,10) L_0x19ef060/d; +o0x7f93f4f004d8 .functor BUFZ 1, C4; HiZ drive +L_0x19ea8b0/d .functor NOR 1, o0x7f93f4f004d8, L_0x19eed60, C4<0>, C4<0>; +L_0x19ea8b0 .delay 1 (10,10,10) L_0x19ea8b0/d; +v0x196fea0_0 .net *"_s166", 0 0, L_0x19ef1c0; 1 drivers +v0x196ffa0_0 .net *"_s168", 0 0, L_0x19ea7c0; 1 drivers +v0x1970080_0 .net *"_s172", 0 0, L_0x19eed60; 1 drivers +v0x1970170_0 .net "carryout", 0 0, L_0x19edfe0; alias, 1 drivers +v0x1970260 .array "carryoutmid", 0 30; +v0x1970260_0 .net v0x1970260 0, 0 0, L_0x19ed190; 1 drivers +v0x1970260_1 .net v0x1970260 1, 0 0, L_0x19d5030; 1 drivers +v0x1970260_2 .net v0x1970260 2, 0 0, L_0x19d5ab0; 1 drivers +v0x1970260_3 .net v0x1970260 3, 0 0, L_0x19d6490; 1 drivers +v0x1970260_4 .net v0x1970260 4, 0 0, L_0x19d6ed0; 1 drivers +v0x1970260_5 .net v0x1970260 5, 0 0, L_0x19d7900; 1 drivers +v0x1970260_6 .net v0x1970260 6, 0 0, L_0x19d82f0; 1 drivers +v0x1970260_7 .net v0x1970260 7, 0 0, L_0x19d8d40; 1 drivers +v0x1970260_8 .net v0x1970260 8, 0 0, L_0x19d9840; 1 drivers +v0x1970260_9 .net v0x1970260 9, 0 0, L_0x19da220; 1 drivers +v0x1970260_10 .net v0x1970260 10, 0 0, L_0x19dac30; 1 drivers +v0x1970260_11 .net v0x1970260 11, 0 0, L_0x19db650; 1 drivers +v0x1970260_12 .net v0x1970260 12, 0 0, L_0x19dc080; 1 drivers +v0x1970260_13 .net v0x1970260 13, 0 0, L_0x19dca70; 1 drivers +v0x1970260_14 .net v0x1970260 14, 0 0, L_0x19dd470; 1 drivers +v0x1970260_15 .net v0x1970260 15, 0 0, L_0x19dde80; 1 drivers +v0x1970260_16 .net v0x1970260 16, 0 0, L_0x1968d90; 1 drivers +v0x1970260_17 .net v0x1970260 17, 0 0, L_0x19df860; 1 drivers +v0x1970260_18 .net v0x1970260 18, 0 0, L_0x19e0260; 1 drivers +v0x1970260_19 .net v0x1970260 19, 0 0, L_0x19e0c70; 1 drivers +v0x1970260_20 .net v0x1970260 20, 0 0, L_0x19e16e0; 1 drivers +v0x1970260_21 .net v0x1970260 21, 0 0, L_0x19e2160; 1 drivers +v0x1970260_22 .net v0x1970260 22, 0 0, L_0x19e2b50; 1 drivers +v0x1970260_23 .net v0x1970260 23, 0 0, L_0x19e35a0; 1 drivers +v0x1970260_24 .net v0x1970260 24, 0 0, L_0x19e4000; 1 drivers +v0x1970260_25 .net v0x1970260 25, 0 0, L_0x19e4a70; 1 drivers +v0x1970260_26 .net v0x1970260 26, 0 0, L_0x19e54f0; 1 drivers +v0x1970260_27 .net v0x1970260 27, 0 0, L_0x19e5ee0; 1 drivers +v0x1970260_28 .net v0x1970260 28, 0 0, L_0x19e6930; 1 drivers +v0x1970260_29 .net v0x1970260 29, 0 0, L_0x19e7370; 1 drivers +v0x1970260_30 .net v0x1970260 30, 0 0, L_0x19e7dc0; 1 drivers +v0x1970db0_0 .net "operandA", 31 0, v0x1971a00_0; 1 drivers +v0x1970e70_0 .net "operandB", 31 0, v0x1971ac0_0; 1 drivers +v0x1970f50_0 .net "overflow", 0 0, L_0x19eda30; alias, 1 drivers +v0x1971010_0 .net "result", 31 0, L_0x19ee140; alias, 1 drivers +L_0x7f93f4ea0408 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +v0x1971180_0 .net "subtract", 0 0, L_0x7f93f4ea0408; 1 drivers +v0x1971220_0 .net "zero", 0 0, L_0x19ea8b0; alias, 1 drivers +v0x19712e0 .array "zeromid", 0 30; +v0x19712e0_0 .net v0x19712e0 0, 0 0, L_0x19ef060; 1 drivers +v0x19712e0_1 .net v0x19712e0 1, 0 0, L_0x19e7720; 1 drivers +v0x19712e0_2 .net v0x19712e0 2, 0 0, L_0x19e8400; 1 drivers +v0x19712e0_3 .net v0x19712e0 3, 0 0, L_0x19e8170; 1 drivers +v0x19712e0_4 .net v0x19712e0 4, 0 0, L_0x19e89a0; 1 drivers +v0x19712e0_5 .net v0x19712e0 5, 0 0, L_0x19e8670; 1 drivers +v0x19712e0_6 .net v0x19712e0 6, 0 0, L_0x19e8e20; 1 drivers +v0x19712e0_7 .net v0x19712e0 7, 0 0, L_0x19e8bc0; 1 drivers +v0x19712e0_8 .net v0x19712e0 8, 0 0, L_0x19e8910; 1 drivers +v0x19712e0_9 .net v0x19712e0 9, 0 0, L_0x19e9090; 1 drivers +v0x19712e0_10 .net v0x19712e0 10, 0 0, L_0x19e9890; 1 drivers +v0x19712e0_11 .net v0x19712e0 11, 0 0, L_0x19e9610; 1 drivers +v0x19712e0_12 .net v0x19712e0 12, 0 0, L_0x19e9d90; 1 drivers +v0x19712e0_13 .net v0x19712e0 13, 0 0, L_0x19e9b00; 1 drivers +v0x19712e0_14 .net v0x19712e0 14, 0 0, L_0x19ea2a0; 1 drivers +v0x19712e0_15 .net v0x19712e0 15, 0 0, L_0x19ea000; 1 drivers +v0x19712e0_16 .net v0x19712e0 16, 0 0, L_0x19e9300; 1 drivers +v0x19712e0_17 .net v0x19712e0 17, 0 0, L_0x19ea510; 1 drivers +v0x19712e0_18 .net v0x19712e0 18, 0 0, L_0x19ead80; 1 drivers +v0x19712e0_19 .net v0x19712e0 19, 0 0, L_0x19eaac0; 1 drivers +v0x19712e0_20 .net v0x19712e0 20, 0 0, L_0x19eb220; 1 drivers +v0x19712e0_21 .net v0x19712e0 21, 0 0, L_0x19eafa0; 1 drivers +v0x19712e0_22 .net v0x19712e0 22, 0 0, L_0x19eb720; 1 drivers +v0x19712e0_23 .net v0x19712e0 23, 0 0, L_0x19eb490; 1 drivers +v0x19712e0_24 .net v0x19712e0 24, 0 0, L_0x19ebc30; 1 drivers +v0x19712e0_25 .net v0x19712e0 25, 0 0, L_0x19eb990; 1 drivers +v0x19712e0_26 .net v0x19712e0 26, 0 0, L_0x19ec150; 1 drivers +v0x19712e0_27 .net v0x19712e0 27, 0 0, L_0x19ebea0; 1 drivers +v0x19712e0_28 .net v0x19712e0 28, 0 0, L_0x19ec680; 1 drivers +v0x19712e0_29 .net v0x19712e0 29, 0 0, L_0x19ec3c0; 1 drivers +v0x19712e0_30 .net v0x19712e0 30, 0 0, o0x7f93f4f004d8; 0 drivers +L_0x19d5190 .part v0x1971a00_0, 1, 1; +L_0x19d52f0 .part v0x1971ac0_0, 1, 1; +L_0x19d5c10 .part v0x1971a00_0, 2, 1; +L_0x19d5d70 .part v0x1971ac0_0, 2, 1; +L_0x19d65f0 .part v0x1971a00_0, 3, 1; +L_0x19d67e0 .part v0x1971ac0_0, 3, 1; +L_0x19d7030 .part v0x1971a00_0, 4, 1; +L_0x19d7190 .part v0x1971ac0_0, 4, 1; +L_0x19d7a60 .part v0x1971a00_0, 5, 1; +L_0x19d7bc0 .part v0x1971ac0_0, 5, 1; +L_0x19d8450 .part v0x1971a00_0, 6, 1; +L_0x19d85b0 .part v0x1971ac0_0, 6, 1; +L_0x19d8ea0 .part v0x1971a00_0, 7, 1; +L_0x19d9110 .part v0x1971ac0_0, 7, 1; +L_0x19d99a0 .part v0x1971a00_0, 8, 1; +L_0x19d9b00 .part v0x1971ac0_0, 8, 1; +L_0x19da380 .part v0x1971a00_0, 9, 1; +L_0x19da4e0 .part v0x1971ac0_0, 9, 1; +L_0x19dad90 .part v0x1971a00_0, 10, 1; +L_0x19daef0 .part v0x1971ac0_0, 10, 1; +L_0x19db7b0 .part v0x1971a00_0, 11, 1; +L_0x19db910 .part v0x1971ac0_0, 11, 1; +L_0x19dc1e0 .part v0x1971a00_0, 12, 1; +L_0x19dc340 .part v0x1971ac0_0, 12, 1; +L_0x19dcbd0 .part v0x1971a00_0, 13, 1; +L_0x19dcd30 .part v0x1971ac0_0, 13, 1; +L_0x19dd5d0 .part v0x1971a00_0, 14, 1; +L_0x19dd730 .part v0x1971ac0_0, 14, 1; +L_0x19ddfe0 .part v0x1971a00_0, 15, 1; +L_0x19d9000 .part v0x1971ac0_0, 15, 1; +L_0x19defe0 .part v0x1971a00_0, 16, 1; +L_0x19df140 .part v0x1971ac0_0, 16, 1; +L_0x19df9c0 .part v0x1971a00_0, 17, 1; +L_0x19dfb20 .part v0x1971ac0_0, 17, 1; +L_0x19e03c0 .part v0x1971a00_0, 18, 1; +L_0x19e0520 .part v0x1971ac0_0, 18, 1; +L_0x19e0e10 .part v0x1971a00_0, 19, 1; +L_0x19e0f30 .part v0x1971ac0_0, 19, 1; +L_0x19e1880 .part v0x1971a00_0, 20, 1; +L_0x19e19a0 .part v0x1971ac0_0, 20, 1; +L_0x19e22c0 .part v0x1971a00_0, 21, 1; +L_0x19e2420 .part v0x1971ac0_0, 21, 1; +L_0x19e2cf0 .part v0x1971a00_0, 22, 1; +L_0x19e2e10 .part v0x1971ac0_0, 22, 1; +L_0x19e3740 .part v0x1971a00_0, 23, 1; +L_0x19e3860 .part v0x1971ac0_0, 23, 1; +L_0x19e41a0 .part v0x1971a00_0, 24, 1; +L_0x19e42c0 .part v0x1971ac0_0, 24, 1; +L_0x19e4c10 .part v0x1971a00_0, 25, 1; +L_0x19e4d30 .part v0x1971ac0_0, 25, 1; +L_0x19e5650 .part v0x1971a00_0, 26, 1; +L_0x19e57b0 .part v0x1971ac0_0, 26, 1; +L_0x19e6080 .part v0x1971a00_0, 27, 1; +L_0x19e61a0 .part v0x1971ac0_0, 27, 1; +L_0x19e6ad0 .part v0x1971a00_0, 28, 1; +L_0x19e6bf0 .part v0x1971ac0_0, 28, 1; +L_0x19e7510 .part v0x1971a00_0, 29, 1; +L_0x19e7630 .part v0x1971ac0_0, 29, 1; +L_0x19e7f60 .part v0x1971a00_0, 30, 1; +L_0x19e8080 .part v0x1971ac0_0, 30, 1; +L_0x19e77e0 .part L_0x19ee140, 1, 1; +L_0x19e8510 .part L_0x19ee140, 2, 1; +L_0x19e8870 .part L_0x19ee140, 3, 1; +L_0x19e8a60 .part L_0x19ee140, 4, 1; +L_0x19e87d0 .part L_0x19ee140, 5, 1; +L_0x19e8f30 .part L_0x19ee140, 6, 1; +L_0x19e8d20 .part L_0x19ee140, 7, 1; +L_0x19e94b0 .part L_0x19ee140, 8, 1; +L_0x19e91a0 .part L_0x19ee140, 9, 1; +L_0x19e99a0 .part L_0x19ee140, 10, 1; +L_0x19e9720 .part L_0x19ee140, 11, 1; +L_0x19e9ea0 .part L_0x19ee140, 12, 1; +L_0x19e9c10 .part L_0x19ee140, 13, 1; +L_0x19ea3b0 .part L_0x19ee140, 14, 1; +L_0x19ea110 .part L_0x19ee140, 15, 1; +L_0x19ea9d0 .part L_0x19ee140, 16, 1; +L_0x19ea620 .part L_0x19ee140, 17, 1; +L_0x19eae40 .part L_0x19ee140, 18, 1; +L_0x19eabd0 .part L_0x19ee140, 19, 1; +L_0x19eb330 .part L_0x19ee140, 20, 1; +L_0x19eb0b0 .part L_0x19ee140, 21, 1; +L_0x19eb830 .part L_0x19ee140, 22, 1; +L_0x19eb5a0 .part L_0x19ee140, 23, 1; +L_0x19ebd40 .part L_0x19ee140, 24, 1; +L_0x19ebaa0 .part L_0x19ee140, 25, 1; +L_0x19ec260 .part L_0x19ee140, 26, 1; +L_0x19ebfb0 .part L_0x19ee140, 27, 1; +L_0x19ec790 .part L_0x19ee140, 28, 1; +L_0x19ec4d0 .part L_0x19ee140, 29, 1; +L_0x19ed330 .part v0x1971a00_0, 0, 1; +L_0x19de140 .part v0x1971ac0_0, 0, 1; +LS_0x19ee140_0_0 .concat8 [ 1 1 1 1], L_0x19ecd70, L_0x19d4c10, L_0x19d5690, L_0x19d6070; +LS_0x19ee140_0_4 .concat8 [ 1 1 1 1], L_0x19d6ab0, L_0x19d74e0, L_0x19d7ed0, L_0x19d8920; +LS_0x19ee140_0_8 .concat8 [ 1 1 1 1], L_0x19d9420, L_0x19d9e00, L_0x19da810, L_0x19db230; +LS_0x19ee140_0_12 .concat8 [ 1 1 1 1], L_0x19dbc60, L_0x19dc650, L_0x19dd050, L_0x19dda60; +LS_0x19ee140_0_16 .concat8 [ 1 1 1 1], L_0x19de670, L_0x19df440, L_0x19dfe40, L_0x19e0850; +LS_0x19ee140_0_20 .concat8 [ 1 1 1 1], L_0x19e12c0, L_0x19e1d40, L_0x19e2730, L_0x19e3180; +LS_0x19ee140_0_24 .concat8 [ 1 1 1 1], L_0x19e3be0, L_0x19e4650, L_0x19e50d0, L_0x19e5ac0; +LS_0x19ee140_0_28 .concat8 [ 1 1 1 1], L_0x19e6510, L_0x19e6f50, L_0x19e79a0, L_0x19de420; +LS_0x19ee140_1_0 .concat8 [ 4 4 4 4], LS_0x19ee140_0_0, LS_0x19ee140_0_4, LS_0x19ee140_0_8, LS_0x19ee140_0_12; +LS_0x19ee140_1_4 .concat8 [ 4 4 4 4], LS_0x19ee140_0_16, LS_0x19ee140_0_20, LS_0x19ee140_0_24, LS_0x19ee140_0_28; +L_0x19ee140 .concat8 [ 16 16 0 0], LS_0x19ee140_1_0, LS_0x19ee140_1_4; +L_0x19ed8a0 .part v0x1971a00_0, 31, 1; +L_0x19ed940 .part v0x1971ac0_0, 31, 1; +L_0x19ef1c0 .part L_0x19ee140, 0, 1; +L_0x19ea7c0 .part L_0x19ee140, 1, 1; +L_0x19eed60 .part L_0x19ee140, 31, 1; +S_0x194cf40 .scope module, "adderfinal" "FullAdder1bit" 2 50, 2 8 0, S_0x194ccf0; + .timescale 0 0; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b0" + .port_info 4 /INPUT 1 "carryin" + .port_info 5 /INPUT 1 "subtract" +L_0x19ed3d0/d .functor XOR 1, L_0x19ed940, L_0x19edfe0, C4<0>, C4<0>; +L_0x19ed3d0 .delay 1 (20,20,20) L_0x19ed3d0/d; +L_0x19de2c0/d .functor XOR 1, L_0x19ed8a0, L_0x19ed3d0, C4<0>, C4<0>; +L_0x19de2c0 .delay 1 (20,20,20) L_0x19de2c0/d; +L_0x19de420/d .functor XOR 1, L_0x19de2c0, L_0x7f93f4ea0408, C4<0>, C4<0>; +L_0x19de420 .delay 1 (20,20,20) L_0x19de420/d; +L_0x19ec940/d .functor AND 1, L_0x19ed8a0, L_0x19ed3d0, C4<1>, C4<1>; +L_0x19ec940 .delay 1 (20,20,20) L_0x19ec940/d; +L_0x19ecaa0/d .functor AND 1, L_0x19de2c0, L_0x7f93f4ea0408, C4<1>, C4<1>; +L_0x19ecaa0 .delay 1 (20,20,20) L_0x19ecaa0/d; +L_0x19edfe0/d .functor OR 1, L_0x19ec940, L_0x19ecaa0, C4<0>, C4<0>; +L_0x19edfe0 .delay 1 (20,20,20) L_0x19edfe0/d; +v0x194d1c0_0 .net "a", 0 0, L_0x19ed8a0; 1 drivers +v0x194d2a0_0 .net "b", 0 0, L_0x19ed3d0; 1 drivers +v0x194d360_0 .net "b0", 0 0, L_0x19ed940; 1 drivers +v0x194d430_0 .net "carryin", 0 0, L_0x7f93f4ea0408; alias, 1 drivers +v0x194d4f0_0 .net "carryout", 0 0, L_0x19edfe0; alias, 1 drivers +v0x194d600_0 .net "cout1", 0 0, L_0x19ec940; 1 drivers +v0x194d6c0_0 .net "cout2", 0 0, L_0x19ecaa0; 1 drivers +v0x194d780_0 .net "subtract", 0 0, L_0x19edfe0; alias, 1 drivers +v0x194d820_0 .net "sum", 0 0, L_0x19de420; 1 drivers +v0x194d950_0 .net "sumAB", 0 0, L_0x19de2c0; 1 drivers +S_0x194db10 .scope module, "adderinit" "FullAdder1bit" 2 45, 2 8 0, S_0x194ccf0; + .timescale 0 0; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b0" + .port_info 4 /INPUT 1 "carryin" + .port_info 5 /INPUT 1 "subtract" +L_0x19ec570/d .functor XOR 1, L_0x19de140, L_0x7f93f4ea0408, C4<0>, C4<0>; +L_0x19ec570 .delay 1 (20,20,20) L_0x19ec570/d; +L_0x19ecc10/d .functor XOR 1, L_0x19ed330, L_0x19ec570, C4<0>, C4<0>; +L_0x19ecc10 .delay 1 (20,20,20) L_0x19ecc10/d; +L_0x19ecd70/d .functor XOR 1, L_0x19ecc10, L_0x7f93f4ea0408, C4<0>, C4<0>; +L_0x19ecd70 .delay 1 (20,20,20) L_0x19ecd70/d; +L_0x19eced0/d .functor AND 1, L_0x19ed330, L_0x19ec570, C4<1>, C4<1>; +L_0x19eced0 .delay 1 (20,20,20) L_0x19eced0/d; +L_0x19ed030/d .functor AND 1, L_0x19ecc10, L_0x7f93f4ea0408, C4<1>, C4<1>; +L_0x19ed030 .delay 1 (20,20,20) L_0x19ed030/d; +L_0x19ed190/d .functor OR 1, L_0x19eced0, L_0x19ed030, C4<0>, C4<0>; +L_0x19ed190 .delay 1 (20,20,20) L_0x19ed190/d; +v0x194dd50_0 .net "a", 0 0, L_0x19ed330; 1 drivers +v0x194de10_0 .net "b", 0 0, L_0x19ec570; 1 drivers +v0x194ded0_0 .net "b0", 0 0, L_0x19de140; 1 drivers +v0x194dfa0_0 .net "carryin", 0 0, L_0x7f93f4ea0408; alias, 1 drivers +v0x194e070_0 .net "carryout", 0 0, L_0x19ed190; alias, 1 drivers +v0x194e160_0 .net "cout1", 0 0, L_0x19eced0; 1 drivers +v0x194e220_0 .net "cout2", 0 0, L_0x19ed030; 1 drivers +v0x194e2e0_0 .net "subtract", 0 0, L_0x7f93f4ea0408; alias, 1 drivers +v0x194e3d0_0 .net "sum", 0 0, L_0x19ecd70; 1 drivers +v0x194e520_0 .net "sumAB", 0 0, L_0x19ecc10; 1 drivers +S_0x194e6e0 .scope generate, "genblk1[1]" "genblk1[1]" 2 47, 2 47 0, S_0x194ccf0; + .timescale 0 0; +P_0x194e8a0 .param/l "i" 0 2 47, +C4<01>; +S_0x194e940 .scope module, "addermid" "FullAdder1bit" 2 48, 2 8 0, S_0x194e6e0; + .timescale 0 0; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b0" + .port_info 4 /INPUT 1 "carryin" + .port_info 5 /INPUT 1 "subtract" +L_0x19d49f0/d .functor XOR 1, L_0x19d52f0, L_0x19ed190, C4<0>, C4<0>; +L_0x19d49f0 .delay 1 (20,20,20) L_0x19d49f0/d; +L_0x19d4ab0/d .functor XOR 1, L_0x19d5190, L_0x19d49f0, C4<0>, C4<0>; +L_0x19d4ab0 .delay 1 (20,20,20) L_0x19d4ab0/d; +L_0x19d4c10/d .functor XOR 1, L_0x19d4ab0, L_0x7f93f4ea0408, C4<0>, C4<0>; +L_0x19d4c10 .delay 1 (20,20,20) L_0x19d4c10/d; +L_0x19d4d70/d .functor AND 1, L_0x19d5190, L_0x19d49f0, C4<1>, C4<1>; +L_0x19d4d70 .delay 1 (20,20,20) L_0x19d4d70/d; +L_0x19d4ed0/d .functor AND 1, L_0x19d4ab0, L_0x7f93f4ea0408, C4<1>, C4<1>; +L_0x19d4ed0 .delay 1 (20,20,20) L_0x19d4ed0/d; +L_0x19d5030/d .functor OR 1, L_0x19d4d70, L_0x19d4ed0, C4<0>, C4<0>; +L_0x19d5030 .delay 1 (20,20,20) L_0x19d5030/d; +v0x194ebb0_0 .net "a", 0 0, L_0x19d5190; 1 drivers +v0x194ec90_0 .net "b", 0 0, L_0x19d49f0; 1 drivers +v0x194ed50_0 .net "b0", 0 0, L_0x19d52f0; 1 drivers +v0x194edf0_0 .net "carryin", 0 0, L_0x7f93f4ea0408; alias, 1 drivers +v0x194ee90_0 .net "carryout", 0 0, L_0x19d5030; alias, 1 drivers +v0x194efa0_0 .net "cout1", 0 0, L_0x19d4d70; 1 drivers +v0x194f060_0 .net "cout2", 0 0, L_0x19d4ed0; 1 drivers +v0x194f120_0 .net "subtract", 0 0, L_0x19ed190; alias, 1 drivers +v0x194f1c0_0 .net "sum", 0 0, L_0x19d4c10; 1 drivers +v0x194f2f0_0 .net "sumAB", 0 0, L_0x19d4ab0; 1 drivers +S_0x194f4b0 .scope generate, "genblk1[2]" "genblk1[2]" 2 47, 2 47 0, S_0x194ccf0; + .timescale 0 0; +P_0x194f670 .param/l "i" 0 2 47, +C4<010>; +S_0x194f730 .scope module, "addermid" "FullAdder1bit" 2 48, 2 8 0, S_0x194f4b0; + .timescale 0 0; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b0" + .port_info 4 /INPUT 1 "carryin" + .port_info 5 /INPUT 1 "subtract" +L_0x19d5430/d .functor XOR 1, L_0x19d5d70, L_0x19d5030, C4<0>, C4<0>; +L_0x19d5430 .delay 1 (20,20,20) L_0x19d5430/d; +L_0x19d5530/d .functor XOR 1, L_0x19d5c10, L_0x19d5430, C4<0>, C4<0>; +L_0x19d5530 .delay 1 (20,20,20) L_0x19d5530/d; +L_0x19d5690/d .functor XOR 1, L_0x19d5530, L_0x7f93f4ea0408, C4<0>, C4<0>; +L_0x19d5690 .delay 1 (20,20,20) L_0x19d5690/d; +L_0x19d57f0/d .functor AND 1, L_0x19d5c10, L_0x19d5430, C4<1>, C4<1>; +L_0x19d57f0 .delay 1 (20,20,20) L_0x19d57f0/d; +L_0x19d5950/d .functor AND 1, L_0x19d5530, L_0x7f93f4ea0408, C4<1>, C4<1>; +L_0x19d5950 .delay 1 (20,20,20) L_0x19d5950/d; +L_0x19d5ab0/d .functor OR 1, L_0x19d57f0, L_0x19d5950, C4<0>, C4<0>; +L_0x19d5ab0 .delay 1 (20,20,20) L_0x19d5ab0/d; +v0x194f9a0_0 .net "a", 0 0, L_0x19d5c10; 1 drivers +v0x194fa80_0 .net "b", 0 0, L_0x19d5430; 1 drivers +v0x194fb40_0 .net "b0", 0 0, L_0x19d5d70; 1 drivers +v0x194fc10_0 .net "carryin", 0 0, L_0x7f93f4ea0408; alias, 1 drivers +v0x194fd40_0 .net "carryout", 0 0, L_0x19d5ab0; alias, 1 drivers +v0x194fe00_0 .net "cout1", 0 0, L_0x19d57f0; 1 drivers +v0x194fec0_0 .net "cout2", 0 0, L_0x19d5950; 1 drivers +v0x194ff80_0 .net "subtract", 0 0, L_0x19d5030; alias, 1 drivers +v0x1950020_0 .net "sum", 0 0, L_0x19d5690; 1 drivers +v0x1950150_0 .net "sumAB", 0 0, L_0x19d5530; 1 drivers +S_0x1950310 .scope generate, "genblk1[3]" "genblk1[3]" 2 47, 2 47 0, S_0x194ccf0; + .timescale 0 0; +P_0x1950520 .param/l "i" 0 2 47, +C4<011>; +S_0x19505e0 .scope module, "addermid" "FullAdder1bit" 2 48, 2 8 0, S_0x1950310; + .timescale 0 0; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b0" + .port_info 4 /INPUT 1 "carryin" + .port_info 5 /INPUT 1 "subtract" +L_0x19d5e10/d .functor XOR 1, L_0x19d67e0, L_0x19d5ab0, C4<0>, C4<0>; +L_0x19d5e10 .delay 1 (20,20,20) L_0x19d5e10/d; +L_0x19d5f10/d .functor XOR 1, L_0x19d65f0, L_0x19d5e10, C4<0>, C4<0>; +L_0x19d5f10 .delay 1 (20,20,20) L_0x19d5f10/d; +L_0x19d6070/d .functor XOR 1, L_0x19d5f10, L_0x7f93f4ea0408, C4<0>, C4<0>; +L_0x19d6070 .delay 1 (20,20,20) L_0x19d6070/d; +L_0x19d61d0/d .functor AND 1, L_0x19d65f0, L_0x19d5e10, C4<1>, C4<1>; +L_0x19d61d0 .delay 1 (20,20,20) L_0x19d61d0/d; +L_0x19d6330/d .functor AND 1, L_0x19d5f10, L_0x7f93f4ea0408, C4<1>, C4<1>; +L_0x19d6330 .delay 1 (20,20,20) L_0x19d6330/d; +L_0x19d6490/d .functor OR 1, L_0x19d61d0, L_0x19d6330, C4<0>, C4<0>; +L_0x19d6490 .delay 1 (20,20,20) L_0x19d6490/d; +v0x1950850_0 .net "a", 0 0, L_0x19d65f0; 1 drivers +v0x1950930_0 .net "b", 0 0, L_0x19d5e10; 1 drivers +v0x19509f0_0 .net "b0", 0 0, L_0x19d67e0; 1 drivers +v0x1950a90_0 .net "carryin", 0 0, L_0x7f93f4ea0408; alias, 1 drivers +v0x1950b30_0 .net "carryout", 0 0, L_0x19d6490; alias, 1 drivers +v0x1950c40_0 .net "cout1", 0 0, L_0x19d61d0; 1 drivers +v0x1950d00_0 .net "cout2", 0 0, L_0x19d6330; 1 drivers +v0x1950dc0_0 .net "subtract", 0 0, L_0x19d5ab0; alias, 1 drivers +v0x1950e60_0 .net "sum", 0 0, L_0x19d6070; 1 drivers +v0x1950f90_0 .net "sumAB", 0 0, L_0x19d5f10; 1 drivers +S_0x1951150 .scope generate, "genblk1[4]" "genblk1[4]" 2 47, 2 47 0, S_0x194ccf0; + .timescale 0 0; +P_0x1951310 .param/l "i" 0 2 47, +C4<0100>; +S_0x19513d0 .scope module, "addermid" "FullAdder1bit" 2 48, 2 8 0, S_0x1951150; + .timescale 0 0; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b0" + .port_info 4 /INPUT 1 "carryin" + .port_info 5 /INPUT 1 "subtract" +L_0x19d6690/d .functor XOR 1, L_0x19d7190, L_0x19d6490, C4<0>, C4<0>; +L_0x19d6690 .delay 1 (20,20,20) L_0x19d6690/d; +L_0x19d69a0/d .functor XOR 1, L_0x19d7030, L_0x19d6690, C4<0>, C4<0>; +L_0x19d69a0 .delay 1 (20,20,20) L_0x19d69a0/d; +L_0x19d6ab0/d .functor XOR 1, L_0x19d69a0, L_0x7f93f4ea0408, C4<0>, C4<0>; +L_0x19d6ab0 .delay 1 (20,20,20) L_0x19d6ab0/d; +L_0x19d6c10/d .functor AND 1, L_0x19d7030, L_0x19d6690, C4<1>, C4<1>; +L_0x19d6c10 .delay 1 (20,20,20) L_0x19d6c10/d; +L_0x19d6d70/d .functor AND 1, L_0x19d69a0, L_0x7f93f4ea0408, C4<1>, C4<1>; +L_0x19d6d70 .delay 1 (20,20,20) L_0x19d6d70/d; +L_0x19d6ed0/d .functor OR 1, L_0x19d6c10, L_0x19d6d70, C4<0>, C4<0>; +L_0x19d6ed0 .delay 1 (20,20,20) L_0x19d6ed0/d; +v0x1951640_0 .net "a", 0 0, L_0x19d7030; 1 drivers +v0x1951720_0 .net "b", 0 0, L_0x19d6690; 1 drivers +v0x19517e0_0 .net "b0", 0 0, L_0x19d7190; 1 drivers +v0x19518b0_0 .net "carryin", 0 0, L_0x7f93f4ea0408; alias, 1 drivers +v0x1951950_0 .net "carryout", 0 0, L_0x19d6ed0; alias, 1 drivers +v0x1951a60_0 .net "cout1", 0 0, L_0x19d6c10; 1 drivers +v0x1951b20_0 .net "cout2", 0 0, L_0x19d6d70; 1 drivers +v0x1951be0_0 .net "subtract", 0 0, L_0x19d6490; alias, 1 drivers +v0x1951c80_0 .net "sum", 0 0, L_0x19d6ab0; 1 drivers +v0x1951db0_0 .net "sumAB", 0 0, L_0x19d69a0; 1 drivers +S_0x1951f70 .scope generate, "genblk1[5]" "genblk1[5]" 2 47, 2 47 0, S_0x194ccf0; + .timescale 0 0; +P_0x1952130 .param/l "i" 0 2 47, +C4<0101>; +S_0x19521f0 .scope module, "addermid" "FullAdder1bit" 2 48, 2 8 0, S_0x1951f70; + .timescale 0 0; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b0" + .port_info 4 /INPUT 1 "carryin" + .port_info 5 /INPUT 1 "subtract" +L_0x19d7280/d .functor XOR 1, L_0x19d7bc0, L_0x19d6ed0, C4<0>, C4<0>; +L_0x19d7280 .delay 1 (20,20,20) L_0x19d7280/d; +L_0x19d7380/d .functor XOR 1, L_0x19d7a60, L_0x19d7280, C4<0>, C4<0>; +L_0x19d7380 .delay 1 (20,20,20) L_0x19d7380/d; +L_0x19d74e0/d .functor XOR 1, L_0x19d7380, L_0x7f93f4ea0408, C4<0>, C4<0>; +L_0x19d74e0 .delay 1 (20,20,20) L_0x19d74e0/d; +L_0x19d7640/d .functor AND 1, L_0x19d7a60, L_0x19d7280, C4<1>, C4<1>; +L_0x19d7640 .delay 1 (20,20,20) L_0x19d7640/d; +L_0x19d77a0/d .functor AND 1, L_0x19d7380, L_0x7f93f4ea0408, C4<1>, C4<1>; +L_0x19d77a0 .delay 1 (20,20,20) L_0x19d77a0/d; +L_0x19d7900/d .functor OR 1, L_0x19d7640, L_0x19d77a0, C4<0>, C4<0>; +L_0x19d7900 .delay 1 (20,20,20) L_0x19d7900/d; +v0x1952460_0 .net "a", 0 0, L_0x19d7a60; 1 drivers +v0x1952540_0 .net "b", 0 0, L_0x19d7280; 1 drivers +v0x1952600_0 .net "b0", 0 0, L_0x19d7bc0; 1 drivers +v0x19526d0_0 .net "carryin", 0 0, L_0x7f93f4ea0408; alias, 1 drivers +v0x1952770_0 .net "carryout", 0 0, L_0x19d7900; alias, 1 drivers +v0x1952880_0 .net "cout1", 0 0, L_0x19d7640; 1 drivers +v0x1952940_0 .net "cout2", 0 0, L_0x19d77a0; 1 drivers +v0x1952a00_0 .net "subtract", 0 0, L_0x19d6ed0; alias, 1 drivers +v0x1952aa0_0 .net "sum", 0 0, L_0x19d74e0; 1 drivers +v0x1952bd0_0 .net "sumAB", 0 0, L_0x19d7380; 1 drivers +S_0x1952d90 .scope generate, "genblk1[6]" "genblk1[6]" 2 47, 2 47 0, S_0x194ccf0; + .timescale 0 0; +P_0x1952f50 .param/l "i" 0 2 47, +C4<0110>; +S_0x1953010 .scope module, "addermid" "FullAdder1bit" 2 48, 2 8 0, S_0x1952d90; + .timescale 0 0; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b0" + .port_info 4 /INPUT 1 "carryin" + .port_info 5 /INPUT 1 "subtract" +L_0x19d7cc0/d .functor XOR 1, L_0x19d85b0, L_0x19d7900, C4<0>, C4<0>; +L_0x19d7cc0 .delay 1 (20,20,20) L_0x19d7cc0/d; +L_0x19d7dc0/d .functor XOR 1, L_0x19d8450, L_0x19d7cc0, C4<0>, C4<0>; +L_0x19d7dc0 .delay 1 (20,20,20) L_0x19d7dc0/d; +L_0x19d7ed0/d .functor XOR 1, L_0x19d7dc0, L_0x7f93f4ea0408, C4<0>, C4<0>; +L_0x19d7ed0 .delay 1 (20,20,20) L_0x19d7ed0/d; +L_0x19d8030/d .functor AND 1, L_0x19d8450, L_0x19d7cc0, C4<1>, C4<1>; +L_0x19d8030 .delay 1 (20,20,20) L_0x19d8030/d; +L_0x19d8190/d .functor AND 1, L_0x19d7dc0, L_0x7f93f4ea0408, C4<1>, C4<1>; +L_0x19d8190 .delay 1 (20,20,20) L_0x19d8190/d; +L_0x19d82f0/d .functor OR 1, L_0x19d8030, L_0x19d8190, C4<0>, C4<0>; +L_0x19d82f0 .delay 1 (20,20,20) L_0x19d82f0/d; +v0x1953280_0 .net "a", 0 0, L_0x19d8450; 1 drivers +v0x1953360_0 .net "b", 0 0, L_0x19d7cc0; 1 drivers +v0x1953420_0 .net "b0", 0 0, L_0x19d85b0; 1 drivers +v0x19534f0_0 .net "carryin", 0 0, L_0x7f93f4ea0408; alias, 1 drivers +v0x19536a0_0 .net "carryout", 0 0, L_0x19d82f0; alias, 1 drivers +v0x1953740_0 .net "cout1", 0 0, L_0x19d8030; 1 drivers +v0x19537e0_0 .net "cout2", 0 0, L_0x19d8190; 1 drivers +v0x19538a0_0 .net "subtract", 0 0, L_0x19d7900; alias, 1 drivers +v0x1953940_0 .net "sum", 0 0, L_0x19d7ed0; 1 drivers +v0x1953a70_0 .net "sumAB", 0 0, L_0x19d7dc0; 1 drivers +S_0x1953c30 .scope generate, "genblk1[7]" "genblk1[7]" 2 47, 2 47 0, S_0x194ccf0; + .timescale 0 0; +P_0x19504d0 .param/l "i" 0 2 47, +C4<0111>; +S_0x1953ef0 .scope module, "addermid" "FullAdder1bit" 2 48, 2 8 0, S_0x1953c30; + .timescale 0 0; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b0" + .port_info 4 /INPUT 1 "carryin" + .port_info 5 /INPUT 1 "subtract" +L_0x19d86c0/d .functor XOR 1, L_0x19d9110, L_0x19d82f0, C4<0>, C4<0>; +L_0x19d86c0 .delay 1 (20,20,20) L_0x19d86c0/d; +L_0x19d87c0/d .functor XOR 1, L_0x19d8ea0, L_0x19d86c0, C4<0>, C4<0>; +L_0x19d87c0 .delay 1 (20,20,20) L_0x19d87c0/d; +L_0x19d8920/d .functor XOR 1, L_0x19d87c0, L_0x7f93f4ea0408, C4<0>, C4<0>; +L_0x19d8920 .delay 1 (20,20,20) L_0x19d8920/d; +L_0x19d8a80/d .functor AND 1, L_0x19d8ea0, L_0x19d86c0, C4<1>, C4<1>; +L_0x19d8a80 .delay 1 (20,20,20) L_0x19d8a80/d; +L_0x19d8be0/d .functor AND 1, L_0x19d87c0, L_0x7f93f4ea0408, C4<1>, C4<1>; +L_0x19d8be0 .delay 1 (20,20,20) L_0x19d8be0/d; +L_0x19d8d40/d .functor OR 1, L_0x19d8a80, L_0x19d8be0, C4<0>, C4<0>; +L_0x19d8d40 .delay 1 (20,20,20) L_0x19d8d40/d; +v0x1954160_0 .net "a", 0 0, L_0x19d8ea0; 1 drivers +v0x1954240_0 .net "b", 0 0, L_0x19d86c0; 1 drivers +v0x1954300_0 .net "b0", 0 0, L_0x19d9110; 1 drivers +v0x19543d0_0 .net "carryin", 0 0, L_0x7f93f4ea0408; alias, 1 drivers +v0x1954470_0 .net "carryout", 0 0, L_0x19d8d40; alias, 1 drivers +v0x1954580_0 .net "cout1", 0 0, L_0x19d8a80; 1 drivers +v0x1954640_0 .net "cout2", 0 0, L_0x19d8be0; 1 drivers +v0x1954700_0 .net "subtract", 0 0, L_0x19d82f0; alias, 1 drivers +v0x19547a0_0 .net "sum", 0 0, L_0x19d8920; 1 drivers +v0x19548d0_0 .net "sumAB", 0 0, L_0x19d87c0; 1 drivers +S_0x1954a90 .scope generate, "genblk1[8]" "genblk1[8]" 2 47, 2 47 0, S_0x194ccf0; + .timescale 0 0; +P_0x1954c50 .param/l "i" 0 2 47, +C4<01000>; +S_0x1954d10 .scope module, "addermid" "FullAdder1bit" 2 48, 2 8 0, S_0x1954a90; + .timescale 0 0; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b0" + .port_info 4 /INPUT 1 "carryin" + .port_info 5 /INPUT 1 "subtract" +L_0x19d8650/d .functor XOR 1, L_0x19d9b00, L_0x19d8d40, C4<0>, C4<0>; +L_0x19d8650 .delay 1 (20,20,20) L_0x19d8650/d; +L_0x19d92c0/d .functor XOR 1, L_0x19d99a0, L_0x19d8650, C4<0>, C4<0>; +L_0x19d92c0 .delay 1 (20,20,20) L_0x19d92c0/d; +L_0x19d9420/d .functor XOR 1, L_0x19d92c0, L_0x7f93f4ea0408, C4<0>, C4<0>; +L_0x19d9420 .delay 1 (20,20,20) L_0x19d9420/d; +L_0x19d9580/d .functor AND 1, L_0x19d99a0, L_0x19d8650, C4<1>, C4<1>; +L_0x19d9580 .delay 1 (20,20,20) L_0x19d9580/d; +L_0x19d96e0/d .functor AND 1, L_0x19d92c0, L_0x7f93f4ea0408, C4<1>, C4<1>; +L_0x19d96e0 .delay 1 (20,20,20) L_0x19d96e0/d; +L_0x19d9840/d .functor OR 1, L_0x19d9580, L_0x19d96e0, C4<0>, C4<0>; +L_0x19d9840 .delay 1 (20,20,20) L_0x19d9840/d; +v0x1954f80_0 .net "a", 0 0, L_0x19d99a0; 1 drivers +v0x1955060_0 .net "b", 0 0, L_0x19d8650; 1 drivers +v0x1955120_0 .net "b0", 0 0, L_0x19d9b00; 1 drivers +v0x19551f0_0 .net "carryin", 0 0, L_0x7f93f4ea0408; alias, 1 drivers +v0x1955290_0 .net "carryout", 0 0, L_0x19d9840; alias, 1 drivers +v0x19553a0_0 .net "cout1", 0 0, L_0x19d9580; 1 drivers +v0x1955460_0 .net "cout2", 0 0, L_0x19d96e0; 1 drivers +v0x1955520_0 .net "subtract", 0 0, L_0x19d8d40; alias, 1 drivers +v0x19555c0_0 .net "sum", 0 0, L_0x19d9420; 1 drivers +v0x19556f0_0 .net "sumAB", 0 0, L_0x19d92c0; 1 drivers +S_0x19558b0 .scope generate, "genblk1[9]" "genblk1[9]" 2 47, 2 47 0, S_0x194ccf0; + .timescale 0 0; +P_0x1955a70 .param/l "i" 0 2 47, +C4<01001>; +S_0x1955b30 .scope module, "addermid" "FullAdder1bit" 2 48, 2 8 0, S_0x19558b0; + .timescale 0 0; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b0" + .port_info 4 /INPUT 1 "carryin" + .port_info 5 /INPUT 1 "subtract" +L_0x19d9ba0/d .functor XOR 1, L_0x19da4e0, L_0x19d9840, C4<0>, C4<0>; +L_0x19d9ba0 .delay 1 (20,20,20) L_0x19d9ba0/d; +L_0x19d9ca0/d .functor XOR 1, L_0x19da380, L_0x19d9ba0, C4<0>, C4<0>; +L_0x19d9ca0 .delay 1 (20,20,20) L_0x19d9ca0/d; +L_0x19d9e00/d .functor XOR 1, L_0x19d9ca0, L_0x7f93f4ea0408, C4<0>, C4<0>; +L_0x19d9e00 .delay 1 (20,20,20) L_0x19d9e00/d; +L_0x19d9f60/d .functor AND 1, L_0x19da380, L_0x19d9ba0, C4<1>, C4<1>; +L_0x19d9f60 .delay 1 (20,20,20) L_0x19d9f60/d; +L_0x19da0c0/d .functor AND 1, L_0x19d9ca0, L_0x7f93f4ea0408, C4<1>, C4<1>; +L_0x19da0c0 .delay 1 (20,20,20) L_0x19da0c0/d; +L_0x19da220/d .functor OR 1, L_0x19d9f60, L_0x19da0c0, C4<0>, C4<0>; +L_0x19da220 .delay 1 (20,20,20) L_0x19da220/d; +v0x1955da0_0 .net "a", 0 0, L_0x19da380; 1 drivers +v0x1955e80_0 .net "b", 0 0, L_0x19d9ba0; 1 drivers +v0x1955f40_0 .net "b0", 0 0, L_0x19da4e0; 1 drivers +v0x1956010_0 .net "carryin", 0 0, L_0x7f93f4ea0408; alias, 1 drivers +v0x19560b0_0 .net "carryout", 0 0, L_0x19da220; alias, 1 drivers +v0x19561c0_0 .net "cout1", 0 0, L_0x19d9f60; 1 drivers +v0x1956280_0 .net "cout2", 0 0, L_0x19da0c0; 1 drivers +v0x1956340_0 .net "subtract", 0 0, L_0x19d9840; alias, 1 drivers +v0x19563e0_0 .net "sum", 0 0, L_0x19d9e00; 1 drivers +v0x1956510_0 .net "sumAB", 0 0, L_0x19d9ca0; 1 drivers +S_0x19566d0 .scope generate, "genblk1[10]" "genblk1[10]" 2 47, 2 47 0, S_0x194ccf0; + .timescale 0 0; +P_0x1956890 .param/l "i" 0 2 47, +C4<01010>; +S_0x1956950 .scope module, "addermid" "FullAdder1bit" 2 48, 2 8 0, S_0x19566d0; + .timescale 0 0; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b0" + .port_info 4 /INPUT 1 "carryin" + .port_info 5 /INPUT 1 "subtract" +L_0x19d6750/d .functor XOR 1, L_0x19daef0, L_0x19da220, C4<0>, C4<0>; +L_0x19d6750 .delay 1 (20,20,20) L_0x19d6750/d; +L_0x19da6b0/d .functor XOR 1, L_0x19dad90, L_0x19d6750, C4<0>, C4<0>; +L_0x19da6b0 .delay 1 (20,20,20) L_0x19da6b0/d; +L_0x19da810/d .functor XOR 1, L_0x19da6b0, L_0x7f93f4ea0408, C4<0>, C4<0>; +L_0x19da810 .delay 1 (20,20,20) L_0x19da810/d; +L_0x19da970/d .functor AND 1, L_0x19dad90, L_0x19d6750, C4<1>, C4<1>; +L_0x19da970 .delay 1 (20,20,20) L_0x19da970/d; +L_0x19daad0/d .functor AND 1, L_0x19da6b0, L_0x7f93f4ea0408, C4<1>, C4<1>; +L_0x19daad0 .delay 1 (20,20,20) L_0x19daad0/d; +L_0x19dac30/d .functor OR 1, L_0x19da970, L_0x19daad0, C4<0>, C4<0>; +L_0x19dac30 .delay 1 (20,20,20) L_0x19dac30/d; +v0x1956bc0_0 .net "a", 0 0, L_0x19dad90; 1 drivers +v0x1956ca0_0 .net "b", 0 0, L_0x19d6750; 1 drivers +v0x1956d60_0 .net "b0", 0 0, L_0x19daef0; 1 drivers +v0x1956e30_0 .net "carryin", 0 0, L_0x7f93f4ea0408; alias, 1 drivers +v0x1956ed0_0 .net "carryout", 0 0, L_0x19dac30; alias, 1 drivers +v0x1956fe0_0 .net "cout1", 0 0, L_0x19da970; 1 drivers +v0x19570a0_0 .net "cout2", 0 0, L_0x19daad0; 1 drivers +v0x1957160_0 .net "subtract", 0 0, L_0x19da220; alias, 1 drivers +v0x1957200_0 .net "sum", 0 0, L_0x19da810; 1 drivers +v0x1957330_0 .net "sumAB", 0 0, L_0x19da6b0; 1 drivers +S_0x19574f0 .scope generate, "genblk1[11]" "genblk1[11]" 2 47, 2 47 0, S_0x194ccf0; + .timescale 0 0; +P_0x19576b0 .param/l "i" 0 2 47, +C4<01011>; +S_0x1957770 .scope module, "addermid" "FullAdder1bit" 2 48, 2 8 0, S_0x19574f0; + .timescale 0 0; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b0" + .port_info 4 /INPUT 1 "carryin" + .port_info 5 /INPUT 1 "subtract" +L_0x19da580/d .functor XOR 1, L_0x19db910, L_0x19dac30, C4<0>, C4<0>; +L_0x19da580 .delay 1 (20,20,20) L_0x19da580/d; +L_0x19db0d0/d .functor XOR 1, L_0x19db7b0, L_0x19da580, C4<0>, C4<0>; +L_0x19db0d0 .delay 1 (20,20,20) L_0x19db0d0/d; +L_0x19db230/d .functor XOR 1, L_0x19db0d0, L_0x7f93f4ea0408, C4<0>, C4<0>; +L_0x19db230 .delay 1 (20,20,20) L_0x19db230/d; +L_0x19db390/d .functor AND 1, L_0x19db7b0, L_0x19da580, C4<1>, C4<1>; +L_0x19db390 .delay 1 (20,20,20) L_0x19db390/d; +L_0x19db4f0/d .functor AND 1, L_0x19db0d0, L_0x7f93f4ea0408, C4<1>, C4<1>; +L_0x19db4f0 .delay 1 (20,20,20) L_0x19db4f0/d; +L_0x19db650/d .functor OR 1, L_0x19db390, L_0x19db4f0, C4<0>, C4<0>; +L_0x19db650 .delay 1 (20,20,20) L_0x19db650/d; +v0x19579e0_0 .net "a", 0 0, L_0x19db7b0; 1 drivers +v0x1957ac0_0 .net "b", 0 0, L_0x19da580; 1 drivers +v0x1957b80_0 .net "b0", 0 0, L_0x19db910; 1 drivers +v0x1957c50_0 .net "carryin", 0 0, L_0x7f93f4ea0408; alias, 1 drivers +v0x1957cf0_0 .net "carryout", 0 0, L_0x19db650; alias, 1 drivers +v0x1957e00_0 .net "cout1", 0 0, L_0x19db390; 1 drivers +v0x1957ec0_0 .net "cout2", 0 0, L_0x19db4f0; 1 drivers +v0x1957f80_0 .net "subtract", 0 0, L_0x19dac30; alias, 1 drivers +v0x1958020_0 .net "sum", 0 0, L_0x19db230; 1 drivers +v0x1958150_0 .net "sumAB", 0 0, L_0x19db0d0; 1 drivers +S_0x1958310 .scope generate, "genblk1[12]" "genblk1[12]" 2 47, 2 47 0, S_0x194ccf0; + .timescale 0 0; +P_0x19584d0 .param/l "i" 0 2 47, +C4<01100>; +S_0x1958590 .scope module, "addermid" "FullAdder1bit" 2 48, 2 8 0, S_0x1958310; + .timescale 0 0; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b0" + .port_info 4 /INPUT 1 "carryin" + .port_info 5 /INPUT 1 "subtract" +L_0x19daf90/d .functor XOR 1, L_0x19dc340, L_0x19db650, C4<0>, C4<0>; +L_0x19daf90 .delay 1 (20,20,20) L_0x19daf90/d; +L_0x19dbb00/d .functor XOR 1, L_0x19dc1e0, L_0x19daf90, C4<0>, C4<0>; +L_0x19dbb00 .delay 1 (20,20,20) L_0x19dbb00/d; +L_0x19dbc60/d .functor XOR 1, L_0x19dbb00, L_0x7f93f4ea0408, C4<0>, C4<0>; +L_0x19dbc60 .delay 1 (20,20,20) L_0x19dbc60/d; +L_0x19dbdc0/d .functor AND 1, L_0x19dc1e0, L_0x19daf90, C4<1>, C4<1>; +L_0x19dbdc0 .delay 1 (20,20,20) L_0x19dbdc0/d; +L_0x19dbf20/d .functor AND 1, L_0x19dbb00, L_0x7f93f4ea0408, C4<1>, C4<1>; +L_0x19dbf20 .delay 1 (20,20,20) L_0x19dbf20/d; +L_0x19dc080/d .functor OR 1, L_0x19dbdc0, L_0x19dbf20, C4<0>, C4<0>; +L_0x19dc080 .delay 1 (20,20,20) L_0x19dc080/d; +v0x1958800_0 .net "a", 0 0, L_0x19dc1e0; 1 drivers +v0x19588e0_0 .net "b", 0 0, L_0x19daf90; 1 drivers +v0x19589a0_0 .net "b0", 0 0, L_0x19dc340; 1 drivers +v0x1958a70_0 .net "carryin", 0 0, L_0x7f93f4ea0408; alias, 1 drivers +v0x1958b10_0 .net "carryout", 0 0, L_0x19dc080; alias, 1 drivers +v0x1958c20_0 .net "cout1", 0 0, L_0x19dbdc0; 1 drivers +v0x1958ce0_0 .net "cout2", 0 0, L_0x19dbf20; 1 drivers +v0x1958da0_0 .net "subtract", 0 0, L_0x19db650; alias, 1 drivers +v0x1958e40_0 .net "sum", 0 0, L_0x19dbc60; 1 drivers +v0x1958f70_0 .net "sumAB", 0 0, L_0x19dbb00; 1 drivers +S_0x1959130 .scope generate, "genblk1[13]" "genblk1[13]" 2 47, 2 47 0, S_0x194ccf0; + .timescale 0 0; +P_0x19592f0 .param/l "i" 0 2 47, +C4<01101>; +S_0x19593b0 .scope module, "addermid" "FullAdder1bit" 2 48, 2 8 0, S_0x1959130; + .timescale 0 0; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b0" + .port_info 4 /INPUT 1 "carryin" + .port_info 5 /INPUT 1 "subtract" +L_0x19db9b0/d .functor XOR 1, L_0x19dcd30, L_0x19dc080, C4<0>, C4<0>; +L_0x19db9b0 .delay 1 (20,20,20) L_0x19db9b0/d; +L_0x19dc540/d .functor XOR 1, L_0x19dcbd0, L_0x19db9b0, C4<0>, C4<0>; +L_0x19dc540 .delay 1 (20,20,20) L_0x19dc540/d; +L_0x19dc650/d .functor XOR 1, L_0x19dc540, L_0x7f93f4ea0408, C4<0>, C4<0>; +L_0x19dc650 .delay 1 (20,20,20) L_0x19dc650/d; +L_0x19dc7b0/d .functor AND 1, L_0x19dcbd0, L_0x19db9b0, C4<1>, C4<1>; +L_0x19dc7b0 .delay 1 (20,20,20) L_0x19dc7b0/d; +L_0x19dc910/d .functor AND 1, L_0x19dc540, L_0x7f93f4ea0408, C4<1>, C4<1>; +L_0x19dc910 .delay 1 (20,20,20) L_0x19dc910/d; +L_0x19dca70/d .functor OR 1, L_0x19dc7b0, L_0x19dc910, C4<0>, C4<0>; +L_0x19dca70 .delay 1 (20,20,20) L_0x19dca70/d; +v0x1959620_0 .net "a", 0 0, L_0x19dcbd0; 1 drivers +v0x1959700_0 .net "b", 0 0, L_0x19db9b0; 1 drivers +v0x19597c0_0 .net "b0", 0 0, L_0x19dcd30; 1 drivers +v0x1959890_0 .net "carryin", 0 0, L_0x7f93f4ea0408; alias, 1 drivers +v0x1959930_0 .net "carryout", 0 0, L_0x19dca70; alias, 1 drivers +v0x1959a40_0 .net "cout1", 0 0, L_0x19dc7b0; 1 drivers +v0x1959b00_0 .net "cout2", 0 0, L_0x19dc910; 1 drivers +v0x1959bc0_0 .net "subtract", 0 0, L_0x19dc080; alias, 1 drivers +v0x1959c60_0 .net "sum", 0 0, L_0x19dc650; 1 drivers +v0x1959d90_0 .net "sumAB", 0 0, L_0x19dc540; 1 drivers +S_0x1959f50 .scope generate, "genblk1[14]" "genblk1[14]" 2 47, 2 47 0, S_0x194ccf0; + .timescale 0 0; +P_0x195a110 .param/l "i" 0 2 47, +C4<01110>; +S_0x195a1d0 .scope module, "addermid" "FullAdder1bit" 2 48, 2 8 0, S_0x1959f50; + .timescale 0 0; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b0" + .port_info 4 /INPUT 1 "carryin" + .port_info 5 /INPUT 1 "subtract" +L_0x19dc3e0/d .functor XOR 1, L_0x19dd730, L_0x19dca70, C4<0>, C4<0>; +L_0x19dc3e0 .delay 1 (20,20,20) L_0x19dc3e0/d; +L_0x19dcf40/d .functor XOR 1, L_0x19dd5d0, L_0x19dc3e0, C4<0>, C4<0>; +L_0x19dcf40 .delay 1 (20,20,20) L_0x19dcf40/d; +L_0x19dd050/d .functor XOR 1, L_0x19dcf40, L_0x7f93f4ea0408, C4<0>, C4<0>; +L_0x19dd050 .delay 1 (20,20,20) L_0x19dd050/d; +L_0x19dd1b0/d .functor AND 1, L_0x19dd5d0, L_0x19dc3e0, C4<1>, C4<1>; +L_0x19dd1b0 .delay 1 (20,20,20) L_0x19dd1b0/d; +L_0x19dd310/d .functor AND 1, L_0x19dcf40, L_0x7f93f4ea0408, C4<1>, C4<1>; +L_0x19dd310 .delay 1 (20,20,20) L_0x19dd310/d; +L_0x19dd470/d .functor OR 1, L_0x19dd1b0, L_0x19dd310, C4<0>, C4<0>; +L_0x19dd470 .delay 1 (20,20,20) L_0x19dd470/d; +v0x195a440_0 .net "a", 0 0, L_0x19dd5d0; 1 drivers +v0x195a520_0 .net "b", 0 0, L_0x19dc3e0; 1 drivers +v0x195a5e0_0 .net "b0", 0 0, L_0x19dd730; 1 drivers +v0x195a6b0_0 .net "carryin", 0 0, L_0x7f93f4ea0408; alias, 1 drivers +v0x1953590_0 .net "carryout", 0 0, L_0x19dd470; alias, 1 drivers +v0x195a960_0 .net "cout1", 0 0, L_0x19dd1b0; 1 drivers +v0x195aa20_0 .net "cout2", 0 0, L_0x19dd310; 1 drivers +v0x195aae0_0 .net "subtract", 0 0, L_0x19dca70; alias, 1 drivers +v0x195ab80_0 .net "sum", 0 0, L_0x19dd050; 1 drivers +v0x195acb0_0 .net "sumAB", 0 0, L_0x19dcf40; 1 drivers +S_0x195ae70 .scope generate, "genblk1[15]" "genblk1[15]" 2 47, 2 47 0, S_0x194ccf0; + .timescale 0 0; +P_0x1953df0 .param/l "i" 0 2 47, +C4<01111>; +S_0x195b190 .scope module, "addermid" "FullAdder1bit" 2 48, 2 8 0, S_0x195ae70; + .timescale 0 0; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b0" + .port_info 4 /INPUT 1 "carryin" + .port_info 5 /INPUT 1 "subtract" +L_0x19dcdd0/d .functor XOR 1, L_0x19d9000, L_0x19dd470, C4<0>, C4<0>; +L_0x19dcdd0 .delay 1 (20,20,20) L_0x19dcdd0/d; +L_0x19dd950/d .functor XOR 1, L_0x19ddfe0, L_0x19dcdd0, C4<0>, C4<0>; +L_0x19dd950 .delay 1 (20,20,20) L_0x19dd950/d; +L_0x19dda60/d .functor XOR 1, L_0x19dd950, L_0x7f93f4ea0408, C4<0>, C4<0>; +L_0x19dda60 .delay 1 (20,20,20) L_0x19dda60/d; +L_0x19ddbc0/d .functor AND 1, L_0x19ddfe0, L_0x19dcdd0, C4<1>, C4<1>; +L_0x19ddbc0 .delay 1 (20,20,20) L_0x19ddbc0/d; +L_0x19ddd20/d .functor AND 1, L_0x19dd950, L_0x7f93f4ea0408, C4<1>, C4<1>; +L_0x19ddd20 .delay 1 (20,20,20) L_0x19ddd20/d; +L_0x19dde80/d .functor OR 1, L_0x19ddbc0, L_0x19ddd20, C4<0>, C4<0>; +L_0x19dde80 .delay 1 (20,20,20) L_0x19dde80/d; +v0x195b400_0 .net "a", 0 0, L_0x19ddfe0; 1 drivers +v0x195b4c0_0 .net "b", 0 0, L_0x19dcdd0; 1 drivers +v0x195b580_0 .net "b0", 0 0, L_0x19d9000; 1 drivers +v0x195b650_0 .net "carryin", 0 0, L_0x7f93f4ea0408; alias, 1 drivers +v0x195b6f0_0 .net "carryout", 0 0, L_0x19dde80; alias, 1 drivers +v0x195b800_0 .net "cout1", 0 0, L_0x19ddbc0; 1 drivers +v0x195b8c0_0 .net "cout2", 0 0, L_0x19ddd20; 1 drivers +v0x195b980_0 .net "subtract", 0 0, L_0x19dd470; alias, 1 drivers +v0x195ba20_0 .net "sum", 0 0, L_0x19dda60; 1 drivers +v0x195bb50_0 .net "sumAB", 0 0, L_0x19dd950; 1 drivers +S_0x195bd10 .scope generate, "genblk1[16]" "genblk1[16]" 2 47, 2 47 0, S_0x194ccf0; + .timescale 0 0; +P_0x195bed0 .param/l "i" 0 2 47, +C4<010000>; +S_0x195bf90 .scope module, "addermid" "FullAdder1bit" 2 48, 2 8 0, S_0x195bd10; + .timescale 0 0; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b0" + .port_info 4 /INPUT 1 "carryin" + .port_info 5 /INPUT 1 "subtract" +L_0x19d90a0/d .functor XOR 1, L_0x19df140, L_0x19dde80, C4<0>, C4<0>; +L_0x19d90a0 .delay 1 (20,20,20) L_0x19d90a0/d; +L_0x19de560/d .functor XOR 1, L_0x19defe0, L_0x19d90a0, C4<0>, C4<0>; +L_0x19de560 .delay 1 (20,20,20) L_0x19de560/d; +L_0x19de670/d .functor XOR 1, L_0x19de560, L_0x7f93f4ea0408, C4<0>, C4<0>; +L_0x19de670 .delay 1 (20,20,20) L_0x19de670/d; +L_0x1968ad0/d .functor AND 1, L_0x19defe0, L_0x19d90a0, C4<1>, C4<1>; +L_0x1968ad0 .delay 1 (20,20,20) L_0x1968ad0/d; +L_0x1968c30/d .functor AND 1, L_0x19de560, L_0x7f93f4ea0408, C4<1>, C4<1>; +L_0x1968c30 .delay 1 (20,20,20) L_0x1968c30/d; +L_0x1968d90/d .functor OR 1, L_0x1968ad0, L_0x1968c30, C4<0>, C4<0>; +L_0x1968d90 .delay 1 (20,20,20) L_0x1968d90/d; +v0x195c200_0 .net "a", 0 0, L_0x19defe0; 1 drivers +v0x195c2e0_0 .net "b", 0 0, L_0x19d90a0; 1 drivers +v0x195c3a0_0 .net "b0", 0 0, L_0x19df140; 1 drivers +v0x195c470_0 .net "carryin", 0 0, L_0x7f93f4ea0408; alias, 1 drivers +v0x195c510_0 .net "carryout", 0 0, L_0x1968d90; alias, 1 drivers +v0x195c620_0 .net "cout1", 0 0, L_0x1968ad0; 1 drivers +v0x195c6e0_0 .net "cout2", 0 0, L_0x1968c30; 1 drivers +v0x195c7a0_0 .net "subtract", 0 0, L_0x19dde80; alias, 1 drivers +v0x195c840_0 .net "sum", 0 0, L_0x19de670; 1 drivers +v0x195c970_0 .net "sumAB", 0 0, L_0x19de560; 1 drivers +S_0x195cb30 .scope generate, "genblk1[17]" "genblk1[17]" 2 47, 2 47 0, S_0x194ccf0; + .timescale 0 0; +P_0x195ccf0 .param/l "i" 0 2 47, +C4<010001>; +S_0x195cdb0 .scope module, "addermid" "FullAdder1bit" 2 48, 2 8 0, S_0x195cb30; + .timescale 0 0; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b0" + .port_info 4 /INPUT 1 "carryin" + .port_info 5 /INPUT 1 "subtract" +L_0x19df1e0/d .functor XOR 1, L_0x19dfb20, L_0x1968d90, C4<0>, C4<0>; +L_0x19df1e0 .delay 1 (20,20,20) L_0x19df1e0/d; +L_0x19df2e0/d .functor XOR 1, L_0x19df9c0, L_0x19df1e0, C4<0>, C4<0>; +L_0x19df2e0 .delay 1 (20,20,20) L_0x19df2e0/d; +L_0x19df440/d .functor XOR 1, L_0x19df2e0, L_0x7f93f4ea0408, C4<0>, C4<0>; +L_0x19df440 .delay 1 (20,20,20) L_0x19df440/d; +L_0x19df5a0/d .functor AND 1, L_0x19df9c0, L_0x19df1e0, C4<1>, C4<1>; +L_0x19df5a0 .delay 1 (20,20,20) L_0x19df5a0/d; +L_0x19df700/d .functor AND 1, L_0x19df2e0, L_0x7f93f4ea0408, C4<1>, C4<1>; +L_0x19df700 .delay 1 (20,20,20) L_0x19df700/d; +L_0x19df860/d .functor OR 1, L_0x19df5a0, L_0x19df700, C4<0>, C4<0>; +L_0x19df860 .delay 1 (20,20,20) L_0x19df860/d; +v0x195d020_0 .net "a", 0 0, L_0x19df9c0; 1 drivers +v0x195d100_0 .net "b", 0 0, L_0x19df1e0; 1 drivers +v0x195d1c0_0 .net "b0", 0 0, L_0x19dfb20; 1 drivers +v0x195d290_0 .net "carryin", 0 0, L_0x7f93f4ea0408; alias, 1 drivers +v0x195d330_0 .net "carryout", 0 0, L_0x19df860; alias, 1 drivers +v0x195d440_0 .net "cout1", 0 0, L_0x19df5a0; 1 drivers +v0x195d500_0 .net "cout2", 0 0, L_0x19df700; 1 drivers +v0x195d5c0_0 .net "subtract", 0 0, L_0x1968d90; alias, 1 drivers +v0x195d660_0 .net "sum", 0 0, L_0x19df440; 1 drivers +v0x195d790_0 .net "sumAB", 0 0, L_0x19df2e0; 1 drivers +S_0x195d950 .scope generate, "genblk1[18]" "genblk1[18]" 2 47, 2 47 0, S_0x194ccf0; + .timescale 0 0; +P_0x195db10 .param/l "i" 0 2 47, +C4<010010>; +S_0x195dbd0 .scope module, "addermid" "FullAdder1bit" 2 48, 2 8 0, S_0x195d950; + .timescale 0 0; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b0" + .port_info 4 /INPUT 1 "carryin" + .port_info 5 /INPUT 1 "subtract" +L_0x19d91b0/d .functor XOR 1, L_0x19e0520, L_0x19df860, C4<0>, C4<0>; +L_0x19d91b0 .delay 1 (20,20,20) L_0x19d91b0/d; +L_0x19dfce0/d .functor XOR 1, L_0x19e03c0, L_0x19d91b0, C4<0>, C4<0>; +L_0x19dfce0 .delay 1 (20,20,20) L_0x19dfce0/d; +L_0x19dfe40/d .functor XOR 1, L_0x19dfce0, L_0x7f93f4ea0408, C4<0>, C4<0>; +L_0x19dfe40 .delay 1 (20,20,20) L_0x19dfe40/d; +L_0x19dffa0/d .functor AND 1, L_0x19e03c0, L_0x19d91b0, C4<1>, C4<1>; +L_0x19dffa0 .delay 1 (20,20,20) L_0x19dffa0/d; +L_0x19e0100/d .functor AND 1, L_0x19dfce0, L_0x7f93f4ea0408, C4<1>, C4<1>; +L_0x19e0100 .delay 1 (20,20,20) L_0x19e0100/d; +L_0x19e0260/d .functor OR 1, L_0x19dffa0, L_0x19e0100, C4<0>, C4<0>; +L_0x19e0260 .delay 1 (20,20,20) L_0x19e0260/d; +v0x195de40_0 .net "a", 0 0, L_0x19e03c0; 1 drivers +v0x195df20_0 .net "b", 0 0, L_0x19d91b0; 1 drivers +v0x195dfe0_0 .net "b0", 0 0, L_0x19e0520; 1 drivers +v0x195e0b0_0 .net "carryin", 0 0, L_0x7f93f4ea0408; alias, 1 drivers +v0x195e150_0 .net "carryout", 0 0, L_0x19e0260; alias, 1 drivers +v0x195e260_0 .net "cout1", 0 0, L_0x19dffa0; 1 drivers +v0x195e320_0 .net "cout2", 0 0, L_0x19e0100; 1 drivers +v0x195e3e0_0 .net "subtract", 0 0, L_0x19df860; alias, 1 drivers +v0x195e480_0 .net "sum", 0 0, L_0x19dfe40; 1 drivers +v0x195e5b0_0 .net "sumAB", 0 0, L_0x19dfce0; 1 drivers +S_0x195e770 .scope generate, "genblk1[19]" "genblk1[19]" 2 47, 2 47 0, S_0x194ccf0; + .timescale 0 0; +P_0x195e930 .param/l "i" 0 2 47, +C4<010011>; +S_0x195e9f0 .scope module, "addermid" "FullAdder1bit" 2 48, 2 8 0, S_0x195e770; + .timescale 0 0; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b0" + .port_info 4 /INPUT 1 "carryin" + .port_info 5 /INPUT 1 "subtract" +L_0x19dfbc0/d .functor XOR 1, L_0x19e0f30, L_0x19e0260, C4<0>, C4<0>; +L_0x19dfbc0 .delay 1 (20,20,20) L_0x19dfbc0/d; +L_0x19e06f0/d .functor XOR 1, L_0x19e0e10, L_0x19dfbc0, C4<0>, C4<0>; +L_0x19e06f0 .delay 1 (20,20,20) L_0x19e06f0/d; +L_0x19e0850/d .functor XOR 1, L_0x19e06f0, L_0x7f93f4ea0408, C4<0>, C4<0>; +L_0x19e0850 .delay 1 (20,20,20) L_0x19e0850/d; +L_0x19e09b0/d .functor AND 1, L_0x19e0e10, L_0x19dfbc0, C4<1>, C4<1>; +L_0x19e09b0 .delay 1 (20,20,20) L_0x19e09b0/d; +L_0x19e0b10/d .functor AND 1, L_0x19e06f0, L_0x7f93f4ea0408, C4<1>, C4<1>; +L_0x19e0b10 .delay 1 (20,20,20) L_0x19e0b10/d; +L_0x19e0c70/d .functor OR 1, L_0x19e09b0, L_0x19e0b10, C4<0>, C4<0>; +L_0x19e0c70 .delay 1 (20,20,20) L_0x19e0c70/d; +v0x195ec60_0 .net "a", 0 0, L_0x19e0e10; 1 drivers +v0x195ed40_0 .net "b", 0 0, L_0x19dfbc0; 1 drivers +v0x195ee00_0 .net "b0", 0 0, L_0x19e0f30; 1 drivers +v0x195eed0_0 .net "carryin", 0 0, L_0x7f93f4ea0408; alias, 1 drivers +v0x195ef70_0 .net "carryout", 0 0, L_0x19e0c70; alias, 1 drivers +v0x195f080_0 .net "cout1", 0 0, L_0x19e09b0; 1 drivers +v0x195f140_0 .net "cout2", 0 0, L_0x19e0b10; 1 drivers +v0x195f200_0 .net "subtract", 0 0, L_0x19e0260; alias, 1 drivers +v0x195f2a0_0 .net "sum", 0 0, L_0x19e0850; 1 drivers +v0x195f3d0_0 .net "sumAB", 0 0, L_0x19e06f0; 1 drivers +S_0x195f590 .scope generate, "genblk1[20]" "genblk1[20]" 2 47, 2 47 0, S_0x194ccf0; + .timescale 0 0; +P_0x195f750 .param/l "i" 0 2 47, +C4<010100>; +S_0x195f810 .scope module, "addermid" "FullAdder1bit" 2 48, 2 8 0, S_0x195f590; + .timescale 0 0; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b0" + .port_info 4 /INPUT 1 "carryin" + .port_info 5 /INPUT 1 "subtract" +L_0x19e05c0/d .functor XOR 1, L_0x19e19a0, L_0x19e0c70, C4<0>, C4<0>; +L_0x19e05c0 .delay 1 (20,20,20) L_0x19e05c0/d; +L_0x19e1160/d .functor XOR 1, L_0x19e1880, L_0x19e05c0, C4<0>, C4<0>; +L_0x19e1160 .delay 1 (20,20,20) L_0x19e1160/d; +L_0x19e12c0/d .functor XOR 1, L_0x19e1160, L_0x7f93f4ea0408, C4<0>, C4<0>; +L_0x19e12c0 .delay 1 (20,20,20) L_0x19e12c0/d; +L_0x19e1420/d .functor AND 1, L_0x19e1880, L_0x19e05c0, C4<1>, C4<1>; +L_0x19e1420 .delay 1 (20,20,20) L_0x19e1420/d; +L_0x19e1580/d .functor AND 1, L_0x19e1160, L_0x7f93f4ea0408, C4<1>, C4<1>; +L_0x19e1580 .delay 1 (20,20,20) L_0x19e1580/d; +L_0x19e16e0/d .functor OR 1, L_0x19e1420, L_0x19e1580, C4<0>, C4<0>; +L_0x19e16e0 .delay 1 (20,20,20) L_0x19e16e0/d; +v0x195fa80_0 .net "a", 0 0, L_0x19e1880; 1 drivers +v0x195fb60_0 .net "b", 0 0, L_0x19e05c0; 1 drivers +v0x195fc20_0 .net "b0", 0 0, L_0x19e19a0; 1 drivers +v0x195fcf0_0 .net "carryin", 0 0, L_0x7f93f4ea0408; alias, 1 drivers +v0x195fd90_0 .net "carryout", 0 0, L_0x19e16e0; alias, 1 drivers +v0x195fea0_0 .net "cout1", 0 0, L_0x19e1420; 1 drivers +v0x195ff60_0 .net "cout2", 0 0, L_0x19e1580; 1 drivers +v0x1960020_0 .net "subtract", 0 0, L_0x19e0c70; alias, 1 drivers +v0x19600c0_0 .net "sum", 0 0, L_0x19e12c0; 1 drivers +v0x19601f0_0 .net "sumAB", 0 0, L_0x19e1160; 1 drivers +S_0x19603b0 .scope generate, "genblk1[21]" "genblk1[21]" 2 47, 2 47 0, S_0x194ccf0; + .timescale 0 0; +P_0x1960570 .param/l "i" 0 2 47, +C4<010101>; +S_0x1960630 .scope module, "addermid" "FullAdder1bit" 2 48, 2 8 0, S_0x19603b0; + .timescale 0 0; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b0" + .port_info 4 /INPUT 1 "carryin" + .port_info 5 /INPUT 1 "subtract" +L_0x19e1020/d .functor XOR 1, L_0x19e2420, L_0x19e16e0, C4<0>, C4<0>; +L_0x19e1020 .delay 1 (20,20,20) L_0x19e1020/d; +L_0x19e1be0/d .functor XOR 1, L_0x19e22c0, L_0x19e1020, C4<0>, C4<0>; +L_0x19e1be0 .delay 1 (20,20,20) L_0x19e1be0/d; +L_0x19e1d40/d .functor XOR 1, L_0x19e1be0, L_0x7f93f4ea0408, C4<0>, C4<0>; +L_0x19e1d40 .delay 1 (20,20,20) L_0x19e1d40/d; +L_0x19e1ea0/d .functor AND 1, L_0x19e22c0, L_0x19e1020, C4<1>, C4<1>; +L_0x19e1ea0 .delay 1 (20,20,20) L_0x19e1ea0/d; +L_0x19e2000/d .functor AND 1, L_0x19e1be0, L_0x7f93f4ea0408, C4<1>, C4<1>; +L_0x19e2000 .delay 1 (20,20,20) L_0x19e2000/d; +L_0x19e2160/d .functor OR 1, L_0x19e1ea0, L_0x19e2000, C4<0>, C4<0>; +L_0x19e2160 .delay 1 (20,20,20) L_0x19e2160/d; +v0x19608a0_0 .net "a", 0 0, L_0x19e22c0; 1 drivers +v0x1960980_0 .net "b", 0 0, L_0x19e1020; 1 drivers +v0x1960a40_0 .net "b0", 0 0, L_0x19e2420; 1 drivers +v0x1960b10_0 .net "carryin", 0 0, L_0x7f93f4ea0408; alias, 1 drivers +v0x1960bb0_0 .net "carryout", 0 0, L_0x19e2160; alias, 1 drivers +v0x1960cc0_0 .net "cout1", 0 0, L_0x19e1ea0; 1 drivers +v0x1960d80_0 .net "cout2", 0 0, L_0x19e2000; 1 drivers +v0x1960e40_0 .net "subtract", 0 0, L_0x19e16e0; alias, 1 drivers +v0x1960ee0_0 .net "sum", 0 0, L_0x19e1d40; 1 drivers +v0x1961010_0 .net "sumAB", 0 0, L_0x19e1be0; 1 drivers +S_0x19611d0 .scope generate, "genblk1[22]" "genblk1[22]" 2 47, 2 47 0, S_0x194ccf0; + .timescale 0 0; +P_0x1961390 .param/l "i" 0 2 47, +C4<010110>; +S_0x1961450 .scope module, "addermid" "FullAdder1bit" 2 48, 2 8 0, S_0x19611d0; + .timescale 0 0; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b0" + .port_info 4 /INPUT 1 "carryin" + .port_info 5 /INPUT 1 "subtract" +L_0x19e1a90/d .functor XOR 1, L_0x19e2e10, L_0x19e2160, C4<0>, C4<0>; +L_0x19e1a90 .delay 1 (20,20,20) L_0x19e1a90/d; +L_0x19e2620/d .functor XOR 1, L_0x19e2cf0, L_0x19e1a90, C4<0>, C4<0>; +L_0x19e2620 .delay 1 (20,20,20) L_0x19e2620/d; +L_0x19e2730/d .functor XOR 1, L_0x19e2620, L_0x7f93f4ea0408, C4<0>, C4<0>; +L_0x19e2730 .delay 1 (20,20,20) L_0x19e2730/d; +L_0x19e2890/d .functor AND 1, L_0x19e2cf0, L_0x19e1a90, C4<1>, C4<1>; +L_0x19e2890 .delay 1 (20,20,20) L_0x19e2890/d; +L_0x19e29f0/d .functor AND 1, L_0x19e2620, L_0x7f93f4ea0408, C4<1>, C4<1>; +L_0x19e29f0 .delay 1 (20,20,20) L_0x19e29f0/d; +L_0x19e2b50/d .functor OR 1, L_0x19e2890, L_0x19e29f0, C4<0>, C4<0>; +L_0x19e2b50 .delay 1 (20,20,20) L_0x19e2b50/d; +v0x19616c0_0 .net "a", 0 0, L_0x19e2cf0; 1 drivers +v0x19617a0_0 .net "b", 0 0, L_0x19e1a90; 1 drivers +v0x1961860_0 .net "b0", 0 0, L_0x19e2e10; 1 drivers +v0x1961930_0 .net "carryin", 0 0, L_0x7f93f4ea0408; alias, 1 drivers +v0x19619d0_0 .net "carryout", 0 0, L_0x19e2b50; alias, 1 drivers +v0x1961ae0_0 .net "cout1", 0 0, L_0x19e2890; 1 drivers +v0x1961ba0_0 .net "cout2", 0 0, L_0x19e29f0; 1 drivers +v0x1961c60_0 .net "subtract", 0 0, L_0x19e2160; alias, 1 drivers +v0x1961d00_0 .net "sum", 0 0, L_0x19e2730; 1 drivers +v0x1961e30_0 .net "sumAB", 0 0, L_0x19e2620; 1 drivers +S_0x1961ff0 .scope generate, "genblk1[23]" "genblk1[23]" 2 47, 2 47 0, S_0x194ccf0; + .timescale 0 0; +P_0x19621b0 .param/l "i" 0 2 47, +C4<010111>; +S_0x1962270 .scope module, "addermid" "FullAdder1bit" 2 48, 2 8 0, S_0x1961ff0; + .timescale 0 0; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b0" + .port_info 4 /INPUT 1 "carryin" + .port_info 5 /INPUT 1 "subtract" +L_0x19e24c0/d .functor XOR 1, L_0x19e3860, L_0x19e2b50, C4<0>, C4<0>; +L_0x19e24c0 .delay 1 (20,20,20) L_0x19e24c0/d; +L_0x19e3070/d .functor XOR 1, L_0x19e3740, L_0x19e24c0, C4<0>, C4<0>; +L_0x19e3070 .delay 1 (20,20,20) L_0x19e3070/d; +L_0x19e3180/d .functor XOR 1, L_0x19e3070, L_0x7f93f4ea0408, C4<0>, C4<0>; +L_0x19e3180 .delay 1 (20,20,20) L_0x19e3180/d; +L_0x19e32e0/d .functor AND 1, L_0x19e3740, L_0x19e24c0, C4<1>, C4<1>; +L_0x19e32e0 .delay 1 (20,20,20) L_0x19e32e0/d; +L_0x19e3440/d .functor AND 1, L_0x19e3070, L_0x7f93f4ea0408, C4<1>, C4<1>; +L_0x19e3440 .delay 1 (20,20,20) L_0x19e3440/d; +L_0x19e35a0/d .functor OR 1, L_0x19e32e0, L_0x19e3440, C4<0>, C4<0>; +L_0x19e35a0 .delay 1 (20,20,20) L_0x19e35a0/d; +v0x19624e0_0 .net "a", 0 0, L_0x19e3740; 1 drivers +v0x19625c0_0 .net "b", 0 0, L_0x19e24c0; 1 drivers +v0x1962680_0 .net "b0", 0 0, L_0x19e3860; 1 drivers +v0x1962750_0 .net "carryin", 0 0, L_0x7f93f4ea0408; alias, 1 drivers +v0x19627f0_0 .net "carryout", 0 0, L_0x19e35a0; alias, 1 drivers +v0x1962900_0 .net "cout1", 0 0, L_0x19e32e0; 1 drivers +v0x19629c0_0 .net "cout2", 0 0, L_0x19e3440; 1 drivers +v0x1962a80_0 .net "subtract", 0 0, L_0x19e2b50; alias, 1 drivers +v0x1962b20_0 .net "sum", 0 0, L_0x19e3180; 1 drivers +v0x1962c50_0 .net "sumAB", 0 0, L_0x19e3070; 1 drivers +S_0x1962e10 .scope generate, "genblk1[24]" "genblk1[24]" 2 47, 2 47 0, S_0x194ccf0; + .timescale 0 0; +P_0x1962fd0 .param/l "i" 0 2 47, +C4<011000>; +S_0x1963090 .scope module, "addermid" "FullAdder1bit" 2 48, 2 8 0, S_0x1962e10; + .timescale 0 0; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b0" + .port_info 4 /INPUT 1 "carryin" + .port_info 5 /INPUT 1 "subtract" +L_0x19e2f00/d .functor XOR 1, L_0x19e42c0, L_0x19e35a0, C4<0>, C4<0>; +L_0x19e2f00 .delay 1 (20,20,20) L_0x19e2f00/d; +L_0x19e3ad0/d .functor XOR 1, L_0x19e41a0, L_0x19e2f00, C4<0>, C4<0>; +L_0x19e3ad0 .delay 1 (20,20,20) L_0x19e3ad0/d; +L_0x19e3be0/d .functor XOR 1, L_0x19e3ad0, L_0x7f93f4ea0408, C4<0>, C4<0>; +L_0x19e3be0 .delay 1 (20,20,20) L_0x19e3be0/d; +L_0x19e3d40/d .functor AND 1, L_0x19e41a0, L_0x19e2f00, C4<1>, C4<1>; +L_0x19e3d40 .delay 1 (20,20,20) L_0x19e3d40/d; +L_0x19e3ea0/d .functor AND 1, L_0x19e3ad0, L_0x7f93f4ea0408, C4<1>, C4<1>; +L_0x19e3ea0 .delay 1 (20,20,20) L_0x19e3ea0/d; +L_0x19e4000/d .functor OR 1, L_0x19e3d40, L_0x19e3ea0, C4<0>, C4<0>; +L_0x19e4000 .delay 1 (20,20,20) L_0x19e4000/d; +v0x1963300_0 .net "a", 0 0, L_0x19e41a0; 1 drivers +v0x19633e0_0 .net "b", 0 0, L_0x19e2f00; 1 drivers +v0x19634a0_0 .net "b0", 0 0, L_0x19e42c0; 1 drivers +v0x1963570_0 .net "carryin", 0 0, L_0x7f93f4ea0408; alias, 1 drivers +v0x1963610_0 .net "carryout", 0 0, L_0x19e4000; alias, 1 drivers +v0x1963720_0 .net "cout1", 0 0, L_0x19e3d40; 1 drivers +v0x19637e0_0 .net "cout2", 0 0, L_0x19e3ea0; 1 drivers +v0x19638a0_0 .net "subtract", 0 0, L_0x19e35a0; alias, 1 drivers +v0x1963940_0 .net "sum", 0 0, L_0x19e3be0; 1 drivers +v0x1963a70_0 .net "sumAB", 0 0, L_0x19e3ad0; 1 drivers +S_0x1963c30 .scope generate, "genblk1[25]" "genblk1[25]" 2 47, 2 47 0, S_0x194ccf0; + .timescale 0 0; +P_0x1963df0 .param/l "i" 0 2 47, +C4<011001>; +S_0x1963eb0 .scope module, "addermid" "FullAdder1bit" 2 48, 2 8 0, S_0x1963c30; + .timescale 0 0; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b0" + .port_info 4 /INPUT 1 "carryin" + .port_info 5 /INPUT 1 "subtract" +L_0x19e3950/d .functor XOR 1, L_0x19e4d30, L_0x19e4000, C4<0>, C4<0>; +L_0x19e3950 .delay 1 (20,20,20) L_0x19e3950/d; +L_0x19e4540/d .functor XOR 1, L_0x19e4c10, L_0x19e3950, C4<0>, C4<0>; +L_0x19e4540 .delay 1 (20,20,20) L_0x19e4540/d; +L_0x19e4650/d .functor XOR 1, L_0x19e4540, L_0x7f93f4ea0408, C4<0>, C4<0>; +L_0x19e4650 .delay 1 (20,20,20) L_0x19e4650/d; +L_0x19e47b0/d .functor AND 1, L_0x19e4c10, L_0x19e3950, C4<1>, C4<1>; +L_0x19e47b0 .delay 1 (20,20,20) L_0x19e47b0/d; +L_0x19e4910/d .functor AND 1, L_0x19e4540, L_0x7f93f4ea0408, C4<1>, C4<1>; +L_0x19e4910 .delay 1 (20,20,20) L_0x19e4910/d; +L_0x19e4a70/d .functor OR 1, L_0x19e47b0, L_0x19e4910, C4<0>, C4<0>; +L_0x19e4a70 .delay 1 (20,20,20) L_0x19e4a70/d; +v0x1964120_0 .net "a", 0 0, L_0x19e4c10; 1 drivers +v0x1964200_0 .net "b", 0 0, L_0x19e3950; 1 drivers +v0x19642c0_0 .net "b0", 0 0, L_0x19e4d30; 1 drivers +v0x1964390_0 .net "carryin", 0 0, L_0x7f93f4ea0408; alias, 1 drivers +v0x1964430_0 .net "carryout", 0 0, L_0x19e4a70; alias, 1 drivers +v0x1964540_0 .net "cout1", 0 0, L_0x19e47b0; 1 drivers +v0x1964600_0 .net "cout2", 0 0, L_0x19e4910; 1 drivers +v0x19646c0_0 .net "subtract", 0 0, L_0x19e4000; alias, 1 drivers +v0x1964760_0 .net "sum", 0 0, L_0x19e4650; 1 drivers +v0x1964890_0 .net "sumAB", 0 0, L_0x19e4540; 1 drivers +S_0x1964a50 .scope generate, "genblk1[26]" "genblk1[26]" 2 47, 2 47 0, S_0x194ccf0; + .timescale 0 0; +P_0x1964c10 .param/l "i" 0 2 47, +C4<011010>; +S_0x1964cd0 .scope module, "addermid" "FullAdder1bit" 2 48, 2 8 0, S_0x1964a50; + .timescale 0 0; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b0" + .port_info 4 /INPUT 1 "carryin" + .port_info 5 /INPUT 1 "subtract" +L_0x19e43b0/d .functor XOR 1, L_0x19e57b0, L_0x19e4a70, C4<0>, C4<0>; +L_0x19e43b0 .delay 1 (20,20,20) L_0x19e43b0/d; +L_0x19e4fc0/d .functor XOR 1, L_0x19e5650, L_0x19e43b0, C4<0>, C4<0>; +L_0x19e4fc0 .delay 1 (20,20,20) L_0x19e4fc0/d; +L_0x19e50d0/d .functor XOR 1, L_0x19e4fc0, L_0x7f93f4ea0408, C4<0>, C4<0>; +L_0x19e50d0 .delay 1 (20,20,20) L_0x19e50d0/d; +L_0x19e5230/d .functor AND 1, L_0x19e5650, L_0x19e43b0, C4<1>, C4<1>; +L_0x19e5230 .delay 1 (20,20,20) L_0x19e5230/d; +L_0x19e5390/d .functor AND 1, L_0x19e4fc0, L_0x7f93f4ea0408, C4<1>, C4<1>; +L_0x19e5390 .delay 1 (20,20,20) L_0x19e5390/d; +L_0x19e54f0/d .functor OR 1, L_0x19e5230, L_0x19e5390, C4<0>, C4<0>; +L_0x19e54f0 .delay 1 (20,20,20) L_0x19e54f0/d; +v0x1964f40_0 .net "a", 0 0, L_0x19e5650; 1 drivers +v0x1965020_0 .net "b", 0 0, L_0x19e43b0; 1 drivers +v0x19650e0_0 .net "b0", 0 0, L_0x19e57b0; 1 drivers +v0x19651b0_0 .net "carryin", 0 0, L_0x7f93f4ea0408; alias, 1 drivers +v0x1965250_0 .net "carryout", 0 0, L_0x19e54f0; alias, 1 drivers +v0x1965360_0 .net "cout1", 0 0, L_0x19e5230; 1 drivers +v0x1965420_0 .net "cout2", 0 0, L_0x19e5390; 1 drivers +v0x19654e0_0 .net "subtract", 0 0, L_0x19e4a70; alias, 1 drivers +v0x1965580_0 .net "sum", 0 0, L_0x19e50d0; 1 drivers +v0x19656b0_0 .net "sumAB", 0 0, L_0x19e4fc0; 1 drivers +S_0x1965870 .scope generate, "genblk1[27]" "genblk1[27]" 2 47, 2 47 0, S_0x194ccf0; + .timescale 0 0; +P_0x1965a30 .param/l "i" 0 2 47, +C4<011011>; +S_0x1965af0 .scope module, "addermid" "FullAdder1bit" 2 48, 2 8 0, S_0x1965870; + .timescale 0 0; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b0" + .port_info 4 /INPUT 1 "carryin" + .port_info 5 /INPUT 1 "subtract" +L_0x19e4e20/d .functor XOR 1, L_0x19e61a0, L_0x19e54f0, C4<0>, C4<0>; +L_0x19e4e20 .delay 1 (20,20,20) L_0x19e4e20/d; +L_0x19e5a00/d .functor XOR 1, L_0x19e6080, L_0x19e4e20, C4<0>, C4<0>; +L_0x19e5a00 .delay 1 (20,20,20) L_0x19e5a00/d; +L_0x19e5ac0/d .functor XOR 1, L_0x19e5a00, L_0x7f93f4ea0408, C4<0>, C4<0>; +L_0x19e5ac0 .delay 1 (20,20,20) L_0x19e5ac0/d; +L_0x19e5c20/d .functor AND 1, L_0x19e6080, L_0x19e4e20, C4<1>, C4<1>; +L_0x19e5c20 .delay 1 (20,20,20) L_0x19e5c20/d; +L_0x19e5d80/d .functor AND 1, L_0x19e5a00, L_0x7f93f4ea0408, C4<1>, C4<1>; +L_0x19e5d80 .delay 1 (20,20,20) L_0x19e5d80/d; +L_0x19e5ee0/d .functor OR 1, L_0x19e5c20, L_0x19e5d80, C4<0>, C4<0>; +L_0x19e5ee0 .delay 1 (20,20,20) L_0x19e5ee0/d; +v0x1965d60_0 .net "a", 0 0, L_0x19e6080; 1 drivers +v0x1965e40_0 .net "b", 0 0, L_0x19e4e20; 1 drivers +v0x1965f00_0 .net "b0", 0 0, L_0x19e61a0; 1 drivers +v0x1965fd0_0 .net "carryin", 0 0, L_0x7f93f4ea0408; alias, 1 drivers +v0x1966070_0 .net "carryout", 0 0, L_0x19e5ee0; alias, 1 drivers +v0x1966180_0 .net "cout1", 0 0, L_0x19e5c20; 1 drivers +v0x1966240_0 .net "cout2", 0 0, L_0x19e5d80; 1 drivers +v0x1966300_0 .net "subtract", 0 0, L_0x19e54f0; alias, 1 drivers +v0x19663a0_0 .net "sum", 0 0, L_0x19e5ac0; 1 drivers +v0x19664d0_0 .net "sumAB", 0 0, L_0x19e5a00; 1 drivers +S_0x1966690 .scope generate, "genblk1[28]" "genblk1[28]" 2 47, 2 47 0, S_0x194ccf0; + .timescale 0 0; +P_0x1966850 .param/l "i" 0 2 47, +C4<011100>; +S_0x1966910 .scope module, "addermid" "FullAdder1bit" 2 48, 2 8 0, S_0x1966690; + .timescale 0 0; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b0" + .port_info 4 /INPUT 1 "carryin" + .port_info 5 /INPUT 1 "subtract" +L_0x19e5850/d .functor XOR 1, L_0x19e6bf0, L_0x19e5ee0, C4<0>, C4<0>; +L_0x19e5850 .delay 1 (20,20,20) L_0x19e5850/d; +L_0x19e6450/d .functor XOR 1, L_0x19e6ad0, L_0x19e5850, C4<0>, C4<0>; +L_0x19e6450 .delay 1 (20,20,20) L_0x19e6450/d; +L_0x19e6510/d .functor XOR 1, L_0x19e6450, L_0x7f93f4ea0408, C4<0>, C4<0>; +L_0x19e6510 .delay 1 (20,20,20) L_0x19e6510/d; +L_0x19e6670/d .functor AND 1, L_0x19e6ad0, L_0x19e5850, C4<1>, C4<1>; +L_0x19e6670 .delay 1 (20,20,20) L_0x19e6670/d; +L_0x19e67d0/d .functor AND 1, L_0x19e6450, L_0x7f93f4ea0408, C4<1>, C4<1>; +L_0x19e67d0 .delay 1 (20,20,20) L_0x19e67d0/d; +L_0x19e6930/d .functor OR 1, L_0x19e6670, L_0x19e67d0, C4<0>, C4<0>; +L_0x19e6930 .delay 1 (20,20,20) L_0x19e6930/d; +v0x1966b80_0 .net "a", 0 0, L_0x19e6ad0; 1 drivers +v0x1966c60_0 .net "b", 0 0, L_0x19e5850; 1 drivers +v0x1966d20_0 .net "b0", 0 0, L_0x19e6bf0; 1 drivers +v0x1966df0_0 .net "carryin", 0 0, L_0x7f93f4ea0408; alias, 1 drivers +v0x1966e90_0 .net "carryout", 0 0, L_0x19e6930; alias, 1 drivers +v0x1966fa0_0 .net "cout1", 0 0, L_0x19e6670; 1 drivers +v0x1967060_0 .net "cout2", 0 0, L_0x19e67d0; 1 drivers +v0x1967120_0 .net "subtract", 0 0, L_0x19e5ee0; alias, 1 drivers +v0x19671c0_0 .net "sum", 0 0, L_0x19e6510; 1 drivers +v0x19672f0_0 .net "sumAB", 0 0, L_0x19e6450; 1 drivers +S_0x19674b0 .scope generate, "genblk1[29]" "genblk1[29]" 2 47, 2 47 0, S_0x194ccf0; + .timescale 0 0; +P_0x1967670 .param/l "i" 0 2 47, +C4<011101>; +S_0x1967730 .scope module, "addermid" "FullAdder1bit" 2 48, 2 8 0, S_0x19674b0; + .timescale 0 0; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b0" + .port_info 4 /INPUT 1 "carryin" + .port_info 5 /INPUT 1 "subtract" +L_0x19e6290/d .functor XOR 1, L_0x19e7630, L_0x19e6930, C4<0>, C4<0>; +L_0x19e6290 .delay 1 (20,20,20) L_0x19e6290/d; +L_0x19e63e0/d .functor XOR 1, L_0x19e7510, L_0x19e6290, C4<0>, C4<0>; +L_0x19e63e0 .delay 1 (20,20,20) L_0x19e63e0/d; +L_0x19e6f50/d .functor XOR 1, L_0x19e63e0, L_0x7f93f4ea0408, C4<0>, C4<0>; +L_0x19e6f50 .delay 1 (20,20,20) L_0x19e6f50/d; +L_0x19e70b0/d .functor AND 1, L_0x19e7510, L_0x19e6290, C4<1>, C4<1>; +L_0x19e70b0 .delay 1 (20,20,20) L_0x19e70b0/d; +L_0x19e7210/d .functor AND 1, L_0x19e63e0, L_0x7f93f4ea0408, C4<1>, C4<1>; +L_0x19e7210 .delay 1 (20,20,20) L_0x19e7210/d; +L_0x19e7370/d .functor OR 1, L_0x19e70b0, L_0x19e7210, C4<0>, C4<0>; +L_0x19e7370 .delay 1 (20,20,20) L_0x19e7370/d; +v0x19679a0_0 .net "a", 0 0, L_0x19e7510; 1 drivers +v0x1967a80_0 .net "b", 0 0, L_0x19e6290; 1 drivers +v0x1967b40_0 .net "b0", 0 0, L_0x19e7630; 1 drivers +v0x1967c10_0 .net "carryin", 0 0, L_0x7f93f4ea0408; alias, 1 drivers +v0x1967cb0_0 .net "carryout", 0 0, L_0x19e7370; alias, 1 drivers +v0x1967dc0_0 .net "cout1", 0 0, L_0x19e70b0; 1 drivers +v0x1967e80_0 .net "cout2", 0 0, L_0x19e7210; 1 drivers +v0x1967f40_0 .net "subtract", 0 0, L_0x19e6930; alias, 1 drivers +v0x1967fe0_0 .net "sum", 0 0, L_0x19e6f50; 1 drivers +v0x1968110_0 .net "sumAB", 0 0, L_0x19e63e0; 1 drivers +S_0x19682d0 .scope generate, "genblk1[30]" "genblk1[30]" 2 47, 2 47 0, S_0x194ccf0; + .timescale 0 0; +P_0x1968490 .param/l "i" 0 2 47, +C4<011110>; +S_0x1968550 .scope module, "addermid" "FullAdder1bit" 2 48, 2 8 0, S_0x19682d0; + .timescale 0 0; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b0" + .port_info 4 /INPUT 1 "carryin" + .port_info 5 /INPUT 1 "subtract" +L_0x19e6ce0/d .functor XOR 1, L_0x19e8080, L_0x19e7370, C4<0>, C4<0>; +L_0x19e6ce0 .delay 1 (20,20,20) L_0x19e6ce0/d; +L_0x19e6e30/d .functor XOR 1, L_0x19e7f60, L_0x19e6ce0, C4<0>, C4<0>; +L_0x19e6e30 .delay 1 (20,20,20) L_0x19e6e30/d; +L_0x19e79a0/d .functor XOR 1, L_0x19e6e30, L_0x7f93f4ea0408, C4<0>, C4<0>; +L_0x19e79a0 .delay 1 (20,20,20) L_0x19e79a0/d; +L_0x19e7b00/d .functor AND 1, L_0x19e7f60, L_0x19e6ce0, C4<1>, C4<1>; +L_0x19e7b00 .delay 1 (20,20,20) L_0x19e7b00/d; +L_0x19e7c60/d .functor AND 1, L_0x19e6e30, L_0x7f93f4ea0408, C4<1>, C4<1>; +L_0x19e7c60 .delay 1 (20,20,20) L_0x19e7c60/d; +L_0x19e7dc0/d .functor OR 1, L_0x19e7b00, L_0x19e7c60, C4<0>, C4<0>; +L_0x19e7dc0 .delay 1 (20,20,20) L_0x19e7dc0/d; +v0x19687c0_0 .net "a", 0 0, L_0x19e7f60; 1 drivers +v0x19688a0_0 .net "b", 0 0, L_0x19e6ce0; 1 drivers +v0x1968960_0 .net "b0", 0 0, L_0x19e8080; 1 drivers +v0x1968a30_0 .net "carryin", 0 0, L_0x7f93f4ea0408; alias, 1 drivers +v0x195a750_0 .net "carryout", 0 0, L_0x19e7dc0; alias, 1 drivers +v0x195a860_0 .net "cout1", 0 0, L_0x19e7b00; 1 drivers +v0x1968ee0_0 .net "cout2", 0 0, L_0x19e7c60; 1 drivers +v0x1968f80_0 .net "subtract", 0 0, L_0x19e7370; alias, 1 drivers +v0x1969020_0 .net "sum", 0 0, L_0x19e79a0; 1 drivers +v0x1969150_0 .net "sumAB", 0 0, L_0x19e6e30; 1 drivers +S_0x19692f0 .scope generate, "genblk2[0]" "genblk2[0]" 2 57, 2 57 0, S_0x194ccf0; + .timescale 0 0; +P_0x195b030 .param/l "j" 0 2 57, +C4<00>; +L_0x19e7720/d .functor NOR 1, L_0x19ef060, L_0x19e77e0, C4<0>, C4<0>; +L_0x19e7720 .delay 1 (10,10,10) L_0x19e7720/d; +v0x19696c0_0 .net *"_s3", 0 0, L_0x19e77e0; 1 drivers +S_0x1969760 .scope generate, "genblk2[1]" "genblk2[1]" 2 57, 2 57 0, S_0x194ccf0; + .timescale 0 0; +P_0x1969970 .param/l "j" 0 2 57, +C4<01>; +L_0x19e8400/d .functor NOR 1, L_0x19e7720, L_0x19e8510, C4<0>, C4<0>; +L_0x19e8400 .delay 1 (10,10,10) L_0x19e8400/d; +v0x1969a30_0 .net *"_s3", 0 0, L_0x19e8510; 1 drivers +S_0x1969b10 .scope generate, "genblk2[2]" "genblk2[2]" 2 57, 2 57 0, S_0x194ccf0; + .timescale 0 0; +P_0x1969d20 .param/l "j" 0 2 57, +C4<010>; +L_0x19e8170/d .functor NOR 1, L_0x19e8400, L_0x19e8870, C4<0>, C4<0>; +L_0x19e8170 .delay 1 (10,10,10) L_0x19e8170/d; +v0x1969de0_0 .net *"_s3", 0 0, L_0x19e8870; 1 drivers +S_0x1969ec0 .scope generate, "genblk2[3]" "genblk2[3]" 2 57, 2 57 0, S_0x194ccf0; + .timescale 0 0; +P_0x196a0d0 .param/l "j" 0 2 57, +C4<011>; +L_0x19e89a0/d .functor NOR 1, L_0x19e8170, L_0x19e8a60, C4<0>, C4<0>; +L_0x19e89a0 .delay 1 (10,10,10) L_0x19e89a0/d; +v0x196a190_0 .net *"_s3", 0 0, L_0x19e8a60; 1 drivers +S_0x196a270 .scope generate, "genblk2[4]" "genblk2[4]" 2 57, 2 57 0, S_0x194ccf0; + .timescale 0 0; +P_0x196a480 .param/l "j" 0 2 57, +C4<0100>; +L_0x19e8670/d .functor NOR 1, L_0x19e89a0, L_0x19e87d0, C4<0>, C4<0>; +L_0x19e8670 .delay 1 (10,10,10) L_0x19e8670/d; +v0x196a540_0 .net *"_s3", 0 0, L_0x19e87d0; 1 drivers +S_0x196a620 .scope generate, "genblk2[5]" "genblk2[5]" 2 57, 2 57 0, S_0x194ccf0; + .timescale 0 0; +P_0x196a830 .param/l "j" 0 2 57, +C4<0101>; +L_0x19e8e20/d .functor NOR 1, L_0x19e8670, L_0x19e8f30, C4<0>, C4<0>; +L_0x19e8e20 .delay 1 (10,10,10) L_0x19e8e20/d; +v0x196a8f0_0 .net *"_s3", 0 0, L_0x19e8f30; 1 drivers +S_0x196a9d0 .scope generate, "genblk2[6]" "genblk2[6]" 2 57, 2 57 0, S_0x194ccf0; + .timescale 0 0; +P_0x196abe0 .param/l "j" 0 2 57, +C4<0110>; +L_0x19e8bc0/d .functor NOR 1, L_0x19e8e20, L_0x19e8d20, C4<0>, C4<0>; +L_0x19e8bc0 .delay 1 (10,10,10) L_0x19e8bc0/d; +v0x196aca0_0 .net *"_s3", 0 0, L_0x19e8d20; 1 drivers +S_0x196ad80 .scope generate, "genblk2[7]" "genblk2[7]" 2 57, 2 57 0, S_0x194ccf0; + .timescale 0 0; +P_0x196af90 .param/l "j" 0 2 57, +C4<0111>; +L_0x19e8910/d .functor NOR 1, L_0x19e8bc0, L_0x19e94b0, C4<0>, C4<0>; +L_0x19e8910 .delay 1 (10,10,10) L_0x19e8910/d; +v0x196b050_0 .net *"_s3", 0 0, L_0x19e94b0; 1 drivers +S_0x196b130 .scope generate, "genblk2[8]" "genblk2[8]" 2 57, 2 57 0, S_0x194ccf0; + .timescale 0 0; +P_0x196b340 .param/l "j" 0 2 57, +C4<01000>; +L_0x19e9090/d .functor NOR 1, L_0x19e8910, L_0x19e91a0, C4<0>, C4<0>; +L_0x19e9090 .delay 1 (10,10,10) L_0x19e9090/d; +v0x196b400_0 .net *"_s3", 0 0, L_0x19e91a0; 1 drivers +S_0x196b4e0 .scope generate, "genblk2[9]" "genblk2[9]" 2 57, 2 57 0, S_0x194ccf0; + .timescale 0 0; +P_0x196b6f0 .param/l "j" 0 2 57, +C4<01001>; +L_0x19e9890/d .functor NOR 1, L_0x19e9090, L_0x19e99a0, C4<0>, C4<0>; +L_0x19e9890 .delay 1 (10,10,10) L_0x19e9890/d; +v0x196b7b0_0 .net *"_s3", 0 0, L_0x19e99a0; 1 drivers +S_0x196b890 .scope generate, "genblk2[10]" "genblk2[10]" 2 57, 2 57 0, S_0x194ccf0; + .timescale 0 0; +P_0x196baa0 .param/l "j" 0 2 57, +C4<01010>; +L_0x19e9610/d .functor NOR 1, L_0x19e9890, L_0x19e9720, C4<0>, C4<0>; +L_0x19e9610 .delay 1 (10,10,10) L_0x19e9610/d; +v0x196bb60_0 .net *"_s3", 0 0, L_0x19e9720; 1 drivers +S_0x196bc40 .scope generate, "genblk2[11]" "genblk2[11]" 2 57, 2 57 0, S_0x194ccf0; + .timescale 0 0; +P_0x196be50 .param/l "j" 0 2 57, +C4<01011>; +L_0x19e9d90/d .functor NOR 1, L_0x19e9610, L_0x19e9ea0, C4<0>, C4<0>; +L_0x19e9d90 .delay 1 (10,10,10) L_0x19e9d90/d; +v0x196bf10_0 .net *"_s3", 0 0, L_0x19e9ea0; 1 drivers +S_0x196bff0 .scope generate, "genblk2[12]" "genblk2[12]" 2 57, 2 57 0, S_0x194ccf0; + .timescale 0 0; +P_0x196c200 .param/l "j" 0 2 57, +C4<01100>; +L_0x19e9b00/d .functor NOR 1, L_0x19e9d90, L_0x19e9c10, C4<0>, C4<0>; +L_0x19e9b00 .delay 1 (10,10,10) L_0x19e9b00/d; +v0x196c2c0_0 .net *"_s3", 0 0, L_0x19e9c10; 1 drivers +S_0x196c3a0 .scope generate, "genblk2[13]" "genblk2[13]" 2 57, 2 57 0, S_0x194ccf0; + .timescale 0 0; +P_0x196c5b0 .param/l "j" 0 2 57, +C4<01101>; +L_0x19ea2a0/d .functor NOR 1, L_0x19e9b00, L_0x19ea3b0, C4<0>, C4<0>; +L_0x19ea2a0 .delay 1 (10,10,10) L_0x19ea2a0/d; +v0x196c670_0 .net *"_s3", 0 0, L_0x19ea3b0; 1 drivers +S_0x196c750 .scope generate, "genblk2[14]" "genblk2[14]" 2 57, 2 57 0, S_0x194ccf0; + .timescale 0 0; +P_0x196c960 .param/l "j" 0 2 57, +C4<01110>; +L_0x19ea000/d .functor NOR 1, L_0x19ea2a0, L_0x19ea110, C4<0>, C4<0>; +L_0x19ea000 .delay 1 (10,10,10) L_0x19ea000/d; +v0x196ca20_0 .net *"_s3", 0 0, L_0x19ea110; 1 drivers +S_0x196cb00 .scope generate, "genblk2[15]" "genblk2[15]" 2 57, 2 57 0, S_0x194ccf0; + .timescale 0 0; +P_0x196cd10 .param/l "j" 0 2 57, +C4<01111>; +L_0x19e9300/d .functor NOR 1, L_0x19ea000, L_0x19ea9d0, C4<0>, C4<0>; +L_0x19e9300 .delay 1 (10,10,10) L_0x19e9300/d; +v0x196cdd0_0 .net *"_s3", 0 0, L_0x19ea9d0; 1 drivers +S_0x196ceb0 .scope generate, "genblk2[16]" "genblk2[16]" 2 57, 2 57 0, S_0x194ccf0; + .timescale 0 0; +P_0x196d0c0 .param/l "j" 0 2 57, +C4<010000>; +L_0x19ea510/d .functor NOR 1, L_0x19e9300, L_0x19ea620, C4<0>, C4<0>; +L_0x19ea510 .delay 1 (10,10,10) L_0x19ea510/d; +v0x196d180_0 .net *"_s3", 0 0, L_0x19ea620; 1 drivers +S_0x196d260 .scope generate, "genblk2[17]" "genblk2[17]" 2 57, 2 57 0, S_0x194ccf0; + .timescale 0 0; +P_0x196d470 .param/l "j" 0 2 57, +C4<010001>; +L_0x19ead80/d .functor NOR 1, L_0x19ea510, L_0x19eae40, C4<0>, C4<0>; +L_0x19ead80 .delay 1 (10,10,10) L_0x19ead80/d; +v0x196d530_0 .net *"_s3", 0 0, L_0x19eae40; 1 drivers +S_0x196d610 .scope generate, "genblk2[18]" "genblk2[18]" 2 57, 2 57 0, S_0x194ccf0; + .timescale 0 0; +P_0x196d820 .param/l "j" 0 2 57, +C4<010010>; +L_0x19eaac0/d .functor NOR 1, L_0x19ead80, L_0x19eabd0, C4<0>, C4<0>; +L_0x19eaac0 .delay 1 (10,10,10) L_0x19eaac0/d; +v0x196d8e0_0 .net *"_s3", 0 0, L_0x19eabd0; 1 drivers +S_0x196d9c0 .scope generate, "genblk2[19]" "genblk2[19]" 2 57, 2 57 0, S_0x194ccf0; + .timescale 0 0; +P_0x196dbd0 .param/l "j" 0 2 57, +C4<010011>; +L_0x19eb220/d .functor NOR 1, L_0x19eaac0, L_0x19eb330, C4<0>, C4<0>; +L_0x19eb220 .delay 1 (10,10,10) L_0x19eb220/d; +v0x196dc90_0 .net *"_s3", 0 0, L_0x19eb330; 1 drivers +S_0x196dd70 .scope generate, "genblk2[20]" "genblk2[20]" 2 57, 2 57 0, S_0x194ccf0; + .timescale 0 0; +P_0x196df80 .param/l "j" 0 2 57, +C4<010100>; +L_0x19eafa0/d .functor NOR 1, L_0x19eb220, L_0x19eb0b0, C4<0>, C4<0>; +L_0x19eafa0 .delay 1 (10,10,10) L_0x19eafa0/d; +v0x196e040_0 .net *"_s3", 0 0, L_0x19eb0b0; 1 drivers +S_0x196e120 .scope generate, "genblk2[21]" "genblk2[21]" 2 57, 2 57 0, S_0x194ccf0; + .timescale 0 0; +P_0x196e330 .param/l "j" 0 2 57, +C4<010101>; +L_0x19eb720/d .functor NOR 1, L_0x19eafa0, L_0x19eb830, C4<0>, C4<0>; +L_0x19eb720 .delay 1 (10,10,10) L_0x19eb720/d; +v0x196e3f0_0 .net *"_s3", 0 0, L_0x19eb830; 1 drivers +S_0x196e4d0 .scope generate, "genblk2[22]" "genblk2[22]" 2 57, 2 57 0, S_0x194ccf0; + .timescale 0 0; +P_0x196e6e0 .param/l "j" 0 2 57, +C4<010110>; +L_0x19eb490/d .functor NOR 1, L_0x19eb720, L_0x19eb5a0, C4<0>, C4<0>; +L_0x19eb490 .delay 1 (10,10,10) L_0x19eb490/d; +v0x196e7a0_0 .net *"_s3", 0 0, L_0x19eb5a0; 1 drivers +S_0x196e880 .scope generate, "genblk2[23]" "genblk2[23]" 2 57, 2 57 0, S_0x194ccf0; + .timescale 0 0; +P_0x196ea90 .param/l "j" 0 2 57, +C4<010111>; +L_0x19ebc30/d .functor NOR 1, L_0x19eb490, L_0x19ebd40, C4<0>, C4<0>; +L_0x19ebc30 .delay 1 (10,10,10) L_0x19ebc30/d; +v0x196eb50_0 .net *"_s3", 0 0, L_0x19ebd40; 1 drivers +S_0x196ec30 .scope generate, "genblk2[24]" "genblk2[24]" 2 57, 2 57 0, S_0x194ccf0; + .timescale 0 0; +P_0x196ee40 .param/l "j" 0 2 57, +C4<011000>; +L_0x19eb990/d .functor NOR 1, L_0x19ebc30, L_0x19ebaa0, C4<0>, C4<0>; +L_0x19eb990 .delay 1 (10,10,10) L_0x19eb990/d; +v0x196ef00_0 .net *"_s3", 0 0, L_0x19ebaa0; 1 drivers +S_0x196efe0 .scope generate, "genblk2[25]" "genblk2[25]" 2 57, 2 57 0, S_0x194ccf0; + .timescale 0 0; +P_0x196f1f0 .param/l "j" 0 2 57, +C4<011001>; +L_0x19ec150/d .functor NOR 1, L_0x19eb990, L_0x19ec260, C4<0>, C4<0>; +L_0x19ec150 .delay 1 (10,10,10) L_0x19ec150/d; +v0x196f2b0_0 .net *"_s3", 0 0, L_0x19ec260; 1 drivers +S_0x196f390 .scope generate, "genblk2[26]" "genblk2[26]" 2 57, 2 57 0, S_0x194ccf0; + .timescale 0 0; +P_0x196f5a0 .param/l "j" 0 2 57, +C4<011010>; +L_0x19ebea0/d .functor NOR 1, L_0x19ec150, L_0x19ebfb0, C4<0>, C4<0>; +L_0x19ebea0 .delay 1 (10,10,10) L_0x19ebea0/d; +v0x196f660_0 .net *"_s3", 0 0, L_0x19ebfb0; 1 drivers +S_0x196f740 .scope generate, "genblk2[27]" "genblk2[27]" 2 57, 2 57 0, S_0x194ccf0; + .timescale 0 0; +P_0x196f950 .param/l "j" 0 2 57, +C4<011011>; +L_0x19ec680/d .functor NOR 1, L_0x19ebea0, L_0x19ec790, C4<0>, C4<0>; +L_0x19ec680 .delay 1 (10,10,10) L_0x19ec680/d; +v0x196fa10_0 .net *"_s3", 0 0, L_0x19ec790; 1 drivers +S_0x196faf0 .scope generate, "genblk2[28]" "genblk2[28]" 2 57, 2 57 0, S_0x194ccf0; + .timescale 0 0; +P_0x196fd00 .param/l "j" 0 2 57, +C4<011100>; +L_0x19ec3c0/d .functor NOR 1, L_0x19ec680, L_0x19ec4d0, C4<0>, C4<0>; +L_0x19ec3c0 .delay 1 (10,10,10) L_0x19ec3c0/d; +v0x196fdc0_0 .net *"_s3", 0 0, L_0x19ec4d0; 1 drivers + .scope S_0x190a3b0; +T_0 ; + %wait E_0x1907540; + %load/vec4 v0x18ce300_0; + %dup/vec4; + %pushi/vec4 0, 0, 3; + %cmp/u; + %jmp/1 T_0.0, 6; + %dup/vec4; + %pushi/vec4 1, 0, 3; + %cmp/u; + %jmp/1 T_0.1, 6; + %dup/vec4; + %pushi/vec4 2, 0, 3; + %cmp/u; + %jmp/1 T_0.2, 6; + %dup/vec4; + %pushi/vec4 3, 0, 3; + %cmp/u; + %jmp/1 T_0.3, 6; + %dup/vec4; + %pushi/vec4 4, 0, 3; + %cmp/u; + %jmp/1 T_0.4, 6; + %dup/vec4; + %pushi/vec4 5, 0, 3; + %cmp/u; + %jmp/1 T_0.5, 6; + %dup/vec4; + %pushi/vec4 6, 0, 3; + %cmp/u; + %jmp/1 T_0.6, 6; + %dup/vec4; + %pushi/vec4 7, 0, 3; + %cmp/u; + %jmp/1 T_0.7, 6; + %jmp T_0.8; +T_0.0 ; + %pushi/vec4 0, 0, 3; + %store/vec4 v0x17b8fa0_0, 0, 3; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x17b6f60_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x17bafe0_0, 0, 1; + %jmp T_0.8; +T_0.1 ; + %pushi/vec4 0, 0, 3; + %store/vec4 v0x17b8fa0_0, 0, 3; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x17b6f60_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x17bafe0_0, 0, 1; + %jmp T_0.8; +T_0.2 ; + %pushi/vec4 1, 0, 3; + %store/vec4 v0x17b8fa0_0, 0, 3; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x17b6f60_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x17bafe0_0, 0, 1; + %jmp T_0.8; +T_0.3 ; + %pushi/vec4 2, 0, 3; + %store/vec4 v0x17b8fa0_0, 0, 3; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x17b6f60_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x17bafe0_0, 0, 1; + %jmp T_0.8; +T_0.4 ; + %pushi/vec4 3, 0, 3; + %store/vec4 v0x17b8fa0_0, 0, 3; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x17b6f60_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x17bafe0_0, 0, 1; + %jmp T_0.8; +T_0.5 ; + %pushi/vec4 3, 0, 3; + %store/vec4 v0x17b8fa0_0, 0, 3; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x17b6f60_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x17bafe0_0, 0, 1; + %jmp T_0.8; +T_0.6 ; + %pushi/vec4 4, 0, 3; + %store/vec4 v0x17b8fa0_0, 0, 3; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x17b6f60_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x17bafe0_0, 0, 1; + %jmp T_0.8; +T_0.7 ; + %pushi/vec4 4, 0, 3; + %store/vec4 v0x17b8fa0_0, 0, 3; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x17b6f60_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x17bafe0_0, 0, 1; + %jmp T_0.8; +T_0.8 ; + %pop/vec4 1; + %jmp T_0; + .thread T_0, $push; + .scope S_0x17ef170; +T_1 ; + %wait E_0x17bf140; + %load/vec4 v0x194b220_0; + %dup/vec4; + %pushi/vec4 0, 0, 3; + %cmp/u; + %jmp/1 T_1.0, 6; + %dup/vec4; + %pushi/vec4 1, 0, 3; + %cmp/u; + %jmp/1 T_1.1, 6; + %dup/vec4; + %pushi/vec4 2, 0, 3; + %cmp/u; + %jmp/1 T_1.2, 6; + %dup/vec4; + %pushi/vec4 3, 0, 3; + %cmp/u; + %jmp/1 T_1.3, 6; + %dup/vec4; + %pushi/vec4 4, 0, 3; + %cmp/u; + %jmp/1 T_1.4, 6; + %jmp T_1.5; +T_1.0 ; + %load/vec4 v0x194bac0_0; + %store/vec4 v0x194be40_0, 0, 32; + %load/vec4 v0x194ae50_0; + %store/vec4 v0x194acb0_0, 0, 1; + %load/vec4 v0x194c050_0; + %store/vec4 v0x194bee0_0, 0, 1; + %load/vec4 v0x194b6a0_0; + %store/vec4 v0x194b530_0, 0, 1; + %jmp T_1.5; +T_1.1 ; + %load/vec4 v0x194bd70_0; + %store/vec4 v0x194be40_0, 0, 32; + %load/vec4 v0x194b0b0_0; + %store/vec4 v0x194acb0_0, 0, 1; + %load/vec4 v0x194c290_0; + %store/vec4 v0x194bee0_0, 0, 1; + %load/vec4 v0x194b910_0; + %store/vec4 v0x194b530_0, 0, 1; + %jmp T_1.5; +T_1.2 ; + %load/vec4 v0x194bca0_0; + %store/vec4 v0x194be40_0, 0, 32; + %load/vec4 v0x194afc0_0; + %store/vec4 v0x194acb0_0, 0, 1; + %load/vec4 v0x194c1c0_0; + %store/vec4 v0x194bee0_0, 0, 1; + %load/vec4 v0x194b840_0; + %store/vec4 v0x194b530_0, 0, 1; + %jmp T_1.5; +T_1.3 ; + %load/vec4 v0x194bb60_0; + %store/vec4 v0x194be40_0, 0, 32; + %load/vec4 v0x194ad90_0; + %store/vec4 v0x194acb0_0, 0, 1; + %load/vec4 v0x194bf80_0; + %store/vec4 v0x194bee0_0, 0, 1; + %load/vec4 v0x194b5d0_0; + %store/vec4 v0x194b530_0, 0, 1; + %jmp T_1.5; +T_1.4 ; + %load/vec4 v0x194bc00_0; + %store/vec4 v0x194be40_0, 0, 32; + %load/vec4 v0x194aef0_0; + %store/vec4 v0x194acb0_0, 0, 1; + %load/vec4 v0x194c120_0; + %store/vec4 v0x194bee0_0, 0, 1; + %load/vec4 v0x194b770_0; + %store/vec4 v0x194b530_0, 0, 1; + %jmp T_1.5; +T_1.5 ; + %pop/vec4 1; + %jmp T_1; + .thread T_1, $push; + .scope S_0x17a8e00; +T_2 ; + %pushi/vec4 10, 0, 32; + %store/vec4 v0x1971a00_0, 0, 32; + %pushi/vec4 18, 0, 32; + %store/vec4 v0x1971ac0_0, 0, 32; + %vpi_call 2 312 "$display", v0x1971c00_0 {0 0 0}; + %end; + .thread T_2; +# The file index is used to find the file name in the following table. +:file_names 3; + "N/A"; + ""; + "alu.v"; diff --git a/alu.t.v b/alu.t.v new file mode 100644 index 0000000..71cca2f --- /dev/null +++ b/alu.t.v @@ -0,0 +1,135 @@ +// ALU testbench +`include "alu.v" + +module testalu (); +reg[31:0] operandA; +reg[31:0] operandB; +reg[2:0] command; + +wire[31:0] result; +wire carryout; +wire zero; +wire overflow; + + ALU alu(result, carryout, zero, overflow, operandA, operandB, command); + + initial begin + $dumpfile("alu.vcd"); + $dumpvars(); + // add test cases + $display("Add test cases"); + // Case 1: Inputs consist of all 0s. + operandA = 32'b00000000000000000000000000000000; operandB = 32'b00000000000000000000000000000000; command = 3'b000; #1500 + if (result !== 32'b00000000000000000000000000000000) $display("Add test case 1 result failed.\nExpected result: %b\tActual result: %b", 32'd0, result); + if (carryout !== 0) $display("Add test case 1 Cout failed\nExpected Cout: %b\tActual Cout: %b", 1'b0, carryout); + if (overflow !== 0) $display("Add test case 1 Overflow failed\nExpected Overflow: %b\tActual Overflow: %b", 1'b0, overflow); + if (zero !== 1) $display("Add test case 1 Zero failed\nExpected Zero: %b\tActual Zero: %b", 1'b1, zero); + + // Case 2: Inputs consist of all 1s. + operandA = 32'b11111111111111111111111111111111; operandB = 32'b11111111111111111111111111111111; command = 3'b000; #1500 + if (result != 32'b11111111111111111111111111111110) $display("Add test case 2 result failed.\nExpected result: %b\tActual result: %b", 32'b11111111111111111111111111111110, result); + if (carryout !== 1) $display("Add test case 2 Cout failed\nExpected Cout: %b\tActual Cout: %b", 1'b1, carryout); + if (overflow !== 0) $display("Add test case 2 Overflow failed\nExpected Overflow: %b\tActual Overflow: %b", 1'b0, overflow); + if (zero !== 0) $display("Add test case 2 Zero failed\nExpected Zero: %b\tActual Zero: %b", 1'b0, zero); + + // Case 3: Overflow and Carryout. + operandA = 32'b10000011111111111111111111111111; operandB = 32'b10111111111111111111111111111111; command = 3'b000; #1500 + if (result != 32'b01000011111111111111111111111110) $display("Add test case 3 result failed.\nExpected result: %b\tActual result: %b", 32'b01000011111111111111111111111110, result); + if (carryout !== 1) $display("Add test case 3 Cout failed\nExpected Cout: %b\tActual Cout: %b", 1'b1, carryout); + if (overflow !== 1) $display("Add test case Overflow failed\nExpected Overflow: %b\tActual Overflow: %b", 1'b1, overflow); + if (zero !== 0) $display("Add test case Zero failed\nExpected Zero: %b\tActual Zero: %b", 1'b0, zero); + + // Case 4: Overflow only. + operandA = 32'b01000000000000000000000000001110; operandB = 32'b01000000000000000000000000001100; command = 3'b000; #1500 + if (result != 32'b10000000000000000000000000011010) $display("Add test case 4 result failed.\nExpected result: %b\tActual result: %b", 32'b10000000000000000000000000011010, result); + if (carryout !== 0) $display("Add test case 4 Cout failed\nExpected Cout: %b\tActual Cout: %b", 1'b1, carryout); + if (overflow !== 1) $display("Add test case 4 Overflow failed\nExpected Overflow: %b\tActual Overflow: %b", 1'b1, overflow); + if (zero !== 0) $display("Add test case 4 Zero failed\nExpected Zero: %b\tActual Zero: %b", 1'b0, zero); + + // subtract test cases + $display("Subtract test cases"); + // Case 1: All zeros + operandA = 32'b00000000000000000000000000000000; operandB = 32'b00000000000000000000000000000000; command = 3'b001; #1500 + if (result !== 32'b00000000000000000000000000000000) $display("Subtract test case 1 result failed.\nExpected result: %b\tActual result: %b", 32'd0, result); + if (carryout !== 0) $display("Subtract test case 1 Cout failed\nExpected Cout: %b\tActual Cout: %b", 1'b1, carryout); + if (overflow !== 1) $display("Subtract test case 1 Overflow failed\nExpected Overflow: %b\tActual Overflow: %b", 1'b0, overflow); + if (zero !== 1) $display("Subtract test case 1 Zero failed\nExpected Zero: %b\tActual Zero: %b", 1'b1, zero); + + // Case 2: Subtract a negative number + operandA = 32'b00000000000000000000000000000000; operandB = 32'b11111111111111111111111111111111; command = 3'b001; #1500 + if (result !== 32'b00000000000000000000000000000001) $display("Subtract test case 2 result failed.\nExpected result: %b\tActual result: %b", 32'b00000000000000000000000000000001, result); + if (carryout !== 0) $display("Subtract test case 2 Cout failed\nExpected Cout: %b\tActual Cout: %b", 1'b0, carryout); + if (overflow !== 0) $display("Subtract test case 2 Overflow failed\nExpected Overflow: %b\tActual Overflow: %b", 1'b0, overflow); + if (zero !== 0) $display("Subtract test case 2 Zero failed\nExpected Zero: %b\tActual Zero: %b", 1'b0, zero); + + // Case 3: Subtract a positive number + operandA = 32'b00000000000000000000000000000000; operandB = 32'b00011111111111111111111111111111; command = 3'b001; #1500 + if (result !== 32'b11100000000000000000000000000001) $display("Subtract test case 2 result failed.\nExpected result: %b\tActual result: %b", 32'b11100000000000000000000000000001, result); + if (carryout !== 0) $display("Subtract test case 2 Cout failed\nExpected Cout: %b\tActual Cout: %b", 1'b0, carryout); + if (overflow !== 0) $display("Subtract test case 2 Overflow failed\nExpected Overflow: %b\tActual Overflow: %b", 1'b0, overflow); + if (zero !== 0) $display("Subtract test case 2 Zero failed\nExpected Zero: %b\tActual Zero: %b", 1'b0, zero); + + // Xor test cases + // two inputs the same; two inputs totally different; two inputs with some bits corresponding + operandA = 32'b01010101010101010101010101010101; operandB = 32'b01010101010101010101010101010101; command = 3'b010; #1500 + if (result !== 32'b00000000000000000000000000000000) $display("Xor test case 1 (inputs same) failed"); + operandA = 32'b01010101010101010101010101010101; operandB = 32'b10101010101010101010101010101010; command = 3'b010; #1500 + if (result !== 32'b11111111111111111111111111111111) $display("Xor test case 2 (inputs different) failed"); + operandA = 32'b01010101010101010101010101010101; operandB = 32'b01011010010110100101101001011010; command = 3'b010; #1500 + if (result !== 32'b00001111000011110000111100001111) $display("Xor test case 3 (inputs somewhat corresponding) failed"); + + // SLT test cases + // inputs greater than, less than, equal to; for positive, negatives, and combinations of each + operandA = 32'd5000; operandB = 32'd100; command = 3'b011; #1500 + if (result !== 32'b00000000000000000000000000000000) $display("SLT test case 1 (postive greater) failed"); + operandA = 32'd50; operandB = 32'd100; command = 3'b011; #1500 + if (result !== 32'b00000000000000000000000000000001) $display("SLT test case 1 (postive less) failed"); + operandA = 32'd100; operandB = 32'd100; command = 3'b011; #1500 + if (result !== 32'b00000000000000000000000000000000) $display("SLT test case 3 (postive equal) failed"); + operandA = -32'd5000; operandB = -32'd100; command = 3'b011; #1500 + if (result !== 32'b00000000000000000000000000000001) $display("SLT test case 4 (negative less) failed"); + operandA = -32'd100; operandB = -32'd5000; command = 3'b011; #1500 + if (result !== 32'b00000000000000000000000000000000) $display("SLT test case 5 (negative greater) failed"); + operandA = -32'd100; operandB = 32'd100; command = 3'b011; #1500 + if (result !== 32'b00000000000000000000000000000001) $display("SLT test case 6 (negative and positive) failed"); + operandA = 32'd100; operandB = -32'd100; command = 3'b011; #1500 + if (result !== 32'b00000000000000000000000000000000) $display("SLT test case 7 (positive and negative) failed"); + + // And test cases + // two inputs exactly the same; two inputs totally different; two inputs with some bits corresponding + operandA = 32'b01010101010101010101010101010101; operandB = 32'b01010101010101010101010101010101; command = 3'b100; #1500 + if (result !== 32'b01010101010101010101010101010101) $display("And test case 1 (inputs same) failed"); + operandA = 32'b01010101010101010101010101010101; operandB = 32'b10101010101010101010101010101010; command = 3'b100; #1500 + if (result !== 32'b00000000000000000000000000000000) $display("And test case 2 (inputs different) failed"); + operandA = 32'b01010101010101010101010101010101; operandB = 32'b01011010010110100101101001011010; command = 3'b100; #1500 + if (result !== 32'b01010000010100000101000001010000) $display("And test case 3 (inputs somewhat corresponding) failed"); + + // Nand test cases + // two inputs exactly the same; two inputs totally different; two inputs with some bits corresponding + operandA = 32'b01010101010101010101010101010101; operandB = 32'b01010101010101010101010101010101; command = 3'b101; #1500 + if (result !== 32'b10101010101010101010101010101010) $display("Nand test case 1 (inputs same) failed"); + operandA = 32'b01010101010101010101010101010101; operandB = 32'b10101010101010101010101010101010; command = 3'b101; #1500 + if (result !== 32'b11111111111111111111111111111111) $display("Nand test case 2 (inputs different) failed"); + operandA = 32'b01010101010101010101010101010101; operandB = 32'b01011010010110100101101001011010; command = 3'b101; #1500 + if (result !== 32'b10101111101011111010111110101111) $displayb("Nand test case 3 (inputs somewhat corresponding) failed"); + + // Nor test cases + // two inputs exactly the same; two inputs totally different; two inputs with some bits corresponding + operandA = 32'b01010101010101010101010101010101; operandB = 32'b01010101010101010101010101010101; command = 3'b111; #1500 + if (result !== 32'b10101010101010101010101010101010) $display("Nor test case 1 (inputs same) failed"); + operandA = 32'b01010101010101010101010101010101; operandB = 32'b10101010101010101010101010101010; command = 3'b111; #1500 + if (result !== 32'b00000000000000000000000000000000) $display("Nor test case 2 (inputs different) failed"); + operandA = 32'b01010101010101010101010101010101; operandB = 32'b01011010010110100101101001011010; command = 3'b111; #1500 + if (result !== 32'b10100000101000001010000010100000) $display("Nor test case 3 (inputs somewhat corresponding) failed"); + + // Or test cases + // two inputs exactly the same; two inputs totally different; two inputs with some bits corresponding + operandA = 32'b01010101010101010101010101010101; operandB = 32'b01010101010101010101010101010101; command = 3'b110; #1500 + if (result !== 32'b01010101010101010101010101010101) $display("Or test case 1 (inputs same) failed"); + operandA = 32'b01010101010101010101010101010101; operandB = 32'b10101010101010101010101010101010; command = 3'b110; #1500 + if (result !== 32'b11111111111111111111111111111111) $display("Or test case 2 (inputs different) failed"); + operandA = 32'b01010101010101010101010101010101; operandB = 32'b01011010010110100101101001011010; command = 3'b110; #1500 + if (result !== 32'b01011111010111110101111101011111) $display("Or test case 3 (inputs somewhat corresponding) failed"); + $finish(); +end +endmodule // testalu diff --git a/alu.v b/alu.v new file mode 100644 index 0000000..6c517e4 --- /dev/null +++ b/alu.v @@ -0,0 +1,128 @@ +// Implementation of an ALU that performs addition, subtraction, XOR, SLT, OR, NOR, NAND, and AND operations. + +`include "operations.v" + +// Definine command numbers +`define CADD 3'd0 +`define CSUB 3'd1 +`define CXOR 3'd2 +`define CSLT 3'd3 +`define CAND 3'd4 +`define CNAND 3'd5 +`define CNOR 3'd6 +`define COR 3'd7 + +// Implementation of a control logic LUT to determine ALU operation. +module ALUcontrolLUT +( +output reg[2:0] muxindex, +output reg invertB, +output reg othercontrolsignal, +input[2:0] ALUcommand +); + + always @(ALUcommand) begin + case (ALUcommand) + `CADD: begin muxindex = 0; invertB=0; othercontrolsignal = 0; end + `CSUB: begin muxindex = 0; invertB=1; othercontrolsignal = 0; end + `CXOR: begin muxindex = 1; invertB=0; othercontrolsignal = 0; end + `CSLT: begin muxindex = 2; invertB=0; othercontrolsignal = 0; end + `CAND: begin muxindex = 3; invertB=0; othercontrolsignal = 0; end + `CNAND: begin muxindex = 3; invertB=0; othercontrolsignal = 1; end + `CNOR: begin muxindex = 4; invertB=0; othercontrolsignal = 1; end + `COR: begin muxindex = 4; invertB=0; othercontrolsignal = 0; end + endcase + end +endmodule + +// Define macros for second LUT. +`define MADDSUB 3'd0 +`define MXOR 3'd1 +`define MSLT 3'd2 +`define MANDNAND 3'd3 +`define MNOROR 3'd4 + +// Decide which operation results to output based on the results of the index +// generated by the control LUT. +module ALUoutputLUT +( +input[31:0] operandA, +input[31:0] operandB, +input[2:0] muxindex, +input invertB, +input othercontrolsignal, +output reg[31:0] result, +output reg carryout, +output reg zero, +output reg overflow +); + +// The results of each module. +wire[31:0] resAddsub; +wire[31:0] resXor; +wire[31:0] resSlt; +wire[31:0] resAndnand; +wire[31:0] resNoror; + +// The carryout flags of each module. +wire carryoutAddSub; +wire carryoutXor; +wire carryoutSLT; +wire carryoutAND; +wire carryoutOR; + +// The zero flags of each module. +wire zeroAddSub; +wire zeroXor; +wire zeroSLT; +wire zeroAND; +wire zeroOR; + +// The overflow flags of each module. +wire overflowAddSub; +wire overflowXor; +wire overflowSLT; +wire overflowAND; +wire overflowOR; + +AddSub #1000 dut0 (resAddsub, carryoutAddSub, zeroAddSub, overflowAddSub, operandA, operandB, invertB); +alu32bitxor dut1 (resXor, carryoutXor, zeroXor, overflowXor, operandA, operandB); +alu32bitslt dut2 (resSlt, carryoutSLT, zeroSLT, overflowSLT, operandA, operandB); +alu32bitandn dut3 (resAndnand, carryoutAND, zeroAND, overflowAND, operandA, operandB, othercontrolsignal); +NOROR dut4 (resNoror, carryoutOR, zeroOR, overflowOR, operandA, operandB, othercontrolsignal); + +// The LUT behaves as a set of muxes that choose each bit of the result and each flag based on the muxindex +// it is passed as an address. +always @(muxindex or resAddsub or resXor or resSlt or resAndnand or resNoror) begin + case(muxindex) + `MADDSUB: begin result = resAddsub; carryout = carryoutAddSub; zero = zeroAddSub; overflow = overflowAddSub; end + `MXOR: begin result = resXor; carryout = carryoutXor; zero = zeroXor; overflow = overflowXor; end + `MSLT: begin result = resSlt; carryout = carryoutSLT; zero = zeroSLT; overflow = overflowSLT; end + `MANDNAND: begin result = resAndnand; carryout = carryoutAND; zero = zeroAND; overflow = overflowAND; end + `MNOROR: begin result = resNoror; carryout = carryoutOR; zero = zeroOR; overflow = overflowOR; end + endcase +end + +endmodule + +// Implementation of the ALU in it's entirety. +module ALU +( +output[31:0] result, +output carryout, +output zero, +output overflow, +input[31:0] operandA, +input[31:0] operandB, +input[2:0] command +); + +wire[2:0] muxindex; +wire invertB; +wire othercontrolsignal; + +ALUcontrolLUT controlLookup (muxindex, invertB, othercontrolsignal, command); + +ALUoutputLUT outputLookup (operandA, operandB, muxindex, invertB, othercontrolsignal, result, carryout, zero, overflow); + +endmodule \ No newline at end of file diff --git a/alu.vcd b/alu.vcd new file mode 100644 index 0000000..106ab92 --- /dev/null +++ b/alu.vcd @@ -0,0 +1,47629 @@ +$date + Fri Oct 13 00:44:23 2017 +$end +$version + Icarus Verilog +$end +$timescale + 1s +$end +$scope module testalu $end +$var wire 1 ! zero $end +$var wire 32 " result [31:0] $end +$var wire 1 # overflow $end +$var wire 1 $ carryout $end +$var reg 3 % command [2:0] $end +$var reg 32 & operandA [31:0] $end +$var reg 32 ' operandB [31:0] $end +$scope module alu $end +$var wire 3 ( command [2:0] $end +$var wire 32 ) operandA [31:0] $end +$var wire 32 * operandB [31:0] $end +$var wire 1 ! zero $end +$var wire 32 + result [31:0] $end +$var wire 1 # overflow $end +$var wire 1 , othercontrolsignal $end +$var wire 3 - muxindex [2:0] $end +$var wire 1 . invertB $end +$var wire 1 $ carryout $end +$scope module controlLookup $end +$var wire 3 / ALUcommand [2:0] $end +$var reg 1 . invertB $end +$var reg 3 0 muxindex [2:0] $end +$var reg 1 , othercontrolsignal $end +$upscope $end +$scope module outputLookup $end +$var wire 1 1 carryoutAND $end +$var wire 1 2 carryoutSLT $end +$var wire 1 3 carryoutXor $end +$var wire 1 . invertB $end +$var wire 3 4 muxindex [2:0] $end +$var wire 32 5 operandA [31:0] $end +$var wire 32 6 operandB [31:0] $end +$var wire 1 , othercontrolsignal $end +$var wire 1 7 overflowAND $end +$var wire 1 8 overflowSLT $end +$var wire 1 9 overflowXor $end +$var wire 1 : zeroAND $end +$var wire 1 ; zeroSLT $end +$var wire 1 < zeroXor $end +$var wire 1 = zeroOR $end +$var wire 1 > zeroAddSub $end +$var wire 32 ? resXor [31:0] $end +$var wire 32 @ resSlt [31:0] $end +$var wire 32 A resNoror [31:0] $end +$var wire 32 B resAndnand [31:0] $end +$var wire 32 C resAddsub [31:0] $end +$var wire 1 D overflowOR $end +$var wire 1 E overflowAddSub $end +$var wire 1 F carryoutOR $end +$var wire 1 G carryoutAddSub $end +$var reg 1 $ carryout $end +$var reg 1 # overflow $end +$var reg 32 H result [31:0] $end +$var reg 1 ! zero $end +$scope module dut0 $end +$var wire 1 I nzero $end +$var wire 32 J operandA [31:0] $end +$var wire 32 K operandB [31:0] $end +$var wire 1 E overflow $end +$var wire 1 . subtract $end +$var wire 1 > zero $end +$var wire 32 L result [31:0] $end +$var wire 31 M carryoutmid [30:0] $end +$var wire 1 G carryout $end +$scope begin ripple[1] $end +$scope module addermid $end +$var wire 1 N a $end +$var wire 1 O b $end +$var wire 1 P b0 $end +$var wire 1 Q carryin $end +$var wire 1 R carryout $end +$var wire 1 S cout1 $end +$var wire 1 T cout2 $end +$var wire 1 . subtract $end +$var wire 1 U sum $end +$var wire 1 V sumAB $end +$upscope $end +$upscope $end +$scope begin ripple[2] $end +$scope module addermid $end +$var wire 1 W a $end +$var wire 1 X b $end +$var wire 1 Y b0 $end +$var wire 1 Z carryin $end +$var wire 1 [ carryout $end +$var wire 1 \ cout1 $end +$var wire 1 ] cout2 $end +$var wire 1 . subtract $end +$var wire 1 ^ sum $end +$var wire 1 _ sumAB $end +$upscope $end +$upscope $end +$scope begin ripple[3] $end +$scope module addermid $end +$var wire 1 ` a $end +$var wire 1 a b $end +$var wire 1 b b0 $end +$var wire 1 c carryin $end +$var wire 1 d carryout $end +$var wire 1 e cout1 $end +$var wire 1 f cout2 $end +$var wire 1 . subtract $end +$var wire 1 g sum $end +$var wire 1 h sumAB $end +$upscope $end +$upscope $end +$scope begin ripple[4] $end +$scope module addermid $end +$var wire 1 i a $end +$var wire 1 j b $end +$var wire 1 k b0 $end +$var wire 1 l carryin $end +$var wire 1 m carryout $end +$var wire 1 n cout1 $end +$var wire 1 o cout2 $end +$var wire 1 . subtract $end +$var wire 1 p sum $end +$var wire 1 q sumAB $end +$upscope $end +$upscope $end +$scope begin ripple[5] $end +$scope module addermid $end +$var wire 1 r a $end +$var wire 1 s b $end +$var wire 1 t b0 $end +$var wire 1 u carryin $end +$var wire 1 v carryout $end +$var wire 1 w cout1 $end +$var wire 1 x cout2 $end +$var wire 1 . subtract $end +$var wire 1 y sum $end +$var wire 1 z sumAB $end +$upscope $end +$upscope $end +$scope begin ripple[6] $end +$scope module addermid $end +$var wire 1 { a $end +$var wire 1 | b $end +$var wire 1 } b0 $end +$var wire 1 ~ carryin $end +$var wire 1 !" carryout $end +$var wire 1 "" cout1 $end +$var wire 1 #" cout2 $end +$var wire 1 . subtract $end +$var wire 1 $" sum $end +$var wire 1 %" sumAB $end +$upscope $end +$upscope $end +$scope begin ripple[7] $end +$scope module addermid $end +$var wire 1 &" a $end +$var wire 1 '" b $end +$var wire 1 (" b0 $end +$var wire 1 )" carryin $end +$var wire 1 *" carryout $end +$var wire 1 +" cout1 $end +$var wire 1 ," cout2 $end +$var wire 1 . subtract $end +$var wire 1 -" sum $end +$var wire 1 ." sumAB $end +$upscope $end +$upscope $end +$scope begin ripple[8] $end +$scope module addermid $end +$var wire 1 /" a $end +$var wire 1 0" b $end +$var wire 1 1" b0 $end +$var wire 1 2" carryin $end +$var wire 1 3" carryout $end +$var wire 1 4" cout1 $end +$var wire 1 5" cout2 $end +$var wire 1 . subtract $end +$var wire 1 6" sum $end +$var wire 1 7" sumAB $end +$upscope $end +$upscope $end +$scope begin ripple[9] $end +$scope module addermid $end +$var wire 1 8" a $end +$var wire 1 9" b $end +$var wire 1 :" b0 $end +$var wire 1 ;" carryin $end +$var wire 1 <" carryout $end +$var wire 1 =" cout1 $end +$var wire 1 >" cout2 $end +$var wire 1 . subtract $end +$var wire 1 ?" sum $end +$var wire 1 @" sumAB $end +$upscope $end +$upscope $end +$scope begin ripple[10] $end +$scope module addermid $end +$var wire 1 A" a $end +$var wire 1 B" b $end +$var wire 1 C" b0 $end +$var wire 1 D" carryin $end +$var wire 1 E" carryout $end +$var wire 1 F" cout1 $end +$var wire 1 G" cout2 $end +$var wire 1 . subtract $end +$var wire 1 H" sum $end +$var wire 1 I" sumAB $end +$upscope $end +$upscope $end +$scope begin ripple[11] $end +$scope module addermid $end +$var wire 1 J" a $end +$var wire 1 K" b $end +$var wire 1 L" b0 $end +$var wire 1 M" carryin $end +$var wire 1 N" carryout $end +$var wire 1 O" cout1 $end +$var wire 1 P" cout2 $end +$var wire 1 . subtract $end +$var wire 1 Q" sum $end +$var wire 1 R" sumAB $end +$upscope $end +$upscope $end +$scope begin ripple[12] $end +$scope module addermid $end +$var wire 1 S" a $end +$var wire 1 T" b $end +$var wire 1 U" b0 $end +$var wire 1 V" carryin $end +$var wire 1 W" carryout $end +$var wire 1 X" cout1 $end +$var wire 1 Y" cout2 $end +$var wire 1 . subtract $end +$var wire 1 Z" sum $end +$var wire 1 [" sumAB $end +$upscope $end +$upscope $end +$scope begin ripple[13] $end +$scope module addermid $end +$var wire 1 \" a $end +$var wire 1 ]" b $end +$var wire 1 ^" b0 $end +$var wire 1 _" carryin $end +$var wire 1 `" carryout $end +$var wire 1 a" cout1 $end +$var wire 1 b" cout2 $end +$var wire 1 . subtract $end +$var wire 1 c" sum $end +$var wire 1 d" sumAB $end +$upscope $end +$upscope $end +$scope begin ripple[14] $end +$scope module addermid $end +$var wire 1 e" a $end +$var wire 1 f" b $end +$var wire 1 g" b0 $end +$var wire 1 h" carryin $end +$var wire 1 i" carryout $end +$var wire 1 j" cout1 $end +$var wire 1 k" cout2 $end +$var wire 1 . subtract $end +$var wire 1 l" sum $end +$var wire 1 m" sumAB $end +$upscope $end +$upscope $end +$scope begin ripple[15] $end +$scope module addermid $end +$var wire 1 n" a $end +$var wire 1 o" b $end +$var wire 1 p" b0 $end +$var wire 1 q" carryin $end +$var wire 1 r" carryout $end +$var wire 1 s" cout1 $end +$var wire 1 t" cout2 $end +$var wire 1 . subtract $end +$var wire 1 u" sum $end +$var wire 1 v" sumAB $end +$upscope $end +$upscope $end +$scope begin ripple[16] $end +$scope module addermid $end +$var wire 1 w" a $end +$var wire 1 x" b $end +$var wire 1 y" b0 $end +$var wire 1 z" carryin $end +$var wire 1 {" carryout $end +$var wire 1 |" cout1 $end +$var wire 1 }" cout2 $end +$var wire 1 . subtract $end +$var wire 1 ~" sum $end +$var wire 1 !# sumAB $end +$upscope $end +$upscope $end +$scope begin ripple[17] $end +$scope module addermid $end +$var wire 1 "# a $end +$var wire 1 ## b $end +$var wire 1 $# b0 $end +$var wire 1 %# carryin $end +$var wire 1 &# carryout $end +$var wire 1 '# cout1 $end +$var wire 1 (# cout2 $end +$var wire 1 . subtract $end +$var wire 1 )# sum $end +$var wire 1 *# sumAB $end +$upscope $end +$upscope $end +$scope begin ripple[18] $end +$scope module addermid $end +$var wire 1 +# a $end +$var wire 1 ,# b $end +$var wire 1 -# b0 $end +$var wire 1 .# carryin $end +$var wire 1 /# carryout $end +$var wire 1 0# cout1 $end +$var wire 1 1# cout2 $end +$var wire 1 . subtract $end +$var wire 1 2# sum $end +$var wire 1 3# sumAB $end +$upscope $end +$upscope $end +$scope begin ripple[19] $end +$scope module addermid $end +$var wire 1 4# a $end +$var wire 1 5# b $end +$var wire 1 6# b0 $end +$var wire 1 7# carryin $end +$var wire 1 8# carryout $end +$var wire 1 9# cout1 $end +$var wire 1 :# cout2 $end +$var wire 1 . subtract $end +$var wire 1 ;# sum $end +$var wire 1 <# sumAB $end +$upscope $end +$upscope $end +$scope begin ripple[20] $end +$scope module addermid $end +$var wire 1 =# a $end +$var wire 1 ># b $end +$var wire 1 ?# b0 $end +$var wire 1 @# carryin $end +$var wire 1 A# carryout $end +$var wire 1 B# cout1 $end +$var wire 1 C# cout2 $end +$var wire 1 . subtract $end +$var wire 1 D# sum $end +$var wire 1 E# sumAB $end +$upscope $end +$upscope $end +$scope begin ripple[21] $end +$scope module addermid $end +$var wire 1 F# a $end +$var wire 1 G# b $end +$var wire 1 H# b0 $end +$var wire 1 I# carryin $end +$var wire 1 J# carryout $end +$var wire 1 K# cout1 $end +$var wire 1 L# cout2 $end +$var wire 1 . subtract $end +$var wire 1 M# sum $end +$var wire 1 N# sumAB $end +$upscope $end +$upscope $end +$scope begin ripple[22] $end +$scope module addermid $end +$var wire 1 O# a $end +$var wire 1 P# b $end +$var wire 1 Q# b0 $end +$var wire 1 R# carryin $end +$var wire 1 S# carryout $end +$var wire 1 T# cout1 $end +$var wire 1 U# cout2 $end +$var wire 1 . subtract $end +$var wire 1 V# sum $end +$var wire 1 W# sumAB $end +$upscope $end +$upscope $end +$scope begin ripple[23] $end +$scope module addermid $end +$var wire 1 X# a $end +$var wire 1 Y# b $end +$var wire 1 Z# b0 $end +$var wire 1 [# carryin $end +$var wire 1 \# carryout $end +$var wire 1 ]# cout1 $end +$var wire 1 ^# cout2 $end +$var wire 1 . subtract $end +$var wire 1 _# sum $end +$var wire 1 `# sumAB $end +$upscope $end +$upscope $end +$scope begin ripple[24] $end +$scope module addermid $end +$var wire 1 a# a $end +$var wire 1 b# b $end +$var wire 1 c# b0 $end +$var wire 1 d# carryin $end +$var wire 1 e# carryout $end +$var wire 1 f# cout1 $end +$var wire 1 g# cout2 $end +$var wire 1 . subtract $end +$var wire 1 h# sum $end +$var wire 1 i# sumAB $end +$upscope $end +$upscope $end +$scope begin ripple[25] $end +$scope module addermid $end +$var wire 1 j# a $end +$var wire 1 k# b $end +$var wire 1 l# b0 $end +$var wire 1 m# carryin $end +$var wire 1 n# carryout $end +$var wire 1 o# cout1 $end +$var wire 1 p# cout2 $end +$var wire 1 . subtract $end +$var wire 1 q# sum $end +$var wire 1 r# sumAB $end +$upscope $end +$upscope $end +$scope begin ripple[26] $end +$scope module addermid $end +$var wire 1 s# a $end +$var wire 1 t# b $end +$var wire 1 u# b0 $end +$var wire 1 v# carryin $end +$var wire 1 w# carryout $end +$var wire 1 x# cout1 $end +$var wire 1 y# cout2 $end +$var wire 1 . subtract $end +$var wire 1 z# sum $end +$var wire 1 {# sumAB $end +$upscope $end +$upscope $end +$scope begin ripple[27] $end +$scope module addermid $end +$var wire 1 |# a $end +$var wire 1 }# b $end +$var wire 1 ~# b0 $end +$var wire 1 !$ carryin $end +$var wire 1 "$ carryout $end +$var wire 1 #$ cout1 $end +$var wire 1 $$ cout2 $end +$var wire 1 . subtract $end +$var wire 1 %$ sum $end +$var wire 1 &$ sumAB $end +$upscope $end +$upscope $end +$scope begin ripple[28] $end +$scope module addermid $end +$var wire 1 '$ a $end +$var wire 1 ($ b $end +$var wire 1 )$ b0 $end +$var wire 1 *$ carryin $end +$var wire 1 +$ carryout $end +$var wire 1 ,$ cout1 $end +$var wire 1 -$ cout2 $end +$var wire 1 . subtract $end +$var wire 1 .$ sum $end +$var wire 1 /$ sumAB $end +$upscope $end +$upscope $end +$scope begin ripple[29] $end +$scope module addermid $end +$var wire 1 0$ a $end +$var wire 1 1$ b $end +$var wire 1 2$ b0 $end +$var wire 1 3$ carryin $end +$var wire 1 4$ carryout $end +$var wire 1 5$ cout1 $end +$var wire 1 6$ cout2 $end +$var wire 1 . subtract $end +$var wire 1 7$ sum $end +$var wire 1 8$ sumAB $end +$upscope $end +$upscope $end +$scope begin ripple[30] $end +$scope module addermid $end +$var wire 1 9$ a $end +$var wire 1 :$ b $end +$var wire 1 ;$ b0 $end +$var wire 1 <$ carryin $end +$var wire 1 =$ carryout $end +$var wire 1 >$ cout1 $end +$var wire 1 ?$ cout2 $end +$var wire 1 . subtract $end +$var wire 1 @$ sum $end +$var wire 1 A$ sumAB $end +$upscope $end +$upscope $end +$scope module adderfinal $end +$var wire 1 B$ a $end +$var wire 1 C$ b $end +$var wire 1 D$ b0 $end +$var wire 1 E$ carryin $end +$var wire 1 G carryout $end +$var wire 1 F$ cout1 $end +$var wire 1 G$ cout2 $end +$var wire 1 . subtract $end +$var wire 1 H$ sum $end +$var wire 1 I$ sumAB $end +$upscope $end +$scope module adderinit $end +$var wire 1 J$ a $end +$var wire 1 K$ b $end +$var wire 1 L$ b0 $end +$var wire 1 . carryin $end +$var wire 1 M$ carryout $end +$var wire 1 N$ cout1 $end +$var wire 1 O$ cout2 $end +$var wire 1 . subtract $end +$var wire 1 P$ sum $end +$var wire 1 Q$ sumAB $end +$upscope $end +$upscope $end +$scope module dut1 $end +$var wire 1 3 carryout $end +$var wire 32 R$ operandA [31:0] $end +$var wire 32 S$ operandB [31:0] $end +$var wire 1 9 overflow $end +$var wire 1 < zero $end +$var wire 32 T$ result [31:0] $end +$scope begin ripple[0] $end +$upscope $end +$scope begin ripple[1] $end +$upscope $end +$scope begin ripple[2] $end +$upscope $end +$scope begin ripple[3] $end +$upscope $end +$scope begin ripple[4] $end +$upscope $end +$scope begin ripple[5] $end +$upscope $end +$scope begin ripple[6] $end +$upscope $end +$scope begin ripple[7] $end +$upscope $end +$scope begin ripple[8] $end +$upscope $end +$scope begin ripple[9] $end +$upscope $end +$scope begin ripple[10] $end +$upscope $end +$scope begin ripple[11] $end +$upscope $end +$scope begin ripple[12] $end +$upscope $end +$scope begin ripple[13] $end +$upscope $end +$scope begin ripple[14] $end +$upscope $end +$scope begin ripple[15] $end +$upscope $end +$scope begin ripple[16] $end +$upscope $end +$scope begin ripple[17] $end +$upscope $end +$scope begin ripple[18] $end +$upscope $end +$scope begin ripple[19] $end +$upscope $end +$scope begin ripple[20] $end +$upscope $end +$scope begin ripple[21] $end +$upscope $end +$scope begin ripple[22] $end +$upscope $end +$scope begin ripple[23] $end +$upscope $end +$scope begin ripple[24] $end +$upscope $end +$scope begin ripple[25] $end +$upscope $end +$scope begin ripple[26] $end +$upscope $end +$scope begin ripple[27] $end +$upscope $end +$scope begin ripple[28] $end +$upscope $end +$scope begin ripple[29] $end +$upscope $end +$scope begin ripple[30] $end +$upscope $end +$scope begin ripple[31] $end +$upscope $end +$upscope $end +$scope module dut2 $end +$var wire 1 2 carryout $end +$var wire 32 U$ operandA [31:0] $end +$var wire 32 V$ operandB [31:0] $end +$var wire 1 8 overflow $end +$var wire 1 ; zero $end +$var wire 1 W$ subzero $end +$var wire 32 X$ subresult [31:0] $end +$var wire 1 Y$ suboverflow $end +$var wire 1 Z$ subcarryout $end +$var wire 32 [$ result [31:0] $end +$scope module subtractor $end +$var wire 1 \$ nzero $end +$var wire 32 ]$ operandA [31:0] $end +$var wire 32 ^$ operandB [31:0] $end +$var wire 1 Y$ overflow $end +$var wire 1 _$ subtract $end +$var wire 1 W$ zero $end +$var wire 32 `$ result [31:0] $end +$var wire 31 a$ carryoutmid [30:0] $end +$var wire 1 Z$ carryout $end +$scope begin ripple[1] $end +$scope module addermid $end +$var wire 1 b$ a $end +$var wire 1 c$ b $end +$var wire 1 d$ b0 $end +$var wire 1 e$ carryin $end +$var wire 1 f$ carryout $end +$var wire 1 g$ cout1 $end +$var wire 1 h$ cout2 $end +$var wire 1 _$ subtract $end +$var wire 1 i$ sum $end +$var wire 1 j$ sumAB $end +$upscope $end +$upscope $end +$scope begin ripple[2] $end +$scope module addermid $end +$var wire 1 k$ a $end +$var wire 1 l$ b $end +$var wire 1 m$ b0 $end +$var wire 1 n$ carryin $end +$var wire 1 o$ carryout $end +$var wire 1 p$ cout1 $end +$var wire 1 q$ cout2 $end +$var wire 1 _$ subtract $end +$var wire 1 r$ sum $end +$var wire 1 s$ sumAB $end +$upscope $end +$upscope $end +$scope begin ripple[3] $end +$scope module addermid $end +$var wire 1 t$ a $end +$var wire 1 u$ b $end +$var wire 1 v$ b0 $end +$var wire 1 w$ carryin $end +$var wire 1 x$ carryout $end +$var wire 1 y$ cout1 $end +$var wire 1 z$ cout2 $end +$var wire 1 _$ subtract $end +$var wire 1 {$ sum $end +$var wire 1 |$ sumAB $end +$upscope $end +$upscope $end +$scope begin ripple[4] $end +$scope module addermid $end +$var wire 1 }$ a $end +$var wire 1 ~$ b $end +$var wire 1 !% b0 $end +$var wire 1 "% carryin $end +$var wire 1 #% carryout $end +$var wire 1 $% cout1 $end +$var wire 1 %% cout2 $end +$var wire 1 _$ subtract $end +$var wire 1 &% sum $end +$var wire 1 '% sumAB $end +$upscope $end +$upscope $end +$scope begin ripple[5] $end +$scope module addermid $end +$var wire 1 (% a $end +$var wire 1 )% b $end +$var wire 1 *% b0 $end +$var wire 1 +% carryin $end +$var wire 1 ,% carryout $end +$var wire 1 -% cout1 $end +$var wire 1 .% cout2 $end +$var wire 1 _$ subtract $end +$var wire 1 /% sum $end +$var wire 1 0% sumAB $end +$upscope $end +$upscope $end +$scope begin ripple[6] $end +$scope module addermid $end +$var wire 1 1% a $end +$var wire 1 2% b $end +$var wire 1 3% b0 $end +$var wire 1 4% carryin $end +$var wire 1 5% carryout $end +$var wire 1 6% cout1 $end +$var wire 1 7% cout2 $end +$var wire 1 _$ subtract $end +$var wire 1 8% sum $end +$var wire 1 9% sumAB $end +$upscope $end +$upscope $end +$scope begin ripple[7] $end +$scope module addermid $end +$var wire 1 :% a $end +$var wire 1 ;% b $end +$var wire 1 <% b0 $end +$var wire 1 =% carryin $end +$var wire 1 >% carryout $end +$var wire 1 ?% cout1 $end +$var wire 1 @% cout2 $end +$var wire 1 _$ subtract $end +$var wire 1 A% sum $end +$var wire 1 B% sumAB $end +$upscope $end +$upscope $end +$scope begin ripple[8] $end +$scope module addermid $end +$var wire 1 C% a $end +$var wire 1 D% b $end +$var wire 1 E% b0 $end +$var wire 1 F% carryin $end +$var wire 1 G% carryout $end +$var wire 1 H% cout1 $end +$var wire 1 I% cout2 $end +$var wire 1 _$ subtract $end +$var wire 1 J% sum $end +$var wire 1 K% sumAB $end +$upscope $end +$upscope $end +$scope begin ripple[9] $end +$scope module addermid $end +$var wire 1 L% a $end +$var wire 1 M% b $end +$var wire 1 N% b0 $end +$var wire 1 O% carryin $end +$var wire 1 P% carryout $end +$var wire 1 Q% cout1 $end +$var wire 1 R% cout2 $end +$var wire 1 _$ subtract $end +$var wire 1 S% sum $end +$var wire 1 T% sumAB $end +$upscope $end +$upscope $end +$scope begin ripple[10] $end +$scope module addermid $end +$var wire 1 U% a $end +$var wire 1 V% b $end +$var wire 1 W% b0 $end +$var wire 1 X% carryin $end +$var wire 1 Y% carryout $end +$var wire 1 Z% cout1 $end +$var wire 1 [% cout2 $end +$var wire 1 _$ subtract $end +$var wire 1 \% sum $end +$var wire 1 ]% sumAB $end +$upscope $end +$upscope $end +$scope begin ripple[11] $end +$scope module addermid $end +$var wire 1 ^% a $end +$var wire 1 _% b $end +$var wire 1 `% b0 $end +$var wire 1 a% carryin $end +$var wire 1 b% carryout $end +$var wire 1 c% cout1 $end +$var wire 1 d% cout2 $end +$var wire 1 _$ subtract $end +$var wire 1 e% sum $end +$var wire 1 f% sumAB $end +$upscope $end +$upscope $end +$scope begin ripple[12] $end +$scope module addermid $end +$var wire 1 g% a $end +$var wire 1 h% b $end +$var wire 1 i% b0 $end +$var wire 1 j% carryin $end +$var wire 1 k% carryout $end +$var wire 1 l% cout1 $end +$var wire 1 m% cout2 $end +$var wire 1 _$ subtract $end +$var wire 1 n% sum $end +$var wire 1 o% sumAB $end +$upscope $end +$upscope $end +$scope begin ripple[13] $end +$scope module addermid $end +$var wire 1 p% a $end +$var wire 1 q% b $end +$var wire 1 r% b0 $end +$var wire 1 s% carryin $end +$var wire 1 t% carryout $end +$var wire 1 u% cout1 $end +$var wire 1 v% cout2 $end +$var wire 1 _$ subtract $end +$var wire 1 w% sum $end +$var wire 1 x% sumAB $end +$upscope $end +$upscope $end +$scope begin ripple[14] $end +$scope module addermid $end +$var wire 1 y% a $end +$var wire 1 z% b $end +$var wire 1 {% b0 $end +$var wire 1 |% carryin $end +$var wire 1 }% carryout $end +$var wire 1 ~% cout1 $end +$var wire 1 !& cout2 $end +$var wire 1 _$ subtract $end +$var wire 1 "& sum $end +$var wire 1 #& sumAB $end +$upscope $end +$upscope $end +$scope begin ripple[15] $end +$scope module addermid $end +$var wire 1 $& a $end +$var wire 1 %& b $end +$var wire 1 && b0 $end +$var wire 1 '& carryin $end +$var wire 1 (& carryout $end +$var wire 1 )& cout1 $end +$var wire 1 *& cout2 $end +$var wire 1 _$ subtract $end +$var wire 1 +& sum $end +$var wire 1 ,& sumAB $end +$upscope $end +$upscope $end +$scope begin ripple[16] $end +$scope module addermid $end +$var wire 1 -& a $end +$var wire 1 .& b $end +$var wire 1 /& b0 $end +$var wire 1 0& carryin $end +$var wire 1 1& carryout $end +$var wire 1 2& cout1 $end +$var wire 1 3& cout2 $end +$var wire 1 _$ subtract $end +$var wire 1 4& sum $end +$var wire 1 5& sumAB $end +$upscope $end +$upscope $end +$scope begin ripple[17] $end +$scope module addermid $end +$var wire 1 6& a $end +$var wire 1 7& b $end +$var wire 1 8& b0 $end +$var wire 1 9& carryin $end +$var wire 1 :& carryout $end +$var wire 1 ;& cout1 $end +$var wire 1 <& cout2 $end +$var wire 1 _$ subtract $end +$var wire 1 =& sum $end +$var wire 1 >& sumAB $end +$upscope $end +$upscope $end +$scope begin ripple[18] $end +$scope module addermid $end +$var wire 1 ?& a $end +$var wire 1 @& b $end +$var wire 1 A& b0 $end +$var wire 1 B& carryin $end +$var wire 1 C& carryout $end +$var wire 1 D& cout1 $end +$var wire 1 E& cout2 $end +$var wire 1 _$ subtract $end +$var wire 1 F& sum $end +$var wire 1 G& sumAB $end +$upscope $end +$upscope $end +$scope begin ripple[19] $end +$scope module addermid $end +$var wire 1 H& a $end +$var wire 1 I& b $end +$var wire 1 J& b0 $end +$var wire 1 K& carryin $end +$var wire 1 L& carryout $end +$var wire 1 M& cout1 $end +$var wire 1 N& cout2 $end +$var wire 1 _$ subtract $end +$var wire 1 O& sum $end +$var wire 1 P& sumAB $end +$upscope $end +$upscope $end +$scope begin ripple[20] $end +$scope module addermid $end +$var wire 1 Q& a $end +$var wire 1 R& b $end +$var wire 1 S& b0 $end +$var wire 1 T& carryin $end +$var wire 1 U& carryout $end +$var wire 1 V& cout1 $end +$var wire 1 W& cout2 $end +$var wire 1 _$ subtract $end +$var wire 1 X& sum $end +$var wire 1 Y& sumAB $end +$upscope $end +$upscope $end +$scope begin ripple[21] $end +$scope module addermid $end +$var wire 1 Z& a $end +$var wire 1 [& b $end +$var wire 1 \& b0 $end +$var wire 1 ]& carryin $end +$var wire 1 ^& carryout $end +$var wire 1 _& cout1 $end +$var wire 1 `& cout2 $end +$var wire 1 _$ subtract $end +$var wire 1 a& sum $end +$var wire 1 b& sumAB $end +$upscope $end +$upscope $end +$scope begin ripple[22] $end +$scope module addermid $end +$var wire 1 c& a $end +$var wire 1 d& b $end +$var wire 1 e& b0 $end +$var wire 1 f& carryin $end +$var wire 1 g& carryout $end +$var wire 1 h& cout1 $end +$var wire 1 i& cout2 $end +$var wire 1 _$ subtract $end +$var wire 1 j& sum $end +$var wire 1 k& sumAB $end +$upscope $end +$upscope $end +$scope begin ripple[23] $end +$scope module addermid $end +$var wire 1 l& a $end +$var wire 1 m& b $end +$var wire 1 n& b0 $end +$var wire 1 o& carryin $end +$var wire 1 p& carryout $end +$var wire 1 q& cout1 $end +$var wire 1 r& cout2 $end +$var wire 1 _$ subtract $end +$var wire 1 s& sum $end +$var wire 1 t& sumAB $end +$upscope $end +$upscope $end +$scope begin ripple[24] $end +$scope module addermid $end +$var wire 1 u& a $end +$var wire 1 v& b $end +$var wire 1 w& b0 $end +$var wire 1 x& carryin $end +$var wire 1 y& carryout $end +$var wire 1 z& cout1 $end +$var wire 1 {& cout2 $end +$var wire 1 _$ subtract $end +$var wire 1 |& sum $end +$var wire 1 }& sumAB $end +$upscope $end +$upscope $end +$scope begin ripple[25] $end +$scope module addermid $end +$var wire 1 ~& a $end +$var wire 1 !' b $end +$var wire 1 "' b0 $end +$var wire 1 #' carryin $end +$var wire 1 $' carryout $end +$var wire 1 %' cout1 $end +$var wire 1 &' cout2 $end +$var wire 1 _$ subtract $end +$var wire 1 '' sum $end +$var wire 1 (' sumAB $end +$upscope $end +$upscope $end +$scope begin ripple[26] $end +$scope module addermid $end +$var wire 1 )' a $end +$var wire 1 *' b $end +$var wire 1 +' b0 $end +$var wire 1 ,' carryin $end +$var wire 1 -' carryout $end +$var wire 1 .' cout1 $end +$var wire 1 /' cout2 $end +$var wire 1 _$ subtract $end +$var wire 1 0' sum $end +$var wire 1 1' sumAB $end +$upscope $end +$upscope $end +$scope begin ripple[27] $end +$scope module addermid $end +$var wire 1 2' a $end +$var wire 1 3' b $end +$var wire 1 4' b0 $end +$var wire 1 5' carryin $end +$var wire 1 6' carryout $end +$var wire 1 7' cout1 $end +$var wire 1 8' cout2 $end +$var wire 1 _$ subtract $end +$var wire 1 9' sum $end +$var wire 1 :' sumAB $end +$upscope $end +$upscope $end +$scope begin ripple[28] $end +$scope module addermid $end +$var wire 1 ;' a $end +$var wire 1 <' b $end +$var wire 1 =' b0 $end +$var wire 1 >' carryin $end +$var wire 1 ?' carryout $end +$var wire 1 @' cout1 $end +$var wire 1 A' cout2 $end +$var wire 1 _$ subtract $end +$var wire 1 B' sum $end +$var wire 1 C' sumAB $end +$upscope $end +$upscope $end +$scope begin ripple[29] $end +$scope module addermid $end +$var wire 1 D' a $end +$var wire 1 E' b $end +$var wire 1 F' b0 $end +$var wire 1 G' carryin $end +$var wire 1 H' carryout $end +$var wire 1 I' cout1 $end +$var wire 1 J' cout2 $end +$var wire 1 _$ subtract $end +$var wire 1 K' sum $end +$var wire 1 L' sumAB $end +$upscope $end +$upscope $end +$scope begin ripple[30] $end +$scope module addermid $end +$var wire 1 M' a $end +$var wire 1 N' b $end +$var wire 1 O' b0 $end +$var wire 1 P' carryin $end +$var wire 1 Q' carryout $end +$var wire 1 R' cout1 $end +$var wire 1 S' cout2 $end +$var wire 1 _$ subtract $end +$var wire 1 T' sum $end +$var wire 1 U' sumAB $end +$upscope $end +$upscope $end +$scope module adderfinal $end +$var wire 1 V' a $end +$var wire 1 W' b $end +$var wire 1 X' b0 $end +$var wire 1 Y' carryin $end +$var wire 1 Z$ carryout $end +$var wire 1 Z' cout1 $end +$var wire 1 [' cout2 $end +$var wire 1 _$ subtract $end +$var wire 1 \' sum $end +$var wire 1 ]' sumAB $end +$upscope $end +$scope module adderinit $end +$var wire 1 ^' a $end +$var wire 1 _' b $end +$var wire 1 `' b0 $end +$var wire 1 _$ carryin $end +$var wire 1 a' carryout $end +$var wire 1 b' cout1 $end +$var wire 1 c' cout2 $end +$var wire 1 _$ subtract $end +$var wire 1 d' sum $end +$var wire 1 e' sumAB $end +$upscope $end +$upscope $end +$upscope $end +$scope module dut3 $end +$var wire 1 1 carryout $end +$var wire 1 , invertand $end +$var wire 32 f' operandA [31:0] $end +$var wire 32 g' operandB [31:0] $end +$var wire 1 7 overflow $end +$var wire 1 : zero $end +$var wire 32 h' result [31:0] $end +$scope begin ripple0[0] $end +$upscope $end +$scope begin ripple0[1] $end +$upscope $end +$scope begin ripple0[2] $end +$upscope $end +$scope begin ripple0[3] $end +$upscope $end +$scope begin ripple0[4] $end +$upscope $end +$scope begin ripple0[5] $end +$upscope $end +$scope begin ripple0[6] $end +$upscope $end +$scope begin ripple0[7] $end +$upscope $end +$scope begin ripple0[8] $end +$upscope $end +$scope begin ripple0[9] $end +$upscope $end +$scope begin ripple0[10] $end +$upscope $end +$scope begin ripple0[11] $end +$upscope $end +$scope begin ripple0[12] $end +$upscope $end +$scope begin ripple0[13] $end +$upscope $end +$scope begin ripple0[14] $end +$upscope $end +$scope begin ripple0[15] $end +$upscope $end +$scope begin ripple0[16] $end +$upscope $end +$scope begin ripple0[17] $end +$upscope $end +$scope begin ripple0[18] $end +$upscope $end +$scope begin ripple0[19] $end +$upscope $end +$scope begin ripple0[20] $end +$upscope $end +$scope begin ripple0[21] $end +$upscope $end +$scope begin ripple0[22] $end +$upscope $end +$scope begin ripple0[23] $end +$upscope $end +$scope begin ripple0[24] $end +$upscope $end +$scope begin ripple0[25] $end +$upscope $end +$scope begin ripple0[26] $end +$upscope $end +$scope begin ripple0[27] $end +$upscope $end +$scope begin ripple0[28] $end +$upscope $end +$scope begin ripple0[29] $end +$upscope $end +$scope begin ripple0[30] $end +$upscope $end +$scope begin ripple0[31] $end +$upscope $end +$scope begin ripple1[0] $end +$upscope $end +$scope begin ripple1[1] $end +$upscope $end +$scope begin ripple1[2] $end +$upscope $end +$scope begin ripple1[3] $end +$upscope $end +$scope begin ripple1[4] $end +$upscope $end +$scope begin ripple1[5] $end +$upscope $end +$scope begin ripple1[6] $end +$upscope $end +$scope begin ripple1[7] $end +$upscope $end +$scope begin ripple1[8] $end +$upscope $end +$scope begin ripple1[9] $end +$upscope $end +$scope begin ripple1[10] $end +$upscope $end +$scope begin ripple1[11] $end +$upscope $end +$scope begin ripple1[12] $end +$upscope $end +$scope begin ripple1[13] $end +$upscope $end +$scope begin ripple1[14] $end +$upscope $end +$scope begin ripple1[15] $end +$upscope $end +$scope begin ripple1[16] $end +$upscope $end +$scope begin ripple1[17] $end +$upscope $end +$scope begin ripple1[18] $end +$upscope $end +$scope begin ripple1[19] $end +$upscope $end +$scope begin ripple1[20] $end +$upscope $end +$scope begin ripple1[21] $end +$upscope $end +$scope begin ripple1[22] $end +$upscope $end +$scope begin ripple1[23] $end +$upscope $end +$scope begin ripple1[24] $end +$upscope $end +$scope begin ripple1[25] $end +$upscope $end +$scope begin ripple1[26] $end +$upscope $end +$scope begin ripple1[27] $end +$upscope $end +$scope begin ripple1[28] $end +$upscope $end +$scope begin ripple1[29] $end +$upscope $end +$scope begin ripple1[30] $end +$upscope $end +$scope begin ripple1[31] $end +$upscope $end +$upscope $end +$scope module dut4 $end +$var wire 1 F carryout $end +$var wire 1 , invertor $end +$var wire 32 i' operandA [31:0] $end +$var wire 32 j' operandB [31:0] $end +$var wire 1 D overflow $end +$var wire 1 = zero $end +$var wire 32 k' result [31:0] $end +$scope begin ripple0[0] $end +$upscope $end +$scope begin ripple0[1] $end +$upscope $end +$scope begin ripple0[2] $end +$upscope $end +$scope begin ripple0[3] $end +$upscope $end +$scope begin ripple0[4] $end +$upscope $end +$scope begin ripple0[5] $end +$upscope $end +$scope begin ripple0[6] $end +$upscope $end +$scope begin ripple0[7] $end +$upscope $end +$scope begin ripple0[8] $end +$upscope $end +$scope begin ripple0[9] $end +$upscope $end +$scope begin ripple0[10] $end +$upscope $end +$scope begin ripple0[11] $end +$upscope $end +$scope begin ripple0[12] $end +$upscope $end +$scope begin ripple0[13] $end +$upscope $end +$scope begin ripple0[14] $end +$upscope $end +$scope begin ripple0[15] $end +$upscope $end +$scope begin ripple0[16] $end +$upscope $end +$scope begin ripple0[17] $end +$upscope $end +$scope begin ripple0[18] $end +$upscope $end +$scope begin ripple0[19] $end +$upscope $end +$scope begin ripple0[20] $end +$upscope $end +$scope begin ripple0[21] $end +$upscope $end +$scope begin ripple0[22] $end +$upscope $end +$scope begin ripple0[23] $end +$upscope $end +$scope begin ripple0[24] $end +$upscope $end +$scope begin ripple0[25] $end +$upscope $end +$scope begin ripple0[26] $end +$upscope $end +$scope begin ripple0[27] $end +$upscope $end +$scope begin ripple0[28] $end +$upscope $end +$scope begin ripple0[29] $end +$upscope $end +$scope begin ripple0[30] $end +$upscope $end +$scope begin ripple0[31] $end +$upscope $end +$scope begin ripple1[0] $end +$upscope $end +$scope begin ripple1[1] $end +$upscope $end +$scope begin ripple1[2] $end +$upscope $end +$scope begin ripple1[3] $end +$upscope $end +$scope begin ripple1[4] $end +$upscope $end +$scope begin ripple1[5] $end +$upscope $end +$scope begin ripple1[6] $end +$upscope $end +$scope begin ripple1[7] $end +$upscope $end +$scope begin ripple1[8] $end +$upscope $end +$scope begin ripple1[9] $end +$upscope $end +$scope begin ripple1[10] $end +$upscope $end +$scope begin ripple1[11] $end +$upscope $end +$scope begin ripple1[12] $end +$upscope $end +$scope begin ripple1[13] $end +$upscope $end +$scope begin ripple1[14] $end +$upscope $end +$scope begin ripple1[15] $end +$upscope $end +$scope begin ripple1[16] $end +$upscope $end +$scope begin ripple1[17] $end +$upscope $end +$scope begin ripple1[18] $end +$upscope $end +$scope begin ripple1[19] $end +$upscope $end +$scope begin ripple1[20] $end +$upscope $end +$scope begin ripple1[21] $end +$upscope $end +$scope begin ripple1[22] $end +$upscope $end +$scope begin ripple1[23] $end +$upscope $end +$scope begin ripple1[24] $end +$upscope $end +$scope begin ripple1[25] $end +$upscope $end +$scope begin ripple1[26] $end +$upscope $end +$scope begin ripple1[27] $end +$upscope $end +$scope begin ripple1[28] $end +$upscope $end +$scope begin ripple1[29] $end +$upscope $end +$scope begin ripple1[30] $end +$upscope $end +$scope begin ripple1[31] $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$enddefinitions $end +#0 +$dumpvars +bx k' +b0 j' +b0 i' +bx h' +b0 g' +b0 f' +xe' +xd' +xc' +xb' +xa' +0`' +x_' +0^' +x]' +x\' +x[' +xZ' +xY' +0X' +xW' +0V' +xU' +xT' +xS' +xR' +xQ' +xP' +0O' +xN' +0M' +xL' +xK' +xJ' +xI' +xH' +xG' +0F' +xE' +0D' +xC' +xB' +xA' +x@' +x?' +x>' +0=' +x<' +0;' +x:' +x9' +x8' +x7' +x6' +x5' +04' +x3' +02' +x1' +x0' +x/' +x.' +x-' +x,' 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define gates with delays +`define AND and #20 +`define OR or #20 +`define NOT not #10 + +module structuralMultiplexer +( + output out, + input address0, address1, + input in0, in1, in2, in3 +); + wire nadd0, nadd1, en0, en1, en2, en3, selen0, selen1, selen2, selen3, out0, out1; + + `NOT add0inv (nadd0, address0); + `NOT add1inv (nadd1, address1); + + `AND nadd0nadd1 (en0, nadd0, nadd1); + `AND add0nadd1 (en1, address0, nadd1); + `AND nadd0add1 (en2, nadd0, address1); + `AND add0nadd1 (en3, address0, address1); + + `AND selector0 (selen0, en0, in0); + `AND selector1 (selen1, en1, in1); + `AND selector2 (selen2, en2, in2); + `AND selector3 (selen3, en3, in3); + + `OR in0orin1 (out0, selen1, selen2); + `OR in2orin3 (out1, selen0, selen3); + + `OR out (out, out0, out1); +endmodule diff --git a/operations.v b/operations.v new file mode 100644 index 0000000..cdd3b1f --- /dev/null +++ b/operations.v @@ -0,0 +1,197 @@ +// The modules defining each operaton of the ALU. + +`define NOR nor #10 +`define OR or #20 +`define AND and #20 +`define XOR xor #20 +`define NOT not #10 + +// Implementation of a 1-bit full adder. When true, subtract inverts input B. +module FullAdder1bit +( + output sum, + output carryout, + input a, + input b, + input carryin +); + wire cout1; + wire cout2; + wire sumAB; + + // B is inverted for subtraction operations. + `XOR AxorB(sumAB, a, b); + `XOR sumABxorCin(sum, sumAB, carryin); + + `AND AandB(cout1, a, b); + `AND sumABandCin(cout2, sumAB, carryin); + + `OR orcarries(carryout, cout1, cout2); +endmodule + +// Implementation of a 32 bit adder/subtractor. +module AddSub +( +output[31:0] result, +output carryout, +output zero, +output overflow, +input[31:0] operandA, +input[31:0] operandB, +input subtract +); + +wire[31:0] invB; +wire[30:0] carryoutmid; +wire nzero; + +// Pass a 1 as the carryin to the first full adder for subtraction. +`XOR invertB (invB[0], operandB[0], subtract); +FullAdder1bit adderinit (result[0], carryoutmid[0], operandA[0], invB[0], subtract); + +genvar i; +generate + for (i = 1; i < 31; i = i + 1) + begin: ripple + `XOR invertB (invB[i], operandB[i], subtract); + FullAdder1bit addermid (result[i], carryoutmid[i], operandA[i], invB[i], carryoutmid[i- 1]); + end +endgenerate + + +`XOR invertB (invB[31], operandB[31], subtract); +FullAdder1bit adderfinal (result[31], carryout, operandA[31], invB[31], carryoutmid[30]); + +// determine overflows +`XOR overflowdetection(overflow, carryoutmid[30], carryout); + +assign nzero = |result; +`NOT notgate(zero, nzero); + + +endmodule + +// Implementation of a 32 bit XOR operation. +module alu32bitxor +( +output[31:0] result, +output carryout, +output zero, +output overflow, +input[31:0] operandA, +input[31:0] operandB +); + +genvar i; +generate + for (i = 0; i < 32; i = i + 1) + begin: ripple + `XOR xorgate (result[i], operandA[i], operandB[i]); + end +endgenerate + +endmodule + +// Implementation of the set-less-than operation. Uses the 32-bit subtractor. +module alu32bitslt +( +output[31:0] result, +output carryout, +output zero, +output overflow, +input[31:0] operandA, +input[31:0] operandB +); +wire[31:0] subresult; +wire subcarryout; +wire subzero; +wire suboverflow; + +// Set invertB to 1 because subtraction is needed. +AddSub subtractor (subresult, subcarryout, subzero, suboverflow, operandA, operandB, 1'b1); + +assign result[31:1] = 31'b0; + +`XOR final (result[0], subresult[31], suboverflow); + +// Doesn't need to set a flag. +assign carryout = 0; +assign zero = 0; +assign overflow = 0; + +endmodule + + +// Implementation of a 32 bit NAND or AND operation. +// When 1, the invertand input indicates a NAND operation. +// When invertand is 0, this module performs an AND operation. +module alu32bitandn +( +output[31:0] result, +output carryout, +output zero, +output overflow, +input[31:0] operandA, +input[31:0] operandB, +input invertand +); +wire interresult[31:0]; + +genvar i; +generate + for (i = 0; i < 32; i = i + 1) + begin: ripple0 + `AND andgate (interresult[i], operandA[i], operandB[i]); + end +endgenerate + +genvar j; +generate + for (j = 0; j < 32; j = j + 1) + begin: ripple1 + `XOR final (result[j], invertand, interresult[j]); + end +endgenerate + +// Doesn't need to set a flag. +assign carryout = 0; +assign zero = 0; +assign overflow = 0; + +endmodule + +// Implementation of a 32 bit NOR or OR operation. +// When 1, the invertnor input indicates a NOR operation. +// When invertor is 0, this module performs an OR operation. +module NOROR +( +output[31:0] result, +output carryout, +output zero, +output overflow, +input[31:0] operandA, +input[31:0] operandB, +input invertor +); + +wire norres[31:0]; +genvar i; +generate + for (i = 0; i < 32; i = i + 1) + begin: ripple0 + `NOR norgate (norres[i], operandA[i], operandB[i]); + end +endgenerate + +genvar j; +generate + for (j = 0; j < 32; j = j + 1) + begin: ripple1 + `XOR final (result[j], invertor, norres[j]); + end +endgenerate + +buf setcarryout (carryout, 'b0); +buf setzero (zero, 'b0); +buf setoverflow (overflow, 'b0); +endmodule \ No newline at end of file diff --git a/work_plan.txt b/work_plan.txt new file mode 100644 index 0000000..d7f432a --- /dev/null +++ b/work_plan.txt @@ -0,0 +1,23 @@ +Work Plan + +Test cases of ALU and submodules: + 2 hours (including learning how to make code self-check) + Finish 10/6/17 + +Verilog implementation of ALU: + + Simple implementation (non-optimized, seperated operations): + 2.5 hours + Finish 10/8/17 + + Optimized implementation (reducing silicon area/delay): + 2 hours + Finish 10/11/17 (stretch goal) + +Uploading to FPGA (writing wrapper and uploading): + 1 hour + Finish 10/10/17 + +Report: + 2 hours + Finish 10/11/17 \ No newline at end of file