From 595651b83b57a0b178d04c0a8d651530100caf09 Mon Sep 17 00:00:00 2001 From: Bryan Werth Date: Wed, 4 Oct 2017 19:21:37 -0400 Subject: [PATCH 01/28] Finished the work plan --- work_plan.txt | 8 ++++++++ 1 file changed, 8 insertions(+) create mode 100644 work_plan.txt diff --git a/work_plan.txt b/work_plan.txt new file mode 100644 index 0000000..6fa8d8d --- /dev/null +++ b/work_plan.txt @@ -0,0 +1,8 @@ +Work Plan +Single-Bit ALU Implementation - 1-2 hours - done by Saturday 10/7 +Single-Bit ALU Test Bench and Debugging - 1 hour - done by Saturday 10/7 +Full ALU Implementation - 30 minutes - done by Monday 10/9 +Full ALU Test Bench and Debugging - 3-4 hours - done by Tuesday 10/10 +ALU Zynq Interfacing - 1-2 hours - done by Tuesday 10/10 +ALU Zynq - 2 hours - done by Tuesday 10/10 +Polishing and Report - 2-3 hours - done by Wednesday 10/11 From 346a166d25e507b812aa461b76a978bb27278f86 Mon Sep 17 00:00:00 2001 From: Wilson Tang Date: Sat, 7 Oct 2017 12:43:25 -0400 Subject: [PATCH 02/28] single alu test bench --- alusingle.t.v | 98 +++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 98 insertions(+) create mode 100644 alusingle.t.v diff --git a/alusingle.t.v b/alusingle.t.v new file mode 100644 index 0000000..392e589 --- /dev/null +++ b/alusingle.t.v @@ -0,0 +1,98 @@ +// Single Bit ALU testbench +`timescale 1 ns / 1 ps +`include "alusinglebit.v" + +module testSingleBitALU (); + reg operandA, operandB, carryin, command; + wire result, carryout, correct; + + ALUsinglebit alusinglebittest(result,carryout,operandA,operandB,carryin,command); + + initial begin + $display("command | carryin operandA operandB| result carryout | correct"); + + //Add + command = `b000; carryin = 0; operandA=0; operandB=0; correct = result==0 #50 + $display("%b| %b %b %b|%b %b| %b", command, carryin, operandA, operandB, result, carryout, correct); + command = `b000; carryin = 0; operandA=0; operandB=1; correct = result==1 #50 + $display("%b| %b %b %b|%b %b| %b", command, carryin, operandA, operandB, result, carryout, correct); + command = `b000; carryin = 0; operandA=1; operandB=0; correct = result==1 #50 + $display("%b| %b %b %b|%b %b| %b", command, carryin, operandA, operandB, result, carryout, correct); + command = `b000; carryin = 0; operandA=1; operandB=1; correct = result==0 #50 + $display("%b| %b %b %b|%b %b| %b", command, carryin, operandA, operandB, result, carryout, correct); + + command = `b000; carryin = 1; operandA=0; operandB=0; correct = result==1 #50 + $display("%b| %b %b %b|%b %b| %b", command, carryin, operandA, operandB, result, carryout, correct); + command = `b000; carryin = 1; operandA=0; operandB=1; correct = result==0 #50 + $display("%b| %b %b %b|%b %b| %b", command, carryin, operandA, operandB, result, carryout, correct); + command = `b000; carryin = 1; operandA=1; operandB=0; correct = result==0 #50 + $display("%b| %b %b %b|%b %b| %b", command, carryin, operandA, operandB, result, carryout, correct); + command = `b000; carryin = 1; operandA=1; operandB=1; correct = result==1 #50 + $display("%b| %b %b %b|%b %b| %b", command, carryin, operandA, operandB, result, carryout, correct); + + + //SL + command = `b010; operandA=0; operandB=0; correct = result==0 #50 + $display("%b| %b %b|%b %b| %b", command, operandA, operandB, result, carryout, correct); + command = `b010; operandA=0; operandB=1; correct = result==1 #50 + $display("%b| %b %b|%b %b| %b", command, operandA, operandB, result, carryout, correct); + command = `b010; operandA=1; operandB=0; correct = result==0 #50 + $display("%b| %b %b|%b %b| %b", command, operandA, operandB, result, carryout, correct); + command = `b010; operandA=1; operandB=1;correct = result==0 #50 + $display("%b| %b %b|%b %b| %b", command, operandA, operandB, result, carryout, correct); + + //XOR + command = `b011; operandA=0; operandB=0; correct = result==0 #50 + $display("%b| %b %b|%b %b| %b", command, operandA, operandB, result, carryout, correct); + command = `b011; operandA=0; operandB=1;correct = result==1 #50 + $display("%b| %b %b|%b %b| %b", command, operandA, operandB, result, carryout, correct); + command = `b011; operandA=1; operandB=0; correct = result==1 #50 + $display("%b| %b %b|%b %b| %b", command, operandA, operandB, result, carryout, correct); + command = `b011; operandA=1; operandB=1; correct = result==0 #50 + $display("%b| %b %b|%b %b| %b", command, operandA, operandB, result, carryout, correct); + + //AND + command = `b100; operandA=0; operandB=0; correct = result==0 #50 + $display("%b| %b %b|%b %b| %b", command, operandA, operandB, result, carryout, correct); + command = `b100; operandA=0; operandB=1; correct = result==0 #50 + $display("%b| %b %b|%b %b| %b", command, operandA, operandB, result, carryout, correct); + command = `b100; operandA=1; operandB=0; correct = result==0 #50 + $display("%b| %b %b|%b %b| %b", command, operandA, operandB, result, carryout, correct); + command = `b100; operandA=1; operandB=1; correct = result==1 #50 + $display("%b| %b %b|%b %b| %b", command, operandA, operandB, result, carryout, correct); + + //NAND + command = `b100; operandA=0; operandB=0; correct = result==1 #50 + $display("%b| %b %b|%b %b| %b", command, operandA, operandB, result, carryout, correct); + command = `b100; operandA=0; operandB=1; correct = result==1 #50 + $display("%b| %b %b|%b %b| %b", command, operandA, operandB, result, carryout, correct); + command = `b100; operandA=1; operandB=0; correct = result==1 #50 + $display("%b| %b %b|%b %b| %b", command, operandA, operandB, result, carryout, correct); + command = `b100; operandA=1; operandB=1; correct = result==0 #50 + $display("%b| %b %b|%b %b| %b", command, operandA, operandB, result, carryout, correct); + + //OR + command = `b100; operandA=0; operandB=0; correct = result===0 #50 + $display("%b| %b %b|%b %b| %b", command, operandA, operandB, result, carryout, correct); + command = `b100; operandA=0; operandB=1; correct = result==1 #50 + $display("%b| %b %b|%b %b| %b", command, operandA, operandB, result, carryout, correct); + command = `b000; operandA=1; operandB=0; correct = result==1 #50 + $display("%b| %b %b|%b %b| %b", command, operandA, operandB, result, carryout, correct); + command = `b000; operandA=1; operandB=1; correct = result==1 #50 + $display("%b| %b %b|%b %b| %b", command, operandA, operandB, result, carryout, correct); + + //NOR + command = `b000; operandA=0; operandB=0; correct = result==1 #50 + $display("%b| %b %b|%b %b| %b", command, operandA, operandB, result, carryout, correct); + command = `b000; operandA=0; operandB=1; correct = result==0 #50 + $display("%b| %b %b|%b %b| %b", command, operandA, operandB, result, carryout, correct); + command = `b000; operandA=1; operandB=0; correct = result==0 #50 + $display("%b| %b %b|%b %b| %b", command, operandA, operandB, result, carryout, correct); + command = `b000; operandA=1; operandB=1; correct = result==0 #50 + $display("%b| %b %b|%b %b| %b", command, operandA, operandB, result, carryout, correct); + + + + end + +endmodule \ No newline at end of file From 7b2b9b9e18f82f555bdab5b217b597a9b3a3655a Mon Sep 17 00:00:00 2001 From: Bryan Werth Date: Tue, 10 Oct 2017 20:43:01 -0400 Subject: [PATCH 03/28] Finished Single Bit ALU --- alu_single_bit.v | 48 ++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 48 insertions(+) create mode 100644 alu_single_bit.v diff --git a/alu_single_bit.v b/alu_single_bit.v new file mode 100644 index 0000000..57264df --- /dev/null +++ b/alu_single_bit.v @@ -0,0 +1,48 @@ +module ALU_single_bit(result, carryout, operandA, operandB, carryin, command); + + output result; + output carryout; + input operandA; + input operandB; + input carryin; + input [2:0] command; + + reg result; + reg carryout = 0; + wire operandA, operandB, carryin, addedResult, xorResult, andResult, nandResult, norResult, orResult; + + single_bit_adder adder(addedResult, carryout, operandA, operandB, carryin); + xor xorgate(xorResult, operandA, operandB); + and andgate(andResult, operandA, operandB); + nand nandgate(nandResult, operandA, operandB); + nor norgate(norResult, operandA, operandB); + or orgate(orResult, operandA, operandB); + + always @ (command) begin + case(command) + 3'b000: result = addedResult; + 3'b010: result = xorResult; + 3'b011: result = operandA Date: Tue, 10 Oct 2017 21:00:34 -0400 Subject: [PATCH 04/28] Fixed the Test Bench --- alusingle.t.v | 70 +++++++++++++++++++++++++-------------------------- 1 file changed, 35 insertions(+), 35 deletions(-) diff --git a/alusingle.t.v b/alusingle.t.v index 392e589..6c39c0e 100644 --- a/alusingle.t.v +++ b/alusingle.t.v @@ -1,10 +1,10 @@ // Single Bit ALU testbench `timescale 1 ns / 1 ps -`include "alusinglebit.v" +`include "alu_single_bit.v" module testSingleBitALU (); - reg operandA, operandB, carryin, command; - wire result, carryout, correct; + reg operandA, operandB, carryin, command, correct; + wire result, carryout; ALUsinglebit alusinglebittest(result,carryout,operandA,operandB,carryin,command); @@ -12,83 +12,83 @@ module testSingleBitALU (); $display("command | carryin operandA operandB| result carryout | correct"); //Add - command = `b000; carryin = 0; operandA=0; operandB=0; correct = result==0 #50 + command = 3'b000; carryin = 0; operandA=0; operandB=0; correct = result==0; #50 $display("%b| %b %b %b|%b %b| %b", command, carryin, operandA, operandB, result, carryout, correct); - command = `b000; carryin = 0; operandA=0; operandB=1; correct = result==1 #50 + command = 3'b000; carryin = 0; operandA=0; operandB=1; correct = result==1; #50 $display("%b| %b %b %b|%b %b| %b", command, carryin, operandA, operandB, result, carryout, correct); - command = `b000; carryin = 0; operandA=1; operandB=0; correct = result==1 #50 + command = 3'b000; carryin = 0; operandA=1; operandB=0; correct = result==1; #50 $display("%b| %b %b %b|%b %b| %b", command, carryin, operandA, operandB, result, carryout, correct); - command = `b000; carryin = 0; operandA=1; operandB=1; correct = result==0 #50 + command = 3'b000; carryin = 0; operandA=1; operandB=1; correct = result==0; #50 $display("%b| %b %b %b|%b %b| %b", command, carryin, operandA, operandB, result, carryout, correct); - command = `b000; carryin = 1; operandA=0; operandB=0; correct = result==1 #50 + command = 3'b000; carryin = 1; operandA=0; operandB=0; correct = result==1; #50 $display("%b| %b %b %b|%b %b| %b", command, carryin, operandA, operandB, result, carryout, correct); - command = `b000; carryin = 1; operandA=0; operandB=1; correct = result==0 #50 + command = 3'b000; carryin = 1; operandA=0; operandB=1; correct = result==0; #50 $display("%b| %b %b %b|%b %b| %b", command, carryin, operandA, operandB, result, carryout, correct); - command = `b000; carryin = 1; operandA=1; operandB=0; correct = result==0 #50 + command = 3'b000; carryin = 1; operandA=1; operandB=0; correct = result==0; #50 $display("%b| %b %b %b|%b %b| %b", command, carryin, operandA, operandB, result, carryout, correct); - command = `b000; carryin = 1; operandA=1; operandB=1; correct = result==1 #50 + command = 3'b000; carryin = 1; operandA=1; operandB=1; correct = result==1; #50 $display("%b| %b %b %b|%b %b| %b", command, carryin, operandA, operandB, result, carryout, correct); //SL - command = `b010; operandA=0; operandB=0; correct = result==0 #50 + command = 3'b010; operandA=0; operandB=0; correct = result==0; #50 $display("%b| %b %b|%b %b| %b", command, operandA, operandB, result, carryout, correct); - command = `b010; operandA=0; operandB=1; correct = result==1 #50 + command = 3'b010; operandA=0; operandB=1; correct = result==1; #50 $display("%b| %b %b|%b %b| %b", command, operandA, operandB, result, carryout, correct); - command = `b010; operandA=1; operandB=0; correct = result==0 #50 + command = 3'b010; operandA=1; operandB=0; correct = result==0; #50 $display("%b| %b %b|%b %b| %b", command, operandA, operandB, result, carryout, correct); - command = `b010; operandA=1; operandB=1;correct = result==0 #50 + command = 3'b010; operandA=1; operandB=1;correct = result==0; #50 $display("%b| %b %b|%b %b| %b", command, operandA, operandB, result, carryout, correct); //XOR - command = `b011; operandA=0; operandB=0; correct = result==0 #50 + command = 3'b011; operandA=0; operandB=0; correct = result==0; #50 $display("%b| %b %b|%b %b| %b", command, operandA, operandB, result, carryout, correct); - command = `b011; operandA=0; operandB=1;correct = result==1 #50 + command = 3'b011; operandA=0; operandB=1;correct = result==1; #50 $display("%b| %b %b|%b %b| %b", command, operandA, operandB, result, carryout, correct); - command = `b011; operandA=1; operandB=0; correct = result==1 #50 + command = 3'b011; operandA=1; operandB=0; correct = result==1; #50 $display("%b| %b %b|%b %b| %b", command, operandA, operandB, result, carryout, correct); - command = `b011; operandA=1; operandB=1; correct = result==0 #50 + command = 3'b011; operandA=1; operandB=1; correct = result==0; #50 $display("%b| %b %b|%b %b| %b", command, operandA, operandB, result, carryout, correct); //AND - command = `b100; operandA=0; operandB=0; correct = result==0 #50 + command = 3'b100; operandA=0; operandB=0; correct = result==0; #50 $display("%b| %b %b|%b %b| %b", command, operandA, operandB, result, carryout, correct); - command = `b100; operandA=0; operandB=1; correct = result==0 #50 + command = 3'b100; operandA=0; operandB=1; correct = result==0; #50 $display("%b| %b %b|%b %b| %b", command, operandA, operandB, result, carryout, correct); - command = `b100; operandA=1; operandB=0; correct = result==0 #50 + command = 3'b100; operandA=1; operandB=0; correct = result==0; #50 $display("%b| %b %b|%b %b| %b", command, operandA, operandB, result, carryout, correct); - command = `b100; operandA=1; operandB=1; correct = result==1 #50 + command = 3'b100; operandA=1; operandB=1; correct = result==1; #50 $display("%b| %b %b|%b %b| %b", command, operandA, operandB, result, carryout, correct); //NAND - command = `b100; operandA=0; operandB=0; correct = result==1 #50 + command = 3'b100; operandA=0; operandB=0; correct = result==1; #50 $display("%b| %b %b|%b %b| %b", command, operandA, operandB, result, carryout, correct); - command = `b100; operandA=0; operandB=1; correct = result==1 #50 + command = 3'b100; operandA=0; operandB=1; correct = result==1; #50 $display("%b| %b %b|%b %b| %b", command, operandA, operandB, result, carryout, correct); - command = `b100; operandA=1; operandB=0; correct = result==1 #50 + command = 3'b100; operandA=1; operandB=0; correct = result==1; #50 $display("%b| %b %b|%b %b| %b", command, operandA, operandB, result, carryout, correct); - command = `b100; operandA=1; operandB=1; correct = result==0 #50 + command = 3'b100; operandA=1; operandB=1; correct = result==0; #50 $display("%b| %b %b|%b %b| %b", command, operandA, operandB, result, carryout, correct); //OR - command = `b100; operandA=0; operandB=0; correct = result===0 #50 + command = 3'b100; operandA=0; operandB=0; correct = result===0; #50 $display("%b| %b %b|%b %b| %b", command, operandA, operandB, result, carryout, correct); - command = `b100; operandA=0; operandB=1; correct = result==1 #50 + command = 3'b100; operandA=0; operandB=1; correct = result==1; #50 $display("%b| %b %b|%b %b| %b", command, operandA, operandB, result, carryout, correct); - command = `b000; operandA=1; operandB=0; correct = result==1 #50 + command = 3'b000; operandA=1; operandB=0; correct = result==1; #50 $display("%b| %b %b|%b %b| %b", command, operandA, operandB, result, carryout, correct); - command = `b000; operandA=1; operandB=1; correct = result==1 #50 + command = 3'b000; operandA=1; operandB=1; correct = result==1; #50 $display("%b| %b %b|%b %b| %b", command, operandA, operandB, result, carryout, correct); //NOR - command = `b000; operandA=0; operandB=0; correct = result==1 #50 + command = 3'b000; operandA=0; operandB=0; correct = result==1; #50 $display("%b| %b %b|%b %b| %b", command, operandA, operandB, result, carryout, correct); - command = `b000; operandA=0; operandB=1; correct = result==0 #50 + command = 3'b000; operandA=0; operandB=1; correct = result==0; #50 $display("%b| %b %b|%b %b| %b", command, operandA, operandB, result, carryout, correct); - command = `b000; operandA=1; operandB=0; correct = result==0 #50 + command = 3'b000; operandA=1; operandB=0; correct = result==0; #50 $display("%b| %b %b|%b %b| %b", command, operandA, operandB, result, carryout, correct); - command = `b000; operandA=1; operandB=1; correct = result==0 #50 + command = 3'b000; operandA=1; operandB=1; correct = result==0; #50 $display("%b| %b %b|%b %b| %b", command, operandA, operandB, result, carryout, correct); From 62fab5dfa9a7ea7a54263c1c5d341b7afae2fd01 Mon Sep 17 00:00:00 2001 From: Bryan Werth Date: Tue, 10 Oct 2017 21:03:14 -0400 Subject: [PATCH 05/28] Changed the module call --- alu_single_bit.t.v | 98 ++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 98 insertions(+) create mode 100644 alu_single_bit.t.v diff --git a/alu_single_bit.t.v b/alu_single_bit.t.v new file mode 100644 index 0000000..6c39c0e --- /dev/null +++ b/alu_single_bit.t.v @@ -0,0 +1,98 @@ +// Single Bit ALU testbench +`timescale 1 ns / 1 ps +`include "alu_single_bit.v" + +module testSingleBitALU (); + reg operandA, operandB, carryin, command, correct; + wire result, carryout; + + ALUsinglebit alusinglebittest(result,carryout,operandA,operandB,carryin,command); + + initial begin + $display("command | carryin operandA operandB| result carryout | correct"); + + //Add + command = 3'b000; carryin = 0; operandA=0; operandB=0; correct = result==0; #50 + $display("%b| %b %b %b|%b %b| %b", command, carryin, operandA, operandB, result, carryout, correct); + command = 3'b000; carryin = 0; operandA=0; operandB=1; correct = result==1; #50 + $display("%b| %b %b %b|%b %b| %b", command, carryin, operandA, operandB, result, carryout, correct); + command = 3'b000; carryin = 0; operandA=1; operandB=0; correct = result==1; #50 + $display("%b| %b %b %b|%b %b| %b", command, carryin, operandA, operandB, result, carryout, correct); + command = 3'b000; carryin = 0; operandA=1; operandB=1; correct = result==0; #50 + $display("%b| %b %b %b|%b %b| %b", command, carryin, operandA, operandB, result, carryout, correct); + + command = 3'b000; carryin = 1; operandA=0; operandB=0; correct = result==1; #50 + $display("%b| %b %b %b|%b %b| %b", command, carryin, operandA, operandB, result, carryout, correct); + command = 3'b000; carryin = 1; operandA=0; operandB=1; correct = result==0; #50 + $display("%b| %b %b %b|%b %b| %b", command, carryin, operandA, operandB, result, carryout, correct); + command = 3'b000; carryin = 1; operandA=1; operandB=0; correct = result==0; #50 + $display("%b| %b %b %b|%b %b| %b", command, carryin, operandA, operandB, result, carryout, correct); + command = 3'b000; carryin = 1; operandA=1; operandB=1; correct = result==1; #50 + $display("%b| %b %b %b|%b %b| %b", command, carryin, operandA, operandB, result, carryout, correct); + + + //SL + command = 3'b010; operandA=0; operandB=0; correct = result==0; #50 + $display("%b| %b %b|%b %b| %b", command, operandA, operandB, result, carryout, correct); + command = 3'b010; operandA=0; operandB=1; correct = result==1; #50 + $display("%b| %b %b|%b %b| %b", command, operandA, operandB, result, carryout, correct); + command = 3'b010; operandA=1; operandB=0; correct = result==0; #50 + $display("%b| %b %b|%b %b| %b", command, operandA, operandB, result, carryout, correct); + command = 3'b010; operandA=1; operandB=1;correct = result==0; #50 + $display("%b| %b %b|%b %b| %b", command, operandA, operandB, result, carryout, correct); + + //XOR + command = 3'b011; operandA=0; operandB=0; correct = result==0; #50 + $display("%b| %b %b|%b %b| %b", command, operandA, operandB, result, carryout, correct); + command = 3'b011; operandA=0; operandB=1;correct = result==1; #50 + $display("%b| %b %b|%b %b| %b", command, operandA, operandB, result, carryout, correct); + command = 3'b011; operandA=1; operandB=0; correct = result==1; #50 + $display("%b| %b %b|%b %b| %b", command, operandA, operandB, result, carryout, correct); + command = 3'b011; operandA=1; operandB=1; correct = result==0; #50 + $display("%b| %b %b|%b %b| %b", command, operandA, operandB, result, carryout, correct); + + //AND + command = 3'b100; operandA=0; operandB=0; correct = result==0; #50 + $display("%b| %b %b|%b %b| %b", command, operandA, operandB, result, carryout, correct); + command = 3'b100; operandA=0; operandB=1; correct = result==0; #50 + $display("%b| %b %b|%b %b| %b", command, operandA, operandB, result, carryout, correct); + command = 3'b100; operandA=1; operandB=0; correct = result==0; #50 + $display("%b| %b %b|%b %b| %b", command, operandA, operandB, result, carryout, correct); + command = 3'b100; operandA=1; operandB=1; correct = result==1; #50 + $display("%b| %b %b|%b %b| %b", command, operandA, operandB, result, carryout, correct); + + //NAND + command = 3'b100; operandA=0; operandB=0; correct = result==1; #50 + $display("%b| %b %b|%b %b| %b", command, operandA, operandB, result, carryout, correct); + command = 3'b100; operandA=0; operandB=1; correct = result==1; #50 + $display("%b| %b %b|%b %b| %b", command, operandA, operandB, result, carryout, correct); + command = 3'b100; operandA=1; operandB=0; correct = result==1; #50 + $display("%b| %b %b|%b %b| %b", command, operandA, operandB, result, carryout, correct); + command = 3'b100; operandA=1; operandB=1; correct = result==0; #50 + $display("%b| %b %b|%b %b| %b", command, operandA, operandB, result, carryout, correct); + + //OR + command = 3'b100; operandA=0; operandB=0; correct = result===0; #50 + $display("%b| %b %b|%b %b| %b", command, operandA, operandB, result, carryout, correct); + command = 3'b100; operandA=0; operandB=1; correct = result==1; #50 + $display("%b| %b %b|%b %b| %b", command, operandA, operandB, result, carryout, correct); + command = 3'b000; operandA=1; operandB=0; correct = result==1; #50 + $display("%b| %b %b|%b %b| %b", command, operandA, operandB, result, carryout, correct); + command = 3'b000; operandA=1; operandB=1; correct = result==1; #50 + $display("%b| %b %b|%b %b| %b", command, operandA, operandB, result, carryout, correct); + + //NOR + command = 3'b000; operandA=0; operandB=0; correct = result==1; #50 + $display("%b| %b %b|%b %b| %b", command, operandA, operandB, result, carryout, correct); + command = 3'b000; operandA=0; operandB=1; correct = result==0; #50 + $display("%b| %b %b|%b %b| %b", command, operandA, operandB, result, carryout, correct); + command = 3'b000; operandA=1; operandB=0; correct = result==0; #50 + $display("%b| %b %b|%b %b| %b", command, operandA, operandB, result, carryout, correct); + command = 3'b000; operandA=1; operandB=1; correct = result==0; #50 + $display("%b| %b %b|%b %b| %b", command, operandA, operandB, result, carryout, correct); + + + + end + +endmodule \ No newline at end of file From 30e8e51cbd044c1c4f500ebcbafe3a551c94383d Mon Sep 17 00:00:00 2001 From: Bryan Werth Date: Tue, 10 Oct 2017 21:19:27 -0400 Subject: [PATCH 06/28] Finished --- alusingle.t.v | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/alusingle.t.v b/alusingle.t.v index 6c39c0e..c53e1a9 100644 --- a/alusingle.t.v +++ b/alusingle.t.v @@ -3,16 +3,18 @@ `include "alu_single_bit.v" module testSingleBitALU (); - reg operandA, operandB, carryin, command, correct; + reg operandA, operandB, carryin, correct; + reg [2:0] command; wire result, carryout; - ALUsinglebit alusinglebittest(result,carryout,operandA,operandB,carryin,command); + assign correct = result == + ALU_single_bit alusinglebittest(result,carryout,operandA,operandB,carryin,command); initial begin $display("command | carryin operandA operandB| result carryout | correct"); //Add - command = 3'b000; carryin = 0; operandA=0; operandB=0; correct = result==0; #50 + command = 3'b000; carryin = 0; operandA=0; operandB=0; #50 $display("%b| %b %b %b|%b %b| %b", command, carryin, operandA, operandB, result, carryout, correct); command = 3'b000; carryin = 0; operandA=0; operandB=1; correct = result==1; #50 $display("%b| %b %b %b|%b %b| %b", command, carryin, operandA, operandB, result, carryout, correct); @@ -91,8 +93,6 @@ module testSingleBitALU (); command = 3'b000; operandA=1; operandB=1; correct = result==0; #50 $display("%b| %b %b|%b %b| %b", command, operandA, operandB, result, carryout, correct); - - end endmodule \ No newline at end of file From 3fdd5c719abc37258f75248963258053ec51e918 Mon Sep 17 00:00:00 2001 From: Bryan Werth Date: Tue, 10 Oct 2017 21:25:47 -0400 Subject: [PATCH 07/28] Clarified Things --- alu_single_bit.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/alu_single_bit.v b/alu_single_bit.v index 57264df..89afa58 100644 --- a/alu_single_bit.v +++ b/alu_single_bit.v @@ -8,7 +8,7 @@ module ALU_single_bit(result, carryout, operandA, operandB, carryin, command); input [2:0] command; reg result; - reg carryout = 0; + wire carryout = 0; wire operandA, operandB, carryin, addedResult, xorResult, andResult, nandResult, norResult, orResult; single_bit_adder adder(addedResult, carryout, operandA, operandB, carryin); From 42cadc450cb30cc0ab3737e370128d379d0d35a6 Mon Sep 17 00:00:00 2001 From: Bryan Werth Date: Wed, 11 Oct 2017 19:32:16 -0400 Subject: [PATCH 08/28] Made the single bit test bench a little bit more user friendly --- alu_single_bit.t.v | 161 +++++++++++++++++++++++---------------------- alu_single_bit.v | 1 - 2 files changed, 83 insertions(+), 79 deletions(-) diff --git a/alu_single_bit.t.v b/alu_single_bit.t.v index 6c39c0e..099fa13 100644 --- a/alu_single_bit.t.v +++ b/alu_single_bit.t.v @@ -1,98 +1,103 @@ // Single Bit ALU testbench -`timescale 1 ns / 1 ps `include "alu_single_bit.v" module testSingleBitALU (); - reg operandA, operandB, carryin, command, correct; + reg operandA, operandB, carryin; + reg [2:0] command; + reg [9:0] numBroken = 0; wire result, carryout; - ALUsinglebit alusinglebittest(result,carryout,operandA,operandB,carryin,command); + ALU_single_bit alusinglebittest(.result (result),.carryout (carryout),.operandA (operandA),.operandB (operandB),.carryin (carryin),.command (command)); + + task checkTestCase; + input [2:0] commandIn; + input operandAIn; + input operandBIn; + input expectedResult; + + begin + command = commandIn; operandA = operandAIn; operandB = operandBIn; #50 + $display("Testing command %b, operandA %b, and operandB %b", command, operandA, operandB); + if (result == expectedResult) begin + $display("Test Passed, result is %b", result); + end else begin + numBroken = numBroken + 1; + $display("ERROR: Expected %b, but actual output was %b", expectedResult, result); + end + end + endtask + + task checkAddTestCase; + input [2:0] commandIn; + input carryinIn; + input operandAIn; + input operandBIn; + input expectedResult; + input expectedCarryout; + + begin + command = commandIn; carryin = carryinIn; operandA = operandAIn; operandB = operandBIn; #50 + $display("Testing command %b, carryin %b, operandA %b, and operandB %b", command, carryin, operandA, operandB); + if (result == expectedResult && carryout == expectedCarryout) begin + $display("Test Passed, result is %b and carryout is %b", result, carryout); + end else begin + numBroken = numBroken + 1; + $display("ERROR: Expected %b as result and %b as carryout, but actual output was %b and actual carryout was %b", expectedResult, expectedCarryout, result, carryout); + end + end + endtask initial begin - $display("command | carryin operandA operandB| result carryout | correct"); - //Add - command = 3'b000; carryin = 0; operandA=0; operandB=0; correct = result==0; #50 - $display("%b| %b %b %b|%b %b| %b", command, carryin, operandA, operandB, result, carryout, correct); - command = 3'b000; carryin = 0; operandA=0; operandB=1; correct = result==1; #50 - $display("%b| %b %b %b|%b %b| %b", command, carryin, operandA, operandB, result, carryout, correct); - command = 3'b000; carryin = 0; operandA=1; operandB=0; correct = result==1; #50 - $display("%b| %b %b %b|%b %b| %b", command, carryin, operandA, operandB, result, carryout, correct); - command = 3'b000; carryin = 0; operandA=1; operandB=1; correct = result==0; #50 - $display("%b| %b %b %b|%b %b| %b", command, carryin, operandA, operandB, result, carryout, correct); - - command = 3'b000; carryin = 1; operandA=0; operandB=0; correct = result==1; #50 - $display("%b| %b %b %b|%b %b| %b", command, carryin, operandA, operandB, result, carryout, correct); - command = 3'b000; carryin = 1; operandA=0; operandB=1; correct = result==0; #50 - $display("%b| %b %b %b|%b %b| %b", command, carryin, operandA, operandB, result, carryout, correct); - command = 3'b000; carryin = 1; operandA=1; operandB=0; correct = result==0; #50 - $display("%b| %b %b %b|%b %b| %b", command, carryin, operandA, operandB, result, carryout, correct); - command = 3'b000; carryin = 1; operandA=1; operandB=1; correct = result==1; #50 - $display("%b| %b %b %b|%b %b| %b", command, carryin, operandA, operandB, result, carryout, correct); + //Add + checkAddTestCase(3'b000,0,0,1,1,0); + checkAddTestCase(3'b000,0,0,1,1,0); + checkAddTestCase(3'b000,0,1,0,1,0); + checkAddTestCase(3'b000,0,1,1,0,1); + checkAddTestCase(3'b000,1,0,0,1,0); + checkAddTestCase(3'b000,1,0,1,0,1); + checkAddTestCase(3'b000,1,1,0,0,1); + checkAddTestCase(3'b000,1,1,1,1,1); - //SL - command = 3'b010; operandA=0; operandB=0; correct = result==0; #50 - $display("%b| %b %b|%b %b| %b", command, operandA, operandB, result, carryout, correct); - command = 3'b010; operandA=0; operandB=1; correct = result==1; #50 - $display("%b| %b %b|%b %b| %b", command, operandA, operandB, result, carryout, correct); - command = 3'b010; operandA=1; operandB=0; correct = result==0; #50 - $display("%b| %b %b|%b %b| %b", command, operandA, operandB, result, carryout, correct); - command = 3'b010; operandA=1; operandB=1;correct = result==0; #50 - $display("%b| %b %b|%b %b| %b", command, operandA, operandB, result, carryout, correct); + //SL + checkTestCase(3'b010,0,0,0); + checkTestCase(3'b010,0,1,1); + checkTestCase(3'b010,1,0,0); + checkTestCase(3'b010,1,1,0); - //XOR - command = 3'b011; operandA=0; operandB=0; correct = result==0; #50 - $display("%b| %b %b|%b %b| %b", command, operandA, operandB, result, carryout, correct); - command = 3'b011; operandA=0; operandB=1;correct = result==1; #50 - $display("%b| %b %b|%b %b| %b", command, operandA, operandB, result, carryout, correct); - command = 3'b011; operandA=1; operandB=0; correct = result==1; #50 - $display("%b| %b %b|%b %b| %b", command, operandA, operandB, result, carryout, correct); - command = 3'b011; operandA=1; operandB=1; correct = result==0; #50 - $display("%b| %b %b|%b %b| %b", command, operandA, operandB, result, carryout, correct); + //XOR + checkTestCase(3'b011,0,0,0); + checkTestCase(3'b011,0,1,1); + checkTestCase(3'b011,1,0,1); + checkTestCase(3'b011,1,1,0); - //AND - command = 3'b100; operandA=0; operandB=0; correct = result==0; #50 - $display("%b| %b %b|%b %b| %b", command, operandA, operandB, result, carryout, correct); - command = 3'b100; operandA=0; operandB=1; correct = result==0; #50 - $display("%b| %b %b|%b %b| %b", command, operandA, operandB, result, carryout, correct); - command = 3'b100; operandA=1; operandB=0; correct = result==0; #50 - $display("%b| %b %b|%b %b| %b", command, operandA, operandB, result, carryout, correct); - command = 3'b100; operandA=1; operandB=1; correct = result==1; #50 - $display("%b| %b %b|%b %b| %b", command, operandA, operandB, result, carryout, correct); + //AND + checkTestCase(3'b100,0,0,0); + checkTestCase(3'b100,0,1,0); + checkTestCase(3'b100,1,0,0); + checkTestCase(3'b100,1,1,1); - //NAND - command = 3'b100; operandA=0; operandB=0; correct = result==1; #50 - $display("%b| %b %b|%b %b| %b", command, operandA, operandB, result, carryout, correct); - command = 3'b100; operandA=0; operandB=1; correct = result==1; #50 - $display("%b| %b %b|%b %b| %b", command, operandA, operandB, result, carryout, correct); - command = 3'b100; operandA=1; operandB=0; correct = result==1; #50 - $display("%b| %b %b|%b %b| %b", command, operandA, operandB, result, carryout, correct); - command = 3'b100; operandA=1; operandB=1; correct = result==0; #50 - $display("%b| %b %b|%b %b| %b", command, operandA, operandB, result, carryout, correct); + //NAND + checkTestCase(3'b101,0,0,1); + checkTestCase(3'b101,0,1,1); + checkTestCase(3'b101,1,0,1); + checkTestCase(3'b101,1,1,0); - //OR - command = 3'b100; operandA=0; operandB=0; correct = result===0; #50 - $display("%b| %b %b|%b %b| %b", command, operandA, operandB, result, carryout, correct); - command = 3'b100; operandA=0; operandB=1; correct = result==1; #50 - $display("%b| %b %b|%b %b| %b", command, operandA, operandB, result, carryout, correct); - command = 3'b000; operandA=1; operandB=0; correct = result==1; #50 - $display("%b| %b %b|%b %b| %b", command, operandA, operandB, result, carryout, correct); - command = 3'b000; operandA=1; operandB=1; correct = result==1; #50 - $display("%b| %b %b|%b %b| %b", command, operandA, operandB, result, carryout, correct); + //OR + checkTestCase(3'b110,0,0,0); + checkTestCase(3'b110,0,1,1); + checkTestCase(3'b110,1,0,1); + checkTestCase(3'b110,1,1,1); - //NOR - command = 3'b000; operandA=0; operandB=0; correct = result==1; #50 - $display("%b| %b %b|%b %b| %b", command, operandA, operandB, result, carryout, correct); - command = 3'b000; operandA=0; operandB=1; correct = result==0; #50 - $display("%b| %b %b|%b %b| %b", command, operandA, operandB, result, carryout, correct); - command = 3'b000; operandA=1; operandB=0; correct = result==0; #50 - $display("%b| %b %b|%b %b| %b", command, operandA, operandB, result, carryout, correct); - command = 3'b000; operandA=1; operandB=1; correct = result==0; #50 - $display("%b| %b %b|%b %b| %b", command, operandA, operandB, result, carryout, correct); - + //NOR + checkTestCase(3'b111,0,0,1); + checkTestCase(3'b111,0,1,0); + checkTestCase(3'b111,1,0,0); + checkTestCase(3'b111,1,1,0); - + $display("%d test cases failed", numBroken); + end endmodule \ No newline at end of file diff --git a/alu_single_bit.v b/alu_single_bit.v index 89afa58..649b8e0 100644 --- a/alu_single_bit.v +++ b/alu_single_bit.v @@ -40,7 +40,6 @@ module single_bit_adder(result, carryout, A, B, carryin); input carryin; wire carryout, result; - wire A,B; assign carryout = (A && B) || (((!A && B) || (A && !B)) && carryin); assign result = (((!A && B) || (A && !B)) && !carryin) || (!((!A && B) || (A && !B)) && carryin); From 6d3691bbdcc3a5805435af6c040a25456c59e87c Mon Sep 17 00:00:00 2001 From: Wilson Tang Date: Wed, 11 Oct 2017 19:33:40 -0400 Subject: [PATCH 09/28] full alu --- alu_single_bit.t.v | 2 +- alusingle.t.v | 3 +-- 2 files changed, 2 insertions(+), 3 deletions(-) diff --git a/alu_single_bit.t.v b/alu_single_bit.t.v index 6c39c0e..f91b14b 100644 --- a/alu_single_bit.t.v +++ b/alu_single_bit.t.v @@ -6,7 +6,7 @@ module testSingleBitALU (); reg operandA, operandB, carryin, command, correct; wire result, carryout; - ALUsinglebit alusinglebittest(result,carryout,operandA,operandB,carryin,command); + ALU_single_bit alusinglebittest(result,carryout,operandA,operandB,carryin,command); initial begin $display("command | carryin operandA operandB| result carryout | correct"); diff --git a/alusingle.t.v b/alusingle.t.v index c53e1a9..4645e91 100644 --- a/alusingle.t.v +++ b/alusingle.t.v @@ -6,8 +6,7 @@ module testSingleBitALU (); reg operandA, operandB, carryin, correct; reg [2:0] command; wire result, carryout; - - assign correct = result == + ALU_single_bit alusinglebittest(result,carryout,operandA,operandB,carryin,command); initial begin From 1f8ddc3318b04e182ccf12ece970e69a06197f75 Mon Sep 17 00:00:00 2001 From: Wilson Tang Date: Wed, 11 Oct 2017 19:42:24 -0400 Subject: [PATCH 10/28] alu.v --- alu.v | 125 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 125 insertions(+) create mode 100644 alu.v diff --git a/alu.v b/alu.v new file mode 100644 index 0000000..49176e5 --- /dev/null +++ b/alu.v @@ -0,0 +1,125 @@ + + +module ALU(result, carryout, operandA, operandB, carryin, command); + + output result[31:0]; + output carryout; + input operandA[31:0]; + input operandB[31:0]; + input carryin; + input [2:0] command; + + reg result; + wire carryout = 0; + wire operandA, operandB, carryin, addedResult, xorResult, andResult, nandResult, norResult, orResult; + + multi_bit_adder adder(addedResult, carryout, operandA, operandB, carryin); + xor xorgate(xorResult, operandA, operandB); + and andgate(andResult, operandA, operandB); + nand nandgate(nandResult, operandA, operandB); + nor norgate(norResult, operandA, operandB); + or orgate(orResult, operandA, operandB); + + always @ (command) begin + case(command) + 3'b000: result = addedResult; + 3'b010: result = xorResult; + 3'b011: result = operandA Date: Wed, 11 Oct 2017 19:42:36 -0400 Subject: [PATCH 11/28] Delete alusingle.t.v --- alusingle.t.v | 97 --------------------------------------------------- 1 file changed, 97 deletions(-) delete mode 100644 alusingle.t.v diff --git a/alusingle.t.v b/alusingle.t.v deleted file mode 100644 index 4645e91..0000000 --- a/alusingle.t.v +++ /dev/null @@ -1,97 +0,0 @@ -// Single Bit ALU testbench -`timescale 1 ns / 1 ps -`include "alu_single_bit.v" - -module testSingleBitALU (); - reg operandA, operandB, carryin, correct; - reg [2:0] command; - wire result, carryout; - - ALU_single_bit alusinglebittest(result,carryout,operandA,operandB,carryin,command); - - initial begin - $display("command | carryin operandA operandB| result carryout | correct"); - - //Add - command = 3'b000; carryin = 0; operandA=0; operandB=0; #50 - $display("%b| %b %b %b|%b %b| %b", command, carryin, operandA, operandB, result, carryout, correct); - command = 3'b000; carryin = 0; operandA=0; operandB=1; correct = result==1; #50 - $display("%b| %b %b %b|%b %b| %b", command, carryin, operandA, operandB, result, carryout, correct); - command = 3'b000; carryin = 0; operandA=1; operandB=0; correct = result==1; #50 - $display("%b| %b %b %b|%b %b| %b", command, carryin, operandA, operandB, result, carryout, correct); - command = 3'b000; carryin = 0; operandA=1; operandB=1; correct = result==0; #50 - $display("%b| %b %b %b|%b %b| %b", command, carryin, operandA, operandB, result, carryout, correct); - - command = 3'b000; carryin = 1; operandA=0; operandB=0; correct = result==1; #50 - $display("%b| %b %b %b|%b %b| %b", command, carryin, operandA, operandB, result, carryout, correct); - command = 3'b000; carryin = 1; operandA=0; operandB=1; correct = result==0; #50 - $display("%b| %b %b %b|%b %b| %b", command, carryin, operandA, operandB, result, carryout, correct); - command = 3'b000; carryin = 1; operandA=1; operandB=0; correct = result==0; #50 - $display("%b| %b %b %b|%b %b| %b", command, carryin, operandA, operandB, result, carryout, correct); - command = 3'b000; carryin = 1; operandA=1; operandB=1; correct = result==1; #50 - $display("%b| %b %b %b|%b %b| %b", command, carryin, operandA, operandB, result, carryout, correct); - - - //SL - command = 3'b010; operandA=0; operandB=0; correct = result==0; #50 - $display("%b| %b %b|%b %b| %b", command, operandA, operandB, result, carryout, correct); - command = 3'b010; operandA=0; operandB=1; correct = result==1; #50 - $display("%b| %b %b|%b %b| %b", command, operandA, operandB, result, carryout, correct); - command = 3'b010; operandA=1; operandB=0; correct = result==0; #50 - $display("%b| %b %b|%b %b| %b", command, operandA, operandB, result, carryout, correct); - command = 3'b010; operandA=1; operandB=1;correct = result==0; #50 - $display("%b| %b %b|%b %b| %b", command, operandA, operandB, result, carryout, correct); - - //XOR - command = 3'b011; operandA=0; operandB=0; correct = result==0; #50 - $display("%b| %b %b|%b %b| %b", command, operandA, operandB, result, carryout, correct); - command = 3'b011; operandA=0; operandB=1;correct = result==1; #50 - $display("%b| %b %b|%b %b| %b", command, operandA, operandB, result, carryout, correct); - command = 3'b011; operandA=1; operandB=0; correct = result==1; #50 - $display("%b| %b %b|%b %b| %b", command, operandA, operandB, result, carryout, correct); - command = 3'b011; operandA=1; operandB=1; correct = result==0; #50 - $display("%b| %b %b|%b %b| %b", command, operandA, operandB, result, carryout, correct); - - //AND - command = 3'b100; operandA=0; operandB=0; correct = result==0; #50 - $display("%b| %b %b|%b %b| %b", command, operandA, operandB, result, carryout, correct); - command = 3'b100; operandA=0; operandB=1; correct = result==0; #50 - $display("%b| %b %b|%b %b| %b", command, operandA, operandB, result, carryout, correct); - command = 3'b100; operandA=1; operandB=0; correct = result==0; #50 - $display("%b| %b %b|%b %b| %b", command, operandA, operandB, result, carryout, correct); - command = 3'b100; operandA=1; operandB=1; correct = result==1; #50 - $display("%b| %b %b|%b %b| %b", command, operandA, operandB, result, carryout, correct); - - //NAND - command = 3'b100; operandA=0; operandB=0; correct = result==1; #50 - $display("%b| %b %b|%b %b| %b", command, operandA, operandB, result, carryout, correct); - command = 3'b100; operandA=0; operandB=1; correct = result==1; #50 - $display("%b| %b %b|%b %b| %b", command, operandA, operandB, result, carryout, correct); - command = 3'b100; operandA=1; operandB=0; correct = result==1; #50 - $display("%b| %b %b|%b %b| %b", command, operandA, operandB, result, carryout, correct); - command = 3'b100; operandA=1; operandB=1; correct = result==0; #50 - $display("%b| %b %b|%b %b| %b", command, operandA, operandB, result, carryout, correct); - - //OR - command = 3'b100; operandA=0; operandB=0; correct = result===0; #50 - $display("%b| %b %b|%b %b| %b", command, operandA, operandB, result, carryout, correct); - command = 3'b100; operandA=0; operandB=1; correct = result==1; #50 - $display("%b| %b %b|%b %b| %b", command, operandA, operandB, result, carryout, correct); - command = 3'b000; operandA=1; operandB=0; correct = result==1; #50 - $display("%b| %b %b|%b %b| %b", command, operandA, operandB, result, carryout, correct); - command = 3'b000; operandA=1; operandB=1; correct = result==1; #50 - $display("%b| %b %b|%b %b| %b", command, operandA, operandB, result, carryout, correct); - - //NOR - command = 3'b000; operandA=0; operandB=0; correct = result==1; #50 - $display("%b| %b %b|%b %b| %b", command, operandA, operandB, result, carryout, correct); - command = 3'b000; operandA=0; operandB=1; correct = result==0; #50 - $display("%b| %b %b|%b %b| %b", command, operandA, operandB, result, carryout, correct); - command = 3'b000; operandA=1; operandB=0; correct = result==0; #50 - $display("%b| %b %b|%b %b| %b", command, operandA, operandB, result, carryout, correct); - command = 3'b000; operandA=1; operandB=1; correct = result==0; #50 - $display("%b| %b %b|%b %b| %b", command, operandA, operandB, result, carryout, correct); - - end - -endmodule \ No newline at end of file From 064766de167c14621fb2d0bda2b7b917ffdb9b70 Mon Sep 17 00:00:00 2001 From: Wilson Tang Date: Wed, 11 Oct 2017 21:08:47 -0400 Subject: [PATCH 12/28] updated alu.v --- alu.v | 161 ++++++++++++++++++++++++++++++++++++---------------------- 1 file changed, 99 insertions(+), 62 deletions(-) diff --git a/alu.v b/alu.v index 49176e5..7ab1d9e 100644 --- a/alu.v +++ b/alu.v @@ -1,19 +1,24 @@ -module ALU(result, carryout, operandA, operandB, carryin, command); +module ALU(result, carryout, overflow, zero, operandA, operandB, command); - output result[31:0]; + output [31:0] result; output carryout; - input operandA[31:0]; - input operandB[31:0]; - input carryin; + output overflow; + output zero; + input [31:0] operandA; + input [31:0] operandB; input [2:0] command; reg result; wire carryout = 0; - wire operandA, operandB, carryin, addedResult, xorResult, andResult, nandResult, norResult, orResult; + wire overflow = 0; + wire zero = 0; + wire operandA, operandB, carryin, addedResult, subResult, xorResult, sltResult, andResult, nandResult, norResult, orResult; - multi_bit_adder adder(addedResult, carryout, operandA, operandB, carryin); + multi_bit_adder adder(addedResult, carryout, overflow, zero, operandA, operandB); + multi_bit_sub subtracter(subResult, carryout, overflow, zero, operantA, operandB) + multi_bit_slt slt(sltResult,A,B) xor xorgate(xorResult, operandA, operandB); and andgate(andResult, operandA, operandB); nand nandgate(nandResult, operandA, operandB); @@ -23,8 +28,9 @@ module ALU(result, carryout, operandA, operandB, carryin, command); always @ (command) begin case(command) 3'b000: result = addedResult; + 3'b001: result = subResult; 3'b010: result = xorResult; - 3'b011: result = operandAB[n] @ n then stop and return 0 +//If A[n]=B[n] @ n continue until the end +//If A = B , return 0 + +module multi_bit_SLT(sltresult,A,B); initial begin + + for () + if ( single_bit_SLT(A[n],B[n]) ) + + elif + + end +endmodule + +//Calculate SLT for a single bit which is simply notA and B +module single_bit_SLT(results,A,B); + + output result; + input A; + input B; + + not notA(nA,A); + and andslt(result,nA,B) + endmodule -module multi_bit_adder(result, carryout, A, B, carryin); +module multi_bit_adder(result, carryout, overflow, zero, A, B); - output result[31:0]; + output [31:0] result; output carryout; - input A[31:0]; - input B[31:0]; - input carryin; + output overflow; + input [31:0] A; + input [31:0] B; - wire carryout, result; + wire carryout, overflow, zero, result; wire A,B; - single_bit_adder adder0 (sum[0], carryout0, a[0], b[0], 0); - single_bit_adder adder1 (sum[1], carryout1, a[1], b[1], carryout0); - single_bit_adder adder2 (sum[2], carryout2, a[2], b[2], carryout1); - single_bit_adder adder3 (sum[3], carryout3, a[3], b[3], carryout2); - - single_bit_adder adder1 (sum[4], carryout4, a[4], b[4], carryout3); - single_bit_adder adder2 (sum[5], carryout5, a[5], b[5], carryout4); - single_bit_adder adder3 (sum[6], carryout6, a[6], b[6], carryout5); - single_bit_adder adder1 (sum[7], carryout7, a[7], b[7], carryout6); - - single_bit_adder adder2 (sum[8], carryout8, a[8], b[8], carryout7); - single_bit_adder adder3 (sum[9], carryout9, a[9], b[9], carryout8); - single_bit_adder adder1 (sum[10], carryout10, a[10], b[10], carryout9); - single_bit_adder adder2 (sum[11], carryout11, a[11], b[11], carryout10); - single_bit_adder adder3 (sum[12], carryout12, a[12], b[12], carryout11); - single_bit_adder adder1 (sum[13], carryout13, a[13], b[13], carryout12); - single_bit_adder adder2 (sum[14], carryout14, a[14], b[14], carryout13); - single_bit_adder adder3 (sum[15], carryout15, a[15], b[15], carryout14); - - single_bit_adder adder1 (sum[16], carryout16, a[16], b[16], carryout15); - single_bit_adder adder2 (sum[17], carryout17, a[17], b[17], carryout16); - single_bit_adder adder3 (sum[18], carryout18, a[18], b[18], carryout17); - single_bit_adder adder1 (sum[19], carryout19, a[19], b[19], carryout18); - - single_bit_adder adder2 (sum[20], carryout20, a[20], b[20], carryout19); - single_bit_adder adder3 (sum[21], carryout21, a[21], b[21], carryout20); - single_bit_adder adder1 (sum[22], carryout22, a[22], b[22], carryout21); - single_bit_adder adder2 (sum[23], carryout23, a[23], b[23], carryout22); - - single_bit_adder adder3 (sum[24], carryout24, a[24], b[24], carryout23); - single_bit_adder adder1 (sum[25], carryout25, a[25], b[25], carryout24); - single_bit_adder adder2 (sum[26], carryout26, a[26], b[26], carryout25); - single_bit_adder adder3 (sum[27], carryout27, a[27], b[27], carryout26); - - single_bit_adder adder1 (sum[28], carryout28, a[28], b[28], carryout27); - single_bit_adder adder2 (sum[29], carryout29, a[29], b[29], carryout28); - single_bit_adder adder3 (sum[30], carryout30, a[30], b[30], carryout29); - single_bit_adder adder1 (sum[31], carryout, a[31], b[31], carryout30); + single_bit_adder adder0 (sum[0], carryout0, A[0], B[0], 0); + single_bit_adder adder1 (sum[1], carryout1, A[1], B[1], carryout0); + single_bit_adder adder2 (sum[2], carryout2, A[2], B[2], carryout1); + single_bit_adder adder3 (sum[3], carryout3, A[3], B[3], carryout2); + + single_bit_adder adder1 (sum[4], carryout4, A[4], B[4], carryout3); + single_bit_adder adder2 (sum[5], carryout5, A[5], B[5], carryout4); + single_bit_adder adder3 (sum[6], carryout6, A[6], B[6], carryout5); + single_bit_adder adder1 (sum[7], carryout7, A[7], B[7], carryout6); + + single_bit_adder adder2 (sum[8], carryout8, A[8], B[8], carryout7); + single_bit_adder adder3 (sum[9], carryout9, A[9], B[9], carryout8); + single_bit_adder adder1 (sum[10], carryout10, A[10], B[10], carryout9); + single_bit_adder adder2 (sum[11], carryout11, A[11], B[11], carryout10); + single_bit_adder adder3 (sum[12], carryout12, A[12], B[12], carryout11); + single_bit_adder adder1 (sum[13], carryout13, A[13], B[13], carryout12); + single_bit_adder adder2 (sum[14], carryout14, A[14], B[14], carryout13); + single_bit_adder adder3 (sum[15], carryout15, A[15], B[15], carryout14); + + single_bit_adder adder1 (sum[16], carryout16, A[16], B[16], carryout15); + single_bit_adder adder2 (sum[17], carryout17, A[17], B[17], carryout16); + single_bit_adder adder3 (sum[18], carryout18, A[18], B[18], carryout17); + single_bit_adder adder1 (sum[19], carryout19, A[19], B[19], carryout18); + + single_bit_adder adder2 (sum[20], carryout20, A[20], B[20], carryout19); + single_bit_adder adder3 (sum[21], carryout21, A[21], B[21], carryout20); + single_bit_adder adder1 (sum[22], carryout22, A[22], B[22], carryout21); + single_bit_adder adder2 (sum[23], carryout23, A[23], B[23], carryout22); + + single_bit_adder adder3 (sum[24], carryout24, A[24], B[24], carryout23); + single_bit_adder adder1 (sum[25], carryout25, A[25], B[25], carryout24); + single_bit_adder adder2 (sum[26], carryout26, A[26], B[26], carryout25); + single_bit_adder adder3 (sum[27], carryout27, A[27], B[27], carryout26); + + single_bit_adder adder1 (sum[28], carryout28, A[28], B[28], carryout27); + single_bit_adder adder2 (sum[29], carryout29, A[29], B[29], carryout28); + single_bit_adder adder3 (sum[30], carryout30, A[30], B[30], carryout29); + single_bit_adder adder1 (sum[31], carryout, A[31], B[31], carryout30); + + xor getoverflow(overflow, carryout30, carryout); + nor getzero(zero, 31'b00000000000000000000000000000000, sum) endmodule -module multi_bit_subtracter(result, carryout, A, B, carryin) +module multi_bit_subtracter(result, carryout, overflow, zero, A, B) output result[31:0]; output carryout; + output overflow; + output zero; input A[31:0]; - input B{31:0]; - input carryin; + input B[31:0]; - wire carryout, result; + wire carryout, overflow, zero, result; wire A,B; not notA(nA,A); not notB(nB,B); - multi_bit_adder subtract1(result,carryout,nA,nB,carryin) + multi_bit_adder subtract1(result, carryout, overflow, zero, nA, nB) endmodule -module single_bit_adder(result, carryout, A, B, carryin); +module single_bit_adder(result, carryout, overflow, A, B, ; output result; output carryout; - input A; - input B; - input carryin; + output overflow; + output zero + input [31:0] A; + input [31:0] B; + wire carryout, result; wire A,B; From 6ff0a0805548dbb1fee8b11c041f51be1bb23a78 Mon Sep 17 00:00:00 2001 From: Bryan Werth Date: Wed, 11 Oct 2017 22:02:51 -0400 Subject: [PATCH 13/28] Finished the test bench --- alu.t.v | 107 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 107 insertions(+) create mode 100644 alu.t.v diff --git a/alu.t.v b/alu.t.v new file mode 100644 index 0000000..120b89c --- /dev/null +++ b/alu.t.v @@ -0,0 +1,107 @@ +`include "alu.v" + +module testALU (); + reg [31:0] operandA, operandB; + reg [2:0] command; + reg [9:0] numBroken = 0; + wire [31:0] result; + wire carryout, ofl, zero; + + ALU testALU(.result (result), .carryout (carryout), .ofl (ofl), .zero (zero), .operandA (operandA), .operandB (operandB), .command (command)); + + task checkTestCase; + input expectedResult, expectedCarryout, expectedOfl, expectedZero; + + begin + $display("Testing command %b, operandA %b, and operandB %b", command, operandA, operandB); + if (result == expectedResult) begin + $display("Test Passed, result is %b, carryout is %b, ofl is %b, and zero is %b", result, carryout, ofl, zero); + end else begin + numBroken = numBroken + 1; + $display("ERROR: Expected %b for result, %b for carryout, %b for ofl, and %b for zero, but actual output was %b, actual carryout was %b, actual ofl was %b, and actual zero is %b", expectedResult, expectedCarryout, expectedOfl, expectedZero, result, carryout, ofl, zero); + end + end + endtask + + initial begin + + //Add + command = 0; operandA = 0; operandB = 0; + checkTestCase(0, 0, 0, 1); + command = 0; operandA = 32'b11111111111111111111111111111111; operandB = 32'b11111111111111111111111111111111; + checkTestCase(32'b11111111111111111111111111111110, 1, 0, 0); + command = 0; operandA = 32'b10000000000000000000000000000001; operandB = 32'b01111111111111111111111111111111; + checkTestCase(0, 1, 0, 1); + command = 0; operandA = 32'b10000000000000000000000000000000; operandB = 32'b10000000000000000000000000000000; + checkTestCase(0, 1, 1, 1); + command = 0; operandA = 32'b11010101010101010101011010101010; operandB = 32'b00000001111111111111111101101010; + checkTestCase(32'b11010111010101010101011000010100, 0, 0, 0); + + //Sub + command = 1; operandA = 0; operandB = 0; + checkTestCase(0, 0, 0, 1); + command = 1; operandA = 32'b11111111111111111111111111111111; operandB = 32'b00000000000000000000000000000001; + checkTestCase(32'b11111111111111111111111111111110, 1, 0, 0); + command = 1; operandA = 32'b10000000000000000000000000000001; operandB = 32'b10000000000000000000000000000001; + checkTestCase(0, 1, 0, 1); + command = 1; operandA = 32'b10000000000000000000000000000000; operandB = 32'b10000000000000000000000000000000; + checkTestCase(0, 1, 1, 1); + command = 1; operandA = 32'b11010101010101010101011010101010; operandB = 32'b11111110000000000000000010010101; + checkTestCase(32'b11010111010101010101011000010100, 0, 0, 0); + + //XOR + command = 2; operandA = 32'b11111111111111111111111111111111; operandB = 32'b00000000000000000000000000000000; + checkTestCase(32'b11111111111111111111111111111111, 0, 0, 0); + command = 2; operandA = 32'b11111111111111111111111111111111; operandB = 32'b11111111111111111111111111111111; + checkTestCase(32'b00000000000000000000000000000000, 0, 0, 1); + command = 2; operandA = 32'b00101010101010101010111010111101; operandB = 32'b00001010101010110101010010110101; + checkTestCase(32'b00100000000000011111101000001000, 0, 0, 0); + + //SLT + command = 3; operandA = 32'b11111111111111111111111111111111; operandB = 32'b00000000000000000000000000000000; + checkTestCase(32'b00000000000000000000000000000000, 0, 0, 1); + command = 3; operandA = 32'b11111111111111111111111111111111; operandB = 32'b11111111111111111111111111111111; + checkTestCase(32'b00000000000000000000000000000000, 0, 0, 1); + command = 3; operandA = 32'b00000000000000000000000000000000; operandB = 32'b11111111111111111111111111111111; + checkTestCase(32'b11111111111111111111111111111111, 0, 0, 0); + + //AND + command = 4; operandA = 32'b11111111111111111111111111111111; operandB = 32'b00000000000000000000000000000000; + checkTestCase(32'b00000000000000000000000000000000, 0, 0, 1); + command = 4; operandA = 32'b11111111111111111111111111111111; operandB = 32'b11111111111111111111111111111111; + checkTestCase(32'b11111111111111111111111111111111, 0, 0, 0); + command = 4; operandA = 32'b00000000000000111111111111111111; operandB = 32'b01000100000101011101110111011011; + checkTestCase(32'b00000000000000011101110111011011, 0, 0, 0); + + //NAND + command = 5; operandA = 32'b11111111111111111111111111111111; operandB = 32'b00000000000000000000000000000000; + checkTestCase(32'b11111111111111111111111111111111, 0, 0, 0); + command = 5; operandA = 32'b11111111111111111111111111111111; operandB = 32'b11111111111111111111111111111111; + checkTestCase(32'b00000000000000000000000000000000, 0, 0, 1); + command = 5; operandA = 32'b00000000000000111111111111111111; operandB = 32'b01000100000101011101110111011011; + checkTestCase(32'b11111111111111100010001000100100, 0, 0, 0); + + //NOR + command = 7; operandA = 32'b11111111111111111111111111111111; operandB = 32'b00000000000000000000000000000000; + checkTestCase(32'b00000000000000000000000000000000, 0, 0, 1); + command = 7; operandA = 32'b00000000000000000000000000000000; operandB = 32'b00000000000000000000000000000000; + checkTestCase(32'b11111111111111111111111111111111, 0, 0, 0); + command = 7; operandA = 32'b00000000000000111111111111111111; operandB = 32'b01000100000101011101110111011011; + checkTestCase(32'b10111011111010000000000000000000, 0, 0, 0); + + //OR + command = 7; operandA = 32'b11111111111111111111111111111111; operandB = 32'b00000000000000000000000000000000; + checkTestCase(32'b11111111111111111111111111111111, 0, 0, 0); + command = 7; operandA = 32'b00000000000000000000000000000000; operandB = 32'b00000000000000000000000000000000; + checkTestCase(32'b00000000000000000000000000000000, 0, 0, 1); + command = 7; operandA = 32'b00000000000000111111111111111111; operandB = 32'b01000100000101011101110111011011; + checkTestCase(32'b01000100000101111111111111111111, 0, 0, 0); + + $display("%d test cases failed", numBroken); + + end +endmodule + + + + \ No newline at end of file From 155dfbc49634b51e3a7f2997e426aa867f862647 Mon Sep 17 00:00:00 2001 From: Wilson Tang Date: Wed, 11 Oct 2017 22:31:43 -0400 Subject: [PATCH 14/28] Updated Lab1 w/many errors --- alu.v | 139 ++++++++++++++++++++++++++++------------------------------ 1 file changed, 68 insertions(+), 71 deletions(-) diff --git a/alu.v b/alu.v index 7ab1d9e..60c731e 100644 --- a/alu.v +++ b/alu.v @@ -10,21 +10,22 @@ module ALU(result, carryout, overflow, zero, operandA, operandB, command); input [31:0] operandB; input [2:0] command; - reg result; + reg [31:0] result; wire carryout = 0; wire overflow = 0; wire zero = 0; wire operandA, operandB, carryin, addedResult, subResult, xorResult, sltResult, andResult, nandResult, norResult, orResult; - multi_bit_adder adder(addedResult, carryout, overflow, zero, operandA, operandB); - multi_bit_sub subtracter(subResult, carryout, overflow, zero, operantA, operandB) - multi_bit_slt slt(sltResult,A,B) + multi_bit_adder adder(addedResult, carryout, overflow, operandA, operandB); + multi_bit_subtracter subtracter(subResult, carryout, overflow, operandA, operandB); + multi_bit_SLT slt(sltResult,operandA,operandB); xor xorgate(xorResult, operandA, operandB); and andgate(andResult, operandA, operandB); nand nandgate(nandResult, operandA, operandB); nor norgate(norResult, operandA, operandB); or orgate(orResult, operandA, operandB); - + and zeros(zero, !(0||result[0]), !(0||result[1]) ,!(0||result[2]) ,!(0||result[3]) ,!(0||result[4]) , !(0||result[5]) ,!(0||result[6]) ,!(0||result[7]) ,!(0||result[8]) ,!(0||result[9]) ,!(0||result[10]) , !(0||result[11]) ,!(0||result[12]) ,!(0||result[13]) ,!(0||result[14]) ,!(0||result[15]) ,!(0||result[16]), !(0||result[17]) ,!(0||result[18]) ,!(0||result[19]) ,!(0||result[20]) ,!(0||result[21]) ,!(0||result[22]), !(0||result[23]) ,!(0||result[24]) ,!(0||result[25]) ,!(0||result[26]) ,!(0||result[27]) ,!(0||result[28]) , !(0||result[29]) ,!(0||result[30]) ,!(0||result[31]) ); + always @ (command) begin case(command) 3'b000: result = addedResult; @@ -46,30 +47,27 @@ endmodule //If A = B , return 0 module multi_bit_SLT(sltresult,A,B); + + output sltresult; + input [31:0] A; + input [31:0] B; + integer i; + + reg sltresult = 0; initial begin - for () - if ( single_bit_SLT(A[n],B[n]) ) + for (i = 0 ; i < 31; i = i+1) begin - elif + //If A[n] Date: Thu, 12 Oct 2017 03:49:51 -0400 Subject: [PATCH 15/28] Down to three errors --- alu.v | 53 +++++++++++++++++++++++++++-------------------------- 1 file changed, 27 insertions(+), 26 deletions(-) diff --git a/alu.v b/alu.v index 60c731e..f2170f6 100644 --- a/alu.v +++ b/alu.v @@ -1,5 +1,3 @@ - - module ALU(result, carryout, overflow, zero, operandA, operandB, command); output [31:0] result; @@ -14,28 +12,28 @@ module ALU(result, carryout, overflow, zero, operandA, operandB, command); wire carryout = 0; wire overflow = 0; wire zero = 0; - wire operandA, operandB, carryin, addedResult, subResult, xorResult, sltResult, andResult, nandResult, norResult, orResult; + wire [31:0] carryin, addedResult, subResult, xorResult, sltResult, andResult, nandResult, norResult, orResult; multi_bit_adder adder(addedResult, carryout, overflow, operandA, operandB); multi_bit_subtracter subtracter(subResult, carryout, overflow, operandA, operandB); multi_bit_SLT slt(sltResult,operandA,operandB); - xor xorgate(xorResult, operandA, operandB); - and andgate(andResult, operandA, operandB); - nand nandgate(nandResult, operandA, operandB); - nor norgate(norResult, operandA, operandB); - or orgate(orResult, operandA, operandB); - and zeros(zero, !(0||result[0]), !(0||result[1]) ,!(0||result[2]) ,!(0||result[3]) ,!(0||result[4]) , !(0||result[5]) ,!(0||result[6]) ,!(0||result[7]) ,!(0||result[8]) ,!(0||result[9]) ,!(0||result[10]) , !(0||result[11]) ,!(0||result[12]) ,!(0||result[13]) ,!(0||result[14]) ,!(0||result[15]) ,!(0||result[16]), !(0||result[17]) ,!(0||result[18]) ,!(0||result[19]) ,!(0||result[20]) ,!(0||result[21]) ,!(0||result[22]), !(0||result[23]) ,!(0||result[24]) ,!(0||result[25]) ,!(0||result[26]) ,!(0||result[27]) ,!(0||result[28]) , !(0||result[29]) ,!(0||result[30]) ,!(0||result[31]) ); + //xor xorgate(xorResult, operandA, operandB); + //and andgate(andResult, operandA, operandB); + //nand nandgate(nandResult, operandA, operandB); + //nor norgate(norResult, operandA, operandB); + //or orgate(orResult, operandA, operandB); + and zeros(zero, !(0||result[0]), !(0||result[1]) ,!(0||result[2]) ,!(0||result[3]) ,!(0||result[4]), !(0||result[5]) ,!(0||result[6]) ,!(0||result[7]) ,!(0||result[8]) ,!(0||result[9]) ,!(0||result[10]) , !(0||result[11]) ,!(0||result[12]) ,!(0||result[13]) ,!(0||result[14]) ,!(0||result[15]) ,!(0||result[16]), !(0||result[17]) ,!(0||result[18]) ,!(0||result[19]) ,!(0||result[20]) ,!(0||result[21]) ,!(0||result[22]), !(0||result[23]) ,!(0||result[24]) ,!(0||result[25]) ,!(0||result[26]) ,!(0||result[27]) ,!(0||result[28]) , !(0||result[29]) ,!(0||result[30]) ,!(0||result[31]) ); always @ (command) begin case(command) 3'b000: result = addedResult; 3'b001: result = subResult; - 3'b010: result = xorResult; + 3'b010: result = operandA ^ operandB; 3'b011: result = sltResult; - 3'b100: result = andResult; - 3'b101: result = nandResult; - 3'b110: result = norResult; - 3'b111: result = orResult; + 3'b100: result = operandA && operandB; + 3'b101: result = !(operandA && operandB); + 3'b110: result = !(operandA || operandB); + 3'b111: result = operandA || operandB; endcase end endmodule @@ -55,21 +53,20 @@ module multi_bit_SLT(sltresult,A,B); reg sltresult = 0; initial begin - - for (i = 0 ; i < 31; i = i+1) begin - + for (i = 31 ; i >= 0; i = i-1) begin //If A[n] B[i])) begin + sltresult = 0; end - end end endmodule -module multi_bit_adder(result, carryout, overflow, A, B); +module multi_bit_adder(sum, carryout, overflow, A, B); - output [31:0] result; + output [31:0] sum; output carryout; output overflow; input [31:0] A; @@ -78,6 +75,10 @@ module multi_bit_adder(result, carryout, overflow, A, B); wire [31:0] result; wire carryout, overflow; wire [31:0] A,B; + wire carryout0,carryout1,carryout2,carryout3,carryout4,carryout5,carryout6,carryout7,carryout8,carryout9; + wire carryout10,carryout11,carryout12,carryout13,carryout14,carryout15,carryout16,carryout17,carryout18; + wire carryout19,carryout20,carryout21,carryout22,carryout23,carryout24,carryout25,carryout26,carryout27; + wire carryout28,carryout29,carryout30; single_bit_adder adder0 (sum[0], carryout0, A[0], B[0], 0); single_bit_adder adder1 (sum[1], carryout1, A[1], B[1], carryout0); @@ -132,23 +133,23 @@ module multi_bit_subtracter(result, carryout, overflow, A, B); wire [31:0] result; wire carryout, overflow; - wire [31:0] A,B; + wire [31:0] A; + reg [31:0] B; wire [31:0] nB; - not notB(nB,B); + nB = !B; multi_bit_adder subtract1(result, carryout, overflow, A, nB); endmodule -module single_bit_adder(result, carryout, overflow, A, B) ; +module single_bit_adder(result, carryout, A, B, carryin) ; output result; output carryout; - output overflow; input A; input B; - + input carryin; wire carryout, result; wire A,B; From 8c10d6c221a93fdda1569c58738d35316ff0273c Mon Sep 17 00:00:00 2001 From: Wilson Tang Date: Thu, 12 Oct 2017 19:04:17 -0400 Subject: [PATCH 16/28] updated alu.v + test bench --- alu.t.v | 2 +- alu.v | 22 +++++++++++----------- 2 files changed, 12 insertions(+), 12 deletions(-) diff --git a/alu.t.v b/alu.t.v index 120b89c..7216ae8 100644 --- a/alu.t.v +++ b/alu.t.v @@ -7,7 +7,7 @@ module testALU (); wire [31:0] result; wire carryout, ofl, zero; - ALU testALU(.result (result), .carryout (carryout), .ofl (ofl), .zero (zero), .operandA (operandA), .operandB (operandB), .command (command)); + ALU testALU(.result (result), .carryout (carryout), .overflow (ofl), .zero (zero), .operandA (operandA), .operandB (operandB), .command (command)); task checkTestCase; input expectedResult, expectedCarryout, expectedOfl, expectedZero; diff --git a/alu.v b/alu.v index f2170f6..b0d0a76 100644 --- a/alu.v +++ b/alu.v @@ -12,17 +12,15 @@ module ALU(result, carryout, overflow, zero, operandA, operandB, command); wire carryout = 0; wire overflow = 0; wire zero = 0; - wire [31:0] carryin, addedResult, subResult, xorResult, sltResult, andResult, nandResult, norResult, orResult; + wire [31:0] carryin, addedResult, subResult, xorResult, andResult, nandResult, norResult, orResult; + wire sltResult; multi_bit_adder adder(addedResult, carryout, overflow, operandA, operandB); multi_bit_subtracter subtracter(subResult, carryout, overflow, operandA, operandB); multi_bit_SLT slt(sltResult,operandA,operandB); - //xor xorgate(xorResult, operandA, operandB); - //and andgate(andResult, operandA, operandB); - //nand nandgate(nandResult, operandA, operandB); - //nor norgate(norResult, operandA, operandB); - //or orgate(orResult, operandA, operandB); - and zeros(zero, !(0||result[0]), !(0||result[1]) ,!(0||result[2]) ,!(0||result[3]) ,!(0||result[4]), !(0||result[5]) ,!(0||result[6]) ,!(0||result[7]) ,!(0||result[8]) ,!(0||result[9]) ,!(0||result[10]) , !(0||result[11]) ,!(0||result[12]) ,!(0||result[13]) ,!(0||result[14]) ,!(0||result[15]) ,!(0||result[16]), !(0||result[17]) ,!(0||result[18]) ,!(0||result[19]) ,!(0||result[20]) ,!(0||result[21]) ,!(0||result[22]), !(0||result[23]) ,!(0||result[24]) ,!(0||result[25]) ,!(0||result[26]) ,!(0||result[27]) ,!(0||result[28]) , !(0||result[29]) ,!(0||result[30]) ,!(0||result[31]) ); + + //Check for zeros + and zeros(zero, !(0||result[0]), !(0||result[1]) ,!(0||result[2]) ,!(0||result[3]) ,!(0||result[4]), !(0||result[5]) ,!(0||result[6]) ,!(0||result[7]) ,!(0||result[8]) ,!(0||result[9]) ,!(0||result[10]) , !(0||result[11]) ,!(0||result[12]) ,!(0||result[13]) ,!(0||result[14]) ,!(0||result[15]) ,!(0||result[16]), !(0||result[17]) ,!(0||result[18]) ,!(0||result[19]) ,!(0||result[20]) ,!(0||result[21]) ,!(0||result[22]), !(0||result[23]) ,!(0||result[24]) ,!(0||result[25]) ,!(0||result[26]) ,!(0||result[27]) ,!(0||result[28]) , !(0||result[29]) ,!(0||result[30]) ,!(0||result[31]) ); always @ (command) begin case(command) @@ -80,7 +78,7 @@ module multi_bit_adder(sum, carryout, overflow, A, B); wire carryout19,carryout20,carryout21,carryout22,carryout23,carryout24,carryout25,carryout26,carryout27; wire carryout28,carryout29,carryout30; - single_bit_adder adder0 (sum[0], carryout0, A[0], B[0], 0); + single_bit_adder adder0 (sum[0], carryout0, A[0], B[0], 1'b0); single_bit_adder adder1 (sum[1], carryout1, A[1], B[1], carryout0); single_bit_adder adder2 (sum[2], carryout2, A[2], B[2], carryout1); single_bit_adder adder3 (sum[3], carryout3, A[3], B[3], carryout2); @@ -134,10 +132,12 @@ module multi_bit_subtracter(result, carryout, overflow, A, B); wire [31:0] result; wire carryout, overflow; wire [31:0] A; - reg [31:0] B; + wire [31:0] B; wire [31:0] nB; - - nB = !B; + + //initial nB[31:0] = ~B[31:0]; + //invert second operand B for subtraction + assign nB = !B[31] && !B[30] && !B[29] && !B[28] && !B[27]&& !B[26] && !B[25] && !B[24] && !B[23] && !B[22] && !B[21]&& !B[20] && !B[19] && !B[18] && !B[17] && !B[16] && !B[15] && !B[14] && !B[13] && !B[12] && !B[11] && !B[10] && !B[9] && !B[8] && !B[7] && !B[6] && !B[5] && !B[4] && !B[3] && !B[2] && !B[1] && !B[0] ; multi_bit_adder subtract1(result, carryout, overflow, A, nB); From 6158866bab3753f3554ca4d97ca8bddbf2d5b4b5 Mon Sep 17 00:00:00 2001 From: Bryan Werth Date: Thu, 12 Oct 2017 19:33:00 -0400 Subject: [PATCH 17/28] Test Bench Worked --- alu.t.v | 61 +++++++++++++++++++++++++++++---------------------------- alu.v | 4 ++-- 2 files changed, 33 insertions(+), 32 deletions(-) diff --git a/alu.t.v b/alu.t.v index 7216ae8..bf5e5cf 100644 --- a/alu.t.v +++ b/alu.t.v @@ -10,7 +10,8 @@ module testALU (); ALU testALU(.result (result), .carryout (carryout), .overflow (ofl), .zero (zero), .operandA (operandA), .operandB (operandB), .command (command)); task checkTestCase; - input expectedResult, expectedCarryout, expectedOfl, expectedZero; + input [31:0] expectedResult; + input expectedCarryout, expectedOfl, expectedZero; begin $display("Testing command %b, operandA %b, and operandB %b", command, operandA, operandB); @@ -26,75 +27,75 @@ module testALU (); initial begin //Add - command = 0; operandA = 0; operandB = 0; + command = 0; operandA = 0; operandB = 0; #50 checkTestCase(0, 0, 0, 1); - command = 0; operandA = 32'b11111111111111111111111111111111; operandB = 32'b11111111111111111111111111111111; + command = 0; operandA = 32'b11111111111111111111111111111111; operandB = 32'b11111111111111111111111111111111; #50 checkTestCase(32'b11111111111111111111111111111110, 1, 0, 0); - command = 0; operandA = 32'b10000000000000000000000000000001; operandB = 32'b01111111111111111111111111111111; + command = 0; operandA = 32'b10000000000000000000000000000001; operandB = 32'b01111111111111111111111111111111; #50 checkTestCase(0, 1, 0, 1); - command = 0; operandA = 32'b10000000000000000000000000000000; operandB = 32'b10000000000000000000000000000000; + command = 0; operandA = 32'b10000000000000000000000000000000; operandB = 32'b10000000000000000000000000000000; #50 checkTestCase(0, 1, 1, 1); - command = 0; operandA = 32'b11010101010101010101011010101010; operandB = 32'b00000001111111111111111101101010; + command = 0; operandA = 32'b11010101010101010101011010101010; operandB = 32'b00000001111111111111111101101010; #50 checkTestCase(32'b11010111010101010101011000010100, 0, 0, 0); //Sub - command = 1; operandA = 0; operandB = 0; + command = 1; operandA = 0; operandB = 0; #50 checkTestCase(0, 0, 0, 1); - command = 1; operandA = 32'b11111111111111111111111111111111; operandB = 32'b00000000000000000000000000000001; + command = 1; operandA = 32'b11111111111111111111111111111111; operandB = 32'b00000000000000000000000000000001; #50 checkTestCase(32'b11111111111111111111111111111110, 1, 0, 0); - command = 1; operandA = 32'b10000000000000000000000000000001; operandB = 32'b10000000000000000000000000000001; + command = 1; operandA = 32'b10000000000000000000000000000001; operandB = 32'b10000000000000000000000000000001; #50 checkTestCase(0, 1, 0, 1); - command = 1; operandA = 32'b10000000000000000000000000000000; operandB = 32'b10000000000000000000000000000000; + command = 1; operandA = 32'b10000000000000000000000000000000; operandB = 32'b10000000000000000000000000000000; #50 checkTestCase(0, 1, 1, 1); - command = 1; operandA = 32'b11010101010101010101011010101010; operandB = 32'b11111110000000000000000010010101; + command = 1; operandA = 32'b11010101010101010101011010101010; operandB = 32'b11111110000000000000000010010101; #50 checkTestCase(32'b11010111010101010101011000010100, 0, 0, 0); //XOR - command = 2; operandA = 32'b11111111111111111111111111111111; operandB = 32'b00000000000000000000000000000000; + command = 2; operandA = 32'b11111111111111111111111111111111; operandB = 32'b00000000000000000000000000000000; #50 checkTestCase(32'b11111111111111111111111111111111, 0, 0, 0); - command = 2; operandA = 32'b11111111111111111111111111111111; operandB = 32'b11111111111111111111111111111111; + command = 2; operandA = 32'b11111111111111111111111111111111; operandB = 32'b11111111111111111111111111111111; #50 checkTestCase(32'b00000000000000000000000000000000, 0, 0, 1); - command = 2; operandA = 32'b00101010101010101010111010111101; operandB = 32'b00001010101010110101010010110101; + command = 2; operandA = 32'b00101010101010101010111010111101; operandB = 32'b00001010101010110101010010110101; #50 checkTestCase(32'b00100000000000011111101000001000, 0, 0, 0); //SLT - command = 3; operandA = 32'b11111111111111111111111111111111; operandB = 32'b00000000000000000000000000000000; + command = 3; operandA = 32'b11111111111111111111111111111111; operandB = 32'b00000000000000000000000000000000; #50 checkTestCase(32'b00000000000000000000000000000000, 0, 0, 1); - command = 3; operandA = 32'b11111111111111111111111111111111; operandB = 32'b11111111111111111111111111111111; + command = 3; operandA = 32'b11111111111111111111111111111111; operandB = 32'b11111111111111111111111111111111; #50 checkTestCase(32'b00000000000000000000000000000000, 0, 0, 1); - command = 3; operandA = 32'b00000000000000000000000000000000; operandB = 32'b11111111111111111111111111111111; + command = 3; operandA = 32'b00000000000000000000000000000000; operandB = 32'b11111111111111111111111111111111; #50 checkTestCase(32'b11111111111111111111111111111111, 0, 0, 0); //AND - command = 4; operandA = 32'b11111111111111111111111111111111; operandB = 32'b00000000000000000000000000000000; + command = 4; operandA = 32'b11111111111111111111111111111111; operandB = 32'b00000000000000000000000000000000; #50 checkTestCase(32'b00000000000000000000000000000000, 0, 0, 1); - command = 4; operandA = 32'b11111111111111111111111111111111; operandB = 32'b11111111111111111111111111111111; + command = 4; operandA = 32'b11111111111111111111111111111111; operandB = 32'b11111111111111111111111111111111; #50 checkTestCase(32'b11111111111111111111111111111111, 0, 0, 0); - command = 4; operandA = 32'b00000000000000111111111111111111; operandB = 32'b01000100000101011101110111011011; + command = 4; operandA = 32'b00000000000000111111111111111111; operandB = 32'b01000100000101011101110111011011; #50 checkTestCase(32'b00000000000000011101110111011011, 0, 0, 0); //NAND - command = 5; operandA = 32'b11111111111111111111111111111111; operandB = 32'b00000000000000000000000000000000; + command = 5; operandA = 32'b11111111111111111111111111111111; operandB = 32'b00000000000000000000000000000000; #50 checkTestCase(32'b11111111111111111111111111111111, 0, 0, 0); - command = 5; operandA = 32'b11111111111111111111111111111111; operandB = 32'b11111111111111111111111111111111; + command = 5; operandA = 32'b11111111111111111111111111111111; operandB = 32'b11111111111111111111111111111111; #50 checkTestCase(32'b00000000000000000000000000000000, 0, 0, 1); - command = 5; operandA = 32'b00000000000000111111111111111111; operandB = 32'b01000100000101011101110111011011; + command = 5; operandA = 32'b00000000000000111111111111111111; operandB = 32'b01000100000101011101110111011011; #50 checkTestCase(32'b11111111111111100010001000100100, 0, 0, 0); //NOR - command = 7; operandA = 32'b11111111111111111111111111111111; operandB = 32'b00000000000000000000000000000000; + command = 7; operandA = 32'b11111111111111111111111111111111; operandB = 32'b00000000000000000000000000000000; #50 checkTestCase(32'b00000000000000000000000000000000, 0, 0, 1); - command = 7; operandA = 32'b00000000000000000000000000000000; operandB = 32'b00000000000000000000000000000000; + command = 7; operandA = 32'b00000000000000000000000000000000; operandB = 32'b00000000000000000000000000000000; #50 checkTestCase(32'b11111111111111111111111111111111, 0, 0, 0); - command = 7; operandA = 32'b00000000000000111111111111111111; operandB = 32'b01000100000101011101110111011011; + command = 7; operandA = 32'b00000000000000111111111111111111; operandB = 32'b01000100000101011101110111011011; #50 checkTestCase(32'b10111011111010000000000000000000, 0, 0, 0); //OR - command = 7; operandA = 32'b11111111111111111111111111111111; operandB = 32'b00000000000000000000000000000000; - checkTestCase(32'b11111111111111111111111111111111, 0, 0, 0); - command = 7; operandA = 32'b00000000000000000000000000000000; operandB = 32'b00000000000000000000000000000000; + command = 7; operandA = 32'b11111111111111111111111111111111; operandB = 32'b00000000000000000000000000000000; #50 + checkTestCase(32'b11111111111111111111111111111111, 0, 0, 0); + command = 7; operandA = 32'b00000000000000000000000000000000; operandB = 32'b00000000000000000000000000000000; #50 checkTestCase(32'b00000000000000000000000000000000, 0, 0, 1); - command = 7; operandA = 32'b00000000000000111111111111111111; operandB = 32'b01000100000101011101110111011011; + command = 7; operandA = 32'b00000000000000111111111111111111; operandB = 32'b01000100000101011101110111011011; #50 checkTestCase(32'b01000100000101111111111111111111, 0, 0, 0); $display("%d test cases failed", numBroken); diff --git a/alu.v b/alu.v index b0d0a76..380d301 100644 --- a/alu.v +++ b/alu.v @@ -20,9 +20,9 @@ module ALU(result, carryout, overflow, zero, operandA, operandB, command); multi_bit_SLT slt(sltResult,operandA,operandB); //Check for zeros - and zeros(zero, !(0||result[0]), !(0||result[1]) ,!(0||result[2]) ,!(0||result[3]) ,!(0||result[4]), !(0||result[5]) ,!(0||result[6]) ,!(0||result[7]) ,!(0||result[8]) ,!(0||result[9]) ,!(0||result[10]) , !(0||result[11]) ,!(0||result[12]) ,!(0||result[13]) ,!(0||result[14]) ,!(0||result[15]) ,!(0||result[16]), !(0||result[17]) ,!(0||result[18]) ,!(0||result[19]) ,!(0||result[20]) ,!(0||result[21]) ,!(0||result[22]), !(0||result[23]) ,!(0||result[24]) ,!(0||result[25]) ,!(0||result[26]) ,!(0||result[27]) ,!(0||result[28]) , !(0||result[29]) ,!(0||result[30]) ,!(0||result[31]) ); + and zeros(zero, !(0||result[0]), !(0||result[1]) ,!(0||result[2]) ,!(0||result[3]) ,!(0||result[4]),!(0||result[5]) ,!(0||result[6]) ,!(0||result[7]) ,!(0||result[8]) ,!(0||result[9]) ,!(0||result[10]) , !(0||result[11]) ,!(0||result[12]) ,!(0||result[13]) ,!(0||result[14]) ,!(0||result[15]) ,!(0||result[16]), !(0||result[17]) ,!(0||result[18]) ,!(0||result[19]) ,!(0||result[20]) ,!(0||result[21]) ,!(0||result[22]), !(0||result[23]) ,!(0||result[24]) ,!(0||result[25]) ,!(0||result[26]) ,!(0||result[27]) ,!(0||result[28]) , !(0||result[29]) ,!(0||result[30]) ,!(0||result[31]) ); - always @ (command) begin + always @ (command || operandA || operandB) begin case(command) 3'b000: result = addedResult; 3'b001: result = subResult; From 848d47809eb20eb1d3e5c4cfb661bf7d1f4fd181 Mon Sep 17 00:00:00 2001 From: Bryan Werth Date: Thu, 12 Oct 2017 22:02:38 -0400 Subject: [PATCH 18/28] Changes were made --- alu.v | 65 ++++++++++++++++++++++++++++++++++++++++++++++++++--------- 1 file changed, 56 insertions(+), 9 deletions(-) diff --git a/alu.v b/alu.v index 380d301..af841fe 100644 --- a/alu.v +++ b/alu.v @@ -8,21 +8,21 @@ module ALU(result, carryout, overflow, zero, operandA, operandB, command); input [31:0] operandB; input [2:0] command; - reg [31:0] result; wire carryout = 0; wire overflow = 0; wire zero = 0; wire [31:0] carryin, addedResult, subResult, xorResult, andResult, nandResult, norResult, orResult; wire sltResult; - + reg [31:0] result; + + assign zero = !(1'b0||result[0]) && !(1'b0||result[1]) && !(1'b0||result[2]) && !(1'b0||result[3]) && !(1'b0||result[4]) && !(1'b0||result[5]) && !(1'b0||result[6]) && !(1'b0||result[7]) && !(1'b0||result[8]) && !(1'b0||result[9]) && !(1'b0||result[10]) && !(1'b0||result[11]) && !(1'b0||result[12]) && !(1'b0||result[13]) && !(1'b0||result[14]) && !(1'b0||result[15]) && !(1'b0||result[16]) && !(1'b0||result[17]) && !(1'b0||result[18]) && !(1'b0||result[19]) && !(1'b0||result[20]) && !(1'b0||result[21]) && !(1'b0||result[22]) && !(1'b0||result[23]) && !(1'b0||result[24]) && !(1'b0||result[25]) && !(1'b0||result[26]) && !(1'b0||result[27]) && !(1'b0||result[28]) && !(1'b0||result[29]) && !(1'b0||result[30]) && !(1'b0||result[31]); + multi_bit_adder adder(addedResult, carryout, overflow, operandA, operandB); multi_bit_subtracter subtracter(subResult, carryout, overflow, operandA, operandB); multi_bit_SLT slt(sltResult,operandA,operandB); + //output_mux result_mux(.result(result),.command(command),.operandA(operandA),.operandB(operandB),.addedResult(addedResult),.subResult(subResult),.sltResult(sltResult)); - //Check for zeros - and zeros(zero, !(0||result[0]), !(0||result[1]) ,!(0||result[2]) ,!(0||result[3]) ,!(0||result[4]),!(0||result[5]) ,!(0||result[6]) ,!(0||result[7]) ,!(0||result[8]) ,!(0||result[9]) ,!(0||result[10]) , !(0||result[11]) ,!(0||result[12]) ,!(0||result[13]) ,!(0||result[14]) ,!(0||result[15]) ,!(0||result[16]), !(0||result[17]) ,!(0||result[18]) ,!(0||result[19]) ,!(0||result[20]) ,!(0||result[21]) ,!(0||result[22]), !(0||result[23]) ,!(0||result[24]) ,!(0||result[25]) ,!(0||result[26]) ,!(0||result[27]) ,!(0||result[28]) , !(0||result[29]) ,!(0||result[30]) ,!(0||result[31]) ); - - always @ (command || operandA || operandB) begin + always @ (*) begin case(command) 3'b000: result = addedResult; 3'b001: result = subResult; @@ -41,7 +41,7 @@ endmodule //If A[n]>B[n] @ n then stop and return 0 //If A[n]=B[n] @ n continue until the end //If A = B , return 0 - + module multi_bit_SLT(sltresult,A,B); output sltresult; @@ -49,19 +49,66 @@ module multi_bit_SLT(sltresult,A,B); input [31:0] B; integer i; - reg sltresult = 0; + reg sltresult; initial begin for (i = 31 ; i >= 0; i = i-1) begin //If A[n] B[i])) begin + i = -1; + end else if ((A[i] && B[i]) || (A[i] && !B[i])) begin sltresult = 0; end end + i = 31; end endmodule +module multi_bit_and(andResult, operandA, operandB); + output [31:0] andResult; + input [31:0] operandA; + input [31:0] operandB; + + //wire [31:0] operandA, operandB; + wire and0,and1,and2,and3,and4,and5,and6,and7,and8,and9,and10,and11,and12,and13,and14,and15,and16,and17,and18,and19,and20,and21,and22,and23,and24,and25,and26,and27,and28,and29,and30,and31; + + assign and0 = operandA[0] && operandB[0]; + assign and1 = operandA[1] && operandB[1]; + assign and2 = operandA[2] && operandB[2]; + assign and3 = operandA[3] && operandB[3]; + assign and4 = operandA[4] && operandB[4]; + assign and5 = operandA[5] && operandB[5]; + assign and6 = operandA[6] && operandB[6]; + assign and7 = operandA[7] && operandB[7]; + assign and8 = operandA[8] && operandB[8]; + assign and9 = operandA[9] && operandB[9]; + assign and10 = operandA[10] && operandB[10]; + assign and11 = operandA[11] && operandB[11]; + assign and12 = operandA[12] && operandB[12]; + assign and13 = operandA[13] && operandB[13]; + assign and14 = operandA[14] && operandB[14]; + assign and15 = operandA[15] && operandB[15]; + assign and16 = operandA[16] && operandB[16]; + assign and17 = operandA[17] && operandB[17]; + assign and18 = operandA[18] && operandB[18]; + assign and19 = operandA[19] && operandB[19]; + assign and20 = operandA[20] && operandB[20]; + assign and21 = operandA[21] && operandB[21]; + assign and22 = operandA[22] && operandB[22]; + assign and23 = operandA[23] && operandB[23]; + assign and24 = operandA[24] && operandB[24]; + assign and25 = operandA[25] && operandB[25]; + assign and26 = operandA[26] && operandB[26]; + assign and27 = operandA[27] && operandB[27]; + assign and28 = operandA[28] && operandB[28]; + assign and29 = operandA[29] && operandB[29]; + assign and30 = operandA[30] && operandB[30]; + assign and31 = operandA[31] && operandB[31]; + + assign andResult = and31 && and30 && and29 && and31 && and30 && and29 && && and28 && and27 && and26 && and25 && and24 && and23 && and22 && and21 && and20 && and19 && and18 && and17 && and16 && and15 && and14 && and13 && and12 && and11 && and10 && and9 && and8 && and7 && and6 && and5 && and4 && and3 && and2 && and1 && and0; +endmodule + + module multi_bit_adder(sum, carryout, overflow, A, B); output [31:0] sum; From b9354fc3008b16fd68914c1f5f705a94fa7f59de Mon Sep 17 00:00:00 2001 From: Wilson Tang Date: Thu, 12 Oct 2017 22:04:51 -0400 Subject: [PATCH 19/28] merging alu.v --- alu.t.v | 6 +++--- alu.v | 67 ++++++++++++++++++++++++++++++++++++++++++++++++--------- 2 files changed, 60 insertions(+), 13 deletions(-) diff --git a/alu.t.v b/alu.t.v index bf5e5cf..e410022 100644 --- a/alu.t.v +++ b/alu.t.v @@ -83,11 +83,11 @@ module testALU (); checkTestCase(32'b11111111111111100010001000100100, 0, 0, 0); //NOR - command = 7; operandA = 32'b11111111111111111111111111111111; operandB = 32'b00000000000000000000000000000000; #50 + command = 6; operandA = 32'b11111111111111111111111111111111; operandB = 32'b00000000000000000000000000000000; #50 checkTestCase(32'b00000000000000000000000000000000, 0, 0, 1); - command = 7; operandA = 32'b00000000000000000000000000000000; operandB = 32'b00000000000000000000000000000000; #50 + command = 6; operandA = 32'b00000000000000000000000000000000; operandB = 32'b00000000000000000000000000000000; #50 checkTestCase(32'b11111111111111111111111111111111, 0, 0, 0); - command = 7; operandA = 32'b00000000000000111111111111111111; operandB = 32'b01000100000101011101110111011011; #50 + command = 6; operandA = 32'b00000000000000111111111111111111; operandB = 32'b01000100000101011101110111011011; #50 checkTestCase(32'b10111011111010000000000000000000, 0, 0, 0); //OR diff --git a/alu.v b/alu.v index 380d301..ce0efda 100644 --- a/alu.v +++ b/alu.v @@ -8,21 +8,21 @@ module ALU(result, carryout, overflow, zero, operandA, operandB, command); input [31:0] operandB; input [2:0] command; - reg [31:0] result; wire carryout = 0; wire overflow = 0; wire zero = 0; wire [31:0] carryin, addedResult, subResult, xorResult, andResult, nandResult, norResult, orResult; wire sltResult; - + reg [31:0] result; + + assign zero = !(1'b0||result[0]) && !(1'b0||result[1]) && !(1'b0||result[2]) && !(1'b0||result[3]) && !(1'b0||result[4]) && !(1'b0||result[5]) && !(1'b0||result[6]) && !(1'b0||result[7]) && !(1'b0||result[8]) && !(1'b0||result[9]) && !(1'b0||result[10]) && !(1'b0||result[11]) && !(1'b0||result[12]) && !(1'b0||result[13]) && !(1'b0||result[14]) && !(1'b0||result[15]) && !(1'b0||result[16]) && !(1'b0||result[17]) && !(1'b0||result[18]) && !(1'b0||result[19]) && !(1'b0||result[20]) && !(1'b0||result[21]) && !(1'b0||result[22]) && !(1'b0||result[23]) && !(1'b0||result[24]) && !(1'b0||result[25]) && !(1'b0||result[26]) && !(1'b0||result[27]) && !(1'b0||result[28]) && !(1'b0||result[29]) && !(1'b0||result[30]) && !(1'b0||result[31]); + multi_bit_adder adder(addedResult, carryout, overflow, operandA, operandB); multi_bit_subtracter subtracter(subResult, carryout, overflow, operandA, operandB); multi_bit_SLT slt(sltResult,operandA,operandB); + //output_mux result_mux(.result(result),.command(command),.operandA(operandA),.operandB(operandB),.addedResult(addedResult),.subResult(subResult),.sltResult(sltResult)); - //Check for zeros - and zeros(zero, !(0||result[0]), !(0||result[1]) ,!(0||result[2]) ,!(0||result[3]) ,!(0||result[4]),!(0||result[5]) ,!(0||result[6]) ,!(0||result[7]) ,!(0||result[8]) ,!(0||result[9]) ,!(0||result[10]) , !(0||result[11]) ,!(0||result[12]) ,!(0||result[13]) ,!(0||result[14]) ,!(0||result[15]) ,!(0||result[16]), !(0||result[17]) ,!(0||result[18]) ,!(0||result[19]) ,!(0||result[20]) ,!(0||result[21]) ,!(0||result[22]), !(0||result[23]) ,!(0||result[24]) ,!(0||result[25]) ,!(0||result[26]) ,!(0||result[27]) ,!(0||result[28]) , !(0||result[29]) ,!(0||result[30]) ,!(0||result[31]) ); - - always @ (command || operandA || operandB) begin + always @ (*) begin case(command) 3'b000: result = addedResult; 3'b001: result = subResult; @@ -41,7 +41,7 @@ endmodule //If A[n]>B[n] @ n then stop and return 0 //If A[n]=B[n] @ n continue until the end //If A = B , return 0 - + module multi_bit_SLT(sltresult,A,B); output sltresult; @@ -49,19 +49,66 @@ module multi_bit_SLT(sltresult,A,B); input [31:0] B; integer i; - reg sltresult = 0; + reg sltresult; initial begin for (i = 31 ; i >= 0; i = i-1) begin //If A[n] B[i])) begin + i = -1; + end else if ((A[i] && B[i]) || (A[i] && !B[i])) begin sltresult = 0; end end + i = 31; end endmodule +module multi_bit_and(andResult, operandA, operandB); + output [31:0] andResult; + input [31:0] operandA; + input [31:0] operandB; + + //wire [31:0] operandA, operandB; + wire and0,and1,and2,and3,and4,and5,and6,and7,and8,and9,and10,and11,and12,and13,and14,and15,and16,and17,and18,and19,and20,and21,and22,and23,and24,and25,and26,and27,and28,and29,and30,and31; + + assign and0 = operandA[0] && operandB[0]; + assign and1 = operandA[1] && operandB[1]; + assign and2 = operandA[2] && operandB[2]; + assign and3 = operandA[3] && operandB[3]; + assign and4 = operandA[4] && operandB[4]; + assign and5 = operandA[5] && operandB[5]; + assign and6 = operandA[6] && operandB[6]; + assign and7 = operandA[7] && operandB[7]; + assign and8 = operandA[8] && operandB[8]; + assign and9 = operandA[9] && operandB[9]; + assign and10 = operandA[10] && operandB[10]; + assign and11 = operandA[11] && operandB[11]; + assign and12 = operandA[12] && operandB[12]; + assign and13 = operandA[13] && operandB[13]; + assign and14 = operandA[14] && operandB[14]; + assign and15 = operandA[15] && operandB[15]; + assign and16 = operandA[16] && operandB[16]; + assign and17 = operandA[17] && operandB[17]; + assign and18 = operandA[18] && operandB[18]; + assign and19 = operandA[19] && operandB[19]; + assign and20 = operandA[20] && operandB[20]; + assign and21 = operandA[21] && operandB[21]; + assign and22 = operandA[22] && operandB[22]; + assign and23 = operandA[23] && operandB[23]; + assign and24 = operandA[24] && operandB[24]; + assign and25 = operandA[25] && operandB[25]; + assign and26 = operandA[26] && operandB[26]; + assign and27 = operandA[27] && operandB[27]; + assign and28 = operandA[28] && operandB[28]; + assign and29 = operandA[29] && operandB[29]; + assign and30 = operandA[30] && operandB[30]; + assign and31 = operandA[31] && operandB[31]; + + assign andResult = and31 && and30 && and29 && and31 && and30 && and29 && && and28 && and27 && and26 && and25 && and24 && and23 && and22 && and21 && and20 && and19 && and18 && and17 && and16 && and15 && and14 && and13 && and12 && and11 && and10 && and9 && and8 && and7 && and6 && and5 && and4 && and3 && and2 && and1 && and0; +endmodule + + module multi_bit_adder(sum, carryout, overflow, A, B); output [31:0] sum; @@ -157,4 +204,4 @@ module single_bit_adder(result, carryout, A, B, carryin) ; assign carryout = (A && B) || (((!A && B) || (A && !B)) && carryin); assign result = (((!A && B) || (A && !B)) && !carryin) || (!((!A && B) || (A && !B)) && carryin); -endmodule \ No newline at end of file +endmodule From 163e26f9ae92ed08e93bae6385a2d44f8201e1d6 Mon Sep 17 00:00:00 2001 From: Bryan Werth Date: Thu, 12 Oct 2017 23:14:51 -0400 Subject: [PATCH 20/28] Logic gates and zero finished --- alu_bryans_piece.v | 306 +++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 306 insertions(+) create mode 100644 alu_bryans_piece.v diff --git a/alu_bryans_piece.v b/alu_bryans_piece.v new file mode 100644 index 0000000..8be95cd --- /dev/null +++ b/alu_bryans_piece.v @@ -0,0 +1,306 @@ +module ALU(result, carryout, overflow, zero, operandA, operandB, command); + + output [31:0] result; + output carryout; + output overflow; + output zero; + input [31:0] operandA; + input [31:0] operandB; + input [2:0] command; + + wire carryout = 0; + wire overflow = 0; + wire zero = 0; + wire [31:0] carryin, addedResult, subResult, xorResult, andResult, orResult; + wire sltResult; + reg [31:0] result; + + + zeroes is_zero(zero,result); + multi_bit_adder adder(addedResult, carryout, overflow, operandA, operandB); + multi_bit_subtracter subtracter(subResult, carryout, overflow, operandA, operandB); + multi_bit_SLT slt(sltResult,operandA,operandB); + multi_bit_and andit(andResult,operandA,operandB); + multi_bit_or orit(orResult,operandA,operandB); + multi_bit_xor xorit(xorResult,operandA,operandB); + //output_mux result_mux(.result(result),.command(command),.operandA(operandA),.operandB(operandB),.addedResult(addedResult),.subResult(subResult),.sltResult(sltResult)); + + always @ (*) begin + case(command) + 3'b000: result = addedResult; + 3'b001: result = subResult; + 3'b010: result = xorResult; + 3'b011: result = sltResult; + 3'b100: result = andResult; + 3'b101: result = ~andResult; + 3'b110: result = ~orResult; + 3'b111: result = orResult; + endcase + end +endmodule + +module zeroes(zero,result); + output zero; + input [31:0] result; + + assign zero = !(1'b0||result[0]) && !(1'b0||result[1]) && !(1'b0||result[2]) && !(1'b0||result[3]) && !(1'b0||result[4]) && !(1'b0||result[5]) && !(1'b0||result[6]) && !(1'b0||result[7]) && !(1'b0||result[8]) && !(1'b0||result[9]) && !(1'b0||result[10]) && !(1'b0||result[11]) && !(1'b0||result[12]) && !(1'b0||result[13]) && !(1'b0||result[14]) && !(1'b0||result[15]) && !(1'b0||result[16]) && !(1'b0||result[17]) && !(1'b0||result[18]) && !(1'b0||result[19]) && !(1'b0||result[20]) && !(1'b0||result[21]) && !(1'b0||result[22]) && !(1'b0||result[23]) && !(1'b0||result[24]) && !(1'b0||result[25]) && !(1'b0||result[26]) && !(1'b0||result[27]) && !(1'b0||result[28]) && !(1'b0||result[29]) && !(1'b0||result[30]) && !(1'b0||result[31]); + +endmodule + + +//We can check if AB[n] @ n then stop and return 0 +//If A[n]=B[n] @ n continue until the end +//If A = B , return 0 + +module multi_bit_SLT(sltresult,A,B); + + output sltresult; + input [31:0] A; + input [31:0] B; + integer i; + + reg sltresult; + initial begin + for (i = 31 ; i >= 0; i = i-1) begin + //If A[n] Date: Thu, 12 Oct 2017 23:26:41 -0400 Subject: [PATCH 21/28] slt sub --- alu.t.v | 2 +- alu.v | 99 ++++++++++++++++----------------------------------------- 2 files changed, 29 insertions(+), 72 deletions(-) diff --git a/alu.t.v b/alu.t.v index e410022..f641cf9 100644 --- a/alu.t.v +++ b/alu.t.v @@ -48,7 +48,7 @@ module testALU (); command = 1; operandA = 32'b10000000000000000000000000000000; operandB = 32'b10000000000000000000000000000000; #50 checkTestCase(0, 1, 1, 1); command = 1; operandA = 32'b11010101010101010101011010101010; operandB = 32'b11111110000000000000000010010101; #50 - checkTestCase(32'b11010111010101010101011000010100, 0, 0, 0); + checkTestCase(32'b11010111010101010101011000010101, 0, 0, 0); //XOR command = 2; operandA = 32'b11111111111111111111111111111111; operandB = 32'b00000000000000000000000000000000; #50 diff --git a/alu.v b/alu.v index b69e93b..b37e853 100644 --- a/alu.v +++ b/alu.v @@ -12,7 +12,7 @@ module ALU(result, carryout, overflow, zero, operandA, operandB, command); wire overflow = 0; wire zero = 0; wire [31:0] carryin, addedResult, subResult, xorResult, andResult, nandResult, norResult, orResult; - wire sltResult; + wire [31:0] sltResult; reg [31:0] result; assign zero = !(1'b0||result[0]) && !(1'b0||result[1]) && !(1'b0||result[2]) && !(1'b0||result[3]) && !(1'b0||result[4]) && !(1'b0||result[5]) && !(1'b0||result[6]) && !(1'b0||result[7]) && !(1'b0||result[8]) && !(1'b0||result[9]) && !(1'b0||result[10]) && !(1'b0||result[11]) && !(1'b0||result[12]) && !(1'b0||result[13]) && !(1'b0||result[14]) && !(1'b0||result[15]) && !(1'b0||result[16]) && !(1'b0||result[17]) && !(1'b0||result[18]) && !(1'b0||result[19]) && !(1'b0||result[20]) && !(1'b0||result[21]) && !(1'b0||result[22]) && !(1'b0||result[23]) && !(1'b0||result[24]) && !(1'b0||result[25]) && !(1'b0||result[26]) && !(1'b0||result[27]) && !(1'b0||result[28]) && !(1'b0||result[29]) && !(1'b0||result[30]) && !(1'b0||result[31]); @@ -36,76 +36,30 @@ module ALU(result, carryout, overflow, zero, operandA, operandB, command); end endmodule -//We can check if AB[n] @ n then stop and return 0 -//If A[n]=B[n] @ n continue until the end -//If A = B , return 0 - +//We can check if A= 0; i = i-1) begin - //If A[n] Date: Thu, 12 Oct 2017 23:56:07 -0400 Subject: [PATCH 22/28] problems w/ carryout --- alu.v | 180 +++++++++++++++++++++++++++++++++++++++++++++++++++------- 1 file changed, 158 insertions(+), 22 deletions(-) diff --git a/alu.v b/alu.v index b37e853..99e6db7 100644 --- a/alu.v +++ b/alu.v @@ -8,34 +8,45 @@ module ALU(result, carryout, overflow, zero, operandA, operandB, command); input [31:0] operandB; input [2:0] command; - wire carryout = 0; - wire overflow = 0; - wire zero = 0; + wire subOverflow,addOverflow,subCarryout,addCarryout; + wire zero; wire [31:0] carryin, addedResult, subResult, xorResult, andResult, nandResult, norResult, orResult; wire [31:0] sltResult; reg [31:0] result; + reg overflow,carryout; - assign zero = !(1'b0||result[0]) && !(1'b0||result[1]) && !(1'b0||result[2]) && !(1'b0||result[3]) && !(1'b0||result[4]) && !(1'b0||result[5]) && !(1'b0||result[6]) && !(1'b0||result[7]) && !(1'b0||result[8]) && !(1'b0||result[9]) && !(1'b0||result[10]) && !(1'b0||result[11]) && !(1'b0||result[12]) && !(1'b0||result[13]) && !(1'b0||result[14]) && !(1'b0||result[15]) && !(1'b0||result[16]) && !(1'b0||result[17]) && !(1'b0||result[18]) && !(1'b0||result[19]) && !(1'b0||result[20]) && !(1'b0||result[21]) && !(1'b0||result[22]) && !(1'b0||result[23]) && !(1'b0||result[24]) && !(1'b0||result[25]) && !(1'b0||result[26]) && !(1'b0||result[27]) && !(1'b0||result[28]) && !(1'b0||result[29]) && !(1'b0||result[30]) && !(1'b0||result[31]); - - multi_bit_adder adder(addedResult, carryout, overflow, operandA, operandB); - multi_bit_subtracter subtracter(subResult, carryout, overflow, operandA, operandB); + zeroes is_zero(zero,result); + multi_bit_adder adder(addedResult, addCarryout, addOverflow, operandA, operandB); + multi_bit_subtracter subtracter(subResult, subCarryout, subOverflow, operandA, operandB); multi_bit_SLT slt(sltResult,operandA,operandB); + multi_bit_and andit(andResult,operandA,operandB); + multi_bit_or orit(orResult,operandA,operandB); + multi_bit_xor xorit(xorResult,operandA,operandB); //output_mux result_mux(.result(result),.command(command),.operandA(operandA),.operandB(operandB),.addedResult(addedResult),.subResult(subResult),.sltResult(sltResult)); always @ (*) begin case(command) - 3'b000: result = addedResult; - 3'b001: result = subResult; - 3'b010: result = operandA ^ operandB; + 3'b000: begin result = addedResult; carryout = addCarryout; overflow = addOverflow; end + 3'b001: begin result = subResult; carryout = subCarryout; overflow = subOverflow; end + 3'b010: result = xorResult; 3'b011: result = sltResult; - 3'b100: result = operandA && operandB; - 3'b101: result = !(operandA && operandB); - 3'b110: result = !(operandA || operandB); - 3'b111: result = operandA || operandB; + 3'b100: result = andResult; + 3'b101: result = ~andResult; + 3'b110: result = ~orResult; + 3'b111: result = orResult; endcase end endmodule +module zeroes(zero,result); + output zero; + input [31:0] result; + + assign zero = !(1'b0||result[0]) && !(1'b0||result[1]) && !(1'b0||result[2]) && !(1'b0||result[3]) && !(1'b0||result[4]) && !(1'b0||result[5]) && !(1'b0||result[6]) && !(1'b0||result[7]) && !(1'b0||result[8]) && !(1'b0||result[9]) && !(1'b0||result[10]) && !(1'b0||result[11]) && !(1'b0||result[12]) && !(1'b0||result[13]) && !(1'b0||result[14]) && !(1'b0||result[15]) && !(1'b0||result[16]) && !(1'b0||result[17]) && !(1'b0||result[18]) && !(1'b0||result[19]) && !(1'b0||result[20]) && !(1'b0||result[21]) && !(1'b0||result[22]) && !(1'b0||result[23]) && !(1'b0||result[24]) && !(1'b0||result[25]) && !(1'b0||result[26]) && !(1'b0||result[27]) && !(1'b0||result[28]) && !(1'b0||result[29]) && !(1'b0||result[30]) && !(1'b0||result[31]); + +endmodule + + //We can check if A Date: Fri, 13 Oct 2017 00:27:17 -0400 Subject: [PATCH 23/28] Finished --- alu.t.v | 4 ++-- alu.v | 9 ++++----- 2 files changed, 6 insertions(+), 7 deletions(-) diff --git a/alu.t.v b/alu.t.v index f641cf9..b9c076e 100644 --- a/alu.t.v +++ b/alu.t.v @@ -60,11 +60,11 @@ module testALU (); //SLT command = 3; operandA = 32'b11111111111111111111111111111111; operandB = 32'b00000000000000000000000000000000; #50 - checkTestCase(32'b00000000000000000000000000000000, 0, 0, 1); + checkTestCase(32'b11111111111111111111111111111111, 0, 0, 1); command = 3; operandA = 32'b11111111111111111111111111111111; operandB = 32'b11111111111111111111111111111111; #50 checkTestCase(32'b00000000000000000000000000000000, 0, 0, 1); command = 3; operandA = 32'b00000000000000000000000000000000; operandB = 32'b11111111111111111111111111111111; #50 - checkTestCase(32'b11111111111111111111111111111111, 0, 0, 0); + checkTestCase(32'b00000000000000000000000000000000, 0, 0, 0); //AND command = 4; operandA = 32'b11111111111111111111111111111111; operandB = 32'b00000000000000000000000000000000; #50 diff --git a/alu.v b/alu.v index 99e6db7..70014f5 100644 --- a/alu.v +++ b/alu.v @@ -135,7 +135,6 @@ module multi_bit_subtracter(result, carryout, overflow, A, B); input [31:0] B; wire [31:0] result; - wire carryout, overflow; wire [31:0] A; wire [31:0] B; wire [31:0] nB; @@ -145,9 +144,9 @@ module multi_bit_subtracter(result, carryout, overflow, A, B); //invert second operand B for subtraction and add 1 to the least significant bit //assign nB = !B[31] && !B[30] && !B[29] && !B[28] && !B[27]&& !B[26] && !B[25] && !B[24] && !B[23] && !B[22] && !B[21]&& !B[20] && !B[19] && !B[18] && !B[17] && !B[16] && !B[15] && !B[14] && !B[13] && !B[12] && !B[11] && !B[10] && !B[9] && !B[8] && !B[7] && !B[6] && !B[5] && !B[4] && !B[3] && !B[2] && !B[1] && !B[0] ; - multi_bit_adder subtract1(sub1, carryout, overflow, A, nB); + multi_bit_adder subtract1(sub1, trash_carryout, trash_overflow, 32'b00000000000000000000000000000001, nB); // Add 1! - multi_bit_adder subtract2(result, carryout, overflow, sub1, 32'b00000000000000000000000000000001); + multi_bit_adder subtract2(result, carryout, overflow, sub1, A); endmodule @@ -252,7 +251,7 @@ module multi_bit_or(orResult, operandA, operandB); assign or30 = operandA[30] || operandB[30]; assign or31 = operandA[31] || operandB[31]; - assign orResult = {or0,or1,or2,or3,or4,or5,or6,or7,or8,or9,or10,or11,or12,or13,or14,or15,or16,or17,or18,or19,or20,or21,or22,or23,or24,or25,or26,or27,or28,or29,or30,or31}; + assign orResult = {or31,or30,or29,or28,or27,or26,or25,or24,or23,or22,or21,or20,or19,or18,or17,or16,or15,or14,or13,or12,or11,or10,or9,or8,or7,or6,or5,or4,or3,or2,or1,or0}; endmodule module multi_bit_xor(xorResult, operandA, operandB); @@ -296,5 +295,5 @@ module multi_bit_xor(xorResult, operandA, operandB); assign xor30 = (!operandA[30] && operandB[30]) || (operandA[30] && !operandB[30]); assign xor31 = (!operandA[31] && operandB[31]) || (operandA[31] && !operandB[31]); - assign xorResult = {xor0,xor1,xor2,xor3,xor4,xor5,xor6,xor7,xor8,xor9,xor10,xor11,xor12,xor13,xor14,xor15,xor16,xor17,xor18,xor19,xor20,xor21,xor22,xor23,xor24,xor25,xor26,xor27,xor28,xor29,xor30,xor31}; + assign xorResult = {xor31,xor30,xor29,xor28,xor27,xor26,xor25,xor24,xor23,xor22,xor21,xor20,xor19,xor18,xor17,xor16,xor15,xor14,xor13,xor12,xor11,xor10,xor9,xor8,xor7,xor6,xor5,xor4,xor3,xor2,xor1,xor0}; endmodule \ No newline at end of file From 075a3f9ce029dc9668852da4803115f950c103f8 Mon Sep 17 00:00:00 2001 From: Wilson Tang Date: Fri, 13 Oct 2017 00:33:50 -0400 Subject: [PATCH 24/28] timing delays added --- alu.v | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/alu.v b/alu.v index 70014f5..68453a1 100644 --- a/alu.v +++ b/alu.v @@ -1,3 +1,11 @@ +`define AND and #30 +`define OR or #30 +`define NOT not #10 +`define NAND nand #20 +`define NOR nor #20 +`define XOR xor #30 + + module ALU(result, carryout, overflow, zero, operandA, operandB, command); output [31:0] result; From ac332055ee9f3d301214c6a7043b451c75cf389b Mon Sep 17 00:00:00 2001 From: Bryan Werth Date: Fri, 13 Oct 2017 00:54:29 -0400 Subject: [PATCH 25/28] Finished --- Waveform.JPG | Bin 0 -> 82848 bytes alu.t.v | 44 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