From d1605305594521483709e2866da31afb4d11c92c Mon Sep 17 00:00:00 2001 From: xiaozhengxu Date: Tue, 3 Oct 2017 16:24:14 -0400 Subject: [PATCH 01/11] Create workplan.txt --- workplan.txt | 4 ++++ 1 file changed, 4 insertions(+) create mode 100644 workplan.txt diff --git a/workplan.txt b/workplan.txt new file mode 100644 index 0000000..3ef20de --- /dev/null +++ b/workplan.txt @@ -0,0 +1,4 @@ +Completing test bench: 2hr, done by Tues Oct 10 +Writing and testing logic verilog: 2hr, done by Tues Oct 10 +Finishing report: 1hr, by Thursday Oct 12 +Total: 5hr From 7c927653a11c166caa20138f4287f3d93b57242e Mon Sep 17 00:00:00 2001 From: juicyslew Date: Tue, 10 Oct 2017 13:40:21 -0400 Subject: [PATCH 02/11] first pass --- AddSub.v | 27 + alu.t.v | 92 + alu.v | 74 + alu.vcd | 172 + multiplexer.t.v | 40 + multiplexer.v | 36 + multiplexer.vcd | 54 + test | 8629 +++++++++++++++++++++++++++++++++++++++++++++++ 8 files changed, 9124 insertions(+) create mode 100644 AddSub.v create mode 100755 alu.t.v create mode 100755 alu.v create mode 100644 alu.vcd create mode 100644 multiplexer.t.v create mode 100644 multiplexer.v create mode 100644 multiplexer.vcd create mode 100755 test diff --git a/AddSub.v b/AddSub.v new file mode 100644 index 0000000..ad7889b --- /dev/null +++ b/AddSub.v @@ -0,0 +1,27 @@ +`define AND and #20 +`define OR or #20 +`define XOR xor #20 //???? +`define NOT not #10 +`define NAND nand #10 +`define NOR nor #10 + +module structAddSub +( + output sum, + output carryout, + input a, + input b, + input sub, carryin +); + wire AxorB; + wire AandB; + wire AxorBandCarryIn; + wire bnew; + + `XOR (bnew, b, sub); + `XOR (AxorB, a, b); + `XOR (sum, AxorB, carryin); + `AND (AandB, a, b); + `AND (AxorBandCarryIn, AxorB, carryin); + `OR (carryout, AxorBandCarryIn, AandB); +endmodule diff --git a/alu.t.v b/alu.t.v new file mode 100755 index 0000000..35e9e74 --- /dev/null +++ b/alu.t.v @@ -0,0 +1,92 @@ +`timescale 1 ns / 1 ps +`include "alu.v" + +`define opADD 3'd0 +`define opSUB 3'd1 +`define opXOR 3'd2 +`define opSLT 3'd3 +`define opAND 3'd4 +`define opNAND 3'd5 +`define opNOR 3'd6 +`define opOR 3'd7 + +module ALUcontrolLUT +( +output reg[2:0] muxindex, +output reg invertB, +output reg flagger, +input[2:0] ALUcommand +); + + always @(ALUcommand) begin + case (ALUcommand) + `opADD: begin muxindex = 0; invertB=0; flagger = 1; end + `opSUB: begin muxindex = 0; invertB=1; flagger = 1; end + `opXOR: begin muxindex = 1; invertB=0; flagger = 0; end + `opSLT: begin muxindex = 2; invertB=0; flagger = 0; end + `opAND: begin muxindex = 3; invertB=1; flagger = 0; end + `opNAND: begin muxindex = 3; invertB=0; flagger = 0; end + `opNOR: begin muxindex = 4; invertB=0; flagger = 0; end + `opOR: begin muxindex = 4; invertB=1; flagger = 0; end + endcase + end +endmodule + +module ALUTestBench(); + reg[2:0] command; + reg[31:0] operandA; + reg[31:0] operandB; + wire invertB; + wire flagger; + wire[2:0] muxindex; + wire[31:0] result; + wire carryout; + wire zero; + wire overflow; + + ALUcontrolLUT controller(muxindex, invertB, flagger, command); + + ALU alu(result, carryout, zero, overflow, operandA, operandB, muxindex, invertB, flagger); + + initial begin + $dumpfile("alu.vcd"); + $dumpvars(0, operandA, operandB, result, overflow, command, muxindex, invertB); + + $display(" A | B | Com | Out "); + operandA = -5358; //Set register a. + operandB = 5369; //Set register b. + command = 0; + #1000 //Delay. + $display(" %d | %d | %d | %d ", $signed(operandA), $signed(operandB), command, $signed(result)); + operandA = 552; //Set register a. + operandB = 600; //Set register b. + command = 1; + #1000 //Delay. + $display(" %d | %d | %d | %d ", $signed(operandA), $signed(operandB), command, $signed(result)); + operandA = 300; //Set register a. + operandB = 25; //Set register b. + command = 2; + #1000 //Delay. + $display(" %d | %d | %d | %d ", $signed(operandA), $signed(operandB), command, $signed(result)); + operandA = 360; //Set register a. + operandB = 111; //Set register b. + command = 4; + #1000 //Delay. + $display(" %d | %d | %d | %d ", $signed(operandA), $signed(operandB), command, $signed(result)); + operandA = -2; //Set register a. + operandB = -60694; //Set register b. + command = 5; + #1000 //Delay. + $display(" %d | %d | %d | %d ", $signed(operandA), $signed(operandB), command, $signed(result)); + operandA = -2959; //Set register a. + operandB = 6333; //Set register b. + command = 6; + #1000 //Delay. + $display(" %d | %d | %d | %d ", $signed(operandA), $signed(operandB), command, $signed(result)); + operandA = -1045; //Set register a. + operandB = 54968; //Set register b. + command = 7; + #1000 //Delay. + $display(" %d | %d | %d | %d ", $signed(operandA), $signed(operandB), command, $signed(result)); + end +endmodule diff --git a/alu.v b/alu.v new file mode 100755 index 0000000..9e1cd2e --- /dev/null +++ b/alu.v @@ -0,0 +1,74 @@ +`define AND and #20 +`define OR or #20 +`define XOR xor #20 //???? +`define NOT not #10 +`define NAND nand #10 +`define NOR nor #10 + +`include "multiplexer.v" +`include "AddSub.v" + +module BitSliceALU +( + output ALUout, + output Cout, + input invertB, + input Cin, + input[2:0] addr, + input bit1, bit2 +); + wire Cout; + wire [7:0] out; + structAddSub structadder(out[0], Cout, bit1, bit2, invertB, Cin); + + wire nored, nanded; + + `XOR (out[1], bit1, bit2); + + `NAND (nanded, bit1, bit2); + `XOR (out[3], invertB, nanded); + + `NOR (nored, bit1, bit2); + `XOR (out[4], invertB, nored); + + //`XOR (out[2], bit1, bit2); + /*wire sum, Cout; + + structAddSub structadder(out[2], Cout, bit1, bit2, invertB, Cin); + + assign out[0] = bit1; + assign out[1] = bit2;*/ + //assign out[7:0] = 8'b0; + + structuralMultiplexer opmux(ALUout, addr, out); +endmodule + +module ALU +( +output[31:0] result, +output carryout, +output zero, +output overflow, +input[31:0] operandA, +input[31:0] operandB, +input[2:0] mux, +input invertB, +input flags +); + //wire control2; + wire overflow; + wire[31:0] Cout; + //integer i = 0; + BitSliceALU bit0(result[0], Cout[0], invertB, 1'b0, mux, operandA[0], operandB[0]); + //always @(*) + genvar i; + generate + for (i = 1; i < 32; i = i+1) + begin: ripple + BitSliceALU bit(result[i], Cout[i], invertB, Cout[i-1], mux, operandA[i], operandB[i]); + end + endgenerate + + + `XOR (overflow, Cout[31], Cout[30]); +endmodule diff --git a/alu.vcd b/alu.vcd new file mode 100644 index 0000000..340cbb2 --- /dev/null +++ b/alu.vcd @@ -0,0 +1,172 @@ +$date + Mon Oct 9 23:40:39 2017 +$end +$version + Icarus Verilog +$end +$timescale + 1ps +$end +$scope module ALUTestBench $end +$var reg 32 ! operandA [31:0] $end +$upscope $end +$scope module ALUTestBench $end +$var reg 32 " operandB [31:0] $end +$upscope $end +$scope module ALUTestBench $end +$var wire 32 # result [31:0] $end +$upscope $end +$scope module ALUTestBench $end +$var wire 1 $ overflow $end +$upscope $end +$scope module ALUTestBench $end +$var reg 3 % command [2:0] $end +$upscope $end +$scope module ALUTestBench $end +$var wire 3 & muxindex [2:0] $end +$upscope $end +$scope module ALUTestBench $end +$var wire 1 ' invertB $end +$upscope $end +$enddefinitions $end +#0 +$dumpvars +0' +b0 & +b0 % +x$ +bx # +b1010011111001 " +b11111111111111111110101100010010 ! +$end +#160000 +bx1 # +#180000 +bx0xxx11 # +#200000 +bx0x1x11 # +#220000 +bx00x1011 # +#240000 +bx0001011 # +#260000 +bx00001011 # +#300000 +bx000001011 # +#340000 +bx0000001011 # +#380000 +bx00000001011 # +#420000 +bx000000001011 # +#460000 +bx0000000001011 # +#500000 +bx00000000001011 # +#540000 +bx000000000001011 # +#580000 +bx0000000000001011 # +#620000 +bx00000000000001011 # +#660000 +bx000000000000001011 # +#700000 +bx0000000000000001011 # +#740000 +bx00000000000000001011 # +#780000 +bx000000000000000001011 # +#820000 +bx0000000000000000001011 # +#860000 +bx00000000000000000001011 # +#900000 +bx000000000000000000001011 # +#940000 +bx0000000000000000000001011 # +#980000 +bx00000000000000000000001011 # +#1000000 +1' +b1 % +b1001011000 " +b1000101000 ! +#1020000 +bx000000000000000000000001011 # +#1060000 +bx0000000000000000000000001011 # +#1080000 +0$ +#1100000 +bx00000000000000000000000001011 # +#1140000 +bx000000000000000000000000001011 # +#1160000 +bx111111111111111111111110010000 # +#1180000 +bx1111111111111111111111110100000 # +#1200000 +b10010100000 # +#1220000 +b10011000000 # +#1260000 +b10000000000 # +#1300000 +b10010000000 # +#2000000 +0' +b1 & +b10 % +b11001 " +b100101100 ! +#2120000 +b10011110000 # +#2130000 +b1110000 # +#2140000 +b100110101 # +#3000000 +1' +b11 & +b100 % +b1101111 " +b101101000 ! +#3080000 +b11111111111111111111111111110111 # +#3140000 +b1101000 # +#4000000 +0' +b101 % +b11111111111111110001001011101010 " +b11111111111111111111111111111110 ! +#4140000 +b1110110100010101 # +#5000000 +b100 & +b110 % +b1100010111101 " +b11111111111111111111010001110001 ! +#5040000 +bx111x11x1xxx1x1x1 # +#5050000 +bx # +#5120000 +b0x # +#5130000 +b1 # +#5150000 +b1100000010 # +#5660000 +1$ +#5680000 +0$ +#6000000 +1' +b111 % +b1101011010111000 " +b11111111111111111111101111101011 ! +#6140000 +b11111111111111111111111111111011 # +#7000000 diff --git a/multiplexer.t.v b/multiplexer.t.v new file mode 100644 index 0000000..1f95ee4 --- /dev/null +++ b/multiplexer.t.v @@ -0,0 +1,40 @@ +// Multiplexer testbench +`timescale 1 ns / 1 ps +`include "multiplexer.v" + +module testMultiplexer (); + reg[2:0] address; + reg[7:0] in; + reg na; + wire out; + //behavioralMultiplexer decoder (out, addr0, addr1, in0, in1, in2, in3); + structuralMultiplexer decoder (out, address, in); // Swap after testing + + initial begin + $dumpfile("multiplexer.vcd"); + $dumpvars(0, address, in, out); + $display("A0 A1 | I0 I1 I2 I3 | Out "); + address = 0; #1000 + $display(" %b %b | %b %b %b %b | %b ", address[0], address[1], in[0], in[1], in[2], in[3], out); + in[0] = 0; + address = 0; #1000 + $display(" %b %b | %b %b %b %b | %b ", address[0], address[1], in[0], in[1], in[2], in[3], out); + in[0] = 1; + address = 0; #1000 + $display(" %b %b | %b %b %b %b | %b ", address[0], address[1], in[0], in[1], in[2], in[3], out); + in[0] = na; + in[1] = 0; + address = 1; #1000 + $display(" %b %b | %b %b %b %b | %b ", address[0], address[1], in[0], in[1], in[2], in[3], out); + in[1] = 1; + address = 1; #1000 + $display(" %b %b | %b %b %b %b | %b ", address[0], address[1], in[0], in[1], in[2], in[3], out); + in[1] = na; + in[2] = 0; + address = 2; #1000 + $display(" %b %b | %b %b %b %b | %b ", address[0], address[1], in[0], in[1], in[2], in[3], out); + in[2] = 1; + address = 2; #1000 + $display(" %b %b | %b %b %b %b | %b ", address[0], address[1], in[0], in[1], in[2], in[3], out); + end +endmodule diff --git a/multiplexer.v b/multiplexer.v new file mode 100644 index 0000000..b47730b --- /dev/null +++ b/multiplexer.v @@ -0,0 +1,36 @@ +`define AND and #20 +`define OR or #20 +`define XOR xor #20 //???? +`define NOT not #10 +`define NAND nand #10 +`define NOR nor #10 + +module bitMultiplexer +( + output out, + input addr, + input[1:0] in +); + wire naddr; + `NOT n_addr(naddr, addr); + `AND and_0(o0, in[0], naddr); + `AND and_1(o1, in[1], addr); + `OR or_out(out, o0, o1); +endmodule + +module structuralMultiplexer +( + output out, + input[2:0] address, + input[7:0] in +); + wire[3:0] mux; + wire[1:0] muxmid; + bitMultiplexer mux_0(mux[0], address[0], in[1:0]); + bitMultiplexer mux_1(mux[1], address[0], in[3:2]); + bitMultiplexer mux_2(mux[2], address[0], in[5:4]); + bitMultiplexer mux_3(mux[3], address[0], in[7:6]); + bitMultiplexer mux_mid_0(muxmid[0], address[1], mux[1:0]); + bitMultiplexer mux_mid_1(muxmid[1], address[1], mux[3:2]); + bitMultiplexer mux_out(out, address[2], muxmid[1:0]); +endmodule diff --git a/multiplexer.vcd b/multiplexer.vcd new file mode 100644 index 0000000..31fb425 --- /dev/null +++ b/multiplexer.vcd @@ -0,0 +1,54 @@ +$date + Mon Oct 9 21:56:39 2017 +$end +$version + Icarus Verilog +$end +$timescale + 1ps +$end +$scope module testMultiplexer $end +$var reg 3 ! address [2:0] $end +$upscope $end +$scope module testMultiplexer $end +$var reg 8 " in [7:0] $end +$upscope $end +$scope module testMultiplexer $end +$var wire 1 # out $end +$upscope $end +$enddefinitions $end +#0 +$dumpvars +x# +bx " +b0 ! +$end +#1000000 +bx0 " +#1120000 +0# +#2000000 +bx1 " +#2120000 +1# +#3000000 +b1 ! +bx0x " +#3130000 +0# +#4000000 +bx1x " +#4120000 +1# +#5000000 +b10 ! +bx0xx " +#5090000 +x# +#5120000 +0# +#6000000 +bx1xx " +#6120000 +1# +#7000000 diff --git a/test b/test new file mode 100755 index 0000000..ab67e2b --- /dev/null +++ b/test @@ -0,0 +1,8629 @@ +#! /usr/local/bin/vvp +:ivl_version "11.0 (devel)" "(s20150603-477-gc855b89)"; +:ivl_delay_selection "TYPICAL"; +:vpi_time_precision - 12; +:vpi_module "system"; +:vpi_module "vhdl_sys"; +:vpi_module "vhdl_textio"; +:vpi_module "v2005_math"; +:vpi_module "va_math"; +S_0x171a660 .scope module, "ALUTestBench" "ALUTestBench" 2 35; + .timescale -9 -12; +o0x7fc2cd934b08 .functor BUFZ 1, C4; HiZ drive +v0x17dbda0_0 .net "carryout", 0 0, o0x7fc2cd934b08; 0 drivers +v0x17dbe90_0 .var "command", 2 0; +v0x17dbf60_0 .net "flagger", 0 0, v0x17dbad0_0; 1 drivers +v0x17dc080_0 .net "invertB", 0 0, v0x17dbbc0_0; 1 drivers +v0x17dc120_0 .net "muxindex", 2 0, v0x17dbc90_0; 1 drivers +v0x17dc210_0 .var "operandA", 31 0; +v0x17dc2b0_0 .var "operandB", 31 0; +v0x17dc350_0 .net "overflow", 0 0, L_0x188d310; 1 drivers +v0x17dc420_0 .net "result", 31 0, L_0x1890560; 1 drivers +o0x7fc2cd934c28 .functor BUFZ 1, C4; HiZ drive +v0x17dc580_0 .net "zero", 0 0, o0x7fc2cd934c28; 0 drivers +S_0x16fa6c0 .scope module, "alu" "ALU" 2 49, 3 46 0, S_0x171a660; + .timescale -9 -12; + .port_info 0 /OUTPUT 32 "result" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /OUTPUT 1 "zero" + .port_info 3 /OUTPUT 1 "overflow" + .port_info 4 /INPUT 32 "operandA" + .port_info 5 /INPUT 32 "operandB" + .port_info 6 /INPUT 3 "mux" + .port_info 7 /INPUT 1 "invertB" + .port_info 8 /INPUT 1 "flags" +L_0x188d310/d .functor XOR 1, L_0x18850e0, L_0x1891910, C4<0>, C4<0>; +L_0x188d310 .delay 1 (20000,20000,20000) L_0x188d310/d; +v0x17da3f0_0 .net "Cout", 31 0, L_0x188ae60; 1 drivers +v0x17da4f0_0 .net *"_s231", 0 0, L_0x18850e0; 1 drivers +v0x17da5d0_0 .net *"_s233", 0 0, L_0x1891910; 1 drivers +v0x17da6c0_0 .net "carryout", 0 0, o0x7fc2cd934b08; alias, 0 drivers +v0x17da780_0 .net "flags", 0 0, v0x17dbad0_0; alias, 1 drivers +v0x17da840_0 .net "invertB", 0 0, v0x17dbbc0_0; alias, 1 drivers +v0x1778750_0 .net "mux", 2 0, v0x17dbc90_0; alias, 1 drivers +v0x1778810_0 .net "operandA", 31 0, v0x17dc210_0; 1 drivers +v0x17788f0_0 .net "operandB", 31 0, v0x17dc2b0_0; 1 drivers +v0x1778a60_0 .net "overflow", 0 0, L_0x188d310; alias, 1 drivers +v0x1777760_0 .net "result", 31 0, L_0x1890560; alias, 1 drivers +v0x1777840_0 .net "zero", 0 0, o0x7fc2cd934c28; alias, 0 drivers +L_0x17e1c70 .part L_0x188ae60, 0, 1; +L_0x17e1da0 .part v0x17dc210_0, 1, 1; +L_0x17e1e40 .part v0x17dc2b0_0, 1, 1; +L_0x17e7390 .part L_0x188ae60, 1, 1; +L_0x17e74c0 .part v0x17dc210_0, 2, 1; +L_0x17e7560 .part v0x17dc2b0_0, 2, 1; +L_0x17ecba0 .part L_0x188ae60, 2, 1; +L_0x17eccd0 .part v0x17dc210_0, 3, 1; +L_0x17ece00 .part v0x17dc2b0_0, 3, 1; +L_0x17f2420 .part L_0x188ae60, 3, 1; +L_0x17f25e0 .part v0x17dc210_0, 4, 1; +L_0x17f2680 .part v0x17dc2b0_0, 4, 1; +L_0x17f7d60 .part L_0x188ae60, 4, 1; +L_0x17f7e90 .part v0x17dc210_0, 5, 1; +L_0x17f7fb0 .part v0x17dc2b0_0, 5, 1; +L_0x17fd4f0 .part L_0x188ae60, 5, 1; +L_0x17fd6b0 .part v0x17dc210_0, 6, 1; +L_0x17fd750 .part v0x17dc2b0_0, 6, 1; +L_0x1802cf0 .part L_0x188ae60, 6, 1; +L_0x1802e20 .part v0x17dc210_0, 7, 1; +L_0x17f8440 .part v0x17dc2b0_0, 7, 1; +L_0x18085b0 .part L_0x188ae60, 7, 1; +L_0x1802fd0 .part v0x17dc210_0, 8, 1; +L_0x18088b0 .part v0x17dc2b0_0, 8, 1; +L_0x180e6d0 .part L_0x188ae60, 8, 1; +L_0x180e800 .part v0x17dc210_0, 9, 1; +L_0x1808a60 .part v0x17dc2b0_0, 9, 1; +L_0x1814010 .part L_0x188ae60, 9, 1; +L_0x180e8a0 .part v0x17dc210_0, 10, 1; +L_0x1814230 .part v0x17dc2b0_0, 10, 1; +L_0x1819950 .part L_0x188ae60, 10, 1; +L_0x1819a80 .part v0x17dc210_0, 11, 1; +L_0x18143e0 .part v0x17dc2b0_0, 11, 1; +L_0x181f270 .part L_0x188ae60, 11, 1; +L_0x1819b20 .part v0x17dc210_0, 12, 1; +L_0x181f4c0 .part v0x17dc2b0_0, 12, 1; +L_0x1824bc0 .part L_0x188ae60, 12, 1; +L_0x1824cf0 .part v0x17dc210_0, 13, 1; +L_0x181f670 .part v0x17dc2b0_0, 13, 1; +L_0x182a490 .part L_0x188ae60, 13, 1; +L_0x1824d90 .part v0x17dc210_0, 14, 1; +L_0x1824e30 .part v0x17dc2b0_0, 14, 1; +L_0x182fd80 .part L_0x188ae60, 14, 1; +L_0x182feb0 .part v0x17dc210_0, 15, 1; +L_0x1802ec0 .part v0x17dc2b0_0, 15, 1; +L_0x1835890 .part L_0x188ae60, 15, 1; +L_0x18086e0 .part v0x17dc210_0, 16, 1; +L_0x1830160 .part v0x17dc2b0_0, 16, 1; +L_0x183b290 .part L_0x188ae60, 16, 1; +L_0x183b3c0 .part v0x17dc210_0, 17, 1; +L_0x1835e60 .part v0x17dc2b0_0, 17, 1; +L_0x1840b30 .part L_0x188ae60, 17, 1; +L_0x183b460 .part v0x17dc210_0, 18, 1; +L_0x183b500 .part v0x17dc2b0_0, 18, 1; +L_0x1846440 .part L_0x188ae60, 18, 1; +L_0x1846570 .part v0x17dc210_0, 19, 1; +L_0x1840f20 .part v0x17dc2b0_0, 19, 1; +L_0x184bcf0 .part L_0x188ae60, 19, 1; +L_0x1846610 .part v0x17dc210_0, 20, 1; +L_0x18466b0 .part v0x17dc2b0_0, 20, 1; +L_0x1851de0 .part L_0x188ae60, 20, 1; +L_0x1851f10 .part v0x17dc210_0, 21, 1; +L_0x184c110 .part v0x17dc2b0_0, 21, 1; +L_0x1857730 .part L_0x188ae60, 21, 1; +L_0x1851fb0 .part v0x17dc210_0, 22, 1; +L_0x1852050 .part v0x17dc2b0_0, 22, 1; +L_0x185cff0 .part L_0x188ae60, 22, 1; +L_0x185d120 .part v0x17dc210_0, 23, 1; +L_0x1857b80 .part v0x17dc2b0_0, 23, 1; +L_0x1862920 .part L_0x188ae60, 23, 1; +L_0x185d1c0 .part v0x17dc210_0, 24, 1; +L_0x185d260 .part v0x17dc2b0_0, 24, 1; +L_0x1868260 .part L_0x188ae60, 24, 1; +L_0x1868390 .part v0x17dc210_0, 25, 1; +L_0x1862da0 .part v0x17dc2b0_0, 25, 1; +L_0x186db50 .part L_0x188ae60, 25, 1; +L_0x1868430 .part v0x17dc210_0, 26, 1; +L_0x18684d0 .part v0x17dc2b0_0, 26, 1; +L_0x1873460 .part L_0x188ae60, 26, 1; +L_0x1873590 .part v0x17dc210_0, 27, 1; +L_0x186dc80 .part v0x17dc2b0_0, 27, 1; +L_0x1879cb0 .part L_0x188ae60, 27, 1; +L_0x1873630 .part v0x17dc210_0, 28, 1; +L_0x18736d0 .part v0x17dc2b0_0, 28, 1; +L_0x187f5f0 .part L_0x188ae60, 28, 1; +L_0x187f720 .part v0x17dc210_0, 29, 1; +L_0x1879de0 .part v0x17dc2b0_0, 29, 1; +L_0x1884f40 .part L_0x188ae60, 29, 1; +L_0x187f7c0 .part v0x17dc210_0, 30, 1; +L_0x187f860 .part v0x17dc2b0_0, 30, 1; +L_0x188a880 .part L_0x188ae60, 30, 1; +L_0x188a9b0 .part v0x17dc210_0, 31, 1; +L_0x182ff50 .part v0x17dc2b0_0, 31, 1; +LS_0x1890560_0_0 .concat8 [ 1 1 1 1], L_0x18902f0, L_0x17e1a00, L_0x17e7120, L_0x17ec930; +LS_0x1890560_0_4 .concat8 [ 1 1 1 1], L_0x17f21b0, L_0x17f7af0, L_0x17fd280, L_0x1802a80; +LS_0x1890560_0_8 .concat8 [ 1 1 1 1], L_0x1808340, L_0x17db7b0, L_0x1813da0, L_0x18196e0; +LS_0x1890560_0_12 .concat8 [ 1 1 1 1], L_0x181f000, L_0x1824950, L_0x182a220, L_0x182fb10; +LS_0x1890560_0_16 .concat8 [ 1 1 1 1], L_0x1835620, L_0x183b020, L_0x18408c0, L_0x18461d0; +LS_0x1890560_0_20 .concat8 [ 1 1 1 1], L_0x184ba80, L_0x1851b70, L_0x18574c0, L_0x185cd80; +LS_0x1890560_0_24 .concat8 [ 1 1 1 1], L_0x18626b0, L_0x1867ff0, L_0x186d8e0, L_0x18731f0; +LS_0x1890560_0_28 .concat8 [ 1 1 1 1], L_0x1879a40, L_0x187f380, L_0x1884cd0, L_0x188a610; +LS_0x1890560_1_0 .concat8 [ 4 4 4 4], LS_0x1890560_0_0, LS_0x1890560_0_4, LS_0x1890560_0_8, LS_0x1890560_0_12; +LS_0x1890560_1_4 .concat8 [ 4 4 4 4], LS_0x1890560_0_16, LS_0x1890560_0_20, LS_0x1890560_0_24, LS_0x1890560_0_28; +L_0x1890560 .concat8 [ 16 16 0 0], LS_0x1890560_1_0, LS_0x1890560_1_4; +LS_0x188ae60_0_0 .concat8 [ 1 1 1 1], L_0x188b560, L_0x17dcd10, L_0x17e2660, L_0x17e7ce0; +LS_0x188ae60_0_4 .concat8 [ 1 1 1 1], L_0x17e8ff0, L_0x17f2d60, L_0x17f8690, L_0x17fded0; +LS_0x188ae60_0_8 .concat8 [ 1 1 1 1], L_0x1803760, L_0x1808fa0, L_0x180f010, L_0x1814900; +LS_0x188ae60_0_12 .concat8 [ 1 1 1 1], L_0x181a270, L_0x181fbc0, L_0x1825510, L_0x182adf0; +LS_0x188ae60_0_16 .concat8 [ 1 1 1 1], L_0x1830890, L_0x1831bd0, L_0x183bbd0, L_0x1841490; +LS_0x188ae60_0_20 .concat8 [ 1 1 1 1], L_0x1846d60, L_0x184c660, L_0x1852730, L_0x1853a70; +LS_0x188ae60_0_24 .concat8 [ 1 1 1 1], L_0x185d920, L_0x18632b0, L_0x1868ba0, L_0x186e410; +LS_0x188ae60_0_28 .concat8 [ 1 1 1 1], L_0x1873d30, L_0x187a5a0, L_0x187ff40, L_0x1885880; +LS_0x188ae60_1_0 .concat8 [ 4 4 4 4], LS_0x188ae60_0_0, LS_0x188ae60_0_4, LS_0x188ae60_0_8, LS_0x188ae60_0_12; +LS_0x188ae60_1_4 .concat8 [ 4 4 4 4], LS_0x188ae60_0_16, LS_0x188ae60_0_20, LS_0x188ae60_0_24, LS_0x188ae60_0_28; +L_0x188ae60 .concat8 [ 16 16 0 0], LS_0x188ae60_1_0, LS_0x188ae60_1_4; +L_0x188b0a0 .part v0x17dc210_0, 0, 1; +L_0x18359c0 .part v0x17dc2b0_0, 0, 1; +L_0x18850e0 .part L_0x188ae60, 31, 1; +L_0x1891910 .part L_0x188ae60, 30, 1; +S_0x16da720 .scope module, "bit0" "BitSliceALU" 3 62, 3 11 0, S_0x16fa6c0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "ALUout" + .port_info 1 /OUTPUT 1 "Cout" + .port_info 2 /INPUT 1 "invertB" + .port_info 3 /INPUT 1 "Cin" + .port_info 4 /INPUT 3 "addr" + .port_info 5 /INPUT 1 "bit1" + .port_info 6 /INPUT 1 "bit2" +L_0x188b710/d .functor XOR 1, L_0x188b0a0, L_0x18359c0, C4<0>, C4<0>; +L_0x188b710 .delay 1 (20000,20000,20000) L_0x188b710/d; +L_0x188b870/d .functor NAND 1, L_0x188b0a0, L_0x18359c0, C4<1>, C4<1>; +L_0x188b870 .delay 1 (10000,10000,10000) L_0x188b870/d; +L_0x188b9d0/d .functor XOR 1, v0x17dbbc0_0, L_0x188b870, C4<0>, C4<0>; +L_0x188b9d0 .delay 1 (20000,20000,20000) L_0x188b9d0/d; +L_0x188bae0/d .functor NOR 1, L_0x188b0a0, L_0x18359c0, C4<0>, C4<0>; +L_0x188bae0 .delay 1 (10000,10000,10000) L_0x188bae0/d; +L_0x188bc40/d .functor XOR 1, v0x17dbbc0_0, L_0x188bae0, C4<0>, C4<0>; +L_0x188bc40 .delay 1 (20000,20000,20000) L_0x188bc40/d; +v0x16d9290_0 .net "ALUout", 0 0, L_0x18902f0; 1 drivers +L_0x7fc2cd8a5018 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +v0x16d9350_0 .net "Cin", 0 0, L_0x7fc2cd8a5018; 1 drivers +v0x16d7540_0 .net "Cout", 0 0, L_0x188b560; 1 drivers +v0x16d75e0_0 .net *"_s11", 0 0, L_0x188bc40; 1 drivers +L_0x7fc2cd8a5060 .functor BUFT 1, C4, C4<0>, C4<0>, C4<0>; +v0x16d5a90_0 .net *"_s15", 0 0, L_0x7fc2cd8a5060; 1 drivers +o0x7fc2cd90c308 .functor BUFZ 3, C4; HiZ drive +; Elide local net with no drivers, v0x16d3d70_0 name=_s17 +v0x16cd0f0_0 .net *"_s3", 0 0, L_0x188b710; 1 drivers +v0x16bd770_0 .net *"_s7", 0 0, L_0x188b9d0; 1 drivers +v0x16baf40_0 .net "addr", 2 0, v0x17dbc90_0; alias, 1 drivers +v0x16bb000_0 .net "bit1", 0 0, L_0x188b0a0; 1 drivers +v0x16b92f0_0 .net "bit2", 0 0, L_0x18359c0; 1 drivers +v0x16b9390_0 .net "invertB", 0 0, v0x17dbbc0_0; alias, 1 drivers +v0x16b75a0_0 .net "nanded", 0 0, L_0x188b870; 1 drivers +v0x16b7640_0 .net "nored", 0 0, L_0x188bae0; 1 drivers +v0x16b5af0_0 .net "out", 7 0, L_0x18951d0; 1 drivers +LS_0x18951d0_0_0 .concat [ 1 1 1 1], L_0x18302d0, L_0x188b710, L_0x7fc2cd8a5060, L_0x188b9d0; +LS_0x18951d0_0_4 .concat [ 1 3 0 0], L_0x188bc40, o0x7fc2cd90c308; +L_0x18951d0 .concat [ 4 4 0 0], LS_0x18951d0_0_0, LS_0x18951d0_0_4; +S_0x16ba780 .scope module, "opmux" "structuralMultiplexer" 3 43, 4 21 0, S_0x16da720; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 3 "address" + .port_info 2 /INPUT 8 "in" +v0x170d030_0 .net "address", 2 0, v0x17dbc90_0; alias, 1 drivers +v0x16fd6b0_0 .net "in", 7 0, L_0x18951d0; alias, 1 drivers +v0x16fae80_0 .net "mux", 3 0, L_0x188e400; 1 drivers +v0x16faf40_0 .net "muxmid", 1 0, L_0x188f920; 1 drivers +v0x16f9230_0 .net "out", 0 0, L_0x18902f0; alias, 1 drivers +L_0x188c630 .part v0x17dbc90_0, 0, 1; +L_0x188c790 .part L_0x18951d0, 0, 2; +L_0x188d020 .part v0x17dbc90_0, 0, 1; +L_0x188d180 .part L_0x18951d0, 2, 2; +L_0x188d9f0 .part v0x17dbc90_0, 0, 1; +L_0x188db50 .part L_0x18951d0, 4, 2; +L_0x188e400 .concat8 [ 1 1 1 1], L_0x188c4d0, L_0x188cec0, L_0x188d890, L_0x188e2a0; +L_0x188e650 .part v0x17dbc90_0, 0, 1; +L_0x188e740 .part L_0x18951d0, 6, 2; +L_0x188ef80 .part v0x17dbc90_0, 1, 1; +L_0x188f0e0 .part L_0x188e400, 0, 2; +L_0x188f920 .concat8 [ 1 1 0 0], L_0x188ee20, L_0x188f7c0; +L_0x188fb20 .part v0x17dbc90_0, 1, 1; +L_0x188fbc0 .part L_0x188e400, 2, 2; +L_0x1890400 .part v0x17dbc90_0, 2, 1; +S_0x169a7e0 .scope module, "mux_0" "bitMultiplexer" 4 29, 4 8 0, S_0x16ba780; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "addr" + .port_info 2 /INPUT 2 "in" +L_0x188bd50/d .functor NOT 1, L_0x188c630, C4<0>, C4<0>, C4<0>; +L_0x188bd50 .delay 1 (10000,10000,10000) L_0x188bd50/d; +L_0x188beb0/d .functor AND 1, L_0x188c0b0, L_0x188bd50, C4<1>, C4<1>; +L_0x188beb0 .delay 1 (20000,20000,20000) L_0x188beb0/d; +L_0x188c210/d .functor AND 1, L_0x188c320, L_0x188c630, C4<1>, C4<1>; +L_0x188c210 .delay 1 (20000,20000,20000) L_0x188c210/d; +L_0x188c4d0/d .functor OR 1, L_0x188beb0, L_0x188c210, C4<0>, C4<0>; +L_0x188c4d0 .delay 1 (20000,20000,20000) L_0x188c4d0/d; +v0x153f140_0 .net *"_s1", 0 0, L_0x188c0b0; 1 drivers +v0x17215c0_0 .net *"_s3", 0 0, L_0x188c320; 1 drivers +v0x1718940_0 .net "addr", 0 0, L_0x188c630; 1 drivers +v0x17015e0_0 .net "in", 1 0, L_0x188c790; 1 drivers +v0x16f89a0_0 .net "naddr", 0 0, L_0x188bd50; 1 drivers +v0x16e1640_0 .net "o0", 0 0, L_0x188beb0; 1 drivers +v0x16d8a00_0 .net "o1", 0 0, L_0x188c210; 1 drivers +v0x16c16a0_0 .net "out", 0 0, L_0x188c4d0; 1 drivers +L_0x188c0b0 .part L_0x188c790, 0, 1; +L_0x188c320 .part L_0x188c790, 1, 1; +S_0x167a840 .scope module, "mux_1" "bitMultiplexer" 4 30, 4 8 0, S_0x16ba780; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "addr" + .port_info 2 /INPUT 2 "in" +L_0x188c830/d .functor NOT 1, L_0x188d020, C4<0>, C4<0>, C4<0>; +L_0x188c830 .delay 1 (10000,10000,10000) L_0x188c830/d; +L_0x188c8f0/d .functor AND 1, L_0x188caa0, L_0x188c830, C4<1>, C4<1>; +L_0x188c8f0 .delay 1 (20000,20000,20000) L_0x188c8f0/d; +L_0x188cc00/d .functor AND 1, L_0x188cd10, L_0x188d020, C4<1>, C4<1>; +L_0x188cc00 .delay 1 (20000,20000,20000) L_0x188cc00/d; +L_0x188cec0/d .functor OR 1, L_0x188c8f0, L_0x188cc00, C4<0>, C4<0>; +L_0x188cec0 .delay 1 (20000,20000,20000) L_0x188cec0/d; +v0x16b8a60_0 .net *"_s1", 0 0, L_0x188caa0; 1 drivers +v0x16a1700_0 .net *"_s3", 0 0, L_0x188cd10; 1 drivers +v0x1698ac0_0 .net "addr", 0 0, L_0x188d020; 1 drivers +v0x1698b60_0 .net "in", 1 0, L_0x188d180; 1 drivers +v0x1681760_0 .net "naddr", 0 0, L_0x188c830; 1 drivers +v0x1678b20_0 .net "o0", 0 0, L_0x188c8f0; 1 drivers +v0x16617c0_0 .net "o1", 0 0, L_0x188cc00; 1 drivers +v0x1658b80_0 .net "out", 0 0, L_0x188cec0; 1 drivers +L_0x188caa0 .part L_0x188d180, 0, 1; +L_0x188cd10 .part L_0x188d180, 1, 1; +S_0x165a8a0 .scope module, "mux_2" "bitMultiplexer" 4 31, 4 8 0, S_0x16ba780; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "addr" + .port_info 2 /INPUT 2 "in" +L_0x188d0c0/d .functor NOT 1, L_0x188d9f0, C4<0>, C4<0>, C4<0>; +L_0x188d0c0 .delay 1 (10000,10000,10000) L_0x188d0c0/d; +L_0x188d270/d .functor AND 1, L_0x188d470, L_0x188d0c0, C4<1>, C4<1>; +L_0x188d270 .delay 1 (20000,20000,20000) L_0x188d270/d; +L_0x188d5d0/d .functor AND 1, L_0x188d6e0, L_0x188d9f0, C4<1>, C4<1>; +L_0x188d5d0 .delay 1 (20000,20000,20000) L_0x188d5d0/d; +L_0x188d890/d .functor OR 1, L_0x188d270, L_0x188d5d0, C4<0>, C4<0>; +L_0x188d890 .delay 1 (20000,20000,20000) L_0x188d890/d; +v0x1641820_0 .net *"_s1", 0 0, L_0x188d470; 1 drivers +v0x1638be0_0 .net *"_s3", 0 0, L_0x188d6e0; 1 drivers +v0x1621890_0 .net "addr", 0 0, L_0x188d9f0; 1 drivers +v0x1621930_0 .net "in", 1 0, L_0x188db50; 1 drivers +v0x1618c50_0 .net "naddr", 0 0, L_0x188d0c0; 1 drivers +v0x1601900_0 .net "o0", 0 0, L_0x188d270; 1 drivers +v0x15f8cc0_0 .net "o1", 0 0, L_0x188d5d0; 1 drivers +v0x15e1960_0 .net "out", 0 0, L_0x188d890; 1 drivers +L_0x188d470 .part L_0x188db50, 0, 1; +L_0x188d6e0 .part L_0x188db50, 1, 1; +S_0x163a900 .scope module, "mux_3" "bitMultiplexer" 4 32, 4 8 0, S_0x16ba780; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "addr" + .port_info 2 /INPUT 2 "in" +L_0x188da90/d .functor NOT 1, L_0x188e650, C4<0>, C4<0>, C4<0>; +L_0x188da90 .delay 1 (10000,10000,10000) L_0x188da90/d; +L_0x188dc80/d .functor AND 1, L_0x188de80, L_0x188da90, C4<1>, C4<1>; +L_0x188dc80 .delay 1 (20000,20000,20000) L_0x188dc80/d; +L_0x188dfe0/d .functor AND 1, L_0x188e0f0, L_0x188e650, C4<1>, C4<1>; +L_0x188dfe0 .delay 1 (20000,20000,20000) L_0x188dfe0/d; +L_0x188e2a0/d .functor OR 1, L_0x188dc80, L_0x188dfe0, C4<0>, C4<0>; +L_0x188e2a0 .delay 1 (20000,20000,20000) L_0x188e2a0/d; +v0x15d8d20_0 .net *"_s1", 0 0, L_0x188de80; 1 drivers +v0x15c19c0_0 .net *"_s3", 0 0, L_0x188e0f0; 1 drivers +v0x15b8d80_0 .net "addr", 0 0, L_0x188e650; 1 drivers +v0x15b8e20_0 .net "in", 1 0, L_0x188e740; 1 drivers +v0x1598d90_0 .net "naddr", 0 0, L_0x188da90; 1 drivers +v0x1591af0_0 .net "o0", 0 0, L_0x188dc80; 1 drivers +v0x1578dd0_0 .net "o1", 0 0, L_0x188dfe0; 1 drivers +v0x1571b30_0 .net "out", 0 0, L_0x188e2a0; 1 drivers +L_0x188de80 .part L_0x188e740, 0, 1; +L_0x188e0f0 .part L_0x188e740, 1, 1; +S_0x161a970 .scope module, "mux_mid_0" "bitMultiplexer" 4 33, 4 8 0, S_0x16ba780; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "addr" + .port_info 2 /INPUT 2 "in" +L_0x188e7e0/d .functor NOT 1, L_0x188ef80, C4<0>, C4<0>, C4<0>; +L_0x188e7e0 .delay 1 (10000,10000,10000) L_0x188e7e0/d; +L_0x188e8a0/d .functor AND 1, L_0x188ea00, L_0x188e7e0, C4<1>, C4<1>; +L_0x188e8a0 .delay 1 (20000,20000,20000) L_0x188e8a0/d; +L_0x188eb60/d .functor AND 1, L_0x188ec70, L_0x188ef80, C4<1>, C4<1>; +L_0x188eb60 .delay 1 (20000,20000,20000) L_0x188eb60/d; +L_0x188ee20/d .functor OR 1, L_0x188e8a0, L_0x188eb60, C4<0>, C4<0>; +L_0x188ee20 .delay 1 (20000,20000,20000) L_0x188ee20/d; +v0x1558e00_0 .net *"_s1", 0 0, L_0x188ea00; 1 drivers +v0x1551b60_0 .net *"_s3", 0 0, L_0x188ec70; 1 drivers +v0x17388e0_0 .net "addr", 0 0, L_0x188ef80; 1 drivers +v0x1738980_0 .net "in", 1 0, L_0x188f0e0; 1 drivers +v0x171ca50_0 .net "naddr", 0 0, L_0x188e7e0; 1 drivers +v0x162d2a0_0 .net "o0", 0 0, L_0x188e8a0; 1 drivers +v0x160d310_0 .net "o1", 0 0, L_0x188eb60; 1 drivers +v0x15ed380_0 .net "out", 0 0, L_0x188ee20; 1 drivers +L_0x188ea00 .part L_0x188f0e0, 0, 1; +L_0x188ec70 .part L_0x188f0e0, 1, 1; +S_0x15fa9e0 .scope module, "mux_mid_1" "bitMultiplexer" 4 34, 4 8 0, S_0x16ba780; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "addr" + .port_info 2 /INPUT 2 "in" +L_0x188f180/d .functor NOT 1, L_0x188fb20, C4<0>, C4<0>, C4<0>; +L_0x188f180 .delay 1 (10000,10000,10000) L_0x188f180/d; +L_0x188f240/d .functor AND 1, L_0x188f3a0, L_0x188f180, C4<1>, C4<1>; +L_0x188f240 .delay 1 (20000,20000,20000) L_0x188f240/d; +L_0x188f500/d .functor AND 1, L_0x188f610, L_0x188fb20, C4<1>, C4<1>; +L_0x188f500 .delay 1 (20000,20000,20000) L_0x188f500/d; +L_0x188f7c0/d .functor OR 1, L_0x188f240, L_0x188f500, C4<0>, C4<0>; +L_0x188f7c0 .delay 1 (20000,20000,20000) L_0x188f7c0/d; +v0x15cd3e0_0 .net *"_s1", 0 0, L_0x188f3a0; 1 drivers +v0x15ad440_0 .net *"_s3", 0 0, L_0x188f610; 1 drivers +v0x158d460_0 .net "addr", 0 0, L_0x188fb20; 1 drivers +v0x158d500_0 .net "in", 1 0, L_0x188fbc0; 1 drivers +v0x156d4a0_0 .net "naddr", 0 0, L_0x188f180; 1 drivers +v0x172cfd0_0 .net "o0", 0 0, L_0x188f240; 1 drivers +v0x172d090_0 .net "o1", 0 0, L_0x188f500; 1 drivers +v0x171d650_0 .net "out", 0 0, L_0x188f7c0; 1 drivers +L_0x188f3a0 .part L_0x188fbc0, 0, 1; +L_0x188f610 .part L_0x188fbc0, 1, 1; +S_0x15daa40 .scope module, "mux_out" "bitMultiplexer" 4 35, 4 8 0, S_0x16ba780; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "addr" + .port_info 2 /INPUT 2 "in" +L_0x188f020/d .functor NOT 1, L_0x1890400, C4<0>, C4<0>, C4<0>; +L_0x188f020 .delay 1 (10000,10000,10000) L_0x188f020/d; +L_0x188fd30/d .functor AND 1, L_0x188fe90, L_0x188f020, C4<1>, C4<1>; +L_0x188fd30 .delay 1 (20000,20000,20000) L_0x188fd30/d; +L_0x188fff0/d .functor AND 1, L_0x1890100, L_0x1890400, C4<1>, C4<1>; +L_0x188fff0 .delay 1 (20000,20000,20000) L_0x188fff0/d; +L_0x18902f0/d .functor OR 1, L_0x188fd30, L_0x188fff0, C4<0>, C4<0>; +L_0x18902f0 .delay 1 (20000,20000,20000) L_0x18902f0/d; +v0x171ae20_0 .net *"_s1", 0 0, L_0x188fe90; 1 drivers +v0x171aee0_0 .net *"_s3", 0 0, L_0x1890100; 1 drivers +v0x17191d0_0 .net "addr", 0 0, L_0x1890400; 1 drivers +v0x1719270_0 .net "in", 1 0, L_0x188f920; alias, 1 drivers +v0x1717480_0 .net "naddr", 0 0, L_0x188f020; 1 drivers +v0x17159d0_0 .net "o0", 0 0, L_0x188fd30; 1 drivers +v0x1715a90_0 .net "o1", 0 0, L_0x188fff0; 1 drivers +v0x1713cb0_0 .net "out", 0 0, L_0x18902f0; alias, 1 drivers +L_0x188fe90 .part L_0x188f920, 0, 1; +L_0x1890100 .part L_0x188f920, 1, 1; +S_0x15baaa0 .scope module, "structadder" "structAddSub" 3 22, 5 8 0, S_0x16da720; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "sub" + .port_info 5 /INPUT 1 "carryin" +L_0x188a7c0/d .functor XOR 1, L_0x18359c0, v0x17dbbc0_0, C4<0>, C4<0>; +L_0x188a7c0 .delay 1 (20000,20000,20000) L_0x188a7c0/d; +L_0x1886bc0/d .functor XOR 1, L_0x188b0a0, L_0x18359c0, C4<0>, C4<0>; +L_0x1886bc0 .delay 1 (20000,20000,20000) L_0x1886bc0/d; +L_0x18302d0/d .functor XOR 1, L_0x1886bc0, L_0x7fc2cd8a5018, C4<0>, C4<0>; +L_0x18302d0 .delay 1 (20000,20000,20000) L_0x18302d0/d; +L_0x1885070/d .functor AND 1, L_0x188b0a0, L_0x18359c0, C4<1>, C4<1>; +L_0x1885070 .delay 1 (20000,20000,20000) L_0x1885070/d; +L_0x18851d0/d .functor AND 1, L_0x1886bc0, L_0x7fc2cd8a5018, C4<1>, C4<1>; +L_0x18851d0 .delay 1 (20000,20000,20000) L_0x18851d0/d; +L_0x188b560/d .functor OR 1, L_0x18851d0, L_0x1885070, C4<0>, C4<0>; +L_0x188b560 .delay 1 (20000,20000,20000) L_0x188b560/d; +v0x16f7580_0 .net "AandB", 0 0, L_0x1885070; 1 drivers +v0x16f5a30_0 .net "AxorB", 0 0, L_0x1886bc0; 1 drivers +v0x16f5ad0_0 .net "AxorBandCarryIn", 0 0, L_0x18851d0; 1 drivers +v0x16f3d10_0 .net "a", 0 0, L_0x188b0a0; alias, 1 drivers +v0x16f3db0_0 .net "b", 0 0, L_0x18359c0; alias, 1 drivers +v0x16ed090_0 .net "bnew", 0 0, L_0x188a7c0; 1 drivers +v0x16ed150_0 .net "carryin", 0 0, L_0x7fc2cd8a5018; alias, 1 drivers +v0x16dd710_0 .net "carryout", 0 0, L_0x188b560; alias, 1 drivers +v0x16dd7d0_0 .net "sub", 0 0, v0x17dbbc0_0; alias, 1 drivers +v0x16daee0_0 .net "sum", 0 0, L_0x18302d0; 1 drivers +S_0x159aab0 .scope generate, "ripple[1]" "ripple[1]" 3 66, 3 66 0, S_0x16fa6c0; + .timescale -9 -12; +P_0x1578e90 .param/l "i" 0 3 66, +C4<01>; +S_0x157aaf0 .scope module, "bit" "BitSliceALU" 3 68, 3 11 0, S_0x159aab0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "ALUout" + .port_info 1 /OUTPUT 1 "Cout" + .port_info 2 /INPUT 1 "invertB" + .port_info 3 /INPUT 1 "Cin" + .port_info 4 /INPUT 3 "addr" + .port_info 5 /INPUT 1 "bit1" + .port_info 6 /INPUT 1 "bit2" +L_0x17dcec0/d .functor XOR 1, L_0x17e1da0, L_0x17e1e40, C4<0>, C4<0>; +L_0x17dcec0 .delay 1 (20000,20000,20000) L_0x17dcec0/d; +L_0x17dd020/d .functor NAND 1, L_0x17e1da0, L_0x17e1e40, C4<1>, C4<1>; +L_0x17dd020 .delay 1 (10000,10000,10000) L_0x17dd020/d; +L_0x17dd180/d .functor XOR 1, v0x17dbbc0_0, L_0x17dd020, C4<0>, C4<0>; +L_0x17dd180 .delay 1 (20000,20000,20000) L_0x17dd180/d; +L_0x17dd2e0/d .functor NOR 1, L_0x17e1da0, L_0x17e1e40, C4<0>, C4<0>; +L_0x17dd2e0 .delay 1 (10000,10000,10000) L_0x17dd2e0/d; +L_0x17dd440/d .functor XOR 1, v0x17dbbc0_0, L_0x17dd2e0, C4<0>, C4<0>; +L_0x17dd440 .delay 1 (20000,20000,20000) L_0x17dd440/d; +v0x15d4090_0 .net "ALUout", 0 0, L_0x17e1a00; 1 drivers +v0x15bda30_0 .net "Cin", 0 0, L_0x17e1c70; 1 drivers +v0x15bdaf0_0 .net "Cout", 0 0, L_0x17dcd10; 1 drivers +v0x15b23a0_0 .net *"_s11", 0 0, L_0x17dd440; 1 drivers +o0x7fc2cd90d7a8 .functor BUFZ 1, C4; HiZ drive +; Elide local net with no drivers, v0x15b2440_0 name=_s15 +o0x7fc2cd90d7d8 .functor BUFZ 3, C4; HiZ drive +; Elide local net with no drivers, v0x15bb260_0 name=_s17 +v0x15bb320_0 .net *"_s3", 0 0, L_0x17dcec0; 1 drivers +v0x15b9650_0 .net *"_s7", 0 0, L_0x17dd180; 1 drivers +v0x15b78c0_0 .net "addr", 2 0, v0x17dbc90_0; alias, 1 drivers +v0x15b5e10_0 .net "bit1", 0 0, L_0x17e1da0; 1 drivers +v0x15b5eb0_0 .net "bit2", 0 0, L_0x17e1e40; 1 drivers +v0x15b40f0_0 .net "invertB", 0 0, v0x17dbbc0_0; alias, 1 drivers +v0x15b4190_0 .net "nanded", 0 0, L_0x17dd020; 1 drivers +v0x159da40_0 .net "nored", 0 0, L_0x17dd2e0; 1 drivers +v0x159dae0_0 .net "out", 7 0, L_0x18919b0; 1 drivers +LS_0x18919b0_0_0 .concat [ 1 1 1 1], L_0x17dc8a0, L_0x17dcec0, o0x7fc2cd90d7a8, L_0x17dd180; +LS_0x18919b0_0_4 .concat [ 1 3 0 0], L_0x17dd440, o0x7fc2cd90d7d8; +L_0x18919b0 .concat [ 4 4 0 0], LS_0x18919b0_0_0, LS_0x18919b0_0_4; +S_0x155ab20 .scope module, "opmux" "structuralMultiplexer" 3 43, 4 21 0, S_0x157aaf0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 3 "address" + .port_info 2 /INPUT 8 "in" +v0x15f9550_0 .net "address", 2 0, v0x17dbc90_0; alias, 1 drivers +v0x15f7800_0 .net "in", 7 0, L_0x18919b0; alias, 1 drivers +v0x15f5d50_0 .net "mux", 3 0, L_0x17dfb10; 1 drivers +v0x15f5e10_0 .net "muxmid", 1 0, L_0x17e1030; 1 drivers +v0x15f4030_0 .net "out", 0 0, L_0x17e1a00; alias, 1 drivers +L_0x17dde30 .part v0x17dbc90_0, 0, 1; +L_0x17ddf90 .part L_0x18919b0, 0, 2; +L_0x17de7d0 .part v0x17dbc90_0, 0, 1; +L_0x17de930 .part L_0x18919b0, 2, 2; +L_0x17df1a0 .part v0x17dbc90_0, 0, 1; +L_0x17df300 .part L_0x18919b0, 4, 2; +L_0x17dfb10 .concat8 [ 1 1 1 1], L_0x17ddcd0, L_0x17de670, L_0x17df040, L_0x17df9b0; +L_0x17dfd60 .part v0x17dbc90_0, 0, 1; +L_0x17dfe50 .part L_0x18919b0, 6, 2; +L_0x17e0690 .part v0x17dbc90_0, 1, 1; +L_0x17e07f0 .part L_0x17dfb10, 0, 2; +L_0x17e1030 .concat8 [ 1 1 0 0], L_0x17e0530, L_0x17e0ed0; +L_0x17e1230 .part v0x17dbc90_0, 1, 1; +L_0x17e12d0 .part L_0x17dfb10, 2, 2; +L_0x17e1b10 .part v0x17dbc90_0, 2, 1; +S_0x173a600 .scope module, "mux_0" "bitMultiplexer" 4 29, 4 8 0, S_0x155ab20; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "addr" + .port_info 2 /INPUT 2 "in" +L_0x17dd550/d .functor NOT 1, L_0x17dde30, C4<0>, C4<0>, C4<0>; +L_0x17dd550 .delay 1 (10000,10000,10000) L_0x17dd550/d; +L_0x17dd6b0/d .functor AND 1, L_0x17dd8b0, L_0x17dd550, C4<1>, C4<1>; +L_0x17dd6b0 .delay 1 (20000,20000,20000) L_0x17dd6b0/d; +L_0x17dda10/d .functor AND 1, L_0x17ddb20, L_0x17dde30, C4<1>, C4<1>; +L_0x17dda10 .delay 1 (20000,20000,20000) L_0x17dda10/d; +L_0x17ddcd0/d .functor OR 1, L_0x17dd6b0, L_0x17dda10, C4<0>, C4<0>; +L_0x17ddcd0 .delay 1 (20000,20000,20000) L_0x17ddcd0/d; +v0x16ad150_0 .net *"_s1", 0 0, L_0x17dd8b0; 1 drivers +v0x169d7d0_0 .net *"_s3", 0 0, L_0x17ddb20; 1 drivers +v0x169afa0_0 .net "addr", 0 0, L_0x17dde30; 1 drivers +v0x169b040_0 .net "in", 1 0, L_0x17ddf90; 1 drivers +v0x1699350_0 .net "naddr", 0 0, L_0x17dd550; 1 drivers +v0x1697600_0 .net "o0", 0 0, L_0x17dd6b0; 1 drivers +v0x16976c0_0 .net "o1", 0 0, L_0x17dda10; 1 drivers +v0x1695b50_0 .net "out", 0 0, L_0x17ddcd0; 1 drivers +L_0x17dd8b0 .part L_0x17ddf90, 0, 1; +L_0x17ddb20 .part L_0x17ddf90, 1, 1; +S_0x172c510 .scope module, "mux_1" "bitMultiplexer" 4 30, 4 8 0, S_0x155ab20; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "addr" + .port_info 2 /INPUT 2 "in" +L_0x17de030/d .functor NOT 1, L_0x17de7d0, C4<0>, C4<0>, C4<0>; +L_0x17de030 .delay 1 (10000,10000,10000) L_0x17de030/d; +L_0x17de0f0/d .functor AND 1, L_0x17de250, L_0x17de030, C4<1>, C4<1>; +L_0x17de0f0 .delay 1 (20000,20000,20000) L_0x17de0f0/d; +L_0x17de3b0/d .functor AND 1, L_0x17de4c0, L_0x17de7d0, C4<1>, C4<1>; +L_0x17de3b0 .delay 1 (20000,20000,20000) L_0x17de3b0/d; +L_0x17de670/d .functor OR 1, L_0x17de0f0, L_0x17de3b0, C4<0>, C4<0>; +L_0x17de670 .delay 1 (20000,20000,20000) L_0x17de670/d; +v0x1693e30_0 .net *"_s1", 0 0, L_0x17de250; 1 drivers +v0x168d1b0_0 .net *"_s3", 0 0, L_0x17de4c0; 1 drivers +v0x167d830_0 .net "addr", 0 0, L_0x17de7d0; 1 drivers +v0x167d8d0_0 .net "in", 1 0, L_0x17de930; 1 drivers +v0x1672140_0 .net "naddr", 0 0, L_0x17de030; 1 drivers +v0x167b000_0 .net "o0", 0 0, L_0x17de0f0; 1 drivers +v0x167b0c0_0 .net "o1", 0 0, L_0x17de3b0; 1 drivers +v0x16793b0_0 .net "out", 0 0, L_0x17de670; 1 drivers +L_0x17de250 .part L_0x17de930, 0, 1; +L_0x17de4c0 .part L_0x17de930, 1, 1; +S_0x17291b0 .scope module, "mux_2" "bitMultiplexer" 4 31, 4 8 0, S_0x155ab20; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "addr" + .port_info 2 /INPUT 2 "in" +L_0x17de870/d .functor NOT 1, L_0x17df1a0, C4<0>, C4<0>, C4<0>; +L_0x17de870 .delay 1 (10000,10000,10000) L_0x17de870/d; +L_0x17dea20/d .functor AND 1, L_0x17dec20, L_0x17de870, C4<1>, C4<1>; +L_0x17dea20 .delay 1 (20000,20000,20000) L_0x17dea20/d; +L_0x17ded80/d .functor AND 1, L_0x17dee90, L_0x17df1a0, C4<1>, C4<1>; +L_0x17ded80 .delay 1 (20000,20000,20000) L_0x17ded80/d; +L_0x17df040/d .functor OR 1, L_0x17dea20, L_0x17ded80, C4<0>, C4<0>; +L_0x17df040 .delay 1 (20000,20000,20000) L_0x17df040/d; +v0x1677660_0 .net *"_s1", 0 0, L_0x17dec20; 1 drivers +v0x1675bb0_0 .net *"_s3", 0 0, L_0x17dee90; 1 drivers +v0x1673e90_0 .net "addr", 0 0, L_0x17df1a0; 1 drivers +v0x1673f30_0 .net "in", 1 0, L_0x17df300; 1 drivers +v0x166d210_0 .net "naddr", 0 0, L_0x17de870; 1 drivers +v0x165d890_0 .net "o0", 0 0, L_0x17dea20; 1 drivers +v0x165d950_0 .net "o1", 0 0, L_0x17ded80; 1 drivers +v0x16521a0_0 .net "out", 0 0, L_0x17df040; 1 drivers +L_0x17dec20 .part L_0x17df300, 0, 1; +L_0x17dee90 .part L_0x17df300, 1, 1; +S_0x170c570 .scope module, "mux_3" "bitMultiplexer" 4 32, 4 8 0, S_0x155ab20; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "addr" + .port_info 2 /INPUT 2 "in" +L_0x17df240/d .functor NOT 1, L_0x17dfd60, C4<0>, C4<0>, C4<0>; +L_0x17df240 .delay 1 (10000,10000,10000) L_0x17df240/d; +L_0x17df430/d .functor AND 1, L_0x17df590, L_0x17df240, C4<1>, C4<1>; +L_0x17df430 .delay 1 (20000,20000,20000) L_0x17df430/d; +L_0x17df6f0/d .functor AND 1, L_0x17df800, L_0x17dfd60, C4<1>, C4<1>; +L_0x17df6f0 .delay 1 (20000,20000,20000) L_0x17df6f0/d; +L_0x17df9b0/d .functor OR 1, L_0x17df430, L_0x17df6f0, C4<0>, C4<0>; +L_0x17df9b0 .delay 1 (20000,20000,20000) L_0x17df9b0/d; +v0x165b060_0 .net *"_s1", 0 0, L_0x17df590; 1 drivers +v0x1659410_0 .net *"_s3", 0 0, L_0x17df800; 1 drivers +v0x16576c0_0 .net "addr", 0 0, L_0x17dfd60; 1 drivers +v0x1657760_0 .net "in", 1 0, L_0x17dfe50; 1 drivers +v0x1655c10_0 .net "naddr", 0 0, L_0x17df240; 1 drivers +v0x1653ef0_0 .net "o0", 0 0, L_0x17df430; 1 drivers +v0x1653fb0_0 .net "o1", 0 0, L_0x17df6f0; 1 drivers +v0x164d270_0 .net "out", 0 0, L_0x17df9b0; 1 drivers +L_0x17df590 .part L_0x17dfe50, 0, 1; +L_0x17df800 .part L_0x17dfe50, 1, 1; +S_0x1709210 .scope module, "mux_mid_0" "bitMultiplexer" 4 33, 4 8 0, S_0x155ab20; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "addr" + .port_info 2 /INPUT 2 "in" +L_0x17dfef0/d .functor NOT 1, L_0x17e0690, C4<0>, C4<0>, C4<0>; +L_0x17dfef0 .delay 1 (10000,10000,10000) L_0x17dfef0/d; +L_0x17dffb0/d .functor AND 1, L_0x17e0110, L_0x17dfef0, C4<1>, C4<1>; +L_0x17dffb0 .delay 1 (20000,20000,20000) L_0x17dffb0/d; +L_0x17e0270/d .functor AND 1, L_0x17e0380, L_0x17e0690, C4<1>, C4<1>; +L_0x17e0270 .delay 1 (20000,20000,20000) L_0x17e0270/d; +L_0x17e0530/d .functor OR 1, L_0x17dffb0, L_0x17e0270, C4<0>, C4<0>; +L_0x17e0530 .delay 1 (20000,20000,20000) L_0x17e0530/d; +v0x163d8f0_0 .net *"_s1", 0 0, L_0x17e0110; 1 drivers +v0x1632200_0 .net *"_s3", 0 0, L_0x17e0380; 1 drivers +v0x163b0c0_0 .net "addr", 0 0, L_0x17e0690; 1 drivers +v0x163b160_0 .net "in", 1 0, L_0x17e07f0; 1 drivers +v0x1639470_0 .net "naddr", 0 0, L_0x17dfef0; 1 drivers +v0x1637720_0 .net "o0", 0 0, L_0x17dffb0; 1 drivers +v0x16377e0_0 .net "o1", 0 0, L_0x17e0270; 1 drivers +v0x1635c70_0 .net "out", 0 0, L_0x17e0530; 1 drivers +L_0x17e0110 .part L_0x17e07f0, 0, 1; +L_0x17e0380 .part L_0x17e07f0, 1, 1; +S_0x16ec5d0 .scope module, "mux_mid_1" "bitMultiplexer" 4 34, 4 8 0, S_0x155ab20; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "addr" + .port_info 2 /INPUT 2 "in" +L_0x17e0890/d .functor NOT 1, L_0x17e1230, C4<0>, C4<0>, C4<0>; +L_0x17e0890 .delay 1 (10000,10000,10000) L_0x17e0890/d; +L_0x17e0950/d .functor AND 1, L_0x17e0ab0, L_0x17e0890, C4<1>, C4<1>; +L_0x17e0950 .delay 1 (20000,20000,20000) L_0x17e0950/d; +L_0x17e0c10/d .functor AND 1, L_0x17e0d20, L_0x17e1230, C4<1>, C4<1>; +L_0x17e0c10 .delay 1 (20000,20000,20000) L_0x17e0c10/d; +L_0x17e0ed0/d .functor OR 1, L_0x17e0950, L_0x17e0c10, C4<0>, C4<0>; +L_0x17e0ed0 .delay 1 (20000,20000,20000) L_0x17e0ed0/d; +v0x1633f50_0 .net *"_s1", 0 0, L_0x17e0ab0; 1 drivers +v0x161d900_0 .net *"_s3", 0 0, L_0x17e0d20; 1 drivers +v0x1612270_0 .net "addr", 0 0, L_0x17e1230; 1 drivers +v0x1612310_0 .net "in", 1 0, L_0x17e12d0; 1 drivers +v0x161b130_0 .net "naddr", 0 0, L_0x17e0890; 1 drivers +v0x16194e0_0 .net "o0", 0 0, L_0x17e0950; 1 drivers +v0x16195a0_0 .net "o1", 0 0, L_0x17e0c10; 1 drivers +v0x1617790_0 .net "out", 0 0, L_0x17e0ed0; 1 drivers +L_0x17e0ab0 .part L_0x17e12d0, 0, 1; +L_0x17e0d20 .part L_0x17e12d0, 1, 1; +S_0x16e9270 .scope module, "mux_out" "bitMultiplexer" 4 35, 4 8 0, S_0x155ab20; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "addr" + .port_info 2 /INPUT 2 "in" +L_0x17e0730/d .functor NOT 1, L_0x17e1b10, C4<0>, C4<0>, C4<0>; +L_0x17e0730 .delay 1 (10000,10000,10000) L_0x17e0730/d; +L_0x17e1440/d .functor AND 1, L_0x17e15a0, L_0x17e0730, C4<1>, C4<1>; +L_0x17e1440 .delay 1 (20000,20000,20000) L_0x17e1440/d; +L_0x17e1700/d .functor AND 1, L_0x17e1810, L_0x17e1b10, C4<1>, C4<1>; +L_0x17e1700 .delay 1 (20000,20000,20000) L_0x17e1700/d; +L_0x17e1a00/d .functor OR 1, L_0x17e1440, L_0x17e1700, C4<0>, C4<0>; +L_0x17e1a00 .delay 1 (20000,20000,20000) L_0x17e1a00/d; +v0x1615ce0_0 .net *"_s1", 0 0, L_0x17e15a0; 1 drivers +v0x1615da0_0 .net *"_s3", 0 0, L_0x17e1810; 1 drivers +v0x1613fc0_0 .net "addr", 0 0, L_0x17e1b10; 1 drivers +v0x1614060_0 .net "in", 1 0, L_0x17e1030; alias, 1 drivers +v0x15fd970_0 .net "naddr", 0 0, L_0x17e0730; 1 drivers +v0x15f22e0_0 .net "o0", 0 0, L_0x17e1440; 1 drivers +v0x15f23a0_0 .net "o1", 0 0, L_0x17e1700; 1 drivers +v0x15fb1a0_0 .net "out", 0 0, L_0x17e1a00; alias, 1 drivers +L_0x17e15a0 .part L_0x17e1030, 0, 1; +L_0x17e1810 .part L_0x17e1030, 1, 1; +S_0x16cc630 .scope module, "structadder" "structAddSub" 3 22, 5 8 0, S_0x157aaf0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "sub" + .port_info 5 /INPUT 1 "carryin" +L_0x17dc650/d .functor XOR 1, L_0x17e1e40, v0x17dbbc0_0, C4<0>, C4<0>; +L_0x17dc650 .delay 1 (20000,20000,20000) L_0x17dc650/d; +L_0x17dc740/d .functor XOR 1, L_0x17e1da0, L_0x17e1e40, C4<0>, C4<0>; +L_0x17dc740 .delay 1 (20000,20000,20000) L_0x17dc740/d; +L_0x17dc8a0/d .functor XOR 1, L_0x17dc740, L_0x17e1c70, C4<0>, C4<0>; +L_0x17dc8a0 .delay 1 (20000,20000,20000) L_0x17dc8a0/d; +L_0x17dca50/d .functor AND 1, L_0x17e1da0, L_0x17e1e40, C4<1>, C4<1>; +L_0x17dca50 .delay 1 (20000,20000,20000) L_0x17dca50/d; +L_0x17dcbb0/d .functor AND 1, L_0x17dc740, L_0x17e1c70, C4<1>, C4<1>; +L_0x17dcbb0 .delay 1 (20000,20000,20000) L_0x17dcbb0/d; +L_0x17dcd10/d .functor OR 1, L_0x17dcbb0, L_0x17dca50, C4<0>, C4<0>; +L_0x17dcd10 .delay 1 (20000,20000,20000) L_0x17dcd10/d; +v0x15dda70_0 .net "AandB", 0 0, L_0x17dca50; 1 drivers +v0x15d2340_0 .net "AxorB", 0 0, L_0x17dc740; 1 drivers +v0x15d23e0_0 .net "AxorBandCarryIn", 0 0, L_0x17dcbb0; 1 drivers +v0x15db200_0 .net "a", 0 0, L_0x17e1da0; alias, 1 drivers +v0x15db2a0_0 .net "b", 0 0, L_0x17e1e40; alias, 1 drivers +v0x15d95b0_0 .net "bnew", 0 0, L_0x17dc650; 1 drivers +v0x15d9670_0 .net "carryin", 0 0, L_0x17e1c70; alias, 1 drivers +v0x15d7860_0 .net "carryout", 0 0, L_0x17dcd10; alias, 1 drivers +v0x15d7920_0 .net "sub", 0 0, v0x17dbbc0_0; alias, 1 drivers +v0x15d5e40_0 .net "sum", 0 0, L_0x17dc8a0; 1 drivers +S_0x16c92d0 .scope generate, "ripple[2]" "ripple[2]" 3 66, 3 66 0, S_0x16fa6c0; + .timescale -9 -12; +P_0x1592430 .param/l "i" 0 3 66, +C4<010>; +S_0x16ac690 .scope module, "bit" "BitSliceALU" 3 68, 3 11 0, S_0x16c92d0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "ALUout" + .port_info 1 /OUTPUT 1 "Cout" + .port_info 2 /INPUT 1 "invertB" + .port_info 3 /INPUT 1 "Cin" + .port_info 4 /INPUT 3 "addr" + .port_info 5 /INPUT 1 "bit1" + .port_info 6 /INPUT 1 "bit2" +L_0x17e2810/d .functor XOR 1, L_0x17e74c0, L_0x17e7560, C4<0>, C4<0>; +L_0x17e2810 .delay 1 (20000,20000,20000) L_0x17e2810/d; +L_0x17e2970/d .functor NAND 1, L_0x17e74c0, L_0x17e7560, C4<1>, C4<1>; +L_0x17e2970 .delay 1 (10000,10000,10000) L_0x17e2970/d; +L_0x17e2ad0/d .functor XOR 1, v0x17dbbc0_0, L_0x17e2970, C4<0>, C4<0>; +L_0x17e2ad0 .delay 1 (20000,20000,20000) L_0x17e2ad0/d; +L_0x17e2be0/d .functor NOR 1, L_0x17e74c0, L_0x17e7560, C4<0>, C4<0>; +L_0x17e2be0 .delay 1 (10000,10000,10000) L_0x17e2be0/d; +L_0x17e2d40/d .functor XOR 1, v0x17dbbc0_0, L_0x17e2be0, C4<0>, C4<0>; +L_0x17e2d40 .delay 1 (20000,20000,20000) L_0x17e2d40/d; +v0x1673600_0 .net "ALUout", 0 0, L_0x17e7120; 1 drivers +v0x16736c0_0 .net "Cin", 0 0, L_0x17e7390; 1 drivers +v0x1677040_0 .net "Cout", 0 0, L_0x17e2660; 1 drivers +v0x16770e0_0 .net *"_s11", 0 0, L_0x17e2d40; 1 drivers +o0x7fc2cd90ec78 .functor BUFZ 1, C4; HiZ drive +; Elide local net with no drivers, v0x1675320_0 name=_s15 +o0x7fc2cd90eca8 .functor BUFZ 3, C4; HiZ drive +; Elide local net with no drivers, v0x16753c0_0 name=_s17 +v0x1653660_0 .net *"_s3", 0 0, L_0x17e2810; 1 drivers +v0x16570a0_0 .net *"_s7", 0 0, L_0x17e2ad0; 1 drivers +v0x1655380_0 .net "addr", 2 0, v0x17dbc90_0; alias, 1 drivers +v0x1655440_0 .net "bit1", 0 0, L_0x17e74c0; 1 drivers +v0x16336c0_0 .net "bit2", 0 0, L_0x17e7560; 1 drivers +v0x1633790_0 .net "invertB", 0 0, v0x17dbbc0_0; alias, 1 drivers +v0x1637100_0 .net "nanded", 0 0, L_0x17e2970; 1 drivers +v0x16371a0_0 .net "nored", 0 0, L_0x17e2be0; 1 drivers +v0x16353e0_0 .net "out", 7 0, L_0x1891a50; 1 drivers +LS_0x1891a50_0_0 .concat [ 1 1 1 1], L_0x17e21f0, L_0x17e2810, o0x7fc2cd90ec78, L_0x17e2ad0; +LS_0x1891a50_0_4 .concat [ 1 3 0 0], L_0x17e2d40, o0x7fc2cd90eca8; +L_0x1891a50 .concat [ 4 4 0 0], LS_0x1891a50_0_0, LS_0x1891a50_0_4; +S_0x16a9330 .scope module, "opmux" "structuralMultiplexer" 3 43, 4 21 0, S_0x16ac690; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 3 "address" + .port_info 2 /INPUT 8 "in" +v0x16f51a0_0 .net "address", 2 0, v0x17dbc90_0; alias, 1 drivers +v0x16f5260_0 .net "in", 7 0, L_0x1891a50; alias, 1 drivers +v0x16d34e0_0 .net "mux", 3 0, L_0x17e5280; 1 drivers +v0x16d35a0_0 .net "muxmid", 1 0, L_0x17e6750; 1 drivers +v0x16d6f20_0 .net "out", 0 0, L_0x17e7120; alias, 1 drivers +L_0x17e3640 .part v0x17dbc90_0, 0, 1; +L_0x17e37a0 .part L_0x1891a50, 0, 2; +L_0x17e3fe0 .part v0x17dbc90_0, 0, 1; +L_0x17e4140 .part L_0x1891a50, 2, 2; +L_0x17e4910 .part v0x17dbc90_0, 0, 1; +L_0x17e4a70 .part L_0x1891a50, 4, 2; +L_0x17e5280 .concat8 [ 1 1 1 1], L_0x17e34e0, L_0x17e3e80, L_0x17e47b0, L_0x17e5120; +L_0x17e54d0 .part v0x17dbc90_0, 0, 1; +L_0x17e55c0 .part L_0x1891a50, 6, 2; +L_0x17e5e00 .part v0x17dbc90_0, 1, 1; +L_0x17dea90 .part L_0x17e5280, 0, 2; +L_0x17e6750 .concat8 [ 1 1 0 0], L_0x17e5ca0, L_0x17e65f0; +L_0x17e6950 .part v0x17dbc90_0, 1, 1; +L_0x17e69f0 .part L_0x17e5280, 2, 2; +L_0x17e7230 .part v0x17dbc90_0, 2, 1; +S_0x168c6f0 .scope module, "mux_0" "bitMultiplexer" 4 29, 4 8 0, S_0x16a9330; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "addr" + .port_info 2 /INPUT 2 "in" +L_0x17e2e50/d .functor NOT 1, L_0x17e3640, C4<0>, C4<0>, C4<0>; +L_0x17e2e50 .delay 1 (10000,10000,10000) L_0x17e2e50/d; +L_0x17e2fb0/d .functor AND 1, L_0x17e30c0, L_0x17e2e50, C4<1>, C4<1>; +L_0x17e2fb0 .delay 1 (20000,20000,20000) L_0x17e2fb0/d; +L_0x17e3220/d .functor AND 1, L_0x17e3330, L_0x17e3640, C4<1>, C4<1>; +L_0x17e3220 .delay 1 (20000,20000,20000) L_0x17e3220/d; +L_0x17e34e0/d .functor OR 1, L_0x17e2fb0, L_0x17e3220, C4<0>, C4<0>; +L_0x17e34e0 .delay 1 (20000,20000,20000) L_0x17e34e0/d; +v0x15978d0_0 .net *"_s1", 0 0, L_0x17e30c0; 1 drivers +v0x1595e20_0 .net *"_s3", 0 0, L_0x17e3330; 1 drivers +v0x1594100_0 .net "addr", 0 0, L_0x17e3640; 1 drivers +v0x15941a0_0 .net "in", 1 0, L_0x17e37a0; 1 drivers +v0x157da80_0 .net "naddr", 0 0, L_0x17e2e50; 1 drivers +v0x15723f0_0 .net "o0", 0 0, L_0x17e2fb0; 1 drivers +v0x15724b0_0 .net "o1", 0 0, L_0x17e3220; 1 drivers +v0x157b2b0_0 .net "out", 0 0, L_0x17e34e0; 1 drivers +L_0x17e30c0 .part L_0x17e37a0, 0, 1; +L_0x17e3330 .part L_0x17e37a0, 1, 1; +S_0x1689390 .scope module, "mux_1" "bitMultiplexer" 4 30, 4 8 0, S_0x16a9330; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "addr" + .port_info 2 /INPUT 2 "in" +L_0x17e3840/d .functor NOT 1, L_0x17e3fe0, C4<0>, C4<0>, C4<0>; +L_0x17e3840 .delay 1 (10000,10000,10000) L_0x17e3840/d; +L_0x17e3900/d .functor AND 1, L_0x17e3a60, L_0x17e3840, C4<1>, C4<1>; +L_0x17e3900 .delay 1 (20000,20000,20000) L_0x17e3900/d; +L_0x17e3bc0/d .functor AND 1, L_0x17e3cd0, L_0x17e3fe0, C4<1>, C4<1>; +L_0x17e3bc0 .delay 1 (20000,20000,20000) L_0x17e3bc0/d; +L_0x17e3e80/d .functor OR 1, L_0x17e3900, L_0x17e3bc0, C4<0>, C4<0>; +L_0x17e3e80 .delay 1 (20000,20000,20000) L_0x17e3e80/d; +v0x1579660_0 .net *"_s1", 0 0, L_0x17e3a60; 1 drivers +v0x1577910_0 .net *"_s3", 0 0, L_0x17e3cd0; 1 drivers +v0x1575e60_0 .net "addr", 0 0, L_0x17e3fe0; 1 drivers +v0x1575f00_0 .net "in", 1 0, L_0x17e4140; 1 drivers +v0x1574140_0 .net "naddr", 0 0, L_0x17e3840; 1 drivers +v0x155dab0_0 .net "o0", 0 0, L_0x17e3900; 1 drivers +v0x155db70_0 .net "o1", 0 0, L_0x17e3bc0; 1 drivers +v0x1552420_0 .net "out", 0 0, L_0x17e3e80; 1 drivers +L_0x17e3a60 .part L_0x17e4140, 0, 1; +L_0x17e3cd0 .part L_0x17e4140, 1, 1; +S_0x166c750 .scope module, "mux_2" "bitMultiplexer" 4 31, 4 8 0, S_0x16a9330; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "addr" + .port_info 2 /INPUT 2 "in" +L_0x17e4080/d .functor NOT 1, L_0x17e4910, C4<0>, C4<0>, C4<0>; +L_0x17e4080 .delay 1 (10000,10000,10000) L_0x17e4080/d; +L_0x17e4230/d .functor AND 1, L_0x17e4390, L_0x17e4080, C4<1>, C4<1>; +L_0x17e4230 .delay 1 (20000,20000,20000) L_0x17e4230/d; +L_0x17e44f0/d .functor AND 1, L_0x17e4600, L_0x17e4910, C4<1>, C4<1>; +L_0x17e44f0 .delay 1 (20000,20000,20000) L_0x17e44f0/d; +L_0x17e47b0/d .functor OR 1, L_0x17e4230, L_0x17e44f0, C4<0>, C4<0>; +L_0x17e47b0 .delay 1 (20000,20000,20000) L_0x17e47b0/d; +v0x155b2e0_0 .net *"_s1", 0 0, L_0x17e4390; 1 drivers +v0x1559690_0 .net *"_s3", 0 0, L_0x17e4600; 1 drivers +v0x1557940_0 .net "addr", 0 0, L_0x17e4910; 1 drivers +v0x1555e90_0 .net "in", 1 0, L_0x17e4a70; 1 drivers +v0x1554170_0 .net "naddr", 0 0, L_0x17e4080; 1 drivers +v0x173adc0_0 .net "o0", 0 0, L_0x17e4230; 1 drivers +v0x173ae80_0 .net "o1", 0 0, L_0x17e44f0; 1 drivers +v0x1739170_0 .net "out", 0 0, L_0x17e47b0; 1 drivers +L_0x17e4390 .part L_0x17e4a70, 0, 1; +L_0x17e4600 .part L_0x17e4a70, 1, 1; +S_0x16693f0 .scope module, "mux_3" "bitMultiplexer" 4 32, 4 8 0, S_0x16a9330; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "addr" + .port_info 2 /INPUT 2 "in" +L_0x17e49b0/d .functor NOT 1, L_0x17e54d0, C4<0>, C4<0>, C4<0>; +L_0x17e49b0 .delay 1 (10000,10000,10000) L_0x17e49b0/d; +L_0x17e4ba0/d .functor AND 1, L_0x17e4d00, L_0x17e49b0, C4<1>, C4<1>; +L_0x17e4ba0 .delay 1 (20000,20000,20000) L_0x17e4ba0/d; +L_0x17e4e60/d .functor AND 1, L_0x17e4f70, L_0x17e54d0, C4<1>, C4<1>; +L_0x17e4e60 .delay 1 (20000,20000,20000) L_0x17e4e60/d; +L_0x17e5120/d .functor OR 1, L_0x17e4ba0, L_0x17e4e60, C4<0>, C4<0>; +L_0x17e5120 .delay 1 (20000,20000,20000) L_0x17e5120/d; +v0x1737420_0 .net *"_s1", 0 0, L_0x17e4d00; 1 drivers +v0x1735970_0 .net *"_s3", 0 0, L_0x17e4f70; 1 drivers +v0x1733c50_0 .net "addr", 0 0, L_0x17e54d0; 1 drivers +v0x1733cf0_0 .net "in", 1 0, L_0x17e55c0; 1 drivers +v0x172d2e0_0 .net "naddr", 0 0, L_0x17e49b0; 1 drivers +v0x170d340_0 .net "o0", 0 0, L_0x17e4ba0; 1 drivers +v0x170d400_0 .net "o1", 0 0, L_0x17e4e60; 1 drivers +v0x16ed3a0_0 .net "out", 0 0, L_0x17e5120; 1 drivers +L_0x17e4d00 .part L_0x17e55c0, 0, 1; +L_0x17e4f70 .part L_0x17e55c0, 1, 1; +S_0x164c7b0 .scope module, "mux_mid_0" "bitMultiplexer" 4 33, 4 8 0, S_0x16a9330; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "addr" + .port_info 2 /INPUT 2 "in" +L_0x17e5660/d .functor NOT 1, L_0x17e5e00, C4<0>, C4<0>, C4<0>; +L_0x17e5660 .delay 1 (10000,10000,10000) L_0x17e5660/d; +L_0x17e5720/d .functor AND 1, L_0x17e5880, L_0x17e5660, C4<1>, C4<1>; +L_0x17e5720 .delay 1 (20000,20000,20000) L_0x17e5720/d; +L_0x17e59e0/d .functor AND 1, L_0x17e5af0, L_0x17e5e00, C4<1>, C4<1>; +L_0x17e59e0 .delay 1 (20000,20000,20000) L_0x17e59e0/d; +L_0x17e5ca0/d .functor OR 1, L_0x17e5720, L_0x17e59e0, C4<0>, C4<0>; +L_0x17e5ca0 .delay 1 (20000,20000,20000) L_0x17e5ca0/d; +v0x16cd400_0 .net *"_s1", 0 0, L_0x17e5880; 1 drivers +v0x16ad460_0 .net *"_s3", 0 0, L_0x17e5af0; 1 drivers +v0x168d4c0_0 .net "addr", 0 0, L_0x17e5e00; 1 drivers +v0x168d560_0 .net "in", 1 0, L_0x17dea90; 1 drivers +v0x166d520_0 .net "naddr", 0 0, L_0x17e5660; 1 drivers +v0x164d580_0 .net "o0", 0 0, L_0x17e5720; 1 drivers +v0x164d640_0 .net "o1", 0 0, L_0x17e59e0; 1 drivers +v0x161d270_0 .net "out", 0 0, L_0x17e5ca0; 1 drivers +L_0x17e5880 .part L_0x17dea90, 0, 1; +L_0x17e5af0 .part L_0x17dea90, 1, 1; +S_0x1649450 .scope module, "mux_mid_1" "bitMultiplexer" 4 34, 4 8 0, S_0x16a9330; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "addr" + .port_info 2 /INPUT 2 "in" +L_0x17e5f60/d .functor NOT 1, L_0x17e6950, C4<0>, C4<0>, C4<0>; +L_0x17e5f60 .delay 1 (10000,10000,10000) L_0x17e5f60/d; +L_0x17e6020/d .functor AND 1, L_0x17e61d0, L_0x17e5f60, C4<1>, C4<1>; +L_0x17e6020 .delay 1 (20000,20000,20000) L_0x17e6020/d; +L_0x17e6330/d .functor AND 1, L_0x17e6440, L_0x17e6950, C4<1>, C4<1>; +L_0x17e6330 .delay 1 (20000,20000,20000) L_0x17e6330/d; +L_0x17e65f0/d .functor OR 1, L_0x17e6020, L_0x17e6330, C4<0>, C4<0>; +L_0x17e65f0 .delay 1 (20000,20000,20000) L_0x17e65f0/d; +v0x15fd2e0_0 .net *"_s1", 0 0, L_0x17e61d0; 1 drivers +v0x15dd340_0 .net *"_s3", 0 0, L_0x17e6440; 1 drivers +v0x15bd3a0_0 .net "addr", 0 0, L_0x17e6950; 1 drivers +v0x15bd440_0 .net "in", 1 0, L_0x17e69f0; 1 drivers +v0x159d3b0_0 .net "naddr", 0 0, L_0x17e5f60; 1 drivers +v0x157d3f0_0 .net "o0", 0 0, L_0x17e6020; 1 drivers +v0x157d4b0_0 .net "o1", 0 0, L_0x17e6330; 1 drivers +v0x155d420_0 .net "out", 0 0, L_0x17e65f0; 1 drivers +L_0x17e61d0 .part L_0x17e69f0, 0, 1; +L_0x17e6440 .part L_0x17e69f0, 1, 1; +S_0x162c820 .scope module, "mux_out" "bitMultiplexer" 4 35, 4 8 0, S_0x16a9330; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "addr" + .port_info 2 /INPUT 2 "in" +L_0x17e5ea0/d .functor NOT 1, L_0x17e7230, C4<0>, C4<0>, C4<0>; +L_0x17e5ea0 .delay 1 (10000,10000,10000) L_0x17e5ea0/d; +L_0x17e6b60/d .functor AND 1, L_0x17e6cc0, L_0x17e5ea0, C4<1>, C4<1>; +L_0x17e6b60 .delay 1 (20000,20000,20000) L_0x17e6b60/d; +L_0x17e6e20/d .functor AND 1, L_0x17e6f30, L_0x17e7230, C4<1>, C4<1>; +L_0x17e6e20 .delay 1 (20000,20000,20000) L_0x17e6e20/d; +L_0x17e7120/d .functor OR 1, L_0x17e6b60, L_0x17e6e20, C4<0>, C4<0>; +L_0x17e7120 .delay 1 (20000,20000,20000) L_0x17e7120/d; +v0x1713420_0 .net *"_s1", 0 0, L_0x17e6cc0; 1 drivers +v0x17134e0_0 .net *"_s3", 0 0, L_0x17e6f30; 1 drivers +v0x1716e60_0 .net "addr", 0 0, L_0x17e7230; 1 drivers +v0x1716f00_0 .net "in", 1 0, L_0x17e6750; alias, 1 drivers +v0x1715140_0 .net "naddr", 0 0, L_0x17e5ea0; 1 drivers +v0x16f3480_0 .net "o0", 0 0, L_0x17e6b60; 1 drivers +v0x16f3540_0 .net "o1", 0 0, L_0x17e6e20; 1 drivers +v0x16f6ec0_0 .net "out", 0 0, L_0x17e7120; alias, 1 drivers +L_0x17e6cc0 .part L_0x17e6750, 0, 1; +L_0x17e6f30 .part L_0x17e6750, 1, 1; +S_0x16294c0 .scope module, "structadder" "structAddSub" 3 22, 5 8 0, S_0x16ac690; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "sub" + .port_info 5 /INPUT 1 "carryin" +L_0x17dcac0/d .functor XOR 1, L_0x17e7560, v0x17dbbc0_0, C4<0>, C4<0>; +L_0x17dcac0 .delay 1 (20000,20000,20000) L_0x17dcac0/d; +L_0x17e2090/d .functor XOR 1, L_0x17e74c0, L_0x17e7560, C4<0>, C4<0>; +L_0x17e2090 .delay 1 (20000,20000,20000) L_0x17e2090/d; +L_0x17e21f0/d .functor XOR 1, L_0x17e2090, L_0x17e7390, C4<0>, C4<0>; +L_0x17e21f0 .delay 1 (20000,20000,20000) L_0x17e21f0/d; +L_0x17e23a0/d .functor AND 1, L_0x17e74c0, L_0x17e7560, C4<1>, C4<1>; +L_0x17e23a0 .delay 1 (20000,20000,20000) L_0x17e23a0/d; +L_0x17e2500/d .functor AND 1, L_0x17e2090, L_0x17e7390, C4<1>, C4<1>; +L_0x17e2500 .delay 1 (20000,20000,20000) L_0x17e2500/d; +L_0x17e2660/d .functor OR 1, L_0x17e2500, L_0x17e23a0, C4<0>, C4<0>; +L_0x17e2660 .delay 1 (20000,20000,20000) L_0x17e2660/d; +v0x16d52a0_0 .net "AandB", 0 0, L_0x17e23a0; 1 drivers +v0x16b3540_0 .net "AxorB", 0 0, L_0x17e2090; 1 drivers +v0x16b3600_0 .net "AxorBandCarryIn", 0 0, L_0x17e2500; 1 drivers +v0x16b6f80_0 .net "a", 0 0, L_0x17e74c0; alias, 1 drivers +v0x16b7040_0 .net "b", 0 0, L_0x17e7560; alias, 1 drivers +v0x16b5260_0 .net "bnew", 0 0, L_0x17dcac0; 1 drivers +v0x16b5320_0 .net "carryin", 0 0, L_0x17e7390; alias, 1 drivers +v0x16935a0_0 .net "carryout", 0 0, L_0x17e2660; alias, 1 drivers +v0x1693640_0 .net "sub", 0 0, v0x17dbbc0_0; alias, 1 drivers +v0x16952c0_0 .net "sum", 0 0, L_0x17e21f0; 1 drivers +S_0x160c890 .scope generate, "ripple[3]" "ripple[3]" 3 66, 3 66 0, S_0x16fa6c0; + .timescale -9 -12; +P_0x15dd420 .param/l "i" 0 3 66, +C4<011>; +S_0x1609530 .scope module, "bit" "BitSliceALU" 3 68, 3 11 0, S_0x160c890; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "ALUout" + .port_info 1 /OUTPUT 1 "Cout" + .port_info 2 /INPUT 1 "invertB" + .port_info 3 /INPUT 1 "Cin" + .port_info 4 /INPUT 3 "addr" + .port_info 5 /INPUT 1 "bit1" + .port_info 6 /INPUT 1 "bit2" +L_0x17e7e90/d .functor XOR 1, L_0x17eccd0, L_0x17ece00, C4<0>, C4<0>; +L_0x17e7e90 .delay 1 (20000,20000,20000) L_0x17e7e90/d; +L_0x17e7ff0/d .functor NAND 1, L_0x17eccd0, L_0x17ece00, C4<1>, C4<1>; +L_0x17e7ff0 .delay 1 (10000,10000,10000) L_0x17e7ff0/d; +L_0x17e8150/d .functor XOR 1, v0x17dbbc0_0, L_0x17e7ff0, C4<0>, C4<0>; +L_0x17e8150 .delay 1 (20000,20000,20000) L_0x17e8150/d; +L_0x17e8260/d .functor NOR 1, L_0x17eccd0, L_0x17ece00, C4<0>, C4<0>; +L_0x17e8260 .delay 1 (10000,10000,10000) L_0x17e8260/d; +L_0x17e83c0/d .functor XOR 1, v0x17dbbc0_0, L_0x17e8260, C4<0>, C4<0>; +L_0x17e83c0 .delay 1 (20000,20000,20000) L_0x17e83c0/d; +v0x1718e70_0 .net "ALUout", 0 0, L_0x17ec930; 1 drivers +v0x1718f30_0 .net "Cin", 0 0, L_0x17ecba0; 1 drivers +v0x1715670_0 .net "Cout", 0 0, L_0x17e7ce0; 1 drivers +v0x1715710_0 .net *"_s11", 0 0, L_0x17e83c0; 1 drivers +o0x7fc2cd910148 .functor BUFZ 1, C4; HiZ drive +; Elide local net with no drivers, v0x170d680_0 name=_s15 +o0x7fc2cd910178 .functor BUFZ 3, C4; HiZ drive +; Elide local net with no drivers, v0x170d770_0 name=_s17 +v0x1701b10_0 .net *"_s3", 0 0, L_0x17e7e90; 1 drivers +v0x1701bd0_0 .net *"_s7", 0 0, L_0x17e8150; 1 drivers +v0x16fd390_0 .net "addr", 2 0, v0x17dbc90_0; alias, 1 drivers +v0x16fd020_0 .net "bit1", 0 0, L_0x17eccd0; 1 drivers +v0x16fd0c0_0 .net "bit2", 0 0, L_0x17ece00; 1 drivers +v0x16f39b0_0 .net "invertB", 0 0, v0x17dbbc0_0; alias, 1 drivers +v0x16f3a50_0 .net "nanded", 0 0, L_0x17e7ff0; 1 drivers +v0x16fab20_0 .net "nored", 0 0, L_0x17e8260; 1 drivers +v0x16fabc0_0 .net "out", 7 0, L_0x1891af0; 1 drivers +LS_0x1891af0_0_0 .concat [ 1 1 1 1], L_0x17e7870, L_0x17e7e90, o0x7fc2cd910148, L_0x17e8150; +LS_0x1891af0_0_4 .concat [ 1 3 0 0], L_0x17e83c0, o0x7fc2cd910178; +L_0x1891af0 .concat [ 4 4 0 0], LS_0x1891af0_0_0, LS_0x1891af0_0_4; +S_0x15ec900 .scope module, "opmux" "structuralMultiplexer" 3 43, 4 21 0, S_0x1609530; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 3 "address" + .port_info 2 /INPUT 8 "in" +v0x156ca20_0 .net "address", 2 0, v0x17dbc90_0; alias, 1 drivers +v0x156cae0_0 .net "in", 7 0, L_0x1891af0; alias, 1 drivers +v0x15696c0_0 .net "mux", 3 0, L_0x17eaa40; 1 drivers +v0x1569780_0 .net "muxmid", 1 0, L_0x17ebf60; 1 drivers +v0x154c940_0 .net "out", 0 0, L_0x17ec930; alias, 1 drivers +L_0x17e8cc0 .part v0x17dbc90_0, 0, 1; +L_0x17e8e20 .part L_0x1891af0, 0, 2; +L_0x17e9700 .part v0x17dbc90_0, 0, 1; +L_0x17e9860 .part L_0x1891af0, 2, 2; +L_0x17ea080 .part v0x17dbc90_0, 0, 1; +L_0x17ea1e0 .part L_0x1891af0, 4, 2; +L_0x17eaa40 .concat8 [ 1 1 1 1], L_0x17e8b60, L_0x17e95a0, L_0x17e9f20, L_0x17ea8e0; +L_0x17eac90 .part v0x17dbc90_0, 0, 1; +L_0x17ead80 .part L_0x1891af0, 6, 2; +L_0x17eb5c0 .part v0x17dbc90_0, 1, 1; +L_0x17eb720 .part L_0x17eaa40, 0, 2; +L_0x17ebf60 .concat8 [ 1 1 0 0], L_0x17eb460, L_0x17ebe00; +L_0x17ec160 .part v0x17dbc90_0, 1, 1; +L_0x17ec200 .part L_0x17eaa40, 2, 2; +L_0x17eca40 .part v0x17dbc90_0, 2, 1; +S_0x15e95a0 .scope module, "mux_0" "bitMultiplexer" 4 29, 4 8 0, S_0x15ec900; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "addr" + .port_info 2 /INPUT 2 "in" +L_0x17e84d0/d .functor NOT 1, L_0x17e8cc0, C4<0>, C4<0>, C4<0>; +L_0x17e84d0 .delay 1 (10000,10000,10000) L_0x17e84d0/d; +L_0x17e8630/d .functor AND 1, L_0x17e8740, L_0x17e84d0, C4<1>, C4<1>; +L_0x17e8630 .delay 1 (20000,20000,20000) L_0x17e8630/d; +L_0x17e88a0/d .functor AND 1, L_0x17e89b0, L_0x17e8cc0, C4<1>, C4<1>; +L_0x17e88a0 .delay 1 (20000,20000,20000) L_0x17e88a0/d; +L_0x17e8b60/d .functor OR 1, L_0x17e8630, L_0x17e88a0, C4<0>, C4<0>; +L_0x17e8b60 .delay 1 (20000,20000,20000) L_0x17e8b60/d; +v0x1615450_0 .net *"_s1", 0 0, L_0x17e8740; 1 drivers +v0x15f37a0_0 .net *"_s3", 0 0, L_0x17e89b0; 1 drivers +v0x15f71e0_0 .net "addr", 0 0, L_0x17e8cc0; 1 drivers +v0x15f72b0_0 .net "in", 1 0, L_0x17e8e20; 1 drivers +v0x15f54c0_0 .net "naddr", 0 0, L_0x17e84d0; 1 drivers +v0x15d3800_0 .net "o0", 0 0, L_0x17e8630; 1 drivers +v0x15d38c0_0 .net "o1", 0 0, L_0x17e88a0; 1 drivers +v0x15d7240_0 .net "out", 0 0, L_0x17e8b60; 1 drivers +L_0x17e8740 .part L_0x17e8e20, 0, 1; +L_0x17e89b0 .part L_0x17e8e20, 1, 1; +S_0x15cc960 .scope module, "mux_1" "bitMultiplexer" 4 30, 4 8 0, S_0x15ec900; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "addr" + .port_info 2 /INPUT 2 "in" +L_0x17e8ec0/d .functor NOT 1, L_0x17e9700, C4<0>, C4<0>, C4<0>; +L_0x17e8ec0 .delay 1 (10000,10000,10000) L_0x17e8ec0/d; +L_0x17e8f80/d .functor AND 1, L_0x17e9180, L_0x17e8ec0, C4<1>, C4<1>; +L_0x17e8f80 .delay 1 (20000,20000,20000) L_0x17e8f80/d; +L_0x17e92e0/d .functor AND 1, L_0x17e93f0, L_0x17e9700, C4<1>, C4<1>; +L_0x17e92e0 .delay 1 (20000,20000,20000) L_0x17e92e0/d; +L_0x17e95a0/d .functor OR 1, L_0x17e8f80, L_0x17e92e0, C4<0>, C4<0>; +L_0x17e95a0 .delay 1 (20000,20000,20000) L_0x17e95a0/d; +v0x15d5520_0 .net *"_s1", 0 0, L_0x17e9180; 1 drivers +v0x15b3860_0 .net *"_s3", 0 0, L_0x17e93f0; 1 drivers +v0x15b72a0_0 .net "addr", 0 0, L_0x17e9700; 1 drivers +v0x15b7340_0 .net "in", 1 0, L_0x17e9860; 1 drivers +v0x15b5580_0 .net "naddr", 0 0, L_0x17e8ec0; 1 drivers +v0x1593870_0 .net "o0", 0 0, L_0x17e8f80; 1 drivers +v0x1593930_0 .net "o1", 0 0, L_0x17e92e0; 1 drivers +v0x15972b0_0 .net "out", 0 0, L_0x17e95a0; 1 drivers +L_0x17e9180 .part L_0x17e9860, 0, 1; +L_0x17e93f0 .part L_0x17e9860, 1, 1; +S_0x15c9600 .scope module, "mux_2" "bitMultiplexer" 4 31, 4 8 0, S_0x15ec900; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "addr" + .port_info 2 /INPUT 2 "in" +L_0x17e97a0/d .functor NOT 1, L_0x17ea080, C4<0>, C4<0>, C4<0>; +L_0x17e97a0 .delay 1 (10000,10000,10000) L_0x17e97a0/d; +L_0x17e9950/d .functor AND 1, L_0x17e9b00, L_0x17e97a0, C4<1>, C4<1>; +L_0x17e9950 .delay 1 (20000,20000,20000) L_0x17e9950/d; +L_0x17e9c60/d .functor AND 1, L_0x17e9d70, L_0x17ea080, C4<1>, C4<1>; +L_0x17e9c60 .delay 1 (20000,20000,20000) L_0x17e9c60/d; +L_0x17e9f20/d .functor OR 1, L_0x17e9950, L_0x17e9c60, C4<0>, C4<0>; +L_0x17e9f20 .delay 1 (20000,20000,20000) L_0x17e9f20/d; +v0x1595590_0 .net *"_s1", 0 0, L_0x17e9b00; 1 drivers +v0x1595650_0 .net *"_s3", 0 0, L_0x17e9d70; 1 drivers +v0x15738b0_0 .net "addr", 0 0, L_0x17ea080; 1 drivers +v0x15772f0_0 .net "in", 1 0, L_0x17ea1e0; 1 drivers +v0x15755d0_0 .net "naddr", 0 0, L_0x17e97a0; 1 drivers +v0x15538e0_0 .net "o0", 0 0, L_0x17e9950; 1 drivers +v0x15539a0_0 .net "o1", 0 0, L_0x17e9c60; 1 drivers +v0x1557320_0 .net "out", 0 0, L_0x17e9f20; 1 drivers +L_0x17e9b00 .part L_0x17ea1e0, 0, 1; +L_0x17e9d70 .part L_0x17ea1e0, 1, 1; +S_0x15ac9c0 .scope module, "mux_3" "bitMultiplexer" 4 32, 4 8 0, S_0x15ec900; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "addr" + .port_info 2 /INPUT 2 "in" +L_0x17ea120/d .functor NOT 1, L_0x17eac90, C4<0>, C4<0>, C4<0>; +L_0x17ea120 .delay 1 (10000,10000,10000) L_0x17ea120/d; +L_0x17ea310/d .functor AND 1, L_0x17ea4c0, L_0x17ea120, C4<1>, C4<1>; +L_0x17ea310 .delay 1 (20000,20000,20000) L_0x17ea310/d; +L_0x17ea620/d .functor AND 1, L_0x17ea730, L_0x17eac90, C4<1>, C4<1>; +L_0x17ea620 .delay 1 (20000,20000,20000) L_0x17ea620/d; +L_0x17ea8e0/d .functor OR 1, L_0x17ea310, L_0x17ea620, C4<0>, C4<0>; +L_0x17ea8e0 .delay 1 (20000,20000,20000) L_0x17ea8e0/d; +v0x1555600_0 .net *"_s1", 0 0, L_0x17ea4c0; 1 drivers +v0x17333c0_0 .net *"_s3", 0 0, L_0x17ea730; 1 drivers +v0x1736e00_0 .net "addr", 0 0, L_0x17eac90; 1 drivers +v0x1736ea0_0 .net "in", 1 0, L_0x17ead80; 1 drivers +v0x17350e0_0 .net "naddr", 0 0, L_0x17ea120; 1 drivers +v0x159ee00_0 .net "o0", 0 0, L_0x17ea310; 1 drivers +v0x159eec0_0 .net "o1", 0 0, L_0x17ea620; 1 drivers +v0x171c4f0_0 .net "out", 0 0, L_0x17ea8e0; 1 drivers +L_0x17ea4c0 .part L_0x17ead80, 0, 1; +L_0x17ea730 .part L_0x17ead80, 1, 1; +S_0x15a9660 .scope module, "mux_mid_0" "bitMultiplexer" 4 33, 4 8 0, S_0x15ec900; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "addr" + .port_info 2 /INPUT 2 "in" +L_0x17eae20/d .functor NOT 1, L_0x17eb5c0, C4<0>, C4<0>, C4<0>; +L_0x17eae20 .delay 1 (10000,10000,10000) L_0x17eae20/d; +L_0x17eaee0/d .functor AND 1, L_0x17eb040, L_0x17eae20, C4<1>, C4<1>; +L_0x17eaee0 .delay 1 (20000,20000,20000) L_0x17eaee0/d; +L_0x17eb1a0/d .functor AND 1, L_0x17eb2b0, L_0x17eb5c0, C4<1>, C4<1>; +L_0x17eb1a0 .delay 1 (20000,20000,20000) L_0x17eb1a0/d; +L_0x17eb460/d .functor OR 1, L_0x17eaee0, L_0x17eb1a0, C4<0>, C4<0>; +L_0x17eb460 .delay 1 (20000,20000,20000) L_0x17eb460/d; +v0x16fc550_0 .net *"_s1", 0 0, L_0x17eb040; 1 drivers +v0x16dc5b0_0 .net *"_s3", 0 0, L_0x17eb2b0; 1 drivers +v0x16dc690_0 .net "addr", 0 0, L_0x17eb5c0; 1 drivers +v0x16bc610_0 .net "in", 1 0, L_0x17eb720; 1 drivers +v0x16bc6f0_0 .net "naddr", 0 0, L_0x17eae20; 1 drivers +v0x169c670_0 .net "o0", 0 0, L_0x17eaee0; 1 drivers +v0x169c730_0 .net "o1", 0 0, L_0x17eb1a0; 1 drivers +v0x167c6d0_0 .net "out", 0 0, L_0x17eb460; 1 drivers +L_0x17eb040 .part L_0x17eb720, 0, 1; +L_0x17eb2b0 .part L_0x17eb720, 1, 1; +S_0x158c9e0 .scope module, "mux_mid_1" "bitMultiplexer" 4 34, 4 8 0, S_0x15ec900; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "addr" + .port_info 2 /INPUT 2 "in" +L_0x17eb7c0/d .functor NOT 1, L_0x17ec160, C4<0>, C4<0>, C4<0>; +L_0x17eb7c0 .delay 1 (10000,10000,10000) L_0x17eb7c0/d; +L_0x17eb880/d .functor AND 1, L_0x17eb9e0, L_0x17eb7c0, C4<1>, C4<1>; +L_0x17eb880 .delay 1 (20000,20000,20000) L_0x17eb880/d; +L_0x17ebb40/d .functor AND 1, L_0x17ebc50, L_0x17ec160, C4<1>, C4<1>; +L_0x17ebb40 .delay 1 (20000,20000,20000) L_0x17ebb40/d; +L_0x17ebe00/d .functor OR 1, L_0x17eb880, L_0x17ebb40, C4<0>, C4<0>; +L_0x17ebe00 .delay 1 (20000,20000,20000) L_0x17ebe00/d; +v0x165c730_0 .net *"_s1", 0 0, L_0x17eb9e0; 1 drivers +v0x163c790_0 .net *"_s3", 0 0, L_0x17ebc50; 1 drivers +v0x163c870_0 .net "addr", 0 0, L_0x17ec160; 1 drivers +v0x161c800_0 .net "in", 1 0, L_0x17ec200; 1 drivers +v0x161c8e0_0 .net "naddr", 0 0, L_0x17eb7c0; 1 drivers +v0x15fc870_0 .net "o0", 0 0, L_0x17eb880; 1 drivers +v0x15fc930_0 .net "o1", 0 0, L_0x17ebb40; 1 drivers +v0x15dc8d0_0 .net "out", 0 0, L_0x17ebe00; 1 drivers +L_0x17eb9e0 .part L_0x17ec200, 0, 1; +L_0x17ebc50 .part L_0x17ec200, 1, 1; +S_0x1589680 .scope module, "mux_out" "bitMultiplexer" 4 35, 4 8 0, S_0x15ec900; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "addr" + .port_info 2 /INPUT 2 "in" +L_0x17eb660/d .functor NOT 1, L_0x17eca40, C4<0>, C4<0>, C4<0>; +L_0x17eb660 .delay 1 (10000,10000,10000) L_0x17eb660/d; +L_0x17ec370/d .functor AND 1, L_0x17ec4d0, L_0x17eb660, C4<1>, C4<1>; +L_0x17ec370 .delay 1 (20000,20000,20000) L_0x17ec370/d; +L_0x17ec630/d .functor AND 1, L_0x17ec740, L_0x17eca40, C4<1>, C4<1>; +L_0x17ec630 .delay 1 (20000,20000,20000) L_0x17ec630/d; +L_0x17ec930/d .functor OR 1, L_0x17ec370, L_0x17ec630, C4<0>, C4<0>; +L_0x17ec930 .delay 1 (20000,20000,20000) L_0x17ec930/d; +v0x15bc9d0_0 .net *"_s1", 0 0, L_0x17ec4d0; 1 drivers +v0x159c940_0 .net *"_s3", 0 0, L_0x17ec740; 1 drivers +v0x159ca00_0 .net "addr", 0 0, L_0x17eca40; 1 drivers +v0x157c980_0 .net "in", 1 0, L_0x17ebf60; alias, 1 drivers +v0x157ca40_0 .net "naddr", 0 0, L_0x17eb660; 1 drivers +v0x155ca00_0 .net "o0", 0 0, L_0x17ec370; 1 drivers +v0x173c490_0 .net "o1", 0 0, L_0x17ec630; 1 drivers +v0x173c550_0 .net "out", 0 0, L_0x17ec930; alias, 1 drivers +L_0x17ec4d0 .part L_0x17ebf60, 0, 1; +L_0x17ec740 .part L_0x17ebf60, 1, 1; +S_0x15495e0 .scope module, "structadder" "structAddSub" 3 22, 5 8 0, S_0x1609530; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "sub" + .port_info 5 /INPUT 1 "carryin" +L_0x17e72d0/d .functor XOR 1, L_0x17ece00, v0x17dbbc0_0, C4<0>, C4<0>; +L_0x17e72d0 .delay 1 (20000,20000,20000) L_0x17e72d0/d; +L_0x17e7710/d .functor XOR 1, L_0x17eccd0, L_0x17ece00, C4<0>, C4<0>; +L_0x17e7710 .delay 1 (20000,20000,20000) L_0x17e7710/d; +L_0x17e7870/d .functor XOR 1, L_0x17e7710, L_0x17ecba0, C4<0>, C4<0>; +L_0x17e7870 .delay 1 (20000,20000,20000) L_0x17e7870/d; +L_0x17e7a20/d .functor AND 1, L_0x17eccd0, L_0x17ece00, C4<1>, C4<1>; +L_0x17e7a20 .delay 1 (20000,20000,20000) L_0x17e7a20/d; +L_0x17e7b80/d .functor AND 1, L_0x17e7710, L_0x17ecba0, C4<1>, C4<1>; +L_0x17e7b80 .delay 1 (20000,20000,20000) L_0x17e7b80/d; +L_0x17e7ce0/d .functor OR 1, L_0x17e7b80, L_0x17e7a20, C4<0>, C4<0>; +L_0x17e7ce0 .delay 1 (20000,20000,20000) L_0x17e7ce0/d; +v0x172d6c0_0 .net "AandB", 0 0, L_0x17e7a20; 1 drivers +v0x1721ab0_0 .net "AxorB", 0 0, L_0x17e7710; 1 drivers +v0x1721b70_0 .net "AxorBandCarryIn", 0 0, L_0x17e7b80; 1 drivers +v0x171d330_0 .net "a", 0 0, L_0x17eccd0; alias, 1 drivers +v0x171d3f0_0 .net "b", 0 0, L_0x17ece00; alias, 1 drivers +v0x171cfc0_0 .net "bnew", 0 0, L_0x17e72d0; 1 drivers +v0x171d080_0 .net "carryin", 0 0, L_0x17ecba0; alias, 1 drivers +v0x1713950_0 .net "carryout", 0 0, L_0x17e7ce0; alias, 1 drivers +v0x17139f0_0 .net "sub", 0 0, v0x17dbbc0_0; alias, 1 drivers +v0x171ab50_0 .net "sum", 0 0, L_0x17e7870; 1 drivers +S_0x16f8ed0 .scope generate, "ripple[4]" "ripple[4]" 3 66, 3 66 0, S_0x16fa6c0; + .timescale -9 -12; +P_0x17157b0 .param/l "i" 0 3 66, +C4<0100>; +S_0x16ed6e0 .scope module, "bit" "BitSliceALU" 3 68, 3 11 0, S_0x16f8ed0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "ALUout" + .port_info 1 /OUTPUT 1 "Cout" + .port_info 2 /INPUT 1 "invertB" + .port_info 3 /INPUT 1 "Cin" + .port_info 4 /INPUT 3 "addr" + .port_info 5 /INPUT 1 "bit1" + .port_info 6 /INPUT 1 "bit2" +L_0x17ed6c0/d .functor XOR 1, L_0x17f25e0, L_0x17f2680, C4<0>, C4<0>; +L_0x17ed6c0 .delay 1 (20000,20000,20000) L_0x17ed6c0/d; +L_0x17ed820/d .functor NAND 1, L_0x17f25e0, L_0x17f2680, C4<1>, C4<1>; +L_0x17ed820 .delay 1 (10000,10000,10000) L_0x17ed820/d; +L_0x17ed980/d .functor XOR 1, v0x17dbbc0_0, L_0x17ed820, C4<0>, C4<0>; +L_0x17ed980 .delay 1 (20000,20000,20000) L_0x17ed980/d; +L_0x17eda90/d .functor NOR 1, L_0x17f25e0, L_0x17f2680, C4<0>, C4<0>; +L_0x17eda90 .delay 1 (10000,10000,10000) L_0x17eda90/d; +L_0x17edbf0/d .functor XOR 1, v0x17dbbc0_0, L_0x17eda90, C4<0>, C4<0>; +L_0x17edbf0 .delay 1 (20000,20000,20000) L_0x17edbf0/d; +v0x160d610_0 .net "ALUout", 0 0, L_0x17f21b0; 1 drivers +v0x160d6b0_0 .net "Cin", 0 0, L_0x17f2420; 1 drivers +v0x1601e30_0 .net "Cout", 0 0, L_0x17e8ff0; 1 drivers +v0x1601ed0_0 .net *"_s11", 0 0, L_0x17edbf0; 1 drivers +o0x7fc2cd911618 .functor BUFZ 1, C4; HiZ drive +; Elide local net with no drivers, v0x15f3cd0_0 name=_s15 +o0x7fc2cd911648 .functor BUFZ 3, C4; HiZ drive +; Elide local net with no drivers, v0x15f3dc0_0 name=_s17 +v0x15fae40_0 .net *"_s3", 0 0, L_0x17ed6c0; 1 drivers +v0x15faf20_0 .net *"_s7", 0 0, L_0x17ed980; 1 drivers +v0x15f91f0_0 .net "addr", 2 0, v0x17dbc90_0; alias, 1 drivers +v0x15f9290_0 .net "bit1", 0 0, L_0x17f25e0; 1 drivers +v0x15f59f0_0 .net "bit2", 0 0, L_0x17f2680; 1 drivers +v0x15f5ac0_0 .net "invertB", 0 0, v0x17dbbc0_0; alias, 1 drivers +v0x15eda00_0 .net "nanded", 0 0, L_0x17ed820; 1 drivers +v0x15edaa0_0 .net "nored", 0 0, L_0x17eda90; 1 drivers +v0x15ed680_0 .net "out", 7 0, L_0x1892340; 1 drivers +LS_0x1892340_0_0 .concat [ 1 1 1 1], L_0x17ed110, L_0x17ed6c0, o0x7fc2cd911618, L_0x17ed980; +LS_0x1892340_0_4 .concat [ 1 3 0 0], L_0x17edbf0, o0x7fc2cd911648; +L_0x1892340 .concat [ 4 4 0 0], LS_0x1892340_0_0, LS_0x1892340_0_4; +S_0x16e1b70 .scope module, "opmux" "structuralMultiplexer" 3 43, 4 21 0, S_0x16ed6e0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 3 "address" + .port_info 2 /INPUT 8 "in" +v0x1633bf0_0 .net "address", 2 0, v0x17dbc90_0; alias, 1 drivers +v0x1633cb0_0 .net "in", 7 0, L_0x1892340; alias, 1 drivers +v0x1639110_0 .net "mux", 3 0, L_0x17f0270; 1 drivers +v0x16391d0_0 .net "muxmid", 1 0, L_0x17f17e0; 1 drivers +v0x1635910_0 .net "out", 0 0, L_0x17f21b0; alias, 1 drivers +L_0x17ee4f0 .part v0x17dbc90_0, 0, 1; +L_0x17ee650 .part L_0x1892340, 0, 2; +L_0x17eee90 .part v0x17dbc90_0, 0, 1; +L_0x17eeff0 .part L_0x1892340, 2, 2; +L_0x17ef860 .part v0x17dbc90_0, 0, 1; +L_0x17ef9c0 .part L_0x1892340, 4, 2; +L_0x17f0270 .concat8 [ 1 1 1 1], L_0x17ee390, L_0x17eed30, L_0x17ef700, L_0x17f0110; +L_0x17f04c0 .part v0x17dbc90_0, 0, 1; +L_0x17f05b0 .part L_0x1892340, 6, 2; +L_0x17f0df0 .part v0x17dbc90_0, 1, 1; +L_0x17f0f50 .part L_0x17f0270, 0, 2; +L_0x17f17e0 .concat8 [ 1 1 0 0], L_0x17f0c90, L_0x17f1680; +L_0x17f19e0 .part v0x17dbc90_0, 1, 1; +L_0x17f1a80 .part L_0x17f0270, 2, 2; +L_0x17f22c0 .part v0x17dbc90_0, 2, 1; +S_0x16dd080 .scope module, "mux_0" "bitMultiplexer" 4 29, 4 8 0, S_0x16e1b70; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "addr" + .port_info 2 /INPUT 2 "in" +L_0x17edd00/d .functor NOT 1, L_0x17ee4f0, C4<0>, C4<0>, C4<0>; +L_0x17edd00 .delay 1 (10000,10000,10000) L_0x17edd00/d; +L_0x17ede60/d .functor AND 1, L_0x17edf70, L_0x17edd00, C4<1>, C4<1>; +L_0x17ede60 .delay 1 (20000,20000,20000) L_0x17ede60/d; +L_0x17ee0d0/d .functor AND 1, L_0x17ee1e0, L_0x17ee4f0, C4<1>, C4<1>; +L_0x17ee0d0 .delay 1 (20000,20000,20000) L_0x17ee0d0/d; +L_0x17ee390/d .functor OR 1, L_0x17ede60, L_0x17ee0d0, C4<0>, C4<0>; +L_0x17ee390 .delay 1 (20000,20000,20000) L_0x17ee390/d; +v0x16d3a10_0 .net *"_s1", 0 0, L_0x17edf70; 1 drivers +v0x16d3b10_0 .net *"_s3", 0 0, L_0x17ee1e0; 1 drivers +v0x16dab80_0 .net "addr", 0 0, L_0x17ee4f0; 1 drivers +v0x16dac20_0 .net "in", 1 0, L_0x17ee650; 1 drivers +v0x16d8f30_0 .net "naddr", 0 0, L_0x17edd00; 1 drivers +v0x16d9020_0 .net "o0", 0 0, L_0x17ede60; 1 drivers +v0x16d5750_0 .net "o1", 0 0, L_0x17ee0d0; 1 drivers +v0x16d5810_0 .net "out", 0 0, L_0x17ee390; 1 drivers +L_0x17edf70 .part L_0x17ee650, 0, 1; +L_0x17ee1e0 .part L_0x17ee650, 1, 1; +S_0x16c1bd0 .scope module, "mux_1" "bitMultiplexer" 4 30, 4 8 0, S_0x16e1b70; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "addr" + .port_info 2 /INPUT 2 "in" +L_0x17ee6f0/d .functor NOT 1, L_0x17eee90, C4<0>, C4<0>, C4<0>; +L_0x17ee6f0 .delay 1 (10000,10000,10000) L_0x17ee6f0/d; +L_0x17ee7b0/d .functor AND 1, L_0x17ee910, L_0x17ee6f0, C4<1>, C4<1>; +L_0x17ee7b0 .delay 1 (20000,20000,20000) L_0x17ee7b0/d; +L_0x17eea70/d .functor AND 1, L_0x17eeb80, L_0x17eee90, C4<1>, C4<1>; +L_0x17eea70 .delay 1 (20000,20000,20000) L_0x17eea70/d; +L_0x17eed30/d .functor OR 1, L_0x17ee7b0, L_0x17eea70, C4<0>, C4<0>; +L_0x17eed30 .delay 1 (20000,20000,20000) L_0x17eed30/d; +v0x16bd450_0 .net *"_s1", 0 0, L_0x17ee910; 1 drivers +v0x16bd550_0 .net *"_s3", 0 0, L_0x17eeb80; 1 drivers +v0x16bd0e0_0 .net "addr", 0 0, L_0x17eee90; 1 drivers +v0x16bd180_0 .net "in", 1 0, L_0x17eeff0; 1 drivers +v0x16b3a70_0 .net "naddr", 0 0, L_0x17ee6f0; 1 drivers +v0x16b3b60_0 .net "o0", 0 0, L_0x17ee7b0; 1 drivers +v0x16babe0_0 .net "o1", 0 0, L_0x17eea70; 1 drivers +v0x16bac80_0 .net "out", 0 0, L_0x17eed30; 1 drivers +L_0x17ee910 .part L_0x17eeff0, 0, 1; +L_0x17eeb80 .part L_0x17eeff0, 1, 1; +S_0x16b5790 .scope module, "mux_2" "bitMultiplexer" 4 31, 4 8 0, S_0x16e1b70; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "addr" + .port_info 2 /INPUT 2 "in" +L_0x17eef30/d .functor NOT 1, L_0x17ef860, C4<0>, C4<0>, C4<0>; +L_0x17eef30 .delay 1 (10000,10000,10000) L_0x17eef30/d; +L_0x17ef0e0/d .functor AND 1, L_0x17ef2e0, L_0x17eef30, C4<1>, C4<1>; +L_0x17ef0e0 .delay 1 (20000,20000,20000) L_0x17ef0e0/d; +L_0x17ef440/d .functor AND 1, L_0x17ef550, L_0x17ef860, C4<1>, C4<1>; +L_0x17ef440 .delay 1 (20000,20000,20000) L_0x17ef440/d; +L_0x17ef700/d .functor OR 1, L_0x17ef0e0, L_0x17ef440, C4<0>, C4<0>; +L_0x17ef700 .delay 1 (20000,20000,20000) L_0x17ef700/d; +v0x16b9070_0 .net *"_s1", 0 0, L_0x17ef2e0; 1 drivers +v0x16ad7c0_0 .net *"_s3", 0 0, L_0x17ef550; 1 drivers +v0x16ad8a0_0 .net "addr", 0 0, L_0x17ef860; 1 drivers +v0x16a1c60_0 .net "in", 1 0, L_0x17ef9c0; 1 drivers +v0x169d4b0_0 .net "naddr", 0 0, L_0x17eef30; 1 drivers +v0x169d140_0 .net "o0", 0 0, L_0x17ef0e0; 1 drivers +v0x169d200_0 .net "o1", 0 0, L_0x17ef440; 1 drivers +v0x1693ad0_0 .net "out", 0 0, L_0x17ef700; 1 drivers +L_0x17ef2e0 .part L_0x17ef9c0, 0, 1; +L_0x17ef550 .part L_0x17ef9c0, 1, 1; +S_0x169ac40 .scope module, "mux_3" "bitMultiplexer" 4 32, 4 8 0, S_0x16e1b70; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "addr" + .port_info 2 /INPUT 2 "in" +L_0x17ef900/d .functor NOT 1, L_0x17f04c0, C4<0>, C4<0>, C4<0>; +L_0x17ef900 .delay 1 (10000,10000,10000) L_0x17ef900/d; +L_0x17efaf0/d .functor AND 1, L_0x17efcf0, L_0x17ef900, C4<1>, C4<1>; +L_0x17efaf0 .delay 1 (20000,20000,20000) L_0x17efaf0/d; +L_0x17efe50/d .functor AND 1, L_0x17eff60, L_0x17f04c0, C4<1>, C4<1>; +L_0x17efe50 .delay 1 (20000,20000,20000) L_0x17efe50/d; +L_0x17f0110/d .functor OR 1, L_0x17efaf0, L_0x17efe50, C4<0>, C4<0>; +L_0x17f0110 .delay 1 (20000,20000,20000) L_0x17f0110/d; +v0x1698ff0_0 .net *"_s1", 0 0, L_0x17efcf0; 1 drivers +v0x16990f0_0 .net *"_s3", 0 0, L_0x17eff60; 1 drivers +v0x16957f0_0 .net "addr", 0 0, L_0x17f04c0; 1 drivers +v0x1695890_0 .net "in", 1 0, L_0x17f05b0; 1 drivers +v0x168d800_0 .net "naddr", 0 0, L_0x17ef900; 1 drivers +v0x168d8f0_0 .net "o0", 0 0, L_0x17efaf0; 1 drivers +v0x1681c90_0 .net "o1", 0 0, L_0x17efe50; 1 drivers +v0x1681d50_0 .net "out", 0 0, L_0x17f0110; 1 drivers +L_0x17efcf0 .part L_0x17f05b0, 0, 1; +L_0x17eff60 .part L_0x17f05b0, 1, 1; +S_0x167d510 .scope module, "mux_mid_0" "bitMultiplexer" 4 33, 4 8 0, S_0x16e1b70; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "addr" + .port_info 2 /INPUT 2 "in" +L_0x17f0650/d .functor NOT 1, L_0x17f0df0, C4<0>, C4<0>, C4<0>; +L_0x17f0650 .delay 1 (10000,10000,10000) L_0x17f0650/d; +L_0x17f0710/d .functor AND 1, L_0x17f0870, L_0x17f0650, C4<1>, C4<1>; +L_0x17f0710 .delay 1 (20000,20000,20000) L_0x17f0710/d; +L_0x17f09d0/d .functor AND 1, L_0x17f0ae0, L_0x17f0df0, C4<1>, C4<1>; +L_0x17f09d0 .delay 1 (20000,20000,20000) L_0x17f09d0/d; +L_0x17f0c90/d .functor OR 1, L_0x17f0710, L_0x17f09d0, C4<0>, C4<0>; +L_0x17f0c90 .delay 1 (20000,20000,20000) L_0x17f0c90/d; +v0x167d290_0 .net *"_s1", 0 0, L_0x17f0870; 1 drivers +v0x1673b90_0 .net *"_s3", 0 0, L_0x17f0ae0; 1 drivers +v0x167aca0_0 .net "addr", 0 0, L_0x17f0df0; 1 drivers +v0x167ad40_0 .net "in", 1 0, L_0x17f0f50; 1 drivers +v0x1679050_0 .net "naddr", 0 0, L_0x17f0650; 1 drivers +v0x1679140_0 .net "o0", 0 0, L_0x17f0710; 1 drivers +v0x1675850_0 .net "o1", 0 0, L_0x17f09d0; 1 drivers +v0x1675910_0 .net "out", 0 0, L_0x17f0c90; 1 drivers +L_0x17f0870 .part L_0x17f0f50, 0, 1; +L_0x17f0ae0 .part L_0x17f0f50, 1, 1; +S_0x1661cf0 .scope module, "mux_mid_1" "bitMultiplexer" 4 34, 4 8 0, S_0x16e1b70; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "addr" + .port_info 2 /INPUT 2 "in" +L_0x17f0ff0/d .functor NOT 1, L_0x17f19e0, C4<0>, C4<0>, C4<0>; +L_0x17f0ff0 .delay 1 (10000,10000,10000) L_0x17f0ff0/d; +L_0x17f10b0/d .functor AND 1, L_0x17f1260, L_0x17f0ff0, C4<1>, C4<1>; +L_0x17f10b0 .delay 1 (20000,20000,20000) L_0x17f10b0/d; +L_0x17f13c0/d .functor AND 1, L_0x17f14d0, L_0x17f19e0, C4<1>, C4<1>; +L_0x17f13c0 .delay 1 (20000,20000,20000) L_0x17f13c0/d; +L_0x17f1680/d .functor OR 1, L_0x17f10b0, L_0x17f13c0, C4<0>, C4<0>; +L_0x17f1680 .delay 1 (20000,20000,20000) L_0x17f1680/d; +v0x166d920_0 .net *"_s1", 0 0, L_0x17f1260; 1 drivers +v0x165d590_0 .net *"_s3", 0 0, L_0x17f14d0; 1 drivers +v0x165d670_0 .net "addr", 0 0, L_0x17f19e0; 1 drivers +v0x165d200_0 .net "in", 1 0, L_0x17f1a80; 1 drivers +v0x165d2e0_0 .net "naddr", 0 0, L_0x17f0ff0; 1 drivers +v0x1653be0_0 .net "o0", 0 0, L_0x17f10b0; 1 drivers +v0x165ad00_0 .net "o1", 0 0, L_0x17f13c0; 1 drivers +v0x165adc0_0 .net "out", 0 0, L_0x17f1680; 1 drivers +L_0x17f1260 .part L_0x17f1a80, 0, 1; +L_0x17f14d0 .part L_0x17f1a80, 1, 1; +S_0x16590b0 .scope module, "mux_out" "bitMultiplexer" 4 35, 4 8 0, S_0x16e1b70; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "addr" + .port_info 2 /INPUT 2 "in" +L_0x17f0e90/d .functor NOT 1, L_0x17f22c0, C4<0>, C4<0>, C4<0>; +L_0x17f0e90 .delay 1 (10000,10000,10000) L_0x17f0e90/d; +L_0x17f1bf0/d .functor AND 1, L_0x17f1d50, L_0x17f0e90, C4<1>, C4<1>; +L_0x17f1bf0 .delay 1 (20000,20000,20000) L_0x17f1bf0/d; +L_0x17f1eb0/d .functor AND 1, L_0x17f1fc0, L_0x17f22c0, C4<1>, C4<1>; +L_0x17f1eb0 .delay 1 (20000,20000,20000) L_0x17f1eb0/d; +L_0x17f21b0/d .functor OR 1, L_0x17f1bf0, L_0x17f1eb0, C4<0>, C4<0>; +L_0x17f21b0 .delay 1 (20000,20000,20000) L_0x17f21b0/d; +v0x1655950_0 .net *"_s1", 0 0, L_0x17f1d50; 1 drivers +v0x164d8c0_0 .net *"_s3", 0 0, L_0x17f1fc0; 1 drivers +v0x164d980_0 .net "addr", 0 0, L_0x17f22c0; 1 drivers +v0x1641d50_0 .net "in", 1 0, L_0x17f17e0; alias, 1 drivers +v0x1641e30_0 .net "naddr", 0 0, L_0x17f0e90; 1 drivers +v0x163d620_0 .net "o0", 0 0, L_0x17f1bf0; 1 drivers +v0x163d260_0 .net "o1", 0 0, L_0x17f1eb0; 1 drivers +v0x163d320_0 .net "out", 0 0, L_0x17f21b0; alias, 1 drivers +L_0x17f1d50 .part L_0x17f17e0, 0, 1; +L_0x17f1fc0 .part L_0x17f17e0, 1, 1; +S_0x162d920 .scope module, "structadder" "structAddSub" 3 22, 5 8 0, S_0x16ed6e0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "sub" + .port_info 5 /INPUT 1 "carryin" +L_0x17ecae0/d .functor XOR 1, L_0x17f2680, v0x17dbbc0_0, C4<0>, C4<0>; +L_0x17ecae0 .delay 1 (20000,20000,20000) L_0x17ecae0/d; +L_0x17ecfb0/d .functor XOR 1, L_0x17f25e0, L_0x17f2680, C4<0>, C4<0>; +L_0x17ecfb0 .delay 1 (20000,20000,20000) L_0x17ecfb0/d; +L_0x17ed110/d .functor XOR 1, L_0x17ecfb0, L_0x17f2420, C4<0>, C4<0>; +L_0x17ed110 .delay 1 (20000,20000,20000) L_0x17ed110/d; +L_0x17ed2c0/d .functor AND 1, L_0x17f25e0, L_0x17f2680, C4<1>, C4<1>; +L_0x17ed2c0 .delay 1 (20000,20000,20000) L_0x17ed2c0/d; +L_0x17ed420/d .functor AND 1, L_0x17ecfb0, L_0x17f2420, C4<1>, C4<1>; +L_0x17ed420 .delay 1 (20000,20000,20000) L_0x17ed420/d; +L_0x17e8ff0/d .functor OR 1, L_0x17ed420, L_0x17ed2c0, C4<0>, C4<0>; +L_0x17e8ff0 .delay 1 (20000,20000,20000) L_0x17e8ff0/d; +v0x162d640_0 .net "AandB", 0 0, L_0x17ed2c0; 1 drivers +v0x1621dc0_0 .net "AxorB", 0 0, L_0x17ecfb0; 1 drivers +v0x1621e80_0 .net "AxorBandCarryIn", 0 0, L_0x17ed420; 1 drivers +v0x1613c60_0 .net "a", 0 0, L_0x17f25e0; alias, 1 drivers +v0x1613d20_0 .net "b", 0 0, L_0x17f2680; alias, 1 drivers +v0x161add0_0 .net "bnew", 0 0, L_0x17ecae0; 1 drivers +v0x161ae70_0 .net "carryin", 0 0, L_0x17f2420; alias, 1 drivers +v0x1619180_0 .net "carryout", 0 0, L_0x17e8ff0; alias, 1 drivers +v0x1619240_0 .net "sub", 0 0, v0x17dbbc0_0; alias, 1 drivers +v0x160d990_0 .net "sum", 0 0, L_0x17ed110; 1 drivers +S_0x15d3d30 .scope generate, "ripple[5]" "ripple[5]" 3 66, 3 66 0, S_0x16fa6c0; + .timescale -9 -12; +P_0x1601f70 .param/l "i" 0 3 66, +C4<0101>; +S_0x15daea0 .scope module, "bit" "BitSliceALU" 3 68, 3 11 0, S_0x15d3d30; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "ALUout" + .port_info 1 /OUTPUT 1 "Cout" + .port_info 2 /INPUT 1 "invertB" + .port_info 3 /INPUT 1 "Cin" + .port_info 4 /INPUT 3 "addr" + .port_info 5 /INPUT 1 "bit1" + .port_info 6 /INPUT 1 "bit2" +L_0x17f2f10/d .functor XOR 1, L_0x17f7e90, L_0x17f7fb0, C4<0>, C4<0>; +L_0x17f2f10 .delay 1 (20000,20000,20000) L_0x17f2f10/d; +L_0x17f3070/d .functor NAND 1, L_0x17f7e90, L_0x17f7fb0, C4<1>, C4<1>; +L_0x17f3070 .delay 1 (10000,10000,10000) L_0x17f3070/d; +L_0x17f31d0/d .functor XOR 1, v0x17dbbc0_0, L_0x17f3070, C4<0>, C4<0>; +L_0x17f31d0 .delay 1 (20000,20000,20000) L_0x17f31d0/d; +L_0x17f32e0/d .functor NOR 1, L_0x17f7e90, L_0x17f7fb0, C4<0>, C4<0>; +L_0x17f32e0 .delay 1 (10000,10000,10000) L_0x17f32e0/d; +L_0x17f3440/d .functor XOR 1, v0x17dbbc0_0, L_0x17f32e0, C4<0>, C4<0>; +L_0x17f3440 .delay 1 (20000,20000,20000) L_0x17f3440/d; +v0x171e9e0_0 .net "ALUout", 0 0, L_0x17f7af0; 1 drivers +v0x171eaf0_0 .net "Cin", 0 0, L_0x17f7d60; 1 drivers +v0x1723810_0 .net "Cout", 0 0, L_0x17f2d60; 1 drivers +v0x17238e0_0 .net *"_s11", 0 0, L_0x17f3440; 1 drivers +o0x7fc2cd912ae8 .functor BUFZ 1, C4; HiZ drive +; Elide local net with no drivers, v0x172adc0_0 name=_s15 +o0x7fc2cd912b18 .functor BUFZ 3, C4; HiZ drive +; Elide local net with no drivers, v0x172aeb0_0 name=_s17 +v0x172aaa0_0 .net *"_s3", 0 0, L_0x17f2f10; 1 drivers +v0x172ab60_0 .net *"_s7", 0 0, L_0x17f31d0; 1 drivers +v0x1728e40_0 .net "addr", 2 0, v0x17dbc90_0; alias, 1 drivers +v0x1728f00_0 .net "bit1", 0 0, L_0x17f7e90; 1 drivers +v0x17273a0_0 .net "bit2", 0 0, L_0x17f7fb0; 1 drivers +v0x1727440_0 .net "invertB", 0 0, v0x17dbbc0_0; alias, 1 drivers +v0x17258a0_0 .net "nanded", 0 0, L_0x17f3070; 1 drivers +v0x1725940_0 .net "nored", 0 0, L_0x17f32e0; 1 drivers +v0x1725590_0 .net "out", 7 0, L_0x18923e0; 1 drivers +LS_0x18923e0_0_0 .concat [ 1 1 1 1], L_0x17f28f0, L_0x17f2f10, o0x7fc2cd912ae8, L_0x17f31d0; +LS_0x18923e0_0_4 .concat [ 1 3 0 0], L_0x17f3440, o0x7fc2cd912b18; +L_0x18923e0 .concat [ 4 4 0 0], LS_0x18923e0_0_0, LS_0x18923e0_0_4; +S_0x15d5a50 .scope module, "opmux" "structuralMultiplexer" 3 43, 4 21 0, S_0x15daea0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 3 "address" + .port_info 2 /INPUT 8 "in" +v0x15ced70_0 .net "address", 2 0, v0x17dbc90_0; alias, 1 drivers +v0x15cee30_0 .net "in", 7 0, L_0x18923e0; alias, 1 drivers +v0x15eed10_0 .net "mux", 3 0, L_0x17f5b60; 1 drivers +v0x15eedb0_0 .net "muxmid", 1 0, L_0x17f7120; 1 drivers +v0x160eca0_0 .net "out", 0 0, L_0x17f7af0; alias, 1 drivers +L_0x17f3d40 .part v0x17dbc90_0, 0, 1; +L_0x17f3ea0 .part L_0x18923e0, 0, 2; +L_0x17f4780 .part v0x17dbc90_0, 0, 1; +L_0x17f48e0 .part L_0x18923e0, 2, 2; +L_0x17f5150 .part v0x17dbc90_0, 0, 1; +L_0x17f52b0 .part L_0x18923e0, 4, 2; +L_0x17f5b60 .concat8 [ 1 1 1 1], L_0x17f3be0, L_0x17f4620, L_0x17f4ff0, L_0x17f5a00; +L_0x17f5e00 .part v0x17dbc90_0, 0, 1; +L_0x17f5ef0 .part L_0x18923e0, 6, 2; +L_0x17f6730 .part v0x17dbc90_0, 1, 1; +L_0x17f6890 .part L_0x17f5b60, 0, 2; +L_0x17f7120 .concat8 [ 1 1 0 0], L_0x17f65d0, L_0x17f6fc0; +L_0x17f7320 .part v0x17dbc90_0, 1, 1; +L_0x17f73c0 .part L_0x17f5b60, 2, 2; +L_0x17f7c00 .part v0x17dbc90_0, 2, 1; +S_0x15cda60 .scope module, "mux_0" "bitMultiplexer" 4 29, 4 8 0, S_0x15d5a50; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "addr" + .port_info 2 /INPUT 2 "in" +L_0x17f3550/d .functor NOT 1, L_0x17f3d40, C4<0>, C4<0>, C4<0>; +L_0x17f3550 .delay 1 (10000,10000,10000) L_0x17f3550/d; +L_0x17f36b0/d .functor AND 1, L_0x17f37c0, L_0x17f3550, C4<1>, C4<1>; +L_0x17f36b0 .delay 1 (20000,20000,20000) L_0x17f36b0/d; +L_0x17f3920/d .functor AND 1, L_0x17f3a30, L_0x17f3d40, C4<1>, C4<1>; +L_0x17f3920 .delay 1 (20000,20000,20000) L_0x17f3920/d; +L_0x17f3be0/d .functor OR 1, L_0x17f36b0, L_0x17f3920, C4<0>, C4<0>; +L_0x17f3be0 .delay 1 (20000,20000,20000) L_0x17f3be0/d; +v0x15cd6e0_0 .net *"_s1", 0 0, L_0x17f37c0; 1 drivers +v0x15cd7e0_0 .net *"_s3", 0 0, L_0x17f3a30; 1 drivers +v0x15b3d90_0 .net "addr", 0 0, L_0x17f3d40; 1 drivers +v0x15b3e60_0 .net "in", 1 0, L_0x17f3ea0; 1 drivers +v0x15baf00_0 .net "naddr", 0 0, L_0x17f3550; 1 drivers +v0x15baff0_0 .net "o0", 0 0, L_0x17f36b0; 1 drivers +v0x15b92d0_0 .net "o1", 0 0, L_0x17f3920; 1 drivers +v0x15b9390_0 .net "out", 0 0, L_0x17f3be0; 1 drivers +L_0x17f37c0 .part L_0x17f3ea0, 0, 1; +L_0x17f3a30 .part L_0x17f3ea0, 1, 1; +S_0x15adac0 .scope module, "mux_1" "bitMultiplexer" 4 30, 4 8 0, S_0x15d5a50; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "addr" + .port_info 2 /INPUT 2 "in" +L_0x17f3f40/d .functor NOT 1, L_0x17f4780, C4<0>, C4<0>, C4<0>; +L_0x17f3f40 .delay 1 (10000,10000,10000) L_0x17f3f40/d; +L_0x17f4000/d .functor AND 1, L_0x17f4200, L_0x17f3f40, C4<1>, C4<1>; +L_0x17f4000 .delay 1 (20000,20000,20000) L_0x17f4000/d; +L_0x17f4360/d .functor AND 1, L_0x17f4470, L_0x17f4780, C4<1>, C4<1>; +L_0x17f4360 .delay 1 (20000,20000,20000) L_0x17f4360/d; +L_0x17f4620/d .functor OR 1, L_0x17f4000, L_0x17f4360, C4<0>, C4<0>; +L_0x17f4620 .delay 1 (20000,20000,20000) L_0x17f4620/d; +v0x15ad740_0 .net *"_s1", 0 0, L_0x17f4200; 1 drivers +v0x15ad840_0 .net *"_s3", 0 0, L_0x17f4470; 1 drivers +v0x1593da0_0 .net "addr", 0 0, L_0x17f4780; 1 drivers +v0x1593e40_0 .net "in", 1 0, L_0x17f48e0; 1 drivers +v0x159af10_0 .net "naddr", 0 0, L_0x17f3f40; 1 drivers +v0x159b000_0 .net "o0", 0 0, L_0x17f4000; 1 drivers +v0x1592020_0 .net "o1", 0 0, L_0x17f4360; 1 drivers +v0x15920c0_0 .net "out", 0 0, L_0x17f4620; 1 drivers +L_0x17f4200 .part L_0x17f48e0, 0, 1; +L_0x17f4470 .part L_0x17f48e0, 1, 1; +S_0x1595ac0 .scope module, "mux_2" "bitMultiplexer" 4 31, 4 8 0, S_0x15d5a50; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "addr" + .port_info 2 /INPUT 2 "in" +L_0x17f4820/d .functor NOT 1, L_0x17f5150, C4<0>, C4<0>, C4<0>; +L_0x17f4820 .delay 1 (10000,10000,10000) L_0x17f4820/d; +L_0x17f49d0/d .functor AND 1, L_0x17f4bd0, L_0x17f4820, C4<1>, C4<1>; +L_0x17f49d0 .delay 1 (20000,20000,20000) L_0x17f49d0/d; +L_0x17f4d30/d .functor AND 1, L_0x17f4e40, L_0x17f5150, C4<1>, C4<1>; +L_0x17f4d30 .delay 1 (20000,20000,20000) L_0x17f4d30/d; +L_0x17f4ff0/d .functor OR 1, L_0x17f49d0, L_0x17f4d30, C4<0>, C4<0>; +L_0x17f4ff0 .delay 1 (20000,20000,20000) L_0x17f4ff0/d; +v0x15993a0_0 .net *"_s1", 0 0, L_0x17f4bd0; 1 drivers +v0x158db00_0 .net *"_s3", 0 0, L_0x17f4e40; 1 drivers +v0x158dbe0_0 .net "addr", 0 0, L_0x17f5150; 1 drivers +v0x158d790_0 .net "in", 1 0, L_0x17f52b0; 1 drivers +v0x1573de0_0 .net "naddr", 0 0, L_0x17f4820; 1 drivers +v0x157af50_0 .net "o0", 0 0, L_0x17f49d0; 1 drivers +v0x157b010_0 .net "o1", 0 0, L_0x17f4d30; 1 drivers +v0x1572060_0 .net "out", 0 0, L_0x17f4ff0; 1 drivers +L_0x17f4bd0 .part L_0x17f52b0, 0, 1; +L_0x17f4e40 .part L_0x17f52b0, 1, 1; +S_0x1579300 .scope module, "mux_3" "bitMultiplexer" 4 32, 4 8 0, S_0x15d5a50; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "addr" + .port_info 2 /INPUT 2 "in" +L_0x17f51f0/d .functor NOT 1, L_0x17f5e00, C4<0>, C4<0>, C4<0>; +L_0x17f51f0 .delay 1 (10000,10000,10000) L_0x17f51f0/d; +L_0x17f53e0/d .functor AND 1, L_0x17f55e0, L_0x17f51f0, C4<1>, C4<1>; +L_0x17f53e0 .delay 1 (20000,20000,20000) L_0x17f53e0/d; +L_0x17f5740/d .functor AND 1, L_0x17f5850, L_0x17f5e00, C4<1>, C4<1>; +L_0x17f5740 .delay 1 (20000,20000,20000) L_0x17f5740/d; +L_0x17f5a00/d .functor OR 1, L_0x17f53e0, L_0x17f5740, C4<0>, C4<0>; +L_0x17f5a00 .delay 1 (20000,20000,20000) L_0x17f5a00/d; +v0x1575b00_0 .net *"_s1", 0 0, L_0x17f55e0; 1 drivers +v0x1575c00_0 .net *"_s3", 0 0, L_0x17f5850; 1 drivers +v0x156db20_0 .net "addr", 0 0, L_0x17f5e00; 1 drivers +v0x156dbc0_0 .net "in", 1 0, L_0x17f5ef0; 1 drivers +v0x156d7a0_0 .net "naddr", 0 0, L_0x17f51f0; 1 drivers +v0x156d890_0 .net "o0", 0 0, L_0x17f53e0; 1 drivers +v0x1553e10_0 .net "o1", 0 0, L_0x17f5740; 1 drivers +v0x1553ed0_0 .net "out", 0 0, L_0x17f5a00; 1 drivers +L_0x17f55e0 .part L_0x17f5ef0, 0, 1; +L_0x17f5850 .part L_0x17f5ef0, 1, 1; +S_0x155af80 .scope module, "mux_mid_0" "bitMultiplexer" 4 33, 4 8 0, S_0x15d5a50; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "addr" + .port_info 2 /INPUT 2 "in" +L_0x17f5f90/d .functor NOT 1, L_0x17f6730, C4<0>, C4<0>, C4<0>; +L_0x17f5f90 .delay 1 (10000,10000,10000) L_0x17f5f90/d; +L_0x17f6050/d .functor AND 1, L_0x17f61b0, L_0x17f5f90, C4<1>, C4<1>; +L_0x17f6050 .delay 1 (20000,20000,20000) L_0x17f6050/d; +L_0x17f6310/d .functor AND 1, L_0x17f6420, L_0x17f6730, C4<1>, C4<1>; +L_0x17f6310 .delay 1 (20000,20000,20000) L_0x17f6310/d; +L_0x17f65d0/d .functor OR 1, L_0x17f6050, L_0x17f6310, C4<0>, C4<0>; +L_0x17f65d0 .delay 1 (20000,20000,20000) L_0x17f65d0/d; +v0x1552180_0 .net *"_s1", 0 0, L_0x17f61b0; 1 drivers +v0x1559390_0 .net *"_s3", 0 0, L_0x17f6420; 1 drivers +v0x1555b30_0 .net "addr", 0 0, L_0x17f6730; 1 drivers +v0x1555bd0_0 .net "in", 1 0, L_0x17f6890; 1 drivers +v0x17338f0_0 .net "naddr", 0 0, L_0x17f5f90; 1 drivers +v0x17339e0_0 .net "o0", 0 0, L_0x17f6050; 1 drivers +v0x173aa60_0 .net "o1", 0 0, L_0x17f6310; 1 drivers +v0x173ab20_0 .net "out", 0 0, L_0x17f65d0; 1 drivers +L_0x17f61b0 .part L_0x17f6890, 0, 1; +L_0x17f6420 .part L_0x17f6890, 1, 1; +S_0x1735610 .scope module, "mux_mid_1" "bitMultiplexer" 4 34, 4 8 0, S_0x15d5a50; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "addr" + .port_info 2 /INPUT 2 "in" +L_0x17f6930/d .functor NOT 1, L_0x17f7320, C4<0>, C4<0>, C4<0>; +L_0x17f6930 .delay 1 (10000,10000,10000) L_0x17f6930/d; +L_0x17f69f0/d .functor AND 1, L_0x17f6ba0, L_0x17f6930, C4<1>, C4<1>; +L_0x17f69f0 .delay 1 (20000,20000,20000) L_0x17f69f0/d; +L_0x17f6d00/d .functor AND 1, L_0x17f6e10, L_0x17f7320, C4<1>, C4<1>; +L_0x17f6d00 .delay 1 (20000,20000,20000) L_0x17f6d00/d; +L_0x17f6fc0/d .functor OR 1, L_0x17f69f0, L_0x17f6d00, C4<0>, C4<0>; +L_0x17f6fc0 .delay 1 (20000,20000,20000) L_0x17f6fc0/d; +v0x1738ed0_0 .net *"_s1", 0 0, L_0x17f6ba0; 1 drivers +v0x1721e10_0 .net *"_s3", 0 0, L_0x17f6e10; 1 drivers +v0x1721ef0_0 .net "addr", 0 0, L_0x17f7320; 1 drivers +v0x1701e50_0 .net "in", 1 0, L_0x17f73c0; 1 drivers +v0x1701f30_0 .net "naddr", 0 0, L_0x17f6930; 1 drivers +v0x16e1f20_0 .net "o0", 0 0, L_0x17f69f0; 1 drivers +v0x16c1f10_0 .net "o1", 0 0, L_0x17f6d00; 1 drivers +v0x16c1fd0_0 .net "out", 0 0, L_0x17f6fc0; 1 drivers +L_0x17f6ba0 .part L_0x17f73c0, 0, 1; +L_0x17f6e10 .part L_0x17f73c0, 1, 1; +S_0x172e930 .scope module, "mux_out" "bitMultiplexer" 4 35, 4 8 0, S_0x15d5a50; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "addr" + .port_info 2 /INPUT 2 "in" +L_0x17f67d0/d .functor NOT 1, L_0x17f7c00, C4<0>, C4<0>, C4<0>; +L_0x17f67d0 .delay 1 (10000,10000,10000) L_0x17f67d0/d; +L_0x17f7530/d .functor AND 1, L_0x17f7690, L_0x17f67d0, C4<1>, C4<1>; +L_0x17f7530 .delay 1 (20000,20000,20000) L_0x17f7530/d; +L_0x17f77f0/d .functor AND 1, L_0x17f7900, L_0x17f7c00, C4<1>, C4<1>; +L_0x17f77f0 .delay 1 (20000,20000,20000) L_0x17f77f0/d; +L_0x17f7af0/d .functor OR 1, L_0x17f7530, L_0x17f77f0, C4<0>, C4<0>; +L_0x17f7af0 .delay 1 (20000,20000,20000) L_0x17f7af0/d; +v0x154ef00_0 .net *"_s1", 0 0, L_0x17f7690; 1 drivers +v0x155ee70_0 .net *"_s3", 0 0, L_0x17f7900; 1 drivers +v0x155ef50_0 .net "addr", 0 0, L_0x17f7c00; 1 drivers +v0x156ee30_0 .net "in", 1 0, L_0x17f7120; alias, 1 drivers +v0x156ef10_0 .net "naddr", 0 0, L_0x17f67d0; 1 drivers +v0x157eeb0_0 .net "o0", 0 0, L_0x17f7530; 1 drivers +v0x15bedf0_0 .net "o1", 0 0, L_0x17f77f0; 1 drivers +v0x15beeb0_0 .net "out", 0 0, L_0x17f7af0; alias, 1 drivers +L_0x17f7690 .part L_0x17f7120, 0, 1; +L_0x17f7900 .part L_0x17f7120, 1, 1; +S_0x162ec30 .scope module, "structadder" "structAddSub" 3 22, 5 8 0, S_0x15daea0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "sub" + .port_info 5 /INPUT 1 "carryin" +L_0x17ed330/d .functor XOR 1, L_0x17f7fb0, v0x17dbbc0_0, C4<0>, C4<0>; +L_0x17ed330 .delay 1 (20000,20000,20000) L_0x17ed330/d; +L_0x17f2830/d .functor XOR 1, L_0x17f7e90, L_0x17f7fb0, C4<0>, C4<0>; +L_0x17f2830 .delay 1 (20000,20000,20000) L_0x17f2830/d; +L_0x17f28f0/d .functor XOR 1, L_0x17f2830, L_0x17f7d60, C4<0>, C4<0>; +L_0x17f28f0 .delay 1 (20000,20000,20000) L_0x17f28f0/d; +L_0x17f2aa0/d .functor AND 1, L_0x17f7e90, L_0x17f7fb0, C4<1>, C4<1>; +L_0x17f2aa0 .delay 1 (20000,20000,20000) L_0x17f2aa0/d; +L_0x17f2c00/d .functor AND 1, L_0x17f2830, L_0x17f7d60, C4<1>, C4<1>; +L_0x17f2c00 .delay 1 (20000,20000,20000) L_0x17f2c00/d; +L_0x17f2d60/d .functor OR 1, L_0x17f2c00, L_0x17f2aa0, C4<0>, C4<0>; +L_0x17f2d60 .delay 1 (20000,20000,20000) L_0x17f2d60/d; +v0x164ec70_0 .net "AandB", 0 0, L_0x17f2aa0; 1 drivers +v0x167ebc0_0 .net "AxorB", 0 0, L_0x17f2830; 1 drivers +v0x167ec80_0 .net "AxorBandCarryIn", 0 0, L_0x17f2c00; 1 drivers +v0x169eb60_0 .net "a", 0 0, L_0x17f7e90; alias, 1 drivers +v0x169ec20_0 .net "b", 0 0, L_0x17f7fb0; alias, 1 drivers +v0x16beb00_0 .net "bnew", 0 0, L_0x17ed330; 1 drivers +v0x16bebc0_0 .net "carryin", 0 0, L_0x17f7d60; alias, 1 drivers +v0x16deaa0_0 .net "carryout", 0 0, L_0x17f2d60; alias, 1 drivers +v0x16deb60_0 .net "sub", 0 0, v0x17dbbc0_0; alias, 1 drivers +v0x16fea40_0 .net "sum", 0 0, L_0x17f28f0; 1 drivers +S_0x1723b20 .scope generate, "ripple[6]" "ripple[6]" 3 66, 3 66 0, S_0x16fa6c0; + .timescale -9 -12; +P_0x1725710 .param/l "i" 0 3 66, +C4<0110>; +S_0x1711ef0 .scope module, "bit" "BitSliceALU" 3 68, 3 11 0, S_0x1723b20; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "ALUout" + .port_info 1 /OUTPUT 1 "Cout" + .port_info 2 /INPUT 1 "invertB" + .port_info 3 /INPUT 1 "Cin" + .port_info 4 /INPUT 3 "addr" + .port_info 5 /INPUT 1 "bit1" + .port_info 6 /INPUT 1 "bit2" +L_0x17f8840/d .functor XOR 1, L_0x17fd6b0, L_0x17fd750, C4<0>, C4<0>; +L_0x17f8840 .delay 1 (20000,20000,20000) L_0x17f8840/d; +L_0x17f89a0/d .functor NAND 1, L_0x17fd6b0, L_0x17fd750, C4<1>, C4<1>; +L_0x17f89a0 .delay 1 (10000,10000,10000) L_0x17f89a0/d; +L_0x17f8b00/d .functor XOR 1, v0x17dbbc0_0, L_0x17f89a0, C4<0>, C4<0>; +L_0x17f8b00 .delay 1 (20000,20000,20000) L_0x17f8b00/d; +L_0x17f8c10/d .functor NOR 1, L_0x17fd6b0, L_0x17fd750, C4<0>, C4<0>; +L_0x17f8c10 .delay 1 (10000,10000,10000) L_0x17f8c10/d; +L_0x17f8d70/d .functor XOR 1, v0x17dbbc0_0, L_0x17f8c10, C4<0>, C4<0>; +L_0x17f8d70 .delay 1 (20000,20000,20000) L_0x17f8d70/d; +v0x1681fb0_0 .net "ALUout", 0 0, L_0x17fd280; 1 drivers +v0x1682070_0 .net "Cin", 0 0, L_0x17fd4f0; 1 drivers +v0x168afa0_0 .net "Cout", 0 0, L_0x17f8690; 1 drivers +v0x168b040_0 .net *"_s11", 0 0, L_0x17f8d70; 1 drivers +o0x7fc2cd913fb8 .functor BUFZ 1, C4; HiZ drive +; Elide local net with no drivers, v0x168ac80_0 name=_s15 +o0x7fc2cd913fe8 .functor BUFZ 3, C4; HiZ drive +; Elide local net with no drivers, v0x168ad20_0 name=_s17 +v0x1689020_0 .net *"_s3", 0 0, L_0x17f8840; 1 drivers +v0x1689100_0 .net *"_s7", 0 0, L_0x17f8b00; 1 drivers +v0x1687580_0 .net "addr", 2 0, v0x17dbc90_0; alias, 1 drivers +v0x1687640_0 .net "bit1", 0 0, L_0x17fd6b0; 1 drivers +v0x1685a80_0 .net "bit2", 0 0, L_0x17fd750; 1 drivers +v0x1685b50_0 .net "invertB", 0 0, v0x17dbbc0_0; alias, 1 drivers +v0x1685770_0 .net "nanded", 0 0, L_0x17f89a0; 1 drivers +v0x1685810_0 .net "nored", 0 0, L_0x17f8c10; 1 drivers +v0x1683d00_0 .net "out", 7 0, L_0x1892480; 1 drivers +LS_0x1892480_0_0 .concat [ 1 1 1 1], L_0x17f8220, L_0x17f8840, o0x7fc2cd913fb8, L_0x17f8b00; +LS_0x1892480_0_4 .concat [ 1 3 0 0], L_0x17f8d70, o0x7fc2cd913fe8; +L_0x1892480 .concat [ 4 4 0 0], LS_0x1892480_0_0, LS_0x1892480_0_4; +S_0x17171e0 .scope module, "opmux" "structuralMultiplexer" 3 43, 4 21 0, S_0x1711ef0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 3 "address" + .port_info 2 /INPUT 8 "in" +v0x16a8fc0_0 .net "address", 2 0, v0x17dbc90_0; alias, 1 drivers +v0x16a9080_0 .net "in", 7 0, L_0x1892480; alias, 1 drivers +v0x16a7520_0 .net "mux", 3 0, L_0x17fb390; 1 drivers +v0x16a75e0_0 .net "muxmid", 1 0, L_0x17fc8b0; 1 drivers +v0x16a5a20_0 .net "out", 0 0, L_0x17fd280; alias, 1 drivers +L_0x17f9670 .part v0x17dbc90_0, 0, 1; +L_0x17f97d0 .part L_0x1892480, 0, 2; +L_0x17fa040 .part v0x17dbc90_0, 0, 1; +L_0x17fa1a0 .part L_0x1892480, 2, 2; +L_0x17fa9f0 .part v0x17dbc90_0, 0, 1; +L_0x17fab50 .part L_0x1892480, 4, 2; +L_0x17fb390 .concat8 [ 1 1 1 1], L_0x17f9510, L_0x17f9ee0, L_0x17fa890, L_0x17fb230; +L_0x17fb5e0 .part v0x17dbc90_0, 0, 1; +L_0x17fb6d0 .part L_0x1892480, 6, 2; +L_0x17fbf10 .part v0x17dbc90_0, 1, 1; +L_0x17fc070 .part L_0x17fb390, 0, 2; +L_0x17fc8b0 .concat8 [ 1 1 0 0], L_0x17fbdb0, L_0x17fc750; +L_0x17fcab0 .part v0x17dbc90_0, 1, 1; +L_0x17fcb50 .part L_0x17fb390, 2, 2; +L_0x17fd390 .part v0x17dbc90_0, 2, 1; +S_0x1703870 .scope module, "mux_0" "bitMultiplexer" 4 29, 4 8 0, S_0x17171e0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "addr" + .port_info 2 /INPUT 2 "in" +L_0x17f8e80/d .functor NOT 1, L_0x17f9670, C4<0>, C4<0>, C4<0>; +L_0x17f8e80 .delay 1 (10000,10000,10000) L_0x17f8e80/d; +L_0x17f8fe0/d .functor AND 1, L_0x17f90f0, L_0x17f8e80, C4<1>, C4<1>; +L_0x17f8fe0 .delay 1 (20000,20000,20000) L_0x17f8fe0/d; +L_0x17f9250/d .functor AND 1, L_0x17f9360, L_0x17f9670, C4<1>, C4<1>; +L_0x17f9250 .delay 1 (20000,20000,20000) L_0x17f9250/d; +L_0x17f9510/d .functor OR 1, L_0x17f8fe0, L_0x17f9250, C4<0>, C4<0>; +L_0x17f9510 .delay 1 (20000,20000,20000) L_0x17f9510/d; +v0x1711c60_0 .net *"_s1", 0 0, L_0x17f90f0; 1 drivers +v0x170ae20_0 .net *"_s3", 0 0, L_0x17f9360; 1 drivers +v0x170af00_0 .net "addr", 0 0, L_0x17f9670; 1 drivers +v0x170ab00_0 .net "in", 1 0, L_0x17f97d0; 1 drivers +v0x170abe0_0 .net "naddr", 0 0, L_0x17f8e80; 1 drivers +v0x1708ea0_0 .net "o0", 0 0, L_0x17f8fe0; 1 drivers +v0x1708f60_0 .net "o1", 0 0, L_0x17f9250; 1 drivers +v0x1707400_0 .net "out", 0 0, L_0x17f9510; 1 drivers +L_0x17f90f0 .part L_0x17f97d0, 0, 1; +L_0x17f9360 .part L_0x17f97d0, 1, 1; +S_0x1705900 .scope module, "mux_1" "bitMultiplexer" 4 30, 4 8 0, S_0x17171e0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "addr" + .port_info 2 /INPUT 2 "in" +L_0x17f9870/d .functor NOT 1, L_0x17fa040, C4<0>, C4<0>, C4<0>; +L_0x17f9870 .delay 1 (10000,10000,10000) L_0x17f9870/d; +L_0x17f9930/d .functor AND 1, L_0x17f9a90, L_0x17f9870, C4<1>, C4<1>; +L_0x17f9930 .delay 1 (20000,20000,20000) L_0x17f9930/d; +L_0x17f9bf0/d .functor AND 1, L_0x17f9d30, L_0x17fa040, C4<1>, C4<1>; +L_0x17f9bf0 .delay 1 (20000,20000,20000) L_0x17f9bf0/d; +L_0x17f9ee0/d .functor OR 1, L_0x17f9930, L_0x17f9bf0, C4<0>, C4<0>; +L_0x17f9ee0 .delay 1 (20000,20000,20000) L_0x17f9ee0/d; +v0x17055f0_0 .net *"_s1", 0 0, L_0x17f9a90; 1 drivers +v0x17056f0_0 .net *"_s3", 0 0, L_0x17f9d30; 1 drivers +v0x1703b80_0 .net "addr", 0 0, L_0x17fa040; 1 drivers +v0x1703c70_0 .net "in", 1 0, L_0x17fa1a0; 1 drivers +v0x16f1f50_0 .net "naddr", 0 0, L_0x17f9870; 1 drivers +v0x16f2060_0 .net "o0", 0 0, L_0x17f9930; 1 drivers +v0x16f1c10_0 .net "o1", 0 0, L_0x17f9bf0; 1 drivers +v0x16f1cd0_0 .net "out", 0 0, L_0x17f9ee0; 1 drivers +L_0x17f9a90 .part L_0x17fa1a0, 0, 1; +L_0x17f9d30 .part L_0x17fa1a0, 1, 1; +S_0x16f7240 .scope module, "mux_2" "bitMultiplexer" 4 31, 4 8 0, S_0x17171e0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "addr" + .port_info 2 /INPUT 2 "in" +L_0x17fa0e0/d .functor NOT 1, L_0x17fa9f0, C4<0>, C4<0>, C4<0>; +L_0x17fa0e0 .delay 1 (10000,10000,10000) L_0x17fa0e0/d; +L_0x17fa290/d .functor AND 1, L_0x17fa440, L_0x17fa0e0, C4<1>, C4<1>; +L_0x17fa290 .delay 1 (20000,20000,20000) L_0x17fa290/d; +L_0x17fa5a0/d .functor AND 1, L_0x17fa6e0, L_0x17fa9f0, C4<1>, C4<1>; +L_0x17fa5a0 .delay 1 (20000,20000,20000) L_0x17fa5a0/d; +L_0x17fa890/d .functor OR 1, L_0x17fa290, L_0x17fa5a0, C4<0>, C4<0>; +L_0x17fa890 .delay 1 (20000,20000,20000) L_0x17fa890/d; +v0x16e3920_0 .net *"_s1", 0 0, L_0x17fa440; 1 drivers +v0x16e3a00_0 .net *"_s3", 0 0, L_0x17fa6e0; 1 drivers +v0x16eae80_0 .net "addr", 0 0, L_0x17fa9f0; 1 drivers +v0x16eaf20_0 .net "in", 1 0, L_0x17fab50; 1 drivers +v0x16eab60_0 .net "naddr", 0 0, L_0x17fa0e0; 1 drivers +v0x16eac20_0 .net "o0", 0 0, L_0x17fa290; 1 drivers +v0x16e8f00_0 .net "o1", 0 0, L_0x17fa5a0; 1 drivers +v0x16e8fc0_0 .net "out", 0 0, L_0x17fa890; 1 drivers +L_0x17fa440 .part L_0x17fab50, 0, 1; +L_0x17fa6e0 .part L_0x17fab50, 1, 1; +S_0x16e7460 .scope module, "mux_3" "bitMultiplexer" 4 32, 4 8 0, S_0x17171e0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "addr" + .port_info 2 /INPUT 2 "in" +L_0x17faa90/d .functor NOT 1, L_0x17fb5e0, C4<0>, C4<0>, C4<0>; +L_0x17faa90 .delay 1 (10000,10000,10000) L_0x17faa90/d; +L_0x17fac80/d .functor AND 1, L_0x17fade0, L_0x17faa90, C4<1>, C4<1>; +L_0x17fac80 .delay 1 (20000,20000,20000) L_0x17fac80/d; +L_0x17faf40/d .functor AND 1, L_0x17fb080, L_0x17fb5e0, C4<1>, C4<1>; +L_0x17faf40 .delay 1 (20000,20000,20000) L_0x17faf40/d; +L_0x17fb230/d .functor OR 1, L_0x17fac80, L_0x17faf40, C4<0>, C4<0>; +L_0x17fb230 .delay 1 (20000,20000,20000) L_0x17fb230/d; +v0x16e59b0_0 .net *"_s1", 0 0, L_0x17fade0; 1 drivers +v0x16e5650_0 .net *"_s3", 0 0, L_0x17fb080; 1 drivers +v0x16e5730_0 .net "addr", 0 0, L_0x17fb5e0; 1 drivers +v0x16e3be0_0 .net "in", 1 0, L_0x17fb6d0; 1 drivers +v0x16e3cc0_0 .net "naddr", 0 0, L_0x17faa90; 1 drivers +v0x16d1fb0_0 .net "o0", 0 0, L_0x17fac80; 1 drivers +v0x16d2070_0 .net "o1", 0 0, L_0x17faf40; 1 drivers +v0x16d1c70_0 .net "out", 0 0, L_0x17fb230; 1 drivers +L_0x17fade0 .part L_0x17fb6d0, 0, 1; +L_0x17fb080 .part L_0x17fb6d0, 1, 1; +S_0x16d72a0 .scope module, "mux_mid_0" "bitMultiplexer" 4 33, 4 8 0, S_0x17171e0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "addr" + .port_info 2 /INPUT 2 "in" +L_0x17fb770/d .functor NOT 1, L_0x17fbf10, C4<0>, C4<0>, C4<0>; +L_0x17fb770 .delay 1 (10000,10000,10000) L_0x17fb770/d; +L_0x17fb830/d .functor AND 1, L_0x17fb990, L_0x17fb770, C4<1>, C4<1>; +L_0x17fb830 .delay 1 (20000,20000,20000) L_0x17fb830/d; +L_0x17fbaf0/d .functor AND 1, L_0x17fbc00, L_0x17fbf10, C4<1>, C4<1>; +L_0x17fbaf0 .delay 1 (20000,20000,20000) L_0x17fbaf0/d; +L_0x17fbdb0/d .functor OR 1, L_0x17fb830, L_0x17fbaf0, C4<0>, C4<0>; +L_0x17fbdb0 .delay 1 (20000,20000,20000) L_0x17fbdb0/d; +v0x16c3930_0 .net *"_s1", 0 0, L_0x17fb990; 1 drivers +v0x16c3a30_0 .net *"_s3", 0 0, L_0x17fbc00; 1 drivers +v0x16caee0_0 .net "addr", 0 0, L_0x17fbf10; 1 drivers +v0x16cafa0_0 .net "in", 1 0, L_0x17fc070; 1 drivers +v0x16cabc0_0 .net "naddr", 0 0, L_0x17fb770; 1 drivers +v0x16cacd0_0 .net "o0", 0 0, L_0x17fb830; 1 drivers +v0x16c8f60_0 .net "o1", 0 0, L_0x17fbaf0; 1 drivers +v0x16c9020_0 .net "out", 0 0, L_0x17fbdb0; 1 drivers +L_0x17fb990 .part L_0x17fc070, 0, 1; +L_0x17fbc00 .part L_0x17fc070, 1, 1; +S_0x16c74c0 .scope module, "mux_mid_1" "bitMultiplexer" 4 34, 4 8 0, S_0x17171e0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "addr" + .port_info 2 /INPUT 2 "in" +L_0x17fc110/d .functor NOT 1, L_0x17fcab0, C4<0>, C4<0>, C4<0>; +L_0x17fc110 .delay 1 (10000,10000,10000) L_0x17fc110/d; +L_0x17fc1d0/d .functor AND 1, L_0x17fc330, L_0x17fc110, C4<1>, C4<1>; +L_0x17fc1d0 .delay 1 (20000,20000,20000) L_0x17fc1d0/d; +L_0x17fc490/d .functor AND 1, L_0x17fc5a0, L_0x17fcab0, C4<1>, C4<1>; +L_0x17fc490 .delay 1 (20000,20000,20000) L_0x17fc490/d; +L_0x17fc750/d .functor OR 1, L_0x17fc1d0, L_0x17fc490, C4<0>, C4<0>; +L_0x17fc750 .delay 1 (20000,20000,20000) L_0x17fc750/d; +v0x16c5a60_0 .net *"_s1", 0 0, L_0x17fc330; 1 drivers +v0x16c56b0_0 .net *"_s3", 0 0, L_0x17fc5a0; 1 drivers +v0x16c5790_0 .net "addr", 0 0, L_0x17fcab0; 1 drivers +v0x16c3c40_0 .net "in", 1 0, L_0x17fcb50; 1 drivers +v0x16c3d20_0 .net "naddr", 0 0, L_0x17fc110; 1 drivers +v0x16b2010_0 .net "o0", 0 0, L_0x17fc1d0; 1 drivers +v0x16b20d0_0 .net "o1", 0 0, L_0x17fc490; 1 drivers +v0x16b1cd0_0 .net "out", 0 0, L_0x17fc750; 1 drivers +L_0x17fc330 .part L_0x17fcb50, 0, 1; +L_0x17fc5a0 .part L_0x17fcb50, 1, 1; +S_0x16b7300 .scope module, "mux_out" "bitMultiplexer" 4 35, 4 8 0, S_0x17171e0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "addr" + .port_info 2 /INPUT 2 "in" +L_0x17fbfb0/d .functor NOT 1, L_0x17fd390, C4<0>, C4<0>, C4<0>; +L_0x17fbfb0 .delay 1 (10000,10000,10000) L_0x17fbfb0/d; +L_0x17fccc0/d .functor AND 1, L_0x17fce20, L_0x17fbfb0, C4<1>, C4<1>; +L_0x17fccc0 .delay 1 (20000,20000,20000) L_0x17fccc0/d; +L_0x17fcf80/d .functor AND 1, L_0x17fd090, L_0x17fd390, C4<1>, C4<1>; +L_0x17fcf80 .delay 1 (20000,20000,20000) L_0x17fcf80/d; +L_0x17fd280/d .functor OR 1, L_0x17fccc0, L_0x17fcf80, C4<0>, C4<0>; +L_0x17fd280 .delay 1 (20000,20000,20000) L_0x17fd280/d; +v0x16a3990_0 .net *"_s1", 0 0, L_0x17fce20; 1 drivers +v0x16a3a90_0 .net *"_s3", 0 0, L_0x17fd090; 1 drivers +v0x16a1f50_0 .net "addr", 0 0, L_0x17fd390; 1 drivers +v0x16a2010_0 .net "in", 1 0, L_0x17fc8b0; alias, 1 drivers +v0x16aaf40_0 .net "naddr", 0 0, L_0x17fbfb0; 1 drivers +v0x16ab050_0 .net "o0", 0 0, L_0x17fccc0; 1 drivers +v0x16aac20_0 .net "o1", 0 0, L_0x17fcf80; 1 drivers +v0x16aace0_0 .net "out", 0 0, L_0x17fd280; alias, 1 drivers +L_0x17fce20 .part L_0x17fc8b0, 0, 1; +L_0x17fd090 .part L_0x17fc8b0, 1, 1; +S_0x16a5710 .scope module, "structadder" "structAddSub" 3 22, 5 8 0, S_0x1711ef0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "sub" + .port_info 5 /INPUT 1 "carryin" +L_0x17f2360/d .functor XOR 1, L_0x17fd750, v0x17dbbc0_0, C4<0>, C4<0>; +L_0x17f2360 .delay 1 (20000,20000,20000) L_0x17f2360/d; +L_0x17f8160/d .functor XOR 1, L_0x17fd6b0, L_0x17fd750, C4<0>, C4<0>; +L_0x17f8160 .delay 1 (20000,20000,20000) L_0x17f8160/d; +L_0x17f8220/d .functor XOR 1, L_0x17f8160, L_0x17fd4f0, C4<0>, C4<0>; +L_0x17f8220 .delay 1 (20000,20000,20000) L_0x17f8220/d; +L_0x17f83d0/d .functor AND 1, L_0x17fd6b0, L_0x17fd750, C4<1>, C4<1>; +L_0x17f83d0 .delay 1 (20000,20000,20000) L_0x17f83d0/d; +L_0x17f8530/d .functor AND 1, L_0x17f8160, L_0x17fd4f0, C4<1>, C4<1>; +L_0x17f8530 .delay 1 (20000,20000,20000) L_0x17f8530/d; +L_0x17f8690/d .functor OR 1, L_0x17f8530, L_0x17f83d0, C4<0>, C4<0>; +L_0x17f8690 .delay 1 (20000,20000,20000) L_0x17f8690/d; +v0x16a3ca0_0 .net "AandB", 0 0, L_0x17f83d0; 1 drivers +v0x16a3d60_0 .net "AxorB", 0 0, L_0x17f8160; 1 drivers +v0x1692070_0 .net "AxorBandCarryIn", 0 0, L_0x17f8530; 1 drivers +v0x1692110_0 .net "a", 0 0, L_0x17fd6b0; alias, 1 drivers +v0x1691d30_0 .net "b", 0 0, L_0x17fd750; alias, 1 drivers +v0x1691df0_0 .net "bnew", 0 0, L_0x17f2360; 1 drivers +v0x1697360_0 .net "carryin", 0 0, L_0x17fd4f0; alias, 1 drivers +v0x1697420_0 .net "carryout", 0 0, L_0x17f8690; alias, 1 drivers +v0x16839f0_0 .net "sub", 0 0, v0x17dbbc0_0; alias, 1 drivers +v0x1683b20_0 .net "sum", 0 0, L_0x17f8220; 1 drivers +S_0x1671d90 .scope generate, "ripple[7]" "ripple[7]" 3 66, 3 66 0, S_0x16fa6c0; + .timescale -9 -12; +P_0x16974e0 .param/l "i" 0 3 66, +C4<0111>; +S_0x16773c0 .scope module, "bit" "BitSliceALU" 3 68, 3 11 0, S_0x1671d90; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "ALUout" + .port_info 1 /OUTPUT 1 "Cout" + .port_info 2 /INPUT 1 "invertB" + .port_info 3 /INPUT 1 "Cin" + .port_info 4 /INPUT 3 "addr" + .port_info 5 /INPUT 1 "bit1" + .port_info 6 /INPUT 1 "bit2" +L_0x17fe080/d .functor XOR 1, L_0x1802e20, L_0x17f8440, C4<0>, C4<0>; +L_0x17fe080 .delay 1 (20000,20000,20000) L_0x17fe080/d; +L_0x17fe1e0/d .functor NAND 1, L_0x1802e20, L_0x17f8440, C4<1>, C4<1>; +L_0x17fe1e0 .delay 1 (10000,10000,10000) L_0x17fe1e0/d; +L_0x17fe340/d .functor XOR 1, v0x17dbbc0_0, L_0x17fe1e0, C4<0>, C4<0>; +L_0x17fe340 .delay 1 (20000,20000,20000) L_0x17fe340/d; +L_0x17fe450/d .functor NOR 1, L_0x1802e20, L_0x17f8440, C4<0>, C4<0>; +L_0x17fe450 .delay 1 (10000,10000,10000) L_0x17fe450/d; +L_0x17fe5b0/d .functor XOR 1, v0x17dbbc0_0, L_0x17fe450, C4<0>, C4<0>; +L_0x17fe5b0 .delay 1 (20000,20000,20000) L_0x17fe5b0/d; +v0x15eb1b0_0 .net "ALUout", 0 0, L_0x1802a80; 1 drivers +v0x15eb250_0 .net "Cin", 0 0, L_0x1802cf0; 1 drivers +v0x15eae90_0 .net "Cout", 0 0, L_0x17fded0; 1 drivers +v0x15eaf30_0 .net *"_s11", 0 0, L_0x17fe5b0; 1 drivers +o0x7fc2cd915488 .functor BUFZ 1, C4; HiZ drive +; Elide local net with no drivers, v0x15e1e70_0 name=_s15 +o0x7fc2cd9154b8 .functor BUFZ 3, C4; HiZ drive +; Elide local net with no drivers, v0x15e1f10_0 name=_s17 +v0x15e9230_0 .net *"_s3", 0 0, L_0x17fe080; 1 drivers +v0x15e9310_0 .net *"_s7", 0 0, L_0x17fe340; 1 drivers +v0x15e7790_0 .net "addr", 2 0, v0x17dbc90_0; alias, 1 drivers +v0x15e7850_0 .net "bit1", 0 0, L_0x1802e20; 1 drivers +v0x15e5c90_0 .net "bit2", 0 0, L_0x17f8440; 1 drivers +v0x15e5d60_0 .net "invertB", 0 0, v0x17dbbc0_0; alias, 1 drivers +v0x15e5980_0 .net "nanded", 0 0, L_0x17fe1e0; 1 drivers +v0x15e5a20_0 .net "nored", 0 0, L_0x17fe450; 1 drivers +v0x15e3f10_0 .net "out", 7 0, L_0x1892520; 1 drivers +LS_0x1892520_0_0 .concat [ 1 1 1 1], L_0x17fda60, L_0x17fe080, o0x7fc2cd915488, L_0x17fe340; +LS_0x1892520_0_4 .concat [ 1 3 0 0], L_0x17fe5b0, o0x7fc2cd9154b8; +L_0x1892520 .concat [ 4 4 0 0], LS_0x1892520_0_0, LS_0x1892520_0_4; +S_0x1662010 .scope module, "opmux" "structuralMultiplexer" 3 43, 4 21 0, S_0x16773c0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 3 "address" + .port_info 2 /INPUT 8 "in" +v0x1607720_0 .net "address", 2 0, v0x17dbc90_0; alias, 1 drivers +v0x16077c0_0 .net "in", 7 0, L_0x1892520; alias, 1 drivers +v0x1605c20_0 .net "mux", 3 0, L_0x1800c10; 1 drivers +v0x1605ce0_0 .net "muxmid", 1 0, L_0x1802130; 1 drivers +v0x1605910_0 .net "out", 0 0, L_0x1802a80; alias, 1 drivers +L_0x17feeb0 .part v0x17dbc90_0, 0, 1; +L_0x17ff010 .part L_0x1892520, 0, 2; +L_0x17ff850 .part v0x17dbc90_0, 0, 1; +L_0x17ff9b0 .part L_0x1892520, 2, 2; +L_0x1800220 .part v0x17dbc90_0, 0, 1; +L_0x1800380 .part L_0x1892520, 4, 2; +L_0x1800c10 .concat8 [ 1 1 1 1], L_0x17fed50, L_0x17ff6f0, L_0x18000c0, L_0x1800ab0; +L_0x1800e60 .part v0x17dbc90_0, 0, 1; +L_0x1800f50 .part L_0x1892520, 6, 2; +L_0x1801790 .part v0x17dbc90_0, 1, 1; +L_0x18018f0 .part L_0x1800c10, 0, 2; +L_0x1802130 .concat8 [ 1 1 0 0], L_0x1801630, L_0x1801fd0; +L_0x1802330 .part v0x17dbc90_0, 1, 1; +L_0x18023d0 .part L_0x1800c10, 2, 2; +L_0x1802b90 .part v0x17dbc90_0, 2, 1; +S_0x166b000 .scope module, "mux_0" "bitMultiplexer" 4 29, 4 8 0, S_0x1662010; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "addr" + .port_info 2 /INPUT 2 "in" +L_0x17fe6c0/d .functor NOT 1, L_0x17feeb0, C4<0>, C4<0>, C4<0>; +L_0x17fe6c0 .delay 1 (10000,10000,10000) L_0x17fe6c0/d; +L_0x17fe820/d .functor AND 1, L_0x17fe930, L_0x17fe6c0, C4<1>, C4<1>; +L_0x17fe820 .delay 1 (20000,20000,20000) L_0x17fe820/d; +L_0x17fea90/d .functor AND 1, L_0x17feba0, L_0x17feeb0, C4<1>, C4<1>; +L_0x17fea90 .delay 1 (20000,20000,20000) L_0x17fea90/d; +L_0x17fed50/d .functor OR 1, L_0x17fe820, L_0x17fea90, C4<0>, C4<0>; +L_0x17fed50 .delay 1 (20000,20000,20000) L_0x17fed50/d; +v0x1663b00_0 .net *"_s1", 0 0, L_0x17fe930; 1 drivers +v0x166ace0_0 .net *"_s3", 0 0, L_0x17feba0; 1 drivers +v0x166ada0_0 .net "addr", 0 0, L_0x17feeb0; 1 drivers +v0x1669080_0 .net "in", 1 0, L_0x17ff010; 1 drivers +v0x1669160_0 .net "naddr", 0 0, L_0x17fe6c0; 1 drivers +v0x16675e0_0 .net "o0", 0 0, L_0x17fe820; 1 drivers +v0x1667680_0 .net "o1", 0 0, L_0x17fea90; 1 drivers +v0x1665ae0_0 .net "out", 0 0, L_0x17fed50; 1 drivers +L_0x17fe930 .part L_0x17ff010, 0, 1; +L_0x17feba0 .part L_0x17ff010, 1, 1; +S_0x16657d0 .scope module, "mux_1" "bitMultiplexer" 4 30, 4 8 0, S_0x1662010; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "addr" + .port_info 2 /INPUT 2 "in" +L_0x17ff0b0/d .functor NOT 1, L_0x17ff850, C4<0>, C4<0>, C4<0>; +L_0x17ff0b0 .delay 1 (10000,10000,10000) L_0x17ff0b0/d; +L_0x17ff170/d .functor AND 1, L_0x17ff2d0, L_0x17ff0b0, C4<1>, C4<1>; +L_0x17ff170 .delay 1 (20000,20000,20000) L_0x17ff170/d; +L_0x17ff430/d .functor AND 1, L_0x17ff540, L_0x17ff850, C4<1>, C4<1>; +L_0x17ff430 .delay 1 (20000,20000,20000) L_0x17ff430/d; +L_0x17ff6f0/d .functor OR 1, L_0x17ff170, L_0x17ff430, C4<0>, C4<0>; +L_0x17ff6f0 .delay 1 (20000,20000,20000) L_0x17ff6f0/d; +v0x1663d60_0 .net *"_s1", 0 0, L_0x17ff2d0; 1 drivers +v0x1663e40_0 .net *"_s3", 0 0, L_0x17ff540; 1 drivers +v0x1651df0_0 .net "addr", 0 0, L_0x17ff850; 1 drivers +v0x1651e90_0 .net "in", 1 0, L_0x17ff9b0; 1 drivers +v0x1657420_0 .net "naddr", 0 0, L_0x17ff0b0; 1 drivers +v0x16574e0_0 .net "o0", 0 0, L_0x17ff170; 1 drivers +v0x1643ab0_0 .net "o1", 0 0, L_0x17ff430; 1 drivers +v0x1643b70_0 .net "out", 0 0, L_0x17ff6f0; 1 drivers +L_0x17ff2d0 .part L_0x17ff9b0, 0, 1; +L_0x17ff540 .part L_0x17ff9b0, 1, 1; +S_0x1642070 .scope module, "mux_2" "bitMultiplexer" 4 31, 4 8 0, S_0x1662010; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "addr" + .port_info 2 /INPUT 2 "in" +L_0x17ff8f0/d .functor NOT 1, L_0x1800220, C4<0>, C4<0>, C4<0>; +L_0x17ff8f0 .delay 1 (10000,10000,10000) L_0x17ff8f0/d; +L_0x17ffaa0/d .functor AND 1, L_0x17ffca0, L_0x17ff8f0, C4<1>, C4<1>; +L_0x17ffaa0 .delay 1 (20000,20000,20000) L_0x17ffaa0/d; +L_0x17ffe00/d .functor AND 1, L_0x17fff10, L_0x1800220, C4<1>, C4<1>; +L_0x17ffe00 .delay 1 (20000,20000,20000) L_0x17ffe00/d; +L_0x18000c0/d .functor OR 1, L_0x17ffaa0, L_0x17ffe00, C4<0>, C4<0>; +L_0x18000c0 .delay 1 (20000,20000,20000) L_0x18000c0/d; +v0x164b0b0_0 .net *"_s1", 0 0, L_0x17ffca0; 1 drivers +v0x164b190_0 .net *"_s3", 0 0, L_0x17fff10; 1 drivers +v0x164ad40_0 .net "addr", 0 0, L_0x1800220; 1 drivers +v0x164ae10_0 .net "in", 1 0, L_0x1800380; 1 drivers +v0x16490e0_0 .net "naddr", 0 0, L_0x17ff8f0; 1 drivers +v0x16491d0_0 .net "o0", 0 0, L_0x17ffaa0; 1 drivers +v0x1647640_0 .net "o1", 0 0, L_0x17ffe00; 1 drivers +v0x16476e0_0 .net "out", 0 0, L_0x18000c0; 1 drivers +L_0x17ffca0 .part L_0x1800380, 0, 1; +L_0x17fff10 .part L_0x1800380, 1, 1; +S_0x1645b40 .scope module, "mux_3" "bitMultiplexer" 4 32, 4 8 0, S_0x1662010; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "addr" + .port_info 2 /INPUT 2 "in" +L_0x18002c0/d .functor NOT 1, L_0x1800e60, C4<0>, C4<0>, C4<0>; +L_0x18002c0 .delay 1 (10000,10000,10000) L_0x18002c0/d; +L_0x18004b0/d .functor AND 1, L_0x1800660, L_0x18002c0, C4<1>, C4<1>; +L_0x18004b0 .delay 1 (20000,20000,20000) L_0x18004b0/d; +L_0x18007c0/d .functor AND 1, L_0x1800900, L_0x1800e60, C4<1>, C4<1>; +L_0x18007c0 .delay 1 (20000,20000,20000) L_0x18007c0/d; +L_0x1800ab0/d .functor OR 1, L_0x18004b0, L_0x18007c0, C4<0>, C4<0>; +L_0x1800ab0 .delay 1 (20000,20000,20000) L_0x1800ab0/d; +v0x16458d0_0 .net *"_s1", 0 0, L_0x1800660; 1 drivers +v0x1643dc0_0 .net *"_s3", 0 0, L_0x1800900; 1 drivers +v0x1643ea0_0 .net "addr", 0 0, L_0x1800e60; 1 drivers +v0x1631e50_0 .net "in", 1 0, L_0x1800f50; 1 drivers +v0x1631f30_0 .net "naddr", 0 0, L_0x18002c0; 1 drivers +v0x1637480_0 .net "o0", 0 0, L_0x18004b0; 1 drivers +v0x1637540_0 .net "o1", 0 0, L_0x18007c0; 1 drivers +v0x1623b20_0 .net "out", 0 0, L_0x1800ab0; 1 drivers +L_0x1800660 .part L_0x1800f50, 0, 1; +L_0x1800900 .part L_0x1800f50, 1, 1; +S_0x16220e0 .scope module, "mux_mid_0" "bitMultiplexer" 4 33, 4 8 0, S_0x1662010; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "addr" + .port_info 2 /INPUT 2 "in" +L_0x1800ff0/d .functor NOT 1, L_0x1801790, C4<0>, C4<0>, C4<0>; +L_0x1800ff0 .delay 1 (10000,10000,10000) L_0x1800ff0/d; +L_0x18010b0/d .functor AND 1, L_0x1801210, L_0x1800ff0, C4<1>, C4<1>; +L_0x18010b0 .delay 1 (20000,20000,20000) L_0x18010b0/d; +L_0x1801370/d .functor AND 1, L_0x1801480, L_0x1801790, C4<1>, C4<1>; +L_0x1801370 .delay 1 (20000,20000,20000) L_0x1801370/d; +L_0x1801630/d .functor OR 1, L_0x18010b0, L_0x1801370, C4<0>, C4<0>; +L_0x1801630 .delay 1 (20000,20000,20000) L_0x1801630/d; +v0x162b0d0_0 .net *"_s1", 0 0, L_0x1801210; 1 drivers +v0x162b1d0_0 .net *"_s3", 0 0, L_0x1801480; 1 drivers +v0x162adb0_0 .net "addr", 0 0, L_0x1801790; 1 drivers +v0x162ae70_0 .net "in", 1 0, L_0x18018f0; 1 drivers +v0x1629150_0 .net "naddr", 0 0, L_0x1800ff0; 1 drivers +v0x1629260_0 .net "o0", 0 0, L_0x18010b0; 1 drivers +v0x16276b0_0 .net "o1", 0 0, L_0x1801370; 1 drivers +v0x1627770_0 .net "out", 0 0, L_0x1801630; 1 drivers +L_0x1801210 .part L_0x18018f0, 0, 1; +L_0x1801480 .part L_0x18018f0, 1, 1; +S_0x1625bb0 .scope module, "mux_mid_1" "bitMultiplexer" 4 34, 4 8 0, S_0x1662010; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "addr" + .port_info 2 /INPUT 2 "in" +L_0x1801990/d .functor NOT 1, L_0x1802330, C4<0>, C4<0>, C4<0>; +L_0x1801990 .delay 1 (10000,10000,10000) L_0x1801990/d; +L_0x1801a50/d .functor AND 1, L_0x1801bb0, L_0x1801990, C4<1>, C4<1>; +L_0x1801a50 .delay 1 (20000,20000,20000) L_0x1801a50/d; +L_0x1801d10/d .functor AND 1, L_0x1801e20, L_0x1802330, C4<1>, C4<1>; +L_0x1801d10 .delay 1 (20000,20000,20000) L_0x1801d10/d; +L_0x1801fd0/d .functor OR 1, L_0x1801a50, L_0x1801d10, C4<0>, C4<0>; +L_0x1801fd0 .delay 1 (20000,20000,20000) L_0x1801fd0/d; +v0x1625940_0 .net *"_s1", 0 0, L_0x1801bb0; 1 drivers +v0x1623e30_0 .net *"_s3", 0 0, L_0x1801e20; 1 drivers +v0x1623f10_0 .net "addr", 0 0, L_0x1802330; 1 drivers +v0x161d580_0 .net "in", 1 0, L_0x18023d0; 1 drivers +v0x161d660_0 .net "naddr", 0 0, L_0x1801990; 1 drivers +v0x1611ec0_0 .net "o0", 0 0, L_0x1801a50; 1 drivers +v0x1611f80_0 .net "o1", 0 0, L_0x1801d10; 1 drivers +v0x16174f0_0 .net "out", 0 0, L_0x1801fd0; 1 drivers +L_0x1801bb0 .part L_0x18023d0, 0, 1; +L_0x1801e20 .part L_0x18023d0, 1, 1; +S_0x1603b90 .scope module, "mux_out" "bitMultiplexer" 4 35, 4 8 0, S_0x1662010; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "addr" + .port_info 2 /INPUT 2 "in" +L_0x1801830/d .functor NOT 1, L_0x1802b90, C4<0>, C4<0>, C4<0>; +L_0x1801830 .delay 1 (10000,10000,10000) L_0x1801830/d; +L_0x18024c0/d .functor AND 1, L_0x1802620, L_0x1801830, C4<1>, C4<1>; +L_0x18024c0 .delay 1 (20000,20000,20000) L_0x18024c0/d; +L_0x1802780/d .functor AND 1, L_0x1802890, L_0x1802b90, C4<1>, C4<1>; +L_0x1802780 .delay 1 (20000,20000,20000) L_0x1802780/d; +L_0x1802a80/d .functor OR 1, L_0x18024c0, L_0x1802780, C4<0>, C4<0>; +L_0x1802a80 .delay 1 (20000,20000,20000) L_0x1802a80/d; +v0x1602150_0 .net *"_s1", 0 0, L_0x1802620; 1 drivers +v0x1602250_0 .net *"_s3", 0 0, L_0x1802890; 1 drivers +v0x160b140_0 .net "addr", 0 0, L_0x1802b90; 1 drivers +v0x160b200_0 .net "in", 1 0, L_0x1802130; alias, 1 drivers +v0x160ae20_0 .net "naddr", 0 0, L_0x1801830; 1 drivers +v0x160af30_0 .net "o0", 0 0, L_0x18024c0; 1 drivers +v0x16091c0_0 .net "o1", 0 0, L_0x1802780; 1 drivers +v0x1609280_0 .net "out", 0 0, L_0x1802a80; alias, 1 drivers +L_0x1802620 .part L_0x1802130, 0, 1; +L_0x1802890 .part L_0x1802130, 1, 1; +S_0x1603ea0 .scope module, "structadder" "structAddSub" 3 22, 5 8 0, S_0x16773c0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "sub" + .port_info 5 /INPUT 1 "carryin" +L_0x17fd430/d .functor XOR 1, L_0x17f8440, v0x17dbbc0_0, C4<0>, C4<0>; +L_0x17fd430 .delay 1 (20000,20000,20000) L_0x17fd430/d; +L_0x17fd900/d .functor XOR 1, L_0x1802e20, L_0x17f8440, C4<0>, C4<0>; +L_0x17fd900 .delay 1 (20000,20000,20000) L_0x17fd900/d; +L_0x17fda60/d .functor XOR 1, L_0x17fd900, L_0x1802cf0, C4<0>, C4<0>; +L_0x17fda60 .delay 1 (20000,20000,20000) L_0x17fda60/d; +L_0x17fdc10/d .functor AND 1, L_0x1802e20, L_0x17f8440, C4<1>, C4<1>; +L_0x17fdc10 .delay 1 (20000,20000,20000) L_0x17fdc10/d; +L_0x17fdd70/d .functor AND 1, L_0x17fd900, L_0x1802cf0, C4<1>, C4<1>; +L_0x17fdd70 .delay 1 (20000,20000,20000) L_0x17fdd70/d; +L_0x17fded0/d .functor OR 1, L_0x17fdd70, L_0x17fdc10, C4<0>, C4<0>; +L_0x17fded0 .delay 1 (20000,20000,20000) L_0x17fded0/d; +v0x15fd5f0_0 .net "AandB", 0 0, L_0x17fdc10; 1 drivers +v0x15fd6b0_0 .net "AxorB", 0 0, L_0x17fd900; 1 drivers +v0x15f1f30_0 .net "AxorBandCarryIn", 0 0, L_0x17fdd70; 1 drivers +v0x15f1fd0_0 .net "a", 0 0, L_0x1802e20; alias, 1 drivers +v0x15f7560_0 .net "b", 0 0, L_0x17f8440; alias, 1 drivers +v0x15f7620_0 .net "bnew", 0 0, L_0x17fd430; 1 drivers +v0x15e3c00_0 .net "carryin", 0 0, L_0x1802cf0; alias, 1 drivers +v0x15e3cc0_0 .net "carryout", 0 0, L_0x17fded0; alias, 1 drivers +v0x15e21c0_0 .net "sub", 0 0, v0x17dbbc0_0; alias, 1 drivers +v0x15e2260_0 .net "sum", 0 0, L_0x17fda60; 1 drivers +S_0x15dd650 .scope generate, "ripple[8]" "ripple[8]" 3 66, 3 66 0, S_0x16fa6c0; + .timescale -9 -12; +P_0x15f76e0 .param/l "i" 0 3 66, +C4<01000>; +S_0x15d1f90 .scope module, "bit" "BitSliceALU" 3 68, 3 11 0, S_0x15dd650; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "ALUout" + .port_info 1 /OUTPUT 1 "Cout" + .port_info 2 /INPUT 1 "invertB" + .port_info 3 /INPUT 1 "Cin" + .port_info 4 /INPUT 3 "addr" + .port_info 5 /INPUT 1 "bit1" + .port_info 6 /INPUT 1 "bit2" +L_0x1803910/d .functor XOR 1, L_0x1802fd0, L_0x18088b0, C4<0>, C4<0>; +L_0x1803910 .delay 1 (20000,20000,20000) L_0x1803910/d; +L_0x1803a70/d .functor NAND 1, L_0x1802fd0, L_0x18088b0, C4<1>, C4<1>; +L_0x1803a70 .delay 1 (10000,10000,10000) L_0x1803a70/d; +L_0x1803bd0/d .functor XOR 1, v0x17dbbc0_0, L_0x1803a70, C4<0>, C4<0>; +L_0x1803bd0 .delay 1 (20000,20000,20000) L_0x1803bd0/d; +L_0x1803ce0/d .functor NOR 1, L_0x1802fd0, L_0x18088b0, C4<0>, C4<0>; +L_0x1803ce0 .delay 1 (10000,10000,10000) L_0x1803ce0/d; +L_0x1803e40/d .functor XOR 1, v0x17dbbc0_0, L_0x1803ce0, C4<0>, C4<0>; +L_0x1803e40 .delay 1 (20000,20000,20000) L_0x1803e40/d; +v0x15640c0_0 .net "ALUout", 0 0, L_0x1808340; 1 drivers +v0x1564160_0 .net "Cin", 0 0, L_0x18085b0; 1 drivers +v0x173d670_0 .net "Cout", 0 0, L_0x1803760; 1 drivers +v0x173d710_0 .net *"_s11", 0 0, L_0x1803e40; 1 drivers +o0x7fc2cd916958 .functor BUFZ 1, C4; HiZ drive +; Elide local net with no drivers, v0x155d730_0 name=_s15 +o0x7fc2cd916988 .functor BUFZ 3, C4; HiZ drive +; Elide local net with no drivers, v0x155d7d0_0 name=_s17 +v0x15576a0_0 .net *"_s3", 0 0, L_0x1803910; 1 drivers +v0x1557780_0 .net *"_s7", 0 0, L_0x1803bd0; 1 drivers +v0x154db20_0 .net "addr", 2 0, v0x17dbc90_0; alias, 1 drivers +v0x154d770_0 .net "bit1", 0 0, L_0x1802fd0; 1 drivers +v0x154d810_0 .net "bit2", 0 0, L_0x18088b0; 1 drivers +v0x1543c40_0 .net "invertB", 0 0, v0x17dbbc0_0; alias, 1 drivers +v0x1543ce0_0 .net "nanded", 0 0, L_0x1803a70; 1 drivers +v0x15421d0_0 .net "nored", 0 0, L_0x1803ce0; 1 drivers +v0x1542270_0 .net "out", 7 0, L_0x18925c0; 1 drivers +LS_0x18925c0_0_0 .concat [ 1 1 1 1], L_0x18032f0, L_0x1803910, o0x7fc2cd916958, L_0x1803bd0; +LS_0x18925c0_0_4 .concat [ 1 3 0 0], L_0x1803e40, o0x7fc2cd916988; +L_0x18925c0 .concat [ 4 4 0 0], LS_0x18925c0_0_0, LS_0x18925c0_0_4; +S_0x15c3c60 .scope module, "opmux" "structuralMultiplexer" 3 43, 4 21 0, S_0x15d1f90; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 3 "address" + .port_info 2 /INPUT 8 "in" +v0x15622b0_0 .net "address", 2 0, v0x17dbc90_0; alias, 1 drivers +v0x1562370_0 .net "in", 7 0, L_0x18925c0; alias, 1 drivers +v0x163ad60_0 .net "mux", 3 0, L_0x1806450; 1 drivers +v0x156b2d0_0 .net "muxmid", 1 0, L_0x1807970; 1 drivers +v0x156b390_0 .net "out", 0 0, L_0x1808340; alias, 1 drivers +L_0x1804740 .part v0x17dbc90_0, 0, 1; +L_0x18048a0 .part L_0x18925c0, 0, 2; +L_0x18050e0 .part v0x17dbc90_0, 0, 1; +L_0x1805240 .part L_0x18925c0, 2, 2; +L_0x1805a60 .part v0x17dbc90_0, 0, 1; +L_0x1805bc0 .part L_0x18925c0, 4, 2; +L_0x1806450 .concat8 [ 1 1 1 1], L_0x18045e0, L_0x1804f80, L_0x1805900, L_0x18062f0; +L_0x18066a0 .part v0x17dbc90_0, 0, 1; +L_0x1806790 .part L_0x18925c0, 6, 2; +L_0x1806fd0 .part v0x17dbc90_0, 1, 1; +L_0x1807130 .part L_0x1806450, 0, 2; +L_0x1807970 .concat8 [ 1 1 0 0], L_0x1806e70, L_0x1807810; +L_0x1807b70 .part v0x17dbc90_0, 1, 1; +L_0x1807c10 .part L_0x1806450, 2, 2; +L_0x1808450 .part v0x17dbc90_0, 2, 1; +S_0x15c2220 .scope module, "mux_0" "bitMultiplexer" 4 29, 4 8 0, S_0x15c3c60; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "addr" + .port_info 2 /INPUT 2 "in" +L_0x1803f50/d .functor NOT 1, L_0x1804740, C4<0>, C4<0>, C4<0>; +L_0x1803f50 .delay 1 (10000,10000,10000) L_0x1803f50/d; +L_0x18040b0/d .functor AND 1, L_0x18041c0, L_0x1803f50, C4<1>, C4<1>; +L_0x18040b0 .delay 1 (20000,20000,20000) L_0x18040b0/d; +L_0x1804320/d .functor AND 1, L_0x1804430, L_0x1804740, C4<1>, C4<1>; +L_0x1804320 .delay 1 (20000,20000,20000) L_0x1804320/d; +L_0x18045e0/d .functor OR 1, L_0x18040b0, L_0x1804320, C4<0>, C4<0>; +L_0x18045e0 .delay 1 (20000,20000,20000) L_0x18045e0/d; +v0x15d7670_0 .net *"_s1", 0 0, L_0x18041c0; 1 drivers +v0x15cb210_0 .net *"_s3", 0 0, L_0x1804430; 1 drivers +v0x15cb2f0_0 .net "addr", 0 0, L_0x1804740; 1 drivers +v0x15caef0_0 .net "in", 1 0, L_0x18048a0; 1 drivers +v0x15cafd0_0 .net "naddr", 0 0, L_0x1803f50; 1 drivers +v0x15c1ed0_0 .net "o0", 0 0, L_0x18040b0; 1 drivers +v0x15c1f90_0 .net "o1", 0 0, L_0x1804320; 1 drivers +v0x15c9290_0 .net "out", 0 0, L_0x18045e0; 1 drivers +L_0x18041c0 .part L_0x18048a0, 0, 1; +L_0x1804430 .part L_0x18048a0, 1, 1; +S_0x15c77f0 .scope module, "mux_1" "bitMultiplexer" 4 30, 4 8 0, S_0x15c3c60; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "addr" + .port_info 2 /INPUT 2 "in" +L_0x1804940/d .functor NOT 1, L_0x18050e0, C4<0>, C4<0>, C4<0>; +L_0x1804940 .delay 1 (10000,10000,10000) L_0x1804940/d; +L_0x1804a00/d .functor AND 1, L_0x1804b60, L_0x1804940, C4<1>, C4<1>; +L_0x1804a00 .delay 1 (20000,20000,20000) L_0x1804a00/d; +L_0x1804cc0/d .functor AND 1, L_0x1804dd0, L_0x18050e0, C4<1>, C4<1>; +L_0x1804cc0 .delay 1 (20000,20000,20000) L_0x1804cc0/d; +L_0x1804f80/d .functor OR 1, L_0x1804a00, L_0x1804cc0, C4<0>, C4<0>; +L_0x1804f80 .delay 1 (20000,20000,20000) L_0x1804f80/d; +v0x15c5cf0_0 .net *"_s1", 0 0, L_0x1804b60; 1 drivers +v0x15c5df0_0 .net *"_s3", 0 0, L_0x1804dd0; 1 drivers +v0x15c59e0_0 .net "addr", 0 0, L_0x18050e0; 1 drivers +v0x15c5ad0_0 .net "in", 1 0, L_0x1805240; 1 drivers +v0x15c3f70_0 .net "naddr", 0 0, L_0x1804940; 1 drivers +v0x15c4080_0 .net "o0", 0 0, L_0x1804a00; 1 drivers +v0x15bd6b0_0 .net "o1", 0 0, L_0x1804cc0; 1 drivers +v0x15bd770_0 .net "out", 0 0, L_0x1804f80; 1 drivers +L_0x1804b60 .part L_0x1805240, 0, 1; +L_0x1804dd0 .part L_0x1805240, 1, 1; +S_0x15b1ff0 .scope module, "mux_2" "bitMultiplexer" 4 31, 4 8 0, S_0x15c3c60; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "addr" + .port_info 2 /INPUT 2 "in" +L_0x1805180/d .functor NOT 1, L_0x1805a60, C4<0>, C4<0>, C4<0>; +L_0x1805180 .delay 1 (10000,10000,10000) L_0x1805180/d; +L_0x1805330/d .functor AND 1, L_0x18054e0, L_0x1805180, C4<1>, C4<1>; +L_0x1805330 .delay 1 (20000,20000,20000) L_0x1805330/d; +L_0x1805640/d .functor AND 1, L_0x1805750, L_0x1805a60, C4<1>, C4<1>; +L_0x1805640 .delay 1 (20000,20000,20000) L_0x1805640/d; +L_0x1805900/d .functor OR 1, L_0x1805330, L_0x1805640, C4<0>, C4<0>; +L_0x1805900 .delay 1 (20000,20000,20000) L_0x1805900/d; +v0x15b76c0_0 .net *"_s1", 0 0, L_0x18054e0; 1 drivers +v0x15a3cc0_0 .net *"_s3", 0 0, L_0x1805750; 1 drivers +v0x15a3da0_0 .net "addr", 0 0, L_0x1805a60; 1 drivers +v0x15a2250_0 .net "in", 1 0, L_0x1805bc0; 1 drivers +v0x15a2330_0 .net "naddr", 0 0, L_0x1805180; 1 drivers +v0x15ab270_0 .net "o0", 0 0, L_0x1805330; 1 drivers +v0x15ab330_0 .net "o1", 0 0, L_0x1805640; 1 drivers +v0x15aaf50_0 .net "out", 0 0, L_0x1805900; 1 drivers +L_0x18054e0 .part L_0x1805bc0, 0, 1; +L_0x1805750 .part L_0x1805bc0, 1, 1; +S_0x15a1f10 .scope module, "mux_3" "bitMultiplexer" 4 32, 4 8 0, S_0x15c3c60; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "addr" + .port_info 2 /INPUT 2 "in" +L_0x1805b00/d .functor NOT 1, L_0x18066a0, C4<0>, C4<0>, C4<0>; +L_0x1805b00 .delay 1 (10000,10000,10000) L_0x1805b00/d; +L_0x1805cf0/d .functor AND 1, L_0x1805ea0, L_0x1805b00, C4<1>, C4<1>; +L_0x1805cf0 .delay 1 (20000,20000,20000) L_0x1805cf0/d; +L_0x1806000/d .functor AND 1, L_0x1806140, L_0x18066a0, C4<1>, C4<1>; +L_0x1806000 .delay 1 (20000,20000,20000) L_0x1806000/d; +L_0x18062f0/d .functor OR 1, L_0x1805cf0, L_0x1806000, C4<0>, C4<0>; +L_0x18062f0 .delay 1 (20000,20000,20000) L_0x18062f0/d; +v0x15a92f0_0 .net *"_s1", 0 0, L_0x1805ea0; 1 drivers +v0x15a93f0_0 .net *"_s3", 0 0, L_0x1806140; 1 drivers +v0x15a7850_0 .net "addr", 0 0, L_0x18066a0; 1 drivers +v0x15a7910_0 .net "in", 1 0, L_0x1806790; 1 drivers +v0x15a5d50_0 .net "naddr", 0 0, L_0x1805b00; 1 drivers +v0x15a5e60_0 .net "o0", 0 0, L_0x1805cf0; 1 drivers +v0x15a5a40_0 .net "o1", 0 0, L_0x1806000; 1 drivers +v0x15a5b00_0 .net "out", 0 0, L_0x18062f0; 1 drivers +L_0x1805ea0 .part L_0x1806790, 0, 1; +L_0x1806140 .part L_0x1806790, 1, 1; +S_0x15a3fd0 .scope module, "mux_mid_0" "bitMultiplexer" 4 33, 4 8 0, S_0x15c3c60; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "addr" + .port_info 2 /INPUT 2 "in" +L_0x1806830/d .functor NOT 1, L_0x1806fd0, C4<0>, C4<0>, C4<0>; +L_0x1806830 .delay 1 (10000,10000,10000) L_0x1806830/d; +L_0x18068f0/d .functor AND 1, L_0x1806a50, L_0x1806830, C4<1>, C4<1>; +L_0x18068f0 .delay 1 (20000,20000,20000) L_0x18068f0/d; +L_0x1806bb0/d .functor AND 1, L_0x1806cc0, L_0x1806fd0, C4<1>, C4<1>; +L_0x1806bb0 .delay 1 (20000,20000,20000) L_0x1806bb0/d; +L_0x1806e70/d .functor OR 1, L_0x18068f0, L_0x1806bb0, C4<0>, C4<0>; +L_0x1806e70 .delay 1 (20000,20000,20000) L_0x1806e70/d; +v0x159d760_0 .net *"_s1", 0 0, L_0x1806a50; 1 drivers +v0x1597630_0 .net *"_s3", 0 0, L_0x1806cc0; 1 drivers +v0x1597710_0 .net "addr", 0 0, L_0x1806fd0; 1 drivers +v0x1583ce0_0 .net "in", 1 0, L_0x1807130; 1 drivers +v0x1583dc0_0 .net "naddr", 0 0, L_0x1806830; 1 drivers +v0x1582270_0 .net "o0", 0 0, L_0x18068f0; 1 drivers +v0x1582330_0 .net "o1", 0 0, L_0x1806bb0; 1 drivers +v0x158b290_0 .net "out", 0 0, L_0x1806e70; 1 drivers +L_0x1806a50 .part L_0x1807130, 0, 1; +L_0x1806cc0 .part L_0x1807130, 1, 1; +S_0x158af70 .scope module, "mux_mid_1" "bitMultiplexer" 4 34, 4 8 0, S_0x15c3c60; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "addr" + .port_info 2 /INPUT 2 "in" +L_0x18071d0/d .functor NOT 1, L_0x1807b70, C4<0>, C4<0>, C4<0>; +L_0x18071d0 .delay 1 (10000,10000,10000) L_0x18071d0/d; +L_0x1807290/d .functor AND 1, L_0x18073f0, L_0x18071d0, C4<1>, C4<1>; +L_0x1807290 .delay 1 (20000,20000,20000) L_0x1807290/d; +L_0x1807550/d .functor AND 1, L_0x1807660, L_0x1807b70, C4<1>, C4<1>; +L_0x1807550 .delay 1 (20000,20000,20000) L_0x1807550/d; +L_0x1807810/d .functor OR 1, L_0x1807290, L_0x1807550, C4<0>, C4<0>; +L_0x1807810 .delay 1 (20000,20000,20000) L_0x1807810/d; +v0x1581f30_0 .net *"_s1", 0 0, L_0x18073f0; 1 drivers +v0x1582030_0 .net *"_s3", 0 0, L_0x1807660; 1 drivers +v0x1589310_0 .net "addr", 0 0, L_0x1807b70; 1 drivers +v0x15893d0_0 .net "in", 1 0, L_0x1807c10; 1 drivers +v0x1587870_0 .net "naddr", 0 0, L_0x18071d0; 1 drivers +v0x1587980_0 .net "o0", 0 0, L_0x1807290; 1 drivers +v0x1585d70_0 .net "o1", 0 0, L_0x1807550; 1 drivers +v0x1585e30_0 .net "out", 0 0, L_0x1807810; 1 drivers +L_0x18073f0 .part L_0x1807c10, 0, 1; +L_0x1807660 .part L_0x1807c10, 1, 1; +S_0x1585a60 .scope module, "mux_out" "bitMultiplexer" 4 35, 4 8 0, S_0x15c3c60; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "addr" + .port_info 2 /INPUT 2 "in" +L_0x1807070/d .functor NOT 1, L_0x1808450, C4<0>, C4<0>, C4<0>; +L_0x1807070 .delay 1 (10000,10000,10000) L_0x1807070/d; +L_0x1807d80/d .functor AND 1, L_0x1807ee0, L_0x1807070, C4<1>, C4<1>; +L_0x1807d80 .delay 1 (20000,20000,20000) L_0x1807d80/d; +L_0x1808040/d .functor AND 1, L_0x1808150, L_0x1808450, C4<1>, C4<1>; +L_0x1808040 .delay 1 (20000,20000,20000) L_0x1808040/d; +L_0x1808340/d .functor OR 1, L_0x1807d80, L_0x1808040, C4<0>, C4<0>; +L_0x1808340 .delay 1 (20000,20000,20000) L_0x1808340/d; +v0x1584040_0 .net *"_s1", 0 0, L_0x1807ee0; 1 drivers +v0x1584120_0 .net *"_s3", 0 0, L_0x1808150; 1 drivers +v0x157d700_0 .net "addr", 0 0, L_0x1808450; 1 drivers +v0x157d7a0_0 .net "in", 1 0, L_0x1807970; alias, 1 drivers +v0x1577670_0 .net "naddr", 0 0, L_0x1807070; 1 drivers +v0x1577730_0 .net "o0", 0 0, L_0x1807d80; 1 drivers +v0x1563d20_0 .net "o1", 0 0, L_0x1808040; 1 drivers +v0x1563de0_0 .net "out", 0 0, L_0x1808340; alias, 1 drivers +L_0x1807ee0 .part L_0x1807970, 0, 1; +L_0x1808150 .part L_0x1807970, 1, 1; +S_0x156afb0 .scope module, "structadder" "structAddSub" 3 22, 5 8 0, S_0x15d1f90; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "sub" + .port_info 5 /INPUT 1 "carryin" +L_0x1802c30/d .functor XOR 1, L_0x18088b0, v0x17dbbc0_0, C4<0>, C4<0>; +L_0x1802c30 .delay 1 (20000,20000,20000) L_0x1802c30/d; +L_0x17e7a90/d .functor XOR 1, L_0x1802fd0, L_0x18088b0, C4<0>, C4<0>; +L_0x17e7a90 .delay 1 (20000,20000,20000) L_0x17e7a90/d; +L_0x18032f0/d .functor XOR 1, L_0x17e7a90, L_0x18085b0, C4<0>, C4<0>; +L_0x18032f0 .delay 1 (20000,20000,20000) L_0x18032f0/d; +L_0x18034a0/d .functor AND 1, L_0x1802fd0, L_0x18088b0, C4<1>, C4<1>; +L_0x18034a0 .delay 1 (20000,20000,20000) L_0x18034a0/d; +L_0x1803600/d .functor AND 1, L_0x17e7a90, L_0x18085b0, C4<1>, C4<1>; +L_0x1803600 .delay 1 (20000,20000,20000) L_0x1803600/d; +L_0x1803760/d .functor OR 1, L_0x1803600, L_0x18034a0, C4<0>, C4<0>; +L_0x1803760 .delay 1 (20000,20000,20000) L_0x1803760/d; +v0x1562010_0 .net "AandB", 0 0, L_0x18034a0; 1 drivers +v0x1569350_0 .net "AxorB", 0 0, L_0x17e7a90; 1 drivers +v0x1569410_0 .net "AxorBandCarryIn", 0 0, L_0x1803600; 1 drivers +v0x15678b0_0 .net "a", 0 0, L_0x1802fd0; alias, 1 drivers +v0x1567970_0 .net "b", 0 0, L_0x18088b0; alias, 1 drivers +v0x1565db0_0 .net "bnew", 0 0, L_0x1802c30; 1 drivers +v0x1565e70_0 .net "carryin", 0 0, L_0x18085b0; alias, 1 drivers +v0x1565aa0_0 .net "carryout", 0 0, L_0x1803760; alias, 1 drivers +v0x1565b60_0 .net "sub", 0 0, v0x17dbbc0_0; alias, 1 drivers +v0x1615980_0 .net "sum", 0 0, L_0x18032f0; 1 drivers +S_0x154b1f0 .scope generate, "ripple[9]" "ripple[9]" 3 66, 3 66 0, S_0x16fa6c0; + .timescale -9 -12; +P_0x154d8e0 .param/l "i" 0 3 66, +C4<01001>; +S_0x154aed0 .scope module, "bit" "BitSliceALU" 3 68, 3 11 0, S_0x154b1f0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "ALUout" + .port_info 1 /OUTPUT 1 "Cout" + .port_info 2 /INPUT 1 "invertB" + .port_info 3 /INPUT 1 "Cin" + .port_info 4 /INPUT 3 "addr" + .port_info 5 /INPUT 1 "bit1" + .port_info 6 /INPUT 1 "bit2" +L_0x1809150/d .functor XOR 1, L_0x180e800, L_0x1808a60, C4<0>, C4<0>; +L_0x1809150 .delay 1 (20000,20000,20000) L_0x1809150/d; +L_0x18092b0/d .functor NAND 1, L_0x180e800, L_0x1808a60, C4<1>, C4<1>; +L_0x18092b0 .delay 1 (10000,10000,10000) L_0x18092b0/d; +L_0x1809410/d .functor XOR 1, v0x17dbbc0_0, L_0x18092b0, C4<0>, C4<0>; +L_0x1809410 .delay 1 (20000,20000,20000) L_0x1809410/d; +L_0x1809520/d .functor NOR 1, L_0x180e800, L_0x1808a60, C4<0>, C4<0>; +L_0x1809520 .delay 1 (10000,10000,10000) L_0x1809520/d; +L_0x1809680/d .functor XOR 1, v0x17dbbc0_0, L_0x1809520, C4<0>, C4<0>; +L_0x1809680 .delay 1 (20000,20000,20000) L_0x1809680/d; +v0x174b4e0_0 .net "ALUout", 0 0, L_0x17db7b0; 1 drivers +v0x174b5a0_0 .net "Cin", 0 0, L_0x180e6d0; 1 drivers +v0x174b660_0 .net "Cout", 0 0, L_0x1808fa0; 1 drivers +v0x174b730_0 .net *"_s11", 0 0, L_0x1809680; 1 drivers +o0x7fc2cd917e28 .functor BUFZ 1, C4; HiZ drive +; Elide local net with no drivers, v0x174b7d0_0 name=_s15 +o0x7fc2cd917e58 .functor BUFZ 3, C4; HiZ drive +; Elide local net with no drivers, v0x174b8c0_0 name=_s17 +v0x174b9a0_0 .net *"_s3", 0 0, L_0x1809150; 1 drivers +v0x174ba80_0 .net *"_s7", 0 0, L_0x1809410; 1 drivers +v0x174bb60_0 .net "addr", 2 0, v0x17dbc90_0; alias, 1 drivers +v0x174bcb0_0 .net "bit1", 0 0, L_0x180e800; 1 drivers +v0x174bd50_0 .net "bit2", 0 0, L_0x1808a60; 1 drivers +v0x174be20_0 .net "invertB", 0 0, v0x17dbbc0_0; alias, 1 drivers +v0x174bec0_0 .net "nanded", 0 0, L_0x18092b0; 1 drivers +v0x174bf60_0 .net "nored", 0 0, L_0x1809520; 1 drivers +v0x174c000_0 .net "out", 7 0, L_0x18926b0; 1 drivers +LS_0x18926b0_0_0 .concat [ 1 1 1 1], L_0x1808b30, L_0x1809150, o0x7fc2cd917e28, L_0x1809410; +LS_0x18926b0_0_4 .concat [ 1 3 0 0], L_0x1809680, o0x7fc2cd917e58; +L_0x18926b0 .concat [ 4 4 0 0], LS_0x18926b0_0_0, LS_0x18926b0_0_4; +S_0x1549270 .scope module, "opmux" "structuralMultiplexer" 3 43, 4 21 0, S_0x154aed0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 3 "address" + .port_info 2 /INPUT 8 "in" +v0x174a4b0_0 .net "address", 2 0, v0x17dbc90_0; alias, 1 drivers +v0x174a570_0 .net "in", 7 0, L_0x18926b0; alias, 1 drivers +v0x174a650_0 .net "mux", 3 0, L_0x180bd50; 1 drivers +v0x174a710_0 .net "muxmid", 1 0, L_0x180d2c0; 1 drivers +v0x174a7d0_0 .net "out", 0 0, L_0x17db7b0; alias, 1 drivers +L_0x1809f80 .part v0x17dbc90_0, 0, 1; +L_0x180a0e0 .part L_0x18926b0, 0, 2; +L_0x180a970 .part v0x17dbc90_0, 0, 1; +L_0x180aad0 .part L_0x18926b0, 2, 2; +L_0x180b340 .part v0x17dbc90_0, 0, 1; +L_0x180b4a0 .part L_0x18926b0, 4, 2; +L_0x180bd50 .concat8 [ 1 1 1 1], L_0x1809e20, L_0x180a810, L_0x180b1e0, L_0x180bbf0; +L_0x180bfa0 .part v0x17dbc90_0, 0, 1; +L_0x180c090 .part L_0x18926b0, 6, 2; +L_0x180c8d0 .part v0x17dbc90_0, 1, 1; +L_0x180ca30 .part L_0x180bd50, 0, 2; +L_0x180d2c0 .concat8 [ 1 1 0 0], L_0x180c770, L_0x180d160; +L_0x180d4c0 .part v0x17dbc90_0, 1, 1; +L_0x17db0f0 .part L_0x180bd50, 2, 2; +L_0x180e570 .part v0x17dbc90_0, 2, 1; +S_0x15477d0 .scope module, "mux_0" "bitMultiplexer" 4 29, 4 8 0, S_0x1549270; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "addr" + .port_info 2 /INPUT 2 "in" +L_0x1809790/d .functor NOT 1, L_0x1809f80, C4<0>, C4<0>, C4<0>; +L_0x1809790 .delay 1 (10000,10000,10000) L_0x1809790/d; +L_0x18098f0/d .functor AND 1, L_0x1809a00, L_0x1809790, C4<1>, C4<1>; +L_0x18098f0 .delay 1 (20000,20000,20000) L_0x18098f0/d; +L_0x1809b60/d .functor AND 1, L_0x1809c70, L_0x1809f80, C4<1>, C4<1>; +L_0x1809b60 .delay 1 (20000,20000,20000) L_0x1809b60/d; +L_0x1809e20/d .functor OR 1, L_0x18098f0, L_0x1809b60, C4<0>, C4<0>; +L_0x1809e20 .delay 1 (20000,20000,20000) L_0x1809e20/d; +v0x1541f40_0 .net *"_s1", 0 0, L_0x1809a00; 1 drivers +v0x1545cd0_0 .net *"_s3", 0 0, L_0x1809c70; 1 drivers +v0x1545d90_0 .net "addr", 0 0, L_0x1809f80; 1 drivers +v0x15459c0_0 .net "in", 1 0, L_0x180a0e0; 1 drivers +v0x1545aa0_0 .net "naddr", 0 0, L_0x1809790; 1 drivers +v0x1543f50_0 .net "o0", 0 0, L_0x18098f0; 1 drivers +v0x1543ff0_0 .net "o1", 0 0, L_0x1809b60; 1 drivers +v0x1731e90_0 .net "out", 0 0, L_0x1809e20; 1 drivers +L_0x1809a00 .part L_0x180a0e0, 0, 1; +L_0x1809c70 .part L_0x180a0e0, 1, 1; +S_0x1731b50 .scope module, "mux_1" "bitMultiplexer" 4 30, 4 8 0, S_0x1549270; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "addr" + .port_info 2 /INPUT 2 "in" +L_0x180a180/d .functor NOT 1, L_0x180a970, C4<0>, C4<0>, C4<0>; +L_0x180a180 .delay 1 (10000,10000,10000) L_0x180a180/d; +L_0x180a240/d .functor AND 1, L_0x180a3f0, L_0x180a180, C4<1>, C4<1>; +L_0x180a240 .delay 1 (20000,20000,20000) L_0x180a240/d; +L_0x180a550/d .functor AND 1, L_0x180a660, L_0x180a970, C4<1>, C4<1>; +L_0x180a550 .delay 1 (20000,20000,20000) L_0x180a550/d; +L_0x180a810/d .functor OR 1, L_0x180a240, L_0x180a550, C4<0>, C4<0>; +L_0x180a810 .delay 1 (20000,20000,20000) L_0x180a810/d; +v0x1737180_0 .net *"_s1", 0 0, L_0x180a3f0; 1 drivers +v0x1737280_0 .net *"_s3", 0 0, L_0x180a660; 1 drivers +v0x1747490_0 .net "addr", 0 0, L_0x180a970; 1 drivers +v0x1747530_0 .net "in", 1 0, L_0x180aad0; 1 drivers +v0x17475d0_0 .net "naddr", 0 0, L_0x180a180; 1 drivers +v0x17476c0_0 .net "o0", 0 0, L_0x180a240; 1 drivers +v0x1747760_0 .net "o1", 0 0, L_0x180a550; 1 drivers +v0x1747800_0 .net "out", 0 0, L_0x180a810; 1 drivers +L_0x180a3f0 .part L_0x180aad0, 0, 1; +L_0x180a660 .part L_0x180aad0, 1, 1; +S_0x17478a0 .scope module, "mux_2" "bitMultiplexer" 4 31, 4 8 0, S_0x1549270; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "addr" + .port_info 2 /INPUT 2 "in" +L_0x180aa10/d .functor NOT 1, L_0x180b340, C4<0>, C4<0>, C4<0>; +L_0x180aa10 .delay 1 (10000,10000,10000) L_0x180aa10/d; +L_0x180abc0/d .functor AND 1, L_0x180adc0, L_0x180aa10, C4<1>, C4<1>; +L_0x180abc0 .delay 1 (20000,20000,20000) L_0x180abc0/d; +L_0x180af20/d .functor AND 1, L_0x180b030, L_0x180b340, C4<1>, C4<1>; +L_0x180af20 .delay 1 (20000,20000,20000) L_0x180af20/d; +L_0x180b1e0/d .functor OR 1, L_0x180abc0, L_0x180af20, C4<0>, C4<0>; +L_0x180b1e0 .delay 1 (20000,20000,20000) L_0x180b1e0/d; +v0x1747ad0_0 .net *"_s1", 0 0, L_0x180adc0; 1 drivers +v0x1747b70_0 .net *"_s3", 0 0, L_0x180b030; 1 drivers +v0x1747c10_0 .net "addr", 0 0, L_0x180b340; 1 drivers +v0x1747cb0_0 .net "in", 1 0, L_0x180b4a0; 1 drivers +v0x1747d50_0 .net "naddr", 0 0, L_0x180aa10; 1 drivers +v0x1747e40_0 .net "o0", 0 0, L_0x180abc0; 1 drivers +v0x1747ee0_0 .net "o1", 0 0, L_0x180af20; 1 drivers +v0x1747f80_0 .net "out", 0 0, L_0x180b1e0; 1 drivers +L_0x180adc0 .part L_0x180b4a0, 0, 1; +L_0x180b030 .part L_0x180b4a0, 1, 1; +S_0x1748020 .scope module, "mux_3" "bitMultiplexer" 4 32, 4 8 0, S_0x1549270; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "addr" + .port_info 2 /INPUT 2 "in" +L_0x180b3e0/d .functor NOT 1, L_0x180bfa0, C4<0>, C4<0>, C4<0>; +L_0x180b3e0 .delay 1 (10000,10000,10000) L_0x180b3e0/d; +L_0x180b5d0/d .functor AND 1, L_0x180b7d0, L_0x180b3e0, C4<1>, C4<1>; +L_0x180b5d0 .delay 1 (20000,20000,20000) L_0x180b5d0/d; +L_0x180b930/d .functor AND 1, L_0x180ba40, L_0x180bfa0, C4<1>, C4<1>; +L_0x180b930 .delay 1 (20000,20000,20000) L_0x180b930/d; +L_0x180bbf0/d .functor OR 1, L_0x180b5d0, L_0x180b930, C4<0>, C4<0>; +L_0x180bbf0 .delay 1 (20000,20000,20000) L_0x180bbf0/d; +v0x1748250_0 .net *"_s1", 0 0, L_0x180b7d0; 1 drivers +v0x17482f0_0 .net *"_s3", 0 0, L_0x180ba40; 1 drivers +v0x1748390_0 .net "addr", 0 0, L_0x180bfa0; 1 drivers +v0x1748430_0 .net "in", 1 0, L_0x180c090; 1 drivers +v0x17484d0_0 .net "naddr", 0 0, L_0x180b3e0; 1 drivers +v0x17485c0_0 .net "o0", 0 0, L_0x180b5d0; 1 drivers +v0x1748660_0 .net "o1", 0 0, L_0x180b930; 1 drivers +v0x1748700_0 .net "out", 0 0, L_0x180bbf0; 1 drivers +L_0x180b7d0 .part L_0x180c090, 0, 1; +L_0x180ba40 .part L_0x180c090, 1, 1; +S_0x1748840 .scope module, "mux_mid_0" "bitMultiplexer" 4 33, 4 8 0, S_0x1549270; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "addr" + .port_info 2 /INPUT 2 "in" +L_0x180c130/d .functor NOT 1, L_0x180c8d0, C4<0>, C4<0>, C4<0>; +L_0x180c130 .delay 1 (10000,10000,10000) L_0x180c130/d; +L_0x180c1f0/d .functor AND 1, L_0x180c350, L_0x180c130, C4<1>, C4<1>; +L_0x180c1f0 .delay 1 (20000,20000,20000) L_0x180c1f0/d; +L_0x180c4b0/d .functor AND 1, L_0x180c5c0, L_0x180c8d0, C4<1>, C4<1>; +L_0x180c4b0 .delay 1 (20000,20000,20000) L_0x180c4b0/d; +L_0x180c770/d .functor OR 1, L_0x180c1f0, L_0x180c4b0, C4<0>, C4<0>; +L_0x180c770 .delay 1 (20000,20000,20000) L_0x180c770/d; +v0x1748ac0_0 .net *"_s1", 0 0, L_0x180c350; 1 drivers +v0x1748bc0_0 .net *"_s3", 0 0, L_0x180c5c0; 1 drivers +v0x1748ca0_0 .net "addr", 0 0, L_0x180c8d0; 1 drivers +v0x1748d40_0 .net "in", 1 0, L_0x180ca30; 1 drivers +v0x1748e20_0 .net "naddr", 0 0, L_0x180c130; 1 drivers +v0x1748f30_0 .net "o0", 0 0, L_0x180c1f0; 1 drivers +v0x1748ff0_0 .net "o1", 0 0, L_0x180c4b0; 1 drivers +v0x17490b0_0 .net "out", 0 0, L_0x180c770; 1 drivers +L_0x180c350 .part L_0x180ca30, 0, 1; +L_0x180c5c0 .part L_0x180ca30, 1, 1; +S_0x17491f0 .scope module, "mux_mid_1" "bitMultiplexer" 4 34, 4 8 0, S_0x1549270; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "addr" + .port_info 2 /INPUT 2 "in" +L_0x180cad0/d .functor NOT 1, L_0x180d4c0, C4<0>, C4<0>, C4<0>; +L_0x180cad0 .delay 1 (10000,10000,10000) L_0x180cad0/d; +L_0x180cb90/d .functor AND 1, L_0x180cd40, L_0x180cad0, C4<1>, C4<1>; +L_0x180cb90 .delay 1 (20000,20000,20000) L_0x180cb90/d; +L_0x180cea0/d .functor AND 1, L_0x180cfb0, L_0x180d4c0, C4<1>, C4<1>; +L_0x180cea0 .delay 1 (20000,20000,20000) L_0x180cea0/d; +L_0x180d160/d .functor OR 1, L_0x180cb90, L_0x180cea0, C4<0>, C4<0>; +L_0x180d160 .delay 1 (20000,20000,20000) L_0x180d160/d; +v0x1749420_0 .net *"_s1", 0 0, L_0x180cd40; 1 drivers +v0x1749520_0 .net *"_s3", 0 0, L_0x180cfb0; 1 drivers +v0x1749600_0 .net "addr", 0 0, L_0x180d4c0; 1 drivers +v0x17496a0_0 .net "in", 1 0, L_0x17db0f0; 1 drivers +v0x1749780_0 .net "naddr", 0 0, L_0x180cad0; 1 drivers +v0x1749890_0 .net "o0", 0 0, L_0x180cb90; 1 drivers +v0x1749950_0 .net "o1", 0 0, L_0x180cea0; 1 drivers +v0x1749a10_0 .net "out", 0 0, L_0x180d160; 1 drivers +L_0x180cd40 .part L_0x17db0f0, 0, 1; +L_0x180cfb0 .part L_0x17db0f0, 1, 1; +S_0x1749b50 .scope module, "mux_out" "bitMultiplexer" 4 35, 4 8 0, S_0x1549270; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "addr" + .port_info 2 /INPUT 2 "in" +L_0x180c970/d .functor NOT 1, L_0x180e570, C4<0>, C4<0>, C4<0>; +L_0x180c970 .delay 1 (10000,10000,10000) L_0x180c970/d; +L_0x180ac60/d .functor AND 1, L_0x17db3c0, L_0x180c970, C4<1>, C4<1>; +L_0x180ac60 .delay 1 (20000,20000,20000) L_0x180ac60/d; +L_0x17db460/d .functor AND 1, L_0x17db5c0, L_0x180e570, C4<1>, C4<1>; +L_0x17db460 .delay 1 (20000,20000,20000) L_0x17db460/d; +L_0x17db7b0/d .functor OR 1, L_0x180ac60, L_0x17db460, C4<0>, C4<0>; +L_0x17db7b0 .delay 1 (20000,20000,20000) L_0x17db7b0/d; +v0x1749d80_0 .net *"_s1", 0 0, L_0x17db3c0; 1 drivers +v0x1749e80_0 .net *"_s3", 0 0, L_0x17db5c0; 1 drivers +v0x1749f60_0 .net "addr", 0 0, L_0x180e570; 1 drivers +v0x174a000_0 .net "in", 1 0, L_0x180d2c0; alias, 1 drivers +v0x174a0e0_0 .net "naddr", 0 0, L_0x180c970; 1 drivers +v0x174a1f0_0 .net "o0", 0 0, L_0x180ac60; 1 drivers +v0x174a2b0_0 .net "o1", 0 0, L_0x17db460; 1 drivers +v0x174a370_0 .net "out", 0 0, L_0x17db7b0; alias, 1 drivers +L_0x17db3c0 .part L_0x180d2c0, 0, 1; +L_0x17db5c0 .part L_0x180d2c0, 1, 1; +S_0x174a900 .scope module, "structadder" "structAddSub" 3 22, 5 8 0, S_0x154aed0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "sub" + .port_info 5 /INPUT 1 "carryin" +L_0x18084f0/d .functor XOR 1, L_0x1808a60, v0x17dbbc0_0, C4<0>, C4<0>; +L_0x18084f0 .delay 1 (20000,20000,20000) L_0x18084f0/d; +L_0x18087f0/d .functor XOR 1, L_0x180e800, L_0x1808a60, C4<0>, C4<0>; +L_0x18087f0 .delay 1 (20000,20000,20000) L_0x18087f0/d; +L_0x1808b30/d .functor XOR 1, L_0x18087f0, L_0x180e6d0, C4<0>, C4<0>; +L_0x1808b30 .delay 1 (20000,20000,20000) L_0x1808b30/d; +L_0x1808ce0/d .functor AND 1, L_0x180e800, L_0x1808a60, C4<1>, C4<1>; +L_0x1808ce0 .delay 1 (20000,20000,20000) L_0x1808ce0/d; +L_0x1808e40/d .functor AND 1, L_0x18087f0, L_0x180e6d0, C4<1>, C4<1>; +L_0x1808e40 .delay 1 (20000,20000,20000) L_0x1808e40/d; +L_0x1808fa0/d .functor OR 1, L_0x1808e40, L_0x1808ce0, C4<0>, C4<0>; +L_0x1808fa0 .delay 1 (20000,20000,20000) L_0x1808fa0/d; +v0x174abc0_0 .net "AandB", 0 0, L_0x1808ce0; 1 drivers +v0x174ac80_0 .net "AxorB", 0 0, L_0x18087f0; 1 drivers +v0x174ad40_0 .net "AxorBandCarryIn", 0 0, L_0x1808e40; 1 drivers +v0x174ade0_0 .net "a", 0 0, L_0x180e800; alias, 1 drivers +v0x174aea0_0 .net "b", 0 0, L_0x1808a60; alias, 1 drivers +v0x174afb0_0 .net "bnew", 0 0, L_0x18084f0; 1 drivers +v0x174b070_0 .net "carryin", 0 0, L_0x180e6d0; alias, 1 drivers +v0x174b130_0 .net "carryout", 0 0, L_0x1808fa0; alias, 1 drivers +v0x174b1f0_0 .net "sub", 0 0, v0x17dbbc0_0; alias, 1 drivers +v0x174b320_0 .net "sum", 0 0, L_0x1808b30; 1 drivers +S_0x174c1b0 .scope generate, "ripple[10]" "ripple[10]" 3 66, 3 66 0, S_0x16fa6c0; + .timescale -9 -12; +P_0x174c380 .param/l "i" 0 3 66, +C4<01010>; +S_0x174c440 .scope module, "bit" "BitSliceALU" 3 68, 3 11 0, S_0x174c1b0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "ALUout" + .port_info 1 /OUTPUT 1 "Cout" + .port_info 2 /INPUT 1 "invertB" + .port_info 3 /INPUT 1 "Cin" + .port_info 4 /INPUT 3 "addr" + .port_info 5 /INPUT 1 "bit1" + .port_info 6 /INPUT 1 "bit2" +L_0x180f1c0/d .functor XOR 1, L_0x180e8a0, L_0x1814230, C4<0>, C4<0>; +L_0x180f1c0 .delay 1 (20000,20000,20000) L_0x180f1c0/d; +L_0x180f320/d .functor NAND 1, L_0x180e8a0, L_0x1814230, C4<1>, C4<1>; +L_0x180f320 .delay 1 (10000,10000,10000) L_0x180f320/d; +L_0x180f480/d .functor XOR 1, v0x17dbbc0_0, L_0x180f320, C4<0>, C4<0>; +L_0x180f480 .delay 1 (20000,20000,20000) L_0x180f480/d; +L_0x180f590/d .functor NOR 1, L_0x180e8a0, L_0x1814230, C4<0>, C4<0>; +L_0x180f590 .delay 1 (10000,10000,10000) L_0x180f590/d; +L_0x180f6f0/d .functor XOR 1, v0x17dbbc0_0, L_0x180f590, C4<0>, C4<0>; +L_0x180f6f0 .delay 1 (20000,20000,20000) L_0x180f6f0/d; +v0x1751c10_0 .net "ALUout", 0 0, L_0x1813da0; 1 drivers +v0x1751cd0_0 .net "Cin", 0 0, L_0x1814010; 1 drivers +v0x1751d90_0 .net "Cout", 0 0, L_0x180f010; 1 drivers +v0x1751e60_0 .net *"_s11", 0 0, L_0x180f6f0; 1 drivers +o0x7fc2cd9192f8 .functor BUFZ 1, C4; HiZ drive +; Elide local net with no drivers, v0x1751f00_0 name=_s15 +o0x7fc2cd919328 .functor BUFZ 3, C4; HiZ drive +; Elide local net with no drivers, v0x1751ff0_0 name=_s17 +v0x17520d0_0 .net *"_s3", 0 0, L_0x180f1c0; 1 drivers +v0x17521b0_0 .net *"_s7", 0 0, L_0x180f480; 1 drivers +v0x1752290_0 .net "addr", 2 0, v0x17dbc90_0; alias, 1 drivers +v0x17523e0_0 .net "bit1", 0 0, L_0x180e8a0; 1 drivers +v0x1752480_0 .net "bit2", 0 0, L_0x1814230; 1 drivers +v0x1752550_0 .net "invertB", 0 0, v0x17dbbc0_0; alias, 1 drivers +v0x17525f0_0 .net "nanded", 0 0, L_0x180f320; 1 drivers +v0x1752690_0 .net "nored", 0 0, L_0x180f590; 1 drivers +v0x1752730_0 .net "out", 7 0, L_0x1892890; 1 drivers +LS_0x1892890_0_0 .concat [ 1 1 1 1], L_0x180eba0, L_0x180f1c0, o0x7fc2cd9192f8, L_0x180f480; +LS_0x1892890_0_4 .concat [ 1 3 0 0], L_0x180f6f0, o0x7fc2cd919328; +L_0x1892890 .concat [ 4 4 0 0], LS_0x1892890_0_0, LS_0x1892890_0_4; +S_0x174c6d0 .scope module, "opmux" "structuralMultiplexer" 3 43, 4 21 0, S_0x174c440; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 3 "address" + .port_info 2 /INPUT 8 "in" +v0x1750bb0_0 .net "address", 2 0, v0x17dbc90_0; alias, 1 drivers +v0x1750c70_0 .net "in", 7 0, L_0x1892890; alias, 1 drivers +v0x1750d50_0 .net "mux", 3 0, L_0x1811e10; 1 drivers +v0x1750e10_0 .net "muxmid", 1 0, L_0x18133d0; 1 drivers +v0x1750ed0_0 .net "out", 0 0, L_0x1813da0; alias, 1 drivers +L_0x180fff0 .part v0x17dbc90_0, 0, 1; +L_0x1810150 .part L_0x1892890, 0, 2; +L_0x1810a30 .part v0x17dbc90_0, 0, 1; +L_0x1810b90 .part L_0x1892890, 2, 2; +L_0x1811400 .part v0x17dbc90_0, 0, 1; +L_0x1811560 .part L_0x1892890, 4, 2; +L_0x1811e10 .concat8 [ 1 1 1 1], L_0x180fe90, L_0x18108d0, L_0x18112a0, L_0x1811cb0; +L_0x18120b0 .part v0x17dbc90_0, 0, 1; +L_0x18121a0 .part L_0x1892890, 6, 2; +L_0x18129e0 .part v0x17dbc90_0, 1, 1; +L_0x1812b40 .part L_0x1811e10, 0, 2; +L_0x18133d0 .concat8 [ 1 1 0 0], L_0x1812880, L_0x1813270; +L_0x18135d0 .part v0x17dbc90_0, 1, 1; +L_0x1813670 .part L_0x1811e10, 2, 2; +L_0x1813eb0 .part v0x17dbc90_0, 2, 1; +S_0x174c940 .scope module, "mux_0" "bitMultiplexer" 4 29, 4 8 0, S_0x174c6d0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "addr" + .port_info 2 /INPUT 2 "in" +L_0x180f800/d .functor NOT 1, L_0x180fff0, C4<0>, C4<0>, C4<0>; +L_0x180f800 .delay 1 (10000,10000,10000) L_0x180f800/d; +L_0x180f960/d .functor AND 1, L_0x180fa70, L_0x180f800, C4<1>, C4<1>; +L_0x180f960 .delay 1 (20000,20000,20000) L_0x180f960/d; +L_0x180fbd0/d .functor AND 1, L_0x180fce0, L_0x180fff0, C4<1>, C4<1>; +L_0x180fbd0 .delay 1 (20000,20000,20000) L_0x180fbd0/d; +L_0x180fe90/d .functor OR 1, L_0x180f960, L_0x180fbd0, C4<0>, C4<0>; +L_0x180fe90 .delay 1 (20000,20000,20000) L_0x180fe90/d; +v0x174cbb0_0 .net *"_s1", 0 0, L_0x180fa70; 1 drivers +v0x174ccb0_0 .net *"_s3", 0 0, L_0x180fce0; 1 drivers +v0x174cd90_0 .net "addr", 0 0, L_0x180fff0; 1 drivers +v0x174ce60_0 .net "in", 1 0, L_0x1810150; 1 drivers +v0x174cf40_0 .net "naddr", 0 0, L_0x180f800; 1 drivers +v0x174d050_0 .net "o0", 0 0, L_0x180f960; 1 drivers +v0x174d110_0 .net "o1", 0 0, L_0x180fbd0; 1 drivers +v0x174d1d0_0 .net "out", 0 0, L_0x180fe90; 1 drivers +L_0x180fa70 .part L_0x1810150, 0, 1; +L_0x180fce0 .part L_0x1810150, 1, 1; +S_0x174d310 .scope module, "mux_1" "bitMultiplexer" 4 30, 4 8 0, S_0x174c6d0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "addr" + .port_info 2 /INPUT 2 "in" +L_0x18101f0/d .functor NOT 1, L_0x1810a30, C4<0>, C4<0>, C4<0>; +L_0x18101f0 .delay 1 (10000,10000,10000) L_0x18101f0/d; +L_0x18102b0/d .functor AND 1, L_0x18104b0, L_0x18101f0, C4<1>, C4<1>; +L_0x18102b0 .delay 1 (20000,20000,20000) L_0x18102b0/d; +L_0x1810610/d .functor AND 1, L_0x1810720, L_0x1810a30, C4<1>, C4<1>; +L_0x1810610 .delay 1 (20000,20000,20000) L_0x1810610/d; +L_0x18108d0/d .functor OR 1, L_0x18102b0, L_0x1810610, C4<0>, C4<0>; +L_0x18108d0 .delay 1 (20000,20000,20000) L_0x18108d0/d; +v0x174d540_0 .net *"_s1", 0 0, L_0x18104b0; 1 drivers +v0x174d640_0 .net *"_s3", 0 0, L_0x1810720; 1 drivers +v0x174d720_0 .net "addr", 0 0, L_0x1810a30; 1 drivers +v0x174d7c0_0 .net "in", 1 0, L_0x1810b90; 1 drivers +v0x174d8a0_0 .net "naddr", 0 0, L_0x18101f0; 1 drivers +v0x174d9b0_0 .net "o0", 0 0, L_0x18102b0; 1 drivers +v0x174da70_0 .net "o1", 0 0, L_0x1810610; 1 drivers +v0x174db30_0 .net "out", 0 0, L_0x18108d0; 1 drivers +L_0x18104b0 .part L_0x1810b90, 0, 1; +L_0x1810720 .part L_0x1810b90, 1, 1; +S_0x174dc70 .scope module, "mux_2" "bitMultiplexer" 4 31, 4 8 0, S_0x174c6d0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "addr" + .port_info 2 /INPUT 2 "in" +L_0x1810ad0/d .functor NOT 1, L_0x1811400, C4<0>, C4<0>, C4<0>; +L_0x1810ad0 .delay 1 (10000,10000,10000) L_0x1810ad0/d; +L_0x1810c80/d .functor AND 1, L_0x1810e80, L_0x1810ad0, C4<1>, C4<1>; +L_0x1810c80 .delay 1 (20000,20000,20000) L_0x1810c80/d; +L_0x1810fe0/d .functor AND 1, L_0x18110f0, L_0x1811400, C4<1>, C4<1>; +L_0x1810fe0 .delay 1 (20000,20000,20000) L_0x1810fe0/d; +L_0x18112a0/d .functor OR 1, L_0x1810c80, L_0x1810fe0, C4<0>, C4<0>; +L_0x18112a0 .delay 1 (20000,20000,20000) L_0x18112a0/d; +v0x174dea0_0 .net *"_s1", 0 0, L_0x1810e80; 1 drivers +v0x174df80_0 .net *"_s3", 0 0, L_0x18110f0; 1 drivers +v0x174e060_0 .net "addr", 0 0, L_0x1811400; 1 drivers +v0x174e130_0 .net "in", 1 0, L_0x1811560; 1 drivers +v0x174e210_0 .net "naddr", 0 0, L_0x1810ad0; 1 drivers +v0x174e320_0 .net "o0", 0 0, L_0x1810c80; 1 drivers +v0x174e3e0_0 .net "o1", 0 0, L_0x1810fe0; 1 drivers +v0x174e4a0_0 .net "out", 0 0, L_0x18112a0; 1 drivers +L_0x1810e80 .part L_0x1811560, 0, 1; +L_0x18110f0 .part L_0x1811560, 1, 1; +S_0x174e5e0 .scope module, "mux_3" "bitMultiplexer" 4 32, 4 8 0, S_0x174c6d0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "addr" + .port_info 2 /INPUT 2 "in" +L_0x18114a0/d .functor NOT 1, L_0x18120b0, C4<0>, C4<0>, C4<0>; +L_0x18114a0 .delay 1 (10000,10000,10000) L_0x18114a0/d; +L_0x1811690/d .functor AND 1, L_0x1811890, L_0x18114a0, C4<1>, C4<1>; +L_0x1811690 .delay 1 (20000,20000,20000) L_0x1811690/d; +L_0x18119f0/d .functor AND 1, L_0x1811b00, L_0x18120b0, C4<1>, C4<1>; +L_0x18119f0 .delay 1 (20000,20000,20000) L_0x18119f0/d; +L_0x1811cb0/d .functor OR 1, L_0x1811690, L_0x18119f0, C4<0>, C4<0>; +L_0x1811cb0 .delay 1 (20000,20000,20000) L_0x1811cb0/d; +v0x174e810_0 .net *"_s1", 0 0, L_0x1811890; 1 drivers +v0x174e910_0 .net *"_s3", 0 0, L_0x1811b00; 1 drivers +v0x174e9f0_0 .net "addr", 0 0, L_0x18120b0; 1 drivers +v0x174ea90_0 .net "in", 1 0, L_0x18121a0; 1 drivers +v0x174eb70_0 .net "naddr", 0 0, L_0x18114a0; 1 drivers +v0x174ec80_0 .net "o0", 0 0, L_0x1811690; 1 drivers +v0x174ed40_0 .net "o1", 0 0, L_0x18119f0; 1 drivers +v0x174ee00_0 .net "out", 0 0, L_0x1811cb0; 1 drivers +L_0x1811890 .part L_0x18121a0, 0, 1; +L_0x1811b00 .part L_0x18121a0, 1, 1; +S_0x174ef40 .scope module, "mux_mid_0" "bitMultiplexer" 4 33, 4 8 0, S_0x174c6d0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "addr" + .port_info 2 /INPUT 2 "in" +L_0x1812240/d .functor NOT 1, L_0x18129e0, C4<0>, C4<0>, C4<0>; +L_0x1812240 .delay 1 (10000,10000,10000) L_0x1812240/d; +L_0x1812300/d .functor AND 1, L_0x1812460, L_0x1812240, C4<1>, C4<1>; +L_0x1812300 .delay 1 (20000,20000,20000) L_0x1812300/d; +L_0x18125c0/d .functor AND 1, L_0x18126d0, L_0x18129e0, C4<1>, C4<1>; +L_0x18125c0 .delay 1 (20000,20000,20000) L_0x18125c0/d; +L_0x1812880/d .functor OR 1, L_0x1812300, L_0x18125c0, C4<0>, C4<0>; +L_0x1812880 .delay 1 (20000,20000,20000) L_0x1812880/d; +v0x174f1c0_0 .net *"_s1", 0 0, L_0x1812460; 1 drivers +v0x174f2c0_0 .net *"_s3", 0 0, L_0x18126d0; 1 drivers +v0x174f3a0_0 .net "addr", 0 0, L_0x18129e0; 1 drivers +v0x174f440_0 .net "in", 1 0, L_0x1812b40; 1 drivers +v0x174f520_0 .net "naddr", 0 0, L_0x1812240; 1 drivers +v0x174f630_0 .net "o0", 0 0, L_0x1812300; 1 drivers +v0x174f6f0_0 .net "o1", 0 0, L_0x18125c0; 1 drivers +v0x174f7b0_0 .net "out", 0 0, L_0x1812880; 1 drivers +L_0x1812460 .part L_0x1812b40, 0, 1; +L_0x18126d0 .part L_0x1812b40, 1, 1; +S_0x174f8f0 .scope module, "mux_mid_1" "bitMultiplexer" 4 34, 4 8 0, S_0x174c6d0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "addr" + .port_info 2 /INPUT 2 "in" +L_0x1812be0/d .functor NOT 1, L_0x18135d0, C4<0>, C4<0>, C4<0>; +L_0x1812be0 .delay 1 (10000,10000,10000) L_0x1812be0/d; +L_0x1812ca0/d .functor AND 1, L_0x1812e50, L_0x1812be0, C4<1>, C4<1>; +L_0x1812ca0 .delay 1 (20000,20000,20000) L_0x1812ca0/d; +L_0x1812fb0/d .functor AND 1, L_0x18130c0, L_0x18135d0, C4<1>, C4<1>; +L_0x1812fb0 .delay 1 (20000,20000,20000) L_0x1812fb0/d; +L_0x1813270/d .functor OR 1, L_0x1812ca0, L_0x1812fb0, C4<0>, C4<0>; +L_0x1813270 .delay 1 (20000,20000,20000) L_0x1813270/d; +v0x174fb20_0 .net *"_s1", 0 0, L_0x1812e50; 1 drivers +v0x174fc20_0 .net *"_s3", 0 0, L_0x18130c0; 1 drivers +v0x174fd00_0 .net "addr", 0 0, L_0x18135d0; 1 drivers +v0x174fda0_0 .net "in", 1 0, L_0x1813670; 1 drivers +v0x174fe80_0 .net "naddr", 0 0, L_0x1812be0; 1 drivers +v0x174ff90_0 .net "o0", 0 0, L_0x1812ca0; 1 drivers +v0x1750050_0 .net "o1", 0 0, L_0x1812fb0; 1 drivers +v0x1750110_0 .net "out", 0 0, L_0x1813270; 1 drivers +L_0x1812e50 .part L_0x1813670, 0, 1; +L_0x18130c0 .part L_0x1813670, 1, 1; +S_0x1750250 .scope module, "mux_out" "bitMultiplexer" 4 35, 4 8 0, S_0x174c6d0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "addr" + .port_info 2 /INPUT 2 "in" +L_0x1812a80/d .functor NOT 1, L_0x1813eb0, C4<0>, C4<0>, C4<0>; +L_0x1812a80 .delay 1 (10000,10000,10000) L_0x1812a80/d; +L_0x18137e0/d .functor AND 1, L_0x1813940, L_0x1812a80, C4<1>, C4<1>; +L_0x18137e0 .delay 1 (20000,20000,20000) L_0x18137e0/d; +L_0x1813aa0/d .functor AND 1, L_0x1813bb0, L_0x1813eb0, C4<1>, C4<1>; +L_0x1813aa0 .delay 1 (20000,20000,20000) L_0x1813aa0/d; +L_0x1813da0/d .functor OR 1, L_0x18137e0, L_0x1813aa0, C4<0>, C4<0>; +L_0x1813da0 .delay 1 (20000,20000,20000) L_0x1813da0/d; +v0x1750480_0 .net *"_s1", 0 0, L_0x1813940; 1 drivers +v0x1750580_0 .net *"_s3", 0 0, L_0x1813bb0; 1 drivers +v0x1750660_0 .net "addr", 0 0, L_0x1813eb0; 1 drivers +v0x1750700_0 .net "in", 1 0, L_0x18133d0; alias, 1 drivers +v0x17507e0_0 .net "naddr", 0 0, L_0x1812a80; 1 drivers +v0x17508f0_0 .net "o0", 0 0, L_0x18137e0; 1 drivers +v0x17509b0_0 .net "o1", 0 0, L_0x1813aa0; 1 drivers +v0x1750a70_0 .net "out", 0 0, L_0x1813da0; alias, 1 drivers +L_0x1813940 .part L_0x18133d0, 0, 1; +L_0x1813bb0 .part L_0x18133d0, 1, 1; +S_0x1751000 .scope module, "structadder" "structAddSub" 3 22, 5 8 0, S_0x174c440; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "sub" + .port_info 5 /INPUT 1 "carryin" +L_0x180e610/d .functor XOR 1, L_0x1814230, v0x17dbbc0_0, C4<0>, C4<0>; +L_0x180e610 .delay 1 (20000,20000,20000) L_0x180e610/d; +L_0x180ea90/d .functor XOR 1, L_0x180e8a0, L_0x1814230, C4<0>, C4<0>; +L_0x180ea90 .delay 1 (20000,20000,20000) L_0x180ea90/d; +L_0x180eba0/d .functor XOR 1, L_0x180ea90, L_0x1814010, C4<0>, C4<0>; +L_0x180eba0 .delay 1 (20000,20000,20000) L_0x180eba0/d; +L_0x180ed50/d .functor AND 1, L_0x180e8a0, L_0x1814230, C4<1>, C4<1>; +L_0x180ed50 .delay 1 (20000,20000,20000) L_0x180ed50/d; +L_0x180eeb0/d .functor AND 1, L_0x180ea90, L_0x1814010, C4<1>, C4<1>; +L_0x180eeb0 .delay 1 (20000,20000,20000) L_0x180eeb0/d; +L_0x180f010/d .functor OR 1, L_0x180eeb0, L_0x180ed50, C4<0>, C4<0>; +L_0x180f010 .delay 1 (20000,20000,20000) L_0x180f010/d; +v0x17512c0_0 .net "AandB", 0 0, L_0x180ed50; 1 drivers +v0x1751380_0 .net "AxorB", 0 0, L_0x180ea90; 1 drivers +v0x1751440_0 .net "AxorBandCarryIn", 0 0, L_0x180eeb0; 1 drivers +v0x1751510_0 .net "a", 0 0, L_0x180e8a0; alias, 1 drivers +v0x17515d0_0 .net "b", 0 0, L_0x1814230; alias, 1 drivers +v0x17516e0_0 .net "bnew", 0 0, L_0x180e610; 1 drivers +v0x17517a0_0 .net "carryin", 0 0, L_0x1814010; alias, 1 drivers +v0x1751860_0 .net "carryout", 0 0, L_0x180f010; alias, 1 drivers +v0x1751920_0 .net "sub", 0 0, v0x17dbbc0_0; alias, 1 drivers +v0x1751a50_0 .net "sum", 0 0, L_0x180eba0; 1 drivers +S_0x17528e0 .scope generate, "ripple[11]" "ripple[11]" 3 66, 3 66 0, S_0x16fa6c0; + .timescale -9 -12; +P_0x1752ab0 .param/l "i" 0 3 66, +C4<01011>; +S_0x1752b70 .scope module, "bit" "BitSliceALU" 3 68, 3 11 0, S_0x17528e0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "ALUout" + .port_info 1 /OUTPUT 1 "Cout" + .port_info 2 /INPUT 1 "invertB" + .port_info 3 /INPUT 1 "Cin" + .port_info 4 /INPUT 3 "addr" + .port_info 5 /INPUT 1 "bit1" + .port_info 6 /INPUT 1 "bit2" +L_0x1814ab0/d .functor XOR 1, L_0x1819a80, L_0x18143e0, C4<0>, C4<0>; +L_0x1814ab0 .delay 1 (20000,20000,20000) L_0x1814ab0/d; +L_0x1814c10/d .functor NAND 1, L_0x1819a80, L_0x18143e0, C4<1>, C4<1>; +L_0x1814c10 .delay 1 (10000,10000,10000) L_0x1814c10/d; +L_0x1814d70/d .functor XOR 1, v0x17dbbc0_0, L_0x1814c10, C4<0>, C4<0>; +L_0x1814d70 .delay 1 (20000,20000,20000) L_0x1814d70/d; +L_0x1814e80/d .functor NOR 1, L_0x1819a80, L_0x18143e0, C4<0>, C4<0>; +L_0x1814e80 .delay 1 (10000,10000,10000) L_0x1814e80/d; +L_0x1814fe0/d .functor XOR 1, v0x17dbbc0_0, L_0x1814e80, C4<0>, C4<0>; +L_0x1814fe0 .delay 1 (20000,20000,20000) L_0x1814fe0/d; +v0x1758340_0 .net "ALUout", 0 0, L_0x18196e0; 1 drivers +v0x1758400_0 .net "Cin", 0 0, L_0x1819950; 1 drivers +v0x17584c0_0 .net "Cout", 0 0, L_0x1814900; 1 drivers +v0x1758590_0 .net *"_s11", 0 0, L_0x1814fe0; 1 drivers +o0x7fc2cd91a7c8 .functor BUFZ 1, C4; HiZ drive +; Elide local net with no drivers, v0x1758630_0 name=_s15 +o0x7fc2cd91a7f8 .functor BUFZ 3, C4; HiZ drive +; Elide local net with no drivers, v0x1758720_0 name=_s17 +v0x1758800_0 .net *"_s3", 0 0, L_0x1814ab0; 1 drivers +v0x17588e0_0 .net *"_s7", 0 0, L_0x1814d70; 1 drivers +v0x17589c0_0 .net "addr", 2 0, v0x17dbc90_0; alias, 1 drivers +v0x1758b10_0 .net "bit1", 0 0, L_0x1819a80; 1 drivers +v0x1758bb0_0 .net "bit2", 0 0, L_0x18143e0; 1 drivers +v0x1758c80_0 .net "invertB", 0 0, v0x17dbbc0_0; alias, 1 drivers +v0x1758d20_0 .net "nanded", 0 0, L_0x1814c10; 1 drivers +v0x1758dc0_0 .net "nored", 0 0, L_0x1814e80; 1 drivers +v0x1758e60_0 .net "out", 7 0, L_0x1892a70; 1 drivers +LS_0x1892a70_0_0 .concat [ 1 1 1 1], L_0x18144e0, L_0x1814ab0, o0x7fc2cd91a7c8, L_0x1814d70; +LS_0x1892a70_0_4 .concat [ 1 3 0 0], L_0x1814fe0, o0x7fc2cd91a7f8; +L_0x1892a70 .concat [ 4 4 0 0], LS_0x1892a70_0_0, LS_0x1892a70_0_4; +S_0x1752e00 .scope module, "opmux" "structuralMultiplexer" 3 43, 4 21 0, S_0x1752b70; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 3 "address" + .port_info 2 /INPUT 8 "in" +v0x17572e0_0 .net "address", 2 0, v0x17dbc90_0; alias, 1 drivers +v0x17573a0_0 .net "in", 7 0, L_0x1892a70; alias, 1 drivers +v0x1757480_0 .net "mux", 3 0, L_0x18177a0; 1 drivers +v0x1757540_0 .net "muxmid", 1 0, L_0x1818d10; 1 drivers +v0x1757600_0 .net "out", 0 0, L_0x18196e0; alias, 1 drivers +L_0x18159d0 .part v0x17dbc90_0, 0, 1; +L_0x1815b30 .part L_0x1892a70, 0, 2; +L_0x18163c0 .part v0x17dbc90_0, 0, 1; +L_0x1816520 .part L_0x1892a70, 2, 2; +L_0x1816d90 .part v0x17dbc90_0, 0, 1; +L_0x1816ef0 .part L_0x1892a70, 4, 2; +L_0x18177a0 .concat8 [ 1 1 1 1], L_0x1815870, L_0x1816260, L_0x1816c30, L_0x1817640; +L_0x18179f0 .part v0x17dbc90_0, 0, 1; +L_0x1817ae0 .part L_0x1892a70, 6, 2; +L_0x1818320 .part v0x17dbc90_0, 1, 1; +L_0x1818480 .part L_0x18177a0, 0, 2; +L_0x1818d10 .concat8 [ 1 1 0 0], L_0x18181c0, L_0x1818bb0; +L_0x1818f10 .part v0x17dbc90_0, 1, 1; +L_0x1818fb0 .part L_0x18177a0, 2, 2; +L_0x18197f0 .part v0x17dbc90_0, 2, 1; +S_0x1753070 .scope module, "mux_0" "bitMultiplexer" 4 29, 4 8 0, S_0x1752e00; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "addr" + .port_info 2 /INPUT 2 "in" +L_0x18150f0/d .functor NOT 1, L_0x18159d0, C4<0>, C4<0>, C4<0>; +L_0x18150f0 .delay 1 (10000,10000,10000) L_0x18150f0/d; +L_0x1815250/d .functor AND 1, L_0x1815450, L_0x18150f0, C4<1>, C4<1>; +L_0x1815250 .delay 1 (20000,20000,20000) L_0x1815250/d; +L_0x18155b0/d .functor AND 1, L_0x18156c0, L_0x18159d0, C4<1>, C4<1>; +L_0x18155b0 .delay 1 (20000,20000,20000) L_0x18155b0/d; +L_0x1815870/d .functor OR 1, L_0x1815250, L_0x18155b0, C4<0>, C4<0>; +L_0x1815870 .delay 1 (20000,20000,20000) L_0x1815870/d; +v0x17532e0_0 .net *"_s1", 0 0, L_0x1815450; 1 drivers +v0x17533e0_0 .net *"_s3", 0 0, L_0x18156c0; 1 drivers +v0x17534c0_0 .net "addr", 0 0, L_0x18159d0; 1 drivers +v0x1753590_0 .net "in", 1 0, L_0x1815b30; 1 drivers +v0x1753670_0 .net "naddr", 0 0, L_0x18150f0; 1 drivers +v0x1753780_0 .net "o0", 0 0, L_0x1815250; 1 drivers +v0x1753840_0 .net "o1", 0 0, L_0x18155b0; 1 drivers +v0x1753900_0 .net "out", 0 0, L_0x1815870; 1 drivers +L_0x1815450 .part L_0x1815b30, 0, 1; +L_0x18156c0 .part L_0x1815b30, 1, 1; +S_0x1753a40 .scope module, "mux_1" "bitMultiplexer" 4 30, 4 8 0, S_0x1752e00; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "addr" + .port_info 2 /INPUT 2 "in" +L_0x1815bd0/d .functor NOT 1, L_0x18163c0, C4<0>, C4<0>, C4<0>; +L_0x1815bd0 .delay 1 (10000,10000,10000) L_0x1815bd0/d; +L_0x1815c90/d .functor AND 1, L_0x1815e40, L_0x1815bd0, C4<1>, C4<1>; +L_0x1815c90 .delay 1 (20000,20000,20000) L_0x1815c90/d; +L_0x1815fa0/d .functor AND 1, L_0x18160b0, L_0x18163c0, C4<1>, C4<1>; +L_0x1815fa0 .delay 1 (20000,20000,20000) L_0x1815fa0/d; +L_0x1816260/d .functor OR 1, L_0x1815c90, L_0x1815fa0, C4<0>, C4<0>; +L_0x1816260 .delay 1 (20000,20000,20000) L_0x1816260/d; +v0x1753c70_0 .net *"_s1", 0 0, L_0x1815e40; 1 drivers +v0x1753d70_0 .net *"_s3", 0 0, L_0x18160b0; 1 drivers +v0x1753e50_0 .net "addr", 0 0, L_0x18163c0; 1 drivers +v0x1753ef0_0 .net "in", 1 0, L_0x1816520; 1 drivers +v0x1753fd0_0 .net "naddr", 0 0, L_0x1815bd0; 1 drivers +v0x17540e0_0 .net "o0", 0 0, L_0x1815c90; 1 drivers +v0x17541a0_0 .net "o1", 0 0, L_0x1815fa0; 1 drivers +v0x1754260_0 .net "out", 0 0, L_0x1816260; 1 drivers +L_0x1815e40 .part L_0x1816520, 0, 1; +L_0x18160b0 .part L_0x1816520, 1, 1; +S_0x17543a0 .scope module, "mux_2" "bitMultiplexer" 4 31, 4 8 0, S_0x1752e00; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "addr" + .port_info 2 /INPUT 2 "in" +L_0x1816460/d .functor NOT 1, L_0x1816d90, C4<0>, C4<0>, C4<0>; +L_0x1816460 .delay 1 (10000,10000,10000) L_0x1816460/d; +L_0x1816610/d .functor AND 1, L_0x1816810, L_0x1816460, C4<1>, C4<1>; +L_0x1816610 .delay 1 (20000,20000,20000) L_0x1816610/d; +L_0x1816970/d .functor AND 1, L_0x1816a80, L_0x1816d90, C4<1>, C4<1>; +L_0x1816970 .delay 1 (20000,20000,20000) L_0x1816970/d; +L_0x1816c30/d .functor OR 1, L_0x1816610, L_0x1816970, C4<0>, C4<0>; +L_0x1816c30 .delay 1 (20000,20000,20000) L_0x1816c30/d; +v0x17545d0_0 .net *"_s1", 0 0, L_0x1816810; 1 drivers +v0x17546b0_0 .net *"_s3", 0 0, L_0x1816a80; 1 drivers +v0x1754790_0 .net "addr", 0 0, L_0x1816d90; 1 drivers +v0x1754860_0 .net "in", 1 0, L_0x1816ef0; 1 drivers +v0x1754940_0 .net "naddr", 0 0, L_0x1816460; 1 drivers +v0x1754a50_0 .net "o0", 0 0, L_0x1816610; 1 drivers +v0x1754b10_0 .net "o1", 0 0, L_0x1816970; 1 drivers +v0x1754bd0_0 .net "out", 0 0, L_0x1816c30; 1 drivers +L_0x1816810 .part L_0x1816ef0, 0, 1; +L_0x1816a80 .part L_0x1816ef0, 1, 1; +S_0x1754d10 .scope module, "mux_3" "bitMultiplexer" 4 32, 4 8 0, S_0x1752e00; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "addr" + .port_info 2 /INPUT 2 "in" +L_0x1816e30/d .functor NOT 1, L_0x18179f0, C4<0>, C4<0>, C4<0>; +L_0x1816e30 .delay 1 (10000,10000,10000) L_0x1816e30/d; +L_0x1817020/d .functor AND 1, L_0x1817220, L_0x1816e30, C4<1>, C4<1>; +L_0x1817020 .delay 1 (20000,20000,20000) L_0x1817020/d; +L_0x1817380/d .functor AND 1, L_0x1817490, L_0x18179f0, C4<1>, C4<1>; +L_0x1817380 .delay 1 (20000,20000,20000) L_0x1817380/d; +L_0x1817640/d .functor OR 1, L_0x1817020, L_0x1817380, C4<0>, C4<0>; +L_0x1817640 .delay 1 (20000,20000,20000) L_0x1817640/d; +v0x1754f40_0 .net *"_s1", 0 0, L_0x1817220; 1 drivers +v0x1755040_0 .net *"_s3", 0 0, L_0x1817490; 1 drivers +v0x1755120_0 .net "addr", 0 0, L_0x18179f0; 1 drivers +v0x17551c0_0 .net "in", 1 0, L_0x1817ae0; 1 drivers +v0x17552a0_0 .net "naddr", 0 0, L_0x1816e30; 1 drivers +v0x17553b0_0 .net "o0", 0 0, L_0x1817020; 1 drivers +v0x1755470_0 .net "o1", 0 0, L_0x1817380; 1 drivers +v0x1755530_0 .net "out", 0 0, L_0x1817640; 1 drivers +L_0x1817220 .part L_0x1817ae0, 0, 1; +L_0x1817490 .part L_0x1817ae0, 1, 1; +S_0x1755670 .scope module, "mux_mid_0" "bitMultiplexer" 4 33, 4 8 0, S_0x1752e00; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "addr" + .port_info 2 /INPUT 2 "in" +L_0x1817b80/d .functor NOT 1, L_0x1818320, C4<0>, C4<0>, C4<0>; +L_0x1817b80 .delay 1 (10000,10000,10000) L_0x1817b80/d; +L_0x1817c40/d .functor AND 1, L_0x1817da0, L_0x1817b80, C4<1>, C4<1>; +L_0x1817c40 .delay 1 (20000,20000,20000) L_0x1817c40/d; +L_0x1817f00/d .functor AND 1, L_0x1818010, L_0x1818320, C4<1>, C4<1>; +L_0x1817f00 .delay 1 (20000,20000,20000) L_0x1817f00/d; +L_0x18181c0/d .functor OR 1, L_0x1817c40, L_0x1817f00, C4<0>, C4<0>; +L_0x18181c0 .delay 1 (20000,20000,20000) L_0x18181c0/d; +v0x17558f0_0 .net *"_s1", 0 0, L_0x1817da0; 1 drivers +v0x17559f0_0 .net *"_s3", 0 0, L_0x1818010; 1 drivers +v0x1755ad0_0 .net "addr", 0 0, L_0x1818320; 1 drivers +v0x1755b70_0 .net "in", 1 0, L_0x1818480; 1 drivers +v0x1755c50_0 .net "naddr", 0 0, L_0x1817b80; 1 drivers +v0x1755d60_0 .net "o0", 0 0, L_0x1817c40; 1 drivers +v0x1755e20_0 .net "o1", 0 0, L_0x1817f00; 1 drivers +v0x1755ee0_0 .net "out", 0 0, L_0x18181c0; 1 drivers +L_0x1817da0 .part L_0x1818480, 0, 1; +L_0x1818010 .part L_0x1818480, 1, 1; +S_0x1756020 .scope module, "mux_mid_1" "bitMultiplexer" 4 34, 4 8 0, S_0x1752e00; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "addr" + .port_info 2 /INPUT 2 "in" +L_0x1818520/d .functor NOT 1, L_0x1818f10, C4<0>, C4<0>, C4<0>; +L_0x1818520 .delay 1 (10000,10000,10000) L_0x1818520/d; +L_0x18185e0/d .functor AND 1, L_0x1818790, L_0x1818520, C4<1>, C4<1>; +L_0x18185e0 .delay 1 (20000,20000,20000) L_0x18185e0/d; +L_0x18188f0/d .functor AND 1, L_0x1818a00, L_0x1818f10, C4<1>, C4<1>; +L_0x18188f0 .delay 1 (20000,20000,20000) L_0x18188f0/d; +L_0x1818bb0/d .functor OR 1, L_0x18185e0, L_0x18188f0, C4<0>, C4<0>; +L_0x1818bb0 .delay 1 (20000,20000,20000) L_0x1818bb0/d; +v0x1756250_0 .net *"_s1", 0 0, L_0x1818790; 1 drivers +v0x1756350_0 .net *"_s3", 0 0, L_0x1818a00; 1 drivers +v0x1756430_0 .net "addr", 0 0, L_0x1818f10; 1 drivers +v0x17564d0_0 .net "in", 1 0, L_0x1818fb0; 1 drivers +v0x17565b0_0 .net "naddr", 0 0, L_0x1818520; 1 drivers +v0x17566c0_0 .net "o0", 0 0, L_0x18185e0; 1 drivers +v0x1756780_0 .net "o1", 0 0, L_0x18188f0; 1 drivers +v0x1756840_0 .net "out", 0 0, L_0x1818bb0; 1 drivers +L_0x1818790 .part L_0x1818fb0, 0, 1; +L_0x1818a00 .part L_0x1818fb0, 1, 1; +S_0x1756980 .scope module, "mux_out" "bitMultiplexer" 4 35, 4 8 0, S_0x1752e00; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "addr" + .port_info 2 /INPUT 2 "in" +L_0x18183c0/d .functor NOT 1, L_0x18197f0, C4<0>, C4<0>, C4<0>; +L_0x18183c0 .delay 1 (10000,10000,10000) L_0x18183c0/d; +L_0x1819120/d .functor AND 1, L_0x1819280, L_0x18183c0, C4<1>, C4<1>; +L_0x1819120 .delay 1 (20000,20000,20000) L_0x1819120/d; +L_0x18193e0/d .functor AND 1, L_0x18194f0, L_0x18197f0, C4<1>, C4<1>; +L_0x18193e0 .delay 1 (20000,20000,20000) L_0x18193e0/d; +L_0x18196e0/d .functor OR 1, L_0x1819120, L_0x18193e0, C4<0>, C4<0>; +L_0x18196e0 .delay 1 (20000,20000,20000) L_0x18196e0/d; +v0x1756bb0_0 .net *"_s1", 0 0, L_0x1819280; 1 drivers +v0x1756cb0_0 .net *"_s3", 0 0, L_0x18194f0; 1 drivers +v0x1756d90_0 .net "addr", 0 0, L_0x18197f0; 1 drivers +v0x1756e30_0 .net "in", 1 0, L_0x1818d10; alias, 1 drivers +v0x1756f10_0 .net "naddr", 0 0, L_0x18183c0; 1 drivers +v0x1757020_0 .net "o0", 0 0, L_0x1819120; 1 drivers +v0x17570e0_0 .net "o1", 0 0, L_0x18193e0; 1 drivers +v0x17571a0_0 .net "out", 0 0, L_0x18196e0; alias, 1 drivers +L_0x1819280 .part L_0x1818d10, 0, 1; +L_0x18194f0 .part L_0x1818d10, 1, 1; +S_0x1757730 .scope module, "structadder" "structAddSub" 3 22, 5 8 0, S_0x1752b70; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "sub" + .port_info 5 /INPUT 1 "carryin" +L_0x1813f50/d .functor XOR 1, L_0x18143e0, v0x17dbbc0_0, C4<0>, C4<0>; +L_0x1813f50 .delay 1 (20000,20000,20000) L_0x1813f50/d; +L_0x1810350/d .functor XOR 1, L_0x1819a80, L_0x18143e0, C4<0>, C4<0>; +L_0x1810350 .delay 1 (20000,20000,20000) L_0x1810350/d; +L_0x18144e0/d .functor XOR 1, L_0x1810350, L_0x1819950, C4<0>, C4<0>; +L_0x18144e0 .delay 1 (20000,20000,20000) L_0x18144e0/d; +L_0x1814640/d .functor AND 1, L_0x1819a80, L_0x18143e0, C4<1>, C4<1>; +L_0x1814640 .delay 1 (20000,20000,20000) L_0x1814640/d; +L_0x18147a0/d .functor AND 1, L_0x1810350, L_0x1819950, C4<1>, C4<1>; +L_0x18147a0 .delay 1 (20000,20000,20000) L_0x18147a0/d; +L_0x1814900/d .functor OR 1, L_0x18147a0, L_0x1814640, C4<0>, C4<0>; +L_0x1814900 .delay 1 (20000,20000,20000) L_0x1814900/d; +v0x17579f0_0 .net "AandB", 0 0, L_0x1814640; 1 drivers +v0x1757ab0_0 .net "AxorB", 0 0, L_0x1810350; 1 drivers +v0x1757b70_0 .net "AxorBandCarryIn", 0 0, L_0x18147a0; 1 drivers +v0x1757c40_0 .net "a", 0 0, L_0x1819a80; alias, 1 drivers +v0x1757d00_0 .net "b", 0 0, L_0x18143e0; alias, 1 drivers +v0x1757e10_0 .net "bnew", 0 0, L_0x1813f50; 1 drivers +v0x1757ed0_0 .net "carryin", 0 0, L_0x1819950; alias, 1 drivers +v0x1757f90_0 .net "carryout", 0 0, L_0x1814900; alias, 1 drivers +v0x1758050_0 .net "sub", 0 0, v0x17dbbc0_0; alias, 1 drivers +v0x1758180_0 .net "sum", 0 0, L_0x18144e0; 1 drivers +S_0x1759010 .scope generate, "ripple[12]" "ripple[12]" 3 66, 3 66 0, S_0x16fa6c0; + .timescale -9 -12; +P_0x17591e0 .param/l "i" 0 3 66, +C4<01100>; +S_0x17592a0 .scope module, "bit" "BitSliceALU" 3 68, 3 11 0, S_0x1759010; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "ALUout" + .port_info 1 /OUTPUT 1 "Cout" + .port_info 2 /INPUT 1 "invertB" + .port_info 3 /INPUT 1 "Cin" + .port_info 4 /INPUT 3 "addr" + .port_info 5 /INPUT 1 "bit1" + .port_info 6 /INPUT 1 "bit2" +L_0x181a420/d .functor XOR 1, L_0x1819b20, L_0x181f4c0, C4<0>, C4<0>; +L_0x181a420 .delay 1 (20000,20000,20000) L_0x181a420/d; +L_0x181a580/d .functor NAND 1, L_0x1819b20, L_0x181f4c0, C4<1>, C4<1>; +L_0x181a580 .delay 1 (10000,10000,10000) L_0x181a580/d; +L_0x181a6e0/d .functor XOR 1, v0x17dbbc0_0, L_0x181a580, C4<0>, C4<0>; +L_0x181a6e0 .delay 1 (20000,20000,20000) L_0x181a6e0/d; +L_0x181a7f0/d .functor NOR 1, L_0x1819b20, L_0x181f4c0, C4<0>, C4<0>; +L_0x181a7f0 .delay 1 (10000,10000,10000) L_0x181a7f0/d; +L_0x181a950/d .functor XOR 1, v0x17dbbc0_0, L_0x181a7f0, C4<0>, C4<0>; +L_0x181a950 .delay 1 (20000,20000,20000) L_0x181a950/d; +v0x175ea70_0 .net "ALUout", 0 0, L_0x181f000; 1 drivers +v0x175eb30_0 .net "Cin", 0 0, L_0x181f270; 1 drivers +v0x175ebf0_0 .net "Cout", 0 0, L_0x181a270; 1 drivers +v0x175ecc0_0 .net *"_s11", 0 0, L_0x181a950; 1 drivers +o0x7fc2cd91bc98 .functor BUFZ 1, C4; HiZ drive +; Elide local net with no drivers, v0x175ed60_0 name=_s15 +o0x7fc2cd91bcc8 .functor BUFZ 3, C4; HiZ drive +; Elide local net with no drivers, v0x175ee50_0 name=_s17 +v0x175ef30_0 .net *"_s3", 0 0, L_0x181a420; 1 drivers +v0x175f010_0 .net *"_s7", 0 0, L_0x181a6e0; 1 drivers +v0x175f0f0_0 .net "addr", 2 0, v0x17dbc90_0; alias, 1 drivers +v0x175f240_0 .net "bit1", 0 0, L_0x1819b20; 1 drivers +v0x175f2e0_0 .net "bit2", 0 0, L_0x181f4c0; 1 drivers +v0x175f3b0_0 .net "invertB", 0 0, v0x17dbbc0_0; alias, 1 drivers +v0x175f450_0 .net "nanded", 0 0, L_0x181a580; 1 drivers +v0x175f4f0_0 .net "nored", 0 0, L_0x181a7f0; 1 drivers +v0x175f590_0 .net "out", 7 0, L_0x1892c50; 1 drivers +LS_0x1892c50_0_0 .concat [ 1 1 1 1], L_0x1819e00, L_0x181a420, o0x7fc2cd91bc98, L_0x181a6e0; +LS_0x1892c50_0_4 .concat [ 1 3 0 0], L_0x181a950, o0x7fc2cd91bcc8; +L_0x1892c50 .concat [ 4 4 0 0], LS_0x1892c50_0_0, LS_0x1892c50_0_4; +S_0x1759530 .scope module, "opmux" "structuralMultiplexer" 3 43, 4 21 0, S_0x17592a0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 3 "address" + .port_info 2 /INPUT 8 "in" +v0x175da10_0 .net "address", 2 0, v0x17dbc90_0; alias, 1 drivers +v0x175dad0_0 .net "in", 7 0, L_0x1892c50; alias, 1 drivers +v0x175dbb0_0 .net "mux", 3 0, L_0x181d070; 1 drivers +v0x175dc70_0 .net "muxmid", 1 0, L_0x181e630; 1 drivers +v0x175dd30_0 .net "out", 0 0, L_0x181f000; alias, 1 drivers +L_0x181b250 .part v0x17dbc90_0, 0, 1; +L_0x181b3b0 .part L_0x1892c50, 0, 2; +L_0x181bc90 .part v0x17dbc90_0, 0, 1; +L_0x181bdf0 .part L_0x1892c50, 2, 2; +L_0x181c660 .part v0x17dbc90_0, 0, 1; +L_0x181c7c0 .part L_0x1892c50, 4, 2; +L_0x181d070 .concat8 [ 1 1 1 1], L_0x181b0f0, L_0x181bb30, L_0x181c500, L_0x181cf10; +L_0x181d310 .part v0x17dbc90_0, 0, 1; +L_0x181d400 .part L_0x1892c50, 6, 2; +L_0x181dc40 .part v0x17dbc90_0, 1, 1; +L_0x181dda0 .part L_0x181d070, 0, 2; +L_0x181e630 .concat8 [ 1 1 0 0], L_0x181dae0, L_0x181e4d0; +L_0x181e830 .part v0x17dbc90_0, 1, 1; +L_0x181e8d0 .part L_0x181d070, 2, 2; +L_0x181f110 .part v0x17dbc90_0, 2, 1; +S_0x17597a0 .scope module, "mux_0" "bitMultiplexer" 4 29, 4 8 0, S_0x1759530; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "addr" + .port_info 2 /INPUT 2 "in" +L_0x181aa60/d .functor NOT 1, L_0x181b250, C4<0>, C4<0>, C4<0>; +L_0x181aa60 .delay 1 (10000,10000,10000) L_0x181aa60/d; +L_0x181abc0/d .functor AND 1, L_0x181acd0, L_0x181aa60, C4<1>, C4<1>; +L_0x181abc0 .delay 1 (20000,20000,20000) L_0x181abc0/d; +L_0x181ae30/d .functor AND 1, L_0x181af40, L_0x181b250, C4<1>, C4<1>; +L_0x181ae30 .delay 1 (20000,20000,20000) L_0x181ae30/d; +L_0x181b0f0/d .functor OR 1, L_0x181abc0, L_0x181ae30, C4<0>, C4<0>; +L_0x181b0f0 .delay 1 (20000,20000,20000) L_0x181b0f0/d; +v0x1759a10_0 .net *"_s1", 0 0, L_0x181acd0; 1 drivers +v0x1759b10_0 .net *"_s3", 0 0, L_0x181af40; 1 drivers +v0x1759bf0_0 .net "addr", 0 0, L_0x181b250; 1 drivers +v0x1759cc0_0 .net "in", 1 0, L_0x181b3b0; 1 drivers +v0x1759da0_0 .net "naddr", 0 0, L_0x181aa60; 1 drivers +v0x1759eb0_0 .net "o0", 0 0, L_0x181abc0; 1 drivers +v0x1759f70_0 .net "o1", 0 0, L_0x181ae30; 1 drivers +v0x175a030_0 .net "out", 0 0, L_0x181b0f0; 1 drivers +L_0x181acd0 .part L_0x181b3b0, 0, 1; +L_0x181af40 .part L_0x181b3b0, 1, 1; +S_0x175a170 .scope module, "mux_1" "bitMultiplexer" 4 30, 4 8 0, S_0x1759530; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "addr" + .port_info 2 /INPUT 2 "in" +L_0x181b450/d .functor NOT 1, L_0x181bc90, C4<0>, C4<0>, C4<0>; +L_0x181b450 .delay 1 (10000,10000,10000) L_0x181b450/d; +L_0x181b510/d .functor AND 1, L_0x181b710, L_0x181b450, C4<1>, C4<1>; +L_0x181b510 .delay 1 (20000,20000,20000) L_0x181b510/d; +L_0x181b870/d .functor AND 1, L_0x181b980, L_0x181bc90, C4<1>, C4<1>; +L_0x181b870 .delay 1 (20000,20000,20000) L_0x181b870/d; +L_0x181bb30/d .functor OR 1, L_0x181b510, L_0x181b870, C4<0>, C4<0>; +L_0x181bb30 .delay 1 (20000,20000,20000) L_0x181bb30/d; +v0x175a3a0_0 .net *"_s1", 0 0, L_0x181b710; 1 drivers +v0x175a4a0_0 .net *"_s3", 0 0, L_0x181b980; 1 drivers +v0x175a580_0 .net "addr", 0 0, L_0x181bc90; 1 drivers +v0x175a620_0 .net "in", 1 0, L_0x181bdf0; 1 drivers +v0x175a700_0 .net "naddr", 0 0, L_0x181b450; 1 drivers +v0x175a810_0 .net "o0", 0 0, L_0x181b510; 1 drivers +v0x175a8d0_0 .net "o1", 0 0, L_0x181b870; 1 drivers +v0x175a990_0 .net "out", 0 0, L_0x181bb30; 1 drivers +L_0x181b710 .part L_0x181bdf0, 0, 1; +L_0x181b980 .part L_0x181bdf0, 1, 1; +S_0x175aad0 .scope module, "mux_2" "bitMultiplexer" 4 31, 4 8 0, S_0x1759530; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "addr" + .port_info 2 /INPUT 2 "in" +L_0x181bd30/d .functor NOT 1, L_0x181c660, C4<0>, C4<0>, C4<0>; +L_0x181bd30 .delay 1 (10000,10000,10000) L_0x181bd30/d; +L_0x181bee0/d .functor AND 1, L_0x181c0e0, L_0x181bd30, C4<1>, C4<1>; +L_0x181bee0 .delay 1 (20000,20000,20000) L_0x181bee0/d; +L_0x181c240/d .functor AND 1, L_0x181c350, L_0x181c660, C4<1>, C4<1>; +L_0x181c240 .delay 1 (20000,20000,20000) L_0x181c240/d; +L_0x181c500/d .functor OR 1, L_0x181bee0, L_0x181c240, C4<0>, C4<0>; +L_0x181c500 .delay 1 (20000,20000,20000) L_0x181c500/d; +v0x175ad00_0 .net *"_s1", 0 0, L_0x181c0e0; 1 drivers +v0x175ade0_0 .net *"_s3", 0 0, L_0x181c350; 1 drivers +v0x175aec0_0 .net "addr", 0 0, L_0x181c660; 1 drivers +v0x175af90_0 .net "in", 1 0, L_0x181c7c0; 1 drivers +v0x175b070_0 .net "naddr", 0 0, L_0x181bd30; 1 drivers +v0x175b180_0 .net "o0", 0 0, L_0x181bee0; 1 drivers +v0x175b240_0 .net "o1", 0 0, L_0x181c240; 1 drivers +v0x175b300_0 .net "out", 0 0, L_0x181c500; 1 drivers +L_0x181c0e0 .part L_0x181c7c0, 0, 1; +L_0x181c350 .part L_0x181c7c0, 1, 1; +S_0x175b440 .scope module, "mux_3" "bitMultiplexer" 4 32, 4 8 0, S_0x1759530; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "addr" + .port_info 2 /INPUT 2 "in" +L_0x181c700/d .functor NOT 1, L_0x181d310, C4<0>, C4<0>, C4<0>; +L_0x181c700 .delay 1 (10000,10000,10000) L_0x181c700/d; +L_0x181c8f0/d .functor AND 1, L_0x181caf0, L_0x181c700, C4<1>, C4<1>; +L_0x181c8f0 .delay 1 (20000,20000,20000) L_0x181c8f0/d; +L_0x181cc50/d .functor AND 1, L_0x181cd60, L_0x181d310, C4<1>, C4<1>; +L_0x181cc50 .delay 1 (20000,20000,20000) L_0x181cc50/d; +L_0x181cf10/d .functor OR 1, L_0x181c8f0, L_0x181cc50, C4<0>, C4<0>; +L_0x181cf10 .delay 1 (20000,20000,20000) L_0x181cf10/d; +v0x175b670_0 .net *"_s1", 0 0, L_0x181caf0; 1 drivers +v0x175b770_0 .net *"_s3", 0 0, L_0x181cd60; 1 drivers +v0x175b850_0 .net "addr", 0 0, L_0x181d310; 1 drivers +v0x175b8f0_0 .net "in", 1 0, L_0x181d400; 1 drivers +v0x175b9d0_0 .net "naddr", 0 0, L_0x181c700; 1 drivers +v0x175bae0_0 .net "o0", 0 0, L_0x181c8f0; 1 drivers +v0x175bba0_0 .net "o1", 0 0, L_0x181cc50; 1 drivers +v0x175bc60_0 .net "out", 0 0, L_0x181cf10; 1 drivers +L_0x181caf0 .part L_0x181d400, 0, 1; +L_0x181cd60 .part L_0x181d400, 1, 1; +S_0x175bda0 .scope module, "mux_mid_0" "bitMultiplexer" 4 33, 4 8 0, S_0x1759530; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "addr" + .port_info 2 /INPUT 2 "in" +L_0x181d4a0/d .functor NOT 1, L_0x181dc40, C4<0>, C4<0>, C4<0>; +L_0x181d4a0 .delay 1 (10000,10000,10000) L_0x181d4a0/d; +L_0x181d560/d .functor AND 1, L_0x181d6c0, L_0x181d4a0, C4<1>, C4<1>; +L_0x181d560 .delay 1 (20000,20000,20000) L_0x181d560/d; +L_0x181d820/d .functor AND 1, L_0x181d930, L_0x181dc40, C4<1>, C4<1>; +L_0x181d820 .delay 1 (20000,20000,20000) L_0x181d820/d; +L_0x181dae0/d .functor OR 1, L_0x181d560, L_0x181d820, C4<0>, C4<0>; +L_0x181dae0 .delay 1 (20000,20000,20000) L_0x181dae0/d; +v0x175c020_0 .net *"_s1", 0 0, L_0x181d6c0; 1 drivers +v0x175c120_0 .net *"_s3", 0 0, L_0x181d930; 1 drivers +v0x175c200_0 .net "addr", 0 0, L_0x181dc40; 1 drivers +v0x175c2a0_0 .net "in", 1 0, L_0x181dda0; 1 drivers +v0x175c380_0 .net "naddr", 0 0, L_0x181d4a0; 1 drivers +v0x175c490_0 .net "o0", 0 0, L_0x181d560; 1 drivers +v0x175c550_0 .net "o1", 0 0, L_0x181d820; 1 drivers +v0x175c610_0 .net "out", 0 0, L_0x181dae0; 1 drivers +L_0x181d6c0 .part L_0x181dda0, 0, 1; +L_0x181d930 .part L_0x181dda0, 1, 1; +S_0x175c750 .scope module, "mux_mid_1" "bitMultiplexer" 4 34, 4 8 0, S_0x1759530; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "addr" + .port_info 2 /INPUT 2 "in" +L_0x181de40/d .functor NOT 1, L_0x181e830, C4<0>, C4<0>, C4<0>; +L_0x181de40 .delay 1 (10000,10000,10000) L_0x181de40/d; +L_0x181df00/d .functor AND 1, L_0x181e0b0, L_0x181de40, C4<1>, C4<1>; +L_0x181df00 .delay 1 (20000,20000,20000) L_0x181df00/d; +L_0x181e210/d .functor AND 1, L_0x181e320, L_0x181e830, C4<1>, C4<1>; +L_0x181e210 .delay 1 (20000,20000,20000) L_0x181e210/d; +L_0x181e4d0/d .functor OR 1, L_0x181df00, L_0x181e210, C4<0>, C4<0>; +L_0x181e4d0 .delay 1 (20000,20000,20000) L_0x181e4d0/d; +v0x175c980_0 .net *"_s1", 0 0, L_0x181e0b0; 1 drivers +v0x175ca80_0 .net *"_s3", 0 0, L_0x181e320; 1 drivers +v0x175cb60_0 .net "addr", 0 0, L_0x181e830; 1 drivers +v0x175cc00_0 .net "in", 1 0, L_0x181e8d0; 1 drivers +v0x175cce0_0 .net "naddr", 0 0, L_0x181de40; 1 drivers +v0x175cdf0_0 .net "o0", 0 0, L_0x181df00; 1 drivers +v0x175ceb0_0 .net "o1", 0 0, L_0x181e210; 1 drivers +v0x175cf70_0 .net "out", 0 0, L_0x181e4d0; 1 drivers +L_0x181e0b0 .part L_0x181e8d0, 0, 1; +L_0x181e320 .part L_0x181e8d0, 1, 1; +S_0x175d0b0 .scope module, "mux_out" "bitMultiplexer" 4 35, 4 8 0, S_0x1759530; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "addr" + .port_info 2 /INPUT 2 "in" +L_0x181dce0/d .functor NOT 1, L_0x181f110, C4<0>, C4<0>, C4<0>; +L_0x181dce0 .delay 1 (10000,10000,10000) L_0x181dce0/d; +L_0x181ea40/d .functor AND 1, L_0x181eba0, L_0x181dce0, C4<1>, C4<1>; +L_0x181ea40 .delay 1 (20000,20000,20000) L_0x181ea40/d; +L_0x181ed00/d .functor AND 1, L_0x181ee10, L_0x181f110, C4<1>, C4<1>; +L_0x181ed00 .delay 1 (20000,20000,20000) L_0x181ed00/d; +L_0x181f000/d .functor OR 1, L_0x181ea40, L_0x181ed00, C4<0>, C4<0>; +L_0x181f000 .delay 1 (20000,20000,20000) L_0x181f000/d; +v0x175d2e0_0 .net *"_s1", 0 0, L_0x181eba0; 1 drivers +v0x175d3e0_0 .net *"_s3", 0 0, L_0x181ee10; 1 drivers +v0x175d4c0_0 .net "addr", 0 0, L_0x181f110; 1 drivers +v0x175d560_0 .net "in", 1 0, L_0x181e630; alias, 1 drivers +v0x175d640_0 .net "naddr", 0 0, L_0x181dce0; 1 drivers +v0x175d750_0 .net "o0", 0 0, L_0x181ea40; 1 drivers +v0x175d810_0 .net "o1", 0 0, L_0x181ed00; 1 drivers +v0x175d8d0_0 .net "out", 0 0, L_0x181f000; alias, 1 drivers +L_0x181eba0 .part L_0x181e630, 0, 1; +L_0x181ee10 .part L_0x181e630, 1, 1; +S_0x175de60 .scope module, "structadder" "structAddSub" 3 22, 5 8 0, S_0x17592a0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "sub" + .port_info 5 /INPUT 1 "carryin" +L_0x1819890/d .functor XOR 1, L_0x181f4c0, v0x17dbbc0_0, C4<0>, C4<0>; +L_0x1819890 .delay 1 (20000,20000,20000) L_0x1819890/d; +L_0x1819d40/d .functor XOR 1, L_0x1819b20, L_0x181f4c0, C4<0>, C4<0>; +L_0x1819d40 .delay 1 (20000,20000,20000) L_0x1819d40/d; +L_0x1819e00/d .functor XOR 1, L_0x1819d40, L_0x181f270, C4<0>, C4<0>; +L_0x1819e00 .delay 1 (20000,20000,20000) L_0x1819e00/d; +L_0x1819fb0/d .functor AND 1, L_0x1819b20, L_0x181f4c0, C4<1>, C4<1>; +L_0x1819fb0 .delay 1 (20000,20000,20000) L_0x1819fb0/d; +L_0x181a110/d .functor AND 1, L_0x1819d40, L_0x181f270, C4<1>, C4<1>; +L_0x181a110 .delay 1 (20000,20000,20000) L_0x181a110/d; +L_0x181a270/d .functor OR 1, L_0x181a110, L_0x1819fb0, C4<0>, C4<0>; +L_0x181a270 .delay 1 (20000,20000,20000) L_0x181a270/d; +v0x175e120_0 .net "AandB", 0 0, L_0x1819fb0; 1 drivers +v0x175e1e0_0 .net "AxorB", 0 0, L_0x1819d40; 1 drivers +v0x175e2a0_0 .net "AxorBandCarryIn", 0 0, L_0x181a110; 1 drivers +v0x175e370_0 .net "a", 0 0, L_0x1819b20; alias, 1 drivers +v0x175e430_0 .net "b", 0 0, L_0x181f4c0; alias, 1 drivers +v0x175e540_0 .net "bnew", 0 0, L_0x1819890; 1 drivers +v0x175e600_0 .net "carryin", 0 0, L_0x181f270; alias, 1 drivers +v0x175e6c0_0 .net "carryout", 0 0, L_0x181a270; alias, 1 drivers +v0x175e780_0 .net "sub", 0 0, v0x17dbbc0_0; alias, 1 drivers +v0x175e8b0_0 .net "sum", 0 0, L_0x1819e00; 1 drivers +S_0x175f740 .scope generate, "ripple[13]" "ripple[13]" 3 66, 3 66 0, S_0x16fa6c0; + .timescale -9 -12; +P_0x175f910 .param/l "i" 0 3 66, +C4<01101>; +S_0x175f9d0 .scope module, "bit" "BitSliceALU" 3 68, 3 11 0, S_0x175f740; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "ALUout" + .port_info 1 /OUTPUT 1 "Cout" + .port_info 2 /INPUT 1 "invertB" + .port_info 3 /INPUT 1 "Cin" + .port_info 4 /INPUT 3 "addr" + .port_info 5 /INPUT 1 "bit1" + .port_info 6 /INPUT 1 "bit2" +L_0x181fd70/d .functor XOR 1, L_0x1824cf0, L_0x181f670, C4<0>, C4<0>; +L_0x181fd70 .delay 1 (20000,20000,20000) L_0x181fd70/d; +L_0x181fed0/d .functor NAND 1, L_0x1824cf0, L_0x181f670, C4<1>, C4<1>; +L_0x181fed0 .delay 1 (10000,10000,10000) L_0x181fed0/d; +L_0x1820030/d .functor XOR 1, v0x17dbbc0_0, L_0x181fed0, C4<0>, C4<0>; +L_0x1820030 .delay 1 (20000,20000,20000) L_0x1820030/d; +L_0x1820140/d .functor NOR 1, L_0x1824cf0, L_0x181f670, C4<0>, C4<0>; +L_0x1820140 .delay 1 (10000,10000,10000) L_0x1820140/d; +L_0x18202a0/d .functor XOR 1, v0x17dbbc0_0, L_0x1820140, C4<0>, C4<0>; +L_0x18202a0 .delay 1 (20000,20000,20000) L_0x18202a0/d; +v0x17650f0_0 .net "ALUout", 0 0, L_0x1824950; 1 drivers +v0x17651b0_0 .net "Cin", 0 0, L_0x1824bc0; 1 drivers +v0x1765270_0 .net "Cout", 0 0, L_0x181fbc0; 1 drivers +v0x1765340_0 .net *"_s11", 0 0, L_0x18202a0; 1 drivers +o0x7fc2cd91d168 .functor BUFZ 1, C4; HiZ drive +; Elide local net with no drivers, v0x17653e0_0 name=_s15 +o0x7fc2cd91d198 .functor BUFZ 3, C4; HiZ drive +; Elide local net with no drivers, v0x17654d0_0 name=_s17 +v0x17655b0_0 .net *"_s3", 0 0, L_0x181fd70; 1 drivers +v0x1765690_0 .net *"_s7", 0 0, L_0x1820030; 1 drivers +v0x1765770_0 .net "addr", 2 0, v0x17dbc90_0; alias, 1 drivers +v0x17658c0_0 .net "bit1", 0 0, L_0x1824cf0; 1 drivers +v0x1765960_0 .net "bit2", 0 0, L_0x181f670; 1 drivers +v0x1765a30_0 .net "invertB", 0 0, v0x17dbbc0_0; alias, 1 drivers +v0x1765ad0_0 .net "nanded", 0 0, L_0x181fed0; 1 drivers +v0x1765b70_0 .net "nored", 0 0, L_0x1820140; 1 drivers +v0x1765c10_0 .net "out", 7 0, L_0x1892e30; 1 drivers +LS_0x1892e30_0_0 .concat [ 1 1 1 1], L_0x181f7a0, L_0x181fd70, o0x7fc2cd91d168, L_0x1820030; +LS_0x1892e30_0_4 .concat [ 1 3 0 0], L_0x18202a0, o0x7fc2cd91d198; +L_0x1892e30 .concat [ 4 4 0 0], LS_0x1892e30_0_0, LS_0x1892e30_0_4; +S_0x175fc60 .scope module, "opmux" "structuralMultiplexer" 3 43, 4 21 0, S_0x175f9d0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 3 "address" + .port_info 2 /INPUT 8 "in" +v0x1764090_0 .net "address", 2 0, v0x17dbc90_0; alias, 1 drivers +v0x1764150_0 .net "in", 7 0, L_0x1892e30; alias, 1 drivers +v0x1764230_0 .net "mux", 3 0, L_0x18229c0; 1 drivers +v0x17642f0_0 .net "muxmid", 1 0, L_0x1823f80; 1 drivers +v0x17643b0_0 .net "out", 0 0, L_0x1824950; alias, 1 drivers +L_0x1820ba0 .part v0x17dbc90_0, 0, 1; +L_0x1820d00 .part L_0x1892e30, 0, 2; +L_0x18215e0 .part v0x17dbc90_0, 0, 1; +L_0x1821740 .part L_0x1892e30, 2, 2; +L_0x1821fb0 .part v0x17dbc90_0, 0, 1; +L_0x1822110 .part L_0x1892e30, 4, 2; +L_0x18229c0 .concat8 [ 1 1 1 1], L_0x1820a40, L_0x1821480, L_0x1821e50, L_0x1822860; +L_0x1822c60 .part v0x17dbc90_0, 0, 1; +L_0x1822d50 .part L_0x1892e30, 6, 2; +L_0x1823590 .part v0x17dbc90_0, 1, 1; +L_0x18236f0 .part L_0x18229c0, 0, 2; +L_0x1823f80 .concat8 [ 1 1 0 0], L_0x1823430, L_0x1823e20; +L_0x1824180 .part v0x17dbc90_0, 1, 1; +L_0x1824220 .part L_0x18229c0, 2, 2; +L_0x1824a60 .part v0x17dbc90_0, 2, 1; +S_0x175fed0 .scope module, "mux_0" "bitMultiplexer" 4 29, 4 8 0, S_0x175fc60; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "addr" + .port_info 2 /INPUT 2 "in" +L_0x18203b0/d .functor NOT 1, L_0x1820ba0, C4<0>, C4<0>, C4<0>; +L_0x18203b0 .delay 1 (10000,10000,10000) L_0x18203b0/d; +L_0x1820510/d .functor AND 1, L_0x1820620, L_0x18203b0, C4<1>, C4<1>; +L_0x1820510 .delay 1 (20000,20000,20000) L_0x1820510/d; +L_0x1820780/d .functor AND 1, L_0x1820890, L_0x1820ba0, C4<1>, C4<1>; +L_0x1820780 .delay 1 (20000,20000,20000) L_0x1820780/d; +L_0x1820a40/d .functor OR 1, L_0x1820510, L_0x1820780, C4<0>, C4<0>; +L_0x1820a40 .delay 1 (20000,20000,20000) L_0x1820a40/d; +v0x1760140_0 .net *"_s1", 0 0, L_0x1820620; 1 drivers +v0x1760240_0 .net *"_s3", 0 0, L_0x1820890; 1 drivers +v0x1760320_0 .net "addr", 0 0, L_0x1820ba0; 1 drivers +v0x17603f0_0 .net "in", 1 0, L_0x1820d00; 1 drivers +v0x17604d0_0 .net "naddr", 0 0, L_0x18203b0; 1 drivers +v0x17605e0_0 .net "o0", 0 0, L_0x1820510; 1 drivers +v0x17606a0_0 .net "o1", 0 0, L_0x1820780; 1 drivers +v0x1760760_0 .net "out", 0 0, L_0x1820a40; 1 drivers +L_0x1820620 .part L_0x1820d00, 0, 1; +L_0x1820890 .part L_0x1820d00, 1, 1; +S_0x17608a0 .scope module, "mux_1" "bitMultiplexer" 4 30, 4 8 0, S_0x175fc60; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "addr" + .port_info 2 /INPUT 2 "in" +L_0x1820da0/d .functor NOT 1, L_0x18215e0, C4<0>, C4<0>, C4<0>; +L_0x1820da0 .delay 1 (10000,10000,10000) L_0x1820da0/d; +L_0x1820e60/d .functor AND 1, L_0x1821060, L_0x1820da0, C4<1>, C4<1>; +L_0x1820e60 .delay 1 (20000,20000,20000) L_0x1820e60/d; +L_0x18211c0/d .functor AND 1, L_0x18212d0, L_0x18215e0, C4<1>, C4<1>; +L_0x18211c0 .delay 1 (20000,20000,20000) L_0x18211c0/d; +L_0x1821480/d .functor OR 1, L_0x1820e60, L_0x18211c0, C4<0>, C4<0>; +L_0x1821480 .delay 1 (20000,20000,20000) L_0x1821480/d; +v0x1760ad0_0 .net *"_s1", 0 0, L_0x1821060; 1 drivers +v0x1760bd0_0 .net *"_s3", 0 0, L_0x18212d0; 1 drivers +v0x1760cb0_0 .net "addr", 0 0, L_0x18215e0; 1 drivers +v0x1760d50_0 .net "in", 1 0, L_0x1821740; 1 drivers +v0x1760e30_0 .net "naddr", 0 0, L_0x1820da0; 1 drivers +v0x1760f40_0 .net "o0", 0 0, L_0x1820e60; 1 drivers +v0x1761000_0 .net "o1", 0 0, L_0x18211c0; 1 drivers +v0x17610c0_0 .net "out", 0 0, L_0x1821480; 1 drivers +L_0x1821060 .part L_0x1821740, 0, 1; +L_0x18212d0 .part L_0x1821740, 1, 1; +S_0x1761200 .scope module, "mux_2" "bitMultiplexer" 4 31, 4 8 0, S_0x175fc60; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "addr" + .port_info 2 /INPUT 2 "in" +L_0x1821680/d .functor NOT 1, L_0x1821fb0, C4<0>, C4<0>, C4<0>; +L_0x1821680 .delay 1 (10000,10000,10000) L_0x1821680/d; +L_0x1821830/d .functor AND 1, L_0x1821a30, L_0x1821680, C4<1>, C4<1>; +L_0x1821830 .delay 1 (20000,20000,20000) L_0x1821830/d; +L_0x1821b90/d .functor AND 1, L_0x1821ca0, L_0x1821fb0, C4<1>, C4<1>; +L_0x1821b90 .delay 1 (20000,20000,20000) L_0x1821b90/d; +L_0x1821e50/d .functor OR 1, L_0x1821830, L_0x1821b90, C4<0>, C4<0>; +L_0x1821e50 .delay 1 (20000,20000,20000) L_0x1821e50/d; +v0x1761430_0 .net *"_s1", 0 0, L_0x1821a30; 1 drivers +v0x1761510_0 .net *"_s3", 0 0, L_0x1821ca0; 1 drivers +v0x17615f0_0 .net "addr", 0 0, L_0x1821fb0; 1 drivers +v0x17616c0_0 .net "in", 1 0, L_0x1822110; 1 drivers +v0x17617a0_0 .net "naddr", 0 0, L_0x1821680; 1 drivers +v0x17618b0_0 .net "o0", 0 0, L_0x1821830; 1 drivers +v0x1761970_0 .net "o1", 0 0, L_0x1821b90; 1 drivers +v0x1761a30_0 .net "out", 0 0, L_0x1821e50; 1 drivers +L_0x1821a30 .part L_0x1822110, 0, 1; +L_0x1821ca0 .part L_0x1822110, 1, 1; +S_0x1761b70 .scope module, "mux_3" "bitMultiplexer" 4 32, 4 8 0, S_0x175fc60; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "addr" + .port_info 2 /INPUT 2 "in" +L_0x1822050/d .functor NOT 1, L_0x1822c60, C4<0>, C4<0>, C4<0>; +L_0x1822050 .delay 1 (10000,10000,10000) L_0x1822050/d; +L_0x1822240/d .functor AND 1, L_0x1822440, L_0x1822050, C4<1>, C4<1>; +L_0x1822240 .delay 1 (20000,20000,20000) L_0x1822240/d; +L_0x18225a0/d .functor AND 1, L_0x18226b0, L_0x1822c60, C4<1>, C4<1>; +L_0x18225a0 .delay 1 (20000,20000,20000) L_0x18225a0/d; +L_0x1822860/d .functor OR 1, L_0x1822240, L_0x18225a0, C4<0>, C4<0>; +L_0x1822860 .delay 1 (20000,20000,20000) L_0x1822860/d; +v0x1761da0_0 .net *"_s1", 0 0, L_0x1822440; 1 drivers +v0x1761ea0_0 .net *"_s3", 0 0, L_0x18226b0; 1 drivers +v0x1761f80_0 .net "addr", 0 0, L_0x1822c60; 1 drivers +v0x1762020_0 .net "in", 1 0, L_0x1822d50; 1 drivers +v0x17620c0_0 .net "naddr", 0 0, L_0x1822050; 1 drivers +v0x1762160_0 .net "o0", 0 0, L_0x1822240; 1 drivers +v0x1762220_0 .net "o1", 0 0, L_0x18225a0; 1 drivers +v0x17622e0_0 .net "out", 0 0, L_0x1822860; 1 drivers +L_0x1822440 .part L_0x1822d50, 0, 1; +L_0x18226b0 .part L_0x1822d50, 1, 1; +S_0x1762420 .scope module, "mux_mid_0" "bitMultiplexer" 4 33, 4 8 0, S_0x175fc60; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "addr" + .port_info 2 /INPUT 2 "in" +L_0x1822df0/d .functor NOT 1, L_0x1823590, C4<0>, C4<0>, C4<0>; +L_0x1822df0 .delay 1 (10000,10000,10000) L_0x1822df0/d; +L_0x1822eb0/d .functor AND 1, L_0x1823010, L_0x1822df0, C4<1>, C4<1>; +L_0x1822eb0 .delay 1 (20000,20000,20000) L_0x1822eb0/d; +L_0x1823170/d .functor AND 1, L_0x1823280, L_0x1823590, C4<1>, C4<1>; +L_0x1823170 .delay 1 (20000,20000,20000) L_0x1823170/d; +L_0x1823430/d .functor OR 1, L_0x1822eb0, L_0x1823170, C4<0>, C4<0>; +L_0x1823430 .delay 1 (20000,20000,20000) L_0x1823430/d; +v0x17626a0_0 .net *"_s1", 0 0, L_0x1823010; 1 drivers +v0x17627a0_0 .net *"_s3", 0 0, L_0x1823280; 1 drivers +v0x1762880_0 .net "addr", 0 0, L_0x1823590; 1 drivers +v0x1762920_0 .net "in", 1 0, L_0x18236f0; 1 drivers +v0x1762a00_0 .net "naddr", 0 0, L_0x1822df0; 1 drivers +v0x1762b10_0 .net "o0", 0 0, L_0x1822eb0; 1 drivers +v0x1762bd0_0 .net "o1", 0 0, L_0x1823170; 1 drivers +v0x1762c90_0 .net "out", 0 0, L_0x1823430; 1 drivers +L_0x1823010 .part L_0x18236f0, 0, 1; +L_0x1823280 .part L_0x18236f0, 1, 1; +S_0x1762dd0 .scope module, "mux_mid_1" "bitMultiplexer" 4 34, 4 8 0, S_0x175fc60; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "addr" + .port_info 2 /INPUT 2 "in" +L_0x1823790/d .functor NOT 1, L_0x1824180, C4<0>, C4<0>, C4<0>; +L_0x1823790 .delay 1 (10000,10000,10000) L_0x1823790/d; +L_0x1823850/d .functor AND 1, L_0x1823a00, L_0x1823790, C4<1>, C4<1>; +L_0x1823850 .delay 1 (20000,20000,20000) L_0x1823850/d; +L_0x1823b60/d .functor AND 1, L_0x1823c70, L_0x1824180, C4<1>, C4<1>; +L_0x1823b60 .delay 1 (20000,20000,20000) L_0x1823b60/d; +L_0x1823e20/d .functor OR 1, L_0x1823850, L_0x1823b60, C4<0>, C4<0>; +L_0x1823e20 .delay 1 (20000,20000,20000) L_0x1823e20/d; +v0x1763000_0 .net *"_s1", 0 0, L_0x1823a00; 1 drivers +v0x1763100_0 .net *"_s3", 0 0, L_0x1823c70; 1 drivers +v0x17631e0_0 .net "addr", 0 0, L_0x1824180; 1 drivers +v0x1763280_0 .net "in", 1 0, L_0x1824220; 1 drivers +v0x1763360_0 .net "naddr", 0 0, L_0x1823790; 1 drivers +v0x1763470_0 .net "o0", 0 0, L_0x1823850; 1 drivers +v0x1763530_0 .net "o1", 0 0, L_0x1823b60; 1 drivers +v0x17635f0_0 .net "out", 0 0, L_0x1823e20; 1 drivers +L_0x1823a00 .part L_0x1824220, 0, 1; +L_0x1823c70 .part L_0x1824220, 1, 1; +S_0x1763730 .scope module, "mux_out" "bitMultiplexer" 4 35, 4 8 0, S_0x175fc60; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "addr" + .port_info 2 /INPUT 2 "in" +L_0x1823630/d .functor NOT 1, L_0x1824a60, C4<0>, C4<0>, C4<0>; +L_0x1823630 .delay 1 (10000,10000,10000) L_0x1823630/d; +L_0x1824390/d .functor AND 1, L_0x18244f0, L_0x1823630, C4<1>, C4<1>; +L_0x1824390 .delay 1 (20000,20000,20000) L_0x1824390/d; +L_0x1824650/d .functor AND 1, L_0x1824760, L_0x1824a60, C4<1>, C4<1>; +L_0x1824650 .delay 1 (20000,20000,20000) L_0x1824650/d; +L_0x1824950/d .functor OR 1, L_0x1824390, L_0x1824650, C4<0>, C4<0>; +L_0x1824950 .delay 1 (20000,20000,20000) L_0x1824950/d; +v0x1763960_0 .net *"_s1", 0 0, L_0x18244f0; 1 drivers +v0x1763a60_0 .net *"_s3", 0 0, L_0x1824760; 1 drivers +v0x1763b40_0 .net "addr", 0 0, L_0x1824a60; 1 drivers +v0x1763be0_0 .net "in", 1 0, L_0x1823f80; alias, 1 drivers +v0x1763cc0_0 .net "naddr", 0 0, L_0x1823630; 1 drivers +v0x1763dd0_0 .net "o0", 0 0, L_0x1824390; 1 drivers +v0x1763e90_0 .net "o1", 0 0, L_0x1824650; 1 drivers +v0x1763f50_0 .net "out", 0 0, L_0x1824950; alias, 1 drivers +L_0x18244f0 .part L_0x1823f80, 0, 1; +L_0x1824760 .part L_0x1823f80, 1, 1; +S_0x17644e0 .scope module, "structadder" "structAddSub" 3 22, 5 8 0, S_0x175f9d0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "sub" + .port_info 5 /INPUT 1 "carryin" +L_0x181f1b0/d .functor XOR 1, L_0x181f670, v0x17dbbc0_0, C4<0>, C4<0>; +L_0x181f1b0 .delay 1 (20000,20000,20000) L_0x181f1b0/d; +L_0x181f3a0/d .functor XOR 1, L_0x1824cf0, L_0x181f670, C4<0>, C4<0>; +L_0x181f3a0 .delay 1 (20000,20000,20000) L_0x181f3a0/d; +L_0x181f7a0/d .functor XOR 1, L_0x181f3a0, L_0x1824bc0, C4<0>, C4<0>; +L_0x181f7a0 .delay 1 (20000,20000,20000) L_0x181f7a0/d; +L_0x181f900/d .functor AND 1, L_0x1824cf0, L_0x181f670, C4<1>, C4<1>; +L_0x181f900 .delay 1 (20000,20000,20000) L_0x181f900/d; +L_0x181fa60/d .functor AND 1, L_0x181f3a0, L_0x1824bc0, C4<1>, C4<1>; +L_0x181fa60 .delay 1 (20000,20000,20000) L_0x181fa60/d; +L_0x181fbc0/d .functor OR 1, L_0x181fa60, L_0x181f900, C4<0>, C4<0>; +L_0x181fbc0 .delay 1 (20000,20000,20000) L_0x181fbc0/d; +v0x17647a0_0 .net "AandB", 0 0, L_0x181f900; 1 drivers +v0x1764860_0 .net "AxorB", 0 0, L_0x181f3a0; 1 drivers +v0x1764920_0 .net "AxorBandCarryIn", 0 0, L_0x181fa60; 1 drivers +v0x17649f0_0 .net "a", 0 0, L_0x1824cf0; alias, 1 drivers +v0x1764ab0_0 .net "b", 0 0, L_0x181f670; alias, 1 drivers +v0x1764bc0_0 .net "bnew", 0 0, L_0x181f1b0; 1 drivers +v0x1764c80_0 .net "carryin", 0 0, L_0x1824bc0; alias, 1 drivers +v0x1764d40_0 .net "carryout", 0 0, L_0x181fbc0; alias, 1 drivers +v0x1764e00_0 .net "sub", 0 0, v0x17dbbc0_0; alias, 1 drivers +v0x1764f30_0 .net "sum", 0 0, L_0x181f7a0; 1 drivers +S_0x1765dc0 .scope generate, "ripple[14]" "ripple[14]" 3 66, 3 66 0, S_0x16fa6c0; + .timescale -9 -12; +P_0x1765f90 .param/l "i" 0 3 66, +C4<01110>; +S_0x1766050 .scope module, "bit" "BitSliceALU" 3 68, 3 11 0, S_0x1765dc0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "ALUout" + .port_info 1 /OUTPUT 1 "Cout" + .port_info 2 /INPUT 1 "invertB" + .port_info 3 /INPUT 1 "Cin" + .port_info 4 /INPUT 3 "addr" + .port_info 5 /INPUT 1 "bit1" + .port_info 6 /INPUT 1 "bit2" +L_0x18256c0/d .functor XOR 1, L_0x1824d90, L_0x1824e30, C4<0>, C4<0>; +L_0x18256c0 .delay 1 (20000,20000,20000) L_0x18256c0/d; +L_0x1825820/d .functor NAND 1, L_0x1824d90, L_0x1824e30, C4<1>, C4<1>; +L_0x1825820 .delay 1 (10000,10000,10000) L_0x1825820/d; +L_0x1825980/d .functor XOR 1, v0x17dbbc0_0, L_0x1825820, C4<0>, C4<0>; +L_0x1825980 .delay 1 (20000,20000,20000) L_0x1825980/d; +L_0x1825a90/d .functor NOR 1, L_0x1824d90, L_0x1824e30, C4<0>, C4<0>; +L_0x1825a90 .delay 1 (10000,10000,10000) L_0x1825a90/d; +L_0x1825bf0/d .functor XOR 1, v0x17dbbc0_0, L_0x1825a90, C4<0>, C4<0>; +L_0x1825bf0 .delay 1 (20000,20000,20000) L_0x1825bf0/d; +v0x176b820_0 .net "ALUout", 0 0, L_0x182a220; 1 drivers +v0x176b8e0_0 .net "Cin", 0 0, L_0x182a490; 1 drivers +v0x176b9a0_0 .net "Cout", 0 0, L_0x1825510; 1 drivers +v0x176ba70_0 .net *"_s11", 0 0, L_0x1825bf0; 1 drivers +o0x7fc2cd91e638 .functor BUFZ 1, C4; HiZ drive +; Elide local net with no drivers, v0x176bb10_0 name=_s15 +o0x7fc2cd91e668 .functor BUFZ 3, C4; HiZ drive +; Elide local net with no drivers, v0x176bc00_0 name=_s17 +v0x176bce0_0 .net *"_s3", 0 0, L_0x18256c0; 1 drivers +v0x176bdc0_0 .net *"_s7", 0 0, L_0x1825980; 1 drivers +v0x176bea0_0 .net "addr", 2 0, v0x17dbc90_0; alias, 1 drivers +v0x176bff0_0 .net "bit1", 0 0, L_0x1824d90; 1 drivers +v0x176c090_0 .net "bit2", 0 0, L_0x1824e30; 1 drivers +v0x176c160_0 .net "invertB", 0 0, v0x17dbbc0_0; alias, 1 drivers +v0x176c200_0 .net "nanded", 0 0, L_0x1825820; 1 drivers +v0x176c2a0_0 .net "nored", 0 0, L_0x1825a90; 1 drivers +v0x176c340_0 .net "out", 7 0, L_0x1893010; 1 drivers +LS_0x1893010_0_0 .concat [ 1 1 1 1], L_0x18250a0, L_0x18256c0, o0x7fc2cd91e638, L_0x1825980; +LS_0x1893010_0_4 .concat [ 1 3 0 0], L_0x1825bf0, o0x7fc2cd91e668; +L_0x1893010 .concat [ 4 4 0 0], LS_0x1893010_0_0, LS_0x1893010_0_4; +S_0x17662e0 .scope module, "opmux" "structuralMultiplexer" 3 43, 4 21 0, S_0x1766050; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 3 "address" + .port_info 2 /INPUT 8 "in" +v0x176a7c0_0 .net "address", 2 0, v0x17dbc90_0; alias, 1 drivers +v0x176a880_0 .net "in", 7 0, L_0x1893010; alias, 1 drivers +v0x176a960_0 .net "mux", 3 0, L_0x1828330; 1 drivers +v0x176aa20_0 .net "muxmid", 1 0, L_0x1829850; 1 drivers +v0x176aae0_0 .net "out", 0 0, L_0x182a220; alias, 1 drivers +L_0x1826550 .part v0x17dbc90_0, 0, 1; +L_0x18266b0 .part L_0x1893010, 0, 2; +L_0x1826f70 .part v0x17dbc90_0, 0, 1; +L_0x18270d0 .part L_0x1893010, 2, 2; +L_0x1827940 .part v0x17dbc90_0, 0, 1; +L_0x1827aa0 .part L_0x1893010, 4, 2; +L_0x1828330 .concat8 [ 1 1 1 1], L_0x18263f0, L_0x1826e10, L_0x18277e0, L_0x18281d0; +L_0x1828580 .part v0x17dbc90_0, 0, 1; +L_0x1828670 .part L_0x1893010, 6, 2; +L_0x1828eb0 .part v0x17dbc90_0, 1, 1; +L_0x1829010 .part L_0x1828330, 0, 2; +L_0x1829850 .concat8 [ 1 1 0 0], L_0x1828d50, L_0x18296f0; +L_0x1829a50 .part v0x17dbc90_0, 1, 1; +L_0x1829af0 .part L_0x1828330, 2, 2; +L_0x182a330 .part v0x17dbc90_0, 2, 1; +S_0x1766550 .scope module, "mux_0" "bitMultiplexer" 4 29, 4 8 0, S_0x17662e0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "addr" + .port_info 2 /INPUT 2 "in" +L_0x1825d00/d .functor NOT 1, L_0x1826550, C4<0>, C4<0>, C4<0>; +L_0x1825d00 .delay 1 (10000,10000,10000) L_0x1825d00/d; +L_0x1825e60/d .functor AND 1, L_0x1825f70, L_0x1825d00, C4<1>, C4<1>; +L_0x1825e60 .delay 1 (20000,20000,20000) L_0x1825e60/d; +L_0x18260d0/d .functor AND 1, L_0x1826240, L_0x1826550, C4<1>, C4<1>; +L_0x18260d0 .delay 1 (20000,20000,20000) L_0x18260d0/d; +L_0x18263f0/d .functor OR 1, L_0x1825e60, L_0x18260d0, C4<0>, C4<0>; +L_0x18263f0 .delay 1 (20000,20000,20000) L_0x18263f0/d; +v0x17667c0_0 .net *"_s1", 0 0, L_0x1825f70; 1 drivers +v0x17668c0_0 .net *"_s3", 0 0, L_0x1826240; 1 drivers +v0x17669a0_0 .net "addr", 0 0, L_0x1826550; 1 drivers +v0x1766a70_0 .net "in", 1 0, L_0x18266b0; 1 drivers +v0x1766b50_0 .net "naddr", 0 0, L_0x1825d00; 1 drivers +v0x1766c60_0 .net "o0", 0 0, L_0x1825e60; 1 drivers +v0x1766d20_0 .net "o1", 0 0, L_0x18260d0; 1 drivers +v0x1766de0_0 .net "out", 0 0, L_0x18263f0; 1 drivers +L_0x1825f70 .part L_0x18266b0, 0, 1; +L_0x1826240 .part L_0x18266b0, 1, 1; +S_0x1766f20 .scope module, "mux_1" "bitMultiplexer" 4 30, 4 8 0, S_0x17662e0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "addr" + .port_info 2 /INPUT 2 "in" +L_0x1826750/d .functor NOT 1, L_0x1826f70, C4<0>, C4<0>, C4<0>; +L_0x1826750 .delay 1 (10000,10000,10000) L_0x1826750/d; +L_0x1826810/d .functor AND 1, L_0x18269c0, L_0x1826750, C4<1>, C4<1>; +L_0x1826810 .delay 1 (20000,20000,20000) L_0x1826810/d; +L_0x1826b20/d .functor AND 1, L_0x1826c60, L_0x1826f70, C4<1>, C4<1>; +L_0x1826b20 .delay 1 (20000,20000,20000) L_0x1826b20/d; +L_0x1826e10/d .functor OR 1, L_0x1826810, L_0x1826b20, C4<0>, C4<0>; +L_0x1826e10 .delay 1 (20000,20000,20000) L_0x1826e10/d; +v0x1767150_0 .net *"_s1", 0 0, L_0x18269c0; 1 drivers +v0x1767250_0 .net *"_s3", 0 0, L_0x1826c60; 1 drivers +v0x1767330_0 .net "addr", 0 0, L_0x1826f70; 1 drivers +v0x17673d0_0 .net "in", 1 0, L_0x18270d0; 1 drivers +v0x17674b0_0 .net "naddr", 0 0, L_0x1826750; 1 drivers +v0x17675c0_0 .net "o0", 0 0, L_0x1826810; 1 drivers +v0x1767680_0 .net "o1", 0 0, L_0x1826b20; 1 drivers +v0x1767740_0 .net "out", 0 0, L_0x1826e10; 1 drivers +L_0x18269c0 .part L_0x18270d0, 0, 1; +L_0x1826c60 .part L_0x18270d0, 1, 1; +S_0x1767880 .scope module, "mux_2" "bitMultiplexer" 4 31, 4 8 0, S_0x17662e0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "addr" + .port_info 2 /INPUT 2 "in" +L_0x1827010/d .functor NOT 1, L_0x1827940, C4<0>, C4<0>, C4<0>; +L_0x1827010 .delay 1 (10000,10000,10000) L_0x1827010/d; +L_0x18271c0/d .functor AND 1, L_0x18273c0, L_0x1827010, C4<1>, C4<1>; +L_0x18271c0 .delay 1 (20000,20000,20000) L_0x18271c0/d; +L_0x1827520/d .functor AND 1, L_0x1827630, L_0x1827940, C4<1>, C4<1>; +L_0x1827520 .delay 1 (20000,20000,20000) L_0x1827520/d; +L_0x18277e0/d .functor OR 1, L_0x18271c0, L_0x1827520, C4<0>, C4<0>; +L_0x18277e0 .delay 1 (20000,20000,20000) L_0x18277e0/d; +v0x1767ab0_0 .net *"_s1", 0 0, L_0x18273c0; 1 drivers +v0x1767b90_0 .net *"_s3", 0 0, L_0x1827630; 1 drivers +v0x1767c70_0 .net "addr", 0 0, L_0x1827940; 1 drivers +v0x1767d40_0 .net "in", 1 0, L_0x1827aa0; 1 drivers +v0x1767e20_0 .net "naddr", 0 0, L_0x1827010; 1 drivers +v0x1767f30_0 .net "o0", 0 0, L_0x18271c0; 1 drivers +v0x1767ff0_0 .net "o1", 0 0, L_0x1827520; 1 drivers +v0x17680b0_0 .net "out", 0 0, L_0x18277e0; 1 drivers +L_0x18273c0 .part L_0x1827aa0, 0, 1; +L_0x1827630 .part L_0x1827aa0, 1, 1; +S_0x17681f0 .scope module, "mux_3" "bitMultiplexer" 4 32, 4 8 0, S_0x17662e0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "addr" + .port_info 2 /INPUT 2 "in" +L_0x18279e0/d .functor NOT 1, L_0x1828580, C4<0>, C4<0>, C4<0>; +L_0x18279e0 .delay 1 (10000,10000,10000) L_0x18279e0/d; +L_0x1827bd0/d .functor AND 1, L_0x1827d80, L_0x18279e0, C4<1>, C4<1>; +L_0x1827bd0 .delay 1 (20000,20000,20000) L_0x1827bd0/d; +L_0x1827ee0/d .functor AND 1, L_0x1828020, L_0x1828580, C4<1>, C4<1>; +L_0x1827ee0 .delay 1 (20000,20000,20000) L_0x1827ee0/d; +L_0x18281d0/d .functor OR 1, L_0x1827bd0, L_0x1827ee0, C4<0>, C4<0>; +L_0x18281d0 .delay 1 (20000,20000,20000) L_0x18281d0/d; +v0x1768420_0 .net *"_s1", 0 0, L_0x1827d80; 1 drivers +v0x1768520_0 .net *"_s3", 0 0, L_0x1828020; 1 drivers +v0x1768600_0 .net "addr", 0 0, L_0x1828580; 1 drivers +v0x17686a0_0 .net "in", 1 0, L_0x1828670; 1 drivers +v0x1768780_0 .net "naddr", 0 0, L_0x18279e0; 1 drivers +v0x1768890_0 .net "o0", 0 0, L_0x1827bd0; 1 drivers +v0x1768950_0 .net "o1", 0 0, L_0x1827ee0; 1 drivers +v0x1768a10_0 .net "out", 0 0, L_0x18281d0; 1 drivers +L_0x1827d80 .part L_0x1828670, 0, 1; +L_0x1828020 .part L_0x1828670, 1, 1; +S_0x1768b50 .scope module, "mux_mid_0" "bitMultiplexer" 4 33, 4 8 0, S_0x17662e0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "addr" + .port_info 2 /INPUT 2 "in" +L_0x1828710/d .functor NOT 1, L_0x1828eb0, C4<0>, C4<0>, C4<0>; +L_0x1828710 .delay 1 (10000,10000,10000) L_0x1828710/d; +L_0x18287d0/d .functor AND 1, L_0x1828930, L_0x1828710, C4<1>, C4<1>; +L_0x18287d0 .delay 1 (20000,20000,20000) L_0x18287d0/d; +L_0x1828a90/d .functor AND 1, L_0x1828ba0, L_0x1828eb0, C4<1>, C4<1>; +L_0x1828a90 .delay 1 (20000,20000,20000) L_0x1828a90/d; +L_0x1828d50/d .functor OR 1, L_0x18287d0, L_0x1828a90, C4<0>, C4<0>; +L_0x1828d50 .delay 1 (20000,20000,20000) L_0x1828d50/d; +v0x1768dd0_0 .net *"_s1", 0 0, L_0x1828930; 1 drivers +v0x1768ed0_0 .net *"_s3", 0 0, L_0x1828ba0; 1 drivers +v0x1768fb0_0 .net "addr", 0 0, L_0x1828eb0; 1 drivers +v0x1769050_0 .net "in", 1 0, L_0x1829010; 1 drivers +v0x1769130_0 .net "naddr", 0 0, L_0x1828710; 1 drivers +v0x1769240_0 .net "o0", 0 0, L_0x18287d0; 1 drivers +v0x1769300_0 .net "o1", 0 0, L_0x1828a90; 1 drivers +v0x17693c0_0 .net "out", 0 0, L_0x1828d50; 1 drivers +L_0x1828930 .part L_0x1829010, 0, 1; +L_0x1828ba0 .part L_0x1829010, 1, 1; +S_0x1769500 .scope module, "mux_mid_1" "bitMultiplexer" 4 34, 4 8 0, S_0x17662e0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "addr" + .port_info 2 /INPUT 2 "in" +L_0x18290b0/d .functor NOT 1, L_0x1829a50, C4<0>, C4<0>, C4<0>; +L_0x18290b0 .delay 1 (10000,10000,10000) L_0x18290b0/d; +L_0x1829170/d .functor AND 1, L_0x18292d0, L_0x18290b0, C4<1>, C4<1>; +L_0x1829170 .delay 1 (20000,20000,20000) L_0x1829170/d; +L_0x1829430/d .functor AND 1, L_0x1829540, L_0x1829a50, C4<1>, C4<1>; +L_0x1829430 .delay 1 (20000,20000,20000) L_0x1829430/d; +L_0x18296f0/d .functor OR 1, L_0x1829170, L_0x1829430, C4<0>, C4<0>; +L_0x18296f0 .delay 1 (20000,20000,20000) L_0x18296f0/d; +v0x1769730_0 .net *"_s1", 0 0, L_0x18292d0; 1 drivers +v0x1769830_0 .net *"_s3", 0 0, L_0x1829540; 1 drivers +v0x1769910_0 .net "addr", 0 0, L_0x1829a50; 1 drivers +v0x17699b0_0 .net "in", 1 0, L_0x1829af0; 1 drivers +v0x1769a90_0 .net "naddr", 0 0, L_0x18290b0; 1 drivers +v0x1769ba0_0 .net "o0", 0 0, L_0x1829170; 1 drivers +v0x1769c60_0 .net "o1", 0 0, L_0x1829430; 1 drivers +v0x1769d20_0 .net "out", 0 0, L_0x18296f0; 1 drivers +L_0x18292d0 .part L_0x1829af0, 0, 1; +L_0x1829540 .part L_0x1829af0, 1, 1; +S_0x1769e60 .scope module, "mux_out" "bitMultiplexer" 4 35, 4 8 0, S_0x17662e0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "addr" + .port_info 2 /INPUT 2 "in" +L_0x1828f50/d .functor NOT 1, L_0x182a330, C4<0>, C4<0>, C4<0>; +L_0x1828f50 .delay 1 (10000,10000,10000) L_0x1828f50/d; +L_0x1829c60/d .functor AND 1, L_0x1829dc0, L_0x1828f50, C4<1>, C4<1>; +L_0x1829c60 .delay 1 (20000,20000,20000) L_0x1829c60/d; +L_0x1829f20/d .functor AND 1, L_0x182a030, L_0x182a330, C4<1>, C4<1>; +L_0x1829f20 .delay 1 (20000,20000,20000) L_0x1829f20/d; +L_0x182a220/d .functor OR 1, L_0x1829c60, L_0x1829f20, C4<0>, C4<0>; +L_0x182a220 .delay 1 (20000,20000,20000) L_0x182a220/d; +v0x176a090_0 .net *"_s1", 0 0, L_0x1829dc0; 1 drivers +v0x176a190_0 .net *"_s3", 0 0, L_0x182a030; 1 drivers +v0x176a270_0 .net "addr", 0 0, L_0x182a330; 1 drivers +v0x176a310_0 .net "in", 1 0, L_0x1829850; alias, 1 drivers +v0x176a3f0_0 .net "naddr", 0 0, L_0x1828f50; 1 drivers +v0x176a500_0 .net "o0", 0 0, L_0x1829c60; 1 drivers +v0x176a5c0_0 .net "o1", 0 0, L_0x1829f20; 1 drivers +v0x176a680_0 .net "out", 0 0, L_0x182a220; alias, 1 drivers +L_0x1829dc0 .part L_0x1829850, 0, 1; +L_0x182a030 .part L_0x1829850, 1, 1; +S_0x176ac10 .scope module, "structadder" "structAddSub" 3 22, 5 8 0, S_0x1766050; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "sub" + .port_info 5 /INPUT 1 "carryin" +L_0x1824b00/d .functor XOR 1, L_0x1824e30, v0x17dbbc0_0, C4<0>, C4<0>; +L_0x1824b00 .delay 1 (20000,20000,20000) L_0x1824b00/d; +L_0x1824fe0/d .functor XOR 1, L_0x1824d90, L_0x1824e30, C4<0>, C4<0>; +L_0x1824fe0 .delay 1 (20000,20000,20000) L_0x1824fe0/d; +L_0x18250a0/d .functor XOR 1, L_0x1824fe0, L_0x182a490, C4<0>, C4<0>; +L_0x18250a0 .delay 1 (20000,20000,20000) L_0x18250a0/d; +L_0x1825250/d .functor AND 1, L_0x1824d90, L_0x1824e30, C4<1>, C4<1>; +L_0x1825250 .delay 1 (20000,20000,20000) L_0x1825250/d; +L_0x18253b0/d .functor AND 1, L_0x1824fe0, L_0x182a490, C4<1>, C4<1>; +L_0x18253b0 .delay 1 (20000,20000,20000) L_0x18253b0/d; +L_0x1825510/d .functor OR 1, L_0x18253b0, L_0x1825250, C4<0>, C4<0>; +L_0x1825510 .delay 1 (20000,20000,20000) L_0x1825510/d; +v0x176aed0_0 .net "AandB", 0 0, L_0x1825250; 1 drivers +v0x176af90_0 .net "AxorB", 0 0, L_0x1824fe0; 1 drivers +v0x176b050_0 .net "AxorBandCarryIn", 0 0, L_0x18253b0; 1 drivers +v0x176b120_0 .net "a", 0 0, L_0x1824d90; alias, 1 drivers +v0x176b1e0_0 .net "b", 0 0, L_0x1824e30; alias, 1 drivers +v0x176b2f0_0 .net "bnew", 0 0, L_0x1824b00; 1 drivers +v0x176b3b0_0 .net "carryin", 0 0, L_0x182a490; alias, 1 drivers +v0x176b470_0 .net "carryout", 0 0, L_0x1825510; alias, 1 drivers +v0x176b530_0 .net "sub", 0 0, v0x17dbbc0_0; alias, 1 drivers +v0x176b660_0 .net "sum", 0 0, L_0x18250a0; 1 drivers +S_0x176c4f0 .scope generate, "ripple[15]" "ripple[15]" 3 66, 3 66 0, S_0x16fa6c0; + .timescale -9 -12; +P_0x176c6c0 .param/l "i" 0 3 66, +C4<01111>; +S_0x176c780 .scope module, "bit" "BitSliceALU" 3 68, 3 11 0, S_0x176c4f0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "ALUout" + .port_info 1 /OUTPUT 1 "Cout" + .port_info 2 /INPUT 1 "invertB" + .port_info 3 /INPUT 1 "Cin" + .port_info 4 /INPUT 3 "addr" + .port_info 5 /INPUT 1 "bit1" + .port_info 6 /INPUT 1 "bit2" +L_0x182afa0/d .functor XOR 1, L_0x182feb0, L_0x1802ec0, C4<0>, C4<0>; +L_0x182afa0 .delay 1 (20000,20000,20000) L_0x182afa0/d; +L_0x182b100/d .functor NAND 1, L_0x182feb0, L_0x1802ec0, C4<1>, C4<1>; +L_0x182b100 .delay 1 (10000,10000,10000) L_0x182b100/d; +L_0x1827230/d .functor XOR 1, v0x17dbbc0_0, L_0x182b100, C4<0>, C4<0>; +L_0x1827230 .delay 1 (20000,20000,20000) L_0x1827230/d; +L_0x182b300/d .functor NOR 1, L_0x182feb0, L_0x1802ec0, C4<0>, C4<0>; +L_0x182b300 .delay 1 (10000,10000,10000) L_0x182b300/d; +L_0x182b460/d .functor XOR 1, v0x17dbbc0_0, L_0x182b300, C4<0>, C4<0>; +L_0x182b460 .delay 1 (20000,20000,20000) L_0x182b460/d; +v0x1771f50_0 .net "ALUout", 0 0, L_0x182fb10; 1 drivers +v0x1772010_0 .net "Cin", 0 0, L_0x182fd80; 1 drivers +v0x17720d0_0 .net "Cout", 0 0, L_0x182adf0; 1 drivers +v0x17721a0_0 .net *"_s11", 0 0, L_0x182b460; 1 drivers +o0x7fc2cd91fb08 .functor BUFZ 1, C4; HiZ drive +; Elide local net with no drivers, v0x1772240_0 name=_s15 +o0x7fc2cd91fb38 .functor BUFZ 3, C4; HiZ drive +; Elide local net with no drivers, v0x1772330_0 name=_s17 +v0x1772410_0 .net *"_s3", 0 0, L_0x182afa0; 1 drivers +v0x17724f0_0 .net *"_s7", 0 0, L_0x1827230; 1 drivers +v0x17725d0_0 .net "addr", 2 0, v0x17dbc90_0; alias, 1 drivers +v0x1772720_0 .net "bit1", 0 0, L_0x182feb0; 1 drivers +v0x17727c0_0 .net "bit2", 0 0, L_0x1802ec0; 1 drivers +v0x1772890_0 .net "invertB", 0 0, v0x17dbbc0_0; alias, 1 drivers +v0x1772930_0 .net "nanded", 0 0, L_0x182b100; 1 drivers +v0x17729d0_0 .net "nored", 0 0, L_0x182b300; 1 drivers +v0x1772a70_0 .net "out", 7 0, L_0x18931f0; 1 drivers +LS_0x18931f0_0_0 .concat [ 1 1 1 1], L_0x182a980, L_0x182afa0, o0x7fc2cd91fb08, L_0x1827230; +LS_0x18931f0_0_4 .concat [ 1 3 0 0], L_0x182b460, o0x7fc2cd91fb38; +L_0x18931f0 .concat [ 4 4 0 0], LS_0x18931f0_0_0, LS_0x18931f0_0_4; +S_0x176ca10 .scope module, "opmux" "structuralMultiplexer" 3 43, 4 21 0, S_0x176c780; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 3 "address" + .port_info 2 /INPUT 8 "in" +v0x1770ef0_0 .net "address", 2 0, v0x17dbc90_0; alias, 1 drivers +v0x1770fb0_0 .net "in", 7 0, L_0x18931f0; alias, 1 drivers +v0x1771090_0 .net "mux", 3 0, L_0x182db80; 1 drivers +v0x1771150_0 .net "muxmid", 1 0, L_0x182f140; 1 drivers +v0x1771210_0 .net "out", 0 0, L_0x182fb10; alias, 1 drivers +L_0x182bd60 .part v0x17dbc90_0, 0, 1; +L_0x182bec0 .part L_0x18931f0, 0, 2; +L_0x182c7a0 .part v0x17dbc90_0, 0, 1; +L_0x182c900 .part L_0x18931f0, 2, 2; +L_0x182d170 .part v0x17dbc90_0, 0, 1; +L_0x182d2d0 .part L_0x18931f0, 4, 2; +L_0x182db80 .concat8 [ 1 1 1 1], L_0x182bc00, L_0x182c640, L_0x182d010, L_0x182da20; +L_0x182de20 .part v0x17dbc90_0, 0, 1; +L_0x182df10 .part L_0x18931f0, 6, 2; +L_0x182e750 .part v0x17dbc90_0, 1, 1; +L_0x182e8b0 .part L_0x182db80, 0, 2; +L_0x182f140 .concat8 [ 1 1 0 0], L_0x182e5f0, L_0x182efe0; +L_0x182f340 .part v0x17dbc90_0, 1, 1; +L_0x182f3e0 .part L_0x182db80, 2, 2; +L_0x182fc20 .part v0x17dbc90_0, 2, 1; +S_0x176cc80 .scope module, "mux_0" "bitMultiplexer" 4 29, 4 8 0, S_0x176ca10; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "addr" + .port_info 2 /INPUT 2 "in" +L_0x182b570/d .functor NOT 1, L_0x182bd60, C4<0>, C4<0>, C4<0>; +L_0x182b570 .delay 1 (10000,10000,10000) L_0x182b570/d; +L_0x182b6d0/d .functor AND 1, L_0x182b7e0, L_0x182b570, C4<1>, C4<1>; +L_0x182b6d0 .delay 1 (20000,20000,20000) L_0x182b6d0/d; +L_0x182b940/d .functor AND 1, L_0x182ba50, L_0x182bd60, C4<1>, C4<1>; +L_0x182b940 .delay 1 (20000,20000,20000) L_0x182b940/d; +L_0x182bc00/d .functor OR 1, L_0x182b6d0, L_0x182b940, C4<0>, C4<0>; +L_0x182bc00 .delay 1 (20000,20000,20000) L_0x182bc00/d; +v0x176cef0_0 .net *"_s1", 0 0, L_0x182b7e0; 1 drivers +v0x176cff0_0 .net *"_s3", 0 0, L_0x182ba50; 1 drivers +v0x176d0d0_0 .net "addr", 0 0, L_0x182bd60; 1 drivers +v0x176d1a0_0 .net "in", 1 0, L_0x182bec0; 1 drivers +v0x176d280_0 .net "naddr", 0 0, L_0x182b570; 1 drivers +v0x176d390_0 .net "o0", 0 0, L_0x182b6d0; 1 drivers +v0x176d450_0 .net "o1", 0 0, L_0x182b940; 1 drivers +v0x176d510_0 .net "out", 0 0, L_0x182bc00; 1 drivers +L_0x182b7e0 .part L_0x182bec0, 0, 1; +L_0x182ba50 .part L_0x182bec0, 1, 1; +S_0x176d650 .scope module, "mux_1" "bitMultiplexer" 4 30, 4 8 0, S_0x176ca10; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "addr" + .port_info 2 /INPUT 2 "in" +L_0x182bf60/d .functor NOT 1, L_0x182c7a0, C4<0>, C4<0>, C4<0>; +L_0x182bf60 .delay 1 (10000,10000,10000) L_0x182bf60/d; +L_0x182c020/d .functor AND 1, L_0x182c220, L_0x182bf60, C4<1>, C4<1>; +L_0x182c020 .delay 1 (20000,20000,20000) L_0x182c020/d; +L_0x182c380/d .functor AND 1, L_0x182c490, L_0x182c7a0, C4<1>, C4<1>; +L_0x182c380 .delay 1 (20000,20000,20000) L_0x182c380/d; +L_0x182c640/d .functor OR 1, L_0x182c020, L_0x182c380, C4<0>, C4<0>; +L_0x182c640 .delay 1 (20000,20000,20000) L_0x182c640/d; +v0x176d880_0 .net *"_s1", 0 0, L_0x182c220; 1 drivers +v0x176d980_0 .net *"_s3", 0 0, L_0x182c490; 1 drivers +v0x176da60_0 .net "addr", 0 0, L_0x182c7a0; 1 drivers +v0x176db00_0 .net "in", 1 0, L_0x182c900; 1 drivers +v0x176dbe0_0 .net "naddr", 0 0, L_0x182bf60; 1 drivers +v0x176dcf0_0 .net "o0", 0 0, L_0x182c020; 1 drivers +v0x176ddb0_0 .net "o1", 0 0, L_0x182c380; 1 drivers +v0x176de70_0 .net "out", 0 0, L_0x182c640; 1 drivers +L_0x182c220 .part L_0x182c900, 0, 1; +L_0x182c490 .part L_0x182c900, 1, 1; +S_0x176dfb0 .scope module, "mux_2" "bitMultiplexer" 4 31, 4 8 0, S_0x176ca10; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "addr" + .port_info 2 /INPUT 2 "in" +L_0x182c840/d .functor NOT 1, L_0x182d170, C4<0>, C4<0>, C4<0>; +L_0x182c840 .delay 1 (10000,10000,10000) L_0x182c840/d; +L_0x182c9f0/d .functor AND 1, L_0x182cbf0, L_0x182c840, C4<1>, C4<1>; +L_0x182c9f0 .delay 1 (20000,20000,20000) L_0x182c9f0/d; +L_0x182cd50/d .functor AND 1, L_0x182ce60, L_0x182d170, C4<1>, C4<1>; +L_0x182cd50 .delay 1 (20000,20000,20000) L_0x182cd50/d; +L_0x182d010/d .functor OR 1, L_0x182c9f0, L_0x182cd50, C4<0>, C4<0>; +L_0x182d010 .delay 1 (20000,20000,20000) L_0x182d010/d; +v0x176e1e0_0 .net *"_s1", 0 0, L_0x182cbf0; 1 drivers +v0x176e2c0_0 .net *"_s3", 0 0, L_0x182ce60; 1 drivers +v0x176e3a0_0 .net "addr", 0 0, L_0x182d170; 1 drivers +v0x176e470_0 .net "in", 1 0, L_0x182d2d0; 1 drivers +v0x176e550_0 .net "naddr", 0 0, L_0x182c840; 1 drivers +v0x176e660_0 .net "o0", 0 0, L_0x182c9f0; 1 drivers +v0x176e720_0 .net "o1", 0 0, L_0x182cd50; 1 drivers +v0x176e7e0_0 .net "out", 0 0, L_0x182d010; 1 drivers +L_0x182cbf0 .part L_0x182d2d0, 0, 1; +L_0x182ce60 .part L_0x182d2d0, 1, 1; +S_0x176e920 .scope module, "mux_3" "bitMultiplexer" 4 32, 4 8 0, S_0x176ca10; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "addr" + .port_info 2 /INPUT 2 "in" +L_0x182d210/d .functor NOT 1, L_0x182de20, C4<0>, C4<0>, C4<0>; +L_0x182d210 .delay 1 (10000,10000,10000) L_0x182d210/d; +L_0x182d400/d .functor AND 1, L_0x182d600, L_0x182d210, C4<1>, C4<1>; +L_0x182d400 .delay 1 (20000,20000,20000) L_0x182d400/d; +L_0x182d760/d .functor AND 1, L_0x182d870, L_0x182de20, C4<1>, C4<1>; +L_0x182d760 .delay 1 (20000,20000,20000) L_0x182d760/d; +L_0x182da20/d .functor OR 1, L_0x182d400, L_0x182d760, C4<0>, C4<0>; +L_0x182da20 .delay 1 (20000,20000,20000) L_0x182da20/d; +v0x176eb50_0 .net *"_s1", 0 0, L_0x182d600; 1 drivers +v0x176ec50_0 .net *"_s3", 0 0, L_0x182d870; 1 drivers +v0x176ed30_0 .net "addr", 0 0, L_0x182de20; 1 drivers +v0x176edd0_0 .net "in", 1 0, L_0x182df10; 1 drivers +v0x176eeb0_0 .net "naddr", 0 0, L_0x182d210; 1 drivers +v0x176efc0_0 .net "o0", 0 0, L_0x182d400; 1 drivers +v0x176f080_0 .net "o1", 0 0, L_0x182d760; 1 drivers +v0x176f140_0 .net "out", 0 0, L_0x182da20; 1 drivers +L_0x182d600 .part L_0x182df10, 0, 1; +L_0x182d870 .part L_0x182df10, 1, 1; +S_0x176f280 .scope module, "mux_mid_0" "bitMultiplexer" 4 33, 4 8 0, S_0x176ca10; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "addr" + .port_info 2 /INPUT 2 "in" +L_0x182dfb0/d .functor NOT 1, L_0x182e750, C4<0>, C4<0>, C4<0>; +L_0x182dfb0 .delay 1 (10000,10000,10000) L_0x182dfb0/d; +L_0x182e070/d .functor AND 1, L_0x182e1d0, L_0x182dfb0, C4<1>, C4<1>; +L_0x182e070 .delay 1 (20000,20000,20000) L_0x182e070/d; +L_0x182e330/d .functor AND 1, L_0x182e440, L_0x182e750, C4<1>, C4<1>; +L_0x182e330 .delay 1 (20000,20000,20000) L_0x182e330/d; +L_0x182e5f0/d .functor OR 1, L_0x182e070, L_0x182e330, C4<0>, C4<0>; +L_0x182e5f0 .delay 1 (20000,20000,20000) L_0x182e5f0/d; +v0x176f500_0 .net *"_s1", 0 0, L_0x182e1d0; 1 drivers +v0x176f600_0 .net *"_s3", 0 0, L_0x182e440; 1 drivers +v0x176f6e0_0 .net "addr", 0 0, L_0x182e750; 1 drivers +v0x176f780_0 .net "in", 1 0, L_0x182e8b0; 1 drivers +v0x176f860_0 .net "naddr", 0 0, L_0x182dfb0; 1 drivers +v0x176f970_0 .net "o0", 0 0, L_0x182e070; 1 drivers +v0x176fa30_0 .net "o1", 0 0, L_0x182e330; 1 drivers +v0x176faf0_0 .net "out", 0 0, L_0x182e5f0; 1 drivers +L_0x182e1d0 .part L_0x182e8b0, 0, 1; +L_0x182e440 .part L_0x182e8b0, 1, 1; +S_0x176fc30 .scope module, "mux_mid_1" "bitMultiplexer" 4 34, 4 8 0, S_0x176ca10; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "addr" + .port_info 2 /INPUT 2 "in" +L_0x182e950/d .functor NOT 1, L_0x182f340, C4<0>, C4<0>, C4<0>; +L_0x182e950 .delay 1 (10000,10000,10000) L_0x182e950/d; +L_0x182ea10/d .functor AND 1, L_0x182ebc0, L_0x182e950, C4<1>, C4<1>; +L_0x182ea10 .delay 1 (20000,20000,20000) L_0x182ea10/d; +L_0x182ed20/d .functor AND 1, L_0x182ee30, L_0x182f340, C4<1>, C4<1>; +L_0x182ed20 .delay 1 (20000,20000,20000) L_0x182ed20/d; +L_0x182efe0/d .functor OR 1, L_0x182ea10, L_0x182ed20, C4<0>, C4<0>; +L_0x182efe0 .delay 1 (20000,20000,20000) L_0x182efe0/d; +v0x176fe60_0 .net *"_s1", 0 0, L_0x182ebc0; 1 drivers +v0x176ff60_0 .net *"_s3", 0 0, L_0x182ee30; 1 drivers +v0x1770040_0 .net "addr", 0 0, L_0x182f340; 1 drivers +v0x17700e0_0 .net "in", 1 0, L_0x182f3e0; 1 drivers +v0x17701c0_0 .net "naddr", 0 0, L_0x182e950; 1 drivers +v0x17702d0_0 .net "o0", 0 0, L_0x182ea10; 1 drivers +v0x1770390_0 .net "o1", 0 0, L_0x182ed20; 1 drivers +v0x1770450_0 .net "out", 0 0, L_0x182efe0; 1 drivers +L_0x182ebc0 .part L_0x182f3e0, 0, 1; +L_0x182ee30 .part L_0x182f3e0, 1, 1; +S_0x1770590 .scope module, "mux_out" "bitMultiplexer" 4 35, 4 8 0, S_0x176ca10; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "addr" + .port_info 2 /INPUT 2 "in" +L_0x182e7f0/d .functor NOT 1, L_0x182fc20, C4<0>, C4<0>, C4<0>; +L_0x182e7f0 .delay 1 (10000,10000,10000) L_0x182e7f0/d; +L_0x182f550/d .functor AND 1, L_0x182f6b0, L_0x182e7f0, C4<1>, C4<1>; +L_0x182f550 .delay 1 (20000,20000,20000) L_0x182f550/d; +L_0x182f810/d .functor AND 1, L_0x182f920, L_0x182fc20, C4<1>, C4<1>; +L_0x182f810 .delay 1 (20000,20000,20000) L_0x182f810/d; +L_0x182fb10/d .functor OR 1, L_0x182f550, L_0x182f810, C4<0>, C4<0>; +L_0x182fb10 .delay 1 (20000,20000,20000) L_0x182fb10/d; +v0x17707c0_0 .net *"_s1", 0 0, L_0x182f6b0; 1 drivers +v0x17708c0_0 .net *"_s3", 0 0, L_0x182f920; 1 drivers +v0x17709a0_0 .net "addr", 0 0, L_0x182fc20; 1 drivers +v0x1770a40_0 .net "in", 1 0, L_0x182f140; alias, 1 drivers +v0x1770b20_0 .net "naddr", 0 0, L_0x182e7f0; 1 drivers +v0x1770c30_0 .net "o0", 0 0, L_0x182f550; 1 drivers +v0x1770cf0_0 .net "o1", 0 0, L_0x182f810; 1 drivers +v0x1770db0_0 .net "out", 0 0, L_0x182fb10; alias, 1 drivers +L_0x182f6b0 .part L_0x182f140, 0, 1; +L_0x182f920 .part L_0x182f140, 1, 1; +S_0x1771340 .scope module, "structadder" "structAddSub" 3 22, 5 8 0, S_0x176c780; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "sub" + .port_info 5 /INPUT 1 "carryin" +L_0x182a3d0/d .functor XOR 1, L_0x1802ec0, v0x17dbbc0_0, C4<0>, C4<0>; +L_0x182a3d0 .delay 1 (20000,20000,20000) L_0x182a3d0/d; +L_0x182a5c0/d .functor XOR 1, L_0x182feb0, L_0x1802ec0, C4<0>, C4<0>; +L_0x182a5c0 .delay 1 (20000,20000,20000) L_0x182a5c0/d; +L_0x182a980/d .functor XOR 1, L_0x182a5c0, L_0x182fd80, C4<0>, C4<0>; +L_0x182a980 .delay 1 (20000,20000,20000) L_0x182a980/d; +L_0x182ab30/d .functor AND 1, L_0x182feb0, L_0x1802ec0, C4<1>, C4<1>; +L_0x182ab30 .delay 1 (20000,20000,20000) L_0x182ab30/d; +L_0x182ac90/d .functor AND 1, L_0x182a5c0, L_0x182fd80, C4<1>, C4<1>; +L_0x182ac90 .delay 1 (20000,20000,20000) L_0x182ac90/d; +L_0x182adf0/d .functor OR 1, L_0x182ac90, L_0x182ab30, C4<0>, C4<0>; +L_0x182adf0 .delay 1 (20000,20000,20000) L_0x182adf0/d; +v0x1771600_0 .net "AandB", 0 0, L_0x182ab30; 1 drivers +v0x17716c0_0 .net "AxorB", 0 0, L_0x182a5c0; 1 drivers +v0x1771780_0 .net "AxorBandCarryIn", 0 0, L_0x182ac90; 1 drivers +v0x1771850_0 .net "a", 0 0, L_0x182feb0; alias, 1 drivers +v0x1771910_0 .net "b", 0 0, L_0x1802ec0; alias, 1 drivers +v0x1771a20_0 .net "bnew", 0 0, L_0x182a3d0; 1 drivers +v0x1771ae0_0 .net "carryin", 0 0, L_0x182fd80; alias, 1 drivers +v0x1771ba0_0 .net "carryout", 0 0, L_0x182adf0; alias, 1 drivers +v0x1771c60_0 .net "sub", 0 0, v0x17dbbc0_0; alias, 1 drivers +v0x1771d90_0 .net "sum", 0 0, L_0x182a980; 1 drivers +S_0x1772c20 .scope generate, "ripple[16]" "ripple[16]" 3 66, 3 66 0, S_0x16fa6c0; + .timescale -9 -12; +P_0x15e5ac0 .param/l "i" 0 3 66, +C4<010000>; +S_0x1772f50 .scope module, "bit" "BitSliceALU" 3 68, 3 11 0, S_0x1772c20; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "ALUout" + .port_info 1 /OUTPUT 1 "Cout" + .port_info 2 /INPUT 1 "invertB" + .port_info 3 /INPUT 1 "Cin" + .port_info 4 /INPUT 3 "addr" + .port_info 5 /INPUT 1 "bit1" + .port_info 6 /INPUT 1 "bit2" +L_0x1830a40/d .functor XOR 1, L_0x18086e0, L_0x1830160, C4<0>, C4<0>; +L_0x1830a40 .delay 1 (20000,20000,20000) L_0x1830a40/d; +L_0x1830ba0/d .functor NAND 1, L_0x18086e0, L_0x1830160, C4<1>, C4<1>; +L_0x1830ba0 .delay 1 (10000,10000,10000) L_0x1830ba0/d; +L_0x1830d00/d .functor XOR 1, v0x17dbbc0_0, L_0x1830ba0, C4<0>, C4<0>; +L_0x1830d00 .delay 1 (20000,20000,20000) L_0x1830d00/d; +L_0x1830e10/d .functor NOR 1, L_0x18086e0, L_0x1830160, C4<0>, C4<0>; +L_0x1830e10 .delay 1 (10000,10000,10000) L_0x1830e10/d; +L_0x1830f70/d .functor XOR 1, v0x17dbbc0_0, L_0x1830e10, C4<0>, C4<0>; +L_0x1830f70 .delay 1 (20000,20000,20000) L_0x1830f70/d; +v0x1778b60_0 .net "ALUout", 0 0, L_0x1835620; 1 drivers +v0x1778c00_0 .net "Cin", 0 0, L_0x1835890; 1 drivers +v0x1778ca0_0 .net "Cout", 0 0, L_0x1830890; 1 drivers +v0x1778d40_0 .net *"_s11", 0 0, L_0x1830f70; 1 drivers +o0x7fc2cd920fd8 .functor BUFZ 1, C4; HiZ drive +; Elide local net with no drivers, v0x1778de0_0 name=_s15 +o0x7fc2cd921008 .functor BUFZ 3, C4; HiZ drive +; Elide local net with no drivers, v0x1778ef0_0 name=_s17 +v0x1778fd0_0 .net *"_s3", 0 0, L_0x1830a40; 1 drivers +v0x17790b0_0 .net *"_s7", 0 0, L_0x1830d00; 1 drivers +v0x1779190_0 .net "addr", 2 0, v0x17dbc90_0; alias, 1 drivers +v0x17792e0_0 .net "bit1", 0 0, L_0x18086e0; 1 drivers +v0x1779380_0 .net "bit2", 0 0, L_0x1830160; 1 drivers +v0x1779450_0 .net "invertB", 0 0, v0x17dbbc0_0; alias, 1 drivers +v0x17794f0_0 .net "nanded", 0 0, L_0x1830ba0; 1 drivers +v0x1779590_0 .net "nored", 0 0, L_0x1830e10; 1 drivers +v0x1779630_0 .net "out", 7 0, L_0x18933d0; 1 drivers +LS_0x18933d0_0_0 .concat [ 1 1 1 1], L_0x182c0c0, L_0x1830a40, o0x7fc2cd920fd8, L_0x1830d00; +LS_0x18933d0_0_4 .concat [ 1 3 0 0], L_0x1830f70, o0x7fc2cd921008; +L_0x18933d0 .concat [ 4 4 0 0], LS_0x18933d0_0_0, LS_0x18933d0_0_4; +S_0x17731e0 .scope module, "opmux" "structuralMultiplexer" 3 43, 4 21 0, S_0x1772f50; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 3 "address" + .port_info 2 /INPUT 8 "in" +v0x17776a0_0 .net "address", 2 0, v0x17dbc90_0; alias, 1 drivers +v0x173c790_0 .net "in", 7 0, L_0x18933d0; alias, 1 drivers +v0x173c870_0 .net "mux", 3 0, L_0x1833690; 1 drivers +v0x1777b70_0 .net "muxmid", 1 0, L_0x1834c50; 1 drivers +v0x1777c10_0 .net "out", 0 0, L_0x1835620; alias, 1 drivers +L_0x1831870 .part v0x17dbc90_0, 0, 1; +L_0x18319d0 .part L_0x18933d0, 0, 2; +L_0x18322b0 .part v0x17dbc90_0, 0, 1; +L_0x1832410 .part L_0x18933d0, 2, 2; +L_0x1832c80 .part v0x17dbc90_0, 0, 1; +L_0x1832de0 .part L_0x18933d0, 4, 2; +L_0x1833690 .concat8 [ 1 1 1 1], L_0x1831710, L_0x1832150, L_0x1832b20, L_0x1833530; +L_0x1833930 .part v0x17dbc90_0, 0, 1; +L_0x1833a20 .part L_0x18933d0, 6, 2; +L_0x1834260 .part v0x17dbc90_0, 1, 1; +L_0x18343c0 .part L_0x1833690, 0, 2; +L_0x1834c50 .concat8 [ 1 1 0 0], L_0x1834100, L_0x1834af0; +L_0x1834e50 .part v0x17dbc90_0, 1, 1; +L_0x1834ef0 .part L_0x1833690, 2, 2; +L_0x1835730 .part v0x17dbc90_0, 2, 1; +S_0x1773430 .scope module, "mux_0" "bitMultiplexer" 4 29, 4 8 0, S_0x17731e0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "addr" + .port_info 2 /INPUT 2 "in" +L_0x1831080/d .functor NOT 1, L_0x1831870, C4<0>, C4<0>, C4<0>; +L_0x1831080 .delay 1 (10000,10000,10000) L_0x1831080/d; +L_0x18311e0/d .functor AND 1, L_0x18312f0, L_0x1831080, C4<1>, C4<1>; +L_0x18311e0 .delay 1 (20000,20000,20000) L_0x18311e0/d; +L_0x1831450/d .functor AND 1, L_0x1831560, L_0x1831870, C4<1>, C4<1>; +L_0x1831450 .delay 1 (20000,20000,20000) L_0x1831450/d; +L_0x1831710/d .functor OR 1, L_0x18311e0, L_0x1831450, C4<0>, C4<0>; +L_0x1831710 .delay 1 (20000,20000,20000) L_0x1831710/d; +v0x17736a0_0 .net *"_s1", 0 0, L_0x18312f0; 1 drivers +v0x17737a0_0 .net *"_s3", 0 0, L_0x1831560; 1 drivers +v0x1773880_0 .net "addr", 0 0, L_0x1831870; 1 drivers +v0x1773950_0 .net "in", 1 0, L_0x18319d0; 1 drivers +v0x1773a30_0 .net "naddr", 0 0, L_0x1831080; 1 drivers +v0x1773b40_0 .net "o0", 0 0, L_0x18311e0; 1 drivers +v0x1773c00_0 .net "o1", 0 0, L_0x1831450; 1 drivers +v0x1773cc0_0 .net "out", 0 0, L_0x1831710; 1 drivers +L_0x18312f0 .part L_0x18319d0, 0, 1; +L_0x1831560 .part L_0x18319d0, 1, 1; +S_0x1773e00 .scope module, "mux_1" "bitMultiplexer" 4 30, 4 8 0, S_0x17731e0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "addr" + .port_info 2 /INPUT 2 "in" +L_0x1831a70/d .functor NOT 1, L_0x18322b0, C4<0>, C4<0>, C4<0>; +L_0x1831a70 .delay 1 (10000,10000,10000) L_0x1831a70/d; +L_0x1831b30/d .functor AND 1, L_0x1831d30, L_0x1831a70, C4<1>, C4<1>; +L_0x1831b30 .delay 1 (20000,20000,20000) L_0x1831b30/d; +L_0x1831e90/d .functor AND 1, L_0x1831fa0, L_0x18322b0, C4<1>, C4<1>; +L_0x1831e90 .delay 1 (20000,20000,20000) L_0x1831e90/d; +L_0x1832150/d .functor OR 1, L_0x1831b30, L_0x1831e90, C4<0>, C4<0>; +L_0x1832150 .delay 1 (20000,20000,20000) L_0x1832150/d; +v0x1774030_0 .net *"_s1", 0 0, L_0x1831d30; 1 drivers +v0x1774130_0 .net *"_s3", 0 0, L_0x1831fa0; 1 drivers +v0x1774210_0 .net "addr", 0 0, L_0x18322b0; 1 drivers +v0x17742b0_0 .net "in", 1 0, L_0x1832410; 1 drivers +v0x1774390_0 .net "naddr", 0 0, L_0x1831a70; 1 drivers +v0x17744a0_0 .net "o0", 0 0, L_0x1831b30; 1 drivers +v0x1774560_0 .net "o1", 0 0, L_0x1831e90; 1 drivers +v0x1774620_0 .net "out", 0 0, L_0x1832150; 1 drivers +L_0x1831d30 .part L_0x1832410, 0, 1; +L_0x1831fa0 .part L_0x1832410, 1, 1; +S_0x1774760 .scope module, "mux_2" "bitMultiplexer" 4 31, 4 8 0, S_0x17731e0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "addr" + .port_info 2 /INPUT 2 "in" +L_0x1832350/d .functor NOT 1, L_0x1832c80, C4<0>, C4<0>, C4<0>; +L_0x1832350 .delay 1 (10000,10000,10000) L_0x1832350/d; +L_0x1832500/d .functor AND 1, L_0x1832700, L_0x1832350, C4<1>, C4<1>; +L_0x1832500 .delay 1 (20000,20000,20000) L_0x1832500/d; +L_0x1832860/d .functor AND 1, L_0x1832970, L_0x1832c80, C4<1>, C4<1>; +L_0x1832860 .delay 1 (20000,20000,20000) L_0x1832860/d; +L_0x1832b20/d .functor OR 1, L_0x1832500, L_0x1832860, C4<0>, C4<0>; +L_0x1832b20 .delay 1 (20000,20000,20000) L_0x1832b20/d; +v0x1774990_0 .net *"_s1", 0 0, L_0x1832700; 1 drivers +v0x1774a70_0 .net *"_s3", 0 0, L_0x1832970; 1 drivers +v0x1774b50_0 .net "addr", 0 0, L_0x1832c80; 1 drivers +v0x1774c20_0 .net "in", 1 0, L_0x1832de0; 1 drivers +v0x1774d00_0 .net "naddr", 0 0, L_0x1832350; 1 drivers +v0x1774e10_0 .net "o0", 0 0, L_0x1832500; 1 drivers +v0x1774ed0_0 .net "o1", 0 0, L_0x1832860; 1 drivers +v0x1774f90_0 .net "out", 0 0, L_0x1832b20; 1 drivers +L_0x1832700 .part L_0x1832de0, 0, 1; +L_0x1832970 .part L_0x1832de0, 1, 1; +S_0x17750d0 .scope module, "mux_3" "bitMultiplexer" 4 32, 4 8 0, S_0x17731e0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "addr" + .port_info 2 /INPUT 2 "in" +L_0x1832d20/d .functor NOT 1, L_0x1833930, C4<0>, C4<0>, C4<0>; +L_0x1832d20 .delay 1 (10000,10000,10000) L_0x1832d20/d; +L_0x1832f10/d .functor AND 1, L_0x1833110, L_0x1832d20, C4<1>, C4<1>; +L_0x1832f10 .delay 1 (20000,20000,20000) L_0x1832f10/d; +L_0x1833270/d .functor AND 1, L_0x1833380, L_0x1833930, C4<1>, C4<1>; +L_0x1833270 .delay 1 (20000,20000,20000) L_0x1833270/d; +L_0x1833530/d .functor OR 1, L_0x1832f10, L_0x1833270, C4<0>, C4<0>; +L_0x1833530 .delay 1 (20000,20000,20000) L_0x1833530/d; +v0x1775300_0 .net *"_s1", 0 0, L_0x1833110; 1 drivers +v0x1775400_0 .net *"_s3", 0 0, L_0x1833380; 1 drivers +v0x17754e0_0 .net "addr", 0 0, L_0x1833930; 1 drivers +v0x1775580_0 .net "in", 1 0, L_0x1833a20; 1 drivers +v0x1775660_0 .net "naddr", 0 0, L_0x1832d20; 1 drivers +v0x1775770_0 .net "o0", 0 0, L_0x1832f10; 1 drivers +v0x1775830_0 .net "o1", 0 0, L_0x1833270; 1 drivers +v0x17758f0_0 .net "out", 0 0, L_0x1833530; 1 drivers +L_0x1833110 .part L_0x1833a20, 0, 1; +L_0x1833380 .part L_0x1833a20, 1, 1; +S_0x1775a30 .scope module, "mux_mid_0" "bitMultiplexer" 4 33, 4 8 0, S_0x17731e0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "addr" + .port_info 2 /INPUT 2 "in" +L_0x1833ac0/d .functor NOT 1, L_0x1834260, C4<0>, C4<0>, C4<0>; +L_0x1833ac0 .delay 1 (10000,10000,10000) L_0x1833ac0/d; +L_0x1833b80/d .functor AND 1, L_0x1833ce0, L_0x1833ac0, C4<1>, C4<1>; +L_0x1833b80 .delay 1 (20000,20000,20000) L_0x1833b80/d; +L_0x1833e40/d .functor AND 1, L_0x1833f50, L_0x1834260, C4<1>, C4<1>; +L_0x1833e40 .delay 1 (20000,20000,20000) L_0x1833e40/d; +L_0x1834100/d .functor OR 1, L_0x1833b80, L_0x1833e40, C4<0>, C4<0>; +L_0x1834100 .delay 1 (20000,20000,20000) L_0x1834100/d; +v0x1775cb0_0 .net *"_s1", 0 0, L_0x1833ce0; 1 drivers +v0x1775db0_0 .net *"_s3", 0 0, L_0x1833f50; 1 drivers +v0x1775e90_0 .net "addr", 0 0, L_0x1834260; 1 drivers +v0x1775f30_0 .net "in", 1 0, L_0x18343c0; 1 drivers +v0x1776010_0 .net "naddr", 0 0, L_0x1833ac0; 1 drivers +v0x1776120_0 .net "o0", 0 0, L_0x1833b80; 1 drivers +v0x17761e0_0 .net "o1", 0 0, L_0x1833e40; 1 drivers +v0x17762a0_0 .net "out", 0 0, L_0x1834100; 1 drivers +L_0x1833ce0 .part L_0x18343c0, 0, 1; +L_0x1833f50 .part L_0x18343c0, 1, 1; +S_0x17763e0 .scope module, "mux_mid_1" "bitMultiplexer" 4 34, 4 8 0, S_0x17731e0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "addr" + .port_info 2 /INPUT 2 "in" +L_0x1834460/d .functor NOT 1, L_0x1834e50, C4<0>, C4<0>, C4<0>; +L_0x1834460 .delay 1 (10000,10000,10000) L_0x1834460/d; +L_0x1834520/d .functor AND 1, L_0x18346d0, L_0x1834460, C4<1>, C4<1>; +L_0x1834520 .delay 1 (20000,20000,20000) L_0x1834520/d; +L_0x1834830/d .functor AND 1, L_0x1834940, L_0x1834e50, C4<1>, C4<1>; +L_0x1834830 .delay 1 (20000,20000,20000) L_0x1834830/d; +L_0x1834af0/d .functor OR 1, L_0x1834520, L_0x1834830, C4<0>, C4<0>; +L_0x1834af0 .delay 1 (20000,20000,20000) L_0x1834af0/d; +v0x1776610_0 .net *"_s1", 0 0, L_0x18346d0; 1 drivers +v0x1776710_0 .net *"_s3", 0 0, L_0x1834940; 1 drivers +v0x17767f0_0 .net "addr", 0 0, L_0x1834e50; 1 drivers +v0x1776890_0 .net "in", 1 0, L_0x1834ef0; 1 drivers +v0x1776970_0 .net "naddr", 0 0, L_0x1834460; 1 drivers +v0x1776a80_0 .net "o0", 0 0, L_0x1834520; 1 drivers +v0x1776b40_0 .net "o1", 0 0, L_0x1834830; 1 drivers +v0x1776c00_0 .net "out", 0 0, L_0x1834af0; 1 drivers +L_0x18346d0 .part L_0x1834ef0, 0, 1; +L_0x1834940 .part L_0x1834ef0, 1, 1; +S_0x1776d40 .scope module, "mux_out" "bitMultiplexer" 4 35, 4 8 0, S_0x17731e0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "addr" + .port_info 2 /INPUT 2 "in" +L_0x1834300/d .functor NOT 1, L_0x1835730, C4<0>, C4<0>, C4<0>; +L_0x1834300 .delay 1 (10000,10000,10000) L_0x1834300/d; +L_0x1835060/d .functor AND 1, L_0x18351c0, L_0x1834300, C4<1>, C4<1>; +L_0x1835060 .delay 1 (20000,20000,20000) L_0x1835060/d; +L_0x1835320/d .functor AND 1, L_0x1835430, L_0x1835730, C4<1>, C4<1>; +L_0x1835320 .delay 1 (20000,20000,20000) L_0x1835320/d; +L_0x1835620/d .functor OR 1, L_0x1835060, L_0x1835320, C4<0>, C4<0>; +L_0x1835620 .delay 1 (20000,20000,20000) L_0x1835620/d; +v0x1776f70_0 .net *"_s1", 0 0, L_0x18351c0; 1 drivers +v0x1777070_0 .net *"_s3", 0 0, L_0x1835430; 1 drivers +v0x1777150_0 .net "addr", 0 0, L_0x1835730; 1 drivers +v0x17771f0_0 .net "in", 1 0, L_0x1834c50; alias, 1 drivers +v0x17772d0_0 .net "naddr", 0 0, L_0x1834300; 1 drivers +v0x17773e0_0 .net "o0", 0 0, L_0x1835060; 1 drivers +v0x17774a0_0 .net "o1", 0 0, L_0x1835320; 1 drivers +v0x1777560_0 .net "out", 0 0, L_0x1835620; alias, 1 drivers +L_0x18351c0 .part L_0x1834c50, 0, 1; +L_0x1835430 .part L_0x1834c50, 1, 1; +S_0x1777d00 .scope module, "structadder" "structAddSub" 3 22, 5 8 0, S_0x1772f50; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "sub" + .port_info 5 /INPUT 1 "carryin" +L_0x182fcc0/d .functor XOR 1, L_0x1830160, v0x17dbbc0_0, C4<0>, C4<0>; +L_0x182fcc0 .delay 1 (20000,20000,20000) L_0x182fcc0/d; +L_0x182aba0/d .functor XOR 1, L_0x18086e0, L_0x1830160, C4<0>, C4<0>; +L_0x182aba0 .delay 1 (20000,20000,20000) L_0x182aba0/d; +L_0x182c0c0/d .functor XOR 1, L_0x182aba0, L_0x1835890, C4<0>, C4<0>; +L_0x182c0c0 .delay 1 (20000,20000,20000) L_0x182c0c0/d; +L_0x18305d0/d .functor AND 1, L_0x18086e0, L_0x1830160, C4<1>, C4<1>; +L_0x18305d0 .delay 1 (20000,20000,20000) L_0x18305d0/d; +L_0x1830730/d .functor AND 1, L_0x182aba0, L_0x1835890, C4<1>, C4<1>; +L_0x1830730 .delay 1 (20000,20000,20000) L_0x1830730/d; +L_0x1830890/d .functor OR 1, L_0x1830730, L_0x18305d0, C4<0>, C4<0>; +L_0x1830890 .delay 1 (20000,20000,20000) L_0x1830890/d; +v0x1777fc0_0 .net "AandB", 0 0, L_0x18305d0; 1 drivers +v0x1778080_0 .net "AxorB", 0 0, L_0x182aba0; 1 drivers +v0x1778140_0 .net "AxorBandCarryIn", 0 0, L_0x1830730; 1 drivers +v0x1778210_0 .net "a", 0 0, L_0x18086e0; alias, 1 drivers +v0x17782d0_0 .net "b", 0 0, L_0x1830160; alias, 1 drivers +v0x17783e0_0 .net "bnew", 0 0, L_0x182fcc0; 1 drivers +v0x17784a0_0 .net "carryin", 0 0, L_0x1835890; alias, 1 drivers +v0x1778560_0 .net "carryout", 0 0, L_0x1830890; alias, 1 drivers +v0x1778620_0 .net "sub", 0 0, v0x17dbbc0_0; alias, 1 drivers +v0x173d460_0 .net "sum", 0 0, L_0x182c0c0; 1 drivers +S_0x17797e0 .scope generate, "ripple[17]" "ripple[17]" 3 66, 3 66 0, S_0x16fa6c0; + .timescale -9 -12; +P_0x17799b0 .param/l "i" 0 3 66, +C4<010001>; +S_0x1779a70 .scope module, "bit" "BitSliceALU" 3 68, 3 11 0, S_0x17797e0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "ALUout" + .port_info 1 /OUTPUT 1 "Cout" + .port_info 2 /INPUT 1 "invertB" + .port_info 3 /INPUT 1 "Cin" + .port_info 4 /INPUT 3 "addr" + .port_info 5 /INPUT 1 "bit1" + .port_info 6 /INPUT 1 "bit2" +L_0x1836490/d .functor XOR 1, L_0x183b3c0, L_0x1835e60, C4<0>, C4<0>; +L_0x1836490 .delay 1 (20000,20000,20000) L_0x1836490/d; +L_0x18365f0/d .functor NAND 1, L_0x183b3c0, L_0x1835e60, C4<1>, C4<1>; +L_0x18365f0 .delay 1 (10000,10000,10000) L_0x18365f0/d; +L_0x1836750/d .functor XOR 1, v0x17dbbc0_0, L_0x18365f0, C4<0>, C4<0>; +L_0x1836750 .delay 1 (20000,20000,20000) L_0x1836750/d; +L_0x1836860/d .functor NOR 1, L_0x183b3c0, L_0x1835e60, C4<0>, C4<0>; +L_0x1836860 .delay 1 (10000,10000,10000) L_0x1836860/d; +L_0x18369c0/d .functor XOR 1, v0x17dbbc0_0, L_0x1836860, C4<0>, C4<0>; +L_0x18369c0 .delay 1 (20000,20000,20000) L_0x18369c0/d; +v0x177f240_0 .net "ALUout", 0 0, L_0x183b020; 1 drivers +v0x177f300_0 .net "Cin", 0 0, L_0x183b290; 1 drivers +v0x177f3c0_0 .net "Cout", 0 0, L_0x1831bd0; 1 drivers +v0x177f490_0 .net *"_s11", 0 0, L_0x18369c0; 1 drivers +o0x7fc2cd9224a8 .functor BUFZ 1, C4; HiZ drive +; Elide local net with no drivers, v0x177f530_0 name=_s15 +o0x7fc2cd9224d8 .functor BUFZ 3, C4; HiZ drive +; Elide local net with no drivers, v0x177f620_0 name=_s17 +v0x177f700_0 .net *"_s3", 0 0, L_0x1836490; 1 drivers +v0x177f7e0_0 .net *"_s7", 0 0, L_0x1836750; 1 drivers +v0x177f8c0_0 .net "addr", 2 0, v0x17dbc90_0; alias, 1 drivers +v0x177fa10_0 .net "bit1", 0 0, L_0x183b3c0; 1 drivers +v0x177fab0_0 .net "bit2", 0 0, L_0x1835e60; 1 drivers +v0x177fb80_0 .net "invertB", 0 0, v0x17dbbc0_0; alias, 1 drivers +v0x177fc20_0 .net "nanded", 0 0, L_0x18365f0; 1 drivers +v0x177fcc0_0 .net "nored", 0 0, L_0x1836860; 1 drivers +v0x177fd60_0 .net "out", 7 0, L_0x18935b0; 1 drivers +LS_0x18935b0_0_0 .concat [ 1 1 1 1], L_0x1835bd0, L_0x1836490, o0x7fc2cd9224a8, L_0x1836750; +LS_0x18935b0_0_4 .concat [ 1 3 0 0], L_0x18369c0, o0x7fc2cd9224d8; +L_0x18935b0 .concat [ 4 4 0 0], LS_0x18935b0_0_0, LS_0x18935b0_0_4; +S_0x1779d00 .scope module, "opmux" "structuralMultiplexer" 3 43, 4 21 0, S_0x1779a70; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 3 "address" + .port_info 2 /INPUT 8 "in" +v0x177e1e0_0 .net "address", 2 0, v0x17dbc90_0; alias, 1 drivers +v0x177e2a0_0 .net "in", 7 0, L_0x18935b0; alias, 1 drivers +v0x177e380_0 .net "mux", 3 0, L_0x18390e0; 1 drivers +v0x177e440_0 .net "muxmid", 1 0, L_0x183a650; 1 drivers +v0x177e500_0 .net "out", 0 0, L_0x183b020; alias, 1 drivers +L_0x18372c0 .part v0x17dbc90_0, 0, 1; +L_0x1837420 .part L_0x18935b0, 0, 2; +L_0x1837d00 .part v0x17dbc90_0, 0, 1; +L_0x1837e60 .part L_0x18935b0, 2, 2; +L_0x18386d0 .part v0x17dbc90_0, 0, 1; +L_0x1838830 .part L_0x18935b0, 4, 2; +L_0x18390e0 .concat8 [ 1 1 1 1], L_0x1837160, L_0x1837ba0, L_0x1838570, L_0x1838f80; +L_0x1839330 .part v0x17dbc90_0, 0, 1; +L_0x1839420 .part L_0x18935b0, 6, 2; +L_0x1839c60 .part v0x17dbc90_0, 1, 1; +L_0x1839dc0 .part L_0x18390e0, 0, 2; +L_0x183a650 .concat8 [ 1 1 0 0], L_0x1839b00, L_0x183a4f0; +L_0x183a850 .part v0x17dbc90_0, 1, 1; +L_0x183a8f0 .part L_0x18390e0, 2, 2; +L_0x183b130 .part v0x17dbc90_0, 2, 1; +S_0x1779f70 .scope module, "mux_0" "bitMultiplexer" 4 29, 4 8 0, S_0x1779d00; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "addr" + .port_info 2 /INPUT 2 "in" +L_0x1836ad0/d .functor NOT 1, L_0x18372c0, C4<0>, C4<0>, C4<0>; +L_0x1836ad0 .delay 1 (10000,10000,10000) L_0x1836ad0/d; +L_0x1836c30/d .functor AND 1, L_0x1836d40, L_0x1836ad0, C4<1>, C4<1>; +L_0x1836c30 .delay 1 (20000,20000,20000) L_0x1836c30/d; +L_0x1836ea0/d .functor AND 1, L_0x1836fb0, L_0x18372c0, C4<1>, C4<1>; +L_0x1836ea0 .delay 1 (20000,20000,20000) L_0x1836ea0/d; +L_0x1837160/d .functor OR 1, L_0x1836c30, L_0x1836ea0, C4<0>, C4<0>; +L_0x1837160 .delay 1 (20000,20000,20000) L_0x1837160/d; +v0x177a1e0_0 .net *"_s1", 0 0, L_0x1836d40; 1 drivers +v0x177a2e0_0 .net *"_s3", 0 0, L_0x1836fb0; 1 drivers +v0x177a3c0_0 .net "addr", 0 0, L_0x18372c0; 1 drivers +v0x177a490_0 .net "in", 1 0, L_0x1837420; 1 drivers +v0x177a570_0 .net "naddr", 0 0, L_0x1836ad0; 1 drivers +v0x177a680_0 .net "o0", 0 0, L_0x1836c30; 1 drivers +v0x177a740_0 .net "o1", 0 0, L_0x1836ea0; 1 drivers +v0x177a800_0 .net "out", 0 0, L_0x1837160; 1 drivers +L_0x1836d40 .part L_0x1837420, 0, 1; +L_0x1836fb0 .part L_0x1837420, 1, 1; +S_0x177a940 .scope module, "mux_1" "bitMultiplexer" 4 30, 4 8 0, S_0x1779d00; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "addr" + .port_info 2 /INPUT 2 "in" +L_0x18374c0/d .functor NOT 1, L_0x1837d00, C4<0>, C4<0>, C4<0>; +L_0x18374c0 .delay 1 (10000,10000,10000) L_0x18374c0/d; +L_0x1837580/d .functor AND 1, L_0x1837780, L_0x18374c0, C4<1>, C4<1>; +L_0x1837580 .delay 1 (20000,20000,20000) L_0x1837580/d; +L_0x18378e0/d .functor AND 1, L_0x18379f0, L_0x1837d00, C4<1>, C4<1>; +L_0x18378e0 .delay 1 (20000,20000,20000) L_0x18378e0/d; +L_0x1837ba0/d .functor OR 1, L_0x1837580, L_0x18378e0, C4<0>, C4<0>; +L_0x1837ba0 .delay 1 (20000,20000,20000) L_0x1837ba0/d; +v0x177ab70_0 .net *"_s1", 0 0, L_0x1837780; 1 drivers +v0x177ac70_0 .net *"_s3", 0 0, L_0x18379f0; 1 drivers +v0x177ad50_0 .net "addr", 0 0, L_0x1837d00; 1 drivers +v0x177adf0_0 .net "in", 1 0, L_0x1837e60; 1 drivers +v0x177aed0_0 .net "naddr", 0 0, L_0x18374c0; 1 drivers +v0x177afe0_0 .net "o0", 0 0, L_0x1837580; 1 drivers +v0x177b0a0_0 .net "o1", 0 0, L_0x18378e0; 1 drivers +v0x177b160_0 .net "out", 0 0, L_0x1837ba0; 1 drivers +L_0x1837780 .part L_0x1837e60, 0, 1; +L_0x18379f0 .part L_0x1837e60, 1, 1; +S_0x177b2a0 .scope module, "mux_2" "bitMultiplexer" 4 31, 4 8 0, S_0x1779d00; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "addr" + .port_info 2 /INPUT 2 "in" +L_0x1837da0/d .functor NOT 1, L_0x18386d0, C4<0>, C4<0>, C4<0>; +L_0x1837da0 .delay 1 (10000,10000,10000) L_0x1837da0/d; +L_0x1837f50/d .functor AND 1, L_0x1838150, L_0x1837da0, C4<1>, C4<1>; +L_0x1837f50 .delay 1 (20000,20000,20000) L_0x1837f50/d; +L_0x18382b0/d .functor AND 1, L_0x18383c0, L_0x18386d0, C4<1>, C4<1>; +L_0x18382b0 .delay 1 (20000,20000,20000) L_0x18382b0/d; +L_0x1838570/d .functor OR 1, L_0x1837f50, L_0x18382b0, C4<0>, C4<0>; +L_0x1838570 .delay 1 (20000,20000,20000) L_0x1838570/d; +v0x177b4d0_0 .net *"_s1", 0 0, L_0x1838150; 1 drivers +v0x177b5b0_0 .net *"_s3", 0 0, L_0x18383c0; 1 drivers +v0x177b690_0 .net "addr", 0 0, L_0x18386d0; 1 drivers +v0x177b760_0 .net "in", 1 0, L_0x1838830; 1 drivers +v0x177b840_0 .net "naddr", 0 0, L_0x1837da0; 1 drivers +v0x177b950_0 .net "o0", 0 0, L_0x1837f50; 1 drivers +v0x177ba10_0 .net "o1", 0 0, L_0x18382b0; 1 drivers +v0x177bad0_0 .net "out", 0 0, L_0x1838570; 1 drivers +L_0x1838150 .part L_0x1838830, 0, 1; +L_0x18383c0 .part L_0x1838830, 1, 1; +S_0x177bc10 .scope module, "mux_3" "bitMultiplexer" 4 32, 4 8 0, S_0x1779d00; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "addr" + .port_info 2 /INPUT 2 "in" +L_0x1838770/d .functor NOT 1, L_0x1839330, C4<0>, C4<0>, C4<0>; +L_0x1838770 .delay 1 (10000,10000,10000) L_0x1838770/d; +L_0x1838960/d .functor AND 1, L_0x1838b60, L_0x1838770, C4<1>, C4<1>; +L_0x1838960 .delay 1 (20000,20000,20000) L_0x1838960/d; +L_0x1838cc0/d .functor AND 1, L_0x1838dd0, L_0x1839330, C4<1>, C4<1>; +L_0x1838cc0 .delay 1 (20000,20000,20000) L_0x1838cc0/d; +L_0x1838f80/d .functor OR 1, L_0x1838960, L_0x1838cc0, C4<0>, C4<0>; +L_0x1838f80 .delay 1 (20000,20000,20000) L_0x1838f80/d; +v0x177be40_0 .net *"_s1", 0 0, L_0x1838b60; 1 drivers +v0x177bf40_0 .net *"_s3", 0 0, L_0x1838dd0; 1 drivers +v0x177c020_0 .net "addr", 0 0, L_0x1839330; 1 drivers +v0x177c0c0_0 .net "in", 1 0, L_0x1839420; 1 drivers +v0x177c1a0_0 .net "naddr", 0 0, L_0x1838770; 1 drivers +v0x177c2b0_0 .net "o0", 0 0, L_0x1838960; 1 drivers +v0x177c370_0 .net "o1", 0 0, L_0x1838cc0; 1 drivers +v0x177c430_0 .net "out", 0 0, L_0x1838f80; 1 drivers +L_0x1838b60 .part L_0x1839420, 0, 1; +L_0x1838dd0 .part L_0x1839420, 1, 1; +S_0x177c570 .scope module, "mux_mid_0" "bitMultiplexer" 4 33, 4 8 0, S_0x1779d00; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "addr" + .port_info 2 /INPUT 2 "in" +L_0x18394c0/d .functor NOT 1, L_0x1839c60, C4<0>, C4<0>, C4<0>; +L_0x18394c0 .delay 1 (10000,10000,10000) L_0x18394c0/d; +L_0x1839580/d .functor AND 1, L_0x18396e0, L_0x18394c0, C4<1>, C4<1>; +L_0x1839580 .delay 1 (20000,20000,20000) L_0x1839580/d; +L_0x1839840/d .functor AND 1, L_0x1839950, L_0x1839c60, C4<1>, C4<1>; +L_0x1839840 .delay 1 (20000,20000,20000) L_0x1839840/d; +L_0x1839b00/d .functor OR 1, L_0x1839580, L_0x1839840, C4<0>, C4<0>; +L_0x1839b00 .delay 1 (20000,20000,20000) L_0x1839b00/d; +v0x177c7f0_0 .net *"_s1", 0 0, L_0x18396e0; 1 drivers +v0x177c8f0_0 .net *"_s3", 0 0, L_0x1839950; 1 drivers +v0x177c9d0_0 .net "addr", 0 0, L_0x1839c60; 1 drivers +v0x177ca70_0 .net "in", 1 0, L_0x1839dc0; 1 drivers +v0x177cb50_0 .net "naddr", 0 0, L_0x18394c0; 1 drivers +v0x177cc60_0 .net "o0", 0 0, L_0x1839580; 1 drivers +v0x177cd20_0 .net "o1", 0 0, L_0x1839840; 1 drivers +v0x177cde0_0 .net "out", 0 0, L_0x1839b00; 1 drivers +L_0x18396e0 .part L_0x1839dc0, 0, 1; +L_0x1839950 .part L_0x1839dc0, 1, 1; +S_0x177cf20 .scope module, "mux_mid_1" "bitMultiplexer" 4 34, 4 8 0, S_0x1779d00; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "addr" + .port_info 2 /INPUT 2 "in" +L_0x1839e60/d .functor NOT 1, L_0x183a850, C4<0>, C4<0>, C4<0>; +L_0x1839e60 .delay 1 (10000,10000,10000) L_0x1839e60/d; +L_0x1839f20/d .functor AND 1, L_0x183a0d0, L_0x1839e60, C4<1>, C4<1>; +L_0x1839f20 .delay 1 (20000,20000,20000) L_0x1839f20/d; +L_0x183a230/d .functor AND 1, L_0x183a340, L_0x183a850, C4<1>, C4<1>; +L_0x183a230 .delay 1 (20000,20000,20000) L_0x183a230/d; +L_0x183a4f0/d .functor OR 1, L_0x1839f20, L_0x183a230, C4<0>, C4<0>; +L_0x183a4f0 .delay 1 (20000,20000,20000) L_0x183a4f0/d; +v0x177d150_0 .net *"_s1", 0 0, L_0x183a0d0; 1 drivers +v0x177d250_0 .net *"_s3", 0 0, L_0x183a340; 1 drivers +v0x177d330_0 .net "addr", 0 0, L_0x183a850; 1 drivers +v0x177d3d0_0 .net "in", 1 0, L_0x183a8f0; 1 drivers +v0x177d4b0_0 .net "naddr", 0 0, L_0x1839e60; 1 drivers +v0x177d5c0_0 .net "o0", 0 0, L_0x1839f20; 1 drivers +v0x177d680_0 .net "o1", 0 0, L_0x183a230; 1 drivers +v0x177d740_0 .net "out", 0 0, L_0x183a4f0; 1 drivers +L_0x183a0d0 .part L_0x183a8f0, 0, 1; +L_0x183a340 .part L_0x183a8f0, 1, 1; +S_0x177d880 .scope module, "mux_out" "bitMultiplexer" 4 35, 4 8 0, S_0x1779d00; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "addr" + .port_info 2 /INPUT 2 "in" +L_0x1839d00/d .functor NOT 1, L_0x183b130, C4<0>, C4<0>, C4<0>; +L_0x1839d00 .delay 1 (10000,10000,10000) L_0x1839d00/d; +L_0x183aa60/d .functor AND 1, L_0x183abc0, L_0x1839d00, C4<1>, C4<1>; +L_0x183aa60 .delay 1 (20000,20000,20000) L_0x183aa60/d; +L_0x183ad20/d .functor AND 1, L_0x183ae30, L_0x183b130, C4<1>, C4<1>; +L_0x183ad20 .delay 1 (20000,20000,20000) L_0x183ad20/d; +L_0x183b020/d .functor OR 1, L_0x183aa60, L_0x183ad20, C4<0>, C4<0>; +L_0x183b020 .delay 1 (20000,20000,20000) L_0x183b020/d; +v0x177dab0_0 .net *"_s1", 0 0, L_0x183abc0; 1 drivers +v0x177dbb0_0 .net *"_s3", 0 0, L_0x183ae30; 1 drivers +v0x177dc90_0 .net "addr", 0 0, L_0x183b130; 1 drivers +v0x177dd30_0 .net "in", 1 0, L_0x183a650; alias, 1 drivers +v0x177de10_0 .net "naddr", 0 0, L_0x1839d00; 1 drivers +v0x177df20_0 .net "o0", 0 0, L_0x183aa60; 1 drivers +v0x177dfe0_0 .net "o1", 0 0, L_0x183ad20; 1 drivers +v0x177e0a0_0 .net "out", 0 0, L_0x183b020; alias, 1 drivers +L_0x183abc0 .part L_0x183a650, 0, 1; +L_0x183ae30 .part L_0x183a650, 1, 1; +S_0x177e630 .scope module, "structadder" "structAddSub" 3 22, 5 8 0, S_0x1779a70; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "sub" + .port_info 5 /INPUT 1 "carryin" +L_0x18357d0/d .functor XOR 1, L_0x1835e60, v0x17dbbc0_0, C4<0>, C4<0>; +L_0x18357d0 .delay 1 (20000,20000,20000) L_0x18357d0/d; +L_0x1830640/d .functor XOR 1, L_0x183b3c0, L_0x1835e60, C4<0>, C4<0>; +L_0x1830640 .delay 1 (20000,20000,20000) L_0x1830640/d; +L_0x1835bd0/d .functor XOR 1, L_0x1830640, L_0x183b290, C4<0>, C4<0>; +L_0x1835bd0 .delay 1 (20000,20000,20000) L_0x1835bd0/d; +L_0x1836090/d .functor AND 1, L_0x183b3c0, L_0x1835e60, C4<1>, C4<1>; +L_0x1836090 .delay 1 (20000,20000,20000) L_0x1836090/d; +L_0x18361f0/d .functor AND 1, L_0x1830640, L_0x183b290, C4<1>, C4<1>; +L_0x18361f0 .delay 1 (20000,20000,20000) L_0x18361f0/d; +L_0x1831bd0/d .functor OR 1, L_0x18361f0, L_0x1836090, C4<0>, C4<0>; +L_0x1831bd0 .delay 1 (20000,20000,20000) L_0x1831bd0/d; +v0x177e8f0_0 .net "AandB", 0 0, L_0x1836090; 1 drivers +v0x177e9b0_0 .net "AxorB", 0 0, L_0x1830640; 1 drivers +v0x177ea70_0 .net "AxorBandCarryIn", 0 0, L_0x18361f0; 1 drivers +v0x177eb40_0 .net "a", 0 0, L_0x183b3c0; alias, 1 drivers +v0x177ec00_0 .net "b", 0 0, L_0x1835e60; alias, 1 drivers +v0x177ed10_0 .net "bnew", 0 0, L_0x18357d0; 1 drivers +v0x177edd0_0 .net "carryin", 0 0, L_0x183b290; alias, 1 drivers +v0x177ee90_0 .net "carryout", 0 0, L_0x1831bd0; alias, 1 drivers +v0x177ef50_0 .net "sub", 0 0, v0x17dbbc0_0; alias, 1 drivers +v0x177f080_0 .net "sum", 0 0, L_0x1835bd0; 1 drivers +S_0x177ff10 .scope generate, "ripple[18]" "ripple[18]" 3 66, 3 66 0, S_0x16fa6c0; + .timescale -9 -12; +P_0x17800e0 .param/l "i" 0 3 66, +C4<010010>; +S_0x17801a0 .scope module, "bit" "BitSliceALU" 3 68, 3 11 0, S_0x177ff10; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "ALUout" + .port_info 1 /OUTPUT 1 "Cout" + .port_info 2 /INPUT 1 "invertB" + .port_info 3 /INPUT 1 "Cin" + .port_info 4 /INPUT 3 "addr" + .port_info 5 /INPUT 1 "bit1" + .port_info 6 /INPUT 1 "bit2" +L_0x183bd80/d .functor XOR 1, L_0x183b460, L_0x183b500, C4<0>, C4<0>; +L_0x183bd80 .delay 1 (20000,20000,20000) L_0x183bd80/d; +L_0x183bee0/d .functor NAND 1, L_0x183b460, L_0x183b500, C4<1>, C4<1>; +L_0x183bee0 .delay 1 (10000,10000,10000) L_0x183bee0/d; +L_0x183c040/d .functor XOR 1, v0x17dbbc0_0, L_0x183bee0, C4<0>, C4<0>; +L_0x183c040 .delay 1 (20000,20000,20000) L_0x183c040/d; +L_0x183c150/d .functor NOR 1, L_0x183b460, L_0x183b500, C4<0>, C4<0>; +L_0x183c150 .delay 1 (10000,10000,10000) L_0x183c150/d; +L_0x183c2b0/d .functor XOR 1, v0x17dbbc0_0, L_0x183c150, C4<0>, C4<0>; +L_0x183c2b0 .delay 1 (20000,20000,20000) L_0x183c2b0/d; +v0x1785990_0 .net "ALUout", 0 0, L_0x18408c0; 1 drivers +v0x1785a50_0 .net "Cin", 0 0, L_0x1840b30; 1 drivers +v0x1785b10_0 .net "Cout", 0 0, L_0x183bbd0; 1 drivers +v0x1785be0_0 .net *"_s11", 0 0, L_0x183c2b0; 1 drivers +o0x7fc2cd923978 .functor BUFZ 1, C4; HiZ drive +; Elide local net with no drivers, v0x1785c80_0 name=_s15 +o0x7fc2cd9239a8 .functor BUFZ 3, C4; HiZ drive +; Elide local net with no drivers, v0x1785d70_0 name=_s17 +v0x1785e50_0 .net *"_s3", 0 0, L_0x183bd80; 1 drivers +v0x1785f30_0 .net *"_s7", 0 0, L_0x183c040; 1 drivers +v0x1786010_0 .net "addr", 2 0, v0x17dbc90_0; alias, 1 drivers +v0x1786160_0 .net "bit1", 0 0, L_0x183b460; 1 drivers +v0x1786200_0 .net "bit2", 0 0, L_0x183b500; 1 drivers +v0x17862d0_0 .net "invertB", 0 0, v0x17dbbc0_0; alias, 1 drivers +v0x1786370_0 .net "nanded", 0 0, L_0x183bee0; 1 drivers +v0x1786410_0 .net "nored", 0 0, L_0x183c150; 1 drivers +v0x17864b0_0 .net "out", 7 0, L_0x1893790; 1 drivers +LS_0x1893790_0_0 .concat [ 1 1 1 1], L_0x183b760, L_0x183bd80, o0x7fc2cd923978, L_0x183c040; +LS_0x1893790_0_4 .concat [ 1 3 0 0], L_0x183c2b0, o0x7fc2cd9239a8; +L_0x1893790 .concat [ 4 4 0 0], LS_0x1893790_0_0, LS_0x1893790_0_4; +S_0x1780430 .scope module, "opmux" "structuralMultiplexer" 3 43, 4 21 0, S_0x17801a0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 3 "address" + .port_info 2 /INPUT 8 "in" +v0x1784900_0 .net "address", 2 0, v0x17dbc90_0; alias, 1 drivers +v0x17849c0_0 .net "in", 7 0, L_0x1893790; alias, 1 drivers +v0x1784aa0_0 .net "mux", 3 0, L_0x183e9d0; 1 drivers +v0x1784b60_0 .net "muxmid", 1 0, L_0x183fef0; 1 drivers +v0x1784c50_0 .net "out", 0 0, L_0x18408c0; alias, 1 drivers +L_0x183cbb0 .part v0x17dbc90_0, 0, 1; +L_0x183cd10 .part L_0x1893790, 0, 2; +L_0x183d5f0 .part v0x17dbc90_0, 0, 1; +L_0x183d750 .part L_0x1893790, 2, 2; +L_0x183dfc0 .part v0x17dbc90_0, 0, 1; +L_0x183e120 .part L_0x1893790, 4, 2; +L_0x183e9d0 .concat8 [ 1 1 1 1], L_0x183ca50, L_0x183d490, L_0x183de60, L_0x183e870; +L_0x183ec20 .part v0x17dbc90_0, 0, 1; +L_0x183ed10 .part L_0x1893790, 6, 2; +L_0x183f550 .part v0x17dbc90_0, 1, 1; +L_0x183f6b0 .part L_0x183e9d0, 0, 2; +L_0x183fef0 .concat8 [ 1 1 0 0], L_0x183f3f0, L_0x183fd90; +L_0x18400f0 .part v0x17dbc90_0, 1, 1; +L_0x1840190 .part L_0x183e9d0, 2, 2; +L_0x18409d0 .part v0x17dbc90_0, 2, 1; +S_0x17806a0 .scope module, "mux_0" "bitMultiplexer" 4 29, 4 8 0, S_0x1780430; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "addr" + .port_info 2 /INPUT 2 "in" +L_0x183c3c0/d .functor NOT 1, L_0x183cbb0, C4<0>, C4<0>, C4<0>; +L_0x183c3c0 .delay 1 (10000,10000,10000) L_0x183c3c0/d; +L_0x183c520/d .functor AND 1, L_0x183c630, L_0x183c3c0, C4<1>, C4<1>; +L_0x183c520 .delay 1 (20000,20000,20000) L_0x183c520/d; +L_0x183c790/d .functor AND 1, L_0x183c8a0, L_0x183cbb0, C4<1>, C4<1>; +L_0x183c790 .delay 1 (20000,20000,20000) L_0x183c790/d; +L_0x183ca50/d .functor OR 1, L_0x183c520, L_0x183c790, C4<0>, C4<0>; +L_0x183ca50 .delay 1 (20000,20000,20000) L_0x183ca50/d; +v0x1780910_0 .net *"_s1", 0 0, L_0x183c630; 1 drivers +v0x1780a10_0 .net *"_s3", 0 0, L_0x183c8a0; 1 drivers +v0x1780af0_0 .net "addr", 0 0, L_0x183cbb0; 1 drivers +v0x1780bc0_0 .net "in", 1 0, L_0x183cd10; 1 drivers +v0x1780ca0_0 .net "naddr", 0 0, L_0x183c3c0; 1 drivers +v0x1780db0_0 .net "o0", 0 0, L_0x183c520; 1 drivers +v0x1780e70_0 .net "o1", 0 0, L_0x183c790; 1 drivers +v0x1780f30_0 .net "out", 0 0, L_0x183ca50; 1 drivers +L_0x183c630 .part L_0x183cd10, 0, 1; +L_0x183c8a0 .part L_0x183cd10, 1, 1; +S_0x1781070 .scope module, "mux_1" "bitMultiplexer" 4 30, 4 8 0, S_0x1780430; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "addr" + .port_info 2 /INPUT 2 "in" +L_0x183cdb0/d .functor NOT 1, L_0x183d5f0, C4<0>, C4<0>, C4<0>; +L_0x183cdb0 .delay 1 (10000,10000,10000) L_0x183cdb0/d; +L_0x183ce70/d .functor AND 1, L_0x183d070, L_0x183cdb0, C4<1>, C4<1>; +L_0x183ce70 .delay 1 (20000,20000,20000) L_0x183ce70/d; +L_0x183d1d0/d .functor AND 1, L_0x183d2e0, L_0x183d5f0, C4<1>, C4<1>; +L_0x183d1d0 .delay 1 (20000,20000,20000) L_0x183d1d0/d; +L_0x183d490/d .functor OR 1, L_0x183ce70, L_0x183d1d0, C4<0>, C4<0>; +L_0x183d490 .delay 1 (20000,20000,20000) L_0x183d490/d; +v0x17812a0_0 .net *"_s1", 0 0, L_0x183d070; 1 drivers +v0x17813a0_0 .net *"_s3", 0 0, L_0x183d2e0; 1 drivers +v0x1781480_0 .net "addr", 0 0, L_0x183d5f0; 1 drivers +v0x1781520_0 .net "in", 1 0, L_0x183d750; 1 drivers +v0x1781600_0 .net "naddr", 0 0, L_0x183cdb0; 1 drivers +v0x1781710_0 .net "o0", 0 0, L_0x183ce70; 1 drivers +v0x17817d0_0 .net "o1", 0 0, L_0x183d1d0; 1 drivers +v0x1781890_0 .net "out", 0 0, L_0x183d490; 1 drivers +L_0x183d070 .part L_0x183d750, 0, 1; +L_0x183d2e0 .part L_0x183d750, 1, 1; +S_0x17819d0 .scope module, "mux_2" "bitMultiplexer" 4 31, 4 8 0, S_0x1780430; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "addr" + .port_info 2 /INPUT 2 "in" +L_0x183d690/d .functor NOT 1, L_0x183dfc0, C4<0>, C4<0>, C4<0>; +L_0x183d690 .delay 1 (10000,10000,10000) L_0x183d690/d; +L_0x183d840/d .functor AND 1, L_0x183da40, L_0x183d690, C4<1>, C4<1>; +L_0x183d840 .delay 1 (20000,20000,20000) L_0x183d840/d; +L_0x183dba0/d .functor AND 1, L_0x183dcb0, L_0x183dfc0, C4<1>, C4<1>; +L_0x183dba0 .delay 1 (20000,20000,20000) L_0x183dba0/d; +L_0x183de60/d .functor OR 1, L_0x183d840, L_0x183dba0, C4<0>, C4<0>; +L_0x183de60 .delay 1 (20000,20000,20000) L_0x183de60/d; +v0x1781c00_0 .net *"_s1", 0 0, L_0x183da40; 1 drivers +v0x1781ce0_0 .net *"_s3", 0 0, L_0x183dcb0; 1 drivers +v0x1781dc0_0 .net "addr", 0 0, L_0x183dfc0; 1 drivers +v0x1781e90_0 .net "in", 1 0, L_0x183e120; 1 drivers +v0x1781f70_0 .net "naddr", 0 0, L_0x183d690; 1 drivers +v0x1782080_0 .net "o0", 0 0, L_0x183d840; 1 drivers +v0x1782140_0 .net "o1", 0 0, L_0x183dba0; 1 drivers +v0x1782200_0 .net "out", 0 0, L_0x183de60; 1 drivers +L_0x183da40 .part L_0x183e120, 0, 1; +L_0x183dcb0 .part L_0x183e120, 1, 1; +S_0x1782340 .scope module, "mux_3" "bitMultiplexer" 4 32, 4 8 0, S_0x1780430; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "addr" + .port_info 2 /INPUT 2 "in" +L_0x183e060/d .functor NOT 1, L_0x183ec20, C4<0>, C4<0>, C4<0>; +L_0x183e060 .delay 1 (10000,10000,10000) L_0x183e060/d; +L_0x183e250/d .functor AND 1, L_0x183e450, L_0x183e060, C4<1>, C4<1>; +L_0x183e250 .delay 1 (20000,20000,20000) L_0x183e250/d; +L_0x183e5b0/d .functor AND 1, L_0x183e6c0, L_0x183ec20, C4<1>, C4<1>; +L_0x183e5b0 .delay 1 (20000,20000,20000) L_0x183e5b0/d; +L_0x183e870/d .functor OR 1, L_0x183e250, L_0x183e5b0, C4<0>, C4<0>; +L_0x183e870 .delay 1 (20000,20000,20000) L_0x183e870/d; +v0x1782570_0 .net *"_s1", 0 0, L_0x183e450; 1 drivers +v0x1782670_0 .net *"_s3", 0 0, L_0x183e6c0; 1 drivers +v0x1782750_0 .net "addr", 0 0, L_0x183ec20; 1 drivers +v0x17827f0_0 .net "in", 1 0, L_0x183ed10; 1 drivers +v0x17828d0_0 .net "naddr", 0 0, L_0x183e060; 1 drivers +v0x17829e0_0 .net "o0", 0 0, L_0x183e250; 1 drivers +v0x1782aa0_0 .net "o1", 0 0, L_0x183e5b0; 1 drivers +v0x1782b60_0 .net "out", 0 0, L_0x183e870; 1 drivers +L_0x183e450 .part L_0x183ed10, 0, 1; +L_0x183e6c0 .part L_0x183ed10, 1, 1; +S_0x1782ca0 .scope module, "mux_mid_0" "bitMultiplexer" 4 33, 4 8 0, S_0x1780430; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "addr" + .port_info 2 /INPUT 2 "in" +L_0x183edb0/d .functor NOT 1, L_0x183f550, C4<0>, C4<0>, C4<0>; +L_0x183edb0 .delay 1 (10000,10000,10000) L_0x183edb0/d; +L_0x183ee70/d .functor AND 1, L_0x183efd0, L_0x183edb0, C4<1>, C4<1>; +L_0x183ee70 .delay 1 (20000,20000,20000) L_0x183ee70/d; +L_0x183f130/d .functor AND 1, L_0x183f240, L_0x183f550, C4<1>, C4<1>; +L_0x183f130 .delay 1 (20000,20000,20000) L_0x183f130/d; +L_0x183f3f0/d .functor OR 1, L_0x183ee70, L_0x183f130, C4<0>, C4<0>; +L_0x183f3f0 .delay 1 (20000,20000,20000) L_0x183f3f0/d; +v0x1782f20_0 .net *"_s1", 0 0, L_0x183efd0; 1 drivers +v0x1782fe0_0 .net *"_s3", 0 0, L_0x183f240; 1 drivers +v0x17830c0_0 .net "addr", 0 0, L_0x183f550; 1 drivers +v0x1783190_0 .net "in", 1 0, L_0x183f6b0; 1 drivers +v0x1783270_0 .net "naddr", 0 0, L_0x183edb0; 1 drivers +v0x1783380_0 .net "o0", 0 0, L_0x183ee70; 1 drivers +v0x1783440_0 .net "o1", 0 0, L_0x183f130; 1 drivers +v0x1783500_0 .net "out", 0 0, L_0x183f3f0; 1 drivers +L_0x183efd0 .part L_0x183f6b0, 0, 1; +L_0x183f240 .part L_0x183f6b0, 1, 1; +S_0x1783640 .scope module, "mux_mid_1" "bitMultiplexer" 4 34, 4 8 0, S_0x1780430; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "addr" + .port_info 2 /INPUT 2 "in" +L_0x183f750/d .functor NOT 1, L_0x18400f0, C4<0>, C4<0>, C4<0>; +L_0x183f750 .delay 1 (10000,10000,10000) L_0x183f750/d; +L_0x183f810/d .functor AND 1, L_0x183f970, L_0x183f750, C4<1>, C4<1>; +L_0x183f810 .delay 1 (20000,20000,20000) L_0x183f810/d; +L_0x183fad0/d .functor AND 1, L_0x183fbe0, L_0x18400f0, C4<1>, C4<1>; +L_0x183fad0 .delay 1 (20000,20000,20000) L_0x183fad0/d; +L_0x183fd90/d .functor OR 1, L_0x183f810, L_0x183fad0, C4<0>, C4<0>; +L_0x183fd90 .delay 1 (20000,20000,20000) L_0x183fd90/d; +v0x1783870_0 .net *"_s1", 0 0, L_0x183f970; 1 drivers +v0x1783970_0 .net *"_s3", 0 0, L_0x183fbe0; 1 drivers +v0x1783a50_0 .net "addr", 0 0, L_0x18400f0; 1 drivers +v0x1783af0_0 .net "in", 1 0, L_0x1840190; 1 drivers +v0x1783bd0_0 .net "naddr", 0 0, L_0x183f750; 1 drivers +v0x1783ce0_0 .net "o0", 0 0, L_0x183f810; 1 drivers +v0x1783da0_0 .net "o1", 0 0, L_0x183fad0; 1 drivers +v0x1783e60_0 .net "out", 0 0, L_0x183fd90; 1 drivers +L_0x183f970 .part L_0x1840190, 0, 1; +L_0x183fbe0 .part L_0x1840190, 1, 1; +S_0x1783fa0 .scope module, "mux_out" "bitMultiplexer" 4 35, 4 8 0, S_0x1780430; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "addr" + .port_info 2 /INPUT 2 "in" +L_0x183f5f0/d .functor NOT 1, L_0x18409d0, C4<0>, C4<0>, C4<0>; +L_0x183f5f0 .delay 1 (10000,10000,10000) L_0x183f5f0/d; +L_0x1840300/d .functor AND 1, L_0x1840460, L_0x183f5f0, C4<1>, C4<1>; +L_0x1840300 .delay 1 (20000,20000,20000) L_0x1840300/d; +L_0x18405c0/d .functor AND 1, L_0x18406d0, L_0x18409d0, C4<1>, C4<1>; +L_0x18405c0 .delay 1 (20000,20000,20000) L_0x18405c0/d; +L_0x18408c0/d .functor OR 1, L_0x1840300, L_0x18405c0, C4<0>, C4<0>; +L_0x18408c0 .delay 1 (20000,20000,20000) L_0x18408c0/d; +v0x17841d0_0 .net *"_s1", 0 0, L_0x1840460; 1 drivers +v0x17842d0_0 .net *"_s3", 0 0, L_0x18406d0; 1 drivers +v0x17843b0_0 .net "addr", 0 0, L_0x18409d0; 1 drivers +v0x1784450_0 .net "in", 1 0, L_0x183fef0; alias, 1 drivers +v0x1784530_0 .net "naddr", 0 0, L_0x183f5f0; 1 drivers +v0x1784640_0 .net "o0", 0 0, L_0x1840300; 1 drivers +v0x1784700_0 .net "o1", 0 0, L_0x18405c0; 1 drivers +v0x17847c0_0 .net "out", 0 0, L_0x18408c0; alias, 1 drivers +L_0x1840460 .part L_0x183fef0, 0, 1; +L_0x18406d0 .part L_0x183fef0, 1, 1; +S_0x1784d80 .scope module, "structadder" "structAddSub" 3 22, 5 8 0, S_0x17801a0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "sub" + .port_info 5 /INPUT 1 "carryin" +L_0x183b1d0/d .functor XOR 1, L_0x183b500, v0x17dbbc0_0, C4<0>, C4<0>; +L_0x183b1d0 .delay 1 (20000,20000,20000) L_0x183b1d0/d; +L_0x1835f00/d .functor XOR 1, L_0x183b460, L_0x183b500, C4<0>, C4<0>; +L_0x1835f00 .delay 1 (20000,20000,20000) L_0x1835f00/d; +L_0x183b760/d .functor XOR 1, L_0x1835f00, L_0x1840b30, C4<0>, C4<0>; +L_0x183b760 .delay 1 (20000,20000,20000) L_0x183b760/d; +L_0x183b910/d .functor AND 1, L_0x183b460, L_0x183b500, C4<1>, C4<1>; +L_0x183b910 .delay 1 (20000,20000,20000) L_0x183b910/d; +L_0x183ba70/d .functor AND 1, L_0x1835f00, L_0x1840b30, C4<1>, C4<1>; +L_0x183ba70 .delay 1 (20000,20000,20000) L_0x183ba70/d; +L_0x183bbd0/d .functor OR 1, L_0x183ba70, L_0x183b910, C4<0>, C4<0>; +L_0x183bbd0 .delay 1 (20000,20000,20000) L_0x183bbd0/d; +v0x1785040_0 .net "AandB", 0 0, L_0x183b910; 1 drivers +v0x1785100_0 .net "AxorB", 0 0, L_0x1835f00; 1 drivers +v0x17851c0_0 .net "AxorBandCarryIn", 0 0, L_0x183ba70; 1 drivers +v0x1785290_0 .net "a", 0 0, L_0x183b460; alias, 1 drivers +v0x1785350_0 .net "b", 0 0, L_0x183b500; alias, 1 drivers +v0x1785460_0 .net "bnew", 0 0, L_0x183b1d0; 1 drivers +v0x1785520_0 .net "carryin", 0 0, L_0x1840b30; alias, 1 drivers +v0x17855e0_0 .net "carryout", 0 0, L_0x183bbd0; alias, 1 drivers +v0x17856a0_0 .net "sub", 0 0, v0x17dbbc0_0; alias, 1 drivers +v0x17857d0_0 .net "sum", 0 0, L_0x183b760; 1 drivers +S_0x1786660 .scope generate, "ripple[19]" "ripple[19]" 3 66, 3 66 0, S_0x16fa6c0; + .timescale -9 -12; +P_0x1786830 .param/l "i" 0 3 66, +C4<010011>; +S_0x17868f0 .scope module, "bit" "BitSliceALU" 3 68, 3 11 0, S_0x1786660; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "ALUout" + .port_info 1 /OUTPUT 1 "Cout" + .port_info 2 /INPUT 1 "invertB" + .port_info 3 /INPUT 1 "Cin" + .port_info 4 /INPUT 3 "addr" + .port_info 5 /INPUT 1 "bit1" + .port_info 6 /INPUT 1 "bit2" +L_0x1841640/d .functor XOR 1, L_0x1846570, L_0x1840f20, C4<0>, C4<0>; +L_0x1841640 .delay 1 (20000,20000,20000) L_0x1841640/d; +L_0x18417a0/d .functor NAND 1, L_0x1846570, L_0x1840f20, C4<1>, C4<1>; +L_0x18417a0 .delay 1 (10000,10000,10000) L_0x18417a0/d; +L_0x1841900/d .functor XOR 1, v0x17dbbc0_0, L_0x18417a0, C4<0>, C4<0>; +L_0x1841900 .delay 1 (20000,20000,20000) L_0x1841900/d; +L_0x1841a10/d .functor NOR 1, L_0x1846570, L_0x1840f20, C4<0>, C4<0>; +L_0x1841a10 .delay 1 (10000,10000,10000) L_0x1841a10/d; +L_0x1841b70/d .functor XOR 1, v0x17dbbc0_0, L_0x1841a10, C4<0>, C4<0>; +L_0x1841b70 .delay 1 (20000,20000,20000) L_0x1841b70/d; +v0x178c0c0_0 .net "ALUout", 0 0, L_0x18461d0; 1 drivers +v0x178c180_0 .net "Cin", 0 0, L_0x1846440; 1 drivers +v0x178c240_0 .net "Cout", 0 0, L_0x1841490; 1 drivers +v0x178c310_0 .net *"_s11", 0 0, L_0x1841b70; 1 drivers +o0x7fc2cd924e48 .functor BUFZ 1, C4; HiZ drive +; Elide local net with no drivers, v0x178c3b0_0 name=_s15 +o0x7fc2cd924e78 .functor BUFZ 3, C4; HiZ drive +; Elide local net with no drivers, v0x178c4a0_0 name=_s17 +v0x178c580_0 .net *"_s3", 0 0, L_0x1841640; 1 drivers +v0x178c660_0 .net *"_s7", 0 0, L_0x1841900; 1 drivers +v0x178c740_0 .net "addr", 2 0, v0x17dbc90_0; alias, 1 drivers +v0x178c890_0 .net "bit1", 0 0, L_0x1846570; 1 drivers +v0x178c930_0 .net "bit2", 0 0, L_0x1840f20; 1 drivers +v0x178ca00_0 .net "invertB", 0 0, v0x17dbbc0_0; alias, 1 drivers +v0x178caa0_0 .net "nanded", 0 0, L_0x18417a0; 1 drivers +v0x178cb40_0 .net "nored", 0 0, L_0x1841a10; 1 drivers +v0x178cbe0_0 .net "out", 7 0, L_0x1893970; 1 drivers +LS_0x1893970_0_0 .concat [ 1 1 1 1], L_0x1840d00, L_0x1841640, o0x7fc2cd924e48, L_0x1841900; +LS_0x1893970_0_4 .concat [ 1 3 0 0], L_0x1841b70, o0x7fc2cd924e78; +L_0x1893970 .concat [ 4 4 0 0], LS_0x1893970_0_0, LS_0x1893970_0_4; +S_0x1786b80 .scope module, "opmux" "structuralMultiplexer" 3 43, 4 21 0, S_0x17868f0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 3 "address" + .port_info 2 /INPUT 8 "in" +v0x178b060_0 .net "address", 2 0, v0x17dbc90_0; alias, 1 drivers +v0x178b120_0 .net "in", 7 0, L_0x1893970; alias, 1 drivers +v0x178b200_0 .net "mux", 3 0, L_0x1844290; 1 drivers +v0x178b2c0_0 .net "muxmid", 1 0, L_0x1845800; 1 drivers +v0x178b380_0 .net "out", 0 0, L_0x18461d0; alias, 1 drivers +L_0x1842470 .part v0x17dbc90_0, 0, 1; +L_0x18425d0 .part L_0x1893970, 0, 2; +L_0x1842eb0 .part v0x17dbc90_0, 0, 1; +L_0x1843010 .part L_0x1893970, 2, 2; +L_0x1843880 .part v0x17dbc90_0, 0, 1; +L_0x18439e0 .part L_0x1893970, 4, 2; +L_0x1844290 .concat8 [ 1 1 1 1], L_0x1842310, L_0x1842d50, L_0x1843720, L_0x1844130; +L_0x18444e0 .part v0x17dbc90_0, 0, 1; +L_0x18445d0 .part L_0x1893970, 6, 2; +L_0x1844e10 .part v0x17dbc90_0, 1, 1; +L_0x1844f70 .part L_0x1844290, 0, 2; +L_0x1845800 .concat8 [ 1 1 0 0], L_0x1844cb0, L_0x18456a0; +L_0x1845a00 .part v0x17dbc90_0, 1, 1; +L_0x1845aa0 .part L_0x1844290, 2, 2; +L_0x18462e0 .part v0x17dbc90_0, 2, 1; +S_0x1786df0 .scope module, "mux_0" "bitMultiplexer" 4 29, 4 8 0, S_0x1786b80; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "addr" + .port_info 2 /INPUT 2 "in" +L_0x1841c80/d .functor NOT 1, L_0x1842470, C4<0>, C4<0>, C4<0>; +L_0x1841c80 .delay 1 (10000,10000,10000) L_0x1841c80/d; +L_0x1841de0/d .functor AND 1, L_0x1841ef0, L_0x1841c80, C4<1>, C4<1>; +L_0x1841de0 .delay 1 (20000,20000,20000) L_0x1841de0/d; +L_0x1842050/d .functor AND 1, L_0x1842160, L_0x1842470, C4<1>, C4<1>; +L_0x1842050 .delay 1 (20000,20000,20000) L_0x1842050/d; +L_0x1842310/d .functor OR 1, L_0x1841de0, L_0x1842050, C4<0>, C4<0>; +L_0x1842310 .delay 1 (20000,20000,20000) L_0x1842310/d; +v0x1787060_0 .net *"_s1", 0 0, L_0x1841ef0; 1 drivers +v0x1787160_0 .net *"_s3", 0 0, L_0x1842160; 1 drivers +v0x1787240_0 .net "addr", 0 0, L_0x1842470; 1 drivers +v0x1787310_0 .net "in", 1 0, L_0x18425d0; 1 drivers +v0x17873f0_0 .net "naddr", 0 0, L_0x1841c80; 1 drivers +v0x1787500_0 .net "o0", 0 0, L_0x1841de0; 1 drivers +v0x17875c0_0 .net "o1", 0 0, L_0x1842050; 1 drivers +v0x1787680_0 .net "out", 0 0, L_0x1842310; 1 drivers +L_0x1841ef0 .part L_0x18425d0, 0, 1; +L_0x1842160 .part L_0x18425d0, 1, 1; +S_0x17877c0 .scope module, "mux_1" "bitMultiplexer" 4 30, 4 8 0, S_0x1786b80; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "addr" + .port_info 2 /INPUT 2 "in" +L_0x1842670/d .functor NOT 1, L_0x1842eb0, C4<0>, C4<0>, C4<0>; +L_0x1842670 .delay 1 (10000,10000,10000) L_0x1842670/d; +L_0x1842730/d .functor AND 1, L_0x1842930, L_0x1842670, C4<1>, C4<1>; +L_0x1842730 .delay 1 (20000,20000,20000) L_0x1842730/d; +L_0x1842a90/d .functor AND 1, L_0x1842ba0, L_0x1842eb0, C4<1>, C4<1>; +L_0x1842a90 .delay 1 (20000,20000,20000) L_0x1842a90/d; +L_0x1842d50/d .functor OR 1, L_0x1842730, L_0x1842a90, C4<0>, C4<0>; +L_0x1842d50 .delay 1 (20000,20000,20000) L_0x1842d50/d; +v0x17879f0_0 .net *"_s1", 0 0, L_0x1842930; 1 drivers +v0x1787af0_0 .net *"_s3", 0 0, L_0x1842ba0; 1 drivers +v0x1787bd0_0 .net "addr", 0 0, L_0x1842eb0; 1 drivers +v0x1787c70_0 .net "in", 1 0, L_0x1843010; 1 drivers +v0x1787d50_0 .net "naddr", 0 0, L_0x1842670; 1 drivers +v0x1787e60_0 .net "o0", 0 0, L_0x1842730; 1 drivers +v0x1787f20_0 .net "o1", 0 0, L_0x1842a90; 1 drivers +v0x1787fe0_0 .net "out", 0 0, L_0x1842d50; 1 drivers +L_0x1842930 .part L_0x1843010, 0, 1; +L_0x1842ba0 .part L_0x1843010, 1, 1; +S_0x1788120 .scope module, "mux_2" "bitMultiplexer" 4 31, 4 8 0, S_0x1786b80; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "addr" + .port_info 2 /INPUT 2 "in" +L_0x1842f50/d .functor NOT 1, L_0x1843880, C4<0>, C4<0>, C4<0>; +L_0x1842f50 .delay 1 (10000,10000,10000) L_0x1842f50/d; +L_0x1843100/d .functor AND 1, L_0x1843300, L_0x1842f50, C4<1>, C4<1>; +L_0x1843100 .delay 1 (20000,20000,20000) L_0x1843100/d; +L_0x1843460/d .functor AND 1, L_0x1843570, L_0x1843880, C4<1>, C4<1>; +L_0x1843460 .delay 1 (20000,20000,20000) L_0x1843460/d; +L_0x1843720/d .functor OR 1, L_0x1843100, L_0x1843460, C4<0>, C4<0>; +L_0x1843720 .delay 1 (20000,20000,20000) L_0x1843720/d; +v0x1788350_0 .net *"_s1", 0 0, L_0x1843300; 1 drivers +v0x1788430_0 .net *"_s3", 0 0, L_0x1843570; 1 drivers +v0x1788510_0 .net "addr", 0 0, L_0x1843880; 1 drivers +v0x17885e0_0 .net "in", 1 0, L_0x18439e0; 1 drivers +v0x17886c0_0 .net "naddr", 0 0, L_0x1842f50; 1 drivers +v0x17887d0_0 .net "o0", 0 0, L_0x1843100; 1 drivers +v0x1788890_0 .net "o1", 0 0, L_0x1843460; 1 drivers +v0x1788950_0 .net "out", 0 0, L_0x1843720; 1 drivers +L_0x1843300 .part L_0x18439e0, 0, 1; +L_0x1843570 .part L_0x18439e0, 1, 1; +S_0x1788a90 .scope module, "mux_3" "bitMultiplexer" 4 32, 4 8 0, S_0x1786b80; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "addr" + .port_info 2 /INPUT 2 "in" +L_0x1843920/d .functor NOT 1, L_0x18444e0, C4<0>, C4<0>, C4<0>; +L_0x1843920 .delay 1 (10000,10000,10000) L_0x1843920/d; +L_0x1843b10/d .functor AND 1, L_0x1843d10, L_0x1843920, C4<1>, C4<1>; +L_0x1843b10 .delay 1 (20000,20000,20000) L_0x1843b10/d; +L_0x1843e70/d .functor AND 1, L_0x1843f80, L_0x18444e0, C4<1>, C4<1>; +L_0x1843e70 .delay 1 (20000,20000,20000) L_0x1843e70/d; +L_0x1844130/d .functor OR 1, L_0x1843b10, L_0x1843e70, C4<0>, C4<0>; +L_0x1844130 .delay 1 (20000,20000,20000) L_0x1844130/d; +v0x1788cc0_0 .net *"_s1", 0 0, L_0x1843d10; 1 drivers +v0x1788dc0_0 .net *"_s3", 0 0, L_0x1843f80; 1 drivers +v0x1788ea0_0 .net "addr", 0 0, L_0x18444e0; 1 drivers +v0x1788f40_0 .net "in", 1 0, L_0x18445d0; 1 drivers +v0x1789020_0 .net "naddr", 0 0, L_0x1843920; 1 drivers +v0x1789130_0 .net "o0", 0 0, L_0x1843b10; 1 drivers +v0x17891f0_0 .net "o1", 0 0, L_0x1843e70; 1 drivers +v0x17892b0_0 .net "out", 0 0, L_0x1844130; 1 drivers +L_0x1843d10 .part L_0x18445d0, 0, 1; +L_0x1843f80 .part L_0x18445d0, 1, 1; +S_0x17893f0 .scope module, "mux_mid_0" "bitMultiplexer" 4 33, 4 8 0, S_0x1786b80; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "addr" + .port_info 2 /INPUT 2 "in" +L_0x1844670/d .functor NOT 1, L_0x1844e10, C4<0>, C4<0>, C4<0>; +L_0x1844670 .delay 1 (10000,10000,10000) L_0x1844670/d; +L_0x1844730/d .functor AND 1, L_0x1844890, L_0x1844670, C4<1>, C4<1>; +L_0x1844730 .delay 1 (20000,20000,20000) L_0x1844730/d; +L_0x18449f0/d .functor AND 1, L_0x1844b00, L_0x1844e10, C4<1>, C4<1>; +L_0x18449f0 .delay 1 (20000,20000,20000) L_0x18449f0/d; +L_0x1844cb0/d .functor OR 1, L_0x1844730, L_0x18449f0, C4<0>, C4<0>; +L_0x1844cb0 .delay 1 (20000,20000,20000) L_0x1844cb0/d; +v0x1789670_0 .net *"_s1", 0 0, L_0x1844890; 1 drivers +v0x1789770_0 .net *"_s3", 0 0, L_0x1844b00; 1 drivers +v0x1789850_0 .net "addr", 0 0, L_0x1844e10; 1 drivers +v0x17898f0_0 .net "in", 1 0, L_0x1844f70; 1 drivers +v0x17899d0_0 .net "naddr", 0 0, L_0x1844670; 1 drivers +v0x1789ae0_0 .net "o0", 0 0, L_0x1844730; 1 drivers +v0x1789ba0_0 .net "o1", 0 0, L_0x18449f0; 1 drivers +v0x1789c60_0 .net "out", 0 0, L_0x1844cb0; 1 drivers +L_0x1844890 .part L_0x1844f70, 0, 1; +L_0x1844b00 .part L_0x1844f70, 1, 1; +S_0x1789da0 .scope module, "mux_mid_1" "bitMultiplexer" 4 34, 4 8 0, S_0x1786b80; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "addr" + .port_info 2 /INPUT 2 "in" +L_0x1845010/d .functor NOT 1, L_0x1845a00, C4<0>, C4<0>, C4<0>; +L_0x1845010 .delay 1 (10000,10000,10000) L_0x1845010/d; +L_0x18450d0/d .functor AND 1, L_0x1845280, L_0x1845010, C4<1>, C4<1>; +L_0x18450d0 .delay 1 (20000,20000,20000) L_0x18450d0/d; +L_0x18453e0/d .functor AND 1, L_0x18454f0, L_0x1845a00, C4<1>, C4<1>; +L_0x18453e0 .delay 1 (20000,20000,20000) L_0x18453e0/d; +L_0x18456a0/d .functor OR 1, L_0x18450d0, L_0x18453e0, C4<0>, C4<0>; +L_0x18456a0 .delay 1 (20000,20000,20000) L_0x18456a0/d; +v0x1789fd0_0 .net *"_s1", 0 0, L_0x1845280; 1 drivers +v0x178a0d0_0 .net *"_s3", 0 0, L_0x18454f0; 1 drivers +v0x178a1b0_0 .net "addr", 0 0, L_0x1845a00; 1 drivers +v0x178a250_0 .net "in", 1 0, L_0x1845aa0; 1 drivers +v0x178a330_0 .net "naddr", 0 0, L_0x1845010; 1 drivers +v0x178a440_0 .net "o0", 0 0, L_0x18450d0; 1 drivers +v0x178a500_0 .net "o1", 0 0, L_0x18453e0; 1 drivers +v0x178a5c0_0 .net "out", 0 0, L_0x18456a0; 1 drivers +L_0x1845280 .part L_0x1845aa0, 0, 1; +L_0x18454f0 .part L_0x1845aa0, 1, 1; +S_0x178a700 .scope module, "mux_out" "bitMultiplexer" 4 35, 4 8 0, S_0x1786b80; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "addr" + .port_info 2 /INPUT 2 "in" +L_0x1844eb0/d .functor NOT 1, L_0x18462e0, C4<0>, C4<0>, C4<0>; +L_0x1844eb0 .delay 1 (10000,10000,10000) L_0x1844eb0/d; +L_0x1845c10/d .functor AND 1, L_0x1845d70, L_0x1844eb0, C4<1>, C4<1>; +L_0x1845c10 .delay 1 (20000,20000,20000) L_0x1845c10/d; +L_0x1845ed0/d .functor AND 1, L_0x1845fe0, L_0x18462e0, C4<1>, C4<1>; +L_0x1845ed0 .delay 1 (20000,20000,20000) L_0x1845ed0/d; +L_0x18461d0/d .functor OR 1, L_0x1845c10, L_0x1845ed0, C4<0>, C4<0>; +L_0x18461d0 .delay 1 (20000,20000,20000) L_0x18461d0/d; +v0x178a930_0 .net *"_s1", 0 0, L_0x1845d70; 1 drivers +v0x178aa30_0 .net *"_s3", 0 0, L_0x1845fe0; 1 drivers +v0x178ab10_0 .net "addr", 0 0, L_0x18462e0; 1 drivers +v0x178abb0_0 .net "in", 1 0, L_0x1845800; alias, 1 drivers +v0x178ac90_0 .net "naddr", 0 0, L_0x1844eb0; 1 drivers +v0x178ada0_0 .net "o0", 0 0, L_0x1845c10; 1 drivers +v0x178ae60_0 .net "o1", 0 0, L_0x1845ed0; 1 drivers +v0x178af20_0 .net "out", 0 0, L_0x18461d0; alias, 1 drivers +L_0x1845d70 .part L_0x1845800, 0, 1; +L_0x1845fe0 .part L_0x1845800, 1, 1; +S_0x178b4b0 .scope module, "structadder" "structAddSub" 3 22, 5 8 0, S_0x17868f0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "sub" + .port_info 5 /INPUT 1 "carryin" +L_0x1840a70/d .functor XOR 1, L_0x1840f20, v0x17dbbc0_0, C4<0>, C4<0>; +L_0x1840a70 .delay 1 (20000,20000,20000) L_0x1840a70/d; +L_0x183b980/d .functor XOR 1, L_0x1846570, L_0x1840f20, C4<0>, C4<0>; +L_0x183b980 .delay 1 (20000,20000,20000) L_0x183b980/d; +L_0x1840d00/d .functor XOR 1, L_0x183b980, L_0x1846440, C4<0>, C4<0>; +L_0x1840d00 .delay 1 (20000,20000,20000) L_0x1840d00/d; +L_0x18411d0/d .functor AND 1, L_0x1846570, L_0x1840f20, C4<1>, C4<1>; +L_0x18411d0 .delay 1 (20000,20000,20000) L_0x18411d0/d; +L_0x1841330/d .functor AND 1, L_0x183b980, L_0x1846440, C4<1>, C4<1>; +L_0x1841330 .delay 1 (20000,20000,20000) L_0x1841330/d; +L_0x1841490/d .functor OR 1, L_0x1841330, L_0x18411d0, C4<0>, C4<0>; +L_0x1841490 .delay 1 (20000,20000,20000) L_0x1841490/d; +v0x178b770_0 .net "AandB", 0 0, L_0x18411d0; 1 drivers +v0x178b830_0 .net "AxorB", 0 0, L_0x183b980; 1 drivers +v0x178b8f0_0 .net "AxorBandCarryIn", 0 0, L_0x1841330; 1 drivers +v0x178b9c0_0 .net "a", 0 0, L_0x1846570; alias, 1 drivers +v0x178ba80_0 .net "b", 0 0, L_0x1840f20; alias, 1 drivers +v0x178bb90_0 .net "bnew", 0 0, L_0x1840a70; 1 drivers +v0x178bc50_0 .net "carryin", 0 0, L_0x1846440; alias, 1 drivers +v0x178bd10_0 .net "carryout", 0 0, L_0x1841490; alias, 1 drivers +v0x178bdd0_0 .net "sub", 0 0, v0x17dbbc0_0; alias, 1 drivers +v0x178bf00_0 .net "sum", 0 0, L_0x1840d00; 1 drivers +S_0x178cd90 .scope generate, "ripple[20]" "ripple[20]" 3 66, 3 66 0, S_0x16fa6c0; + .timescale -9 -12; +P_0x178cf60 .param/l "i" 0 3 66, +C4<010100>; +S_0x178d020 .scope module, "bit" "BitSliceALU" 3 68, 3 11 0, S_0x178cd90; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "ALUout" + .port_info 1 /OUTPUT 1 "Cout" + .port_info 2 /INPUT 1 "invertB" + .port_info 3 /INPUT 1 "Cin" + .port_info 4 /INPUT 3 "addr" + .port_info 5 /INPUT 1 "bit1" + .port_info 6 /INPUT 1 "bit2" +L_0x1846f10/d .functor XOR 1, L_0x1846610, L_0x18466b0, C4<0>, C4<0>; +L_0x1846f10 .delay 1 (20000,20000,20000) L_0x1846f10/d; +L_0x1847070/d .functor NAND 1, L_0x1846610, L_0x18466b0, C4<1>, C4<1>; +L_0x1847070 .delay 1 (10000,10000,10000) L_0x1847070/d; +L_0x18471d0/d .functor XOR 1, v0x17dbbc0_0, L_0x1847070, C4<0>, C4<0>; +L_0x18471d0 .delay 1 (20000,20000,20000) L_0x18471d0/d; +L_0x18472e0/d .functor NOR 1, L_0x1846610, L_0x18466b0, C4<0>, C4<0>; +L_0x18472e0 .delay 1 (10000,10000,10000) L_0x18472e0/d; +L_0x1847440/d .functor XOR 1, v0x17dbbc0_0, L_0x18472e0, C4<0>, C4<0>; +L_0x1847440 .delay 1 (20000,20000,20000) L_0x1847440/d; +v0x17927f0_0 .net "ALUout", 0 0, L_0x184ba80; 1 drivers +v0x17928b0_0 .net "Cin", 0 0, L_0x184bcf0; 1 drivers +v0x1792970_0 .net "Cout", 0 0, L_0x1846d60; 1 drivers +v0x1792a40_0 .net *"_s11", 0 0, L_0x1847440; 1 drivers +o0x7fc2cd926318 .functor BUFZ 1, C4; HiZ drive +; Elide local net with no drivers, v0x1792ae0_0 name=_s15 +o0x7fc2cd926348 .functor BUFZ 3, C4; HiZ drive +; Elide local net with no drivers, v0x1792bd0_0 name=_s17 +v0x1792cb0_0 .net *"_s3", 0 0, L_0x1846f10; 1 drivers +v0x1792d90_0 .net *"_s7", 0 0, L_0x18471d0; 1 drivers +v0x1792e70_0 .net "addr", 2 0, v0x17dbc90_0; alias, 1 drivers +v0x1792fc0_0 .net "bit1", 0 0, L_0x1846610; 1 drivers +v0x1793060_0 .net "bit2", 0 0, L_0x18466b0; 1 drivers +v0x1793130_0 .net "invertB", 0 0, v0x17dbbc0_0; alias, 1 drivers +v0x17931d0_0 .net "nanded", 0 0, L_0x1847070; 1 drivers +v0x1793270_0 .net "nored", 0 0, L_0x18472e0; 1 drivers +v0x1793310_0 .net "out", 7 0, L_0x1893b50; 1 drivers +LS_0x1893b50_0_0 .concat [ 1 1 1 1], L_0x18468f0, L_0x1846f10, o0x7fc2cd926318, L_0x18471d0; +LS_0x1893b50_0_4 .concat [ 1 3 0 0], L_0x1847440, o0x7fc2cd926348; +L_0x1893b50 .concat [ 4 4 0 0], LS_0x1893b50_0_0, LS_0x1893b50_0_4; +S_0x178d2b0 .scope module, "opmux" "structuralMultiplexer" 3 43, 4 21 0, S_0x178d020; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 3 "address" + .port_info 2 /INPUT 8 "in" +v0x1791790_0 .net "address", 2 0, v0x17dbc90_0; alias, 1 drivers +v0x1791850_0 .net "in", 7 0, L_0x1893b50; alias, 1 drivers +v0x1791930_0 .net "mux", 3 0, L_0x1849af0; 1 drivers +v0x17919f0_0 .net "muxmid", 1 0, L_0x184b0b0; 1 drivers +v0x1791ab0_0 .net "out", 0 0, L_0x184ba80; alias, 1 drivers +L_0x1847d40 .part v0x17dbc90_0, 0, 1; +L_0x1847ea0 .part L_0x1893b50, 0, 2; +L_0x1848780 .part v0x17dbc90_0, 0, 1; +L_0x18488e0 .part L_0x1893b50, 2, 2; +L_0x18490e0 .part v0x17dbc90_0, 0, 1; +L_0x1849240 .part L_0x1893b50, 4, 2; +L_0x1849af0 .concat8 [ 1 1 1 1], L_0x1847be0, L_0x1848620, L_0x1848a70, L_0x1849990; +L_0x1849d40 .part v0x17dbc90_0, 0, 1; +L_0x1849e30 .part L_0x1893b50, 6, 2; +L_0x184a6c0 .part v0x17dbc90_0, 1, 1; +L_0x184a820 .part L_0x1849af0, 0, 2; +L_0x184b0b0 .concat8 [ 1 1 0 0], L_0x184a560, L_0x184af50; +L_0x184b2b0 .part v0x17dbc90_0, 1, 1; +L_0x184b350 .part L_0x1849af0, 2, 2; +L_0x184bb90 .part v0x17dbc90_0, 2, 1; +S_0x178d520 .scope module, "mux_0" "bitMultiplexer" 4 29, 4 8 0, S_0x178d2b0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "addr" + .port_info 2 /INPUT 2 "in" +L_0x1847550/d .functor NOT 1, L_0x1847d40, C4<0>, C4<0>, C4<0>; +L_0x1847550 .delay 1 (10000,10000,10000) L_0x1847550/d; +L_0x18476b0/d .functor AND 1, L_0x18477c0, L_0x1847550, C4<1>, C4<1>; +L_0x18476b0 .delay 1 (20000,20000,20000) L_0x18476b0/d; +L_0x1847920/d .functor AND 1, L_0x1847a30, L_0x1847d40, C4<1>, C4<1>; +L_0x1847920 .delay 1 (20000,20000,20000) L_0x1847920/d; +L_0x1847be0/d .functor OR 1, L_0x18476b0, L_0x1847920, C4<0>, C4<0>; +L_0x1847be0 .delay 1 (20000,20000,20000) L_0x1847be0/d; +v0x178d790_0 .net *"_s1", 0 0, L_0x18477c0; 1 drivers +v0x178d890_0 .net *"_s3", 0 0, L_0x1847a30; 1 drivers +v0x178d970_0 .net "addr", 0 0, L_0x1847d40; 1 drivers +v0x178da40_0 .net "in", 1 0, L_0x1847ea0; 1 drivers +v0x178db20_0 .net "naddr", 0 0, L_0x1847550; 1 drivers +v0x178dc30_0 .net "o0", 0 0, L_0x18476b0; 1 drivers +v0x178dcf0_0 .net "o1", 0 0, L_0x1847920; 1 drivers +v0x178ddb0_0 .net "out", 0 0, L_0x1847be0; 1 drivers +L_0x18477c0 .part L_0x1847ea0, 0, 1; +L_0x1847a30 .part L_0x1847ea0, 1, 1; +S_0x178def0 .scope module, "mux_1" "bitMultiplexer" 4 30, 4 8 0, S_0x178d2b0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "addr" + .port_info 2 /INPUT 2 "in" +L_0x1847f40/d .functor NOT 1, L_0x1848780, C4<0>, C4<0>, C4<0>; +L_0x1847f40 .delay 1 (10000,10000,10000) L_0x1847f40/d; +L_0x1848000/d .functor AND 1, L_0x1848200, L_0x1847f40, C4<1>, C4<1>; +L_0x1848000 .delay 1 (20000,20000,20000) L_0x1848000/d; +L_0x1848360/d .functor AND 1, L_0x1848470, L_0x1848780, C4<1>, C4<1>; +L_0x1848360 .delay 1 (20000,20000,20000) L_0x1848360/d; +L_0x1848620/d .functor OR 1, L_0x1848000, L_0x1848360, C4<0>, C4<0>; +L_0x1848620 .delay 1 (20000,20000,20000) L_0x1848620/d; +v0x178e120_0 .net *"_s1", 0 0, L_0x1848200; 1 drivers +v0x178e220_0 .net *"_s3", 0 0, L_0x1848470; 1 drivers +v0x178e300_0 .net "addr", 0 0, L_0x1848780; 1 drivers +v0x178e3a0_0 .net "in", 1 0, L_0x18488e0; 1 drivers +v0x178e480_0 .net "naddr", 0 0, L_0x1847f40; 1 drivers +v0x178e590_0 .net "o0", 0 0, L_0x1848000; 1 drivers +v0x178e650_0 .net "o1", 0 0, L_0x1848360; 1 drivers +v0x178e710_0 .net "out", 0 0, L_0x1848620; 1 drivers +L_0x1848200 .part L_0x18488e0, 0, 1; +L_0x1848470 .part L_0x18488e0, 1, 1; +S_0x178e850 .scope module, "mux_2" "bitMultiplexer" 4 31, 4 8 0, S_0x178d2b0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "addr" + .port_info 2 /INPUT 2 "in" +L_0x1848820/d .functor NOT 1, L_0x18490e0, C4<0>, C4<0>, C4<0>; +L_0x1848820 .delay 1 (10000,10000,10000) L_0x1848820/d; +L_0x18489d0/d .functor AND 1, L_0x1848bd0, L_0x1848820, C4<1>, C4<1>; +L_0x18489d0 .delay 1 (20000,20000,20000) L_0x18489d0/d; +L_0x1848d30/d .functor AND 1, L_0x1848e40, L_0x18490e0, C4<1>, C4<1>; +L_0x1848d30 .delay 1 (20000,20000,20000) L_0x1848d30/d; +L_0x1848a70/d .functor OR 1, L_0x18489d0, L_0x1848d30, C4<0>, C4<0>; +L_0x1848a70 .delay 1 (20000,20000,20000) L_0x1848a70/d; +v0x178ea80_0 .net *"_s1", 0 0, L_0x1848bd0; 1 drivers +v0x178eb60_0 .net *"_s3", 0 0, L_0x1848e40; 1 drivers +v0x178ec40_0 .net "addr", 0 0, L_0x18490e0; 1 drivers +v0x178ed10_0 .net "in", 1 0, L_0x1849240; 1 drivers +v0x178edf0_0 .net "naddr", 0 0, L_0x1848820; 1 drivers +v0x178ef00_0 .net "o0", 0 0, L_0x18489d0; 1 drivers +v0x178efc0_0 .net "o1", 0 0, L_0x1848d30; 1 drivers +v0x178f080_0 .net "out", 0 0, L_0x1848a70; 1 drivers +L_0x1848bd0 .part L_0x1849240, 0, 1; +L_0x1848e40 .part L_0x1849240, 1, 1; +S_0x178f1c0 .scope module, "mux_3" "bitMultiplexer" 4 32, 4 8 0, S_0x178d2b0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "addr" + .port_info 2 /INPUT 2 "in" +L_0x1849180/d .functor NOT 1, L_0x1849d40, C4<0>, C4<0>, C4<0>; +L_0x1849180 .delay 1 (10000,10000,10000) L_0x1849180/d; +L_0x1849370/d .functor AND 1, L_0x1849570, L_0x1849180, C4<1>, C4<1>; +L_0x1849370 .delay 1 (20000,20000,20000) L_0x1849370/d; +L_0x18496d0/d .functor AND 1, L_0x18497e0, L_0x1849d40, C4<1>, C4<1>; +L_0x18496d0 .delay 1 (20000,20000,20000) L_0x18496d0/d; +L_0x1849990/d .functor OR 1, L_0x1849370, L_0x18496d0, C4<0>, C4<0>; +L_0x1849990 .delay 1 (20000,20000,20000) L_0x1849990/d; +v0x178f3f0_0 .net *"_s1", 0 0, L_0x1849570; 1 drivers +v0x178f4f0_0 .net *"_s3", 0 0, L_0x18497e0; 1 drivers +v0x178f5d0_0 .net "addr", 0 0, L_0x1849d40; 1 drivers +v0x178f670_0 .net "in", 1 0, L_0x1849e30; 1 drivers +v0x178f750_0 .net "naddr", 0 0, L_0x1849180; 1 drivers +v0x178f860_0 .net "o0", 0 0, L_0x1849370; 1 drivers +v0x178f920_0 .net "o1", 0 0, L_0x18496d0; 1 drivers +v0x178f9e0_0 .net "out", 0 0, L_0x1849990; 1 drivers +L_0x1849570 .part L_0x1849e30, 0, 1; +L_0x18497e0 .part L_0x1849e30, 1, 1; +S_0x178fb20 .scope module, "mux_mid_0" "bitMultiplexer" 4 33, 4 8 0, S_0x178d2b0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "addr" + .port_info 2 /INPUT 2 "in" +L_0x1849ed0/d .functor NOT 1, L_0x184a6c0, C4<0>, C4<0>, C4<0>; +L_0x1849ed0 .delay 1 (10000,10000,10000) L_0x1849ed0/d; +L_0x1849f90/d .functor AND 1, L_0x184a140, L_0x1849ed0, C4<1>, C4<1>; +L_0x1849f90 .delay 1 (20000,20000,20000) L_0x1849f90/d; +L_0x184a2a0/d .functor AND 1, L_0x184a3b0, L_0x184a6c0, C4<1>, C4<1>; +L_0x184a2a0 .delay 1 (20000,20000,20000) L_0x184a2a0/d; +L_0x184a560/d .functor OR 1, L_0x1849f90, L_0x184a2a0, C4<0>, C4<0>; +L_0x184a560 .delay 1 (20000,20000,20000) L_0x184a560/d; +v0x178fda0_0 .net *"_s1", 0 0, L_0x184a140; 1 drivers +v0x178fea0_0 .net *"_s3", 0 0, L_0x184a3b0; 1 drivers +v0x178ff80_0 .net "addr", 0 0, L_0x184a6c0; 1 drivers +v0x1790020_0 .net "in", 1 0, L_0x184a820; 1 drivers +v0x1790100_0 .net "naddr", 0 0, L_0x1849ed0; 1 drivers +v0x1790210_0 .net "o0", 0 0, L_0x1849f90; 1 drivers +v0x17902d0_0 .net "o1", 0 0, L_0x184a2a0; 1 drivers +v0x1790390_0 .net "out", 0 0, L_0x184a560; 1 drivers +L_0x184a140 .part L_0x184a820, 0, 1; +L_0x184a3b0 .part L_0x184a820, 1, 1; +S_0x17904d0 .scope module, "mux_mid_1" "bitMultiplexer" 4 34, 4 8 0, S_0x178d2b0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "addr" + .port_info 2 /INPUT 2 "in" +L_0x184a8c0/d .functor NOT 1, L_0x184b2b0, C4<0>, C4<0>, C4<0>; +L_0x184a8c0 .delay 1 (10000,10000,10000) L_0x184a8c0/d; +L_0x184a980/d .functor AND 1, L_0x184ab30, L_0x184a8c0, C4<1>, C4<1>; +L_0x184a980 .delay 1 (20000,20000,20000) L_0x184a980/d; +L_0x184ac90/d .functor AND 1, L_0x184ada0, L_0x184b2b0, C4<1>, C4<1>; +L_0x184ac90 .delay 1 (20000,20000,20000) L_0x184ac90/d; +L_0x184af50/d .functor OR 1, L_0x184a980, L_0x184ac90, C4<0>, C4<0>; +L_0x184af50 .delay 1 (20000,20000,20000) L_0x184af50/d; +v0x1790700_0 .net *"_s1", 0 0, L_0x184ab30; 1 drivers +v0x1790800_0 .net *"_s3", 0 0, L_0x184ada0; 1 drivers +v0x17908e0_0 .net "addr", 0 0, L_0x184b2b0; 1 drivers +v0x1790980_0 .net "in", 1 0, L_0x184b350; 1 drivers +v0x1790a60_0 .net "naddr", 0 0, L_0x184a8c0; 1 drivers +v0x1790b70_0 .net "o0", 0 0, L_0x184a980; 1 drivers +v0x1790c30_0 .net "o1", 0 0, L_0x184ac90; 1 drivers +v0x1790cf0_0 .net "out", 0 0, L_0x184af50; 1 drivers +L_0x184ab30 .part L_0x184b350, 0, 1; +L_0x184ada0 .part L_0x184b350, 1, 1; +S_0x1790e30 .scope module, "mux_out" "bitMultiplexer" 4 35, 4 8 0, S_0x178d2b0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "addr" + .port_info 2 /INPUT 2 "in" +L_0x184a760/d .functor NOT 1, L_0x184bb90, C4<0>, C4<0>, C4<0>; +L_0x184a760 .delay 1 (10000,10000,10000) L_0x184a760/d; +L_0x184b4c0/d .functor AND 1, L_0x184b620, L_0x184a760, C4<1>, C4<1>; +L_0x184b4c0 .delay 1 (20000,20000,20000) L_0x184b4c0/d; +L_0x184b780/d .functor AND 1, L_0x184b890, L_0x184bb90, C4<1>, C4<1>; +L_0x184b780 .delay 1 (20000,20000,20000) L_0x184b780/d; +L_0x184ba80/d .functor OR 1, L_0x184b4c0, L_0x184b780, C4<0>, C4<0>; +L_0x184ba80 .delay 1 (20000,20000,20000) L_0x184ba80/d; +v0x1791060_0 .net *"_s1", 0 0, L_0x184b620; 1 drivers +v0x1791160_0 .net *"_s3", 0 0, L_0x184b890; 1 drivers +v0x1791240_0 .net "addr", 0 0, L_0x184bb90; 1 drivers +v0x17912e0_0 .net "in", 1 0, L_0x184b0b0; alias, 1 drivers +v0x17913c0_0 .net "naddr", 0 0, L_0x184a760; 1 drivers +v0x17914d0_0 .net "o0", 0 0, L_0x184b4c0; 1 drivers +v0x1791590_0 .net "o1", 0 0, L_0x184b780; 1 drivers +v0x1791650_0 .net "out", 0 0, L_0x184ba80; alias, 1 drivers +L_0x184b620 .part L_0x184b0b0, 0, 1; +L_0x184b890 .part L_0x184b0b0, 1, 1; +S_0x1791be0 .scope module, "structadder" "structAddSub" 3 22, 5 8 0, S_0x178d020; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "sub" + .port_info 5 /INPUT 1 "carryin" +L_0x1846380/d .functor XOR 1, L_0x18466b0, v0x17dbbc0_0, C4<0>, C4<0>; +L_0x1846380 .delay 1 (20000,20000,20000) L_0x1846380/d; +L_0x18467e0/d .functor XOR 1, L_0x1846610, L_0x18466b0, C4<0>, C4<0>; +L_0x18467e0 .delay 1 (20000,20000,20000) L_0x18467e0/d; +L_0x18468f0/d .functor XOR 1, L_0x18467e0, L_0x184bcf0, C4<0>, C4<0>; +L_0x18468f0 .delay 1 (20000,20000,20000) L_0x18468f0/d; +L_0x1846aa0/d .functor AND 1, L_0x1846610, L_0x18466b0, C4<1>, C4<1>; +L_0x1846aa0 .delay 1 (20000,20000,20000) L_0x1846aa0/d; +L_0x1846c00/d .functor AND 1, L_0x18467e0, L_0x184bcf0, C4<1>, C4<1>; +L_0x1846c00 .delay 1 (20000,20000,20000) L_0x1846c00/d; +L_0x1846d60/d .functor OR 1, L_0x1846c00, L_0x1846aa0, C4<0>, C4<0>; +L_0x1846d60 .delay 1 (20000,20000,20000) L_0x1846d60/d; +v0x1791ea0_0 .net "AandB", 0 0, L_0x1846aa0; 1 drivers +v0x1791f60_0 .net "AxorB", 0 0, L_0x18467e0; 1 drivers +v0x1792020_0 .net "AxorBandCarryIn", 0 0, L_0x1846c00; 1 drivers +v0x17920f0_0 .net "a", 0 0, L_0x1846610; alias, 1 drivers +v0x17921b0_0 .net "b", 0 0, L_0x18466b0; alias, 1 drivers +v0x17922c0_0 .net "bnew", 0 0, L_0x1846380; 1 drivers +v0x1792380_0 .net "carryin", 0 0, L_0x184bcf0; alias, 1 drivers +v0x1792440_0 .net "carryout", 0 0, L_0x1846d60; alias, 1 drivers +v0x1792500_0 .net "sub", 0 0, v0x17dbbc0_0; alias, 1 drivers +v0x1792630_0 .net "sum", 0 0, L_0x18468f0; 1 drivers +S_0x17934c0 .scope generate, "ripple[21]" "ripple[21]" 3 66, 3 66 0, S_0x16fa6c0; + .timescale -9 -12; +P_0x1793690 .param/l "i" 0 3 66, +C4<010101>; +S_0x1793750 .scope module, "bit" "BitSliceALU" 3 68, 3 11 0, S_0x17934c0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "ALUout" + .port_info 1 /OUTPUT 1 "Cout" + .port_info 2 /INPUT 1 "invertB" + .port_info 3 /INPUT 1 "Cin" + .port_info 4 /INPUT 3 "addr" + .port_info 5 /INPUT 1 "bit1" + .port_info 6 /INPUT 1 "bit2" +L_0x184c810/d .functor XOR 1, L_0x1851f10, L_0x184c110, C4<0>, C4<0>; +L_0x184c810 .delay 1 (20000,20000,20000) L_0x184c810/d; +L_0x184c970/d .functor NAND 1, L_0x1851f10, L_0x184c110, C4<1>, C4<1>; +L_0x184c970 .delay 1 (10000,10000,10000) L_0x184c970/d; +L_0x184cad0/d .functor XOR 1, v0x17dbbc0_0, L_0x184c970, C4<0>, C4<0>; +L_0x184cad0 .delay 1 (20000,20000,20000) L_0x184cad0/d; +L_0x17da980/d .functor NOR 1, L_0x1851f10, L_0x184c110, C4<0>, C4<0>; +L_0x17da980 .delay 1 (10000,10000,10000) L_0x17da980/d; +L_0x17daae0/d .functor XOR 1, v0x17dbbc0_0, L_0x17da980, C4<0>, C4<0>; +L_0x17daae0 .delay 1 (20000,20000,20000) L_0x17daae0/d; +v0x1798f20_0 .net "ALUout", 0 0, L_0x1851b70; 1 drivers +v0x1798fe0_0 .net "Cin", 0 0, L_0x1851de0; 1 drivers +v0x17990a0_0 .net "Cout", 0 0, L_0x184c660; 1 drivers +v0x1799170_0 .net *"_s11", 0 0, L_0x17daae0; 1 drivers +o0x7fc2cd9277e8 .functor BUFZ 1, C4; HiZ drive +; Elide local net with no drivers, v0x1799210_0 name=_s15 +o0x7fc2cd927818 .functor BUFZ 3, C4; HiZ drive +; Elide local net with no drivers, v0x1799300_0 name=_s17 +v0x17993e0_0 .net *"_s3", 0 0, L_0x184c810; 1 drivers +v0x17994c0_0 .net *"_s7", 0 0, L_0x184cad0; 1 drivers +v0x17995a0_0 .net "addr", 2 0, v0x17dbc90_0; alias, 1 drivers +v0x17996f0_0 .net "bit1", 0 0, L_0x1851f10; 1 drivers +v0x1799790_0 .net "bit2", 0 0, L_0x184c110; 1 drivers +v0x1799860_0 .net "invertB", 0 0, v0x17dbbc0_0; alias, 1 drivers +v0x1799900_0 .net "nanded", 0 0, L_0x184c970; 1 drivers +v0x17999a0_0 .net "nored", 0 0, L_0x17da980; 1 drivers +v0x1799a40_0 .net "out", 7 0, L_0x1893d30; 1 drivers +LS_0x1893d30_0_0 .concat [ 1 1 1 1], L_0x184be20, L_0x184c810, o0x7fc2cd9277e8, L_0x184cad0; +LS_0x1893d30_0_4 .concat [ 1 3 0 0], L_0x17daae0, o0x7fc2cd927818; +L_0x1893d30 .concat [ 4 4 0 0], LS_0x1893d30_0_0, LS_0x1893d30_0_4; +S_0x17939e0 .scope module, "opmux" "structuralMultiplexer" 3 43, 4 21 0, S_0x1793750; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 3 "address" + .port_info 2 /INPUT 8 "in" +v0x1797ec0_0 .net "address", 2 0, v0x17dbc90_0; alias, 1 drivers +v0x1797f80_0 .net "in", 7 0, L_0x1893d30; alias, 1 drivers +v0x1798060_0 .net "mux", 3 0, L_0x184fc30; 1 drivers +v0x1798120_0 .net "muxmid", 1 0, L_0x18511a0; 1 drivers +v0x17981e0_0 .net "out", 0 0, L_0x1851b70; alias, 1 drivers +L_0x184deb0 .part v0x17dbc90_0, 0, 1; +L_0x184e010 .part L_0x1893d30, 0, 2; +L_0x184e850 .part v0x17dbc90_0, 0, 1; +L_0x184e9b0 .part L_0x1893d30, 2, 2; +L_0x184f220 .part v0x17dbc90_0, 0, 1; +L_0x184f380 .part L_0x1893d30, 4, 2; +L_0x184fc30 .concat8 [ 1 1 1 1], L_0x184dd50, L_0x184e6f0, L_0x184f0c0, L_0x184fad0; +L_0x184fe80 .part v0x17dbc90_0, 0, 1; +L_0x184ff70 .part L_0x1893d30, 6, 2; +L_0x18507b0 .part v0x17dbc90_0, 1, 1; +L_0x1850910 .part L_0x184fc30, 0, 2; +L_0x18511a0 .concat8 [ 1 1 0 0], L_0x1850650, L_0x1851040; +L_0x18513a0 .part v0x17dbc90_0, 1, 1; +L_0x1851440 .part L_0x184fc30, 2, 2; +L_0x1851c80 .part v0x17dbc90_0, 2, 1; +S_0x1793c50 .scope module, "mux_0" "bitMultiplexer" 4 29, 4 8 0, S_0x17939e0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "addr" + .port_info 2 /INPUT 2 "in" +L_0x17dabf0/d .functor NOT 1, L_0x184deb0, C4<0>, C4<0>, C4<0>; +L_0x17dabf0 .delay 1 (10000,10000,10000) L_0x17dabf0/d; +L_0x17dad50/d .functor AND 1, L_0x17db020, L_0x17dabf0, C4<1>, C4<1>; +L_0x17dad50 .delay 1 (20000,20000,20000) L_0x17dad50/d; +L_0x17daf10/d .functor AND 1, L_0x184dba0, L_0x184deb0, C4<1>, C4<1>; +L_0x17daf10 .delay 1 (20000,20000,20000) L_0x17daf10/d; +L_0x184dd50/d .functor OR 1, L_0x17dad50, L_0x17daf10, C4<0>, C4<0>; +L_0x184dd50 .delay 1 (20000,20000,20000) L_0x184dd50/d; +v0x1793ec0_0 .net *"_s1", 0 0, L_0x17db020; 1 drivers +v0x1793fc0_0 .net *"_s3", 0 0, L_0x184dba0; 1 drivers +v0x17940a0_0 .net "addr", 0 0, L_0x184deb0; 1 drivers +v0x1794170_0 .net "in", 1 0, L_0x184e010; 1 drivers +v0x1794250_0 .net "naddr", 0 0, L_0x17dabf0; 1 drivers +v0x1794360_0 .net "o0", 0 0, L_0x17dad50; 1 drivers +v0x1794420_0 .net "o1", 0 0, L_0x17daf10; 1 drivers +v0x17944e0_0 .net "out", 0 0, L_0x184dd50; 1 drivers +L_0x17db020 .part L_0x184e010, 0, 1; +L_0x184dba0 .part L_0x184e010, 1, 1; +S_0x1794620 .scope module, "mux_1" "bitMultiplexer" 4 30, 4 8 0, S_0x17939e0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "addr" + .port_info 2 /INPUT 2 "in" +L_0x184e0b0/d .functor NOT 1, L_0x184e850, C4<0>, C4<0>, C4<0>; +L_0x184e0b0 .delay 1 (10000,10000,10000) L_0x184e0b0/d; +L_0x184e170/d .functor AND 1, L_0x184e2d0, L_0x184e0b0, C4<1>, C4<1>; +L_0x184e170 .delay 1 (20000,20000,20000) L_0x184e170/d; +L_0x184e430/d .functor AND 1, L_0x184e540, L_0x184e850, C4<1>, C4<1>; +L_0x184e430 .delay 1 (20000,20000,20000) L_0x184e430/d; +L_0x184e6f0/d .functor OR 1, L_0x184e170, L_0x184e430, C4<0>, C4<0>; +L_0x184e6f0 .delay 1 (20000,20000,20000) L_0x184e6f0/d; +v0x1794850_0 .net *"_s1", 0 0, L_0x184e2d0; 1 drivers +v0x1794950_0 .net *"_s3", 0 0, L_0x184e540; 1 drivers +v0x1794a30_0 .net "addr", 0 0, L_0x184e850; 1 drivers +v0x1794ad0_0 .net "in", 1 0, L_0x184e9b0; 1 drivers +v0x1794bb0_0 .net "naddr", 0 0, L_0x184e0b0; 1 drivers +v0x1794cc0_0 .net "o0", 0 0, L_0x184e170; 1 drivers +v0x1794d80_0 .net "o1", 0 0, L_0x184e430; 1 drivers +v0x1794e40_0 .net "out", 0 0, L_0x184e6f0; 1 drivers +L_0x184e2d0 .part L_0x184e9b0, 0, 1; +L_0x184e540 .part L_0x184e9b0, 1, 1; +S_0x1794f80 .scope module, "mux_2" "bitMultiplexer" 4 31, 4 8 0, S_0x17939e0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "addr" + .port_info 2 /INPUT 2 "in" +L_0x184e8f0/d .functor NOT 1, L_0x184f220, C4<0>, C4<0>, C4<0>; +L_0x184e8f0 .delay 1 (10000,10000,10000) L_0x184e8f0/d; +L_0x184eaa0/d .functor AND 1, L_0x184eca0, L_0x184e8f0, C4<1>, C4<1>; +L_0x184eaa0 .delay 1 (20000,20000,20000) L_0x184eaa0/d; +L_0x184ee00/d .functor AND 1, L_0x184ef10, L_0x184f220, C4<1>, C4<1>; +L_0x184ee00 .delay 1 (20000,20000,20000) L_0x184ee00/d; +L_0x184f0c0/d .functor OR 1, L_0x184eaa0, L_0x184ee00, C4<0>, C4<0>; +L_0x184f0c0 .delay 1 (20000,20000,20000) L_0x184f0c0/d; +v0x17951b0_0 .net *"_s1", 0 0, L_0x184eca0; 1 drivers +v0x1795290_0 .net *"_s3", 0 0, L_0x184ef10; 1 drivers +v0x1795370_0 .net "addr", 0 0, L_0x184f220; 1 drivers +v0x1795440_0 .net "in", 1 0, L_0x184f380; 1 drivers +v0x1795520_0 .net "naddr", 0 0, L_0x184e8f0; 1 drivers +v0x1795630_0 .net "o0", 0 0, L_0x184eaa0; 1 drivers +v0x17956f0_0 .net "o1", 0 0, L_0x184ee00; 1 drivers +v0x17957b0_0 .net "out", 0 0, L_0x184f0c0; 1 drivers +L_0x184eca0 .part L_0x184f380, 0, 1; +L_0x184ef10 .part L_0x184f380, 1, 1; +S_0x17958f0 .scope module, "mux_3" "bitMultiplexer" 4 32, 4 8 0, S_0x17939e0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "addr" + .port_info 2 /INPUT 2 "in" +L_0x184f2c0/d .functor NOT 1, L_0x184fe80, C4<0>, C4<0>, C4<0>; +L_0x184f2c0 .delay 1 (10000,10000,10000) L_0x184f2c0/d; +L_0x184f4b0/d .functor AND 1, L_0x184f6b0, L_0x184f2c0, C4<1>, C4<1>; +L_0x184f4b0 .delay 1 (20000,20000,20000) L_0x184f4b0/d; +L_0x184f810/d .functor AND 1, L_0x184f920, L_0x184fe80, C4<1>, C4<1>; +L_0x184f810 .delay 1 (20000,20000,20000) L_0x184f810/d; +L_0x184fad0/d .functor OR 1, L_0x184f4b0, L_0x184f810, C4<0>, C4<0>; +L_0x184fad0 .delay 1 (20000,20000,20000) L_0x184fad0/d; +v0x1795b20_0 .net *"_s1", 0 0, L_0x184f6b0; 1 drivers +v0x1795c20_0 .net *"_s3", 0 0, L_0x184f920; 1 drivers +v0x1795d00_0 .net "addr", 0 0, L_0x184fe80; 1 drivers +v0x1795da0_0 .net "in", 1 0, L_0x184ff70; 1 drivers +v0x1795e80_0 .net "naddr", 0 0, L_0x184f2c0; 1 drivers +v0x1795f90_0 .net "o0", 0 0, L_0x184f4b0; 1 drivers +v0x1796050_0 .net "o1", 0 0, L_0x184f810; 1 drivers +v0x1796110_0 .net "out", 0 0, L_0x184fad0; 1 drivers +L_0x184f6b0 .part L_0x184ff70, 0, 1; +L_0x184f920 .part L_0x184ff70, 1, 1; +S_0x1796250 .scope module, "mux_mid_0" "bitMultiplexer" 4 33, 4 8 0, S_0x17939e0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "addr" + .port_info 2 /INPUT 2 "in" +L_0x1850010/d .functor NOT 1, L_0x18507b0, C4<0>, C4<0>, C4<0>; +L_0x1850010 .delay 1 (10000,10000,10000) L_0x1850010/d; +L_0x18500d0/d .functor AND 1, L_0x1850230, L_0x1850010, C4<1>, C4<1>; +L_0x18500d0 .delay 1 (20000,20000,20000) L_0x18500d0/d; +L_0x1850390/d .functor AND 1, L_0x18504a0, L_0x18507b0, C4<1>, C4<1>; +L_0x1850390 .delay 1 (20000,20000,20000) L_0x1850390/d; +L_0x1850650/d .functor OR 1, L_0x18500d0, L_0x1850390, C4<0>, C4<0>; +L_0x1850650 .delay 1 (20000,20000,20000) L_0x1850650/d; +v0x17964d0_0 .net *"_s1", 0 0, L_0x1850230; 1 drivers +v0x17965d0_0 .net *"_s3", 0 0, L_0x18504a0; 1 drivers +v0x17966b0_0 .net "addr", 0 0, L_0x18507b0; 1 drivers +v0x1796750_0 .net "in", 1 0, L_0x1850910; 1 drivers +v0x1796830_0 .net "naddr", 0 0, L_0x1850010; 1 drivers +v0x1796940_0 .net "o0", 0 0, L_0x18500d0; 1 drivers +v0x1796a00_0 .net "o1", 0 0, L_0x1850390; 1 drivers +v0x1796ac0_0 .net "out", 0 0, L_0x1850650; 1 drivers +L_0x1850230 .part L_0x1850910, 0, 1; +L_0x18504a0 .part L_0x1850910, 1, 1; +S_0x1796c00 .scope module, "mux_mid_1" "bitMultiplexer" 4 34, 4 8 0, S_0x17939e0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "addr" + .port_info 2 /INPUT 2 "in" +L_0x18509b0/d .functor NOT 1, L_0x18513a0, C4<0>, C4<0>, C4<0>; +L_0x18509b0 .delay 1 (10000,10000,10000) L_0x18509b0/d; +L_0x1850a70/d .functor AND 1, L_0x1850c20, L_0x18509b0, C4<1>, C4<1>; +L_0x1850a70 .delay 1 (20000,20000,20000) L_0x1850a70/d; +L_0x1850d80/d .functor AND 1, L_0x1850e90, L_0x18513a0, C4<1>, C4<1>; +L_0x1850d80 .delay 1 (20000,20000,20000) L_0x1850d80/d; +L_0x1851040/d .functor OR 1, L_0x1850a70, L_0x1850d80, C4<0>, C4<0>; +L_0x1851040 .delay 1 (20000,20000,20000) L_0x1851040/d; +v0x1796e30_0 .net *"_s1", 0 0, L_0x1850c20; 1 drivers +v0x1796f30_0 .net *"_s3", 0 0, L_0x1850e90; 1 drivers +v0x1797010_0 .net "addr", 0 0, L_0x18513a0; 1 drivers +v0x17970b0_0 .net "in", 1 0, L_0x1851440; 1 drivers +v0x1797190_0 .net "naddr", 0 0, L_0x18509b0; 1 drivers +v0x17972a0_0 .net "o0", 0 0, L_0x1850a70; 1 drivers +v0x1797360_0 .net "o1", 0 0, L_0x1850d80; 1 drivers +v0x1797420_0 .net "out", 0 0, L_0x1851040; 1 drivers +L_0x1850c20 .part L_0x1851440, 0, 1; +L_0x1850e90 .part L_0x1851440, 1, 1; +S_0x1797560 .scope module, "mux_out" "bitMultiplexer" 4 35, 4 8 0, S_0x17939e0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "addr" + .port_info 2 /INPUT 2 "in" +L_0x1850850/d .functor NOT 1, L_0x1851c80, C4<0>, C4<0>, C4<0>; +L_0x1850850 .delay 1 (10000,10000,10000) L_0x1850850/d; +L_0x18515b0/d .functor AND 1, L_0x1851710, L_0x1850850, C4<1>, C4<1>; +L_0x18515b0 .delay 1 (20000,20000,20000) L_0x18515b0/d; +L_0x1851870/d .functor AND 1, L_0x1851980, L_0x1851c80, C4<1>, C4<1>; +L_0x1851870 .delay 1 (20000,20000,20000) L_0x1851870/d; +L_0x1851b70/d .functor OR 1, L_0x18515b0, L_0x1851870, C4<0>, C4<0>; +L_0x1851b70 .delay 1 (20000,20000,20000) L_0x1851b70/d; +v0x1797790_0 .net *"_s1", 0 0, L_0x1851710; 1 drivers +v0x1797890_0 .net *"_s3", 0 0, L_0x1851980; 1 drivers +v0x1797970_0 .net "addr", 0 0, L_0x1851c80; 1 drivers +v0x1797a10_0 .net "in", 1 0, L_0x18511a0; alias, 1 drivers +v0x1797af0_0 .net "naddr", 0 0, L_0x1850850; 1 drivers +v0x1797c00_0 .net "o0", 0 0, L_0x18515b0; 1 drivers +v0x1797cc0_0 .net "o1", 0 0, L_0x1851870; 1 drivers +v0x1797d80_0 .net "out", 0 0, L_0x1851b70; alias, 1 drivers +L_0x1851710 .part L_0x18511a0, 0, 1; +L_0x1851980 .part L_0x18511a0, 1, 1; +S_0x1798310 .scope module, "structadder" "structAddSub" 3 22, 5 8 0, S_0x1793750; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "sub" + .port_info 5 /INPUT 1 "carryin" +L_0x184bc30/d .functor XOR 1, L_0x184c110, v0x17dbbc0_0, C4<0>, C4<0>; +L_0x184bc30 .delay 1 (20000,20000,20000) L_0x184bc30/d; +L_0x184bf80/d .functor XOR 1, L_0x1851f10, L_0x184c110, C4<0>, C4<0>; +L_0x184bf80 .delay 1 (20000,20000,20000) L_0x184bf80/d; +L_0x184be20/d .functor XOR 1, L_0x184bf80, L_0x1851de0, C4<0>, C4<0>; +L_0x184be20 .delay 1 (20000,20000,20000) L_0x184be20/d; +L_0x184c3a0/d .functor AND 1, L_0x1851f10, L_0x184c110, C4<1>, C4<1>; +L_0x184c3a0 .delay 1 (20000,20000,20000) L_0x184c3a0/d; +L_0x184c500/d .functor AND 1, L_0x184bf80, L_0x1851de0, C4<1>, C4<1>; +L_0x184c500 .delay 1 (20000,20000,20000) L_0x184c500/d; +L_0x184c660/d .functor OR 1, L_0x184c500, L_0x184c3a0, C4<0>, C4<0>; +L_0x184c660 .delay 1 (20000,20000,20000) L_0x184c660/d; +v0x17985d0_0 .net "AandB", 0 0, L_0x184c3a0; 1 drivers +v0x1798690_0 .net "AxorB", 0 0, L_0x184bf80; 1 drivers +v0x1798750_0 .net "AxorBandCarryIn", 0 0, L_0x184c500; 1 drivers +v0x1798820_0 .net "a", 0 0, L_0x1851f10; alias, 1 drivers +v0x17988e0_0 .net "b", 0 0, L_0x184c110; alias, 1 drivers +v0x17989f0_0 .net "bnew", 0 0, L_0x184bc30; 1 drivers +v0x1798ab0_0 .net "carryin", 0 0, L_0x1851de0; alias, 1 drivers +v0x1798b70_0 .net "carryout", 0 0, L_0x184c660; alias, 1 drivers +v0x1798c30_0 .net "sub", 0 0, v0x17dbbc0_0; alias, 1 drivers +v0x1798d60_0 .net "sum", 0 0, L_0x184be20; 1 drivers +S_0x1799bf0 .scope generate, "ripple[22]" "ripple[22]" 3 66, 3 66 0, S_0x16fa6c0; + .timescale -9 -12; +P_0x1799dc0 .param/l "i" 0 3 66, +C4<010110>; +S_0x1799e80 .scope module, "bit" "BitSliceALU" 3 68, 3 11 0, S_0x1799bf0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "ALUout" + .port_info 1 /OUTPUT 1 "Cout" + .port_info 2 /INPUT 1 "invertB" + .port_info 3 /INPUT 1 "Cin" + .port_info 4 /INPUT 3 "addr" + .port_info 5 /INPUT 1 "bit1" + .port_info 6 /INPUT 1 "bit2" +L_0x18528e0/d .functor XOR 1, L_0x1851fb0, L_0x1852050, C4<0>, C4<0>; +L_0x18528e0 .delay 1 (20000,20000,20000) L_0x18528e0/d; +L_0x1852a40/d .functor NAND 1, L_0x1851fb0, L_0x1852050, C4<1>, C4<1>; +L_0x1852a40 .delay 1 (10000,10000,10000) L_0x1852a40/d; +L_0x1852ba0/d .functor XOR 1, v0x17dbbc0_0, L_0x1852a40, C4<0>, C4<0>; +L_0x1852ba0 .delay 1 (20000,20000,20000) L_0x1852ba0/d; +L_0x1852cb0/d .functor NOR 1, L_0x1851fb0, L_0x1852050, C4<0>, C4<0>; +L_0x1852cb0 .delay 1 (10000,10000,10000) L_0x1852cb0/d; +L_0x1852e10/d .functor XOR 1, v0x17dbbc0_0, L_0x1852cb0, C4<0>, C4<0>; +L_0x1852e10 .delay 1 (20000,20000,20000) L_0x1852e10/d; +v0x179f650_0 .net "ALUout", 0 0, L_0x18574c0; 1 drivers +v0x179f710_0 .net "Cin", 0 0, L_0x1857730; 1 drivers +v0x179f7d0_0 .net "Cout", 0 0, L_0x1852730; 1 drivers +v0x179f8a0_0 .net *"_s11", 0 0, L_0x1852e10; 1 drivers +o0x7fc2cd928cb8 .functor BUFZ 1, C4; HiZ drive +; Elide local net with no drivers, v0x179f940_0 name=_s15 +o0x7fc2cd928ce8 .functor BUFZ 3, C4; HiZ drive +; Elide local net with no drivers, v0x179fa30_0 name=_s17 +v0x179fb10_0 .net *"_s3", 0 0, L_0x18528e0; 1 drivers +v0x179fbf0_0 .net *"_s7", 0 0, L_0x1852ba0; 1 drivers +v0x179fcd0_0 .net "addr", 2 0, v0x17dbc90_0; alias, 1 drivers +v0x179fe20_0 .net "bit1", 0 0, L_0x1851fb0; 1 drivers +v0x179fec0_0 .net "bit2", 0 0, L_0x1852050; 1 drivers +v0x179ff90_0 .net "invertB", 0 0, v0x17dbbc0_0; alias, 1 drivers +v0x17a0030_0 .net "nanded", 0 0, L_0x1852a40; 1 drivers +v0x17a00d0_0 .net "nored", 0 0, L_0x1852cb0; 1 drivers +v0x17a0170_0 .net "out", 7 0, L_0x1893f10; 1 drivers +LS_0x1893f10_0_0 .concat [ 1 1 1 1], L_0x18522c0, L_0x18528e0, o0x7fc2cd928cb8, L_0x1852ba0; +LS_0x1893f10_0_4 .concat [ 1 3 0 0], L_0x1852e10, o0x7fc2cd928ce8; +L_0x1893f10 .concat [ 4 4 0 0], LS_0x1893f10_0_0, LS_0x1893f10_0_4; +S_0x179a110 .scope module, "opmux" "structuralMultiplexer" 3 43, 4 21 0, S_0x1799e80; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 3 "address" + .port_info 2 /INPUT 8 "in" +v0x179e5f0_0 .net "address", 2 0, v0x17dbc90_0; alias, 1 drivers +v0x179e6b0_0 .net "in", 7 0, L_0x1893f10; alias, 1 drivers +v0x179e790_0 .net "mux", 3 0, L_0x1855530; 1 drivers +v0x179e850_0 .net "muxmid", 1 0, L_0x1856af0; 1 drivers +v0x179e910_0 .net "out", 0 0, L_0x18574c0; alias, 1 drivers +L_0x1853710 .part v0x17dbc90_0, 0, 1; +L_0x1853870 .part L_0x1893f10, 0, 2; +L_0x1854150 .part v0x17dbc90_0, 0, 1; +L_0x18542b0 .part L_0x1893f10, 2, 2; +L_0x1854b20 .part v0x17dbc90_0, 0, 1; +L_0x1854c80 .part L_0x1893f10, 4, 2; +L_0x1855530 .concat8 [ 1 1 1 1], L_0x18535b0, L_0x1853ff0, L_0x18549c0, L_0x18553d0; +L_0x18557d0 .part v0x17dbc90_0, 0, 1; +L_0x18558c0 .part L_0x1893f10, 6, 2; +L_0x1856100 .part v0x17dbc90_0, 1, 1; +L_0x1856260 .part L_0x1855530, 0, 2; +L_0x1856af0 .concat8 [ 1 1 0 0], L_0x1855fa0, L_0x1856990; +L_0x1856cf0 .part v0x17dbc90_0, 1, 1; +L_0x1856d90 .part L_0x1855530, 2, 2; +L_0x18575d0 .part v0x17dbc90_0, 2, 1; +S_0x179a380 .scope module, "mux_0" "bitMultiplexer" 4 29, 4 8 0, S_0x179a110; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "addr" + .port_info 2 /INPUT 2 "in" +L_0x1852f20/d .functor NOT 1, L_0x1853710, C4<0>, C4<0>, C4<0>; +L_0x1852f20 .delay 1 (10000,10000,10000) L_0x1852f20/d; +L_0x1853080/d .functor AND 1, L_0x1853190, L_0x1852f20, C4<1>, C4<1>; +L_0x1853080 .delay 1 (20000,20000,20000) L_0x1853080/d; +L_0x18532f0/d .functor AND 1, L_0x1853400, L_0x1853710, C4<1>, C4<1>; +L_0x18532f0 .delay 1 (20000,20000,20000) L_0x18532f0/d; +L_0x18535b0/d .functor OR 1, L_0x1853080, L_0x18532f0, C4<0>, C4<0>; +L_0x18535b0 .delay 1 (20000,20000,20000) L_0x18535b0/d; +v0x179a5f0_0 .net *"_s1", 0 0, L_0x1853190; 1 drivers +v0x179a6f0_0 .net *"_s3", 0 0, L_0x1853400; 1 drivers +v0x179a7d0_0 .net "addr", 0 0, L_0x1853710; 1 drivers +v0x179a8a0_0 .net "in", 1 0, L_0x1853870; 1 drivers +v0x179a980_0 .net "naddr", 0 0, L_0x1852f20; 1 drivers +v0x179aa90_0 .net "o0", 0 0, L_0x1853080; 1 drivers +v0x179ab50_0 .net "o1", 0 0, L_0x18532f0; 1 drivers +v0x179ac10_0 .net "out", 0 0, L_0x18535b0; 1 drivers +L_0x1853190 .part L_0x1853870, 0, 1; +L_0x1853400 .part L_0x1853870, 1, 1; +S_0x179ad50 .scope module, "mux_1" "bitMultiplexer" 4 30, 4 8 0, S_0x179a110; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "addr" + .port_info 2 /INPUT 2 "in" +L_0x1853910/d .functor NOT 1, L_0x1854150, C4<0>, C4<0>, C4<0>; +L_0x1853910 .delay 1 (10000,10000,10000) L_0x1853910/d; +L_0x18539d0/d .functor AND 1, L_0x1853bd0, L_0x1853910, C4<1>, C4<1>; +L_0x18539d0 .delay 1 (20000,20000,20000) L_0x18539d0/d; +L_0x1853d30/d .functor AND 1, L_0x1853e40, L_0x1854150, C4<1>, C4<1>; +L_0x1853d30 .delay 1 (20000,20000,20000) L_0x1853d30/d; +L_0x1853ff0/d .functor OR 1, L_0x18539d0, L_0x1853d30, C4<0>, C4<0>; +L_0x1853ff0 .delay 1 (20000,20000,20000) L_0x1853ff0/d; +v0x179af80_0 .net *"_s1", 0 0, L_0x1853bd0; 1 drivers +v0x179b080_0 .net *"_s3", 0 0, L_0x1853e40; 1 drivers +v0x179b160_0 .net "addr", 0 0, L_0x1854150; 1 drivers +v0x179b200_0 .net "in", 1 0, L_0x18542b0; 1 drivers +v0x179b2e0_0 .net "naddr", 0 0, L_0x1853910; 1 drivers +v0x179b3f0_0 .net "o0", 0 0, L_0x18539d0; 1 drivers +v0x179b4b0_0 .net "o1", 0 0, L_0x1853d30; 1 drivers +v0x179b570_0 .net "out", 0 0, L_0x1853ff0; 1 drivers +L_0x1853bd0 .part L_0x18542b0, 0, 1; +L_0x1853e40 .part L_0x18542b0, 1, 1; +S_0x179b6b0 .scope module, "mux_2" "bitMultiplexer" 4 31, 4 8 0, S_0x179a110; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "addr" + .port_info 2 /INPUT 2 "in" +L_0x18541f0/d .functor NOT 1, L_0x1854b20, C4<0>, C4<0>, C4<0>; +L_0x18541f0 .delay 1 (10000,10000,10000) L_0x18541f0/d; +L_0x18543a0/d .functor AND 1, L_0x18545a0, L_0x18541f0, C4<1>, C4<1>; +L_0x18543a0 .delay 1 (20000,20000,20000) L_0x18543a0/d; +L_0x1854700/d .functor AND 1, L_0x1854810, L_0x1854b20, C4<1>, C4<1>; +L_0x1854700 .delay 1 (20000,20000,20000) L_0x1854700/d; +L_0x18549c0/d .functor OR 1, L_0x18543a0, L_0x1854700, C4<0>, C4<0>; +L_0x18549c0 .delay 1 (20000,20000,20000) L_0x18549c0/d; +v0x179b8e0_0 .net *"_s1", 0 0, L_0x18545a0; 1 drivers +v0x179b9c0_0 .net *"_s3", 0 0, L_0x1854810; 1 drivers +v0x179baa0_0 .net "addr", 0 0, L_0x1854b20; 1 drivers +v0x179bb70_0 .net "in", 1 0, L_0x1854c80; 1 drivers +v0x179bc50_0 .net "naddr", 0 0, L_0x18541f0; 1 drivers +v0x179bd60_0 .net "o0", 0 0, L_0x18543a0; 1 drivers +v0x179be20_0 .net "o1", 0 0, L_0x1854700; 1 drivers +v0x179bee0_0 .net "out", 0 0, L_0x18549c0; 1 drivers +L_0x18545a0 .part L_0x1854c80, 0, 1; +L_0x1854810 .part L_0x1854c80, 1, 1; +S_0x179c020 .scope module, "mux_3" "bitMultiplexer" 4 32, 4 8 0, S_0x179a110; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "addr" + .port_info 2 /INPUT 2 "in" +L_0x1854bc0/d .functor NOT 1, L_0x18557d0, C4<0>, C4<0>, C4<0>; +L_0x1854bc0 .delay 1 (10000,10000,10000) L_0x1854bc0/d; +L_0x1854db0/d .functor AND 1, L_0x1854fb0, L_0x1854bc0, C4<1>, C4<1>; +L_0x1854db0 .delay 1 (20000,20000,20000) L_0x1854db0/d; +L_0x1855110/d .functor AND 1, L_0x1855220, L_0x18557d0, C4<1>, C4<1>; +L_0x1855110 .delay 1 (20000,20000,20000) L_0x1855110/d; +L_0x18553d0/d .functor OR 1, L_0x1854db0, L_0x1855110, C4<0>, C4<0>; +L_0x18553d0 .delay 1 (20000,20000,20000) L_0x18553d0/d; +v0x179c250_0 .net *"_s1", 0 0, L_0x1854fb0; 1 drivers +v0x179c350_0 .net *"_s3", 0 0, L_0x1855220; 1 drivers +v0x179c430_0 .net "addr", 0 0, L_0x18557d0; 1 drivers +v0x179c4d0_0 .net "in", 1 0, L_0x18558c0; 1 drivers +v0x179c5b0_0 .net "naddr", 0 0, L_0x1854bc0; 1 drivers +v0x179c6c0_0 .net "o0", 0 0, L_0x1854db0; 1 drivers +v0x179c780_0 .net "o1", 0 0, L_0x1855110; 1 drivers +v0x179c840_0 .net "out", 0 0, L_0x18553d0; 1 drivers +L_0x1854fb0 .part L_0x18558c0, 0, 1; +L_0x1855220 .part L_0x18558c0, 1, 1; +S_0x179c980 .scope module, "mux_mid_0" "bitMultiplexer" 4 33, 4 8 0, S_0x179a110; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "addr" + .port_info 2 /INPUT 2 "in" +L_0x1855960/d .functor NOT 1, L_0x1856100, C4<0>, C4<0>, C4<0>; +L_0x1855960 .delay 1 (10000,10000,10000) L_0x1855960/d; +L_0x1855a20/d .functor AND 1, L_0x1855b80, L_0x1855960, C4<1>, C4<1>; +L_0x1855a20 .delay 1 (20000,20000,20000) L_0x1855a20/d; +L_0x1855ce0/d .functor AND 1, L_0x1855df0, L_0x1856100, C4<1>, C4<1>; +L_0x1855ce0 .delay 1 (20000,20000,20000) L_0x1855ce0/d; +L_0x1855fa0/d .functor OR 1, L_0x1855a20, L_0x1855ce0, C4<0>, C4<0>; +L_0x1855fa0 .delay 1 (20000,20000,20000) L_0x1855fa0/d; +v0x179cc00_0 .net *"_s1", 0 0, L_0x1855b80; 1 drivers +v0x179cd00_0 .net *"_s3", 0 0, L_0x1855df0; 1 drivers +v0x179cde0_0 .net "addr", 0 0, L_0x1856100; 1 drivers +v0x179ce80_0 .net "in", 1 0, L_0x1856260; 1 drivers +v0x179cf60_0 .net "naddr", 0 0, L_0x1855960; 1 drivers +v0x179d070_0 .net "o0", 0 0, L_0x1855a20; 1 drivers +v0x179d130_0 .net "o1", 0 0, L_0x1855ce0; 1 drivers +v0x179d1f0_0 .net "out", 0 0, L_0x1855fa0; 1 drivers +L_0x1855b80 .part L_0x1856260, 0, 1; +L_0x1855df0 .part L_0x1856260, 1, 1; +S_0x179d330 .scope module, "mux_mid_1" "bitMultiplexer" 4 34, 4 8 0, S_0x179a110; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "addr" + .port_info 2 /INPUT 2 "in" +L_0x1856300/d .functor NOT 1, L_0x1856cf0, C4<0>, C4<0>, C4<0>; +L_0x1856300 .delay 1 (10000,10000,10000) L_0x1856300/d; +L_0x18563c0/d .functor AND 1, L_0x1856570, L_0x1856300, C4<1>, C4<1>; +L_0x18563c0 .delay 1 (20000,20000,20000) L_0x18563c0/d; +L_0x18566d0/d .functor AND 1, L_0x18567e0, L_0x1856cf0, C4<1>, C4<1>; +L_0x18566d0 .delay 1 (20000,20000,20000) L_0x18566d0/d; +L_0x1856990/d .functor OR 1, L_0x18563c0, L_0x18566d0, C4<0>, C4<0>; +L_0x1856990 .delay 1 (20000,20000,20000) L_0x1856990/d; +v0x179d560_0 .net *"_s1", 0 0, L_0x1856570; 1 drivers +v0x179d660_0 .net *"_s3", 0 0, L_0x18567e0; 1 drivers +v0x179d740_0 .net "addr", 0 0, L_0x1856cf0; 1 drivers +v0x179d7e0_0 .net "in", 1 0, L_0x1856d90; 1 drivers +v0x179d8c0_0 .net "naddr", 0 0, L_0x1856300; 1 drivers +v0x179d9d0_0 .net "o0", 0 0, L_0x18563c0; 1 drivers +v0x179da90_0 .net "o1", 0 0, L_0x18566d0; 1 drivers +v0x179db50_0 .net "out", 0 0, L_0x1856990; 1 drivers +L_0x1856570 .part L_0x1856d90, 0, 1; +L_0x18567e0 .part L_0x1856d90, 1, 1; +S_0x179dc90 .scope module, "mux_out" "bitMultiplexer" 4 35, 4 8 0, S_0x179a110; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "addr" + .port_info 2 /INPUT 2 "in" +L_0x18561a0/d .functor NOT 1, L_0x18575d0, C4<0>, C4<0>, C4<0>; +L_0x18561a0 .delay 1 (10000,10000,10000) L_0x18561a0/d; +L_0x1856f00/d .functor AND 1, L_0x1857060, L_0x18561a0, C4<1>, C4<1>; +L_0x1856f00 .delay 1 (20000,20000,20000) L_0x1856f00/d; +L_0x18571c0/d .functor AND 1, L_0x18572d0, L_0x18575d0, C4<1>, C4<1>; +L_0x18571c0 .delay 1 (20000,20000,20000) L_0x18571c0/d; +L_0x18574c0/d .functor OR 1, L_0x1856f00, L_0x18571c0, C4<0>, C4<0>; +L_0x18574c0 .delay 1 (20000,20000,20000) L_0x18574c0/d; +v0x179dec0_0 .net *"_s1", 0 0, L_0x1857060; 1 drivers +v0x179dfc0_0 .net *"_s3", 0 0, L_0x18572d0; 1 drivers +v0x179e0a0_0 .net "addr", 0 0, L_0x18575d0; 1 drivers +v0x179e140_0 .net "in", 1 0, L_0x1856af0; alias, 1 drivers +v0x179e220_0 .net "naddr", 0 0, L_0x18561a0; 1 drivers +v0x179e330_0 .net "o0", 0 0, L_0x1856f00; 1 drivers +v0x179e3f0_0 .net "o1", 0 0, L_0x18571c0; 1 drivers +v0x179e4b0_0 .net "out", 0 0, L_0x18574c0; alias, 1 drivers +L_0x1857060 .part L_0x1856af0, 0, 1; +L_0x18572d0 .part L_0x1856af0, 1, 1; +S_0x179ea40 .scope module, "structadder" "structAddSub" 3 22, 5 8 0, S_0x1799e80; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "sub" + .port_info 5 /INPUT 1 "carryin" +L_0x1851d20/d .functor XOR 1, L_0x1852050, v0x17dbbc0_0, C4<0>, C4<0>; +L_0x1851d20 .delay 1 (20000,20000,20000) L_0x1851d20/d; +L_0x18521b0/d .functor XOR 1, L_0x1851fb0, L_0x1852050, C4<0>, C4<0>; +L_0x18521b0 .delay 1 (20000,20000,20000) L_0x18521b0/d; +L_0x18522c0/d .functor XOR 1, L_0x18521b0, L_0x1857730, C4<0>, C4<0>; +L_0x18522c0 .delay 1 (20000,20000,20000) L_0x18522c0/d; +L_0x1852470/d .functor AND 1, L_0x1851fb0, L_0x1852050, C4<1>, C4<1>; +L_0x1852470 .delay 1 (20000,20000,20000) L_0x1852470/d; +L_0x18525d0/d .functor AND 1, L_0x18521b0, L_0x1857730, C4<1>, C4<1>; +L_0x18525d0 .delay 1 (20000,20000,20000) L_0x18525d0/d; +L_0x1852730/d .functor OR 1, L_0x18525d0, L_0x1852470, C4<0>, C4<0>; +L_0x1852730 .delay 1 (20000,20000,20000) L_0x1852730/d; +v0x179ed00_0 .net "AandB", 0 0, L_0x1852470; 1 drivers +v0x179edc0_0 .net "AxorB", 0 0, L_0x18521b0; 1 drivers +v0x179ee80_0 .net "AxorBandCarryIn", 0 0, L_0x18525d0; 1 drivers +v0x179ef50_0 .net "a", 0 0, L_0x1851fb0; alias, 1 drivers +v0x179f010_0 .net "b", 0 0, L_0x1852050; alias, 1 drivers +v0x179f120_0 .net "bnew", 0 0, L_0x1851d20; 1 drivers +v0x179f1e0_0 .net "carryin", 0 0, L_0x1857730; alias, 1 drivers +v0x179f2a0_0 .net "carryout", 0 0, L_0x1852730; alias, 1 drivers +v0x179f360_0 .net "sub", 0 0, v0x17dbbc0_0; alias, 1 drivers +v0x179f490_0 .net "sum", 0 0, L_0x18522c0; 1 drivers +S_0x17a0320 .scope generate, "ripple[23]" "ripple[23]" 3 66, 3 66 0, S_0x16fa6c0; + .timescale -9 -12; +P_0x17a04f0 .param/l "i" 0 3 66, +C4<010111>; +S_0x17a05b0 .scope module, "bit" "BitSliceALU" 3 68, 3 11 0, S_0x17a0320; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "ALUout" + .port_info 1 /OUTPUT 1 "Cout" + .port_info 2 /INPUT 1 "invertB" + .port_info 3 /INPUT 1 "Cin" + .port_info 4 /INPUT 3 "addr" + .port_info 5 /INPUT 1 "bit1" + .port_info 6 /INPUT 1 "bit2" +L_0x18581a0/d .functor XOR 1, L_0x185d120, L_0x1857b80, C4<0>, C4<0>; +L_0x18581a0 .delay 1 (20000,20000,20000) L_0x18581a0/d; +L_0x1858300/d .functor NAND 1, L_0x185d120, L_0x1857b80, C4<1>, C4<1>; +L_0x1858300 .delay 1 (10000,10000,10000) L_0x1858300/d; +L_0x1858460/d .functor XOR 1, v0x17dbbc0_0, L_0x1858300, C4<0>, C4<0>; +L_0x1858460 .delay 1 (20000,20000,20000) L_0x1858460/d; +L_0x1858570/d .functor NOR 1, L_0x185d120, L_0x1857b80, C4<0>, C4<0>; +L_0x1858570 .delay 1 (10000,10000,10000) L_0x1858570/d; +L_0x18586d0/d .functor XOR 1, v0x17dbbc0_0, L_0x1858570, C4<0>, C4<0>; +L_0x18586d0 .delay 1 (20000,20000,20000) L_0x18586d0/d; +v0x17a5d90_0 .net "ALUout", 0 0, L_0x185cd80; 1 drivers +v0x17a5e50_0 .net "Cin", 0 0, L_0x185cff0; 1 drivers +v0x17a5f10_0 .net "Cout", 0 0, L_0x1853a70; 1 drivers +v0x17a5fe0_0 .net *"_s11", 0 0, L_0x18586d0; 1 drivers +o0x7fc2cd92a188 .functor BUFZ 1, C4; HiZ drive +; Elide local net with no drivers, v0x17a6080_0 name=_s15 +o0x7fc2cd92a1b8 .functor BUFZ 3, C4; HiZ drive +; Elide local net with no drivers, v0x17a6170_0 name=_s17 +v0x17a6250_0 .net *"_s3", 0 0, L_0x18581a0; 1 drivers +v0x17a6330_0 .net *"_s7", 0 0, L_0x1858460; 1 drivers +v0x17a6410_0 .net "addr", 2 0, v0x17dbc90_0; alias, 1 drivers +v0x17a6560_0 .net "bit1", 0 0, L_0x185d120; 1 drivers +v0x17a6600_0 .net "bit2", 0 0, L_0x1857b80; 1 drivers +v0x17a66d0_0 .net "invertB", 0 0, v0x17dbbc0_0; alias, 1 drivers +v0x17a6770_0 .net "nanded", 0 0, L_0x1858300; 1 drivers +v0x17a6810_0 .net "nored", 0 0, L_0x1858570; 1 drivers +v0x17a68b0_0 .net "out", 7 0, L_0x18940f0; 1 drivers +LS_0x18940f0_0_0 .concat [ 1 1 1 1], L_0x18578b0, L_0x18581a0, o0x7fc2cd92a188, L_0x1858460; +LS_0x18940f0_0_4 .concat [ 1 3 0 0], L_0x18586d0, o0x7fc2cd92a1b8; +L_0x18940f0 .concat [ 4 4 0 0], LS_0x18940f0_0_0, LS_0x18940f0_0_4; +S_0x17a0840 .scope module, "opmux" "structuralMultiplexer" 3 43, 4 21 0, S_0x17a05b0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 3 "address" + .port_info 2 /INPUT 8 "in" +v0x17a4d00_0 .net "address", 2 0, v0x17dbc90_0; alias, 1 drivers +v0x17a4dc0_0 .net "in", 7 0, L_0x18940f0; alias, 1 drivers +v0x17a4ea0_0 .net "mux", 3 0, L_0x185ae90; 1 drivers +v0x17a4f60_0 .net "muxmid", 1 0, L_0x185c3b0; 1 drivers +v0x17a5050_0 .net "out", 0 0, L_0x185cd80; alias, 1 drivers +L_0x18590c0 .part v0x17dbc90_0, 0, 1; +L_0x1859220 .part L_0x18940f0, 0, 2; +L_0x1859ab0 .part v0x17dbc90_0, 0, 1; +L_0x1859c10 .part L_0x18940f0, 2, 2; +L_0x185a480 .part v0x17dbc90_0, 0, 1; +L_0x185a5e0 .part L_0x18940f0, 4, 2; +L_0x185ae90 .concat8 [ 1 1 1 1], L_0x1858f60, L_0x1859950, L_0x185a320, L_0x185ad30; +L_0x185b0e0 .part v0x17dbc90_0, 0, 1; +L_0x185b1d0 .part L_0x18940f0, 6, 2; +L_0x185ba10 .part v0x17dbc90_0, 1, 1; +L_0x185bb70 .part L_0x185ae90, 0, 2; +L_0x185c3b0 .concat8 [ 1 1 0 0], L_0x185b8b0, L_0x185c250; +L_0x185c5b0 .part v0x17dbc90_0, 1, 1; +L_0x185c650 .part L_0x185ae90, 2, 2; +L_0x185ce90 .part v0x17dbc90_0, 2, 1; +S_0x17a0ab0 .scope module, "mux_0" "bitMultiplexer" 4 29, 4 8 0, S_0x17a0840; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "addr" + .port_info 2 /INPUT 2 "in" +L_0x18587e0/d .functor NOT 1, L_0x18590c0, C4<0>, C4<0>, C4<0>; +L_0x18587e0 .delay 1 (10000,10000,10000) L_0x18587e0/d; +L_0x1858940/d .functor AND 1, L_0x1858b40, L_0x18587e0, C4<1>, C4<1>; +L_0x1858940 .delay 1 (20000,20000,20000) L_0x1858940/d; +L_0x1858ca0/d .functor AND 1, L_0x1858db0, L_0x18590c0, C4<1>, C4<1>; +L_0x1858ca0 .delay 1 (20000,20000,20000) L_0x1858ca0/d; +L_0x1858f60/d .functor OR 1, L_0x1858940, L_0x1858ca0, C4<0>, C4<0>; +L_0x1858f60 .delay 1 (20000,20000,20000) L_0x1858f60/d; +v0x17a0d20_0 .net *"_s1", 0 0, L_0x1858b40; 1 drivers +v0x17a0e20_0 .net *"_s3", 0 0, L_0x1858db0; 1 drivers +v0x17a0f00_0 .net "addr", 0 0, L_0x18590c0; 1 drivers +v0x17a0fd0_0 .net "in", 1 0, L_0x1859220; 1 drivers +v0x17a10b0_0 .net "naddr", 0 0, L_0x18587e0; 1 drivers +v0x17a11c0_0 .net "o0", 0 0, L_0x1858940; 1 drivers +v0x17a1280_0 .net "o1", 0 0, L_0x1858ca0; 1 drivers +v0x17a1340_0 .net "out", 0 0, L_0x1858f60; 1 drivers +L_0x1858b40 .part L_0x1859220, 0, 1; +L_0x1858db0 .part L_0x1859220, 1, 1; +S_0x17a1480 .scope module, "mux_1" "bitMultiplexer" 4 30, 4 8 0, S_0x17a0840; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "addr" + .port_info 2 /INPUT 2 "in" +L_0x18592c0/d .functor NOT 1, L_0x1859ab0, C4<0>, C4<0>, C4<0>; +L_0x18592c0 .delay 1 (10000,10000,10000) L_0x18592c0/d; +L_0x1859380/d .functor AND 1, L_0x1859530, L_0x18592c0, C4<1>, C4<1>; +L_0x1859380 .delay 1 (20000,20000,20000) L_0x1859380/d; +L_0x1859690/d .functor AND 1, L_0x18597a0, L_0x1859ab0, C4<1>, C4<1>; +L_0x1859690 .delay 1 (20000,20000,20000) L_0x1859690/d; +L_0x1859950/d .functor OR 1, L_0x1859380, L_0x1859690, C4<0>, C4<0>; +L_0x1859950 .delay 1 (20000,20000,20000) L_0x1859950/d; +v0x17a16b0_0 .net *"_s1", 0 0, L_0x1859530; 1 drivers +v0x17a17b0_0 .net *"_s3", 0 0, L_0x18597a0; 1 drivers +v0x17a1890_0 .net "addr", 0 0, L_0x1859ab0; 1 drivers +v0x17a1930_0 .net "in", 1 0, L_0x1859c10; 1 drivers +v0x17a1a10_0 .net "naddr", 0 0, L_0x18592c0; 1 drivers +v0x17a1b20_0 .net "o0", 0 0, L_0x1859380; 1 drivers +v0x17a1be0_0 .net "o1", 0 0, L_0x1859690; 1 drivers +v0x17a1ca0_0 .net "out", 0 0, L_0x1859950; 1 drivers +L_0x1859530 .part L_0x1859c10, 0, 1; +L_0x18597a0 .part L_0x1859c10, 1, 1; +S_0x17a1de0 .scope module, "mux_2" "bitMultiplexer" 4 31, 4 8 0, S_0x17a0840; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "addr" + .port_info 2 /INPUT 2 "in" +L_0x1859b50/d .functor NOT 1, L_0x185a480, C4<0>, C4<0>, C4<0>; +L_0x1859b50 .delay 1 (10000,10000,10000) L_0x1859b50/d; +L_0x1859d00/d .functor AND 1, L_0x1859f00, L_0x1859b50, C4<1>, C4<1>; +L_0x1859d00 .delay 1 (20000,20000,20000) L_0x1859d00/d; +L_0x185a060/d .functor AND 1, L_0x185a170, L_0x185a480, C4<1>, C4<1>; +L_0x185a060 .delay 1 (20000,20000,20000) L_0x185a060/d; +L_0x185a320/d .functor OR 1, L_0x1859d00, L_0x185a060, C4<0>, C4<0>; +L_0x185a320 .delay 1 (20000,20000,20000) L_0x185a320/d; +v0x17a2010_0 .net *"_s1", 0 0, L_0x1859f00; 1 drivers +v0x17a20f0_0 .net *"_s3", 0 0, L_0x185a170; 1 drivers +v0x17a21d0_0 .net "addr", 0 0, L_0x185a480; 1 drivers +v0x17a22a0_0 .net "in", 1 0, L_0x185a5e0; 1 drivers +v0x17a2380_0 .net "naddr", 0 0, L_0x1859b50; 1 drivers +v0x17a2490_0 .net "o0", 0 0, L_0x1859d00; 1 drivers +v0x17a2550_0 .net "o1", 0 0, L_0x185a060; 1 drivers +v0x17a2610_0 .net "out", 0 0, L_0x185a320; 1 drivers +L_0x1859f00 .part L_0x185a5e0, 0, 1; +L_0x185a170 .part L_0x185a5e0, 1, 1; +S_0x17a2750 .scope module, "mux_3" "bitMultiplexer" 4 32, 4 8 0, S_0x17a0840; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "addr" + .port_info 2 /INPUT 2 "in" +L_0x185a520/d .functor NOT 1, L_0x185b0e0, C4<0>, C4<0>, C4<0>; +L_0x185a520 .delay 1 (10000,10000,10000) L_0x185a520/d; +L_0x185a710/d .functor AND 1, L_0x185a910, L_0x185a520, C4<1>, C4<1>; +L_0x185a710 .delay 1 (20000,20000,20000) L_0x185a710/d; +L_0x185aa70/d .functor AND 1, L_0x185ab80, L_0x185b0e0, C4<1>, C4<1>; +L_0x185aa70 .delay 1 (20000,20000,20000) L_0x185aa70/d; +L_0x185ad30/d .functor OR 1, L_0x185a710, L_0x185aa70, C4<0>, C4<0>; +L_0x185ad30 .delay 1 (20000,20000,20000) L_0x185ad30/d; +v0x17a2980_0 .net *"_s1", 0 0, L_0x185a910; 1 drivers +v0x17a2a80_0 .net *"_s3", 0 0, L_0x185ab80; 1 drivers +v0x17a2b60_0 .net "addr", 0 0, L_0x185b0e0; 1 drivers +v0x17a2c00_0 .net "in", 1 0, L_0x185b1d0; 1 drivers +v0x17a2ce0_0 .net "naddr", 0 0, L_0x185a520; 1 drivers +v0x17a2df0_0 .net "o0", 0 0, L_0x185a710; 1 drivers +v0x17a2eb0_0 .net "o1", 0 0, L_0x185aa70; 1 drivers +v0x17a2f70_0 .net "out", 0 0, L_0x185ad30; 1 drivers +L_0x185a910 .part L_0x185b1d0, 0, 1; +L_0x185ab80 .part L_0x185b1d0, 1, 1; +S_0x17a30b0 .scope module, "mux_mid_0" "bitMultiplexer" 4 33, 4 8 0, S_0x17a0840; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "addr" + .port_info 2 /INPUT 2 "in" +L_0x185b270/d .functor NOT 1, L_0x185ba10, C4<0>, C4<0>, C4<0>; +L_0x185b270 .delay 1 (10000,10000,10000) L_0x185b270/d; +L_0x185b330/d .functor AND 1, L_0x185b490, L_0x185b270, C4<1>, C4<1>; +L_0x185b330 .delay 1 (20000,20000,20000) L_0x185b330/d; +L_0x185b5f0/d .functor AND 1, L_0x185b700, L_0x185ba10, C4<1>, C4<1>; +L_0x185b5f0 .delay 1 (20000,20000,20000) L_0x185b5f0/d; +L_0x185b8b0/d .functor OR 1, L_0x185b330, L_0x185b5f0, C4<0>, C4<0>; +L_0x185b8b0 .delay 1 (20000,20000,20000) L_0x185b8b0/d; +v0x17a3330_0 .net *"_s1", 0 0, L_0x185b490; 1 drivers +v0x17a3430_0 .net *"_s3", 0 0, L_0x185b700; 1 drivers +v0x17a3510_0 .net "addr", 0 0, L_0x185ba10; 1 drivers +v0x17a35b0_0 .net "in", 1 0, L_0x185bb70; 1 drivers +v0x17a3690_0 .net "naddr", 0 0, L_0x185b270; 1 drivers +v0x17a37a0_0 .net "o0", 0 0, L_0x185b330; 1 drivers +v0x17a3860_0 .net "o1", 0 0, L_0x185b5f0; 1 drivers +v0x17a3920_0 .net "out", 0 0, L_0x185b8b0; 1 drivers +L_0x185b490 .part L_0x185bb70, 0, 1; +L_0x185b700 .part L_0x185bb70, 1, 1; +S_0x17a3a60 .scope module, "mux_mid_1" "bitMultiplexer" 4 34, 4 8 0, S_0x17a0840; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "addr" + .port_info 2 /INPUT 2 "in" +L_0x185bc10/d .functor NOT 1, L_0x185c5b0, C4<0>, C4<0>, C4<0>; +L_0x185bc10 .delay 1 (10000,10000,10000) L_0x185bc10/d; +L_0x185bcd0/d .functor AND 1, L_0x185be30, L_0x185bc10, C4<1>, C4<1>; +L_0x185bcd0 .delay 1 (20000,20000,20000) L_0x185bcd0/d; +L_0x185bf90/d .functor AND 1, L_0x185c0a0, L_0x185c5b0, C4<1>, C4<1>; +L_0x185bf90 .delay 1 (20000,20000,20000) L_0x185bf90/d; +L_0x185c250/d .functor OR 1, L_0x185bcd0, L_0x185bf90, C4<0>, C4<0>; +L_0x185c250 .delay 1 (20000,20000,20000) L_0x185c250/d; +v0x17a3c90_0 .net *"_s1", 0 0, L_0x185be30; 1 drivers +v0x17a3d90_0 .net *"_s3", 0 0, L_0x185c0a0; 1 drivers +v0x17a3e70_0 .net "addr", 0 0, L_0x185c5b0; 1 drivers +v0x17a3f10_0 .net "in", 1 0, L_0x185c650; 1 drivers +v0x17a3ff0_0 .net "naddr", 0 0, L_0x185bc10; 1 drivers +v0x17a40e0_0 .net "o0", 0 0, L_0x185bcd0; 1 drivers +v0x17a41a0_0 .net "o1", 0 0, L_0x185bf90; 1 drivers +v0x17a4260_0 .net "out", 0 0, L_0x185c250; 1 drivers +L_0x185be30 .part L_0x185c650, 0, 1; +L_0x185c0a0 .part L_0x185c650, 1, 1; +S_0x17a43a0 .scope module, "mux_out" "bitMultiplexer" 4 35, 4 8 0, S_0x17a0840; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "addr" + .port_info 2 /INPUT 2 "in" +L_0x185bab0/d .functor NOT 1, L_0x185ce90, C4<0>, C4<0>, C4<0>; +L_0x185bab0 .delay 1 (10000,10000,10000) L_0x185bab0/d; +L_0x185c7c0/d .functor AND 1, L_0x185c920, L_0x185bab0, C4<1>, C4<1>; +L_0x185c7c0 .delay 1 (20000,20000,20000) L_0x185c7c0/d; +L_0x185ca80/d .functor AND 1, L_0x185cb90, L_0x185ce90, C4<1>, C4<1>; +L_0x185ca80 .delay 1 (20000,20000,20000) L_0x185ca80/d; +L_0x185cd80/d .functor OR 1, L_0x185c7c0, L_0x185ca80, C4<0>, C4<0>; +L_0x185cd80 .delay 1 (20000,20000,20000) L_0x185cd80/d; +v0x17a45d0_0 .net *"_s1", 0 0, L_0x185c920; 1 drivers +v0x17a46d0_0 .net *"_s3", 0 0, L_0x185cb90; 1 drivers +v0x17a47b0_0 .net "addr", 0 0, L_0x185ce90; 1 drivers +v0x17a4850_0 .net "in", 1 0, L_0x185c3b0; alias, 1 drivers +v0x17a4930_0 .net "naddr", 0 0, L_0x185bab0; 1 drivers +v0x17a4a40_0 .net "o0", 0 0, L_0x185c7c0; 1 drivers +v0x17a4b00_0 .net "o1", 0 0, L_0x185ca80; 1 drivers +v0x17a4bc0_0 .net "out", 0 0, L_0x185cd80; alias, 1 drivers +L_0x185c920 .part L_0x185c3b0, 0, 1; +L_0x185cb90 .part L_0x185c3b0, 1, 1; +S_0x17a5180 .scope module, "structadder" "structAddSub" 3 22, 5 8 0, S_0x17a05b0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "sub" + .port_info 5 /INPUT 1 "carryin" +L_0x1857670/d .functor XOR 1, L_0x1857b80, v0x17dbbc0_0, C4<0>, C4<0>; +L_0x1857670 .delay 1 (20000,20000,20000) L_0x1857670/d; +L_0x18520f0/d .functor XOR 1, L_0x185d120, L_0x1857b80, C4<0>, C4<0>; +L_0x18520f0 .delay 1 (20000,20000,20000) L_0x18520f0/d; +L_0x18578b0/d .functor XOR 1, L_0x18520f0, L_0x185cff0, C4<0>, C4<0>; +L_0x18578b0 .delay 1 (20000,20000,20000) L_0x18578b0/d; +L_0x1857da0/d .functor AND 1, L_0x185d120, L_0x1857b80, C4<1>, C4<1>; +L_0x1857da0 .delay 1 (20000,20000,20000) L_0x1857da0/d; +L_0x1857f00/d .functor AND 1, L_0x18520f0, L_0x185cff0, C4<1>, C4<1>; +L_0x1857f00 .delay 1 (20000,20000,20000) L_0x1857f00/d; +L_0x1853a70/d .functor OR 1, L_0x1857f00, L_0x1857da0, C4<0>, C4<0>; +L_0x1853a70 .delay 1 (20000,20000,20000) L_0x1853a70/d; +v0x17a5440_0 .net "AandB", 0 0, L_0x1857da0; 1 drivers +v0x17a5500_0 .net "AxorB", 0 0, L_0x18520f0; 1 drivers +v0x17a55c0_0 .net "AxorBandCarryIn", 0 0, L_0x1857f00; 1 drivers +v0x17a5690_0 .net "a", 0 0, L_0x185d120; alias, 1 drivers +v0x17a5750_0 .net "b", 0 0, L_0x1857b80; alias, 1 drivers +v0x17a5860_0 .net "bnew", 0 0, L_0x1857670; 1 drivers +v0x17a5920_0 .net "carryin", 0 0, L_0x185cff0; alias, 1 drivers +v0x17a59e0_0 .net "carryout", 0 0, L_0x1853a70; alias, 1 drivers +v0x17a5aa0_0 .net "sub", 0 0, v0x17dbbc0_0; alias, 1 drivers +v0x17a5bd0_0 .net "sum", 0 0, L_0x18578b0; 1 drivers +S_0x17a6a60 .scope generate, "ripple[24]" "ripple[24]" 3 66, 3 66 0, S_0x16fa6c0; + .timescale -9 -12; +P_0x17a6c30 .param/l "i" 0 3 66, +C4<011000>; +S_0x17a6cf0 .scope module, "bit" "BitSliceALU" 3 68, 3 11 0, S_0x17a6a60; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "ALUout" + .port_info 1 /OUTPUT 1 "Cout" + .port_info 2 /INPUT 1 "invertB" + .port_info 3 /INPUT 1 "Cin" + .port_info 4 /INPUT 3 "addr" + .port_info 5 /INPUT 1 "bit1" + .port_info 6 /INPUT 1 "bit2" +L_0x185dad0/d .functor XOR 1, L_0x185d1c0, L_0x185d260, C4<0>, C4<0>; +L_0x185dad0 .delay 1 (20000,20000,20000) L_0x185dad0/d; +L_0x185dc30/d .functor NAND 1, L_0x185d1c0, L_0x185d260, C4<1>, C4<1>; +L_0x185dc30 .delay 1 (10000,10000,10000) L_0x185dc30/d; +L_0x185dd90/d .functor XOR 1, v0x17dbbc0_0, L_0x185dc30, C4<0>, C4<0>; +L_0x185dd90 .delay 1 (20000,20000,20000) L_0x185dd90/d; +L_0x185dea0/d .functor NOR 1, L_0x185d1c0, L_0x185d260, C4<0>, C4<0>; +L_0x185dea0 .delay 1 (10000,10000,10000) L_0x185dea0/d; +L_0x185e000/d .functor XOR 1, v0x17dbbc0_0, L_0x185dea0, C4<0>, C4<0>; +L_0x185e000 .delay 1 (20000,20000,20000) L_0x185e000/d; +v0x17ac4c0_0 .net "ALUout", 0 0, L_0x18626b0; 1 drivers +v0x17ac580_0 .net "Cin", 0 0, L_0x1862920; 1 drivers +v0x17ac640_0 .net "Cout", 0 0, L_0x185d920; 1 drivers +v0x17ac710_0 .net *"_s11", 0 0, L_0x185e000; 1 drivers +o0x7fc2cd92b658 .functor BUFZ 1, C4; HiZ drive +; Elide local net with no drivers, v0x17ac7b0_0 name=_s15 +o0x7fc2cd92b688 .functor BUFZ 3, C4; HiZ drive +; Elide local net with no drivers, v0x17ac8a0_0 name=_s17 +v0x17ac980_0 .net *"_s3", 0 0, L_0x185dad0; 1 drivers +v0x17aca60_0 .net *"_s7", 0 0, L_0x185dd90; 1 drivers +v0x17acb40_0 .net "addr", 2 0, v0x17dbc90_0; alias, 1 drivers +v0x17acc90_0 .net "bit1", 0 0, L_0x185d1c0; 1 drivers +v0x17acd30_0 .net "bit2", 0 0, L_0x185d260; 1 drivers +v0x17ace00_0 .net "invertB", 0 0, v0x17dbbc0_0; alias, 1 drivers +v0x17acea0_0 .net "nanded", 0 0, L_0x185dc30; 1 drivers +v0x17acf40_0 .net "nored", 0 0, L_0x185dea0; 1 drivers +v0x17acfe0_0 .net "out", 7 0, L_0x18942d0; 1 drivers +LS_0x18942d0_0_0 .concat [ 1 1 1 1], L_0x185d4b0, L_0x185dad0, o0x7fc2cd92b658, L_0x185dd90; +LS_0x18942d0_0_4 .concat [ 1 3 0 0], L_0x185e000, o0x7fc2cd92b688; +L_0x18942d0 .concat [ 4 4 0 0], LS_0x18942d0_0_0, LS_0x18942d0_0_4; +S_0x17a6f80 .scope module, "opmux" "structuralMultiplexer" 3 43, 4 21 0, S_0x17a6cf0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 3 "address" + .port_info 2 /INPUT 8 "in" +v0x17ab460_0 .net "address", 2 0, v0x17dbc90_0; alias, 1 drivers +v0x17ab520_0 .net "in", 7 0, L_0x18942d0; alias, 1 drivers +v0x17ab600_0 .net "mux", 3 0, L_0x1860720; 1 drivers +v0x17ab6c0_0 .net "muxmid", 1 0, L_0x1861ce0; 1 drivers +v0x17ab780_0 .net "out", 0 0, L_0x18626b0; alias, 1 drivers +L_0x185e900 .part v0x17dbc90_0, 0, 1; +L_0x185ea60 .part L_0x18942d0, 0, 2; +L_0x185f340 .part v0x17dbc90_0, 0, 1; +L_0x185f4a0 .part L_0x18942d0, 2, 2; +L_0x185fd10 .part v0x17dbc90_0, 0, 1; +L_0x185fe70 .part L_0x18942d0, 4, 2; +L_0x1860720 .concat8 [ 1 1 1 1], L_0x185e7a0, L_0x185f1e0, L_0x185fbb0, L_0x18605c0; +L_0x18609c0 .part v0x17dbc90_0, 0, 1; +L_0x1860ab0 .part L_0x18942d0, 6, 2; +L_0x18612f0 .part v0x17dbc90_0, 1, 1; +L_0x1861450 .part L_0x1860720, 0, 2; +L_0x1861ce0 .concat8 [ 1 1 0 0], L_0x1861190, L_0x1861b80; +L_0x1861ee0 .part v0x17dbc90_0, 1, 1; +L_0x1861f80 .part L_0x1860720, 2, 2; +L_0x18627c0 .part v0x17dbc90_0, 2, 1; +S_0x17a71f0 .scope module, "mux_0" "bitMultiplexer" 4 29, 4 8 0, S_0x17a6f80; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "addr" + .port_info 2 /INPUT 2 "in" +L_0x185e110/d .functor NOT 1, L_0x185e900, C4<0>, C4<0>, C4<0>; +L_0x185e110 .delay 1 (10000,10000,10000) L_0x185e110/d; +L_0x185e270/d .functor AND 1, L_0x185e380, L_0x185e110, C4<1>, C4<1>; +L_0x185e270 .delay 1 (20000,20000,20000) L_0x185e270/d; +L_0x185e4e0/d .functor AND 1, L_0x185e5f0, L_0x185e900, C4<1>, C4<1>; +L_0x185e4e0 .delay 1 (20000,20000,20000) L_0x185e4e0/d; +L_0x185e7a0/d .functor OR 1, L_0x185e270, L_0x185e4e0, C4<0>, C4<0>; +L_0x185e7a0 .delay 1 (20000,20000,20000) L_0x185e7a0/d; +v0x17a7460_0 .net *"_s1", 0 0, L_0x185e380; 1 drivers +v0x17a7560_0 .net *"_s3", 0 0, L_0x185e5f0; 1 drivers +v0x17a7640_0 .net "addr", 0 0, L_0x185e900; 1 drivers +v0x17a7710_0 .net "in", 1 0, L_0x185ea60; 1 drivers +v0x17a77f0_0 .net "naddr", 0 0, L_0x185e110; 1 drivers +v0x17a7900_0 .net "o0", 0 0, L_0x185e270; 1 drivers +v0x17a79c0_0 .net "o1", 0 0, L_0x185e4e0; 1 drivers +v0x17a7a80_0 .net "out", 0 0, L_0x185e7a0; 1 drivers +L_0x185e380 .part L_0x185ea60, 0, 1; +L_0x185e5f0 .part L_0x185ea60, 1, 1; +S_0x17a7bc0 .scope module, "mux_1" "bitMultiplexer" 4 30, 4 8 0, S_0x17a6f80; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "addr" + .port_info 2 /INPUT 2 "in" +L_0x185eb00/d .functor NOT 1, L_0x185f340, C4<0>, C4<0>, C4<0>; +L_0x185eb00 .delay 1 (10000,10000,10000) L_0x185eb00/d; +L_0x185ebc0/d .functor AND 1, L_0x185edc0, L_0x185eb00, C4<1>, C4<1>; +L_0x185ebc0 .delay 1 (20000,20000,20000) L_0x185ebc0/d; +L_0x185ef20/d .functor AND 1, L_0x185f030, L_0x185f340, C4<1>, C4<1>; +L_0x185ef20 .delay 1 (20000,20000,20000) L_0x185ef20/d; +L_0x185f1e0/d .functor OR 1, L_0x185ebc0, L_0x185ef20, C4<0>, C4<0>; +L_0x185f1e0 .delay 1 (20000,20000,20000) L_0x185f1e0/d; +v0x17a7df0_0 .net *"_s1", 0 0, L_0x185edc0; 1 drivers +v0x17a7ef0_0 .net *"_s3", 0 0, L_0x185f030; 1 drivers +v0x17a7fd0_0 .net "addr", 0 0, L_0x185f340; 1 drivers +v0x17a8070_0 .net "in", 1 0, L_0x185f4a0; 1 drivers +v0x17a8150_0 .net "naddr", 0 0, L_0x185eb00; 1 drivers +v0x17a8260_0 .net "o0", 0 0, L_0x185ebc0; 1 drivers +v0x17a8320_0 .net "o1", 0 0, L_0x185ef20; 1 drivers +v0x17a83e0_0 .net "out", 0 0, L_0x185f1e0; 1 drivers +L_0x185edc0 .part L_0x185f4a0, 0, 1; +L_0x185f030 .part L_0x185f4a0, 1, 1; +S_0x17a8520 .scope module, "mux_2" "bitMultiplexer" 4 31, 4 8 0, S_0x17a6f80; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "addr" + .port_info 2 /INPUT 2 "in" +L_0x185f3e0/d .functor NOT 1, L_0x185fd10, C4<0>, C4<0>, C4<0>; +L_0x185f3e0 .delay 1 (10000,10000,10000) L_0x185f3e0/d; +L_0x185f590/d .functor AND 1, L_0x185f790, L_0x185f3e0, C4<1>, C4<1>; +L_0x185f590 .delay 1 (20000,20000,20000) L_0x185f590/d; +L_0x185f8f0/d .functor AND 1, L_0x185fa00, L_0x185fd10, C4<1>, C4<1>; +L_0x185f8f0 .delay 1 (20000,20000,20000) L_0x185f8f0/d; +L_0x185fbb0/d .functor OR 1, L_0x185f590, L_0x185f8f0, C4<0>, C4<0>; +L_0x185fbb0 .delay 1 (20000,20000,20000) L_0x185fbb0/d; +v0x17a8750_0 .net *"_s1", 0 0, L_0x185f790; 1 drivers +v0x17a8830_0 .net *"_s3", 0 0, L_0x185fa00; 1 drivers +v0x17a8910_0 .net "addr", 0 0, L_0x185fd10; 1 drivers +v0x17a89e0_0 .net "in", 1 0, L_0x185fe70; 1 drivers +v0x17a8ac0_0 .net "naddr", 0 0, L_0x185f3e0; 1 drivers +v0x17a8bd0_0 .net "o0", 0 0, L_0x185f590; 1 drivers +v0x17a8c90_0 .net "o1", 0 0, L_0x185f8f0; 1 drivers +v0x17a8d50_0 .net "out", 0 0, L_0x185fbb0; 1 drivers +L_0x185f790 .part L_0x185fe70, 0, 1; +L_0x185fa00 .part L_0x185fe70, 1, 1; +S_0x17a8e90 .scope module, "mux_3" "bitMultiplexer" 4 32, 4 8 0, S_0x17a6f80; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "addr" + .port_info 2 /INPUT 2 "in" +L_0x185fdb0/d .functor NOT 1, L_0x18609c0, C4<0>, C4<0>, C4<0>; +L_0x185fdb0 .delay 1 (10000,10000,10000) L_0x185fdb0/d; +L_0x185ffa0/d .functor AND 1, L_0x18601a0, L_0x185fdb0, C4<1>, C4<1>; +L_0x185ffa0 .delay 1 (20000,20000,20000) L_0x185ffa0/d; +L_0x1860300/d .functor AND 1, L_0x1860410, L_0x18609c0, C4<1>, C4<1>; +L_0x1860300 .delay 1 (20000,20000,20000) L_0x1860300/d; +L_0x18605c0/d .functor OR 1, L_0x185ffa0, L_0x1860300, C4<0>, C4<0>; +L_0x18605c0 .delay 1 (20000,20000,20000) L_0x18605c0/d; +v0x17a90c0_0 .net *"_s1", 0 0, L_0x18601a0; 1 drivers +v0x17a91c0_0 .net *"_s3", 0 0, L_0x1860410; 1 drivers +v0x17a92a0_0 .net "addr", 0 0, L_0x18609c0; 1 drivers +v0x17a9340_0 .net "in", 1 0, L_0x1860ab0; 1 drivers +v0x17a9420_0 .net "naddr", 0 0, L_0x185fdb0; 1 drivers +v0x17a9530_0 .net "o0", 0 0, L_0x185ffa0; 1 drivers +v0x17a95f0_0 .net "o1", 0 0, L_0x1860300; 1 drivers +v0x17a96b0_0 .net "out", 0 0, L_0x18605c0; 1 drivers +L_0x18601a0 .part L_0x1860ab0, 0, 1; +L_0x1860410 .part L_0x1860ab0, 1, 1; +S_0x17a97f0 .scope module, "mux_mid_0" "bitMultiplexer" 4 33, 4 8 0, S_0x17a6f80; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "addr" + .port_info 2 /INPUT 2 "in" +L_0x1860b50/d .functor NOT 1, L_0x18612f0, C4<0>, C4<0>, C4<0>; +L_0x1860b50 .delay 1 (10000,10000,10000) L_0x1860b50/d; +L_0x1860c10/d .functor AND 1, L_0x1860d70, L_0x1860b50, C4<1>, C4<1>; +L_0x1860c10 .delay 1 (20000,20000,20000) L_0x1860c10/d; +L_0x1860ed0/d .functor AND 1, L_0x1860fe0, L_0x18612f0, C4<1>, C4<1>; +L_0x1860ed0 .delay 1 (20000,20000,20000) L_0x1860ed0/d; +L_0x1861190/d .functor OR 1, L_0x1860c10, L_0x1860ed0, C4<0>, C4<0>; +L_0x1861190 .delay 1 (20000,20000,20000) L_0x1861190/d; +v0x17a9a70_0 .net *"_s1", 0 0, L_0x1860d70; 1 drivers +v0x17a9b70_0 .net *"_s3", 0 0, L_0x1860fe0; 1 drivers +v0x17a9c50_0 .net "addr", 0 0, L_0x18612f0; 1 drivers +v0x17a9cf0_0 .net "in", 1 0, L_0x1861450; 1 drivers +v0x17a9dd0_0 .net "naddr", 0 0, L_0x1860b50; 1 drivers +v0x17a9ee0_0 .net "o0", 0 0, L_0x1860c10; 1 drivers +v0x17a9fa0_0 .net "o1", 0 0, L_0x1860ed0; 1 drivers +v0x17aa060_0 .net "out", 0 0, L_0x1861190; 1 drivers +L_0x1860d70 .part L_0x1861450, 0, 1; +L_0x1860fe0 .part L_0x1861450, 1, 1; +S_0x17aa1a0 .scope module, "mux_mid_1" "bitMultiplexer" 4 34, 4 8 0, S_0x17a6f80; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "addr" + .port_info 2 /INPUT 2 "in" +L_0x18614f0/d .functor NOT 1, L_0x1861ee0, C4<0>, C4<0>, C4<0>; +L_0x18614f0 .delay 1 (10000,10000,10000) L_0x18614f0/d; +L_0x18615b0/d .functor AND 1, L_0x1861760, L_0x18614f0, C4<1>, C4<1>; +L_0x18615b0 .delay 1 (20000,20000,20000) L_0x18615b0/d; +L_0x18618c0/d .functor AND 1, L_0x18619d0, L_0x1861ee0, C4<1>, C4<1>; +L_0x18618c0 .delay 1 (20000,20000,20000) L_0x18618c0/d; +L_0x1861b80/d .functor OR 1, L_0x18615b0, L_0x18618c0, C4<0>, C4<0>; +L_0x1861b80 .delay 1 (20000,20000,20000) L_0x1861b80/d; +v0x17aa3d0_0 .net *"_s1", 0 0, L_0x1861760; 1 drivers +v0x17aa4d0_0 .net *"_s3", 0 0, L_0x18619d0; 1 drivers +v0x17aa5b0_0 .net "addr", 0 0, L_0x1861ee0; 1 drivers +v0x17aa650_0 .net "in", 1 0, L_0x1861f80; 1 drivers +v0x17aa730_0 .net "naddr", 0 0, L_0x18614f0; 1 drivers +v0x17aa840_0 .net "o0", 0 0, L_0x18615b0; 1 drivers +v0x17aa900_0 .net "o1", 0 0, L_0x18618c0; 1 drivers +v0x17aa9c0_0 .net "out", 0 0, L_0x1861b80; 1 drivers +L_0x1861760 .part L_0x1861f80, 0, 1; +L_0x18619d0 .part L_0x1861f80, 1, 1; +S_0x17aab00 .scope module, "mux_out" "bitMultiplexer" 4 35, 4 8 0, S_0x17a6f80; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "addr" + .port_info 2 /INPUT 2 "in" +L_0x1861390/d .functor NOT 1, L_0x18627c0, C4<0>, C4<0>, C4<0>; +L_0x1861390 .delay 1 (10000,10000,10000) L_0x1861390/d; +L_0x18620f0/d .functor AND 1, L_0x1862250, L_0x1861390, C4<1>, C4<1>; +L_0x18620f0 .delay 1 (20000,20000,20000) L_0x18620f0/d; +L_0x18623b0/d .functor AND 1, L_0x18624c0, L_0x18627c0, C4<1>, C4<1>; +L_0x18623b0 .delay 1 (20000,20000,20000) L_0x18623b0/d; +L_0x18626b0/d .functor OR 1, L_0x18620f0, L_0x18623b0, C4<0>, C4<0>; +L_0x18626b0 .delay 1 (20000,20000,20000) L_0x18626b0/d; +v0x17aad30_0 .net *"_s1", 0 0, L_0x1862250; 1 drivers +v0x17aae30_0 .net *"_s3", 0 0, L_0x18624c0; 1 drivers +v0x17aaf10_0 .net "addr", 0 0, L_0x18627c0; 1 drivers +v0x17aafb0_0 .net "in", 1 0, L_0x1861ce0; alias, 1 drivers +v0x17ab090_0 .net "naddr", 0 0, L_0x1861390; 1 drivers +v0x17ab1a0_0 .net "o0", 0 0, L_0x18620f0; 1 drivers +v0x17ab260_0 .net "o1", 0 0, L_0x18623b0; 1 drivers +v0x17ab320_0 .net "out", 0 0, L_0x18626b0; alias, 1 drivers +L_0x1862250 .part L_0x1861ce0, 0, 1; +L_0x18624c0 .part L_0x1861ce0, 1, 1; +S_0x17ab8b0 .scope module, "structadder" "structAddSub" 3 22, 5 8 0, S_0x17a6cf0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "sub" + .port_info 5 /INPUT 1 "carryin" +L_0x185cf30/d .functor XOR 1, L_0x185d260, v0x17dbbc0_0, C4<0>, C4<0>; +L_0x185cf30 .delay 1 (20000,20000,20000) L_0x185cf30/d; +L_0x185d3f0/d .functor XOR 1, L_0x185d1c0, L_0x185d260, C4<0>, C4<0>; +L_0x185d3f0 .delay 1 (20000,20000,20000) L_0x185d3f0/d; +L_0x185d4b0/d .functor XOR 1, L_0x185d3f0, L_0x1862920, C4<0>, C4<0>; +L_0x185d4b0 .delay 1 (20000,20000,20000) L_0x185d4b0/d; +L_0x185d660/d .functor AND 1, L_0x185d1c0, L_0x185d260, C4<1>, C4<1>; +L_0x185d660 .delay 1 (20000,20000,20000) L_0x185d660/d; +L_0x185d7c0/d .functor AND 1, L_0x185d3f0, L_0x1862920, C4<1>, C4<1>; +L_0x185d7c0 .delay 1 (20000,20000,20000) L_0x185d7c0/d; +L_0x185d920/d .functor OR 1, L_0x185d7c0, L_0x185d660, C4<0>, C4<0>; +L_0x185d920 .delay 1 (20000,20000,20000) L_0x185d920/d; +v0x17abb70_0 .net "AandB", 0 0, L_0x185d660; 1 drivers +v0x17abc30_0 .net "AxorB", 0 0, L_0x185d3f0; 1 drivers +v0x17abcf0_0 .net "AxorBandCarryIn", 0 0, L_0x185d7c0; 1 drivers +v0x17abdc0_0 .net "a", 0 0, L_0x185d1c0; alias, 1 drivers +v0x17abe80_0 .net "b", 0 0, L_0x185d260; alias, 1 drivers +v0x17abf90_0 .net "bnew", 0 0, L_0x185cf30; 1 drivers +v0x17ac050_0 .net "carryin", 0 0, L_0x1862920; alias, 1 drivers +v0x17ac110_0 .net "carryout", 0 0, L_0x185d920; alias, 1 drivers +v0x17ac1d0_0 .net "sub", 0 0, v0x17dbbc0_0; alias, 1 drivers +v0x17ac300_0 .net "sum", 0 0, L_0x185d4b0; 1 drivers +S_0x17ad190 .scope generate, "ripple[25]" "ripple[25]" 3 66, 3 66 0, S_0x16fa6c0; + .timescale -9 -12; +P_0x17ad360 .param/l "i" 0 3 66, +C4<011001>; +S_0x17ad420 .scope module, "bit" "BitSliceALU" 3 68, 3 11 0, S_0x17ad190; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "ALUout" + .port_info 1 /OUTPUT 1 "Cout" + .port_info 2 /INPUT 1 "invertB" + .port_info 3 /INPUT 1 "Cin" + .port_info 4 /INPUT 3 "addr" + .port_info 5 /INPUT 1 "bit1" + .port_info 6 /INPUT 1 "bit2" +L_0x1863460/d .functor XOR 1, L_0x1868390, L_0x1862da0, C4<0>, C4<0>; +L_0x1863460 .delay 1 (20000,20000,20000) L_0x1863460/d; +L_0x18635c0/d .functor NAND 1, L_0x1868390, L_0x1862da0, C4<1>, C4<1>; +L_0x18635c0 .delay 1 (10000,10000,10000) L_0x18635c0/d; +L_0x1863720/d .functor XOR 1, v0x17dbbc0_0, L_0x18635c0, C4<0>, C4<0>; +L_0x1863720 .delay 1 (20000,20000,20000) L_0x1863720/d; +L_0x1863830/d .functor NOR 1, L_0x1868390, L_0x1862da0, C4<0>, C4<0>; +L_0x1863830 .delay 1 (10000,10000,10000) L_0x1863830/d; +L_0x1863990/d .functor XOR 1, v0x17dbbc0_0, L_0x1863830, C4<0>, C4<0>; +L_0x1863990 .delay 1 (20000,20000,20000) L_0x1863990/d; +v0x17b2bf0_0 .net "ALUout", 0 0, L_0x1867ff0; 1 drivers +v0x17b2cb0_0 .net "Cin", 0 0, L_0x1868260; 1 drivers +v0x17b2d70_0 .net "Cout", 0 0, L_0x18632b0; 1 drivers +v0x17b2e40_0 .net *"_s11", 0 0, L_0x1863990; 1 drivers +o0x7fc2cd92cb28 .functor BUFZ 1, C4; HiZ drive +; Elide local net with no drivers, v0x17b2ee0_0 name=_s15 +o0x7fc2cd92cb58 .functor BUFZ 3, C4; HiZ drive +; Elide local net with no drivers, v0x17b2fd0_0 name=_s17 +v0x17b30b0_0 .net *"_s3", 0 0, L_0x1863460; 1 drivers +v0x17b3190_0 .net *"_s7", 0 0, L_0x1863720; 1 drivers +v0x17b3270_0 .net "addr", 2 0, v0x17dbc90_0; alias, 1 drivers +v0x17b33c0_0 .net "bit1", 0 0, L_0x1868390; 1 drivers +v0x17b3460_0 .net "bit2", 0 0, L_0x1862da0; 1 drivers +v0x17b3530_0 .net "invertB", 0 0, v0x17dbbc0_0; alias, 1 drivers +v0x17b35d0_0 .net "nanded", 0 0, L_0x18635c0; 1 drivers +v0x17b3670_0 .net "nored", 0 0, L_0x1863830; 1 drivers +v0x17b3710_0 .net "out", 7 0, L_0x18944b0; 1 drivers +LS_0x18944b0_0_0 .concat [ 1 1 1 1], L_0x1862c00, L_0x1863460, o0x7fc2cd92cb28, L_0x1863720; +LS_0x18944b0_0_4 .concat [ 1 3 0 0], L_0x1863990, o0x7fc2cd92cb58; +L_0x18944b0 .concat [ 4 4 0 0], LS_0x18944b0_0_0, LS_0x18944b0_0_4; +S_0x17ad6b0 .scope module, "opmux" "structuralMultiplexer" 3 43, 4 21 0, S_0x17ad420; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 3 "address" + .port_info 2 /INPUT 8 "in" +v0x17b1b90_0 .net "address", 2 0, v0x17dbc90_0; alias, 1 drivers +v0x17b1c50_0 .net "in", 7 0, L_0x18944b0; alias, 1 drivers +v0x17b1d30_0 .net "mux", 3 0, L_0x18660b0; 1 drivers +v0x17b1df0_0 .net "muxmid", 1 0, L_0x1867620; 1 drivers +v0x17b1eb0_0 .net "out", 0 0, L_0x1867ff0; alias, 1 drivers +L_0x1864290 .part v0x17dbc90_0, 0, 1; +L_0x18643f0 .part L_0x18944b0, 0, 2; +L_0x1864cd0 .part v0x17dbc90_0, 0, 1; +L_0x1864e30 .part L_0x18944b0, 2, 2; +L_0x18656a0 .part v0x17dbc90_0, 0, 1; +L_0x1865800 .part L_0x18944b0, 4, 2; +L_0x18660b0 .concat8 [ 1 1 1 1], L_0x1864130, L_0x1864b70, L_0x1865540, L_0x1865f50; +L_0x1866300 .part v0x17dbc90_0, 0, 1; +L_0x18663f0 .part L_0x18944b0, 6, 2; +L_0x1866c30 .part v0x17dbc90_0, 1, 1; +L_0x1866d90 .part L_0x18660b0, 0, 2; +L_0x1867620 .concat8 [ 1 1 0 0], L_0x1866ad0, L_0x18674c0; +L_0x1867820 .part v0x17dbc90_0, 1, 1; +L_0x18678c0 .part L_0x18660b0, 2, 2; +L_0x1868100 .part v0x17dbc90_0, 2, 1; +S_0x17ad920 .scope module, "mux_0" "bitMultiplexer" 4 29, 4 8 0, S_0x17ad6b0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "addr" + .port_info 2 /INPUT 2 "in" +L_0x1863aa0/d .functor NOT 1, L_0x1864290, C4<0>, C4<0>, C4<0>; +L_0x1863aa0 .delay 1 (10000,10000,10000) L_0x1863aa0/d; +L_0x1863c00/d .functor AND 1, L_0x1863d10, L_0x1863aa0, C4<1>, C4<1>; +L_0x1863c00 .delay 1 (20000,20000,20000) L_0x1863c00/d; +L_0x1863e70/d .functor AND 1, L_0x1863f80, L_0x1864290, C4<1>, C4<1>; +L_0x1863e70 .delay 1 (20000,20000,20000) L_0x1863e70/d; +L_0x1864130/d .functor OR 1, L_0x1863c00, L_0x1863e70, C4<0>, C4<0>; +L_0x1864130 .delay 1 (20000,20000,20000) L_0x1864130/d; +v0x17adb90_0 .net *"_s1", 0 0, L_0x1863d10; 1 drivers +v0x17adc90_0 .net *"_s3", 0 0, L_0x1863f80; 1 drivers +v0x17add70_0 .net "addr", 0 0, L_0x1864290; 1 drivers +v0x17ade40_0 .net "in", 1 0, L_0x18643f0; 1 drivers +v0x17adf20_0 .net "naddr", 0 0, L_0x1863aa0; 1 drivers +v0x17ae030_0 .net "o0", 0 0, L_0x1863c00; 1 drivers +v0x17ae0f0_0 .net "o1", 0 0, L_0x1863e70; 1 drivers +v0x17ae1b0_0 .net "out", 0 0, L_0x1864130; 1 drivers +L_0x1863d10 .part L_0x18643f0, 0, 1; +L_0x1863f80 .part L_0x18643f0, 1, 1; +S_0x17ae2f0 .scope module, "mux_1" "bitMultiplexer" 4 30, 4 8 0, S_0x17ad6b0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "addr" + .port_info 2 /INPUT 2 "in" +L_0x1864490/d .functor NOT 1, L_0x1864cd0, C4<0>, C4<0>, C4<0>; +L_0x1864490 .delay 1 (10000,10000,10000) L_0x1864490/d; +L_0x1864550/d .functor AND 1, L_0x1864750, L_0x1864490, C4<1>, C4<1>; +L_0x1864550 .delay 1 (20000,20000,20000) L_0x1864550/d; +L_0x18648b0/d .functor AND 1, L_0x18649c0, L_0x1864cd0, C4<1>, C4<1>; +L_0x18648b0 .delay 1 (20000,20000,20000) L_0x18648b0/d; +L_0x1864b70/d .functor OR 1, L_0x1864550, L_0x18648b0, C4<0>, C4<0>; +L_0x1864b70 .delay 1 (20000,20000,20000) L_0x1864b70/d; +v0x17ae520_0 .net *"_s1", 0 0, L_0x1864750; 1 drivers +v0x17ae620_0 .net *"_s3", 0 0, L_0x18649c0; 1 drivers +v0x17ae700_0 .net "addr", 0 0, L_0x1864cd0; 1 drivers +v0x17ae7a0_0 .net "in", 1 0, L_0x1864e30; 1 drivers +v0x17ae880_0 .net "naddr", 0 0, L_0x1864490; 1 drivers +v0x17ae990_0 .net "o0", 0 0, L_0x1864550; 1 drivers +v0x17aea50_0 .net "o1", 0 0, L_0x18648b0; 1 drivers +v0x17aeb10_0 .net "out", 0 0, L_0x1864b70; 1 drivers +L_0x1864750 .part L_0x1864e30, 0, 1; +L_0x18649c0 .part L_0x1864e30, 1, 1; +S_0x17aec50 .scope module, "mux_2" "bitMultiplexer" 4 31, 4 8 0, S_0x17ad6b0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "addr" + .port_info 2 /INPUT 2 "in" +L_0x1864d70/d .functor NOT 1, L_0x18656a0, C4<0>, C4<0>, C4<0>; +L_0x1864d70 .delay 1 (10000,10000,10000) L_0x1864d70/d; +L_0x1864f20/d .functor AND 1, L_0x1865120, L_0x1864d70, C4<1>, C4<1>; +L_0x1864f20 .delay 1 (20000,20000,20000) L_0x1864f20/d; +L_0x1865280/d .functor AND 1, L_0x1865390, L_0x18656a0, C4<1>, C4<1>; +L_0x1865280 .delay 1 (20000,20000,20000) L_0x1865280/d; +L_0x1865540/d .functor OR 1, L_0x1864f20, L_0x1865280, C4<0>, C4<0>; +L_0x1865540 .delay 1 (20000,20000,20000) L_0x1865540/d; +v0x17aee80_0 .net *"_s1", 0 0, L_0x1865120; 1 drivers +v0x17aef60_0 .net *"_s3", 0 0, L_0x1865390; 1 drivers +v0x17af040_0 .net "addr", 0 0, L_0x18656a0; 1 drivers +v0x17af110_0 .net "in", 1 0, L_0x1865800; 1 drivers +v0x17af1f0_0 .net "naddr", 0 0, L_0x1864d70; 1 drivers +v0x17af300_0 .net "o0", 0 0, L_0x1864f20; 1 drivers +v0x17af3c0_0 .net "o1", 0 0, L_0x1865280; 1 drivers +v0x17af480_0 .net "out", 0 0, L_0x1865540; 1 drivers +L_0x1865120 .part L_0x1865800, 0, 1; +L_0x1865390 .part L_0x1865800, 1, 1; +S_0x17af5c0 .scope module, "mux_3" "bitMultiplexer" 4 32, 4 8 0, S_0x17ad6b0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "addr" + .port_info 2 /INPUT 2 "in" +L_0x1865740/d .functor NOT 1, L_0x1866300, C4<0>, C4<0>, C4<0>; +L_0x1865740 .delay 1 (10000,10000,10000) L_0x1865740/d; +L_0x1865930/d .functor AND 1, L_0x1865b30, L_0x1865740, C4<1>, C4<1>; +L_0x1865930 .delay 1 (20000,20000,20000) L_0x1865930/d; +L_0x1865c90/d .functor AND 1, L_0x1865da0, L_0x1866300, C4<1>, C4<1>; +L_0x1865c90 .delay 1 (20000,20000,20000) L_0x1865c90/d; +L_0x1865f50/d .functor OR 1, L_0x1865930, L_0x1865c90, C4<0>, C4<0>; +L_0x1865f50 .delay 1 (20000,20000,20000) L_0x1865f50/d; +v0x17af7f0_0 .net *"_s1", 0 0, L_0x1865b30; 1 drivers +v0x17af8f0_0 .net *"_s3", 0 0, L_0x1865da0; 1 drivers +v0x17af9d0_0 .net "addr", 0 0, L_0x1866300; 1 drivers +v0x17afa70_0 .net "in", 1 0, L_0x18663f0; 1 drivers +v0x17afb50_0 .net "naddr", 0 0, L_0x1865740; 1 drivers +v0x17afc60_0 .net "o0", 0 0, L_0x1865930; 1 drivers +v0x17afd20_0 .net "o1", 0 0, L_0x1865c90; 1 drivers +v0x17afde0_0 .net "out", 0 0, L_0x1865f50; 1 drivers +L_0x1865b30 .part L_0x18663f0, 0, 1; +L_0x1865da0 .part L_0x18663f0, 1, 1; +S_0x17aff20 .scope module, "mux_mid_0" "bitMultiplexer" 4 33, 4 8 0, S_0x17ad6b0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "addr" + .port_info 2 /INPUT 2 "in" +L_0x1866490/d .functor NOT 1, L_0x1866c30, C4<0>, C4<0>, C4<0>; +L_0x1866490 .delay 1 (10000,10000,10000) L_0x1866490/d; +L_0x1866550/d .functor AND 1, L_0x18666b0, L_0x1866490, C4<1>, C4<1>; +L_0x1866550 .delay 1 (20000,20000,20000) L_0x1866550/d; +L_0x1866810/d .functor AND 1, L_0x1866920, L_0x1866c30, C4<1>, C4<1>; +L_0x1866810 .delay 1 (20000,20000,20000) L_0x1866810/d; +L_0x1866ad0/d .functor OR 1, L_0x1866550, L_0x1866810, C4<0>, C4<0>; +L_0x1866ad0 .delay 1 (20000,20000,20000) L_0x1866ad0/d; +v0x17b01a0_0 .net *"_s1", 0 0, L_0x18666b0; 1 drivers +v0x17b02a0_0 .net *"_s3", 0 0, L_0x1866920; 1 drivers +v0x17b0380_0 .net "addr", 0 0, L_0x1866c30; 1 drivers +v0x17b0420_0 .net "in", 1 0, L_0x1866d90; 1 drivers +v0x17b0500_0 .net "naddr", 0 0, L_0x1866490; 1 drivers +v0x17b0610_0 .net "o0", 0 0, L_0x1866550; 1 drivers +v0x17b06d0_0 .net "o1", 0 0, L_0x1866810; 1 drivers +v0x17b0790_0 .net "out", 0 0, L_0x1866ad0; 1 drivers +L_0x18666b0 .part L_0x1866d90, 0, 1; +L_0x1866920 .part L_0x1866d90, 1, 1; +S_0x17b08d0 .scope module, "mux_mid_1" "bitMultiplexer" 4 34, 4 8 0, S_0x17ad6b0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "addr" + .port_info 2 /INPUT 2 "in" +L_0x1866e30/d .functor NOT 1, L_0x1867820, C4<0>, C4<0>, C4<0>; +L_0x1866e30 .delay 1 (10000,10000,10000) L_0x1866e30/d; +L_0x1866ef0/d .functor AND 1, L_0x18670a0, L_0x1866e30, C4<1>, C4<1>; +L_0x1866ef0 .delay 1 (20000,20000,20000) L_0x1866ef0/d; +L_0x1867200/d .functor AND 1, L_0x1867310, L_0x1867820, C4<1>, C4<1>; +L_0x1867200 .delay 1 (20000,20000,20000) L_0x1867200/d; +L_0x18674c0/d .functor OR 1, L_0x1866ef0, L_0x1867200, C4<0>, C4<0>; +L_0x18674c0 .delay 1 (20000,20000,20000) L_0x18674c0/d; +v0x17b0b00_0 .net *"_s1", 0 0, L_0x18670a0; 1 drivers +v0x17b0c00_0 .net *"_s3", 0 0, L_0x1867310; 1 drivers +v0x17b0ce0_0 .net "addr", 0 0, L_0x1867820; 1 drivers +v0x17b0d80_0 .net "in", 1 0, L_0x18678c0; 1 drivers +v0x17b0e60_0 .net "naddr", 0 0, L_0x1866e30; 1 drivers +v0x17b0f70_0 .net "o0", 0 0, L_0x1866ef0; 1 drivers +v0x17b1030_0 .net "o1", 0 0, L_0x1867200; 1 drivers +v0x17b10f0_0 .net "out", 0 0, L_0x18674c0; 1 drivers +L_0x18670a0 .part L_0x18678c0, 0, 1; +L_0x1867310 .part L_0x18678c0, 1, 1; +S_0x17b1230 .scope module, "mux_out" "bitMultiplexer" 4 35, 4 8 0, S_0x17ad6b0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "addr" + .port_info 2 /INPUT 2 "in" +L_0x1866cd0/d .functor NOT 1, L_0x1868100, C4<0>, C4<0>, C4<0>; +L_0x1866cd0 .delay 1 (10000,10000,10000) L_0x1866cd0/d; +L_0x1867a30/d .functor AND 1, L_0x1867b90, L_0x1866cd0, C4<1>, C4<1>; +L_0x1867a30 .delay 1 (20000,20000,20000) L_0x1867a30/d; +L_0x1867cf0/d .functor AND 1, L_0x1867e00, L_0x1868100, C4<1>, C4<1>; +L_0x1867cf0 .delay 1 (20000,20000,20000) L_0x1867cf0/d; +L_0x1867ff0/d .functor OR 1, L_0x1867a30, L_0x1867cf0, C4<0>, C4<0>; +L_0x1867ff0 .delay 1 (20000,20000,20000) L_0x1867ff0/d; +v0x17b1460_0 .net *"_s1", 0 0, L_0x1867b90; 1 drivers +v0x17b1560_0 .net *"_s3", 0 0, L_0x1867e00; 1 drivers +v0x17b1640_0 .net "addr", 0 0, L_0x1868100; 1 drivers +v0x17b16e0_0 .net "in", 1 0, L_0x1867620; alias, 1 drivers +v0x17b17c0_0 .net "naddr", 0 0, L_0x1866cd0; 1 drivers +v0x17b18d0_0 .net "o0", 0 0, L_0x1867a30; 1 drivers +v0x17b1990_0 .net "o1", 0 0, L_0x1867cf0; 1 drivers +v0x17b1a50_0 .net "out", 0 0, L_0x1867ff0; alias, 1 drivers +L_0x1867b90 .part L_0x1867620, 0, 1; +L_0x1867e00 .part L_0x1867620, 1, 1; +S_0x17b1fe0 .scope module, "structadder" "structAddSub" 3 22, 5 8 0, S_0x17ad420; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "sub" + .port_info 5 /INPUT 1 "carryin" +L_0x1862860/d .functor XOR 1, L_0x1862da0, v0x17dbbc0_0, C4<0>, C4<0>; +L_0x1862860 .delay 1 (20000,20000,20000) L_0x1862860/d; +L_0x185d300/d .functor XOR 1, L_0x1868390, L_0x1862da0, C4<0>, C4<0>; +L_0x185d300 .delay 1 (20000,20000,20000) L_0x185d300/d; +L_0x1862c00/d .functor XOR 1, L_0x185d300, L_0x1868260, C4<0>, C4<0>; +L_0x1862c00 .delay 1 (20000,20000,20000) L_0x1862c00/d; +L_0x1862ff0/d .functor AND 1, L_0x1868390, L_0x1862da0, C4<1>, C4<1>; +L_0x1862ff0 .delay 1 (20000,20000,20000) L_0x1862ff0/d; +L_0x1863150/d .functor AND 1, L_0x185d300, L_0x1868260, C4<1>, C4<1>; +L_0x1863150 .delay 1 (20000,20000,20000) L_0x1863150/d; +L_0x18632b0/d .functor OR 1, L_0x1863150, L_0x1862ff0, C4<0>, C4<0>; +L_0x18632b0 .delay 1 (20000,20000,20000) L_0x18632b0/d; +v0x17b22a0_0 .net "AandB", 0 0, L_0x1862ff0; 1 drivers +v0x17b2360_0 .net "AxorB", 0 0, L_0x185d300; 1 drivers +v0x17b2420_0 .net "AxorBandCarryIn", 0 0, L_0x1863150; 1 drivers +v0x17b24f0_0 .net "a", 0 0, L_0x1868390; alias, 1 drivers +v0x17b25b0_0 .net "b", 0 0, L_0x1862da0; alias, 1 drivers +v0x17b26c0_0 .net "bnew", 0 0, L_0x1862860; 1 drivers +v0x17b2780_0 .net "carryin", 0 0, L_0x1868260; alias, 1 drivers +v0x17b2840_0 .net "carryout", 0 0, L_0x18632b0; alias, 1 drivers +v0x17b2900_0 .net "sub", 0 0, v0x17dbbc0_0; alias, 1 drivers +v0x17b2a30_0 .net "sum", 0 0, L_0x1862c00; 1 drivers +S_0x17b38c0 .scope generate, "ripple[26]" "ripple[26]" 3 66, 3 66 0, S_0x16fa6c0; + .timescale -9 -12; +P_0x17b3a90 .param/l "i" 0 3 66, +C4<011010>; +S_0x17b3b50 .scope module, "bit" "BitSliceALU" 3 68, 3 11 0, S_0x17b38c0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "ALUout" + .port_info 1 /OUTPUT 1 "Cout" + .port_info 2 /INPUT 1 "invertB" + .port_info 3 /INPUT 1 "Cin" + .port_info 4 /INPUT 3 "addr" + .port_info 5 /INPUT 1 "bit1" + .port_info 6 /INPUT 1 "bit2" +L_0x1868d50/d .functor XOR 1, L_0x1868430, L_0x18684d0, C4<0>, C4<0>; +L_0x1868d50 .delay 1 (20000,20000,20000) L_0x1868d50/d; +L_0x1868eb0/d .functor NAND 1, L_0x1868430, L_0x18684d0, C4<1>, C4<1>; +L_0x1868eb0 .delay 1 (10000,10000,10000) L_0x1868eb0/d; +L_0x1869010/d .functor XOR 1, v0x17dbbc0_0, L_0x1868eb0, C4<0>, C4<0>; +L_0x1869010 .delay 1 (20000,20000,20000) L_0x1869010/d; +L_0x1869120/d .functor NOR 1, L_0x1868430, L_0x18684d0, C4<0>, C4<0>; +L_0x1869120 .delay 1 (10000,10000,10000) L_0x1869120/d; +L_0x1869280/d .functor XOR 1, v0x17dbbc0_0, L_0x1869120, C4<0>, C4<0>; +L_0x1869280 .delay 1 (20000,20000,20000) L_0x1869280/d; +v0x17b9320_0 .net "ALUout", 0 0, L_0x186d8e0; 1 drivers +v0x17b93e0_0 .net "Cin", 0 0, L_0x186db50; 1 drivers +v0x17b94a0_0 .net "Cout", 0 0, L_0x1868ba0; 1 drivers +v0x17b9570_0 .net *"_s11", 0 0, L_0x1869280; 1 drivers +o0x7fc2cd92dff8 .functor BUFZ 1, C4; HiZ drive +; Elide local net with no drivers, v0x17b9610_0 name=_s15 +o0x7fc2cd92e028 .functor BUFZ 3, C4; HiZ drive +; Elide local net with no drivers, v0x17b9700_0 name=_s17 +v0x17b97e0_0 .net *"_s3", 0 0, L_0x1868d50; 1 drivers +v0x17b98c0_0 .net *"_s7", 0 0, L_0x1869010; 1 drivers +v0x17b99a0_0 .net "addr", 2 0, v0x17dbc90_0; alias, 1 drivers +v0x17b9af0_0 .net "bit1", 0 0, L_0x1868430; 1 drivers +v0x17b9b90_0 .net "bit2", 0 0, L_0x18684d0; 1 drivers +v0x17b9c60_0 .net "invertB", 0 0, v0x17dbbc0_0; alias, 1 drivers +v0x17b9d00_0 .net "nanded", 0 0, L_0x1868eb0; 1 drivers +v0x17b9da0_0 .net "nored", 0 0, L_0x1869120; 1 drivers +v0x17b9e40_0 .net "out", 7 0, L_0x1894690; 1 drivers +LS_0x1894690_0_0 .concat [ 1 1 1 1], L_0x1868730, L_0x1868d50, o0x7fc2cd92dff8, L_0x1869010; +LS_0x1894690_0_4 .concat [ 1 3 0 0], L_0x1869280, o0x7fc2cd92e028; +L_0x1894690 .concat [ 4 4 0 0], LS_0x1894690_0_0, LS_0x1894690_0_4; +S_0x17b3de0 .scope module, "opmux" "structuralMultiplexer" 3 43, 4 21 0, S_0x17b3b50; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 3 "address" + .port_info 2 /INPUT 8 "in" +v0x17b82c0_0 .net "address", 2 0, v0x17dbc90_0; alias, 1 drivers +v0x17b8380_0 .net "in", 7 0, L_0x1894690; alias, 1 drivers +v0x17b8460_0 .net "mux", 3 0, L_0x186b9a0; 1 drivers +v0x17b8520_0 .net "muxmid", 1 0, L_0x186cf10; 1 drivers +v0x17b85e0_0 .net "out", 0 0, L_0x186d8e0; alias, 1 drivers +L_0x1869b80 .part v0x17dbc90_0, 0, 1; +L_0x1869ce0 .part L_0x1894690, 0, 2; +L_0x186a5c0 .part v0x17dbc90_0, 0, 1; +L_0x186a720 .part L_0x1894690, 2, 2; +L_0x186af90 .part v0x17dbc90_0, 0, 1; +L_0x186b0f0 .part L_0x1894690, 4, 2; +L_0x186b9a0 .concat8 [ 1 1 1 1], L_0x1869a20, L_0x186a460, L_0x186ae30, L_0x186b840; +L_0x186bbf0 .part v0x17dbc90_0, 0, 1; +L_0x186bce0 .part L_0x1894690, 6, 2; +L_0x186c520 .part v0x17dbc90_0, 1, 1; +L_0x186c680 .part L_0x186b9a0, 0, 2; +L_0x186cf10 .concat8 [ 1 1 0 0], L_0x186c3c0, L_0x186cdb0; +L_0x186d110 .part v0x17dbc90_0, 1, 1; +L_0x186d1b0 .part L_0x186b9a0, 2, 2; +L_0x186d9f0 .part v0x17dbc90_0, 2, 1; +S_0x17b4050 .scope module, "mux_0" "bitMultiplexer" 4 29, 4 8 0, S_0x17b3de0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "addr" + .port_info 2 /INPUT 2 "in" +L_0x1869390/d .functor NOT 1, L_0x1869b80, C4<0>, C4<0>, C4<0>; +L_0x1869390 .delay 1 (10000,10000,10000) L_0x1869390/d; +L_0x18694f0/d .functor AND 1, L_0x1869600, L_0x1869390, C4<1>, C4<1>; +L_0x18694f0 .delay 1 (20000,20000,20000) L_0x18694f0/d; +L_0x1869760/d .functor AND 1, L_0x1869870, L_0x1869b80, C4<1>, C4<1>; +L_0x1869760 .delay 1 (20000,20000,20000) L_0x1869760/d; +L_0x1869a20/d .functor OR 1, L_0x18694f0, L_0x1869760, C4<0>, C4<0>; +L_0x1869a20 .delay 1 (20000,20000,20000) L_0x1869a20/d; +v0x17b42c0_0 .net *"_s1", 0 0, L_0x1869600; 1 drivers +v0x17b43c0_0 .net *"_s3", 0 0, L_0x1869870; 1 drivers +v0x17b44a0_0 .net "addr", 0 0, L_0x1869b80; 1 drivers +v0x17b4570_0 .net "in", 1 0, L_0x1869ce0; 1 drivers +v0x17b4650_0 .net "naddr", 0 0, L_0x1869390; 1 drivers +v0x17b4760_0 .net "o0", 0 0, L_0x18694f0; 1 drivers +v0x17b4820_0 .net "o1", 0 0, L_0x1869760; 1 drivers +v0x17b48e0_0 .net "out", 0 0, L_0x1869a20; 1 drivers +L_0x1869600 .part L_0x1869ce0, 0, 1; +L_0x1869870 .part L_0x1869ce0, 1, 1; +S_0x17b4a20 .scope module, "mux_1" "bitMultiplexer" 4 30, 4 8 0, S_0x17b3de0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "addr" + .port_info 2 /INPUT 2 "in" +L_0x1869d80/d .functor NOT 1, L_0x186a5c0, C4<0>, C4<0>, C4<0>; +L_0x1869d80 .delay 1 (10000,10000,10000) L_0x1869d80/d; +L_0x1869e40/d .functor AND 1, L_0x186a040, L_0x1869d80, C4<1>, C4<1>; +L_0x1869e40 .delay 1 (20000,20000,20000) L_0x1869e40/d; +L_0x186a1a0/d .functor AND 1, L_0x186a2b0, L_0x186a5c0, C4<1>, C4<1>; +L_0x186a1a0 .delay 1 (20000,20000,20000) L_0x186a1a0/d; +L_0x186a460/d .functor OR 1, L_0x1869e40, L_0x186a1a0, C4<0>, C4<0>; +L_0x186a460 .delay 1 (20000,20000,20000) L_0x186a460/d; +v0x17b4c50_0 .net *"_s1", 0 0, L_0x186a040; 1 drivers +v0x17b4d50_0 .net *"_s3", 0 0, L_0x186a2b0; 1 drivers +v0x17b4e30_0 .net "addr", 0 0, L_0x186a5c0; 1 drivers +v0x17b4ed0_0 .net "in", 1 0, L_0x186a720; 1 drivers +v0x17b4fb0_0 .net "naddr", 0 0, L_0x1869d80; 1 drivers +v0x17b50c0_0 .net "o0", 0 0, L_0x1869e40; 1 drivers +v0x17b5180_0 .net "o1", 0 0, L_0x186a1a0; 1 drivers +v0x17b5240_0 .net "out", 0 0, L_0x186a460; 1 drivers +L_0x186a040 .part L_0x186a720, 0, 1; +L_0x186a2b0 .part L_0x186a720, 1, 1; +S_0x17b5380 .scope module, "mux_2" "bitMultiplexer" 4 31, 4 8 0, S_0x17b3de0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "addr" + .port_info 2 /INPUT 2 "in" +L_0x186a660/d .functor NOT 1, L_0x186af90, C4<0>, C4<0>, C4<0>; +L_0x186a660 .delay 1 (10000,10000,10000) L_0x186a660/d; +L_0x186a810/d .functor AND 1, L_0x186aa10, L_0x186a660, C4<1>, C4<1>; +L_0x186a810 .delay 1 (20000,20000,20000) L_0x186a810/d; +L_0x186ab70/d .functor AND 1, L_0x186ac80, L_0x186af90, C4<1>, C4<1>; +L_0x186ab70 .delay 1 (20000,20000,20000) L_0x186ab70/d; +L_0x186ae30/d .functor OR 1, L_0x186a810, L_0x186ab70, C4<0>, C4<0>; +L_0x186ae30 .delay 1 (20000,20000,20000) L_0x186ae30/d; +v0x17b55b0_0 .net *"_s1", 0 0, L_0x186aa10; 1 drivers +v0x17b5690_0 .net *"_s3", 0 0, L_0x186ac80; 1 drivers +v0x17b5770_0 .net "addr", 0 0, L_0x186af90; 1 drivers +v0x17b5840_0 .net "in", 1 0, L_0x186b0f0; 1 drivers +v0x17b5920_0 .net "naddr", 0 0, L_0x186a660; 1 drivers +v0x17b5a30_0 .net "o0", 0 0, L_0x186a810; 1 drivers +v0x17b5af0_0 .net "o1", 0 0, L_0x186ab70; 1 drivers +v0x17b5bb0_0 .net "out", 0 0, L_0x186ae30; 1 drivers +L_0x186aa10 .part L_0x186b0f0, 0, 1; +L_0x186ac80 .part L_0x186b0f0, 1, 1; +S_0x17b5cf0 .scope module, "mux_3" "bitMultiplexer" 4 32, 4 8 0, S_0x17b3de0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "addr" + .port_info 2 /INPUT 2 "in" +L_0x186b030/d .functor NOT 1, L_0x186bbf0, C4<0>, C4<0>, C4<0>; +L_0x186b030 .delay 1 (10000,10000,10000) L_0x186b030/d; +L_0x186b220/d .functor AND 1, L_0x186b420, L_0x186b030, C4<1>, C4<1>; +L_0x186b220 .delay 1 (20000,20000,20000) L_0x186b220/d; +L_0x186b580/d .functor AND 1, L_0x186b690, L_0x186bbf0, C4<1>, C4<1>; +L_0x186b580 .delay 1 (20000,20000,20000) L_0x186b580/d; +L_0x186b840/d .functor OR 1, L_0x186b220, L_0x186b580, C4<0>, C4<0>; +L_0x186b840 .delay 1 (20000,20000,20000) L_0x186b840/d; +v0x17b5f20_0 .net *"_s1", 0 0, L_0x186b420; 1 drivers +v0x17b6020_0 .net *"_s3", 0 0, L_0x186b690; 1 drivers +v0x17b6100_0 .net "addr", 0 0, L_0x186bbf0; 1 drivers +v0x17b61a0_0 .net "in", 1 0, L_0x186bce0; 1 drivers +v0x17b6280_0 .net "naddr", 0 0, L_0x186b030; 1 drivers +v0x17b6390_0 .net "o0", 0 0, L_0x186b220; 1 drivers +v0x17b6450_0 .net "o1", 0 0, L_0x186b580; 1 drivers +v0x17b6510_0 .net "out", 0 0, L_0x186b840; 1 drivers +L_0x186b420 .part L_0x186bce0, 0, 1; +L_0x186b690 .part L_0x186bce0, 1, 1; +S_0x17b6650 .scope module, "mux_mid_0" "bitMultiplexer" 4 33, 4 8 0, S_0x17b3de0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "addr" + .port_info 2 /INPUT 2 "in" +L_0x186bd80/d .functor NOT 1, L_0x186c520, C4<0>, C4<0>, C4<0>; +L_0x186bd80 .delay 1 (10000,10000,10000) L_0x186bd80/d; +L_0x186be40/d .functor AND 1, L_0x186bfa0, L_0x186bd80, C4<1>, C4<1>; +L_0x186be40 .delay 1 (20000,20000,20000) L_0x186be40/d; +L_0x186c100/d .functor AND 1, L_0x186c210, L_0x186c520, C4<1>, C4<1>; +L_0x186c100 .delay 1 (20000,20000,20000) L_0x186c100/d; +L_0x186c3c0/d .functor OR 1, L_0x186be40, L_0x186c100, C4<0>, C4<0>; +L_0x186c3c0 .delay 1 (20000,20000,20000) L_0x186c3c0/d; +v0x17b68d0_0 .net *"_s1", 0 0, L_0x186bfa0; 1 drivers +v0x17b69d0_0 .net *"_s3", 0 0, L_0x186c210; 1 drivers +v0x17b6ab0_0 .net "addr", 0 0, L_0x186c520; 1 drivers +v0x17b6b50_0 .net "in", 1 0, L_0x186c680; 1 drivers +v0x17b6c30_0 .net "naddr", 0 0, L_0x186bd80; 1 drivers +v0x17b6d40_0 .net "o0", 0 0, L_0x186be40; 1 drivers +v0x17b6e00_0 .net "o1", 0 0, L_0x186c100; 1 drivers +v0x17b6ec0_0 .net "out", 0 0, L_0x186c3c0; 1 drivers +L_0x186bfa0 .part L_0x186c680, 0, 1; +L_0x186c210 .part L_0x186c680, 1, 1; +S_0x17b7000 .scope module, "mux_mid_1" "bitMultiplexer" 4 34, 4 8 0, S_0x17b3de0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "addr" + .port_info 2 /INPUT 2 "in" +L_0x186c720/d .functor NOT 1, L_0x186d110, C4<0>, C4<0>, C4<0>; +L_0x186c720 .delay 1 (10000,10000,10000) L_0x186c720/d; +L_0x186c7e0/d .functor AND 1, L_0x186c990, L_0x186c720, C4<1>, C4<1>; +L_0x186c7e0 .delay 1 (20000,20000,20000) L_0x186c7e0/d; +L_0x186caf0/d .functor AND 1, L_0x186cc00, L_0x186d110, C4<1>, C4<1>; +L_0x186caf0 .delay 1 (20000,20000,20000) L_0x186caf0/d; +L_0x186cdb0/d .functor OR 1, L_0x186c7e0, L_0x186caf0, C4<0>, C4<0>; +L_0x186cdb0 .delay 1 (20000,20000,20000) L_0x186cdb0/d; +v0x17b7230_0 .net *"_s1", 0 0, L_0x186c990; 1 drivers +v0x17b7330_0 .net *"_s3", 0 0, L_0x186cc00; 1 drivers +v0x17b7410_0 .net "addr", 0 0, L_0x186d110; 1 drivers +v0x17b74b0_0 .net "in", 1 0, L_0x186d1b0; 1 drivers +v0x17b7590_0 .net "naddr", 0 0, L_0x186c720; 1 drivers +v0x17b76a0_0 .net "o0", 0 0, L_0x186c7e0; 1 drivers +v0x17b7760_0 .net "o1", 0 0, L_0x186caf0; 1 drivers +v0x17b7820_0 .net "out", 0 0, L_0x186cdb0; 1 drivers +L_0x186c990 .part L_0x186d1b0, 0, 1; +L_0x186cc00 .part L_0x186d1b0, 1, 1; +S_0x17b7960 .scope module, "mux_out" "bitMultiplexer" 4 35, 4 8 0, S_0x17b3de0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "addr" + .port_info 2 /INPUT 2 "in" +L_0x186c5c0/d .functor NOT 1, L_0x186d9f0, C4<0>, C4<0>, C4<0>; +L_0x186c5c0 .delay 1 (10000,10000,10000) L_0x186c5c0/d; +L_0x186d320/d .functor AND 1, L_0x186d480, L_0x186c5c0, C4<1>, C4<1>; +L_0x186d320 .delay 1 (20000,20000,20000) L_0x186d320/d; +L_0x186d5e0/d .functor AND 1, L_0x186d6f0, L_0x186d9f0, C4<1>, C4<1>; +L_0x186d5e0 .delay 1 (20000,20000,20000) L_0x186d5e0/d; +L_0x186d8e0/d .functor OR 1, L_0x186d320, L_0x186d5e0, C4<0>, C4<0>; +L_0x186d8e0 .delay 1 (20000,20000,20000) L_0x186d8e0/d; +v0x17b7b90_0 .net *"_s1", 0 0, L_0x186d480; 1 drivers +v0x17b7c90_0 .net *"_s3", 0 0, L_0x186d6f0; 1 drivers +v0x17b7d70_0 .net "addr", 0 0, L_0x186d9f0; 1 drivers +v0x17b7e10_0 .net "in", 1 0, L_0x186cf10; alias, 1 drivers +v0x17b7ef0_0 .net "naddr", 0 0, L_0x186c5c0; 1 drivers +v0x17b8000_0 .net "o0", 0 0, L_0x186d320; 1 drivers +v0x17b80c0_0 .net "o1", 0 0, L_0x186d5e0; 1 drivers +v0x17b8180_0 .net "out", 0 0, L_0x186d8e0; alias, 1 drivers +L_0x186d480 .part L_0x186cf10, 0, 1; +L_0x186d6f0 .part L_0x186cf10, 1, 1; +S_0x17b8710 .scope module, "structadder" "structAddSub" 3 22, 5 8 0, S_0x17b3b50; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "sub" + .port_info 5 /INPUT 1 "carryin" +L_0x18681a0/d .functor XOR 1, L_0x18684d0, v0x17dbbc0_0, C4<0>, C4<0>; +L_0x18681a0 .delay 1 (20000,20000,20000) L_0x18681a0/d; +L_0x1863060/d .functor XOR 1, L_0x1868430, L_0x18684d0, C4<0>, C4<0>; +L_0x1863060 .delay 1 (20000,20000,20000) L_0x1863060/d; +L_0x1868730/d .functor XOR 1, L_0x1863060, L_0x186db50, C4<0>, C4<0>; +L_0x1868730 .delay 1 (20000,20000,20000) L_0x1868730/d; +L_0x18688e0/d .functor AND 1, L_0x1868430, L_0x18684d0, C4<1>, C4<1>; +L_0x18688e0 .delay 1 (20000,20000,20000) L_0x18688e0/d; +L_0x1868a40/d .functor AND 1, L_0x1863060, L_0x186db50, C4<1>, C4<1>; +L_0x1868a40 .delay 1 (20000,20000,20000) L_0x1868a40/d; +L_0x1868ba0/d .functor OR 1, L_0x1868a40, L_0x18688e0, C4<0>, C4<0>; +L_0x1868ba0 .delay 1 (20000,20000,20000) L_0x1868ba0/d; +v0x17b89d0_0 .net "AandB", 0 0, L_0x18688e0; 1 drivers +v0x17b8a90_0 .net "AxorB", 0 0, L_0x1863060; 1 drivers +v0x17b8b50_0 .net "AxorBandCarryIn", 0 0, L_0x1868a40; 1 drivers +v0x17b8c20_0 .net "a", 0 0, L_0x1868430; alias, 1 drivers +v0x17b8ce0_0 .net "b", 0 0, L_0x18684d0; alias, 1 drivers +v0x17b8df0_0 .net "bnew", 0 0, L_0x18681a0; 1 drivers +v0x17b8eb0_0 .net "carryin", 0 0, L_0x186db50; alias, 1 drivers +v0x17b8f70_0 .net "carryout", 0 0, L_0x1868ba0; alias, 1 drivers +v0x17b9030_0 .net "sub", 0 0, v0x17dbbc0_0; alias, 1 drivers +v0x17b9160_0 .net "sum", 0 0, L_0x1868730; 1 drivers +S_0x17b9ff0 .scope generate, "ripple[27]" "ripple[27]" 3 66, 3 66 0, S_0x16fa6c0; + .timescale -9 -12; +P_0x17ba1c0 .param/l "i" 0 3 66, +C4<011011>; +S_0x17ba280 .scope module, "bit" "BitSliceALU" 3 68, 3 11 0, S_0x17b9ff0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "ALUout" + .port_info 1 /OUTPUT 1 "Cout" + .port_info 2 /INPUT 1 "invertB" + .port_info 3 /INPUT 1 "Cin" + .port_info 4 /INPUT 3 "addr" + .port_info 5 /INPUT 1 "bit1" + .port_info 6 /INPUT 1 "bit2" +L_0x186e5c0/d .functor XOR 1, L_0x1873590, L_0x186dc80, C4<0>, C4<0>; +L_0x186e5c0 .delay 1 (20000,20000,20000) L_0x186e5c0/d; +L_0x186e720/d .functor NAND 1, L_0x1873590, L_0x186dc80, C4<1>, C4<1>; +L_0x186e720 .delay 1 (10000,10000,10000) L_0x186e720/d; +L_0x186e880/d .functor XOR 1, v0x17dbbc0_0, L_0x186e720, C4<0>, C4<0>; +L_0x186e880 .delay 1 (20000,20000,20000) L_0x186e880/d; +L_0x186e990/d .functor NOR 1, L_0x1873590, L_0x186dc80, C4<0>, C4<0>; +L_0x186e990 .delay 1 (10000,10000,10000) L_0x186e990/d; +L_0x186eaf0/d .functor XOR 1, v0x17dbbc0_0, L_0x186e990, C4<0>, C4<0>; +L_0x186eaf0 .delay 1 (20000,20000,20000) L_0x186eaf0/d; +v0x17bfa50_0 .net "ALUout", 0 0, L_0x18731f0; 1 drivers +v0x17bfb10_0 .net "Cin", 0 0, L_0x1873460; 1 drivers +v0x17bfbd0_0 .net "Cout", 0 0, L_0x186e410; 1 drivers +v0x17bfca0_0 .net *"_s11", 0 0, L_0x186eaf0; 1 drivers +o0x7fc2cd92f4c8 .functor BUFZ 1, C4; HiZ drive +; Elide local net with no drivers, v0x17bfd40_0 name=_s15 +o0x7fc2cd92f4f8 .functor BUFZ 3, C4; HiZ drive +; Elide local net with no drivers, v0x17bfe30_0 name=_s17 +v0x17bff10_0 .net *"_s3", 0 0, L_0x186e5c0; 1 drivers +v0x17bfff0_0 .net *"_s7", 0 0, L_0x186e880; 1 drivers +v0x17c00d0_0 .net "addr", 2 0, v0x17dbc90_0; alias, 1 drivers +v0x17c0220_0 .net "bit1", 0 0, L_0x1873590; 1 drivers +v0x17c02c0_0 .net "bit2", 0 0, L_0x186dc80; 1 drivers +v0x17c0390_0 .net "invertB", 0 0, v0x17dbbc0_0; alias, 1 drivers +v0x17c0430_0 .net "nanded", 0 0, L_0x186e720; 1 drivers +v0x17c04d0_0 .net "nored", 0 0, L_0x186e990; 1 drivers +v0x17c0570_0 .net "out", 7 0, L_0x1894870; 1 drivers +LS_0x1894870_0_0 .concat [ 1 1 1 1], L_0x186dfa0, L_0x186e5c0, o0x7fc2cd92f4c8, L_0x186e880; +LS_0x1894870_0_4 .concat [ 1 3 0 0], L_0x186eaf0, o0x7fc2cd92f4f8; +L_0x1894870 .concat [ 4 4 0 0], LS_0x1894870_0_0, LS_0x1894870_0_4; +S_0x17ba510 .scope module, "opmux" "structuralMultiplexer" 3 43, 4 21 0, S_0x17ba280; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 3 "address" + .port_info 2 /INPUT 8 "in" +v0x17be9f0_0 .net "address", 2 0, v0x17dbc90_0; alias, 1 drivers +v0x17beab0_0 .net "in", 7 0, L_0x1894870; alias, 1 drivers +v0x17beb90_0 .net "mux", 3 0, L_0x18712b0; 1 drivers +v0x17bec50_0 .net "muxmid", 1 0, L_0x1872820; 1 drivers +v0x17bed10_0 .net "out", 0 0, L_0x18731f0; alias, 1 drivers +L_0x186f4e0 .part v0x17dbc90_0, 0, 1; +L_0x186f640 .part L_0x1894870, 0, 2; +L_0x186fed0 .part v0x17dbc90_0, 0, 1; +L_0x1870030 .part L_0x1894870, 2, 2; +L_0x18708a0 .part v0x17dbc90_0, 0, 1; +L_0x1870a00 .part L_0x1894870, 4, 2; +L_0x18712b0 .concat8 [ 1 1 1 1], L_0x186f380, L_0x186fd70, L_0x1870740, L_0x1871150; +L_0x1871500 .part v0x17dbc90_0, 0, 1; +L_0x18715f0 .part L_0x1894870, 6, 2; +L_0x1871e30 .part v0x17dbc90_0, 1, 1; +L_0x1871f90 .part L_0x18712b0, 0, 2; +L_0x1872820 .concat8 [ 1 1 0 0], L_0x1871cd0, L_0x18726c0; +L_0x1872a20 .part v0x17dbc90_0, 1, 1; +L_0x1872ac0 .part L_0x18712b0, 2, 2; +L_0x1873300 .part v0x17dbc90_0, 2, 1; +S_0x17ba780 .scope module, "mux_0" "bitMultiplexer" 4 29, 4 8 0, S_0x17ba510; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "addr" + .port_info 2 /INPUT 2 "in" +L_0x186ec00/d .functor NOT 1, L_0x186f4e0, C4<0>, C4<0>, C4<0>; +L_0x186ec00 .delay 1 (10000,10000,10000) L_0x186ec00/d; +L_0x186ed60/d .functor AND 1, L_0x186ef60, L_0x186ec00, C4<1>, C4<1>; +L_0x186ed60 .delay 1 (20000,20000,20000) L_0x186ed60/d; +L_0x186f0c0/d .functor AND 1, L_0x186f1d0, L_0x186f4e0, C4<1>, C4<1>; +L_0x186f0c0 .delay 1 (20000,20000,20000) L_0x186f0c0/d; +L_0x186f380/d .functor OR 1, L_0x186ed60, L_0x186f0c0, C4<0>, C4<0>; +L_0x186f380 .delay 1 (20000,20000,20000) L_0x186f380/d; +v0x17ba9f0_0 .net *"_s1", 0 0, L_0x186ef60; 1 drivers +v0x17baaf0_0 .net *"_s3", 0 0, L_0x186f1d0; 1 drivers +v0x17babd0_0 .net "addr", 0 0, L_0x186f4e0; 1 drivers +v0x17baca0_0 .net "in", 1 0, L_0x186f640; 1 drivers +v0x17bad80_0 .net "naddr", 0 0, L_0x186ec00; 1 drivers +v0x17bae90_0 .net "o0", 0 0, L_0x186ed60; 1 drivers +v0x17baf50_0 .net "o1", 0 0, L_0x186f0c0; 1 drivers +v0x17bb010_0 .net "out", 0 0, L_0x186f380; 1 drivers +L_0x186ef60 .part L_0x186f640, 0, 1; +L_0x186f1d0 .part L_0x186f640, 1, 1; +S_0x17bb150 .scope module, "mux_1" "bitMultiplexer" 4 30, 4 8 0, S_0x17ba510; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "addr" + .port_info 2 /INPUT 2 "in" +L_0x186f6e0/d .functor NOT 1, L_0x186fed0, C4<0>, C4<0>, C4<0>; +L_0x186f6e0 .delay 1 (10000,10000,10000) L_0x186f6e0/d; +L_0x186f7a0/d .functor AND 1, L_0x186f950, L_0x186f6e0, C4<1>, C4<1>; +L_0x186f7a0 .delay 1 (20000,20000,20000) L_0x186f7a0/d; +L_0x186fab0/d .functor AND 1, L_0x186fbc0, L_0x186fed0, C4<1>, C4<1>; +L_0x186fab0 .delay 1 (20000,20000,20000) L_0x186fab0/d; +L_0x186fd70/d .functor OR 1, L_0x186f7a0, L_0x186fab0, C4<0>, C4<0>; +L_0x186fd70 .delay 1 (20000,20000,20000) L_0x186fd70/d; +v0x17bb380_0 .net *"_s1", 0 0, L_0x186f950; 1 drivers +v0x17bb480_0 .net *"_s3", 0 0, L_0x186fbc0; 1 drivers +v0x17bb560_0 .net "addr", 0 0, L_0x186fed0; 1 drivers +v0x17bb600_0 .net "in", 1 0, L_0x1870030; 1 drivers +v0x17bb6e0_0 .net "naddr", 0 0, L_0x186f6e0; 1 drivers +v0x17bb7f0_0 .net "o0", 0 0, L_0x186f7a0; 1 drivers +v0x17bb8b0_0 .net "o1", 0 0, L_0x186fab0; 1 drivers +v0x17bb970_0 .net "out", 0 0, L_0x186fd70; 1 drivers +L_0x186f950 .part L_0x1870030, 0, 1; +L_0x186fbc0 .part L_0x1870030, 1, 1; +S_0x17bbab0 .scope module, "mux_2" "bitMultiplexer" 4 31, 4 8 0, S_0x17ba510; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "addr" + .port_info 2 /INPUT 2 "in" +L_0x186ff70/d .functor NOT 1, L_0x18708a0, C4<0>, C4<0>, C4<0>; +L_0x186ff70 .delay 1 (10000,10000,10000) L_0x186ff70/d; +L_0x1870120/d .functor AND 1, L_0x1870320, L_0x186ff70, C4<1>, C4<1>; +L_0x1870120 .delay 1 (20000,20000,20000) L_0x1870120/d; +L_0x1870480/d .functor AND 1, L_0x1870590, L_0x18708a0, C4<1>, C4<1>; +L_0x1870480 .delay 1 (20000,20000,20000) L_0x1870480/d; +L_0x1870740/d .functor OR 1, L_0x1870120, L_0x1870480, C4<0>, C4<0>; +L_0x1870740 .delay 1 (20000,20000,20000) L_0x1870740/d; +v0x17bbce0_0 .net *"_s1", 0 0, L_0x1870320; 1 drivers +v0x17bbdc0_0 .net *"_s3", 0 0, L_0x1870590; 1 drivers +v0x17bbea0_0 .net "addr", 0 0, L_0x18708a0; 1 drivers +v0x17bbf70_0 .net "in", 1 0, L_0x1870a00; 1 drivers +v0x17bc050_0 .net "naddr", 0 0, L_0x186ff70; 1 drivers +v0x17bc160_0 .net "o0", 0 0, L_0x1870120; 1 drivers +v0x17bc220_0 .net "o1", 0 0, L_0x1870480; 1 drivers +v0x17bc2e0_0 .net "out", 0 0, L_0x1870740; 1 drivers +L_0x1870320 .part L_0x1870a00, 0, 1; +L_0x1870590 .part L_0x1870a00, 1, 1; +S_0x17bc420 .scope module, "mux_3" "bitMultiplexer" 4 32, 4 8 0, S_0x17ba510; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "addr" + .port_info 2 /INPUT 2 "in" +L_0x1870940/d .functor NOT 1, L_0x1871500, C4<0>, C4<0>, C4<0>; +L_0x1870940 .delay 1 (10000,10000,10000) L_0x1870940/d; +L_0x1870b30/d .functor AND 1, L_0x1870d30, L_0x1870940, C4<1>, C4<1>; +L_0x1870b30 .delay 1 (20000,20000,20000) L_0x1870b30/d; +L_0x1870e90/d .functor AND 1, L_0x1870fa0, L_0x1871500, C4<1>, C4<1>; +L_0x1870e90 .delay 1 (20000,20000,20000) L_0x1870e90/d; +L_0x1871150/d .functor OR 1, L_0x1870b30, L_0x1870e90, C4<0>, C4<0>; +L_0x1871150 .delay 1 (20000,20000,20000) L_0x1871150/d; +v0x17bc650_0 .net *"_s1", 0 0, L_0x1870d30; 1 drivers +v0x17bc750_0 .net *"_s3", 0 0, L_0x1870fa0; 1 drivers +v0x17bc830_0 .net "addr", 0 0, L_0x1871500; 1 drivers +v0x17bc8d0_0 .net "in", 1 0, L_0x18715f0; 1 drivers +v0x17bc9b0_0 .net "naddr", 0 0, L_0x1870940; 1 drivers +v0x17bcac0_0 .net "o0", 0 0, L_0x1870b30; 1 drivers +v0x17bcb80_0 .net "o1", 0 0, L_0x1870e90; 1 drivers +v0x17bcc40_0 .net "out", 0 0, L_0x1871150; 1 drivers +L_0x1870d30 .part L_0x18715f0, 0, 1; +L_0x1870fa0 .part L_0x18715f0, 1, 1; +S_0x17bcd80 .scope module, "mux_mid_0" "bitMultiplexer" 4 33, 4 8 0, S_0x17ba510; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "addr" + .port_info 2 /INPUT 2 "in" +L_0x1871690/d .functor NOT 1, L_0x1871e30, C4<0>, C4<0>, C4<0>; +L_0x1871690 .delay 1 (10000,10000,10000) L_0x1871690/d; +L_0x1871750/d .functor AND 1, L_0x18718b0, L_0x1871690, C4<1>, C4<1>; +L_0x1871750 .delay 1 (20000,20000,20000) L_0x1871750/d; +L_0x1871a10/d .functor AND 1, L_0x1871b20, L_0x1871e30, C4<1>, C4<1>; +L_0x1871a10 .delay 1 (20000,20000,20000) L_0x1871a10/d; +L_0x1871cd0/d .functor OR 1, L_0x1871750, L_0x1871a10, C4<0>, C4<0>; +L_0x1871cd0 .delay 1 (20000,20000,20000) L_0x1871cd0/d; +v0x17bd000_0 .net *"_s1", 0 0, L_0x18718b0; 1 drivers +v0x17bd100_0 .net *"_s3", 0 0, L_0x1871b20; 1 drivers +v0x17bd1e0_0 .net "addr", 0 0, L_0x1871e30; 1 drivers +v0x17bd280_0 .net "in", 1 0, L_0x1871f90; 1 drivers +v0x17bd360_0 .net "naddr", 0 0, L_0x1871690; 1 drivers +v0x17bd470_0 .net "o0", 0 0, L_0x1871750; 1 drivers +v0x17bd530_0 .net "o1", 0 0, L_0x1871a10; 1 drivers +v0x17bd5f0_0 .net "out", 0 0, L_0x1871cd0; 1 drivers +L_0x18718b0 .part L_0x1871f90, 0, 1; +L_0x1871b20 .part L_0x1871f90, 1, 1; +S_0x17bd730 .scope module, "mux_mid_1" "bitMultiplexer" 4 34, 4 8 0, S_0x17ba510; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "addr" + .port_info 2 /INPUT 2 "in" +L_0x1872030/d .functor NOT 1, L_0x1872a20, C4<0>, C4<0>, C4<0>; +L_0x1872030 .delay 1 (10000,10000,10000) L_0x1872030/d; +L_0x18720f0/d .functor AND 1, L_0x18722a0, L_0x1872030, C4<1>, C4<1>; +L_0x18720f0 .delay 1 (20000,20000,20000) L_0x18720f0/d; +L_0x1872400/d .functor AND 1, L_0x1872510, L_0x1872a20, C4<1>, C4<1>; +L_0x1872400 .delay 1 (20000,20000,20000) L_0x1872400/d; +L_0x18726c0/d .functor OR 1, L_0x18720f0, L_0x1872400, C4<0>, C4<0>; +L_0x18726c0 .delay 1 (20000,20000,20000) L_0x18726c0/d; +v0x17bd960_0 .net *"_s1", 0 0, L_0x18722a0; 1 drivers +v0x17bda60_0 .net *"_s3", 0 0, L_0x1872510; 1 drivers +v0x17bdb40_0 .net "addr", 0 0, L_0x1872a20; 1 drivers +v0x17bdbe0_0 .net "in", 1 0, L_0x1872ac0; 1 drivers +v0x17bdcc0_0 .net "naddr", 0 0, L_0x1872030; 1 drivers +v0x17bddd0_0 .net "o0", 0 0, L_0x18720f0; 1 drivers +v0x17bde90_0 .net "o1", 0 0, L_0x1872400; 1 drivers +v0x17bdf50_0 .net "out", 0 0, L_0x18726c0; 1 drivers +L_0x18722a0 .part L_0x1872ac0, 0, 1; +L_0x1872510 .part L_0x1872ac0, 1, 1; +S_0x17be090 .scope module, "mux_out" "bitMultiplexer" 4 35, 4 8 0, S_0x17ba510; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "addr" + .port_info 2 /INPUT 2 "in" +L_0x1871ed0/d .functor NOT 1, L_0x1873300, C4<0>, C4<0>, C4<0>; +L_0x1871ed0 .delay 1 (10000,10000,10000) L_0x1871ed0/d; +L_0x1872c30/d .functor AND 1, L_0x1872d90, L_0x1871ed0, C4<1>, C4<1>; +L_0x1872c30 .delay 1 (20000,20000,20000) L_0x1872c30/d; +L_0x1872ef0/d .functor AND 1, L_0x1873000, L_0x1873300, C4<1>, C4<1>; +L_0x1872ef0 .delay 1 (20000,20000,20000) L_0x1872ef0/d; +L_0x18731f0/d .functor OR 1, L_0x1872c30, L_0x1872ef0, C4<0>, C4<0>; +L_0x18731f0 .delay 1 (20000,20000,20000) L_0x18731f0/d; +v0x17be2c0_0 .net *"_s1", 0 0, L_0x1872d90; 1 drivers +v0x17be3c0_0 .net *"_s3", 0 0, L_0x1873000; 1 drivers +v0x17be4a0_0 .net "addr", 0 0, L_0x1873300; 1 drivers +v0x17be540_0 .net "in", 1 0, L_0x1872820; alias, 1 drivers +v0x17be620_0 .net "naddr", 0 0, L_0x1871ed0; 1 drivers +v0x17be730_0 .net "o0", 0 0, L_0x1872c30; 1 drivers +v0x17be7f0_0 .net "o1", 0 0, L_0x1872ef0; 1 drivers +v0x17be8b0_0 .net "out", 0 0, L_0x18731f0; alias, 1 drivers +L_0x1872d90 .part L_0x1872820, 0, 1; +L_0x1873000 .part L_0x1872820, 1, 1; +S_0x17bee40 .scope module, "structadder" "structAddSub" 3 22, 5 8 0, S_0x17ba280; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "sub" + .port_info 5 /INPUT 1 "carryin" +L_0x186da90/d .functor XOR 1, L_0x186dc80, v0x17dbbc0_0, C4<0>, C4<0>; +L_0x186da90 .delay 1 (20000,20000,20000) L_0x186da90/d; +L_0x1869ee0/d .functor XOR 1, L_0x1873590, L_0x186dc80, C4<0>, C4<0>; +L_0x1869ee0 .delay 1 (20000,20000,20000) L_0x1869ee0/d; +L_0x186dfa0/d .functor XOR 1, L_0x1869ee0, L_0x1873460, C4<0>, C4<0>; +L_0x186dfa0 .delay 1 (20000,20000,20000) L_0x186dfa0/d; +L_0x186e150/d .functor AND 1, L_0x1873590, L_0x186dc80, C4<1>, C4<1>; +L_0x186e150 .delay 1 (20000,20000,20000) L_0x186e150/d; +L_0x186e2b0/d .functor AND 1, L_0x1869ee0, L_0x1873460, C4<1>, C4<1>; +L_0x186e2b0 .delay 1 (20000,20000,20000) L_0x186e2b0/d; +L_0x186e410/d .functor OR 1, L_0x186e2b0, L_0x186e150, C4<0>, C4<0>; +L_0x186e410 .delay 1 (20000,20000,20000) L_0x186e410/d; +v0x17bf100_0 .net "AandB", 0 0, L_0x186e150; 1 drivers +v0x17bf1c0_0 .net "AxorB", 0 0, L_0x1869ee0; 1 drivers +v0x17bf280_0 .net "AxorBandCarryIn", 0 0, L_0x186e2b0; 1 drivers +v0x17bf350_0 .net "a", 0 0, L_0x1873590; alias, 1 drivers +v0x17bf410_0 .net "b", 0 0, L_0x186dc80; alias, 1 drivers +v0x17bf520_0 .net "bnew", 0 0, L_0x186da90; 1 drivers +v0x17bf5e0_0 .net "carryin", 0 0, L_0x1873460; alias, 1 drivers +v0x17bf6a0_0 .net "carryout", 0 0, L_0x186e410; alias, 1 drivers +v0x17bf760_0 .net "sub", 0 0, v0x17dbbc0_0; alias, 1 drivers +v0x17bf890_0 .net "sum", 0 0, L_0x186dfa0; 1 drivers +S_0x17c0720 .scope generate, "ripple[28]" "ripple[28]" 3 66, 3 66 0, S_0x16fa6c0; + .timescale -9 -12; +P_0x17c08f0 .param/l "i" 0 3 66, +C4<011100>; +S_0x17c09b0 .scope module, "bit" "BitSliceALU" 3 68, 3 11 0, S_0x17c0720; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "ALUout" + .port_info 1 /OUTPUT 1 "Cout" + .port_info 2 /INPUT 1 "invertB" + .port_info 3 /INPUT 1 "Cin" + .port_info 4 /INPUT 3 "addr" + .port_info 5 /INPUT 1 "bit1" + .port_info 6 /INPUT 1 "bit2" +L_0x1873ee0/d .functor XOR 1, L_0x1873630, L_0x18736d0, C4<0>, C4<0>; +L_0x1873ee0 .delay 1 (20000,20000,20000) L_0x1873ee0/d; +L_0x1874040/d .functor NAND 1, L_0x1873630, L_0x18736d0, C4<1>, C4<1>; +L_0x1874040 .delay 1 (10000,10000,10000) L_0x1874040/d; +L_0x18741a0/d .functor XOR 1, v0x17dbbc0_0, L_0x1874040, C4<0>, C4<0>; +L_0x18741a0 .delay 1 (20000,20000,20000) L_0x18741a0/d; +L_0x18742b0/d .functor NOR 1, L_0x1873630, L_0x18736d0, C4<0>, C4<0>; +L_0x18742b0 .delay 1 (10000,10000,10000) L_0x18742b0/d; +L_0x1874410/d .functor XOR 1, v0x17dbbc0_0, L_0x18742b0, C4<0>, C4<0>; +L_0x1874410 .delay 1 (20000,20000,20000) L_0x1874410/d; +v0x17c6190_0 .net "ALUout", 0 0, L_0x1879a40; 1 drivers +v0x17c6250_0 .net "Cin", 0 0, L_0x1879cb0; 1 drivers +v0x17c6310_0 .net "Cout", 0 0, L_0x1873d30; 1 drivers +v0x17c63e0_0 .net *"_s11", 0 0, L_0x1874410; 1 drivers +o0x7fc2cd930998 .functor BUFZ 1, C4; HiZ drive +; Elide local net with no drivers, v0x17c6480_0 name=_s15 +o0x7fc2cd9309c8 .functor BUFZ 3, C4; HiZ drive +; Elide local net with no drivers, v0x17c6570_0 name=_s17 +v0x17c6650_0 .net *"_s3", 0 0, L_0x1873ee0; 1 drivers +v0x17c6730_0 .net *"_s7", 0 0, L_0x18741a0; 1 drivers +v0x17c6810_0 .net "addr", 2 0, v0x17dbc90_0; alias, 1 drivers +v0x17c6960_0 .net "bit1", 0 0, L_0x1873630; 1 drivers +v0x17c6a00_0 .net "bit2", 0 0, L_0x18736d0; 1 drivers +v0x17c6ad0_0 .net "invertB", 0 0, v0x17dbbc0_0; alias, 1 drivers +v0x17c6b70_0 .net "nanded", 0 0, L_0x1874040; 1 drivers +v0x17c6c10_0 .net "nored", 0 0, L_0x18742b0; 1 drivers +v0x17c6cb0_0 .net "out", 7 0, L_0x1894a50; 1 drivers +LS_0x1894a50_0_0 .concat [ 1 1 1 1], L_0x18738c0, L_0x1873ee0, o0x7fc2cd930998, L_0x18741a0; +LS_0x1894a50_0_4 .concat [ 1 3 0 0], L_0x1874410, o0x7fc2cd9309c8; +L_0x1894a50 .concat [ 4 4 0 0], LS_0x1894a50_0_0, LS_0x1894a50_0_4; +S_0x17c0c40 .scope module, "opmux" "structuralMultiplexer" 3 43, 4 21 0, S_0x17c09b0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 3 "address" + .port_info 2 /INPUT 8 "in" +v0x17c50e0_0 .net "address", 2 0, v0x17dbc90_0; alias, 1 drivers +v0x17c51a0_0 .net "in", 7 0, L_0x1894a50; alias, 1 drivers +v0x17c5280_0 .net "mux", 3 0, L_0x1877b00; 1 drivers +v0x17c5370_0 .net "muxmid", 1 0, L_0x1879070; 1 drivers +v0x17c5460_0 .net "out", 0 0, L_0x1879a40; alias, 1 drivers +L_0x1874d10 .part v0x17dbc90_0, 0, 1; +L_0x180d560 .part L_0x1894a50, 0, 2; +L_0x180de80 .part v0x17dbc90_0, 0, 1; +L_0x180dfe0 .part L_0x1894a50, 2, 2; +L_0x1877190 .part v0x17dbc90_0, 0, 1; +L_0x18772f0 .part L_0x1894a50, 4, 2; +L_0x1877b00 .concat8 [ 1 1 1 1], L_0x1874bb0, L_0x180dd20, L_0x1877030, L_0x18779a0; +L_0x1877d50 .part v0x17dbc90_0, 0, 1; +L_0x1877e40 .part L_0x1894a50, 6, 2; +L_0x1878680 .part v0x17dbc90_0, 1, 1; +L_0x18787e0 .part L_0x1877b00, 0, 2; +L_0x1879070 .concat8 [ 1 1 0 0], L_0x1878520, L_0x1878f10; +L_0x1879270 .part v0x17dbc90_0, 1, 1; +L_0x1879310 .part L_0x1877b00, 2, 2; +L_0x1879b50 .part v0x17dbc90_0, 2, 1; +S_0x17c0eb0 .scope module, "mux_0" "bitMultiplexer" 4 29, 4 8 0, S_0x17c0c40; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "addr" + .port_info 2 /INPUT 2 "in" +L_0x1874520/d .functor NOT 1, L_0x1874d10, C4<0>, C4<0>, C4<0>; +L_0x1874520 .delay 1 (10000,10000,10000) L_0x1874520/d; +L_0x1874680/d .functor AND 1, L_0x1874790, L_0x1874520, C4<1>, C4<1>; +L_0x1874680 .delay 1 (20000,20000,20000) L_0x1874680/d; +L_0x18748f0/d .functor AND 1, L_0x1874a00, L_0x1874d10, C4<1>, C4<1>; +L_0x18748f0 .delay 1 (20000,20000,20000) L_0x18748f0/d; +L_0x1874bb0/d .functor OR 1, L_0x1874680, L_0x18748f0, C4<0>, C4<0>; +L_0x1874bb0 .delay 1 (20000,20000,20000) L_0x1874bb0/d; +v0x17c1120_0 .net *"_s1", 0 0, L_0x1874790; 1 drivers +v0x17c1220_0 .net *"_s3", 0 0, L_0x1874a00; 1 drivers +v0x17c1300_0 .net "addr", 0 0, L_0x1874d10; 1 drivers +v0x17c13d0_0 .net "in", 1 0, L_0x180d560; 1 drivers +v0x17c14b0_0 .net "naddr", 0 0, L_0x1874520; 1 drivers +v0x17c15c0_0 .net "o0", 0 0, L_0x1874680; 1 drivers +v0x17c1680_0 .net "o1", 0 0, L_0x18748f0; 1 drivers +v0x17c1740_0 .net "out", 0 0, L_0x1874bb0; 1 drivers +L_0x1874790 .part L_0x180d560, 0, 1; +L_0x1874a00 .part L_0x180d560, 1, 1; +S_0x17c1880 .scope module, "mux_1" "bitMultiplexer" 4 30, 4 8 0, S_0x17c0c40; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "addr" + .port_info 2 /INPUT 2 "in" +L_0x1874db0/d .functor NOT 1, L_0x180de80, C4<0>, C4<0>, C4<0>; +L_0x1874db0 .delay 1 (10000,10000,10000) L_0x1874db0/d; +L_0x180d6d0/d .functor AND 1, L_0x180d8d0, L_0x1874db0, C4<1>, C4<1>; +L_0x180d6d0 .delay 1 (20000,20000,20000) L_0x180d6d0/d; +L_0x180da30/d .functor AND 1, L_0x180db70, L_0x180de80, C4<1>, C4<1>; +L_0x180da30 .delay 1 (20000,20000,20000) L_0x180da30/d; +L_0x180dd20/d .functor OR 1, L_0x180d6d0, L_0x180da30, C4<0>, C4<0>; +L_0x180dd20 .delay 1 (20000,20000,20000) L_0x180dd20/d; +v0x17c1ab0_0 .net *"_s1", 0 0, L_0x180d8d0; 1 drivers +v0x17c1bb0_0 .net *"_s3", 0 0, L_0x180db70; 1 drivers +v0x17c1c90_0 .net "addr", 0 0, L_0x180de80; 1 drivers +v0x17c1d30_0 .net "in", 1 0, L_0x180dfe0; 1 drivers +v0x17c1e10_0 .net "naddr", 0 0, L_0x1874db0; 1 drivers +v0x17c1f20_0 .net "o0", 0 0, L_0x180d6d0; 1 drivers +v0x17c1fe0_0 .net "o1", 0 0, L_0x180da30; 1 drivers +v0x17c20a0_0 .net "out", 0 0, L_0x180dd20; 1 drivers +L_0x180d8d0 .part L_0x180dfe0, 0, 1; +L_0x180db70 .part L_0x180dfe0, 1, 1; +S_0x17c21e0 .scope module, "mux_2" "bitMultiplexer" 4 31, 4 8 0, S_0x17c0c40; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "addr" + .port_info 2 /INPUT 2 "in" +L_0x180df20/d .functor NOT 1, L_0x1877190, C4<0>, C4<0>, C4<0>; +L_0x180df20 .delay 1 (10000,10000,10000) L_0x180df20/d; +L_0x180e0d0/d .functor AND 1, L_0x180e2d0, L_0x180df20, C4<1>, C4<1>; +L_0x180e0d0 .delay 1 (20000,20000,20000) L_0x180e0d0/d; +L_0x180e430/d .functor AND 1, L_0x1876e80, L_0x1877190, C4<1>, C4<1>; +L_0x180e430 .delay 1 (20000,20000,20000) L_0x180e430/d; +L_0x1877030/d .functor OR 1, L_0x180e0d0, L_0x180e430, C4<0>, C4<0>; +L_0x1877030 .delay 1 (20000,20000,20000) L_0x1877030/d; +v0x17c2410_0 .net *"_s1", 0 0, L_0x180e2d0; 1 drivers +v0x17c24f0_0 .net *"_s3", 0 0, L_0x1876e80; 1 drivers +v0x17c25d0_0 .net "addr", 0 0, L_0x1877190; 1 drivers +v0x17c26a0_0 .net "in", 1 0, L_0x18772f0; 1 drivers +v0x17c2780_0 .net "naddr", 0 0, L_0x180df20; 1 drivers +v0x17c2890_0 .net "o0", 0 0, L_0x180e0d0; 1 drivers +v0x17c2950_0 .net "o1", 0 0, L_0x180e430; 1 drivers +v0x17c2a10_0 .net "out", 0 0, L_0x1877030; 1 drivers +L_0x180e2d0 .part L_0x18772f0, 0, 1; +L_0x1876e80 .part L_0x18772f0, 1, 1; +S_0x17c2b50 .scope module, "mux_3" "bitMultiplexer" 4 32, 4 8 0, S_0x17c0c40; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "addr" + .port_info 2 /INPUT 2 "in" +L_0x1877230/d .functor NOT 1, L_0x1877d50, C4<0>, C4<0>, C4<0>; +L_0x1877230 .delay 1 (10000,10000,10000) L_0x1877230/d; +L_0x1877420/d .functor AND 1, L_0x1877580, L_0x1877230, C4<1>, C4<1>; +L_0x1877420 .delay 1 (20000,20000,20000) L_0x1877420/d; +L_0x18776e0/d .functor AND 1, L_0x18777f0, L_0x1877d50, C4<1>, C4<1>; +L_0x18776e0 .delay 1 (20000,20000,20000) L_0x18776e0/d; +L_0x18779a0/d .functor OR 1, L_0x1877420, L_0x18776e0, C4<0>, C4<0>; +L_0x18779a0 .delay 1 (20000,20000,20000) L_0x18779a0/d; +v0x17c2d80_0 .net *"_s1", 0 0, L_0x1877580; 1 drivers +v0x17c2e80_0 .net *"_s3", 0 0, L_0x18777f0; 1 drivers +v0x17c2f60_0 .net "addr", 0 0, L_0x1877d50; 1 drivers +v0x17c3000_0 .net "in", 1 0, L_0x1877e40; 1 drivers +v0x17c30e0_0 .net "naddr", 0 0, L_0x1877230; 1 drivers +v0x17c31f0_0 .net "o0", 0 0, L_0x1877420; 1 drivers +v0x17c32b0_0 .net "o1", 0 0, L_0x18776e0; 1 drivers +v0x17c3370_0 .net "out", 0 0, L_0x18779a0; 1 drivers +L_0x1877580 .part L_0x1877e40, 0, 1; +L_0x18777f0 .part L_0x1877e40, 1, 1; +S_0x17c34b0 .scope module, "mux_mid_0" "bitMultiplexer" 4 33, 4 8 0, S_0x17c0c40; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "addr" + .port_info 2 /INPUT 2 "in" +L_0x1877ee0/d .functor NOT 1, L_0x1878680, C4<0>, C4<0>, C4<0>; +L_0x1877ee0 .delay 1 (10000,10000,10000) L_0x1877ee0/d; +L_0x1877fa0/d .functor AND 1, L_0x1878100, L_0x1877ee0, C4<1>, C4<1>; +L_0x1877fa0 .delay 1 (20000,20000,20000) L_0x1877fa0/d; +L_0x1878260/d .functor AND 1, L_0x1878370, L_0x1878680, C4<1>, C4<1>; +L_0x1878260 .delay 1 (20000,20000,20000) L_0x1878260/d; +L_0x1878520/d .functor OR 1, L_0x1877fa0, L_0x1878260, C4<0>, C4<0>; +L_0x1878520 .delay 1 (20000,20000,20000) L_0x1878520/d; +v0x17c3730_0 .net *"_s1", 0 0, L_0x1878100; 1 drivers +v0x17c3830_0 .net *"_s3", 0 0, L_0x1878370; 1 drivers +v0x17c3910_0 .net "addr", 0 0, L_0x1878680; 1 drivers +v0x17c39b0_0 .net "in", 1 0, L_0x18787e0; 1 drivers +v0x17c3a90_0 .net "naddr", 0 0, L_0x1877ee0; 1 drivers +v0x17c3ba0_0 .net "o0", 0 0, L_0x1877fa0; 1 drivers +v0x17c3c60_0 .net "o1", 0 0, L_0x1878260; 1 drivers +v0x17c3d20_0 .net "out", 0 0, L_0x1878520; 1 drivers +L_0x1878100 .part L_0x18787e0, 0, 1; +L_0x1878370 .part L_0x18787e0, 1, 1; +S_0x17c3e60 .scope module, "mux_mid_1" "bitMultiplexer" 4 34, 4 8 0, S_0x17c0c40; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "addr" + .port_info 2 /INPUT 2 "in" +L_0x1878880/d .functor NOT 1, L_0x1879270, C4<0>, C4<0>, C4<0>; +L_0x1878880 .delay 1 (10000,10000,10000) L_0x1878880/d; +L_0x1878940/d .functor AND 1, L_0x1878af0, L_0x1878880, C4<1>, C4<1>; +L_0x1878940 .delay 1 (20000,20000,20000) L_0x1878940/d; +L_0x1878c50/d .functor AND 1, L_0x1878d60, L_0x1879270, C4<1>, C4<1>; +L_0x1878c50 .delay 1 (20000,20000,20000) L_0x1878c50/d; +L_0x1878f10/d .functor OR 1, L_0x1878940, L_0x1878c50, C4<0>, C4<0>; +L_0x1878f10 .delay 1 (20000,20000,20000) L_0x1878f10/d; +v0x17c4090_0 .net *"_s1", 0 0, L_0x1878af0; 1 drivers +v0x17c4190_0 .net *"_s3", 0 0, L_0x1878d60; 1 drivers +v0x17c4270_0 .net "addr", 0 0, L_0x1879270; 1 drivers +v0x17c4310_0 .net "in", 1 0, L_0x1879310; 1 drivers +v0x17c43f0_0 .net "naddr", 0 0, L_0x1878880; 1 drivers +v0x17c4500_0 .net "o0", 0 0, L_0x1878940; 1 drivers +v0x17c45c0_0 .net "o1", 0 0, L_0x1878c50; 1 drivers +v0x17c4680_0 .net "out", 0 0, L_0x1878f10; 1 drivers +L_0x1878af0 .part L_0x1879310, 0, 1; +L_0x1878d60 .part L_0x1879310, 1, 1; +S_0x17c47c0 .scope module, "mux_out" "bitMultiplexer" 4 35, 4 8 0, S_0x17c0c40; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "addr" + .port_info 2 /INPUT 2 "in" +L_0x1878720/d .functor NOT 1, L_0x1879b50, C4<0>, C4<0>, C4<0>; +L_0x1878720 .delay 1 (10000,10000,10000) L_0x1878720/d; +L_0x1879480/d .functor AND 1, L_0x18795e0, L_0x1878720, C4<1>, C4<1>; +L_0x1879480 .delay 1 (20000,20000,20000) L_0x1879480/d; +L_0x1879740/d .functor AND 1, L_0x1879850, L_0x1879b50, C4<1>, C4<1>; +L_0x1879740 .delay 1 (20000,20000,20000) L_0x1879740/d; +L_0x1879a40/d .functor OR 1, L_0x1879480, L_0x1879740, C4<0>, C4<0>; +L_0x1879a40 .delay 1 (20000,20000,20000) L_0x1879a40/d; +v0x17c49f0_0 .net *"_s1", 0 0, L_0x18795e0; 1 drivers +v0x17c4af0_0 .net *"_s3", 0 0, L_0x1879850; 1 drivers +v0x17c4bd0_0 .net "addr", 0 0, L_0x1879b50; 1 drivers +v0x17c4c70_0 .net "in", 1 0, L_0x1879070; alias, 1 drivers +v0x17c4d50_0 .net "naddr", 0 0, L_0x1878720; 1 drivers +v0x17c4e60_0 .net "o0", 0 0, L_0x1879480; 1 drivers +v0x17c4f20_0 .net "o1", 0 0, L_0x1879740; 1 drivers +v0x17c4fe0_0 .net "out", 0 0, L_0x1879a40; alias, 1 drivers +L_0x18795e0 .part L_0x1879070, 0, 1; +L_0x1879850 .part L_0x1879070, 1, 1; +S_0x17c55b0 .scope module, "structadder" "structAddSub" 3 22, 5 8 0, S_0x17c09b0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "sub" + .port_info 5 /INPUT 1 "carryin" +L_0x18733a0/d .functor XOR 1, L_0x18736d0, v0x17dbbc0_0, C4<0>, C4<0>; +L_0x18733a0 .delay 1 (20000,20000,20000) L_0x18733a0/d; +L_0x186ee00/d .functor XOR 1, L_0x1873630, L_0x18736d0, C4<0>, C4<0>; +L_0x186ee00 .delay 1 (20000,20000,20000) L_0x186ee00/d; +L_0x18738c0/d .functor XOR 1, L_0x186ee00, L_0x1879cb0, C4<0>, C4<0>; +L_0x18738c0 .delay 1 (20000,20000,20000) L_0x18738c0/d; +L_0x1873a70/d .functor AND 1, L_0x1873630, L_0x18736d0, C4<1>, C4<1>; +L_0x1873a70 .delay 1 (20000,20000,20000) L_0x1873a70/d; +L_0x1873bd0/d .functor AND 1, L_0x186ee00, L_0x1879cb0, C4<1>, C4<1>; +L_0x1873bd0 .delay 1 (20000,20000,20000) L_0x1873bd0/d; +L_0x1873d30/d .functor OR 1, L_0x1873bd0, L_0x1873a70, C4<0>, C4<0>; +L_0x1873d30 .delay 1 (20000,20000,20000) L_0x1873d30/d; +v0x17c5870_0 .net "AandB", 0 0, L_0x1873a70; 1 drivers +v0x17c5930_0 .net "AxorB", 0 0, L_0x186ee00; 1 drivers +v0x17c59f0_0 .net "AxorBandCarryIn", 0 0, L_0x1873bd0; 1 drivers +v0x17c5a90_0 .net "a", 0 0, L_0x1873630; alias, 1 drivers +v0x17c5b50_0 .net "b", 0 0, L_0x18736d0; alias, 1 drivers +v0x17c5c60_0 .net "bnew", 0 0, L_0x18733a0; 1 drivers +v0x17c5d20_0 .net "carryin", 0 0, L_0x1879cb0; alias, 1 drivers +v0x17c5de0_0 .net "carryout", 0 0, L_0x1873d30; alias, 1 drivers +v0x17c5ea0_0 .net "sub", 0 0, v0x17dbbc0_0; alias, 1 drivers +v0x17c5fd0_0 .net "sum", 0 0, L_0x18738c0; 1 drivers +S_0x17c6e60 .scope generate, "ripple[29]" "ripple[29]" 3 66, 3 66 0, S_0x16fa6c0; + .timescale -9 -12; +P_0x17c7030 .param/l "i" 0 3 66, +C4<011101>; +S_0x17c70f0 .scope module, "bit" "BitSliceALU" 3 68, 3 11 0, S_0x17c6e60; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "ALUout" + .port_info 1 /OUTPUT 1 "Cout" + .port_info 2 /INPUT 1 "invertB" + .port_info 3 /INPUT 1 "Cin" + .port_info 4 /INPUT 3 "addr" + .port_info 5 /INPUT 1 "bit1" + .port_info 6 /INPUT 1 "bit2" +L_0x187a750/d .functor XOR 1, L_0x187f720, L_0x1879de0, C4<0>, C4<0>; +L_0x187a750 .delay 1 (20000,20000,20000) L_0x187a750/d; +L_0x187a8b0/d .functor NAND 1, L_0x187f720, L_0x1879de0, C4<1>, C4<1>; +L_0x187a8b0 .delay 1 (10000,10000,10000) L_0x187a8b0/d; +L_0x187aa10/d .functor XOR 1, v0x17dbbc0_0, L_0x187a8b0, C4<0>, C4<0>; +L_0x187aa10 .delay 1 (20000,20000,20000) L_0x187aa10/d; +L_0x187ab20/d .functor NOR 1, L_0x187f720, L_0x1879de0, C4<0>, C4<0>; +L_0x187ab20 .delay 1 (10000,10000,10000) L_0x187ab20/d; +L_0x187ac80/d .functor XOR 1, v0x17dbbc0_0, L_0x187ab20, C4<0>, C4<0>; +L_0x187ac80 .delay 1 (20000,20000,20000) L_0x187ac80/d; +v0x17cc8c0_0 .net "ALUout", 0 0, L_0x187f380; 1 drivers +v0x17cc980_0 .net "Cin", 0 0, L_0x187f5f0; 1 drivers +v0x17cca40_0 .net "Cout", 0 0, L_0x187a5a0; 1 drivers +v0x17ccb10_0 .net *"_s11", 0 0, L_0x187ac80; 1 drivers +o0x7fc2cd931e68 .functor BUFZ 1, C4; HiZ drive +; Elide local net with no drivers, v0x17ccbb0_0 name=_s15 +o0x7fc2cd931e98 .functor BUFZ 3, C4; HiZ drive +; Elide local net with no drivers, v0x17ccca0_0 name=_s17 +v0x17ccd80_0 .net *"_s3", 0 0, L_0x187a750; 1 drivers +v0x17cce60_0 .net *"_s7", 0 0, L_0x187aa10; 1 drivers +v0x17ccf40_0 .net "addr", 2 0, v0x17dbc90_0; alias, 1 drivers +v0x17cd090_0 .net "bit1", 0 0, L_0x187f720; 1 drivers +v0x17cd130_0 .net "bit2", 0 0, L_0x1879de0; 1 drivers +v0x17cd200_0 .net "invertB", 0 0, v0x17dbbc0_0; alias, 1 drivers +v0x17cd2a0_0 .net "nanded", 0 0, L_0x187a8b0; 1 drivers +v0x17cd340_0 .net "nored", 0 0, L_0x187ab20; 1 drivers +v0x17cd3e0_0 .net "out", 7 0, L_0x1894c30; 1 drivers +LS_0x1894c30_0_0 .concat [ 1 1 1 1], L_0x187a130, L_0x187a750, o0x7fc2cd931e68, L_0x187aa10; +LS_0x1894c30_0_4 .concat [ 1 3 0 0], L_0x187ac80, o0x7fc2cd931e98; +L_0x1894c30 .concat [ 4 4 0 0], LS_0x1894c30_0_0, LS_0x1894c30_0_4; +S_0x17c7380 .scope module, "opmux" "structuralMultiplexer" 3 43, 4 21 0, S_0x17c70f0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 3 "address" + .port_info 2 /INPUT 8 "in" +v0x17cb860_0 .net "address", 2 0, v0x17dbc90_0; alias, 1 drivers +v0x17cb920_0 .net "in", 7 0, L_0x1894c30; alias, 1 drivers +v0x17cba00_0 .net "mux", 3 0, L_0x187d440; 1 drivers +v0x17cbac0_0 .net "muxmid", 1 0, L_0x187e9b0; 1 drivers +v0x17cbb80_0 .net "out", 0 0, L_0x187f380; alias, 1 drivers +L_0x187b670 .part v0x17dbc90_0, 0, 1; +L_0x187b7d0 .part L_0x1894c30, 0, 2; +L_0x187c060 .part v0x17dbc90_0, 0, 1; +L_0x187c1c0 .part L_0x1894c30, 2, 2; +L_0x187ca30 .part v0x17dbc90_0, 0, 1; +L_0x187cb90 .part L_0x1894c30, 4, 2; +L_0x187d440 .concat8 [ 1 1 1 1], L_0x187b510, L_0x187bf00, L_0x187c8d0, L_0x187d2e0; +L_0x187d690 .part v0x17dbc90_0, 0, 1; +L_0x187d780 .part L_0x1894c30, 6, 2; +L_0x187dfc0 .part v0x17dbc90_0, 1, 1; +L_0x187e120 .part L_0x187d440, 0, 2; +L_0x187e9b0 .concat8 [ 1 1 0 0], L_0x187de60, L_0x187e850; +L_0x187ebb0 .part v0x17dbc90_0, 1, 1; +L_0x187ec50 .part L_0x187d440, 2, 2; +L_0x187f490 .part v0x17dbc90_0, 2, 1; +S_0x17c75f0 .scope module, "mux_0" "bitMultiplexer" 4 29, 4 8 0, S_0x17c7380; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "addr" + .port_info 2 /INPUT 2 "in" +L_0x187ad90/d .functor NOT 1, L_0x187b670, C4<0>, C4<0>, C4<0>; +L_0x187ad90 .delay 1 (10000,10000,10000) L_0x187ad90/d; +L_0x187aef0/d .functor AND 1, L_0x187b0f0, L_0x187ad90, C4<1>, C4<1>; +L_0x187aef0 .delay 1 (20000,20000,20000) L_0x187aef0/d; +L_0x187b250/d .functor AND 1, L_0x187b360, L_0x187b670, C4<1>, C4<1>; +L_0x187b250 .delay 1 (20000,20000,20000) L_0x187b250/d; +L_0x187b510/d .functor OR 1, L_0x187aef0, L_0x187b250, C4<0>, C4<0>; +L_0x187b510 .delay 1 (20000,20000,20000) L_0x187b510/d; +v0x17c7860_0 .net *"_s1", 0 0, L_0x187b0f0; 1 drivers +v0x17c7960_0 .net *"_s3", 0 0, L_0x187b360; 1 drivers +v0x17c7a40_0 .net "addr", 0 0, L_0x187b670; 1 drivers +v0x17c7b10_0 .net "in", 1 0, L_0x187b7d0; 1 drivers +v0x17c7bf0_0 .net "naddr", 0 0, L_0x187ad90; 1 drivers +v0x17c7d00_0 .net "o0", 0 0, L_0x187aef0; 1 drivers +v0x17c7dc0_0 .net "o1", 0 0, L_0x187b250; 1 drivers +v0x17c7e80_0 .net "out", 0 0, L_0x187b510; 1 drivers +L_0x187b0f0 .part L_0x187b7d0, 0, 1; +L_0x187b360 .part L_0x187b7d0, 1, 1; +S_0x17c7fc0 .scope module, "mux_1" "bitMultiplexer" 4 30, 4 8 0, S_0x17c7380; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "addr" + .port_info 2 /INPUT 2 "in" +L_0x187b870/d .functor NOT 1, L_0x187c060, C4<0>, C4<0>, C4<0>; +L_0x187b870 .delay 1 (10000,10000,10000) L_0x187b870/d; +L_0x187b930/d .functor AND 1, L_0x187bae0, L_0x187b870, C4<1>, C4<1>; +L_0x187b930 .delay 1 (20000,20000,20000) L_0x187b930/d; +L_0x187bc40/d .functor AND 1, L_0x187bd50, L_0x187c060, C4<1>, C4<1>; +L_0x187bc40 .delay 1 (20000,20000,20000) L_0x187bc40/d; +L_0x187bf00/d .functor OR 1, L_0x187b930, L_0x187bc40, C4<0>, C4<0>; +L_0x187bf00 .delay 1 (20000,20000,20000) L_0x187bf00/d; +v0x17c81f0_0 .net *"_s1", 0 0, L_0x187bae0; 1 drivers +v0x17c82f0_0 .net *"_s3", 0 0, L_0x187bd50; 1 drivers +v0x17c83d0_0 .net "addr", 0 0, L_0x187c060; 1 drivers +v0x17c8470_0 .net "in", 1 0, L_0x187c1c0; 1 drivers +v0x17c8550_0 .net "naddr", 0 0, L_0x187b870; 1 drivers +v0x17c8660_0 .net "o0", 0 0, L_0x187b930; 1 drivers +v0x17c8720_0 .net "o1", 0 0, L_0x187bc40; 1 drivers +v0x17c87e0_0 .net "out", 0 0, L_0x187bf00; 1 drivers +L_0x187bae0 .part L_0x187c1c0, 0, 1; +L_0x187bd50 .part L_0x187c1c0, 1, 1; +S_0x17c8920 .scope module, "mux_2" "bitMultiplexer" 4 31, 4 8 0, S_0x17c7380; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "addr" + .port_info 2 /INPUT 2 "in" +L_0x187c100/d .functor NOT 1, L_0x187ca30, C4<0>, C4<0>, C4<0>; +L_0x187c100 .delay 1 (10000,10000,10000) L_0x187c100/d; +L_0x187c2b0/d .functor AND 1, L_0x187c4b0, L_0x187c100, C4<1>, C4<1>; +L_0x187c2b0 .delay 1 (20000,20000,20000) L_0x187c2b0/d; +L_0x187c610/d .functor AND 1, L_0x187c720, L_0x187ca30, C4<1>, C4<1>; +L_0x187c610 .delay 1 (20000,20000,20000) L_0x187c610/d; +L_0x187c8d0/d .functor OR 1, L_0x187c2b0, L_0x187c610, C4<0>, C4<0>; +L_0x187c8d0 .delay 1 (20000,20000,20000) L_0x187c8d0/d; +v0x17c8b50_0 .net *"_s1", 0 0, L_0x187c4b0; 1 drivers +v0x17c8c30_0 .net *"_s3", 0 0, L_0x187c720; 1 drivers +v0x17c8d10_0 .net "addr", 0 0, L_0x187ca30; 1 drivers +v0x17c8de0_0 .net "in", 1 0, L_0x187cb90; 1 drivers +v0x17c8ec0_0 .net "naddr", 0 0, L_0x187c100; 1 drivers +v0x17c8fd0_0 .net "o0", 0 0, L_0x187c2b0; 1 drivers +v0x17c9090_0 .net "o1", 0 0, L_0x187c610; 1 drivers +v0x17c9150_0 .net "out", 0 0, L_0x187c8d0; 1 drivers +L_0x187c4b0 .part L_0x187cb90, 0, 1; +L_0x187c720 .part L_0x187cb90, 1, 1; +S_0x17c9290 .scope module, "mux_3" "bitMultiplexer" 4 32, 4 8 0, S_0x17c7380; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "addr" + .port_info 2 /INPUT 2 "in" +L_0x187cad0/d .functor NOT 1, L_0x187d690, C4<0>, C4<0>, C4<0>; +L_0x187cad0 .delay 1 (10000,10000,10000) L_0x187cad0/d; +L_0x187ccc0/d .functor AND 1, L_0x187cec0, L_0x187cad0, C4<1>, C4<1>; +L_0x187ccc0 .delay 1 (20000,20000,20000) L_0x187ccc0/d; +L_0x187d020/d .functor AND 1, L_0x187d130, L_0x187d690, C4<1>, C4<1>; +L_0x187d020 .delay 1 (20000,20000,20000) L_0x187d020/d; +L_0x187d2e0/d .functor OR 1, L_0x187ccc0, L_0x187d020, C4<0>, C4<0>; +L_0x187d2e0 .delay 1 (20000,20000,20000) L_0x187d2e0/d; +v0x17c94c0_0 .net *"_s1", 0 0, L_0x187cec0; 1 drivers +v0x17c95c0_0 .net *"_s3", 0 0, L_0x187d130; 1 drivers +v0x17c96a0_0 .net "addr", 0 0, L_0x187d690; 1 drivers +v0x17c9740_0 .net "in", 1 0, L_0x187d780; 1 drivers +v0x17c9820_0 .net "naddr", 0 0, L_0x187cad0; 1 drivers +v0x17c9930_0 .net "o0", 0 0, L_0x187ccc0; 1 drivers +v0x17c99f0_0 .net "o1", 0 0, L_0x187d020; 1 drivers +v0x17c9ab0_0 .net "out", 0 0, L_0x187d2e0; 1 drivers +L_0x187cec0 .part L_0x187d780, 0, 1; +L_0x187d130 .part L_0x187d780, 1, 1; +S_0x17c9bf0 .scope module, "mux_mid_0" "bitMultiplexer" 4 33, 4 8 0, S_0x17c7380; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "addr" + .port_info 2 /INPUT 2 "in" +L_0x187d820/d .functor NOT 1, L_0x187dfc0, C4<0>, C4<0>, C4<0>; +L_0x187d820 .delay 1 (10000,10000,10000) L_0x187d820/d; +L_0x187d8e0/d .functor AND 1, L_0x187da40, L_0x187d820, C4<1>, C4<1>; +L_0x187d8e0 .delay 1 (20000,20000,20000) L_0x187d8e0/d; +L_0x187dba0/d .functor AND 1, L_0x187dcb0, L_0x187dfc0, C4<1>, C4<1>; +L_0x187dba0 .delay 1 (20000,20000,20000) L_0x187dba0/d; +L_0x187de60/d .functor OR 1, L_0x187d8e0, L_0x187dba0, C4<0>, C4<0>; +L_0x187de60 .delay 1 (20000,20000,20000) L_0x187de60/d; +v0x17c9e70_0 .net *"_s1", 0 0, L_0x187da40; 1 drivers +v0x17c9f70_0 .net *"_s3", 0 0, L_0x187dcb0; 1 drivers +v0x17ca050_0 .net "addr", 0 0, L_0x187dfc0; 1 drivers +v0x17ca0f0_0 .net "in", 1 0, L_0x187e120; 1 drivers +v0x17ca1d0_0 .net "naddr", 0 0, L_0x187d820; 1 drivers +v0x17ca2e0_0 .net "o0", 0 0, L_0x187d8e0; 1 drivers +v0x17ca3a0_0 .net "o1", 0 0, L_0x187dba0; 1 drivers +v0x17ca460_0 .net "out", 0 0, L_0x187de60; 1 drivers +L_0x187da40 .part L_0x187e120, 0, 1; +L_0x187dcb0 .part L_0x187e120, 1, 1; +S_0x17ca5a0 .scope module, "mux_mid_1" "bitMultiplexer" 4 34, 4 8 0, S_0x17c7380; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "addr" + .port_info 2 /INPUT 2 "in" +L_0x187e1c0/d .functor NOT 1, L_0x187ebb0, C4<0>, C4<0>, C4<0>; +L_0x187e1c0 .delay 1 (10000,10000,10000) L_0x187e1c0/d; +L_0x187e280/d .functor AND 1, L_0x187e430, L_0x187e1c0, C4<1>, C4<1>; +L_0x187e280 .delay 1 (20000,20000,20000) L_0x187e280/d; +L_0x187e590/d .functor AND 1, L_0x187e6a0, L_0x187ebb0, C4<1>, C4<1>; +L_0x187e590 .delay 1 (20000,20000,20000) L_0x187e590/d; +L_0x187e850/d .functor OR 1, L_0x187e280, L_0x187e590, C4<0>, C4<0>; +L_0x187e850 .delay 1 (20000,20000,20000) L_0x187e850/d; +v0x17ca7d0_0 .net *"_s1", 0 0, L_0x187e430; 1 drivers +v0x17ca8d0_0 .net *"_s3", 0 0, L_0x187e6a0; 1 drivers +v0x17ca9b0_0 .net "addr", 0 0, L_0x187ebb0; 1 drivers +v0x17caa50_0 .net "in", 1 0, L_0x187ec50; 1 drivers +v0x17cab30_0 .net "naddr", 0 0, L_0x187e1c0; 1 drivers +v0x17cac40_0 .net "o0", 0 0, L_0x187e280; 1 drivers +v0x17cad00_0 .net "o1", 0 0, L_0x187e590; 1 drivers +v0x17cadc0_0 .net "out", 0 0, L_0x187e850; 1 drivers +L_0x187e430 .part L_0x187ec50, 0, 1; +L_0x187e6a0 .part L_0x187ec50, 1, 1; +S_0x17caf00 .scope module, "mux_out" "bitMultiplexer" 4 35, 4 8 0, S_0x17c7380; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "addr" + .port_info 2 /INPUT 2 "in" +L_0x187e060/d .functor NOT 1, L_0x187f490, C4<0>, C4<0>, C4<0>; +L_0x187e060 .delay 1 (10000,10000,10000) L_0x187e060/d; +L_0x187edc0/d .functor AND 1, L_0x187ef20, L_0x187e060, C4<1>, C4<1>; +L_0x187edc0 .delay 1 (20000,20000,20000) L_0x187edc0/d; +L_0x187f080/d .functor AND 1, L_0x187f190, L_0x187f490, C4<1>, C4<1>; +L_0x187f080 .delay 1 (20000,20000,20000) L_0x187f080/d; +L_0x187f380/d .functor OR 1, L_0x187edc0, L_0x187f080, C4<0>, C4<0>; +L_0x187f380 .delay 1 (20000,20000,20000) L_0x187f380/d; +v0x17cb130_0 .net *"_s1", 0 0, L_0x187ef20; 1 drivers +v0x17cb230_0 .net *"_s3", 0 0, L_0x187f190; 1 drivers +v0x17cb310_0 .net "addr", 0 0, L_0x187f490; 1 drivers +v0x17cb3b0_0 .net "in", 1 0, L_0x187e9b0; alias, 1 drivers +v0x17cb490_0 .net "naddr", 0 0, L_0x187e060; 1 drivers +v0x17cb5a0_0 .net "o0", 0 0, L_0x187edc0; 1 drivers +v0x17cb660_0 .net "o1", 0 0, L_0x187f080; 1 drivers +v0x17cb720_0 .net "out", 0 0, L_0x187f380; alias, 1 drivers +L_0x187ef20 .part L_0x187e9b0, 0, 1; +L_0x187f190 .part L_0x187e9b0, 1, 1; +S_0x17cbcb0 .scope module, "structadder" "structAddSub" 3 22, 5 8 0, S_0x17c70f0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "sub" + .port_info 5 /INPUT 1 "carryin" +L_0x1879bf0/d .functor XOR 1, L_0x1879de0, v0x17dbbc0_0, C4<0>, C4<0>; +L_0x1879bf0 .delay 1 (20000,20000,20000) L_0x1879bf0/d; +L_0x180d770/d .functor XOR 1, L_0x187f720, L_0x1879de0, C4<0>, C4<0>; +L_0x180d770 .delay 1 (20000,20000,20000) L_0x180d770/d; +L_0x187a130/d .functor XOR 1, L_0x180d770, L_0x187f5f0, C4<0>, C4<0>; +L_0x187a130 .delay 1 (20000,20000,20000) L_0x187a130/d; +L_0x187a2e0/d .functor AND 1, L_0x187f720, L_0x1879de0, C4<1>, C4<1>; +L_0x187a2e0 .delay 1 (20000,20000,20000) L_0x187a2e0/d; +L_0x187a440/d .functor AND 1, L_0x180d770, L_0x187f5f0, C4<1>, C4<1>; +L_0x187a440 .delay 1 (20000,20000,20000) L_0x187a440/d; +L_0x187a5a0/d .functor OR 1, L_0x187a440, L_0x187a2e0, C4<0>, C4<0>; +L_0x187a5a0 .delay 1 (20000,20000,20000) L_0x187a5a0/d; +v0x17cbf70_0 .net "AandB", 0 0, L_0x187a2e0; 1 drivers +v0x17cc030_0 .net "AxorB", 0 0, L_0x180d770; 1 drivers +v0x17cc0f0_0 .net "AxorBandCarryIn", 0 0, L_0x187a440; 1 drivers +v0x17cc1c0_0 .net "a", 0 0, L_0x187f720; alias, 1 drivers +v0x17cc280_0 .net "b", 0 0, L_0x1879de0; alias, 1 drivers +v0x17cc390_0 .net "bnew", 0 0, L_0x1879bf0; 1 drivers +v0x17cc450_0 .net "carryin", 0 0, L_0x187f5f0; alias, 1 drivers +v0x17cc510_0 .net "carryout", 0 0, L_0x187a5a0; alias, 1 drivers +v0x17cc5d0_0 .net "sub", 0 0, v0x17dbbc0_0; alias, 1 drivers +v0x17cc700_0 .net "sum", 0 0, L_0x187a130; 1 drivers +S_0x17cd590 .scope generate, "ripple[30]" "ripple[30]" 3 66, 3 66 0, S_0x16fa6c0; + .timescale -9 -12; +P_0x17cd760 .param/l "i" 0 3 66, +C4<011110>; +S_0x17cd820 .scope module, "bit" "BitSliceALU" 3 68, 3 11 0, S_0x17cd590; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "ALUout" + .port_info 1 /OUTPUT 1 "Cout" + .port_info 2 /INPUT 1 "invertB" + .port_info 3 /INPUT 1 "Cin" + .port_info 4 /INPUT 3 "addr" + .port_info 5 /INPUT 1 "bit1" + .port_info 6 /INPUT 1 "bit2" +L_0x18800f0/d .functor XOR 1, L_0x187f7c0, L_0x187f860, C4<0>, C4<0>; +L_0x18800f0 .delay 1 (20000,20000,20000) L_0x18800f0/d; +L_0x1880250/d .functor NAND 1, L_0x187f7c0, L_0x187f860, C4<1>, C4<1>; +L_0x1880250 .delay 1 (10000,10000,10000) L_0x1880250/d; +L_0x18803b0/d .functor XOR 1, v0x17dbbc0_0, L_0x1880250, C4<0>, C4<0>; +L_0x18803b0 .delay 1 (20000,20000,20000) L_0x18803b0/d; +L_0x18804c0/d .functor NOR 1, L_0x187f7c0, L_0x187f860, C4<0>, C4<0>; +L_0x18804c0 .delay 1 (10000,10000,10000) L_0x18804c0/d; +L_0x1880620/d .functor XOR 1, v0x17dbbc0_0, L_0x18804c0, C4<0>, C4<0>; +L_0x1880620 .delay 1 (20000,20000,20000) L_0x1880620/d; +v0x17d2ff0_0 .net "ALUout", 0 0, L_0x1884cd0; 1 drivers +v0x17d30b0_0 .net "Cin", 0 0, L_0x1884f40; 1 drivers +v0x17d3170_0 .net "Cout", 0 0, L_0x187ff40; 1 drivers +v0x17d3240_0 .net *"_s11", 0 0, L_0x1880620; 1 drivers +o0x7fc2cd933338 .functor BUFZ 1, C4; HiZ drive +; Elide local net with no drivers, v0x17d32e0_0 name=_s15 +o0x7fc2cd933368 .functor BUFZ 3, C4; HiZ drive +; Elide local net with no drivers, v0x17d33d0_0 name=_s17 +v0x17d34b0_0 .net *"_s3", 0 0, L_0x18800f0; 1 drivers +v0x17d3590_0 .net *"_s7", 0 0, L_0x18803b0; 1 drivers +v0x17d3670_0 .net "addr", 2 0, v0x17dbc90_0; alias, 1 drivers +v0x17d37c0_0 .net "bit1", 0 0, L_0x187f7c0; 1 drivers +v0x17d3860_0 .net "bit2", 0 0, L_0x187f860; 1 drivers +v0x17d3930_0 .net "invertB", 0 0, v0x17dbbc0_0; alias, 1 drivers +v0x17d39d0_0 .net "nanded", 0 0, L_0x1880250; 1 drivers +v0x17d3a70_0 .net "nored", 0 0, L_0x18804c0; 1 drivers +v0x17d3b10_0 .net "out", 7 0, L_0x1894e10; 1 drivers +LS_0x1894e10_0_0 .concat [ 1 1 1 1], L_0x187fad0, L_0x18800f0, o0x7fc2cd933338, L_0x18803b0; +LS_0x1894e10_0_4 .concat [ 1 3 0 0], L_0x1880620, o0x7fc2cd933368; +L_0x1894e10 .concat [ 4 4 0 0], LS_0x1894e10_0_0, LS_0x1894e10_0_4; +S_0x17cdab0 .scope module, "opmux" "structuralMultiplexer" 3 43, 4 21 0, S_0x17cd820; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 3 "address" + .port_info 2 /INPUT 8 "in" +v0x17d1f90_0 .net "address", 2 0, v0x17dbc90_0; alias, 1 drivers +v0x17d2050_0 .net "in", 7 0, L_0x1894e10; alias, 1 drivers +v0x17d2130_0 .net "mux", 3 0, L_0x1882d40; 1 drivers +v0x17d21f0_0 .net "muxmid", 1 0, L_0x1884300; 1 drivers +v0x17d22b0_0 .net "out", 0 0, L_0x1884cd0; alias, 1 drivers +L_0x1880f20 .part v0x17dbc90_0, 0, 1; +L_0x1881080 .part L_0x1894e10, 0, 2; +L_0x1881960 .part v0x17dbc90_0, 0, 1; +L_0x1881ac0 .part L_0x1894e10, 2, 2; +L_0x1882330 .part v0x17dbc90_0, 0, 1; +L_0x1882490 .part L_0x1894e10, 4, 2; +L_0x1882d40 .concat8 [ 1 1 1 1], L_0x1880dc0, L_0x1881800, L_0x18821d0, L_0x1882be0; +L_0x1882fe0 .part v0x17dbc90_0, 0, 1; +L_0x18830d0 .part L_0x1894e10, 6, 2; +L_0x1883910 .part v0x17dbc90_0, 1, 1; +L_0x1883a70 .part L_0x1882d40, 0, 2; +L_0x1884300 .concat8 [ 1 1 0 0], L_0x18837b0, L_0x18841a0; +L_0x1884500 .part v0x17dbc90_0, 1, 1; +L_0x18845a0 .part L_0x1882d40, 2, 2; +L_0x1884de0 .part v0x17dbc90_0, 2, 1; +S_0x17cdd20 .scope module, "mux_0" "bitMultiplexer" 4 29, 4 8 0, S_0x17cdab0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "addr" + .port_info 2 /INPUT 2 "in" +L_0x1880730/d .functor NOT 1, L_0x1880f20, C4<0>, C4<0>, C4<0>; +L_0x1880730 .delay 1 (10000,10000,10000) L_0x1880730/d; +L_0x1880890/d .functor AND 1, L_0x18809a0, L_0x1880730, C4<1>, C4<1>; +L_0x1880890 .delay 1 (20000,20000,20000) L_0x1880890/d; +L_0x1880b00/d .functor AND 1, L_0x1880c10, L_0x1880f20, C4<1>, C4<1>; +L_0x1880b00 .delay 1 (20000,20000,20000) L_0x1880b00/d; +L_0x1880dc0/d .functor OR 1, L_0x1880890, L_0x1880b00, C4<0>, C4<0>; +L_0x1880dc0 .delay 1 (20000,20000,20000) L_0x1880dc0/d; +v0x17cdf90_0 .net *"_s1", 0 0, L_0x18809a0; 1 drivers +v0x17ce090_0 .net *"_s3", 0 0, L_0x1880c10; 1 drivers +v0x17ce170_0 .net "addr", 0 0, L_0x1880f20; 1 drivers +v0x17ce240_0 .net "in", 1 0, L_0x1881080; 1 drivers +v0x17ce320_0 .net "naddr", 0 0, L_0x1880730; 1 drivers +v0x17ce430_0 .net "o0", 0 0, L_0x1880890; 1 drivers +v0x17ce4f0_0 .net "o1", 0 0, L_0x1880b00; 1 drivers +v0x17ce5b0_0 .net "out", 0 0, L_0x1880dc0; 1 drivers +L_0x18809a0 .part L_0x1881080, 0, 1; +L_0x1880c10 .part L_0x1881080, 1, 1; +S_0x17ce6f0 .scope module, "mux_1" "bitMultiplexer" 4 30, 4 8 0, S_0x17cdab0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "addr" + .port_info 2 /INPUT 2 "in" +L_0x1881120/d .functor NOT 1, L_0x1881960, C4<0>, C4<0>, C4<0>; +L_0x1881120 .delay 1 (10000,10000,10000) L_0x1881120/d; +L_0x18811e0/d .functor AND 1, L_0x18813e0, L_0x1881120, C4<1>, C4<1>; +L_0x18811e0 .delay 1 (20000,20000,20000) L_0x18811e0/d; +L_0x1881540/d .functor AND 1, L_0x1881650, L_0x1881960, C4<1>, C4<1>; +L_0x1881540 .delay 1 (20000,20000,20000) L_0x1881540/d; +L_0x1881800/d .functor OR 1, L_0x18811e0, L_0x1881540, C4<0>, C4<0>; +L_0x1881800 .delay 1 (20000,20000,20000) L_0x1881800/d; +v0x17ce920_0 .net *"_s1", 0 0, L_0x18813e0; 1 drivers +v0x17cea20_0 .net *"_s3", 0 0, L_0x1881650; 1 drivers +v0x17ceb00_0 .net "addr", 0 0, L_0x1881960; 1 drivers +v0x17ceba0_0 .net "in", 1 0, L_0x1881ac0; 1 drivers +v0x17cec80_0 .net "naddr", 0 0, L_0x1881120; 1 drivers +v0x17ced90_0 .net "o0", 0 0, L_0x18811e0; 1 drivers +v0x17cee50_0 .net "o1", 0 0, L_0x1881540; 1 drivers +v0x17cef10_0 .net "out", 0 0, L_0x1881800; 1 drivers +L_0x18813e0 .part L_0x1881ac0, 0, 1; +L_0x1881650 .part L_0x1881ac0, 1, 1; +S_0x17cf050 .scope module, "mux_2" "bitMultiplexer" 4 31, 4 8 0, S_0x17cdab0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "addr" + .port_info 2 /INPUT 2 "in" +L_0x1881a00/d .functor NOT 1, L_0x1882330, C4<0>, C4<0>, C4<0>; +L_0x1881a00 .delay 1 (10000,10000,10000) L_0x1881a00/d; +L_0x1881bb0/d .functor AND 1, L_0x1881db0, L_0x1881a00, C4<1>, C4<1>; +L_0x1881bb0 .delay 1 (20000,20000,20000) L_0x1881bb0/d; +L_0x1881f10/d .functor AND 1, L_0x1882020, L_0x1882330, C4<1>, C4<1>; +L_0x1881f10 .delay 1 (20000,20000,20000) L_0x1881f10/d; +L_0x18821d0/d .functor OR 1, L_0x1881bb0, L_0x1881f10, C4<0>, C4<0>; +L_0x18821d0 .delay 1 (20000,20000,20000) L_0x18821d0/d; +v0x17cf280_0 .net *"_s1", 0 0, L_0x1881db0; 1 drivers +v0x17cf360_0 .net *"_s3", 0 0, L_0x1882020; 1 drivers +v0x17cf440_0 .net "addr", 0 0, L_0x1882330; 1 drivers +v0x17cf510_0 .net "in", 1 0, L_0x1882490; 1 drivers +v0x17cf5f0_0 .net "naddr", 0 0, L_0x1881a00; 1 drivers +v0x17cf700_0 .net "o0", 0 0, L_0x1881bb0; 1 drivers +v0x17cf7c0_0 .net "o1", 0 0, L_0x1881f10; 1 drivers +v0x17cf880_0 .net "out", 0 0, L_0x18821d0; 1 drivers +L_0x1881db0 .part L_0x1882490, 0, 1; +L_0x1882020 .part L_0x1882490, 1, 1; +S_0x17cf9c0 .scope module, "mux_3" "bitMultiplexer" 4 32, 4 8 0, S_0x17cdab0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "addr" + .port_info 2 /INPUT 2 "in" +L_0x18823d0/d .functor NOT 1, L_0x1882fe0, C4<0>, C4<0>, C4<0>; +L_0x18823d0 .delay 1 (10000,10000,10000) L_0x18823d0/d; +L_0x18825c0/d .functor AND 1, L_0x18827c0, L_0x18823d0, C4<1>, C4<1>; +L_0x18825c0 .delay 1 (20000,20000,20000) L_0x18825c0/d; +L_0x1882920/d .functor AND 1, L_0x1882a30, L_0x1882fe0, C4<1>, C4<1>; +L_0x1882920 .delay 1 (20000,20000,20000) L_0x1882920/d; +L_0x1882be0/d .functor OR 1, L_0x18825c0, L_0x1882920, C4<0>, C4<0>; +L_0x1882be0 .delay 1 (20000,20000,20000) L_0x1882be0/d; +v0x17cfbf0_0 .net *"_s1", 0 0, L_0x18827c0; 1 drivers +v0x17cfcf0_0 .net *"_s3", 0 0, L_0x1882a30; 1 drivers +v0x17cfdd0_0 .net "addr", 0 0, L_0x1882fe0; 1 drivers +v0x17cfe70_0 .net "in", 1 0, L_0x18830d0; 1 drivers +v0x17cff50_0 .net "naddr", 0 0, L_0x18823d0; 1 drivers +v0x17d0060_0 .net "o0", 0 0, L_0x18825c0; 1 drivers +v0x17d0120_0 .net "o1", 0 0, L_0x1882920; 1 drivers +v0x17d01e0_0 .net "out", 0 0, L_0x1882be0; 1 drivers +L_0x18827c0 .part L_0x18830d0, 0, 1; +L_0x1882a30 .part L_0x18830d0, 1, 1; +S_0x17d0320 .scope module, "mux_mid_0" "bitMultiplexer" 4 33, 4 8 0, S_0x17cdab0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "addr" + .port_info 2 /INPUT 2 "in" +L_0x1883170/d .functor NOT 1, L_0x1883910, C4<0>, C4<0>, C4<0>; +L_0x1883170 .delay 1 (10000,10000,10000) L_0x1883170/d; +L_0x1883230/d .functor AND 1, L_0x1883390, L_0x1883170, C4<1>, C4<1>; +L_0x1883230 .delay 1 (20000,20000,20000) L_0x1883230/d; +L_0x18834f0/d .functor AND 1, L_0x1883600, L_0x1883910, C4<1>, C4<1>; +L_0x18834f0 .delay 1 (20000,20000,20000) L_0x18834f0/d; +L_0x18837b0/d .functor OR 1, L_0x1883230, L_0x18834f0, C4<0>, C4<0>; +L_0x18837b0 .delay 1 (20000,20000,20000) L_0x18837b0/d; +v0x17d05a0_0 .net *"_s1", 0 0, L_0x1883390; 1 drivers +v0x17d06a0_0 .net *"_s3", 0 0, L_0x1883600; 1 drivers +v0x17d0780_0 .net "addr", 0 0, L_0x1883910; 1 drivers +v0x17d0820_0 .net "in", 1 0, L_0x1883a70; 1 drivers +v0x17d0900_0 .net "naddr", 0 0, L_0x1883170; 1 drivers +v0x17d0a10_0 .net "o0", 0 0, L_0x1883230; 1 drivers +v0x17d0ad0_0 .net "o1", 0 0, L_0x18834f0; 1 drivers +v0x17d0b90_0 .net "out", 0 0, L_0x18837b0; 1 drivers +L_0x1883390 .part L_0x1883a70, 0, 1; +L_0x1883600 .part L_0x1883a70, 1, 1; +S_0x17d0cd0 .scope module, "mux_mid_1" "bitMultiplexer" 4 34, 4 8 0, S_0x17cdab0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "addr" + .port_info 2 /INPUT 2 "in" +L_0x1883b10/d .functor NOT 1, L_0x1884500, C4<0>, C4<0>, C4<0>; +L_0x1883b10 .delay 1 (10000,10000,10000) L_0x1883b10/d; +L_0x1883bd0/d .functor AND 1, L_0x1883d80, L_0x1883b10, C4<1>, C4<1>; +L_0x1883bd0 .delay 1 (20000,20000,20000) L_0x1883bd0/d; +L_0x1883ee0/d .functor AND 1, L_0x1883ff0, L_0x1884500, C4<1>, C4<1>; +L_0x1883ee0 .delay 1 (20000,20000,20000) L_0x1883ee0/d; +L_0x18841a0/d .functor OR 1, L_0x1883bd0, L_0x1883ee0, C4<0>, C4<0>; +L_0x18841a0 .delay 1 (20000,20000,20000) L_0x18841a0/d; +v0x17d0f00_0 .net *"_s1", 0 0, L_0x1883d80; 1 drivers +v0x17d1000_0 .net *"_s3", 0 0, L_0x1883ff0; 1 drivers +v0x17d10e0_0 .net "addr", 0 0, L_0x1884500; 1 drivers +v0x17d1180_0 .net "in", 1 0, L_0x18845a0; 1 drivers +v0x17d1260_0 .net "naddr", 0 0, L_0x1883b10; 1 drivers +v0x17d1370_0 .net "o0", 0 0, L_0x1883bd0; 1 drivers +v0x17d1430_0 .net "o1", 0 0, L_0x1883ee0; 1 drivers +v0x17d14f0_0 .net "out", 0 0, L_0x18841a0; 1 drivers +L_0x1883d80 .part L_0x18845a0, 0, 1; +L_0x1883ff0 .part L_0x18845a0, 1, 1; +S_0x17d1630 .scope module, "mux_out" "bitMultiplexer" 4 35, 4 8 0, S_0x17cdab0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "addr" + .port_info 2 /INPUT 2 "in" +L_0x18839b0/d .functor NOT 1, L_0x1884de0, C4<0>, C4<0>, C4<0>; +L_0x18839b0 .delay 1 (10000,10000,10000) L_0x18839b0/d; +L_0x1884710/d .functor AND 1, L_0x1884870, L_0x18839b0, C4<1>, C4<1>; +L_0x1884710 .delay 1 (20000,20000,20000) L_0x1884710/d; +L_0x18849d0/d .functor AND 1, L_0x1884ae0, L_0x1884de0, C4<1>, C4<1>; +L_0x18849d0 .delay 1 (20000,20000,20000) L_0x18849d0/d; +L_0x1884cd0/d .functor OR 1, L_0x1884710, L_0x18849d0, C4<0>, C4<0>; +L_0x1884cd0 .delay 1 (20000,20000,20000) L_0x1884cd0/d; +v0x17d1860_0 .net *"_s1", 0 0, L_0x1884870; 1 drivers +v0x17d1960_0 .net *"_s3", 0 0, L_0x1884ae0; 1 drivers +v0x17d1a40_0 .net "addr", 0 0, L_0x1884de0; 1 drivers +v0x17d1ae0_0 .net "in", 1 0, L_0x1884300; alias, 1 drivers +v0x17d1bc0_0 .net "naddr", 0 0, L_0x18839b0; 1 drivers +v0x17d1cd0_0 .net "o0", 0 0, L_0x1884710; 1 drivers +v0x17d1d90_0 .net "o1", 0 0, L_0x18849d0; 1 drivers +v0x17d1e50_0 .net "out", 0 0, L_0x1884cd0; alias, 1 drivers +L_0x1884870 .part L_0x1884300, 0, 1; +L_0x1884ae0 .part L_0x1884300, 1, 1; +S_0x17d23e0 .scope module, "structadder" "structAddSub" 3 22, 5 8 0, S_0x17cd820; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "sub" + .port_info 5 /INPUT 1 "carryin" +L_0x187f530/d .functor XOR 1, L_0x187f860, v0x17dbbc0_0, C4<0>, C4<0>; +L_0x187f530 .delay 1 (20000,20000,20000) L_0x187f530/d; +L_0x1879f90/d .functor XOR 1, L_0x187f7c0, L_0x187f860, C4<0>, C4<0>; +L_0x1879f90 .delay 1 (20000,20000,20000) L_0x1879f90/d; +L_0x187fad0/d .functor XOR 1, L_0x1879f90, L_0x1884f40, C4<0>, C4<0>; +L_0x187fad0 .delay 1 (20000,20000,20000) L_0x187fad0/d; +L_0x187fc80/d .functor AND 1, L_0x187f7c0, L_0x187f860, C4<1>, C4<1>; +L_0x187fc80 .delay 1 (20000,20000,20000) L_0x187fc80/d; +L_0x187fde0/d .functor AND 1, L_0x1879f90, L_0x1884f40, C4<1>, C4<1>; +L_0x187fde0 .delay 1 (20000,20000,20000) L_0x187fde0/d; +L_0x187ff40/d .functor OR 1, L_0x187fde0, L_0x187fc80, C4<0>, C4<0>; +L_0x187ff40 .delay 1 (20000,20000,20000) L_0x187ff40/d; +v0x17d26a0_0 .net "AandB", 0 0, L_0x187fc80; 1 drivers +v0x17d2760_0 .net "AxorB", 0 0, L_0x1879f90; 1 drivers +v0x17d2820_0 .net "AxorBandCarryIn", 0 0, L_0x187fde0; 1 drivers +v0x17d28f0_0 .net "a", 0 0, L_0x187f7c0; alias, 1 drivers +v0x17d29b0_0 .net "b", 0 0, L_0x187f860; alias, 1 drivers +v0x17d2ac0_0 .net "bnew", 0 0, L_0x187f530; 1 drivers +v0x17d2b80_0 .net "carryin", 0 0, L_0x1884f40; alias, 1 drivers +v0x17d2c40_0 .net "carryout", 0 0, L_0x187ff40; alias, 1 drivers +v0x17d2d00_0 .net "sub", 0 0, v0x17dbbc0_0; alias, 1 drivers +v0x17d2e30_0 .net "sum", 0 0, L_0x187fad0; 1 drivers +S_0x17d3cc0 .scope generate, "ripple[31]" "ripple[31]" 3 66, 3 66 0, S_0x16fa6c0; + .timescale -9 -12; +P_0x17d3e90 .param/l "i" 0 3 66, +C4<011111>; +S_0x17d3f50 .scope module, "bit" "BitSliceALU" 3 68, 3 11 0, S_0x17d3cc0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "ALUout" + .port_info 1 /OUTPUT 1 "Cout" + .port_info 2 /INPUT 1 "invertB" + .port_info 3 /INPUT 1 "Cin" + .port_info 4 /INPUT 3 "addr" + .port_info 5 /INPUT 1 "bit1" + .port_info 6 /INPUT 1 "bit2" +L_0x1885a30/d .functor XOR 1, L_0x188a9b0, L_0x182ff50, C4<0>, C4<0>; +L_0x1885a30 .delay 1 (20000,20000,20000) L_0x1885a30/d; +L_0x1885b90/d .functor NAND 1, L_0x188a9b0, L_0x182ff50, C4<1>, C4<1>; +L_0x1885b90 .delay 1 (10000,10000,10000) L_0x1885b90/d; +L_0x1885cf0/d .functor XOR 1, v0x17dbbc0_0, L_0x1885b90, C4<0>, C4<0>; +L_0x1885cf0 .delay 1 (20000,20000,20000) L_0x1885cf0/d; +L_0x1885e00/d .functor NOR 1, L_0x188a9b0, L_0x182ff50, C4<0>, C4<0>; +L_0x1885e00 .delay 1 (10000,10000,10000) L_0x1885e00/d; +L_0x1885f60/d .functor XOR 1, v0x17dbbc0_0, L_0x1885e00, C4<0>, C4<0>; +L_0x1885f60 .delay 1 (20000,20000,20000) L_0x1885f60/d; +v0x17d9720_0 .net "ALUout", 0 0, L_0x188a610; 1 drivers +v0x17d97e0_0 .net "Cin", 0 0, L_0x188a880; 1 drivers +v0x17d98a0_0 .net "Cout", 0 0, L_0x1885880; 1 drivers +v0x17d9970_0 .net *"_s11", 0 0, L_0x1885f60; 1 drivers +o0x7fc2cd934808 .functor BUFZ 1, C4; HiZ drive +; Elide local net with no drivers, v0x17d9a10_0 name=_s15 +o0x7fc2cd934838 .functor BUFZ 3, C4; HiZ drive +; Elide local net with no drivers, v0x17d9b00_0 name=_s17 +v0x17d9be0_0 .net *"_s3", 0 0, L_0x1885a30; 1 drivers +v0x17d9cc0_0 .net *"_s7", 0 0, L_0x1885cf0; 1 drivers +v0x17d9da0_0 .net "addr", 2 0, v0x17dbc90_0; alias, 1 drivers +v0x17d9ef0_0 .net "bit1", 0 0, L_0x188a9b0; 1 drivers +v0x17d9f90_0 .net "bit2", 0 0, L_0x182ff50; 1 drivers +v0x17da060_0 .net "invertB", 0 0, v0x17dbbc0_0; alias, 1 drivers +v0x17da100_0 .net "nanded", 0 0, L_0x1885b90; 1 drivers +v0x17da1a0_0 .net "nored", 0 0, L_0x1885e00; 1 drivers +v0x17da240_0 .net "out", 7 0, L_0x1894ff0; 1 drivers +LS_0x1894ff0_0_0 .concat [ 1 1 1 1], L_0x1885410, L_0x1885a30, o0x7fc2cd934808, L_0x1885cf0; +LS_0x1894ff0_0_4 .concat [ 1 3 0 0], L_0x1885f60, o0x7fc2cd934838; +L_0x1894ff0 .concat [ 4 4 0 0], LS_0x1894ff0_0_0, LS_0x1894ff0_0_4; +S_0x17d41e0 .scope module, "opmux" "structuralMultiplexer" 3 43, 4 21 0, S_0x17d3f50; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 3 "address" + .port_info 2 /INPUT 8 "in" +v0x17d86c0_0 .net "address", 2 0, v0x17dbc90_0; alias, 1 drivers +v0x17d8780_0 .net "in", 7 0, L_0x1894ff0; alias, 1 drivers +v0x17d8860_0 .net "mux", 3 0, L_0x1888680; 1 drivers +v0x17d8920_0 .net "muxmid", 1 0, L_0x1889c40; 1 drivers +v0x17d89e0_0 .net "out", 0 0, L_0x188a610; alias, 1 drivers +L_0x1886860 .part v0x17dbc90_0, 0, 1; +L_0x18869c0 .part L_0x1894ff0, 0, 2; +L_0x18872a0 .part v0x17dbc90_0, 0, 1; +L_0x1887400 .part L_0x1894ff0, 2, 2; +L_0x1887c70 .part v0x17dbc90_0, 0, 1; +L_0x1887dd0 .part L_0x1894ff0, 4, 2; +L_0x1888680 .concat8 [ 1 1 1 1], L_0x1886700, L_0x1887140, L_0x1887b10, L_0x1888520; +L_0x1888920 .part v0x17dbc90_0, 0, 1; +L_0x1888a10 .part L_0x1894ff0, 6, 2; +L_0x1889250 .part v0x17dbc90_0, 1, 1; +L_0x18893b0 .part L_0x1888680, 0, 2; +L_0x1889c40 .concat8 [ 1 1 0 0], L_0x18890f0, L_0x1889ae0; +L_0x1889e40 .part v0x17dbc90_0, 1, 1; +L_0x1889ee0 .part L_0x1888680, 2, 2; +L_0x188a720 .part v0x17dbc90_0, 2, 1; +S_0x17d4450 .scope module, "mux_0" "bitMultiplexer" 4 29, 4 8 0, S_0x17d41e0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "addr" + .port_info 2 /INPUT 2 "in" +L_0x1886070/d .functor NOT 1, L_0x1886860, C4<0>, C4<0>, C4<0>; +L_0x1886070 .delay 1 (10000,10000,10000) L_0x1886070/d; +L_0x18861d0/d .functor AND 1, L_0x18862e0, L_0x1886070, C4<1>, C4<1>; +L_0x18861d0 .delay 1 (20000,20000,20000) L_0x18861d0/d; +L_0x1886440/d .functor AND 1, L_0x1886550, L_0x1886860, C4<1>, C4<1>; +L_0x1886440 .delay 1 (20000,20000,20000) L_0x1886440/d; +L_0x1886700/d .functor OR 1, L_0x18861d0, L_0x1886440, C4<0>, C4<0>; +L_0x1886700 .delay 1 (20000,20000,20000) L_0x1886700/d; +v0x17d46c0_0 .net *"_s1", 0 0, L_0x18862e0; 1 drivers +v0x17d47c0_0 .net *"_s3", 0 0, L_0x1886550; 1 drivers +v0x17d48a0_0 .net "addr", 0 0, L_0x1886860; 1 drivers +v0x17d4970_0 .net "in", 1 0, L_0x18869c0; 1 drivers +v0x17d4a50_0 .net "naddr", 0 0, L_0x1886070; 1 drivers +v0x17d4b60_0 .net "o0", 0 0, L_0x18861d0; 1 drivers +v0x17d4c20_0 .net "o1", 0 0, L_0x1886440; 1 drivers +v0x17d4ce0_0 .net "out", 0 0, L_0x1886700; 1 drivers +L_0x18862e0 .part L_0x18869c0, 0, 1; +L_0x1886550 .part L_0x18869c0, 1, 1; +S_0x17d4e20 .scope module, "mux_1" "bitMultiplexer" 4 30, 4 8 0, S_0x17d41e0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "addr" + .port_info 2 /INPUT 2 "in" +L_0x1886a60/d .functor NOT 1, L_0x18872a0, C4<0>, C4<0>, C4<0>; +L_0x1886a60 .delay 1 (10000,10000,10000) L_0x1886a60/d; +L_0x1886b20/d .functor AND 1, L_0x1886d20, L_0x1886a60, C4<1>, C4<1>; +L_0x1886b20 .delay 1 (20000,20000,20000) L_0x1886b20/d; +L_0x1886e80/d .functor AND 1, L_0x1886f90, L_0x18872a0, C4<1>, C4<1>; +L_0x1886e80 .delay 1 (20000,20000,20000) L_0x1886e80/d; +L_0x1887140/d .functor OR 1, L_0x1886b20, L_0x1886e80, C4<0>, C4<0>; +L_0x1887140 .delay 1 (20000,20000,20000) L_0x1887140/d; +v0x17d5050_0 .net *"_s1", 0 0, L_0x1886d20; 1 drivers +v0x17d5150_0 .net *"_s3", 0 0, L_0x1886f90; 1 drivers +v0x17d5230_0 .net "addr", 0 0, L_0x18872a0; 1 drivers +v0x17d52d0_0 .net "in", 1 0, L_0x1887400; 1 drivers +v0x17d53b0_0 .net "naddr", 0 0, L_0x1886a60; 1 drivers +v0x17d54c0_0 .net "o0", 0 0, L_0x1886b20; 1 drivers +v0x17d5580_0 .net "o1", 0 0, L_0x1886e80; 1 drivers +v0x17d5640_0 .net "out", 0 0, L_0x1887140; 1 drivers +L_0x1886d20 .part L_0x1887400, 0, 1; +L_0x1886f90 .part L_0x1887400, 1, 1; +S_0x17d5780 .scope module, "mux_2" "bitMultiplexer" 4 31, 4 8 0, S_0x17d41e0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "addr" + .port_info 2 /INPUT 2 "in" +L_0x1887340/d .functor NOT 1, L_0x1887c70, C4<0>, C4<0>, C4<0>; +L_0x1887340 .delay 1 (10000,10000,10000) L_0x1887340/d; +L_0x18874f0/d .functor AND 1, L_0x18876f0, L_0x1887340, C4<1>, C4<1>; +L_0x18874f0 .delay 1 (20000,20000,20000) L_0x18874f0/d; +L_0x1887850/d .functor AND 1, L_0x1887960, L_0x1887c70, C4<1>, C4<1>; +L_0x1887850 .delay 1 (20000,20000,20000) L_0x1887850/d; +L_0x1887b10/d .functor OR 1, L_0x18874f0, L_0x1887850, C4<0>, C4<0>; +L_0x1887b10 .delay 1 (20000,20000,20000) L_0x1887b10/d; +v0x17d59b0_0 .net *"_s1", 0 0, L_0x18876f0; 1 drivers +v0x17d5a90_0 .net *"_s3", 0 0, L_0x1887960; 1 drivers +v0x17d5b70_0 .net "addr", 0 0, L_0x1887c70; 1 drivers +v0x17d5c40_0 .net "in", 1 0, L_0x1887dd0; 1 drivers +v0x17d5d20_0 .net "naddr", 0 0, L_0x1887340; 1 drivers +v0x17d5e30_0 .net "o0", 0 0, L_0x18874f0; 1 drivers +v0x17d5ef0_0 .net "o1", 0 0, L_0x1887850; 1 drivers +v0x17d5fb0_0 .net "out", 0 0, L_0x1887b10; 1 drivers +L_0x18876f0 .part L_0x1887dd0, 0, 1; +L_0x1887960 .part L_0x1887dd0, 1, 1; +S_0x17d60f0 .scope module, "mux_3" "bitMultiplexer" 4 32, 4 8 0, S_0x17d41e0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "addr" + .port_info 2 /INPUT 2 "in" +L_0x1887d10/d .functor NOT 1, L_0x1888920, C4<0>, C4<0>, C4<0>; +L_0x1887d10 .delay 1 (10000,10000,10000) L_0x1887d10/d; +L_0x1887f00/d .functor AND 1, L_0x1888100, L_0x1887d10, C4<1>, C4<1>; +L_0x1887f00 .delay 1 (20000,20000,20000) L_0x1887f00/d; +L_0x1888260/d .functor AND 1, L_0x1888370, L_0x1888920, C4<1>, C4<1>; +L_0x1888260 .delay 1 (20000,20000,20000) L_0x1888260/d; +L_0x1888520/d .functor OR 1, L_0x1887f00, L_0x1888260, C4<0>, C4<0>; +L_0x1888520 .delay 1 (20000,20000,20000) L_0x1888520/d; +v0x17d6320_0 .net *"_s1", 0 0, L_0x1888100; 1 drivers +v0x17d6420_0 .net *"_s3", 0 0, L_0x1888370; 1 drivers +v0x17d6500_0 .net "addr", 0 0, L_0x1888920; 1 drivers +v0x17d65a0_0 .net "in", 1 0, L_0x1888a10; 1 drivers +v0x17d6680_0 .net "naddr", 0 0, L_0x1887d10; 1 drivers +v0x17d6790_0 .net "o0", 0 0, L_0x1887f00; 1 drivers +v0x17d6850_0 .net "o1", 0 0, L_0x1888260; 1 drivers +v0x17d6910_0 .net "out", 0 0, L_0x1888520; 1 drivers +L_0x1888100 .part L_0x1888a10, 0, 1; +L_0x1888370 .part L_0x1888a10, 1, 1; +S_0x17d6a50 .scope module, "mux_mid_0" "bitMultiplexer" 4 33, 4 8 0, S_0x17d41e0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "addr" + .port_info 2 /INPUT 2 "in" +L_0x1888ab0/d .functor NOT 1, L_0x1889250, C4<0>, C4<0>, C4<0>; +L_0x1888ab0 .delay 1 (10000,10000,10000) L_0x1888ab0/d; +L_0x1888b70/d .functor AND 1, L_0x1888cd0, L_0x1888ab0, C4<1>, C4<1>; +L_0x1888b70 .delay 1 (20000,20000,20000) L_0x1888b70/d; +L_0x1888e30/d .functor AND 1, L_0x1888f40, L_0x1889250, C4<1>, C4<1>; +L_0x1888e30 .delay 1 (20000,20000,20000) L_0x1888e30/d; +L_0x18890f0/d .functor OR 1, L_0x1888b70, L_0x1888e30, C4<0>, C4<0>; +L_0x18890f0 .delay 1 (20000,20000,20000) L_0x18890f0/d; +v0x17d6cd0_0 .net *"_s1", 0 0, L_0x1888cd0; 1 drivers +v0x17d6dd0_0 .net *"_s3", 0 0, L_0x1888f40; 1 drivers +v0x17d6eb0_0 .net "addr", 0 0, L_0x1889250; 1 drivers +v0x17d6f50_0 .net "in", 1 0, L_0x18893b0; 1 drivers +v0x17d7030_0 .net "naddr", 0 0, L_0x1888ab0; 1 drivers +v0x17d7140_0 .net "o0", 0 0, L_0x1888b70; 1 drivers +v0x17d7200_0 .net "o1", 0 0, L_0x1888e30; 1 drivers +v0x17d72c0_0 .net "out", 0 0, L_0x18890f0; 1 drivers +L_0x1888cd0 .part L_0x18893b0, 0, 1; +L_0x1888f40 .part L_0x18893b0, 1, 1; +S_0x17d7400 .scope module, "mux_mid_1" "bitMultiplexer" 4 34, 4 8 0, S_0x17d41e0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "addr" + .port_info 2 /INPUT 2 "in" +L_0x1889450/d .functor NOT 1, L_0x1889e40, C4<0>, C4<0>, C4<0>; +L_0x1889450 .delay 1 (10000,10000,10000) L_0x1889450/d; +L_0x1889510/d .functor AND 1, L_0x18896c0, L_0x1889450, C4<1>, C4<1>; +L_0x1889510 .delay 1 (20000,20000,20000) L_0x1889510/d; +L_0x1889820/d .functor AND 1, L_0x1889930, L_0x1889e40, C4<1>, C4<1>; +L_0x1889820 .delay 1 (20000,20000,20000) L_0x1889820/d; +L_0x1889ae0/d .functor OR 1, L_0x1889510, L_0x1889820, C4<0>, C4<0>; +L_0x1889ae0 .delay 1 (20000,20000,20000) L_0x1889ae0/d; +v0x17d7630_0 .net *"_s1", 0 0, L_0x18896c0; 1 drivers +v0x17d7730_0 .net *"_s3", 0 0, L_0x1889930; 1 drivers +v0x17d7810_0 .net "addr", 0 0, L_0x1889e40; 1 drivers +v0x17d78b0_0 .net "in", 1 0, L_0x1889ee0; 1 drivers +v0x17d7990_0 .net "naddr", 0 0, L_0x1889450; 1 drivers +v0x17d7aa0_0 .net "o0", 0 0, L_0x1889510; 1 drivers +v0x17d7b60_0 .net "o1", 0 0, L_0x1889820; 1 drivers +v0x17d7c20_0 .net "out", 0 0, L_0x1889ae0; 1 drivers +L_0x18896c0 .part L_0x1889ee0, 0, 1; +L_0x1889930 .part L_0x1889ee0, 1, 1; +S_0x17d7d60 .scope module, "mux_out" "bitMultiplexer" 4 35, 4 8 0, S_0x17d41e0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "addr" + .port_info 2 /INPUT 2 "in" +L_0x18892f0/d .functor NOT 1, L_0x188a720, C4<0>, C4<0>, C4<0>; +L_0x18892f0 .delay 1 (10000,10000,10000) L_0x18892f0/d; +L_0x188a050/d .functor AND 1, L_0x188a1b0, L_0x18892f0, C4<1>, C4<1>; +L_0x188a050 .delay 1 (20000,20000,20000) L_0x188a050/d; +L_0x188a310/d .functor AND 1, L_0x188a420, L_0x188a720, C4<1>, C4<1>; +L_0x188a310 .delay 1 (20000,20000,20000) L_0x188a310/d; +L_0x188a610/d .functor OR 1, L_0x188a050, L_0x188a310, C4<0>, C4<0>; +L_0x188a610 .delay 1 (20000,20000,20000) L_0x188a610/d; +v0x17d7f90_0 .net *"_s1", 0 0, L_0x188a1b0; 1 drivers +v0x17d8090_0 .net *"_s3", 0 0, L_0x188a420; 1 drivers +v0x17d8170_0 .net "addr", 0 0, L_0x188a720; 1 drivers +v0x17d8210_0 .net "in", 1 0, L_0x1889c40; alias, 1 drivers +v0x17d82f0_0 .net "naddr", 0 0, L_0x18892f0; 1 drivers +v0x17d8400_0 .net "o0", 0 0, L_0x188a050; 1 drivers +v0x17d84c0_0 .net "o1", 0 0, L_0x188a310; 1 drivers +v0x17d8580_0 .net "out", 0 0, L_0x188a610; alias, 1 drivers +L_0x188a1b0 .part L_0x1889c40, 0, 1; +L_0x188a420 .part L_0x1889c40, 1, 1; +S_0x17d8b10 .scope module, "structadder" "structAddSub" 3 22, 5 8 0, S_0x17d3f50; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "sub" + .port_info 5 /INPUT 1 "carryin" +L_0x1884e80/d .functor XOR 1, L_0x182ff50, v0x17dbbc0_0, C4<0>, C4<0>; +L_0x1884e80 .delay 1 (20000,20000,20000) L_0x1884e80/d; +L_0x1885350/d .functor XOR 1, L_0x188a9b0, L_0x182ff50, C4<0>, C4<0>; +L_0x1885350 .delay 1 (20000,20000,20000) L_0x1885350/d; +L_0x1885410/d .functor XOR 1, L_0x1885350, L_0x188a880, C4<0>, C4<0>; +L_0x1885410 .delay 1 (20000,20000,20000) L_0x1885410/d; +L_0x18855c0/d .functor AND 1, L_0x188a9b0, L_0x182ff50, C4<1>, C4<1>; +L_0x18855c0 .delay 1 (20000,20000,20000) L_0x18855c0/d; +L_0x1885720/d .functor AND 1, L_0x1885350, L_0x188a880, C4<1>, C4<1>; +L_0x1885720 .delay 1 (20000,20000,20000) L_0x1885720/d; +L_0x1885880/d .functor OR 1, L_0x1885720, L_0x18855c0, C4<0>, C4<0>; +L_0x1885880 .delay 1 (20000,20000,20000) L_0x1885880/d; +v0x17d8dd0_0 .net "AandB", 0 0, L_0x18855c0; 1 drivers +v0x17d8e90_0 .net "AxorB", 0 0, L_0x1885350; 1 drivers +v0x17d8f50_0 .net "AxorBandCarryIn", 0 0, L_0x1885720; 1 drivers +v0x17d9020_0 .net "a", 0 0, L_0x188a9b0; alias, 1 drivers +v0x17d90e0_0 .net "b", 0 0, L_0x182ff50; alias, 1 drivers +v0x17d91f0_0 .net "bnew", 0 0, L_0x1884e80; 1 drivers +v0x17d92b0_0 .net "carryin", 0 0, L_0x188a880; alias, 1 drivers +v0x17d9370_0 .net "carryout", 0 0, L_0x1885880; alias, 1 drivers +v0x17d9430_0 .net "sub", 0 0, v0x17dbbc0_0; alias, 1 drivers +v0x17d9560_0 .net "sum", 0 0, L_0x1885410; 1 drivers +S_0x17db900 .scope module, "controller" "ALUcontrolLUT" 2 47, 2 13 0, S_0x171a660; + .timescale -9 -12; + .port_info 0 /OUTPUT 3 "muxindex" + .port_info 1 /OUTPUT 1 "invertB" + .port_info 2 /OUTPUT 1 "flagger" + .port_info 3 /INPUT 3 "ALUcommand" +v0x1777ab0_0 .net "ALUcommand", 2 0, v0x17dbe90_0; 1 drivers +v0x17dbad0_0 .var "flagger", 0 0; +v0x17dbbc0_0 .var "invertB", 0 0; +v0x17dbc90_0 .var "muxindex", 2 0; +E_0x1778b20 .event edge, v0x1777ab0_0; + .scope S_0x17db900; +T_0 ; + %wait E_0x1778b20; + %load/vec4 v0x1777ab0_0; + %dup/vec4; + %pushi/vec4 0, 0, 3; + %cmp/u; + %jmp/1 T_0.0, 6; + %dup/vec4; + %pushi/vec4 1, 0, 3; + %cmp/u; + %jmp/1 T_0.1, 6; + %dup/vec4; + %pushi/vec4 2, 0, 3; + %cmp/u; + %jmp/1 T_0.2, 6; + %dup/vec4; + %pushi/vec4 3, 0, 3; + %cmp/u; + %jmp/1 T_0.3, 6; + %dup/vec4; + %pushi/vec4 4, 0, 3; + %cmp/u; + %jmp/1 T_0.4, 6; + %dup/vec4; + %pushi/vec4 5, 0, 3; + %cmp/u; + %jmp/1 T_0.5, 6; + %dup/vec4; + %pushi/vec4 6, 0, 3; + %cmp/u; + %jmp/1 T_0.6, 6; + %dup/vec4; + %pushi/vec4 7, 0, 3; + %cmp/u; + %jmp/1 T_0.7, 6; + %jmp T_0.8; +T_0.0 ; + %pushi/vec4 0, 0, 3; + %store/vec4 v0x17dbc90_0, 0, 3; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x17dbbc0_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x17dbad0_0, 0, 1; + %jmp T_0.8; +T_0.1 ; + %pushi/vec4 0, 0, 3; + %store/vec4 v0x17dbc90_0, 0, 3; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x17dbbc0_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x17dbad0_0, 0, 1; + %jmp T_0.8; +T_0.2 ; + %pushi/vec4 1, 0, 3; + %store/vec4 v0x17dbc90_0, 0, 3; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x17dbbc0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x17dbad0_0, 0, 1; + %jmp T_0.8; +T_0.3 ; + %pushi/vec4 2, 0, 3; + %store/vec4 v0x17dbc90_0, 0, 3; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x17dbbc0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x17dbad0_0, 0, 1; + %jmp T_0.8; +T_0.4 ; + %pushi/vec4 3, 0, 3; + %store/vec4 v0x17dbc90_0, 0, 3; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x17dbbc0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x17dbad0_0, 0, 1; + %jmp T_0.8; +T_0.5 ; + %pushi/vec4 3, 0, 3; + %store/vec4 v0x17dbc90_0, 0, 3; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x17dbbc0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x17dbad0_0, 0, 1; + %jmp T_0.8; +T_0.6 ; + %pushi/vec4 4, 0, 3; + %store/vec4 v0x17dbc90_0, 0, 3; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x17dbbc0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x17dbad0_0, 0, 1; + %jmp T_0.8; +T_0.7 ; + %pushi/vec4 4, 0, 3; + %store/vec4 v0x17dbc90_0, 0, 3; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x17dbbc0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x17dbad0_0, 0, 1; + %jmp T_0.8; +T_0.8 ; + %pop/vec4 1; + %jmp T_0; + .thread T_0, $push; + .scope S_0x171a660; +T_1 ; + %vpi_call 2 52 "$dumpfile", "alu.vcd" {0 0 0}; + %vpi_call 2 53 "$dumpvars", 32'sb00000000000000000000000000000000, v0x17dc210_0, v0x17dc2b0_0, v0x17dc420_0, v0x17dc350_0, v0x17dbe90_0, v0x17dc120_0, v0x17dc080_0 {0 0 0}; + %vpi_call 2 55 "$display", " A | B | Com | Out " {0 0 0}; + %pushi/vec4 4294961938, 0, 32; + %store/vec4 v0x17dc210_0, 0, 32; + %pushi/vec4 5369, 0, 32; + %store/vec4 v0x17dc2b0_0, 0, 32; + %pushi/vec4 0, 0, 3; + %store/vec4 v0x17dbe90_0, 0, 3; + %delay 1000000, 0; + %load/vec4 v0x17dc210_0; + %load/vec4 v0x17dc2b0_0; + %load/vec4 v0x17dc420_0; + %vpi_call 2 60 "$display", " %d | %d | %d | %d ", S<2,vec4,s32>, S<1,vec4,s32>, v0x17dbe90_0, S<0,vec4,s32> {3 0 0}; + %pushi/vec4 552, 0, 32; + %store/vec4 v0x17dc210_0, 0, 32; + %pushi/vec4 600, 0, 32; + %store/vec4 v0x17dc2b0_0, 0, 32; + %pushi/vec4 1, 0, 3; + %store/vec4 v0x17dbe90_0, 0, 3; + %delay 1000000, 0; + %load/vec4 v0x17dc210_0; + %load/vec4 v0x17dc2b0_0; + %load/vec4 v0x17dc420_0; + %vpi_call 2 65 "$display", " %d | %d | %d | %d ", S<2,vec4,s32>, S<1,vec4,s32>, v0x17dbe90_0, S<0,vec4,s32> {3 0 0}; + %pushi/vec4 300, 0, 32; + %store/vec4 v0x17dc210_0, 0, 32; + %pushi/vec4 25, 0, 32; + %store/vec4 v0x17dc2b0_0, 0, 32; + %pushi/vec4 2, 0, 3; + %store/vec4 v0x17dbe90_0, 0, 3; + %delay 1000000, 0; + %load/vec4 v0x17dc210_0; + %load/vec4 v0x17dc2b0_0; + %load/vec4 v0x17dc420_0; + %vpi_call 2 70 "$display", " %d | %d | %d | %d ", S<2,vec4,s32>, S<1,vec4,s32>, v0x17dbe90_0, S<0,vec4,s32> {3 0 0}; + %pushi/vec4 360, 0, 32; + %store/vec4 v0x17dc210_0, 0, 32; + %pushi/vec4 111, 0, 32; + %store/vec4 v0x17dc2b0_0, 0, 32; + %pushi/vec4 4, 0, 3; + %store/vec4 v0x17dbe90_0, 0, 3; + %delay 1000000, 0; + %load/vec4 v0x17dc210_0; + %load/vec4 v0x17dc2b0_0; + %load/vec4 v0x17dc420_0; + %vpi_call 2 75 "$display", " %d | %d | %d | %d ", S<2,vec4,s32>, S<1,vec4,s32>, v0x17dbe90_0, S<0,vec4,s32> {3 0 0}; + %pushi/vec4 4294967294, 0, 32; + %store/vec4 v0x17dc210_0, 0, 32; + %pushi/vec4 4294906602, 0, 32; + %store/vec4 v0x17dc2b0_0, 0, 32; + %pushi/vec4 5, 0, 3; + %store/vec4 v0x17dbe90_0, 0, 3; + %delay 1000000, 0; + %load/vec4 v0x17dc210_0; + %load/vec4 v0x17dc2b0_0; + %load/vec4 v0x17dc420_0; + %vpi_call 2 80 "$display", " %d | %d | %d | %d ", S<2,vec4,s32>, S<1,vec4,s32>, v0x17dbe90_0, S<0,vec4,s32> {3 0 0}; + %pushi/vec4 4294964337, 0, 32; + %store/vec4 v0x17dc210_0, 0, 32; + %pushi/vec4 6333, 0, 32; + %store/vec4 v0x17dc2b0_0, 0, 32; + %pushi/vec4 6, 0, 3; + %store/vec4 v0x17dbe90_0, 0, 3; + %delay 1000000, 0; + %load/vec4 v0x17dc210_0; + %load/vec4 v0x17dc2b0_0; + %load/vec4 v0x17dc420_0; + %vpi_call 2 85 "$display", " %d | %d | %d | %d ", S<2,vec4,s32>, S<1,vec4,s32>, v0x17dbe90_0, S<0,vec4,s32> {3 0 0}; + %pushi/vec4 4294966251, 0, 32; + %store/vec4 v0x17dc210_0, 0, 32; + %pushi/vec4 54968, 0, 32; + %store/vec4 v0x17dc2b0_0, 0, 32; + %pushi/vec4 7, 0, 3; + %store/vec4 v0x17dbe90_0, 0, 3; + %delay 1000000, 0; + %load/vec4 v0x17dc210_0; + %load/vec4 v0x17dc2b0_0; + %load/vec4 v0x17dc420_0; + %vpi_call 2 90 "$display", " %d | %d | %d | %d ", S<2,vec4,s32>, S<1,vec4,s32>, v0x17dbe90_0, S<0,vec4,s32> {3 0 0}; + %end; + .thread T_1; +# The file index is used to find the file name in the following table. +:file_names 6; + "N/A"; + ""; + "alu.t.v"; + "./alu.v"; + "./multiplexer.v"; + "./AddSub.v"; From af8352682071bec926ec35687aa2b602995d2d2b Mon Sep 17 00:00:00 2001 From: juicyslew Date: Tue, 10 Oct 2017 14:44:08 -0400 Subject: [PATCH 03/11] small edits --- AddSub.v | 6 +++--- alu.v | 3 ++- 2 files changed, 5 insertions(+), 4 deletions(-) diff --git a/AddSub.v b/AddSub.v index ad7889b..836f71f 100644 --- a/AddSub.v +++ b/AddSub.v @@ -12,16 +12,16 @@ module structAddSub input a, input b, input sub, carryin -); +); //Add 1 to least significant bit during subtraction wire AxorB; wire AandB; wire AxorBandCarryIn; wire bnew; `XOR (bnew, b, sub); - `XOR (AxorB, a, b); + `XOR (AxorB, a, bnew); `XOR (sum, AxorB, carryin); - `AND (AandB, a, b); + `AND (AandB, a, bnew); `AND (AxorBandCarryIn, AxorB, carryin); `OR (carryout, AxorBandCarryIn, AandB); endmodule diff --git a/alu.v b/alu.v index 9e1cd2e..b8475c5 100755 --- a/alu.v +++ b/alu.v @@ -19,6 +19,7 @@ module BitSliceALU ); wire Cout; wire [7:0] out; + structAddSub structadder(out[0], Cout, bit1, bit2, invertB, Cin); wire nored, nanded; @@ -53,7 +54,7 @@ input[31:0] operandA, input[31:0] operandB, input[2:0] mux, input invertB, -input flags +input flagger ); //wire control2; wire overflow; From 53693ea4a5deb28f6e8c4b6b73ea4a6738beea4f Mon Sep 17 00:00:00 2001 From: Xiaozheng Xu Date: Tue, 10 Oct 2017 18:53:12 -0400 Subject: [PATCH 04/11] adding minor changes to add one when subtracting, changing interface of ALU to match instruction and assigning the zero flag. Code is not tested yet. --- alu.t.v | 22 ---------------------- alu.v | 46 +++++++++++++++++++++++++++++++++++++--------- 2 files changed, 37 insertions(+), 31 deletions(-) diff --git a/alu.t.v b/alu.t.v index 35e9e74..ce87d36 100755 --- a/alu.t.v +++ b/alu.t.v @@ -10,28 +10,6 @@ `define opNOR 3'd6 `define opOR 3'd7 -module ALUcontrolLUT -( -output reg[2:0] muxindex, -output reg invertB, -output reg flagger, -input[2:0] ALUcommand -); - - always @(ALUcommand) begin - case (ALUcommand) - `opADD: begin muxindex = 0; invertB=0; flagger = 1; end - `opSUB: begin muxindex = 0; invertB=1; flagger = 1; end - `opXOR: begin muxindex = 1; invertB=0; flagger = 0; end - `opSLT: begin muxindex = 2; invertB=0; flagger = 0; end - `opAND: begin muxindex = 3; invertB=1; flagger = 0; end - `opNAND: begin muxindex = 3; invertB=0; flagger = 0; end - `opNOR: begin muxindex = 4; invertB=0; flagger = 0; end - `opOR: begin muxindex = 4; invertB=1; flagger = 0; end - endcase - end -endmodule - module ALUTestBench(); reg[2:0] command; reg[31:0] operandA; diff --git a/alu.v b/alu.v index b8475c5..f856cef 100755 --- a/alu.v +++ b/alu.v @@ -27,10 +27,10 @@ module BitSliceALU `XOR (out[1], bit1, bit2); `NAND (nanded, bit1, bit2); - `XOR (out[3], invertB, nanded); + `XOR (out[2], invertB, nanded); `NOR (nored, bit1, bit2); - `XOR (out[4], invertB, nored); + `XOR (out[3], invertB, nored); //`XOR (out[2], bit1, bit2); /*wire sum, Cout; @@ -41,7 +41,30 @@ module BitSliceALU assign out[1] = bit2;*/ //assign out[7:0] = 8'b0; - structuralMultiplexer opmux(ALUout, addr, out); + structuralMultiplexer opmux(ALUout, addr, out); //Can potentially change the mux to be 4 input +endmodule + + +module ALUcontrolLUT +( +output reg[2:0] muxindex, +output reg invertB, +output reg flagger, +input[2:0] ALUcommand +); + + always @(ALUcommand) begin + case (ALUcommand) + `opADD: begin muxindex = 0; invertB=0; flagger = 1; end + `opSUB: begin muxindex = 0; invertB=1; flagger = 1; end + `opXOR: begin muxindex = 1; invertB=0; flagger = 0; end + `opSLT: begin muxindex = 0; invertB=0; flagger = 0; end + `opAND: begin muxindex = 2; invertB=1; flagger = 0; end + `opNAND: begin muxindex = 2; invertB=0; flagger = 0; end + `opNOR: begin muxindex = 3; invertB=0; flagger = 0; end + `opOR: begin muxindex = 3; invertB=1; flagger = 0; end + endcase + end endmodule module ALU @@ -52,16 +75,20 @@ output zero, output overflow, input[31:0] operandA, input[31:0] operandB, -input[2:0] mux, -input invertB, -input flagger +input[2:0] command, +//input invertB, +//input flagger ); //wire control2; wire overflow; wire[31:0] Cout; + reg invertB; + reg flagger; + reg muxindex; //integer i = 0; - BitSliceALU bit0(result[0], Cout[0], invertB, 1'b0, mux, operandA[0], operandB[0]); - //always @(*) + //for the 0th bit slice, pass in invertB for Cin too (add one if subtracting) + BitSliceALU bit0(result[0], Cout[0], invertB, invertB, mux, operandA[0], operandB[0]); + ALUcontrolLUT ctrl(muxindex, invertB, flagger, command); genvar i; generate for (i = 1; i < 32; i = i+1) @@ -69,7 +96,8 @@ input flagger BitSliceALU bit(result[i], Cout[i], invertB, Cout[i-1], mux, operandA[i], operandB[i]); end endgenerate + //BitSliceALU bit31(result[31], Cout[31], invertB, Cout[30], mux, operandA[31], operandB[31]); - + assign zero = ^result; //a bit wise OR on all bits of result, might not be allowed to do this `XOR (overflow, Cout[31], Cout[30]); endmodule From 2476ad553082351a828103f79059285da5b9c9cd Mon Sep 17 00:00:00 2001 From: Xiaozheng Xu Date: Tue, 10 Oct 2017 23:18:29 -0400 Subject: [PATCH 05/11] Working ALU with all functionality, but not comprehensive testing. --- TheBigOR.v | 26 +++++ alu.t.v | 52 ++++----- alu.v | 67 +++++++---- alu.vcd | 312 ++++++++++++++++++++++++++++++++------------------ multiplexer.v | 23 +++- 5 files changed, 313 insertions(+), 167 deletions(-) create mode 100644 TheBigOR.v diff --git a/TheBigOR.v b/TheBigOR.v new file mode 100644 index 0000000..34335f2 --- /dev/null +++ b/TheBigOR.v @@ -0,0 +1,26 @@ +`timescale 1 ns / 1 ps +`define BIGOR or #320 + +module TheBigOR +( + output out, + input[31:0] in +); +`BIGOR (out, in[0], in[1], in[2], in[3], in[4], in[5], in[6], in[7], + in[8], in[9], in[10], in[11], in[12], in[13], in[14], in[15], + in[16], in[17], in[18], in[19], in[20], in[21], in[22], in[23], + in[24], in[25], in[26], in[27], in[28], in[29], in[30], in[31]); +endmodule + +/*module bigortest(); + reg[31:0] in; + wire out; + TheBigOR mine(out, in); + initial begin + $display(" in | Out "); + in = 5000; #1000 + $display(" %b | %b ", in, out); + in = 0; #1000 + $display(" %b | %b ", in, out); + end +endmodule*/ \ No newline at end of file diff --git a/alu.t.v b/alu.t.v index ce87d36..94107cd 100755 --- a/alu.t.v +++ b/alu.t.v @@ -1,70 +1,64 @@ `timescale 1 ns / 1 ps `include "alu.v" -`define opADD 3'd0 -`define opSUB 3'd1 -`define opXOR 3'd2 -`define opSLT 3'd3 -`define opAND 3'd4 -`define opNAND 3'd5 -`define opNOR 3'd6 -`define opOR 3'd7 - module ALUTestBench(); reg[2:0] command; reg[31:0] operandA; reg[31:0] operandB; - wire invertB; - wire flagger; - wire[2:0] muxindex; + wire[1:0] muxindex; wire[31:0] result; wire carryout; wire zero; wire overflow; - ALUcontrolLUT controller(muxindex, invertB, flagger, command); + //ALUcontrolLUT controller(muxindex, invertB, flagger, command); - ALU alu(result, carryout, zero, overflow, operandA, operandB, muxindex, invertB, flagger); + ALU alu(result, carryout, zero, overflow, operandA, operandB, command); initial begin $dumpfile("alu.vcd"); - $dumpvars(0, operandA, operandB, result, overflow, command, muxindex, invertB); + $dumpvars(0, operandA, operandB, result, overflow, command, muxindex); $display(" A | B | Com | Out "); operandA = -5358; //Set register a. operandB = 5369; //Set register b. command = 0; - #1000 //Delay. - $display(" %d | %d | %d | %d ", $signed(operandA), $signed(operandB), command, $signed(result)); + #10000 //Delay. + $display(" %b | %b | %b | %b | %b ", $signed(operandA), $signed(operandB), command, $signed(result), overflow); operandA = 552; //Set register a. operandB = 600; //Set register b. command = 1; - #1000 //Delay. - $display(" %d | %d | %d | %d ", $signed(operandA), $signed(operandB), command, $signed(result)); + #10000 //Delay. + $display(" %b | %b | %b | %b ", $signed(operandA), $signed(operandB), command, $signed(result)); operandA = 300; //Set register a. operandB = 25; //Set register b. command = 2; - #1000 //Delay. - $display(" %d | %d | %d | %d ", $signed(operandA), $signed(operandB), command, $signed(result)); + #10000 //Delay. + $display(" %b | %b | %b | %b ", $signed(operandA), $signed(operandB), command, $signed(result)); + operandA = 200; //Set register a. + operandB = 985; //Set register b. + command = 3; + #10000 //Delay. + $display(" %b | %b | %b | %b ", $signed(operandA), $signed(operandB), command, $signed(result)); operandA = 360; //Set register a. operandB = 111; //Set register b. command = 4; - #1000 //Delay. - $display(" %d | %d | %d | %d ", $signed(operandA), $signed(operandB), command, $signed(result)); + #10000 //Delay. + $display(" %b | %b | %b | %b ", $signed(operandA), $signed(operandB), command, $signed(result)); operandA = -2; //Set register a. operandB = -60694; //Set register b. command = 5; - #1000 //Delay. - $display(" %d | %d | %d | %d ", $signed(operandA), $signed(operandB), command, $signed(result)); + #10000 //Delay. + $display(" %b | %b | %b | %b ", $signed(operandA), $signed(operandB), command, $signed(result)); operandA = -2959; //Set register a. operandB = 6333; //Set register b. command = 6; - #1000 //Delay. - $display(" %d | %d | %d | %d ", $signed(operandA), $signed(operandB), command, $signed(result)); + #10000 //Delay. + $display(" %b | %b | %b | %b ", $signed(operandA), $signed(operandB), command, $signed(result)); operandA = -1045; //Set register a. operandB = 54968; //Set register b. command = 7; - #1000 //Delay. - $display(" %d | %d | %d | %d ", $signed(operandA), $signed(operandB), command, $signed(result)); + #10000 //Delay. + $display(" %b | %b | %b | %b ", $signed(operandA), $signed(operandB), command, $signed(result)); end endmodule diff --git a/alu.v b/alu.v index f856cef..9ecb71c 100755 --- a/alu.v +++ b/alu.v @@ -5,8 +5,18 @@ `define NAND nand #10 `define NOR nor #10 +`define opADD 3'd0 +`define opSUB 3'd1 +`define opXOR 3'd2 +`define opSLT 3'd3 +`define opAND 3'd4 +`define opNAND 3'd5 +`define opNOR 3'd6 +`define opOR 3'd7 + `include "multiplexer.v" `include "AddSub.v" +`include "TheBigOR.v" module BitSliceALU ( @@ -14,11 +24,11 @@ module BitSliceALU output Cout, input invertB, input Cin, - input[2:0] addr, + input[1:0] addr, input bit1, bit2 ); - wire Cout; - wire [7:0] out; + //wire Cout; + wire [3:0] out; structAddSub structadder(out[0], Cout, bit1, bit2, invertB, Cin); @@ -32,22 +42,13 @@ module BitSliceALU `NOR (nored, bit1, bit2); `XOR (out[3], invertB, nored); - //`XOR (out[2], bit1, bit2); - /*wire sum, Cout; - - structAddSub structadder(out[2], Cout, bit1, bit2, invertB, Cin); - - assign out[0] = bit1; - assign out[1] = bit2;*/ - //assign out[7:0] = 8'b0; - - structuralMultiplexer opmux(ALUout, addr, out); //Can potentially change the mux to be 4 input + Multiplexer2 opmux(ALUout, addr, out); //Can potentially change the mux to be 4 input endmodule module ALUcontrolLUT ( -output reg[2:0] muxindex, +output reg[1:0] muxindex, output reg invertB, output reg flagger, input[2:0] ALUcommand @@ -75,29 +76,49 @@ output zero, output overflow, input[31:0] operandA, input[31:0] operandB, -input[2:0] command, +input[2:0] command //input invertB, //input flagger ); //wire control2; - wire overflow; wire[31:0] Cout; - reg invertB; - reg flagger; - reg muxindex; + wire slt; + wire isSlt; + wire nSlt; + wire invertB; + wire flagger; + wire[1:0] muxindex; + wire muxidec; + wire[31:0] preresult; + //integer i = 0; //for the 0th bit slice, pass in invertB for Cin too (add one if subtracting) - BitSliceALU bit0(result[0], Cout[0], invertB, invertB, mux, operandA[0], operandB[0]); ALUcontrolLUT ctrl(muxindex, invertB, flagger, command); + BitSliceALU bit0(preresult[0], Cout[0], invertB, invertB, muxindex, operandA[0], operandB[0]); + genvar i; generate for (i = 1; i < 32; i = i+1) begin: ripple - BitSliceALU bit(result[i], Cout[i], invertB, Cout[i-1], mux, operandA[i], operandB[i]); + BitSliceALU bit(preresult[i], Cout[i], invertB, Cout[i-1], muxindex, operandA[i], operandB[i]); end endgenerate //BitSliceALU bit31(result[31], Cout[31], invertB, Cout[30], mux, operandA[31], operandB[31]); + `OR (carryout, 1'b0, Cout[31]); //set carryout + TheBigOR bigger(zero, preresult); //a bit wise OR on all bits of result, might not be allowed to do this + `XOR (overflow, Cout[31], Cout[30]); //set overflow + + bitMultiplexer sltSL(slt, overflow, {preresult[31], operandA[31]}); //compute is less than + `OR (muxidec, muxindex[0], muxindex[1]); + `NOR (isSlt, flagger, muxidec); + bitMultiplexer sltOut(result[0], isSlt, {preresult[0], slt}); - assign zero = ^result; //a bit wise OR on all bits of result, might not be allowed to do this - `XOR (overflow, Cout[31], Cout[30]); + `NOT (nSlt, isSlt); + genvar j; + generate + for (j = 1; j < 32; j = j + 1) + begin: SLTSet + `AND (result[j], nSlt, preresult[j]); + end + endgenerate endmodule diff --git a/alu.vcd b/alu.vcd index 340cbb2..990c2da 100644 --- a/alu.vcd +++ b/alu.vcd @@ -1,5 +1,5 @@ $date - Mon Oct 9 23:40:39 2017 + Tue Oct 10 23:17:11 2017 $end $version Icarus Verilog @@ -23,150 +23,234 @@ $scope module ALUTestBench $end $var reg 3 % command [2:0] $end $upscope $end $scope module ALUTestBench $end -$var wire 3 & muxindex [2:0] $end -$upscope $end -$scope module ALUTestBench $end -$var wire 1 ' invertB $end +$var wire 2 & muxindex [1:0] $end $upscope $end $enddefinitions $end #0 $dumpvars -0' -b0 & +bz & b0 % x$ bx # b1010011111001 " b11111111111111111110101100010010 ! $end -#160000 -bx1 # -#180000 -bx0xxx11 # -#200000 -bx0x1x11 # -#220000 -bx00x1011 # -#240000 -bx0001011 # -#260000 -bx00001011 # -#300000 -bx000001011 # -#340000 -bx0000001011 # -#380000 -bx00000001011 # -#420000 -bx000000001011 # -#460000 -bx0000000001011 # -#500000 -bx00000000001011 # -#540000 -bx000000000001011 # -#580000 -bx0000000000001011 # -#620000 -bx00000000000001011 # -#660000 -bx000000000000001011 # -#700000 -bx0000000000000001011 # -#740000 -bx00000000000000001011 # -#780000 -bx000000000000000001011 # -#820000 -bx0000000000000000001011 # -#860000 -bx00000000000000000001011 # -#900000 -bx000000000000000000001011 # -#940000 -bx0000000000000000000001011 # -#980000 -bx00000000000000000000001011 # -#1000000 -1' +#130000 +bx1x # +#150000 +bx0xxx1x # +#170000 +bx0x101x # +#190000 +bx00x101x # +#210000 +bx000101x # +#230000 +bx0000101x # +#270000 +bx00000101x # +#310000 +bx000000101x # +#350000 +bx0000000101x # +#390000 +bx00000000101x # +#430000 +bx000000000101x # +#470000 +bx0000000000101x # +#510000 +bx00000000000101x # +#550000 +bx000000000000101x # +#590000 +bx0000000000000101x # +#630000 +bx00000000000000101x # +#670000 +bx000000000000000101x # +#710000 +bx0000000000000000101x # +#750000 +bx00000000000000000101x # +#790000 +bx000000000000000000101x # +#830000 +bx0000000000000000000101x # +#870000 +bx00000000000000000000101x # +#910000 +bx000000000000000000000101x # +#950000 +bx0000000000000000000000101x # +#990000 +bx00000000000000000000000101x # +#1030000 +bx000000000000000000000000101x # +#1070000 +bx0000000000000000000000000101x # +#1110000 +bx00000000000000000000000000101x # +#1150000 +bx000000000000000000000000000101x # +#1160000 +0$ +#1190000 +b101x # +#1250000 +b1011 # +#10000000 b1 % b1001011000 " b1000101000 ! -#1020000 -bx000000000000000000000001011 # -#1060000 -bx0000000000000000000000001011 # -#1080000 +#10080000 +b1010 # +#10110000 +b11000 # +#10130000 +b1011100 # +#10150000 +b1001100 # +#10170000 +b11001000 # +#10210000 +b111000000 # +#10250000 +b1111010000 # +#10290000 +b11111010000 # +#10330000 +b111111010000 # +#10370000 +b1111111010000 # +#10410000 +b11111111010000 # +#10450000 +b111111111010000 # +#10490000 +b1111111111010000 # +#10530000 +b11111111111010000 # +#10570000 +b111111111111010000 # +#10610000 +b1111111111111010000 # +#10650000 +b11111111111111010000 # +#10690000 +b111111111111111010000 # +#10730000 +b1111111111111111010000 # +#10770000 +b11111111111111111010000 # +#10800000 +1$ +#10810000 +b111111111111111111010000 # +#10820000 0$ -#1100000 -bx00000000000000000000000001011 # -#1140000 -bx000000000000000000000000001011 # -#1160000 -bx111111111111111111111110010000 # -#1180000 -bx1111111111111111111111110100000 # -#1200000 -b10010100000 # -#1220000 -b10011000000 # -#1260000 -b10000000000 # -#1300000 -b10010000000 # -#2000000 -0' -b1 & +#10840000 +1$ +#10850000 +b1111111111111111111010000 # +#10860000 +0$ +#10880000 +1$ +#10890000 +b11111111111111111111010000 # +#10900000 +0$ +#10930000 +b111111111111111111111010000 # +#10960000 +1$ +#10970000 +b1111111111111111111111010000 # +#10980000 +0$ +#11000000 +1$ +#11010000 +b11111111111111111111111010000 # +#11020000 +0$ +#11050000 +b111111111111111111111111010000 # +#11060000 +1$ +#11090000 +b1111111111111111111111111010000 # +#11100000 +0$ +#11130000 +b11111111111111111111111111010000 # +#20000000 b10 % b11001 " b100101100 ! -#2120000 -b10011110000 # -#2130000 -b1110000 # -#2140000 -b100110101 # -#3000000 -1' -b11 & +#20040000 +b0 # +#20060000 +b11111111111111111111111111010000 # +#20070000 +b11111111111111111111111111110000 # +#20080000 +b101110000 # +#20090000 +b100110100 # +#30000000 +b11 % +b1111011001 " +b11001000 ! +#30060000 +b0 # +#30070000 +b1 # +#40000000 b100 % b1101111 " b101101000 ! -#3080000 -b11111111111111111111111111110111 # -#3140000 +#40060000 +b10010100001 # +#40070000 +b10010100000 # +#40080000 +b10000100000 # +#40090000 b1101000 # -#4000000 -0' +#40900000 +1$ +#40940000 +0$ +#50000000 b101 % b11111111111111110001001011101010 " b11111111111111111111111111111110 ! -#4140000 +#50080000 +b1101001 # +#50090000 b1110110100010101 # -#5000000 -b100 & +#60000000 b110 % b1100010111101 " b11111111111111111111010001110001 ! -#5040000 -bx111x11x1xxx1x1x1 # -#5050000 -bx # -#5120000 -b0x # -#5130000 -b1 # -#5150000 -b1100000010 # -#5660000 +#60080000 +b100000001 # +#60100000 +b1100000011 # +#60680000 1$ -#5680000 +#60700000 0$ -#6000000 -1' +#60770000 +b1100000010 # +#60790000 +b1100000011 # +#70000000 b111 % b1101011010111000 " b11111111111111111111101111101011 ! -#6140000 +#70090000 b11111111111111111111111111111011 # -#7000000 +#80000000 diff --git a/multiplexer.v b/multiplexer.v index b47730b..ec479e1 100644 --- a/multiplexer.v +++ b/multiplexer.v @@ -4,6 +4,8 @@ `define NOT not #10 `define NAND nand #10 `define NOR nor #10 +`define NAND3 nand #20 +`define NAND4 nand #30 module bitMultiplexer ( @@ -18,7 +20,26 @@ module bitMultiplexer `OR or_out(out, o0, o1); endmodule -module structuralMultiplexer +module Multiplexer2 +( + output out, + input [1:0] address, + input [3:0] in +); + wire nA0, nA1; + wire[3:0] preout; + `NOT A0inv(nA0, address[0]); + `NOT A1inv(nA1, address[1]); + `NAND3 AG0(preout[0], nA0, nA1, in[0]); + `NAND3 AG1(preout[1], address[0], nA1, in[1]); + `NAND3 AG2(preout[2], address[1], nA0, in[2]); + `NAND3 AG3(preout[3], address[0], address[1], in[3]); + `NAND4 AGT(out, preout[0], preout[1], preout[2], preout[3]); + +endmodule + + +module Multiplexer3 ( output out, input[2:0] address, From d18e77172dfc7db1b70a2f70aae3d6e3a8fe3efd Mon Sep 17 00:00:00 2001 From: juicyslew Date: Wed, 11 Oct 2017 16:30:29 -0400 Subject: [PATCH 06/11] SLT broke :( --- alu.t.v | 44 +++++++++++++++++++++++++++++++++++--------- alu.v | 20 +++++++++++++------- alu.vcd | 49 +++++++++++++++++++++++++++---------------------- 3 files changed, 75 insertions(+), 38 deletions(-) diff --git a/alu.t.v b/alu.t.v index 94107cd..257080f 100755 --- a/alu.t.v +++ b/alu.t.v @@ -5,6 +5,7 @@ module ALUTestBench(); reg[2:0] command; reg[31:0] operandA; reg[31:0] operandB; + reg[31:0] expected; wire[1:0] muxindex; wire[31:0] result; wire carryout; @@ -19,46 +20,71 @@ module ALUTestBench(); $dumpfile("alu.vcd"); $dumpvars(0, operandA, operandB, result, overflow, command, muxindex); - $display(" A | B | Com | Out "); + $display(" A | B | Com | Out | Exp "); operandA = -5358; //Set register a. operandB = 5369; //Set register b. command = 0; + expected = 11; #10000 //Delay. - $display(" %b | %b | %b | %b | %b ", $signed(operandA), $signed(operandB), command, $signed(result), overflow); + $display(" %d | %d | %d | %d | %d ", $signed(operandA), $signed(operandB), command, $signed(result), $signed(expected)); operandA = 552; //Set register a. operandB = 600; //Set register b. command = 1; + expected = -48; #10000 //Delay. - $display(" %b | %b | %b | %b ", $signed(operandA), $signed(operandB), command, $signed(result)); + $display(" %d | %d | %d | %d | %d ", $signed(operandA), $signed(operandB), command, $signed(result), $signed(expected)); operandA = 300; //Set register a. operandB = 25; //Set register b. command = 2; + expected = 32'b100110101; #10000 //Delay. - $display(" %b | %b | %b | %b ", $signed(operandA), $signed(operandB), command, $signed(result)); + $display(" %d | %d | %d | %d | %d ", $signed(operandA), $signed(operandB), command, $signed(result), $signed(expected)); operandA = 200; //Set register a. operandB = 985; //Set register b. command = 3; + expected = 1; #10000 //Delay. - $display(" %b | %b | %b | %b ", $signed(operandA), $signed(operandB), command, $signed(result)); + $display(" %d | %d | %d | %d | %d ", $signed(operandA), $signed(operandB), command, $signed(result), $signed(expected)); operandA = 360; //Set register a. operandB = 111; //Set register b. command = 4; + expected = 32'b001101000; #10000 //Delay. - $display(" %b | %b | %b | %b ", $signed(operandA), $signed(operandB), command, $signed(result)); + $display(" %d | %d | %d | %d | %d ", $signed(operandA), $signed(operandB), command, $signed(result), $signed(expected)); operandA = -2; //Set register a. operandB = -60694; //Set register b. command = 5; + expected = 32'b00000000000000001110110100010101; #10000 //Delay. - $display(" %b | %b | %b | %b ", $signed(operandA), $signed(operandB), command, $signed(result)); + $display(" %d | %d | %d | %d | %d ", $signed(operandA), $signed(operandB), command, $signed(result), $signed(expected)); operandA = -2959; //Set register a. operandB = 6333; //Set register b. command = 6; + expected = 32'b00000000000000000000001100000010; + //11111111111111111111010001110001 + //00000000000000000001100010111101 #10000 //Delay. - $display(" %b | %b | %b | %b ", $signed(operandA), $signed(operandB), command, $signed(result)); + $display(" %d | %d | %d | %d | %d ", $signed(operandA), $signed(operandB), command, $signed(result), $signed(expected)); operandA = -1045; //Set register a. operandB = 54968; //Set register b. command = 7; + expected = 32'b11111111111111111111111111111011; + //11111111111111111111101111101011 + //00000000000000001101011010111000 #10000 //Delay. - $display(" %b | %b | %b | %b ", $signed(operandA), $signed(operandB), command, $signed(result)); + $display(" %d | %d | %d | %d | %d ", $signed(operandA), $signed(operandB), command, $signed(result), $signed(expected)); + operandA = 9050; //Set register a. + operandB = 985; //Set register b. + command = 3; + expected = 0; + #10000 //Delay. + $display(" %d | %d | %d | %d | %d ", $signed(operandA), $signed(operandB), command, $signed(result), $signed(expected)); + operandA = -10505; //Set register a. + operandB = 2; //Set register b. + command = 3; + expected = 1; + #10000 //Delay. + $display(" %d | %d | %d | %d | %d ", $signed(operandA), $signed(operandB), command, $signed(result), $signed(expected)); + end endmodule diff --git a/alu.v b/alu.v index 9ecb71c..231d1e0 100755 --- a/alu.v +++ b/alu.v @@ -85,17 +85,19 @@ input[2:0] command wire slt; wire isSlt; wire nSlt; - wire invertB; - wire flagger; + wire invertB; + wire flagger; wire[1:0] muxindex; wire muxidec; wire[31:0] preresult; + wire preflow; + wire prezero; //integer i = 0; //for the 0th bit slice, pass in invertB for Cin too (add one if subtracting) ALUcontrolLUT ctrl(muxindex, invertB, flagger, command); BitSliceALU bit0(preresult[0], Cout[0], invertB, invertB, muxindex, operandA[0], operandB[0]); - + genvar i; generate for (i = 1; i < 32; i = i+1) @@ -104,14 +106,18 @@ input[2:0] command end endgenerate //BitSliceALU bit31(result[31], Cout[31], invertB, Cout[30], mux, operandA[31], operandB[31]); - `OR (carryout, 1'b0, Cout[31]); //set carryout - TheBigOR bigger(zero, preresult); //a bit wise OR on all bits of result, might not be allowed to do this - `XOR (overflow, Cout[31], Cout[30]); //set overflow + TheBigOR bigger(prezero, preresult); //a bit wise OR on all bits of result, might not be allowed to do this + `XOR (preflow, Cout[31], Cout[30]); //determine overflow + + `AND (zero, flagger, prezero); //set zero if flagger + `AND (carryout, flagger, Cout[31]); //set carryout if flagger + `AND (overflow, flagger, preflow); //set overflow if flagger - bitMultiplexer sltSL(slt, overflow, {preresult[31], operandA[31]}); //compute is less than + bitMultiplexer sltSL(slt, preflow, {preresult[31], operandA[31]}); //compute is less than `OR (muxidec, muxindex[0], muxindex[1]); `NOR (isSlt, flagger, muxidec); bitMultiplexer sltOut(result[0], isSlt, {preresult[0], slt}); + //`OR(result[0], preresult[0], 1'b0); `NOT (nSlt, isSlt); genvar j; diff --git a/alu.vcd b/alu.vcd index 990c2da..e1a8cf5 100644 --- a/alu.vcd +++ b/alu.vcd @@ -1,5 +1,5 @@ $date - Tue Oct 10 23:17:11 2017 + Wed Oct 11 16:26:57 2017 $end $version Icarus Verilog @@ -93,7 +93,7 @@ bx0000000000000000000000000101x # bx00000000000000000000000000101x # #1150000 bx000000000000000000000000000101x # -#1160000 +#1180000 0$ #1190000 b101x # @@ -143,45 +143,45 @@ b111111111111111010000 # b1111111111111111010000 # #10770000 b11111111111111111010000 # -#10800000 -1$ #10810000 b111111111111111111010000 # #10820000 -0$ -#10840000 1$ +#10840000 +0$ #10850000 b1111111111111111111010000 # #10860000 -0$ -#10880000 1$ +#10880000 +0$ #10890000 b11111111111111111111010000 # #10900000 +1$ +#10920000 0$ #10930000 b111111111111111111111010000 # -#10960000 -1$ #10970000 b1111111111111111111111010000 # #10980000 -0$ -#11000000 1$ +#11000000 +0$ #11010000 b11111111111111111111111010000 # #11020000 +1$ +#11040000 0$ #11050000 b111111111111111111111111010000 # -#11060000 +#11080000 1$ #11090000 b1111111111111111111111111010000 # -#11100000 +#11120000 0$ #11130000 b11111111111111111111111111010000 # @@ -219,10 +219,6 @@ b10010100000 # b10000100000 # #40090000 b1101000 # -#40900000 -1$ -#40940000 -0$ #50000000 b101 % b11111111111111110001001011101010 " @@ -239,10 +235,6 @@ b11111111111111111111010001110001 ! b100000001 # #60100000 b1100000011 # -#60680000 -1$ -#60700000 -0$ #60770000 b1100000010 # #60790000 @@ -254,3 +246,16 @@ b11111111111111111111101111101011 ! #70090000 b11111111111111111111111111111011 # #80000000 +b11 % +b1111011001 " +b10001101011010 ! +#80060000 +b1 # +#80090000 +b0 # +#80130000 +b1 # +#90000000 +b10 " +b11111111111111111101011011110111 ! +#100000000 From 01d5df9673735519d8a394721645cbc4a349d709 Mon Sep 17 00:00:00 2001 From: juicyslew Date: Wed, 11 Oct 2017 19:49:39 -0400 Subject: [PATCH 07/11] IT WORKS, IT'S ALIVE --- alu.t.v | 58 ++++++++++-- alu.v | 12 ++- alu.vcd | 277 ++++++++++++++++++++++++++++++++++++++++++++------------ 3 files changed, 277 insertions(+), 70 deletions(-) diff --git a/alu.t.v b/alu.t.v index 257080f..35d7889 100755 --- a/alu.t.v +++ b/alu.t.v @@ -6,7 +6,6 @@ module ALUTestBench(); reg[31:0] operandA; reg[31:0] operandB; reg[31:0] expected; - wire[1:0] muxindex; wire[31:0] result; wire carryout; wire zero; @@ -18,7 +17,7 @@ module ALUTestBench(); initial begin $dumpfile("alu.vcd"); - $dumpvars(0, operandA, operandB, result, overflow, command, muxindex); + $dumpvars(0, operandA, operandB, result, overflow, zero, carryout, command, expected); $display(" A | B | Com | Out | Exp "); operandA = -5358; //Set register a. @@ -44,7 +43,7 @@ module ALUTestBench(); command = 3; expected = 1; #10000 //Delay. - $display(" %d | %d | %d | %d | %d ", $signed(operandA), $signed(operandB), command, $signed(result), $signed(expected)); + $display(" %d | %d | %d | %d | %d | %b | %b ", $signed(operandA), $signed(operandB), command, $signed(result), $signed(expected), overflow, zero); operandA = 360; //Set register a. operandB = 111; //Set register b. command = 4; @@ -78,13 +77,60 @@ module ALUTestBench(); command = 3; expected = 0; #10000 //Delay. - $display(" %d | %d | %d | %d | %d ", $signed(operandA), $signed(operandB), command, $signed(result), $signed(expected)); + $display(" %d | %d | %d | %d | %d | %b | %b ", $signed(operandA), $signed(operandB), command, $signed(result), $signed(expected), overflow, zero); operandA = -10505; //Set register a. operandB = 2; //Set register b. command = 3; expected = 1; #10000 //Delay. - $display(" %d | %d | %d | %d | %d ", $signed(operandA), $signed(operandB), command, $signed(result), $signed(expected)); - + $display(" %d | %d | %d | %d | %d | %b | %b ", $signed(operandA), $signed(operandB), command, $signed(result), $signed(expected), overflow, zero); + operandA = 1; //Set register a. + operandB = 2; //Set register b. + command = 3; + expected = 1; + #10000 //Delay. + $display(" %d | %d | %d | %d | %d | %b | %b ", $signed(operandA), $signed(operandB), command, $signed(result), $signed(expected), overflow, zero); + operandA = 1; //Set register a. + operandB = 2; //Set register b. + command = 1; + expected = -1; + #10000 //Delay. + $display(" %d | %d | %d | %d | %d | %b | %b ", $signed(operandA), $signed(operandB), command, $signed(result), $signed(expected), overflow, zero); + operandA = -1; //Set register a. + operandB = 2; //Set register b. + command = 3; + expected = 1; + #10000 //Delay. + $display(" %d | %d | %d | %d | %d | %b | %b ", $signed(operandA), $signed(operandB), command, $signed(result), $signed(expected), overflow, zero); + operandA = -1; //Set register a. + operandB = 2; //Set register b. + command = 1; + expected = -3; + #10000 //Delay. + $display(" %d | %d | %d | %d | %d | %b | %b ", $signed(operandA), $signed(operandB), command, $signed(result), $signed(expected), overflow, zero); + operandA = 1; //Set register a. + operandB = -2; //Set register b. + command = 3; + expected = 0; + #10000 //Delay. + $display(" %d | %d | %d | %d | %d | %b | %b ", $signed(operandA), $signed(operandB), command, $signed(result), $signed(expected), overflow, zero); + operandA = 1; //Set register a. + operandB = -2; //Set register b. + command = 1; + expected = 3; + #10000 //Delay. + $display(" %d | %d | %d | %d | %d | %b | %b ", $signed(operandA), $signed(operandB), command, $signed(result), $signed(expected), overflow, zero); + operandA = -3; //Set register a. + operandB = -2; //Set register b. + command = 3; + expected = 1; + #10000 //Delay. + $display(" %d | %d | %d | %d | %d | %b | %b ", $signed(operandA), $signed(operandB), command, $signed(result), $signed(expected), overflow, zero); + operandA = -3; //Set register a. + operandB = -2; //Set register b. + command = 1; + expected = -1; + #10000 //Delay. + $display(" %d | %d | %d | %d | %d | %b | %b ", $signed(operandA), $signed(operandB), command, $signed(result), $signed(expected), overflow, zero); end endmodule diff --git a/alu.v b/alu.v index 231d1e0..535c795 100755 --- a/alu.v +++ b/alu.v @@ -59,7 +59,7 @@ input[2:0] ALUcommand `opADD: begin muxindex = 0; invertB=0; flagger = 1; end `opSUB: begin muxindex = 0; invertB=1; flagger = 1; end `opXOR: begin muxindex = 1; invertB=0; flagger = 0; end - `opSLT: begin muxindex = 0; invertB=0; flagger = 0; end + `opSLT: begin muxindex = 0; invertB=1; flagger = 0; end `opAND: begin muxindex = 2; invertB=1; flagger = 0; end `opNAND: begin muxindex = 2; invertB=0; flagger = 0; end `opNOR: begin muxindex = 3; invertB=0; flagger = 0; end @@ -92,6 +92,7 @@ input[2:0] command wire[31:0] preresult; wire preflow; wire prezero; + wire nzero; //integer i = 0; //for the 0th bit slice, pass in invertB for Cin too (add one if subtracting) @@ -106,18 +107,19 @@ input[2:0] command end endgenerate //BitSliceALU bit31(result[31], Cout[31], invertB, Cout[30], mux, operandA[31], operandB[31]); - TheBigOR bigger(prezero, preresult); //a bit wise OR on all bits of result, might not be allowed to do this + TheBigOR bigger(nzero, preresult); //a bit wise OR on all bits of result, might not be allowed to do this `XOR (preflow, Cout[31], Cout[30]); //determine overflow + `NOT (prezero, nzero); `AND (zero, flagger, prezero); //set zero if flagger `AND (carryout, flagger, Cout[31]); //set carryout if flagger `AND (overflow, flagger, preflow); //set overflow if flagger + //`OR(overflow, preflow, 1'b0); - bitMultiplexer sltSL(slt, preflow, {preresult[31], operandA[31]}); //compute is less than + bitMultiplexer sltSL(slt, preflow, {operandA[31], preresult[31]}); //compute is less than `OR (muxidec, muxindex[0], muxindex[1]); `NOR (isSlt, flagger, muxidec); - bitMultiplexer sltOut(result[0], isSlt, {preresult[0], slt}); - //`OR(result[0], preresult[0], 1'b0); + bitMultiplexer sltOut(result[0], isSlt, {slt, preresult[0]}); `NOT (nSlt, isSlt); genvar j; diff --git a/alu.vcd b/alu.vcd index e1a8cf5..a35fc9c 100644 --- a/alu.vcd +++ b/alu.vcd @@ -1,5 +1,5 @@ $date - Wed Oct 11 16:26:57 2017 + Wed Oct 11 19:43:16 2017 $end $version Icarus Verilog @@ -20,16 +20,24 @@ $scope module ALUTestBench $end $var wire 1 $ overflow $end $upscope $end $scope module ALUTestBench $end -$var reg 3 % command [2:0] $end +$var wire 1 % zero $end $upscope $end $scope module ALUTestBench $end -$var wire 2 & muxindex [1:0] $end +$var wire 1 & carryout $end +$upscope $end +$scope module ALUTestBench $end +$var reg 3 ' command [2:0] $end +$upscope $end +$scope module ALUTestBench $end +$var reg 32 ( expected [31:0] $end $upscope $end $enddefinitions $end #0 $dumpvars -bz & -b0 % +b1011 ( +b0 ' +x& +x% x$ bx # b1010011111001 " @@ -38,114 +46,190 @@ $end #130000 bx1x # #150000 -bx0xxx1x # +bx0xxx11 # #170000 -bx0x101x # +bx0x1011 # #190000 -bx00x101x # +bx00x1011 # #210000 -bx000101x # +bx0001011 # #230000 -bx0000101x # +bx00001011 # #270000 -bx00000101x # +bx000001011 # #310000 -bx000000101x # +bx0000001011 # #350000 -bx0000000101x # +bx00000001011 # #390000 -bx00000000101x # +bx000000001011 # #430000 -bx000000000101x # +bx0000000001011 # +#460000 +0% #470000 -bx0000000000101x # +bx00000000001011 # #510000 -bx00000000000101x # +bx000000000001011 # #550000 -bx000000000000101x # +bx0000000000001011 # #590000 -bx0000000000000101x # +bx00000000000001011 # #630000 -bx00000000000000101x # +bx000000000000001011 # #670000 -bx000000000000000101x # +bx0000000000000001011 # #710000 -bx0000000000000000101x # +bx00000000000000001011 # #750000 -bx00000000000000000101x # +bx000000000000000001011 # #790000 -bx000000000000000000101x # +bx0000000000000000001011 # #830000 -bx0000000000000000000101x # +bx00000000000000000001011 # #870000 -bx00000000000000000000101x # +bx000000000000000000001011 # #910000 -bx000000000000000000000101x # +bx0000000000000000000001011 # #950000 -bx0000000000000000000000101x # +bx00000000000000000000001011 # #990000 -bx00000000000000000000000101x # +bx000000000000000000000001011 # #1030000 -bx000000000000000000000000101x # +bx0000000000000000000000001011 # #1070000 -bx0000000000000000000000000101x # +bx00000000000000000000000001011 # #1110000 -bx00000000000000000000000000101x # +bx000000000000000000000000001011 # #1150000 -bx000000000000000000000000000101x # +bx0000000000000000000000000001011 # +#1160000 +1& #1180000 0$ #1190000 -b101x # -#1250000 b1011 # #10000000 -b1 % +b11111111111111111111111111010000 ( +b1 ' b1001011000 " b1000101000 ! #10080000 -b1010 # +0& +#10100000 +1& #10110000 b11000 # +#10120000 +0& #10130000 b1011100 # +#10140000 +1& #10150000 b1001100 # +#10160000 +0& #10170000 b11001000 # +#10180000 +1& +#10200000 +0& #10210000 b111000000 # +#10220000 +1& +#10240000 +0& #10250000 b1111010000 # +#10260000 +1& +#10280000 +0& #10290000 b11111010000 # +#10300000 +1& +#10320000 +0& #10330000 b111111010000 # +#10340000 +1& +#10360000 +0& #10370000 b1111111010000 # +#10380000 +1& +#10400000 +0& #10410000 b11111111010000 # +#10420000 +1& +#10440000 +0& #10450000 b111111111010000 # +#10460000 +1& +#10480000 +0& #10490000 b1111111111010000 # +#10500000 +1& +#10520000 +0& #10530000 b11111111111010000 # +#10540000 +1& +#10560000 +0& #10570000 b111111111111010000 # +#10580000 +1& +#10600000 +0& #10610000 b1111111111111010000 # +#10620000 +1& +#10640000 +0& #10650000 b11111111111111010000 # +#10660000 +1& +#10680000 +0& #10690000 b111111111111111010000 # +#10700000 +1& +#10720000 +0& #10730000 b1111111111111111010000 # +#10740000 +1& +#10760000 +0& #10770000 b11111111111111111010000 # +#10780000 +1& +#10800000 +0& #10810000 b111111111111111111010000 # #10820000 +1& 1$ #10840000 0$ @@ -154,10 +238,12 @@ b1111111111111111111010000 # #10860000 1$ #10880000 +0& 0$ #10890000 b11111111111111111111010000 # #10900000 +1& 1$ #10920000 0$ @@ -168,10 +254,12 @@ b1111111111111111111111010000 # #10980000 1$ #11000000 +0& 0$ #11010000 b11111111111111111111111010000 # #11020000 +1& 1$ #11040000 0$ @@ -181,81 +269,152 @@ b111111111111111111111111010000 # 1$ #11090000 b1111111111111111111111111010000 # +#11100000 +0& #11120000 0$ #11130000 b11111111111111111111111111010000 # #20000000 -b10 % +b100110101 ( +b10 ' b11001 " b100101100 ! #20040000 b0 # +#20050000 +b1 # #20060000 -b11111111111111111111111111010000 # +b11111111111111111111111111010001 # #20070000 b11111111111111111111111111110000 # #20080000 b101110000 # #20090000 b100110100 # +#20110000 +b100110101 # #30000000 -b11 % +b1 ( +b11 ' b1111011001 " b11001000 ! #30060000 +b1 # +#30080000 b0 # -#30070000 +#30190000 b1 # #40000000 -b100 % +b1101000 ( +b100 ' b1101111 " b101101000 ! #40060000 -b10010100001 # -#40070000 -b10010100000 # +b11111111111111111111110011101111 # #40080000 -b10000100000 # -#40090000 +b11101001 # +#40100000 b1101000 # #50000000 -b101 % +b1110110100010101 ( +b101 ' b11111111111111110001001011101010 " b11111111111111111111111111111110 ! -#50080000 -b1101001 # #50090000 +b1110110100010100 # +#50110000 b1110110100010101 # #60000000 -b110 % +b1100000010 ( +b110 ' b1100010111101 " b11111111111111111111010001110001 ! #60080000 b100000001 # #60100000 b1100000011 # -#60770000 +#60120000 b1100000010 # -#60790000 -b1100000011 # #70000000 -b111 % +b11111111111111111111111111111011 ( +b111 ' b1101011010111000 " b11111111111111111111101111101011 ! #70090000 +b11111111111111111111111111111010 # +#70110000 b11111111111111111111111111111011 # #80000000 -b11 % +b0 ( +b11 ' b1111011001 " b10001101011010 ! #80060000 b1 # -#80090000 +#80750000 b0 # -#80130000 -b1 # #90000000 +b1 ( b10 " b11111111111111111101011011110111 ! +#90170000 +b1 # #100000000 +b1 ! +#100830000 +b0 # +#101370000 +b1 # +#110000000 +b11111111111111111111111111111111 ( +b1 ' +#110040000 +b11111111111111111111111111111111 # +#120000000 +b1 ( +b11 ' +b11111111111111111111111111111111 ! +#120040000 +b1 # +#130000000 +b11111111111111111111111111111101 ( +b1 ' +#130020000 +1& +#130040000 +b11111111111111111111111111111101 # +#140000000 +b0 ( +b11 ' +b11111111111111111111111111111110 " +b1 ! +#140020000 +0& +#140040000 +b1 # +#140170000 +b0 # +#150000000 +b11 ( +b1 ' +#150040000 +b10 # +#150060000 +b11 # +#160000000 +b1 ( +b11 ' +b11111111111111111111111111111101 ! +#160040000 +b1 # +#160060000 +b0 # +#160170000 +b1 # +#170000000 +b11111111111111111111111111111111 ( +b1 ' +#170040000 +b11111111111111111111111111111111 # +#180000000 From c5964a5f3949dd0dbc1e691d7daaeca145eac936 Mon Sep 17 00:00:00 2001 From: Xiaozheng Xu Date: Wed, 11 Oct 2017 23:18:44 -0400 Subject: [PATCH 08/11] adding some comments --- alu.t.v | 2 +- alu.v | 14 +++++++------- alu.vcd | 2 +- 3 files changed, 9 insertions(+), 9 deletions(-) diff --git a/alu.t.v b/alu.t.v index 35d7889..d05e01c 100755 --- a/alu.t.v +++ b/alu.t.v @@ -19,7 +19,7 @@ module ALUTestBench(); $dumpfile("alu.vcd"); $dumpvars(0, operandA, operandB, result, overflow, zero, carryout, command, expected); - $display(" A | B | Com | Out | Exp "); + $display(" A | B | Com | Out | Exp | Overflow | Zero"); operandA = -5358; //Set register a. operandB = 5369; //Set register b. command = 0; diff --git a/alu.v b/alu.v index 535c795..9eab42e 100755 --- a/alu.v +++ b/alu.v @@ -91,7 +91,6 @@ input[2:0] command wire muxidec; wire[31:0] preresult; wire preflow; - wire prezero; wire nzero; //integer i = 0; @@ -110,23 +109,24 @@ input[2:0] command TheBigOR bigger(nzero, preresult); //a bit wise OR on all bits of result, might not be allowed to do this `XOR (preflow, Cout[31], Cout[30]); //determine overflow - `NOT (prezero, nzero); - `AND (zero, flagger, prezero); //set zero if flagger + `NOT (zero, nzero); //set zero for each operation `AND (carryout, flagger, Cout[31]); //set carryout if flagger `AND (overflow, flagger, preflow); //set overflow if flagger //`OR(overflow, preflow, 1'b0); + //Set SLT if the mux command is 3 bitMultiplexer sltSL(slt, preflow, {operandA[31], preresult[31]}); //compute is less than - `OR (muxidec, muxindex[0], muxindex[1]); - `NOR (isSlt, flagger, muxidec); - bitMultiplexer sltOut(result[0], isSlt, {slt, preresult[0]}); + `OR (muxidec, muxindex[0], muxindex[1]); //test if muxindex is 0 + `NOR (isSlt, flagger, muxidec); //test if muxindex and flagger is zero, in which case it is SLT + bitMultiplexer sltOut(result[0], isSlt, {slt, preresult[0]}); //Set the first bit to be SLT value + //Change the rest of the bits to 0 if SLT `NOT (nSlt, isSlt); genvar j; generate for (j = 1; j < 32; j = j + 1) begin: SLTSet - `AND (result[j], nSlt, preresult[j]); + `AND (result[j], nSlt, preresult[j]); //This and operation changes the bit to 0 if nSlt is false, and keeps the result otherwise. end endgenerate endmodule diff --git a/alu.vcd b/alu.vcd index a35fc9c..d0870d0 100644 --- a/alu.vcd +++ b/alu.vcd @@ -1,5 +1,5 @@ $date - Wed Oct 11 19:43:16 2017 + Wed Oct 11 23:03:50 2017 $end $version Icarus Verilog From fad2d4c9115d2f486ce91477a5353c04c76958a1 Mon Sep 17 00:00:00 2001 From: Xiaozheng Xu Date: Thu, 12 Oct 2017 22:07:36 -0400 Subject: [PATCH 09/11] Writing a first version of automated testing, half working. --- alu.t.v | 68 ++++++++++++++++++++++++++++++++++++++++----------- alu.v | 2 +- multiplexer.v | 32 ++++++++++++------------ 3 files changed, 71 insertions(+), 31 deletions(-) diff --git a/alu.t.v b/alu.t.v index d05e01c..fdcfb5a 100755 --- a/alu.t.v +++ b/alu.t.v @@ -11,25 +11,63 @@ module ALUTestBench(); wire zero; wire overflow; + integer OperandAs[1:6]; + integer OperandBs[1:6]; + integer addresults[1:6]; + integer a; + + integer notpassed = 0; + //ALUcontrolLUT controller(muxindex, invertB, flagger, command); ALU alu(result, carryout, zero, overflow, operandA, operandB, command); - initial begin - $dumpfile("alu.vcd"); - $dumpvars(0, operandA, operandB, result, overflow, zero, carryout, command, expected); - + // initial begin + // $dumpfile("alu.vcd"); + // $dumpvars(0, operandA, operandB, result, overflow, zero, carryout, command, expected); + // end + initial begin $display(" A | B | Com | Out | Exp | Overflow | Zero"); - operandA = -5358; //Set register a. - operandB = 5369; //Set register b. + //Test the Add operation: command = 0; - expected = 11; - #10000 //Delay. - $display(" %d | %d | %d | %d | %d ", $signed(operandA), $signed(operandB), command, $signed(result), $signed(expected)); - operandA = 552; //Set register a. - operandB = 600; //Set register b. + OperandAs[1] = -5358; OperandAs[2] = 0; OperandAs[3] = -35; + OperandBs[1] = 5369; OperandBs[2] = 0; OperandBs[3] = -65; + addresults[1]= 11; addresults[2]= 0 ; addresults[3]= -100; + OperandAs[4] = 730; OperandAs[5] = 4294967210; OperandAs[6] = -4294961800; + OperandBs[4] = -520; OperandBs[5] = 300; OperandBs[6] = -30000; + addresults[4]= 210 ; addresults[5]= 0; addresults[6]= 0; + for (a = 1; a < 7; a = a + 1) + #10000 //Delay + begin: addtest + operandA = OperandAs[a]; + operandB = OperandBs[a]; + #10000 //Delay + if((result != addresults[a]) && (overflow != 1)) begin + notpassed = notpassed + 1; // Add to test not passed + $display("Test Case adding %d to %d Failed with result %d and overflow %d", operandA, operandB, result, overflow); + end + end + + //Test the Subtract operation command = 1; - expected = -48; + OperandAs[1] = -5358; OperandAs[2] = 0; OperandAs[3] = -35; + OperandAs[4] = 730; OperandAs[5] = 4294967210; OperandAs[6] = -4294961800; + OperandBs[1] = 5369; OperandBs[2] = 0; OperandBs[3] = -65; + OperandBs[4] = -520; OperandBs[5] = 300; OperandBs[6] = -30000; + addresults[1]= 11; addresults[2]= 0 ; addresults[3]= -100; + addresults[4]= 210 ; addresults[5]= 0; addresults[6]= 0; + for (a = 1; a < 7; a = a + 1) + #10000 + begin: subtracttest + operandA = OperandAs[a]; + operandB = OperandBs[a]; + #10000 + if((result != addresults[a]) && (overflow != 1)) begin + notpassed = notpassed + 1; // Add to test not passed + $display("Test Case subtracting %d - %d Failed", operandA, operandB); + end + end + #10000 //Delay. $display(" %d | %d | %d | %d | %d ", $signed(operandA), $signed(operandB), command, $signed(result), $signed(expected)); operandA = 300; //Set register a. @@ -131,6 +169,8 @@ module ALUTestBench(); command = 1; expected = -1; #10000 //Delay. - $display(" %d | %d | %d | %d | %d | %b | %b ", $signed(operandA), $signed(operandB), command, $signed(result), $signed(expected), overflow, zero); - end + //$display(" %d | %d | %d | %d | %d | %b | %b ", $signed(operandA), $signed(operandB), command, $signed(result), $signed(expected), overflow, zero); + + $display("Number of test failed %d", notpassed); +end endmodule diff --git a/alu.v b/alu.v index 9eab42e..bc9741b 100755 --- a/alu.v +++ b/alu.v @@ -102,7 +102,7 @@ input[2:0] command generate for (i = 1; i < 32; i = i+1) begin: ripple - BitSliceALU bit(preresult[i], Cout[i], invertB, Cout[i-1], muxindex, operandA[i], operandB[i]); + BitSliceALU bitany(preresult[i], Cout[i], invertB, Cout[i-1], muxindex, operandA[i], operandB[i]); end endgenerate //BitSliceALU bit31(result[31], Cout[31], invertB, Cout[30], mux, operandA[31], operandB[31]); diff --git a/multiplexer.v b/multiplexer.v index ec479e1..590d204 100644 --- a/multiplexer.v +++ b/multiplexer.v @@ -39,19 +39,19 @@ module Multiplexer2 endmodule -module Multiplexer3 -( - output out, - input[2:0] address, - input[7:0] in -); - wire[3:0] mux; - wire[1:0] muxmid; - bitMultiplexer mux_0(mux[0], address[0], in[1:0]); - bitMultiplexer mux_1(mux[1], address[0], in[3:2]); - bitMultiplexer mux_2(mux[2], address[0], in[5:4]); - bitMultiplexer mux_3(mux[3], address[0], in[7:6]); - bitMultiplexer mux_mid_0(muxmid[0], address[1], mux[1:0]); - bitMultiplexer mux_mid_1(muxmid[1], address[1], mux[3:2]); - bitMultiplexer mux_out(out, address[2], muxmid[1:0]); -endmodule +// module Multiplexer3 +// ( +// output out, +// input[2:0] address, +// input[7:0] in +// ); +// wire[3:0] mux; +// wire[1:0] muxmid; +// bitMultiplexer mux_0(mux[0], address[0], in[1:0]); +// bitMultiplexer mux_1(mux[1], address[0], in[3:2]); +// bitMultiplexer mux_2(mux[2], address[0], in[5:4]); +// bitMultiplexer mux_3(mux[3], address[0], in[7:6]); +// bitMultiplexer mux_mid_0(muxmid[0], address[1], mux[1:0]); +// bitMultiplexer mux_mid_1(muxmid[1], address[1], mux[3:2]); +// bitMultiplexer mux_out(out, address[2], muxmid[1:0]); +// endmodule From 6d72fab90bf55cea95ec1f2171aeb77d80c71209 Mon Sep 17 00:00:00 2001 From: Xiaozheng Xu Date: Fri, 13 Oct 2017 00:28:23 -0400 Subject: [PATCH 10/11] Final, working code and complete testing that's automated. Perhaps more comments can be added and code cleaned up more. --- alu.t.v | 313 ++++++++----- alu.v | 14 +- alu.vcd | 1344 +++++++++++++++++++++++++++++++++++++++++++++---------- 3 files changed, 1303 insertions(+), 368 deletions(-) diff --git a/alu.t.v b/alu.t.v index fdcfb5a..f27fe35 100755 --- a/alu.t.v +++ b/alu.t.v @@ -5,172 +5,241 @@ module ALUTestBench(); reg[2:0] command; reg[31:0] operandA; reg[31:0] operandB; - reg[31:0] expected; wire[31:0] result; wire carryout; wire zero; wire overflow; - integer OperandAs[1:6]; - integer OperandBs[1:6]; - integer addresults[1:6]; + integer OperandAs[1:12]; + integer OperandBs[1:12]; + integer results[1:12]; integer a; integer notpassed = 0; + integer totaltests = 0; //ALUcontrolLUT controller(muxindex, invertB, flagger, command); ALU alu(result, carryout, zero, overflow, operandA, operandB, command); - // initial begin - // $dumpfile("alu.vcd"); - // $dumpvars(0, operandA, operandB, result, overflow, zero, carryout, command, expected); - // end initial begin - $display(" A | B | Com | Out | Exp | Overflow | Zero"); - //Test the Add operation: + $dumpfile("alu.vcd"); + $dumpvars(0, operandA, operandB, result, overflow, zero, carryout, command); + + //$display(" A | B | Com | Out | Exp | Overflow | Zero"); + //Test Add operation: command = 0; OperandAs[1] = -5358; OperandAs[2] = 0; OperandAs[3] = -35; OperandBs[1] = 5369; OperandBs[2] = 0; OperandBs[3] = -65; - addresults[1]= 11; addresults[2]= 0 ; addresults[3]= -100; - OperandAs[4] = 730; OperandAs[5] = 4294967210; OperandAs[6] = -4294961800; - OperandBs[4] = -520; OperandBs[5] = 300; OperandBs[6] = -30000; - addresults[4]= 210 ; addresults[5]= 0; addresults[6]= 0; + results[1]= 11; results[2]= 0 ; results[3]= -100; + OperandAs[4] = 730; OperandAs[5] = 2147483448; OperandAs[6] = -2147483248; + OperandBs[4] = -520; OperandBs[5] = 1100; OperandBs[6] = -12099; + results[4]= 210 ; results[5]= 0; results[6]= 0; for (a = 1; a < 7; a = a + 1) - #10000 //Delay begin: addtest operandA = OperandAs[a]; operandB = OperandBs[a]; - #10000 //Delay - if((result != addresults[a]) && (overflow != 1)) begin + totaltests = totaltests + 2; + #20000 //Delay + if((result != results[a]) && (overflow != 1)) begin notpassed = notpassed + 1; // Add to test not passed - $display("Test Case adding %d to %d Failed with result %d and overflow %d", operandA, operandB, result, overflow); + $display("Test Case adding %b to %b Failed with result %d, overflow %d", operandA, operandB, result, overflow); + end + if ((result == 0) && (zero!=1))begin //Zero flag check + notpassed = notpassed + 1; + $display("Test Case adding %d to %d Failed with result %d, and zero %d", operandA, operandB, result, zero); end end //Test the Subtract operation command = 1; OperandAs[1] = -5358; OperandAs[2] = 0; OperandAs[3] = -35; - OperandAs[4] = 730; OperandAs[5] = 4294967210; OperandAs[6] = -4294961800; OperandBs[1] = 5369; OperandBs[2] = 0; OperandBs[3] = -65; - OperandBs[4] = -520; OperandBs[5] = 300; OperandBs[6] = -30000; - addresults[1]= 11; addresults[2]= 0 ; addresults[3]= -100; - addresults[4]= 210 ; addresults[5]= 0; addresults[6]= 0; + results[1]= -10727; results[2]= 0 ; results[3]= 30; + + OperandAs[4] = 730; OperandAs[5] = 2147481648; OperandAs[6] = -2147423648; + OperandBs[4] = -520; OperandBs[5] = -12983; OperandBs[6] = 300000; + results[4]= 1250 ; results[5]= 0; results[6]= 0; for (a = 1; a < 7; a = a + 1) #10000 begin: subtracttest operandA = OperandAs[a]; operandB = OperandBs[a]; + totaltests = totaltests + 2; #10000 - if((result != addresults[a]) && (overflow != 1)) begin + if((result != results[a]) && (overflow != 1)) begin notpassed = notpassed + 1; // Add to test not passed - $display("Test Case subtracting %d - %d Failed", operandA, operandB); + $display("Test Case subtracting %d from %d Failed with result %d and overflow %d", operandB, operandA, result, overflow); + end + if ((result == 0) && (zero!=1))begin //Zero flag check + notpassed = notpassed + 1; + $display("Test Case subtracting %d to %d Failed with result %d, and zero %d", operandA, operandB, result, zero); end end - #10000 //Delay. - $display(" %d | %d | %d | %d | %d ", $signed(operandA), $signed(operandB), command, $signed(result), $signed(expected)); - operandA = 300; //Set register a. - operandB = 25; //Set register b. + //Test XOR command = 2; - expected = 32'b100110101; - #10000 //Delay. - $display(" %d | %d | %d | %d | %d ", $signed(operandA), $signed(operandB), command, $signed(result), $signed(expected)); - operandA = 200; //Set register a. - operandB = 985; //Set register b. + OperandAs[1] = 300; OperandAs[2] = 32'b1001001; OperandAs[3] = 32'b000011111; + OperandBs[1] = 25; OperandBs[2] = 32'b1001001; OperandBs[3] = 32'b000011111; + results[1]= 32'b100110101; results[2] = 0; results[3]= 0; + OperandAs[4] = 32'b1101010101010001010; + OperandBs[4] = 0; + results[4] = 32'b1101010101010001010; + + for (a = 1; a < 5; a = a + 1) + #10000 + begin: xortest + operandA = OperandAs[a]; + operandB = OperandBs[a]; + totaltests = totaltests + 2; + #10000 + if(result != results[a]) begin + notpassed = notpassed + 1; // Add to test not passed + $display("Test Case XOR %b and %b Failed with result %b", operandB, operandA, result); + end + if ((result == 0) && (zero!=1))begin //Zero flag check + notpassed = notpassed + 1; + $display("Test Case XOR %b and %b Failed with result %b, and zero %b", operandA, operandB, result, zero); + end + end + + //Test SLT command = 3; - expected = 1; - #10000 //Delay. - $display(" %d | %d | %d | %d | %d | %b | %b ", $signed(operandA), $signed(operandB), command, $signed(result), $signed(expected), overflow, zero); - operandA = 360; //Set register a. - operandB = 111; //Set register b. + OperandAs[1] = 200; OperandAs[2] = -800; OperandAs[3] = -9000; + OperandBs[1] = 700; OperandBs[2] = -200; OperandBs[3] = 1293846473; + results[1]= 1; results[2]= 1; results[3]= 1; + + OperandAs[4] = 0; OperandAs[5] = 2147481648; OperandAs[6] = -2147423648; + OperandBs[4] = 0; OperandBs[5] = -12983; OperandBs[6] = 300000; + results[4]= 0; results[5]= 0; results[6]= 1; + + OperandAs[7] = 102938761; OperandAs[8] = -800; OperandAs[9] = 54086; + OperandBs[7] = 234; OperandBs[8] = -3773377; OperandBs[9] = -2988888; + results[7]= 0; results[8] = 0; results[9]= 0; + + OperandAs[10] = 700; OperandAs[11] = -800; + OperandBs[10] = 700; OperandBs[11] = -800; + results[10]= 0; results[11]= 0; + + for (a = 1; a < 12; a = a + 1) + #10000 + begin: slttest + operandA = OperandAs[a]; + operandB = OperandBs[a]; + totaltests = totaltests + 2; + #10000 + if(result != results[a]) begin + notpassed = notpassed + 1; // Add to test not passed + $display("Test Case slt %d and %d Failed with result %d", operandB, operandA, result); + end + if ((result == 0) && (zero!=1))begin //Zero flag check + notpassed = notpassed + 1; + $display("Test Case slt %d and %d Failed with result %d, and zero %d", operandA, operandB, result, zero); + end + end + + + //Test AND command = 4; - expected = 32'b001101000; - #10000 //Delay. - $display(" %d | %d | %d | %d | %d ", $signed(operandA), $signed(operandB), command, $signed(result), $signed(expected)); - operandA = -2; //Set register a. - operandB = -60694; //Set register b. + OperandAs[1] = 32'b111010001; OperandAs[2] = 32'b101001; OperandAs[3] = 32'b000011111; + OperandBs[1] = 32'b010101001; OperandBs[2] = 32'b010000; OperandBs[3] = 32'b000000000; + results[1] = 32'b010000001; results[2] = 0; results[3]= 0; + OperandAs[4] = 32'b11010101010; + OperandBs[4] = 32'b10100010010; + results[4] = 32'b10000000010; + + for (a = 1; a < 5; a = a + 1) + #10000 + begin: andtest + operandA = OperandAs[a]; + operandB = OperandBs[a]; + totaltests = totaltests + 2; + #10000 + if(result != results[a]) begin + notpassed = notpassed + 1; // Add to test not passed + $display("Test Case AND %b and %b Failed with result %b", operandB, operandA, result); + end + if ((result == 0) && (zero!=1))begin //Zero flag check + notpassed = notpassed + 1; + $display("Test Case AND %b and %b Failed with result %b, and zero %b", operandA, operandB, result, zero); + end + end + + //Test NAND command = 5; - expected = 32'b00000000000000001110110100010101; - #10000 //Delay. - $display(" %d | %d | %d | %d | %d ", $signed(operandA), $signed(operandB), command, $signed(result), $signed(expected)); - operandA = -2959; //Set register a. - operandB = 6333; //Set register b. - command = 6; - expected = 32'b00000000000000000000001100000010; - //11111111111111111111010001110001 - //00000000000000000001100010111101 - #10000 //Delay. - $display(" %d | %d | %d | %d | %d ", $signed(operandA), $signed(operandB), command, $signed(result), $signed(expected)); - operandA = -1045; //Set register a. - operandB = 54968; //Set register b. + OperandAs[1] = 32'b111010001; OperandAs[2] = 32'b11111111111111111111111111111111; OperandAs[3] = 32'b000011111; + OperandBs[1] = 32'b010101001; OperandBs[2] = 32'b11111111111111111111111111111111; OperandBs[3] = 32'b000000000; + results[1] = 32'b11111111111111111111111101111110; results[2] = 0; results[3] = 32'b11111111111111111111111111111111; + + for (a = 1; a < 4; a = a + 1) + #10000 + begin: nandtest + operandA = OperandAs[a]; + operandB = OperandBs[a]; + totaltests = totaltests + 2; + #10000 + if(result != results[a]) begin + notpassed = notpassed + 1; // Add to test not passed + $display("Test Case NAND %b and %b Failed with result %b", operandB, operandA, result); + end + if ((result == 0) && (zero!=1))begin //Zero flag check + notpassed = notpassed + 1; + $display("Test Case NAND %b and %b Failed with result %b, and zero %b", operandA, operandB, result, zero); + end + end + + //Test OR command = 7; - expected = 32'b11111111111111111111111111111011; - //11111111111111111111101111101011 - //00000000000000001101011010111000 - #10000 //Delay. - $display(" %d | %d | %d | %d | %d ", $signed(operandA), $signed(operandB), command, $signed(result), $signed(expected)); - operandA = 9050; //Set register a. - operandB = 985; //Set register b. - command = 3; - expected = 0; - #10000 //Delay. - $display(" %d | %d | %d | %d | %d | %b | %b ", $signed(operandA), $signed(operandB), command, $signed(result), $signed(expected), overflow, zero); - operandA = -10505; //Set register a. - operandB = 2; //Set register b. - command = 3; - expected = 1; - #10000 //Delay. - $display(" %d | %d | %d | %d | %d | %b | %b ", $signed(operandA), $signed(operandB), command, $signed(result), $signed(expected), overflow, zero); - operandA = 1; //Set register a. - operandB = 2; //Set register b. - command = 3; - expected = 1; - #10000 //Delay. - $display(" %d | %d | %d | %d | %d | %b | %b ", $signed(operandA), $signed(operandB), command, $signed(result), $signed(expected), overflow, zero); - operandA = 1; //Set register a. - operandB = 2; //Set register b. - command = 1; - expected = -1; - #10000 //Delay. - $display(" %d | %d | %d | %d | %d | %b | %b ", $signed(operandA), $signed(operandB), command, $signed(result), $signed(expected), overflow, zero); - operandA = -1; //Set register a. - operandB = 2; //Set register b. - command = 3; - expected = 1; - #10000 //Delay. - $display(" %d | %d | %d | %d | %d | %b | %b ", $signed(operandA), $signed(operandB), command, $signed(result), $signed(expected), overflow, zero); - operandA = -1; //Set register a. - operandB = 2; //Set register b. - command = 1; - expected = -3; - #10000 //Delay. - $display(" %d | %d | %d | %d | %d | %b | %b ", $signed(operandA), $signed(operandB), command, $signed(result), $signed(expected), overflow, zero); - operandA = 1; //Set register a. - operandB = -2; //Set register b. - command = 3; - expected = 0; - #10000 //Delay. - $display(" %d | %d | %d | %d | %d | %b | %b ", $signed(operandA), $signed(operandB), command, $signed(result), $signed(expected), overflow, zero); - operandA = 1; //Set register a. - operandB = -2; //Set register b. - command = 1; - expected = 3; - #10000 //Delay. - $display(" %d | %d | %d | %d | %d | %b | %b ", $signed(operandA), $signed(operandB), command, $signed(result), $signed(expected), overflow, zero); - operandA = -3; //Set register a. - operandB = -2; //Set register b. - command = 3; - expected = 1; - #10000 //Delay. - $display(" %d | %d | %d | %d | %d | %b | %b ", $signed(operandA), $signed(operandB), command, $signed(result), $signed(expected), overflow, zero); - operandA = -3; //Set register a. - operandB = -2; //Set register b. - command = 1; - expected = -1; - #10000 //Delay. - //$display(" %d | %d | %d | %d | %d | %b | %b ", $signed(operandA), $signed(operandB), command, $signed(result), $signed(expected), overflow, zero); + OperandAs[1] = 32'b111010001; OperandAs[2] = 32'b00000; OperandAs[3] = 32'b000011111; + OperandBs[1] = 32'b010101001; OperandBs[2] = 32'b00000; OperandBs[3] = 32'b000000000; + results[1] = 32'b111111001; results[2] = 0; results[3]= 32'b000011111; - $display("Number of test failed %d", notpassed); + for (a = 1; a < 4; a = a + 1) + #10000 + begin: ortest + operandA = OperandAs[a]; + operandB = OperandBs[a]; + totaltests = totaltests + 2; + #10000 + if(result != results[a]) begin + notpassed = notpassed + 1; // Add to test not passed + $display("Test Case OR %b with %b Failed with result %b", operandB, operandA, result); + end + if ((result == 0) && (zero!=1))begin //Zero flag check + notpassed = notpassed + 1; + $display("Test Case OR %b with %b Failed with result %b, and zero %b", operandA, operandB, result, zero); + end + end + + //Test NOR + command = 6; + OperandAs[1] = 32'b111010001; OperandAs[2] = 32'b00000; OperandAs[3] = 32'b000011111; + OperandBs[1] = 32'b010101001; OperandBs[2] = 32'b00000; OperandBs[3] = 32'b11111111111111111111111111100000; + results[1] = 32'b11111111111111111111111000000110; results[2] = 32'b11111111111111111111111111111111; results[3]= 0; + + for (a = 1; a < 4; a = a + 1) + #10000 + begin: nortest + operandA = OperandAs[a]; + operandB = OperandBs[a]; + totaltests = totaltests + 2; + #10000 + if(result != results[a]) begin + notpassed = notpassed + 1; // Add to test not passed + $display("Test Case NOR %b with %b Failed with result %b", operandB, operandA, result); + end + if ((result == 0) && (zero!=1))begin //Zero flag check + notpassed = notpassed + 1; + $display("Test Case NOR %b with %b Failed with result %b, and zero %b", operandA, operandB, result, zero); + end + end + + //Print our total test results + if (notpassed == 0) begin + $display("All %d tests passed! :)", totaltests); + end + else begin + $display("Number of test failed %d", notpassed); + end end endmodule diff --git a/alu.v b/alu.v index bc9741b..2ac10d4 100755 --- a/alu.v +++ b/alu.v @@ -77,10 +77,7 @@ output overflow, input[31:0] operandA, input[31:0] operandB, input[2:0] command -//input invertB, -//input flagger ); - //wire control2; wire[31:0] Cout; wire slt; wire isSlt; @@ -97,7 +94,6 @@ input[2:0] command //for the 0th bit slice, pass in invertB for Cin too (add one if subtracting) ALUcontrolLUT ctrl(muxindex, invertB, flagger, command); BitSliceALU bit0(preresult[0], Cout[0], invertB, invertB, muxindex, operandA[0], operandB[0]); - genvar i; generate for (i = 1; i < 32; i = i+1) @@ -105,14 +101,10 @@ input[2:0] command BitSliceALU bitany(preresult[i], Cout[i], invertB, Cout[i-1], muxindex, operandA[i], operandB[i]); end endgenerate - //BitSliceALU bit31(result[31], Cout[31], invertB, Cout[30], mux, operandA[31], operandB[31]); - TheBigOR bigger(nzero, preresult); //a bit wise OR on all bits of result, might not be allowed to do this + `XOR (preflow, Cout[31], Cout[30]); //determine overflow - - `NOT (zero, nzero); //set zero for each operation `AND (carryout, flagger, Cout[31]); //set carryout if flagger `AND (overflow, flagger, preflow); //set overflow if flagger - //`OR(overflow, preflow, 1'b0); //Set SLT if the mux command is 3 bitMultiplexer sltSL(slt, preflow, {operandA[31], preresult[31]}); //compute is less than @@ -129,4 +121,8 @@ input[2:0] command `AND (result[j], nSlt, preresult[j]); //This and operation changes the bit to 0 if nSlt is false, and keeps the result otherwise. end endgenerate + + TheBigOR bigger(nzero, result); //a bit wise OR on all bits of result, might not be allowed to do this + `NOT (zero, nzero); //set zero for each operation + endmodule diff --git a/alu.vcd b/alu.vcd index d0870d0..5162e91 100644 --- a/alu.vcd +++ b/alu.vcd @@ -1,5 +1,5 @@ $date - Wed Oct 11 23:03:50 2017 + Fri Oct 13 00:10:37 2017 $end $version Icarus Verilog @@ -28,13 +28,9 @@ $upscope $end $scope module ALUTestBench $end $var reg 3 ' command [2:0] $end $upscope $end -$scope module ALUTestBench $end -$var reg 32 ( expected [31:0] $end -$upscope $end $enddefinitions $end #0 $dumpvars -b1011 ( b0 ' x& x% @@ -109,312 +105,1186 @@ bx0000000000000000000000000001011 # 0$ #1190000 b1011 # -#10000000 -b11111111111111111111111111010000 ( -b1 ' -b1001011000 " -b1000101000 ! -#10080000 +#20000000 +b0 " +b0 ! +#20080000 +0& +#20110000 +b11111111111111111110101100001001 # +#20130000 +b11111111111111111110101111000001 # +#20150000 +b10100111000000 # +#20170000 +b0 # +#20500000 +1% +#40000000 +b11111111111111111111111110111111 " +b11111111111111111111111111011101 ! +#40080000 +1& +#40110000 +b1000000 # +#40150000 +b11111111111111111111111101011000 # +#40190000 +b11111111111111111111111100011100 # +#40230000 +b11111111111111111111111110011100 # +#40440000 +0% +#60000000 +b11111111111111111111110111111000 " +b1011011010 ! +#60060000 +0& +#60080000 +1& +#60100000 +0& +#60110000 +b11111111111111111111101010011110 # +#60120000 +1& +#60130000 +b11111111111111111111101011011110 # +#60140000 +0& +#60150000 +b11111111111111111111010011011010 # +#60160000 +1& +#60170000 +b11111111111111111111010011010010 # +#60180000 +0& +#60190000 +b11111111111111111110100011010010 # +#60200000 +1& +#60220000 0& -#10100000 +#60230000 +b11111111111111111101000011010010 # +#60240000 1& -#10110000 -b11000 # -#10120000 +#60260000 0& -#10130000 -b1011100 # -#10140000 +#60270000 +b11111111111111111010000011010010 # +#60280000 1& -#10150000 -b1001100 # -#10160000 +#60300000 0& -#10170000 -b11001000 # -#10180000 +#60310000 +b11111111111111110100000011010010 # +#60320000 1& -#10200000 +#60340000 0& -#10210000 -b111000000 # -#10220000 +#60350000 +b11111111111111101000000011010010 # +#60360000 1& -#10240000 +#60380000 0& -#10250000 -b1111010000 # -#10260000 +#60390000 +b11111111111111010000000011010010 # +#60400000 1& -#10280000 +#60420000 0& -#10290000 -b11111010000 # -#10300000 +#60430000 +b11111111111110100000000011010010 # +#60440000 1& -#10320000 +#60460000 0& -#10330000 -b111111010000 # -#10340000 +#60470000 +b11111111111101000000000011010010 # +#60480000 1& -#10360000 +#60500000 0& -#10370000 -b1111111010000 # -#10380000 +#60510000 +b11111111111010000000000011010010 # +#60520000 1& -#10400000 +#60540000 0& -#10410000 -b11111111010000 # -#10420000 +#60550000 +b11111111110100000000000011010010 # +#60560000 1& -#10440000 +#60580000 0& -#10450000 -b111111111010000 # -#10460000 +#60590000 +b11111111101000000000000011010010 # +#60600000 1& -#10480000 +#60620000 0& -#10490000 -b1111111111010000 # -#10500000 +#60630000 +b11111111010000000000000011010010 # +#60640000 1& -#10520000 +#60660000 0& -#10530000 -b11111111111010000 # -#10540000 +#60670000 +b11111110100000000000000011010010 # +#60680000 1& -#10560000 +#60700000 0& -#10570000 -b111111111111010000 # -#10580000 +#60710000 +b11111101000000000000000011010010 # +#60720000 1& -#10600000 +#60740000 0& -#10610000 -b1111111111111010000 # -#10620000 +#60750000 +b11111010000000000000000011010010 # +#60760000 1& -#10640000 +#60780000 0& -#10650000 -b11111111111111010000 # -#10660000 +#60790000 +b11110100000000000000000011010010 # +#60800000 1& -#10680000 +#60820000 0& -#10690000 -b111111111111111010000 # -#10700000 +#60830000 +b11101000000000000000000011010010 # +#60840000 1& -#10720000 +#60860000 0& -#10730000 -b1111111111111111010000 # -#10740000 +#60870000 +b11010000000000000000000011010010 # +#60880000 1& -#10760000 +#60900000 0& -#10770000 -b11111111111111111010000 # -#10780000 +#60910000 +b10100000000000000000000011010010 # +#60920000 1& -#10800000 +1$ +#60950000 +b1000000000000000000000011010010 # +#60960000 0& -#10810000 -b111111111111111111010000 # -#10820000 +#60990000 +b10000000000000000000000011010010 # +#61000000 1& +#61020000 +0$ +#61030000 +b11010010 # +#80000000 +b10001001100 " +b1111111111111111111111100111000 ! +#80100000 +0& +1$ +#80110000 +b10100010000 # +#80130000 +b10100000100 # +#80140000 +0$ +#80150000 +b11110000100 # +#80160000 +1$ +#80180000 +0$ +#80190000 +b1110000100 # +#80200000 +1$ +#80220000 +0$ +#80240000 +1$ +#80260000 +0$ +#80280000 +1$ +#80300000 +0$ +#80320000 +1$ +#80340000 +0$ +#80360000 +1$ +#80380000 +0$ +#80400000 +1$ +#80420000 +0$ +#80440000 +1$ +#80460000 +0$ +#80480000 +1$ +#80500000 +0$ +#80520000 +1$ +#80540000 +0$ +#80560000 +1$ +#80580000 +0$ +#80600000 +1$ +#80620000 +0$ +#80640000 +1$ +#80660000 +0$ +#80680000 +1$ +#80700000 +0$ +#80720000 +1$ +#80740000 +0$ +#80760000 +1$ +#80780000 +0$ +#80800000 +1$ +#80820000 +0$ +#80840000 +1$ +#80860000 +0$ +#80880000 +1$ +#80930000 +b10000000000000000000001110000100 # +#100000000 +b11111111111111111101000010111101 " +b10000000000000000000000110010000 ! +#100080000 +1& +#100110000 +b10000000000000000010000110001100 # +#100120000 +0$ +#100140000 +1$ +#100150000 +b10000000000000000111000010001101 # +#100160000 +0$ +#100170000 +b10000000000000000111000001001101 # +#100180000 +1$ +#100190000 +b10000000000000001101001001001101 # +#100200000 +0$ +#100220000 +1$ +#100230000 +b10000000000000011101001001001101 # +#100240000 +0$ +#100260000 +1$ +#100270000 +b10000000000000111101001001001101 # +#100280000 +0$ +#100300000 +1$ +#100310000 +b10000000000001111101001001001101 # +#100320000 +0$ +#100340000 +1$ +#100350000 +b10000000000011111101001001001101 # +#100360000 +0$ +#100380000 +1$ +#100390000 +b10000000000111111101001001001101 # +#100400000 +0$ +#100420000 +1$ +#100430000 +b10000000001111111101001001001101 # +#100440000 +0$ +#100460000 +1$ +#100470000 +b10000000011111111101001001001101 # +#100480000 +0$ +#100500000 +1$ +#100510000 +b10000000111111111101001001001101 # +#100520000 +0$ +#100540000 +1$ +#100550000 +b10000001111111111101001001001101 # +#100560000 +0$ +#100580000 +1$ +#100590000 +b10000011111111111101001001001101 # +#100600000 +0$ +#100620000 1$ -#10840000 +#100630000 +b10000111111111111101001001001101 # +#100640000 0$ -#10850000 -b1111111111111111111010000 # -#10860000 +#100660000 1$ -#10880000 +#100670000 +b10001111111111111101001001001101 # +#100680000 +0$ +#100700000 +1$ +#100710000 +b10011111111111111101001001001101 # +#100720000 +0$ +#100740000 +1$ +#100750000 +b10111111111111111101001001001101 # +#100760000 +0$ +#100780000 +1$ +#100790000 +b11111111111111111101001001001101 # +#100830000 +b1111111111111111101001001001101 # +#120000000 +b1 ' +#120080000 0& +#120100000 0$ -#10890000 -b11111111111111111111010000 # -#10900000 +#120110000 +b1111111111111111101001001001100 # +#120130000 +b10000000000000000010110010010000 # +#120150000 +b10000000000000000010110010010001 # +#120170000 +b10000000000000000010100001010111 # +#120210000 +b10000000000000000010000111010011 # +#120250000 +b10000000000000000011000011010011 # +#130000000 +b1010011111001 " +b11111111111111111110101100010010 ! +#130080000 +1& +#130110000 +b10000000000000000101101001010001 # +#130130000 +b10000000000000000101111000010001 # +#130150000 +b11111111111111111101111000010001 # +#130170000 +b11111111111111111101011000011001 # +#150000000 +b0 " +b0 ! +#150060000 +0& +#150080000 1& +#150100000 +0& +#150110000 +b11111111111111111111111100011011 # +#150120000 +1& +#150130000 +b11111111111111111111111111110111 # +#150140000 +0& +#150150000 +b11111111111111111111111111110110 # +#150160000 +1& +#150170000 +b11111111111111111111111111101100 # +#150180000 +0& +#150200000 +1& +#150210000 +b11111111111111111111111111011000 # +#150220000 +0& +#150240000 +1& +#150250000 +b11111111111111111111111110110000 # +#150260000 +0& +#150280000 +1& +#150290000 +b11111111111111111111111101100000 # +#150300000 +0& +#150320000 +1& +#150330000 +b11111111111111111111111011000000 # +#150340000 +0& +#150360000 +1& +#150370000 +b11111111111111111111110110000000 # +#150380000 +0& +#150400000 +1& +#150410000 +b11111111111111111111101100000000 # +#150420000 +0& +#150440000 +1& +#150450000 +b11111111111111111111011000000000 # +#150460000 +0& +#150480000 +1& +#150490000 +b11111111111111111110110000000000 # +#150500000 +0& +#150520000 +1& +#150530000 +b11111111111111111101100000000000 # +#150540000 +0& +#150560000 +1& +#150570000 +b11111111111111111011000000000000 # +#150580000 +0& +#150600000 +1& +#150610000 +b11111111111111110110000000000000 # +#150620000 +0& +#150640000 +1& +#150650000 +b11111111111111101100000000000000 # +#150660000 +0& +#150680000 +1& +#150690000 +b11111111111111011000000000000000 # +#150700000 +0& +#150720000 +1& +#150730000 +b11111111111110110000000000000000 # +#150740000 +0& +#150760000 +1& +#150770000 +b11111111111101100000000000000000 # +#150780000 +0& 1$ -#10920000 +#150800000 0$ -#10930000 -b111111111111111111111010000 # -#10970000 -b1111111111111111111111010000 # -#10980000 +#150810000 +b11111111111011000000000000000000 # +#150850000 +b11111111110110000000000000000000 # +#150890000 +b11111111101100000000000000000000 # +#150930000 +b11111111011000000000000000000000 # +#150940000 1$ -#11000000 +#150960000 +1& +0$ +#150970000 +b11111110110000000000000000000000 # +#150980000 0& +1$ +#151000000 0$ -#11010000 -b11111111111111111111111010000 # -#11020000 +#151010000 +b11111101100000000000000000000000 # +#151050000 +b11111011000000000000000000000000 # +#151090000 +b11110110000000000000000000000000 # +#151130000 +b11101100000000000000000000000000 # +#151170000 +b11011000000000000000000000000000 # +#151200000 +1$ +#151210000 +b10110000000000000000000000000000 # +#151220000 1& +#151250000 +b1100000000000000000000000000000 # +#151260000 +0& +#151280000 +0$ +#151290000 +b11000000000000000000000000000000 # +#151320000 1$ -#11040000 +#151330000 +b10000000000000000000000000000000 # +#151340000 +1& +#151360000 0$ -#11050000 -b111111111111111111111111010000 # -#11080000 +#151370000 +b0 # +#151700000 +1% +#170000000 +b11111111111111111111111110111111 " +b11111111111111111111111111011101 ! +#170080000 +0& +#170100000 +1& +#170110000 +b1000000 # +#170120000 +0& +#170140000 +1& +#170160000 +0& +#170170000 +b110 # +#170180000 +1& +#170200000 +0& +#170210000 +b1110 # +#170220000 +1& +#170240000 +0& +#170250000 +b111110 # +#170260000 +1& +#170280000 +0& +#170290000 +b11110 # +#170300000 +1& +#170320000 +0& +#170340000 +1& +#170360000 +0& +#170380000 +1& +#170400000 +0& +#170420000 +1& +#170440000 +0% +0& +#170460000 +1& +#170480000 +0& +#170500000 +1& +#170520000 +0& +#170540000 +1& +#170560000 +0& +#170580000 +1& +#170600000 +0& +#170620000 +1& +#170640000 +0& +#170660000 +1& +#170680000 +0& +#170700000 +1& +#170720000 +0& +#170740000 +1& +#170760000 +0& +#170780000 +1& +#170800000 +0& +#170820000 +1& +#170840000 +0& +#170860000 +1& +#170880000 +0& +#170900000 +1& +#170920000 +0& +#170940000 +1& +#170960000 +0& +#170980000 +1& +#171000000 +0& +#171020000 +1& +#171040000 +0& +#171060000 +1& 1$ -#11090000 -b1111111111111111111111111010000 # -#11100000 +#171080000 +0$ +#190000000 +b11111111111111111111110111111000 " +b1011011010 ! +#190080000 0& -#11120000 +#190110000 +b11111111111111111111110100011110 # +#190130000 +b11111111111111111111110101011110 # +#190150000 +b10111011010 # +#190190000 +b10011010010 # +#190230000 +b10011000010 # +#190270000 +b10011100010 # +#210000000 +b11111111111111111100110101001001 " +b1111111111111111111100000110000 ! +#210110000 +b1111111111111111100111010101000 # +#210130000 +b1111111111111111100101010101000 # +#210150000 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+#230360000 +0$ +#230370000 +b10000001111111000101011000000000 # +#230380000 +1$ +#230390000 +b10000011111111000101011000000000 # +#230400000 +0$ +#230410000 +b10000011111111000101011010000000 # +#230420000 +1$ +#230430000 +b10000111111111000101011010000000 # +#230440000 +0$ +#230460000 +1$ +#230470000 +b10001111111111000101011010000000 # +#230480000 +0$ +#230500000 +1$ +#230510000 +b10011111111111000101011010000000 # +#230520000 +0$ +#230540000 +1$ +#230550000 +b10111111111111000101011010000000 # +#230560000 +0$ +#230580000 +1$ +#230590000 +b11111111111111000101011010000000 # +#230630000 +b1111111111111000101011010000000 # +#240000000 b10 ' -b11001 " -b100101100 ! -#20040000 +#240020000 +0$ +0& +#240040000 b0 # -#20050000 +#240050000 b1 # -#20060000 -b11111111111111111111111111010001 # -#20070000 -b11111111111111111111111111110000 # -#20080000 -b101110000 # -#20090000 +#240060000 +b1111111111111000101011010000001 # +#240070000 +b11111111111111000111111110000000 # +#240080000 +b10000000000001000111100110000000 # +#250000000 +b11001 " +b100101100 ! +#250090000 b100110100 # -#20110000 +#250110000 b100110101 # -#30000000 -b1 ( +#270000000 +b1001001 " +b1001001 ! +#270090000 +b1 # +#270110000 +b0 # +#270440000 +1% +#290000000 +b11111 " +b11111 ! +#310000000 +b0 " +b1101010101010001010 ! +#310090000 +b1101010101010001010 # +#310420000 +0% +#320000000 b11 ' -b1111011001 " +#320060000 +b0 # +#320190000 +b1 # +#320650000 +b0 # +#320980000 +1% +#330000000 +b1010111100 " b11001000 ! -#30060000 +#331070000 b1 # -#30080000 +#331400000 +0% +#350000000 +b11111111111111111111111100111000 " +b11111111111111111111110011100000 ! +#350170000 b0 # -#30190000 +#350500000 +1% +#350980000 b1 # -#40000000 -b1101000 ( -b100 ' -b1101111 " -b101101000 ! -#40060000 -b11111111111111111111110011101111 # -#40080000 -b11101001 # -#40100000 -b1101000 # -#50000000 -b1110110100010101 ( -b101 ' -b11111111111111110001001011101010 " -b11111111111111111111111111111110 ! -#50090000 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