diff --git a/.DS_Store b/.DS_Store new file mode 100644 index 0000000..aecde5d Binary files /dev/null and b/.DS_Store differ diff --git a/.gitignore b/.gitignore new file mode 100644 index 0000000..a251a56 --- /dev/null +++ b/.gitignore @@ -0,0 +1,2 @@ +tests + diff --git a/adder1bit.v b/adder1bit.v new file mode 100644 index 0000000..5ebf2f4 --- /dev/null +++ b/adder1bit.v @@ -0,0 +1,25 @@ +`include "gates.v" + +module adder1bit +( + output sum, + output carryout, + input a, + input b, + input carryin +); + wire BCin; + wire ACin; + wire AB; + + wire BxorCin; + + `AND(BCin,b,carryin); + `AND(ACin,a,carryin); + `AND(AB, a, b); + `OR(carryout,BCin,ACin,AB); + + `XOR(BxorCin,b,carryin); + `XOR(sum,a,BxorCin); + +endmodule \ No newline at end of file diff --git a/alu.t.v b/alu.t.v new file mode 100644 index 0000000..f5344c2 --- /dev/null +++ b/alu.t.v @@ -0,0 +1,83 @@ +`include "alu.v" +`define ADD 3'd0 +`define SUB 3'd1 +`define XOR 3'd2 +`define SLT 3'd3 +`define AND 3'd4 +`define NAND 3'd5 +`define NOR 3'd6 +`define OR 3'd7 + +module ALU_test(); + reg [31:0] A, B; + reg [2:0] command; + wire [31:0] result; + wire carryout,zero,overflow; + + ALU ALU_full(result[31:0],carryout,zero,overflow,A[31:0],B[31:0],command[2:0]); + + reg [31:0] testAVals [11:0]; + reg [31:0] testBVals [11:0]; + reg [2:0] testcommand[11:0]; + reg [31:0] testresults [11:0]; + reg testcarryouts [11:0]; + reg testzero [11:0]; + reg testoverflow[11:0]; + + task testALU; + input expectedCarryout, expectedZero, expectedOverflow; + input [31:0] a,b,expectedResult; + input [2:0] MuxIndex; + input integer testIndex; + begin + A=a; B=b; command=MuxIndex; #5000 + if (result == expectedResult && carryout == expectedCarryout && overflow == expectedOverflow) + $display("Test %d succeeded", testIndex); + else + $display("Test %d failed", testIndex); + $display("Operation: %d, Inputs: %b and %b, Output: %b, Carry out: %b, Overflow: %b", MuxIndex, a, b, result, carryout, overflow); + end + endtask + + integer i; + + initial begin + $dumpfile("alu.vcb"); + $dumpvars; + + testAVals[0] = 32'h7FFFFFFF; testBVals[0] = 32'h1; testcommand[0] = `ADD; testresults[0] = 32'h80000000; testoverflow[0] = 1; testzero[0]=0; testcarryouts[0]=0; + + testAVals[1] = 32'd100; testBVals[1] = 32'd475; testcommand[1] = `ADD; testresults[1] = 32'd575; testcarryouts[1] = 0; testzero[1]=0; testoverflow[1]=0; + + + + testAVals[2] = 32'h0FFF; testBVals[2] = 32'h00FF; testcommand[2] = `SUB; testresults[2] = 32'h0F00; testcarryouts[2] = 1; testzero[2]=0; testoverflow[2]=0; + + testAVals[3] = 32'h0000; testBVals[3] = 32'hFFFF; testcommand[3] = `SUB; testresults[3] = 32'hFFFF0001; testcarryouts[3] = 0; testzero[3]=0; testoverflow[3]=0; + + + + testAVals[4] = 32'h0F0F; testBVals[4] = 32'hF0FF; testcommand[4] = `XOR; testresults[4] = 32'hFFF0; testcarryouts[4] = 0; testzero[4]=0; testoverflow[4]=0; + + testAVals[5] = 32'hFFFF; testBVals[5] = 32'h00FF; testcommand[5] = `AND; testresults[5] = 32'h00FF; testcarryouts[5] = 0; testzero[5]=0; testoverflow[5]=0; + + testAVals[6] = 32'hFF00; testBVals[6] = 32'hFFF0; testcommand[6] = `NAND; testresults[6] = 32'hFFFF00FF; testcarryouts[6] = 0; testzero[6]=0; testoverflow[6]=0; + + testAVals[7] = 32'h00FF; testBVals[7] = 32'h0FFF; testcommand[7] = `NOR; testresults[7] = 32'hFFFFF000; testcarryouts[7] = 0; testzero[7]=0; testoverflow[7]=0; + + testAVals[8] = 32'h00FF; testBVals[8] = 32'h0F0F; testcommand[8] = `OR; testresults[8] = 32'h0FFF; testcarryouts[8] = 0; testzero[8]=0; testoverflow[8]=0; + + + + testAVals[9] = 32'd15422; testBVals[9] = 32'd15421; testcommand[9] = `SLT; testresults[9] = 32'b0; testcarryouts[9] = 0; testzero[9]=0; testoverflow[9]=0; + + testAVals[10] = 32'd15422; testBVals[10] = 32'd15422; testcommand[10] = `SLT; testresults[10] = 32'b0; testcarryouts[10] = 0; testzero[10]=1; testoverflow[10]=0; + + testAVals[11] = 32'd15422; testBVals[11] = 32'd15423; testcommand[11] = `SLT; testresults[11] = 32'b1; testcarryouts[11] = 0; testzero[11]=0; testoverflow[11]=0; + + + for (i = 0; i < 12; i = i + 1) begin + testALU(testcarryouts[i], testzero[i], testoverflow[i], testAVals[i], testBVals[i], testresults[i], testcommand[i], i); + end + end +endmodule \ No newline at end of file diff --git a/alu.v b/alu.v new file mode 100644 index 0000000..e5e2407 --- /dev/null +++ b/alu.v @@ -0,0 +1,98 @@ +`include "gates.v" +`include "alu1bit.v" + +`define ADD 3'd0 +`define SUB 3'd1 +`define XOR 3'd2 +`define SLT 3'd3 +`define AND 3'd4 +`define NAND 3'd5 +`define NOR 3'd6 +`define OR 3'd7 + +module ALUcontrolLUT +( + output reg[2:0] muxindex, + output reg invertA, + output reg invertB, + input[2:0] ALUcommand +); + always @(ALUcommand) begin + case (ALUcommand) + `ADD: begin muxindex = 0; invertA = 0; invertB = 0; end + `SUB: begin muxindex = 0; invertA = 0; invertB = 1; end + `XOR: begin muxindex = 1; invertA = 0; invertB = 0; end + `SLT: begin muxindex = 2; invertA = 0; invertB = 1; end + `AND: begin muxindex = 3; invertA = 0; invertB = 0; end + `NOR: begin muxindex = 3; invertA = 1; invertB = 1; end + `OR: begin muxindex = 4; invertA = 0; invertB = 0; end + `NAND: begin muxindex = 4; invertA = 1; invertB = 1; end + endcase + end + +endmodule + +module ALU +( + output[31:0] result, + output carryout, + output zero, + output overflow, + input[31:0] operandA, + input[31:0] operandB, + input[2:0] command +); + + wire set; + wire invertA; + wire invertB; + wire[2:0] operation; + wire[31:0] carryins; + + ALUcontrolLUT control(operation, invertA, invertB, command); + + generate + genvar i; + for (i=0; i<31; i=i+1) begin + if (i == 0) + ALU1bit bitSliceALU( + result[i], + carryins[i+1], + operation, + operandA[i], + operandB[i], + invertA, + invertB, + invertB, + set + ); + else + ALU1bit bitSliceALU( + result[i], + carryins[i+1], + operation, + operandA[i], + operandB[i], + invertA, + invertB, + carryins[i], + 1'b0 + ); + end + endgenerate + + ALU1bitMSB lastBit( + result[31], + carryout, + overflow, + set, + operation, + operandA[31], + operandB[31], + invertA, + invertB, + carryins[31], + 1'b0 + ); + +endmodule diff --git a/alu.vcb b/alu.vcb new file mode 100644 index 0000000..477bb0f --- /dev/null +++ b/alu.vcb @@ -0,0 +1,12723 @@ +$date + Fri Oct 13 01:01:10 2017 +$end +$version + Icarus Verilog +$end +$timescale + 1s +$end +$scope module ALU_test $end +$var wire 1 ! carryout $end +$var wire 1 " overflow $end +$var wire 32 # result [31:0] $end +$var wire 1 $ zero $end +$var reg 32 % A [31:0] $end +$var reg 32 & B [31:0] $end +$var reg 3 ' command [2:0] $end +$var integer 32 ( i [31:0] $end +$scope module ALU_full $end +$var wire 32 ) carryins [31:0] $end +$var wire 1 ! carryout $end +$var wire 3 * command [2:0] $end +$var wire 1 + invertA $end +$var wire 1 , invertB $end +$var wire 32 - operandA [31:0] $end +$var wire 32 . operandB [31:0] $end +$var wire 3 / operation [2:0] $end +$var wire 1 " overflow $end +$var wire 32 0 result [31:0] $end +$var wire 1 1 set $end +$var wire 1 $ zero $end +$scope module control $end +$var wire 3 2 ALUcommand [2:0] $end +$var reg 1 3 invertA $end +$var reg 1 4 invertB $end +$var reg 3 5 muxindex [2:0] $end +$upscope $end +$scope module lastBit $end +$var wire 1 6 AandB $end +$var wire 1 7 AnA $end +$var wire 1 8 AorB $end +$var wire 1 9 AxorB $end +$var wire 1 : BnB $end +$var wire 1 ; _carryout $end +$var wire 1 < _overflow $end +$var wire 1 = carryin $end +$var wire 1 ! carryout $end +$var wire 1 + invertA $end +$var wire 1 , invertB $end +$var wire 1 > less $end +$var wire 1 ? nA $end +$var wire 1 @ nB $end +$var wire 1 A operandA $end +$var wire 1 B operandB $end +$var wire 3 C operation [2:0] $end +$var wire 1 " overflow $end +$var wire 1 D result $end +$var wire 1 1 set $end +$var wire 1 E sum $end +$var wire 1 F useCarryout $end +$var wire 1 G useOverflow $end +$var wire 8 H values [7:0] $end +$scope module Aselect $end +$var wire 1 A a $end +$var wire 1 ? b $end +$var wire 1 I d0 $end +$var wire 1 J d1 $end +$var wire 1 K nSelect $end +$var wire 1 + select $end +$var wire 1 7 selected $end +$upscope $end +$scope module Bselect $end +$var wire 1 B a $end +$var wire 1 @ b $end +$var wire 1 L d0 $end +$var wire 1 M d1 $end +$var wire 1 N nSelect $end +$var wire 1 , select $end +$var wire 1 : selected $end +$upscope $end +$scope module adder $end +$var wire 1 O AB $end +$var wire 1 P ACin $end +$var wire 1 Q BCin $end +$var wire 1 R BxorCin $end +$var wire 1 7 a $end +$var wire 1 : b $end +$var wire 1 = carryin $end +$var wire 1 ; carryout $end +$var wire 1 E sum $end +$upscope $end +$scope module resultSelect $end +$var wire 1 S d0 $end +$var wire 1 T d1 $end +$var wire 1 U d2 $end +$var wire 1 V d3 $end +$var wire 1 W d4 $end +$var wire 1 X d5 $end +$var wire 1 Y d6 $end +$var wire 1 Z d7 $end +$var wire 8 [ inputs [7:0] $end +$var wire 1 \ nselect0 $end +$var wire 1 ] nselect1 $end +$var wire 1 ^ nselect2 $end +$var wire 3 _ select [2:0] $end +$var wire 1 D selected $end +$upscope $end +$upscope $end +$scope begin genblk1 $end +$scope begin genblk2 $end +$scope module bitSliceALU $end +$var wire 1 ` AandB $end +$var wire 1 a AnA $end +$var wire 1 b AorB $end +$var wire 1 c AxorB $end +$var wire 1 d BnB $end +$var wire 1 e _carryout $end +$var wire 1 , carryin $end +$var wire 1 f carryout $end +$var wire 1 + invertA $end +$var wire 1 , invertB $end +$var wire 1 1 less $end +$var wire 1 g nA $end +$var wire 1 h nB $end +$var wire 1 i operandA $end +$var wire 1 j operandB $end +$var wire 3 k operation [2:0] $end +$var wire 1 l result $end +$var wire 1 m sum $end +$var wire 1 n useCarryout $end +$var wire 8 o values [7:0] $end +$scope module Aselect $end +$var wire 1 i a $end +$var wire 1 g b $end +$var wire 1 p d0 $end +$var wire 1 q d1 $end +$var wire 1 r nSelect $end +$var wire 1 + select $end +$var wire 1 a selected $end +$upscope $end +$scope module Bselect $end +$var wire 1 j a $end +$var wire 1 h b $end +$var wire 1 s d0 $end +$var wire 1 t d1 $end +$var wire 1 u nSelect $end +$var wire 1 , select $end +$var wire 1 d selected $end +$upscope $end +$scope module adder $end +$var wire 1 v AB $end +$var wire 1 w ACin $end +$var wire 1 x BCin $end +$var wire 1 y BxorCin $end +$var wire 1 a a $end +$var wire 1 d b $end +$var wire 1 , carryin $end +$var wire 1 e carryout $end +$var wire 1 m sum $end +$upscope $end +$scope module resultSelect $end +$var wire 1 z d0 $end +$var wire 1 { d1 $end +$var wire 1 | d2 $end +$var wire 1 } d3 $end +$var wire 1 ~ d4 $end +$var wire 1 !" d5 $end +$var wire 1 "" d6 $end +$var wire 1 #" d7 $end +$var wire 8 $" inputs [7:0] $end +$var wire 1 %" nselect0 $end +$var wire 1 &" nselect1 $end +$var wire 1 '" nselect2 $end +$var wire 3 (" select [2:0] $end +$var wire 1 l selected $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope begin genblk01 $end +$scope begin genblk3 $end +$scope module bitSliceALU $end +$var wire 1 )" AandB $end +$var wire 1 *" AnA $end +$var wire 1 +" AorB $end +$var wire 1 ," AxorB $end +$var wire 1 -" BnB $end +$var wire 1 ." _carryout $end +$var wire 1 /" carryin $end +$var wire 1 0" carryout $end +$var wire 1 + invertA $end +$var wire 1 , invertB $end +$var wire 1 1" less $end +$var wire 1 2" nA $end +$var wire 1 3" nB $end +$var wire 1 4" operandA $end +$var wire 1 5" operandB $end +$var wire 3 6" operation [2:0] $end +$var wire 1 7" result $end +$var wire 1 8" sum $end +$var wire 1 9" useCarryout $end +$var wire 8 :" values [7:0] $end +$scope module Aselect $end +$var wire 1 4" a $end +$var wire 1 2" b $end +$var wire 1 ;" d0 $end +$var wire 1 <" d1 $end +$var wire 1 =" nSelect $end +$var wire 1 + select $end +$var wire 1 *" selected $end +$upscope $end +$scope module Bselect $end +$var wire 1 5" a $end +$var wire 1 3" b $end +$var wire 1 >" d0 $end +$var wire 1 ?" d1 $end +$var wire 1 @" nSelect $end +$var wire 1 , select $end +$var wire 1 -" selected $end +$upscope $end +$scope module adder $end +$var wire 1 A" AB $end +$var wire 1 B" ACin $end +$var wire 1 C" BCin $end +$var wire 1 D" BxorCin $end +$var wire 1 *" a $end +$var wire 1 -" b $end +$var wire 1 /" carryin $end +$var wire 1 ." carryout $end +$var wire 1 8" sum $end +$upscope $end +$scope module resultSelect $end +$var wire 1 E" d0 $end +$var wire 1 F" d1 $end +$var wire 1 G" d2 $end +$var wire 1 H" d3 $end +$var wire 1 I" d4 $end +$var wire 1 J" d5 $end +$var wire 1 K" d6 $end +$var wire 1 L" d7 $end +$var wire 8 M" inputs [7:0] $end +$var wire 1 N" nselect0 $end +$var wire 1 O" nselect1 $end +$var wire 1 P" nselect2 $end +$var wire 3 Q" select [2:0] $end +$var wire 1 7" selected $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope begin genblk001 $end +$scope begin genblk3 $end +$scope module bitSliceALU $end +$var wire 1 R" AandB $end +$var wire 1 S" AnA $end +$var wire 1 T" AorB $end +$var wire 1 U" AxorB $end +$var wire 1 V" BnB $end +$var wire 1 W" _carryout $end +$var wire 1 X" carryin $end +$var wire 1 Y" carryout $end +$var wire 1 + invertA $end +$var wire 1 , invertB $end +$var wire 1 Z" less $end +$var wire 1 [" nA $end +$var wire 1 \" nB $end +$var wire 1 ]" operandA $end +$var wire 1 ^" operandB $end +$var wire 3 _" operation [2:0] $end +$var wire 1 `" result $end +$var wire 1 a" sum $end +$var wire 1 b" useCarryout $end +$var wire 8 c" values [7:0] $end +$scope module Aselect $end +$var wire 1 ]" a $end +$var wire 1 [" b $end +$var wire 1 d" d0 $end +$var wire 1 e" d1 $end +$var wire 1 f" nSelect $end +$var wire 1 + select $end +$var wire 1 S" selected $end +$upscope $end +$scope module Bselect $end +$var wire 1 ^" a $end +$var wire 1 \" b $end +$var wire 1 g" d0 $end +$var wire 1 h" d1 $end +$var wire 1 i" nSelect $end +$var wire 1 , select $end +$var wire 1 V" selected $end +$upscope $end +$scope module adder $end +$var wire 1 j" AB $end +$var wire 1 k" ACin $end +$var wire 1 l" BCin $end +$var wire 1 m" BxorCin $end +$var wire 1 S" a $end +$var wire 1 V" b $end +$var wire 1 X" carryin $end +$var wire 1 W" carryout $end +$var wire 1 a" sum $end +$upscope $end +$scope module resultSelect $end +$var wire 1 n" d0 $end +$var wire 1 o" d1 $end +$var wire 1 p" d2 $end +$var wire 1 q" d3 $end +$var wire 1 r" d4 $end +$var wire 1 s" d5 $end +$var wire 1 t" d6 $end +$var wire 1 u" d7 $end +$var wire 8 v" inputs [7:0] $end +$var wire 1 w" nselect0 $end +$var wire 1 x" nselect1 $end +$var wire 1 y" nselect2 $end +$var wire 3 z" select [2:0] $end +$var wire 1 `" selected $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope begin genblk0001 $end +$scope begin genblk3 $end +$scope module bitSliceALU $end +$var wire 1 {" AandB $end +$var wire 1 |" AnA $end +$var wire 1 }" AorB $end +$var wire 1 ~" AxorB $end +$var wire 1 !# BnB $end +$var wire 1 "# _carryout $end +$var wire 1 ## carryin $end +$var wire 1 $# carryout $end +$var wire 1 + invertA $end +$var wire 1 , invertB $end +$var wire 1 %# less $end +$var wire 1 &# nA $end +$var wire 1 '# nB $end +$var wire 1 (# operandA $end +$var wire 1 )# operandB $end +$var wire 3 *# operation [2:0] $end +$var wire 1 +# result $end +$var wire 1 ,# sum $end +$var wire 1 -# useCarryout $end +$var wire 8 .# values [7:0] $end +$scope module Aselect $end +$var wire 1 (# a $end +$var wire 1 &# b $end +$var wire 1 /# d0 $end +$var wire 1 0# d1 $end +$var wire 1 1# nSelect $end +$var wire 1 + select $end +$var wire 1 |" selected $end +$upscope $end +$scope module Bselect $end +$var wire 1 )# a $end +$var wire 1 '# b $end +$var wire 1 2# d0 $end +$var wire 1 3# d1 $end +$var wire 1 4# nSelect $end +$var wire 1 , select $end +$var wire 1 !# selected $end +$upscope $end +$scope module adder $end +$var wire 1 5# AB $end +$var wire 1 6# ACin $end +$var wire 1 7# BCin $end +$var wire 1 8# BxorCin $end +$var wire 1 |" a $end +$var wire 1 !# b $end +$var wire 1 ## carryin $end +$var wire 1 "# carryout $end +$var wire 1 ,# sum $end +$upscope $end +$scope module resultSelect $end +$var wire 1 9# d0 $end +$var wire 1 :# d1 $end +$var wire 1 ;# d2 $end +$var wire 1 <# d3 $end +$var wire 1 =# d4 $end +$var wire 1 ># d5 $end +$var wire 1 ?# d6 $end +$var wire 1 @# d7 $end +$var wire 8 A# inputs [7:0] $end +$var wire 1 B# nselect0 $end +$var wire 1 C# nselect1 $end +$var wire 1 D# nselect2 $end +$var wire 3 E# select [2:0] $end +$var wire 1 +# selected $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope begin genblk00001 $end +$scope begin genblk3 $end +$scope module bitSliceALU $end +$var wire 1 F# AandB $end +$var wire 1 G# AnA $end +$var wire 1 H# AorB $end +$var wire 1 I# AxorB $end +$var wire 1 J# BnB $end +$var wire 1 K# _carryout $end +$var wire 1 L# carryin $end +$var wire 1 M# carryout $end +$var wire 1 + invertA $end +$var wire 1 , invertB $end +$var wire 1 N# less $end +$var wire 1 O# nA $end +$var wire 1 P# nB $end +$var wire 1 Q# operandA $end +$var wire 1 R# operandB $end +$var wire 3 S# operation [2:0] $end +$var wire 1 T# result $end +$var wire 1 U# sum $end +$var wire 1 V# useCarryout $end +$var wire 8 W# values [7:0] $end +$scope module Aselect $end +$var wire 1 Q# a $end +$var wire 1 O# b $end +$var wire 1 X# d0 $end +$var wire 1 Y# d1 $end +$var wire 1 Z# nSelect $end +$var wire 1 + select $end +$var wire 1 G# selected $end +$upscope $end +$scope module Bselect $end +$var wire 1 R# a $end +$var wire 1 P# b $end +$var wire 1 [# d0 $end +$var wire 1 \# d1 $end +$var wire 1 ]# nSelect $end +$var wire 1 , select $end +$var wire 1 J# selected $end +$upscope $end +$scope module adder $end +$var wire 1 ^# AB $end +$var wire 1 _# ACin $end +$var wire 1 `# BCin $end +$var wire 1 a# BxorCin $end +$var wire 1 G# a $end +$var wire 1 J# b $end +$var wire 1 L# carryin $end +$var wire 1 K# carryout $end +$var wire 1 U# sum $end +$upscope $end +$scope module resultSelect $end +$var wire 1 b# d0 $end +$var wire 1 c# d1 $end +$var wire 1 d# d2 $end +$var wire 1 e# d3 $end +$var wire 1 f# d4 $end +$var wire 1 g# d5 $end +$var wire 1 h# d6 $end +$var wire 1 i# d7 $end +$var wire 8 j# inputs [7:0] $end +$var wire 1 k# nselect0 $end +$var wire 1 l# nselect1 $end +$var wire 1 m# nselect2 $end +$var wire 3 n# select [2:0] $end +$var wire 1 T# selected $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope begin genblk000001 $end +$scope begin genblk3 $end +$scope module bitSliceALU $end +$var wire 1 o# AandB $end +$var wire 1 p# AnA $end +$var wire 1 q# AorB $end +$var wire 1 r# AxorB $end +$var wire 1 s# BnB $end +$var wire 1 t# _carryout $end +$var wire 1 u# carryin $end +$var wire 1 v# carryout $end +$var wire 1 + invertA $end +$var wire 1 , invertB $end +$var wire 1 w# less $end +$var wire 1 x# nA $end +$var wire 1 y# nB $end +$var wire 1 z# operandA $end +$var wire 1 {# operandB $end +$var wire 3 |# operation [2:0] $end +$var wire 1 }# result $end +$var wire 1 ~# sum $end +$var wire 1 !$ useCarryout $end +$var wire 8 "$ values [7:0] $end +$scope module Aselect $end +$var wire 1 z# a $end +$var wire 1 x# b $end +$var wire 1 #$ d0 $end +$var wire 1 $$ d1 $end +$var wire 1 %$ nSelect $end +$var wire 1 + select $end +$var wire 1 p# selected $end +$upscope $end +$scope module Bselect $end +$var wire 1 {# a $end +$var wire 1 y# b $end +$var wire 1 &$ d0 $end +$var wire 1 '$ d1 $end +$var wire 1 ($ nSelect $end +$var wire 1 , select $end +$var wire 1 s# selected $end +$upscope $end +$scope module adder $end +$var wire 1 )$ AB $end +$var wire 1 *$ ACin $end +$var wire 1 +$ BCin $end +$var wire 1 ,$ BxorCin $end +$var wire 1 p# a $end +$var wire 1 s# b $end +$var wire 1 u# carryin $end +$var wire 1 t# carryout $end +$var wire 1 ~# sum $end +$upscope $end +$scope module resultSelect $end +$var wire 1 -$ d0 $end +$var wire 1 .$ d1 $end +$var wire 1 /$ d2 $end +$var wire 1 0$ d3 $end +$var wire 1 1$ d4 $end +$var wire 1 2$ d5 $end +$var wire 1 3$ d6 $end +$var wire 1 4$ d7 $end +$var wire 8 5$ inputs [7:0] $end +$var wire 1 6$ nselect0 $end +$var wire 1 7$ nselect1 $end +$var wire 1 8$ nselect2 $end +$var wire 3 9$ select [2:0] $end +$var wire 1 }# selected $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope begin genblk0000001 $end +$scope begin genblk3 $end +$scope module bitSliceALU $end +$var wire 1 :$ AandB $end +$var wire 1 ;$ AnA $end +$var wire 1 <$ AorB $end +$var wire 1 =$ AxorB $end +$var wire 1 >$ BnB $end +$var wire 1 ?$ _carryout $end +$var wire 1 @$ carryin $end +$var wire 1 A$ carryout $end +$var wire 1 + invertA $end +$var wire 1 , invertB $end +$var wire 1 B$ less $end +$var wire 1 C$ nA $end +$var wire 1 D$ nB $end +$var wire 1 E$ operandA $end +$var wire 1 F$ operandB $end +$var wire 3 G$ operation [2:0] $end +$var wire 1 H$ result $end +$var wire 1 I$ sum $end +$var wire 1 J$ useCarryout $end +$var wire 8 K$ values [7:0] $end +$scope module Aselect $end +$var wire 1 E$ a $end +$var wire 1 C$ b $end +$var wire 1 L$ d0 $end +$var wire 1 M$ d1 $end +$var wire 1 N$ nSelect $end +$var wire 1 + select $end +$var wire 1 ;$ selected $end +$upscope $end +$scope module Bselect $end +$var wire 1 F$ a $end +$var wire 1 D$ b $end +$var wire 1 O$ d0 $end +$var wire 1 P$ d1 $end +$var wire 1 Q$ nSelect $end +$var wire 1 , select $end +$var wire 1 >$ selected $end +$upscope $end +$scope module adder $end +$var wire 1 R$ AB $end +$var wire 1 S$ ACin $end +$var wire 1 T$ BCin $end +$var wire 1 U$ BxorCin $end +$var wire 1 ;$ a $end +$var wire 1 >$ b $end +$var wire 1 @$ carryin $end +$var wire 1 ?$ carryout $end +$var wire 1 I$ sum $end +$upscope $end +$scope module resultSelect $end +$var wire 1 V$ d0 $end +$var wire 1 W$ d1 $end +$var wire 1 X$ d2 $end +$var wire 1 Y$ d3 $end +$var wire 1 Z$ d4 $end +$var wire 1 [$ d5 $end +$var wire 1 \$ d6 $end +$var wire 1 ]$ d7 $end +$var wire 8 ^$ inputs [7:0] $end +$var wire 1 _$ nselect0 $end +$var wire 1 `$ nselect1 $end +$var wire 1 a$ nselect2 $end +$var wire 3 b$ select [2:0] $end +$var wire 1 H$ selected $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope begin genblk00000001 $end +$scope begin genblk3 $end +$scope module bitSliceALU $end +$var wire 1 c$ AandB $end +$var wire 1 d$ AnA $end +$var wire 1 e$ AorB $end +$var wire 1 f$ AxorB $end +$var wire 1 g$ BnB $end +$var wire 1 h$ _carryout $end +$var wire 1 i$ carryin $end +$var wire 1 j$ carryout $end +$var wire 1 + invertA $end +$var wire 1 , invertB $end +$var wire 1 k$ less $end +$var wire 1 l$ nA $end +$var wire 1 m$ nB $end +$var wire 1 n$ operandA $end +$var wire 1 o$ operandB $end +$var wire 3 p$ operation [2:0] $end +$var wire 1 q$ result $end +$var wire 1 r$ sum $end +$var wire 1 s$ useCarryout $end +$var wire 8 t$ values [7:0] $end +$scope module Aselect $end +$var wire 1 n$ a $end +$var wire 1 l$ b $end +$var wire 1 u$ d0 $end +$var wire 1 v$ d1 $end +$var wire 1 w$ nSelect $end +$var wire 1 + select $end +$var wire 1 d$ selected $end +$upscope $end +$scope module Bselect $end +$var wire 1 o$ a $end +$var wire 1 m$ b $end +$var wire 1 x$ d0 $end +$var wire 1 y$ d1 $end +$var wire 1 z$ nSelect $end +$var wire 1 , select $end +$var wire 1 g$ selected $end +$upscope $end +$scope module adder $end +$var wire 1 {$ AB $end +$var wire 1 |$ ACin $end +$var wire 1 }$ BCin $end +$var wire 1 ~$ BxorCin $end +$var wire 1 d$ a $end +$var wire 1 g$ b $end +$var wire 1 i$ carryin $end +$var wire 1 h$ carryout $end +$var wire 1 r$ sum $end +$upscope $end +$scope module resultSelect $end +$var wire 1 !% d0 $end +$var wire 1 "% d1 $end +$var wire 1 #% d2 $end +$var wire 1 $% d3 $end +$var wire 1 %% d4 $end +$var wire 1 &% d5 $end +$var wire 1 '% d6 $end +$var wire 1 (% d7 $end +$var wire 8 )% inputs [7:0] $end +$var wire 1 *% nselect0 $end +$var wire 1 +% nselect1 $end +$var wire 1 ,% nselect2 $end +$var wire 3 -% select [2:0] $end +$var wire 1 q$ selected $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope begin genblk000000001 $end +$scope begin genblk3 $end +$scope module bitSliceALU $end +$var wire 1 .% AandB $end +$var wire 1 /% AnA $end +$var wire 1 0% AorB $end +$var wire 1 1% AxorB $end +$var wire 1 2% BnB $end +$var wire 1 3% _carryout $end +$var wire 1 4% carryin $end +$var wire 1 5% carryout $end +$var wire 1 + invertA $end +$var wire 1 , invertB $end +$var wire 1 6% less $end +$var wire 1 7% nA $end +$var wire 1 8% nB $end +$var wire 1 9% operandA $end +$var wire 1 :% operandB $end +$var wire 3 ;% operation [2:0] $end +$var wire 1 <% result $end +$var wire 1 =% sum $end +$var wire 1 >% useCarryout $end +$var wire 8 ?% values [7:0] $end +$scope module Aselect $end +$var wire 1 9% a $end +$var wire 1 7% b $end +$var wire 1 @% d0 $end +$var wire 1 A% d1 $end +$var wire 1 B% nSelect $end +$var wire 1 + select $end +$var wire 1 /% selected $end +$upscope $end +$scope module Bselect $end +$var wire 1 :% a $end +$var wire 1 8% b $end +$var wire 1 C% d0 $end +$var wire 1 D% d1 $end +$var wire 1 E% nSelect $end +$var wire 1 , select $end +$var wire 1 2% selected $end +$upscope $end +$scope module adder $end +$var wire 1 F% AB $end +$var wire 1 G% ACin $end +$var wire 1 H% BCin $end +$var wire 1 I% BxorCin $end +$var wire 1 /% a $end +$var wire 1 2% b $end +$var wire 1 4% carryin $end +$var wire 1 3% carryout $end +$var wire 1 =% sum $end +$upscope $end +$scope module resultSelect $end +$var wire 1 J% d0 $end +$var wire 1 K% d1 $end +$var wire 1 L% d2 $end +$var wire 1 M% d3 $end +$var wire 1 N% d4 $end +$var wire 1 O% d5 $end +$var wire 1 P% d6 $end +$var wire 1 Q% d7 $end +$var wire 8 R% inputs [7:0] $end +$var wire 1 S% nselect0 $end +$var wire 1 T% nselect1 $end +$var wire 1 U% nselect2 $end +$var wire 3 V% select [2:0] $end +$var wire 1 <% selected $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope begin genblk0000000001 $end +$scope begin genblk3 $end +$scope module bitSliceALU $end +$var wire 1 W% AandB $end +$var wire 1 X% AnA $end +$var wire 1 Y% AorB $end +$var wire 1 Z% AxorB $end +$var wire 1 [% BnB $end +$var wire 1 \% _carryout $end +$var wire 1 ]% carryin $end +$var wire 1 ^% carryout $end +$var wire 1 + invertA $end +$var wire 1 , invertB $end +$var wire 1 _% less $end +$var wire 1 `% nA $end +$var wire 1 a% nB $end +$var wire 1 b% operandA $end +$var wire 1 c% operandB $end +$var wire 3 d% operation [2:0] $end +$var wire 1 e% result $end +$var wire 1 f% sum $end +$var wire 1 g% useCarryout $end +$var wire 8 h% values [7:0] $end +$scope module Aselect $end +$var wire 1 b% a $end +$var wire 1 `% b $end +$var wire 1 i% d0 $end +$var wire 1 j% d1 $end +$var wire 1 k% nSelect $end +$var wire 1 + select $end +$var wire 1 X% selected $end +$upscope $end +$scope module Bselect $end +$var wire 1 c% a $end +$var wire 1 a% b $end +$var wire 1 l% d0 $end +$var wire 1 m% d1 $end +$var wire 1 n% nSelect $end +$var wire 1 , select $end +$var wire 1 [% selected $end +$upscope $end +$scope module adder $end +$var wire 1 o% AB $end +$var wire 1 p% ACin $end +$var wire 1 q% BCin $end +$var wire 1 r% BxorCin $end +$var wire 1 X% a $end +$var wire 1 [% b $end +$var wire 1 ]% carryin $end +$var wire 1 \% carryout $end +$var wire 1 f% sum $end +$upscope $end +$scope module resultSelect $end +$var wire 1 s% d0 $end +$var wire 1 t% d1 $end +$var wire 1 u% d2 $end +$var wire 1 v% d3 $end +$var wire 1 w% d4 $end +$var wire 1 x% d5 $end +$var wire 1 y% d6 $end +$var wire 1 z% d7 $end +$var wire 8 {% inputs [7:0] $end +$var wire 1 |% nselect0 $end +$var wire 1 }% nselect1 $end +$var wire 1 ~% nselect2 $end +$var wire 3 !& select [2:0] $end +$var wire 1 e% selected $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope begin genblk00000000001 $end +$scope begin genblk3 $end +$scope module bitSliceALU $end +$var wire 1 "& AandB $end +$var wire 1 #& AnA $end +$var wire 1 $& AorB $end +$var wire 1 %& AxorB $end +$var wire 1 && BnB $end +$var wire 1 '& _carryout $end +$var wire 1 (& carryin $end +$var wire 1 )& carryout $end +$var wire 1 + invertA $end +$var wire 1 , invertB $end +$var wire 1 *& less $end +$var wire 1 +& nA $end +$var wire 1 ,& nB $end +$var wire 1 -& operandA $end +$var wire 1 .& operandB $end +$var wire 3 /& operation [2:0] $end +$var wire 1 0& result $end +$var wire 1 1& sum $end +$var wire 1 2& useCarryout $end +$var wire 8 3& values [7:0] $end +$scope module Aselect $end +$var wire 1 -& a $end +$var wire 1 +& b $end +$var wire 1 4& d0 $end +$var wire 1 5& d1 $end +$var wire 1 6& nSelect $end +$var wire 1 + select $end +$var wire 1 #& selected $end +$upscope $end +$scope module Bselect $end +$var wire 1 .& a $end +$var wire 1 ,& b $end +$var wire 1 7& d0 $end +$var wire 1 8& d1 $end +$var wire 1 9& nSelect $end +$var wire 1 , select $end +$var wire 1 && selected $end +$upscope $end +$scope module adder $end +$var wire 1 :& AB $end +$var wire 1 ;& ACin $end +$var wire 1 <& BCin $end +$var wire 1 =& BxorCin $end +$var wire 1 #& a $end +$var wire 1 && b $end +$var wire 1 (& carryin $end +$var wire 1 '& carryout $end +$var wire 1 1& sum $end +$upscope $end +$scope module resultSelect $end +$var wire 1 >& d0 $end +$var wire 1 ?& d1 $end +$var wire 1 @& d2 $end +$var wire 1 A& d3 $end +$var wire 1 B& d4 $end +$var wire 1 C& d5 $end +$var wire 1 D& d6 $end +$var wire 1 E& d7 $end +$var wire 8 F& inputs [7:0] $end +$var wire 1 G& nselect0 $end +$var wire 1 H& nselect1 $end +$var wire 1 I& nselect2 $end +$var wire 3 J& select [2:0] $end +$var wire 1 0& selected $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope begin genblk000000000001 $end +$scope begin genblk3 $end +$scope module bitSliceALU $end +$var wire 1 K& AandB $end +$var wire 1 L& AnA $end +$var wire 1 M& AorB $end +$var wire 1 N& AxorB $end +$var wire 1 O& BnB $end +$var wire 1 P& _carryout $end +$var wire 1 Q& carryin $end +$var wire 1 R& carryout $end +$var wire 1 + invertA $end +$var wire 1 , invertB $end +$var wire 1 S& less $end +$var wire 1 T& nA $end +$var wire 1 U& nB $end +$var wire 1 V& operandA $end +$var wire 1 W& operandB $end +$var wire 3 X& operation [2:0] $end +$var wire 1 Y& result $end +$var wire 1 Z& sum $end +$var wire 1 [& useCarryout $end +$var wire 8 \& values [7:0] $end +$scope module Aselect $end +$var wire 1 V& a $end +$var wire 1 T& b $end +$var wire 1 ]& d0 $end +$var wire 1 ^& d1 $end +$var wire 1 _& nSelect $end +$var wire 1 + select $end +$var wire 1 L& selected $end +$upscope $end +$scope module Bselect $end +$var wire 1 W& a $end +$var wire 1 U& b $end +$var wire 1 `& d0 $end +$var wire 1 a& d1 $end +$var wire 1 b& nSelect $end +$var wire 1 , select $end +$var wire 1 O& selected $end +$upscope $end +$scope module adder $end +$var wire 1 c& AB $end +$var wire 1 d& ACin $end +$var wire 1 e& BCin $end +$var wire 1 f& BxorCin $end +$var wire 1 L& a $end +$var wire 1 O& b $end +$var wire 1 Q& carryin $end +$var wire 1 P& carryout $end +$var wire 1 Z& sum $end +$upscope $end +$scope module resultSelect $end +$var wire 1 g& d0 $end +$var wire 1 h& d1 $end +$var wire 1 i& d2 $end +$var wire 1 j& d3 $end +$var wire 1 k& d4 $end +$var wire 1 l& d5 $end +$var wire 1 m& d6 $end +$var wire 1 n& d7 $end +$var wire 8 o& inputs [7:0] $end +$var wire 1 p& nselect0 $end +$var wire 1 q& nselect1 $end +$var wire 1 r& nselect2 $end +$var wire 3 s& select [2:0] $end +$var wire 1 Y& selected $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope begin genblk0000000000001 $end +$scope begin genblk3 $end +$scope module bitSliceALU $end +$var wire 1 t& AandB $end +$var wire 1 u& AnA $end +$var wire 1 v& AorB $end +$var wire 1 w& AxorB $end +$var wire 1 x& BnB $end +$var wire 1 y& _carryout $end +$var wire 1 z& carryin $end +$var wire 1 {& carryout $end +$var wire 1 + invertA $end +$var wire 1 , invertB $end +$var wire 1 |& less $end +$var wire 1 }& nA $end +$var wire 1 ~& nB $end +$var wire 1 !' operandA $end +$var wire 1 "' operandB $end +$var wire 3 #' operation [2:0] $end +$var wire 1 $' result $end +$var wire 1 %' sum $end +$var wire 1 &' useCarryout $end +$var wire 8 '' values [7:0] $end +$scope module Aselect $end +$var wire 1 !' a $end +$var wire 1 }& b $end +$var wire 1 (' d0 $end +$var wire 1 )' d1 $end +$var wire 1 *' nSelect $end +$var wire 1 + select $end +$var wire 1 u& selected $end +$upscope $end +$scope module Bselect $end +$var wire 1 "' a $end +$var wire 1 ~& b $end +$var wire 1 +' d0 $end +$var wire 1 ,' d1 $end +$var wire 1 -' nSelect $end +$var wire 1 , select $end +$var wire 1 x& selected $end +$upscope $end +$scope module adder $end +$var wire 1 .' AB $end +$var wire 1 /' ACin $end +$var wire 1 0' BCin $end +$var wire 1 1' BxorCin $end +$var wire 1 u& a $end +$var wire 1 x& b $end +$var wire 1 z& carryin $end +$var wire 1 y& carryout $end +$var wire 1 %' sum $end +$upscope $end +$scope module resultSelect $end +$var wire 1 2' d0 $end +$var wire 1 3' d1 $end +$var wire 1 4' d2 $end +$var wire 1 5' d3 $end +$var wire 1 6' d4 $end +$var wire 1 7' d5 $end +$var wire 1 8' d6 $end +$var wire 1 9' d7 $end +$var wire 8 :' inputs [7:0] $end +$var wire 1 ;' nselect0 $end +$var wire 1 <' nselect1 $end +$var wire 1 =' nselect2 $end +$var wire 3 >' select [2:0] $end +$var wire 1 $' selected $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope begin genblk00000000000001 $end +$scope begin genblk3 $end +$scope module bitSliceALU $end +$var wire 1 ?' AandB $end +$var wire 1 @' AnA $end +$var wire 1 A' AorB $end +$var wire 1 B' AxorB $end +$var wire 1 C' BnB $end +$var wire 1 D' _carryout $end +$var wire 1 E' carryin $end +$var wire 1 F' carryout $end +$var wire 1 + invertA $end +$var wire 1 , invertB $end +$var wire 1 G' less $end +$var wire 1 H' nA $end +$var wire 1 I' nB $end +$var wire 1 J' operandA $end +$var wire 1 K' operandB $end +$var wire 3 L' operation [2:0] $end +$var wire 1 M' result $end +$var wire 1 N' sum $end +$var wire 1 O' useCarryout $end +$var wire 8 P' values [7:0] $end +$scope module Aselect $end +$var wire 1 J' a $end +$var wire 1 H' b $end +$var wire 1 Q' d0 $end +$var wire 1 R' d1 $end +$var wire 1 S' nSelect $end +$var wire 1 + select $end +$var wire 1 @' selected $end +$upscope $end +$scope module Bselect $end +$var wire 1 K' a $end +$var wire 1 I' b $end +$var wire 1 T' d0 $end +$var wire 1 U' d1 $end +$var wire 1 V' nSelect $end +$var wire 1 , select $end +$var wire 1 C' selected $end +$upscope $end +$scope module adder $end +$var wire 1 W' AB $end +$var wire 1 X' ACin $end +$var wire 1 Y' BCin $end +$var wire 1 Z' BxorCin $end +$var wire 1 @' a $end +$var wire 1 C' b $end +$var wire 1 E' carryin $end +$var wire 1 D' carryout $end +$var wire 1 N' sum $end +$upscope $end +$scope module resultSelect $end +$var wire 1 [' d0 $end +$var wire 1 \' d1 $end +$var wire 1 ]' d2 $end +$var wire 1 ^' d3 $end +$var wire 1 _' d4 $end +$var wire 1 `' d5 $end +$var wire 1 a' d6 $end +$var wire 1 b' d7 $end +$var wire 8 c' inputs [7:0] $end +$var wire 1 d' nselect0 $end +$var wire 1 e' nselect1 $end +$var wire 1 f' nselect2 $end +$var wire 3 g' select [2:0] $end +$var wire 1 M' selected $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope begin genblk000000000000001 $end +$scope begin genblk3 $end +$scope module bitSliceALU $end +$var wire 1 h' AandB $end +$var wire 1 i' AnA $end +$var wire 1 j' AorB $end +$var wire 1 k' AxorB $end +$var wire 1 l' BnB $end +$var wire 1 m' _carryout $end +$var wire 1 n' carryin $end +$var wire 1 o' carryout $end +$var wire 1 + invertA $end +$var wire 1 , invertB $end +$var wire 1 p' less $end +$var wire 1 q' nA $end +$var wire 1 r' nB $end +$var wire 1 s' operandA $end +$var wire 1 t' operandB $end +$var wire 3 u' operation [2:0] $end +$var wire 1 v' result $end +$var wire 1 w' sum $end +$var wire 1 x' useCarryout $end +$var wire 8 y' values [7:0] $end +$scope module Aselect $end +$var wire 1 s' a $end +$var wire 1 q' b $end +$var wire 1 z' d0 $end +$var wire 1 {' d1 $end +$var wire 1 |' nSelect $end +$var wire 1 + select $end +$var wire 1 i' selected $end +$upscope $end +$scope module Bselect $end +$var wire 1 t' a $end +$var wire 1 r' b $end +$var wire 1 }' d0 $end +$var wire 1 ~' d1 $end +$var wire 1 !( nSelect $end +$var wire 1 , select $end +$var wire 1 l' selected $end +$upscope $end +$scope module adder $end +$var wire 1 "( AB $end +$var wire 1 #( ACin $end +$var wire 1 $( BCin $end +$var wire 1 %( BxorCin $end +$var wire 1 i' a $end +$var wire 1 l' b $end +$var wire 1 n' carryin $end +$var wire 1 m' carryout $end +$var wire 1 w' sum $end +$upscope $end +$scope module resultSelect $end +$var wire 1 &( d0 $end +$var wire 1 '( d1 $end +$var wire 1 (( d2 $end +$var wire 1 )( d3 $end +$var wire 1 *( d4 $end +$var wire 1 +( d5 $end +$var wire 1 ,( d6 $end +$var wire 1 -( d7 $end +$var wire 8 .( inputs [7:0] $end +$var wire 1 /( nselect0 $end +$var wire 1 0( nselect1 $end +$var wire 1 1( nselect2 $end +$var wire 3 2( select [2:0] $end +$var wire 1 v' selected $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope begin genblk0000000000000001 $end +$scope begin genblk3 $end +$scope module bitSliceALU $end +$var wire 1 3( AandB $end +$var wire 1 4( AnA $end +$var wire 1 5( AorB $end +$var wire 1 6( AxorB $end +$var wire 1 7( BnB $end +$var wire 1 8( _carryout $end +$var wire 1 9( carryin $end +$var wire 1 :( carryout $end +$var wire 1 + invertA $end +$var wire 1 , invertB $end +$var wire 1 ;( less $end +$var wire 1 <( nA $end +$var wire 1 =( nB $end +$var wire 1 >( operandA $end +$var wire 1 ?( operandB $end +$var wire 3 @( operation [2:0] $end +$var wire 1 A( result $end +$var wire 1 B( sum $end +$var wire 1 C( useCarryout $end +$var wire 8 D( values [7:0] $end +$scope module Aselect $end +$var wire 1 >( a $end +$var wire 1 <( b $end +$var wire 1 E( d0 $end +$var wire 1 F( d1 $end +$var wire 1 G( nSelect $end +$var wire 1 + select $end +$var wire 1 4( selected $end +$upscope $end +$scope module Bselect $end +$var wire 1 ?( a $end +$var wire 1 =( b $end +$var wire 1 H( d0 $end +$var wire 1 I( d1 $end +$var wire 1 J( nSelect $end +$var wire 1 , select $end +$var wire 1 7( selected $end +$upscope $end +$scope module adder $end +$var wire 1 K( AB $end +$var wire 1 L( ACin $end +$var wire 1 M( BCin $end +$var wire 1 N( BxorCin $end +$var wire 1 4( a $end +$var wire 1 7( b $end +$var wire 1 9( carryin $end +$var wire 1 8( carryout $end +$var wire 1 B( sum $end +$upscope $end +$scope module resultSelect $end +$var wire 1 O( d0 $end +$var wire 1 P( d1 $end +$var wire 1 Q( d2 $end +$var wire 1 R( d3 $end +$var wire 1 S( d4 $end +$var wire 1 T( d5 $end +$var wire 1 U( d6 $end +$var wire 1 V( d7 $end +$var wire 8 W( inputs [7:0] $end +$var wire 1 X( nselect0 $end +$var wire 1 Y( nselect1 $end +$var wire 1 Z( nselect2 $end +$var wire 3 [( select [2:0] $end +$var wire 1 A( selected $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope begin genblk00000000000000001 $end +$scope begin genblk3 $end +$scope module bitSliceALU $end +$var wire 1 \( AandB $end +$var wire 1 ]( AnA $end +$var wire 1 ^( AorB $end +$var wire 1 _( AxorB $end +$var wire 1 `( BnB $end +$var wire 1 a( _carryout $end +$var wire 1 b( carryin $end +$var wire 1 c( carryout $end +$var wire 1 + invertA $end +$var wire 1 , invertB $end +$var wire 1 d( less $end +$var wire 1 e( nA $end +$var wire 1 f( nB $end +$var wire 1 g( operandA $end +$var wire 1 h( operandB $end +$var wire 3 i( operation [2:0] $end +$var wire 1 j( result $end +$var wire 1 k( sum $end +$var wire 1 l( useCarryout $end +$var wire 8 m( values [7:0] $end +$scope module Aselect $end +$var wire 1 g( a $end +$var wire 1 e( b $end +$var wire 1 n( d0 $end +$var wire 1 o( d1 $end +$var wire 1 p( nSelect $end +$var wire 1 + select $end +$var wire 1 ]( selected $end +$upscope $end +$scope module Bselect $end +$var wire 1 h( a $end +$var wire 1 f( b $end +$var wire 1 q( d0 $end +$var wire 1 r( d1 $end +$var wire 1 s( nSelect $end +$var wire 1 , select $end +$var wire 1 `( selected $end +$upscope $end +$scope module adder $end +$var wire 1 t( AB $end +$var wire 1 u( ACin $end +$var wire 1 v( BCin $end +$var wire 1 w( BxorCin $end +$var wire 1 ]( a $end +$var wire 1 `( b $end +$var wire 1 b( carryin $end +$var wire 1 a( carryout $end +$var wire 1 k( sum $end +$upscope $end +$scope module resultSelect $end +$var wire 1 x( d0 $end +$var wire 1 y( d1 $end +$var wire 1 z( d2 $end +$var wire 1 {( d3 $end +$var wire 1 |( d4 $end +$var wire 1 }( d5 $end +$var wire 1 ~( d6 $end +$var wire 1 !) d7 $end +$var wire 8 ") inputs [7:0] $end +$var wire 1 #) nselect0 $end +$var wire 1 $) nselect1 $end +$var wire 1 %) nselect2 $end +$var wire 3 &) select [2:0] $end +$var wire 1 j( selected $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope begin genblk000000000000000001 $end +$scope begin genblk3 $end +$scope module bitSliceALU $end +$var wire 1 ') AandB $end +$var wire 1 () AnA $end +$var wire 1 )) AorB $end +$var wire 1 *) AxorB $end +$var wire 1 +) BnB $end +$var wire 1 ,) _carryout $end +$var wire 1 -) carryin $end +$var wire 1 .) carryout $end +$var wire 1 + invertA $end +$var wire 1 , invertB $end +$var wire 1 /) less $end +$var wire 1 0) nA $end +$var wire 1 1) nB $end +$var wire 1 2) operandA $end +$var wire 1 3) operandB $end +$var wire 3 4) operation [2:0] $end +$var wire 1 5) result $end +$var wire 1 6) sum $end +$var wire 1 7) useCarryout $end +$var wire 8 8) values [7:0] $end +$scope module Aselect $end +$var wire 1 2) a $end +$var wire 1 0) b $end +$var wire 1 9) d0 $end +$var wire 1 :) d1 $end +$var wire 1 ;) nSelect $end +$var wire 1 + select $end +$var wire 1 () selected $end +$upscope $end +$scope module Bselect $end +$var wire 1 3) a $end +$var wire 1 1) b $end +$var wire 1 <) d0 $end +$var wire 1 =) d1 $end +$var wire 1 >) nSelect $end +$var wire 1 , select $end +$var wire 1 +) selected $end +$upscope $end +$scope module adder $end +$var wire 1 ?) AB $end +$var wire 1 @) ACin $end +$var wire 1 A) BCin $end +$var wire 1 B) BxorCin $end +$var wire 1 () a $end +$var wire 1 +) b $end +$var wire 1 -) carryin $end +$var wire 1 ,) carryout $end +$var wire 1 6) sum $end +$upscope $end +$scope module resultSelect $end +$var wire 1 C) d0 $end +$var wire 1 D) d1 $end +$var wire 1 E) d2 $end +$var wire 1 F) d3 $end +$var wire 1 G) d4 $end +$var wire 1 H) d5 $end +$var wire 1 I) d6 $end +$var wire 1 J) d7 $end +$var wire 8 K) inputs [7:0] $end +$var wire 1 L) nselect0 $end +$var wire 1 M) nselect1 $end +$var wire 1 N) nselect2 $end +$var wire 3 O) select [2:0] $end +$var wire 1 5) selected $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope begin genblk0000000000000000001 $end +$scope begin genblk3 $end +$scope module bitSliceALU $end +$var wire 1 P) AandB $end +$var wire 1 Q) AnA $end +$var wire 1 R) AorB $end +$var wire 1 S) AxorB $end +$var wire 1 T) BnB $end +$var wire 1 U) _carryout $end +$var wire 1 V) carryin $end +$var wire 1 W) carryout $end +$var wire 1 + invertA $end +$var wire 1 , invertB $end +$var wire 1 X) less $end +$var wire 1 Y) nA $end +$var wire 1 Z) nB $end +$var wire 1 [) operandA $end +$var wire 1 \) operandB $end +$var wire 3 ]) operation [2:0] $end +$var wire 1 ^) result $end +$var wire 1 _) sum $end +$var wire 1 `) useCarryout $end +$var wire 8 a) values [7:0] $end +$scope module Aselect $end +$var wire 1 [) a $end +$var wire 1 Y) b $end +$var wire 1 b) d0 $end +$var wire 1 c) d1 $end +$var wire 1 d) nSelect $end +$var wire 1 + select $end +$var wire 1 Q) selected $end +$upscope $end +$scope module Bselect $end +$var wire 1 \) a $end +$var wire 1 Z) b $end +$var wire 1 e) d0 $end +$var wire 1 f) d1 $end +$var wire 1 g) nSelect $end +$var wire 1 , select $end +$var wire 1 T) selected $end +$upscope $end +$scope module adder $end +$var wire 1 h) AB $end +$var wire 1 i) ACin $end +$var wire 1 j) BCin $end +$var wire 1 k) BxorCin $end +$var wire 1 Q) a $end +$var wire 1 T) b $end +$var wire 1 V) carryin $end +$var wire 1 U) carryout $end +$var wire 1 _) sum $end +$upscope $end +$scope module resultSelect $end +$var wire 1 l) d0 $end +$var wire 1 m) d1 $end +$var wire 1 n) d2 $end +$var wire 1 o) d3 $end +$var wire 1 p) d4 $end +$var wire 1 q) d5 $end +$var wire 1 r) d6 $end +$var wire 1 s) d7 $end +$var wire 8 t) inputs [7:0] $end +$var wire 1 u) nselect0 $end +$var wire 1 v) nselect1 $end +$var wire 1 w) nselect2 $end +$var wire 3 x) select [2:0] $end +$var wire 1 ^) selected $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope begin genblk00000000000000000001 $end +$scope begin genblk3 $end +$scope module bitSliceALU $end +$var wire 1 y) AandB $end +$var wire 1 z) AnA $end +$var wire 1 {) AorB $end +$var wire 1 |) AxorB $end +$var wire 1 }) BnB $end +$var wire 1 ~) _carryout $end +$var wire 1 !* carryin $end +$var wire 1 "* carryout $end +$var wire 1 + invertA $end +$var wire 1 , invertB $end +$var wire 1 #* less $end +$var wire 1 $* nA $end +$var wire 1 %* nB $end +$var wire 1 &* operandA $end +$var wire 1 '* operandB $end +$var wire 3 (* operation [2:0] $end +$var wire 1 )* result $end +$var wire 1 ** sum $end +$var wire 1 +* useCarryout $end +$var wire 8 ,* values [7:0] $end +$scope module Aselect $end +$var wire 1 &* a $end +$var wire 1 $* b $end +$var wire 1 -* d0 $end +$var wire 1 .* d1 $end +$var wire 1 /* nSelect $end +$var wire 1 + select $end +$var wire 1 z) selected $end +$upscope $end +$scope module Bselect $end +$var wire 1 '* a $end +$var wire 1 %* b $end +$var wire 1 0* d0 $end +$var wire 1 1* d1 $end +$var wire 1 2* nSelect $end +$var wire 1 , select $end +$var wire 1 }) selected $end +$upscope $end +$scope module adder $end +$var wire 1 3* AB $end +$var wire 1 4* ACin $end +$var wire 1 5* BCin $end +$var wire 1 6* BxorCin $end +$var wire 1 z) a $end +$var wire 1 }) b $end +$var wire 1 !* carryin $end +$var wire 1 ~) carryout $end +$var wire 1 ** sum $end +$upscope $end +$scope module resultSelect $end +$var wire 1 7* d0 $end +$var wire 1 8* d1 $end +$var wire 1 9* d2 $end +$var wire 1 :* d3 $end +$var wire 1 ;* d4 $end +$var wire 1 <* d5 $end +$var wire 1 =* d6 $end +$var wire 1 >* d7 $end +$var wire 8 ?* inputs [7:0] $end +$var wire 1 @* nselect0 $end +$var wire 1 A* nselect1 $end +$var wire 1 B* nselect2 $end +$var wire 3 C* select [2:0] $end +$var wire 1 )* selected $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope begin genblk000000000000000000001 $end +$scope begin genblk3 $end +$scope module bitSliceALU $end +$var wire 1 D* AandB $end +$var wire 1 E* AnA $end +$var wire 1 F* AorB $end +$var wire 1 G* AxorB $end +$var wire 1 H* BnB $end +$var wire 1 I* _carryout $end +$var wire 1 J* carryin $end +$var wire 1 K* carryout $end +$var wire 1 + invertA $end +$var wire 1 , invertB $end +$var wire 1 L* less $end +$var wire 1 M* nA $end +$var wire 1 N* nB $end +$var wire 1 O* operandA $end +$var wire 1 P* operandB $end +$var wire 3 Q* operation [2:0] $end +$var wire 1 R* result $end +$var wire 1 S* sum $end +$var wire 1 T* useCarryout $end +$var wire 8 U* values [7:0] $end +$scope module Aselect $end +$var wire 1 O* a $end +$var wire 1 M* b $end +$var wire 1 V* d0 $end +$var wire 1 W* d1 $end +$var wire 1 X* nSelect $end +$var wire 1 + select $end +$var wire 1 E* selected $end +$upscope $end +$scope module Bselect $end +$var wire 1 P* a $end +$var wire 1 N* b $end +$var wire 1 Y* d0 $end +$var wire 1 Z* d1 $end +$var wire 1 [* nSelect $end +$var wire 1 , select $end +$var wire 1 H* selected $end +$upscope $end +$scope module adder $end +$var wire 1 \* AB $end +$var wire 1 ]* ACin $end +$var wire 1 ^* BCin $end +$var wire 1 _* BxorCin $end +$var wire 1 E* a $end +$var wire 1 H* b $end +$var wire 1 J* carryin $end +$var wire 1 I* carryout $end +$var wire 1 S* sum $end +$upscope $end +$scope module resultSelect $end +$var wire 1 `* d0 $end +$var wire 1 a* d1 $end +$var wire 1 b* d2 $end +$var wire 1 c* d3 $end +$var wire 1 d* d4 $end +$var wire 1 e* d5 $end +$var wire 1 f* d6 $end +$var wire 1 g* d7 $end +$var wire 8 h* inputs [7:0] $end +$var wire 1 i* nselect0 $end +$var wire 1 j* nselect1 $end +$var wire 1 k* nselect2 $end +$var wire 3 l* select [2:0] $end +$var wire 1 R* selected $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope begin genblk0000000000000000000001 $end +$scope begin genblk3 $end +$scope module bitSliceALU $end +$var wire 1 m* AandB $end +$var wire 1 n* AnA $end +$var wire 1 o* AorB $end +$var wire 1 p* AxorB $end +$var wire 1 q* BnB $end +$var wire 1 r* _carryout $end +$var wire 1 s* carryin $end +$var wire 1 t* carryout $end +$var wire 1 + invertA $end +$var wire 1 , invertB $end +$var wire 1 u* less $end +$var wire 1 v* nA $end +$var wire 1 w* nB $end +$var wire 1 x* operandA $end +$var wire 1 y* operandB $end +$var wire 3 z* operation [2:0] $end +$var wire 1 {* result $end +$var wire 1 |* sum $end +$var wire 1 }* useCarryout $end +$var wire 8 ~* values [7:0] $end +$scope module Aselect $end +$var wire 1 x* a $end +$var wire 1 v* b $end +$var wire 1 !+ d0 $end +$var wire 1 "+ d1 $end +$var wire 1 #+ nSelect $end +$var wire 1 + select $end +$var wire 1 n* selected $end +$upscope $end +$scope module Bselect $end +$var wire 1 y* a $end +$var wire 1 w* b $end +$var wire 1 $+ d0 $end +$var wire 1 %+ d1 $end +$var wire 1 &+ nSelect $end +$var wire 1 , select $end +$var wire 1 q* selected $end +$upscope $end +$scope module adder $end +$var wire 1 '+ AB $end +$var wire 1 (+ ACin $end +$var wire 1 )+ BCin $end +$var wire 1 *+ BxorCin $end +$var wire 1 n* a $end +$var wire 1 q* b $end +$var wire 1 s* carryin $end +$var wire 1 r* carryout $end +$var wire 1 |* sum $end +$upscope $end +$scope module resultSelect $end +$var wire 1 ++ d0 $end +$var wire 1 ,+ d1 $end +$var wire 1 -+ d2 $end +$var wire 1 .+ d3 $end +$var wire 1 /+ d4 $end +$var wire 1 0+ d5 $end +$var wire 1 1+ d6 $end +$var wire 1 2+ d7 $end +$var wire 8 3+ inputs [7:0] $end +$var wire 1 4+ nselect0 $end +$var wire 1 5+ nselect1 $end +$var wire 1 6+ nselect2 $end +$var wire 3 7+ select [2:0] $end +$var wire 1 {* selected $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope begin genblk00000000000000000000001 $end +$scope begin genblk3 $end +$scope module bitSliceALU $end +$var wire 1 8+ AandB $end +$var wire 1 9+ AnA $end +$var wire 1 :+ AorB $end +$var wire 1 ;+ AxorB $end +$var wire 1 <+ BnB $end +$var wire 1 =+ _carryout $end +$var wire 1 >+ carryin $end +$var wire 1 ?+ carryout $end +$var wire 1 + invertA $end +$var wire 1 , invertB $end +$var wire 1 @+ less $end +$var wire 1 A+ nA $end +$var wire 1 B+ nB $end +$var wire 1 C+ operandA $end +$var wire 1 D+ operandB $end +$var wire 3 E+ operation [2:0] $end +$var wire 1 F+ result $end +$var wire 1 G+ sum $end +$var wire 1 H+ useCarryout $end +$var wire 8 I+ values [7:0] $end +$scope module Aselect $end +$var wire 1 C+ a $end +$var wire 1 A+ b $end +$var wire 1 J+ d0 $end +$var wire 1 K+ d1 $end +$var wire 1 L+ nSelect $end +$var wire 1 + select $end +$var wire 1 9+ selected $end +$upscope $end +$scope module Bselect $end +$var wire 1 D+ a $end +$var wire 1 B+ b $end +$var wire 1 M+ d0 $end +$var wire 1 N+ d1 $end +$var wire 1 O+ nSelect $end +$var wire 1 , select $end +$var wire 1 <+ selected $end +$upscope $end +$scope module adder $end +$var wire 1 P+ AB $end +$var wire 1 Q+ ACin $end +$var wire 1 R+ BCin $end +$var wire 1 S+ BxorCin $end +$var wire 1 9+ a $end +$var wire 1 <+ b $end +$var wire 1 >+ carryin $end +$var wire 1 =+ carryout $end +$var wire 1 G+ sum $end +$upscope $end +$scope module resultSelect $end +$var wire 1 T+ d0 $end +$var wire 1 U+ d1 $end +$var wire 1 V+ d2 $end +$var wire 1 W+ d3 $end +$var wire 1 X+ d4 $end +$var wire 1 Y+ d5 $end +$var wire 1 Z+ d6 $end +$var wire 1 [+ d7 $end +$var wire 8 \+ inputs [7:0] $end +$var wire 1 ]+ nselect0 $end +$var wire 1 ^+ nselect1 $end +$var wire 1 _+ nselect2 $end +$var wire 3 `+ select [2:0] $end +$var wire 1 F+ selected $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope begin genblk000000000000000000000001 $end +$scope begin genblk3 $end +$scope module bitSliceALU $end +$var wire 1 a+ AandB $end +$var wire 1 b+ AnA $end +$var wire 1 c+ AorB $end +$var wire 1 d+ AxorB $end +$var wire 1 e+ BnB $end +$var wire 1 f+ _carryout $end +$var wire 1 g+ carryin $end +$var wire 1 h+ carryout $end +$var wire 1 + invertA $end +$var wire 1 , invertB $end +$var wire 1 i+ less $end +$var wire 1 j+ nA $end +$var wire 1 k+ nB $end +$var wire 1 l+ operandA $end +$var wire 1 m+ operandB $end +$var wire 3 n+ operation [2:0] $end +$var wire 1 o+ result $end +$var wire 1 p+ sum $end +$var wire 1 q+ useCarryout $end +$var wire 8 r+ values [7:0] $end +$scope module Aselect $end +$var wire 1 l+ a $end +$var wire 1 j+ b $end +$var wire 1 s+ d0 $end +$var wire 1 t+ d1 $end +$var wire 1 u+ nSelect $end +$var wire 1 + select $end +$var wire 1 b+ selected $end +$upscope $end +$scope module Bselect $end +$var wire 1 m+ a $end +$var wire 1 k+ b $end +$var wire 1 v+ d0 $end +$var wire 1 w+ d1 $end +$var wire 1 x+ nSelect $end +$var wire 1 , select $end +$var wire 1 e+ selected $end +$upscope $end +$scope module adder $end +$var wire 1 y+ AB $end +$var wire 1 z+ ACin $end +$var wire 1 {+ BCin $end +$var wire 1 |+ BxorCin $end +$var wire 1 b+ a $end +$var wire 1 e+ b $end +$var wire 1 g+ carryin $end +$var wire 1 f+ carryout $end +$var wire 1 p+ sum $end +$upscope $end +$scope module resultSelect $end +$var wire 1 }+ d0 $end +$var wire 1 ~+ d1 $end +$var wire 1 !, d2 $end +$var wire 1 ", d3 $end +$var wire 1 #, d4 $end +$var wire 1 $, d5 $end +$var wire 1 %, d6 $end +$var wire 1 &, d7 $end +$var wire 8 ', inputs [7:0] $end +$var wire 1 (, nselect0 $end +$var wire 1 ), nselect1 $end +$var wire 1 *, nselect2 $end +$var wire 3 +, select [2:0] $end +$var wire 1 o+ selected $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope begin genblk0000000000000000000000001 $end +$scope begin genblk3 $end +$scope module bitSliceALU $end +$var wire 1 ,, AandB $end +$var wire 1 -, AnA $end +$var wire 1 ., AorB $end +$var wire 1 /, AxorB $end +$var wire 1 0, BnB $end +$var wire 1 1, _carryout $end +$var wire 1 2, carryin $end +$var wire 1 3, carryout $end +$var wire 1 + invertA $end +$var wire 1 , invertB $end +$var wire 1 4, less $end +$var wire 1 5, nA $end +$var wire 1 6, nB $end +$var wire 1 7, operandA $end +$var wire 1 8, operandB $end +$var wire 3 9, operation [2:0] $end +$var wire 1 :, result $end +$var wire 1 ;, sum $end +$var wire 1 <, useCarryout $end +$var wire 8 =, values [7:0] $end +$scope module Aselect $end +$var wire 1 7, a $end +$var wire 1 5, b $end +$var wire 1 >, d0 $end +$var wire 1 ?, d1 $end +$var wire 1 @, nSelect $end +$var wire 1 + select $end +$var wire 1 -, selected $end +$upscope $end +$scope module Bselect $end +$var wire 1 8, a $end +$var wire 1 6, b $end +$var wire 1 A, d0 $end +$var wire 1 B, d1 $end +$var wire 1 C, nSelect $end +$var wire 1 , select $end +$var wire 1 0, selected $end +$upscope $end +$scope module adder $end +$var wire 1 D, AB $end +$var wire 1 E, ACin $end +$var wire 1 F, BCin $end +$var wire 1 G, BxorCin $end +$var wire 1 -, a $end +$var wire 1 0, b $end +$var wire 1 2, carryin $end +$var wire 1 1, carryout $end +$var wire 1 ;, sum $end +$upscope $end +$scope module resultSelect $end +$var wire 1 H, d0 $end +$var wire 1 I, d1 $end +$var wire 1 J, d2 $end +$var wire 1 K, d3 $end +$var wire 1 L, d4 $end +$var wire 1 M, d5 $end +$var wire 1 N, d6 $end +$var wire 1 O, d7 $end +$var wire 8 P, inputs [7:0] $end +$var wire 1 Q, nselect0 $end +$var wire 1 R, nselect1 $end +$var wire 1 S, nselect2 $end +$var wire 3 T, select [2:0] $end +$var wire 1 :, selected $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope begin $gen1[25] $end +$scope begin genblk3 $end +$scope module bitSliceALU $end +$var wire 1 U, AandB $end +$var wire 1 V, AnA $end +$var wire 1 W, AorB $end +$var wire 1 X, AxorB $end +$var wire 1 Y, BnB $end +$var wire 1 Z, _carryout $end +$var wire 1 [, carryin $end +$var wire 1 \, carryout $end +$var wire 1 + invertA $end +$var wire 1 , invertB $end +$var wire 1 ], less $end +$var wire 1 ^, nA $end +$var wire 1 _, nB $end +$var wire 1 `, operandA $end +$var wire 1 a, operandB $end +$var wire 3 b, operation [2:0] $end +$var wire 1 c, result $end +$var wire 1 d, sum $end +$var wire 1 e, useCarryout $end +$var wire 8 f, values [7:0] $end +$scope module Aselect $end +$var wire 1 `, a $end +$var wire 1 ^, b $end +$var wire 1 g, d0 $end +$var wire 1 h, d1 $end +$var wire 1 i, nSelect $end +$var wire 1 + select $end +$var wire 1 V, selected $end +$upscope $end +$scope module Bselect $end +$var wire 1 a, a $end +$var wire 1 _, b $end +$var wire 1 j, d0 $end +$var wire 1 k, d1 $end +$var wire 1 l, nSelect $end +$var wire 1 , select $end +$var wire 1 Y, selected $end +$upscope $end +$scope module adder $end +$var wire 1 m, AB $end +$var wire 1 n, ACin $end +$var wire 1 o, BCin $end +$var wire 1 p, BxorCin $end +$var wire 1 V, a $end +$var wire 1 Y, b $end +$var wire 1 [, carryin $end +$var wire 1 Z, carryout $end +$var wire 1 d, sum $end +$upscope $end +$scope module resultSelect $end +$var wire 1 q, d0 $end +$var wire 1 r, d1 $end +$var wire 1 s, d2 $end +$var wire 1 t, d3 $end +$var wire 1 u, d4 $end +$var wire 1 v, d5 $end +$var wire 1 w, d6 $end +$var wire 1 x, d7 $end +$var wire 8 y, inputs [7:0] $end +$var wire 1 z, nselect0 $end +$var wire 1 {, nselect1 $end +$var wire 1 |, nselect2 $end +$var wire 3 }, select [2:0] $end +$var wire 1 c, selected $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope begin $gen1[26] $end +$scope begin genblk3 $end +$scope module bitSliceALU $end +$var wire 1 ~, AandB $end +$var wire 1 !- AnA $end +$var wire 1 "- AorB $end +$var wire 1 #- AxorB $end +$var wire 1 $- BnB $end +$var wire 1 %- _carryout $end +$var wire 1 &- carryin $end +$var wire 1 '- carryout $end +$var wire 1 + invertA $end +$var wire 1 , invertB $end +$var wire 1 (- less $end +$var wire 1 )- nA $end +$var wire 1 *- nB $end +$var wire 1 +- operandA $end +$var wire 1 ,- operandB $end +$var wire 3 -- operation [2:0] $end +$var wire 1 .- result $end +$var wire 1 /- sum $end +$var wire 1 0- useCarryout $end +$var wire 8 1- values [7:0] $end +$scope module Aselect $end +$var wire 1 +- a $end +$var wire 1 )- b $end +$var wire 1 2- d0 $end +$var wire 1 3- d1 $end +$var wire 1 4- nSelect $end +$var wire 1 + select $end +$var wire 1 !- selected $end +$upscope $end +$scope module Bselect $end +$var wire 1 ,- a $end +$var wire 1 *- b $end +$var wire 1 5- d0 $end +$var wire 1 6- d1 $end +$var wire 1 7- nSelect $end +$var wire 1 , select $end +$var wire 1 $- selected $end +$upscope $end +$scope module adder $end +$var wire 1 8- AB $end +$var wire 1 9- ACin $end +$var wire 1 :- BCin $end +$var wire 1 ;- BxorCin $end +$var wire 1 !- a $end +$var wire 1 $- b $end +$var wire 1 &- carryin $end +$var wire 1 %- carryout $end +$var wire 1 /- sum $end +$upscope $end +$scope module resultSelect $end +$var wire 1 <- d0 $end +$var wire 1 =- d1 $end +$var wire 1 >- d2 $end +$var wire 1 ?- d3 $end +$var wire 1 @- d4 $end +$var wire 1 A- d5 $end +$var wire 1 B- d6 $end +$var wire 1 C- d7 $end +$var wire 8 D- inputs [7:0] $end +$var wire 1 E- nselect0 $end +$var wire 1 F- nselect1 $end +$var wire 1 G- nselect2 $end +$var wire 3 H- select [2:0] $end +$var wire 1 .- selected $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope begin $gen1[27] $end +$scope begin genblk3 $end +$scope module bitSliceALU $end +$var wire 1 I- AandB $end +$var wire 1 J- AnA $end +$var wire 1 K- AorB $end +$var wire 1 L- AxorB $end +$var wire 1 M- BnB $end +$var wire 1 N- _carryout $end +$var wire 1 O- carryin $end +$var wire 1 P- carryout $end +$var wire 1 + invertA $end +$var wire 1 , invertB $end +$var wire 1 Q- less $end +$var wire 1 R- nA $end +$var wire 1 S- nB $end +$var wire 1 T- operandA $end +$var wire 1 U- operandB $end +$var wire 3 V- operation [2:0] $end +$var wire 1 W- result $end +$var wire 1 X- sum $end +$var wire 1 Y- useCarryout $end +$var wire 8 Z- values [7:0] $end +$scope module Aselect $end +$var wire 1 T- a $end +$var wire 1 R- b $end +$var wire 1 [- d0 $end +$var wire 1 \- d1 $end +$var wire 1 ]- nSelect $end +$var wire 1 + select $end +$var wire 1 J- selected $end +$upscope $end +$scope module Bselect $end +$var wire 1 U- a $end +$var wire 1 S- b $end +$var wire 1 ^- d0 $end +$var wire 1 _- d1 $end +$var wire 1 `- nSelect $end +$var wire 1 , select $end +$var wire 1 M- selected $end +$upscope $end +$scope module adder $end +$var wire 1 a- AB $end +$var wire 1 b- ACin $end +$var wire 1 c- BCin $end +$var wire 1 d- BxorCin $end +$var wire 1 J- a $end +$var wire 1 M- b $end +$var wire 1 O- carryin $end +$var wire 1 N- carryout $end +$var wire 1 X- sum $end +$upscope $end +$scope module resultSelect $end +$var wire 1 e- d0 $end +$var wire 1 f- d1 $end +$var wire 1 g- d2 $end +$var wire 1 h- d3 $end +$var wire 1 i- d4 $end +$var wire 1 j- d5 $end +$var wire 1 k- d6 $end +$var wire 1 l- d7 $end +$var wire 8 m- inputs [7:0] $end +$var wire 1 n- nselect0 $end +$var wire 1 o- nselect1 $end +$var wire 1 p- nselect2 $end +$var wire 3 q- select [2:0] $end +$var wire 1 W- selected $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope begin $gen1[28] $end +$scope begin genblk3 $end +$scope module bitSliceALU $end +$var wire 1 r- AandB $end +$var wire 1 s- AnA $end +$var wire 1 t- AorB $end +$var wire 1 u- AxorB $end +$var wire 1 v- BnB $end +$var wire 1 w- _carryout $end +$var wire 1 x- carryin $end +$var wire 1 y- carryout $end +$var wire 1 + invertA $end +$var wire 1 , invertB $end +$var wire 1 z- less $end +$var wire 1 {- nA $end +$var wire 1 |- nB $end +$var wire 1 }- operandA $end +$var wire 1 ~- operandB $end +$var wire 3 !. operation [2:0] $end +$var wire 1 ". result $end +$var wire 1 #. sum $end +$var wire 1 $. useCarryout $end +$var wire 8 %. values [7:0] $end +$scope module Aselect $end +$var wire 1 }- a $end +$var wire 1 {- b $end +$var wire 1 &. d0 $end +$var wire 1 '. d1 $end +$var wire 1 (. nSelect $end +$var wire 1 + select $end +$var wire 1 s- selected $end +$upscope $end +$scope module Bselect $end +$var wire 1 ~- a $end +$var wire 1 |- b $end +$var wire 1 ). d0 $end +$var wire 1 *. d1 $end +$var wire 1 +. nSelect $end +$var wire 1 , select $end +$var wire 1 v- selected $end +$upscope $end +$scope module adder $end +$var wire 1 ,. AB $end +$var wire 1 -. ACin $end +$var wire 1 .. BCin $end +$var wire 1 /. BxorCin $end +$var wire 1 s- a $end +$var wire 1 v- b $end +$var wire 1 x- carryin $end +$var wire 1 w- carryout $end +$var wire 1 #. sum $end +$upscope $end +$scope module resultSelect $end +$var wire 1 0. d0 $end +$var wire 1 1. d1 $end +$var wire 1 2. d2 $end +$var wire 1 3. d3 $end +$var wire 1 4. d4 $end +$var wire 1 5. d5 $end +$var wire 1 6. d6 $end +$var wire 1 7. d7 $end +$var wire 8 8. inputs [7:0] $end +$var wire 1 9. nselect0 $end +$var wire 1 :. nselect1 $end +$var wire 1 ;. nselect2 $end +$var wire 3 <. select [2:0] $end +$var wire 1 ". selected $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope begin $gen1[29] $end +$scope begin genblk3 $end +$scope module bitSliceALU $end +$var wire 1 =. AandB $end +$var wire 1 >. AnA $end +$var wire 1 ?. AorB $end +$var wire 1 @. AxorB $end +$var wire 1 A. BnB $end +$var wire 1 B. _carryout $end +$var wire 1 C. carryin $end +$var wire 1 D. carryout $end +$var wire 1 + invertA $end +$var wire 1 , invertB $end +$var wire 1 E. less $end +$var wire 1 F. nA $end +$var wire 1 G. nB $end +$var wire 1 H. operandA $end +$var wire 1 I. operandB $end +$var wire 3 J. operation [2:0] $end +$var wire 1 K. result $end +$var wire 1 L. sum $end +$var wire 1 M. useCarryout $end +$var wire 8 N. values [7:0] $end +$scope module Aselect $end +$var wire 1 H. a $end +$var wire 1 F. b $end +$var wire 1 O. d0 $end +$var wire 1 P. d1 $end +$var wire 1 Q. nSelect $end +$var wire 1 + select $end +$var wire 1 >. selected $end +$upscope $end +$scope module Bselect $end +$var wire 1 I. a $end +$var wire 1 G. b $end +$var wire 1 R. d0 $end +$var wire 1 S. d1 $end +$var wire 1 T. nSelect $end +$var wire 1 , select $end +$var wire 1 A. selected $end +$upscope $end +$scope module adder $end +$var wire 1 U. AB $end +$var wire 1 V. ACin $end +$var wire 1 W. BCin $end +$var wire 1 X. BxorCin $end +$var wire 1 >. a $end +$var wire 1 A. b $end +$var wire 1 C. carryin $end +$var wire 1 B. carryout $end +$var wire 1 L. sum $end +$upscope $end +$scope module resultSelect $end +$var wire 1 Y. d0 $end +$var wire 1 Z. d1 $end +$var wire 1 [. d2 $end +$var wire 1 \. d3 $end +$var wire 1 ]. d4 $end +$var wire 1 ^. d5 $end +$var wire 1 _. d6 $end +$var wire 1 `. d7 $end +$var wire 8 a. inputs [7:0] $end +$var wire 1 b. nselect0 $end +$var wire 1 c. nselect1 $end +$var wire 1 d. nselect2 $end +$var wire 3 e. select [2:0] $end +$var wire 1 K. selected $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope begin $gen1[30] $end +$scope begin genblk3 $end +$scope module bitSliceALU $end +$var wire 1 f. AandB $end +$var wire 1 g. AnA $end +$var wire 1 h. AorB $end +$var wire 1 i. AxorB $end +$var wire 1 j. BnB $end +$var wire 1 k. _carryout $end +$var wire 1 l. carryin $end +$var wire 1 m. carryout $end +$var wire 1 + invertA $end +$var wire 1 , invertB $end +$var wire 1 n. less $end +$var wire 1 o. nA $end +$var wire 1 p. nB $end +$var wire 1 q. operandA $end +$var wire 1 r. operandB $end +$var wire 3 s. operation [2:0] $end +$var wire 1 t. result $end +$var wire 1 u. sum $end +$var wire 1 v. useCarryout $end +$var wire 8 w. values [7:0] $end +$scope module Aselect $end +$var wire 1 q. a $end +$var wire 1 o. b $end +$var wire 1 x. d0 $end +$var wire 1 y. d1 $end +$var wire 1 z. nSelect $end +$var wire 1 + select $end +$var wire 1 g. selected $end +$upscope $end +$scope module Bselect $end +$var wire 1 r. a $end +$var wire 1 p. b $end +$var wire 1 {. d0 $end +$var wire 1 |. d1 $end +$var wire 1 }. nSelect $end +$var wire 1 , select $end +$var wire 1 j. selected $end +$upscope $end +$scope module adder $end +$var wire 1 ~. AB $end +$var wire 1 !/ ACin $end +$var wire 1 "/ BCin $end +$var wire 1 #/ BxorCin $end +$var wire 1 g. a $end +$var wire 1 j. b $end +$var wire 1 l. carryin $end +$var wire 1 k. carryout $end +$var wire 1 u. sum $end +$upscope $end +$scope module resultSelect $end +$var wire 1 $/ d0 $end +$var wire 1 %/ d1 $end +$var wire 1 &/ d2 $end +$var wire 1 '/ d3 $end +$var wire 1 (/ d4 $end +$var wire 1 )/ d5 $end +$var wire 1 */ d6 $end +$var wire 1 +/ d7 $end +$var wire 8 ,/ inputs [7:0] $end +$var wire 1 -/ nselect0 $end +$var wire 1 ./ nselect1 $end +$var wire 1 // nselect2 $end +$var wire 3 0/ select [2:0] $end +$var wire 1 t. selected $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope task testALU $end +$var reg 3 1/ MuxIndex [2:0] $end +$var reg 32 2/ a [31:0] $end +$var reg 32 3/ b [31:0] $end +$var reg 1 4/ expectedCarryout $end +$var reg 1 5/ expectedOverflow $end +$var reg 32 6/ expectedResult [31:0] $end +$var reg 1 7/ expectedZero $end +$var integer 32 8/ testIndex [31:0] $end +$upscope $end +$upscope $end +$enddefinitions $end +#0 +$dumpvars +b0 8/ +07/ +b10000000000000000000000000000000 6/ +15/ +04/ +b1 3/ +b1111111111111111111111111111111 2/ +b0 1/ +b0 0/ +x// +x./ +x-/ +b0xx0zx ,/ +z+/ +z*/ +z)/ +z(/ +z'/ +z&/ +x%/ +x$/ +x#/ +x"/ +x!/ +x~. +x}. +x|. +z{. +xz. +xy. +xx. +b0xx0zx w. +xv. +xu. +xt. +b0 s. +0r. +1q. +zp. +zo. +0n. +xm. +xl. +xk. +xj. +zi. +xh. +xg. +xf. +b0 e. +xd. +xc. +xb. +b0xx0zx a. +z`. +z_. +z^. +z]. +z\. +z[. +xZ. +xY. +xX. +xW. +xV. +xU. +xT. +xS. +zR. +xQ. +xP. +xO. +b0xx0zx N. +xM. +xL. +xK. +b0 J. +0I. +1H. +zG. +zF. +0E. +xD. +xC. +xB. +xA. +z@. +x?. +x>. +x=. +b0 <. +x;. +x:. +x9. +b0xx0zx 8. +z7. +z6. +z5. +z4. +z3. +z2. +x1. +x0. +x/. +x.. +x-. +x,. +x+. +x*. +z). +x(. +x'. +x&. +b0xx0zx %. +x$. +x#. +x". +b0 !. +0~- +1}- +z|- +z{- +0z- +xy- +xx- +xw- +xv- +zu- +xt- +xs- +xr- +b0 q- +xp- +xo- +xn- +b0xx0zx m- +zl- +zk- +zj- +zi- +zh- +zg- +xf- +xe- +xd- +xc- +xb- +xa- +x`- +x_- +z^- +x]- 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+#57740 +0B. +1L. +b10001 N. +b10001 a. +#57770 +0l. +0D. +b1000000000000000000000000000000z ) +#57800 +0"/ +1#/ +#57830 +0k. +1u. +b10001 w. +b10001 ,/ +#57860 +0= +0m. +b0z ) +#57890 +0< +0Q +1R +#57920 +0; +1E +b111 o +b111 $" +11 +b10001 H +b10001 [ +#57970 +1| +#58060 +1l +b1 # +b1 0 +#60000 +b1100 ( diff --git a/alu1bit.t.v b/alu1bit.t.v new file mode 100644 index 0000000..c9c8e3b --- /dev/null +++ b/alu1bit.t.v @@ -0,0 +1,126 @@ +`include "alu1bit.v" +`define ADD 3'd0 +`define SUB 3'd0 +`define XOR 3'd1 +`define SLT 3'd2 +`define AND 3'd3 +`define NOR 3'd3 +`define NAND 3'd4 +`define OR 3'd4 + +module alu1bit_test(); + reg A, B, carryin, Ainvert, Binvert, less; + reg [2:0] muxindex; + wire result,carryout; + + ALU1bit alu1bit(result, carryout, muxindex, A, B, Ainvert, Binvert,carryin, less); + + reg testAVals [29:0]; + reg testBVals [29:0]; + reg testcarryin [29:0]; + reg testAinvert[29:0]; + reg testBinvert[29:0]; + reg testless[29:0]; + reg [2:0] testmuxindex[29:0]; + reg testresults [29:0]; + reg testcarryouts [29:0]; + + task testALU; + input cin,Ainv,Binv,Less,a, b, expectedOut, expectedOverflow; + input [2:0] MuxIndex; + input integer testIndex; + begin + A=a; B=b; carryin=cin; Ainvert=Ainv; Binvert=Binv;less=Less; muxindex=MuxIndex; #5000 + if (result == expectedOut && carryout == expectedOverflow) + $display("Test %d succeeded", testIndex); + else + $display("Test %d failed", testIndex); + $display("Operation: %d, Invert A: %b, Invert B: %b, Inputs: %b and %b, Carry in: %b, Output: %b, Carry out: %b", muxindex, Ainv, Binv, a, b, carryin, result, carryout); + $display("\n"); + end + endtask + + integer i; + + initial begin + + testAVals[0] = 0; testBVals[0] = 0; testcarryin[0] = 0; testAinvert[0]=0; testBinvert[0] = 0; testless[0] = 0; testmuxindex[0] = `ADD; testresults[0] = 0; testcarryouts[0] = 0; + + testAVals[1] = 0; testBVals[1] = 1; testcarryin[1] = 0; testAinvert[1]=0; testBinvert[1] = 0; testless[1] = 0; testmuxindex[1] = `ADD; testresults[1] = 1; testcarryouts[1] = 0; + + testAVals[2] = 1; testBVals[2] = 1; testcarryin[2] = 0; testAinvert[2]=0; testBinvert[2] = 0; testless[2] = 0; testmuxindex[2] = `ADD; testresults[2] = 0; testcarryouts[2] = 1; + + testAVals[3] = 1; testBVals[3] = 1; testcarryin[3] = 1; testAinvert[3]=0; testBinvert[3] = 0; testless[3] = 0; testmuxindex[3] = `ADD; testresults[3] = 1; testcarryouts[3] = 1; + + + + testAVals[4] = 0; testBVals[4] = 0; testcarryin[4] = 1; testAinvert[4]=0; testBinvert[4] = 1; testless[4] = 0; testmuxindex[4] = `SUB; testresults[4] = 0; testcarryouts[4] = 1; + + testAVals[5] = 1; testBVals[5] = 0; testcarryin[5] = 1; testAinvert[5]=0; testBinvert[5] = 1; testless[5] = 0; testmuxindex[5] = `SUB; testresults[5] = 1; testcarryouts[5] = 1; + + testAVals[6] = 0; testBVals[6] = 1; testcarryin[6] = 1; testAinvert[6]=0; testBinvert[6] = 1; testless[6] = 0; testmuxindex[6] = `SUB; testresults[6] = 1; testcarryouts[6] = 0; + + testAVals[7] = 1; testBVals[7] = 1; testcarryin[7] = 1; testAinvert[7]=0; testBinvert[7] = 1; testless[7] = 0; testmuxindex[7] = `SUB; testresults[7] = 0; testcarryouts[7] = 1; + + + + testAVals[8] = 0; testBVals[8] = 0; testcarryin[8] = 0; testAinvert[8]=0; testBinvert[8] = 0; testless[8] = 0; testmuxindex[8] = `XOR; testresults[8] = 0; testcarryouts[8] = 0; + + testAVals[9] = 0; testBVals[9] = 1; testcarryin[9] = 0; testAinvert[9]=0; testBinvert[9] = 0; testless[9] = 0; testmuxindex[9] = `XOR; testresults[9] = 1; testcarryouts[9] = 0; + + testAVals[10] = 1; testBVals[10] = 0; testcarryin[10] = 0; testAinvert[10]=0; testBinvert[10] = 0; testless[10] = 0; testmuxindex[10] = `XOR; testresults[10] = 1; testcarryouts[10] = 0; + + testAVals[11] = 1; testBVals[11] = 1; testcarryin[11] = 0; testAinvert[11]=0; testBinvert[11] = 0; testless[11] = 0; testmuxindex[11] = `XOR; testresults[11] = 0; testcarryouts[11] = 0; + + + + testAVals[12] = 1; testBVals[12] = 1; testcarryin[12] = 1; testAinvert[12]=0; testBinvert[12] = 0; testless[12] = 0; testmuxindex[12] = `SLT; testresults[12] = 0; testcarryouts[12] = 0; + + testAVals[13] = 0; testBVals[13] = 0; testcarryin[13] = 0; testAinvert[13]=0; testBinvert[13] = 0; testless[13] = 1; testmuxindex[13] = `SLT; testresults[13] = 1; testcarryouts[13] = 0; + + + + testAVals[14] = 0; testBVals[14] = 0; testcarryin[14] = 0; testAinvert[14]=0; testBinvert[14] = 0; testless[14] = 0; testmuxindex[14] = `AND; testresults[14] = 0; testcarryouts[14] = 0; + + testAVals[15] = 0; testBVals[15] = 1; testcarryin[15] = 0; testAinvert[15]=0; testBinvert[15] = 0; testless[15] = 0; testmuxindex[15] = `AND; testresults[15] = 0; testcarryouts[15] = 0; + + testAVals[14] = 1; testBVals[16] = 0; testcarryin[16] = 0; testAinvert[16]=0; testBinvert[16] = 0; testless[16] = 0; testmuxindex[16] = `AND; testresults[16] = 0; testcarryouts[16] = 0; + + testAVals[17] = 1; testBVals[17] = 1; testcarryin[17] = 0; testAinvert[17]=0; testBinvert[17] = 0; testless[17] = 0; testmuxindex[17] = `AND; testresults[17] = 1; testcarryouts[17] = 0; + + + + testAVals[18] = 0; testBVals[18] = 0; testcarryin[18] = 0; testAinvert[18]=1; testBinvert[18] = 1; testless[18] = 0; testmuxindex[18] = `NAND; testresults[18] = 1; testcarryouts[18] = 0; + + testAVals[19] = 0; testBVals[19] = 1; testcarryin[19] = 0; testAinvert[19]=1; testBinvert[19] = 1; testless[19] = 0; testmuxindex[19] = `NAND; testresults[19] = 1; testcarryouts[19] = 0; + + testAVals[20] = 1; testBVals[20] = 0; testcarryin[20] = 0; testAinvert[20]=1; testBinvert[20] = 1; testless[20] = 0; testmuxindex[20] = `NAND; testresults[20] = 1; testcarryouts[20] = 0; + + testAVals[21] = 1; testBVals[21] = 1; testcarryin[21] = 0; testAinvert[21]=1; testBinvert[21] = 1; testless[21] = 0; testmuxindex[21] = `NAND; testresults[21] = 0; testcarryouts[21] = 0; + + + + testAVals[22] = 0; testBVals[22] = 0; testcarryin[22] = 0; testAinvert[22]=1; testBinvert[22] = 1; testless[22] = 0; testmuxindex[22] = `NOR; testresults[22] = 1; testcarryouts[22] = 0; + + testAVals[23] = 0; testBVals[23] = 1; testcarryin[23] = 0; testAinvert[23]=1; testBinvert[23] = 1; testless[23] = 0; testmuxindex[23] = `NOR; testresults[23] = 0; testcarryouts[23] = 0; + + testAVals[24] = 1; testBVals[24] = 0; testcarryin[24] = 0; testAinvert[24]=1; testBinvert[24] = 1; testless[24] = 0; testmuxindex[24] = `NOR; testresults[24] = 0; testcarryouts[24] = 0; + + testAVals[25] = 1; testBVals[25] = 1; testcarryin[25] = 0; testAinvert[25]=1; testBinvert[25] = 1; testless[25] = 0; testmuxindex[25] = `NOR; testresults[25] = 0; testcarryouts[25] = 0; + + + + testAVals[26] = 0; testBVals[26] = 0; testcarryin[26] = 0; testAinvert[26]=0; testBinvert[26] = 0; testless[26] = 0; testmuxindex[26] = `OR; testresults[26] = 0; testcarryouts[26] = 0; + + testAVals[27] = 0; testBVals[27] = 1; testcarryin[27] = 0; testAinvert[27]=0; testBinvert[27] = 0; testless[27] = 0; testmuxindex[27] = `OR; testresults[27] = 1; testcarryouts[27] = 0; + + testAVals[28] = 1; testBVals[28] = 0; testcarryin[28] = 0; testAinvert[28]=0; testBinvert[28] = 0; testless[28] = 0; testmuxindex[28] = `OR; testresults[28] = 1; testcarryouts[28] = 0; + + testAVals[29] = 1; testBVals[29] = 1; testcarryin[29] = 0; testAinvert[29]=0; testBinvert[29] = 0; testless[29] = 0; testmuxindex[29] = `OR; testresults[29] = 1; testcarryouts[29] = 0; + + + for (i = 0; i < 30; i = i + 1) begin + testALU(testcarryin[i],testAinvert[i],testBinvert[i],testless[i],testAVals[i], testBVals[i], testresults[i], testcarryouts[i], testmuxindex[i], i); + end + end +endmodule \ No newline at end of file diff --git a/alu1bit.v b/alu1bit.v new file mode 100644 index 0000000..8be8f75 --- /dev/null +++ b/alu1bit.v @@ -0,0 +1,114 @@ +`include "gates.v" +`include "adder1bit.v" +`include "mux.v" + +module ALU1bit +( + output result, + output carryout, + input[2:0] operation, + input operandA, + input operandB, + input invertA, + input invertB, + input carryin, + input less +); + + wire nA; + wire nB; + wire AnA; + wire BnB; + wire AorB; + wire AandB; + wire AxorB; + wire sum; + wire useCarryout; + wire _carryout; + wire[7:0] values; + + `NOT(nA, operandA); + `NOT(nB, operandB); + mux2to1 Aselect(AnA, operandA, nA, invertA); + mux2to1 Bselect(BnB, operandB, nB, invertB); + `AND(AandB, AnA, BnB); + `OR(AorB, AnA, BnB); + `XOR(AxorB, operandA, operandB); + adder1bit adder(sum, _carryout, AnA, BnB, carryin); + + `NOR(useCarryout, operation[0], operation[2]); + `AND(carryout, _carryout, useCarryout); + + assign values[0] = sum; + assign values[1] = AxorB; + assign values[2] = less; + assign values[3] = AandB; + assign values[4] = AorB; + assign values[5] = 0; + assign values[6] = 0; + assign values[7] = 0; + + mux8to1 resultSelect(result, values, operation); + +endmodule + + +module ALU1bitMSB +( + output result, + output carryout, + output overflow, + output set, + input[2:0] operation, + input operandA, + input operandB, + input invertA, + input invertB, + input carryin, + input less +); + + wire nA; + wire nB; + wire AnA; + wire BnB; + wire AorB; + wire AandB; + wire AxorB; + wire sum; + wire useCarryout; + wire _carryout; + wire useOverflow; + wire _overflow; + wire[7:0] values; + + `NOT(nA, operandA); + `NOT(nB, operandB); + mux2to1 Aselect(AnA, operandA, nA, invertA); + mux2to1 Bselect(BnB, operandB, nB, invertB); + `AND(AandB, AnA, BnB); + `OR(AorB, AnA, BnB); + `XOR(AxorB, operandA, operandB); + adder1bit adder(sum, _carryout, AnA, BnB, carryin); + + `NOR3(useCarryout, operation[0], operation[1], operation[2]); + `AND(carryout, _carryout, useCarryout); + + assign values[0] = sum; + assign values[1] = AxorB; + assign values[2] = less; + assign values[3] = AandB; + assign values[4] = AorB; + assign values[5] = 0; + assign values[6] = 0; + assign values[7] = 0; + + mux8to1 resultSelect(result, values, operation); + + assign set = sum; + `XOR(_overflow, carryout, carryin); + + `NOR3(useOverflow, operation[0], operation[1], operation[2]); + `AND(overflow, _overflow, useOverflow); + +endmodule \ No newline at end of file diff --git a/assets/1bitALU-MSB.png b/assets/1bitALU-MSB.png new file mode 100644 index 0000000..56c4180 Binary files /dev/null and b/assets/1bitALU-MSB.png differ diff --git a/assets/1bitALU.png b/assets/1bitALU.png new file mode 100644 index 0000000..3b0b5df Binary files /dev/null and b/assets/1bitALU.png differ diff --git a/assets/32bitALU.png b/assets/32bitALU.png new file mode 100644 index 0000000..1e37cd6 Binary files /dev/null and b/assets/32bitALU.png differ diff --git a/assets/timing.png b/assets/timing.png new file mode 100644 index 0000000..775f365 Binary files /dev/null and b/assets/timing.png differ diff --git a/gates.v b/gates.v new file mode 100644 index 0000000..35e6448 --- /dev/null +++ b/gates.v @@ -0,0 +1,8 @@ +`define AND and #30 +`define OR or #30 +`define NOT not #10 +`define XOR xor #30 +`define NOR nor #20 +`define NOR3 nor #30 +`define AND4 and #50 +`define OR8 or #90 diff --git a/mux.v b/mux.v new file mode 100644 index 0000000..874517b --- /dev/null +++ b/mux.v @@ -0,0 +1,44 @@ +`include "gates.v" + +module mux2to1 +( + output selected, + input a, + input b, + input select +); + + wire d0, d1, nSelect; + + `NOT(nSelect, select); + `AND(d0, a, nSelect); + `AND(d1, b, select); + `OR(selected, d0, d1); + +endmodule + + +module mux8to1 +( + output selected, + input[7:0] inputs, + input[2:0] select +); + +wire nselect0,nselect1,nselect2; +wire d0, d1, d2, d3, d4, d5, d6, d7; + +`NOT(nselect0, select[0]); +`NOT(nselect1, select[1]); +`NOT(nselect2, select[2]); +`AND4(d0, inputs[0], nselect2, nselect1, nselect0); +`AND4(d1, inputs[1], nselect2, nselect1, select[0]); +`AND4(d2, inputs[2], nselect2, select[1], nselect0); +`AND4(d3, inputs[3], nselect2, select[1], select[0]); +`AND4(d4, inputs[4], select[2], nselect1, nselect0); +`AND4(d5, inputs[5], select[2], nselect1, select[0]); +`AND4(d6, inputs[6], select[2], select[1], nselect0); +`AND4(d7, inputs[7], select[2], select[1], select[0]); +`OR8(selected,d0,d1,d2,d3,d4,d5,d6,d7); + +endmodule diff --git a/report.md b/report.md new file mode 100644 index 0000000..d231a54 --- /dev/null +++ b/report.md @@ -0,0 +1,54 @@ +***Computer Architecture*** +***Lab 1 Report*** +***Joseph Lee and Sam Myers*** +***10/12/2017*** + +### Implementation +We implemented our ALU using a bitslice approach in which all but the most significant bit are identical slices (the MSB is a slightly modified version of every other bitslice ALU). The carry-ins for each bit slice are hooked up to the previous carry-outs, as one would expect. The block diagrams below (figures 1 and 2) show our bitslice implementations. + +One interesting thing that we did is we have two flags internal to each bit in the slice that allows us to invert one or both of the operands. This gives us the flexibility to implement multiple operations with the same gates using DeMorgan’s law (NAND from OR, NOR from AND) as well as subtraction and SLT by inverting only the second input. + +We implemented SLT by having an extra “less” control signal that feeds directly into the corresponding terminal of the 1-bit ALU multiplexer. For every bit but the least significant, this signal is hard-coded to 0; the ALU for the most significant bit outputs a “set” signal directly from its 1-bit adder that loops back into the least significant bit’s “less” input. Since the control signals for SLT are the same as for subtraction, the “set” signal corresponds to the most significant bit of the difference between the inputs. + +Another interesting implementation approach that allowed us to have our adder always connected to the inputs without incorrectly raising overflow, carryout, or zero flags is that we included a small logic block to determine if the adder was being used (NOR the bits of the operation signal, since addition and subtraction both use 000) and only output those flags if appropriate. + +![Figure 1](assets/1bitALU.png) +*Figure 1: Block diagram of the 1-bit ALU used for bits 0-30.* + +![Figure 2](assets/1bitALU-MSB.png) +*Figure 2: Block diagram of the 1-bit ALU used for bit 31.* + +![Figure 3](assets/32bitALU.png) +*Figure 3: Block diagram of the 32-bit ALU.* + +### Test Results +For our 1 bit ALU testbench we conducted pseudo-exhaustive testing. We quickly determined that truly exhaustive testing would not be feasible or necessary based on the total number of input bits of each 1-bit ALU. Each 1-bit ALU has inputs A, B, invertA, invertB, carryin, less, and a 3 bit operation control signal meaning that a truly exhaustive test would require 2^7 or 128 test cases. However, it is readily apparent that if we verify that invertA and invertB do in fact invert A and B respectively then it is not necessary to test them in every case. This reduced the number of necessary tests to 32. We further reduced the number of tests by abbreviating our test cases for the SLT function since SLT is a function that really does not make much sense in the context of a single bit. Since some of our logic functions rely on invertA and invertB working properly, separately testing invertA and invertB was not necessary reducing our total number of test cases to 30, a much more reasonable number. + +For our 32-bit ALU test bench we performed mostly edge case testing and just enough tests to convince ourselves that it was working as intended. For our ADD operation this meant testing a scenario that overflowed and contained a carryout as well as a simple regular addition. For our overflow case we chose to add 0x7FFFFFFF with 0x1 as this was a simple case that would validate our overflow and carryout behavior. For the normal addition we just tested adding 100 to 475. For our subtract we decided to test one case in which the result was negative and one in which the result was positive. For this we just used simple hex numbers for simplification. For our logic functions we decided that one test case for each was sufficient since we had exhaustively tested the logic portion of the 1-bit ALU. For these tests we again just used simple hex numbers of 0s and Fs just to simplify the expected results. To test our SLT function we decided that there were 3 important cases: A < B, A > B and A = B and that one of each case would be sufficient to convince ourselves that SLT was working properly. We just random decimal numbers to implement these cases. + +Our test bench caught quite a few flaws in our implementation. Initially we were seeing an undefined value on most of our outputs. We quickly traced this back to missing brackets in our definition of our 8 to 1 multiplexer. We also found that our test cases caught a simple (but at first hard to find) bug in our implementation of NAND. This case was particularly cool in that our approach to finding it was to create a truth table for the output of “NAND”. Our truth table had the exact behavior of NOR. Immediately this prompted us to look for our OR gate. Sure enough we had accidentally copied and pasted `AND there instead of OR. Our test bench also caught a lot of errors around improper handling of the flags where carryout would sometimes be high when performing a logic function. We fixed this by adding our internal flags useCarryout and useOverflow. + +We also ran into cases where in the development process we added specific test cases to better understand the results we were getting. One example of this is that our adder was returning about half undefined values and the rest were defined (and correct). We tried plugging in a few different values for the operands to look for any patterns in the bug. This led us to eventually find that the bigger the result was supposed to be, the more bits were undefined. We eventually traced this back to a timing problem - we were not waiting long enough before reading our output state. +### Timing Analysis +#### Timing analysis of ADD function: +Based on our GTKwave analysis the worst case propagation delay of our add function is 3060 ticks. This seems reasonable as the add function is serial meaning that the propagation delay of each bit adds to the total propagation delay. +#### Timing analysis of Subtract function: +Since our subtract is implemented using our adder and an inverter, the worst case propagation delay for the subtract function would be 3070 ticks. We could verify this using simulation if we set up a worst case test in terms of propagation delay (something in which the result is 0xFFFFFFFF. (note, in our initial testbench we accidently used 4 character hexadecimal numbers which correlates to 16 bits instead of 32. This is the reason why we do not currently have a subtract worst case test case. We could implement this by doing 0xFFFFFFFF - 0). +#### Timing analysis of XOR function: +Since our XOR function is a parallel operation (as are all of the basic logic functions) it makes sense that our propagation delay is significantly shorter at 150 ticks. +#### Timing analysis of AND function: +Our AND function also has a propagation delay of 150 ticks which makes sense given that its implementation is very similar to XOR. +#### Timing analysis of NAND function: +Our NAND propagation delay is 240 ticks which makes sense given that our implementation is to invert both operands and pass into an OR gate. We get additional propagation delay from the multiplexer that selects the inverted operands. In hindsight we should have implemented these the opposite way so that NAND and NOR were our basic gates and the other logic functions implemented by manipulating the inputs. +#### Timing analysis of NOR function: +Our NOR propagation delay was also 240 ticks which makes sense since it is implemented in the same way that NAND is implemented. +#### Timing analysis of OR function: +Our OR propagation delay is 240 ticks as well. We wanted to look at this analytically taking a deeper look at our implementation since our intuition said that the OR propagation delay should be more similar to AND and OR, but we ran out of time. +#### Timing analysis of SLT function: +Our SLT propagation delay was 3070 ticks which makes sense as it is effectively implemented as a subtract operation. + +![Figure 4](assets/timing.png) +*Figure 4: Waveforms showing the time delay for ALU operations.* + +### Work Plan Reflection +Our work plan was actually fairly accurate in predicting the total time spent. The exact distribution of time did vary slightly between our plan and what we actually did - mostly due to parallelization that we did not anticipate being possible (we were able to write the 32-bit implementation in parallel with our 1 bit bit-slice). Our test bench for the 1-bit ALU ended up taking significantly longer than the full 32-bit test bench (about 3 hours for the 1-bit and an hour and half for the 32-bit). This was due to the fact that the 1-bit test bench needed to be more exhaustive, that more of the control lines were exposed and had to be manually set. Also most of the code for the 1-bit ALU test bench was reusable in the 32-bit test bench implementation, speeding up the development time. diff --git a/work_plan.md b/work_plan.md new file mode 100644 index 0000000..a32610f --- /dev/null +++ b/work_plan.md @@ -0,0 +1,36 @@ +**Implementation Planning - 1 hour** + +* Basic implementation planning focussing specifically on the SLT functionality and how to get things to work using a bit slice approach. + +**1-bit ALU implementation - 3 hours** + +* Implement add/subtract - 1 hour + +* Implement SLT - 1 hour + +* Add logic functions - 1 hour + +**1-bit test bench - 1 hour** + +Test bench to test functionality of 1 bit ALU slice. Probably not exhaustive since there are a lot of possible combinations, but we will cover all the edge cases and a random sampling of middle cases. + +**Chain together 1-bit ALUs into 32-bit, add control logic - 1 hour** + +Chain our bit slices together into a 32 bit ALU, add control logic to handle 32 bit inputs more cleanly + +**32-bit test bench - 2 hours** + +Write a testbench to test functionally of our 32 bit ALU. Definitely not exhaustively so we will have to think about relevant edge cases. + +**Lab report - 3 hours, 10 minutes** + +* Implementation & results - 2 hours + +* Timing analysis - 1 hour + +* Work plan reflection - 10 minutes + +**_Total - 11 hours, 10 minutes_** + +(split up between the two of us) +