From 79becf4b626adeda1925fa9038da507aded33407 Mon Sep 17 00:00:00 2001 From: Bryan Werth Date: Tue, 24 Oct 2017 02:51:08 -0400 Subject: [PATCH 01/41] Finished the Work Plan --- work_plan.txt | 7 +++++++ 1 file changed, 7 insertions(+) create mode 100644 work_plan.txt diff --git a/work_plan.txt b/work_plan.txt new file mode 100644 index 0000000..db70b84 --- /dev/null +++ b/work_plan.txt @@ -0,0 +1,7 @@ +Input Conditioner First Pass - done 10/24 - 2 hours +Shift Register First Pass - done 10/24 - 2 hours +Implement Midpoint on FPGA - done 10/24 - 2 hours +Test Benches for Input Conditioner and Shift Register - done 10/27 - 2 hours +SPI Memory First Pass - done 10/29 - 1 hour +Final SPI Memory Testing - done 10/30 - 1.5 hours +Final Report - done 10/31 - 2 hours \ No newline at end of file From b7b6ed4ee40ae56b7d00b177a683a12331abbf0f Mon Sep 17 00:00:00 2001 From: Bryan Werth Date: Tue, 24 Oct 2017 18:42:01 -0400 Subject: [PATCH 02/41] Finished Input Conditioner First Pass --- inputconditioner.v | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/inputconditioner.v b/inputconditioner.v index 736a866..5c49b70 100644 --- a/inputconditioner.v +++ b/inputconditioner.v @@ -20,8 +20,17 @@ output reg negativeedge // 1 clk pulse at falling edge of conditioned reg[counterwidth-1:0] counter = 0; reg synchronizer0 = 0; reg synchronizer1 = 0; + reg conditioned1 = 0; always @(posedge clk ) begin + if(conditioned == 0 && conditioned1 == 1) begin + negativeedge = 1; + end else if (conditioned == 1 && conditioned1 == 0) begin + positiveedge = 1; + end else if (positiveedge == 1 || negativeedge == 1) begin + positiveedge = 0; + negativeedge = 0; + end if(conditioned == synchronizer1) counter <= 0; else begin @@ -34,5 +43,6 @@ output reg negativeedge // 1 clk pulse at falling edge of conditioned end synchronizer0 <= noisysignal; synchronizer1 <= synchronizer0; + conditioned1 <= conditioned; end endmodule From 389fe5a562b140c4ad790d6113996dbacab8e734 Mon Sep 17 00:00:00 2001 From: Wilson Tang Date: Tue, 24 Oct 2017 19:13:02 -0400 Subject: [PATCH 03/41] conditioner typo --- inputconditioner.v | 19 +++++++++---------- 1 file changed, 9 insertions(+), 10 deletions(-) diff --git a/inputconditioner.v b/inputconditioner.v index 5c49b70..165a183 100644 --- a/inputconditioner.v +++ b/inputconditioner.v @@ -27,19 +27,18 @@ output reg negativeedge // 1 clk pulse at falling edge of conditioned negativeedge = 1; end else if (conditioned == 1 && conditioned1 == 0) begin positiveedge = 1; - end else if (positiveedge == 1 || negativeedge == 1) begin + end else if (positiveedge == 1 || negativeedge == 1) begin positiveedge = 0; negativeedge = 0; - end - if(conditioned == synchronizer1) + end + if(conditioned == synchronizer1) + counter <= 0; + else begin + if( counter == waittime) begin counter <= 0; - else begin - if( counter == waittime) begin - counter <= 0; - conditioned <= synchronizer1; - end - else - counter <= counter+1; + conditioned <= synchronizer1; + end else begin + counter <= counter+1; end synchronizer0 <= noisysignal; synchronizer1 <= synchronizer0; From 004d4325bdb9339b915860193ad107fbeefa85ec Mon Sep 17 00:00:00 2001 From: Joseph Lee Date: Tue, 24 Oct 2017 20:07:51 -0400 Subject: [PATCH 04/41] Finished shiftregister.v --- shiftregister.v | 18 +++++++++++++++++- 1 file changed, 17 insertions(+), 1 deletion(-) diff --git a/shiftregister.v b/shiftregister.v index b4ec057..6c26075 100644 --- a/shiftregister.v +++ b/shiftregister.v @@ -19,7 +19,23 @@ output serialDataOut // Positive edge synchronized ); reg [width-1:0] shiftregistermem; + always @(posedge clk) begin - // Your Code Here + + if(parallelLoad==1) begin + // load the register with parallelDataIn + shiftregistermem <= parallelDataIn; + end + + else if(parallelLoad==0) begin + if(peripheralClkEdge==1) begin + //grab the MSB as SDO and then shift everything over 1 place + serialDataOut <= shiftregistermem[width-1]; + shiftregistermem<={shiftregistermem[width-2:0],serialDataIn}; + end + end + //parallelDataOut is just the current state of the register + parallelDataOut <= shiftregistermem; + end endmodule From 3091e5c7ecd814f1791fa6a0b11bc98373642a6c Mon Sep 17 00:00:00 2001 From: Joseph Lee Date: Tue, 24 Oct 2017 20:15:21 -0400 Subject: [PATCH 05/41] Finished shiftregister.v for real now --- shiftregister.v | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/shiftregister.v b/shiftregister.v index 6c26075..dbadfa5 100644 --- a/shiftregister.v +++ b/shiftregister.v @@ -14,8 +14,8 @@ input peripheralClkEdge, // Edge indicator input parallelLoad, // 1 = Load shift reg with parallelDataIn input [width-1:0] parallelDataIn, // Load shift reg in parallel input serialDataIn, // Load shift reg serially -output [width-1:0] parallelDataOut, // Shift reg data contents -output serialDataOut // Positive edge synchronized +output reg [width-1:0] parallelDataOut, // Shift reg data contents +output reg serialDataOut // Positive edge synchronized ); reg [width-1:0] shiftregistermem; From ea3232938f1c0ae08c6e97781cc374cbb0566b71 Mon Sep 17 00:00:00 2001 From: CompArch Date: Tue, 24 Oct 2017 20:44:14 -0400 Subject: [PATCH 06/41] midpt.v --- midpoint.v | 115 +++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 115 insertions(+) create mode 100644 midpoint.v diff --git a/midpoint.v b/midpoint.v new file mode 100644 index 0000000..60885e3 --- /dev/null +++ b/midpoint.v @@ -0,0 +1,115 @@ +//-------------------------------------------------------------------------------- +// Wrapper for Lab 2: Midpoint.v +// +// Rationale: +// The ZYBO board has 4 buttons, 4 switches, and 4 LEDs. But if we want to +// show the results of a 4-bit add operation, we will need at least 6 LEDs! +// +// This wrapper module allows for 4-bit operands to be loaded in one at a +// time, and multiplexes the LEDs to show the SUM and carryout/overflow at +// different times. +// +// Your job: +/ +// +// Usage: +// btn0 - load parallel load into input conditioner -> shift register +// btn1 - show first 4 bits +// btn2 - show last 4 bits +// sw0 - Serial In Input into input conditioner -> shift register +// sw1 - Clk Edge +// +// Note: Buttons, switches, and LEDs have the least-significant (0) position +// on the right. +//-------------------------------------------------------------------------------- + +`timescale 1ns / 1ps + + +//-------------------------------------------------------------------------------- +// Basic building block modules +//-------------------------------------------------------------------------------- + +// JK flip-flop +module jkff1 +( + input trigger, + input j, + input k, + output reg q +); + always @(posedge trigger) begin + if(j && ~k) begin + q <= 1'b1; + end + else if(k && ~j) begin + q <= 1'b0; + end + else if(k && j) begin + q <= ~q; + end + end +endmodule + +// Two-input MUX with parameterized bit width (default: 1-bit) +module mux2 #( parameter W = 1 ) +( + input[W-1:0] in0, + input[W-1:0] in1, + input sel, + output[W-1:0] out +); + // Conditional operator - http://www.verilog.renerta.com/source/vrg00010.htm + assign out = (sel) ? in1 : in0; +endmodule + + +//-------------------------------------------------------------------------------- +// Main Lab 0 wrapper module +// Interfaces with switches, buttons, and LEDs on ZYBO board. Allows for two +// 4-bit operands to be stored, and two results to be alternately displayed +// to the LEDs. +//-------------------------------------------------------------------------------- + +module midpoint +( + input clk, + input [1:0] sw, + input [2:0] btn, + output [3:0] led +); + + reg[7:0] parallaData = 8`b11000011; //Assign default parallel in + wire[3:0] res0, res1; // + wire[7:0] shiftregister; // Current Shift Register Values + wire res_sel; // Select between display options + wire parallelslc; // select parallel input + wire serialin; // binary input for serial input + wire serialclk; // clk edge for serial input + + + // Capture button input to switch which MUX input to LEDs + jkff1 src_sel(.trigger(clk), .j(btn[2]), .k(btn[1]), .q(res_sel)); + mux2 #(4) output_select(.in0(res0), .in1(res1), .sel(res_sel), .out(led)); + + + //Map to input conditioner + inputconditioner parallel(.noisysignal(btn[0]),.clk(clk),.negativeedge(parallelslc)); + inputconditioner serialinputs(.noisysignal(sw[0]),.clk(clk),.conditioned(serialin)); + inputconditioner serialclocks(.noisysignal(sw[1]),.clk(clk),.positiveedge(serialclk)); + + //Input into Shift Register + shiftregister shifted(.clk(clk),.peripheralClkEdge(serialclk),.parallelLoad(parallelslc),.parallelDataIn(parallelData),.serialDataIn(serialin),.parallelDataOut(shiftregister)); + + + // Assign bits of shiftregister to appropriate display boxes + assign res0[0] = shiftregister[0]; + assign res0[1] = shiftregister[1]; + assign res0[2] = shiftregister[2]; + assign res0[3] = shiftregister[3]; + assign res1[0] = shiftregister[4]; + assign res1[1] = shiftregister[5]; + assign res1[2] = shiftregister[6]; + assign res1[3] = shiftregister[7]; + +endmodule From bb577e34ffdb068ece4751ebd9ed70f4b9bbdbcf Mon Sep 17 00:00:00 2001 From: Bryan Werth Date: Tue, 24 Oct 2017 20:50:29 -0400 Subject: [PATCH 07/41] Added Test Benches --- inputconditioner.t.v | 11 ++++++++--- shiftregister.t.v | 7 ++++++- 2 files changed, 14 insertions(+), 4 deletions(-) diff --git a/inputconditioner.t.v b/inputconditioner.t.v index 2814163..fe23005 100644 --- a/inputconditioner.t.v +++ b/inputconditioner.t.v @@ -22,8 +22,13 @@ module testConditioner(); always #10 clk=!clk; // 50MHz Clock initial begin - // Your Test Code - // Be sure to test each of the three conditioner functions: - // Synchronization, Debouncing, Edge Detection + pin = 0; #50 + pin = 1; #100 + pin = 0; #100 + pin = 1; #150 + pin = 0; #30 + pin = 1; #60 + pin = 0; #30 + end endmodule diff --git a/shiftregister.t.v b/shiftregister.t.v index abe5b48..9c1964e 100644 --- a/shiftregister.t.v +++ b/shiftregister.t.v @@ -21,8 +21,13 @@ module testshiftregister(); .parallelDataOut(parallelDataOut), .serialDataOut(serialDataOut)); + initial clk=0; + always #10 clk=!clk; + initial begin - // Your Test Code + parallelLoad = 1; parallelDataIn = 8'b10000000; #100 + serialDataIn = 1; peripheralClkEdge = 1; parallelLoad = 0; #20 + serialDataIn = 0; #200 end endmodule From b6575c4fab9e9708a1d44b964b228f2286d1429a Mon Sep 17 00:00:00 2001 From: Bryan Werth Date: Tue, 24 Oct 2017 20:58:46 -0400 Subject: [PATCH 08/41] Fixed Test Benches --- inputconditioner.t.v | 1 + shiftregister.t.v | 1 + 2 files changed, 2 insertions(+) diff --git a/inputconditioner.t.v b/inputconditioner.t.v index fe23005..b70ef43 100644 --- a/inputconditioner.t.v +++ b/inputconditioner.t.v @@ -1,6 +1,7 @@ //------------------------------------------------------------------------ // Input Conditioner test bench //------------------------------------------------------------------------ +`include "inputconditioner.v" module testConditioner(); diff --git a/shiftregister.t.v b/shiftregister.t.v index 9c1964e..521c525 100644 --- a/shiftregister.t.v +++ b/shiftregister.t.v @@ -1,6 +1,7 @@ //------------------------------------------------------------------------ // Shift Register test bench //------------------------------------------------------------------------ +`include "shiftregister.v" module testshiftregister(); From dd3f8b63ef5dc936c9c69344cbe6d044fb674036 Mon Sep 17 00:00:00 2001 From: Bryan Werth Date: Tue, 24 Oct 2017 21:31:00 -0400 Subject: [PATCH 09/41] Fixed Test Benches --- inputconditioner.t.v | 26 ++++++++++++++------------ shiftregister.t.v | 13 ++++++++----- 2 files changed, 22 insertions(+), 17 deletions(-) diff --git a/inputconditioner.t.v b/inputconditioner.t.v index b70ef43..8fb0918 100644 --- a/inputconditioner.t.v +++ b/inputconditioner.t.v @@ -5,7 +5,7 @@ module testConditioner(); - reg clk; + reg clk = 0; reg pin; wire conditioned; wire rising; @@ -15,21 +15,23 @@ module testConditioner(); .noisysignal(pin), .conditioned(conditioned), .positiveedge(rising), - .negativeedge(falling)) - + .negativeedge(falling)); // Generate clock (50MHz) - initial clk=0; - always #10 clk=!clk; // 50MHz Clock + initial begin + forever begin + clk = !clk; #10; + end + end initial begin - pin = 0; #50 - pin = 1; #100 - pin = 0; #100 - pin = 1; #150 - pin = 0; #30 - pin = 1; #60 - pin = 0; #30 + pin = 0; #50; + pin = 1; #100; + pin = 0; #100; + pin = 1; #150; + pin = 0; #30; + pin = 1; #60; + pin = 0; #30; end endmodule diff --git a/shiftregister.t.v b/shiftregister.t.v index 521c525..663ed0f 100644 --- a/shiftregister.t.v +++ b/shiftregister.t.v @@ -22,13 +22,16 @@ module testshiftregister(); .parallelDataOut(parallelDataOut), .serialDataOut(serialDataOut)); - initial clk=0; - always #10 clk=!clk; + initial begin + forever begin + clk = !clk; #10; + end + end initial begin - parallelLoad = 1; parallelDataIn = 8'b10000000; #100 - serialDataIn = 1; peripheralClkEdge = 1; parallelLoad = 0; #20 - serialDataIn = 0; #200 + parallelLoad = 1; parallelDataIn = 8'b10000000; #100; + serialDataIn = 1; peripheralClkEdge = 1; parallelLoad = 0; #20; + serialDataIn = 0; #200; end endmodule From 6ee1a5aaaba7675f3aedbbdae00e1df89f3e93a2 Mon Sep 17 00:00:00 2001 From: Bryan Werth Date: Tue, 24 Oct 2017 21:32:50 -0400 Subject: [PATCH 10/41] Fixed inputconditioner --- inputconditioner.v | 33 +++++++++++++++++---------------- 1 file changed, 17 insertions(+), 16 deletions(-) diff --git a/inputconditioner.v b/inputconditioner.v index 165a183..71381e0 100644 --- a/inputconditioner.v +++ b/inputconditioner.v @@ -6,16 +6,16 @@ //------------------------------------------------------------------------ module inputconditioner -( -input clk, // Clock domain to synchronize input to -input noisysignal, // (Potentially) noisy input signal -output reg conditioned, // Conditioned output signal -output reg positiveedge, // 1 clk pulse at rising edge of conditioned -output reg negativeedge // 1 clk pulse at falling edge of conditioned -); +(clk,noisysignal,conditioned,positiveedge,negativeedge); parameter counterwidth = 3; // Counter size, in bits, >= log2(waittime) parameter waittime = 3; // Debounce delay, in clock cycles + + input clk; + input noisysignal; + output reg conditioned; + output reg positiveedge; + output reg negativeedge; reg[counterwidth-1:0] counter = 0; reg synchronizer0 = 0; @@ -27,18 +27,19 @@ output reg negativeedge // 1 clk pulse at falling edge of conditioned negativeedge = 1; end else if (conditioned == 1 && conditioned1 == 0) begin positiveedge = 1; - end else if (positiveedge == 1 || negativeedge == 1) begin + end else if (positiveedge == 1 || negativeedge == 1) begin positiveedge = 0; negativeedge = 0; - end - if(conditioned == synchronizer1) - counter <= 0; - else begin - if( counter == waittime) begin + end + if(conditioned == synchronizer1) counter <= 0; - conditioned <= synchronizer1; - end else begin - counter <= counter+1; + else begin + if( counter == waittime) begin + counter <= 0; + conditioned <= synchronizer1; + end + else + counter <= counter+1; end synchronizer0 <= noisysignal; synchronizer1 <= synchronizer0; From a48dbbb22e2dee7f0ee3cd77424764c2f0f87106 Mon Sep 17 00:00:00 2001 From: CompArch Date: Wed, 25 Oct 2017 19:50:26 -0400 Subject: [PATCH 11/41] Test Sequence --- Test_Sequence.txt | 27 +++++++++++++ inputconditioner.v | 46 ++++++++++++---------- midpoint.v | 98 +++++++++++++++++++++++++++++++++++++++++++--- 3 files changed, 145 insertions(+), 26 deletions(-) create mode 100644 Test_Sequence.txt diff --git a/Test_Sequence.txt b/Test_Sequence.txt new file mode 100644 index 0000000..aa3e10c --- /dev/null +++ b/Test_Sequence.txt @@ -0,0 +1,27 @@ +Test Sequence + +Controls: + +Button0: Parallel Data In +Button1: Show Last 4 Bits +Button2: Show First 4 Bits + +Switch0: Serial Data In +Switch1: Serial Data In CLk Edge + +To begin testing first press Button0, then Button1. +You should see the following sequence in the 4 LEDS: 0011 +Press Button2 to see the first 4 bits which should be: 1100 + +Now to test the serial data in functionality set switch0 to HIGH and toggle Switch1 to high +This should write a 1 bit to the back of the shift register and you should see the following: +Press Button1: 0111 +Press Button2: 1000 + +Now set switch0 to low and toggle switch1 to high +This should write a 0 bit to the back of the shift register and you should see the following: +Press Button1: 1110 +Press Button2: 0000 + + +Now press Button0 again and the output should be 11000011 again. \ No newline at end of file diff --git a/inputconditioner.v b/inputconditioner.v index 165a183..6cee994 100644 --- a/inputconditioner.v +++ b/inputconditioner.v @@ -6,16 +6,16 @@ //------------------------------------------------------------------------ module inputconditioner -( -input clk, // Clock domain to synchronize input to -input noisysignal, // (Potentially) noisy input signal -output reg conditioned, // Conditioned output signal -output reg positiveedge, // 1 clk pulse at rising edge of conditioned -output reg negativeedge // 1 clk pulse at falling edge of conditioned -); +(clk,noisysignal,conditioned,positiveedge,negativeedge); parameter counterwidth = 3; // Counter size, in bits, >= log2(waittime) parameter waittime = 3; // Debounce delay, in clock cycles + + input clk; + input noisysignal; + output reg conditioned; + output reg positiveedge; + output reg negativeedge; reg[counterwidth-1:0] counter = 0; reg synchronizer0 = 0; @@ -23,25 +23,29 @@ output reg negativeedge // 1 clk pulse at falling edge of conditioned reg conditioned1 = 0; always @(posedge clk ) begin - if(conditioned == 0 && conditioned1 == 1) begin - negativeedge = 1; - end else if (conditioned == 1 && conditioned1 == 0) begin - positiveedge = 1; - end else if (positiveedge == 1 || negativeedge == 1) begin + if(conditioned == 0 && conditioned1 == 1) begin + negativeedge = 1; + end else if (conditioned == 1 && conditioned1 == 0) begin + positiveedge = 1; + end else if (positiveedge == 1 || negativeedge == 1) begin positiveedge = 0; negativeedge = 0; - end - if(conditioned == synchronizer1) - counter <= 0; - else begin - if( counter == waittime) begin + end + if(conditioned == synchronizer1) counter <= 0; - conditioned <= synchronizer1; - end else begin - counter <= counter+1; + else begin + if( counter == waittime) begin + counter <= 0; + conditioned <= synchronizer1; + end + else + counter <= counter+1; end synchronizer0 <= noisysignal; synchronizer1 <= synchronizer0; - conditioned1 <= conditioned; + conditioned1 <= conditioned; end endmodule + + + diff --git a/midpoint.v b/midpoint.v index 60885e3..287a456 100644 --- a/midpoint.v +++ b/midpoint.v @@ -9,8 +9,6 @@ // time, and multiplexes the LEDs to show the SUM and carryout/overflow at // different times. // -// Your job: -/ // // Usage: // btn0 - load parallel load into input conditioner -> shift register @@ -63,6 +61,97 @@ module mux2 #( parameter W = 1 ) assign out = (sel) ? in1 : in0; endmodule +//------------------------------------------------------------------------ +// Input Conditioner +// 1) Synchronizes input to clock domain +// 2) Debounces input +// 3) Creates pulses at edge transitions +//------------------------------------------------------------------------ + +module inputconditioner +(clk,noisysignal,conditioned,positiveedge,negativeedge); + + parameter counterwidth = 3; // Counter size, in bits, >= log2(waittime) + parameter waittime = 3; // Debounce delay, in clock cycles + + input clk; + input noisysignal; + output reg conditioned; + output reg positiveedge; + output reg negativeedge; + + reg[counterwidth-1:0] counter = 0; + reg synchronizer0 = 0; + reg synchronizer1 = 0; + reg conditioned1 = 0; + + always @(posedge clk ) begin + if(conditioned == 0 && conditioned1 == 1) begin + negativeedge = 1; + end else if (conditioned == 1 && conditioned1 == 0) begin + positiveedge = 1; + end else if (positiveedge == 1 || negativeedge == 1) begin + positiveedge = 0; + negativeedge = 0; + end + if(conditioned == synchronizer1) + counter <= 0; + else begin + if( counter == waittime) begin + counter <= 0; + conditioned <= synchronizer1; + end + else + counter <= counter+1; + end + synchronizer0 <= noisysignal; + synchronizer1 <= synchronizer0; + conditioned1 <= conditioned; + end +endmodule + +//------------------------------------------------------------------------ +// Shift Register +// Parameterized width (in bits) +// Shift register can operate in two modes: +// - serial in, parallel out +// - parallel in, serial out +//------------------------------------------------------------------------ + +module shiftregister +#(parameter width = 8) +( +input clk, // FPGA Clock +input peripheralClkEdge, // Edge indicator +input parallelLoad, // 1 = Load shift reg with parallelDataIn +input [width-1:0] parallelDataIn, // Load shift reg in parallel +input serialDataIn, // Load shift reg serially +output reg [width-1:0] parallelDataOut, // Shift reg data contents +output reg serialDataOut // Positive edge synchronized +); + + reg [width-1:0] shiftregistermem; + + always @(posedge clk) begin + + if(parallelLoad==1) begin + // load the register with parallelDataIn + shiftregistermem <= parallelDataIn; + end + + else if(parallelLoad==0) begin + if(peripheralClkEdge==1) begin + //grab the MSB as SDO and then shift everything over 1 place + serialDataOut <= shiftregistermem[width-1]; + shiftregistermem<={shiftregistermem[width-2:0],serialDataIn}; + end + end + //parallelDataOut is just the current state of the register + parallelDataOut <= shiftregistermem; + + end +endmodule + //-------------------------------------------------------------------------------- // Main Lab 0 wrapper module @@ -79,7 +168,7 @@ module midpoint output [3:0] led ); - reg[7:0] parallaData = 8`b11000011; //Assign default parallel in + reg[7:0] parallelData = 8'b11000011; //Assign default parallel in wire[3:0] res0, res1; // wire[7:0] shiftregister; // Current Shift Register Values wire res_sel; // Select between display options @@ -89,10 +178,9 @@ module midpoint // Capture button input to switch which MUX input to LEDs - jkff1 src_sel(.trigger(clk), .j(btn[2]), .k(btn[1]), .q(res_sel)); + jkff1 src_sel(.trigger(clk), .j(btn[1]), .k(btn[2]), .q(res_sel)); mux2 #(4) output_select(.in0(res0), .in1(res1), .sel(res_sel), .out(led)); - //Map to input conditioner inputconditioner parallel(.noisysignal(btn[0]),.clk(clk),.negativeedge(parallelslc)); inputconditioner serialinputs(.noisysignal(sw[0]),.clk(clk),.conditioned(serialin)); From 70fec8c2107acf3a8a16ca5d4dd73a0a787271c6 Mon Sep 17 00:00:00 2001 From: Bryan Werth Date: Mon, 30 Oct 2017 01:59:45 -0400 Subject: [PATCH 12/41] Finite State Machine First Pass is Working --- fsm.v | 63 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 63 insertions(+) create mode 100644 fsm.v diff --git a/fsm.v b/fsm.v new file mode 100644 index 0000000..6201f43 --- /dev/null +++ b/fsm.v @@ -0,0 +1,63 @@ +// MISO_BUFF DM_WE ADDR_WE SR_WE +//CS 0 0 0 0 +//~CS 0 0 1 1 +//shiftRegOutP[0] 1 0 0 1 +//~shiftRegOutP[0]0 1 0 0 +module fsm(MISO_BUFF,DM_WE,ADDR_WE,SR_WE,POS_EDGE,CS,shiftRegOutP0); + input POS_EDGE; + input CS; + input shiftRegOutP0; + output MISO_BUFF; + output DM_WE; + output ADDR_WE; + output SR_WE; + + reg [1:0] state; + reg MISO_BUFF,DM_WE,ADDR_WE,SR_WE; + wire [1:0] next_state; + + assign next_state = fsm_function(state,POS_EDGE,CS,shiftRegOutP0); + + function [1:0] fsm_function; + input [1:0] state; + input POS_EDGE; + input CS; + input ShiftRegOutP0; + case(state) + 2'b00:if(!CS) begin + fsm_function = 2'b01; + end + 2'b01:if(shiftRegOutP0) begin + fsm_function = 2'b10; + end else if (!shiftRegOutP0) begin + fsm_function = 2'b11; + end + 2'b10:if(CS) begin + fsm_function = 2'b00; + end + 2'b11:if(CS) begin + fsm_function = 2'b00; + end + default:fsm_function = 2'b00; + endcase + endfunction + + always @ (*) begin + state <= next_state; + if (state == 2'b00) begin + MISO_BUFF <= 0; + DM_WE <= 0; + SR_WE <= 0; + end else if (state == 2'b01) begin + ADDR_WE <= 1; + SR_WE <= 1; + end else if (state == 2'b10) begin + MISO_BUFF <= 1; + ADDR_WE <= 0; + end else if (state == 2'b11) begin + DM_WE <= 1; + ADDR_WE <= 0; + SR_WE <= 0; + end + end +endmodule \ No newline at end of file From 387a1e6fc235fce266eedbdd8304fdf365e2b987 Mon Sep 17 00:00:00 2001 From: Wilson Tang Date: Tue, 31 Oct 2017 16:20:21 -0400 Subject: [PATCH 13/41] first version of spi --- spimemory.v | 266 ++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 266 insertions(+) diff --git a/spimemory.v b/spimemory.v index c6ed4f7..d9a89a8 100644 --- a/spimemory.v +++ b/spimemory.v @@ -2,6 +2,201 @@ // SPI Memory //------------------------------------------------------------------------ +//-------------------------------------------------------------------------------- +// Wrapper for Lab 2: Midpoint.v +// +// Rationale: +// The ZYBO board has 4 buttons, 4 switches, and 4 LEDs. But if we want to +// show the results of a 4-bit add operation, we will need at least 6 LEDs! +// +// This wrapper module allows for 4-bit operands to be loaded in one at a +// time, and multiplexes the LEDs to show the SUM and carryout/overflow at +// different times. +// +// +// Usage: +// btn0 - load parallel load into input conditioner -> shift register +// btn1 - show first 4 bits +// btn2 - show last 4 bits +// sw0 - Serial In Input into input conditioner -> shift register +// sw1 - Clk Edge +// +// Note: Buttons, switches, and LEDs have the least-significant (0) position +// on the right. +//-------------------------------------------------------------------------------- + +`timescale 1ns / 1ps + +//-------------------------------------------------------------------------------- +// Basic building block modules +//-------------------------------------------------------------------------------- + +// JK flip-flop +module jkff1 +( + input trigger, + input j, + input k, + output reg q +); + always @(posedge trigger) begin + if(j && ~k) begin + q <= 1'b1; + end + else if(k && ~j) begin + q <= 1'b0; + end + else if(k && j) begin + q <= ~q; + end + end +endmodule + +// Two-input MUX with parameterized bit width (default: 1-bit) +module mux2 #( parameter W = 1 ) +( + input[W-1:0] in0, + input[W-1:0] in1, + input sel, + output[W-1:0] out +); + // Conditional operator - http://www.verilog.renerta.com/source/vrg00010.htm + assign out = (sel) ? in1 : in0; +endmodule + +module dff #(parameter W = 1) +( + input trigger, + input enable, + input [W-1:0] d, + output reg [W-1:0] q +); + always @p(posedge trigger) begin + if(enable) begin + q <=d; + end + end + +endmodule + +module dlatch +( + input [7:0] data , + input clk, + input addr_we, + output [6:0] addr +); + +reg [6:0] addr; + +always @(posedge clk) begin + if(addr_we) begin + assign addr = data[7:1]; + end +end + +endmodule + +//------------------------------------------------------------------------ +// Input Conditioner +// 1) Synchronizes input to clock domain +// 2) Debounces input +// 3) Creates pulses at edge transitions +//------------------------------------------------------------------------ + +module inputconditioner +(clk,noisysignal,conditioned,positiveedge,negativeedge); + + parameter counterwidth = 3; // Counter size, in bits, >= log2(waittime) + parameter waittime = 3; // Debounce delay, in clock cycles + + input clk; + input noisysignal; + output reg conditioned; + output reg positiveedge; + output reg negativeedge; + + reg[counterwidth-1:0] counter = 0; + reg synchronizer0 = 0; + reg synchronizer1 = 0; + reg conditioned1 = 0; + + always @(posedge clk ) begin + if(conditioned == 0 && conditioned1 == 1) begin + negativeedge = 1; + end else if (conditioned == 1 && conditioned1 == 0) begin + positiveedge = 1; + end else if (positiveedge == 1 || negativeedge == 1) begin + positiveedge = 0; + negativeedge = 0; + end + if(conditioned == synchronizer1) + counter <= 0; + else begin + if( counter == waittime) begin + counter <= 0; + conditioned <= synchronizer1; + end + else + counter <= counter+1; + end + synchronizer0 <= noisysignal; + synchronizer1 <= synchronizer0; + conditioned1 <= conditioned; + end +endmodule + +//------------------------------------------------------------------------ +// Shift Register +// Parameterized width (in bits) +// Shift register can operate in two modes: +// - serial in, parallel out +// - parallel in, serial out +//------------------------------------------------------------------------ + +module shiftregister +#(parameter width = 8) +( +input clk, // FPGA Clock +input peripheralClkEdge, // Edge indicator +input parallelLoad, // 1 = Load shift reg with parallelDataIn +input [width-1:0] parallelDataIn, // Load shift reg in parallel +input serialDataIn, // Load shift reg serially +output reg [width-1:0] parallelDataOut, // Shift reg data contents +output reg serialDataOut // Positive edge synchronized +); + + reg [width-1:0] shiftregistermem; + + always @(posedge clk) begin + + if(parallelLoad==1) begin + // load the register with parallelDataIn + shiftregistermem <= parallelDataIn; + end + + else if(parallelLoad==0) begin + if(peripheralClkEdge==1) begin + //grab the MSB as SDO and then shift everything over 1 place + serialDataOut <= shiftregistermem[width-1]; + shiftregistermem<={shiftregistermem[width-2:0],serialDataIn}; + end + end + //parallelDataOut is just the current state of the register + parallelDataOut <= shiftregistermem; + + end +endmodule + + +//-------------------------------------------------------------------------------- +// Main Lab 2 wrapper module +// Interfaces with switches, buttons, and LEDs on ZYBO board. Allows for two +// operations: read and write. 8 bits are entered (first 7 are address and the last is a R/W flag) +// Read: +// Write: +//-------------------------------------------------------------------------------- + module spiMemory ( input clk, // FPGA clock @@ -12,6 +207,77 @@ module spiMemory output [3:0] leds // LEDs for debugging ) + integer i; + wire[7:0] parallelData // ParallelData Out + wire[6:0] address // address + wire[3:0] res0, res1; // + wire[7:0] shiftregister; // Current Shift Register Values + wire res_sel; // Select between display options + wire parallelslc; // select parallel input + wire serialin; // binary input for serial input + wire posSCLK; // clk edge for serial input + wire negSCLK; // + wire CS ; // chip select + wire Flag; // R/W flag + wire miso_buff; // miso_buff + wire dm_we; // dm_we + wire addr_we; // addr_we + wire sr_we; // sr_we + + //Map to input conditioners + inputconditioner MOSI(.noisysignal(mosi_pin),.clk(clk),.conditioned(serialin)); + inputconditioner SCLK(.noisysignal(sclk_pin),.clk(clk),.positiveedge(posSCLK),.negativeedge(negSCLK)); + inputconditioner CS(.noisysignal(cs_pin),.clk(clk),.conditioned(CS)); + + //finite statemachine + fsm(.POS_EDGE(posSCLK),.CS(CS),.shiftRegOutP0(Flag),.MISO_BUFF(miso_buff),.DM_WE(dm_we),.ADDR_WE(sr_we),.SR_WE(sr_we)); + + //Address Latch + dlatch addr_latch(.data(parallelData),.clk(clk),.addr_we(addr_we),.addr(address)); + + //Wait for chip select to be asserted low and begin + always @(posedge clk) begin + If() + + //Read first 8 bits + for (i = 7; i > 0; i = i-1) begin + assign serialin + end + + shiftregister shifted(.clk(clk),.peripheralClkEdge(posSCLK),.parallelLoad(parallelslc),.parallelDataIn(parallelData),.serialDataIn(serialin),.parallelDataOut(shiftregister)); + + + //Write Operation + + + shiftregister shifted(.clk(clk),.peripheralClkEdge(posSCLK),.parallelLoad(parallelslc),.parallelDataIn(parallelData),.serialDataIn(serialin),.parallelDataOut(shiftregister)); + + //data memory + datamemory data(.clk(clk),.address(address),.writeEnable(dm_we),.dataIn(shiftregister)); + + //Input into Shift Register + + + //Read Operation + + shiftregister shifted(.clk(clk),.peripheralClkEdge(posSCLK),.parallelLoad(parallelslc),.parallelDataIn(d_out),.serialDataOut()); + + //data memory + datamemory data(.clk(clk),.dataOut(),.address(),.writeEnable(dm_we)); + + + + + + // Assign bits of shiftregister to appropriate display boxes + assign res0[0] = shiftregister[0]; + assign res0[1] = shiftregister[1]; + assign res0[2] = shiftregister[2]; + assign res0[3] = shiftregister[3]; + assign res1[0] = shiftregister[4]; + assign res1[1] = shiftregister[5]; + assign res1[2] = shiftregister[6]; + assign res1[3] = shiftregister[7]; endmodule From f980c18f393d444d2e142801109f9ac435549afb Mon Sep 17 00:00:00 2001 From: Bryan Werth Date: Tue, 31 Oct 2017 20:59:40 -0400 Subject: [PATCH 14/41] Finished first pass implementation --- inputconditioner.v | 10 +++++----- spimemory.v | 16 +++++++++++++++- 2 files changed, 20 insertions(+), 6 deletions(-) diff --git a/inputconditioner.v b/inputconditioner.v index 6cee994..99548df 100644 --- a/inputconditioner.v +++ b/inputconditioner.v @@ -23,27 +23,27 @@ module inputconditioner reg conditioned1 = 0; always @(posedge clk ) begin - if(conditioned == 0 && conditioned1 == 1) begin + if(conditioned1 == 0 && conditioned == 1) begin negativeedge = 1; - end else if (conditioned == 1 && conditioned1 == 0) begin + end else if (conditioned1 == 1 && conditioned == 0) begin positiveedge = 1; end else if (positiveedge == 1 || negativeedge == 1) begin positiveedge = 0; negativeedge = 0; end - if(conditioned == synchronizer1) + if(conditioned1 == synchronizer1) counter <= 0; else begin if( counter == waittime) begin counter <= 0; - conditioned <= synchronizer1; + conditioned1 <= synchronizer1; end else counter <= counter+1; end synchronizer0 <= noisysignal; synchronizer1 <= synchronizer0; - conditioned1 <= conditioned; + conditioned <= conditioned1; end endmodule diff --git a/spimemory.v b/spimemory.v index d9a89a8..3effacb 100644 --- a/spimemory.v +++ b/spimemory.v @@ -52,6 +52,15 @@ module jkff1 end endmodule +module tristatebuffer(out,in,en); + input [7:0] in; + input en; + output [7:0] out; + + assign out = en ? in : 8'b0; + +endmodule + // Two-input MUX with parameterized bit width (default: 1-bit) module mux2 #( parameter W = 1 ) ( @@ -215,6 +224,7 @@ module spiMemory wire res_sel; // Select between display options wire parallelslc; // select parallel input wire serialin; // binary input for serial input + wire serialout; // serial output of shift register wire posSCLK; // clk edge for serial input wire negSCLK; // wire CS ; // chip select @@ -223,6 +233,7 @@ module spiMemory wire dm_we; // dm_we wire addr_we; // addr_we wire sr_we; // sr_we + wire output_ff_out // output ff output //Map to input conditioners inputconditioner MOSI(.noisysignal(mosi_pin),.clk(clk),.conditioned(serialin)); @@ -235,6 +246,9 @@ module spiMemory //Address Latch dlatch addr_latch(.data(parallelData),.clk(clk),.addr_we(addr_we),.addr(address)); + dff output_ff(.trigger(clk),.enable(negSCLK),.d(serialout),.q(output_ff_out)); + + tristatebuffer outbuffer(.out(miso_pin),.in(output_ff_out),.en(miso_buff)); //Wait for chip select to be asserted low and begin always @(posedge clk) begin If() @@ -260,7 +274,7 @@ module spiMemory //Read Operation - shiftregister shifted(.clk(clk),.peripheralClkEdge(posSCLK),.parallelLoad(parallelslc),.parallelDataIn(d_out),.serialDataOut()); + shiftregister shifted(.clk(clk),.peripheralClkEdge(posSCLK),.parallelLoad(parallelslc),.parallelDataIn(d_out),.serialDataOut(serialout)); //data memory datamemory data(.clk(clk),.dataOut(),.address(),.writeEnable(dm_we)); From eac0358d001efd25a28d4e1c8c6b56576f7100cb Mon Sep 17 00:00:00 2001 From: Joseph Lee Date: Wed, 1 Nov 2017 01:10:21 -0400 Subject: [PATCH 15/41] added timing conditions --- fsm.v | 21 ++++++++++++++++++--- spimemory.v | 26 -------------------------- 2 files changed, 18 insertions(+), 29 deletions(-) diff --git a/fsm.v b/fsm.v index 6201f43..d06440f 100644 --- a/fsm.v +++ b/fsm.v @@ -3,10 +3,11 @@ //~CS 0 0 1 1 //shiftRegOutP[0] 1 0 0 1 //~shiftRegOutP[0]0 1 0 0 -module fsm(MISO_BUFF,DM_WE,ADDR_WE,SR_WE,POS_EDGE,CS,shiftRegOutP0); +module fsm(MISO_BUFF,DM_WE,ADDR_WE,SR_WE,POS_EDGE,CS,shiftRegOutP0,clk); input POS_EDGE; input CS; input shiftRegOutP0; + input clk; output MISO_BUFF; output DM_WE; output ADDR_WE; @@ -15,6 +16,8 @@ module fsm(MISO_BUFF,DM_WE,ADDR_WE,SR_WE,POS_EDGE,CS,shiftRegOutP0); reg [1:0] state; reg MISO_BUFF,DM_WE,ADDR_WE,SR_WE; wire [1:0] next_state; + parameter counter_num_bits = 4; + reg[counter_num_bits-1:0] counter = 0; assign next_state = fsm_function(state,POS_EDGE,CS,shiftRegOutP0); @@ -42,14 +45,16 @@ module fsm(MISO_BUFF,DM_WE,ADDR_WE,SR_WE,POS_EDGE,CS,shiftRegOutP0); endcase endfunction - always @ (*) begin + always @ (posedge clk) begin state <= next_state; if (state == 2'b00) begin MISO_BUFF <= 0; DM_WE <= 0; SR_WE <= 0; end else if (state == 2'b01) begin - ADDR_WE <= 1; + if(counter==0) begin + counter <= 1; + end SR_WE <= 1; end else if (state == 2'b10) begin MISO_BUFF <= 1; @@ -59,5 +64,15 @@ module fsm(MISO_BUFF,DM_WE,ADDR_WE,SR_WE,POS_EDGE,CS,shiftRegOutP0); ADDR_WE <= 0; SR_WE <= 0; end + if (counter==7)begin + ADDR_WE<=1; + end + else if (counter==8)begin + ADDR_WE <=0; + counter<=0; + end + else if (counter>0)begin + counter<=counter+1; + end end endmodule \ No newline at end of file diff --git a/spimemory.v b/spimemory.v index 3effacb..81d12fe 100644 --- a/spimemory.v +++ b/spimemory.v @@ -249,19 +249,6 @@ module spiMemory dff output_ff(.trigger(clk),.enable(negSCLK),.d(serialout),.q(output_ff_out)); tristatebuffer outbuffer(.out(miso_pin),.in(output_ff_out),.en(miso_buff)); - //Wait for chip select to be asserted low and begin - always @(posedge clk) begin - If() - - //Read first 8 bits - for (i = 7; i > 0; i = i-1) begin - assign serialin - end - - shiftregister shifted(.clk(clk),.peripheralClkEdge(posSCLK),.parallelLoad(parallelslc),.parallelDataIn(parallelData),.serialDataIn(serialin),.parallelDataOut(shiftregister)); - - - //Write Operation shiftregister shifted(.clk(clk),.peripheralClkEdge(posSCLK),.parallelLoad(parallelslc),.parallelDataIn(parallelData),.serialDataIn(serialin),.parallelDataOut(shiftregister)); @@ -269,19 +256,6 @@ module spiMemory //data memory datamemory data(.clk(clk),.address(address),.writeEnable(dm_we),.dataIn(shiftregister)); - //Input into Shift Register - - - //Read Operation - - shiftregister shifted(.clk(clk),.peripheralClkEdge(posSCLK),.parallelLoad(parallelslc),.parallelDataIn(d_out),.serialDataOut(serialout)); - - //data memory - datamemory data(.clk(clk),.dataOut(),.address(),.writeEnable(dm_we)); - - - - // Assign bits of shiftregister to appropriate display boxes assign res0[0] = shiftregister[0]; From f90df213b375a9110b619726f7c8be36064aab84 Mon Sep 17 00:00:00 2001 From: Bryan Werth Date: Wed, 1 Nov 2017 20:13:47 -0400 Subject: [PATCH 16/41] spi memory compiles now! --- spimemory.v | 39 +++++++++++++++++---------------------- 1 file changed, 17 insertions(+), 22 deletions(-) diff --git a/spimemory.v b/spimemory.v index 81d12fe..2fe717e 100644 --- a/spimemory.v +++ b/spimemory.v @@ -57,7 +57,7 @@ module tristatebuffer(out,in,en); input en; output [7:0] out; - assign out = en ? in : 8'b0; + assign out = en ? in : 8'bz; endmodule @@ -80,7 +80,7 @@ module dff #(parameter W = 1) input [W-1:0] d, output reg [W-1:0] q ); - always @p(posedge trigger) begin + always @ (posedge trigger) begin if(enable) begin q <=d; end @@ -93,14 +93,12 @@ module dlatch input [7:0] data , input clk, input addr_we, - output [6:0] addr + output reg [6:0] addr ); -reg [6:0] addr; - always @(posedge clk) begin if(addr_we) begin - assign addr = data[7:1]; + addr = data[7:1]; end end @@ -206,19 +204,16 @@ endmodule // Write: //-------------------------------------------------------------------------------- -module spiMemory -( - input clk, // FPGA clock - input sclk_pin, // SPI clock - input cs_pin, // SPI chip select - output miso_pin, // SPI master in slave out - input mosi_pin, // SPI master out slave in - output [3:0] leds // LEDs for debugging -) - - integer i; - wire[7:0] parallelData // ParallelData Out - wire[6:0] address // address +module spiMemory(clk,sclk_pin,cs_pin,miso_pin,mosi_pin,leds); + input clk; + input sclk_pin; + input cs_pin; + output miso_pin; + input mosi_pin; + output [3:0] leds; + + wire[7:0] parallelData; // ParallelData Out + wire[6:0] address; // address wire[3:0] res0, res1; // wire[7:0] shiftregister; // Current Shift Register Values wire res_sel; // Select between display options @@ -233,12 +228,12 @@ module spiMemory wire dm_we; // dm_we wire addr_we; // addr_we wire sr_we; // sr_we - wire output_ff_out // output ff output + wire output_ff_out; // output ff output //Map to input conditioners - inputconditioner MOSI(.noisysignal(mosi_pin),.clk(clk),.conditioned(serialin)); + inputconditioner MOSI_conditioner(.noisysignal(mosi_pin),.clk(clk),.conditioned(serialin)); inputconditioner SCLK(.noisysignal(sclk_pin),.clk(clk),.positiveedge(posSCLK),.negativeedge(negSCLK)); - inputconditioner CS(.noisysignal(cs_pin),.clk(clk),.conditioned(CS)); + inputconditioner CS_conditioner(.noisysignal(cs_pin),.clk(clk),.conditioned(CS)); //finite statemachine fsm(.POS_EDGE(posSCLK),.CS(CS),.shiftRegOutP0(Flag),.MISO_BUFF(miso_buff),.DM_WE(dm_we),.ADDR_WE(sr_we),.SR_WE(sr_we)); From 2020254f9d6dad9f51134fc35c74a39e2d3620f2 Mon Sep 17 00:00:00 2001 From: Bryan Werth Date: Wed, 1 Nov 2017 20:37:16 -0400 Subject: [PATCH 17/41] spimemory compiles and is correct --- spimemory.v | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/spimemory.v b/spimemory.v index 2fe717e..187c9f3 100644 --- a/spimemory.v +++ b/spimemory.v @@ -53,11 +53,11 @@ module jkff1 endmodule module tristatebuffer(out,in,en); - input [7:0] in; + input in; input en; - output [7:0] out; + output out; - assign out = en ? in : 8'bz; + assign out = en ? in : 1'bz; endmodule From 33610b686ae1cb24aa01a25e691aa2c8ad7b15e9 Mon Sep 17 00:00:00 2001 From: Wilson Tang Date: Wed, 1 Nov 2017 21:00:08 -0400 Subject: [PATCH 18/41] fpga --- spimemory_fpga.v | 346 +++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 346 insertions(+) create mode 100644 spimemory_fpga.v diff --git a/spimemory_fpga.v b/spimemory_fpga.v new file mode 100644 index 0000000..73d7406 --- /dev/null +++ b/spimemory_fpga.v @@ -0,0 +1,346 @@ +//------------------------------------------------------------------------ +// SPI Memory +//------------------------------------------------------------------------ + +//-------------------------------------------------------------------------------- +// Wrapper for Lab 2: spimemory +// +// Rationale: +// The ZYBO board has 4 buttons, 4 switches, and 4 LEDs. We want to be able to verify the miso pin +// so we need to display the current miso value and have another indicator to indicate if it is tristated to // differentiate between '0' and 'z'. +// Usage: +// sw0 - Serial In Input into input conditioner -> shift register +// sw1 - Clk Edge +// sw2 - Chip Select +// led0 - Miso +// led3 - Tristated? +// Note: Buttons, switches, and LEDs have the least-significant (0) position +// on the right. +//-------------------------------------------------------------------------------- + +`timescale 1ns / 1ps + +//-------------------------------------------------------------------------------- +// Basic building block modules +//-------------------------------------------------------------------------------- + + +module dff #(parameter W = 1) +( + input trigger, + input enable, + input [W-1:0] d, + output reg [W-1:0] q +); + always @ (posedge trigger) begin + if(enable) begin + q <=d; + end + end + +endmodule + +module dlatch +( + input [7:0] data , + input clk, + input addr_we, + output reg [6:0] addr +); + +always @(posedge clk) begin + if(addr_we) begin + addr = data[7:1]; + end +end + +endmodule + + +module tristatebuffer(out,in,en); + input in; + input en; + output out; + + assign out = en ? in : 1'bz; + +endmodule + +//------------------------------------------------------------------------ +// Input Conditioner +// 1) Synchronizes input to clock domain +// 2) Debounces input +// 3) Creates pulses at edge transitions +//------------------------------------------------------------------------ + +module inputconditioner +(clk,noisysignal,conditioned,positiveedge,negativeedge); + + parameter counterwidth = 3; // Counter size, in bits, >= log2(waittime) + parameter waittime = 3; // Debounce delay, in clock cycles + + input clk; + input noisysignal; + output reg conditioned; + output reg positiveedge; + output reg negativeedge; + + reg[counterwidth-1:0] counter = 0; + reg synchronizer0 = 0; + reg synchronizer1 = 0; + reg conditioned1 = 0; + + always @(posedge clk ) begin + if(conditioned == 0 && conditioned1 == 1) begin + negativeedge = 1; + end else if (conditioned == 1 && conditioned1 == 0) begin + positiveedge = 1; + end else if (positiveedge == 1 || negativeedge == 1) begin + positiveedge = 0; + negativeedge = 0; + end + if(conditioned == synchronizer1) + counter <= 0; + else begin + if( counter == waittime) begin + counter <= 0; + conditioned <= synchronizer1; + end + else + counter <= counter+1; + end + synchronizer0 <= noisysignal; + synchronizer1 <= synchronizer0; + conditioned1 <= conditioned; + end +endmodule + +//------------------------------------------------------------------------ +// Shift Register +// Parameterized width (in bits) +// Shift register can operate in two modes: +// - serial in, parallel out +// - parallel in, serial out +//------------------------------------------------------------------------ + +module shiftregister +#(parameter width = 8) +( +input clk, // FPGA Clock +input peripheralClkEdge, // Edge indicator +input parallelLoad, // 1 = Load shift reg with parallelDataIn +input [width-1:0] parallelDataIn, // Load shift reg in parallel +input serialDataIn, // Load shift reg serially +output reg [width-1:0] parallelDataOut, // Shift reg data contents +output reg serialDataOut // Positive edge synchronized +); + + reg [width-1:0] shiftregistermem; + + always @(posedge clk) begin + + if(parallelLoad==1) begin + // load the register with parallelDataIn + shiftregistermem <= parallelDataIn; + end + + else if(parallelLoad==0) begin + if(peripheralClkEdge==1) begin + //grab the MSB as SDO and then shift everything over 1 place + serialDataOut <= shiftregistermem[width-1]; + shiftregistermem<={shiftregistermem[width-2:0],serialDataIn}; + end + end + //parallelDataOut is just the current state of the register + parallelDataOut <= shiftregistermem; + + end +endmodule + + +//------------------------------------------------------------------------ +// Data Memory +// Positive edge triggered +// dataOut always has the value mem[address] +// If writeEnable is true, writes dataIn to mem[address] +//------------------------------------------------------------------------ + +module datamemory +#( + parameter addresswidth = 7, + parameter depth = 2**addresswidth, + parameter width = 8 +) +( + input clk, + output reg [width-1:0] dataOut, + input [addresswidth-1:0] address, + input writeEnable, + input [width-1:0] dataIn +); + + + reg [width-1:0] memory [depth-1:0]; + + always @(posedge clk) begin + if(writeEnable) + memory[address] <= dataIn; + dataOut <= memory[address]; + end + +endmodule + + +//------------------------------------------------------------------------ +// Finite State Machine +// +// MISO_BUFF DM_WE ADDR_WE SR_WE +//CS 0 0 0 0 +//~CS 0 0 1 1 +//shiftRegOutP[0] 1 0 0 1 +//~shiftRegOutP[0]0 1 0 0 +// +//------------------------------------------------------------------------ + +module fsm(MISO_BUFF,DM_WE,ADDR_WE,SR_WE,POS_EDGE,CS,shiftRegOutP0,clk); + input POS_EDGE; + input CS; + input shiftRegOutP0; + input clk; + output MISO_BUFF; + output DM_WE; + output ADDR_WE; + output SR_WE; + + reg [1:0] state; + reg MISO_BUFF,DM_WE,ADDR_WE,SR_WE; + wire [1:0] next_state; + parameter counter_num_bits = 4; + reg[counter_num_bits-1:0] counter = 0; + + assign next_state = fsm_function(state,POS_EDGE,CS,shiftRegOutP0); + + function [1:0] fsm_function; + input [1:0] state; + input POS_EDGE; + input CS; + input ShiftRegOutP0; + case(state) + 2'b00:if(!CS) begin + fsm_function = 2'b01; + end + 2'b01:if(shiftRegOutP0) begin + fsm_function = 2'b10; + end else if (!shiftRegOutP0) begin + fsm_function = 2'b11; + end + 2'b10:if(CS) begin + fsm_function = 2'b00; + end + 2'b11:if(CS) begin + fsm_function = 2'b00; + end + default:fsm_function = 2'b00; + endcase + endfunction + + always @ (posedge clk) begin + state <= next_state; + if (state == 2'b00) begin + MISO_BUFF <= 0; + DM_WE <= 0; + SR_WE <= 0; + end else if (state == 2'b01) begin + if(counter==0) begin + counter <= 1; + end + SR_WE <= 1; + end else if (state == 2'b10) begin + MISO_BUFF <= 1; + ADDR_WE <= 0; + end else if (state == 2'b11) begin + DM_WE <= 1; + ADDR_WE <= 0; + SR_WE <= 0; + end + if (counter==7)begin + ADDR_WE<=1; + end + else if (counter==8)begin + ADDR_WE <=0; + counter<=0; + end + else if (counter>0)begin + counter<=counter+1; + end + end +endmodule + +//-------------------------------------------------------------------------------- +// Main Lab 2 wrapper module +// Interfaces with switches, buttons, and LEDs on ZYBO board. Allows for two +// operations: read and write. 8 bits are entered (first 7 are address and the last is a R/W flag) +// Read: +// Write: +// sw[0] = mosi pin +// sw[1] = clk edge +// sw[2] = chip select +// led0 = miso +// led3 = tristated +//-------------------------------------------------------------------------------- + +module spiMemory(clk,sw,leds); + input clk; + input [2:0] sw; + output reg [3:0] leds; + + wire[7:0] parallelData; // ParallelData Out + wire[6:0] address; // address + wire[7:0] shiftregister; // Current Shift Register Values + wire miso; // current miso value + wire res_sel; // Select between display options + wire parallelslc; // select parallel input + wire serialin; // binary input for serial input + wire serialout; // serial output of shift register + wire posSCLK; // clk edge for serial input + wire negSCLK; // + wire CS ; // chip select + wire Flag; // R/W flag + wire miso_buff; // miso_buff + wire dm_we; // dm_we + wire addr_we; // addr_we + wire sr_we; // sr_we + wire output_ff_out; // output ff output + + + //Map to input conditioners + inputconditioner MOSI_conditioner(.noisysignal(sw[0]),.clk(clk),.conditioned(serialin)); + inputconditioner SCLK(.noisysignal(sw[1]),.clk(clk),.positiveedge(posSCLK),.negativeedge(negSCLK)); + inputconditioner CS_conditioner(.noisysignal(sw[2]),.clk(clk),.conditioned(CS)); + + //finite statemachine + fsm fsm(.POS_EDGE(posSCLK),.CS(sw[2]),.shiftRegOutP0(Flag),.MISO_BUFF(miso_buff),.DM_WE(dm_we),.ADDR_WE(sr_we),.SR_WE(sr_we)); + + //Address Latch + dlatch addr_latch(.data(parallelData),.clk(clk),.addr_we(addr_we),.addr(address)); + + dff output_ff(.trigger(clk),.enable(negSCLK),.d(serialout),.q(output_ff_out)); + + tristatebuffer outbuffer(.out(miso),.in(output_ff_out),.en(miso_buff)); + + + shiftregister shifted(.clk(clk),.peripheralClkEdge(posSCLK),.parallelLoad(parallelslc),.parallelDataIn(parallelData),.serialDataIn(serialin),.parallelDataOut(shiftregister)); + + //data memory + datamemory data(.clk(clk),.address(address),.writeEnable(dm_we),.dataIn(shiftregister)); + + + // Assign bits of shiftregister to appropriate display boxes + initial begin + leds[0] <= miso; + if (miso == 1'bz ) begin + leds[3] <= 1 ; + end + end +endmodule + From 4a8c8b929fe43dceed973cd7aab54e144d38fbc7 Mon Sep 17 00:00:00 2001 From: Wilson Tang Date: Wed, 1 Nov 2017 21:29:24 -0400 Subject: [PATCH 19/41] fpga --- spimemory_fpga.v | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/spimemory_fpga.v b/spimemory_fpga.v index 73d7406..6c94403 100644 --- a/spimemory_fpga.v +++ b/spimemory_fpga.v @@ -289,10 +289,10 @@ endmodule // led3 = tristated //-------------------------------------------------------------------------------- -module spiMemory(clk,sw,leds); +module spiMemory(clk,sw,led); input clk; input [2:0] sw; - output reg [3:0] leds; + output reg [3:0] led; wire[7:0] parallelData; // ParallelData Out wire[6:0] address; // address @@ -337,9 +337,9 @@ module spiMemory(clk,sw,leds); // Assign bits of shiftregister to appropriate display boxes initial begin - leds[0] <= miso; + led[0] <= miso; if (miso == 1'bz ) begin - leds[3] <= 1 ; + led[3] <= 1 ; end end endmodule From 0391cabe4bb968a98fade98872f00d4be641b31a Mon Sep 17 00:00:00 2001 From: Bryan Werth Date: Wed, 1 Nov 2017 22:15:01 -0400 Subject: [PATCH 20/41] Fixed the fsm --- fsm.v | 14 ++++++++------ inputconditioner.v | 10 +++++----- 2 files changed, 13 insertions(+), 11 deletions(-) diff --git a/fsm.v b/fsm.v index d06440f..a145d44 100644 --- a/fsm.v +++ b/fsm.v @@ -25,7 +25,7 @@ module fsm(MISO_BUFF,DM_WE,ADDR_WE,SR_WE,POS_EDGE,CS,shiftRegOutP0,clk); input [1:0] state; input POS_EDGE; input CS; - input ShiftRegOutP0; + input shiftRegOutP0; case(state) 2'b00:if(!CS) begin fsm_function = 2'b01; @@ -47,25 +47,27 @@ module fsm(MISO_BUFF,DM_WE,ADDR_WE,SR_WE,POS_EDGE,CS,shiftRegOutP0,clk); always @ (posedge clk) begin state <= next_state; - if (state == 2'b00) begin + if (next_state == 2'b00) begin MISO_BUFF <= 0; DM_WE <= 0; SR_WE <= 0; - end else if (state == 2'b01) begin - if(counter==0) begin + ADDR_WE <= 0; + end else if (next_state == 2'b01) begin + if(POS_EDGE) begin counter <= 1; end SR_WE <= 1; - end else if (state == 2'b10) begin + end else if (next_state == 2'b10) begin MISO_BUFF <= 1; ADDR_WE <= 0; - end else if (state == 2'b11) begin + end else if (next_state == 2'b11) begin DM_WE <= 1; ADDR_WE <= 0; SR_WE <= 0; end if (counter==7)begin ADDR_WE<=1; + counter <= counter + 1; end else if (counter==8)begin ADDR_WE <=0; diff --git a/inputconditioner.v b/inputconditioner.v index 99548df..47618a5 100644 --- a/inputconditioner.v +++ b/inputconditioner.v @@ -23,10 +23,10 @@ module inputconditioner reg conditioned1 = 0; always @(posedge clk ) begin - if(conditioned1 == 0 && conditioned == 1) begin - negativeedge = 1; - end else if (conditioned1 == 1 && conditioned == 0) begin - positiveedge = 1; + if(conditioned1 == 0 && conditioned == 1) begin + negativeedge = 1; + end else if (conditioned1 == 1 && conditioned == 0) begin + positiveedge = 1; end else if (positiveedge == 1 || negativeedge == 1) begin positiveedge = 0; negativeedge = 0; @@ -43,7 +43,7 @@ module inputconditioner end synchronizer0 <= noisysignal; synchronizer1 <= synchronizer0; - conditioned <= conditioned1; + conditioned <= conditioned1; end endmodule From c7b97ffdc88412bbd2f948b8743a410920fda96b Mon Sep 17 00:00:00 2001 From: Bryan Werth Date: Wed, 1 Nov 2017 23:41:28 -0400 Subject: [PATCH 21/41] Fixed some things with spi memory --- spimemory.v | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/spimemory.v b/spimemory.v index 187c9f3..9dfcb22 100644 --- a/spimemory.v +++ b/spimemory.v @@ -215,7 +215,7 @@ module spiMemory(clk,sclk_pin,cs_pin,miso_pin,mosi_pin,leds); wire[7:0] parallelData; // ParallelData Out wire[6:0] address; // address wire[3:0] res0, res1; // - wire[7:0] shiftregister; // Current Shift Register Values + wire[7:0] parallelOut; // Current Shift Register Values wire res_sel; // Select between display options wire parallelslc; // select parallel input wire serialin; // binary input for serial input @@ -236,7 +236,7 @@ module spiMemory(clk,sclk_pin,cs_pin,miso_pin,mosi_pin,leds); inputconditioner CS_conditioner(.noisysignal(cs_pin),.clk(clk),.conditioned(CS)); //finite statemachine - fsm(.POS_EDGE(posSCLK),.CS(CS),.shiftRegOutP0(Flag),.MISO_BUFF(miso_buff),.DM_WE(dm_we),.ADDR_WE(sr_we),.SR_WE(sr_we)); + fsm fsm_process(.POS_EDGE(posSCLK),.CS(CS),.shiftRegOutP0(parallelOut[0]),.clk(clk),.MISO_BUFF(miso_buff),.DM_WE(dm_we),.ADDR_WE(sr_we),.SR_WE(sr_we)); //Address Latch dlatch addr_latch(.data(parallelData),.clk(clk),.addr_we(addr_we),.addr(address)); @@ -246,21 +246,21 @@ module spiMemory(clk,sclk_pin,cs_pin,miso_pin,mosi_pin,leds); tristatebuffer outbuffer(.out(miso_pin),.in(output_ff_out),.en(miso_buff)); - shiftregister shifted(.clk(clk),.peripheralClkEdge(posSCLK),.parallelLoad(parallelslc),.parallelDataIn(parallelData),.serialDataIn(serialin),.parallelDataOut(shiftregister)); + shiftregister shifted(.clk(clk),.peripheralClkEdge(posSCLK),.parallelLoad(parallelslc),.parallelDataIn(parallelData),.serialDataIn(serialin),.parallelDataOut(parallelOut)); //data memory datamemory data(.clk(clk),.address(address),.writeEnable(dm_we),.dataIn(shiftregister)); // Assign bits of shiftregister to appropriate display boxes - assign res0[0] = shiftregister[0]; - assign res0[1] = shiftregister[1]; - assign res0[2] = shiftregister[2]; - assign res0[3] = shiftregister[3]; - assign res1[0] = shiftregister[4]; - assign res1[1] = shiftregister[5]; - assign res1[2] = shiftregister[6]; - assign res1[3] = shiftregister[7]; + assign res0[0] = parallelOut[0]; + assign res0[1] = parallelOut[1]; + assign res0[2] = parallelOut[2]; + assign res0[3] = parallelOut[3]; + assign res1[0] = parallelOut[4]; + assign res1[1] = parallelOut[5]; + assign res1[2] = parallelOut[6]; + assign res1[3] = parallelOut[7]; endmodule From 1cf7056ab03bf15ebaa49c9b516522b3234d36e2 Mon Sep 17 00:00:00 2001 From: Wilson Tang Date: Wed, 1 Nov 2017 23:41:35 -0400 Subject: [PATCH 22/41] fpga edits 1 --- spimemory_fpga.v | 30 +++++++++++++++--------------- 1 file changed, 15 insertions(+), 15 deletions(-) diff --git a/spimemory_fpga.v b/spimemory_fpga.v index 6c94403..706ed76 100644 --- a/spimemory_fpga.v +++ b/spimemory_fpga.v @@ -292,25 +292,25 @@ endmodule module spiMemory(clk,sw,led); input clk; input [2:0] sw; - output reg [3:0] led; + output reg [3:0] led; wire[7:0] parallelData; // ParallelData Out - wire[6:0] address; // address + wire[6:0] address; // address wire[7:0] shiftregister; // Current Shift Register Values wire miso; // current miso value wire res_sel; // Select between display options wire parallelslc; // select parallel input wire serialin; // binary input for serial input - wire serialout; // serial output of shift register + wire serialout; // serial output of shift register wire posSCLK; // clk edge for serial input - wire negSCLK; // - wire CS ; // chip select - wire Flag; // R/W flag - wire miso_buff; // miso_buff - wire dm_we; // dm_we - wire addr_we; // addr_we - wire sr_we; // sr_we - wire output_ff_out; // output ff output + wire negSCLK; // + wire CS ; // chip select + wire Flag; // R/W flag + wire miso_buff; // miso_buff + wire dm_we; // dm_we + wire addr_we; // addr_we + wire sr_we; // sr_we + wire output_ff_out; // output ff output //Map to input conditioners @@ -319,14 +319,14 @@ module spiMemory(clk,sw,led); inputconditioner CS_conditioner(.noisysignal(sw[2]),.clk(clk),.conditioned(CS)); //finite statemachine - fsm fsm(.POS_EDGE(posSCLK),.CS(sw[2]),.shiftRegOutP0(Flag),.MISO_BUFF(miso_buff),.DM_WE(dm_we),.ADDR_WE(sr_we),.SR_WE(sr_we)); + fsm finite_statemachine(.clk(clk),.POS_EDGE(posSCLK),.CS(sw[2]),.shiftRegOutP0(Flag),.MISO_BUFF(miso_buff),.DM_WE(dm_we),.ADDR_WE(sr_we),.SR_WE(sr_we)); //Address Latch dlatch addr_latch(.data(parallelData),.clk(clk),.addr_we(addr_we),.addr(address)); - dff output_ff(.trigger(clk),.enable(negSCLK),.d(serialout),.q(output_ff_out)); + dff output_ff(.trigger(clk),.enable(negSCLK),.d(serialout),.q(output_ff_out)); - tristatebuffer outbuffer(.out(miso),.in(output_ff_out),.en(miso_buff)); + tristatebuffer outbuffer(.out(miso),.in(output_ff_out),.en(miso_buff)); shiftregister shifted(.clk(clk),.peripheralClkEdge(posSCLK),.parallelLoad(parallelslc),.parallelDataIn(parallelData),.serialDataIn(serialin),.parallelDataOut(shiftregister)); @@ -338,7 +338,7 @@ module spiMemory(clk,sw,led); // Assign bits of shiftregister to appropriate display boxes initial begin led[0] <= miso; - if (miso == 1'bz ) begin + if (miso === 1'bz ) begin led[3] <= 1 ; end end From fc8ea63fa5f2e11c8e6a786fb6189eca8602d5ad Mon Sep 17 00:00:00 2001 From: Bryan Werth Date: Wed, 1 Nov 2017 23:52:28 -0400 Subject: [PATCH 23/41] Fixed spi memory --- spimemory.v | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/spimemory.v b/spimemory.v index 9dfcb22..7365573 100644 --- a/spimemory.v +++ b/spimemory.v @@ -236,20 +236,20 @@ module spiMemory(clk,sclk_pin,cs_pin,miso_pin,mosi_pin,leds); inputconditioner CS_conditioner(.noisysignal(cs_pin),.clk(clk),.conditioned(CS)); //finite statemachine - fsm fsm_process(.POS_EDGE(posSCLK),.CS(CS),.shiftRegOutP0(parallelOut[0]),.clk(clk),.MISO_BUFF(miso_buff),.DM_WE(dm_we),.ADDR_WE(sr_we),.SR_WE(sr_we)); + fsm fsm_process(.POS_EDGE(posSCLK),.CS(CS),.shiftRegOutP0(parallelOut[0]),.clk(clk),.MISO_BUFF(miso_buff),.DM_WE(dm_we),.ADDR_WE(addr_we),.SR_WE(sr_we)); //Address Latch - dlatch addr_latch(.data(parallelData),.clk(clk),.addr_we(addr_we),.addr(address)); + dlatch addr_latch(.data(parallelOut),.clk(clk),.addr_we(addr_we),.addr(address)); dff output_ff(.trigger(clk),.enable(negSCLK),.d(serialout),.q(output_ff_out)); tristatebuffer outbuffer(.out(miso_pin),.in(output_ff_out),.en(miso_buff)); - shiftregister shifted(.clk(clk),.peripheralClkEdge(posSCLK),.parallelLoad(parallelslc),.parallelDataIn(parallelData),.serialDataIn(serialin),.parallelDataOut(parallelOut)); + shiftregister shifted(.clk(clk),.peripheralClkEdge(posSCLK),.parallelLoad(sr_we),.parallelDataIn(parallelData),.serialDataIn(serialin),.parallelDataOut(parallelOut),.serialDataOut(serialout)); //data memory - datamemory data(.clk(clk),.address(address),.writeEnable(dm_we),.dataIn(shiftregister)); + datamemory data(.clk(clk),.address(address),.writeEnable(dm_we),.dataIn(parallelOut),.dataOut(parallelData)); // Assign bits of shiftregister to appropriate display boxes From f231e30adbb95b7be12c2928e9457f8e9bd1bf8c Mon Sep 17 00:00:00 2001 From: Bryan Werth Date: Wed, 1 Nov 2017 23:54:29 -0400 Subject: [PATCH 24/41] Fixed spi memory --- spimemory.v | 79 +++++++++++++++++++++++++++-------------------------- 1 file changed, 40 insertions(+), 39 deletions(-) diff --git a/spimemory.v b/spimemory.v index 4d405b7..7365573 100644 --- a/spimemory.v +++ b/spimemory.v @@ -53,12 +53,12 @@ module jkff1 endmodule module tristatebuffer(out,in,en); - input in; - input en; - output out; - - assign out = en ? in : 1'bz; - + input in; + input en; + output out; + + assign out = en ? in : 1'bz; + endmodule // Two-input MUX with parameterized bit width (default: 1-bit) @@ -75,31 +75,31 @@ endmodule module dff #(parameter W = 1) ( - input trigger, - input enable, - input [W-1:0] d, - output reg [W-1:0] q + input trigger, + input enable, + input [W-1:0] d, + output reg [W-1:0] q ); - always @ (posedge trigger) begin - if(enable) begin - q <=d; - end - end + always @ (posedge trigger) begin + if(enable) begin + q <=d; + end + end endmodule module dlatch ( - input [7:0] data , - input clk, - input addr_we, - output reg [6:0] addr + input [7:0] data , + input clk, + input addr_we, + output reg [6:0] addr ); always @(posedge clk) begin - if(addr_we) begin - addr = data[7:1]; - end + if(addr_we) begin + addr = data[7:1]; + end end endmodule @@ -206,29 +206,29 @@ endmodule module spiMemory(clk,sclk_pin,cs_pin,miso_pin,mosi_pin,leds); input clk; - input sclk_pin; - input cs_pin; + input sclk_pin; + input cs_pin; output miso_pin; - input mosi_pin; - output [3:0] leds; + input mosi_pin; + output [3:0] leds; wire[7:0] parallelData; // ParallelData Out - wire[6:0] address; // address + wire[6:0] address; // address wire[3:0] res0, res1; // wire[7:0] parallelOut; // Current Shift Register Values wire res_sel; // Select between display options wire parallelslc; // select parallel input wire serialin; // binary input for serial input - wire serialout; // serial output of shift register + wire serialout; // serial output of shift register wire posSCLK; // clk edge for serial input - wire negSCLK; // - wire CS ; // chip select - wire Flag; // R/W flag - wire miso_buff; // miso_buff - wire dm_we; // dm_we - wire addr_we; // addr_we - wire sr_we; // sr_we - wire output_ff_out; // output ff output + wire negSCLK; // + wire CS ; // chip select + wire Flag; // R/W flag + wire miso_buff; // miso_buff + wire dm_we; // dm_we + wire addr_we; // addr_we + wire sr_we; // sr_we + wire output_ff_out; // output ff output //Map to input conditioners inputconditioner MOSI_conditioner(.noisysignal(mosi_pin),.clk(clk),.conditioned(serialin)); @@ -241,9 +241,9 @@ module spiMemory(clk,sclk_pin,cs_pin,miso_pin,mosi_pin,leds); //Address Latch dlatch addr_latch(.data(parallelOut),.clk(clk),.addr_we(addr_we),.addr(address)); - dff output_ff(.trigger(clk),.enable(negSCLK),.d(serialout),.q(output_ff_out)); - - tristatebuffer outbuffer(.out(miso_pin),.in(output_ff_out),.en(miso_buff)); + dff output_ff(.trigger(clk),.enable(negSCLK),.d(serialout),.q(output_ff_out)); + + tristatebuffer outbuffer(.out(miso_pin),.in(output_ff_out),.en(miso_buff)); shiftregister shifted(.clk(clk),.peripheralClkEdge(posSCLK),.parallelLoad(sr_we),.parallelDataIn(parallelData),.serialDataIn(serialin),.parallelDataOut(parallelOut),.serialDataOut(serialout)); @@ -263,3 +263,4 @@ module spiMemory(clk,sclk_pin,cs_pin,miso_pin,mosi_pin,leds); assign res1[3] = parallelOut[7]; endmodule + From e63207dcd1b85650f956d0bc92e17dcfe8f54168 Mon Sep 17 00:00:00 2001 From: Wilson Tang Date: Wed, 1 Nov 2017 23:59:13 -0400 Subject: [PATCH 25/41] updated spimemory --- spimemory_fpga.v | 31 +++++++++++++++---------------- 1 file changed, 15 insertions(+), 16 deletions(-) diff --git a/spimemory_fpga.v b/spimemory_fpga.v index d4f98f5..75337b4 100644 --- a/spimemory_fpga.v +++ b/spimemory_fpga.v @@ -292,25 +292,25 @@ endmodule module spiMemory(clk,sw,led); input clk; input [2:0] sw; - output reg [3:0] led; + output reg [3:0] led; wire[7:0] parallelData; // ParallelData Out - wire[6:0] address; // address - wire[7:0] shiftregister; // Current Shift Register Values + wire[6:0] address; // address + wire[7:0] parallelOut; // Current Shift Register Values wire miso; // current miso value wire res_sel; // Select between display options wire parallelslc; // select parallel input wire serialin; // binary input for serial input - wire serialout; // serial output of shift register + wire serialout; // serial output of shift register wire posSCLK; // clk edge for serial input - wire negSCLK; // - wire CS ; // chip select - wire Flag; // R/W flag - wire miso_buff; // miso_buff - wire dm_we; // dm_we - wire addr_we; // addr_we - wire sr_we; // sr_we - wire output_ff_out; // output ff output + wire negSCLK; // + wire CS ; // chip select + wire Flag; // R/W flag + wire miso_buff; // miso_buff + wire dm_we; // dm_we + wire addr_we; // addr_we + wire sr_we; // sr_we + wire output_ff_out; // output ff output //Map to input conditioners @@ -319,7 +319,7 @@ module spiMemory(clk,sw,led); inputconditioner CS_conditioner(.noisysignal(sw[2]),.clk(clk),.conditioned(CS)); //finite statemachine - fsm finite_statemachine(.clk(clk),.POS_EDGE(posSCLK),.CS(sw[2]),.shiftRegOutP0(Flag),.MISO_BUFF(miso_buff),.DM_WE(dm_we),.ADDR_WE(sr_we),.SR_WE(sr_we)); + fsm fsm_process(.POS_EDGE(posSCLK),.CS(CS),.shiftRegOutP0(parallelOut[0]),.clk(clk),.MISO_BUFF(miso_buff),.DM_WE(dm_we),.ADDR_WE(addr_we),.SR_WE(sr_we)); //Address Latch dlatch addr_latch(.data(parallelData),.clk(clk),.addr_we(addr_we),.addr(address)); @@ -327,12 +327,11 @@ module spiMemory(clk,sw,led); dff output_ff(.trigger(clk),.enable(negSCLK),.d(serialout),.q(output_ff_out)); tristatebuffer outbuffer(.out(miso),.in(output_ff_out),.en(miso_buff)); - - shiftregister shifted(.clk(clk),.peripheralClkEdge(posSCLK),.parallelLoad(parallelslc),.parallelDataIn(parallelData),.serialDataIn(serialin),.parallelDataOut(shiftregister)); + shiftregister shifted(.clk(clk),.peripheralClkEdge(posSCLK),.parallelLoad(sr_we),.parallelDataIn(parallelData),.serialDataIn(serialin),.parallelDataOut(parallelOut),.serialDataOut(serialout)); //data memory - datamemory data(.clk(clk),.address(address),.writeEnable(dm_we),.dataIn(shiftregister)); + datamemory data(.clk(clk),.address(address),.writeEnable(dm_we),.dataIn(parallelOut),.dataOut(parallelData)); // Assign bits of shiftregister to appropriate display boxes From 95517bde798d78bdc42cc07b223d595bf8c54cd6 Mon Sep 17 00:00:00 2001 From: Bryan Werth Date: Thu, 2 Nov 2017 00:05:11 -0400 Subject: [PATCH 26/41] Fixed spi memory organizationally --- spimemory.v | 38 ++++++++++++++++++++------------------ 1 file changed, 20 insertions(+), 18 deletions(-) diff --git a/spimemory.v b/spimemory.v index 7365573..512bba9 100644 --- a/spimemory.v +++ b/spimemory.v @@ -229,14 +229,26 @@ module spiMemory(clk,sclk_pin,cs_pin,miso_pin,mosi_pin,leds); wire addr_we; // addr_we wire sr_we; // sr_we wire output_ff_out; // output ff output - + + // Assign bits of shiftregister to appropriate display boxes + assign res0[0] = parallelOut[0]; + assign res0[1] = parallelOut[1]; + assign res0[2] = parallelOut[2]; + assign res0[3] = parallelOut[3]; + assign res1[0] = parallelOut[4]; + assign res1[1] = parallelOut[5]; + assign res1[2] = parallelOut[6]; + assign res1[3] = parallelOut[7]; + //Map to input conditioners - inputconditioner MOSI_conditioner(.noisysignal(mosi_pin),.clk(clk),.conditioned(serialin)); - inputconditioner SCLK(.noisysignal(sclk_pin),.clk(clk),.positiveedge(posSCLK),.negativeedge(negSCLK)); - inputconditioner CS_conditioner(.noisysignal(cs_pin),.clk(clk),.conditioned(CS)); + //(clk,noisysignal,conditioned,positiveedge,negativeedge); + inputconditioner MOSI_conditioner(.clk(clk),.conditioned(serialin),.noisysignal(mosi_pin)); + inputconditioner SCLK(.clk(clk),.noisysignal(sclk_pin),.positiveedge(posSCLK),.negativeedge(negSCLK)); + inputconditioner CS_conditioner(.clk(clk),.conditioned(CS),.noisysignal(cs_pin)); //finite statemachine - fsm fsm_process(.POS_EDGE(posSCLK),.CS(CS),.shiftRegOutP0(parallelOut[0]),.clk(clk),.MISO_BUFF(miso_buff),.DM_WE(dm_we),.ADDR_WE(addr_we),.SR_WE(sr_we)); + //(MISO_BUFF,DM_WE,ADDR_WE,SR_WE,POS_EDGE,CS,shiftRegOutP0,clk) + fsm fsm_process(.MISO_BUFF(miso_buff),.DM_WE(dm_we),.ADDR_WE(addr_we),.SR_WE(sr_we),.POS_EDGE(posSCLK),.CS(CS),.shiftRegOutP0(parallelOut[0]),.clk(clk)); //Address Latch dlatch addr_latch(.data(parallelOut),.clk(clk),.addr_we(addr_we),.addr(address)); @@ -245,22 +257,12 @@ module spiMemory(clk,sclk_pin,cs_pin,miso_pin,mosi_pin,leds); tristatebuffer outbuffer(.out(miso_pin),.in(output_ff_out),.en(miso_buff)); - + //(clk,peripheralClkEdge,parallelLoad,parallelDataIn,serialDataIn,parallelDataOut,serialDataOut) shiftregister shifted(.clk(clk),.peripheralClkEdge(posSCLK),.parallelLoad(sr_we),.parallelDataIn(parallelData),.serialDataIn(serialin),.parallelDataOut(parallelOut),.serialDataOut(serialout)); //data memory - datamemory data(.clk(clk),.address(address),.writeEnable(dm_we),.dataIn(parallelOut),.dataOut(parallelData)); - - - // Assign bits of shiftregister to appropriate display boxes - assign res0[0] = parallelOut[0]; - assign res0[1] = parallelOut[1]; - assign res0[2] = parallelOut[2]; - assign res0[3] = parallelOut[3]; - assign res1[0] = parallelOut[4]; - assign res1[1] = parallelOut[5]; - assign res1[2] = parallelOut[6]; - assign res1[3] = parallelOut[7]; + //clk,dataOut,address,writeEnable,dataIn + datamemory data(.clk(clk),.dataOut(parallelData),.address(address),.writeEnable(dm_we),.dataIn(parallelOut)); endmodule From 5fee3772882d48b3fdddb6511827bebc392e428e Mon Sep 17 00:00:00 2001 From: Bryan Werth Date: Thu, 2 Nov 2017 00:09:14 -0400 Subject: [PATCH 27/41] Updated fsm within spimemory_fpga.v --- spimemory_fpga.v | 19 +++++++++++++------ 1 file changed, 13 insertions(+), 6 deletions(-) diff --git a/spimemory_fpga.v b/spimemory_fpga.v index 75337b4..53b7454 100644 --- a/spimemory_fpga.v +++ b/spimemory_fpga.v @@ -202,6 +202,11 @@ endmodule // //------------------------------------------------------------------------ +// MISO_BUFF DM_WE ADDR_WE SR_WE +//CS 0 0 0 0 +//~CS 0 0 1 1 +//shiftRegOutP[0] 1 0 0 1 +//~shiftRegOutP[0]0 1 0 0 module fsm(MISO_BUFF,DM_WE,ADDR_WE,SR_WE,POS_EDGE,CS,shiftRegOutP0,clk); input POS_EDGE; input CS; @@ -224,7 +229,7 @@ module fsm(MISO_BUFF,DM_WE,ADDR_WE,SR_WE,POS_EDGE,CS,shiftRegOutP0,clk); input [1:0] state; input POS_EDGE; input CS; - input ShiftRegOutP0; + input shiftRegOutP0; case(state) 2'b00:if(!CS) begin fsm_function = 2'b01; @@ -246,25 +251,27 @@ module fsm(MISO_BUFF,DM_WE,ADDR_WE,SR_WE,POS_EDGE,CS,shiftRegOutP0,clk); always @ (posedge clk) begin state <= next_state; - if (state == 2'b00) begin + if (next_state == 2'b00) begin MISO_BUFF <= 0; DM_WE <= 0; SR_WE <= 0; - end else if (state == 2'b01) begin - if(counter==0) begin + ADDR_WE <= 0; + end else if (next_state == 2'b01) begin + if(POS_EDGE) begin counter <= 1; end SR_WE <= 1; - end else if (state == 2'b10) begin + end else if (next_state == 2'b10) begin MISO_BUFF <= 1; ADDR_WE <= 0; - end else if (state == 2'b11) begin + end else if (next_state == 2'b11) begin DM_WE <= 1; ADDR_WE <= 0; SR_WE <= 0; end if (counter==7)begin ADDR_WE<=1; + counter <= counter + 1; end else if (counter==8)begin ADDR_WE <=0; From c5eba8d8c0bf0e69c7ece491d3592d99f902130e Mon Sep 17 00:00:00 2001 From: Bryan Werth Date: Thu, 2 Nov 2017 00:16:04 -0400 Subject: [PATCH 28/41] Finished readding everything to spimemory_fpga.v --- spimemory_fpga.v | 95 +++++++++++++++++++++++++++++------------------- 1 file changed, 58 insertions(+), 37 deletions(-) diff --git a/spimemory_fpga.v b/spimemory_fpga.v index 53b7454..0f8cb7d 100644 --- a/spimemory_fpga.v +++ b/spimemory_fpga.v @@ -73,6 +73,13 @@ endmodule // 3) Creates pulses at edge transitions //------------------------------------------------------------------------ +//------------------------------------------------------------------------ +// Input Conditioner +// 1) Synchronizes input to clock domain +// 2) Debounces input +// 3) Creates pulses at edge transitions +//------------------------------------------------------------------------ + module inputconditioner (clk,noisysignal,conditioned,positiveedge,negativeedge); @@ -91,27 +98,27 @@ module inputconditioner reg conditioned1 = 0; always @(posedge clk ) begin - if(conditioned == 0 && conditioned1 == 1) begin - negativeedge = 1; - end else if (conditioned == 1 && conditioned1 == 0) begin - positiveedge = 1; + if(conditioned1 == 0 && conditioned == 1) begin + negativeedge = 1; + end else if (conditioned1 == 1 && conditioned == 0) begin + positiveedge = 1; end else if (positiveedge == 1 || negativeedge == 1) begin positiveedge = 0; negativeedge = 0; end - if(conditioned == synchronizer1) + if(conditioned1 == synchronizer1) counter <= 0; else begin if( counter == waittime) begin counter <= 0; - conditioned <= synchronizer1; + conditioned1 <= synchronizer1; end else counter <= counter+1; end synchronizer0 <= noisysignal; synchronizer1 <= synchronizer0; - conditioned1 <= conditioned; + conditioned <= conditioned1; end endmodule @@ -123,6 +130,14 @@ endmodule // - parallel in, serial out //------------------------------------------------------------------------ +//------------------------------------------------------------------------ +// Shift Register +// Parameterized width (in bits) +// Shift register can operate in two modes: +// - serial in, parallel out +// - parallel in, serial out +//------------------------------------------------------------------------ + module shiftregister #(parameter width = 8) ( @@ -141,15 +156,15 @@ output reg serialDataOut // Positive edge synchronized if(parallelLoad==1) begin // load the register with parallelDataIn - shiftregistermem <= parallelDataIn; + shiftregistermem <= parallelDataIn; end else if(parallelLoad==0) begin - if(peripheralClkEdge==1) begin - //grab the MSB as SDO and then shift everything over 1 place - serialDataOut <= shiftregistermem[width-1]; - shiftregistermem<={shiftregistermem[width-2:0],serialDataIn}; - end + if(peripheralClkEdge==1) begin + //grab the MSB as SDO and then shift everything over 1 place + serialDataOut <= shiftregistermem[width-1]; + shiftregistermem<={shiftregistermem[width-2:0],serialDataIn}; + end end //parallelDataOut is just the current state of the register parallelDataOut <= shiftregistermem; @@ -301,50 +316,56 @@ module spiMemory(clk,sw,led); input [2:0] sw; output reg [3:0] led; - wire[7:0] parallelData; // ParallelData Out - wire[6:0] address; // address - wire[7:0] parallelOut; // Current Shift Register Values - wire miso; // current miso value + wire[7:0] parallelData; // ParallelData Out + wire[6:0] address; // address + wire[3:0] res0, res1; // + wire[7:0] parallelOut; // Current Shift Register Values wire res_sel; // Select between display options wire parallelslc; // select parallel input wire serialin; // binary input for serial input - wire serialout; // serial output of shift register + wire serialout; // serial output of shift register wire posSCLK; // clk edge for serial input - wire negSCLK; // - wire CS ; // chip select - wire Flag; // R/W flag - wire miso_buff; // miso_buff - wire dm_we; // dm_we - wire addr_we; // addr_we - wire sr_we; // sr_we - wire output_ff_out; // output ff output + wire negSCLK; // + wire CS ; // chip select + wire Flag; // R/W flag + wire miso_buff; // miso_buff + wire dm_we; // dm_we + wire addr_we; // addr_we + wire sr_we; // sr_we + wire output_ff_out; // output ff output + wire miso; - //Map to input conditioners - inputconditioner MOSI_conditioner(.noisysignal(sw[0]),.clk(clk),.conditioned(serialin)); - inputconditioner SCLK(.noisysignal(sw[1]),.clk(clk),.positiveedge(posSCLK),.negativeedge(negSCLK)); - inputconditioner CS_conditioner(.noisysignal(sw[2]),.clk(clk),.conditioned(CS)); + //Map to input conditioners noisy signal sw[0]...sw[2] + //(clk,noisysignal,conditioned,positiveedge,negativeedge); + inputconditioner MOSI_conditioner(.clk(clk),.conditioned(serialin),.noisysignal(sw[0])); + inputconditioner SCLK(.clk(clk),.noisysignal(sw[1]),.positiveedge(posSCLK),.negativeedge(negSCLK)); + inputconditioner CS_conditioner(.clk(clk),.conditioned(CS),.noisysignal(sw[2])); //finite statemachine - fsm fsm_process(.POS_EDGE(posSCLK),.CS(CS),.shiftRegOutP0(parallelOut[0]),.clk(clk),.MISO_BUFF(miso_buff),.DM_WE(dm_we),.ADDR_WE(addr_we),.SR_WE(sr_we)); + //(MISO_BUFF,DM_WE,ADDR_WE,SR_WE,POS_EDGE,CS,shiftRegOutP0,clk) + fsm fsm_process(.MISO_BUFF(miso_buff),.DM_WE(dm_we),.ADDR_WE(addr_we),.SR_WE(sr_we),.POS_EDGE(posSCLK),.CS(CS),.shiftRegOutP0(parallelOut[0]),.clk(clk)); //Address Latch - dlatch addr_latch(.data(parallelData),.clk(clk),.addr_we(addr_we),.addr(address)); + dlatch addr_latch(.data(parallelOut),.clk(clk),.addr_we(addr_we),.addr(address)); - dff output_ff(.trigger(clk),.enable(negSCLK),.d(serialout),.q(output_ff_out)); - - tristatebuffer outbuffer(.out(miso),.in(output_ff_out),.en(miso_buff)); + dff output_ff(.trigger(clk),.enable(negSCLK),.d(serialout),.q(output_ff_out)); + + tristatebuffer outbuffer(.out(miso_pin),.in(output_ff_out),.en(miso_buff)); + //(clk,peripheralClkEdge,parallelLoad,parallelDataIn,serialDataIn,parallelDataOut,serialDataOut) shiftregister shifted(.clk(clk),.peripheralClkEdge(posSCLK),.parallelLoad(sr_we),.parallelDataIn(parallelData),.serialDataIn(serialin),.parallelDataOut(parallelOut),.serialDataOut(serialout)); //data memory - datamemory data(.clk(clk),.address(address),.writeEnable(dm_we),.dataIn(parallelOut),.dataOut(parallelData)); + //clk,dataOut,address,writeEnable,dataIn + datamemory data(.clk(clk),.dataOut(parallelData),.address(address),.writeEnable(dm_we),.dataIn(parallelOut)); + // Assign bits of shiftregister to appropriate display boxes initial begin led[0] <= miso; - if (miso == 1'bz ) begin + if (miso === 1'bz ) begin led[3] <= 1 ; end end From 2365796ce34a1347e3dd580af4c1c6debd5faa6c Mon Sep 17 00:00:00 2001 From: Bryan Werth Date: Thu, 2 Nov 2017 00:24:09 -0400 Subject: [PATCH 29/41] Fixed the outputs of spimemory_fpga.v --- spimemory_fpga.v | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/spimemory_fpga.v b/spimemory_fpga.v index 0f8cb7d..cd546b2 100644 --- a/spimemory_fpga.v +++ b/spimemory_fpga.v @@ -364,8 +364,9 @@ module spiMemory(clk,sw,led); // Assign bits of shiftregister to appropriate display boxes initial begin - led[0] <= miso; - if (miso === 1'bz ) begin + if (miso) begin + led[0] <= 1; + end else if (miso === 1'bz ) begin led[3] <= 1 ; end end From 1c73271d40a1b8a60ac59693b624c0e9b629941a Mon Sep 17 00:00:00 2001 From: Wilson Tang Date: Thu, 2 Nov 2017 00:39:44 -0400 Subject: [PATCH 30/41] spi merge --- spimemory.v | 117 ++++++++++++++++++++++++++-------------------------- 1 file changed, 59 insertions(+), 58 deletions(-) diff --git a/spimemory.v b/spimemory.v index 7365573..a6ef118 100644 --- a/spimemory.v +++ b/spimemory.v @@ -53,12 +53,12 @@ module jkff1 endmodule module tristatebuffer(out,in,en); - input in; - input en; - output out; - - assign out = en ? in : 1'bz; - + input in; + input en; + output out; + + assign out = en ? in : 1'bz; + endmodule // Two-input MUX with parameterized bit width (default: 1-bit) @@ -75,31 +75,31 @@ endmodule module dff #(parameter W = 1) ( - input trigger, - input enable, - input [W-1:0] d, - output reg [W-1:0] q + input trigger, + input enable, + input [W-1:0] d, + output reg [W-1:0] q ); - always @ (posedge trigger) begin - if(enable) begin - q <=d; - end - end + always @ (posedge trigger) begin + if(enable) begin + q <=d; + end + end endmodule module dlatch ( - input [7:0] data , - input clk, - input addr_we, - output reg [6:0] addr + input [7:0] data , + input clk, + input addr_we, + output reg [6:0] addr ); always @(posedge clk) begin - if(addr_we) begin - addr = data[7:1]; - end + if(addr_we) begin + addr = data[7:1]; + end end endmodule @@ -206,61 +206,62 @@ endmodule module spiMemory(clk,sclk_pin,cs_pin,miso_pin,mosi_pin,leds); input clk; - input sclk_pin; - input cs_pin; + input sclk_pin; + input cs_pin; output miso_pin; - input mosi_pin; - output [3:0] leds; + input mosi_pin; + output [3:0] leds; wire[7:0] parallelData; // ParallelData Out - wire[6:0] address; // address + wire[6:0] address; // address wire[3:0] res0, res1; // wire[7:0] parallelOut; // Current Shift Register Values wire res_sel; // Select between display options wire parallelslc; // select parallel input wire serialin; // binary input for serial input - wire serialout; // serial output of shift register + wire serialout; // serial output of shift register wire posSCLK; // clk edge for serial input - wire negSCLK; // - wire CS ; // chip select - wire Flag; // R/W flag - wire miso_buff; // miso_buff - wire dm_we; // dm_we - wire addr_we; // addr_we - wire sr_we; // sr_we - wire output_ff_out; // output ff output + wire negSCLK; // + wire CS ; // chip select + wire Flag; // R/W flag + wire miso_buff; // miso_buff + wire dm_we; // dm_we + wire addr_we; // addr_we + wire sr_we; // sr_we + wire output_ff_out; // output ff output + + // Assign bits of shiftregister to appropriate display boxes + assign res0[0] = parallelOut[0]; + assign res0[1] = parallelOut[1]; + assign res0[2] = parallelOut[2]; + assign res0[3] = parallelOut[3]; + assign res1[0] = parallelOut[4]; + assign res1[1] = parallelOut[5]; + assign res1[2] = parallelOut[6]; + assign res1[3] = parallelOut[7]; //Map to input conditioners - inputconditioner MOSI_conditioner(.noisysignal(mosi_pin),.clk(clk),.conditioned(serialin)); - inputconditioner SCLK(.noisysignal(sclk_pin),.clk(clk),.positiveedge(posSCLK),.negativeedge(negSCLK)); - inputconditioner CS_conditioner(.noisysignal(cs_pin),.clk(clk),.conditioned(CS)); + //(clk,noisysignal,conditioned,positiveedge,negativeedge); + inputconditioner MOSI_conditioner(.clk(clk),.conditioned(serialin),.noisysignal(mosi_pin)); + inputconditioner SCLK(.clk(clk),.noisysignal(sclk_pin),.positiveedge(posSCLK),.negativeedge(negSCLK)); + inputconditioner CS_conditioner(.clk(clk),.conditioned(CS),.noisysignal(cs_pin)); //finite statemachine - fsm fsm_process(.POS_EDGE(posSCLK),.CS(CS),.shiftRegOutP0(parallelOut[0]),.clk(clk),.MISO_BUFF(miso_buff),.DM_WE(dm_we),.ADDR_WE(addr_we),.SR_WE(sr_we)); + //(MISO_BUFF,DM_WE,ADDR_WE,SR_WE,POS_EDGE,CS,shiftRegOutP0,clk) + fsm fsm_process(.MISO_BUFF(miso_buff),.DM_WE(dm_we),.ADDR_WE(addr_we),.SR_WE(sr_we),.POS_EDGE(posSCLK),.CS(CS),.shiftRegOutP0(parallelOut[0]),.clk(clk)); //Address Latch dlatch addr_latch(.data(parallelOut),.clk(clk),.addr_we(addr_we),.addr(address)); - dff output_ff(.trigger(clk),.enable(negSCLK),.d(serialout),.q(output_ff_out)); - - tristatebuffer outbuffer(.out(miso_pin),.in(output_ff_out),.en(miso_buff)); - + dff output_ff(.trigger(clk),.enable(negSCLK),.d(serialout),.q(output_ff_out)); + + tristatebuffer outbuffer(.out(miso_pin),.in(output_ff_out),.en(miso_buff)); + //(clk,peripheralClkEdge,parallelLoad,parallelDataIn,serialDataIn,parallelDataOut,serialDataOut) shiftregister shifted(.clk(clk),.peripheralClkEdge(posSCLK),.parallelLoad(sr_we),.parallelDataIn(parallelData),.serialDataIn(serialin),.parallelDataOut(parallelOut),.serialDataOut(serialout)); //data memory - datamemory data(.clk(clk),.address(address),.writeEnable(dm_we),.dataIn(parallelOut),.dataOut(parallelData)); - - - // Assign bits of shiftregister to appropriate display boxes - assign res0[0] = parallelOut[0]; - assign res0[1] = parallelOut[1]; - assign res0[2] = parallelOut[2]; - assign res0[3] = parallelOut[3]; - assign res1[0] = parallelOut[4]; - assign res1[1] = parallelOut[5]; - assign res1[2] = parallelOut[6]; - assign res1[3] = parallelOut[7]; + //clk,dataOut,address,writeEnable,dataIn + datamemory data(.clk(clk),.dataOut(parallelData),.address(address),.writeEnable(dm_we),.dataIn(parallelOut)); -endmodule - +endmodule \ No newline at end of file From f9ea9a6fe0ad58e4193e4d8255c59aef77feb798 Mon Sep 17 00:00:00 2001 From: Wilson Tang Date: Thu, 2 Nov 2017 00:48:27 -0400 Subject: [PATCH 31/41] added filler wire --- spimemory.v | 24 +++++++----------------- 1 file changed, 7 insertions(+), 17 deletions(-) diff --git a/spimemory.v b/spimemory.v index 475b504..c6a331f 100644 --- a/spimemory.v +++ b/spimemory.v @@ -212,10 +212,9 @@ module spiMemory(clk,sclk_pin,cs_pin,miso_pin,mosi_pin,leds); input mosi_pin; output [3:0] leds; - wire[7:0] parallelData; // ParallelData Out + wire[7:0] parallelData; // ParallelData Out wire[6:0] address; // address - wire[3:0] res0, res1; // - wire[7:0] parallelOut; // Current Shift Register Values + wire[7:0] parallelOut; // Current Shift Register Values wire res_sel; // Select between display options wire parallelslc; // select parallel input wire serialin; // binary input for serial input @@ -228,23 +227,14 @@ module spiMemory(clk,sclk_pin,cs_pin,miso_pin,mosi_pin,leds); wire dm_we; // dm_we wire addr_we; // addr_we wire sr_we; // sr_we - wire output_ff_out; // output ff output - - // Assign bits of shiftregister to appropriate display boxes - assign res0[0] = parallelOut[0]; - assign res0[1] = parallelOut[1]; - assign res0[2] = parallelOut[2]; - assign res0[3] = parallelOut[3]; - assign res1[0] = parallelOut[4]; - assign res1[1] = parallelOut[5]; - assign res1[2] = parallelOut[6]; - assign res1[3] = parallelOut[7]; + wire output_ff_out; // output ff output + wire filler; // filler wire //Map to input conditioners //(clk,noisysignal,conditioned,positiveedge,negativeedge); - inputconditioner MOSI_conditioner(.clk(clk),.conditioned(serialin),.noisysignal(mosi_pin)); - inputconditioner SCLK(.clk(clk),.noisysignal(sclk_pin),.positiveedge(posSCLK),.negativeedge(negSCLK)); - inputconditioner CS_conditioner(.clk(clk),.conditioned(CS),.noisysignal(cs_pin)); + inputconditioner MOSI_conditioner(.clk(clk),.noisysignal(mosi_pin),.conditioned(serialin),.positiveedge(filler),.negativeedge(filler)); + inputconditioner SCLK(.clk(clk),.noisysignal(sclk_pin),.conditioned(filler),.positiveedge(posSCLK),.negativeedge(negSCLK)); + inputconditioner CS_conditioner(.clk(clk),.noisysignal(cs_pin),conditioned(CS),.positiveedge(filler),.negativeedge(filler)); //finite statemachine //(MISO_BUFF,DM_WE,ADDR_WE,SR_WE,POS_EDGE,CS,shiftRegOutP0,clk) From dfc240c7e7d692bbe80c958979c7afaf8412bd8a Mon Sep 17 00:00:00 2001 From: Bryan Werth Date: Thu, 2 Nov 2017 12:41:05 -0400 Subject: [PATCH 32/41] Made a first pass at the function required for the test bench. I only did read, but write should be the same, just with a 16 bit mosi_pin input --- spimemory_testbench.v | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) create mode 100644 spimemory_testbench.v diff --git a/spimemory_testbench.v b/spimemory_testbench.v new file mode 100644 index 0000000..17a9a85 --- /dev/null +++ b/spimemory_testbench.v @@ -0,0 +1,21 @@ +task read; +input sclk; +input clk; +input [7:0] readAddress; +wire i = 0; +begin + cs = 0; + repeat (16) begin + @ (posedge clk) begin + if (i<=7) begin + mosi_pin = readAddress[i]; + i = i + 1; + sclk_pin = sclk; //or whatever the sclk input is + end else begin + sclk_pin = sclk; + i = i + 1; + end + end + end + cs = 1; +end \ No newline at end of file From 16717c81bceb47070e1e31df5d09b57ad9afdc2c Mon Sep 17 00:00:00 2001 From: Wilson Tang Date: Thu, 2 Nov 2017 19:43:54 -0400 Subject: [PATCH 33/41] spimemory.t.v --- datamemory.v | 2 +- spimemory.v | 8 ++++++-- 2 files changed, 7 insertions(+), 3 deletions(-) diff --git a/datamemory.v b/datamemory.v index 0d82131..02225af 100644 --- a/datamemory.v +++ b/datamemory.v @@ -17,7 +17,7 @@ module datamemory input [addresswidth-1:0] address, input writeEnable, input [width-1:0] dataIn -) +); reg [width-1:0] memory [depth-1:0]; diff --git a/spimemory.v b/spimemory.v index c6a331f..02d1d3b 100644 --- a/spimemory.v +++ b/spimemory.v @@ -1,3 +1,7 @@ + +`include "fsm.v" +`include "datamemory.v" + //------------------------------------------------------------------------ // SPI Memory //------------------------------------------------------------------------ @@ -222,7 +226,7 @@ module spiMemory(clk,sclk_pin,cs_pin,miso_pin,mosi_pin,leds); wire posSCLK; // clk edge for serial input wire negSCLK; // wire CS ; // chip select - wire Flag; // R/W flag + wire Flag; // R/W flag wire miso_buff; // miso_buff wire dm_we; // dm_we wire addr_we; // addr_we @@ -234,7 +238,7 @@ module spiMemory(clk,sclk_pin,cs_pin,miso_pin,mosi_pin,leds); //(clk,noisysignal,conditioned,positiveedge,negativeedge); inputconditioner MOSI_conditioner(.clk(clk),.noisysignal(mosi_pin),.conditioned(serialin),.positiveedge(filler),.negativeedge(filler)); inputconditioner SCLK(.clk(clk),.noisysignal(sclk_pin),.conditioned(filler),.positiveedge(posSCLK),.negativeedge(negSCLK)); - inputconditioner CS_conditioner(.clk(clk),.noisysignal(cs_pin),conditioned(CS),.positiveedge(filler),.negativeedge(filler)); + inputconditioner CS_conditioner(.clk(clk),.noisysignal(cs_pin),.conditioned(CS),.positiveedge(filler),.negativeedge(filler)); //finite statemachine //(MISO_BUFF,DM_WE,ADDR_WE,SR_WE,POS_EDGE,CS,shiftRegOutP0,clk) From d3ba0ac99be5187837ba042872114a39dc970e3d Mon Sep 17 00:00:00 2001 From: Wilson Tang Date: Thu, 2 Nov 2017 19:44:28 -0400 Subject: [PATCH 34/41] spimemory.t.v --- spimemory.t.v | 90 +++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 90 insertions(+) create mode 100644 spimemory.t.v diff --git a/spimemory.t.v b/spimemory.t.v new file mode 100644 index 0000000..8f2cecb --- /dev/null +++ b/spimemory.t.v @@ -0,0 +1,90 @@ +`include "spimemory.v" + +module testspimemory(); + reg clk; // FPGA clock + reg sclk_pin; // SPI clock + reg cs_pin; // SPI chip select + wire miso_pin; // SPI master in slave out, has memory address + reg mosi_pin; // SPI master out slave in, for reading + wire [3:0] leds; // leds + reg [15:0] data; // data + + spiMemory dut(.clk(clk), + .sclk_pin(sclk_pin), + .cs_pin(cs_pin), + .miso_pin(miso_pin), + .mosi_pin(mosi_pin), + .leds(leds) + ); + + // generating the clock and initialize system + initial begin + sclk_pin = 0; + clk=0; + end + always #50 clk=!clk; // 50MHz Clock + always #50 sclk_pin=!sclk_pin; + + initial begin + + + cs_pin = 1; #500 + + //Test Case 1: Write: Address: 00000010 Data: 111111111 + + data = 16'b0000001011111111; + + cs_pin = 0; #100 + + mosi_pin = data[15]; #100 + mosi_pin = data[14]; #100 + mosi_pin = data[13]; #100 + mosi_pin = data[12]; #100 + mosi_pin = data[11]; #100 + mosi_pin = data[10]; #100 + mosi_pin = data[9]; #100 + + mosi_pin = data[8]; #100 + + mosi_pin = data[7]; #100 + mosi_pin = data[6]; #100 + mosi_pin = data[5]; #100 + mosi_pin = data[4]; #100 + mosi_pin = data[3]; #100 + mosi_pin = data[2]; #100 + mosi_pin = data[1]; #100 + mosi_pin = data[0]; #100 + + //checkSPI spi_case1(.data(16'b0000001011111111),.clk(clk),.slck(slck),.cs_pin(cs_pin),.mosi_pin(mosi_pin)); + + #100 + + cs_pin = 1; #600 + + // TestCase 2: Read: Address: 00000011 Data: 111111111 + + mosi_pin = data[15]; #100 + mosi_pin = data[14]; #100 + mosi_pin = data[13]; #100 + mosi_pin = data[12]; #100 + mosi_pin = data[11]; #100 + mosi_pin = data[10]; #100 + mosi_pin = data[9]; #100 + + mosi_pin = data[8]; #100 + + if ((miso_pin != data[7])) $display ("Test Failed at Read Element 1: %b ", miso_pin); #100 + if ((miso_pin != data[6])) $display ("Test Failed at Read Element 1: %b ", miso_pin); #100 + if ((miso_pin != data[5])) $display ("Test Failed at Read Element 1: %b ", miso_pin); #100 + if ((miso_pin != data[4])) $display ("Test Failed at Read Element 1: %b ", miso_pin); #100 + if ((miso_pin != data[3])) $display ("Test Failed at Read Element 1: %b ", miso_pin); #100 + if ((miso_pin != data[2])) $display ("Test Failed at Read Element 1: %b ", miso_pin); #100 + if ((miso_pin != data[1])) $display ("Test Failed at Read Element 1: %b ", miso_pin); #100 + if ((miso_pin != data[0])) $display ("Test Failed at Read Element 1: %b ", miso_pin); #100 + //checkSPI spi_case2(.data(16'b0000001111111111),.clk(clk),.slck(slck),.cs_pin(cs_pin),.mosi_pin(mosi_pin)); + + #100 $finish; + end + +endmodule + From 04328332b32a3943cefa1fbaacb9efe0558a26af Mon Sep 17 00:00:00 2001 From: Wilson Tang Date: Thu, 2 Nov 2017 20:31:09 -0400 Subject: [PATCH 35/41] test case 3 --- spimemory.t.v | 42 ++++++++++++++++++++++++++++++++++++++---- 1 file changed, 38 insertions(+), 4 deletions(-) diff --git a/spimemory.t.v b/spimemory.t.v index 8f2cecb..88bcde0 100644 --- a/spimemory.t.v +++ b/spimemory.t.v @@ -22,7 +22,7 @@ module testspimemory(); sclk_pin = 0; clk=0; end - always #50 clk=!clk; // 50MHz Clock + always #5 clk=!clk; // 50MHz Clock always #50 sclk_pin=!sclk_pin; initial begin @@ -32,6 +32,7 @@ module testspimemory(); //Test Case 1: Write: Address: 00000010 Data: 111111111 + $display ("Initialize Testing"); data = 16'b0000001011111111; cs_pin = 0; #100 @@ -61,7 +62,9 @@ module testspimemory(); cs_pin = 1; #600 - // TestCase 2: Read: Address: 00000011 Data: 111111111 + // TestCase 2: Read: Address: 00000011 + + data = 16'b0000001111111111; mosi_pin = data[15]; #100 mosi_pin = data[14]; #100 @@ -69,11 +72,11 @@ module testspimemory(); mosi_pin = data[12]; #100 mosi_pin = data[11]; #100 mosi_pin = data[10]; #100 - mosi_pin = data[9]; #100 + mosi_pin = data[9]; #1001 mosi_pin = data[8]; #100 - if ((miso_pin != data[7])) $display ("Test Failed at Read Element 1: %b ", miso_pin); #100 + if ((miso_pin != data[7])) begin $display ("Test Failed at Read Element 1: %b ", miso_pin); end #100 if ((miso_pin != data[6])) $display ("Test Failed at Read Element 1: %b ", miso_pin); #100 if ((miso_pin != data[5])) $display ("Test Failed at Read Element 1: %b ", miso_pin); #100 if ((miso_pin != data[4])) $display ("Test Failed at Read Element 1: %b ", miso_pin); #100 @@ -83,8 +86,39 @@ module testspimemory(); if ((miso_pin != data[0])) $display ("Test Failed at Read Element 1: %b ", miso_pin); #100 //checkSPI spi_case2(.data(16'b0000001111111111),.clk(clk),.slck(slck),.cs_pin(cs_pin),.mosi_pin(mosi_pin)); + cs_pin = 0; #100 + + // TestCase 3: Read other Address: 000000101 + // Check to make sure that our Write didnt write to other parts + + data = 16'b0000010111111111; + + mosi_pin = data[15]; #100 + mosi_pin = data[14]; #100 + mosi_pin = data[13]; #100 + mosi_pin = data[12]; #100 + mosi_pin = data[11]; #100 + mosi_pin = data[10]; #100 + mosi_pin = data[9]; #100 + + mosi_pin = data[8]; #100 + + $display ("Testing ongoing"); + if ((miso_pin != 0)) $display ("Test Failed at Read Element 1: %b ", miso_pin); #100 + if ((miso_pin != 0)) $display ("Test Failed at Read Element 1: %b ", miso_pin); #100 + if ((miso_pin != 0)) $display ("Test Failed at Read Element 1: %b ", miso_pin); #100 + if ((miso_pin != 0)) $display ("Test Failed at Read Element 1: %b ", miso_pin); #100 + if ((miso_pin != 0)) $display ("Test Failed at Read Element 1: %b ", miso_pin); #100 + if ((miso_pin != 0)) $display ("Test Failed at Read Element 1: %b ", miso_pin); #100 + if ((miso_pin != 0)) $display ("Test Failed at Read Element 1: %b ", miso_pin); #100 + if ((miso_pin != 1)) begin $display ("Test Failed at Read Element 1: %b ", miso_pin); end #100 + + //checkSPI spi_case2(.data(16'b0000001111111111),.clk(clk),.slck(slck),.cs_pin(cs_pin),.mosi_pin(mosi_pin)); #100 $finish; end endmodule + + + From 0d9e4b65fa8e5344350842fe8a70e422952466c6 Mon Sep 17 00:00:00 2001 From: Bryan Werth Date: Thu, 2 Nov 2017 22:06:05 -0400 Subject: [PATCH 36/41] commit --- fsm.v | 12 +++++------- spimemory.t.v | 46 +++++++++++++++++++++++++++++++--------------- spimemory.v | 17 +++++++++++++---- spimemory_fpga.v | 2 -- 4 files changed, 49 insertions(+), 28 deletions(-) diff --git a/fsm.v b/fsm.v index a145d44..6570940 100644 --- a/fsm.v +++ b/fsm.v @@ -3,11 +3,10 @@ //~CS 0 0 1 1 //shiftRegOutP[0] 1 0 0 1 //~shiftRegOutP[0]0 1 0 0 -module fsm(MISO_BUFF,DM_WE,ADDR_WE,SR_WE,POS_EDGE,CS,shiftRegOutP0,clk); +module fsm(MISO_BUFF,DM_WE,ADDR_WE,SR_WE,POS_EDGE,CS,shiftRegOutP0); input POS_EDGE; input CS; input shiftRegOutP0; - input clk; output MISO_BUFF; output DM_WE; output ADDR_WE; @@ -19,11 +18,10 @@ module fsm(MISO_BUFF,DM_WE,ADDR_WE,SR_WE,POS_EDGE,CS,shiftRegOutP0,clk); parameter counter_num_bits = 4; reg[counter_num_bits-1:0] counter = 0; - assign next_state = fsm_function(state,POS_EDGE,CS,shiftRegOutP0); + assign next_state = fsm_function(state,CS,shiftRegOutP0); function [1:0] fsm_function; input [1:0] state; - input POS_EDGE; input CS; input shiftRegOutP0; case(state) @@ -45,7 +43,7 @@ module fsm(MISO_BUFF,DM_WE,ADDR_WE,SR_WE,POS_EDGE,CS,shiftRegOutP0,clk); endcase endfunction - always @ (posedge clk) begin + always @ (posedge POS_EDGE) begin state <= next_state; if (next_state == 2'b00) begin MISO_BUFF <= 0; @@ -53,13 +51,13 @@ module fsm(MISO_BUFF,DM_WE,ADDR_WE,SR_WE,POS_EDGE,CS,shiftRegOutP0,clk); SR_WE <= 0; ADDR_WE <= 0; end else if (next_state == 2'b01) begin - if(POS_EDGE) begin + if(counter == 0) begin counter <= 1; end - SR_WE <= 1; end else if (next_state == 2'b10) begin MISO_BUFF <= 1; ADDR_WE <= 0; + SR_WE <= 1; end else if (next_state == 2'b11) begin DM_WE <= 1; ADDR_WE <= 0; diff --git a/spimemory.t.v b/spimemory.t.v index 88bcde0..be8cf61 100644 --- a/spimemory.t.v +++ b/spimemory.t.v @@ -1,33 +1,50 @@ `include "spimemory.v" module testspimemory(); - reg clk; // FPGA clock - reg sclk_pin; // SPI clock + reg clk = 0; // FPGA clock + reg sclk_pin = 0; // SPI clock reg cs_pin; // SPI chip select wire miso_pin; // SPI master in slave out, has memory address reg mosi_pin; // SPI master out slave in, for reading wire [3:0] leds; // leds reg [15:0] data; // data + wire serialin; + wire posSCLK; + wire CS; + wire miso_buff; + wire shiftRegOutP; + wire [7:0] parallelOut; + wire [7:0] parallelData; + wire sr_we; spiMemory dut(.clk(clk), .sclk_pin(sclk_pin), .cs_pin(cs_pin), .miso_pin(miso_pin), .mosi_pin(mosi_pin), - .leds(leds) + .leds(leds), + .serialin(serialin), + .posSCLK(posSCLK), + .CS(CS), + .miso_buff(miso_buff), + .shiftRegOutP(shiftRegOutP), + .parallelOut(parallelOut), + .parallelData(parallelData), + .sr_we(sr_we) ); - // generating the clock and initialize system - initial begin - sclk_pin = 0; - clk=0; - end - always #5 clk=!clk; // 50MHz Clock - always #50 sclk_pin=!sclk_pin; + initial begin + forever begin + clk = !clk; #5; + end + end // 50MHz Clock + initial begin + forever begin + sclk_pin = !sclk_pin; #50; + end + end initial begin - - cs_pin = 1; #500 //Test Case 1: Write: Address: 00000010 Data: 111111111 @@ -76,7 +93,7 @@ module testspimemory(); mosi_pin = data[8]; #100 - if ((miso_pin != data[7])) begin $display ("Test Failed at Read Element 1: %b ", miso_pin); end #100 + if ((miso_pin != data[7])) $display ("Test Failed at Read Element 1: %b ", miso_pin); #100 if ((miso_pin != data[6])) $display ("Test Failed at Read Element 1: %b ", miso_pin); #100 if ((miso_pin != data[5])) $display ("Test Failed at Read Element 1: %b ", miso_pin); #100 if ((miso_pin != data[4])) $display ("Test Failed at Read Element 1: %b ", miso_pin); #100 @@ -111,10 +128,9 @@ module testspimemory(); if ((miso_pin != 0)) $display ("Test Failed at Read Element 1: %b ", miso_pin); #100 if ((miso_pin != 0)) $display ("Test Failed at Read Element 1: %b ", miso_pin); #100 if ((miso_pin != 0)) $display ("Test Failed at Read Element 1: %b ", miso_pin); #100 - if ((miso_pin != 1)) begin $display ("Test Failed at Read Element 1: %b ", miso_pin); end #100 + if ((miso_pin != 1)) begin $display ("Test Failed at Read Element 1: %b ", miso_pin); end #100; //checkSPI spi_case2(.data(16'b0000001111111111),.clk(clk),.slck(slck),.cs_pin(cs_pin),.mosi_pin(mosi_pin)); - #100 $finish; end endmodule diff --git a/spimemory.v b/spimemory.v index 02d1d3b..ecac44a 100644 --- a/spimemory.v +++ b/spimemory.v @@ -29,8 +29,6 @@ // on the right. //-------------------------------------------------------------------------------- -`timescale 1ns / 1ps - //-------------------------------------------------------------------------------- // Basic building block modules //-------------------------------------------------------------------------------- @@ -208,13 +206,21 @@ endmodule // Write: //-------------------------------------------------------------------------------- -module spiMemory(clk,sclk_pin,cs_pin,miso_pin,mosi_pin,leds); +module spiMemory(clk,sclk_pin,cs_pin,miso_pin,mosi_pin,leds,serialin,posSCLK,CS,miso_buff,shiftRegOutP,parallelOut,parallelData,sr_we); input clk; input sclk_pin; input cs_pin; output miso_pin; input mosi_pin; output [3:0] leds; + output serialin; + output posSCLK; + output CS; + output miso_buff; + output shiftRegOutP; + output [7:0] parallelOut; + output [7:0] parallelData; + output sr_we; wire[7:0] parallelData; // ParallelData Out wire[6:0] address; // address @@ -233,7 +239,10 @@ module spiMemory(clk,sclk_pin,cs_pin,miso_pin,mosi_pin,leds); wire sr_we; // sr_we wire output_ff_out; // output ff output wire filler; // filler wire + wire shiftRegOutP; + assign shiftRegOutP = parallelOut[0]; + //Map to input conditioners //(clk,noisysignal,conditioned,positiveedge,negativeedge); inputconditioner MOSI_conditioner(.clk(clk),.noisysignal(mosi_pin),.conditioned(serialin),.positiveedge(filler),.negativeedge(filler)); @@ -242,7 +251,7 @@ module spiMemory(clk,sclk_pin,cs_pin,miso_pin,mosi_pin,leds); //finite statemachine //(MISO_BUFF,DM_WE,ADDR_WE,SR_WE,POS_EDGE,CS,shiftRegOutP0,clk) - fsm fsm_process(.MISO_BUFF(miso_buff),.DM_WE(dm_we),.ADDR_WE(addr_we),.SR_WE(sr_we),.POS_EDGE(posSCLK),.CS(CS),.shiftRegOutP0(parallelOut[0]),.clk(clk)); + fsm fsm_process(.MISO_BUFF(miso_buff),.DM_WE(dm_we),.ADDR_WE(addr_we),.SR_WE(sr_we),.POS_EDGE(posSCLK),.CS(CS),.shiftRegOutP0(parallelOut[0])); //Address Latch dlatch addr_latch(.data(parallelOut),.clk(clk),.addr_we(addr_we),.addr(address)); diff --git a/spimemory_fpga.v b/spimemory_fpga.v index cd546b2..526d0f8 100644 --- a/spimemory_fpga.v +++ b/spimemory_fpga.v @@ -18,8 +18,6 @@ // on the right. //-------------------------------------------------------------------------------- -`timescale 1ns / 1ps - //-------------------------------------------------------------------------------- // Basic building block modules //-------------------------------------------------------------------------------- From 51b52ae7e3b6b187605bd7033cb9005010809f02 Mon Sep 17 00:00:00 2001 From: Bryan Werth Date: Thu, 2 Nov 2017 22:38:39 -0400 Subject: [PATCH 37/41] updated fsm --- fsm.v | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/fsm.v b/fsm.v index 6570940..93bd6f4 100644 --- a/fsm.v +++ b/fsm.v @@ -18,7 +18,7 @@ module fsm(MISO_BUFF,DM_WE,ADDR_WE,SR_WE,POS_EDGE,CS,shiftRegOutP0); parameter counter_num_bits = 4; reg[counter_num_bits-1:0] counter = 0; - assign next_state = fsm_function(state,CS,shiftRegOutP0); + function [1:0] fsm_function; input [1:0] state; @@ -44,7 +44,7 @@ module fsm(MISO_BUFF,DM_WE,ADDR_WE,SR_WE,POS_EDGE,CS,shiftRegOutP0); endfunction always @ (posedge POS_EDGE) begin - state <= next_state; + next_state <= fsm_function(state,CS,shiftRegOutP0); if (next_state == 2'b00) begin MISO_BUFF <= 0; DM_WE <= 0; From 956bd8f425a059a385f042f1a33586b166d459ad Mon Sep 17 00:00:00 2001 From: Bryan Werth Date: Thu, 2 Nov 2017 22:40:35 -0400 Subject: [PATCH 38/41] fixed error in fsm --- fsm.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/fsm.v b/fsm.v index 93bd6f4..a29dea7 100644 --- a/fsm.v +++ b/fsm.v @@ -14,7 +14,7 @@ module fsm(MISO_BUFF,DM_WE,ADDR_WE,SR_WE,POS_EDGE,CS,shiftRegOutP0); reg [1:0] state; reg MISO_BUFF,DM_WE,ADDR_WE,SR_WE; - wire [1:0] next_state; + reg [1:0] next_state; parameter counter_num_bits = 4; reg[counter_num_bits-1:0] counter = 0; From 2e5967e1ad29530c10f5308b0510d00599a89828 Mon Sep 17 00:00:00 2001 From: Wilson Tang Date: Fri, 3 Nov 2017 14:01:14 -0400 Subject: [PATCH 39/41] merging --- spimemory.t.v | 52 +++++++++++++++++++++++++++++++-------------------- spimemory.v | 20 ++++++++++++++------ 2 files changed, 46 insertions(+), 26 deletions(-) diff --git a/spimemory.t.v b/spimemory.t.v index 88bcde0..ae5cdf2 100644 --- a/spimemory.t.v +++ b/spimemory.t.v @@ -1,33 +1,50 @@ `include "spimemory.v" module testspimemory(); - reg clk; // FPGA clock - reg sclk_pin; // SPI clock + reg clk = 0; // FPGA clock + reg sclk_pin = 0; // SPI clock reg cs_pin; // SPI chip select wire miso_pin; // SPI master in slave out, has memory address reg mosi_pin; // SPI master out slave in, for reading wire [3:0] leds; // leds reg [15:0] data; // data + wire serialin; + wire posSCLK; + wire CS; + wire miso_buff; + wire shiftRegOutP; + wire [7:0] parallelOut; + wire [7:0] parallelData; + wire sr_we; spiMemory dut(.clk(clk), .sclk_pin(sclk_pin), .cs_pin(cs_pin), .miso_pin(miso_pin), .mosi_pin(mosi_pin), - .leds(leds) + .leds(leds), + .serialin(serialin), + .posSCLK(posSCLK), + .CS(CS), + .miso_buff(miso_buff), + .shiftRegOutP(shiftRegOutP), + .parallelOut(parallelOut), + .parallelData(parallelData), + .sr_we(sr_we) ); - // generating the clock and initialize system - initial begin - sclk_pin = 0; - clk=0; - end - always #5 clk=!clk; // 50MHz Clock - always #50 sclk_pin=!sclk_pin; + initial begin + forever begin + clk = !clk; #5; + end + end // 50MHz Clock + initial begin + forever begin + sclk_pin = !sclk_pin; #50; + end + end initial begin - - cs_pin = 1; #500 //Test Case 1: Write: Address: 00000010 Data: 111111111 @@ -76,7 +93,7 @@ module testspimemory(); mosi_pin = data[8]; #100 - if ((miso_pin != data[7])) begin $display ("Test Failed at Read Element 1: %b ", miso_pin); end #100 + if ((miso_pin != data[7])) $display ("Test Failed at Read Element 1: %b ", miso_pin); #100 if ((miso_pin != data[6])) $display ("Test Failed at Read Element 1: %b ", miso_pin); #100 if ((miso_pin != data[5])) $display ("Test Failed at Read Element 1: %b ", miso_pin); #100 if ((miso_pin != data[4])) $display ("Test Failed at Read Element 1: %b ", miso_pin); #100 @@ -111,14 +128,9 @@ module testspimemory(); if ((miso_pin != 0)) $display ("Test Failed at Read Element 1: %b ", miso_pin); #100 if ((miso_pin != 0)) $display ("Test Failed at Read Element 1: %b ", miso_pin); #100 if ((miso_pin != 0)) $display ("Test Failed at Read Element 1: %b ", miso_pin); #100 - if ((miso_pin != 1)) begin $display ("Test Failed at Read Element 1: %b ", miso_pin); end #100 + if ((miso_pin != 1)) begin $display ("Test Failed at Read Element 1: %b ", miso_pin); end #100; //checkSPI spi_case2(.data(16'b0000001111111111),.clk(clk),.slck(slck),.cs_pin(cs_pin),.mosi_pin(mosi_pin)); - #100 $finish; end -endmodule - - - - +endmodule \ No newline at end of file diff --git a/spimemory.v b/spimemory.v index 02d1d3b..f02b1fb 100644 --- a/spimemory.v +++ b/spimemory.v @@ -1,4 +1,3 @@ - `include "fsm.v" `include "datamemory.v" @@ -29,8 +28,6 @@ // on the right. //-------------------------------------------------------------------------------- -`timescale 1ns / 1ps - //-------------------------------------------------------------------------------- // Basic building block modules //-------------------------------------------------------------------------------- @@ -208,13 +205,21 @@ endmodule // Write: //-------------------------------------------------------------------------------- -module spiMemory(clk,sclk_pin,cs_pin,miso_pin,mosi_pin,leds); +module spiMemory(clk,sclk_pin,cs_pin,miso_pin,mosi_pin,leds,serialin,posSCLK,CS,miso_buff,shiftRegOutP,parallelOut,parallelData,sr_we); input clk; input sclk_pin; input cs_pin; output miso_pin; input mosi_pin; output [3:0] leds; + output serialin; + output posSCLK; + output CS; + output miso_buff; + output shiftRegOutP; + output [7:0] parallelOut; + output [7:0] parallelData; + output sr_we; wire[7:0] parallelData; // ParallelData Out wire[6:0] address; // address @@ -233,6 +238,9 @@ module spiMemory(clk,sclk_pin,cs_pin,miso_pin,mosi_pin,leds); wire sr_we; // sr_we wire output_ff_out; // output ff output wire filler; // filler wire + wire shiftRegOutP; + + assign shiftRegOutP = parallelOut[0]; //Map to input conditioners //(clk,noisysignal,conditioned,positiveedge,negativeedge); @@ -242,7 +250,7 @@ module spiMemory(clk,sclk_pin,cs_pin,miso_pin,mosi_pin,leds); //finite statemachine //(MISO_BUFF,DM_WE,ADDR_WE,SR_WE,POS_EDGE,CS,shiftRegOutP0,clk) - fsm fsm_process(.MISO_BUFF(miso_buff),.DM_WE(dm_we),.ADDR_WE(addr_we),.SR_WE(sr_we),.POS_EDGE(posSCLK),.CS(CS),.shiftRegOutP0(parallelOut[0]),.clk(clk)); + fsm fsm_process(.MISO_BUFF(miso_buff),.DM_WE(dm_we),.ADDR_WE(addr_we),.SR_WE(sr_we),.POS_EDGE(posSCLK),.CS(CS),.shiftRegOutP0(parallelOut[0])); //Address Latch dlatch addr_latch(.data(parallelOut),.clk(clk),.addr_we(addr_we),.addr(address)); @@ -258,4 +266,4 @@ module spiMemory(clk,sclk_pin,cs_pin,miso_pin,mosi_pin,leds); //clk,dataOut,address,writeEnable,dataIn datamemory data(.clk(clk),.dataOut(parallelData),.address(address),.writeEnable(dm_we),.dataIn(parallelOut)); -endmodule +endmodule \ No newline at end of file From 5d0115e422e6f0dd9324b50116ce4d9e67f090f1 Mon Sep 17 00:00:00 2001 From: Bryan Werth Date: Wed, 13 Dec 2017 12:49:41 -0500 Subject: [PATCH 40/41] Finished finally --- fsm.v | 128 ++++++++++++++++++++++++++++++++++--------- spimemory.t.v | 149 ++++++++++++++++++++++++++++---------------------- spimemory.v | 62 +++++++++++++++------ writeup.pdf | Bin 0 -> 205464 bytes 4 files changed, 232 insertions(+), 107 deletions(-) create mode 100644 writeup.pdf diff --git a/fsm.v b/fsm.v index a29dea7..e9ab029 100644 --- a/fsm.v +++ b/fsm.v @@ -3,35 +3,49 @@ //~CS 0 0 1 1 //shiftRegOutP[0] 1 0 0 1 //~shiftRegOutP[0]0 1 0 0 -module fsm(MISO_BUFF,DM_WE,ADDR_WE,SR_WE,POS_EDGE,CS,shiftRegOutP0); +module fsm(MISO_BUFF,DM_WE,ADDR_WE,SR_WE,POS_EDGE,CS,shiftRegOutP0,clk,state,counter,relevant_shiftRegOutP0,clk_counter); input POS_EDGE; input CS; input shiftRegOutP0; + input clk; output MISO_BUFF; output DM_WE; output ADDR_WE; output SR_WE; - - reg [1:0] state; + output [1:0] state; + output [5:0] counter; + output [1:0] relevant_shiftRegOutP0; + output [5:0] clk_counter; + + wire [1:0] state; reg MISO_BUFF,DM_WE,ADDR_WE,SR_WE; reg [1:0] next_state; - parameter counter_num_bits = 4; + parameter counter_num_bits = 5; reg[counter_num_bits-1:0] counter = 0; + reg start_counter; + wire [1:0] previous_state; + reg [1:0] counter_type; + reg [1:0] relevant_shiftRegOutP0; + reg already_counted; + reg [5:0] clk_counter; + reg [1:0] counter_flag; - - + assign state = next_state; + function [1:0] fsm_function; input [1:0] state; input CS; - input shiftRegOutP0; + input relevant_shiftRegOutP0; case(state) 2'b00:if(!CS) begin fsm_function = 2'b01; end - 2'b01:if(shiftRegOutP0) begin + 2'b01:if(relevant_shiftRegOutP0 == 2'b10) begin fsm_function = 2'b10; - end else if (!shiftRegOutP0) begin + end else if (relevant_shiftRegOutP0 == 2'b01) begin fsm_function = 2'b11; + end else if (already_counted && counter == 0 && CS) begin + fsm_function = 2'b00; end 2'b10:if(CS) begin fsm_function = 2'b00; @@ -42,37 +56,101 @@ module fsm(MISO_BUFF,DM_WE,ADDR_WE,SR_WE,POS_EDGE,CS,shiftRegOutP0); default:fsm_function = 2'b00; endcase endfunction - + + always @ (posedge clk) begin + if(counter == 7) begin + clk_counter <= 1; + counter_flag <= 2'b01; + end else if (counter == 10 && relevant_shiftRegOutP0 == 2'b10) begin + clk_counter <= 1; + counter_flag <= 2'b10; + end else if (counter == 18 && relevant_shiftRegOutP0 == 2'b10) begin + clk_counter <= 1; + counter_flag <= 2'b11; + end else if (clk_counter == 3 && counter_flag == 2'b01) begin + relevant_shiftRegOutP0 <= shiftRegOutP0 ? 2'b10 : 2'b01; + clk_counter <= 0; + end else if (clk_counter == 6 && counter_flag == 2'b10) begin + MISO_BUFF <= 1; + clk_counter <= 0; + end else if (clk_counter == 6 && counter_flag == 2'b11) begin + MISO_BUFF <= 0; + clk_counter <= 0; + counter <= 0; + relevant_shiftRegOutP0 <= 2'b00; + end else if (clk_counter > 0) begin + clk_counter <= clk_counter + 1; + end + end + always @ (posedge POS_EDGE) begin - next_state <= fsm_function(state,CS,shiftRegOutP0); + next_state <= fsm_function(state,CS,relevant_shiftRegOutP0); if (next_state == 2'b00) begin MISO_BUFF <= 0; DM_WE <= 0; SR_WE <= 0; ADDR_WE <= 0; + already_counted <= 0; end else if (next_state == 2'b01) begin - if(counter == 0) begin + if(counter == 0 && !already_counted) begin counter <= 1; + counter_type <= 2'b01; + already_counted <= 1; end end else if (next_state == 2'b10) begin - MISO_BUFF <= 1; ADDR_WE <= 0; - SR_WE <= 1; + DM_WE <= 0; + if(counter > 0) begin + SR_WE <= 1; + MISO_BUFF <= 1; + end end else if (next_state == 2'b11) begin - DM_WE <= 1; + DM_WE <= 0; ADDR_WE <= 0; SR_WE <= 0; end - if (counter==7)begin - ADDR_WE<=1; + if (counter == 7) begin + ADDR_WE <= 1; + //relevant_shiftRegOutP0 <= shiftRegOutP0 ? 2'b10 : 2'b01; counter <= counter + 1; - end - else if (counter==8)begin - ADDR_WE <=0; - counter<=0; - end - else if (counter>0)begin - counter<=counter+1; - end + end else if (counter == 8) begin + ADDR_WE <= 0; + counter <= counter + 1; + end else if (counter == 9) begin + if (relevant_shiftRegOutP0 == 2'b10) begin + SR_WE <= 1; + end + counter <= counter + 1; + end else if (counter == 10) begin + SR_WE <= 0; + counter <= counter + 1; + //end else if (counter == ) begin + //if (next_state == 2'b10) begin + //MISO_BUFF <= 1; + //end + //counter <= counter + 1; + //end else if (counter == 10) begin + //if (relevant_shiftRegOutP0 == 2'b10) begin + // MISO_BUFF <= 1; + //end + end else if (counter == 15) begin + if (relevant_shiftRegOutP0 == 2'b01) begin + DM_WE <= 1; + end + counter <= counter + 1; + end else if (counter == 16) begin + DM_WE <= 0; + SR_WE <= 0; + //counter <= 0; + if (relevant_shiftRegOutP0 == 2'b01) begin + MISO_BUFF <= 0; + counter <= 0; + relevant_shiftRegOutP0 <= 2'b00; + end else if (relevant_shiftRegOutP0 == 2'b10) begin + counter <= counter + 1; + end + end else if (counter > 0) begin + counter <= counter + 1; + end end endmodule \ No newline at end of file diff --git a/spimemory.t.v b/spimemory.t.v index be8cf61..ed5c46e 100644 --- a/spimemory.t.v +++ b/spimemory.t.v @@ -8,7 +8,7 @@ module testspimemory(); reg mosi_pin; // SPI master out slave in, for reading wire [3:0] leds; // leds reg [15:0] data; // data - wire serialin; + wire buffered_serialin; wire posSCLK; wire CS; wire miso_buff; @@ -16,6 +16,15 @@ module testspimemory(); wire [7:0] parallelOut; wire [7:0] parallelData; wire sr_we; + wire dm_we; + wire [1:0] state; + wire conditioned_clk; + wire [4:0] counter; + wire output_ff_out; + wire addr_we; + wire [1:0] relevant_shiftRegOutP0; + wire [6:0] address; + wire [5:0] clk_counter; spiMemory dut(.clk(clk), .sclk_pin(sclk_pin), @@ -23,24 +32,33 @@ module testspimemory(); .miso_pin(miso_pin), .mosi_pin(mosi_pin), .leds(leds), - .serialin(serialin), + .buffered_serialin(buffered_serialin), .posSCLK(posSCLK), .CS(CS), .miso_buff(miso_buff), .shiftRegOutP(shiftRegOutP), .parallelOut(parallelOut), .parallelData(parallelData), - .sr_we(sr_we) + .sr_we(sr_we), + .dm_we(dm_we), + .state(state), + .conditioned_clk(conditioned_clk), + .counter(counter), + .output_ff_out(output_ff_out), + .addr_we(addr_we), + .relevant_shiftRegOutP0(relevant_shiftRegOutP0), + .address(address), + .clk_counter(clk_counter) ); initial begin forever begin - clk = !clk; #5; + clk = !clk; #1; end end // 50MHz Clock initial begin forever begin - sclk_pin = !sclk_pin; #50; + sclk_pin = !sclk_pin; #10; end end @@ -52,89 +70,88 @@ module testspimemory(); $display ("Initialize Testing"); data = 16'b0000001011111111; - cs_pin = 0; #100 - - mosi_pin = data[15]; #100 - mosi_pin = data[14]; #100 - mosi_pin = data[13]; #100 - mosi_pin = data[12]; #100 - mosi_pin = data[11]; #100 - mosi_pin = data[10]; #100 - mosi_pin = data[9]; #100 - - mosi_pin = data[8]; #100 - - mosi_pin = data[7]; #100 - mosi_pin = data[6]; #100 - mosi_pin = data[5]; #100 - mosi_pin = data[4]; #100 - mosi_pin = data[3]; #100 - mosi_pin = data[2]; #100 - mosi_pin = data[1]; #100 - mosi_pin = data[0]; #100 + cs_pin = 0; #20 + + mosi_pin = data[15]; #20 + mosi_pin = data[14]; #20 + mosi_pin = data[13]; #20 + mosi_pin = data[12]; #20 + mosi_pin = data[11]; #20 + mosi_pin = data[10]; #20 + mosi_pin = data[9]; #20 + + mosi_pin = 0; #20 + + mosi_pin = data[7]; #20 + mosi_pin = data[6]; #20 + mosi_pin = data[5]; #20 + mosi_pin = data[4]; #20 + mosi_pin = data[3]; #20 + mosi_pin = data[2]; #20 + mosi_pin = data[1]; #20 + mosi_pin = data[0]; #20 //checkSPI spi_case1(.data(16'b0000001011111111),.clk(clk),.slck(slck),.cs_pin(cs_pin),.mosi_pin(mosi_pin)); - #100 + #500 cs_pin = 1; #600 - // TestCase 2: Read: Address: 00000011 + // TestCase 2: Read: Address: 00000010 + + cs_pin = 0; #20 data = 16'b0000001111111111; - mosi_pin = data[15]; #100 - mosi_pin = data[14]; #100 - mosi_pin = data[13]; #100 - mosi_pin = data[12]; #100 - mosi_pin = data[11]; #100 - mosi_pin = data[10]; #100 - mosi_pin = data[9]; #1001 + mosi_pin = data[15]; #20 + mosi_pin = data[14]; #20 + mosi_pin = data[13]; #20 + mosi_pin = data[12]; #20 + mosi_pin = data[11]; #20 + mosi_pin = data[10]; #20 + mosi_pin = data[9]; #20 - mosi_pin = data[8]; #100 + mosi_pin = 1; #20 - if ((miso_pin != data[7])) $display ("Test Failed at Read Element 1: %b ", miso_pin); #100 - if ((miso_pin != data[6])) $display ("Test Failed at Read Element 1: %b ", miso_pin); #100 - if ((miso_pin != data[5])) $display ("Test Failed at Read Element 1: %b ", miso_pin); #100 - if ((miso_pin != data[4])) $display ("Test Failed at Read Element 1: %b ", miso_pin); #100 - if ((miso_pin != data[3])) $display ("Test Failed at Read Element 1: %b ", miso_pin); #100 - if ((miso_pin != data[2])) $display ("Test Failed at Read Element 1: %b ", miso_pin); #100 - if ((miso_pin != data[1])) $display ("Test Failed at Read Element 1: %b ", miso_pin); #100 - if ((miso_pin != data[0])) $display ("Test Failed at Read Element 1: %b ", miso_pin); #100 + if ((miso_pin != data[7])) $display ("Test Failed at Read Element 1: %b ", miso_pin); #20 + if ((miso_pin != data[6])) $display ("Test Failed at Read Element 1: %b ", miso_pin); #20 + if ((miso_pin != data[5])) $display ("Test Failed at Read Element 1: %b ", miso_pin); #20 + if ((miso_pin != data[4])) $display ("Test Failed at Read Element 1: %b ", miso_pin); #20 + if ((miso_pin != data[3])) $display ("Test Failed at Read Element 1: %b ", miso_pin); #20 + if ((miso_pin != data[2])) $display ("Test Failed at Read Element 1: %b ", miso_pin); #20 + if ((miso_pin != data[1])) $display ("Test Failed at Read Element 1: %b ", miso_pin); #20 + if ((miso_pin != data[0])) $display ("Test Failed at Read Element 1: %b ", miso_pin); #20 + #500 //checkSPI spi_case2(.data(16'b0000001111111111),.clk(clk),.slck(slck),.cs_pin(cs_pin),.mosi_pin(mosi_pin)); - - cs_pin = 0; #100 + cs_pin = 1; #600 + cs_pin = 0; #20 // TestCase 3: Read other Address: 000000101 // Check to make sure that our Write didnt write to other parts data = 16'b0000010111111111; - mosi_pin = data[15]; #100 - mosi_pin = data[14]; #100 - mosi_pin = data[13]; #100 - mosi_pin = data[12]; #100 - mosi_pin = data[11]; #100 - mosi_pin = data[10]; #100 - mosi_pin = data[9]; #100 + mosi_pin = data[15]; #20 + mosi_pin = data[14]; #20 + mosi_pin = data[13]; #20 + mosi_pin = data[12]; #20 + mosi_pin = data[11]; #20 + mosi_pin = data[10]; #20 + mosi_pin = data[9]; #20 - mosi_pin = data[8]; #100 + mosi_pin = 1; #20 $display ("Testing ongoing"); - if ((miso_pin != 0)) $display ("Test Failed at Read Element 1: %b ", miso_pin); #100 - if ((miso_pin != 0)) $display ("Test Failed at Read Element 1: %b ", miso_pin); #100 - if ((miso_pin != 0)) $display ("Test Failed at Read Element 1: %b ", miso_pin); #100 - if ((miso_pin != 0)) $display ("Test Failed at Read Element 1: %b ", miso_pin); #100 - if ((miso_pin != 0)) $display ("Test Failed at Read Element 1: %b ", miso_pin); #100 - if ((miso_pin != 0)) $display ("Test Failed at Read Element 1: %b ", miso_pin); #100 - if ((miso_pin != 0)) $display ("Test Failed at Read Element 1: %b ", miso_pin); #100 - if ((miso_pin != 1)) begin $display ("Test Failed at Read Element 1: %b ", miso_pin); end #100; + if ((miso_pin != 0)) $display ("Test Failed at Read Element 1: %b ", miso_pin); #20 + if ((miso_pin != 0)) $display ("Test Failed at Read Element 1: %b ", miso_pin); #20 + if ((miso_pin != 0)) $display ("Test Failed at Read Element 1: %b ", miso_pin); #20 + if ((miso_pin != 0)) $display ("Test Failed at Read Element 1: %b ", miso_pin); #20 + if ((miso_pin != 0)) $display ("Test Failed at Read Element 1: %b ", miso_pin); #20 + if ((miso_pin != 0)) $display ("Test Failed at Read Element 1: %b ", miso_pin); #20 + if ((miso_pin != 0)) $display ("Test Failed at Read Element 1: %b ", miso_pin); #20 + if ((miso_pin != 1)) begin $display ("Test Failed at Read Element 1: %b ", miso_pin); end #20; //checkSPI spi_case2(.data(16'b0000001111111111),.clk(clk),.slck(slck),.cs_pin(cs_pin),.mosi_pin(mosi_pin)); end -endmodule - - - - +endmodule \ No newline at end of file diff --git a/spimemory.v b/spimemory.v index ecac44a..56312ab 100644 --- a/spimemory.v +++ b/spimemory.v @@ -100,7 +100,7 @@ module dlatch always @(posedge clk) begin if(addr_we) begin - addr = data[7:1]; + addr <= data[7:1]; end end @@ -117,7 +117,7 @@ module inputconditioner (clk,noisysignal,conditioned,positiveedge,negativeedge); parameter counterwidth = 3; // Counter size, in bits, >= log2(waittime) - parameter waittime = 3; // Debounce delay, in clock cycles + parameter waittime = 1; // Debounce delay, in clock cycles input clk; input noisysignal; @@ -131,27 +131,27 @@ module inputconditioner reg conditioned1 = 0; always @(posedge clk ) begin - if(conditioned == 0 && conditioned1 == 1) begin - negativeedge = 1; - end else if (conditioned == 1 && conditioned1 == 0) begin - positiveedge = 1; + if(conditioned1 == 0 && conditioned == 1) begin + negativeedge = 1; + end else if (conditioned1 == 1 && conditioned == 0) begin + positiveedge = 1; end else if (positiveedge == 1 || negativeedge == 1) begin positiveedge = 0; negativeedge = 0; end - if(conditioned == synchronizer1) + if(conditioned1 == synchronizer1) counter <= 0; else begin if( counter == waittime) begin counter <= 0; - conditioned <= synchronizer1; + conditioned1 <= synchronizer1; end else counter <= counter+1; end synchronizer0 <= noisysignal; synchronizer1 <= synchronizer0; - conditioned1 <= conditioned; + conditioned <= conditioned1; end endmodule @@ -206,14 +206,14 @@ endmodule // Write: //-------------------------------------------------------------------------------- -module spiMemory(clk,sclk_pin,cs_pin,miso_pin,mosi_pin,leds,serialin,posSCLK,CS,miso_buff,shiftRegOutP,parallelOut,parallelData,sr_we); +module spiMemory(clk,sclk_pin,cs_pin,miso_pin,mosi_pin,leds,buffered_serialin,posSCLK,CS,miso_buff,shiftRegOutP,parallelOut,parallelData,sr_we,dm_we,state,conditioned_clk,counter,output_ff_out,addr_we,relevant_shiftRegOutP0,address,clk_counter); input clk; input sclk_pin; input cs_pin; output miso_pin; input mosi_pin; output [3:0] leds; - output serialin; + output buffered_serialin; output posSCLK; output CS; output miso_buff; @@ -221,7 +221,16 @@ module spiMemory(clk,sclk_pin,cs_pin,miso_pin,mosi_pin,leds,serialin,posSCLK,CS, output [7:0] parallelOut; output [7:0] parallelData; output sr_we; - + output dm_we; + output [1:0] state; + output conditioned_clk; + output [4:0] counter; + output output_ff_out; + output addr_we; + output [1:0] relevant_shiftRegOutP0; + output [6:0] address; + output [5:0] clk_counter; + wire[7:0] parallelData; // ParallelData Out wire[6:0] address; // address wire[7:0] parallelOut; // Current Shift Register Values @@ -240,19 +249,40 @@ module spiMemory(clk,sclk_pin,cs_pin,miso_pin,mosi_pin,leds,serialin,posSCLK,CS, wire output_ff_out; // output ff output wire filler; // filler wire wire shiftRegOutP; - + wire [1:0] state; + wire conditioned_clk; + wire [4:0] counter; + wire buffered_serialin; + wire buffered_posSCLK; assign shiftRegOutP = parallelOut[0]; + wire [1:0] relevant_shiftRegOutP0; + wire miso_buff_d2,miso_buff_d1,dm_we_d2,dm_we_d1,addr_we_d2,addr_we_d1,sr_we_d2,sr_we_d1; + wire [5:0] clk_counter; + wire clk; //Map to input conditioners //(clk,noisysignal,conditioned,positiveedge,negativeedge); inputconditioner MOSI_conditioner(.clk(clk),.noisysignal(mosi_pin),.conditioned(serialin),.positiveedge(filler),.negativeedge(filler)); - inputconditioner SCLK(.clk(clk),.noisysignal(sclk_pin),.conditioned(filler),.positiveedge(posSCLK),.negativeedge(negSCLK)); + inputconditioner SCLK(.clk(clk),.noisysignal(sclk_pin),.conditioned(conditioned_clk),.positiveedge(posSCLK),.negativeedge(negSCLK)); inputconditioner CS_conditioner(.clk(clk),.noisysignal(cs_pin),.conditioned(CS),.positiveedge(filler),.negativeedge(filler)); //finite statemachine //(MISO_BUFF,DM_WE,ADDR_WE,SR_WE,POS_EDGE,CS,shiftRegOutP0,clk) - fsm fsm_process(.MISO_BUFF(miso_buff),.DM_WE(dm_we),.ADDR_WE(addr_we),.SR_WE(sr_we),.POS_EDGE(posSCLK),.CS(CS),.shiftRegOutP0(parallelOut[0])); + fsm fsm_process(.MISO_BUFF(miso_buff),.DM_WE(dm_we),.ADDR_WE(addr_we),.SR_WE(sr_we),.POS_EDGE(posSCLK),.CS(CS),.shiftRegOutP0(parallelOut[0]),.clk(clk),.state(state),.counter(counter),.relevant_shiftRegOutP0(relevant_shiftRegOutP0),.clk_counter(clk_counter)); + //dff miso_buff_buffer2(.trigger(clk),.enable(1'b1),.d(miso_buff_d2),.q(miso_buff_d1)); + //dff mis_buff_buffer1(.trigger(clk),.enable(1'b1),.d(miso_buff_d1),.q(miso_buff)); + + //dff dm_we_buffer2(.trigger(clk),.enable(1'b1),.d(dm_we_d2),.q(dm_we_d1)); + //dff dm_we_buffer1(.trigger(clk),.enable(1'b1),.d(dm_we_d1),.q(dm_we)); + + //dff addr_we_buffer2(.trigger(clk),.enable(1'b1),.d(addr_we_d2),.q(addr_we_d1)); + //dff addr_we_buffer1(.trigger(clk),.enable(1'b1),.d(addr_we_d1),.q(addr_we)); + + //dff sr_we_buffer2(.trigger(clk),.enable(1'b1),.d(sr_we_d2),.q(sr_we_d1)); + //dff sr_we_buffer1(.trigger(clk),.enable(1'b1),.d(sr_we_d1),.q(sr_we)); + + dff serialin_buffer(.trigger(posSCLK),.enable(1'b1),.d(serialin),.q(buffered_serialin)); //Address Latch dlatch addr_latch(.data(parallelOut),.clk(clk),.addr_we(addr_we),.addr(address)); @@ -261,7 +291,7 @@ module spiMemory(clk,sclk_pin,cs_pin,miso_pin,mosi_pin,leds,serialin,posSCLK,CS, tristatebuffer outbuffer(.out(miso_pin),.in(output_ff_out),.en(miso_buff)); //(clk,peripheralClkEdge,parallelLoad,parallelDataIn,serialDataIn,parallelDataOut,serialDataOut) - shiftregister shifted(.clk(clk),.peripheralClkEdge(posSCLK),.parallelLoad(sr_we),.parallelDataIn(parallelData),.serialDataIn(serialin),.parallelDataOut(parallelOut),.serialDataOut(serialout)); + shiftregister shifted(.clk(clk),.peripheralClkEdge(posSCLK),.parallelLoad(sr_we),.parallelDataIn(parallelData),.serialDataIn(buffered_serialin),.parallelDataOut(parallelOut),.serialDataOut(serialout)); //data memory //clk,dataOut,address,writeEnable,dataIn diff --git a/writeup.pdf b/writeup.pdf new file mode 100644 index 0000000000000000000000000000000000000000..6775a1937170bc5d4634cf1e3afaa823b62ad27b GIT binary patch literal 205464 zcmb@t3piB&_b>jQ&A99#w=rEw3fnYN5fK`&}rO_W@Q+!aE) zNu*MgYoc_QkZwX3)u*$j&;LB%-#P#DoaZ^u^P4bx_UxJcey{ghul0JZ^-hDdTBWmO z(K1}4p#CCjb) z0~WMs6xe5N-dsoY&;E29GnbbzkDhz?QvZgPEAt1{H)*-LF_Jz69zS2Twc10sv}Vm0 z``W(Rq#F+_Eca%v8c6^4gSjp!y81pdtn#eioqMw%#df3+`OJ;~T#u0pEVItgJX3YQ z<3r3lg#WHQ z7qYBj?sUJxJNsl=VW(Em>m83(yIUU9Z|Ny++Q6+@>hIOO;G$;V_3FTO%NC{b%HJ3C zuJ5|M-Na#hsJnT0z~sRZNgLwrv@L^511?6dBFbk4>94pueq?-_o9R)@iq-R1ot2(H zdrr-6P4NqfYYRR1JV~zdeECT!sQcqu6SG%)PMK`{b}aDrysq!9rS7@yt$PMfrR*%N zTq^#vFD`8T`eR=EZn{kl-^^$@>(#vZu4n13Eofu=>*sRaODZKt^Gf=bWlf{x*(lwA zA<47FOFW-`e-j(aip_Fwf=7kkRvFC*}*J+lZI%TbVkU zvXaJe%2}+~$o>|K)=`(=pU1u#)_ruJE}u|XrSaP#fRL2t`X1?i{#-`Ts=NBn<#o4? zhczgi^Oxv#o47xt?1C>^z&g0^+2Jh1sM-7ti_@(OYb6Kv#QSf~^!jo7>*E`yE|R~R zS{y26Ll(BI4BeMJ?UCb{@^-^LB_nYs1`d9_%BA(V8qSy1DyP*RlV`swcoV`TGBGEO zOU2?hu|I@jd|whFlq6awcmB7as1UnJZ_j; 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+module spiMemory(clk,sclk_pin,cs_pin,miso_pin,mosi_pin,leds,buffered_serialin,posSCLK,CS,miso_buff,shiftRegOutP,parallelOut,parallelData,sr_we,dm_we,state,conditioned_clk,counter,output_ff_out,addr_we,relevant_shiftRegOutP0,address,clk_counter,serialin); input clk; input sclk_pin; input cs_pin; output miso_pin; input mosi_pin; + output serialin; output [3:0] leds; output buffered_serialin; output posSCLK; @@ -229,7 +230,6 @@ module spiMemory(clk,sclk_pin,cs_pin,miso_pin,mosi_pin,leds,buffered_serialin,po output [1:0] relevant_shiftRegOutP0; output [6:0] address; output [5:0] clk_counter; - output serialin; output posSCLK; output CS; output miso_buff;