diff --git a/.gitignore b/.gitignore new file mode 100644 index 0000000..72fd5f8 --- /dev/null +++ b/.gitignore @@ -0,0 +1,2 @@ +*.out +*.vcd diff --git a/Lab-2-Midpoint-Check-In-Report.md b/Lab-2-Midpoint-Check-In-Report.md new file mode 100644 index 0000000..3ebcd1e --- /dev/null +++ b/Lab-2-Midpoint-Check-In-Report.md @@ -0,0 +1,55 @@ +# Lab 2 Midpoint Check-In Report +Jonah Spear, David Papp + +# Input Conditioning + +Our waveform illustrates the three desired characteristics: + +![](https://d2mxuefqeaa7sj.cloudfront.net/s_B9532690B10F570C9A4A02C57E09079770E739AAA391501DF085C097B989418B_1508953194069_input_fixed.png) + + +**Input synchronisation:** The conditioned input is synchronised with the noisy input with the clock. This part was already done for us. + +**Input debouncing:** We create a noisy signal with several bounces prior to stabilisation in both the positive and negative directions. It is evident from the waveform image that the conditioned input only changes if the input pin is stable for at least three cycles. Because of this, there is a three cycle delay between when the noisy signal changes to when conditioned registers this change. + +**Edge detection:** It is evident from the waveform image that rising rises for exactly one clock cycle when conditioned switches from 0 to 1. Conversely, falling rises for exactly one clock cycle when conditioned switches from 1 to 0. Rising and falling flip at the exact time that condition flips. + + +**Circuit diagram:** + + + +**Question:** If the main system clock is running at 50MHz, what is the maximum length input glitch that will be suppressed by this design for a `waittime` of 10? Include the analysis in your report. + +With a *waittime* of 10, the noisy signal needs to be steady for 10 cycles before the conditioned input changes. With a 50MHz clock, each cycle takes 2e-8 seconds. Ten cycles will thus take 2e-7 seconds. + + +---------- +# Shift Register + +**Test bench for shiftregister.v:** We tested three properties of our shift register. First, we tested that parallel load was working properly. We confirmed that parallelDataOut was the same as the parallelDataIn when parallel load was enabled. +Next, we confirmed that the shift register advances one position and appends the correct serialDataIn value. We did this by manually setting the peripheralClkEdge and adding ones and zeros in manual clock cycles and verifying parallelDataOut in each iteration. +Finally, we made sure that serialDataOut was correct. This was simple to test, since we essentially just needed to make sure that we were reading the right value. + + + +---------- +# Midpoint + + +Pressing and releasing the button will reset the LEDs to the binary representation of hA5, which is b10101001. + +Switch 0 will provide the serialBitIn. It will update when switch 1 is toggled from 0 to 1. + +Switching switch 1 to from 0 to 1 will trigger a Clk Edge in the shift register, which will cause the register to shift. + + +We will confirm that our FPGA works by first initialising our LEDs to 0. We will then toggle switch 0 to ON, and proceeded to toggle switch 1 off and on several times. This will push a few 1s into our LED queue. We will then toggle switch 0 to OFF. Now, when we toggle switch 1 off and on, it will push 0s into our LED queue. +Finally, we will check that parallel load works as expected. When we press the button, the LEDs are set to the sequence 10101001. + + + +---------- + + + diff --git a/Lab-2-Report.md b/Lab-2-Report.md new file mode 100644 index 0000000..3861bff --- /dev/null +++ b/Lab-2-Report.md @@ -0,0 +1,64 @@ +# Lab 2 Report +Jonah Spear, David Papp + + +# Note: + +We never finished this lab and at this point we’re submitting for partial credit. + + +# Input Conditioning + +Our waveform illustrates the three desired characteristics: + +![](https://d2mxuefqeaa7sj.cloudfront.net/s_B9532690B10F570C9A4A02C57E09079770E739AAA391501DF085C097B989418B_1508953194069_input_fixed.png) + + +**Input synchronisation:** The conditioned input is synchronised with the noisy input with the clock. This part was already done for us. + +**Input debouncing:** We create a noisy signal with several bounces prior to stabilisation in both the positive and negative directions. It is evident from the waveform image that the conditioned input only changes if the input pin is stable for at least three cycles. Because of this, there is a three cycle delay between when the noisy signal changes to when conditioned registers this change. + +**Edge detection:** It is evident from the waveform image that rising rises for exactly one clock cycle when conditioned switches from 0 to 1. Conversely, falling rises for exactly one clock cycle when conditioned switches from 1 to 0. Rising and falling flip at the exact time that condition flips. + + + + + +**Circuit diagram:** + + + +**Question:** If the main system clock is running at 50MHz, what is the maximum length input glitch that will be suppressed by this design for a `waittime` of 10? Include the analysis in your report. + +With a *waittime* of 10, the noisy signal needs to be steady for 10 cycles before the conditioned input changes. With a 50MHz clock, each cycle takes 2e-8 seconds. Ten cycles will thus take 2e-7 seconds. + + +---------- +# Shift Register + +**Test bench for shiftregister.v:** We tested three properties of our shift register. First, we tested that parallel load was working properly. We confirmed that parallelDataOut was the same as the parallelDataIn when parallel load was enabled. +Next, we confirmed that the shift register advances one position and appends the correct serialDataIn value. We did this by manually setting the peripheralClkEdge and adding ones and zeros in manual clock cycles and verifying parallelDataOut in each iteration. +Finally, we made sure that serialDataOut was correct. This was simple to test, since we essentially just needed to make sure that we were reading the right value. + + + +---------- +# Midpoint + + +Pressing and releasing the button will reset the LEDs to the binary representation of hA5, which is b10101001. + +Switch 0 will provide the serialBitIn. It will update when switch 1 is toggled from 0 to 1. + +Switching switch 1 to from 0 to 1 will trigger a Clk Edge in the shift register, which will cause the register to shift. + + +We will confirm that our FPGA works by first initialising our LEDs to 0. We will then toggle switch 0 to ON, and proceeded to toggle switch 1 off and on several times. This will push a few 1s into our LED queue. We will then toggle switch 0 to OFF. Now, when we toggle switch 1 off and on, it will push 0s into our LED queue. +Finally, we will check that parallel load works as expected. When we press the button, the LEDs are set to the sequence 10101001. + + + +---------- + + + diff --git a/ZYBO_Master.xdc b/ZYBO_Master.xdc new file mode 100644 index 0000000..2375822 --- /dev/null +++ b/ZYBO_Master.xdc @@ -0,0 +1,146 @@ +## This file is a general .xdc for the ZYBO Rev B board +## To use it in a project: +## - uncomment the lines corresponding to used pins +## - rename the used signals according to the project + + +##Clock signal +set_property -dict { PACKAGE_PIN L16 IOSTANDARD LVCMOS33 } [get_ports { clk }]; #IO_L11P_T1_SRCC_35 Sch=sysclk +#create_clock -add -name sys_clk_pin -period 8.00 -waveform {0 4} [get_ports { clk }]; + + +##Switches +set_property -dict { PACKAGE_PIN G15 IOSTANDARD LVCMOS33 } [get_ports { sw[0] }]; #IO_L19N_T3_VREF_35 Sch=SW0 +set_property -dict { PACKAGE_PIN P15 IOSTANDARD LVCMOS33 } [get_ports { sw[1] }]; #IO_L24P_T3_34 Sch=SW1 +#set_property -dict { PACKAGE_PIN W13 IOSTANDARD LVCMOS33 } [get_ports { sw[2] }]; #IO_L4N_T0_34 Sch=SW2 +#set_property -dict { PACKAGE_PIN T16 IOSTANDARD LVCMOS33 } [get_ports { sw[3] }]; #IO_L9P_T1_DQS_34 Sch=SW3 + + +##Buttons +set_property -dict { PACKAGE_PIN R18 IOSTANDARD LVCMOS33 } [get_ports { btn }]; #IO_L20N_T3_34 Sch=BTN0 +#set_property -dict { PACKAGE_PIN P16 IOSTANDARD LVCMOS33 } [get_ports { btn[1] }]; #IO_L24N_T3_34 Sch=BTN1 +#set_property -dict { PACKAGE_PIN V16 IOSTANDARD LVCMOS33 } [get_ports { btn[2] }]; #IO_L18P_T2_34 Sch=BTN2 +#set_property -dict { PACKAGE_PIN Y16 IOSTANDARD LVCMOS33 } [get_ports { btn[3] }]; #IO_L7P_T1_34 Sch=BTN3 + + +##LEDs +#set_property -dict { PACKAGE_PIN M14 IOSTANDARD LVCMOS33 } [get_ports { led[0] }]; #IO_L23P_T3_35 Sch=LED0 +#set_property -dict { PACKAGE_PIN M15 IOSTANDARD LVCMOS33 } [get_ports { led[1] }]; #IO_L23N_T3_35 Sch=LED1 +#set_property -dict { PACKAGE_PIN G14 IOSTANDARD LVCMOS33 } [get_ports { led[2] }]; #IO_0_35=Sch=LED2 +#set_property -dict { PACKAGE_PIN D18 IOSTANDARD LVCMOS33 } [get_ports { led[3] }]; #IO_L3N_T0_DQS_AD1N_35 Sch=LED3 + + +##I2S Audio Codec +#set_property -dict { PACKAGE_PIN K18 IOSTANDARD LVCMOS33 } [get_ports ac_bclk]; #IO_L12N_T1_MRCC_35 Sch=AC_BCLK +#set_property -dict { PACKAGE_PIN T19 IOSTANDARD LVCMOS33 } [get_ports ac_mclk]; #IO_25_34 Sch=AC_MCLK +#set_property -dict { PACKAGE_PIN P18 IOSTANDARD LVCMOS33 } [get_ports ac_muten]; #IO_L23N_T3_34 Sch=AC_MUTEN +#set_property -dict { PACKAGE_PIN M17 IOSTANDARD LVCMOS33 } [get_ports ac_pbdat]; #IO_L8P_T1_AD10P_35 Sch=AC_PBDAT +#set_property -dict { PACKAGE_PIN L17 IOSTANDARD LVCMOS33 } [get_ports ac_pblrc]; #IO_L11N_T1_SRCC_35 Sch=AC_PBLRC +#set_property -dict { PACKAGE_PIN K17 IOSTANDARD LVCMOS33 } [get_ports ac_recdat]; #IO_L12P_T1_MRCC_35 Sch=AC_RECDAT +#set_property -dict { PACKAGE_PIN M18 IOSTANDARD LVCMOS33 } [get_ports ac_reclrc]; #IO_L8N_T1_AD10N_35 Sch=AC_RECLRC + + +##Audio Codec/external EEPROM IIC bus +#set_property -dict { PACKAGE_PIN N18 IOSTANDARD LVCMOS33 } [get_ports ac_scl]; #IO_L13P_T2_MRCC_34 Sch=AC_SCL +#set_property -dict { PACKAGE_PIN N17 IOSTANDARD LVCMOS33 } [get_ports ac_sda]; #IO_L23P_T3_34 Sch=AC_SDA + + +##Additional Ethernet signals +#set_property -dict { PACKAGE_PIN F16 IOSTANDARD LVCMOS33 } [get_ports eth_int_b]; #IO_L6P_T0_35 Sch=ETH_INT_B +#set_property -dict { PACKAGE_PIN E17 IOSTANDARD LVCMOS33 } [get_ports eth_rst_b]; #IO_L3P_T0_DQS_AD1P_35 Sch=ETH_RST_B + + +##HDMI Signals +#set_property -dict { PACKAGE_PIN H17 IOSTANDARD TMDS_33 } [get_ports hdmi_clk_n]; #IO_L13N_T2_MRCC_35 Sch=HDMI_CLK_N +#set_property -dict { PACKAGE_PIN H16 IOSTANDARD TMDS_33 } [get_ports hdmi_clk_p]; #IO_L13P_T2_MRCC_35 Sch=HDMI_CLK_P +#set_property -dict { PACKAGE_PIN D20 IOSTANDARD TMDS_33 } [get_ports { hdmi_d_n[0] }]; #IO_L4N_T0_35 Sch=HDMI_D0_N +#set_property -dict { PACKAGE_PIN D19 IOSTANDARD TMDS_33 } [get_ports { hdmi_d_p[0] }]; #IO_L4P_T0_35 Sch=HDMI_D0_P +#set_property -dict { PACKAGE_PIN B20 IOSTANDARD TMDS_33 } [get_ports { hdmi_d_n[1] }]; #IO_L1N_T0_AD0N_35 Sch=HDMI_D1_N +#set_property -dict { PACKAGE_PIN C20 IOSTANDARD TMDS_33 } [get_ports { hdmi_d_p[1] }]; #IO_L1P_T0_AD0P_35 Sch=HDMI_D1_P +#set_property -dict { PACKAGE_PIN A20 IOSTANDARD TMDS_33 } [get_ports { hdmi_d_n[2] }]; #IO_L2N_T0_AD8N_35 Sch=HDMI_D2_N +#set_property -dict { PACKAGE_PIN B19 IOSTANDARD TMDS_33 } [get_ports { hdmi_d_p[2] }]; #IO_L2P_T0_AD8P_35 Sch=HDMI_D2_P +#set_property -dict { PACKAGE_PIN E19 IOSTANDARD LVCMOS33 } [get_ports hdmi_cec]; #IO_L5N_T0_AD9N_35 Sch=HDMI_CEC +#set_property -dict { PACKAGE_PIN E18 IOSTANDARD LVCMOS33 } [get_ports hdmi_hpd]; #IO_L5P_T0_AD9P_35 Sch=HDMI_HPD +#set_property -dict { PACKAGE_PIN F17 IOSTANDARD LVCMOS33 } [get_ports hdmi_out_en]; #IO_L6N_T0_VREF_35 Sch=HDMI_OUT_EN +#set_property -dict { PACKAGE_PIN G17 IOSTANDARD LVCMOS33 } [get_ports hdmi_scl]; #IO_L16P_T2_35 Sch=HDMI_SCL +#set_property -dict { PACKAGE_PIN G18 IOSTANDARD LVCMOS33 } [get_ports hdmi_sda]; #IO_L16N_T2_35 Sch=HDMI_SDA + + +##Pmod Header JA (XADC) +#set_property -dict { PACKAGE_PIN N15 IOSTANDARD LVCMOS33 } [get_ports { ja_p[0] }]; #IO_L21P_T3_DQS_AD14P_35 Sch=JA1_R_p +#set_property -dict { PACKAGE_PIN L14 IOSTANDARD LVCMOS33 } [get_ports { ja_p[1] }]; #IO_L22P_T3_AD7P_35 Sch=JA2_R_P +#set_property -dict { PACKAGE_PIN K16 IOSTANDARD LVCMOS33 } [get_ports { ja_p[2] }]; #IO_L24P_T3_AD15P_35 Sch=JA3_R_P +#set_property -dict { PACKAGE_PIN K14 IOSTANDARD LVCMOS33 } [get_ports { ja_p[3] }]; #IO_L20P_T3_AD6P_35 Sch=JA4_R_P +#set_property -dict { PACKAGE_PIN N16 IOSTANDARD LVCMOS33 } [get_ports { ja_n[0] }]; #IO_L21N_T3_DQS_AD14N_35 Sch=JA1_R_N +#set_property -dict { PACKAGE_PIN L15 IOSTANDARD LVCMOS33 } [get_ports { ja_n[1] }]; #IO_L22N_T3_AD7N_35 Sch=JA2_R_N +#set_property -dict { PACKAGE_PIN J16 IOSTANDARD LVCMOS33 } [get_ports { ja_n[2] }]; #IO_L24N_T3_AD15N_35 Sch=JA3_R_N +#set_property -dict { PACKAGE_PIN J14 IOSTANDARD LVCMOS33 } [get_ports { ja_n[3] }]; #IO_L20N_T3_AD6N_35 Sch=JA4_R_N + + +##Pmod Header JB +#set_property -dict { PACKAGE_PIN T20 IOSTANDARD LVCMOS33 } [get_ports { jb_p[0] }]; #IO_L15P_T2_DQS_34 Sch=JB1_p +#set_property -dict { PACKAGE_PIN U20 IOSTANDARD LVCMOS33 } [get_ports { jb_n[0] }]; #IO_L15N_T2_DQS_34 Sch=JB1_N +#set_property -dict { PACKAGE_PIN V20 IOSTANDARD LVCMOS33 } [get_ports { jb_p[1] }]; #IO_L16P_T2_34 Sch=JB2_P +#set_property -dict { PACKAGE_PIN W20 IOSTANDARD LVCMOS33 } [get_ports { jb_n[1] }]; #IO_L16N_T2_34 Sch=JB2_N +#set_property -dict { PACKAGE_PIN Y18 IOSTANDARD LVCMOS33 } [get_ports { jb_p[2] }]; #IO_L17P_T2_34 Sch=JB3_P +#set_property -dict { PACKAGE_PIN Y19 IOSTANDARD LVCMOS33 } [get_ports { jb_n[2] }]; #IO_L17N_T2_34 Sch=JB3_N +#set_property -dict { PACKAGE_PIN W18 IOSTANDARD LVCMOS33 } [get_ports { jb_p[3] }]; #IO_L22P_T3_34 Sch=JB4_P +#set_property -dict { PACKAGE_PIN W19 IOSTANDARD LVCMOS33 } [get_ports { jb_n[3] }]; #IO_L22N_T3_34 Sch=JB4_N + + +##Pmod Header JC +#set_property -dict { PACKAGE_PIN V15 IOSTANDARD LVCMOS33 } [get_ports { jc_p[0] }]; #IO_L10P_T1_34 Sch=JC1_P +#set_property -dict { PACKAGE_PIN W15 IOSTANDARD LVCMOS33 } [get_ports { jc_n[0] }]; #IO_L10N_T1_34 Sch=JC1_N +#set_property -dict { PACKAGE_PIN T11 IOSTANDARD LVCMOS33 } [get_ports { jc_p[1] }]; #IO_L1P_T0_34 Sch=JC2_P +#set_property -dict { PACKAGE_PIN T10 IOSTANDARD LVCMOS33 } [get_ports { jc_n[1] }]; #IO_L1N_T0_34 Sch=JC2_N +#set_property -dict { PACKAGE_PIN W14 IOSTANDARD LVCMOS33 } [get_ports { jc_p[2] }]; #IO_L8P_T1_34 Sch=JC3_P +#set_property -dict { PACKAGE_PIN Y14 IOSTANDARD LVCMOS33 } [get_ports { jc_n[2] }]; #IO_L8N_T1_34 Sch=JC3_N +#set_property -dict { PACKAGE_PIN T12 IOSTANDARD LVCMOS33 } [get_ports { jc_p[3] }]; #IO_L2P_T0_34 Sch=JC4_P +#set_property -dict { PACKAGE_PIN U12 IOSTANDARD LVCMOS33 } [get_ports { jc_n[3] }]; #IO_L2N_T0_34 Sch=JC4_N + + +##Pmod Header JD +#set_property -dict { PACKAGE_PIN T14 IOSTANDARD LVCMOS33 } [get_ports { jd_p[0] }]; #IO_L5P_T0_34 Sch=JD1_P +#set_property -dict { PACKAGE_PIN T15 IOSTANDARD LVCMOS33 } [get_ports { jd_n[0] }]; #IO_L5N_T0_34 Sch=JD1_N +#set_property -dict { PACKAGE_PIN P14 IOSTANDARD LVCMOS33 } [get_ports { jd_p[1] }]; #IO_L6P_T0_34 Sch=JD2_P +#set_property -dict { PACKAGE_PIN R14 IOSTANDARD LVCMOS33 } [get_ports { jd_n[1] }]; #IO_L6N_T0_VREF_34 Sch=JD2_N +#set_property -dict { PACKAGE_PIN U14 IOSTANDARD LVCMOS33 } [get_ports { jd_p[2] }]; #IO_L11P_T1_SRCC_34 Sch=JD3_P +#set_property -dict { PACKAGE_PIN U15 IOSTANDARD LVCMOS33 } [get_ports { jd_n[2] }]; #IO_L11N_T1_SRCC_34 Sch=JD3_N +#set_property -dict { PACKAGE_PIN V17 IOSTANDARD LVCMOS33 } [get_ports { jd_p[3] }]; #IO_L21P_T3_DQS_34 Sch=JD4_P +#set_property -dict { PACKAGE_PIN V18 IOSTANDARD LVCMOS33 } [get_ports { jd_n[3] }]; #IO_L21N_T3_DQS_34 Sch=JD4_N + + +##Pmod Header JE +set_property -dict { PACKAGE_PIN V12 IOSTANDARD LVCMOS33 } [get_ports { je[0] }]; #IO_L4P_T0_34 Sch=JE1 +set_property -dict { PACKAGE_PIN W16 IOSTANDARD LVCMOS33 } [get_ports { je[1] }]; #IO_L18N_T2_34 Sch=JE2 +set_property -dict { PACKAGE_PIN J15 IOSTANDARD LVCMOS33 } [get_ports { je[2] }]; #IO_25_35 Sch=JE3 +set_property -dict { PACKAGE_PIN H15 IOSTANDARD LVCMOS33 } [get_ports { je[3] }]; #IO_L19P_T3_35 Sch=JE4 +set_property -dict { PACKAGE_PIN V13 IOSTANDARD LVCMOS33 } [get_ports { je[4] }]; #IO_L3N_T0_DQS_34 Sch=JE7 +set_property -dict { PACKAGE_PIN U17 IOSTANDARD LVCMOS33 } [get_ports { je[5] }]; #IO_L9N_T1_DQS_34 Sch=JE8 +set_property -dict { PACKAGE_PIN T17 IOSTANDARD LVCMOS33 } [get_ports { je[6] }]; #IO_L20P_T3_34 Sch=JE9 +set_property -dict { PACKAGE_PIN Y17 IOSTANDARD LVCMOS33 } [get_ports { je[7] }]; #IO_L7N_T1_34 Sch=JE10 + + +##USB-OTG overcurrent detect pin +#set_property -dict { PACKAGE_PIN U13 IOSTANDARD LVCMOS33 } [get_ports otg_oc]; #IO_L3P_T0_DQS_PUDC_B_34 Sch=OTG_OC + + +##VGA Connector +#set_property -dict { PACKAGE_PIN M19 IOSTANDARD LVCMOS33 } [get_ports { vga_r[0] }]; #IO_L7P_T1_AD2P_35 Sch=VGA_R1 +#set_property -dict { PACKAGE_PIN L20 IOSTANDARD LVCMOS33 } [get_ports { vga_r[1] }]; #IO_L9N_T1_DQS_AD3N_35 Sch=VGA_R2 +#set_property -dict { PACKAGE_PIN J20 IOSTANDARD LVCMOS33 } [get_ports { vga_r[2] }]; #IO_L17P_T2_AD5P_35 Sch=VGA_R3 +#set_property -dict { PACKAGE_PIN G20 IOSTANDARD LVCMOS33 } [get_ports { vga_r[3] }]; #IO_L18N_T2_AD13N_35 Sch=VGA_R4 +#set_property -dict { PACKAGE_PIN F19 IOSTANDARD LVCMOS33 } [get_ports { vga_r[4] }]; #IO_L15P_T2_DQS_AD12P_35 Sch=VGA_R5 +#set_property -dict { PACKAGE_PIN H18 IOSTANDARD LVCMOS33 } [get_ports { vga_g[0] }]; #IO_L14N_T2_AD4N_SRCC_35 Sch=VGA_G0 +#set_property -dict { PACKAGE_PIN N20 IOSTANDARD LVCMOS33 } [get_ports { vga_g[1] }]; #IO_L14P_T2_SRCC_34 Sch=VGA_G1 +#set_property -dict { PACKAGE_PIN L19 IOSTANDARD LVCMOS33 } [get_ports { vga_g[2] }]; #IO_L9P_T1_DQS_AD3P_35 Sch=VGA_G2 +#set_property -dict { PACKAGE_PIN J19 IOSTANDARD LVCMOS33 } [get_ports { vga_g[3] }]; #IO_L10N_T1_AD11N_35 Sch=VGA_G3 +#set_property -dict { PACKAGE_PIN H20 IOSTANDARD LVCMOS33 } [get_ports { vga_g[4] }]; #IO_L17N_T2_AD5N_35 Sch=VGA_G4 +#set_property -dict { PACKAGE_PIN F20 IOSTANDARD LVCMOS33 } [get_ports { vga_g[5] }]; #IO_L15N_T2_DQS_AD12N_35 Sch=VGA=G5 +#set_property -dict { PACKAGE_PIN P20 IOSTANDARD LVCMOS33 } [get_ports { vga_b[0] }]; #IO_L14N_T2_SRCC_34 Sch=VGA_B1 +#set_property -dict { PACKAGE_PIN M20 IOSTANDARD LVCMOS33 } [get_ports { vga_b[1] }]; #IO_L7N_T1_AD2N_35 Sch=VGA_B2 +#set_property -dict { PACKAGE_PIN K19 IOSTANDARD LVCMOS33 } [get_ports { vga_b[2] }]; #IO_L10P_T1_AD11P_35 Sch=VGA_B3 +#set_property -dict { PACKAGE_PIN J18 IOSTANDARD LVCMOS33 } [get_ports { vga_b[3] }]; #IO_L14P_T2_AD4P_SRCC_35 Sch=VGA_B4 +#set_property -dict { PACKAGE_PIN G19 IOSTANDARD LVCMOS33 } [get_ports { vga_b[4] }]; #IO_L18P_T2_AD13P_35 Sch=VGA_B5 +#set_property -dict { PACKAGE_PIN P19 IOSTANDARD LVCMOS33 } [get_ports vga_hs]; #IO_L13N_T2_MRCC_34 Sch=VGA_HS +#set_property -dict { PACKAGE_PIN R19 IOSTANDARD LVCMOS33 } [get_ports vga_vs]; #IO_0_34 Sch=VGA_VS diff --git a/datamemory.v b/datamemory.v index 0d82131..bfc8238 100644 --- a/datamemory.v +++ b/datamemory.v @@ -17,11 +17,15 @@ module datamemory input [addresswidth-1:0] address, input writeEnable, input [width-1:0] dataIn -) +); reg [width-1:0] memory [depth-1:0]; + /*initial begin + memory[0] = 8'b11111111; + end*/ + always @(posedge clk) begin if(writeEnable) memory[address] <= dataIn; diff --git a/dff.v b/dff.v new file mode 100644 index 0000000..640e4a4 --- /dev/null +++ b/dff.v @@ -0,0 +1,13 @@ +module dff #( parameter W = 1 ) +( + input trigger, + input enable, + input [W-1:0] d, + output reg [W-1:0] q +); + always @(posedge trigger) begin + if(enable) begin + q <= d; + end + end +endmodule \ No newline at end of file diff --git a/fsm.v b/fsm.v new file mode 100644 index 0000000..6378ff9 --- /dev/null +++ b/fsm.v @@ -0,0 +1,144 @@ +`timescale 1 ns / 1 ps + +//Example of a Finite State Machine where the traffic light state dictates the driving. + +module finiteStateMachine( + input clk, + input sclk_posedge, + input chip_select, + input r_w, + output reg MISO_BUFE, + output reg DM_WE, + output reg ADDR_WE, + output reg SR_WE +); + + localparam addressLoad = 1; + localparam branch = 2; + localparam write = 3; + localparam read = 4; + localparam reset = 0; + localparam dataLoad = 5; + localparam dataLoad2 = 6; + localparam writeFinish = 7; + + reg[7:0] state = reset; + + integer counter = 0; + //change states on the clk cycles + + always @(posedge clk) begin + + // Some state transitions should happen immediately + if ((state == reset) && (chip_select == 0)) begin + $display("start"); + state <= addressLoad; + end + else if (state == branch) begin + $display("branch"); + if (r_w == 0) begin // write + state <= write; + end + else begin // read + state <= dataLoad; + end + end + else if (state == dataLoad) begin + $display("dataLoad1"); + state <= dataLoad2; + end + else if (state == dataLoad2) begin + $display("dataLoad2"); + state <= read; + end + else if (state == writeFinish) begin + $display("write finish"); + state <= reset; + end + + // Some states need to wait a given tim based on the serial clock. + if (sclk_posedge) begin + if (state == addressLoad) begin + if (counter == 7) begin + counter <= 0; + state <= branch; + end + else begin + counter <= counter + 1; + end + end + else if (state == read) begin + $display("read"); + if (counter == 7) begin + counter <= 0; + state <= reset; + end + else begin + counter <= counter + 1; + end + end + else if (state == write) begin + $display("write"); + if (counter == 8) begin + counter <= 0; + state <= writeFinish; + end + else begin + counter <= counter + 1; + end + end + end + + + case (state) + addressLoad: begin + MISO_BUFE <= 0; + DM_WE <= 0; + ADDR_WE <= 0; + SR_WE <= 0; + end + branch: begin + MISO_BUFE <= 0; + DM_WE <= 0; + ADDR_WE <= 1; + SR_WE <= 0; + end + write: begin + MISO_BUFE <= 0; + DM_WE <= 1; + ADDR_WE <= 0; + SR_WE <= 0; + end + read: begin + MISO_BUFE <= 1; + DM_WE <= 0; + ADDR_WE <= 0; + SR_WE <= 0; + end + dataLoad: begin + MISO_BUFE <= 0; + DM_WE <= 0; + ADDR_WE <= 0; + SR_WE <= 0; + end + dataLoad2: begin + MISO_BUFE <= 0; + DM_WE <= 0; + ADDR_WE <= 0; + SR_WE <= 1; + end + writeFinish: begin + MISO_BUFE <= 0; + DM_WE <= 1; + ADDR_WE <= 0; + SR_WE <= 0; + end + reset: begin + MISO_BUFE <= 0; + DM_WE <= 0; + ADDR_WE <= 0; + SR_WE <= 0; + end + endcase + end +endmodule diff --git a/inputconditioner.t.v b/inputconditioner.t.v index 2814163..ab9666a 100644 --- a/inputconditioner.t.v +++ b/inputconditioner.t.v @@ -1,6 +1,7 @@ //------------------------------------------------------------------------ // Input Conditioner test bench //------------------------------------------------------------------------ +`include "inputconditioner.v" module testConditioner(); @@ -9,21 +10,44 @@ module testConditioner(); wire conditioned; wire rising; wire falling; - + inputconditioner dut(.clk(clk), .noisysignal(pin), .conditioned(conditioned), .positiveedge(rising), - .negativeedge(falling)) + .negativeedge(falling)); // Generate clock (50MHz) initial clk=0; - always #10 clk=!clk; // 50MHz Clock - + always #5 clk=!clk; // 50MHz Clock + initial begin + $dumpfile("inputconditioner.vcd"); + $dumpvars; + // Initialize conditioner by running at 0 for 3 clock cycles + pin=0; #40 + + pin=1; #10 + pin=0; #10 + pin=1; #80 + pin=0; #100 + pin=1; #10 + pin=0; #10 + pin=1; #10 + pin=0; #50 + pin=1; #10 + pin=0; #10 + pin=1; #10 + pin=0; #10 + pin=1; #80 + pin=0; + #100 + $finish; + end + // Your Test Code // Be sure to test each of the three conditioner functions: // Synchronization, Debouncing, Edge Detection - + endmodule diff --git a/inputconditioner.v b/inputconditioner.v index 736a866..22b3c5f 100644 --- a/inputconditioner.v +++ b/inputconditioner.v @@ -6,33 +6,42 @@ //------------------------------------------------------------------------ module inputconditioner +#( + parameter wait_time = 3 +) ( input clk, // Clock domain to synchronize input to input noisysignal, // (Potentially) noisy input signal -output reg conditioned, // Conditioned output signal +output reg conditioned, // Conditioned output signal output reg positiveedge, // 1 clk pulse at rising edge of conditioned output reg negativeedge // 1 clk pulse at falling edge of conditioned ); + reg[wait_time-1:0] prev_vals; - parameter counterwidth = 3; // Counter size, in bits, >= log2(waittime) - parameter waittime = 3; // Debounce delay, in clock cycles - - reg[counterwidth-1:0] counter = 0; - reg synchronizer0 = 0; - reg synchronizer1 = 0; - always @(posedge clk ) begin - if(conditioned == synchronizer1) - counter <= 0; - else begin - if( counter == waittime) begin - counter <= 0; - conditioned <= synchronizer1; + // Case 1: The previous values are all 1s + if( prev_vals == ((2**wait_time) - 1)) begin + if (conditioned == 0) begin + positiveedge <= 1; end - else - counter <= counter+1; + else begin + positiveedge <= 0; + end + conditioned <= 1; end - synchronizer0 <= noisysignal; - synchronizer1 <= synchronizer0; + // Case 2: The previous values are all 0s + else if( prev_vals == 0) begin + if (conditioned == 1) begin + negativeedge <= 1; + end + else begin + negativeedge <= 0; + end + + conditioned <= 0; + end + + prev_vals <= {prev_vals, noisysignal}; end + endmodule diff --git a/inputconditioner.vcd b/inputconditioner.vcd new file mode 100644 index 0000000..1b8a81f --- /dev/null +++ b/inputconditioner.vcd @@ -0,0 +1,446 @@ +$date + Wed Oct 25 13:37:41 2017 +$end +$version + Icarus Verilog +$end +$timescale + 1s +$end +$scope module testConditioner $end +$var wire 1 ! conditioned $end +$var wire 1 " falling $end +$var wire 1 # rising $end +$var reg 1 $ clk $end +$var reg 1 % pin $end +$scope module dut $end +$var wire 1 & clk $end +$var wire 1 ' noisysignal $end +$var reg 1 ( conditioned $end +$var reg 1 ) negativeedge $end +$var reg 1 * positiveedge $end +$var reg 3 + prev_vals [2:0] $end +$upscope $end +$upscope $end +$enddefinitions $end +#0 +$dumpvars +bx + +x* +x) +x( +0' +0& +0% +0$ +x# +x" +x! +$end +#5 +bx0 + +1$ +1& +#10 +0$ +0& +#15 +bx00 + +1$ +1& +#20 +0$ +0& +#25 +b0 + +1$ +1& +#30 +0$ +0& +#35 +0( +0! +0) +0" +1$ +1& +#40 +0$ +0& +1% +1' +#45 +b1 + +1$ +1& +#50 +0$ +0& +0% +0' +#55 +b10 + +1$ +1& +#60 +0$ +0& +1% +1' +#65 +b101 + +1$ +1& +#70 +0$ +0& +#75 +b11 + +1$ +1& +#80 +0$ +0& +#85 +b111 + +1$ +1& +#90 +0$ +0& +#95 +1( +1! +1* +1# +1$ +1& +#100 +0$ +0& +#105 +0* +0# +1$ +1& +#110 +0$ +0& +#115 +1$ +1& +#120 +0$ +0& +#125 +1$ +1& +#130 +0$ +0& +#135 +1$ +1& +#140 +0$ +0& +0% +0' +#145 +b110 + +1$ +1& +#150 +0$ +0& +#155 +b100 + +1$ +1& +#160 +0$ +0& +#165 +b0 + +1$ +1& +#170 +0$ +0& +#175 +0( +0! +1) +1" +1$ +1& +#180 +0$ +0& +#185 +0) +0" +1$ +1& +#190 +0$ +0& +#195 +1$ +1& +#200 +0$ +0& +#205 +1$ +1& +#210 +0$ +0& +#215 +1$ +1& +#220 +0$ +0& +#225 +1$ +1& +#230 +0$ +0& +#235 +1$ +1& +#240 +0$ +0& +1% +1' +#245 +b1 + +1$ +1& +#250 +0$ +0& +0% +0' +#255 +b10 + +1$ +1& +#260 +0$ +0& +1% +1' +#265 +b101 + +1$ +1& +#270 +0$ +0& +0% +0' +#275 +b10 + +1$ +1& +#280 +0$ +0& +#285 +b100 + +1$ +1& +#290 +0$ +0& +#295 +b0 + +1$ +1& +#300 +0$ +0& +#305 +1$ +1& +#310 +0$ +0& +#315 +1$ +1& +#320 +0$ +0& +1% +1' +#325 +b1 + +1$ +1& +#330 +0$ +0& +0% +0' +#335 +b10 + +1$ +1& +#340 +0$ +0& +1% +1' +#345 +b101 + +1$ +1& +#350 +0$ +0& +0% +0' +#355 +b10 + +1$ +1& +#360 +0$ +0& +1% +1' +#365 +b101 + +1$ +1& +#370 +0$ +0& +#375 +b11 + +1$ +1& +#380 +0$ +0& +#385 +b111 + +1$ +1& +#390 +0$ +0& +#395 +1( +1! +1* +1# +1$ +1& +#400 +0$ +0& +#405 +0* +0# +1$ +1& +#410 +0$ +0& +#415 +1$ +1& +#420 +0$ +0& +#425 +1$ +1& +#430 +0$ +0& +#435 +1$ +1& +#440 +0$ +0& +0% +0' +#445 +b110 + +1$ +1& +#450 +0$ +0& +#455 +b100 + +1$ +1& +#460 +0$ +0& +#465 +b0 + +1$ +1& +#470 +0$ +0& +#475 +0( +0! +1) +1" +1$ +1& +#480 +0$ +0& +#485 +0) +0" +1$ +1& +#490 +0$ +0& +#495 +1$ +1& +#500 +0$ +0& +#505 +1$ +1& +#510 +0$ +0& +#515 +1$ +1& +#520 +0$ +0& +#525 +1$ +1& +#530 +0$ +0& +#535 +1$ +1& +#540 +0$ +0& diff --git a/midpoint.v b/midpoint.v new file mode 100644 index 0000000..cf4071b --- /dev/null +++ b/midpoint.v @@ -0,0 +1,19 @@ +// midpoint tests the + +`include "inputconditioner.v" +`include "shiftregister.v" + +module midpoint +( +input clk, +input btn, +input [1:0] sw, +output [7:0] je +); + wire neg_edg, pos_edg, srl_in; + inputconditioner i1 (clk, btn, , , neg_edg); + inputconditioner i2 (clk, sw[0], srl_in, , ); + inputconditioner i3 (clk, sw[1], , pos_edg, ); + + shiftregister shft(clk, pos_edg, neg_edg, 8'hA5, srl_in, je, ); +endmodule diff --git a/names.filter b/names.filter new file mode 100644 index 0000000..7c85ea0 --- /dev/null +++ b/names.filter @@ -0,0 +1,9 @@ +# Example filter file +# Each line has a value (which much match what is in the wave viewer exactly) and a string alias to replace the value if found +00 Reset +01 AddressLoad +02 Branch +03 Write +04 Read +05 DataLoad +06 DataLoad2 diff --git a/shiftregister.t.v b/shiftregister.t.v index abe5b48..c1b0f7c 100644 --- a/shiftregister.t.v +++ b/shiftregister.t.v @@ -1,6 +1,7 @@ //------------------------------------------------------------------------ // Shift Register test bench //------------------------------------------------------------------------ +`include "shiftregister.v" module testshiftregister(); @@ -10,20 +11,135 @@ module testshiftregister(); wire[7:0] parallelDataOut; wire serialDataOut; reg[7:0] parallelDataIn; - reg serialDataIn; - + reg serialDataIn; + // Instantiate with parameter width = 8 - shiftregister #(8) dut(.clk(clk), + shiftregister #(8) dut(.clk(clk), .peripheralClkEdge(peripheralClkEdge), - .parallelLoad(parallelLoad), - .parallelDataIn(parallelDataIn), - .serialDataIn(serialDataIn), - .parallelDataOut(parallelDataOut), + .parallelLoad(parallelLoad), + .parallelDataIn(parallelDataIn), + .serialDataIn(serialDataIn), + .parallelDataOut(parallelDataOut), .serialDataOut(serialDataOut)); + initial clk = 0; + initial begin - // Your Test Code + $dumpfile("shiftregister.vcd"); + $dumpvars; + + peripheralClkEdge = 0; + // Test parallel loads + parallelLoad = 1; + parallelDataIn = 8'b00000000; + clk = 1; #10 clk = 0; #10 + if (parallelDataOut == 8'b00000000) begin + $display("Test Case 1 Passed"); + end + else begin + $display("Test Case 1 Failed!"); + end + + parallelDataIn = 8'b00001111; + clk = 1; #10 clk = 0; #10; + if (parallelDataOut == 8'b00001111) begin + $display("Test Case 2 Passed"); + end + else begin + $display("Test Case 2 Failed!"); + end + + parallelDataIn = 8'b11111111; + clk = 1; #10 clk = 0; #10 + if (parallelDataOut == 8'b11111111) begin + $display("Test Case 3 Passed"); + end + else begin + $display("Test Case 3 Failed!"); + end + if (serialDataOut == 1) begin + $display("Test Case 10 serialDataOut Passed"); + end + else begin + $display("Test Case 10 serialDataOut Failed!"); + $display("%8b", serialDataOut); + end + + + parallelLoad = 0; + parallelDataIn = 8'b00000000; + clk = 1; #10 clk = 0; #10 + if (parallelDataOut == 8'b00000000) begin + $display("Test Case 4 Failed!"); + end + else begin + $display("Test Case 4 Passed"); + end + + + // serial tests + clk = 0; #10 + parallelLoad = 1; + parallelDataIn = 8'b00000000; + clk = 1; #10 clk = 0; #10 + + parallelLoad = 0; + serialDataIn = 1; + peripheralClkEdge = 1; + + clk = 1; #5 clk = 0; #5 + if (parallelDataOut == 8'b00000001) begin + $display("Test Case 6 Passed"); + end + else begin + $display("Test Case 6 Failed!"); + $display("%8b", parallelDataOut); + end + if (serialDataOut == 0) begin + $display("Test Case 7 Passed"); + end + else begin + $display("Test Case 7 Failed!"); + $display("%8b", serialDataOut); + end + + clk = 1; #5 clk = 0; #5 + + if (parallelDataOut == 8'b00000011) begin + $display("passed serial test 2"); + end + else begin + $display("failed serial test 2"); + $display("%8b", parallelDataOut); + end + + clk = 1; #5 clk = 0; #5 + if (parallelDataOut == 8'b00000111) begin + $display("passed serial test 3"); + end + else begin + $display("failed serial test 3"); + $display("%8b", parallelDataOut); + end + + serialDataIn = 0; + clk = 1; #5 clk = 0; #5 + if (parallelDataOut == 8'b00001110) begin + $display("passed serial test 4"); + end + else begin + $display("failed serial test 4"); + $display("%8b", parallelDataOut); + end + if (serialDataOut == 0) begin + $display("passed serialOut test 2"); + end + else begin + $display("failed serialOut test 2"); + $display("%8b", serialDataOut); + end + + // test serialDataOut end endmodule - diff --git a/shiftregister.v b/shiftregister.v index b4ec057..a62744f 100644 --- a/shiftregister.v +++ b/shiftregister.v @@ -18,8 +18,19 @@ output [width-1:0] parallelDataOut, // Shift reg data contents output serialDataOut // Positive edge synchronized ); - reg [width-1:0] shiftregistermem; + reg [width-1:0] data; + always @(posedge clk) begin - // Your Code Here + if (parallelLoad) begin + data <= parallelDataIn; + end + else if (peripheralClkEdge) begin + data <= {data[width - 2:0], serialDataIn}; + end + end + assign serialDataOut = data[width - 1]; + assign parallelDataOut = data; + + endmodule diff --git a/shiftregister.vcd b/shiftregister.vcd new file mode 100644 index 0000000..199cf2d --- /dev/null +++ b/shiftregister.vcd @@ -0,0 +1,139 @@ +$date + Wed Oct 25 20:27:31 2017 +$end +$version + Icarus Verilog +$end +$timescale + 1s +$end +$scope module testshiftregister $end +$var wire 8 ! parallelDataOut [7:0] $end +$var wire 1 " serialDataOut $end +$var reg 1 # clk $end +$var reg 8 $ parallelDataIn [7:0] $end +$var reg 1 % parallelLoad $end +$var reg 1 & peripheralClkEdge $end +$var reg 1 ' serialDataIn $end +$scope module dut $end +$var wire 1 ( clk $end +$var wire 8 ) parallelDataIn [7:0] $end +$var wire 8 * parallelDataOut [7:0] $end +$var wire 1 + parallelLoad $end +$var wire 1 , peripheralClkEdge $end +$var wire 1 - serialDataIn $end +$var wire 1 " serialDataOut $end +$var reg 8 . data [7:0] $end +$upscope $end +$upscope $end +$enddefinitions $end +#0 +$dumpvars +b0 . +x- +0, +1+ +b0 * +b0 ) +1( +x' +0& +1% +b0 $ +1# +0" +b0 ! +$end +#10 +0# +0( +#20 +b1111 . +b1111 ! +b1111 * +1# +1( +b1111 $ +b1111 ) +#30 +0# +0( +#40 +1" +b11111111 . +b11111111 ! +b11111111 * +1# +1( +b11111111 $ +b11111111 ) +#50 +0# +0( +#60 +1# +1( +b0 $ +b0 ) +0% +0+ +#70 +0# +0( +#90 +0" +b0 . +b0 ! +b0 * +1# +1( +1% +1+ +#100 +0# +0( +#110 +b1 . +b1 ! +b1 * +1# +1( +1& +1, +1' +1- +0% +0+ +#115 +0# +0( +#120 +b11 . +b11 ! +b11 * +1# +1( +#125 +0# +0( +#130 +b111 . +b111 ! +b111 * +1# +1( +#135 +0# +0( +#140 +b1110 . +b1110 ! +b1110 * +1# +1( +0' +0- +#145 +0# +0( +#150 diff --git a/sim/sim.cache/wt/gui_resources.wdf b/sim/sim.cache/wt/gui_resources.wdf new file mode 100644 index 0000000..3e30634 --- /dev/null +++ b/sim/sim.cache/wt/gui_resources.wdf @@ -0,0 +1,24 @@ +version:1 +70726f6a656374:76697661646f5f75736167655c6775695f7265736f7572636573:61646473726377697a6172645f737065636966795f68646c5f6e65746c6973745f626c6f636b5f64657369676e:32:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f7265736f7572636573:61646473726377697a6172645f737065636966795f6f725f6372656174655f636f6e73747261696e745f66696c6573:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f7265736f7572636573:626173656469616c6f675f63616e63656c:32:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f7265736f7572636573:626173656469616c6f675f6f6b:3432:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f7265736f7572636573:636d646d73676469616c6f675f6f6b:34:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f7265736f7572636573:636f6e73747261696e747363686f6f73657270616e656c5f6164645f6578697374696e675f6f725f6372656174655f6e65775f636f6e73747261696e7473:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f7265736f7572636573:636f6e73747261696e747363686f6f73657270616e656c5f6164645f66696c6573:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f7265736f7572636573:66696c6573657470616e656c5f66696c655f7365745f70616e656c5f74726565:3130:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f7265736f7572636573:666c6f776e6176696761746f727472656570616e656c5f666c6f775f6e6176696761746f725f74726565:3137:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f7265736f7572636573:67657474696e6773746172746564766965775f6372656174655f6e65775f70726f6a656374:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f7265736f7572636573:68636f6465656469746f725f7365617263685f746578745f636f6d626f5f626f78:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f7265736f7572636573:68617264776172657472656570616e656c5f68617264776172655f747265655f7461626c65:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f7265736f7572636573:6d73677472656570616e656c5f6d6573736167655f766965775f74726565:38:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f7265736f7572636573:7061636f6d6d616e646e616d65735f6164645f736f7572636573:33:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f7265736f7572636573:7061636f6d6d616e646e616d65735f6175746f5f636f6e6e6563745f746172676574:32:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f7265736f7572636573:7061636f6d6d616e646e616d65735f6f70656e5f68617264776172655f6d616e61676572:32:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f7265736f7572636573:706176696577735f646576696365:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f7265736f7572636573:7061727463686f6f7365725f626f61726473:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f7265736f7572636573:7061727463686f6f7365725f7061727473:32:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f7265736f7572636573:70726f6772616d667067616469616c6f675f70726f6772616d:34:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f7265736f7572636573:70726f6a6563746e616d6563686f6f7365725f70726f6a6563745f6e616d65:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f7265736f7572636573:73726363686f6f73657270616e656c5f6164645f68646c5f616e645f6e65746c6973745f66696c65735f746f5f796f75725f70726f6a656374:31:00:00 +eof:1335099877 diff --git a/sim/sim.cache/wt/java_command_handlers.wdf b/sim/sim.cache/wt/java_command_handlers.wdf new file mode 100644 index 0000000..c69ede2 --- /dev/null +++ b/sim/sim.cache/wt/java_command_handlers.wdf @@ -0,0 +1,14 @@ +version:1 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:616464736f7572636573:33:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6175746f636f6e6e656374746172676574:31:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6c61756e636870726f6772616d66706761:32:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6e657770726f6a656374:31:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6f70656e68617264776172656d616e61676572:34:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:70726f6772616d646576696365:32:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:72756e62697467656e:32:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:72756e696d706c656d656e746174696f6e:34:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:72756e73796e746865736973:36:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:73686f7776696577:32:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:766965777461736b696d706c656d656e746174696f6e:32:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:766965777461736b70726f6a6563746d616e61676572:31:00:00 +eof:1308606398 diff --git a/sim/sim.cache/wt/project.wpc b/sim/sim.cache/wt/project.wpc new file mode 100644 index 0000000..0a638ea --- /dev/null +++ b/sim/sim.cache/wt/project.wpc @@ -0,0 +1,4 @@ +version:1 +57656254616c6b5472616e736d697373696f6e417474656d70746564:2 +6d6f64655f636f756e7465727c4755494d6f6465:1 +eof: diff --git a/sim/sim.cache/wt/synthesis.wdf b/sim/sim.cache/wt/synthesis.wdf new file mode 100644 index 0000000..15ebfb4 --- /dev/null +++ b/sim/sim.cache/wt/synthesis.wdf @@ -0,0 +1,39 @@ +version:1 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d70617274:7863377a303130636c673430302d31:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6e616d65:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d746f70:6d6964706f696e74:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d696e636c7564655f64697273:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d67656e65726963:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d766572696c6f675f646566696e65:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d636f6e737472736574:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d7365755f70726f74656374:64656661756c743a3a6e6f6e65:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d666c617474656e5f686965726172636879:64656661756c743a3a72656275696c74:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d67617465645f636c6f636b5f636f6e76657273696f6e:64656661756c743a3a6f6666:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d646972656374697665:64656661756c743a3a64656661756c74:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d72746c:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d72746c5f736b69705f6970:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d72746c5f736b69705f636f6e73747261696e7473:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6e6f5f6c63:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d62756667:64656661756c743a3a3132:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d66616e6f75745f6c696d6974:64656661756c743a3a3130303030:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73687265675f6d696e5f73697a65:64656661756c743a3a33:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6d6f6465:64656661756c743a3a64656661756c74:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d66736d5f65787472616374696f6e:64656661756c743a3a6175746f:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6b6565705f6571756976616c656e745f726567697374657273:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d7265736f757263655f73686172696e67:64656661756c743a3a6175746f:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d636173636164655f647370:64656661756c743a3a6175746f:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d636f6e74726f6c5f7365745f6f70745f7468726573686f6c64:64656661756c743a3a6175746f:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6d61785f6272616d:64656661756c743a3a2d31:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6d61785f7572616d:64656661756c743a3a2d31:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6d61785f647370:64656661756c743a3a2d31:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6d61785f6272616d5f636173636164655f686569676874:64656661756c743a3a2d31:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6d61785f7572616d5f636173636164655f686569676874:64656661756c743a3a2d31:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d726574696d696e67:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6e6f5f73726c65787472616374:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d617373657274:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6e6f5f74696d696e675f64726976656e:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73666375:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 +73796e746865736973:73796e7468657369735c7573616765:656c6170736564:30303a30303a313873:00:00 +73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f7065616b:313439342e3338374d42:00:00 +73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f6761696e:3430352e3335324d42:00:00 +eof:452193476 diff --git a/sim/sim.cache/wt/synthesis_details.wdf b/sim/sim.cache/wt/synthesis_details.wdf new file mode 100644 index 0000000..78f8d66 --- /dev/null +++ b/sim/sim.cache/wt/synthesis_details.wdf @@ -0,0 +1,3 @@ +version:1 +73796e746865736973:73796e7468657369735c7573616765:686c735f6970:30:00:00 +eof:2511430288 diff --git a/sim/sim.cache/wt/webtalk_pa.xml b/sim/sim.cache/wt/webtalk_pa.xml new file mode 100644 index 0000000..6aa0e9f --- /dev/null +++ b/sim/sim.cache/wt/webtalk_pa.xml @@ -0,0 +1,64 @@ + + + + +
+ + +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+ + diff --git a/sim/sim.hw/hw_1/hw.xml b/sim/sim.hw/hw_1/hw.xml new file mode 100644 index 0000000..4253063 --- /dev/null +++ b/sim/sim.hw/hw_1/hw.xml @@ -0,0 +1,16 @@ + + + + + + + + + + + + + + + + diff --git a/sim/sim.hw/sim.lpr b/sim/sim.hw/sim.lpr new file mode 100644 index 0000000..e87eed2 --- /dev/null +++ b/sim/sim.hw/sim.lpr @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/sim/sim.runs/.jobs/vrs_config_1.xml b/sim/sim.runs/.jobs/vrs_config_1.xml new file mode 100644 index 0000000..19ce55a --- /dev/null +++ b/sim/sim.runs/.jobs/vrs_config_1.xml @@ -0,0 +1,5 @@ + + + + + diff --git a/sim/sim.runs/.jobs/vrs_config_10.xml b/sim/sim.runs/.jobs/vrs_config_10.xml new file mode 100644 index 0000000..038c596 --- /dev/null +++ b/sim/sim.runs/.jobs/vrs_config_10.xml @@ -0,0 +1,5 @@ + + + + + diff --git a/sim/sim.runs/.jobs/vrs_config_2.xml b/sim/sim.runs/.jobs/vrs_config_2.xml new file mode 100644 index 0000000..0ea1672 --- /dev/null +++ b/sim/sim.runs/.jobs/vrs_config_2.xml @@ -0,0 +1,5 @@ + + + + + diff --git a/sim/sim.runs/.jobs/vrs_config_3.xml b/sim/sim.runs/.jobs/vrs_config_3.xml new file mode 100644 index 0000000..19ce55a --- /dev/null +++ b/sim/sim.runs/.jobs/vrs_config_3.xml @@ -0,0 +1,5 @@ + + + + + diff --git a/sim/sim.runs/.jobs/vrs_config_4.xml b/sim/sim.runs/.jobs/vrs_config_4.xml new file mode 100644 index 0000000..0ea1672 --- /dev/null +++ b/sim/sim.runs/.jobs/vrs_config_4.xml @@ -0,0 +1,5 @@ + + + + + diff --git a/sim/sim.runs/.jobs/vrs_config_5.xml b/sim/sim.runs/.jobs/vrs_config_5.xml new file mode 100644 index 0000000..19ce55a --- /dev/null +++ b/sim/sim.runs/.jobs/vrs_config_5.xml @@ -0,0 +1,5 @@ + + + + + diff --git a/sim/sim.runs/.jobs/vrs_config_6.xml b/sim/sim.runs/.jobs/vrs_config_6.xml new file mode 100644 index 0000000..0ea1672 --- /dev/null +++ b/sim/sim.runs/.jobs/vrs_config_6.xml @@ -0,0 +1,5 @@ + + + + + diff --git a/sim/sim.runs/.jobs/vrs_config_7.xml b/sim/sim.runs/.jobs/vrs_config_7.xml new file mode 100644 index 0000000..038c596 --- /dev/null +++ b/sim/sim.runs/.jobs/vrs_config_7.xml @@ -0,0 +1,5 @@ + + + + + diff --git a/sim/sim.runs/.jobs/vrs_config_8.xml b/sim/sim.runs/.jobs/vrs_config_8.xml new file mode 100644 index 0000000..19ce55a --- /dev/null +++ b/sim/sim.runs/.jobs/vrs_config_8.xml @@ -0,0 +1,5 @@ + + + + + diff --git a/sim/sim.runs/.jobs/vrs_config_9.xml b/sim/sim.runs/.jobs/vrs_config_9.xml new file mode 100644 index 0000000..0ea1672 --- /dev/null +++ b/sim/sim.runs/.jobs/vrs_config_9.xml @@ -0,0 +1,5 @@ + + + + + diff --git a/sim/sim.runs/impl_1/.Vivado_Implementation.queue.rst b/sim/sim.runs/impl_1/.Vivado_Implementation.queue.rst new file mode 100644 index 0000000..e69de29 diff --git a/sim/sim.runs/impl_1/.init_design.begin.rst b/sim/sim.runs/impl_1/.init_design.begin.rst new file mode 100644 index 0000000..db2a9e9 --- /dev/null +++ b/sim/sim.runs/impl_1/.init_design.begin.rst @@ -0,0 +1,5 @@ + + + + + diff --git a/sim/sim.runs/impl_1/.init_design.end.rst b/sim/sim.runs/impl_1/.init_design.end.rst new file mode 100644 index 0000000..e69de29 diff --git a/sim/sim.runs/impl_1/.opt_design.begin.rst b/sim/sim.runs/impl_1/.opt_design.begin.rst new file mode 100644 index 0000000..db2a9e9 --- /dev/null +++ b/sim/sim.runs/impl_1/.opt_design.begin.rst @@ -0,0 +1,5 @@ + + + + + diff --git a/sim/sim.runs/impl_1/.opt_design.end.rst b/sim/sim.runs/impl_1/.opt_design.end.rst new file mode 100644 index 0000000..e69de29 diff --git a/sim/sim.runs/impl_1/.place_design.begin.rst b/sim/sim.runs/impl_1/.place_design.begin.rst new file mode 100644 index 0000000..db2a9e9 --- /dev/null +++ b/sim/sim.runs/impl_1/.place_design.begin.rst @@ -0,0 +1,5 @@ + + + + + diff --git a/sim/sim.runs/impl_1/.place_design.end.rst b/sim/sim.runs/impl_1/.place_design.end.rst new file mode 100644 index 0000000..e69de29 diff --git a/sim/sim.runs/impl_1/.route_design.begin.rst b/sim/sim.runs/impl_1/.route_design.begin.rst new file mode 100644 index 0000000..db2a9e9 --- /dev/null +++ b/sim/sim.runs/impl_1/.route_design.begin.rst @@ -0,0 +1,5 @@ + + + + + diff --git a/sim/sim.runs/impl_1/.route_design.end.rst b/sim/sim.runs/impl_1/.route_design.end.rst new file mode 100644 index 0000000..e69de29 diff --git a/sim/sim.runs/impl_1/.vivado.begin.rst b/sim/sim.runs/impl_1/.vivado.begin.rst new file mode 100644 index 0000000..3821c7f --- /dev/null +++ b/sim/sim.runs/impl_1/.vivado.begin.rst @@ -0,0 +1,10 @@ + + + + + + + + + + diff --git a/sim/sim.runs/impl_1/.vivado.end.rst b/sim/sim.runs/impl_1/.vivado.end.rst new file mode 100644 index 0000000..e69de29 diff --git a/sim/sim.runs/impl_1/.write_bitstream.begin.rst b/sim/sim.runs/impl_1/.write_bitstream.begin.rst new file mode 100644 index 0000000..1eb98c5 --- /dev/null +++ b/sim/sim.runs/impl_1/.write_bitstream.begin.rst @@ -0,0 +1,5 @@ + + + + + diff --git a/sim/sim.runs/impl_1/.write_bitstream.end.rst b/sim/sim.runs/impl_1/.write_bitstream.end.rst new file mode 100644 index 0000000..e69de29 diff --git a/sim/sim.runs/impl_1/ISEWrap.js b/sim/sim.runs/impl_1/ISEWrap.js new file mode 100755 index 0000000..8284d2d --- /dev/null +++ b/sim/sim.runs/impl_1/ISEWrap.js @@ -0,0 +1,244 @@ +// +// Vivado(TM) +// ISEWrap.js: Vivado Runs Script for WSH 5.1/5.6 +// Copyright 1986-1999, 2001-2013,2015 Xilinx, Inc. All Rights Reserved. +// + +// GLOBAL VARIABLES +var ISEShell = new ActiveXObject( "WScript.Shell" ); +var ISEFileSys = new ActiveXObject( "Scripting.FileSystemObject" ); +var ISERunDir = ""; +var ISELogFile = "runme.log"; +var ISELogFileStr = null; +var ISELogEcho = true; +var ISEOldVersionWSH = false; + + + +// BOOTSTRAP +ISEInit(); + + + +// +// ISE FUNCTIONS +// +function ISEInit() { + + // 1. RUN DIR setup + var ISEScrFP = WScript.ScriptFullName; + var ISEScrN = WScript.ScriptName; + ISERunDir = + ISEScrFP.substr( 0, ISEScrFP.length - ISEScrN.length - 1 ); + + // 2. LOG file setup + ISELogFileStr = ISEOpenFile( ISELogFile ); + + // 3. LOG echo? + var ISEScriptArgs = WScript.Arguments; + for ( var loopi=0; loopi> " + ISELogFile + " 2>&1"; + ISEExitCode = ISEShell.Run( ISECmdLine, 0, true ); + ISELogFileStr = ISEOpenFile( ISELogFile ); + + } else { // WSH 5.6 + + // LAUNCH! + ISEShell.CurrentDirectory = ISERunDir; + + // Redirect STDERR to STDOUT + ISECmdLine = "%comspec% /c " + ISECmdLine + " 2>&1"; + var ISEProcess = ISEShell.Exec( ISECmdLine ); + + // BEGIN file creation + var ISENetwork = WScript.CreateObject( "WScript.Network" ); + var ISEHost = ISENetwork.ComputerName; + var ISEUser = ISENetwork.UserName; + var ISEPid = ISEProcess.ProcessID; + var ISEBeginFile = ISEOpenFile( "." + ISEStep + ".begin.rst" ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.WriteLine( " " ); + ISEBeginFile.WriteLine( " " ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.Close(); + + var ISEOutStr = ISEProcess.StdOut; + var ISEErrStr = ISEProcess.StdErr; + + // WAIT for ISEStep to finish + while ( ISEProcess.Status == 0 ) { + + // dump stdout then stderr - feels a little arbitrary + while ( !ISEOutStr.AtEndOfStream ) { + ISEStdOut( ISEOutStr.ReadLine() ); + } + + WScript.Sleep( 100 ); + } + + ISEExitCode = ISEProcess.ExitCode; + } + + ISELogFileStr.Close(); + + // END/ERROR file creation + if ( ISEExitCode != 0 ) { + ISETouchFile( ISEStep, "error" ); + + } else { + ISETouchFile( ISEStep, "end" ); + } + + return ISEExitCode; +} + + +// +// UTILITIES +// +function ISEStdOut( ISELine ) { + + ISELogFileStr.WriteLine( ISELine ); + + if ( ISELogEcho ) { + WScript.StdOut.WriteLine( ISELine ); + } +} + +function ISEStdErr( ISELine ) { + + ISELogFileStr.WriteLine( ISELine ); + + if ( ISELogEcho ) { + WScript.StdErr.WriteLine( ISELine ); + } +} + +function ISETouchFile( ISERoot, ISEStatus ) { + + var ISETFile = + ISEOpenFile( "." + ISERoot + "." + ISEStatus + ".rst" ); + ISETFile.Close(); +} + +function ISEOpenFile( ISEFilename ) { + + // This function has been updated to deal with a problem seen in CR #870871. + // In that case the user runs a script that runs impl_1, and then turns around + // and runs impl_1 -to_step write_bitstream. That second run takes place in + // the same directory, which means we may hit some of the same files, and in + // particular, we will open the runme.log file. Even though this script closes + // the file (now), we see cases where a subsequent attempt to open the file + // fails. Perhaps the OS is slow to release the lock, or the disk comes into + // play? In any case, we try to work around this by first waiting if the file + // is already there for an arbitrary 5 seconds. Then we use a try-catch block + // and try to open the file 10 times with a one second delay after each attempt. + // Again, 10 is arbitrary. But these seem to stop the hang in CR #870871. + // If there is an unrecognized exception when trying to open the file, we output + // an error message and write details to an exception.log file. + var ISEFullPath = ISERunDir + "/" + ISEFilename; + if (ISEFileSys.FileExists(ISEFullPath)) { + // File is already there. This could be a problem. Wait in case it is still in use. + WScript.Sleep(5000); + } + var i; + for (i = 0; i < 10; ++i) { + try { + return ISEFileSys.OpenTextFile(ISEFullPath, 8, true); + } catch (exception) { + var error_code = exception.number & 0xFFFF; // The other bits are a facility code. + if (error_code == 52) { // 52 is bad file name or number. + // Wait a second and try again. + WScript.Sleep(1000); + continue; + } else { + WScript.StdErr.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath); + var exceptionFilePath = ISERunDir + "/exception.log"; + if (!ISEFileSys.FileExists(exceptionFilePath)) { + WScript.StdErr.WriteLine("See file " + exceptionFilePath + " for details."); + var exceptionFile = ISEFileSys.OpenTextFile(exceptionFilePath, 8, true); + exceptionFile.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath); + exceptionFile.WriteLine("\tException name: " + exception.name); + exceptionFile.WriteLine("\tException error code: " + error_code); + exceptionFile.WriteLine("\tException message: " + exception.message); + exceptionFile.Close(); + } + throw exception; + } + } + } + // If we reached this point, we failed to open the file after 10 attempts. + // We need to error out. + WScript.StdErr.WriteLine("ERROR: Failed to open file " + ISEFullPath); + WScript.Quit(1); +} diff --git a/sim/sim.runs/impl_1/ISEWrap.sh b/sim/sim.runs/impl_1/ISEWrap.sh new file mode 100755 index 0000000..e1a8f5d --- /dev/null +++ b/sim/sim.runs/impl_1/ISEWrap.sh @@ -0,0 +1,63 @@ +#!/bin/sh + +# +# Vivado(TM) +# ISEWrap.sh: Vivado Runs Script for UNIX +# Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved. +# + +HD_LOG=$1 +shift + +# CHECK for a STOP FILE +if [ -f .stop.rst ] +then +echo "" >> $HD_LOG +echo "*** Halting run - EA reset detected ***" >> $HD_LOG +echo "" >> $HD_LOG +exit 1 +fi + +ISE_STEP=$1 +shift + +# WRITE STEP HEADER to LOG +echo "" >> $HD_LOG +echo "*** Running $ISE_STEP" >> $HD_LOG +echo " with args $@" >> $HD_LOG +echo "" >> $HD_LOG + +# LAUNCH! +$ISE_STEP "$@" >> $HD_LOG 2>&1 & + +# BEGIN file creation +ISE_PID=$! +if [ X != X$HOSTNAME ] +then +ISE_HOST=$HOSTNAME #bash +else +ISE_HOST=$HOST #csh +fi +ISE_USER=$USER +ISE_BEGINFILE=.$ISE_STEP.begin.rst +/bin/touch $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE +echo " " >> $ISE_BEGINFILE +echo " " >> $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE + +# WAIT for ISEStep to finish +wait $ISE_PID + +# END/ERROR file creation +RETVAL=$? +if [ $RETVAL -eq 0 ] +then + /bin/touch .$ISE_STEP.end.rst +else + /bin/touch .$ISE_STEP.error.rst +fi + +exit $RETVAL + diff --git a/sim/sim.runs/impl_1/gen_run.xml b/sim/sim.runs/impl_1/gen_run.xml new file mode 100644 index 0000000..b2f0eac --- /dev/null +++ b/sim/sim.runs/impl_1/gen_run.xml @@ -0,0 +1,104 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Default settings for Implementation. + + + + + + + + + + + + diff --git a/sim/sim.runs/impl_1/htr.txt b/sim/sim.runs/impl_1/htr.txt new file mode 100644 index 0000000..0670d3b --- /dev/null +++ b/sim/sim.runs/impl_1/htr.txt @@ -0,0 +1,9 @@ +# +# Vivado(TM) +# htr.txt: a Vivado-generated description of how-to-repeat the +# the basic steps of a run. Note that runme.bat/sh needs +# to be invoked for Vivado to track run status. +# Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. +# + +vivado -log midpoint.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source midpoint.tcl -notrace diff --git a/sim/sim.runs/impl_1/init_design.pb b/sim/sim.runs/impl_1/init_design.pb new file mode 100644 index 0000000..e2c802d Binary files /dev/null and b/sim/sim.runs/impl_1/init_design.pb differ diff --git a/sim/sim.runs/impl_1/midpoint.bit b/sim/sim.runs/impl_1/midpoint.bit new file mode 100644 index 0000000..b9d421e Binary files /dev/null and b/sim/sim.runs/impl_1/midpoint.bit differ diff --git a/sim/sim.runs/impl_1/midpoint.tcl b/sim/sim.runs/impl_1/midpoint.tcl new file mode 100644 index 0000000..920d862 --- /dev/null +++ b/sim/sim.runs/impl_1/midpoint.tcl @@ -0,0 +1,66 @@ +proc start_step { step } { + set stopFile ".stop.rst" + if {[file isfile .stop.rst]} { + puts "" + puts "*** Halting run - EA reset detected ***" + puts "" + puts "" + return -code error + } + set beginFile ".$step.begin.rst" + set platform "$::tcl_platform(platform)" + set user "$::tcl_platform(user)" + set pid [pid] + set host "" + if { [string equal $platform unix] } { + if { [info exist ::env(HOSTNAME)] } { + set host $::env(HOSTNAME) + } + } else { + if { [info exist ::env(COMPUTERNAME)] } { + set host $::env(COMPUTERNAME) + } + } + set ch [open $beginFile w] + puts $ch "" + puts $ch "" + puts $ch " " + puts $ch " " + puts $ch "" + close $ch +} + +proc end_step { step } { + set endFile ".$step.end.rst" + set ch [open $endFile w] + close $ch +} + +proc step_failed { step } { + set endFile ".$step.error.rst" + set ch [open $endFile w] + close $ch +} + + +start_step write_bitstream +set ACTIVE_STEP write_bitstream +set rc [catch { + create_msg_db write_bitstream.pb + set_param xicom.use_bs_reader 1 + open_checkpoint midpoint_routed.dcp + set_property webtalk.parent_dir /home/jspear/Development/School/Comp_Arc/Lab2/sim/sim.cache/wt [current_project] + catch { write_mem_info -force midpoint.mmi } + write_bitstream -force midpoint.bit + catch {write_debug_probes -no_partial_ltxfile -quiet -force debug_nets} + catch {file copy -force debug_nets.ltx midpoint.ltx} + close_msg_db -file write_bitstream.pb +} RESULT] +if {$rc} { + step_failed write_bitstream + return -code error $RESULT +} else { + end_step write_bitstream + unset ACTIVE_STEP +} + diff --git a/sim/sim.runs/impl_1/midpoint.vdi b/sim/sim.runs/impl_1/midpoint.vdi new file mode 100644 index 0000000..57bd0a6 --- /dev/null +++ b/sim/sim.runs/impl_1/midpoint.vdi @@ -0,0 +1,432 @@ +#----------------------------------------------------------- +# Vivado v2017.2 (64-bit) +# SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 +# IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 +# Start of session at: Wed Oct 25 21:40:18 2017 +# Process ID: 5899 +# Current directory: /home/jspear/Development/School/Comp_Arc/Lab2/sim/sim.runs/impl_1 +# Command line: vivado -log midpoint.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source midpoint.tcl -notrace +# Log file: /home/jspear/Development/School/Comp_Arc/Lab2/sim/sim.runs/impl_1/midpoint.vdi +# Journal file: /home/jspear/Development/School/Comp_Arc/Lab2/sim/sim.runs/impl_1/vivado.jou +#----------------------------------------------------------- +source midpoint.tcl -notrace +Design is defaulting to srcset: sources_1 +Design is defaulting to constrset: constrs_1 +INFO: [Netlist 29-17] Analyzing 4 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +INFO: [Project 1-479] Netlist was created with Vivado 2017.2 +INFO: [Device 21-403] Loading part xc7z010clg400-1 +INFO: [Project 1-570] Preparing netlist for logic optimization +Parsing XDC File [/home/jspear/Development/School/Comp_Arc/Lab2/ZYBO_Master.xdc] +Finished Parsing XDC File [/home/jspear/Development/School/Comp_Arc/Lab2/ZYBO_Master.xdc] +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +Command: opt_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7z010-clg400' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010-clg400' +Running DRC as a precondition to command opt_design + +Starting DRC Task +Command: report_drc (run_mandatory_drcs) for: opt_checks +INFO: [DRC 23-27] Running DRC with 4 threads +report_drc (run_mandatory_drcs) completed successfully +INFO: [Project 1-461] DRC finished with 0 Errors +INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information. + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.47 . Memory (MB): peak = 1378.207 ; gain = 45.016 ; free physical = 10319 ; free virtual = 20551 +INFO: [Timing 38-35] Done setting XDC timing constraints. + +Starting Logic Optimization Task + +Phase 1 Retarget +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +INFO: [Opt 31-49] Retargeted 0 cell(s). +Phase 1 Retarget | Checksum: c1ca5825 + +Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 1818.699 ; gain = 0.000 ; free physical = 9950 ; free virtual = 20182 +INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 0 cells + +Phase 2 Constant propagation +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +Phase 2 Constant propagation | Checksum: c1ca5825 + +Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 1818.699 ; gain = 0.000 ; free physical = 9950 ; free virtual = 20182 +INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells + +Phase 3 Sweep +Phase 3 Sweep | Checksum: 14fe552a6 + +Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1818.699 ; gain = 0.000 ; free physical = 9950 ; free virtual = 20182 +INFO: [Opt 31-389] Phase Sweep created 6 cells and removed 0 cells + +Phase 4 BUFG optimization +Phase 4 BUFG optimization | Checksum: 14fe552a6 + +Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1818.699 ; gain = 0.000 ; free physical = 9950 ; free virtual = 20182 +INFO: [Opt 31-389] Phase BUFG optimization created 0 cells and removed 0 cells + +Phase 5 Shift Register Optimization +Phase 5 Shift Register Optimization | Checksum: 14fe552a6 + +Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1818.699 ; gain = 0.000 ; free physical = 9950 ; free virtual = 20182 +INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells + +Starting Connectivity Check Task + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1818.699 ; gain = 0.000 ; free physical = 9950 ; free virtual = 20182 +Ending Logic Optimization Task | Checksum: 14fe552a6 + +Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1818.699 ; gain = 0.000 ; free physical = 9950 ; free virtual = 20182 + +Starting Power Optimization Task +INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns. +Ending Power Optimization Task | Checksum: 19d912689 + +Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1818.699 ; gain = 0.000 ; free physical = 9950 ; free virtual = 20182 +21 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. +opt_design completed successfully +opt_design: Time (s): cpu = 00:00:08 ; elapsed = 00:00:07 . Memory (MB): peak = 1818.699 ; gain = 485.508 ; free physical = 9950 ; free virtual = 20182 +Writing placer database... +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Write XDEF Complete: Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 1842.711 ; gain = 0.000 ; free physical = 9948 ; free virtual = 20182 +INFO: [Common 17-1381] The checkpoint '/home/jspear/Development/School/Comp_Arc/Lab2/sim/sim.runs/impl_1/midpoint_opt.dcp' has been generated. +Command: report_drc -file midpoint_drc_opted.rpt +INFO: [DRC 23-27] Running DRC with 4 threads +INFO: [Coretcl 2-168] The results of DRC are in file /home/jspear/Development/School/Comp_Arc/Lab2/sim/sim.runs/impl_1/midpoint_drc_opted.rpt. +report_drc completed successfully +INFO: [Chipscope 16-241] No debug cores found in the current design. +Before running the implement_debug_core command, either use the Set Up Debug wizard (GUI mode) +or use the create_debug_core and connect_debug_core Tcl commands to insert debug cores into the design. +Command: place_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7z010-clg400' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010-clg400' +Command: report_drc (run_mandatory_drcs) for: incr_eco_checks +INFO: [DRC 23-27] Running DRC with 4 threads +report_drc (run_mandatory_drcs) completed successfully +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. +Running DRC as a precondition to command place_design +Command: report_drc (run_mandatory_drcs) for: placer_checks +INFO: [DRC 23-27] Running DRC with 4 threads +report_drc (run_mandatory_drcs) completed successfully +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. + +Starting Placer Task +INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 4 CPUs + +Phase 1 Placer Initialization + +Phase 1.1 Placer Initialization Netlist Sorting +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1850.715 ; gain = 0.000 ; free physical = 9935 ; free virtual = 20167 +Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 14ca5cf03 + +Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1850.715 ; gain = 0.000 ; free physical = 9935 ; free virtual = 20167 +INFO: [Timing 38-35] Done setting XDC timing constraints. +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1850.715 ; gain = 0.000 ; free physical = 9935 ; free virtual = 20167 + +Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device +INFO: [Timing 38-35] Done setting XDC timing constraints. +Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: e889b640 + +Time (s): cpu = 00:00:00.32 ; elapsed = 00:00:00.24 . Memory (MB): peak = 1850.715 ; gain = 0.000 ; free physical = 9936 ; free virtual = 20168 + +Phase 1.3 Build Placer Netlist Model +Phase 1.3 Build Placer Netlist Model | Checksum: 1d803f5c8 + +Time (s): cpu = 00:00:00.33 ; elapsed = 00:00:00.24 . Memory (MB): peak = 1850.715 ; gain = 0.000 ; free physical = 9936 ; free virtual = 20168 + +Phase 1.4 Constrain Clocks/Macros +Phase 1.4 Constrain Clocks/Macros | Checksum: 1d803f5c8 + +Time (s): cpu = 00:00:00.33 ; elapsed = 00:00:00.24 . Memory (MB): peak = 1850.715 ; gain = 0.000 ; free physical = 9936 ; free virtual = 20168 +Phase 1 Placer Initialization | Checksum: 1d803f5c8 + +Time (s): cpu = 00:00:00.33 ; elapsed = 00:00:00.24 . Memory (MB): peak = 1850.715 ; gain = 0.000 ; free physical = 9936 ; free virtual = 20168 + +Phase 2 Global Placement +WARNING: [Place 46-30] place_design is not in timing mode. Skip physical synthesis in placer +Phase 2 Global Placement | Checksum: 1b5704437 + +Time (s): cpu = 00:00:00.62 ; elapsed = 00:00:00.37 . Memory (MB): peak = 1882.730 ; gain = 32.016 ; free physical = 9930 ; free virtual = 20162 + +Phase 3 Detail Placement + +Phase 3.1 Commit Multi Column Macros +Phase 3.1 Commit Multi Column Macros | Checksum: 1b5704437 + +Time (s): cpu = 00:00:00.63 ; elapsed = 00:00:00.37 . Memory (MB): peak = 1882.730 ; gain = 32.016 ; free physical = 9930 ; free virtual = 20162 + +Phase 3.2 Commit Most Macros & LUTRAMs +Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 14ee8c1ba + +Time (s): cpu = 00:00:00.64 ; elapsed = 00:00:00.37 . Memory (MB): peak = 1882.730 ; gain = 32.016 ; free physical = 9930 ; free virtual = 20162 + +Phase 3.3 Area Swap Optimization +Phase 3.3 Area Swap Optimization | Checksum: 15274315a + +Time (s): cpu = 00:00:00.65 ; elapsed = 00:00:00.38 . Memory (MB): peak = 1882.730 ; gain = 32.016 ; free physical = 9930 ; free virtual = 20162 + +Phase 3.4 Pipeline Register Optimization +Phase 3.4 Pipeline Register Optimization | Checksum: 15274315a + +Time (s): cpu = 00:00:00.66 ; elapsed = 00:00:00.38 . Memory (MB): peak = 1882.730 ; gain = 32.016 ; free physical = 9930 ; free virtual = 20162 + +Phase 3.5 Small Shape Detail Placement +Phase 3.5 Small Shape Detail Placement | Checksum: 19b131221 + +Time (s): cpu = 00:00:00.72 ; elapsed = 00:00:00.42 . Memory (MB): peak = 1882.730 ; gain = 32.016 ; free physical = 9929 ; free virtual = 20161 + +Phase 3.6 Re-assign LUT pins +Phase 3.6 Re-assign LUT pins | Checksum: 19b131221 + +Time (s): cpu = 00:00:00.72 ; elapsed = 00:00:00.42 . Memory (MB): peak = 1882.730 ; gain = 32.016 ; free physical = 9929 ; free virtual = 20161 + +Phase 3.7 Pipeline Register Optimization +Phase 3.7 Pipeline Register Optimization | Checksum: 19b131221 + +Time (s): cpu = 00:00:00.72 ; elapsed = 00:00:00.42 . Memory (MB): peak = 1882.730 ; gain = 32.016 ; free physical = 9929 ; free virtual = 20161 +Phase 3 Detail Placement | Checksum: 19b131221 + +Time (s): cpu = 00:00:00.72 ; elapsed = 00:00:00.43 . Memory (MB): peak = 1882.730 ; gain = 32.016 ; free physical = 9929 ; free virtual = 20161 + +Phase 4 Post Placement Optimization and Clean-Up + +Phase 4.1 Post Commit Optimization +Phase 4.1 Post Commit Optimization | Checksum: 19b131221 + +Time (s): cpu = 00:00:00.73 ; elapsed = 00:00:00.43 . Memory (MB): peak = 1882.730 ; gain = 32.016 ; free physical = 9929 ; free virtual = 20161 + +Phase 4.2 Post Placement Cleanup +Phase 4.2 Post Placement Cleanup | Checksum: 19b131221 + +Time (s): cpu = 00:00:00.74 ; elapsed = 00:00:00.43 . Memory (MB): peak = 1882.730 ; gain = 32.016 ; free physical = 9929 ; free virtual = 20162 + +Phase 4.3 Placer Reporting +Phase 4.3 Placer Reporting | Checksum: 19b131221 + +Time (s): cpu = 00:00:00.74 ; elapsed = 00:00:00.43 . Memory (MB): peak = 1882.730 ; gain = 32.016 ; free physical = 9929 ; free virtual = 20162 + +Phase 4.4 Final Placement Cleanup +Phase 4.4 Final Placement Cleanup | Checksum: 147869b64 + +Time (s): cpu = 00:00:00.74 ; elapsed = 00:00:00.43 . Memory (MB): peak = 1882.730 ; gain = 32.016 ; free physical = 9929 ; free virtual = 20162 +Phase 4 Post Placement Optimization and Clean-Up | Checksum: 147869b64 + +Time (s): cpu = 00:00:00.74 ; elapsed = 00:00:00.43 . Memory (MB): peak = 1882.730 ; gain = 32.016 ; free physical = 9929 ; free virtual = 20162 +Ending Placer Task | Checksum: c4929310 + +Time (s): cpu = 00:00:00.74 ; elapsed = 00:00:00.43 . Memory (MB): peak = 1882.730 ; gain = 32.016 ; free physical = 9932 ; free virtual = 20164 +36 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered. +place_design completed successfully +Writing placer database... +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Write XDEF Complete: Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1882.730 ; gain = 0.000 ; free physical = 9931 ; free virtual = 20165 +INFO: [Common 17-1381] The checkpoint '/home/jspear/Development/School/Comp_Arc/Lab2/sim/sim.runs/impl_1/midpoint_placed.dcp' has been generated. +report_io: Time (s): cpu = 00:00:00.11 ; elapsed = 00:00:00.14 . Memory (MB): peak = 1882.730 ; gain = 0.000 ; free physical = 9923 ; free virtual = 20155 +report_utilization: Time (s): cpu = 00:00:00.08 ; elapsed = 00:00:00.10 . Memory (MB): peak = 1882.730 ; gain = 0.000 ; free physical = 9929 ; free virtual = 20161 +report_control_sets: Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.08 . Memory (MB): peak = 1882.730 ; gain = 0.000 ; free physical = 9929 ; free virtual = 20161 +Command: route_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7z010-clg400' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010-clg400' +Running DRC as a precondition to command route_design +Command: report_drc (run_mandatory_drcs) for: router_checks +INFO: [DRC 23-27] Running DRC with 4 threads +report_drc (run_mandatory_drcs) completed successfully +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. + + +Starting Routing Task +INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 4 CPUs +Checksum: PlaceDB: a243f121 ConstDB: 0 ShapeSum: 224ea1ef RouteDB: 0 + +Phase 1 Build RT Design +Phase 1 Build RT Design | Checksum: 17af5ee1d + +Time (s): cpu = 00:00:09 ; elapsed = 00:00:07 . Memory (MB): peak = 1894.719 ; gain = 11.988 ; free physical = 9856 ; free virtual = 20088 + +Phase 2 Router Initialization +INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. + +Phase 2.1 Fix Topology Constraints +Phase 2.1 Fix Topology Constraints | Checksum: 17af5ee1d + +Time (s): cpu = 00:00:09 ; elapsed = 00:00:07 . Memory (MB): peak = 1908.719 ; gain = 25.988 ; free physical = 9841 ; free virtual = 20073 + +Phase 2.2 Pre Route Cleanup +Phase 2.2 Pre Route Cleanup | Checksum: 17af5ee1d + +Time (s): cpu = 00:00:09 ; elapsed = 00:00:07 . Memory (MB): peak = 1908.719 ; gain = 25.988 ; free physical = 9841 ; free virtual = 20073 + Number of Nodes with overlaps = 0 +Phase 2 Router Initialization | Checksum: 1a406675 + +Time (s): cpu = 00:00:09 ; elapsed = 00:00:07 . Memory (MB): peak = 1917.719 ; gain = 34.988 ; free physical = 9834 ; free virtual = 20066 + +Phase 3 Initial Routing +Phase 3 Initial Routing | Checksum: 3ac3d490 + +Time (s): cpu = 00:00:09 ; elapsed = 00:00:07 . Memory (MB): peak = 1917.719 ; gain = 34.988 ; free physical = 9837 ; free virtual = 20069 + +Phase 4 Rip-up And Reroute + +Phase 4.1 Global Iteration 0 + Number of Nodes with overlaps = 0 +Phase 4.1 Global Iteration 0 | Checksum: 16dd6649b + +Time (s): cpu = 00:00:09 ; elapsed = 00:00:07 . Memory (MB): peak = 1917.719 ; gain = 34.988 ; free physical = 9837 ; free virtual = 20069 +Phase 4 Rip-up And Reroute | Checksum: 16dd6649b + +Time (s): cpu = 00:00:09 ; elapsed = 00:00:07 . Memory (MB): peak = 1917.719 ; gain = 34.988 ; free physical = 9837 ; free virtual = 20069 + +Phase 5 Delay and Skew Optimization +Phase 5 Delay and Skew Optimization | Checksum: 16dd6649b + +Time (s): cpu = 00:00:09 ; elapsed = 00:00:07 . Memory (MB): peak = 1917.719 ; gain = 34.988 ; free physical = 9837 ; free virtual = 20069 + +Phase 6 Post Hold Fix + +Phase 6.1 Hold Fix Iter +Phase 6.1 Hold Fix Iter | Checksum: 16dd6649b + +Time (s): cpu = 00:00:09 ; elapsed = 00:00:07 . Memory (MB): peak = 1917.719 ; gain = 34.988 ; free physical = 9837 ; free virtual = 20069 +Phase 6 Post Hold Fix | Checksum: 16dd6649b + +Time (s): cpu = 00:00:09 ; elapsed = 00:00:07 . Memory (MB): peak = 1917.719 ; gain = 34.988 ; free physical = 9837 ; free virtual = 20069 + +Phase 7 Route finalize + +Router Utilization Summary + Global Vertical Routing Utilization = 0.0318131 % + Global Horizontal Routing Utilization = 0.0078125 % + Routable Net Status* + *Does not include unroutable nets such as driverless and loadless. + Run report_route_status for detailed report. + Number of Failed Nets = 0 + Number of Unrouted Nets = 0 + Number of Partially Routed Nets = 0 + Number of Node Overlaps = 0 + +Congestion Report +North Dir 1x1 Area, Max Cong = 16.2162%, No Congested Regions. +South Dir 1x1 Area, Max Cong = 16.2162%, No Congested Regions. +East Dir 1x1 Area, Max Cong = 7.35294%, No Congested Regions. +West Dir 1x1 Area, Max Cong = 2.94118%, No Congested Regions. +Phase 7 Route finalize | Checksum: 16dd6649b + +Time (s): cpu = 00:00:09 ; elapsed = 00:00:07 . Memory (MB): peak = 1917.719 ; gain = 34.988 ; free physical = 9837 ; free virtual = 20069 + +Phase 8 Verifying routed nets + + Verification completed successfully +Phase 8 Verifying routed nets | Checksum: 16dd6649b + +Time (s): cpu = 00:00:09 ; elapsed = 00:00:07 . Memory (MB): peak = 1919.719 ; gain = 36.988 ; free physical = 9836 ; free virtual = 20068 + +Phase 9 Depositing Routes +Phase 9 Depositing Routes | Checksum: 103b01834 + +Time (s): cpu = 00:00:09 ; elapsed = 00:00:07 . Memory (MB): peak = 1919.719 ; gain = 36.988 ; free physical = 9836 ; free virtual = 20068 +INFO: [Route 35-16] Router Completed Successfully + +Time (s): cpu = 00:00:09 ; elapsed = 00:00:07 . Memory (MB): peak = 1919.719 ; gain = 36.988 ; free physical = 9852 ; free virtual = 20084 + +Routing Is Done. +44 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered. +route_design completed successfully +route_design: Time (s): cpu = 00:00:11 ; elapsed = 00:00:08 . Memory (MB): peak = 1945.750 ; gain = 63.020 ; free physical = 9852 ; free virtual = 20084 +Writing placer database... +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Write XDEF Complete: Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 1945.750 ; gain = 0.000 ; free physical = 9850 ; free virtual = 20084 +INFO: [Common 17-1381] The checkpoint '/home/jspear/Development/School/Comp_Arc/Lab2/sim/sim.runs/impl_1/midpoint_routed.dcp' has been generated. +Command: report_drc -file midpoint_drc_routed.rpt -pb midpoint_drc_routed.pb -rpx midpoint_drc_routed.rpx +INFO: [DRC 23-27] Running DRC with 4 threads +INFO: [Coretcl 2-168] The results of DRC are in file /home/jspear/Development/School/Comp_Arc/Lab2/sim/sim.runs/impl_1/midpoint_drc_routed.rpt. +report_drc completed successfully +Command: report_methodology -file midpoint_methodology_drc_routed.rpt -rpx midpoint_methodology_drc_routed.rpx +INFO: [Timing 38-35] Done setting XDC timing constraints. +INFO: [DRC 23-133] Running Methodology with 4 threads +INFO: [Coretcl 2-1520] The results of Report Methodology are in file /home/jspear/Development/School/Comp_Arc/Lab2/sim/sim.runs/impl_1/midpoint_methodology_drc_routed.rpt. +report_methodology completed successfully +Command: report_power -file midpoint_power_routed.rpt -pb midpoint_power_summary_routed.pb -rpx midpoint_power_routed.rpx +WARNING: [Power 33-232] No user defined clocks were found in the design! +Resolution: Please specify clocks using create_clock/create_generated_clock for sequential elements. For pure combinatorial circuits, please specify a virtual clock, otherwise the vectorless estimation might be inaccurate +INFO: [Timing 38-35] Done setting XDC timing constraints. +Running Vector-less Activity Propagation... + +Finished Running Vector-less Activity Propagation +51 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered. +report_power completed successfully +INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max. +INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 4 CPUs +WARNING: [Timing 38-313] There are no user specified timing constraints. Timing constraints are needed for proper timing analysis. +INFO: [Common 17-206] Exiting Vivado at Wed Oct 25 21:40:50 2017... +#----------------------------------------------------------- +# Vivado v2017.2 (64-bit) +# SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 +# IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 +# Start of session at: Wed Oct 25 21:41:47 2017 +# Process ID: 8072 +# Current directory: /home/jspear/Development/School/Comp_Arc/Lab2/sim/sim.runs/impl_1 +# Command line: vivado -log midpoint.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source midpoint.tcl -notrace +# Log file: /home/jspear/Development/School/Comp_Arc/Lab2/sim/sim.runs/impl_1/midpoint.vdi +# Journal file: /home/jspear/Development/School/Comp_Arc/Lab2/sim/sim.runs/impl_1/vivado.jou +#----------------------------------------------------------- +source midpoint.tcl -notrace +Command: open_checkpoint midpoint_routed.dcp + +Starting open_checkpoint Task + +Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.03 . Memory (MB): peak = 1087.020 ; gain = 0.000 ; free physical = 10568 ; free virtual = 20807 +INFO: [Netlist 29-17] Analyzing 4 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +INFO: [Project 1-479] Netlist was created with Vivado 2017.2 +INFO: [Device 21-403] Loading part xc7z010clg400-1 +INFO: [Project 1-570] Preparing netlist for logic optimization +Parsing XDC File [/home/jspear/Development/School/Comp_Arc/Lab2/sim/sim.runs/impl_1/.Xil/Vivado-8072-Kreyshawn/dcp3/midpoint.xdc] +Finished Parsing XDC File [/home/jspear/Development/School/Comp_Arc/Lab2/sim/sim.runs/impl_1/.Xil/Vivado-8072-Kreyshawn/dcp3/midpoint.xdc] +Reading XDEF placement. +Reading placer database... +Reading XDEF routing. +Read XDEF File: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1307.180 ; gain = 0.000 ; free physical = 10312 ; free virtual = 20552 +Restored from archive | CPU: 0.020000 secs | Memory: 0.051208 MB | +Finished XDEF File Restore: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1307.180 ; gain = 0.000 ; free physical = 10312 ; free virtual = 20552 +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +INFO: [Project 1-604] Checkpoint was created with Vivado v2017.2 (64-bit) build 1909853 +Command: write_bitstream -force midpoint.bit +Attempting to get a license for feature 'Implementation' and/or device 'xc7z010-clg400' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010-clg400' +Running DRC as a precondition to command write_bitstream +Command: report_drc (run_mandatory_drcs) for: bitstream_checks +INFO: [DRC 23-27] Running DRC with 4 threads +WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. +report_drc (run_mandatory_drcs) completed successfully +INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings +INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. +INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. +INFO: [Designutils 20-2272] Running write_bitstream with 4 threads. +Loading data files... +Loading site data... +Loading route data... +Processing options... +Creating bitmap... +Creating bitstream... +Writing bitstream ./midpoint.bit... +INFO: [Vivado 12-1842] Bitgen Completed Successfully. +INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. +INFO: [Common 17-186] '/home/jspear/Development/School/Comp_Arc/Lab2/sim/sim.runs/impl_1/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Wed Oct 25 21:42:09 2017. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. +16 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered. +write_bitstream completed successfully +write_bitstream: Time (s): cpu = 00:00:08 ; elapsed = 00:00:10 . Memory (MB): peak = 1738.680 ; gain = 431.500 ; free physical = 10288 ; free virtual = 20526 +INFO: [Common 17-206] Exiting Vivado at Wed Oct 25 21:42:09 2017... diff --git a/sim/sim.runs/impl_1/midpoint_29201.backup.vdi b/sim/sim.runs/impl_1/midpoint_29201.backup.vdi new file mode 100644 index 0000000..d2e0834 --- /dev/null +++ b/sim/sim.runs/impl_1/midpoint_29201.backup.vdi @@ -0,0 +1,372 @@ +#----------------------------------------------------------- +# Vivado v2017.2 (64-bit) +# SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 +# IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 +# Start of session at: Wed Oct 25 21:33:23 2017 +# Process ID: 29201 +# Current directory: /home/jspear/Development/School/Comp_Arc/Lab2/sim/sim.runs/impl_1 +# Command line: vivado -log midpoint.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source midpoint.tcl -notrace +# Log file: /home/jspear/Development/School/Comp_Arc/Lab2/sim/sim.runs/impl_1/midpoint.vdi +# Journal file: /home/jspear/Development/School/Comp_Arc/Lab2/sim/sim.runs/impl_1/vivado.jou +#----------------------------------------------------------- +source midpoint.tcl -notrace +Design is defaulting to srcset: sources_1 +Design is defaulting to constrset: constrs_1 +INFO: [Netlist 29-17] Analyzing 2 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +INFO: [Project 1-479] Netlist was created with Vivado 2017.2 +INFO: [Device 21-403] Loading part xc7z010clg400-1 +INFO: [Project 1-570] Preparing netlist for logic optimization +Parsing XDC File [/home/jspear/Development/School/Comp_Arc/Lab2/ZYBO_Master.xdc] +Finished Parsing XDC File [/home/jspear/Development/School/Comp_Arc/Lab2/ZYBO_Master.xdc] +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +Command: opt_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7z010-clg400' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010-clg400' +Running DRC as a precondition to command opt_design + +Starting DRC Task +Command: report_drc (run_mandatory_drcs) for: opt_checks +INFO: [DRC 23-27] Running DRC with 4 threads +report_drc (run_mandatory_drcs) completed successfully +INFO: [Project 1-461] DRC finished with 0 Errors +INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information. + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.48 . Memory (MB): peak = 1379.207 ; gain = 46.016 ; free physical = 11262 ; free virtual = 21450 +INFO: [Timing 38-35] Done setting XDC timing constraints. + +Starting Logic Optimization Task + +Phase 1 Retarget +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +INFO: [Opt 31-49] Retargeted 0 cell(s). +Phase 1 Retarget | Checksum: 1a4acf38d + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1830.699 ; gain = 0.000 ; free physical = 10896 ; free virtual = 21084 +INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 0 cells + +Phase 2 Constant propagation +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +Phase 2 Constant propagation | Checksum: 1a4acf38d + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1830.699 ; gain = 0.000 ; free physical = 10896 ; free virtual = 21084 +INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells + +Phase 3 Sweep +Phase 3 Sweep | Checksum: 16cf96f78 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1830.699 ; gain = 0.000 ; free physical = 10896 ; free virtual = 21084 +INFO: [Opt 31-389] Phase Sweep created 7 cells and removed 0 cells + +Phase 4 BUFG optimization +Phase 4 BUFG optimization | Checksum: 16cf96f78 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.02 . Memory (MB): peak = 1830.699 ; gain = 0.000 ; free physical = 10896 ; free virtual = 21084 +INFO: [Opt 31-389] Phase BUFG optimization created 0 cells and removed 0 cells + +Phase 5 Shift Register Optimization +Phase 5 Shift Register Optimization | Checksum: 16cf96f78 + +Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 1830.699 ; gain = 0.000 ; free physical = 10896 ; free virtual = 21084 +INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells + +Starting Connectivity Check Task + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1830.699 ; gain = 0.000 ; free physical = 10896 ; free virtual = 21084 +Ending Logic Optimization Task | Checksum: 16cf96f78 + +Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 1830.699 ; gain = 0.000 ; free physical = 10896 ; free virtual = 21084 + +Starting Power Optimization Task +INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns. +Ending Power Optimization Task | Checksum: 2959f42ce + +Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1830.699 ; gain = 0.000 ; free physical = 10896 ; free virtual = 21084 +21 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. +opt_design completed successfully +opt_design: Time (s): cpu = 00:00:08 ; elapsed = 00:00:07 . Memory (MB): peak = 1830.699 ; gain = 497.508 ; free physical = 10896 ; free virtual = 21084 +Writing placer database... +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Write XDEF Complete: Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1854.711 ; gain = 0.000 ; free physical = 10895 ; free virtual = 21084 +INFO: [Common 17-1381] The checkpoint '/home/jspear/Development/School/Comp_Arc/Lab2/sim/sim.runs/impl_1/midpoint_opt.dcp' has been generated. +Command: report_drc -file midpoint_drc_opted.rpt +INFO: [DRC 23-27] Running DRC with 4 threads +INFO: [Coretcl 2-168] The results of DRC are in file /home/jspear/Development/School/Comp_Arc/Lab2/sim/sim.runs/impl_1/midpoint_drc_opted.rpt. +report_drc completed successfully +INFO: [Chipscope 16-241] No debug cores found in the current design. +Before running the implement_debug_core command, either use the Set Up Debug wizard (GUI mode) +or use the create_debug_core and connect_debug_core Tcl commands to insert debug cores into the design. +Command: place_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7z010-clg400' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010-clg400' +Command: report_drc (run_mandatory_drcs) for: incr_eco_checks +INFO: [DRC 23-27] Running DRC with 4 threads +report_drc (run_mandatory_drcs) completed successfully +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. +Running DRC as a precondition to command place_design +Command: report_drc (run_mandatory_drcs) for: placer_checks +INFO: [DRC 23-27] Running DRC with 4 threads +report_drc (run_mandatory_drcs) completed successfully +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. + +Starting Placer Task +INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 4 CPUs + +Phase 1 Placer Initialization + +Phase 1.1 Placer Initialization Netlist Sorting +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1862.715 ; gain = 0.000 ; free physical = 10892 ; free virtual = 21080 +Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 1bd56c8f9 + +Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 1862.715 ; gain = 0.000 ; free physical = 10892 ; free virtual = 21080 +INFO: [Timing 38-35] Done setting XDC timing constraints. +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1862.715 ; gain = 0.000 ; free physical = 10892 ; free virtual = 21080 + +Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device +INFO: [Timing 38-35] Done setting XDC timing constraints. +Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: ef0970d3 + +Time (s): cpu = 00:00:00.41 ; elapsed = 00:00:00.26 . Memory (MB): peak = 1862.715 ; gain = 0.000 ; free physical = 10890 ; free virtual = 21080 + +Phase 1.3 Build Placer Netlist Model +Phase 1.3 Build Placer Netlist Model | Checksum: 12646a149 + +Time (s): cpu = 00:00:00.43 ; elapsed = 00:00:00.28 . Memory (MB): peak = 1862.715 ; gain = 0.000 ; free physical = 10890 ; free virtual = 21081 + +Phase 1.4 Constrain Clocks/Macros +Phase 1.4 Constrain Clocks/Macros | Checksum: 12646a149 + +Time (s): cpu = 00:00:00.43 ; elapsed = 00:00:00.28 . Memory (MB): peak = 1862.715 ; gain = 0.000 ; free physical = 10890 ; free virtual = 21081 +Phase 1 Placer Initialization | Checksum: 12646a149 + +Time (s): cpu = 00:00:00.43 ; elapsed = 00:00:00.28 . Memory (MB): peak = 1862.715 ; gain = 0.000 ; free physical = 10890 ; free virtual = 21081 + +Phase 2 Global Placement +WARNING: [Place 46-30] place_design is not in timing mode. Skip physical synthesis in placer +Phase 2 Global Placement | Checksum: 1d6a8340e + +Time (s): cpu = 00:00:00.69 ; elapsed = 00:00:00.38 . Memory (MB): peak = 1886.727 ; gain = 24.012 ; free physical = 10884 ; free virtual = 21075 + +Phase 3 Detail Placement + +Phase 3.1 Commit Multi Column Macros +Phase 3.1 Commit Multi Column Macros | Checksum: 1d6a8340e + +Time (s): cpu = 00:00:00.70 ; elapsed = 00:00:00.38 . Memory (MB): peak = 1886.727 ; gain = 24.012 ; free physical = 10884 ; free virtual = 21075 + +Phase 3.2 Commit Most Macros & LUTRAMs +Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 1c5abcf2c + +Time (s): cpu = 00:00:00.70 ; elapsed = 00:00:00.39 . Memory (MB): peak = 1886.727 ; gain = 24.012 ; free physical = 10884 ; free virtual = 21075 + +Phase 3.3 Area Swap Optimization +Phase 3.3 Area Swap Optimization | Checksum: 11c270229 + +Time (s): cpu = 00:00:00.72 ; elapsed = 00:00:00.39 . Memory (MB): peak = 1886.727 ; gain = 24.012 ; free physical = 10884 ; free virtual = 21076 + +Phase 3.4 Pipeline Register Optimization +Phase 3.4 Pipeline Register Optimization | Checksum: 11c270229 + +Time (s): cpu = 00:00:00.72 ; elapsed = 00:00:00.39 . Memory (MB): peak = 1886.727 ; gain = 24.012 ; free physical = 10884 ; free virtual = 21076 + +Phase 3.5 Small Shape Detail Placement +Phase 3.5 Small Shape Detail Placement | Checksum: 1d1fed80c + +Time (s): cpu = 00:00:00.78 ; elapsed = 00:00:00.44 . Memory (MB): peak = 1886.727 ; gain = 24.012 ; free physical = 10883 ; free virtual = 21075 + +Phase 3.6 Re-assign LUT pins +Phase 3.6 Re-assign LUT pins | Checksum: 1d1fed80c + +Time (s): cpu = 00:00:00.78 ; elapsed = 00:00:00.44 . Memory (MB): peak = 1886.727 ; gain = 24.012 ; free physical = 10883 ; free virtual = 21075 + +Phase 3.7 Pipeline Register Optimization +Phase 3.7 Pipeline Register Optimization | Checksum: 1d1fed80c + +Time (s): cpu = 00:00:00.78 ; elapsed = 00:00:00.44 . Memory (MB): peak = 1886.727 ; gain = 24.012 ; free physical = 10883 ; free virtual = 21075 +Phase 3 Detail Placement | Checksum: 1d1fed80c + +Time (s): cpu = 00:00:00.78 ; elapsed = 00:00:00.44 . Memory (MB): peak = 1886.727 ; gain = 24.012 ; free physical = 10883 ; free virtual = 21075 + +Phase 4 Post Placement Optimization and Clean-Up + +Phase 4.1 Post Commit Optimization +Phase 4.1 Post Commit Optimization | Checksum: 1d1fed80c + +Time (s): cpu = 00:00:00.79 ; elapsed = 00:00:00.44 . Memory (MB): peak = 1886.727 ; gain = 24.012 ; free physical = 10883 ; free virtual = 21075 + +Phase 4.2 Post Placement Cleanup +Phase 4.2 Post Placement Cleanup | Checksum: 1d1fed80c + +Time (s): cpu = 00:00:00.80 ; elapsed = 00:00:00.44 . Memory (MB): peak = 1886.727 ; gain = 24.012 ; free physical = 10883 ; free virtual = 21075 + +Phase 4.3 Placer Reporting +Phase 4.3 Placer Reporting | Checksum: 1d1fed80c + +Time (s): cpu = 00:00:00.80 ; elapsed = 00:00:00.44 . Memory (MB): peak = 1886.727 ; gain = 24.012 ; free physical = 10883 ; free virtual = 21075 + +Phase 4.4 Final Placement Cleanup +Phase 4.4 Final Placement Cleanup | Checksum: 2495dc6b6 + +Time (s): cpu = 00:00:00.80 ; elapsed = 00:00:00.44 . Memory (MB): peak = 1886.727 ; gain = 24.012 ; free physical = 10883 ; free virtual = 21075 +Phase 4 Post Placement Optimization and Clean-Up | Checksum: 2495dc6b6 + +Time (s): cpu = 00:00:00.80 ; elapsed = 00:00:00.44 . Memory (MB): peak = 1886.727 ; gain = 24.012 ; free physical = 10883 ; free virtual = 21075 +Ending Placer Task | Checksum: 162e9ec5b + +Time (s): cpu = 00:00:00.80 ; elapsed = 00:00:00.45 . Memory (MB): peak = 1886.727 ; gain = 24.012 ; free physical = 10886 ; free virtual = 21078 +36 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered. +place_design completed successfully +Writing placer database... +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Write XDEF Complete: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1886.727 ; gain = 0.000 ; free physical = 10887 ; free virtual = 21080 +INFO: [Common 17-1381] The checkpoint '/home/jspear/Development/School/Comp_Arc/Lab2/sim/sim.runs/impl_1/midpoint_placed.dcp' has been generated. +report_io: Time (s): cpu = 00:00:00.10 ; elapsed = 00:00:00.13 . Memory (MB): peak = 1886.727 ; gain = 0.000 ; free physical = 10878 ; free virtual = 21071 +report_utilization: Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.10 . Memory (MB): peak = 1886.727 ; gain = 0.000 ; free physical = 10884 ; free virtual = 21077 +report_control_sets: Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.08 . Memory (MB): peak = 1886.727 ; gain = 0.000 ; free physical = 10885 ; free virtual = 21077 +Command: route_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7z010-clg400' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010-clg400' +Running DRC as a precondition to command route_design +Command: report_drc (run_mandatory_drcs) for: router_checks +INFO: [DRC 23-27] Running DRC with 4 threads +report_drc (run_mandatory_drcs) completed successfully +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. + + +Starting Routing Task +INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 4 CPUs +Checksum: PlaceDB: b2818609 ConstDB: 0 ShapeSum: b0686652 RouteDB: 0 + +Phase 1 Build RT Design +Phase 1 Build RT Design | Checksum: cfedce98 + +Time (s): cpu = 00:00:09 ; elapsed = 00:00:07 . Memory (MB): peak = 1894.719 ; gain = 7.992 ; free physical = 10805 ; free virtual = 20997 + +Phase 2 Router Initialization +INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. + +Phase 2.1 Fix Topology Constraints +Phase 2.1 Fix Topology Constraints | Checksum: cfedce98 + +Time (s): cpu = 00:00:09 ; elapsed = 00:00:07 . Memory (MB): peak = 1909.719 ; gain = 22.992 ; free physical = 10790 ; free virtual = 20983 + +Phase 2.2 Pre Route Cleanup +Phase 2.2 Pre Route Cleanup | Checksum: cfedce98 + +Time (s): cpu = 00:00:09 ; elapsed = 00:00:07 . Memory (MB): peak = 1909.719 ; gain = 22.992 ; free physical = 10790 ; free virtual = 20983 + Number of Nodes with overlaps = 0 +Phase 2 Router Initialization | Checksum: 1470ef40e + +Time (s): cpu = 00:00:09 ; elapsed = 00:00:07 . Memory (MB): peak = 1914.719 ; gain = 27.992 ; free physical = 10785 ; free virtual = 20978 + +Phase 3 Initial Routing +Phase 3 Initial Routing | Checksum: 106569aa6 + +Time (s): cpu = 00:00:09 ; elapsed = 00:00:07 . Memory (MB): peak = 1914.719 ; gain = 27.992 ; free physical = 10786 ; free virtual = 20979 + +Phase 4 Rip-up And Reroute + +Phase 4.1 Global Iteration 0 + Number of Nodes with overlaps = 0 +Phase 4.1 Global Iteration 0 | Checksum: f664493f + +Time (s): cpu = 00:00:09 ; elapsed = 00:00:07 . Memory (MB): peak = 1914.719 ; gain = 27.992 ; free physical = 10786 ; free virtual = 20979 +Phase 4 Rip-up And Reroute | Checksum: f664493f + +Time (s): cpu = 00:00:09 ; elapsed = 00:00:07 . Memory (MB): peak = 1914.719 ; gain = 27.992 ; free physical = 10786 ; free virtual = 20979 + +Phase 5 Delay and Skew Optimization +Phase 5 Delay and Skew Optimization | Checksum: f664493f + +Time (s): cpu = 00:00:09 ; elapsed = 00:00:07 . Memory (MB): peak = 1914.719 ; gain = 27.992 ; free physical = 10786 ; free virtual = 20979 + +Phase 6 Post Hold Fix + +Phase 6.1 Hold Fix Iter +Phase 6.1 Hold Fix Iter | Checksum: f664493f + +Time (s): cpu = 00:00:09 ; elapsed = 00:00:07 . Memory (MB): peak = 1914.719 ; gain = 27.992 ; free physical = 10786 ; free virtual = 20979 +Phase 6 Post Hold Fix | Checksum: f664493f + +Time (s): cpu = 00:00:09 ; elapsed = 00:00:07 . Memory (MB): peak = 1914.719 ; gain = 27.992 ; free physical = 10786 ; free virtual = 20979 + +Phase 7 Route finalize + +Router Utilization Summary + Global Vertical Routing Utilization = 0.0192849 % + Global Horizontal Routing Utilization = 0.00758272 % + Routable Net Status* + *Does not include unroutable nets such as driverless and loadless. + Run report_route_status for detailed report. + Number of Failed Nets = 0 + Number of Unrouted Nets = 0 + Number of Partially Routed Nets = 0 + Number of Node Overlaps = 0 + +Congestion Report +North Dir 1x1 Area, Max Cong = 9.90991%, No Congested Regions. +South Dir 1x1 Area, Max Cong = 11.7117%, No Congested Regions. +East Dir 1x1 Area, Max Cong = 8.82353%, No Congested Regions. +West Dir 1x1 Area, Max Cong = 2.94118%, No Congested Regions. +Phase 7 Route finalize | Checksum: f664493f + +Time (s): cpu = 00:00:09 ; elapsed = 00:00:07 . Memory (MB): peak = 1914.719 ; gain = 27.992 ; free physical = 10786 ; free virtual = 20979 + +Phase 8 Verifying routed nets + + Verification completed successfully +Phase 8 Verifying routed nets | Checksum: f664493f + +Time (s): cpu = 00:00:09 ; elapsed = 00:00:07 . Memory (MB): peak = 1916.719 ; gain = 29.992 ; free physical = 10786 ; free virtual = 20979 + +Phase 9 Depositing Routes +Phase 9 Depositing Routes | Checksum: f664493f + +Time (s): cpu = 00:00:09 ; elapsed = 00:00:07 . Memory (MB): peak = 1916.719 ; gain = 29.992 ; free physical = 10786 ; free virtual = 20979 +INFO: [Route 35-16] Router Completed Successfully + +Time (s): cpu = 00:00:09 ; elapsed = 00:00:07 . Memory (MB): peak = 1916.719 ; gain = 29.992 ; free physical = 10801 ; free virtual = 20994 + +Routing Is Done. +44 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered. +route_design completed successfully +route_design: Time (s): cpu = 00:00:11 ; elapsed = 00:00:08 . Memory (MB): peak = 1942.750 ; gain = 56.023 ; free physical = 10801 ; free virtual = 20994 +Writing placer database... +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Write XDEF Complete: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1942.750 ; gain = 0.000 ; free physical = 10801 ; free virtual = 20995 +INFO: [Common 17-1381] The checkpoint '/home/jspear/Development/School/Comp_Arc/Lab2/sim/sim.runs/impl_1/midpoint_routed.dcp' has been generated. +Command: report_drc -file midpoint_drc_routed.rpt -pb midpoint_drc_routed.pb -rpx midpoint_drc_routed.rpx +INFO: [DRC 23-27] Running DRC with 4 threads +INFO: [Coretcl 2-168] The results of DRC are in file /home/jspear/Development/School/Comp_Arc/Lab2/sim/sim.runs/impl_1/midpoint_drc_routed.rpt. +report_drc completed successfully +Command: report_methodology -file midpoint_methodology_drc_routed.rpt -rpx midpoint_methodology_drc_routed.rpx +INFO: [Timing 38-35] Done setting XDC timing constraints. +INFO: [DRC 23-133] Running Methodology with 4 threads +INFO: [Coretcl 2-1520] The results of Report Methodology are in file /home/jspear/Development/School/Comp_Arc/Lab2/sim/sim.runs/impl_1/midpoint_methodology_drc_routed.rpt. +report_methodology completed successfully +Command: report_power -file midpoint_power_routed.rpt -pb midpoint_power_summary_routed.pb -rpx midpoint_power_routed.rpx +WARNING: [Power 33-232] No user defined clocks were found in the design! +Resolution: Please specify clocks using create_clock/create_generated_clock for sequential elements. For pure combinatorial circuits, please specify a virtual clock, otherwise the vectorless estimation might be inaccurate +INFO: [Timing 38-35] Done setting XDC timing constraints. +Running Vector-less Activity Propagation... + +Finished Running Vector-less Activity Propagation +51 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered. +report_power completed successfully +INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max. +INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 4 CPUs +WARNING: [Timing 38-313] There are no user specified timing constraints. Timing constraints are needed for proper timing analysis. +INFO: [Common 17-206] Exiting Vivado at Wed Oct 25 21:33:55 2017... diff --git a/sim/sim.runs/impl_1/midpoint_5899.backup.vdi b/sim/sim.runs/impl_1/midpoint_5899.backup.vdi new file mode 100644 index 0000000..bfdb811 --- /dev/null +++ b/sim/sim.runs/impl_1/midpoint_5899.backup.vdi @@ -0,0 +1,372 @@ +#----------------------------------------------------------- +# Vivado v2017.2 (64-bit) +# SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 +# IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 +# Start of session at: Wed Oct 25 21:40:18 2017 +# Process ID: 5899 +# Current directory: /home/jspear/Development/School/Comp_Arc/Lab2/sim/sim.runs/impl_1 +# Command line: vivado -log midpoint.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source midpoint.tcl -notrace +# Log file: /home/jspear/Development/School/Comp_Arc/Lab2/sim/sim.runs/impl_1/midpoint.vdi +# Journal file: /home/jspear/Development/School/Comp_Arc/Lab2/sim/sim.runs/impl_1/vivado.jou +#----------------------------------------------------------- +source midpoint.tcl -notrace +Design is defaulting to srcset: sources_1 +Design is defaulting to constrset: constrs_1 +INFO: [Netlist 29-17] Analyzing 4 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +INFO: [Project 1-479] Netlist was created with Vivado 2017.2 +INFO: [Device 21-403] Loading part xc7z010clg400-1 +INFO: [Project 1-570] Preparing netlist for logic optimization +Parsing XDC File [/home/jspear/Development/School/Comp_Arc/Lab2/ZYBO_Master.xdc] +Finished Parsing XDC File [/home/jspear/Development/School/Comp_Arc/Lab2/ZYBO_Master.xdc] +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +Command: opt_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7z010-clg400' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010-clg400' +Running DRC as a precondition to command opt_design + +Starting DRC Task +Command: report_drc (run_mandatory_drcs) for: opt_checks +INFO: [DRC 23-27] Running DRC with 4 threads +report_drc (run_mandatory_drcs) completed successfully +INFO: [Project 1-461] DRC finished with 0 Errors +INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information. + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.47 . Memory (MB): peak = 1378.207 ; gain = 45.016 ; free physical = 10319 ; free virtual = 20551 +INFO: [Timing 38-35] Done setting XDC timing constraints. + +Starting Logic Optimization Task + +Phase 1 Retarget +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +INFO: [Opt 31-49] Retargeted 0 cell(s). +Phase 1 Retarget | Checksum: c1ca5825 + +Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 1818.699 ; gain = 0.000 ; free physical = 9950 ; free virtual = 20182 +INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 0 cells + +Phase 2 Constant propagation +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +Phase 2 Constant propagation | Checksum: c1ca5825 + +Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 1818.699 ; gain = 0.000 ; free physical = 9950 ; free virtual = 20182 +INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells + +Phase 3 Sweep +Phase 3 Sweep | Checksum: 14fe552a6 + +Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1818.699 ; gain = 0.000 ; free physical = 9950 ; free virtual = 20182 +INFO: [Opt 31-389] Phase Sweep created 6 cells and removed 0 cells + +Phase 4 BUFG optimization +Phase 4 BUFG optimization | Checksum: 14fe552a6 + +Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1818.699 ; gain = 0.000 ; free physical = 9950 ; free virtual = 20182 +INFO: [Opt 31-389] Phase BUFG optimization created 0 cells and removed 0 cells + +Phase 5 Shift Register Optimization +Phase 5 Shift Register Optimization | Checksum: 14fe552a6 + +Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1818.699 ; gain = 0.000 ; free physical = 9950 ; free virtual = 20182 +INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells + +Starting Connectivity Check Task + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1818.699 ; gain = 0.000 ; free physical = 9950 ; free virtual = 20182 +Ending Logic Optimization Task | Checksum: 14fe552a6 + +Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1818.699 ; gain = 0.000 ; free physical = 9950 ; free virtual = 20182 + +Starting Power Optimization Task +INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns. +Ending Power Optimization Task | Checksum: 19d912689 + +Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1818.699 ; gain = 0.000 ; free physical = 9950 ; free virtual = 20182 +21 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. +opt_design completed successfully +opt_design: Time (s): cpu = 00:00:08 ; elapsed = 00:00:07 . Memory (MB): peak = 1818.699 ; gain = 485.508 ; free physical = 9950 ; free virtual = 20182 +Writing placer database... +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Write XDEF Complete: Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 1842.711 ; gain = 0.000 ; free physical = 9948 ; free virtual = 20182 +INFO: [Common 17-1381] The checkpoint '/home/jspear/Development/School/Comp_Arc/Lab2/sim/sim.runs/impl_1/midpoint_opt.dcp' has been generated. +Command: report_drc -file midpoint_drc_opted.rpt +INFO: [DRC 23-27] Running DRC with 4 threads +INFO: [Coretcl 2-168] The results of DRC are in file /home/jspear/Development/School/Comp_Arc/Lab2/sim/sim.runs/impl_1/midpoint_drc_opted.rpt. +report_drc completed successfully +INFO: [Chipscope 16-241] No debug cores found in the current design. +Before running the implement_debug_core command, either use the Set Up Debug wizard (GUI mode) +or use the create_debug_core and connect_debug_core Tcl commands to insert debug cores into the design. +Command: place_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7z010-clg400' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010-clg400' +Command: report_drc (run_mandatory_drcs) for: incr_eco_checks +INFO: [DRC 23-27] Running DRC with 4 threads +report_drc (run_mandatory_drcs) completed successfully +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. +Running DRC as a precondition to command place_design +Command: report_drc (run_mandatory_drcs) for: placer_checks +INFO: [DRC 23-27] Running DRC with 4 threads +report_drc (run_mandatory_drcs) completed successfully +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. + +Starting Placer Task +INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 4 CPUs + +Phase 1 Placer Initialization + +Phase 1.1 Placer Initialization Netlist Sorting +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1850.715 ; gain = 0.000 ; free physical = 9935 ; free virtual = 20167 +Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 14ca5cf03 + +Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1850.715 ; gain = 0.000 ; free physical = 9935 ; free virtual = 20167 +INFO: [Timing 38-35] Done setting XDC timing constraints. +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1850.715 ; gain = 0.000 ; free physical = 9935 ; free virtual = 20167 + +Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device +INFO: [Timing 38-35] Done setting XDC timing constraints. +Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: e889b640 + +Time (s): cpu = 00:00:00.32 ; elapsed = 00:00:00.24 . Memory (MB): peak = 1850.715 ; gain = 0.000 ; free physical = 9936 ; free virtual = 20168 + +Phase 1.3 Build Placer Netlist Model +Phase 1.3 Build Placer Netlist Model | Checksum: 1d803f5c8 + +Time (s): cpu = 00:00:00.33 ; elapsed = 00:00:00.24 . Memory (MB): peak = 1850.715 ; gain = 0.000 ; free physical = 9936 ; free virtual = 20168 + +Phase 1.4 Constrain Clocks/Macros +Phase 1.4 Constrain Clocks/Macros | Checksum: 1d803f5c8 + +Time (s): cpu = 00:00:00.33 ; elapsed = 00:00:00.24 . Memory (MB): peak = 1850.715 ; gain = 0.000 ; free physical = 9936 ; free virtual = 20168 +Phase 1 Placer Initialization | Checksum: 1d803f5c8 + +Time (s): cpu = 00:00:00.33 ; elapsed = 00:00:00.24 . Memory (MB): peak = 1850.715 ; gain = 0.000 ; free physical = 9936 ; free virtual = 20168 + +Phase 2 Global Placement +WARNING: [Place 46-30] place_design is not in timing mode. Skip physical synthesis in placer +Phase 2 Global Placement | Checksum: 1b5704437 + +Time (s): cpu = 00:00:00.62 ; elapsed = 00:00:00.37 . Memory (MB): peak = 1882.730 ; gain = 32.016 ; free physical = 9930 ; free virtual = 20162 + +Phase 3 Detail Placement + +Phase 3.1 Commit Multi Column Macros +Phase 3.1 Commit Multi Column Macros | Checksum: 1b5704437 + +Time (s): cpu = 00:00:00.63 ; elapsed = 00:00:00.37 . Memory (MB): peak = 1882.730 ; gain = 32.016 ; free physical = 9930 ; free virtual = 20162 + +Phase 3.2 Commit Most Macros & LUTRAMs +Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 14ee8c1ba + +Time (s): cpu = 00:00:00.64 ; elapsed = 00:00:00.37 . Memory (MB): peak = 1882.730 ; gain = 32.016 ; free physical = 9930 ; free virtual = 20162 + +Phase 3.3 Area Swap Optimization +Phase 3.3 Area Swap Optimization | Checksum: 15274315a + +Time (s): cpu = 00:00:00.65 ; elapsed = 00:00:00.38 . Memory (MB): peak = 1882.730 ; gain = 32.016 ; free physical = 9930 ; free virtual = 20162 + +Phase 3.4 Pipeline Register Optimization +Phase 3.4 Pipeline Register Optimization | Checksum: 15274315a + +Time (s): cpu = 00:00:00.66 ; elapsed = 00:00:00.38 . Memory (MB): peak = 1882.730 ; gain = 32.016 ; free physical = 9930 ; free virtual = 20162 + +Phase 3.5 Small Shape Detail Placement +Phase 3.5 Small Shape Detail Placement | Checksum: 19b131221 + +Time (s): cpu = 00:00:00.72 ; elapsed = 00:00:00.42 . Memory (MB): peak = 1882.730 ; gain = 32.016 ; free physical = 9929 ; free virtual = 20161 + +Phase 3.6 Re-assign LUT pins +Phase 3.6 Re-assign LUT pins | Checksum: 19b131221 + +Time (s): cpu = 00:00:00.72 ; elapsed = 00:00:00.42 . Memory (MB): peak = 1882.730 ; gain = 32.016 ; free physical = 9929 ; free virtual = 20161 + +Phase 3.7 Pipeline Register Optimization +Phase 3.7 Pipeline Register Optimization | Checksum: 19b131221 + +Time (s): cpu = 00:00:00.72 ; elapsed = 00:00:00.42 . Memory (MB): peak = 1882.730 ; gain = 32.016 ; free physical = 9929 ; free virtual = 20161 +Phase 3 Detail Placement | Checksum: 19b131221 + +Time (s): cpu = 00:00:00.72 ; elapsed = 00:00:00.43 . Memory (MB): peak = 1882.730 ; gain = 32.016 ; free physical = 9929 ; free virtual = 20161 + +Phase 4 Post Placement Optimization and Clean-Up + +Phase 4.1 Post Commit Optimization +Phase 4.1 Post Commit Optimization | Checksum: 19b131221 + +Time (s): cpu = 00:00:00.73 ; elapsed = 00:00:00.43 . Memory (MB): peak = 1882.730 ; gain = 32.016 ; free physical = 9929 ; free virtual = 20161 + +Phase 4.2 Post Placement Cleanup +Phase 4.2 Post Placement Cleanup | Checksum: 19b131221 + +Time (s): cpu = 00:00:00.74 ; elapsed = 00:00:00.43 . Memory (MB): peak = 1882.730 ; gain = 32.016 ; free physical = 9929 ; free virtual = 20162 + +Phase 4.3 Placer Reporting +Phase 4.3 Placer Reporting | Checksum: 19b131221 + +Time (s): cpu = 00:00:00.74 ; elapsed = 00:00:00.43 . Memory (MB): peak = 1882.730 ; gain = 32.016 ; free physical = 9929 ; free virtual = 20162 + +Phase 4.4 Final Placement Cleanup +Phase 4.4 Final Placement Cleanup | Checksum: 147869b64 + +Time (s): cpu = 00:00:00.74 ; elapsed = 00:00:00.43 . Memory (MB): peak = 1882.730 ; gain = 32.016 ; free physical = 9929 ; free virtual = 20162 +Phase 4 Post Placement Optimization and Clean-Up | Checksum: 147869b64 + +Time (s): cpu = 00:00:00.74 ; elapsed = 00:00:00.43 . Memory (MB): peak = 1882.730 ; gain = 32.016 ; free physical = 9929 ; free virtual = 20162 +Ending Placer Task | Checksum: c4929310 + +Time (s): cpu = 00:00:00.74 ; elapsed = 00:00:00.43 . Memory (MB): peak = 1882.730 ; gain = 32.016 ; free physical = 9932 ; free virtual = 20164 +36 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered. +place_design completed successfully +Writing placer database... +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Write XDEF Complete: Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1882.730 ; gain = 0.000 ; free physical = 9931 ; free virtual = 20165 +INFO: [Common 17-1381] The checkpoint '/home/jspear/Development/School/Comp_Arc/Lab2/sim/sim.runs/impl_1/midpoint_placed.dcp' has been generated. +report_io: Time (s): cpu = 00:00:00.11 ; elapsed = 00:00:00.14 . Memory (MB): peak = 1882.730 ; gain = 0.000 ; free physical = 9923 ; free virtual = 20155 +report_utilization: Time (s): cpu = 00:00:00.08 ; elapsed = 00:00:00.10 . Memory (MB): peak = 1882.730 ; gain = 0.000 ; free physical = 9929 ; free virtual = 20161 +report_control_sets: Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.08 . Memory (MB): peak = 1882.730 ; gain = 0.000 ; free physical = 9929 ; free virtual = 20161 +Command: route_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7z010-clg400' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010-clg400' +Running DRC as a precondition to command route_design +Command: report_drc (run_mandatory_drcs) for: router_checks +INFO: [DRC 23-27] Running DRC with 4 threads +report_drc (run_mandatory_drcs) completed successfully +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. + + +Starting Routing Task +INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 4 CPUs +Checksum: PlaceDB: a243f121 ConstDB: 0 ShapeSum: 224ea1ef RouteDB: 0 + +Phase 1 Build RT Design +Phase 1 Build RT Design | Checksum: 17af5ee1d + +Time (s): cpu = 00:00:09 ; elapsed = 00:00:07 . Memory (MB): peak = 1894.719 ; gain = 11.988 ; free physical = 9856 ; free virtual = 20088 + +Phase 2 Router Initialization +INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. + +Phase 2.1 Fix Topology Constraints +Phase 2.1 Fix Topology Constraints | Checksum: 17af5ee1d + +Time (s): cpu = 00:00:09 ; elapsed = 00:00:07 . Memory (MB): peak = 1908.719 ; gain = 25.988 ; free physical = 9841 ; free virtual = 20073 + +Phase 2.2 Pre Route Cleanup +Phase 2.2 Pre Route Cleanup | Checksum: 17af5ee1d + +Time (s): cpu = 00:00:09 ; elapsed = 00:00:07 . Memory (MB): peak = 1908.719 ; gain = 25.988 ; free physical = 9841 ; free virtual = 20073 + Number of Nodes with overlaps = 0 +Phase 2 Router Initialization | Checksum: 1a406675 + +Time (s): cpu = 00:00:09 ; elapsed = 00:00:07 . Memory (MB): peak = 1917.719 ; gain = 34.988 ; free physical = 9834 ; free virtual = 20066 + +Phase 3 Initial Routing +Phase 3 Initial Routing | Checksum: 3ac3d490 + +Time (s): cpu = 00:00:09 ; elapsed = 00:00:07 . Memory (MB): peak = 1917.719 ; gain = 34.988 ; free physical = 9837 ; free virtual = 20069 + +Phase 4 Rip-up And Reroute + +Phase 4.1 Global Iteration 0 + Number of Nodes with overlaps = 0 +Phase 4.1 Global Iteration 0 | Checksum: 16dd6649b + +Time (s): cpu = 00:00:09 ; elapsed = 00:00:07 . Memory (MB): peak = 1917.719 ; gain = 34.988 ; free physical = 9837 ; free virtual = 20069 +Phase 4 Rip-up And Reroute | Checksum: 16dd6649b + +Time (s): cpu = 00:00:09 ; elapsed = 00:00:07 . Memory (MB): peak = 1917.719 ; gain = 34.988 ; free physical = 9837 ; free virtual = 20069 + +Phase 5 Delay and Skew Optimization +Phase 5 Delay and Skew Optimization | Checksum: 16dd6649b + +Time (s): cpu = 00:00:09 ; elapsed = 00:00:07 . Memory (MB): peak = 1917.719 ; gain = 34.988 ; free physical = 9837 ; free virtual = 20069 + +Phase 6 Post Hold Fix + +Phase 6.1 Hold Fix Iter +Phase 6.1 Hold Fix Iter | Checksum: 16dd6649b + +Time (s): cpu = 00:00:09 ; elapsed = 00:00:07 . Memory (MB): peak = 1917.719 ; gain = 34.988 ; free physical = 9837 ; free virtual = 20069 +Phase 6 Post Hold Fix | Checksum: 16dd6649b + +Time (s): cpu = 00:00:09 ; elapsed = 00:00:07 . Memory (MB): peak = 1917.719 ; gain = 34.988 ; free physical = 9837 ; free virtual = 20069 + +Phase 7 Route finalize + +Router Utilization Summary + Global Vertical Routing Utilization = 0.0318131 % + Global Horizontal Routing Utilization = 0.0078125 % + Routable Net Status* + *Does not include unroutable nets such as driverless and loadless. + Run report_route_status for detailed report. + Number of Failed Nets = 0 + Number of Unrouted Nets = 0 + Number of Partially Routed Nets = 0 + Number of Node Overlaps = 0 + +Congestion Report +North Dir 1x1 Area, Max Cong = 16.2162%, No Congested Regions. +South Dir 1x1 Area, Max Cong = 16.2162%, No Congested Regions. +East Dir 1x1 Area, Max Cong = 7.35294%, No Congested Regions. +West Dir 1x1 Area, Max Cong = 2.94118%, No Congested Regions. +Phase 7 Route finalize | Checksum: 16dd6649b + +Time (s): cpu = 00:00:09 ; elapsed = 00:00:07 . Memory (MB): peak = 1917.719 ; gain = 34.988 ; free physical = 9837 ; free virtual = 20069 + +Phase 8 Verifying routed nets + + Verification completed successfully +Phase 8 Verifying routed nets | Checksum: 16dd6649b + +Time (s): cpu = 00:00:09 ; elapsed = 00:00:07 . Memory (MB): peak = 1919.719 ; gain = 36.988 ; free physical = 9836 ; free virtual = 20068 + +Phase 9 Depositing Routes +Phase 9 Depositing Routes | Checksum: 103b01834 + +Time (s): cpu = 00:00:09 ; elapsed = 00:00:07 . Memory (MB): peak = 1919.719 ; gain = 36.988 ; free physical = 9836 ; free virtual = 20068 +INFO: [Route 35-16] Router Completed Successfully + +Time (s): cpu = 00:00:09 ; elapsed = 00:00:07 . Memory (MB): peak = 1919.719 ; gain = 36.988 ; free physical = 9852 ; free virtual = 20084 + +Routing Is Done. +44 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered. +route_design completed successfully +route_design: Time (s): cpu = 00:00:11 ; elapsed = 00:00:08 . Memory (MB): peak = 1945.750 ; gain = 63.020 ; free physical = 9852 ; free virtual = 20084 +Writing placer database... +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Write XDEF Complete: Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 1945.750 ; gain = 0.000 ; free physical = 9850 ; free virtual = 20084 +INFO: [Common 17-1381] The checkpoint '/home/jspear/Development/School/Comp_Arc/Lab2/sim/sim.runs/impl_1/midpoint_routed.dcp' has been generated. +Command: report_drc -file midpoint_drc_routed.rpt -pb midpoint_drc_routed.pb -rpx midpoint_drc_routed.rpx +INFO: [DRC 23-27] Running DRC with 4 threads +INFO: [Coretcl 2-168] The results of DRC are in file /home/jspear/Development/School/Comp_Arc/Lab2/sim/sim.runs/impl_1/midpoint_drc_routed.rpt. +report_drc completed successfully +Command: report_methodology -file midpoint_methodology_drc_routed.rpt -rpx midpoint_methodology_drc_routed.rpx +INFO: [Timing 38-35] Done setting XDC timing constraints. +INFO: [DRC 23-133] Running Methodology with 4 threads +INFO: [Coretcl 2-1520] The results of Report Methodology are in file /home/jspear/Development/School/Comp_Arc/Lab2/sim/sim.runs/impl_1/midpoint_methodology_drc_routed.rpt. +report_methodology completed successfully +Command: report_power -file midpoint_power_routed.rpt -pb midpoint_power_summary_routed.pb -rpx midpoint_power_routed.rpx +WARNING: [Power 33-232] No user defined clocks were found in the design! +Resolution: Please specify clocks using create_clock/create_generated_clock for sequential elements. For pure combinatorial circuits, please specify a virtual clock, otherwise the vectorless estimation might be inaccurate +INFO: [Timing 38-35] Done setting XDC timing constraints. +Running Vector-less Activity Propagation... + +Finished Running Vector-less Activity Propagation +51 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered. +report_power completed successfully +INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max. +INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 4 CPUs +WARNING: [Timing 38-313] There are no user specified timing constraints. Timing constraints are needed for proper timing analysis. +INFO: [Common 17-206] Exiting Vivado at Wed Oct 25 21:40:50 2017... diff --git a/sim/sim.runs/impl_1/midpoint_clock_utilization_routed.rpt b/sim/sim.runs/impl_1/midpoint_clock_utilization_routed.rpt new file mode 100644 index 0000000..5955862 --- /dev/null +++ b/sim/sim.runs/impl_1/midpoint_clock_utilization_routed.rpt @@ -0,0 +1,154 @@ +Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. +-------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2017.2 (lin64) Build 1909853 Thu Jun 15 18:39:10 MDT 2017 +| Date : Wed Oct 25 21:40:50 2017 +| Host : Kreyshawn running 64-bit Ubuntu 14.04.5 LTS +| Command : report_clock_utilization -file midpoint_clock_utilization_routed.rpt +| Design : midpoint +| Device : 7z010-clg400 +| Speed File : -1 PRODUCTION 1.11 2014-09-11 +-------------------------------------------------------------------------------------- + +Clock Utilization Report + +Table of Contents +----------------- +1. Clock Primitive Utilization +2. Global Clock Resources +3. Global Clock Source Details +4. Clock Regions: Key Resource Utilization +5. Clock Regions : Global Clock Summary +6. Device Cell Placement Summary for Global Clock g0 +7. Clock Region Cell Placement per Global Clock: Region X1Y0 +8. Clock Region Cell Placement per Global Clock: Region X1Y1 + +1. Clock Primitive Utilization +------------------------------ + ++----------+------+-----------+-----+--------------+--------+ +| Type | Used | Available | LOC | Clock Region | Pblock | ++----------+------+-----------+-----+--------------+--------+ +| BUFGCTRL | 1 | 32 | 0 | 0 | 0 | +| BUFH | 0 | 48 | 0 | 0 | 0 | +| BUFIO | 0 | 8 | 0 | 0 | 0 | +| BUFMR | 0 | 4 | 0 | 0 | 0 | +| BUFR | 0 | 8 | 0 | 0 | 0 | +| MMCM | 0 | 2 | 0 | 0 | 0 | +| PLL | 0 | 2 | 0 | 0 | 0 | ++----------+------+-----------+-----+--------------+--------+ + + +2. Global Clock Resources +------------------------- + ++-----------+-----------+-----------------+------------+----------------+--------------+-------------------+-------------+-----------------+--------------+-------+----------------------+---------------+ +| Global Id | Source Id | Driver Type/Pin | Constraint | Site | Clock Region | Load Clock Region | Clock Loads | Non-Clock Loads | Clock Period | Clock | Driver Pin | Net | ++-----------+-----------+-----------------+------------+----------------+--------------+-------------------+-------------+-----------------+--------------+-------+----------------------+---------------+ +| g0 | src0 | BUFG/O | None | BUFGCTRL_X0Y16 | n/a | 2 | 28 | 0 | | | clk_IBUF_BUFG_inst/O | clk_IBUF_BUFG | ++-----------+-----------+-----------------+------------+----------------+--------------+-------------------+-------------+-----------------+--------------+-------+----------------------+---------------+ +* Clock Loads column represents the clock pin loads (pin count) +** Non-Clock Loads column represents the non-clock pin loads (pin count) + + +3. Global Clock Source Details +------------------------------ + ++-----------+-----------+-----------------+------------+-----------+--------------+-------------+-----------------+---------------------+--------------+-----------------+----------+ +| Source Id | Global Id | Driver Type/Pin | Constraint | Site | Clock Region | Clock Loads | Non-Clock Loads | Source Clock Period | Source Clock | Driver Pin | Net | ++-----------+-----------+-----------------+------------+-----------+--------------+-------------+-----------------+---------------------+--------------+-----------------+----------+ +| src0 | g0 | IBUF/O | IOB_X0Y78 | IOB_X0Y78 | X1Y1 | 1 | 0 | | | clk_IBUF_inst/O | clk_IBUF | ++-----------+-----------+-----------------+------------+-----------+--------------+-------------+-----------------+---------------------+--------------+-----------------+----------+ +* Clock Loads column represents the clock pin loads (pin count) +** Non-Clock Loads column represents the non-clock pin loads (pin count) + + +4. Clock Regions: Key Resource Utilization +------------------------------------------ + ++-------------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+ +| | Global Clock | BUFRs | BUFMRs | BUFIOs | MMCM | PLL | GT | PCI | ILOGIC | OLOGIC | FF | LUTM | RAMB18 | RAMB36 | DSP48E2 | ++-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+ +| Clock Region Name | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | ++-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+ +| X0Y0 | 0 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1100 | 0 | 400 | 0 | 20 | 0 | 10 | 0 | 20 | +| X1Y0 | 1 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 27 | 1100 | 14 | 350 | 0 | 40 | 0 | 20 | 0 | 20 | +| X0Y1 | 0 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1100 | 0 | 400 | 0 | 20 | 0 | 10 | 0 | 20 | +| X1Y1 | 1 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 1 | 1100 | 1 | 350 | 0 | 40 | 0 | 20 | 0 | 20 | ++-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+ +* Global Clock column represents track count; while other columns represents cell counts + + +5. Clock Regions : Global Clock Summary +--------------------------------------- + ++----+----+----+ +| | X0 | X1 | ++----+----+----+ +| Y1 | 0 | 1 | +| Y0 | 0 | 1 | ++----+----+----+ + + +6. Device Cell Placement Summary for Global Clock g0 +---------------------------------------------------- + ++-----------+-----------------+-------------------+-------+-------------+---------------+-------------+----------+----------------+----------+---------------+ +| Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net | ++-----------+-----------------+-------------------+-------+-------------+---------------+-------------+----------+----------------+----------+---------------+ +| g0 | BUFG/O | n/a | | | | 28 | 0 | 0 | 0 | clk_IBUF_BUFG | ++-----------+-----------------+-------------------+-------+-------------+---------------+-------------+----------+----------------+----------+---------------+ +* Logic Loads column represents load cell count of all cell types other than IO, GT and clock resources +** IO Loads column represents load cell count of IO types +*** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc) +**** GT Loads column represents load cell count of GT types + + ++----+----+-----+ +| | X0 | X1 | ++----+----+-----+ +| Y1 | 0 | 1 | +| Y0 | 0 | 27 | ++----+----+-----+ + + +7. Clock Region Cell Placement per Global Clock: Region X1Y0 +------------------------------------------------------------ + ++-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+---------------+ +| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net | ++-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+---------------+ +| g0 | n/a | BUFG/O | None | 27 | 0 | 27 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | clk_IBUF_BUFG | ++-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+---------------+ +* Clock Loads column represents the clock pin loads (pin count) +** Non-Clock Loads column represents the non-clock pin loads (pin count) +*** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts + + +8. Clock Region Cell Placement per Global Clock: Region X1Y1 +------------------------------------------------------------ + ++-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+---------------+ +| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net | ++-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+---------------+ +| g0 | n/a | BUFG/O | None | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | clk_IBUF_BUFG | ++-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+---------------+ +* Clock Loads column represents the clock pin loads (pin count) +** Non-Clock Loads column represents the non-clock pin loads (pin count) +*** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts + + + +# Location of BUFG Primitives +set_property LOC BUFGCTRL_X0Y16 [get_cells clk_IBUF_BUFG_inst] + +# Location of IO Primitives which is load of clock spine + +# Location of clock ports +set_property LOC IOB_X0Y78 [get_ports clk] + +# Clock net "clk_IBUF_BUFG" driven by instance "clk_IBUF_BUFG_inst" located at site "BUFGCTRL_X0Y16" +#startgroup +create_pblock {CLKAG_clk_IBUF_BUFG} +add_cells_to_pblock [get_pblocks {CLKAG_clk_IBUF_BUFG}] [get_cells -filter { PRIMITIVE_GROUP != I/O && IS_PRIMITIVE==1 && PRIMITIVE_LEVEL !=INTERNAL } -of_object [get_pins -filter {DIRECTION==IN} -of_objects [get_nets -hierarchical -filter {PARENT=="clk_IBUF_BUFG"}]]] +resize_pblock [get_pblocks {CLKAG_clk_IBUF_BUFG}] -add {CLOCKREGION_X1Y0:CLOCKREGION_X1Y0 CLOCKREGION_X1Y1:CLOCKREGION_X1Y1} +#endgroup diff --git a/sim/sim.runs/impl_1/midpoint_control_sets_placed.rpt b/sim/sim.runs/impl_1/midpoint_control_sets_placed.rpt new file mode 100644 index 0000000..a7826de --- /dev/null +++ b/sim/sim.runs/impl_1/midpoint_control_sets_placed.rpt @@ -0,0 +1,63 @@ +Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. +------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2017.2 (lin64) Build 1909853 Thu Jun 15 18:39:10 MDT 2017 +| Date : Wed Oct 25 21:40:39 2017 +| Host : Kreyshawn running 64-bit Ubuntu 14.04.5 LTS +| Command : report_control_sets -verbose -file midpoint_control_sets_placed.rpt +| Design : midpoint +| Device : xc7z010 +------------------------------------------------------------------------------------- + +Control Set Information + +Table of Contents +----------------- +1. Summary +2. Flip-Flop Distribution +3. Detailed Control Set Information + +1. Summary +---------- + ++----------------------------------------------------------+-------+ +| Status | Count | ++----------------------------------------------------------+-------+ +| Number of unique control sets | 2 | +| Unused register locations in slices containing registers | 4 | ++----------------------------------------------------------+-------+ + + +2. Flip-Flop Distribution +------------------------- + ++--------------+-----------------------+------------------------+-----------------+--------------+ +| Clock Enable | Synchronous Set/Reset | Asynchronous Set/Reset | Total Registers | Total Slices | ++--------------+-----------------------+------------------------+-----------------+--------------+ +| No | No | No | 15 | 6 | +| No | No | Yes | 0 | 0 | +| No | Yes | No | 0 | 0 | +| Yes | No | No | 0 | 0 | +| Yes | No | Yes | 0 | 0 | +| Yes | Yes | No | 13 | 3 | ++--------------+-----------------------+------------------------+-----------------+--------------+ + + +3. Detailed Control Set Information +----------------------------------- + ++----------------+----------------+------------------+------------------+----------------+ +| Clock Signal | Enable Signal | Set/Reset Signal | Slice Load Count | Bel Load Count | ++----------------+----------------+------------------+------------------+----------------+ +| clk_IBUF_BUFG | i1/data_reg[7] | i1/neg_edg | 3 | 13 | +| clk_IBUF_BUFG | | | 6 | 15 | ++----------------+----------------+------------------+------------------+----------------+ + + ++--------+-----------------------+ +| Fanout | Number of ControlSets | ++--------+-----------------------+ +| 13 | 1 | +| 15 | 1 | ++--------+-----------------------+ + + diff --git a/sim/sim.runs/impl_1/midpoint_drc_opted.rpt b/sim/sim.runs/impl_1/midpoint_drc_opted.rpt new file mode 100644 index 0000000..634d3df --- /dev/null +++ b/sim/sim.runs/impl_1/midpoint_drc_opted.rpt @@ -0,0 +1,41 @@ +Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. +------------------------------------------------------------------------------------ +| Tool Version : Vivado v.2017.2 (lin64) Build 1909853 Thu Jun 15 18:39:10 MDT 2017 +| Date : Wed Oct 25 21:40:38 2017 +| Host : Kreyshawn running 64-bit Ubuntu 14.04.5 LTS +| Command : report_drc -file midpoint_drc_opted.rpt +| Design : midpoint +| Device : xc7z010clg400-1 +| Speed File : -1 +| Design State : Synthesized +------------------------------------------------------------------------------------ + +Report DRC + +Table of Contents +----------------- +1. REPORT SUMMARY +2. REPORT DETAILS + +1. REPORT SUMMARY +----------------- + Netlist: netlist + Floorplan: design_1 + Design limits: + Ruledeck: default + Max violations: + Violations found: 1 ++--------+----------+--------------------+------------+ +| Rule | Severity | Description | Violations | ++--------+----------+--------------------+------------+ +| ZPS7-1 | Warning | PS7 block required | 1 | ++--------+----------+--------------------+------------+ + +2. REPORT DETAILS +----------------- +ZPS7-1#1 Warning +PS7 block required +The PS7 cell must be used in this Zynq design in order to enable correct default configuration. +Related violations: + + diff --git a/sim/sim.runs/impl_1/midpoint_drc_routed.pb b/sim/sim.runs/impl_1/midpoint_drc_routed.pb new file mode 100644 index 0000000..70698d1 Binary files /dev/null and b/sim/sim.runs/impl_1/midpoint_drc_routed.pb differ diff --git a/sim/sim.runs/impl_1/midpoint_drc_routed.rpt b/sim/sim.runs/impl_1/midpoint_drc_routed.rpt new file mode 100644 index 0000000..3bb4a21 --- /dev/null +++ b/sim/sim.runs/impl_1/midpoint_drc_routed.rpt @@ -0,0 +1,41 @@ +Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. +------------------------------------------------------------------------------------------------------------------ +| Tool Version : Vivado v.2017.2 (lin64) Build 1909853 Thu Jun 15 18:39:10 MDT 2017 +| Date : Wed Oct 25 21:40:48 2017 +| Host : Kreyshawn running 64-bit Ubuntu 14.04.5 LTS +| Command : report_drc -file midpoint_drc_routed.rpt -pb midpoint_drc_routed.pb -rpx midpoint_drc_routed.rpx +| Design : midpoint +| Device : xc7z010clg400-1 +| Speed File : -1 +| Design State : Routed +------------------------------------------------------------------------------------------------------------------ + +Report DRC + +Table of Contents +----------------- +1. REPORT SUMMARY +2. REPORT DETAILS + +1. REPORT SUMMARY +----------------- + Netlist: netlist + Floorplan: design_1 + Design limits: + Ruledeck: default + Max violations: + Violations found: 1 ++--------+----------+--------------------+------------+ +| Rule | Severity | Description | Violations | ++--------+----------+--------------------+------------+ +| ZPS7-1 | Warning | PS7 block required | 1 | ++--------+----------+--------------------+------------+ + +2. REPORT DETAILS +----------------- +ZPS7-1#1 Warning +PS7 block required +The PS7 cell must be used in this Zynq design in order to enable correct default configuration. +Related violations: + + diff --git a/sim/sim.runs/impl_1/midpoint_drc_routed.rpx b/sim/sim.runs/impl_1/midpoint_drc_routed.rpx new file mode 100644 index 0000000..6be4760 Binary files /dev/null and b/sim/sim.runs/impl_1/midpoint_drc_routed.rpx differ diff --git a/sim/sim.runs/impl_1/midpoint_io_placed.rpt b/sim/sim.runs/impl_1/midpoint_io_placed.rpt new file mode 100644 index 0000000..a4dc874 --- /dev/null +++ b/sim/sim.runs/impl_1/midpoint_io_placed.rpt @@ -0,0 +1,442 @@ +Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. +------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2017.2 (lin64) Build 1909853 Thu Jun 15 18:39:10 MDT 2017 +| Date : Wed Oct 25 21:40:39 2017 +| Host : Kreyshawn running 64-bit Ubuntu 14.04.5 LTS +| Command : report_io -file midpoint_io_placed.rpt +| Design : midpoint +| Device : xc7z010 +| Speed File : -1 +| Package : clg400 +| Package Version : FINAL 2012-10-23 +| Package Pin Delay Version : VERS. 2.0 2012-10-23 +------------------------------------------------------------------------------------------------- + +IO Information + +Table of Contents +----------------- +1. Summary +2. IO Assignments by Package Pin + +1. Summary +---------- + ++---------------+ +| Total User IO | ++---------------+ +| 12 | ++---------------+ + + +2. IO Assignments by Package Pin +-------------------------------- + ++------------+-------------+------------+-------------------------+---------------+-------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+------+------------------+ +| Pin Number | Signal Name | Bank Type | Pin Name | Use | IO Standard | IO Bank | Drive (mA) | Slew | On-Chip Termination | Off-Chip Termination | Voltage | Constraint | Pull Type | DQS Bias | Vref | Signal Integrity | ++------------+-------------+------------+-------------------------+---------------+-------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+------+------------------+ +| A1 | | | PS_DDR_DM0_502 | PSS IO | | | | | | | | | | | | | +| A2 | | | PS_DDR_DQ2_502 | PSS IO | | | | | | | | | | | | | +| A3 | | | VCCO_DDR_502 | VCCO | | | | | | | any** | | | | | | +| A4 | | | PS_DDR_DQ3_502 | PSS IO | | | | | | | | | | | | | +| A5 | | | PS_MIO6_500 | PSS IO | | | | | | | | | | | | | +| A6 | | | PS_MIO5_500 | PSS IO | | | | | | | | | | | | | +| A7 | | | PS_MIO1_500 | PSS IO | | | | | | | | | | | | | +| A8 | | | GND | GND | | | | | | | 0.0 | | | | | | +| A9 | | | PS_MIO43_501 | PSS IO | | | | | | | | | | | | | +| A10 | | | PS_MIO37_501 | PSS IO | | | | | | | | | | | | | +| A11 | | | PS_MIO36_501 | PSS IO | | | | | | | | | | | | | +| A12 | | | PS_MIO34_501 | PSS IO | | | | | | | | | | | | | +| A13 | | | VCCO_MIO1_501 | VCCO | | | | | | | any** | | | | | | +| A14 | | | PS_MIO32_501 | PSS IO | | | | | | | | | | | | | +| A15 | | | PS_MIO26_501 | PSS IO | | | | | | | | | | | | | +| A16 | | | PS_MIO24_501 | PSS IO | | | | | | | | | | | | | +| A17 | | | PS_MIO20_501 | PSS IO | | | | | | | | | | | | | +| A18 | | | GND | GND | | | | | | | 0.0 | | | | | | +| A19 | | | PS_MIO16_501 | PSS IO | | | | | | | | | | | | | +| A20 | | High Range | IO_L2N_T0_AD8N_35 | User IO | | 35 | | | | | | | | | | | +| B1 | | | GND | GND | | | | | | | 0.0 | | | | | | +| B2 | | | PS_DDR_DQS_N0_502 | PSS IO | | | | | | | | | | | | | +| B3 | | | PS_DDR_DQ1_502 | PSS IO | | | | | | | | | | | | | +| B4 | | | PS_DDR_DRST_B_502 | PSS IO | | | | | | | | | | | | | +| B5 | | | PS_MIO9_500 | PSS IO | | | | | | | | | | | | | +| B6 | | | VCCO_MIO0_500 | VCCO | | | | | | | any** | | | | | | +| B7 | | | PS_MIO4_500 | PSS IO | | | | | | | | | | | | | +| B8 | | | PS_MIO2_500 | PSS IO | | | | | | | | | | | | | +| B9 | | | PS_MIO51_501 | PSS IO | | | | | | | | | | | | | +| B10 | | | PS_SRST_B_501 | PSS IO | | | | | | | | | | | | | +| B11 | | | GND | GND | | | | | | | 0.0 | | | | | | +| B12 | | | PS_MIO48_501 | PSS IO | | | | | | | | | | | | | +| B13 | | | PS_MIO50_501 | PSS IO | | | | | | | | | | | | | +| B14 | | | PS_MIO47_501 | PSS IO | | | | | | | | | | | | | +| B15 | | | PS_MIO45_501 | PSS IO | | | | | | | | | | | | | +| B16 | | | VCCO_MIO1_501 | VCCO | | | | | | | any** | | | | | | +| B17 | | | PS_MIO22_501 | PSS IO | | | | | | | | | | | | | +| B18 | | | PS_MIO18_501 | PSS IO | | | | | | | | | | | | | +| B19 | | High Range | IO_L2P_T0_AD8P_35 | User IO | | 35 | | | | | | | | | | | +| B20 | | High Range | IO_L1N_T0_AD0N_35 | User IO | | 35 | | | | | | | | | | | +| C1 | | | PS_DDR_DQ6_502 | PSS IO | | | | | | | | | | | | | +| C2 | | | PS_DDR_DQS_P0_502 | PSS IO | | | | | | | | | | | | | +| C3 | | | PS_DDR_DQ0_502 | PSS IO | | | | | | | | | | | | | +| C4 | | | GND | GND | | | | | | | 0.0 | | | | | | +| C5 | | | PS_MIO14_500 | PSS IO | | | | | | | | | | | | | +| C6 | | | PS_MIO11_500 | PSS IO | | | | | | | | | | | | | +| C7 | | | PS_POR_B_500 | PSS IO | | | | | | | | | | | | | +| C8 | | | PS_MIO15_500 | PSS IO | | | | | | | | | | | | | +| C9 | | | GND | GND | | | | | | | 0.0 | | | | | | +| C10 | | | PS_MIO52_501 | PSS IO | | | | | | | | | | | | | +| C11 | | | PS_MIO53_501 | PSS IO | | | | | | | | | | | | | +| C12 | | | PS_MIO49_501 | PSS IO | | | | | | | | | | | | | +| C13 | | | PS_MIO29_501 | PSS IO | | | | | | | | | | | | | +| C14 | | | GND | GND | | | | | | | 0.0 | | | | | | +| C15 | | | PS_MIO30_501 | PSS IO | | | | | | | | | | | | | +| C16 | | | PS_MIO28_501 | PSS IO | | | | | | | | | | | | | +| C17 | | | PS_MIO41_501 | PSS IO | | | | | | | | | | | | | +| C18 | | | PS_MIO39_501 | PSS IO | | | | | | | | | | | | | +| C19 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | +| C20 | | High Range | IO_L1P_T0_AD0P_35 | User IO | | 35 | | | | | | | | | | | +| D1 | | | PS_DDR_DQ5_502 | PSS IO | | | | | | | | | | | | | +| D2 | | | VCCO_DDR_502 | VCCO | | | | | | | any** | | | | | | +| D3 | | | PS_DDR_DQ4_502 | PSS IO | | | | | | | | | | | | | +| D4 | | | PS_DDR_A13_502 | PSS IO | | | | | | | | | | | | | +| D5 | | | PS_MIO8_500 | PSS IO | | | | | | | | | | | | | +| D6 | | | PS_MIO3_500 | PSS IO | | | | | | | | | | | | | +| D7 | | | VCCO_MIO0_500 | VCCO | | | | | | | any** | | | | | | +| D8 | | | PS_MIO7_500 | PSS IO | | | | | | | | | | | | | +| D9 | | | PS_MIO12_500 | PSS IO | | | | | | | | | | | | | +| D10 | | | PS_MIO19_501 | PSS IO | | | | | | | | | | | | | +| D11 | | | PS_MIO23_501 | PSS IO | | | | | | | | | | | | | +| D12 | | | VCCO_MIO1_501 | VCCO | | | | | | | any** | | | | | | +| D13 | | | PS_MIO27_501 | PSS IO | | | | | | | | | | | | | +| D14 | | | PS_MIO40_501 | PSS IO | | | | | | | | | | | | | +| D15 | | | PS_MIO33_501 | PSS IO | | | | | | | | | | | | | +| D16 | | | PS_MIO46_501 | PSS IO | | | | | | | | | | | | | +| D17 | | | GND | GND | | | | | | | 0.0 | | | | | | +| D18 | | High Range | IO_L3N_T0_DQS_AD1N_35 | User IO | | 35 | | | | | | | | | | | +| D19 | | High Range | IO_L4P_T0_35 | User IO | | 35 | | | | | | | | | | | +| D20 | | High Range | IO_L4N_T0_35 | User IO | | 35 | | | | | | | | | | | +| E1 | | | PS_DDR_DQ7_502 | PSS IO | | | | | | | | | | | | | +| E2 | | | PS_DDR_DQ8_502 | PSS IO | | | | | | | | | | | | | +| E3 | | | PS_DDR_DQ9_502 | PSS IO | | | | | | | | | | | | | +| E4 | | | PS_DDR_A12_502 | PSS IO | | | | | | | | | | | | | +| E5 | | | VCCO_DDR_502 | VCCO | | | | | | | any** | | | | | | +| E6 | | | PS_MIO0_500 | PSS IO | | | | | | | | | | | | | +| E7 | | | PS_CLK_500 | PSS Clock | | | | | | | | | | | | | +| E8 | | | PS_MIO13_500 | PSS IO | | | | | | | | | | | | | +| E9 | | | PS_MIO10_500 | PSS IO | | | | | | | | | | | | | +| E10 | | | GND | GND | | | | | | | 0.0 | | | | | | +| E11 | | | PS_MIO_VREF_501 | PSS IO | | | | | | | | | | | | | +| E12 | | | PS_MIO42_501 | PSS IO | | | | | | | | | | | | | +| E13 | | | PS_MIO38_501 | PSS IO | | | | | | | | | | | | | +| E14 | | | PS_MIO17_501 | PSS IO | | | | | | | | | | | | | +| E15 | | | VCCO_MIO1_501 | VCCO | | | | | | | any** | | | | | | +| E16 | | | PS_MIO31_501 | PSS IO | | | | | | | | | | | | | +| E17 | | High Range | IO_L3P_T0_DQS_AD1P_35 | User IO | | 35 | | | | | | | | | | | +| E18 | | High Range | IO_L5P_T0_AD9P_35 | User IO | | 35 | | | | | | | | | | | +| E19 | | High Range | IO_L5N_T0_AD9N_35 | User IO | | 35 | | | | | | | | | | | +| E20 | | | GND | GND | | | | | | | 0.0 | | | | | | +| F1 | | | PS_DDR_DM1_502 | PSS IO | | | | | | | | | | | | | +| F2 | | | PS_DDR_DQS_N1_502 | PSS IO | | | | | | | | | | | | | +| F3 | | | GND | GND | | | | | | | 0.0 | | | | | | +| F4 | | | PS_DDR_A14_502 | PSS IO | | | | | | | | | | | | | +| F5 | | | PS_DDR_A10_502 | PSS IO | | | | | | | | | | | | | +| F6 | | Dedicated | TDO_0 | Config | | 0 | | | | | | | | | | | +| F7 | | | GND | GND | | | | | | | 0.0 | | | | | | +| F8 | | | VCCPAUX | PSS VCCAUX | | | | | | | | | | | | | +| F9 | | Dedicated | TCK_0 | Config | | 0 | | | | | | | | | | | +| F10 | | | RSVDGND | GND | | | | | | | | | | | | | +| F11 | | Dedicated | VCCBATT_0 | Config | | 0 | | | | | | | | | | | +| F12 | | | PS_MIO35_501 | PSS IO | | | | | | | | | | | | | +| F13 | | | PS_MIO44_501 | PSS IO | | | | | | | | | | | | | +| F14 | | | PS_MIO21_501 | PSS IO | | | | | | | | | | | | | +| F15 | | | PS_MIO25_501 | PSS IO | | | | | | | | | | | | | +| F16 | | High Range | IO_L6P_T0_35 | User IO | | 35 | | | | | | | | | | | +| F17 | | High Range | IO_L6N_T0_VREF_35 | User IO | | 35 | | | | | | | | | | | +| F18 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | +| F19 | | High Range | IO_L15P_T2_DQS_AD12P_35 | User IO | | 35 | | | | | | | | | | | +| F20 | | High Range | IO_L15N_T2_DQS_AD12N_35 | User IO | | 35 | | | | | | | | | | | +| G1 | | | VCCO_DDR_502 | VCCO | | | | | | | any** | | | | | | +| G2 | | | PS_DDR_DQS_P1_502 | PSS IO | | | | | | | | | | | | | +| G3 | | | PS_DDR_DQ10_502 | PSS IO | | | | | | | | | | | | | +| G4 | | | PS_DDR_A11_502 | PSS IO | | | | | | | | | | | | | +| G5 | | | PS_DDR_VRN_502 | PSS IO | | | | | | | | | | | | | +| G6 | | Dedicated | TDI_0 | Config | | 0 | | | | | | | | | | | +| G7 | | | VCCPINT | PSS VCCINT | | | | | | | | | | | | | +| G8 | | | VCCPLL | PSS VCCPLL | | | | | | | | | | | | | +| G9 | | | VCCPAUX | PSS VCCAUX | | | | | | | | | | | | | +| G10 | | | GND | GND | | | | | | | 0.0 | | | | | | +| G11 | | | VCCBRAM | VCCBRAM | | | | | | | | | | | | | +| G12 | | | GND | GND | | | | | | | 0.0 | | | | | | +| G13 | | | VCCINT | VCCINT | | | | | | | | | | | | | +| G14 | | High Range | IO_0_35 | User IO | | 35 | | | | | | | | | | | +| G15 | sw[0] | High Range | IO_L19N_T3_VREF_35 | INPUT | LVCMOS33 | 35 | | | | NONE | | FIXED | | | | NONE | +| G16 | | | GND | GND | | | | | | | 0.0 | | | | | | +| G17 | | High Range | IO_L16P_T2_35 | User IO | | 35 | | | | | | | | | | | +| G18 | | High Range | IO_L16N_T2_35 | User IO | | 35 | | | | | | | | | | | +| G19 | | High Range | IO_L18P_T2_AD13P_35 | User IO | | 35 | | | | | | | | | | | +| G20 | | High Range | IO_L18N_T2_AD13N_35 | User IO | | 35 | | | | | | | | | | | +| H1 | | | PS_DDR_DQ14_502 | PSS IO | | | | | | | | | | | | | +| H2 | | | PS_DDR_DQ13_502 | PSS IO | | | | | | | | | | | | | +| H3 | | | PS_DDR_DQ11_502 | PSS IO | | | | | | | | | | | | | +| H4 | | | VCCO_DDR_502 | VCCO | | | | | | | any** | | | | | | +| H5 | | | PS_DDR_VRP_502 | PSS IO | | | | | | | | | | | | | +| H6 | | | PS_DDR_VREF0_502 | PSS IO | | | | | | | | | | | | | +| H7 | | | GND | GND | | | | | | | 0.0 | | | | | | +| H8 | | | VCCPAUX | PSS VCCAUX | | | | | | | | | | | | | +| H9 | | | GND | GND | | | | | | | 0.0 | | | | | | +| H10 | | | VCCBRAM | VCCBRAM | | | | | | | | | | | | | +| H11 | | | GND | GND | | | | | | | 0.0 | | | | | | +| H12 | | | VCCINT | VCCINT | | | | | | | | | | | | | +| H13 | | | GND | GND | | | | | | | 0.0 | | | | | | +| H14 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | +| H15 | je[3] | High Range | IO_L19P_T3_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| H16 | | High Range | IO_L13P_T2_MRCC_35 | User IO | | 35 | | | | | | | | | | | +| H17 | | High Range | IO_L13N_T2_MRCC_35 | User IO | | 35 | | | | | | | | | | | +| H18 | | High Range | IO_L14N_T2_AD4N_SRCC_35 | User IO | | 35 | | | | | | | | | | | +| H19 | | | GND | GND | | | | | | | 0.0 | | | | | | +| H20 | | High Range | IO_L17N_T2_AD5N_35 | User IO | | 35 | | | | | | | | | | | +| J1 | | | PS_DDR_DQ15_502 | PSS IO | | | | | | | | | | | | | +| J2 | | | GND | GND | | | | | | | 0.0 | | | | | | +| J3 | | | PS_DDR_DQ12_502 | PSS IO | | | | | | | | | | | | | +| J4 | | | PS_DDR_A9_502 | PSS IO | | | | | | | | | | | | | +| J5 | | | PS_DDR_BA2_502 | PSS IO | | | | | | | | | | | | | +| J6 | | Dedicated | TMS_0 | Config | | 0 | | | | | | | | | | | +| J7 | | | VCCPINT | PSS VCCINT | | | | | | | | | | | | | +| J8 | | | GND | GND | | | | | | | 0.0 | | | | | | +| J9 | | Dedicated | VCCADC_0 | XADC | | 0 | | | | | | | | | | | +| J10 | | Dedicated | GNDADC_0 | XADC | | 0 | | | | | | | | | | | +| J11 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | +| J12 | | | GND | GND | | | | | | | 0.0 | | | | | | +| J13 | | | VCCINT | VCCINT | | | | | | | | | | | | | +| J14 | | High Range | IO_L20N_T3_AD6N_35 | User IO | | 35 | | | | | | | | | | | +| J15 | je[2] | High Range | IO_25_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| J16 | | High Range | IO_L24N_T3_AD15N_35 | User IO | | 35 | | | | | | | | | | | +| J17 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | +| J18 | | High Range | IO_L14P_T2_AD4P_SRCC_35 | User IO | | 35 | | | | | | | | | | | +| J19 | | High Range | IO_L10N_T1_AD11N_35 | User IO | | 35 | | | | | | | | | | | +| J20 | | High Range | IO_L17P_T2_AD5P_35 | User IO | | 35 | | | | | | | | | | | +| K1 | | | PS_DDR_A8_502 | PSS IO | | | | | | | | | | | | | +| K2 | | | PS_DDR_A1_502 | PSS IO | | | | | | | | | | | | | +| K3 | | | PS_DDR_A3_502 | PSS IO | | | | | | | | | | | | | +| K4 | | | PS_DDR_A7_502 | PSS IO | | | | | | | | | | | | | +| K5 | | | GND | GND | | | | | | | 0.0 | | | | | | +| K6 | | Dedicated | VCCO_0 | VCCO | | 0 | | | | | any** | | | | | | +| K7 | | | GND | GND | | | | | | | 0.0 | | | | | | +| K8 | | | VCCPAUX | PSS VCCAUX | | | | | | | | | | | | | +| K9 | | Dedicated | VP_0 | XADC | | 0 | | | | | | | | | | | +| K10 | | Dedicated | VREFN_0 | XADC | | 0 | | | | | | | | | | | +| K11 | | | GND | GND | | | | | | | 0.0 | | | | | | +| K12 | | | VCCINT | VCCINT | | | | | | | | | | | | | +| K13 | | | GND | GND | | | | | | | 0.0 | | | | | | +| K14 | | High Range | IO_L20P_T3_AD6P_35 | User IO | | 35 | | | | | | | | | | | +| K15 | | | GND | GND | | | | | | | 0.0 | | | | | | +| K16 | | High Range | IO_L24P_T3_AD15P_35 | User IO | | 35 | | | | | | | | | | | +| K17 | | High Range | IO_L12P_T1_MRCC_35 | User IO | | 35 | | | | | | | | | | | +| K18 | | High Range | IO_L12N_T1_MRCC_35 | User IO | | 35 | | | | | | | | | | | +| K19 | | High Range | IO_L10P_T1_AD11P_35 | User IO | | 35 | | | | | | | | | | | +| K20 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | +| L1 | | | PS_DDR_A5_502 | PSS IO | | | | | | | | | | | | | +| L2 | | | PS_DDR_CKP_502 | PSS IO | | | | | | | | | | | | | +| L3 | | | VCCO_DDR_502 | VCCO | | | | | | | any** | | | | | | +| L4 | | | PS_DDR_A6_502 | PSS IO | | | | | | | | | | | | | +| L5 | | | PS_DDR_BA0_502 | PSS IO | | | | | | | | | | | | | +| L6 | | Dedicated | PROGRAM_B_0 | Config | | 0 | | | | | | | | | | | +| L7 | | | VCCPINT | PSS VCCINT | | | | | | | | | | | | | +| L8 | | | GND | GND | | | | | | | 0.0 | | | | | | +| L9 | | Dedicated | VREFP_0 | XADC | | 0 | | | | | | | | | | | +| L10 | | Dedicated | VN_0 | XADC | | 0 | | | | | | | | | | | +| L11 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | +| L12 | | | GND | GND | | | | | | | 0.0 | | | | | | +| L13 | | | VCCINT | VCCINT | | | | | | | | | | | | | +| L14 | | High Range | IO_L22P_T3_AD7P_35 | User IO | | 35 | | | | | | | | | | | +| L15 | | High Range | IO_L22N_T3_AD7N_35 | User IO | | 35 | | | | | | | | | | | +| L16 | clk | High Range | IO_L11P_T1_SRCC_35 | INPUT | LVCMOS33 | 35 | | | | NONE | | FIXED | | | | NONE | +| L17 | | High Range | IO_L11N_T1_SRCC_35 | User IO | | 35 | | | | | | | | | | | +| L18 | | | GND | GND | | | | | | | 0.0 | | | | | | +| L19 | | High Range | IO_L9P_T1_DQS_AD3P_35 | User IO | | 35 | | | | | | | | | | | +| L20 | | High Range | IO_L9N_T1_DQS_AD3N_35 | User IO | | 35 | | | | | | | | | | | +| M1 | | | GND | GND | | | | | | | 0.0 | | | | | | +| M2 | | | PS_DDR_CKN_502 | PSS IO | | | | | | | | | | | | | +| M3 | | | PS_DDR_A2_502 | PSS IO | | | | | | | | | | | | | +| M4 | | | PS_DDR_A4_502 | PSS IO | | | | | | | | | | | | | +| M5 | | | PS_DDR_WE_B_502 | PSS IO | | | | | | | | | | | | | +| M6 | | Dedicated | CFGBVS_0 | Config | | 0 | | | | | | | | | | | +| M7 | | | GND | GND | | | | | | | 0.0 | | | | | | +| M8 | | | VCCPAUX | PSS VCCAUX | | | | | | | | | | | | | +| M9 | | Dedicated | DXP_0 | Temp Sensor | | 0 | | | | | | | | | | | +| M10 | | Dedicated | DXN_0 | Temp Sensor | | 0 | | | | | | | | | | | +| M11 | | | GND | GND | | | | | | | 0.0 | | | | | | +| M12 | | | VCCINT | VCCINT | | | | | | | | | | | | | +| M13 | | | GND | GND | | | | | | | 0.0 | | | | | | +| M14 | | High Range | IO_L23P_T3_35 | User IO | | 35 | | | | | | | | | | | +| M15 | | High Range | IO_L23N_T3_35 | User IO | | 35 | | | | | | | | | | | +| M16 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | +| M17 | | High Range | IO_L8P_T1_AD10P_35 | User IO | | 35 | | | | | | | | | | | +| M18 | | High Range | IO_L8N_T1_AD10N_35 | User IO | | 35 | | | | | | | | | | | +| M19 | | High Range | IO_L7P_T1_AD2P_35 | User IO | | 35 | | | | | | | | | | | +| M20 | | High Range | IO_L7N_T1_AD2N_35 | User IO | | 35 | | | | | | | | | | | +| N1 | | | PS_DDR_CS_B_502 | PSS IO | | | | | | | | | | | | | +| N2 | | | PS_DDR_A0_502 | PSS IO | | | | | | | | | | | | | +| N3 | | | PS_DDR_CKE_502 | PSS IO | | | | | | | | | | | | | +| N4 | | | GND | GND | | | | | | | 0.0 | | | | | | +| N5 | | | PS_DDR_ODT_502 | PSS IO | | | | | | | | | | | | | +| N6 | | | RSVDVCC3 | Reserved | | | | | | | | | | | | | +| N7 | | | VCCPINT | PSS VCCINT | | | | | | | | | | | | | +| N8 | | | GND | GND | | | | | | | 0.0 | | | | | | +| N9 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | +| N10 | | | GND | GND | | | | | | | 0.0 | | | | | | +| N11 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | +| N12 | | | GND | GND | | | | | | | 0.0 | | | | | | +| N13 | | | VCCINT | VCCINT | | | | | | | | | | | | | +| N14 | | | GND | GND | | | | | | | 0.0 | | | | | | +| N15 | | High Range | IO_L21P_T3_DQS_AD14P_35 | User IO | | 35 | | | | | | | | | | | +| N16 | | High Range | IO_L21N_T3_DQS_AD14N_35 | User IO | | 35 | | | | | | | | | | | +| N17 | | High Range | IO_L23P_T3_34 | User IO | | 34 | | | | | | | | | | | +| N18 | | High Range | IO_L13P_T2_MRCC_34 | User IO | | 34 | | | | | | | | | | | +| N19 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | +| N20 | | High Range | IO_L14P_T2_SRCC_34 | User IO | | 34 | | | | | | | | | | | +| P1 | | | PS_DDR_DQ16_502 | PSS IO | | | | | | | | | | | | | +| P2 | | | VCCO_DDR_502 | VCCO | | | | | | | any** | | | | | | +| P3 | | | PS_DDR_DQ17_502 | PSS IO | | | | | | | | | | | | | +| P4 | | | PS_DDR_RAS_B_502 | PSS IO | | | | | | | | | | | | | +| P5 | | | PS_DDR_CAS_B_502 | PSS IO | | | | | | | | | | | | | +| P6 | | | PS_DDR_VREF1_502 | PSS IO | | | | | | | | | | | | | +| P7 | | | GND | GND | | | | | | | 0.0 | | | | | | +| P8 | | | VCCPINT | PSS VCCINT | | | | | | | | | | | | | +| P9 | | | GND | GND | | | | | | | 0.0 | | | | | | +| P10 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | +| P11 | | | GND | GND | | | | | | | 0.0 | | | | | | +| P12 | | | VCCINT | VCCINT | | | | | | | | | | | | | +| P13 | | | GND | GND | | | | | | | 0.0 | | | | | | +| P14 | | High Range | IO_L6P_T0_34 | User IO | | 34 | | | | | | | | | | | +| P15 | sw[1] | High Range | IO_L24P_T3_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | +| P16 | | High Range | IO_L24N_T3_34 | User IO | | 34 | | | | | | | | | | | +| P17 | | | GND | GND | | | | | | | 0.0 | | | | | | +| P18 | | High Range | IO_L23N_T3_34 | User IO | | 34 | | | | | | | | | | | +| P19 | | High Range | IO_L13N_T2_MRCC_34 | User IO | | 34 | | | | | | | | | | | +| P20 | | High Range | IO_L14N_T2_SRCC_34 | User IO | | 34 | | | | | | | | | | | +| R1 | | | PS_DDR_DQ19_502 | PSS IO | | | | | | | | | | | | | +| R2 | | | PS_DDR_DQS_P2_502 | PSS IO | | | | | | | | | | | | | +| R3 | | | PS_DDR_DQ18_502 | PSS IO | | | | | | | | | | | | | +| R4 | | | PS_DDR_BA1_502 | PSS IO | | | | | | | | | | | | | +| R5 | | | VCCO_DDR_502 | VCCO | | | | | | | any** | | | | | | +| R6 | | | RSVDVCC2 | Reserved | | | | | | | | | | | | | +| R7 | | | VCCPINT | PSS VCCINT | | | | | | | | | | | | | +| R8 | | | GND | GND | | | | | | | 0.0 | | | | | | +| R9 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | +| R10 | | Dedicated | INIT_B_0 | Config | | 0 | | | | | | | | | | | +| R11 | | Dedicated | DONE_0 | Config | | 0 | | | | | | | | | | | +| R12 | | | GND | GND | | | | | | | 0.0 | | | | | | +| R13 | | | VCCINT | VCCINT | | | | | | | | | | | | | +| R14 | | High Range | IO_L6N_T0_VREF_34 | User IO | | 34 | | | | | | | | | | | +| R15 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | +| R16 | | High Range | IO_L19P_T3_34 | User IO | | 34 | | | | | | | | | | | +| R17 | | High Range | IO_L19N_T3_VREF_34 | User IO | | 34 | | | | | | | | | | | +| R18 | btn | High Range | IO_L20N_T3_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | +| R19 | | High Range | IO_0_34 | User IO | | 34 | | | | | | | | | | | +| R20 | | | GND | GND | | | | | | | 0.0 | | | | | | +| T1 | | | PS_DDR_DM2_502 | PSS IO | | | | | | | | | | | | | +| T2 | | | PS_DDR_DQS_N2_502 | PSS IO | | | | | | | | | | | | | +| T3 | | | GND | GND | | | | | | | 0.0 | | | | | | +| T4 | | | PS_DDR_DQ20_502 | PSS IO | | | | | | | | | | | | | +| T5 | | | NC | Not Connected | | | | | | | | | | | | | +| T6 | | | RSVDVCC1 | Reserved | | | | | | | | | | | | | +| T7 | | | GND | GND | | | | | | | 0.0 | | | | | | +| T8 | | Dedicated | VCCO_13 | VCCO | | 13 | | | | | any** | | | | | | +| T9 | | | NC | Not Connected | | | | | | | | | | | | | +| T10 | | High Range | IO_L1N_T0_34 | User IO | | 34 | | | | | | | | | | | +| T11 | | High Range | IO_L1P_T0_34 | User IO | | 34 | | | | | | | | | | | +| T12 | | High Range | IO_L2P_T0_34 | User IO | | 34 | | | | | | | | | | | +| T13 | | | GND | GND | | | | | | | 0.0 | | | | | | +| T14 | | High Range | IO_L5P_T0_34 | User IO | | 34 | | | | | | | | | | | +| T15 | | High Range | IO_L5N_T0_34 | User IO | | 34 | | | | | | | | | | | +| T16 | | High Range | IO_L9P_T1_DQS_34 | User IO | | 34 | | | | | | | | | | | +| T17 | je[6] | High Range | IO_L20P_T3_34 | OUTPUT | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| T18 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | +| T19 | | High Range | IO_25_34 | User IO | | 34 | | | | | | | | | | | +| T20 | | High Range | IO_L15P_T2_DQS_34 | User IO | | 34 | | | | | | | | | | | +| U1 | | | VCCO_DDR_502 | VCCO | | | | | | | any** | | | | | | +| U2 | | | PS_DDR_DQ22_502 | PSS IO | | | | | | | | | | | | | +| U3 | | | PS_DDR_DQ23_502 | PSS IO | | | | | | | | | | | | | +| U4 | | | PS_DDR_DQ21_502 | PSS IO | | | | | | | | | | | | | +| U5 | | | NC | Not Connected | | | | | | | | | | | | | +| U6 | | | GND | GND | | | | | | | 0.0 | | | | | | +| U7 | | | NC | Not Connected | | | | | | | | | | | | | +| U8 | | | NC | Not Connected | | | | | | | | | | | | | +| U9 | | | NC | Not Connected | | | | | | | | | | | | | +| U10 | | | NC | Not Connected | | | | | | | | | | | | | +| U11 | | Dedicated | VCCO_13 | VCCO | | 13 | | | | | any** | | | | | | +| U12 | | High Range | IO_L2N_T0_34 | User IO | | 34 | | | | | | | | | | | +| U13 | | High Range | IO_L3P_T0_DQS_PUDC_B_34 | User IO | | 34 | | | | | | | | | | | +| U14 | | High Range | IO_L11P_T1_SRCC_34 | User IO | | 34 | | | | | | | | | | | +| U15 | | High Range | IO_L11N_T1_SRCC_34 | User IO | | 34 | | | | | | | | | | | +| U16 | | | GND | GND | | | | | | | 0.0 | | | | | | +| U17 | je[5] | High Range | IO_L9N_T1_DQS_34 | OUTPUT | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| U18 | | High Range | IO_L12P_T1_MRCC_34 | User IO | | 34 | | | | | | | | | | | +| U19 | | High Range | IO_L12N_T1_MRCC_34 | User IO | | 34 | | | | | | | | | | | +| U20 | | High Range | IO_L15N_T2_DQS_34 | User IO | | 34 | | | | | | | | | | | +| V1 | | | PS_DDR_DQ24_502 | PSS IO | | | | | | | | | | | | | +| V2 | | | PS_DDR_DQ30_502 | PSS IO | | | | | | | | | | | | | +| V3 | | | PS_DDR_DQ31_502 | PSS IO | | | | | | | | | | | | | +| V4 | | | VCCO_DDR_502 | VCCO | | | | | | | any** | | | | | | +| V5 | | | NC | Not Connected | | | | | | | | | | | | | +| V6 | | | NC | Not Connected | | | | | | | | | | | | | +| V7 | | | NC | Not Connected | | | | | | | | | | | | | +| V8 | | | NC | Not Connected | | | | | | | | | | | | | +| V9 | | | GND | GND | | | | | | | 0.0 | | | | | | +| V10 | | | NC | Not Connected | | | | | | | | | | | | | +| V11 | | | NC | Not Connected | | | | | | | | | | | | | +| V12 | je[0] | High Range | IO_L4P_T0_34 | OUTPUT | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| V13 | je[4] | High Range | IO_L3N_T0_DQS_34 | OUTPUT | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| V14 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | +| V15 | | High Range | IO_L10P_T1_34 | User IO | | 34 | | | | | | | | | | | +| V16 | | High Range | IO_L18P_T2_34 | User IO | | 34 | | | | | | | | | | | +| V17 | | High Range | IO_L21P_T3_DQS_34 | User IO | | 34 | | | | | | | | | | | +| V18 | | High Range | IO_L21N_T3_DQS_34 | User IO | | 34 | | | | | | | | | | | +| V19 | | | GND | GND | | | | | | | 0.0 | | | | | | +| V20 | | High Range | IO_L16P_T2_34 | User IO | | 34 | | | | | | | | | | | +| W1 | | | PS_DDR_DQ26_502 | PSS IO | | | | | | | | | | | | | +| W2 | | | GND | GND | | | | | | | 0.0 | | | | | | +| W3 | | | PS_DDR_DQ29_502 | PSS IO | | | | | | | | | | | | | +| W4 | | | PS_DDR_DQS_N3_502 | PSS IO | | | | | | | | | | | | | +| W5 | | | PS_DDR_DQS_P3_502 | PSS IO | | | | | | | | | | | | | +| W6 | | | NC | Not Connected | | | | | | | | | | | | | +| W7 | | Dedicated | VCCO_13 | VCCO | | 13 | | | | | any** | | | | | | +| W8 | | | NC | Not Connected | | | | | | | | | | | | | +| W9 | | | NC | Not Connected | | | | | | | | | | | | | +| W10 | | | NC | Not Connected | | | | | | | | | | | | | +| W11 | | | NC | Not Connected | | | | | | | | | | | | | +| W12 | | | GND | GND | | | | | | | 0.0 | | | | | | +| W13 | | High Range | IO_L4N_T0_34 | User IO | | 34 | | | | | | | | | | | +| W14 | | High Range | IO_L8P_T1_34 | User IO | | 34 | | | | | | | | | | | +| W15 | | High Range | IO_L10N_T1_34 | User IO | | 34 | | | | | | | | | | | +| W16 | je[1] | High Range | IO_L18N_T2_34 | OUTPUT | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| W17 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | +| W18 | | High Range | IO_L22P_T3_34 | User IO | | 34 | | | | | | | | | | | +| W19 | | High Range | IO_L22N_T3_34 | User IO | | 34 | | | | | | | | | | | +| W20 | | High Range | IO_L16N_T2_34 | User IO | | 34 | | | | | | | | | | | +| Y1 | | | PS_DDR_DM3_502 | PSS IO | | | | | | | | | | | | | +| Y2 | | | PS_DDR_DQ28_502 | PSS IO | | | | | | | | | | | | | +| Y3 | | | PS_DDR_DQ25_502 | PSS IO | | | | | | | | | | | | | +| Y4 | | | PS_DDR_DQ27_502 | PSS IO | | | | | | | | | | | | | +| Y5 | | | GND | GND | | | | | | | 0.0 | | | | | | +| Y6 | | | NC | Not Connected | | | | | | | | | | | | | +| Y7 | | | NC | Not Connected | | | | | | | | | | | | | +| Y8 | | | NC | Not Connected | | | | | | | | | | | | | +| Y9 | | | NC | Not Connected | | | | | | | | | | | | | +| Y10 | | Dedicated | VCCO_13 | VCCO | | 13 | | | | | any** | | | | | | +| Y11 | | | NC | Not Connected | | | | | | | | | | | | | +| Y12 | | | NC | Not Connected | | | | | | | | | | | | | +| Y13 | | | NC | Not Connected | | | | | | | | | | | | | +| Y14 | | High Range | IO_L8N_T1_34 | User IO | | 34 | | | | | | | | | | | +| Y15 | | | GND | GND | | | | | | | 0.0 | | | | | | +| Y16 | | High Range | IO_L7P_T1_34 | User IO | | 34 | | | | | | | | | | | +| Y17 | je[7] | High Range | IO_L7N_T1_34 | OUTPUT | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| Y18 | | High Range | IO_L17P_T2_34 | User IO | | 34 | | | | | | | | | | | +| Y19 | | High Range | IO_L17N_T2_34 | User IO | | 34 | | | | | | | | | | | +| Y20 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | ++------------+-------------+------------+-------------------------+---------------+-------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+------+------------------+ +* Default value +** Special VCCO requirements may apply. Please consult the device family datasheet for specific guideline on VCCO requirements. + + diff --git a/sim/sim.runs/impl_1/midpoint_methodology_drc_routed.rpt b/sim/sim.runs/impl_1/midpoint_methodology_drc_routed.rpt new file mode 100644 index 0000000..1f74b5a --- /dev/null +++ b/sim/sim.runs/impl_1/midpoint_methodology_drc_routed.rpt @@ -0,0 +1,175 @@ +Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. +----------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2017.2 (lin64) Build 1909853 Thu Jun 15 18:39:10 MDT 2017 +| Date : Wed Oct 25 21:40:49 2017 +| Host : Kreyshawn running 64-bit Ubuntu 14.04.5 LTS +| Command : report_methodology -file midpoint_methodology_drc_routed.rpt -rpx midpoint_methodology_drc_routed.rpx +| Design : midpoint +| Device : xc7z010clg400-1 +| Speed File : -1 +| Design State : Routed +----------------------------------------------------------------------------------------------------------------------- + +Report Methodology + +Table of Contents +----------------- +1. REPORT SUMMARY +2. REPORT DETAILS + +1. REPORT SUMMARY +----------------- + Netlist: netlist + Floorplan: design_1 + Design limits: + Max violations: + Violations found: 28 ++-----------+----------+-----------------------------+------------+ +| Rule | Severity | Description | Violations | ++-----------+----------+-----------------------------+------------+ +| TIMING-17 | Warning | Non-clocked sequential cell | 28 | ++-----------+----------+-----------------------------+------------+ + +2. REPORT DETAILS +----------------- +TIMING-17#1 Warning +Non-clocked sequential cell +The clock pin i1/conditioned_reg/C is not reached by a timing clock +Related violations: + +TIMING-17#2 Warning +Non-clocked sequential cell +The clock pin i1/negativeedge_reg/C is not reached by a timing clock +Related violations: + +TIMING-17#3 Warning +Non-clocked sequential cell +The clock pin i1/prev_vals_reg[0]/C is not reached by a timing clock +Related violations: + +TIMING-17#4 Warning +Non-clocked sequential cell +The clock pin i1/prev_vals_reg[1]/C is not reached by a timing clock +Related violations: + +TIMING-17#5 Warning +Non-clocked sequential cell +The clock pin i1/prev_vals_reg[2]/C is not reached by a timing clock +Related violations: + +TIMING-17#6 Warning +Non-clocked sequential cell +The clock pin i2/conditioned_reg/C is not reached by a timing clock +Related violations: + +TIMING-17#7 Warning +Non-clocked sequential cell +The clock pin i2/prev_vals_reg[0]/C is not reached by a timing clock +Related violations: + +TIMING-17#8 Warning +Non-clocked sequential cell +The clock pin i2/prev_vals_reg[1]/C is not reached by a timing clock +Related violations: + +TIMING-17#9 Warning +Non-clocked sequential cell +The clock pin i2/prev_vals_reg[2]/C is not reached by a timing clock +Related violations: + +TIMING-17#10 Warning +Non-clocked sequential cell +The clock pin i3/conditioned_reg/C is not reached by a timing clock +Related violations: + +TIMING-17#11 Warning +Non-clocked sequential cell +The clock pin i3/positiveedge_reg/C is not reached by a timing clock +Related violations: + +TIMING-17#12 Warning +Non-clocked sequential cell +The clock pin i3/prev_vals_reg[0]/C is not reached by a timing clock +Related violations: + +TIMING-17#13 Warning +Non-clocked sequential cell +The clock pin i3/prev_vals_reg[1]/C is not reached by a timing clock +Related violations: + +TIMING-17#14 Warning +Non-clocked sequential cell +The clock pin i3/prev_vals_reg[2]/C is not reached by a timing clock +Related violations: + +TIMING-17#15 Warning +Non-clocked sequential cell +The clock pin shft/data_reg[0]/C is not reached by a timing clock +Related violations: + +TIMING-17#16 Warning +Non-clocked sequential cell +The clock pin shft/data_reg[1]/C is not reached by a timing clock +Related violations: + +TIMING-17#17 Warning +Non-clocked sequential cell +The clock pin shft/data_reg[1]_lopt_replica/C is not reached by a timing clock +Related violations: + +TIMING-17#18 Warning +Non-clocked sequential cell +The clock pin shft/data_reg[2]/C is not reached by a timing clock +Related violations: + +TIMING-17#19 Warning +Non-clocked sequential cell +The clock pin shft/data_reg[2]_lopt_replica/C is not reached by a timing clock +Related violations: + +TIMING-17#20 Warning +Non-clocked sequential cell +The clock pin shft/data_reg[3]/C is not reached by a timing clock +Related violations: + +TIMING-17#21 Warning +Non-clocked sequential cell +The clock pin shft/data_reg[3]_lopt_replica/C is not reached by a timing clock +Related violations: + +TIMING-17#22 Warning +Non-clocked sequential cell +The clock pin shft/data_reg[4]/C is not reached by a timing clock +Related violations: + +TIMING-17#23 Warning +Non-clocked sequential cell +The clock pin shft/data_reg[4]_lopt_replica/C is not reached by a timing clock +Related violations: + +TIMING-17#24 Warning +Non-clocked sequential cell +The clock pin shft/data_reg[5]/C is not reached by a timing clock +Related violations: + +TIMING-17#25 Warning +Non-clocked sequential cell +The clock pin shft/data_reg[5]_lopt_replica/C is not reached by a timing clock +Related violations: + +TIMING-17#26 Warning +Non-clocked sequential cell +The clock pin shft/data_reg[6]/C is not reached by a timing clock +Related violations: + +TIMING-17#27 Warning +Non-clocked sequential cell +The clock pin shft/data_reg[6]_lopt_replica/C is not reached by a timing clock +Related violations: + +TIMING-17#28 Warning +Non-clocked sequential cell +The clock pin shft/data_reg[7]/C is not reached by a timing clock +Related violations: + + diff --git a/sim/sim.runs/impl_1/midpoint_methodology_drc_routed.rpx b/sim/sim.runs/impl_1/midpoint_methodology_drc_routed.rpx new file mode 100644 index 0000000..f9f35f7 Binary files /dev/null and b/sim/sim.runs/impl_1/midpoint_methodology_drc_routed.rpx differ diff --git a/sim/sim.runs/impl_1/midpoint_opt.dcp b/sim/sim.runs/impl_1/midpoint_opt.dcp new file mode 100644 index 0000000..c369fdf Binary files /dev/null and b/sim/sim.runs/impl_1/midpoint_opt.dcp differ diff --git a/sim/sim.runs/impl_1/midpoint_placed.dcp b/sim/sim.runs/impl_1/midpoint_placed.dcp new file mode 100644 index 0000000..6bc6e22 Binary files /dev/null and b/sim/sim.runs/impl_1/midpoint_placed.dcp differ diff --git a/sim/sim.runs/impl_1/midpoint_power_routed.rpt b/sim/sim.runs/impl_1/midpoint_power_routed.rpt new file mode 100644 index 0000000..d6822bd --- /dev/null +++ b/sim/sim.runs/impl_1/midpoint_power_routed.rpt @@ -0,0 +1,151 @@ +Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. +---------------------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2017.2 (lin64) Build 1909853 Thu Jun 15 18:39:10 MDT 2017 +| Date : Wed Oct 25 21:40:49 2017 +| Host : Kreyshawn running 64-bit Ubuntu 14.04.5 LTS +| Command : report_power -file midpoint_power_routed.rpt -pb midpoint_power_summary_routed.pb -rpx midpoint_power_routed.rpx +| Design : midpoint +| Device : xc7z010clg400-1 +| Design State : routed +| Grade : commercial +| Process : typical +| Characterization : Production +---------------------------------------------------------------------------------------------------------------------------------------------- + +Power Report + +Table of Contents +----------------- +1. Summary +1.1 On-Chip Components +1.2 Power Supply Summary +1.3 Confidence Level +2. Settings +2.1 Environment +2.2 Clock Constraints +3. Detailed Reports +3.1 By Hierarchy + +1. Summary +---------- + ++--------------------------+-------+ +| Total On-Chip Power (W) | 1.202 | +| Dynamic (W) | 1.087 | +| Device Static (W) | 0.115 | +| Effective TJA (C/W) | 11.5 | +| Max Ambient (C) | 71.1 | +| Junction Temperature (C) | 38.9 | +| Confidence Level | Low | +| Setting File | --- | +| Simulation Activity File | --- | +| Design Nets Matched | NA | ++--------------------------+-------+ + + +1.1 On-Chip Components +---------------------- + ++----------------+-----------+----------+-----------+-----------------+ +| On-Chip | Power (W) | Used | Available | Utilization (%) | ++----------------+-----------+----------+-----------+-----------------+ +| Slice Logic | 0.019 | 44 | --- | --- | +| LUT as Logic | 0.010 | 5 | 17600 | 0.03 | +| BUFG | 0.006 | 1 | 32 | 3.13 | +| Register | 0.004 | 28 | 35200 | 0.08 | +| Others | 0.000 | 8 | --- | --- | +| Signals | 0.049 | 34 | --- | --- | +| I/O | 1.019 | 12 | 100 | 12.00 | +| Static Power | 0.115 | | | | +| Total | 1.202 | | | | ++----------------+-----------+----------+-----------+-----------------+ + + +1.2 Power Supply Summary +------------------------ + ++-----------+-------------+-----------+-------------+------------+ +| Source | Voltage (V) | Total (A) | Dynamic (A) | Static (A) | ++-----------+-------------+-----------+-------------+------------+ +| Vccint | 1.000 | 0.090 | 0.084 | 0.006 | +| Vccaux | 1.800 | 0.048 | 0.037 | 0.011 | +| Vcco33 | 3.300 | 0.285 | 0.284 | 0.001 | +| Vcco25 | 2.500 | 0.000 | 0.000 | 0.000 | +| Vcco18 | 1.800 | 0.000 | 0.000 | 0.000 | +| Vcco15 | 1.500 | 0.000 | 0.000 | 0.000 | +| Vcco135 | 1.350 | 0.000 | 0.000 | 0.000 | +| Vcco12 | 1.200 | 0.000 | 0.000 | 0.000 | +| Vccaux_io | 1.800 | 0.000 | 0.000 | 0.000 | +| Vccbram | 1.000 | 0.000 | 0.000 | 0.000 | +| MGTAVcc | 1.000 | 0.000 | 0.000 | 0.000 | +| MGTAVtt | 1.200 | 0.000 | 0.000 | 0.000 | +| MGTVccaux | 1.800 | 0.000 | 0.000 | 0.000 | +| Vccpint | 1.000 | 0.025 | 0.000 | 0.025 | +| Vccpaux | 1.800 | 0.010 | 0.000 | 0.010 | +| Vccpll | 1.800 | 0.003 | 0.000 | 0.003 | +| Vcco_ddr | 1.500 | 0.000 | 0.000 | 0.000 | +| Vcco_mio0 | 1.800 | 0.000 | 0.000 | 0.000 | +| Vcco_mio1 | 1.800 | 0.000 | 0.000 | 0.000 | +| Vccadc | 1.800 | 0.020 | 0.000 | 0.020 | ++-----------+-------------+-----------+-------------+------------+ + + +1.3 Confidence Level +-------------------- + ++-----------------------------+------------+--------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------+ +| User Input Data | Confidence | Details | Action | ++-----------------------------+------------+--------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------+ +| Design implementation state | High | Design is routed | | +| Clock nodes activity | Low | User specified less than 75% of clocks | Provide missing clock activity with a constraint file, simulation results or by editing the "By Clock Domain" view | +| I/O nodes activity | Low | More than 75% of inputs are missing user specification | Provide missing input activity with simulation results or by editing the "By Resource Type -> I/Os" view | +| Internal nodes activity | Medium | User specified less than 25% of internal nodes | Provide missing internal nodes activity with simulation results or by editing the "By Resource Type" views | +| Device models | High | Device models are Production | | +| | | | | +| Overall confidence level | Low | | | ++-----------------------------+------------+--------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------+ + + +2. Settings +----------- + +2.1 Environment +--------------- + ++-----------------------+------------------------+ +| Ambient Temp (C) | 25.0 | +| ThetaJA (C/W) | 11.5 | +| Airflow (LFM) | 250 | +| Heat Sink | none | +| ThetaSA (C/W) | 0.0 | +| Board Selection | medium (10"x10") | +| # of Board Layers | 8to11 (8 to 11 Layers) | +| Board Temperature (C) | 25.0 | ++-----------------------+------------------------+ + + +2.2 Clock Constraints +--------------------- + ++-------+--------+-----------------+ +| Clock | Domain | Constraint (ns) | ++-------+--------+-----------------+ + + +3. Detailed Reports +------------------- + +3.1 By Hierarchy +---------------- + ++----------+-----------+ +| Name | Power (W) | ++----------+-----------+ +| midpoint | 1.087 | +| i1 | 0.013 | +| i2 | 0.008 | +| i3 | 0.010 | +| shft | 0.009 | ++----------+-----------+ + + diff --git a/sim/sim.runs/impl_1/midpoint_power_routed.rpx b/sim/sim.runs/impl_1/midpoint_power_routed.rpx new file mode 100644 index 0000000..b7044ed Binary files /dev/null and b/sim/sim.runs/impl_1/midpoint_power_routed.rpx differ diff --git a/sim/sim.runs/impl_1/midpoint_power_summary_routed.pb b/sim/sim.runs/impl_1/midpoint_power_summary_routed.pb new file mode 100644 index 0000000..1fb9b2d Binary files /dev/null and b/sim/sim.runs/impl_1/midpoint_power_summary_routed.pb differ diff --git a/sim/sim.runs/impl_1/midpoint_route_status.pb b/sim/sim.runs/impl_1/midpoint_route_status.pb new file mode 100644 index 0000000..d44de2a Binary files /dev/null and b/sim/sim.runs/impl_1/midpoint_route_status.pb differ diff --git a/sim/sim.runs/impl_1/midpoint_route_status.rpt b/sim/sim.runs/impl_1/midpoint_route_status.rpt new file mode 100644 index 0000000..63629c3 --- /dev/null +++ b/sim/sim.runs/impl_1/midpoint_route_status.rpt @@ -0,0 +1,11 @@ +Design Route Status + : # nets : + ------------------------------------------- : ----------- : + # of logical nets.......................... : 54 : + # of nets not needing routing.......... : 19 : + # of internally routed nets........ : 19 : + # of routable nets..................... : 35 : + # of fully routed nets............. : 35 : + # of nets with routing errors.......... : 0 : + ------------------------------------------- : ----------- : + diff --git a/sim/sim.runs/impl_1/midpoint_routed.dcp b/sim/sim.runs/impl_1/midpoint_routed.dcp new file mode 100644 index 0000000..e5c5516 Binary files /dev/null and b/sim/sim.runs/impl_1/midpoint_routed.dcp differ diff --git a/sim/sim.runs/impl_1/midpoint_timing_summary_routed.rpt b/sim/sim.runs/impl_1/midpoint_timing_summary_routed.rpt new file mode 100644 index 0000000..b498b98 --- /dev/null +++ b/sim/sim.runs/impl_1/midpoint_timing_summary_routed.rpt @@ -0,0 +1,173 @@ +Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. +--------------------------------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2017.2 (lin64) Build 1909853 Thu Jun 15 18:39:10 MDT 2017 +| Date : Wed Oct 25 21:40:50 2017 +| Host : Kreyshawn running 64-bit Ubuntu 14.04.5 LTS +| Command : report_timing_summary -warn_on_violation -max_paths 10 -file midpoint_timing_summary_routed.rpt -rpx midpoint_timing_summary_routed.rpx +| Design : midpoint +| Device : 7z010-clg400 +| Speed File : -1 PRODUCTION 1.11 2014-09-11 +--------------------------------------------------------------------------------------------------------------------------------------------------------- + +Timing Summary Report + +------------------------------------------------------------------------------------------------ +| Timer Settings +| -------------- +------------------------------------------------------------------------------------------------ + + Enable Multi Corner Analysis : Yes + Enable Pessimism Removal : Yes + Pessimism Removal Resolution : Nearest Common Node + Enable Input Delay Default Clock : No + Enable Preset / Clear Arcs : No + Disable Flight Delays : No + Ignore I/O Paths : No + Timing Early Launch at Borrowing Latches : false + + Corner Analyze Analyze + Name Max Paths Min Paths + ------ --------- --------- + Slow Yes Yes + Fast Yes Yes + + + +check_timing report + +Table of Contents +----------------- +1. checking no_clock +2. checking constant_clock +3. checking pulse_width_clock +4. checking unconstrained_internal_endpoints +5. checking no_input_delay +6. checking no_output_delay +7. checking multiple_clock +8. checking generated_clocks +9. checking loops +10. checking partial_input_delay +11. checking partial_output_delay +12. checking latch_loops + +1. checking no_clock +-------------------- + There are 28 register/latch pins with no clock driven by root clock pin: clk (HIGH) + + +2. checking constant_clock +-------------------------- + There are 0 register/latch pins with constant_clock. + + +3. checking pulse_width_clock +----------------------------- + There are 0 register/latch pins which need pulse_width check + + +4. checking unconstrained_internal_endpoints +-------------------------------------------- + There are 54 pins that are not constrained for maximum delay. (HIGH) + + There are 0 pins that are not constrained for maximum delay due to constant clock. + + +5. checking no_input_delay +-------------------------- + There are 3 input ports with no input delay specified. (HIGH) + + There are 0 input ports with no input delay but user has a false path constraint. + + +6. checking no_output_delay +--------------------------- + There are 8 ports with no output delay specified. (HIGH) + + There are 0 ports with no output delay but user has a false path constraint + + There are 0 ports with no output delay but with a timing clock defined on it or propagating through it + + +7. checking multiple_clock +-------------------------- + There are 0 register/latch pins with multiple clocks. + + +8. checking generated_clocks +---------------------------- + There are 0 generated clocks that are not connected to a clock source. + + +9. checking loops +----------------- + There are 0 combinational loops in the design. + + +10. checking partial_input_delay +-------------------------------- + There are 0 input ports with partial input delay specified. + + +11. checking partial_output_delay +--------------------------------- + There are 0 ports with partial output delay specified. + + +12. checking latch_loops +------------------------ + There are 0 combinational latch loops in the design through latch input + + + +------------------------------------------------------------------------------------------------ +| Design Timing Summary +| --------------------- +------------------------------------------------------------------------------------------------ + + WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints + ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- + NA NA NA NA NA NA NA NA NA NA NA NA + + +There are no user specified timing constraints. + + +------------------------------------------------------------------------------------------------ +| Clock Summary +| ------------- +------------------------------------------------------------------------------------------------ + + +------------------------------------------------------------------------------------------------ +| Intra Clock Table +| ----------------- +------------------------------------------------------------------------------------------------ + +Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints +----- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- + + +------------------------------------------------------------------------------------------------ +| Inter Clock Table +| ----------------- +------------------------------------------------------------------------------------------------ + +From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints +---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- + + +------------------------------------------------------------------------------------------------ +| Other Path Groups Table +| ----------------------- +------------------------------------------------------------------------------------------------ + +Path Group From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints +---------- ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- + + +------------------------------------------------------------------------------------------------ +| Timing Details +| -------------- +------------------------------------------------------------------------------------------------ + + diff --git a/sim/sim.runs/impl_1/midpoint_timing_summary_routed.rpx b/sim/sim.runs/impl_1/midpoint_timing_summary_routed.rpx new file mode 100644 index 0000000..80bece1 Binary files /dev/null and b/sim/sim.runs/impl_1/midpoint_timing_summary_routed.rpx differ diff --git a/sim/sim.runs/impl_1/midpoint_utilization_placed.pb b/sim/sim.runs/impl_1/midpoint_utilization_placed.pb new file mode 100644 index 0000000..f057bc8 Binary files /dev/null and b/sim/sim.runs/impl_1/midpoint_utilization_placed.pb differ diff --git a/sim/sim.runs/impl_1/midpoint_utilization_placed.rpt b/sim/sim.runs/impl_1/midpoint_utilization_placed.rpt new file mode 100644 index 0000000..c5ff784 --- /dev/null +++ b/sim/sim.runs/impl_1/midpoint_utilization_placed.rpt @@ -0,0 +1,201 @@ +Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. +------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2017.2 (lin64) Build 1909853 Thu Jun 15 18:39:10 MDT 2017 +| Date : Wed Oct 25 21:40:39 2017 +| Host : Kreyshawn running 64-bit Ubuntu 14.04.5 LTS +| Command : report_utilization -file midpoint_utilization_placed.rpt -pb midpoint_utilization_placed.pb +| Design : midpoint +| Device : 7z010clg400-1 +| Design State : Fully Placed +------------------------------------------------------------------------------------------------------------- + +Utilization Design Information + +Table of Contents +----------------- +1. Slice Logic +1.1 Summary of Registers by Type +2. Slice Logic Distribution +3. Memory +4. DSP +5. IO and GT Specific +6. Clocking +7. Specific Feature +8. Primitives +9. Black Boxes +10. Instantiated Netlists + +1. Slice Logic +-------------- + ++-------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-------------------------+------+-------+-----------+-------+ +| Slice LUTs | 5 | 0 | 17600 | 0.03 | +| LUT as Logic | 5 | 0 | 17600 | 0.03 | +| LUT as Memory | 0 | 0 | 6000 | 0.00 | +| Slice Registers | 28 | 0 | 35200 | 0.08 | +| Register as Flip Flop | 28 | 0 | 35200 | 0.08 | +| Register as Latch | 0 | 0 | 35200 | 0.00 | +| F7 Muxes | 0 | 0 | 8800 | 0.00 | +| F8 Muxes | 0 | 0 | 4400 | 0.00 | ++-------------------------+------+-------+-----------+-------+ + + +1.1 Summary of Registers by Type +-------------------------------- + ++-------+--------------+-------------+--------------+ +| Total | Clock Enable | Synchronous | Asynchronous | ++-------+--------------+-------------+--------------+ +| 0 | _ | - | - | +| 0 | _ | - | Set | +| 0 | _ | - | Reset | +| 0 | _ | Set | - | +| 0 | _ | Reset | - | +| 0 | Yes | - | - | +| 0 | Yes | - | Set | +| 0 | Yes | - | Reset | +| 0 | Yes | Set | - | +| 28 | Yes | Reset | - | ++-------+--------------+-------------+--------------+ + + +2. Slice Logic Distribution +--------------------------- + ++-------------------------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-------------------------------------------+------+-------+-----------+-------+ +| Slice | 9 | 0 | 4400 | 0.20 | +| SLICEL | 3 | 0 | | | +| SLICEM | 6 | 0 | | | +| LUT as Logic | 5 | 0 | 17600 | 0.03 | +| using O5 output only | 0 | | | | +| using O6 output only | 3 | | | | +| using O5 and O6 | 2 | | | | +| LUT as Memory | 0 | 0 | 6000 | 0.00 | +| LUT as Distributed RAM | 0 | 0 | | | +| LUT as Shift Register | 0 | 0 | | | +| LUT Flip Flop Pairs | 4 | 0 | 17600 | 0.02 | +| fully used LUT-FF pairs | 2 | | | | +| LUT-FF pairs with one unused LUT output | 2 | | | | +| LUT-FF pairs with one unused Flip Flop | 2 | | | | +| Unique Control Sets | 2 | | | | ++-------------------------------------------+------+-------+-----------+-------+ +* Note: Review the Control Sets Report for more information regarding control sets. + + +3. Memory +--------- + ++----------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++----------------+------+-------+-----------+-------+ +| Block RAM Tile | 0 | 0 | 60 | 0.00 | +| RAMB36/FIFO* | 0 | 0 | 60 | 0.00 | +| RAMB18 | 0 | 0 | 120 | 0.00 | ++----------------+------+-------+-----------+-------+ +* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1 + + +4. DSP +------ + ++-----------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-----------+------+-------+-----------+-------+ +| DSPs | 0 | 0 | 80 | 0.00 | ++-----------+------+-------+-----------+-------+ + + +5. IO and GT Specific +--------------------- + ++-----------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-----------------------------+------+-------+-----------+-------+ +| Bonded IOB | 12 | 12 | 100 | 12.00 | +| IOB Master Pads | 5 | | | | +| IOB Slave Pads | 6 | | | | +| Bonded IPADs | 0 | 0 | 2 | 0.00 | +| Bonded IOPADs | 0 | 0 | 130 | 0.00 | +| PHY_CONTROL | 0 | 0 | 2 | 0.00 | +| PHASER_REF | 0 | 0 | 2 | 0.00 | +| OUT_FIFO | 0 | 0 | 8 | 0.00 | +| IN_FIFO | 0 | 0 | 8 | 0.00 | +| IDELAYCTRL | 0 | 0 | 2 | 0.00 | +| IBUFDS | 0 | 0 | 96 | 0.00 | +| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 8 | 0.00 | +| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 8 | 0.00 | +| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 100 | 0.00 | +| ILOGIC | 0 | 0 | 100 | 0.00 | +| OLOGIC | 0 | 0 | 100 | 0.00 | ++-----------------------------+------+-------+-----------+-------+ + + +6. Clocking +----------- + ++------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++------------+------+-------+-----------+-------+ +| BUFGCTRL | 1 | 0 | 32 | 3.13 | +| BUFIO | 0 | 0 | 8 | 0.00 | +| MMCME2_ADV | 0 | 0 | 2 | 0.00 | +| PLLE2_ADV | 0 | 0 | 2 | 0.00 | +| BUFMRCE | 0 | 0 | 4 | 0.00 | +| BUFHCE | 0 | 0 | 48 | 0.00 | +| BUFR | 0 | 0 | 8 | 0.00 | ++------------+------+-------+-----------+-------+ + + +7. Specific Feature +------------------- + ++-------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-------------+------+-------+-----------+-------+ +| BSCANE2 | 0 | 0 | 4 | 0.00 | +| CAPTUREE2 | 0 | 0 | 1 | 0.00 | +| DNA_PORT | 0 | 0 | 1 | 0.00 | +| EFUSE_USR | 0 | 0 | 1 | 0.00 | +| FRAME_ECCE2 | 0 | 0 | 1 | 0.00 | +| ICAPE2 | 0 | 0 | 2 | 0.00 | +| STARTUPE2 | 0 | 0 | 1 | 0.00 | +| XADC | 0 | 0 | 1 | 0.00 | ++-------------+------+-------+-----------+-------+ + + +8. Primitives +------------- + ++----------+------+---------------------+ +| Ref Name | Used | Functional Category | ++----------+------+---------------------+ +| FDRE | 28 | Flop & Latch | +| OBUF | 8 | IO | +| LUT4 | 4 | LUT | +| IBUF | 4 | IO | +| LUT5 | 2 | LUT | +| LUT2 | 1 | LUT | +| BUFG | 1 | Clock | ++----------+------+---------------------+ + + +9. Black Boxes +-------------- + ++----------+------+ +| Ref Name | Used | ++----------+------+ + + +10. Instantiated Netlists +------------------------- + ++----------+------+ +| Ref Name | Used | ++----------+------+ + + diff --git a/sim/sim.runs/impl_1/opt_design.pb b/sim/sim.runs/impl_1/opt_design.pb new file mode 100644 index 0000000..90b8ab9 Binary files /dev/null and b/sim/sim.runs/impl_1/opt_design.pb differ diff --git a/sim/sim.runs/impl_1/place_design.pb b/sim/sim.runs/impl_1/place_design.pb new file mode 100644 index 0000000..a4a9c2f Binary files /dev/null and b/sim/sim.runs/impl_1/place_design.pb differ diff --git a/sim/sim.runs/impl_1/project.wdf b/sim/sim.runs/impl_1/project.wdf new file mode 100644 index 0000000..50d189a --- /dev/null +++ b/sim/sim.runs/impl_1/project.wdf @@ -0,0 +1,31 @@ +version:1 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:737263736574636f756e74:31:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f6e73747261696e74736574636f756e74:31:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64657369676e6d6f6465:52544c:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73796e7468657369737374726174656779:56697661646f2053796e7468657369732044656661756c7473:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:696d706c7374726174656779:56697661646f20496d706c656d656e746174696f6e2044656661756c7473:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:63757272656e7473796e74686573697372756e:73796e74685f31:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:63757272656e74696d706c72756e:696d706c5f31:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:746f74616c73796e74686573697372756e73:31:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:746f74616c696d706c72756e73:31:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f72655f636f6e7461696e6572:66616c7365:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73696d756c61746f725f6c616e6775616765:4d69786564:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:7461726765745f6c616e6775616765:566572696c6f67:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64656661756c745f6c696272617279:78696c5f64656661756c746c6962:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:7461726765745f73696d756c61746f72:5853696d:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f7873696d:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f6d6f64656c73696d:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f717565737461:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f696573:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f766373:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f72697669657261:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f61637469766568646c:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f7873696d:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f6d6f64656c73696d:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f717565737461:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f696573:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f766373:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f72697669657261:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f61637469766568646c:30:00:00 +5f5f48494444454e5f5f:5f5f48494444454e5f5f:50726f6a65637455554944:6238616665393763616261623435353261333030613663643238356561386437:506172656e742050412070726f6a656374204944:00 +eof:2855082633 diff --git a/sim/sim.runs/impl_1/route_design.pb b/sim/sim.runs/impl_1/route_design.pb new file mode 100644 index 0000000..01dc00f Binary files /dev/null and b/sim/sim.runs/impl_1/route_design.pb differ diff --git a/sim/sim.runs/impl_1/rundef.js b/sim/sim.runs/impl_1/rundef.js new file mode 100644 index 0000000..05872ac --- /dev/null +++ b/sim/sim.runs/impl_1/rundef.js @@ -0,0 +1,44 @@ +// +// Vivado(TM) +// rundef.js: a Vivado-generated Runs Script for WSH 5.1/5.6 +// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. +// + +echo "This script was generated under a different operating system." +echo "Please update the PATH variable below, before executing this script" +exit + +var WshShell = new ActiveXObject( "WScript.Shell" ); +var ProcEnv = WshShell.Environment( "Process" ); +var PathVal = ProcEnv("PATH"); +if ( PathVal.length == 0 ) { + PathVal = "/opt/Xilinx/Vivado/2017.2/ids_lite/ISE/bin/lin64;/opt/Xilinx/Vivado/2017.2/ids_lite/ISE/lib/lin64;/opt/Xilinx/Vivado/2017.2/bin;"; +} else { + PathVal = "/opt/Xilinx/Vivado/2017.2/ids_lite/ISE/bin/lin64;/opt/Xilinx/Vivado/2017.2/ids_lite/ISE/lib/lin64;/opt/Xilinx/Vivado/2017.2/bin;" + PathVal; +} + +ProcEnv("PATH") = PathVal; + +var RDScrFP = WScript.ScriptFullName; +var RDScrN = WScript.ScriptName; +var RDScrDir = RDScrFP.substr( 0, RDScrFP.length - RDScrN.length - 1 ); +var ISEJScriptLib = RDScrDir + "/ISEWrap.js"; +eval( EAInclude(ISEJScriptLib) ); + + +// pre-commands: +ISETouchFile( "write_bitstream", "begin" ); +ISEStep( "vivado", + "-log midpoint.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source midpoint.tcl -notrace" ); + + + + + +function EAInclude( EAInclFilename ) { + var EAFso = new ActiveXObject( "Scripting.FileSystemObject" ); + var EAInclFile = EAFso.OpenTextFile( EAInclFilename ); + var EAIFContents = EAInclFile.ReadAll(); + EAInclFile.Close(); + return EAIFContents; +} diff --git a/sim/sim.runs/impl_1/runme.bat b/sim/sim.runs/impl_1/runme.bat new file mode 100644 index 0000000..220ba68 --- /dev/null +++ b/sim/sim.runs/impl_1/runme.bat @@ -0,0 +1,11 @@ +@echo off + +rem Vivado (TM) +rem runme.bat: a Vivado-generated Script +rem Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. + + +set HD_SDIR=%~dp0 +cd /d "%HD_SDIR%" +set PATH=%SYSTEMROOT%\system32;%PATH% +cscript /nologo /E:JScript "%HD_SDIR%\rundef.js" %* diff --git a/sim/sim.runs/impl_1/runme.log b/sim/sim.runs/impl_1/runme.log new file mode 100644 index 0000000..aca8766 --- /dev/null +++ b/sim/sim.runs/impl_1/runme.log @@ -0,0 +1,430 @@ + +*** Running vivado + with args -log midpoint.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source midpoint.tcl -notrace + + +****** Vivado v2017.2 (64-bit) + **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 + **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 + ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. + +source midpoint.tcl -notrace +Design is defaulting to srcset: sources_1 +Design is defaulting to constrset: constrs_1 +INFO: [Netlist 29-17] Analyzing 4 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +INFO: [Project 1-479] Netlist was created with Vivado 2017.2 +INFO: [Device 21-403] Loading part xc7z010clg400-1 +INFO: [Project 1-570] Preparing netlist for logic optimization +Parsing XDC File [/home/jspear/Development/School/Comp_Arc/Lab2/ZYBO_Master.xdc] +Finished Parsing XDC File [/home/jspear/Development/School/Comp_Arc/Lab2/ZYBO_Master.xdc] +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +Command: opt_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7z010-clg400' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010-clg400' +Running DRC as a precondition to command opt_design + +Starting DRC Task +Command: report_drc (run_mandatory_drcs) for: opt_checks +INFO: [DRC 23-27] Running DRC with 4 threads +report_drc (run_mandatory_drcs) completed successfully +INFO: [Project 1-461] DRC finished with 0 Errors +INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information. + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.47 . Memory (MB): peak = 1378.207 ; gain = 45.016 ; free physical = 10319 ; free virtual = 20551 +INFO: [Timing 38-35] Done setting XDC timing constraints. + +Starting Logic Optimization Task + +Phase 1 Retarget +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +INFO: [Opt 31-49] Retargeted 0 cell(s). +Phase 1 Retarget | Checksum: c1ca5825 + +Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 1818.699 ; gain = 0.000 ; free physical = 9950 ; free virtual = 20182 +INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 0 cells + +Phase 2 Constant propagation +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +Phase 2 Constant propagation | Checksum: c1ca5825 + +Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 1818.699 ; gain = 0.000 ; free physical = 9950 ; free virtual = 20182 +INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells + +Phase 3 Sweep +Phase 3 Sweep | Checksum: 14fe552a6 + +Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1818.699 ; gain = 0.000 ; free physical = 9950 ; free virtual = 20182 +INFO: [Opt 31-389] Phase Sweep created 6 cells and removed 0 cells + +Phase 4 BUFG optimization +Phase 4 BUFG optimization | Checksum: 14fe552a6 + +Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1818.699 ; gain = 0.000 ; free physical = 9950 ; free virtual = 20182 +INFO: [Opt 31-389] Phase BUFG optimization created 0 cells and removed 0 cells + +Phase 5 Shift Register Optimization +Phase 5 Shift Register Optimization | Checksum: 14fe552a6 + +Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1818.699 ; gain = 0.000 ; free physical = 9950 ; free virtual = 20182 +INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells + +Starting Connectivity Check Task + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1818.699 ; gain = 0.000 ; free physical = 9950 ; free virtual = 20182 +Ending Logic Optimization Task | Checksum: 14fe552a6 + +Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1818.699 ; gain = 0.000 ; free physical = 9950 ; free virtual = 20182 + +Starting Power Optimization Task +INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns. +Ending Power Optimization Task | Checksum: 19d912689 + +Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1818.699 ; gain = 0.000 ; free physical = 9950 ; free virtual = 20182 +21 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. +opt_design completed successfully +opt_design: Time (s): cpu = 00:00:08 ; elapsed = 00:00:07 . Memory (MB): peak = 1818.699 ; gain = 485.508 ; free physical = 9950 ; free virtual = 20182 +Writing placer database... +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Write XDEF Complete: Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 1842.711 ; gain = 0.000 ; free physical = 9948 ; free virtual = 20182 +INFO: [Common 17-1381] The checkpoint '/home/jspear/Development/School/Comp_Arc/Lab2/sim/sim.runs/impl_1/midpoint_opt.dcp' has been generated. +Command: report_drc -file midpoint_drc_opted.rpt +INFO: [DRC 23-27] Running DRC with 4 threads +INFO: [Coretcl 2-168] The results of DRC are in file /home/jspear/Development/School/Comp_Arc/Lab2/sim/sim.runs/impl_1/midpoint_drc_opted.rpt. +report_drc completed successfully +INFO: [Chipscope 16-241] No debug cores found in the current design. +Before running the implement_debug_core command, either use the Set Up Debug wizard (GUI mode) +or use the create_debug_core and connect_debug_core Tcl commands to insert debug cores into the design. +Command: place_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7z010-clg400' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010-clg400' +Command: report_drc (run_mandatory_drcs) for: incr_eco_checks +INFO: [DRC 23-27] Running DRC with 4 threads +report_drc (run_mandatory_drcs) completed successfully +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. +Running DRC as a precondition to command place_design +Command: report_drc (run_mandatory_drcs) for: placer_checks +INFO: [DRC 23-27] Running DRC with 4 threads +report_drc (run_mandatory_drcs) completed successfully +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. + +Starting Placer Task +INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 4 CPUs + +Phase 1 Placer Initialization + +Phase 1.1 Placer Initialization Netlist Sorting +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1850.715 ; gain = 0.000 ; free physical = 9935 ; free virtual = 20167 +Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 14ca5cf03 + +Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1850.715 ; gain = 0.000 ; free physical = 9935 ; free virtual = 20167 +INFO: [Timing 38-35] Done setting XDC timing constraints. +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1850.715 ; gain = 0.000 ; free physical = 9935 ; free virtual = 20167 + +Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device +INFO: [Timing 38-35] Done setting XDC timing constraints. +Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: e889b640 + +Time (s): cpu = 00:00:00.32 ; elapsed = 00:00:00.24 . Memory (MB): peak = 1850.715 ; gain = 0.000 ; free physical = 9936 ; free virtual = 20168 + +Phase 1.3 Build Placer Netlist Model +Phase 1.3 Build Placer Netlist Model | Checksum: 1d803f5c8 + +Time (s): cpu = 00:00:00.33 ; elapsed = 00:00:00.24 . Memory (MB): peak = 1850.715 ; gain = 0.000 ; free physical = 9936 ; free virtual = 20168 + +Phase 1.4 Constrain Clocks/Macros +Phase 1.4 Constrain Clocks/Macros | Checksum: 1d803f5c8 + +Time (s): cpu = 00:00:00.33 ; elapsed = 00:00:00.24 . Memory (MB): peak = 1850.715 ; gain = 0.000 ; free physical = 9936 ; free virtual = 20168 +Phase 1 Placer Initialization | Checksum: 1d803f5c8 + +Time (s): cpu = 00:00:00.33 ; elapsed = 00:00:00.24 . Memory (MB): peak = 1850.715 ; gain = 0.000 ; free physical = 9936 ; free virtual = 20168 + +Phase 2 Global Placement +WARNING: [Place 46-30] place_design is not in timing mode. Skip physical synthesis in placer +Phase 2 Global Placement | Checksum: 1b5704437 + +Time (s): cpu = 00:00:00.62 ; elapsed = 00:00:00.37 . Memory (MB): peak = 1882.730 ; gain = 32.016 ; free physical = 9930 ; free virtual = 20162 + +Phase 3 Detail Placement + +Phase 3.1 Commit Multi Column Macros +Phase 3.1 Commit Multi Column Macros | Checksum: 1b5704437 + +Time (s): cpu = 00:00:00.63 ; elapsed = 00:00:00.37 . Memory (MB): peak = 1882.730 ; gain = 32.016 ; free physical = 9930 ; free virtual = 20162 + +Phase 3.2 Commit Most Macros & LUTRAMs +Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 14ee8c1ba + +Time (s): cpu = 00:00:00.64 ; elapsed = 00:00:00.37 . Memory (MB): peak = 1882.730 ; gain = 32.016 ; free physical = 9930 ; free virtual = 20162 + +Phase 3.3 Area Swap Optimization +Phase 3.3 Area Swap Optimization | Checksum: 15274315a + +Time (s): cpu = 00:00:00.65 ; elapsed = 00:00:00.38 . Memory (MB): peak = 1882.730 ; gain = 32.016 ; free physical = 9930 ; free virtual = 20162 + +Phase 3.4 Pipeline Register Optimization +Phase 3.4 Pipeline Register Optimization | Checksum: 15274315a + +Time (s): cpu = 00:00:00.66 ; elapsed = 00:00:00.38 . Memory (MB): peak = 1882.730 ; gain = 32.016 ; free physical = 9930 ; free virtual = 20162 + +Phase 3.5 Small Shape Detail Placement +Phase 3.5 Small Shape Detail Placement | Checksum: 19b131221 + +Time (s): cpu = 00:00:00.72 ; elapsed = 00:00:00.42 . Memory (MB): peak = 1882.730 ; gain = 32.016 ; free physical = 9929 ; free virtual = 20161 + +Phase 3.6 Re-assign LUT pins +Phase 3.6 Re-assign LUT pins | Checksum: 19b131221 + +Time (s): cpu = 00:00:00.72 ; elapsed = 00:00:00.42 . Memory (MB): peak = 1882.730 ; gain = 32.016 ; free physical = 9929 ; free virtual = 20161 + +Phase 3.7 Pipeline Register Optimization +Phase 3.7 Pipeline Register Optimization | Checksum: 19b131221 + +Time (s): cpu = 00:00:00.72 ; elapsed = 00:00:00.42 . Memory (MB): peak = 1882.730 ; gain = 32.016 ; free physical = 9929 ; free virtual = 20161 +Phase 3 Detail Placement | Checksum: 19b131221 + +Time (s): cpu = 00:00:00.72 ; elapsed = 00:00:00.43 . Memory (MB): peak = 1882.730 ; gain = 32.016 ; free physical = 9929 ; free virtual = 20161 + +Phase 4 Post Placement Optimization and Clean-Up + +Phase 4.1 Post Commit Optimization +Phase 4.1 Post Commit Optimization | Checksum: 19b131221 + +Time (s): cpu = 00:00:00.73 ; elapsed = 00:00:00.43 . Memory (MB): peak = 1882.730 ; gain = 32.016 ; free physical = 9929 ; free virtual = 20161 + +Phase 4.2 Post Placement Cleanup +Phase 4.2 Post Placement Cleanup | Checksum: 19b131221 + +Time (s): cpu = 00:00:00.74 ; elapsed = 00:00:00.43 . Memory (MB): peak = 1882.730 ; gain = 32.016 ; free physical = 9929 ; free virtual = 20162 + +Phase 4.3 Placer Reporting +Phase 4.3 Placer Reporting | Checksum: 19b131221 + +Time (s): cpu = 00:00:00.74 ; elapsed = 00:00:00.43 . Memory (MB): peak = 1882.730 ; gain = 32.016 ; free physical = 9929 ; free virtual = 20162 + +Phase 4.4 Final Placement Cleanup +Phase 4.4 Final Placement Cleanup | Checksum: 147869b64 + +Time (s): cpu = 00:00:00.74 ; elapsed = 00:00:00.43 . Memory (MB): peak = 1882.730 ; gain = 32.016 ; free physical = 9929 ; free virtual = 20162 +Phase 4 Post Placement Optimization and Clean-Up | Checksum: 147869b64 + +Time (s): cpu = 00:00:00.74 ; elapsed = 00:00:00.43 . Memory (MB): peak = 1882.730 ; gain = 32.016 ; free physical = 9929 ; free virtual = 20162 +Ending Placer Task | Checksum: c4929310 + +Time (s): cpu = 00:00:00.74 ; elapsed = 00:00:00.43 . Memory (MB): peak = 1882.730 ; gain = 32.016 ; free physical = 9932 ; free virtual = 20164 +36 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered. +place_design completed successfully +Writing placer database... +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Write XDEF Complete: Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1882.730 ; gain = 0.000 ; free physical = 9931 ; free virtual = 20165 +INFO: [Common 17-1381] The checkpoint '/home/jspear/Development/School/Comp_Arc/Lab2/sim/sim.runs/impl_1/midpoint_placed.dcp' has been generated. +report_io: Time (s): cpu = 00:00:00.11 ; elapsed = 00:00:00.14 . Memory (MB): peak = 1882.730 ; gain = 0.000 ; free physical = 9923 ; free virtual = 20155 +report_utilization: Time (s): cpu = 00:00:00.08 ; elapsed = 00:00:00.10 . Memory (MB): peak = 1882.730 ; gain = 0.000 ; free physical = 9929 ; free virtual = 20161 +report_control_sets: Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.08 . Memory (MB): peak = 1882.730 ; gain = 0.000 ; free physical = 9929 ; free virtual = 20161 +Command: route_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7z010-clg400' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010-clg400' +Running DRC as a precondition to command route_design +Command: report_drc (run_mandatory_drcs) for: router_checks +INFO: [DRC 23-27] Running DRC with 4 threads +report_drc (run_mandatory_drcs) completed successfully +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. + + +Starting Routing Task +INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 4 CPUs +Checksum: PlaceDB: a243f121 ConstDB: 0 ShapeSum: 224ea1ef RouteDB: 0 + +Phase 1 Build RT Design +Phase 1 Build RT Design | Checksum: 17af5ee1d + +Time (s): cpu = 00:00:09 ; elapsed = 00:00:07 . Memory (MB): peak = 1894.719 ; gain = 11.988 ; free physical = 9856 ; free virtual = 20088 + +Phase 2 Router Initialization +INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. + +Phase 2.1 Fix Topology Constraints +Phase 2.1 Fix Topology Constraints | Checksum: 17af5ee1d + +Time (s): cpu = 00:00:09 ; elapsed = 00:00:07 . Memory (MB): peak = 1908.719 ; gain = 25.988 ; free physical = 9841 ; free virtual = 20073 + +Phase 2.2 Pre Route Cleanup +Phase 2.2 Pre Route Cleanup | Checksum: 17af5ee1d + +Time (s): cpu = 00:00:09 ; elapsed = 00:00:07 . Memory (MB): peak = 1908.719 ; gain = 25.988 ; free physical = 9841 ; free virtual = 20073 + Number of Nodes with overlaps = 0 +Phase 2 Router Initialization | Checksum: 1a406675 + +Time (s): cpu = 00:00:09 ; elapsed = 00:00:07 . Memory (MB): peak = 1917.719 ; gain = 34.988 ; free physical = 9834 ; free virtual = 20066 + +Phase 3 Initial Routing +Phase 3 Initial Routing | Checksum: 3ac3d490 + +Time (s): cpu = 00:00:09 ; elapsed = 00:00:07 . Memory (MB): peak = 1917.719 ; gain = 34.988 ; free physical = 9837 ; free virtual = 20069 + +Phase 4 Rip-up And Reroute + +Phase 4.1 Global Iteration 0 + Number of Nodes with overlaps = 0 +Phase 4.1 Global Iteration 0 | Checksum: 16dd6649b + +Time (s): cpu = 00:00:09 ; elapsed = 00:00:07 . Memory (MB): peak = 1917.719 ; gain = 34.988 ; free physical = 9837 ; free virtual = 20069 +Phase 4 Rip-up And Reroute | Checksum: 16dd6649b + +Time (s): cpu = 00:00:09 ; elapsed = 00:00:07 . Memory (MB): peak = 1917.719 ; gain = 34.988 ; free physical = 9837 ; free virtual = 20069 + +Phase 5 Delay and Skew Optimization +Phase 5 Delay and Skew Optimization | Checksum: 16dd6649b + +Time (s): cpu = 00:00:09 ; elapsed = 00:00:07 . Memory (MB): peak = 1917.719 ; gain = 34.988 ; free physical = 9837 ; free virtual = 20069 + +Phase 6 Post Hold Fix + +Phase 6.1 Hold Fix Iter +Phase 6.1 Hold Fix Iter | Checksum: 16dd6649b + +Time (s): cpu = 00:00:09 ; elapsed = 00:00:07 . Memory (MB): peak = 1917.719 ; gain = 34.988 ; free physical = 9837 ; free virtual = 20069 +Phase 6 Post Hold Fix | Checksum: 16dd6649b + +Time (s): cpu = 00:00:09 ; elapsed = 00:00:07 . Memory (MB): peak = 1917.719 ; gain = 34.988 ; free physical = 9837 ; free virtual = 20069 + +Phase 7 Route finalize + +Router Utilization Summary + Global Vertical Routing Utilization = 0.0318131 % + Global Horizontal Routing Utilization = 0.0078125 % + Routable Net Status* + *Does not include unroutable nets such as driverless and loadless. + Run report_route_status for detailed report. + Number of Failed Nets = 0 + Number of Unrouted Nets = 0 + Number of Partially Routed Nets = 0 + Number of Node Overlaps = 0 + +Congestion Report +North Dir 1x1 Area, Max Cong = 16.2162%, No Congested Regions. +South Dir 1x1 Area, Max Cong = 16.2162%, No Congested Regions. +East Dir 1x1 Area, Max Cong = 7.35294%, No Congested Regions. +West Dir 1x1 Area, Max Cong = 2.94118%, No Congested Regions. +Phase 7 Route finalize | Checksum: 16dd6649b + +Time (s): cpu = 00:00:09 ; elapsed = 00:00:07 . Memory (MB): peak = 1917.719 ; gain = 34.988 ; free physical = 9837 ; free virtual = 20069 + +Phase 8 Verifying routed nets + + Verification completed successfully +Phase 8 Verifying routed nets | Checksum: 16dd6649b + +Time (s): cpu = 00:00:09 ; elapsed = 00:00:07 . Memory (MB): peak = 1919.719 ; gain = 36.988 ; free physical = 9836 ; free virtual = 20068 + +Phase 9 Depositing Routes +Phase 9 Depositing Routes | Checksum: 103b01834 + +Time (s): cpu = 00:00:09 ; elapsed = 00:00:07 . Memory (MB): peak = 1919.719 ; gain = 36.988 ; free physical = 9836 ; free virtual = 20068 +INFO: [Route 35-16] Router Completed Successfully + +Time (s): cpu = 00:00:09 ; elapsed = 00:00:07 . Memory (MB): peak = 1919.719 ; gain = 36.988 ; free physical = 9852 ; free virtual = 20084 + +Routing Is Done. +44 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered. +route_design completed successfully +route_design: Time (s): cpu = 00:00:11 ; elapsed = 00:00:08 . Memory (MB): peak = 1945.750 ; gain = 63.020 ; free physical = 9852 ; free virtual = 20084 +Writing placer database... +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Write XDEF Complete: Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 1945.750 ; gain = 0.000 ; free physical = 9850 ; free virtual = 20084 +INFO: [Common 17-1381] The checkpoint '/home/jspear/Development/School/Comp_Arc/Lab2/sim/sim.runs/impl_1/midpoint_routed.dcp' has been generated. +Command: report_drc -file midpoint_drc_routed.rpt -pb midpoint_drc_routed.pb -rpx midpoint_drc_routed.rpx +INFO: [DRC 23-27] Running DRC with 4 threads +INFO: [Coretcl 2-168] The results of DRC are in file /home/jspear/Development/School/Comp_Arc/Lab2/sim/sim.runs/impl_1/midpoint_drc_routed.rpt. +report_drc completed successfully +Command: report_methodology -file midpoint_methodology_drc_routed.rpt -rpx midpoint_methodology_drc_routed.rpx +INFO: [Timing 38-35] Done setting XDC timing constraints. +INFO: [DRC 23-133] Running Methodology with 4 threads +INFO: [Coretcl 2-1520] The results of Report Methodology are in file /home/jspear/Development/School/Comp_Arc/Lab2/sim/sim.runs/impl_1/midpoint_methodology_drc_routed.rpt. +report_methodology completed successfully +Command: report_power -file midpoint_power_routed.rpt -pb midpoint_power_summary_routed.pb -rpx midpoint_power_routed.rpx +WARNING: [Power 33-232] No user defined clocks were found in the design! +Resolution: Please specify clocks using create_clock/create_generated_clock for sequential elements. For pure combinatorial circuits, please specify a virtual clock, otherwise the vectorless estimation might be inaccurate +INFO: [Timing 38-35] Done setting XDC timing constraints. +Running Vector-less Activity Propagation... + +Finished Running Vector-less Activity Propagation +51 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered. +report_power completed successfully +INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max. +INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 4 CPUs +WARNING: [Timing 38-313] There are no user specified timing constraints. Timing constraints are needed for proper timing analysis. +INFO: [Common 17-206] Exiting Vivado at Wed Oct 25 21:40:50 2017... + +*** Running vivado + with args -log midpoint.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source midpoint.tcl -notrace + + +****** Vivado v2017.2 (64-bit) + **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 + **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 + ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. + +source midpoint.tcl -notrace +Command: open_checkpoint midpoint_routed.dcp + +Starting open_checkpoint Task + +Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.03 . Memory (MB): peak = 1087.020 ; gain = 0.000 ; free physical = 10568 ; free virtual = 20807 +INFO: [Netlist 29-17] Analyzing 4 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +INFO: [Project 1-479] Netlist was created with Vivado 2017.2 +INFO: [Device 21-403] Loading part xc7z010clg400-1 +INFO: [Project 1-570] Preparing netlist for logic optimization +Parsing XDC File [/home/jspear/Development/School/Comp_Arc/Lab2/sim/sim.runs/impl_1/.Xil/Vivado-8072-Kreyshawn/dcp3/midpoint.xdc] +Finished Parsing XDC File [/home/jspear/Development/School/Comp_Arc/Lab2/sim/sim.runs/impl_1/.Xil/Vivado-8072-Kreyshawn/dcp3/midpoint.xdc] +Reading XDEF placement. +Reading placer database... +Reading XDEF routing. +Read XDEF File: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1307.180 ; gain = 0.000 ; free physical = 10312 ; free virtual = 20552 +Restored from archive | CPU: 0.020000 secs | Memory: 0.051208 MB | +Finished XDEF File Restore: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1307.180 ; gain = 0.000 ; free physical = 10312 ; free virtual = 20552 +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +INFO: [Project 1-604] Checkpoint was created with Vivado v2017.2 (64-bit) build 1909853 +Command: write_bitstream -force midpoint.bit +Attempting to get a license for feature 'Implementation' and/or device 'xc7z010-clg400' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010-clg400' +Running DRC as a precondition to command write_bitstream +Command: report_drc (run_mandatory_drcs) for: bitstream_checks +INFO: [DRC 23-27] Running DRC with 4 threads +WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. +report_drc (run_mandatory_drcs) completed successfully +INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings +INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. +INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. +INFO: [Designutils 20-2272] Running write_bitstream with 4 threads. +Loading data files... +Loading site data... +Loading route data... +Processing options... +Creating bitmap... +Creating bitstream... +Writing bitstream ./midpoint.bit... +INFO: [Vivado 12-1842] Bitgen Completed Successfully. +INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. +INFO: [Common 17-186] '/home/jspear/Development/School/Comp_Arc/Lab2/sim/sim.runs/impl_1/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Wed Oct 25 21:42:09 2017. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. +16 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered. +write_bitstream completed successfully +write_bitstream: Time (s): cpu = 00:00:08 ; elapsed = 00:00:10 . Memory (MB): peak = 1738.680 ; gain = 431.500 ; free physical = 10288 ; free virtual = 20526 +INFO: [Common 17-206] Exiting Vivado at Wed Oct 25 21:42:09 2017... diff --git a/sim/sim.runs/impl_1/runme.sh b/sim/sim.runs/impl_1/runme.sh new file mode 100755 index 0000000..82293f2 --- /dev/null +++ b/sim/sim.runs/impl_1/runme.sh @@ -0,0 +1,43 @@ +#!/bin/sh + +# +# Vivado(TM) +# runme.sh: a Vivado-generated Runs Script for UNIX +# Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. +# + +if [ -z "$PATH" ]; then + PATH=/opt/Xilinx/Vivado/2017.2/ids_lite/ISE/bin/lin64:/opt/Xilinx/Vivado/2017.2/bin +else + PATH=/opt/Xilinx/Vivado/2017.2/ids_lite/ISE/bin/lin64:/opt/Xilinx/Vivado/2017.2/bin:$PATH +fi +export PATH + +if [ -z "$LD_LIBRARY_PATH" ]; then + LD_LIBRARY_PATH=/opt/Xilinx/Vivado/2017.2/ids_lite/ISE/lib/lin64 +else + LD_LIBRARY_PATH=/opt/Xilinx/Vivado/2017.2/ids_lite/ISE/lib/lin64:$LD_LIBRARY_PATH +fi +export LD_LIBRARY_PATH + +HD_PWD='/home/jspear/Development/School/Comp_Arc/Lab2/sim/sim.runs/impl_1' +cd "$HD_PWD" + +HD_LOG=runme.log +/bin/touch $HD_LOG + +ISEStep="./ISEWrap.sh" +EAStep() +{ + $ISEStep $HD_LOG "$@" >> $HD_LOG 2>&1 + if [ $? -ne 0 ] + then + exit + fi +} + +# pre-commands: +/bin/touch .write_bitstream.begin.rst +EAStep vivado -log midpoint.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source midpoint.tcl -notrace + + diff --git a/sim/sim.runs/impl_1/usage_statistics_webtalk.html b/sim/sim.runs/impl_1/usage_statistics_webtalk.html new file mode 100644 index 0000000..d22e639 --- /dev/null +++ b/sim/sim.runs/impl_1/usage_statistics_webtalk.html @@ -0,0 +1,456 @@ +Device Usage Statistics Report +

Device Usage Page (usage_statistics_webtalk.html)

This HTML page displays the device usage statistics that will be sent to Xilinx.
To see the actual file transmitted to Xilinx, please click here.

+ + + + + + + + + + + + + + + + + +
software_version_and_target_device
betaFALSEbuild_version1909853
date_generatedWed Oct 25 21:42:06 2017os_platformLIN64
product_versionVivado v2017.2 (64-bit)project_idb8afe97cabab4552a300a6cd285ea8d7
project_iteration2random_id9645f00e3026595abd5d9ced78dfe930
registration_id9645f00e3026595abd5d9ced78dfe930route_designTRUE
target_devicexc7z010target_familyzynq
target_packageclg400target_speed-1
tool_flowVivado

+ + + + + + + + +
user_environment
cpu_nameIntel(R) Core(TM) i7-5600U CPU @ 2.60GHzcpu_speed3100.804 MHz
os_nameUbuntuos_releaseUbuntu 14.04.5 LTS
system_ram16.000 GBtotal_processors1

+ + +
vivado_usage
+ + + + + + + + + + + + + +
java_command_handlers
addsources=3autoconnecttarget=1launchprogramfpga=1newproject=1
openhardwaremanager=2programdevice=1runbitgen=2runimplementation=4
runsynthesis=6showview=2viewtaskimplementation=2viewtaskprojectmanager=1
+ + + +
other_data
guimode=1
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
project_data
constraintsetcount=1core_container=falsecurrentimplrun=impl_1currentsynthesisrun=synth_1
default_library=xil_defaultlibdesignmode=RTLexport_simulation_activehdl=0export_simulation_ies=0
export_simulation_modelsim=0export_simulation_questa=0export_simulation_riviera=0export_simulation_vcs=0
export_simulation_xsim=0implstrategy=Vivado Implementation Defaultslaunch_simulation_activehdl=0launch_simulation_ies=0
launch_simulation_modelsim=0launch_simulation_questa=0launch_simulation_riviera=0launch_simulation_vcs=0
launch_simulation_xsim=0simulator_language=Mixedsrcsetcount=1synthesisstrategy=Vivado Synthesis Defaults
target_language=Verilogtarget_simulator=XSimtotalimplruns=1totalsynthesisruns=1
+
+ + + + +
unisim_transformation
+ + + + + + + + + + + +
post_unisim_transformation
bufg=1fdre=22gnd=4ibuf=4
lut2=1lut4=4lut5=2obuf=8
vcc=4
+
+ + + + + + + + + + + +
pre_unisim_transformation
bufg=1fdre=22gnd=4ibuf=4
lut2=1lut4=4lut5=2obuf=8
vcc=4
+

+ + + + +
report_drc
+ + + + + + + + + + + + + +
command_line_options
-append=default::[not_specified]-checks=default::[not_specified]-fail_on=default::[not_specified]-force=default::[not_specified]
-format=default::[not_specified]-messages=default::[not_specified]-name=default::[not_specified]-return_string=default::[not_specified]
-ruledecks=default::[not_specified]-upgrade_cw=default::[not_specified]-waived=default::[not_specified]
+
+ + + +
results
zps7-1=1
+

+ + + + + + + + + +
report_utilization
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
clocking
bufgctrl_available=32bufgctrl_fixed=0bufgctrl_used=1bufgctrl_util_percentage=3.13
bufhce_available=48bufhce_fixed=0bufhce_used=0bufhce_util_percentage=0.00
bufio_available=8bufio_fixed=0bufio_used=0bufio_util_percentage=0.00
bufmrce_available=4bufmrce_fixed=0bufmrce_used=0bufmrce_util_percentage=0.00
bufr_available=8bufr_fixed=0bufr_used=0bufr_util_percentage=0.00
mmcme2_adv_available=2mmcme2_adv_fixed=0mmcme2_adv_used=0mmcme2_adv_util_percentage=0.00
plle2_adv_available=2plle2_adv_fixed=0plle2_adv_used=0plle2_adv_util_percentage=0.00
+
+ + + + + + +
dsp
dsps_available=80dsps_fixed=0dsps_used=0dsps_util_percentage=0.00
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
io_standard
blvds_25=0diff_hstl_i=0diff_hstl_i_18=0diff_hstl_ii=0
diff_hstl_ii_18=0diff_hsul_12=0diff_mobile_ddr=0diff_sstl135=0
diff_sstl135_r=0diff_sstl15=0diff_sstl15_r=0diff_sstl18_i=0
diff_sstl18_ii=0hstl_i=0hstl_i_18=0hstl_ii=0
hstl_ii_18=0hsul_12=0lvcmos12=0lvcmos15=0
lvcmos18=0lvcmos25=0lvcmos33=1lvds_25=0
lvttl=0mini_lvds_25=0mobile_ddr=0pci33_3=0
ppds_25=0rsds_25=0sstl135=0sstl135_r=0
sstl15=0sstl15_r=0sstl18_i=0sstl18_ii=0
tmds_33=0
+
+ + + + + + + + + + + + + + +
memory
block_ram_tile_available=60block_ram_tile_fixed=0block_ram_tile_used=0block_ram_tile_util_percentage=0.00
ramb18_available=120ramb18_fixed=0ramb18_used=0ramb18_util_percentage=0.00
ramb36_fifo_available=60ramb36_fifo_fixed=0ramb36_fifo_used=0ramb36_fifo_util_percentage=0.00
+
+ + + + + + + + + + + + + + + + +
primitives
bufg_functional_category=Clockbufg_used=1fdre_functional_category=Flop & Latchfdre_used=28
ibuf_functional_category=IOibuf_used=4lut2_functional_category=LUTlut2_used=1
lut4_functional_category=LUTlut4_used=4lut5_functional_category=LUTlut5_used=2
obuf_functional_category=IOobuf_used=8
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
slice_logic
f7_muxes_available=8800f7_muxes_fixed=0f7_muxes_used=0f7_muxes_util_percentage=0.00
f8_muxes_available=4400f8_muxes_fixed=0f8_muxes_used=0f8_muxes_util_percentage=0.00
lut_as_logic_available=17600lut_as_logic_fixed=0lut_as_logic_used=5lut_as_logic_util_percentage=0.03
lut_as_memory_available=6000lut_as_memory_fixed=0lut_as_memory_used=0lut_as_memory_util_percentage=0.00
register_as_flip_flop_available=35200register_as_flip_flop_fixed=0register_as_flip_flop_used=28register_as_flip_flop_util_percentage=0.08
register_as_latch_available=35200register_as_latch_fixed=0register_as_latch_used=0register_as_latch_util_percentage=0.00
slice_luts_available=17600slice_luts_fixed=0slice_luts_used=5slice_luts_util_percentage=0.03
slice_registers_available=35200slice_registers_fixed=0slice_registers_used=28slice_registers_util_percentage=0.08
fully_used_lut_ff_pairs_fixed=0.08fully_used_lut_ff_pairs_used=2lut_as_distributed_ram_fixed=0lut_as_distributed_ram_used=0
lut_as_logic_available=17600lut_as_logic_fixed=0lut_as_logic_used=5lut_as_logic_util_percentage=0.03
lut_as_memory_available=6000lut_as_memory_fixed=0lut_as_memory_used=0lut_as_memory_util_percentage=0.00
lut_as_shift_register_fixed=0lut_as_shift_register_used=0lut_ff_pairs_with_one_unused_flip_flop_fixed=0lut_ff_pairs_with_one_unused_flip_flop_used=2
lut_ff_pairs_with_one_unused_lut_output_fixed=2lut_ff_pairs_with_one_unused_lut_output_used=2lut_flip_flop_pairs_available=17600lut_flip_flop_pairs_fixed=0
lut_flip_flop_pairs_used=4lut_flip_flop_pairs_util_percentage=0.02slice_available=4400slice_fixed=0
slice_used=9slice_util_percentage=0.20slicel_fixed=0slicel_used=3
slicem_fixed=0slicem_used=6unique_control_sets_used=2using_o5_and_o6_fixed=2
using_o5_and_o6_used=2using_o5_output_only_fixed=2using_o5_output_only_used=0using_o6_output_only_fixed=0
using_o6_output_only_used=3
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
specific_feature
bscane2_available=4bscane2_fixed=0bscane2_used=0bscane2_util_percentage=0.00
capturee2_available=1capturee2_fixed=0capturee2_used=0capturee2_util_percentage=0.00
dna_port_available=1dna_port_fixed=0dna_port_used=0dna_port_util_percentage=0.00
efuse_usr_available=1efuse_usr_fixed=0efuse_usr_used=0efuse_usr_util_percentage=0.00
frame_ecce2_available=1frame_ecce2_fixed=0frame_ecce2_used=0frame_ecce2_util_percentage=0.00
icape2_available=2icape2_fixed=0icape2_used=0icape2_util_percentage=0.00
startupe2_available=1startupe2_fixed=0startupe2_used=0startupe2_util_percentage=0.00
xadc_available=1xadc_fixed=0xadc_used=0xadc_util_percentage=0.00
+

+ + + +
router
+ + + + + + + + + + + + + + + + + + + + + + + + + +
usage
actual_expansions=120390bogomips=5188bram18=0bram36=0
bufg=0bufr=0ctrls=2dsp=0
effort=2estimated_expansions=31824ff=28global_clocks=1
high_fanout_nets=0iob=12lut=5movable_instances=56
nets=60pins=209pll=0router_runtime=0.000000
router_timing_driven=1threads=4timing_constraints_exist=1
+

+ + + + +
synthesis
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
command_line_options
-assert=default::[not_specified]-bufg=default::12-cascade_dsp=default::auto-constrset=default::[not_specified]
-control_set_opt_threshold=default::auto-directive=default::default-fanout_limit=default::10000-flatten_hierarchy=default::rebuilt
-fsm_extraction=default::auto-gated_clock_conversion=default::off-generic=default::[not_specified]-include_dirs=default::[not_specified]
-keep_equivalent_registers=default::[not_specified]-max_bram=default::-1-max_bram_cascade_height=default::-1-max_dsp=default::-1
-max_uram=default::-1-max_uram_cascade_height=default::-1-mode=default::default-name=default::[not_specified]
-no_lc=default::[not_specified]-no_srlextract=default::[not_specified]-no_timing_driven=default::[not_specified]-part=xc7z010clg400-1
-resource_sharing=default::auto-retiming=default::[not_specified]-rtl=default::[not_specified]-rtl_skip_constraints=default::[not_specified]
-rtl_skip_ip=default::[not_specified]-seu_protect=default::none-sfcu=default::[not_specified]-shreg_min_size=default::3
-top=midpoint-verilog_define=default::[not_specified]
+
+ + + + + + +
usage
elapsed=00:00:18shls_ip=0memory_gain=405.352MBmemory_peak=1494.387MB
+

+ + diff --git a/sim/sim.runs/impl_1/usage_statistics_webtalk.xml b/sim/sim.runs/impl_1/usage_statistics_webtalk.xml new file mode 100644 index 0000000..f27c44f --- /dev/null +++ b/sim/sim.runs/impl_1/usage_statistics_webtalk.xml @@ -0,0 +1,404 @@ + + +
+
+ + + + + + + + + + + + + + + +
+
+ + + + + + +
+
+
+ + + + + + + + + + + +
+
+ +
+
+
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+
+ + + + +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+
+ + + + + + + + + + + + +
+
+ + + + + + + + + + + + + + +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+
+
+
+ + + + + + + + + + + + + + + + + + + + + + + +
+
+
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+
+ + + + +
+
+
+
+ + + + + + + + + +
+
+ + + + + + + + + +
+
+
+
+ + + + + + + + + + + + +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+
+
+ diff --git a/sim/sim.runs/impl_1/vivado.jou b/sim/sim.runs/impl_1/vivado.jou new file mode 100644 index 0000000..abbf37c --- /dev/null +++ b/sim/sim.runs/impl_1/vivado.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Vivado v2017.2 (64-bit) +# SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 +# IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 +# Start of session at: Wed Oct 25 21:41:47 2017 +# Process ID: 8072 +# Current directory: /home/jspear/Development/School/Comp_Arc/Lab2/sim/sim.runs/impl_1 +# Command line: vivado -log midpoint.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source midpoint.tcl -notrace +# Log file: /home/jspear/Development/School/Comp_Arc/Lab2/sim/sim.runs/impl_1/midpoint.vdi +# Journal file: /home/jspear/Development/School/Comp_Arc/Lab2/sim/sim.runs/impl_1/vivado.jou +#----------------------------------------------------------- +source midpoint.tcl -notrace diff --git a/sim/sim.runs/impl_1/vivado.pb b/sim/sim.runs/impl_1/vivado.pb new file mode 100644 index 0000000..7626436 Binary files /dev/null and b/sim/sim.runs/impl_1/vivado.pb differ diff --git a/sim/sim.runs/impl_1/vivado_29201.backup.jou b/sim/sim.runs/impl_1/vivado_29201.backup.jou new file mode 100644 index 0000000..5e42c18 --- /dev/null +++ b/sim/sim.runs/impl_1/vivado_29201.backup.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Vivado v2017.2 (64-bit) +# SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 +# IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 +# Start of session at: Wed Oct 25 21:33:23 2017 +# Process ID: 29201 +# Current directory: /home/jspear/Development/School/Comp_Arc/Lab2/sim/sim.runs/impl_1 +# Command line: vivado -log midpoint.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source midpoint.tcl -notrace +# Log file: /home/jspear/Development/School/Comp_Arc/Lab2/sim/sim.runs/impl_1/midpoint.vdi +# Journal file: /home/jspear/Development/School/Comp_Arc/Lab2/sim/sim.runs/impl_1/vivado.jou +#----------------------------------------------------------- +source midpoint.tcl -notrace diff --git a/sim/sim.runs/impl_1/vivado_5899.backup.jou b/sim/sim.runs/impl_1/vivado_5899.backup.jou new file mode 100644 index 0000000..a38d241 --- /dev/null +++ b/sim/sim.runs/impl_1/vivado_5899.backup.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Vivado v2017.2 (64-bit) +# SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 +# IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 +# Start of session at: Wed Oct 25 21:40:18 2017 +# Process ID: 5899 +# Current directory: /home/jspear/Development/School/Comp_Arc/Lab2/sim/sim.runs/impl_1 +# Command line: vivado -log midpoint.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source midpoint.tcl -notrace +# Log file: /home/jspear/Development/School/Comp_Arc/Lab2/sim/sim.runs/impl_1/midpoint.vdi +# Journal file: /home/jspear/Development/School/Comp_Arc/Lab2/sim/sim.runs/impl_1/vivado.jou +#----------------------------------------------------------- +source midpoint.tcl -notrace diff --git a/sim/sim.runs/impl_1/write_bitstream.pb b/sim/sim.runs/impl_1/write_bitstream.pb new file mode 100644 index 0000000..46ed19d Binary files /dev/null and b/sim/sim.runs/impl_1/write_bitstream.pb differ diff --git a/sim/sim.runs/synth_1/.Vivado_Synthesis.queue.rst b/sim/sim.runs/synth_1/.Vivado_Synthesis.queue.rst new file mode 100644 index 0000000..e69de29 diff --git a/sim/sim.runs/synth_1/.Xil/midpoint_propImpl.xdc b/sim/sim.runs/synth_1/.Xil/midpoint_propImpl.xdc new file mode 100644 index 0000000..b66ff90 --- /dev/null +++ b/sim/sim.runs/synth_1/.Xil/midpoint_propImpl.xdc @@ -0,0 +1,25 @@ +set_property SRC_FILE_INFO {cfile:/home/jspear/Development/School/Comp_Arc/Lab2/ZYBO_Master.xdc rfile:../../../../ZYBO_Master.xdc id:1} [current_design] +set_property src_info {type:XDC file:1 line:8 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN L16 IOSTANDARD LVCMOS33 } [get_ports { clk }]; #IO_L11P_T1_SRCC_35 Sch=sysclk +set_property src_info {type:XDC file:1 line:13 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN G15 IOSTANDARD LVCMOS33 } [get_ports { sw[0] }]; #IO_L19N_T3_VREF_35 Sch=SW0 +set_property src_info {type:XDC file:1 line:14 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN P15 IOSTANDARD LVCMOS33 } [get_ports { sw[1] }]; #IO_L24P_T3_34 Sch=SW1 +set_property src_info {type:XDC file:1 line:20 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN R18 IOSTANDARD LVCMOS33 } [get_ports { btn }]; #IO_L20N_T3_34 Sch=BTN0 +set_property src_info {type:XDC file:1 line:114 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN V12 IOSTANDARD LVCMOS33 } [get_ports { je[0] }]; #IO_L4P_T0_34 Sch=JE1 +set_property src_info {type:XDC file:1 line:115 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN W16 IOSTANDARD LVCMOS33 } [get_ports { je[1] }]; #IO_L18N_T2_34 Sch=JE2 +set_property src_info {type:XDC file:1 line:116 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN J15 IOSTANDARD LVCMOS33 } [get_ports { je[2] }]; #IO_25_35 Sch=JE3 +set_property src_info {type:XDC file:1 line:117 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN H15 IOSTANDARD LVCMOS33 } [get_ports { je[3] }]; #IO_L19P_T3_35 Sch=JE4 +set_property src_info {type:XDC file:1 line:118 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN V13 IOSTANDARD LVCMOS33 } [get_ports { je[4] }]; #IO_L3N_T0_DQS_34 Sch=JE7 +set_property src_info {type:XDC file:1 line:119 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN U17 IOSTANDARD LVCMOS33 } [get_ports { je[5] }]; #IO_L9N_T1_DQS_34 Sch=JE8 +set_property src_info {type:XDC file:1 line:120 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN T17 IOSTANDARD LVCMOS33 } [get_ports { je[6] }]; #IO_L20P_T3_34 Sch=JE9 +set_property src_info {type:XDC file:1 line:121 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN Y17 IOSTANDARD LVCMOS33 } [get_ports { je[7] }]; #IO_L7N_T1_34 Sch=JE10 diff --git a/sim/sim.runs/synth_1/.vivado.begin.rst b/sim/sim.runs/synth_1/.vivado.begin.rst new file mode 100644 index 0000000..34b284d --- /dev/null +++ b/sim/sim.runs/synth_1/.vivado.begin.rst @@ -0,0 +1,5 @@ + + + + + diff --git a/sim/sim.runs/synth_1/.vivado.end.rst b/sim/sim.runs/synth_1/.vivado.end.rst new file mode 100644 index 0000000..e69de29 diff --git a/sim/sim.runs/synth_1/ISEWrap.js b/sim/sim.runs/synth_1/ISEWrap.js new file mode 100755 index 0000000..8284d2d --- /dev/null +++ b/sim/sim.runs/synth_1/ISEWrap.js @@ -0,0 +1,244 @@ +// +// Vivado(TM) +// ISEWrap.js: Vivado Runs Script for WSH 5.1/5.6 +// Copyright 1986-1999, 2001-2013,2015 Xilinx, Inc. All Rights Reserved. +// + +// GLOBAL VARIABLES +var ISEShell = new ActiveXObject( "WScript.Shell" ); +var ISEFileSys = new ActiveXObject( "Scripting.FileSystemObject" ); +var ISERunDir = ""; +var ISELogFile = "runme.log"; +var ISELogFileStr = null; +var ISELogEcho = true; +var ISEOldVersionWSH = false; + + + +// BOOTSTRAP +ISEInit(); + + + +// +// ISE FUNCTIONS +// +function ISEInit() { + + // 1. RUN DIR setup + var ISEScrFP = WScript.ScriptFullName; + var ISEScrN = WScript.ScriptName; + ISERunDir = + ISEScrFP.substr( 0, ISEScrFP.length - ISEScrN.length - 1 ); + + // 2. LOG file setup + ISELogFileStr = ISEOpenFile( ISELogFile ); + + // 3. LOG echo? + var ISEScriptArgs = WScript.Arguments; + for ( var loopi=0; loopi> " + ISELogFile + " 2>&1"; + ISEExitCode = ISEShell.Run( ISECmdLine, 0, true ); + ISELogFileStr = ISEOpenFile( ISELogFile ); + + } else { // WSH 5.6 + + // LAUNCH! + ISEShell.CurrentDirectory = ISERunDir; + + // Redirect STDERR to STDOUT + ISECmdLine = "%comspec% /c " + ISECmdLine + " 2>&1"; + var ISEProcess = ISEShell.Exec( ISECmdLine ); + + // BEGIN file creation + var ISENetwork = WScript.CreateObject( "WScript.Network" ); + var ISEHost = ISENetwork.ComputerName; + var ISEUser = ISENetwork.UserName; + var ISEPid = ISEProcess.ProcessID; + var ISEBeginFile = ISEOpenFile( "." + ISEStep + ".begin.rst" ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.WriteLine( " " ); + ISEBeginFile.WriteLine( " " ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.Close(); + + var ISEOutStr = ISEProcess.StdOut; + var ISEErrStr = ISEProcess.StdErr; + + // WAIT for ISEStep to finish + while ( ISEProcess.Status == 0 ) { + + // dump stdout then stderr - feels a little arbitrary + while ( !ISEOutStr.AtEndOfStream ) { + ISEStdOut( ISEOutStr.ReadLine() ); + } + + WScript.Sleep( 100 ); + } + + ISEExitCode = ISEProcess.ExitCode; + } + + ISELogFileStr.Close(); + + // END/ERROR file creation + if ( ISEExitCode != 0 ) { + ISETouchFile( ISEStep, "error" ); + + } else { + ISETouchFile( ISEStep, "end" ); + } + + return ISEExitCode; +} + + +// +// UTILITIES +// +function ISEStdOut( ISELine ) { + + ISELogFileStr.WriteLine( ISELine ); + + if ( ISELogEcho ) { + WScript.StdOut.WriteLine( ISELine ); + } +} + +function ISEStdErr( ISELine ) { + + ISELogFileStr.WriteLine( ISELine ); + + if ( ISELogEcho ) { + WScript.StdErr.WriteLine( ISELine ); + } +} + +function ISETouchFile( ISERoot, ISEStatus ) { + + var ISETFile = + ISEOpenFile( "." + ISERoot + "." + ISEStatus + ".rst" ); + ISETFile.Close(); +} + +function ISEOpenFile( ISEFilename ) { + + // This function has been updated to deal with a problem seen in CR #870871. + // In that case the user runs a script that runs impl_1, and then turns around + // and runs impl_1 -to_step write_bitstream. That second run takes place in + // the same directory, which means we may hit some of the same files, and in + // particular, we will open the runme.log file. Even though this script closes + // the file (now), we see cases where a subsequent attempt to open the file + // fails. Perhaps the OS is slow to release the lock, or the disk comes into + // play? In any case, we try to work around this by first waiting if the file + // is already there for an arbitrary 5 seconds. Then we use a try-catch block + // and try to open the file 10 times with a one second delay after each attempt. + // Again, 10 is arbitrary. But these seem to stop the hang in CR #870871. + // If there is an unrecognized exception when trying to open the file, we output + // an error message and write details to an exception.log file. + var ISEFullPath = ISERunDir + "/" + ISEFilename; + if (ISEFileSys.FileExists(ISEFullPath)) { + // File is already there. This could be a problem. Wait in case it is still in use. + WScript.Sleep(5000); + } + var i; + for (i = 0; i < 10; ++i) { + try { + return ISEFileSys.OpenTextFile(ISEFullPath, 8, true); + } catch (exception) { + var error_code = exception.number & 0xFFFF; // The other bits are a facility code. + if (error_code == 52) { // 52 is bad file name or number. + // Wait a second and try again. + WScript.Sleep(1000); + continue; + } else { + WScript.StdErr.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath); + var exceptionFilePath = ISERunDir + "/exception.log"; + if (!ISEFileSys.FileExists(exceptionFilePath)) { + WScript.StdErr.WriteLine("See file " + exceptionFilePath + " for details."); + var exceptionFile = ISEFileSys.OpenTextFile(exceptionFilePath, 8, true); + exceptionFile.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath); + exceptionFile.WriteLine("\tException name: " + exception.name); + exceptionFile.WriteLine("\tException error code: " + error_code); + exceptionFile.WriteLine("\tException message: " + exception.message); + exceptionFile.Close(); + } + throw exception; + } + } + } + // If we reached this point, we failed to open the file after 10 attempts. + // We need to error out. + WScript.StdErr.WriteLine("ERROR: Failed to open file " + ISEFullPath); + WScript.Quit(1); +} diff --git a/sim/sim.runs/synth_1/ISEWrap.sh b/sim/sim.runs/synth_1/ISEWrap.sh new file mode 100755 index 0000000..e1a8f5d --- /dev/null +++ b/sim/sim.runs/synth_1/ISEWrap.sh @@ -0,0 +1,63 @@ +#!/bin/sh + +# +# Vivado(TM) +# ISEWrap.sh: Vivado Runs Script for UNIX +# Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved. +# + +HD_LOG=$1 +shift + +# CHECK for a STOP FILE +if [ -f .stop.rst ] +then +echo "" >> $HD_LOG +echo "*** Halting run - EA reset detected ***" >> $HD_LOG +echo "" >> $HD_LOG +exit 1 +fi + +ISE_STEP=$1 +shift + +# WRITE STEP HEADER to LOG +echo "" >> $HD_LOG +echo "*** Running $ISE_STEP" >> $HD_LOG +echo " with args $@" >> $HD_LOG +echo "" >> $HD_LOG + +# LAUNCH! +$ISE_STEP "$@" >> $HD_LOG 2>&1 & + +# BEGIN file creation +ISE_PID=$! +if [ X != X$HOSTNAME ] +then +ISE_HOST=$HOSTNAME #bash +else +ISE_HOST=$HOST #csh +fi +ISE_USER=$USER +ISE_BEGINFILE=.$ISE_STEP.begin.rst +/bin/touch $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE +echo " " >> $ISE_BEGINFILE +echo " " >> $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE + +# WAIT for ISEStep to finish +wait $ISE_PID + +# END/ERROR file creation +RETVAL=$? +if [ $RETVAL -eq 0 ] +then + /bin/touch .$ISE_STEP.end.rst +else + /bin/touch .$ISE_STEP.error.rst +fi + +exit $RETVAL + diff --git a/sim/sim.runs/synth_1/gen_run.xml b/sim/sim.runs/synth_1/gen_run.xml new file mode 100644 index 0000000..e9e4d9a --- /dev/null +++ b/sim/sim.runs/synth_1/gen_run.xml @@ -0,0 +1,44 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Vivado Synthesis Defaults + + + + diff --git a/sim/sim.runs/synth_1/htr.txt b/sim/sim.runs/synth_1/htr.txt new file mode 100644 index 0000000..8cf3c97 --- /dev/null +++ b/sim/sim.runs/synth_1/htr.txt @@ -0,0 +1,9 @@ +# +# Vivado(TM) +# htr.txt: a Vivado-generated description of how-to-repeat the +# the basic steps of a run. Note that runme.bat/sh needs +# to be invoked for Vivado to track run status. +# Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. +# + +vivado -log midpoint.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source midpoint.tcl diff --git a/sim/sim.runs/synth_1/midpoint.dcp b/sim/sim.runs/synth_1/midpoint.dcp new file mode 100644 index 0000000..b511e83 Binary files /dev/null and b/sim/sim.runs/synth_1/midpoint.dcp differ diff --git a/sim/sim.runs/synth_1/midpoint.tcl b/sim/sim.runs/synth_1/midpoint.tcl new file mode 100644 index 0000000..29d6969 --- /dev/null +++ b/sim/sim.runs/synth_1/midpoint.tcl @@ -0,0 +1,35 @@ +# +# Synthesis run script generated by Vivado +# + +set_param xicom.use_bs_reader 1 +create_project -in_memory -part xc7z010clg400-1 + +set_param project.singleFileAddWarning.threshold 0 +set_param project.compositeFile.enableAutoGeneration 0 +set_param synth.vivado.isSynthRun true +set_property webtalk.parent_dir /home/jspear/Development/School/Comp_Arc/Lab2/sim/sim.cache/wt [current_project] +set_property parent.project_path /home/jspear/Development/School/Comp_Arc/Lab2/sim/sim.xpr [current_project] +set_property default_lib xil_defaultlib [current_project] +set_property target_language Verilog [current_project] +set_property ip_output_repo /home/jspear/Development/School/Comp_Arc/Lab2/sim/sim.cache/ip [current_project] +set_property ip_cache_permissions {read write} [current_project] +read_verilog -library xil_defaultlib /home/jspear/Development/School/Comp_Arc/Lab2/midpoint.v +# Mark all dcp files as not used in implementation to prevent them from being +# stitched into the results of this synthesis run. Any black boxes in the +# design are intentionally left as such for best results. Dcp files will be +# stitched into the design at a later time, either when this synthesis run is +# opened, or when it is stitched into a dependent implementation run. +foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] { + set_property used_in_implementation false $dcp +} +read_xdc /home/jspear/Development/School/Comp_Arc/Lab2/ZYBO_Master.xdc +set_property used_in_implementation false [get_files /home/jspear/Development/School/Comp_Arc/Lab2/ZYBO_Master.xdc] + + +synth_design -top midpoint -part xc7z010clg400-1 + + +write_checkpoint -force -noxdef midpoint.dcp + +catch { report_utilization -file midpoint_utilization_synth.rpt -pb midpoint_utilization_synth.pb } diff --git a/sim/sim.runs/synth_1/midpoint.vds b/sim/sim.runs/synth_1/midpoint.vds new file mode 100644 index 0000000..663d67f --- /dev/null +++ b/sim/sim.runs/synth_1/midpoint.vds @@ -0,0 +1,289 @@ +#----------------------------------------------------------- +# Vivado v2017.2 (64-bit) +# SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 +# IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 +# Start of session at: Wed Oct 25 21:39:45 2017 +# Process ID: 5002 +# Current directory: /home/jspear/Development/School/Comp_Arc/Lab2/sim/sim.runs/synth_1 +# Command line: vivado -log midpoint.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source midpoint.tcl +# Log file: /home/jspear/Development/School/Comp_Arc/Lab2/sim/sim.runs/synth_1/midpoint.vds +# Journal file: /home/jspear/Development/School/Comp_Arc/Lab2/sim/sim.runs/synth_1/vivado.jou +#----------------------------------------------------------- +source midpoint.tcl -notrace +Command: synth_design -top midpoint -part xc7z010clg400-1 +Starting synth_design +Attempting to get a license for feature 'Synthesis' and/or device 'xc7z010-clg400' +INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z010-clg400' +INFO: Launching helper process for spawning children vivado processes +INFO: Helper process launched with PID 5151 +WARNING: [Synth 8-2292] literal value truncated to fit in 2 bits [/home/jspear/Development/School/Comp_Arc/Lab2/midpoint.v:18] +--------------------------------------------------------------------------------- +Starting RTL Elaboration : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 1147.863 ; gain = 46.246 ; free physical = 10484 ; free virtual = 20716 +--------------------------------------------------------------------------------- +INFO: [Synth 8-638] synthesizing module 'midpoint' [/home/jspear/Development/School/Comp_Arc/Lab2/midpoint.v:6] +INFO: [Synth 8-638] synthesizing module 'inputconditioner' [/home/jspear/Development/School/Comp_Arc/Lab2/inputconditioner.v:8] + Parameter wait_time bound to: 3 - type: integer +INFO: [Synth 8-256] done synthesizing module 'inputconditioner' (1#1) [/home/jspear/Development/School/Comp_Arc/Lab2/inputconditioner.v:8] +INFO: [Synth 8-638] synthesizing module 'shiftregister' [/home/jspear/Development/School/Comp_Arc/Lab2/shiftregister.v:9] + Parameter width bound to: 8 - type: integer +INFO: [Synth 8-256] done synthesizing module 'shiftregister' (2#1) [/home/jspear/Development/School/Comp_Arc/Lab2/shiftregister.v:9] +INFO: [Synth 8-256] done synthesizing module 'midpoint' (3#1) [/home/jspear/Development/School/Comp_Arc/Lab2/midpoint.v:6] +--------------------------------------------------------------------------------- +Finished RTL Elaboration : Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 1172.121 ; gain = 70.504 ; free physical = 10501 ; free virtual = 20733 +--------------------------------------------------------------------------------- + +Report Check Netlist: ++------+------------------+-------+---------+-------+------------------+ +| |Item |Errors |Warnings |Status |Description | ++------+------------------+-------+---------+-------+------------------+ +|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | ++------+------------------+-------+---------+-------+------------------+ +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 1172.121 ; gain = 70.504 ; free physical = 10501 ; free virtual = 20733 +--------------------------------------------------------------------------------- +INFO: [Device 21-403] Loading part xc7z010clg400-1 +INFO: [Project 1-570] Preparing netlist for logic optimization + +Processing XDC Constraints +Initializing timing engine +Parsing XDC File [/home/jspear/Development/School/Comp_Arc/Lab2/ZYBO_Master.xdc] +Finished Parsing XDC File [/home/jspear/Development/School/Comp_Arc/Lab2/ZYBO_Master.xdc] +INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/jspear/Development/School/Comp_Arc/Lab2/ZYBO_Master.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/midpoint_propImpl.xdc]. +Resolution: To avoid this warning, move constraints listed in [.Xil/midpoint_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. +Completed Processing XDC Constraints + +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1486.371 ; gain = 0.000 ; free physical = 10264 ; free virtual = 20497 +--------------------------------------------------------------------------------- +Finished Constraint Validation : Time (s): cpu = 00:00:12 ; elapsed = 00:00:12 . Memory (MB): peak = 1486.375 ; gain = 384.758 ; free physical = 10337 ; free virtual = 20569 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Loading Part and Timing Information +--------------------------------------------------------------------------------- +Loading part: xc7z010clg400-1 +--------------------------------------------------------------------------------- +Finished Loading Part and Timing Information : Time (s): cpu = 00:00:12 ; elapsed = 00:00:12 . Memory (MB): peak = 1486.375 ; gain = 384.758 ; free physical = 10337 ; free virtual = 20569 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Applying 'set_property' XDC Constraints +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:12 ; elapsed = 00:00:12 . Memory (MB): peak = 1486.375 ; gain = 384.758 ; free physical = 10338 ; free virtual = 20571 +--------------------------------------------------------------------------------- +INFO: [Synth 8-5544] ROM "positiveedge" won't be mapped to Block RAM because address size (3) smaller than threshold (5) +INFO: [Synth 8-5544] ROM "conditioned" won't be mapped to Block RAM because address size (3) smaller than threshold (5) +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:12 ; elapsed = 00:00:12 . Memory (MB): peak = 1486.375 ; gain = 384.758 ; free physical = 10331 ; free virtual = 20564 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start RTL Component Statistics +--------------------------------------------------------------------------------- +Detailed RTL Component Info : ++---Registers : + 8 Bit Registers := 1 + 3 Bit Registers := 3 + 1 Bit Registers := 9 ++---Muxes : + 2 Input 8 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 16 +--------------------------------------------------------------------------------- +Finished RTL Component Statistics +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start RTL Hierarchical Component Statistics +--------------------------------------------------------------------------------- +Hierarchical RTL Component report +Module inputconditioner +Detailed RTL Component Info : ++---Registers : + 3 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 1 Bit Muxes := 5 +Module shiftregister +Detailed RTL Component Info : ++---Registers : + 8 Bit Registers := 1 ++---Muxes : + 2 Input 8 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 1 +--------------------------------------------------------------------------------- +Finished RTL Hierarchical Component Statistics +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Part Resource Summary +--------------------------------------------------------------------------------- +Part Resources: +DSPs: 80 (col length:40) +BRAMs: 120 (col length: RAMB18 40 RAMB36 20) +--------------------------------------------------------------------------------- +Finished Part Resource Summary +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Cross Boundary and Area Optimization +--------------------------------------------------------------------------------- +WARNING: [Synth 8-6014] Unused sequential element i1/positiveedge_reg was removed. [/home/jspear/Development/School/Comp_Arc/Lab2/inputconditioner.v:24] +WARNING: [Synth 8-6014] Unused sequential element i2/positiveedge_reg was removed. [/home/jspear/Development/School/Comp_Arc/Lab2/inputconditioner.v:24] +WARNING: [Synth 8-6014] Unused sequential element i2/negativeedge_reg was removed. [/home/jspear/Development/School/Comp_Arc/Lab2/inputconditioner.v:34] +WARNING: [Synth 8-6014] Unused sequential element i3/negativeedge_reg was removed. [/home/jspear/Development/School/Comp_Arc/Lab2/inputconditioner.v:34] +--------------------------------------------------------------------------------- +Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:12 ; elapsed = 00:00:12 . Memory (MB): peak = 1486.375 ; gain = 384.758 ; free physical = 10321 ; free virtual = 20554 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Applying XDC Timing Constraints +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:18 ; elapsed = 00:00:18 . Memory (MB): peak = 1486.375 ; gain = 384.758 ; free physical = 10195 ; free virtual = 20426 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Timing Optimization +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Timing Optimization : Time (s): cpu = 00:00:18 ; elapsed = 00:00:18 . Memory (MB): peak = 1486.375 ; gain = 384.758 ; free physical = 10195 ; free virtual = 20426 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Technology Mapping +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Technology Mapping : Time (s): cpu = 00:00:18 ; elapsed = 00:00:18 . Memory (MB): peak = 1494.379 ; gain = 392.762 ; free physical = 10194 ; free virtual = 20424 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished IO Insertion : Time (s): cpu = 00:00:18 ; elapsed = 00:00:18 . Memory (MB): peak = 1494.379 ; gain = 392.762 ; free physical = 10194 ; free virtual = 20424 +--------------------------------------------------------------------------------- + +Report Check Netlist: ++------+------------------+-------+---------+-------+------------------+ +| |Item |Errors |Warnings |Status |Description | ++------+------------------+-------+---------+-------+------------------+ +|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | ++------+------------------+-------+---------+-------+------------------+ +--------------------------------------------------------------------------------- +Start Renaming Generated Instances +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Instances : Time (s): cpu = 00:00:18 ; elapsed = 00:00:18 . Memory (MB): peak = 1494.379 ; gain = 392.762 ; free physical = 10194 ; free virtual = 20424 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Rebuilding User Hierarchy +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:18 ; elapsed = 00:00:18 . Memory (MB): peak = 1494.379 ; gain = 392.762 ; free physical = 10194 ; free virtual = 20424 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Ports +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Ports : Time (s): cpu = 00:00:18 ; elapsed = 00:00:18 . Memory (MB): peak = 1494.379 ; gain = 392.762 ; free physical = 10194 ; free virtual = 20424 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:00:18 ; elapsed = 00:00:18 . Memory (MB): peak = 1494.379 ; gain = 392.762 ; free physical = 10194 ; free virtual = 20424 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Nets +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Nets : Time (s): cpu = 00:00:18 ; elapsed = 00:00:18 . Memory (MB): peak = 1494.379 ; gain = 392.762 ; free physical = 10194 ; free virtual = 20424 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Writing Synthesis Report +--------------------------------------------------------------------------------- + +Report BlackBoxes: ++-+--------------+----------+ +| |BlackBox name |Instances | ++-+--------------+----------+ ++-+--------------+----------+ + +Report Cell Usage: ++------+-----+------+ +| |Cell |Count | ++------+-----+------+ +|1 |BUFG | 1| +|2 |LUT2 | 1| +|3 |LUT4 | 4| +|4 |LUT5 | 2| +|5 |FDRE | 22| +|6 |IBUF | 4| +|7 |OBUF | 8| ++------+-----+------+ + +Report Instance Areas: ++------+---------+-------------------+------+ +| |Instance |Module |Cells | ++------+---------+-------------------+------+ +|1 |top | | 42| +|2 | i1 |inputconditioner | 8| +|3 | i2 |inputconditioner_0 | 5| +|4 | i3 |inputconditioner_1 | 7| +|5 | shft |shiftregister | 9| ++------+---------+-------------------+------+ +--------------------------------------------------------------------------------- +Finished Writing Synthesis Report : Time (s): cpu = 00:00:18 ; elapsed = 00:00:18 . Memory (MB): peak = 1494.379 ; gain = 392.762 ; free physical = 10194 ; free virtual = 20424 +--------------------------------------------------------------------------------- +Synthesis finished with 0 errors, 0 critical warnings and 4 warnings. +Synthesis Optimization Runtime : Time (s): cpu = 00:00:14 ; elapsed = 00:00:14 . Memory (MB): peak = 1494.379 ; gain = 78.512 ; free physical = 10254 ; free virtual = 20484 +Synthesis Optimization Complete : Time (s): cpu = 00:00:18 ; elapsed = 00:00:18 . Memory (MB): peak = 1494.387 ; gain = 392.762 ; free physical = 10254 ; free virtual = 20484 +INFO: [Project 1-571] Translating synthesized netlist +INFO: [Netlist 29-17] Analyzing 4 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +INFO: [Project 1-570] Preparing netlist for logic optimization +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +19 Infos, 5 Warnings, 0 Critical Warnings and 0 Errors encountered. +synth_design completed successfully +synth_design: Time (s): cpu = 00:00:19 ; elapsed = 00:00:19 . Memory (MB): peak = 1494.387 ; gain = 405.352 ; free physical = 10222 ; free virtual = 20453 +INFO: [Common 17-1381] The checkpoint '/home/jspear/Development/School/Comp_Arc/Lab2/sim/sim.runs/synth_1/midpoint.dcp' has been generated. +report_utilization: Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.10 . Memory (MB): peak = 1518.395 ; gain = 0.000 ; free physical = 10223 ; free virtual = 20454 +INFO: [Common 17-206] Exiting Vivado at Wed Oct 25 21:40:12 2017... diff --git a/sim/sim.runs/synth_1/midpoint_utilization_synth.pb b/sim/sim.runs/synth_1/midpoint_utilization_synth.pb new file mode 100644 index 0000000..216973d Binary files /dev/null and b/sim/sim.runs/synth_1/midpoint_utilization_synth.pb differ diff --git a/sim/sim.runs/synth_1/midpoint_utilization_synth.rpt b/sim/sim.runs/synth_1/midpoint_utilization_synth.rpt new file mode 100644 index 0000000..0b56ffe --- /dev/null +++ b/sim/sim.runs/synth_1/midpoint_utilization_synth.rpt @@ -0,0 +1,174 @@ +Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. +----------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2017.2 (lin64) Build 1909853 Thu Jun 15 18:39:10 MDT 2017 +| Date : Wed Oct 25 21:40:12 2017 +| Host : Kreyshawn running 64-bit Ubuntu 14.04.5 LTS +| Command : report_utilization -file midpoint_utilization_synth.rpt -pb midpoint_utilization_synth.pb +| Design : midpoint +| Device : 7z010clg400-1 +| Design State : Synthesized +----------------------------------------------------------------------------------------------------------- + +Utilization Design Information + +Table of Contents +----------------- +1. Slice Logic +1.1 Summary of Registers by Type +2. Memory +3. DSP +4. IO and GT Specific +5. Clocking +6. Specific Feature +7. Primitives +8. Black Boxes +9. Instantiated Netlists + +1. Slice Logic +-------------- + ++-------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-------------------------+------+-------+-----------+-------+ +| Slice LUTs* | 5 | 0 | 17600 | 0.03 | +| LUT as Logic | 5 | 0 | 17600 | 0.03 | +| LUT as Memory | 0 | 0 | 6000 | 0.00 | +| Slice Registers | 22 | 0 | 35200 | 0.06 | +| Register as Flip Flop | 22 | 0 | 35200 | 0.06 | +| Register as Latch | 0 | 0 | 35200 | 0.00 | +| F7 Muxes | 0 | 0 | 8800 | 0.00 | +| F8 Muxes | 0 | 0 | 4400 | 0.00 | ++-------------------------+------+-------+-----------+-------+ +* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count. + + +1.1 Summary of Registers by Type +-------------------------------- + ++-------+--------------+-------------+--------------+ +| Total | Clock Enable | Synchronous | Asynchronous | ++-------+--------------+-------------+--------------+ +| 0 | _ | - | - | +| 0 | _ | - | Set | +| 0 | _ | - | Reset | +| 0 | _ | Set | - | +| 0 | _ | Reset | - | +| 0 | Yes | - | - | +| 0 | Yes | - | Set | +| 0 | Yes | - | Reset | +| 0 | Yes | Set | - | +| 22 | Yes | Reset | - | ++-------+--------------+-------------+--------------+ + + +2. Memory +--------- + ++----------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++----------------+------+-------+-----------+-------+ +| Block RAM Tile | 0 | 0 | 60 | 0.00 | +| RAMB36/FIFO* | 0 | 0 | 60 | 0.00 | +| RAMB18 | 0 | 0 | 120 | 0.00 | ++----------------+------+-------+-----------+-------+ +* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1 + + +3. DSP +------ + ++-----------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-----------+------+-------+-----------+-------+ +| DSPs | 0 | 0 | 80 | 0.00 | ++-----------+------+-------+-----------+-------+ + + +4. IO and GT Specific +--------------------- + ++-----------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-----------------------------+------+-------+-----------+-------+ +| Bonded IOB | 12 | 0 | 100 | 12.00 | +| Bonded IPADs | 0 | 0 | 2 | 0.00 | +| Bonded IOPADs | 0 | 0 | 130 | 0.00 | +| PHY_CONTROL | 0 | 0 | 2 | 0.00 | +| PHASER_REF | 0 | 0 | 2 | 0.00 | +| OUT_FIFO | 0 | 0 | 8 | 0.00 | +| IN_FIFO | 0 | 0 | 8 | 0.00 | +| IDELAYCTRL | 0 | 0 | 2 | 0.00 | +| IBUFDS | 0 | 0 | 96 | 0.00 | +| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 8 | 0.00 | +| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 8 | 0.00 | +| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 100 | 0.00 | +| ILOGIC | 0 | 0 | 100 | 0.00 | +| OLOGIC | 0 | 0 | 100 | 0.00 | ++-----------------------------+------+-------+-----------+-------+ + + +5. Clocking +----------- + ++------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++------------+------+-------+-----------+-------+ +| BUFGCTRL | 1 | 0 | 32 | 3.13 | +| BUFIO | 0 | 0 | 8 | 0.00 | +| MMCME2_ADV | 0 | 0 | 2 | 0.00 | +| PLLE2_ADV | 0 | 0 | 2 | 0.00 | +| BUFMRCE | 0 | 0 | 4 | 0.00 | +| BUFHCE | 0 | 0 | 48 | 0.00 | +| BUFR | 0 | 0 | 8 | 0.00 | ++------------+------+-------+-----------+-------+ + + +6. Specific Feature +------------------- + ++-------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-------------+------+-------+-----------+-------+ +| BSCANE2 | 0 | 0 | 4 | 0.00 | +| CAPTUREE2 | 0 | 0 | 1 | 0.00 | +| DNA_PORT | 0 | 0 | 1 | 0.00 | +| EFUSE_USR | 0 | 0 | 1 | 0.00 | +| FRAME_ECCE2 | 0 | 0 | 1 | 0.00 | +| ICAPE2 | 0 | 0 | 2 | 0.00 | +| STARTUPE2 | 0 | 0 | 1 | 0.00 | +| XADC | 0 | 0 | 1 | 0.00 | ++-------------+------+-------+-----------+-------+ + + +7. Primitives +------------- + ++----------+------+---------------------+ +| Ref Name | Used | Functional Category | ++----------+------+---------------------+ +| FDRE | 22 | Flop & Latch | +| OBUF | 8 | IO | +| LUT4 | 4 | LUT | +| IBUF | 4 | IO | +| LUT5 | 2 | LUT | +| LUT2 | 1 | LUT | +| BUFG | 1 | Clock | ++----------+------+---------------------+ + + +8. Black Boxes +-------------- + ++----------+------+ +| Ref Name | Used | ++----------+------+ + + +9. Instantiated Netlists +------------------------ + ++----------+------+ +| Ref Name | Used | ++----------+------+ + + diff --git a/sim/sim.runs/synth_1/project.wdf b/sim/sim.runs/synth_1/project.wdf new file mode 100644 index 0000000..50d189a --- /dev/null +++ b/sim/sim.runs/synth_1/project.wdf @@ -0,0 +1,31 @@ +version:1 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:737263736574636f756e74:31:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f6e73747261696e74736574636f756e74:31:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64657369676e6d6f6465:52544c:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73796e7468657369737374726174656779:56697661646f2053796e7468657369732044656661756c7473:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:696d706c7374726174656779:56697661646f20496d706c656d656e746174696f6e2044656661756c7473:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:63757272656e7473796e74686573697372756e:73796e74685f31:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:63757272656e74696d706c72756e:696d706c5f31:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:746f74616c73796e74686573697372756e73:31:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:746f74616c696d706c72756e73:31:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f72655f636f6e7461696e6572:66616c7365:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73696d756c61746f725f6c616e6775616765:4d69786564:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:7461726765745f6c616e6775616765:566572696c6f67:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64656661756c745f6c696272617279:78696c5f64656661756c746c6962:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:7461726765745f73696d756c61746f72:5853696d:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f7873696d:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f6d6f64656c73696d:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f717565737461:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f696573:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f766373:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f72697669657261:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f61637469766568646c:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f7873696d:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f6d6f64656c73696d:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f717565737461:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f696573:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f766373:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f72697669657261:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f61637469766568646c:30:00:00 +5f5f48494444454e5f5f:5f5f48494444454e5f5f:50726f6a65637455554944:6238616665393763616261623435353261333030613663643238356561386437:506172656e742050412070726f6a656374204944:00 +eof:2855082633 diff --git a/sim/sim.runs/synth_1/rundef.js b/sim/sim.runs/synth_1/rundef.js new file mode 100644 index 0000000..1a0e5d5 --- /dev/null +++ b/sim/sim.runs/synth_1/rundef.js @@ -0,0 +1,40 @@ +// +// Vivado(TM) +// rundef.js: a Vivado-generated Runs Script for WSH 5.1/5.6 +// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. +// + +echo "This script was generated under a different operating system." +echo "Please update the PATH variable below, before executing this script" +exit + +var WshShell = new ActiveXObject( "WScript.Shell" ); +var ProcEnv = WshShell.Environment( "Process" ); +var PathVal = ProcEnv("PATH"); +if ( PathVal.length == 0 ) { + PathVal = "/opt/Xilinx/Vivado/2017.2/ids_lite/ISE/bin/lin64;/opt/Xilinx/Vivado/2017.2/ids_lite/ISE/lib/lin64;/opt/Xilinx/Vivado/2017.2/bin;"; +} else { + PathVal = "/opt/Xilinx/Vivado/2017.2/ids_lite/ISE/bin/lin64;/opt/Xilinx/Vivado/2017.2/ids_lite/ISE/lib/lin64;/opt/Xilinx/Vivado/2017.2/bin;" + PathVal; +} + +ProcEnv("PATH") = PathVal; + +var RDScrFP = WScript.ScriptFullName; +var RDScrN = WScript.ScriptName; +var RDScrDir = RDScrFP.substr( 0, RDScrFP.length - RDScrN.length - 1 ); +var ISEJScriptLib = RDScrDir + "/ISEWrap.js"; +eval( EAInclude(ISEJScriptLib) ); + + +ISEStep( "vivado", + "-log midpoint.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source midpoint.tcl" ); + + + +function EAInclude( EAInclFilename ) { + var EAFso = new ActiveXObject( "Scripting.FileSystemObject" ); + var EAInclFile = EAFso.OpenTextFile( EAInclFilename ); + var EAIFContents = EAInclFile.ReadAll(); + EAInclFile.Close(); + return EAIFContents; +} diff --git a/sim/sim.runs/synth_1/runme.bat b/sim/sim.runs/synth_1/runme.bat new file mode 100644 index 0000000..220ba68 --- /dev/null +++ b/sim/sim.runs/synth_1/runme.bat @@ -0,0 +1,11 @@ +@echo off + +rem Vivado (TM) +rem runme.bat: a Vivado-generated Script +rem Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. + + +set HD_SDIR=%~dp0 +cd /d "%HD_SDIR%" +set PATH=%SYSTEMROOT%\system32;%PATH% +cscript /nologo /E:JScript "%HD_SDIR%\rundef.js" %* diff --git a/sim/sim.runs/synth_1/runme.log b/sim/sim.runs/synth_1/runme.log new file mode 100644 index 0000000..0c0b94b --- /dev/null +++ b/sim/sim.runs/synth_1/runme.log @@ -0,0 +1,288 @@ + +*** Running vivado + with args -log midpoint.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source midpoint.tcl + + +****** Vivado v2017.2 (64-bit) + **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 + **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 + ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. + +source midpoint.tcl -notrace +Command: synth_design -top midpoint -part xc7z010clg400-1 +Starting synth_design +Attempting to get a license for feature 'Synthesis' and/or device 'xc7z010-clg400' +INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z010-clg400' +INFO: Launching helper process for spawning children vivado processes +INFO: Helper process launched with PID 5151 +WARNING: [Synth 8-2292] literal value truncated to fit in 2 bits [/home/jspear/Development/School/Comp_Arc/Lab2/midpoint.v:18] +--------------------------------------------------------------------------------- +Starting RTL Elaboration : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 1147.863 ; gain = 46.246 ; free physical = 10484 ; free virtual = 20716 +--------------------------------------------------------------------------------- +INFO: [Synth 8-638] synthesizing module 'midpoint' [/home/jspear/Development/School/Comp_Arc/Lab2/midpoint.v:6] +INFO: [Synth 8-638] synthesizing module 'inputconditioner' [/home/jspear/Development/School/Comp_Arc/Lab2/inputconditioner.v:8] + Parameter wait_time bound to: 3 - type: integer +INFO: [Synth 8-256] done synthesizing module 'inputconditioner' (1#1) [/home/jspear/Development/School/Comp_Arc/Lab2/inputconditioner.v:8] +INFO: [Synth 8-638] synthesizing module 'shiftregister' [/home/jspear/Development/School/Comp_Arc/Lab2/shiftregister.v:9] + Parameter width bound to: 8 - type: integer +INFO: [Synth 8-256] done synthesizing module 'shiftregister' (2#1) [/home/jspear/Development/School/Comp_Arc/Lab2/shiftregister.v:9] +INFO: [Synth 8-256] done synthesizing module 'midpoint' (3#1) [/home/jspear/Development/School/Comp_Arc/Lab2/midpoint.v:6] +--------------------------------------------------------------------------------- +Finished RTL Elaboration : Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 1172.121 ; gain = 70.504 ; free physical = 10501 ; free virtual = 20733 +--------------------------------------------------------------------------------- + +Report Check Netlist: ++------+------------------+-------+---------+-------+------------------+ +| |Item |Errors |Warnings |Status |Description | ++------+------------------+-------+---------+-------+------------------+ +|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | ++------+------------------+-------+---------+-------+------------------+ +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 1172.121 ; gain = 70.504 ; free physical = 10501 ; free virtual = 20733 +--------------------------------------------------------------------------------- +INFO: [Device 21-403] Loading part xc7z010clg400-1 +INFO: [Project 1-570] Preparing netlist for logic optimization + +Processing XDC Constraints +Initializing timing engine +Parsing XDC File [/home/jspear/Development/School/Comp_Arc/Lab2/ZYBO_Master.xdc] +Finished Parsing XDC File [/home/jspear/Development/School/Comp_Arc/Lab2/ZYBO_Master.xdc] +INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/jspear/Development/School/Comp_Arc/Lab2/ZYBO_Master.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/midpoint_propImpl.xdc]. +Resolution: To avoid this warning, move constraints listed in [.Xil/midpoint_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. +Completed Processing XDC Constraints + +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1486.371 ; gain = 0.000 ; free physical = 10264 ; free virtual = 20497 +--------------------------------------------------------------------------------- +Finished Constraint Validation : Time (s): cpu = 00:00:12 ; elapsed = 00:00:12 . Memory (MB): peak = 1486.375 ; gain = 384.758 ; free physical = 10337 ; free virtual = 20569 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Loading Part and Timing Information +--------------------------------------------------------------------------------- +Loading part: xc7z010clg400-1 +--------------------------------------------------------------------------------- +Finished Loading Part and Timing Information : Time (s): cpu = 00:00:12 ; elapsed = 00:00:12 . Memory (MB): peak = 1486.375 ; gain = 384.758 ; free physical = 10337 ; free virtual = 20569 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Applying 'set_property' XDC Constraints +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:12 ; elapsed = 00:00:12 . Memory (MB): peak = 1486.375 ; gain = 384.758 ; free physical = 10338 ; free virtual = 20571 +--------------------------------------------------------------------------------- +INFO: [Synth 8-5544] ROM "positiveedge" won't be mapped to Block RAM because address size (3) smaller than threshold (5) +INFO: [Synth 8-5544] ROM "conditioned" won't be mapped to Block RAM because address size (3) smaller than threshold (5) +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:12 ; elapsed = 00:00:12 . Memory (MB): peak = 1486.375 ; gain = 384.758 ; free physical = 10331 ; free virtual = 20564 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start RTL Component Statistics +--------------------------------------------------------------------------------- +Detailed RTL Component Info : ++---Registers : + 8 Bit Registers := 1 + 3 Bit Registers := 3 + 1 Bit Registers := 9 ++---Muxes : + 2 Input 8 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 16 +--------------------------------------------------------------------------------- +Finished RTL Component Statistics +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start RTL Hierarchical Component Statistics +--------------------------------------------------------------------------------- +Hierarchical RTL Component report +Module inputconditioner +Detailed RTL Component Info : ++---Registers : + 3 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 1 Bit Muxes := 5 +Module shiftregister +Detailed RTL Component Info : ++---Registers : + 8 Bit Registers := 1 ++---Muxes : + 2 Input 8 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 1 +--------------------------------------------------------------------------------- +Finished RTL Hierarchical Component Statistics +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Part Resource Summary +--------------------------------------------------------------------------------- +Part Resources: +DSPs: 80 (col length:40) +BRAMs: 120 (col length: RAMB18 40 RAMB36 20) +--------------------------------------------------------------------------------- +Finished Part Resource Summary +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Cross Boundary and Area Optimization +--------------------------------------------------------------------------------- +WARNING: [Synth 8-6014] Unused sequential element i1/positiveedge_reg was removed. [/home/jspear/Development/School/Comp_Arc/Lab2/inputconditioner.v:24] +WARNING: [Synth 8-6014] Unused sequential element i2/positiveedge_reg was removed. [/home/jspear/Development/School/Comp_Arc/Lab2/inputconditioner.v:24] +WARNING: [Synth 8-6014] Unused sequential element i2/negativeedge_reg was removed. [/home/jspear/Development/School/Comp_Arc/Lab2/inputconditioner.v:34] +WARNING: [Synth 8-6014] Unused sequential element i3/negativeedge_reg was removed. [/home/jspear/Development/School/Comp_Arc/Lab2/inputconditioner.v:34] +--------------------------------------------------------------------------------- +Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:12 ; elapsed = 00:00:12 . Memory (MB): peak = 1486.375 ; gain = 384.758 ; free physical = 10321 ; free virtual = 20554 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Applying XDC Timing Constraints +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:18 ; elapsed = 00:00:18 . Memory (MB): peak = 1486.375 ; gain = 384.758 ; free physical = 10195 ; free virtual = 20426 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Timing Optimization +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Timing Optimization : Time (s): cpu = 00:00:18 ; elapsed = 00:00:18 . Memory (MB): peak = 1486.375 ; gain = 384.758 ; free physical = 10195 ; free virtual = 20426 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Technology Mapping +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Technology Mapping : Time (s): cpu = 00:00:18 ; elapsed = 00:00:18 . Memory (MB): peak = 1494.379 ; gain = 392.762 ; free physical = 10194 ; free virtual = 20424 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished IO Insertion : Time (s): cpu = 00:00:18 ; elapsed = 00:00:18 . Memory (MB): peak = 1494.379 ; gain = 392.762 ; free physical = 10194 ; free virtual = 20424 +--------------------------------------------------------------------------------- + +Report Check Netlist: ++------+------------------+-------+---------+-------+------------------+ +| |Item |Errors |Warnings |Status |Description | ++------+------------------+-------+---------+-------+------------------+ +|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | ++------+------------------+-------+---------+-------+------------------+ +--------------------------------------------------------------------------------- +Start Renaming Generated Instances +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Instances : Time (s): cpu = 00:00:18 ; elapsed = 00:00:18 . Memory (MB): peak = 1494.379 ; gain = 392.762 ; free physical = 10194 ; free virtual = 20424 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Rebuilding User Hierarchy +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:18 ; elapsed = 00:00:18 . Memory (MB): peak = 1494.379 ; gain = 392.762 ; free physical = 10194 ; free virtual = 20424 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Ports +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Ports : Time (s): cpu = 00:00:18 ; elapsed = 00:00:18 . Memory (MB): peak = 1494.379 ; gain = 392.762 ; free physical = 10194 ; free virtual = 20424 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:00:18 ; elapsed = 00:00:18 . Memory (MB): peak = 1494.379 ; gain = 392.762 ; free physical = 10194 ; free virtual = 20424 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Nets +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Nets : Time (s): cpu = 00:00:18 ; elapsed = 00:00:18 . Memory (MB): peak = 1494.379 ; gain = 392.762 ; free physical = 10194 ; free virtual = 20424 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Writing Synthesis Report +--------------------------------------------------------------------------------- + +Report BlackBoxes: ++-+--------------+----------+ +| |BlackBox name |Instances | ++-+--------------+----------+ ++-+--------------+----------+ + +Report Cell Usage: ++------+-----+------+ +| |Cell |Count | ++------+-----+------+ +|1 |BUFG | 1| +|2 |LUT2 | 1| +|3 |LUT4 | 4| +|4 |LUT5 | 2| +|5 |FDRE | 22| +|6 |IBUF | 4| +|7 |OBUF | 8| ++------+-----+------+ + +Report Instance Areas: ++------+---------+-------------------+------+ +| |Instance |Module |Cells | ++------+---------+-------------------+------+ +|1 |top | | 42| +|2 | i1 |inputconditioner | 8| +|3 | i2 |inputconditioner_0 | 5| +|4 | i3 |inputconditioner_1 | 7| +|5 | shft |shiftregister | 9| ++------+---------+-------------------+------+ +--------------------------------------------------------------------------------- +Finished Writing Synthesis Report : Time (s): cpu = 00:00:18 ; elapsed = 00:00:18 . Memory (MB): peak = 1494.379 ; gain = 392.762 ; free physical = 10194 ; free virtual = 20424 +--------------------------------------------------------------------------------- +Synthesis finished with 0 errors, 0 critical warnings and 4 warnings. +Synthesis Optimization Runtime : Time (s): cpu = 00:00:14 ; elapsed = 00:00:14 . Memory (MB): peak = 1494.379 ; gain = 78.512 ; free physical = 10254 ; free virtual = 20484 +Synthesis Optimization Complete : Time (s): cpu = 00:00:18 ; elapsed = 00:00:18 . Memory (MB): peak = 1494.387 ; gain = 392.762 ; free physical = 10254 ; free virtual = 20484 +INFO: [Project 1-571] Translating synthesized netlist +INFO: [Netlist 29-17] Analyzing 4 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +INFO: [Project 1-570] Preparing netlist for logic optimization +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +19 Infos, 5 Warnings, 0 Critical Warnings and 0 Errors encountered. +synth_design completed successfully +synth_design: Time (s): cpu = 00:00:19 ; elapsed = 00:00:19 . Memory (MB): peak = 1494.387 ; gain = 405.352 ; free physical = 10222 ; free virtual = 20453 +INFO: [Common 17-1381] The checkpoint '/home/jspear/Development/School/Comp_Arc/Lab2/sim/sim.runs/synth_1/midpoint.dcp' has been generated. +report_utilization: Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.10 . Memory (MB): peak = 1518.395 ; gain = 0.000 ; free physical = 10223 ; free virtual = 20454 +INFO: [Common 17-206] Exiting Vivado at Wed Oct 25 21:40:12 2017... diff --git a/sim/sim.runs/synth_1/runme.sh b/sim/sim.runs/synth_1/runme.sh new file mode 100755 index 0000000..5907234 --- /dev/null +++ b/sim/sim.runs/synth_1/runme.sh @@ -0,0 +1,39 @@ +#!/bin/sh + +# +# Vivado(TM) +# runme.sh: a Vivado-generated Runs Script for UNIX +# Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. +# + +if [ -z "$PATH" ]; then + PATH=/opt/Xilinx/Vivado/2017.2/ids_lite/ISE/bin/lin64:/opt/Xilinx/Vivado/2017.2/bin +else + PATH=/opt/Xilinx/Vivado/2017.2/ids_lite/ISE/bin/lin64:/opt/Xilinx/Vivado/2017.2/bin:$PATH +fi +export PATH + +if [ -z "$LD_LIBRARY_PATH" ]; then + LD_LIBRARY_PATH=/opt/Xilinx/Vivado/2017.2/ids_lite/ISE/lib/lin64 +else + LD_LIBRARY_PATH=/opt/Xilinx/Vivado/2017.2/ids_lite/ISE/lib/lin64:$LD_LIBRARY_PATH +fi +export LD_LIBRARY_PATH + +HD_PWD='/home/jspear/Development/School/Comp_Arc/Lab2/sim/sim.runs/synth_1' +cd "$HD_PWD" + +HD_LOG=runme.log +/bin/touch $HD_LOG + +ISEStep="./ISEWrap.sh" +EAStep() +{ + $ISEStep $HD_LOG "$@" >> $HD_LOG 2>&1 + if [ $? -ne 0 ] + then + exit + fi +} + +EAStep vivado -log midpoint.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source midpoint.tcl diff --git a/sim/sim.runs/synth_1/vivado.jou b/sim/sim.runs/synth_1/vivado.jou new file mode 100644 index 0000000..205b130 --- /dev/null +++ b/sim/sim.runs/synth_1/vivado.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Vivado v2017.2 (64-bit) +# SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 +# IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 +# Start of session at: Wed Oct 25 21:39:45 2017 +# Process ID: 5002 +# Current directory: /home/jspear/Development/School/Comp_Arc/Lab2/sim/sim.runs/synth_1 +# Command line: vivado -log midpoint.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source midpoint.tcl +# Log file: /home/jspear/Development/School/Comp_Arc/Lab2/sim/sim.runs/synth_1/midpoint.vds +# Journal file: /home/jspear/Development/School/Comp_Arc/Lab2/sim/sim.runs/synth_1/vivado.jou +#----------------------------------------------------------- +source midpoint.tcl -notrace diff --git a/sim/sim.runs/synth_1/vivado.pb b/sim/sim.runs/synth_1/vivado.pb new file mode 100644 index 0000000..b66af09 Binary files /dev/null and b/sim/sim.runs/synth_1/vivado.pb differ diff --git a/sim/sim.xpr b/sim/sim.xpr new file mode 100644 index 0000000..4afcc59 --- /dev/null +++ b/sim/sim.xpr @@ -0,0 +1,144 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Vivado Synthesis Defaults + + + + + + + + + + + Default settings for Implementation. + + + + + + + + + + + + + + + + + diff --git a/spimemory.t.v b/spimemory.t.v new file mode 100644 index 0000000..b947e55 --- /dev/null +++ b/spimemory.t.v @@ -0,0 +1,109 @@ +//------------------------------------------------------------------------ +// SPI Memory Test Bench +//------------------------------------------------------------------------ +`include "spimemory.v" + +module testSPIMemory(); + + reg clk; // FPGA Clock + reg sclk_pin; // SPI Clock + reg cs_pin; // SPI Chip Select (enables SPI) + reg mosi_pin; // SPI master out slave in + wire miso_pin; // SPI master in slave out + + spiMemory spi(clk, sclk_pin, cs_pin, mosi_pin, miso_pin, ); + + initial clk = 0; + initial cs_pin = 1; + reg [7:0] testOut = 8'bxxxxxxxx; // last bit is 1 for read + always #1 clk=!clk; + + initial begin + $dumpfile("spimemory.vcd"); + $dumpvars; + + //#50; + + cs_pin = 0; + mosi_pin = 0; + sclk_pin = 0; #10 sclk_pin = 1; #10; // 1 + mosi_pin = 0; + sclk_pin = 0; #10 sclk_pin = 1; #10; // 2 + mosi_pin = 0; + sclk_pin = 0; #10 sclk_pin = 1; #10; // 3 + mosi_pin = 0; + sclk_pin = 0; #10 sclk_pin = 1; #10; // 4 + mosi_pin = 0; + sclk_pin = 0; #10 sclk_pin = 1; #10; // 5 + mosi_pin = 0; + sclk_pin = 0; #10 sclk_pin = 1; #10; // 6 + mosi_pin = 0; + sclk_pin = 0; #10 sclk_pin = 1; #10; // 7 + mosi_pin = 0; // write + sclk_pin = 0; #10 sclk_pin = 1; #10; // 8 + + cs_pin = 1; + mosi_pin = 0; + // Read output + sclk_pin = 0; #10 sclk_pin = 1; #10; // 1 + mosi_pin = 0; + sclk_pin = 0; #10 sclk_pin = 1; #10; // 2 + mosi_pin = 0; + sclk_pin = 0; #10 sclk_pin = 1; #10; // 3 + mosi_pin = 1; + sclk_pin = 0; #10 sclk_pin = 1; #10; // 4 + mosi_pin = 1; + sclk_pin = 0; #10 sclk_pin = 1; #10; // 5 + mosi_pin = 0; + sclk_pin = 0; #10 sclk_pin = 1; #10; // 6 + mosi_pin = 0; + sclk_pin = 0; #10 sclk_pin = 1; #10; // 7 + mosi_pin = 0; + sclk_pin = 0; #10 sclk_pin = 1; #10; // 8 + + // Push input + cs_pin = 0; + mosi_pin = 0; + sclk_pin = 0; #10 sclk_pin = 1; #10; // 1 + mosi_pin = 0; + sclk_pin = 0; #10 sclk_pin = 1; #10; // 2 + mosi_pin = 0; + sclk_pin = 0; #10 sclk_pin = 1; #10; // 3 + mosi_pin = 0; + sclk_pin = 0; #10 sclk_pin = 1; #10; // 4 + mosi_pin = 0; + sclk_pin = 0; #10 sclk_pin = 1; #10; // 5 + mosi_pin = 0; + sclk_pin = 0; #10 sclk_pin = 1; #10; // 6 + mosi_pin = 0; + sclk_pin = 0; #10 sclk_pin = 1; #10; // 7 + mosi_pin = 1; // read + sclk_pin = 0; #10 sclk_pin = 1; #10; // 8 + + mosi_pin = 1'bX; + // Read output + sclk_pin = 0; #10 sclk_pin = 1; #10; // 1 + testOut[0] = miso_pin; + sclk_pin = 0; #10 sclk_pin = 1; #10; // 2 + testOut[1] = miso_pin; + sclk_pin = 0; #10 sclk_pin = 1; #10; // 3 + testOut[2] = miso_pin; + sclk_pin = 0; #10 sclk_pin = 1; #10; // 4 + testOut[3] = miso_pin; + sclk_pin = 0; #10 sclk_pin = 1; #10; // 5 + testOut[4] = miso_pin; + sclk_pin = 0; #10 sclk_pin = 1; #10; // 6 + testOut[5] = miso_pin; + sclk_pin = 0; #10 sclk_pin = 1; #10; // 7 + testOut[6] = miso_pin; + sclk_pin = 0; #10 sclk_pin = 1; #10; // 8 + sclk_pin = 0; #10 sclk_pin = 1; #10; // 8 + sclk_pin = 0; #10 sclk_pin = 1; #10; // 8 + sclk_pin = 0; #10 sclk_pin = 1; #10; // 8 + + cs_pin = 1; + $display("%8b", testOut); + $finish; + end + +endmodule diff --git a/spimemory.v b/spimemory.v index c6ed4f7..b9a00ff 100644 --- a/spimemory.v +++ b/spimemory.v @@ -1,17 +1,66 @@ //------------------------------------------------------------------------ // SPI Memory //------------------------------------------------------------------------ +`include "inputconditioner.v" +`include "shiftregister.v" +`include "dff.v" +`include "datamemory.v" +`include "fsm.v" module spiMemory ( input clk, // FPGA clock input sclk_pin, // SPI clock input cs_pin, // SPI chip select - output miso_pin, // SPI master in slave out input mosi_pin, // SPI master out slave in + output miso_pin, // SPI master in slave out output [3:0] leds // LEDs for debugging -) +); + wire MISO_BUFE, DM_WE, ADDR_WE, SR_WE; + + wire chip_select; + wire sclk_pos, sclk_neg; + inputconditioner #(1) c2(.clk(clk), + .noisysignal(sclk_pin), + .positiveedge(sclk_pos), + .negativeedge(sclk_neg)); + inputconditioner c3(.clk(clk), + .noisysignal(cs_pin), + .conditioned(chip_select)); + + wire[7:0] shiftRegOutP, dataMemoryOut; + wire serialOut; + + shiftregister #(8) sr(.clk(clk), + .peripheralClkEdge(sclk_pos), + .parallelLoad(SR_WE), + .parallelDataIn(dataMemoryOut), + .serialDataIn(mosi_pin), + .parallelDataOut(shiftRegOutP), + .serialDataOut(serialOut)); + + wire[7:0] address; + dff #(8) dff1(clk, ADDR_WE, shiftRegOutP, address); + wire q; + dff #(1) dff2(clk, sclk_neg, serialOut, q); + + // Tri-state buffer + assign miso_pin = (MISO_BUFE) ? q : 1'bz; + + datamemory dataMemory(.clk(clk), + .dataOut(dataMemoryOut), + .dataIn(shiftRegOutP), + .address(address[7:1]), + .writeEnable(DM_WE)); + + finiteStateMachine fsm(.clk(clk), + .sclk_posedge(sclk_pos), + .chip_select(chip_select), + .r_w(shiftRegOutP[0]), + .MISO_BUFE(MISO_BUFE), + .DM_WE(DM_WE), + .ADDR_WE(ADDR_WE), + .SR_WE(SR_WE)); endmodule - diff --git a/spimemory.vcd b/spimemory.vcd new file mode 100644 index 0000000..22d4483 --- /dev/null +++ b/spimemory.vcd @@ -0,0 +1,3073 @@ +$date + Wed Nov 1 19:22:08 2017 +$end +$version + Icarus Verilog +$end +$timescale + 1ps +$end +$scope module testSPIMemory $end +$var wire 1 ! miso_pin $end +$var reg 1 " clk $end +$var reg 1 # cs_pin $end +$var reg 1 $ mosi_pin $end +$var reg 1 % sclk_pin $end +$var reg 8 & testOut [7:0] $end +$scope module spi $end +$var wire 1 ' ADDR_WE $end +$var wire 1 ( DM_WE $end +$var wire 1 ) MISO_BUFE $end +$var wire 1 * SR_WE $end +$var wire 8 + address [7:0] $end +$var wire 1 , chip_select $end +$var wire 1 - clk $end +$var wire 1 . cs_pin $end +$var wire 8 / dataMemoryOut [7:0] $end +$var wire 4 0 leds [3:0] $end +$var wire 1 ! miso_pin $end +$var wire 1 1 mosi_pin $end +$var wire 1 2 q $end +$var wire 1 3 sclk_neg $end +$var wire 1 4 sclk_pin $end +$var wire 1 5 sclk_pos $end +$var wire 1 6 serialOut $end +$var wire 8 7 shiftRegOutP [7:0] $end +$scope module c2 $end +$var wire 1 - clk $end +$var wire 1 4 noisysignal $end +$var reg 1 8 conditioned $end +$var reg 1 9 negativeedge $end +$var reg 1 : positiveedge $end +$var reg 1 ; prev_vals $end +$upscope $end +$scope module c3 $end +$var wire 1 - clk $end +$var wire 1 . noisysignal $end +$var reg 1 < conditioned $end +$var reg 1 = negativeedge $end +$var reg 1 > positiveedge $end +$var reg 3 ? prev_vals [2:0] $end +$upscope $end +$scope module sr $end +$var wire 1 - clk $end +$var wire 8 @ parallelDataIn [7:0] $end +$var wire 8 A parallelDataOut [7:0] $end +$var wire 1 * parallelLoad $end +$var wire 1 5 peripheralClkEdge $end +$var wire 1 1 serialDataIn $end +$var wire 1 6 serialDataOut $end +$var reg 8 B data [7:0] $end +$upscope $end +$scope module dff1 $end +$var wire 8 C d [7:0] $end +$var wire 1 ' enable $end +$var wire 1 - trigger $end +$var reg 8 D q [7:0] $end +$upscope $end +$scope module dff2 $end +$var wire 1 6 d $end +$var wire 1 3 enable $end +$var wire 1 - trigger $end +$var reg 1 E q $end +$upscope $end +$scope module dataMemory $end +$var wire 7 F address [6:0] $end +$var wire 1 - clk $end +$var wire 8 G dataIn [7:0] $end +$var wire 1 ( writeEnable $end +$var reg 8 H dataOut [7:0] $end +$upscope $end +$scope module fsm $end +$var wire 1 , chip_select $end +$var wire 1 - clk $end +$var wire 1 I r_w $end +$var wire 1 5 sclk_posedge $end +$var reg 1 J ADDR_WE $end +$var reg 1 K DM_WE $end +$var reg 1 L MISO_BUFE $end +$var reg 1 M SR_WE $end +$var integer 32 N counter [31:0] $end +$var reg 8 O state [7:0] $end +$upscope $end +$upscope $end +$upscope $end +$enddefinitions $end +#0 +$dumpvars +b0 O +b0 N +xM +xL +xK +xJ +xI +bx H +bx G +bx F +xE +bx D +bx C +bx B +bx A +bx @ +bx ? +x> +x= +x< +x; +x: +x9 +x8 +bx 7 +x6 +x5 +04 +x3 +x2 +01 +bz 0 +bx / +0. +0- +x, +bx + +x* +x) +x( +x' +bx & +0% +0$ +0# +0" +x! +$end +#1000 +z! +0; +bx0 ? +0M +0* +0J +0' +0K +0( +0L +0) +1" +1- +#2000 +0" +0- +#3000 +bx00 ? +08 +09 +03 +1" +1- +#4000 +0" +0- +#5000 +b0 ? +1" +1- +#6000 +0" +0- +#7000 +0< +0, +0= +1" +1- +#8000 +0" +0- +#9000 +b1 O +1" +1- +#10000 +0" +0- +1% +14 +#11000 +1; +1" +1- +#12000 +0" +0- +#13000 +18 +1: +15 +1" +1- +#14000 +0" +0- +#15000 +0I +b1 N +bx0 B +bx0 7 +bx0 A +bx0 C +bx0 G +0: +05 +1" +1- +#16000 +0" +0- +#17000 +1" +1- +#18000 +0" +0- +#19000 +1" +1- +#20000 +0" +0- +0% +04 +#21000 +0; +1" +1- +#22000 +0" +0- +#23000 +08 +19 +13 +1" +1- +#24000 +0" +0- +#25000 +09 +03 +1" +1- +#26000 +0" +0- +#27000 +1" +1- +#28000 +0" +0- +#29000 +1" +1- +#30000 +0" +0- +1% +14 +#31000 +1; +1" +1- +#32000 +0" +0- +#33000 +18 +1: +15 +1" +1- +#34000 +0" +0- +#35000 +b10 N +bx00 B +bx00 7 +bx00 A +bx00 C +bx00 G +0: +05 +1" +1- +#36000 +0" +0- +#37000 +1" +1- +#38000 +0" +0- +#39000 +1" +1- +#40000 +0" +0- +0% +04 +#41000 +0; +1" +1- +#42000 +0" +0- +#43000 +08 +19 +13 +1" +1- +#44000 +0" +0- +#45000 +09 +03 +1" +1- +#46000 +0" +0- +#47000 +1" +1- +#48000 +0" +0- +#49000 +1" +1- +#50000 +0" +0- +1% +14 +#51000 +1; +1" +1- +#52000 +0" +0- +#53000 +18 +1: +15 +1" +1- +#54000 +0" +0- +#55000 +b11 N +bx000 B +bx000 7 +bx000 A +bx000 C +bx000 G +0: +05 +1" +1- +#56000 +0" +0- +#57000 +1" +1- +#58000 +0" +0- +#59000 +1" +1- +#60000 +0" +0- +0% +04 +#61000 +0; +1" +1- +#62000 +0" +0- +#63000 +08 +19 +13 +1" +1- +#64000 +0" +0- +#65000 +09 +03 +1" +1- +#66000 +0" +0- +#67000 +1" +1- +#68000 +0" +0- +#69000 +1" +1- +#70000 +0" +0- +1% +14 +#71000 +1; +1" +1- +#72000 +0" +0- +#73000 +18 +1: +15 +1" +1- +#74000 +0" +0- +#75000 +b100 N +bx0000 B +bx0000 7 +bx0000 A +bx0000 C +bx0000 G +0: +05 +1" +1- +#76000 +0" +0- +#77000 +1" +1- +#78000 +0" +0- +#79000 +1" +1- +#80000 +0" +0- +0% +04 +#81000 +0; +1" +1- +#82000 +0" +0- +#83000 +08 +19 +13 +1" +1- +#84000 +0" +0- +#85000 +09 +03 +1" +1- +#86000 +0" +0- +#87000 +1" +1- +#88000 +0" +0- +#89000 +1" +1- +#90000 +0" +0- +1% +14 +#91000 +1; +1" +1- +#92000 +0" +0- +#93000 +18 +1: +15 +1" +1- +#94000 +0" +0- +#95000 +b101 N +bx00000 B +bx00000 7 +bx00000 A +bx00000 C +bx00000 G +0: +05 +1" +1- +#96000 +0" +0- +#97000 +1" +1- +#98000 +0" +0- +#99000 +1" +1- +#100000 +0" +0- +0% +04 +#101000 +0; +1" +1- +#102000 +0" +0- +#103000 +08 +19 +13 +1" +1- +#104000 +0" +0- +#105000 +09 +03 +1" +1- +#106000 +0" +0- +#107000 +1" +1- +#108000 +0" +0- +#109000 +1" +1- +#110000 +0" +0- +1% +14 +#111000 +1; +1" +1- +#112000 +0" +0- +#113000 +18 +1: +15 +1" +1- +#114000 +0" +0- +#115000 +b110 N +bx000000 B +bx000000 7 +bx000000 A +bx000000 C +bx000000 G +0: +05 +1" +1- +#116000 +0" +0- +#117000 +1" +1- +#118000 +0" +0- +#119000 +1" +1- +#120000 +0" +0- +0% +04 +#121000 +0; +1" +1- +#122000 +0" +0- +#123000 +08 +19 +13 +1" +1- +#124000 +0" +0- +#125000 +09 +03 +1" +1- +#126000 +0" +0- +#127000 +1" +1- +#128000 +0" +0- +#129000 +1" +1- +#130000 +0" +0- +1% +14 +#131000 +1; +1" +1- +#132000 +0" +0- +#133000 +18 +1: +15 +1" +1- +#134000 +0" +0- +#135000 +b111 N +bx0000000 B +bx0000000 7 +bx0000000 A +bx0000000 C +bx0000000 G +0: +05 +1" +1- +#136000 +0" +0- +#137000 +1" +1- +#138000 +0" +0- +#139000 +1" +1- +#140000 +0" +0- +0% +04 +#141000 +0; +1" +1- +#142000 +0" +0- +#143000 +08 +19 +13 +1" +1- +#144000 +0" +0- +#145000 +09 +03 +1" +1- +#146000 +0" +0- +#147000 +1" +1- +#148000 +0" +0- +#149000 +1" +1- +#150000 +0" +0- +1% +14 +#151000 +1; +1" +1- +#152000 +0" +0- +#153000 +18 +1: +15 +1" +1- +#154000 +0" +0- +#155000 +06 +b10 O +b0 N +b0 B +b0 7 +b0 A +b0 C +b0 G +0: +05 +1" +1- +#156000 +0" +0- +#157000 +1J +1' +b11 O +1" +1- +#158000 +0" +0- +#159000 +b0 F +0J +0' +1K +1( +b0 D +b0 + +1" +1- +#160000 +0" +0- +0% +04 +1# +1. +#161000 +0; +b1 ? +1" +1- +#162000 +0" +0- +#163000 +b0 H +b0 / +b0 @ +b11 ? +08 +19 +13 +1" +1- +#164000 +0" +0- +#165000 +09 +03 +b111 ? +0E +02 +1" +1- +#166000 +0" +0- +#167000 +1< +1, +1> +1" +1- +#168000 +0" +0- +#169000 +0> +1" +1- +#170000 +0" +0- +1% +14 +#171000 +1; +1" +1- +#172000 +0" +0- +#173000 +18 +1: +15 +1" +1- +#174000 +0" +0- +#175000 +b1 N +0: +05 +1" +1- +#176000 +0" +0- +#177000 +1" +1- +#178000 +0" +0- +#179000 +1" +1- +#180000 +0" +0- +0% +04 +#181000 +0; +1" +1- +#182000 +0" +0- +#183000 +08 +19 +13 +1" +1- +#184000 +0" +0- +#185000 +09 +03 +1" +1- +#186000 +0" +0- +#187000 +1" +1- +#188000 +0" +0- +#189000 +1" +1- +#190000 +0" +0- +1% +14 +#191000 +1; +1" +1- +#192000 +0" +0- +#193000 +18 +1: +15 +1" +1- +#194000 +0" +0- +#195000 +b10 N +0: +05 +1" +1- +#196000 +0" +0- +#197000 +1" +1- +#198000 +0" +0- +#199000 +1" +1- +#200000 +0" +0- +0% +04 +#201000 +0; +1" +1- +#202000 +0" +0- +#203000 +08 +19 +13 +1" +1- +#204000 +0" +0- +#205000 +09 +03 +1" +1- +#206000 +0" +0- +#207000 +1" +1- +#208000 +0" +0- +#209000 +1" +1- +#210000 +0" +0- +1% +14 +#211000 +1; +1" +1- +#212000 +0" +0- +#213000 +18 +1: +15 +1" +1- +#214000 +0" +0- +#215000 +b11 N +0: +05 +1" +1- +#216000 +0" +0- +#217000 +1" +1- +#218000 +0" +0- +#219000 +1" +1- +#220000 +0" +0- +0% +04 +1$ +11 +#221000 +0; +1" +1- +#222000 +0" +0- +#223000 +08 +19 +13 +1" +1- +#224000 +0" +0- +#225000 +09 +03 +1" +1- +#226000 +0" +0- +#227000 +1" +1- +#228000 +0" +0- +#229000 +1" +1- +#230000 +0" +0- +1% +14 +#231000 +1; +1" +1- +#232000 +0" +0- +#233000 +18 +1: +15 +1" +1- +#234000 +0" +0- +#235000 +1I +b100 N +b1 B +b1 7 +b1 A +b1 C +b1 G +0: +05 +1" +1- +#236000 +0" +0- +#237000 +1" +1- +#238000 +0" +0- +#239000 +b1 H +b1 / +b1 @ +1" +1- +#240000 +0" +0- +0% +04 +#241000 +0; +1" +1- +#242000 +0" +0- +#243000 +08 +19 +13 +1" +1- +#244000 +0" +0- +#245000 +09 +03 +1" +1- +#246000 +0" +0- +#247000 +1" +1- +#248000 +0" +0- +#249000 +1" +1- +#250000 +0" +0- +1% +14 +#251000 +1; +1" +1- +#252000 +0" +0- +#253000 +18 +1: +15 +1" +1- +#254000 +0" +0- +#255000 +b101 N +b11 B +b11 7 +b11 A +b11 C +b11 G +0: +05 +1" +1- +#256000 +0" +0- +#257000 +1" +1- +#258000 +0" +0- +#259000 +b11 H +b11 / +b11 @ +1" +1- +#260000 +0" +0- +0% +04 +0$ +01 +#261000 +0; +1" +1- +#262000 +0" +0- +#263000 +08 +19 +13 +1" +1- +#264000 +0" +0- +#265000 +09 +03 +1" +1- +#266000 +0" +0- +#267000 +1" +1- +#268000 +0" +0- +#269000 +1" +1- +#270000 +0" +0- +1% +14 +#271000 +1; +1" +1- +#272000 +0" +0- +#273000 +18 +1: +15 +1" +1- +#274000 +0" +0- +#275000 +0I +b110 N +b110 B +b110 7 +b110 A +b110 C +b110 G +0: +05 +1" +1- +#276000 +0" +0- +#277000 +1" +1- +#278000 +0" +0- +#279000 +b110 H +b110 / +b110 @ +1" +1- +#280000 +0" +0- +0% +04 +#281000 +0; +1" +1- +#282000 +0" +0- +#283000 +08 +19 +13 +1" +1- +#284000 +0" +0- +#285000 +09 +03 +1" +1- +#286000 +0" +0- +#287000 +1" +1- +#288000 +0" +0- +#289000 +1" +1- +#290000 +0" +0- +1% +14 +#291000 +1; +1" +1- +#292000 +0" +0- +#293000 +18 +1: +15 +1" +1- +#294000 +0" +0- +#295000 +b111 N +b1100 B +b1100 7 +b1100 A +b1100 C +b1100 G +0: +05 +1" +1- +#296000 +0" +0- +#297000 +1" +1- +#298000 +0" +0- +#299000 +b1100 H +b1100 / +b1100 @ +1" +1- +#300000 +0" +0- +0% +04 +#301000 +0; +1" +1- +#302000 +0" +0- +#303000 +08 +19 +13 +1" +1- +#304000 +0" +0- +#305000 +09 +03 +1" +1- +#306000 +0" +0- +#307000 +1" +1- +#308000 +0" +0- +#309000 +1" +1- +#310000 +0" +0- +1% +14 +#311000 +1; +1" +1- +#312000 +0" +0- +#313000 +18 +1: +15 +1" +1- +#314000 +0" +0- +#315000 +b1000 N +b11000 B +b11000 7 +b11000 A +b11000 C +b11000 G +0: +05 +1" +1- +#316000 +0" +0- +#317000 +1" +1- +#318000 +0" +0- +#319000 +b11000 H +b11000 / +b11000 @ +1" +1- +#320000 +0" +0- +0% +04 +0# +0. +#321000 +0; +b110 ? +1" +1- +#322000 +0" +0- +#323000 +b100 ? +08 +19 +13 +1" +1- +#324000 +0" +0- +#325000 +09 +03 +b0 ? +1" +1- +#326000 +0" +0- +#327000 +0< +0, +1= +1" +1- +#328000 +0" +0- +#329000 +0= +1" +1- +#330000 +0" +0- +1% +14 +#331000 +1; +1" +1- +#332000 +0" +0- +#333000 +18 +1: +15 +1" +1- +#334000 +0" +0- +#335000 +b111 O +b0 N +b110000 B +b110000 7 +b110000 A +b110000 C +b110000 G +0: +05 +1" +1- +#336000 +0" +0- +#337000 +b0 O +1" +1- +#338000 +0" +0- +#339000 +0K +0( +b1 O +b110000 H +b110000 / +b110000 @ +1" +1- +#340000 +0" +0- +0% +04 +#341000 +0; +1" +1- +#342000 +0" +0- +#343000 +08 +19 +13 +1" +1- +#344000 +0" +0- +#345000 +09 +03 +1" +1- +#346000 +0" +0- +#347000 +1" +1- +#348000 +0" +0- +#349000 +1" +1- +#350000 +0" +0- +1% +14 +#351000 +1; +1" +1- +#352000 +0" +0- +#353000 +18 +1: +15 +1" +1- +#354000 +0" +0- +#355000 +b1 N +b1100000 B +b1100000 7 +b1100000 A +b1100000 C +b1100000 G +0: +05 +1" +1- +#356000 +0" +0- +#357000 +1" +1- +#358000 +0" +0- +#359000 +1" +1- +#360000 +0" +0- +0% +04 +#361000 +0; +1" +1- +#362000 +0" +0- +#363000 +08 +19 +13 +1" +1- +#364000 +0" +0- +#365000 +09 +03 +1" +1- +#366000 +0" +0- +#367000 +1" +1- +#368000 +0" +0- +#369000 +1" +1- +#370000 +0" +0- +1% +14 +#371000 +1; +1" +1- +#372000 +0" +0- +#373000 +18 +1: +15 +1" +1- +#374000 +0" +0- +#375000 +16 +b10 N +b11000000 B +b11000000 7 +b11000000 A +b11000000 C +b11000000 G +0: +05 +1" +1- +#376000 +0" +0- +#377000 +1" +1- +#378000 +0" +0- +#379000 +1" +1- +#380000 +0" +0- +0% +04 +#381000 +0; +1" +1- +#382000 +0" +0- +#383000 +08 +19 +13 +1" +1- +#384000 +0" +0- +#385000 +09 +03 +1E +12 +1" +1- +#386000 +0" +0- +#387000 +1" +1- +#388000 +0" +0- +#389000 +1" +1- +#390000 +0" +0- +1% +14 +#391000 +1; +1" +1- +#392000 +0" +0- +#393000 +18 +1: +15 +1" +1- +#394000 +0" +0- +#395000 +b11 N +b10000000 B +b10000000 7 +b10000000 A +b10000000 C +b10000000 G +0: +05 +1" +1- +#396000 +0" +0- +#397000 +1" +1- +#398000 +0" +0- +#399000 +1" +1- +#400000 +0" +0- +0% +04 +#401000 +0; +1" +1- +#402000 +0" +0- +#403000 +08 +19 +13 +1" +1- +#404000 +0" +0- +#405000 +09 +03 +1" +1- +#406000 +0" +0- +#407000 +1" +1- +#408000 +0" +0- +#409000 +1" +1- +#410000 +0" +0- +1% +14 +#411000 +1; +1" +1- +#412000 +0" +0- +#413000 +18 +1: +15 +1" +1- +#414000 +0" +0- +#415000 +06 +b100 N +b0 B +b0 7 +b0 A +b0 C +b0 G +0: +05 +1" +1- +#416000 +0" +0- +#417000 +1" +1- +#418000 +0" +0- +#419000 +1" +1- +#420000 +0" +0- +0% +04 +#421000 +0; +1" +1- +#422000 +0" +0- +#423000 +08 +19 +13 +1" +1- +#424000 +0" +0- +#425000 +09 +03 +0E +02 +1" +1- +#426000 +0" +0- +#427000 +1" +1- +#428000 +0" +0- +#429000 +1" +1- +#430000 +0" +0- +1% +14 +#431000 +1; +1" +1- +#432000 +0" +0- +#433000 +18 +1: +15 +1" +1- +#434000 +0" +0- +#435000 +b101 N +0: +05 +1" +1- +#436000 +0" +0- +#437000 +1" +1- +#438000 +0" +0- +#439000 +1" +1- +#440000 +0" +0- +0% +04 +#441000 +0; +1" +1- +#442000 +0" +0- +#443000 +08 +19 +13 +1" +1- +#444000 +0" +0- +#445000 +09 +03 +1" +1- +#446000 +0" +0- +#447000 +1" +1- +#448000 +0" +0- +#449000 +1" +1- +#450000 +0" +0- +1% +14 +#451000 +1; +1" +1- +#452000 +0" +0- +#453000 +18 +1: +15 +1" +1- +#454000 +0" +0- +#455000 +b110 N +0: +05 +1" +1- +#456000 +0" +0- +#457000 +1" +1- +#458000 +0" +0- +#459000 +1" +1- +#460000 +0" +0- +0% +04 +1$ +11 +#461000 +0; +1" +1- +#462000 +0" +0- +#463000 +08 +19 +13 +1" +1- +#464000 +0" +0- +#465000 +09 +03 +1" +1- +#466000 +0" +0- +#467000 +1" +1- +#468000 +0" +0- +#469000 +1" +1- +#470000 +0" +0- +1% +14 +#471000 +1; +1" +1- +#472000 +0" +0- +#473000 +18 +1: +15 +1" +1- +#474000 +0" +0- +#475000 +1I +b111 N +b1 B +b1 7 +b1 A +b1 C +b1 G +0: +05 +1" +1- +#476000 +0" +0- +#477000 +1" +1- +#478000 +0" +0- +#479000 +1" +1- +#480000 +0" +0- +0% +04 +x$ +x1 +#481000 +0; +1" +1- +#482000 +0" +0- +#483000 +08 +19 +13 +1" +1- +#484000 +0" +0- +#485000 +09 +03 +1" +1- +#486000 +0" +0- +#487000 +1" +1- +#488000 +0" +0- +#489000 +1" +1- +#490000 +0" +0- +1% +14 +#491000 +1; +1" +1- +#492000 +0" +0- +#493000 +18 +1: +15 +1" +1- +#494000 +0" +0- +#495000 +xI +b10 O +b0 N +b1x B +b1x 7 +b1x A +b1x C +b1x G +0: +05 +1" +1- +#496000 +0" +0- +#497000 +1J +1' +b101 O +1" +1- +#498000 +0" +0- +#499000 +b1 F +0J +0' +b110 O +b1x D +b1x + +1" +1- +#500000 +0" +0- +0% +04 +bxz & +#501000 +0; +bx H +bx / +bx @ +1M +1* +b100 O +1" +1- +#502000 +0" +0- +#503000 +0! +x6 +0M +0* +1L +1) +bx B +bx 7 +bx A +bx C +bx G +08 +19 +13 +1" +1- +#504000 +0" +0- +#505000 +x! +09 +03 +xE +x2 +1" +1- +#506000 +0" +0- +#507000 +1" +1- +#508000 +0" +0- +#509000 +1" +1- +#510000 +0" +0- +1% +14 +#511000 +1; +1" +1- +#512000 +0" +0- +#513000 +18 +1: +15 +1" +1- +#514000 +0" +0- +#515000 +b1 N +0: +05 +1" +1- +#516000 +0" +0- +#517000 +1" +1- +#518000 +0" +0- +#519000 +1" +1- +#520000 +0" +0- +0% +04 +bxz & +#521000 +0; +1" +1- +#522000 +0" +0- +#523000 +08 +19 +13 +1" +1- +#524000 +0" +0- +#525000 +09 +03 +1" +1- +#526000 +0" +0- +#527000 +1" +1- +#528000 +0" +0- +#529000 +1" +1- +#530000 +0" +0- +1% +14 +#531000 +1; +1" +1- +#532000 +0" +0- +#533000 +18 +1: +15 +1" +1- +#534000 +0" +0- +#535000 +b10 N +0: +05 +1" +1- +#536000 +0" +0- +#537000 +1" +1- +#538000 +0" +0- +#539000 +1" +1- +#540000 +0" +0- +0% +04 +bxz & +#541000 +0; +1" +1- +#542000 +0" +0- +#543000 +08 +19 +13 +1" +1- +#544000 +0" +0- +#545000 +09 +03 +1" +1- +#546000 +0" +0- +#547000 +1" +1- +#548000 +0" +0- +#549000 +1" +1- +#550000 +0" +0- +1% +14 +#551000 +1; +1" +1- +#552000 +0" +0- +#553000 +18 +1: +15 +1" +1- +#554000 +0" +0- +#555000 +b11 N +0: +05 +1" +1- +#556000 +0" +0- +#557000 +1" +1- +#558000 +0" +0- +#559000 +1" +1- +#560000 +0" +0- +0% +04 +bxz & +#561000 +0; +1" +1- +#562000 +0" +0- +#563000 +08 +19 +13 +1" +1- +#564000 +0" +0- +#565000 +09 +03 +1" +1- +#566000 +0" +0- +#567000 +1" +1- +#568000 +0" +0- +#569000 +1" +1- +#570000 +0" +0- +1% +14 +#571000 +1; +1" +1- +#572000 +0" +0- +#573000 +18 +1: +15 +1" +1- +#574000 +0" +0- +#575000 +b100 N +0: +05 +1" +1- +#576000 +0" +0- +#577000 +1" +1- +#578000 +0" +0- +#579000 +1" +1- +#580000 +0" +0- +0% +04 +bxz & +#581000 +0; +1" +1- +#582000 +0" +0- +#583000 +08 +19 +13 +1" +1- +#584000 +0" +0- +#585000 +09 +03 +1" +1- +#586000 +0" +0- +#587000 +1" +1- +#588000 +0" +0- +#589000 +1" +1- +#590000 +0" +0- +1% +14 +#591000 +1; +1" +1- +#592000 +0" +0- +#593000 +18 +1: +15 +1" +1- +#594000 +0" +0- +#595000 +b101 N +0: +05 +1" +1- +#596000 +0" +0- +#597000 +1" +1- +#598000 +0" +0- +#599000 +1" +1- +#600000 +0" +0- +0% +04 +bxz & +#601000 +0; +1" +1- +#602000 +0" +0- +#603000 +08 +19 +13 +1" +1- +#604000 +0" +0- +#605000 +09 +03 +1" +1- +#606000 +0" +0- +#607000 +1" +1- +#608000 +0" +0- +#609000 +1" +1- +#610000 +0" +0- +1% +14 +#611000 +1; +1" +1- +#612000 +0" +0- +#613000 +18 +1: +15 +1" +1- +#614000 +0" +0- +#615000 +b110 N +0: +05 +1" +1- +#616000 +0" +0- +#617000 +1" +1- +#618000 +0" +0- +#619000 +1" +1- +#620000 +0" +0- +0% +04 +bxz & +#621000 +0; +1" +1- +#622000 +0" +0- +#623000 +08 +19 +13 +1" +1- +#624000 +0" +0- +#625000 +09 +03 +1" +1- +#626000 +0" +0- +#627000 +1" +1- +#628000 +0" +0- +#629000 +1" +1- +#630000 +0" +0- +1% +14 +#631000 +1; +1" +1- +#632000 +0" +0- +#633000 +18 +1: +15 +1" +1- +#634000 +0" +0- +#635000 +b111 N +0: +05 +1" +1- +#636000 +0" +0- +#637000 +1" +1- +#638000 +0" +0- +#639000 +1" +1- +#640000 +0" +0- +0% +04 +#641000 +0; +1" +1- +#642000 +0" +0- +#643000 +08 +19 +13 +1" +1- +#644000 +0" +0- +#645000 +09 +03 +1" +1- +#646000 +0" +0- +#647000 +1" +1- +#648000 +0" +0- +#649000 +1" +1- +#650000 +0" +0- +1% +14 +#651000 +1; +1" +1- +#652000 +0" +0- +#653000 +18 +1: +15 +1" +1- +#654000 +0" +0- +#655000 +b0 O +b0 N +0: +05 +1" +1- +#656000 +0" +0- +#657000 +z! +0L +0) +b1 O +1" +1- +#658000 +0" +0- +#659000 +1" +1- +#660000 +0" +0- +0% +04 +#661000 +0; +1" +1- +#662000 +0" +0- +#663000 +08 +19 +13 +1" +1- +#664000 +0" +0- +#665000 +09 +03 +1" +1- +#666000 +0" +0- +#667000 +1" +1- +#668000 +0" +0- +#669000 +1" +1- +#670000 +0" +0- +1% +14 +#671000 +1; +1" +1- +#672000 +0" +0- +#673000 +18 +1: +15 +1" +1- +#674000 +0" +0- +#675000 +b1 N +0: +05 +1" +1- +#676000 +0" +0- +#677000 +1" +1- +#678000 +0" +0- +#679000 +1" +1- +#680000 +0" +0- +0% +04 +#681000 +0; +1" +1- +#682000 +0" +0- +#683000 +08 +19 +13 +1" +1- +#684000 +0" +0- +#685000 +09 +03 +1" +1- +#686000 +0" +0- +#687000 +1" +1- +#688000 +0" +0- +#689000 +1" +1- +#690000 +0" +0- +1% +14 +#691000 +1; +1" +1- +#692000 +0" +0- +#693000 +18 +1: +15 +1" +1- +#694000 +0" +0- +#695000 +b10 N +0: +05 +1" +1- +#696000 +0" +0- +#697000 +1" +1- +#698000 +0" +0- +#699000 +1" +1- +#700000 +0" +0- +1# +1. diff --git a/vivado.jou b/vivado.jou new file mode 100644 index 0000000..dc883d7 --- /dev/null +++ b/vivado.jou @@ -0,0 +1,57 @@ +#----------------------------------------------------------- +# Vivado v2017.2 (64-bit) +# SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 +# IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 +# Start of session at: Wed Oct 25 21:01:35 2017 +# Process ID: 4769 +# Current directory: /home/jspear/Development/School/Comp_Arc/Lab2 +# Command line: vivado +# Log file: /home/jspear/Development/School/Comp_Arc/Lab2/vivado.log +# Journal file: /home/jspear/Development/School/Comp_Arc/Lab2/vivado.jou +#----------------------------------------------------------- +start_gui +create_project sim /home/jspear/Development/School/Comp_Arc/Lab2/sim -part xc7z010clg400-1 +add_files -fileset constrs_1 -norecurse /home/jspear/Development/School/Comp_Arc/Lab2/ZYBO_Master.xdc +add_files -norecurse /home/jspear/Development/School/Comp_Arc/Lab2/midpoint.v +update_compile_order -fileset sources_1 +launch_runs synth_1 -jobs 2 +wait_on_run synth_1 +launch_runs impl_1 -jobs 2 +wait_on_run impl_1 +reset_run synth_1 +launch_runs synth_1 -jobs 2 +wait_on_run synth_1 +launch_runs impl_1 -jobs 2 +wait_on_run impl_1 +reset_run synth_1 +launch_runs synth_1 -jobs 2 +wait_on_run synth_1 +launch_runs impl_1 -jobs 2 +wait_on_run impl_1 +open_run impl_1 +launch_runs impl_1 -to_step write_bitstream -jobs 2 +wait_on_run impl_1 +open_hw +connect_hw_server +open_hw_target +set_property PROGRAM.FILE {/home/jspear/Development/School/Comp_Arc/Lab2/sim/sim.runs/impl_1/midpoint.bit} [get_hw_devices xc7z010_1] +current_hw_device [get_hw_devices xc7z010_1] +refresh_hw_device -update_hw_probes false [lindex [get_hw_devices xc7z010_1] 0] +set_property PROBES.FILE {} [get_hw_devices xc7z010_1] +set_property FULL_PROBES.FILE {} [get_hw_devices xc7z010_1] +set_property PROGRAM.FILE {/home/jspear/Development/School/Comp_Arc/Lab2/sim/sim.runs/impl_1/midpoint.bit} [get_hw_devices xc7z010_1] +program_hw_devices [get_hw_devices xc7z010_1] +refresh_hw_device [lindex [get_hw_devices xc7z010_1] 0] +reset_run synth_1 +launch_runs synth_1 -jobs 2 +wait_on_run synth_1 +launch_runs impl_1 -jobs 2 +wait_on_run impl_1 +refresh_design +launch_runs impl_1 -to_step write_bitstream -jobs 2 +wait_on_run impl_1 +set_property PROBES.FILE {} [get_hw_devices xc7z010_1] +set_property FULL_PROBES.FILE {} [get_hw_devices xc7z010_1] +set_property PROGRAM.FILE {/home/jspear/Development/School/Comp_Arc/Lab2/sim/sim.runs/impl_1/midpoint.bit} [get_hw_devices xc7z010_1] +program_hw_devices [get_hw_devices xc7z010_1] +refresh_hw_device [lindex [get_hw_devices xc7z010_1] 0] diff --git a/vivado.log b/vivado.log new file mode 100644 index 0000000..1b510e0 --- /dev/null +++ b/vivado.log @@ -0,0 +1,144 @@ +#----------------------------------------------------------- +# Vivado v2017.2 (64-bit) +# SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 +# IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 +# Start of session at: Wed Oct 25 21:01:35 2017 +# Process ID: 4769 +# Current directory: /home/jspear/Development/School/Comp_Arc/Lab2 +# Command line: vivado +# Log file: /home/jspear/Development/School/Comp_Arc/Lab2/vivado.log +# Journal file: /home/jspear/Development/School/Comp_Arc/Lab2/vivado.jou +#----------------------------------------------------------- +start_gui +create_project sim /home/jspear/Development/School/Comp_Arc/Lab2/sim -part xc7z010clg400-1 +INFO: [IP_Flow 19-234] Refreshing IP repositories +INFO: [IP_Flow 19-1704] No user IP repositories specified +INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/opt/Xilinx/Vivado/2017.2/data/ip'. +add_files -fileset constrs_1 -norecurse /home/jspear/Development/School/Comp_Arc/Lab2/ZYBO_Master.xdc +add_files -norecurse /home/jspear/Development/School/Comp_Arc/Lab2/midpoint.v +update_compile_order -fileset sources_1 +launch_runs synth_1 -jobs 2 +[Wed Oct 25 21:26:20 2017] Launched synth_1... +Run output will be captured here: /home/jspear/Development/School/Comp_Arc/Lab2/sim/sim.runs/synth_1/runme.log +launch_runs impl_1 -jobs 2 +[Wed Oct 25 21:27:06 2017] Launched impl_1... +Run output will be captured here: /home/jspear/Development/School/Comp_Arc/Lab2/sim/sim.runs/impl_1/runme.log +reset_run synth_1 +launch_runs synth_1 -jobs 2 +[Wed Oct 25 21:30:59 2017] Launched synth_1... +Run output will be captured here: /home/jspear/Development/School/Comp_Arc/Lab2/sim/sim.runs/synth_1/runme.log +launch_runs impl_1 -jobs 2 +[Wed Oct 25 21:31:45 2017] Launched impl_1... +Run output will be captured here: /home/jspear/Development/School/Comp_Arc/Lab2/sim/sim.runs/impl_1/runme.log +reset_run synth_1 +launch_runs synth_1 -jobs 2 +[Wed Oct 25 21:32:38 2017] Launched synth_1... +Run output will be captured here: /home/jspear/Development/School/Comp_Arc/Lab2/sim/sim.runs/synth_1/runme.log +launch_runs impl_1 -jobs 2 +[Wed Oct 25 21:33:23 2017] Launched impl_1... +Run output will be captured here: /home/jspear/Development/School/Comp_Arc/Lab2/sim/sim.runs/impl_1/runme.log +open_run impl_1 +INFO: [Netlist 29-17] Analyzing 2 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +INFO: [Project 1-479] Netlist was created with Vivado 2017.2 +INFO: [Device 21-403] Loading part xc7z010clg400-1 +INFO: [Project 1-570] Preparing netlist for logic optimization +Parsing XDC File [/home/jspear/Development/School/Comp_Arc/Lab2/.Xil/Vivado-4769-Kreyshawn/dcp13/midpoint.xdc] +Finished Parsing XDC File [/home/jspear/Development/School/Comp_Arc/Lab2/.Xil/Vivado-4769-Kreyshawn/dcp13/midpoint.xdc] +Reading XDEF placement. +Reading placer database... +Reading XDEF routing. +Read XDEF File: Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.01 . Memory (MB): peak = 6292.703 ; gain = 0.000 ; free physical = 11413 ; free virtual = 21611 +Restored from archive | CPU: 0.020000 secs | Memory: 0.043633 MB | +Finished XDEF File Restore: Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.01 . Memory (MB): peak = 6292.703 ; gain = 0.000 ; free physical = 11413 ; free virtual = 21611 +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +open_run: Time (s): cpu = 00:00:12 ; elapsed = 00:00:07 . Memory (MB): peak = 6439.301 ; gain = 331.160 ; free physical = 11332 ; free virtual = 21531 +WARNING: [Timing 38-313] There are no user specified timing constraints. Timing constraints are needed for proper timing analysis. +launch_runs impl_1 -to_step write_bitstream -jobs 2 +[Wed Oct 25 21:34:19 2017] Launched impl_1... +Run output will be captured here: /home/jspear/Development/School/Comp_Arc/Lab2/sim/sim.runs/impl_1/runme.log +open_hw +connect_hw_server +INFO: [Labtools 27-2285] Connecting to hw_server url TCP:localhost:3121 +INFO: [Labtools 27-2222] Launching hw_server... +INFO: [Labtools 27-2221] Launch Output: + +****** Xilinx hw_server v2017.2 + **** Build date : Jun 15 2017-18:45:18 + ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. + + +open_hw_target +INFO: [Labtoolstcl 44-466] Opening hw_target localhost:3121/xilinx_tcf/Digilent/210279651540A +set_property PROGRAM.FILE {/home/jspear/Development/School/Comp_Arc/Lab2/sim/sim.runs/impl_1/midpoint.bit} [get_hw_devices xc7z010_1] +current_hw_device [get_hw_devices xc7z010_1] +refresh_hw_device -update_hw_probes false [lindex [get_hw_devices xc7z010_1] 0] +INFO: [Labtools 27-1434] Device xc7z010 (JTAG device index = 1) is programmed with a design that has no supported debug core(s) in it. +WARNING: [Labtools 27-3361] The debug hub core was not detected. +Resolution: +1. Make sure the clock connected to the debug hub (dbg_hub) core is a free running clock and is active. +2. Make sure the BSCAN_SWITCH_USER_MASK device property in Vivado Hardware Manager reflects the user scan chain setting in the design and refresh the device. To determine the user scan chain setting in the design, open the implemented design and use 'get_property C_USER_SCAN_CHAIN [get_debug_cores dbg_hub]'. +For more details on setting the scan chain property, consult the Vivado Debug and Programming User Guide (UG908). +ERROR: [Labtoolstcl 44-513] HW Target shutdown. Closing target: localhost:3121/xilinx_tcf/Digilent/210279651540A +INFO: [Labtoolstcl 44-466] Opening hw_target localhost:3121/xilinx_tcf/Digilent/210279651540A +WARNING: [Labtoolstcl 44-129] No matching hw_ila_data was found. +INFO: [Labtools 27-1434] Device xc7z010 (JTAG device index = 1) is programmed with a design that has no supported debug core(s) in it. +WARNING: [Labtools 27-3361] The debug hub core was not detected. +Resolution: +1. Make sure the clock connected to the debug hub (dbg_hub) core is a free running clock and is active. +2. Make sure the BSCAN_SWITCH_USER_MASK device property in Vivado Hardware Manager reflects the user scan chain setting in the design and refresh the device. To determine the user scan chain setting in the design, open the implemented design and use 'get_property C_USER_SCAN_CHAIN [get_debug_cores dbg_hub]'. +For more details on setting the scan chain property, consult the Vivado Debug and Programming User Guide (UG908). +WARNING: [Labtoolstcl 44-129] No matching hw_ila_data was found. +set_property PROBES.FILE {} [get_hw_devices xc7z010_1] +set_property FULL_PROBES.FILE {} [get_hw_devices xc7z010_1] +set_property PROGRAM.FILE {/home/jspear/Development/School/Comp_Arc/Lab2/sim/sim.runs/impl_1/midpoint.bit} [get_hw_devices xc7z010_1] +program_hw_devices [get_hw_devices xc7z010_1] +INFO: [Labtools 27-3164] End of startup status: HIGH +refresh_hw_device [lindex [get_hw_devices xc7z010_1] 0] +INFO: [Labtools 27-1434] Device xc7z010 (JTAG device index = 1) is programmed with a design that has no supported debug core(s) in it. +WARNING: [Labtools 27-3361] The debug hub core was not detected. +Resolution: +1. Make sure the clock connected to the debug hub (dbg_hub) core is a free running clock and is active. +2. Make sure the BSCAN_SWITCH_USER_MASK device property in Vivado Hardware Manager reflects the user scan chain setting in the design and refresh the device. To determine the user scan chain setting in the design, open the implemented design and use 'get_property C_USER_SCAN_CHAIN [get_debug_cores dbg_hub]'. +For more details on setting the scan chain property, consult the Vivado Debug and Programming User Guide (UG908). +reset_run synth_1 +launch_runs synth_1 -jobs 2 +[Wed Oct 25 21:39:45 2017] Launched synth_1... +Run output will be captured here: /home/jspear/Development/School/Comp_Arc/Lab2/sim/sim.runs/synth_1/runme.log +launch_runs impl_1 -jobs 2 +[Wed Oct 25 21:40:17 2017] Launched impl_1... +Run output will be captured here: /home/jspear/Development/School/Comp_Arc/Lab2/sim/sim.runs/impl_1/runme.log +refresh_design +INFO: [Netlist 29-17] Analyzing 4 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +INFO: [Project 1-479] Netlist was created with Vivado 2017.2 +INFO: [Project 1-570] Preparing netlist for logic optimization +Parsing XDC File [/home/jspear/Development/School/Comp_Arc/Lab2/.Xil/Vivado-4769-Kreyshawn/dcp19/midpoint.xdc] +Finished Parsing XDC File [/home/jspear/Development/School/Comp_Arc/Lab2/.Xil/Vivado-4769-Kreyshawn/dcp19/midpoint.xdc] +Reading XDEF placement. +Reading placer database... +Reading XDEF routing. +Read XDEF File: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 6960.090 ; gain = 0.000 ; free physical = 10718 ; free virtual = 20958 +Restored from archive | CPU: 0.010000 secs | Memory: 0.048988 MB | +Finished XDEF File Restore: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 6960.090 ; gain = 0.000 ; free physical = 10718 ; free virtual = 20958 +WARNING: [Timing 38-313] There are no user specified timing constraints. Timing constraints are needed for proper timing analysis. +launch_runs impl_1 -to_step write_bitstream -jobs 2 +[Wed Oct 25 21:41:47 2017] Launched impl_1... +Run output will be captured here: /home/jspear/Development/School/Comp_Arc/Lab2/sim/sim.runs/impl_1/runme.log +set_property PROBES.FILE {} [get_hw_devices xc7z010_1] +set_property FULL_PROBES.FILE {} [get_hw_devices xc7z010_1] +set_property PROGRAM.FILE {/home/jspear/Development/School/Comp_Arc/Lab2/sim/sim.runs/impl_1/midpoint.bit} [get_hw_devices xc7z010_1] +program_hw_devices [get_hw_devices xc7z010_1] +INFO: [Labtools 27-3164] End of startup status: HIGH +refresh_hw_device [lindex [get_hw_devices xc7z010_1] 0] +INFO: [Labtools 27-1434] Device xc7z010 (JTAG device index = 1) is programmed with a design that has no supported debug core(s) in it. +WARNING: [Labtools 27-3361] The debug hub core was not detected. +Resolution: +1. Make sure the clock connected to the debug hub (dbg_hub) core is a free running clock and is active. +2. Make sure the BSCAN_SWITCH_USER_MASK device property in Vivado Hardware Manager reflects the user scan chain setting in the design and refresh the device. To determine the user scan chain setting in the design, open the implemented design and use 'get_property C_USER_SCAN_CHAIN [get_debug_cores dbg_hub]'. +For more details on setting the scan chain property, consult the Vivado Debug and Programming User Guide (UG908). +ERROR: [Labtoolstcl 44-513] HW Target shutdown. Closing target: localhost:3121/xilinx_tcf/Digilent/210279651540A +exit +INFO: [Common 17-206] Exiting Vivado at Thu Oct 26 09:36:40 2017... diff --git a/work_plan.txt b/work_plan.txt new file mode 100644 index 0000000..e73ea9e --- /dev/null +++ b/work_plan.txt @@ -0,0 +1,36 @@ +Work Plan Lab 2 + +Jonah Spear and David Papp + +Input Conditioning: do 10/24 +Implementation: 1 hours +Test Bench: 2 hours +Composing deliverables: 0.5 hours + + +Shift Register: do 10/24 +Implementation: 1 hours +Test bench: 2 hours +Composing deliverables: 0.25 hours + + +Midpoint check in due 10/25: +Implementation: 1 hour +Deliverables: 1 hour + + +SPI Memory do 10/29 +Implementation: 1 hour +Testing: 1.5 hours + + +Inconveniences/debugging do 10/29 +2 hours + + +Lab write up do 10/29 +1 hour + + +Total: +14.5 Hours