diff --git a/inputconditioner.t.v b/inputconditioner.t.v index 2814163..5e703c3 100644 --- a/inputconditioner.t.v +++ b/inputconditioner.t.v @@ -1,6 +1,8 @@ //------------------------------------------------------------------------ // Input Conditioner test bench //------------------------------------------------------------------------ +`timescale 1 ns / 1 ps +`include "inputconditioner.v" module testConditioner(); @@ -14,16 +16,49 @@ module testConditioner(); .noisysignal(pin), .conditioned(conditioned), .positiveedge(rising), - .negativeedge(falling)) + .negativeedge(falling)); // Generate clock (50MHz) - initial clk=0; - always #10 clk=!clk; // 50MHz Clock - + initial clk = 0; + always #10 clk=!clk; // 50MHz Clock initial begin // Your Test Code // Be sure to test each of the three conditioner functions: // Synchronization, Debouncing, Edge Detection - + $dumpfile("inputconditioner.vcd"); + $dumpvars(); + + //Testing Synchronization and edge detection + pin = 0; #150 + pin = 1; #133 + pin = 0; #231 + pin = 1; #52 + pin = 0; #100 + + //Testing debouncing when input bounces but remains zero + pin = 0; #5 + pin = 1; #5 + pin = 0; #5 + pin = 1; #5 + pin = 0; #100 + //Check that conditioned = 0 the whole time + + //Testing debouncing when input bounces and switches to one + pin = 0; #5 + pin = 1; #5 + pin = 0; #5 + pin = 1; #2 + pin = 0; #3 + pin = 1; #1 + pin = 0; #5 + pin = 1; #160 + //Check that conditioned = 0 and then switches to 1 after pin has settled + + //Check delay for even clock cycle changes + pin = 0; #120 + pin = 1; #120 + pin = 0; #120 + $finish; + end endmodule diff --git a/inputconditioner.v b/inputconditioner.v index 736a866..22f8208 100644 --- a/inputconditioner.v +++ b/inputconditioner.v @@ -27,6 +27,16 @@ output reg negativeedge // 1 clk pulse at falling edge of conditioned else begin if( counter == waittime) begin counter <= 0; + if (synchronizer1 == 0 && conditioned == 1) begin + negativeedge <= 1; + end + if (synchronizer1 == 1 && conditioned == 0) begin + positiveedge <= 1; + end + else begin + negativeedge <= 0; + positiveedge <= 0; + end conditioned <= synchronizer1; end else diff --git a/midpoint.v b/midpoint.v new file mode 100644 index 0000000..45658b5 --- /dev/null +++ b/midpoint.v @@ -0,0 +1,89 @@ +//------------------------------------------------------------------------ +// Midpoint module +//------------------------------------------------------------------------ + +// JK flip-flop +module jkff1 +( + input trigger, + input j, + input k, + output reg q +); + always @(posedge trigger) begin + if(j && ~k) begin + q <= 1'b1; + end + else if(k && ~j) begin + q <= 1'b0; + end + else if(k && j) begin + q <= ~q; + end + end +endmodule + +// Two-input MUX with parameterized bit width (default: 1-bit) +module mux2 #( parameter W = 1 ) +( + input[W-1:0] in0, + input[W-1:0] in1, + input sel, + output[W-1:0] out +); + // Conditional operator - http://www.verilog.renerta.com/source/vrg00010.htm + assign out = (sel) ? in1 : in0; +endmodule + + +module Midpoint( + input clk, + input [1:0] sw, + input[3:0] btn, + output [3:0] led + ); + wire peripheralClkEdge; + wire parallelLoad; + wire serialDataIn; + wire[7:0] parallelDataOut; + wire serialDataOut; + wire[7:0] parallelDataIn; + wire[3:0] res0, res1; + wire res_sel; + + assign parallelDataIn = 8'b10011001; + // Instantiate with parameter width = 8 + shiftregister #(8) sr1(.clk(clk), + .peripheralClkEdge(peripheralClkEdge), + .parallelLoad(parallelLoad), + .parallelDataIn(parallelDataIn), + .serialDataIn(serialDataIn), + .parallelDataOut(parallelDataOut), + .serialDataOut(serialDataOut)); + + inputconditioner ICParallelLoad(.clk(clk), + .noisysignal(btn[0]), + .conditioned(), + .positiveedge(), + .negativeedge(parallelLoad)); + + inputconditioner ICSerialIn(.clk(clk), + .noisysignal(sw[0]), + .conditioned(serialDataIn), + .positiveedge(), + .negativeedge()); + + inputconditioner ICPerfClock(.clk(clk), + .noisysignal(sw[1]), + .conditioned(), + .positiveedge(peripheralClkEdge), + .negativeedge()); + + assign res0 = parallelDataOut[3:0]; + assign res1 = parallelDataOut[7:4]; + + // Capture button input to switch which MUX input to LEDs + jkff1 src_sel(.trigger(clk), .j(btn[3]), .k(btn[2]), .q(res_sel)); + mux2 #(4) output_select(.in0(res0), .in1(res1), .sel(res_sel), .out(led)); + +endmodule diff --git a/shiftregister.t.v b/shiftregister.t.v index abe5b48..5bdce3d 100644 --- a/shiftregister.t.v +++ b/shiftregister.t.v @@ -1,7 +1,7 @@ //------------------------------------------------------------------------ // Shift Register test bench //------------------------------------------------------------------------ - +`include "shiftregister.v" module testshiftregister(); reg clk; @@ -20,9 +20,39 @@ module testshiftregister(); .serialDataIn(serialDataIn), .parallelDataOut(parallelDataOut), .serialDataOut(serialDataOut)); - + + initial clk = 0; + always #10 clk=!clk; // 50MHz Clock + initial begin - // Your Test Code + $dumpfile("shiftregister.vcd"); + $dumpvars(0, clk, peripheralClkEdge, parallelLoad, parallelDataOut, serialDataOut, parallelDataIn, serialDataIn); + + peripheralClkEdge = 0; + parallelLoad = 1; + parallelDataIn = 8'b10011101; #50 + $display("parallelDataOut after loading b10011101: %b", parallelDataOut); + + parallelLoad = 0; + serialDataIn = 0; #100 + $display("parallelDataOut shouldn't change: %b", parallelDataOut); + + $display("serialdata out before shifting: %b", serialDataOut); + peripheralClkEdge = 1; + parallelLoad = 0; + serialDataIn = 0; #20 + $display("parallelDataOut after shifting in 0: %b", parallelDataOut); + $display("serialdata out after shifting: %b", serialDataOut); + + serialDataIn = 1; #20 + $display("parallelDataOut after shifting in 1: %b", parallelDataOut); + $display("serialdata out after shifting: %b", serialDataOut); + + serialDataIn = 1; #20 + $display("parallelDataOut after shifting in 1: %b", parallelDataOut); + $display("serialdata out after shifting: %b", serialDataOut); + + $finish; end endmodule diff --git a/shiftregister.v b/shiftregister.v index b4ec057..23055d4 100644 --- a/shiftregister.v +++ b/shiftregister.v @@ -19,7 +19,17 @@ output serialDataOut // Positive edge synchronized ); reg [width-1:0] shiftregistermem; + + assign parallelDataOut = shiftregistermem; + assign serialDataOut = shiftregistermem[width-1]; + always @(posedge clk) begin - // Your Code Here + if (parallelLoad) begin + shiftregistermem <= parallelDataIn; + end + else if (peripheralClkEdge) begin + shiftregistermem[width-1:1] <= shiftregistermem[width-2:0]; + shiftregistermem[0] <= serialDataIn; + end end endmodule diff --git a/workplan.txt b/workplan.txt new file mode 100644 index 0000000..c8608c5 --- /dev/null +++ b/workplan.txt @@ -0,0 +1,8 @@ +Input Conditioning implementation: 1hr +Input conditioning test bench: 1hr +Shift Register implementation: 2hr +Mid point deliverable (FPGA, report): 2hr +SPI memory implementation: 4hr +SPI testing: 2hr +Final report: 1hr +Total: 13hr