From 6100e6070f10c93495cf31ec5f6a8dc421de9e02 Mon Sep 17 00:00:00 2001 From: xiaozhengxu Date: Mon, 23 Oct 2017 00:17:40 -0400 Subject: [PATCH 1/5] Create workplan.txt --- workplan.txt | 8 ++++++++ 1 file changed, 8 insertions(+) create mode 100644 workplan.txt diff --git a/workplan.txt b/workplan.txt new file mode 100644 index 0000000..c8608c5 --- /dev/null +++ b/workplan.txt @@ -0,0 +1,8 @@ +Input Conditioning implementation: 1hr +Input conditioning test bench: 1hr +Shift Register implementation: 2hr +Mid point deliverable (FPGA, report): 2hr +SPI memory implementation: 4hr +SPI testing: 2hr +Final report: 1hr +Total: 13hr From 3e0642e7f7f17dfc44d3284341fa749cb9b318c8 Mon Sep 17 00:00:00 2001 From: Xiaozheng Xu Date: Tue, 24 Oct 2017 21:56:47 -0400 Subject: [PATCH 2/5] inputconditioner logic seems to work, but the test bench is not complete and doesn't stop by itself. --- inputconditioner.t.v | 42 +++++++++++++++++++++++++++++++++++++----- inputconditioner.v | 8 ++++++++ 2 files changed, 45 insertions(+), 5 deletions(-) diff --git a/inputconditioner.t.v b/inputconditioner.t.v index 2814163..64d16f5 100644 --- a/inputconditioner.t.v +++ b/inputconditioner.t.v @@ -1,6 +1,8 @@ //------------------------------------------------------------------------ // Input Conditioner test bench //------------------------------------------------------------------------ +`timescale 1 ns / 1 ps +`include "inputconditioner.v" module testConditioner(); @@ -9,21 +11,51 @@ module testConditioner(); wire conditioned; wire rising; wire falling; + + integer currenttime = 0; inputconditioner dut(.clk(clk), .noisysignal(pin), .conditioned(conditioned), .positiveedge(rising), - .negativeedge(falling)) + .negativeedge(falling)); // Generate clock (50MHz) - initial clk=0; - always #10 clk=!clk; // 50MHz Clock - + initial clk = 0; + always #10 clk=!clk; // 50MHz Clock initial begin // Your Test Code // Be sure to test each of the three conditioner functions: // Synchronization, Debouncing, Edge Detection - + $dumpfile("inputconditioner.vcd"); + $dumpvars(0, clk, pin, conditioned, rising, falling); + + //Testing Synchronization and edge detection + pin = 0; #22 + pin = 1; #133 + pin = 0; #231 + pin = 1; #52 + pin = 0; #100 + + //Testing debouncing when input bounces but remains zero + pin = 0; #5 + pin = 1; #5 + pin = 0; #5 + pin = 1; #5 + pin = 0; #100 + //Check that conditioned = 0 the whole time + + //Testing debouncing when input bounces and switches to one + pin = 0; #5 + pin = 1; #5 + pin = 0; #5 + pin = 1; #2 + pin = 0; #3 + pin = 1; #1 + pin = 0; #5 + pin = 1; #100; + //Check that conditioned = 0 and then switches to 1 after pin has settled + currenttime = 800; + end endmodule diff --git a/inputconditioner.v b/inputconditioner.v index 736a866..79ae2e1 100644 --- a/inputconditioner.v +++ b/inputconditioner.v @@ -22,12 +22,20 @@ output reg negativeedge // 1 clk pulse at falling edge of conditioned reg synchronizer1 = 0; always @(posedge clk ) begin + positiveedge <= 0; + negativeedge <= 0; if(conditioned == synchronizer1) counter <= 0; else begin if( counter == waittime) begin counter <= 0; conditioned <= synchronizer1; + if (synchronizer1 == 0) begin + negativeedge <= 1; + end + if (synchronizer1 == 1) begin + positiveedge <= 1; + end end else counter <= counter+1; From 90fceebc2ece33758d8c1fae15d0ad033880d0c2 Mon Sep 17 00:00:00 2001 From: Xiaozheng Xu Date: Wed, 25 Oct 2017 11:41:30 -0400 Subject: [PATCH 3/5] Stopped infinite clock with finish. Test bench is almost complete. Can test more debouncing --- inputconditioner.t.v | 13 ++++++++----- inputconditioner.v | 6 +++--- 2 files changed, 11 insertions(+), 8 deletions(-) diff --git a/inputconditioner.t.v b/inputconditioner.t.v index 64d16f5..8433dff 100644 --- a/inputconditioner.t.v +++ b/inputconditioner.t.v @@ -11,8 +11,6 @@ module testConditioner(); wire conditioned; wire rising; wire falling; - - integer currenttime = 0; inputconditioner dut(.clk(clk), .noisysignal(pin), @@ -32,7 +30,7 @@ module testConditioner(); $dumpvars(0, clk, pin, conditioned, rising, falling); //Testing Synchronization and edge detection - pin = 0; #22 + pin = 0; #150 pin = 1; #133 pin = 0; #231 pin = 1; #52 @@ -54,8 +52,13 @@ module testConditioner(); pin = 0; #3 pin = 1; #1 pin = 0; #5 - pin = 1; #100; + pin = 1; #160 //Check that conditioned = 0 and then switches to 1 after pin has settled - currenttime = 800; + + //Check delay for even clock cycle changes + pin = 0; #120 + pin = 1; #120 + pin = 0; #120 + $finish; end endmodule diff --git a/inputconditioner.v b/inputconditioner.v index 79ae2e1..d093110 100644 --- a/inputconditioner.v +++ b/inputconditioner.v @@ -29,13 +29,13 @@ output reg negativeedge // 1 clk pulse at falling edge of conditioned else begin if( counter == waittime) begin counter <= 0; - conditioned <= synchronizer1; - if (synchronizer1 == 0) begin + if (synchronizer1 == 0 && conditioned == 1) begin negativeedge <= 1; end - if (synchronizer1 == 1) begin + if (synchronizer1 == 1 && conditioned == 0) begin positiveedge <= 1; end + conditioned <= synchronizer1; end else counter <= counter+1; From 1bf49e0b3388c0e4f52a16478f3e6fac896549ea Mon Sep 17 00:00:00 2001 From: Xiaozheng Xu Date: Wed, 25 Oct 2017 19:47:56 -0400 Subject: [PATCH 4/5] Adding seemingly working shift register and midpoint --- midpoint.v | 56 +++++++++++++++++++++++++++++++++++++++++++++++ shiftregister.t.v | 36 +++++++++++++++++++++++++++--- shiftregister.v | 12 +++++++++- 3 files changed, 100 insertions(+), 4 deletions(-) create mode 100644 midpoint.v diff --git a/midpoint.v b/midpoint.v new file mode 100644 index 0000000..351e10a --- /dev/null +++ b/midpoint.v @@ -0,0 +1,56 @@ +//------------------------------------------------------------------------ +// Midpoint module +//------------------------------------------------------------------------ +`include "shiftregister.v" +`include "inputconditioner.v" + +module Midpoint( + input [1:0] sw, + input btn, + output [3:0] led + ); + reg clk; + wire peripheralClkEdge; + wire parallelLoad; + wire[7:0] parallelDataOut; + wire serialDataOut; + wire[7:0] parallelDataIn; + + reg pin; + wire conditioned; + wire rising; + wire falling; + + assign parallelDataIn = 8'b10011001; + // Instantiate with parameter width = 8 + shiftregister #(8) sr1(.clk(clk), + .peripheralClkEdge(peripheralClkEdge), + .parallelLoad(parallelLoad), + .parallelDataIn(parallelDataIn), + .serialDataIn(serialDataIn), + .parallelDataOut(parallelDataOut), + .serialDataOut(serialDataOut)); + + inputconditioner ICParallelLoad(.clk(clk), + .noisysignal(btn), + .conditioned(), + .positiveedge(), + .negativeedge(parallelLoad)); + + inputconditioner ICSerialIn(.clk(clk), + .noisysignal(sw[0]), + .conditioned(serialDataIn), + .positiveedge(), + .negativeedge()); + + inputconditioner ICPerfClock(.clk(clk), + .noisysignal(sw[1]), + .conditioned(), + .positiveedge(peripheralClkEdge), + .negativeedge()); + + // Generate clock (50MHz) + initial clk = 0; + always #10 clk=!clk; // 50MHz Clock + +endmodule \ No newline at end of file diff --git a/shiftregister.t.v b/shiftregister.t.v index abe5b48..5bdce3d 100644 --- a/shiftregister.t.v +++ b/shiftregister.t.v @@ -1,7 +1,7 @@ //------------------------------------------------------------------------ // Shift Register test bench //------------------------------------------------------------------------ - +`include "shiftregister.v" module testshiftregister(); reg clk; @@ -20,9 +20,39 @@ module testshiftregister(); .serialDataIn(serialDataIn), .parallelDataOut(parallelDataOut), .serialDataOut(serialDataOut)); - + + initial clk = 0; + always #10 clk=!clk; // 50MHz Clock + initial begin - // Your Test Code + $dumpfile("shiftregister.vcd"); + $dumpvars(0, clk, peripheralClkEdge, parallelLoad, parallelDataOut, serialDataOut, parallelDataIn, serialDataIn); + + peripheralClkEdge = 0; + parallelLoad = 1; + parallelDataIn = 8'b10011101; #50 + $display("parallelDataOut after loading b10011101: %b", parallelDataOut); + + parallelLoad = 0; + serialDataIn = 0; #100 + $display("parallelDataOut shouldn't change: %b", parallelDataOut); + + $display("serialdata out before shifting: %b", serialDataOut); + peripheralClkEdge = 1; + parallelLoad = 0; + serialDataIn = 0; #20 + $display("parallelDataOut after shifting in 0: %b", parallelDataOut); + $display("serialdata out after shifting: %b", serialDataOut); + + serialDataIn = 1; #20 + $display("parallelDataOut after shifting in 1: %b", parallelDataOut); + $display("serialdata out after shifting: %b", serialDataOut); + + serialDataIn = 1; #20 + $display("parallelDataOut after shifting in 1: %b", parallelDataOut); + $display("serialdata out after shifting: %b", serialDataOut); + + $finish; end endmodule diff --git a/shiftregister.v b/shiftregister.v index b4ec057..23055d4 100644 --- a/shiftregister.v +++ b/shiftregister.v @@ -19,7 +19,17 @@ output serialDataOut // Positive edge synchronized ); reg [width-1:0] shiftregistermem; + + assign parallelDataOut = shiftregistermem; + assign serialDataOut = shiftregistermem[width-1]; + always @(posedge clk) begin - // Your Code Here + if (parallelLoad) begin + shiftregistermem <= parallelDataIn; + end + else if (peripheralClkEdge) begin + shiftregistermem[width-1:1] <= shiftregistermem[width-2:0]; + shiftregistermem[0] <= serialDataIn; + end end endmodule From 6c443171d69c99e60a91055f10d9d720d0c01f4d Mon Sep 17 00:00:00 2001 From: Xiaozheng Xu Date: Wed, 25 Oct 2017 21:22:52 -0400 Subject: [PATCH 5/5] working midpoint on FPGA, modified input conditioner --- inputconditioner.t.v | 2 +- inputconditioner.v | 6 +++-- midpoint.v | 61 ++++++++++++++++++++++++++++++++++---------- 3 files changed, 52 insertions(+), 17 deletions(-) diff --git a/inputconditioner.t.v b/inputconditioner.t.v index 8433dff..5e703c3 100644 --- a/inputconditioner.t.v +++ b/inputconditioner.t.v @@ -27,7 +27,7 @@ module testConditioner(); // Be sure to test each of the three conditioner functions: // Synchronization, Debouncing, Edge Detection $dumpfile("inputconditioner.vcd"); - $dumpvars(0, clk, pin, conditioned, rising, falling); + $dumpvars(); //Testing Synchronization and edge detection pin = 0; #150 diff --git a/inputconditioner.v b/inputconditioner.v index d093110..22f8208 100644 --- a/inputconditioner.v +++ b/inputconditioner.v @@ -22,8 +22,6 @@ output reg negativeedge // 1 clk pulse at falling edge of conditioned reg synchronizer1 = 0; always @(posedge clk ) begin - positiveedge <= 0; - negativeedge <= 0; if(conditioned == synchronizer1) counter <= 0; else begin @@ -35,6 +33,10 @@ output reg negativeedge // 1 clk pulse at falling edge of conditioned if (synchronizer1 == 1 && conditioned == 0) begin positiveedge <= 1; end + else begin + negativeedge <= 0; + positiveedge <= 0; + end conditioned <= synchronizer1; end else diff --git a/midpoint.v b/midpoint.v index 351e10a..45658b5 100644 --- a/midpoint.v +++ b/midpoint.v @@ -1,26 +1,56 @@ //------------------------------------------------------------------------ // Midpoint module //------------------------------------------------------------------------ -`include "shiftregister.v" -`include "inputconditioner.v" + +// JK flip-flop +module jkff1 +( + input trigger, + input j, + input k, + output reg q +); + always @(posedge trigger) begin + if(j && ~k) begin + q <= 1'b1; + end + else if(k && ~j) begin + q <= 1'b0; + end + else if(k && j) begin + q <= ~q; + end + end +endmodule + +// Two-input MUX with parameterized bit width (default: 1-bit) +module mux2 #( parameter W = 1 ) +( + input[W-1:0] in0, + input[W-1:0] in1, + input sel, + output[W-1:0] out +); + // Conditional operator - http://www.verilog.renerta.com/source/vrg00010.htm + assign out = (sel) ? in1 : in0; +endmodule + module Midpoint( + input clk, input [1:0] sw, - input btn, + input[3:0] btn, output [3:0] led ); - reg clk; wire peripheralClkEdge; wire parallelLoad; + wire serialDataIn; wire[7:0] parallelDataOut; wire serialDataOut; wire[7:0] parallelDataIn; + wire[3:0] res0, res1; + wire res_sel; - reg pin; - wire conditioned; - wire rising; - wire falling; - assign parallelDataIn = 8'b10011001; // Instantiate with parameter width = 8 shiftregister #(8) sr1(.clk(clk), @@ -32,7 +62,7 @@ module Midpoint( .serialDataOut(serialDataOut)); inputconditioner ICParallelLoad(.clk(clk), - .noisysignal(btn), + .noisysignal(btn[0]), .conditioned(), .positiveedge(), .negativeedge(parallelLoad)); @@ -49,8 +79,11 @@ module Midpoint( .positiveedge(peripheralClkEdge), .negativeedge()); - // Generate clock (50MHz) - initial clk = 0; - always #10 clk=!clk; // 50MHz Clock + assign res0 = parallelDataOut[3:0]; + assign res1 = parallelDataOut[7:4]; + + // Capture button input to switch which MUX input to LEDs + jkff1 src_sel(.trigger(clk), .j(btn[3]), .k(btn[2]), .q(res_sel)); + mux2 #(4) output_select(.in0(res0), .in1(res1), .sel(res_sel), .out(led)); -endmodule \ No newline at end of file +endmodule